Certain aspects of the present disclosure generally relate to a hybrid back-end-of-line (BEOL) dielectric for a high capacitance density metal-oxide-metal (MOM) capacitor, especially in lower BEOL layers. One example semiconductor device includes an active layer and a first metal layer disposed above the active layer. The first metal layer generally includes: a first electrode; a second electrode, wherein the first and second electrodes have interdigitated fingers; a first dielectric material disposed at least partially between at least two adjacent fingers of the first and second electrodes; and a second dielectric material, wherein the second dielectric material is different from the first dielectric material and wherein the first electrode, the second electrode, and the first dielectric material compose a portion of a metal-oxide-metal (MOM) capacitor.

BACKGROUND

Field of the Disclosure

Certain aspects of the present disclosure generally relate to semiconductor devices and, more particularly, to a hybrid back-end-of-line (BEOL) dielectric for a high capacitance density metal-oxide-metal (MOM) capacitor, especially in lower BEOL layers.

Description of Related Art

A continued emphasis in semiconductor technology is to create improved performance semiconductor devices at competitive prices. This emphasis over the years has resulted in extreme miniaturization of semiconductor devices, made possible by continued advances in semiconductor processes and materials in combination with new and sophisticated device designs. Large numbers of transistors are employed in integrated circuits (ICs) in many electronic devices. For example, components such as central processing units (CPUs), graphics processing units (GPUs), and memory systems each employ a large quantity of transistors for logic circuits and memory devices. The ICs may include various layers of conductors (e.g., metal layers) disposed between layers of dielectric material, which are formed during a back-end-of-line (BEOL) fabrication process. The conductors facilitate electrical wiring between various electrical components including transistors, amplifiers, inverters, control logic, memory, power management circuits, buffers, filters, resonators, capacitors, inductors, resistors, etc. The conductors may also be used to create certain structures, such as metal-oxide-metal (MOM) capacitors.

SUMMARY

Certain aspects of the present disclosure provide a semiconductor device. The semiconductor device includes an active layer and a first metal layer disposed above the active layer. The first metal layer generally includes a first electrode; a second electrode, wherein the first and second electrodes have interdigitated fingers; a first dielectric material disposed at least partially between at least two adjacent fingers of the first and second electrodes; and a second dielectric material, wherein the second dielectric material is different from the first dielectric material and wherein the first electrode, the second electrode, and the first dielectric material compose a portion of a metal-oxide-metal (MOM) capacitor.

Certain aspects of the present disclosure provide a method for fabricating a semiconductor device. The method generally forming an active layer and forming a first metal layer above the active layer. The first metal layer generally includes a first electrode; a second electrode, wherein the first and second electrodes have interdigitated fingers; a first dielectric material disposed at least partially between at least two adjacent fingers of the first and second electrodes; and a second dielectric material, wherein: the second dielectric material is different from the first dielectric material; and the first electrode, the second electrode, and the first dielectric material compose a portion of a metal-oxide-metal (MOM) capacitor.

DETAILED DESCRIPTION

Certain aspects of the present disclosure generally relate to a hybrid back-end-of-line (BEOL) dielectric for a high capacitance density metal-oxide-metal (MOM) capacitor, especially in lower BEOL layers of a semiconductor device, and methods for fabricating the same. With one dielectric material disposed in-between the metal fingers of a MOM capacitor and a different dielectric material disposed in-between the metal routing lines on the same metal layer and in the dielectric layers, the capacitance and capacitance density of a MOM capacitor may be increased, without increasing regular routing parasitic capacitance.

Example Semiconductor Device

FIG. 1is a cross-sectional view of an example semiconductor device100, in which certain aspects of the present disclosure may be practiced. As shown, the semiconductor device100may include a substrate102, a dielectric region104, an active electrical device106(e.g., a transistor), dielectric layers108, local conductive interconnects110(e.g., source-drain conductive contacts, which are often abbreviated as CA), first conductive vias112, and a first layer of conductive traces114(e.g., metal layer one M1). In certain aspects, the semiconductor device100may include additional layers of conductive vias116(e.g., via layer one V1and via layer two V2), additional layers of conductive traces118(e.g., metal layer two M2and metal layer three M3), under-bump conductive pads120, and solder bumps124.

The substrate102may be, for example, a portion of a semiconductor wafer, such as a silicon wafer. The dielectric region104may be disposed above the substrate102. The dielectric region104may comprise an oxide, such as silicon dioxide (SiO2). In aspects, the dielectric region104may be a shallow trench isolation (STI) region configured to electrically isolate the active electrical device106from other electrical components, such as other electrical devices.

The active electrical device106may be disposed above the substrate102. In this example, the active electrical device106may include one or more transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs). In aspects, the MOSFETs may include fin field-effect transistors (finFETs) and/or gate-all-around (GAA) FETs. In certain aspects, the active electrical device106may be an inverter, amplifier, and/or other suitable electrical devices comprising transistors. The local conductive interconnects110may be electrically coupled to the active electrical device106. For example, the source and/or drain of the active electrical device106may be electrically coupled to the local conductive interconnects110, which are electrically coupled to the first conductive vias112. In certain aspects, the active electrical device106(and the local interconnects110) may be formed during a front-end-of-line (FEOL) fabrication process.

The first conductive via112, additional conductive vias116, and layers of conductive traces114,118may be disposed above electrical components (e.g., the active electrical device106) and formed during a back-end-of-line (BEOL) fabrication process of the semiconductor device100. In aspects, the first conductive via112, additional conductive vias116, and layers of conductive traces114,118may be embedded in the dielectric layers108. The dielectric layers108may comprise an oxide, such as silicon dioxide. The first conductive vias112, additional conductive vias116, and layers of conductive traces114,118provide electrical routing between the active electrical device106and other electrical components (not shown), including, for example, capacitors, inductors, resistors, an integrated passive device, a power management integrated circuit (PMIC), a memory chip, etc.

In this example, the semiconductor device100may be a flip-chip ball grid array (FC-BGA) integrated circuit having multiple solder bumps124electrically coupled to the under-bump conductive pads120. In certain cases, the semiconductor device100may have conductive pillars (e.g., copper (Cu) pillars) that electrically couple the semiconductor device100to a package substrate, an interposer, or a circuit board, for example.

In certain aspects, the first layer of conductive traces114and/or one or more of the additional layers of conductive traces118may each implement a layer of a MOM capacitor, described herein with respect toFIGS. 2 and 3A-3E. The conductive traces (e.g., in M1, M2, and M3) implementing fingers of the MOM capacitor on any one metal layer may be electrically isolated from one another by a portion of the one or more dielectric layers108disposed between the conductive traces.

Example MOM Capacitors

MOM capacitors are passive devices, which may be utilized in advanced logic or radio frequency (RF) circuits. MOM capacitors exploit the effect of lateral (or intra-layer) capacitive coupling between the plates formed by standard metallization wiring lines. Lateral capacitive coupling may provide better matching characteristics than vertical coupling due to a better process control of lateral dimensions than that of metal and dielectric layer thicknesses. To increase the capacitive density (capacitance per unit area of silicon chip), several metal layers are connected in parallel by vias, forming a vertical metal wall or mesh. Normally, the lowest metal layers with minimum metal line width and spacing are used for MOMs to maximize the capacitance density.

FIG. 2depicts an example metal-oxide-metal (MOM) capacitor10, in which certain aspects of the present disclosure may be practiced. The MOM capacitor10has an interdigitated double patterning structure with metal fingers interdigitated. The existence of these fingers causes the MOM capacitor10to also be referred to as a finger metal-oxide-metal capacitor (FMOM). As used herein, the term “finger” refers to the generally rectilinear element of a node that is interdigitated with other similar generally rectilinear elements. The MOM capacitor10is formed from two nodes. The first node of the MOM capacitor10is a first conductive element12(formed from elements12A,12B, and12C). The second node of the MOM capacitor10is a second conductive element14(formed from elements14A,14B, and14C). The various elements12A,12B, and12C of first conductive element12are electrically coupled to one another with vias16. Similarly, the various elements14A,14B, and14C of second conductive element14are electrically coupled to one another with vias18. Each of the elements12A,12B, and12C includes a first set of metal fingers20A. Similarly, each of the elements14A,14B, and14C includes a second set of metal fingers20B, which, as shown, are interdigitated with the metal fingers20A of the elements12A,12B, and12C.

As illustrated inFIG. 2, the elements12A,12B, and12C are vertically stacked relative to one another. The elements12A,12B, and12C are also designed to be directly disposed over one another so that the vias16are aligned. The elements12A and14A are disposed in a first metal layer, the elements12B and14B are disposed in a second metal layer arranged below the first metal layer, and the elements12C and14C are disposed in a third metal layer arranged below the second metal layer. It should be appreciated that the layers in the MOM capacitor10may be rotated ninety degrees relative to adjacent layers. That is, the first metal layer with elements12A and14A may be rotated ninety degrees relative to the second metal layer with elements12B and14B, which may be rotated ninety degrees relative to the third metal layer with elements12C and14C.

FIG. 3Ais a cross-sectional view of metal layers300A for a device. The metal layers300A may represent lower BEOL layers (e.g., M1, M2, and/or M3) in a semiconductor device, for example. As illustrated, the metal layers300A may include a dielectric material302, routing metal lines304, and a MOM capacitor306.

The dielectric material302may surround the routing metal lines304and at least a portion of the MOM capacitor306. The dielectric material302may comprise any of various suitable dielectric materials, such as silicon dioxide. Additionally, the dielectric material302may have a relatively low dielectric constant (κ) (e.g., κ323.5). Having a relatively low dielectric constant may result in a relatively low capacitive density, which may be inadequate for certain applications demanding higher capacitive density, as explained below.

The routing metal lines304may be arranged on either side of the MOM capacitor306. Furthermore, the routing metal lines304may be disposed within the dielectric material302and be disposed in at least one row. Each row may represent a different metal layer of the device. In certain aspects, the routing metal lines304may be composed of copper (Cu). Additionally, if the routing metal lines304are composed of Cu, the routing metal lines304may include a barrier layer. Therefore, the fabrication process for the metal layers300A may involve Cu patterning on the dielectric material302.

The MOM capacitor may include at least one row of metal lines308,310, and312, where each of the metal lines308,310, and312inFIG. 3Arepresents a cross-section of a finger of the MOM capacitor. Metal lines308and310may be disposed separated from one another with the dielectric material302filling at least a portion of the space between metal lines308and310. The same can be said of metal lines310and312. Additionally, metal lines308and312may be coupled to one electrode, while metal line310is coupled to another electrode different than the electrode coupled to metal lines308and312. In this manner, a capacitance may be generated between metal lines308and310, and a capacitance may be generated between metal lines310and312.

Although only two rows of metal lines (e.g., two metal layers) are illustrated inFIG. 3A, it is to be understood that a device may include more than two metal layers. Furthermore, although the MOM capacitor306is illustrated as having one electrode with two fingers and another electrode with one finger, it is to be understood that a MOM capacitor may have any number of fingers for each electrode.

Example MOM Capacitors with Hybrid Dielectrics

In advanced complementary metal-oxide-semiconductor (CMOS) technologies, for example, dielectric materials in lower back-end-of-line (BEOL) layers may commonly have low, or even extremely low, dielectric constants. As a consequence, a metal-oxide-metal (MOM) capacitor occupying one or more lower metal layer may have a low capacitive density, which may not be suitable for certain applications demanding higher capacitive density from such MOM capacitors.

Accordingly, certain aspects of the present disclosure provide a MOM capacitor with a hybrid dielectric for relatively higher capacitance density. Furthermore, for certain aspects, stable metals such as cobalt (Co) or ruthenium (Ru), which do not involve using a barrier layer, may be used to implement at least the lower BEOL metal layers.

FIG. 3Bis a cross-sectional view of metal layers300B for a device, in accordance with certain aspects of the present disclosure. The metal layers300A may represent lower BEOL layers (e.g., M1, M2, and/or M3) in a semiconductor device, for example. When compared with reference toFIG. 3A, metal layers300B may be somewhat similar in construction. However, metal layers300B may include metal lines314, which may be composed of cobalt (Co), ruthenium (Ru), or the like, as opposed to copper (Cu). Similarly, the MOM capacitor306may include at least one row of metal lines316,318, and320, where each of the metal lines316,318, and320inFIG. 3Brepresents a cross-section of a finger of the MOM capacitor. By implementing the metal lines314and the metal lines316,318, and320with Co or Ru instead of Cu, a barrier layer need not be used.

Furthermore, using Co, Ru, or any other metal not needing a barrier layer for the metal lines314and the metal lines316,318, and320may enable implementing a combination of different dielectric materials (referred to herein as a “hybrid dielectric”) in the same metal layer. As shown, a dielectric material322may be disposed between the metal lines316,318, and320of the MOM capacitor306within each row (e.g., each metal layer). The dielectric material322is different from the dielectric material302. For example, the dielectric material322may be have a relatively high dielectric constant (e.g., κ=16), compared to the relatively low dielectric constant (e.g., κ=3.5) of the dielectric material302. By having a relatively high dielectric constant in comparison to the dielectric constant of the dielectric material302, the dielectric material322may provide a higher MOM capacitance without any change to the dimensions of the MOM capacitor306, thereby also offering increased capacitance density compared to the MOM capacitor ofFIG. 3A. The dielectric material302is used between the metal layers composing the MOM capacitor and also outside of the MOM capacitor (e.g., surrounding the metal lines314), such that the regular routing parasitic capacitance is not increased between the homogeneous dielectric implementation ofFIG. 3Aand the hybrid dielectric implementation ofFIG. 3B.

FIG. 3Cis a cross-sectional view of metal layers300C for a device, in accordance with certain aspects of the present disclosure. When compared with reference to metal layers300B ofFIG. 3B, metal layers300C may be similar in construction. However, the dielectric material322in the metal layers300C may not completely fill the spaces between the metal lines316,318, and320(i.e., the dielectric material322only partially fills the space between metal fingers of the MOM capacitor). For example, as illustrated inFIG. 3C, the dielectric material322may be U-shaped. The dielectric material322may have a high dielectric constant, but with this design, the effective dielectric constant for the combination of dielectric materials in the spaces between the metal lines316,318,320will be lower than having the higher κ dielectric material322completely filling these spaces, but the MOM capacitor will have a higher capacitance and an increased capacitance density compared to the MOM capacitor ofFIG. 3A. For example, the effective dielectric constant may be 2 to 3 times higher than that of the dielectric material302.

FIG. 3Dis a cross-sectional view of metal layers300D for a device, in accordance with certain aspects of the present disclosure. When compared with reference to metal layers300B ofFIG. 3B, metal layers300D may be similar in construction. However, each space between metal lines316,318, and320may have a portion of dielectric material322disposed between two portions of dielectric material302. The relative amounts of dielectric material302and dielectric material322in each space between metal lines316,318, and322may depend on the particular design (e.g., on the desired capacitance and manufacturing limitations). For example, there may be a larger portion of dielectric material302on one side of dielectric material322than on the other side of dielectric material322. In certain aspects, there may be equal portions of dielectric material302on either side of dielectric material322. With this design, the effective dielectric constant for the combination of dielectric materials in the spaces between the metal lines316,318,320will be lower than having the higher κ dielectric material322completely filling these spaces, but the MOM capacitor will have a higher capacitance and an increased capacitance density compared to the MOM capacitor ofFIG. 3A.

FIG. 3Eis a cross-sectional view of metal layers300E for a device, in accordance with certain aspects of the present disclosure. When compared with reference to metal layers300B ofFIG. 3B, metal layers300E may be similar in construction. However, each space between metal lines316,318, and320of the MOM capacitor may have a portion of dielectric material302disposed between two portions of dielectric material322. The relative amounts of dielectric material302and dielectric material322in each space between metal lines316,318, and322may depend on the particular design (e.g., on the desired capacitance and manufacturing limitations). For example, there may be a larger portion of dielectric material322on one side of dielectric material302than on the other side of dielectric material302. In certain aspects, there may be equal portions of dielectric material322on either side of dielectric material302. Furthermore, the portions of dielectric material322may not have perfectly vertical edges. For example, the portion of dielectric material302may widen from top to bottom. As another example, the portion of dielectric material302may decrease in width from top to bottom. With this design, the effective dielectric constant for the combination of dielectric materials in the spaces between the metal lines316,318,320will be lower than having the higher κ dielectric material322completely filling these spaces, but the MOM capacitor will have a higher capacitance and an increased capacitance density compared to the MOM capacitor ofFIG. 3A.

For certain aspects, the various structures of the dielectric material322and/or dielectric material302illustrated inFIGS. 3A-3Emay be combined. For example, one metal layer of the MOM capacitor may have a dielectric material322that completely fills the spaces between the metal lines316,318, and320, whereas another metal layer of the MOM capacitor may have U-shaped dielectric material. Furthermore, one metal layer of the MOM capacitor may have dielectric material302with a relatively low κ, whereas another metal layer of the MOM capacitor may have dielectric material322with a relatively high κ.

Example Fabrication Processes

FIGS. 4A-4Gillustrate example operations for fabricating metal layers for a semiconductor device, including a MOM capacitor with a hybrid dielectric, in accordance with certain aspects of the present disclosure. These operations may occur during BEOL fabrication of lower layers, for example.

FIG. 4Adepicts a cross-sectional view of a portion of a workpiece400, in accordance with certain aspects of the present disclosure. InFIG. 4A, the workpiece400may represent a lower metal layer (e.g., M1) of a semiconductor device. As shown, the workpiece400may be fabricated by forming a dielectric material302and metal lines314,316,318, and320. As depicted, the metal lines may be arranged such that a portion of the dielectric material302is between adjacent pairs of metal lines. Alternatively, there may be no dielectric material302between at least some adjacent pairs of metal lines. In certain aspects, the dielectric material302may have a relatively low dielectric constant (e.g., κ=3.5).

As shown inFIG. 4B, one or more portions of the workpiece400may be masked out (e.g., with a hard mask comprising silicon nitride). As shown, mask406and mask408may be formed above the dielectric material302. Mask406may extend along a width410of the workpiece400, which may cover routing metal lines and a metal line designated as an outer finger for a MOM capacitor. Likewise, mask408may extend along a width412of the workpiece400, which may cover routing metal lines and a metal line designated as another outer finger for the MOM capacitor.

After masking, a portion of the dielectric material302of workpiece400may be removed (e.g., etched) to create gap402and gap404. Gap402may separate metal line316and metal line318, while gap404may separate metal line318and metal line320. In certain aspects, gaps402and404may be the same size, while in other aspects, gaps402and404may be different sizes.

As portrayed inFIG. 4C, a dielectric material322with a relatively high dielectric constant (e.g., κ=16) may be deposited to fill gaps402and404of workpiece400. Furthermore, in certain aspects, the dielectric material322may undergo chemical-mechanical planarization (CMP) to remove any excess dielectric material above the height of the masks406,408.

FIG. 4Eshows another CMP being performed on the dielectric material322above the height of the metal layer414. After the CMP, the dielectric material322is generally flush with the top of metal layer414.

FIG. 4Fdepicts another layer416of dielectric material302being formed (e.g., deposited) above metal layer414and another metal layer418being formed above the dielectric layer416. Additionally, in certain aspects, similar processes as depicted inFIG. 4Amay be performed on metal layer418.

FIG. 4Gdepicts a cross-sectional view of the workpiece400after the processes depicted inFIGS. 4B-4Eare repeated on metal layer418. These operations may be repeated any desired number of times, which may depend on the number of metal layers in the MOM capacitor.

FIG. 5is a flow diagram of example operations500for fabricating a semiconductor device (e.g., the semiconductor device100depicted inFIG. 1), in accordance with certain aspects of the present disclosure. The operations500may be performed by a semiconductor fabrication facility (also known as a “fab house” or foundry), for example.

The operations500may begin at block505with the fabrication facility forming an active layer. The active layer may include transistors (e.g., planar transistors, fin field-effect transistors (finFETs), and/or gate-all-around (GAA) transistors) and/or other semiconductor components (e.g., active electrical device106).

At block510, the fabrication facility may form a first metal layer (e.g., metal layer414) above the active layer. The first metal layer may include a first electrode (e.g., element12C) and a second electrode (e.g., element14C), where the first and second electrodes have interdigitated fingers (e.g., metal fingers20A and20B). The first metal layer may also include a first dielectric material (e.g., dielectric material322) disposed at least partially between at least two adjacent fingers of the first and second electrodes and a second dielectric material (e.g., dielectric material302), which is different from the first dielectric material. The first electrode, the second electrode, and the first dielectric material compose a portion of a metal-oxide-metal (MOM) capacitor (e.g., MOM capacitor10or306).

In certain aspects, a dielectric constant of the first dielectric material (e.g., dielectric material322) is greater than a dielectric constant of the second dielectric material (e.g., dielectric material302). In certain aspects, the dielectric constant of the first dielectric material is at least three times greater than the dielectric constant of the second dielectric material.

In certain aspects, the first electrode (e.g., element12C) and/or the second electrode (e.g., element14C) comprise cobalt or ruthenium. Alternatively, the first electrode and/or the second electrode may comprise any stable metal that does not implicate the use of a barrier metal. These stable metals include tungsten, molybdenum, ruthenium, palladium, osmium, iridium, and platinum.

According to certain aspects, the first dielectric material (e.g., dielectric material322) completely fills a space (e.g., gap402) in the first metal layer (e.g., metal layer414) between the at least two adjacent fingers (e.g., metal lines316and318) of the first and second electrodes. According to other aspects, a space in the first metal layer between the at least two adjacent fingers of the first and second electrodes is occupied by the first dielectric material and the second dielectric material (e.g., as shown inFIGS. 3C-3E). In certain aspects, the space in the first metal layer between the at least two adjacent fingers of the first and second electrodes is occupied by a region comprising the first dielectric material disposed between two regions comprising the second dielectric material (e.g., as shown inFIG. 3D). In other aspects, the space in the first metal layer between the at least two adjacent fingers of the first and second electrodes is occupied by a region comprising the second dielectric material disposed between two regions comprising the first dielectric material (e.g., as illustrated inFIG. 3E). In certain aspects, the space in the first metal layer between the at least two adjacent fingers of the first and second electrodes is occupied by a U-shaped region comprising the first dielectric material and wrapped around another region comprising the second dielectric material (e.g., as depicted inFIG. 3C).

In certain aspects, the first metal layer further comprises one or more metal lines (e.g., metal lines314). In this case, the second dielectric material (e.g., dielectric material302) may be disposed between the one or more metal lines and at least one of the first electrode or the second electrode. In certain aspects, the first electrode (e.g., element12C), the second electrode (e.g., element14C), and the one or more metal lines (e.g., metal line314) comprise cobalt, ruthenium, tungsten, molybdenum, palladium, osmium, iridium, or platinum.

In certain aspects, the operations500further comprise forming a dielectric layer (e.g., dielectric layer416) above the first metal layer (e.g., metal layer414). In this case, the dielectric layer may comprise the second dielectric material (e.g., dielectric material302). In certain aspects, the operations500further comprise forming a second metal layer (e.g., metal layer418) above the dielectric layer. The second metal layer may include a third electrode (e.g., element12B) and a fourth electrode (e.g., element14B), where the third and fourth electrodes have interdigitated fingers (e.g., metal fingers20A and20B). The second metal layer may also include a third dielectric material (e.g., dielectric material322) disposed at least partially between at least two adjacent fingers of the third and fourth electrodes, where the third dielectric material is different from at least one of the first dielectric material or the second dielectric material. In this case, the MOM capacitor may include the first electrode, the second electrode, the third electrode, the fourth electrode, the first dielectric material, the third dielectric material, and at least a portion of the dielectric layer between the first and second electrodes of the first metal layer and the third and fourth electrodes of the second metal layer. In certain aspects, the first dielectric material is the same as the third dielectric material, whereas in other aspects, the first and third dielectric materials are different. In certain aspects, the third dielectric material completely fills a space in the second metal layer between the at least two adjacent fingers of the third and fourth electrodes (e.g., as shown inFIG. 4G). In other aspects, a space in the second metal layer between the at least two adjacent fingers of the third and fourth electrodes is occupied by the second dielectric material and the third dielectric material. In this case, the space in the second metal layer between the at least two adjacent fingers of the third and fourth electrodes may be occupied by a region comprising the second dielectric material disposed between two regions comprising the third dielectric material, or as an alternative, the space in the second metal layer between the at least two adjacent fingers of the third and fourth electrodes may be occupied by a region comprising the third dielectric material disposed between two regions comprising the second dielectric material. In certain aspects, the space in the second metal layer between the at least two adjacent fingers of the third and fourth electrodes is occupied by a U-shaped region comprising the third dielectric material and wrapped around another region comprising the second dielectric material.

In certain aspects, at least one of the first metal layer or the second metal layer lacks a barrier metal.

In certain aspects, at least one of the first metal layer or the second metal layer comprises cobalt, ruthenium, tungsten, molybdenum, palladium, osmium, iridium, or platinum. In this case, one or more metal layers disposed above the first metal layer and the second metal layer may comprise copper.

The apparatus and methods described in the detailed description are illustrated in the accompanying drawings by various blocks, modules, components, circuits, steps, processes, algorithms, etc. (collectively referred to as “elements”). These elements may be implemented using hardware, for example.

One or more of the components, steps, features, and/or functions illustrated herein may be rearranged and/or combined into a single component, step, feature, or function or embodied in several components, steps, or functions. Additional elements, components, steps, and/or functions may also be added without departing from features disclosed herein. The apparatus, devices, and/or components illustrated herein may be configured to perform one or more of the methods, features, or steps described herein.