SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM COMPRISING THE SAME

A semiconductor device includes a substrate comprising a chip region and a scribe lane region including a first key pattern region, a capping insulating layer disposed on the scribe lane region, a barrier metal layer covering the capping insulating layer and an inner wall of a via hole penetrating the capping insulating layer, a substrate layer disposed on the barrier metal layer and filling the via hole, an insulating plate and an upper base layer disposed on the substrate layer, a pattern insulating layer disposed on the capping insulating layer in the first key pattern region, a stacked structure disposed on the upper base layer and the pattern insulating layer, and first pattern structures overlapping the pattern insulating layer in a vertical direction and penetrating the stacked structure and the pattern insulating layer, wherein the pattern insulating layer extends through the barrier metal layer in the first key pattern region.

CROSS-REFERENCE TO RELATED APPLICATION

BACKGROUND

The inventive concept relates to a semiconductor device and an electronic system including the semiconductor device. Specifically, the inventive concept relates to a semiconductor device including a non-volatile vertical memory device and an electronic system including the semiconductor device.

In an electronic system requiring data storage, a semiconductor device capable have high-capacity data storage capabilities is required, and accordingly, a method of increasing the data storage capacity of the semiconductor device has been researched. For example, as one of the methods of increasing the data storage capacity of the semiconductor device, a semiconductor device including a vertical memory device having three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells is proposed.

SUMMARY

The inventive concept provides a semiconductor device having improved structural reliability and performance while preventing contamination of semiconductor equipment used to manufacture the semiconductor device, and an electronic system including the semiconductor device.

According to an aspect of the inventive concept, there is provided a semiconductor device including a substrate including a chip region and a scribe lane region around the chip region and including a first key pattern region, a capping insulating layer disposed on the scribe lane region, a barrier metal layer covering the capping insulating layer and an inner wall of a via hole penetrating the capping insulating layer, a substrate layer disposed on the barrier metal layer and filling the via hole, an insulating plate and an upper base layer sequentially disposed on the substrate layer, a pattern insulating layer disposed on the capping insulating layer in the first key pattern region, a stacked structure disposed on the upper base layer and the pattern insulating layer, and a plurality of first pattern structures overlapping the pattern insulating layer in a vertical direction and penetrating the stacked structure and a part of the pattern insulating layer, wherein the pattern insulating layer extends through the barrier metal layer in the first key pattern region in a vertical direction.

According to another aspect of the inventive concept, there is provided a semiconductor device including a substrate including a chip region including a memory cell region and a connection region, a capping insulating layer disposed on the chip region, a barrier metal layer covering the capping insulating layer and an inner wall of a via hole penetrating the capping insulating layer, a substrate layer disposed on the barrier metal layer and filling the via hole, a lower base layer disposed on the substrate layer in the memory cell region and an insulating plate disposed on the substrate layer in the connection region, an upper base layer disposed on the lower base layer and the insulating plate, a pattern insulating layer disposed on the capping insulating layer in a partial region of the connection region, a stacked structure disposed on the pattern insulating layer and the upper base layer, and a plurality of dummy channel structures overlapping the pattern insulating layer in a vertical direction and penetrating the stacked structure and a part of the pattern insulating layer, wherein the pattern insulating layer extends through the barrier metal layer in the connection region in a vertical direction.

According to another aspect of the inventive concept, there is provided an electronic system including a main substrate, a semiconductor device on the main substrate, and a controller electrically connected to the semiconductor device on the main substrate, wherein the semiconductor device includes a substrate including a chip region and a scribe lane region around the chip region and including a first key pattern region, a capping insulating layer disposed on the scribe lane region, a barrier metal layer covering the capping insulating layer and an inner wall of a via hole penetrating the capping insulating layer, a substrate layer disposed on the barrier metal layer and filling the via hole, an insulating plate and an upper base layer sequentially disposed on the substrate layer, a pattern insulating layer disposed on the capping insulating layer in the first key pattern region, a stacked structure disposed on the upper base layer and the pattern insulating layer, and a plurality of first pattern structures overlapping the pattern insulating layer in a vertical direction and penetrating the stacked structure and a part of the pattern insulating layer, wherein the pattern insulating layer extends through the barrier metal layer in the first key pattern region in a vertical direction.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof may not be repeated.

It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element (or using any form of the word “contact”), there are no intervening elements present at the point of contact.

FIG.1is a block diagram of a semiconductor device10according to an example embodiment.

Referring toFIG.1, the semiconductor device10may include a memory cell array20and a peripheral circuit30. The memory cell array20includes a plurality of memory cell blocks BLK1, BLK2, . . . , BLKp. Each of the plurality of memory cell blocks BLK1, BLK2, . . . , BLKp may include a plurality of memory cells. The memory cell blocks BLK1, BLK2, . . . , BLKp may be connected to the peripheral circuit30through bit lines BL, word lines WL, a string selection line SSL, and a ground selection line GSL.

The peripheral circuit30may include a row decoder32, a page buffer34, a data input/output (I/O) circuit36, control logic38, and a common source line (CSL) driver39. Although not illustrated, the peripheral circuit30may further include various circuits, such as a voltage generation circuit generating various voltages necessary for the operation of the semiconductor device10, an error correction circuit for correcting errors in data read from the memory cell array20, an input/output interface, etc.

The memory cell array20may be connected to the row decoder32through the word lines WL, the string selection lines SSL, and the ground selection lines GSL, and to the page buffer34through the bit lines BL. In the memory cell array20, each of the plurality of memory cells included in the plurality of memory cell blocks BLK1, BLK2, . . . , BLKp may be a flash memory cell. The memory cell array20may include a 3D memory cell array. The 3D memory cell array may include a plurality of NAND strings, and each of the plurality of NAND strings may include a plurality of memory cells respectively connected to a plurality of vertically stacked word lines WL.

The peripheral circuit30may receive an address ADDR, a command CMD, and a control signal CTRL from the outside of the semiconductor device10, and may transmit/receive data DATA to/from a device outside the semiconductor device10.

The row decoder32may select at least one of the plurality of memory cell blocks BLK1, BLK2, . . . , BLKp in response to the address ADDR from the outside, and may select the word line WL, the string selection line SSL, and the ground selection line GSL of the selected memory cell block. The row decoder32may transmit a voltage for performing a memory operation to the word line WL of the selected memory cell block.

The page buffer34may be connected to the memory cell array20through the bit lines BL. The page buffer34may operate as a write driver during a program operation to apply a voltage according to the data DATA to be stored in the memory cell array20to the bit line BL, and may operate as a sense amplifier during a read operation to sense the data DATA stored in the memory cell array20. The page buffer34may operate according to a control signal PCTL provided from the control logic38.

The data input/output circuit36may be connected to the page buffer34through a plurality of data lines DLs. The data input/output circuit36may receive the data DATA from a memory controller (not shown) during a program operation, and provide the program data DATA to the page buffer34based on a column address C_ADDR provided from the control logic38. During a read operation, the data input/output circuit36may provide the read data DATA stored in the page buffer34to the memory controller based on the column address C_ADDR provided from the control logic38.

The data input/output circuit36may transfer an input address or command to the control logic38or the row decoder32. The peripheral circuit30may further include an electro static discharge (ESD) circuit and a pull-up/pull-down driver.

The control logic38may receive the command CMD and the control signal CTRL from the memory controller. The control logic38may provide the row address R_ADDR to the row decoder32and the column address C_ADDR to the data input/output circuit36. The control logic38may generate various internal control signals used in the semiconductor device10in response to the control signal CTRL. For example, the control logic38may adjust voltage levels provided to the word line WL and the bit line BL when performing a memory operation, such as a program operation or an erase operation.

The common source line driver39may be connected to the memory cell array20through the common source line CSL. The common source line driver39may apply a common source voltage (e.g., a power supply voltage) or a ground voltage to the common source line CSL based on a control signal CTRL_BIAS of the control logic38.

FIG.2is an equivalent circuit diagram of a memory cell array MCA of the semiconductor device10according to example embodiments.

Referring toFIG.2, the memory cell array MCA may include a plurality of memory cell strings MCS. The memory cell array MCA may include a plurality of bit lines BL (e.g., BL1, BL2, . . . , BLm), a plurality of word lines WL (e.g., WL1, WL2, . . . , WLn−1, WLn), at least one string selection line SSL, at least one ground selection line GSL, and the common source line CSL. The plurality of memory cell strings MCS may be formed between the plurality of bit lines BL and the common source line CSL. AlthoughFIG.2illustrates a case where each of the plurality of memory cell strings MCS includes two string selection lines SSL, the inventive concept is not limited thereto. For example, each of the plurality of memory cell strings MCS may include one string selection line SSL.

Each of the plurality of memory cell strings MCS may include a string selection transistor SST, a ground selection transistor GST, and a plurality of memory cell transistors MC1, MC2, . . . , MCn−1, MCn. A drain region of the string selection transistor SST may be connected to a corresponding one of the bit lines BL, and a source region of the ground selection transistor GST may be connected to the common source line CSL. The common source line CSL may be a region where source regions of the plurality of ground selection transistors GST are connected in common.

The string selection transistor SST may be connected to the string selection line SSL, and the ground selection transistor GST may be connected to the ground selection line GSL. The plurality of memory cell transistors MC1, MC2, . . . , MCn−1, MCn may be connected to the plurality of word lines WL, respectively.

FIG.3is a plan view illustrating a partial region of a semiconductor device100according to an example embodiment.

Referring toFIG.3, the semiconductor device100may include a chip region CR and a scribe lane region SLR surrounding the chip region CR. The chip region CR may be a high-density region having a relatively high pattern density, and the scribe lane region SLR may be a low-density region having a relatively low pattern density. The chip region CR may include a cell array region of a semiconductor memory device, a peripheral circuit region including circuits configured to be electrically connected to cell arrays included in the cell array region, and a core region. In some embodiments, the chip region CR may include at least one non-volatile memory device. In some embodiments, the at least one non-volatile memory device may include a NAND flash memory, a vertical NAND memory (hereinafter referred to as ‘VNAND’), a NOR flash memory, Resistive Random Access Memory (RRAM), Phase-Change Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin Injection Spin Transfer Torque Random Access Memory (STT-RAM), or a combination thereof. The at least one non-volatile memory device may be implemented as a three-dimensional (3D) array structure. For example, the chip region CR may include the memory cell array20and the peripheral circuit30included in the semiconductor device10described with reference toFIG.1. In some embodiments, the at least one non-volatile memory device may further include a volatile memory device such as dynamic random access memory (DRAM).

The scribe lane region SLR is a part of the scribe lane region of a wafer (not shown) which remains around the chip region CR after the individualization process of the chip region CR. In an embodiment, the scribe lane region SLR may include a first key pattern region KPB and a second key pattern region KPS. On the scribe lane region SLR, the first key pattern region KPB and the second key pattern region KPS may be arranged around the edge corners of the chip region CR. For example, on the scribe lane region SLR, the first key pattern region KPB may be disposed outside both vertices of the chip region CR facing each other in an oblique direction, and the second key pattern region KPS may be disposed outside the other both vertices of the chip region CR. However, the inventive concept is not limited thereto, and the first key pattern region KPB and the second key pattern region KPS may be arranged in other ways as desired. Various keys, such as an alignment key, an overlay key, and a focus key, may be disposed in the first key pattern region KPB and the second key pattern region KPS. In addition, the same type of keys or different types of keys may be arranged in the first key pattern region KPB and the second key pattern region KPS. The first key pattern region KPB and the second key pattern region KPS are described below in detail with reference toFIGS.5A to6B.

FIG.4is a cross-sectional view of a semiconductor device100according to an example embodiment. Specifically,FIG.4is a cross-sectional view illustrating a part of the chip region (e.g., chip region CR ofFIG.3) of the semiconductor device100.

Referring toFIG.4, the semiconductor device100may include a cell array structure CS and a peripheral circuit structure PS overlapping each other in a vertical direction (Z direction).

The cell array structure CS may include a memory cell region MEC in which the memory cell array20described with reference toFIG.1is disposed and a connection region CON disposed on one side of the memory cell region MEC in a first horizontal direction (X direction).

The peripheral circuit structure PS may include a substrate50, peripheral circuit transistors60TR disposed on the substrate50, and a peripheral circuit wiring structure70. The first horizontal direction (X direction) and a second horizontal direction (Y direction) may be directions that are parallel to an upper surface of the substrate50and perpendicular to one another. The vertical direction (Z direction) may be a direction that is perpendicular to the upper surface of the substrate50.

The substrate50may be a semiconductor substrate. For example, the substrate50may include Si, Ge, or SiGe. An active region AC may be defined by a device isolation layer52in the substrate50, and the plurality of peripheral circuit transistors60TR may be formed on the active region AC. The plurality of peripheral circuit transistors60TR may include a peripheral circuit gate60G and source/drain regions62disposed on parts of the substrate50of both sides of the peripheral circuit gate60G. The plurality of peripheral circuit transistors60TR may comprise the peripheral circuit30described with reference toFIG.1.

A plurality of peripheral circuit wiring structures70may include a plurality of peripheral circuit contacts72and a plurality of peripheral circuit wiring layers74. At least some of the plurality of peripheral circuit wiring layers74may be configured to be electrically connectable to the peripheral circuit transistor60TR. The plurality of peripheral circuit contacts72may be configured to interconnect some selected from among the plurality of peripheral circuit transistors60TR to the plurality of peripheral circuit wiring layers74. The plurality of peripheral circuit transistors60TR and the plurality of peripheral circuit wiring structures70included in the peripheral circuit structure PS may be covered by an interlayer insulating layer80. The interlayer insulating layer80may include a silicon oxide layer, a silicon nitride layer, a SiON layer, a SiOCN layer, or a combination thereof.

A capping insulating layer110may be disposed on the interlayer insulating layer80. The capping insulating layer110may include a first capping insulating layer111and a second capping insulating layer113sequentially disposed on the interlayer insulating layer80. The first capping insulating layer111may include, for example, silicon nitride, and the second capping insulating layer113may include, for example, silicon oxide.

The capping insulating layer110may have a via hole BVH. The via hole BVH may extend through the capping insulating layer110in a vertical direction (Z direction). Specifically, the via hole BVH may extend from the upper surface of the second capping insulating layer113to the lower surface of the first capping insulating layer111. A part of the peripheral circuit wiring layer74may be exposed by the via hole BVH.

A barrier metal layer BML may cover the upper surface of the capping insulating layer110and the inner wall of the via hole BVH. In an embodiment, the barrier metal layer BML may conformally cover the upper surface of the capping insulating layer110and the inner wall of the via hole BVH. For example, the barrier metal layer BML may contact the upper surface of the capping insulating layer110and the inner wall of the via hole BVH. The barrier metal layer BML may include a first barrier metal layer BM covering the upper surface of the capping insulating layer110and a second barrier metal layer VBM covering the inner wall of the via hole BVH. In an embodiment, the first barrier metal layer BM and the second barrier metal layer VBM may include a metal nitride or a metal silicide. For example, the first barrier metal layer BM and the second barrier metal layer VBM may include TIN, Ti—Si—N(TSN), WN, or WSi. The first barrier metal layer BM and the second barrier metal layer VBM are named for convenience of explanation, and may be formed together. Accordingly, the first barrier metal layer BM and the second barrier metal layer VBM may be integrated.

A substrate layer120may be disposed on the barrier metal layer BML. The substrate layer120may contact an upper surface of the barrier metal layer BML. The substrate layer120may function as a source region supplying current to vertical memory cells formed in the cell array structure CS. In an embodiment, the substrate layer120may include a semiconductor material, such as polysilicon. A part of the substrate layer120may form a via BV by filling an empty space inside the second barrier metal layer VBM covering the inner wall of the via hole BVH. For example, the substrate layer120may be formed together with the via BV, and may be integrated. The peripheral circuit wiring structure70and the substrate layer120may be electrically connected to each other through the via BV.

A lower base layer131may be disposed on the substrate layer120in the memory cell region MEC. The lower base layer131may contact the substrate layer120. The lower base layer131may include, for example, polysilicon doped with impurities, polysilicon undoped with impurities, metal, or a combination thereof. The lower base layer131may function as a source region supplying current to vertical memory cells formed in the cell array structure CS together with the substrate layer120.

An insulating plate133may be disposed on the substrate layer120in the connection region CON. The insulating plate133may contact the substrate layer120. In an embodiment, the insulating plate133may be an insulating material layer having an Oxide-Nitride-Oxide (ONO) structure. For example, the insulating plate133may include a plurality of insulating layers sequentially stacked on the substrate layer120.

An upper base layer140may be disposed on the lower base layer131and the insulating plate133. The upper base layer140may contact the lower base layer131and the insulating plate133. The upper base layer140may include a semiconductor material. For example, the upper base layer140may include polysilicon doped with impurities, polysilicon undoped with impurities, metal, or a combination thereof. The upper base layer140may function as a source region supplying current to vertical memory cells formed in the cell array structure CS together with the substrate layer120and the lower base layer131.

A stacked structure150may be disposed on the upper base layer140. The stacked structure150may include a plurality of insulating layers151and a plurality of gate electrodes153alternately disposed in a vertical direction (Z direction). The plurality of insulating layers151may include, for example, silicon oxide, silicon nitride, or silicon oxynitride. The plurality of gate electrodes153may include, for example, tungsten, nickel, cobalt, tantalum, tungsten nitride, titanium nitride, tantalum nitride, or a combination thereof. The plurality of gate electrodes153may correspond to the ground selection line GSL, the word lines WL, and at least one string selection line SSL constituting the memory cell string MCS (seeFIG.2). For example, inFIG.4, the uppermost gate electrode153may function as the ground selection line GSL, the lowermost two gate electrodes153inFIG.4may function as the string selection lines SSL, and the remaining gate electrodes153may function as the word lines WL.

The stacked structure150may extend to have a length decreasing in the first horizontal direction (X direction) away from the substrate layer120on the connection region CON. That is, the stacked structure150may have a stepped structure.

The stacked structure150may be covered by an interlayer insulating layer CL. The interlayer insulating layer CL may contact upper and side surfaces of the plurality of insulating layers151and the plurality of gate electrodes153. The interlayer insulating layer CL may include a silicon oxide layer, a silicon nitride layer, or a combination thereof.

A plurality of channel structures160may be disposed in the memory cell region MEC. Each of the plurality of channel structures160may penetrate the stacked structure150, the upper base layer140, the lower base layer131, and at least a part of the substrate layer120and extend in the vertical direction (Z direction). Accordingly, lower surfaces of the plurality of channel structures160may be in contact with the substrate layer120. For example, lower surfaces of the plurality of channel structures160may be at a lower vertical level than an upper surface of the substrate layer120. The plurality of channel structures160may be arranged to be spaced apart from each other with a certain space therebetween in the first horizontal direction (X direction) and the second horizontal direction (Y direction).

Each of the plurality of channel structures160may include a gate insulating layer161, a channel layer163, a filling insulating layer165, and a conductive plug167. The gate insulating layer161and the channel layer163may be sequentially disposed on the sidewall of a channel hole160H. For example, the gate insulating layer161may be conformally disposed on the sidewall of the channel hole160H, and the channel layer163may be conformally disposed on the sidewall and bottom surface of the channel hole160H. A filling insulating layer165may fill an internal space of the channel layer163. In an embodiment, the filling insulating layer165may be omitted, and in this case, the channel layer163may have a pillar structure without an internal space. A conductive plug167may be disposed on the upper side of the channel hole160H to contact the channel layer163and block an entrance of the channel hole160H.

A plurality of dummy channel structures160D may be disposed in the connection region CON. The plurality of dummy channel structures160D may not be electrically connected to the bit lines BL. The plurality of dummy channel structures160D may penetrate the interlayer insulating layer CL, the stacked structure150, the upper base layer140, the insulating plate133, and at least a part of the substrate layer120and extend in the vertical direction (Z direction). The plurality of dummy channel structures160D may be formed in a dummy channel hole160DH. Similar to the channel structure160, each of the plurality of dummy channel structures160D may include a gate insulating layer161D, a channel layer163D, a filling insulating layer165D, and a conductive plug167D. The gate insulating layer161D, the channel layer163D, the filling insulating layer165D, and the conductive plug167D of the dummy channel structures160D may be formed of the same materials as the gate insulating layer161, the channel layer163, the filling insulating layer165, and the conductive plug167, respectively, of the channel structures160. In an embodiment, the horizontal area and vertical length of each of the plurality of dummy channel structures160D may be greater than the horizontal area and vertical length of each of the plurality of channel structures160.

A first upper insulating layer UL1and a second upper insulating layer UL2may be sequentially disposed on the stacked structure150and the interlayer insulating layer CL. The first upper insulating layer UL1and the second upper insulating layer UL2may include silicon oxide, silicon nitride, or a combination thereof.

A plurality of bit line contacts BLC may contact the conductive plug167of the channel structure160and the conductive plug167D of the dummy channel structure160D through the first upper insulating layer UL1. A bit line BL may be disposed on a bit line contact BLC contacting the conductive plug167of the channel structure160among the plurality of bit line contacts BLC. The bit line BL may not be disposed on a bit line contact BLC contacting the conductive plug167D of the dummy channel structure160D among the plurality of bit line contacts BLC. The plurality of bit lines BL may penetrate the second upper insulating layer UL2and contact the bit line contacts BLC respectively corresponding thereto. The plurality of bit lines BL may be connected to the channel structures160corresponding thereto through the plurality of bit line contacts BLC corresponding thereto.

Each of a plurality of contact structures CNT may be disposed in the connection region CON. Each of the plurality of contact structures CNT may penetrate the first upper insulating layer UL1, the interlayer insulating layer CL, and a part of the gate electrode153and extend in the vertical direction (Z direction). The plurality of contact structures CNT may penetrate the first upper insulating layer UL1and connect a plurality of wiring layers ML in contact with the plurality of contact structures CNT to the plurality of gate electrodes153.

FIG.5Ais a plan view illustrating the first key pattern region KPB of the semiconductor device100according to an example embodiment.FIG.5Bis a cross-sectional view taken along a line A-A′ ofFIG.5A.

Referring toFIGS.5A and5B, the semiconductor device100may include the first key pattern region KPB positioned on the scribe lane region SLR. In an embodiment, a plurality of first pattern structures170B may be disposed in the first key pattern region KPB. In an embodiment, the horizontal area and vertical length of each of the plurality of first pattern structures170B may be greater than the horizontal area and vertical length of each of a plurality of second pattern structures170S, as described below with reference toFIGS.6A and6B. Each of the plurality of first pattern structures170B may have a rectangular shape on a plane (X-Y plane) perpendicular to the vertical direction (Z direction). In an embodiment, the plurality of first pattern structures170B may be arranged to form a cross shape. However, the inventive concept is not limited thereto, and the plurality of first pattern structures170B may be arranged in other ways as desired. In an embodiment, a pattern insulating layer115may be disposed in a region of the first key pattern region KPB where the plurality of first pattern structures170B are disposed. For example, as shown inFIG.5A, the pattern insulating layer115may be disposed in a region of the first key pattern region KPB where the plurality of first pattern structures170B are disposed, and the substrate layer120may surround the pattern insulating layer115.

The semiconductor device100may include the substrate50, the peripheral circuit wiring structure70disposed on the substrate50, and the interlayer insulating layer80disposed on the substrate50and covering the peripheral circuit wiring structure70in the first key pattern region KPB. The substrate50, the peripheral circuit wiring structure70, and the interlayer insulating layer80ofFIG.5Bmay respectively correspond to the substrate50, the peripheral circuit wiring structure70, and the interlayer insulating layer80ofFIG.4.

A capping insulating layer110may be disposed on the interlayer insulating layer80in the first key pattern region KPB. The capping insulating layer110may include a first capping insulating layer111and a second capping insulating layer113sequentially disposed on the interlayer insulating layer80. The second barrier metal layer VBM and the via BV may be disposed on the capping insulating layer110to sequentially cover the inner wall of a via hole. The capping insulating layer110, the via BV, and the second barrier metal layer VBM ofFIG.5Bmay respectively correspond to the capping insulating layer110, the via BV, and the second barrier metal layer VBM ofFIG.4.

The pattern insulating layer115and the first barrier metal layer BM may be disposed on the capping insulating layer110. The substrate layer120, the insulating plate133, and the upper base layer140may be sequentially disposed on the first barrier metal layer BM. The pattern insulating layer115may be formed by etching the sequentially disposed first barrier metal layer BM, the substrate layer120, the insulating plate133, and the upper base layer140, and filling with an insulating material layer. Accordingly, the pattern insulating layer115may extend through the first barrier metal layer BM in the vertical direction (Z direction). For example, the first barrier metal layer BM may be removed from a region where the pattern insulating layer115is disposed. In an embodiment, the upper surface of the pattern insulating layer115may be positioned at the same vertical level as the lower surface of the lowermost insulating layer among the plurality of insulating layers151(i.e., the same vertical level as the upper surface of the upper base layer140). In an embodiment, the pattern insulating layer115may contact an upper surface of the second capping insulating layer113. In an embodiment, the lower surface of the pattern insulating layer115may be positioned at the same vertical level as the upper surface of the second capping insulating layer113. In another embodiment, the lower surface of the pattern insulating layer115may be positioned at a lower vertical level than the upper surface of the second capping insulating layer113. For example, the pattern insulating layer115may extend through the second capping insulating layer113in the vertical direction (Z direction). In an embodiment, the pattern insulating layer115may be silicon oxide.

In an embodiment, the pattern insulating layer115may include the same material as the second capping insulating layer113. For example, the pattern insulating layer115and the second capping insulating layer113may include silicon oxide.

The stacked structure150may be disposed on the pattern insulating layer115and the upper base layer140. The stacked structure150may include the plurality of insulating layers151and the plurality of gate electrodes153alternately disposed in the vertical direction (Z direction). The stacked structure150ofFIG.5Bmay correspond to the stacked structure150ofFIG.4.

Each of the plurality of first pattern structures170B may be disposed on the first key pattern region KPB of the scribe lane region SLR. In an embodiment, the plurality of first pattern structures170B may be disposed to overlap the pattern insulating layer115in a vertical direction. Each of the plurality of first pattern structures170B may penetrate the stacked structure150and at least a part of the pattern insulating layer115and extend in the vertical direction (Z direction). Side surfaces of the plurality of first pattern structures170B may be discontinuous in the vertical direction (Z direction). For example, at a middle portion of the first pattern structures170B, a portion of the side surface may be parallel to an upper surface of the substrate50, and at upper and lower portions of the first pattern structures170B, portions of the surface may be at an acute angle to the upper surface of the substrate50.

Each of the plurality of first pattern structures170B may include a first barrier layer171B and a first metal layer173B. The first barrier layer171B and the first metal layer173B may be sequentially disposed on the inner wall of a first pattern channel hole170BH. The first barrier layer171B may contact side surfaces of the plurality of insulating layers151and the plurality of gate electrodes153, and the first metal layer173B may contact the first barrier layer171B. The first metal layer173B may be spaced apart from the plurality of insulating layers151and the plurality of gate electrodes153by the first barrier layer171B. For example, the first barrier layer171B and the first metal layer173B may be sequentially and conformally disposed on the sidewall and bottom surface of the first pattern channel hole170BH. In an embodiment, the first barrier layer171B may include TIN, Ti—Si—N(TSN), WN, or WSi. In an embodiment, the first barrier layer171B may include TIN, Ti—Si—N(TSN), and a combination thereof. For example, the first barrier layer171B may be formed of TIN, Ti—Si—N(TSN), and a combination thereof. In an embodiment, the first metal layer173B may include tungsten, nickel, cobalt, tantalum, tungsten nitride, titanium nitride, tantalum nitride, or a combination thereof. For example, the first metal layer173B may be formed of tungsten, nickel, cobalt, tantalum, tungsten nitride, titanium nitride, tantalum nitride, or a combination thereof.

InFIG.5B, each of the plurality of first pattern structures170B is illustrated as having the same length in the vertical direction (length in the Z direction), but is not limited thereto. For example, some of the plurality of first pattern structures170B may have different lengths from the other first pattern structures170B in the vertical direction, and all of the plurality of first pattern structures170B may have different lengths in the vertical direction.

The first upper insulating layer UL1and the second upper insulating layer UL2may be sequentially disposed on the stacked structure150. The first upper insulating layer UL1and the second upper insulating layer UL2ofFIG.5Bmay respectively correspond to the first upper insulating layer UL1and the second upper insulating layer UL2ofFIG.4.

FIG.6Ais a plan view illustrating the second key pattern region KPS of the semiconductor device100according to an embodiment.FIG.6Bis a cross-sectional view taken along a line B-B′ ofFIG.6A.

Referring toFIGS.6A and6B, the semiconductor device100may include the second key pattern region KPS positioned on the scribe lane region SLR. The plurality of second pattern structures170S may be disposed in the second key pattern region KPS. Each of the plurality of second pattern structures170S may have a square shape on the plane (X-Y plane) perpendicular to the vertical direction (Z direction). In an embodiment, the plurality of second pattern structures170S may be arranged to form a cross shape. However, the inventive concept is not limited thereto, and the plurality of second pattern structures170S may be arranged in other ways as needed.

The semiconductor device100may include the substrate50, the peripheral circuit wiring structure70disposed on the substrate50, and the interlayer insulating layer80disposed on the substrate50and covering the peripheral circuit wiring structure70in the second key pattern region KPS. The substrate50, the peripheral circuit wiring structure70, and the interlayer insulating layer80ofFIG.6Bmay respectively correspond to the substrate50, the peripheral circuit wiring structure70, and the interlayer insulating layer80ofFIG.4.

In the second key pattern region KPS, the capping insulating layer110including the first capping insulating layer111and the second capping insulating layer113, the barrier metal layer BML including the first barrier metal layer BM and the second barrier metal layer VBM, the substrate layer120, the insulating plate133, and the upper base layer140may be sequentially disposed on the interlayer insulating layer80. For example, the pattern insulating layer115(seeFIG.5B) may not be disposed in the second key pattern region KPS. The capping insulating layer110includes a via hole of which the inner wall is covered by the second barrier metal layer VBM, and the via BV may be disposed in the via hole. The capping insulating layer110, the substrate layer120, the insulating plate133, the upper base layer140, the via BV, and the second barrier metal layer VBM ofFIG.6Bmay respectively correspond to the capping insulating layer110, the substrate layer120, the insulating plate133, the upper base layer140, the via BV, the first barrier metal layer BM, and the second barrier metal layer VBM ofFIG.4.

The stacked structure150may be disposed on the upper base layer140. The stacked structure150may include the plurality of insulating layers151and the plurality of gate electrodes153alternately disposed in a vertical direction (Z direction). The stacked structure150ofFIG.6Bmay correspond to the stacked structure150ofFIG.4.

Each of the plurality of second pattern structures170S may be disposed on the second key pattern region KPS of the scribe lane region SLR. Each of the plurality of second pattern structures170S may penetrate the stacked structure150, the upper base layer140, the insulating plate133, and at least a part of the substrate layer120and extend in the vertical direction (Z direction).

Each of the plurality of second pattern structures170S may include a second barrier layer171S and a second metal layer173S. The configuration of the plurality of second pattern structures170S may be substantially the same as the configuration of the plurality of first pattern structures170B, when viewed in cross-section.

The first upper insulating layer UL1and the second upper insulating layer UL2may be sequentially disposed on the stacked structure150. The first upper insulating layer UL1and the second upper insulating layer UL2ofFIG.6Bmay respectively correspond to the first upper insulating layer UL1and the second upper insulating layer UL2ofFIG.4.

The semiconductor device100according to an embodiment may include the pattern insulating layer115penetrating the barrier metal layer BML and overlapping the plurality of first pattern structures170B in a vertical direction on the first key pattern region KPB in which the plurality of first pattern structures170B having a relatively large horizontal area and vertical length are disposed. Accordingly, the barrier metal layer BML may be removed in the region where the plurality of first pattern structures170B are formed, which may prevent occurrence of a channel hole punching phenomenon in a process of etching the first pattern channel hole170BH to form the plurality of first pattern structures170B. Accordingly, contamination of semiconductor equipment that may occur due to exposure of a part of the barrier metal layer BML by the channel hole punching phenomenon may be prevented, and separation between the substrate layer120and the capping insulating layer110that may occur during a process of removing a sacrificial layer on the first pattern channel hole170BH formed after the etching process may be prevented. Accordingly, the structural reliability of the semiconductor device100may be improved.

FIG.7is a cross-sectional view of a semiconductor device100aaccording to an example embodiment. Specifically,FIG.7is a cross-sectional view taken along a line A-A′ ofFIG.5A. Each configuration of the semiconductor device100ashown inFIG.7is similar to each configuration of the semiconductor device100described with reference toFIGS.4to6B, and thus, hereinafter, differences therebetween are mainly described.

Referring toFIG.7, the semiconductor device100amay include a plurality of first pattern structures170Ba extending through the stacked structure150and the pattern insulating layer115in a vertical direction (Z direction). Each of the plurality of first pattern structures170Ba may include a first insulating layer171Ba, a second insulating layer173Ba, a third insulating layer175Ba, and a channel layer177Ba. The first insulating layer171Ba, the second insulating layer173Ba, the third insulating layer175Ba, and the channel layer177Ba may be sequentially disposed on the inner wall of the first pattern channel hole170BH. In an embodiment, the first insulating layer171Ba, the second insulating layer173Ba, and the third insulating layer175Ba may have an ONO structure together. For example, the first insulating layer171Ba, the second insulating layer173Ba, and the third insulating layer175Ba may form an ONO structure. For example, the first insulating layer171Ba and the third insulating layer175Ba may include silicon oxide, and the second insulating layer173Ba may include silicon nitride. In an embodiment, the channel layer177Ba may include polysilicon doped with impurities and/or polysilicon undoped with impurities.

FIG.8is a cross-sectional view illustrating a part of the chip region (e.g., chip region CR, seeFIG.3) of a semiconductor device200according to an example embodiment. Each component of the semiconductor device200shown inFIG.8is similar to the corresponding component of the semiconductor device100described with reference toFIGS.4to6B, and thus, hereinafter, differences therebetween are mainly described.

Referring toFIG.8, the semiconductor device200may include a cell array structure CS and a peripheral circuit structure PS overlapping each other in a vertical direction (Z direction).

The peripheral circuit structure PS may include the substrate50, peripheral circuit transistors60TR disposed on the substrate50, and the peripheral circuit wiring structure70. The plurality of peripheral circuit transistors60TR may include a peripheral circuit gate60G and source/drain regions62disposed on parts of the substrate50of both sides of the peripheral circuit gate60G. The peripheral circuit wiring structure70may include a plurality of peripheral circuit contacts72and a plurality of peripheral circuit wiring layers74. The peripheral circuit transistor60TR and the peripheral circuit wiring structure70may be covered with the interlayer insulating layer80.

The capping insulating layer110may be disposed between the cell array structure CS and the peripheral circuit structure PS. The capping insulating layer110may include the first capping insulating layer111and the second capping insulating layer113sequentially disposed on the interlayer insulating layer80.

The barrier metal layer BML may cover the upper surface of the capping insulating layer110and the inner wall of the via hole BVH penetrating the capping insulating layer110. For example, the barrier metal layer BML may contact the upper surface of the capping insulating layer110and the inner wall of the via hole BVH. The barrier metal layer BML may include the first barrier metal layer BM covering the upper surface of the capping insulating layer110and the second barrier metal layer VBM covering the inner wall of the via hole BVH.

A substrate layer120may be disposed on the barrier metal layer BML. The substrate layer120may contact an upper surface of the barrier metal layer BML. The substrate layer120may fill an empty space inside the second barrier metal layer VBM covering the inner wall of the via hole BVH. The via BV may be formed together with the substrate layer120. For example, the via BV may be formed at the same time and of the same material as the substrate layer120.

The lower base layer131may be disposed on the substrate layer120in the memory cell region MEC, and the insulating plate133may be disposed on the substrate layer120in the connection region CON. For example, the lower base layer131may contact the substrate layer120in the memory cell region MEC, and the insulating plate133may contact the substrate layer120in the connection region CON. An upper base layer140may be disposed on the lower base layer131and the insulating plate133. The upper base layer140may contact the lower base layer131and the insulating plate133.

In an embodiment, a pattern insulating layer210may be disposed on the capping insulating layer110in at least a part of the connection region CON. The pattern insulating layer210may extend through the first barrier metal layer BM in a vertical direction (Z direction). Accordingly, the first barrier metal layer BM may be removed in the region where the pattern insulating layer210is disposed. In an embodiment, the upper surface of the pattern insulating layer210may be positioned at the same vertical level as the lower surface of the lowermost insulating layer among the plurality of insulating layers151(i.e., the same vertical level as the upper surface of the upper base layer140). In an embodiment, the lower surface of the pattern insulating layer210may be positioned at the same vertical level as the upper surface of the second capping insulating layer113. For example, the lower surface of the pattern insulating layer210may contact the upper surface of the second capping insulating layer113. In another embodiment, the lower surface of the pattern insulating layer210may be positioned at a lower vertical level than the upper surface of the second capping insulating layer113.

In an embodiment, the pattern insulating layer210may be formed of the same material as the second capping insulating layer113. For example, the pattern insulating layer210and the second capping insulating layer113may be formed of silicon oxide.

In an embodiment, the pattern insulating layer210may not be disposed in the memory cell region MEC. Accordingly, the first barrier metal layer BM may not be removed from the memory cell region MEC.

The stacked structure150may be disposed on the pattern insulating layer210and the upper base layer140. The stacked structure150may include the plurality of insulating layers151and the plurality of gate electrodes153alternately disposed in the vertical direction (Z direction). The stacked structure150may be covered by an interlayer insulating layer CL.

The plurality of channel structures160may be disposed in the memory cell region MEC. Each of the plurality of channel structures160may penetrate the stacked structure150, the upper base layer140, the lower base layer131, and at least a part of the substrate layer120and extend in the vertical direction (Z direction). Each of the plurality of channel structures160may be provided in a channel hole160H, and may include a gate insulating layer161, a channel layer163, a filling insulating layer165, and a conductive plug167.

The plurality of dummy channel structures160D may be disposed in the connection region CON. The plurality of dummy channel structures160D may not be electrically connected to the bit lines BL. Each of the plurality of dummy channel structures160D may extend through the interlayer insulating layer CL, the stacked structure150, and at least a part of the pattern insulating layer210in the vertical direction (Z direction). Lower surfaces of the plurality of dummy channel structures160D may be at a lower vertical level than an upper surface of the pattern insulating layer210. The pattern insulating layer210may contact a bottom surface and a portion of the sidewalls of the plurality of dummy channel structures160D. Similar to the channel structure160, each of the plurality of dummy channel structures160D may include a gate insulating layer161D, a channel layer163D, a filling insulating layer165D, and a conductive plug167D. The gate insulating layer161D, the channel layer163D, the filling insulating layer165D, and the conductive plug167D of the dummy channel structures160D may be formed of the same materials as the gate insulating layer161, the channel layer163, the filling insulating layer165, and the conductive plug167, respectively, of the channel structures160. In an embodiment, the horizontal area and horizontal width of each of the plurality of dummy channel structures160D may be greater than the horizontal area and horizontal width of each of the plurality of channel structures160.

The first upper insulating layer UL1and the second upper insulating layer UL2may be sequentially disposed on the stacked structure150and the interlayer insulating layer CL. The plurality of bit line contacts BLC may contact the conductive plug167of the channel structure160and the conductive plug167D of the dummy channel structure160D through the first upper insulating layer UL1. The bit line BL may be disposed on a bit line contact BLC contacting the conductive plug167of the channel structure160among the plurality of bit line contacts BLC. The bit line BL may not be disposed on a bit line contact BLC contacting the conductive plug167D of the dummy channel structure160D among the plurality of bit line contacts BLC. The plurality of bit lines BL may penetrate the second upper insulating layer UL2and contact the bit line contacts BLC corresponding thereto.

Each of the plurality of contact structures CNT may be disposed in the connection region CON. Each of the plurality of contact structures CNT may penetrate the first upper insulating layer UL1, the interlayer insulating layer CL, and a part of the gate electrode153and extend in the vertical direction (Z direction).

The semiconductor device200according to an example embodiment may include a pattern insulating layer210penetrating the barrier metal layer BML and overlapping the plurality of dummy channel structures160D in a vertical direction in at least a part of the connection region CON where the dummy channel structure160D having a relatively large horizontal area and a relatively large length is disposed. Accordingly, the barrier metal layer BML may be removed in the region where the plurality of dummy channel structures160D are formed, which may prevent occurrence of a channel hole punching phenomenon in a process of etching the dummy channel holes160DH to form the plurality of dummy channel structures160D. Accordingly, contamination of semiconductor equipment that may occur due to exposure of a part of the barrier metal layer BML by the channel hole punching phenomenon may be prevented, and separation between the substrate layer120and the capping insulating layer110that may occur during a process of removing a sacrificial layer on the dummy channel holes160DH formed after the etching process may be prevented. Accordingly, the structural reliability of the semiconductor device200may be improved.

FIGS.9A to10Dare cross-sectional views illustrating a method of manufacturing the semiconductor device100, according to an example embodiment. Specifically,FIGS.9A to9Eare cross-sectional views showing regions corresponding to the first key pattern region KPB, andFIGS.10A to10Dare cross-sectional views showing regions corresponding to the second key pattern region KPS.

Referring toFIGS.9A and10A, the peripheral circuit structure PS including the peripheral circuit transistor60TR disposed on the substrate50and the peripheral circuit wiring structure70covered by the interlayer insulating layer80may be formed. Next, the first capping insulating layer111and the second capping insulating layer113may be sequentially formed on the peripheral circuit structure PS. Next, the via hole BVH penetrating the first capping insulating layer111and the second capping insulating layer113and exposing the peripheral circuit wiring structure70in the bottom surface thereof may be formed.

Referring toFIGS.9B and10B, in a resultant ofFIGS.9A and10A, the barrier metal layer BML covering the inner wall of the via hole BVH and the upper surface of the second capping insulating layer113may be formed. Next, the substrate layer120, the insulating plate133, and the upper base layer140may be sequentially formed on the barrier metal layer BML. In an embodiment, in a process of forming the substrate layer120on the barrier metal layer BML, the via BV filling the via hole BVH penetrating the capping insulating layer110may be formed together with the substrate layer120.

Referring toFIG.9C, in a resultant ofFIGS.9B and10B, the substrate layer120, the insulating plate133, and the upper base layer140formed on the first key pattern region (e.g., first key pattern region KPB, seeFIG.3) may be etched. Next, the pattern insulating layer115may be formed on the capping insulating layer110of the first key pattern region (e.g., first key pattern region KPB, seeFIG.3) exposed by the etching. In this regard, the substrate layer120, the insulating plate133, and the upper base layer140formed on the second key pattern region KPS are not etched, and thus, the substrate layer120, the insulating plate133, and the upper base layer140of the second key pattern region KPS may not be removed as shown inFIG.10B.

Referring toFIGS.9D and10C, a stacked structure150S may be formed in a resultant ofFIGS.9C and10B. Specifically, the stacked structure150S may be formed on the pattern insulating layer115and the upper base layer140in the first key pattern region KPB, and the stacked structure150S may be formed on the upper base layer140in the second key pattern region KPS. The stacked structure150S may be formed by alternately forming a plurality of insulating layers151and a plurality of sacrificial layers153S. The plurality of sacrificial layers153S may be replaced with the plurality of gate electrodes153through a series of processes after the method of manufacturing the semiconductor device100described with reference toFIGS.9A to10D.

Next, the first pattern channel hole170BH penetrating the stacked structure150S and at least a part of the pattern insulating layer115may be formed in the first key pattern region KPB, and the second pattern hole170SH penetrating the stacked structure150S, the upper base layer140, the insulating plate133, and at least a part of the substrate layer120may be formed in the second key pattern region KPS. In an embodiment, the horizontal area and vertical length of the first pattern channel hole170BH may be greater than the horizontal area and vertical length of the second pattern hole170SH.

Referring toFIGS.9E and10D, in resultants ofFIGS.9D and10C, the first pattern structure170B and the second pattern structure170S may be formed. Specifically, the first barrier layer171B and the first metal layer173B may be sequentially formed on the inner wall of the first pattern channel hole170BH in the first key pattern region KPB, and the second barrier layer171S and the second metal layer173S may be sequentially formed on the inner wall of the second pattern hole170SH in the second key pattern region KPS. Thereafter, the semiconductor device100may be formed by forming the channel structure160, the dummy channel structure160D, the contact structure CNT, and the bit line BL shown inFIG.4.

FIG.11is a diagram schematically illustrating an electronic system1000including a semiconductor device1100according to an example embodiment.

Referring toFIG.11, the electronic system1000according to an example embodiment may include the semiconductor device1100and a controller1200electrically connected to the semiconductor device1100. The electronic system1000may be a storage device including one or a plurality of semiconductor devices1100or an electronic device including the storage device. For example, the electronic system1000may be a solid state drive device (SSD) including at least one semiconductor device1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

The semiconductor device1100may be a non-volatile memory device. For example, the semiconductor device1100may be a NAND flash memory device including at least one of the structures described above with respect to the semiconductor devices100,100a, and200with reference toFIGS.3to8. The semiconductor device1100may include a first structure1100F and a second structure1100S on the first structure1100F. In some embodiments, the first structure1100F may be disposed next to the second structure1100S. The first structure1100F may be a peripheral circuit structure including a decoder circuit1110, a page buffer1120, and a logic circuit1130. The second structure1100S may be a memory cell structure including the bit line BL, the common source line CSL, the plurality of word lines WL, the first and second gate upper lines UL1and UL2, the first and second gate lower lines LL1and LL2, and a plurality of memory cell strings CSTR between the bit line BL and the common source line CSL.

In the second structure1100S, the plurality of memory cell strings CSTR may include lower transistors LT1and LT2adjacent to the common source line CSL, upper transistors UT1and UT2adjacent to the bit line BL, and a plurality of memory cell transistors MCT disposed between the lower transistors LT1and LT2and the upper transistors UT1and UT2. The number of lower transistors LT1and LT2and the number of upper transistors UT1and UT2may be variously modified according to some embodiments.

In some embodiments, the upper transistors UT1and UT2may include string selection transistors, and the lower transistors LT1and LT2may include ground selection transistors. The plurality of gate lower lines LL1and LL2may be gate electrodes of the lower transistors LT1and LT2, respectively. The word line WL may be a gate electrode of the memory cell transistor MCT, and the gate upper lines UL1and UL2may be gate electrodes of the upper transistors UT1and UT2.

The common source line CSL, the plurality of gate lower lines LL1and LL2, the plurality of word lines WL, and the plurality of gate upper lines UL1and UL2may be electrically connected to the decoder circuit1110through a plurality of first connection wirings1115extending to the second structure1100S in the first structure1100F. The plurality of bit lines BL may be electrically connected to the page buffer1120through a plurality of second connection wirings1125extending to the second structure1100S in the first structure1100F.

In the first structure1100F, the decoder circuit1110and the page buffer1120may perform a control operation on at least one of the plurality of memory cell transistors MCT. The decoder circuit1110and the page buffer1120may be controlled by the logic circuit1130.

The semiconductor device1100may communicate with the controller1200through the input/output pads1101electrically connected to the logic circuit1130. The input/output pads1101may be electrically connected to the logic circuit1130through input/output connection wiring1135extending to the second structure1100S in the first structure1100F.

The controller1200may include a processor1210, a NAND controller1220, and a host interface1230. According to some embodiments, the electronic system1000may include a plurality of semiconductor devices1100, and, in this case, the controller1200may control the plurality of semiconductor devices1100.

The processor1210may control the overall operation of the electronic system1000including the controller1200. The processor1210may operate according to certain firmware and may access the semiconductor device1100by controlling the NAND controller1220. The NAND controller1220may include a NAND interface1221that processes communication with the semiconductor device1100. A control command for controlling the semiconductor device1100, data to be written to the plurality of memory cell transistors MCT of the semiconductor device1100, and data to be read from the plurality of memory cell transistors MCT of the semiconductor device1100may be transmitted through the NAND interface1221. The host interface1230may provide a communication function between the electronic system1000and an external host. When a control command is received from an external host through the host interface1230, the processor1210may control the semiconductor device1100in response to the control command.

FIG.12is a schematic perspective view of an electronic system2000including a semiconductor device according to an example embodiment.

Referring toFIG.12, the electronic system2000according to an example embodiment may include a main substrate2001, a controller2002mounted on the main substrate2001, one or more semiconductor packages2003, and DRAM2004. The semiconductor package2003and the DRAM2004may be connected to the controller2002through a plurality of wiring patterns2005formed on the main substrate2001.

The main substrate2001may include a connector2006including a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector2006may vary depending on a communication interface between the electronic system2000and the external host. In some embodiments, the electronic system2000may communicate with an external host according to any one of interfaces, such as Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI-Express), Serial Advanced Technology Attachment (SATA), M-Phy for Universal Flash Storage (UFS), etc. In some embodiments, the electronic system2000may operate by power supplied from an external host through the connector2006. The electronic system2000may further include a Power Management Integrated Circuit (PMIC) that distributes the power supplied from the external host to the controller2002and the semiconductor package2003.

The controller2002may write data to the semiconductor package2003or read data from the semiconductor package2003and improve the operating speed of the electronic system2000.

The DRAM2004may be a buffer memory mitigating a speed difference between the semiconductor package2003, which is a data storage space, and an external host. The DRAM2004included in the electronic system2000may also operate as a kind of cache memory, and may provide a space temporarily storing data in a control operation on the semiconductor package2003. When the electronic system2000includes the DRAM2004, the controller2002may further include a DRAM controller controlling the DRAM2004in addition to the NAND controller controlling the semiconductor package2003.

The semiconductor package2003may include first and second semiconductor packages2003aand2003bspaced apart from each other. Each of the first and second semiconductor packages2003aand2003bmay be a semiconductor package including the plurality of semiconductor chips2200. Each of the first and second semiconductor packages2003aand2003bmay include a package substrate2100, a plurality of semiconductor chips2200on the package substrate2100, an adhesive layer2300disposed on a lower surface of each of the plurality of semiconductor chips2200, a connection structure2400electrically connecting the plurality of semiconductor chips2200and the package substrate2100, and a molding layer2500covering the plurality of semiconductor chips2200and the connection structure2400on the package substrate2100.

The package substrate2100may be a printed circuit board including a plurality of package upper pads2130. Each of the plurality of semiconductor chips2200may include input/output pads2210. The input/output pads2210may correspond to the input/output pads1101ofFIG.11. Each of the plurality of semiconductor chips2200may include a plurality of gate stacks3210and a plurality of channel structures3220. Each of the plurality of semiconductor chips2200may include at least one of the structures described above with respect to the semiconductor devices100,100a, and200with reference toFIGS.3to8.

In some embodiments, the connection structure2400may be a bonding wire electrically connecting the input/output pad2210and the package upper pad2130. Accordingly, in the first and second semiconductor packages2003aand2003b, the plurality of semiconductor chips2200may be electrically connected to each other using a bonding wire method, and may be electrically connected to the package upper pads2130of the package substrate2100. In some embodiments, in the first and second semiconductor packages2003aand2003b, the plurality of semiconductor chips2200may be electrically connected to each other by a connection structure including a through silicon via TSV instead of the connection structure2400of the bonding wire method.

In some embodiments, the controller2002and the plurality of semiconductor chips2200may be included in one package. In some embodiments, the controller2002and the plurality of semiconductor chips2200may be mounted on a separate interposer substrate different from the main substrate2001, and the controller2002and the plurality of semiconductor chips2200may be connected to each other by wirings formed on the interposer substrate.

FIG.13is a schematic cross-sectional view of semiconductor packages according to an example embodiment. InFIG.13, the configuration along the line II-II′ ofFIG.12is shown in more detail.

Referring toFIG.13, in a semiconductor package2003, each of semiconductor chips2200bmay include a semiconductor substrate4010, a first structure4100on the semiconductor substrate4010, and a second structure4200bonded to the first structure4100using a wafer bonding method on the first structure4100.

The first structure4100may include a peripheral circuit region including a peripheral wiring4110and first bonding structures4150. The second structure4200may include a common source line4205, a gate stack structure4210between the common source line4205and the first structure4100, memory channel structures4220penetrating the gate stack structure4210, and second bonding structures4250electrically connected to the word lines (e.g., word lines WL ofFIG.11) of the memory channel structures4220and the gate stack structure4210, respectively. For example, the second bonding structures4250may be electrically connected to the memory channel structures4220and the word lines (e.g., word lines WL ofFIG.11) respectively through the bit lines4240electrically connected to the memory channel structures4220and gate connection wirings electrically connected to word lines (e.g., word lines WL inFIG.11). The first bonding structures4150of the first structure4100and the second bonding structures4250of the second structure4200may be bonded in contact with each other. Bonded parts of the first bonding structures4150and the second bonding structures4250may include, for example, copper (Cu).

Each of the semiconductor chips2200bmay further include the input/output pads (e.g., input/output pads2210inFIG.12) electrically connected to the peripheral wirings4110of the first structure4100.

The semiconductor chips2200ofFIG.12and the semiconductor chips2200bofFIG.13may be electrically connected to each other by the connection structures2400in the form of bonding wires. However, in some embodiments, semiconductor chips in one semiconductor package, such as the semiconductor chips2200ofFIG.12and the semiconductor chips2200bofFIG.13, may be electrically connected to each other by a connection structure including the through electrode TSV.