Concentric capacitor structure

A concentric capacitor structure generally comprising concentric capacitors is disclosed. Each concentric capacitor comprises a first plurality of perimeter plates formed on a first layer of a substrate and a second plurality of perimeter plates formed on a second layer of the substrate. The first plurality of perimeter plates extend in a first direction and the second plurality of perimeter plates extend in a second direction different than the first direction. A first set of the first plurality of perimeter plates is electrically coupled to a first set of the second plurality of perimeter plates and a second set of the first plurality of perimeter plates is electrically coupled to a second set of the second plurality of perimeter plates. A plurality of capacitive cross-plates are formed in the first layer such that each cross-plate overlaps least two of the second plurality of perimeter plates.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. These advances, however, have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.

Various active and/or passive electronic components can be formed on a semiconductor IC. Capacitors are essential components for many ICs, such as sample-and-hold circuits, analog-to-digital (A/D) circuits, digital-to-analog (D/A) circuits and resonant circuits, switched-capacitor and continuous-time filters, as well as to many radio frequency (RF) applications. Capacitors are extensively used for many logic and other applications in the semiconductor manufacturing industry and are integrated into various types of semiconductor devices. Due to higher integration requirements to minimize costs associated with IC fabrication processes, the semiconductor manufacturing industry strives toward economization of each process step and minimization of chip size, while maximizing quality and functionality to the extent possible. Due to these trends of miniaturization or scaling of ICs to provide smaller ICs and improved performance, capacitor designs that consume low areas and possess high capacitance density are highly desirable.

Analog ICs generally employ various types of integrated capacitors utilizing metal-oxide-semiconductors (MOS) including p-n junction capacitors, metal-insulator-metal (MIM) capacitors, poly-to-poly capacitors, metal-oxide-metal (MOM) capacitors, and other structures. MOM capacitors, also known as vertical parallel plate (VPP) capacitors, can include natural vertical capacitors (NVCAPs), lateral flux capacitors, comb capacitors, interdigitated finger capacitors, etc. and are one of the most widely used MOS capacitors due to respective characteristics, e.g., high capacitance density, low parasitic capacitance, symmetric design, superior RF characteristics, good matching characteristics, and processing advantages.

DETAILED DESCRIPTION

Terms used herein are only used to describe the specific embodiments, which are not used to limit the claims appended herewith. For example, unless limited otherwise, the term “one” or “the” of the single form may also represent the plural form. The terms such as “first” and “second” are used for describing various devices, areas and layers, etc., though such terms are only used for distinguishing one device, one area or one layer from another device, another area or another layer. Therefore, the first area can also be referred to as the second area without departing from the spirit of the claimed subject matter, and the others are deduced by analogy. Moreover, space orientation terms such as “under”, “on”, “up”, “down”, etc. are used to describe a relationship between a device or a characteristic and another device or another characteristic in the drawing. It should be noted that the space orientation term can cover different orientations of the device besides the orientation of the device illustrated in the drawing. For example, if the device in the drawing is turned over, the device located “under” or “below” the other devices or characteristics is reoriented to be located “above” the other devices or characteristics. Therefore, the space orientation term “under” may include two orientations of “above” and “below”.

Embodiments of the present disclosure are applicable to various types of integrated capacitors utilizing metal-oxide-semiconductors (MOS) including, but not limited to, p-n junction capacitors, metal-insulator-metal (MIM) capacitors, poly-to-poly capacitors, metal-oxide-metal (MOM) capacitors, and combinations thereof. Exemplary MOM or vertical parallel plate (VPP) capacitors include but are not limited to, natural vertical capacitors (NVCAPs), lateral flux capacitors, comb capacitors, interdigitated finger capacitors, etc. Exemplary capacitors according to embodiments of the present disclosure provide high capacitance density, low parasitic capacitance, symmetric design, superior RF characteristics, good matching characteristics, and superior processing advantages over conventional capacitors.

Exemplary capacitors according to embodiments of the present disclosure can exploit the effect of intralayer and/or interlayer capacitive coupling between plates formed by standard metallization wiring lines and/or vias. Lateral capacitive coupling can provide better matching characteristics than vertical coupling due to a better process control of lateral dimensions than that of metal and dielectric layer thicknesses. To increase the capacity density (capacitance per unit area of silicon chip), several metal layers can be connected in parallel by vias, forming a vertical metal wall or mesh. Normally, the lowest metal layers (e.g., M1-M5 layers) having a minimum metal line width and spacing can be used for exemplary capacitors to maximize capacitance density.

FIG. 1is a top view or cross section of an integrated capacitor structure according to some embodiments of the present disclosure.FIG. 2Ais a vertical cross section of a switch for the integrated capacitor structure ofFIG. 1, andFIG. 2Bis a schematic diagram for an exemplary switch. With reference toFIGS. 1, 2A and 2B, an integrated capacitor structure100includes a matrix of integrated capacitor units110, each of which comprises an outer vertical metal plate(s)112and an inner vertical metal plate(s)114. In the non-limiting configuration illustrated inFIG. 1, the inner vertical metal plate(s)114forms an H-shaped structure115with outer vertical metal plate(s)112enveloping each structure115and separating adjacent units110and adjacent, parallel inner vertical metal plates114within the H-shaped structure115. In some embodiments, the interior structures in the capacitor units110can possess other suitable geometries. Further, in some embodiments of the present disclosure, an integrated capacitor structure100has different or varying interior structures for any number of capacitor units110within an exemplary integrated capacitor structure100. It should also be noted that the number of integrated capacitor units110in the illustrated structure100is only exemplary as embodiments according to the present disclosure can include more or less than the six integrated capacitor units110depicted.

The outer vertical metal plates112can be insulated from adjacent inner vertical metal plates114using an insulation material116such as, but not limited to, interlayer dielectrics or other suitable insulators employed in semiconductor fabrication processes. The outer and inner vertical metal plates112,114can be formed on a semiconductor substrate (not shown) and can be formed from several metal layers connected in parallel by vias, or otherwise, to thereby form a vertical metal wall or mesh. The outer vertical metal plate112can be electrically connected to a signal line (not shown), and the inner vertical metal plate(s)114can be electrically connected to a ground node122in a switch120depicted inFIG. 2A. Exemplary switches120can comprise one or more grounding nodes122and/or gate notes124whereby each interior structure115is connected to one switch120. Exemplary switches120can be, but are not limited to, a metal-oxide-semiconductor field effect transistor (MOSFET), a diode, a bipolar junction transistor (BJT), a PN transistor, an NP transistor, an NPN transistor, a PNP transistor, or other switching mechanism. In some embodiments of the present disclosure, an exemplary integrated capacitor structure100can comprise a plurality of different switches for the respective units110within the integrated capacitor structure100. Further, any or all of the capacitor units110can be independently tuned by a respective switch120.

For example, various embodiments of the present disclosure can provide an exemplary high resolution and low area switched capacitance technique and system to switch between capacitor units110within a structure100. One such technique is illustrated inFIG. 2Bwhere appropriate switching mechanisms250or sets thereof, e.g., diode, transistor, etc. are utilized to switch between one or more sets or banks of capacitors or capacitor units within a structure. Such an exemplary switching mechanism can be employed to change capacitance thereby affecting oscillation frequency in a respective device. Additional discussion regarding this and other exemplary, non-limiting switching mechanisms are provided in commonly-assigned U.S. patent application Ser. No. 13/902,392 filed May 24, 2013 and entitled, “A High Resolution and Process Limitation-Free Switched Capacitance Method and Apparatus,” the entire disclosure of which is incorporated herein by reference. Thus, an exemplary structure100can provide a wide range of capacitance for various applications. As the sides of each of the integrated capacitor units110are facing substantially similar environments, the integrated capacitor structure100provides exemplary matching characteristics and there is no need to provide dummy metals that typically surround conventional capacitor units.

FIG. 3is a top view or cross section of an integrated capacitor structure according to other embodiments of the present disclosure.FIG. 4is a perspective view of the integrated capacitor structure ofFIG. 3. With reference toFIGS. 3 and 4, an integrated capacitor structure300includes two interior integrated capacitor units310, each of which comprises an outer vertical metal plate(s)312and an inner vertical metal plate(s)314or post. Vertical metal plates (s)312may also comprise metal layer(s) and vias) in between. In the non-limiting embodiment illustrated inFIG. 3, the inner vertical metal plate(s)314forms a post-like structure315with outer vertical metal plate(s)312enveloping each structure315and separating adjacent units310. Of course, the interior structures in the capacitor units310can possess other geometries in some embodiments. Further, some embodiments of the present disclosure can provide an integrated capacitor structure300having different or varying interior structures for any number of capacitor units310, and it should also be noted that the number of integrated capacitor units310within the illustrated structure300is only exemplary as embodiments according to the present disclosure can include more or less than the two integrated capacitor units310depicted. As illustrated inFIGS. 3 and 4, additional plates317,318,319can be concentrically provided in coils for an exemplary integrated capacitor structure300.

Adjacent vertical metal plates312,314,317,318,319can be insulated from each other using an insulation material316such as, but not limited to, interlayer dielectrics or other suitable insulators employed in semiconductor fabrication processes. These metal plates can be formed on a semiconductor substrate (not shown) and can be formed from several metal layers connected in parallel by vias, or otherwise, to thereby form a vertical metal wall or mesh. The outer vertical metal plate312and additional plate(s)318can be electrically connected to a signal line (not shown), and the inner vertical metal plate(s)314and additional plates317,319can be electrically connected to a ground node in an exemplary switch described above. Exemplary switches can be, but are not limited to, a MOSFET, a diode, a BJT, a PN transistor, an NP transistor, an NPN transistor, a PNP transistor, or other switching mechanism. In some embodiments of the present disclosure, an exemplary integrated capacitor structure300can comprise a plurality of different switches for the respective units310within the integrated capacitor structure300. Further, any or all of the capacitor units310can be independently tuned by a respective switch. Thus, an exemplary structure300can provide a wide range of capacitance for various applications. For example, in some embodiments of the present disclosure an inner structure or coil can possess a capacitance of 1 fF with concentric coils or structures possessing capacitances of 2 fF, 4 fF, 8 fF, etc. Thus, some embodiments can utilize the structure depicted inFIGS. 3 and 4to provide a varactor-like capacitor.

FIGS. 5-10provide top views or cross sections of various integrated capacitor structures according to additional embodiments of the present disclosure. With reference toFIGS. 5 and 6, integrated capacitor structures500,600can include a matrix of integrated capacitor units510, each of which comprises an outer vertical metal plate(s)512and an inner vertical metal plate(s)514. In the non-limiting configuration illustrated inFIG. 5, the inner vertical metal plate(s)514forms an I-shaped structure515with outer vertical metal plate(s)512enveloping each structure515and separating adjacent units510and adjacent, parallel inner vertical metal plates514within the I-shaped structure515. The interior structures515in the capacitor units510can possess other geometries in some embodiments. In the non-limiting configuration illustrated inFIG. 6, the inner vertical metal plate(s)514forms one or more I-shaped structures515with the outer vertical metal plate512enveloping each structure(s)515and separating adjacent units510. As illustrated, some units510can include a plurality of inner vertical metal plates514. It should be also noted that the number of integrated capacitor units510in the illustrated structures500,600is only exemplary as embodiments according to the present disclosure can include more or less than the eight integrated capacitor units510depicted. The outer vertical metal plates512can be insulated from adjacent inner vertical metal plates514using an insulation material516such as, but not limited to, interlayer dielectrics or other suitable insulators employed in semiconductor fabrication processes. The outer and inner vertical metal plates512,514can be formed on a semiconductor substrate (not shown) and can be formed from several metal layers connected in parallel by vias, or otherwise, to thereby form a vertical metal wall or mesh. The outer vertical metal plate512can be electrically connected to a signal line (not shown), and the inner vertical metal plate(s)514can be electrically connected to a ground node in an exemplary switch described above. In some embodiments, if the switch is “ON”, the inner vertical plate(s)514is connected to the ground. Conversely, in some embodiments if the switch is “OFF”, the inner vertical plates are floating which provides a minor parasitic between the outer and inner vertical metal plates512,514. In additional embodiments of the disclosure, each different section of the inner metal plate514can be connected to the same or to different switches to control capacitance of the respective device based on the design specifications therefor. Exemplary switches can be, but are not limited to, a MOSFET, a diode, a BJT, a PN transistor, an NP transistor, an NPN transistor, a PNP transistor, or other switching mechanism. In some embodiments of the present disclosure, exemplary integrated capacitor structures500,600can comprise a plurality of different switches for the respective units510within the integrated capacitor structures500,600. Further, any or all of the capacitor units510can be independently tuned by a respective switch. Thus, exemplary structures500,600can provide a wide range of capacitance for various applications.

With reference toFIGS. 7 and 8, integrated capacitor structures700,800include a matrix of integrated capacitor units710, each of which comprises an outer vertical metal plate(s)712and an inner vertical metal plate(s)714. In the non-limiting configurations illustrated inFIGS. 7 and 8, the inner vertical metal plate(s)714form an I-shaped structure715with the outer vertical metal plate712enveloping each structure715and separating adjacent units710and adjacent, parallel inner vertical metal plates714within the I-shaped structure715. The capacitor units710can possess other suitable geometries in some embodiments. It should be also noted that the number of integrated capacitor units710in the illustrated structures700,800is only exemplary as embodiments according to the present disclosure can include more or less than the eight integrated capacitor units710depicted. In the depicted configurations, additional vertical metal plates750can envelope the capacitor structure800(FIG. 8) or partially enclose the capacitor structure700(FIG. 7). Additional concentric plates (not shown) or coils can also be employed to provide structures having varying and tunable capacitances such as the concentric plates illustrated inFIGS. 3 and 4. The outer vertical metal plate(s)712can be insulated from adjacent inner vertical metal plates714and/or additional plates750using an insulation material716such as, but not limited to, interlayer dielectrics or other suitable insulators employed in semiconductor fabrication processes. The vertical metal plates712,714,750can be formed on a semiconductor substrate (not shown) and can be formed from several metal layers connected in parallel by vias, or otherwise, to thereby form a vertical metal wall or mesh. The outer vertical metal plate(s)712and/or any additional plates, as applicable, can be electrically connected to a signal line (not shown), and the inner vertical metal plate(s)714and/or additional plates750can be electrically connected to a ground node in an exemplary switch described above. Exemplary switches can be, but are not limited to, a MOSFET, a diode, a BJT, a PN transistor, an NP transistor, an NPN transistor, a PNP transistor, or other switching mechanism. In some embodiments of the present disclosure, exemplary integrated capacitor structures700,800can comprise a plurality of different switches for the respective units710within the integrated capacitor structures700,800. Further, any or all of the capacitor units710can be independently tuned by a respective switch. Thus, exemplary structures700,800can provide a wide range of capacitance for various applications.

With reference toFIG. 9, an integrated capacitor structure900includes an interdigitated finger matrix910having a first set912of finger structures including vertical metal plates and a second set914of finger structures also including vertical metal plates. It should be also noted that the number of interdigitated fingers in the illustrated structure900is only exemplary as embodiments according to the present disclosure can include more or less than the three digits depicted. The first and second sets912,914of finger structures can be insulated from each other and adjacent digits in the same set using an insulation material916such as, but not limited to, interlayer dielectrics or other insulators employed in semiconductor fabrication processes. The first and second sets912,914can be formed on a semiconductor substrate (not shown) and can be formed from several metal layers connected in parallel by vias, or otherwise, to thereby form a vertical metal wall or mesh. One of the two sets of finger structures912or914can be electrically connected to a signal line (not shown), and the other set of finger structures914or912can be electrically connected to a ground node in an exemplary switch920described above. Exemplary switches can be, but are not limited to, a MOSFET, a diode, a BJT, a PN transistor, an NP transistor, an NPN transistor, a PNP transistor, or other switching mechanism. In some embodiments of the present disclosure, the structure900can be a MOM capacitor.

With reference toFIG. 10, an exemplary integrated capacitor structure1000can be a differential capacitor comprising a first interdigitated structure1010opposing a second interdigitated structure1020each electrically connected to a signal line (not shown). Digits1011,1021of the respective structures complement and can, in some embodiments, mirror opposing digits on the other structure thereby forming a plurality of differential capacitor units1005. Each of the digits1011,1021and connecting portions thereof comprise vertical metal plates. Positioned in these differential capacitor units1005and hence between digits1011,1021of the first and second interdigitated structures1010,1020are interior vertical metal plates1014each electrically connected to a ground node in an exemplary switch described above. Of course, the interior vertical metal plates1014can possess any suitable geometry. Exemplary switches can be, but are not limited to, a MOSFET, a diode, a BJT, a PN transistor, an NP transistor, an NPN transistor, a PNP transistor, or other switching mechanism. It should be noted that the number of differential capacitor units1005in the illustrated structure is only exemplary as embodiments according to the present disclosure can include more or less than the three differential capacitor units1005depicted. The digits1011,1012and interior metal plates1014can be insulated from adjacent vertical metal plates using an insulation material1016such as, but not limited to, interlayer dielectrics or other suitable insulators employed in semiconductor fabrication processes. The vertical metal plates can be formed on a semiconductor substrate (not shown) and can be formed from several metal layers connected in parallel by vias, or otherwise, to thereby form a vertical metal wall or mesh. In some embodiments of the present disclosure, an exemplary integrated capacitor structure1000can comprise a plurality of different switches for the respective units1005. Further, any or all of the capacitor units1005can be independently tuned by a respective switch. Thus, an exemplary differential capacitor structure1000can provide a wide range of capacitance for various applications.

FIG. 11is a top view of one embodiment of a concentric capacitor structure1100. The concentric capacitor structure1100comprises a plurality of concentric capacitors1102a,1102b. Each of the concentric capacitors1102a,1102bcomprise a first concentric capacitive plate1104,1108and a second concentric capacitive plate11061110. The first concentric capacitive plates1104,1108are coupled to a first unidirectional metal1112and the second concentric capacitive plates1106,1110bare coupled to a second unidirectional metal1114. In some embodiments, each of the first concentric capacitive plates1104,1108define a negative capacitive plate and each of the second concentric capacitive plates1106,1110define a positive capacitive plate. Each of the capacitive plates1104,1106,1108,1110comprise a plurality orthogonal metal routing plates formed in at least a first routing layer1124aand a second routing layer1124b, as shown inFIGS. 11B and 11Crespectively.

FIG. 11Aillustrates the first concentric capacitor1102a. The first concentric capacitor1102acomprise a first concentric capacitive plate1104and a second concentric capacitive plate1106. The first concentric capacitive plate1104comprises a first set of metal routing plates1104a-1104d(or perimeter plates1104a-1104d). The second concentric capacitive plate1106comprises a second set of metal routing plates1106a-1106d(also referred to as perimeter plates herein). The perimeter plates1104a-1106ddefine the perimeters of the respective concentric capacitive plates1104,1106. A first subset of each of the first and second sets of perimeter plates1104a,1104c,1106a,1106care formed in a first routing layer1124aand extend longitudinally in a first direction. A second subset of each of the first and second set of perimeter plates1104b,1104d,1106b,1106dare formed in a second routing layer1124band extend longitudinally in a second direction. In some embodiments, the first direction is orthogonal to the second direction. The ends of the first subset of perimeter plates1104a,1104c,1106a,1106coverlap the ends of the second subset of perimeter plates1104b,1104d,1106b,1106d. The first set of perimeter plates1104a-1104dare coupled by a plurality of inter-layer vias1126acoupling the ends of each of the first plurality of perimeter plates1104a-1104dto define a first continuous capacitive plate1104. Similarly, the second set of perimeter plates1106a-1106dare coupled by a plurality of inter-layer vias1126bto define a second continuous capacitive plate1106. As used herein, reference numbers1104-1110are used to refer to the concentric capacitor plates as a single connected plate. References to reference numbers having letters, for example, references to reference number1104a-1104d, refer to individual perimeter plates of the concentric capacitor plates.

Each of the concentric capacitors1102a,1102bcomprise a plurality of cross-plate routing plates1116,1118. The cross-plate routing plates1116,1118extend from at least the first concentric capacitive plate1104,1108of a concentric capacitor1102a,1102bto at least the second concentric capacitive plate1106,1110of the concentric capacitor1102a,1102b. For example, as illustrated inFIG. 11A, the first concentric capacitor1102acomprises a first plurality of cross-plate routing plates1116extending from first perimeter plates1104aand1104cto second perimeter plates1106aand1106c. Similarly, a second plurality of cross-plate routing plates1118extend from first perimeter plates1104band1104dto second perimeter plates1106band1106d. In some embodiments, the cross-plate routing plates1116,1118extend from an outermost perimeter plate1104ato an innermost perimeter plate1106b(seeFIGS. 11B and 11C).

The cross-plate routing plates1116,1118are formed in an opposite routing layer from the routing layer comprising the overlapping perimeter plates. For example, as shown inFIG. 11B, the first perimeter plates1104aand1104cand second perimeter plates1106aand1106care formed in the first routing layer1124a. The first set of cross-plate routing plates1116, which overlap the first perimeter plates1104a,1104cand second perimeter plates1106a,1106c, are formed in the second routing layer1124b(seeFIG. 11C). Similarly, the first perimeter plates1104band1104dand second perimeter plates1106band1106dare formed in the second routing layer. The second set of cross-plate routing plates1118, which overlap the first perimeter plates1104b,1104dand second perimeter plates1106b,1106d, are formed in the first routing layer1124a.

In some embodiments, the cross-plate routing plates1116,1118extend in a direction orthogonal to the longitudinal direction of the overlapping perimeter plates1104a-1106d. For example, as shown inFIG. 11A, the first perimeter plates1104aand1104cand second perimeter plates1106aand1106cextend longitudinally in the first direction. The first set of cross-plate routing plates1116overlap the first perimeter plates1104a,1104cand second perimeter plates1106a,1106cand extend longitudinally in the second direction. Similarly, the first perimeter plates1104band1104dand second perimeter plates1106band1106dextend longitudinally in the second direction. The second set of cross-plate routing plates1118overlap the first perimeter plates1104b,1104dand second perimeter plates1106b,1106cand extend longitudinally in the first direction. The cross-plate routing plates1116,1118are coupled to the perimeter plates1104a-1106dby a plurality of inter-layer vias1120a,1120b. Although embodiments having orthogonal plates are illustrated herein, it will be recognized that the cross-plate routing plates and overlapping perimeter plates may overlap at any suitable angle. For example, in some embodiments, the cross-plate routing plates may extend in a forty-five degree angle, or any other suitable angle, with respect to the overlapping perimeter plates.

In some embodiments, each routing layer1124a,1124bcomprises metal routing plates extending in a single longitudinal direction.FIGS. 11B & 11Crespectively illustrate the first and second routing layers1124a,1124bof the concentric capacitive structure1100. As shown inFIG. 11B, the first routing layer1124acomprises first perimeter plates1104a,1104c, second perimeter plates1106a,1106c, and the second plurality of cross-plate routing plates1118. Each of the first perimeter plates1104a,1104c, second perimeter plates1106a,1106c, and second plurality of cross-plate routing plates1118extend longitudinally in the first direction. Similarly, as shown inFIG. 11C, the second routing layer1124bcomprises first perimeter plates1104b,1104d, second perimeter plates1106b,1106d, and the first plurality of cross-plate routing plates1116. Each of the first perimeter plates1104b,1104d, second perimeter plates1106b,1106d, and first plurality of cross-plate routing plates1116extend longitudinally in the second direction.

In some embodiments, the first direction is perpendicular to the second direction. In some embodiments, the perimeter plates1104a-1106dextend in third orthogonal direction to define a capacitive plate area. In some embodiments, the concentric capacitive structure1100comprises additional routing layers comprising perimeter plates and/or cross-plate routing plates that are symmetric with the routing plates formed on one of the first routing layer1124aor the second routing layer1124b.

The cross-plate routing plates1116,1118are coupled to the capacitive plates1104,1106,1108,1110by a plurality of vias1120a,1120b(or contacts). A first set of vias1120acouple the first capacitive plates1104,1108to a first set of cross-plate routing plates1116a,1118a. A second set of vias1120bcouple the second capacitive plates1106,1110to a second set of cross-plate routing plates1116b,1118. In the illustrate embodiment, the first set of cross-plate routing plates1116a,1118aare alternated with the second set of cross-plate routing plates1116b,1118. It will be recognized that any suitable pattern of coupling the cross-plate routing plates1116,1118to the concentric capacitive plates1104-1110may be used.

In some embodiments, the first capacitive plates1104,1108are coupled to a first unidirectional metal1112to define negative capacitive plates, or C− plates, of the concentric capacitors1102a,1102b. The second capacitive plates1106,1110are coupled to a second unidirectional metal1114to define positive capacitive plates, or C+ plates, of the concentric capacitors1102a,1102b. It should be noted that the number of concentric capacitive structures1102a,1102bis only exemplary and embodiments according to the present disclosure can include more or less than the two concentric sets of capacitive plates depicted.

Each of the cross-plate routing plates1116,1118are coupled to at least one of the concentric capacitive plates1104-1110. In some embodiments, the cross-plate routing plates1116,1118extend from an outer capacitive plate1104to an inner capacitive plate1110. The cross-plate routing plates1116-1118may be coupled to multiple concentric capacitive plates1104-1110having the same polarity. For example, with reference toFIG. 11, a first set of the cross-plate routing plates1116a,1118aare coupled to each of the first concentric capacitive plates1104,1108(negative capacitive plates) and a second set of the cross-plate routing plates1116b,1118are coupled to each of the second concentric capacitive plates1106,1110(positive capacitive plates). In some embodiments, each of the cross-plate routing plates1116,1118are coupled to a single concentric capacitive plate1104-1110.

The cross-plate routing plates1116,1118provide an increased capacitance to the concentric capacitors1102a,1102b. The cross-plate routing plates1116-1118are coupled to the concentric capacitive plates1104-1110and will develop a charge when the concentric capacitive plates1104-1110are coupled to a signal. In some embodiments, a capacitive charge is developed between cross-plate routing plates1116-1118alternatively coupled to the positive and negative capacitive plates1104-1110.

In traditional concentric capacitor structures, the concentric capacitors have a ½ capacitance loss in each direction as compared to a concentric capacitive structure1100having the same layout area. In other words, traditional concentric capacitor structures or require four times the capacitive area to produce the same capacitance as the layout area of the concentric capacitive structure1100. The concentric capacitor structure1100provides a natural common-centroid placement, which reduces process variation and ensures coherent variations of the concentric capacitors1102a,1102b. The concentric capacitor structure1100is compatible with an unidirectional one-dimensional back end of the line (BEOL) process that can be used to manufacture a semiconductor structure, including the concentric capacitor structure1100

In some embodiments, the first routing layer1124ais separated from the second routing layer1124bby one or more insulators. For example, the first routing layer1124aand the second routing layer1124bmay be separated by an insulator such as, for example, interlayer dielectrics. The perimeter plates and/or the cross-plate routing plates1116,1118within each routing layer may be insulated from the other routing plates within the routing layer by an insulation material, such as, for example, intralayer dielectrics or other suitable insulators. In some embodiments, an air gap exists between the negative capacitive plates1104a,1106aand the positive capacitive plates1104b,1106bof the concentric capacitors1102a,1102b.

FIGS. 12-15illustrate one embodiment of a concentric capacitive structure1200.FIG. 12illustrates a top perspective view of the concentric capacitive structure1200. The concentric capacitive structure1200comprises four routing layers1202a-1202d(seeFIG. 13). Each of the routing layers1224a-1224dcomprise a set of perimeter routing plates and a set of cross-plate routing plates. The perimeter routing plates of the routing layers1202a-1202ddefine a plurality of concentric capacitors1202a,1202b. Each of the concentric capacitors1202a,1202bcomprise a first concentric plate1204,1208and a second concentric plate1206,1210. Each of the concentric capacitor plates1204-1210comprise a first set of perimeter plates1204a-1210dand a second set of symmetrical perimeter plates1234a-1240d. The first set of perimeter plates1204a-1210dare formed in the first and second routing layers1224a,1224band the second set of symmetrical perimeter plates1234a-1240dare formed in the third and fourth routing layers1224c,1224d. In some embodiments, the first concentric plates1204,1208comprise negative capacitive plates, C−, and the second concentric plates1206,1210comprise positive capacitive plates, C+. As used herein, reference numbers1204-1210, without sub-letters, are used to refer to a complete concentric capacitive plate comprising multiple layers of concentrically arranged perimeter plates (e.g., perimeter plates in all four layers). Reference numbers1204a-1210dand1234a-1240dare used to refer to individual plates, formed in a specific routing layer, of each of the concentric capacitive plates that form the complete concentric capacitive plate.

The first set of concentric capacitive plates1204-1210each comprise a layer of perimeter plates comprising a first set of perimeter plates1204a-1210a,1204c-1210cformed in the first routing layer1224aand a second set of perimeter plates1204b-1210b,1204d-1210dformed in the second routing layer1224b. The first set of perimeter plates1204a-1210a,1204c-1210cand the second set of perimeter plates1204b-1210b,1204d-1210doverlap at the edges of the respective plates and are joined by a plurality of interlayer vias1226a,1226bto define concentric capacitive plates1204-1210. The first set of concentric capacitive plates1204-1210are similar to the concentric capacitive plates1104-1110discussed with respect toFIGS. 11-11C.

A second layer of perimeter plates are symmetrically disposed over the first layer of perimeter plates1204a-1210d. The second set of perimeter plates comprise a first set of perimeter plates1234a-1240a,1234c-1240cformed in the third routing layer1224cand a second set of perimeter plates1234b-1240b,1234d-1240dformed in the fourth routing layer1224d. The first set of perimeter plates1234a-1240a,1234c-1240cand the second set of perimeter plates1234b-1240b,1234d-1240doverlap at the edges of the respective plates and are joined by a plurality of interlayer vias1242,1242b. The second layer of perimeter plates1234a-1240dare symmetrically sized and arranged with respect to the first layer of perimeter plates1204a-1210d. The first layer of perimeter plates1204a-1210dare coupled to the second layer of perimeter plates1234a-1240dby a plurality of inter-plate vias1244to define concentric capacitive plates1204-1210.

The concentric capacitive plates1204-1210define a capacitive area in a third direction. The number layers having perimeter plates and/or cross-plates may be selected to provide a specific capacitance for each of the concentric capacitors1202a,1202b. For example, adding additional routing layers having additional perimeter plates and/or cross-plate routing plates increases the individual capacitance of each of the concentric capacitors1202a,1202bwithout increasing the lateral footprint of the concentric structure1200. Similarly, having fewer routing layers decreases the capacitance of each of the concentric capacitors1202a,1202b.

The first concentric capacitive plates1204,1208may be coupled to a first unidirectional metal1212and the second concentric capacitive plates1206,1210may be coupled to a second unidirectional metal1214. The first concentric capacitive plates1204,1208may comprise positive capacitive plates, C+, and the second concentric capacitive plates1206,1210may comprise negative capacitive plates, C−. It will be recognized that the plurality of the first concentric capacitive plates1204,1208and the second concentric capacitive plates1206,1210may be reversed. In some embodiments, each of the first concentric capacitive plates1204,1208are coupled to one or more switches (not shown) to selectively couple the concentric capacitors1202a,1202bto a signal source.

Each of the concentric capacitors1202a,1202bcomprise a plurality of cross-plate routing plates1216,1218,1246,1248. The cross-plate routing plates1216,1218,1246,1258extend from a first concentric capacitive plate1204,1208to a second concentric capacitive plate1206,1210. The cross-plate routing plates1216,1218,1246,1248are similar to the cross-plate routing plates1116-1118discussed with respect toFIGS. 11-11C. The cross-plate routing plates1216,1218,1246,1248are formed in opposite routing layers from routing layer of the overlapping perimeter plates. For example, as illustrated inFIG. 13, a first set of perimeter plates1204a,1204cand a second set of perimeter plates1206a,1206care formed in a first routing layer1224a. A first set of cross-plate routing plates1216a,1216b, which overlap the first concentric capacitive plate1204and the second concentric capacitive plate1206, are formed in a second routing layer1224b. Similarly, a third set of perimeter plates1234a,1234cand a fourth set of perimeter plates1236a,1236care formed in a third routing layer1224c. A second set of cross-plate routing plates1246a,1246b, which overlap the first concentric capacitive plate1204and the second concentric capacitive plate1206, are formed in a fourth routing layer1224d.

The cross-routing plates1216,1218,1246,1248extend longitudinally in a direction orthogonal to the longitudinal axis of the overlapping perimeter plates. For example, as shown inFIG. 13, first perimeter plates1204a,1234aof the first concentric capacitive plate1204are formed in the first routing layer1224aand the third routing layer1224crespectively. The first perimeter plates1204a,1234aextend longitudinally in a first direction. A plurality over cross-plate routing plates1216,1246are formed in the second routing layer1224band the fourth routing layer1224drespectively. Each of the plurality of cross-plate routing plates1216,1246extend longitudinally in a second direction, orthogonal to the first direction. The cross-plate routing plates1216,1246are coupled to the first perimeter plates1204a,1234aby a plurality of vias1220.

Each of the routing layers1224a-1224dcomprises metal routing plates extending in a single longitudinal direction. For example, the first routing layer1224acomprises a set of perimeter plates1204a-1210a,1204c-1210cand a plurality of cross-plate routing plates1218. Each of the perimeter plates1204a-1210a,1204c-1210cand each of the plurality of cross-plate routing plates1218extend in a first longitudinal direction. Similarly, the second routing layer1224bcomprises a set of perimeter plates1204b-1210b,1204d-1210dand a plurality of cross-plate routing plates1216. Each of the perimeter plates1204b-1210b,1204d-1210dand each of the cross-plate routing plates1216extend in a second longitudinal direction. The third routing layer1224cand the fourth routing layer1224dcomprise metal routing plates similar to respective first and second routing layers1224a,1224b.

The cross-plate routing plates1216,1218,1246,1248increase the capacitance of the concentric capacitive plates1204-1210. In some embodiments, a first set of the cross-plate routing plates1216a,1218a,1246a,1248aare coupled to the first concentric capacitive plates1204,1208and a second set of the cross-plate routing plates1216b,1218b,1246b,1248bare coupled to the second concentric capacitive plates1206,1210. In some embodiments the first concentric capacitive plates1204,1208and the cross-plate routing plates1216a,1218a,1246a,1248acoupled thereto define respective negative capacitive plates, C− plates, of the concentric capacitors1202a,1202band the second concentric capacitive plates1206,1210and the cross-plate routing plates1216b,1218b,1246b,1248bcoupled thereto define respective positive capacitive plates, C+ plates, of the concentric capacitors1202a,1202b. For example, a plate set1260illustrates a first cross-plate1262and a second cross-plate1264. The first cross-plate is coupled to the concentric capacitive plate1204and the second cross-plate1264is coupled to the concentric capacitive plate1206. When a signal is applied to the concentric capacitor1202a, a capacitive charge develops between the first cross-plate1262and the second cross-plate1264. The capacitive charge developed in the plate set1260increases the total capacitance of the concentric capacitor1202a.

The concentric capacitive structure1200may be coupled to a switch to selectively couple the concentric capacitors1224a,1224bto a signal source. For example, in some embodiments, the negative concentric capacitive plates1204,1208are coupled to at least one switch. The at least one switch selectively couples the first concentric capacitor1202aand/or the second concentric capacitor1202bto a signal source. When a negative concentric plate of a capacitor, such as, for example, the negative concentric plate1204of the first concentric capacitor1202a, is coupled to a signal source, a capacitance is developed between the negative concentric plate1204and the positive concentric plate1206of the first concentric capacitor1202a. The positive concentric plate1206of the first concentric capacitor1202aand the positive concentric plate1210of the second concentric capacitor1202bare both coupled to the unidirectional metal1226. Therefore, some charge will flow to the positive concentric plate1210of the second concentric capacitor1202bwhen the first concentric capacitor1202ais coupled to a signal source (and conversely from the second capacitor1202bto the first capacitor1202awhen the second capacitor1202bis energized). However, the gap between the first concentric capacitor1202aand the second concentric capacitor1202bis such that any capacitance developed therebetween can be ignored.

FIG. 16illustrates a differential capacitive structure1300comprising a first concentric capacitor bank1302aand a second concentric capacitor bank1302b. The first concentric capacitor bank1302acomprises a first concentric capacitor1304aand a second concentric capacitor1304b. The second concentric capacitor bank1302bcomprises a first concentric capacitor1306aand a second concentric capacitor1306b. Each of the concentric capacitive structures1304a-1306bare formed according to the embodiments of concentric capacitors disclosed herein in reference toFIGS. 11-15, and the similar features and construction are not repeated herein.

A first plate of each of the concentric capacitors1304a,1304bof the first capacitor bank1302aare coupled to a first unidirectional metal1318. A second plate of each of the concentric capacitors1304a,1304bare coupled to switches1322a,1322bby a second unidirectional metal1324a,1324b. A first plate of each of the concentric capacitors1306a,1306bof the second capacitor bank1302bare coupled to a first unidirectional metal1326. A second plate of each of the concentric capacitors1306a,1306bare coupled to switches1322a,1322by a second unidirectional metal1328a,1328b. The switches1322a,1322bare configured to selectively couple each of the concentric capacitors1304a-1306bto a signal source (not shown). In some embodiments, the switches1322a,1322bare combined into a single switch, such as, for example, the switch120illustrated inFIGS. 2A-2B. The switches1322a,1322bare configured to selectively couple each of the concentric capacitors1304a-1306b, or any combination thereof, to a signal source.

In the illustrated embodiment, the first concentric capacitive structure1302aand the second concentric capacitive structure1302bare identical. The resolution of the differential capacitive structure1300is determined by the capacitive difference between the first concentric capacitors1304a,1306aand the second concentric capacitors1304b,1306b. In some embodiments, the change in capacitance, ΔC, is equal to Con−Coff, where Concomprises the concentric capacitors coupled to a signal source and Coffcomprises the capacitors disconnected from the signal source.

FIG. 17is a flowchart illustrating one embodiment of a method1400for forming a concentric capacitor structure. In a first step1402, a first plurality of capacitive perimeter plates is formed on a first routing layer of a semiconductor substrate. The first plurality of capacitive perimeter plates extend longitudinally in a first direction. In a second step1404, a second plurality of capacitive perimeter plates are formed on a second routing layer of the semiconductor substrate. The second plurality of capacitive perimeter plates extend in a second direction. The second direction may be orthogonal to the first direction. The first plurality and the second plurality of capacitive perimeter plates overlap at the edges of each of the capacitive perimeter plates to form a geometric shape, such as, for example, a square.

In a third step1406, a first set of the first plurality of capacitive perimeter plates are electrically coupled to a first set of the second plurality of capacitive perimeter plates to form an outer concentric capacitive plate and a second set of the first plurality of capacitive perimeter plates is electrically coupled to a second set of the second plurality of capacitive perimeter to form an inner concentric capacitive plate. The capacitive perimeter plates may be coupled by a plurality of interlayer vias located, for example, at the edges of the perimeter plates.

In a fifth step1408, a first plurality of capacitive cross-plates is formed on the first routing layer. The first plurality of capacitive cross-plates extend longitudinally in the first direction. The first plurality of capacitive cross plates are positioned such that each of the first plurality of capacitive cross-plates at least partially overlaps the second plurality of capacitive perimeter plates formed on the second routing layer. Each of the first plurality of capacitive cross-plates is electrically to at least one of the second plurality of capacitive perimeter plates. The capacitive cross-plates may be alternatively coupled to the inner and outer concentric capacitive plates. In some embodiments, a second plurality of capacitive cross-plates are formed in the second routing layer. The second plurality of capacitive cross-plates extend longitudinally in the second direction. Each of the second plurality of capacitive cross-plates at least partially overlap the first plurality of capacitive perimeter plates formed in the first routing layer. Each of the second plurality of capacitive cross-plates is electrically to at least one of the first plurality of capacitive perimeter plates. For example, in some embodiments, the capacitive cross-plates are alternatively coupled to the inner and outer concentric capacitive plates. The capacitive cross-plates may be coupled to the perimeter plates by a plurality of interlayer vias.

One of the broader forms of the present disclosure provides a capacitor structure having a semiconductor substrate and a matrix of capacitor units formed over the semiconductor substrate each capacitor unit. Any number of units, 2, 4, 6, 8, and so forth can be included in an exemplary matrix. The matrix includes an interior structure comprised of one or more vertical plates, each vertical plate of the interior structure formed from a plurality of conductive portions connected vertically to each other. Exemplary interior structures can be, but are not limited to, an H-shaped structure, an I-shaped structure, a vertical post, or combinations thereof. The matrix also includes an exterior structure comprised of one or more vertical plates, each vertical plate of the exterior structure formed from a plurality of conductive portions connected vertically to each other, the exterior structure substantially encompassing the interior structure. The exterior structure can be electrically connected to a signal line. In some embodiments, the exterior structures of adjacent capacitor units are electrically connected to each other. The matrix further includes insulative material separating the interior and exterior structures. The capacitor structure also provides a switching mechanism included in the capacitor structure to switch between ones of the plural capacitor units. In various embodiments, each interior structure within the matrix can be electrically connected to a ground node of the switching mechanism. In other embodiments, plural interior structures within the matrix can be connected to different ground nodes of the switching mechanism. Exemplary switching mechanisms can be, but are not limited to, MOSFETs, diodes, BJTs, a PN transistor, an NP transistor, an NPN transistor, a PNP transistor, or combinations thereof. In another embodiment of the present disclosure the capacitor structure can include one or more additional structures, each partially or completely encompassing the matrix of capacitor units. In certain embodiments, adjacent additional structures are alternately electrically connected to signal and ground nodes to thereby change capacitive characteristics of the capacitor structure. In a further embodiment of the present disclosure, the exterior structure further comprises a first set of one or more vertical plates substantially encompassing half of the interior structure, and a second set of one or more vertical plates substantially encompassing an opposing half of the interior structure, each vertical plate of the first and second sets formed from a plurality of conductive portions connected vertically to each other in the respective sets. In this embodiment, the first set is electrically connected to a first signal line, and the second set is electrically connected to a second signal line.

Other broad forms of the present disclosure provide a capacitor structure having a semiconductor substrate and a grid of capacitor elements formed over the semiconductor substrate each capacitor element having a first structure electrically connected to a signal line and a second structure electrically connected to a ground line of a switching mechanism included in the capacitor structure to switch between ones of the capacitor elements in the grid. Any number of elements, 2, 4, 6, 8, and so forth can be included in an exemplary grid. The capacitor structure also includes insulative material separating the first and second structures. In some embodiments, the first structure substantially encompasses one or more second structures. For example, exemplary second structures can be, but are not limited to, an H-shaped structure, an I-shaped structure, a vertical post, or combinations thereof. In additional embodiments, plural second structures within the grid are connected to different ground lines of the switching mechanism. Exemplary switching mechanisms can be, but are not limited to, MOSFETs, diodes, BJTs, a PN transistor, an NP transistor, an NPN transistor, a PNP transistor, or combinations thereof. Another embodiment of the present disclosure further comprises one or more additional structures, each partially or completely encompassing the grid of capacitor elements. One such embodiment includes adjacent additional structures that are alternately electrically connected to signal and ground lines to thereby change the capacitance of the capacitor structure. A further embodiment of the present disclosure provides a first structure having a first set of one or more vertical plates substantially encompassing half of a second structure and a second set of one or more vertical plates substantially encompassing an opposing half of the second structure, each vertical plate of the first and second sets formed from a plurality of conductive portions connected vertically to each other in the respective sets. In this embodiment, the first set is electrically connected to a first signal line, and the second set is electrically connected to a second signal line. In an additional embodiment of the present disclosure, the first structure is a first set of interdigital fingers electrically connected to each other and the second structure is a second set of interdigital fingers electrically connected to each other.

An additional embodiment of the present disclosure provides a method of forming an integrated capacitor structure comprising the steps of providing a semiconductor substrate and forming a grid of capacitor elements over the semiconductor substrate each capacitor element having a first structure electrically connected to a signal line and a second structure electrically connected to a ground line of a switching mechanism included in the capacitor structure to switch between ones of the capacitor elements in the grid. The method also comprises providing insulative material separating the first and second structures.

Other broad forms of the present disclosure provide a concentric capacitor structure. The concentric capacitor structure comprises a semiconductor substrate having a first routing layer and a second routing layer. At least one concentric capacitor is formed on the semiconductor substrate. Each of the at least one concentric capacitors comprise a first plurality of capacitive perimeter plates formed on the first routing layer and a second plurality of capacitive perimeter plates formed on the second routing layer. The first plurality of capacitive perimeter plates extend in a first direction. The second plurality of capacitive perimeter plates extend in a second direction. The second direction is different than the first direction. A first set of the first plurality of capacitive perimeter plates are electrically coupled to a first set of the second plurality capacitive perimeter plates. The first set of the first and second pluralities of capacitive perimeter plates define an outer concentric capacitive plate. A second set of the first plurality of capacitive perimeter plates is electrically coupled to a second set of the second plurality of capacitive perimeter plates. The second set of the first and second pluralities of r capacitive perimeter plates define an inner concentric capacitive plate. A first plurality of capacitive cross-plates are formed on the first routing layer. The first plurality of capacitive cross-plates extend longitudinally in the first direction. Each of the first plurality of capacitive cross-plates overlap at least two of the second plurality of capacitive perimeter plates formed in the second routing layer. Each of the first plurality of capacitive cross-plates are electrically coupled to at least one of the second plurality of capacitive perimeter plates.

Other broad forms of the present disclosure provide a differential capacitive structure. The differential capacitive structure comprises a semiconductor substrate, a first concentric capacitor bank, a second concentric capacitor bank, and a switching mechanism. The semiconductor substrate comprises a first routing layer and a second routing layer. Each of the concentric capacitor banks comprise a first plurality of capacitive perimeter plates formed on the first routing layer and a second plurality of capacitive perimeter plates formed on the second routing layer. The first plurality of capacitive perimeter plates extend in a first direction. The second plurality of capacitive perimeter plates extend in a second direction. The second direction is different than the first direction. A first set of the first plurality of capacitive perimeter plates are electrically coupled to a first set of the second plurality capacitive perimeter plates. The first set of the first and second pluralities of capacitive perimeter plates define an outer concentric capacitive plate. A second set of the first plurality of capacitive perimeter plates are electrically coupled to a second set of the second plurality of capacitive perimeter plates. The second set of the first and second pluralities of capacitive perimeter plates define an inner concentric capacitive plate. A first plurality of capacitive cross-plates are formed on the first routing layer. The first plurality of capacitive cross-plates extend longitudinally in the first direction. Each of the first plurality of capacitive cross-plates overlap at least two of the second plurality of capacitive perimeter plates formed in the second routing layer. Each of the first plurality of capacitive cross-plates are electrically coupled to at least one of the second plurality of capacitive perimeter plates. The switching mechanism is configured to selectively couple the outer concentric capacitive plates to a signal source.

An additional embodiment of the present disclosure provides a method for forming a concentric capacitor structure. The method comprises the steps of forming a first plurality of capacitive perimeter plates on a first routing layer of a semiconductor substrate; forming a second plurality of capacitive perimeter plates on a second routing layer of the semiconductor substrate; electrically coupling a first set of the first plurality of capacitive perimeter plates to a first set of the second plurality of capacitive perimeter plates to form a plurality of outer concentric capacitive plates; electrically coupling a second set of the first plurality of capacitive perimeter plates to a second set of the second plurality of capacitive perimeter plates to form a plurality of inner concentric capacitive plates; forming a first plurality of capacitive cross-plates on the first routing layer; and electrically coupling each of the first plurality of capacitive cross-plates to at least one of the second plurality of capacitive perimeter plates. The first plurality of capacitive cross-plates extend longitudinally in the first direction. Each of the first plurality of capacitive cross-plates at least partially overlap the second plurality of capacitive perimeter plates formed on the second routing layer. The first plurality of capacitive perimeter plates extend in a first direction and the second plurality of capacitive perimeter plates extend in a second direction. The first direction is different than the second direction.

Embodiments of the present disclosure thus described provide higher Q values than conventional capacitor elements, provide for no local variation due to a lack of process variation within the same capacitor structure when switching, and provide tunable or compensable capacitances for a respective capacitor. Additionally, exemplary embodiments can provide varying parasitic capacitances for diodes when the biasing is changed, e.g., if the diode is forward biased then no parasitic capacitance is provided.

Embodiments of the present disclosure thus described provide an enhanced capacitance density compared to traditional concentric capacitor structures without increasing the layout area. Additionally, exemplary embodiments provide coherent variation between concentric capacitor plates defined by the concentric orthogonal metal routing plates and do not impact unidirectional, one-dimensional BEOL processes used for manufacture of semiconductor structures.

It can be emphasized that the above-described embodiments, particularly any “preferred” embodiments, are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the disclosure. Many variations and modifications can be made to the above-described embodiments of the disclosure without departing substantially from the spirit and principles of the disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure and the present disclosure and protected by the following claims.

As shown by the various configurations and embodiments illustrated inFIGS. 1-16, various switched capacitor structures have been described.