Temperature-insensitive bias circuit for high-power amplifiers

An exemplary bias circuit is coupled to an amplifier. The bias circuit comprises a first bipolar transistor, a second bipolar transistor and a third bipolar transistor. The first bipolar transistor has a base connected to a first node, and the first node is connected to a reference voltage through a first resistor. The second bipolar transistor has a base connected to the first node. The third bipolar transistor has a collector connected to the first node and a base connected to an emitter of the first bipolar transistor at a second node. An emitter of the second bipolar transistor is connected to a base of a fourth bipolar transistor associated with the amplifier, and the second bipolar transistor does not have a resistor connected to the emitter of the second bipolar transistor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention is generally in the field of semiconductors. More specifically, the invention is in the field of semiconductor circuits.

2. Related Art

Amplifiers based on bipolar technology are widely used in a variety of applications, including wireless communication, such as radio frequency (“RF”) communication, for example. Bias circuits perform an important function by supplying the base bias current to the bipolar transistor for controlling the operation modes of the bipolar transistor.

Currently known bias circuits for bipolar transistors, however, include a number of disadvantages. In general, known bias circuits consume large current and require a high reference voltage, or otherwise comprise very complex circuits which consume large die area, all of which are undesirable. Moreover, known bias circuits generally suffer from being temperature sensitive such that the quiescent current of the amplifier's transistor is subject to temperature variations.

Accordingly, there is a strong need in the art for an area efficient, temperature-insensitive bias circuit for high-power amplifiers.

SUMMARY OF THE INVENTION

The present invention is directed to an area efficient, temperature-insensitive bias circuit for high-power amplifiers, in one exemplary embodiment, a bias circuit is coupled to an amplifier, such as an RF amplifier, and comprises a first bipolar transistor, a second bipolar transistor and a third bipolar transistor. The first bipolar transistor has a base connected to a first node, and the first node is connected to a reference voltage through a first resistor. The second bipolar transistor has a base connected to the first node. The third bipolar transistor has a coilector connected to the first node and a base connected to an emitter of the first bipolar transistor at a second node. An emitter of the second bipolar transistor is connected to a base of a fourth bipolar transistor associated with the amplifier, and the second bipolar transistor does not have a resistor connected to the emitter of the second bipolar transistor.

As a result of the above arrangement, an emitter size ratio of the first bipolar transistor to the second bipolar transistor is independent of an emitter size ratio of the third bipolar transistor to the fourth bipolar transistor, thereby allowing the die area consumed by the transistors of the bias circuit to be significantly reduced.

In one embodiment, the bias circuit further comprises a control circuit connected to the second node, wherein the control circuit draws an increased current during a high mode operation and draws a reduced current during a low mode operation. For example, the control circuit may have a reduced resistance during the high mode operation and an increased resistance during the low mode operation. According to one particular embodiment, the control circuit comprises a fifth bipolar transistor having a collector connected to the second node through a second resistor and to ground through a third resistor. An emitter of the fifth bipolar transistor is coupled to ground, and a base of the fifth bipolar transistor is connected to a control voltage through a fourth resistor. As discussed below, this particular arrangement results in an amplifier quiescent current which is significantly insensitive to temperature variations.

According to another embodiment, the bias circuit further comprises a high-temperature gain compensation circuit connected in parallel with the first resistor and is configured to draw current at high temperatures. According to one particular embodiment, the high-temperature gain compensation circuit comprises a second resistor and a Schottky diode, wherein a first end of the second resistor is connected to the reference voltage, a second end of the second resistor is connected to an anode of the Schottky diode, and a cathode of the Schottky diode is connected to the first node. As discussed below, this particular arrangement provides compensation for amplifier gain drop during high temperatures.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is directed to an area efficient, temperature-insensitive bias circuit for high-power amplifiers. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention. The specific details not described in the present application are within the knowledge of a person of ordinary skill in the art.

To illustrate the features and advantages of the present invention by way of contrast, a brief description of known bias circuit100inFIG. 1is provided. Referring toFIG. 1, there is shown a circuit diagram depicting known bias circuit100coupled to amplifier102. Known bias circuit100includes bipolar transistors104,106and108, resistors116,118and120, and control circuit114.

One end of resistor116is connected to reference voltage (“Vref”)128, and the other end of resistor116is connected to node126. The base of transistor104, the base of transistor106and the collector of transistor108are coupled to node126. The emitter of transistor104is connected to the base of transistor108and to ground138at node136through resistor118. The emitter of transistor108is also connected to ground138at node136. The emitter of transistor106at node140is also coupled to ground138through shunt resistor120.

Amplifier102includes bipolar transistor110having a base coupled to node140of known bias circuit100, and an emitter coupled to ground138. Control circuit114includes bipolar transistor112having a collector coupled to node126through resistor122. The base of transistor112is coupled to control voltage (“Vcont”)144through resistor124, and the emitter of transistor112coupled to ground138at node136. Nodes130,132and134may be connected to a bias voltage or may be directly connected to a supply voltage (“VCC”), as is known in the art.

With the arrangement as shown inFIG. 1, collector current150of transistor110represents the quiescent current (“Icq”) of transistor110. In order to produce collector current150having a magnitude N times that of collector current152of transistor108, the ratios between the following elements are required: the emitter size of transistor106is N times larger than the emitter size of transistor104; the emitter size of transistor110is N times larger than the emitter size of transistor108; the value of resistor118is N times greater than the value of resistor120, where N is an arbitrary integer. As a result, the magnitude of collector current162of transistor106will be N times the magnitude of collector current160of transistor104, and the magnitude of collector current150of transistor110will be N times the magnitude of collector current152of transistor108.

However, a number of disadvantages are associated with bias circuit100. High power devices necessitate a large N value, thereby requiring the emitter size of transistor106to be substantially large in order to maintain a size N times greater than the emitter size of transistor104. As a consequence, large die area is consumed by transistor106, which is undesirable for many applications. On the other hand, if the emitter size ratio of transistor108to transistor110were decreased in order to reduce the die area consumed by transistor108, large reference current (“Iref”)154is drawn through resistor116as a result of large collector current152drawn by transistor108, resulting in significant power consumption trade-off as a result of reducing the size of transistor108. As is known in the art, a high Iref is undesirable.

Continuing withFIG. 1, control circuit114can be configured to control bias circuit100for low output power mode by supplying Vcont144to turn on transistor112. During this low output power mode, current168is drawn by transistor112, and voltage at node126is decreased, thereby reducing collector current152drawn by transistor108. As a consequence of reducing collector current152from Iref154, the temperature tracking capability of bias circuit100is significantly reduced, and consequently Icq150become sensitive to variations in temperature, which as discussed above, is undesirable.

Referring now toFIG. 2, there is shown exemplary bias circuit200in accordance with one embodiment of the present invention. InFIG. 2, bias circuit200is shown coupled to amplifier202, which may be employed in a number of applications, such as RF communication, for example. As discussed in greater detail below, bias circuit200results in significantly reduced Vref228and Iref254while generating Icq250which is largely insensitive to temperature variations. Moreover, due to the particular arrangement of bias circuit200, the die area consumed by bias circuit200is significantly reduced.

InFIG. 2, bias circuit200comprises bipolar transistors204,206and208, resistor216, control circuit214and high-temperature gain compensation circuit280. Reference Voltage (“Vref”)228is supplied to node227of bias circuit200, and resistor216is connected across nodes226and227. As shown inFIG. 2, high-temperature gain compensation circuit280is connected in parallel with resistor216across nodes226and227. More particularly, one end of resistor270is connected to node276and the other end of resistor270is connected to the anode of Schottky diode272. The cathode of Schottky diode272is connected to node226.

The base of transistor204, the base of transistor206and the collector of transistor208are coupled to node226. The emitter of transistor208is connected to ground238at node236, and the emitter of transistor206is connected to amplifier202at node240, and is not connected to ground through a shunt resistor. The emitter of transistor204is coupled at node242to the base of transistor208and to control circuit214. Control circuit214comprises transistor212and resistors222,224and274, where the collector at node237of transistor212is connected to node242through resistor222, the emitter of transistor212is connected to ground238at node236, and the base of transistor212is coupled to control voltage (“Vcont”)244through resistor224. Resistor274of control circuit214is also connected across nodes236and237as shown in FIG.2.

Amplifier202includes bipolar transistor210, which may be a high-power transistor, having a base coupled to node240of bias circuit200, and an emitter coupled to ground238. Nodes230,232and234may be connected to a bias voltage or may be directly connected to VCC.

Since a shunt resistor is not connected between the emitter of transistor206and ground238, the size of transistor206can be reduced. In operation, transistor204can be represented by transistors305and307in circuit block304ofFIG. 3, where nodes330and342respectively correspond to nodes230and242in FIG.2. Accordingly, resistor222and/or resistor274of control circuit214may be used to dissipate current from transistor305, which is a virtually divided part of transistor204. With this arrangement, an arbitrary emitter size ratio of transistor204to transistor206can be achieved while maintaining a 1:N emitter size ratio of transistor208to transistor210, thereby allowing the emitter area of transistor206to be further reduced. The ratios between the following elements are provided by the arrangement of bias circuit200: the emitter size of transistor210is N times larger than the emitter size of transistor208; the emitter size of transistor204: the emitter size of transistor305: the emitter size of transistor307: the emitter size of transistor206is equal to 1: (N−M)/N:M/N:M, where M is a number less than N and does not have to be an integer. For Icq250to be N times collector current252of transistor208, a value “R2” defined by Equation 1 can be used to represent the effective resistance of control circuit214and is defined by the following formula:R2=M·Vt·n3·ln⁡(Ib3Is3)Ib3·(N-M)Equation⁢⁢1

where n3 is an ideality factor of forward base current for transistor208, Is3 is a reverse saturation current of transistor208, and Ib3 is base current276of transistor208given by the following formula:Ib3=Is3·exp⁡(Vbe3n3·Vt)Equation⁢⁢2

where Vbe3 is the base-to-emitter voltage of transistor208.

With this arrangement, collector current262of transistor206is M times greater than collector current260of transistor204, and collector current250of transistor210is N times greater than collector current252of transistor208. As discussed above, the particular arrangement of bias circuit200allows the emitter size ratio of transistors208to transistor210to be independent from the emitter size ratio of transistors204to transistor206, therefore allowing the overall area of the bias transistors204,206and208to be reduced.

Another advantage of bias circuit200is that Iref254can be significantly reduced while achieving a reduced size of transistor206, and without a shunt resistor connected between the emitter of transistor206and ground238. As a further benefit of reduced Iref254, Vref228is also reduced since voltage drop across resistor216is lowered by reduced Iref254.

Control circuit214can be configured for “high mode” operation or “low mode” operation. Vcont244provides a high signal to activate transistor212for high mode operation or a low signal to disable transistor212for low mode operation. In high mode operation, transistor212is turned on, and the resistance of control circuit214is reduced and corresponds to the resistance of resistor222. Due to the reduced resistance of, and the corresponding increased current drawn by, control circuit214, base current276available for the base of transistor208is reduced which in turn causes collector current252of transistor208to decrease. Decreased collector current252of transistor208results in an increase in the respective base currents of transistors206and210and thus results in an increased Icq250.

In low mode operation, transistor212is turned off, and the resistance of control circuit214is increased and corresponds to the total resistance of resistors222and274. Due to the increased resistance of, and the corresponding decreased current drawn by, control circuit214, base current276available for the base of transistor208is increased which in turn causes collector current252of transistor208to increase. Increased collector current252of transistor208results in a decrease in the respective base currents of transistors206and210and thus results in a reduced Icq250.

Thus, although transitions between low mode operation and high mode operation can break the 1:N ratio of collector current252of transistor208to collector current250of transistor210, current250is still tracked by current252with a certain ratio. Therefore, quiescent current variation with temperature caused by operation mode control can be significantly suppressed.

With reference to graph400ofFIG. 4, graph400illustrates quiescent current variations over temperature achieved by bias circuits according to various embodiments. For example, curve402illustrates the quiescent current variation over temperature of known bias circuit100. Since curve402has a steep slope, Icq of known bias circuit100exhibits high sensitivity to temperature variations. Curve404illustrates the quiescent current variation over temperature of known bias circuit200without high temperature gain compensation circuit280, and curve406illustrates the quiescent current variation over temperature of known bias circuit200with high temperature gain compensation circuit280. Curves404and406, each of which has a relatively flat slope, corresponds to Icq of known bias circuit200being substantially insensitive to temperature variations.

Curve406illustrates that high temperature gain compensation circuit280of bias circuit200provides compensation for gain drop at high temperatures. At high temperatures, transistor208consumes larger current, which causes a voltage drop at node226. As the voltage difference between Vref228and the voltage at node226become larger, Schottky diode272gradually turns on drawing current278, which increases Iref254. As a result of increased Iref254, Icq250of transistor210is also increased, thereby providing enhanced power gain of amplifier202.

FIG. 5illustrate alternative control circuit514which may be used to replace control circuit214ofFIG. 2according to one embodiment, such that Vcont544provides a high signal for low mode operation and a low signal for high mode operation. Control circuit514comprises transistors512and582, and resistors522,574,580and584, where transistor512, resistors522and574, and nodes542,537and536respectively correspond to transistor212, resistors222and274, and nodes242,237and236in FIG.2. The collector of transistor282is connected at node586to the base of transistor512, and the emitter of transistor282is coupled to ground538at node536. Resistor580is connected across nodes588and586, where node588may be connected to a bias voltage or may be directly connected to VCC. The base of transistor582is coupled to Vcont544through resistor584, such than transistor582is turned on and transistor512is turned off during low mode operation, and transistor582is turned off and transistor512is turned on during high mode operation.

From the above description of exemplary embodiments of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skill in the art would recognize that changes could be made in form and detail without departing from the spirit and the scope of the invention. The described exemplary embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular exemplary embodiments described herein, but is capable of many rearrangements, modifications, and substitutions without departing from the scope of the invention.

Thus, an area efficient, temperature-insensitive bias circuit for high-power amplifiers has been described.