Digital-to-analog conversion apparatus and method having signal calibration mechanism

The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism. A DAC circuit includes conversion circuits to generate an output analog signal and an echo-canceling analog signal. An echo transmission circuit performs signal processing on an echo path to generate an echo signal. An echo calibration circuit includes odd and even calibration circuits to perform mapping according to offset tables and perform processing according to response coefficients on odd and even input parts of an input digital signal to generate odd and even calibration parts of an echo-canceling calibration signal. A calibration parameter calculation circuit generates offsets according to an error signal between the echo signal and the echo-canceling calibration signal and path information related to the echo calibration circuit. The echo calibration circuit makes the coefficients converge according to the error signal and pseudo noise transmission path information, and updates the offset tables according to the offset.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a digital-to-analog conversion apparatus and a digital-to-analog conversion method having signal calibration mechanism.

2. Description of Related Art

A digital-to-analog conversion apparatus is an important circuit component to convert a signal from a digital form to an analog form. The digital-to-analog conversion apparatus multiply different digital codes by corresponding conversion gain values to generate analog signals having different intensities.

However, an error is generated in the digital-to-analog conversion apparatus due to offsets of current sources therein. Further, an echo is generated due to the mismatch of a transmission path that transmits the signal. Different calibration technologies are required for the digital-to-analog conversion apparatus to perform calibration on the input and output signals to accomplish a better conversion result.

SUMMARY OF THE INVENTION

In consideration of the problem of the prior art, an object of the present invention is to supply a digital-to-analog conversion apparatus and a digital-to-analog conversion method having signal calibration mechanism.

The present invention discloses a digital-to-analog conversion apparatus having signal calibration mechanism that includes a digital-to-analog conversion circuit, an echo transmission circuit, an echo calibration circuit and a calibration parameter calculation circuit. The digital-to-analog conversion circuit includes a plurality of conversion circuits operating at a first frequency to perform conversion according to a signal feeding related to an input digital signal having an input codeword to generate an output analog signal and an echo-canceling analog signal, wherein the echo-canceling analog signal at least performs output echo-canceling on the output analog signal at an echo path. The echo transmission circuit performs signal processing that includes down-sampling on the echo path to generate an echo signal having a second frequency, wherein the second frequency is a half of the first frequency. The echo calibration circuit includes an odd calibration circuit and an even calibration circuit operating at the second frequency and corresponding to the conversion circuits that generate the echo-canceling analog signal, wherein the odd calibration circuit and the even calibration circuit perform mapping according to a plurality of offset tables and perform processing according to a plurality groups of response coefficients on the signal feeding related to an odd input part and an even input part of the input digital signal respectively, to generate an odd calibration part and an even calibration part of an echo-canceling calibration signal. The calibration parameter calculation circuit operating at the second frequency generates a plurality offsets according to an error signal between the echo signal and the echo-canceling calibration signal and path information related to the echo calibration circuit, wherein the echo calibration circuit makes the groups of response coefficients converge according to the error signal and pseudo noise transmission path information from the digital-to-analog conversion circuit to the echo transmission circuit, and further updates the offset tables according to the offsets.

The present invention also discloses a digital-to-analog conversion method having signal calibration mechanism used in a digital-to-analog conversion apparatus that includes steps outlined below. Conversion is performed according to a signal feeding related to an input digital signal having an input codeword to generate an output analog signal and an echo-canceling analog signal by a digital-to-analog conversion circuit such that the echo-canceling analog signal at least performs output echo-canceling on the output analog signal at an echo path, wherein the digital-to-analog conversion circuit includes a plurality of conversion circuits operating at a first frequency. Signal processing that includes down-sampling is performed on the echo path to generate an echo signal having a second frequency by an echo transmission circuit, wherein the second frequency is a half of the first frequency. Mapping is performed according to a plurality of offset tables and processing is performed according to a plurality groups of response coefficients on the signal feeding related to an odd input part and an even input part of the input digital signal respectively by an echo calibration circuit, to generate an odd calibration part and an even calibration part of an echo-canceling calibration signal, wherein the echo calibration circuit comprises an odd calibration circuit and an even calibration circuit operating at the second frequency and corresponding to the conversion circuits that generate the echo-canceling analog signal. A plurality offsets are generated according to an error signal between the echo signal and the echo-canceling calibration signal and path information related to the echo calibration circuit by a calibration parameter calculation circuit operating at the second frequency. The groups of response coefficients are converged according to the error signal and pseudo noise transmission path information from the digital-to-analog conversion circuit to the echo transmission circuit and the offset tables are further updated according to the offsets by the echo calibration circuit.

These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art behind reading the following detailed description of the preferred embodiments that are illustrated in the various figures and drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An aspect of the present invention is to provide a digital-to-analog conversion apparatus and a digital-to-analog conversion method having signal calibration mechanism to generate an output analog signal and an echo-canceling analog signal having a first frequency and perform calibration thereon by using internal circuits that operate in a second frequency, which is a half of the first frequency according to an echo signal through down-sampling.

Reference is now made toFIG.1.FIG.1illustrates a circuit diagram of a digital-to-analog conversion apparatus100having signal calibration mechanism according to an embodiment of the present invention. The digital-to-analog conversion apparatus100includes a signal input circuit110, a digital-to-analog conversion circuit120(abbreviated as DAC inFIG.1), an echo transmission circuit130(abbreviated as ETC inFIG.1), an echo calibration circuit140(abbreviated as ECC inFIG.1) and a calibration parameter calculation circuit150(abbreviated as CPC inFIG.1).

The signal input circuit110performs signal feeding on the digital-to-analog conversion circuit120. The digital-to-analog conversion circuit120includes a plurality of conversion circuits operating at a first frequency, wherein the first frequency is such as, but not limited to 800 MHz. The digital-to-analog conversion circuit120performs digital-to-analog conversion according to a signal feeding related to an input digital signal IS having an input codeword to generate an output analog signal OD and an echo-canceling analog signal. The echo-canceling analog signal at least performs output echo-canceling on the output analog signal OD at an echo path EP.

The operation of the signal input circuit110and the digital-to-analog conversion circuit120is described in the following paragraphs in accompany withFIG.2andFIG.3.

FIG.2illustrates a more detailed block diagram of the signal input circuit110according to an embodiment of the present invention. The signal input circuit110includes an odd feeding circuit200, an even feeding circuit210an odd pseudo noise generation circuit220(abbreviated as OPN inFIG.2) and an even pseudo noise generation circuit230(abbreviated as EPN inFIG.2).

FIG.3illustrates a more detailed block diagram of the digital-to-analog conversion circuit120according to an embodiment of the present invention. The conversion circuits of the digital-to-analog conversion circuit120include an output conversion circuit300, an output echo-canceling conversion circuit310(abbreviated as OECC inFIG.3) and a pseudo noise conversion circuit320(abbreviated as PCC nFIG.3).

The odd feeding circuit200retrieves and outputs an odd input part ISO of the input digital signal IS. The even feeding circuit210retrieves and outputs an even input part ISE of the input digital signal IS. As a result, when the input digital signal IS has a first frequency, each of the odd input part ISO and the even input part ISE has a second frequency, in which the value of the second frequency is about the half of the value of the first frequency. Take the example of the value described above, the second frequency is 400 MHz under the condition that the first frequency is 800 MHz.

In an embodiment, the odd feeding circuit200and the even feeding circuit210receive the input digital signal IS from a signal source SS inFIG.1, which is such as a transmitter (TX) in a communication system. Further, each of the odd feeding circuit200and the even feeding circuit210can be implemented by a filter circuit to perform filtering on and output the odd input part ISO and the even input part ISE.

The output conversion circuit300receives and performs conversion on the odd input part ISO and the even input part ISE to generate the output analog signal OD. The output echo-canceling conversion circuit310also receives and performs conversion on the odd input part ISO and the even input part ISE to generate an output echo-canceling analog signal OEC included in the echo-canceling analog signal. The output analog signal OD is the signal actually transmitted to an external terminal. However, the output analog signal OD may be leaked to a receiver (RX, not illustrated in the figure) through the echo path EP inFIG.1. As a result, the output echo-canceling analog signal OEC performs echo-canceling on the output analog signal OD leaked to the echo path EP.

The odd pseudo noise generation circuit220generates and feeds an odd pseudo noise digital signal INO to the digital-to-analog conversion circuit120. The even pseudo noise generation circuit230generates and feeds an even pseudo noise digital signal INE to the digital-to-analog conversion circuit120. In an embodiment, each of the odd pseudo noise digital signal INO and the even pseudo noise digital signal INE is a random signal of 0 and 1 that simulates a noise.

The pseudo noise conversion circuit320receives and performs conversion on the odd pseudo noise digital signal INO and the even pseudo noise digital signal INE to generate a pseudo noise analog signal ON to the echo path EP. The generation of the odd pseudo noise digital signal INO and the even pseudo noise digital signal INE and the feedback of the pseudo noise analog signal ON are used to measure a response from the digital-to-analog conversion circuit120to the echo path EP.

In an embodiment, the digital-to-analog conversion circuit120further includes an adding circuit330that adds the analog signals described above and transmits the added result to the echo path EP inFIG.1to perform echo-canceling on the output analog signal OD leaked to the echo path EP.

The echo transmission circuit130inFIG.1performs signal processing that includes down-sampling on the echo path EP to generate an echo signal ES having a second frequency, wherein the second frequency is a half of the first frequency. The signal processing includes such as but not limited to echo response processing and analog-to-digital conversion performed based on down-sampling to generate the echo signal ES.

Each of the conversion circuits in the digital-to-analog conversion circuit120described above includes a plurality of current sources (not illustrated in the figure) to generate the analog signal according to the control of the corresponding signal feeding. The current sources include thermometer-controlled current sources and binary-controlled current sources each having a current offset such that the analog signal includes a static mismatch error.

The echo calibration circuit140cancels the static mismatch error generated from each of the conversion circuits. By using an odd calibration circuit and an even calibration circuit operating at the second frequency and corresponding to the conversion circuits that generate the echo-canceling analog signal included therein, the echo calibration circuit140performs mapping according to a plurality of offset tables and perform processing according to a plurality groups of response coefficients on the signal feeding related to an odd input part ISO and an even input part ISE of the input digital signal IS respectively, to generate an odd calibration part and an even calibration part of an echo-canceling calibration signal.

Further, the echo calibration circuit140further performs processing on the odd pseudo noise digital signal INO and the even pseudo noise digital signal INE according to a group of odd pseudo noise response parameters CCNO and a group of even pseudo noise response parameters CCNE (as illustrated inFIG.4) to generate an odd pseudo noise calibration signal ECNO and an even pseudo noise calibration signal ECNE.

FIG.4illustrates a more detailed block diagram of the echo calibration circuit140according to an embodiment of the present invention. The echo calibration circuit140includes an odd output echo-canceling calibration circuit400, an even output echo-canceling calibration circuit410, an odd pseudo noise calibration circuit420and an even pseudo noise calibration circuit430.

The odd output echo-canceling calibration circuit400includes a first mapping circuit440A and a first response circuit440B. The first mapping circuit440A receives and performs mapping on the odd input part ISO of the input digital signal IS according to a first offset table TB1 to generate a first mapped signal DS1. The first response circuit440B receives and performs processing on the first mapped signal DS1 according to a first group of response coefficients CC1 to generate an odd output echo-canceling calibration signal ECS1.

The even output echo-canceling calibration circuit410includes a second mapping circuit450A and a second response circuit450B. The second mapping circuit450A receives and performs mapping on the even input part ISE of the input digital signal IS according to a second offset table TB2 to generate a second mapped signal DS2. The second response circuit450B receives and performs processing on the second mapped signal DS2 according to a second group of response coefficients CC2 to generate an even output echo-canceling calibration signal ECS2.

In the mapping circuits described above, each of the offset tables includes a plurality of one-to-one corresponding relations between a plurality of codewords and a plurality of codeword offset values. The input codeword corresponds to one of the codewords in the first offset table TB1 and the second offset table TB2. In an initial status, all the codeword offset values are set to be 0.

The odd pseudo noise calibration circuit420receives and performs processing on the odd pseudo noise digital signal INO according to a group of odd pseudo noise response coefficients CCNO to generate the odd pseudo noise calibration signal ECNO. The even pseudo noise calibration circuit430receives and performs processing on the even pseudo noise digital signal INE according to a group of even pseudo noise response coefficients CCNE to generate the even pseudo noise calibration signal ECNE.

In an embodiment, the digital-to-analog conversion apparatus100inFIG.1further includes an error calculation circuit160to calculate an error signal DIS, which is a difference between the echo signal ES and a sum of the calibration signals described above (i.e., ECS1-ECS2, ECNO and ECNE).

In an embodiment, the digital-to-analog conversion apparatus100inFIG.1further includes a remained echo-canceling circuit170(abbreviated as REC inFIG.1) to perform echo-canceling on a remained echo. The remained echo-canceling circuit170includes a remained echo response circuit180(abbreviated as RER inFIG.1) and a canceling circuit190.

The remained echo response circuit180receives and performs processing on the input digital signal IS according to a group of remained echo response coefficients CCR to generate a remained echo-canceling signal ECR. The canceling circuit190performs subtraction on the remained echo-canceling signal ECR and the error signal DIS to generate a final error signal FDIS. The remained echo response circuit180makes group of remained echo response coefficients CCR converge according to the final error signal FDIS.

The calibration parameter calculation circuit150substantially generates the offsets according to the error signal DIS, which is a difference between the echo signal ES and a sum of the calibration signals described above (i.e., ECS1-ECS2, ECNO and ECNE), and path information related to the echo calibration circuit140. In an embodiment, the calibration parameter calculation circuit150substantially generates the offsets according to the final error signal FDIS after being processed by the remained echo-canceling circuit170.

In an embodiment, the path information includes the path delays DL1-DL2 of the response circuit (the first response circuit440B and second response circuit450B) to the calibration parameter calculation circuit150. Since the operation of these circuits takes time, the calibration parameter calculation circuit150needs to track the calculated offsets to the correct input codeword according to the path delays DL1-DL2.

In an embodiment, the calibration parameter calculation circuit150receives the first and the second groups of response coefficients CC1-CC2 of the first and the second response circuits440B-450B, performs one-dimensional inversion respectively on these response coefficients, multiplies the values of the final error signal FDIS by the inversed response coefficients and accumulates the multiplication results to generate corresponding inverted offsets values. According to the path delays DL1-DL2, the calibration parameter calculation circuit150further sets each of the inverted offset values to be the first and the second offsets DA1-DA2 corresponding to the first and the second mapping circuits440A-450A.

It is appreciated that the generation of the offset values described above is merely an example. In other embodiments, the calibration parameter calculating circuit150may generate the offset values by using other methods.

The echo calibration circuit140further performs training according to the final error signal FDIS and the pseudo-noise transmission path information from the digital-to-analog conversion circuit120to the echo transmission circuit130such that each of the groups of response coefficients converges to accomplish the object of performing calibration on the digital-to-analog conversion circuit120. The pseudo-noise transmission path information can be obtained according to the feeding of the odd pseudo noise digital signal INO and the even pseudo noise digital signal INE and the transmission of the pseudo-noise analog signal ON.

In order to avoid the interaction between the training objects, the digital-to-analog conversion apparatus100performs training having different stages.

In a first training stage, the output conversion circuit300and the pseudo noise conversion circuit320are enabled such that the odd pseudo noise calibration circuit420and the even pseudo noise calibration circuit430make the odd pseudo noise response coefficients CCNO and the even pseudo noise response coefficients CCNE converge according to the echo signal ES. The first response circuit440B and second response circuit450B set the converged odd pseudo noise response coefficients CCNO and the converged even pseudo noise response coefficients CCNE to be the first response coefficients CC1 and the second response coefficients CC2 respectively.

In a second training stage, the output echo-canceling conversion circuit310is further enabled to update the first offset table TB1 and the second offset table TB2 according to the first offset DA1 and the second offset DA2 in the offsets related to the odd output echo-canceling calibration circuit400and the even output echo-canceling calibration circuit410.

In an embodiment, the offset values of the current sources included in the output echo-canceling conversion circuit310have different combinations generated according to different combinations of the input codewords such that a mapping relation exists between the offset values of the current sources and the offset values of the input codewords. In the second training stage, the calibration parameter calculation circuit150distinguishes the offset values that the different input codeword corresponds to into a plurality of value groups according to an operation status of each of the current sources. The calibration parameter calculating circuit150further sets each of the current sources to be a target current source to further set a corresponding current offset value calculation formula. The current offset value calculation formula is a subtraction result of two of the value groups such that the current offset value of each of the current sources besides the target current source cancels out in the two value groups.

In an embodiment, the calibration parameter calculation circuit150sets the current offset values of two of current sources to be 0 as anchor points to avoid the interaction of the system.

By using the method described above, the calibration parameter calculating circuit150can update the first and the second offset table TB1-TB2 of the first and the second mapping circuit440A-450A.

In an embodiment, the output echo-canceling conversion circuit310may further includes s a control circuit (not illustrated) to sort the current offset values that the current sources correspond to, so as to generate a turn-on order to turn on the current sources according to the input codeword based on the turn-on order by using a thermometer control mechanism such that a linearity of the current sources when the current sources turn on according to the turn-on order is larger than a predetermined value. The setting of the turn-on order can be performed by using different methods and is not described herein.

When the output analog signal OD is transmitted through a transformer, a reflection from the transformer or a mismatch against external impedance may result in echoes to the echo-transmitting path EP that can not be fully canceled by the output echo-canceling analog signal OEC. As a result, in some embodiments, a mismatch echo-canceling circuit can be disposed in the digital-to-analog conversion apparatus100to cancel the echoes generated due to the mismatch.

Reference is now made toFIGS.1-4at the same time. The circuits related to performing mismatch echo-canceling are illustrated as dashed-line blocks inFIGS.1-4.

As illustrated inFIG.2, in some embodiments, the signal input circuit110further includes an odd filtering circuit240and an even filtering circuit250to respectively retrieve and perform filtering on the odd input part ISO and the even input part ISE of the input digital signal IS to output an odd filtered signal FSO and an even filtered signal FSE to the digital-to-analog conversion circuit120.

Further, the signal input circuit110may selectively include a limiting circuit260to limit an extremely large value and an extremely small value of the odd filtered signal FSO and the even filtered signal FSE to be a predetermined maximum value and a predetermined minimum value and transmit the maximum value and the minimum value to the digital-to-analog conversion circuit120.

For example, when a common value of each of the odd filtered signal FSO and the even filtered signal FSE ranges from −6 to +6, a peak error may occur during the subsequent calibration process performed by the calibration circuit when an uncommon value, e.g., −7 or +7 occurs. As a result, the limiting circuit260can limit the extremely large values of −7 and +7 to be the predetermined maximum value and the predetermined minimum value of −6 and +6 respectively to avoid the occurrence of peak error.

As illustrated inFIG.3, the digital-to-analog conversion circuit120further includes a mismatch echo-canceling conversion circuit340(abbreviated as MECC inFIG.3) to receive and perform conversion on the odd filtered signal FSO and the even filtered signal FSE to generate a mismatch echo-canceling analog signal MEC.

As illustrated inFIG.4, the echo calibration circuit140further includes an odd mismatch echo-canceling calibration circuit460and an even mismatch echo-canceling calibration circuit470.

The odd mismatch echo-canceling calibration circuit460includes a third mapping circuit480A and a third response circuit480B. The third mapping circuit480A receives and performs mapping on the odd filtered signal FSO according to a third offset table TB3 to generate a third mapped signal DS3. The third response circuit480B receives and performs processing on the third mapped signal DS3 according to a third group of response coefficients CC3 to generate an odd mismatch echo-canceling calibration signal ECS3.

The even mismatch echo-canceling calibration circuit470includes a fourth mapping circuit490A and a fourth response circuit490B. The fourth mapping circuit490A receives and performs mapping on the even filtered signal FSE according to a fourth offset table TB4 to generate a fourth mapped signal DS4. The fourth response circuit490B receives and performs processing on the fourth mapped signal DS4 according to a fourth group of response coefficients CC4 to generate an even mismatch echo-canceling calibration signal ECS4.

Similarly, each of the offset tables includes a plurality of one-to-one corresponding relations between a plurality of codewords and a plurality of codeword offset values. The detail of these offset tables is not described herein.

The error calculation circuit160further calculates the error signal DIS, which is a difference between the echo signal ES and a sum of the calibration signal described above, the odd mismatch echo-canceling calibration signal ECS3 and the even mismatch echo-canceling calibration signal ECS4.

The calibration parameter calculation circuit150generates the offsets according to the final error signal FDIS and path information related to the odd mismatch echo-canceling calibration circuit460and the even mismatch echo-canceling calibration circuit470, i.e., the path delays DL3-DL4 illustrated inFIG.5to track the calculated offsets to the correct input codeword according to the path delays DL3-DL4. Further, the calibration parameter calculation circuit150receives the third and the fourth groups of response coefficients CC3-CC4 of the third and the fourth response circuits480B-490B, performs one-dimensional inversion respectively on these response coefficients, multiplies the values of the final error signal FDIS by the inversed response coefficients and accumulates the multiplication results to generate corresponding inverted offsets values. According to the path delays DL3-DL4, the calibration parameter calculating circuit150further sets each of the inverted offset values to be the third and the fourth offsets DA3-DA4 corresponding to the third and the fourth mapping circuits480A-490A.

It is appreciated that the generation of the offset values described above is merely an example. In other embodiments, the calibration parameter calculating circuit150may generate the offset values by using other methods.

The first training stage performed under the condition that the circuits for performing mismatch echo-canceling are included is similar to the first training stage performed described above. The only difference is that the third response circuit480B and the fourth response circuit490B receive and set the converged odd pseudo noise response coefficients CCNO and the converged even pseudo noise response coefficients CCNE to be the third group of response coefficients CC3 and the fourth group of response coefficients CC4 respectively.

The second training stage performed under the condition that the circuits for performing mismatch echo-canceling are included is similar to the second training stage performed described above. The only difference is that the mismatch echo-canceling conversion circuit340is also enabled to output the mismatch echo-canceling analog signal MEC and update the third and the fourth offset tables TB3-TB4 according to the related third and the fourth offsets DA3-DA4. In an embodiment, the third and the fourth offset tables TB3-TB4 can selectively be updated according to the feeding of the third and the fourth offsets DA3-DA4 without setting any anchor point. However, the present invention is not limited thereto.

Reference is now made toFIG.5.FIG.5illustrates a block diagram of a digital-to-analog conversion apparatus500according to another embodiment of the present invention. The configuration of the digital-to-analog conversion apparatus500inFIG.5is similar to the configuration of the digital-to-analog conversion apparatus100inFIG.1. The identical components are not described herein.

In the present embodiment, the digital-to-analog conversion apparatus500inFIG.5includes the circuits for performing mismatch echo-canceling and is equipped with the mechanism that updates the group of odd filtering coefficients FOX of the odd filtering circuit240and the group of even filtering coefficients FXE of the even filtering circuit250inFIG.2.

More specifically, two down-sampling circuits (not illustrated in the figure) can be disposed in the echo transmission circuit130inFIG.5to generate an odd echo signal ESO and an even echo signal ESE having the second frequency. The odd echo signal ESO has an odd sign and the even echo signal ESE has an even sign. InFIG.5, the odd echo signal ESO is used to perform calculation with the echo-canceling calibration signal to generate the error signal DIS. However, in other embodiments, the even echo signal ESE can also be used to perform calculation with the echo-canceling calibration signal to generate the error signal DIS.

Further, the digital-to-analog conversion apparatus500further includes an updating circuit510. The updating circuit510includes an odd response circuit520(abbreviated as ORC inFIG.5), an even response circuit530(abbreviated as ERC inFIG.5) and a mutual calculation circuit540.

The odd response circuit520retrieves and performs response processing on the odd input part ISO of the input digital signal IS to output an odd response signal RSO. The even response circuit530retrieves and performs response processing on the even input part ISE of the input digital signal IS to output an even response signal RSE.

The mutual calculation circuit540receives the odd response signal RSO, the even response signal RSE, the odd echo signal ESO and the even echo signal ESE. The mutual calculation circuit540further performs mutual calculation on the odd response signal RSO, the even response signal RSE, the odd sign of the odd echo signal ESO and the even sign of the even echo signal ESE. Each of the odd sign and even sign may use +1 and −1 to represent a positive sign and a negative sign respectively. The odd sign is respectively used to perform calculation with the odd response signal RSO and the even response signal RSE. The even sign is also respectively used to perform calculation with the odd response signal RSO and the even response signal RSE. Such a mutual calculation generates a mutual calculation result MOR having the first frequency such that the odd filtering circuit240and the even filtering circuit250update the odd filtering coefficients FOX and the even filtering coefficients FXE according to the mutual calculation result MOR.

As a result, the digital-to-analog conversion apparatus100of the present invention generates an output analog signal and an echo-canceling analog signal having a first frequency and perform calibration thereon by using internal circuits that operate in a second frequency, which is a half of the first frequency according to an echo signal through down-sampling.

Reference is now made toFIG.6.FIG.6illustrates a flow chart of a digital-to-analog conversion method600having signal calibration mechanism according to an embodiment of the present invention.

In addition to the apparatus described above, the present disclosure further provides the digital-to-analog conversion method600having signal calibration mechanism that can be used in such as, but not limited to, the digital-to-analog conversion apparatus100inFIG.1. As illustrated inFIG.6, an embodiment of the digital-to-analog conversion method600includes the following steps.

In step S610, conversion is performed according to the signal feeding related to the input digital signal IS having the input codeword to generate the output analog signal OD and the echo-canceling analog signal by the digital-to-analog conversion circuit120such that the echo-canceling analog signal at least performs output echo-canceling on the output analog signal OD at the echo path EP, wherein the digital-to-analog conversion circuit120includes the conversion circuits operating at the first frequency.

In step S620, signal processing that includes down-sampling is performed on the echo path EP to generate the echo signal ES having the second frequency by the echo transmission circuit130, wherein the second frequency is a half of the first frequency.

In step S630, mapping is performed according to the offset tables and processing is performed according to the groups of response coefficients on the signal feeding related to the odd input part ISO and the even input part ISE of the input digital signal IS respectively by the echo calibration circuit140, to generate the odd calibration part and the even calibration part of the echo-canceling calibration signal, wherein the echo calibration circuit140includes the odd calibration circuit and the even calibration circuit operating at the second frequency and corresponding to the conversion circuits that generate the echo-canceling analog signal.

In step S640, the offsets are generated according to the error signal DIS between the echo signal ES and the echo-canceling calibration signal and path information related to the echo calibration circuit140by the calibration parameter calculation circuit150operating at the second frequency.

In step S650, the groups of response coefficients are converged according to the error signal ES and the pseudo noise transmission path information from the digital-to-analog conversion circuit120to the echo transmission circuit130and the offset tables are further updated according to the offsets by the echo calibration circuit140.

It is appreciated that the embodiments described above are merely an example. In other embodiments, it should be appreciated that many modifications and changes may be made by those of ordinary skill in the art without departing, from the spirit of the disclosure.

In summary, the present invention discloses the digital-to-analog conversion apparatus and the digital-to-analog conversion method having signal calibration mechanism to generate an output analog signal and an echo-canceling analog signal having a first frequency and perform calibration thereon by using internal circuits that operate in a second frequency, which is a half of the first frequency according to an echo signal through down-sampling.