Field-effect transistors with buried gates and methods of manufacturing the same

Field-effect transistors with buried gates and methods of manufacturing the same are disclosed. An example apparatus includes a source, a drain, and a semiconductor material positioned between the source and the drain. The example apparatus further includes a first gate positioned adjacent the semiconductor material. The example apparatus also includes a second gate positioned adjacent the semiconductor material. A portion of the semiconductor material is positioned between the first and second gates.

CLAIM OF PRIORITY

This Application is a National Stage Entry of, and claims priority to, PCT Patent Application No. PCT/US17/68564, filed on Dec. 27, 2017, and titled “FIELD-EFFECT TRANSISTORS WITH BURIED GATES AND METHODS OF MANUFACTURING THE SAME”, which is incorporated by reference in its entirety for all purposes.

FIELD OF THE DISCLOSURE

This disclosure relates generally to semiconductor devices, and, more particularly, to field-effect transistors with buried gates and methods of manufacturing the same.

BACKGROUND

Field-effect transistors (FETs) include a gate to control the conductivity of a semiconductor material extending between a source and drain of the transistor. More particularly, when energized, the gate activates a channel to enable current to pass between the source and the drain. The channel (and, thus, the flow of current) is typically located near the surface of the semiconductor material close to the gate. However, it is possible for electrical paths to develop between the source and drain within the main body of the semiconductor material below the channel. Current within the bulk or main body of the semiconductor material below the channel is sometimes referred to as “punch through current,” or simply, “punch through.”

Punch through is problematic to the performance of transistors because it cannot be controlled or modulated by the electric field produced by the gate. The likelihood of punch through occurring increases as the scale of the transistor decreases and/or as the voltage applied to the transistor increases. Accordingly, the punch through effect poses challenges to reducing the scale of transistors and using transistors in high voltage applications.

The figures are not to scale. Instead, for clarity, the thickness of layers and/or regions may be enlarged in the drawings. Moreover, the illustrated layers and/or regions are idealized; it being understood that manufacturing in the real world may result in blending and/or irregularities between layer(s) and/or region(s). Wherever beneficial, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. As used in this patent, stating that any part (e.g., a layer, film, area, or plate) is in any way on positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part one or more intermediate part(s) located therebetween. Stating that any part is in contact with another part means that there is no intermediate part between the two parts.

DETAILED DESCRIPTION

FIG. 1is a cross-sectional view of a planar transistor100manufactured using known techniques. InFIG. 1, a gate102may be switched on and off based on the application of an electric potential. When energized, the gate102produces an electric field that extends into the semiconductor material104to control the conductivity of the semiconductor material104. When the electric field is applied to the semiconductor material104, a channel (represented by the broken line106) is activated between source and drain regions108,110to allow the flow of current therebetween. The channel typically forms in a region having a thickness of less than about 4 nanometers within the semiconductor material104in the surface of the semiconductor material104adjacent a polarization layer112. The channel within this thin region is sometimes referred to as a two-dimensional (2D) electron gas.

While the flow of current within the channel106at the interface between the polarization layer112and the semiconductor material104may be controlled by controlling the electric field produced by the gate102, there may be situations where current will flow through the main body of the semiconductor material104outside of the channel. In particular, the ability of the electric field to control the conductivity of the semiconductor material104is dependent on the reach of the electric field into the semiconductor material. There is a limit to the reach of the electric field for which control is effective. For purposes of explanation, this limit is referred to herein as the “effective control reach” of the electric field produced by the gate102and is represented inFIG. 1by the dashed line114.

As shown inFIG. 1, the effective control reach114associated with the gate102does not reach through the full thickness of the semiconductor material104. As such, there is a region of the semiconductor material104for which the gate102cannot effectively control the conductivity of the material. In such situations, there is the possibility of a punch through current (represented by the arrow116) appearing within the semiconductor material104that goes underneath and around the effective control reach114of the electric field produced by the gate.

One known solution to reducing the likelihood of punch through current is to reduce the thickness of the semiconductor material104. If the semiconductor material104is sufficiently thin, the effective control reach114associated with the gate102may extend into a buffer layer118beneath the semiconductor material104(adjacent on opposite surface of the semiconductor material104to where the channel106is located). The buffer layer118may be formed of a material that has a higher bandgap than the semiconductor material104to effectively act as an insulator or barrier that blocks electrical paths from forming for current to flow therethrough

A problem with the known approach of reducing the thickness of the semiconductor material104is that this thickness reduction can adversely impact the mobility of electrons in the semiconductor material104and, thus, adversely impact the performance of the transistor100. Accordingly, rather than reducing the thickness of the semiconductor material, examples disclosed herein reduce the likelihood of punch through current by extending the effective control reach of the electric field produced by the gate. In some examples disclosed herein, the effective control reach is extended by embedding or burying a second gate within the body of the semiconductor material beneath a first gate on top of the semiconductor material. In disclosed examples, the first and second gates are positioned in vertical alignment. For purposes of explanation, the first gate on top of the semiconductor material is referred to herein as the “top gate,” whereas the second gate within the body of the semiconductor material is referred to herein as the “buried gate.” Examples disclosed herein achieve a reduction in punch through without reducing the thickness of the layer of semiconductor material and/or reduce punch through even with a thicker layer of semiconductor material than what is used in known transistors. In particular, in examples where the semiconductor material is gallium nitride, the semiconductor layer in known transistors is typically less than or equal to 20 nanometers but no thinner than 10 nanometers. In some disclosed examples, the thickness of the semiconductor layer is greater than 20 nanometers (e.g., 25 nm, 30 nm, 50 nm, 100 nm) while still reducing (e.g., preventing) punch through current below the channel.

FIG. 2is a cross-sectional view of an example transistor200constructed in accordance with teachings of this disclosure. In the illustrated example ofFIG. 2, the transistor200is formed on a base semiconductor substrate or wafer202. The base substrate202may be formed of any suitable semiconductor material, such as, for example, silicon (Si) with the crystalline structure arranged in any suitable orientation (e.g., Si 111, Si 110, Si 100). Additionally or alternatively, the base substrate202may be formed of other suitable semiconductor materials (e.g., germanium (Ge), gallium arsenide (GaAs), etc.). For purposes of explanation, the base substrate202will be assumed to be Si 111.

In the illustrated example ofFIG. 2, a buffer layer204is formed on the base substrate202to serve as a transition between the different crystalline structures of the base substrate202and an upper semiconductor material206. The buffer layer204may include a composition of aluminum (Al), gallium (Ga), and nitrogen (N). More particularly, in some examples, aluminum nitride (AlN) is deposited on the base substrate202with aluminum gallium nitride (AlGaN) deposited thereafter. In the illustrated example, the upper semiconductor material206is gallium nitride (GaN). Gallium nitride is beneficial for transistors used in high voltage applications because it has a bandgap that is nearly three times greater than silicon (silicon has a bandgap of approximately 1.1 eV, whereas gallium nitride has a bandgap of approximately 3.4 eV).

A polarization layer208is formed on the upper semiconductor material206and supports a top gate210. The polarization layer208may include a composition of aluminum (Al), indium (In), gallium (Ga), and nitrogen (N). In the illustrated example, the top gate210includes a gate conductor212that is surrounded by a gate dielectric214. The gate conductor212may be metal (e.g., aluminum (Al), tungsten (W), etc.) or a non-metal conductor (e.g., polysilicon). The gate dielectric214may be formed of silicon dioxide (SiO2) or any suitable high-K dielectric such as, for example, alumina (Al2O3), hafnia (HfO2), zirconia (ZrO2), silicon nitride (Si3N4), etc.

On either side of the top gate210, the transistor200ofFIG. 2includes a doped source region216and a doped drain region218. In the illustrated example, the source and drain regions216,218include a crystal structure of indium gallium nitride (InGaN) that has been highly doped with silicon to improve electrical connectivity with metal contacts220,222formed on the respective source and drain regions216,218.

In the illustrated example, the top gate210produces an electric field when powered that is capable of controlling the conductivity of the semiconductor material206within an effective control reach224of the electric field. As shown inFIG. 2, the effective control reach224extends over a channel226(e.g., at the interface between the semiconductor material206and the polarization layer208) of the transistor200to effectively control current flow therethrough.

In contrast with the known transistor100ofFIG. 1, the example transistor200ofFIG. 2includes a buried gate228within the main body of the semiconductor material206spaced apart from and in vertical alignment with the top gate210. As such, a portion of the semiconductor material206is between the buried gate228and the top gate210above the semiconductor material206. In other words, the buried gate228is positioned on one side of the channel226while the top gate210is positioned on the opposite side of the channel226. Further, as shown in the illustrated example, a second portion of the semiconductor material206is below the buried gate228(e.g., the second portion is farther away from the top gate210than the buried gate228). In other examples, the buried gate228may be in contact with the buffer layer204such that no portion of the semiconductor material206is below the buried gate228. In other words, the buried gate228may be positioned at the bottom of the semiconductor material206.

In some examples, the buried gate228is made of the same material as the top gate210. For example, the buried gate may be formed of a refractory metal (e.g., tungsten (W), titanium nitride (TiN), thallium nitride (Tl3N), etc.) or a non-metal conductor (e.g., resistive polysilicon). In other examples, the material of the buried gate228may be different than the material of the top gate210. In the illustrated example, the buried gate228is electrically connected to (in circuit with) the top gate210(as represented by the line230) so that both gates are maintained at the same electric potential. In this manner, both gates210,228are switched on and off together to produce a corresponding electric field that modulates or otherwise controls the conductivity of the semiconductor material206.

The effectiveness or ability of the gates210,228to control the conductivity of the semiconductor material206depends upon the distance between either one of the gates210,228and the location of the semiconductor material206to be controlled because the electric field produced by the gates210,228weakens as the distance increases. The limit to the reach of such an electric field for which control is effective to satisfy performance specifications is referred to herein as the effective control reach of the electric field. For purposes of explanation, separate effective control reaches for electric fields produced by each of the gates210,228are illustrated inFIG. 2. In particular, the top gate210has an effective control reach224associated with the electric field it produces. The buried gate228has a separate corresponding effective control reach232for its electric field. In some examples, the separate electric fields function as a single electric field that controls the region defined by the combination of both effective control reaches224,234. Thus, in the illustrated example, the buried gate228is a means for extending the effective control reach of the top gate210. In the illustrated example, the buried gate228is positioned within the effective control reach224of the electric field produced by the top gate210such that there is significant overlap in the effective control reaches224,232associated with the two gates210,228. In other examples, the buried gate228may be positioned outside of the effective control reach224associated with the top gate210but close enough so that the effective control reaches224,232of the two gates still overlap. In other words, the distance between the top gate210and the buried gate228may be any suitable distance less than the combined distance of both effective control reaches224,232.

As shown in the illustrated example, the effective control reach232of the buried gate228extends into the buffer layer204. That is, the effective control reach is greater than the thickness of the portion of the semiconductor material206between the buried gate228and the buffer layer204. As a result, the gates210,228, working in combination, are able to control the conductivity of the semiconductor material206throughout its entire thickness (between the buffer layer204and the polarization layer208). This is achieved without reducing the thickness of the semiconductor material206. That is, this may be implemented in a semiconductor material that is more than 20 nm thick. In this manner, the likelihood of punch through current (represented by the arrow234) is significantly reduced because the punch through current would be forced to travel through the buffer layer204, which has a much higher bandgap than the semiconductor material206. In particular, gallium nitride (associated with the semiconductor material206in this example) has a bandgap of approximately 3.4 eV, whereas aluminum gallium nitride (associated with the buffer layer204in this example) can have a bandgap as high as 6.2 eV (depending on the concentration of the aluminum).

The inclusion of a buried gate may be incorporated into any suitable transistor made of any suitable type(s) of materials. For instance, a buried gate may be positioned within a semiconductor material that is not associated with an underlying buffer layer. In such examples, while extending the effective control reach deeper into the semiconductor material may not extend into a different material as described above, the increased depth of the effective control reach with a buried gate may nevertheless reduce the likelihood of punch through by forcing longer electrical paths to form within the main body of the material between the source and drain regions.

FIG. 3is a cross-sectional view of another example transistor300constructed in accordance with teachings of this disclosure. The example transistor300is similar to the transistor ofFIG. 2. For instance, like transistor200ofFIG. 2, the example transistor300ofFIG. 3includes a base semiconductor substrate202, buffer layer204, semiconductor material206, polarization layer208, gate210(including the gate conductor212and gate dielectric214), and source and drain regions216,218with the associated metal contacts220,222. The example transistor300ofFIG. 3also includes a buried gate302similar to the buried gate228ofFIG. 2, except that the gate302ofFIG. 3is buried using a different manufacturing process than the process used to bury the gate228ofFIG. 2. In particular, inFIG. 3, the buried gate302is positioned between first and second portions304,306of the semiconductor material206. In the illustrated example, the first and second portions304,306of the semiconductor material206are separately formed and attached to one another via a bonding oxide308positioned therebetween. By contrast, the semiconductor material206shown inFIG. 2is a unitary or integrated layer of material that is epitaxially grown over the buried gate228. Further detail regarding different example methods of manufacturing the example transistors200,300ofFIGS. 2 and 3are provided below in connection withFIGS. 4-22. In particular,FIGS. 4-11correspond to the manufacture of the example transistor200ofFIG. 2.FIGS. 12-22correspond to the manufacture of the example transistor300ofFIG. 3

In addition to the bonding oxide308, the example transistor300ofFIG. 3differs from the example transistor200ofFIG. 2in that the buried gates228,302in each example have different dimensions. The buried gates228,302may have any suitable dimensions. In some examples, the buried gates228,302may have any suitable thickness ranging from 5 nanometers up to 100 nanometers (e.g., 5 nm, 20 nm, 50 nm, etc.). By way of comparison, the full thickness of the semiconductor material206(e.g., between the buffer layer204and the polarization layer208) may range from 0.5 micrometers to 1 micrometer. In some examples, the buried gates228,302have a length ranging from the length of the top gate210(e.g., the length236as shown inFIG. 2) up to the distance between the source and drain regions216,218(e.g., the length310as shown inFIG. 3). In other examples, the buried gates228,302may have a length even greater than that shown inFIG. 3or less than that shown inFIG. 2. While the dimensions of the top gate and the buried gate may vary, preferably at least a portion of the top gate is in vertical alignment (e.g., positioned directly above) a portion of the buried gate.

FIG. 4is a flowchart representative of an example method to manufacture the example transistor200ofFIG. 2.FIGS. 5-11illustrate stages in the manufacturing of the transistor200ofFIG. 2and will be referenced in the following discussion ofFIG. 4. The example process begins at block402where the buffer layer204is deposited on the base semiconductor substrate202(as represented inFIG. 5). At block404, a first portion of the semiconductor material206is deposited on the buffer layer204(as represented inFIG. 6). At block406, the gate228to be buried is formed on the first portion of the semiconductor material206(as represented inFIG. 7). In some examples, the gate228is formed by depositing the material for the gate228across the surface of the first portion of the semiconductor material206. Thereafter, a pattern and etch process are implemented to remove unneeded portions of the material associated with the gate228to leave the gate228as shown inFIG. 7.

At block408, a second portion of the semiconductor material206is grown over the gate thereby burying the same (as represented inFIG. 8). In the illustrated example ofFIG. 8, a dashed line is provided to demarcate where the first portion of the semiconductor material206ends and the second portion of the semiconductor material206begins. However, the dashed line is provided only for purposes of reference relative toFIG. 7because the second portion of the semiconductor material206becomes an integral extension of the first portion using the process of lateral epitaxial overgrowth (LEO). Thus, in subsequent drawings (FIGS. 9-11) the dashed line is removed. Not only does LEO result in the first and second portions of the semiconductor material206becoming an integrated or unitary layer or material, LEO enables the semiconductor material206to grow over the buried gate228, thereby covering and surrounding the gate as shown in the illustrated example ofFIG. 8.

At block410, the polarization layer208is deposited on the semiconductor material206(as represented inFIG. 9). At block412, the polarization layer208and the semiconductor material206are etched to form a metal via through to the buried gate228to enable formation of an electrical connection with the top gate210. In the illustrated example ofFIG. 10, the etched region that extends to the buried gate8is represented by dashed lines1002to indicate that the etching is not performed in the plane of the cross-sectional view of the illustrated examples. More generally, any portion of the buried gate228may be accessed via etching to subsequently provide an electrical connection between the buried gate228and the top gate210. In this manner, the electrical potential of both gates210,228will be the same so that they effectively operate as a single gate with an extended electrical field when energized.

At block414, the source and drain regions216,218are formed. In some examples, the source and drain regions216,218are formed by etching through the polarization layer208down to the semiconductor material206and then epitaxially growing the material used for the source and drain regions216,218. In some examples, the material used for the source and drain regions216,218corresponds to indium gallium nitride (InGaN). Once the crystalline structure of the source and drain regions216,218have been formed, they may be doped with a dopant (e.g., silicon). At block416, the top gate210is formed electrically connected to the buried gate (e.g., via the etched region1002). In some examples, the top gate is formed by forming an oxide layer (e.g., a silicate) on the polarization layer208and the source and drain regions216,218followed by a patterned mask to etch an opening in the oxide layer for the top gate210. Thereafter, the gate dielectric214is deposited to the surface of the opening to a particular thickness and then the gate conductor212fills in the remainder of the opening. In some examples, the gate conductor212may be aligned with the metal via deposited on the buried gate228described above at block408to electrically connect the buried gate228and the top gate210. In other examples, an opening may be etched through the oxide layer down to the metal via associated with the buried gate228that is subsequently filled with a conductive material (e.g., metal) that is connected to the gate conductor212with metal interconnects formed during subsequent back-end-of-line processes. At block418, metal contacts220,222are deposited. In some examples, additional openings are etched into the oxide layer mentioned above in connection with block416that correspond to the metal contacts220,222. Subsequently, the material used for the metal contacts220,222is deposited into the corresponding openings in the oxide layer. The completion of blocks414,416, and418is represented inFIG. 11, which corresponds to the example transistor200ofFIG. 2. Thereafter, the example process ofFIG. 4ends.

Although the example method ofFIG. 4is described with reference to the flowchart shown inFIG. 4and the example stages illustrated inFIGS. 5-11, many other methods of manufacturing the example transistor200ofFIG. 2may alternatively be used. For example, the order of execution of the blocks inFIG. 4may be changed, and/or some of the blocks described may be changed, eliminated, or combined. Similarly, additional operations (e.g., singulation) may be included in the manufacturing process before, in between, or after the blocks shown inFIG. 4.

FIG. 12is a flowchart representative of an example method to manufacture the example transistor300ofFIG. 3.FIGS. 13-22illustrate stages in the manufacturing of the transistor300ofFIG. 3and will be referenced in the following discussion ofFIG. 12. The example process ofFIG. 12begins with two parallel sub-processes that result in upper and lower assemblies for the example transistor300that are subsequently stacked and bonded together. The first sub-process corresponds to blocks1202-1208. At block1202, the buffer layer204is deposited on a first semiconductor substrate (e.g., the base substrate202) (as represented inFIG. 13). At block1204, a first portion304of the semiconductor material206is deposited on the buffer layer204(as represented inFIG. 14). At block1206, the gate302to be buried is formed on the first portion304of the semiconductor material206(as represented inFIG. 15). The formation of the gate302may be done in the manner explained above for gate228. At block1208, a first bonding oxide (e.g., the bonding oxide308) is deposited on the first portion304of the semiconductor material206surrounding the buried gate302(as represented inFIG. 16). In the illustrated example ofFIG. 16, the first bonding oxide308surrounds the buried gate302but does not cover the buried gate302. In other examples, the first bonding oxide308may cover both the first portion304of the semiconductor material206and the buried gate302. The completion of block1208is the end of the first parallel sub-process of the example method ofFIG. 12and results in a lower assembly1600of the example transistor300ofFIG. 3.

The second parallel sub-process ofFIG. 12corresponds to blocks1210-1214. At block1210, a second bonding oxide1702is deposited on a second semiconductor substrate1704(as represented inFIG. 17). In some examples, the second semiconductor substrate1704is made of the same material as the first semiconductor substrate202used in the lower assembly1600of the transistor300. For instance, in some examples, the first and second semiconductor substrates202,1704correspond to separate silicon wafers. In other examples, the first and second semiconductor substrates202,1704may be formed of different materials. At block1212, the polarization layer208is deposited on the second bonding oxide1702(as represented inFIG. 18). The second bonding oxide1702serves to facilitate the adhesion of the polarization layer208on the second semiconductor substrate1704. At block1214, the second portion306of the semiconductor material206is deposited on the polarization layer208(as represented inFIG. 19). The completion of block1214is the end of the second parallel sub-process of the example method ofFIG. 12and results in an upper assembly1900of the example transistor300ofFIG. 3.

The lower assembly1600(FIG. 16) resulting from the first sub-process and the upper assembly1900(FIG. 19) resulting from the second sub-process are brought together at block1216of the example process ofFIG. 12. In particular, at block1216, the second portion306of the semiconductor material206(associated with the upper assembly1900) is inverted and attached to the first portion304of the semiconductor material206(associated with the lower assembly1600) via the first bonding oxide308. That is, as shown in the illustrated example ofFIG. 20, the upper assembly1900is flipped over (relative to the orientation shown inFIG. 19) and positioned on top of the lower assembly1600so that the gate302is sandwiched (and, thus, buried) between the first and second portions304,306of the semiconductor material206. The first bonding oxide308serves to facilitate the adhesion of the separate portions304,306of the semiconductor material206. In some examples, the attached assemblies1600,1900undergo an annealing process to strengthen the adhesion between the first bonding oxide308and the portions304,306of the semiconductor material206.

At block1218, the second semiconductor substrate1704and the second bonding oxide1702are removed from the polarization layer208(as represented inFIG. 21). At this point in the process, the buried gate302is buried between separate portions304,306of the semiconductor material206with a polarization layer208positioned thereon. This is similar to the arrangement shown inFIG. 20except that inFIG. 21, the separate portions304,306of the semiconductor material206are not integrally formed but, instead, are adhered to one another via the bonding oxide308. Despite this difference blocks1220,1222,1224, and1226in the example process ofFIG. 12are respectively identical to blocks412,414,416, and418as described above in connection withFIG. 4. Therefore, while the processes of blocks1220,1222,1224, and1226are represented inFIG. 12, the explanation of those blocks is not repeated. Instead, the reader is referred to the above description of blocks412,414,416, and418for a complete discussion of these blocks. Upon completion of block1226, the example process ofFIG. 12ends.

Although the example method ofFIG. 12is described with reference to the flowchart shown inFIG. 12and the example stages illustrated inFIGS. 13-22, many other methods of manufacturing the example transistor300ofFIG. 3may alternatively be used. For example, the order of execution of the blocks inFIG. 12may be changed, and/or some of the blocks described may be changed, eliminated, or combined. As a particular example, the formation of the gate302(block1206) followed by the deposition of the bonding oxide (block1208) as part of the first parallel sub-process may alternatively be implemented at the end of the second sub-process (e.g., following block1214) to arrive at a similar end result as described above. Further, additional operations may be included in the manufacturing process before, in between, or after the blocks shown inFIG. 12.

The example buried gate transistors200,300disclosed herein may be included in any suitable electronic component.FIGS. 23-26illustrate various examples of apparatus that may include any of the example transistors200,300disclosed herein.

FIG. 23is a top view of a wafer300and dies2302that may include one or more buried gate transistors, or may be included in an IC package whose substrate includes one or more buried gate transistors (e.g., as discussed below with reference toFIG. 25) in accordance with any of the examples disclosed herein. The wafer2300may be composed of semiconductor material and may include one or more dies2302having IC structures formed on a surface of the wafer2300. Each of the dies2302may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer2300may undergo a singulation process in which the dies2302are separated from one another to provide discrete “chips” of the semiconductor product. The die2302may include one or more buried gate transistors (e.g., as discussed below with reference toFIG. 24), one or more transistors (e.g., some of the transistors2440ofFIG. 24, discussed below) and/or supporting circuitry to route electrical signals to the transistors, as well as any other IC components. In some examples, the wafer2300or the die2302may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die2302. For example, a memory array formed by multiple memory devices may be formed on a same die2302as a processing device (e.g., the processing device2702ofFIG. 27) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array.

FIG. 24is a cross-sectional side view of an IC device2400that may include one or more buried gate transistors2401, or may be included in an IC package whose substrate includes one or more buried gate transistors (e.g., as discussed below with reference toFIG. 25), in accordance with the examples disclosed herein. One or more of the IC devices2400may be included in one or more dies2302(FIG. 23). The IC device2400may be formed on a substrate2402(e.g., the wafer2300ofFIG. 23) and may be included in a die (e.g., the die2302ofFIG. 23). The substrate2402may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The substrate2402may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some examples, the substrate2402may be formed using alternative materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the substrate2402. Although a few examples of materials from which the substrate2402may be formed are described here, any material that may serve as a foundation for an IC device2400may be used. The substrate2402may be part of a singulated die (e.g., the dies2302ofFIG. 23) or a wafer (e.g., the wafer2300ofFIG. 23).

The IC device2400may include one or more device layers2404disposed on the substrate2402. The device layer2404may include features of one or more transistors2440(e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the substrate2402. The device layer2404may include, for example, one or more source and/or drain (S/D) regions2420, a gate2422to control current flow in the transistors2440between the S/D regions2420, and one or more S/D contacts2424to route electrical signals to/from the S/D regions2420. The transistors2440may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors2440are not limited to the type and configuration depicted inFIG. 24and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

The S/D regions2420may be formed within the substrate2402adjacent to the gate2422of each transistor2440. The S/D regions2420may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate2402to form the S/D regions2420. An annealing process that activates the dopants and causes them to diffuse farther into the substrate2402may follow the ion-implantation process. In the latter process, the substrate2402may first be etched to form recesses at the locations of the S/D regions2420. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions2420. In some implementations, the S/D regions2420may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some examples, the S/D regions2420may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further examples, one or more layers of metal and/or metal alloys may be used to form the S/D regions2420.

In some examples, the device layer2404may include one or more buried gate transistors, in addition to or instead of transistors2440.FIG. 24illustrates a single buried gate transistor2401in the device layer2404for illustration purposes, but any number and structure of buried gate transistors may be included in a device layer2404. A buried gate transistor included in a device layer2404may be referred to as a “front end” device. In some examples, the IC device2400may not include any front end buried gate transistors. One or more buried gate transistors in the device layer2404may be coupled to any suitable other ones of the devices in the device layer2404, to any devices in the metallization stack2419(discussed below), and/or to one or more of the conductive contacts2436(discussed below).

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors2440and/or buried gate transistor2401) of the device layer2404through one or more interconnect layers disposed on the device layer2404(illustrated inFIG. 24as interconnect layers2406-2310). For example, electrically conductive features of the device layer2404(e.g., the gate2422and the S/D contacts2424) may be electrically coupled with the interconnect structures2428of the interconnect layers2406-2310. The one or more interconnect layers2406-2310may form a metallization stack (also referred to as an “ILD stack”)2419of the IC device2400. In some examples, one or more buried gate transistors may be disposed in one or more of the interconnect layers2406-2310, in accordance with any of the techniques disclosed herein. A buried gate transistor included in the metallization stack2419may be referred to as a “back-end” device. In some examples, the IC device2400may not include any back-end buried gate transistors; in some examples, the IC device2400may include both front- and back-end buried gate transistors. One or more buried gate transistors in the metallization stack2419may be coupled to any suitable ones of the devices in the device layer2404, and/or to one or more of the conductive contacts2436(discussed below).

The interconnect structures2428may be arranged within the interconnect layers2406-2310to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures2428depicted inFIG. 24). Although a particular number of interconnect layers2406-2310is depicted inFIG. 24, examples of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some examples, the interconnect structures2428may include lines2428aand/or vias2428bfilled with an electrically conductive material such as a metal. The lines2428amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the substrate2402upon which the device layer2404is formed. For example, the lines2428amay route electrical signals in a direction in and out of the page from the perspective ofFIG. 24. The vias2428bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the substrate2402upon which the device layer2404is formed. In some examples, the vias2428bmay electrically couple lines2428aof different interconnect layers2406-2310together.

The interconnect layers2406-2310may include a dielectric material2426disposed between the interconnect structures2428, as shown inFIG. 24. In some examples, the dielectric material2426disposed between the interconnect structures2428in different ones of the interconnect layers2406-2310may have different compositions; in other examples, the composition of the dielectric material2426between different interconnect layers2406-2310may be the same.

A first interconnect layer2406(referred to as Metal 1 or “M1”) may be formed directly on the device layer2404. In some examples, the first interconnect layer2406may include lines2428aand/or vias2428b, as shown. The lines2428aof the first interconnect layer2406may be coupled with contacts (e.g., the S/D contacts2424) of the device layer2404.

A second interconnect layer2408(referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer2406. In some examples, the second interconnect layer2408may include vias2428bto couple the lines2428aof the second interconnect layer2408with the lines2428aof the first interconnect layer2406. Although the lines2428aand the vias2428bare structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer2408) for the sake of clarity, the lines2428aand the vias2428bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some examples.

A third interconnect layer2410(referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer2408according to similar techniques and configurations described in connection with the second interconnect layer2408or the first interconnect layer2406. In some examples, the interconnect layers that are “higher up” in the metallization stack2419in the IC device2400(i.e., further away from the device layer2404) may be thicker.

The IC device2400may include a solder resist material2434(e.g., polyimide or similar material) and one or more conductive contacts2436formed on the interconnect layers2406-2310. InFIG. 24, the conductive contacts2436are illustrated as taking the form of bond pads. The conductive contacts2436may be electrically coupled with the interconnect structures2428and configured to route the electrical signals of the transistor(s)2440to other external devices. For example, solder bonds may be formed on the one or more conductive contacts2436to mechanically and/or electrically couple a chip including the IC device2400with another component (e.g., a circuit board). The IC device2400may include additional or alternate structures to route the electrical signals from the interconnect layers2406-2310; for example, the conductive contacts2436may include other analogous features (e.g., posts) that route the electrical signals to external components.

FIG. 25is a cross-sectional view of an example IC package2500that may include one or more buried gate transistors. The package substrate2502may be formed of a dielectric material, and may have conductive pathways extending through the dielectric material between upper and lower faces2522,2524, or between different locations on the upper face2522, and/or between different locations on the lower face2524. These conductive pathways may take the form of any of the interconnects2428discussed above with reference toFIG. 24. In some examples, any number of buried gate transistors (with any suitable structure) may be included in a package substrate2502. In some examples, no buried gate transistors may be included in the package substrate2502.

The IC package2500may include a die2506coupled to the package substrate2502via conductive contacts2504of the die2506, first-level interconnects2508, and conductive contacts2510of the package substrate2502. The conductive contacts2510may be coupled to conductive pathways2512through the package substrate2502, allowing circuitry within the die2506to electrically couple to various ones of the conductive contacts2514or to the buried gate transistors (or to other devices included in the package substrate2502, not shown). The first-level interconnects2508illustrated inFIG. 25are solder bumps, but any suitable first-level interconnects2508may be used. As used herein, a “conductive contact” may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket).

In some examples, an underfill material2516may be disposed between the die2506and the package substrate2502around the first-level interconnects2508, and a mold compound2518may be disposed around the die2506and in contact with the package substrate2502. In some examples, the underfill material2516may be the same as the mold compound2518. Example materials that may be used for the underfill material2516and the mold compound2518are epoxy mold materials, as suitable. Second-level interconnects2520may be coupled to the conductive contacts2514. The second-level interconnects2520illustrated inFIG. 25are solder halls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects2520may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects2520may be used to couple the IC package2500to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference toFIG. 26.

InFIG. 25, the IC package2500is a flip chip package, and includes a buried gate transistor in the package substrate2502. The number and location of buried gate transistors in the package substrate2502of the IC package2500is simply illustrative, and any number of buried gate transistors (with any suitable structure) may be included in a package substrate2502. In some examples, no buried gate transistors may be included in the package substrate2502. The die2506may take the form of any of the examples of the die2302discussed herein (e.g., may include any of the examples of the IC device2400). In some examples, the die2506may include one or more buried gate transistors (e.g., as discussed above with reference toFIG. 23andFIG. 24); in other examples, the die2506may not include any buried gate transistors.

Although the IC package2500illustrated inFIG. 25is a flip chip package, other package architectures may be used. For example, the IC package2500may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package2500may be a wafer-level chip scale package (WLCSP) or a panel fanout (FO) package. Although a single die2506is illustrated in the IC package2500ofFIG. 25, an IC package2500may include multiple dies2506(e.g., with one or more of the multiple dies2506coupled to buried gate transistors included in the package substrate2502). An IC package2500may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face2522or the second face2524of the package substrate2502. More generally, an IC package2500may include any other active or passive components known in the art.

FIG. 26is a cross-sectional side view of an IC device assembly2600that may include one or more IC packages or other electronic components (e.g., a die) including one or more buried gate transistors, in accordance with any of the examples disclosed herein. The IC device assembly2600includes a number of components disposed on a circuit board2602(which may be, for example, a motherboard). The IC device assembly2600includes components disposed on a first face2640of the circuit board2602and an opposing second face2642of the circuit board2602; generally, components may be disposed on one or both faces2640and2642. Any of the IC packages discussed below with reference to the IC device assembly2600may take the form of any of the examples of the IC package2500discussed above with reference toFIG. 25(e.g., may include one or more buried gate transistors in a package substrate2502or in a die).

In some examples, the circuit board2602may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board2602. In other examples, the circuit board2602may be a non-PCB substrate.

The IC device assembly2600illustrated inFIG. 26includes a package-on-interposer structure2636coupled to the first face2640of the circuit board2602by coupling components2616. The coupling components2616may electrically and mechanically couple the package-on-interposer structure2636to the circuit board2602, and may include solder balls (as shown inFIG. 26), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure2636may include an IC package2620coupled to an interposer2604by coupling components2618. The coupling components2618may take any suitable form for the application, such as the forms discussed above with reference to the coupling components2616. Although a single IC package2620is shown inFIG. 26, multiple IC packages may be coupled to the interposer2604; indeed, additional interposers may be coupled to the interposer2604. The interposer2604may provide an intervening substrate used to bridge the circuit board2602and the IC package2620. The IC package2620may be or include, for example, a die (the die2302ofFIG. 23), an IC device (e.g., the IC device2400ofFIG. 24), or any other suitable component. Generally, the interposer2604may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer2604may couple the IC package2620(e.g., a die) to a set of BGA conductive contacts of the coupling components2616for coupling to the circuit board2602. In the example illustrated inFIG. 26, the IC package2620and the circuit board2602are attached to opposing sides of the interposer2604; in other examples, the IC package2620and the circuit board2602may be attached to a same side of the interposer2604. In some examples, three or more components may be interconnected by way of the interposer2604.

The IC device assembly2600may include an IC package2624coupled to the first face2640of the circuit board2602by coupling components2622. The coupling components2622may take the form of any of the examples discussed above with reference to the coupling components2616, and the IC package2624may take the form of any of the examples discussed above with reference to the IC package2620.

The IC device assembly2600illustrated inFIG. 26includes a package-on-package structure2634coupled to the second face2642of the circuit board2602by coupling components2628. The package-on-package structure2634may include a first IC package2626and a second IC package2632coupled together by coupling components2630such that the first IC package2626is disposed between the circuit board2602and the second IC package2632. The coupling components2628,2630may take the form of any of the examples of the coupling components2616discussed above, and the IC packages2626,2632may take the form f any of the examples of the IC package2620discussed above. The package-on-package structure2634may be configured in accordance with any of the package-on-package structures known in the art.

FIG. 27is a block diagram of an example electrical device2700that may include one or more buried gate transistors, in accordance with any of the examples disclosed herein. For example, any suitable ones of the components of the electrical device2700may include one or more of the IC packages2500, IC devices2400, or dies2302disclosed herein. A number of components are illustrated inFIG. 27as included in the electrical device2700, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some examples, some or all of the components included in the electrical device2700may be attached to one or more motherboards. In some examples, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various examples, the electrical device2700may not include one or more of the components illustrated inFIG. 27, but the electrical device2700may include interface circuitry for coupling to the one or more components. For example, the electrical device2700may not include a display device2706, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device2706may be coupled. In another set of examples, the electrical device2700may not include an audio input device2724or an audio output device2708, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device2724or audio output device2708may be coupled.

The electrical device2700may include a processing device2702(e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device2702may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device2700may include a memory2704, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some examples, the memory2704may include memory that shares a die with the processing device2702. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

The electrical device2700may include battery/power circuitry2714. The battery/power circuitry2714may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device2700to an energy source separate from the electrical device2700(e.g., AC line power).

The electrical device2700may include a display device2706(or corresponding interface circuitry, as discussed above). The display device2706may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device2700may include an audio output device2708(or corresponding interface circuitry, as discussed above). The audio output device2708may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.

The electrical device2700may include an audio input device2724(or corresponding interface circuitry, as discussed above). The audio input device2724may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The electrical device2700may include a GPS device2718(or corresponding interface circuitry, as discussed above). The GPS device2718may be in communication with a satellite-based system and may receive a location of the electrical device2700, as known in the art.

The electrical device2700may include an other output device2710(or corresponding interface circuitry, as discussed above). Examples of the other output device2710may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

The electrical device2700may include an other input device2720(or corresponding interface circuitry, as discussed above). Examples of the other input device2720may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (MID) reader.

From the foregoing, it will be appreciated that example transistors and example methods of manufacturing transistors have been disclosed that include a buried gate maintained at the same electrical potential as a top gate to prevent punch through without reducing a thickness of a semiconductor layer in which a channel is to be formed. The buried gate extends the effective control reach of the electrical field produced by the gates deeper into the semiconductor layer of the transistor, thereby reducing the likelihood of punch through current arising between the source and drain regions of the transistor. More particularly, in some examples, a buried gate is positioned to extend the effective control reach of an electrical field produced by the top gate into a layer of material with a higher bandgap than the semiconductor material of the transistor. The higher bandgap layer serves as an insulator that effectively blocks the formation of an electrical path for punch through current. Reducing the likelihood of punch through current in this matter enables the use of transistors at higher voltages and/or enables the fabrication of smaller transistors giving rise to transistors with improved performance.

The following paragraphs provide various examples of the examples disclosed herein.

Example 1 is a field-effect transistor that includes a source, a drain, and a semiconductor material positioned between the source and the drain. The transistor also includes a first gate positioned adjacent the semiconductor material, and a second gate positioned adjacent the semiconductor material. A portion of the semiconductor material positioned between the first and second gates.

Example 2 includes the transistor as defined in Example 1, wherein the portion of the semiconductor material is a first portion. The first gate is positioned between the first portion of the semiconductor material and a second portion of the semiconductor material.

Example 3 includes the transistor as defined in Example 2, wherein the first and second portions of the semiconductor material are parts of an integrated layer of the semiconductor material.

Example 4 includes the transistor as defined in Example 3, wherein the integrated layer of the semiconductor material surrounds the first gate.

Example 5 includes the system as defined in Example 2, and further includes a bonding oxide adjacent to the first gate, the first portion of the semiconductor material coupled to the second portion of the semiconductor material via the bonding oxide.

Example 6 includes the transistor as defined in Example 5, wherein the bonding oxide is to separate the first portion of the semiconductor material from the first gate.

Example 7 includes the transistor as defined in any one of Examples 2-5, wherein the semiconductor material is a first semiconductor material. The transistor further includes a second semiconductor material. The second portion of the first semiconductor material is positioned between the first gate and the second semiconductor material.

Example 8 includes the transistor as defined in Example 7, wherein the second semiconductor material has a wider bandgap than the first semiconductor material.

Example 9 includes the transistor as defined in any one of Examples 7 or 8, wherein the first semiconductor material includes gallium and nitrogen, the second semiconductor material including aluminum, gallium, and nitrogen.

Example 10 includes the transistor as defined in any one of Examples 7-9, wherein a distance between the first gate and the second semiconductor material is less than or equal to an effective control reach of an electrical field produced by the first gate when powered.

Example 11 includes the transistor as defined in any one of Examples 1-10, wherein at least a portion of the first gate and at least a portion of the second gate are in vertical alignment.

Example 12 includes the transistor as defined in any one of Examples 1-11, wherein the first gate includes at least one of polysilicon or a refractory metal.

Example 13 includes the transistor as defined in any one of Examples 1-12, wherein a distance between the first gate and the second gate is less than a combined distance of a first effective control reach associated with the first gate and a second effective control reach associated with the second gate. The first and second effective control reaches corresponding to electrical fields to be produced by the first and second gates when the first and second gates are powered.

Example 14 includes the transistor as defined in any one of Examples 1-13, wherein a length of the first gate in a direction of electron flow along a channel between the source and the drain is greater than or equal to a length of the second gate and less than or equal to a distance between the source and the drain.

Example 15 includes the transistor as defined in any one of Examples 1-14, wherein the first gate is electrically connected to the second gate to maintain the first and second gates at a same electric potential.

Example 16 is a field-effect transistor that includes a source, a drain, and a semiconductor layer. The transistor further includes a buried gate positioned beneath a top surface of the semiconductor layer, and a top gate positioned above the top surface of the semiconductor layer. The buried gate and the top gate are to activate a channel between the source and the drain.

Example 17 includes the transistor as defined in Example 16, wherein the buried gate is embedded within the semiconductor layer. The semiconductor layer surrounds the buried gate.

Example 18 includes the transistor as defined in Example 16, wherein the buried gate is between a first portion of the semiconductor layer and a second portion of the semiconductor layer.

Example 19 includes the transistor as defined in Example 18, and further includes a bonding oxide to attach the first and second portions of the semiconductor layer.

Example 20 includes the transistor as defined any one of Examples 18 or 19, wherein the first portion of the semiconductor layer is positioned closer to the top gate than the buried gate. The second portion of the semiconductor layer positioned farther away from the top gate than the buried gate.

Example 21 includes the transistor as defined in any one of Examples 16-20, wherein the buried gate includes a different material than the top gate.

Example 22 includes the transistor as defined in any one of Examples 16-21, and further includes a semiconductor material different than the semiconductor layer. The buried gate is positioned between the semiconductor material and the top gate.

Example 23 includes the transistor as defined in Example 22, wherein the semiconductor material exhibits a wider bandgap than the semiconductor layer.

Example 24 includes the transistor as defined in any one of Examples 22 or 23, wherein the semiconductor layer includes gallium and nitrogen. The semiconductor material includes aluminum, gallium, and nitrogen.

Example 25 includes the transistor as defined in any one of Examples 22-24, wherein an effective control reach of an electrical field to be produced by the buried gate when powered is to extend into the semiconductor material.

Example 26 includes the transistor as defined in any one of Examples 16-25, wherein the top gate is to produce a first electrical field when powered and the buried gate is to produce a second electrical field when powered, the buried gate is spaced apart from the top gate by less than a combined effective control reach of the first and second electrical fields.

Example 27 includes the transistor as defined in any one of Examples 16-26, wherein a length of the buried gate in a direction of electron flow within the channel is greater than or equal to a length of the top gate and less than or equal to a distance between the source and the drain.

Example 28 includes the transistor as defined in any one of Examples 16-27, and further includes an electrical connector to maintain the top gate and the buried gate at a same electrical potential.

Example 29 is a transistor that includes a semiconductor substrate, a source, a drain, and a gate having an effective control reach to activate a channel in the semiconductor substrate between the source and the drain. The transistor further includes means for extending the effective control reach of the gate.

Example 30 includes the transistor as defined in Example 29, wherein the gate and the means for extending are in circuit.

Example 31 includes the transistor as defined in Example 30, wherein the gate and the means for extending are maintained at a same electrical potential.

Example 32 includes the transistor as defined in any one of Examples 29-31, wherein the means for extending is buried beneath at least a portion of the semiconductor substrate.

Example 33 includes the transistor as defined in any one of Examples 29-32, wherein the extending means is to extend the effective control reach of the gate to reduce a likelihood of punch through.

Example 34 is a system that includes a processing device including: a communications chip, and a transistor. The transistor includes a semiconductor material, a first gate positioned above a top surface of the semiconductor material, and a second gate positioned below a top surface of the semiconductor material.

Example 35 includes the system as defined in Example 34, wherein the second gate is embedded within the semiconductor material. The semiconductor material surrounds the second gate.

Example 36 includes the system as defined in Example 34, wherein the second gate is between a first portion of the semiconductor material and a second portion of the semiconductor material.

Example 37 includes the system as defined in Example 36, and further includes a bonding oxide to attach the first and second portions of the semiconductor material.

Example 38 includes the system as defined in any one of Examples 36 or 37, wherein the first portion of the semiconductor material is positioned closer to the first gate than the second gate. The second portion of the semiconductor material is positioned farther away from the first gate than the second gate.

Example 39 includes the system as defined in any one of Examples 34-38, wherein the second gate includes a different material than the first gate.

Example 40 includes the system as defined in any one of Examples 34-38, and further includes a semiconductor buffer layer positioned below the second gate.

Example 41 includes the system as defined in Example 40, wherein the semiconductor buffer layer exhibits a wider bandgap than the semiconductor material.

Example 42 includes the system as defined in any one of Examples 40 or 41, wherein the semiconductor material includes gallium and nitrogen. The semiconductor buffer layer includes aluminum, gallium, and nitrogen.

Example 43 includes the system as defined in any one of Examples 40-42, wherein an effective control reach of an electrical field to be produced by the second gate when powered is to extend into the semiconductor buffer layer.

Example 44 includes the system as defined in any one of Examples 34-43, wherein the first gate is to produce a first electrical field when powered and the second gate is to produce a second electrical field when powered. The second gate is spaced apart from the first gate by less than a combined effective control reach of the first and second electrical fields.

Example 45 includes the system as defined in any one of Examples 34-44, wherein a length of the second gate in a direction of electron flow between a source and a drain of the transistor is greater than or equal to a length of the first gate and less than or equal to a distance between the source and the drain.

Example 46 includes the system as defined in any one of Examples 34-45, and further includes an electrical connector to maintain the first gate and the second gate at a same electrical potential.

Example 47 is a method of manufacturing a field-effect transistor. The method includes forming a first gate, forming a semiconductor material to bury the first gate, and forming a second gate. A portion of the semiconductor material is positioned between the first gate and the second gate.

Example 48 includes the method as defined in Example 47, and further includes forming the semiconductor material by: forming a first portion of the semiconductor material, forming the first gate on the first portion of the semiconductor material, and forming a second portion of the semiconductor material over the first gate using lateral epitaxial overgrowth of the first portion of the semiconductor material.

Example 49 includes the method as defined in Example 48, and further includes forming the semiconductor material by: forming a first portion of the semiconductor material in connection with a first semiconductor wafer, forming a second portion of the semiconductor material in connection with a second semiconductor wafer, and attaching the first portion of the semiconductor material to the second portion of the semiconductor material via a bonding oxide. The first and second portions of the semiconductor material are to sandwich the first gate therebetween.

Example 50 includes the method as defined in Example 49, and further includes forming the bonding oxide on the first portion of the semiconductor material adjacent the first gate. The first gate is formed on the first portion of the semiconductor material.

Example 51 includes the method as defined in any one of Examples 48-50, wherein the portion of the semiconductor material is a first portion. The method further includes: forming a buffer layer on a semiconductor substrate, and forming a second portion of the semiconductor material on the buffer layer.

Example 52 includes the method as defined in any one of Examples 48-51, and further includes electrically connecting the first gate to the second gate to enable the First gate to be maintained at a same electric potential as the second gate when powered.