Wide bandwidth read and write memory system and method

A memory device includes a first memory array, a first read port, a second read port, and a control input port. The first memory array contains a plurality of memory cells arranged in an array configuration. The first read port is configured to read first data from a single memory cell during a single read cycle, and the second read port is configured to read second data from a group of memory cells controlled by a common word line. Further, the control input is configured to receive a mode signal indicating a functional mode for the memory device including a first read mode and a second read mode. When the mode signal indicates the first read mode, the first read port is used to read the first data. When the mode signal indicates the second read mode, the first read port is used to read out the first data and the second read port is used to read the second data.

TECHNICAL FIELD

The present invention generally relates to the field of integrated circuit memory devices and, more particularly, to systems, devices and methods to enhance read/write bandwidth for memory arrays

BACKGROUND ART

The scale of memory arrays has dramatically increased with technology progresses and increasing demands over the past few decades. In a conventional memory array, the readout circuit may occupy a significant portion of the entire chip area. In order to simplify the readout circuit, a number of columns are grouped as a logic column, and therefore a number of adjacent memory cells on one row are normally grouped together into a memory cell unit to share one word line or one X address. Write or read operations are performed on one single memory cell per cell unit in each clock cycle in the conventional memory array. For example, a 512×32 static random access memory (SRAM) normally consists of 128 rows, each of which includes 128 SRAM cells grouped into 32 memory cell units. That is, one memory cell unit corresponds to every four SRAM cells, and the four SRAM cells share one readout circuit.

During a write operation, an address decoder in an SRAM array receives row and column addresses over the address bus, and decodes the row addresses to enable a word line. Data on an input data port is written into one SRAM cell within a cell unit identified by the input column address while the data in the other three SRAM cells in the same memory cell unit remain the same. During a read operation, bit lines of all columns are first pre-charged, while the address decoder decodes the received addresses for the read operation. Once the address decoder completes address decoding, one word line is selected to connect the contents of one row of cell units to the bit lines while the pre-charging is terminated. Bit lines of one of the four columns are selected by the column address and then are sensed and amplified, thus completing a read operation.

DISCLOSURE OF INVENTION

Technical Problem

However, a conventional SRAM array having one set of address decoders can only complete one write or one read operation in one clock cycle. Multiple-port SRAM can complete multiple write and/or read operations in one clock cycle. However, the enhanced multiple read/write capability often increases the number of word lines and bit lines, SRAM cell area, control circuit complexity, design cost, and manufacturing cost. For example, the area size of a dual port SRAM cell array normally doubles the area size of a single port SRAM cell array.

Similar problems also exist in other types of memory arrays that employ word lines and bit lines to access the memory cells. The disclosed methods and systems are directed to solve one or more problems set forth above and other problems.

Technical Solution

One aspect of the present disclosure includes a memory device. The memory device includes a first memory array, a first read port, a second read port, and a control input port. The first memory array contains a plurality of memory cells arranged in an array configuration. The first read port is configured to read first data from a single memory cell during a single read cycle, and the second read port is configured to read second data from a group of memory cells controlled by a common word line. Further, the control input is configured to receive a mode signal indicating a functional mode for the memory device including a first read mode and a second read mode. When the mode signal indicates the first read mode, the first read port is used to read out the first data. When the mode signal indicates the second read mode, the first read port is used to read out the first data and the second read port is used to read out the second data.

Another aspect of the present disclosure includes a memory device. The memory device includes a memory array, a first write port, a second write port, and a control input port. The memory array is configured to contain a plurality of memory cells arranged in an array configuration. The first write port is configured to write first data into a single memory cell during a single writing cycle, and the second write port is configured to write second data into a group of memory cells controlled by a common word line during the single writing cycle. Further, the control input port is configured to receive a mode signal indicating a functional mode for the memory device including a first write mode and a second write mode. When the mode signal indicates the first write mode, the first write port is used to write the first data; when the mode signal indicates the second write mode, the second write port is used to write the second data.

Another aspect of the present disclosure includes a method for pseudo dual port memory operation of a memory device including a memory array. The memory array contains a plurality of memory cells arranged in an array configuration. The method includes providing a first address for a first operation and a second address for a second operation during a single clock cycle, and providing a first enable signal to control a first group of memory cells to start the first operation based on the first address. The method also includes latching results from the first operation, providing a control signal to switch from the first operation to the second operation, and providing a second enable signal to control a second group of memory cells to start the second operation based on the second address.

Another aspect of the present disclosure includes a static random access memory (SRAM) device. The SRAM device includes a memory array, an address decoder, a read/write control module, a write module, and a read module. The memory array is configured to receive word lines and bit lines, the memory array comprising a first number of rows and a second number of columns of memory cells, each row being controlled by a word line, each column being connected by a bit line and a complementary bit line, every third number of adjacent columns being grouped as a logical column corresponding to a bit of data and every third number of adjacent memory cells on one row being grouped as a memory cell unit. The address decoder is configured to receive an address bus and to generate a word line and a column select signal. Further, the read/write control module configured to receive control signals to generate a write mode control, a write enable and a read enable. The write module is configured to receive the write mode control, the write enable, the column address, a first write input and a second write input and to connect to drive the bit lines and complementary bit lines, the write module selects one or more sets of the third number of bit lines and complementary bit lines in every logic column to be written. The read module is configured to receive the read enable, the column address, the bit lines and the complementary bit lines and to generate a first read output and a second read output, the read module multiplexing the third number of bit lines and complementary bit lines in every logic column.

Advantageous Effects

The disclosed systems and methods may significantly enhance read/write bandwidth for memory arrays by using additional input and output ports at the memory peripheral and utilizing the bit lines. The disclosed systems and methods also provides a performance similar to that of the conventional two-port memory at a chip-area cost similar to that of the conventional one-port memory. Other advantages and applications are obvious to those skilled in the art.

BEST MODE

Mode for Invention

Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. The embodiments are used to explain the invention and not to limit the invention. One skilled in the art will exchange, adjust and improve the specific embodiments; however, these exchanges, adjustments and improvements will be included as part of the invention.

FIG. 1andFIG. 1Aillustrates an exemplary block diagram100of an input/output interface for a memory array102involving additional input/output ports to enhance the bandwidth for memory write and read operations. As shown inFIG. 1andFIG. 1A, an address bus101provides the memory array102with row and column addresses for write or read, and a control line103is used to control operations (write or read) and function modes (normal or wide bandwidth). A normal bandwidth write port104is used to input data for write in a normal bandwidth write mode, and a wide bandwidth write port105is used to input multiple data for parallel writes in a wide bandwidth write mode. Similarly, the data in the memory array102are read out through a normal bandwidth read port106in a normal bandwidth read mode, and through a wide bandwidth read port107or a second data read port in a wide bandwidth read mode. The bandwidths for read and write operations are enhanced due to the use of the wide bandwidth write and read ports105and107.

FIG. 1Billustrates an exemplary block diagram150of a memory array with enhanced read and write bandwidths in certain implementations. In addition to the input/output ports inFIG. 1A, the memory array102further comprises of an address decoder111, a read/write control module112, a write module114, memory cells113, a read module115and a read register module116. The address decoder111receives addresses from the address bus101, drives the word line and delivers the column addresses to the write module114and the read module115and read register module116. The read/write control module112comprises an optional sequential control module, a write control module and a read control module (not shown). Read/write control module112receives the control line103, and generates a read enable, a write enable and a write mode control. The write module114may receive the write enable, write mode control and column address; and deliver the data input from the normal bandwidth write port104or wide bandwidth write port105to a selected memory cell or selected memory cells. The read module115may receive the read enable and column address, and deliver data in a selected memory cell or selected memory cells directly to the normal bandwidth read port106or the read register module116. The read register module116may temporarily store the data and deliver the data to the wide bandwidth read port or second data read port107.

To enhance the write bandwidth, the exemplary memory array150is written in by two aforementioned write modes, the normal bandwidth write mode and the wide bandwidth write mode. In the normal bandwidth write mode, data coming from the normal bandwidth write port104is written to a SRAM cell selected by input row and column addresses. Three unselected SRAM cells in the same memory cell unit have high impedance, and their internal data will not be overwritten. However, in the wide bandwidth write mode, write module114allows the data in four SRAM cells included in one memory cell unit to be refreshed simultaneously. Although SRAM is used to illustrate various embodiments in this disclosure, other types of memory can also be used without departing the principles of the disclosed embodiments.

To enhance the read bandwidth, the exemplary memory array150is also read out by two aforementioned read modes, normal bandwidth read mode and wide bandwidth read mode. The read module115comprises low-speed read (sensing) modules and a high-speed read (sensing) module (not shown). The high-speed read module requires significantly more chip area than the low-speed read module. Bit lines of each individual SRAM cell are connected with its own low-speed read module for reading multiple SRAM cells in parallel at a relatively low speed, and four SRAM cells in a memory cell unit share a high-speed read module for reading out one of the SRAM cells at a faster speed. In the normal bandwidth read mode, the high-speed read module first senses and amplifies data from one SRAM cell as specified by the column address. The data are outputted to the normal bandwidth read port106. In the wide bandwidth read mode, at first the high-speed read module outputs the data in the selected SRAM cell to the normal bandwidth read port106. Then the data in the other unselected SRAM cells are outputted in parallel to the wide-bandwidth read port107using their own low-speed read sensing modules. Alternatively, the data in the unselected SRAM cells are stored in the read register module116and ready for output sequentially through the second data read port107while another row is being read and outputted to normal bandwidth read port106in the normal bandwidth read mode. Therefore, by using two read ports, an equivalent configuration of pseudo dual read port memory is formed with a single port memory array to enhance the read bandwidth.

FIG. 2illustrates a block diagram200of a conventional SRAM array allowing one-bit read/write operation. SRAM cells203,204,205and206on four different columns are controlled by one common word line WL0207, and SRAM cells222,223,224and225on four different columns are controlled by another common word line WL1217.

During a write cycle, a write-enable signal WE226is enabled, and data are written into a memory cell selected by a column address228. The column address of “00” selects the SRAM cells203or222; the column address of “01” selects the SRAM cells204or223; the column address of “10” selects the SRAM cells205or224; and the column address of “11” selects the SRAM cells206or225. In particular, data are inputted to write modules208,209,210and211through the normal bandwidth write port104, and further passed to the set of bit lines BL and BL_N (i.e. bit line bar, the differential signal of BL, as indicated by218inFIG. 2together with the bit line BL) selected by the column address228while the unselected three sets of bit lines BL and BL_N are kept high-impedance. For example, when the column address is “01”, data are sent to the bit lines219which are connected to the SRAM cells223and204, and the other bit lines218,220and221are kept as high-impedance. If WL0207is enabled, the data are written into the SRAM cell204and the data in all the other SRAM cells remain the same.

During a read cycle, if one of the word lines WL1217and WL0207is enabled, the decoders212and213receive the column address228and select one of the four SRAM cells in the corresponding row. The data in the selected SRAM cell is read out by the high speed readout module214and output to a normal bandwidth output port106.

FIG. 3Aillustrates an exemplary block diagram300of a SRAM array which performs a write operation based on one bit of input data. AlthoughFIG. 3Aand/or other figures in this disclosure use a same number or label to refer a device or component shown in a conventional device, it is understand that the device or component described in the disclosed embodiments is for the convenience of illustration and is not necessarily identical to the ones shown in the conventional device. As shown inFIG. 3A, SRAM cells203,204,205and206on four different columns are controlled by one common word line WL0207, and SRAM cells222,223,224and225on four different columns are controlled by another common word line WL1217. Data are written into a memory cell selected by a column address228. The column addresses of “00”, “01”, “10”, and “11” select SRAM cells203or222,204or223,205or224, and206or225, respectively. A write enable226and a write mode control313are generated by a write control logic in the read/write control module112. In a write operation, the write enable WE226is first enabled, and the write mode control313is used to select the write mode as the normal bandwidth write mode or the wide bandwidth write mode. The write module114includes write modules308,309,310and311.

In the normal bandwidth write mode, one bit of data are inputted to one of the write modules308,309,310or311through a normal bandwidth write port104during each write cycle. Data are further written to the set of bit lines BL and BL_N selected by the column address228while the unselected three sets of bit lines BL and BL_N are connected as high-impedance. In certain embodiments, the word line WL0207is selected and the column address is “01”. Data are sent to the bit lines319which are connected to the memory cells223and204, and the other bit lines318,320and321are connected as high-impedance. When WL0is enabled, the data are written into the SRAM cell204, and the data in all the other SRAM cells remain the same.

In the wide bandwidth write mode, four bits of data are provided to the write modules308,309,310and311, respectively, from a wide bandwidth write port105. Column address228is not used in this mode. Four bits of data are sent to the bit lines318,319,320and321through line A (329), line B (330), line C (331), and line D (332), respectively. In one embodiment, the word line WL0207is enabled, the data are written in parallel into the SRAM cells203,204,205and206, and the data in SRAM cell222,223,224and225remain the same.

FIG. 3Billustrates a truth table350for the write modules inFIG. 3A. In one embodiment as shown in row352, the write enable WE226is disabled (i.e., WE226is “0”), and the outputs of the write modules308,309,310, and311are all connected as high-impedance (Z). In another embodiment as shown in row354, both the WE226and the write mode control313are enabled. The wide bandwidth write mode is activated (i.e., write mode control is ‘1’). Data and the complimentary data A328and A_N343, B329and B_N344, C330and C_N345, and D331and D_N346are sent in parallel to the bit lines318,319,320and321that are connected to the write modules308,309,310and311, respectively. In certain embodiments as shown in rows356,358,360and362, the WE226is enabled, and the write mode control313is disabled. The normal bandwidth write mode is activated. When the column address228is “11” as shown in row362, the data BIT_IN is inputted from the normal bandwidth write port104. BIT_IN341and the complementary BIT_IN_N342are written to the set of bit lines BL and BL_N connected with the SRAM cells225and206. Similarly, when the column address228is “00”, “01” or “10” as shown in rows356,358and360, the data BIT_IN are inputted from the normal bandwidth write port104, and BIT_IN and BIT_IN_N are written to the bit lines BL and BL_N connected with the SRAM cells222and203,223and204, or224and205, respectively. Other unaddressed bit lines are kept in high-impedance Z.

FIG. 4Aillustrates an exemplary block diagram400of the SRAM array in a wide bandwidth read mode for a parallel read operation. SRAM cells203,204,205and206on four different columns are controlled by one common word line WL0207, and SRAM cells222,223,224and225on four different columns are controlled by another common word line WL1217. All columns share a high-speed read module214, and each column has its own separate low-speed read modules411,412,413and414, respectively. The high-speed read module214consumes a larger chip area than the low-speed read modules411,412,413and414although the read speed of214is faster than that of the low-speed read modules. High-speed read module214and low-speed read modules411,412,413and414may be included in read module115(inFIG. 1B).

Data in SRAM cells on one row are read out within two clock cycles. In certain embodiments, high speed read module214is capable of finishing the read sensing of data on bit lines within the first clock cycle while the read process of low speed read modules411,412,413and414takes longer than one clock cycle and therefore may be completed in the second clock cycle. For example, data in the SRAM cell203are read out to normal bandwidth read port439(106inFIG. 1) during the first clock cycle, and data in the SRAM cells204,205and206are read out to the wide bandwidth read port407(107inFIG. 1) during the second clock cycle.

More particularly, during the first clock cycle, the word line WL0207is enabled, and the bit lines of the SRAM cell203are selected by the multiplexers212and213as specified by the column address228. Data in the SRAM cell203are directly read to the high speed read module214, the sensed and amplified result is outputted on bus439. While the data in the SRAM cell203is read by high speed read module214, the data from the SRAM cells203,204,205and206are also sensed, and amplified by the low speed read modules414,411,412, and413.

During the second clock cycle, the word line WL0207remains enabled, the signals in the SRAM cells203,204,205and206are still sensed and amplified by the low-speed read modules414,411,412and413if the sensing process is not completed in the first clock cycle. By the end of the second clock cycle, the signals415,418,419, and420are outputted in parallel to the wide bandwidth read port407. Signal415may also be provided by read module414to the wide bandwidth read port407, but may be ignored because the SRAM cell203is already read during the first clock cycle. In addition, similarly, data in each of SRAM cells203,204,205, and206may also be read out through high speed read module214during the first clock cycles while the remaining data in remaining cells are read out in the second clock cycles.

Further, wide bandwidth read port407may be controlled by a read control module to output a particular signal415,418,419, or420. Alternatively, wide bandwidth read port407may provide all signals415,418,419, and420, and an outside multiplexer may be used to select a particular signal415,418,419, or420. Other configurations may also be used.

FIG. 4Billustrates an exemplary block diagram450of a SRAM array implemented in the wide bandwidth read mode for sequential read operations. SRAM cells203,204,205and206in four different columns are controlled by one common word line WL0207, and SRAM cells222,223,224and225on four different columns are controlled by another common word line WL1217. Similar toFIG. 4A, all columns share a high-speed read module214, and each column has its separate low-speed read modules411,412,413and414, respectively. The high speed read module214is capable of completing the read sensing of data on bit lines within a first clock cycle while the read process of low speed read modules411,412,413and414takes longer than one clock cycle and therefore may be completed in a second clock cycle. Latches421,422,423, and424are provided to latch outputs from low speed read modules411,412,413and414, respectively.

During the first clock cycle, the WL0207is enabled. The SRAM cell203is then selected by the column address228using the two-bit multiplexers212and213, and the data in SRAM cell203is sent to the high speed read module214and the output signal is then provided to the normal bandwidth data port439(106inFIG. 1). Thus, SRAM cell203is read out during the first clock cycle on normal bandwidth data port439(106inFIG. 1). While the data in the SRAM cell203is read, the data from the SRAM cells203,204,205and206are also sensed, and amplified by the low speed read modules414,412,412and413.

During the second clock cycle, the word line WL0207remains enabled, the signals in the SRAM cells203,204,205and206are still sensed and amplified by the low-speed read modules414,411,412and413if the sensing process is not completed in the first clock cycle. The read out data in the low-speed read modules414,411,412and413are held in the latches421,422,423and424, respectively. The read control module416controls the multiplexer409to output the data held in latch422(content of memory cell204) to a second data read port440(e.g., wide bandwidth read port107inFIG. 1). Thus, SRAM cell204is read out during the second clock cycle on second data read port440(i.e. wide bandwidth data port107inFIG. 1) through multiplexer409under the multiplexer control signal generated by read control module416.

During the third clock cycle or a subsequent clock cycle, the WL0207is no longer enabled, and the read control module416controls the multiplexer409to output the data held by the latch423to the second data read port440directly. Thus, content of SRAM cell205is read out during the third clock cycle on second data read port440(i.e. wide bandwidth data port107inFIG. 1). At the same time, another word line (e.g., WL1217) may be enabled and a second data from another SRAM cell on another row (e.g., SRAM cell223) may be readout using high speed read module214to normal bandwidth data port439(i.e.106inFIG. 1). Thus, at the end of this clock cycle, data corresponding to two different addresses (cell223and cell205) are presented at two separate ports simultaneously.

During the fourth clock cycle, the read control module416controls the multiplexer409to output the data (SRAM cell206) in the latch424directly to the second data read port440. Therefore, by the end of the fourth clock cycle, the data in the memory cells203,204,205and206are read out sequentially within four consecutive clock cycles from the normal bandwidth data port439(106inFIG. 1) and the second data read port440(107inFIG. 1).

More specifically, to take full advantage of the read bandwidth, the WL0207can be disabled in the third clock cycle, bit lines BL and BL_N may be pre-charged, and the next word line WL1217may be enabled. The SRAM cell223is then selected by the column address228using the multiplexer212and213, and the data in the SRAM cell223are outputted to the high speed read module214and then to the normal bandwidth data port439(i.e.106inFIG. 1). Also, during the third clock cycle, one of the latched contents of individual SRAM cells203,204,205and206can be read out from the bus440(i.e. wide bandwidth data port107inFIG. 1) through multiplexer409under the multiplexer control signal generated by read control module416. And contents of memory cell222,223,224and225are sensed and read by slow read modules414,411,412and413, respectively at the same time.

During the fourth clock cycle, the WL1217remains enabled. The data sensing and reading of memory cells222,223,224and225are completed in the low-speed read modules414,411,412and413. If the read control module416does not update the latches421,422,423and424, then in fourth clock cycle and the next clock cycle or cycles, each data of memory cells203,204,205and206may be outputted to bus440(107inFIG. 1) under the multiplexer409control signal generated by read control module416. Alternatively, if read control module416updates the latches421,422,423and424to latch in the sensed and read memory contents of memory cells222,223,224, and225, then data of either memory cells222,223,224or225may be outputted to bus440(107inFIG. 1) through multiplexer409under the multiplexer control signal generated by read control module416. Thus, data are pipelined through both the wide bandwidth read port107and the normal bandwidth read port106.

In addition to using more input/output ports, the write/read bandwidths are further enhanced by applying the sequential read/write control module which allows a write operation to follow a read operation within one clock cycle, thus may form pseudo dual read/write ports. All bit lines are pre-charged while the address decoder first decodes the read addresses. Upon generating the read addresses, the pre-charging is terminated and the word line is enabled. The read module captures the data and is then disconnected from the selected bit lines. While the read module goes on to amplify the captured data, the write-enable signal becomes valid and the write address is decoded to enable a word line for write. Data are written into the selected bit line by a write module. The write operation may be done to either the same cells on the same word line with the cells being read out or cells on different word lines. The read operation in the above-mentioned write-after-read operation can be substituted with another write operation, and thus two write operations in one clock cycle using the same or similar control mechanism.

FIG. 5illustrates a timing diagram500of SRAM control signals and output signals in a clock cycle in the SRAM array as shown inFIG. 2. CLK501is a clock signal, and ADDRESS502is an address bus signal. WL503is the word line signal for the SRAM cells. WL503is enabled after the address decoder decodes ADDRESS502and is disabled at falling edge of the clock cycle CLK501. Assuming the data contained in the SRAM cell is “1”. Bit lines BL504and BL_N505are pre-charged to high till the ADDRESS502is decoded and the WL503is enabled. The BL remains at a high level while BL_N505is slowly pulled down by the content of the SRAM cell. A read circuit samples and amplifies the levels of the BL504and BL_N505at sampling time506to produce read out data SA507and SA_N508. At the same time, the BL504and BL_N505are disconnected from the read circuit. A digital level of “high” is properly outputted from the signals SA507and SA_N508.

FIG. 6Aillustrates an exemplary timing diagram600of increasing write bandwidth by using two address decoders to add a write operation in a read clock cycle such that a read operation and a write operation can be performed in one clock cycle. CLK501is the clock signal. ADDR_R601is a first address signal for the read operation. ADDR_W602is a second address signal for the write operation. WL_R604is a word line signal enabling a row of SRAM cells for read. WL_W605is a word line signal enabling a row of SRAM cells for write. WE_DELAY603is the write mode control signal. In one embodiment where data to be read is “1” and the data to be write is “0”, BL606and BL_N607are pre-charged to “1” at the beginning of the read clock cycle, and the pre-charge completes before ADDR_R601is decoded and WL_R604is enabled. Data in BL_N607slowly drops in order to restore to “0”. At a sampling time506, the read module214senses and amplifies the data in the BL606and BL_N607to be SA608and SA_N609, and then disconnect from the BL606and BL_N607. Subsequently, WE_DELAY603is enabled and ADDR_W601has already been decoded. Data “0” and “1” to be written are sent to BL606and BL_N607, respectively. The write drivers which drive the bit lines in this embodiment has both a pull up and pull down capability, thus the write action is not limited to after a bit lines pre-charging. BL606is immediately pulled down and BL_N607is pulled up. Read out data “1” has already been properly sampled, sensed and outputted from the SA608, and the write-indata “0” is properly written to the BL606as well. The SRAM array can read data first and then write data. Alternatively, the read can also be replaced with a write so that two write operations happen sequentially, no bit liens pre-charging necessary between the two write actions, thus may form pseudo dual write ports.

FIG. 6Aillustrates an exemplary timing diagram600of increasing write bandwidth by using two address decoders to add a write operation in a read clock cycle such that a read operation and a write operation can be performed in one clock cycle. CLK501is the clock signal. ADDR_R601is a first address signal for the read operation. ADDR_W602is a second address signal for the write operation. WE_DELAY603is the delay write enable control signal which enables the write word line after a certain delay in timing. WL_R604is a read word line for a row of SRAM cells being read. WL_R604is active after the decoding of the read address601and is disabled before WE_DELAY603is active. WL_W605is a word line signal selecting a row of SRAM cells for write. WL_W605is enabled after WE_DELAY603is active and is disabled before the next rising edge of CLK501.

In one embodiment, where data to be read is “1” and the data to be write is “0”, BL606and BL_N607are pre-charged to “1” at the beginning of the read clock cycle, and the pre-charge is completed before ADDR_R601is decoded and WL_R604is enabled. When WL_R604is active. BL_N607is slowly pulled down by memory cell controlled by WL_R604. At sampling time506, the read module214senses the data on BL606and BL_N607and later amplifies the data to be read out as “1” on SA and SA_N ports. Also, at sampling time the read module214are disconnected from the BL606and BL_N607. Then, Data “0” and “1” are written on to BL606and BL_N607, respectively. BL606is immediately pulled down and BL_N607is pulled up. WE_DELAY603enabled the word line WL_W605which is selected by the write address decoder through decoding ADDR_W602. A data “0” is then stored on the memory cell on bit line BL606and BL_N607, which is enabled by word line WL_W605. Thus, the SRAM array can read data first and then write data in the same clock cycle. Alternatively, the read operation can also be replaced by a write operation so that two write operations can be performed in the same clock cycle, thus may form pseudo dual write ports.

FIG. 6Billustrates an exemplary block diagram650of an address decoder receiving two addresses and comprising two decoders to sequentially select one of the two addresses in one clock cycle. The word lines for read611are decoded from ADDR_R601by a decoder610, and the word lines for write612are decoded from ADDR_W602by a decoder615. Before the WE_DELAY603is enabled, the word line read selection signal611is outputted as target word lines613to allow reading from a particular target row. When WE_DELAY603is enabled, the word line write selection signal612is outputted as the target word lines613to allow writing to the target SRAM cell. Read and write operations may be targeted to different rows.

FIG. 6Cillustrates an exemplary timing diagram of using one address decoder to increase the write bandwidth by adding a write operation during a read clock cycle. The sequential read and write operations are the same as inFIG. 6A, except that read and write addresses are inputted sequentially on one address bus ADDR632. The read address is decoded from ADDR632before WL_R604is enabled, and later in the clock cycle, the write address is decoded from ADDR632before WL_W605is enabled. The read and write operations can be performed on the same SRAM cell (the read address and write address are the same) or on two different SRAM cells (the read address and write address are different from each other).

Operation is similar toFIG. 6A. In the embodiment where both read and write operations are done to the same cell, the data in the bit lines BL606and BL_N607are sensed and amplified to SA608and SA_N609at a time of506before the write operation refreshes the data. As a result, data originally existing in the SRAM cell has already been properly recorded from the SA, and other data are properly written to the BL as well. The SRAM array can read data first and then write data. Alternatively, the read can also be replaced with a write so that two write operations happen sequentially.

FIG. 6Dillustrates an exemplary block diagram680of an address decoder that comprises one decoder for sequentially decoding a write address and a read address from one address ADDR616in one clock cycle as inFIG. 6C. As shown inFIG. 6D, decoder610is coupled to a plurality of pass gates, for example, pass gates620,621,622and623, and an output end of each pass gate is connected to ground through a NMOS transistor. At the beginning of the clock cycle, bit lines are pre-charged, and the pass gates620,621,622and623are at first closed. The NMOS transistors624,625,626and627are enabled to set “0” to all word lines. A read address inputted through the address bus ADDR616is decoded by the decoder610. The decoding results are passing through the pass gates620,621,622and623which are enabled by enable signal618to enable a word line in word lines613for reading. At the rising edge of WE_DELAY603, the pass gates620,621,622and623are disabled and the NMOS transistors624,625,626and627are turned on again to discharge the word line previous charged for reading. Then the pass gates620,621,622and623are turned on again, this time passing the write word line selection signal generated by decoder610based on the write address on ADDR632, to enable one of the word lines in613to select a row of memory cells for writing. Thus, write or read operations can be performed on SRAM cells on two different rows.

A plural number of SRAM arrays may share one read (sensing) module115(as inFIG. 1B) to save chip area.FIG. 7illustrates a method for employing one read module to serve two SRAM arrays. The bit lines of two separate SRAM arrays705and706having the same column address are multiplexed by an array multiplexer included in the read module702. The array multiplexer is controlled by a select signal, selecting data on either bit lines705or706for sensing and amplifying. Within one clock cycle, a write operation may be performed on one of SRAM array705or706while either a write or a read operation may be performed on the other SRAM array706or705. In one embodiment, both SRAM arrays are under write operations. One word line703in the SRAM array705is enabled, and data are written into the cells controlled by703through a write port708; at the same time, another word line711is enabled in the SRAM array706, and data are written into the cells controlled by word line711through a write port709. In another embodiment, a read and a separate write operation are performed on the SRAM arrays705and706, respectively. The word line703in the SRAM array705is enabled, and data in memory cells controlled by word line703are read out by a read module702to a read port704; at the same time, the word line711is enabled in the SRAM array706, and data are written into cells controlled by711through the write port709. The write port can be either the normal or the wide bandwidth write port, and the read ports can be either the normal or the wide bandwidth read port.

The disclosed methods and systems may significantly enhance read/write bandwidth for memory arrays by using additional input and output ports and/or adjusting timing sequences for read and write operations. While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art.

INDUSTRIAL APPLICABILITY

The disclosed devices and methods may be used in various applications in stand-alone memory devices and embedded memory devices in processors, SOC chips, computing systems, communication and other digital systems. For example, the disclosed devices and methods may be used in high performance processor cache applications, high-efficient data processing applications crossing multiple levels of memory hierarchy or even crossing multiple levels of networked systems.