Power switch

A power switch device includes a first terminal intended to be connected to a source of a first supply potential, a second terminal configured to supply a second potential, and a third terminal intended to be connected to a second source of a third supply potential. The device includes a first PMOS transistor having a source connected to the second terminal and a drain connected to the third terminal, a second PMOS transistor having a source connected to the second terminal, and a third PMOS transistor having a source connected to the first terminal and a drain connected to the drain of the second transistor. A control circuit generates gate control signals to control operation of the first, second and third PMOS transistors dependent on the first, second, and third supply potentials.

PRIORITY CLAIM

This application claims the priority benefit of French Application for Patent No. 2108858, filed on Aug. 24, 2021, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.

TECHNICAL FIELD

The present disclosure relates generally to electronic circuits and, more particularly, to power switches.

BACKGROUND

Power switches are circuit elements, for example, of integrated circuits, which receive a plurality of signals and provide, at an output terminal of the switch, one signal selected from the received signals. The signal selected from the received signals is determined based on at least one control signal provided to the power switch.

The power switches receive power potentials and supply a power potential selected from the received power potentials.

Known power switches suffer from various drawbacks.

There is a need to overcome at least some of the disadvantages of known power switches.

For example, it would be desirable to have a power switch that is less bulky than known power switches.

For example, it would be desirable to have a power switch implemented with metal oxide semiconductor (MOS) transistors configured to hold a lower maximum gate-to-source voltage than the power potentials received by the power switch and the power potential provided by the power switch.

For example, it would also be desirable to have a power switch and a switch control circuit that is powered by the power potentials received by the power switch and the power potential supplied by the power switch, and which is implemented with MOS transistors configured to hold a maximum gate-to-source voltage substantially equal to or equal to the maximum gate-to-source voltage that the MOS transistors of the switch can withstand, the latter being lower than at least one of the voltages received and supplied by the switch.

For example, it would be desirable to have a power switch and a switch control circuit that reduces current leakage in the switch.

SUMMARY

One embodiment addresses all or some of the drawbacks of known power switches.

One embodiment provides a device comprising: a first terminal for connection to a first voltage source supplying a first power supply potential referenced to ground; a second terminal configured to supply a second supply potential referenced to ground; a third terminal for connection to a second voltage source supplying a third power supply potential referenced to ground; a first PMOS transistor having a source connected to the second terminal and a drain connected to the third terminal; a second PMOS transistor having a source connected to the second terminal; and a third PMOS transistor having a source connected to the first terminal and a drain connected to the drain of the second PMOS transistor.

According to one embodiment, the device further comprises a control circuit for the first, second, and third transistors, the control circuit being configured to receive the first, second, and third supply potentials.

According to one embodiment, the control circuit is configured to receive a first binary signal, and to control the first, second, and third transistors at least based on the first signal, a first binary state of the first signal corresponding to a request to the control circuit to switch the second and third transistors to the on state and switch the first transistor to the off state, and a second binary state of the first signal corresponding to a request to the control circuit to switch the second and third transistors to the off state and switch the first transistor to the on state.

According to one embodiment, the control circuit is further configured to condition a switching to the on state of the second and third transistors to the fact that the first potential is non-zero.

According to one embodiment, the control circuit is further configured to compare the third supply potential to ground, and to force a switching of the third transistor to the on state if the third supply potential is zero.

According to one embodiment, the control circuit comprises: a first circuit configured to supply a first high reference potential equal to A times the first supply potential and a first low reference potential equal to B times the first supply potential, with A and B positive numbers strictly less than 1, A being greater than B; and a second circuit configured to supply a second high reference potential equal to C times the second supply potential and a second low reference potential equal to D times the second supply potential, with C and D positive numbers strictly less than 1, C being greater than D.

According to one embodiment, a maximum potential difference that can be applied between the gate and source of each of the first, second and third transistors determines the numbers A, B, C and D.

According to one embodiment, the control circuit comprises: a third circuit configured to receive a second binary signal comprised between ground and the first high reference potential and to provide, at the gate of the third transistor, a third binary signal determined by the second signal and comprised between the first low reference potential and the first supply potential; a fourth circuit configured to receive a fourth binary signal comprised between ground and the second high reference potential and to provide, at the gate of the second transistor, a fifth binary signal determined by the fourth signal and comprised between the second low reference potential and the second supply potential; and a fifth circuit configured to receive a sixth binary signal comprised between ground and the second high reference potential and to provide, at the gate of the first transistor, a seventh binary signal determined by the sixth signal and comprised between the second low reference potential and the second supply potential.

According to one embodiment, the control circuit comprises: a sixth circuit configured to be powered between the second high reference potential and ground, to receive the first binary signal, to provide the fourth and sixth signals; a seventh circuit configured to be powered between the first high reference potential and ground, to receive a binary signal from the sixth circuit comprised between the second high reference potential and ground, and to provide the second binary signal at least from the binary signal received from the sixth circuit.

According to one embodiment, the sixth circuit is configured to determine the state of the fourth and sixth signals and of the binary signal that the sixth circuit provides to the seventh circuit at least based on the first signal.

According to one embodiment: the control circuit further comprises an eighth circuit configured to receive the first high reference potential, to detect when the first high reference potential is strictly positive, and to provide to the sixth circuit an eighth binary signal comprised between the second high reference potential and ground and having a binary state determined by the said detection, and the sixth circuit is configured to determine the state of the fourth and sixth signals and of the binary signal that the sixth circuit provides to the seventh circuit at least based on the first signal and the eighth signal.

According to one embodiment, the seventh circuit comprises a ninth circuit configured to receive the binary signal received from the sixth circuit and provide a ninth binary signal determined by the received binary signal comprised between ground and the first high reference potential, the seventh circuit being configured to determine the state of the second binary signal at least based on the ninth binary signal.

According to one embodiment: the control circuit comprises a tenth circuit configured to supply a third high reference potential equal to E times the third supply potential, with E a positive number strictly less than 1 determined by the maximum potential difference that can be applied between the gate and the source of each of the first, second and third transistors; the control circuit comprises an eleventh circuit configured to receive the third high reference potential, to detect when the third high reference potential is strictly positive, and to provide the seventh circuit with a tenth binary signal comprised between the first high reference potential and ground and having a binary state determined by said detection; and the seventh circuit is configured to determine the state of the second binary signal at least based on the binary signal received from the sixth circuit and the tenth signal.

According to one embodiment, the first, second, and third transistors are drift PMOS transistors.

According to one embodiment, the device further comprises the first and second voltage sources.

DETAILED DESCRIPTION

For the sake of clarity, only the operations and elements that are useful for an understanding of the embodiments described herein have been illustrated and described in detail. In particular, the various usual electronic circuits and systems in which a power switch may be provided have not been detailed, as the described embodiments are compatible with such usual circuits and systems.

FIG.1illustrates one embodiment of the device1comprising a power switch2and a circuit3for controlling the switch2.

The switch2, delineated by dashed lines inFIG.1, comprises a terminal200, a terminal202and a terminal204.

The terminal200is intended to receive a supply potential Vbat, for example referenced to the ground GND and positive. In other words, the terminal200is intended to be connected to a voltage source4supplying the potential Vbat to terminal200. For example, the voltage source4is a battery. For example, the potential Vbat has values up to 3.6 V. For example, the value of the potential Vbat may vary during operation of the device1, for example between a zero value and a maximum value, for example equal to 3.6 V.

The terminal204is intended to receive a supply potential Vdd, for example referenced to the ground GND and positive. In other words, the terminal204is intended to be connected to a voltage source5supplying the potential Vdd to terminal204. For example, the voltage source5is a main power source of a system comprising the device1. For example, the potential Vdd has a nominal value of 3.6 V. For example, the value of the potential Vdd may vary during operation of the device1, for example between a zero value and a maximum value, for example equal to 3.6 V. For example, the potential Vdd has a maximum value when the device1is connected to the main power supply, and a zero value otherwise.

The terminal202is configured to supply (i.e., output) a potential Vsw, for example referenced to ground GND and positive. For example, the potential Vsw is generated from the potentials Vbat and Vdd received by the switch2. For example, the potential Vsw is the potential for supplying one or more electronic circuits coupled to the terminal202, or, in other words, the terminal202is coupled to one or more electronic circuits configured to be supplied by the potential Vsw.

The switch2comprises a transistor T1. The transistor T1is a P-channel MOS, or PMOS, transistor. The source-drain path of transistor T1couples terminal202to terminal204. The switch2comprises a single transistor, namely transistor T1, between its terminals202and204. For example, the transistor T1has its source S1connected to terminal202and its drain D1connected to terminal204. The source S1of the transistor T1is connected to the body region of the transistor T1. The intrinsic diode Di1of transistor T1thus has its anode on the terminal204side, and its cathode on the terminal202side.

The switch2comprises a transistor T2and a transistor T3with source-drain paths coupled in series between the terminals202and200. The transistors T2and T3are P-channel MOS, or PMOS, transistors. The transistors T2and T3couple the terminal202to terminal200. Between the terminals202and200, the switch2comprises only two transistors, namely transistors T2and T3. For example, transistor T2has its source S2connected to terminal202. The source S2of the transistor T2is connected to the body region of transistor T2. The intrinsic diode Di2of transistor T2thus has its anode on the terminal200side, and its cathode on the terminal202side. For example, transistor T3has its source S3connected to terminal200and its drain D3connected to the drain D2of the transistor T2. The source S3of transistor T3is connected to the body region of transistor T3. The intrinsic diode Di3of transistor T3thus has its anode on the terminal202side, and its cathode on the terminal200side.

The switch2is controlled by means of the signals cmd1, cmd2, and cmd3applied to the gate G1of the transistor T1, the gate G2of transistor T2, and the gate G3of transistor T3, respectively. For example, depending on the control signals cmd1, cmd2and cmd3, the potential Vsw on the terminal202of switch2is selectively derived from the potential Vbat or the potential Vdd. In other words, depending on the control signals cmd1, cmd2, and cmd3, the potential Vsw is equal to the potential Vbat (neglecting the voltage drops in the transistors T2and T3) or the potential Vdd (neglecting the voltage drop in transistor T1).

Compared to known power switches, the switch2comprises only one PMOS transistor between its terminals202and204, namely the transistor T1, resulting in the switch2being less bulky than known switches.

Preferably, transistor T1is half the size as each of the transistors T2and T3, so that the impedance seen on terminal202when transistors T2and T3are in the off state and the transistor T1is in the on state is the same as when the transistors T2and T3are in the on state and transistor T1is in the off state.

For example, the switch2allows circuits to be powered with the potential Vsw derived from the potential Vdd when the potential Vdd is greater than a threshold Vth, and with the potential Vsw derived from the potential Vbat when the potential Vdd is less than the threshold Vth, for example when the potential Vdd is zero.

For example, the source5delivers a potential Vdd higher than the threshold Vth if the device1is connected to a main power supply and a potential Vdd lower than the threshold Vth, or even zero, if not. For example, source4is a battery of the device1. The switch2then makes it possible to maintain a non-zero supply potential Vsw when the device1is disconnected from the main power supply5and the potential Vdd becomes zero, by coupling the terminals200and202(supply on battery4), and, conversely, to save the battery4when the device1is coupled to the main power supply and the potential Vdd is higher than the threshold Vth, by coupling the terminals204and202(supply on the main power supply5).

According to one embodiment, the device1comprises a circuit6(“RST” block inFIG.1) configured to provide a binary signal EN to a first binary state when the potential Vdd is lower than the threshold Vth and to a second binary state when the potential Vdd is lower than the threshold Vth. For example, the circuit6comprises a terminal configured to provide the signal EN, and a terminal configured to receive the potential Vdd. For example, when the potential Vdd increases and exceeds the threshold Vth, the signal EN switches from its first binary state to its second binary state.

For example, the circuit6is powered by the potential Vsw, and then comprises a power terminal receiving the potential Vdd, and a power terminal connected to ground GND.

Preferably, the first binary state of the signal EN is a low state corresponding to the ground potential GND and the second binary state of the signal EN is a high state corresponding to the potential Vsw. Thus, when the potential Vsw is zero, the signal EN is by default in the low state, i.e., at ground GND.

The control circuit3is configured to control the transistors T1, T2and T3. The circuit3receives the potentials Vdd, Vsw and Vbat.

According to one embodiment, the signal cmd1is a binary signal whose high state corresponds to the potential Vsw, and whose low state corresponds to the ground potential GND, signal cmd2is a binary signal whose high state corresponds to the potential Vsw and whose low state corresponds to the ground potential GND, and signal cmd3is a binary signal, the high state of which corresponds to the potential Vbat and the low state corresponds to the ground potential GND.

According to one embodiment, the circuit3is configured to control the transistors T1, T2and T3at least based on the signal EN. The first binary state, for example the low state of the EN signal instructs the circuit3to drive the transistors T1, T2, and T3to electrically couple the terminals200and202and to electrically isolate the terminals204and202, and the second binary state, for example, the high state, of the EN signal instructs the circuit3to drive the transistors T1, T2, and T3to electrically couple the terminals204and202and to electrically isolate the terminals200and202. In other words, the first binary state of the signal EN corresponds to a request to the circuit3to switch transistors T2and T3to the on state and switch the transistor T1to the off state, and the second binary state of the signal EN corresponds to a request to the circuit3to switch the transistors T2and T3to the off state and switch the transistor T1to the on state.

For example, the case is considered where the potential Vdd is higher than the threshold Vth and the potential Vsw is non-zero. In this case, when the signal EN is in its second binary state, the circuit3applies, for example, the low state of the signal cmd1to the gate G1of the transistor T1, which is then in the on state, the high state of the signal cmd2to the gate G2of the transistor T2, which is then in the off state, and the high state of the signal cmd3to the gate of the transistor T3, which is then in the off state.

Again, by way of example, the case is considered where the potential Vbat is non-zero, the potential Vsw is non-zero and the potential Vdd is lower than the threshold Vth. In this case, the signal EN is in its first binary state and the circuit3applies, for example, the high state of the signal cmd1to the gate G1of the transistor T1which is then in the off state, the low state of the signal cmd2to the gate G2of the transistor T2which is then in the on state, and the low state of the signal cmd3to the gate G3of the transistor T3which is then in the on state.

Again, by way of example, when the potentials Vsw and Vbat are zero, the low state of the signal cmd1, when applied to the gate G1of the transistor T1, does not allow the transistor T1to be switched to the on state. However, the application of a non-zero potential Vdd on the terminal204causes a current to flow from the terminal204to the terminal202, via the diode Di1, which allows the potential Vsw to increase. The signal cmd1is maintained at its low state, and the increase in potential Vsw causes the voltage between the gate G1and the source S1, or the gate-source voltage of the transistor T1, to become sufficient for the transistor T1to switch to the on state and thus couple terminals204and202. Preferably, during this operating phase, the circuit3applies the high state of the signal cmd2to the gate G2of the transistor T2, so that the gate-source voltage of the transistor T2remains zero and the transistor T2remains in the off state, thereby avoiding current leakage from the terminal204to the terminal200, via the diode Di1or the transistor T1in the on state, the transistor T2and the diode Di3.

Again, by way of example, when the potentials Vsw and Vdd are zero, the application of the low level of the signal cmd3to the gate G3of the transistor T3makes it possible, when the potential Vbat is sufficiently high, to switch the transistor T3to the on state. On the other hand, the low level of the signal cmd2, when applied to the gate G2of the transistor T2, does not allow the transistor T2to be switched to the on state. However, because the transistor T3is in the on state, a current flows from the terminal200to the terminal202, via the transistor T3which is in the on state, and the diode Di2, and the potential Vsw increase. The increase of the potential Vsw and the maintenance of the signal cmd2in the low state cause the voltage between the gate G2and the source S2, or the gate-source voltage of the transistor T2, to become sufficient for the transistor T2to switch to the on state. The two transistors T2and T3in the on state then couple the terminals204and202, and the potential Vsw is then substantially equal to the potential Vbat. Preferably, during this operating phase, the circuit3applies the high state of signal cmd1to the gate G1of the transistor T1, so that the transistor T1remains in the off state, thus avoiding current leakage from the terminal200to the terminal204via the transistors T3, T2and T1.

FIG.2represents an example of one embodiment of a method for controlling the switch2ofFIG.1, for example implemented by the circuit3.

In a step300(block “EN?”), the circuit3observes the binary state of the signal EN.

In the step300, if the signal EN is in its second binary state (output Vdd of block200), for example the high state, this means that the circuit3must electrically couple the terminals204and202, and electrically isolate the terminals202and200. The step300is then followed by a step302(block “T1ON T2, T3OFF”)

In the step302, the circuit3controls the switching of the transistor T1to the on state by applying the low state of the signal cmd1to the gate G1of the transistor T1, and the switching of transistors T2and T3to the off state, by applying the high state of the signal cmd2to the gate G2of the transistor T2and the high state of the signal cmd3to the gate G3of transistor T3.

For example, in the step302, if the potential Vsw is zero, as soon as the potential Vdd is higher than the threshold of the diode Di1, a current flows from the terminal204to the terminal202, via the diode Di1as described relative toFIG.1. Thus, the potential Vsw increases until the transistor T1is switched to the on state by circuit3. At the same time, preferably, the circuit3maintains transistors T2and T3in the off state, for example, by maintaining the signal cmd2in its high state (potential Vsw) and signal cmd3in its high state (potential Vbat).

In the step300, if signal EN is in its first binary state (output Vbat of block200), for example, the low state, this means that circuit3must electrically couple the terminals200and202, and electrically isolate the terminals204and202. The step300is then followed by a step304(block “Vbat>0”).

In the step304, the circuit3checks whether the potential Vbat is zero, for example by comparing the potential Vbat to ground GND.

In the step304, if the potential Vbat is non-zero (output Y of block204), and, more precisely, strictly positive, the method continues at a step306(block “T1OFF T2, T3ON”).

In the step306, the circuit3controls the switching of the transistor T2to the on state, by applying the low state of the signal cmd2to the gate G2of the transistor T2, the switching of transistor T3to the on state, by applying the low state of the signal cmd3to the gate G3of transistor T3, and switching the transistor T1to the off state, by applying the high state of the signal cmd1to the gate G1of the transistor T1.

For example, in the step306, if the potential Vsw is zero, as soon as the potential Vbat is high enough for the transistor T3to switch to the on state, a current flows from the terminal200to the terminal202, via the transistor T3in the on state and the diode Di2as described as an example relative toFIG.1. Thus, the potential Vsw increases until the transistor T2is switched to the on state, by the circuit3. At the same time, preferably, the circuit3maintains the transistor T1in the off state, for example, by maintaining the signal cmd1at its high state (potential Vsw).

In the step304, if the potential Vbat is zero (output N of block204), then it is preferable not to electrically couple the terminals200and202to each other. The method then continues at a step308(block “T1ON T2, T3OFF”).

The step308is identical to step302. Thus, in the step304, if the potential Vdd is non-zero, for example below the threshold Vth but not zero, and the potential Vbat is zero, then implementing the step308maintains a non-zero potential Vsw.

When the circuit3implements the step304, the circuit3is configured to condition the switching of the transistors T2and T3to the on state, and preferably the switching of the transistor T1to the off state, due to the potential Vbat being non-zero. In other words, the circuit3is configured to control the on state of transistors T2and T3, for example following the reception of the first binary state of the signal EN, only if, in addition, the potential Vbat is non-zero.

According to an alternative embodiment, the steps304and306may be omitted, the step300then being directly followed by the step308when the signal EN is in its first binary state during the step300. In this variant, the circuit3is not configured to condition the switching of the transistors T2and T3to the on state, due to the fact that the potential Vbat is non-zero.

Preferably, although not shown inFIG.2, each of the steps302,306, and308is followed by the step300, so that the implementation of these steps is performed continuously or repeatedly.

According to one embodiment, the method further comprises a step310(block “Vdd>0?”). In the step310, the circuit3checks whether the potential Vdd is zero, for example by comparing it to the ground GND.

At the step310, if the potential Vdd is zero (output N of block210), the method continues at a step312(block “T3ON”). Otherwise (branch Y of block210) step310is implemented again.

In the step312, circuit3forces the transistor T3to switch to the on state, for example by applying the low state of the signal cmd3to the gate G3of transistor3. Thus, if the potential Vbat is sufficient, the transistor T3is switched to the on state. This allows, when the potentials Vsw and Vdd are zero, but the potential Vbat is non-zero, to increase the potential Vsw by electrically coupling the terminals200and202via the transistor T3which is in the on state and the diode Di2.

Although not shown inFIG.2, preferably the step312is followed by the step310, such that step310is implemented continuously or repeatedly.

Preferably, the switching of the transistor T3to the on state resulting from the implementation of the step312overrides the switching of transistor T3to the off state, resulting from the implementation of the step308, or, in other words, takes precedence over the switching of transistor T3to the off state, resulting from the implementation of the step308.

In an alternative embodiment, the steps310and312are omitted. In one such variant, the circuit3is not configured to force a switching of the transistor T3to the on state, when the potential Vdd is zero.

It has been described above in relative toFIGS.1and2the case where the maximum values of the gate-source voltage that can be supported by the transistors T1, T2and T3are higher than the maximum values of potentials Vbat and Vdd.

It would be desirable to be able to make the switch2with the transistors having maximum gate-source voltages of values lower than the maximum values of the potentials Vbat and Vdd. For example, this allows for an integrated circuit comprising the device1to be implemented entirely with MOS transistors having maximum gate-source voltages of values lower than the maximum potential values Vbat and Vdd. This results in a reduction in the surface area of the integrated circuit relative to the case where it is implemented with larger MOS transistors having maximum gate-source voltages higher than or equal to the maximum values of the potentials Vbat and Vdd.

FIG.3shows another embodiment of the switch2ofFIG.1.

The provision of drift transistors T1, T2, T3allows each transistor T1, T2, T3to support a maximum voltage between its source and its drain, or maximum drain-source voltage, and a maximum voltage between its gate and its drain, or maximum gate-drain voltage, higher than or equal to the maximum values of the potentials Vbat and Vdd.

On the other hand, it is considered here that the transistors T1, T2and T3each have a maximum gate-source voltage lower than the maximum values of the potentials Vbat and Vdd.

Thus, according to one embodiment, the control circuit3(not represented inFIG.3) then comprises: a circuit configured to supply a high reference potential VrefHB equal to A times the supply potential Vbat and a low reference potential VrefLB equal to B times the supply potential Vbat, with A and B positive numbers strictly less than 1, A being greater than B; and a circuit configured to supply a high reference potential VrefHS equal to C times the supply potential Vsw and a low reference potential VrefLS equal to D times the supply potential Vsw, with C and D positive numbers strictly less than 1, C being greater than D.

According to one embodiment, the numbers A, B, C and D are determined by the maximum gate-source voltage supported by each of the transistors T1, T2and T3. Preferably, the numbers A, B, C, and D are determined such that the difference between the potentials Vbat and VrefLB, the difference between the potentials VrefHB and GND, the difference between the potentials Vsw and VrefLS, and the difference between the potentials VrefHS and GND are each lower than the maximum gate-source voltage supported by each of the transistors T1, T2, and T3. In this way, the circuit3handles binary signals whose low and high states are equal to the potentials GND and VrefHB, GND and VrefHS, VrefLS and Vsw, and/or VrefLB and Vbat. These binary signals are compatible with the voltage holding properties of the transistors T1, T2and T3, and, for example, of the MOS transistors of the device1such as, in particular, the transistors implementing the circuit3.

According to one embodiment, the circuit3further comprises a circuit configured to supply a high reference potential VrefHM equal to E times the potential Vdd and a low reference potential VrefLM equal to F times the potential Vdd, with E and F being positive numbers strictly less than 1. Moreover, the number E is greater than the number F. In a similar manner to the numbers A, B, C and D, the numbers E and F are determined by the maximum potential difference that can be applied between the gate and the source of each of the transistors T1, T2and T3. In other words, the numbers E and F are determined by the maximum gate-to-source voltage supported by each of the transistors T1, T2and T3. Preferably, the numbers E and F are determined such that the difference between the potentials Vdd and VrefLM, and the difference between the potentials VrefHM and GND are each lower than the maximum gate-source voltage supported by each of the transistors T1, T2and T3. In this way, circuit3can further handle the binary signals whose low and high states are equal to the potentials GND and VrefHM, and/or the potentials VrefLM and Vdd. These binary signals are compatible with the voltage handling properties of the transistors T1, T2, and T3, and, for example, of the MOS transistors of the device1such as, in particular, the transistors implementing the circuit3.

Although not illustrated inFIG.3, in one such embodiment, preferably, the circuit6(FIG.1) is preferably powered by the difference between the potentials VrefHS and GND. In other words, preferably, the low state of the signal EN is then the ground potential GND and the high state of the signal EN is then the potential VrefHS. Furthermore, preferably in one such embodiment, the circuit6determines whether the potential Vdd is higher than the threshold Vth by comparing the potential VrefHM to a threshold Vth′, where comparing the potential VrefHM to the threshold Vth′ is equivalent to comparing the potential Vdd to the threshold Vth.

In the embodiment ofFIG.3, according to one embodiment, the high state of the signal cmd1corresponds to the potential Vsw, the low state of the signal cmd1corresponds to the potential VrefLS, the high state of the signal cmd2corresponds to the potential Vsw, the low state of the signal cmd2corresponds to the potential VrefLS, the high state of the signal cmd3corresponds to the potential Vbat, and the low state of the signal cmd3corresponds to the potential VrefLB.

According to one embodiment, the operation of the circuit3, and preferably the operation of the circuit6, are identical to what has been described relative toFIGS.1and2, with the only difference that the low levels of signals cmd1, cmd2and cmd3no longer correspond to the GND potential, but instead correspond to the VrefLS potential, the VrefLS potential and the VrefLB potential, respectively.

The implementation of the circuit3in the case described relative toFIG.3is within the reach of the person skilled in the art from the functional and structural indications given above.

In particular, the person skilled in the art may implement the circuit3by means of circuits configured to generate the potentials VrefHB, VrefLB, VrefHS and VrefLS, and, for example, the circuit configured to generate the potentials VrefHM and VrefLM. These circuits are commonly referred to as Reference Voltage Generators. Examples of reference voltage generators are described in the paper by Kumar, et al., “Power Sequence free 400 Mbps 90 μW 6000 μm21.8V-3.3V Stress Tolerant I/O Buffer in 28 nm CMOS” presented in 2013 at the ESSCIRC conference (incorporated by reference). The person skilled in the art will be able to find other examples of such circuits in the literature.

Furthermore, to implement the circuit3, and preferably the circuit6, the person skilled in the art may use level shifter or splitter circuits configured to receive a binary signal having a low level corresponding to a first potential and a high level corresponding to a second potential, and to provide a binary signal having a low level corresponding to a third potential different from the first potential and a high level corresponding to a fourth potential, for example, different from the second potential. For example, the circuit3may comprise circuits configured to receive a binary signal between the potentials (or levels) VrefHS and GND, VrefHB and GND, and VrefHS and GND, and to provide a binary signal between the potentials (or levels) VrefHB and GND, Vbat and VrefLB, and Vsw and VrefLS respectively. Examples of such circuits are also described in the aforementioned article, although the person skilled in the art will be able to find other examples of such circuits in the literature.

FIG.4shows, in block form and in more detail, one embodiment of the control circuit3of the switch2ofFIG.3.

For example, the signal EN is in its first binary state when the potential Vdd is lower than the threshold Vth, and in its second binary state when the potential Vdd is higher than the threshold Vth. Preferably, the first binary state of the signal EN corresponds to the potential GND and the second binary state of the signal EN corresponds to the potential VrefHS.

In this embodiment, the circuit3comprises a circuit400of the type described above, configured to supply the potential VrefHB and the potential VrefLB. For example, the circuit400is configured to supply the potentials VrefHB and VrefLB from the potential Vbat, preferably from the difference between the potentials Vbat and GND. For example, the circuit400receives the potentials Vbat and GND, for example, at the power terminals of the circuit400.

In this embodiment, the circuit3further comprises a circuit402of the type described above, configured to supply the potential VrefHS and the potential VrefLS. For example, the circuit402is configured to supply the potentials VrefHS and VrefLS from the potential Vsw, preferably from the difference between the potentials Vsw and GND. For example, the circuit402receives the potentials Vsw and GND, for example, at the power terminals of the circuit402.

According to one embodiment, the control circuit3comprises the circuits404,406and408, of the type described above.

The circuit404is configured to receive a binary signal cmd3′ between the ground GND and the potential VrefHB and to provide, to gate G3of transistor T3(not shown inFIG.4), the binary signal cmd3. The signal cmd3is determined by the signal cmd3′ and is between the potential Vbat and the potential VrefLB. In other words, the signal cmd3corresponds to the signal cmd3′ with the difference that the signal cmd3is between the potentials Vbat and VrefLB while the signal cmd3′ is between the potentials VrefHB and GND. Preferably, the signal cmd3is in the low state, respectively high, when the signal cmd3′ is in the low state, respectively high. For example, the circuit404receives the difference between the potentials Vbat and VrefLB and the difference between the potentials VrefHB and GND, for example, at four respective power terminals.

The circuit406is configured to receive a binary signal cmd2′ between the ground GND and the potential VrefHS and to provide, at the gate G2of the transistor T2(not shown inFIG.4), the binary signal cmd2. The signal cmd2is determined by the signal cmd2′ and is between the potential Vsw and the potential VrefLS. In other words, the signal cmd2corresponds to the signal cmd2′ with the difference that the signal cmd2is between the potentials Vsw and VrefLS while the signal cmd2′ is between the potentials VrefHS and GND. Preferably, the signal cmd2is in the low state, respectively high, when the signal cmd2′ is in the low state, respectively high. For example, the circuit406receives the difference between the potentials Vsw and VrefLS and the difference between the potentials VrefHS and GND, for example, at four respective power terminals.

Circuit408is configured to receive a binary signal cmd1′ between the ground GND and the potential VrefHS and to provide, at the gate G1of the transistor T1(not shown inFIG.4), the binary signal cmd1. The signal cmd1is determined by the signal cmd1′ and is between the potential Vsw and the potential VrefLS. In other words, the signal cmd1corresponds to the signal cmd1′ with the difference that the signal cmd1is between the potentials Vsw and VrefLS while the signal cmd1′ is between the potentials VrefHS and GND. Preferably, the signal cmd1is in the low, respectively high, state when the signal cmd1′ is in the low, respectively high, state. For example, the circuit408receives the difference between the potentials Vsw and VrefLS and the difference between the potentials VrefHS and GND, for example, at four respective power terminals.

In a similar manner to the signals cmd1, cdm2, and cmd3, the signals cmd1′, cmd2′, and cmd3′ are at least in part determined by the signal EN, i.e., by the binary state or potential level of the signal EN.

More particularly, according to one embodiment, the control circuit3comprises a circuit410and a circuit412.

The circuit410is configured to receive the signal EN, and to provide the signals cmd2′ and cmd1′. The circuit410is further configured to provide a binary signal cmd3″ determining, at least in part, the state of the signal cmd3′. The signal cmd3″ is, like the signals cmd1′, cmd2′ and EN, between the potentials VrefHS and GND.

The circuit410is powered by the difference between the potentials VrefHS and GND, and receives, for example, the potentials VrefHS and GND at two respective power terminals. Supplying the circuit410with the VrefHS potential results from the fact that the signals EN, cmd1′ and cmd2′ are between the potentials VrefHS and GND, and allows, for example, the maximum voltage that the MOS transistors of the circuit410can withstand between two of their terminals (gate, source, drain) to be lower than the maximum values of the potentials Vbat and Vsw.

The circuit412is configured to receive the signal cmd3″, and to provide the signal cmd3′. The circuit412is powered by the difference between the potentials VrefHB and GND, and receives, for example, the potentials VrefHB and GND on two respective power terminals. This allows, for example, the maximum voltage that the MOS transistors of the circuit412can withstand between two of their terminals (gate, source, drain) to be less than the maximum values of the potentials Vbat and Vsw.

According to one embodiment, to determine the signal cmd3′ at least in part from the signal cmd3″, the circuit412includes a circuit414.

The circuit414is configured to receive the signal cmd3″ between the potentials VrefHS and GND and to provide a binary signal cmd3″′ between the potentials VrefHB and GND. The signal cmd3″′ is determined by the signal cmd3″. In other words, the signal cmd3″′ corresponds to the signal cmd3″ with the difference that the signal cmd3″′ is between the potentials VrefHB and GND while the signal cmd3″ is between the potentials VrefHS and GND. Preferably, the signal cmd3″′ is in the low state, respectively high, when the signal cmd3″ is in the low state, respectively high. For example, the circuit414receives the difference between the potentials VrefHB and GND, for example, at two respective power supply terminals.

In the embodiment illustrated inFIG.4, the circuit3is configured to condition a switching of the transistors T2and T3, to the on state, when required by the signal EN, due to the fact that the potential Vbat is non-zero.

The circuit3then comprises a circuit418. The circuit418is configured to provide a binary signal cmd4, a first binary state of which, for example the low state, indicates that the potential Vbat is strictly positive, and thus non-zero, and a second binary state of which, for example the high state, indicates that the potential Vbat is zero. To this end, the circuit418preferably receives the signal VrefHB.

The signal cmd4is between the potentials VrefHS and GND. In other words, the low state of the signal cmd4corresponds to the potential GND and the high state of the cmd4signal corresponds to the potential VrefHS. The circuit418is powered by the difference between the potentials VrefHS and GND and receives, for example, the potentials VrefHS and GND at respective power terminals.

For example, the circuit418comprises a comparator circuit, preferably powered by the difference between the potentials VrefHS and GND, configured to compare the potential VrefHB to the potential GND. Indeed, because the potential VrefHB is equal to A times the potential Vbat, the potential VrefHB is strictly positive, respectively zero, when the potential Vbat is strictly positive, respectively zero.

The signal cmd4is received by the circuit410, or, in other words, provided by the circuit418to the circuit410. In one such embodiment, the circuit410is configured to provide the signals cmd1′, cmd2′ and cmd3″ from the signals EN and cmd4.

For example, when the circuit receives the first binary state of the signal EN, indicating a request to switch transistors T2and T3to the on state, and the signal cmd4indicates that the potential Vbat is strictly positive, the circuit410provides the signals cmd3″, cmd1′, and cmd2′ so as to control a switching of the transistors T2and T3to the on state and a switching of the transistor T1to the off state. On the other hand, if the circuit410receives the second binary state of the signal EN and/or the signal cmd4indicates that the potential Vbat is zero, the circuit410provides the signals cmd3″, cmd1′ and cmd2′ so as to control a switching of the transistors T2and T3to the off state and a switching of the transistor T1to the on state.

For example, the circuit410is implemented by combinational logic gates implemented by MOS transistors, the logic gates preferably being powered by the difference between the potentials VrefHS and GND. The logic gates are configured to provide the signals cmd3″, cmd1′ and cmd2′ from the signals EN and cmd4.

In an alternative embodiment not shown, the circuit3is not configured to condition a switching of the transistors T2and T3to the on state, when required by the signal EN, on the potential Vbat being non-zero.

In this variant, the circuit418may be omitted. For example, the circuit410, for example the combinational logic gates implementing it, is then configured to determine the signals cmd3″, cmd2′ and cmd1′ solely from the signal EN.

In the embodiment illustrated inFIG.4, the circuit3is further configured to force a switching of the transistor T3to the on state when the potential Vdd is zero.

The circuit3then comprises a circuit420and a circuit422.

The circuit420of the type previously described relative toFIG.3, is configured to supply the potential VrefHM and the potential VrefLM. For example, the circuit420is configured to supply the potentials VrefHM and VrefLM from the potential Vdd, preferably from the difference between the potentials Vdd and GND. For example, the circuit420receives the potentials Vdd and GND, for example, at the power supply terminals of the circuit420.

The circuit422is configured to provide a binary signal cmd5having a first binary state, for example the high state, indicating that the potential Vdd is strictly positive, and thus non-zero, and of which a second binary state, for example the low state, indicates that the potential Vdd is zero. To this end, the circuit418preferably receives the signal VrefHM.

The signal cmd5is between the potentials VrefHB and GND. In other words, the low state of the signal cmd5corresponds to the potential GND and the high state of the signal cmd5corresponds to the potential VrefHB. The circuit422is powered by the difference between the potentials VrefHB and GND and receives, for example, the potentials VrefHB and GND at respective power terminals.

For example, circuit422comprises a comparator circuit, preferably powered by the difference between potentials VrefHB and GND, configured to compare the potential VrefHM to potential GND. Indeed, because the potential VrefHM is equal to E times the potential Vdd, the potential VrefHM is strictly positive, respectively zero, when the potential Vdd is strictly positive, respectively zero.

The signal cmd5is received by the circuit412, or, in other words, provided by the circuit422to the circuit412. In one such embodiment, the circuit412is configured to provide signals cmd3′ from the signals cmd3″ and cmd5, or, in other words, from signals cmd3″′ and cmd5.

For example, when the signals cmd5and cmd3″ received by the circuit412indicate, respectively, that the potential Vdd is strictly positive and that the transistor T3should be switched to the off state, the circuit412provides the signal cmd3′ so as to command the transistor T3to be switched to the off state. On the other hand, if the signal cmd5indicates that the potential Vdd is zero and/or if the signal cmd3″ indicates that the transistor T3is to be switched to the on state, the circuit412provides the signal cmd3′ so as to control a switching of the transistor T3to the on state.

For example, the circuit412, with the exception of its circuit414, is implemented by the combinational logic gates implemented by the MOS transistors, the logic gates preferably being powered by the difference between the potentials VrefHB and GND. The supply of the circuit412by the potential VrefHB results from the fact that the two signals cmd3″′ and cmd5are between the potentials VrefHB and GND. The logic gates of the circuit412are configured to provide the signal cmd3′ from the signals cmd5and cmd3″′.

In an alternative embodiment not shown, the circuit3is not configured to force a switching of the transistor T3to the on state when the potential Vdd is zero.

In this variant, the circuits420and422may be omitted from the circuit3, although the circuit420may still be provided in the circuit6(FIG.1). For example, the circuit412, for example the combinational logic gates that implement it, is then configured to determine the signal cmd3′ only from the signal cmd3″, thus the signal cmd3″′.

According to one embodiment, the circuit3implements the embodiment or one of the alternative embodiments of the method described relative toFIG.2.

FIG.5illustrates one embodiment of a method for providing the control signal EN to the circuit3ofFIG.1or4. For example, this method is implemented by the circuit6(FIG.1).

At a step500(block “Vdd>Vth?”), the potential Vdd is compared to the threshold Vth.

According to one embodiment in which the transistors T1, T2, and T3are configured to support a maximum source-gate voltage higher than or equal to the potentials Vdd and Vbat, the circuit6(FIG.1) comprises a comparator circuit configured to compare the potential Vdd to the threshold Vth. The comparator circuit is then powered by the difference between the potentials Vsw and GND, so that the signal EN is between the potentials Vsw and GND.

According to one embodiment in which the transistors T1, T2, and T3are configured to support a maximum source-gate voltage lower than the potentials Vdd and Vbat, the circuit6(FIG.1) comprises a comparator circuit configured to compare the potential VrefHM to a threshold Vth′ determined by the threshold Vth, so that the comparison of the potential VrefHM to the threshold Vth′ is equivalent to comparing the potential Vdd to the threshold Vth. The comparator circuit is then supplied with the difference between the potentials VrefHS and GND, so that the signal EN is between the potentials VrefHS and GND.

If the potential Vdd is higher than the threshold Vth (output Y of block500), the method continues at a step502(block “Vdd”). In the step502, the signal EN is switched to its second binary state, or, in other words the circuit3receives a request to switch the transistor T1to the on state and switch the transistors T2and T3to the off state. The step502is followed by the step500.

According to one embodiment in which the transistors T1, T2, and T3are configured to support a maximum source-to-gate voltage greater than or equal to the potentials Vdd and Vbat, the second binary state of the signal EN corresponds to the potential Vsw.

According to one embodiment in which the transistors T1, T2, and T3are configured to support a maximum source-gate voltage lower than the potentials Vdd and Vbat, the second binary state of the signal EN corresponds to the potential VrefHS.

If the potential Vdd is lower than the threshold Vth (output N of block500), the method continues at a step504(block “Vbat”). In the step504, preferably immediately after the potential Vdd becomes lower than the threshold Vth, the signal EN is switched to its first binary state, or, in other words, the circuit3receives a request to switch the transistor T1to the off state and switch the transistors T2and T3to the on state. The step504is followed by the step500.

According to one embodiment, the first binary state of the EN signal corresponds to the potential GND.

Although not detailed above, preferably, when the potential Vsw is not sufficient for the circuit6to implement the comparison of the potential Vdd to the threshold Vth, i.e., when the potential Vsw is not sufficient to power the circuit6, for example, at the beginning of the operation of the device1when the potential Vsw is still zero, the signal EN is by default kept at the low state, i.e., at the potential GND. In other words, when the potential Vsw is not sufficient to supply the circuit6correctly, the signal EN is by default in the low state indicating to the circuit3a request to switch the transistor T1to the off state and to switch the transistors T2and T3to the on state.

According to one embodiment, the transistors T1, T2and T3and the transistors of the circuit3and, preferably, of the circuit6, are MOS transistors having a gate oxide the thickness of which is substantially equal to, for example, equal to 32 angstroms, the channel length of these transistors being, for example, substantially equal to, preferably equal to, 28 nm. For example, these transistors are configured to support a maximum drain-to-source voltage, a maximum source-to-gate voltage, and a maximum drain-to-gate voltage substantially equal to 1.8 V when they are not at extended drain, and to support a maximum drain-to-source voltage and a maximum drain-to-gate voltage higher than 1.8 V when at extended drain although the maximum gate-to-source voltage they support remains substantially equal to 1.8 V.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variants will readily occur to those skilled in the art. In particular, although a circuit420configured to supply not only the potential VrefHM, but also the potential VrefLM has been described, in alternative embodiments the circuit420is configured to provide the potential VrefHM without supplying the potential VrefLM.

Finally, the practical implementation of the embodiments and variants described herein is within the capabilities of those skilled in the art based on the functional description provided hereinabove. In particular, implementation of the described circuits, including circuits410and412, is within the scope of the person skilled in the art from the functional and structural indications given above.