Advanced lithography and self-assembled devices

Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

CROSS-REFERENCE TO RELATED APPLICATION

This patent application is a U.S. National Phase Application under 35 U.S.C. § 371 of International Application No. PCT/US2016/068586, filed Dec. 23, 2016, entitled “ADVANCED LITHOGRAPHY AND SELF-ASSEMBLED DEVICES,” which designates the United States of America, the entire disclosure of which is hereby incorporated by reference in its entirety and for all purposes.

TECHNICAL FIELD

Embodiments of the disclosure are in the field of semiconductor devices and processing and, in particular, sub-10 nm pitch patterning and self-assembled devices.

BACKGROUND

Variability in conventional and currently known fabrication processes may limit the possibility to further extend them into the sub-10 nm range. Consequently, fabrication of the functional components needed for future technology nodes may require the introduction of new methodologies or the integration of new technologies in current fabrication processes or in place of current fabrication processes.

DESCRIPTION OF THE EMBODIMENTS

Advanced pitch patterning and self-assembled devices are described, in particular advanced pitch patterning techniques and self-assembled device fabrication methods to generate sub-10 nanometer (nm) devices and structures. In the following description, numerous specific details are set forth, such as specific integration and material regimes, in order to provide a thorough understanding of embodiments of the present disclosure. It will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known features, such as integrated circuit design layouts, are not described in detail in order to not unnecessarily obscure embodiments of the present disclosure. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

“Comprising.” This term is open-ended. As used in the appended claims, this term does not foreclose additional structure or steps.

“Configured To.” Various units or components may be described or claimed as “configured to” perform a task or tasks. In such contexts, “configured to” is used to connote structure by indicating that the units/components include structure that performs those task or tasks during operation. As such, the unit/component can be said to be configured to perform the task even when the specified unit/component is not currently operational (e.g., is not on/active). Reciting that a unit/circuit/component is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112, sixth paragraph, for that unit/component.

“First,” “Second,” etc. As used herein, these terms are used as labels for nouns that they precede, and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). For example, reference to a “first” solar cell does not necessarily imply that this solar cell is the first solar cell in a sequence; instead the term “first” is used to differentiate this solar cell from another solar cell (e.g., a “second” solar cell).

“Coupled”—The following description refers to elements or nodes or features being “coupled” together. As used herein, unless expressly stated otherwise, “coupled” means that one element/node/feature is directly or indirectly joined to (or directly or indirectly communicates with) another element/node/feature, and not necessarily mechanically.

Embodiments described herein may be directed to front-end-of-line (FEOL) semiconductor processing and structures. FEOL is the first portion of integrated circuit (IC) fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) are patterned in the semiconductor substrate or layer. FEOL generally covers everything up to (but not including) the deposition of metal interconnect layers. Following the last FEOL operation, the result is typically a wafer with isolated transistors (e.g., without any wires).

Embodiments described herein may be directed to back end of line (BEOL) semiconductor processing and structures. BEOL is the second portion of IC fabrication where the individual devices (e.g., transistors, capacitors, resistors, etc.) get interconnected with wiring on the wafer, e.g., the metallization layer or layers. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. In the BEOL part of the fabrication stage contacts (pads), interconnect wires, vias and dielectric structures are formed. For modern IC processes, more than 10 metal layers may be added in the BEOL. Embodiments described below may be applicable to FEOL processing and structures, BEOL processing and structures, or both FEOL and BEOL processing and structures. In particular, although an exemplary processing scheme may be illustrated using a FEOL processing scenario, such approaches may also be applicable to BEOL processing. Likewise, although an exemplary processing scheme may be illustrated using a BEOL processing scenario, such approaches may also be applicable to FEOL processing.

Pitch division processing and patterning schemes may be implemented to enable embodiments described herein or may be included as part of embodiments described herein. Pitch division patterning typically refers to pitch halving, pitch quartering etc. Pitch division schemes may be applicable to FEOL processing, BEOL processing, or both FEOL (device) and BEOL (metallization) processing. In accordance with one or more embodiments described herein, optical lithography is first implemented to print unidirectional lines (e.g., either strictly unidirectional or predominantly unidirectional) in a pre-defined pitch. Pitch division processing is then implemented as a technique to increase line density.

In an embodiment, the term “grating structure” for metal lines, ILD lines or hardmask lines is used herein to refer to a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning, as is known in the art. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like patterns described herein may have metal lines, ILD lines or hardmask lines spaced at a substantially consistent pitch and having a substantially consistent width. For example, in some embodiments the pitch variation would be within ten percent and the width variation would be within ten percent, and in some embodiments, the pitch variation would be within five percent and the width variation would be within five percent. The pattern may be fabricated by a pitch halving or pitch quartering, or other pitch division, approach. In an embodiment, the grating is not necessarily single pitch.

In a first example, pitch halving can be implemented to double the line density of a fabricated grating structure.FIG. 1Aillustrates a cross-sectional view of a starting structure following deposition, but prior to patterning, of a hardmask material layer formed on an interlayer dielectric (ILD) layer.FIG. 1Billustrates a cross-sectional view of the structure ofFIG. 1Afollowing patterning of the hardmask layer by pitch halving.

Referring toFIG. 1A, a starting structure100has a hardmask material layer104formed on an interlayer dielectric (ILD) layer102. A patterned mask106is disposed above the hardmask material layer104. The patterned mask106has spacers108formed along sidewalls of features (lines) thereof, on the hardmask material layer104.

Referring toFIG. 1B, the hardmask material layer104is patterned in a pitch halving approach. Specifically, the patterned mask106is first removed. The resulting pattern of the spacers108has double the density, or half the pitch or the features of the mask106. The pattern of the spacers108is transferred, e.g., by an etch process, to the hardmask material layer104to form a patterned hardmask110, as is depicted inFIG. 1B. In one such embodiment, the patterned hardmask110is formed with a grating pattern having unidirectional lines. The grating pattern of the patterned hardmask110may be a tight pitch grating structure. For example, the tight pitch may not be achievable directly through conventional lithography techniques. Even further, although not shown, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the patterned hardmask110ofFIG. 1Bmay have hardmask lines spaced at a constant pitch and having a constant width relative to one another. The dimensions achieved may be far smaller than the critical dimension of the lithographic technique employed.

Accordingly, for either front-end of line (FEOL) or back-end of line (BEOL), or both, integrations schemes, a blanket film may be patterned using lithography and etch processing which may involve, e.g., spacer-based-double-patterning (SBDP) or pitch halving, or spacer-based-quadruple-patterning (SBQP) or pitch quartering. It is to be appreciated that other pitch division approaches may also be implemented.

For example,FIG. 2illustrates cross-sectional views in a spacer-based-sextuple-patterning (SBSP) processing scheme which involves pitch division by a factor of six. Referring toFIG. 2, at operation (a), a sacrificial pattern X is shown following litho, slim and etch processing. At operation (b), spacers A and B are shown following deposition and etching. At operation (c), the pattern of operation (b) is shown following spacer A removal. At operation (d), the pattern of operation (c) is shown following spacer C deposition. At operation (e), the pattern of operation (d) is shown following spacer C etch. At operation (f), a pitch/6 pattern is achieved following sacrificial pattern X removal and spacer B removal.

In another example,FIG. 3illustrates cross-sectional views in a spacer-based-nonuple-patterning (SBNP) processing scheme which involves pitch division by a factor of nine. Referring toFIG. 3, at operation (a), a sacrificial pattern X is shown following litho, slim and etch processing. At operation (b), spacers A and B are shown following deposition and etching. At operation (c), the pattern of operation (b) is shown following spacer A removal. At operation (d), the pattern of operation (c) is shown following spacer C and D deposition and etch. At operation (e), a pitch/9 pattern is achieved following spacer C removal.

In any case, in an embodiment, a gridded layout may be fabricated by conventional or state-of the-art lithography, such as 193 nm immersion lithography (193i). Pitch division may be implemented to increase the density of lines in the gridded layout by a factor of n. Gridded layout formation with 193i lithography plus pitch division by a factor of n can be designated as 193i+P/n Pitch Division. In one such embodiment, 193 nm immersion scaling can be extended for many generations with cost effective pitch division.

In the manufacture of integrated circuit devices, multi-gate transistors, such as tri-gate transistors, have become more prevalent as device dimensions continue to scale down. In conventional processes, tri-gate transistors are generally fabricated on either bulk silicon substrates or silicon-on-insulator substrates. In some instances, bulk silicon substrates are preferred due to their lower cost and compatibility with the existing high-yielding bulk silicon substrate infrastructure.

Scaling multi-gate transistors has not been without consequence, however. As the dimensions of these fundamental building blocks of microelectronic circuitry are reduced and as the sheer number of fundamental building blocks fabricated in a given region is increased, the constraints on the semiconductor processes used to fabricate these building blocks have become overwhelming.

In an embodiment, directed self-assembly (DSA) is implemented for hardmask differentiation (e.g., forming hardmasks with different etch properties). In some embodiments differentiated hardmasks may also be referred to as “colored” hardmasks, wherein hardmasks having the same color have the same or similar etch selectivities and wherein hardmasks having different colors have different etch selectivities. It should be noted that in actual practice, the term “color” does not refer to the actual color of the hardmask material. Hardmask differentiation (or coloring) may be used for patterning or selectively removing semiconductor fins among a plurality of gridded semiconductor fins. One or more embodiments described herein is directed to processes and structures based on and resulting from aligned pitch-quartered (or other) patterning approaches for edge placement error (EPE) rectification. One or more embodiments may be described as a differentiated or “colored” alternating hardmask approach for semiconductor fin patterning. Embodiments may include one or more of DSA, semiconductor material patterning, pitch division such as pitch quartering, differentiated hardmask selectivity, self-alignment for fin patterning. One or more embodiments is particularly suited for non-planar semiconductor device fabrication.

In accordance with an embodiment of the present disclosure, doubling of allowed edge placement error and doubling of the cut size for cutting of small features at tight pitch is implemented for very fine fin patterning. In one embodiment, all features (e.g., fin lines) are transferred into a semiconductor substrate with a single population of critical dimension (CD) variation. This approach is in contrast to state of the art approaches that rely on spacer-based pitch quartering which typically has three discrete populations of line widths (e.g., backbone or mandrel, complement and spacer dimensions).

To provide context, it may be desirable to use bulk silicon for fins or trigate based semiconductor devices. In an embodiment, directed self-assembly (DSA) is implemented to accomplish pitch division and “coloring” of every other feature in a desired pattern. In one such embodiment, the patterning approach is particularly applicable to patterning silicon fins in a tri-gate transition patterning flow. In an embodiment advantages of implementing approaches described herein may include one or more of: (1) enabling a single population of feature widths, (2) doubling the edge placement error requirements for feature cutting, (3) doubling dimensions of the hole or opening required to cut a single feature (e.g., relaxing the restrictions on the size of the opening), or (4) reducing the cost of the patterning process. Structural artifacts resulting from the process include, in an embodiment, a single population of critical dimensions and at the transitions from one pitch to another and/or from one grid to another at the guard rings surrounding the die of the chips. Embodiments may enable cutting of tight pitch lines without scaling the edge-placement error requirements.

In an exemplary processing scheme,FIGS. 4A-4Nillustrate cross-sectional view of various operations in a method of fabricating non-planar semiconductor devices, in accordance with an embodiment of the present disclosure.

FIG. 4Aillustrates a bulk semiconductor substrate402having a first patterned hardmask404formed thereon. In an embodiment, the bulk semiconductor substrate402is a bulk single crystalline silicon substrate having fins402etched therein. In one embodiment, the bulk semiconductor substrate402is undoped or lightly doped at this stage. For example, in a particular embodiment, the bulk semiconductor substrate402has a concentration of less than approximately 1E17 atoms/cm3of boron dopant impurity atoms.

In an embodiment, the first patterned hardmask404includes features having a pitch406. In one such embodiment, the first patterned hardmask404represents half of the possible number of fins ultimately formed in the substrate402. That is, the pitch406is effectively relaxed to double the pitch of the final pattern of fins formed. In one embodiment, the first hardmask404is patterned directly using a lithographic process. However, in other embodiments, pitch division is applied, e.g., pitch halving, and is used to provide patterned hardmask404with pitch406. It is to be appreciated that, in an embodiment, the first guide pattern can be formed using conventional patterning (litho/etch), only litho, spacer-based double patterning or other pitch division methods. In one embodiment, the guide pattern is separated from the DSA pattern through the use of two or more hardmasks such that the CDs are formed from a single population (e.g., one etch)).

FIG. 4Billustrates the structure ofFIG. 4Afollowing formation of a second hardmask layer408between the first patterned hardmask404. In an embodiment, the second hardmask layer408is formed by forming a blanket hardmask layer over the substrate402and first patterned hardmask404and then planarizing the blanket hardmask layer to form second hardmask layer408, e.g., by chemical mechanical planarization (CMP). In another embodiment, ALD or CVD techniques will follow the contour of the surface of the wafer and since fin cuts are used as an example, the wafer is substantially flat at this point in the process.

In an embodiment, the second hardmask layer408has an etch characteristic different from an etch characteristic of the first patterned hardmask404.

In one embodiment, one or both of the second hardmask layer408or the first patterned hardmask404is a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials, such as silicon carbide. In another embodiment, a hardmask material includes a metal species. For example, a hardmask or other overlying material may include a layer of a nitride of titanium (e.g., titanium nitride) or another metal. Potentially lesser amounts of other materials, such as oxygen, may be included in one or more of these layers. The hardmask layers may be formed by CVD, PVD, or by other deposition methods.

FIG. 4Cillustrates the structure ofFIG. 4Bfollowing application of a selective brush material layer410. The selective brush material410is a selective material that may be applied, in some embodiments, by a brush. It should be noted that “brush material” is often used as a term of art in DSA processes and does not imply that the selective material410is used as a brush. In an embodiment, the selective brush material layer410adheres to only the first patterned hardmask404, as is depicted inFIG. 4C. In another embodiment, however, the selective brush material is applied to the second hardmask layer408instead. In yet another embodiment, the selective brush material layer410adheres to only the first patterned hardmask404and a second different selective brush material is formed on the second hardmask layer408.

In an embodiment, the selective brush material layer410includes a molecular species including polystyrene with a head group selected from the group consisting of —SH, —PO3H2, —CO2H, —NRH, —NRR′, and —Si(OR)3. In another embodiment, selective brush material layer410includes a molecular species including polymethacrylate with a head group selected from the group consisting of —SH, —PO3H2, —CO2H, —NRH, —NRR′, and —Si(OR)3. In an embodiment, the selective brush material layer410is attracted to one constituent of a DSA block co-polymer (e.g., polystyrene or polymethylmethacrylate). The selective material layer410may include other suitable materials in other embodiments.

FIG. 4Dillustrates the structure ofFIG. 4Cfollowing application of a direct self-assembly (DSA) block co-polymer414/416(A/B) and polymer assembly process. In an embodiment, a DSA block co-polymer is coated on the surface and annealed to segregate the polymer into first polymer blocks414and second polymer blocks416(identified as416A and416B inFIG. 4D). In one embodiment, polymer blocks416preferentially attach to the selective brush material layer410during the anneal process. The polymer blocks414adhere to the second hardmask layer408. In a particular embodiment, however, the pitch of the assembly is half the pitch of the first patterned hardmask404. In this case, portions416A of the polymer blocks416adhere to the selective brush material layer410on the first hardmask404while portions416B of the polymer blocks416are formed on the second hardmask layer408between polymer blocks414.

In an embodiment, the block copolymer molecule414/416(A/B) is a polymeric molecule formed of a chain of covalently bonded monomers. In a di-block copolymer, there are two different types of monomers, and these different types of monomers are primarily included within two different blocks or contiguous sequences of monomers. The illustrated block copolymer molecule includes a block of polymer414and a block of polymer416(A/B). In an embodiment, the block of polymer414includes predominantly a chain of covalently linked monomer A (e.g., A-A-A-A-A . . . ), whereas the block of polymer416(A/B) includes predominantly a chain of covalently linked monomer B (e.g., B-B-B-B-B . . . ). The monomers A and B may represent any of the different types of monomers used in block copolymers known in the arts. By way of example, the monomer A may represent monomers to form polystyrene, and the monomer B may represent monomers to form poly(methyl methacrylate) (PMMA), or vice versa, although the scope of the disclosure is not so limited. In other embodiments, there may be more than two blocks. Moreover, in other embodiments, each of the blocks may include different types of monomers (e.g., each block may itself be a copolymer). In one embodiment, the block of polymer414and the block of polymer416(A/B) are covalently bonded together. The block of polymer414and the block of polymer416(A/B) may be of approximately equal length, or one block may be significantly longer than the other.

Typically, the blocks of block copolymers (e.g., the block of polymer414and the block of polymer416(A/B)) may each have different chemical properties. As one example, one of the blocks may be relatively more hydrophobic (e.g., water repelling) and the other may be relatively more hydrophilic (water attracting). At least conceptually, one of the blocks may be relatively more similar to oil and the other block may be relatively more similar to water. Such differences in chemical properties between the different blocks of polymers, whether a hydrophilic-hydrophobic difference or otherwise, may cause the block copolymer molecules to self-assemble. For example, the self-assembly may be based on microphase separation of the polymer blocks. Conceptually, this may be similar to the phase separation of oil and water which are generally immiscible. Similarly, differences in hydrophilicity between the polymer blocks (e.g., one block is relatively hydrophobic and the other block is relatively hydrophilic), may cause a roughly analogous microphase separation where the different polymer blocks try to “separate” from each other due to chemical dislike for the other.

However, in an embodiment, since the polymer blocks are covalently bonded to one another, they cannot completely separate on a macroscopic scale. Rather, polymer blocks of a given type may tend to segregate or conglomerate with polymer blocks of the same type of other molecules in extremely small (e.g., nano-sized) regions or phases. The particular size and shape of the regions or microphases generally depends at least in part upon the relative lengths of the polymer blocks. In an embodiment, by way of example, in two block copolymers, if the blocks are approximately the same length, a grid like pattern of alternating polymer414lines and polymer416(A/B) lines is generated.

In an embodiment, the polymer414/polymer416(A/B) grating is first applied as an unassembled block copolymer layer portion that includes a block copolymer material applied, e.g., by brush or other coating process. The unassembled aspect refers to scenarios where, at the time of deposition, the block copolymer has not yet substantially phase separated and/or self-assembled to form nanostructures. In this unassembled form, the block polymer molecules are relatively highly randomized, with the different polymer blocks relatively highly randomly oriented and located. The unassembled block copolymer layer portion may be applied in a variety of different ways. By way of example, the block copolymer may be dissolved in a solvent and then spin coated over the surface. Alternatively, the unassembled block copolymer may be spray coated, dip coated, immersion coated, or otherwise coated or applied over the surface. Other ways of applying block copolymers, as well as other ways known in the arts for applying similar organic coatings, may potentially be used. Then, the unassembled layer may form an assembled block copolymer layer portion, e.g., by microphase separation and/or self-assembly of the unassembled block copolymer layer portion. The microphase separation and/or self-assembly occurs through rearrangement and/or repositioning of the block copolymer molecules, and in particular to rearrangement and/or repositioning of the different polymer blocks of the block copolymer molecules.

In one such embodiment, an annealing treatment may be applied to the unassembled block copolymer in order to initiate, accelerate, increase the quality of, or otherwise promote microphase separation and/or self-assembly. In some embodiments, the annealing treatment may include a treatment that is operable to increase a temperature of the block copolymer. One example of such a treatment is baking the layer, heating the layer in an oven or under a thermal lamp, applying infrared radiation to the layer, or otherwise applying heat to or increasing the temperature of the layer. The desired temperature increase will generally be sufficient to significantly accelerate the rate of microphase separation and/or self-assembly of the block polymer without damaging the block copolymer or any other important materials or structures of the integrated circuit substrate. Commonly, the heating may range between about 50° C. to about 300° C., or between about 75° C. to about 250° C., but not exceeding thermal degradation limits of the block copolymer or integrated circuit substrate. The heating or annealing may help to provide energy to the block copolymer molecules to make them more mobile/flexible in order to increase the rate of the microphase separation and/or improve the quality of the microphase separation. Such microphase separation or rearrangement/repositioning of the block copolymer molecules may lead to self-assembly to form extremely small (e.g., nano-scale) structures. The self-assembly may occur under the influence of surface energy, molecular affinities, and other surface-related and chemical-related forces.

In any case, in some embodiments, self-assembly of block copolymers, whether based on hydrophobic-hydrophilic differences or otherwise, may be used to form extremely small periodic structures (e.g., precisely spaced nano-scale structures or lines). In some embodiments, they may be used to form nano-scale lines or other nano-scale structures that can ultimately be used to form semiconductor fin lines.

FIG. 4Eillustrates the structure ofFIG. 4Dfollowing removal of one of the blocks of the di-block co-polymer. In an embodiment, the polymer portions414are removed selectively through a wet or dry etch process to leave portions416(A/B). The pitch of the remaining portions416(A/B) is approximately half the pitch of the first patterned hardmask404.

FIG. 4Fillustrates the structure ofFIG. 4Efollowing transfer of the pattern of the remaining polymer portions into the underlying bull crystalline semiconductor substrate. In an embodiment, the pattern of the remaining polymer portion416(A/B), i.e., the pattern of first patterned hardmask404as pitch halved, is etched into the bulk semiconductor substrate402. The patterning patterns second hardmask layer408to form second patterned hardmask layer424corresponding to polymer portions416B. First patterned hardmask404corresponds to polymer portions416A. In an embodiment, a plurality of fins418is formed directly in the bulk substrate402which becomes patterned substrate420and, as such, are formed continuous with the bulk substrate402/420at an approximately planar surface422.

FIG. 4Gillustrates the structure ofFIG. 4Ffollowing removal of the remaining polymer layer and any brush layers. In an embodiment, the remaining polymer layer416(A/B) and the brush layer410are removed to leave the plurality of alternating fins418having alternating “colored” first patterned hardmask404and second patterned hardmask424thereon. In one embodiment, the remaining polymer layer416(A/B) and the brush layer410are removed using an ashing and cleans process. The resulting pitch426of the fins is half of the pitch406of the original first patterned hardmask404.

FIG. 4Hillustrates the structure ofFIG. 4Gfollowing formation of an inter-layer dielectric (ILD) layer428between the plurality of fins418. In an embodiment, the ILD layer428is composed of silicon dioxide, such as is used in a shallow trench isolation fabrication process. However, other dielectrics may be used instead, such as nitrides of carbides. The ILD layer428may be deposited by a chemical vapor deposition (CVD) or other deposition process (e.g., ALD, PECVD, PVD, HDP assisted CVD, low temp CVD) and may be planarized by a chemical mechanical polishing (CMP) technique to reveal uppermost surfaces of hardmask layers404and428.

FIG. 4Iillustrates the structure ofFIG. 4Hfollowing formation and patterning of a photoresist material to form a patterned mask430. In an embodiment, patterned mask430has an opening432formed therein. The opening432exposes a target one of the plurality of fins418having first patterned hardmask404thereon for ultimate fin removal. The opening432has a cut dimension436. In an embodiment, restraints on the cut dimension436are relaxed, and may even expose portions of neighboring fins having second patterned hardmask424thereon. In an embodiment, the patterning operation prepares for cutting away of unwanted features using “coloring” or hardmask material differentiation to allow for cut sizes to be twice the pitch426of the features418(i.e., to result in the original pitch406). In one embodiment, the hardmask material allows differentiation through plasma or wet etch selectivity between the two hardmask materials. Furthermore, the edge placement error (EPE)434is half pitch. By comparison, in a standard patterning process, without coloring, the cut dimension is 1× pitch and the edge-placement error (EPE) is ¼ pitch. Thus, in an embodiment, the process described herein doubles the edge placement error budget and doubles the size of the holes or openings required to cut a single feature.

In an embodiment, patterned mask430is composed of a photoresist layer, as is known in the art, and may be patterned by conventional lithography and development processes. In a particular embodiment, the portions of the photoresist layer exposed to the light source are removed upon developing the photoresist layer. Thus, patterned photoresist layer is composed of a positive photoresist material. In a specific embodiment, the photoresist layer is composed of a positive photoresist material such as, but not limited to, a 248 nm resist, a 193 nm resist, a 157 nm resist, an extreme ultraviolet (EUV) resist, an e-beam resist, an imprint layer, or a phenolic resin matrix with a diazonaphthoquinone sensitizer. In another particular embodiment, the portions of the photoresist layer exposed to the light source are retained upon developing the photoresist layer. Thus, the photoresist layer is composed of a negative photoresist material. In a specific embodiment, the photoresist layer is composed of a negative photoresist material such as, but not limited to, consisting of poly-cis-isoprene or poly-vinyl-cinnamate. In an embodiment, lithographic operations are performed using 193 nm immersion lithography (193i), EUV and/or electron-beam direct write (EBDW) lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, the patterned mask430is a trilayer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon-containing ARC layer. In one such embodiment, a spin-on glass material with added chromophores is used to aid in suppressing reflectivity. Chemically they are (siloxanes) silicon-carbon containing polymers. When annealed they form a mixture of silicon dioxide and carbon polymers.

FIG. 4Jillustrates the structure ofFIG. 4Ifollowing etching of the select one of the plurality of fins418and subsequent removal of patterned mask430. In one embodiment, this process is referred to as a “fin cut”, or “feature selection” operation of the process. In an embodiment, one of the plurality of fins418is removed at location438to form patterned plurality of fins418′ having a first interrupted pattern. In one such embodiment, the exposed first patterned hardmask404is first removed using an etch process selective to any exposed second patterned hardmask424and selective to ILD layer428. In another embodiment, a “fin keep” approach is used, where the features are selected using the opposite tone of photoresist and protected during the etch process while the background or unprotected fins are removed. It is the reverse polarity of the lithographic process (e.g., negative vs. positive tone imaging). It is to be appreciated that either process can be used at this operation. The exposed fin is then removed at location438with an etch process selective to exposed second patterned hardmask424and selective to ILD layer428. In a first embodiment, the fin is removed at location438to a level440leaving a protruding portion446above planar surface422. In a second embodiment, the fin is removed at location438to a level442approximately co-planar with planar surface422. In a third embodiment, the fin is removed at location438to a level444leaving a recess448below planar surface422.

FIG. 4Killustrates the structure ofFIG. 4Jfollowing formation and patterning of a photoresist material to form a patterned mask450. In an embodiment, patterned mask450has an opening452formed therein. The opening452exposes a target second of the plurality of fins418′ having second patterned hardmask424thereon for ultimate fin removal. In an embodiment, the patterning operation prepares for cutting away of unwanted features using “coloring” or hardmask material differentiation to allow for cut sizes to be twice the pitch426of the features418′. As described in association withFIG. 4I, the process described herein doubles the edge placement error budget and doubles the size of the holes or openings required to cut a single feature. In an embodiment, patterned mask450is composed of a material such as described in association withFIG. 4I.

FIG. 4Lillustrates the structure ofFIG. 4Kfollowing etching of the select second of the plurality of fins418′. In an embodiment, the second of the plurality of fins418′ is removed at location454to form patterned plurality of fins418″ having a second interrupted pattern. In one such embodiment, the exposed second patterned hardmask424is first removed using an etch process selective to any exposed first patterned hardmask104and selective to ILD layer428. The exposed fin is then removed at location454with an etch process selective to exposed first patterned hardmask404and selective to ILD layer428. In a first embodiment, the fin is removed at location454to a level456leaving a protruding portion above planar surface422at a height above surface440of protruding portion446. In a second embodiment, the fin is removed at location454to a level458leaving a protruding portion464above planar surface422and at approximately the same height as surface440of protruding portion446. In a third embodiment, the fin is removed at location454to a level460approximately co-planar with planar surface422. In a fourth embodiment, the fin is removed at location454to a level462leaving a recess466below planar surface422.

FIG. 4Millustrates the structure ofFIG. 4Lfollowing removal of the patterned mask450and formation of an inter-layer dielectric (ILD) layer468over the plurality of fins418″ and in locations438and454of removed fins. In an embodiment, the ILD layer468is composed of silicon dioxide, such as is used in a shallow trench isolation fabrication process. However, other dielectrics may be used instead, such as nitrides or carbides. The ILD layer468may be deposited by a chemical vapor deposition (CVD) or other deposition process (e.g., ALD, PECVD, PVD, HDP assisted CVD, low temp CVD). Spin-on materials are another common option for these films. Many low-k dielectric materials can be spun-on the wafer and cured. These are commonly used in the industry.

FIG. 4Nillustrates the structure ofFIG. 4Mfollowing planarization of ILD layer468and removal of first and second patterned hardmasks404and424. In an embodiment, a chemical mechanical polishing (CMP) technique is used to remove the first patterned hardmask404and the second hardmask424, to recess the ILD layers428and468to formed planarized ILD layer428′ and468′, respectively, and to expose surfaces of the plurality of fins418″. In an embodiment, the planarized ILD layer428′ is composed of substantially the same material as planarized ILD layer468′. In another embodiment, the planarized ILD layer428′ is composed of a different material than planarized ILD layer468′. In either case, in an embodiment, a seam is formed between ILD layer468′ and ILD layer428′, e.g., at location438or454. It is to be appreciated that, in an embodiment, the exposed surface of the plurality of fins418″ can be used to form planar semiconductor devices.

In accordance with another embodiment,FIG. 5illustrates the structure ofFIG. 4Nfollowing exposing of upper portions of the plurality of fins418″. Referring toFIG. 5, the ILD layer468′ and the ILD layer428′ are recessed to expose protruding portions472of fins418′ and to provide recessed ILD layer468″ and recessed ILD layer428″ to a recess height476. The recess height476defines a location between upper fin portions472and lower fin portions474. The recessing of the ILD layer468′ and the ILD layer428′ may be performed by a plasma, vapor or wet etch process. In one embodiment, a dry etch process selective to silicon fins418″ is used, the dry etch process based on a plasma generated from gases such as, but not limited to NF3, CHF3, C4F5, HBr and O2with typically pressures in the range of 30-100 mTorr and a plasma bias of 50-1000 Watts.

In an exemplary embodiment, referring again toFIGS. 4J, 4L and 5, a semiconductor structure includes a plurality of semiconductor fins418″ protruding from a substantially planar surface422of a semiconductor substrate420. The plurality of semiconductor fins418″ has a grating pattern interrupted by a first location438having a first fin portion446having a first height. The grating pattern of the semiconductor fins is further interrupted by a second location454having a second fin portion464having a second height. In one embodiment, the second height of the second fin portion454is different from the first height of the first fin portion446. In another embodiment, the second height of the second fin portion454is the same as the first height of the first fin portion446. In an embodiment, the grating pattern has a constant pitch126when viewed without the interruptions.

In an exemplary embodiment, referring again toFIGS. 4J, 4L, and 5, a semiconductor structure includes a plurality of semiconductor fins418″ protruding from a substantially planar surface422of a semiconductor substrate420. The plurality of semiconductor fins418″ has a grating pattern interrupted by a first location438having a first recess. In one embodiment, the grating pattern of the semiconductor fins is further interrupted by a second location454having one of a second recess, or a fin portion. In an embodiment, the grating pattern has a constant pitch426when viewed without the interruptions. In an embodiment, a trench isolation layer468″ is disposed in and over the recess.

It is to be appreciated that the above approach may be applied to fabricating other semiconductor geometries beyond semiconductor fins. For example, in an embodiment, the above approach is implemented for fabricating semiconductor nanowires or semiconductor nanoribbons. In an embodiment, the term “semiconductor body” or “semiconductor bodies” refers generally to geometries such as fins, nanowires and nanoribbons.

It is to be appreciated that the structures resulting from the above exemplary processing schemes, e.g., structures fromFIGS. 4N and 5, may be used in a same or similar form for subsequent processing operations to complete device fabrication, such as PMOS and NMOS device fabrication. As an example of a completed device,FIGS. 6A and 6Billustrate a cross-sectional view and a plan view (taken along the a-a′ axis of the cross-sectional view), respectively, of a non-planar semiconductor device, in accordance with an embodiment of the present disclosure.

Referring toFIG. 6A, a semiconductor structure or device600includes a non-planar active region (e.g., a fin structure including protruding fin portion604and sub-fin region605) formed from substrate602, and within isolation region606. A gate line608is disposed over the protruding portions604of the non-planar active region as well as over a portion of the isolation region606. As shown, gate line608includes a gate electrode650and a gate dielectric layer652. In one embodiment, gate line608may also include a dielectric cap layer654. A gate contact614, and overlying gate contact via616are also seen from this perspective, along with an overlying metal interconnect660, all of which are disposed in inter-layer dielectric stacks or layers670. Also seen from the perspective ofFIG. 6A, the gate contact614is, in one embodiment, disposed over isolation region606, but not over the non-planar active regions.

As is also depicted inFIG. 6A, in an embodiment, an artifact of fin select recessing remains in the final structure. For example, in the embodiment shown, a residual protruding portion699remains. In other embodiments, a recess may remain, as described above.

As is also depicted inFIG. 6A, in an embodiment, an interface680exists between a protruding fin portion604and sub-fin region605. The interface680can be a transition region between a doped sub-fin region605and a lightly or undoped upper fin portion604. In one such embodiment, each fin is approximately 10 nanometers wide or less, and sub-fin dopants are supplied from an adjacent solid state doping layer at the sub-fin location. In a particular such embodiment, each fin is less than 10 nanometers wide.

Referring toFIG. 6B, the gate line608is shown as disposed over the protruding fin portions604. Source and drain regions604A and604B of the protruding fin portions604can be seen from this perspective. In one embodiment, the source and drain regions604A and604B are doped portions of original material of the protruding fin portions604. In another embodiment, the material of the protruding fin portions604is removed and replaced with another semiconductor material, e.g., by epitaxial deposition. In either case, the source and drain regions604A and604B may extend below the height of dielectric layer606, i.e., into the sub-fin region605. In accordance with an embodiment of the present disclosure, the more heavily doped sub-fin regions, i.e., the doped portions of the fins below interface680, inhibits source to drain leakage through this portion of the bulk semiconductor fins.

In an embodiment, the semiconductor structure or device600is a non-planar device such as, but not limited to, a fin-FET or a tri-gate device. In such an embodiment, a corresponding semiconducting channel region is composed of or is formed in a three-dimensional body. In one such embodiment, the gate electrode stacks of gate lines608surround at least a top surface and a pair of sidewalls of the three-dimensional body.

Substrate602may be composed of a semiconductor material that can withstand a manufacturing process and in which charge can migrate. In an embodiment, substrate602is a bulk substrate composed of a crystalline silicon, silicon/germanium or germanium layer doped with a charge carrier, such as but not limited to phosphorus, arsenic, boron or a combination thereof, to form active region604. In one embodiment, the concentration of silicon atoms in bulk substrate602is greater than 97%. In another embodiment, bulk substrate602is composed of an epitaxial layer grown atop a distinct crystalline substrate, e.g. a silicon epitaxial layer grown atop a boron-doped bulk silicon mono-crystalline substrate. Bulk substrate602may alternatively be composed of a group III-V material. In an embodiment, bulk substrate602is composed of a III-V material such as, but not limited to, gallium nitride, gallium phosphide, gallium arsenide, indium phosphide, indium antimonide, indium gallium arsenide, aluminum gallium arsenide, indium gallium phosphide, or a combination thereof. In one embodiment, bulk substrate602is composed of a III-V material and the charge-carrier dopant impurity atoms are ones such as, but not limited to, carbon, silicon, germanium, oxygen, sulfur, selenium or tellurium.

Isolation region606may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, portions of a permanent gate structure from an underlying bulk substrate or isolate active regions formed within an underlying bulk substrate, such as isolating fin active regions. For example, in one embodiment, the isolation region606is composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

Gate line608may be composed of a gate electrode stack which includes a gate dielectric layer652and a gate electrode layer650. In an embodiment, the gate electrode of the gate electrode stack is composed of a metal gate and the gate dielectric layer is composed of a high-K material. For example, in one embodiment, the gate dielectric layer is composed of a material such as, but not limited to, hafnium oxide, hafnium oxy-nitride, hafnium silicate, lanthanum oxide, zirconium oxide, zirconium silicate, tantalum oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. Furthermore, a portion of gate dielectric layer may include a layer of native oxide formed from the top few layers of the substrate602. In an embodiment, the gate dielectric layer is composed of a top high-k portion and a lower portion composed of an oxide of a semiconductor material. In one embodiment, the gate dielectric layer is composed of a top portion of hafnium oxide and a bottom portion of silicon dioxide or silicon oxy-nitride. In some implementations, a portion of the gate dielectric is a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate.

In one embodiment, the gate electrode is composed of a metal layer such as, but not limited to, metal nitrides, metal carbides, metal silicides, metal aluminides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel or conductive metal oxides. In a specific embodiment, the gate electrode is composed of a non-workfunction-setting fill material formed above a metal workfunction-setting layer. The gate electrode layer may consist of a P-type workfunction metal or an N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a conductive fill layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5.2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV. In some implementations, the gate electrode may consist of a “U”-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the disclosure, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

Spacers associated with the gate electrode stacks may be composed of a material suitable to ultimately electrically isolate, or contribute to the isolation of, a permanent gate structure from adjacent conductive contacts, such as self-aligned contacts. For example, in one embodiment, the spacers are composed of a dielectric material such as, but not limited to, silicon dioxide, silicon oxy-nitride, silicon nitride, or carbon-doped silicon nitride.

Gate contact614and overlying gate contact via616may be composed of a conductive material. In an embodiment, one or more of the contacts or vias are composed of a metal species. The metal species may be a pure metal, such as tungsten, nickel, or cobalt, or may be an alloy such as a metal-metal alloy or a metal-semiconductor alloy (e.g., such as a silicide material).

In an embodiment (although not shown), providing structure600involves formation of a contact pattern which is very well aligned to an existing gate pattern while eliminating the use of a lithographic operation with exceedingly tight registration budget. In one such embodiment, this approach enables the use of intrinsically highly selective wet etching (e.g., versus conventionally implemented dry or plasma etching) to generate contact openings. In an embodiment, a contact pattern is formed by utilizing an existing gate pattern in combination with a contact plug lithography operation. In one such embodiment, the approach enables elimination of the need for an otherwise critical lithography operation to generate a contact pattern, as used in conventional approaches. In an embodiment, a trench contact grid is not separately patterned, but is rather formed between poly (gate) lines. For example, in one such embodiment, a trench contact grid is formed subsequent to gate grating patterning but prior to gate grating cuts.

Furthermore, the gate stack structure608may be fabricated by a replacement gate process. In such a scheme, dummy gate material such as polysilicon or silicon nitride pillar material, may be removed and replaced with permanent gate electrode material. In one such embodiment, a permanent gate dielectric layer is also formed in this process, as opposed to being carried through from earlier processing. In an embodiment, dummy gates are removed by a dry etch or wet etch process. In one embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a dry etch process including use of SF6. In another embodiment, dummy gates are composed of polycrystalline silicon or amorphous silicon and are removed with a wet etch process including use of aqueous NH4OH or tetramethylammonium hydroxide. In one embodiment, dummy gates are composed of silicon nitride and are removed with a wet etch including aqueous phosphoric acid.

In an embodiment, one or more approaches described herein contemplate essentially a dummy and replacement gate process in combination with a dummy and replacement contact process to arrive at structure600. In one such embodiment, the replacement contact process is performed after the replacement gate process to allow high temperature anneal of at least a portion of the permanent gate stack. For example, in a specific such embodiment, an anneal of at least a portion of the permanent gate structures, e.g., after a gate dielectric layer is formed, is performed at a temperature greater than approximately 600 degrees Celsius. The anneal is performed prior to formation of the permanent contacts.

Referring again toFIG. 6A, the arrangement of semiconductor structure or device600places the gate contact over isolation regions. Such an arrangement may be viewed as inefficient use of layout space. In another embodiment, however, a semiconductor device has contact structures that contact portions of a gate electrode formed over an active region. In general, prior to (e.g., in addition to) forming a gate contact structure (such as a via) over an active portion of a gate and in a same layer as a trench contact via, one or more embodiments of the present disclosure include first using a gate aligned trench contact process. Such a process may be implemented to form trench contact structures for semiconductor structure fabrication, e.g., for integrated circuit fabrication. In an embodiment, a trench contact pattern is formed as aligned to an existing gate pattern. By contrast, conventional approaches typically involve an additional lithography process with tight registration of a lithographic contact pattern to an existing gate pattern in combination with selective contact etches. For example, a conventional process may include patterning of a poly (gate) grid with separate patterning of contact features.

It is to be appreciated that not all aspects of the processes described above need be practiced to fall within the spirit and scope of embodiments of the present disclosure. For example, in one embodiment, dummy gates need not ever be formed prior to fabricating gate contacts over active portions of the gate stacks. The gate stacks described above may actually be permanent gate stacks as initially formed. Also, the processes described herein may be used to fabricate one or a plurality of semiconductor devices. The semiconductor devices may be transistors or like devices. For example, in an embodiment, the semiconductor devices are a metal-oxide semiconductor (MOS) transistors for logic or memory, or are bipolar transistors. Also, in an embodiment, the semiconductor devices have a three-dimensional architecture, such as a trigate device, an independently accessed double gate device, or a FIN-FET. One or more embodiments may be particularly useful for fabricating semiconductor devices at a sub-10 nanometer (10 nm) technology node.

It is to be appreciated that in the above exemplary FEOL embodiments, in an embodiment, sub-10 nanometer processing is implemented to directly to in the fabrication schemes and resulting structures. In other embodiment, FEOL considerations may be driven by BEOL sub-10 nanometer processing requirements. For example, material selection and layouts for FEOL layers and devices may need to accommodate BEOL sub-10 nanometer processing. In one such embodiment, material selection and gate stack architectures are selected to accommodate high density metallization of the BEOL layers, e.g., to reduce fringe capacitance in transistor structures formed in the FEOL layers but coupled together by high density metallization of the BEOL layers. As such, FEOL structures and processing may be directly impacted by sub-10 nanometer processing or may be indirectly impacted as a result of sub-10 nanometer processing of BEOL layers.

Back end of line (BEOL) layers of integrated circuits commonly include electrically conductive microelectronic structures, which are known in the arts as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias are typically formed by a lithographic process. Representatively, a photoresist layer may be spin coated over a dielectric layer, the photoresist layer may be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer may be developed in order to form an opening in the photoresist layer. Next, an opening for the via may be etched in the dielectric layer by using the opening in the photoresist layer as an etch mask. This opening is referred to as a via opening. Finally, the via opening may be filled with one or more metals or other conductive materials to form the via.

In the past, the sizes and the spacing of vias has progressively decreased, and it is expected that in the future the sizes and the spacing of the vias will continue to progressively decrease, for at least some types of integrated circuits (e.g., advanced microprocessors, chipset components, graphics chips, etc.). When patterning extremely small vias with extremely small pitches by such lithographic processes, several challenges present themselves. One such challenge is that the overlay between the vias and the overlying interconnects, and the overlay between the vias and the underlying landing interconnects, generally need to be controlled to high tolerances on the order of a quarter of the via pitch. As via pitches scale ever smaller over time, the overlay tolerances tend to scale with them at an even greater rate than lithographic equipment is able to keep up.

Another such challenge is that the critical dimensions of the via openings generally tend to scale faster than the resolution capabilities of the lithographic scanners. Shrink technologies exist to shrink the critical dimensions of the via openings. However, the shrink amount tends to be limited by the minimum via pitch, as well as by the ability of the shrink process to be sufficiently optical proximity correction (OPC) neutral, and to not significantly compromise line width roughness (LWR) and/or critical dimension uniformity (CDU). Yet another such challenge is that the LWR and/or CDU characteristics of photoresists generally need to improve as the critical dimensions of the via openings decrease in order to maintain the same overall fraction of the critical dimension budget. However, currently the LWR and/or CDU characteristics of most photoresists are not improving as rapidly as the critical dimensions of the via openings are decreasing.

A further such challenge is that the extremely small via pitches generally tend to be below the resolution capabilities of even extreme ultraviolet (EUV) lithographic scanners. As a result, commonly several different lithographic masks may be used, which tend to increase the costs. At some point, if pitches continue to decrease, it may not be possible, even with multiple masks, to print via openings for these extremely small pitches using EUV scanners.

The above factors are also relevant for considering placement and scaling of non-conductive spaces or interruptions between metal lines (referred to as “plugs,” “dielectric plugs” or “metal line ends” among the metal lines of back end of line (BEOL) metal interconnect structures. The above factors are also relevant for conductive tabs which, by definition, are conductive linkers between two conductive metal lines, such as between two parallel conductive lines. The tabs are typically in a same layer as the metal lines. Thus, improvements are needed in the area of back end metallization manufacturing technologies for fabricating metal lines, metal vias, conductive tabs, and dielectric plugs.

In some embodiments described below, patterning and aligning of via features (or other BEOL features) is achieved using several reticles and critical alignment strategies. In other embodiments, by contrast, approaches described herein enable fabrication of self-aligned plugs and/or vias. In latter embodiments, it may be the case that only one critical overlay step (Mx+1 grating) need be implemented.

It is to be appreciated that the layers and materials described below in association with back end of line (BEOL) structures and processing are typically formed on or above an underlying semiconductor substrate or structure, such as underlying device layer(s) of an integrated circuit. In an embodiment, an underlying semiconductor substrate represents a general workpiece object used to manufacture integrated circuits. The semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials, such as substrates including germanium, carbon, or group III-V materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. Furthermore, the structures depicted may be fabricated on underlying lower level interconnect layers.

Although the following methods of fabricating a metallization layer, or portions of a metallization layer, of a BEOL metallization layer are described in detail with respect to select operations, it is to be appreciated that additional or intermediate operations for fabrication may include standard microelectronic fabrication processes such as lithography, etch, thin films deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, the use of sacrificial layers, the use of etch stop layers, the use of planarization stop layers, and/or any other associated action with microelectronic component fabrication. Also, it is to be appreciated that the process operations described for the following process flows may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed.

In some cases, the resulting structures enable fabrication of vias that are directly centered on underlying metal lines. The vias may be wider than, narrower than, or the same thickness as the underlying metal lines, e.g., due to non-perfect selective etch processing. Nonetheless, in an embodiment, the centers of the vias are aligned (match up) with the centers of the metal lines. As such, in an embodiment, offset due to conventional lithograph/dual damascene patterning that must otherwise be tolerated, may not be a factor for the resulting structures of one or more of the following process schemes.

It is to be appreciated that some of the interconnect fabrication schemes described below can be implemented to save numerous alignment/exposures, can be implemented to improve electrical contact (e.g., by reducing via resistance), or can be implemented to reduce total process operations and processing time otherwise required for patterning such features using conventional approaches. It is also to be appreciated that in subsequent or additional fabrication operations beyond those shown, in some instances, dielectric layer(s) may be removed from a layer of metal lines to provide air gaps between the metal lines.

In accordance with an embodiment of the present disclosure, a backbone approach is described. The backbone approach may involve multiple stages of atomic layer deposition (ALD). In an embodiment, tight pitch formation is achieved by iterative spacer formation, e.g., using ALD processing.

To provide context, lithographic patterning of features for semiconductor manufacturing is limited to the resolution of imaging tool whether it be optical (e.g. 193 nm), electron beam or EUV. Process methods such as multiple pass patterning, pattern shrink methods and spacer-based pitch division can be used to extend the resolution by factors of 2 to 4 or even possibly a factor of 8. Such methods, however, may be limited in that the process variation in the original lithographic steps remain with the similar magnitude in the final pattern. For example, a lithographic operation may have a variation of +/−3 nm. If this is employed with pitch division process methods to generate a final pitch of 8 nm (4 nm feature size), the resulting final patterns vary by 4 nm+/−3 nm.

One or more embodiments described herein involve the use of iterative spacer or thin film deposition to define all or substantially all of the final critical small features for a layer such as a BEOL layer. The variation of such features may be better than +/−1 nm which is consistent with ALD technology. Multiple materials may be employed to enable “coloring” of patterns to enable addressing alternative features (e.g., vias, cuts, plugs, etc.) with enlarged margin for edge placement errors.

FIGS. 7A and 7Billustrate cross-sectional views of target foundation structures for enabling very tight pitch final patterns for semiconductor layers, in accordance with embodiments of the present disclosure.

Referring toFIG. 7A, a target foundation layer700includes a patterning layer702above a hardmask layer704above a transfer layer706above a substrate708. The patterning layer702includes backbone features710. The backbone features710are relatively wider features (e.g., 6-12 nanometers) with intervening groupings712of relatively smaller features (e.g., 6-100 s of smaller features between adjacent backbone features710, where the smaller features are, e.g., 4-6 nanometers wide).

In an embodiment, each of the intervening groupings712of relatively smaller features includes small features716of a first material type, small features714of a second material type different from the first material type, and small features718of a third material type different from the first material type and the second material type. The difference in material types may provide differing etch characteristics or selectivity between the material types. In an embodiment, the material of the backbone features710is the same as the material of the third material type of the small features718, as is depicted inFIG. 7A. In another embodiment, the material of the backbone features710is the different from the material of the third material type of the small features718, but has similar etch characteristics or selectivity the third material type of the small features718.

Referring toFIG. 7B, a target foundation layer750includes a patterning layer752above a hardmask layer754above a transfer layer756above a substrate758. The patterning layer752includes backbone features760. The backbone features760are relatively wider features (e.g., 6-12 nanometers) with intervening groupings762of relatively smaller features (e.g., 6-100 s of smaller features between adjacent backbone features760, where the smaller features are, e.g., 4-6 nanometers wide).

In an embodiment, each of the intervening groupings762of relatively smaller features includes small features764of a first material type, small features766of a second material type different from the first material type, and small features768of a third material type different from the first material type and the second material type. The difference in material types may provide differing etch characteristics or selectivity between the material types. In an embodiment, the material of the backbone features760is the same as the material of the second material type of the small features766, as is depicted inFIG. 7B. In another embodiment, the material of the backbone features760is the different from the material of the second material type of the small features766, but has similar etch characteristics or selectivity the third material type of the small features766.

Referring to bothFIGS. 7A and 7B, in an embodiment, the structures700or750include several iterative vertical layers of alternating materials that will ultimately define the final locations of features in a semiconductor pattern (e.g., metals, transistors, etc.) Occasional larger feature are present as they represent the lithographically defined structures that, in an embodiment, are larger (wider) since they have larger size variation. In an embodiment, six to hundreds of narrow features are between the wide features.

FIGS. 8A-8Hillustrate cross-sectional views of representing various operations in a method of fabricating target foundation structures for enabling very tight pitch final patterns for semiconductor layers, in accordance with embodiments of the present disclosure. Overall, in an embodiment, iterative thin film generation operations are employed. For example, conformal thin film deposition followed by an anisotropic etch (e.g., spacer formation), selective growth, or directed self-assembly (DSA) is performed. A patterning process such as described below may be implemented to provide a patterning process suitable to generate very tight pitch final patterns for semiconductor layers. In an embodiment, advantages of implementing such a process flow include improved dimensional control of tight pitch features with a built-in method to color alternating features to allow self-aligned via, plug and cut formation.

FIG. 8Aillustrates a process operation involving tall backbone formation. A plurality of backbone features808is formed above a hardmask layer806formed above a transfer layer804formed above a substrate802. In an embodiment, formation of the plurality of backbone features808involves use of a standard lithography operation (e.g., 193 nm or EUV) followed by etch transfer into a hardmask (e.g., SiN, SiO2, SiC) and then removal of any remaining resist and/or anti-reflection layers (e.g., thru ash or wet cleans).

FIG. 8Billustrates a process operation involving first spacer (spacer1) formation. A first set of small features810of a first material composition is formed along the sidewalls of each of the plurality of backbone features808. In an embodiment, the first set of small features810is formed using a deposition (e.g., ALD) and etch approach. In another embodiment, the first set of small features810is formed using a selective growth approach.

FIG. 8Cillustrates a process operation involving second spacer (spacer2) formation, third spacer (spacer3) formation, and fourth spacer (spacer4) formation, with the specific layers shown as one possible exemplary embodiment. A second set of small features812of a second material composition is formed along the exposed sidewalls of each of the first set of small features810. A third set of small features814of a third material composition is formed along the exposed sidewalls of each of the second set of small features812. A fourth set of small features816of the second material composition is formed along the exposed sidewalls of each of the third set of small features814. In an embodiment, the second set of small features812is first formed using a deposition (e.g., ALD) and etch approach or selective growth approach. The third set of small features814is then formed using another deposition (e.g., ALD) and etch approach or selective growth approach. The fourth set of small features816is then formed using another deposition (e.g., ALD) and etch approach or selective growth approach.

FIG. 8Dillustrates a process operation involving continued layer generation. Additional spacer layers818are formed in sequence with select ordering of material types. The additional spacer layers818may be fabricated using deposition and etch approaches, selective growth approaches, or a combination thereof. It is to be appreciated that more layers mat be added than are shown. For example, in an embodiment, additional 20-200 sets of spacers are formed at this stage. The deposition of spacers may be completed prior to merging of adjacent sidewall growth, e.g., spacer formation is halted when an opening820remains. It is to be appreciated that although deposition and etch approaches or selective growth approaches are described as options forFIGS. 8A-8D, directed self-assembly (DSA) may be used in place of or as one of the options for spacer formation described herein. In one such example, tri-block based DSA is used. An example of tri-block based DSA is described below in association withFIGS. 12A-12K.

In an embodiment, referring collectively toFIGS. 8A-8D, iterative generation of thin layers of alternating materials on sides of original lithography-defined template features is performed. One potential method to achieve such a structure is through thin film deposition followed by anisotropic etch. In an embodiment, a single process tool is used to perform both the deposition and etch to greatly improve the efficiency of this approach. Other methods of generating thin layers of well-controlled thickness include selective growth or DSA.

FIG. 8Eillustrates a process operation involving backbone removal. The backbone features808are removed to leave openings822. In an embodiment, the openings822have a width approximately the same as the width of opening820, as is depicted inFIG. 8E. In an embodiment, each of the openings820and822has spacers824as sidewalls, the spacers824of the first material composition. As indicated, some of the spacers824are as re-designated from previously labeled spacers810. In an embodiment, the backbone features808are removed in order to provide more space for further small feature generation.

FIG. 8Fillustrates a process operation involving continued layer generation. The openings820and822are ultimately completely filled using continued spacer formation. In an exemplary embodiment, spacers826are formed along the exposed sidewalls of the spacers824. In one such embodiment, the spacers826are of the second material composition. In an embodiment, a final wide feature828is ultimately formed at the centers of each of the openings820and822at a stage when further spacer formation is not desired or achievable. In an embodiment, the formation of the final wide features828involves merging of material growth formed along adjacent sidewalls of the spacers826. In one such embodiment, the merging of material growth provides final wide features828each having a seam approximately centered within the final wide feature828. In an embodiment, the final wide features828are of the third material composition.

FIG. 8Gillustrates a process operation involving planarization of the structure ofFIG. 8F. In an embodiment, the planarization is performed using a chemical mechanical polishing (CMP) operation. In an embodiment, the planarization process provides a flat structure prior to plug/cut and via process operations. The locations828directly centered under the original lithographic features (which resulted in openings822) and half-way spaced there between (which resulted in opening820) may be targeted to be larger in order to accommodate larger size variation associated with lithographic operations compared to a single thin film (plus etch) operation. In an embodiment, as shown, the structure ofFIG. 8Gis similar to or the same as described in association withFIG. 7A.

FIG. 8Hillustrates a process operation involving selective removal of all of the features of the first material composition, e.g., spacers810/824(corresponding to small features716of the first material type from the structure ofFIG. 7A, as shown inFIG. 8G). In an embodiment, the small features716of the first material type are removed using a selective etch process that does not remove, or only marginally removes the remaining spacer materials. In the exemplary embodiment shown inFIG. 8H, subsequent to removing the small features716of the first material type, metal line patterning features830are formed in the openings created upon removing of all of the small features716of the first material type. Some of the metal line patterning features830are associated with underlying via patterning features832. Although not depicted, select ones of the small features716of the first material type may be retained (e.g., through a photolithography blocking process that blocks the select ones of the small features716of the first material type from removal) to form plug patterning features. In an embodiment, the metal line patterning features830, the via patterning features832, and any plug patterning features, are ultimately patterned into the hardmask layer806and transfer layer804for ultimate patterning of an underlying layer. In another embodiment, as depicted, the metal line patterning features830, the via patterning features832, and any plug patterning features actually represent metal lines, vias and plugs formed in the layer834as shown. Whether metal line patterning features830or actual metal lines, each may have an overlying hardmask cap layer836to protect the features during subsequent processing of layer834, as is depicted inFIG. 8H. Referring again toFIG. 8H, in an embodiment, by only removing one spacer type, additional margin is provided for process variation in plug, via and/or cut patterning operations.

FIGS. 8H′ and8H″ illustrate cross-sectional views of exemplary structures following via and plug patterning, in accordance with an embodiment of the present disclosure.

FIG. 8H′ illustrates a process operation involving selective removal of all of the material of the backbone features710and all of the small features718of the third material type from the structure of8H. In an embodiment, the backbone features710and the small features718of the third material type are removed using a selective etch process that does not remove, or only marginally removes the remaining spacer materials or already replaced spacer materials. In the exemplary embodiment shown inFIG. 8H′, subsequent to removing backbone features710and the small features718of the third material type, second metal line patterning features838are formed in most or all of the openings created upon removing the backbone features710and the small features718of the third material type. In one embodiment, any remaining of the openings created upon removing the backbone features710and the small features718of the third material type are filled with a plug material850(e.g., to provide a line-end feature composed of non-conductive material such as SiN or SiO2), or are preserved as a plug region. Some of the second metal line patterning features838are associated with underlying second via patterning features840. In an embodiment, the second metal line patterning features838, the second via patterning features840, and any plug patterning features850, are ultimately patterned into the hardmask layer806and transfer layer804for ultimate patterning of an underlying layer. In another embodiment, as depicted, the second metal line patterning features838, the second via patterning features840, and any plug patterning features850actually represent metal lines, vias and plugs, respectively.

It is to be appreciated that since the metal lines830(or patterning features) and the second metal lines838(or patterning features) are formed in different processing operations, the composition of the metal lines830and second metal lines838may differ. In an exemplary embodiment,FIG. 8H″ illustrates an example where metal lines830′ differ in composition from metal lines838. Thus, alternating features may be composed of different conducting material.

It is to be appreciated that some older forms of spacer-based pitch division techniques may be used in high volume manufacturing. Embodiments described above surrounding the backbone approach may be implemented to extend one or two passes of spacer-based pitch division to a very high number of iterative spacer formation operations. One or more embodiments provides an approach for semiconductor chip density scaling at high manufacturing yields. One or more embodiments provide an approach for fabricating dense interconnects, or even transistors (if applied to FEOL processing), with consistently well-formed feature sizes. It is to be appreciated that reverse engineering of a product fabricated using a backbone approach may reveal predominantly tight pitch features (e.g., sub 10 nm pitch features) with occasional wide one-dimensional (1D) features. Cross-sectional scanning electron microscopy (XSEM) may reveal “colored” (e.g., differing from one another with respect to a property such as etch selectivity) hardmasks on alternating features.

In accordance with an embodiment of the present disclosure, pitch division is applied to provide an approach for fabricating alternating metal lines in a BEOL fabrication scheme. One or more embodiments described herein are directed to pitch division patterning process flows that increase overlay margins for vias, cuts and plugs. Embodiments may enable continued scaling of the pitch of metal layers beyond the resolution capability of state-of-the art lithography equipment. In an embodiment, spacing between metal lines is constant and can be controlled to Angstrom level precision using ALD. In an embodiment, a process flow is designed so that a “replacement ILD” flow is possible. That is, the ILD can be deposited after the pattern and metallization is complete. The patterning flows typically damage the ILD through the etch/cleans steps but in this flow, the ILD can be deposited last and therefore avoid damage during patterning.

To provide context, edge placement error of via, cut and plug patterning is problematic when feature sizes and pitches are scaled. State of the art solutions to address such problems involve either attempts to tighten edge placement error by improving scanner overlay and improving critical dimension (CD) control or attempts to use super-self-aligned integration approaches. By contrast, embodiments described herein involve implementation of a process that can achieve similar improvements in edge placement error margin without requiring improvements in lithographic tooling or super-self-alignment.

In accordance with an embodiment of the present disclosure, metal lines are fabricated in two separate operation sequences in order to double the amount of overlay margin for cuts/plugs and via patterning. In a first portion of an exemplary process flow, pitch division methods are used to pattern metal lines, plugs and then vias into an interlayer dielectric material. In a second portion of the exemplary process flow, trenches/via openings are filled with metal (e.g., dual damascene metallization) and then polished. Sacrificial hardmask layers are then removed in between the metal lines. The metal lines are then coated with a sacrificial dielectric material using, e.g., atomic layer deposition (ALD). In a third portion of the exemplary process flow, an isotropic spacer etch is performed to expose bottoms of the trenches. Using a plug patterning flow, dielectric material is added to the locations where metal lines ends should occur, and via etches are completed on the complementary metal lines. The metal from the first metal lines acts as an etch stop to prevent etching in these locations. In a fourth portion of the exemplary process flow, trenches are filled with metal and polished to expose the metal. After polish, sacrificial hardmask material is removed and, optionally, replaced with a dielectric material and then polished again to finish the metallization process. By tuning the deposition of the dielectric material, airgaps can be inserted as well. Additionally, embodiments may involve use of a sacrificial hardmask material instead of metal. The sacrificial hardmask can be removed and replaced with metal at the “second” metallization operation.

In an exemplary processing scheme,FIGS. 9A-9Lillustrate angled cross-sectional views of portions of integrated circuit layers representing various operations in a method involving pitch division patterning with increased overlay margin for back end of line (BEOL) interconnect fabrication, in accordance with an embodiment of the present disclosure.

Referring toFIG. 9A, a starting point structure900is provided as a beginning point for fabricating a new metallization layer. The starting point structure900includes a hardmask layer902disposed on a sacrificial layer904disposed on an inter-layer dielectric (ILD) layer906. The ILD layer may be disposed above a substrate and, in one embodiment, is disposed over an underlying metallization layer. In one embodiment, the hardmask layer902is a silicon nitride (SiN) or titanium nitride hardmask layer. In one embodiment, the sacrificial layer is a silicon layer such as a polycrystalline silicon layer or an amorphous silicon layer.

Referring toFIG. 9B, the hardmask layer902and the sacrificial layer904of the structure ofFIG. 9Bare patterned. The hardmask layer902and the sacrificial layer904are patterned to form patterned hardmask layer908and patterned sacrificial layer910, respectively. Patterned hardmask layer908and patterned sacrificial layer910include a pattern of first line openings912and line end regions914. In an embodiment, a silicon sacrificial layer is suitable for patterning to fine features using an anisotropic plasma etch process. In an embodiment, a lithographic resist mask exposure and etch process is used to form patterned hardmask layer908and patterned sacrificial layer910, with subsequent removal of the resist layer or stack. In an embodiment, the first line openings912have a grating type pattern, as is depicted inFIG. 9B. In an embodiment, a pitch division patterning scheme is used to form the pattern of first line openings912. Examples of suitable pitch division schemes are described in greater detail below. A subsequent line “cut” or plug preservation lithography process may then be used to define line end regions914.

FIG. 9Cillustrates the structure ofFIG. 9Bfollowing underlying via location patterning. Via openings916may be formed at select locations of the ILD layer906to form patterned ILD layer918. In an embodiment, vias are patterned using a self-aligned via process. The select locations are formed within regions of the ILD layer906exposed by the first line openings912. In an embodiment, a separate lithographic and etch process is used to form via openings916subsequent to the lithographic patterning process used to form first line openings912.

FIG. 9Dillustrates the structure ofFIG. 9Cfollowing a first metallization process. In an embodiment, a dual-damascene metallization process is used where vias and metal lines are filled at the same time. Interconnect lines920and conductive vias920are formed in the first line openings and the via openings916. In an embodiment, a metal fill process is performed to provide interconnect lines920and conductive vias920. In an embodiment, the metal fill process is performed using a metal deposition and subsequent planarization processing scheme, such as a chemical mechanical planarization (CMP) process. In the case that the patterned sacrificial hardmask layer910is composed substantially of silicon, a liner material may be deposited prior to forming a conductive fill layer, in order to inhibit silicidation of the patterned sacrificial hardmask layer910.

FIG. 9Eillustrates the structure ofFIG. 9Dfollowing exposure of the interconnect lines920. The patterned hardmask layer908and the patterned sacrificial layer910are removed to leave interconnect lines920exposed, with underlying conductive vias in the patterned ILD layer918. Line end openings924are revealed. Line end openings924provide breaks in the grating pattern of the interconnect lines920. In an embodiment, the patterned hardmask layer908and the patterned sacrificial layer910are removed using a selective wet etch process.

FIG. 9Fillustrates the structure ofFIG. 9Efollowing formation of a conformal patterning layer. A spacer material layer926is formed over and conformal with the grating pattern of the interconnect lines920. In an embodiment, atomic layer deposition (ALD) is used due to the fact that it is highly conformal and extremely accurate (e.g., control to the Angstrom level). It is to be appreciated that the line end openings924are, in an embodiment, too short to effectively disrupt the general grating pattern of the interconnect lines920with respect to formation of the conformal spacer material layer926. In one such embodiment, the line end openings924are filled with the spacer material layer926without disrupting the general grating pattern of the interconnect lines920. In an embodiment, the spacer material layer926is deposited using a chemical vapor deposition (CVD) or atomic layer deposition (ALD) process. In one embodiment, the spacer material layer926is a silicon layer such as a polycrystalline silicon layer or an amorphous silicon layer. In a specific such embodiment, a liner material is deposited on the interconnect lines920prior to forming a silicon spacer material layer, in order to inhibit silicidation of the spacer material layer926. In an embodiment, the line end cuts (plugs) are less than or equal to 2× the spacer thickness so that they are completely filled with the conformal dielectric material. If they are larger than 2× the thickness, seams may form and metal may short the lines together during subsequent processing.

FIG. 9Gillustrates the structure ofFIG. 9Ffollowing formation of spacer lines from the spacer material layer. In an embodiment, spacers928are formed along the sidewalls of interconnect lines920using an anisotropic plasma etching process. In one embodiment, the spacer material layer926remains in the line end openings924to form line end placeholder portions930for interconnect lines920.

FIG. 9Hillustrates the structure ofFIG. 9Gfollowing formation of a plug placeholder layer. A plug placeholder layer932is formed between spacers928of adjacent interconnect lines920. The plug placeholder layer932is initially formed in locations where a second set of interconnect lines will ultimately be formed. In an embodiment, the plug placeholder layer932is formed using a deposition and planarization process, confining the plug placeholder layer932between the spacers928.

FIG. 9Iillustrates the structure ofFIG. 9Hfollowing patterning of the plug placeholder layer. The plug placeholder layer932is patterned to retain plug placeholders934in select locations where line ends are ultimately formed. In an embodiment, a lithographic resist mask exposure and etch process is used to form plug placeholders934, with subsequent removal of the resist layer or stack.

FIG. 9Jillustrates the structure ofFIG. 9Ifollowing a second metallization process. Interconnect lines936are formed in the openings (second line openings) formed upon patterning of the plug placeholder layer932to form plug placeholders934. Additionally, although the separate processing operations are omitted from the figures, via openings, and ultimately conductive vias938, may be formed in select locations below the conductive lines936. Such a process results in a double patterned (two different via patterning operations) ILD layer940, as is depicted inFIG. 9J.

In an embodiment, a metal fill process is performed to provide interconnect lines936and conductive vias938. In an embodiment, the metal fill process is performed using a metal deposition and subsequent planarization processing scheme, such as a chemical mechanical planarization (CMP) process. In the case that the spacers928are composed substantially of silicon, a liner material may be deposited prior to forming a conductive fill layer, in order to inhibit silicidation of the spacers928.

It is to be appreciated that, in an embodiment, since interconnect lines936(and corresponding conductive vias938) are formed in a later process than the process used to fabricate interconnect lines920(and corresponding conductive vias922), the interconnect lines936can be fabricated using a different material than is used to fabricate the conductive lines920. In one such embodiment, a metallization layer ultimately includes conductive interconnects of alternating, differing first and second compositions.

FIG. 9Killustrates the structure ofFIG. 9Jfollowing exposure of the two sets of interconnect lines920and936. The spacers928, the line end placeholder portions930, and the plug placeholders934are removed to leave interconnect lines920and936exposed, with underlying conductive vias922and938, respectively, in the patterned ILD layer940. Line end openings942are revealed. Line end openings942provide breaks in the grating pattern of the interconnect lines920and in the grating pattern of the interconnect lines936. In an embodiment, the spacers928, the line end placeholder portions930, and the plug placeholders934are removed using a selective wet etch process.

In an embodiment, the structure ofFIG. 9Krepresents a final metallization structure having an air gap architecture. That is, since the interconnect lines920and936are ultimately exposed in the process described herein, an air gap architecture is enabled. In another embodiment, since the interconnect lines920and936are exposed at this stage in the process, there is an opportunity to remove sidewall portions of a diffusion barrier layer of the interconnect lines. For example, in one embodiment, removal of such a diffusion barrier layer physically thins the conductive features of the interconnect lines920and936. In another embodiment, resistance of such interconnect lines920and936is reduced upon removal of sidewall portions of such a diffusion barrier layer. As labeled inFIG. 9K, features sidewall portions960of interconnect lines920and936are exposed, while portions962beneath the lines are not. As such, in one embodiment, a diffusion barrier layer of interconnect lines920and936is removed from the sidewalls960of the interconnect lines920and936but not from regions962of the interconnect lines920and936. In a particular embodiment, removal of sidewall portions of such a diffusion barrier layer involves removal of a Ta and/or TaN layer.

Thus, with reference to operations9A-9K, in an embodiment, a method of fabricating a back end of line (BEOL) metallization layer includes forming a plurality of conductive lines920/936in a sacrificial material928formed above a substrate. Each of the plurality of conductive lines920/936includes a barrier layer formed along a bottom of and sidewalls a conductive fill layer. The sacrificial material928is then removed. The barrier layer is removed from the sidewalls of the conductive fill layer (e.g., at locations960). In one embodiment, removing the barrier layer from the sidewalls of the conductive fill layer includes removing a tantalum or tantalum nitride layer from sidewalls of a conductive fill layer including a material selected from the group consisting of Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au and alloys thereof.

FIG. 9Lillustrates the structure ofFIG. 9Kfollowing formation of a permanent ILD layer. Inter-layer dielectric (ILD) layer946/948is formed among the interconnect lines920and936. The ILD layer946/948includes portions946between interconnect lines920and936. The ILD layer946/948also includes line end (or dielectric plug) portions948between at locations of the line breaks of the interconnect lines920and936.

Referring again toFIG. 9L, in an embodiment, a semiconductor structure999includes a substrate (underlying ILD layer940of which is shown). A plurality of alternating first920and second936conductive line types is disposed along a same direction of a back end of line (BEOL) metallization layer disposed above the substrate. In one embodiment, as described in association withFIG. 9K, a total composition of the first conductive line type920is different from a total composition of the second conductive line type936. In a specific such embodiment, the total composition of the first conductive line type920is substantially composed of copper, and the total composition of the second conductive line type936is substantially composed of a material selected from the group consisting of Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au and alloys thereof, or vice versa. However, in another embodiment, a total composition of the first conductive line type920is the same as a total composition of the second conductive line type936.

In an embodiment, the lines of the first conductive line type920are spaced apart by a pitch, and the lines of the second conductive line type936are spaced apart by the same pitch. In one embodiment, the plurality of alternating first and second conductive line types is disposed in an inter-layer dielectric (ILD) layer946/948. In another embodiment, however, the lines of the plurality of alternating first and second conductive line types920/936are separated by an air gap, as described in association withFIG. 9K.

In an embodiment, the lines of the plurality of alternating first and second conductive line types920/936each include a barrier layer disposed along a bottom of and sidewalls of the line. In another embodiment, however, the lines of the plurality of alternating first and second conductive line types920/936each include a barrier layer disposed along a bottom962of the line but not along sidewalls960of the line, as was described in an embodiment ofFIG. 9K. In one embodiment, one or more of the lines of the plurality of alternating first and second conductive line types is connected to an underlying via922/938connected to an underlying metallization layer of the semiconductor structure. In an embodiment, one or more of the lines of the plurality of alternating first and second conductive line types920/936is interrupted by a dielectric plug948.

A resulting structure999such as described in association withFIG. 9L(or the air gap structure ofFIG. 9K) may subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure999ofFIG. 9L(or the structure ofFIG. 9K) may represent the final metal interconnect layer in an integrated circuit. It is to be appreciated that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed. It is also to be appreciated that the above examples have focused on metal line and plug or line end formation. However, in other embodiments, similar approaches may be used to form via openings in an ILD layer.

In accordance with one or more embodiments of the present disclosure, self-aligned DSA di-block or selective growth bottom-up approaches are described. One or more embodiments described herein are directed to self-aligned via and plug patterning. The self-aligned aspect of the processes described herein may be based on a directed self-assembly (DSA) mechanism, as described in greater detail below. However, it is to be appreciated that selective growth mechanisms may be employed in place of, or in combination with, DSA-based approaches. In an embodiment, processes described herein enable realization of self-aligned metallization for back-end of line feature fabrication. More specifically, one or more embodiments are directed to an approach that employs an underlying metal as a template to build the conductive vias and non-conductive spaces or interruptions between metals (referred to as “plugs”).

FIGS. 10A-10Millustrate portions of integrated circuit layers representing various operations in a method of self-aligned via and metal patterning, in accordance with an embodiment of the present disclosure. In each illustration at each described operation, plan views are shown on the left-hand side, and corresponding cross-sectional views are shown on the right-hand side. These views will be referred to herein as corresponding cross-sectional views and plan views.

FIG. 10Aillustrates a plan view and corresponding cross-sectional views of options for a previous layer metallization structure, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-section view option (a), a starting structure1000includes a pattern of metal lines1002and interlayer dielectric (ILD) lines1004. The starting structure1000may be patterned in a grating-like pattern with metal lines spaced at a constant pitch and having a constant width (e.g., for a DSA embodiment, but not necessarily needed for a directed selective growth embodiment), as is depicted inFIG. 10A. The pattern, for example, may be fabricated by a pitch halving or pitch quartering approach. Some of the lines may be associated with underlying vias, such as line1002′ shown as an example in the cross-sectional views.

Referring again toFIG. 10A, alternative options (b)-(f) address situations where an additional film is formed (e.g., deposited, grown, or left as an artifact remaining from a previous patterning process) on a surface of one of, or both of, the metal lines1002and interlayer dielectric lines1004. In example (b), an additional film1006is disposed on the interlayer dielectric lines1004. In example, (c), an additional film1008is disposed on the metal lines1002. In example, (d) an additional film1006is disposed on the interlayer dielectric lines1004, and an additional film1008is disposed on the metal lines1002. Furthermore, although the metal lines1002and the interlayer dielectric lines1004are depicted as co-planar in (a), in other embodiments, they are not co-planar. For example, in (e), the metal lines1002protrude above the interlayer dielectric lines1004. In example, (f), the metal lines1002are recessed below the interlayer dielectric lines1004.

Referring again to examples (b)-(d), an additional layer (e.g., layer1006or1008) can be used as a hardmask (HM) or protection layer or be used to enable a selective growth and/or self-assembly described below in association with subsequent processing operations. Such additional layers may also be used to protect the ILD lines from further processing. In addition, selectively depositing another material over the metal lines may be beneficial for similar reasons. Referring again to examples (e) and (f), it may also be possible to recess either the ILD lines or the metal lines with any combination of protective/HM materials on either or both surfaces. Overall, there exist numerous options at this stage for preparing ultimately underlying surfaces for a selective or directed self-assembly process.

FIG. 10Billustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 10Afollowing formation of interlayer dielectric (ILD) lines1010above the structure ofFIG. 10A, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (c) taken along axes a-a′ and c-c′, respectively, the ILD lines1010are formed in a grating structure perpendicular to the direction of underlying lines1004. In an embodiment, a blanket film of the material of lines1010is deposited by chemical vapor deposition or like techniques. In an embodiment, the blanket film is then patterned using lithography and etch processing which may involve, e.g., spacer-based-quadruple-patterning (SBQP) or pitch quartering. It is to be appreciated that the grating pattern of lines1010can be fabricated by numerous methods, including EUV and/or EBDW lithography, directed self-assembly, etc. As will be described in greater detail below, subsequent metal layer will thus be patterned in the orthogonal direction relative to the previous metal layer since the grating of lines1010is orthogonal to the direction of the underlying structure. In one embodiment, a single 193 nm lithography mask is used with alignment/registration to the previous metal layer1002(e.g., grating of lines1010aligns to the previous layer ‘plug’ pattern in X and to the previous metal grating in Y). Referring to cross-sectional structures (b) and (d), a hardmask1012may be formed on, or retained following pattering of, dielectric lines1010. The hardmask1012can be used to protect lines1010during subsequent patterning steps. As described in greater detail below, the formation of lines1010in a grating pattern exposes regions of the previous metal lines1002and previous ILD lines1004(or corresponding hardmask layers on1002/1004). The exposed regions correspond to all possible future via locations where metal is exposed. In one embodiment, the previous layer metal layer (e.g., lines1002) is protected, labeled, brushed, etc. at this point in the process flow.

FIG. 10Cillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 10Bfollowing selective differentiation all of the potential via locations from all of the plug locations, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a)-(d) taken along axes, a-a′, b-b′, c-c′ and d-d′, respectively, following formation of ILD lines1010, a surface modification layer1014is formed on exposed regions of the underlying ILD lines1004. In an embodiment, surface modification layer1014is a dielectric layer. In an embodiment, surface modification layer1014is formed by a selective bottom-up growth approach. In one such embodiment, the bottom-up growth approach involves a directed self-assembly (DSA) brush coat that has one polymer component which assembles preferentially on the underlying ILD lines1004or, alternatively, on the metal lines1002(or on a sacrificial layer deposited or grown on the underlying metal or ILD material).

FIG. 10Dillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 10Cfollowing differential polymer addition to the exposed portions of underlying metal and ILD lines ofFIG. 10C, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a)-(d) taken along axes, a-a′, b-b′, c-c′ and d-d′, respectively, directed self-assembly (DSA) or selective growth on exposed portions of the underlying metal/ILD1002/1004grating is used to form intervening lines1016with alternating polymers or alternating polymer components in between the ILD lines1010. For example, as shown, polymer1016A (or polymer component1016A) is formed on or above the exposed portions of interlayer dielectric (ILD) lines1004ofFIG. 10C, while polymer1016B (or polymer component1016B) is formed on or above the exposed portions of the metal lines1002ofFIG. 10C. Although polymer1016A is formed on or above the surface modification layer1014described in association withFIG. 10C(see cross-sectional views (b) and (d) ofFIG. 10D), it is to be appreciated that, in other embodiments, the surface modification layer1014can be omitted and the alternating polymers or alternating polymer components can instead be formed directly in the structure described in association withFIG. 10B.

Referring again toFIG. 10D, in an embodiment, once the surface of the underlying structure (e.g., structure1000ofFIG. 10A) has been prepared (e.g., such as the structure ofFIG. 10Bor the structure ofFIG. 10C) or is used directly, a 50-50 diblock copolymer, such as polystyrene-polymethyl methacrylate (PS-PMMA), is coated on the substrate and annealed to drive self-assembly, leading to the polymer1016A/polymer1016B layer1016ofFIG. 10D. In one such embodiment, with appropriate surface energy conditions, the block copolymers segregate based on the underlying material exposed between ILD lines1010. For example, in a specific embodiment, polystyrene aligns selectively to the exposed portions of underlying metal lines1002(or corresponding metal line cap or hardmask material). Meanwhile, the polymethyl methacrylate aligns selectively to the exposed portions of ILD lines1004(or corresponding metal line cap or hardmask material).

Thus, in an embodiment, the underlying metal and ILD grid, as exposed between ILD lines1010is recreated in the block co-polymer (BCP, i.e., polymer1016A/polymer1016B). This can particularly be so if the BCP pitch is commensurate with the underlying grating pitch. The polymer grid (polymer1016A/polymer1016B) is, in one embodiment, robust against certain small deviations from a well aligned grid. For example, if small plugs effectively place an oxide or like material where a well aligned grid would have metal, a well aligned polymer1016A/polymer1016B grid can still be achieved. However, since the ILD lines grating is, in one embodiment, an idealized grating structure, with no metal disruptions of the ILD backbone, it may be necessary to render the ILD surface neutral since both types of polymer (1016A and1016B) will, in such an instance, be exposed to ILD like material while only one type is exposed to metal.

In an embodiment, the thickness of the coated polymer (polymer1016A/polymer1016B) is approximately the same as, or slightly thicker than, the ultimate thickness of an ILD ultimately formed in its place. In an embodiment, as described in greater detail below, the polymer grid is formed not as an etch resist, but rather as scaffolding for ultimately growing a permanent ILD layer there around. As such, the thickness of the polymer1016(polymer1016A/polymer1016B) can be important since it may be used to define the ultimate thickness of a subsequently formed permanent ILD layer. That is, in one embodiment, the polymer grating shown inFIG. 10Dis eventually replaced with an ILD grating of roughly the same thickness.

In an embodiment, as mentioned above, the grid of polymer1016A/polymer1016B ofFIG. 10Dis a block copolymer. In one such embodiment, the block copolymer molecule is a polymeric molecule formed of a chain of covalently bonded monomers. In a block copolymer, there are at least two different types of monomers, and these different types of monomers are primarily included within different blocks or contiguous sequences of monomers. The illustrated block copolymer molecule includes a block of polymer1016A and a block of polymer1016B. In an embodiment, the block of polymer1016A includes predominantly a chain of covalently linked monomer A (e.g., A-A-A-A-A . . . ), whereas the block of polymer1016B includes predominantly a chain of covalently linked monomer B (e.g., B-B-B-B-B . . . ). The monomers A and B may represent any of the different types of monomers used in block copolymers known in the arts. By way of example, the monomer A may represent monomers to form polystyrene, and the monomer B may represent monomers to form poly(methyl methacrylate) (PMMA), although the scope of the disclosure is not so limited. In other embodiments, there may be more than two blocks. Moreover, in other embodiments, each of the blocks may include different types of monomers (e.g., each block may itself be a copolymer). In one embodiment, the block of polymer1016A and the block of polymer1016B are covalently bonded together. The block of polymer1016A and the block of polymer1016B may be of approximately equal length, or one block may be significantly longer than the other.

Typically, the blocks of block copolymers (e.g., the block of polymer1016A and the block of polymer1016B) may each have different chemical properties. As one example, one of the blocks may be relatively more hydrophobic (e.g., water repelling) and the other may be relatively more hydrophilic (water attracting). At least conceptually, one of the blocks may be relatively more similar to oil and the other block may be relatively more similar to water. Such differences in chemical properties between the different blocks of polymers, whether a hydrophilic-hydrophobic difference or otherwise, may cause the block copolymer molecules to self-assemble. For example, the self-assembly may be based on microphase separation of the polymer blocks. Conceptually, this may be similar to the phase separation of oil and water which are generally immiscible. Similarly, differences in hydrophilicity between the polymer blocks (e.g., one block is relatively hydrophobic and the other block is relatively hydrophilic), may cause a roughly analogous microphase separation where the different polymer blocks try to “separate” from each other due to chemical dislike for the other.

However, in an embodiment, since the polymer blocks are covalently bonded to one another, they cannot completely separate on a macroscopic scale. Rather, polymer blocks of a given type may tend to segregate or conglomerate with polymer blocks of the same type of other molecules in extremely small (e.g., nano-sized) regions or phases. The particular size and shape of the regions or microphases generally depends at least in part upon the relative lengths of the polymer blocks. In an embodiment, by way of example (as shown inFIG. 10D), in two block copolymers, if the blocks are approximately the same length, a grid like pattern of alternating polymer1016A lines and polymer1016B lines is generated. In another embodiment (not shown), in two block copolymers, if one of the blocks is longer than the other, but not too much longer than the other, columnar structures may formed. In the columnar structures, the block copolymer molecules may align with their shorter polymer blocks microphase separated into the interior of the columns and their longer polymer blocks extending away from the columns and surrounding the columns. For example, if the block of polymer1016A were longer than the block of polymer1016B, but not too much longer, columnar structures may formed in which many block copolymer molecules align with their shorter blocks of polymer1016B forming columnar structures surrounded by a phase having the longer blocks of polymer1016A. When this occurs in an area of sufficient size, a two-dimensional array of generally hexagonally-packed columnar structures may be formed.

In an embodiment, the polymer1016A/polymer1016B grating is first applied as an unassembled block copolymer layer portion that includes a block copolymer material applied, e.g., by brush or other coating process. The unassembled aspect refers to scenarios where, at the time of deposition, the block copolymer has not yet substantially phase separated and/or self-assembled to form nanostructures. In this unassembled form, the block polymer molecules are relatively highly randomized, with the different polymer blocks relatively highly randomly oriented and located, which is in contrast to the assembled block copolymer layer portion discussed in association with the resulting structure ofFIG. 10D. The unassembled block copolymer layer portion may be applied in a variety of different ways. By way of example, the block copolymer may be dissolved in a solvent and then spin coated over the surface. Alternatively, the unassembled block copolymer may be spray coated, dip coated, immersion coated, or otherwise coated or applied over the surface. Other ways of applying block copolymers, as well as other ways known in the arts for applying similar organic coatings, may potentially be used. Then, the unassembled layer may form an assembled block copolymer layer portion, e.g., by microphase separation and/or self-assembly of the unassembled block copolymer layer portion. The microphase separation and/or self-assembly occurs through rearrangement and/or repositioning of the block copolymer molecules, and in particular to rearrangement and/or repositioning of the different polymer blocks of the block copolymer molecules.

In one such embodiment, an annealing treatment may be applied to the unassembled block copolymer in order to initiate, accelerate, increase the quality of, or otherwise promote microphase separation and/or self-assembly. In some embodiments, the annealing treatment may include a treatment that is operable to increase a temperature of the block copolymer. One example of such a treatment is baking the layer, heating the layer in an oven or under a thermal lamp, applying infrared radiation to the layer, or otherwise applying heat to or increasing the temperature of the layer. The desired temperature increase will generally be sufficient to significantly accelerate the rate of microphase separation and/or self-assembly of the block polymer without damaging the block copolymer or any other important materials or structures of the integrated circuit substrate. Commonly, the heating may range between about 50° C. to about 300° C., or between about 75° C. to about 250° C., but not exceeding thermal degradation limits of the block copolymer or integrated circuit substrate. The heating or annealing may help to provide energy to the block copolymer molecules to make them more mobile/flexible in order to increase the rate of the microphase separation and/or improve the quality of the microphase separation. Such microphase separation or rearrangement/repositioning of the block copolymer molecules may lead to self-assembly to form extremely small (e.g., nano-scale) structures. The self-assembly may occur under the influence of surface energy, molecular affinities, and other surface-related and chemical-related forces.

In any case, in some embodiments, self-assembly of block copolymers, whether based on hydrophobic-hydrophilic differences or otherwise, may be used to form extremely small periodic structures (e.g., precisely spaced nano-scale structures or lines). In some embodiments, they may be used to form nano-scale lines or other nano-scale structures that can ultimately be used to form via and openings. In some embodiments, directed self-assembly of block copolymers may be used to form vias that are self-aligned with interconnects, as described in greater detail below.

Referring again toFIG. 10D, in an embodiment, for a DSA process, in addition to direction from the underlying ILD/metal1004/1002surfaces the growth process can be affected by the sidewalls of the material of ILD lines1010. As such, in one embodiment, DSA is controlled through graphoepitaxy (from the sidewalls of lines1010) and chemoepitaxy (from the underlying exposed surface characteristics). Constraining the DSA process both physically and chemically can significantly aid the process from a defectivity standpoint. The resulting polymers1016A/1016B have fewer degrees of freedom and are fully constrained in all directions through chemical (e.g., underlying ILD or metal lines, or surface modifications made thereto by, for example, a brush approach) and physical (e.g., from the trenches formed between the ILD lines1010).

In an alternative embodiment, a selective growth process is used in place of a DSA approach.FIG. 10Eillustrates a cross-sectional view of the structure ofFIG. 10Bfollowing selective the exposed portions of underlying metal and ILD lines, in accordance with another embodiment of the present disclosure. Referring toFIG. 10E, a first material type1090is grown above exposed portions of underlying ILD lines1004. A second, different, material type1092is grown above exposed portions of underlying metal lines1002. In an embodiment, the selective growth is achieved by a dep-etch-dep-etch approach for each of the first and second materials, resulting in a plurality of layers of each of the materials, as depicted inFIG. 10E. Such an approach may be favorable versus conventional selective growth techniques which can form “mushroom-top” shaped films. The mushroom topping film growth tendency can be reduced through an alternating deposition/etch/deposition (dep-etch-dep-etch) approach. In another embodiment, a film is deposited selectively over the metal followed by a different film selectively over the ILD (or vice versa) and repeated numerous times creating a sandwich-like stack. In another embodiment, both materials are grown simultaneously in a reaction chamber (e.g., by a CVD style process) that grows selectively on each exposed region of the underlying substrate.

FIG. 10Fillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 10Dfollowing removal of one species of polymer, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a)-(d) taken along axes, a-a′, b-b′, c-c′ and d-d′, respectively, polymer or polymer portion1016A is removed to re-expose the ILD lines1004(or hardmask or cap layers formed on the ILD lines1004), while polymer or polymer portion1016B is retained above the metal lines1002. In an embodiment, a deep ultra-violet (DUV) flood expose followed by a wet etch or a selective dry etch is used to selectively remove polymer1016A. It is to be appreciated that, instead of first removal of the polymer from the ILD lines1004(as depicted), removal from the metal lines1002may instead be first performed. Alternatively, a dielectric film is selectively grown over the region, and a mixed scaffolding is not used.

FIG. 10Gillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 10Ffollowing formation of an ILD material in the locations opened upon removal of the one species of polymer, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a)-(d) taken along axes, a-a′, b-b′, c-c′ and d-d′, respectively, the exposed regions of underlying ILD lines1004are filled with a permanent interlayer dielectric (ILD) layer1018. As such, the open spaces between all possible via positions are filled with an ILD layer1018includes a hardmask layer1020disposed thereon, as depicted in the plan view and in the cross-sectional views (b) and (d) ofFIG. 10G. It is to be appreciated that the material of ILD layer1018need not be the same material as ILD lines1010. In an embodiment, the ILD layer1018is formed by a deposition and polish process. In the case where ILD layer1018is formed with an accompanying hardmask layer1020, a special ILD fill material may be used (e.g., polymer encapsulated nanoparticles of ILD that fills holes/trenches). In such a case, a polish operation may not be necessary.

Referring again toFIG. 10G, in an embodiment, the resulting structure includes a uniform ILD structure (ILD lines1010+ILD layer1018), and the locations of all possible plugs are covered in hardmask1020and all possible vias are in areas of polymer1016B. In one such embodiment, ILD lines1010and ILD layer1018are composed of a same material. In another such embodiment, ILD lines1010and ILD layer1018are composed of different ILD materials. In either case, in a specific embodiment, a distinction such as a seam between the materials of ILD lines1010and ILD layer1018may be observed in the final structure. Exemplary seams1099are shown inFIG. 10Gfor illustrative purposes.

FIG. 10Hillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 10Gfollowing via patterning, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a)-(d) taken along axes, a-a′, b-b′, c-c′ and d-d′, respectively, via locations1022A,1022B and1022C are opened by removal of polymer1016B in select locations. In an embodiment, selective via location formation is accomplished by using a lithographic technique. In one such embodiment, polymer1016B is globally removed with an ash and refilled with photoresist. The photoresist may be highly sensitive and have a large acid diffusion and aggressive deprotection or crosslinking (depending on resist tone) because the latent image is confined in both directions by ILD (e.g., by ILD lines1010and ILD layer1018). The resist serves as a digital switch to turn “on” or “off” depending whether a via is required in a particular location or not. Ideally, the photoresist can be used to fill the holes only, without spilling over. In an embodiment, the via locations1022A,1022B and1022C are fully confined with the process such that line edge or width roughness (LWR) and line collapse and/or reflection is mitigated if not eliminated. In an embodiment, low doses are used with EUV/EBDW and increase runrate significantly. In one embodiment, an additional advantage with the use of EBDW is that only a single shot type/size that can increase runrate by significantly reducing the number of apertures required as well as lowering the dose that needs to be delivered. In a case that 193 nm immersion lithography is used, in an embodiment, the process flow confines the via locations in both directions such the size of the via that actually is patterned is twice the size of the actual via on the wafer (e.g., assuming 1:1 line/space patterns). Alternatively, the via locations can be selected in the reverse tone where the vias that need to be retained are protected with photoresist and the remaining sites are removed and later filled with ILD. Such an approach can allow a single metal fill/polish process at the end of the patterning flow rather than two separate metal deposition steps.

FIG. 10Iillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 10Hfollowing via formation, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a)-(d) taken along axes, a-a′, b-b′, c-c′ and d-d′, respectively, via locations1022A,1022B and1022C are filled with metal to form vias1024A,1024B and1024C, respectively. In an embodiment, via locations1022A,1022B and1022C are filled with excess metal, and a subsequent polish operation is performed. In another embodiment, however, via locations1022A,1022B and1022C are filled without metal overfilling and the polishing operation is omitted. It is to be appreciated that the via fill illustrated inFIG. 10Imay be skipped in a reverse tone via selection approach.

FIG. 10Jillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 10Ifollowing removal of the second species of polymer and replacement with an ILD material, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a)-(d) taken along axes, a-a′, b-b′, c-c′ and d-d′, respectively, remaining polymer or polymer portion1016B (e.g., where vias locations have not been selected) is removed to re-expose the metal lines1002. Subsequently, an ILD layer1026is formed in the locations where the remaining polymer or polymer portion1016B was removed, as depicted inFIG. 10J.

Referring again toFIG. 10J, in an embodiment, the resulting structure includes a uniform ILD structure (ILD lines1010+ILD layer1018+ILD layer1026), and the locations of all possible plugs are covered in hardmask1020. In one such embodiment, ILD lines1010, ILD layer1018and ILD layer1026are composed of a same material. In another such embodiment, two of ILD lines1010, ILD layer1018and ILD layer1026are composed of a same material and the third is composed of a different ILD material. In yet another such embodiment, all of ILD lines1010, ILD layer1018and ILD layer1026are composed of a different ILD material with respect to one another. In any case, in a specific embodiment, a distinction such as a seam between the materials of ILD lines1010and ILD layer1026may be observed in the final structure. Exemplary seams1097are shown inFIG. 10Jfor illustrative purposes. Likewise, a distinction such as a seam between the materials of ILD layer1018and ILD layer1026may be observed in the final structure. Exemplary seams1098are shown inFIG. 10Jfor illustrative purposes.

FIG. 10Killustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 10Jfollowing patterning of a resist or mask in selected plug locations, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes, a-a′ and b-b′, respectively, plug positions1028A,1028B and1028C are preserved by forming a mask or resist layer over those locations. Such preservation patterning may be referred to as metal end-to-end lithographic patterning, wherein plug positions are determined where breaks in subsequently formed metal lines are required. It is to be appreciated that since the plug locations can only be in those locations where ILD layer1018/hardmask1020are positioned, plugs can occur over the previous layer ILD lines1004. In an embodiment, the patterning is achieved by using a lithography operation (e.g., EUV, EBDW or immersion 193 nm). In an embodiment, the process illustrated inFIG. 10K, demonstrates use of a positive tone patterning process where the regions where spaces between metal need to occur are preserved. It is to be appreciated that, in another embodiment, it is also possible to open holes instead and reverse the tone of the process.

FIG. 10Lillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 10Kfollowing hardmask removal and ILD layer recessing, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes, a-a′ and b-b′, respectively, hardmask1020is removed and ILD layer1018and ILD layer1026are recessed to form recessed ILD layer1018′ and recessed ILD layer1026′, respectively, by etching of these layers below their original uppermost surfaces. It is to be appreciated that the recessing of ILD layer1018and ILD layer1026is performed without etching or recessing ILD lines1010. The selectivity may be achieved by use of a hardmask layer1012on the ILD lines (as depicted in cross-sectional views (a) and (b)). Alternatively, in a case that the ILD lines1010are composed of an ILD material different from the material of ILD layer1018and ILD layer1026, a selective etch may be used even in the absence of a hardmask1012. The recessing of ILD layer1018and ILD layer1026is to provide locations for the second level of metal lines, as isolated by ILD lines1010, as described below. The extent or depth of the recess is, in one embodiment, selected based on the desired ultimate thickness of the metal lines formed thereon. It is to be appreciated that the ILD layer1018in the plug locations1028A,1028B and1028C is not recessed.

FIG. 10Millustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 10Lfollowing metal line formation, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a), (b) and (c) taken along axes, a-a′, b-b′ and c-c′, respectively, metal for forming metal interconnect lines is formed conformally above the structure ofFIG. 10L. The metal is then planarized, e.g., by CMP, to provide metal lines1030, which are confined to locations above recessed ILD layer1018′ and recessed ILD layer1026′. The metal lines1030are coupled with underlying metal lines1002through the predetermined via locations1024A,1024B and1024C (1024B is shown in cross-sectional view (c); note that for illustrative purposes, another via1032is depicted directly adjacent plug1028B in cross-sectional view (b) even though this is inconsistent with the previous figures). The metal lines1030are isolated from one another by ILD lines1010and are disrupted or broken-up by the preserved plugs1028A,1028B and1028C. Any hardmask remaining on the plug locations and/or on the ILD lines1010may be removed at this portion of the process flow, as depicted inFIG. 10M. The metal (e.g., copper and associated barrier and seed layers) deposition and planarization process to form metal lines1030may be that typically used for standard back end of line (BEOL) single or dual damascene processing. In an embodiment, in subsequent fabrication operations, the ILD lines1010may be removed to provide air gaps between the resulting metal lines1030.

The structure ofFIG. 10Mmay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 10Mmay represent the final metal interconnect layer in an integrated circuit. It is to be appreciated that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed. Furthermore, although the above process flow focused on applications of directed self-assembly (DSA), selective growth processes may be used instead in one or more locations of the process flow. In any case, the resulting structures enable fabrication of vias that are directly centered on underlying metal lines. That is, the vias may be wider than, narrower than, or the same thickness as the underlying metal lines, e.g., due to non-perfect selective etch processing. Nonetheless, in an embodiment, the centers of the vias are directly aligned (match up) with the centers of the metal lines. As such, in an embodiment, offset due to conventional lithograph/dual damascene patterning that must otherwise be tolerated, is not a factor for the resulting structures described herein.

One or more embodiments described herein are directed to previous layer self-aligned via and plug patterning. The self-aligned aspect of the processes described herein may be based on a directed self-assembly (DSA) mechanism, as described in greater detail below. However, it is to be appreciated that selective growth mechanisms may be employed in place of, or in combination with, DSA-based approaches. In an embodiment, processes described herein enable realization of self-aligned metallization for back-end of line feature fabrication.

FIGS. 11A-11Millustrate portions of integrated circuit layers representing various operations in a method of self-aligned via and metal patterning, in accordance with an embodiment of the present disclosure. In each illustration at each described operation, plan views are shown on the left-hand side, and corresponding cross-sectional views are shown on the right-hand side. These views will be referred to herein as corresponding cross-sectional views and plan views.

FIG. 11Aillustrates a plan view and corresponding cross-sectional views of options for a previous layer metallization structure, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-section view option (a), a starting structure1100includes a pattern of metal lines1102and interlayer dielectric (ILD) lines1104. The starting structure1100may be patterned in a grating-like pattern with metal lines spaced at a constant pitch and having a constant width, as is depicted inFIG. 11Aif self-assembling materials are being used. If a directed selective growth technique is used, then the underlying pattern does not have to be a single pitch or width. The pattern, for example, may be fabricated by a pitch halving or pitch quartering approach. Some of the lines may be associated with underlying vias, such as line1102′ shown as an example in the cross-sectional views.

Referring again toFIG. 11A, alternative options (b)-(f) address situations where an additional film is formed (e.g., deposited, grown, or left as an artifact remaining from a previous patterning process) on a surface of one of, or both of, the metal lines1102and interlayer dielectric lines1104. In example (b), an additional film1106is disposed on the interlayer dielectric lines1104. In example, (c), an additional film1108is disposed on the metal lines1102. In example, (d) an additional film1106is disposed on the interlayer dielectric lines1104, and an additional film1108is disposed on the metal lines1102. Furthermore, although the metal lines1102and the interlayer dielectric lines1104are depicted as co-planar in (a), in other embodiments, they are not co-planar. For example, in (e), the metal lines1102protrude above the interlayer dielectric lines1104. In example, (f), the metal lines1102are recessed below the interlayer dielectric lines1104.

Referring again to examples (b)-(d), an additional layer (e.g., layer1106or1108) can be used as a hardmask (HM) or protection layer or be used to enable a selective growth and/or self-assembly described below in association with subsequent processing operations. Such additional layers may also be used to protect the ILD lines from further processing. In addition, selectively depositing another material over the metal lines may be beneficial for similar reasons. Referring again to examples (e) and (f), it may also be possible to recess either the ILD lines or the metal lines with any combination of protective/HM materials on either or both surfaces. Overall, there exist numerous options at this stage for preparing ultimately underlying surfaces for a selective or directed self-assembly process.

FIG. 11Billustrates a plan view and corresponding cross-sectional views of options for directed self-assembly (DSA) growth on an underlying metal/ILD grating (e.g., on a structure such as shown inFIG. 11A), in accordance with an embodiment of the present disclosure. Referring to the plan view, the structure1110includes a layer with alternating polymers or alternating polymer components. For example, as shown, Polymer A (or polymer component A) is formed on or above the interlayer dielectric (ILD) lines1104ofFIG. 11A, while Polymer B (or polymer component B) is formed on or above the metal lines1102ofFIG. 11A. Referring to the cross-sectional views, in (a) Polymer A (or polymer component A) is formed on the ILD lines1104, and Polymer B (or polymer component B) is formed on the metal lines1102. In (b), Polymer A (or polymer component A) is formed on an additional film1106formed on the ILD lines1104, while Polymer B (or polymer component B) is formed on the metal lines1102. In (c), Polymer A (or polymer component A) is formed on the ILD lines1104, while Polymer B (or polymer component B) is formed on an additional film1108formed on the metal lines1102. In (d), Polymer A (or polymer component A) is formed on an additional film1106formed on the ILD lines1104, and Polymer B (or polymer component B) is formed on an additional film1108formed on the metal lines1102.

Referring again toFIG. 11B, in an embodiment, once the surface of the underlying structure (e.g., structure1100ofFIG. 11A) has been prepared, a 50-50 diblock copolymer, such as polystyrene-polymethyl methacrylate (PS-PMMA), is coated on the substrate and annealed to drive self-assembly, leading to the Polymer A/Polymer B layer of structure1110ofFIG. 11B. In one such embodiment, with appropriate surface energy conditions, the block copolymers segregate based on the underlying material of structure1100. For example, in a specific embodiment, polystyrene aligns selectively to the underlying metal lines1102(or corresponding metal line cap or hardmask material). Meanwhile, the polymethyl methacrylate aligns selectively to the ILD lines1104(or corresponding metal line cap or hardmask material).

Thus, in an embodiment, the underlying metal and ILD grid is recreated in the block co-polymer (BCP, i.e., Polymer A/Polymer B). This can particularly be so if the BCP pitch is commensurate with the underlying grating pitch. The polymer grid (Polymer A/Polymer B) is, in one embodiment, robust against certain small deviations from a highly well-aligned grid. For example, if small plugs effectively place an oxide or like material where a highly well-aligned grid would have metal, a highly well-aligned Polymer A/Polymer B grid can still be achieved. However, since the ILD lines grating is, in one embodiment, an idealized grating structure, with no metal disruptions of the ILD backbone, it may be necessary to render the ILD surface neutral since both types of polymer (A and B) will, in such an instance, be exposed to ILD like material while only one type is exposed to metal.

In an embodiment, the thickness of the coated polymer (Polymer A/B) is approximately the same as, or slightly thicker than, the ultimate thickness of an ILD ultimately formed in its place. In an embodiment, as described in greater detail below, the polymer grid is formed not as an etch resist, but rather as scaffolding for ultimately growing a permanent ILD layer there around. As such, the thickness of the polymer (A/B) can be important since it may be used to define the ultimate thickness of a subsequently formed permanent ILD layer. That is, in one embodiment, the polymer grating shown inFIG. 11Bis eventually replaced with an ILD grating of roughly the same thickness.

In an embodiment, as mentioned above, the grid of Polymer A/Polymer B ofFIG. 2is a block copolymer. In one such embodiment, the block copolymer molecule is one such as described above in association withFIG. 10D. In an embodiment, by way of a first example (as shown inFIG. 11B), in two block copolymers, if the blocks are approximately the same length, a grid like pattern of alternating Polymer A lines and Polymer B lines is generated. In another embodiment, by way of a second example (not shown), in two block copolymers, if one of the blocks is longer than the other, but not too much longer than the other, vertical columnar structures may be formed. In the columnar structures, the block copolymer molecules may align with their shorter polymer blocks microphase separated into the interior of the columns and their longer polymer blocks extending away from the columns and surrounding the columns. For example, if the block of Polymer A were longer than the block of Polymer B, but not too much longer, columnar structures may formed in which many block copolymer molecules align with their shorter blocks of Polymer B forming columnar structures surrounded by a phase having the longer blocks of Polymer A. When this occurs in an area of sufficient size, a two-dimensional array of generally hexagonally-packed columnar structures may be formed.

In an embodiment, the Polymer A/Polymer B grating is first applied as an unassembled block copolymer layer portion that includes a block copolymer material applied, e.g., by brush or other coating process, as described above in association withFIG. 10D. In such embodiment, an annealing treatment is applied to an unassembled block copolymer in order to initiate, accelerate, increase the quality of, or otherwise promote microphase separation and/or self-assembly, as described above in association withFIG. 10D.

FIG. 11Cillustrates a plan view and corresponding cross-sectional view of the structure ofFIG. 11Bfollowing removal of one species of polymer, in accordance with an embodiment of the present disclosure. Referring toFIG. 11C, Polymer B is removed to re-expose the metal lines1102(or hardmask or cap layers formed on the metal lines1102), while Polymer A is retained in the ILD lines1104, forming structure1112. In an embodiment, a deep ultra-violet (DUV) flood expose followed by a wet etch or a selective dry etch is used to selectively remove Polymer B. It is to be appreciated that, instead of first removal of the polymer from the metal lines1102(as depicted), removal from the ILD lines may instead be first performed.

FIG. 11Dillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 11Cfollowing formation of a sacrificial material layer over the metal lines1102, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional view (b), structure1114includes a Sacrificial B layer formed above or on the metal lines1102and between the Polymer A lines which are above or on the ILD lines1104. In an embodiment, referring to cross-sectional view (a), a low temperature deposition fills trenches between Polymer A lines, e.g., with an oxide (e.g., TiOx) or other sacrificial material as a conformal layer1116. The conformal layer1116is then confined to regions above metal lines1102by a dry etch or chemical mechanical planarization (CMP) process. The resulting layer is referred to herein as Sacrificial B, since in some embodiments the material is ultimately replaced with a permanent ILD material. However, in other embodiments, it is to be appreciated that a permanent ILD material may instead be formed at this stage. In the case that a sacrificial material is used, in an embodiment, the sacrificial material has the requisite deposition properties, thermal stability, and etch selectivity to other materials used in the process.

FIG. 11Eillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 11Dfollowing replacement of Polymer A with a permanent interlayer dielectric (ILD) material, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional view (c), structure1118includes permanent interlayer dielectric (ILD) lines1120on or above the ILD lines1104and between the Sacrificial B material lines. In an embodiment, as depicted in cross-sectional view (a), the Polymer A lines are removed. Then, referring to cross-sectional view (b), an ILD material layer1119is formed conformally over the resulting structure. The conformal layer1119is then confined to regions above the ILD lines1104by a dry etch or chemical mechanical planarization (CMP) process. In an embodiment, the structure1118effectively replaces the polymer (A/B) grating ofFIG. 11Bwith a very thick material grating (e.g., permanent ILD1120and Sacrificial B) commensurate with the underlying metal grating and aligned with the underlying grating. The two different materials may be used to ultimately define possible locations for plugs and vias, as described in greater detail below.

FIG. 11Fillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 11Efollowing selective hardmask formation on the permanent ILD lines, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional view (c), structure1122includes a hardmask layer1124formed on the permanent interlayer dielectric (ILD) lines1120. In one embodiment, referring to cross-sectional view (c), a selective growth process is used to form hardmask layer1124as confined to the surfaces of the permanent ILD lines1120. In another embodiment, a conformal material layer1123is first formed (cross-sectional view (a)) on a structure having recessed permanent ILD lines1120. The conformal layer1123is then subjected to a timed etch and or CMP process to form hardmask layer1124(cross-sectional view (b)). In the latter case, the ILD lines1120are recessed relative to the Sacrificial B material and then a non-conformal (planarizing) hardmask1123is deposited on the resulting grating. The material1123is thinner on Sacrificial B lines than on the recessed ILD lines1120such that a timed etch of the hardmask or a polish operation removes the material1123selectively from the Sacrificial B material.

FIG. 11Gillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 11Ffollowing removal of Sacrificial B lines and replacement with permanent ILD lines1128, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional view (c), structure1126includes permanent ILD lines1128in place of the Sacrificial B lines ofFIG. 11F, i.e., above and in alignment with the metal lines1102. In an embodiment, the Sacrificial B material is removed (cross-sectional view (a)) and replaced with permanent ILD lines1128(cross-sectional view (c)), e.g., by deposition of a conformal layer and subsequent timed etch or CMP processing (cross-sectional view (b)). In an embodiment, the resulting structure1126includes a uniform ILD material (permanent ILD lines1120+permanent ILD lines1128) where the locations of all possible plugs are covered in hardmask1124and all possible vias are in areas of exposed permanent ILD lines1128. In one such embodiment, permanent ILD lines1120and permanent ILD lines1128are composed of a same material. In another such embodiment, permanent ILD lines1120and permanent ILD lines1128are composed of different ILD materials. In either case, in a specific embodiment, a distinction such as a seam between the materials of permanent ILD lines1120and permanent ILD lines1128may be observed in the final structure1126. Exemplary seams1199are shown inFIG. 11Ffor illustrative purposes.

FIG. 11Hillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 11Gfollowing trench formation (e.g., grating definition), in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a)-(d) taken along axes, a-a′, b-b′, c-c′ and d-d′, respectively, a grating in structure1130for ultimately defining regions between a pattern of metal lines is defined by forming trenches1132in the structure ofFIG. 11G, perpendicular to the grating ofFIG. 11G. In an embodiment, the trenches1132are formed by patterning and etching a grating pattern into the sacrificial grating of earlier structures. In one embodiment, a grid is formed, effectively, defining the location of all spaces between ultimately formed metal lines along with all plugs and vias simultaneously. In an embodiment, the trenches1132reveal portions of underlying ILD lines1104and metal lines1102.

FIG. 11Iillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 11Hfollowing formation of a sacrificial material grating in the trenches ofFIG. 11H, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a)-(d) taken along axes, a-a′, b-b′, c-c′ and d-d′, respectively, a material layer1134, which is an interlayer dielectric layer or sacrificial layer is formed in the trenches1132of the structure ofFIG. 11H. In an embodiment, the material layer1134is formed by conformal deposition and subsequent timed etch or CMP with permanent ILD material or a sacrificial layer (e.g., which can be later removed if an air gap is to be fabricated). In the former case, the material layer1134ultimately becomes ILD material between subsequently formed parallel metal lines on a same metal layer. In the latter case, the material may be referred to as Sacrificial C material, as depicted. In one embodiment, material layer1134has a high etch selectivity to other ILD material and to the hardmask layer1128.

FIG. 11Jillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 11Ifollowing formation and patterning of a mask and subsequent etching of via locations, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes, a-a′ and b-b′, respectively, a mask1136is formed on the structure ofFIG. 11I. The mask is patterned, e.g., by a lithographic process, to have openings1137formed therein. In an embodiment, the openings are determined based on desired via patterning. That is, at this stage, all possible vias and plugs (e.g., as placeholders) have been patterned and are self-aligned to the ultimate metal layers above and below. Here, a subset of the vias and plug locations is selected for preservation, as are locations for etching metal line positions. In one embodiment, an ArF or EUV or ebeam resist is used to cut or select the vias to be etched, i.e., at locations of the exposed portions of metal lines1102. It is to be appreciated that the hardmask1124and the material layer1134act as the actual etch masks which determine the shape and position of the vias. The mask1136merely serves to block the remaining vias from being etched. As such, tolerance on opening1137size is relaxed since the surrounding materials (e.g., hardmask1124and material layer1134) of the selected via locations (i.e., the portion of openings1137directly above the exposed portions of the metal lines1102) are resistant to the etch process used to remove the ILD line1128above the selected portions of the metal lines1102for ultimate via fabrication. In one embodiment, the mask1136is composed of a topographic masking portion1136C, an anti-reflective coating (ARC) layer1136B, and a photoresist layer1136A. In a particular such embodiment, the topographic masking portion136C is a carbon hardmask (CHM) layer and the anti-reflective coating layer136B is a silicon ARC layer.

FIG. 11Killustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 11Jfollowing mask and hardmask removal and subsequent plug patterning and etch, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes, a-a′ and b-b′, respectively, the mask1136shown inFIG. 11Jis removed following via location patterning. Subsequently, a second mask1138is formed and patterned to cover selected plug locations. Specifically, in an embodiment, and as depicted inFIG. 11K, portions of hardmask1124are preserved in locations where plugs will ultimately be formed. That is, at this stage, all possible plugs in the form of hardmask plugs exist. The patterning operation ofFIG. 11Kserves to remove all hardmask1124portions except those selected for plug preservation. The patterning effectively exposes a substantial portion of ILD lines1120and1128, e.g., as a unified dielectric layer.

FIG. 11Lillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 11Kfollowing mask removal and metal line trench etch, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes, a-a′ and b-b′, respectively, the mask1138shown inFIG. 11Kis removed following via location patterning. Subsequently, a partial etch of the exposed portions of ILD lines1120and1128is performed to provide recessed ILD lines1120′ and1128′. The extent of recess may be based on a timed etch process, as targeted to a depth of a desired metal line thickness. The portions of ILD lines1120protected by the preserved hardmask1124portions are not recessed by the etch, as depicted inFIG. 11L. Additionally, the material layer1134(which may be a sacrificial material or a permanent ILD material) is also not etched or recessed. It is to be appreciated that no lithography operation is needed for the process illustrated byFIG. 11Lsince the vias locations (at exposed portions of metal lines1102) have already been etched and the plugs (at locations where hardmask1124was preserved).

FIG. 11Millustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 11Lfollowing metal line deposition and polish, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes, a-a′ and b-b′, respectively, metal for forming metal interconnect lines is formed conformally above the structure ofFIG. 11L. The metal is then planarized, e.g., by CMP, to provide metal lines1140. The metal lines are coupled with underlying metal lines through the predetermined via locations, and are isolated by the preserved plugs1142and1144. The metal (e.g., copper and associated barrier and seed layers) deposition and planarization process may be that of standard BEOL dual damascene processing. It is to be appreciated that, in subsequent fabrication operations, the material layer lines1134may be removed to provide air gaps between the resulting metal lines1140.

The structure ofFIG. 11Mmay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 11Mmay represent the final metal interconnect layer in an integrated circuit. It is to be appreciated that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed. Furthermore, although the above process flow focused on applications of directed self-assembly (DSA), selective growth processes may be used instead in one or more locations of the process flow. In any case, the resulting structures enable fabrication of vias that are directly centered on underlying metal lines. That is, the vias may be wider than, narrower than, or the same thickness as the underlying metal lines, e.g., due to non-perfect selective etch processing. Nonetheless, in an embodiment, the centers of the vias are directly aligned (match up) with the centers of the metal lines. As such, in an embodiment, offset due to conventional lithograph/dual damascene patterning that must otherwise be tolerated, is not a factor for the resulting structures described herein.

In accordance with an embodiment of the present disclosure, self-aligned DSA tri-block bottom-up approaches are described. One or more embodiments described herein are directed to triblock copolymers for self-aligning vias or contacts. Through the use of more advanced block copolymers and a directed self-assembly strategy, alignment to an underlying tight metal layer can be achieved. Embodiments described herein may be implemented to improve cost, scalability, pattern placement error, and variability.

In general, one or more embodiments described herein involves the use of the three phases of a triblock copolymer material to effect phase separation into “self-aligned photobuckets,” e.g., the use of a self-aligning triblock copolymer to generate aligned photobuckets is described. Additional embodiments directed at the fabrication and use of photobuckets is described in greater detail below in embodiments beyond the present embodiments ofFIGS. 12A-12K. It is also to be appreciated, however, that embodiments are not limited to the concept of photobuckets, but have far reaching applications to structures having pre-formed features fabricated using bottom-up and/or directed self-assembly (DSA) approach.

FIGS. 12A-12Cillustrate angled cross-sectional views representing various operations in a method using triblock copolymers for forming self-aligning vias or contacts for back end of line (BEOL) interconnects, in accordance with an embodiment of the present disclosure.

Referring toFIG. 12A, a semiconductor structure layer1200has a grating pattern of alternating metal lines1202and interlayer dielectric (ILD) lines1204. The structure1200may be treated with a first molecular brush operation (i) with first molecular species1206. The structure1200may also be treated with a second molecular brush operations (ii) with second molecular species1208. It is to be appreciated that the order of operations (i) and (ii) may be reversed, or may even be performed at substantially the same time.

Referring toFIG. 12B, the molecular brush operations may be performed to alter or provide a derivative surface for the alternating metal lines1202and ILD lines1204. For example, the surface of metal lines1202may be treated to have an A/B surface1210on metal lines1202. The surface of ILD lines1204may be treated to have a C surface1212on ILD lines1204.

Referring toFIG. 12C, the structure ofFIG. 12Bmay be treated with a treatment operation (iii) which involves application of a triblock block copolymer (triblock BCP)1214, and possible subsequent segregating treatment, to form a segregated structure1220. Segregated structure1220includes first regions1222of a segregated triblock BCP above the ILD lines1204. Alternating second regions1224and third regions1226of the segregated triblock BCP are above the metal lines1202. The ultimate arrangement of the three blocks of the triblock copolymer1214is based on chemo-epitaxy since only an underlying pattern (and not a co-planar pattern, as is used in grapho-epitaxy) is used to direct the assembly of the triblock copolymer1214to form the segregated structure1220.

Referring collectively toFIGS. 12A-12C, in an embodiment, a structure1220for directed self-assembly of a back end of line (BEOL) semiconductor structure metallization layer includes a substrate (not shown, but described below, and to be appreciated as being below ILD lines1204and metal lines1202)). A lower metallization layer includes alternating metal lines1202and dielectric lines1204disposed above the substrate. A triblock copolymer layer1214is disposed above the lower metallization layer. The triblock copolymer layer includes a first segregated block component1222disposed over the dielectric lines1204of the lower metallization layer. The triblock copolymer layer includes alternating second1224and third1226segregated block components disposed over the metal lines1202of the lower metallization layer.

In an embodiment, the third segregated block1226component of the triblock copolymer layer1214is photosensitive. In an embodiment, the triblock copolymer layer1214is formed to a thickness approximately in the range of 5-100 nanometers. In an embodiment, the triblock copolymer layer1214includes a triblock copolymer species selected from the group consisting of any three of poly-styrene and other polyvinylarenes, polyisoprene and other polyolefins, poly-methacrylate and other poly-esters, polydimethylsiloxane (PDMS) and related Si-based polymers, polyferrocenylsilanes, polyethyelene oxide (PEO) and related poly-ethers and poly-vinylpyridine. In one embodiment, the alternating second1224and third1226segregated block components have a ratio of approximately 1:1, as is depicted inFIG. 21C(and as is described below in association withFIG. 12H). In another embodiment, the alternating second1224and third1226segregated block components have a ratio of X:1, second segregated block component1224to third segregated block component1226, where X is greater than 1, and where the third segregated block component1226has a columnar structure surrounded by the second segregated block component, as is described below in association withFIG. 12I. In another embodiment, the triblock copolymer layer1214is a blend of homopolymers of A, B, and/or C or diblock BCPs of the A-B, B-C, or A-C components in order to achieve the desired morphology.

In an embodiment, the structure1220further includes a first molecular brush layer1212disposed on the dielectric lines1204of the lower metallization layer. In that embodiment, the first segregated block component1222is disposed on the first molecular brush layer. In an embodiment, the structure1220also includes a second, different, molecular brush layer1210disposed on the metal lines102of the lower metallization layer. The alternating second1224and third1226segregated block components are disposed on the second molecular brush layer1210. In one embodiment, the first molecular brush layer1212includes a molecular species1208including polystyrene with a head group selected from the group consisting of —SH, —PO3H2, —CO2H, —NRH, —NRR′, and —Si(OR)3, and the second molecular brush layer1210includes a molecular species1206including polymethacrylate with a head group selected from the group consisting of —SH, —PO3H2, —CO2H, —NRH, —NRR′, and —Si(OR)3.

In an embodiment, the alternating metal lines1202and dielectric lines1204of the lower metallization layer have a grating pattern with a constant pitch. In an embodiment, the third segregated block component1226of the triblock copolymer layer1214defines all possible via locations for a metallization layer above the lower metallization layer. In an embodiment, the third segregated block component1226of the triblock copolymer layer1214is photosensitive to an extreme ultra-violet (EUV) source or an e-beam source.

FIG. 12Dillustrates an angled cross-sectional view representing an operation in a method using triblock copolymers for forming self-aligning vias or contacts for back end of line (BEOL) interconnects, in accordance with an embodiment of the present disclosure.

Referring toFIG. 12D, all portions of the third segregated block component1226of the structure1220ofFIG. 12Care removed. In one such embodiment, the removal of all portions of the third segregated block component1226opens all possible via locations that may be formed above the underlying metallization later. The openings may be filled with a photo-resist layer to ultimately allow for selection of only those via locations need for a particular design. It is to be appreciated that, in the case ofFIG. 12D, the third segregated block component1226of the structure1220may be, but need not be, photosensitive, since the removal of all portions of the third segregated block component1226of the structure1220ofFIG. 12Cmay be performed by selective etching alone (e.g., selective to first segregated block component1222and to second segregated block component1224). In one such embodiment, the selective etching may be performed using a selective dry etch or a selective wet etch, or both.

FIG. 12Eillustrates an angled cross-sectional view representing an operation in another method using triblock copolymers for forming self-aligning vias or contacts for back end of line (BEOL) interconnects, in accordance with another embodiment of the present disclosure.

Referring toFIG. 12E, only select portions of the third segregated block component1226of the structure1220ofFIG. 12Care removed. In one such embodiment, the removal of only select portions of the third segregated block component1226only those via locations above the underlying metallization layer needed for a particular design. It is to be appreciated that, in the case ofFIG. 2E, the third segregated block component1226of the structure1220is photosensitive, and location selection is performed using localized, but highly tolerant lithographic exposure. The exposure may be described as tolerant since neighboring materials1222and1224adjacent locations1226are, in one embodiment, not photosensitive to the lithography used to select the locations for portions of removal of component1226.

FIG. 12Fillustrates a triblock copolymer for forming self-aligning vias or contacts for back end of line (BEOL) interconnects, in accordance with an embodiment of the present disclosure.

Referring toFIG. 12F, a segregated triblock BCP1250may be partitioned along axis1252by portions1222,1224,1226. It is to be appreciated that other partitioning arrangements may be possible, such as asymmetrical arrangements. In an embodiment, there is etch selectivity between components1222,1224and1226, which may be a s great as 10:1 etch selectivity for one component relative to the other two components. In an embodiment, the use of triblock BCP1250can improve pattern fidelity and reduce critical dimension (CD) variation. In an embodiment, the segregated triblock BCP1250can be implemented to enable a self-aligning strategy that complements a 193 nanometer immersion lithography (193i) or an extreme ultraviolet lithography (EUVL) process.

It is to be appreciated that, typically, the blocks of triblock copolymers may each have different chemical properties. As one example, one of the blocks may be relatively more hydrophobic (e.g., water repelling) while the two blocks may be relatively more hydrophilic (water attracting), or vice versa. At least conceptually, one of the blocks may be relatively more similar to oil and the other two blocks may be relatively more similar to water, or vice versa. Such differences in chemical properties between the different blocks of polymers, whether a hydrophilic-hydrophobic difference or otherwise, may cause the block copolymer molecules to self-assemble. For example, the self-assembly may be based on microphase separation of the polymer blocks. Conceptually, this may be similar to the phase separation of oil and water which are generally immiscible.

Similarly, differences in hydrophilicity between the polymer blocks may cause a roughly analogous microphase separation where the different polymer blocks try to “separate” from each other due to chemical dislike for one another. However, in an embodiment, since the polymer blocks are covalently bonded to one another, they cannot completely separate on a macroscopic scale. Rather, polymer blocks of a given type may tend to segregate or conglomerate with polymer blocks of the same type of other molecules in extremely small (e.g., nano-sized) regions or phases. The particular size and shape of the regions or microphases generally depends at least in part upon the relative lengths of the polymer blocks. In an embodiment, by way of example,FIGS. 12C, 12H and 12Idepict possible assembly schemes for a triblock copolymer.

It is to be appreciated that a pattern needed to open a pre-formed via or plug location can be made to be relatively small, enabling an increase in the overlay margin of a lithographic process. The pattern features can be made of uniform size, which can reduce scan time on direct write ebeam and/or optical proximity correction (OPC) complexity with optical lithography. The pattern features can also be made to be shallow, which can improve the patterning resolution. A subsequently performed etch process may be an isotropic chemically selective etch. Such an etch process mitigates otherwise associated with profile and critical dimension and mitigates anisotropic issues typically associated with dry etch approaches. Such an etch process is also relatively much less expensive from an equipment and throughput perspective as compared to other selective removal approaches.

The following describes portions of integrated circuit layers representing various operations in a method of self-aligned via and metal patterning. In particular,FIGS. 12G and 12Hillustrate plan views and corresponding cross-sectional views representing various operations in a method using triblock copolymers for forming self-aligning vias or contacts for back end of line (BEOL) interconnects, in accordance with an embodiment of the present disclosure.

FIG. 12Gillustrates a plan view and corresponding cross-sectional views taken along the a-a′ axis of options for a previous layer metallization structure, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-section view option (a), a starting structure1260includes a pattern of metal lines1262and interlayer dielectric (ILD) lines1264. The starting structure1260may be patterned in a grating-like pattern with metal lines spaced at a constant pitch and having a constant width, as is depicted inFIG. 12Gin the case that self-assembling materials are ultimately formed thereon. In the case of cross-sectional view (a), the pattern of metal lines1262and interlayer dielectric (ILD) lines1264are planar with one another. Some of the lines may be associated with underlying vias, such as line1262′ shown as an example in the cross-sectional views.

Referring again toFIG. 12G, alternative options (b)-(f) address situations where an additional film is formed (e.g., deposited, grown, or left as an artifact remaining from a previous patterning process) on a surface of one of, or both of, the metal lines1262and interlayer dielectric lines1264. In example (b), an additional film1266is disposed on the interlayer dielectric lines1264. In example, (c), an additional film1268is disposed on the metal lines1262. In example, (d) an additional film1266is disposed on the interlayer dielectric lines1264, and an additional film1268is disposed on the metal lines1262. Furthermore, although the metal lines1262and the interlayer dielectric lines1264are depicted as co-planar in (a), in other embodiments, they are not co-planar. For example, in (e), the metal lines1262protrude above the interlayer dielectric lines1264. In example, (f), the metal lines1262are recessed below the interlayer dielectric lines1264.

Referring again to examples (b)-(d), an additional layer (e.g., layer1266or1268) can be used as a hardmask (HM) or protection layer or be used to enable self-assembly described below in association with subsequent processing operations. Such additional layers may also be used to protect the ILD lines from further processing. In addition, selectively depositing another material over the metal lines may be beneficial for similar reasons. Referring again to examples (e) and (f), it may also be possible to recess either the ILD lines or the metal lines with any combination of protective/HM materials on either or both surfaces. Overall, there exist numerous options at this stage for preparing ultimately underlying surfaces for a directed self-assembly process.

Referring toFIG. 12H, a triblock copolymer layer1270is formed on the structure ofFIG. 12G(e.g., plan view and cross-sectional structure (a)). The triblock copolymer layer1270is segregated to have regions1272formed above the ILD lines1264, and to have alternating second regions1274and third regions1276formed above metal lines1262.

Referring to the cross-sectional view along the b-b′ axis ofFIG. 12H, the third regions1276are shown above the metal lines1262, and the first regions1272are shown above the ILD lines1264. In accordance with one embodiment, also shown between first regions1272and ILD lines1264is layer1280which may be a remnant of a molecular brush layer. However, it is to be appreciated that layer1280may not be present. In accordance with one embodiment, third regions1276are shown as formed directly on metal lines1262. However, it is to be appreciated that remnants of a molecular brush layer may be between the third regions1276and the metal lines1262.

Referring to the cross-sectional view along the c-c′ axis ofFIG. 12H, the second regions1274are shown above the metal lines1262, and the first regions1272are shown above the ILD lines1264. In accordance with one embodiment, also shown between first regions1272and ILD lines1264is layer1280which may be a remnant of a molecular brush layer. However, it is to be appreciated that layer1280may not be present. In accordance with one embodiment, also shown between second regions1274and metal lines1262is layer1282which may be a remnant of a molecular brush layer. However, it is to be appreciated that layer1282may not be present. It is also to be appreciated that regions1276may be formed as photosensitive or may be replaced by a photosensitive material.

Thus, in an embodiment, an underlying metal and ILD grid is recreated in a block copolymer (BCP). This can particularly be so if the BCP pitch is commensurate with the underlying grating pitch. The polymer grid is, in one embodiment, robust against certain small deviations from a highly well-aligned grid such. For example, if small plugs effectively place an oxide or like material where a highly well-aligned grid would have metal, an essentially highly well-aligned block copolymer grid can still be achieved.

In an embodiment, referring again toFIG. 12H, the thickness of the coated with triblock copolymer layer1270is approximately the same as, or slightly thicker than, the ultimate thickness of an ILD ultimately formed in its place. In an embodiment, as described in greater detail below, the polymer grid is formed not as an etch resist, but rather as scaffolding for ultimately growing a permanent ILD layer there around. As such, the thickness of the with triblock copolymer layer1270can be important since it may be used to define the ultimate thickness of a subsequently formed permanent ILD layer. That is, in one embodiment, the polymer grating shown inFIG. 12His eventually replaced with an ILD/metal line grating of roughly the same thickness.

In an embodiment, the triblock copolymer layer1270molecule is a polymeric molecule formed of a chain of covalently bonded monomers. In a triblock copolymer, there are three different types of monomers, and these different types of monomers are primarily included within different blocks or contiguous sequences of monomers. In an embodiment, the triblock copolymer layer1270is first applied as an unassembled block copolymer layer portion that includes a block copolymer material applied, e.g., by brush or other coating process. The unassembled aspect refers to scenarios where, at the time of deposition, the block copolymer has not yet substantially phase separated and/or self-assembled to form nanostructures. In this unassembled form, the block polymer molecules are relatively highly randomized, with the different polymer blocks relatively highly randomly oriented and located, which is in contrast to the assembled triblock copolymer layer1270discussed in association with the resulting structure ofFIG. 12H. The unassembled block copolymer layer portion may be applied in a variety of different ways. By way of example, the block copolymer may be dissolved in a solvent and then spin coated over the surface. Alternatively, the unassembled block copolymer may be spray coated, dip coated, immersion coated, or otherwise coated or applied over the surface. Other ways of applying block copolymers, as well as other ways known in the art for applying similar organic coatings, may potentially be used. Then, the unassembled layer may form an assembled block copolymer layer portion, e.g., by microphase separation and/or self-assembly of the unassembled block copolymer layer portion. The microphase separation and/or self-assembly occurs through rearrangement and/or repositioning of the block copolymer molecules, and in particular to rearrangement and/or repositioning of the different polymer blocks of the block copolymer molecules to form triblock copolymer layer1270.

In one such embodiment, an annealing treatment may be applied to the unassembled block copolymer in order to initiate, accelerate, increase the quality of, or otherwise promote microphase separation and/or self-assembly to form triblock copolymer layer1270. In some embodiments, the annealing treatment may include a treatment that is operable to increase a temperature of the block copolymer. One example of such a treatment is baking the layer, heating the layer in an oven or under a thermal lamp, applying infrared radiation to the layer, or otherwise applying heat to or increasing the temperature of the layer. The desired temperature increase will generally be sufficient to significantly accelerate the rate of microphase separation and/or self-assembly of the block polymer without damaging the block copolymer or any other important materials or structures of the integrated circuit substrate. Commonly, the heating may range between about 50° C. to about 300° C., or between about 75° C. to about 250° C., but not exceeding thermal degradation limits of the block copolymer or integrated circuit substrate. The heating or annealing may help to provide energy to the block copolymer molecules to make them more mobile/flexible in order to increase the rate of the microphase separation and/or improve the quality of the microphase separation. Such microphase separation or rearrangement/repositioning of the block copolymer molecules may lead to self-assembly to form extremely small (e.g., nano-scale) structures. The self-assembly may occur under the influence of forces such as surface tension, molecular likes and dislikes, and other surface-related and chemical-related forces.

In any case, in some embodiments, self-assembly of block copolymers, whether based on hydrophobic-hydrophilic differences or otherwise, may be used to form extremely small periodic structures (e.g., precisely spaced nano-scale structures or lines) in the form of triblock copolymer layer12720. In some embodiments, they may be used to form nano-scale lines or other nano-scale structures that can ultimately be used to form via openings. In some embodiments, directed self-assembly of block copolymers may be used to form vias that are self-aligned with interconnects, as described in greater detail below.

It is to be appreciated that the two components of a triblock copolymer structure that are formed above metal lines need not have a 1:1 ratio (a 1:1 ratio was shown inFIGS. 12C and 12H). For example, the third segregated block component may be present in a lesser amount than the second component and may have a columnar structure surrounded by the second segregated block component.FIGS. 12I-12Lillustrate plan views and corresponding cross-sectional views representing various operations in a method using triblock copolymers for forming self-aligning vias or contacts for back end of line (BEOL) interconnects, in accordance with an embodiment of the present disclosure.

Referring toFIG. 12I, a plan view and corresponding cross-sectional view taken along the d-d′ axis shows the third component1276in lesser amount than the second component1274. The third segregated block component1276has a columnar structure surrounded by the second segregated block component1274.

Referring toFIG. 12J, a plan view shows lithography1290selection of certain ones1292of the third segregated block component1276is performed to ultimately provide via locations for an upper metallization structure.

It is to be appreciated thatFIG. 12Ieffectively illustrates an unexposed photosensitive DSA structure, whileFIG. 12Jillustrates an exposed photosensitive DSA structure. In contrast toFIG. 12H,FIGS. 12I and 12Jdemonstrate an example of a columnar structure which may formed when many block copolymer molecules align with their shorter blocks of one of polymer forming columnar structures surrounded by a phase having the longer blocks of another polymer. In accordance with an embodiment of the present disclosure, the photoactive properties of a DSA structure provides the ability to effectively “plug” or “cut” one type of DSA polymer region with, e.g., e-beam or EUV exposure.

Referring toFIG. 12K, a plan view shows exposed/chemically amplified regions1294in the zones of exposure. By selectivity, the only active modification is of the material of exposed portions of the third segregated block component1276. It is to be appreciated that, although shown as already cleared inFIG. 12K, the select regions may not yet be cleared.

Referring toFIG. 12L, a plan view and corresponding cross-sectional view taken along the e-e′ axis shows post lithographic development to provide cleared regions1294. The cleared regions1294may ultimately be used for via formation.

The resulting patterned DSA structure ofFIG. 12L(orFIG. 12C, 12D, 12E or 12H) described above in may ultimately be used as a scaffolding from which permanent layers are ultimately formed. That is, it may be the case that none of the DSA materials exist in a final structure, but rather are used to direct fabrication of a finalized interconnect structure. In one such embodiment, a permanent ILD replaces one or more regions of the DSA material and subsequent processing (such as metal line fabrication) is completed. That is, it is possible that all DSA components ultimately removed for final self-aligned via and plug formation. In other embodiments at least some of the DSA material may remain behind in the final structure.

With reference again toFIGS. 12A-12C, 12G, 12H and 12I-12L, in an embodiment, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer that has alternating metal lines and dielectric lines above a substrate. A triblock copolymer layer is formed above the lower metallization layer. The triblock copolymer layer is segregated to form a first segregated block component over the dielectric lines of the lower metallization layer, and to form alternating second and third segregated block components disposed over the metal lines of the lower metallization layer. The third segregated block component is photosensitive. The method also includes irradiating and developing select locations of the third segregated block component to provide via openings over the metal lines of the lower metallization layer.

In an embodiment, the alternating second and third segregated block components have a ratio of approximately 1:1, as was described in association withFIGS. 12C and 12H. In another embodiment, the alternating second and third segregated block components have a ratio of X:1, second segregated block component to third segregated block component, where X is greater than 1. In that embodiment, the third segregated block component has a columnar structure surrounded by the second segregated block component, as was described in association withFIG. 12I.

In an embodiment, the method further includes, subsequent to irradiating and developing select locations of the third segregated block component to provide the via openings, using the resulting patterned triblock copolymer layer as a scaffolding to form a second level of alternating metal lines and dielectric lines above, coupled to, and orthogonal with the first level of alternating metal lines and dielectric lines. In one embodiment, one or more components of the triblock copolymer layer are retained in the final structure. However, in other embodiments, all components of the triblock copolymer layer are ultimately sacrificial in the sense that none of the material is retained in the final product. An exemplary embodiment of an implementation of the latter embodiment is described below in association withFIG. 13.

In an embodiment, the method further includes, prior to forming the triblock copolymer layer, forming a first molecular brush layer on the dielectric lines of the lower metallization layer, and forming a second, different, molecular brush layer on the metal lines of the lower metallization layer, exemplary embodiments of which were described above in association withFIGS. 12A-12C. In an embodiment, irradiating and developing the select locations of the third segregated block component includes exposing the select locations of the third segregated block component to an extreme ultra-violet (EUV) source or an e-beam source.

Provided merely as an example of a final structure that may ultimately be obtained,FIG. 13illustrates a plan view and corresponding cross-sectional views of a self-aligned via structure following metal line, via and plug formation, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes, f-f′ and g-g′, respectively, an upper level of metal lines1302is provided in a dielectric framework (e.g., on dielectric layer1304and adjacent to dielectric lines1314. The metal lines1302are coupled with underlying metal lines1262through the predetermined via locations (an example1306of which is shown in cross-sectional view (a)), and are isolated by plugs (examples of which include plugs1308and1310). The underlying lines1262and1264may be as described above in association withFIG. 12G, as formed in a direction orthogonal to the metal lines1302. It is to be appreciated that, in subsequent fabrication operations, the dielectric lines1314may be removed to provide air gaps between the resulting metal lines1302.

A resulting structure such as that described in association withFIG. 13may subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 13may represent the final metal interconnect layer in an integrated circuit. It is to be appreciated that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed. In any case, the resulting structures enable fabrication of vias that are directly centered on underlying metal lines. That is, the vias may be wider than, narrower than, or the same thickness as the underlying metal lines, e.g., due to non-perfect selective etch processing. Nonetheless, in an embodiment, the centers of the vias are directly aligned (match up) with the centers of the metal lines. As such, in an embodiment, offset due to conventional lithograph/dual damascene patterning that must otherwise be tolerated, is not a factor for the resulting structures described herein. It is to be appreciated that the above examples have focused on via/contact formation. However, in other embodiments, similar approaches may be used to preserve or form regions for line end termination (plugs) within a metal line layer.

It is to be appreciated that process flows described herein may be described as predominantly DSA-based (such as several of the process schemes described above), while other may be predominantly etch-based. In accordance with an embodiment of the present disclosure, a deep subtractive approach is implemented for BEOL processing. One or more embodiments described herein are directed to subtractive approaches for self-aligned via and plug patterning, and structure resulting there from. In an embodiment, processes described herein enable realization of self-aligned metallization for back-end of line feature fabrication. Overlay problems anticipated for next generation via and plug patterning may be addressed by one or more approaches described herein. In general, one or more embodiment described herein involves the use of a subtractive method to pre-form every via and plug using the trenches already etched. An additional operation is then used to select which of the vias and plugs to retain.

FIGS. 14A-14Nillustrate portions of integrated circuit layers representing various operations in a method of subtractive self-aligned via and plug patterning, in accordance with an embodiment of the present disclosure. In each illustration at each described operation, an angled three-dimensional cross-section view is provided.

FIG. 14Aillustrates a starting point structure1400for a subtractive via and plug process following deep metal line fabrication, in accordance with an embodiment of the present disclosure. Referring toFIG. 14A, structure1400includes metal lines1402with intervening interlayer dielectric (ILD) lines1404. The ILD lines1404include a plug cap layer1406. In an embodiment, as described in greater detail below in association withFIG. 14E, the plug cap layer1406is later patterned to ultimately define all possible location for later plug formation.

In an embodiment, the grating structure formed by metal lines1402is a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern ofFIG. 14Amay have metal lines spaced at a constant pitch and having a constant width. The pattern may be fabricated by a pitch halving or pitch quartering approach. It is also to be appreciated that some of the lines1402may be associated with underlying vias for coupling to a previous interconnect layer.

In an embodiment, the metal lines1402are formed by patterning trenches into an ILD material (e.g., the ILD material of lines1404) having the plug cap layer1406formed thereon. The trenches are then filled by metal and, if needed, planarized to the plug cap layer1406. In an embodiment, the metal trench and fill process involves high aspect ratio features. For example, in one embodiment, the aspect ratio of metal line height (h) to metal line width (w) is approximately in the range of 5-10.

FIG. 14Billustrates the structure ofFIG. 14Afollowing recessing of the metal lines, in accordance with an embodiment of the present disclosure. Referring toFIG. 14B, the metal lines1402are recessed selectively to provide first level metal lines1408. The recessing is performed selectively to the ILD lines1404and the plug cap layer1406. The recessing may be performed by etching through dry etch, wet etch, or a combination thereof. The extent of recessing may be determined by the targeted thickness (th) of the first level metal lines1408for use as suitable conductive interconnect lines within a back end of line (BEOL) interconnect structure.

FIG. 14Cillustrates the structure ofFIG. 14Bfollowing hardmask fill in the recessed regions of the recessed metal lines, in accordance with an embodiment of the present disclosure. Referring toFIG. 14C, hardmask layer1410is formed in the regions formed during recessing to form the first level metal lines1408. The hardmask layer1410may be formed by a material deposition and chemical mechanical planarization (CMP) process to the level of plug cap layer1406, or by a controlled bottom-up only growth process. In one specific embodiment, the hardmask layer1410is composed of a carbon-rich material.

FIG. 14Dillustrates the structure ofFIG. 14Cfollowing deposition and patterning a hardmask layer, in accordance with an embodiment of the present disclosure. Referring toFIG. 14Da second hardmask layer1412is formed on or above the hardmask layer1410and plug cap layer1406. In one such embodiment, the second hardmask layer1412is formed with a grating pattern orthogonal to the grating pattern of the first level metal lines1408/ILD lines1404, as is depicted inFIG. 14D. In one specific embodiment, the second hardmask layer1412is composed of a silicon-based anti-reflective coating material. In an embodiment, the grating structure formed by second hardmask layer1412is a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning, as is known in the art. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the second hardmask layer1412ofFIG. 14Dmay have hardmask lines spaced at a constant pitch and having a constant width.

FIG. 14Eillustrates the structure ofFIG. 14Dfollowing trench formation defined using the pattern of the hardmask ofFIG. 14D, in accordance with an embodiment of the present disclosure. Referring toFIG. 14E, the exposed regions (i.e., unprotected by1412) of the hardmask layer1410and the plug cap layer1406are etched to form trenches1414. The etch stops on, and thus exposes, the top surfaces of the first level metal lines1408and the ILD lines1404.

FIG. 14Fillustrates the structure ofFIG. 14Efollowing ILD formation in the trenches ofFIG. 14Eand removal of the second hardmask, in accordance with an embodiment of the present disclosure. Referring toFIG. 14F, second ILD lines1416are formed in the trenches1414ofFIG. 14E. In an embodiment, a flowable ILD material is used to fill trenches1414. In an embodiment, the trenches1414are filled and the fill material is subsequently planarized. The planarization may further be used to remove second hardmask layer1412, re-exposing the hardmask layer1410and the plug cap layer1406, as is depicted inFIG. 14F.

Referring again toFIG. 14F, in an embodiment, the resulting structure includes a uniform ILD structure (ILD lines1404+ILD lines1416). The locations of all possible plugs are occupied by the remaining portions of the plug cap layer1406, while all possible via locations are occupied by the remaining portions of hardmask layer1410. In one such embodiment, ILD lines1404and ILD line1416are composed of a same material. In another such embodiment, ILD lines1404and ILD lines1416are composed of different ILD materials. In either case, in a specific embodiment, a distinction such as a seam between the materials of ILD lines1404and ILD lines1416may be observed in the final structure. Furthermore, in an embodiment, there is no distinct etch stop layer where the ILD lines1404and ILD lines1416meet, in contrast to conventional single or dual damascene patterning.

FIG. 14Gillustrates the structure ofFIG. 14Ffollowing removal of the remaining portions of hardmask layer occupying all possible via locations, in accordance with an embodiment of the present disclosure. Referring toFIG. 14G, the remaining portions of hardmask layer1410are selectively removed to form openings1418for all possible via locations. In one such embodiment, the hardmask layer1410is composed substantially of carbon and is removed selectively with an ash process.

In general, one or more embodiment described herein involves the use of a subtractive method to pre-form every via and plug using the trenches already etched. An additional operation is then used to select which of the vias and plugs to retain. Such operations can be illustrated using “photobuckets,” although the selection process may also be performed using a more conventional resist expose and ILD backfill approach. It is also to be appreciated that embodiments are not limited to the concept of photobuckets, but have far reaching applications to structures having pre-formed features fabricated using bottom-up and/or directed self-assembly (DSA) approach. Additional embodiments directed at the fabrication and use of photobuckets is described in greater detail below in embodiments beyond the present embodiments ofFIGS. 14A-14N and 15A-15D.

FIG. 14Hillustrates the structure ofFIG. 14Gfollowing photobucket formation in all possible via locations, in accordance with an embodiment of the present disclosure. Referring toFIG. 14H, photobuckets1420are formed in all possible via locations above exposed portions of the first level metal lines1408. In an embodiment, the openings1418ofFIG. 14Gare filled with an ultrafast photoresist or ebeam resist or other photosensitive material. In one such embodiment, a thermal reflow of a polymer into the openings1418is used following a spin coat application. In one embodiment, the fast photoresist is fabricated by removing a quencher from an existing photoresist material. In another embodiment, the photobuckets1420are formed by an etch-back process and/or a lithography/shrink/etch process. It is to be appreciated that the photobuckets need not be filled with actual photoresist, so long as the material acts as a photosensitive switch.

FIG. 14Iillustrates the structure ofFIG. 14Hfollowing via location selection, in accordance with an embodiment of the present disclosure. Referring toFIG. 14I, the photobuckets1420fromFIG. 14Hin select via locations are removed. In locations where vias are not selected to be formed, the photobuckets1420are retained, converted to a permanent ILD material, or replaced with a permanent ILD material. As an example,FIG. 14Iillustrates a via location1422with corresponding photobucket1420being removed to expose a portion of one of the first level metal lines1408. The other locations previously occupied by photobuckets1420are now shown as regions1424inFIG. 14I. The locations1424are not selected for via formation and instead make up part of the final ILD structure. In one embodiment, the material of the photobuckets1420is retained in the locations1424as a final ILD material. In another embodiment, the material of the photobuckets1420is modified, e.g., by cross-linking, in the locations1424to form a final ILD material. In yet another embodiment, the material of the photobuckets1420in the locations1424is replaced by a final ILD material.

Referring again toFIG. 14I, to form via location1422, lithography is used to expose the corresponding photobucket1420. However, the lithographic constraints may be relaxed and misalignment tolerance may be high since the photobucket1420is surrounded by non-photolyzable materials. Furthermore, in an embodiment, instead of exposing at, e.g. 30 mJ/cm2, such a photobucket might be exposed at, e.g., 3 mJ/cm2. Normally this would result in very poor CD control and roughness. But in this case, the CD and roughness control will be defined by the photobucket1420, which can be very well controlled and defined. Thus, the photobucket approach may be used to circumvent imaging/dose tradeoff which limits the throughput of next generation lithographic processes.

Referring again toFIG. 14I, in an embodiment, the resulting structure includes a uniform ILD structure (ILD1424+ILD lines1404+ILD lines1416). In one such embodiment, two or all of ILD1424, ILD lines1404and ILD line1416are composed of a same material. In another such embodiment, ILD1424, ILD lines1404and ILD lines1416are composed of different ILD materials. In either case, in a specific embodiment, a distinction such as a seam between the materials of ILD1424and ILD lines1404(e.g., seam1497) and/or between ILD1424and ILD lines1416(e.g., seam1498) is observed in the final structure.

FIG. 14Jillustrates the structure ofFIG. 14Ifollowing hardmask fill in the openings ofFIG. 14I, in accordance with an embodiment of the present disclosure. Referring toFIG. 14J, a hardmask layer1426is formed in via location1422and above ILD locations1424. The hardmask layer1426may be formed by deposition and subsequent chemical mechanical planarization.

FIG. 14Killustrates the structure ofFIG. 14Jfollowing removal of the plug cap layer and formation of a second plurality of photobuckets, in accordance with an embodiment of the present disclosure. Referring toFIG. 14K, the plug cap layer1406is removed, e.g., by a selective etching process. Photobuckets1428are then formed in all possible plug locations above exposed portions of the ILD lines1404. In an embodiment, openings formed upon removal of the plug cap layer1406are filled with an ultrafast photoresist or ebeam resist or other photosensitive material. In one such embodiment, a thermal reflow of a polymer into the openings is used following a spin coat application. In one embodiment, the fast photoresist is fabricated by removing a quencher from an existing photoresist material. In another embodiment, the photobuckets1428are formed by an etch-back process and/or a lithography/shrink/etch process. It is to be appreciated that the photobuckets need not be filled with actual photoresist, so long as the material acts as a photosensitive switch.

FIG. 14Lillustrates the structure ofFIG. 14Kfollowing plug location selection, in accordance with an embodiment of the present disclosure. Referring toFIG. 14L, the photobuckets1428fromFIG. 14Kthat are not in select plug locations are removed. In locations where plugs are selected to be formed, the photobuckets1428are retained, converted to a permanent ILD material, or replaced with a permanent ILD material. As an example,FIG. 14Lillustrates non-plug locations1430with corresponding photobuckets1428being removed to expose a portion of the ILD lines1404. The other location previously occupied by photobucket1428is now shown as region1432inFIG. 14L. The region1432is selected for plug formation and makes up part of the final ILD structure. In one embodiment, the material of the corresponding photobucket1428is retained in the region1432as a final ILD material. In another embodiment, the material of the photobucket1428is modified, e.g., by cross-linking, in the region1432to form a final ILD material. In yet another embodiment, the material of the photobucket1428in the region1432is replaced by a final ILD material. In any case, region1432can also be referred to as plug1432.

Referring again toFIG. 14L, to form openings1430, lithography is used to expose the corresponding photobuckets1428. However, the lithographic constraints may be relaxed and misalignment tolerance may be high since the photobuckets1428are surrounded by non-photolyzable materials. Furthermore, in an embodiment, instead of exposing at, e.g. 30 mJ/cm2, such photobuckets might be exposed at, e.g., 3 mJ/cm2. Normally this would result in very poor CD control and roughness. But in this case, the CD and roughness control will be defined by the photobuckets1428, which can be very well controlled and defined. Thus, the photobucket approach may be used to circumvent imaging/dose tradeoff which limits the throughput of next generation lithographic processes.

Referring again toFIG. 14L, in an embodiment, the resulting structure includes a uniform ILD structure (plug1432+ILD1424+ILD lines1404+ILD lines1416). In one such embodiment, two or more of plug1432, ILD1424, ILD lines1404and ILD line1416are composed of a same material. In another such embodiment, plug1432, ILD1424, ILD lines1404and ILD lines1416are composed of different ILD materials. In either case, in a specific embodiment, a distinction such as a seam between the materials of plug1432and ILD lines1404(e.g., seam1499) and/or between plug1432and ILD lines1416(e.g., seam1496) is observed in the final structure.

FIG. 14Millustrates the structure ofFIG. 14Lfollowing removal of the hardmask layer ofFIG. 14L, in accordance with an embodiment of the present disclosure. Referring toFIG. 14M, the hardmask layer1426is selectively removed to form metal line and via openings1434. In one such embodiment, the hardmask layer1426is composed substantially of carbon and is removed selectively with an ash process.

FIG. 14Nillustrates the structure ofFIG. 14Mfollowing metal line and via formation, in accordance with an embodiment of the present disclosure. Referring toFIG. 14N, metal lines1434and vias (one shown as1438) are formed upon metal fill of the openings1434ofFIG. 14M. The metal lines1436are coupled to the underlying metal lines1408by vias1438and are interrupted by plugs1432. In an embodiment, openings1434are filled in a damascene approach, where metal is used to overfill the openings and is then planarized back to provide the structure shown inFIG. 14N. Thus, the metal (e.g., copper and associated barrier and seed layers) deposition and planarization process to form metal lines and vias in the above approach may be that typically used for standard back end of line (BEOL) single or dual damascene processing. In an embodiment, in subsequent fabrication operations, the ILD lines1416may be removed to provide air gaps between the resulting metal lines1436.

The structure ofFIG. 14Nmay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 14Nmay represent the final metal interconnect layer in an integrated circuit. It is to be appreciated that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed. In any case, the resulting structures enable fabrication of vias that are directly centered on underlying metal lines. That is, the vias may be wider than, narrower than, or the same thickness as the underlying metal lines, e.g., due to non-perfect selective etch processing. Nonetheless, in an embodiment, the centers of the vias are directly aligned (match up) with the centers of the metal lines. Furthermore, the ILD used to select which plugs and vias will likely be very different from the primary ILD and will be highly self-aligned in both directions. As such, in an embodiment, offset due to conventional lithograph/dual damascene patterning that must otherwise be tolerated, is not a factor for the resulting structures described herein. Referring again toFIG. 14N, then, self-aligned fabrication by the subtractive approach may be complete at this stage. A next layer fabricated in a like manner may involve performing the described process once again. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

The above described process flow involves use of deep trench etching. In another aspect, a shallower approach involves a plug-only self-aligned subtractive processing scheme. As an example,FIGS. 15A-15Dillustrate portions of integrated circuit layers representing various operations in a method of subtractive self-aligned plug patterning, in accordance with another embodiment of the present disclosure. In each illustration at each described operation, plan views are shown on top, and corresponding cross-sectional views are shown on the bottom. These views will be referred to herein as corresponding cross-sectional views and plan views.

FIG. 15Aillustrates a plan view and corresponding cross-sectional views of a starting plug grid, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a′ and b-b′, respectively, a starting plug grid structure1500includes an ILD layer1502having a first hardmask layer1504disposed thereon. A second hardmask layer1508is disposed on the first hardmask layer1504and is patterned to have a grating structure. A third hardmask layer1506is disposed on the second hardmask layer1508and on the first hardmask layer1504. Additionally, openings1510remain between the grating structure of the second hardmask layer1508and the third hardmask layer1506.

FIG. 15Billustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 15Afollowing photobucket fill, exposure and development, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a′ and b-b′, respectively, photobuckets1512are formed in the openings1510ofFIG. 15A. Subsequently, select photobuckets are exposed and removed to provide selected plug locations1514, as depicted inFIG. 15B.

FIG. 15Cillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 15Bfollowing plug formation, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a′ and b-b′, respectively, plugs1516are formed in the openings1514ofFIG. 15B. In one embodiment, the plugs1516are formed by a spin-on approach and/or a deposition and etch back approach.

FIG. 15Dillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 15Cfollowing removal of a hardmask layer and the remaining photobuckets, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a′ and b-b′, respectively, the third hardmask layer1506is removed, leaving the second hardmask layer1508and the plugs1516. The resulting pattern (second hardmask layer1508and plugs1516) can subsequently be used to pattern hardmask layer1504for ultimate patterning of ILD layer1502. In one embodiment, the third hardmask layer1506is composed substantially of carbon and is removed by performing an ash process.

Thus, the structure ofFIG. 15Dmay subsequently be used as a foundation for forming ILD line and plug patterns. It is to be appreciated that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed. In any case, the resulting structures enable fabrication of self-aligned plugs. As such, in an embodiment, offset due to conventional lithograph/dual damascene patterning that must otherwise be tolerated, is not a factor for the resulting structures described herein.

In accordance with an embodiment of the present disclosure, dielectric helmet-based approaches and/or hardmask selectivity-based approaches for back end of line (BEOL) interconnect fabrication, and the resulting structures, are described. One or more embodiments described herein are directed to methods of using a dielectric helmet for directed self-assembly (DSA) or selective growth to enable the fabrication of self-aligned interconnects. Embodiments may address or implement one or more of the use of a dielectric helmet, directed self-assembly, selective deposition, self-alignment, or patterning interconnects at tight pitch. Embodiments may be implemented to provide improved via shorting margin by self-alignment with “coloring” through selective deposition, and subsequent directed self-assembly, e.g., for sub-10 nm technology nodes.

To provide context, current solutions to improve shorting margin may include: (1) using metal recess to fill alternate metal trenches with different hard masks, (2) using different “color” metal caps to as a template for directed self-assembly (DSA) or selective growth, or (3) recessing the metal or ILD to “steer” the via towards the line of interest. Overall, typical process flows for improving via shorting margin require a metal recess. However, recessing metal with acceptable uniformity has proven to be a challenge in many such processing schemes.

In accordance with an embodiment of the present disclosure, one or more of the above issues is addressed by implementing a method of depositing a non-conformal dielectric cap on half of a population of interconnects. The non-conformal dielectric cap is used as a template for selective growth or directed self-assembly. In one such embodiment, such an approach may be applied to any interconnect metal layer and, possibly, to gate contacts. In a specific embodiment, a need for metal recess as is seen in state-of-the art approaches is effectively eliminated from the processing schemes described herein.

As a general overview of concepts involved herein,FIGS. 16A-16Dillustrate cross-sectional views of portions of integrated circuit layers representing various operations in a method involving dielectric helmet formation for back end of line (BEOL) interconnect fabrication, in accordance with an embodiment of the present disclosure.

Referring toFIG. 16A, a starting point structure1600is provided as a beginning point for fabricating a new metallization layer. The starting point structure1600includes a hardmask layer1604disposed on an inter-layer dielectric (ILD) layer1602. As described below, the ILD layer may be disposed above a substrate and, in one embodiment, is disposed over an underlying metallization layer. Openings are formed in the hardmask layer1604which correspond to trenches formed in the ILD layer1602. Alternating one of the trenches are filled with a conductive layer to provide first metal lines1606(and, in some cases, corresponding conductive vias1607). The remaining trenches are not filled, providing open trenches1608. In an embodiment, the starting structure1600is fabricated by patterning a hardmask and ILD layer and then metallizing half of the population of metal trenches (e.g., alternating one of the trenches), leaving the other half of the population open. In one embodiment, the trenches in the ILD are patterned using a pitch division patterning process flow. It is to be appreciated that the following process operation described below may first involve pitch division, or may not. In either case, but particularly when pitch division is also used, embodiments may enable continued scaling of the pitch of metal layers beyond the resolution capability of state-of-the art lithography equipment.

FIG. 16Billustrates the structure ofFIG. 16Afollowing deposition of a non-conformal dielectric cap layer1610over the structure1600. The non-conformal dielectric cap layer1610includes a first portion1600A that covers exposed surfaces of the hardmask layer1604and the metal lines1606. The non-conformal dielectric cap layer1610includes a second portion1610B continuous with the first portion1610A. The second portion1610B of the non-conformal dielectric cap layer1610is formed in the open trenches1608, along sidewalls1608A and the bottom1608B of the open trenches1608. In an embodiment, the second portion1610B of the non-conformal dielectric cap layer1610is substantially thinner than the first portion1610A, as is depicted inFIG. 16B. In other embodiments, portion1610B is nonexistent or is discontinuous. In this way, the deposition of the non-conformal dielectric cap layer1610is considered to be a non-conformal deposition since the thickness of non-conformal dielectric cap layer1610is not the same in all locations. The resulting geometry may be referred to as a helmet shape for the non-conformal dielectric cap layer1610since the uppermost portions of the ILD layer1602have the thickest portion of the non-conformal dielectric cap layer1610thereon and, thus, are protected to a greater extent than other regions. In one embodiment, the non-conformal dielectric cap layer1610is a dielectric material such as, but not limited to silicon nitride or silicon oxy-nitride. In one embodiment, the non-conformal dielectric cap layer1610is formed using a plasma-enhanced chemical vapor deposition (PECVD) process or, in another embodiment physical vapor deposition (PVD).

FIG. 16Cillustrates the structure ofFIG. 16Bfollowing via patterning, metallization, and planarization of the second half of the metal lines. In an embodiment, a metal fill process is performed to provide second metal lines1612. In one embodiment, however, prior to the metal fill, via locations are first selected and opened. Then, upon metal fill, vias1613are formed as associated with certain ones of the second metal lines1612. In one such embodiment, via openings are formed by extending certain one of the open trenches1608by etching through the non-conformal dielectric cap layer1610at the bottom of the select trenches1608and then extended the trench through the dielectric layer1602. The result is a breaking of the continuity of the non-conformal dielectric cap layer1610at the via locations of the second metal lines1612, as is depicted inFIG. 16C.

In an embodiment, the metal fill process used to form second metal lines1612and conductive vias1613is performed using a metal deposition and subsequent planarization processing scheme, such as a chemical mechanical planarization (CMP) process. The planarization process exposes, but does not remove, the non-conformal dielectric cap layer1610, as is depicted inFIG. 16C. It is to be appreciated that, in an embodiment, since the second metal lines1612(and corresponding conductive vias1613) are formed in a later process than the process used to fabricate first metal lines1606(and corresponding conductive vias1607), the second metal lines1612can be fabricated using a different material than is used to fabricate the first metal lines1606. In one such embodiment, a metallization layer ultimately includes conductive interconnects of alternating, differing first and second compositions. In another embodiment, however, the metal lines1612and1606are fabricated from substantially the same material.

In an embodiment, the first metal lines1606are spaced apart by a pitch, and the second metal lines1612are spaced apart by the same pitch. In other embodiments, the lines are not necessarily spaced by a pitch. However, by inclusion of the non-conformal dielectric cap layer1610, or dielectric helmet, only the surfaces of the second metal lines1612are exposed. As a result, the pitch between neighboring first and second metal lines that would otherwise be exposed is relaxed to only the pitch of the second metal lines. Thus, alternating exposed dielectric surfaces of the non-conformal dielectric cap layer1610and exposed surfaces of the second metal lines1612provide a differentiated surface at the pitch of the second metal lines1612.

FIG. 16Dillustrates the structure ofFIG. 16Cfollowing a directed self-assembly or selective deposition approach to ultimately form two different, alternating, first and second hardmask layers1614and1616, respectively. In an embodiment, the materials of the hardmask layers1614and1616exhibit differing etch selectivity to one another. The first hardmask layer1614is aligned with exposed regions of the non-conformal dielectric cap layer1610. The second hardmask layer1616is aligned with exposed regions of the second metal lines1612. As described in greater detail below, directed self-assembly or selective growth can be used to align the first and second hardmask layers1614and1616selectively to dielectric and metal surfaces, respectively.

In a first general embodiment, in order to ultimately form first and second hardmask layers1614and1616, a direct self-assembly (DSA) block co-polymer deposition and polymer assembly process is performed. In an embodiment, a DSA block co-polymer is coated on the surface and annealed to segregate the polymer into first blocks and second blocks. In one embodiment, the first polymer blocks preferentially attaches to the non-conformal dielectric cap layer1610. The second polymer blocks adhere to the second metal lines1612. In an embodiment, the block copolymer molecule is a polymeric molecule formed of a chain of covalently bonded monomers, examples of which are described above.

Referring again toFIG. 16D, in the case of a DSA process, in a first embodiment, the first and second hardmask layers1614and1616are the first and second block polymers, respectively. In a second embodiment, however, the first and second block polymers are each sequentially replaces with the materials of the first and second hardmask layers1614and1616. In one such embodiment, selective etching and deposition process are used to replace the first and second block polymers with the materials of the first and second hardmask layers1614and1616, respectively.

In a second general embodiment, in order to ultimately form first and second hardmask layers1614and1616, a selective growth process is instead of a DSA approach. In one such embodiment, the material of the first hardmask layer1614is grown above exposed portions of the underlying non-conformal dielectric cap layer1610. A second, different, material of the second hardmask layer1616is grown above exposed portions of underlying second metal lines1612. In an embodiment, the selective growth is achieved by a dep-etch-dep-etch approach for each of the first and second materials, resulting in a plurality of layers of each of the materials. Such an approach may be favorable versus conventional selective growth techniques which can form “mushroom-top” shaped films. The mushroom topping film growth tendency can be reduced through an alternating deposition/etch/deposition (dep-etch-dep-etch) approach. In another embodiment, a film is deposited selectively over the metal followed by a different film selectively over the ILD (or vice versa) and repeated numerous times creating a sandwich-like stack. In another embodiment, both materials are grown simultaneously in a reaction chamber (e.g., by a CVD style process) that grows selectively on each exposed region of the underlying substrate.

As described in greater detail below, in an embodiment, the resulting structure ofFIG. 16Denables improved via shorting margins when fabricating later via layers on the structure ofFIG. 16D. In one embodiment, improved shorting margin is achieved since fabricating a structure with alternating “color” hardmasks reduces the risk of a via shorting to the wrong metal line. In one embodiment, self-alignment is achieved since the alternating color hard masks are self-aligned to the metal trenches beneath. In one embodiment, the need for a metal recess is removed from the processing scheme since which can reduce process variation.

In a first more detailed exemplary process flow,FIGS. 16E-16Pillustrate cross-sectional views of portions of integrated circuit layers representing various operations in another method involving dielectric helmet formation for back end of line (BEOL) interconnect fabrication, in accordance with an embodiment of the present disclosure.

Referring toFIG. 16E, a starting point structure1630is provided following first metal pass processing as a beginning point for fabricating a new metallization layer. The starting point structure1630includes a hardmask layer1634(e.g., silicon nitride) disposed on an inter-layer dielectric (ILD) layer1632. As described below, the ILD layer may be disposed above a substrate and, in one embodiment, is disposed over an underlying metallization layer. First metal lines1636(and, in some cases, corresponding conductive vias1637) are formed in the ILD layer1632. Protruding portions1636A of the metal lines1636have adjacent dielectric spacers1638. A sacrificial hardmask layer1640(e.g., amorphous silicon) is included between neighboring dielectric spacers1638. Although not depicted, in one embodiment, the metal lines1636are formed by first removal of a second sacrificial hardmask material between dielectric spacers1638and then etching of the hardmask layer1634and the ILD layer1632to form trenches which are then filled in a metallization process.

FIG. 16Fillustrates the structure ofFIG. 16Efollowing second pass metal processing up to an including trench etch. Referring toFIG. 16F, sacrificial hardmask layer1640is removed to expose hardmask layer1634. Exposed portions of the hardmask layer1634are removed and trenches1642are formed in the ILD layer1632.

FIG. 16Gillustrates the structure ofFIG. 16Ffollowing sacrificial material fill. A sacrificial material1644is formed in the trenches1642and over the spacers1638and metal lines1636. In an embodiment the sacrificial material1644is formed in a spin-on process, leaving a substantially flat layer, as is depicted inFIG. 16G.

FIG. 16Hillustrates the structure ofFIG. 16Gfollowing a planarization process to re-expose the hardmask layer1634, to remove the dielectric spacers1638, and to remove protruding portions1636A of the metal lines1636. Additionally, the planarization process confined the sacrificial material1644to the trenches1642formed in dielectric layer1632. In an embodiment, the planarization process is performed using a chemical mechanical polishing (CMP) process.

FIG. 16Iillustrates the structure ofFIG. 16Hfollowing sacrificial material removal. In an embodiment, the sacrificial material1644is removed from trenches1642using a wet etch or dry etch process.

FIG. 16Jillustrates the structure ofFIG. 16Ifollowing deposition of a non-conformal dielectric cap layer1646, which may be referred to as a dielectric helmet. In an embodiment, the non-conformal dielectric cap layer1646is formed using a physical vapor deposition (PVD) or chemical vapor deposition (CVD) process such as a plasma-enhanced CVD (PECVD) process. The non-conformal dielectric cap layer1646may be as described above in association with the non-conformal dielectric cap layer1610.

FIG. 16Killustrates the structure ofFIG. 16Jfollowing deposition of a sacrificial cap layer. A sacrificial cap layer1648is formed on upper surfaces of the non-conformal dielectric cap layer1646, and may be implemented to protect the non-conformal dielectric cap layer1646during a subsequent etch or CMP process. In an embodiment, the sacrificial cap layer1648is a titanium nitride (TiN) layer formed by, e.g., PVD or CVD processing.

FIG. 16Lillustrates the structure ofFIG. 16Kfollowing via lithography and etch processing. Select ones of the trenches1638are exposed and subject to an etch process that breaks through the non-conformal dielectric cap layer1646at location1650and extends the trench to provide a via location1652, as was described above.

FIG. 16Millustrates the structure ofFIG. 16Lfollowing second metal line fabrication. In an embodiment, second metal lines1654(and in some cases, associated conductive vias1656) are formed by performing a metal fill and polish process. The polish process may be a CMP process that further removes the sacrificial cap layer1648.

FIG. 16Nillustrates the structure ofFIG. 16Mfollowing directed self-assembly (DSA) or selective growth, e.g., to provide first and second alternating placeholder materials1658and1660(or can be permanent materials, as described in association withFIG. 16D).

FIG. 16Oillustrates the structure ofFIG. 16Nfollowing replacement of the first and second alternating placeholder materials1658and1660with permanent first and second hardmask layers1662and1664, respectively. The processing forFIGS. 16N and 16Omay be as described in association withFIG. 16D.

FIG. 16Pillustrates the structure ofFIG. 16Ofollowing next layer via patterning. An upper ILD layer1666is formed above the first and second hardmask layers1662and1664. An opening1668is formed in the upper ILD layer1666. In one embodiment, the opening1668is formed wider than a via feature size. A select one of the exposed first and second hardmask layers1662and1664locations is selected for selective removal, e.g., by a selective etch process. In this case, a first hardmask1662region is removed selective to exposed portions of the second hardmask layer and1664. A conductive via1670is then formed in the opening1668and in the regions where the first hardmask1662region has been removed. The conductive via1670contacts one of the first metal lines1636. In an embodiment, the conductive via1670contacts one of the first metal lines1636without shorting to one of the adjacent second metal lines1654. In a specific embodiment, a portion1672of the conductive via1670is disposed on a second hardmask layer1664portion without contacting an underlying second metal line1654, as is depicted inFIG. 16P. In an embodiment, then, an improved shorting margin is realized.

In an embodiment, as described in the embodiment above, a first hardmask1662region is removed for via1670fabrication. In this case, forming the opening upon removal of the selected first hardmask1662region further requires etching through an uppermost portion of the non-conformal dielectric cap layer1646. In another embodiment, however, a second hardmask1664region is removed for via1670fabrication. In this case, forming the opening upon removal of such a selected second hardmask1664region directly exposes the metal line1654to which the via1670is connected.

In a second more detailed exemplary process flow, involving a via etch first approach,FIGS. 17A-17Jillustrate cross-sectional views of portions of integrated circuit layers representing various operations in another method involving dielectric helmet formation for back end of line (BEOL) interconnect fabrication, in accordance with an embodiment of the present disclosure.

Referring toFIG. 17A, a starting point structure1700is provided following first metal pass processing as a beginning point for fabricating a new metallization layer. The starting point structure1700includes a hardmask layer1704(e.g., silicon nitride) disposed on an inter-layer dielectric (ILD) layer1702. As described below, the ILD layer may be disposed above a substrate and, in one embodiment, is disposed over an underlying metallization layer. First metal lines1706(and, in some cases, corresponding conductive vias1707) are formed in the ILD layer1702. Protruding portions1706A of the metal lines1706have adjacent dielectric spacers1708. A sacrificial hardmask layer1710(e.g., amorphous silicon) is included between neighboring dielectric spacers1708. Although not depicted, in one embodiment, the metal lines1706are formed by first removal of a second sacrificial hardmask material between dielectric spacers1708and then etching of the hardmask layer1704and the ILD layer1702to form trenches which are then filled in a metallization process.

FIG. 17Billustrates the structure ofFIG. 17Afollowing second pass metal processing up to an including trench and via location etch. Referring toFIG. 17B, sacrificial hardmask layer1710is removed to expose hardmask layer1704. Exposed portions of the hardmask layer1704are removed and trenches1712are formed in the ILD layer1702. Additionally, in an embodiment, via locations1722are formed in select locations using a via lithography and etch process, as is depicted inFIG. 17B.

FIG. 17Cillustrates the structure ofFIG. 17Bfollowing sacrificial material fill. A sacrificial material1714is formed in the trenches1712and over the spacers1708and metal lines1706. In an embodiment the sacrificial material1714is formed in a spin-on process, leaving a substantially flat layer, as is depicted inFIG. 17C.

FIG. 17Dillustrates the structure ofFIG. 17Cfollowing a planarization process to re-expose the hardmask layer1704, to remove the dielectric spacers1708, and to remove protruding portions1706A of the metal lines1706. Additionally, the planarization process confined the sacrificial material1714to the trenches1712formed in dielectric layer1702. In an embodiment, the planarization process is performed using a chemical mechanical polishing (CMP) process.

FIG. 17Eillustrates the structure ofFIG. 17Dfollowing partial removal of the sacrificial material1714to provide recessed sacrificial material1715. In an embodiment, the sacrificial material1714is recessed within trenches1712using a wet etch or dry etch process. The recessed sacrificial material1715may be retained at this point to protect a metal layer underlying via location1722.

FIG. 17Fillustrates the structure ofFIG. 17Efollowing deposition of a non-conformal dielectric cap layer1716, which may be referred to as a dielectric helmet. In an embodiment, the non-conformal dielectric cap layer1716is formed using a physical vapor deposition (PVD), a selective growth process, or a chemical vapor deposition (CVD) process such as a plasma-enhanced CVD (PECVD) process. The non-conformal dielectric cap layer1716may be as described above in association with the non-conformal dielectric cap layer1710. Alternatively, the non-conformal dielectric cap layer1716may only include upper portions1716A, with essentially no portion of the non-conformal dielectric cap layer1716being formed in trenches1712, as is depicted inFIG. 17F.

FIG. 17Gillustrates the structure ofFIG. 17Ffollowing second metal line fabrication. In an embodiment, second metal lines1724(and in some cases, associated conductive vias1726) are formed by performing a metal fill and polish process subsequent to removal of the recessed sacrificial material1715. The polish process may be a CMP process.

FIG. 17Hillustrates the structure ofFIG. 17Gfollowing directed self-assembly (DSA) or selective growth, e.g., to provide first and second alternating placeholder materials1728and1730(or can be permanent materials, as described in association withFIG. 16D).

FIG. 17Iillustrates the structure ofFIG. 17Hfollowing replacement of the first and second alternating placeholder materials1728and1730with permanent first and second hardmask layers1732and1734, respectively. The processing forFIGS. 17H and 31may be as described in association withFIG. 16D.

FIG. 17Jillustrates the structure ofFIG. 17Ifollowing next layer via patterning. An upper ILD layer1736is formed above the first and second hardmask layers1732and1734. An opening1738is formed in the upper ILD layer1736. In one embodiment, the opening1738is formed wider than a via feature size. A select one of the exposed first and second hardmask layers1732and1734locations is selected for selective removal, e.g., by a selective etch process. In this case, a first hardmask1732region is removed selective to exposed portions of the second hardmask layer and1734. A conductive via1740is then formed in the opening1738and in the regions where the first hardmask1732region has been removed. The conductive via1740contacts one of the first metal lines1706. In an embodiment, the conductive via1740contacts one of the first metal lines1706without shorting to one of the adjacent second metal lines1724. In a specific embodiment, a portion1742of the conductive via1740is disposed on a second hardmask layer1734portion without contacting an underlying second metal line1724, as is depicted inFIG. 17J. In an embodiment, then, an improved shorting margin is realized.

In an embodiment, as described in the embodiment above, a first hardmask1732region is removed for via1740fabrication. In this case, forming the opening upon removal of the selected first hardmask1732region further requires etching through an uppermost portion of the non-conformal dielectric cap layer1716. In another embodiment, however, a second hardmask1734region is removed for via1740fabrication. In this case, forming the opening upon removal of such a selected second hardmask1734region directly exposes the metal line1724to which the via1740is connected.

Referring again toFIGS. 16P and 17J, by cross-section analysis, a dielectric helmet can be viewed over half the metal populations. Additionally, hardmasks of different materials are self-aligned to the dielectric helmet. Such structures may include one or more of a conductive via with improved shorting margin, alternating hardmask materials, the presence of a dielectric helmet. A resulting structure such as described in association withFIG. 16P or 17Jmay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structures ofFIG. 16P or 17Jmay represent the final metal interconnect layer in an integrated circuit. It is to be appreciated that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed.

In accordance with an embodiment of the present disclosure, pattern accumulation layers for vias and plugs are described. One or more embodiments described herein are directed to process schemes for via critical dimension (CD) control. Embodiments may include improvements related to via CD control, via CD uniformity, edge placement error (EPE), via self-alignment. Embodiments may improve edge placement error (EPE) in semiconductor patterning of vias and may enable self-alignment of multiple via lithography passes. In an embodiment, all via edges are defined with gratings instead of standard resist edges. A sacrificial grating is created beneath the via resist in the same direction as the metal the vias are landing on. Vias are patterned with standard photoresist. However, during subsequent etches through the sacrificial grating and the grating of a self-aligned via (SAV) metal grating (e.g., two crossed gratings), all via edges are defined by the gratings. In an embodiment, no variability from the via resist edge is transferred into the substrate, and the resulting process capability enables better control of via CDs and improves yields and process capability.

To provide context for embodiments described below, currently known solutions involve the use of a resist edge to define a via edge which determines the shorting margin to the metal below. However, standard via resist patterning is known to have much higher edge placement error than grating patterning. By contrast, in accordance with embodiments described herein, by using a sacrificial grating to define via edge provides much improves control of the via edge, and the risk of shorting to the wrong metal is greatly improved.

In accordance with embodiments described herein, a pattern accumulation flow is described for multiple via patterns with a sacrificial grating in the stack to define via edges post etch. A “sieve” stack is built by coating a hardmask on a patterned upper metal (M1) inter-layer dielectric layer with plugs already present. The hardmask planarizes the wafer for subsequent processing. The next layer formed may be used as an etch stop, followed by formation of an accumulation layer. At this stage, a grating may be created at twice the pitch of the underlying lower metal (M0) layer and in the same direction as the M0 grating. This grating effectively blocks every other M0 lines below and ultimately defines the critical dimension (CD) of the via post etch. In an embodiment, since the grating is twice the pitch of the underlying M0, a substantial amount of hardmask (+/−20 nm) between vias is included to allow for edge placement error (EPE) of an overlying resist feature.

Next, multiple via mask patterns are accumulated through a grating and in an accumulation layer. After accumulation, the grating is inverted without an extra lithography operation in order to expose other lower metal (M0) lines and protect the vias which have already created. A liner is added between gratings to ensure vias on adjacent M0 lines do not merge. Spacing between vias can be modulated with the thickness of the liner.

Finally, the via patterns from one to several via masks can be accumulated through the inverted grating to complete patterning in the accumulation of all drawn vias. The grating is then removed and the accumulated via pattern in the accumulation layer is etched down through the upper metal (M1) hardmask grating into the inter-layer dielectric below the M1 lines and to the M0 below. The stack above the M1 grating and the overlying hardmask layer are removed. Subsequently, trenches and vias are metallized and then polished. The result is very good CD control of the formed vias in both directions, and self-alignment of all the vias to one another.

In an aspect, then, one or more embodiments described herein are directed to an approach that employs an underlying metal grating structure, or a pair of orthogonal such structures, as a template to build overlying conductive vias. In an exemplary processing scheme,FIGS. 18A-18Willustrate plan views (upper portions of Figures) and corresponding angled (middle portions of Figures) and cross-sectional views (lower portions of Figures) representing various operations in a metal via processing schemes for back end of line (BEOL) interconnects, in accordance with an embodiment of the present disclosure.

Referring toFIG. 18A, a starting point structure1800is provided as a beginning point for fabricating a new metallization layer. The starting point structure1800includes an array of alternating metal lines1802and dielectric lines1804. The metal lines1802have upper surfaces that are approximately co-planar with upper surfaces of the dielectric lines1804. An etch stop layer1806is then formed on the starting structure1800, as is depicted inFIG. 18B.

Referring toFIG. 18C, an inter-layer dielectric layer1808is formed on the structure ofFIG. 18B. A patterned hardmask1810is then formed on the structure ofFIG. 18C, and the pattern of the patterned hardmask1810is transferred partially into the inter-layer dielectric layer1808to form patterned inter-layer dielectric layer1812having metal line regions1814formed therein, as is depicted inFIG. 18D. In an embodiment, the patterned hardmask1810has a grating type pattern, as is depicted. In a specific embodiment, the patterned hardmask1810is composed of titanium nitride (TiN).

Referring toFIG. 18E, a hardmask layer1816is formed on the structure ofFIG. 18D. In an embodiment, the bottom surface of the hardmask layer1816is conformal with the topography of the structure ofFIG. 18D, while the upper surface of the hardmask layer1816is planarized. In a specific embodiment, the hardmask layer1816is a carbon hardmask (CHM) layer. An etch stop layer1818is then formed on the structure ofFIG. 18E, as is depicted inFIG. 18F. In a specific embodiment, the etch stop layer1818is composed of silicon oxide (SiOx or SiO2).

Referring toFIG. 18G, a pattern accumulation layer1820is then formed on the structure ofFIG. 18F. In an embodiment, the pattern accumulation layer1820is a layer in which more than one pattern will ultimately accumulate, e.g., for eventual via patterning. In a specific embodiment, the pattern accumulation layer1820is composed of amorphous silicon (a-Si). A patterned hardmask1822is then formed on the structure ofFIG. 18G, as is depicted inFIG. 18H. In an embodiment, the patterned hardmask1822has a grating type pattern, as is depicted. In one such embodiment, the grating type pattern is orthogonal to the grating of patterned hardmask1810and parallel to the grating of the metal lines1802. However, in an embodiment, from a top down perspective, the patterned hardmask1822exposes only every other of the metal lines1802(e.g., metal line1802(A)) and blocks alternating ones of the metal lines1802(e.g., metal line1802(B)), as is depicted inFIG. 18H. In a specific embodiment, the patterned hardmask1822is composed of silicon nitride (SiN).

Referring toFIG. 18I, a hardmask1824is then formed on the structure ofFIG. 18H. In a specific embodiment, the hardmask1824is a carbon hardmask (CHM). The hardmask1824is then patterned (e.g., by a lithographic process using single or multiple layer resist structures) and the pattern is transferred into portions of the pattern accumulation layer1820exposed by the patterned hardmask1822to form a once patterned memory layer1826, as is depicted inFIG. 18J. In an embodiment, the pattern is transferred into portions of the pattern accumulation layer1820by an etch process that uses etch stop layer1818as a terminating point. In an embodiment, subsequent to forming the once patterned memory layer1826, the hardmask1824is removed, as is also depicted inFIG. 18J. It is to be appreciated that the process may be repeated for several different masking operations.

Referring toFIG. 18K, a blocking line1828is then formed by filling the opening in patterned hardmask1822of the structure ofFIG. 18Jwith a blocking material layer. In a specific embodiment, the blocking material layer is a flowable silicon oxide material. In other embodiments, the blocking material layer is any of a number of other suitable materials. The patterned hardmask1822is then removed from the structure ofFIG. 18Kto leave the blocking line1828remaining, as is depicted inFIG. 18L.

Referring toFIG. 18M, an insulating spacer forming material layer1830is then formed on the structure ofFIG. 18L, conformal with the blocking line1828. In an embodiment, the insulating spacer forming material layer1830is composed of a dielectric material. In one embodiment, the spacer forming material layer1830is composed of silicon oxide (SiOx or SiO2). The spacer forming material layer1830is then patterned to form spacers1832adjacent the sidewalls of the blocking line1828, as is depicted inFIG. 18N. In an embodiment, the spacer forming material layer1830is patterned to form spacers1832using an anisotropic dry etch process.

Referring toFIG. 18O, a collective pattern of the blocking line1828, the spacers1832, and protective regions of a patterning mask formed subsequent to forming the spacers1832is then transferred into the once patterned memory layer1826to form a twice patterned memory layer1834. In an embodiment, the pattern is transferred into the once patterned memory layer1826by an etch process that uses etch stop layer1818as a terminating point. The blocking line1828, the spacers1832, and any additional mask material of the structure ofFIG. 18Oare then removed to expose the twice patterned memory layer1834, as is depicted inFIG. 18P.

Referring toFIG. 18Q, the pattern of the twice patterned memory layer1834of the structure ofFIG. 18Pis then transferred to the etch stop layer1818to form patterned etch stop layer1836and to expose portion of the hardmask layer1816. In one embodiment, the pattern of the twice patterned memory layer1834is transferred to the etch stop layer1818using a dry etch process. The twice patterned memory layer1834of the structure ofFIG. 18Qis then removed, as is depicted inFIG. 18R.

Referring toFIG. 18S, the pattern of the patterned etch stop layer1836of the structure ofFIG. 18Ris then transferred into the hardmask layer1816to form patterned hardmask layer1838. Patterned hardmask layer1838exposes portions of the line regions1814of the patterned inter-layer dielectric layer1812and portions of the patterned hardmask1810. That is, although the patterned hardmask layer1838exposes areas wider than the line regions1814of the patterned inter-layer dielectric layer1812, the patterned hardmask1810protects “exposed” regions of the patterned inter-layer dielectric layer1812outside of the line regions1814. The pattern of the patterned hardmask layer1838of the structure ofFIG. 18Sis then transferred to the patterned inter-layer dielectric layer1812to form twice patterned inter-layer dielectric layer1840and to expose etch stop layer1806, as is depicted inFIG. 18T. However, in an embodiment, the patterned hardmask1810inhibits total transfer pattern, as is also depicted inFIG. 18T. In one embodiment, the pattern of the patterned hardmask layer1838is transferred to the patterned inter-layer dielectric layer1812by an etch process that uses etch stop layer1806as a terminating point.

Referring toFIG. 18U, exposed portions of the etch stop layer1806of the structure ofFIG. 18Tare removed to form patterned etch stop layer1842and to expose via locations1844for metal lines1802. The patterned etch stop layer1836, the patterned hardmask layer1838, and the patterned hardmask1810of the structure ofFIG. 18Uare then removed, as is depicted inFIG. 18V. The removal exposes twice patterned inter-layer dielectric layer1840and via locations1844for metal lines1802, as well as locations1846for upper metal lines. In an embodiment, the patterned etch stop layer1836, the patterned hardmask layer1838, and the patterned hardmask1810are removed using a selective wet etch process.

Referring toFIG. 18W, an upper metallization layer is formed for the structure ofFIG. 18V. In particular, a metal fill process is performed to provide metal vias1848and metal lines1850. In an embodiment, the metal fill process is performed using a metal deposition and subsequent planarization processing scheme, such as a chemical mechanical planarization (CMP) process. In an embodiment, the surface of the structure formed ofFIG. 18Wis substantially the same as the surface of, although orthogonal to, the starting structure1800ofFIG. 18A. Thus, in an embodiment, the process described in association withFIGS. 18B-18Wmay be repeated on the structure ofFIG. 18Wto form a next metallization layer, and so on.

A resulting structure such as described in association withFIG. 18Wmay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 18Wmay represent the final metal interconnect layer in an integrated circuit. It is to be appreciated that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed. It is also to be appreciated that the above examples have focused on via/contact formation. However, in other embodiments, similar approaches may be used to preserve or form regions for line end termination (plugs) within a metal line layer.

In accordance with an embodiment of the present disclosure, grid-based via and plug patterning approaches are described. One or more embodiments described herein are directed to grid self-aligned and super self-aligned metal via processing schemes. Embodiments described herein may be implemented to provide self-alignment methodology for metal/via layers. Almost all plug and via geometries are made possible by implementing approaches described herein. Additionally, the final via critical dimension (CD) may be independent from the lithography implemented for patterning. Furthermore, approaches described herein may provide a “circular flow” in that the end of the process flow has an identical or substantially identical layer stack and layout as the beginning of the process flow. Thus, once every operation in the process flow is developed, the process flow can be repeated as many times as needed to add as many metal/via layers as required. In one or more embodiments, overlap between perpendicular grids is used to define placement of vias and metal lines. The size of the via may be determined by the overlapped areas between two grids.

To provide context for embodiments described below, as compared with currently known approaches for via self-alignment, approaches described herein may provide for almost any plug and via placement available. Approaches described herein may require fewer selective etches. Approaches described herein may provide for final plug and via CDs that are independent of the lithography utilized. In an aspect, then, one or more embodiments described herein are directed to an approach that employs an underlying metal grating structure as a template to build overlying conductive vias. It is to be appreciated that similar approaches may be implemented to fabricate non-conductive spaces or interruptions between metals (plugs).

In an exemplary processing scheme,FIGS. 19A-19Lillustrate plan views (upper portions of Figures) and corresponding angled cross-sectional views (lower portions of Figures) representing various operations in a grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects, in accordance with an embodiment of the present disclosure. It is to be appreciated that, although in reality they are not, different metallization layers are shown as separated (upper and lower) in the angled cross-sectional views for clarity.

Referring toFIG. 19A, a starting point structure1900is provided as a beginning point for fabricating a new metallization layer. The starting point structure1900includes an array of alternating metal lines1902and dielectric lines1904. The metal lines1902are recessed below the dielectric lines1904. A hardmask layer1906is disposed above the metal lines1902, and alternating with the dielectric lines1904. In an embodiment, the dielectric lines1904are composed of silicon nitride (SiN), and the hardmask layer1906is composed of silicon carbide (SiC) or silicon oxide (SiO2). A next patterning layer1908is then fabricated above the starting point structure1900, as is depicted inFIG. 19B. In an embodiment, the next patterning layer1908includes an etch stop layer1910, a dielectric layer1912and a grating structure1914. In an embodiment, the etch stop layer1910is composed of silicon oxide (SiO), the dielectric layer1912is composed of silicon nitride (SiN), and the grating structure1914is composed of silicon oxide (SiO). In an embodiment, the grating structure1914is formed using a pitch halving or pitch quartering scheme, e.g., by spacer patterning.

Referring toFIG. 19C, the pattern of the grating structure1914is transferred to the dielectric layer1912to form patterned dielectric layer1916. In an embodiment, the pattern of the grating structure1914is transferred to the dielectric layer1912using an etch process that utilizes etch stop layer1910as an end-point for the etch process. A breakthrough etch is then performed to remove exposed portions of the etch stop layer1910to form patterned etch stop layer1918, as is depicted inFIG. 19D. In an embodiment, the breakthrough etch reveals all possible via locations1920that could potentially be formed into structure1900.

Referring toFIG. 19E, plug patterning is then performed by forming a patterned hard mask1922on the structure ofFIG. 19Din locations where plugs are to be preserved. A unified pattern of the patterned hard mask1922and the grating structure1914is then transferred into structure1900to form structure1900′ having regions1924for metal line formation within structure1900, as is depicted inFIG. 19F. In an embodiment, the unified pattern of the patterned hard mask1922and the grating structure1914is transferred into structure1900using an etch process. Such an etch process may etch both the layers1904and1906at substantially the same rate (or may be performed as several etch operations) and may be followed by a cleans process to remove the patterned hard mask1922, as is also depicted inFIG. 19F.

Referring toFIG. 19G, via patterning is then performed by forming a patterned lithographic mask1926on the structure ofFIG. 19F, the patterned lithographic mask1926exposing locations where vias are to be formed (e.g., a via selection process). A unified pattern of the patterned lithographic mask1926and the grating structure1914is then transferred into structure1900′ to form structure1900″ having regions1928for metal via formation within structure1900′, as is depicted inFIG. 19H. In an embodiment, the unified pattern of the patterned lithographic mask1926and the grating structure1914is transferred into structure1900′ using an etch process. Such an etch process may etch the layer1906selective to the layer1904, and may be followed by a cleans process to remove the patterned lithographic mask1926, as is also depicted inFIG. 19H.

Referring toFIG. 19I, a metal fill process is performed on the structure ofFIG. 19Ito provide underlying structure1930. The metal fill process forms metal vias1932and metal lines1934in structure1930. The metal fill process may also fill the regions between the grating structure1914with metal lines1936, as is depicted inFIG. 19I. In an embodiment, the metal fill process is performed using a metal deposition and subsequent planarization processing scheme. The structure ofFIG. 19Imay then be reduced in thickness to remove the grating structure1914, to expose the patterned dielectric1916and top provide metal lines1938, which are reduced in thickness from metal lines1936, as is depicted inFIG. 19J. In an embodiment, structure ofFIG. 19Imay then be reduced in thickness using a planarization process such as a chemical mechanical planarization (CMP) process.

Referring toFIG. 19K, metal lines1938are removed from the structure ofFIG. 19Jto leave patterned dielectric layer1916and patterned etch stop layer1918. The metal lines1938may be removed by a selective etch process that removes the metal lines1938and also ensures that no metal is left to remain at a height above the material layer1904and1906(i.e., such that no metal remains above the plug regions of structure1930). A hardmask layer1940is then formed on the structure ofFIG. 19K, between the lines of patterned dielectric layer1916, as is depicted inFIG. 19L. In an embodiment, the hardmask layer1940is composed of silicon carbide (SiC) or silicon oxide (SiO2) and is formed using a deposition and planarization processing scheme. In one embodiment, the hardmask layer1940is composed of the same material as the hardmask layer1906. In an embodiment, the surface of the structure formed from patterned dielectric layer1916and the hardmask layer1940is substantially the same as the surface of, although orthogonal to, the starting structure1900ofFIG. 19A. Thus, in an embodiment, the process described in association withFIGS. 19B-19Lmay be repeated on the structure ofFIG. 19Lto form a next metallization layer, and so on.

It is to be appreciated that the process described in association withFIGS. 19B-19Las repeated on the structure ofFIG. 19Lto form a next metallization layer may be referred to as a circular flow in that the end of the process flow has an identical or substantially identical layer stack and layout as the beginning of the process flow. In one embodiment, forming an additional metallization layer includes using such a circular flow. However, it is also to be appreciated that a circular or repetitive flow may only be implemented for select metallization layers. Other metallization layers in a resulting stack (e.g., layers above or below or in between layers fabricated using the processing scheme ofFIGS. 19B-19L) may be fabricated using convention dual damascene or other approaches.

A resulting structure such as1931described in association withFIG. 19Lmay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure1931ofFIG. 19Lmay represent the final metal interconnect layer in an integrated circuit. It is also to be appreciated that, in subsequent fabrication operations, the dielectric lines may be removed to provide air gaps between the resulting metal lines. It is to be appreciated that the above examples have focused on via/contact formation. However, in other embodiments, similar approaches may be used to preserve or form regions for line end termination (plugs) within a metal line layer.

In accordance with an embodiment of the present disclosure, grating-based via and plug patterning is described. One or more embodiments described herein are directed to grating based plugs and cuts for feature end formation. Embodiments may involve one or more of lithography patterning, associated line-end CD yield, and spacer-based patterning. Embodiments employ methods to create plugs and cuts with placement control and uniformity of one dimensional (1D) features. It is to be appreciated that there is trade-off between better control for line ends (plugs) or via placements with the implication that via and line ends are placed at more restricted locations.

To provide context for embodiments described herein, in order to enable patterning tighter pitch features in semiconductor manufacturing, grating and plug or grating and cut approaches are being applied to more layers. As feature dimensions continue to shrink, the ability to robustly pattern cuts and plugs can limit scaling and yield. Cut and plug features are generally defined directly by a lithographic operation with primarily two dimensional (2D) features. Such 2D features have much higher variation and non-uniformity than one dimensional (1D) features.

With respect toFIGS. 20A-20Gdescribed below, in an embodiment, an overview of a simplified patterning process to generate grating defined plugs is presented. A sacrificial 1D pattern is generated orthogonal to a primary direction of a layer being patterned. A selection mask is then used to cut or keep the portions of the 1D pattern that will ultimately be used to cut or keep portions of the primary grating. The final edges of the cut/keep on the primary pattern are thus defined by edges of the 1D sacrificial grating, with much better control and uniformity.FIGS. 20A-20Gillustrate plan views (upper) and corresponding cross-sectional views (middle and lower) representing various operations in a method of fabricating grating based plugs and cuts for feature end formation for back end of line (BEOL) interconnects, in accordance with an embodiment of the present disclosure.

Referring toFIG. 20A, a starting point structure2000is provided as a beginning point for fabricating a new metallization layer. The starting point structure2000includes an interlayer dielectric (ILD) material layer2002having a first hardmask layer2004formed thereon. A second hardmask layer2006is formed on the first hardmask layer2004. The second hardmask layer2006has a grating pattern, which may be viewed as a primarily one dimensional (1D) grating pattern. In an embodiment, the grating pattern of the second hardmask2006is ultimately used to define 1D locations of the final layer to be patterned but does not yet have the end of feature positions patterned therein. First hardmask layer2004and/or second hardmask layer2006may be fabricated from a material such as, but not limited to, silicon nitride (SiN), silicon oxide (SiO2), titanium nitride (TiN), or silicon (Si). In one embodiment, first hardmask layer2004and second hardmask layer2006are fabricated from different materials from one another.

Referring toFIG. 20B, a third hardmask layer2008is formed on the structure ofFIG. 20A. In an embodiment, the third hardmask layer2008has a grating pattern, which may be viewed as a primarily one dimensional (1D) grating pattern orthogonal to the 1D grating pattern of the second hardmask layer2006. The third hardmask layer2008may be fabricated from a material such as, but not limited to, silicon nitride (SiN), silicon oxide (SiO2), titanium nitride (TiN), or silicon (Si). In one embodiment, the third hardmask layer2008is fabricated from a material different than the materials of the first hardmask layer2004and the second hardmask layer2006. It is to be appreciated that any one of the hardmask layers described above may actually include a plurality of sublayers, e.g., to provide improved etch selectivity.

In an embodiment, the grating pattern of the third hardmask layer2008and the grating pattern of the second hardmask layer2006together define all allowed line end locations for a metal line metallization layer. In one such embodiment, the grating pattern of the third hardmask layer2008and the grating pattern of the second hardmask layer2006together define line end locations at locations where the lines of the grating patterns overlap. In another such embodiment, the grating pattern of the third hardmask layer2008and the grating pattern of the second hardmask layer2006together define line end locations at locations where spaces are exposed between lines of the grating patterns.

Referring toFIG. 20C, regions of a lithographic patterning mask2010are formed on the structure ofFIG. 20B. The regions of the lithographic patterning mask2010may be formed from a photo-resist layer or layers, or like lithographic patterning mask. In an embodiment, the regions of the lithographic patterning mask2010provide a pattern of cut/keep regions on the sacrificial grating formed from the second hardmask layer2006and the third hardmask layer2008. In an embodiment, then, a lithography process is used to select (cut or keep) portions of the sacrificial grating which will eventually define the end locations of a primary pattern of metal lines. In one such embodiment, 193 nm or EUV lithography is used together with an etch transferring of the resist pattern into underlying layers prior to etching the sacrificial grating pattern. In one embodiment, the lithographic process involves multiple exposures of resist layers or deposition/etch/deposition repetitive processing. It is to be appreciated that the masked regions may be referred to as cutting or keeping locations, where the orthogonal grating overlap regions or spaces between gratings are used to define plug (or perhaps via) locations.

Referring toFIG. 20D, using the regions of the lithographic patterning mask2010of the structure ofFIG. 20Cas a mask, the third hardmask layer2008is selectively etched to form patterned hardmask layer2012. That is, a portion of the sacrificial grating is etched to take on portions of the pattern of the regions of the lithographic patterning mask2010that protect portions of the third hardmask layer2008from an etching process. In an embodiment, the portions of the third hardmask layer2008that are removed in the etch process are not part of the final target design. In an embodiment, the regions of the lithographic patterning mask2010are removed subsequent to forming the patterned hardmask layer2012, as is depicted inFIG. 20D.

Referring toFIG. 20E, a combined pattern formed the second hardmask layer2006and the patterned hard mask layer2012of the structure ofFIG. 20Dis transferred into the first hardmask layer2004and into the ILD material layer2002, e.g., by a selective etch process. The patterning forms a patterned ILD layer2014and a patterned hardmask layer2016.

Referring toFIG. 20F, the patterned hard mask layer2012and the second hardmask layer2006(i.e., the sacrificial grating) of the structure ofFIG. 20Eis then removed. The patterned hardmask layer2016may be retained at this stage, as is depicted inFIG. 20F, or may be removed. Selective wet or dry processing techniques can be employed for removal of the patterned hard mask layer2012and the second hardmask layer2006(and, possibly, the patterned hardmask layer2016). It is to be appreciated that the resulting structure ofFIG. 20Fcan subsequently be used as a starting point for metal fill with the option of first removing the remaining patterned hardmask layer2016. The end locations (line ends) of what will be metal features are defined by the edges of the 1D sacrificial grating transferred in to the ILD material layer2002and, hence, are well controlled.

Referring toFIG. 20G, a metal fill process is performed on the structure ofFIG. 20Fto form metal lines2018in the openings patterned ILD layer2014. The metal lines have lines ends formed by the breaks in continuity formed in the patterned ILD layer2014. In an embodiment, the metal fill process is performed by depositing and then planarizing one or more metal layers over the patterned ILD layer2014. The patterned hardmask layer2016may be retained during the metal deposition process and then removed during the planarization process, as is depicted inFIGS. 20F and 20G. However, in other embodiments, the patterned hardmask layer2016is removed prior to the metal fill process. In still other embodiments, the patterned hardmask layer2016is retained in the final structure. Referring again toFIG. 20G, it is to be appreciated that the metal lines2018may be formed over underlying features, such, as conductive via2020shown as an example.

A resulting structure such as described in association withFIG. 20Gmay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 20Gmay represent the final metal interconnect layer in an integrated circuit. It is to be appreciated that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed. In an embodiment, offset due to conventional lithograph/dual damascene patterning that must otherwise be tolerated, is not a factor for the resulting structures described herein. It is to be appreciated that the above examples have focused on line end/plug/cut formation or preservation. However, in other embodiments, similar approaches may be used to form vias/contacts above or below a metal line layer. It is also to be appreciated that, in subsequent fabrication operations, the dielectric lines may be removed to provide air gaps between the resulting metal lines.

Referring again toFIGS. 20A-20G, in an embodiment, a patterning process to generate grating defined plugs has been described. The advantages of such an embodiment may include better dimensional control of end-to-end features that reduces the probability of end-to-end shorting (yield failure) otherwise observed under conditions of worst case process variation. Improved dimensional control of end-to-end features provides more area under worse case process variation for via landing and coverage. Accordingly, in an embodiment, improved electrical connection may be achieved from layer to layer, with increased yield and product performance. Improved dimensional control of end-to-end features can enable smaller end-to-end widths and, therefore, better product density (cost per functionality) may be achieved.

In embodiment, an advantage of embodiments of the present disclosure is that all the line-end locations are defined by a single lithography operation. For example, when plug/cut pitches become very small the common solution is to use multiple passes of lithography with additional processing to generate a composite plug/cut pattern. By contrast, in embodiments described herein, the feature-end locations are a function of multiple lithography operations and, hence, have larger variation than when a single lithography operation is used to define the feature-end as is the case with embodiments described herein.

In accordance with an embodiment of the present disclosure, line end cutting approaches are described. One or more embodiments described herein are directed to techniques for patterning metal line ends. Embodiments may include aspects of one or more of contact fabrication, damascene processing, dual damascene processing, interconnect fabrications, and metal line trench patterning.

To provide context, in the advanced nodes of semiconductor manufacturing, the low level interconnects are created by separate patterning processes of the line grating, line ends, and vias. The fidelity of the composite pattern tends to degrade as the vias encroach upon the line ends and vice-versa. Embodiments described herein provide for a line end process also known as a plug process that eliminates associated proximity rules. Embodiments may allow for a via to be placed at the line end and a large via to strap across a line end.

To provide further context,FIG. 21Aillustrates a plan view and corresponding cross-sectional view taken along the a-a′ axis of the plan view of a metallization layer of a conventional semiconductor device.FIG. 21Billustrates a cross-sectional view of a line end or plug fabricated using a currently known processing scheme.FIG. 21Cillustrates another cross-sectional view of a line end or plug fabricated using a currently known processing scheme.

Referring toFIG. 21A, a metallization layer2100includes metal lines2102formed in a dielectric layer2104. The metal lines2102may be coupled to underlying vias2103. The dielectric layer2104may include line end or plug regions2105. Referring toFIG. 21B, a conventional line end or plug region2105of a dielectric layer2104may be fabricated by patterning a hardmask layer2110on the dielectric layer2104and then etching exposed portions of the dielectric layer2104. The exposed portions of the dielectric layer2104may be etched to a depth suitable to form a line trench2106or further etched to a depth suitable to form a via trench2108. Referring toFIG. 21C, two vias adjacent opposing sidewalls of the line end or plug2105may be fabricated in a single large exposure2116to ultimately form line trenches2112and via trenches2114.

However, referring again toFIGS. 21A-21C, fidelity issues and/or hardmask erosion issues may lead to imperfect patterning regimes. By contrast, one or more embodiments described herein include implementation of a process flow involving construction of a line end dielectric (plug) after a trench and via patterning process. In a an exemplary processing scheme,FIGS. 21D-21Jillustrate cross-sectional views representing various operations in a process for patterning metal line ends for back end of line (BEOL) interconnects, in accordance with an embodiment of the present disclosure.

Referring toFIG. 21D, a method of fabricating a metallization layer of an interconnect structure for a semiconductor die includes forming a line trench2128in an upper portion (above a lower portion2130) of an interlayer dielectric (ILD) material layer2126formed above an underlying metallization layer2120. The underlying metallization layer2120includes metal lines2122disposed in a dielectric layer2124.

Referring toFIG. 21E, via trenches2132A and2132B are formed in the lower portion2130of the ILD material layer2126to form a patterned lower portion2130′ of the ILD material layer2126. As an exemplary embodiment, the via trench2132A exposes two metal lines2122of the underlying metallization layer2120, while the via trench2132B exposes one metal line2122of the underlying metallization layer2120.

Referring toFIG. 21F, a sacrificial material2134, such as a matrix material, is formed above the ILD material layer (portions2130′ shown inFIG. 21F) and in the line trench2128and the via trenches2132A and2132B. In an embodiment, a patterned hardmask layer2136is formed on the sacrificial material2134, as is depicted inFIG. 21F.

Referring toFIG. 21G, the sacrificial material2134is patterned to form an opening (left-hand side opening ofFIG. 21G) exposing a portion of the lower metallization layer2120between the two metal lines2122of the underlying metallization layer2120associated with via trench2132A ofFIG. 21E. In the exemplary embodiment shown, the sacrificial material2134is further patterned to form an opening (right-hand side opening ofFIG. 21G) exposing a portion of the patterned lower portion2130′ of the ILD material layer adjacent via trench2132B ofFIG. 2E. In an embodiment, the sacrificial material2134is patterned by transferring the pattern of patterned hardmask2136to the sacrificial material2134by an etch process.

Referring toFIG. 21H, the openings of the sacrificial material2134(now shown as patterned and filled sacrificial material2134′) are filled with a dielectric material2138. In one embodiment, the openings of the sacrificial material2134are filled with the dielectric material2138using a deposition process selected form the group consisting of atomic layer deposition (ALD) and chemical vapor deposition (CVD). In one embodiment, the openings of the sacrificial material2134are filled with the dielectric material2138of a first dielectric material composition. In one such embodiment, the ILD material layer2126includes a second dielectric material composed of a different material than the first dielectric material composition. In another such embodiment, however, the ILD material layer2126is composed of the first dielectric material.

Referring toFIG. 21I, the filled sacrificial material2134′ is removed to provide dielectric plugs2140A and2140B. In the exemplary embodiment shown, dielectric plug2140A is disposed on the portion of the lower metallization layer2120between the two metal lines2122of the underlying metallization layer2120. Dielectric plug2140A is adjacent a via trench2132A and line trench2128′ and, in the case shown inFIG. 21, is between essentially symmetric via trenches2132A and line trenches2128′. Dielectric plug2140B is disposed on a portion of the patterned lower portion2130′ of the ILD material layer2126. Dielectric plug2140B neighbors a via trench2142B and corresponding line trench (right-hand side of dielectric plug2140B). In an embodiment, the structure ofFIG. 21His subjected to a planarization process used to remove overburden regions (regions above and over surfaces on either side of the trench) of the dielectric material2138, to remove the patterned hardmask2136, and to reduce a height of the sacrificial material2134′ and the portions of the dielectric material2138therein. The sacrificial material2134′ is then removed by using a selective wet or dry processing etch technique.

Referring toFIG. 21J, the line trenches2128′ and the via trenches2132A and2132B are filled with a conductive material. In one embodiment, filling the line trenches2128′ and the via trenches2132A and2132B with the conductive material forms metal lines2142and conductive vias2144in a patterned dielectric layer2130′. In an exemplary embodiment, referring to plug2140A, a first metal line2142and a first conductive via2144are directly adjacent to the left-hand sidewall of dielectric plug2140A. A second metal line2142and a second conductive via2144are directly adjacent to the right-hand sidewall of dielectric plug2140A. Referring to plug2140B, a first metal line2142is directly adjacent to the right-hand sidewall of dielectric plug2140B and an underlying portion of the patterned lower portion2130′ of the ILD layer is directly adjacent a first conductive via2144. On the left-hand side of dielectric plug2140B, however, only a metal line2142and not an associated conductive via are associated with the dielectric plug2140B. In an embodiment, the metal fill process is performed by depositing and then planarizing one or more metal layers over the structure ofFIG. 21.

Referring again toFIG. 21Jseveral different embodiments can be demonstrated using the illustration. For example, in an embodiment, the structure ofFIG. 21Jrepresents a final metallization layer structure. In another embodiment, the dielectric plugs2140A and2140B are removed to provide an air gap structure. In another embodiment, the dielectric plugs2140A and2140B are replaced with another dielectric material. In another embodiment, the dielectric plugs2140A and2140B may be a sacrificial pattern that is ultimately transferred to another underlying interlayer dielectric material layer.

In an exemplary embodiment, referring again toFIG. 21J(and previous processing operations), a metallization layer of an interconnect structure for a semiconductor die includes a metal line2142disposed in a trench2128′ of an interlayer dielectric (ILD) material layer2126. The ILD material layer2126is composed of a first dielectric material. A conductive via2144is disposed in the ILD2126material layer, below and electrically connected to the metal line2142. A dielectric plug2140A (or2140B) is directly adjacent to the metal line2142and the conductive via2144. A second metal line2142and conductive via2144may also be directly adjacent to the dielectric plug (e.g., dielectric plug2140A). In one embodiment, the dielectric plug2140A (or2140B) is composed of a second dielectric material different from the first dielectric material.

It is to be appreciated that filling the openings of the sacrificial material2134with the dielectric material may lead to formation of a seam in the dielectric material approximately in the center of the resulting dielectric plug. For example,FIG. 21Killustrates a cross-sectional view of a metallization layer of an interconnect structure for a semiconductor die that includes dielectric line ends or plugs having a seam therein, in accordance with an embodiment of the present disclosure.

Referring toFIG. 21K, a metallization layer of an interconnect structure for a semiconductor die includes metal lines2140disposed in trenches of an interlayer dielectric (ILD) material layer (lower portion2130′ shown). Conductive vias2144are disposed in the ILD material layer2130′, below and electrically connected to the metal lines2142. Dielectric plugs2152A and2152B are directly adjacent to the metal lines2142and the conductive vias2144. The dielectric plugs2152A and2152B each include a seam2150approximately in the center of the dielectric plug, e.g., attributable to deposition formation of the dielectric plug by chemical vapor deposition (CVD) or atomic layer deposition (ALD).

It is to be appreciated that a line end or plug may be associated with metal lines that do not have underlying vias immediately adjacent the dielectric plug. For example,FIG. 21Lillustrates a cross-sectional view of a metallization layer of an interconnect structure for a semiconductor die that includes a dielectric line end or plug that is not immediately adjacent a conductive via, in accordance with an embodiment of the present disclosure. Referring toFIG. 21L, dielectric plug2152is associated with metal lines2142that do not have underlying vias (such as vias2144) immediately adjacent the dielectric plug2152(and over associated patterned dielectric layer2154′).

A resulting structure such as described in association withFIG. 21J,FIG. 21KorFIG. 21Lmay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 21J,FIG. 21KorFIG. 21Lmay represent the final metal interconnect layer in an integrated circuit. In an embodiment, offset due to conventional lithography/dual damascene patterning that must otherwise be tolerated, is mitigated for the resulting structures described herein. It is also to be appreciated that, in subsequent fabrication operations, the dielectric layer(s) may be removed to provide air gaps between the resulting metal lines.

In accordance with an embodiment of the present disclosure, self-aligned etching of pre-formed vias and plugs is described. One or more embodiments described herein are directed to self-aligned via and plug patterning. The self-aligned aspect of the processes described herein may be based on a directed self-assembly (DSA) mechanism, as described in greater detail below. However, it is to be appreciated that selective growth mechanisms may be employed in place of, or in combination with, DSA-based approaches. In an embodiment, processes described herein enable realization of self-aligned metallization for back-end of line feature fabrication.

Embodiments described herein may be directed to self-aligned isotropic etch processing of pre-formed vias or plugs, or both. For example, a processing scheme may involve pre-formation of every possible via and plug in a metallization layer, such as a back end of line metallization layer of a semiconductor structure. Lithography is then employed to select specific via and/or plug locations to open/close (e.g., keep/remove). Implementation of embodiments described herein can involve the use of such an etch scheme to form all vias/plugs in a photo-bucket arrangement for every corresponding via/metal layer in a metallization stack. As will be appreciated, vias may be formed in a layer different from a layer than plugs are formed in (e.g., the latter being formed in a metal line layer that is vertically between via layers), or plugs and vias may be formed in a same layer.

One or more embodiments described herein offer a more efficient approach to patterning by maximizing the overlay process window, minimizing the size and shape of required patterns, and increasing the efficiency of the lithography process to pattern holes or plugs. In a more specific embodiment, a pattern needed to open a pre-formed via or plug location can be made to be relatively small, enabling an increase in the overlay margin of a lithographic process. The pattern features can be made of uniform size, which can reduce scan time on direct write ebeam and/or optical proximity correction (OPC) complexity with optical lithography. The pattern features can also be made to be shallow, which can improve the patterning resolution. A subsequently performed etch process may be an isotropic chemically selective etch. Such an etch process mitigates otherwise associated with profile and critical dimension and mitigates anisotropic issues typically associated with dry etch approaches. Such an etch process is also relatively much less expensive from an equipment and throughput perspective as compared to other selective removal approaches.

As an exemplary general processing scheme,FIGS. 22A-22Gillustrate portions of integrated circuit layers representing various operations in a method involving self-aligned isotropic etching of pre-formed via or plug locations, in accordance with an embodiment of the present disclosure. In each illustration at each described operation, plan views are shown on the left-hand side, and corresponding cross-sectional views are shown on the right-hand side. These views will be referred to herein as corresponding cross-sectional views and plan views.

FIG. 22Aillustrates a plan view and corresponding cross-sectional view (taken along the a-a′ axis) of a starting structure following pre-patterning of holes/trenches2204in a substrate or layer2202. In one embodiment, the substrate or layer2202is an inter-layer dielectric (ILD) material layer.

Although not depicted for simplicity, it is to be appreciated that the holes/trenches2204may expose underlying features, such as underlying metal lines. Furthermore, in an embodiment, the starting structure may be patterned in a grating-like pattern with holes/trenches2204spaced at a constant pitch and having a constant width. The pattern, for example, may be fabricated by a pitch halving or pitch quartering, etc., approach. In the case that a via layer is fabricated, some of the holes/trenches2204may be associated with underlying lower level metallization lines.

FIG. 22Billustrates a plan view and corresponding cross-sectional view (taken along the b-b′ axis) of the structure ofFIG. 22Afollowing the filling of holes/trenches2204with a sacrificial or permanent placeholder material2206. In the case that a permanent placeholder material is used, an ILD material may be used to fill holes/trenches2204. In the case that a sacrificial placeholder material is used, more flexibility in design choice may be afforded. For example, in one embodiment, a material that would not otherwise be suitable for retention in a final structure may be used, such as a structurally weak polymer or a soft photo-resist material. As depicted in the cross-sectional view ofFIG. 22B, formation of a slight recess2208of the sacrificial or permanent placeholder material2206in the holes/trenches2204may be included to assist with subsequent processing. In one embodiment, the sacrificial or permanent placeholder material2206is a spin-on dielectric material.

FIG. 22Cillustrates a plan view and corresponding cross-sectional view (taken along the c-c′ axis) of the structure ofFIG. 22Bfollowing the formation of a patterning layer2210. In an embodiment the patterning layer2210is a photo-sensitive material, such as a positive tone photo-resist layer. In another embodiment, the patterning layer2210is an anti-reflective coating material. In an embodiment, the patterning layer2210includes a stack of material layers including one or more photo-sensitive material layers and/or one or more anti-reflective coating material layers.

FIG. 22Dillustrates a plan view and corresponding cross-sectional view (taken along the d-d′ axis) of the structure ofFIG. 22Cfollowing patterning of the patterning layer2210to form openings2212in the patterning layer2210. Referring toFIG. 22D, the openings2212expose underlying portions of the sacrificial or permanent placeholder material2206. In particular, the openings2212expose underlying portions of the sacrificial or permanent placeholder material2206only at the holes/trenches2204where a via or plug is selected to be formed. In an embodiment, the openings2212in the patterning layer2210are substantially smaller than the exposed holes/trenches2204. As described briefly above, the formation of openings2212that are relatively smaller than exposed holes/trenches2204provides a markedly increased tolerance for misalignment issues. In an embodiment, the patterning layer2210is a photo-sensitive material and the openings2212are formed by a lithographic process, such as a positive tone lithographic process.

FIG. 22Eillustrates a plan view and corresponding cross-sectional view (taken along the e-e′ axis) of the structure ofFIG. 22Dfollowing removal of the sacrificial or permanent placeholder material2206in locations exposed by the openings2212to form re-exposed holes/trenches2214. In an embodiment, the sacrificial or permanent placeholder material2206is removed by an isotropic etching process. In one such embodiment, the isotropic etching process involves application of a wet etchant. The wet etchant accesses and etches the sacrificial or permanent placeholder material2206through openings2212. The etch process is isotropic in the sense that material that is not exposed by openings2212, but is accessible through openings2212, can be etched to selectively formed re-exposed holes/trenches2214in desired locations for via or plug formation. In one embodiment, the wet etch process etches the sacrificial or permanent placeholder material2206without etching, or without substantially etching the patterning layer2210.

In an embodiment, the sacrificial or permanent placeholder material2206is a spin-on carbon hardmask material and the etch process is a TMAH-based etch process. In another embodiment, the sacrificial or permanent placeholder material2206is a spin-on bottom anti-reflective coating (BARC) material and the etch process is a TMAH-based etch process. In another embodiment, the sacrificial or permanent placeholder material2206is a spin-on bottom glass material and the etch process is a wet etch process based on an organic solvent, an acid or a base. In another embodiment, the sacrificial or permanent placeholder material2206is a spin-on metal oxide material and the etch process is a wet etch process based on commercially available cleans chemicals. In another embodiment, the sacrificial or permanent placeholder material2206is a CVD carbon material and the etch process is based on an oxygen plasma ash.

FIG. 22Fillustrates a plan view and corresponding cross-sectional view (taken along the f-f′ axis) of the structure ofFIG. 22Efollowing removal of the patterning layer2210. In an embodiment, the patterning layer2210is a photo-resist layer, and the photo-resist layer is removed by a wet stripping or plasma ashing process. The removal of the patterning layer2210completely exposes the re-exposed holes/trenches2214.

FIG. 22Gillustrates a plan view and corresponding cross-sectional view (taken along the g-g′ axis) of the structure ofFIG. 22Ffollowing the filling of the re-exposed holes/trenches2214with a material layer2216and subsequent planarization. In an embodiment, the material layer2216is for forming plugs and is a permanent ILD material. In another embodiment, the material layer116is for forming conductive vias and is a metal fill layer. In one such embodiment, the metal fill layer is a single material layer, or is formed from several layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, may be used to form such a metal fill layer. In an embodiment, the metal fill layer is composed of a conductive material such as, but not limited to, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au or alloys thereof. In the case that the material layer116is planarized following deposition, a chemical mechanical polishing process may be used.

In an embodiment, the material layer2216is a material suitable for forming a conductive via. In one such embodiment, the sacrificial or permanent placeholder material2206is a permanent placeholder material such as a permanent ILD material. In another such embodiment, the sacrificial or permanent placeholder material2206is a sacrificial placeholder material that is subsequently removed and replaced with a material such as a permanent ILD material. In another embodiment, the material layer2216is a material suitable for forming a dielectric plug. In one such embodiment, the sacrificial or permanent placeholder material2206is a sacrificial placeholder material that is subsequently removed or partially removed to enable metal line formation.

It is to be appreciated that the resulting structure ofFIG. 22Gmay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 22Gmay represent the final metal interconnect layer in an integrated circuit. Furthermore, it is to be appreciated that the above examples do not include etch-stop or metal capping layers in the Figures that may otherwise be necessary for patterning. However, for clarity, such layers are not included in the Figures since they do not impact the overall concept.

In another aspect, embodiments are directed to a process flow implementing an isotropic dry etch together with a hole shrink process. In one such embodiment, a patterning scheme provides pinhole patterning in a mask layer following the filling of all via locations with an organic polymer. As an exemplary processing scheme,FIGS. 22H-22Jillustrate angled cross-sectional views showing portions of integrated circuit layers representing various operations in a method involving self-aligned isotropic etching of pre-formed via locations, in accordance with an embodiment of the present disclosure.

FIG. 22Hillustrates a starting structure following filling of all possible via locations with a placeholder material. Referring toFIG. 22H, a metallization layer2252(such as an ILD layer of a metallization layer) is formed above a substrate (not shown) and includes a plurality of metal lines2254therein. ILD material(s), which may be two or more distinct ILD materials2256and2258surround the locations where vias may possibly be formed. A sacrificial placeholder material2260occupies the locations where all possible vias may be formed above the metal lines2252. A mask layer2262, such as a thin low temperature oxide mask layer is formed on the underlying structure. It is to be appreciated that sacrificial placeholder material2260is not present over adjacent features, which may be accomplished by a deposition and planarization or recess process.

FIG. 22Iillustrates the structure ofFIG. 22Hfollowing patterning of the mask layer2262to form openings2264in the mask layer2262. Referring toFIG. 22I, the openings2264expose underlying portions of the sacrificial placeholder material2260. In particular, the openings2264expose underlying portions of the sacrificial placeholder material2260only at the locations where a via is selected to be formed. In an embodiment, the openings2264in the mask layer2262are substantially smaller than the exposed sacrificial placeholder material2260. As described briefly above, the formation of openings2264that are relatively smaller than the exposed sacrificial placeholder material2260provides a markedly increased tolerance for misalignment issues. The process effectively “shrinks” the via locations to the sizing of “pinholes” with respect to selection and patterning of the actual via locations. In an embodiment, the mask layer2262is patterned with openings2262by first forming and patterning a photo-sensitive material on the mask layer2262by a lithographic process, such as a positive tone lithographic process, and then patterning the mask layer2262by an etch process.

FIG. 22Jillustrates the structure ofFIG. 22Ifollowing removal of the sacrificial placeholder material2260in locations exposed by the openings2264to form exposed via locations2266. In an embodiment, the sacrificial placeholder material2260is removed at the via locations2266by an isotropic etching process. In one such embodiment, the sacrificial placeholder material2260is an organic polymer, and the isotropic etching process is an isotropic plasma ash (oxygen plasma) or wet cleans process.

Referring again toFIG. 22J, it is to be appreciated that subsequent processing may involve removal of the mask layer2262and filling of holes/trenches2266with a conductive via material. Also, remaining sacrificial placeholder material2260not exposed by openings2264(i.e., not selected as via locations) may be replaced with a permanent ILD material. The resulting structure may subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the resulting structure may represent the final metal interconnect layer in an integrated circuit.

In accordance with one or more embodiments of the present disclosure, as mentioned above, approaches described herein may build on the use of so-called “photobuckets,” in which every possible feature, e.g. via or plug, is pre-patterned into a substrate. Then, a photoresist is filled into patterned features and the lithography operation is merely used to choose select vias for via opening formation. The photobucket approach may allow for larger critical dimensions (CD)s and/or errors in overlay while retaining the ability to choose the via or plug of interest. Lithographic approaches for selecting particular photobuckets may include, but may not be limited to, 193 nm immersion lithography (i193), extreme ultra-violet (EUV) and/or e-beam direct write (EBDW) lithography.

Overall, in accordance with one or more embodiments of the present disclosure, a DSA approach or a subtractive approach is rendered as photosensitive. In one view, a form of photobuckets is achieved where lithographic constraints may be relaxed and misalignment tolerance may be high since the photobucket is surrounded by non-photolyzable materials. Furthermore, in an embodiment, instead of exposing at, e.g. 30 mJ/cm2, such a photobucket might be exposed at, e.g., 3 mJ/cm2. Normally this would result in very poor CD control and roughness. But in this case, the CD and roughness control will be defined by the photobucket geometry, which can be very well controlled and defined. Thus, such a photobucket approach may be used to circumvent imaging/dose tradeoff which limits the throughput of next generation lithographic processes. In an embodiment, photobucket material that is not selected for removal is ultimately retained as a permanent ILD portion in a semiconductor structure. In another embodiment, photobucket material that is not selected for removal is ultimately exchanged for a permanent ILD portion in a semiconductor structure.

In an embodiment, a photobucket “ILD” composition is typically very different from standard ILD and, in one embodiment, is highly self-aligned in both directions. More generally, in an embodiment, the term photobucket as used herein involves use of an ultrafast photoresist or ebeam resist or other photosensitive material as formed in etched openings. In one such embodiment, a thermal reflow of a polymer into the openings is used following a spin coat application. In one embodiment, the fast photoresist is fabricated by removing a quencher from an existing photoresist material. In another embodiment, the photobuckets are formed by an etch-back process and/or a lithography/shrink/etch process. It is to be appreciated that the photobuckets need not be filled with actual photoresist, so long as the material acts as a photosensitive switch. In one embodiment, lithography is used to expose the corresponding photobuckets that are selected for removal. However, the lithographic constraints may be relaxed and misalignment tolerance may be high since the photobuckets are surrounded by non-photolyzable materials. In one embodiment, the photobuckets are subject to exposure of extreme ultraviolet (EUV) light in order to expose the photobuckets, where in a particular embodiment, EUV exposure is in the range of 5-15 nanometers. Although many embodiments described herein involve photobucket material based on polymers, in other embodiments, photobucket material based on nanoparticles are similarly implemented.

In accordance with an embodiment of the present disclosure, a photobucket approach is described. One or more embodiments described herein are directed to subtractive approaches for self-aligned via and plug patterning, and structure resulting there from. In an embodiment, processes described herein enable realization of self-aligned metallization for back-end of line feature fabrication. Overlay problems anticipated for next generation via and plug patterning may be addressed by one or more approaches described herein. More specifically, one or more embodiment described herein involves the use of a subtractive method to pre-form every via and plug using the trenches already etched. An additional operation is then used to select which of the vias and plugs to retain. Such operations can be illustrated using photobuckets, although the selection process may also be performed using a more conventional resist expose and ILD backfill approach.

In a first aspect, a vias first, plugs second approach is used. As an example,FIGS. 23A-23Lillustrate portions of integrated circuit layers representing various operations in a method of subtractive self-aligned via and plug patterning, in accordance with an embodiment of the present disclosure. In each illustration at each described operation, cross-sectional and/or angled views are shown. These views will be referred to herein as corresponding cross-sectional views and angled views.

FIG. 23Aillustrates a cross-sectional view of a starting structure2300following deposition, but prior to patterning, of a first hardmask material layer2304formed on an interlayer dielectric (ILD) layer2302, in accordance with an embodiment of the present disclosure. Referring toFIG. 23A, a patterned mask2306has spacers2308formed along sidewalls thereof, on or above the first hardmask material layer2304.

FIG. 23Billustrates the structure ofFIG. 23Afollowing patterning of the first hardmask layer by pitch doubling, in accordance with an embodiment of the present disclosure. Referring toFIG. 23B, the patterned mask2306is removed and the resulting pattern of the spacers2308is transferred, e.g., by an etch process, to the first hardmask material layer2304to form a first patterned hardmask2310. In one such embodiment, the first patterned hardmask2310is formed with a grating pattern, as is depicted inFIG. 23B. In an embodiment, the grating structure of the first patterned hardmask2310is a tight pitch grating structure. In a specific such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed (mask2306), but the pitch may be halved by the use of spacer mask patterning, as is depicted inFIGS. 23A and 23B. Even further, although not shown, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the first patterned hardmask2310ofFIG. 23Bmay have hardmask lines spaced at a constant pitch and having a constant width.

FIG. 23Cillustrates the structure ofFIG. 23Bfollowing formation of a second patterned hardmask, in accordance with an embodiment of the present disclosure. Referring toFIG. 23C, a second patterned hardmask2312is formed interleaved with the first patterned hardmask2310. In one such embodiment, the second patterned hardmask2312is formed by deposition of a second hardmask material layer (having a composition different from the first hardmask material layer2304. The second hardmask material layer is then planarized, e.g., by chemical mechanical polishing (CMP), to provide the second patterned hardmask2312.

FIG. 23Dillustrates the structure ofFIG. 23Cfollowing deposition of a hardmask cap layer, in accordance with an embodiment of the present disclosure. Referring toFIG. 23D, a hardmask cap layer2314is formed on the first patterned hardmask2310and the first patterned hardmask2312. In one such embodiment, the material composition and etch selectivity of the hardmask cap layer2314is different as compared to the first patterned hardmask2310and the first patterned hardmask2312.

FIG. 23Eillustrates the structure ofFIG. 23Dfollowing patterning of the hardmask cap layer, in accordance with an embodiment of the present disclosure. Referring toFIG. 23E, a patterned hardmask cap layer2314is formed on the first patterned hardmask2310and the first patterned hardmask2312. In one such embodiment, the patterned hardmask cap layer2314is formed with a grating pattern orthogonal to the grating pattern of the first patterned hardmask2310and the first patterned hardmask2312, as is depicted inFIG. 23E. In an embodiment, the grating structure formed by the patterned hardmask cap layer2314is a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the patterned hardmask cap layer2314ofFIG. 23Emay have hardmask lines spaced at a constant pitch and having a constant width.

FIG. 23Fillustrates the structure ofFIG. 23Efollowing further patterning of the first patterned hardmask and subsequent formation of a plurality of photobuckets, in accordance with an embodiment of the present disclosure. Referring toFIG. 23F, using the patterned hardmask cap layer2314as a mask, the first patterned hardmask2310if further patterned to form first patterned hardmask2316. The second patterned hardmask2312is not further patterned in this process. Subsequently, the patterned hardmask cap layer2314is removed, and photobuckets2318are formed in the resulting openings above the ILD layer2302. The photobuckets2318, at this stage, represent all possible via locations in a resulting metallization layer.

FIG. 23Gillustrates the structure ofFIG. 23Ffollowing photobucket exposure and development to leave selected via locations, and subsequent via opening etch into the underlying ILD, in accordance with an embodiment of the present disclosure. Referring toFIG. 23Gselect photobuckets2318are exposed and removed to provide selected via locations2320. The via location2320are subjected to a selective etch process, such as a selective plasma etch process, to extend the via openings into the underlying ILD layer2302, forming patterned ILD layer2302′. The etching is selective to remaining photobuckets2318, to first patterned hardmask2316, and to the second patterned hardmask2312.

FIG. 23Hillustrates the structure ofFIG. 23Gfollowing removal of the remaining photobuckets, subsequent formation of a hardmask material, and subsequent formation of a second plurality of photobuckets, in accordance with an embodiment of the present disclosure. Referring toFIG. 23H, the remaining photobuckets are removed, e.g., by a selective etch process. All openings formed (e.g., openings formed upon removal of photobuckets2318as well as the via locations2320) are then filled with a hardmask material2322, such as a carbon-based hardmask material. Subsequently, the first patterned hardmask2316is removed, e.g., with a selective etch process, and the resulting openings are filled with a second plurality of photobuckets2324. The photobuckets2324, at this stage, represent all possible plug locations in a resulting metallization layer. It is to be appreciated that the second patterned hardmask2312is not further patterned at this stage in the process.

FIG. 23Iillustrates the structure ofFIG. 23Hfollowing plug location selection, in accordance with an embodiment of the present disclosure. Referring toFIG. 23I, the photobuckets2324fromFIG. 23Hin are removed from locations2326where plugs will not be formed. In locations where plugs are selected to be formed, the photobuckets2324are retained. In one embodiment, in order to form locations2326where plugs will not be formed, lithography is used to expose the corresponding photobuckets2324. The exposed photobuckets may then be removed by a developer.

FIG. 23Jillustrates the structure ofFIG. 23Ifollowing removal of the most recently formed hardmask from via and line locations, in accordance with an embodiment of the present disclosure. Referring toFIG. 23J, the hardmask material2322depicted inFIG. 23Iis removed. In one such embodiment, the hardmask material2322is a carbon-based hardmask material and is removed with a plasma ashing process. As shown, features remaining include, the patterned ILD layer2302′, the photobuckets2324retained for plug formation, and the via openings2328. Although not shown, it is to be appreciated that, in an embodiment, the second hardmask layer2312is also retained at this stage.

FIG. 23Killustrates the structure ofFIG. 23Jfollowing recessing of the patterned ILD layer in locations not protected by plug-forming photobuckets, in accordance with an embodiment of the present disclosure. Referring toFIG. 23K, the portions of patterned ILD layer2302′ not protected by photobuckets2324are recessed to provide metal line openings2330, in addition to the via openings2328.

FIG. 23Lillustrates the structure ofFIG. 23Kfollowing metal fill, in accordance with an embodiment of the present disclosure. Referring toFIG. 23L, metallization2332is formed in the openings2328and2332. In one such embodiment, the metallization2332is formed by a metal fill and polish back process. Referring to the left-hand portion ofFIG. 23L, the structure is shown as including a lower portion including patterned ILD layer2302′ having metal lines and vias (shown collectively as2332) formed therein. An upper region of the structure2334includes the second patterned hardmask2312as well as the remaining (plug location) photobuckets2324. In an embodiment, the upper region2334is removed, e.g., by CMP or etch back, prior to subsequent fabrication. However, in an alternative embodiment, the upper region2334is retained in the final structure.

The structure ofFIG. 23Lmay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 23Lmay represent the final metal interconnect layer in an integrated circuit. It is to be appreciated that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed. Referring again toFIG. 23L, self-aligned fabrication by the subtractive approach may be complete at this stage. A next layer fabricated in a like manner likely requires initiation of the entire process once again. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

In a second aspect, a plugs first, vias second approach is used. As an example,FIGS. 23M-23Sillustrate portions of integrated circuit layers representing various operations in a method of subtractive self-aligned plug and via patterning, in accordance with another embodiment of the present disclosure. In each illustration at each described operation, plan views are shown on top, and corresponding cross-sectional views are shown on the bottom. These views will be referred to herein as corresponding cross-sectional views and plan views.

FIG. 23Millustrates a plan view and corresponding cross-sectional views of a starting orthogonal grid formed above a substrate2351, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a′ and b-b′, respectively, a starting grid structure2350includes a grating ILD layer2352having a first hardmask layer2354disposed thereon. A second hardmask layer2356is disposed on the first hardmask layer2354and is patterned to have a grating structure orthogonal to the underlying grating structure. Additionally, openings2358remain between the grating structure of the second hardmask layer2356and the underlying grating formed by the ILD layer2352and the first hardmask layer2354.

FIG. 23Nillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 23Mfollowing opening fill and etch back, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a′ and b-b′, respectively, the openings2358ofFIG. 23Mare filled with a dielectric layer2360, such as silicon oxide layer. Such a dielectric layer2360can be formed with deposited oxide films such as by chemical vapor deposition (CVD), high density plasma deposition (HDP), or spin on dielectrics. The material as deposited may require etch back in order to achieve the relative height shown inFIG. 23N, leaving upper openings2358′.

FIG. 23Oillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 23Nfollowing photobucket fill, exposure, and development to leave selected plug locations, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a′ and b-b′, respectively, photobuckets are formed in the upper openings2358′ ofFIG. 23N. Subsequently, most photobuckets are exposed and removed. However, select photobuckets2362are not exposed and thus retained to provide selected plug locations, as depicted inFIG. 23O.

FIG. 23Pillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 23Ofollowing removal of portions of the dielectric layer2360, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a′ and b-b′, respectively, the portions of dielectric layer2360that are not covered by a photobucket2362are removed. However, the portions of dielectric layer2360that are covered by a photobucket2362remain in the structure ofFIG. 23P. In one embodiment, the portions of dielectric layer2360that are not covered by a photobucket2362are removed by a wet etch process.

FIG. 23Qillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 23Pfollowing photobucket fill, exposure, and development to leave selected via locations, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a′ and b-b′, respectively, photobuckets are formed in the openings formed upon removal of portions of the dielectric layer2360. Subsequently, select photobuckets are exposed and removed to provide selected via locations2364, as is depicted inFIG. 23Q.

FIG. 23Rillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 23Qfollowing via opening etch into the underlying ILD, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a′ and b-b′, respectively, the via location2364ofFIG. 23Qare subjected to a selective etch process, such as a selective plasma etch process, to extend the via openings2364to opening2364′ which are formed into the underlying ILD layer2352.

FIG. 23Sillustrates a plan view and corresponding cross-sectional views of the structure ofFIG. 23Rfollowing removal of the second hardmask layer and the remaining photobucket material, in accordance with an embodiment of the present disclosure. Referring to the plan view and corresponding cross-sectional views (a) and (b) taken along axes a-a′ and b-b′, respectively, the second hardmask layer2356as well as any remaining photobucket material (i.e., photobucket material that was not already exposed and developed) is removed. The removal may be performed selective to all other remaining features. In one such embodiment, the second hardmask layer2356is a carbon based hardmask material, and the removal is performed by an Oz plasma ash process. Referring again toFIG. 23S, remaining at this stage is the ILD layer2352having via openings2364′ formed therein, and the portions of the dielectric layer2360that were preserved for the plug locations (e.g., preserved by the overlying photobucket material). Thus, in one embodiment, the structure ofFIG. 23Sincludes an ILD layer2352patterned with via openings (for subsequent metal fill) with locations of dielectric layer2360to create plugs. The remaining openings2366can be filled with metal to form metal lines. It is to be appreciated that the hardmask2354may be removed.

Accordingly, once filled with metal interconnect material, the structure ofFIG. 23Smay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, once filled with metal interconnect material, the structure ofFIG. 23Smay represent the final metal interconnect layer in an integrated circuit. Referring again toFIG. 23S, self-aligned fabrication by the subtractive approach may be complete at this stage. A next layer fabricated in a like manner likely requires initiation of the entire process once again. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

It is to be appreciated that the approaches described in association withFIGS. 23A-23L and 23M-23Sare not necessarily performed as forming vias aligned to an underlying metallization layer. As such, in some contexts, these process schemes could be viewed as involving blind shooting in the top down direction with respect to any underlying metallization layers. In a third aspect, a subtractive approach provides alignment with an underlying metallization layer. As an example,FIGS. 24A-24Iillustrate portions of integrated circuit layers representing various operations in a method of subtractive self-aligned via patterning, in accordance with another embodiment of the present disclosure. In each illustration at each described operation, an angled three-dimensional cross-section view is provided.

FIG. 24Aillustrates a starting point structure2400for a subtractive via and plug process following deep metal line fabrication, in accordance with an embodiment of the present disclosure. Referring toFIG. 24A, structure2400includes metal lines2402with intervening interlayer dielectric (ILD) lines2404. It is to be appreciated that some of the lines2402may be associated with underlying vias for coupling to a previous interconnect layer. In an embodiment, the metal lines2402are formed by patterning trenches into an ILD material (e.g., the ILD material of lines2404). The trenches are then filled by metal and, if needed, planarized to the top of the ILD lines2404. In an embodiment, the metal trench and fill process involves high aspect ratio features. For example, in one embodiment, the aspect ratio of metal line height (h) to metal line width (w) is approximately in the range of 5-10.

FIG. 24Billustrates the structure ofFIG. 24Afollowing recessing of the metal lines, in accordance with an embodiment of the present disclosure. Referring toFIG. 24B, the metal lines2402are recessed selectively to provide first level metal lines2406. The recessing is performed selectively to the ILD lines2404. The recessing may be performed by etching through dry etch, wet etch, or a combination thereof. The extent of recessing may be determined by the targeted thickness of the first level metal lines2406for use as suitable conductive interconnect lines within a back end of line (BEOL) interconnect structure.

FIG. 24Cillustrates the structure ofFIG. 24Bfollowing formation of an inter-layer dielectric (ILD) layer, in accordance with an embodiment of the present disclosure. Referring toFIG. 24C, an ILD material layer2408is deposited and, if necessary, planarized, to a level above the recessed metal lines2406and the ILD lines2404.

FIG. 24Dillustrates the structure ofFIG. 24Cfollowing deposition and patterning of a hardmask layer, in accordance with an embodiment of the present disclosure. Referring toFIG. 24Da hardmask layer2410is formed on the ILD layer2408. In one such embodiment, the hardmask layer2410is formed with a grating pattern orthogonal to the grating pattern of the first level metal lines2406/ILD lines2404, as is depicted inFIG. 24D. In an embodiment, the grating structure formed by the hardmask layer2410is a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the second hardmask layer2410ofFIG. 24Dmay have hardmask lines spaced at a constant pitch and having a constant width.

FIG. 24Eillustrates the structure ofFIG. 24Dfollowing trench formation defined using the pattern of the hardmask ofFIG. 24D, in accordance with an embodiment of the present disclosure. Referring toFIG. 24E, the exposed regions (i.e., unprotected by2410) of the ILD layer2408are etched to form trenches2412and patterned ILD layer2414. The etch stops on, and thus exposes, the top surfaces of the first level metal lines2406and the ILD lines2404.

FIG. 24Fillustrates the structure ofFIG. 24Efollowing photobucket formation in all possible via locations, in accordance with an embodiment of the present disclosure. Referring toFIG. 24F, photobuckets2416are formed in all possible via locations above exposed portions of the recessed metal lines2406. In one embodiment, the photobuckets2416are formed essentially co-planar with the top surfaces of the ILD lines2404, as depicted inFIG. 24F. Additionally, referring again toFIG. 24F, the hardmask layer2410may be removed from the patterned ILD layer2414.

FIG. 24Gillustrates the structure ofFIG. 24Ffollowing via location selection, in accordance with an embodiment of the present disclosure. Referring toFIG. 24G, the photobuckets2416fromFIG. 24Fin select via locations2418are removed. In locations where vias are not selected to be formed, the photobuckets2416are retained. In one embodiment, in order to form via locations2418, lithography is used to expose the corresponding photobuckets2416. The exposed photobuckets may then be removed by a developer.

FIG. 24Hillustrates the structure ofFIG. 24Gfollowing conversion of the remaining photobuckets to permanent ILD material, in accordance with an embodiment of the present disclosure. Referring toFIG. 24H, the material of the photobuckets2416is modified, e.g., by cross-linking upon a baking operation, in the locations to form a final ILD material2420. In one such embodiment, the cross-linking provides for a solubility switch upon the baking. The final, cross-linked material has inter-dielectric properties and, thus, can be retained in a final metallization structure.

Referring again toFIG. 24H, in an embodiment, the resulting structure includes up to three different dielectric material regions (ILD lines2404+ILD lines2414+cross-linked photobucket2420) in a single plane2450of the metallization structure. In one such embodiment, two or all of ILD lines2404, ILD lines2414, and cross-linked photobucket2420are composed of a same material. In another such embodiment, ILD lines2404, ILD lines2414, and cross-linked photobucket2420are all composed of different ILD materials. In either case, in a specific embodiment, a distinction such as a vertical seam between the materials of ILD lines2404and ILD lines2414(e.g., seam2497) and/or between ILD lines2404and cross-linked photobucket2420(e.g., seam2498) and/or between ILD lines2414and cross-linked photobucket2420(e.g., seam2499) may be observed in the final structure.

FIG. 24Iillustrates the structure ofFIG. 24Hfollowing metal line and via formation, in accordance with an embodiment of the present disclosure. Referring toFIG. 24I, metal lines2422and vias2424are formed upon metal fill of the openings ofFIG. 24H. The metal lines2422are coupled to the underlying metal lines2406by the vias2424. In an embodiment, the openings are filled in a damascene approach or a bottom-up fill approach to provide the structure shown inFIG. 24I. Thus, the metal (e.g., copper and associated barrier and seed layers) deposition to form metal lines and vias in the above approach may be that typically used for standard back end of line (BEOL) processing. In an embodiment, in subsequent fabrication operations, the ILD lines2414may be removed to provide air gaps between the resulting metal lines2424.

The structure ofFIG. 24Imay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 24Imay represent the final metal interconnect layer in an integrated circuit. Referring again toFIG. 24I, self-aligned fabrication by the subtractive approach may be complete at this stage. A next layer fabricated in a like manner likely requires initiation of the entire process once again. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

In accordance with an embodiment of the present disclosure, multi-colored photobuckets are described. One or more embodiments described herein are directed to the use of multicolored photobuckets as an approach for addressing plug and via fabrication below the lithography pitch limit. One or more embodiments described herein are directed to subtractive approaches for self-aligned via and plug patterning, and structures resulting there from. In an embodiment, processes described herein enable realization of self-aligned metallization for back-end of line feature fabrication. Overlay problems anticipated for next generation via and plug patterning may be addressed by one or more approaches described herein.

In an exemplary embodiment, approaches described below build on approaches using so-called photobuckets, in which every possible feature, e.g. via, is re-patterned into a substrate. Then, a photoresist is filled into patterned features and the lithography operation is merely used to choose select vias for via opening formation. In a particular embodiment described below, a lithography operation is used to define a relatively large hole above a plurality of “multicolored photobuckets,” which can then be opened up by a flood exposure of a particular wavelength. The multicolored photobucket approach allows for larger critical dimensions (CD)s and/or errors in overlay while retaining the ability to choose the via of interest. In one such embodiment, a trench is used to contain the resist itself and multiple wavelengths of flood exposure are used to selectively open the vias of interest.

More specifically, one or more embodiment described herein involves the use of a subtractive method to pre-form every via or via opening using the trenches already etched. An additional operation is then used to select which of the vias and plugs to retain. Such operations can be illustrated using photobuckets, although the selection process may also be performed using a more conventional resist expose and ILD backfill approach.

In an example, a self-aligned via opening approach may be used. As an exemplary processing scheme,FIGS. 25A-25Hillustrate portions of integrated circuit layers representing various operations in a method of subtractive self-aligned via patterning using multi-colored photobuckets, in accordance with an embodiment of the present disclosure. In each illustration at each described operation, cross-sectional views are shown.

FIG. 25Aillustrates a cross-sectional view of a starting structure2500following deposition, but prior to patterning, of a first hardmask material layer2504formed on an interlayer dielectric (ILD) layer2502, in accordance with an embodiment of the present disclosure. Referring toFIG. 25A, a patterned mask2506has spacers2508formed along sidewalls thereof, on or above the first hardmask material layer2504.

FIG. 25Billustrates the structure ofFIG. 25Afollowing first time patterning of the first hardmask layer and subsequent first color photobucket fill, in accordance with an embodiment of the present disclosure. Referring toFIG. 25B, the patterned mask2506and corresponding spacers2508are used together as a mask during an etch to form trenches2510through the first hardmask material layer2504and partially into the ILD layer2502. The trenches2510are then filled with first color photobuckets2512.

FIG. 25Cillustrates the structure ofFIG. 25Bfollowing second time patterning of the first hardmask layer and subsequent second color photobucket fill, in accordance with an embodiment of the present disclosure. Referring toFIG. 25C, the patterned mask2506is removed and a second plurality of trenches2514is etched through the first hardmask material layer2504and partially into the ILD layer2502, between spacers2508. Subsequently, the trenches2514are filled with a second color photobucket material layer2516.

Referring again toFIG. 25C, the negative pattern of the spacers2508is thus transferred, e.g., by two etch processes forming trenches2510and2514, to the first hardmask material layer2504. In one such embodiment, the spacers2508and, hence, the trenches2510and2514are formed with a grating pattern, as is depicted inFIG. 25C. In an embodiment, the grating pattern is a tight pitch grating pattern. In a specific such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be limited to mask2506, but the pitch may be halved by the use of negative spacer mask patterning, as is depicted inFIGS. 25A-25C. Even further, although not shown, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the photobuckets2512and2516, collectively, is spaced at a constant pitch and has a constant width.

FIG. 25Dillustrates the structure ofFIG. 25Cfollowing planarization to isolate the first and second color photobuckets from one another, in accordance with an embodiment of the present disclosure. Referring toFIG. 25D, the second color photobucket material layer2516and the top portions of the spacers2508are planarized, e.g., by chemical mechanical polishing (CMP), until the top surfaces of the first color photobuckets2512are exposed, forming discrete second color photobuckets2518from the photobucket material layer2516. In one embodiment, the combination of first color photobuckets2512and second color photobuckets2518represent all possible via locations in a subsequently formed metallization structure.

FIG. 25Eillustrates the structure ofFIG. 25Dfollowing exposure and development of a first color photobucket to leave a selected via location, in accordance with an embodiment of the present disclosure. Referring toFIG. 25E, a second hardmask2520is formed and patterned on the structure ofFIG. 25D. The patterned second hardmask2520reveals a selected first color photobucket2512A. The selected photobucket2512A is exposed to light irradiation and removed (i.e., developed) to provide a selected via opening2513A. It is to be appreciated that description herein concerning forming and patterning a hardmask layer involves, in an embodiment, mask formation above a blanket hardmask later. The mask formation may involve use of one or more layers suitable for lithographic processing. Upon patterning the one or more lithographic layers, the pattern is transferred to the hardmask layer by an etch process to provide a patterned hardmask layer.

Referring again toFIG. 25E, it may not be possible to reveal only the selected photobucket2512A upon patterning of the second hardmask layer2520. For example, one or more adjacent (or nearby) second color photobuckets2518may also be revealed. These additionally revealed photobuckets may not be desirable locations for ultimate via formation. However, any revealed second color photobuckets2518are, in an embodiment, not modified upon exposure to the irradiation used to for patterning the group of first color photobuckets2512. For example, in one embodiment, the first color photobuckets2512are susceptible to red flood exposure2521and can be developed to remove select of the first color photobuckets2512, as is shown inFIG. 25E. In that embodiment, the second color photobuckets2518are not susceptible to red flood exposure and, thus, cannot be developed and removed even if revealed during the red flood exposure, as is shown inFIG. 25E. In an embodiment, by having neighboring photobuckets of different irradiation susceptibility, larger patterns and/or offset tolerance may be accommodated to relax the restrictions otherwise associated with patterning the second hardmask layer2520.

FIG. 25Fillustrates the structure ofFIG. 25Efollowing exposure and development of a second color photobucket to leave an additional selected via location, in accordance with an embodiment of the present disclosure. Referring toFIG. 25F, a third hardmask2522is formed and patterned on the structure ofFIG. 25E. The third hardmask2522may also fill the selected via opening2513A, as is depicted inFIG. 25F. The patterned third hardmask2522reveals selected second color photobuckets2518A and2518B. The selected photobuckets2518A and2518B are exposed to light irradiation and removed (i.e., developed) to provide selected via openings2519A and2519B, respectively.

Referring again toFIG. 25F, it may not be possible to reveal only the selected photobuckets2518A and2518B upon patterning of the third hardmask layer2522. For example, one or more adjacent (or nearby) first color photobuckets2512may also be revealed. These additionally revealed photobuckets may not be desirable locations for ultimate via formation. However, any revealed first color photobuckets2512are, in an embodiment, not modified upon exposure to the irradiation used to for patterning the group of second color photobuckets2518. For example, in one embodiment, the second color photobuckets2518are susceptible to green flood exposure2523and can be developed to remove select of the second color photobuckets2518, as is shown inFIG. 25F. In that embodiment, the first color photobuckets2512are not susceptible to green flood exposure and, thus, cannot be developed and removed even if revealed during the green flood exposure, as is shown inFIG. 25F. In an embodiment, by having neighboring photobuckets of different irradiation susceptibility, larger patterns and/or offset tolerance may be accommodated to relax the restrictions otherwise associated with patterning the third hardmask layer2522.

FIG. 25Gillustrates the structure ofFIG. 25Ffollowing removal of the third hardmask layer and etching to form via locations, in accordance with an embodiment of the present disclosure. Referring toFIG. 25G, the third hardmask layer2522is removed. In one such embodiment, the third hardmask layer2522is a carbon-based hardmask layer and is removed by an ashing process. Then, the pattern of the via openings2519A,2513A and2519B are subjected to a selective etch process, such as a selective plasma etch process, to extend the via openings deeper into the underlying ILD layer2502, forming via patterned ILD layer2502′ with via locations2524. The etching is selective to remaining photobuckets2512and2518and to the spacers2508.

FIG. 25Hillustrates the structure ofFIG. 25Gprior to metal fill, in accordance with an embodiment of the present disclosure. Referring toFIG. 25H, all remaining first color and second color photobuckets2512and2518are removed. The remaining first color and second color photobuckets2512and2518may be removed directly, or may first be exposed and developed to enable removal. The removal of the remaining first color and second color photobuckets2512and2518provides metal line trenches2526, some of which are coupled to via locations2524in patterned ILD layer2502′. Subsequent process can include removal of spacers2508and hardmask layer2504, and metal fill of metal line trenches2526and via locations2524. In one such embodiment, metallization is formed by a metal fill and polish back process.

The structure ofFIG. 25H, upon metal fill, may subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 25H, upon metal fill, may represent the final metal interconnect layer in an integrated circuit. Referring again toFIG. 25H, self-aligned fabrication by the subtractive approach may be complete at this stage. A next layer fabricated in a like manner likely requires initiation of the entire process once again. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

Referring again toFIGS. 25A-25H, several options may be considered as viable for providing first color photobuckets2512and second color photobuckets2518. For example, in an embodiment, two different positive tone organic photoresists are used. It is to be appreciated that in one such embodiment, materials with different chemical structures can be selected for first color photobuckets2512and second color photobuckets2518to allow for different coating, photoactivation and development processes to be used. As an exemplary embodiment, a conventional 193 nm litho poly-methacrylate resist system is chosen for first color photobuckets2512, while a conventional 248 nm poly-hydroxystyrene photoresist system is chosen for the second color photobuckets2518. The significant chemical differences between these two types of resins allow two different organic casting solvents to be used; this may be necessary since the material of the second color photobuckets2518is coated with the material of the first color photobuckets2512already present. The casting solvent for the first color photobuckets2512is not limited, while for the second color photobuckets2518, alcoholic solvents could be used as they still can solubilize PHS materials but not less polar poly-methacrylates.

The combination of a poly-methacrylate resin as the material of the first color photobuckets2512and a poly-hydroxystyrene resin as the material of the second color photobuckets2518can, in an embodiment, enable two different exposure wavelengths to be used. Typical 193 nm litho polymers are based on poly-methacrylates with 193 nm absorbing photo acid generator (PAG) since the polymer does not absorb strongly at this wavelength. Poly-hydroxystyrenes, on the other hand, may not be appropriate since they absorb 193 nm strongly and prevent activation of PAG throughout the film. In one embodiment, then, the material of the first color photobuckets2512can be selectively activated and developed in the presence of 193 nm photons. In order to accentuate photospeed differences between the first color photobuckets2512and the second color photobuckets2518, factors such as PAG absorbance at 193 nm, PAG loading and photoacid strength can be tuned for each. Additionally, strong 193 nm absorbers can be added to the second color photobuckets2518(or deposited selectively on top of the second color photobuckets2518) to decrease PAG activation within the bulk of the film. Following exposure, in a particular embodiment, development of the first color photobuckets2512selectively is carried out with standard TMAH developer where minimal development of the second color photobuckets2518will occur.

In an embodiment, in order to selectively remove the second color photobuckets2518in presence of the first color photobuckets2512, a second lower energy wavelength is used which only activates PAG in the second color photobuckets2518and not in the first color photobuckets2512. This can be achieved in two ways. First, in one embodiment, PAGs with differing absorbance characteristics are used. For example, trialkylsulfonium salts have very low absorbance at wavelengths such as at 248 nm, whereas triarylsulfoniums have very high absorbance. Thus, selectivity is achieved by using triarylsulfonium or other 248 nm absorbing PAGs in the second color photobuckets2518while using trialkylsulfonium or other non-248 nm absorbing PAG in the first color photobuckets2512. Alternatively, a sensitizer can be incorporated into the second color photobuckets2518which absorbs low energy photons transferring energy to PAG selectively in the second color photobuckets2518with no activation occurring in the first color photobuckets2512, since there is no sensitizer present.

In another embodiment,FIG. 25Iillustrates an exemplary dual tone resist for one photobucket type and an exemplary single tone resist for another photobucket type, in accordance with an embodiment of the present disclosure. Referring toFIG. 25I, in one embodiment, a dual tone photoresist system (PB-1) is used for the material of the first color photobuckets2512. A single tone (slow) photoresist system (PB-2) is used for the material of the second color photobuckets2518. A dual tone photoresist may be characterized as having a photo-response that is effectively turned off at higher doses due to activation of photobase generators included in system. The photogenerated base neutralizes photoacid and prevents polymer deprotection. In an embodiment, during exposure of the first color photobuckets2512, dose is selected such that dual tone resist (PB-1) is operating as a fast positive tone system, whereas single tone resist (PB-2) has not received sufficient photons for solubility switch to be activated. This allows PB-1 to be removed with TMAH developer without removal of PB-2. In order to selectively remove PB-2 without removing PB-1, a higher dose is used for the second exposure (i.e., exposure of the second color photobuckets2518). The dose selected needs to both activate sufficient PAG in PB-2 to allow dissolution in TMAH and move PB-2 into negative tone response regime through activation of PBG. In this scheme, the same PAGs can be used for PB-1 and PB-2 and the same exposure wavelengths can be used for exposures1and2. It is to be appreciated that PB-1 may require incorporation of photobase generator (PBG); however, it is likely that different types of polymers will be needed to allow coating of PB-2 once PB-1 is already coated. As described above, utilization of poly-methylmethacrylate type resist for PB-1 and PHS-type for PB-2 could satisfy this requirement.

It is to be appreciated that the above designated materials for first and second color photobuckets2512and2518, respectively, could be switched, in accordance with embodiments of the present disclosure. Also, the above multi-color photobucket approach can be referred to as 1-D. Similar approaches could be applied to 2-D systems using crossed gratings, although the photobucket material would have to withstand the etch and cleans from the crossed grating above. The result would be a checkerboard-type pattern with smaller vias/plugs in the perpendicular direction versus those in the approach described above. Additionally, it is to be appreciated that the approaches described in association withFIGS. 25A-25Hare not necessarily performed as forming vias aligned to an underlying metallization layer, although they certainly can be implemented as such. In other contexts, these process schemes could be viewed as involving blind shooting in the top down direction with respect to any underlying metallization layers.

In accordance with an embodiment of the present disclosure, photobuckets for conductive tabs are described.

By way of example,FIG. 26Aillustrates a plan view of a conventional back end of line (BEOL) metallization layer. Referring toFIG. 26A, a conventional BEOL metallization layer2600is shown with conductive lines or routing2604disposed in an inter-layer dielectric layer2602. The metal lines may generally run parallel to one another and may include cuts, breaks or plugs2606in the continuity of one or more of the conductive lines2604. In order to electrically couple two or more of the parallel metal lines, upper or lower layer routing2608is included in a previous or next metallization layer. Such upper or lower layer routing2608may include a conductive line2610coupling conductive vias2612. It is to be appreciated that, since the upper or lower layer routing2608is included in a previous or next metallization layer, the upper or lower layer routing2608can consume vertical real estate of a semiconductor structure that includes the metallization layers.

By contrast,FIG. 26Billustrates a plan view of a back end of line (BEOL) metallization layer having a conductive tab coupling metal lines of the metallization layer, in accordance with an embodiment of the present disclosure. Referring toFIG. 26B, a BEOL metallization layer2650is shown with conductive lines or routing2654disposed in an inter-layer dielectric layer2652. The metal lines may generally run parallel to one another and may include cuts, breaks or plugs2656in the continuity of one or more of the conductive lines2654. In order to electrically couple two or more of the parallel metal lines, a conductive tab158is included in the metallization layer2650. It is to be appreciated that, since the conductive tab2658is included in the same metallization layer as the conductive lines2654, the conductive tab2658consumption of vertical real estate of a semiconductor structure that includes the metallization layer can be reduced relative to the structure ofFIG. 26A.

One or more embodiments described herein are directed to photobucket approaches for damascene plug and tab patterning. Such patterning schemes may be implemented to enable bi-directional spacer-based interconnects. Implementations may be particularly suitable for electrically connecting two parallel lines of a metallization layer where the two metal lines were fabricated using a spacer-based approach which otherwise may restrict the inclusion of conductive connection between two adjacent lines in a same metallization layer. In general, one or more embodiments are directed to an approach that employs a damascene technique to form conductive tabs and non-conductive spaces or interruptions between metals (plugs).

More specifically, one or more embodiment described herein involves the use of a damascene method to form tabs and plugs. Initially, every possible tab and plug location is first patterning in a hardmask layer. An additional operation is then used to select which of the tab and plug locations to retain. The locations are then transferred into an underlying inter-layer dielectric layer. Such operations can be illustrated using photobuckets. In a particular embodiment, a method for damascene patterning of vias, plugs, and tabs with is provided with self-alignment using a photobucketing approach and selective hard masks.

In accordance with an embodiment of the present disclosure, photobucket patterning is used for fabricating plugs and tabs in a self-aligned manner. A general overview process flow can involve (1) fabrication of a cross-grating, followed by (2) photobucketing for plug definition and changing the photoresist to a “hard” material that can withstand downstream processing, followed by (3) grating tone reversal by backfilling with a tillable material, recessing the tillable material, and removing the original cross-grating, followed by (4) photobucketing for “Tab” definition, followed by (5) etch transferring the pattern into an underlying inter-layer dielectric (ILD) layer and polishing away the additional hard mask materials. It is to be appreciated that although the general process flow does not include vias, in an embodiment, approaches described herein can be implemented to extend to multiple passes of plugs, vias, and tabs using a same self-aligned grating.

As an example,FIGS. 27A-27Killustrate angled cross-sectional views representing various operations in a method of fabricating a back end of line (BEOL) metallization layer having a conductive tab coupling metal lines of the metallization layer, in accordance with an embodiment of the present disclosure.

Referring toFIG. 27A, a first operation in a cross-grating patterning scheme is performed above an inter-layer dielectric (ILD) layer2702formed above a substrate2700. A blanket hardmask2704is first formed on the ILD layer2702. A first grating hardmask2706is formed along a first direction above the blanket hardmask2704. In an embodiment, the first grating hardmask2706is formed with a grating pattern, as is depicted inFIG. 27A. In an embodiment, the grating structure of the first grating hardmask2706is a tight pitch grating structure. In a specific such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the first grating hardmask2706ofFIG. 27Amay have hardmask lines tightly spaced at a constant pitch and having a constant width.

Referring toFIG. 27B, a second operation in a cross-grating patterning scheme is performed above the inter-layer dielectric (ILD) layer2702. A second grating hardmask2708is formed along a second direction above the blanket hardmask2704. The second direction is orthogonal to the first direction. The second grating hardmask2708has an overlying hardmask2710thereon. In an embodiment, the second grating hardmask2710is fabricated in a patterning process using the overlying hardmask2710. The continuity of the second grating hardmask2708is broken by lines of the first grating hardmask2706and, as such, portions of the first grating hardmask2706extend under the overlying hardmask2710. In an embodiment, the second grating hardmask2708is formed interleaved with the first grating hardmask2706. In one such embodiment, the second grating hardmask2708is formed by deposition of a second hardmask material layer having a composition different from the first grating hardmask2706. The second hardmask material layer is then planarized, e.g., by chemical mechanical polishing (CMP), and then patterned using the overlying hardmask2710to provide the second grating hardmask2708. As was the case for the first grating hardmask2706, in an embodiment, the grating structure of the second grating hardmask2708is a tight pitch grating structure. In a specific such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the second grating hardmask2708ofFIG. 27Amay have hardmask lines tightly spaced at a constant pitch and having a constant width.

Referring toFIG. 27C, a plug photobucket patterning scheme is performed as a first photobucketing process. In an embodiment, photobuckets2712are formed on all of the exposed openings between the first grating hardmask2706and the second grating hardmask2708. In an embodiment, a via patterning process is optionally performed prior to the plug photobucket patterning process. The via patterning may be direct patterning or may involve a separate photobucketing process.

Referring toFIG. 27D, select ones of the photobuckets2712are removed while other photobuckets2712are retained, e.g., by not exposing a select photobucket2712to a lithography and development process used to open all other photobuckets2712. The exposed portions of the blanket hardmask2704ofFIG. 27Aare then etched to provide first-time patterned hardmask2714. The retained photobuckets2712, at this stage, represent the plug locations in a final metallization layer. That is, in the first photobucket process, photobuckets are removed from locations where plugs will not be formed. In one embodiment, in order to form locations where plugs will not be formed, lithography is used to expose the corresponding photobuckets. The exposed photobuckets may then be removed by a developer.

Referring toFIG. 27E, a grating tone reversal process is performed. In an embodiment, dielectric regions2716is formed in all of the exposed regions of the structure ofFIG. 27D. In an embodiment, the dielectric regions2716are formed by deposition of a dielectric layer and etch back to form dielectric regions2716.

Referring toFIG. 27F, the portions of the first grating hardmask2706not covered by the overlying hardmask2710are then removed to leave only portions2706′ of the first grating hardmask2706remaining under the overlying hardmask2710.

Referring toFIG. 27G, a tab photobucket patterning scheme is performed as a second photobucketing process. In an embodiment, photobuckets2718are formed in all of the exposed openings formed upon removal of exposed portions of the first grating hardmask2706.

Referring toFIG. 27H, select ones of the photobuckets2718are removed while other photobuckets2718are retained, e.g., by not exposing photobuckets2718to a lithography and development process used to open the other photobuckets. The exposed portions of the first-time patterned hardmask2714ofFIGS. 27D-27Gare then etched to provide second-time patterned hardmask2715. The retained photobuckets2718, at this stage, represent the locations where conductive tabs will not be in a final metallization layer. That is, in the second photobucket process, photobuckets are removed from locations where conductive tabs will ultimately be formed. In one embodiment, in order to form locations where conductive tabs will be formed, lithography is used to expose the corresponding photobuckets. The exposed photobuckets may then be removed by a developer.

Referring toFIG. 27I, the overlying hardmask2710, the second grating hardmask2708, and the dielectric regions2716are removed. Subsequently, portions of the second-time patterned hardmask2715exposed upon removal of the overlying hardmask2710are removed to provide third-time patterned hardmask2720, the second grating hardmask2708, and the dielectric regions2716are removed. In an embodiment, remaining ones of the photobuckets2712and2718are first hardened (e.g., by a bake process), prior to removing the overlying hardmask2710, the second grating hardmask2708, and the dielectric regions2716. At this stage, select ones of the photobuckets2712, select ones of the photobuckets2718, and retained portions2706′ of the first grating hardmask2706remain above the third-time patterned hardmask2720. In an embodiment, the overlying hardmask2710, the second grating hardmask2708, and the dielectric regions2716are removed using a selective wet etch process, while the portions of the second-time patterned hardmask2715exposed upon removal of the overlying hardmask2710are removed to provide third-time patterned hardmask2720using a dry etch process.

Referring toFIG. 27J, the pattern of the third-time patterned hardmask2720is transferred to an upper portion of the ILD layer2702to form patterned ILD layer2722. In an embodiment, then, a plug and tab pattern of the third-time patterned hardmask2720is transferred to the ILD layer2702to form patterned ILD layer2722. In an embodiment, an etch process is used to transfer the pattern into the ILD layer2702. In one such embodiment, the select ones of the photobuckets2712, select ones of the photobuckets2718, and retained portions2706′ of the first grating hardmask2706remaining above the third-time patterned hardmask2720are removed or consumed during the etching used to form patterned ILD layer2722. In another embodiment, the select ones of the photobuckets2712, select ones of the photobuckets2718, and retained portions2706′ of the first grating hardmask2706remaining above the third-time patterned hardmask2720are removed prior to or subsequent to the etching used to form patterned ILD layer2722.

Referring toFIG. 27K, following formation of patterned ILD layer2732, conductive lines2724are formed. In one embodiment, the conductive lines2724are formed using a metal fill and polish back process. During the formation of conductive lines2724, a conductive tab2728coupling two metal lines2724is also formed. Thus, in an embodiment, a conductive coupling (tab2728) between conductive lines2724is formed at the same time as the conductive lines2724, in a same ILD layer2722, and in a same plane as the conductive lines2724. Additionally, plugs2726may be formed as a break or interruption in one or more of the conductive lines2724, as is depicted inFIG. 27K. In one such embodiment, the plug2726is a region of the ILD layer2702that is preserved during pattern transfer to form patterned ILD layer2722. In an embodiment, the third-time patterned hardmask2720is removed, as is depicted inFIG. 27K. In one such embodiment, the third-time patterned hardmask2720is removed subsequent to forming the conductive lines2724and tab2728, e.g., using a post metallization chemical mechanical planarization (CMP) process.

Referring again toFIG. 27K, in an embodiment, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer2722disposed above a substrate2700. A plurality of conductive lines2724is disposed in the ILD layer2722along a first direction. A conductive tab2728is disposed in the ILD layer2722. The conductive tab couples two of the plurality of conductive lines2724along a second direction orthogonal to the first direction.

Such an arrangement as depicted inFIG. 27Kmay not otherwise be achievable by conventional lithographic processing at either small pitch, small width, or both. Also, self-alignment may not be achievable with conventional processes. Furthermore, arrangement as depicted inFIG. 27Kmay not otherwise be achievable in cases where a pitch division scheme is used to ultimately provide a pattern for the conductive lines2724.

In an embodiment, the conductive tab2728is continuous, and not contiguous, with the two of the plurality of conductive lines, as is depicted inFIG. 27K. In an embodiment, the conductive tab2728is co-planar with the two of the plurality of conductive lines2724, as is depicted inFIG. 27K. In an embodiment, the BEOL metallization layer further includes a dielectric plug2726disposed at an end of one of the plurality of conductive lines2724, as is depicted inFIG. 27K. In one embodiment, the dielectric plug2726is continuous, and not contiguous, with the ILD layer, as is depicted inFIG. 27K. In one embodiment, although not shown, the BEOL metallization layer further includes a conductive via disposed below and electrically coupled to one of the plurality of conductive lines2724.

The structure ofFIG. 27Kmay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 3Kmay represent the final metal interconnect layer in an integrated circuit. Referring again toFIG. 27K, such self-aligned fabrication by a damascene photobucket approach may be continued to fabricate a next metallization layer. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches. It is also to be appreciated that, although not depicted, one or more of the conductive lines2724may be coupled to an underlying conductive via which may be formed using an additional photobucket operation. In an embodiment, as an alternative to the above described two-dimensional approach, a one-dimensional grating approach may also be implemented for plugs and tabs (and possibly via) patterning. Such a one-dimensional approach provides confinement in only one direction. As such, the pitch may be “tight” in one direction and “loose” in one direction.

One or more embodiments described herein are directed to photobucket approaches for subtractive plug and tab patterning. Such patterning schemes may be implemented to enable bi-directional spacer-based interconnects. Implementations may be particularly suitable for electrically connecting two parallel lines of a metallization layer where the two metal lines were fabricated using a spacer-based approach which otherwise may restrict the inclusion of conductive connection between two adjacent lines in a same metallization layer. In general, one or more embodiments are directed to an approach that employs a subtractive technique to form conductive tabs and non-conductive spaces or interruptions between metals (plugs).

One or more embodiments described herein provide an approach for subtractively patterning vias, cuts, and/or tabs with self-alignment using a photobucketing approach and selective hard masks. Embodiments may involve use of a so-called textile patterning approach for subtractively-patterned self-aligned interconnects, plugs, and vias. A textile approach may involve implementation of a textile pattern of hardmasks with etch selectivity among each hardmask material. In specific embodiments described herein, a textile processing scheme is implemented to pattern interconnects, cuts, and vias subtractively.

As an overview of one or more embodiments described herein, a general overview process flow can involve the following process sequence: (1) fabrication using a textile process flow with four “color” hardmasks that are etch selective to one another, (2) removing a first of the hardmask types for photobucketing for vias, (3) backfilling the first hardmask material, (4) removing a second of the hardmask types for photobucketing for cuts (or plugs), (5) backfilling the second mask material, (6) removing a third of the hardmask types for photobucketing for conductive tabs, (7) subtractively etching metal for cuts and tabs, and (8) hardmask removal and subsequent backfilling with permanent ILD material and polish back.

FIGS. 28A-28Tillustrate angled cross-sectional views representing various operations in a method of fabricating a back end of line (BEOL) metallization layer having a conductive tab coupling metal lines of the metallization layer, in accordance with an embodiment of the present disclosure.

Referring toFIG. 28A, a grating patterning scheme is performed above a blanket hardmask layer2802formed above a metal layer2800formed above a substrate (not shown). A first grating hardmask2804is formed along a first direction above the blanket hardmask2802. A second grating hardmask2806is formed along the first direction and alternating with the first grating hardmask2804. In an embodiment, the first grating hardmask2804is formed from a material having an etch selectivity different than the material of the second grating hardmask2806.

In an embodiment, the first and second grating hardmasks2804and2806are formed with a grating pattern, as is depicted inFIG. 28A. In an embodiment, the grating structure of the first and second grating hardmasks2804and2806is a tight pitch grating structure. In a specific such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the first and second grating hardmasks2804and2806ofFIG. 28Amay have hardmask lines tightly spaced at a constant pitch and having a constant width.

Referring toFIG. 28B, a sacrificial cross-grating patterning process is performed. An overlying hardmask2808is formed with a grating pattern along a second direction, orthogonal to first direction, i.e., orthogonal to the first and second grating hardmasks2804and2806.

In an embodiment, the overlying hardmask2808is formed with a tight pitch grating structure. In a specific such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the overlying hardmask2808ofFIG. 28Bmay have hardmask lines tightly spaced at a constant pitch and having a constant width.

Referring toFIG. 28C, textile pattern formation is performed. Regions of the first hardmask2804exposed between the grating of the overlying hardmask2808are selectively etched and replaced with regions of a third hardmask2810. Regions of the second hardmask2806exposed between the grating of the overlying hardmask2808are selectively etched and replaced with regions of a fourth hardmask2812. In an embodiment, the third hardmask2810is formed from a material having an etch selectivity different than the material of the first hardmask2804and the second hardmask2806. In a further embodiment, the fourth hardmask2812is formed from a material having an etch selectivity different than the material of the first hardmask2804, the second hardmask2806, and the third hardmask2810.

Referring toFIG. 28D, the overlying hardmask2808is removed. In an embodiment, the overlying hardmask2808is removed using an etch, ash or cleans process selective to the first hardmask2804, the second hardmask2806, the third hardmask2810, and the fourth hardmask2812to leave a textile pattern as is illustrated inFIG. 28D.

FIGS. 28E-28Hare associated with a via patterning process. Referring toFIG. 28E, the third hardmask2810is removed selective to the first hardmask2804, selective to the second hardmask2806, and selective to the fourth hardmask2812to provide openings2814exposing portions of the blanket hardmask2802. In an embodiment, the third hardmask2810is removed selective to the first hardmask2804, selective to the second hardmask2806, and selective to the fourth hardmask2812using a selective etch or cleans process.

Referring toFIG. 28F, a via photobucket patterning scheme is performed as a first photobucketing process. In an embodiment, photobuckets are formed in all of the exposed openings2814ofFIG. 28E. Select ones of the photobuckets are removed to re-expose openings2814while other photobuckets2816are retained, e.g., by not exposing photobuckets2816to a lithography and development process used to open all other of the first photobuckets (in the specific case illustrated, three photobuckets are retained while one is removed).

Referring toFIG. 28G, the exposed portion of the blanket hardmask2802is then etched to provide first-time patterned hardmask2820. Additionally, the metal layer2800is etched through the opening to provide an etch trench2818in a first-time patterned metal layer2822. The first-time patterned metal layer2822includes a conductive via2824. Subsequent to the subtractive metal etch, the remaining photobuckets2816are removed to re-expose associated openings2814.

Referring toFIG. 28H, the trench2818and the openings2814are backfilled with a hardmask material. In an embodiment, a material similar to or the same as the material of the third hardmask2810is formed on the structure ofFIG. 28Gand planarized or etched back to provide deep hardmask region2826and shallow hardmask region2828. In one embodiment, deep hardmask region2826and shallow hardmask region2828are of the third material type (e.g., the material type of third hardmask2810).

FIGS. 28I-28Lare associated with a metal line cut or plug formation patterning process. Referring toFIG. 28I, the first hardmask2804is removed selective to the second hardmask2806, selective to the deep hardmask region2826and shallow hardmask region2828of the third material type, and selective to the fourth hardmask2812to provide openings2830exposing portions of the first-time patterned hardmask2820. In an embodiment, the first hardmask2804is removed selective to the second hardmask2806, selective to the deep hardmask region2826and shallow hardmask region2828of the third material type, and selective to the fourth hardmask2812using a selective etch or cleans process.

Referring toFIG. 28J, a cut or plug photobucket patterning scheme is performed as a second photobucketing process. In an embodiment, photobuckets are formed in all of the exposed openings2830ofFIG. 28I. Select ones of the photobuckets are removed to re-expose openings2830while other photobuckets2832are retained, e.g., by not exposing photobuckets2832to a lithography and development process used to open all other of the second photobuckets (in the specific case illustrated, three photobuckets are retained while one is removed). The removed photobuckets, at this stage, represent the locations where cuts or plugs will be in a final metallization layer. That is, in the second photobucket process, photobuckets are removed from locations where plugs or cuts will ultimately be formed.

Referring toFIG. 28K, the exposed portion of the first-time patterned hardmask2820is then etched to provide second-time patterned hardmask2834having a trench2836formed therein. Subsequent to the etching, the remaining photobuckets2832are removed to re-expose associated openings2830.

Referring toFIG. 28L, the trench2834and the openings2830are backfilled with a hardmask material. In an embodiment, a material similar to or the same as the material of the first hardmask2804is formed on the structure ofFIG. 28Kand planarized or etched back to provide deep hardmask region2838and shallow hardmask region2840. In one embodiment, deep hardmask region2838and shallow hardmask region2840are of the first material type (e.g., the material type of first hardmask2804).

Referring toFIG. 28M, the fourth hardmask2812is removed selective to the deep hardmask region2838and shallow hardmask region2840of the first material type, selective to the second hardmask2806, and selective to the deep hardmask region2826and shallow hardmask region2828of the third material type. In an embodiment, the fourth hardmask2812is removed selective to the deep hardmask region2838and shallow hardmask region2840of the first material type, selective to the second hardmask2806, and selective to the deep hardmask region2826and shallow hardmask region2828of the third material type using a selective etch or cleans process. A deep etch process is performed through the resulting openings and entirely through the second-time patterned hardmask2834to form third-time patterned hardmask2842, and entirely through the first-time patterned metal layer2822to form second-time patterned metal layer2844. Although not depicted, at this stage a second cut or plug patterning process may be performed.

Referring toFIG. 28N, the deep openings formed in association withFIG. 28Mare backfilled with a hardmask material. In an embodiment, a material similar to or the same as the material of the fourth hardmask2812is formed on the structure ofFIG. 28Mand planarized or etched back to provide deep hardmask regions2846. In one embodiment, deep hardmask regions2846are of the fourth material type (e.g., the material type of fourth hardmask2812). In an optional embodiment, as illustrated in association with2899ofFIG. 28S, described below, an ILD layer (such as a low-k dielectric layer) may first be filled and etch back to a level of the second-time patterned metal layer2844. The hardmask material of the fourth type (i.e., a shallow version of2846) is then formed on the ILD layer.

FIGS. 28O-28Rare associated with a conductive tab formation patterning process. Referring toFIG. 28O, the second hardmask2806is removed selective to the deep hardmask region2838and shallow hardmask region2840of the first material type, selective to the deep hardmask region2826and shallow hardmask region2828of the third material type, and selective to the deep hardmask regions2846of the fourth material type to provide openings2848exposing portions of the third-time patterned hardmask2842. In an embodiment, the second hardmask2806is removed selective to the deep hardmask region2838and shallow hardmask region2840of the first material type, selective to the deep hardmask region2826and shallow hardmask region2828of the third material type, and selective to the deep hardmask regions2846of the fourth material type using a selective etch or cleans process.

Referring toFIG. 28P, a conductive tab photobucket patterning scheme is performed as a third photobucketing process. In an embodiment, photobuckets are formed in all of the exposed openings2848ofFIG. 28O. Select ones of the photobuckets are removed to re-expose openings2848while other photobuckets2850are retained, e.g., by not exposing photobuckets2850to a lithography and development process used to open all other of the third photobuckets (in the specific case illustrated, one photobucket2850is retained while three are removed). The removed photobuckets, at this stage, represent the locations where conductive tabs will not be formed in a final metallization layer. That is, in the third photobucket process, photobuckets2850are retained locations where conductive tabs will ultimately be formed.

Referring toFIG. 28Q, the exposed portion of the third-time patterned hardmask2842is then etched through openings2848to provide fourth-time patterned hardmask2852having trenches2854formed therein. Subsequent to the etching, the remaining photobucket2850is removed.

Referring toFIG. 28R, the deep hardmask region2838and shallow hardmask region2840of the first material type is removed selective to the deep hardmask region2826and shallow hardmask region2828of the third material type and selective to the deep hardmask regions2846of the fourth material type to further expose portions of the fourth-time patterned hardmask2852. In an embodiment, the deep hardmask region2838and shallow hardmask region2840of the first material type is removed selective to the deep hardmask region2826and shallow hardmask region2828of the third material type and selective to the deep hardmask regions2846of the fourth material type using a selective etch or cleans process.

Referring toFIG. 28S, a deep etch process is performed through the resulting openings and entirely through the second-time patterned metal layer2844to form third-time patterned metal layer2856. At this stage, in the case that an ILD layer2899is formed at the operation associated withFIG. 28N, as described above in an optional embodiment, portions of such an ILD layer2899are viewable in the structure ofFIG. 28S.

Referring to part (a) ofFIG. 28T, in an embodiment, hardmask removal of remaining hardmask portions2828,2846,2852ofFIG. 28Sis performed, and the structure is subsequently planarized. In one embodiment, the height of deep hardmask region2826is reduced, but the region is not all together removed, to form via cap2858and ILD2860. Additionally, a plug region2862is formed. In one embodiment, ILD2899is formed in association withFIG. 28N, and in one such embodiment plug region2862includes a material different than ILD2899. In another embodiment, ILD2899is not formed in association withFIG. 28N, and the entire portions of ILD2860and plug2862are formed at the same time and with a same material, e.g., using an ILD back-fill process. In an embodiment, the metallization portion of the structure includes metal lines2864, a conductive via2824(having via cap2858thereon), and a conductive tab2866, as is depicted in part (a) ofFIG. 28T.

Referring to part (a) ofFIG. 28T, in an embodiment, an ILD backfill2861is formed on the structure ofFIG. 28S. In one such embodiment, an ILD film is deposited and then etched back to provide the structure of part (b) ofFIG. 28T. In an embodiment, leaving the hardmasks ofFIG. 28Sin place, templating of a next metallization layer may be performed. That is, the topography with the leave-behind hard masks may be used to template the next layer patterning process.

In either case, whether part (a) or (b) ofFIG. 28T, embodiments described herein include a leave-behind hardmask material (2858or2826) above a conductive via2824of a final metallization layer in a semiconductor structure. Additionally, referring again toFIG. 28A-28T, it is to be appreciated that the order for cut, via, and tab patterning may be interchangeable. Also, while the exemplary process flow shows one cut, one via, and one tab pass, multiple passes of each type of patterning may be performed.

Referring again to part (a) ofFIG. 28T, in an embodiment, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer2860. A plurality of conductive lines2864is disposed in the ILD layer2860along a first direction. A conductive tab2866couples two of the plurality of conductive lines2864along a second direction orthogonal to the first direction.

Such an arrangement as depicted inFIG. 28Tmay not otherwise be achievable by conventional lithographic processing at either small pitch, small width, or both. Also, self-alignment may not be achievable with a conventional processing scheme. Furthermore, arrangements as depicted inFIG. 28Tmay not otherwise be achievable in cases where a pitch division scheme is used to ultimately provide a pattern for the conductive lines2864.

In an embodiment, the conductive tab2866is continuous, but not contiguous, with the two of the plurality of conductive lines2864. In an embodiment, the conductive tab2866is co-planar with the two of the plurality of conductive lines2866. In an embodiment, the BEOL metallization layer further includes a plug of dielectric material2862disposed at an end of one of the plurality of conductive lines2866. In one embodiment, the BEOL metallization layer further includes a conductive via.

The structures ofFIG. 28Tmay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structures ofFIG. 28Tmay represent the final metal interconnect layer in an integrated circuit. Referring again toFIG. 28T, such self-aligned fabrication by a subtractive photobucket approach may be continued to fabricate a next metallization layer. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

In accordance with an embodiment of the present disclosure, resist tailoring for tolerance of exposure misalignment is described. Resist tailoring may include one or more of an internal quench, a grafted layer quench, or a layer-on-top quench. One or more embodiments described herein are directed to two-stage bake photoresists with releasable quenchers. Applications may be directed toward one or more of extreme ultra-violet (EUV) lithography, general lithography applications, solutions for overlay issues, and general photoresist technologies. In an embodiment, materials are described that are suitable for improving performance of photo-bucket-based approaches. In such an approach, a resist material is confined to a pre-patterned hardmask. Select ones of the photobuckets are then removed using a high-resolution lithography tool, e.g., an EUV lithography tool. Specific embodiments may be implemented to improve uniformity of the resist material response across a given photobucket.

To provide context, one goal in a photobucket approach may be the ability to first diffuse any EUV-released acids across an exposed photobucket to improve the uniformity of the resist response across the selected bucket. In past approaches, this has been achieved by the use of special materials which enable the acid to diffuse across the photobucket at a low enough temperature to avoid a solubility-switch reaction instigated from these acids. However, the action of another resist component, namely the quencher, may prevent such an advantage from being fully realized. In particular, the quencher may neutralize the acids before they are able to diffuse or spread across a given photobucket. Addressing such issues, in accordance with one or more embodiments described herein, a standard quencher is replaced with a quencher that can be released by an ultra-violet (UV) exposure or the like, providing the ability to avoid premature acid neutralization.

More particularly, in accordance with one or more embodiments described herein, a photobucket resist material including a UV-released quencher is implemented to effectively provide a “2-stage PEB” where the effect of EUV exposure is effectively averaged across a given photobucket. Such embodiments may enable a “digital” bucket response, in which the entire photobucket either clears out or does not. In specific embodiments, such a response is more tolerant to edge-placement errors, in which an aerial image does not perfectly align to the photobucket grid.

To exemplify one or more of the concepts involved herein,FIGS. 29A-29Cillustrates cross-sectional views and corresponding plan views of various operations in a method of patterning using photobuckets including a two-stage bake photoresist, in accordance with an embodiment of the present disclosure.

Referring toFIG. 29A, a pre-patterned hardmask2904is disposed above a substrate2902. The pre-patterned hardmask2904has openings filled with a two-stage bake photoresist2906. The two-stage bake photoresist2906is confined to the openings in the pre-patterned hardmask2904, e.g., to provide a grid of potential via locations.

Referring toFIG. 29B, select ones of the photobuckets are subjected to an exposure2907from a lithography tool. The two-stage bake photoresist2906is exposed with a lithography tool, e.g., an EUV lithography tool, to select which vias to open. In an embodiment, alignment between the lithography tool and the pre-patterned hardmask2904grid is imperfect resulting in an asymmetry of exposure in the target bucket and/or partial exposure in the neighboring bucket. As seen in the plan view, the exposure2907is a displaced aerial image2908.

Referring toFIG. 29C, although the exposure ofFIG. 29Bmay have involved mis-alignment and partial exposure of non-selected photobuckets, only the selected photobuckets are cleared to form openings2920, leaving unselected photobuckets as closed photobuckets2912. In one embodiment, the process used to ensure only select photobuckets are ultimately opened, following exposure2907of select regions of the two-stage bake photoresist2906, all of the two-stage bake photoresist2906is first baked for acid diffusion. An ultra-violet (UV) quench release is then performed for acid neutralization. A second bake is then performed for a solubility switch, as described in greater detail below. In a specific embodiment, the photoacids released from the first bake operation are diffused throughout the photobucket. The UV flood exposure releases quenchers and then the final solubility-switch bake is performed. The process is elaborated below in association withFIGS. 30A-30E.

As a result, the select locations which receive a greater exposure are ultimately cleared to provide open photobucket locations2920following development. The non-selected locations which receive no exposure, or only partial exposure but to a lesser extent in the case of mis-alignment, remain as closed photobucket locations2912following development.

To exemplify a contrasting scenario where a conventional photoresist is used,FIG. 1Dillustrates a cross-sectional view of a conventional resist photobucket structure following photobucket development after a mis-aligned exposure. A photobucket region2954is shown as only partially cleared2950with some residual photoresist2952remaining. In the case that the photobucket2954is a selected photobucket, the misaligned exposure2907only partially clears the photobucket, which may lead to subsequent poor quality fabrication of conductive structure in such locations. In the case that the photobucket2954is a non-selected photobucket, some unwanted opening2950occurs, potentially leading to subsequent formation of conductive structures in unwanted locations.

In a more detailed process description,FIGS. 30A-30Eillustrates schematic views of various operations in a method of patterning using photobuckets including a two-stage bake photoresist, in accordance with an embodiment of the present disclosure.

Referring toFIG. 30A, first3002and second3004photobuckets each include a photolyzable composition including an acid-deprotectable photoresist material, a photo-acid-generating (PAG) component3010, and a photo-base-generating component3012. A misaligned EUV or e-beam exposure3006is performed on a selected photobucket3002and a non-selected photobucket3004, which heavily exposes the selected photobucket3002and partially exposes the non-selected photobucket3004but to a lesser extent. In a specific embodiment, the photo-base-generating component3012is a UV-releasable quencher.

Referring toFIG. 30B, a first bake is performed. In one embodiment, the first bake is performed at a temperature too low to cause a solubility switch. In one such embodiment, the bake is a diffusion only bake leading to diffused materials3020and3022of photobuckets3002and3004, respectively.

Referring toFIG. 30C, quenchers3014are released to form materials3024and3026for photobuckets3002and3004, respectively. In one embodiment, the quenchers3014are UV-released quenchers. In a specific such embodiment, the UV-released quenchers are released by UV flood exposure, e.g., a 365 nm exposure. In an embodiment, the photobuckets3002and3004are both exposed to the flood exposure to the same extent.

Referring toFIG. 30D, a second bake is performed to provide materials3028and3030of photobuckets3002and3004, respectively. In an embodiment, the second bake is generates a solubility switch, in which a sub-critical acid concentration quenched. In this manner, there are essentially no local acid concentrations. That is, deprotection of part of an unintended only partially exposed photobucket does not occur.

Referring toFIG. 30E, the photobuckets3002and3004are subjected to a development process. The selected photobucket3002is cleared upon development to provide a cleared photobucket3032. The non-selected photobucket3004is not cleared upon development and remains a blocked photobucket3034. In this way, even in the event of a mis-aligned exposure, a digital photobucket response (open or closed only, without partial open) is achieved.

It is to be appreciated that not all embodiments require a single composition to achieve a two-stage bake photoresist. In a first alternative example,FIGS. 30A′ illustrates a schematic view of an operation in another method of patterning using photobuckets, in accordance with an embodiment of the present disclosure. Referring toFIG. 30A′, first3002′ and second3004′ photobuckets each include a grafted photo-base-generating component3050along a bottom and sidewalls of the first3002′ and second3004′ photobuckets. A photolyzable composition is formed within the grafted photo-base-generating component3050. The photolyzable composition includes an acid-deprotectable photoresist material and a photo-acid-generating (PAG) component3010′. An exposure3006′ and multi-stage development process may then performed similar to the above described approaches.

In a second alternative example,FIGS. 30A″ illustrates a schematic view of an operation in another method of patterning using photobuckets, in accordance with an embodiment of the present disclosure. Referring toFIG. 30A″, first3002″ and second3004″ photobuckets each include a photolyzable composition including an acid-deprotectable photoresist material and a photo-acid-generating (PAG) component3010″. Subsequent to performing a first bake, a layer3060including a base-generating component is formed on the first3002″ and second3004″. The photobuckets3002″ and3004″ are then exposed to ultraviolet (UV) radiation. In this case, the base component does not need to be introduced via a photo-base generator, but may rather be deposited in a later process operation, e.g., by vapor deposition of a base layer or exposure to basic atmosphere NMP.

Applications of the above described photoresist compositions and approaches may be implemented for to create regular structures covering all possible via (or plug) locations, followed by selective patterning of only the desired features. To provide further material details, in an embodiment, referring again toFIGS. 30A-30E, photobuckets3002and3004include photolyzable composition. The photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength. The photolyzable composition also includes a photo-acid-generating (PAG) component having substantial transparency at the wavelength. The photolyzable composition includes a base-generating component having substantial absorptivity at the wavelength. In alternative embodiments, the acid-deprotectable photoresist material is not substantially transparent at the wavelength.

In an embodiment, the base-generating component is one selected from the group consisting of a photo-base-generating component, an electron-base-generating component, a chemical-base-generating component, and a UV-base-generating component. In one embodiment, the base-generating component is a sonication-base-generating component. In an embodiment, the base-generating component is UV-absorbing. In an embodiment, the base-generating component includes a low-energy UV chromophore. In a specific such embodiment, the low-energy UV chromophore is selected from the group consisting of anthracenylcarbamates, naphthalenylcarbamates, 2-nitrophenylcarbamates, arylcarbamates, coumarins, phenylglyoxylic acid, substituted acetophenones and benzophenones. In one embodiment, the low-energy UV chromophore is a photo-released amine. In an embodiment, the base-generating component includes a material selected from the group consisting of N,N-dicyclohexyl-2-nitrophenylcarbamate, N,N-disubstituted carbamates and mono-substituted carbamates.

In an embodiment, the PAG component includes a material selected from the group consisting of triethyl, trimethyl and other trialkylsulfonates, where the sulfonate group is selected from the group consisting of trifluoromethylsulfonate, nonanfluorobutanesulfonate, and p-tolylsulfonate, or other examples containing —SO3sulfonate anion bound to organic group. In an embodiment, the acid-deprotectable photoresist material is an acid-deprotectable material selected from the group consisting of a polymer, a molecular glass, a carbosilane and a metal oxide. In one embodiment, a metal oxide is used and a release base is not needed. In an embodiment, the acid-deprotectable photoresist material includes a material selected from the group consisting of a polyhydroxystyrene, a polymethacrylate, small molecular weight molecular glass versions of a polyhydroxystyrene or a polymethacrylate which contain ester functionality sensitive to acid-catalyzed deprotection to carboxylic acid, a carbosilane, and a metal oxide possessing functionality sensitive to acid catalyzed deprotection or cross-linking.

In an embodiment, the wavelength is approximately 365 nm. In an embodiment, the acid-deprotectable photoresist material is substantially absorbing at a wavelength of approximately 13.5 nanometers. In an embodiment, the acid-deprotectable photoresist material is substantially absorbing at an energy approximately in the range of 5-150 keV. In an embodiment, a molar ratio of the PAG component to the base-generating component is at least 50:1.

Referring again toFIGS. 30A-30E, 30A′ and30A″, in accordance with an embodiment of the present disclosure, a method of selecting a photobucket for semiconductor processing includes providing a structure having a first photobucket3002neighboring a second photobucket3004. The structure is exposed to extreme ultraviolet (EUV) or e-beam radiation3006, where the first photobucket3002is exposed to the EUV or e-beam radiation3006to a greater extent than the second photobucket3004. Subsequent to exposing the structure to EUV or e-beam radiation3006, a first bake of the first and second photobuckets is performed as is described in association withFIG. 30B. Subsequent to performing the first bake, the structure to ultraviolet (UV) radiation, where the first photobucket is exposed to the UV radiation to approximately the same extent as the second photobucket, as is described in association withFIG. 30C. Subsequent to exposing the structure to UV radiation, a second bake of the first and second photobuckets is performed as is described in association withFIG. 30D. Subsequent to performing the second bake, the structure is developed. The developing opens the first photobucket and leaves the second photobucket closed as is described in association with FIG.30E.

In an embodiment, exposing the structure to extreme ultraviolet (EUV) or e-beam radiation includes exposing the structure to energy having a wavelength approximately 13.5 nanometers. In another embodiment, exposing the structure to extreme ultraviolet (EUV) or e-beam radiation includes exposing the structure to energy in the range of 5-150 keV. In an embodiment, exposing the structure to UV radiation includes exposing the structure to energy having a wavelength approximately 365 nanometers. In an embodiment, the first bake is performed at a temperature approximately in the range of 50-120 degrees Celsius for a duration of approximately in the range of 0.5-5 minutes. In an embodiment, the second bake is performed at a temperature approximately in the range of 100-180 degrees Celsius for a duration of approximately in the range of 0.5-5 minutes.

In an embodiment, referring specifically toFIG. 30A, the first and second photobuckets each include a photolyzable composition including an acid-deprotectable photoresist material, a photo-acid-generating (PAG) component, and a photo-base-generating component. In one such embodiment, exposing the structure to extreme ultraviolet (EUV) or e-beam radiation includes activating the PAG component. The first bake diffuses acid formed from activating the PAG component throughout the first and second photobuckets. Exposing the structure to UV radiation includes activating the photo-base-generating component. The second bake quenches a total amount of acid formed in the second photobucket with base generated from the photo-base-generating component but does not quench a total amount of acid formed in the first photobucket.

In another embodiment, referring specifically toFIG. 30A′, the first and second photobuckets each include a grafted photo-base-generating component along a bottom and sidewalls of the first and second photobuckets and a photolyzable composition formed within the grafted photo-base-generating component. The photolyzable composition includes an acid-deprotectable photoresist material and a photo-acid-generating (PAG) component. In one such embodiment, exposing the structure to extreme ultraviolet (EUV) or e-beam radiation includes activating the PAG component. The first bake diffuses acid formed from activating the PAG component throughout the first and second photobuckets. Exposing the structure to UV radiation includes activating the grafted photo-base-generating component. The second bake quenches a total amount of acid formed in the second photobucket with base generated from the photo-base-generating component but does not quench a total amount of acid formed in the first photobucket.

In another embodiment, referring specifically toFIG. 30A″, the first and second photobuckets each include a photolyzable composition including an acid-deprotectable photoresist material and a photo-acid-generating (PAG) component. The method further includes, subsequent to performing the first bake and prior to exposing the structure to ultraviolet (UV) radiation, forming a layer including a base-generating component on the first and second photobuckets. In one such embodiment, exposing the structure to extreme ultraviolet (EUV) or e-beam radiation includes activating the PAG component. The first bake diffuses acid formed from activating the PAG component throughout the first and second photobuckets. Exposing the structure to UV radiation includes activating the base-generating component. The second bake quenches a total amount of acid formed in the second photobucket with base generated from the base-generating component but does not quench a total amount of acid formed in the first photobucket.

In any of the above described cases, in an embodiment, developing the structure includes, in the case of positive tone development, immersion or coating with standard aqueous TMAH developer (e.g., in a concentration range from 0.1M-1M) or other aqueous or alcoholic developer based on tetraalkylammonium hydroxides for 30-120 seconds followed by rinse with DI water. In another embodiment, in the case of negative tone development, developing the structure includes immersion or coating with organic solvents such as cyclohexanone, 2-heptanone, propylene glycol methylethyl acetate or others followed by rinse with another organic solvent such as hexane, heptane, cyclohexane or the like.

In an exemplary embodiment, approaches described above build on approaches using so-called photobuckets, in which every possible feature, e.g. via, is pre-patterned into a substrate. Then, a photoresist is filled into patterned features and the lithography operation is merely used to choose select vias for via opening formation. In a particular embodiment, a lithography operation is used to define a relatively large hole above a plurality of photobuckets that include a two-stage bake photoresist, as described above. The two-stage bake photoresist photobucket approach allows for larger critical dimensions (CD)s and/or errors in overlay while retaining the ability to choose the via of interest.

In accordance with an embodiment of the present disclosure, image tone reversal of resist, e.g., for photobuckets, is described. One or more embodiments described herein are directed to a class of materials with special properties to enable pattern reversal (e.g., holes reversed to posts), and related processing approaches and the structures resulting there from. The class of materials may be a class of soft materials, e.g., photoresist-like materials. As a general approach, a resist-like material is deposited in a pre-patterned hardmask. The resist-like material may then be selected out with a high-resolution lithography tool, e.g., an extreme ultra-violet (EUV) processing tool. On the other hand, resist-like material may instead be left to remain permanently in a finally fabricated structure, e.g., as an inter-layer dielectric (ILD) material or structure (“plugs”) that form breaks between metal lines. Overlay (edge placement) problems anticipated for next generation plug patterning may be addressed by one or more approaches described herein.

More specifically, one or more embodiments described herein are directed to use of a spin-on dielectric (e.g., ILD) with particular properties that enable the filling of holes (“buckets”) in a patterned photoresist layer without destroying the photoresist layer pattern. First, the spin-on dielectric material is introduced in a solvent which does not dissolve or cause intermixing of the photoresist and the dielectric material. It is to be appreciated that good fillability of holes is required. Initial cross-linking (or setting) of the spin-on dielectric film is accomplished under conditions where the photoresist and spin-on dielectric do not intermix and lose pattern information. Once the pattern is reversed, the material within the bucket is then converted through baking/curing to a dielectric with desired properties such as k-value, modulus, etch selectivity etc. Although not limited to such material, a spin-on dielectric material based on a 1,3,5-trisilacyclohexane building block may be implemented to satisfy the above criteria. Cross-linking with loss of solubility of such a material (or other silicon based dielectrics) can be initiated either thermally, or at lower temperatures, by use of acid, base or Lewis acid catalyst processes. In one embodiment, such low temperature catalysis is critical for the implementation of approaches described herein.

In an embodiment, approaches described herein involves taking a best imaging performance (e.g., which comes from positive tone materials) in order to produce a negative-tone pattern, where the final film possesses sought after material properties. The final material properties may be akin to those of a high performance low-k dielectric/ILD material). By contrast, state-of the art options for direct patterning of dielectric films are limited and not expected to exhibit the necessary lithographic performance to be manufacturable for future scaled down technology generations.

As described in greater detail below in association withFIGS. 31 and 32A-32H, in accordance with embodiments described herein, trenches pre-patterned in an ILD material are filled with chemically amplified photoresist. Using high resolution lithography (e.g., EUV), selected holes within the trenches are exposed and removed via conventional positive tone processing. At this stage, the empty holes are treated with a pre-catalyst layer. In one such embodiment, the pre-catalyst layer is a self-assembled monolayer (SAM)-containing attached catalyst layer. The resulting decorated holes are then filled with dielectric precursor, with accompanying overburden. The localization (or close proximity) of the catalyst in the holes leads to selective cross-linking and setting of the dielectric in the holes only. Overburden and photoresist are removed followed by final curing of dielectric (if needed) and metallization processes.

In accordance with an embodiment of the present disclosure, a key feature of approaches described herein involves the accommodation of varying pattern density with varying thickness of overburden. In one embodiment, such accommodation is enabled since cross-linking only occurs in/near the hole and an overburden ultimately removed by planarization (e.g., by chemical mechanical polishing). In an embodiment, selective cross-linking of a dielectric material in a hole is effected without effecting the same in regions of overburden. In a particular embodiment, following positive tone lithographic patterning and development, a hydrophilic Si—OH terminated surface is exposed in the holes and anywhere photoresist has been removed. The hydrophilic surface may be present prior to photoresist coating or created during, e.g., tetramethylammonium hydroxide (TMAH) development or subsequent rinses. It is to be appreciated that photoresist that has not been exposed and developed will maintain characteristic mildly or strongly hydrophobic nature and, thus, the patterning process effectively creates hydrophilic and hydrophobic domains.

In an embodiment, the exposed hydrophilic surface is functionalized with a surface grafting agent which carries either catalyst or pre-catalyst needed to cross-link a dielectric material. Subsequent coating of dielectric leads to the filling of holes with overburden, as described above, and as illustrated in greater detail below. Upon activation and controlled diffusion of pre-catalyst with, e.g., a low temperature bake, the dielectric material is selectively cross-linked in the hole with minimal cross-linking occurring in the overburden, i.e., directly above the hole. The overburden dielectric material can then be removed using casting solvent or dissolution in another solvent. It is to be appreciated that the removal process may also remove photoresist, or photoresist can be removed with another solvent or by an ashing process. In an embodiment, with the tone reversed, the dielectric material may be baked/cured at a relatively higher temperature prior to metallization or other processing.

In accordance with one or more embodiments described herein, there are several approaches for installing catalyst or pre-catalyst in a hole. For some dielectric materials, strong Bronsted acids are required. In other cases, strong Lewis acids may be employed. For ease of description herein, the term “acid” is used to refer to both scenarios. In an embodiment, direct adsorption of catalyst or pre-catalyst is employed. In this scenario, the catalyst is coated onto a hydrophilic surface and held strongly via H-bonding or other electrostatic interaction. Subsequent coating of a dielectric material leads to acid and dielectric precursor localized in the hole, where thermal or other activation initiates desired cross-linking chemistry. In an exemplary embodiment, the reaction of an Si—OH rich surface with the strong Lewis acid B(C6F5)3leading to formation of Si—O—B(C6F5)3H+. This resulting Lewis acid is used to catalyze cross-linking of hydrosilane precursor molecules at relatively lower temperature than non-catalyzed processes. In one embodiment, the large size of the catalyst employed minimizes diffusion into the overburden regions.

In another embodiment, approaches involve covalent adhesion of a catalyst or pre-catalyst via silane chemistries such as chloro-, alkoxy-, and amino silanes or other surface grafting groups that may include siloxanes, silyl chlorides, alkenes, alkynes, amines, phosphines, thiols, phosphonic acids or carboxylic acids. In this scenario, a catalyst or precatalyst is covalently linked to a grafting agent. For example, well-known acid generators (e.g., photo- or thermal) based on onium salts can be attached to siloxanes (e.g., [(MeO)3Si—CH2CH2CH2SR2][X], where R=alkyl or aryl groups and X=weakly coordinating anions such as triflate, nonaflate, H—B(C6F5)3, BF4, etc.). The catalyst or pre-catalyst can be either selectively attached to the ILD of interest, or selectively removed from the resist using thermal, dry etch, or wet etch processes. In yet another embodiment, the catalyst or pre-catalyst is introduced prior to photoresist coating using similar techniques. In this scenario, to be effective, the grafted material must not interfere with lithography and must survive subsequent processing.

As an exemplary vehicle for demonstrating the concepts described herein,FIG. 31illustrates an angled view of an alternating pattern of inter-layer dielectric (ILD) lines and resist lines, with a hole formed in one of the resist lines, in accordance with an embodiment of the present disclosure. Referring toFIG. 31, a pattern3100includes alternating ILD lines3102and resist lines3104. A hole3106is formed in one of the resist lines3104, e.g., by conventional lithography. As described below, in association withFIGS. 32A-32H, a pattern such as the pattern3100can be subjected to tone reversal.

In an exemplary process flow,FIGS. 32A-32Hillustrate cross-sectional views in a fabrication process involving image tone-reversal with a dielectric using bottom-up cross-linking, in accordance with an embodiment of the present disclosure.

FIG. 32Aillustrates a cross-sectional view of a starting structure following pre-patterning of trenches3204in an ILD material3202. Select ones of the trenches3204are filled with a chemically amplified photoresist3206, while others have been processed to provide unfilled trenches (or unfilled trench portions, as shown inFIG. 31). For example, in one embodiment, using high resolution lithography (e.g., extreme ultra-violet (EUV) lithography), selected holes within the trenches3204are exposed and removed via conventional positive tone processing.

Although not depicted for simplicity, it is to be appreciated that the unfilled trenches (or holes formed within filled trenches) may expose underlying features, such as underlying metal lines, in region3208. Furthermore, in an embodiment, the starting structure may be patterned in a grating-like pattern with trenches spaced at a constant pitch and having a constant width. The pattern, for example, may be fabricated by a pitch halving or pitch quartering approach. Some of the trenches may be associated with underlying vias or lower level metallization lines.

FIG. 32Billustrates a cross-sectional view of the structure ofFIG. 32Afollowing treatment of the empty trenches or holes with a pre-catalyst layer3210which, in one embodiment, is a self-assembled monolayer (SAM)-containing catalyst material. In one such embodiment, as depicted, the pre-catalyst layer3210is formed on exposed portions of the ILD3202, but not on exposed portions of the resist3206or any exposed metal such as at regions3208. In an embodiment, the pre-catalyst layer3210is formed by exposing the structure ofFIG. 32Ato pre-catalyst-forming molecules in the vapor phase, or molecules dissolved in solvent. In one embodiment, the pre-catalyst layer is a layer of catalyst or pre-catalyst formed by direct adsorption, as described above. In another embodiment, the pre-catalyst layer3210is a layer of catalyst or pre-catalyst formed by covalent adhesion.

FIG. 32Cillustrates a cross-sectional view of the structure ofFIG. 32Bfollowing filling of the resulting decorated holes with a dielectric material3212. It is to be appreciated that the dielectric material3212has a portion3212A filling the trenches or holed and a portion3212B above the trenches or holes. The portions3212B is referred to herein as overburden. In one embodiment, the dielectric material3212is a spin-on dielectric material.

In an embodiment, the dielectric material3212is selected from a class of materials based on hydrosilane precursor molecules, where catalyst mediates reaction of Si—H bonds with cross-linkers such as water, tetraethoxyorthosilicate (TEOS), hexaethoxytrisilacyclohexane or similar multifunctional cross-linkers. In one such embodiment, the dielectric material3212includes trisilacyclohexanes which may subsequently be linked together by O groups. In other embodiments, alkoxy silane based dielectric precursors or silsesquioxane (SSQ) are used for the dielectric material3212.

FIG. 32Dillustrates a cross-sectional view of the structure ofFIG. 32Cfollowing cross-linking of the portions3212A of the dielectric material3212. In an embodiment, the localization (or close proximity) of the catalyst (e.g., pre-catalyst layer3210) in the unfilled trenches or holes leads to selective cross-linking to form cross-linked regions3214and setting of the portions3212A of the dielectric material3212in the holes only. That is, in an embodiment, the portions3212B of the dielectric material3212are not cross-linked. In an embodiment, the cross-linking used to form regions3214is effected by a thermal curing process, i.e., by heating.

In an embodiment, the dielectric material3212includes trisilacyclohexanes and the cross-linking used to form regions3214includes linking trisilacyclohexanes together by O groups. Referring toFIG. 33A, a trisilacyclohexane3300is illustrated. Referring toFIG. 33B, two cross-linked (XL) trisilacyclohexane molecules3300form a cross-linked material3320.FIG. 33Cillustrates an idealized representation of a linked trisilacyclohexane structure3340. It is to be appreciated that, in reality, structure3340is used to represent a complex mix of oligomers, but the common point is the H-capped trisilacyclohexane rings.

FIG. 32Eillustrates a cross-sectional view of the structure ofFIG. 32Dfollowing removal of the overburden regions3212B of the dielectric material3212.FIG. 32Fillustrates a cross-sectional view of the structure ofFIG. 32Efollowing removal of the resist3206selective to the cross-linked regions3214. In an embodiment, as is depicted, the resist3206is removed in a subsequent and different processing operation (such as a second wet chemical development operation) from the processing operation used to remove the overburden regions3212B of the dielectric material3212(such as a first wet chemical development operation). In another embodiment, however, the resist3206is removed in a same processing operation used to remove the overburden regions3212B of the dielectric material3212(such as a wet chemical development operation). In an embodiment, the remaining cross-linked regions3214are subjected to an additional curing process (e.g., additional heating following the cross-linking curing process). In one embodiment, the additional curing is performed following removal of the resist3206and the overburden regions3212B.

FIG. 32Gillustrates a cross-sectional view of the structure ofFIG. 32Ffollowing formation of a metal fill layer3216. The metal fill layer3216may be formed in the open trenches (or holes) fromFIG. 32F, and in overburden regions. The metal fill layer may be a single material layer, or may be formed from several layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, may be used to form metal fill layer3216. In an embodiment, the metal fill layer3216is composed of a conductive material such as, but not limited to, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au or alloys thereof.

FIG. 32Hillustrates a cross-sectional view of the structure ofFIG. 32Gfollowing planarization of the metal fill layer to form metal features3218(e.g., metal lines or vias). In an embodiment, the planarization of the metal fill layer3216to form metal features3218is performed using a chemical mechanical polishing process. An exemplary resulting structure is shown inFIG. 32H, where metal features3218alternate with cross-linked (dielectric) regions3214in an ILD material3202.

It is to be appreciated that the resulting structure ofFIG. 32Hmay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 32Hmay represent the final metal interconnect layer in an integrated circuit. Furthermore, it is to be appreciated that the above examples do not include etch-stop or metal capping layers in the Figures that may otherwise be necessary for patterning. However, for clarity, such layers are not included in the Figures since they do not impact the overall bottom-up fill concept.

With reference again toFIGS. 32A-32H, such a patterning scheme may be implemented as an integrated patterning approach that involves creating regular structures covering all possible locations, followed by selective patterning of only the desired features. The cross-lined regions3214represent a material that can remain in a final structure as an ILD between the ends of the metal lines (e.g., as plugs).

In accordance with an embodiment of the present disclosure, diagonal mask patterning is described. One or more embodiments described herein are directed to diagonal hardmask patterning for overlay improvements, particularly in the fabrication of back end of line (BEOL) features for semiconductor integrated circuits. Applications of patterning based on diagonal hardmasks may include, but need not be limited to, implementation in 193 nm immersion lithography, extreme ultraviolet (EUV) lithography, interconnect fabrication, overlay improvements, overlay budget, plug patterning, via patterning. Embodiments may be particularly useful for the self-aligned fabrication of BEOL structures.

In an embodiment, approaches described herein involve an integration scheme that tolerates increased via and plug overlay margin relative to existing approaches. In one such embodiment, all potential vias and plugs are pre-patterned and filled with resist to form a plurality of photobuckets. Subsequently, in a specific embodiment, EUV or 193 nm lithography is used to select certain of the via and plug locations for actual, ultimate, via and plug fabrication. In an embodiment, diagonal line patterning is used to increase nearest-neighbor distances resulting in an increase by a factor of the square root of two in overlay budget. More specifically, one or more embodiment described herein involves the use of a subtractive method to pre-form every via and plug using the trenches already etched. An additional operation is then used to select which of the vias and plugs to retain. Such operations are illustrated using photobuckets, although the selection process may also be performed using a more conventional resist expose and ILD backfill approach.

In an aspect, a diagonal hardmask approach may be implemented. As an example,FIGS. 34A-34Xillustrate portions of integrated circuit layers representing various operations in a method of self-aligned via and plug patterning using diagonal hardmasks, in accordance with an embodiment of the present disclosure. In each illustration at each described operation, cross-sectional and/or plan and/or angled views are shown. These views will be referred to herein as corresponding cross-sectional views, plan views and angled views.

FIG. 34Aillustrates a cross-sectional view of a starting structure3400following deposition, but prior to patterning, of a first hardmask material layer3404formed on an interlayer dielectric (ILD) layer3402, in accordance with an embodiment of the present disclosure. Referring toFIG. 34A, a patterned mask3406has spacers3408formed along sidewalls thereof, on or above the first hardmask material layer3404.

FIG. 34Billustrates a cross-sectional view of the structure ofFIG. 34Afollowing patterning of the first hardmask layer by pitch doubling, in accordance with an embodiment of the present disclosure. Referring toFIG. 34B, the patterned mask3406is removed and the resulting pattern of the spacers3408is transferred, e.g., by an etch process, to the first hardmask material layer3404to form a first patterned hardmask3410. In one such embodiment, the first patterned hardmask3410is formed with a grating pattern, as is depicted inFIG. 34B. In an embodiment, the grating structure of the first patterned hardmask3410is a tight pitch grating structure. In a specific such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed (mask3406), but the pitch may be halved by the use of spacer mask patterning, as is depicted inFIGS. 34A and 34B. Even further, although not shown, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the first patterned hardmask3410ofFIG. 34Bmay have hardmask lines spaced at a constant pitch and having a constant width.

FIG. 34Cillustrates a cross-sectional view of the structure ofFIG. 34Bfollowing formation of a second patterned hardmask, in accordance with an embodiment of the present disclosure. Referring toFIG. 34C, a second patterned hardmask3412is formed interleaved with the first patterned hardmask3410. In one such embodiment, the second patterned hardmask3412is formed by deposition of a second hardmask material layer (e.g., having a composition different from the first hardmask material layer3404). The second hardmask material layer is then planarized, e.g., by chemical mechanical polishing (CMP), to provide the second patterned hardmask3412.

FIG. 34Dillustrates a cross-sectional view of the structure ofFIG. 34Cfollowing deposition of a hardmask cap layer (third hardmask layer), in accordance with an embodiment of the present disclosure. Referring toFIG. 34D, a hardmask cap layer3414is formed on the first patterned hardmask3410and the first patterned hardmask3412. In one such embodiment, the material composition and etch selectivity of the hardmask cap layer3414is different as compared to the first patterned hardmask3410and the first patterned hardmask3412.

FIG. 34Eillustrates an angled view of the structure ofFIG. 34Dfollowing patterning of the hardmask cap layer, in accordance with an embodiment of the present disclosure. Referring toFIG. 34E, a patterned hardmask cap layer3414is formed on the first patterned hardmask3410and the first patterned hardmask3412. In one such embodiment, the patterned hardmask cap layer3414is formed with a grating pattern orthogonal to the grating pattern of the first patterned hardmask3410and the first patterned hardmask3412, as is depicted inFIG. 34E. In an embodiment, the grating structure formed by the patterned hardmask cap layer3414is a tight pitch grating structure. In one such embodiment, the tight pitch is not achievable directly through conventional lithography. For example, a pattern based on conventional lithography may first be formed, but the pitch may be halved by the use of spacer mask patterning. Even further, the original pitch may be quartered by a second round of spacer mask patterning. Accordingly, the grating-like pattern of the patterned hardmask cap layer3414ofFIG. 34Emay have hardmask lines spaced at a constant pitch and having a constant width. It is to be appreciated that description herein concerning forming and patterning a hardmask layer (or hardmask cap layer, such as hardmask cap layer3414) involves, in an embodiment, mask formation above a blanket hardmask or hardmask cap layer. The mask formation may involve use of one or more layers suitable for lithographic processing. Upon patterning the one or more lithographic layers, the pattern is transferred to the hardmask or hardmask cap layer by an etch process to provide a patterned hardmask or hardmask cap layer.

FIG. 34Fillustrates an angled view and corresponding plan view of the structure ofFIG. 34Efollowing further patterning of the first patterned hardmask, in accordance with an embodiment of the present disclosure. Referring toFIG. 34F, using the patterned hardmask cap layer3414as a mask, the first patterned hardmask3410is further patterned to form first patterned hardmask3416. The second patterned hardmask3412is not further patterned in this process. In an embodiment, the first patterned hardmask3410is patterned to a depth sufficient to expose regions of ILD layer3402as is depicted inFIG. 34F.

FIG. 34Gillustrates a plan view of the structure ofFIG. 34Ffollowing removal of the hardmask cap layer and formation of a fourth hardmask layer, in accordance with an embodiment of the present disclosure. Referring toFIG. 34G, the hardmask cap layer (third hardmask layer)3414is removed, e.g., by a wet etch process, dry etch process, or CMP process. A fourth hardmask layer3418is formed on the resulting structure by, in one embodiment, a deposition and CMP process. In one such embodiment, the fourth hardmask layer3418is formed by deposition of a material layer different from the material of the second patterned hardmask layer3412and the first patterned hardmask layer3416.

FIG. 34Hillustrates a plan view of the structure ofFIG. 34Gfollowing deposition and patterning of a first diagonal hardmask layer, in accordance with an embodiment of the present disclosure. Referring toFIG. 34H, a first diagonal hardmask layer3420is formed on the fourth hardmask layer3418, the second patterned hardmask layer3412, and the first patterned hardmask layer3416arrangement ofFIG. 34G. In an embodiment, the first diagonal hardmask layer3420has a pattern essentially or highly symmetrically diagonal, e.g., at 45 degrees relative to the grating structure of the second pattern hardmask layer3412, to cover alternate lines of the fourth hardmask layer3418. In an embodiment, the diagonal pattern of the first diagonal hardmask layer3420is printed at minimum critical dimension (CD), i.e., without the use of pitch halving or pitch quartering. It is to be appreciated that the individual lines may be printed even larger than minimum CD so long as some area of adjacent rows of the fourth hardmask layer3418remains revealed. Regardless, the grating-like pattern of the first diagonal hardmask layer3420ofFIG. 34Hmay have hardmask lines spaced at a constant pitch and having a constant width. It is to be appreciated that description herein concerning forming and patterning a diagonal hardmask layer (such as the first diagonal hardmask layer3420) involves, in an embodiment, mask formation above a blanket hardmask layer. The mask formation may involve use of one or more layers suitable for lithographic processing. Upon patterning the one or more lithographic layers, the pattern is transferred to the hardmask layer by an etch process to provide a diagonally patterned hardmask layer. In a particular embodiment, the first diagonal hardmask layer is a carbon-based hardmask layer.

FIG. 34Iillustrates a plan view of the structure ofFIG. 34Hfollowing removal of revealed regions of the fourth hardmask layer, in accordance with an embodiment of the present disclosure. Referring toFIG. 34I, using the first diagonal hardmask layer3420as a mask, revealed regions of the fourth hardmask layer3418are removed. In one such embodiment, the revealed regions of the fourth hardmask layer3418are removed by an isotropic etch process (e.g., a wet etch process or non-anisotropic plasma etch process) such that any partial exposure leads to full removal of the partially revealed block of fourth hardmask material. In one embodiment, regions where the fourth hardmask layer3418have been removed reveal portions of the ILD layer3402, as is depicted inFIG. 34I.

FIG. 34Jillustrates a plan view of the structure ofFIG. 34Ifollowing removal of the first diagonal hardmask layer, in accordance with an embodiment of the present disclosure. Referring toFIG. 34J, the first diagonal hardmask layer3420is removed to reveal the first patterned hardmask layer3416and the second patterned hardmask layer3412. Also revealed are the portions of the fourth hardmask layer3418that were protected from isotropic etching by the first diagonal hardmask layer3420. Accordingly, along each alternate row or down each alternate column of the resulting grid-like pattern ofFIG. 34J, a region of the fourth hardmask layer3418is alternated with a revealed region of the underlying ILD layer3402. That is, the result is a checkerboard pattern of ILD layer3402regions and fourth hardmask layer regions3418. As such, an increase by a factor the square root of two is achieved in the nearest neighbor distance3422(shown as distance in direction b). In a particular embodiment, the first diagonal hardmask layer3420is a carbon-based hardmask material and is removed with a plasma ashing process.

FIG. 34Killustrates a plan view of the structure ofFIG. 34Jfollowing first plurality of photobucket formation, in accordance with an embodiment of the present disclosure. Referring toFIG. 34K, a first plurality of photobuckets3424is formed in openings above the ILD layer3402such that no portion of the ILD layer3402remains revealed. The photobuckets3424, at this stage, represent a first half of all possible via locations in a resulting metallization layer.

FIG. 34Lillustrates a plan view and corresponding cross-sectional view (taken along the a-a′ axis) of the structure ofFIG. 34Kfollowing photobucket exposure and development to form selected via locations, and subsequent via opening etch into the underlying ILD, in accordance with an embodiment of the present disclosure. Referring toFIG. 34Lselect photobuckets3424are exposed and removed to provide selected via locations3426. The via locations3426are subjected to a selective etch process, such as a selective plasma etch process, to extend via openings into the underlying ILD layer3402, forming patterned ILD layer3402′. The etching is selective to remaining, unexposed, photobuckets3424, selective to the first patterned hardmask layer3416, selective to the second patterned hardmask layer3412, and selective to the fourth hardmask layer3418.

FIG. 34Millustrates a plan view and corresponding cross-sectional view (taken along the b-b′ axis) of the structure ofFIG. 34Lfollowing removal of the remaining photobuckets and subsequent formation of a fifth hardmask material, in accordance with an embodiment of the present disclosure. Referring toFIG. 34M, the remaining of the first plurality of photobuckets3424are removed, e.g., by a selective etch or ash process. All openings revealed (e.g., openings formed upon removal of photobuckets3424along with the via locations3426) are then filled with a hardmask material3428, such as a carbon-based hardmask material.

FIG. 34Nillustrates a plan view and corresponding cross-sectional view (taken along the c-c′ axis) of the structure ofFIG. 34Mfollowing removal of the remaining regions of the fourth hardmask layer, in accordance with an embodiment of the present disclosure. Referring toFIG. 34N, all remaining regions of the fourth hardmask layer3418are removed, e.g., by a selective etch or ash process. In one embodiment, regions where the remaining fourth hardmask layer3418have been removed reveal portions of the patterned ILD layer3402′, as is depicted inFIG. 34N.

FIG. 34Oillustrates a plan view and corresponding cross-sectional view (taken along the d-d′ axis) of the structure ofFIG. 34Nfollowing second plurality of photobucket formation, in accordance with an embodiment of the present disclosure. Referring toFIG. 34O, a second plurality of photobuckets3430is formed in openings above the patterned ILD layer3402′ such that no portion of the patterned ILD layer3402′ remains revealed. The photobuckets3430, at this stage, represent a second half of all possible via locations in a resulting metallization layer.

FIG. 34Pillustrates a plan view and corresponding cross-sectional view (taken along the e-e′ axis) of the structure ofFIG. 34Ofollowing photobucket exposure and development to form selected via locations, and subsequent via opening etch into the underlying ILD, in accordance with an embodiment of the present disclosure. Referring toFIG. 34P, select photobuckets3430are exposed and removed to provide selected via locations3432. The via locations3432are subjected to a selective etch process, such as a selective plasma etch process, to extend via openings into the underlying patterned ILD layer3402′, forming further patterned ILD layer3402″. The etching is selective to remaining, unexposed, photobuckets3430, selective to the first patterned hardmask layer3416, selective to the second patterned hardmask layer3412, and selective to the hardmask material3428.

FIG. 34Qillustrates a plan view and corresponding cross-sectional view (taken along the f-f′ axis) of the structure ofFIG. 34Pfollowing removal of the fifth hardmask material, trench etching, and subsequent sacrificial layer formation, in accordance with an embodiment of the present disclosure. Referring toFIG. 34Q, hardmask material layer3428is removed, revealing all of the original first and second halves of the potential via locations. The patterned ILD layer3402″ is then patterned to form ILD layer3402′ which includes the via openings3432and3426, along with trenches3436where via openings were not formed. The trenches3436will ultimately be used for metal line fabrication, as is described below. Upon completion of the trench etch, all openings (including via openings3426and3432and trenches3436) are filled with a sacrificial material3434. In one embodiment, the hardmask material layer3428is a carbon-based hardmask material and is removed with a plasma ashing process. In one embodiment, the sacrificial material3434is flowable organic or inorganic material such as a sacrificial light absorbing material (SLAM). The sacrificial material3434is either formed to, or planarized to, a level of the first patterned hardmask3416and the second patterned hardmask3412, as is depicted inFIG. 34Q.

FIG. 34Rillustrates a plan view of the structure ofFIG. 34Qfollowing deposition and patterning of a second diagonal hardmask layer, in accordance with an embodiment of the present disclosure. Referring toFIG. 34R, a second diagonal hardmask layer3438is formed on the sacrificial material3434, the second patterned hardmask layer3412, and the first patterned hardmask layer3416arrangement ofFIG. 34Q. In an embodiment, the second diagonal hardmask layer3438has a pattern essentially or highly symmetrically diagonal, e.g., at 45 degrees relative to the grating structure of the second pattern hardmask layer3412, to cover alternate lines of the first patterned hardmask layer3416. In an embodiment, the diagonal pattern of the second diagonal hardmask layer3438is printed at minimum critical dimension (CD), i.e., without the use of pitch halving or pitch quartering. It is to be appreciated that the individual lines may be printed even larger than minimum CD so long as some area of adjacent rows of the first patterned hardmask layer3416remains revealed. Regardless, the grating-like pattern of the second diagonal hardmask layer3438ofFIG. 34Rmay have hardmask lines spaced at a constant pitch and having a constant width. It is to be appreciated that description herein concerning forming and patterning a diagonal hardmask layer (such as the second diagonal hardmask layer3438) involves, in an embodiment, mask formation above a blanket hardmask layer. The mask formation may involve use of one or more layers suitable for lithographic processing. Upon patterning the one or more lithographic layers, the pattern is transferred to the hardmask layer by an etch process to provide a diagonally patterned hardmask layer. In a particular embodiment, the second diagonal hardmask layer3438is a carbon-based hardmask layer.

FIG. 34Sillustrates a plan view and corresponding cross-sectional view (taken along the g-g′ axis) of the structure ofFIG. 34Rfollowing removal of revealed regions of the first patterned hardmask layer, removal of the second diagonal hardmask layer, and following third plurality of photobucket formation, in accordance with an embodiment of the present disclosure. Referring toFIG. 34S, using the second diagonal hardmask layer3438as a mask, revealed regions of the first patterned hardmask layer3416are removed. In one such embodiment, the revealed regions of the first patterned hardmask layer3416are removed by an isotropic etch process (e.g., a wet etch process or non-anisotropic plasma etch process) such that any partial revealing leads to full removal of the partially revealed block of the first patterned hardmask layer3416. Referring again toFIG. 34S, the second diagonal hardmask layer3438is removed to reveal the sacrificial material3434and the second patterned hardmask layer3412. Also revealed are the portions of the first patterned hardmask layer3416that were protected from isotropic etching by the second diagonal hardmask layer3438. In a particular embodiment, the second diagonal hardmask layer3438is a carbon-based hardmask material and is removed with a plasma ashing process. Referring again toFIG. 34S, a third plurality of photobuckets3440is formed in the resulting openings above the patterned ILD layer3402″′ such that no portion of the patterned ILD layer3402′″ remains revealed. The photobuckets3440, at this stage, represent a first half of all possible plug locations in a resulting metallization layer. Accordingly, along each alternate row or down each alternate column of the resulting grid-like pattern ofFIG. 34S, a region of the first patterned hardmask layer3416is alternated with a photobucket3440. That is, the result is a checkerboard pattern of photobucket3440regions and first patterned hardmask layer3416regions. As such, an increase by a factor the square root of two is achieved in the nearest neighbor distance3442(shown as distance in direction b).

FIG. 34Tillustrates a plan view and corresponding cross-sectional view (taken along the h-h′ axis) of the structure ofFIG. 34Sfollowing plug location selection and trench etching, in accordance with an embodiment of the present disclosure. Referring toFIG. 34T, the photobuckets3440fromFIG. 34Sin are removed from locations3442where plugs will not be formed. In locations where plugs are selected to be formed, the photobuckets3440are retained. In one embodiment, in order to form locations3442where plugs will not be formed, lithography is used to expose the corresponding photobuckets3440. The exposed photobuckets may then be removed by a developer. The patterned ILD layer3402″′ is then patterned to form ILD layer3402″″ which includes trenches3444formed at locations3442. The trenches3444will ultimately be used for metal line fabrication, as is described below.

FIG. 34Uillustrates a plan view and corresponding cross-sectional view (taken along the i-i′ axis) of the structure ofFIG. 34Tfollowing removal of remaining third photobuckets and subsequent hardmask formation, in accordance with an embodiment of the present disclosure. Referring toFIG. 34U, all remaining photobuckets3440are removed, e.g., by an ashing process. Upon removal of all remaining photobuckets3440, all openings (including trenches3444) are filled with a hardmask material layer3446. In one embodiment, the hardmask material layer3446is a carbon-based hardmask material.

FIG. 34Villustrates a plan view and corresponding cross-sectional view (taken along the j-j′ axis) of the structure ofFIG. 34Vfollowing first patterned hardmask removal and fourth plurality of photobucket formation, in accordance with an embodiment of the present disclosure. Referring toFIG. 34V, the first patterned hardmask layer3416is removed (e.g., by a selective dry or wet etch process), and a fourth plurality of photobuckets3448is formed in the resulting openings above the patterned ILD layer3402″″ such that no portion of the patterned ILD layer3402″″ remains revealed. The photobuckets3448, at this stage, represent a second half of all possible plug locations in a resulting metallization layer.

FIG. 34Willustrates a plan view and corresponding cross-sectional view (taken along the k-k′ axis) of the structure ofFIG. 34Vfollowing plug location selection and trench etching, in accordance with an embodiment of the present disclosure. Referring toFIG. 34W, the photobuckets3448fromFIG. 34Vin are removed from locations3450where plugs will not be formed. In locations where plugs are selected to be formed, the photobuckets3448are retained. In one embodiment, in order to form locations3450where plugs will not be formed, lithography is used to expose the corresponding photobuckets3448. The exposed photobuckets may then be removed by a developer. The patterned ILD layer3402″″ is then patterned to form ILD layer3402″″′ which includes trenches3452formed at locations3450. The trenches3452will ultimately be used for metal line fabrication, as is described below.

FIG. 34Xillustrates a plan view and corresponding first cross-sectional view (taken along the l-l′ axis) and second cross-sectional view (taken along the m-m′ axis) of the structure ofFIG. 34Wfollowing removal of remaining fourth photobuckets, hardmask material layer and sacrificial material, and subsequent metal fill, in accordance with an embodiment of the present disclosure. Referring toFIG. 34X, remaining fourth photobuckets3448, hardmask material layer3446and sacrificial material3434are removed. In one such embodiment, the hardmask material layer3446is a carbon-based hardmask material, and both the hardmask material layer3446and the remaining fourth photobuckets3448are removed with a plasma ashing process. In one embodiment, the sacrificial material3434is removed in a different etch process. Referring to the plan view ofFIG. 34X, metallization3454is formed interleaved and co-planar with the second patterned hardmask layer3412. Referring to the first cross-sectional view taken along the l-l′ axis of the plan view ofFIG. 34X, the metallization3454fills trenches3452and3454(i.e., as corresponding to the cross-sectional view taken along the k-k′ axis ofFIG. 34W) formed in patterned interlayer dielectric layer3402″″′. Referring to the second cross-sectional view taken along the m-m′ axis of the plan view ofFIG. 34X, the metallization3454also fills trenches3436and via openings3432and3426(i.e., as corresponding to the cross-sectional view taken along the f-f′ axis ofFIG. 34Q) formed in patterned interlayer dielectric layer3402″″′. Thus, the metallization3454is used to form a plurality of conductive lines and conductive vias in an interlayer dielectric layer for a metallization structure, such as a BEOL metallization structure.

In an embodiment, the metallization3454is formed by a metal fill and polish back process. In one such embodiment, the second patterned hardmask layer3412is reduced in thickness during the polish back process. In a particular such embodiment, although reduced in thickness, a portion of the second patterned hardmask3412is retained, as is depicted inFIG. 34X. Accordingly, metal features3456that are neither conductive lines nor conductive vias formed in the patterned interlayer dielectric layer3402″″′ remain interleaved with the second patterned hardmask layer and on or above (but not in) the patterned interlayer dielectric layer3402″″′, as is also depicted inFIG. 34X. In an alternative particular embodiment (not shown), the second patterned hardmask3412is entirely removed during the polish back. Accordingly, metal features3456that are neither conductive lines nor conductive vias are not retained in the final structure. In either case, the described structures forFIG. 34Xmay subsequently be used as a foundation for forming subsequent metal line/via and ILD layers. Alternatively, the structure ofFIG. 34Xmay represent the final metal interconnect layer in an integrated circuit.

It is to be appreciated that the above process operations may be practiced in alternative sequences, not every operation need be performed and/or additional process operations may be performed. Referring again toFIG. 34X, metallization layer fabrication by using a diagonal hardmask may be complete at this stage. A next layer fabricated in a like manner likely requires initiation of the entire process once again. Alternatively, other approaches may be used at this stage to provide additional interconnect layers, such as conventional dual or single damascene approaches.

In an embodiment, as used throughout the present description, interlayer dielectric (ILD) material is composed of or includes a layer of a dielectric or insulating material. Examples of suitable dielectric materials include, but are not limited to, oxides of silicon (e.g., silicon dioxide (SiO2)), doped oxides of silicon, fluorinated oxides of silicon, carbon doped oxides of silicon, various low-k dielectric materials known in the arts, and combinations thereof. The interlayer dielectric material may be formed by conventional techniques, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), or by other deposition methods.

In an embodiment, as is also used throughout the present description, metal lines or interconnect line material (and via material) is composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers (e.g., layers including one or more of Ta, TaN, Ti or TiN), stacks of different metals or alloys, etc. Thus, the interconnect lines may be a single material layer, or may be formed from several layers, including conductive liner layers and fill layers. Any suitable deposition process, such as electroplating, chemical vapor deposition or physical vapor deposition, may be used to form interconnect lines. In an embodiment, the interconnect lines are composed of a conductive material such as, but not limited to, Cu, Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, W, Ag, Au or alloys thereof. The interconnect lines are also sometimes referred to in the art as traces, wires, lines, metal, or simply interconnect.

In an embodiment, as is also used throughout the present description, hardmask materials are composed of dielectric materials different from the interlayer dielectric material. In one embodiment, different hardmask materials may be used in different regions so as to provide different growth or etch selectivity to each other and to the underlying dielectric and metal layers. In some embodiments, a hardmask layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials. In another embodiment, a hardmask material includes a metal species. For example, a hardmask or other overlying material may include a layer of a nitride of titanium or another metal (e.g., titanium nitride). Potentially lesser amounts of other materials, such as oxygen, may be included in one or more of these layers. Alternatively, other hardmask layers known in the arts may be used depending upon the particular implementation. The hardmask layers may be formed by CVD, PVD, or by other deposition methods.

In an embodiment, as is also used throughout the present description, lithographic operations are performed using 193 nm immersion litho (i193), EUV and/or EBDW lithography, or the like. A positive tone or a negative tone resist may be used. In one embodiment, a lithographic mask is a trilayer mask composed of a topographic masking portion, an anti-reflective coating (ARC) layer, and a photoresist layer. In a particular such embodiment, the topographic masking portion is a carbon hardmask (CHM) layer and the anti-reflective coating layer is a silicon ARC layer.

In accordance with embodiments described herein, optical and SEM metrology for photobuckets is described. It is to be appreciated that the use of a pre-patterned hard mask to define lithographic pattern can make overlay measurements challenging because the response to exposure of such patterning is digital (binary) and feature sizes are quantized. Hence, the size of the underlying mask pattern becomes the minimum measurable unit of overlay, which is too large for effective process control. The approach described below not only enables an overlay measure that is much smaller than the underlying pre-patterned hard mask size, but also provides a signal response that is amplified many times that of the overlay shift, enabling a very accurate overlay measure.

To provide a structural framework for concepts described herein,FIGS. 35A-35Dillustrate cross-sectional views and corresponding top-down views representing various operations a patterning processing scheme using pre-patterned hard masks, in accordance with an embodiment of the present disclosure.

Referring toFIG. 35A, a first pre-patterned hardmask3502and a second pre-patterned hardmask3504are formed above an underlying layer3506. All possible via or plug locations are exposed as openings3508in the pre-patterned hardmask3502and the second pre-patterned hardmask3504.

Referring toFIG. 35B, a plurality of photoresist layer portions3510is formed in the openings3508ofFIG. 35A.

Referring toFIG. 35C, select ones3512of the plurality of photoresist layer portions3510are exposed by a lithographic exposure3514. The select ones3512of the plurality of photoresist layer portions3510exposed by the lithographic exposure3514may represent the via or plug locations that will ultimately be opened or selected.

However, in accordance with an embodiment of the present disclosure, the lithographic exposure3514has an overlay error in the X-direction ofFIG. 35C. For example, the exposed photoresist layer3512on the left hand-side of the cross-section view is shifted to the right to an extent that a portion of the photo-resist is not exposed by the lithographic exposure3514. All exposed photoresist layers3512of the top-down view are shifted to the right to an extent that a portion of the photo-resist is not exposed by the lithographic exposure3514. Furthermore, the shift may be substantial enough to partially expose neighboring locations, as is depicted inFIG. 35C.

Referring toFIG. 35D, the select locations3512are cleared of exposed photo-resist to provide openings3516. The openings3516may be used for subsequent via or plug fabrication, depending on the specific layer of the semiconductor structure.

However, in the case that an insufficient exposure of the locations3512is performed due to overlay error, some openings3516may catastrophically not be completely opened. In general, the exposure3514must provide a critical number of electrons or photons to completely clear the select ones3512of the plurality of photoresist layer portions3510to provide openings3516. Some overlay error may be tolerated, but substantial overlay error may not be tolerated. Additionally, as described in greater detail below, even in the case that all openings3516are completely opened, successful fabrication of a next layer may require an overlay measurement based at least to some extent on the openings3516.

One or more embodiments described herein are directed to approaches involving the use of multi-pitch grating structures on a layer to extract overlay information relative to an underlying layer. Embodiments described herein may be implemented to solve issues associated with measuring overlay between a layer patterned on top of a pre-patterned hardmask (e.g., via or plug) and the underlying pre-patterned hard mask layer (e.g., photobucket) by using an optical metrology tool. In an embodiment, gratings are patterned at two or more pitches that are different from the underlying pre-patterned gratings, but parallel to one of the underlying gratings. A shift in overlay of the current layer versus the hard mask pattern results in an optical signal that moves with the overlay and is proportional to the overlay error. By comparison, optical overlay typically involves real features, thus providing an analogue response. Here, movement is quantized as opposed moving in analogue motion. That is, the response is digital (e.g., digitized and magnified motion) in that it is based on steps. In one embodiment, a “fringe” pattern is measured.

FIGS. 36A-36Edescribed below demonstrate the generation of optical signals using photobuckets that respond to a change in overlay. It is to be appreciated that conventional optical metrology tools measure relatively large targets (e.g., 20-30 microns). For embodiments described herein, structures are generated from arrays of lines/spaces that are below the resolution limit of an inspection tool and which leverage the photobuckets concept to create moving edges that can be detected/measured with conventional overlay measurement algorithms. The final pattern seen by the metrology tool shows measurable optical edges due to diffraction and scattering of light from sub-resolution patterns that move with overlay.FIG. 36Fshows a possible optical metrology mark for use in association withFIGS. 36A-36E.

FIG. 36Aillustrates a top-down view of an overlay scenario where a current layer is overlaid on an underlying pre-patterned hard mask grid, in accordance with an embodiment of the present disclosure.

Referring toFIG. 36A, an underlying layer includes a first pre-patterned hardmask3602and a second pre-patterned hardmask3604. A plurality of photoresist layer portions3610and a plurality of openings3616(having been exposed and developed) are among the first pre-patterned hardmask3602and the second pre-patterned hardmask3604structures. A current layer is represented by overlay images3650A. The overlay images3650A have an overlay shift of zero and a pitch delta of P/4. The pitch of the overlay images3650A of the current layer shown as 25% larger (in the top half region3652A) and 25% smaller (in the bottom half region3654A) as an exemplary embodiment. Wide unexposed features3656A and3658A are included in the current layer, as is depicted inFIG. 36A.

FIG. 36Billustrates a top-down view of an overlay scenario where a current layer has a positive overlay of quarter pitch with respect to an underlying pre-patterned hard mask grid, in accordance with an embodiment of the present disclosure.

Referring toFIG. 36B, an underlying layer includes a first pre-patterned hardmask3602and a second pre-patterned hardmask3604. A plurality of photoresist layer portions3610and a plurality of openings3616(having been exposed and developed) are among the first pre-patterned hardmask3602and the second pre-patterned hardmask3604structures. A current layer is represented by overlay images3650B. The overlay images3650B have a positive (+ve) overlay shift of P/4. Wide unexposed features3656B and3658B are included in the current layer, with movement of the wide unexposed features3656B and3658B as depicted inFIG. 36B.

FIG. 36Cillustrates a top-down view of an overlay scenario where a current layer has a positive overlay of half pitch with respect to an underlying pre-patterned hard mask grid, in accordance with an embodiment of the present disclosure.

Referring toFIG. 36C, an underlying layer includes a first pre-patterned hardmask3602and a second pre-patterned hardmask3604. A plurality of photoresist layer portions3610and a plurality of openings3616(having been exposed and developed) are among the first pre-patterned hardmask3602and the second pre-patterned hardmask3604structures. A current layer is represented by overlay images3650C. The overlay images3650C have a positive (+ve) overlay shift of P/2. Wide unexposed features3656C and3658C are included in the current layer, with movement of the wide unexposed features3656C and3658C as depicted inFIG. 36C.

FIG. 36Dillustrates a top-down view of an overlay scenario where a current layer has a positive overlay of an arbitrary value Δ with respect to an underlying pre-patterned hard mask grid, in accordance with an embodiment of the present disclosure.

Referring toFIG. 36D, an underlying layer includes a first pre-patterned hardmask3602and a second pre-patterned hardmask3604. A plurality of photoresist layer portions3610and a plurality of openings3616(having been exposed and developed) are among the first pre-patterned hardmask3602and the second pre-patterned hardmask3604structures. A current layer is represented by overlay images3650D. The overlay images3650D have an overlay shift of zero and a pitch delta of P+Δ. Wide unexposed features3656D and3658D are included in the current layer, as is depicted inFIG. 36D.

FIG. 36Eillustrates a top-down view of an overlay scenario where a current layer has a positive overlay of an arbitrary value Δ with respect to an underlying pre-patterned hard mask grid, where a measurable Δ is made as small as needed by changing s resist sensitivity and/or the drawn feature size, in accordance with an embodiment of the present disclosure.

Referring toFIG. 36E, an underlying layer includes a first pre-patterned hardmask3602and a second pre-patterned hardmask3604. A plurality of photoresist layer portions3610and a plurality of openings3616(having been exposed and developed) are among the first pre-patterned hardmask3602and the second pre-patterned hardmask3604structures. A current layer is represented by overlay images3650E. The overlay images3650E have an overlay shift of +A and a pitch delta of P+Δ. Wide unexposed features3656E and3658E are included in the current layer, with movement of the wide unexposed features3656E and3658E as depicted inFIG. 36E. In an embodiment, for a small overlay shift of Δ, the measured signal is amplified to the order of P, and Δ can be as small as needed.

FIG. 36Fillustrates an exemplary metrology structure suitable for the approaches described above in association withFIGS. 36A-36E, in accordance with an embodiment of the present disclosure. Referring toFIG. 36F, a metrology structure3697includes both layer 1 features3698(e.g., underlying layer) and layer 2 features3699(e.g., current layer). In one embodiment, the width of each of the features is approximately 20-30 microns, as is depicted inFIG. 36F. Such a structure may be included in a scribe line or on die in a drop-in cell, for example. In an embodiment, a completed die may include a region having a beat frequency of wide features formed by an array of vias or plugs in a collection of narrow features. The presence of two different beat frequencies in any direction may imply the use of the above described technique to measure overlay. The approach described above may enable accurate measurement of overlay in photobuckets for every via or plug patterning layer that uses the technique. Embodiments may enhance accuracy for future generations of technology while using current technology overlay measurement tools.

One or more embodiments described herein are directed to approaches involving measuring overlay on pre-patterned hardmask (e.g., photobuckets) using critical dimension scanning electron microscopy (CDSEM) techniques. Embodiments described herein may be implemented to solve issues associated with measuring overlay between a via and/or plug layer patterned on top of a pre-patterned hardmask layer (e.g., photobucket layer) and the underlying pre-patterned hardmask layer by using a scanning electron microscope (e.g., CDSEM). In an embodiment, via or plug locations are patterned at pitches that are slightly different from the underlying pre-patterned hardmask pitch. Due to an overlay mismatch, the position of the photobucket that clears depends on the amount of overlay mismatch.

FIG. 37Aillustrates a top-down view of an overlay scenario where a current layer is overlaid on an underlying pre-patterned hardmask, in accordance with an embodiment of the present disclosure.

Referring toFIG. 37A, an underlying layer includes a first pre-patterned hardmask3702and a second pre-patterned hardmask3704. A plurality of photoresist layer portions3710and a plurality of openings3716(having been exposed and developed) are among the first pre-patterned hardmask3702and the second pre-patterned hardmask3704structures. A current layer is represented by overlay images3750A. The overlay images3750A have an overlay shift in X of zero and in Y of zero. The pitch of the overlay images3750A of the current layer is 25% larger relative to the underlying layer as an exemplary embodiment, i.e., patterned at pitch+Δ, where Δ=P/4. Region3760A highlights a location of a “photobucket cluster” at zero overlay shift (PB0,0).

FIG. 37Billustrates a top-down view of an overlay scenario where a current layer has a positive overlay shift of quarter pitch with respect to the underlying pre-patterned hardmask grid in the X-direction, in accordance with an embodiment of the present disclosure.

Referring toFIG. 37B, an underlying layer includes a first pre-patterned hardmask3702and a second pre-patterned hardmask3704. A plurality of photoresist layer portions3710and a plurality of openings3716(having been exposed and developed) are among the first pre-patterned hardmask3702and the second pre-patterned hardmask3704structures. A current layer is represented by overlay images3750B. The overlay images3750B have an overlay shift in X of PX/4 and in Y of zero. The pitch of the overlay images3750B of the current layer is 25% larger relative to the underlying layer as an exemplary embodiment, i.e., patterned at pitch+Δ, where Δ=P/4. Region3760B highlights a location of X=−2PXand Y=0 for a photobucket cluster with respect to PB0,0. The region3760B and corresponding open/closed vertical column move left by an amount equal to twice the pitch. It is to be appreciated that the open/closed column will have a different contrast from the other columns due to the fact that the exposed photobucket density is different from the other columns in the region.

FIG. 37Cillustrates a top-down view of an overlay scenario where a current layer has a negative overlay of quarter pitch with respect to the underlying pre-patterned hardmask grid in the X-direction, in accordance with an embodiment of the present disclosure.

Referring toFIG. 37C, an underlying layer includes a first pre-patterned hardmask3702and a second pre-patterned hardmask3704. A plurality of photoresist layer portions3710and a plurality of openings3716(having been exposed and developed) are among the first pre-patterned hardmask3702and the second pre-patterned hardmask3704structures. A current layer is represented by overlay images3750C. The overlay images3750C have an overlay shift in X of −PX/4 and in Y of zero. The pitch of the overlay images3750C of the current layer is 25% larger relative to the underlying layer as an exemplary embodiment, i.e., patterned at pitch+Δ, where Δ=P/4. Region3760C highlights a location of X=+2PXand Y=0 for a photobucket cluster with respect to PB0,0. The region3760C and corresponding open/closed vertical column move right by an amount equal to twice the pitch.

FIG. 37Dillustrates a top-down view of an overlay scenario where a current layer has a positive overlay of quarter pitch with respect to the underlying pre-patterned hardmask grid in the Y-direction, in accordance with an embodiment of the present disclosure.

Referring toFIG. 37D, an underlying layer includes a first pre-patterned hardmask3702and a second pre-patterned hardmask3704. A plurality of photoresist layer portions3710and a plurality of openings3716(having been exposed and developed) are among the first pre-patterned hardmask3702and the second pre-patterned hardmask3704structures. A current layer is represented by overlay images3750D. The overlay images3750D have an overlay shift in X of zero and in Y of PY/4. The pitch of the overlay images3750D of the current layer is 25% larger relative to the underlying layer as an exemplary embodiment, i.e., patterned at pitch+Δ, where Δ=P/4. Region3760D highlights a location of X=0 and Y=−2PYfor a photobucket cluster with respect to PB0,0. The region3760D and corresponding open/closed horizontal row move down by an amount equal to twice the pitch.

FIG. 37Eillustrates a top-down view of an overlay scenario where a current layer has a positive overlay of quarter pitch with respect to the underlying pre-patterned hardmask grid in the X-direction and has a positive overlay of quarter pitch with respect to the underlying pre-patterned hardmask grid in the Y-direction, in accordance with an embodiment of the present disclosure.

Referring toFIG. 37E, an underlying layer includes a first pre-patterned hardmask3702and a second pre-patterned hardmask3704. A plurality of photoresist layer portions3710and a plurality of openings3716(having been exposed and developed) are among the first pre-patterned hardmask3702and the second pre-patterned hardmask3704structures. A current layer is represented by overlay images3750E. The overlay images3750E have an overlay shift in X of PX/4 and in Y of PY/4. The pitch of the overlay images3750E of the current layer is 25% larger relative to the underlying layer as an exemplary embodiment, i.e., patterned at pitch+Δ, where Δ=P/4. Region3760E highlights a location of X=−2PXand Y=−2PYfor a photobucket cluster with respect to PB0,0. The region3760E and corresponding open/closed horizontal row move down by an amount equal to twice the pitch. Additionally, the region3760E and corresponding open/closed vertical column move left by an amount equal to twice the pitch.

With reference again toFIGS. 37A-37E, it is to be appreciated that cross-sectional analysis of a semiconductor chip may reveal an alignment mark that includes vertical and horizontal arrays of vias and/or plugs among a plurality of gridded vias and plugs as indicative of the application of one or more embodiments described herein. Such structures may be included in a scribe line or on die in a drop-in cell, for example. The application of such an approach may enable accurate measurement of overlay in photobuckets for every via and/or plug patterning layer that is intended for use with CDSEM metrology. It is also to be appreciated that conventional overlay techniques may not work with this style of patterning.

In accordance with an embodiment of the present disclosure, new structures for high resolution phase shift masks (PSM) fabrication for lithography, such as extreme ultra-violet lithography (EUV), are described. Such PSM masks may be used for general (direct) lithography or complementary lithography.

Photolithography is commonly used in a manufacturing process to form patterns in a layer of photoresist. In the photolithography process, a photoresist layer is deposited over an underlying layer that is to be etched. Typically, the underlying layer is a semiconductor layer, but may be any type of hardmask or dielectric material. The photoresist layer is then selectively exposed to radiation through a photomask or reticle. The photoresist is then developed and those portions of the photoresist that are exposed to the radiation are removed, in the case of “positive” photoresist.

The photomask or reticle used to pattern the wafer is placed within a photolithography exposure tool, commonly known as a “stepper” or “scanner.” In the stepper or scanner machine, the photomask or reticle is placed between a radiation source and a wafer. The photomask or reticle is typically formed from patterned chrome (absorber layer) placed on a quartz substrate. The radiation passes substantially unattenuated through the quartz sections of the photomask or reticle in locations where there is no chrome. In contrast, the radiation does not pass through the chrome portions of the mask. Because radiation incident on the mask either completely passes through the quartz sections or is completely blocked by the chrome sections, this type of mask is referred to as a binary mask. After the radiation selectively passes through the mask, the pattern on the mask is transferred into the photoresist by projecting an image of the mask into the photoresist through a series of lenses.

As features on the photomask or reticle become closer and closer together, diffraction effects begin to take effect when the size of the features on the mask are comparable to the wavelength of the light source. Diffraction blurs the image projected onto the photoresist, resulting in poor resolution.

One state of the art method of preventing diffraction patterns from interfering with the desired patterning of the photoresist is to cover selected openings in the photomask or reticle with a transparent layer known as a shifter. The shifter shifts one of the sets of exposing rays out of phase with another adjacent set, which nullifies the interference pattern from diffraction. This approach is referred to as a phase shift mask (PSM) approach. Nevertheless, alternative mask fabrication schemes that reduce defects and increase throughput in mask production are important focus areas of lithography process development.

One or more embodiments of the present disclosure are directed to methods for fabricating lithographic masks and the resulting lithographic masks. To provide context, the requirement to meet aggressive device scaling goals set forth by the semiconductor industry harbors on the ability of lithographic masks to pattern smaller features with high fidelity. However, approaches to pattern smaller and smaller features present formidable challenges for mask fabrication. In this regard, lithographic masks widely in use today rely on the concept of phase shift mask (PSM) technology to pattern features. However, reducing defects while creating smaller and smaller patterns remains one of the biggest obstacles in mask fabrication. Use of the phase shift mask may have several disadvantages. First, the design of a phase shift mask is a relatively complicated procedure that requires significant resources. Second, because of the nature of a phase shift mask, it is difficult to check whether or not defects are present in the phase shift mask. Such defects in phase shift masks arise out of the current integration schemes employed to produce the mask itself. Conventional phase shift masks adopt a cumbersome and somewhat defect prone approach to pattern thick light absorbing materials and then transfer the pattern to a secondary layer that aids in the phase shifting. To complicate matters, the absorber layer is subjected to plasma etch twice and, consequently, unwanted effects of plasma etch such as loading effects, reactive ion etch lag, charging and reproducible effects leads to defects in mask production.

Innovation in materials and novel integration techniques to fabricate defect free lithographic masks remains a high priority to enable device scaling. Accordingly, in order to exploit the full benefits of a phase shift mask technology, a novel integration scheme that employs (i) patterning a shifter layer with high fidelity and (ii) patterning an absorber only once and during the final stages of fabrication may be needed. Additionally, such a fabrication scheme may also offer other advantages such as flexibility in material choices, decreased substrate damage during fabrication, and increased throughput in mask fabrication.

FIG. 38illustrates a cross sectional view of a lithography mask structure3801in accordance with an embodiment of the present disclosure. The lithography mask3801includes an in-die region3810, a frame region3820and a die-frame interface region3830. The die-frame interface region3830includes adjacent portions of the in-die region3810and the frame region3820. The in-die region3810includes a patterned shifter layer3806disposed directly on a substrate3800, wherein the patterned shifter layer has features that have sidewalls. The frame region3820surrounds the in-die region3810and includes a patterned absorber layer3802disposed directly on the substrate3800.

The die-frame interface region3830, disposed on substrate3800, includes a dual layer stack3840. The dual layer stack3840includes an upper layer3804, disposed on the lower patterned shifter layer3806. The upper layer3804of the dual layer stack3840is composed of a same material as the patterned absorber layer3802of the frame region3820.

In an embodiment, an uppermost surface3808of the features of the patterned shifter layer3806have a height that is different than an uppermost surface3812of features of the die-frame interface region and different than an uppermost surface3814of the features in the frame region. Furthermore, in an embodiment the height of the uppermost surface3812of the features of the die-frame interface region is different than the height of the uppermost surface3814of the features of the frame region. Typical thickness of the phase shifter layer3806ranges from 40-100 nm, while a typical thickness of the absorber layer ranges from 30-100 nm. In an embodiment, the thickness of the absorber layer3802in the frame region3820is 50 nm, the combined thickness of the absorber layer3804which is disposed on the shifter layer3806in the die-frame interface region3830is 120 nm and the thickness of the absorber in the frame region is 70 nm. In an embodiment, the substrate3800is quartz, the patterned shifter layer includes a material such as but not limited to molybdenum-silicide, molybdenum-silicon oxynitride, molybdenum-silicon nitride, silicon oxynitride, or silicon nitride, and the absorber material is chrome.

In accordance with an embodiment of the present disclosure, complementary electron beam lithography is described. One or more embodiments described herein are directed to lithographic approaches and tooling involving or suitable for complementary e-beam lithography (CEBL), including semiconductor processing considerations when implementing such approaches and tooling.

Complementary lithography draws on the strengths of two lithography technologies, working hand-in-hand, to lower the cost of patterning critical layers in logic devices at 20 nm half-pitch and below, in high-volume manufacturing (HVM). The most cost-effective way to implement complementary lithography is to combine optical lithography with e-beam lithography (EBL). The process of transferring integrated circuit (IC) designs to the wafer entails the following: optical lithography to print unidirectional lines (either strictly unidirectional or predominantly unidirectional) in a pre-defined pitch, pitch division techniques to increase line density, and EBL to “cut” the lines. EBL is also used to pattern other critical layers, notably contact and via holes. Optical lithography can be used alone to pattern other layers. When used to complement optical lithography, EBL is referred to as CEBL, or complementary EBL. CEBL is directed to cutting lines and holes. By not attempting to pattern all layers, CEBL plays a complementary but crucial role in meeting the industry's patterning needs at advanced (smaller) technology nodes (e.g., 10 nm or smaller such as 7 nm or 5 nm technology nodes). CEBL also extends the use of current optical lithography technology, tools and infrastructure.

As described above, electron beam (ebeam) lithography may be implemented to complement standard lithographic techniques in order to achieved desired scaling of features for integrated circuit fabrication. An electron beam lithography tool may be used to perform the ebeam lithography. In an exemplary embodiment,FIG. 39is a cross-sectional schematic representation of an ebeam column of an electron beam lithography apparatus.

Referring toFIG. 39, an ebeam column3900includes an electron source3902for providing a beam of electrons3904. The beam of electrons3904is passed through a limiting aperture3906and, subsequently, through high aspect ratio illumination optics3908. The outgoing beam3910is then passed through a slit3912and may be controlled by a slim lens3914, e.g., which may be magnetic. Ultimately, the beam3904is passed through a shaping aperture3916(which may be a one-dimensional (1-D) shaping aperture) and then through a blanker aperture array (BAA)3918. The BAA3918includes a plurality of physical apertures therein, such as openings formed in a thin slice of silicon. It may be the case that only a portion of the BAA3918is exposed to the ebeam at a given time. Alternatively, or in conjunction, only a portion3920of the ebeam3904that passes through the BAA3918is allowed to pass through a final aperture3922(e.g., beam portion3921is shown as blocked) and, possibly, a stage feedback deflector3924.

Referring again toFIG. 39, the resulting ebeam3926ultimately impinges as a spot3928on a surface of a wafer3930, such as a silicon wafer used in IC manufacture. Specifically, the resulting ebeam may impinge on a photo-resist layer on the wafer, but embodiments are not so limited. A stage scan3932moves the wafer3930relative to the beam3926along the direction of the arrow3934shown inFIG. 39. It is to be appreciated that an ebeam tool in its entirely may include numerous columns3900of the type depicted inFIG. 39. Also, the ebeam tool may have an associated base computer, and each column may further have a corresponding column computer.

In an embodiment, when referring below to openings or apertures in a blanker aperture array (BAA), all or some of the openings or apertures of the BAA can be switched open or “closed” (e.g., by beam deflecting) as the wafer/die moves underneath along a wafer travel or scan direction. In one embodiment, the BAA can be independently controlled as to whether each opening passes the ebeam through to the sample or deflects the beam into, e.g., a Faraday cup or blanking aperture. The ebeam column or apparatus including such a BAA may be built to deflect the overall beam coverage to just a portion of the BAA, and then individual openings in the BAA are electrically configured to pass the ebeam (“on”) or not pass (“off”). For example, un-deflected electrons pass through to the wafer and expose a resist layer, while deflected electrons are caught in the Faraday cup or blanking aperture. It is to be appreciated that reference to “openings” or “opening heights” refers to the spot size impinged on the receiving wafer and not to the physical opening in the BAA since the physical openings are substantially larger (e.g., micron scale) than the spot size (e.g., nanometer scale) ultimately generated from the BAA. Thus, when described herein as the pitch of a BAA or column of openings in a BAA being said to “correspond” to the pitch of metal lines, such description actually refers to the relationship between pitch of the impinging spots as generated from the BAA and the pitch of the lines being cut. As an example provided below, the spots generated from the BAA4310have a pitch the same as the pitch of the lines4300(when both columns of BAA openings are considered together). Meanwhile, the spots generated from only one column of the staggered array of the BAA4310have twice the pitch as the pitch of the lines4300.

In an embodiment, a staggered beam aperture array is implemented to solve throughput of an ebeam machine while also enabling minimum wire pitch. With no stagger, consideration of edge placement error (EPE) means that a minimum pitch that is twice the wire width cannot be cut since there is no possibility of stacking vertically in a single stack. For example,FIG. 40illustrates an aperture4000of a BAA relative to a line4002to be cut or to have vias placed in targeted locations while the line is scanned along the direction of the arrow4004under the aperture4000. Referring toFIG. 40, for a given line4002to be cut or vias to be placed, the EPE4006of the cutter opening (aperture) results in a rectangular opening in the BAA grid that is the pitch of the line.

FIG. 41illustrates two non-staggered apertures4100and4102of a BAA relative to two lines4104and4106, respectively, to be cut or to have vias placed in targeted locations while the lines are scanned along the direction of the arrow4108under the apertures4100and4102. Referring toFIG. 41, when the rectangular opening4000ofFIG. 40is placed in a vertical single column with other such rectangular openings (e.g., now as4100and4102), the allowed pitch of the lines to be cut is limited by 2×EPE4110plus the distance requirement4112between the BAA opens4100and4102plus the width of one wire4104or4106. The resulting spacing4114is shown by the arrow on the far right ofFIG. 41. Such a linear array may severely limit the pitch of the wiring to be substantially greater than 3-4× of the width of the wires, which may be unacceptable. Another possibly unacceptable alternative would be to cut tighter pitch wires in two (or more) passes with slightly offset wire locations; this approach could severely limit the throughput of the ebeam machine.

By contrast toFIG. 41,FIG. 42illustrates two columns4202and4204of staggered apertures4206of a BAA4200relative to a plurality of lines4208to be cut or to have vias placed in targeted locations while the lines4208are scanned along the direction4210under the apertures4206, with scanning direction shown by the arrow, in accordance with an embodiment of the present disclosure. Referring toFIG. 41, a staggered BAA4200includes two linear arrays4202and4204, staggered spatially as shown. The two staggered arrays4202and4204cut (or place vias at) alternate lines4208. The lines4208are, in one embodiment, placed on a tight grid at twice the wire width. As used throughout the present disclosure, the term staggered array can refer to a staggering of openings4206that stagger in one direction (e.g., the vertical direction) and either have no overlap or have some overlap when viewed as scanning in the orthogonal direction (e.g., the horizontal direction). In the latter case, the effective overlap provides for tolerance in misalignment.

It is to be appreciated that, although a staggered array is shown herein as two vertical columns for simplicity, the openings or apertures of a single “column” need not be columnar in the vertical direction. For example, in an embodiment, so long as a first array collectively has a pitch in the vertical direction, and a second array staggered in the scan direction from the first array collectively has the pitch in the vertical direction, the a staggered array is achieved. Thus, reference to or depiction of a vertical column herein can actually be made up of one or more columns unless specified as being a single column of openings or apertures. In one embodiment, in the case that a “column” of openings is not a single column of openings, any offset within the “column” can be compensated with strobe timing. In an embodiment, the critical point is that the openings or apertures of a staggered array of a BAA lie on a specific pitch in the first direction, but are offset in the second direction to allow them to place cuts or vias without any gap between cuts or vias in the first direction.

Thus, one or more embodiments are directed to a staggered beam aperture array where openings are staggered to allow meeting EPE cuts and/or via requirements as opposed to an inline arrangement that cannot accommodate for EPE technology needs. By contrast, with no stagger, the problem of edge placement error (EPE) means that a minimum pitch that is twice the wire width cannot be cut since there is no possibility of stacking vertically in single stack. Instead, in an embodiment, use of a staggered BAA enables much greater than 4000 times faster than individually ebeam writing each wire location. Furthermore, a staggered array allows a wire pitch to be twice the wire width. In a particular embodiment, an array has 4096 staggered openings over two columns such that EPE for each of the cut and via locations can be made. It is to be appreciated that a staggered array, as contemplated herein, may include two or more columns of staggered openings.

In an embodiment, use of a staggered array leaves space for including metal around the apertures of the BAA which contain one or two electrodes for passing or steering the ebeam to the wafer or steering to a Faraday cup or blanking aperture. That is, each opening may be separately controlled by electrodes to pass or deflect the ebeam. In one embodiment, the BAA has 4096 openings, and the ebeam apparatus covers the entire array of 4096 openings, with each opening electrically controlled. Throughput improvements are enabled by sweeping the wafer under the opening as shown by the thick black arrows.

In a particular embodiment, a staggered BAA has two rows of staggered BAA openings. Such an array permits tight pitch wires, where wire pitch can be 2× the wire width. Furthermore, all wires can be cut in a single pass (or vias can be made in a single pass), thereby enabling throughput on the ebeam machine.FIG. 21Aillustrates two columns of staggered apertures (left) of a BAA relative to a plurality of lines (right) having cuts (breaks in the horizontal lines) or vias (filled-in boxes) patterned using the staggered BAA, with scanning direction shown by the arrow, in accordance with an embodiment of the present disclosure.

Referring toFIG. 43A, the line result from a single staggered array could be as depicted, where lines are of single pitch, with cuts and vias patterned. In particular,FIG. 43Adepicts a plurality of lines4300or open line positions4302where no lines exist. Vias4304and cuts4306may be formed along lines4300. The lines4300are shown relative to a BAA4310having a scanning direction4312. Thus,FIG. 43Amay be viewed as a typical pattern produced by a single staggered array. Dotted lines show where cuts occurred in the patterned lines (including total cut to remove a full line or line portion). The via locations4304are patterning vias that land on top of the wires4300.

It is to be appreciated that an ebeam column that includes a staggered beam aperture array (staggered BAA) as described above may also include other features in addition to those described in association withFIG. 39. For example, in an embodiment, the sample stage can be rotated by 90 degrees to accommodate alternating metallization layers which may be printed orthogonally to one another (e.g., rotated between X and Y scanning directions). In another embodiment, an e-beam tool is capable of rotating a wafer by 90 degrees prior to loading the wafer on the stage.

FIG. 43Billustrates a cross-sectional view of a stack4350of metallization layers4352in an integrated circuit based on metal line layouts of the type illustrated inFIG. 43A, in accordance with an embodiment of the present disclosure. Referring toFIG. 43B, in an exemplary embodiment, a metal cross-section for an interconnect stack4350is derived from a single BAA array for the lower eight matched metal layers4354,4356,4358,4360,4362,4364,4366and4368. It is to be appreciated that upper thicker/wider metal lines4370and4372would not be made with the single BAA. Via locations4374are depicted as connecting the lower eight matched metal layers4354,4356,4358,4360,4362,4364,4366and4368.

Overall, in an embodiment, complementary lithography as described herein involves first fabricating a gridded layout by conventional or state-of the-art lithography, such as 193 nm immersion lithography (193i). Pitch division may be implemented to increase the density of lines in the gridded layout by a factor of n. Gridded layout formation with 193i lithography plus pitch division by a factor of n can be designated as 193i+P/n Pitch Division. Patterning of the pitch divided gridded layout may then be patterned using electron beam direct write (EBDW) “cuts.” In one such embodiment, 193 nm immersion scaling can be extended for many generations with cost effective pitch division. In one embodiment, complementary EBL is used to break gratings continuity and to pattern vias. In another embodiment, complementary EUV is used to break gratings continuity and to pattern vias.

FIG. 44illustrates a computing device4400in accordance with one implementation of the disclosure. The computing device4400houses a board4402. The board4402may include a number of components, including but not limited to a processor4404and at least one communication chip4406. The processor4404is physically and electrically coupled to the board4402. In some implementations the at least one communication chip4406is also physically and electrically coupled to the board4402. In further implementations, the communication chip4406is part of the processor4404.

The processor4404of the computing device4400includes an integrated circuit die packaged within the processor4404. In some implementations of embodiments of the disclosure, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the disclosure. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip4406also includes an integrated circuit die packaged within the communication chip4406. In accordance with another implementation of the disclosure, the integrated circuit die of the communication chip is built in accordance with implementations of the disclosure.

In further implementations, another component housed within the computing device4400may contain an integrated circuit die built in accordance with implementations of embodiments of the disclosure.

FIG. 45illustrates an interposer4500that includes one or more embodiments of the disclosure. The interposer4500is an intervening substrate used to bridge a first substrate4502to a second substrate4504. The first substrate4502may be, for instance, an integrated circuit die. The second substrate4504may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer4500is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer4500may couple an integrated circuit die to a ball grid array (BGA)506that can subsequently be coupled to the second substrate4504. In some embodiments, the first and second substrates4502/4504are attached to opposing sides of the interposer4500. In other embodiments, the first and second substrates4502/4504are attached to the same side of the interposer4500. And in further embodiments, three or more substrates are interconnected by way of the interposer4500.

The interposer may include metal interconnects4508and vias4510, including but not limited to through-silicon vias (TSVs)4512. The interposer4500may further include embedded devices4514, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer4500. In accordance with embodiments of the disclosure, apparatuses or processes disclosed herein may be used in the fabrication of interposer4500.

Thus, embodiments of the present disclosure include sub-10 nm pitch patterning and self-assembled devices.

An integrated circuit structure includes a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a grating pattern interrupted by a partial body portion. A trench isolation layer is between the plurality of semiconductor bodies and adjacent to lower portions of the plurality of semiconductor bodies, but not adjacent to upper portions of the plurality of semiconductor bodies, where the trench isolation layer is over the partial body portion. One or more gate electrode stacks are on top surfaces and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies and on portions of the trench isolation layer. A back end of line (BEOL) metallization layer is above the one or more gate electrode stacks, the BEOL metallization layer including a plurality of alternating first and second conductive line types along a same direction, wherein a total composition of the first conductive line type is different from a total composition of the second conductive line type.

The integrated circuit structure of example embodiment 1, wherein the lines of the first conductive line type are spaced apart by a pitch, and wherein the lines of the second conductive line type are spaced apart by the pitch.

The integrated circuit structure of example embodiment 1 or 2, wherein the plurality of alternating first and second conductive line types is in an inter-layer dielectric (ILD) layer.

The integrated circuit structure of example embodiment 1 or 2, wherein the lines of the plurality of alternating first and second conductive line types are separated by an air gap.

The integrated circuit structure of example embodiment 1, 2, 3 or 4, wherein the total composition of the first conductive line type substantially includes copper, and wherein the total composition of the second conductive line type substantially includes a material selected from the group consisting of Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au and alloys thereof.

The integrated circuit structure of example embodiment 1, 2, 3, 4 or 5, wherein the lines of the plurality of alternating first and second conductive line types each include a barrier layer along a bottom of and sidewalls of the line.

The integrated circuit structure of example embodiment 1, 2, 3, 4 or 5, wherein the lines of the plurality of alternating first and second conductive line types each include a barrier layer along a bottom of the line but not along sidewalls of the line.

The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6 or 7, wherein one or more of the lines of the plurality of alternating first and second conductive line types is connected to an underlying via connected to an underlying metallization layer, the underlying metallization layer between the one or more gate electrode stacks and the BEOL metallization layer, and wherein one or more of the lines of the plurality of alternating first and second conductive line types is interrupted by a dielectric plug.

The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6, 7 or 8, wherein the grating pattern has a constant pitch.

The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6, 7, 8 or 9, further including source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are adjacent to the upper portions of the plurality of semiconductor bodies and include a semiconductor material different than the semiconductor material of the semiconductor bodies.

The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6, 7, 8 or 9, further including source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are within the upper portions of the plurality of semiconductor bodies.

The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10 or 11, wherein each of the one or more gate electrode stacks includes a high-k gate dielectric layer and a metal gate electrode.

The integrated circuit structure of example embodiment 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 or 12, wherein the first conductive line types have an upper surface with a metallic composition different from a metallic composition of an upper surface of the second conductive line types.

An integrated circuit structure includes a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a grating pattern interrupted by a partial body portion. A trench isolation layer is between the plurality of semiconductor bodies and adjacent to lower portions of the plurality of semiconductor bodies, but not adjacent to upper portions of the plurality of semiconductor bodies, where the trench isolation layer is over the partial body portion. One or more gate electrode stacks is on top surfaces and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies and on portions of the trench isolation layer. A back end of line (BEOL) metallization layer is above the one or more gate electrode stacks, the BEOL metallization layer including a plurality of alternating first and second conductive line types along a same direction, wherein the lines of the plurality of alternating first and second conductive line types each include a barrier layer along a bottom of the line but not along sidewalls of the line.

The integrated circuit structure of example embodiment 14, wherein the lines of the first conductive line type are spaced apart by a pitch, and wherein the lines of the second conductive line type are spaced apart by the pitch.

The integrated circuit structure of example embodiment 14 or 15, wherein the plurality of alternating first and second conductive line types is in an inter-layer dielectric (ILD) layer.

The integrated circuit structure of example embodiment 14 or 15, wherein the lines of the plurality of alternating first and second conductive line types are separated by an air gap.

The integrated circuit structure of example embodiment 14, 15, 16 or 17, wherein a total composition of the first conductive line type is the same as a total composition of the second conductive line type.

The integrated circuit structure of example embodiment 14, 15, 16 or 17, wherein a total composition of the first conductive line type substantially includes copper, and wherein a total composition of the second conductive line type substantially includes a material selected from the group consisting of Al, Ti, Zr, Hf, V, Ru, Co, Ni, Pd, Pt, Cu, W, Ag, Au and alloys thereof.

The integrated circuit structure of example embodiment 14, 15, 16, 17, 18 or 19, wherein one or more of the lines of the plurality of alternating first and second conductive line types is connected to an underlying via connected to an underlying metallization layer, the underlying metallization layer between the one or more gate electrode stacks and the BEOL metallization layer, and wherein one or more of the lines of the plurality of alternating first and second conductive line types is interrupted by a dielectric plug.

The integrated circuit structure of example embodiment 14, 15, 16, 17, 18, 19 or 20, wherein the grating pattern has a constant pitch.

The integrated circuit structure of example embodiment 14, 15, 16, 17, 18, 19, 20 or 21, further including source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are adjacent to the upper portions of the plurality of semiconductor bodies and include a semiconductor material different than the semiconductor material of the semiconductor bodies.

The integrated circuit structure of example embodiment 14, 15, 16, 17, 18, 19, 20 or 21, further including source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are within the upper portions of the plurality of semiconductor bodies.

The integrated circuit structure of example embodiment 14, 15, 16, 17, 18, 19, 20, 21, 22 or 23, wherein each of the one or more gate electrode stacks includes a high-k gate dielectric layer and a metal gate electrode.

An integrated circuit structure includes a plurality of semiconductor bodies protruding from a surface of a semiconductor substrate, the plurality of semiconductor bodies having a first grating pattern interrupted by a partial body portion. A trench isolation layer is between the plurality of semiconductor bodies and adjacent to lower portions of the plurality of semiconductor bodies, but not adjacent to upper portions of the plurality of semiconductor bodies, where the trench isolation layer is over the partial body portion. One or more gate electrode stacks is on top surfaces and laterally adjacent to sidewalls of the upper portions of the plurality of semiconductor bodies and on portions of the trench isolation layer. A first back end of line (BEOL) metallization layer is above the one or more gate electrode stacks, the first BEOL metallization layer including a second grating of alternating metal lines and dielectric lines in a first direction. A second BEOL metallization layer is above the first BEOL metallization layer, the second BEOL metallization layer including a third grating of alternating metal lines and dielectric lines in a second direction. The second direction is orthogonal to the first direction. Each metal line of the third grating of the second BEOL metallization layer is on a dielectric layer including alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first BEOL metallization layer. Each dielectric line of the third grating of the second BEOL metallization layer includes a continuous region of a third dielectric material distinct from the alternating distinct regions of the first dielectric material and the second dielectric material.

The integrated circuit structure of example embodiment 25, wherein a metal line of the second BEOL metallization layer is electrically coupled to a metal line of the first BEOL metallization layer by a via having a center directly aligned with a center of the metal line of the first BEOL metallization layer and with a center of the metal line of the second BEOL metallization layer.

The integrated circuit structure of example embodiment 25 or 26, wherein a metal line of the second BEOL metallization layer is disrupted by a plug having a center directly aligned with a center of a dielectric line of the first BEOL metallization layer.

The integrated circuit structure of example embodiment 25, 26 or 27, wherein none of the first dielectric material, the second dielectric material, and the third dielectric material are the same material.

The integrated circuit structure of example embodiment 25, 26 or 27, wherein only two of the first dielectric material, the second dielectric material, and the third dielectric material are the same material.

The integrated circuit structure of example embodiment 25, 26, 27, 28 or 29, wherein the alternating distinct regions of the first dielectric material and the second dielectric material are separated by seams, and wherein the continuous region of the third dielectric material is separated from the alternating distinct regions of the first dielectric material and the second dielectric material by seams.

The integrated circuit structure of example embodiment 25, 26, 27 or 30, wherein all of the first dielectric material, the second dielectric material, and the third dielectric material are the same material.

The integrated circuit structure of example embodiment 25, 26, 27, 28, 29, 30 or 31, wherein the first grating pattern has a constant pitch.

The integrated circuit structure of example embodiment 25, 26, 27, 28, 29, 30, 31 or 32, further including source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are adjacent to the upper portions of the plurality of semiconductor bodies and include a semiconductor material different than the semiconductor material of the semiconductor bodies.

The integrated circuit structure of example embodiment 25, 26, 27, 28, 29, 30, 31 or 32, further including source or drain regions on both sides of the one or more gate electrode stacks, wherein the source or drain regions are within the upper portions of the plurality of semiconductor bodies.

The integrated circuit structure of example embodiment 25, 26, 27, 28, 29, 30, 31, 32, 33 or 34, wherein each of the one or more gate electrode stacks includes a high-k gate dielectric layer and a metal gate electrode.

The integrated circuit structure of example embodiment 25, 26, 27, 28, 29, 30, 31, 32, 33, 34 or 35, wherein an etch stop layer or an additional dielectric layer separates the first BEOL metallization layer and the second BEOL metallization layer.

A method of fabricating an integrated circuit structure includes forming a plurality of backbone features above a substrate, forming a first set of spacers along sidewalls of each of the plurality of backbone features, the first set of spacers having a first material composition different than a material composition of the plurality of backbone features, forming a second set of spacers along sidewalls of each of the first set of spacers, the second set of spacers having a second material composition different than the first material composition and different than the material composition of the plurality of backbone features, forming a third set of spacers along sidewalls of each of the second set of spacers, the third set of spacers having a third material composition different than the first material composition, different than the second material composition, and different than the material composition of the plurality of backbone features, forming a fourth set of spacers along sidewalls of each of the third set of spacers, the fourth set of spacers having the second material composition, forming a fifth set of spacers laterally adjacent to sidewalls of each of the fourth set of spacers, the fifth set of spacers having the first material composition, removing the plurality of backbone features subsequent to forming the fifth set of spacers, forming a sixth set of spacers along sidewalls of each of the first set of spacers and along sidewalls of each of the fifth set of spacers subsequent to removing the plurality of backbone features, the sixth set of spacers having the second material composition, forming a final feature in each opening between adjacent pairs of spacers of the sixth set of spacers, planarizing the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the fifth set of spacers, the sixth set of spacers, and the final features to form a target foundation layer, and using the target foundation layer to form a metallization layer of a semiconductor structure.

The method of example embodiment 37, wherein forming the plurality of backbone features includes using a standard lithography operation.

The method of example embodiment 37 or 38, wherein forming the plurality of backbone features includes forming a plurality of features including a material selected from the group consisting of silicon nitride, silicon oxide and silicon carbide.

The method of example embodiment 37, 38 or 39, wherein forming the first set of spacers includes depositing a material of the first set of spacers conformal with the plurality of backbone features using an atomic layer deposition (ALD) process, and anisotropically etching the material of the first set of spacers to form the first set of spacers along the sidewalls of each of plurality of backbone features.

The method of example embodiment 37, 38 or 39, wherein forming the first set of spacers includes selectively growing a material of the first set of spacers along the sidewalls of each of plurality of backbone features.

The method of example embodiment 37, 38, 39, 40 or 41, wherein each final feature has a lateral width greater than a lateral width of each spacers from the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the fifth set of spacers, and the sixth set of spacers.

The method of example embodiment 37, 38, 39, 40, 41 or 42, wherein each final feature is formed by a merging of material growth formed along adjacent pairs of spacers of the sixth set of spacers.

The method of example embodiment 37, 38, 39, 40, 41, 42 or 43, wherein each final feature includes the third material composition.

The method of example embodiment 37, 38, 39, 40, 41, 42, 43 or 44, wherein using the target foundation layer to form the metallization layer of the semiconductor structure includes removing all portions of the first material composition to form a first plurality of trenches, and forming a first plurality of conductive lines in the first plurality of trenches.

The method of example embodiment 45, wherein using the target foundation layer to form the metallization layer of the semiconductor structure further includes removing all portions of the third material composition to form a second plurality of trenches, and forming a second plurality of conductive lines in the second plurality of trenches.

The method of example embodiment 46, wherein the first plurality of conductive lines and the second plurality of conductive lines are of a same composition.

The method of example embodiment 46, wherein the first plurality of conductive lines and the second plurality of conductive lines are of a different composition.

The method of example embodiment 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47 or 48, further including forming an additional 20-200 sets of spacers between forming the fifth set of spacers and the sixth set of spacers, and prior to removing the plurality of backbone features.

A target structure for fabricating an integrated circuit structure includes a first set of spacers above a hardmask layer above a substrate, the first set of spacers having a first material composition. A second set of spacers is along outer sidewalls of each of the first set of spacers, the second set of spacers having a second material composition different than the first material composition. A third set of spacers is along sidewalls of each of the second set of spacers, the third set of spacers having a third material composition different than the first material composition, and different than the second material composition. A fourth set of spacers is along sidewalls of each of the third set of spacers, the fourth set of spacers having the second material composition. A fifth set of spacers is laterally adjacent to sidewalls of each of the fourth set of spacers, the fifth set of spacers having the first material composition. A sixth set of spacers is along inner sidewalls of each of the first set of spacers and along sidewalls of each of the fifth set of spacers, the sixth set of spacers having the second material composition. A final feature is in each opening between adjacent pairs of spacers of the sixth set of spacers.

The target structure of example embodiment 50, wherein the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the fifth set of spacers, the sixth set of spacers, and the final features are substantially co-planar with one another.

The target structure of example embodiment 50 or 51, wherein each final feature has a lateral width greater than a lateral width of each spacers from the first set of spacers, the second set of spacers, the third set of spacers, the fourth set of spacers, the fifth set of spacers, and the sixth set of spacers.

The target structure of example embodiment 52, wherein the lateral width of each final feature is in the range of 6-12 nanometers.

The target structure of example embodiment 50, 51, 52 or 53, wherein each final feature has a seam approximately centered within the final feature.

The target structure of example embodiment 50, 51, 52, 53 or 54, wherein each final feature includes the third material composition.