Test key and method for validating the position of a word line overlaying a trench capacitor in DRAMS

A test key for validating the position of a word line structure overlaying a deep trench capacitor of a DRAM. The test key is deposited in the scribe line region of a wafer. The deep trench capacitor is deposited in the scribe line region and has a buried plate. A rectangular word line is deposited in the scribe line and covers a portion of the deep trench capacitor, and two passing word lines are deposited above the deep trench. A first doping region and a second doping region are deposited between the rectangular word line and the first passing word line and between the rectangular word line and the second passing word line respectively. A first plug, a second plug and a third plugs are coupled to the first doping region, the second doping region and the buried plate respectively.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a test key and particularly to a test key and method for validating the position of a word line structure overlaying the deep trench capacitor in a DRAM.

2. Description of the Prior Art

The essential charge storage devices in a DRAM (Dynamic Random Access Memory) are frequently implemented by trench capacitors. The trench capacitor is formed in the substrate and has a capacitance proportional to the depth of the trench. That is to say, by increasing the depth of the trench, which results in a larger surface area of the plates , the trench capacitor provides a higher capacitance.

FIG. 1 is a diagram showing the layout of a conventional DRAM. A trench capacitor 10 is disposed beneath the passing word line. A transistor 14 is coupled to a node 16 of the trench capacitor 10 through a diffusion region 18 . A diffusion region 20 is coupled to a plug 22 . The plug 22 is coupled to a bit line (not shown). Thus, data is read from or written into the trench capacitor 10 through the node 16 by operation of the transistor 14 . The transistor 14 is controlled by voltages on the word line 12 . When a high voltage level is on the word line 12 , a conductive channel is formed below the word line 12 so that a current flows from or to the node 16 through the diffusion regions 18 and 20 , whereby the data is read from or written into the capacitor 10 .

FIG. 2 shows a cross section along the line AA in FIG. 1 . An STI (Shallow Trench Isolation) 28 is formed in the substrate and trench capacitor to define an active area and isolate the trench capacitor 10 from the word line 12 formed later. After formation of the word line 12 , the diffusion regions 18 and 20 , used as a source and drain, on two sides of the word line 12 are formed by ion implantation with masking of the word line 12 and STI 28 . Thus, the position of the word line 12 overlaying the trench capacitor 10 has great impact on the profiles of the source and drain. For the DRAM having trench capacitors used as storage devices, an improper overlay of the word line and capacitor results in current leakage between adjacent memory cells or even defective cells. Validating the position of the word line is an essential step for DRAM manufacturing.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a test key and method for validating the position of a word line structure overlaying the deep trench capacitor in a DRAM.

The present invention provides a test key for validating the position of a word line overlaying a trench capacitor, which is deposited in a scribe line region of a wafer, the test key comprises a trench capacitor deposited in the scribe line region and has a buried plate, a rectangular word line deposited in the scribe line region and covers a portion of the trench capacitor, a first and second passing word line deposited above the trench capacitor, a first and second doping region respectively deposited between the rectangular word line and the first passing word line, and the rectangular word line and the second passing word line, a first plug coupled to the first doping region, a second plug coupled to the second doping region, and a third plug coupled to the buried plate.

The present invention further provides a method for validating the position of a word line overlaying a trench capacitor, comprising the steps of providing a wafer having at least one scribe line region and a memory cell region, forming a test key in the scribe line region and a plurality of memory cells in the memory cell region, wherein the test key comprises a trench capacitor deposited in the scribe line region and has a buried plate, a rectangular word line deposited in the scribe line region and covers a portion of the trench capacitor, a first and second passing word line deposited above the trench capacitor, a first and second doping region respectively deposited between the rectangular word line and the first passing word line, and the rectangular word line and the second passing word line, a first plug coupled to the first doping region, a second plug coupled to the second doping region, and a third plug coupled to the buried plate, measuring a first current between the first and third plug resulting from applying a predetermined voltage difference between the first and third plug, applying a predetermined voltage level on the rectangular word line and floating the second plug, and a second current between the second and third plug resulting from applying the predetermined voltage difference between the second and third plug, applying the predetermined voltage level on the rectangular word line and floating the first plug, and validating the position of the rectangular word line by the measured first and second currents.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3 shows the layout of a test key for validating the position of the word line structure overlaying the deep trench capacitors in a DRAM according to one embodiment of the invention. FIGS. 4 a and 4 b show cross sections along the line BB and CC in FIG. 3 .

A trench capacitor 110 is formed in the scribe line region 160 of a wafer 100 . The trench capacitor 110 includes a storage node 11 b , buried plates 181 in a buried N well and a dielectric layer therebetween. The storage node 11 b is isolated from the P well by a collar oxide 126 .

A rectangular word line 12 a , and passing word lines 12 b and 12 c are disposed on the scribe line region 160 . The rectangular word line 12 a overlaps part of the deep trench capacitor 110 while the passing word lines 12 b and 12 c are located above the deep trench capacitor 110 . The widths of the passing word lines 12 b and 12 c are substantially the same and are 0.6 m approximately, which is smaller than that of the rectangular word line 12 a , 0.6 m approximately.

By ion implantation, doping regions 201 and 202 are respectively formed between the rectangular word line 12 a and passing word line 12 b , and the passing word lines 12 b and 12 c , as shown in FIG. 4 a.

Referring to FIGS. 4 a and 4 b , it is noted that the buried plates 181 , doping regions 201 and 202 , and rectangular word line 12 a form two transistors 141 and 142 . The gate, source and drain of the transistor 141 are respectively the rectangular word line 12 a , buried plate 181 and doping region 201 while those of the transistor 142 are respectively the rectangular word line 12 a , buried plate 181 and doping region 202 .

For validating the position of the word line structure using the test key, currents I 1 and I 2 respectively between the plugs CS 1 and CB 1 , and CS 1 and CS 2 are measured under specific bias configurations.

The current I 1 results from applying a predetermined bias voltage Vbias to the rectangular word line 12 a , applying a voltage difference VDC between the plugs CS 1 and CB 1 , and floating the plug CS 2 . The magnitude of the current I 1 is derived by the following equation:

where W 1 is the width of the plug CB 1 , Lbs 1 is the diffusion distance of the buried plate 181 , L is the misaligned distance of the rectangular word line 12 a , Ls is the distance between the region 201 and trench capacitor 110 , and C is a constant.

The current I 2 results from applying the predetermined bias voltage Vbias to the rectangular word line 12 a , applying the voltage difference VDC between the plugs CS 1 and CS 2 , and floating the plug CS 1 . The magnitude of the current I 2 is derived by the following equation:

where W 2 is the width of the plug CB 2 , Lbs 2 is the diffusion distance of the buried plate 181 , L is the misaligned distance of the rectangular word line 12 a , Ls 2 is the distance between the region 202 and trench capacitor 110 , and C is a constant.

Since the transistors 141 and 142 are formed by processing steps using the same parameters, the widths W 1 and W 2 of the plugs CB 1 and CB 2 are the same and represented by W, the diffusion distances of all the buried plates 181 are the same and represented by Lbs, and the distances Ls 1 and Ls 2 are also the same and represented by Ls. Thus, from the equations (1) and (2), the ratio I 1 /I 2 and L are derived by the following equations.

Accordingly, there is no misalignment ( L 0) only if the currents I 1 and I 2 are substantially the same. On the other hand, if there is a significant difference between the magnitudes of the currents I 1 and I 2 , the misaligned distance of the rectangular word line 12 a can be derived by the equation (4). The current I 1 is smaller than I 2 if the word lines 12 a , 12 b and 12 c are improperly close to the transistor 141 while the current I 1 is larger than I 2 if the word lines 12 a , 12 b and 12 c are improperly close to the transistor 142 .

The method for validating the position of a word line structure within a deep trench capacitor in a DRAM according to one embodiment of the invention is described in the following.

First, a wafer having at least one scribe line region and a memory cell region is provided.

Second, a test key, as shown in FIG. 3 , is formed in the scribe line region and a plurality of memory cells, as shown in FIGS. 1 and 2 are formed in the memory cell region.

Third, currents I 1 and I 2 respectively between the plugs CS 1 and CB 1 , and CS 1 and CS 2 are measured under specific bias configurations. The current I 1 results from applying a predetermined bias voltage Vbias to the rectangular word line 12 a , applying a voltage difference VDC between the plugs CS 1 and CB 1 , and floating the plug CS 2 . The current I 2 results from applying the predetermined bias voltage Vbias to the rectangular word line 12 a , applying the voltage difference VDC between the plugs CS 1 and CS 2 , and floating the plug CS 1 .

Finally, the misalignment of the rectangular word line 12 a is detected by the magnitudes of the currents I 1 and I 2 according to the previously described equations (3) and (4). There is no misalignment ( L 0) only if the currents I 1 and I 2 are substantially the same. On the other hand, if there is a significant difference between the magnitudes of the currents I 1 and I 2 , the misaligned distance of the rectangular word line 12 a can be derived by the equation (4). The current I 1 is smaller than I 2 if the word lines 12 a , 12 b and 12 c are improperly close to the transistor 141 while the current I 1 is larger than I 2 if the word lines 12 a , 12 b and 12 c are improperly close to the transistor 142 .

Since the positions of the word lines of the test key and memory cells are interlocked , validating the position of the word line structure used in the memory cells can be also implemented by measurement of the currents I 1 and I 2 .

In conclusion, the present invention provides a test key and method for validating the position of the word line structure overlaying the deep trench capacitors in a DRAM. The validity of the word line position is determined by current measurement. This achieves rapid validation without occupying part of the memory cell region by the test key which is disposed in the scribe line region of the wafer.