Methods of forming semiconductor devices

In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device includes forming a trench from a top surface of a substrate having a device region. The device region is adjacent to the top surface than an opposite bottom surface. The trench surrounds the sidewalls of the device region. The trench is filled with an adhesive. An adhesive layer is formed over the top surface of the substrate. A carrier is attached with the adhesive layer. The substrate is thinned from the bottom surface to expose at least a portion of the adhesive and a back surface of the device region. The adhesive layer is removed and adhesive is etched to expose a sidewall of the device region.

TECHNICAL FIELD

The present invention relates generally to semiconductor devices, and more particularly to method of forming semiconductor devices.

BACKGROUND

Semiconductor devices are used in many electronic and other applications. Semiconductor devices may comprise integrated circuits that are formed on semiconductor wafers. Alternatively, semiconductor devices may be formed as monolithic devices, e.g., discrete devices. Semiconductor devices are formed on semiconductor wafers by depositing many types of thin films of material over the semiconductor wafers, patterning the thin films of material, doping selective regions of the semiconductor wafers, etc.

In a conventional semiconductor fabrication process, a large number of semiconductor devices are fabricated in a single wafer. After completion of device level and interconnect level fabrication processes, the semiconductor devices on the wafer are separated. For example, the wafer may undergo singulation. During singulation, the wafer is mechanically treated and the semiconductor devices are physically separated to form individual dies. Purely mechanical separation is not very space efficient compared to chemical processes. However, chemical separation of small sized dies requires overcoming many difficult process issues.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by illustrative embodiments of the present invention.

In accordance with an embodiment of the present invention, a method of fabricating a semiconductor device comprises forming a trench from a top surface of a substrate having a device region, which is adjacent to the top surface than an opposite bottom surface. The trench surrounds the sidewalls of the device region. The trench is filled with an adhesive. An adhesive layer is formed over the top surface of the substrate. A carrier is attached with the adhesive layer. The substrate is thinned from the bottom surface to expose at least a portion of the adhesive and a back surface of the device region. The adhesive layer is removed and adhesive is etched to expose a sidewall of the device region.

In accordance with another embodiment of the present invention, a method of fabricating a semiconductor device includes embedding a plurality of chips in an adhesive. The adhesive covers a top surface and sidewalls of each chip of the plurality of chips. A high density plasma is generated using CF4and oxygen. The adhesive is removed using the high density plasma thereby exposing the sidewalls and the top surface.

In accordance with another embodiment of the present invention, a method of fabricating a semiconductor device includes forming a trench from a top surface of a substrate having a device region. The device region is adjacent to the top surface than an opposite bottom surface of the substrate. The trench surrounds sidewalls of the device region. The trench is filled with an adhesive. An adhesive layer is formed by the adhesive over the top surface of the substrate. A carrier is attached with the adhesive layer. The substrate is thinned from the bottom surface to expose at least a portion of the adhesive and a back surface of the device region. A high density plasma is generated using CF4and oxygen. The adhesive in the trench and over the top surface of the substrate is etched using the high density plasma to expose a sidewall of the device region.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Chip Scale Packages (CSP) are used for packing small components such as diodes, transistors, and others. CSPs typically have an area no greater than 1.2 times that of the die and are usually a single-die, direct surface mountable package. For example, die sizes may be vary between about 0.05 mm2to about 50 mm2. Because of the small sized dies, each wafer yields many thousand units. For example, an 8-inch wafer can yield up to 200,000 to 600,000 dies. Assembly of such small sized dies may be performed after fabrication in a different or same facility by picking up loose dies, for example, using a special pick up process like “ball feed” method.

For small sized dies, substantial amount of real estate on the silicon wafer may be lost to dicing streets, which are regions that separate adjacent dies. Therefore, methods of forming small semiconductor dies are needed using narrow dicing streets. Narrow dicing streets may be enabled by the use of chemical and/or plasma etching processes. However, chemical etching processes cannot practically (within a reasonable time) etch through the complete wafer. Therefore, a combination of mechanical and chemical processes has to be used in dicing a wafer into a plurality of semiconductor dies. However, such methods require overcoming the problems associated with stabilizing a thin wafer during a thinning or grinding process. Embodiments of the invention overcome these and other problems to enable dicing of semiconductor wafer into dies.

FIGS. 1-8illustrate a method of fabricating a semiconductor die in accordance with an embodiment of the invention.FIGS. 9-12illustrate alternative embodiments of fabricating the semiconductor die.

FIG. 1, which includesFIGS. 1A and 1B, illustrates a semiconductor substrate after formation of device regions and metallization layers, whereinFIG. 1Aillustrates a cross-sectional view andFIG. 1Billustrates a top view.

Referring toFIG. 1A, a semiconductor substrate10after the completion of front end processing and back end processing is illustrated. The semiconductor substrate10has a plurality of semiconductor devices, i.e., chip100, formed within. The chip100may be any type of chip. For example, the chip100may be a logic chip, a memory chip, an analog chip, and other types of chips. The chip100may comprise a plurality of devices such as transistors or diodes forming an integrated circuit or may be a discrete device such as a single transistor or a single diode.

In one embodiment, the substrate10may comprise a semiconductor wafer such as a silicon wafer. In other embodiments, the substrate10may comprise other semiconductor materials including alloys such as SiGe, SiC or compound semiconductor materials such as GaAs, InP, InAs, GaN, sapphire, silicon on insulation, for example.

Referring toFIG. 1A, device regions110are disposed within the substrate10. The device regions110may include doped regions in various embodiments. Further, some portion of the device regions110may be formed over the substrate10. The device regions110may include the active regions such as channel regions of transistors.

The substrate10comprises a top surface11and an opposite bottom surface12. In various embodiments, the active devices are formed closer to the top surface11of the substrate10than the bottom surface12. The active devices are formed in device regions110of the substrate10. Device regions110extends over a depth dDR, which depending on the device, is about 50 μm to about 500 μm, and about 200 μm in one embodiment.

In various embodiments, all necessary interconnects, connections, pads etc. for coupling between devices and/or with external circuitry are formed over the substrate10. Accordingly, a metallization layer20is formed over the substrate10. The metallization layer20may comprise one or more levels of metallization. Each level of metallization may comprise metal lines or vias embedded within an insulating layer. The metallization layer20may comprise metal lines and vias to contact the device regions110and also to couple different devices within each chip100.

A protective layer30, such as a passivation layer, may be formed over the metallization layer20before further processing. The protective layer30may comprise an oxide, nitride, polyimide, or other suitable materials known to one skilled in the art. The protective layer30may comprise a hard mask in one embodiment, and a resist mask in another embodiment. The protective layer30helps to protect the metallization layer20as well as the device regions110during subsequent processing.

Further, a final depth of the chip100will be determined after thinning as will be described subsequently. The bottom surface of the device regions110is therefore shown as dashed lines.

FIG. 1Billustrates a top view of the substrate10comprising a plurality of chips. Each chip100is separated from each other by a plurality of regions called scribe lines or dicing channels50. The dicing channels50may comprise additional circuitry or other structures, which may be used for testing.

Referring to the cross-sectional view ofFIG. 2, a plurality of trenches60is formed. In various embodiments, the plurality of trenches60is formed using a plasma dicing process. The plurality of trenches60are formed along the dicing channels50. As illustrated inFIG. 2, after the partial dicing, the height H60of the plurality of trenches60is about 50 μm to about 500 μm, and about 200 μm in one embodiment. The width W60of the plurality of trenches60is about 10 μm to about 50 μm, and about 20 μm in one embodiment. The length L100of the chip100is about 200 μm to about 10 mm, and about 300 μm in one embodiment. The ratio of the height H60of the plurality of trenches60to the length L100of the chip100is about 2.5:1 (small chip area) to about 1:20 (large chip area).

Referring toFIG. 3, the substrate10is attached to a carrier80using an adhesive. The plurality of trenches60is filled with an adhesive compound70. In various embodiments, the adhesive compound70surrounds all the sidewalls around the chip100. In various embodiments, having an adhesive layer over only the top surface of the protective layer30as in conventional wafer handling process is not sufficient to provide mechanical stability because of the large number of small chips100. Because of the small area of the chip100and the large number of chips100per wafer (e.g., about 200,000 to about 500,000), they are also supported along the sidewalls to avoid mechanical failure of the substrate10during substrate thinning.

After filling the plurality of trenches60with the adhesive compound70, an overfill layer70A is formed over the top surface of the protective layer30. In various embodiments, the overfill layer70A has a thickness of about 1 μm to about 100 μm.

A carrier80is placed over the overfill layer70A of the adhesive compound70. The viscous nature of the adhesive compound70allows it to flow along the sidewalls of the plurality of trenches60. In various embodiments, the surface tension and viscosity of the adhesive compound70are selected to maximize wetting of the sidewalls of the plurality of trenches60.

Further, in some embodiments, a primer coating may be applied prior to coating the adhesive compound70. The primer coating is tuned to react with the surface of the plurality of trenches60and convert potentially high surface energy surfaces to lower surface energy surfaces by forming a primer layer. Thus, the adhesive compound70interacts only with the primer layer improving the bonding.

The adhesive compound70may comprise an organic compound such an epoxy based compound in one or more embodiments. In various embodiments, the adhesive compound70comprises an acrylic based, not photoactive, organic glue. In another embodiment, the adhesive compound70comprises SU-8, which is a negative tone epoxy based photo resist.

In alternative embodiments, the adhesive compound70may comprise a molding compound. In one embodiment, the adhesive compound70comprises an imide and/or components such a poly-methyl-methacrylate (PMMA) used in forming a poly-imide.

In another embodiment, the adhesive compound70comprises components for forming an epoxy-based resin or co-polymer and may include components for a solid-phase epoxy resin and a liquid-phase epoxy resin. Embodiments of the invention also include combinations of different type of adhesive components and non-adhesive components such as combinations of acrylic base organic glue, SU-8, imide, epoxy-based resins etc.

In various embodiments, the adhesive component70comprises less than about 1% inorganic material, and about 0.1% to about 1% inorganic material in one embodiment. The absence of inorganic content improves the removal of the adhesive component70without leaving residues after plasma etching (described below inFIG. 7).

In one or more embodiments, the adhesive compound70may comprise thermosetting resins, which may be cured by annealing at an elevated temperature. Alternatively, in some embodiments, a low temperature anneal or bake may be performed to cure the adhesive compound70so that adhesive bonding between the carrier80and the adhesive compound70and between the adhesive compound70and the substrate10is formed. Some embodiments may not require any additional heating and may be cured at room temperature.

However, in various embodiments, the adhesive component70is chosen to minimize high temperature processes because, at this stage of processing, the device regions110and the metallization layer20has been already fabricated and therefore high temperature processing can have deleterious effect on these layers.

As next illustrated inFIG. 4, the bottom surface12of the substrate10is exposed to a thinning process. A thinning tool90, which may be a grinding tool in one embodiment, reduces the thickness of the substrate10. In another embodiment, the thinning tool90may use a chemical process such as a wet etch or a plasma etch to thin the substrate10.

Referring toFIG. 5, the thinning process is stopped after reaching the bottom surface of the plurality of trenches60. Thus, after the thinning, an under surface13of the device regions110is exposed along with a surface of the adhesive component70within the plurality of trenches60.

A back side metallization layer120is formed over the under surface13. The back side metallization layer120may be formed as a blanket (unpatterned) metal layer in one embodiment. In another embodiment, a patterned metal layer may be formed within the back side metallization layer120. In one embodiment, redistribution lines may be formed within the back side metallization layer120. The redistribution lines may be used as interconnect on the back side, for example, coupling different circuit blocks (e.g., devices on a system on chip).

FIG. 6, which includesFIGS. 6A and 6B, illustrates the plurality of chips embedded in a matrix of the adhesive component70, whereinFIG. 6Aillustrates a cross-sectional view andFIG. 6Billustrates a top view. At this stage of processing, the chips100are suspended within the adhesive component70because the substrate10has been removed by thinning (FIG. 6B). The chips100may be attached along the under surface13by the back side metallization layer120.

Referring toFIG. 7, the embedded chips100are placed within a plasma chamber150of a plasma tool and subjected to a plasma process.

In various embodiments, a high density plasma is used to remove the adhesive component70. Accordingly, the plasma tool is a high density plasma etch tool, for example, an microwave generator plasma tool or alternatively an inductively coupled plasma tool. The plasma chemistry is controlled by a flow of gasses through the chamber from an inlet181and an outlet182. The wafer like structure having the plurality of chips100embedded in the adhesive compound70is placed on a chuck. The plasma may be generated by powering the power input node190from about 100 W to about 2000 W, and about 850 W in one embodiment. Additionally remote plasma generated by a microwave plasma generation unit may be used in some embodiments.

In various embodiments, the plasma is formed from a mixture of tetra-fluoro-methane (CF4) and oxygen. In an etch chemistry comprising CF4, the addition of O2results in creation of more free fluorine radicals that increases the reactivity of the plasma.

Conventional plasma processes using low density process significantly etch silicon dioxide and silicon nitride. Further, this etching is isotropic exasperating any over etch of the overlying layers. Embodiments of the invention avoid such deleterious removal of oxide and nitride layers from over the chip100by using an etch chemistry having improved selectivity. In various embodiments, the relative amount of CF4in the plasma relative to oxygen is very low, which improves the selectivity of the plasma. In one or more embodiments, wherein a ratio of the amount of the CF4to the amount of the oxygen in the gas fed through the inlet181into the plasma chamber150is about 1:10 to about 1:100. In various embodiments, the etch selectivity between the adhesive component70and silicon dioxide is about 1:0.05 to about 1:0.1, between the adhesive component70and silicon nitride is about 1:0.05 to about 1:0.1, and between the adhesive component70and silicon is about 1:0.025 to about 1:0.05. Therefore, the etching process removes the adhesive component70without removing the other components of the chip100.

Further, in various embodiments, the etching is isotropic owing to the large number of fluorine radicals and chamber pressure. Having an isotropic etch process avoids the formation of spacers of adhesive component70around the sidewalls of the device regions110. After the plasma process, the sidewalls of the device regions110expose the semiconductor material leaving no particles/residues or spacers of the adhesive component70, which may be oxidized subsequently to form a native oxide. Advantageously, because of the volatile nature of the adhesive component70no particles or residue remain.

In various embodiments, the plasma process advantageously removes the adhesive component70, for example, having a thickness of about 10 μm to about 50 μm, in less than one hour.

FIG. 8, which includesFIGS. 8A and 8B, illustrates the chips100after the removal of the adhesive component70in accordance with an embodiment of the invention, whereinFIG. 8Aillustrates a cross-sectional view andFIG. 8Billustrates a top view. The back side metallization layer120may be diced or may be sufficiently thin to be broken by mechanical pressure (e.g., bending) thereby forming a plurality of semiconductor devices.

FIGS. 9-11illustrate an alternate embodiment of the invention of forming a plurality of semiconductor devices.

In this embodiment, the process flow follows the prior embodiment as described with respect toFIGS. 1-2in forming a plurality of trenches60. However, subsequently, referring toFIG. 9, more than one adhesive is used in this embodiment. First, the plurality of trenches60is filled with an adhesive component70. After filling the plurality of trenches60, an adhesive layer having a second adhesive component170is formed over the top surface of the protection layer30and the top surface of the adhesive component70. For example, the second adhesive component170may be chosen so that it is easily removed with a wet etch process thereby reducing the time for the plasma etch process. Alternatively, the second adhesive component170may be chosen to be removed faster in the plasma process. For example, the second adhesive component170may be less dense compared to the adhesive component70and may be etched faster. The second adhesive component170may have a different composition than the adhesive component70because of the different requirements between the material filling the trenches60and the planar adhesive layer. For example, the material filling the trenches60may be required to have good wettability so as to provide mechanical stability while the adhesive layer between the substrate10and the carrier80may only need to provide bonding support.

Referring toFIG. 10, a back side metallization layer120is formed as in the prior embodiment. Next, as illustrated inFIG. 11, the second adhesive component170is removed in a first etching step. In one embodiment, the first etching step is a wet etch process.

Next, the chips100are placed within an etch chamber and the adhesive component70is etched in a high density plasma as described with respect toFIG. 7. Subsequent processing follows the prior embodiment.

FIG. 12illustrates another embodiment of a method of fabricating a semiconductor device.

This embodiment is similar to the embodiment ofFIG. 9-11because it has the adhesive component70and the second adhesive component170. However, this embodiment further includes a third adhesive component270between the adhesive component70and the sidewalls of the chip100. In some embodiments, the second adhesive component170may be skipped thereby having only the adhesive component70and the third adhesive component270.

As illustrated inFIG. 12, the third adhesive component270is formed as a liner over the sidewalls of the plurality of trenches60, which form the sidewalls of the chip100. The third adhesive component270may comprise a thickness of about 0.05 μm to about 0.1 μm in various embodiments. The third adhesive component270may be used to promote adhesion while improving the ease of removal of the adhesive subsequently.

For example, in one embodiment, the third adhesive component270may be much easier to remove in a etch process such as a plasma etch compared to the adhesive component70. Therefore, the adhesive contacting the sidewalls of the chip100(third adhesive component270) is removed without leaving any residues. In one or more alternative embodiments, the adhesive material may comprise a plurality of layers. Thus, in this embodiment, the density of the adhesive material reduces along the depth so that the deeper layers of the adhesive etch faster than the upper layers.

Further, in another example embodiment, the adhesive component70may be easier to remove than the third adhesive component270. Such an embodiment may be used to lower the plasma etching time. This may be advantageous when the third adhesive component270provides the necessary structural stability that may not be possible to achieve using the adhesive component70directly on the sidewalls of the chip100. Thus, in this embodiment, the density of the adhesive material increases along the depth so that the deeper layers of the adhesive take longer to etch while the upper layers are removed relatively faster.

While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. As an illustration, the embodiments described inFIG. 1-8may be combined with the embodiments described inFIG. 9-11orFIG. 12. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present invention.