Memory device

A memory device including a first cell block including a plurality of word lines and first to Kth (K is a natural number) redundancy word lines, a second cell block including a plurality of word lines and (K+1)th to Nth (N is a natural number greater than K) redundancy word lines, and a control unit suitable for performing control so that the first to Nth redundancy word lines replace the word lines of the first or second cell block, refreshing the word lines of the first and the second cell blocks simultaneously in a first section, and sequentially refreshing the first to Nth redundancy word lines in a second section.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The present application claims priority of Korean Patent Application No. 10-2015-0031658, filed on Mar. 6, 2015, which is incorporated herein by reference in its entirety.

BACKGROUND

Exemplary embodiments of the present invention relate to a memory device.

2. Description of the Related Art

Memory cells are the most basic unit for storing information and may each store one or more bits of data. Integration of memory devices has increased to the point where tens of millions of memory cells are included in a single memory device. But if even one memory cell has a defect, the memory device may not perform as required. However, discarding such memory devices would hurt product yield.

Several methods are being proposed to handle defective memory cells of memory devices. For example, a memory device may include extra cells (referred to as redundancy cells) in addition to memory cells. The memory device may be repaired using redundancy cells to replace the defective memory cells. This repair operation using redundancy cells is performed on each row/column. That is, the memory and redundancy cells are arranged in rows and columns for each cell block. When a defective memory cell occurs in a cell block, the row/column of memory cells that include the defective memory cell is substituted with a row/column of redundancy cells.

FIG. 1is a diagram illustrating row repair operations for a memory device.

Referring toFIG. 1, the memory device may include a plurality of cell blocks110to140, each including a plurality of word lines WL0to WL511and redundancy word lines RWL0to RWL7, and address storage units150to180corresponding to the plurality of cell blocks110to140. The address storage units150to180may include fuse sets FS0to FS7corresponding to the redundancy word lines of the cell blocks110to140.

The address storage units150to180may store the addresses of the word lines to be replaced with the redundancy word lines in the cell block110to140. For example, if the word line WL0of the cell block110is to be replaced with the redundancy word line RWL0of the cell block110, the address of the word line WL0of the cell block110may be stored in the fuse set FS0of the address storage unit150. When an active operation is performed, the memory device may activate the redundancy word line RWL0of the cell block110instead of the word line WL0of the cell block110using the address of the word line WL0of the cell block110that has been stored in the fuse set FS0of the address storage unit150.

In the memory device ofFIG. 1, the redundancy word lines of each cell block may replace only the word lines of the corresponding cell block in which they are included resulting in inefficiencies. For example, when 9 defective word lines are present in the cell block110, all 9 defective word lines cannot be replaced because 8 redundancy word lines RWL0to RWL7are used in the cell block110. Accordingly, the memory device is treated as defective product even if there are no defective word lines in the remaining cell blocks120to140and the remaining 24 redundancy word lines of the cell blocks120to140are not used.

SUMMARY

Various embodiments are directed to a memory device capable of repairing a word line of one cell block using a redundancy word line of another cell block.

Also, various embodiments are directed to a memory device, wherein a word line of one cell block is substituted with a redundancy word line of another cell block by refreshing redundancy word lines only after all the word lines are refreshed and two word lines of each cell block are prevented from being simultaneously activated although the word lines of a plurality of cell blocks are refreshed simultaneously.

In an embodiment, a memory device may including a first cell block including a plurality of word lines and first to Kth(K is a natural number) redundancy word lines, a second cell block including a plurality of word lines and (K+1)thto Nth(N is a natural number greater than K) redundancy word lines, and a control unit suitable for controlling the first to Nthredundancy word lines to replace the word lines of the first or second cell block, refreshing the word lines of the first and the second cell blocks simultaneously in a first section, and sequentially refreshing the first to Nthredundancy word lines in a second section.

In an embodiment, a memory device may include a first cell block including a plurality of word lines and first to Kth(K is a natural number) redundancy word lines, a second cell block including a plurality of word lines and (K+1)thto Nth(N is a natural number greater than K) redundancy word lines, first to Nthaddress storage units corresponding to the first to Nthredundancy word lines and suitable for storing addresses of the word lines of the first or second cell block, an address counting unit suitable for storing a counting address by counting when a refresh operation is performed, and a word line control unit suitable for refreshing word lines that belong to the first and the second cell blocks and correspond to the counting address in a first section, and refreshing a redundancy word line that belongs to the first to Nthredundancy word lines and corresponds to the counting address in a second section, wherein when the counting address is identical with one or more of the addresses stored in the address storage units in the first section, the word line control unit skips refreshing the word line corresponding to the counting address.

In an embodiment, a memory device may include a plurality of cell blocks including a plurality of word lines, a plurality of redundancy word lines suitable for replacing corresponding word lines of the cell blocks, and a control unit suitable for refreshing the word lines of the cell blocks simultaneously, except for the replaced word lines by the redundancy word lines, in a first section, and sequentially refreshing the redundancy word lines in a second section.

DETAILED DESCRIPTION

FIG. 2is a diagram illustrating a refresh operation of a memory device including a plurality of cell blocks.

Referring toFIG. 2, the memory device may include a plurality of cell blocks210to240and an address counting unit250. The plurality of cell blocks210to240may include word lines WL0to WL511and redundancy word lines RWL0to RWL15. In the memory device ofFIG. 2, the redundancy word lines RWL0to RWL15included in each of the cell blocks210to240may also repair word lines included in another cell block.

When performing a refresh operation, the memory device ofFIG. 2may refresh the plurality of cell blocks210to240simultaneously. More specifically, whenever a refresh pulse REFP is activated, the memory device may refresh the word lines of the respective cell blocks210to240. The memory device may select word lines to be refreshed in the respective cell blocks210to240using a counting address CA generated by the address counting unit250. Whenever the refresh pulse REFP is applied, the address counting unit250may change the value of the counting address CA.

When performing a refresh operation, the memory device ofFIG. 2may sequentially select the word line WL0to the word line WL511of each of the cell blocks210to240using the counting address CA. If a selected word line has been replaced by a redundancy word line, the memory device may refresh the redundancy word line instead of the selected word line.

In this example, the word line WL0of the cell block210has been replaced by the redundancy word line RWL0of the cell block230. When the refresh pulse REFP is activated, the word lines of the respective cell blocks210to240corresponding to the counting address CA are refreshed. For example, if the counting address CA corresponds to the word line WL0, the word lines WL0of the respective cell blocks220to240are refreshed (REFRESH). Since the word line WL0of the cell block210has been replaced by the redundancy word line RWL0of the cell block230, the redundancy word line RWL0of the cell block230is refreshed (REFRESH_RWL) instead of the word line WL0of the cell block210. When the two word lines WL0and RWL0of a single cell block230are simultaneously refreshed, the data of memory cells connected to the refreshed word lines collide.

Accordingly, in order to repair a word line of one cell block using a redundancy word line of another cell block, such a data collision is to be prevented when a refresh operation is performed.

In the examples ofFIGS. 3 to 6, a memory device includes two cell blocks and each of the cell blocks includes 512 word lines and 8 redundancy word lines. The number of cell blocks included in a memory device and the number of word lines and redundancy word lines included in each cell block may be changed depending on the circuit design of the memory device.

FIG. 3is a configuration diagram illustrating a memory device in accordance with an embodiment of the present invention.

Referring toFIG. 3, the memory device may include a command input unit310, an address input unit320, a command decoder330, a control unit340, a first cell block350, and a second cell block360.

The command input unit310may receive commands CMDs from a memory controller, and the address input unit320may receive addresses ADDs from the memory controller. Each of the commands CMDs and the addresses ADDs may include signals of multiple bits.

The command decoder330may generate an active command ACT, a precharge command PRE, a refresh command REF, a self-refresh start command SREF_EN, and a self-refresh end command SREF_EX by decoding the commands CMDs received from the command input unit310. The command decoder330may activate which of the active command ACT, the precharge command PRE, the refresh command REF, the self-refresh start command SREF_EN, and the self-refresh end command SREF_EX corresponds to a combination of the received commands CMDs.

The first cell block350may include a plurality of word lines WL0to WL511and first to eighth redundancy word lines RWL0to RWL7. The second cell block360may include a plurality of word lines WL0to WL511and ninth to sixteenth redundancy word lines RWL0to RWL15. Each of the word lines WL0to WL511and RWL0to RWL15may be connected to memory cells MC.

The control unit340may control the word lines WL0to WL511of the cell blocks350and360in response to the commands ACT, PRE, REF, SREF_EN, and SREF_EX. The control unit340may activate a selected word line in response to an input address ADD<0:9> when the active command ACT is activated and precharge the activated word line when the precharge command PRE is activated. When the refresh command REF is activated, the control unit340may refresh a word line (i.e., activate the word line for a specific time).

Furthermore, the control unit340may periodically refresh a word line during a section from a point of time at which the self-refresh start command SREF_EN is activated to a point of time at which the self-refresh end command SREF_EX is activated.

When the active command ACT is activated, the control unit340may activate a word line corresponding to the input address ADD<0:9>. Each of the input addresses ADD<0:9> may include a block address ADD<9> for selecting one of the first and the second cell blocks350and360and a row address ADD<0:8> for selecting one of the word lines WL0to WL511of the selected cell block. When the word line corresponding to the input address ADD<0:9> has been replaced by a redundancy word line, the control unit340may activate the redundancy word line.

In a first section, the control unit340may refresh the first and the second cell blocks350and360simultaneously and sequentially refresh the plurality of word lines WL0to WL511of the first and the second cell blocks350and360. The first section may be a section in which the word lines WL0to WL511are refreshed.

In the first section, the control unit340may bypass the refresh of a selected word line that has been substituted with a redundancy word line. That is, the control unit340skips a refresh operation on the selected word line and the substituted redundancy word line.

In a second section, the control unit340may sequentially refresh the first to sixteenth redundancy word lines RWL0to RWL15. The redundancy word lines RWL0to RWL15of the second section may be refreshed. The first section and the second section may be alternately repeated. For example, when all the word lines WL0to WL511of the first and the second cell blocks350and360are sequentially refreshed in the first section, the memory device may terminate the first section and enter the second section. When all the redundancy word lines RWL0to RWL15are sequentially refreshed in the second section, the first section may start again. In the second section, the control unit340bypasses the refresh of a redundancy word line that has failed among the first to sixteenth redundancy word lines RWL0to RWL15.

FIGS. 4A and 4Bare diagrams illustrating the operation of the memory device ofFIG. 3.FIG. 4Ais a diagram illustrating the active operation of the memory device, andFIG. 4Bis a diagram illustrating the refresh operation of the memory device. Referring toFIGS. 4A and 4B, the first and the second cell blocks350and360and the word lines WL0to WL511and the redundancy word lines RWL0to RWL15are illustrated.

A left-sided diagram401ofFIG. 4Aillustrates a word line (e.g., the word line55of the first cell block350) corresponding to the input address ADD<0:9> in the memory device that has not been repaired. A right-sided diagram402ofFIG. 4Aillustrates that a word line (e.g., the word line55of the first cell block350) corresponding to the input address ADD<0:9> in the memory device has been repaired (e.g., the word line55of the first cell block350has been replaced by the redundancy word line RWL13).

Referring to the diagram401, when the active command ACT is applied and the word line55of the first cell block350is selected by the address ADD<0:9>, the word line55of the first cell block350is activated. Thereafter, when the precharge command PRE is activated, the word line55of the first cell block350is precharged.

Referring to the diagram402, when the active command ACT is applied and the word line55of the first cell block350is selected by the address ADD<0:9>, the redundancy word line RWL13is activated instead of the word line55of the first cell block350. When the precharge command PRE is activated, the redundancy word line RWL13is precharged.

A left-sided diagram403ofFIG. 4Billustrates a refresh operation in the first section, and a right-sided diagram404ofFIG. 4Billustrates a refresh operation in the second section. Likewise, as shown in the diagram402ofFIG. 4A, the word line55of the first cell block350in the memory device has been replaced by the redundancy word line RWL13.

Referring to the diagram403, in the first section, the first and the second cell blocks350and360are refreshed simultaneously, and the word lines WL0to WL511of the first and the second cell blocks350and360are refreshed one at a time. In the diagram403, arrows R1and R2denote refresh directions.

When the word lines WL0to WL54have been sequentially refreshed and the word line WL55is to be refreshed in the first and second cell blocks350and360, the word line WL55of the second cell block360is properly refreshed. In contrast, the word line WL55and the redundancy word line RWL13of the first cell block350are bypassed. There is no influence on the operation of the memory device although the word line WL55of the first cell block350is not refreshed because it is not used as a defective word line. Since the redundancy word line RWL13is not refreshed, the second cell block360is prevented from simultaneously refreshing two word lines (i.e., the word line WL55and the redundancy word line RWL13). Thereafter, when the word lines WL511of the first and the second cell blocks350and360are refreshed, the first section terminates, and the second section starts.

Referring to the diagram404, in the second section, the redundancy word lines RWL0to RWL15are sequentially refreshed. In the diagram404, an arrow R denotes a refresh direction. In the second section, there is no concern that two word lines may be simultaneously refreshed in a single cell block because only the redundancy word lines are refreshed. In the second section, however, the refresh of a defective redundancy word line of the redundancy word lines RWL0to RWL15is bypassed. Thereafter, when the redundancy word line RWL15is refreshed, the second section terminates, and the first section starts.

In the memory device ofFIG. 3, a refresh section is divided into two sections, and word lines and redundancy word lines are refreshed in different sections. A repaired word line is skipped without being refreshed in a section for refreshing word lines. Instead, a redundancy word line replacing the repaired word line is refreshed in a section for refreshing redundancy word lines. Accordingly, two word lines being refreshed in a single cell block at the same time is prevented. A word line of one cell block may be repaired using a redundancy word line of any other cell block, thereby increasing utilization efficiency of redundancy word lines. Refresh operations may be quickly completed because all the cell blocks are refreshed simultaneously.

FIG. 5is a configuration diagram illustrating the control unit340ofFIG. 3.

Referring toFIG. 5, the control unit340may include an address counting unit510, first to sixteenth address storage units520_0to520_15, a refresh control unit530, and a word line control unit540.

When a refresh operation is performed, the address counting unit510may generate a counting address CA<0:9> by counting. The address counting unit510may increase the value of the counting address CA<0:9> by 1 by counting whenever the refresh pulse REFP is activated. That is, when a Kthword line has been selected, the counting address CA<0:9> is changed so that a (K+1)thword line is selected next.

The address counting unit510may deactivate a section signal SEC while counting the values of the counting addresses CA<0:9> as values (e.g., 0 to 511) corresponding to the word lines WL0to WL511of the first and the second cell blocks350and360and may activate the section signal SEC while counting the values of the counting addresses CA<0:9> as values (e.g., 512 to 527) corresponding to the redundancy word lines RWL0to RWL15of the first and the second cell blocks350and360. The section signal SEC indicates any one of the first and the second sections, and it may be deactivated in the first section and activated in the second section.

When the value of the counting address CA<0:9> reaches 527, the address counting unit510may activate a reset signal RESET and count the counting address CA<0:9> from 0 again. The address counting unit510may output only the counting addresses CA<0:8>.

The address storage units520_0to520_15may correspond to the respective redundancy word lines RWL0to RWL15. The address storage units520_0to520_15may store the addresses of word lines to be repaired (hereinafter referred to as repair addresses). The address storage units520_0to520_15may include a plurality of fuses5200to5215for storing the bits of multi-bit information. The address storage units520_0to520_15may output repair addresses F0<0:9> to F15<0:9> stored in the plurality of fuses5200to5215and enable signals EN0to EN15.

The fuses5200_9to5215_9may store block addresses F0<9> to F15<9> to select a cell block. The fuses5200_0˜5200_8to5215_0˜5215_8may store addresses F0<0:8> to F15<0:8> to designate a word line in a selected cell block. The enable signals EN0to EN15are deactivated in the initial state. When a memory device is fabricated, the enable signal of an address storage unit in which a repair address is stored is activated. In contrast, although the repair address is stored, the enable signal of a word line storage unit corresponding to a defective redundancy word line is deactivated.

For example, in the initial state, the enable signal EN0has been deactivated to “0.” If a repair address is stored in the address storage unit520_0in the process of fabricating a memory device, the enable signal EN0is activated to “1.” If a defect has occurred in the redundancy word line RWL0, the enable signal EN0is deactivated to “0.” If the address of the word line WL0of the second cell block360is to be stored in the address storage unit520_0, a block address (e.g., “1”) to designate the second cell block360may be stored in the fuse5200_9, and addresses (e.g., “000000000”) corresponding to the location of the word line WL0may be stored in the fuses5200_0to5200_8.

The refresh control unit530may control the refresh operation of the memory device. The refresh operation is divided into an auto-refresh operation and a self-refresh operation. The auto-refresh operation is performed by a command applied to a system including a memory device. The self-refresh operation is autonomously performed by a memory device when a system including the memory device does not operate for a specific time. The refresh command REF is a command that controls the auto-refresh operation, and the self-refresh start command SREF_EN and the self-refresh end command SREF_EX are commands that control the self-refresh operation.

The refresh control unit530may activate the refresh pulse REFP and a refresh signal REFS in response to the refresh command REF or periodically activate the refresh pulse REFP and the refresh signal REFS in a section defined by the self-refresh start and end commands SREF_EN and SREF_EX. The refresh pulse REFP and the refresh signal REFS are periodically activated from the time when the self-refresh start command SREF_EN is applied to the time when the self-refresh end command SREF_EX is applied. The refresh signal REFS may be activated in the section in which a refresh operation is performed.

The word line control unit540may activate a word line corresponding to the address ADD<0:9> when the active command ACT is activated. If the address ADD<0:9> is identical with one of the repair addresses F0<0:9> to F15<0:9>, the word line control unit540may activate a redundancy word line corresponding to the one of repair addresses F0<0:9> to F15<0:9> instead of the word line corresponding to the address ADD<0:9>. The word line control unit540may precharge an activated word line when the precharge command PRE is activated.

When the refresh signal REFS is activated in the first section (i.e., the section in which the section signal SEC is deactivated), the word line control unit540may refresh word lines corresponding to the counting address CA<0:8> in the first and the second cell blocks350and360simultaneously. If the counting address CA<0:8> is identical with one or more of the repair addresses F0<0:8> to F15<0:8>, the refreshes of word lines and redundancy word lines corresponding to the one or more of repair addresses F0<0:9> to F15<0:9> may be bypassed.

For reference, only counting addresses CA<0:8> of the counting addresses CA<0:9> are required to select word lines in the first section. The reason for this is that the number of word lines of the cell block is 512. Furthermore, only counting addresses CA<0:3> of the counting addresses CA<0:9> are required to select redundancy word lines in the second section. The reason for this is that the number of redundancy word lines is 16. If a counting address is identical with a repair address in the first section, it means that the counting address CA<0:8> is identical with one of the repair addresses F0<0:8> to F15<0:8>.

It is assumed that the value of the repair address F0<0:9> corresponds to the word line WL511of the second cell block360(e.g., F0<9>=“1”, and F0<0:8>=“111111111”). If the counting address CA<0:8> is “11111111”, the word lines WL511need to be refreshed in the first and the second cell blocks350and360. However, since the counting address CA<0:8> is identical with the repair address F0<0:8>, the refresh of the word line WL511of the second cell block360corresponding to the repair address F0<0:9> is bypassed, and only the word line WL511of the first cell block350is refreshed. Furthermore, the refresh of the redundancy word line RWL0corresponding to the repair address F0<0:9> is also bypassed.

When the refresh signal REFS is activated in the second section (i.e., the section in which the section signal SEC has been activated), the word line control unit540may refresh a redundancy word line corresponding to the counting address CA<0:3>. That is, the word line control unit540may sequentially refresh the redundancy word lines RWL0to RWL15. The word line control unit540may not simultaneously refresh the first and the second cell blocks350and360in the second section. In this case, the refresh of a redundancy word line corresponding to a deactivated enable signal among the redundancy word lines RWL0to RWL15may be bypassed.

FIG. 6is a configuration diagram illustrating the word line control unit540ofFIG. 5.

Referring toFIG. 6, the word line control unit540may include first to sixteenth comparison units610_0to610_15, first to sixteenth control signal generation units620_0to620_15, a first word line driving unit630, a second word line driving unit640, an address selection unit601, and first and second signal combination units602and603.

The address selection unit601may receive the address ADD<0:9> and the counting address CA<0:8>, may select one address, and may output the selected address (i.e., the input address SA<0:9> of the comparison units610_1to610_15). When the refresh signal REFS is deactivated, the address selection unit601may transfer the addresses ADD<0> to ADD<9> as the respective input addresses SA<0> to SA<9>. When the refresh signal REFS is activated, the address selection unit601may transfer the counting addresses CA<0> to CA<8> as the respective input addresses SA<0> to SA<8>.

The comparison units610_0to610_15correspond to the respective address storage units520_0to520_15. When the enable signals EN0to EN15is activated, the comparison units610_0to610_15may compare the input address SA<0:9> with the repair addresses F0<0:9> to F15<0:9> of the address storage units520_0to520_15. The comparison units610_0to610_15may generate first comparison signals CP1<0:15> and second comparison signals CP2<0:15>, respectively. The first comparison signals CP1<0> to CP1<15> may indicate the results of comparisons between the input address SA<0:8> and the repair addresses F0<0:8> to F15<0:8>. The second comparison signals CP2<0> to CP2<15> may indicate the results of comparisons between the input address SA<9> and the respective repair addresses F0<9> to F15<9>. The first comparison signal CP1<X> (X is an integer of 0<X515) may be activated if the input address SA<0:8> is identical with the repair address FX<0:8>. The second comparison CP2<X> may be activated if the input address SA<9> is identical with the repair address FX<9>.

The control signal generation units620_0to620_15may generate respective control signals HIT<0:15> and respective bypass signals BS1<0:15> and BS2<0:15> for controlling a corresponding redundancy word line based on the comparison results CP1<0:15> and CP2<0:15> of the respective comparison units610_0to610_15. The first bypass signals BS1<0> to BS1<15> may correspond to the first cell block350, and the second bypass signals BS2<0> to BS2<15> may correspond to the second cell block360.

When the refresh signal REFS is deactivated (i.e., the active precharge operation of a common word line), the control signal generation units620_0to620_15may activate the respective control signals HIT<0:15> when all of the respective comparison signals CP1<0:15> and CP2<0:15> are activated and may deactivate the control signals HIT<0:15> if not.

For example, when the refresh signal REFS is deactivated, the control signal generation unit620_0may activate the control signal HIT<0> if both the comparison signals CP1<0> and CP2<0> are activated and may deactivate the control signal HIT<0> if not.

When the refresh signal REFS are activated and the section signal SEC is deactivated (I.e., a refresh operation in the first section), the control signal generation units620_0to620_15may deactivate the respective control signals HIT<0:15>. Furthermore, the control signal generation units620_0to620_15may deactivate the respective bypass signals BS1<0:15> and BS2<0:15> when the respective comparison signals CP1<0:15> are deactivated and may activate a bypass signal corresponding to a cell block designated by the values of the repair addresses F0<9> to F15<9> when the respective comparison signals CP1<0:15> are activated.

For example, it is assumed that the repair address F0<0:9> has a value corresponding to the word line WL0of the first cell block350(e.g., F0<9>=“0”, and F0<0:8>=“000000000”). If the counting address CA<0:8> is “000000000”, the comparison signal CP1<0> is activated, and the control signal generation unit620_0may activate the bypass signal BS1<0> corresponding to the value of the repair address F0<9> so that the refresh of the first cell block350is bypassed.

When both the refresh signal REFS and the section signal SEC are activated (i.e., a refresh operation in the second section), the control signal generation units620_0to620_15may decode the counting address CA<0:3> and activate the control signal HIT<0:15> corresponding to the value of the counting address CA<0:3>. For example, in the second section, if the value of the counting address CA<0:3> is “0000”, the control signal generation unit620_0activates the control signal HIT<0>. In this case, if the enable signal EN0has been deactivated, the control signal generation unit620_0does not activate the control signal HIT<0> although the value of the counting address CA<0:3> is “0000.”

The first signal combination unit602may deactivate a signal NXE when one or more of the control signals HIT<0:15> are enabled and may activate the signal NXE when all of the control signals HIT<0:15> are deactivated.

The second signal combination unit603may activate a first bypass combination signal BS1when one or more of the bypass signals BS1<0> to BS1<15> are activated and may deactivate the first bypass combination signal BS1when all of the bypass signals BS1<0> to BS1<15> are deactivated. Furthermore, the second signal combination unit603may activate a second bypass combination signal BS2when one or more of the bypass signals BS2<0> to BS2<15> are activated and may deactivate the second bypass combination signal BS2when all of the bypass signals BS2<0> to BS2<15> are deactivated.

The first word line driving unit630may correspond to the first cell block350and control the word lines WL0to WL511and the redundancy word lines RWL0to RWL7of the first cell block350. If the active command ACT has been activated, the first word line driving unit630may activate a word line corresponding to the address ADD<0:9> when the signal NXE is activated and may activate a redundancy word line corresponding to a control signal that has been activated among the control signals HIT<0> to HTT<7> when the signal NXE is deactivated. When the precharge command PRE is activated, the first word line driving unit630may precharge an activated word line. If the refresh signal REFS has been activated, the first word line driving unit630may refresh a word line corresponding to the counting address CA<0:8> when the signal NXE is activated and may refresh a redundancy word line corresponding to a control signal that has been activated among the control signals HIT<0> to HTT<7> when the signal NXE is deactivated. In this case, although the signal NXE has been activated, the first word line driving unit630may not perform a refresh operation when the first bypass combination signal BS1is activated.

The second word line driving unit640may correspond to the second cell block360and control the word lines WL0to WL511and the redundancy word lines RWL8to RWL15of the second cell block360. If the active command ACT has been activated, the second word line driving unit640may activate a word line corresponding to the address ADD<0:9> when the signal NXE is activated and may activate a redundancy word line corresponding to a control signal that has been activated among the control signals HIT<8> to HTT<15> when the signal NXE is deactivated. When the precharge command PRE is activated, the second word line driving unit640may precharge an activated word line. If the refresh signal REFS has been activated, the second word line driving unit640may refresh a word line corresponding to the counting address CA<0:8> when the signal NXE is activated and may refresh a redundancy word line corresponding to a control signal that has been activated among the control signals HIT<8> to HTT<15> when the signal NXE is deactivated. In this case, although the signal NXE has been activated, the second word line driving unit640may not perform a refresh operation when the second bypass combination signal BS2is activated.

In the following descriptions ofFIGS. 7 to 10, it is described as an example that a memory device includes four cell blocks and each of the cell blocks includes 256 word lines and 4 redundancy word lines.

The number of cell blocks included in a memory device and the number of word lines and redundancy word lines included in each cell block may be changed depending on the circuit design of the memory device.

FIG. 7is a configuration diagram illustrating a memory device in accordance with an embodiment of the present invention.

Referring toFIG. 7, the memory device may include a command input unit710, an address input unit720, a command decoder730, a control unit740, and first to fourth cell blocks750_0to750_3.

Each of the first to fourth cell blocks750_0to750_3may include a plurality of word lines WL0to WL255. The first cell block750_0may include redundancy word lines RWL0to RWL3, and the second cell block750_1may include redundancy word lines RWL4to RWL7, and the third cell block750_2may include redundancy word lines RWL8to RWL11, and the fourth cell block750_3may include redundancy word lines RWL12to RWL15. The word lines WL0to WL255and the redundancy word lines RWL0to RWL15may be connected to memory cells MC.

The control unit740may control the word lines WL0to WL255of the cell blocks750_0to750_3in response to commands ACT, PRE, REF, SREF_EN, and SREF_EX. The control unit740may activate a selected word line in response to an input address ADD<0:9> when the active command ACT is activated and precharge the activated word line when the precharge command PRE is activated. When the refresh command REF is activated, the control unit740may refresh a selected word line (i.e., activate the selected word line for a specific time). Furthermore, the control unit740may periodically refresh a selected word line in the section from when the self-refresh start command SREF_EN is activated to when the self-refresh end command SREF_EX is activated.

The control unit740may activate a word line corresponding to the input address ADD<0:9> when the active command ACT is activated. The input address ADD<0:9> may include a block address ADD<8:9> for selecting one of the first to fourth cell blocks750_0and750_3and a row address ADD<0:7> for selecting one of the word lines WL0to WL255of the selected cell block. When the word line corresponding to the input address ADD<0:9> has been replaced by a redundancy word line, the control unit740may activate the redundancy word line.

The control unit740may refresh the first to fourth cell blocks750_0to750_3simultaneously in a first section. The control unit740may sequentially refresh the plurality of word lines WL0to WL255of the first to fourth cell blocks750_0to750_3. In the first section, the control unit740may bypass the refresh of a selected word line that has been substituted with a redundancy word line. That is, the control unit740skips a refresh operation on the selected word line and the substituted redundancy word line.

The control unit740may sequentially refresh the redundancy word lines RWL0to RWL15in a second section. The refresh of a defective redundancy word line of the redundancy word lines RWL0to RWL15may be bypassed. The second section may be a section in which a redundancy word line is refreshed. The first section and the second section may be alternately repeated.

FIGS. 8A and 8Bare diagrams illustrating the operation of the memory device ofFIG. 7.FIG. 8Ais a diagram illustrating the active operation of the memory device, andFIG. 8Bis a diagram illustrating the refresh operation of the memory device. Referring toFIGS. 8A and 8B, in order to describe an operation for activating or refreshing a word line in the memory device, the first to fourth cell blocks750_0to750_3and the word lines WL0to WL255and the redundancy word lines RWL0to RWL15have been illustrated.

A left-sided diagram801ofFIG. 8Aillustrates that a word line (e.g., the word line WL55of the first cell block750_0) corresponding to the input address ADD<0:9> in the memory device has not been repaired. A right-sided diagram802ofFIG. 8Aillustrates that a word line (e.g., the word line WL55of the first cell block750_0) corresponding to the input address ADD<0:9> in the memory device has been repaired (e.g., replaced by the redundancy word line RWL13).

Referring to the diagram801, when the active command ACT is applied and the word line WL55of the first cell block750_0is selected by the address ADD<0:9>, the word line WL55of the first cell block750_0is activated. Thereafter, when the precharge command PRE is activated, the word line WL55of the first cell block750_0is precharged.

Referring to the diagram802, when the active command ACT is applied and the word line WL55of the first cell block750_0is selected by the address ADD<0:9>, the redundancy word line RWL13is activated instead of the word line WL55of the first cell block750_0. When the precharge command PRE is activated, the redundancy word line RWL13is precharged.

AFIG. 803on the left ofFIG. 8Billustrates a refresh operation in the first section, and aFIG. 804on the right ofFIG. 8Billustrates a refresh operation in the second section. Likewise, as shown in the diagram802ofFIG. 8A, it is assumed that in the memory device, the word line WL55of the first cell block750_0has been replaced by the redundancy word line RWL13.

Referring to the diagram803, in the first section, the first to the second cell blocks750_0to750_3are refreshed one at a time. In the diagram803, arrows R1to R4denote refresh directions.

When the word lines WL0to WL54have been sequentially refreshed and the word line WL55is to be refreshed in the first to fourth cell blocks750_0to750_3, the word lines WL55of the second to fourth cell blocks750_1to750_3are properly refreshed. In contrast, the word line WL55of the first cell block750_0is not refreshed, and the redundancy word line RWL13that has replaced the word line WL55is not refreshed. Thereafter, when the word lines WL255of the first to fourth cell blocks750_0to750_3are refreshed, the first section terminates, and the second section starts. Referring to the diagram804, in the second section, the redundancy word lines RWL0to RWL15are sequentially refreshed. In the diagram804, an arrow R denotes a refresh direction. In this case, the refresh of a defective redundancy word line may be bypassed. When the redundancy word line RWL15is refreshed, the second section terminates, and the first section starts.

In the memory device ofFIG. 7, a refresh section is divided into two refresh sections, and a word line and a redundancy word line are refreshed in different sections. A repaired word line is skipped without being refreshed in a section for refreshing word lines. Instead, a redundancy word line replacing the repaired word line is refreshed in a section for refreshing redundancy word lines. Accordingly, two word lines being refreshed in one cell block at the same time is prevented. A word line of one cell block may be repaired using a redundancy word line of any other cell block, thereby increasing utilization efficiency of redundancy word lines. Refresh operations may be quickly completed because all the cell blocks are refreshed simultaneously.

FIG. 9is a configuration diagram illustrating the control unit740ofFIG. 7.

Referring toFIG. 9, the control unit740may include an address counting unit910, first to sixteenth address storage units920_0to920_15, a refresh control unit930, and a word line control unit940.

The address counting unit910may deactivate a section signal SEC while counting the values of counting addresses CA<0:8> as values (e.g., 0 to 255) corresponding to the word lines WL0to WL255of the first to fourth cell blocks750_0to750_3and may activate the section signal SEC while counting the values of the counting addresses CA<0:8> as values (e.g., 256 to 271) corresponding to the redundancy word lines RWL0to RWL15. When the value of the counting address CA<0:8> reaches 271, the address counting unit910may activate the reset signal RESET and count the counting address CA<0:8> from 0 again. The address counting unit910may output only the counting addresses CA<0:7>.

The address storage units920_0to920_15may correspond to the respective redundancy word lines RWL0to RWL15. The address storage units920_0to920_15may include a plurality of fuses9200to9215for storing multi-bit information.

The fuses9200_8˜9200_9to9215_8˜9215_9may store bits F0<8:9> to F15<8:9> that designate a cell block in repair addresses. The fuses9200_0˜9200_7to9215_0˜9215_7may store bits F0<0:7> to F15<0:7> that designate a word line within a cell block in repair addresses. If block addresses F<8:9> are “00”, “10”, “01”, and “11”, they may correspond to the first to fourth cell blocks750_0to750_3.

When a refresh signal REFS is activated in the first section (i.e., the section in which the section signal SEC has been deactivated), the word line control unit940may refresh word lines that correspond to the counting address CA<0:7> in the first to fourth cell blocks750_0to750_3simultaneously. In this case, if the counting address CA<0:7> is identical with one or more of repair addresses F0<0:7> to F15<0:7>, the refresh of word lines and redundancy word lines corresponding to the one or more of repair addresses F0<0:9> to F15<0:9> may be bypassed.

When the refresh signal REFS is activated in the second section (i.e., the section in which the section signal SEC has been activated), the word line control unit940may refresh a redundancy word line corresponding to the counting addresses CA<0:3>. In this case, the refresh of a defective redundancy word line of the redundancy word lines RWL0to RWL15may be bypassed. That is, in the second section, the word line control unit940may not refresh the first to fourth cell blocks750_0to750_3, but may sequentially refresh the redundancy word lines RWL0to RWL15.

FIG. 10is a configuration diagram illustrating the word line control unit940ofFIG. 9.

Referring toFIG. 10, the word line control unit940may include first to sixteenth comparison units1010_0to1010_15, first to sixteenth control signal generation units1020_0to1020_15, first to fourth word line driving units1030_0to1030_3, an address selection unit1001, and first and second signal combination units1002and1003.

The address selection unit1001may receive an address ADD<0:9> and a counting address CA<0:7>, may select one address, and may output the selected address (i.e., it becomes the input address SA<0:9> of the comparison units1010_1to1010_15). When the refresh signal REFS is deactivated, the address selection unit1001may transfer the addresses ADD<0> to ADD<9> as respective input addresses SA<0> to SA<9>. When the refresh signal REFS is activated, the address selection unit1001may transfer the counting addresses CA<0> to CA<7> as the input addresses SA<0> to SA<7>.

If respective enable signals EN0to EN15have been activated, the comparison units1010_0to1010_15may compare the input address SA<0:9> with the respective repair addresses F0<0:9> to F15<0:9> of the respective address storage units920_0to920_15and generate respective comparison signals CP1<0:15> and respective comparison signals CP2<0:15>. The first comparison signals CP1<0> to CP1<15> may indicate the results of comparisons between the input address SA<0:7> and the respective repair addresses F0<0:7> to F15<0:7>, and the second comparison signals CP2<0> to CP2<15> may indicate the results of comparisons between the input address SA<8:9> and the respective repair addresses F0<8:9> to F15<8:9>. The first comparison signal CP1<X> (X is an integer of 0≦X≦15) may be activated when the input address SA<0:7> is identical with the repair address FX<0:7>. The second comparison signal CP2<X> may be activated when the input address SA<8:9> is identical with the repair address FX<8:9>.

The control signal generation units1020_0to1020_15may generate control signals HIT<0:15> and bypass signals BS1<0:15> to BS4<0:15>, for controlling a redundancy word line based on the comparison results CP1<0:15> and CP2<0:15> of the comparison units1010_0to1010_15. The first to fourth bypass signals BS1<0:15> to BS4<0:15> may correspond to the first to fourth cell blocks750_0to750_3.

When the refresh signal REFS is deactivated, the control signal generation units1020_0to1020_15may activate the respective control signals HIT<0:15> when all of the corresponding comparison signals CP1<0:15> and CP2<0:15> are activated and may deactivate the control signals HIT<0:15> if not.

When the refresh signal REFS is activated and the section signal SEC is deactivated, the control signal generation units1020_0to1020_15may deactivate the respective control signals HIT<0:15>. Furthermore, the control signal generation units1020_0to1020_15may deactivate the bypass signals BS1<0:15> to BS4<0:15> if a corresponding comparison signal CP1<0:15> has been deactivated and may activate a bypass signal corresponding to a cell block designated by the values of the repair addresses F0<8:9> to F15<8:9> if a corresponding comparison signal CP1<0:15> has been activated.

For example, it is assumed that the repair address F0<0:9> has a value corresponding to the word line WL0of the first cell block750_0(e.g., F<8:9>=“00”, and F<0:7>=“000000000”). If the counting address CA<0:7> is “00000000”, the comparison signal CP1<0> is activated. The control signal generation unit1020_0may activate the bypass signal BS1<0> corresponding to the value of the repair signal F0<8:9> so that the refresh of the first cell block750_0is bypassed.

When both the refresh signal REFS and the section signal SEC are activated, the control signal generation units1020_0to1020_15may decode the counting address CA<0:3> and activate the control signal HIT<0:15> corresponding to the value of the decoded counting address CA<0:3>. In this case, if the enable signal has been deactivated, a control signal corresponding to the value of the counting address CA<0:3> is not activated.

When one or more of the bypass signals BS1<0> to BS1<15> are activated, the second signal combination unit1003may activate the first bypass combination signal BS1. When one or more of the bypass signals BS2<0> to BS2<15> are activated, the second signal combination unit1003may activate the second bypass combination signal BS2. When one or more of the bypass signals BS3<0> to BS3<15> are activated, the second signal combination unit1003may activate the third bypass combination signal BS3. When one or more of the bypass signals BS4<0> to BS4<15> are activated, the second signal combination unit1003may activate the fourth bypass combination signal BS4.

The operations of the first to the fourth word line driving units1030_0to1030_3are similar to those of the word line driving units630and640ofFIG. 6except for the number of word lines controlled and the number of redundancy word lines controlled.

In the above description, repairing a word line may mean that a redundancy word line is used instead of the word line by substituting the word line.

The memory device of this technology may improve utilization efficiency of redundancy word lines by repairing a word line of one cell block using a redundancy word line of another cell block.

Furthermore, the memory device of this technology may refresh the word lines of a plurality of cell blocks by refreshing all the word lines and then refreshing redundancy word lines although a word line of a cell block has been substituted with a redundancy word line of another cell block.