Semiconductor device and dicing method

According to an embodiment, a semiconductor device includes a silicon substrate, a device layer, and a lower layer. The device layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2018-033567, filed on Feb. 27, 2018, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor device and dicing method.

BACKGROUND

Power devices formed on a silicon substrate undergo dicing after a pre-process, and the power device is packaged with its rear surface being connected using solder, eutectic metal or metal, or conductive resin or nonconductive resin. The metal or the like on the rear surface plays a role of electric connection, barrier metal for a connection material, a connection material, heat dissipation, or the like. Peeling of the metal or the like on the rear surface leads to an open failure to deteriorate electric properties. Further, a large crack in the metal or the like on the rear surface becomes a chip crack (fissure-shaped damage in a chip) when the metal or the like undergoes heat cycle, drop impact, mounting impact, or the like, and may lead to defective properties. In a case where a die attach film of nonconductive resin is used, the peeling of the rear surface or the presence of a large crack in the rear surface lowers the stability of die bonding. Therefore, avoiding a defect of the metal or the like on the rear surface caused by the cutting is an important thing leading to an improvement in reliability.

DETAILED DESCRIPTION

According to an embodiment, a semiconductor device includes a silicon substrate, device layer, and a lower layer. The device layer is formed on an upper surface of the silicon substrate. The lower layer is formed on a lower surface of the silicon substrate and has a side surface connecting to a side surface of the silicon substrate. At least a pair of side surfaces of the semiconductor device has a curved shape widening from an upper side toward a lower side.

An embodiment of the present invention will be hereinafter described with reference to the drawings. This embodiment does not limit the present invention. Note that, though the description in this embodiment uses up and down relations such as an upper side, a lower side, an upper surface, and a lower surface, these up and down relations are determined for convenience' sake and do not necessarily indicate up and down relations in terms of the gravitational direction during the manufacture, during the use, and so on. Further, the expression “having a curvature” does not necessarily mean that a portion in question constitutes part of the circumference, but is used to mean that a portion in question has a curved shape.

Further, “vertical” does not necessarily mean strictly vertical, and for example, may include “substantially vertical” like the side surface of the semiconductor device1illustrated inFIG. 4.

The semiconductor device according to this embodiment has a device layer, a metal layer, and so on formed in its front surface by a semiconductor pre-process. After the completion of the pre-process, a rear surface of a silicon substrate is thinned using a back grinder, and by subsequent chemical polishing of the rear surface, fractured surfaces and/or adherent matter caused by the back grinding are removed, and thereafter rear metal is formed using a sputtering device, and the resultant is blade-diced into chips. Thereafter, the chip is encapsulated in a package using a die bonder.

FIG. 1AtoFIG. 1Eare views illustrating the states of the semiconductor device according to this embodiment up to the dicing. The semiconductor device uses a semiconductor substrate10illustrated inFIG. 1A, and the semiconductor device is formed on the silicon substrate10.

First, as illustrated inFIG. 1B, by the pre-process, the device layer12including various semiconductor films, insulating films, metal interconnecting wires, and so on is formed on an upper surface10aof the silicon substrate10. In forming the device layer12, processing steps of the pre-process, such as, for example, cleaning, deposition, semiconductor film formation, insulating film formation, photolithography, etching, impurity doping, and activation are performed in a predetermined order. In the formed device layer12, its upper surface12aserves as a front surface and its lower surface12bfaces the upper surface10aof the silicon substrate10.

Next, as illustrated inFIG. 1C, the back grinding is applied to a surface of the silicon substrate10opposite to the upper surface10a, that is, a surface opposite to the surface on which the device layer12is formed, to adjust the thickness of the silicon substrate10. This process is not limited to the back grinding, but may be other physical thinning such as grinding, polishing, CMP (Chemical Mechanical Polishing), chemical etching, or sand blasting.

Thereafter, the lower surface10bof the silicon substrate10is further lightly etched using a HF (hydrogen fluoride)-based chemical. The etching used is not limited to the etching using a chemical solution, but may be dry etching using gas. Alternatively, the light etching may be replaced by a step of removing only a necessary amount of a fractured surface of the rear surface by grinding or polishing.

Next, as illustrated inFIG. 1D, a metal layer14is formed as a lower layer on the lower surface10bof the silicon substrate10by sputtering. In the formed metal layer14, its upper surface14afaces the lower surface10bof the silicon substrate10. A method for forming the metal layer14is not limited to the sputtering, but may be vapor deposition, plating, or chemical or physical formation processing.

The metal may be formed by, for example, depositing Ti (titanium) and thereafter forming a Ni (nickel) film and an Au (gold) film so as to cover Ti. The metal of the metal layer14is not limited to Ti, but may be any metal as long as it can be the rear metal, and another example of the metal layer14is a metal film containing at least one of Ti, Cu (copper), Zn (zinc), Pd (palladium), Ni, Ag (silver), and Au.

Next, as illustrated inFIG. 1E, the resultant is transferred onto a dicing tape16and is cut into chips using a blade dicer. The dicing tape16is set with its upper surface16afacing a lower surface14bof the metal layer14, and cut regions20are formed using a dicing blade. The cut regions20are formed from the upper surface12aof the device layer12so as to reach at least the dicing tape16.

FIG. 2is a view illustrating a relation between the dicing blade30and the board to be cut. As illustrated inFIG. 2andFIG. 3B(to be described later), the dicing blade30is set so as to dice the device layer12, the silicon substrate10, and the metal layer14, for example, with part of the dicing tape16being cut to such a degree that an upper surface of the dicing tape16is superficially cut, and the dicing blade30dices the whole board.

As the dicing blade30, one having a blade portion32suitable both for cutting metal and for cutting silicon is used. In the dicing, the blade portion32cuts the metal layer14and the silicon. As described above, in this cutting, the upper surface16aof the dicing tape16is also superficially cut.

FIG. 3AandFIG. 3Bare views illustrating the states of the board and the dicing blade30at a dicing instant.FIG. 3AandFIG. 3Bare views seen in the direction A and the direction B indicated inFIG. 2respectively, that is, views illustrating the states seen in a direction perpendicular to the dicing blade30and in a direction parallel to the dicing blade30respectively.

As illustrated inFIG. 3A, the blade portion32of the dicing blade30has a length large enough to cut at least the metal layer14, the device layer12, and the silicon substrate10, and superficially cut the upper surface16aof the dicing tape16. The blade portion32cuts the device layer12, the silicon substrate10, the metal layer14, and the upper surface16aof the dicing tape16together. The width of the dicing blade30in this embodiment is 15 to 50 μm at its thick portion, but at least its portion cutting the metal layer14has a curvature at its edge and thus this portion is thinner than the thick root portion of the dicing blade30. Further, the width of a dicing curve in the metal layer14differs depending on the depth of cut.

FIG. 3Bis a view illustrating a cross section of the dicing blade30seen in the direction B. Incidentally, the dicing blade30is not hatched inFIG. 3Bbecause a material of the dicing blade30is not limited.

A side surface of the blade portion32of the dicing blade30has such a curvature as to depict a curve from the middle of the height of the silicon substrate10. This curvature is smooth as illustrated inFIG. 3B.

In the dicing blade30, the blade portion32has diamond particles selected so as to be suitable both for cutting the metal and for cutting the silicon substrate10, for instance.

As another example, instead of the dicing blade30being used so as to reach the middle of the dicing tape16as in the typical method, by adjusting the height of the dicing blade30so that up to the lower surface14bof the metal layer14is cut and the vicinity of the upper surface of the dicing tape16is cut by the edge of the blade portion32, it is possible for the lower portion of the semiconductor device1to have a curvature as illustrated inFIG. 1Eas a result of the cutting. That is, the blade portion32of the dicing blade30may be controlled to be located at a position that is higher and further shallower than the position illustrated inFIG. 3Aso that the metal layer14is cut.

As described above, in this embodiment, the dicing may be single-cut dicing that achieves the cutting up to the metal layer14and the transfer of the curvature that the side surface of the blade portion32has to the curvature of the side surface of the semiconductor device1.

FIG. 4is a view illustrating a cross section of the semiconductor device1according to this embodiment. In the semiconductor device1, the metal layer14, the silicon substrate10, and the device layer12are formed in stack. In a side surface of the semiconductor device1, a side surface20bin the silicon substrate10has a curvature from the middle and connects to a side surface20aof the metal layer14while maintaining the curvature. In other words, the side surface of the semiconductor device1has a curvature in such a manner that the area of the semiconductor device1in a plane view increases from an upper side toward a lower side of the side surface of the silicon substrate10and the side surface further widens toward a lower side of the metal layer14in contact with the lower surface10bof the silicon substrate10. Because of an individual difference, the side surface of the blade portion32of the dicing blade30is not exactly a flat surface, and accordingly, the whole side surface20bmay have a gentle curvature in conformity with the shape of the blade portion32, instead of being strictly separated into a flat portion and a portion having the curvature.

The semiconductor device1inFIG. 4is one chip taken out from the board illustrated inFIG. 1E, with the dicing tape16being removed from the lower surface14bof the metal layer14. In this state, the chip is die-bonding and thereafter goes through steps of wire bonding, molding, and so on, to be formed into a semiconductor package.

In the formed semiconductor device1, the length of the lower surface14bof the metal layer14is longer than the length of the upper surface12aof the device layer12in the sectional view. Three-dimensionally speaking, for example, the chip is rectangular and is formed so as to have a larger area in the lower surface14bof the metal layer14than in the upper surface12aof the device layer12. Further, in the formed semiconductor device1, the length of each side of the lower surface14bof the metal layer14is longer than the length of a corresponding side of the upper surface12aof the device layer12.

Thus making the lower surface larger in area than the upper surface makes it possible to keep a sufficient distance between chip front surfaces (that is, the upper surfaces12a) in such a case where they are transported in a side-by-side arrangement after the dicing, to thereby reduce a possibility of the mutual contact of the front surfaces of the chips. Accordingly, the chips are unlikely to get chipped or surface chipping is unlikely to occur, due to the collision of the chips, leading to a quality improvement of the chips. As a result, it is possible to reduce a bonding failure or to prevent a decrease in flexural strength.

What chipping means here is that a surface is superficially cracked, has a fissure, or gets chipped. The chipping deteriorates the performance of the semiconductor device1when it is transported, processed, or used.

FIG. 5illustrates a state where the semiconductor device1is die-bonding on a support substrate40. For example, the metal layer14is bonded on the support substrate40using solder42. Owing to the curvature that the side surface of the semiconductor device1has, a contact surface between the solder42and the metal layer14is larger than in a case where the side surface is vertical. This as a result can improve die shear strength, that is, can improve die bondability. This is true not only in the bonding by the solder42but also in the bonding by die bonding resin.

Further, owing to the presence of the curvature as illustrated inFIG. 5, the connection area between the solder42and the metal layer14at the time of the bonding by the solder42is larger than in the case where the side surface of the metal layer14is vertical. This increases the distance of the side surface up to the front surface of the semiconductor device1, making it possible to prevent the metal layer14and the device layer12from being short-circuited on the side surface, prevent the metal layer14and the front surface of the device layer12from being short-circuited, and prevent the interconnecting wires in the device layer12in the front surface and the solder used for the bonding from being short-circuited. For the same reason, it is possible to reduce a leakage current from the side surface of the semiconductor device1through the solder42.

However, if a length by which the lower surface14bof the metal layer14is longer than the upper surface12aof the device layer12is over about 25% of the thickness of the semiconductor device1, the area necessary as the chip becomes large and the curvature of the side surface becomes gentle, and moreover, the dicing blade30comes to have an unusual shape, which is not preferable. More preferably, the length by which the lower surface14bof the metal layer14protrudes from the upper surface12aof the device layer12is desirably about 5% to about 25% of the thickness of the semiconductor device1.

As described above, according to this embodiment, the semiconductor device1has a shape whose side surface has the curvature from the upper surface toward the lower surface and which has a larger area in the lower surface than in the upper surface, making it possible to improve the die-bonding strength while reducing the leakage current. Further, since the distance to the front surface is long, a short circuit on the side surface is unlikely to occur. Preventing the short circuit between the metal layer14and the side surface also makes it possible to prevent the short circuit between the metal layer14and the front surface such as a wiring layer of the semiconductor device1and the short circuit between the side surface and the front surface of the semiconductor device1. In addition, since it is possible to keep the distance between the chip front surfaces long, the collision of the chips is unlikely to occur during the transport after the dicing, making it possible to improve the qualities of the chips.

In many cases, typically, silicon and metal are separately cut, but in this embodiment, one dicing blade is used for the cutting. This as a result can increase the throughput in the dicing step. Dual cutting enables a further increase in this throughput.

Incidentally, in the above, the lower layer of the semiconductor device1is the metal layer14, but may be a die attach film. The die attach film may be a conductive die attach film, for instance. Forming the semiconductor device1using the die attach film enables stacking without processing the semiconductor device1when the semiconductor package is manufactured by the stacking.

MODIFICATION EXAMPLES

In the above-described embodiment, the dicing is the single-cut dicing, but is not limited to this and may be step-cut dicing

Specifically, in this modification example, a dicing blade for cutting the silicon substrate10and a dicing blade for cutting the metal layer14are separately prepared, and these layers are cut using the dicing blades more suitable for the respective layers. That is, the silicon substrate10may be cut by a blade portion32of a dicing blade30for cutting silicon, and the metal layer14may be cut by a blade portion32of a dicing blade30for cutting metal.

FIG. 6is a view illustrating a semiconductor device1formed by the step cutting. To form the semiconductor device1according to this modification example, first cutting is first performed to the board having undergone the pre-process, up to such a depth as to penetrate through the lower surface10bof the silicon substrate10using a first dicing blade for cutting silicon. The first cutting may reach the upper surface14aof the metal layer14, but does not completely cut the metal layer14because its purpose is not to cut the metal layer14.

After the first cutting is finished, second cutting is performed to the metal layer14exposed to a first cut surface, using a second dicing blade narrower in blade width than the first dicing blade, so as to cut up to the lower surface14bof the metal layer14. The second cutting may superficially cut the upper surface16aof the dicing tape16as in the above-described embodiment.

In the first cutting, the cutting is performed so as to cause a side surface20cto have a curvature as in the semiconductor device1according to the above-described embodiment. This is because up to the silicon substrate10is cut into the same sectional shape as that of the dicing blade. In the subsequent second cutting, the metal layer14is cut vertically. Alternatively, in this modification example as well, the cutting is performed so as to cause an exposed side surface20dto have a cross section having a curvature as in the above-described embodiment, as illustrated inFIG. 4orFIG. 7.

FIG. 7is a view illustrating a semiconductor device1according to a modification example ofFIG. 6. The cross section illustrated inFIG. 7is formed by adjusting the height of the dicing blade so that the cutting is performed up to the lower surface14bof the metal layer14as described in the above-described embodiment when the metal layer14is cut. As described above, the height may be adjusted so that the dicing tape16is cut up to its middle, that is, the upper surface16aof the dicing tape16is superficially cut.

FIG. 8is a view illustrating a semiconductor device1according to another example of this embodiment. As illustrated inFIG. 8, the substantially vertical portion may extend to a lower side of the silicon substrate10. In such a case as well, the same effects as those inFIG. 6and so on can be obtained.

FIG. 9is a view illustrating a semiconductor device1according to still another example of this embodiment. As illustrated inFIG. 9, when the silicon substrate10is cut, an upper layer portion of the metal layer14may also be cut.

As described above, according to these modification examples, owing to the curvature that the side surface20chas, the lower surface14bis larger in area than the upper surface12a, and in a case where the chip shape, that is, the shape of the semiconductor device1is rectangular, the length of each side of the lower surface14bis longer than the length of the corresponding side of the upper surface12a, as in the semiconductor device1according to the above-described embodiment. This difference in length makes it possible to reduce the collision of the upper surfaces12of the semiconductor devices1. The step cutting permits the selection of the blades for metal and for silicon, leading to a further quality improvement, compared with the aforesaid single cutting.

Specifically, since the blades for cutting the silicon substrate10and for cutting the metal layer14are different, the chipping of the front surface and the side surface of the silicon substrate10and the rear chipping in the lower surface14bof the metal layer14are prevented in the dicing step, leading to an improvement in deflective strength and making it possible to improve a yield of the chips. Further, even if a crack such as a fissure occurs in the lower portion of the silicon substrate10, since the lower surface10bof the silicon substrate10suffering the chipping physically connects to the upper surface14aof the metal layer14and the portion suffering the chipping is fixed to the metal layer14on at least its lower surface, the portion suffering the chipping does not easily peel off, making it possible to prevent the generation of dust in a post-process.

Further, in the case where the side surface20dis vertical, in the side surface20d, an effect on a bonding agent such as the solder or the die bonding resin is the same as the conventional effect, but owing to the curvature that the side surface20chas, a force pressing a side of the side surface20cfrom above is applied from the bonding agent as in the above-described embodiment, making it possible to obtain the same effects. In a case where the bonding agent is a conductive bonding agent such as solder, it is also possible to further reduce the leakage of a current in the side surface or the front surface as in the above-described embodiment

For example, in cutting out the semiconductor device1as a chip, the board is cut in directions intersecting with each other, and the cutting in one of the directions may be the single cutting, and the cutting in the other direction may be the step cutting. The cutting in the both directions may of course be the single cutting or the step cutting. Further, out of the two pairs of opposed side surfaces, only one pair of the side surfaces may have a curvature as described above.

Further, the silicon substrate10of the semiconductor device1may be replaced by a different substrate. For example, when the substrate is a substrate using gallium nitride (GaN), silicon carbide (SiC), or the like, the dicing method according to the above-described embodiment can also bring about the same effects as are obtained in the above-described semiconductor device1.

Further, the semiconductor device1may be formed such that its side surface has a curvature from the middle of the metal layer14as illustrated inFIG. 10. The position of the curve in the silicon substrate10and the metal layer14may be thus varied depending on the thickness of the metal layer14.

The shape of the above-described semiconductor device1can be found through the observation of the cross section of the chip or the observation of its side surface using a microscope or the like, for instance.