SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A manufacturing method of a semiconductor device includes forming an oxide semiconductor layer on an insulating layer, a part of the insulating layer being exposed from the oxide semiconductor layer, performing a plasma process by use of chlorine-containing gas on the part of the insulating layer exposed from the oxide semiconductor layer, and removing chlorine impurities from a surface layer of the exposed part of the insulating layer. The chlorine impurities may be removed by a first etching process performed by use of fluorine-containing gas. The fluorine-containing gas may contain CF4 and CHF3. The plasma process may be a second etching process performed by use of chlorine-containing gas.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2015-138011 filed on Jul. 9, 2015, the entire contents of which are incorporated herein by reference.

FIELD

The present invention relates to a semiconductor device and a manufacturing method of the semiconductor device.

Recently, a driving circuit of a display device, a personal computer or the like includes a semiconductor device such as a transistor, a diode or the like as a microscopic switching element. Especially in a display device, a semiconductor device is used as a selective transistor that supplies a voltage or a current in accordance with the gray scale of each of pixels and also used in a driving circuit that selects a pixel to which the voltage or the current is to be supplied. The characteristics required of a semiconductor device vary in accordance with the use thereof. For example, a semiconductor device used as a selective transistor is required to have a low off-current or little variance in characteristics from another selective semiconductor. A semiconductor device used in a driving circuit is required to have a high on-current.

To be used in a display device as described above, a semiconductor device including a channel formed of amorphous silicon, low-temperature polysilicon or single crystalline silicon has been conventionally developed. The semiconductor device including a channel formed of amorphous silicon or low-temperature polysilicon is formed in a process of 600° C. or lower, and therefore can be formed by use of a glass substrate. Especially, a semiconductor device including a channel formed of amorphous silicon can be formed with a simpler structure and in a process of 400° C. or lower, and therefore can be formed, for example, by use of a large glass substrate referred to as an eighth-generation glass substrate (2160×2460 mm). However, such a semiconductor device including a channel formed of amorphous silicon has a low mobility and is not usable in a driving circuit.

A semiconductor device including a channel formed of low-temperature polysilicon or single crystalline silicon has a higher mobility than the semiconductor device including a channel formed of amorphous silicon, and therefore is usable as a selective transistor and also in a driving circuit. However, such a semiconductor device including a channel formed of low-temperature polysilicon or single crystalline silicon has a complicated structure and needs a complicated process to be manufactured. In addition, such a semiconductor device needs to be formed in a process of 500° C. or higher, and therefore cannot be formed by use of a large glass substrate as described above. A semiconductor device including a channel formed of amorphous silicon, low-temperature polysilicon or single crystalline silicon has a high off-current. In the case where such a semiconductor device is used as a selective transistor, it is difficult to keep the applied voltage for a long time.

For the above-described reasons, a semiconductor device including a channel formed of an oxide semiconductor, instead of amorphous silicon, low-temperature polysilicon or single crystalline silicon, has been progressively developed recently (e.g., Japanese Laid-Open Patent Publication No. 2010-062229). It is known that a semiconductor device including a channel formed of an oxide semiconductor can be formed with a simple structure and in a low-temperature process like a semiconductor device including a channel formed of amorphous silicon, and has a mobility higher than that of a semiconductor device including a channel formed of amorphous silicon. It is also known that such a semiconductor device including a channel formed of an oxide semiconductor has a very low off-current.

However, an oxide semiconductor is known to have a low tolerance against acid and to be etched when contacting an acidic aqueous solution. In the semiconductor device including a channel formed of an oxide semiconductor that is disclosed in Japanese Laid-Open Patent Publication No. 2010-062229, a conductive layer that is to be formed into a gate electrode, and source and drain electrodes is dry-etched with chlorine-containing gas. As a result of the dry etching, a chlorine-containing etching product is generated. When the chlorine-containing etching product is reacted with water, hydrochloric acid is generated. Hydrochloric acid etches the oxide semiconductor. In the case where the oxide semiconductor used for the channel is etched, characteristics desired for the semiconductor device are not provided. Even in the case where the oxide semiconductor is etched slightly and initial characteristics of the semiconductor device are not abnormal, the reliability of the semiconductor device may be lowered; for example, the characteristics may be fluctuated when the semiconductor device is irradiated with light.

SUMMARY

A manufacturing method of a semiconductor device in an embodiment according to the present invention includes forming an oxide semiconductor layer on an insulating layer, a part of the insulating layer being exposed from the oxide semiconductor layer, performing a plasma process by use of chlorine-containing gas on the part of the insulating layer exposed from the oxide semiconductor layer, and removing chlorine impurities from a surface layer of the exposed part of the insulating layer.

A manufacturing method of a semiconductor device in an embodiment according to the present invention includes performing a plasma process by use of chlorine-containing gas on a part of an insulating layer, the part of the insulating layer being exposed, removing chlorine impurities from a surface layer of the part of the insulating layer, and forming an oxide semiconductor layer on the part of the insulating layer.

A semiconductor device in an embodiment according to the present invention includes a gate electrode, a gate insulating layer on the gate electrode, an oxide semiconductor layer facing the gate electrode with the gate insulating layer being therebetween, and source and drain electrodes on the oxide semiconductor layer, the source and drain electrodes being connected with the oxide semiconductor layer. A part of the gate insulating layer exposed from the oxide semiconductor layer and the source and drain electrodes has a thickness smaller than that of a part of the gate insulating layer below the oxide semiconductor layer and a part of the gate insulating layer below the source and drain electrodes.

A semiconductor device in an embodiment according to the present invention includes an underlying layer, source and drain electrodes on the underlying layer, an oxide semiconductor layer on a part of the underlying layer exposed from the source and drain electrodes, the oxide semiconductor layer being connected with the source and drain electrodes, a gate insulating layer on the oxide semiconductor layer, and a gate electrode facing the oxide semiconductor layer with the gate insulating layer being therebetween. A part of the underlying layer below the oxide semiconductor layer has a thickness smaller than that of a part of the underlying layer below the source and drain electrodes.

DESCRIPTION OF EMBODIMENTS

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The disclosure is merely exemplary, and alternations and modifications readily conceivable by a person of ordinary skill in the art without departing from the gist of the present invention are duly encompassed in the scope of the present invention. In the drawings, components may be shown schematically regarding the width, thickness, shape and the like, instead of being shown in accordance with the actual sizes, for the sake of clear illustration. The drawings are merely exemplary and do not limit the interpretations of the present invention in any way. In the specification and the drawings, components that are substantially the same as those shown in a previous drawing(s) bear the identical reference signs thereto, and detailed descriptions thereof may be omitted. The following embodiments are presented for the purpose of providing a highly reliable semiconductor device and a manufacturing method of such a semiconductor device.

In the following description of the embodiments, the expression that “a first member and a second member are connected with each other” indicates that at least the first member and the second member are electrically connected with each other. Namely, the first member and the second member may be physically connected with each other directly, or another member may be provided between the first member and the second member.

With reference toFIG. 1throughFIG. 3, an overview of a semiconductor device10in embodiment 1 according to the present invention will be described. The semiconductor device10in embodiment 1 is usable in a pixel or a driving circuit of a liquid crystal display device (LCD), a spontaneous emission display device using an organic light-emitting diode (OLED) such as an organic EL element, a quantum dot or the like for a display unit, or a reflection-type display device such as an electronic paper or the like.

It should be noted that a semiconductor device according to the present invention is not limited to being used in a display device, and may be used in, for example, an integrated circuit (IC) such as a microprocessing unit (MPU) or the like. The semiconductor device10in embodiment 1 has a structure including a channel formed of an oxide semiconductor. In embodiment 1, the semiconductor device10is a transistor. This does not limit the semiconductor device according to the present invention to being a transistor.

[Structure of the Semiconductor Device10]

FIG. 1is a plan view showing an overview of the semiconductor device10in embodiment 1 according to the present invention.FIG. 2is a cross-sectional view showing an overview of the semiconductor device10in embodiment 1 according to the present invention, taken along line A-A′ inFIG. 1,FIG. 3is a cross-sectional view showing an overview of the semiconductor device10in embodiment 1 according to the present invention, taken along line B-B′ inFIG. 1. As shown inFIG. 1throughFIG. 3, the semiconductor device10includes a substrate100, an underlying layer110, a gate electrode120, a gate insulating layer130, an oxide semiconductor layer140, source and drain electrodes150, and a protective layer160. The semiconductor device10is a bottom gate-type transistor.

The underlying layer110is located on the substrate100. The gate electrode120is located on the underlying layer110. The gate insulating layer130is located on the gate electrode120and the underlying layer110. The oxide semiconductor layer140is located to face the gate electrode120with the gate insulating layer130being provided therebetween. As shown inFIG. 1, as seen in a plan view, the oxide semiconductor layer140is located inner to the gate electrode120.

As shown inFIG. 3, a gate insulating layer130-1has a smaller thickness than that of a gate insulating layer130-2. The gate insulating layer130-1is located in an area where neither the oxide semiconductor layer140nor the source and drain electrodes150are located, namely, an area exposed from the oxide semiconductor layer140and the source and drain electrodes150. The gate insulating layer130-2is located below the oxide semiconductor layer140. As shown inFIG. 2, a gate insulating layer130-3has the same thickness as that of a gate insulating layer130-4. The gate insulating layer130-3is located below the oxide semiconductor layer140. The gate insulating layer130-4is located below the source and drain electrodes150.

As shown inFIG. 2, the source and drain electrodes150are located on the oxide semiconductor layer140and a part of the gate insulating layer130where the oxide semiconductor layer140is not located. The source and drain electrodes150are connected with the oxide semiconductor layer140. The source and drain electrodes150include a pair of electrodes separated from each other with a distance. In accordance with the applied voltage, one of the pair of electrodes is the source electrode, and the other electrode is the drain electrode. The distance between the pair of electrodes corresponds to a channel length of the semiconductor device10. A part of the oxide semiconductor layer140that is located between the pair of electrodes has a thickness smaller than that of a part of the oxide semiconductor layer140that is below the source and drain electrodes150.

The protective layer160covers the gate insulating layer130, the oxide semiconductor layer140, and the source and drain electrodes150.

The substrate100may be formed of a glass substrate. Alternatively, the substrate100may be formed of a light-transmissive insulating material such as quartz, sapphire, a resin or the like. In the case where the semiconductor device10is used in an integrated circuit, not in a display device, the substrate100may be formed of a non-light-transmissive material, for example, a semiconductor such as silicon, silicon carbide, a compound semiconductor or the like, or a conductive material such as stainless steel or the like.

The underlying layer110may be formed of a material that suppresses diffusion of impurities from the substrate100into the oxide semiconductor layer140. For example, the underlying layer110may be formed of silicon nitride (SiNx), silicon nitride oxide (SiNxOy), silicon oxide (SiOx), silicon oxide nitride (SiOxNy), aluminum nitride (AlNx), aluminum nitride oxide (AlNxOy), aluminum oxide (AlOx), aluminum oxide nitride (AlOxNy), or the like (x and y each represent an arbitrary value). Alternatively, the underlying layer110may have a structure including a stack of films of any of such materials.

SiOxNyand AlOxNyare respectively a silicon compound and an aluminum compound containing nitrogen (N) at a lower content than oxygen (O). SiNxOyand AlNxOyare respectively a silicon compound and an aluminum compound containing oxygen at a lower content than nitrogen.

The underlying layer110described above as an example may be formed by a PVD (Physical Vapor Deposition) method or a CVD (Chemical Vapor Deposition) method. Examples of the usable PVD method include sputtering, vacuum vapor deposition, electron beam vapor deposition, plating, molecular beam epitaxy, and the like. Examples of the usable CVD method include thermal CVD, plasma CVD, catalyst CVD (Cat (catalytic)-CVD or hot-wire CVD), and the like.

The gate electrode120may be formed of a commonly used metal material or a commonly used conductive semiconductor material. For example, the gate electrode120may be formed of aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), zinc (Zn), molybdenum (Mo), indium (In), tin (Sn), hafnium (Hf), tantalum (Ta), tungsten (W), platinum (Pt), bismuth (Bi), or the like. 0Alternatively, the gate electrode120may be formed of an alloy of such materials or a nitride of such materials. Still alternatively, the gate electrode120may be formed of a conductive oxide semiconductor such as ITO (indium tin oxide), IGO (indium gallium oxide), IZO (indium zinc oxide), GZO (zinc oxide containing gallium as a dopant), or the like. The gate electrode120may have a structure including a stack of films of any of such materials.

Preferably, the material used for the gate electrode120is resistant to a heat treatment step in a manufacturing process of a semiconductor device including a channel formed of an oxide semiconductor, and has a work function with which the transistor is of an enhancement type that is turned off when a voltage of 0 V is applied to the gate electrode120.

The gate insulating layer130may be formed of an inorganic insulating material such as SiOx, SiNx, SiOxNy, SiNxOy, AlOx, AlNx, AlOxNy, AlNxOy, or the like, like the underlying layer110. Alternatively, the gate insulating layer130may have a stack of films of any of such materials. The gate insulating layer130may be formed by substantially the same method as that of the underlying layer110. The gate insulating layer130and the underlying layer110may be formed of the same material as, or different materials from, each other.

The oxide semiconductor layer140may be formed of a metal oxide material having the characteristics of a semiconductor. For example, the oxide semiconductor layer140may be formed of an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn) and oxygen (O). Especially, the oxide semiconductor layer140may be formed of an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4. It should be noted that the oxide semiconductor used in the present invention and containing In, Ga, Zn and O is not limited to having the above-described composition ratio. An oxide semiconductor having a different composition ratio is also usable. For example, in order to improve the mobility, the ratio of In may be increased. In order to increase the bandgap and thus decrease the influence of light, the ratio of Ga may be increased.

The oxide semiconductor containing In, Ga, Zn and O may contain another element added thereto. For example, a metal element such as Al, Sn or the like may be added. Instead of the above-described oxide semiconductor, zinc oxide (ZnO), nickel oxide (NiO), tin oxide (SnO2), titanium oxide (TiO2), vanadium oxide (VO2), indium oxide (In2O3), strontium titanate (SrTiO3), or the like may be used. The oxide semiconductor layer140may be amorphous or crystalline. Alternatively, the oxide semiconductor layer140may have a mixed phase of an amorphous phase and a crystalline phase.

The source and drain electrodes150may be formed of a commonly used metal material or a commonly used conductive semiconductor material, like the gate electrode120. For example, the source and drain electrodes150may be formed of Al, Ti, Cr, Co, Ni, Zn, Mo, In, Sn, Hf, Ta, W, Pt, Bi, or the like. Alternatively, the source and drain electrodes150may be formed of an alloy of such materials or a nitride of such materials, Still alternatively, the source and drain electrodes150may be formed of a conductive oxide semiconductor such as ITO, IGO, IZO, GZO, or the like. The source and drain electrodes150may have a structure including a stack of films of any of such materials. Preferably, the material used for the source and drain electrodes150is resistant to a heat treatment step in a manufacturing process of a semiconductor device including a channel formed of an oxide semiconductor, and has a low contact resistance with the oxide semiconductor layer140. As a material having a good electric contact with the oxide semiconductor layer140, a metal material having a work function smaller than that of the oxide semiconductor layer140is usable for the source and drain electrodes150.

The protective layer160may be formed of an inorganic insulating material such as SiOx, SiNx, SiOxNy, SiNxOy, AlOx, AlNx, AlOxNy, AlNxOy, or the like, like the underlying layer110and the gate insulating layer130. Instead of the above-listed inorganic insulating materials, the protective layer160may be formed of a TEOS layer or an organic insulating material. The protective layer160may be formed by substantially the same method as that of the underlying layer110.

The “TEOS layer” refers to a CVD layer formed of TEOS (Tetra Ethyl Ortho Silicate), and has an effect of alleviating the steps of, and thus flattening, a layer therebelow. The underlying layer110and the gate insulating layer130may be formed of a TEOS layer.

Examples of the usable organic insulating material include a polyimide resin, an acrylic resin, an epoxy resin, a silicone resin, a fluorine resin, a siloxane resin, and the like. The protective layer160may be formed of a single layer or a stack of films of such materials. For example, the protective layer160may include a stack of an inorganic insulating material and an organic insulating material.

[Manufacturing Method of the Semiconductor Device10]

With reference toFIG. 4throughFIG. 13, a manufacturing method of the semiconductor device10in embodiment 1 according to the present invention will be described.FIG. 4throughFIG. 13are each a cross-sectional view taken along line A-A′ or B-B′ inFIG. 1.FIG. 4andFIG. 5are respectively a1cross-sectional view taken along line A-A′ and a cross-sectional view taken along line B-B′ showing a step of forming the gate electrode120in the manufacturing method of the semiconductor device10in embodiment 1 according to the present invention. Referring toFIG. 4andFIG. 5, the underlying layer110and a film for the gate electrode120are formed on the substrate100, and patterning is performed by photolithography and etching to form the gate electrode120shown inFIG. 1. Preferably, the etching for forming the gate electrode120is performed under the condition that the etching rate ratio of the gate electrode120with respect to the underlying layer110is high.

FIG. 6andFIG. 7are respectively a cross-sectional view taken along line A-A′ and a cross-sectional view taken along line B-B′ showing a step of forming the gate insulating layer130in the manufacturing method of the semiconductor device10in embodiment 1 according to the present invention. Referring toFIG. 6andFIG. 7, the gate insulating layer130is formed on the underlying layer110and the gate electrode120. An opening may be formed in the gate insulating layer130.

FIG. 8andFIG. 9are respectively a cross-sectional view taken along line A-A and a cross-sectional view taken along line B-B′ showing a step of forming the oxide semiconductor layer140in the manufacturing method of the semiconductor device10in embodiment 1 according to the present invention. Referring toFIG. 8andFIG. 9, a film for the oxide semiconductor layer140is formed on the gate insulating layer130, and patterning is performed by photolithography and etching to form the oxide semiconductor layer140shown inFIG. 1.

The oxide semiconductor layer140may be formed by sputtering. The etching performed to form the oxide semiconductor layer140may be dry etching or wet etching. In the case where the oxide semiconductor layer140is formed by wet etching, an etchant containing oxalic acid, an etchant containing phosphoric acid, or an etchant containing hydrogen fluoride may be used.

FIG. 10andFIG. 11are respectively a cross-sectional view taken along line A-A′ and a cross-sectional view taken along line B-B′ showing a step of forming the source and drain electrodes150in the manufacturing method of the semiconductor device10in embodiment 1 according to the present invention. Referring toFIG. 10andFIG. 11, a film for the source and drain electrodes150is formed on the gate insulating layer130and the oxide semiconductor layer140, and patterning is performed by photolithography and etching to form the source and drain electrodes150shown inFIG. 1.

The etching for forming the source and drain electrodes150may be performed by use of chlorine-containing gas. As a result of the dry etching, the source and drain electrodes150are formed, and a part of the oxide semiconductor layer140and a part of the gate insulating layer130that are below the etched-away part of the film for the source and drain electrodes150are exposed. InFIG. 10andFIG. 11, the part of the oxide semiconductor layer140that is exposed by the dry etching is half-etched in order to suppress the etching for forming the source and drain electrodes150from being left partially undone. Namely, the oxide semiconductor layer140is etched so that the part of the oxide semiconductor layer140exposed from the source and drain electrodes150has a thickness smaller than that of the part of the oxide semiconductor layer140located below the source and drain electrodes150. There is no specific limitation on the thickness of the half-etched part of the oxide semiconductor layer140. The thickness of the half-etched part of the oxide semiconductor layer140may be greater than, or equal to, half of the thickness of the non-half-etched part of the oxide semiconductor layer140, or may be less than, or equal to, half of the thickness of the non-half-etched part of the oxide semiconductor layer140.

Examples of the gas usable for the dry etching include chlorine gas (Cl2), boron trichloride gas (BCl3), carbon tetrachloride gas (CCl4) and the like. These types of gas may be used independently or as a mixture thereof. For example, the dry etching may be performed by use of mixed gas of Cl2and BCl3. The dry etching may be reactive ion etching (RIE), or a plasma process performed by use of any of the above-described types of gas.

With the dry etching, the gate insulating layer130formed of an inorganic insulating material such as, for example, SiOx, SiNx, SiOxNy, SiNxOy, AlOx, AlNx, AlOxNy, AlNxOy, or the like is not etched almost at all. Namely, a part of the gate insulating layer130in a region132shown inFIG. 11that is exposed from the oxide semiconductor layer140is not etched almost at all. Even if the gate insulating layer130is etched by the dry etching, the etching amount of the part of the gate insulating layer130in the region132is smaller than the etching amount of the oxide semiconductor layer140.

The part of the gate insulating layer130that is in the region132is exposed to a dry etching atmosphere. In other words, the part of the gate insulating layer130that is in the region132is exposed to plasma using chlorine-containing gas. Therefore, an etching product containing chlorine is attached to a surface of the part of the gate insulating layer130that is in the region132. Alternatively, chlorine atoms or chlorine ions are implanted into an area having a certain depth from the surface of the part of the gate insulating layer130that is in the region132. The etching product and the implanted chlorine atoms or chlorine ions are considered as chlorine impurities. The chlorine impurities are considered to be present in a surface layer of the gate insulating layer130. The chlorine impurities are not limited to being generated by the dry etching performed to form the source and drain electrodes150, and may be generated by another type of plasma process performed by use of chlorine-containing gas.

When the chlorine impurities are reacted with water, hydrochloric acid is generated. When, for example, the substrate inFIG. 10andFIG. 11is washed, the chlorine impurities present in the part of the gate insulating layer130that is in the region132are reacted with water to generate hydrochloric acid. Hydrochloric acid generated in the region132etches the part of the oxide semiconductor layer140exposed from the source and drain electrodes150. In addition, when the substrate is removed outside from a vacuum device used for dry etching or the like, the chlorine impurities are reacted with moisture contained in the air to generate hydrochloric acid. Also, the chlorine impurities are reacted with moisture contained in the gate insulating layer130or the protective layer160formed on the gate insulating layer130in a later step, and as a result, hydrochloric acid is generated. Therefore, the chlorine impurities need to be removed in order to prevent the generation of hydrochloric acid. In this and the following descriptions of manufacturing methods of semiconductor devices in embodiments according to the present invention, an assembly of the substrate100(100A,100B) and the layer(s) formed thereon at each step will be referred to as the “substrate” for the sake of convenience.

FIG. 12andFIG. 13are respectively a cross-sectional view taken along line A-A and a cross-sectional view taken along line B-B′ showing a step of performing a chlorine removal process of removing the chlorine impurities in the manufacturing method of the semiconductor device10in embodiment 1 according to the present invention. Referring toFIG. 12andFIG. 13, the chlorine impurities present in the surface layer of the part of the gate insulating layer130that is in the region132(seeFIG. 11) exposed from the oxide semiconductor layer140are removed.

The chlorine removal process may be performed by dry etching by use of fluorine-containing gas. With the dry etching, the part of the gate insulating layer130that is in the region132, in which the chlorine impurities are present, namely, the part of the gate insulating layer130exposed from the source and drain electrodes150and the oxide semiconductor layer140, is half-etched. The dry etching removes the chlorine impurities from the surface layer of the part of the gate insulating layer130that is in the region132. There is no specific limitation on the thickness of the half-etched part of the gate insulating layer130. The thickness of the half-etched part of the gate insulating layer130may be greater than, or equal to, half of the thickness of the non-half-etched part of the gate insulating layer130, or may be less than, or equal to, half of the thickness of the non-half-etched part of the gate insulating layer130.

Examples of the gas usable for the dry etching for the chlorine removal process include carbon tetrafluoride gas (CF4), methane trifluoride gas (CHF3), fluorocarbon gas (C2F5), sulfur hexafluoride gas (SF6) and the like. These types of gas may be used independently or as a mixture thereof. For example, the dry etching may be performed by use of mixed gas of CF4and CHF3. The dry etching may be reactive ion etching (RIE), or a plasma process performed by use of any of the above-described types of gas.

With the dry etching performed for the chlorine removal process, the oxide semiconductor layer140is not etched almost at all. Namely, a part of the oxide semiconductor layer140in a region142shown inFIG. 12andFIG. 13that is exposed from the source and drain electrodes150is not etched almost at all. Even if the oxide semiconductor layer140is etched by the dry etching for the chlorine removal process, the etching amount of the part of the oxide semiconductor layer140in the region142is smaller than the etching amount of the gate insulating layer130.

The depth of the half-etching performed on the gate insulating layer130may be determined in accordance with the position of the chlorine impurities (e.g., depth profile of chlorine atoms by a SIMS analysis). In the case where, for example, the chlorine impurities are present in the surface layer of the gate insulating layer130, it is sufficient that the chlorine impurities are removed by the dry etching and the gate insulating layer130is etched even slightly. By contrast, in the case where chlorine atoms or chlorine ions are implanted into an area having a certain depth from the surface of the gate insulating layer130, it is preferable that the gate insulating layer130is etched to a level deeper than the area into which the chlorine atoms or the chlorine ions are implanted.

In the above example, the chlorine removal process is performed by dry etching by use of fluorine-containing gas. The method of the chlorine removal process is not limited to this. For example, the chlorine removal process may be performed by dry etching by use of another type of gas not containing chlorine. Instead of dry etching, plasma process, reverse sputtering or the like is usable for the chlorine removal process. Alternatively, the chlorine removal process may be performed by wet etching by use of a liquid chemical.

When the chlorine impurities are reacted with water, hydrochloric acid is generated. Therefore, the substrate may be kept in vacuum between the dry etching step for forming the source and drain electrodes150and the chlorine removal step. Keeping the substrate between these two steps suppresses hydrochloric acid from being generated due to moisture in the air.

The protective layer160is formed on the entirety of a surface of the substrate shown inFIG. 12andFIG. 13. With the above-described manufacturing method, the semiconductor device10in embodiment 1 according to the present invention is manufactured.

As described above, with the manufacturing method of the semiconductor device10in embodiment 1 according to the present invention, the chlorine impurities generated in the surface layer of the gate insulating layer130by the plasma process performed by use of chlorine-containing gas are removed. Therefore, generation of chlorine is suppressed in later steps, and thus the oxide semiconductor layer140is suppressed from being etched. The semiconductor device10manufactured by such a method is highly reliable.

With reference toFIG. 14throughFIG. 16, an overview of a semiconductor device10A in embodiment 2 according to the present invention will be described. The semiconductor device10A in embodiment 2 is usable in a pixel or a driving circuit of a liquid crystal display device (LCD), a spontaneous emission display device using an organic light-emitting diode (OLED) such as an organic EL element, a quantum dot or the like for a display unit, or a reflection-type display device such as an electronic paper or the like.

[Structure of the Semiconductor Device10A]

FIG. 14is a plan view showing an overview of the semiconductor device10A in embodiment 2 according to the present invention.FIG. 15is a cross-sectional view showing an overview of the semiconductor device10A in embodiment 2 according to the present invention, taken along line C-C′ inFIG. 14.FIG. 16is a cross-sectional view showing an overview of the semiconductor device10A in embodiment 2 according to the present invention, taken along line D-D′ inFIG. 14. As shown inFIG. 14throughFIG. 16, the semiconductor device10A includes a substrate100A, an underlying layer110A, source and drain electrodes150A, an oxide semiconductor layer140A, a gate insulating layer130A, a gate electrode120A, and a protective layer160A. The semiconductor device10A is a top gate-type transistor.

The underlying layer110A is located on the substrate100A. The source and drain electrodes150A are located on the underlying layer110A and has an opening152A formed therein. The oxide semiconductor layer140A is located on a part of the underlying layer110A that is a bottom part of the opening152A and on the source and drain electrodes150A. In other words, the oxide semiconductor layer140A is located on the part of the underlying layer110A exposed from the source and drain electrodes150A and is connected with the source and drain electrodes150A.

The gate insulating layer130A is located on the oxide semiconductor layer140A and the source and drain electrodes150A. The gate electrode120A is located to face the oxide semiconductor layer140A with the gate insulating layer130A being provided therebetween. As shown inFIG. 14, as seen in a plan view, the gate electrode120A covers the oxide semiconductor layer140A. Namely, the oxide semiconductor layer140A is located inner to the gate electrode120A.

As shown inFIG. 15andFIG. 16, an underlying layer110A-1in an area where the source and drain electrodes150A are not provided, namely, the underlying layer110A-1exposed from the source and drain electrodes150A to contact the oxide semiconductor layer140A, has a thickness smaller than that of an underlying layer110A-2located below the source and drain electrodes150A.

The source and drain electrodes150A include a pair of electrodes separated from each other with a distance. In accordance with the applied voltage, one of the pair of electrodes is the source electrode, and the other electrode is the drain electrode. The distance between the pair of electrodes corresponds to a channel length of the semiconductor device10A.

The protective layer160A covers the gate electrode120A and the gate insulating layer130A.

The substrate100A, the underlying layer110A, the gate electrode120A, the gate insulating layer130A, the oxide semiconductor layer140A, the source and drain electrodes150A, and the protective layer160A may be formed of substantially the same materials as those of the semiconductor device10in embodiment 1.

[Manufacturing Method of the Semiconductor Device10A]

With reference toFIG. 17throughFIG. 26, a manufacturing method of the semiconductor device10A in embodiment 2 according to the present invention will be described,FIG. 17throughFIG. 26are each a cross-sectional view taken along line C-C′ or D-D′ inFIG. 14.FIG. 17andFIG. 18are respectively a cross-sectional view taken along line C-C′ and a cross-sectional view taken along line D-D′ showing a step of forming the source and drain electrodes150A in the manufacturing method of the semiconductor device10A in embodiment 2 according to the present invention. Referring toFIG. 17andFIG. 18, the underlying layer110A and a film for the source and drain electrodes150A are formed on the substrate100A, and patterning is performed by photolithography and etching to form the source and drain electrodes150A shown inFIG. 14. Preferably, the etching for forming the source and drain electrodes150A is performed under the condition that the etching rate ratio of the source and drain electrodes150A with respect to the underlying layer110A is high.

The etching for forming the source and drain electrodes150A may be performed by use of chlorine-containing gas. As a result of the dry etching, the source and drain electrodes150A are formed, and a part of the underlying110A that is below the etched-away part of the film for the source and drain electrodes150A is exposed. It is preferable to perform over-etching until the underlying layer110A is exposed completely by the dry etching in order to suppress the etching for forming the source and drain electrodes150A from being left partially undone.

Examples of the gas usable for the dry etching include Cl2, BCl3, CCl4and the like. These types of gas may be used independently or as a mixture thereof. For example, the dry etching may be performed by use of mixed gas of Cl2and BCl3. The dry etching may be RIE, or a plasma process performed by use of any of the above-described types of gas.

With the dry etching, the underlying layer110A formed of an inorganic insulating material such as, for example, SiOx, SiNx, SiOxNy, AlOx, AlNx, AlOxNy, AlNxOy, or the like is not etched almost at all. Namely, parts of the underlying layer110A in regions112A and114A shown inFIG. 17andFIG. 18that are exposed from the source and drain electrodes150A are not etched almost at all.

The parts of the underlying layer110A that are in the regions112A and114A are exposed to a dry etching atmosphere. In other words, the parts of the underlying layer110A that are in the regions112A and114A are exposed to plasma using chlorine-containing gas. Therefore, chlorine impurities are attached to a surface of the underlying layer110A or implanted into the underlying layer110A. The chlorine impurities are not limited to being generated by the dry etching performed to form the source and drain electrodes150A, and may be generated by another type of plasma process performed by use of chlorine-containing gas.

When the chlorine impurities are reacted with water, hydrochloric acid is generated. When, for example, the substrate inFIG. 17andFIG. 18is washed, the chlorine impurities present in the parts of the underlying layer110A that are in the regions112A and114A are reacted with water to generate hydrochloric acid. Also, the chlorine impurities are reacted with moisture contained in the oxide semiconductor layer140A formed on the parts of the underlying layer110A that are in the regions112A and114A in a later step, and as a result, hydrochloric acid is generated. Hydrochloric acid etches the oxide semiconductor layer140A located on the regions112A and114A. Therefore, the chlorine impurities need to be removed in order to prevent the generation of hydrochloric acid.

FIG. 19andFIG. 20are respectively a cross-sectional view taken along line C-C′ and a cross-sectional view taken along line D-D′ showing a step of performing a chlorine removal process of removing the chlorine impurities in the manufacturing method of the semiconductor device10A in embodiment 2 according to the present invention. Referring toFIG. 19andFIG. 20, the chlorine impurities present in the parts of the underlying layer110A that are in the regions112A and114A are removed.

The chlorine removal process may be performed by dry etching by use of fluorine-containing gas. With the dry etching, the parts of the underlying layer110A that are in the regions112A and114A, in which the chlorine impurities are present, namely, the parts of the underlying layer110A exposed from the source and drain electrodes150A are half-etched. The dry etching removes the chlorine impurities from the surface layer of the parts of the underlying layer110A that are in the regions112A and114A. There is no specific limitation on the thickness of the half-etched part of the underlying layer110A. The thickness of the half-etched parts of the underlying layer110A may be greater than, or equal to, half of the thickness of the non-half-etched part of the underlying layer110A, or may be less than, or equal to, half of the thickness of the non-half-etched part of the underlying layer110A.

Examples of the gas usable for the dry etching for the chlorine removal process include CF4, CHF3, C2F6, SF6and the like. These types of gas may be used independently or as a mixture thereof. For example, the dry etching may be performed by use of mixed gas of CF4and CHF3. The dry etching may be RIE, or a plasma process performed by use of any of the above-described types of gas.

The depth of the half-etching performed on the underlying layer110A may be determined in accordance with the position of the chlorine impurities. In the case where, for example, the chlorine impurities are present in the surface layer of the underlying layer110A, it is sufficient that the chlorine impurities are removed by the dry etching and the underlying layer110A is etched even slightly. By contrast, in the case where chlorine atoms or chlorine ions are implanted into an area having a certain depth from the surface of the underlying layer110A, it is preferable that the underlying layer110A is etched to a level deeper than the area into which the chlorine atoms or the chlorine ions are implanted.

In the above example, the chlorine removal process is performed by dry etching by use of fluorine-containing gas. The method of the chlorine removal process is not limited to this. For example, the chlorine removal process may be performed by dry etching by use of another type of gas not containing chlorine. Instead of dry etching, plasma process, reverse sputtering or the like is usable for the chlorine removal process. Alternatively, the chlorine removal process may be performed by wet etching by use of a liquid chemical.

When the chlorine impurities are reacted with water, hydrochloric acid is generated. Therefore, the substrate may be kept in vacuum between the dry etching step for forming the source and drain electrodes150A and the chlorine removal step. Keeping the substrate between these two steps suppresses hydrochloric acid from being generated due to moisture in the air.

FIG. 21andFIG. 22are respectively a cross-sectional view taken along line C-C′ and a cross-sectional view taken along line D-D′ showing a step of forming the oxide semiconductor layer140A in the manufacturing method of the semiconductor device10A in embodiment 2 according to the present invention. Referring toFIG. 21andFIG. 22, a film for the oxide semiconductor layer140A is formed on the underlying layer110A and the source and drain electrodes150A, and patterning is performed by photolithography and etching to form the oxide semiconductor layer140A shown inFIG. 14.

The oxide semiconductor layer140A may be formed by sputtering. The etching performed to form the oxide semiconductor layer140A may be dry etching or wet etching. In the case where the oxide semiconductor layer140A is formed by wet etching, an etchant containing oxalic acid, an etchant containing phosphoric acid, or an etchant containing hydrogen fluoride may be used.

FIG. 23andFIG. 24are respectively a cross-sectional view taken along line C-C′ and a cross-sectional view taken along line D-D′ showing a step of forming the gate insulating layer130A in the manufacturing method of the semiconductor device10A in embodiment 2 according to the present invention. Referring toFIG. 23andFIG. 24, the gate insulating layer130A is formed on the source and drain electrodes150A and the oxide semiconductor layer140A. When necessary, an opening may be formed in the gate insulating layer130A.

FIG. 25andFIG. 26are respectively a cross-sectional view taken along line C-C′ and a cross-sectional view taken along line D-D′ showing a step of forming the gate electrode120A in the manufacturing method of the semiconductor device10A in embodiment 2 according to the present invention. Referring toFIG. 25andFIG. 26, a film for the gate electrode120A is formed on gate insulating layer130A, and patterning is performed by photolithography and etching to form the gate electrode120A shown inFIG. 14. Preferably, the etching for forming the gate electrode120A is performed under the condition that the etching rate ratio of the gate electrode120A with respect to the gate insulating layer130A is high.

The protective layer160A is formed on the entirety of a surface of the substrate shown inFIG. 25andFIG. 26. With the above-described manufacturing method, the semiconductor device10A in embodiment 2 according to the present invention is manufactured.

As described above, with the manufacturing method of the semiconductor device10A in embodiment 2 according to the present invention, the chlorine impurities generated in the surface layer of the underlying layer110A by the plasma process performed by use of chlorine-containing gas are removed. Therefore, generation of chlorine is suppressed in later steps, and thus the oxide semiconductor layer140A is suppressed from being etched. The semiconductor device10A manufactured by such a method is highly reliable.

With reference toFIG. 27andFIG. 28, an overview of a semiconductor device10B in embodiment 3 according to the present invention will be described. The semiconductor device10B in embodiment 3 is usable in a pixel or a driving circuit of a liquid crystal display device (LCD), a spontaneous emission display device using an organic light-emitting diode (OLED) such as an organic EL element, a quantum dot or the like for a display unit, or a reflection-type display device such as an electronic paper or the like.

[Structure of the Semiconductor Device10B]

A plan view of the semiconductor device10B is the same as that of the semiconductor device10A in embodiment 2 (shown inFIG. 14), andFIG. 14is referred to for the description.FIG. 27is a cross-sectional view showing an overview of the semiconductor device10B in embodiment 3 according to the present invention, taken along line C-C′ inFIG. 14.FIG. 28is a cross-sectional view showing an overview of the semiconductor device10B in embodiment 3 according to the present invention, taken along line D-D′ inFIG. 14. As shown inFIG. 27andFIG. 28, the semiconductor device10B includes a substrate100B, an underlying layer110B, an oxide semiconductor layer140B, source and drain electrodes150B, a gate insulating layer130B, a gate electrode120B, and a protective layer160B. The semiconductor device10B is a top gate-type transistor.

The underlying layer110B is located on the substrate100B. The oxide semiconductor layer140B is located on the underlying layer110B. The source and drain electrodes150B are located on the underlying layer110B and the oxide semiconductor layer140B and patterned to expose a part of the oxide semiconductor layer140B. An underlying layer110B-1exposed from the oxide semiconductor layer140B has a thickness smaller than that of an underlying layer110B-2located below the oxide semiconductor layer140B or the source and drain electrodes150B. An oxide semiconductor layer140B-1exposed from the source and drain electrodes150B has a thickness smaller than that of an oxide semiconductor layer140B-2located below the source and drain electrodes150B.

The gate insulating layer130B is located on the oxide semiconductor layer140B and the source and drain electrodes150B. The gate electrode120B is located to face the oxide semiconductor layer140B with the gate insulating layer130B being provided therebetween. Like inFIG. 14, as seen in a plan view, the gate electrode120B is located to cover the oxide semiconductor layer140B. Namely, the oxide semiconductor layer140B is located inner to the gate electrode120B.

The source and drain electrodes150B include a pair of electrodes separated from each other with a distance. In accordance with the applied voltage, one of the pair of electrodes is the source electrode, and the other electrode is the drain electrode. The distance between the pair of electrodes corresponds to a channel length of the semiconductor device10B.

The protective layer160B covers the gate electrode120B and the gate insulating layer130B.

The substrate100B, the underlying layer110B, the gate electrode120B, the gate insulating layer130B, the oxide semiconductor layer140B, the source and drain electrodes150B, and the protective layer160B may be formed of substantially the same materials as those of the semiconductor device10in embodiment 1.

[Manufacturing Method of the Semiconductor Device10B]

With reference toFIG. 29throughFIG. 38, a manufacturing method of the semiconductor device10B in embodiment 3 according to the present invention will be described,FIG. 29throughFIG. 38are each a cross-sectional view taken along line C-C′ or D-D′ inFIG. 14.FIG. 29andFIG. 30are respectively a cross-sectional view taken along line C-C′ and a cross-sectional view taken along line D-D′ showing a step of forming the oxide semiconductor layer140B in the manufacturing method of the semiconductor device10B in embodiment 3 according to the present invention. Referring toFIG. 29andFIG. 30, the underlying layer110B and a film for the oxide semiconductor layer140B are formed on the substrate100B, and patterning is performed by photolithography and etching to form the oxide semiconductor layer140B like inFIG. 14.

The oxide semiconductor layer140B may be formed by sputtering. The etching performed to form the oxide semiconductor layer140B may be dry etching or wet etching. In the case where the oxide semiconductor layer140B is formed by wet etching, an etchant containing oxalic acid, an etchant containing phosphoric acid, or an etchant containing hydrogen fluoride may be used.

FIG. 31andFIG. 32are respectively a cross-sectional view taken along line C-C′ and a cross-sectional view taken along line D-D′ showing a step of forming the source and drain electrodes150B in the manufacturing method of the semiconductor device10B in embodiment 3 according to the present invention. Referring toFIG. 31andFIG. 32, a film for the source and drain electrodes150B is formed on the underlying layer110B and the oxide semiconductor layer140B, and patterning is performed by photolithography and etching to form the source and drain electrodes150B like inFIG. 14.

The etching for forming the source and drain electrodes150B may be performed by use of chlorine-containing gas. As a result of the dry etching, the source and drain electrodes150B are formed, and a part of the oxide semiconductor layer140B and a part of the underlying110B that are below the etched-away part of the film for the source and drain electrodes150B are exposed. The part of the oxide semiconductor layer140B that is exposed by the dry etching is half-etched in order to suppress the etching for forming the source and drain electrodes150B from being left partially undone. Namely, the oxide semiconductor layer140B is etched so that the thickness of the oxide semiconductor layer140B-1exposed from the source and drain electrodes150B is smaller than that of the oxide semiconductor layer140B-2located below the source and drain electrodes150B. There is no specific limitation on the thickness of the half-etched part of the oxide semiconductor layer140B. The thickness of the half-etched part of the oxide semiconductor layer140B may be greater than, or equal to, half of the thickness of the non-half-etched part of the oxide semiconductor layer140B, or may be less than, or equal to, half of the thickness of the non-half-etched part of the oxide semiconductor layer140B.

Examples of the gas usable for the dry etching include Cl2, BCl3, CCl4and the like. These types of gas may be used independently or as a mixture thereof. For example, the dry etching may be performed by use of mixed gas of Cl2and BCl3. The dry etching may be RIE, or a plasma process performed by use of any of the above-described types of gas.

With the dry etching, the underlying layer110B formed of an inorganic insulating material such as, for example, SiOx, SiNx, SiOxNy, SiNxOy, AlOx, AlNx, AlOxNy, AlNxOy, or the like is not etched almost at all. Namely, a part of the underlying layer110B in a region114B shown inFIG. 32that is exposed from the source and drain electrodes150B and the oxide semiconductor layer140B is not etched almost at all.

The part of the underlying layer110B that is in the region114B is exposed to a dry etching atmosphere. In other words, the part of the underlying layer110B that is in the region114B is exposed to plasma using chlorine-containing gas. Therefore, chlorine impurities are attached to a surface of the underlying layer110B or implanted into the underlying layer110B. The chlorine impurities are not limited to being generated by the dry etching performed to form the source and drain electrodes150B, and may be generated by another type of plasma process performed by use of chlorine-containing gas.

When the chlorine impurities are reacted with water, hydrochloric acid is generated. When, for example, the substrate inFIG. 31andFIG. 32is washed, the chlorine impurities present in the part of the underlying layer110B that is in the region114B are reacted with water to generate hydrochloric acid. Also, the chlorine impurities are reacted with moisture contained in the oxide semiconductor layer140B formed on the part of the underlying layer110B that is in the region114B in a later step, and as a result, hydrochloric acid is generated. Hydrochloric acid etches the oxide semiconductor layer140B located on the region114B. Therefore, the chlorine impurities need to be removed in order to prevent the generation of hydrochloric acid.

FIG. 33andFIG. 34are respectively a cross-sectional view taken along line C-C′ and a cross-sectional view taken along line D-D′ showing a step of performing a chlorine removal process of removing the chlorine impurities in the manufacturing method of the semiconductor device10B in embodiment 3 according to the present invention. Referring toFIG. 33andFIG. 34, the chlorine impurities present in the part of the underlying layer110B that is in the region114B are removed.

The chlorine removal process may be performed by dry etching by use of fluorine-containing gas. With the dry etching, the part of the underlying layer110B that is in the region114B, in which the chlorine impurities are present, namely, the part of the underlying layer110B exposed from the source and drain electrodes150B and the oxide semiconductor layer140B is half-etched. The dry etching removes the chlorine impurities from the surface layer of the part of the underlying layer110B that is in the region114B. There is no specific limitation on the thickness of the half-etched underlying layer110B-1. The thickness of the half-etched underlying layer110B-1may be greater than, or equal to, half of the thickness of the non-half-etched underlying layer110B-2, or may be less than, or equal to, half of the thickness of the non-half-etched underlying layer110B-2.

Examples of the gas usable for the dry etching for the chlorine removal process include CF4, CHF3, C2F6, SF6and the like. These types of gas may be used independently or as a mixture thereof. For example, the dry etching may be performed by use of mixed gas of CF4and CHF3. The dry etching may be RIE, or a plasma process performed by use of any of the above-described types of gas.

The depth of the half-etching performed on the underlying layer110B may be determined in accordance with the position of the chlorine impurities. In the case where, for example, the chlorine impurities are present in the surface layer of the underlying layer110B, it is sufficient that the chlorine impurities are removed by the dry etching and the underlying layer110B is etched even slightly. By contrast, in the case where chlorine atoms or chlorine ions are implanted into an area having a certain depth from the surface of the underlying layer110B, it is preferable that the underlying layer110B is etched to a level deeper than the area into which the chlorine atoms or the chlorine ions are implanted.

In the above example, the chlorine removal process is performed by dry etching by use of fluorine-containing gas. The method of the chlorine removal process is not limited to this. For example, the chlorine removal process may be performed by dry etching by use of another type of gas not containing chlorine. Instead of dry etching, plasma process, reverse sputtering or the like is usable for the chlorine removal process. Alternatively, the chlorine removal process may be performed by wet etching by use of a liquid chemical.

When the chlorine impurities are reacted with water, hydrochloric acid is generated. Therefore, the substrate may be kept in vacuum between the dry etching step for forming the source and drain electrodes150B and the chlorine removal step. Keeping the substrate between these two steps suppresses hydrochloric acid from being generated due to moisture in the air.

FIG. 35andFIG. 36are respectively a cross-sectional view taken along line C-C′ and a cross-sectional view taken along line D-D′ showing a step of forming the gate insulating layer130B in the manufacturing method of the semiconductor device10B in embodiment 3 according to the present invention. Referring toFIG. 35andFIG. 36, the gate insulating layer130B is formed on the source and drain electrodes150B and the oxide semiconductor layer140B. An opening may be formed in the gate insulating layer130B.

FIG. 37andFIG. 38are respectively a cross-sectional view taken along line C-C′ and a cross-sectional view taken along line D-D′ showing a step of forming the gate electrode120B in the manufacturing method of the semiconductor device10B in embodiment 3 according to the present invention. Referring toFIG. 37andFIG. 38, a film for the gate electrode120B is formed on gate insulating layer130B, and patterning is performed by photolithography and etching to form the gate electrode120B like inFIG. 14. Preferably, the etching for forming the gate electrode120B is performed under the condition that the etching rate ratio of the gate electrode120B with respect to the gate insulating layer130B is high.

The protective layer160B is formed on the entirety of a surface of the substrate shown inFIG. 37andFIG. 38. With the above-described manufacturing method, the semiconductor device10B in embodiment 3 according to the present invention is manufactured.

As described above, with the manufacturing method of the semiconductor device10B in embodiment 3 according to the present invention, the chlorine impurities generated in the surface layer of the underlying layer110B by the plasma process performed by use of chlorine-containing gas are removed. Therefore, generation of chlorine is suppressed in later steps, and thus the oxide semiconductor layer140B is suppressed from being etched. The semiconductor device10B manufactured by such a method is highly reliable.

EXAMPLES

Semiconductor devices in embodiment 1 and embodiment 2 (examples) according to the present invention and semiconductor devices in a comparative example were manufactured. The following evaluations were performed on these semiconductor devices: impurity evaluation on the insulating layer to which the chlorine impurities were attached or implanted, transistor characteristic fluctuation evaluation performed by directing light toward the semiconductor devices, and evaluation with optical microscope. Hereinafter, the results of these evaluations will be described.

Test samples were manufactured to reproduce the state of the part of the gate insulating layer130in the region132in embodiment 1 (seeFIG. 11) and the state of the parts of the underlying layer110A in the regions112A and114A in embodiment 2 (seeFIG. 17andFIG. 18). On the test samples, an impurity evaluation was performed in the depth direction by time-of-flight secondary ion mass spectrometry (ToF-SIMS).

FIG. 39A,FIG. 39B,FIG. 39C,FIG. 40AandFIG. 40Bshow a manufacturing method of example test samples and comparative example test samples. First, as shown inFIG. 39A, an insulating layer210formed of SiOxcorresponding to the underlying layer was formed to a thickness of about 500 nm on a silicon substrate200. Next, as shown inFIG. 39B, a surface of the insulating layer210was subjected to dry etching by use of mixed gas of Cl2and BCl3as an example of the chlorine-containing gas (chlorine etching220). The insulating layer210was not etched almost at all by the chlorine etching220. Next, as shown inFIG. 390, the insulating layer210having the chlorine impurities implanted thereto was subjected to dry etching by use of mixed gas of CF4, CHF3and Ar as an example of the fluorine-containing gas (fluorine etching230). The insulating layer210was etched by about 50 nm by the fluorine etching230.

The chlorine etching220and the fluorine etching230were performed under the following conditions.

[Conditions for the Chlorine Etching220]

[Conditions for the Fluorine Etching230]

The example samples were subjected to the fluorine etching230, whereas the comparative example samples were not subjected to the fluorine etching230. Namely, the difference between the example samples and the comparative example samples was whether the fluorine etching230was performed or not.

Next, as shown inFIG. 40A, an oxide semiconductor layer240formed of IGZO was formed by sputtering to a thickness of about 80 nm on the insulating layer210. As IGZO, an IGZO target having a composition ratio of In:Ga:Zn:O=1:1:1:4 was used. Next, as shown inFIG. 40B, a protective layer250formed of SiOxwas formed to a thickness of about 200 nm on the oxide semiconductor layer240. The samples having a structure shown inFIG. 40Bwere analyzed by ToF-SIMS from above the samples (from the side on which the protective layer250was formed)

FIG. 41andFIG. 42respectively show the results of the ToF-SIMS analysis performed on the example samples according to the present invention and on the comparative example samples. InFIG. 41andFIG. 42, the insulating layer210is expressed as US-SiOx, the oxide semiconductor layer240is expressed as IGZO, and the protective layer250is expressed as Cap-SiOx. The solid line represents the chlorine concentration (Cl concentration), the dotted line represents the gallium oxide concentration (GaO concentration), and the white line represents the silicon concentration (Si concentration). As shown inFIG. 41, regarding the example samples, it has been confirmed that the Cl concentration profile in the UC-SiOxfilm, the IGZO film and the Cap-SiOxfilm and at an interface between these thin films does not exhibit any specific concentration gradient and is generally constant.

By contrast, as shown inFIG. 42, regarding the comparative example samples, it has been confirmed that the Cl concentration profile is higher at and in the vicinity of the interface between the UC-SiOxfilm and the IGZO film and at and in the vicinity of the interface between the IGZO film and the Cap-SiOxfilm than in each of these thin films. It has also been confirmed that the Cl concentration in the comparative example samples at both of the interfaces is higher by one digit than the Cl concentration in the example samples. Namely, in the comparative example samples, the chlorine impurities implanted into the surface layer of the US-SiOxfilm by the chlorine etching220were not removed and were piled up at the interfaces between the thin films. By contrast, in the example samples, the chlorine impurities implanted into the surface layer of the US-SiOxfilm were removed by the fluorine etching230.

It is considered that the chlorine impurities were piled up at and in the vicinity of the interface between IGZO and Cap-SiOxbecause the chlorine impurities present at and in the vicinity of the interface between UC-SiOxand IGZO were diffused by heat generated by the film formation of Cap-SiOxand trapped at and in the vicinity of the interface between IGZO and Cap-SiOx.

Based on the results, it is considered that the chlorine impurities are diffused by heat and piled up at the interfaces between the thin films.

Semiconductor devices10in embodiment 1 (example) according to the present invention and semiconductor devices in a comparative example were manufactured. These semiconductor devices were evaluated on the transistor characteristics when being irradiated with light and the transistor characteristics when not being irradiated with light. The semiconductor devices in the comparative example were manufactured by the manufacturing method of the semiconductor device10except that the chlorine removal step was not performed.

The channel length (L) and the channel width (W) of the manufactured semiconductor devices were L/W =6.0/6.0 μm. Namely, referring toFIG. 1, the distance between the pair of electrodes as the source and drain electrodes150, and the width of each of the source and drain electrodes150, were both 6.0 μm, For evaluating the transistor characteristics, the drain voltage VD was fixed to 10 V and the gate voltage VG was varied from −20 V to +20 V to measure the drain current ID, thus to find the ID-VG characteristic. The temperature at the time of the transistor characteristic evaluation was 85° C. The transistor characteristic evaluation was performed in a dark room, and the part of the oxide semiconductor layer140exposed from the source and drain electrodes150was irradiated with light directed from above, namely, from the side of the protective layer160. The irradiation light was white LED light of 7000 lx.

FIG. 43andFIG. 44respectively show the results of the transistor reliability test performed on the example samples and on the comparative example samples. InFIG. 43andFIG. 44, the solid line represents the transistor characteristic evaluated without irradiation with light (Dark characteristic), and the white line represents the transistor characteristic evaluated with irradiation with light (Photo characteristic). As shown inFIG. 43, regarding the example samples, there is almost no difference between the Dark characteristic and the Photo characteristic. By contrast, as shown inFIG. 44, regarding the comparative example samples, as compared with the Dark characteristic, the Photo characteristic is shifted to the minus side of the gate voltage VG at the rise of the drain current ID, and the rise of the drain current ID is milder. Namely, it is considered that in the comparative example samples, a defect is generated in the oxide semiconductor layer acting as the channel, whereas in the example samples, generation of the defect in the oxide semiconductor layer acting as the channel is suppressed.

Semiconductor devices10A in embodiment 2 (example) according to the present invention and semiconductor devices in a comparative example were manufactured. These semiconductor devices were evaluated on the shape thereof by an optical microscope. The semiconductor devices in the comparative example were manufactured by the manufacturing method of the semiconductor device10A except that the chlorine removal step was not performed.

FIG. 45shows an optical micrograph of a transistor as an example sample according to the present invention.FIG. 46is a schematic cross-sectional view ofFIG. 45taken along line E-E′ inFIG. 45,FIG. 47shows an optical micrograph of a transistor as a comparative example sample.FIG. 48is a schematic cross-sectional view ofFIG. 47taken along line E-E′ inFIG. 47.

The example sample shown inFIG. 45and the comparative example sample shown inFIG. 47are compared. In the example sample, no specific shape abnormality is found in the oxide semiconductor layer140. By contrast, in the comparative example sample, a shape abnormality is found in a region145A (FIG. 48) where the underlying layer110A and the oxide semiconductor layer140A are in contact with each other. More specifically, in the comparative example, spots149A are found in the region145A. The spots149A are considered to be formed because the oxide semiconductor layer140A was etched, resulting in formation of a cavity in the region145A shown inFIG. 48.

FIG. 49shows an optical micrograph of a transistor as an example sample according to the present invention.FIG. 50is a schematic cross-sectional view ofFIG. 49taken along line F-F′ inFIG. 49.FIG. 51shows an optical micrograph of a transistor as a comparative example sample.FIG. 52is a schematic cross-sectional view ofFIG. 51taken along line F-F′ inFIG. 51.

The example sample shown inFIG. 49and the comparative example sample shown inFIG. 51are compared. In the example sample, no specific shape abnormality is found in the oxide semiconductor layer140. By contrast, in the comparative example sample, a shape abnormality is found in a region147A (FIG. 52) where the underlying layer110A and the oxide semiconductor layer140A are in contact with each other, and the oxide semiconductor layer140A and the gate insulating layer130A are in contact with each other. More specifically, in the comparative example, spots149A are found in the region147A. The spots149A are considered to be formed because the oxide semiconductor layer140A was etched, resulting in formation of a cavity in the region147A shown inFIG. 52.

From the above-described results, it has been confirmed that in the examples, the chlorine impurities are not piled up at the interfaces between the thin films, the transistor characteristics are fluctuated little by the presence/absence of light, and no shape abnormality occurs, unlike in the comparative examples. Namely, the semiconductor devices in the examples are more reliable than the semiconductor devices in the comparative examples.

The present invention is not limited to any of the above-described embodiments, and may be appropriately modified without departing from the gist of the present invention.