Non-volatile semiconductor memory

A non-volatile semiconductor memory comprising at least one EPROM/EEPROM memory cell that includes a floating gate transistor and a coupling capacitor, said floating gate transistor comprising a field effect transistor and a polysilicon layer, the coupling capacitor comprising a first electrode and a second electrode as well as a dielectric interposed between said electrodes, the first electrode of the coupling capacitor being electrically coupled with the polysilicon layer of the floating gate transistor, and the control electrode of the floating gate transistor forming the second electrode of the coupling capacitor. The invention also relates to a display device and an arrangement for controlling a display device, which each comprise a non-volatile semiconductor memory.

The invention relates to a non-volatile semiconductor memory comprising at least one EPROM (Erasable and Programmable Read-Only Memory)/EEPROM (Electrically Erasable and Programmable Read-Only Memory) memory cell containing a floating gate transistor and a coupling capacitor, said floating gate transistor comprising a field effect transistor and a polysilicon layer, and the coupling capacitor comprising a first electrode and a second electrode as well as a dielectric interposed between said electrodes. The invention also relates to a display device and to an arrangement for controlling a display device.

EPROM/EEPROM memory cells are used to build up non-volatile semiconductor memories, in particular, for integrated circuits (embedded EPROM/EEPROM) and, in general, for use in computers or microprocessor-controlled devices for storing programs and/or data that should be retained also when no supply voltage is applied. Also so-termed driver circuits for display screens, for example liquid crystal display screens, comprise several non-volatile semiconductor memories to adjust certain parameters that optimize the visual contrast of the display screen.

An EPROM/EEPROM memory cell generally comprises a floating gate transistor whose floating gate is positively charged or negatively charged and hence represents, respectively, an erased or a programmed state. An EPROM/EEPROM memory cell may further comprise a coupling capacitor that induces the voltage applied to the control electrode into the floating gate. An EEPROM memory cell generally also comprises a second transistor, which is an access transistor.

Customarily, the control electrode and the floating gate are each formed by a polysilicon layer. This has the disadvantage that the manufacturing process is complicated and hence expensive. A further drawback resides in that a comparatively large area of the semiconductive substrate is needed to accommodate the separate coupling capacitor.

Therefore, it is an object of the invention to provide a non-volatile semiconductor memory comprising an improved EPROM/EEPROM memory cell.

This object is achieved by a non-volatile semiconductor memory comprising at least one EPROM/EEPROM memory cell that includes a floating gate transistor and a coupling capacitor, said floating gate transistor comprising a field effect transistor and a polysilicon layer, the coupling capacitor comprising a first electrode and a second electrode as well as a dielectric interposed between said electrodes, the first electrode of the coupling capacitor being electrically coupled with the polysilicon layer of the floating gate transistor, and the control electrode of the floating gate transistor forming the second electrode of the coupling capacitor.

It is advantageous that the floating gate transistor and the coupling capacitor of a memory cell are arranged one above the other or one inside the other rather than next to one another. By virtue thereof, the space required by the non-volatile semiconductor memory on the semiconductor substrate can be reduced and a saving in valuable semiconductor material can be made. The manufacturing costs are further reduced as only one polysilicon layer is used.

In addition, the parasitic capacitances of such a floating gate are lower than the parasitic capacitances of a floating gate made of an isolated polysilicon layer, as is customarily used in a floating gate transistor.

The advantageous embodiments of the invention as claimed in the sub-claims enable the manufacturing steps for such an EPROM/EEPROM memory cell to be inserted without additional expenditure into a customary CMOS (Complementary Metal Oxide Semiconductor) manufacturing method for integrated circuits.

The invention further relates to a display device equipped with an arrangement for controlling the display device and to an arrangement for controlling a display device, which arrangement comprises a non-volatile semiconductor memory including at least one EPROM/EEPROM memory cell comprising a floating gate transistor and a coupling capacitor, said floating gate transistor comprising a field effect transistor and a polysilicon layer, the coupling capacitor comprising a first electrode and a second electrode as well as a dielectric interposed between said electrodes, the first electrode of the coupling capacitor being electrically coupled with the polysilicon layer of the floating gate transistor, and the control electrode of the floating gate transistor forming the second electrode of the coupling capacitor.

A display device, for example a liquid crystal display screen, comprises at least an arrangement, for example an integrated circuit, for controlling said display device. For storing data, the arrangement for controlling a display device may comprise non-volatile semiconductor memories having one or more EPROM/EEPROM memory cells. An EPROM memory cell of a non-volatile semiconductor memory comprises a floating gate transistor and a coupling capacitor. An EEPROM memory cell generally additionally comprises an access transistor. To electrically address the individual components in a memory cell, a non-volatile semiconductor memory comprises lines, i.e. word lines and bit lines.

The floating gate transistor comprises a field effect transistor, preferably a MOS (Metal Oxide Semiconductor) field effect transistor and a polysilicon layer. It is particularly preferred that the field effect transistor is an n-channel MOS field effect transistor. A field effect transistor comprises an emitter (source), a collector (drain) and a control electrode. The coupling capacitor preferably is an MIM (Metal-Insulator-Metal) capacitor comprising two metallic electrodes.

A non-volatile memory comprising at least one EPROM/EEPROM memory cell can be manufactured using, for example, CMOS technology. To manufacture an EPROM/EEPROM memory cell in accordance with the invention, use can be made of a CMOS process wherein a polysilicon layer and two or more metal layers are provided.

FIG. 1is a plan view of an embodiment of an EPROM memory cell of a non-volatile memory, which memory cell can be manufactured by means of a CMOS process, in which embodiment a polysilicon layer and four electroconductive layers, so-termed interconnection layers are provided. The EPROM memory cell comprises a floating gate transistor and a coupling capacitor.FIG. 1shows the semiconductive substrate1, doped semiconductor regions2,3in the semiconductive substrate1, a polysilicon layer6, electroconductive interconnection layers8,10,12,14, and electroconductive contact holes (vias)15,16,18,19,20,21, which electrically interconnect the individual layers and regions, such as the polysilicon layer6, the doped semiconductor regions2,3and the interconnection layers8,10,12,14. The dielectric layers situated between the semiconductive substrate1, polysilicon layer6and the individual interconnection layers8,10,12,14are not shown inFIG. 1. A field oxide layer that electrically insulates the floating gate transistors of the individual EPROM memory cells are not shown either.

FIG. 2is a diagrammatic cross-sectional view taken on the intersection line A-A′ of the embodiment of an EPROM memory cell shown inFIG. 1. Semiconductor regions2,3, which are preferably n-doped, are implanted into the semiconductive substrate1, which is preferably p-doped. The first semiconductor region2is the collector (drain) and the second semiconductor region3is the emitter (source) of the floating gate transistor. On the semiconductive substrate1there is a field oxide layer4that is interrupted in the active regions of the semiconductive substrate1, i.e. in the areas of the first and the second semiconductor region2,3. The field oxide layer4preferably comprises SiO2. A first dielectric layer5is present on the first and the second semiconductor region2,3as well as on the semiconductive substrate1sandwiched between said regions and on the field oxide layer4. A polysilicon layer6is embedded in the first dielectric layer5. The polysilicon layer6preferably comprises doped polysilicon and is embedded in the first dielectric layer5in such a manner that only a thin layer of the material of the first dielectric layer5is present between the semiconductive substrate1, or the first and the second semiconductor region2,3, and the polysilicon layer6. This so-termed tunnel oxide region7is so thin that electrons are capable of tunneling from the semiconductive substrate1to the polysilicon layer6or from the polysilicon layer6to the first semiconductor region2. (Fowler-Nordheim tunneling).

A first interconnection layer8is provided in accordance with a structure on the first dielectric layer5. The first interconnection layer8is structured such that a part of the first interconnection layer8electrically contacts the second semiconductor region3, i.e. the emitter, via a first contact hole16. In addition, another part of the first interconnection layer8electrically contacts the first semiconductor region2, i.e. the collector, via a second contact hole15. In this region, the first interconnection layer8serves as a bit line that addresses the emitter and the collector.

A second dielectric layer9is present on the first dielectric layer5and on the first interconnection layer8. A second interconnection layer10is present on the second dielectric layer9. Said second interconnection layer10is electrically connected to the first interconnection layer8by means of a third contact hole18. A third dielectric layer11is provided on the second interconnection layer10. A third interconnection layer12is provided on the third dielectric layer11, said third interconnection layer being structured such that it serves as the first electrode of the coupling capacitor. The third interconnection layer12is provided with a fourth dielectric layer13. A fourth interconnection layer14, which is structured such that it serves as a control electrode of the floating gate transistor, is embedded in the fourth dielectric layer13. In addition, the fourth interconnection layer14serves as the second electrode of the coupling capacitor. By suitably structuring the fourth interconnection layer14, it is achieved that said interconnection layer additionally serves as a word line for controlling the control electrode.

Outside the area of the non-volatile memory, the first interconnection layer8and the second interconnection layer10can be structured such that they form further components of the arrangement for controlling the display device. Such a component may be, for example, a column decoder for an array of non-volatile semiconductor memories, an input-output chip (I/O chip), a SRAM (Static Random Access Memory) memory cell, a ROM (Read-Only Memory) memory cell or a logic component.

FIG. 3is a diagrammatic cross-sectional view taken along the intersection line B-B′ of the embodiment of an EPROM memory cell shown inFIG. 1. As is shown inFIG. 3, the third interconnection layer12is electrically connected, via a fourth contact hole21, to the second interconnection layer10, via a fifth contact hole18to the first interconnection layer8, and via a sixth contact hole20to the polysilicon layer6of the floating gate transistor. Besides, the fourth contact hole21connects the third interconnection layer12to the second interconnection layer10, the fifth contact hole18connects the second interconnection layer10to the first interconnection layer8, and the sixth contact hole20connects the first interconnection layer8to the polysilicon layer6. The third interconnection layer12and the polysilicon layer6form the floating gate of the floating gate transistor. The contact hole19establishes electric contact between the fourth interconnection layer14and a part of the third interconnection layer12.

The dielectric layers5,9,11,13preferably comprise SiO2, Si3N4or a combination of these materials, and are preferably provided by means of, for example, PECVD (Plasma-Enhanced Chemical Vapor Deposition) processes. The interconnection layers8,10,12,14as well as the electroconductive contact holes15,16,18,19,20,21comprise preferably Ti/TiN/Al(Cu) as the electroconductive material. Alternatively, the interconnection layers8,10,12,14may each comprise different electroconductive materials.

In a further possible embodiment the EPROM memory cell only comprises two interconnection layers, one interconnection layer serving as the first electrode of the coupling capacitor, and the second interconnection layer serving as the control electrode and the second electrode of the coupling capacitor, and two dielectric layers.

Programming, erasing and reading an EPROM/EEPROM memory cell in accordance with the invention takes place by means of customary processes and methods.