Clock generator with programmable non-overlapping-clock-edge capability

A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay is adjusted by programming the on-chip clock generator using either hardware and/or software programming. In hardware programming, the amount of delay adjusted by physically altering the composition of delay elements in the on-chip clock generator. In software programming, the delay is adjusted using software commands to control the operation of delay elements in the on-chip clock generator, or to select the paths that delay the signals.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a programmable clock generator for integrated circuits, very large scale integrated circuits (VLSI), and ultra large scale integrated circuits (ULSI). More particularly, the present invention relates to a programmable clock generator for selecting optimal non-overlapping clocking signals for controlling elements on a chip.

2. Related Art

Most microprocessor chips operate as control driven, synchronous sequential systems. This means the sequence of operations in the system is synchronized by a master clock signal (usually an external clock). This clock signal is usually one of the forms shown inFIG. 1; which illustrates a square wave with a 50% duty cycle.

The master clock signal allows system operations to occur at regularly spaced-intervals. In particular, operations on the chip are made to take place at times when the clock signal is making a transition from low-to-high or from high-to-low; rising edge102or falling edge104, respectively.

Many microprocessor chips have their timing controlled by two or more related clock signals generated by an on-chip clock generator based on the master clock signal.FIG. 2Aillustrates one such combination utilizing two clock signals identified by φ1and φ2. This clocking arrangement provides four different edges and three different states per period, compared to only two edges and two states per period provided with a single clock signal as shown in FIG.1.FIG. 2Billustrates examples of the three possible states for clock signals φ1and φ2. For elements on the chip to function properly, it is important that edges of clock signals φ1and φ2are non-overlapping. If the edges overlap there will be more restrictions on data transfer and signal hand shaking.

Additionally, it is equally important that non-overlapping clock edges be evenly distributed to all corners of a chip regardless of the distance which those signals must travel. As chip size increases, clock signals φ1and φ2have to travel greater distances throughout the chip. This causes clock signals φ1and φ2to become degraded. As distances increase, rising edges202,206and failing edges204,208may become obscured (experience phase shifts and increases in transition times) and can overlap. This phenomenon, sometimes referred to as clock skew, is caused by a number of factors, including: loading, unwanted noise, coupling, capacitance, resistance, inductance and other debilitating effects.

To account for these factors, designers must separate the rising and falling edges202,204,206,208of different clock signals (i.e., φ1and φ2) with a large enough margin of time to allow for clock skew. For instance, failing edge204and rising edge206must be separated by a minimum temporal distance or amount of time (T) to avoid overlapping states; especially for level-triggering operations in metal-oxide-silicon (MOS) technology. The larger T is, the less likely the chip will fail due to overlapping signals caused by skewing. The wide range of operating environments to which the chip(s) may be subject must be considered in selecting T. Therefore, to provide an adequate margin, manufacturers are forced to select T large enough to provide functionality in a worst-case environment. However, a large T is a significant cycle time constraint. Therefore chip design is not optimized for each environment.

To illustrate this, consider current chip design practices that must account for clock skew by designing a chip with a minimum safety distance T between signals against worst-case conditions. Once T is selected the chip is manufactured and tested. If the chip designer selected a clock speed that has insufficient non-overlapping time, the chip will not function due to overlapping states for some circuits located on the chip. When a chip runs properly, chip designers assume they have chosen the correct frequency, clock states; rise and fall times, and non-overlapping time T. However, chip designers do not know whether a faster clock speed or a smaller T are possible. To find out, chip manufacturers must build entirely new chips with different process parameters, which is inefficient and expensive.

Presently, no programming or tweaking can be performed after a chip is finalized. It is possible to have an on-chip clock generator running at different clock frequencies than external crystal oscillators, but the non-overlapping time of the clock edges generated by the clock generator is fixed by circuit hardware. Therefore, what is needed is a flexible system and method of programming an on-chip clock generator at the manufacturing stage to achieve adjustable as well as optimal non-overlapping times T between clock edges.

At the post-manufacturing stage, environmental conditions, such as heat and cold can also affect clock skewing. If a chip is manufactured under laboratory conditions, it may function properly. However, temperature changes may cause the chip to malfunction due to skewed clock signals. Therefore, what is needed is an on-chip clock generator that can be dynamically programmed to select non-overlapping times T to account for environmental fluctuations while the chip is in an operational environment, such as a processor chip operating in a computer.

SUMMARY OF THE INVENTION

The present invention is directed to a system and method for providing programmable non-overlapping clock generation on a chip. The present invention includes four main embodiments. The first embodiment is directed to the overall operation of an on-chip clock generator. The second embodiment is directed to a hardware programmable clock generation system and method. The third embodiment is directed to a software programmable clock generation system and method. The fourth embodiment is directed to a combination of all three embodiments.

The programmable on-chip clock generator provides two phases of a system clock with non-overlapping edges. The programmability of the clock generator provides flexibility during chip fabrication, and when a chip is functioning in a operational environment.

During the manufacturing phases of chip production, characteristics of the on-chip clock generator are altered to ensure the edges of the two generated clocks do not overlap. This allows the manufacturer to optimize the performance of the chip while the chip is undergoing initial production testing. This feature obviates the need to perform costly and time consuming trial-and-error design and redesign of on-chip clock generators.

Additionally, the present invention provides a technique for optimizing the performance of the on-chip clock generator after the chips have left the manufacturing environment. One feature of the present invention is the ability to adjust clock generation dynamically to account for climatic changes in an operational, or other post-production, environment. This allows chips to be manufactured with wider tolerances and allows operation of the chip to be optimized when the chip is in the operational environment.

Adjustments to the on-chip clock generator during the manufacturing phase are referred to as hardware programming because the manufacturer alters the physical composition of the clock generator. Adjustments to the on-chip clock generator once the chip is fabricated and in the operational environment are referred to as software programming. This terminology reflects the fact that through the use of software commands, the characteristics of the on-chip clock generator can be adjusted to compensate for changes in the operating environment. Programming capability in both cases is accomplished by adding or subtracting delay elements in feedback paths within the clock generator circuit.

In the drawings the left-most digit of a reference number identifies the drawing in which the reference number first appears.

DETAILED DESCRIPTION OF THE INVENTION

I. General Overview

A. Brief Overview

The present invention is directed to a system and method for providing non-overlapped clock generation on a chip. The present invention includes four main embodiments. The first embodiment is directed to the overall operation of an on chip clock generator. The second embodiment is directed to a hardware programmable clock generation system and method. The third embodiment is directed to a software programmable clock generation system and method. The fourth embodiment is directed to a combination of the first three embodiments.

These embodiments of the present invention are discussed in the following sections.

FIG. 3illustrates a high level block diagram of an environment301in which the present invention operates. Environment301may be a wafer containing hundreds of chips at a fabrication/testing stage or a computer in a user environment. As illustrated, environment301includes an external clock generator302and a chip304. In a preferred embodiment, external clock generator302is a crystal oscillator, which produces a signal similar to that shown in FIG.1.

Chip304has circuit elements310. Many computers require more than one processor chip. As shown inFIG. 3, an optional co-processor or peripheral chip305may be coupled to chip304.

Chip304also has an internal clock generator308, which provides multiple clock signals to elements310. In a preferred embodiment clock generator308provides two clock signals, φ1and φ2; similar to FIG.2A. To ensure that active portions of clock signals φ1and φ2are non-overlapping, clock generator308is programmed to achieve optimal non-overlapping clock generation. Accordingly, clock generator308provides a plurality of programmable non-overlapping times between clock signals φ1and φ2. In the preferred embodiment, clock generator308provides the option of selecting between 0.5 ns, 2.5 ns and 4.5 ns of non-overlapping time between clock signals φ1and φ2shown as T in FIG.2A. In alternative embodiments, T must be less than the period of CLKIN401. Furthermore, for a 50% duty cycle T should be less than the period of CLKIN/2. If this condition is not met, the circuit may chop out clocks.

This flexibility permits adjustments to clock generation if there is not enough holding time between clock edges by increasing T between clock signals φ1and φ2. On the other hand, if there is too much holding time between clock signals φ1and φ2, T can be decreased. In either case, “tweaking” can be performed while the chip is being tested (during the manufacture stage) without expensive and costly changes to the clock design.

Adjustments to clock generator308can also be performed in an operational environment (product usage stage). As a result, clock generator308can be adjusted for climatic changes which can affect whether clock signals φ1and φ2are non-overlapping.

II. Clock Generator

FIG. 4illustrates a high level block diagram of clock generator308. Clock generator308includes an input waveform stabilizer402, a clock-to-clock non-overlapping time adjuster406, and a clock driver410having a two phase output φ1and φ2(CLK OUT411).

Operation of clock generator308is generally illustrated in the flow chart shown in FIG.5. In describing the operation of clock generator308reference will be made toFIGS. 2-8.

Referring now toFIGS. 4 and 5, in a step502, clock generator308receives an external clock signal401from external clock302shown as “CLKTN”401(as shown in FIG.4). In a step504, input waveform stabilizer02stabilizes CLKIN401. Waveform stabilizer402reshapes CLKIN401into a square wave (CLK405) because CLK1N401tends to be distorted due to input jitter, noise from ground bounce and coupling. In the preferred embodiment, waveform stabilizer402is a Schmitt trigger. The structure and operation of a Schmitt trigger are well known to those skilled in the art.

In a step508, CLK405is received by clock-to-clock non-overlapping time adjuster406, and multiple signals with non-overlapping active phases407are generated with adjustable delay between edges. The clock generator308can be programmed to provide desired holding times between clock edges.

There are two types of programming that can occur: hardware and software. Hardware programming normally occurs during the testing stages of a chip and involves altering the chip physically. This process is typically irreversible. Software programming normally occurs while a chip is functioning in an operational environment. Software programming is dynamic, allowing adjustments to delay time T between clock edges without physically altering the chip. Programming capability in both cases is accomplished by adding or subtracting delay elements in feedback paths within the clock generator circuit (to be described).

1. Hardware Programming

FIG. 6Aillustrates the hardware embodiment of a clock to clock non-overlapping time adjuster406according to the present invention. Referring toFIG. 6A, clock-to-clock non-overlapping time adjuster406includes logic gates602,603, delay element(s)604and drivers622,624.

In the preferred embodiment, logic gates602and603are NOR gates and delay elements604are inverters. Other logic elements can be substituted for the ones described in the preferred embodiment. For instance, inverter604can be replaced with NAND gates having inputs tied together. Additionally, delay elements604can be any device (i.e., resistors) that delay a signal.

Delay elements604, form delay paths606A,606B (generally606) which govern the amount of delay between clock signal φ1and clock signal φ2. Adjusting the length of delay paths606by adding or subtracting delay elements604coupled to logic gates602,603, increases or decreases the amount of time T between edges of clock signals φ1and φ2. Typically, a chip designer will include more delay elements604than needed to afford latitude in the selection of possible delay times. Selection from a plurality of pre-planned delay paths606provide a corresponding plurality of non-overlapping optional times between clock edges.

FIG. 6Billustrates clock-to-clock non-overlapping time adjuster406with generic delay paths or delay segments τ1and τ2to delay clock signals φ1and φ2. Delay segments τ1and τ2are equivalent to delay paths606shown in FIG.6A. Changing the amount of delay allows the amount of time between edges of φ1and φ2to be adjusted. The amount of delay introduced in these segments τ1and τ2is programmable by adding or deleting delay elements604.

Referring toFIG. 6B, time adjuster406operates as follows. An input clock signal (CLK)405passes through inverter609to form inverted clock signal601(NOTCLK601). CLK405and NOTCLK601are used to form two new clock signals φ1and φ2. CLK405is an input signal to NOR gate602along with a delayed signal φ2. NOTCLK601is an input signal to NOR gate603along with delayed φ1signal.

FIG. 6Cis a timing diagram illustrating the operation of the clock to clock non-overlapping time adjuster406of the present invention. Referring toFIGS. 6B and 6C, the technique of the clock to clock non-overlapping time adjuster406will now be described. Note, gate delays, which are shown as t inFIG. 6C, are negligible. Note: t=gate delay; τ=delay of a delay element; and T=t+τ.

As shown inFIG. 6C, in the beginning of region1, clock405transitions to a logic high state, which forces951to the logic low state. A delay timer τ1later, delayed φ1transitions to a low state. Since NOTCLK601is at a logic low state, this transition forces φ2to transition to a logic high state.

As a result of delay τ1, the rising transition of φ2lags behind the falling transition of451by the amount of τ1plus any gate delay times t. The amount of time separating the falling transitions of φ1from the rising transitions of φ2is controlled by adjusting τ1. If the circuit designer wishes to increase the clock frequency, τ1is programmed to a lesser amount. On the other hand, if the circuit operation is hampered by overlapping falling and rising transitions of φ1and φ2, respectively, τ1is increased until this problem is rectified. In this manner, the circuit is optimized by increasing the clock frequency to the maximum permissible level without the transitions overlapping.

In a similar fashion, the falling edges of φ2are separated from the rising edges of φ1by controlling the amount of delay programmed into τ2. If the delay in τ2is increased, the separation between the falling edges of φ2and the rising edges of τ1is increased, and if the delay in τ2is decreased, the separation is decreased. Therefore, the circuit can be further optimized by adjusting the time T between the falling edges of φ2and the rising edges of φ1.

An example of hardware programming is illustrated in FIG.7.FIG. 7represents a portion of delay path606of FIG.6A. Programming is accomplished by closing or opening switches707,711. When switch707is closed, nodes720and722are shorted together. Additionally, by opening switch711delay elements604A,604B are completely dropped out of the circuit or “shorted out.” Thus, closing switch707and opening switch711, bypasses delay elements604A,604B and decreases the amount of path delay for a signal. Opening switch707and closing switch711increases the amount of path delay for a signal that passes through delay path606.

There are a number of ways to close or open switches707,711. Such techniques include fuse/anti-fuse processing, laser burning, ion beam milling and other techniques. In the preferred embodiment laser “zap” burning technique is used to open/close switches707,711.

2. Software Programming

FIGS. 8A and 8Bare logic level circuit diagrams of a clock-to-clock non-overlapping time adjuster406according to a software embodiment of the present invention.FIGS. 8A and 8Bare similar toFIG. 6with the exception of the manner in which the delay elements τ are implemented. In other words, the software embodiment operates in a manner similar to that of the hardware embodiment described above. However, in the software embodiment, the delay times τ1and τ2are not fixed at the time of fabrication as they are in the hardware embodiment. In the software embodiment, the amount of delay chosen for τ1and τ2is selected using software, and can be changed as required to compensate for changes in operating conditions or other operational parameters.

FIG. 8Aillustrates a software embodiment using path selection to adjust delay times τ1and τ2. Referring toFIG. 8A, multiple paths (generally822) are established on the chip, each having different propagation delay times. The paths822are duplicated for τ1and τ2. Delay paths822can be implemented using a multiplicity of delay elements.FIG. 8Ashows delay paths822made up of inverters604. If inverters are chosen, an even number must be used in each path822for proper operation.

The manner of path selection will now be described. Control words850A,850B are generated and sent to demultiplexers824A,824B selecting the paths to be followed. Control words850A,850B are also sent to multiplexers825A,825B for selecting paths to be followed. Control words850A,850B command demultiplexers824A,824B and multiplexers825A,825B to route the signals output from NOR-gates826A,826B, respectively, through a specified path822. The amount of delay, therefore, varies depending on the propagation delay of the selected path822.

FIG. 8Billustrates a software embodiment using path-length selection to adjust delay times τ1and τ2. In this embodiment paths842A,842B are made up of strings of delay elements846and multiple connection points848. Control words850are sent to switches844A,844B. The control words850A,850B ‘command’ switch844A,844B, respectively to select the signal at one of connection points848along the string. The farther along the string connection point848is chosen, the longer the delay time will be. Switches844A,844B are multiplexers.

Strings842A,842B are shown inFIG. 8Bas being implemented using inverters as the delay elements846. If inverters are used, the paths must be chosen such that only an even number of inverters can be selected to make up the delay of the signal. A number of other elements846can also be chosen to make up delay paths842A,842B.

The present invention can be implemented using a combination of the hardware and software embodiments described above. For example, the delay strings can be first adjusted to a maximum delay time as described in the hardware embodiment. Then, fine tuning can be accomplished in the operational environment using the software embodiments described above.