Systems and methods for interrupt distribution

A data processing system configured to execute a plurality of threads includes a plurality of domains and a plurality of domain interrupt controller circuits, each domain interrupt controller corresponding to a domain of the plurality of domains. Each domain interrupt controller includes an interrupt selection circuit configured to select an interrupt request from a set of interrupt requests received by the interrupt selection circuit and determine an interrupt vector for the selected interrupt request, a programmable domain-thread storage circuit configured to store an enable indicator corresponding to each thread of the plurality of threads in which the enable indicator for each corresponding thread indicates whether or not the corresponding domain is permitted to route interrupt vectors to the corresponding thread, and a routing circuit configured to route the interrupt vector to a selected thread of the plurality of threads which is selected based at least in part on the enable indicators.

BACKGROUND

Field

This disclosure relates generally to semiconductor processing systems, and more specifically, to distributing interrupts in multi-core or multi-thread microprocessor systems.

Related Art

Real-time operating systems require very short interrupt service times from request to completion. In a device, the number of interrupt sources could be very large compared to the number of cores and threads that are implemented. In single core devices, an interrupt priority tree can be implemented for that core to select the highest priority interrupt source (IRQ) to be serviced. With an increase of integrated cores within a single device, a priority tree was associated with each core. When thread architecture was introduced, the number of priority trees scaled by the number of cores times the number of threads per device. Such an implementation had two major disadvantages. First, the architecture is not scalable and would cause a significant increase in power and area to implement the required uniform interrupt routing from all sources to all the cores and thread. Second, the software had to pre-select the interrupt sources for the cores and threads without any knowledge of the real-time load on the core while the application is running that would potentially impact interrupt service latency.

DETAILED DESCRIPTION

Systems and methods for automatic interrupt distribution in a multi-core and/or multi-threaded processor system are disclosed. Each interrupt is assigned to a domain. In addition, one or more threads are assigned to a given domain. Interrupt requests go to a domain priority tree. Each interrupt request is routed to a thread[m] based on a programmable domain thread register (DTR) made up of thread[m] select bits. Each domain priority tree calculates the highest priority interrupt request for that domain. The outputs of the domain priority tree (vector_out[m] and priority_out[m]) are the highest priority interrupt request queue associated with each thread. When more than one thread is assigned to a given domain, a round-robin algorithm routes the interrupt request to one of the threads associated with the domain as the threads are or become available. The routing logic can be implemented in hardware and reduces the need to have a one-to-one correspondence between domain and thread, thus reducing the overall system costs. Further, the routing hardware automatically balances the load of the interrupt requests between peripherals and threads.

FIG. 1is a block diagram of an embodiment of a multi-core, multi-thread microprocessor system100in which an interrupt controller104can be used to manage interrupt requests from various different internal and external interrupt sources102, such as timers, serial input/output, analog to digital converters, keypad and switch inputs, and changes in logic levels on pins, among others. An interrupt is a communication process in which an internal or external device issues an interrupt request to a processor device106. Processor device106checks for interrupt requests, and if an interrupt request is present, resets the interrupt, saves the return address, redirects to the memory location associated with the interrupt, handles the interrupt request, and then returns to processing at the return address.

Microprocessor system100includes one or more processor devices106that each include one or more processing cores108each capable of executing program instructions of one or more threads110, one or more memory devices112(e.g., random access memory (RAM), cache), and interrupt handler114. Processor device102can include other components that are not shown, such as input/output handlers, a memory management unit, communication busses, and bus interface units (BIU), among others. Processing cores108can access instruction data and operand data memory device112, I/O handlers, or other sources. Data resulting from the execution of the instructions can be stored in memory device112or provided to an I/O device. Interrupt handler114includes interrupt service routines (ISRs) that attend to the interrupt requests by clearing interrupt flags and save register contents that may be affected by execution of the ISR. Interrupt controller104sends an interrupt vector that includes a pointer to a routine that will handle the interrupt in interrupt handler114.

Referring toFIGS. 1 and 2,FIG. 2is a block diagram of interrupt controller104for multi-core, multi-thread microprocessor system100ofFIG. 1in accordance with selected embodiments of the invention. In the example shown, interrupt controller104includes priority select registers202, one or more domain interrupt controller circuits204, and thread routing circuit220for one or more threads110being executed by one or more processing cores108. Domain interrupt controller circuit204includes interrupt selection circuit206, programmable domain-thread storage circuit212, thread select circuit214, and interrupt vector and priority selection circuit216. Interrupt controller104further includes thread routing circuit220with a multiplexer218. Together, programmable domain-thread storage circuit212, thread select circuit214, interrupt vector and priority selection circuit216, and thread routing circuit220are referred to as a “router” herein. In the example shown, there are N domains and M threads, with N being a value less than M. Each domain has a corresponding domain interrupt controller circuit204, and each thread has a corresponding thread routing circuit220.

Priority select registers (PSRs)202are coupled for bi-directional access with interrupt sources102via a register access bus. Information regarding the priority, type, source, and which interrupts can be handled by threads110ad interrupt handlers114associated with each domain interrupt controller circuit204can be provided via a programming interface to PSRs202or other suitable mechanism, for example, from interrupt sources102directly. Other suitable information and attributes of the interrupts can be included in PSRs202. PSRs202provide domain enable indicators (ENABLE(N)) and interrupt source priority to each domain interrupt controller circuit204. The domain enable indicators can be implemented as bits in a word, with each bit representing an interrupt source. Each domain can be associated with a word of domain enable indicators, with the bits being set to indicate whether or not a particular domain can handle a particular interrupt. Interrupts can be set up as high priority or low priority, or other suitable priority level. The priority indicators can be implemented as bits in one or more words, with one or more of the bits representing whether the priority of an interrupt source is low, high, or something in-between.

Information for PSRs202such as priority and domain enable indicators can be programmed/initialized via register access bus201when system100is configured, and replaced or updated periodically, depending on interrupt sources102connected to interrupt controller104. The PSR information can be stored in non-volatile memory accessible by system100during power-up initialization. Alternatively, PSRs202may include non-volatile memory configured to store the interrupt information indefinitely.

Data processing system100can include a resource domain controller (not shown) with information that groups various resources, such as bus masters and peripherals, into common domains. Each group of resources can be referred to as a domain interrupt controller circuit204that include threads110executing on processing cores108and one or more peripheral devices (shown as interrupt sources102) that issue interrupt requests. Instead of statically assigning threads110to interrupt sources102, interrupt controller104dynamically assigns interrupt requests to available threads110based on domain interrupt controller circuits204that are enabled to handle a particular type of interrupt and interrupt priority, as further described below.

The interrupt source priority and enable information from PSRs202is provided to interrupt selection circuit206from priority select registers202. Interrupt selection circuit206also receives interrupt requests from interrupt sources102. Information regarding an interrupt vector associated with each interrupt request can be programmed in interrupt selection circuit206or provided to interrupt selection circuit206by other suitable means. An interrupt vector is a location in interrupt handler114to which processing will be directed when an interrupt request is received. The location specified by an interrupt vector may depend on the type of interrupt, the priority of the interrupt, and/or other suitable criteria. The interrupt vector and corresponding interrupt priority is provided as input to interrupt vector and priority selection circuit216from interrupt selection circuit206for each domain interrupt controller circuit204.

Domain-thread storage circuit212can store information regarding which thread110can receive which interrupt, and can be programmed via register access bus211or other suitable method. Information regarding which threads are configured to handle which interrupt requests can be programmed in domain-thread storage circuit212via register access bus211or provided to domain-thread storage circuit212by other suitable means. Thread select circuit214is configured to receive information regarding which thread can receive which interrupt from domain-thread storage circuit212and to provide which thread is enabled for each interrupt in a particular domain to interrupt vector and priority selection circuit216. Thread select circuit214also provides a thread select signal to multiplexer218to allocate a corresponding interrupt vector and interrupt priority to each thread routing circuit220.

Interrupt vector and priority selection circuit216receives interrupt vector and priority information for corresponding domains from interrupt selection circuit206. Thread select circuit214selects the next available thread to handle a received interrupt request based on the enabled thread information from domain-thread storage circuit212. The selected thread information for each interrupt is provided to interrupt vector and priority selection circuit216from thread select circuit214. Interrupt vector and priority selection circuit216provides interrupt vectors and a corresponding priority indicator for each interrupt vector to multiplexer218for each domain204to each thread routing circuit210. Typically, the interrupt with the highest priority is selected for an available thread that is capable of handling the particular type of interrupt, however, other selection criteria can be used. Thread routing circuit210can include a connection such as a bus between a domain (n) and each thread (m), to provide interrupt vectors and priorities from each domain (e.g. vector [n][0:M−1] and priority [n][0:M−1]) to available threads110(e.g., vector [0:N−1][m] and priority [0:N−1][m]) via multiplexer218.

Interrupt controller104provides load balancing for servicing interrupts, allowing interrupts to be serviced by any available thread110associated with each domain interrupt controller circuit204. Interrupts are programmed to each domain interrupt controller circuit204, and each domain interrupt controller circuit204outputs the highest priority interrupt. An interrupt can be associated with more than one domain interrupt controller circuit204, and one or more threads110can be associated with each domain interrupt controller circuit204. Domain-thread storage circuit212indicates which threads110can receive an interrupt for the particular domain interrupt controller circuit204. Thread select circuit214synchronizes allocation of interrupts in domain interrupt controller circuits204with threads110that are available to handle the interrupts. Multiplexer218provides an interrupt vector and interrupt priority to a corresponding thread110based on a control signal from thread select circuit214.

Referring toFIGS. 1 and 3,FIG. 3is a timing diagram of an example of interrupt distribution of five interrupt requests routed to four threads110in the microprocessor system ofFIG. 1. At time T1, five interrupt requests (IRQ[0:4]) are received by interrupt controller104. First interrupt request IRQ[0] is assigned to first thread IRQ-T[0] at time T2, second interrupt request IRQ[1] is assigned to second thread IRQ-T[1] at time T3, third interrupt request IRQ[2] is assigned to third thread IRQ-T[2] at time T4, and fourth interrupt request IRQ[3] is assigned to fourth thread IRQ-T[0] at time T5. The remaining fifth interrupt request IRQ[4] is suspended until one of threads IRQ-T[0:3] becomes available.

At time T6, first thread IRQ-T[0] finishes processing first interrupt request IRQ[0]. After the next clock cycle at time T7, first thread IRQ-T[0] begins processing fifth interrupt IRQ[4]. At time T8, second and third threads IRQ-T[1:2] finish processing respective second and third interrupt requests IRQ[1:2]. At time T9, second and third threads IRQ-T[1:2] become available to process subsequent interrupt requests (not shown). At time T10, first thread IRQ-T[0] finishes processing fifth interrupt request IRQ[4]. At time T11, fourth thread IRQ-T[3] finishes processing fourth interrupt request IRQ[3] and is also now available to process a subsequent interrupt request. Note that although there were not enough threads available to process all of the interrupts request simultaneously, the remaining fifth interrupt request was serviced one clock cycle after the first thread finished processing the first interrupt request. Any available thread associated with a particular domain and capable of handling a particular interrupt request can be assigned to service the interrupt request, thereby reducing the amount of time that may otherwise be required to wait if the fifth interrupt request had been statically assigned to another thread that did not become available as soon as the first thread.

By now it should be appreciated that there has been provided, in some embodiments, a data processing system configured to execute a plurality of threads (M threads) can comprise a plurality of domains (N domains), wherein the data processing system is configured to execute a plurality of software codes each having data portions that are isolated in a domain of the plurality of domains and a plurality of domain interrupt controller circuits (204). Each domain interrupt controller circuit can correspond to a corresponding domain of the plurality of domains. Each domain interrupt controller circuit can comprise an interrupt selection circuit (206) configured to select an interrupt request from a set of interrupt requests received by the interrupt selection circuit and determine an interrupt vector for the selected interrupt request, and a programmable domain-thread storage circuit (212) configured to store an enable indicator corresponding to each thread of the plurality of threads. The enable indicator for each corresponding thread can indicate whether or not the corresponding domain is permitted to route interrupt vectors to the corresponding thread. A routing circuit (214and216) can be configured to route the interrupt vector to a selected thread of the plurality of threads which is selected based at least in part on the enable indicators.

In another aspect, the set of interrupt requests can be provided by a plurality of interrupt sources.

In another aspect, the data processing system can further comprise the plurality of interrupt sources.

In another aspect, the data processing system can further comprise priority status storage circuit configured to store a priority level of each interrupt source (PRI) and configured to store, for each domain of the plurality of domains, an enable bit per interrupt source (enable[N]).

In another aspect, in each domain interrupt controller circuit, the interrupt selection circuit can be configured to select an interrupt request based on the priority level of each interrupt source and the enable bit per interrupt source for the corresponding domain.

In another aspect, the data processing system can further comprise a plurality of processor cores (108), in which each processor core is configured to execute one or more threads of the plurality of threads.

In another aspect, the data processing system can further comprise a processor core configured to execute the plurality of threads.

In another aspect, the enable indicators of the programmable storage circuit in each domain interrupt controller circuit can be configured to be dynamically updated during operation of the data processing system.

In another aspect, the routing circuit of each domain interrupt controller circuit can comprise a connection (216and218) between the corresponding domain (n) and each thread (m) of the plurality of threads (e.g. (vector[n][0to M−1]).

In another aspect, the routing circuit of each domain interrupt controller circuit can receive status information from each thread of the plurality of threads in which the selected thread is based on the enable indicators and the received status information from each thread.

In other embodiments, a method in a data processing system having a plurality of domains and configured to execute a plurality of threads wherein the data processing system is configured to execute a plurality of software codes each having data portions that are isolated in a domain of the plurality of domains, can comprise programming a domain-thread storage circuit corresponding to each domain of the plurality of domains with an enable indicator corresponding to each thread of the plurality of threads. The enable indicators of the domain-thread storage circuit of each corresponding domain can indicate a set of threads of the plurality of threads to which interrupt vectors are permitted to be routed from the corresponding domain. In one domain of the plurality of domains, a first interrupt request from a set of received interrupt requests can be selected. A first interrupt vector for the selected first interrupt request can be determined. Based on the enable indicators corresponding to the one domain, a first thread to receive the selected interrupt request can be selected. The first interrupt vector can be routed to the selected thread.

In another aspect, the method can further comprise, in the one domain, selecting a second interrupt request from the set of received interrupt requests, and determining a second interrupt vector for the selected second interrupt request. Based on the enable indicator corresponding to the one domain, a second thread to receive the selected second interrupt request can be selected. The second interrupt vector can be routed to the second selected thread.

In another aspect, the set of received interrupt requests can be received from a plurality of interrupt sources, and selecting the first interrupt request can be performed based on a priority level of each interrupt source and an enable bit per interrupt source for the one domain.

In another aspect, the method can further comprise programming the domain-thread storage circuit corresponding to the one domain with a different set of enable indicators such that the one domain can be permitted to route interrupt vectors to a different set of threads of the plurality of threads.

In another aspect, the data processing system can include a plurality of cores each configured to execute a set of threads of the plurality of threads.

In another aspect, the method can further comprise receiving status information from each thread of the plurality of threads, wherein the selecting the first thread can be selected based on the enable indicator corresponding to the one domain and the received status information from each thread.

In further embodiments, a data processing system configured to execute a plurality of threads (M threads) can comprise a plurality of domains (N domains). The data processing system can be configured to execute a plurality of software codes each having data portions that are isolated in a domain of the plurality of domains. A plurality of processor cores can each be configured to execute a set of threads of the plurality of threads. A plurality of domain interrupt controller circuits (204) can each correspond to a corresponding domain of the plurality of domains. Each domain interrupt controller circuit can comprise an interrupt selection circuit (206) configured to select an interrupt request from a set of interrupt requests received by the interrupt selection circuit and determine an interrupt vector for the selected interrupt request. A programmable domain-thread storage circuit (212) can be configured to store an enable indicator corresponding to each thread of the plurality of threads. The enable indicator for each corresponding thread can indicate whether or not the corresponding domain is permitted to route interrupt vectors to the corresponding thread. A routing circuit (214and216) can be configured to route the interrupt vector to a selected thread of the plurality of threads which is selected based at least in part on the enable indicators. The routing circuit can include a connection (216and218) between the corresponding domain (n) and each thread (m) of the plurality of threads (e.g. (vector[n][0 to M−1]).

In another aspect, the data processing system can further comprise a plurality of interrupt sources. The set of interrupt requests can be provided by a plurality of interrupt sources

In another aspect, the routing circuit of each domain interrupt controller circuit can receive status information from each thread of the plurality of threads in which the selected thread can be based on the enable indicators and the received status information from each thread.

In another aspect, the enable indicators of the programmable storage circuit in each domain interrupt controller circuit can be configured to be dynamically updated during operation of the data processing system.

Because the apparatus implementing the present disclosure is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present disclosure and in order not to obfuscate or distract from the teachings of the present disclosure.

The term “thread,” as used herein, is defined as a sequence of software instructions designed for execution on a computer system. A thread, or computer software program or code, may include a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system. The threads or software codes can have code and data portions that are grouped in a resource domain204(FIG. 2).

Also for example, in one embodiment, the illustrated elements of system100are circuit located on a single integrated circuit or within a same device. Alternatively, system100may include any number of separate integrated circuits or separate devices interconnected with each other. For example, memory112may be located on a same integrated circuit as processor device106or on a separate integrated circuit or located within another peripheral or slave discretely separate from other elements of system100. Interrupt handler114and I/O circuit may also be located on separate integrated circuits or devices. Also for example, system100or portions thereof may be soft or code representations of physical circuit or of logical representations convertible into physical circuit. As such, system100may be embodied in a hardware description language of any appropriate type.

In one embodiment, system100is a computer system such as a personal computer system. Other embodiments may include different types of computer systems. Computer systems are information handling systems which can be designed to give independent computing power to one or more users. Computer systems may be found in many forms including but not limited to mainframes, minicomputers, servers, workstations, personal computers, notepads, personal digital assistants, electronic games, automotive and other embedded systems, cell phones and various other wireless devices. A typical computer system includes at least one processing unit, associated memory and a number of input/output (I/O) devices.

A computer system processes information according to a program or software code and produces resultant output information via I/O devices. A program is a list of instructions such as a particular application program and/or an operating system. A computer program is typically stored internally on computer readable storage medium or transmitted to the computer system via a computer readable transmission medium. A computer process typically includes an executing (running) program or portion of a program, current program values and state information, and the resources used by the operating system to manage the execution of the process. A parent process may spawn other, child processes to help perform the overall functionality of the parent process. Because the parent process specifically spawns the child processes to perform a portion of the overall functionality of the parent process, the functions performed by child processes (and grandchild processes, etc.) may sometimes be described as being performed by the parent process.