Multilevel class-D power stage including a capacitive charge pump

An amplifier comprises eight transistors: the first coupled to a linked node and to a positive output node, the second coupled to the linked node and to a negative output node, the third coupled to the positive output node and a common potential, the fourth coupled to the negative output node and the common potential, the fifth coupled to a battery node, the sixth coupled to the fifth transistor and to the positive output node, the seventh coupled to the battery node, and the eighth coupled to the seventh transistor and to the negative output node. The amplifier also includes a charge pump to convert the battery voltage to an increased voltage on the linked node. The charge pump includes capacitors and operates at a lower frequency in lower power mode and a higher frequency in higher power mode to increase power provided to the linked node.

BACKGROUND

In some amplifier applications, a “class-D” amplifier architecture is used. For example, a class-D amplifier may be used in battery-powered audio applications. In some such systems, a multi-level class-D amplifier coupled to a charge pump, which increases a voltage from a power supply and may be used to deliver higher power to a load (e.g., a speaker). In a multi-level class-D amplifier, the pulse width modulated output may switch between three voltage levels. The three voltage levels may be ground, a battery voltage, and a linked voltage from the charge pump. Some class-D amplifier circuits may include control logic to operate the charge pump at different frequencies and increase the power available to the load.

SUMMARY

An amplifier comprises eight transistors: the first coupled to a linked node and to a positive output node, the second coupled to the linked node and to a negative output node, the third coupled to the positive output node and a common potential, the fourth coupled to the negative output node and the common potential, the fifth coupled to a voltage source node, the sixth coupled to the fifth transistor and to the positive output node, the seventh coupled to the voltage source node, and the eighth coupled to the seventh transistor and to the negative output node. In some examples, the amplifier also includes a charge pump configured to convert the voltage on the voltage source node to an increased voltage on the linked node. The charge pump includes capacitors and is configured to operate at a first, lower frequency for a first, lower power mode of operation and at a second, higher frequency for a second, higher power mode of operation.

The amplifier includes a controller configured to generate control signals for the eight transistors. In response to input signals to be amplified being within a first voltage range, the controller operates the amplifier in a lower power mode of operation, and toggles the voltage on one of the positive and negative output nodes between a common potential and the voltage on the power source node, while holding the other output node at the common potential. In the lower power mode of operation, the first and second transistors are in the off state, and the fifth and seventh transistors are in an on state.

While the positive input signal is in a positive half cycle and the negative input signal is in a negative half cycle, the controller keeps the fourth transistor in an on state and the eighth transistor in an off state, keeping the voltage on the negative output node at the common potential, and reciprocally toggles on and off the third and sixth transistors, switching the voltage on the positive output node between the common potential and the power source voltage. While the positive input signal is in a negative half cycle and the negative input signal is in a positive half cycle, the controller keeps the third transistor in an on state and the sixth transistor in an off state, keeping the voltage on the positive output node at the common potential, and reciprocally toggles on and off the eighth and fourth transistors, switching the voltage on the negative output node between the common potential and the power source voltage.

While input signals to be amplified are outside the first voltage range, the controller operates the amplifier in a higher power mode of operation, and toggles the voltage on one of the positive and negative output nodes between the voltage on the power source node and the increased voltage on the linked node from the charge pump while holding the other output node at the common potential. While the positive input signal is in a positive half cycle and the negative input signal is in a negative half cycle, the controller keeps the fourth and seventh transistors in an on state and the second and eighth transistors in an off state, keeping the voltage on the negative output node at the common potential. The controller keeps the sixth transistor in an on state and the third transistor in an off state, and reciprocally toggles on and off the first and fifth transistors, switching the voltage on the positive output node between the power source voltage and the increased voltage on the linked node from the charge pump.

While the positive input signal is in a negative half cycle and the negative input signal is in a positive half cycle, the controller keeps the third and fifth transistors in an on state and the first and sixth transistors in an off state, keeping the voltage on the positive output node at the common potential. The controller keeps the eighth transistor in an on state and the fourth transistor in an off state, and reciprocally toggles on and off the second and seventh transistors, switching the voltage on the negative output node between the power source voltage and the increased voltage on the linked node from the charge pump.

In some examples, the amplifier includes comparison logic to compare the positive and negative input signals to three ramp signals and determine whether the amplifier should operate in a lower or a higher power mode. Two of the ramp signals have the same peak-to-peak magnitude, which corresponds to the difference between the increased voltage from the charge pump and the power source voltage, but different common mode levels. The third ramp signal has a different peak-to-peak magnitude, which corresponds to the difference between the power source voltage and the common potential, and a different common mode level.

DETAILED DESCRIPTION

As described herein, an output stage of a class-D amplifier includes transistors coupled together in a configuration that permits the use of a charge pump for higher amplitude input signals to be amplified, and permits amplifier operation without the charge pump for lower amplitude input signals. In one example, the transistors include a first transistor coupled to a charge pump voltage source node and a positive output node of the amplifier. A second transistor couples to the charge pump voltage source node and a negative output node of the amplifier. A third transistor couples to the positive output node, and a fourth transistor couples to the negative output node. A fifth transistor is coupled to a source voltage node. A sixth transistor is coupled to the fifth transistor and the positive output node. A seventh transistor is coupled to the source voltage node. An eighth transistor is coupled to the seventh transistor and the negative output node.

A charge pump is also included as part of, or coupled to, the amplifier, and converts a source voltage (e.g., a battery voltage) of the source voltage node to a boosted voltage for the charge pump voltage source node. The charge pump voltage from the charge pump is greater than the source voltage. The charge pump uses capacitors to increase the voltage, avoiding the larger area, higher profile, and higher cost associated with inductor-based methods of boosting voltage. Responsive to a magnitude of an input signal to be amplified being within a particular voltage range (e.g., at the lower amplitude level using only the battery voltage, not the additional voltage from the charge pump), a controller coupled to or included within the amplifier generates control signals to keep the first and second transistors in an off state, disconnecting the charge pump from the positive and negative output nodes, and generates control signals to keep the fifth and seventh transistors in an on state.

During the positive half cycle of the positive input signal and the negative half cycle of the negative input signal, the controller generates control signals to keep the fourth transistor in an on state and the eighth transistor in an off state, causing the voltage on the negative output node to be a common level voltage. The controller also generates control signals to reciprocally toggle on and off the third and sixth transistors, causing the voltage on the positive output node to be either the battery voltage or the common level voltage.

During the negative half cycle of the positive input signal and the positive half cycle of the negative input signal, the controller generates control signals to keep the third transistor in an on state and the sixth transistor in an off state, causing the voltage on the positive output node to be the common level voltage. The controller also generates control signals to reciprocally toggle on and off the fourth and eighth transistors, causing the voltage on the negative output node to be either the battery voltage or the common level voltage.

Responsive to the magnitude of the input signal being outside the particular voltage range (e.g., at the higher amplitude requiring increased voltage from the charge pump) and during the positive half cycle of the positive input signal and the negative half cycle of the negative input signal, the controller generates control signals to keep the fourth and the seventh transistors in an on state and the second and the eighth transistors in an off state, causing the voltage on the negative output node to be the common level voltage. The controller also generates control signals to keep the sixth transistor in an on state, the third transistor in an off state, and reciprocally toggle the first and fifth transistors, causing the voltage on the positive output node to be either the boosted voltage from the charge pump or the battery voltage.

During the negative half cycle of the positive input cycle and the positive half cycle of the negative input signal, the controller generates control signals to keep the eighth transistor in an on state, the fourth transistor in an off state, and reciprocally toggle the second and seventh transistors, causing the voltage on the negative output node to be either the boosted voltage from the charge pump or the battery voltage. The controller also generates control signals to keep the third and fifth transistors in an on state and the first and sixth transistors in an off state, causing the voltage on the positive output node to be the common level voltage. Responsive to the duty cycle of the voltage output by the amplifier being less than a particular threshold, the controller generates control signals to operate the charge pump at a first frequency. Responsive to the duty cycle of the voltage output by the amplifier being greater than the particular threshold, the controller generates control signals to operate the charge pump at a second frequency which is greater than the first frequency.

FIG. 1illustrates an example output stage100of an amplifier. Additional components may be included as part of the amplifier as well, at least some of which are illustrated in other figures and discussed below. In the example ofFIG. 1, the output stage100includes a charge pump110and a multi-level class-D full bridge driver120. The charge pump110is coupled to a voltage source node105and to a second node115. The voltage source node105may be coupled to a voltage source (not shown), and thus the voltage on the voltage source node105may be the voltage of that particular voltage source. In one example, the voltage source is a battery, although the voltage source can be other than a battery in other examples. The voltage source node105is labeled as “VBATT” to illustrate the example in which the voltage source is a battery. The voltage source node105is referred to herein as the “VBATT node”.

Node115is labeled as “VLINK” to illustrate voltage output by charge pump110linked to bridge driver120. Node115is referred to herein as the “VLINK node”. The charge pump110may be part of, or separate from, the amplifier's output stage100. The charge pump110receives the voltage from the VBATT node105and generates an output voltage that is greater than the voltage on the VBATT node. The output voltage from the charge pump110is provided to the VLINK node115. In this example, the charge pump110outputs a voltage that is three times the voltage at the VBATT node105, but any appropriate increase in voltage may be used.

The bridge driver120in the example ofFIG. 1includes eight transistors shown as M1, M2, M3, M4, M5, M6, M7, and M8arranged into three switch networks. The first switch network150includes M1and M2. The drains of M1and M2connect to the VLINK node115. The source of M1is connected to a node130, which represents the positive output node (OUTP) of the amplifier. The source of M2is connected to a node135, which represents the negative (minus) output node (OUTM) of the amplifier. Each of M1and M2is controlled by respective control signals shown inFIG. 1as CTL1(for M1) and CTL2(for M2) applied to the respective gates of M1and M2. The first switch network150connects a voltage at VLINK node115to the output nodes OUTP130and OUTM135.

The third switch network170includes M3and M4. The sources of M3and M4are connected to a common potential (e.g., ground). The drain of M3is connected to OUTP node130and the drain of M4is connected to OUTM node135. M3is controlled by control signal CTL3applied to its gate. M4is controlled by control signal CTL4applied to its gate. The third switch network170connects a common potential to the output nodes OUTP130and OUTM135.

The second switch network160A includes M5and M6and the second switch network160B includes M7and M8. The sources of M5and M7connect to VBATT node105. The drain of M5connects to the drain of M6. The drain of M7connects to the drain of M8. The source of M6connects to OUTP node130. The source of M8connects to OUTM node135. M5, M6, M7, and M8are controlled by a respective control signal applied to the respective gates of the transistors. M5is controlled by control signal CTL5, M6is controlled by control signal CTL6, M7is controlled by control signal CTL7, and M8is controlled by control signal CTL8. The second switch network160A connects a voltage at VBATT node105to OUTP node130. The second switch network160B connects a voltage at VBATT node105to OUTM node135.

In some examples, at least one of the transistors M1-M8is a laterally diffused metal oxide semiconductor field effect transistor (LDMOS). In some implementations, all of the transistors M1-M8are LDMOS transistors. In the example ofFIG. 1, transistors M1-M8are n-type LDMOS transistors. The bulk (sometimes called “back gate”) connection of each transistor may be connected to the source of the respective transistor. Switches and control logic to dynamically connect the bulk of each transistor to different potentials and nodes need not be included. The transistors M1-M8are shown as metal oxide semiconductor field effect transistors, but can be implemented as other types of transistors, for example bipolar junction transistors.

In operation, the transistors M1-M8of the output stage100provide voltage to OUTP node130and OUTM node135, and by extension to a load140connected to them. Transistors M1-M8are controlled in multiple different modes of operation depending on the magnitude of the input signal to be amplified. For example, a lower power mode of operation is used in response to the input signal being less than a threshold level and a higher power mode of operation is used in response to the input signal being greater than the threshold level. Each of these operational modes is explained below.

FIG. 2illustrates the lower power mode of operation. In this mode, the input signal is less than a threshold and the voltage from the battery is sufficient. The first switch network150disconnects the voltage at VLINK node115from output nodes OUTP130and OUTM135. Control logic (shown in other figures) generates control signals CTL1and CTL2to maintain M1and M2in an off state, as indicated by the “X”s through M1and M2. While M1and M2are in an off state, the voltage on VLINK node115remains the boosted voltage from the charge pump, which is available to the output nodes at any time. In response to the output amplification increase, M1and M2may immediately begin toggling to transfer the boosted voltage from the charge pump. While the output stage100operates in a lower power mode and the charge pump110is disconnected from bridge drive120, charge pump110may operate in a lower power mode of operation at a lower frequency, for example 50 kiloHerz (kHz).

While the amplifier operates in the lower power mode of operation and M1and M2are kept in an off state, the control logic also generates control signals CTL5and CTL7to maintain M5and M7in an on state. As such, the VBATT voltage, and not VLINK, may be switched through M5and M6to OUTP node130and through M7and M8to OUTM node135as shown by the dashed arrows.

During the positive half cycle of the positive input signal and the negative half cycle of the negative input signal, the control logic generates control signals CTL4and CTL8to maintain M4in an on state and M8in an off state, causing the voltage on OUTM node135to be ground. The control logic also generates control signals CTL6and CTL3to reciprocally toggle M6and M3on and off, causing the voltage on OUTP node130to toggle between VBATT and ground as shown in sections310and330ofFIG. 3.

During the negative half cycle of the positive input signal and the positive half cycle of the negative input signal, not shown inFIG. 3, the controller generates control signals CTL3and CTL6to maintain M3in an on state and M6in an off state, causing the voltage on OUTP node130to be ground. The control logic also generates control signals CTL4and CTL8to reciprocally toggle M4and M8on and off, causing the voltage on OUTM node15to toggle between VBATT and ground.

Thus, the output of the amplifier comprises OUTP node130and OUTM node135and provides a differential output, which in the lower power mode of operation varies between +VBATT and −VBATT. Some implementations may include a current recycling phase, where both OUTM and OUTP are at the same voltage potential by having M3and M4(or M6and M8) on at the same time. During this phase, current is recycled through the transistor switches in the on state.

FIG. 3shows a waveform for OUTP130of output stage100inFIG. 1during both lower and higher power modes of operation, and a waveform of the filtered input signal INP. In response to the INP signal being less than a threshold level, the lower power mode of operation is used as shown in sections310and330. While the output stage100operates in a lower power mode, the charge pump110may be disconnected from bridge driver120, and the OUTP voltage switches between the battery voltage at VBATT105and ground, as described herein with reference toFIG. 2. The OUTP waveform in section320illustrates the OUTP voltage in response to the magnitude of the INP signal being greater than the threshold. While the output stage100operates in a higher power mode, the charge pump110may provide the boosted voltage at VLINK node115, and by extension deliver higher power to the load. In the higher power mode of operation, the voltage on VLINK node115switches between the increased voltage VLINK from the charge pump110and the battery voltage from VBATT105.

FIG. 4shows an example output stage400of an amplifier including a charge pump410. The output stage400is described herein with reference toFIG. 1and includes a variable frequency charge pump410and a bridge driver120. Charge pump410in the example ofFIG. 4includes seven transistors, shown as CP-M1, CP-M2, CP-M3, CP-M4, CP-M5, CP-M6and CP-M7, where CP indicates charge pump. The source of CP-M1connects to VBATT node105and the drain connects to node405. A capacitor C1connects to node405and node415. The drain of CP-M2and the source of CP-M3connect to node415. The source of CP-M2connects to a common potential (e.g., ground). The drain of CP-M3connects to VBATT node105. CP-M1, CP-M2, and CP-M3are controlled by respective control signals not shown inFIG. 4, which are applied to the respective transistors' gate terminals.

The source of CP-M4connects to node405, and the drain connects to node425. A capacitor C2connects to node425and node420. The drain of CP-M5and the source of CP-M6connect to node420. The source of CP-M5connects to a common potential (e.g., ground). The drain of CP-M6connects to VBATT node105. CP-M4, CP-M5, and CP-M6are controlled by respective control signals not shown inFIG. 4, which are applied to the respective transistors' gate terminals. The source of CP-M7connects to node425, and the drain connects to VLINK node115. CP-M7is controlled by a control signal not shown inFIG. 4which is applied to the gate terminal. A capacitor C3connects to VLINK node115and a common potential (e.g., ground).

In operation, during a first clock phase, CP-M1and CP-M2are maintained in an on state, and C1is charged to approximately VBATT. CP-M3and CP-M4are maintained in an off state. During a second clock phase initiated after C1is charged to approximately VBATT, CP-M3, CP-M4, and CP-M5are maintained in an on state. C2is charged to approximately two times VBATT while CP-M1, CP-M2, CP-M6, and CP-M7are maintained in an off state. During a third clock phase initiated after C2is charged to approximately two times VBATT, CP-M6and CP-M7are maintained in an on state, and C3is charged to approximately three times VBATT. CP-M4and CP-M5are maintained in an off state. Thus, the voltage at VLINK node115is approximately three times VBATT. In this way, the charge pump410transfers power to VLINK node115, and the power at VLINK node115is transferred through bridge driver120to load140, as indicated by the dashed arrows.

The third clock phase may also be used to charge C1at the same time. As discussed above, CP-M4is maintained in an off state while C1and C3are charged. While CP-M6and CP-M7are maintained in an on state and CP-M4and CP-M5are maintained in an off state to charge C3, CP-M1and CP-M2may be maintained in an on state and CP-M3maintained in an off state to charge C1. In this case, the first clock phase and the third clock phase are the same. While only three stages are shown here, any number of stages may be used to increase the voltage at VLINK node115to any appropriate level.

The use of capacitors causes the charge pump to be cheaper, lower profile, and smaller size than a similar inductor-based boost converter. As discussed above with reference toFIG. 2, the capacitors store charge such that the boosted voltage from the charge pump is available to the bridge driver120at any time. In contrast, inductor based boost converters cannot maintain the boosted voltage at VLINK node115and may experience a delay while the inductors charge, resulting in a slower increase in the voltage on VLINK node115. Inductor based boost converters use a voltage regulator to control the voltage available to other circuits from the inductor based boost converter.

Inductor based boost converters may experience difficulties with stability as the inductors and capacitors oscillate. Further, design of controllers for inductor based boost converters may be difficult because they work in tandem with a voltage regulator to control the voltage output to VLINK node115. In contrast, the capacitive charge pump410maintains a steadier voltage on VLINK node115at all times and is controlled in part by an open feedback loop associated with voltage on the output nodes, the same feedback loop used to inform control of bridge driver120. This results in a single feedback circuit providing feedback to both the charge pump410and the bridge driver120. The control complexity is thus lower than in some inductor based boost converters, which use two separate closed loop feedback circuits—one for the inductor based boost converter and another for the bridge driver. The chip area devoted to control of the capacitor based charge pump410is also smaller than in some inductor based boost converters and amplifiers.

While the output stage400operates at a higher power mode of operation, charge pump410provides the increased voltage to VLINK node115. The first switch network150connects the voltage at VLINK node115to output nodes OUTP130and OUTM135, while the third switch network170disconnects the common potential from output nodes OUTP130and OUTM135.

During the positive half cycle of the positive input signal and the negative half cycle of the negative input signal, control logic (shown in other figures) generates control signals CTL4and CTL7to maintain M4and M7in an on state and control signals CTL2and CTL8to maintain M2and M8in an off state, causing the voltage on OUTM135to be the common potential. The control logic also generates control signal CTL6to maintain M6in an on state and control signal CTL3to maintain M3in an off state, disconnecting the common potential from OUTP130as indicated by the “X” through M3. The control logic generates control signals CTL1and CTL5to reciprocally toggle M1and M5on and off, causing the voltage on OUTP130to switch between VLINK and VBATT.

During the negative half cycle of the positive input signal and the positive half cycle of the negative input signal, the control logic generates control signal CTL8to maintain M8in an on state and control signal CTL4to maintain M4in an off state, disconnecting the common potential from OUTM135as indicated by the “X” through M4. The control logic also generates control signals CTL2and CTL7to reciprocally toggle M2and M7on and off, causing the voltage on OUTM135to switch between VLINK and VBATT. The control logic also generates control signals CTL3and CTL5to maintain M3and M5in an on state and control signals CTL1and CTL6to maintain M1and M6in an off state, causing the voltage on OUTP130to be the common potential.

Because M1and M5are reciprocally turned on and off, the voltage on OUTP node130may toggle between VLINK and VBATT as shown in section320ofFIG. 3. Because M2and M7are reciprocally turned on and off, the voltage on OUTM node135may toggle between VLINK and VBATT. Thus, the output node of the amplifier comprises OUTP node130and OUTM node135and provides a differential output, varying between +VLINK and −VLINK. The state of M6and M8need not be on or off for bridge driver120to output voltage between +VLINK and −VLINK. In some implementations, M6and M8are maintained in an on state for ease of control.

In some examples, the charge pump410operates at variable frequencies according to the power used by the amplifier. While the magnitude of the INP signal is greater than the threshold, the output stage400operates in a higher power mode, and charge pump410provides the boosted voltage through VLINK node115. While output stage400operates in the higher power mode, the charge pump410may operate at a mid-level power mode or a higher power mode of operation. At the mid-level power mode, the charge pump410operates at a lower frequency than it does in its higher power mode of operation. For example, the charge pump410illustrated inFIG. 4operates at 760 kiloHerz (kHz) in the mid-level power mode, but operates at 1.52 MHz in the higher power mode. The lower frequency and the higher frequency may be selected based on the FET driving losses within the charge pump and the capacitance of C1, C2, and C3.

The mid-level power mode or higher power mode of operation of charge pump410is selected based on the duty cycle of the amplifier output. For example, control logic indicates charge pump410operates in mid-level power mode based on the pulse width modulation signal at VLINK node115having a duty cycle less than a threshold value. In the example ofFIG. 4, the charge pump410operates in mid-level power mode based on the pulse width modulation signal at VLINK node115having a duty cycle less than 50%. Control logic indicates charge pump410operates in higher power mode based on the pulse width modulation signal at VLINK node115having a duty cycle greater than a threshold value. In the example ofFIG. 4, the charge pump410operates in higher power mode in response to the pulse width modulation signal at VLINK node115having a duty cycle greater than 50%.

FIG. 5is a model of the charge pump410in the example output stage400ofFIG. 4. As it operates at higher frequencies, the output impedance of the charge pump410decreases, and the current output deliverable by charge pump410increases. The charge pump410effectively operates as a step-up transformer coupled to VBATT node105and resistor R0. R0represents the output impedance of the charge pump410and is further coupled to VLINK node115. Capacitor C3is coupled between VLINK node115and a common potential (e.g., ground). The transformer comprises a primary winding510and a secondary winding520, where the ratio of the number of turns in the primary winding, Np, to the number of turns in the secondary winding, Ns, in this example is 1:3. This illustrates that charge pump410continues to provide approximately three times the voltage of VBATT to VLINK node115. As the frequency increases, the output impedance R0decreases and the voltage at VLINK node115approaches VLINK.

FIG. 6shows a waveform OUTP130of output stage400inFIG. 4during lower and higher power modes of operation characteristic of output stage400, and a waveform of the filtered input signal INP. As shown in and described with reference toFIG. 3, in response to the INP signal being less than a threshold level such as VBATT in this example, the lower power mode of operation610for output stage400is used and illustrated as sections310and330. While the output stage400operates in lower power mode610, the charge pump410may be disconnected from bridge driver120and operate in a lower power mode at a lower frequency, such as 50 kHz as discussed above with reference toFIG. 2, while maintaining the boosted voltage at VLINK node115. The OUTP voltage results from the battery voltage at VBATT105alone, as described herein with reference toFIG. 2.

The OUTP waveform in section320illustrates the OUTP voltage in response to the magnitude of the INP signal being greater than the threshold, VBATT in this example. While the output stage400operates in a higher power mode620, the charge pump410may provide the boosted voltage at VLINK node115. The charge pump410operates in a mid-level power mode630and a higher power mode640, as described herein with reference toFIGS. 4 and 5. In mid-level power mode630, the example charge pump410operates at a lower frequency, such as 760 kHz. In higher power mode640, the example charge pump410operates at a higher frequency, such as 1.52 MHz. As described herein with reference toFIG. 4, the charge pump410operates in mid-level power mode630in response to the pulse width modulation signal at VLINK node115having a duty cycle less than 50% and operates in higher power mode640in response to the signal having a duty cycle greater than 50%.

The different frequencies of operation allow charge pump410to dynamically respond to the changing power used by output stage400based on the desired amplification of the input signal. While output stage400operates in a lower power mode of operation, charge pump410operates at a lower power mode as well, at a lower frequency such as 50 kHz. The capacitors within charge pump410maintain the boosted VLINK voltage on VLINK node115while charge pump410operates at a lower power mode. While output stage400operates in a higher power mode, charge pump410operates in either a mid-level power mode or a higher power mode at the corresponding frequencies, increasing the power available to the output nodes based on the desired amplification of the input signal.

FIG. 7shows an example amplifier700including the output stage400described herein with reference toFIG. 4and a multi-level ramp generator730. The amplifier700in this example also includes a subtractor710P, a subtractor710M, a loop filter720, comparison logic740, and controller750. An input signal705to be amplified includes two signals: INP705P and INM705M. INP705P represents the positive input signal, and INM705M represents the negative (minus) input signal. INP705P is provided to the subtractor710P, and INM705M is provided to the subtractor710M.

The difference signal from each subtractor is then filtered by loop filter720, which may comprise a fourth-order filter, to generate two filtered input signals, INTP722and INTM724. Loop filter720compensates for non-linear factors in example amplifier700, for example dead time. INTP722corresponds to INP705P and has a similar shape as INP705P. INTM724corresponds to INM705M and has a similar shape as INM705M. Multi-level ramp generator730generates three triangular voltage waveforms: RAMP_HI732, RAMP_MID734, and RAMP_LO736. The three RAMP signals are compared to INTP722and INTM724by comparison logic740to generate pulse width modulated signals, which are the comparator outputs745provided to the controller750.

The control logic noted above may include the controller750and/or other components shown inFIG. 7. The controller750includes modulation logic752, drivers754, and mode detection756. Modulation logic752and drivers754generate the control signals CTL1-CTL8discussed herein with reference toFIG. 1that are provided to the gates of M1-M8in the output stage100. Mode detection756generates the control signals provided to the gates of CP-M1through CP-M7in charge pump410discussed herein with reference toFIG. 4. The assorted control signals760generated by controller750are provided to output stage400. The output signal generated by the output stage400(e.g., the voltages on OUTP130and OUTM135) is provided to the speaker and also serves as a feedback signal to the subtractors710.

FIG. 8illustrates an example of the three triangular voltage waveforms generated by multi-level ramp generator730, and an example INTP722waveform and INTM724waveform. RAMP_HI732has a minimum voltage of V2and a maximum voltage of V3. RAMP_MID734has a minimum voltage of V1and a maximum voltage of V2. RAMP_LO736has a minimum voltage of V0and a maximum voltage of V1. The voltage difference between V3and V2, the voltage difference between V2and V1, and the voltage difference between V1and V0(referred to as the peak-to-peak voltage for the ramps) may be selected such that the overall relationship from the input to the comparators to the output of the final output stage maintains a substantially constant gain. For example, the peak-to-peak voltages for RAMP_HI732and RAMP_LO736are chosen to have the same ratio as the difference between VLINK and VBATT. The peak-to-peak voltage for RAMP_MID734is chosen to have the same ratio as the difference between VBATT and ground. RAMP_HI732, RAMP_MID734, and RAMP_LO736may have different peak-to-peak magnitudes and different common mode levels as shown. The use of three ramp signals, each with different common mode levels, may capture information related to the negative parts of INTP722and INTM724that would be outside the voltage range covered by only two ramp signals. This may reduce common mode error and the total harmonic distortion of the amplifier.

A portion of the signals output by the loop filter720, INTP722and INTM724, are shown superimposed on the sawtooth waveforms of RAMP_HI732, RAMP_MID734, and RAMP_LO736. Voltages V2and V1, the range of RAMP_MID734, generally represent the threshold voltages for determining whether the controller750is to operate the output stage400in the lower power mode of operation610or the higher power mode of operation620noted above. While the magnitudes of INTP722and INTM724are less than V2but greater than V1, for example as identified at810, the output745of comparison logic740includes a time varying square wave with a first duty cycle, which corresponds to the pulse width modulation signal associated with the voltage VBATT. While the magnitudes of INTP722and INTM724are greater than V2or less than V1, for example as identified at820, the output745of comparison logic740includes a time varying square wave with a second duty cycle, which corresponds to the pulse width modulation signal associated with voltage VLINK.

The controller750uses the output signals745from the comparison logic740of varying duty cycles to determine whether the output stage400should be operated in the lower power mode of operation610without use of the voltage from the charge pump410or in the higher power mode of operation620to use the voltage from charge pump410. If the controller750determines the output stage400should be operated in the higher power mode of operation620, the controller750further determines whether the charge pump410should be operated in the mid-level power mode of operation630at the lower frequency or in the higher power mode of operation640at the higher frequency based on the duty cycles of the output signals745from the comparison logic740. The controller750and comparison logic740are discussed further with reference toFIG. 11.

RAMP_HI732, RAMP_MID734, and RAMP_LO736have substantially the same frequency, carefully controlled amplitudes, and different common modes. Further, RAMP_MID734is 180° out of phase with RAMP_HI732and RAMP_LO736such that the maxima of RAMP_MID734are substantially aligned with the minima of RAMP_HI732, and the minima of RAMP_MID734are substantially aligned with the maxima of RAMP_LO736. To generate RAMP signals with these characteristics, multi-level ramp generator730includes an independent ramp generator for each RAMP signal.

FIG. 9shows an example multi-level ramp generator900for use in an amplifier, such as amplifier700described herein with reference toFIG. 7. Ramp generator900includes a bias voltage common mode (VCM) generator910, a reference voltage generator920, and three ramp generators: high ramp generator930, middle ramp generator940, and low ramp generator950. As shown inFIG. 8, each ramp has a different common mode level. The bias VCM generator910generates a VCM for each ramp generator: VCM_HI912for high ramp generator930, VCM_MID914for middle ramp generator940, and VCM_LO916for low ramp generator950. In some implementations, the bias VCM generator910generates a single VCM, such as VCM_MID914, for all three ramp generators930,940, and950. VCM_HI912and VCM_LO916are then generated using the peak-to-peak voltages of each ramp and the corresponding voltage difference relative to VCM_MID914.

Reference voltage generator920generates a high voltage reference signal and a low voltage reference signal for each ramp generator to indicate the upper and lower voltages of each ramp, such as voltages V0, V1, V2, and V3described herein with reference toFIG. 8. Reference voltage generator920generates REFHI_HI932and REFHI_LO934for high ramp generator930, which in the example ofFIG. 8correspond to V3and V2. Reference voltage generator920generates REFMID_HI942and REFMID_LO944for middle ramp generator940, which in the example ofFIG. 8correspond to V2and V1. Reference voltage generator920generates REFLO_HI952and REFLO_LO954for low ramp generator950, which in the example ofFIG. 8correspond to V1and V0. REFHI_LO934and REFMID_HI942are substantially the same voltage. Similarly, REFMID_LO944and REFLO_HI952are substantially the same voltage.

Each of high ramp generator930, middle ramp generator940, and low ramp generator950receive the appropriate VCM signal from bias VCM generator920, the appropriate high voltage reference signal and low voltage signal from reference voltage generator930, and the same clock reference signal. From these inputs, high ramp generator930generates RAMP_HI732, middle ramp generator940generates RAMP_MID734, and low ramp generator950generates RAMP_LO736.

FIG. 10shows an example ramp generator1000in multi-level ramp generator900. Ramp generator1000includes a delay locked loop (DLL)1010and a ramp generator based voltage controlled oscillator (VCO)1050. The DLL1010allows multi-level ramp generator900to synchronize the frequencies of the generated ramps to a single reference clock, and includes a phase-frequency detector (PFD)1015, a charge pump1020, a loop filter1025, and a transconductance circuit1030. The PFD1015receives the reference clock signal CLK_REF and a clock feedback signal CLK_FB, and outputs signals UP and DN, which are square waves with a pulse width proportional to the phase difference between CLK_REF and CLK_FB. Charge pump1020receives UP and DOWN from PFD1015and works in conjunction with loop filter1025as an integrator to generate a voltage control signal VCtrl. VCtrl is converted to a current control signal ICtrl through transconductance circuit1030.

Ramp generator based VCO1050receives ICtrl, as well as the high reference voltage signal and the low voltage reference signal for the particular ramp generator, such as those generated by reference voltage generator920. Ramp generator based VCO1050outputs the particular ramp signal for the particular ramp generator and the clock feedback signal CLK_FB. For example, ramp generator based VCO1050receives VCM_HI912, REFHI_HI932, and REFHI_LO934and outputs RAMP_HI732. The ramp generated by ramp generator based VCO1050is provided to other components in the amplifier, such as comparison logic740, while CLK_FB is provided to PFD1015in a closed feedback loop.

FIG. 11shows an example comparison logic and modulation logic in the example amplifier700ofFIG. 7. As described above with reference toFIGS. 7 and 8, comparison logic740compares INTP722and INTM724to the ramps RAMP_HI732, RAMP_MID734, and RAMP_LO736generated by multi-level ramp generator730. The results of these comparisons are used by controller750to determine which mode of operation output stage400should be operated in, and to generate appropriate control signals for elements within output stage400. Analysis blocks1100A,11006, and1100C illustrate operation of an example comparison logic740and modulation logic752. Analysis block1100A results in control signals for M1and M5, analysis block1100B results in control signals for M3, M4, M6, and M8, and analysis block1100C results in control signals for M2and M7.

In analysis block1100A, comparator1105compares RAMP_LO736and INTM724, and outputs a pulse width modulated signal that is logic high in response to RAMP_LO736being greater than INTM724and logic low in response to RAMP_LO736being less than INTM724. Comparator1110compares INTP722and RAMP_HI732, and outputs a pulse width modulated signal that is logic high in response to INTP722being greater than RAMP_HI732and logic low in response to INTP722being less than RAMP_HI732. OR gate1115in modulation logic752receives the output signals of comparator1105and comparator1110, and outputs CTL1for M1in output stage400.

As discussed above with reference toFIGS. 4, M1and M5cannot be on at the same time, and so CTL1passes through inverter1120to become CTL5for M5. Thus, analysis block1100A results in the control signals for M1and M5. While output stage400is in a higher power mode of operation620, CTL1and CTL5cause M1and M5to toggle on and off reciprocally, and provide either VLINK or VBATT to OUTP node130. While output stage400is in a lower power mode of operation610, CTL1causes M1to maintain an off state, disconnecting bridge driver120and OUTP node130from VLINK node115, and CTL5causes M5to maintain an on state.

In analysis block1100B, comparator1125compares INTP722and RAMP_MID734, and outputs a pulse width modulated signal that is logic high in response to INTP722being greater than RAMP_MID734and logic low in response to INTP722being less than RAMP_MID734. In response to INTP722being greater than RAMP_MID734, output stage400operates in a higher power mode. Comparator1130compares INTM724and RAMP_MID734, and outputs a pulse width modulated signal that is logic high in response to INTM724being greater than RAMP_MID734and logic low in response to INTM724being less than RAMP_MID734.

AND gate1140in modulation logic752receives the output signal of comparator1125directly, and the output signal of comparator1130after it is inverted by inverter1135. AND gate1140outputs CTL6for M6in output stage400. As discussed above with reference toFIGS. 2, M6and M3cannot be on at the same time, and so CTL6passes through inverter1140to become CTL3for M3. Thus, analysis block1100B results in the control signals for M3and M6. While output stage400is in a higher power mode of operation620, CTL3causes M3to maintain an off state, disconnecting ground from OUTP node130, and CTL6causes M6to maintain its current state. While output stage400is in a lower power mode of operation610, CTL3and CTL6cause M3and M6to toggle on and off reciprocally, and provide either ground or VBATT to OUTP node130.

AND gate1155in modulation logic752receives the output signal of comparator1130directly, and the output signal of comparator1125after it is inverted by inverter1150. AND gate1155outputs CTL8for M8in output stage400. As discussed above with reference toFIGS. 2, M8and M4cannot be on at the same time, and so CTL8passes through inverter1160to become CTL4for M4. Thus, analysis block1100B also results in the control signals for M4and M8. While output stage400is in a higher power mode of operation620, CTL4causes M4to maintain an off state, disconnecting ground from OUTM node135, and CTL8causes M8to maintain an on state. While output stage400is in a lower power mode of operation610, CTL4and CTL8cause M4and M8to toggle on and off reciprocally, and provide either ground or VBATT to OUTM node135.

In analysis block1100C, comparator1165compares RAMP_LO736and INTP722, and outputs a pulse width modulated signal that is logic high in response to RAMP_LO736being greater than INTP722and logic low in response to RAMP_LO736being less than INTP722. Comparator1170compares INTM724and RAMP_HI732, and outputs a pulse width modulated signal that is logic high in response to INTM724being greater than RAMP_HI732and logic low in response to INTM724being less than RAMP_HI732. OR gate1175in modulation logic752receives the output signals of comparator1165and comparator1170, and outputs CTL2for M2in output stage400.

As discussed above with reference toFIGS. 4, M2and M7cannot be on at the same time, and so CTL2passes through inverter1180to become CTL7for M7. Thus, analysis block1100C results in the control signals for M2and M7. While output stage400is in a higher power mode of operation620, CTL2and CTL7cause M2and M7to toggle on and off reciprocally, and provide either VLINK or VBATT to OUTM node135. While output stage400is in a lower power mode of operation610, CTL2causes M2to maintain an off state, disconnecting bridge driver120and OUTM node135from VLINK node115, and CTL7causes M7to maintain an on state.

FIG. 12shows an example mode detection logic756in the example amplifier700ofFIG. 7. Analysis block1210determines if output stage400is operating in a lower power mode160. Analysis block1250determines if output stage400is operating in a higher power mode620, and whether charge pump410should operate in a mid-level power mode630or in a higher power mode640.

In analysis block1210, OR gate1215receives CTL6and CTL8, and outputs an indicator signal1220that is logic high in response to CTL6or CTL8being a pulse width modulated signal. Indicator signal1220is input to a pulse duration detector1225. Output signal1230from pulse duration detector1225is logic high in response to indicator signal1220including pulse width modulated pulses. This in turn indicates output stage400is operating in a lower power mode610, and VBATT from the battery is sufficient. Charge pump410should operate in a mid-level power mode630at a lower frequency or in a lower power mode itself, for example at a frequency as low as 47 kHz.

In analysis block1250, OR gate1255receives CTL1and CTL2, and outputs an indicator signal1260that is logic high in response to either M1or M2being in an on state and logic low in response to both M1and M2being in an off state, disconnecting charge pump410from bridge driver120. Indicator signal1260is associated with voltage VLINK, and is input to an edge detector1265and a pulse duration detector1275. The duty cycle of indicator signal1260is indicative of how long OUTP node130and OUTM node135receive VLINK from charge pump410.

If edge detector1265detects a logic high value from indicator signal1260, but pulse duration detector1275determines indicator signal1260has a duty cycle less than a certain threshold, then output stage400is operating in a higher power mode620, but the mid-level power mode and corresponding lower frequency of operation for charge pump410delivers sufficient power to the load. If the pulse duration detector1275determines indicator signal1260has a duty cycle greater than a certain threshold, then output stage400is operating in a higher power mode620, and charge pump410should operate in a higher power mode640at a higher frequency to deliver additional power to the load.

In this description, the term “couple” or “couples” means either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, X may be a function of Y and any number of other factors.

Modifications are possible in the described examples, and other implementations and modifications are possible, within the scope of the claims.