Target row generator, DRAM, and method for determining a target row

The present disclosure provides a target row generator. The target row generator includes a plurality of counting modules, a comparing module and a first processing module. Each of the plurality of counting modules is configured to generate a counting record, and includes a reset timer. The reset timer is configured to generate a reset signal to reset a corresponding one of the plurality of counting modules. The comparing module is connected to the plurality of counting modules and is configured to compare a plurality of counting records generated by the plurality of counting modules. The first processing module is connected to the comparing module and is configured to generate a target row record based on a comparison result from the comparing module. The quantity of the plurality of counting records is less than the quantity of the plurality of stressed rows.

TECHNICAL FIELD

The present disclosure relates to a circuit, a dynamic random access memory (DRAM) and a method, and more particularly, to a target row generator, a DRAM and a method for determining a target row.

DISCUSSION OF THE BACKGROUND

A DRAM usually has high cell density, and row hammer problems are frequently incurred. When a row of the DRAM is repeatedly activated, charges of the row may leak and interact electrically with an adjacent row, causing the adjacent row, which is not desired to be activated, to experience a bit flipping phenomenon.

This Discussion of the Background section is for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed in this section constitutes a prior art to the present disclosure, and no part of this section may be used as an admission that any part of this application, including this Discussion of the Background section, constitutes prior art to the present disclosure.

SUMMARY

One aspect of the present disclosure provides a target row generator. The target row generator comprises a plurality of counting modules, a comparing module and a first processing module. Each of the plurality of counting modules is configured to generate a counting record. The comparing module is connected to the plurality of counting modules and is configured to compare a plurality of counting records generated by the plurality of counting modules. The first processing module is connected to the comparing module and is configured to generate a target row record based on a comparison result from the comparing module. In some embodiments, each of the plurality of counting records represents a stressed degree of a corresponding one of a plurality of stressed rows. In some embodiments, the quantity of the plurality of counting modules is less than the quantity of the plurality of stressed rows.

In some embodiments, each of the plurality of counting modules is configured to record a stressed degree of one of a plurality of rows, and the counting record of each of the plurality of counting modules is generated based on the stressed degree of a corresponding one of the plurality of rows.

In some embodiments, each of the plurality of counting modules includes a gate, an address storage unit and a counter. The gate is configured to allow passage of a stressed row address of the corresponding one of the plurality of rows. The address storage unit is connected to the gate and is configured to store the stressed row address of the corresponding one of the plurality of rows. The counter is connected between the address storage unit and the comparing module, and the counter is configured to record the stressed degree of the corresponding one of the plurality of rows, and to generate the counting record.

In some embodiments, each of the plurality of counting modules further includes a reset timer connected to the gate, the address storage unit and the counter, wherein the reset timer is configured to generate a reset signal to reset the gate, the address storage unit, the counter and the reset timer itself.

In some embodiments, the target row generator further comprises an enabling module connected to the plurality of counting modules and configured to generate an enable signal.

In some embodiments, the target row generator further comprises a second processing module connected to the first processing module, the enabling module and the plurality of counting modules, wherein the second processing module is configured to generate a reset signal to reset one of the plurality of counting modules.

Another aspect of the present disclosure provides a dynamic random access memory (DRAM). The DRAM comprises a memory array including a plurality of banks and a row-determining circuit, wherein the row-determining circuit is connected to the memory array. Each of the plurality of banks includes a plurality of rows. In some embodiments, the row-determining circuit includes a target row generator configured to generate a target row record, and the target row generator includes a plurality of counting modules, a comparing module and a first processing module. Each of the plurality of counting modules is configured to generate a counting record. The comparing module is connected to the plurality of counting modules and is configured to compare a plurality of counting records generated by the plurality of counting modules. The first processing module is connected to the comparing module and is configured to generate the target row record based on a comparison result from the comparing module, in some embodiments, each of the plurality of counting records represents a stressed degree of a corresponding one of a plurality of stressed rows. In some embodiments, the quantity of the plurality of counting modules is less than the quantity of the plurality of stressed rows.

In some embodiments, each of the plurality of counting modules is configured to record a stressed degree of one of the plurality of rows, and the counting record of each of the plurality of counting to modules is generated based on the stressed degree of a corresponding one of the plurality of rows.

In some embodiments, each of the plurality of counting modules includes a gate, an address storage unit and a counter. The gate is configured to allow passage of a stressed row address of the corresponding one of the plurality of rows. The address storage unit is connected to the gate and is configured to store the stressed row address of the corresponding one of the plurality of rows. The counter is connected between the address storage unit and the comparing module, and the counter is configured to record the stressed degree of the corresponding one of the plurality of rows and to generate the counting record.

In some embodiments, each of the plurality of counting modules further includes a reset timer connected to the gate, the address storage unit and the counter, wherein the reset timer is configured to generate a reset signal to reset the gate, the address storage unit, the counter and the reset timer itself.

In some embodiments, the target row generator further includes an enabling module connected to the plurality of counting modules and configured to generate an enable signal.

In some embodiments, the target row generator further includes a second processing module connected to the first processing module, the enabling module and the plurality of counting modules, wherein the second processing module is configured to generate a reset signal to reset one of the plurality of counting modules.

In some embodiments, the DRAM further comprises a command decoder connected to the plurality of counting modules and configured to generate an active command and the stressed row address for each of the plurality of counting modules.

In some embodiments, the command decoder is connected to the gate of each of the plurality of counting modules.

In some embodiments, the row-determining circuit further includes a row address multiplexer connected to the first processing module of the target row generator and configured to generate a row address record.

Another aspect of the present disclosure provides a method for determining a target row. The method comprises the following steps. A plurality of counting records are generated, wherein each of the plurality of counting records represents a stressed degree of a corresponding one of a plurality of stressed rows, and the quantity of the plurality of counting records is less than the quantity of the plurality of stressed rows. The plurality of counting records are compared based on the stressed degree to generate a comparison result. A target row record is generated based on the comparison result.

In some embodiments, the method further comprises a step of removing one of the plurality of counting records, wherein the removed one of the plurality of counting records has a lower stressed degree.

In some embodiments, the step of removing one of the plurality of counting records is performed if the number of the plurality of counting records is equal to a reference number.

In some embodiments, the method further comprises a step of removing one of the plurality of counting records, wherein the removed one of the plurality of counting records remains zero during a preset period of time.

In some embodiments, the step of removing one of the plurality of counting records is performed if the number of the plurality of counting records is equal to a reference number.

With the above-mentioned configurations of the target row generator, space occupied by the plurality of counters in the DRAM is reduced. Consequently, the disadvantages of a conventional target row generator can be alleviated.

The foregoing has outlined rather broadly the features and technical advantages of the present disclosure in order that the detailed description of the disclosure that follows may be better understood. Additional features and technical advantages of the disclosure are described hereinafter, and form the subject of the claims of the disclosure. It should be appreciated by those skilled in the art that the concepts and specific embodiments disclosed may be utilized as a basis for modifying or designing other structures, or processes, for carrying out the purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit or scope of the disclosure as set forth in the appended claims.

DETAILED DESCRIPTION

FIG. 1is a block diagram of a DRAM9in accordance with some embodiments of the present disclosure. Referring toFIG. 1, in some embodiments, the DRAM9includes a memory array91, a plurality of row decoders92, a controlling module93, a command decoder94, an address storage module95, a plurality of column latches96, a plurality of column decoders97, an I/O gating98, a plurality of sensing amplifiers99and a row-determining circuit1.

FIG. 2Ais a schematic diagram illustrating the memory array91of the DRAM9in accordance with some embodiments of the present disclosure, andFIG. 2Bis a schematic diagram illustrating a bank911of the memory array91in accordance with some embodiments of the present disclosure. Referring toFIG. 2A, in some embodiments, the memory array91includes a plurality of banks911, and the number of the plurality of banks911is defined as M. Referring toFIG. 2B, each of the plurality of banks911includes a plurality of rows9111and a plurality of columns9112, and the number of the plurality of rows9111included in each of the plurality of banks911is defined as N. In other embodiments, the number of the plurality of banks911and the number of the plurality of rows9111included in each of the plurality of banks911may be varied.

FIG. 2Cis a schematic diagram illustrating a relationship between the plurality of banks911and the plurality of row decoders92, and a relationship between the plurality of banks911and the plurality of column decoders97, in accordance with some embodiments of the present disclosure. Referring toFIG. 2C, in some embodiments, the plurality of row decoders92are respectively connected to the plurality of banks911, and each of the plurality of row decoders92is configured to activate a row9111(seeFIG. 2B) of a corresponding one of the plurality of banks911. In some embodiments, the sensing amplifiers99are respectively connected to the plurality of banks911. In some embodiments, the plurality of column decoders97are respectively connected to the plurality of sensing amplifiers99, and each of the plurality of column decoders97is configured to activate a column9112(seeFIG. 2B) of a corresponding one of the plurality of banks911.

Referring back toFIG. 1, in some embodiments, the row-determining circuit1is connected to the plurality of row decoders92and is configured to determine which row9111(seeFIG. 2B) of the corresponding one of the plurality of banks911(seeFIG. 2A) is to be refreshed.

Referring toFIG. 1, in some embodiments, the controlling module93is connected to the plurality of row decoders92and the plurality of column decoders97, and the controlling module93is configured to control operations of the plurality of row decoders92and the plurality of column decoders97. The command decoder94is connected to the controlling module93and the row-determining circuit1, and the command decoder94is configured to generate a refresh commend (Cr), an active command (Ca) and a stressed row address (Asr). The address storage module95is connected to the row-determining circuit1, the controlling module93and the plurality of column latches96, and the address storage module95is configured to generate a plurality of address records (Ra) for an auto-refreshing to process. In some embodiments, the plurality of column latches96are respectively connected to the plurality of column decoders97. The I/O gating98is connected to the plurality of sensing amplifiers99, and is configured to input or output a data.

Referring toFIG. 1, in some embodiments, the address storage module95and the column latches % are configured as registers, while the configurations of the address storage module95and the column latches96may be varied in other embodiments.

FIG. 3is a block diagram illustrating the row-determining circuit1in accordance with some embodiments of the present disclosure. Referring toFIG. 3, in some embodiments, the row-determining circuit1includes a plurality of row latches11, a row address multiplexer12, a target row generator13and an auto-refresh counter14. In some embodiments, the plurality of row latches11are respectively connected to the plurality of row decoders92. In some embodiments, the row address multiplexer12is connected between the address storage module95and the plurality of row latches11, and the row address multiplexer12is configured to generate an auto-refreshing row address (Aa) and a target row address (Atr). In some embodiments, the target row generator13is connected between the command decoder94and the row address multiplexer12, and the target row generator13is configured to generate a target row record (Rtr). In some embodiments, the auto-refresh counter14is connected to the row address multiplexer12and is configured to generate a counting signal (Sc) to update the auto-refreshing row address (Aa).

Referring toFIG. 3, in some embodiments, the plurality of row latches11are configured as registers, while in other embodiments, the configurations of the plurality of row latches11may be varied.

FIG. 4is a block diagram illustrating the target row generator13in accordance with some embodiments of the present disclosure. Referring toFIG. 4, in some embodiments, the target row generator13includes a plurality of counting modules131, a comparing module132, a first processing module133, an enabling module134and a second processing module135.

In some embodiments, a row9111that suffers from a row hammer problem is regarded as a stressed row. Referring toFIG. 4, in some embodiments, the plurality of counting modules131are connected to the command decoder94. Each of the plurality of counting modules131is configured to record a stressed degree of one of the plurality of rows9111(seeFIG. 2B) of the plurality of banks911(seeFIG. 2A), and to generate a counting record (Rc). In some embodiments, the stressed degree is correlated with a stressed time of the stressed row, and the stressed time is defined as the activated times of a row that is adjacent to the stressed row. In such a manner, the counting record (Rc) of each of the plurality of counting modules131is generated based on the stressed time of a corresponding one of the plurality of rows9111.

Referring toFIG. 4, in some embodiments, the comparing module132is connected to the plurality of counting modules131. In some embodiments, the comparing module132is configured to compare a plurality of counting records (Rc) generated by the plurality of counting modules131, and to output two comparison records to the first processing module133. In some embodiments, the number of the plurality of counting records (Rc) is less than the number of the plurality of rows9111.

Referring toFIG. 4, in some embodiments, the first processing module133is connected between the comparing module132and the row address multiplexer12. In some embodiments, the first processing module133is configured to generate the target row record (Rtr) based on one of the two comparison records from the comparing module132. In some embodiments, the one of the two comparison records is generated from a counting record (Rc), which has a highest stressed time of the plurality of counting records (Rc), wherein the row9111that corresponds to the counting record (Rc) having the highest stressed time of the plurality of counting records (Rc) is defined as a target row. In some embodiments, the first processing module133is further configured to generate a numerical signal (Sn) based on the other one of the two comparison records from the comparing module132. In some embodiments, the other one of the two comparison records is generated from a counting record (Rc) having a lower stressed degree (such as the lowest stressed time of the plurality of counting records (Rc). In some embodiments, the numerical signal (Sn) is generated for determining which of the plurality of counting modules131is to be reset.

Referring toFIG. 4, in some embodiments, the enabling module134is connected to the plurality of counting modules131and the second processing module135, and the enabling module134is configured to generate an enable signal (Se) for the plurality of counting modules131and the second processing module135to actuate counting record-removing processes.

Referring toFIG. 4, in some embodiments, the second processing module135is connected to the first processing module133, the plurality of counting modules131and the enabling module134. In some embodiments, the second processing module135is configured to reset one of the plurality of counting modules131based on the numerical signal (Sn) generated by the first processing module133.

FIG. 5is a block diagram illustrating the counting module131of the target row generator13in accordance with some embodiments of the present disclosure. Referring toFIG. 5, in some embodiments, each of the plurality of counting modules131includes a gate1311, an address storage unit1312, a counter1313and a reset timer1314. In some embodiments, the gate1311is connected to the command decoder94and is configured to allow passage of the stressed row address (Asr) of the corresponding one of the plurality of rows9111(seeFIG. 2B) based on the stressed row address (Asr). In some embodiments, the address storage unit1312is connected to the gate1311and the comparing module132, and the address storage unit1312is configured to store the stressed row address (Asr) of the corresponding one of the plurality of rows9111. In some embodiments, the counter1313is connected between the address storage unit1312and the comparing module132, and the counter1313is configured to record the stressed time of the corresponding one of the plurality of rows9111, and to generate the counting record (Rc). In some embodiments, the reset timer1314is connected to the gate3111, the address storage unit1312and the counter1313. In some embodiments, the reset timer1314is configured to generate a first reset signal (Sr1) to reset the gate1311, the address storage unit1312, the counter1313, and the reset timer1314itself.

Referring toFIG. 5, in some embodiments, when the address storage unit1312of one of the plurality of counting modules131stores the stressed row address (Asr) of one of the plurality of rows9111, the gate1311of a corresponding one of the plurality of counting modules131is regarded as an active gate. A detailed description of the active gate will be illustrated in the following paragraphs.

Referring toFIG. 5, in some embodiments, the gate1311of each of the plurality of counting modules131is configured as a transistor, while the configuration of the gate1311of each of the plurality of counting modules131may be varied.

Referring toFIG. 5, in some embodiments, the second processing module135is connected to the first processing module133(seeFIG. 4), the enabling module134, and the gate1311, the address storage unit1312, the counter1313and the reset timer1314of each of the plurality of counting modules131. In some embodiments, the second processing module135is configured to generate a second reset signal (Sr2) to reset the gate1311, the address storage unit1312, the counter1313and the reset timer1314of one of the plurality of counting modules131.

FIG. 6is a block diagram illustrating the first processing module133of the target row generator13in accordance with some embodiments of the present disclosure. Referring toFIG. 6, in some embodiments, the first processing module133includes a first processing unit1331and a second processing unit1332. In some embodiments, the first processing unit1331is connected between the comparing module132and the row address multiplexer12. In some embodiments, the first processing unit1331is configured to generate the target row record (Rtr). In some embodiments, the second processing unit1332is connected between the comparing module132and the second processing module135. In some embodiments, the second processing unit1332is configured to generate the numerical signal (Sn).

FIG. 7is a block diagram illustrating the enabling module134of the target row generator13in accordance with some embodiments of the present disclosure. Referring toFIG. 7, in some embodiments, the enabling module134is connected to the second processing module135and the gate1311and the reset timer1314of each of the plurality of counting modules131. In some embodiments, the enabling module134includes a comparing unit1341and a third processing unit1342. In some embodiments, the comparing unit1341is connected to the gate1311of each of the plurality of counting modules131, and is configured to compare the number of a plurality of active gates with a reference number (RN). In some embodiments, the third processing unit1342is connected to the comparing unit1341, the reset timer1314of each of the plurality of counting modules131, and the second processing module135. In some embodiments, the third processing unit1342is configured to generate the enable signal (Se) when the number of active gates is equal to the reference number (RN) based on the output of the comparing unit1341.

Referring toFIG. 7, in some embodiments, the reference number (RN) is a given value and is the same as the number of the plurality of counting modules131, such that when the number of the plurality of active gates is equal to the reference number (RN), it is indicated that the address storage unit1312of each of the plurality of counting modules131stores the stressed row address (Asr) of the corresponding one of the plurality of rows9111, and that it is necessary to actuate reset processes for the subsequent counting process. In other embodiments, such configurations may be varied.

FIG. 8is another block diagram illustrating the row-determining circuit10of the DRAM9in accordance with some embodiments of the present disclosure. Referring toFIG. 8, in some embodiments, the row-determining circuit10further includes a filtering module15connected between the command decoder94and the target row generator13. In some embodiments, the filtering module15is configured to reduce a working burden of the target row generator13.

FIG. 9is a block diagram illustrating the filtering module15in accordance with some embodiments of the present disclosure. Referring toFIG. 9, in some embodiments, the filtering module15includes a plurality of filtering units151respectively connected to the plurality of counting modules131. In some embodiments, each of the filtering units151is configured to implement a filtering process, such that a working burden of a corresponding one of the plurality of counting modules131is reduced. During the filtering process, each of the plurality of filtering units151allows passage of only one of a plurality of active commands (Ca) and only one of a plurality of stressed row addresses (Asr) after receiving a preset quantity of the plurality of active commands (Ca) and a preset quantity of the plurality of stressed row addresses (Asr). In some embodiments, each of the filtering units151is configured as a linear feedback shift register (LFSR), while in other embodiments, such configuration may be varied.

FIG. 10is a flowchart illustrating a method2for determining the target row in accordance with some embodiments of the present disclosure. Referring toFIG. 10, in some embodiments, the method2includes a step21, in which the plurality of counting records (Rc) are generated, wherein each of the plurality of counting records (Rc) represents the stressed time of a corresponding one of a plurality of stressed rows, and the quantity of the plurality of counting records (Rc) is less than the quantity of the plurality of stressed rows; a step22, in which the plurality of counting records (Rc) are compared to select a counting record (Rc) from the plurality of counting records (Rc); a step23, in which the target row record (Rtr) is generated, and the target row record (Rtr) is generated based on the counting record (Rc) selected from the plurality of counting records (Rc).

In some embodiments, a memory-array-refreshing process includes two sub-processes: the auto-refreshing process and a row-hammer-refreshing process. In some embodiments, during the memory-array-refreshing process, the DRAM9uses most of its operating time performing the auto-refreshing process, and uses the remaining time performing the row-hammer-refreshing process. In other embodiments, such configuration may be varied.

Referring back toFIG. 3, in some embodiments, during the auto-refreshing process, the auto-refresh counter14first generates the counting signal (Sc), and the counting signal (Sc) is sent to the row address multiplexer12to update the auto-refreshing row address (Aa). Next, the row address multiplexer12generates an updated auto-refreshing row address (Aa), and the updated auto-refreshing row address (Aa) is sent to the plurality of row decoders92through the plurality of row latches21. Subsequently, each of the plurality of banks911(seeFIG. 2A) is refreshed based on the updated auto-refreshing row address (Aa). For example, when the counting signal (Sc) indicates number one, a first row of each of the plurality of banks911is refreshed, and when the counting signal (Sc) is updated to indicate number two, a second row of each of the plurality of banks911is then refreshed.

Referring toFIG. 3, in some embodiments, during the row-hammer-refreshing process, the target row generator13first generates the target row record (Rtf). Next, the target row record (Rtr) is sent to the row address multiplexer12, and the row address multiplexer12generates the target row address (Atr) based on the target row record (Rtr). Next, the target row address (Atr) is sent to the plurality of row decoders92through the plurality of row latches11. Subsequently, each of the plurality of banks911(seeFIG. 2A) is refreshed based on the target row address (Atr).

Referring toFIG. 4, in some embodiments, during a target-row-record generating process, the plurality of counting modules131first generate the plurality of counting records (Rc). Next, the plurality of counting records (Rc) are compared. Next, the counting record (Rc) having the highest stressed time is selected from the plurality of counting records (Rc). Subsequently, the target row record (Rtr) is generated from the counting record (Rc) having the highest stressed time of the plurality of counting records (Rc).

In some embodiments, the target-row-record generating process includes three sub-processes: a counting process, a first reset process and a second reset process, in some embodiments, the first reset process and the second reset process are simultaneously actuated, while in other embodiments, such configuration may be varied.

FIG. 11is a schematic diagram illustrating the counting process of the counting module131in accordance with some embodiments of the present disclosure. Referring toFIG. 11, in some embodiments, when the DRAM9(seeFIG. 1) is not actuated, the plurality of counting modules131(seeFIG. 4) do not record the stressed time of any one of the plurality of rows9111(seeFIG. 2B). In some embodiments, after the DRAM9is actuated, when one of the plurality of rows9111is stressed, the command decoder94sends the active command (Ca) and the stressed row address (Asr) of the one of the plurality of rows9111to one of the plurality of counting modules131. In some embodiments, since the one of the plurality of counting modules131does not record the stressed time of any one of the plurality of rows9111, the gate1311of the one of the plurality of counting modules131first allows passage of the active command (Ca) and the stressed row address (Asr) of the one of the plurality of rows9111; next, the stressed row address (Asr) of the one of the plurality of rows9111is stored by the address storage unit1312of the one of the plurality of counting modules131, and the active command (Ca) is sent to the reset timer1314of the one of the plurality of counting modules131to restart the timing of the reset timer1314; subsequently, the counter1313of the one of the plurality of counting modules131records one stressed time for the one of the plurality of rows9111.

Referring toFIG. 11, in some embodiments, when the one of the plurality of rows9111(seeFIG. 2B) is further stressed, the gate1311of the one of the plurality of counting modules131allows the passage of the active command (Ca) and the stressed row address (Asr) of the one of the plurality of rows; consequently, the counter1313of the one of the plurality of counting modules1313records another stressed time for the one of the plurality of rows9111, and the timing of the reset timer1314of the one of the plurality of counting modules131is again restarted.

Referring toFIG. 11, in some embodiments, when another one of the plurality of rows9111(seeFIG. 2B) is stressed, the gate1311of the one of the plurality of counting modules131prohibits the passage of the active command (Ca) and the stressed row address (Asr) of another one of the plurality of rows9111; consequently, another one of the plurality of counting modules131that do not record the stressed time of any one of the plurality of rows9111allows the passage of the active command (Ca) and the stressed row address (Asr) of another one of the plurality of rows9111.

Referring back toFIG. 7, in some embodiments, when the number of active gates is equal to the reference number (RN), such condition indicates that none of the plurality of counting modules131(seeFIG. 4) is available to record the stressed time of one of the plurality of rows9111(seeFIG. 2B) that has not been recorded; as a result, the enabling module134sends the enable signals (Se) to the reset timers1314(seeFIG. 5) of all of the plurality of counting modules131to perform the first reset process, and sends the enable signals (Se) to the second processing module135to perform the second reset process.

FIG. 12is a schematic diagram illustrating the first reset process of the counting module131in accordance with some embodiments of the present disclosure. Referring toFIG. 12, in some embodiments, during the first reset process, the reset timer1314of each of the plurality of counting modules131sends the first reset signal (Sr1) to the gate1311, the address storage unit1312, the counter1313, and the reset timer1314itself if the reset timer1314of a corresponding one of the plurality of counting modules131has not been restarted during the preset period of time. In some embodiments, when the reset timer1314of the corresponding one of the plurality of counting modules131has not been restarted during the preset period of time, such condition indicates that zero stressed times have been recorded during the preset period of time; consequently, the gate1311, the address storage unit1312, the counter1313and the reset timer1314of the corresponding one of the plurality of counting modules131are reset for the subsequent counting process.

FIG. 13is a schematic diagram illustrating the second reset process of the counting module131in accordance with some embodiments of the present disclosure. Referring toFIG. 13, in some embodiments, during the second reset process, the second processing module135sends the second reset signal (Sr2) to the gate1311, the address storage unit1312, the counter1313and the reset timer1314of a corresponding one of the plurality of counting modules131based on the numerical signal (Sn) from the first processing module133; consequently, the gate1311, the address storage unit1312, the counter1313and the reset timer1314of the corresponding one of the plurality of counting modules131that has the counting record (Rc) having the lower stressed degree, such as the lowest stressed degree, are reset for the subsequent counting process.

FIG. 14is a block diagram illustrating a comparative target row generator13′. Referring toFIG. 14, the comparative target row generator13′ is connected to the row address multiplexer12and is configured to generate a target row record (Rtr). The comparative target row generator13′ includes a processing unit131′ and a counting unit132′. The processing unit131′ is connected to the row address multiplexer12and is configured to generate the target row record (Rtr). The counting unit132′ is connected to the processing unit131′ and is configured to generate a plurality of target rows.

FIG. 15is a block diagram illustrating the counting unit132′ of the comparative target row generator131′. Referring toFIG. 15, the counting unit132′ includes a plurality of counting blocks1321′ connected to the processing unit131′, and each of the plurality of counting blocks1321′ is configured to determine a target row. Each of the counting blocks1321′ includes a plurality of counters and a processor, and the number of the plurality of counters included in each of the plurality of counting blocks1321′ is the same as the number of the plurality of rows9111(seeFIG. 2B) of each of the plurality of banks911(seeFIG. 2A). The plurality of counters of each of the counting blocks1321′ are configured to respectively record the stressed times for the plurality of rows9111. The processor of each of the counting blocks1321′ is configured to determine the target row. The number of the plurality of counting blocks1321′ is the same as the number of the plurality of banks911.

Referring toFIG. 15, during a target-row-determining process of the comparative target row generator13′ (seeFIG. 14), for each of the plurality of counting blocks1321′, if the number of the stressed time of one of the plurality of counters reaches a threshold value, the target row is determined to be the row which corresponds to the one of the plurality of counters. After each of the plurality of counting blocks1321′ determines the target row, the target row is sent to the processing unit131′. Subsequently, the processing unit131′ generates the target row record (Rtr). Since the processing unit131′ only sends one target row record (Rtr) for all of the plurality of banks911(seeFIG. 2A), the selection by the processing unit131′ of the target row from the plurality of counting blocks1321′ is based on the order of time priority. For example, when the third counting block1321′ determines and sends the target row to the processing unit131′ earlier than the other counting blocks1321′, the processing unit131′ then generates the target row record (Rtr) for all of the plurality of banks911based on the target row determined by the third counting block1321′.

In the comparative target row generator13′, each of the plurality of rows9111of the plurality of banks911requires a counter to record the stressed time. Therefore, the comparative target row generator13′ includes a large number of counters. In contrast, the target row generator13of the present disclosure includes a limited number of counters to record the stressed time of a corresponding one of the plurality of rows9111. Therefore, space occupied by the plurality of counters in the target row generator13is reduced. As a result, a size of the DRAM9can also be reduced correspondingly.

One aspect of the present disclosure provides a target row generator. In some embodiments, the target row generator includes a plurality of counting modules, a comparing module and a first processing module. Each of the plurality of counting modules is configured to generate a counting record. In some embodiments, the comparing module is connected to the plurality of counting modules and is configured to compare a plurality of counting records generated by the plurality of counting modules. In some embodiments, the first processing module is connected to the comparing module and is configured to generate a target row record based on a comparison result from the comparing module. In some embodiments, each of the plurality of counting records represents a stressed degree of a corresponding one of a plurality of stressed rows. In some embodiments, the quantity of the plurality of counting modules is less than the quantity of the plurality of stressed rows.

One aspect of the present disclosure provides a dynamic random access memory (DRAM). The DRAM includes a memory array with a plurality of banks, and a row-determining circuit connected to the memory array. Each of the plurality of banks includes a plurality of rows. In some embodiments, the row-determining circuit includes a target row generator configured to generate a target row record, and the target row generator includes a plurality of counting modules, a comparing module and a first processing module. Each of the plurality of counting modules is configured to generate a counting record. The comparing module is connected to the plurality of counting modules and is configured to compare a plurality of counting records generated by the plurality of counting modules. The first processing module is connected to the comparing module and is configured to generate the target row record based on a comparison result from the comparing module. In some embodiments, each of the plurality of counting records represents a stressed degree of a corresponding one of a plurality of stressed rows. In some embodiments, the quantity of the plurality of counting modules is less than the quantity of the plurality of stressed rows.

One aspect of the present disclosure provides a method for determining a target row. The method includes the following steps. A plurality of counting records are generated, wherein each of the plurality of counting records represents a stressed degree of a corresponding one of a plurality of stressed rows, and the quantity of the plurality of counting records is less than the quantity of the plurality of stressed rows. The plurality of counting records are compared based on the stressed degree to generate a comparison result. A target row record is generated based on the comparison result.