Pitch division patterning techniques

Embodiments of the invention comprise pitch division techniques to extend the capabilities of lithographic techniques beyond their minimum pitch. The pitch division techniques described herein employ additional processing to ensure pitch divided lines have the spatial isolation necessary to prevent shorting problems. The pitch division techniques described herein further employ processing acts to increase the structural robustness of high aspect ratio features.

FIELD

Embodiments of the invention generally pertain to semiconductor processing and more specifically to pitch division techniques and processing acts to increase physical stability of pitch divided lines.

BACKGROUND

Feature sizes for integrated circuits are continuously being reduced in response to many factors, including demand for increased portability, computing power, memory capacity and energy efficiency. Reduced feature sizes for integrated circuits are related to the techniques used to form said features. For example, lithography is commonly used to pattern features (e.g., conductive lines) of integrated circuits. The periodicity of these patterned features maybe described as a pitch.

Pitch describes the distance between identical points of two neighboring features. Lithographic techniques cannot reliably form features below a minimum pitch due to factors such as optics and light or radiation wavelength. Thus, the minimum pitch of a lithographic technique is an obstacle to feature size reduction.

Techniques to extend the capabilities of lithographic techniques beyond their minimum pitch are referred to as pitch division, or pattern density multiplication, techniques. For example, when a pitch is halved, this reduction is referred to as pitch doubling, and when a pitch is quartered, this reduction is referred to as pitch quadrupling or pitch quad.

Prior art pitch quad techniques typically require line reduction to be finalized prior to transferring a pattern to a hard mask layer. Furthermore, if feature size is shrunk below 15 nm, the physical strength of the feature may not be enough to withstand processing environments. Pitch quad lines produced by prior art methods are susceptible to feature collapse due to capillary forces (e.g., moisture in the air, fluid processing) and shorting problems (because of the reduced space between the lines).

The descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of the invention is provided below, followed by a more detailed description with reference to the drawings.

DETAILED DESCRIPTION

The following description provides examples, such as material types, etch chemistries, and processing conditions, in order to provide a thorough description of embodiments of the present invention; however, a person of ordinary skill in the art will understand the present invention may be practiced without employing these specific details.

Process acts and structures necessary to understand the embodiments of the present invention are described in detail below. The description below does not form a complete process flow for manufacturing a semiconductor device, and the semiconductor structures described below do not form a complete semiconductor device. Additional acts to form complete semiconductor devices from the semiconductor structures may be performed by fabrication techniques known in the art.

As described above, pitch quad techniques extend the capabilities of lithographic techniques beyond their minimum pitch. The pitch quad techniques described herein differ from the prior art by employing additional processing to ensure pitch quad lines have the spatial isolation necessary to prevent shorting problems. The pitch quad techniques described herein further employ processing acts to increase the structural robustness of pitch quad lines.

As described herein, pitch quad may be accomplished via a double “pitch double” process (i.e., a process of forming spacer layers on a pattern to halve a pitch) utilizing a patterning stack including two hard mask layers. In one embodiment, photo-resist pads are placed to overlap a first set of spacers included on a patterning stack to form a pattern. This pattern is then etched onto the first hard mask layer of the patterning stack. Another spacer layer is deposited on the etched pattern, and the first hard mask layer is selectively removed to form a second set of spacers. The second set of spacers is further processed to produce a final pitch quad mask pattern, transferred to the second hard mask layer of the patterning stack.

In another embodiment, a “shark jaw” series of pitch quad lines are produced without use of photo resist pads, but rather with an additional spacer layer to form “negative spacers.” Negative spacers comprise a deposited spacer layer that is subsequently removed (i.e., the negative spacers never form lines of the final pattern) to produce a pattern of lines spaced apart in a staggered “shark jaw” formation.

If a quad pitch line comprises a lateral dimension below 15 nm, the physical strength of the line may not be enough to withstand processing environments. Pattern distortion and damaging may be difficult to control with the conventional aspect ratios of pitch quad lines produced by the prior art. In one embodiment, two full stack etches are used to avoid, during processing, individual pitch quad lines wherein each line comprises a lateral dimension equal to the space between each line (i.e., the final pitch quad line may comprise a lateral dimension equal to the spacing between the lines, but this is avoiding during the processing stages). This embodiment processes lines with an increased physical stability due to the increased ratio of the depth/vertical dimension of the line to the width/lateral dimension of the line that is encountered during processing.

Illustrations included herein, are not drawn to scale and are not meant to be actual views of any particular semiconductor structure or semiconductor device. Rather, the illustrations are merely idealized representations that are employed to describe the present invention. Additionally, elements common between illustrations may retain the same numerical designation.

FIGS. 1A-1Gillustrate top-views and cross-sectional views of a patterning stack processed according to an embodiment of the invention. With reference toFIG. 1A, patterning stack100includes first dielectric anti-reflective coating (DARC) layer120, first hard mask layer130, second DARC layer140, second hard mask layer150, thin silicon dioxide layer159, and substrate layer160. First and second hard mask layers130and150may comprise, for example, one of transparent carbon, amorphous carbon, silicon containing hardmask, or metal containing hardmask.

As stated above, illustrations of patterning stack layers are not meant to accurately represent the scale of each layer. For example, the first and second DARC layer, functioning as an etch-stop, may each comprise a thickness of 2-4 nm and the first and second hard mask layer may each comprise a thickness of 50-100 nm.

Patterning stack100may further include photo resist pattern110. In this embodiment, photo resist pattern110includes lines111and112with large pads113and114, which will subsequently be branched for future contact landing pads (described below). Lines111and112have a lateral dimension of 4 F and are equally spaced by a distance of 4 F, wherein 8 F is the minimum lithography pitch.

FIG. 1Afurther illustrates patterning stack100after a spacer layer is applied to photo resist pattern110to form spacers115. This spacer layer (and subsequent spacer layers discussed below) may comprise any low temperature, conformal thin film deposition (e.g., silicon dioxide, silicon nitride, silicon carbonate, silicon oxynitride). This spacer layer (and subsequent spacer layers discussed below) may be deposited according to methods known in the art—e.g., chemical vapor deposition using O3 and TEOS to form silicon oxide, atomic layer deposition using a silicon precursor with an oxygen or nitrogen precursor to form silicon oxides and nitrides. Spacers115may be formed by any method known in the art (e.g., a reactive ion etch (RIE) process selectively stopping at DARC layer120). Spacers115may comprise a lateral dimension of ¼ of the photo resist pattern, i.e., 1 F. This will be the final lateral dimension of the pattern.

FIG. 1Billustrates, after spacers115are formed, photo resist pattern110may then be selectively removed via an O2 or forming gas plasma process to expose spacers115. Photo resist110may also be removed via a wet etch process.

After photo resist pattern110is removed, photo resist pads101-104may placed over the spacer at the ends of the spacers115. The placement of the pads is such that it will divide or branch the subsequent spacers described below. Photo resist pads101-104thus serve as a “redistribution spacer” to ensure subsequent formed lines are not too close together and are spatially isolated from each other. In this embodiment, photo resist pads101-104are illustrated as having a staggered placement. This placement will provide additional space in for subsequent placement of contact landing pads for the final pattern lines, as described below.

FIG. 1Cillustrates the pattern formed by spacers115and photo-resist pads101-104transferred to first hard mask layer130to form pattern135. This transfer may be executed via an RIE process. In another embodiment (not illustrated), spacers115are transferred to first hard mask layer130, and photo resist pads101-104are placed onto hard mask layer130(rather than spacers115) in order to redistribute the second spacer layer described below.

FIG. 1Dillustrates a second spacer layer deposited on pattern135to form spacers136. The lateral dimension of spacers136may determine the final critical dimension of the resulting pattern (i.e., 1 F). Spacers136are spread out based on the previous placement of photo resist pads101-104.

FIG. 1Eillustrates pattern135with the remaining hard mask layer subsequently removed via processes known in the art (e.g., with a plasma or wet chemical etching process), such that spacers136remain as pitch quad lines. As illustrated in the cross section view included inFIG. 1E, the space between spacers136is 1 F and the lateral dimension of the lines of spacers136is 1 F—i.e., one quarter of the initial lithographic pitch of photo resist pattern110. Furthermore spacers136, as illustrated comprise eight lines—i.e., four times the original amount of lines formed by photo resist pattern110(two).

The ends of spacers136may be “chopped” via a selective RIE or wet etch process to form lines180-187. The ends of spacers136, as illustrated, may be chopped in a manner so that ends of lines180-187are staggered with respect to each other.

Landing contact pads190-197may be placed on ends180-187, and the pattern may then be transferred to hard mask layer150as illustrated inFIG. 1F. Landing pads190-197are structurally isolated from each other as a result of the redistribution on the lines of spacers136via photo resist pads101-104. Landing pads190-197are sufficiently spaced as to eliminate potential shorting issues. This pattern may be combined with any peripheral CMOS components.

Resulting hard mask pattern155may be transferred to substrate layer160. It will be appreciated that substrate layer160may include a layer of a single material, a plurality of layers of different materials, a layer or layers having regions of different materials or structures in them, etc. These materials may include semiconductors, insulators, conductors, or combinations thereof. For example, the substrate may comprise gallium nitride, doped polysilicon, an electrical device active area, or a metal layer (e.g., a tungsten, tungsten silicide, titanium nitride, aluminum or copper layer, or combinations thereof). As described above, pattern155may directly correspond to the desired placement of conductive features, such as interconnects, in the substrate.

In another embodiment, a “shark jaw” series of pitch quad lines may be produced without the use of photo-resist pads101-104.FIGS. 2A-2Fillustrate top-views and cross-sectional views of a patterning stack processed according to an embodiment of the invention.FIG. 2Aillustrates patterning stack200(similar to patterning stack100) including first DARC layer220, first hard mask layer225, second DARC layer260, second hard mask layer265, and substrate layer270. Patterning stack200may further include photo resist pattern210. In the illustrated embodiment, lines of photo resist pattern210comprise a lateral dimension of 3 F after inclusion of a resist trim from4F. For example, photo resist pattern210may be etched using any etching method known in the art to adjust the lateral dimensions of the lines of photo resist pattern210. The extent of the etch is preferably selected so that the lateral dimensions of the modified lines are substantially equal to the desired spacing between subsequent formed spacers described below.

Dimension201of photo resist pattern210and space202between lines of photo resist pattern210are degrees of freedom that can be adjusted to account for subsequent contact landing pads described below. These degrees of freedom may further contribute to the redistribution of the line ends of the final pitch quad lines.

A spacer layer is deposited on photo resist pattern210to form spacers215having a lateral dimension of 1 F.FIG. 2Billustrates patterning stack200with photo resist pattern210removed, and the pattern formed by spacers215transferred to first hard mask layer225to form pattern230. The lateral dimension of the lines of pattern230is 1 F.

FIG. 2Cillustrates another spacer layer deposited and etched onto pattern230to form negative spacers240. The term “negative” spacer is used herein to describe spacers that will be removed to create a space, as described below. The lateral dimension of the lines of spacers240is 1 F, and the space separating each of spacers240is also 1 F.

First hard mask layer225may then be filled with filling material250, as illustrated inFIG. 2D. Filling material250as illustrated comprises a photo resist material. Filling material250may alternatively comprise an organic etch material, or the same material as hard mask layers225and265. If filling material250is a photo resist material, chop pattern245may be formed by exposing the photo resist material. If filling material250is a material other than photo resist material, chop pattern245may be formed by further coating the fill material with photo resist, and exposing chop pattern245.

InFIG. 2D, chop pattern245exposes DARC layer260. Chop pattern245forms lines251-256, made from fill material250. Line251includes end257that may be used to include an electrical contact, thus eliminating the need for a contact landing pad (lines252-256, as illustrated, include similar ends). Fill material250may further be etched or polished to expose spacers240and pattern230.

FIG. 2Eillustrates patterning stack200with negative spacers240removed. Negative spacers240may be removed via any process known in the art (e.g., wet chemical or plasma etch). Pattern230may subsequently be chopped to pattern285, which is transferred to second hard mask layer265, and finally into substrate270, as shown inFIG. 2F. Thus pitch quad lines271-284are created—lines271-276corresponding to lines251-256, and lines277-284corresponding to chop pattern245. Chopped pattern245may be shaped to account for contact landing pads required for lines277-284because these lines do not have a wide end similar to those of lines217-276. Lines271-284are structurally isolated from each other, and will not have any shorting issues due to the lines staggered “shark jaw” placement.

Embodiments of the invention described below comprise process acts to produce trenches that will form lines with increased physical stability over the prior art due to the ratio of the depth/vertical dimension of the line to the width/lateral dimension of the line. Pitch quad processing acts, including the above pitch quad method embodiments, may be used in conjunction with the following operations.

FIGS. 3A-3Hillustrate a top-view and a cross-sectional view of a patterning stack processed according to an embodiment of the invention.FIG. 3Aillustrates patterning stack300further including DARC layer329, hard mask layer330, first etch stop layer339, cap layer340, second etch stop layer349, floating gate poly layer350, gate dielectric layer359, and bulk layer360. Cap layer340may be referred to as a “sacrificial” cap layer, as it will be removed during processing as described below. Cap layer340may comprise, for example, undoped poly cap or nitride cap. Etch stop layers339and349may comprise, for example, silicon dioxide.

Patterning stack300may further include photo resist pattern310. A spacer layer may be deposited on photo resist pattern310for form spacers315. Lines of photo resist pattern may have a lateral dimension of 3 F (i.e., initial lateral dimension of 4 F with trim process described above), and spacers315may have a lateral dimension that, when further processed, may improve the physical strength of the final line (note that spacers315do not necessarily define the final lateral dimension).

FIG. 3Billustrates patterning stack300with photo resist pattern310selectively removed. Additional spacer layer320may be deposited on spacers315to form pattern321. Lines of pattern321comprise a lateral dimension of 3 F, each line spaced apart by a distance of 1 F. The spaces between the lines define the final lateral dimension. This pattern may be used as a mask to transfer form a pattern to hard mask layer330. Photo resist311may be deposited on the peripheral areas of the pattern formed by spacers315and spacer layer320.

FIG. 3Cillustrates pattern321transferred to hard mask layer330. As illustrated, the lines of pattern321have a lateral dimension of 3 F, separated by a 1 F space. Thus the lines of pattern322have an increased physical stability (compared to, for example, lines with a lateral dimension of 1 F separated by a 1 F space). Thus lines of pattern322are less susceptible to distortion during subsequent processing.

For each of the 1 F spaces separating the lines of pattern322, etches into bulk layer360of the patterning stack300are performed to create set of trenches400as shown inFIG. 3D. Said etches into bulk layer360may be performed by any process known in the art.

Remaining hard mask layer330may be removed and trenches400may subsequently be filled with a filling material. Filling material may be any material suitable to form the resulting pitch quad lines (e.g., a spacer oxide material, spacer nitride material, a dielectric material for shallow trench isolation (STI) features, a conductor metal). First cap layer340may be removed to expose filled trenches400, as illustrated byFIG. 3E. Exposed filled trenches400each have a lateral dimension of 1 F separated by a 3 F space, and have increased physical stability due to the vertical dimension of each filled trench.

Second spacer layer345may be deposited on the exposed first set of trenches to form pattern of lines410, each line having a lateral dimension of 3 F separated by a 1 F space similar to pattern322, as illustrated inFIG. 3F.

For each of the 1 F spaces separating the lines pattern410, an etch into bulk layer360of patterning stack300is performed to create a set of trenches450as shown inFIG. 3G. Trenches450lines are self-aligned with each other and with filled trenches400, due to the aforementioned processing acts. This resulting self-alignment is an improvement over prior art methods for pitch division, such as double patterning, as these methods are prone to misalignment. Additional photo resist mask390may be applied to add any pattern to edges395. Trenches450are filled with the filling material to form a pattern of lines comprising the filled trenches400and450, each filled trench comprising a lateral dimension of 1 F separated by a 1 F space as shown inFIG. 3H. In one embodiment, each of filled trenches400and450have a depth/vertical dimension of 3 F.

Having described the invention in detail and by reference to specific embodiments thereof, it will be apparent that modifications and variations are possible without departing from the scope of the invention defined in the appended claims. More specifically, although some aspects of the present invention are identified herein as preferred or particularly advantageous, it is contemplated that the present invention is not necessarily limited to these preferred aspects of the invention. Many modifications may be made to adapt the teachings of the present invention to a particular situation without departing from the scope thereof.