Transparent shared memory access in a software development system

The invention relates to a method for transparently writing to shared memory when debugging a multiple processor system. In this method, a software memory map reflecting the memory usage of the processors in the system to be debugged is created. Two or more debug sessions associated with processors in the system are activated. When a debug session makes a write request to a shared memory location, a check is made to see if the processor associated with that debug session has write access to the shared memory location. If it does, that processor is used to execute the write. If it does not, the software memory map is searched to find a processor that does have write access to the shared memory location and that processor is used to execute the write.

FIELD OF THE INVENTION

This invention generally relates to software development systems, and more specifically to debugging support for embedded software applications executing on multiple processor architectures.

BACKGROUND OF THE INVENTION

The advent of the system-on-a-chip (SOC) architectures for embedded systems has created many challenges for the software development systems used to develop and debug software applications that execute on these architectures. These systems may be comprised of multiple interconnected processors that share the use of on-chip and off-chip memory. A processor may include some combination of instruction cache (ICache) and data cache (DCache) to improve processing performance and can be instantiated from a design library as a single megacell. Furthermore, multiple megacells, with memory being shared among them, may be incorporated in a single embedded system. The processors may physically share the same memory without accessing data or executing code located in the same memory locations or they may use some portion of the shared memory as common shared memory. Common shared memory contains executable code or data that will be accessed or executed by more than one processor, possibly simultaneously.

These multiprocessor systems are often built by combining existing single processors. As a result, these systems often lack the hardware support to properly manage memory accesses and cache coherency while an application is being debugged. To keep the cost per chip low, often the circuitry permitting write access to shared memory may be limited to a subset of the processors sharing that memory. While this limited write access is acceptable when executing a fully debugged application, it is problematic during the development and debugging process. The debug process, by its very nature, requires the ability to download code and data to shared memory, to change code and data when problems are detected, and to set software breakpoints all while maintaining a synchronized view of memory across multiple processors. It is possible to re-tool debugger infrastructure to comprehend such multiprocessor systems but it is expensive to build specialized debuggers for every multiprocessor configuration.

SUMMARY OF THE INVENTION

An illustrative embodiment of the present invention seeks to provide a method for transparently writing to shared memory when debugging a multiple processor system. In this method, a software memory map reflecting the memory usage of the processors in the system to be debugged is created. Two or more debug sessions associated with processors in the system are activated. When a debug session makes a write request to a shared memory location, a check is made to see if the processor associated with that debug session has write access to the shared memory location. If it does, that processor is used to execute the write. If it does not, the software memory map is searched to find a processor that does have write access to the shared memory location and that processor is used to execute the write.

In another embodiment, the above method is enhanced to provide for cache coherency updates in the processors that have read access to the shared memory location that is being changed by the write request. The software memory map is search to locate all processors having read access to that shared memory location. The write request is broadcast to all located processors so that they can perform any needed cache coherency operations.

In alternate embodiments, the broadcasted write request contains an indication that the write has already occurred and the purpose of the broadcast is to notify the processor in the event a cache coherency update is necessary. The receiving processors do not necessarily have to execute the write. The receiving processors may perform the cache update using special hardware for maintaining cache coherency that does not necessarily require that the write to shared memory be executed by that processor.

In another embodiment, the method is further enhanced to handle coherency of software breakpoints in shared memory. If the write request is to a shared memory location that contains a software breakpoint, the software memory map is searched to find all processors with read access to the shared memory location. Each of the located processors is sent the new instruction that is to be written in the shared memory location so that the software representation containing all software breakpoints associated with each processor can be updated with the new instruction. Then, software breakpoint is reset with the new instruction. The resetting of the software breakpoint comprises clearing the software breakpoint at the shared memory location, performing the write request, and then setting a new software breakpoint at the shared memory location.

In other embodiments, a software development system is provided that executes the above methods during the debugging of the multiple processor system. And, a digital system is provided that executes the code that is debugged using the above methods.

Corresponding numerals and symbols in the different figures and tables refer to corresponding parts unless otherwise indicated.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Thus, a need has been identified for a software development system and methods to handle the debugging of software applications on hardware architectures comprised of multiple processors with shared memory. The software development system should be constructed in such a way as to comprehend most conceivable combinations of processors, memory, cache, and memory access limitations without requiring specialized debugging support. It should require no additional hardware support and very minimal software support from the debugger. The architecture of the software development system must be able to comprehend the memory access limitation of the entire system, i.e., which processors can read/write which parts of memory, manage cache coherency as a result of memory writes, and provide software breakpoint coherency. Methods must be provided to handle write accesses to shared memory from a debug session associated with a processor not having such access, to maintain cache coherency among the processors when changes are made to common shared memory, and to maintain software breakpoint coherency across multiple debug sessions.

FIG. 1illustrates the elements of a system for debugging embedded software applications executing on an embedded digital system comprised of multiple processors configured with shared memory. General-purpose personal computer100is connected to target hardware106with emulation controller104. Target hardware106is a digital system that includes processors110a–110n, memory112, and emulation logic108to support software debugging activities.

Processors110a–110nare connected to memory112, which holds the application program that is to be debugged. Processors110a–110nare not necessarily identical but each contains circuitry, e.g., scan chains connected to a test access port, to allow some level of emulation access to registers, local memory, etc. Memory112may be any combination of on-chip and off-chip memory. Some portions of memory112may be shared by processors110a–110n. Emulation logic108interacts with emulation controller104during the debugging of the application program. Typically, emulation controller104is connected to target hardware106through a JTAG test access port. Details of the general construction of such digital systems are well known and may be found readily elsewhere. For example. U.S. Pat. No. 5,072,418 issued to Frederick Boutaud, et al, describes a digital signal processor (DSP) in detail. U.S. Pat. No. 5,329,471 issued to Gary Swoboda et al, describes in detail how to test and emulate a DSP. General purpose computing system100hosts a software development system that incorporates software debugging and emulation software with which the user interacts through user interface102.

FIG. 2is a block diagram of the logical architecture of an embodiment of the software development system with user interface102that executes on personal computer100. The software development system is comprised of a set of tightly integrated modules providing tools to support the entire software development process for embedded software applications. At the top level, Integrated Tools Environment214comprises user interface102, a source code editor, a code profiling tool, and a project management tool. Environment214further comprises a general extension language (GEL) similar to C that lets the user create functions to extend the usefulness of the software development system. The GEL language includes a number of predefined functions that allow the user to control the state of the actual/simulated target, access the actual/simulated target memory locations, and to display results in the output window. The GEL language is described completely in the online documentation of the Texas Instruments' software development system Code Composer Studio, version 2.0.

The second level of this architecture comprises the tools for generating code (block216), for debugging code (block218), and for analyzing the performance of the code in real-time (block220). In addition, this level includes support for adding additional development tools as “plug-ins” (block222). A “plug in” is a software application that may be dynamically added to the software development system to extend the functionality of the system.

The third level provides the low-level support for debugging. It comprises an instruction set simulator (block224) for host debugging, software for configuring the debug resources available on the target hardware (block226), and software for interfacing to the target hardware (block228). An access mechanism230connects host computer100and target hardware106. In one embodiment, access mechanism230is embodied by emulation controller104.

FIG. 3presents the initial display of a setup utility for the software development system ofFIG. 2that is used to define the system configuration of the target hardware. This system configuration consists of one or more device drivers that handle communication with the target hardware plus other information and files that describe the characteristics of the target hardware. The specified system configuration is stored in a specially formatted file, the board data file, that is recorded in the system registry where it can be retrieved by the software development system when it is started. When the software development system is started, it uses the information in the specified system configuration to do any required initialization for communication with the target hardware. This initialization includes loading the required drivers and starting debug sessions for each processor in the target hardware.

The setup utility interface is divided into three panes: system configuration pane300, available board types pane302, and command/information pane304. System configuration pane300displays a hierarchical representation of the system configuration. The top level is called My System. It holds the system configuration and cannot be modified. The second level displays the target board and the emulation connection used for that board. This level corresponds to a particular device driver. The third level of hierarchy lists the processors on the target board.

Although a multiple processor configuration is represented as a series of boards, in fact each “board” is really either a single processor or a single emulator scan chain that could be attached to one or more boards with multiple processors. The device driver associated with the board comprehends all the processors on the scan chain.

The contents of available board types pane302change as selections are made in the system configuration pane300. When the My System icon is selected in system configuration pane300, available board types pane302lists all available target boards and simulators. Each of these entries represents the device driver for that target. When a target board or simulator is selected in system configuration pane300, available board types pane302lists the processors available for that target. The user may drag-and-drop items from available board types pane302to system configuration pane300. The setup utility does not allow the user to create an unsupported processor or target board configuration.

After adding a target board or simulator to system configuration pane300, the user may change the properties of that device. The user can specify the board name, the board data file, board properties, the processor configuration (for target boards that allow multiple CPUs) and startup GEL file(s).

Command/information pane304provides information describing the target board or simulator highlighted in available board types pane302. It also contains commands for importing a configuration file, installing or uninstalling a device driver, and adding a device driver to a system configuration.

FIG. 4illustrates the display of a parallel debug manager (PDM) that is invoked when the software development system ofFIG. 2is initialized with a configuration file describing a target system containing multiple processors. Debug block218ofFIG. 2includes the parallel debug manager ofFIG. 4. Using Open Dialog402, the user may open a separate debug window for any processor110on target hardware106. Each debug window will be associated with a debug session for the selected processor that was created when the software development system loaded the system configuration file for the target hardware. The parallel debug manager can be used to broadcast breakpoint commands to processors110in the JTAG scan path, as will be described later.

FIG. 5presents a block diagram of a prototypical embedded digital system comprised of multiple processors configured with shared memory that can be debugged using the software development system ofFIG. 1. Digital system500, which corresponds to target hardware106ofFIG. 1, contains processors510a–510f. Processors510a–510fhave access to shared memory subsystem512which is utilized as instruction memory. Shared memory subsystem512contains the application program or programs to be debugged. Emulation logic108interacts with emulation controller104during the debugging of the application program or programs loaded in shared memory subsystem512. Emulation logic108comprises support for:

Non-intrusive access to internal and external memory

Minimally-intrusive access to CPU and peripheral registers

Control of the execution of background code while continuing to service real-time interrupts

Break on a software breakpoint instruction (instruction replacement)

Break on a specified program or data access without requiring instruction replacement (accomplished using bus comparators).

Break on external attention-request from debug host or additional hardware

Break after the execution of a single instruction (single-stepping)

Control over the execution of code from device power-up

Non-intrusive determination of device status

Detection of a system reset, emulation/test-logic reset, or power-down occurrence

Detecting the absence of a system clock or memory-ready signal

Checking if global interrupts are enabled

Other embodiments may have a subset of these capabilities. The design of emulation logic for a digital system comprised of multiple processors is well known and is described in detail in U.S. Pat. Nos. 5,329,471 and 5,828,824 issued to Gary Swoboda, et al.

The sharing of instruction memory by multiple processors as illustrated inFIG. 5creates added complexity for the software development system used to debug applications on such hardware configurations. As described previously, a debug session for each processor is started when the software development system loads the system configuration file. Each debug window started with the PDM ofFIG. 4, while only having awareness of the associated processor, may possibly set or clear software breakpoints in shared memory. Other active debug sessions must be made aware of such changes or inconsistent execution results may occur. The software development system must have a method for maintaining the coherency of software breakpoints among the debug sessions.

FIG. 6presents a block diagram of a processor510of the digital system ofFIG. 5. Processor510is comprised of central processing unit (CPU)600, local dual access memories602, single access memory604, and instruction cache606. Local memory602is accessible as data memory only and local memory604is accessible both as program and data memory. Instruction cache606is connected to shared memory subsystem512by cache bus608. Emulation logic108has the same access to local memories602and604and to shared memory subsystem512as CPU600. If CPU600does not have write access to shared memory subsystem512, emulation logic108will not have write access to shared memory subsystem512.

FIG. 7is a block diagram illustrating emulation logic108ofFIG. 1in more detail. Emulation circuitry108provides common debug accesses (reading and writing of memory and registers) without direct CPU intervention through a Debug and Test Direct Memory Access (DT-DMA) mechanism108a. Because the DT-DMA mechanism uses the same memory access mechanism as the CPU, any read or write access that the CPU can perform in a single operation can be done via a DT-DMA memory access. The DT-DMA mechanism will present an address via address bus720(and data via interface710, in the case of a write) to the CPU, which will perform the operation during an open bus cycle slot. DT-DMA request signal721is asserted by the emulation circuitry to request a read or write transaction. Once memory812or830has provided the desired data, it is presented back to the DT-DMA mechanism. DT-DMA ready signal722is asserted by instruction buffer unit706to indicate that a requested data item is available to the emulation circuitry.

The DT-DMA mechanism can operate in either a preemptive or non-preemptive mode. In non-preemptive mode, the DT-DMA mechanism waits for the desired memory bus(es) to be unused for a cycle (referred to as a hole), at which point the DT-DMA mechanism uses it to perform the read or write operation. These memory holes will occur naturally while the CPU is running (e.g. while waiting on newly fetched data or during a pipeline protection cycle). A program memory hole will occur when the fetch queue is full, typically due to several consecutive instructions with no branches. In preemptive mode, a NULL is jammed into the decode stage of the pipeline, essentially creating a hole. Non-preemptive accesses to zero-wait state memory712take no cycles away from the CPU. If wait-stated memory730is accessed, the pipeline will stall during each wait-state, just as a normal memory access would cause a stall. CPU registers must always be accessed preemptively. Also, it is possible for the debug software to jam certain instructions into the pipeline using the DT-DMA mechanism. This must be done preemptively.

For a data write, Data Address Generation circuitry (DAGEN)722schedules a write request in response to a request721from the emulation circuitry and a DT-DMA address is placed on the address bus EAB. Write data is simultaneously placed on the E and F busses750in response to a control signal. A tag signal on address bus EAB752is also asserted by DAGEN722in response to the DT-DMA request so that the write transaction can be identified as such by instruction cache606, which monitors the write address bus EAB752. Coherence circuitry716monitors address bus EAB752and causes cache606to invalidate a cache entry, if the address of a cache entry matches the DT-DMA write address.

FIG. 8presents a block diagram of one embodiment of the data flow paths between the shared memory and the processors ofFIG. 5. CPUs600a–600fhave read access to shared memory subsystem512through cache buses608a–608fto fill instruction caches606a–606frespectively. However, only CPU600ahas write access to shared memory subsystem512. Emulation access port806provides emulation logic108access to shared memory subsystem512. Emulation access port806is connected to shared memory arbitration unit808via bi-directional bus802. The other side of emulation access port806is connected to CPU600aby bi-directional bus800. Emulation logic108is able to read and write local memories602and604on CPUs600a–600fbut only has write access to shared memory subsystem512through CPU600a. Emulation logic108uses CPU600ato perform any needed reads or writes to shared memory subsystem512, such as managing software breakpoints or loading programs. Note that CPUs600a–600fare all designed identically but only CPU600ais connected to emulation access port806.

The limited write access to shared instruction memory as illustrated byFIG. 8creates added complexity for the software development system used to debug applications on such hardware configurations. As described previously, a debug session for each processor is initiated by the software development system when the system configuration file is loaded. Each debug session requires write access through the emulation logic to shared instruction memory to carry out typical debug operations such as loading new code segments into shared memory or managing software breakpoints. Such write access is only available through CPU600aso the software development system must have a method for transferring write requests to shared instruction memory from the debug sessions for CPUs600b–600fto CPU600a.

Additional debugging complexity is introduced by the presence of instruction caches606a–606fin processors510a–510f. Because a location in common shared memory may be contained in one or more of instruction caches606a–606f, the caches must be invalidated when an emulation write occurs to shared memory subsystem512to insure coherence with the common shared memory. The method used to invalidate cache needs to balance hardware complexity against software efficacy. At one extreme, hardware support for multiprocessor bus snooping to invalidate all caches might be provided, but at high cost. At the other extreme, common shared memory segments can be made non-cacheable, sacrificing execution speed. A good middle ground alternative is to provide a method whereby the software development system can invalidate all caches. The software development system could invalidate the instruction cache of each processor having access to the common shared memory segment by performing the write to common shared memory on each processor. The drawbacks of this approach include wasted bandwidth due to multiple writes of the same data to common shared memory and temporary incoherence of the system as each cache is invalidated in turn.

Another limitation of this method for invalidating cache becomes apparent when the target hardware architecture limits the write access of the processors to shared memory such as in the embodiment ofFIG. 8. Maintaining cache coherence generally requires a write path to shared memory from all processors that have read access to the shared memory. Depending on the design of the cache hardware, either the entire cache is invalidated if an memory location is written that is contained in the cache or just the cache entry corresponding to the memory location is invalidated. An alternate approach to maintaining cache coherence must be employed when such a write path is not provided. One possible solution is to increase hardware cost by designing the system in such as way as to allow the emulator to write to memory even though the processor cannot. Another approach is to have the emulation software understand the organization of the cache and have it invalidate cache entries. This solution then ties cache invalidation capabilities to emulation software release. Each time a new cache organization is developed, new emulation software must be provided. A more efficient method for effecting instruction cache invalidation is desirable.

FIG. 9presents a flowgraph of a method used by the software development system ofFIG. 2to transfer a write request to a shared-memory location from a processor having only read access to that location to a processor which has write access. Such a method is advantageous when debugging a target hardware architecture in which two or more of the processors have shared memory and at least one of those processors does not have write access to the shared memory. At step900, a software memory map detailing how each processor in the target hardware views physical memory is created. This software memory map may be a single data structure or multiple data structures. The software memory map is created when the software development system ofFIG. 2loads the startup GEL file for each processor specified in the system configuration of the target hardware. A predefined GEL function, GEL_MapAddStr( ), is used in the startup file(s) to identify the shared memory segments of the target hardware in the memory map.

GEL_MapAddStr( ) has four parameters: address, page, length, “attribute”, and waitstate. The address parameter identifies the starting address of a range in memory. The page parameter identifies the type of memory in the address range: instruction memory, data memory, or I/O space. The length parameter defines the length of the range of memory. The attribute parameter is a string that defines one or more attributes for the specified memory range. The waitstate parameter defines the number of waitstates for memory range.

Two special attribute strings are used to specify shared memory: RAM|SHnC|CACHE and ROM|SHnC|CACHE. The first element of the attribute string must identify the type of access available to emulation logic108: RAM or ROM. The rest of the attributes can be specified in any order. RAM specifies that access to memory is read and write. ROM specifies that access to memory is read-only. The SHnC element of the attribute string is broken down as follows: the string “SH” specifies shared memory, the number n identifies the segment of memory being shared, and the string “C” is used to designate common shared memory, i.e. memory that contains code or data that will be accessed or executed by more than one processor, possibly simultaneously. The “C” designation causes the debugger to halt all processors that share the designated memory when a write occurs to that shared memory and to halt all processors when stepping over a breakpoint set in that shared memory. “C” is optional, but should always be appended as the default setting. The default settings for these actions can be overridden by setting shared memory options as described later in the discussion ofFIG. 15. The CACHE element of the attribute string causes the target driver to invalidate the cache when any processor writes to the shared memory block.

FIG. 10illustrates a memory map of one or more processors510of the digital system ofFIG. 5. As discussed earlier, various processors may have different memory maps. If emulation logic108has both read and write access to shared memory1000through a processor510, its associated startup GEL file will identify the shared memory by the GEL function call: GEL_MapAddStr(0xF40000, 0, RAM|SH1C|CACHE, 0). This function call indicates that there is common shared instruction memory beginning at address 0xF40000, emulation logic108has both read and write access to this shared memory through the processor, and the processor has an instruction cache. If emulation logic108has only read access to shared memory1000through a processor510, its associated startup GEL file will identify the shared memory by the GEL function call: GEL_MapAddStr(0xF40000, 0, ROM|SH1C|CACHE, 0). This function call indicates that there is common shared instruction memory beginning at address 0xF40000, emulation logic108has only read access to this shared memory through the processor, and the processor has an instruction cache. If the data flow paths for processors510a–510fare as illustrated byFIG. 6, the startup GEL file for processor510awill contain the GEL function call GEL_MapAddStr(0xF40000, 0, RAM|SH1C|CACHE, 0) to indicate that emulation logic108has write access to shared memory1000through it. The startup GEL files for processors510b–510fwill contain the GEL function call MapAddStr(0xF40000, 0, ROM|SH1C|CACHE, 0) to indicate that emulation logic108does not have write access to shared memory through them.

Shared memory segments may be in different addressable regions for different processors. That is, on processor A, the segment might start at 0x8000 and on processor B the same segment could start at 0x4000. Equivalent segment sizes are generally expected though segments of varying size may be specified and the behavior of the methods described herein is predictable. The segment number n in the SHnC element of the attribute string will be the same for both processors but the address will differ. The shared memory segment for processor A might be specified in the startup GEL file by the function call GEL_MapAddStr(0x8000, 0, RAM|SH1C|CACHE, 0) and the same segment for processor B might be specified by GEL_MapAddStr(0x4000, 0, ROM|SH1C|CACHE, 0).

Referring again toFIG. 9, in step902, debug sessions are activated for two or more processors in the system and at least one debug window is opened for one of the debug sessions. These debug sessions are comprised of the minimal functionality required to permit coordination of debug information among the processors. Using the parallel debug manager depicted inFIG. 4, the user selects open option400. In response to this selection, open dialog box402is displayed. Open dialog box402contains a list of all of the processors in the target hardware. Selecting processors from this list causes debug windows404to be activated for those processors.

As steps904and906indicate, all memory accesses from the active debug sessions are monitored to detect if a write request is made to a shared memory segment. If a write request to a shared memory segment is detected in step906, a check is made at step908to determine if the processor associated with the debug session making the write request has write access to shared memory location. If the processor does have write access, it is selected to perform the write as indicated by step910. If it does not have write access, the memory maps of the other processors in the target system are searched at step912to locate a processor that does have write access to the shared memory location. As step914shows, the processor found in step912is selected to perform the write request. At step916, the write request is passed to the processor selected at step910or step914.

FIG. 11depicts the logical architecture of the software development system ofFIG. 2when configured for debugging a target hardware system with multiple processors and shared memory such as that depicted inFIG. 5. Memory maps1102a–1102fare a software representation of the memory layout of target hardware500. These memory maps are created when the software development system is initialized as described in the discussion of step900above. Drivers1108a–1108fare also instantiated for processors510a–510f. These drivers provide the communication interface between debug sessions1104a–1104fand processors510a–510f. Debug sessions1104a–1104fare also activated for processors510a–510frespectively. Each debug session1104comprises a breakpoint manager1110that manages all software breakpoints for the session.

Bus manager1106is a software layer between debug sessions1104a–1104fand drivers1108a–1008fthat is responsible for the activities depicted in step908through step916of the method ofFIG. 9. When bus manager1006receives a write request to shared memory512from a debug session1104, the bus manager checks the memory map1102for the debug session1104making the write request to see if the processor510for which the debug session1104was activated has write access to the memory location in shared memory512. If the processor510does have write access to the memory location, bus manager1106sends the write request to the driver1108for the processor510associated with the debug session1104that initiated the write request. If the processor510does not have write access, bus manager1106searches the memory maps1102a–1102fto find a second processor510that does have write access to the shared memory location. Bus manager1106then sends the write request to driver1108for the selected second processor510.

FIGS. 12A and 12Bpresent a flowgraph of another method used by the software development system ofFIG. 2to transfer a write request to a shared memory location from a processor having read-only access to that location to a processor which has write access. This method is the method ofFIG. 9with additional improvements. If the processors in the target hardware have instruction caches and share instruction memory, the instruction caches must be invalidated when a value is written to the shared memory. Step900as described above is enhanced to include denoting in the software memory map those areas of memory that contain instructions and those that contain data. Steps902–916are as described previously Subsequent to step916, execution moves to step1200ofFIG. 12B. At step1202, a check is made to determine if the write request was to instruction memory. If the write request is not to instruction memory, the method resumes at step904. Otherwise, at step1204, the memory map is searched to locate all other processors that share the memory location. At step1206, the write request is broadcast to all processors located in step1204. Each processor will perform instruction cache coherency updates if required as indicated by step1208. The method then resumes at step904.

Returning toFIG. 11, the steps of the method ofFIGS. 12A–12Bthat are analogous to those of the method ofFIG. 9are executed by the software development system as described in the previous discussion ofFIG. 11. Memory maps1102a–1102fare created as discussed with step900, using the page parameter of the GEL_MapAddStr( ) function to denote whether the shared memory segment is instruction memory or data memory. The determination as to whether the write request is to instruction memory or data memory (step1202) is made by bus manager1106by looking at the memory map1102associated with the debug session1104that made the write request. If the write request is to instruction memory, bus manager1106searches all memory maps1102to locate processors510that share the memory location. It broadcasts the write request to the drivers1108of the located processors510. The drivers1108cause instruction cache coherency updates to occur where required on their associated processors510.

In another embodiment, steps1206and1208are accomplished in a more efficient way through a special write request. The special write request, which is broadcast to all processors located in step1204, indicates that the data has already been written to the shared memory location by another processor. Therefore, the processors receiving this special write request do not necessarily have to perform the write. But, if necessary, the processors receiving the special write request will perform instruction cache coherency updates. The processors may accomplish the cache coherency updates without requiring an actual write to memory through the use of special emulation circuitry as described above in the discussion ofFIG. 7.

In other embodiments, the method ofFIG. 12may be altered to handle the invalidation of different types of caches including instruction caches, data caches, and translation lookaside buffers (TLB) used for mapping virtual memory addresses to physical addresses. Step1202, the check for a write to instruction memory, may be removed if two or more of the different types of caches are present, or may be altered to check for a write to data cache or write that affects the TLB has occurred if only data cache or only TLB support is present. . At step1208, any type of cache that is affected by the write is invalidated. And, steps1206and1208may be further enhanced by providing a special write request as previously described.

FIGS. 13A–13Dpresent flowgraphs of methods for maintaining the coherency of software breakpoints in common shared memory used by the software development system ofFIG. 2. To maintain coherency of software breakpoints across multiple debug sessions, any software breakpoint set or cleared in common shared memory must be set or cleared for every processor having read access to the common shared memory.FIG. 13Apresents a flowgraph for a method to maintain software breakpoint coherency across multiple debug sessions. At step1300, a software memory map detailing how the processors in the target system may access and use memory is created. At step1302, two or more debug sessions are activated and at least one debug window is opened. As indicated by step1303, the method terminates when the debug sessions are terminated. At step1304, a check is made to determine if one of the debug sessions has requested that a software breakpoint be set in common shared memory. If such a request has been made, at step1306the software breakpoint is set such that all debug sessions are notified of the setting of the breakpoint and the method continues at step1303. If the setting of a breakpoint has not been requested, the method continues at step1305where a check is made to see if one of the active debug sessions has requested that a software breakpoint in common shared memory be cleared. If not, the method continues at step1303. If a clear request has been made, at step1307, the software breakpoint is cleared such that all active debug sessions are notified that the breakpoint has been cleared. The method then continues at step1303.

The software memory map is created and the debug sessions are activated as described withFIG. 9above. Bus manager1106ofFIG. 11intercepts the software breakpoint setting and clearing requests from each active debug session1104and causes all debug sessions1104to be notified of any breakpoint changes in common shared memory. When a breakpoint is set or cleared in common shared memory by a debug session1104, bus manager1106searches memory maps1102to locate all processors601having read access to the common shared memory and their associated debug sessions. Bus manager1106interacts with the breakpoint manager1110of each located debug session1104to update the breakpoint table for the debug session appropriately.

FIG. 13Bpresents a flowgraph of an improvement to the method ofFIG. 13A. Steps1308–1310replace step1306ofFIG. 13A. At step1308, the software memory map is searched to locate all processors having read access to the common shared memory location where the software breakpoint is to be set. At step1309, the software representation maintained for software breakpoints for each located processor is updated to reflect the setting of the breakpoint. At step1310, the software breakpoint instruction is written to the common shared memory location.

FIG. 13Cpresents a flowgraph of an improvement to the method ofFIG. 13A. Steps1311–1313replace step1307ofFIG. 13A. At step1311, the original instruction store in the software representation maintained for software breakpoints is written into the common shared memory location that contains the software breakpoint instruction. At step1312, the software memory map is searched to locate all processors having read access to the common shared memory location where the software breakpoint was set. At step1313, the software representation maintained for software breakpoints for each located processor is updated to reflect the removal of the breakpoint.

FIG. 13Dpresents a flowgraph of an improvement to the method ofFIG. 13A. Steps1314to1317have been added to incorporate a method for stepping over a software breakpoint in common shared memory or resuming execution after hitting a breakpoint in common shared memory. At step1305, if there is no request to clear a breakpoint, the method continues at step1314. At step1314, a check is made to determine if there is a request to step over a software breakpoint in common shared memory or resume execution after hitting a breakpoint in common shared memory. If there is not, the method resumes at step1303. If there is such a request, at step1315the software breakpoint is cleared in such a way that all debug sessions are notified that the breakpoint has been removed. At step1316, the processor for which the request was made is stepped to the instruction after the shared memory location containing the software breakpoint. At step1317, the software breakpoint is again set such that all debug sessions are notified of the setting of the breakpoint.

The methods ofFIGS. 13A–13Dmay be further improved to maintain coherency of software breakpoints on target systems such as that presented inFIG. 8where all processors do not have write access to the common shared memory by incorporating the methods ofFIG. 9andFIG. 12. And, for target systems where the processors have cache, the cache coherency method ofFIG. 14may be incorporated into the methods ofFIGS. 13A–13D.

FIG. 14presents a flowgraph of a method for transparently maintaining cache coherency used by the software development system ofFIG. 2when debugging a multiple processor system with common shared instruction memory. At step1400, a software memory map is created. In this software memory map are indications as to whether or not the shared memory locations contain program instructions and whether or not a processor has an instruction cache. At step1402, one or more debug sessions are activated. As indicated by step1404, the method is used until all debug sessions are terminated. At step1406, a check is made to see if a debug session has requested a write to shared memory. If not, the method continues at step1404. If a write to shared memory has been requested, the write request is passed to the processor associated with the debug session making the request for execution at step1407. At step1408, a check is made to determine if the memory location written is in shared instruction memory. If it is not, the method continues at step1404. If the memory location written is in shared instruction memory, at step1410the software memory map is searched to locate all processors having read access to the shared memory location. At step1412, the write request is broadcast to all process having the read access. At step1414, instruction cache coherency updates are performed if necessary as a result of the write to instruction memory. The method then continues at step1404.

An enhanced version of the method ofFIG. 14is provided by replacing step1407with steps908to916of the method ofFIG. 9such that the cache coherency method will work on target hardware architectures in which all processors do not have write access to common shared instruction memory such as the architecture depicted inFIG. 8. An additional enhancement is provided by incorporating in step1414the use of a special write request as described previously with steps1206and1208ofFIG. 12.

In an embodiment, the cache coherency methods are implemented by the logical architecture ofFIG. 11in which bus manager1106handles shared memory access issues so that debug sessions1104are not required to have knowledge of the actual memory usage of their associated processors. Bus manager1106monitors all write requests from the debug sessions1104to detect any requests to write to shared instruction memory. If such a write request is made by a debug session1104, bus manager1106sends the write request to the driver1108for the processor510associated with the requesting debug session1104. Bus manager1106then searches memory maps1102to locate all processors510having read access to the location in shared instruction memory that has been changed and notifies the driver1108of each located processor510that the write has occurred. Each notified driver1108then takes appropriate action to cause the instruction cache, if any, of the associated processor510to be updated if necessary.

In other embodiments the method ofFIG. 14may be altered to handle the invalidation of different types of caches including instruction caches, data caches, and translation lookaside buffers (TLB) used for mapping virtual memory addresses to physical addresses. At step1400, indications of the presence of any type of cache on the processors are included in the software memory map, Step1408, the check for a write to instruction memory, may be removed if two or more of the different types of caches are present, or may be altered to check for a write to data cache or a write that affects the TLB has occurred if only data cache or only TLB support is present. At step1414, any type of cache that is affected by the write is invalidated. Enhanced versions, as described with the discussion ofFIG. 14above, should be obvious to one skilled in the art.

FIG. 15presents a representation of a dialog window of the software development system ofFIG. 2that permits various options regarding shared memory to be changed by the user while debugging an application. As a general rule, to insure execution coherency among multiple processors having common shared memory, all processors having read access to a shared memory location that is to be written should be halted during a write to that location. If the shared memory location contains a software breakpoint, that breakpoint will be cleared and reset during the write which could permit invalid code to be executed or cause a breakpoint to be missed if all affected processors are not halted. In addition, the data in that location may be incorrect if the processor was executing.

When stepping over a software breakpoint that is set in common shared memory or resuming execution after hitting the breakpoint, the breakpoint is first cleared, then the code is stepped, and finally the breakpoint is reset. If other processors execute code in that memory location during this time, they could miss the breakpoint.

However, halting the processors does have an adverse impact on any real-time execution behavior of the application. If the user wishes to maximize execution in favor of real-time behavior and risk losing execution coherency, he may use the dialog ofFIG. 15or execute special GEL functions to toggle whether or not affected processors should be halted during a write to shared memory or when a software breakpoint in shared memory is stepped over. Alternatively, if the user knows a shared memory segment is not accessed in certain processors, he can choose not to specify the shared segment in the configuration file for those processors or use GEL commands to remove the segment from the software memory map for those processors.

Option1501allows the user to override the default action when writing to a common shared memory location. The user clicks on the check box to toggle this option. Alternatively, the user can execute the GEL functions GEL_SharedMemHaltOnWriteOff( ) and GEL_SharedMemHaltOnWriteOn( ).

Option1502allows the user to override the default action when stepping over a software breakpoint (or resuming execution after hitting a breakpoint) that is set in a common shared memory location. The user clicks on the check box to toggle this option. Alternatively, the user can execute the GEL functions GEL_SharedMemHaltOnStepOff( ) and GEL_SharedMemHaltOnStepOn( ).

FIGS. 16A–16Cillustrate three common configurations of shared memory in target hardware106ofFIG. 1. InFIG. 16A, processor1602and processor1604have read and write access through read circuitry1622and write circuitry1624to all locations in shared memory1620. InFIG. 16B, processor1602and processor1604have read access to all locations in shared memory1620through read circuitry1622. However, each processor has write access through write circuitry1626only to segments of shared memory1620that it owns and segment ownership is not shared. Processor1602will not be able to write to shared memory locations owned by processor1604and vice versa.

InFIG. 16C, shared memory1620is only nominally shared between processor1602and processor1604. Each processor has exclusive read and write access to a portion of shared memory1620. Processor1602has read and write access to private memory1634through access circuitry1630and processor1604has read and write access to private memory1636through access circuitry1632.

In addition to the simple configurations shown inFIGS. 16A–16C, target hardware106may have more complex shared memory configurations that are combinations of these. For example, a four processor digital system could be created in which two of the processors share a memory area with each processor having write access to half of the total shared memory. The other two processors in turn share their own area of memory similarly. The methods and systems described herein comprehend the simple shared memory configurations and the more complex configurations.

FIG. 17illustrates the system ofFIG. 1as expanded to allow debugging of software applications running on a hardware architecture comprising multiple digital systems with shared memory. General-purpose personal computer100is connected to target hardware106a–106nwith emulation controllers104a–104n. Target hardware106a–106nare digital systems that include processors110a–110z, memory112a–112n, and emulation logic108a–108nto support software debugging activities. Memory112may be any combination of on-chip and off-chip memory. Processors110a–110zare connected to off-chip memory132.

The fact that a software application to be debugged is being executed on a single target system as illustrated inFIG. 1or on a multiple board target system as illustrated inFIG. 17is irrelevant to the operation of the present invention. For purposes of simplicity in this specification, execution on a single target system is assumed. Extension of the invention to multiple board target systems should be obvious to one skilled in the art.

As used herein, “associated” means a controlling relationship, such as a memory resource that is controlled by an associated port.

While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various other embodiments of the invention will be apparent to persons skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications of the embodiments as fall within the true scope and spirit of the invention.