Metal routing techniques

Various implementations described herein are directed to a method for identifying pre-routed metal lines in a higher layer of a multi-layered structure. The method may recognize gaps in the pre-routed metal lines of the higher layer, and also, the method may automatically fill the gaps with conductive stubs to modify the pre-routed metal lines in the higher layer as a continuous metal line with an extended length.

BACKGROUND

In conventional circuit designs, lower-level metal layers may show degradation as compared to higher metal layers. Due to scaling in advanced process nodes, the metal layer resistance may substantially degrade with extended use. The routing of critical signals in the lower-level metals may cause significant performance degradation because of the high-wire resistance. In some cases, the performance metal routing is critical for low-level memories when compared to larger memories, such as, e.g., cache memories. For instance, it may be more critical to speed-up timing of low-level memories due to continuous increases in clock computing frequencies. In some cases, faster timing of clock computing frequencies in low-level memories would boost overall computing performance. As such, there exists a need to overcome deficiencies in conventional circuit designs by improving the performance of metal routing that may be considered critical for some low-level memory applications.

DETAILED DESCRIPTION

Various implementations described herein are directed to metal routing fabrication schemes and techniques for various circuit applications in physical design. For instance, the various schemes and techniques described herein may provide for flexible top-metal usage schemes and techniques that improve performance. Also, various metal routing fabrication schemes and techniques described herein provide for a novel metal routing architecture in physical layout design of circuit layout structures by using top-metal layers to reduce wire-resistance and/or reduce wire-capacitance so as to thereby improve performance.

In some implementations, higher-metal stacks may be reserved for routing global signals that fly over each sub-bank in a multi-bank memory design. The higher-metal stacks may be programed to perform different functions based on different memory configurations, and the critical signals within a given memory bank may be pre-routed in lower level metal, wherein alternating metal layers are disposed perpendicular to each other in a vertical stack configuration. For instance, even metal layers (e.g., M0, M2, M4, etc.) may be disposed with a horizontal orientation, and also, poly layer along with odd metal layers (e.g., M1, M3, M5, etc.) may be disposed with a vertical orientation. In some flexible-bank configurations, the top-metal layers (e.g., M3, M4) may be programmed to send the buffered input/output signals from the macro memory left-edge to each individual bank, where they are used to accomplish local buffering so as to control individual banks. In some cases, the critical signals within the individual banks that remain in lower metal layers (e.g., M1, M2) may be pre-routed, and the same top-metal layers (e.g., M3, M4) that are reserved for signal-routing may be unused as the inputs are in the middle itself and no buffering is needed.

Some schemes and techniques described herein may be used to program tracks to strap the lower-level metals for critical signal nets (e.g., M4 may be strapped to M2, and M3 may be strapped to M1). These straps may be strategically programmed, and also, the remaining top-metal that is unused is left unprogrammed and floating to reduce capacitance on the critical signal nets. In this instance, the critical signal's resistance may be significantly reduced so as to improve performance. In reference to some memory instances, such as for larger multi-bank memory instances (e.g., flexible bank: FB=4), stub programming may be applied and used to provide longer routes over larger distances to farther banks. In reference to other memory instances, such as for smaller 2-bank memory instances (e.g., flexible bank: FB=2), via programming may be applied and used to strap and improve resistance. By using via-pillars at the source and the destination, the effective via-resistance for some inter-layer vias may be reduced, and also, combination of stub and via-programming may be used to make these top-metal layers flexible in some flexible bank (FB) designs.

Various implementations of providing metal routing architecture will be described herein with reference toFIGS.1-7.

FIGS.1A-1Billustrate diagrams of metal routing architecture in accordance with various implementations described herein. In particular,FIG.1Aillustrates a diagram100A of metal routing architecture104A, andFIG.1Billustrates a diagram100B of metal routing architecture104B. The metal routing architectures104A,104B provide for flexible top-metal (or high metal) usage schemes and techniques for improving performance. For instance, as shown inFIGS.1A-1B, the various metal routing schemes and techniques described herein may be used to extend higher metal lines to improve performance.

In various implementations, the metal routing architecture104A,104B shown inFIGS.1A,1Bmay be implemented as a system or a device having various integrated circuit (IC) components that are arranged and coupled together as an assemblage or combination of parts that provide for physical circuit designs and related structures. In some instances, a method of designing, providing and/or fabricating the metal routing architecture104A,104B inFIGS.1A,1Bas an integrated system or device may involve use of the various IC circuit components described herein so as to thereby implement various circuit fabrication schemes and techniques associated therewith. Moreover, the metal routing architecture104A,104B may be integrated with computing circuitry and related components on a single chip, and the metal routing architecture104A,104B may be implemented and incorporated in embedded systems for automotive, electronic, mobile, server and IoT applications.

As shown inFIG.1A, the metal routing architecture104A may include multiple layers (LM, HM) that are arranged and vertically stacked in a multi-layered structure. In some implementations, the multiple layers (LM, HM) may include a lower layer (LM) and a higher layer (HM), wherein the lower layer (LM) may be referred to as a bottom layer, and wherein the higher layer (HM) may be referred to as a top layer. The metal routing architecture104A may include pre-routed metal lines114formed in the higher layer (HM) of the multi-layered structure, and also, the metal routing architecture104A may include pre-routed metal lines118formed in the lower layer (LM) of the multi-layered structure. Also, in various instances, the metal routing architecture104A may include gaps (open) in the pre-routed metal lines114of the higher layer (HM). Moreover, in some instances, as shown inFIG.1B, the gaps (open) may be filled with conductive stubs (stub) so as to thereby modify the pre-routed metal lines114in the higher layer (HM) as a continuous metal line124having an extended length that is longer than the pre-routed metal lines118in the lower layer (LM).

In some implementations, in reference toFIG.1B, the metal routing architecture104B may be manufactured, or caused to be manufactured, as integrated circuitry along with the pre-routed metal lines114with the stubs (stub) in the higher layer (HM) as the continuous metal line124with the extended length. Also, in this instances, the metal routing architecture104B may be manufactured, or caused to be manufactured, as the integrated circuitry along with the pre-routed metal lines118in the lower layer (LM). The multi-layered structure may also include the multiple layers (LM, HM) including the higher layer (HM) and a lower layer (LM) that is disposed beneath the higher layer (HM). Moreover, the multiple layers (LM, HM) may also be arranged in a stack configuration with the higher layer (HM) disposed above the lower layer (LM). The pre-routed metal lines118in the lower layer (LM) may have a length that is less than a length of the pre-routed metal lines114of the higher layer (HM).

In various implementations, as shown inFIGS.1A-1B, the gaps (open) may be automatically filled with conductive stubs (stub), which may refer to extending the pre-routed metal lines114in the higher layer (HM) as the continuous metal line124with the extended length such that the length of the pre-routed metal lines114of the higher layer (HM) is greater than the length of the pre-routed metal lines118in the lower layer (LM). In some instances, as shown inFIG.1A, the gaps (open) in the pre-routed metal lines118of the higher layer (HM) may refer to spatial openings that are formed between portions of the pre-routed metal lines118of the higher layer (HM). Further, as shown inFIG.1B, the stubs (stub) may refer to conductive branches that bridge the spatial openings that are formed between the portions of the pre-routed metal lines118of the higher layer (HM). Moreover, the continuous metal lines124formed by modifying the pre-routed metal lines114in the higher layer (HM) may be used to achieve longer lengths of conductive metal lines124for improved transmission of critical signals between circuit components in a power grid network.

FIGS.2A-2Billustrate diagrams of metal routing architecture in accordance with various implementations described herein. In particular,FIG.2Aillustrates a diagram200A of metal routing architecture204A, andFIG.2Billustrates a diagram200B of metal routing architecture204B. The metal routing architectures204A,204B provide for flexible top-metal (or high metal) usage schemes and techniques for improving performance. For instance, as shown inFIGS.2A-2B, the various metal routing schemes and techniques described herein may be used to couple lower metal lines to higher metal lines to improve performance.

In various implementations, the metal routing architecture204A,204B shown inFIGS.2A,2Bmay be implemented as a system or a device having various integrated circuit (IC) components that are arranged and coupled together as an assemblage or combination of parts that provide for physical circuit designs and related structures. In some instances, a method of designing, providing and/or fabricating the metal routing architecture204A,204B inFIGS.2A,2Bas an integrated system or device may involve use of the various IC circuit components described herein so as to thereby implement various circuit fabrication schemes and techniques associated therewith. Moreover, the metal routing architecture204A,204B may be integrated with computing circuitry and related components on a single chip, and the metal routing architecture204A,204B may be implemented and incorporated in embedded systems for automotive, electronic, mobile, server and IoT applications.

As shown inFIG.2A, the metal routing architecture204A may include multiple layers (LM, HM) that are arranged and vertically stacked in a multi-layered structure. In some implementations, the multiple layers (LM, HM) may include a lower layer (LM) and a higher layer (HM), wherein the lower layer (LM) may be referred to as a bottom layer, and wherein the higher layer (HM) may be referred to as a top layer. The metal routing architecture204A may include pre-routed metal lines214formed in the higher layer (HM) of the multi-layered structure, and also, the metal routing architecture204A may include pre-routed metal lines218formed in the lower layer (LM) of the multi-layered structure. Also, in various instances, the metal routing architecture204A may include gaps (open) in the pre-routed metal lines214of the higher layer (HM). Also, in some instances, as shown inFIG.2B, one or more gaps (open) may be filled with conductive stubs (stub) so as to thereby modify the pre-routed metal lines214in the higher layer (HM) as a continuous metal line224having an extended length that is longer than the pre-routed metal lines218in the lower layer (LM).

In some implementations, in reference toFIG.1A, the metal routing architecture104A may include the pre-routed metal lines214,218in the multiple layers (LM, HM) of the multi-layered structure. Also, the multiple layers (LM, HM) may include one or more first pre-routed metal lines218in a lower layer (LM) as a first layer of the layers, and also, the multiple layers (LM, HM) may include one or more second pre-routed metal lines214in a higher layer (HM) as a second layer of the layers. Also, as shown inFIG.2B, the first pre-routed metal line218may be coupled to one or more second pre-routed metal lines214with conductive vias (via) that extend between the first layer (LM) and the second layer (HM).

In some implementations, in reference toFIG.1B, the metal routing architecture104B may be manufactured, or caused to be manufactured, as integrated circuitry with the first pre-routed metal line218coupled to the one or more second pre-routed metal lines214with the conductive vias (via) that extend between the first layer and the second layer. Also, the metal routing architecture104B may include gaps (open) in the second pre-routed metal line214of the second layer (HM), and in some instances, the gaps (open) may be filled with conductive stubs (stub) so as to modify the second pre-routed metal lines214in the second layer (HM) as a continuous metal line224with an extended length. The first layer (LM) may refer to a lower metal layer (LM) that is disposed underneath the second layer (HM), and the second layer (HM) may refer to a higher metal layer (HM) that is different than the first layer (LM), and also, the layers (LM, HM) may be arranged in a stack configuration with the higher metal layer (HM) disposed above the lower metal layer (LM).

In some implementations, in reference toFIGS.1A-1B, the first pre-routed metal line218may be formed in the lower layer (LM), and the first pre-routed metal line218may have a length that is less than a length of the second pre-routed metal line214of the higher layer (HM). Also, as shown in reference toFIG.2B, one or more gaps (open) may be filled with conductive stubs (stub) that are used extend the second pre-routed metal line214in the higher layer (HM) as the continuous metal line224with the extended length such that the length of the extended pre-routed metal lines224of the higher layer (HM) is greater than the length of the pre-routed metal lines218in the lower layer (LM). Also, the gaps (open) formed in the second pre-routed metal lines214of the higher layer (HM) may be associated with spatial openings that are formed between portions of the second pre-routed metal lines214of the higher layer (HM). Also, the stubs (stub) may refer to conductive branches that bridge the spatial openings that are formed between the portions of the second pre-routed metal lines214of the higher layer (HM).

FIGS.3A-3Billustrate diagrams of metal routing architecture in accordance with various implementations described herein. In particular,FIG.3Aillustrates a diagram300A of metal routing architecture304A, andFIG.3Billustrates a diagram300B of metal routing architecture304B. The metal routing architectures304A,304B provide for flexible top-metal (or high metal) usage schemes and techniques for improving performance. For instance, as shown inFIGS.3A-3B, the various metal routing schemes and techniques described herein may be used to extend higher metal lines and/or couple lower metal lines to the higher metal lines so as to thereby improve performance.

In various implementations, the metal routing architecture304A,304B shown inFIGS.3A,3Bmay be implemented as a system or a device having various integrated circuit (IC) components that are arranged and coupled together as an assemblage or combination of parts that provide for physical circuit designs and related structures. In some instances, a method of designing, providing and/or fabricating the metal routing architecture304A,304B inFIGS.3A,3Bas an integrated system or device may involve use of the various IC circuit components described herein so as to thereby implement various circuit fabrication schemes and techniques associated therewith. Moreover, the metal routing architecture304A,304B may be integrated with computing circuitry and related components on a single chip, and the metal routing architecture304A,304B may be implemented and incorporated in embedded systems for automotive, electronic, mobile, server and IoT applications.

As shown inFIG.3A, the metal routing architecture304A may include multiple layers (LM, HM) that are arranged and vertically stacked in a multi-layered structure. In some implementations, the multiple layers (LM, HM) may include a lower layer (LM) and a higher layer (HM), wherein the lower layer (LM) may be referred to as a bottom layer, and wherein the higher layer (HM) may be referred to as a top layer. The metal routing architecture304A may include pre-routed metal lines314formed in the higher layer (HM) of the multi-layered structure, and also, the metal routing architecture304A may include pre-routed metal lines318formed in the lower layer (LM) of the multi-layered structure. Also, in various instances, the metal routing architecture304A may have gaps (open) in the pre-routed metal lines314of the higher layer (HM). Further, in some instances, as shown inFIG.3B, the gaps (open) may be filled with conductive stubs (stub) so as to thereby modify the pre-routed metal lines314in the higher layer (HM) as a continuous metal line324having an extended length that is longer than the pre-routed metal lines318in the lower layer (LM).

In some implementations, in reference toFIG.3B, the metal routing architecture304B may be manufactured, or caused to be manufactured, as integrated circuitry along with the longer pre-routed metal lines314in the higher layer (HM) as the continuous metal line324with the extended length. Also, in various instances, the metal routing architecture304B may be manufactured, or caused to be manufactured, as integrated circuitry along with the shorter pre-routed metal line218that is coupled to the longer pre-routed metal line214with the conductive vias (via) that extend between the lower metal layer (LM) and the higher metal layer (HM). Also, the metal lines314,318in the multiple layers (LM, HM) of the multi-layered structure may refer to shorter metal lines318in the lower layer (LM) of the multiple layers and to longer metal lines314in the higher layer (HM) of the multiple layers. Also, in some instances, the gaps (open) in the longer metal lines314of the higher layer (HM) may be filled with conductive stubs (stub) so as to modify the longer metal lines314in the higher layer (HM) as the continuous metal line324with an extended length. Also, the shorter metal line318in the lower layer (LM) may be coupled to the longer metal line324with conductive vias (via) that extend between the lower layer (LM) and the higher layer (HM).

In various implementations, the metal lines314,318may refer to pre-routed metal lines, wherein the shorter metal line318refers to a shorter pre-routed metal line, and wherein the longer metal line318refers to a longer pre-routed metal line. Also, in various instances, the longer metal line314may have a longer length that is greater than a shorter length of the shorter metal line318. Also, the gaps (open) may be filled with conductive stubs (stub), which refers to extending the longer pre-routed metal line314in the higher layer (HM) as the continuous metal line324with the extended length such that a length of the longer pre-routed metal line314of the higher layer (HM) is greater than a length of the shorter pre-routed metal line318in the lower layer (LM). Further, the gaps (open) in the longer pre-routed metal line314of the higher layer (HM) may refer to spatial openings that are formed between portions of the longer pre-routed metal lines314of the higher layer (HM). Moreover, the stubs (stub) may refer to conductive branches that bridge the spatial openings that are formed between the portions of the longer pre-routed metal lines314of the higher layer (HM).

FIGS.4-6illustrate diagrams of methods for providing metal routing architecture in accordance with implementations described herein. In particular,FIG.4shows a method400for extending higher metal lines in reference toFIGS.1A-1B,FIG.5shows a method500for coupling lower metal lines to higher metal lines in reference toFIGS.2A-2B, and also,FIG.6shows a method600for extending higher metal lines and coupling lower/higher metal lines in reference toFIGS.3A-3B. The various methods400,500,600for providing metal routing architectures may be used to implement flexible top-metal (or high metal) usage schemes and techniques for improving performance. In larger multi-bank memory instances (e.g., FB=4), stub programming may be applied and used to provide longer routes over larger distances to farther banks. Further, in smaller two-bank memory instances (e.g., FB=2), via programming may be applied and used to strap and improve resistance. In some instances, the methods inFIGS.4-6may be configured to program metal stacks in the higher layer so as to perform various different functions based on different memory configurations, wherein stub programming may be applied and used to provide longer routes over larger distances to farther banks in larger multi-bank memory configurations, and wherein via programming may also be applied and used to strap the pre-routed metal lines and improve resistance in smaller multi-bank memory configurations.

FIG.4illustrates a process diagram of a method400for providing metal routing architecture in accordance with implementations described herein.

It should be understood that even though method400indicates a particular order of operation execution, in some cases, various portions of operations may be executed in a different order, and on different systems. In other cases, additional operations and/or steps may be added to and/or omitted from method400. Also, method400may be implemented in hardware and/or software. If implemented in hardware, method400may be implemented with components and/or circuitry, as described in reference toFIGS.1A-1B. If implemented in software, method400may be implemented as a program or software instruction process configured for providing metal routing architecture, as described herein. Also, if implemented in software, instructions related to implementing the method400may be stored in memory and/or a database. For instance, a computer or some other type of computing device having a processor and memory may be configured to perform method400.

As described in reference toFIG.4, the method400may be used for fabricating and/or manufacturing, or causing to be fabricated and/or manufactured, an integrated circuit (IC) that implements the various metal routing schemes and techniques in physical design as described herein for providing metal routing architecture using various associated devices, components and/or circuitry described herein.

At block410, method400may identify pre-routed metal lines in a higher layer of a multi-layered structure. At block420, method400may recognize gaps in the pre-routed metal lines of the higher layer. At block430, method400may automatically fill the gaps with conductive stubs to modify the pre-routed metal lines in the higher layer as a continuous metal line with an extended length. Moreover, method400may manufacture, or cause to be manufactured, integrated circuitry with the pre-routed metal lines in the higher layer as the continuous metal line with the extended length.

In various implementations, the multi-layered structure may include multiple layers including, e.g., the higher layer and a lower layer that is disposed beneath the higher layer, and also, the multiple layers may be arranged in a stack configuration with the higher layer disposed above the lower layer. Also, method400may be configured to identify pre-routed metal lines in the lower layer of the multi-layered structure, and the lower layer may have the pre-routed metal lines with a length that is less than a length of the pre-routed metal lines of the higher layer. In some instances, automatically filling the gaps with conductive stubs may refer to extending the pre-routed metal lines in the higher layer as the continuous metal line with the extended length such that the length of the pre-routed metal lines of the higher layer is greater than the length of the pre-routed metal lines in the lower layer.

In some implementations, the gaps in the pre-routed metal lines of the higher layer may refer to spatial openings that are formed between portions of the pre-routed metal lines of the higher layer, and the stubs may refer to conductive branches that bridge the spatial openings that are formed between the portions of the pre-routed metal lines of the higher layer. Also, the continuous metal lines formed by modifying the pre-routed metal lines in the higher layer may be used to achieve longer lengths of conductive metal lines for improved transmission of critical signals between circuit components in a power grid network.

FIG.5illustrates a process diagram of a method500for providing metal routing architecture in accordance with implementations described herein.

It should be understood that even though method500indicates a particular order of operation execution, in some cases, various portions of operations may be executed in a different order, and on different systems. In other cases, additional operations and/or steps may be added to and/or omitted from method500. Also, method500may be implemented in hardware and/or software. If implemented in hardware, method500may be implemented with components and/or circuitry, as described in reference toFIGS.2A-2B. If implemented in software, method500may be implemented as a program or software instruction process configured for providing metal routing architecture, as described herein. Also, if implemented in software, instructions related to implementing the method500may be stored in memory and/or a database. For instance, a computer or some other type of computing device having a processor and memory may be configured to perform method500.

As described in reference toFIG.5, the method500may be used for fabricating and/or manufacturing, or causing to be fabricated and/or manufactured, an integrated circuit (IC) that implements the various metal routing schemes and techniques in physical design as described herein for providing metal routing architecture using various associated devices, components and/or circuitry described herein.

At block510, method500may identify pre-routed metal lines in layers of a multi-layered structure. At block520, method500may recognize a first pre-routed metal line in a first layer of the layers. At block530, method500may recognize a second pre-routed metal line in a second layer of the layers. At block540, method500may automatically coupling the first pre-routed metal line to the second pre-routed metal line with conductive vias that extend between the first layer and the second layer. Also, method400may manufacture, or cause to be manufactured, integrated circuitry having the first pre-routed metal line coupled to the second pre-routed metal line with the conductive via that extends between the first layer and the second layer.

In various implementations, method500may recognize gaps in the second pre-routed metal line of the second layer, and also, method500may automatically fill the gaps with conductive stubs to modify the second pre-routed metal lines in the second layer as a continuous metal line with an extended length. Also, the first layer may refer to a lower layer that is disposed underneath the second layer, the second layer refers to a higher layer that is different than the first layer, and the layers are arranged in a stack configuration with the higher layer disposed above the lower layer.

In various implementations, method500may identify the first pre-routed metal line in the lower layer, and the lower layer has the first pre-routed metal line with a length that is less than a length of the second pre-routed metal line of the higher layer. Also, automatically filling the gaps with conductive stubs may refer to extending the second pre-routed metal line in the higher layer as the continuous metal line with the extended length such that the length of the pre-routed metal lines of the higher layer is greater than the length of the pre-routed metal lines in the lower layer. Also, the gaps in the second pre-routed metal line of the higher layer are associated with spatial openings that are formed between portions of the second pre-routed metal line of the higher layer, and the stubs may refer to conductive branches that bridge the spatial openings that are formed between the portions of the second pre-routed metal line of the higher layer.

FIG.6illustrates a process diagram of a method600for providing metal routing architecture in accordance with implementations described herein.

It should be understood that even though method600indicates a particular order of operation execution, in some cases, various portions of operations may be executed in a different order, and on different systems. In other cases, additional operations and/or steps may be added to and/or omitted from method600. Also, method600may be implemented in hardware and/or software. If implemented in hardware, method600may be implemented with components and/or circuitry, as described in reference toFIGS.3A-3B. If implemented in software, method600may be implemented as a program or software instruction process configured for providing metal routing architecture, as described herein. Also, if implemented in software, instructions related to implementing the method600may be stored in memory and/or a database. For instance, a computer or some other type of computing device having a processor and memory may be configured to perform method600.

As described in reference toFIG.6, the method600may be used for fabricating and/or manufacturing, or causing to be fabricated and/or manufactured, an integrated circuit (IC) that implements the various metal routing schemes and techniques in physical design as described herein for providing metal routing architecture using various associated devices, components and/or circuitry described herein.

At block610, method600may identify metal lines in multiple layers of a multi-layered structure. At block620, method600may recognize a shorter metal line in a lower layer of the multiple layers. At block630, method600may recognize a longer metal line in a higher layer of the multiple layers. At block640, method600may recognize gaps in the longer metal lines of the higher layer. At block650, method600may automatically fill the gaps with conductive stubs to modify the longer metal lines in the higher layer as a continuous metal line with an extended length. Also, at block660, method600may automatically couple the shorter metal line to the longer pre-routed metal line with conductive vias that extend between the lower layer and the higher layer.

Moreover, method600may manufacture, or cause to be manufactured, integrated circuitry with the longer pre-routed metal line in the higher layer as the continuous metal line with the extended length. Also, method600may manufacture, or cause to be manufactured, integrated circuitry having the shorter pre-routed metal line coupled to the longer pre-routed metal line with the conductive via that extends between the lower layer and the higher layer.

The metal lines may refer to pre-routed metal lines, the shorter metal line may refer to a shorter pre-routed metal line, the longer metal line may refer to a longer pre-routed metal line, and the longer metal line may have a longer length that is greater than a shorter length of the shorter metal line. Also, automatically filling the gaps with conductive stubs may refer to extending the longer pre-routed metal line in the higher layer as the continuous metal line with the extended length such that the length of the longer pre-routed metal line of the higher layer is greater than the length of the shorter pre-routed metal line in the lower layer. Further, the gaps in the longer pre-routed metal line of the higher layer may refer to spatial openings that are formed between portions of the longer pre-routed metal line of the higher layer, and the stubs may refer to conductive branches that bridge the spatial openings that are formed between the portions of the longer pre-routed metal line of the higher layer.

FIG.7illustrates a system700for providing metal routing architecture in physical design in accordance with various implementations described herein.

In reference toFIG.7, the system700is associated with at least one computing device704that is implemented as a special purpose machine configured for implementing the metal routing schemes and techniques in physical design, as described herein. In various instances, the computing device704may have any standard element(s) and component(s), including at least one processor(s)710, memory712(e.g., non-transitory computer-readable storage medium), one or more database(s)740, power, peripherals, along with various other computing elements and/or components that may not be specifically shown inFIG.7. The computing device704may include instructions recorded and/or stored on the non-transitory computer-readable medium712that are executable by the at least one processor710. The computing device704may be associated with a display device750(e.g., a monitor or other display) that may be used to provide a user interface (UI)752, such as, e.g., a graphical user interface (GUI). In various instances, the UI752may be used to receive parameters and/or preferences from a user for managing, operating, and controlling the computing device704. Thus, in some instances, the computing device704may include the display device750for providing various output data and information to a user, and also, the display device750may include the UI752for receiving various input data and information from the user.

In reference toFIG.7, the computing device704may include a routing manager720that may be configured to cause the at least one processor710to implement various metal routing schemes and techniques as described herein in reference toFIGS.1A-6, including providing metal routing architecture related to implementing integrated circuitry in physical design. In some implementations, the routing manager720may be implemented in hardware and/or software. For instance, if implemented in software, the routing manager720may be stored in memory712or database740. Also, in some instances, if implemented in hardware, the routing manager720may refer to a separate processing component that is configured to interface with the processor710and/or various other components.

In some instances, the routing manager720may be configured to cause the at least one processor710to perform various operations, as provided herein in reference to metal routing schemes and techniques described inFIGS.1A-6. Also, in some instances, the memory712has stored thereon instructions that, when executed by the processor710, cause the processor710to perform one or more or all of the following operations.

For instance, the routing manager720may be configured to cause the at least one processor710to perform various process related operations, such as, e.g., extending higher metal lines. The process related operations may include identifying pre-routed metal lines in a higher layer of a multi-layered structure and recognizing gaps in the pre-routed metal lines of the higher layer. The process related operations may include automatically filling the gaps with conductive stubs to modify the pre-routed metal lines in the higher layer as a continuous metal line with an extended length. Moreover, the process related operations may include manufacturing, or causing to be manufactured, integrated circuitry with the pre-routed metal lines in the higher layer as the continuous metal line with the extended length.

Also, in some instances, the routing manager720may be configured to cause the at least one processor710to perform various other process related operations, such as, e.g., coupling lower metal lines to higher metal lines. The process related operations may include identifying pre-routed metal lines in layers of a multi-layered structure and recognizing a first pre-routed metal line in a first layer of the layers. The process related operations may include recognizing a second pre-routed metal line in a second layer of the layers and automatically coupling the first pre-routed metal line to the second pre-routed metal line with conductive vias that extend between the first layer and the second layer. Moreover, the process related operations may include manufacturing, or causing to be manufactured, integrated circuitry having the first pre-routed metal line coupled to the second pre-routed metal line with the conductive via that extends between the first layer and the second layer.

Also, in some instances, the routing manager720may be configured to cause the at least one processor710to perform various other process related operations, such as, e.g., extending higher metal lines along with coupling lower/higher metal lines. For instance, the process related operations may include identifying metal lines in multiple layers of a multi-layered structure and recognizing a shorter metal line in a lower layer of the multiple layers. The process related operations may include recognizing a longer metal line in a higher layer of the multiple layers and recognizing gaps in the longer metal lines of the higher layer. Also, the process related operations may include automatically filling the gaps with conductive stubs to modify the longer metal lines in the higher layer as a continuous metal line with an extended length and automatically coupling the shorter metal line to the longer pre-routed metal line with conductive vias that extend between the lower layer and the higher layer. Moreover, the process related operations may also include manufacturing, or causing to be manufactured, integrated circuitry with the longer pre-routed metal line in the higher layer as the continuous metal line with the extended length.

In various implementations, in reference to larger memory instances, such as for larger multi-bank memory instances (e.g., FB=4), stub programming may be used to provide longer routes over larger distances to farther banks. In other implementations, in reference to other memory instances, such as for smaller 2-bank memory instances (e.g., FB=2), via-programming may be applied and used to strap and improve resistance.

In various implementations, methods inFIGS.4-6may be configured to program metal stacks in higher layers so as to perform various different functions based on different memory configurations. For instance, stub programming may be applied and used to provide longer routes over larger distances to farther banks in larger multi-bank memory instances, and/or related configurations. In other instances, via programming may also be applied and used to strap pre-routed metal lines in various layers to thereby improve resistance in smaller multi-bank memory configurations.

In accordance with the various implementations described herein in reference toFIGS.1A-6, any one or more or all of process related operations performed by the routing manager720may be altered, modified, and/or changed so as to provide the various specific embodiments as shown inFIGS.1A-6. Also, the metal routings may be formed in various structural semiconductor architecture of a logic block or module having a set of shapes with width and space definitions, and the logic block or module may comprise a physical structure associated with an integrated circuit that is included in a place-and-route (PNR) environment for electronic design automation (EDA) and/or software/hardware related thereto.

Further, in reference toFIG.7, the computing device704may include a simulator722that is configured to cause the at least one processor710to simulate integrated circuitry and/or generate one or more simulations of integrated circuitry. In various implementations, the simulator722may be referred to as a simulating component, and also, the simulator722may be implemented in hardware and/or software. If implemented in software, the simulator722may be recorded or stored in memory712or database740. If implemented in hardware, the simulator720may refer to a separate processing component configured to interface with the processor710. In some instances, the simulator722may be a SPICE simulator that is configured to generate SPICE simulations of the integrated circuitry. Generally, SPICE is an acronym for Simulation Program with Integrated Circuit Emphasis, which is an open source analog electronic circuit simulator. SPICE may refer to a general-purpose software program used by the semiconductor industry to check the integrity of integrated circuit designs and to predict the behavior of integrated circuit designs. Thus, in some implementations, the routing manager720may be configured to interface with the simulator722so as to generate various timing data based on one or more or all simulations (including, e.g., SPICE simulations) of integrated circuitry that is utilized for analyzing performance characteristics of an integrated circuit including timing data of the integrated circuit. Also, the routing manager720may be configured to use one or more or all simulations (including, e.g., SPICE simulations) of the integrated circuit for evaluating operating behavior and conditions thereof.

In various implementations, the computing device704may include one or more databases740that are configured to store and/or record various data and information related to implementing metal routing schemes and techniques in physical design. Also, in some instances, the database(s)740may be configured to store and record data and information related to integrated circuitry, operating conditions, operating behaviors, timing data and any other related characteristics. Also, the database(s)740may be configured to store data and information associated with integrated circuitry and/or timing data in reference to simulation data (including, e.g., SPICE simulation data).

It should be intended that the claimed subject matter of the claims not be limited to the implementations and illustrations provided herein, but include modified forms of those implementations including portions of implementations and combinations of various elements of different implementations in accordance with the claims. It should be appreciated that in development of any such implementation, as in any engineering or design project, numerous implementation-specific decisions could be made to achieve developers' specific goals, such as compliance with system-related and business related constraints, which may vary in one implementation to another. It should be appreciated that such a development effort may be complex and time-consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having benefit of this disclosure.

Described herein are implementations of a method for identify pre-routed metal lines in a higher layer of a multi-layered structure. The method may recognize gaps in the pre-routed metal lines of the higher layer, and also, the method may automatically fill the gaps with conductive stubs to modify the pre-routed metal lines in the higher layer as a continuous metal line with an extended length. Also, method may manufacture, or cause to be manufactured, integrated circuitry with the pre-routed metal lines in the higher layer as the continuous metal line with the extended length.

Described herein are implementations of a method for identifying pre-routed metal lines in layers of a multi-layered structure. The method may recognize a first pre-routed metal line in a first layer of the layers, and the method may recognize a second pre-routed metal line in a second layer of the layers. Also, the method may automatically couple the first pre-routed metal line to the second pre-routed metal line with conductive vias that extend between the first layer and the second layer.

Described herein are implementations of a method for identifying metal lines in multiple layers of a multi-layered structure. The method may recognize a shorter metal line in a lower layer of the multiple layers, and the method may recognize a longer metal line in a higher layer of the multiple layers. The method may recognize gaps in the longer metal lines of the higher layer. The method may automatically fill the gaps with conductive stubs to modify the longer metal lines in the higher layer as a continuous metal line with an extended length. The method may automatically couple the shorter metal line to the longer metal line with conductive vias that extend between the lower layer and the higher layer.

Reference has been made in detail to various implementations, examples of which are illustrated in the accompanying drawings and figures. In the above detailed description, numerous specific details are set forth to provide a thorough understanding of the disclosure provided herein. However, the present disclosure provided herein may be practiced without these specific details. In other instances, well-known methods, procedures, components, circuits and/or networks have not been described in detail so as not to unnecessarily obscure details of the embodiments.

It should also be understood that, although various terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For instance, a first element could be termed a second element, and, similarly, a second element could be termed a first element. Also, the first element and the second element are both elements, respectively, but they are not to be considered the same element.

While the foregoing is directed to implementations of various techniques described herein, other and further implementations may be devised in accordance with the disclosure herein, which may be determined by the claims that follow.

Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims may not be necessarily limited to the specific features or acts described above. Rather, specific features and acts described above are disclosed as example forms of implementing the subject matter of the claims that follow.