Semiconductor memory device with test mode and testing method thereof

A synchronous SRAM includes a register sequentially providing data signals of the burst length in a test mode, and a transfer circuit applying data signals output from the register to a memory array for burst-writing, and providing to an external source via an IO buffer a data signal read out in a burst manner later than the burst writing by 1 clock cycle. It is not necessary to additionally apply a data signal for writing. The required number of address signals can be reduced. Thus, testing can be simplified.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device and a testing method thereof. Particularly, the present invention relates to a semiconductor memory device operating in synchronization with a clock signal, having a test mode to test whether each memory cell is proper or not, and a testing method thereof.

2. Description of the Background Art

Semiconductor memory devices such as SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) are conventionally subjected to testing prior to shipment to determine whether each memory cell is proper or not. This testing includes the steps of writing predetermined data into each of a plurality of memory cells included in the memory array, and reading out data from each memory cell. Determination is made that a memory cell is proper when the logic of data read out from that memory cell matches the logic of the data read into that memory cell. A memory cell is determined to be defective when such logics of data do not match. A defective memory cell is replaced with a spare memory cell.

Some testing methods conduct writing of external data into a memory cell and reading out data from another memory cell concurrently (for example, refer to Japanese Patent Laying-Open No. 59-175100).

In the conventional testing method, a data signal is written after an address signal and the data signal are applied to the semiconductor memory device from a tester, and a data signal is read out after an address signal is applied to the semiconductor memory device from the tester. There was a disadvantage that the testing operation is complex.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor memory device and a testing method thereof that can readily test whether each memory cell is proper or not.

According to an aspect of the present invention, a semiconductor memory device includes a plurality of memory cells, a register sequentially providing one by one N (N is an integer of at least 2) data signals that are written in advance in a test mode testing whether each memory cell is proper or not, a decoder sequentially selecting one by one N memory cells among the plurality of memory cells according to an address signal, a write circuit sequentially writing the N data signals output from the register into the N memory cells selected by the decoder, and a read circuit operating later than the write circuit by M (M is an integer of at least 1 and not more than N−1) clock cycles to sequentially read out a data signal from the N memory cells selected by the decoder. Since a data signal to be written is output from the register, a data signal for writing does not have to be additionally applied from an external source. Furthermore, since N memory cells are selected in response to one address signal and writing/reading of a data signal with respect to selected memory cells is conducted, the number of address signals to be input can be reduced. Therefore, testing is simplified.

According to another aspect of the present invention, a testing method includes the steps of rendering active the semiconductor memory device of the above aspect to set the semiconductor memory device in a test mode, applying an address signal to the decoder, and determining whether each memory cell is proper or not based on the data signal read out by the read circuit. The semiconductor memory device can be tested by applying an address signal and comparing the read out data signal with an expected value. Thus, the testing operation can be simplified.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring toFIG. 1, a synchronous SRAM according to an embodiment of the present invention includes control signal buffers1and2, an address buffer3, a clock buffer4, control circuits5and6, a memory array7, an IO buffer8, a selector9, a register unit10, and a transfer circuit11.

Control signal buffer1transmits external control signals /CS, /WE, /OE to control circuit5. Control signal buffer2transmits external control signals CNT0-CNTi (i is an integer of at least 0) to control circuit6. Address buffer3transmits external address signals A0-Aj (j is an integer of at least 0) to control circuit5. Clock buffer4supplies an external clock signal CLK to the entire SRAM.

Control circuit5generates various internal signals such as row address signals RA0-RAa, column address signals CA0-CAb (a and b are integers of at least 0), and transfer control signals PD1-PD4and PD1d-PD4daccording to signals /CS, /WE, /OE, . . . applied via control signal buffer1, address buffer3and clock buffer4to provide entire control of the SRAM by the generated internal signals.

Control circuit6generates test mode signals TMA1-TMAc and TMB1-TMBc (c is an integer of at least 1) according to signals CNT0-CNTi applied via control signal buffer2to provide these signals TMA1-TMAc and TMB1-TMBc to selector9and register unit10.

Memory array7is divided into four memory blocks MB1-MB4. Each of memory blocks MB1-MB4includes a plurality of memory cells arranged in a plurality of rows and columns. Each memory cells stores one data signal.

IO buffer8outputs from the semiconductor memory device a read out data signal Q applied from memory array7via transfer circuit11, and provides to selector9an externally applied write data signal D. In a test mode, selector9is under control of control circuit6through signals TMA1-TMAc to apply write data signal D from IO buffer8to register unit10. In a normal operation mode, selector9provides write data signal D from IO buffer8to transfer circuit11.

In a test mode, register unit10is under control of control circuit6through signals TMB1-TMBc to output write data signal D directed to testing to transfer circuit11.

In a write operation, transfer circuit11responds to signals PD1-PD4from control circuit5to select any of the four memory blocks MB1-MB4of memory array7, and provides write data signal D from selector9or register unit10to the selected memory block. In a read out operation, transfer circuit11responds to signals PD1d-PD4dfrom control circuit5to select any of memory blocks MB1-MB4of memory array7, and couples the selected memory block with IO buffer8. In a test mode, transfer circuit11conducts writing and reading of data signals concurrently. The operation of transfer circuit11in a test mode will be described in detail afterwards.

FIG. 2is a circuit block diagram of a structure of memory block MB1. Referring toFIG. 2, memory block MB1includes (n+1)×(m+1) memory cells MC arranged in (n+1) rows and (m+1) columns (each of n and m is an integer of at least 1), word lines WL0-WLn provided corresponding to the (n+1) rows, respectively, m+1 pairs of bit lines BL and /BL provided corresponding to (m+1) columns, respectively, (m+1) column select lines CL0-CLm provided corresponding to (m+1) columns, respectively, and a pair of data input/output lines IO and /IO.

Referring toFIG. 3, memory cell MC includes P-channel MOS transistors31and32, and N-channel MOS transistors33-36. P-channel MOS transistors31and32are connected between the line of power supply potential VCC and storage nodes N1and N2, and have their gates connected to storage nodes N2and N1, respectively. N-channel MOS transistors33and34are connected between respective storage nodes N1and N2and the line of ground potential GND, and have their gates connected to storage nodes N2and N1, respectively.

MOS transistors32and34form a first inverter that applies to storage node N2an inverted signal of the signal at storage node N1. MOS transistors31and33form a second inverter that applies to storage node N1an inverted signal of the signal at storage node N2. The first and second inverters form a latch circuit storing the signals of storage nodes N1and N2. N-channel MOS transistor35is connected between bit line BL and storage node N1. N-channel MOS transistor36is connected between bit line /BL and storage node N2. N-channel MOS transistors35and36have their gates connected to word line WL.

In a write operation, word line WL is pulled up to an H level (logical high), whereby N-channel MOS transistors35and36conduct. Then, one of bit lines BL and /BL is brought to an H level whereas the other bit line is brought to an L level according to write data signal D, whereby a signal is written into each of storage nodes N1and N2. For example, when data signal D is at an H level (1), a signal of an H level and a signal of an L level are written into storage nodes N1and N2, respectively. When data signal D is at an L level (0), signals of an L level and an H level are written into storage nodes N1and N2, respectively. In response to word line WL being pulled down to an L level, N-channel MOS transistors35and36are rendered nonconductive. The signals of storage nodes N1and N2are latched by MOS transistors31-34.

In a read out operation, bit lines BL and /BL are precharged to an H level, and then word line WL is pulled up to an H level. In response, N-channel MOS transistors35and36are rendered conductive. One of bit lines BL and /BL is pulled down to an L level according to the storage data of memory cell MC. For example, when storage nodes N1and N2are at an H level and an L level, respectively, current flows from bit line /BL to the line of ground potential GND via N-channel MOS transistors36and34, whereby bit line /BL is brought to an L level. The potential of bit line BL is not reduced since N-channel MOS transistor33is nonconductive. By comparing the potentials of bit lines BL and /BL, a data signal can be read out from memory cell MC. Word line WL is pulled down to an L level, and the read operation ends.

One end of each bit line pair BL and /BL is connected to bit line peripheral circuit12whereas the other end of each bit line pair is connected to column select gate13. As shown inFIG. 3, bit line peripheral circuit12includes N-channel MOS transistors37and38and a P-channel MOS transistor39corresponding to each bit line pair BL and /BL. N-channel MOS transistors37and38are diode-connected between the line of power supply potential VCC and one end of bit lines BL and /BL to charge respective bit lines to an H level. P-channel MOS transistor39is connected between bit lines BL and /BL, and receives a bit line equalize signal /BLEQ at its gate. In response to signal /BLEQ pulled down to an L level of activation, P-channel MOS transistor39conducts, whereby the potentials of bit lines BL and /BL are equalized.

As shown inFIG. 2, column select gate13includes transfer gates14and15and an inverter16provided corresponding to bit lines BL and /BL. Transfer gate14is connected between the other end of bit line BL and a data input/output line IO. Transfer gate15is connected between the other end of bit line /BL and a data input/output line /IO. Column select line CL is directly connected to the N-channel MOS transistor side gate of corresponding transfer gates14and15, and connected to the P-channel MOS transistor side gate of corresponding transfer gates14and15via corresponding inverter16. When any column select line CL from (m+1) column select lines CL0-CLn is pulled up to an H level of selection, transfer gates14and15corresponding to that pulled up column select line CL conduct, whereby bit line pair BL and /BL corresponding to that column select line CL is coupled with data input/output line pair IO, /IO.

Row decoder20selects any of (n+1) word lines WL0-WLn according to row address signals RA0-RAa from control circuit5to drive the selected word line WL to an H level of selection. Specifically, row decoder20includes a NAND gate21and an inverter22provided corresponding to each word line WL. Each word line WL is assigned unique row address signals RA0-RAa in advance. NAND gate21and inverter22receive preassigned row address signals RA0-RAa, and pulls up a corresponding word line WL to an H level of selection in response to block select signal BS1brought to an H level. Block select signal BS1attains an H level of selection when memory block MB1is specified by address signals A0-Aj.

Column decoder23selects any of (m+1) column select lines CL0-CLm according to address signals CA0-CAa from control circuit5to pull up the selected column select line CL to an H level of selection. Specifically, column decoder23includes a NAND gate24and an inverter25provided corresponding to each column select line CL. Each column select line CL is assigned unique column address signals CA0-CAb in advance. NAND gate24and inverter25pull up corresponding column select line CL to an H level of selection in response to input of preassigned column address signals CA0-CAb.

In a write operation, write driver26drives one of data input/output lines IO, /IO to an H level and the other of data input/output lines IO, /IO to an L level according to write data signal D. In a read operation, sense amplifier27compares the potentials of data input/output lines IO, /IO to output a data signal Q of a logic level corresponding to the comparison result.

The operation of memory block MB1shown inFIGS. 2 and 3will be described hereinafter. It is assumed that memory block MB1is selected and block select signal BS1is at an H level of selection. In a write operation, word line WL of the row specified by row address signals RA0-RAa is pulled up to an H level of selection by row decoder20, whereby respective memory cells MC of that row are rendered active. Then, column select line CL of a column specified by column address signals CA0-CAb is pulled up to an H level of selection by column decoder23, whereby transfer gates14and15of that column are rendered conductive. One activated memory cell MC is connected to write driver26via bit line pair BL and /BL and data input/output line pair IO, /IO.

Write driver26drives one of data input/output lines IO, /IO to an H level and the other data input/output line to an L level according to write data signal D to write data into memory cell MC. When word line WL and column select line CL are pulled down to an L level, data is stored into memory cell MC.

In a reading operation, column select line CL of the column specified by column address signals CA0-CAb is pulled up to an H level of selection. Transfer gates14and15of that column are rendered conductive, whereby bit lines BL and /BL are connected to sense amplifier27via data input/output line pair IO, /IO. Then, bit line equalize signal /BLEQ is brought to an L level of activation, whereby each P-channel MOS transistor39conducts. In response, the potentials of bit lines BL and /BL are equalized.

After bit line equalize signal /BLEQ attains an H level of inactivation and each P-channel MOS transistor39is rendered nonconductive, word line WL of a row according to row address signals RA0-RAa is pulled up to an H level of selection. In response, each memory cell MC of that row is rendered active. Accordingly, current flows from one of bit lines BL and /BL to memory cell MC according to the stored data in memory cell MC. In response, the potential of one of data input/output lines IO, /IO is reduced. Sense amplifier27compares the potentials of data input/output lines IO, /IO to output a data signal Q of a logic level corresponding to the comparison result.

In a burst operation where data signals are written/read out continuously, a plurality of (for example, 4) column select lines are sequentially brought to an H level for every one clock cycle. The second and subsequent column address signals CA0-CAb are generated in control circuit5. Specifically, control circuit5includes a burst counter40, as shown in FIG.4. Burst counter40latches internal column address signals PCA0-PCAb generated based on external address signals A0-Aj, and provides the same as the first of column address signals CA0-CAb. Burst counter40counts the number of pulses of clock signal CLK, and increments (+1) the values of output column address signals CA0-CAb. Accordingly, four continuous column address signals CA0-CAb are generated, and four column select lines are sequentially selected. Data signals are sequentially written/read out with respect to four memory cells MC.

FIG. 5is a circuit block diagram of a structure of transfer circuit11. Referring toFIG. 5, transfer circuit11includes write gates41-44, read gates45-48, a buffer49, a write data line WDL and a read data line RDL. Buffer49applies write data signal D from selector9or register unit10to write data line WDL. Write gates41-44are provided between respective write data line WDL and write driver26of memory blocks MB1-MB4, and conduct in response to respective signals PD1-PD4attaining an H level of activation. When write gates41-44are rendered conductive, data signal D is applied to write driver26of memory blocks MB1-MB4.

Read gates45-48are provided between sense amplifier27of respective memory blocks MB1-MB4and a read data line RDL, and conduct in response to respective signals PD1d-PD4dattaining an H level of activation. When read gates45-48are rendered conductive, read out data signal Q is applied from sense amplifier27of respective memory blocks MB1-MB4to read data line RDL. Read data line RDL is connected to IO buffer8.

FIG. 6is a block diagram representing the portion related to generation of transfer control signals PD1-PD4and PD1d-PD4din control circuit5. Referring toFIG. 6, control circuit5includes a block select decoder51, a delay circuit52, and a burst counter53. Block select decoder51is rendered active when test mode signal TM is at an L level of inactivation, i.e., when in a normal operation mode, to select any of transfer control signals PD1-PD4according to address signals A0and A1to pull up the selected signal to an H level of selection at a predetermined timing. Burst counter53is rendered active when test mode signal TM is at an H level of activation, i.e., when in a test mode, to bring signals PD1-PD4to an H level at every 1/2 cycle in synchronization with clock signal CLK, as shown in FIG.7. Delay circuit52delays signals PD1-PD4by just one cycle to generate signals PD1d-PD4d.

For example, at cycle1, signal PD1attains an H level to render write gate41conductive, whereby data signal D is written into memory cell MC of memory block MB1. At cycle2, signals PD1dand PD2attain an H level to render read gate45conductive, whereby read out data signal Q of memory block MB1is applied to read data line RDL. Also, write gate42is rendered conductive, whereby data signal D is written into memory cell MC of memory block MB2.

At cycle3, signals PD2dand PD3attain an H level to render read gate46conductive, whereby read out data signal Q of memory block MB2is applied to read data line RDL. Also, write gate43is rendered conductive, whereby data signal D is written into memory cell MC of memory block MB3.

At cycle4, signals PD3dand PD4attain an H level to render read gate47conductive, whereby read out data signal Q of memory block MB3is applied to read data line RDL. Also, write gate44is rendered conductive, whereby data signal D is written into memory cell MC of memory block MB4.

At cycle5, signals PD4dand PD1attain an H level to render read gate48conductive. Read out data signal Q of memory block MB4is applied to read data line RDL. Also, write gate41is rendered conductive, whereby data signal D is written into memory cell MC of memory block MB1.

The operation of this SRAM in a test mode will be described here. The SRAM has a tester (not shown) connected. The tester writes test data signals D0-D3of the burst length (4 here) to a desired register (for example, RG1) among a plurality of registers RG1-RGc in register unit10, as shown inFIGS. 8 and 9. Specifically, the tester renders active a test mode signal TMA1corresponding to register RG1among test mode signals TMA1-TMAc. Signal TMA1rendered active becomes the delay signal of clock signal CLK, and attains an H level at the rising edge of clock signal CLK. The tester pulls down signal /WE to an L level in synchronization with a rising edge (time t1) of clock signal CLK, and inputs the first data signal D0. Then, three data signals D1-D3are sequentially input in synchronization with a rising edge of clock signal CLK. Accordingly, test data signals D0-D3are written into register RG1via IO buffer8and selector9.

Referring toFIGS. 10-12, the tester has data signals D0-D3in register RG1burst-written into a plurality of memory cells MC in memory array7, and has data signals Q0-Q3read out in a bursting manner from the plurality of memory cells MC where data signals D0-D3are written. Specifically, a test mode signal TMB1among test mode signals TMB1-TMBc corresponding to a desired register RG1is rendered active. Signal TMB1rendered active becomes a delay signal of clock signal CLK, and attains an H level at the rising edge of clock signal CLK. Then, the tester inputs a start address signal A (0, 0) (address signal specifying memory cell MC located at the 0th row and 0th column inFIG. 2) in synchronization with a rising edge (time t0) of clock signal CLK, and brings signal /WE to an L level. As shown inFIGS. 6 and 7, write gate41corresponding to memory block MB1is rendered conductive at cycle1. Data signal DO output from register RGJ is written into memory cell MC specified by address signal A (0,0) in memory block MBJ1. The write latency is 1 cycle here.

At the next rising edge (time t1) of clock signal CLK, burst counter40ofFIG. 4generates an address signal A (0,1) (address signal specifying a memory cell MC located at the 0th row and first column inFIG. 2) that is an incremented version of address signal A (0,0). As shown inFIGS. 6 and 7, read gate45corresponding to memory block MB1as well as write gate42corresponding to memory block MB2are rendered conductive at cycle2. Data signal Q0is read out from memory cell MC that is specified by address signal A (0,0) in memory block MB1. Also, data signal D1is written into a memory cell MC specified by address signal A (0, 1) in memory block MB2.

Similarly at cycle3, data signal Q1is read out from memory cell MC specified by address signal A (0, 1) in memory block MB2, and data signal D2is written into memory cell MC specified by address signal A (0, 2) in memory block MB3.

At cycle4, data signal Q2is read out from memory cell MC specified by address signal A (0, 2) of memory block MB3, and data signal D3is written into memory cell MC specified by address signal A (0, 2) in memory block4.

At cycle4, the next start address signal A (1, 0) is input. At cycle5, data signal Q3is read out from memory cell MC specified by address signal A (0, 3) of memory block MB4. Also, data signal D0is written into memory cell MC specified by address signal A (1, 0) in memory block MB1. Thus, in a similar manner, data signal writing/reading is conducted with respect to all the memory cells MC.

Determination is made that, when the logic level of a read out data signal Q of memory cell MC matches an expected value (the logic level of data signal D written into that memory cell MC), that memory cell MC is proper. When the logic level of read out data signal Q of memory cell MC does not match the expected value, determination is made that the relevant memory cell is defective. The address signal of that defective memory cell MC is stored in the tester.

The defective memory cell MC is replaced with a spare memory cell (not shown). In the case where the defective memory cell MC cannot be replaced with a spare memory cell, that SRAM is discarded.

Since data signals D0-D3for writing are output from register RG in the present embodiment, it is not necessary to additionally apply a data signal for writing from the tester. Furthermore, since four memory cells MC are selected in response to one of address signals A0-Aj and data signal writing/reading is conducted on the selected memory cell MC, the number of address signals A0-Aj to the input can be reduced. Therefore, the testing can be simplified.

Since data signal writing and reading are carried out concurrently in a test mode, the time required for testing can be shortened as compared to the conventional case where a data signal is read out from respective memory cells MC after data signals are written into all respective memory cells MC.

Although only one register RG1is employed in the present embodiment, a plurality of registers RG1-RGc may be employed instead in which data signals D0-D3of patterns differing from each other are stored. In this case, registers RG1-RGc are appropriately switched. This is advantageous in that a more complicated test pattern can be written into memory array7.