Package substrate first-level-interconnect architecture

Embodiments of the present disclosure may relate to a package substrate that may include a layer having a layer surface that is planarized and a via within the layer, where the via includes a via surface that is exposed on the layer surface, and where the via surface is planarized. The package substrate may further include a bond pad on the layer surface, where a first thickness of the bond pad includes a seed layer on the via surface, and where a second thickness of the bond pad includes a plating stack on the seed layer. Other embodiments may be described or claimed.

FIELD

Embodiments of the present disclosure relate generally to semiconductor packaging. More particularly, embodiments of the present disclosure relate to bond pads for package substrates.

BACKGROUND

Electronic devices typically include integrated circuit (IC) die. The IC die may be inserted into an IC package to form a first level assembly before it is incorporated into a higher level assembly. Over time, electronic devices typically include more features, and thus more IC die, in the same amount of space or in less space. Use of an increased number of IC die in an IC package may therefore result in space-related issues in electronic devices.

DETAILED DESCRIPTION

Embodiments of the present disclosure may relate to a package substrate that may include a layer having a layer surface that is planarized and a via within the layer, where the via includes a via surface that is exposed on the layer surface, and where the via surface is planarized. The package substrate may further include a bond pad on the layer surface, where a first thickness of the bond pad includes a seed layer on the via surface, and where a second thickness of the bond pad includes a plating stack on the seed layer.

In various embodiments, the phrase “a first feature formed, deposited, or otherwise disposed on a second feature,” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature.

An IC die may be coupled with a package substrate to form an IC package. The IC package may be referred to as a first level assembly. The first level assembly may include an electrical connection between the IC die and the package substrate, for example, between a bond pad of the IC die, which may be referred to as an IC pad of the IC die, and a bond pad of the package substrate. The electrical connection between the IC die and the package substrate may be referred to as a first level interconnect (FLI). The IC package may be coupled with, for example, a circuit board, to form a second level assembly for an electronic device. An electrical connection between the package substrate and the circuit board may be referred to as a second level interconnect.

As electronic devices include more features, and thus more IC die, it may be challenging to include the IC die in the same amount of space. The challenge may be even greater as electronic devices become smaller and more compact. The distance between bond pads of a package substrate may be referred to as the pitch. This distance also may be referred to as the bump pitch, given that a solder bump may be used to couple the bond pad with an IC pad to form an FLI. The ability to provide a finer pitch, and thus place IC die closer to one another, may enable more IC die to be coupled with a package substrate.

Thickness variation of an FLI may limit the ability to provide finer bump pitches. For example, a large thickness variation of an FLI may lead to package substrates designed at finer pitch and yield losses at the die-to-package-assembly process. Consequently, knowing that a given process has FLI thickness variation may lead to providing coarser bump pitches to avoid yield loss.

Planarization may refer to the removal of material to even out irregular topography of a surface and thus make the surface relatively flat or planar. Planarization of inner layers of a substrate package may be one way to compensate for thickness variation of an FLI on an outer surface. However, planarization of inner layers may lead to thickness variation of the inner layers, which may cause performance issues in the package substrate, such as, for example, impedance mismatch issues or reliability issues. Further, FLI thickness variation may be exacerbated by the presence of multiple inner layers, each of which may have thickness variation.

As part of the manufacturing process, copper plating and dry film photoresist, which also may be referred to as dry film resist (DFR), may be applied to an FLI. Planarization after copper plating an FLI and polishing both the DFR and the copper plating may be another way to address thickness variation of an FLI. However, this may subject the package substrate to additional processes that may introduce additional FLI thickness variation, which may negate the intended benefits of this approach.

Embodiments herein relate to aspects that enable the ability to provide a package substrate that has an FLI with relatively small thickness variation. The ability to reduce FLI thickness variation may enable the ability to provide a finer pitch. The ability to provide a finer pitch may reduce yield loss and increase the number of IC die that may be coupled with a package substrate.

FIG. 1depicts an example package substrate, in accordance with various embodiments. Package substrate100may include a layer102having a layer surface104that is planarized. Layer102may be a dielectric layer that includes any type of dielectric material, including, but not limited to, for example, solder resist, buildup films, organic materials, inorganic materials such as silicon dioxide (SiO2), organic materials filled with inorganic fillers, etc. Layer surface104may be a top surface, a side surface, an angled surface, a bottom surface, or any other surface of layer102.

Package substrate100may further include a via110within the layer102, where the via110includes a via surface112that is exposed on the layer surface104, and where the via surface112is planarized. The via110may be an electrically conductive microelectronic structure that electrically couples structures above a via with structures below the via. The via surface112may be a top surface, a side surface, an angled surface, a bottom surface, or any other surface of via110.

The layer surface104and via surface112may be planarized using any chemical planarization process, any mechanical planarization process, any chemical-mechanical planarization (CMP) process, or any other process that results in layer surface104and via surface112being flat or substantially flat. Chemical planarization may include, for example, applying a chemical or immersing an object in a chemical, to, for example, remove material from a surface or even out irregular topography, to make the surface flat or substantially flat. Mechanical planarization may include, for example, rotating a pad or moving a pad on a surface, to, for example, remove material from a surface or even out irregular topography, to make the surface flat or substantially flat. CMP may be a hybrid of chemical planarization and mechanical planarization that may include, for example, applying a chemical and a rotating or moving pad on a surface, to, for example, remove material from a surface or even out irregular topography, to make the surface flat or substantially flat.

Package substrate110may further include a bond pad120on the layer surface104, where a first thickness of the bond pad120includes a seed layer124on the via surface112, and wherein a second thickness of the bond pad includes a plating stack128on the seed layer124. Bond pad120may provide electric continuity when coupled with an IC pad of an IC die. As used herein, a reference to being “on” a surface or a structure includes being on any side of the surface or structure, including being on a top, a side, a bottom, or any other part of the surface or structure.

Seed layer124may be referred to as a surface finish. In some embodiments, seed layer124may be a titanium-copper (Ti—Cu) layer, where the titanium is on the layer surface112, and the copper is on the titanium. In some embodiments, the thickness of the titanium may be less than 0.5 micrometers (um), measured from where the titanium contacts the layer surface112to the end of titanium opposite where it contacts the layer surface112, and the thickness of the copper may be less than 2.5 um, measured from where the copper contacts the titanium to the end of the copper opposite where it contacts the titanium. In some embodiments, the seed layer124may be a titanium layer. In some embodiments, the thickness of the titanium may be less than 3 um. In some embodiments, the seed layer124may be a tungsten-copper (W—Cu) layer, where the tungsten is on the layer surface, and the copper is on the tungsten. In some embodiments, the thickness of the tungsten may be less than 0.5 um, measured from where the tungsten contacts the layer surface112to the end of tungsten opposite where it contacts the layer surface112, and the thickness of the copper may be less than 2.5 um, measured from where the copper contacts the tungsten to the end of the copper opposite where it contacts the tungsten. In some embodiments, the seed layer124may be a tantalum-copper (Ta—Cu) layer, where the tantalum is on the layer surface, and where the copper is on the tantalum. In some embodiments, the thickness of the tantalum may be less than 0.5 um, measured from where the tantalum contacts the layer surface112to the end of tantalum opposite where it contacts the layer surface112, and the thickness of the copper may be less than 2.5 um, measured from where the copper contacts the tantalum to the end of the copper opposite where it contacts the tantalum.

In some embodiments, plating stack128may be a nickel-palladium-gold (Ni—Pd—Au or NPG) stack, where the nickel may be on the seed layer124, the palladium may be on the nickel, and the gold may be on the palladium. In some embodiments, the thickness of the nickel may be less than 10 um, measured from where the nickel contacts the seed layer124to the end of the nickel opposite where it contacts the seed layer124, and it may be between 2 um and 0.5 um, again measured from where the nickel contacts the seed layer124to the end of the nickel opposite where it contacts the seed layer124; the thickness of the palladium may be less than 0.5 um, measured from where the palladium contacts the nickel to the end of the palladium opposite where it contacts the nickel; and the thickness of the gold may be less than 5 um, measured from where the gold contacts the palladium to the end of the gold opposite where it contacts the palladium. In some embodiments, the plating stack128may be a cobalt/tungsten alloy-palladium-gold stack, where the cobalt/tungsten alloy may be on the seed layer, the palladium may be on the cobalt/tungsten alloy, and gold may be on the palladium. In some embodiments, the plating stack128may be a nickel-copper stack, where the nickel may be on the seed layer and the copper may be on the nickel.

In some embodiments, the plating128stack may be an electrolytic stack or an electroless stack. For an electrolytic stack, which also may be referred to as an elytic stack, an electric current may be used for deposition of the plating material. For an electroless stack, something other than an electric current, for example, a chemical agent, may be used for deposition of the plating material. In some embodiments, package substrate100may include solder on the bond pad120. Solder may help to form the FLI between the package substrate100and an IC die during assembly of an IC package. Alternatively or additionally, the solder may be on an IC pad of the IC die. The solder may be any type of solder that helps to form the FLI and may be any lead-free or leaded solder. The solder may be, for example, tin-copper, tin-silver, tin-silver-copper that includes 96.5% tin, 3% silver, and 0.5% copper (SAC305), or tin-silver-copper that includes 95.5% tin, 4% silver, and 0.5% copper (SAC405). In some embodiments, a material other than solder, for example, copper or gold, may be used to help form the FLI.

AlthoughFIG. 1depicts the package substrate100as including one layer, package substrate100may include any number of layers. Further, althoughFIG. 1depicts package substrate100as including a certain number of bond pads, package substrate100may include any number of bond pads. Similarly, althoughFIG. 1depicts package substrate100as including a certain number of vias, package substrate100may include any number of vias.

FIG. 2depicts an example IC package, in accordance with various embodiments. IC package200may include a package substrate210, such as, for example, package substrate100. The package substrate210may include a dielectric layer212having a dielectric surface214that is planarized. The package substrate210may further include a via216buried in the dielectric layer212, where the via216includes a via surface218that is exposed on the dielectric surface214, and where the via surface218is planarized.

The package substrate210may further include a bond pad220on the dielectric surface214, where a first thickness of the bond pad220includes a surface finish224on the via surface218. In some embodiments, the surface finish224may be a seed layer that includes titanium and copper. Further, a second thickness of the bond pad220may include a plating stack228on the surface finish224. In some embodiments, the thickness of the titanium may be less than 0.5 um, measured from where the titanium contacts the layer surface112to the end of titanium opposite where it contacts the layer surface112, and the thickness of the copper may be less than 2.5 um, measured from where the copper contacts the titanium to the end of the copper opposite where it contacts the titanium. In some embodiments, the plating stack228may be an NPG stack, where the nickel is on the surface finish, the palladium is on the nickel, and the gold is on the palladium. In some embodiments, the thickness of the nickel may be less than 10 um, measured from where the nickel contacts the seed layer124to the end of the nickel opposite where it contacts the seed layer124; the thickness of the palladium may be less than 0.5 um, measured from where the palladium contacts the nickel to the end of the palladium opposite where it contacts the nickel; and the thickness of the gold may be less than 5 um, measured from where the gold contacts the palladium to the end of the gold opposite where it contacts the palladium. In some embodiments, the plating228stack may be an electrolytic stack.

IC package200may further include a die230that includes an IC pad232. IC die230may be any type of IC die, for example, a single element semiconductor, such as, for example, a silicon IC die; or, for example, a compound semiconductor, such as, for example, a gallium arsenide (GaAs) IC die. IC package200may further include solder240coupled with the bond pad220and the IC pad232, to form an FLI between the package substrate210and the IC die230. The solder240may be on the bond pad220. Alternatively or additionally, the solder240may be on the IC pad232. The solder may be any type of solder that helps to form the FLI and may be any lead-free or leaded solder. The solder may be, for example, tin-copper, tin-silver, tin-silver-copper that includes 96.5% tin, 3% silver, and 0.5% copper (SAC305), or tin-silver-copper that includes 95.5% tin, 4% silver, and 0.5% copper (SAC405). In some embodiments, a material other than solder, for example, copper or gold, may be included to help form the FLI.

AlthoughFIG. 2depicts the package substrate210as including one layer, package substrate210may include any number of layers. Further, althoughFIG. 2depicts package substrate210as including a certain number of bond pads, package substrate200may include any number of bond pads. Similarly, althoughFIG. 2depicts package substrate200as including a certain number of vias, package substrate200may include any number of vias.

FIGS. 3A-3Fdepict portions of integrated circuit layers representing various operations in an example process of producing a package substrate, in accordance with various embodiments. Referring toFIG. 3A, starting structure300may include a layer302having a layer surface304that is planarized. Layer302may be, for example, layer102described above, and layer surface304may be, for example, layer surface104described above.

Starting structure300may further include a via310within the layer302, where the via310includes a via surface312that is exposed on the layer surface304, and where the via surface312is planarized. Via310may be, for example, via110described above, and via surface312may be, for example, via surface112described above.

Referring toFIG. 3B, a seed layer320may be deposited on the layer surface304, where the seed layer320may cover the via310. Seed layer320may be, for example, seed layer124described above. Referring toFIG. 3C, lamination330, which may be any lamination, including, for example, DFR lamination, may be placed on seed layer320, where the lamination320includes an opening332over the via310. Placement of the lamination330may be based on, for example, defining a bond pad size or shape, using, for example, a patterning process that may include use of, for example, resist material.

Referring toFIG. 3D, an NPG stack340may be plated on the seed layer320in the opening332. NPG stack340may be, for example, a plating stack128described above that may be an NPG stack described above. Referring toFIG. 3E, lamination330may be removed. Referring toFIG. 3F, the seed layer320exposed by removal of the lamination330may be removed. Etching, for example, may be used to remove the seed layer320exposed by removal of the lamination330. Further, material, for example, resist material, remaining from, for example, a patterning process used define a size or shape of a bond pad, may be removed by, for example, etching. The NPG stack340on the remaining seed layer320may form a bond pad350, which may be, for example, bond pad120described above.

FIG. 4depicts an example process of producing a package substrate, in accordance with various embodiments. In some embodiments, process400may include, at402, creating a via on a pad. The pad may be, for example, a copper pad. Further, the pad may be an isolated pad, or the pad may have one or more traces, for example, one or more copper traces, emerging from the pad as part of an interconnect metal layer for the via. A via may be created using any process, such as, for example, a lithographic via (LiV) process, a self-aligned via process, a zero-misalignment process, a laser drilled via process, etc.

In some embodiments, process400may further include, at404, burying the via in a dielectric applied over the via and the pad. In some embodiments, process400may further include, at406, planarizing the dielectric to reveal a surface of the via through a flat surface of the dielectric. In some embodiments, planarizing the dielectric to reveal the surface of the via through the flat surface of the dielectric may include using a chemical process, a mechanical process, or a chemical-mechanical process to planarize the dielectric to reveal the surface of the via through the flat surface of the dielectric.

In some embodiments, process400may include, at408, depositing a seed layer over the flat surface, where the seed layer may cover the via. In some embodiments, process400may further include, at410, plating an NPG stack on the seed layer, where the seed layer and NPG stack form a bond pad on the via.

In some embodiments, process400may include defining a size or shape of the bond pad. In some embodiments, process400may further include placing a lamination on the seed layer, wherein the lamination includes an opening over the via, and wherein the NPG stack is plated in the opening. In some embodiments, process400may further include removing the lamination. In some embodiments, process400may include removing the seed layer exposed by removal of the lamination. In some embodiments, process400may include placing solder on the bond pad.

The formation of a bond pad through the direct deposition of a surface finish on a planarized surface and the application of a plating stack on that surface finish as described in embodiments herein, along with, for example, an LiV process, may provide an FLI with little thickness variation. Consequently, embodiments herein may enable a pitch, or scaling of a bump pitch, below 45 um. Thus, with regard to bump thickness variation (BTV) improvement, embodiments herein may minimize FLI thickness variation through planarization along with, for example, an LiV process, to provide a flat or substantially flat dielectric surface on which to apply a surface finish. In addition, a thin elytic plating stack may be achieved utilizing conformal plating, as the plating stack conforms to the contours of the surface finish, which may contribute to minimizing FLI thickness variation. Further, embodiments herein may be used with, for example, an embedded interconnect bridge (EmIB) process, for providing an interconnection between two IC die coupled with a package substrate.

FIG. 5depicts an example electronic device, in accordance with various embodiments. Electronic device500may be suitable for use with various components ofFIG. 1orFIG. 2. As shown, electronic device500may include one or more processors or processor cores502and system memory504. For the purpose of this application, including the claims, the terms “processor” and “processor cores” may be considered synonymous, unless the context clearly requires otherwise. The processor502may include any type of processors, such as a central processing unit (CPU), a microprocessor, and the like. The processor502may be implemented as an integrated circuit having multi-cores, e.g., a multi-core microprocessor. The processor502may be coupled with a package substrate, for example, package substrate100or package substrate210, that includes bond pads, for example, bond pads120or bond pads220, to form an IC package, for example, IC package200.

The electronic device500may include mass storage devices506(such as diskette, hard drive, volatile memory (e.g., dynamic random-access memory (DRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), and so forth). In general, system memory504and/or mass storage devices506may be temporal and/or persistent storage of any type, including, but not limited to, volatile and non-volatile memory, optical, magnetic, and/or solid state mass storage, and so forth. Volatile memory may include, but is not limited to, static and/or dynamic random access memory. Non-volatile memory may include, but is not limited to, electrically erasable programmable read-only memory, phase change memory, resistive memory, and so forth.

The electronic device500may further include I/O devices508(such as a display (e.g., a touchscreen display)), keyboard, cursor control, remote control, gaming controller, image capture device, a camera, one or more sensors, and so forth) and communication interfaces510(such as network interface cards, modems, infrared receivers, radio receivers (e.g., Bluetooth), and so forth).

The communication interfaces510may include communication chips (not shown) that may be configured to operate the device500in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or Long-Term Evolution (LTE) network. The communication chips may also be configured to operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chips may be configured to operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond.

The above-described electronic device500elements may be coupled to each other via system bus512. In the case of multiple buses, they may be bridged by one or more bus bridges (not shown). Each of these elements may perform its conventional functions known in the art. In particular, system memory504and mass storage devices506may be employed to store a working copy and a permanent copy of the programming instructions for the operation of various components of electronic device500, including but not limited to an operating system of electronic device500and/or one or more applications. The various elements may be implemented by assembler instructions supported by processor(s)502or high-level languages that may be compiled into such instructions.

The permanent copy of the programming instructions may be placed into mass storage devices506in the factory, or in the field through, for example, a distribution medium (not shown), such as a compact disc (CD), or through communication interface510(from a distribution server (not shown)). That is, one or more distribution media having an implementation of the agent program may be employed to distribute the agent and to program various electronic devices.

The number, capability, and/or capacity of the elements508,510,512may vary, depending on whether electronic device500is used as a stationary electronic device, such as a set-top box or desktop computer, or a mobile electronic device, such as a tablet computing device, laptop computer, game console, or smartphone. Their constitutions are otherwise known, and accordingly will not be further described.

In embodiments, memory504may include computational logic522configured to implement various firmware and/or software services associated with operations of the electronic device500. For some embodiments, at least one of processors502may be packaged together with computational logic522configured to practice aspects of embodiments described herein to form a System in Package (SiP) or a System on Chip (SoC).

In various implementations, the electronic device500may be one or more components of a data center, a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a digital camera, or an IoT user equipment. In further implementations, the electronic device500may be any other electronic device that processes data.

Some non-limiting examples are provided below.

EXAMPLES

Example 1 may include a package substrate, comprising: a layer having a layer surface that is planarized; a via within the layer, wherein the via includes a via surface that is exposed on the layer surface, and wherein the via surface is planarized; and a bond pad on the layer surface, wherein a first thickness of the bond pad includes a seed layer on the via surface, and wherein a second thickness of the bond pad includes a plating stack on the seed layer.

Example 2 may include the package substrate of Example 1 or some other example herein, wherein the seed layer is a titanium-copper (Ti—Cu) layer, and wherein the titanium is on the layer surface, and wherein the copper is on the titanium.

Example 3 may include the package substrate of Example 2 or some other example herein, wherein a thickness of the titanium is less than 0.5 micrometers (um) and a thickness of the copper is less than 2.5 um.

Example 4 may include the package substrate of Example 1 or some other example herein, wherein the seed layer is one of a titanium layer, a tungsten-copper layer, wherein the tungsten is on the layer surface, and wherein the copper is on the tungsten, or a tantalum-copper layer, wherein the tantalum is on the layer surface, and wherein the copper is on the tantalum.

Example 5 may include the package substrate of Example 1, 2, 4, or some other example herein, wherein the plating stack is a nickel-palladium-gold stack, and wherein nickel is on the seed layer, palladium is on the nickel, and gold is on the palladium.

Example 6 may include the package substrate of Example 5 or some other example herein, wherein a thickness of the nickel is less than 10 um, a thickness of the palladium is less than 0.5 um, and a thickness of the gold is less than 5 um.

Example 7 may include the package substrate of Example 1, 2, 4, or some other example herein, wherein the plating stack is a cobalt/tungsten alloy-palladium-gold stack, and wherein the cobalt/tungsten alloy is on the seed layer, palladium is on the cobalt/tungsten alloy, and gold is on the palladium.

Example 8 may include the package substrate of Example 1, 2, 4, or some other example herein, wherein the plating stack is a nickel-copper stack, and wherein nickel is on the seed layer and copper is on the nickel.

Example 9 may include the package substrate of Example 1, 2, 4, or some other example herein, wherein the plating stack is one of an electrolytic stack or an electroless plating stack.

Example 10 may include the package substrate of Example 1, 2, 4, or some other example herein, further comprising solder on the bond pad.

Example 11 may include an integrated circuit (IC) package, comprising: a package substrate, wherein the package substrate includes a dielectric layer having a dielectric surface that is planarized; a via buried in the dielectric layer, wherein the via includes a via surface that is exposed on the dielectric surface, and wherein the via surface is planarized; and a bond pad on the dielectric surface, wherein a first thickness of the bond pad includes a surface finish on the via surface, and wherein a second thickness of the bond pad includes a plating stack on the surface finish; a die that includes an IC pad; and a solder ball coupled with the bond pad and the IC pad, to form a first level interconnect between the substrate package and the IC die.

Example 12 may include the IC package of Example 11 or some other example herein, wherein the surface finish is a seed layer that includes titanium and copper.

Example 13 may include the IC package of Example 12 or some other example herein, wherein a thickness of the titanium is less than 0.5 micrometers (um) and a thickness of the copper is less than 2.5 um.

Example 14 may include the IC package of Example 11, 12, 13, or some other example herein, wherein the plating stack is a nickel-palladium-gold stack, and wherein nickel is on top of the surface finish, palladium is on top of the nickel, and gold is on top of the palladium.

Example 15 may include the IC package of Example 14 or some other example herein, wherein a thickness of the nickel is less than 10 um, a thickness of the palladium is less than 0.5 um, and a thickness of the gold is less than 5 um.

Example 16 may include the IC package of Example 14 or some other example herein, wherein the plating stack is an electrolytic stack.

Example 17 may include a method of producing a package substrate, comprising: creating a via on a pad; burying the via in a dielectric applied over the via and the pad; planarizing the dielectric to reveal a top of the via through a flat surface of the dielectric; depositing a seed layer over the flat surface, wherein the seed layer is to cover the via; and plating a nickel-palladium-gold (NPG) stack on the seed layer over the via, wherein the seed layer and NPG stack form a bond pad on the via.

Example 18 may include the method of Example 17 or some other example herein, wherein planarizing the dielectric to reveal the top of the via through the flat surface of the dielectric includes using a chemical process, a mechanical process, or a chemical-mechanical (CMP) process to planarize the dielectric to reveal the top of the via through the flat surface of the dielectric.

Example 19 may include the method of Example 17, 18, or some other example herein, further comprising: defining a size or shape of the bond pad; placing a lamination on the seed layer, wherein the lamination includes an opening over the via, and wherein the NPG stack is plated in the opening; removing the lamination; and removing the seed layer exposed by removal of the lamination.

Example 20 may include the method of Example 17, 18, or some other example herein, further comprising placing solder on the bond pad.