CAPACITOR CIRCUIT OF A MULTI-BANK ARRAY TYPE AND A CAPACITANCE VARIABLE CIRCUIT HAVING THE SAME

A multi-bank array type capacitor circuit is provided. The capacitor circuit includes a first cap bank including first to mth switch-capacitor circuits which are connected in parallel with each other, wherein the first to mth switch-capacitor circuits have different capacitances based on a first weight; and a second cap bank, connected in parallel with the first cap bank, and including first to mth switch-capacitor circuits which are connected in parallel with each other, wherein the first to mth switch-capacitor circuits have different capacitances based on a second weight that is different from the first weight.

BACKGROUND

The following description relates to a capacitor circuit of a multi-bank array type and a capacitance variable circuit having the same.

2. Description of Related Art

Typically, bands of various frequencies may be implemented in a Radio Frequency (RF) field, and in a process of integrating these various frequency bands, it is becoming increasingly difficult and complicated to implement an antenna that can utilize all of these various frequency bands or multi-bands. Accordingly, it may be beneficial to implement a switch that converts impedance of the antenna.

Typically, when an array of capacitors is used to set various capacitance values, typically, a binary weighted method may be implemented.

However, the binary weighted method may not be suitable to tune capacitance for impedance tuning of the antenna.

A typical capacitor circuit of a multi-bank array type may include a binary weighted array capacitor that implements a binary weighted array, and although it is simple, a uniform distribution of capacitance is not uniform depending on an impedance matching frequency of the antenna. Because a frequency “f” and capacitance “c” have a relationship depending on the equation ‘

when the frequency is tuned using the capacitance, a rough frequency distribution is shown as the frequency increases, and conversely a dense frequency distribution is shown as the frequency decreases.

Accordingly, for a typical capacitor circuit that tunes a frequency using a capacitance by implementing a binary weighted method, it may be difficult to uniformly tune when the frequency band changes, and thus there is a problem that tuning may not at a level that a user desires.

SUMMARY

In a general aspect, a multi-bank array type capacitor circuit includes a first cap bank including first to mthswitch-capacitor circuits connected in parallel with each other, wherein the first to mthswitch-capacitor circuits are configured to have different capacitances based on a first weight; and a second cap bank connected in parallel with the first cap bank, and including first to mthswitch-capacitor circuits which are connected in parallel with each other, wherein the first to mthswitch-capacitor circuits are configured to have different capacitances based on a second weight that is different from the first weight, wherein m is a natural number equal to or greater than 2.

Each of the first to mthswitch-capacitor circuits of the first cap bank may include a capacitor and a switch connected in series with each other, and wherein respective capacitors of the first to mthswitch-capacitor circuits of the first cap bank may be configured to have different capacitances based on the first weight.

Each of the first to mthswitch-capacitor circuits of the second cap bank may include a capacitor and a switch connected in series with each other, and wherein respective capacitors of the first to mthswitch-capacitor circuits of the second cap bank may be configured to have different capacitances based on the second weight.

The capacitor circuit may include a set of cap banks comprising the second cap bank to a nthcap bank; wherein the nthcap bank may be connected in parallel with the first cap bank or the second cap bank, and the nthcap bank may include first to mthswitch-capacitor circuits which are connected in parallel with each other, wherein the first to mthswitch-capacitor circuits of the nthcap bank may be configured to have different capacitances based on an nthweight that is different from the first weight or the second weight, and wherein n is a natural number that is greater than or equal to 3.

Each of the first to mthswitch-capacitor circuits of the nthcap bank may include a capacitor and a switch connected in series with each other.

Respective capacitors of the first to mthswitch-capacitor circuits of the nthcap bank may be configured to have different capacitances based on the nthweight.

In a general aspect, a capacitance variable circuit includes a capacitor circuit configured to have at least a first cap bank and a second cap bank; and a control circuit configured to control a change in capacitance of at least one of the first cap bank and the second cap bank, wherein the first cap bank includes first to mthswitch-capacitor circuits which are connected in parallel with each other, wherein the first to mthswitch-capacitor circuits are configured to have different capacitances based on a first weight, wherein the second cap bank is connected in parallel with the first cap bank, and includes first to mthswitch-capacitor circuits connected in parallel with each other, and wherein the first to mthswitch-capacitor circuits are configured to have different capacitances based on a second weight that is different from the first weight.

Each of the first to mthswitch-capacitor circuits of the first cap bank may include a capacitor and a switch connected in series with each other, and wherein respective capacitors of the first to mthswitch-capacitor circuits of the first cap bank may be configured to have different capacitances based on the first weight.

Each of the first to mthswitch-capacitor circuits of the second cap bank may include a capacitor and a switch connected in series with each other, and wherein respective capacitors of the first to mthswitch-capacitor circuits of the second cap bank may be configured to have different capacitances based on the second weight.

The capacitance variable circuit may further include a set of cap banks including the second cap bank to a nthcap banks; wherein the nthcap bank may be connected in parallel with the first cap bank or second cap bank, and the nthcap bank may include first to mthswitch-capacitor circuits which may be connected in parallel with each other, wherein the first to mthswitch-capacitor circuits of the nthcap bank may be configured to have different capacitances based on an nthweight that is different from the first weight or the second weight, and wherein n is a natural number that is greater than or equal to 3.

Each of the first to mthswitch-capacitor circuits of the nthcap bank may include a capacitor and a switch connected in series with each other.

Respective capacitors of the first to mthswitch-capacitor circuits of the nthcap bank may be configured to have different capacitances based on the nthweight.

The control circuit may include a switch controller configured to convert a received control bit into a switch control signal; and a cap switch buffer configured to select at least one cap bank from among a plurality of cap banks comprised in the capacitor circuit based on the switch control signal and to control a change in capacitance of the selected cap bank based on the switch control signal.

The switch controller may include a first decoder configured to generate a bank selection signal of the switch control signal based on an upper bit of the received control bit; and a second decoder configured to generate a capacitor selection signal of the switch control signal based on a lower bit of the control bit.

The cap switch buffer may include a first inverter device and a second inverter device which are connected in series.

The first inverter device and the second inverter device may be configured to transfer the bank selection signal of the switch control signal and the capacitor selection signal to a corresponding cap bank of the capacitor circuit.

In a general aspect, a capacitance circuit includes a control circuit; and a cap bank circuit comprising a plurality of cap banks connected in parallel with each other, each of the plurality of cap banks comprising a plurality of switch capacitor circuits connected in parallel with each other, wherein each of the plurality of switch capacitor circuits comprises a switch and a capacitor connected in series with each other, wherein each of the capacitors is configured to have different non-binary weighted capacitances; and wherein the control circuit is configured to select a cap bank of the plurality of cap banks based on a first control signal, and select one or more capacitors of the switch capacitor circuits based on a second control signal.

The control circuit may be configured to control a change in capacitance of the selected cap bank.

The control circuit may be configured to selectively turn on or turn off a switch of a selected switch capacitor circuit based on the second control signal.

DETAILED DESCRIPTION

The terminology used herein is for the purpose of describing particular examples only, and is not to be used to limit the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term “and/or” includes any one and any combination of any two or more of the associated listed items. As used herein, the terms “include,” “comprise,” and “have” specify the presence of stated features, numbers, operations, elements, components, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, elements, components, and/or combinations thereof.

In addition, terms such as first, second, A, B, (a), (b), and the like may be used herein to describe components. Each of these terminologies is not used to define an essence, order, or sequence of a corresponding component but used merely to distinguish the corresponding component from other component(s).

Also, in the description of example embodiments, detailed description of structures or functions that are thereby known after an understanding of the disclosure of the present application will be omitted when it is deemed that such description will cause ambiguous interpretation of the example embodiments.

Hereinafter, examples will be described in detail with reference to the accompanying drawings, and like reference numerals in the drawings refer to like elements throughout.

One or more examples may provide a capacitor circuit in which each of a plurality of cap banks includes an array capacitor circuit and is implemented to have a different capacitance weight, and a capacitance variable circuit having the same.

In the one or more examples, the capacitance may be tuned in a tuning range of different capacitances for each cap bank by implementing each of a plurality of cap banks to include an array capacitor and each cap bank to have a different capacitance weight.

FIG.1illustrates an example capacitor circuit, in accordance with one or more embodiments.

Referring toFIG.1, the example capacitor circuit may include a first cap bank100-1and a second cap bank100-2.

The first cap bank100-1may include first to mthswitch-capacitor circuits SC1-1to SC1-m(where m is a natural number that is equal to, or greater than, 2) which may be connected in parallel with each other.

The first to mthswitch-capacitor circuits SC1-1to SC1-mof the first cap bank100-1may include different capacitances of, or based on, a first weight WT1.

The second cap bank100-2may be connected in parallel with the first cap bank100-1, and may include first to mthswitch-capacitor circuits SC2-1to SC2-mwhich are connected in parallel with each other.

The first to mthswitch-capacitor circuits SC1-1to SC1-mof the first cap bank100-1may include different capacitances of, or based on, a second weight WT2that is different from the first weight WT1.

Each of the first to mthswitch-capacitor circuits SC1-1to SC1-mof the first cap bank100-1may include a capacitor and a switch which are connected in series with each other.

In an example, the first switch-capacitor circuit SC1-1of the first cap bank100-1may include a first capacitor C1-1and a first switch S1-1which are connected in series with each other.

Additionally, the mthswitch-capacitor circuit SC1-mof the first cap bank100-1may include an mthcapacitor C1-mand an mthswitch S1-mwhich are connected in series with each other.

The first to mthcapacitors C1-1and C1-2to C1-mof the first cap bank100-1may be set to have different capacitances of, or based on, the first weight WT1.

In an example, the first weight WT1is k1, the first capacitor C1-1of the first cap bank100-1is k1*(2{circumflex over ( )}0) pF, and the mthcapacitor C1-mof the first cap bank100-1becomes k1*(2{circumflex over ( )}(m−1)) pF.

Each of the first to mthswitch-capacitor circuits SC2-1to SC2-mof the second cap bank100-2may include a capacitor and a switch which are connected in series with each other.

In an example, the first switch-capacitor circuit SC2-1of the second cap bank100-2may include a first capacitor C2-1and a first switch S2-1which are connected in series with each other.

Additionally, the mthswitch-capacitor circuit SC2-mof the second cap bank100-2may include an mthcapacitor C2-mand an mthswitch S2-mwhich are connected in series with each other.

The first to mthcapacitors C2-1to C2-mof the second cap bank100-2may be set to have different capacitances based on the second weight WT2.

In an example, the second weight WT2may be k2, the first capacitor C2-1of the second cap bank100-2is k2*(2{circumflex over ( )}0), and the mthcapacitor C2-mof the first cap bank100-1becomes k2*(2{circumflex over ( )}(m−1)) pF.

FIG.1illustrates an example in which the capacitor circuit100includes two first and second cap banks100-1and100-2. However, this is only an example, and the number of cap banks is not limited to two. In an example, the number of cap banks may be less than 2 or greater than two.

For each drawing of the one or more examples, unnecessary redundant descriptions of the same reference numerals and components having the same function may be omitted, and possible differences may be described for each drawing.

FIG.2illustrates an example capacitor circuit, in accordance with one or more embodiments, andFIG.3illustrates an example capacitor circuit, in accordance with one or more embodiments.

Referring toFIG.2, the example capacitor circuit100may further include respective first, second, and third cap banks100-1,100-2, and100-3.

The first cap bank100-1may include first to fourth switch-capacitor circuits SC1-1to SC1-4.

In an example, the first switch-capacitor circuit SC1-1of the first cap bank100-1may include a first capacitor C1-1and a first switch S1-1which are connected in series with each other. The second switch-capacitor circuit SC1-2of the first cap bank100-1may include a second capacitor C1-2and a third switch S1-2which are connected in series with each other. The third switch-capacitor circuit SC1-3of the first cap bank100-1may include a third capacitor C1-3and a third switch S1-3which are connected in series with each other. Additionally, the fourth switch-capacitor circuit SC1-4of the first cap bank100-1may include a fourth capacitor C1-4and a fourth switch S1-4which are connected in series with each other.

The second cap bank100-2may include first to fourth switch-capacitor circuits SC2-1to SC2-4.

In an example, the first switch-capacitor circuit SC2-1of the second cap bank100-2may include a first capacitor C2-1and a first switch S2-1which are connected in series with each other. The second switch-capacitor circuit SC2-2of the second cap bank100-2may include a second capacitor C2-2and a second switch S2-2which are connected in series with each other. The third switch-capacitor circuit SC2-3of the second cap bank100-2may include a third capacitor C2-3and a third switch S2-3which are connected in series with each other. Additionally, the fourth switch-capacitor circuit SC2-4of the second cap bank100-2may include a fourth capacitor C2-4and a fourth switch S2-4which are connected in series with each other.

The third cap bank100-3may include first to fourth switch-capacitor circuits SC3-1to SC3-4.

In an example, the first switch-capacitor circuit SC3-1of the third cap bank100-3may include a first capacitor C3-1and a first switch S3-1which are connected in series with each other. The second switch-capacitor circuit SC3-2of the third cap bank100-3may include a second capacitor C3-2and a second switch S3-2which are connected in series with each other. The third switch-capacitor circuit SC3-3of the third cap bank100-3may include a third capacitor C3-3and a third switch S3-3which are connected in series with each other. Additionally, the fourth switch-capacitor circuit SC3-4of the third cap bank100-3may include a fourth capacitor C3-4and a fourth switch S3-4which are connected in series with each other.

FIG.2illustrates an example in which the capacitor circuit100includes three first to third cap banks100-1,100-2, and100-3. However, this is only an example, and the examples are not limited to this example. Additionally,FIG.2illustrates examples in which each of the first, second, and third cap banks100-1,100-2, and100-3includes four first to fourth switch-capacitors. However, this is only an example, and the examples are not limited to these examples.

Referring toFIG.3, the capacitor circuit100may further include third to nthcap banks100-3to100-nin the capacitor circuit ofFIG.1.

Referring again toFIG.3, the third cap bank100-3may be connected in parallel to the first and second cap banks100-1and100-2(for example, the first and second cap banks100-1and100-2illustrated inFIG.1), and may include first to mthswitch-capacitor circuits SC3-1to SC3-mwhich are connected in parallel with each other.

The first to mthswitch-capacitor circuits SC3-1to SC3-mof the third cap bank100-3may be set to have different capacitances based on a third weight WT3that is different from the first and second weights WT1and WT2.

Referring toFIG.3, the nthcap bank100-nmay include first to mthswitch-capacitor circuits SCn1to SCn-m connected in parallel to other cap banks such as the first to third cap banks100-1,100-2, and100-3, and connected in parallel with each other.

The first to mthswitch-capacitor circuits SCn-1to SCn-m of the nthcap bank100-nmay include different capacitances of an nthweight WTn that is different from the first to third weights WT1to WT3.

Each of the first to mthswitch-capacitor circuits SC3-1to SC3-mof the third cap bank100-3may include a capacitor and a switch which are connected in series with each other.

In an example, the first switch-capacitor circuit SC3-1of the third cap bank100-3may include a first capacitor C3-1and a first switch S3-1which are connected in series with each other.

Additionally, the mthswitch-capacitor circuit SC3mof the third cap bank100-3may include an mthcapacitor C3-mand an mthswitch S3-mwhich are connected in series with each other.

The first to mthcapacitors C3-1to C3-mof the third cap bank100-3may be set to have different capacitances based on the third weight WT3.

In an example, the third weight WT3is k3, the third capacitor C3-1of the third cap bank100-3is k3*(2{circumflex over ( )}0), and the mthcapacitor C3-mof the third cap bank100-3becomes k3*(2{circumflex over ( )}(m−1)) pF.

Each of the first to mthswitch-capacitor circuits SCN-1to SCN-m of the Nthcap bank100-N may include a capacitor and a switch which are connected in series with each other.

In an example, the first switch-capacitor circuit SCN-1of the Nthcap bank100-N may include a first capacitor CN-1and a first switch SN-1which are connected in series with each other.

Additionally, the mthswitch-capacitor circuit SCN-m of the Nthcap bank100-N may include an mthcapacitor CN-m and an mthswitch SN-m which are connected in series with each other.

Each of the first to mthswitch-capacitor circuits SCn-1to SCn-m of the nthcap bank100-nis a capacitor which may be set to have different capacitances based on the Nthweight WTN.

In an example, the third weight WTN is kN, the third capacitor CN-1of the Nthcap bank100-N is kN*(2{circumflex over ( )}0), and the mthcapacitor CN-m of the Nthcap bank100-N is kN*(2{circumflex over ( )}(m−1)) pF.

In one or more examples, the first weight WT1, the second weight WT2, and the Nthweight WTN are weights to set different capacitances, and may be binary weights as in the example above, but the one or more examples are not limited thereto, and may be a variety of weights, such as double weights and triple weights, and they are not limited to a specific multiple relationship as long as different weights are applied for each bank.

FIG.4illustrates an example capacitance variable circuit, in accordance with one or more embodiments.

Referring toFIG.4, an example capacitance variable circuit may include a cap bank circuit100including at least a first cap bank100-1and a second cap bank100-2, and a control circuit200that controls a variation of a capacitance of the cap bank circuit100.

The first cap bank100-1may include first to mthswitch-capacitor circuits SC1-1to SC1-mwhich are connected in parallel with each other.

The first to mthswitch-capacitor circuits SC1-1to SC1-mmay include different capacitances based on a first weight WT1.

The second cap bank100-2may be connected in parallel to the first cap bank100-1, and may include first to mthswitch-capacitor circuits SC2-1to SC2-mwhich are connected in parallel with each other.

The second to mthswitch-capacitor circuits SC1-1to SC1-mmay include different capacitances based on a second weight WT2that is different from the first weight WT1.

The control circuit200may select at least one of the first and second cap banks included in the cap bank circuit100, and may control a change in capacitance of the selected cap bank.

Each of the first to mthswitch-capacitor circuits SC1-1to SC1-mof the first cap bank100-1may include a capacitor and a switch which are connected in series with each other.

In an example, the first switch-capacitor circuit SC1-1of the first cap bank100-1may include a first capacitor SC1-1and a first switch S1-1which are connected in series with each other.

Additionally, the mthswitch-capacitor circuit SC1-mof the first cap bank100-1may include an mthcapacitor C1-mand an mthswitch S1-mwhich are connected in series with each other.

The first to mthcapacitors C1-1to C1-mof the first to mthswitch-capacitor circuits SC1-1to SC1-mof the first cap bank100-1may be set to have different capacitances based on the first weight WT1.

In an example, the first weight WT1is k1, the first capacitor C1-1of the first cap bank100-1is k1*(2{circumflex over ( )}0) pF, the second capacitor C1-2of the first cap bank100-1is k1*(2{circumflex over ( )}1) pF, and the mthcapacitor C1-mof the first cap bank100-1becomes k1*(2{circumflex over ( )}(m−1)) pF.

Each of the first to mthswitch-capacitor circuits SC2-1to SC2-mof the second cap bank100-2may include a capacitor and a switch which are connected in series to each other.

In an example, the first switch-capacitor circuit SC2-1of the second cap bank100-2may include a first capacitor C2-1and a first switch S2-1which are connected in series with each other.

Additionally, the mthswitch-capacitor circuit SC2-mof the second cap bank100-2may include an mthcapacitor C2-mand an mthswitch S2-mwhich are connected in series with each other.

Each of the first to mthcapacitors of the first to mthswitch-capacitor circuits SC2-1to SC2-mof the second cap bank100-2may be set to have different capacitances based on the second weight WT2.

In an example, the second weight WT2is k2, the first capacitor C2-1of the second cap bank100-2is k2*(2{circumflex over ( )}0), the second capacitor C2-2of the first cap bank100-1is k2*(2{circumflex over ( )}1) pF, and the mthcapacitor C1-mof the first cap bank100-1becomes k2*(2{circumflex over ( )}(m−1)) pF.

FIG.4illustrates an example in which the capacitor circuit100includes two first and second cap banks100-1and100-2, but this is only an example for convenience of description, and the one or more examples are not limited to this example.

FIG.5illustrates an example capacitance variable circuit, in accordance with one or more embodiments, andFIG.6illustrates an example capacitance variable circuit, in accordance with one or more embodiments.

Referring toFIG.5, the capacitor circuit100may further include first, second, and third cap banks100-1,100-2, and100-3.

The first cap bank100-1may include first to fourth switch-capacitor circuits SC1-1to SC1-4.

In an example, the first switch-capacitor circuit SC1-1of the first cap bank100-1may include a first capacitor C1-1and a first switch S1-1which are connected in series with each other. The second switch-capacitor circuit SC1-2of the first cap bank100-1may include a second capacitor C1-2and a third switch S1-2which are connected in series with each other. The third switch-capacitor circuit SC1-3of the first cap bank100-1may include a third capacitor C1-3and a third switch S1-3which are connected in series with each other. Additionally, the fourth switch-capacitor circuit SC1-4of the first cap bank100-1may include a fourth capacitor C1-4and a fourth switch S1-4which are connected in series with each other.

Each of the respective first to fourth switches S1-1to S1-4of the first cap bank100-1may be turned on or turned off in response to a capacitor selection signal SSC from the control circuit200.

The second cap bank100-2may include first to fourth switch-capacitor circuits SC2-1to SC2-4.

In an example, the first switch-capacitor circuit SC2-1of the second cap bank100-2may include a first capacitor C2-1and a first switch S2-1which are connected in series with each other. The second switch-capacitor circuit SC2-2of the second cap bank100-2may include a second capacitor C2-2and a second switch S2-2which are connected in series with each other. The third switch-capacitor circuit SC2-3of the first cap bank100-2may include a third capacitor C2-3and a third switch S2-3which are connected in series with each other. Additionally, the fourth switch-capacitor circuit SC2-4of the second cap bank100-2may include a fourth capacitor C2-4and a fourth switch S2-4which are connected in series with each other.

Each of the first to fourth switches S2-1to S2-4of the second cap bank100-2may be turned on or turned off in response to the capacitor selection signal SSC from the control circuit200.

The third cap bank100-3may include first to fourth switch-capacitor circuits SC3-1to SC3-4.

In an example, the first switch-capacitor circuit SC3-1of the third cap bank100-3may include a first capacitor C3-1and a first switch S3-1which are connected in series with each other. The second switch-capacitor circuit SC3-2of the third cap bank100-3may include a second capacitor C3-2and a second switch S3-2which are connected in series with each other. The third switch-capacitor circuit SC3-3of the third cap bank100-3may include a third capacitor C3-3and a third switch S3-3which are connected in series with each other. Additionally, the fourth switch-capacitor circuit SC3-4of the third cap bank100-3may include a fourth capacitor C3-4and a fourth switch S3-4which are connected in series with each other.

Each of the first to fourth switches S2-1to S2-4of the third cap bank100-3may be turned on or turned off in response to the capacitor selection signal SSC from the control circuit200.

FIG.5illustrates an example in which the capacitor circuit100includes three first and third cap banks100-1,100-2, and100-3. However, this is only an example, and the one or more embodiments are not limited to this example.

Referring toFIG.6, the example capacitor circuit100may further include third to nthcap banks100-3to100-nin the capacitor circuit ofFIG.4.

Referring toFIG.6, the third cap bank100-3may be connected in parallel with the first and second cap banks100-1and100-2(for example, the first and second cap banks100-1and100-2illustrated inFIG.4), and may include first to mthswitch-capacitor circuits SC3-1to SC3-mwhich are connected in parallel with each other.

The first to mthswitch-capacitor circuits SC3-1to SC3-mof the third cap bank100-3may be set to have different capacitances based on a third weight WT3that is different from the first and second weights WT1and WT2.

The nthcap bank100-nmay include first to mthswitch-capacitor circuits SCN1to SCN-m connected in parallel with other cap banks such as the first to third cap banks100-1,100-2, and100-3, and connected in parallel with each other.

The first to mthswitch-capacitor circuits SCN-1to SCN-m of the nthcap bank100-nmay include different capacitances based on an nthweight WTn that is different from the first to third weights WT1to WT3.

Each of the first to mthswitch-capacitor circuits SC3-1to SC3-mof the third cap bank100-3may include a capacitor and a switch which are connected in series with each other.

In an example, the first switch-capacitor circuit SC3-1of the third cap bank100-3may include a first capacitor C3-1and a first switch S3-1which are connected in series with each other.

Additionally, the mthswitch-capacitor circuit SC3mof the third cap bank100-3may include an mthcapacitor C3-mand an mthswitch S3-mwhich are connected in series with each other.

The first to mthcapacitors C3-1to C3-mof the third cap bank100-3may be set to have different capacitances based on the third weight WT3.

In an example, the third weight WT3is k3, the third capacitor C3-1of the third cap bank100-3is k3*(2{circumflex over ( )}0), and the mthcapacitor C3-mof the third cap bank100-3becomes k3*(2{circumflex over ( )}(m−1)) pF.

Each of the first to mthswitch-capacitor circuits SCN-1to SCN-m of the Nthcap bank100-N may include a capacitor and a switch which are connected in series with each other.

In an example, the first switch-capacitor circuit SCN-1of the Nthcap bank100-N may include a first capacitor CN-1and a first switch SN-1which are connected in series with each other.

Additionally, the mthswitch-capacitor circuit SCN-m of the Nthcap bank100-N may include an mthcapacitor CN-m and an mthswitch SN-m which are connected in series with each other.

Each of the first to mthswitch-capacitor circuits SCn-1to SCn-m of the nthcap bank100-nmay be a capacitor that may be set to have different capacitances based on the Nthweight WTN.

In an example, the third weight WTN is kN, the third capacitor CN-1of the Nthcap bank100-N is kN*(2{circumflex over ( )}0), and the mthcapacitor CN-m of the Nthcap bank100-N is kN*(2{circumflex over ( )}(m−1)) pF.

Referring toFIG.4toFIG.6, the control circuit200may include a switch controller210and a cap switch buffer220.

The switch controller210may convert a received control bit Scode into a switch control signal SES including a bank selection signal SSB to select at least one bank from among banks included in the capacitor circuit100based on the received control bit Scode and a capacitor selection signal SSC to control a change in capacitance of a corresponding bank selected based on the control bit Scode.

The cap switch buffer220may transmit the bank selection signal SSB and the capacitor selection signal SSC of the switch control signal SES from the switch control signal SES to the corresponding bank.

FIG.7illustrates an example switch controller, in accordance with one or more embodiments.

Referring toFIG.7, the switch controller210may include a first decoder211and a second decoder212.

The first decoder211may generate the bank selection signals SSB (SSB1to SSBn) of the switch control signal SES based on an upper bit of the received control bit Scode.

The second decoder212may generate the capacitor selection signals SSC (SSC1to SSCm) of the switch control signal SES based on a lower bit of the control bit Scode.

In an example, when the control bit Scode is 6 bits including two upper bits (2{circumflex over ( )}5 and 2{circumflex over ( )}4) and four lower bits (2{circumflex over ( )}3, 2{circumflex over ( )}2, 2{circumflex over ( )}1, and 2{circumflex over ( )}0), the first decoder211may generate the bank selection signals SSB (SSB1to SSBn) based on two upper bits (2{circumflex over ( )}5 and 2{circumflex over ( )}4).

The second decoder212may generate the capacitor selection signals SSC (SSC1to SSCm) based on four lower bits (2{circumflex over ( )}3, 2{circumflex over ( )}2, 2{circumflex over ( )}1, and 2{circumflex over ( )}0).

FIG.8illustrates an example of a cap switch buffer, in accordance with one or more embodiments.

Referring toFIG.8, the example cap switch buffer220may include a first inverter device221and a second inverter device222which are connected in series.

The first inverter device221and the second inverter device222may transmit the bank selection signals SSB1to SSBn and the capacitor selection signals SSC1to SSCm of the switch control signal SES to corresponding cap banks100-1and100-2of the capacitor circuit100.

Hereinafter, as illustrated inFIG.3, the capacitor circuit100may include first, second, and third cap banks100-1,100-2, and100-3, and a switching on or switching off state depending on the switch control signal Scode for an example where the first, second, and third cap banks100-1,100-2, and100-3respectively include first, second, third, and fourth switches SC1-1to SC1-4, SC2-1to SC2-4, SC3-1to SC3-4, and SC4-1to SC4-4will be described with reference toFIG.9toFIG.11.

Additionally, as illustrated inFIG.4toFIG.6, the bank selection signal SSB may include first to mthbank selection signals SE1to SEm.

In an example, when the first bank selection signal SE1is at a high level, the first cap bank100-1may be selected, and when the mthbank selection signal SEm is at a high level, the mthcap bank100-mmay be selected.

Referring toFIG.8, the cap switch buffer220may include two inverters which are connected in series to perform a buffer function, which is only an example, and the one or more examples are not limited thereto.

Hereinafter,FIG.9,FIG.10, andFIG.11are based on the circuit illustrated inFIG.5, and the control bit Scode will be described as an example of 6 bits including two upper bits (2{circumflex over ( )}5 and 2{circumflex over ( )}4) and four lower bits (2{circumflex over ( )}3, 2{circumflex over ( )}2, 2{circumflex over ( )}1, and 2{circumflex over ( )}0).

FIG.9illustrates an example switch state table of a first cap bank depending on a switch control signal, in accordance with one or more embodiments.

Referring toFIG.9, the first cap bank100-1may be selected by a first bank selection signal SE1of the bank selection signal SSB based on a logic state 00 of the two upper bits (2{circumflex over ( )}5 and 2{circumflex over ( )}4) in the 6-bit switch control signal Scode. In this example, depending on the capacitor selection signal SSC based on a logic state of the four lower bits (2{circumflex over ( )}3, 2{circumflex over ( )}2, 2{circumflex over ( )}1, and 2{circumflex over ( )}0) in the 6-bit switch control signal Scode, as illustrated inFIG.9, the four switches S1-1, S1-2, S1-3, and S1-4may be controlled in different switching states, and thus the capacitance may be varied.

In this example, all switches of the second and third cap banks100-2and100-3may be in an off state depending on second and third bank selection signals SE2and SE3of the bank selection signal SSB based on the logic state 00 of the two upper bits (2{circumflex over ( )}5 and 2{circumflex over ( )}4) in the 6-bit switch control signal Scode.

FIG.10illustrates an example switch state table of a second cap bank depending on a switch control signal, in accordance with one or more embodiments.

Referring toFIG.10, for the first cap bank100-1, all switches may be turned on by the first bank selection signal SE1of the bank selection signal SSB based on a logic state 01 of the two upper bits (2{circumflex over ( )}5 and 2{circumflex over ( )}4) in the 6-bit switch control signal Scode.

The second cap bank100-2may be selected by a second bank selection signal SE2of the bank selection signal SSB based on a logic state 01 of the two upper bits (2{circumflex over ( )}5 and 2{circumflex over ( )}4) in the 6-bit switch control signal Scode. In this example, depending on the capacitor selection signal SSC based on a logic state of the four lower bits (2{circumflex over ( )}3, 2{circumflex over ( )}2, 2{circumflex over ( )}1, and 2{circumflex over ( )}0) in the 6-bit switch control signal Scode, as illustrated inFIG.10, the four switches S2-1, S2-2, S2-3, and S2-4are controlled in different switching states, and thus the capacitance may be varied.

In this example, all the switches of the third cap bank100-3may be in an off state depending on the third bank selection signal SE3of the bank selection signal SSB based on the logic state 01 of the two upper bits (2{circumflex over ( )}5 and 2{circumflex over ( )}4) in the 6-bit switch control signal Scode.

FIG.11illustrates an example switch state table of a third cap bank depending on a switch control signal, in accordance with one or more embodiments.

Referring toFIG.11, for the first and second cap banks100-1and100-2, all switches may be turned on by the first and second bank selection signals SE1and SE2of the bank selection signal SSB based on a logic state 11 of the two upper bits (2{circumflex over ( )}5 and 2{circumflex over ( )}4) in the 6-bit switch control signal Scode.

The third cap bank100-2may be selected by a first bank selection signal SE3of the bank selection signal SSB based on a logic state 11 of the two upper bits (2{circumflex over ( )}5 and 2{circumflex over ( )}4) in the 6-bit switch control signal Scode. In this example, depending on the capacitor selection signal SSC based on a logic state of the four lower bits (2{circumflex over ( )}3, 2{circumflex over ( )}2, 2{circumflex over ( )}1, and 2{circumflex over ( )}0) in the 6-bit switch control signal Scode, as illustrated inFIG.11, the four switches S2-1, S2-2, S2-3, and S2-4are controlled in different switching states, and thus the capacitance may be varied.

In an example, the switch control circuit200of the example capacitance variable circuit may be implemented as a computing environment in which a processor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc.), a memory (e.g., a volatile memory (e.g., a RAM, etc.)), a non-volatile memory (e.g., a ROM, a flash memory, etc.), an input device (e.g., a keyboard, a mouse, a pen, a voice input device, a touch input device, an infrared camera, a video input device, etc.), an output device (e.g., a display, a speaker, a printer, etc.), and a communication connection device (e.g., a modem, a network interface card (NIC)), an integrated network interface, a radio frequency transmitter/receiver, an infrared port, a USB interface, etc.) are interconnected (using, e.g., a peripheral component interconnection (PCI), a USB, firmware (IEEE 1394), an optical bus structure, a network, etc.).

The computing environment may be implemented as a personal computer, a server computer, a handheld or laptop device, a mobile device (e.g., a mobile phone, a PDA, a media player, etc.), a multiprocessor system, consumer electronics, a minicomputer, a mainframe computer, a distributed computing environment including any of the foregoing systems or devices, etc., but the examples are not limited thereto.