Semiconductor device

A semiconductor device is disclosed. One embodiment includes a trench within a semiconductor body and a gate insulating structure at opposing sidewalls within the trench. A gate electrode structure adjoins the gate insulating structure within the trench and a dielectric structure adjoins the gate electrode structure within the trench. The gate electrode structure is in contact with the semiconductor body at a bottom side of the trench and is electrically coupled to a drain zone over an element having a voltage blocking capability.

BACKGROUND

In semiconductor devices such as power transistors breakdown voltage and on-state resistance depend on parameters such as doping and thickness of a drift zone. Whereas a high doping density and a short extension of a drift zone may lead to a low on-state resistance and a low device breakdown voltage, lower doping densities and longer extensions of the drift zone may lead to a higher on-state resistance and a higher device breakdown voltage. In order to improve both, lowering the on-state resistance and increasing the voltage blocking capability, a decoupling between these two measures is desirable. One configuration of a vertical MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a TEDFET (Trench Extended Drain Field Effect Transistor) which allows for an improved decoupling of voltage blocking capability and on-state resistance compared to conventional MOSFETs by controlling the conductivity in the drift zone by drift control zones. Manufacture of TEDFETs may include processes having a considerable impact on costs and device reliability.

With regard to a semiconductor device including drift zones and drift control zones, a need exists for an improved device reliability.

DETAILED DESCRIPTION

In one or more embodiments, a semiconductor device as described herein includes a trench within a semiconductor body and a gate insulating structure at opposing sidewalls within the trench. A gate electrode structure adjoins the gate insulating structure within the trench and a dielectric structure adjoins the gate electrode structure within the trench. Furthermore, the gate electrode structure is in contact with the semiconductor body at a bottom side of the trench and is electrically coupled to a drain zone over an element having a voltage blocking capability.

According to one embodiment of a method of manufacturing a semiconductor device as described hereinafter, a trench is formed within a semiconductor body and a gate insulating structure is formed at opposing sidewalls within the trench. A gate electrode structure is formed adjoining the gate insulating structure within the trench, the gate electrode structure being formed in contact with the semiconductor body at a bottom side of the trench. At a bottom side of the trench, the gate electrode structure is electrically coupled to a drain region over an element including a blocking voltage capability. Then, a dielectric structure is formed adjoining the gate electrode structure within the trench.

FIG. 1illustrates a cross-sectional view of a portion of a semiconductor device100such as a TEDFET including a trench102formed within a semiconductor body104. A gate insulating structure106is formed at opposing sidewalls within the trench102. A gate electrode structure110which may include a first gate electrode layer having portions108,108′ of different conductivity type and a second gate electrode layer having portions109,109′ of different conductivity type adjoins the gate insulating structure106. A dielectric structure115which may include a dielectric layer113and a dielectric filling material114adjoins the gate electrode structure110within the trench102. Within the dielectric structure115a void117may be present.

The gate insulating structure106, the gate electrode structure110and the dielectric structure115within the trench102form a drift control zone configured to control the conductivity of a channel region119extending from a source zone120to a drain zone122through a body region125and a drift zone126. The gate electrode structure110is in contact with the semiconductor body104at a bottom side128of the trench102and electrically coupled to the drain zone122over an element133having a voltage blocking capability. Element133may be a diode including regions131,132of different conductivity type.

By controlling the conductivity in the channel region119by field-effect via the drift control zone formed within the trench102, the conductivity in the drift zone126may be increased without increasing the doping density within that zone. The increase of the conductivity may be achieved by forming an accumulation zone in the channel region119adjoining the gate insulating structure by field-effect or by forming an inversion zone in the channel region119by field-effect. A thickness of the gate insulating structure may be chosen such that a required insulation strength between the drift zone126and the drift control zone can be achieved taking into account a voltage drop characteristic along the drift zone126and the voltage drop characteristic along the gate electrode structure110in reverse mode, i.e., when applying a blocking voltage.

In one embodiment illustrated inFIG. 1, portions108′,109′ of the semiconductor gate electrode structure110are of different conductivity type than portions108,109, i.e., portions108′ and109′ are of p-type and portions108and109are of n-type. According to another embodiment, the conductivity type, i.e., n-type or p-type, of the regions108,108′,109,109′ may be vice versa to the illustration ofFIG. 1. Furthermore, a doping density within portions108′,109′ may be higher than in portions108,109. A doping density of regions108,109may be less than 1015cm−3or even less than 1014cm−3. A conductivity type of portions108,109of gate electrode structure110may also be equal to the conductivity type of portions108′,109′ provided that the doping density in portions108′,109′ is higher than in portions108,109.

An interface between regions108,108′ and accordingly regions109,109′ may be located in a depth that corresponds or approximately corresponds to the depth of an interface between body region125and drift zone126. The conductivity type of the gate electrode structure110may also be independent from the conductivity type of the source and drift zones120,122provided that the gate electrode structure110is electrically coupled to the drift zone122over the element133including a voltage blocking capability.

The doping density of the drift zone126may be smaller than the doping density in the body region125and may have a value of less than 1015cm−3or even less than 1014cm−3. In the embodiment illustrated inFIG. 1, the conductivity type of the drift zone126is n-type and different from the p-type conductivity of body region125. In this case an accumulation zone may be formed in the channel region119in an on-state of the device100. According to another embodiment, the conductivity type of the drift zone126may also comply with the conductivity type of the body region125. In this case, an inversion zone may be formed in the channel region119in an on-state of the device100.

Device100illustrated in the cross-sectional view ofFIG. 1is an example of one embodiment. Further embodiments may include different structural elements.

The gate electrode structure110may also be formed of one or more than two semiconductor layers. These semiconductor layers may be non-epitaxial layers such as polycrystalline or amorphous layers. As an example, the gate electrode structure may include a polycrystalline or an amorphous silicon layer. According to another embodiment, the gate electrode structure may include SiC or GaN. Latter materials have a wider band gap than Si leading to a beneficial lower reverse current within the drift control zone.

The dielectric structure may also include a single or more than two dielectric layers such as undoped or doped silicon oxide layers, e.g., BPSG (Boro-Phospho-Silicate-Glass), PSG (Phospho-Silicate-Glass).

The voltage blocking capability of element133may be chosen such that in an on-state of device100having a low voltage applied to source zone120and drain zone122, e.g., 0 V to source zone120and 1 V to drain zone122in case of a n-channel MOSFET, and a comparatively higher voltage applied to the gate electrode structure110, e.g., 10 V of 15 V, a current flow from the gate electrode structure110to the drain zone122is prevented by the voltage blocking capability of element133.

FIGS. 2A to 2Hillustrate schematic cross-sectional views of a portion of a semiconductor body during manufacture of a semiconductor device such as device100ofFIG. 1. Apart from elements and process features illustrated with regard to the following cross-sectional views, further processes may be carried out prior or after any one or in between any two of the process stages illustrated with reference toFIGS. 2A to 2H.

Referring to the schematic cross-sectional view of a portion of a semiconductor body204, a trench202is formed within the semiconductor body204extending through a drift zone226into a drain zone222. The trench202may be formed by an etch process using an etching mask on a surface250of the semiconductor body204, for example.

The semiconductor body204may include an epitaxial layer formed on a semiconductor substrate. For example, the drift zone226may be grown on a semiconductor substrate including the drain zone222. The drain zone may be of n-type conductivity and may have a higher doping concentration than the drift zone226which may be of either n-type or p-type conductivity. The semiconductor body204may be of Si or include Si.

As illustrated in the cross-sectional view ofFIG. 2B, p-type dopants such as B are introduced into the semiconductor body204in a region231at a bottom side of the trench202. The p-type dopants may be implanted into the semiconductor body204using an implant mask which may include a stray oxide, for example (not illustrated inFIG. 2B). The p-type dopants may also be introduced into region231by diffusion.

Referring to the schematic cross-sectional view of a portion of the semiconductor body204illustrated inFIG. 2C, n-type dopants such as P or As are introduced into a region232embedded in region231. The n-type dopants may be implanted or diffused into region232(not illustrated inFIG. 2C). N-type region232adjoins to a bottom side of the trench202. N-Type region232together with p-type region231constitute a diode233as an element having a voltage blocking capability which is electrically coupled to the drain zone222.

A gate insulating structure206is formed at sidewalls and at a bottom side of the trench202as well as on the surface250of the semiconductor body204. The gate insulating structure206may be formed as a gate oxide layer such as a thermal oxide, i.e., an oxide formed by thermal oxidation in a high temperature process at temperatures in a range between 800° C. to 1200° C., for example. By forming the gate insulating structure206of a thermal oxide layer similar to the gate oxide of a known MOS transistor, a beneficial interface having a low defect density may be achieved between the gate insulating structure206and the drift zone226which may improve the device reliability. When forming the gate insulating structure206of a gate oxide layer, access oxygen may be introduced into this layer omitting annealing in a nutritious atmosphere. The gate insulating structure206may include one or a plurality of insulating layers.

Referring to the schematic cross-sectional view ofFIG. 2D, a first gate electrode layer208is formed on the gate insulating structure206. The first gate electrode layer208may be formed by deposition of undoped or slightly doped polysilicon, for example. The first gate electrode layer may also be formed of a different polycrystalline or amorphous semiconductor materials. A thickness of the first gate electrode layer208may be in a range of 10 nm to 1000 nm, in one embodiment 50 nm to 100 nm, for example.

Thereafter, as illustrated in the schematic cross-sectional view ofFIG. 2E, the gate insulating structure206and the first gate electrode layer208are patterned, e.g., by anisotropic etching removing those parts of these elements which are either on the surface250of the semiconductor body204or on a bottom side of the trench202. Thus, the gate insulating structure206and the first gate electrode layer208remain on the sidewalls of the trench202.

Referring to the schematic cross-sectional view illustrated inFIG. 2F, a second gate electrode layer209is formed on the first gate electrode layer208, at a surface250of the semiconductor body204and at a bottom side of the trench202adjoining the n-type region232. For example, the second gate electrode layer209may be formed of undoped or slightly doped polysilicon having a thickness in a range of 10 nm to 1000 nm, in one embodiment 50 nm to 100 nm, for example. However, another polycrystalline or amorphous semiconductor material may be used as a material for the second gate electrode layer209. Thus, a gate electrode structure210including the first gate electrode layer208and the second gate electrode layer209is formed. The gate electrode structure210is electrically coupled to the drain zone222over the diode233being an element including a voltage blocking capability configured to prevent a current flow from the electrode structure210to the drain zone222in an on-state of the finalized device. When forming the first and the second gate electrode layers208,209, these layers may be undoped or slightly doped having a dopant concentration of less than 1015cm−3or even less than 1014cm−3, for example.

Referring to the cross-sectional view illustrated inFIG. 2G, a first dielectric layer213such as an oxide layer is formed on the second gate electrode layer209. The first dielectric layer213may have a thickness within a range of several tens to several hundreds of nanometers, e.g., 50 nm to 300 nm. On the first dielectric layer213, a second dielectric layer214, e.g., a doped silicon glass such as BPSG or PSG is formed. A reflow of the second dielectric layer214may follow to fill up the trench202. A void217may remain within the second dielectric layer214after carrying out the reflow. The first and second dielectric layers213,214constituting dielectric structure215are removed from a surface250of the semiconductor body204by a method such as etching. The dielectric layer214may also be replaced by a non-dielectric trench filling material such as polysilicon.

Referring also to the schematic cross-sectional view illustrated inFIG. 2H, dopants are introduced into a portion208′ and a portion209′ of the gate electrode structure.

Propagation of dopants along the sidewalls of the trench202may be controlled by adjusting time and temperature of a diffusion process of these dopants. A depth d of portions208′,209′ from the surface250of the semiconductor body204may be chosen such that it coincides with a depth of a body region which has been previously formed or which may be formed in later processes, for example.

Within the trench202, a drift control zone including gate insulating structure206, gate electrode structure210and dielectric structure215is formed.

Further elements required to finalize device100,200such as a source zone, a body region, and further semiconductor regions may be formed prior, after, in between or together with processes described above. For example, when introducing dopants into regions231,232, these dopants may be introduced in further areas of semiconductor body204, e.g., by a suitable mask, to form additional semiconductor regions, e.g., a source zone or body region.

The embodiments described above with regard toFIGS. 1 and 2provide beneficial effects such as a low interface charge at the interface between the drift zone and the gate insulating structure when using a thermal oxide for the gate insulating structure similar to known MOS processes. Furthermore, alkaline ions may be gettered within a BPSG layer of the dielectric layer filling in the trench. These effects account for improving the device reliability.

A leakage current of the drift control zone may be reduced by minimizing the thickness of the gate electrode structure to a value in a range of 5 to 30 nm, in one embodiment 10 to 20 nm. The gate electrode structure may also be formed by deposition of amorphous silicon and annealing, whereas the annealing may be a rapid thermal annealing or laser annealing, for example. The leakage current within the drift control zone may also be reduced by annealing the gate electrode structure in a hydrogen ambient at high temperatures such as 1000° C. to 1100° C. leading to large silicon grains of a gate electrode structure made of silicon. These grains may have a diameter of several micrometers, for example.