Interconnect substrate, semiconductor device, methods of fabricating, inspecting, and mounting the semiconductor device, circuit board, and electronic instrument

A semiconductor device including a substrate (10). An interconnect pattern (12) is formed over the substrate (10), and the substrate (10) has a first portion (14) and a second portion (16) to be superposed on the first portion (14). The first portion (14) has edges (22), (24), (26) and (28) as positioning references. The second portion (16) has a shape to be superposed over the first portion (14) except the edges (22), (24), (26) and (28).

TECHNICAL FIELD

The present invention relates to an interconnect substrate, a semiconductor device, methods of fabricating, inspecting, and mounting the semiconductor device, a circuit board, and an electronic instrument.

BACKGROUND ART

Packages having a structure in which a first portion of a substrate equipped with a semiconductor chip is bent and bonded to a second portion of the substrate provided with external terminals, or in which a first substrate equipped with a semiconductor chip is bonded to a second substrate provided with the external terminals have been developed. Since these packages enable the area of the substrate to be increased while reducing the planar size, the degree of freedom relating to the design of the interconnect pattern increases. Therefore, a stacked structure in which a number of semiconductor chips are superposed one on top of the other can be easily formed.

However, it is difficult to bend and superpose a substrate accurately at a desired position. It is also difficult to bond a plurality of substrates at a precise position. The package shapes may differ from each other since part of a substrate projects from a portion having external terminals when bending and superposing a substrate. In such a case, relative positions of package outline and external terminals may differ from each other, so that the positioning of external terminals with reference to the package outline.

DISCLOSURE OF THE INVENTION

The present invention has been achieved to solve this problem. An objective of the present invention is to provide an interconnect substrate enabling easy positioning, a semiconductor device, methods of fabricating, inspecting, and mounting the semiconductor device, a circuit board, and an electronic instrument.

(1) According to the present invention, there is provided an interconnect substrate over which an interconnect pattern is formed, comprising:a first portion; anda second portion to be superposed on the first portion,wherein the first portion has an end part as a positioning reference; andwherein the second portion has a shape so as to be superposed on the first portion except the end part.

Note that the superposed second portion is not always in contact with the first portion. According to the present invention, the second portion has a shape so as to be superposed on the first portion except the end part which is a positioning reference. Therefore, if the second portion is superposed on the first portion, the interconnect substrate can be positioned by using the end part of the first portion as the positioning reference.

(2) In this interconnect substrate, the end part as the positioning reference may include two edges which are perpendicular to each other.

This enables to determine positions by using these two edges.

(3) In this interconnect substrate, the first portion may comprise a rectangular body section and a projected section which extends from at least one edge of the body section and includes the end part.

This enables to determine positions by using the projected section or the two edges of the projected section.

(4) In this interconnect substrate, the projected section may be a region determined by:an edge which is a boundary between the projected section and the body section;a first edge which is perpendicular to the edge as a boundary; anda second top edge which is parallel to the edge as a boundary,wherein the end part as a positioning reference may include the first and second edges.

(5) In this interconnect substrate, the body section of the first portion may include an edge having no projected section; and the second portion may be disposed adjacent to the edge having no projected section.

(6) In this interconnect substrate, the second portion may have a depressed section facing the projected section of the first portion.

(7) In this interconnect substrate, the first portion may have a plurality of the end parts as positioning references; and at least one of the end parts may be formed from an area in the body section other than an area from which the projected section extends.

(8) In this interconnect substrate, the first portion may be larger than the second portion; and the two edges which are perpendicular to each other may form a corner section of the first portion.

(9) In this interconnect substrate, the first portion may have a depressed end part including the two edges which are perpendicular to each other and have an right angle.

(10) In this interconnect substrate, a plurality of holes may be formed in the end parts.

(11) In this interconnect substrate, the second portion may continuously extend from the first portion.

(12) In this interconnect substrate, the second portion may be separated from the first portion; and the first and second portions may be connected by the interconnect pattern.

Since the first and second portions are separated, the substrate can be easily bent or folded in the region between the first and second portions.

(13) According to the present invention, there is provided a semiconductor device comprising: at least one semiconductor chip; anda substrate which has a first portion and a second portion to be superposed on the first portion, and on which the semiconductor chip is mounted,wherein the first portion includes an end part as a positioning reference; andwherein the second portion has a shape which avoids being superposed on the end part of the first portion.

Note that the superposed second portion is not always in contact with the first portion. According to the present invention, the second portion has a shape which avoids being superposed on the end part as a positioning reference. Therefore, if the second portion is superposed on the first portion, the interconnect substrate can be positioned by using the end part of the first portion as the positioning reference.

(14) In this semiconductor device, a plurality of external terminals may be provided in the first portion.

According to this configuration, the relative positions between the end part as a positioning reference in the first portion and the external terminals are fixed, therefore the positioning of the external terminals can be easily done by using the end part as a positioning reference. If the electrical characteristics of the semiconductor device are inspected, it is sufficient to put the semiconductor device into a socket. Moreover, rate of defectives due to mispositioning of the external terminals can be reduced when mounting the semiconductor device on a circuit board.

(15) In this semiconductor device, the interconnect substrate may be used as the substrate.

(16) Over a circuit board according to the present invention the above-described semiconductor device is mounted.

(17) An electronic instrument according to the present invention is provided with the above-described semiconductor device.

(18) According to the present invention, there is provided a method of fabricating a semiconductor device, comprising the steps of:mounting at least one semiconductor chip over the interconnect substrate as defined in any one of claims1to10; andsuperposing the second portion on the first portion of the interconnect substrate.

Note that the superposed second portion is not always in contact with the first portion. According to the present invention, the second portion has a shape to be superposed on the first portion except the end part as the positioning reference. According to the semiconductor device obtained in this manner, if the second portion is superposed on the first portion, the positioning of the interconnect substrate can be done by using the end part of the first portion as the positioning reference.

(19) According to the present invention, there is provided a method of inspecting a semiconductor device comprising the steps of:positioning the above-described semiconductor device by using a plurality of end parts as positioning references; andinspecting electrical characteristics of the semiconductor device.

According to the present invention, the positioning and inspection can be done by using the end parts of the first portion as the positioning reference.

(20) According to the present invention, there is provided a method of mounting a semiconductor device, comprising the steps of:positioning the above-described semiconductor device by using a plurality of end parts as positioning references; andmounting the semiconductor device on a circuit board.

According to the present invention, the positioning for the mounting can be easily done by using the end parts of the first portion as the positioning references.

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment

FIG. 1is a view illustrating a method of fabricating a semiconductor device according to a first embodiment to which the present invention is applied.FIG. 2is a view illustrating a semiconductor device according to the present embodiment and a method for inspecting or mounting the semiconductor device.FIG. 3is a view showing a circuit board equipped with the semiconductor device according to the present embodiment.

Substrate

A substrate10shown inFIG. 1is used in the semiconductor device according to the present embodiment. The substrate10is used as an interposer for mounting at least one (plurality inFIG. 1) of semiconductor chips40and42. The material for the substrate10may be any organic or inorganic material or a composite structure of these materials. As examples of the substrate10formed using an organic material, a two-layer or three-layer flexible substrate formed of a polyimide resin and the like can be given. It is preferable to use a flexible substrate in the case of bending the substrate10. As the flexible substrate, a substrate called an FPC (Flexible Printed Circuit), a substrate called a glass epoxy tape, or a tape substrate used in TAB (Tape Automated Bonding) technology may be used. As examples of the substrate10formed using an inorganic material, a ceramic substrate, a glass substrate, and the like can be given. As examples of a substrate formed of a composite structure of organic and inorganic materials, a glass epoxy substrate and the like can be given. These substrates may be multilayer substrates or built-up substrates.

An interconnect pattern12is formed on one edge of the substrate10. The interconnect pattern12may be formed using a conductive material such as copper. The interconnect pattern12is preferably plated with solder, tin, gold, nickel, or a composite material of these. The substrate10with the interconnect pattern12formed thereon may be called an interconnect substrate.

The interconnect pattern12may be bonded to the substrate10through an adhesive (not shown), thereby forming a three-layer substrate. The interconnect pattern12may be formed on the substrate10without using an adhesive, thereby forming a two-layer substrate. The interconnect pattern12is preferably covered with a protective layer such as resist (not shown) in the area excluding the electrical connections such as land sections.

The substrate10includes a first portion14and a second portion16. The second portion16is superposed on the first portion14, as shown in FIG.2. Specifically, the second portion16is superposed on the first portion14by bending or folding the substrate10in the region between the first and second portions14and16. The first and second portions14and16may be separated but connected by the interconnect pattern12. An example of the latter case is described in the next embodiment. Although the first and second portions14and16come into contact with each other and have an overlapping section, these portions may not be in contact with each other.

The first portion14includes a rectangular body section17and at least one (plurality inFIG. 1) projected section18. The projected sections18are formed so as to extend from the edge of the body section17. In the example shown inFIG. 1, the projected sections18are formed so as to extend from one edge (virtual edge) of the rectangular body section17in a direction perpendicular thereto. However, the projected sections18may be formed so as to extend in a direction other than the perpendicular. InFIG. 1, assuming that the region of the first portion14continuously formed with the second portion16with the same width is the body section17, the projected sections18are formed on the two parallel edges (top and bottom edges inFIG. 1) of the rectangular body section17. A projected section20is formed from the region consisting of the two projected sections18and the body section17in a direction opposite to the second portion16.

The projected sections18have a top edge22parallel to one edge of the body section17and edges24extending from the edge of the body section17in a direction perpendicular thereto. Specifically, the edges22and24are perpendicular to each other. The projected section20has an edge26parallel to one edge of the body section17and edges28extending from the edge of the body section17in a direction perpendicular thereto. The edges26and28are perpendicular to each other. Lines extending from the edge22of the projected section18and the edge26of the projected section20are perpendicular to each other.

The edge24of the projected section18and the edge28of the projected section20form a concave end part30. The angle formed by the edge24and the edge28is a right angle.

The end part including the edges22and24of the projected section18, the end part including the edges26and28of the projected section20, the end part including the edges24and28of the projected sections18and20, or the end part including the edges22and26of the projected sections18and20becomes a positioning reference. Specifically, among the two edges22and24perpendicular to each other, the two edges26and28perpendicular to each other, the two edges24and28perpendicular to each other, and the two edges22and26perpendicular to each other, at least one pair of two edges becomes the positioning reference.

Since relative positions of the positioning references and the external terminals are fixed, the accurate position of the external terminals can be easily determined from the outline of the substrate including the positioning references when inspecting or mounting the semiconductor device described later.

A plurality of external terminals44is provided on the first portion14. At least one semiconductor chip42may be mounted on the first portion14. The mounting type of the semiconductor chip42is described later in the description of the semiconductor device.

The second portion16is shaped so as to be superposed on the first portion14in the area other than the above-described end parts which become the positioning references. In the example shown inFIG. 1, the second portion16has a shape similar to that of the region of the first portion14excluding the projected sections18and20. Since the second portion16has such a shape, the second portion16does not overlap the end parts of the first portion14which become the positioning references when superposing the second portion16on the first portion14, as shown in FIG.2.

The second portion16is disposed adjacent to the body section17which is defined in the description of the projected sections18of the first portion14in the area other than the projected sections18. In the example shown inFIG. 1, the second portion16is continuously and integrally formed with the first portion14. A slit (not shown) may be formed between the first and second portions14and16. The substrate10can be easily bent or folded in the region between the first and second portions14and16by forming a slit.

At least one semiconductor chip40is mounted on the second portion16. The mounting type of the semiconductor chip40is described later in the description of the semiconductor device.

Note that the above-described body section17is only an example and the definition of the body section is not limited thereto. InFIG. 1, assuming that the region of the first portion14continuously formed with the second portion16with the same width (region including the projected section20) is the body section, the projected sections18are formed on two parallel edges (top and bottom edges inFIG. 1) of the body section. Assuming that the region including the two projected sections18and the region connecting these projected sections18with the same width as the projected sections18is the body section, the projected section20is formed on the body section in a direction opposite to the second portion16. In both cases, each of the projected sections18and20extends from one edge of the rectangular body section so as to have a width smaller than the length of the edge (virtual edge) of the body section.

The body section may be referred to as a rectangular section surrounded by the projected sections18and20(body section17, for example) irrespective of the width of the second portion16.

Fabrication Method for Semiconductor Device

In the method of fabricating the semiconductor device according to the present embodiment, at least one of the semiconductor chips40and42is mounted on the substrate10. For example, the semiconductor chip42is mounted on the first portion14of the substrate10and the semiconductor chip40is mounted on the second portion16. This step is carried out while allowing the substrate10to extend without bending.

The second portion16is then superposed on the first portion14. For example, the second portion16is superposed on the first portion14by bending or folding the substrate10in the region between the first and second portions14and16.

The method may include a step of providing a plurality of external terminals44(see FIG.3). For example, the external terminals44are formed through through-holes11formed in the substrate10so as to project from the edge of the substrate opposite to the edge on which the interconnect pattern12is formed. The external terminals44may be formed using solder or the like. Balls may be formed due to surface tension by melting solder provided in the through-holes11. The through-holes11may be filled with a conductive material and solder balls may be placed on the conductive material. In addition, the inner surface of the through-holes11may be plated.

In this case, the positions of the through-holes11correspond to the positions at which the external terminals are formed. Therefore, the positioning references of the substrate and the positions for the external terminals can be determined more accurately by stamping the positioning references and the through-holes11in the same step using a die when fabricating the substrate. In the case where the positioning references and the through-holes11cannot be formed in the same step, positioning reference holes may be simultaneously formed with the through-holes11, and the positioning references of the substrate may be formed based on the positioning reference holes.

Semiconductor Device

FIG. 3is a view showing the semiconductor device according to the present embodiment. The semiconductor device includes the substrate10and at least one of the semiconductor chips40and42. The substrate10is the same as described above.

A plurality of through-holes11is formed in the substrate10. The through-holes11are used to connect a plurality of external terminals44to the interconnect pattern12. The external terminals44projecting from the edge of the substrate10opposite to the edge on which the interconnect pattern12is formed can be electrically connected to the interconnect pattern12through the through-holes11. For example, in the case where the interconnect pattern12extends over the through-holes11, the external terminals44can be provided on the interconnect pattern12through the through-holes11.

The external terminals44are formed using solder or the like. Balls may be formed due to surface tension by melting solder with which the through-holes11are filled. Solder balls may be placed on a conductive material provided in the through-holes11. The inner surfaces of the through-holes11may be plated.

The interconnect pattern12formed to extend over the through-holes11may be bent into the through-holes11and used as an external terminal. For example, part of the interconnect pattern12may be pushed into the through-holes11using a die or the like, thereby causing the interconnect pattern12to project as an external terminal from the edge of the substrate10opposite to the edge on which the interconnect pattern12is formed. Instead of positively forming the external terminals, the external terminals may be formed using solder cream applied to a motherboard when mounting the semiconductor device on the motherboard due to surface tension during melting. This semiconductor device is a land grid array semiconductor device in which land sections for forming the external terminals are formed on the edge to be mounted on a circuit board.

The semiconductor chips40and42are stacked by bending the substrate10, as shown in FIG.3. This enables the semiconductor device to be miniaturized. It is preferable that the semiconductor chips40and42be bonded using an adhesive46or the like or secured by a mechanical method.

In the present embodiment, the semiconductor chips40and42are bonded to the interconnect pattern12by using an anisotropic conductive film32. The mounting type of the semiconductor chip40is not particularly limited. In the case of applying face down bonding, the semiconductor chip40is mounted on the interconnect pattern12. Electrodes (preferably bumps) of the semiconductor chip40are bonded to the interconnect pattern12. The electrodes may be bonded using an anisotropic conductive adhesive or conductive resin paste (resin containing silver paste) other than the anisotropic conductive film32. The electrodes (preferably bumps) may be bonded to the interconnect pattern12by using a metal junction such as Au—Au, Au—Sn, or solder, or the shrinkage force of an insulating resin. Face up mounting using wire bonding or TAB mounting technique by connecting fingers may also be applied.

Part of the interconnect pattern12formed on the first portion14and part of the pattern formed on the second portion16may be mirror-symmetrical or have the same shape. This enables design data and a mask used when forming the interconnect pattern12on the substrate10to be commonly used, thereby reducing the initial cost for fabricating the interconnect substrate.

In the present embodiment, the substrate10is bent, with the edge on which the semiconductor chips40and42are mounted being the inner edge. The substrate10is bent in the area between the two semiconductor chips40and42. As shown inFIG. 2, the second portion16is superposed on the first portion14of the substrate10so as not to overlap the projected sections18and20. Therefore, the semiconductor device can be easily positioned by utilizing at least two edges which are perpendicular to each other among the edges22,24,26, and28of the projected sections18and20.

In the case where the interconnect pattern12is partly mirror-symmetrical on the first and second portions14and16, the semiconductor chips40and42may have a mirror-symmetrical circuit structure. In the case where the interconnect pattern12partly has the same shape on the first and second portions14and16, the semiconductor chips40and42may have the same circuit structure.

In the case where the semiconductor chips40and42have a mirror-symmetrical circuit structure or the same circuit structure, each element can be electrically connected from the same external terminals44. In the case where the semiconductor chips40and42are memories, address terminals and data terminals are easily shared using the same external terminal44.

For example, in the case where the semiconductor chips40and42are memories, information can be read out from or written into memory cells of each memory at the same address from the same external terminal44. A plurality of (two, for example) semiconductor chips can be separately controlled using the same external terminal arrangement by separating the semiconductor chips40and42merely by the connection of a chip-select terminal.

According to the present embodiment, a semiconductor device with a stacked structure can be fabricated using a cheap single-edged substrate, whereby cost can be reduced. The description given in the present embodiment may be applied to other embodiments to a large extent.

In the present embodiment, a semiconductor device having external terminals is described. Part of the substrate may be extended and the external connection may be established therefrom. Part of the substrate may be used as leads for connectors, or connectors may be mounted on the substrate. In addition, the interconnect pattern of the substrate may be connected to other electronic instruments.

Inspecting Method for Semiconductor Device

FIG. 2is a view illustrating a method of inspecting the semiconductor device according to the present embodiment. The semiconductor device according to the present embodiment is designed so as to be positioned by utilizing the projected sections18and20of the first portion14of the substrate10, as described above. Therefore, the electrical characteristics of the semiconductor device can be easily inspected by putting the semiconductor device into a socket (not shown).

In the example shown inFIG. 2, the socket (not shown) has guides50,52, and54. The guides50and52engage with the projected sections18, and the guide54engages with the projected section20. The socket may have pins56in addition to or in place of the guides50,52, and54. The pins56come in contact with the two depressed sections30formed by the projected section20and the projected sections18(formed by the edges24and28which are perpendicular to each other).

The positioning of the semiconductor device1can be easily carried out by allowing two edges which are perpendicular to each other among the edges22,24,26, and28of the projected sections18and20to engage with at least one of the guides50,52, and54or the pair of pins56. The guides50,52, and54need not be concave as shown inFIG. 2insofar as the guides can secure at least two edges. As shown inFIG. 2, at least two pins56may be used as the guides. Since the area for establishing electrical connection with the inedge of the semiconductor device1such as the external terminals44and the position of a probe or socket can be determined in this manner, the semiconductor device1can be inspected using the probe or socket.

Mounting Method for Semiconductor Device and Circuit Board

FIG. 3is a view showing a circuit board equipped with the semiconductor device according to the present embodiment. InFIG. 3, the semiconductor device1is mounted on a circuit board2. A glass epoxy substrate or the like is generally used as the circuit board2. Interconnect pattern3is formed on the circuit board2by using copper or the like so as to form a desired circuit. Electrical conductivity between the semiconductor device1and the circuit board2is established by connecting the interconnect pattern3to the external terminals of the semiconductor device1.

The semiconductor device1can be easily positioned in the same manner as described for the inspecting method for the semiconductor device. Therefore, a portion for establishing electrical connection such as the external terminals44can be bonded to the interconnect pattern3of the circuit board2with high accuracy, whereby the occurrence of failure due to mispositioning can be reduced. Specifically, relative positions between the components (including the external terminals44) and the above-described positioning structure in a plan view is accurately determined, the external terminals44can be accurately bonded to the interconnect pattern3by making a mounting device for the semiconductor device such as a chip mounter recognize the positioning structure.

The present invention is not limited to the above embodiment and various modifications are possible. Other embodiments are described below.

Second Embodiment

FIG. 4is a view illustrating a method of fabricating a semiconductor device according to a second embodiment to which the present invention is applied.FIG. 5is a view illustrating a semiconductor device according to the present embodiment and a method for inspecting or mounting the semiconductor device.FIG. 6is a view illustrating a method of fabricating a semiconductor device according to a modification example of the present embodiment.

In the present embodiment, a substrate60shown inFIG. 4is used. Interconnect pattern62is formed on the substrate60. The substrate60has first and second portions64and66. The first and second portions64and66are formed separately but connected by the interconnect pattern62. The interconnect pattern62is preferably insulated by applying flexible resist thereon.

The first portion64has a projected section68which extends from one edge (virtual edge) of a rectangular body section in a direction perpendicular thereto and has a width smaller than the length of the edge of the body section. An edge72at the top of the projected section68and an edge74extending in a direction perpendicular to the edge of the body section intersect at right angles. Therefore, the positioning of the external terminals80and other components such as an inspection device or interconnect pattern3(seeFIG. 3) can be easily done at the time of inspecting or mounting the semiconductor device by using the projected section68, specifically, the edges72and74of the projected section68perpendicular to each other. A plurality of end parts which form the edges72and74becomes positioning references.

The second portion66has a depressed section70with a shape avoiding the projected section68of the first portion64. The depressed section70is disposed so as to face the projected section68. Specifically, the projected section68is disposed inedge the depressed section70. Therefore, the second portion66is shaped so as to be superposed on the first portion64in the area other than the end parts (end part which forms the edges72and74or projected section68) which become the positioning references. Not only the first portion64but also the second portion66may be used as the positioning references.

The description of the substrate10in the first embodiment is applicable to other structures of the substrate60.

In the method of fabricating the semiconductor device according to the present embodiment, at least one of semiconductor chips76and78is mounted on the substrate60. For example, the semiconductor chip78is mounted on the first portion64of the substrate60and the semiconductor chip76is mounted on the second portion66. This step is carried out while allowing the substrate60to extend without bending.

The second portion66is then superposed on the first portion64. In the present embodiment, since the first and second portions64and66are separated, the second portion66is superposed on the first portion64by bending or folding the interconnect pattern62.

The method may include a step of providing a plurality of external terminals80. The description of the external terminals44in the first embodiment is applicable to the details of the external terminals80.

According to the semiconductor device fabricated in this manner, the projected section68is formed on the first portion64and the second portion66is superposed on the first portion64in the area other than the projected section68, as shown in FIG.5. Therefore, the semiconductor device can be easily positioned using the projected section68. For example, the semiconductor device can be positioned by allowing a guide82to engage with the projected section68. The description in the first embodiment is applicable to the details therefor.

According to the present embodiment, since the semiconductor device can be easily positioned, the inspecting and mounting steps of the semiconductor device can be performed with high accuracy. The description in the first embodiment is applicable to the details thereof.

As a modification example of the present embodiment, the first portion64may have at least one end part for the positioning reference, the one end part extending from an area in the rectangular body section other than an area from which the projected section68extends. Specifically, the first portion64has a plurality of end parts which become the positioning references, wherein at least one end part is formed by the projected section68and at least one other end part is formed from the area other than the area from which the projected section68is formed. In the example shown inFIG. 6, the end part for the positioning reference, which is formed from the area other than the area from which the projected section68is formed, is formed by edges82and84which form the outline of the first portion64. The edges82and84extend so as to be perpendicular to each other.

As indicated by the dash-double-dotted line shown inFIG. 6, the first portion64may be shaped so that all edges of the body section except for the projected section68(three edges) are located outedge the second portion66when superposing the second portion66. The first portion64may be shaped so that two adjacent edges of the body section except for the projected section68are present outedge the second portion66. This enables the position of the semiconductor device to be recognized two-dimensionally with ease when inspecting or mounting the semiconductor device using at least two adjacent edges of the first portion64as the references.

The semiconductor device may be positioned by allowing the end part to engage with a guide such as a socket, or by recognizing the edges82and84of the first portion64as images using a camera or the like. The positioning of the semiconductor device by image recognition is applicable to other embodiments. Positioning accuracy of the semiconductor device may be further improved by using the end part including the edges82and84which are perpendicular to each other, and using a plurality of end parts or the projected section68including the edges72and74.

Third Embodiment

FIG. 7is a view showing a semiconductor device according to a third embodiment to which the present invention is applied. This semiconductor device includes a substrate90having first and second portions92and94. The first and second portions92and94are stacked. The first and second portions92and94may be formed either continuously and integrally or separately. The details thereof are described in the first and second embodiments. At least one semiconductor chip (not shown) is provided between the first and second portions92and94. External terminals (not shown) may be provided on the first portion92.

In the present embodiment, a plurality of holes96is formed on the first portion92. A plurality of end parts for forming the holes96becomes the positioning references of the semiconductor device. Specifically, the semiconductor device can be easily positioned by inserting pins or the like into the holes96.

The second portion94is designed so that the second portion94is superposed on the first portion92in the area other than the holes96on the first portion92(or end parts for forming the holes). In the example shown inFIG. 7, notches are formed on the second portion94corresponding to the regions of the first portion92in which the holes96are formed.

In the present embodiment, since the semiconductor device has a plurality of end parts (end parts in which the holes96are formed) which become the positioning references, the external terminals (not shown) can be accurately inspected using the inspection device, or mounted on the interconnect pattern3(seeFIG. 3) using the end parts at the time of inspecting or mounting the semiconductor device. If sections (corner of the substrate, projected section, depressed section, and the like) which can be distinguished from their appearance are formed on the first portion92instead of the holes96, these sections can be used as the positioning references.

Fourth Embodiment

FIG. 8is a view showing a semiconductor device according to a fourth embodiment to which the present invention is applied. This semiconductor device includes a substrate100having first and second portions102and104. The first and second portions102and104are stacked. The first and second portions102and104may be continuously and integrally formed. In the example shown inFIG. 8, the first and second portions102and104are separated but connected by the interconnect pattern106. The details thereof are described in the first and second embodiments. At least one semiconductor chip (not shown) is provided between the first and second portions102and104. External terminals (not shown) may be provided on the first portion102.

In the present embodiment, the first portion102is larger than the second portion104. Two edges108and110among the edges which forms the outline of the first portion102extend to be perpendicular to each other. The edges108and110which are perpendicular to each other may form a corner section of the first portion102. End parts including the edges108and110which are perpendicular to each other function as the positioning references for the semiconductor device by engaging the end parts with a guide112such as a socket.

Since the second portion104is smaller than the first portion102, the second portion104is shaped so as to be superposed on the first portion102in the area other than the end parts which become the positioning references.

According to the present embodiment, the external terminals (not shown) can be accurately inspected using the inspection device or mounted on the interconnect pattern3(seeFIG. 3) when inspecting or mounting the semiconductor device by using the edges108and110which are perpendicular to each other among the edges which forms the outline of the first portion102or by using end parts including these edges.

In the present embodiment, the first portion described in the second embodiment may be formed and used as the positioning structure.

Fifth Embodiment

FIG. 9is a view showing a semiconductor device according to a fifth embodiment to which the present invention is applied. In the above embodiments, the substrate having the first and second portions are described. The substrate may have a third portion and other portions. A substrate120used in the semiconductor device according to the present embodiment includes first to third portions122,124, and126. The description given in the above embodiments is applicable to the first and second portions122and124. Semiconductor chips130and132are mounted on the first and second portions122and124. In this case, at least one of the semiconductor chips130and132is mounted in at least either the first portion122or the second portion124.

In the example shown inFIG. 9, the third portion126of the substrate120extends from the second portion124. The third portion126may extend from the first portion122. The third portion126is shape so as to be superposed on the first portion122in the area other than the end parts of the first portion122which become the positioning references in the same manner as the second portion124. Specifically, the third portion126has the same structure as the second portion124. The description given in the above embodiments is applicable to the structure of the first and second portions122and124. The description given in the above embodiments is applicable to the structure of the external terminals44and the like.

According to the present embodiment, in addition to the effects described in the above embodiments, a semiconductor device equipped with an increased number of semiconductor chips can be fabricated.

FIG. 10shows a notebook-type personal computer200and a portable telephone300as examples of an electronic instrument equipped with the semiconductor device to which the present invention is applied.

In the above-described embodiments, a built-up substrate or a multi-layer substrate may be used as the substrate insofar as the total cost does not increase.

Note that the “semiconductor chip” that is a structural component of the present invention could be replaced by an “electronic element,” and electronic elements (either active elements or passive elements) can be mounted on a substrate to fabricate an electronic component, in a manner similar to that of semiconductor chips. Examples of electronic components fabricated by using such electronic elements include optical elements, resistors, capacitors, coils, oscillators, filters, temperature sensors, thermistors, varistors, variable resistors, or fuses, by way of example.

All of the above-described embodiments may be applied to a semiconductor device (or mounted module) in which semiconductor chips and other electronic elements are mounted on a substrate in combination.

In the above-described embodiments, an example in which the substrate is layered by bending the substrate is described. The present invention is not limited to this and is applicable to all methods for layering the substrates. In the case of layering the substrates, upper and lower substrates may be electrically connected using bumps or connectors. In this case, the above-described positioning structure may be formed only on the substrate on which the external terminals are formed (lower substrate) or the substrate layered on the lower substrate. The present invention may be applied to all embodiments other than the case of bending the substrate.