Solid-state imaging device, control method thereof, and electronic apparatus

An imaging device includes a plurality of pixels including a first pixel and a second pixel, and a differential amplifier including a first amplification transistor, a second amplification transistor, and a first load transistor. The first load transistor receives a power source voltage. The imaging device includes a first signal line coupled to the first amplification transistor and the first load transistor, a second signal line coupled to the second amplification transistor, and a first reset transistor configured to receive the power source voltage. A gate of the first reset transistor is coupled to the first load transistor. The first pixel includes a first photoelectric conversion element and the first amplification transistor, and the second pixel includes a second photoelectric conversion element and the second amplification transistor.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a national stage application under 35 U.S.C. 371 and claims the benefit of PCT Application No. PCT/JP2017/037475 having an international filing date of 17 Oct. 2017, which designated the United States, which PCT application claimed the benefit of Japanese Patent Application No. 2016-209290 filed 26 Oct. 2016, the entire disclosures of each of which are incorporated herein by reference.

TECHNICAL FIELD

The present technology relates to a solid-state imaging device, a control method thereof, and an electronic apparatus and more particularly to a solid-state imaging device capable of adjusting an operation range of a differential amplifier within an optimal operation range, a control method thereof, and an electronic apparatus.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the benefit of Japanese Priority Patent Application JP 2016-209290 filed on Oct. 26, 2016, the entire contents of which are incorporated herein by reference.

BACKGROUND ART

A solid-state imaging device has, for example, a configuration in which a photodiode (PD) corresponding to a photoelectric conversion element, four pixel transistors including a transfer transistor, a reset transistor, an amplification transistor, and a selection transistor, and a floating diffusion (FD) are disposed at each pixel. In each pixel, a signal charge which is photoelectrically converted by the PD is transferred to the FD, is converted into voltage information and is amplified by the amplification transistor, and is output to the AD conversion unit. The AD conversion unit realizes an AD conversion by comparing a voltage of an input analog pixel signal with a voltage of a reference signal having a slope shape with a constant inclination in the direction of time and counting a time until an output of a comparison result is inverted.

Hitherto, a source follower circuit has been widely used to amplify the pixel signal using the amplification transistor, but a differential amplifier having a large amplification ratio is also proposed (for example, see Patent Literatures 1 and 2). If the amplification rate is large, there is an effect that an input-referred noise generated in the AD conversion unit at the subsequent stage becomes small.

For example, in a case where a source follower circuit is used, it is assumed that the conversion efficiency of the pixel is 100 μV/e- (the output amplitude of the amplification transistor is 100 μV in a case of the input of electron of 1 e- by the PD), the noise of the output unit of the amplification transistor is 100 μVrms (1e-rms), and the noise of the AD conversion unit is 100 μV (1e-rms). Since the total noise at this time is represented by the square sum of √(100 μVrms2+100 μVrms2)=141 μVrms, the input-referred noise is 1.41 e-rms.

Meanwhile, in a case where the differential amplifier is used, it is assumed that the conversion efficiency of the pixel is 500 μV/e-, the noise of the output unit of the amplification transistor is 500 μVrms (1e-rms), and the noise of the AD conversion unit is 100 μVrms (0.2e-rms). Since the total noise at this time is represented by the square sum of √(500 μVrms2+100 μVrms2)=510 μVrms, the input-referred noise is 1.02 e-rms.

Thus, since the input-referred noise of the AD conversion unit becomes smaller as the conversion efficiency of the pixel becomes higher, a noise reduction effect is exhibited.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

Since the output signal of the differential amplifier changes in accordance with the amount of light incident to the PD, parameters such as a parasitic capacitance Cgd between the gate and the drain (G-D) of the signal side amplification transistor or a small signal output resistance ro of the PMOS change. Since the gain of the differential amplifier depends on the parasitic capacitance Cgd of G-D of the amplification transistor or the small signal output resistance ro, the gain eventually changes in accordance with the amount of light incident to the PD. The magnitude of variation also changes within the operation range of the differential amplifier. There is an optimal operation range in which the gain is large and the gain variation is small in the operation range of the differential amplifier and the operation range of the differential amplifier is determined by the operation point immediately after resetting.

However, there is a case where the control of the operation point may be difficult immediately after the reset of the differential amplifier and the differential amplifier may be separated from the optimal operation range. As a result, the conversion efficiency of pixels decreases and the linearity deteriorates.

The present technology is made in view of such circumstances and is to adjust an operation range of a differential amplifier to an optimal operation range.

Solution to Problem

According to a first aspect of the present technology, provided is an imaging device including: a plurality of pixels including a first pixel and a second pixel; a differential amplifier including a first amplification transistor, a second amplification transistor, and a first load transistor, the first load transistor being configured to receive a power source voltage; a first signal line coupled to the first amplification transistor and the first load transistor; a second signal line coupled to the second amplification transistor; and a first reset transistor configured to receive the power source voltage, a gate of the first reset transistor being coupled to the first load transistor. The first pixel includes a first photoelectric conversion element and the first amplification transistor, and the second pixel includes a second photoelectric conversion element and the second amplification transistor.

According to a second aspect of the present technology, provided is an imaging device including: a first pixel including a first photoelectric conversion element, a first transfer transistor, and a first amplification transistor; a second pixel including a second photoelectric conversion element, a second transfer transistor, and a second amplification transistor; a first signal line coupled to the first amplification transistor; a second signal line coupled to the second amplification transistor; a first load transistor coupled to the first signal line, the first load transistor being configured to receive a power source voltage; and a first reset transistor configured to receive the power source voltage, a gate of the first reset transistor being coupled to the first load transistor. One of a source and a drain of the first amplification transistor is coupled to one of a source and a drain of the second amplification transistor, and the other of the source and the drain of the first amplification transistor is coupled to the other of the source and the drain of the second amplification transistor.

According to a third aspect of the present technology, provided is an imaging device including: a differential amplifier including: a first load transistor coupled to a power source; a second load transistor coupled to the power source; a first amplification transistor of a first pixel; a second amplification transistor of a second pixel; a first signal line coupled to the first load transistor and the first amplification transistor; and a second signal line coupled to the second load transistor and the second amplification transistor, wherein outputs of the first and second amplification transistors are connected to one another; and a reset element coupled to the differential amplifier and to reset the first pixel with a first current on the first signal line and reset the second pixel on the second signal line with a second current during a reset operation.

In the first to third aspects of the present technology, the pixel array unit (or plurality of pixels) may be provided with the first and second unit pixels (or first and second pixels) each including the photoelectric conversion element configured to photoelectrically convert the light incident to the pixel, the transfer transistor configured to transfer the signal charge photoelectrically converted by the photoelectric conversion element to the FD, the reset transistor configured to reset the signal charge of the FD, the amplification transistor configured to convert the signal charge stored in the FD into a voltage signal and output the voltage signal, and the selection transistor configured to select the pixel and in the differential amplifier component constituting the differential amplifier along with the amplification transistors and the selection transistors of the first and second unit pixels, a difference in current flowing to each of the signal side and the reference side of the differential pair is generated.

The solid-state imaging device and the electronic apparatus may be independent devices or modules assembled to other devices.

Advantageous Effects of Invention

According to the first to third aspects of the present technology, the operation range of the differential amplifier can be adjusted to the optimal operation range.

Additionally, the effects described herein are not necessarily limited and may be any of the effects described in the present technology.

DESCRIPTION OF EMBODIMENTS

Hereinafter, a mode for carrying out the present technology (hereinafter, referred to as an embodiment) will be described. In addition, a description will be made according to the following procedure.

1. Schematic configuration of solid-state imaging device according to first embodiment

2. Configuration example of column signal processing unit

3. First configuration example of differential amplifier component

4. Second configuration example of differential amplifier component

5. Third configuration example of differential amplifier component

6. Fourth configuration example of differential amplifier component

7. Fifth configuration example of differential amplifier component

8. Sixth configuration example of differential amplifier component

9. Seventh configuration example of differential amplifier component

10. Eighth configuration example of differential amplifier component

11. Ninth configuration example of differential amplifier component

12. Tenth configuration example of differential amplifier component

13. Eleventh configuration example of differential amplifier component

14. Twelfth configuration example of differential amplifier component

15. Thirteenth configuration example of differential amplifier component

16. Fourteenth configuration example of differential amplifier component

17. Fifteenth configuration example of differential amplifier component

18. Schematic configuration of solid-state imaging device of second embodiment

19. Configuration example of signal switching unit

21. Application Example of Electronic Apparatus>

<1. Schematic configuration of solid-state imaging device of first embodiment>

FIG. 1is a diagram showing a schematic configuration of a solid-state imaging device (a CMOS image sensor) according to a first embodiment of the present technology.

A solid-state imaging device1ofFIG. 1includes a pixel array unit11, a differential amplifier component12, a vertical scanning circuit13, a column signal processing unit14, a horizontal scanning circuit15, and the like which are formed on, for example, a semiconductor substrate using Si (silicon) as a semiconductor.

The pixel array unit11is provided with a unit pixel10S and a dummy pixel10D. Specifically, the unit pixels10S are arranged in an array inside an effective pixel area of the pixel array unit11and one dummy pixel10D is disposed in at least one pixel column outside the effective pixel area. The unit pixel10S is a pixel which outputs a pixel signal corresponding to a light receiving amount and corresponding to an output of the solid-state imaging device1and the dummy pixel10D is a kind of the unit pixel10S, but is a pixel which detects a reference value of a black level and is formed on an optical black (OPB) area being light-shielded by a metal film or the like so that incident light does not enter a photoelectric conversion element.

A selection control signal SEL_S transferred via a selection signal line21, a reset control signal RST_S transferred via a reset signal line22, and a transfer control signal TRG_S transferred via a transfer signal line23are respectively supplied from the vertical scanning circuits13to the unit pixels10S.

A selection control signal SEL_D transferred via a selection signal line31, a reset control signal RST_D transferred via a reset signal line32, and a transfer control signal TRG_D transferred via a transfer signal line33are respectively supplied from the vertical scanning circuits13to the dummy pixels10D.

The unit pixel10S is connected to the differential amplifier component12via a column signal line41, a column reset line42, and a column Vcom line43. The dummy pixel10D is connected to the differential amplifier component12via a column signal line51, a column reset line52, and a column Vcom line43.

The differential amplifier component12constitutes a differential amplifier together with an amplification transistor104and a selection transistor105(FIG. 3) of the unit pixel10S and an amplification transistor114and a selection transistor115(FIG. 3) of the dummy pixel10D, amplifies a pixel signal corresponding to an output of the unit pixel10S, and outputs the pixel signal to the column signal processing unit14. The unit pixel10S is a signal side pixel which constitutes a differential pair of the differential amplifier component12and the dummy pixel10D is a reference side pixel which constitutes a differential pair. The pixel signal which is amplified by the differential amplifier is output to the column signal processing unit14via the column signal line41.

The vertical scanning circuit13includes a shift register or an address decoder and drives each unit pixel10S by the unit of row or the like by supplying the selection control signal SEL_S, the reset control signal RST_S, and the transfer control signal TRG_S to each unit pixel10S of the pixel array unit11and supplying the selection control signal SEL_D, the reset control signal RST_D, and the transfer control signal TRG_D to the dummy pixel10D.

For example, the vertical scanning circuit13performs an electronic shutter operation for sweeping out signals of the unit pixels10S of the row in the electronic shutter row and a reading operation for reading signals of the unit pixels10S of the row in the reading row while scanning the unit pixels10S of the pixel array unit11by the unit of row in the electronic shutter rows and the reading row in the vertical direction (the up and down direction).

Here, although not shown in the drawings, the vertical scanning circuit13includes a reading scanning system for performing a reading operation of reading the signals of the unit pixels10S in the reading row while sequentially selecting the unit pixels10S by the unit of row and an electronic shutter scanning system for performing an electronic shutter operation on the same row (the electronic shutter row) positioned just before by the amount of time corresponding to the shutter speed compared to the reading scanning by the reading scanning system.

Then, a period from a timing in which unnecessary signals charges of the photoelectric conversion unit are reset by the shutter scanning of the electronic shutter scanning system to a timing in which signals of the unit pixels10S are read by the reading scanning of the reading scanning system becomes an accumulation period (an exposure period) by each unit of the signal charge in the unit pixels10S. That is, the electronic shutter operation is an operation of resetting (sweeping out) signal charges stored in the photoelectric conversion unit and starting to accumulate new signal charges from the reset.

The pixel signal which is output from each of the unit pixels10S of the pixel row selectively scanned by the vertical scanning circuit13is input to the column signal processing unit14via each of the column signal lines41every pixel column.

The column signal processing unit14performs a predetermined signal process on the pixel signal output from each of the unit pixels10S of the reading row selected by the vertical scanning of the vertical scanning circuit13, for example, every pixel column of the pixel array unit11and temporarily stores the pixel signal having been subjected to the signal process.

For example, the column signal processing unit14performs an AD conversion process and a correlated double sampling (CDS) process for removing reset noise or a fixed pattern noise originated from a pixel such as a variation in threshold value of the amplification transistor on the pixel signal output from each of the unit pixels10S of the reading row selected by the vertical scanning

The horizontal scanning circuit15includes a shift register or an address decoder and sequentially and horizontally scans each of the pixel columns of the pixel array unit11in the column signal processing unit14storing the pixel signal having been subjected to the signal process. By the horizontal scanning of the horizontal scanning circuit15, the pixel signal having been subjected to the AD conversion of each of the unit pixels10S of the reading row and stored in the column signal processing unit14is output from the output unit16to the outside of the apparatus.

The solid-state imaging device1with the above-described configuration is a CMOS image sensor called a column AD type in which a CDS process and an AD conversion process are performed for each pixel column.

<2. Configuration Example of Column Signal Processing Unit>

FIG. 2is a diagram showing a configuration example of the column signal processing unit14.

The column signal processing unit14includes capacitive elements61and62, a comparator63, a counter64, a data storage unit65, and a reference signal generation circuit66. Among them, the capacitive elements61and62, the comparator63, and the counter64are provided by the unit of the pixel column.

The pixel signal output from the unit pixel10S is amplified by the differential amplifier including the differential amplifier component12and is input to the capacitive element61via the column signal line41. Meanwhile, a slope-shaped reference signal of which a level (a voltage) changes in an inclined manner with time is input from the reference signal generation circuit66to the capacitive element62. The capacitive elements61and62are capacitive elements for an analog CDS (AUTO ZERO) which cancels variations of analog elements.

The comparator63outputs a difference signal obtained by comparing (a voltage of) the pixel signal input via the capacitive element61and (a voltage of) of the reference signal input via the capacitive element62to the counter64. For example, a Hi (High) difference signal is supplied to the counter64in a case where the reference signal is smaller than the pixel signal and a Lo (Low) difference signal is supplied to the counter64in a case where the reference signal is larger than the pixel signal.

The counter64calculates a count value P by the counting during the supply of the Hi difference signal in the preset phase (P-phase) comparison period. Further, the counter64calculates a count value D by the counting during the supply of the Hi difference signal in the data phase (D-phase) comparison period. Then, the counter64supplies a difference value (D-P) obtained by subtracting the count value P in the P-phase comparison period from the count value D in the D-phase comparison period as the pixel data having been subjected to the CDS process and the AD conversion process to the data storage unit65.

The data storage unit65stores the pixel data having been subjected to the AD conversion process and supplied from the counter64of each of the pixel columns and sequentially outputs the pixel data to the output unit16at a predetermined timing in accordance with the control of the horizontal scanning circuit15.

<3. First Configuration Example of Differential Amplifier Component>

FIG. 3is a diagram showing the first configuration example of the differential amplifier component12.

Further,FIG. 3also shows detained configuration examples of the unit pixel10S and the dummy pixel10D disposed at the same pixel column.

The unit pixel10S includes a photodiode (PD)101, a transfer transistor102, a reset transistor103, an amplification transistor104, a selection transistor105, and a floating diffusion (FD)106.

The PD101is a photoelectric conversion element which obtains a signal charge in response to the incident light. The transfer transistor102transfers the signal charge stored in the PD101to the FD106on the basis of the transfer control signal TRG_S. The reset transistor103resets the signal charge of the FD106on the basis of the reset control signal RST_S. The amplification transistor104converts the signal charge of the FD106into a voltage signal and amplifies and outputs the voltage signal. The selection transistor105performs a control of determining whether an own pixel is a selected pixel among the unit pixels10S arranged in an array inside the pixel array unit11on the basis of the selection control signal SEL_S. The FD106is a charge storage portion which stores the signal charge transferred from the PD101by the transfer transistor102.

The dummy pixel10D includes a PD111, a transfer transistor112, a reset transistor113, an amplification transistor114, a selection transistor115, and a FD116.

The dummy pixel10D has the same configuration as that of the unit pixel10S, but is different from the unit pixel10S in that the PD111is light-shielded by a metal film or the like so that the incident light does not enter. The transfer transistor112is controlled by the transfer control signal TRG_D, the reset transistor113is controlled by the reset control signal RST_D, and the selection transistor115is controlled by the selection control signal SEL_D.

Additionally, the capacitances connected to the FD106of the unit pixel10S and the FD116of the dummy pixel10D indicate the parasitic capacitance of the floating diffusion and do not exist as capacitive element parts.

The differential amplifier component12includes an NMOS tail current source150, PMOS loads151and152constituting a current mirror circuit, and a resetting constant current circuit (or reset element)153.

The NMOS tail current source150is connected to the sources of the amplification transistors104and114via the column Vcom line43. A bias voltage Vbn is applied to the gate of the NMOS tail current source150and a constant current flows to the amplification transistors104and114.

The drain of one PMOS load151constituting the current mirror circuit is connected to the drain of the selection transistor115of the dummy pixel10D via the column signal line51. The drain of the other PMOS load152constituting the current mirror circuit is connected to the drain of the selection transistor105of the unit pixel10S via the column signal line41. The sources of the PMOS loads151and152are connected to a constant voltage source Vdd.

The PMOS loads151and152constituting the current mirror circuit allow the same current to flow to the column signal line51near the dummy pixel10D and the column signal line41near the unit pixel10S (e.g., during a read operation).

The resetting constant current circuit153is also connected to the column signal line51of the dummy pixel10D. The resetting constant current circuit153is a circuit which is connected between a constant voltage source Vbr1and the drain of the PMOS load151and through which a current of a predetermined current value IrstL (IrstL1, IrstL2) flows. Specifically, as will be described later, the resetting constant current circuit153outputs a first current value IrstL1during the resetting period and outputs a second current value InstR2smaller than the first current value IrstL1during the reading period so that different currents flow to the reference side of the differential pair between the resetting period and the reading period. Further, with this configuration, different currents flow to the reference side and the signal side of the differential pair during the resetting period.

The drain of the reset transistor113of the dummy pixel10D is connected to the column reset line52and the reset voltage Vrst is supplied to the column reset line52.

Meanwhile, the drain of the reset transistor103of the unit pixel10S is connected to the column reset line42and the column reset line42is connected to the column signal line41.

The differential amplifier component12constitutes the differential amplifier together with the amplification transistor114and the selection transistor115of the dummy pixel10D and the amplification transistor104and the selection transistor105of the unit pixel10S.

Referring toFIG. 4, operations of the differential amplifier component12, the unit pixel10S, and the dummy pixel10D of the first configuration example will be described.

FIG. 4shows a timing chart of the unit pixel10S and the dummy pixel10D of the pixel array unit11, the differential amplifier component12of the first configuration example, and the column signal processing unit14during a period 1H. The unit pixel10S and the dummy pixel10D are pixels of the same pixel column.

First, at the time t1, the selection control signal SEL_S and the selection control signal SEL_D supplied to the dummy pixel10D at the same column as the unit pixel10S selected to read the pixel signal is set to High (Hi) and the selection transistor105of the unit pixel10S and the selection transistor115of the dummy pixel10D are turned on. The selection control signal SEL_S and the selection control signal SEL_D are Hi until the time t11corresponding to the end of the period 1H and thus the unit pixel10S and the dummy pixel10D are selected.

The resetting period starts from the next time t2so that the reset control signals RST_S and RST_D are set to High (Hi). With this configuration, the reset transistor103of the unit pixel10S and the reset transistor113of the dummy pixel10D are turned on. Further, the resetting constant current circuit153changes the output current value IrstL to the first current value (the reset current value) IrstL1(>IrstL2) larger than the second current value InstL2kept so far.

In this state, the differential amplifier operates as a voltage follower, the potential of the FD116of the dummy pixel10D becomes the reset voltage Vrst, and the potential of the FD106and the potential VSL_S of the column signal line41of the unit pixel10S also follow the reset voltage Vrst.

At the next time t3, the reset control signals RST_S and RST_D are changed to Low (Lo) and the reset transistors103and113are turned off. When the reset transistors103and113are turned off, the potentials of the FDs106and116slightly decrease by switch feedthrough. However, a voltage variation of the potential VSL_S of the column signal line41can be reduced by the in-phase cancellation effect of the differential amplifier. In a case of a single-ended source-grounded amplifier, for example, the FD voltage drop due to feedthrough at the time of resetting is amplified by the gain of the amplifier of the pixel and the output end may exceed the operation range.

At the time t4after a predetermined time elapses from the time t3, the current value IrstL output from the resetting constant current circuit153is returned from the first current value IrstL1to the second current value InstL2(<IrstL1) smaller than the first current value.

As shown inFIG. 4, the potential VSL_S of the column signal line41rises after the time t4in response to the period until the time t4in which the resetting constant current circuit153outputs the first current value IrstL1from the time t3in which the reset transistors103and113are turned off. The raised potential VSL_S of the column signal line41becomes the operation point (the operation start potential) used to determine the operation range of the differential amplifier.

InFIG. 4, the potential VSL_S in a case where the resetting constant current circuit153is not provided and the operation point is not adjusted is indicated by a dashed line. The optimal operation range of the differential amplifier exists at a range higher than the original operation point of the differential amplifier. If the resetting constant current circuit153allows a current larger than that of the signal side column signal line41to flow to the reference side column signal line51of the differential amplifier during a period from the time t3to the time t4, the potential VSL_S of the column signal line41is raised to the optimal operation range of the differential amplifier.

For example, in a case where the differential amplifier is in an equilibrium state during a period from the time t3to the time t4, a current of about 7 uA flows to each of the PMOS loads151and152when the current value output from the NMOS tail current source150is 20 uA and the first current value IrstL1output from the resetting constant current circuit153is 6 uA. For this reason, a current of about 13 uA flows to the amplification transistor114of the dummy pixel10D and a current of about 7 uA flows to the amplification transistor104of the unit pixel10S. Thus, the resetting constant current circuit153generates a difference in the currents respectively flowing to the signal side and the reference side of the differential pair.

Meanwhile, since a current of about 10 uA flows to each of the PMOS loads151and152in a case where the second current value InstL2output from the resetting constant current circuit153is 0 while the current value output from the NMOS tail current source150is 20 uA in a case where the differential amplifier is in an equilibrium state during the reading period to be described later, a current of about 10 uA flows to each of the amplification transistors114and104.

A period from the time t3in which the resetting constant current circuit153allows a current larger than that of the signal side column signal line41to flow to the reference side column signal line51of the differential amplifier to the time t4is determined in advance on the basis of the optimal operation range of the differential amplifier in design.

Specifically, it is possible to design the magnitude of the current at the reference side and the signal side during the resetting period when the resetting constant current circuit153is used. Further, it is possible to also design a difference between the gate voltage of the amplification transistor114of the reference side dummy pixel10D and the gate voltage of the amplification transistor104of the signal side unit pixel10S. After the reset transistors103and113are turned off, the gates of the amplification transistors114and104are floated and thus the reading period is set. Here, if the variation amount of the current at the reference side and the signal side of the reading period is designed, the output voltage of the differential amplifier, that is, the potential VSL_S of the column signal line41can be adjusted within the optimal operation range.

During a P-phase comparison period from the time t5to the time t6after the potential VSL_S of the column signal line41is adjusted to the operation point (the operation start potential) of the optimal operation range of the differential amplifier, the voltage of the pixel signal of the unit pixel10S and the voltage of the reference signal supplied from the reference signal generation circuit66are compared with each other and the count value P is calculated.

During a period from the time t7to the time t8, the transfer control signal TRG_S of Hi is supplied to the transfer transistor102of the unit pixel10S, the transfer transistor102is turned on, and the signal charge stored in the PD101is transferred to the FD106. At this time, the transfer control signal TRG_D supplied to the transfer transistor112of the dummy pixel10D is in the state of Lo.

The reading period of the pixel signal is set after the time t8in which the transfer transistor102of the unit pixel10S is turned off, the counter64sets the count value-P obtained by bit-inverting the count value P calculated in the P-phase comparison period to the initial count value.

During the D-phase comparison period from the time t9to t10, the voltage of the pixel signal of the unit pixel10S and the voltage of the reference signal supplied from the reference signal generation circuit66are compared with each other and a difference value (D-P) obtained by subtracting the count value P of the P-phase comparison period from the count value D of the D-phase comparison period is calculated.

Finally, if the selection control signal SEL_S and the selection control signal SEL_D are changed to Lo at the time t11, the selection transistor105of the unit pixel10S and the selection transistor115of the dummy pixel10D are turned off so that the period 1H ends.

As described above, according to the differential amplifier component12of the first configuration example ofFIG. 3, the first current value IrstL1is output from the resetting constant current circuit153during the resetting period so that a current larger than that of the signal side column signal line41is output to the reference side column signal line51. Further, the resetting constant current circuit153outputs the second current value InstR2smaller than the first current value IrstL1during the reading period. In this way, if the resetting constant current circuit153generates a difference in current flowing to each of the signal side and the reference side of the differential pair during the resetting period to change the current flowing to the amplification transistors114and104between the resetting period and the reading period, the potential VSL_S of the column signal line41can be adjusted to the optimal operation point (operation range) of the differential amplifier at the upside (the high potential side) in relation to the original operation point of the differential amplifier. As a result, it is possible to improve linearity by improving the conversion efficiency of the amplification transistor104.

The differential amplifier component12of the first configuration example ofFIG. 3is a configuration example of adjusting the operation point of the differential amplifier in a case where the optimal operation point of the differential amplifier is located at the upside (the high potential side) in relation to the original operation point of the differential amplifier.

Next, a configuration example of adjusting the operation point of the differential amplifier in a case where the optimal operation point of the differential amplifier is located at the downside (the low potential side) in relation to the original operation point of the differential amplifier will be described.

<4. Second Configuration Example Of Differential Amplifier Component>

FIG. 5is a diagram showing a second configuration example of the differential amplifier component12.

FIG. 5also shows detailed configurations of the unit pixel10S and the dummy pixel10D disposed at the same pixel column. Additionally, inFIG. 5, the same reference numerals will be given to the parts common to those of the first configuration example shown inFIG. 3and a description of the part will be appropriately omitted. The same applies to the description after the third configuration example to be described later.

The arrangement of the resetting constant current circuit153of the differential amplifier component12of the second configuration example ofFIG. 5is different from that of the first configuration example shown inFIG. 3. That is, in the differential amplifier component12of the first configuration example ofFIG. 3, the resetting constant current circuit153is connected between the constant voltage source Vbr1and the drain of the PMOS load151and a current of the predetermined current value IrstL flows to the reference side column signal line51. However, in the differential amplifier component12of the second configuration example, the resetting constant current circuit153is connected between the constant voltage source Vbrr and the drain of the PMOS load152and a current of the predetermined current value IrstR (IrstR1, IrstR2) flows to the signal side column signal line41. The other configurations ofFIG. 5including the configurations of the unit pixel10S and the dummy pixel10D are similar to those of the first configuration example ofFIG. 3.

FIG. 6shows a timing chart of the unit pixel10S and the dummy pixel10D of the pixel array unit11, the differential amplifier component12of the second configuration example, and the column signal processing unit14during a period 1H.

The timing chart ofFIG. 6corresponds to the timing chart ofFIG. 4of the first configuration example and the time t31to the time t41ofFIG. 6respectively correspond to the time t1to the time t11ofFIG. 4. Also inFIG. 6, a description will be made by focusing on a part different from the timing chart of the first configuration example described inFIG. 4.

At the time t32in which the resetting period starts, the reset control signals RST_S and RST_D are set to Hi and the reset transistor103of the unit pixel10S and the reset transistor113of the dummy pixel10D are turned on. At the same time, the resetting constant current circuit153changes the output current value IrstR to the first current value (the reset current value) IrstR1(>IrstR2) larger than the second current value InstR2kept so far.

At the next time t33, the reset control signals RST_S and RST_D are changed to Lo and the reset transistors103and113are turned off.

At the time t34after a predetermined time elapses from the time t33, the current value IrstR output from the resetting constant current circuit153is returned from the first current value IrstR1to the second current value InstR2(<IrstR1) smaller than the first current value.

In this way, if the resetting constant current circuit153outputs the first current value IrstR1so that a current larger than that of the reference side column signal line51is output to the signal side column signal line41during the resetting period, the original operation point (the operation start potential) of the differential amplifier can be adjusted to a potential smaller than the original operation point of the differential amplifier as shown inFIG. 6.

The operations at the other time (the time t31and the time t35to the time t41) are similar to those of the first configuration example described with reference toFIG. 4.

According to the differential amplifier component12of the second configuration example ofFIG. 5, the resetting constant current circuit153outputs the first current value IrstR1so that a current larger than that of the reference side column signal line51is output to the signal side column signal line41during the resetting period. Further, the resetting constant current circuit153outputs the second current value InstR2smaller than the first current value IrstR1during the reading period. In this way, if the resetting constant current circuit153generates a difference in current flowing to each of the signal side and the reference side of the differential pair during the resetting period to change a current flowing to the amplification transistors114and104between the resetting period and the reading period, the potential VSL_S of the column signal line41can be adjusted to the optimal operation point (operation range) of the differential amplifier at the downside (the low potential side) in relation to the original operation point of the differential amplifier as shown inFIG. 6. As a result, it is possible to improve linearity by improving the conversion efficiency of the amplification transistor104.

<5. Third Configuration Example of Differential Amplifier Component>

FIG. 7is a diagram showing a third configuration example of the differential amplifier component12.

The differential amplifier component12of the third configuration example ofFIG. 7has both configurations of the first configuration example shown inFIG. 3and the second configuration example shown inFIG. 5. That is, the differential amplifier component12of the third configuration example includes both a resetting constant current circuit153L which is connected between the constant voltage source Vbr1and the drain of the PMOS load151and allows a current of the predetermined current value IrstL to flow to the reference side column signal line51and a resetting constant current circuit153R which is connected between the constant voltage source Vbrr and the drain of the PMOS load152and allows a current of the predetermined current value IrstR to flow to the signal side column signal line41. The other configurations ofFIG. 7including the configurations of the unit pixel10S and the dummy pixel10D are similar to those of the first configuration example and the second configuration example.

FIG. 8shows a timing chart of the unit pixel10S and the dummy pixel10D of the pixel array unit11, the differential amplifier component12of the third configuration example, and the column signal processing unit14during a period 1H.

The timing chart ofFIG. 8corresponds to the timing chart ofFIG. 4of the first configuration example and the time t51to the time t61ofFIG. 8respectively correspond to the time t1to the time t11ofFIG. 4. Also inFIG. 8, a description will be made by focusing on a part different from the timing chart of the first configuration example described inFIG. 4.

At the time t52in which the resetting period starts, the reset control signals RST_S and RST_D are set to Hi and the reset transistor103of the unit pixel10S and the reset transistor113of the dummy pixel10D are turned on.

Further, at the time t52, the reference side resetting constant current circuit153L changes the output current value IrstL to the first current value (the reset current value) IrstL3(>IrstR4) larger than the second current value IrstL4kept so far. At the same time, the signal side resetting constant current circuit153R changes the output current value IrstR to the first current value (the reset current value) IrstR6(<IrstR5) smaller than the second current value IrstR5kept so far. With this configuration, the amount of the current flowing to the amplification transistor114of the dummy pixel10D via the column signal line51becomes larger than the amount of the current flowing to the amplification transistor104of the unit pixel10S via the column signal line41.

At the next time t53, the reset control signals RST_S and RST_D are changed to Lo and the reset transistors103and113are turned off.

At the time t54after a predetermined time elapses from the time t53, the reference side resetting constant current circuit153L changes the output current value IrstL to the second current value IrstL4(<IrstR3) smaller than the first current value (the reset current value) IrstL3kept so far. At the same time, the signal side resetting constant current circuit153R changes the output current value IrstR to the second current value IrstR5(>IrstR6) larger than the first current value (the reset current value) IrstR6kept so far.

The operations at the other time (the time t51and the time t55to the time t61) are similar to those of the first configuration example described with reference toFIG. 4.

The reference side resetting constant current circuit153L allows a current of the first current value IrstL3larger than before to flow and the signal side resetting constant current circuit153R allows a current of the first current value IrstR6smaller than before to flow so that the amount of the current flowing to the amplification transistor114of the dummy pixel10D via the column signal line51becomes larger than the amount of the current flowing to the amplification transistor104of the unit pixel10S via the column signal line41during a period from the time t52to the time t54. With this configuration, as shown inFIG. 8, the potential VSL_S of the column signal line41can be adjusted to the optimal operation point (operation range) of the differential amplifier at the upside (the high potential side) in relation to the original operation point of the differential amplifier. As a result, it is possible to improve linearity by improving the conversion efficiency of the amplification transistor104.

Additionally, according to the third configuration example, since the resetting constant current circuit153is provided at both the reference side and the signal side, the potential can be adjusted to the optimal operation point (operation range) of the differential amplifier at the downside (the low potential side) in relation to the original operation point of the differential amplifier.

Specifically, the reference side resetting constant current circuit153L sets the output current value IrstL to the second current value IrstL4(<IrstL3) having a small value during a period from the time t52to the time t54and sets the output current value to the first current value IrstL3having a large value during other periods. The signal side resetting constant current circuit153R sets the output current value IrstR to the first current value IrstR6(>IrstR5) having a large value during a period from the time t52to the time t54and sets the output current value to the second current value IrstR6having a small value during other periods.

With this configuration, the amount of the current flowing to the amplification transistor104of the unit pixel10S via the column signal line41becomes larger than the amount of the current flowing to the amplification transistor114of the dummy pixel10D via the column signal line51and the potential VSL_S of the column signal line41is adjusted to the downside (the low potential side) in relation to the original operation point of the differential amplifier.

<6. Fourth Configuration Example of Differential Amplifier Component>

FIG. 9is a diagram showing a fourth configuration example of the differential amplifier component12.

In the differential amplifier component12of the fourth configuration example of

FIG. 9, the resetting constant current circuit153shown inFIG. 3is replaced by a constant current source171and a switch172. The constant current source171outputs a predetermined current. The switch172turns on and off the connection between the constant current source171and the column signal line51on the basis of the control signal SWL. The on/off state of the switch172changes between the resetting period and the reading period. The other configurations ofFIG. 9including the configurations of the unit pixel10S and the dummy pixel10D are similar to those of the first configuration example.

FIG. 10shows a timing chart of the unit pixel10S and the dummy pixel10D of the pixel array unit11, the differential amplifier component12of the fourth configuration example, and the column signal processing unit14during a period 1H.

The timing chart ofFIG. 10corresponds to the timing chart ofFIG. 4of the first configuration example and the time t71to the time t81ofFIG. 10respectively correspond to the time t1to the time t11ofFIG. 4. Also inFIG. 10, a description will be made by focusing on a part different from the timing chart of the first configuration example described inFIG. 4.

At the time t72in which the resetting period starts, the reset control signals RST_S and RST_D are set to Hi and the reset transistor103of the unit pixel10S and the reset transistor113of the dummy pixel10D are turned on.

Further, at the time t72, the control signal SWL of Hi is supplied to the switch172so that the switch172connects the constant current source171and the column signal line51to each other. With this configuration, a predetermined current flows from the constant current source171to the reference side column signal line51.

At the next time t73, the reset control signals RST_S and RST_D are changed to Lo and the reset transistors103and113are turned off.

At the time t74after a predetermined time elapses from the time t73, the control signal SWL is changed from Hi to Lo and the switch172is turned off so that the constant current source171is separated from the column signal line51.

The operations at the other time (the time t71and the time t75to the time t81) are similar to those of the first configuration example described with reference toFIG. 4.

If the constant current source171is connected to the column signal line51during a period from the time t72to the time t74, the amount of the current flowing to the amplification transistor114of the dummy pixel10D via the column signal line51becomes larger than the amount of the current flowing to the amplification transistor104of the unit pixel10S via the column signal line41. With this configuration, as shown inFIG. 10, the potential VSL_S of the column signal line41can be adjusted to the optimal operation point (operation range) of the differential amplifier located at the upside (the high potential side) in relation to the original operation point of the differential amplifier. As a result, it is possible to improve linearity by improving the conversion efficiency of the amplification transistor104.

<7. Fifth Configuration Example of Differential Amplifier Component>

FIG. 11is a diagram showing a fifth configuration example of the differential amplifier component12.

In the differential amplifier component12of the fifth configuration example ofFIG. 11, the resetting constant current circuit153shown inFIG. 5is replaced by the constant current source171and the switch172. In other words, in the differential amplifier component12of the fifth configuration example, the constant current source171and the switch172of the fourth configuration example shown inFIG. 9are provided at the signal side instead of the reference side. The switch172turns on and off the connection between the constant current source171and the column signal line41on the basis of the control signal SWR. The on/off state of the switch172changes between the resetting period and the reading period. The other configurations ofFIG. 11including the configurations of the unit pixel10S and the dummy pixel10D are similar to those of the fourth configuration example ofFIG. 9.

FIG. 12shows a timing chart of the unit pixel10S and the dummy pixel10D of the pixel array unit11, the differential amplifier component12of the fifth configuration example, and the column signal processing unit14during a period 1H.

The timing chart ofFIG. 12corresponds to the timing chart ofFIG. 6of the second configuration example and the time t91to the time t101respectively correspond to the time t31to the time t41ofFIG. 6. Also inFIG. 12, a description will be made by focusing on a part different from the timing chart of the second configuration example described with reference toFIG. 6.

At the time t92in which the resetting period starts, the reset control signals RST_S and RST_D are set to Hi and the reset transistor103of the unit pixel10S and the reset transistor113of the dummy pixel10D are turned on.

Further, at the time t92, the control signal SWR of Hi is supplied to the switch172so that the switch172connects the constant current source171and the column signal line41to each other. With this configuration, a predetermined current flows from the constant current source171to the signal side column signal line41.

At the next time t93, the reset control signals RST_S and RST_D are changed to Lo and the reset transistors103and113are turned off.

At the time t94after a predetermined time elapses from the time t93, the control signal SWR is changed from Hi to Lo and the switch172is turned off so that the constant current source171is separated from the column signal line41.

The operations at the other time (the time t91and the time t95to the time t101) are similar to those of the second configuration example described with reference toFIG. 6.

If the constant current source171is connected to the column signal line41during a period from the time t92to the time t94, the amount of the current flowing to the amplification transistor104of the unit pixel10S via the column signal line41becomes larger than the amount of the current flowing to the amplification transistor114of the dummy pixel10D via the column signal line51. With this configuration, as shown inFIG. 12, the potential VSL_S of the column signal line41can be adjusted to the optimal operation point (operation range) of the differential amplifier located at the downside (the low potential side) in relation to the original operation point of the differential amplifier. As a result, it is possible to improve linearity by improving the conversion efficiency of the amplification transistor104.

<8. Sixth Configuration Example of Differential Amplifier Component>

FIG. 13is a diagram showing a sixth configuration example of the differential amplifier component12.

The differential amplifier component12of the sixth configuration example ofFIG. 13has both configurations of the fourth configuration example shown inFIG. 9and the fifth configuration example shown inFIG. 11. That is, the differential amplifier component12of the sixth configuration example includes both a constant current source171L and a switch172L connected between the constant voltage source Vbr1and the drain of the PMOS load151and a constant current source171R and a switch172R connected between the constant voltage source Vbrr and the drain of the PMOS load152. The switch172L turns on and off the connection between the constant current source171L and the column signal line51on the basis of the control signal SWL. The switch172R turns on and off the connection between the constant current source171R and the column signal line41on the basis of the control signal SWR. The on/off states of the switch172L and172R change between the resetting period and the reading period. The other configurations ofFIG. 13including the configurations of the unit pixel10S and the dummy pixel10D are similar to those of the fourth configuration example and the fifth configuration example.

FIG. 14shows a timing chart of the unit pixel10S and the dummy pixel10D of the pixel array unit11, the differential amplifier component12of the sixth configuration example, and the column signal processing unit14during a period 1H.

The timing chart ofFIG. 14corresponds to the timing chart ofFIG. 8of the third configuration example and the time t111to the time t121respectively correspond to the time t51to the time t61ofFIG. 8. Also inFIG. 14, a description will be made by focusing on a part different from the timing chart of the third configuration example described with reference toFIG. 8.

At the time t112in which the resetting period starts, the reset control signals RST_S and RST_D are set to Hi and the reset transistor103of the unit pixel10S and the reset transistor113of the dummy pixel10D are turned on.

Further, at the time t112, the control signal SWL of Hi is supplied to the switch172L so that the switch172L connects the constant current source171L and the column signal line51to each other. With this configuration, a predetermined current flows from the constant current source171L to the reference side column signal line51.

At the same time t112, the control signal SWR of Lo is supplied to the switch172R so that the switch172R separates the constant current source171R from the column signal line41. With this configuration, a current flowing from the constant current source171R so far does not flow to the signal side column signal line41.

At the next time t113, the reset control signals RST_S and RST_D are changed to Lo and the reset transistors103and113are turned off.

At the time t114after a predetermined time elapses from the time t113, the control signal SWL is changed from Hi to Lo and the switch172L is turned off so that the constant current source171L is separated from the column signal line51. With this configuration, a current does not flow from the constant current source171L to the reference side column signal line51. Further, at the time t114, the control signal SWR is changed from Lo to Hi and the switch172R is turned on so that the constant current source171R is connected to the column signal line41. With this configuration, a predetermined current flows from the constant current source171R to the signal side column signal line41.

The operations at the other time (the time t111and the time t115to the time t121) are similar to those of the first configuration example described with reference toFIG. 4.

If the constant current source171L is connected to the column signal line51and the constant current source171R is separated from the column signal line41during a period from the time t112to the time t114, the amount of the current flowing to the amplification transistor114of the dummy pixel10D via the column signal line51becomes larger than the amount of the current flowing to the amplification transistor104of the unit pixel10S via the column signal line41. With this configuration, as shown inFIG. 14, the potential VSL_S of the column signal line41can be adjusted to the optimal operation point (operation range) of the differential amplifier located at the upside (the high potential side) in relation to the original operation point of the differential amplifier. As a result, it is possible to improve linearity by improving the conversion efficiency of the amplification transistor104.

Additionally, according to the sixth configuration example, since the constant current source171and the switch172are provided at both the reference side and the signal side, the potential can be adjusted to the optimal operation point (operation range) of the differential amplifier located at the downside (the low potential side) in relation to the original operation point of the differential amplifier.

Specifically, the differential amplifier component12changes the control signal SWL to Lo and changes the control signal SWR to Hi so that the constant current source171L is separated from the column signal line51and the constant current source171R is connected to the column signal line41during a period from the time t112to the time t114. With this configuration, the amount of the current flowing to the amplification transistor104of the unit pixel10S via the column signal line41becomes larger than the amount of the current flowing to the amplification transistor114of the dummy pixel10D via the column signal line51. With this configuration, the potential VSL_S of the column signal line41can be adjusted to the optimal operation point (operation range) of the differential amplifier located at the downside (the low potential side) in relation to the original operation point of the differential amplifier. As a result, it is possible to improve linearity by improving the conversion efficiency of the amplification transistor104.

<9. Seventh Configuration Example of Differential Amplifier Component>

FIG. 15is a diagram showing a seventh configuration example of the differential amplifier component12.

In the differential amplifier component12of the seventh configuration example shown inFIG. 15, a resetting PMOS transistor191is provided instead of the resetting constant current circuit153of the first configuration example shown inFIG. 3. The source of the resetting PMOS transistor191is connected to the constant voltage source Vdd and the drain of the resetting PMOS transistor191is connected to the column signal line51and the drain of the PMOS load151. The control signal Vbph of Hi or the control signal Vbp1of Lo is supplied to the gate of the resetting PMOS transistor191.

The operation of the seventh configuration example ofFIG. 15will be described with reference to the flowchart ofFIG. 4. That is, when the control signal Vbp1of Lo is supplied to the gate of the resetting PMOS transistor191to turn on the resetting PMOS transistor191at the same time when the reset transistor103of the unit pixel10S and the reset transistor113of the dummy pixel10D are turned on during a period from the time t2to the time t4, a predetermined current flows from the resetting PMOS transistor191to the reference side column signal line51. In other periods, since the control signal Vbph of Hi is supplied to the gate of the resetting PMOS transistor191to turn off the resetting PMOS transistor191, a current does not flow from the resetting PMOS transistor191to the reference side column signal line51.

With this configuration, as shown inFIG. 4, the potential VSL_S of the column signal line41can be adjusted to the optimal operation point (operation range) of the differential amplifier located at the upside (the high potential side) in relation to the original operation point of the differential amplifier. As a result, it is possible to improve linearity by improving the conversion efficiency of the amplification transistor104.

<10. Eighth Configuration Example of Differential Amplifier Component>

FIG. 16is a diagram showing an eighth configuration example of the differential amplifier component12.

In the differential amplifier component12of the eighth configuration example of

FIG. 16, a switch201and a resistor202which are connected in series to each other are provided instead of the resetting constant current circuit153of the first configuration example shown inFIG. 3. The other end different from the side of the resistor202in the switch201is connected to the constant voltage source Vbr1. The other end different from the side of the switch201in the resistor202is connected to the column signal line51and the drain of the PMOS load151. The switch201turns on and off the connection between the constant voltage source Vbr1and the resistor202on the basis of the control signal SWL.

The operation of the eighth configuration example ofFIG. 16will be described with reference to the flowchart ofFIG. 4. That is, when the control signal SWL of Hi is supplied to the switch201to turn on the switch201at the same time when the reset transistor103of the unit pixel10S and the reset transistor113of the dummy pixel10D are turned on during a period from the time t2to the time t4, a predetermined current flows from the resistor202to the reference side column signal line51. In other periods, since the control signal SWL of Lo is supplied to the switch201to turn off the switch201, a current does not flow from the resistor202to the reference side column signal line51.

With this configuration, as shown inFIG. 4, the potential VSL_S of the column signal line41can be adjusted to the optimal operation point (operation range) of the differential amplifier located at the upside (the high potential side) in relation to the original operation point of the differential amplifier. As a result, it is possible to improve linearity by improving the conversion efficiency of the amplification transistor104.

<11. Ninth Configuration Example of Differential Amplifier Component>

FIG. 17is a diagram showing a ninth configuration example of the differential amplifier component12.

In the differential amplifier component12of the ninth configuration example ofFIG. 17, a reset element comprising a resetting PMOS transistor221and a switch222are provided instead of the resetting constant current circuit153of the first configuration example shown inFIG. 3.

The source of the resetting PMOS transistor221is connected to the constant voltage source Vbr1and the drain of the resetting PMOS transistor221is connected to the column signal line51and the drain of the PMOS load151via the switch222. A bias voltage Vbp for turning on the resetting PMOS transistor221is normally supplied to the gate of the resetting PMOS transistor221. The switch222turns on and off the connection between the drain of the resetting PMOS transistor221and the column signal line51and the drain of the PMOS load151on the basis of the control signal SWL.

The operation of the ninth configuration example ofFIG. 17will be described with reference to the flowchart ofFIG. 4. That is, when the control signal SWL of Hi is supplied to the switch222to turn on the switch222at the same time when the reset transistor103of the unit pixel10S and the reset transistor113of the dummy pixel10D are turned on during a period from the time t2to the time t4, a predetermined current flows from the resetting PMOS transistor221to the reference side column signal line51. In other periods, since the control signal SWL of Lo is supplied to the switch222to turn off the switch222, a current does not flow from the resetting PMOS transistor221to the reference side column signal line51.

With this configuration, as shown inFIG. 4, the potential VSL_S of the column signal line41can be adjusted to the optimal operation point (operation range) of the differential amplifier located at the upside (the high potential side) in relation to the original operation point of the differential amplifier. As a result, it is possible to improve linearity by improving the conversion efficiency of the amplification transistor104.

<12. Tenth Configuration Example of Differential Amplifier Component>

FIG. 18is a diagram showing a tenth configuration example of the differential amplifier component12.

In the differential amplifier component12of the tenth configuration example ofFIG. 18, the gate of the resetting PMOS transistor221of the ninth configuration example shown inFIG. 17is connected to the column signal line51, the drain and the gate of the PMOS load151, and the gate of the PMOS load152. In this case, there is an advantage that the bias voltage Vbp applied to the gate of the resetting PMOS transistor221is not necessary compared to the ninth configuration example.

Since the operation of the tenth configuration example is similar to that of the ninth configuration example, a description will be omitted.

Also in the tenth configuration example, similarly to the ninth configuration example, the potential VSL_S of the column signal line41can be adjusted to the optimal operation point (operation range) of the differential amplifier located at the upside (the high potential side) in relation to the original operation point of the differential amplifier. As a result, it is possible to improve linearity by improving the conversion efficiency of the amplification transistor104.

<13. Eleventh Configuration Example of Differential Amplifier Component>

FIG. 19is a diagram showing an eleventh configuration example of the differential amplifier component12.

In the differential amplifier component12of the eleventh configuration example of

FIG. 19, the resetting constant current circuit153of the first configuration example shown inFIG. 3is omitted and the signal side is provided with a resetting NMOS transistor241and a switch242instead.

The drain of the resetting NMOS transistor241is connected to the drain of the

PMOS load152and the column signal line41and the source of the resetting NMOS transistor241is connected to the low potential Vbrg (for example, GND) via the switch242. A bias voltage Vbn for turning on the resetting NMOS transistor241is normally supplied to the gate of the resetting NMOS transistor241. The switch242turns on and off the connection between the source of the resetting NMOS transistor241and the low potential Vbrg on the basis of the control signal SWR.

The operation of the eleventh configuration example ofFIG. 19will be described with reference to the flowchart ofFIG. 4. That is, when the control signal SWR of Hi is supplied to the switch242to turn on the switch242at the same time when the reset transistor103of the unit pixel10S and the reset transistor113of the dummy pixel10D are turned on during a period from the time t2to the time t4, a predetermined current flows from the drain of the PMOS load152to the low potential Vbrg via the resetting NMOS transistor241. In other periods, since the control signal SWR of Lo is supplied to the switch242to turn off the switch242, a current does not flow between the drain and the source of the resetting NMOS transistor241.

The differential amplifier components12of the seventh to tenth configuration examples shown inFIGS. 15 to 18adjusts the operation point of the differential amplifier to the upside (the high potential side) in relation to the original operation point of the differential amplifier by increasing the amount of the current supplied to the reference side amplification transistor114compared to the signal side amplification transistor104during the resetting period.

In contrast, the differential amplifier component12of the eleventh configuration example ofFIG. 19adjusts the operation point of the differential amplifier to the upside (the high potential side) in relation to the original operation point of the differential amplifier by drawing a part of the current flowing through the PMOS load152to the resetting NMOS transistor241during the resetting period so that the amount of the current supplied to the signal side amplification transistor104becomes smaller than that of the reference side amplification transistor114.

<14. Twelfth Configuration Example of Differential Amplifier Component>

FIG. 20is a diagram showing a twelfth configuration example of the differential amplifier component12.

The differential amplifier component12of the twelfth configuration example ofFIG. 20has a configuration in which PMOS transistors261and262are added to the tenth configuration example shown inFIG. 18by a cascode connection.

Specifically, the source of the PMOS transistor261is connected to the drain and the gate of the PMOS load151, the gate of the resetting PMOS transistor221, and the other end different from the side of the resetting PMOS transistor221in the switch222. The drain of the PMOS transistor261is connected to the drain of the selection transistor115via the column signal line51.

The source of the PMOS transistor262is connected to the drain of the PMOS load152. The drain of the PMOS transistor262is connected to the drains of the selection transistor105and the reset transistor103via the column signal line41and the column reset line42.

A bias voltage Vbp2is applied to the gates of the PMOS transistors261and262.

<15. Thirteenth Configuration Example of Differential Amplifier Component>

FIG. 21is a diagram showing a thirteenth configuration example of the differential amplifier component12.

The differential amplifier component12of the thirteenth configuration example of

FIG. 21is different from that of the twelfth configuration example ofFIG. 20in that the connection destination of the other end different from the side of the resetting PMOS transistor221in the switch222is different.

In the twelfth configuration example ofFIG. 20, the other end different from the side of the resetting PMOS transistor221in the switch222is connected to the source side of the PMOS transistor261. However, in the thirteenth configuration example ofFIG. 21, the other end thereof is connected to the drain side of the PMOS transistor261. The other configurations are similar to those of the twelfth configuration example.

<16. Fourteenth Configuration Example of Differential Amplifier Component>

FIG. 22is a diagram showing a fourteenth configuration example of the differential amplifier component12.

The differential amplifier component12of the fourteenth configuration example ofFIG. 22has a configuration in which the NMOS transistors271and272are added to the tenth configuration example shown inFIG. 18by a cascode connection.

Specifically, the drain of the NMOS transistor271is connected to the drain and the gate of the PMOS load151, the gate of the resetting PMOS transistor221, and the other end different from the side of the resetting PMOS transistor221in the switch222. The source of the NMOS transistor271is connected to the drain of the selection transistor115via the column signal line51.

The drain of the NMOS transistor272is connected to the drain of the PMOS load152. The drain of the NMOS transistor272is connected to the drains of the selection transistor105and the reset transistor103via the column signal line41and the column reset line42.

A bias voltage Vbn2is applied to the gates of the NMOS transistors271and272.

<17. Fifteenth Configuration Example of Differential Amplifier Component>

FIG. 23is a diagram showing a fifteenth configuration example of the differential amplifier component12.

The differential amplifier component12of the fifteenth configuration example of

FIG. 23is different from that of the fourteenth configuration example ofFIG. 22in that the connection destination of the other end different from the side of the resetting PMOS transistor221in the switch222is different.

In the fourteenth configuration example ofFIG. 22, the other end different from the side of the resetting PMOS transistor221in the switch222is connected to the drain side of the NMOS transistor271. However, in the fifteenth configuration example ofFIG. 23, the other end thereof is connected to the source side of the NMOS transistor271. The other configurations are similar to those of the thirteenth configuration example.

Also in the differential amplifier components12of the twelfth to fifteenth configuration examples having a cascode structure shown inFIGS. 20 to 23, similarly to the tenth configuration example shown inFIG. 18, the potential VSL_S of the column signal line41can be adjusted to the optimal operation point (operation range) of the differential amplifier located at the upside (the high potential side) in relation to the original operation point of the differential amplifier. As a result, it is possible to improve linearity by improving the conversion efficiency of the amplification transistor104.

The differential amplifier components12of the seventh configuration example of

FIG. 15to the fifteenth configuration example ofFIG. 23are configured to adjust the operation point (the operation range) of the differential amplifier to the upside (the high potential side) in relation to the original operation point of the differential amplifier by increasing the amount of the current supplied to the reference side amplification transistor114to be larger than the amount of the current supplied to the signal side amplification transistor104during the resetting period.

However, in the seventh configuration example ofFIG. 15to the fifteenth configuration example ofFIG. 23(excluding the eleventh configuration example ofFIG. 19), the resetting circuit generating a current difference is provided at the signal side like, for example, the second configuration example ofFIG. 5and in the eleventh configuration example ofFIG. 19, the resetting circuit generating a difference in current is provided at the reference side. With this configuration, if the amount of the current supplied to the signal side amplification transistor104becomes larger than the amount of the current supplied to the reference side amplification transistor114during the resetting period, the operation point (the operation range) of the differential amplifier can be adjusted to the downside (the low potential side) in relation to the original operation point of the differential amplifier.

Further, for example, similarly to the third configuration example ofFIG. 7, the resetting circuits of the seventh configuration example ofFIG. 15to the fifteenth configuration example ofFIG. 23are provided at both the reference side and the signal side. With this configuration, the operation point (the operation range) of the differential amplifier can be, of course, adjusted to both the upside (the high potential side) and the downside (the low potential side) in relation to the original operation point of the differential amplifier.

<18. Schematic Configuration of Solid-State Imaging Device of Second Embodiment>

FIG. 24is a diagram showing a schematic configuration of a solid-state imaging device according to a second embodiment of the present technology.

InFIG. 24, the same reference numerals will be given to the parts common to those of the first embodiment shown inFIG. 1and a description of the part will be appropriately omitted.

In the above-described first embodiment, the differential pair of the differential amplifier includes the unit pixel10S inside the effective pixel area and the dummy pixel10D outside the effective pixel area of the pixel array unit11.

In the second embodiment, the differential pair of the differential amplifier includes the unit pixel10S disposed in the odd row (hereinafter, referred to as an odd row pixel10S_O) and the unit pixel10S disposed in the even row (hereinafter, referred to as an even row pixel10S_E) in the unit pixels10S inside the effective pixel area of the pixel array unit11.

In the pixel array unit11, the odd row pixel10S_O and the even row pixel10S_E are alternately arranged in the vertical direction. InFIG. 24, the column signal line41and the column reset line42connected to the odd row pixel10S_O are indicated by a column signal line41_O and a column reset line42_O and the column signal line41and the column reset line42connected to the even row pixel10S_E are indicated by a column signal line41_E and a column reset line42_E.

Additionally, the dummy pixel10D disposed outside the effective pixel area is not shown inFIG. 24.

A signal switching unit301is newly added to the solid-state imaging device1of the second embodiment. The signal switching unit301switches the output destination of the pixel signal in a case where the signal side pixel of the differential pair of the differential amplifier component12is the odd row pixel10S_O or the even row pixel10S_E. In a case where the odd row pixel10S_O is the signal side pixel of the differential pair, the even row pixel10S_E becomes the reference side pixel of the differential pair. Meanwhile, in a case where the even row pixel10S_E is the signal side pixel of the differential pair, the odd row pixel10S_O becomes the reference side pixel of the differential pair. The odd row pixel10S_O and the even row pixel10S_E constituting the differential pair do not need to be the unit pixels10S of the adjacent pixel rows. However, since the correlation of the device variations becomes higher as the distance between the pixels constituting the differential pair becomes shorter, the characteristic variation may be decreased if the differential pair includes the odd row pixel10S_O and the even row pixel10S_E of the adjacent pixel rows.

<19. Configuration Example of Signal Switching Unit>

FIG. 25is a diagram showing a detailed configuration of the signal switching unit301along with the details of the differential amplifier component12, the odd row pixel10S_O, and the even row pixel10S_E.

InFIG. 25, the differential amplifier component12of the first configuration example shown inFIG. 3is employed as the differential amplifier component12. Both the odd row pixel10S_O and the even row pixel10S_E have the same configuration as that of the unit pixel10S shown inFIG. 3.

The signal switching unit301includes switches311to314which switch the terminals A and B. The switch311switches the column signal line41_E of the even row pixel10S_E to the signal side or the reference side of the differential amplifier component12. The switch312switches the column signal line41_O of the odd row pixel10S_O to the signal side or the reference side of the differential amplifier component12. The switch313switches the connection destination of the reset transistor103of the even row pixel10S_E to the reset voltage Vrst or the drain of the PMOS load152. The switch314switches the connection destination of the reset transistor103of the odd row pixel10S_O to the reset voltage Vrst or the drain of the PMOS load152.

An example ofFIG. 25shows a state in which the switches311to314all select the terminal A. In this case, the odd row pixel10S_O becomes the signal side of the differential pair to perform the same operation as that of the unit pixel10S ofFIG. 3and the even row pixel10S_E becomes the reference side of the differential pair to perform the same operation as that of the dummy pixel10D ofFIG. 3.

The reset control signal RST_S, the transfer control signal TRG_S, and the selection control signal SEL_S of the even row pixel10S_E at the reference side are controlled in the same manner as the reset control signal RST_D, the transfer control signal TRG_D, and the selection control signal SEL_D ofFIG. 4and the reset control signal RST_S, the transfer control signal TRG_S, and the selection control signal SEL_S of the odd row pixel10S_O at the signal side are controlled in the same manner as the reset control signal RST_S, the transfer control signal TRG_S, and the selection control signal SEL_S ofFIG. 4.

In contrast, in a case where the switches311to314all select the terminal B, the even row pixel10S_E becomes the signal side of the differential pair to perform the same operation as that of the unit pixel10S ofFIG. 3and the odd row pixel10S_O becomes the reference side of the differential pair to perform the same operation as that of the dummy pixel10D ofFIG. 3.

The signal switching unit301switches the terminals A and B of the switches311to314by, for example, the unit of row.

Also in the solid-state imaging device1of the above-described second embodiment, the original operation point of the differential amplifier can be adjusted to the optimal operation range located at the upside (the high potential side) in relation to the original operation point of the differential amplifier. As a result, it is possible to improve linearity by improving the conversion efficiency of the amplification transistor104.

Additionally, in the above-described second embodiment, a configuration in which the differential amplifier component12of the first configuration example shown inFIG. 3is employed as the differential amplifier component12has been exemplified, but it is needless to mention that the second to fifteenth configuration examples or other configurations (not shown) can be employed.

The solid-state imaging device1according to an embodiment of the present technology includes the pixel array unit11in which the first and second unit pixels are arranged and the differential amplifier component12which constitutes the differential amplifier along with the amplification transistor and the selection transistor of the first and second unit pixels. In the solid-state imaging device1of the first embodiment, the first unit pixel is the unit pixel10S and the second unit pixel is the dummy pixel10D. In the solid-state imaging device1of the second embodiment, the first unit pixel is the odd row pixel10S_O and the second unit pixel is the even row pixel10S_E.

The differential amplifier component12includes the resetting circuit which generates a difference in current flowing to each of the signal side and the reference side of the differential pair during the resetting period of resetting the signal charge of the FD. The resetting circuit is the resetting constant current circuit153(153L,153R) in the first to third configuration examples, the constant current source171and the switch172in the fourth to sixth configuration examples, the resetting PMOS transistor191in the seventh configuration example, the switch201and the resistor202in the eighth configuration example, the resetting PMOS transistor221and the switch222in the ninth and tenth configuration examples, and the resetting NMOS transistor241and the switch242in the eleventh configuration example. These resetting circuits are disposed between the node of the arbitrary voltage (Vbr1, Vbrr, Vdd, Vbrg, Vdd) and the source node of the NMOS transistor (271,272) or the drain node of the PMOS transistor (151,152) at the signal side or the reference side of the differential pair of the differential amplifier component12.

Since the resetting circuit performs a control of generating a difference in current flowing to each of the signal side and the reference side of the differential pair during the resetting period and allows the current flowing to each of the signal side and the reference side of the differential pair to be the same during the reading period, the operation point of the differential amplifier can be adjusted to the optimal operation point.

Additionally, the control of the resetting circuit may be performed inversely. That is, even in a case where the resetting circuit performs a control in which the currents flowing to the signal side and the reference side of the differential pair are the same during the resetting period and a difference in current is generated in the signal side and the reference side of the differential pair during the reading period, the operation point of the differential amplifier can be adjusted to the optimal operation point. For example, the same current flows to the signal side and the reference side of the differential pair when the resetting circuit is turned on (during the resetting period) while the transistor sizes (for example, W sizes) of the signal side and the reference side of the differential pair are different from each other and a difference in current is generated in the current flowing to each of the signal side and the reference side of the differential pair when the resetting circuit is turned off.

Thus, since the solid-state imaging device1includes the current generation circuit which generates a difference in current flowing to each of the signal side and the reference side of the differential pair during the resetting period or the reading period as in the above-described resetting circuit, the operation point of the differential amplifier can be adjusted to the optimal operation point.

<21. Application Example of Electronic Apparatus>

The present technology is not limited to the application to the solid-state imaging device. That is, the present technology can be applied to all electronic apparatuses using a solid-state imaging device for an image capturing unit (a photoelectric conversion unit) like an imaging apparatus such as a digital still camera or a video camera, a mobile terminal device having an imaging function, or a copying machine using a solid-state imaging device in an image reading unit. The solid-state imaging device may be in a form formed as a single chip or in a modular form having an imaging function in which an imaging unit and a signal processing unit or an optical system are packaged together.

FIG. 26is a block diagram showing a configuration example of an imaging apparatus which is an electronic apparatus according to an embodiment of the present technology.

An imaging apparatus400ofFIG. 26includes an optical unit401which is a lens group or the like, a solid-state imaging device (an imaging device)402which adopts the configuration of the solid-state imaging device1ofFIG. 1 or 24, and a digital signal processor (DSP) circuit403which is a camera signal process circuit. Further, the imaging apparatus400also includes a frame memory404, a display unit405, a recording unit406, an operation unit407, and a power supply unit408. The DSP circuit403, the frame memory404, the display unit405, the recording unit406, the operation unit407, and the power supply unit408are connected to one another via a bus line409.

The optical unit401takes incident light (image light) from a subject and forms an image on an imaging surface of the solid-state imaging device402. The solid-state imaging device402converts a light amount of the incident light formed as an image on the imaging surface by the optical unit401into an electric signal by the unit of pixel and outputs the electric signal as a pixel signal. As the solid-state imaging device402, the solid-state imaging device1ofFIG. 1 or 24, that is, the solid-state imaging device capable of adjusting the operation point (the operation range) of the differential amplifier from the original operation point of the differential amplifier to the optimal operation point can be used.

The display unit405includes, for example, a thin display such as a liquid crystal display (LCD) or an organic electro luminescence (EL) display and displays a moving image or a still image captured by the solid-state imaging device402. The recording unit406records a moving image or a still image captured by the solid-state imaging device402in a recording medium such as a hard disk or a semiconductor memory.

The operation unit407generates operation instructions for various functions of the imaging apparatus400under the operation of the user. The power supply unit408supplies power to supply targets like the DSP circuit403, the frame memory404, the display unit405, the recording unit406, and the operation unit407.

As described above, if the solid-state imaging device1according to the above-described embodiments is used as the solid-state imaging device402, it is possible to improve linearity by improving the conversion efficiency of the amplification transistor104. Thus, it is possible to improve the quality of the captured image even in the imaging apparatus400such as a video camera, a digital camera, and a mobile device camera for a cellular phone.

<Application Example of Image Sensor>

FIG. 27is a diagram showing an application example of an image sensor corresponding to the above-described solid-state imaging device1.

The image sensor including the configuration of the above-described solid-state imaging device1can be used for, for example, various cases of sensing visible light, infrared light, ultraviolet light, and X rays as below.Device used for capturing viewing image, such as digital camera or portable device with camera functionDevice used for traffic, such as vehicle sensors for capturing images at front, back, periphery, and inside of car for safe driving such as automatic stop and recognition of driver state, monitoring camera for monitoring traveling vehicle or road, and ranging sensors for measuring vehicle-to-vehicle distanceDevice used for home appliances such as TV, refrigerator, and air conditioner in order to capture gesture of user and operate device according to gestureDevice for medical care or healthcare, such as endoscope and device performing angiography by receiving infrared lightDevice for security, such as surveillance camera for preventing crime and camera for authenticating personDevice for cosmetics, such as skin measuring device for capturing skin and microscope for capturing scalpDevice for sports, such as wearable camera or action camera for sports applicationDevice for agriculture, such as camera for monitoring condition of fields and crops

Further, the present technology is not limited to the application to the solid-state imaging device that captures an image by detecting a distribution of an incident light amount of visible light and can be also applied to a solid-state imaging device that captures an image from a distribution of an incident light amount of infrared light, X-ray, or particle or all solid-state imaging devices (physical quantity distribution detection devices) such as finger print detection devices that capture an image by detecting other physical quantities such as a pressure or a static capacity as a broad meaning.

Further, the present technology is not limited to the solid-state imaging device and can be applied to all semiconductor devices including other semiconductor integrated circuits.

The embodiments of the present technology are not limited to the above-described embodiments and various modifications can be made without departing from the spirit of the present technology.

For example, as the pixel configuration of the pixel array unit11, a pixel configuration may be employed in which a charge storage unit is provided between the transfer transistor and the FD to temporarily store a charge generated by the PD and a global shutter operation simultaneously exposing all pixels is possible. Further, an FD sharing pixel configuration that shares the FD by the adjacent pixels can be also employed.

For example, in the above-described circuit configurations, it is also possible to realize a circuit configuration in which the polarity of the transistor (NMOS transistor and PMOS transistor) is switched. In that case, Hi and Lo are opposite signals for the control signal input to the transistor.

In the above-described embodiments, it has been described such that the reference signal is a slope signal in which the level (voltage) monotonically increases with the elapse of time, but the reference signal may be a slope signal in which the level (voltage) monotonously decreases with the elapse of time.

For example, a configuration in which all or a part of the above-described embodiments are combined can be employed.

Additionally, the effects described in this specification are merely examples and are not intended to be limiting and there may be effects other than those described in this specification.

Additionally, the present technology can have the following configuration.

An imaging device comprising:

a plurality of pixels including a first pixel and a second pixel;

a differential amplifier including a first amplification transistor, a second amplification transistor, and a first load transistor, the first load transistor being configured to receive a power source voltage;

a first signal line coupled to the first amplification transistor and the first load transistor;

a second signal line coupled to the second amplification transistor;

a first reset transistor configured to receive the power source voltage, a gate of the first reset transistor being coupled to the first load transistor,

wherein the first pixel includes a first photoelectric conversion element and the first amplification transistor, and the second pixel includes a second photoelectric conversion element and the second amplification transistor.

The imaging device according to (1), further comprising: a switch circuit coupled between the first reset transistor and the first signal line.

The imaging device according to (2), wherein the switch circuit connects one of a source and a drain of the first reset transistor to the first signal line during a reset operation of the first and second pixels such that the first signal line carries a larger current than the second signal line.

The imaging device according to (3), the switch circuit disconnects one of the source and the drain of the first reset transistor from the first signal line during a read operation of the first and second pixels such that the first signal line and the second signal line carry a same current.

The imaging device according to (1), further comprising: a second load transistor configured to receive the power source voltage and coupled to the second signal line.

The imaging device according to (5), wherein the first pixel includes a second reset transistor, and the second pixel includes a third reset transistor.

The imaging device according to (6), further comprising:

a third signal line and a fourth signal line coupled to a reset voltage source; and a signal switching unit to select one of the first pixel and the second pixel as a reference pixel and select the other one of the first pixel and the second pixel as an effective pixel through the first, second, third, and fourth signal lines.

The imaging device according to (7), wherein the signal switching unit includes:

a first switch between the first load transistor and the first amplification transistor; a second switch between the second load transistor and the second amplification transistor;

a third switch between the second reset transistor and the reset voltage source; and a fourth switch between the third reset transistor and the reset voltage source.

The imaging device according to (8), wherein each of the first, second, third and fourth switches are switchable between a first position and a second position.

The imaging device according to (9), wherein the signal switching unit causes the first, second, third, and fourth switches to be in the first position to select the first pixel as the reference pixel and the second pixel as the effective pixel, and wherein the signal switching unit causes the first, second third, and fourth switches to be in the second position to select the first pixel as the effective pixel and the second pixel as the reference pixel.

The imaging device according to (6), the first pixel is in an even numbered row of the plurality of pixels and the second pixel is in an odd numbered row of the plurality of pixels.

An imaging device comprising:

a first pixel including a first photoelectric conversion element, a first transfer transistor, and a first amplification transistor;

a second pixel including a second photoelectric conversion element, a second transfer transistor, and a second amplification transistor;

a first signal line coupled to the first amplification transistor;

a second signal line coupled to the second amplification transistor;

a first load transistor coupled to the first signal line, the first load transistor being configured to receive a power source voltage; and

a first reset transistor configured to receive the power source voltage, a gate of the first reset transistor being coupled to the first load transistor,

wherein one of a source and a drain of the first amplification transistor is coupled to one of a source and a drain of the second amplification transistor, and the other of the source and the drain of the first amplification transistor is coupled to the other of the source and the drain of the second amplification transistor.

The imaging device according to (12), further comprising:

a switch circuit coupled between the first reset transistor and the first signal line.

The imaging device according to (13), wherein the switch circuit connects one of a source and a drain of the first reset transistor to the first signal line during a reset operation of the first and second pixels such that the first signal line carries a larger current than the second signal line.

The imaging device according to (14), wherein the switch circuit disconnects one of the source and the drain of the first reset transistor from the first signal line during a read operation of the first and second pixels such that the first signal line and the second signal line carry a same current.

The imaging device according to (12), further comprising:

a second load transistor configured to receive the power source voltage and coupled to the second signal line, wherein the first pixel includes a second reset transistor, and the second pixel includes a third reset transistor;

a third signal line and a fourth signal line coupled to a reset voltage source; and

a signal switching unit to select one of the first pixel and the second pixel as a reference pixel and select the other one of the first pixel and the second pixel as an effective pixel through the first, second, third, and fourth signal lines.

a differential amplifier including:

a first load transistor coupled to a power source;

a second load transistor coupled to the power source;

a first amplification transistor of a first pixel;

a second amplification transistor of a second pixel;

a first signal line coupled to the first load transistor and the first amplification transistor; and

a second signal line coupled to the second load transistor and the second amplification transistor, wherein outputs of the first and second amplification transistors are connected to one another; and

a reset element coupled to the differential amplifier and to reset the first pixel with a first current on the first signal line and reset the second pixel on the second signal line with a second current during a reset operation.

The imaging device according to (17), wherein the reset element comprises a first reset transistor and a switch circuit coupled between the first reset transistor and the first signal line,

wherein the switch circuit connects one of a source and a drain of the first reset transistor to the first signal line during the reset operation such that the first current is larger than the second current, and

wherein the switch circuit disconnects one of the source and the drain of the first reset transistor from the first signal line during a read operation of the first and second pixels such that first current and the second current are the same.

The imaging device according to (18), further comprising:

a third signal line and a fourth signal line coupled to a reset voltage source; and

a signal switching unit to select one of the first pixel and the second pixel as a reference pixel and select the other one of the first pixel and the second pixel as an effective pixel through the first, second, third, and fourth signal lines.

The imaging device according to (19),

wherein the first pixel includes a second reset transistor, and the second pixel includes a third reset transistor,

wherein the signal switching unit includes:

a first switch between the first load transistor and the first amplification transistor;

a second switch between the second load transistor and the second amplification transistor;

a third switch between the second reset transistor and the reset voltage source; and

a fourth switch between the third reset transistor and the reset voltage source,

wherein each of the first, second, third and fourth switches are switchable between a first position and a second position, and

wherein the signal switching unit causes the first, second, third, and fourth switches to be in the first position to select the first pixel as the reference pixel and the second pixel as the effective pixel, and wherein the signal switching unit causes the first, second third, and fourth switches to be in the second position to select the first pixel as the effective pixel and the second pixel as the reference pixel.

A solid-state imaging device including:

a pixel array unit provided with first and second unit pixels each including a photoelectric conversion element configured to photoelectrically convert light incident to a pixel, a transfer transistor configured to transfer a signal charge photoelectrically converted by the photoelectric conversion element to an FD, a reset transistor configured to reset the signal charge of the FD, an amplification transistor configured to convert the signal charge stored in the FD into a voltage signal and output the voltage signal, and a selection transistor configured to select the pixel; and

a differential amplifier component constituting a differential amplifier together with the amplification transistor and the selection transistor of the first and second unit pixels,

in which the differential amplifier component includes a current generation circuit that generates a difference in current flowing to each of a signal side and a reference side of a differential pair.

The solid-state imaging device according to (21), in which the current generation circuit generates a difference in current flowing to each of the signal side and the reference side of the differential pair during a resetting period of resetting the signal charge of the FD.

The solid-state imaging device according to (21) or (22), in which the current generation circuit outputs a predetermined current to the signal side or the reference side of the differential pair.

The solid-state imaging device according to any of (21) to (23), in which the current generation circuit draws a predetermined current from the signal side or the reference side of the differential pair.

The solid-state imaging device according to any of (21) to (24), in which a different current flows to the current generation circuit between the resetting period and a reading period of reading a signal converted into a voltage by the FD.

The solid-state imaging device according to any of (21) to (25), in which the current generation circuit includes a switch and an on/off state of a switch changes between the resetting period and a reading period of reading a signal converted into a voltage by the FD.

The solid-state imaging device according to (26), in which the current generation circuit includes a resistor.

The solid-state imaging device according to (26), in which the current generation circuit includes a transistor having a gate to which a constant bias voltage is applied.

The solid-state imaging device according to (26), in which the current generation circuit includes a transistor and a gate of the transistor is connected to a drain of a PMOS transistor at a signal side or a reference side of the differential pair.

The solid-state imaging device according to any of (21) to (25), in which the current generation circuit includes a transistor and a voltage applied to a gate thereof changes between the resetting period and a reading period of reading a signal converted into a voltage by the FD.

The solid-state imaging device according to any of (21) to (30), in which the differential amplifier has a cascode structure.

The solid-state imaging device according to any of (21) to (31), in which the first unit pixel is a pixel disposed inside an effective pixel area and the second unit pixel is a pixel disposed outside the effective pixel area.

The solid-state imaging device according to any of (21) to (31), in which the first unit pixel is a pixel disposed in an odd row inside an effective pixel area and the second unit pixel is a pixel disposed in an even row inside the effective pixel area.

The solid-state imaging device according to (33), further including:

a signal switching unit configured to switch pixel signal output destinations of the first unit pixel and the second unit pixel to the signal side or the reference side of the differential pair.

The solid-state imaging device according to any of (21) to (34), in which the differential amplifier component includes the current generation circuit at both the signal side and the reference side of the differential pair.

The solid-state imaging device according to any of (21) to (35), in which the current generation circuit is disposed between a node of an arbitrary voltage and a source node of an NMOS transistor or a drain node of a PMOS transistor at the signal side or the reference side of the differential pair of the differential amplifier component.

A method of controlling a solid-state imaging device including: a pixel array unit provided with first and second unit pixels each including a photoelectric conversion element configured to photoelectrically convert light incident to a pixel, a transfer transistor configured to transfer a signal charge photoelectrically converted by the photoelectric conversion element to an FD, a reset transistor configured to reset the signal charge of the FD, an amplification transistor configured to convert the signal charge stored in the FD into a voltage signal and output the voltage signal, and a selection transistor configured to select the pixel; and a differential amplifier component constituting a differential amplifier together with the amplification transistor and the selection transistor of the first and second unit pixels,

in which a current generation circuit of the differential amplifier component generates a difference in current flowing to each of a signal side and a reference side of a differential pair.

An electronic apparatus including

a solid-state imaging device including:

a pixel array unit provided with first and second unit pixels each including a photoelectric conversion element configured to photoelectrically convert light incident to a pixel, a transfer transistor configured to transfer a signal charge photoelectrically converted by the photoelectric conversion element to an FD, a reset transistor configured to reset the signal charge of the FD, an amplification transistor configured to convert the signal charge stored in the FD into a voltage signal and output the voltage signal, and a selection transistor configured to select the pixel; and

a differential amplifier component constituting a differential amplifier together with the amplification transistor and the selection transistor of the first and second unit pixels,

in which the differential amplifier component includes a current generation circuit that generates a difference in current flowing to each of a signal side and a reference side of a differential pair.

REFERENCE SIGNS LIST