Semiconductor device

A semiconductor device includes a first electrode layer and a second electrode layer. The first electrode layer extends in a first direction. The second electrode layer extends in the first direction for a different length from the first electrode layer, and is symmetric with respect to a center line of the first electrode layer in a second direction. The second electrode layer defines a capacitor with the first electrode layer.

BACKGROUND

Generally, a deep trench capacitor (DTC) may be used as a replacement for a ceramic capacitor in a printed circuit board (PCB). However, a traditional DTC requires an additional landing area for a contact landing to a substrate.

DETAILED DESCRIPTION

FIG. 1Ais a cross-sectional view of a semiconductor device1having a symmetric structure, in accordance with some embodiments of the present disclosure. Referring toFIG. 1A, the semiconductor device1includes a first electrode layer12, a dielectric layer16and a second electrode layer14. The first electrode layer12, the dielectric layer16and the second electrode layer14together define (or form) a capacitor.

The dielectric layer16is disposed between the first electrode layer12and the second electrode layer14, and extends in the first direction X for a length different from the first electrode layer12. For clear of illustration, the thickness of the dielectric layer16is exaggerated. In fact, the dielectric layer16is very thin with respect to the first and second electrode layers12and14. In addition, the dielectric layer16partially covers the first electrode layer12. Moreover, the dielectric layer16is substantially symmetric with respect to a center line A-A′ of the first electrode layer12in a second direction Y different from the first direction X. Generally, the center line A-A′ crosses the center of the first electrode layer12. In some embodiments, the first direction X is orthogonal to the second direction Y.

The second electrode layer14is disposed on the dielectric layer16, and extends in the first direction X for a length different from the first electrode layer12, but substantially the same as the dielectric layer14. In the present embodiment, the second electrode layer14is shorter than the first electrode layer12. In that case, the second electrode layer16partially covers the first electrode layer12, and exposes a terminal portion123and another terminal portion125of the first electrode layer12.

The terminal portion123of the first electrode layer12includes a surface122, a sidewall124and a corner126connecting the surface122with the sidewall124. The surface122of the terminal portion123, for example, serves as a land to allow an interconnect feature (not shown), such as contact, to place thereon. To allow and facilitate the placement, the length of the surface122of the terminal portion123in the first direction X is long enough to accommodate the interconnect feature. In some embodiments, the length ranges from approximately 10 angstrom to approximately 10,000 angstrom.

Likewise, due to symmetricity, the terminal portion125of the first electrode layer12includes a surface127, a sidewall (not numbered) and a corner (not numbered) connecting the surface127with the sidewall. The function and spatial features of the terminal portion125are similar to those of the terminal portion123and therefor are not discussed.

Please note that it is not intended for the disclosure to be limited to the examples shown above. One skilled in the art can apply the principles of the present disclosure to other applications as well without departing from the scope of the disclosure. In different applications, the surface122of the terminal portion123can have different lengths.

Furthermore, the second electrode layer14is also substantially symmetric with respect to the center line A-A′ of the first electrode layer12. As a result, the terminal portions123and125, exposed by the second electrode layer14, are substantially the same in size. Accordingly, the surface122of the terminal portion123is substantially the same as the surface127of the terminal portion125in length.

FIG. 1Bis a zoom-in diagram for clearly showing the profile of the corner126of the first electrode layer12shown inFIG. 1A, in accordance with some embodiments of the present disclosure. Referring toFIG. 1B, the corner126has a rounded shape as a result of a manufacturing method according to embodiments of the present disclosure, which will be discussed in detail below with reference toFIGS. 2A to 2J.

FIGS. 2A to 2Jare diagrams showing a method of manufacturing the semiconductor device1shown inFIG. 1A, in accordance with some embodiments of the present disclosure. Referring toFIG. 2A, a semiconductor structure25is provided. The semiconductor structure25includes a first conductive layer22, an insulating layer26on the first conductive layer22, and a second conductive layer24on the insulating layer26. A layer derivative from the first conductive layer22serves as the first electrode layer12of the capacitor shown inFIG. 1A. Similarly, a layer derivative from the second conductive layer24serves as the second electrode layer14of the capacitor shown inFIG. 1A. Moreover, a layer derivative from the insulating layer26serves as the dielectric layer16of the capacitor shown inFIG. 1A.

After the semiconductor structure25is provided, a photoresist layer28is formed on the second conductive layer24by, for example, a priming process, a coating process and a soft bake process, which are performed in order. In the present embodiment, the photoresist layer28includes a positive photoresist. However, the disclosure is not limited thereto. In other embodiments, the photoresist layer28includes a negative photoresist.

Afterwards, a photomask29having a pattern is provided. Light, such as ultraviolet (UV) light, radiates the photoresist layer28via the photomask29. Accordingly, the pattern of the photomask29is transferred onto the photoresist layer28. In the present embodiment, since the photoresist layer28is a positive photoresist, a portion of the photoresist layer28exposed to the light remains, and other portions are removed.

During the whole process for manufacturing the semiconductor device1, only one photomask (i.e., the photomask29shown inFIG. 2A) is required. Specifically, the photoresist layer28is not removed until the whole process for manufacturing the semiconductor device1shown inFIG. 1Ais finished. In the following process, the first conductive layer22, the insulating layer26and the second conductive layer24are patterned without removing the photoresist layer28. Therefore, there is no need to introduce another photoresist layer having a different pattern from the photoresist layer28. Specifically, the first conductive layer22, the insulating layer26and the second conductive layer24are patterned by using the photoresist layer28and its derivative photoresist layer as a mask, which will be described and illustrated in detail with reference toFIGS. 2C to 2J. As a result, a lot of operations for preparing a lot of masks can be omitted, and therefore the manufacturing process is simplified and cost efficient.

Referring toFIG. 2B, a first patterned photoresist layer280, having a first sidewall281, a second sidewall284and a surface286, is formed on the second conductive layer24by, for example, a development process on the photoresist layer28, followed by a hard bake process. The first patterned photoresist layer280exposes a first terminal portion241and a second terminal portion243of the second conductive layer24. In an embodiment, the second terminal portion243and the first terminal portion241are symmetrical to each other with respect to the center line A-A′.

Referring toFIG. 2C, a first electrode20and a second electrode27are provided at the opposite sides of the semiconductor structure25. The first electrode20is biased by a voltage source23, and the second electrode27is biased by a voltage source26. The voltage source23and the voltage source26provide a differential voltage in an etching process. For example, the voltage source23provides a voltage of 5 volts, and the voltage source26provides a voltage of 0 volts.

In the etching process, an etch chemistry (not shown), such as gas, is introduced and the voltage provided by the voltage source23is applied to generate plasma (i.e., the ionized gas atoms). Afterwards, with an electric field established between the first electrode20and the second electrode27, the ionized gas atoms bombard the second conductive layer24, using the first patterned photoresist layer280as a mask, and thereby anisotropically etching the second conductive layer24. Moreover, etching selectivity can be well-controlled, such that the first patterned photoresist layer280is only etched slightly.

Referring toFIG. 2D, a first patterned second conductive layer240is formed by, for example, a plasma etching process as discussed in the illustrative embodiment ofFIG. 2C, removing the first and second terminal portions241and243of the second conductive layer24. As a result, terminal portions261and263of the insulating layer26that were covered by the first and second terminal portions241and243of the second conductive layer24are exposed.

Referring toFIG. 2E, a first patterned insulating layer260is formed by, for example, a plasma etching process as discussed in the illustrative embodiment ofFIGS. 2C and 2D, using the first patterned photoresist layer280as a mask. The plasma etching process removes exposed portions261and263of the insulating layer26.

Selectivity of the plasma etching process can be well controlled, such that the first patterned photoresist layer280is only slightly etched when the insulating layer26is etched. Moreover, a detection approach can be applied, such that the etching process stops until portions220and222of the first conductive layer22under the portions261and263of the insulating layer26are exposed.

Referring toFIG. 2F, the second electrode27is not biased, and only the first electrode20facing the first patterned photoresist layer280is still biased. An etch chemistry (not shown), such as gas, is introduced and ionized by an electromagnetic (EM) field established by the biased first electrode20. The ionized gas atoms trim the surface286, the first sidewall281and the second sidewall284of the first patterned photoresist layer280by, for example, an etching process. In an embodiment, the first patterned photoresist layer280is etched isotropically. In an embodiment, the plasma is inductive coupled plasma (ICP).

Unlike the stage shown in the illustrative embodiment ofFIG. 2C, in the present stage, because the second electrode27is not biased, an ion bombardment would generally not occur.

Referring toFIG. 2G, a second patterned photoresist layer282is formed on the first patterned second conductive layer240by, for example, an etching process as discussed in the illustrative embodiment ofFIG. 2F. The first sidewall281, the second sidewall284and the surface286of the first patterned photoresist layer280after the trimming process are reduced by substantially a length D1.

A terminal portion245and a terminal portion247of the first patterned second conductive layer240are exposed by the second patterned photoresist layer282.

Referring toFIG. 2H, the present stage is similar to the stage described and illustrated with reference toFIG. 2C. An etch chemistry (not shown), such as gas, is introduced and the voltage provided by the voltage source23is applied to generate plasma (i.e., the ionized gas atoms). Afterwards, with an electric field established between the first electrode20and the second electrode27, the ionized gas atoms bombard the first patterned second conductive layer240and the first conductive layer22, using the second patterned photoresist layer282as a mask. Specifically, the ionized gas atoms bombard the terminal portions245and247of the first patterned second conductive layer240and the terminal portions220and222of the first conductive layer22. Because the terminal portions245and247of the first patterned second conductive layer240are not masked by any photoresist layer, the etching process performed on the terminal portions245and247is called “a blanket etching process.”

In the present disclosure, the second patterned photoresist layer282, which is derivative from the photoresist layer28, is used as a mask for patterning the first patterned second conductive layer240. The method of the present disclosure does not require any other photoresist layer. Therefore, the manufacturing process is simplified.

Referring toFIG. 2I, the present stage is similar to the stage described and illustrated with reference toFIG. 2E. A second patterned second conductive layer14is formed by, for example, an etching process on the first patterned second conductive layer240, exposing terminal portions265and267of the first patterned insulating layer260. The second patterned second conductive layer14serves as the second electrode layer14shown inFIG. 1A.

Similar to the description in the illustrative embodiment ofFIG. 2H, in the present disclosure, the second patterned photoresist layer282, which is derivative from the photoresist layer28, is used as a mask for patterning the first patterned insulating layer260. The method of the present disclosure does not require any other photoresist layer. Therefore, the manufacturing process is simplified and cost efficient.

Referring toFIG. 2J, a second patterned insulating layer16is formed on the first patterned first conductive layer12by, for example, an etching process on the first patterned insulating layer260, exposing terminal portions123and125of the first patterned first conductive layer12. In some embodiments, the first patterned insulating layer260is etched anisotropically.

During the etch of the first patterned insulating layer260, a corner126and a surface122of the terminal portion123are also etched. Before the corner126is etched, the profile of the corner126is, for example, a right angle, while the surface122is a substantially planar surface. That is, the corner126and the surface122have different profiles. The profiles relates to the etching rate, which will be described in detail with reference toFIGS. 3A to 3C. The corner126is etched at a higher etching rate than the surface122. As a result, the corner126has a rounded shape.

In the embodiments, the terminal portions245and247of the first patterned second conductive layer240and the terminal portions265and267of the second patterned insulating layer260are not masked. As a result, the corner126of the terminal portion123of the first patterned first conductive layer12has a rounded shape. The corner126having a rounded shape reflects that a semiconductor device is manufactured according to the method of the present disclosure.

In some existing manufacturing processes, to form a ladder shape, no trimming process as mentioned in the illustrative embodiment ofFIGS. 2F and 2Jare taken. Rather, a patterned photoresist layer (such as the first patterned photoresist layer280) is removed. Afterwards, another patterned photoresist layer is formed on the first conductive layer22and the first patterned second conductive layer240. The other patterned photoresist layer fully encapsulates the first patterned second conductive layer240and the first patterned insulating layer260. Accordingly, a terminal portion of the first conductive layer22is exposed. Since the first patterned second conductive layer240and the first patterned insulating layer260are encapsulated, a blanket etching does not occur. As a result, a corner (for example, the corner126) does not have a rounded shape after the etching process.

Moreover, referring back toFIG. 2A, in the present embodiment, the photomask29is aligned to the center line A-A′ of the first conductive layer22. As a result, referring toFIG. 2B, the first patterned photoresist layer280is symmetric with respect to the center line A-A′ of the first conductive layer22in structure. Accordingly, the first terminal portion241is the same as the second terminal portion243in length. Since, referring toFIG. 2D, the first and second terminal portions241and243have the same in size and, referring toFIG. 2F, the patterned photoresist layer282is trimmed for the same length at the first and second sidewalls280and282, the terminal portions245and247are the same in size, resulting in that, referring toFIG. 2H, the terminal portions220and222are the same in size. As a result, the semiconductor device1is symmetric in structure.

In another embodiment, referring toFIG. 2A, the photomask29is not aligned to the center line A-A′ of the first conductive layer22. The photomask29is freely arranged over the semiconductor structure25. Referring toFIG. 2B, the terminal portions241and243are not the same in size, resulting in that referring toFIG. 2Dthe terminal portions220and222are not the same in size. However, Referring toFIG. 2G, the terminal portions220and222, which are not the same in size, are removed. As a result, the semiconductor device1is still symmetric. That is, if a semiconductor device is manufactured according to the method of the present disclosure, no matter the photomask29is aligned to the center line of a bottom layer (such as the first conductive layer22), the semiconductor device can still have a symmetric structure. As a result, the manufacturing process is not confined to be performed with the relatively high accuracy on the aligning process. The manufacturing process is simplified.

Additionally, referring toFIG. 2H, for convenience of illustration, the first conductive layer22is a little longer than the first patterned second conductive layer240. In fact, the first conductive layer22is a virgin material, which means that the first conductive layer22has not patterned yet. Therefore, the first conductive layer22is quite longer than the first patterned second conductive layer240. In that case, the profile formed by the first conductive layer22and the first patterned second conductive layer240cannot be regarded as a ladder shape. To form a ladder shape, the first conductive layer22needs to be patterned.

In some existing manufacturing processes, in order to form a ladder structure, as mentioned above, another patterned photoresist layer is planned to be formed on the first conductive layer22, and encapsulates the patterned second conductive layer240. In order to make the semiconductor device symmetric, a photomask must be perfectly aligned to the center of the first conductive layer22. However, in practice, it is difficult to precisely align the photomask to the center of the first conductive layer22. If the photomask is not enough precisely aligned to the center of the first conductive layer22, a first portion and a second portion of the first conductive layer22masked by the other patterned photoresist layer are different in size. Afterwards, in the etching process, two terminal portions of the first conductive layer22exposed by the other patterned photoresist layer are removed, and the other patterned photoresist layer is subsequently stripped. A semiconductor device defined by the patterned first electrode layer and the patterned second electrode layer has two ladders at opposite sides. A surface of the first portion serves as a surface of one ladder, and a surface of the second portion serves as a surface of another ladder. As mentioned above, the surfaces of the first and second portion are not symmetrical, resulting in two ladders of different sizes. That is, such semiconductor device is not symmetric with respect to the patterned first electrode layer.

FIGS. 3A to 3Care diagrams for explaining relationship between etching rate and etch angle, in accordance with some embodiments of the present disclosure. Referring toFIG. 3A, the horizontal axis represents an etch angle ranging from approximately 0 degree to approximately 90 degree. The etch angle refers to an angle between a direction in which an object such as an ionized particle moves and a normal direction of a surface upon which the object impinges. The vertical axis represents the etching rate.FIG. 3Ashows that the etching rate is relatively fast at the angle of 80 degrees, and is relatively slow at the angle of 0 degree. The etching rate is different as the etch angle is different. The above values in degree are only for exemplary, and the present disclosure is not limited thereto.

Referring toFIG. 3B, an object30moves in a direction substantially parallel to the normal direction of a surface32. As a result, the angle is approximately 0 degree. Contrarily, referring toFIG. 3C, the object30moves in a direction substantially orthogonal to the normal direction of the surface32. As a result, the angle is approximately 90 degrees. Referring back toFIG. 2J, the corner126after etch has a rounded shape due to a higher etching rate than the surface122.

FIG. 4is a cross-sectional view of a semiconductor device4, in accordance with some embodiments of the present disclosure. Referring toFIG. 4, the semiconductor device4includes a deep trench capacitor (DTC) defined by a first dielectric layer40, a first electrode layer42, a second dielectric layer44and a second electrode layer46. The first electrode layer42and the second electrode layer46are coupled to an interconnect feature418in, for example, a metal-1 layer, via an interconnect feature414and an interconnect feature416, respectively. A portion of the DTC is formed in a well412in a substrate410.

The DTC is symmetric in structure with respect to a center line B-B′ of any one of the first dielectric layer40, the first electrode layer42, the second dielectric layer44and the second electrode layer46. Specifically, a terminal portion421and a terminal portion424of the first electrode layer42are exposed by the second electrode layer46. The terminal portion421and the terminal portion424are the same in structure (or in size).

The terminal portion421has a sidewall420, a surface423and a corner422connecting the sidewall420with the surface423. The surface423of the terminal portion421serves as a land to allow the interconnect feature414, such as contact, to place thereon. To allow and facilitate the placement, the surface423is required to be larger in length than the surface of the interconnect feature414. In some embodiments, the surface423of the terminal portion421ranges from approximately 10 angstroms to approximately 10,000 angstroms. Moreover, the corner422has a rounded shape. The surface423of the terminal portion421and a surface (not labeled) of the terminal portion424has the substantially same length D3.

The symmetric structure of the DTC and the corner422having a rounded shape reflect that the DTC is manufactured by the process described and illustrated with reference toFIGS. 2A to 2J. That manufacturing process is simplified and cost efficient.

FIG. 5is a cross-sectional view of a semiconductor device5, in accordance with some embodiments of the present disclosure. Referring toFIG. 5, the semiconductor device5is similar to the semiconductor device1described and illustrated with reference toFIG. 1Aexcept that, the semiconductor device5includes a first layer52of a first material and a second layer54of a second material different from the first material.

The second layer54is disposed on the first layer52, and extends in a first direction X for a different length from the first layer52. The second layer54exposes a terminal portion521and a terminal portion523of the first layer52. The second layer54is symmetric with respect to a center line C-C′ of the first layer52. As a result, the terminal portion521and the terminal portion523are substantially the same in structure. That is, a surface522of the terminal portion521and a surface525of the terminal portion are substantially the same in size.

Moreover, the terminal portion521has a surface522, a sidewall524and a corner526connecting the surface522with the sidewall524. The corner526has a rounded shape. Furthermore, the terminal portion525also has a corner (not labeled) having a rounded shape.

The symmetric structure of the semiconductor device5and the corner526having a rounded shape can evidence that the semiconductor device6is manufactured by the process described and illustrated with reference toFIGS. 2A to 2J.

FIG. 6is a cross-sectional view of a semiconductor structure60of a semiconductor device6, in accordance with some embodiments of the present disclosure. Referring toFIG. 6, the semiconductor device6is similar to the semiconductor device5described and illustrated with reference toFIG. 5except that, the semiconductor structure60is a bulk including a first portion62and a second portion64.

The first portion62extends in a first direction X. The second portion64protrudes, in a second direction Y, from a center portion of the first portion62. The second portion64exposes a terminal portion621and a terminal portion623of the first portion64. Additionally, the second portion64is symmetric with respect to a center line D-D′ of the first portion62in the second direction Y. As a result, the terminal portion621and the terminal portion623are substantially the same in structure. That is, a surface622of the terminal portion621and a surface625of the terminal portion623are substantially the same in size.

Moreover, the terminal portion621has a surface622, a sidewall624and a corner626connecting the surface622with the sidewall624. The corner626has a rounded shape. Furthermore, the terminal portion623also has a corner (not labeled) having a rounded shape.

The symmetric structure of the semiconductor structure60and the corner626having a rounded shape can evidence that the semiconductor structure60is manufactured by the process described and illustrated with reference toFIGS. 2A to 2J.

Some embodiments have one or a combination of the following features and/or advantages. In some embodiments, a semiconductor device includes a first electrode layer and a second electrode layer. The first electrode layer extends in a first direction. The second electrode layer extends in the first direction for a different length from the first electrode layer, and is symmetric with respect to a center line of the first electrode layer in a second direction. The second electrode layer defines a capacitor with the first electrode layer.

In some embodiments, a semiconductor device includes a structure a first portion and a second portion. The first portion extends in a first direction. The second portion protrudes, in a second direction, from a center portion of the first portion, and is symmetric with respect to a center line of the first portion in the second direction.

In some embodiments, a method includes providing a semiconductor structure including a first conductive layer and a second conductive layer over the first conductive layer; providing a photoresist layer on the second conductive layer; forming a first patterned photoresist layer by patterning the photoresist layer; patterning the second conductive layer as a first patterned second conductive layer by using the first patterned photoresist layer as a mask; forming a second patterned photoresist layer by trimming the first patterned photoresist layer; and patterning the first conductive layer as a first patterned conductive layer, and the first patterned second conductive layer as a second patterned second conductive layer by using the second patterned photoresist as a mask.