One embodiment provides a phase-locked loop (PLL), in which a sequencer controls a loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of a first resistance change device in the loop filter is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority from Japanese Patent Application No. 2011-166073 filed on Jul. 28, 2011, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a phase-locked loop (PLL).

BACKGROUND

PLLs are used to accurately obtain various frequencies needed in systems. PLLS are necessarily mounted on general digital large-scale integration (LSI) circuits, such as a central processing unit (CPU) processor, a microcomputer, a digital system-on-chip (SoC), a baseband-processor, and a field programmable gate array (FPGA). The uses of PLLs include keeping generating a constant frequency as in the case of the clock of a microcomputer, and frequently changing frequencies as in the case of wireless communication.

Conventionally, PLLs have been able to substantially meet required specifications only by stably being operated. It has been sufficed that PLLs can obtain high-precision output with less frequency variation and less error. However, in recent years, there has been increased a demand for high-speed response, in addition to a demand for appropriate spectrum purity, i.e., less spurious-signal and less phase noise. More specifically, in digital communication/broadcast, high-speed frequency switching PLLs are required. In the case of the use of frequently switching frequencies, a response characteristic on the time axis, which is difficult to perceive from a frequency characteristic, becomes problematic.

In addition, in order to reduce the electric-power consumption of LSIs, a normally-off type computer has been proposed. In the normally-off type computer, electric-power supplied to each circuit is frequently interrupted. When electric-power is interrupted, a PLL loses a stable operation state. When the PLL is powered again, a time-delay at least in the order of several milliseconds (ms) is caused until an operation of the PLL is stabilized. Although it can be considered to exclude the PLL from targets of the interruption of the supply of electric-power thereto, the consumption electric-current of the PLL is in the order of 10 milliamperes (mA). Thus, if the PLL is excluded from targets of the interruption of the supply of electric-power, the power consumption thereof cannot sufficiently be reduced. If the PLL is designed by placing importance only on the speed-up of the PLL, an output frequency thereof is unstable. Thus, it is difficult to apply the PLL in applications. Consequently, a PLL with stability and fast response capability has been desired.

DETAILED DESCRIPTION

One embodiment provides a phase-locked loop (PLL), including: a phase detector configured to detect a phase difference between a reference signal and a feedback signal and output a first signal based on the phase difference; a charge pump configured to generate electric-current based on the first signal; a loop filter connected to the charge pump and output a second signal converted from the electric current, the loop filter having a first resistance change device; a voltage-controlled oscillator (VCO) configured to control an output frequency thereof according to the second signal input thereto from the loop filter; a frequency divider configured to perform frequency-dividing of an output signal of the VCO and to generate a feedback signal to be input to the phase detector; and a sequencer configured to control the loop filter, wherein the sequencer controls the loop filter such that, when a signal indicating turning-off of a power supply of the PLL is input thereto, or when a signal indicating turning-on of the power supply of the PLL is input thereto, a resistance value of the first resistance change device is a first resistance value, and that, after the PLL is stabilized, the resistance value of the first resistance change device is a second resistance value which is higher than the first resistance value.

First Embodiment

Hereinafter, an embodiment is described with reference to the drawings.FIG. 1illustrates a PLL according to the present embodiment. The PLL includes a phase detector10, a charge pump20, a loop filter30, a VCO40, a frequency divider50, a sequencer60, multiplexers70, and switches80.

The PLL generates a signal fvcohaving a frequency which is N-times that of a reference signal fref. A reference signal frefand a feedback signal fdivare input to the phase detector10that compares the phases of the reference signal frefand the feedback signal fdivwith each other. Then, if the phase of the feedback signal fdivadvances, the phase detector10outputs a voltage drop signal to the charge pump20via the multiplexer70. If the phase of the feedback signal fdivlags, the phase detector10outputs a boost signal to the charge pump20via the multiplexer70.

The charge pump20is driven, based on a signal output from the phase detector10and input thereto via the multiplexer70, and supplies electric-current in a boost direction or a voltage drop direction. Electric-current generated in the charge pump20is input to the loop filter30.

The loop filter30converts electric-current generated at the charge pump20into a power-supply voltage to be applied to the VCO40. Then, the loop filter30inputs the power-supply voltage to the loop filter30. The detailed configuration of the loop filter30is described below with reference toFIG. 3. The VCO40is an oscillating circuit that controls an output frequency according to a voltage input thereto from the loop filter30. An output of the VCO40is made as that of the PLL, and input to the frequency divider50via the switch80.

The frequency divider50outputs a signal input thereto by changing the frequency of the input signal into an integral multiple thereof. Generally, the frequency division number of the frequency divider50is variable. For example, if the frequency division number of the frequency divider50is changed from 250 to 300 during an operation thereof in which the frequency of the reference signal frefis 1 mega-hertz (MHz), the frequency of the output signal fvcochanges from 250 MHz to 300 MHz.FIG. 2illustrates change of the frequency of the output signal fvcoof the PLL. Ringing of a response characteristic occurs since the frequency division number is changed until the frequency of the output signal changes. Thus, it takes time until the frequency of the output signal of the PLL becomes a target frequency. A state in which the difference between the frequency of the output signal of the PLL and the target frequency is within a predetermined range (±Δf) is referred to as a state in which the PLL is locked up (i.e., stabilized). A state in which the difference therebetween exceeds the predetermined range is referred to as an unlocked state. An unlocked state is caused, e.g., when the target frequency or the reference frequency is changed by a request of a processor, or due to the influence of noise. The difference between the frequency of an output signal of the PLL and the target frequency exceeds the predetermined range not only when the PLL is in an unlocked state, but when the power supply for the PLL is turned on again after once turned off.

A delay caused until a PLL is stabilized is due to the fact that the PLL includes a feedback loop. The transfer function of the closed loop of the PLL is expressed by the following function H(s).

Time taken to stabilize the frequency of an output signal fvcoof the PLL is influenced by the time constant of the loop filter30. The change ωout(=2πfvco) of the angular frequency of an output signal fvcoof the PLL is given by the following expressions.

ω⁡(t)=A[1-ⅇ-ζωn⁢t⁢{cos⁡(ωn⁢1-ζ2⁢t)+ωn1-ζ2⁢sin⁡(ωn⁢1-ζ2⁢t)}]=A⁡[1-ωn1-ζ2⁢sin⁡(ωn⁢1-ζ2⁢t+θ)]⁢⁢θ=tan-1⁢1-ζ2ωn[Expression⁢⁢2]
A frequency step-response is a function that oscillates with a period given by the following expression, and attenuates at a time constant of (ζωn)−1.
ωn√{square root over (1−ζ2)}  [Expression 3]
To reduce the lock-up time of the PLL, it is advisable to maximize a value of ζωn. The value of ζωnis given by the following expression. Thus, the filter time constant of the loop filter30affects the lock-up time of the PLL.

However, if the damping constant ζ is simply increased, the cutoff frequency ωLPFd of the loop filter becomes high, so that phase noise in an output signal fvcoof the PLL is increased. In addition, a spurious-phenomenon occurs, in which a frequency component of the reference signal frefis mixed into the output signal fvco. Accordingly, a stable output that is a basic requirement specific of the PLL cannot be achieved.

Thus, when the PLL is unlocked, or when the power supply of the PLL is turned on, the time constant of the loop filter30is set to be small. After the PLL is locked up, the time constant of the loop filter30is set to be large. That is, when the PLL is unlocked, or when the power supply of the PLL is turned on, the resistance of the loop filter30is set to be low. After the PLL is locked up, the resistance of the loop filter30is set to be high. Incidentally, the following description is made by assuming that when the power supply of the PLL is turned on, the time constant of the loop filter30is set to be small (that is, the resistance of the loop filter30is set to be low). However, the PLL can be configured such that, in the case of turning off the power supply of the PLL, the turning-off of the power supply is performed after the time constant of the loop filter30is set to be small, so that when the PLL is activated, the PLL is put into a state in which the time constant is small.

According to the present embodiment, not only when the unlocked state of the PLL including the loop filter30is detected, but when the turning-on (or turning-off) of the power supply of the PLL is detected, the resistance of the loop filter30is set to be small. Thus, the PLL can be configured such that after the power supply of the PLL is turned on, the time constant of the loop filter30is set at a small value before the difference between the frequency of the output signal of the PLL and the target frequency is compared with the predetermined range. Consequently, after the power supply is turned on, the PLL can be brought into a lockup state more quickly.

Thus, in order to control the time constant of the loop filter30, the sequencer60, the multiplexers70, and the switches80are provided in the PLL. The loop filter30is configured, as illustrated inFIG. 3.

A signal Control is input to the sequencer60in a case where an unlocked state occurs (i.e., the reference frequency is changed, or the frequency division number of the frequency divider50is changed) when an external control circuit (not shown) makes a power-off request, or where the lockup state of the PLL is detected. The detection of the lockup state is performed by a lockup detector (not shown). Information represented by the signal Control includes the reference frequency, the frequency division number, and other setting items. The sequencer60transmits control signals to the loop filter30, the multiplexers70, and the switches80, based on the signal Control. Thus, the time constant of the loop filter30is adjusted. In an example illustrated inFIG. 3, the sequencer60controls the loop filter30by generating, from the signal Control, a signal Normal indicating whether writing to a resistance change type device (briefly, resistance change device)31is performed, a signal Write “H” indicating whether the resistance change type device31is set in a high-resistance state, and a signal Write “L” indicating whether the resistance change type device31is set in a low-resistance state.

As illustrated inFIG. 3, the loop filter30includes the resistance change type device31, switches32ato32econtrolled by the sequencer60, and a capacitor33.

Each of the switches32ato32eis a switch configured using an n-metal-oxide-semiconductor (nMOS) and a p-metal-oxide-semiconductor (pMOS). The switches32aand32care connected to the charging side of the charge pump20. The switches32band32dare connected to the discharging side of the charge pump20. In addition, the switches32aand32bare connected to each other. The switches32cand32dare connected to each other. Incidentally, inFIG. 3, a signal applied to the nMOS of each of the switches32ato32eis shown, while the drawing of a signal applied to the pMOS of each of the switches32ato32eis omitted. The reversal value of a value represented by a signal input to each nMOS is applied to an associated pMOS.

The resistance change type device31is, e.g., a magnetic tunnel junction (MTJ) of a spin torque transfer random access memory (STT-RAM), a phase change material of a phase change memory (PCM), a resistance change element of a resistance random access memory (ReRAM), a resistance change memory utilizing resistance change due to a field effect, or an ion memory. Hereinafter, a description is made by assuming that the resistance change type device31is implemented according to an electric-current writing method. The resistance change type device31has one terminal connected to the switches32aand32b, and the other terminal connected to the switches32cand32d.

The resistance change type device according to the electric-current writing method is a device whose resistance value is set by applying a predetermined electric-current between the terminals of the device. The resistance change type device according to the electric-current writing method is put into a low-resistance state or a high-resistance state, according to the direction of electric-current applied to the device. This embodiment is described by assuming that when electric-current flows from the terminal of the resistance change device31, which is connected to the switches32cand32d, to the terminal thereof connected to the switches32aand32b, the resistance change device31is put into the low-resistance state, and that when electric-current flows to the terminal of the resistance change device31, which is connected to the switches32cand32d, from the terminal thereof connected to the switches32aand32b, the resistance change device31is put into the high-resistance state.

When the PLL is unlocked, or when the power supply of the PLL is turned on, the sequencer60sets the levels of the signals Normal, Write “H”, and Write “L” at “L”, “L”, and “H”, respectively. The signals Write “H” and Write “L” are passed through delay devices, ORed with the signal Normal, and input to the switches32aand32b, respectively. The signal Write “H” is input to the switch32cvia the delay device. The signal Write “L” is input to the switch32dvia the delay device. The signal Normal is input to the switch32e.

Then, the switches32band32care turned on, while the switches32a,32d, and32eare turned off. Thus, as indicated by a dashed line inFIG. 4, electric-current flows through the switch32c, the resistance change device31, and the switch32b. The magnitude of electric-current can be adjusted according to the length of a pulse input to the charge pump20. If programmed electric-current is applied as indicated by the dashed line inFIG. 4, the resistance change device31is brought into a low-resistance state.

On the other hand, when the PLL is locked up, the sequencer60sets the levels of the signals Normal, Write “H”, and Write “L” at “L”, “H”, and “L”, respectively. Then, the switches32aand32dare turned on, while the switches32b,32c, and32eare turned of Thus, as indicated by a dashed line inFIG. 5, electric-current flows, which passes through the switch32a, the resistance change device31, and the switch32d. If the programmed electric-current is applied in the direction indicated by the dashed line inFIG. 5, the resistance change device31is brought into a high-resistance state.

If the resistance change device31is in the low-resistance state, the time constant of the loop filter30is small, as compared with that thereof in the high-resistance state. The cutoff frequency ωLPFwhich is the reciprocal of the time constant of the loop filter30is large. Thus, the damping constant becomes large. Accordingly, in the low-resistance state, the PLL can quickly be converged, as compared with that in the high-resistance state. However, in the high-resistance state, the PLL can stably be operated by suppressing phase noise and spurious signals, as compared with that in the low-resistance state.

In the normal state in which the resistance value of the resistance change device31is not changed, the sequencer60sets the levels of the signals Normal, Write “H”, and Write “L” at “H”, “L”, and “L”, respectively. Then, the switches32a,32b, and32eare turned on, while the switches32cand32dare turned off. Thus, as indicated by dashed lines inFIG. 6, electric-current can be caused to flow through the switch32a, the resistance change device31, and the switch32e. Alternatively, electric-current can be caused to flow through the switch32e, the resistance change device31, and the switch32b. That is, according to an output of the phase detector10, charging or discharging is performed by the charge pump20, so that a voltage-level applied to the VCO40is charged or discharged via the loop filter30to or from the level of the electric-potential VVCOof the VCO40.

At that time, the charge pump20performs only charging or discharging. Thus, the electric-current caused to flow to the resistance change device31is less in magnitude than the programmed electric-current that is used to write a resistance value to the resistance change device31. Accordingly, no resistance value is written to the resistance change device31normally. Sometimes, charging and discharging occur instantaneously, i.e., substantially at the same time due to the skew of an output of the phase detector10. Thus, through-electric-current flows therethrough. However, at that time, no electric current flows in the resistance change device31. Electric-current flows only through the charge pump20, and the switches32aand32b. Thus, no erroneous writing to the resistance change device31occurs.

However, if a pulse to the charge pump20from the phase detector10is accidentally lengthened, e.g., just after the activation of the power supply to the PLL, erroneous writing to the resistance change may be performed. Thus, switches32fand32gand each inrush resistance34are inserted into the loop filter30, as illustrated inFIG. 7to thereby prevent the occurrence of the erroneous writing. The switches32fand32gare turned on/off according to the signal Normal. During a normal operation (in which the level of the signal Normal is “H”), the switches32fand32gare turned off. However, during an operation of writing to the resistance change device31(in which the level of the signal Normal is “L”), the switches32fand32gare turned on. Consequently, during the normal operation, an amount of electric-current flowing from the charge pump20to the resistance change device31is suppressed. Thus, the occurrence of the erroneous writing to the resistance change device31can be prevented.

The sequencer60also controls the multiplexers70and the switches80shown inFIG. 1according to which of the operation of writing to the resistance change device31, and the normal operation is performed. Each of the multiplexers70is provided between the phase detector10and the charge pump20. When the resistance value of the resistance change device31is changed, the phase detector10and the charge pump20are disconnected from each other by the multiplexers70to interrupt the feedback loop of the PLL. Each of the multiplexers70is a switch that switches output signals according to the signal Normal. During the normal operation (in which the level of the signal Normal is “H”), the multiplexers70outputs signals input thereto from the phase detector10. However, during the operation of writing to the resistance change device31(in which the level of the signal Normal is “L”), the multiplexers70output signals input thereto from the sequencer60. The sequencer60inputs, when the resistance value of the resistance change device31is changed, a writing pulse signal to each of the multiplexers70to thereby control the charge pump20instead of the phase detector10.

The switches80are provided at the preceding stage of the frequency divider50and at that of the phase detector10, respectively. When the resistance value of the resistance value change device31is changed, the sequencer60inputs control signals to the switches80to turn off the switches80. The turning-off of the switches80can also interrupt the feedback loop of the PLL. Incidentally, each switch80can be either a complementary-MOS (CMOS) switch or a resistance change type device whose resistance becomes infinitive.

Thus, the influence of noise due to outputs of the VCO40and the phase detector10is avoided by interrupting the feedback loop of the PLL when the resistance value of the resistance change device31is changed.

In addition, although the feedback loop of the PLL can be interrupted only by the multiplexers70, the power consumption of the PLL at the time of changing the resistance value of the resistance change device31can be reduced using the switches80in addition to the multiplexers70to interrupt the feedback loop of the PLL. This is because of the fact that the operations of the phase detector10and the frequency divider50, which digitally operate, are stopped.

FIG. 8illustrates a process performed by the PLL when the resistance value of the loop filter30is changed. In step S10, when receiving from an external control circuit a signal indicating that the reference frequency of the PLL is changed, or that the PLL is activated, the sequencer60inputs control signals to the multiplexers70and the switches80to interrupt the feedback loop. Then, in step S11, the sequencer60controls the turning-on/turning-off of the switches32ato32e(or32ato32g) provided in the loop filter30. Next, in step S12, the resistance value of the resistance change device31is changed by applying electric-current to the loop filter30via the charge pump20. Then, the sequencer60inputs control signals to the multiplexers70and the switches80to restore the feedback loop to a normal closed-loop state.

Hereinafter, an appropriate method for determining the damping constant of the loop filter30is described. In order to maximize the value of ζωngiven by Expression 4, it is advisable to make the loop filter30show high-speed response.FIG. 9schematically illustrates the relationship between the damping constant ζ and the variation of the frequency of the VCO40. As illustrated inFIG. 9, if the damping constant ζ is small, the feedback loop of the PLL is underdamped. The variation of the frequency of the VCO40is reduced in response to a pulse operation of the charge pump20. Thus, the PLL operates stably. In contrast with this, if the damping constant ζ is large, the variation of the frequency of the VCO40is increased in response to a pulse operation of the charge pump20. The damping action of the feedback loop of the PLL is enhanced. The convergence of the damped oscillation is enhanced. Consequently, the PLL is quickly locked up. Thus, when the PLL is unlocked, or when the electric-power of the PLL is turned on, it is desirable to set the damping constant as meeting the following Expression 5, thereby to avoid oscillation of the output signal of the PLL until the PLL is locked up. A settling time can be shortened at least by setting the damping constant at about 1.

The resistance value of the resistance change device31is set to be increased so that as the PLL approaches a lockup state, the damping constant ζ of the loop filter30is reduced. Consequently, phase noise and spurious signals can be suppressed from signals output therefrom to the phase detector10. Accordingly, the PLL operates more stably.

Thus, when the PLL is unlocked, or when the power supply is turned on, the resistance value of the resistance change device31is set to be low. When the PLL is locked up, the resistance value of the resistance change device31is set to be high. Consequently, a PLL with stability and readiness can be provided. In addition, because the PLL according to the present embodiment uses the resistance change device, the resistance value thereof can be changed by the single device between the low-resistance state and the high-resistance state.

In the description made with reference toFIG. 3, it has been described that each of the switches32ato32din the loop filter30is configured using an nMOS and a pMOS. However, paths from the charge pump20are clearly differentiated into a charging one and a discharging one. Thus, as illustrated inFIG. 10, a pMOS and an nMOS can be used in the charging path and the discharging path, respectively. Thus, the number of circuit devices of the switch can be reduced. Although an nMOS and a pMOS can be used in the charging path and the discharging path, respectively, the on-state characteristic of each transistor is increased. Therefore, it is difficult to predict the characteristic of the loop filter. Accordingly, it is more preferable that a pMOS switch and an nMOS switch are used in the charging path and the discharging path, respectively.

An input signal input to the loop filter130from the sequencer60shown inFIG. 10is the same as that input to the loop filter30described by referring toFIG. 3. When the PLL is unlocked, or when the power supply of the PLL is turned on, the sequencer60sets the signal-levels of the signals Normal, Write “H”, and Write “L” at “L”, “L”, and “H”, respectively. Then, switches132band132care turned on, while switches132aand132dare turned off. Thus, the resistance change device31is brought into a low-resistance state similar to the state described with reference toFIG. 4.

When the PLL is locked up, the sequencer60sets the signal-levels of the signals Normal, Write “H”, and Write “L” at “L”, “H”, and “I,”, respectively. Then, the switches132aand132dare turned on, while the switches132band132care turned off. Thus, the resistance change device31is brought into a high-resistance state similar to the state described with reference toFIG. 5.

In the normal state, the sequencer60sets the signal-levels of the signals Normal, Write “H”, and Write “L” at “H”, “L”, and “L”, respectively. Then, the switches132a,132band32eare turned on, while the switches132cand132dare turned off. Thus, the resistance change device31is brought into a state similar to the state described with reference toFIG. 6.

A three-terminal device can be used as the resistance change device. The three-terminal resistance change device has a terminal for writing a resistance value. A resistance value to be written to the resistance change device is determined according to the value input to this terminal.

FIG. 11illustrates a loop filter230using a three-terminal resistance change device. A control signal is input to a three-terminal resistance change device231from the sequencer60. The resistance value of the resistance change device231changes according to the control signal. When the resistance value of the resistance change device231is changed, the sequencer60turns off the switch32e. In the normal state, the sequencer60controls the switch32eso as to be turned on.

Thus, in the case of using the three-terminal resistance change device, the loop filter230doesn't need to be provided with the switches32ato32dneeded in the loop filter30illustrated inFIG. 30.

The loop filter can be configured as illustrated inFIG. 12to prevent the electric-potential VVCOof the VCO40from being discharged when the power supply of the PLL is turned off. The loop filter330illustrated inFIG. 12is configured by adding a switch32hto the loop filter30illustrated inFIG. 3. The sequencer60controls the switches32eand32hto be turned off when the power supply of the PLL is turned off. Consequently, the loop filter330can retain electric charge stored in the capacitor33. Thus, because the PLL is in a state in which a certain amount of electric charge is stored in the capacitor33when the power supply is turned on again, the PLL can quickly be locked up. However, in order to turn off the switches32eand32hwhen the power supply of the PLL is turned off, it is necessary to apply a voltage to the sequencer60. If a resistance change device whose resistance is infinitive is used as each of the switches32eand32h, the power supply of the sequencer60can be turned off when the power supply of the PLL is turned off.

In the foregoing description, the present embodiment and the modifications thereof have been described. The present embodiment can appropriately be changed to modifications other than the above Modifications 1 to 3 without departing from the spirit of the invention. For example, switches and an inrush resistance can be provided in each of Modifications 1 to 3, as illustrated inFIG. 7, to prevent erroneous writing. Alternatively, some of Modifications 1 to 3 and other modifications can be combined with one another.

Second Embodiment

The present embodiment is an embodiment in the case of provided plural resistance change devices in the loop filter.FIG. 13illustrates a loop filter530and a sequencer560of a PLL according to the present embodiment. Other components of the PLL according to the present embodiment are similar to the corresponding ones according to the first embodiment. Thus, the description thereof is omitted. Incidentally,FIG. 13illustrates a signal applied to the nMOS of each of switches32ato32m, similarly toFIG. 3. However, a signal applied to the pMOS thereof is omitted. The reversal value of a value represented by the signal input to the nMOS thereof is applied to the pMOS thereof.

FIG. 13illustrates the loop filter530, in which two resistance change devices are arranged in parallel to each other, by way of example. In the loop filter530, switches32iand32jare provided at both ends of the first resistance change device31a, respectively. Switches32kand32mare provided at both ends of the second resistance change device31b, respectively. The switches32i,32j,32k, and32mare turned on/off according to control signals input from the sequencer560. A signal R1_en is input to the switches32iand32jfrom the sequencer560. If the signal-level of the signal R1_en is “H”, the switches32iand32jare turned on. A signal R2_en is input to the switches32kand32mfrom the sequencer560. If the signal-level of the signal R2_en is “H”, the switches32kand32mare turned on.

It can be selected by these switches whether electric-current is applied to the first resistance change device31a, and whether electric-current is applied to the second resistance change device31b. Hereinafter, a state in which the switches32iand32jprovided at both ends of the resistance change device31aare turned off, and a state in which the switches32kand32mprovided at both ends of the resistance change device31bare turned off, are referred to as a state in which the resistance change device is turned off. On the other hand, a state in which the switches32iand32jprovided at both ends of the resistance change device31aare turned on, and a state in which the switches32kand32mprovided at both ends of the resistance change device31bare turned on, are referred to as a state in which the resistance change device is turned on.

FIG. 14illustrates the combinations of the states of the first resistance change device31aand the second resistance change device31b. Each of the first resistance change device31aand the second resistance change device31bcan be put into a high-resistance state, a low-resistance state, and an off-state. If both of the first resistance change device31aand the second resistance change device31bare in an on-state, the resistance value of the loop filter530is that of a combined resistance of the first resistance change device31aand the second resistance change device31b.

If all the resistance values in the high-resistance state and the low-resistance state of the first resistance change device31aand the second resistance change device31bdiffer from one another, the resistance values respectively corresponding to eight conditions (i.e., Condition1to8shown inFIG. 14) of the resistance to electric-current flowing between the charge pump20and the loop filter530differ from one another.

Utilizing this, the resistance value of the loop filter530can be set to be low when the PLL is unlocked, or when the power supply of the PLL is turned on, and to increase step by step as the PLL approaches a stable state.

For example, a time elapsed since the PLL is unlocked, or since the power supply of the PLL is turned on is measured by counting clock-cycles from the reference frequency of a signal input to the PLL. Then, as illustrated inFIG. 15, the elapsed time is divided into stages at every predetermined elapsed-time Δt. Then, the resistance values of the first resistance change device31aand the second resistance change device31band the on-states or off-states of the switches provided at both ends of each of the resistance change devices31aand31bare changed such that the resistance value of the loop filter530increases every time the PLL passes the stages. For example, at a first stage, the resistance change devices are set to be in Condition8shown inFIG. 14. Then, at a second stage, the resistance change devices are set to be in Condition6. Next, at a third stage, the resistance change devices are set to be in Condition4. Then, at a fourth stage, the resistance change devices are set to be in Condition1. In the sequencer560, a nonvolatile lookup table can be provided. Then, the state to be set at each stage can preliminarily be set in the lookup table.

An output of the phase detector10can be input to the sequencer560. In addition, the resistance value of the loop filter530can be changed step by step according to temporal variation of phase difference output by the phase detector10.

In the cases of detecting the unlocked state of the PLL, and requesting the activation of the PLL from a state in which the power supply is turned off, the initial value of the resistance value of the loop filter530can be changed. For example, the state in which the unlocked state of the PLL is detected is considered to be closer to the stable state than that in which the activation of the PLL is requested. Thus, if the unlocked state of the PLL is detected, the initial value of the resistance value of the loop filter530is set to be high (e.g., Condition5shown inFIG. 14). If the activation of the PLL is requested, the initial value of the resistance value of the loop filter530is set to be low (e.g., Condition8shown inFIG. 14). Consequently, in the case where the activation of the PLL is requested, the PLL can be put into a lockup state more quickly. In the case where the unlocked state of the PLL is detected, the PLL can be operated more stably.

FIG. 16shows a process flow illustrating a process performed by the PLL when the resistance value of the loop filter530is changed. InFIG. 16, each process which the same as that illustrated inFIG. 8is designated with the same reference numeral used inFIG. 8. In step S11, when the resistance value of the loop filter530is changed, one of the resistance change devices, whose resistance value is changed, is selected using the switches32ito32m. As described in the first embodiment, the turning-on or turning-off of the switches32ato32eis controlled. Then, after the writing to the selected resistance change device is finished, if the writing to another of the resistance change devices is needed (No in step S20), the resistance change device is selected and the writing thereto is performed.

FIG. 17illustrates a timing chart of the sequencer60. A signal CLK_ref represents a reference frequency input to the PLL. As illustrated inFIG. 17, in the normal state, the level of the signal Normal is set at “H”. If the writing to the resistance change device is performed, the level of the signal Normal is set at “L”. According to which of the resistance change devices the writing target is, the level of one of signals R1_en and R2_en is set at “H”. The level of the other signal is set at “L”. During a normal operation, the level of at least one of the signals R1_en and R2_en is set at “H”, based on the lookup table provided in the sequencer60.

Thus, according to the second embodiment, the resistance of the loop filter can finely be changed. In addition, according to the present embodiment, the resistance change devices are used. Thus, as compared with the case of using resistances each having a fixed resistance value, the resistance value of the loop filter can be controlled at finer levels.

In the description made with reference toFIG. 13, it has been described that the switches32i,32j,32k, and32min the loop filter30use nMOSs and pMOSs. However, as illustrated inFIG. 18, these switches can be configured as nMOS switches32nto32q. Consequently, the number of circuit devices of each switch can be reduced. Incidentally, pMOS switches can be used instead of the nMOS switches32nto32q.

Also in the present embodiment, other various alterations thereof can be made. The modifications described in the first embodiment can be applied thereto. In the second embodiment, the example using the two resistance change devices has been described. However, three or more resistance change devices can be used. Incidentally, if the number of resistance change devices is increased, the number of switches provided at both ends of each of the resistance change devices increases. Thus, the junction capacitance of transistors configuring the switches may affect the gain of the loop filter. Therefore, preferably, the number of the resistance change devices connected in parallel with one another is equal to or less than 4.

The invention is not limited to the above embodiments. The embodiments will be appropriately changed without departing from the scope of the invention.