Simultaneous two/dual port access on 6T SRAM

A method includes generating a first and a second internal clock signal from a clock signal, wherein a first internal clock signal edge of the first internal clock signal and a second internal clock signal edge of the second internal clock signal are generated from a same edge of the clock signal. A first one of the first and the second internal clock edges is used to trigger a first operation on a six-transistor (6T) Static Random Access Memory (SRAM) cell of a SRAM array. A second one of the first and the second internal clock edges is used to trigger a second operation on the 6T SRAM cell. The first and the second operations are performed on different ports of the 6T SRAM. The first and the second operations are performed within a same clock cycle of the clock signal.

BACKGROUND

Static Random Access Memory (SRAM) is widely used in integrated circuits. SRAM cells stores data in latches that are formed of two P-type Metal-Oxide-Semiconductor (PMOS) devices and two N-type Metal-Oxide-Semiconductor (NMOS) devices. SRAMs have many designs including, for example, Six-Transistor (6T) SRAMs, Eight-Transistor (8T) SRAMs, single-port SRAMs, two-port SRAMs, dual-port SRAMs, and the like. An SRAM may be referred to as a two/dual port SRAM, indicating that the SRAM may be a two-port SRAM or a dual-port SRAM.

Conventionally, 8T SRAMs with two/dual ports are operated with two clock signals, one for read/write operations, and one for write/read operations. The two clock signals are independent from each other. Although the performance of the two/dual portion 8T SRAMs is high due to the fact the that the two clock signals may be tuned independently from each other, the chip area occupied by the two/dual port 8T SRAMs is high. Accordingly, pseudo two-/dual-port 6T SRAMs were designed.

The sizes of the 6T SRAMs are smaller compared to two/dual port 8T SRAMs. For example, the chip area occupied by 8T SRAMs may be 1.5 times the chip area occupied by 6T SRAMs. Due to structure limitations, the 6T SRAMs use one clock signal for both read operations and write operations, wherein the rising edges of the clock signal are used for read operations, and the falling edges of the clock signal are used for write operations, or vice versa.

The performance of the pseudo two/dual port 6T SRAMs, however, is limited. This is because the read operations and the write operations are tied together, and the clock cycle time has to be long enough to accommodate the one of the read and write operations that takes longer time to finish. Hence, it is difficult to tune the performance of pseudo two-/dual port 6T SRAMs.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

A clock generation scheme for reading and writing Static Random Access Memory (SRAM) cells and the exemplary clock generation circuits are provided in accordance with various exemplary embodiments. The variations and the operation of the embodiments are discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Throughout the description, for example, inFIGS. 4 and 6, the rising edges of some clock signals are used as examples for triggering actions such as the generation internal clock signal edges. In alternative embodiments, the falling edges may also be used to trigger actions. It is appreciated that the concepts “row” and “column” may be interchangeable, and the concepts “row address” and “column address” may be interchangeable, an address may thus be referred to as a “row/column” address, indicating it may be a row address or a column address.

FIG. 1illustrates an exemplary block diagram of SRAM array10and the supporting circuits for performing read and write operations on SRAM array10. In some embodiments, SRAM array10includes a plurality of memory cells30arranged as an array. Memory cells30may be six-transistor (6T) SRAM cells, wherein an exemplary circuit diagram of a 6T SRAM cell is shown. Throughout the description, memory cells30are used as two/dual port cells (although there may have one physical port), on which the read and write operations may be performed in a same clock cycle of clock signal CLK (FIGS. 4 and 6). The expression of two/dual port indicates that memory cell30may be a dual-port SRAM cell or a two-port SRAM cell. Although the read and write operations that are performed in the same clock cycle are performed sequentially, the order may be transparent to the user of the SRAM cells. Accordingly, throughout the description, the read and write operations that are performed in the same clock cycle are referred to as simultaneous read and write operations.

The supporting circuits for performing read and write operations on SRAM array10include read/write clock generator12, write address latches & pre-decoder14, read address latches & pre-decoder16, write column decoder18, read column decoder20, Sense Amplifier (SA)/write driver22, and read/write row decoder24. Read/write clock generator12is configured to receive a single clock signal CLK, and generate internal read and write clock signals CKP1and CKP2(FIGS. 4 and 6), which internal read/write clock signals CKP1and CKP2are used for the read and write operations of the memory cells in SRAM array10. Throughout the description, the symbol “/” represents “and” or “or,” and whether the symbol “/” represents an “and” or an “or” is related to the context in which the symbol “/” is used. For example, “SA/write driver” represents SA and write driver, and “read/write clock signals CKP1and CKP2” means one of clock signals CKP1and CKP2is used as an internal write clock signal, and the other one of clock signals CKP1and CKP2is used as an internal read clock signal.

Write address latches & pre-decoder14is configured to receive and latch write address AA (a row address), and pre-decode write address AA. Read address latches & pre-decoder16is configured to receive and latch read address AB (a row address), and pre-decode read address AB. The pre-decoded addresses are provided to read/write row decoder24, which selects one of word-lines WL. The selected word-line WL is the word-line of the SRAM cell30on which the read or write operation is to be performed. Read/write row decoder24uses word-line driver26to drive word-lines WL for both read and write operations. In some embodiments, word-line driver26comprises an OR gate, which performs the OR operation on the pre-decoded addresses received from write latches & pre-decoder14and read latches & pre-decoder16. Word-line driver26outputs the resulting “OR”ed address to enable the selected word-line WL.

FIG. 1also illustrates write column decoder18and read column decoder20for decoding the column of the selected SRAM cell30for performing the write operation and the read operation, respectively. SA22is configured to read from, and amplifier signals for, bit-lines (such as BL and BLB) of memory array10. Write driver22is configured to drive input data to write to the bit-lines (such as BL and BLB) of memory array10.

FIG. 2illustrates a symbol diagram for the read and write operations of memory cell30inFIG. 1. As shown inFIG. 2, a single clock CLK is used to operate memory array10and SRAM cell30. Symbol “D” represents the input data, and symbol “Q” represents the read-out data. Symbols WEB and REB are write-enable and read-enable signals, respectively, which control whether a write operation or a read operation is to be performed. Symbol AA is the write address, and Symbol AB is the read address.

FIG. 3illustrates an exemplary read/write clock generator12, which receives clock signal CLK, and generates internal clock signal CKP1. The falling edge of internal clock signal CKP1triggers the generation of the rising edge of internal clock signal CKP2. The edges (either the rising edges or the falling edges) of internal clock signals CKP1and CKP2are used to trigger read operations and write operations, respectively. Signals CKRE and CKWE are enable signals for the read and write operations, respectively, and may have inversed phases than WEB and REB signals, respectively, inFIG. 2. Also, in other embodiments, CKP1may be triggered by CLK falling edge, and CKP2may be triggered by CKP1failing edge.

FIG. 4illustrates an exemplary sequence diagram, wherein the clock signal CLK, REB, WEB, AA, and AB inFIG. 2and clock signal CLK, internal clock signals CKP1and CKP2inFIG. 3, and the signal on word-line WL (FIG. 1) are illustrated. The signals in the sequence diagram may be generated using the circuit inFIG. 3. The symbols “cyc,” “t,” “r,” “w,” “ab, “aa,” “s,” and “h” represent cycle, time, read, write, AA address, AB address, setup time, and hold time, respectively. For example, symbol “trcyc” represents read clock cycle time, and symbol “tabs” represent the setup time for read address AB.

FIG. 4illustrates three examples, including a read operation in clock cycle trcyc, a write operation in clock cycle twcyc, and simultaneous read and write operations in clock cycle trwcyc. In the illustrated examples inFIG. 4(and also inFIG. 6), internal clocks CKP1and CKP2are the internal read clock and the internal write clock, respectively. In the first example, at time T1, read enable signal REB and read address AB are already ready, which enables the read operation. The rising edge of clock signal CLK at time T1results in (triggers) the generation of the rising edge ER1of internal clock signal CKP1, which in turn results in the generation of rising edge ER2of word-line WL. The read operation on the selected SRAM cell30inFIG. 1is thus performed.

In the second example, at time T2, write enable signal WEB and write address AA are already ready, which enables the write operation. The rising edge of clock signal CLK at time T2results in the generation of the rising edge ER3of internal clock signal CKP2, which in turn results in (triggers) the generation of rising edge ER4of word-line WL. The write operation on the selected SRAM cell30inFIG. 1is thus performed.

In the third example in which the simultaneously read and write operations are performed, at time T3, write enable signal WEB, write address AA, read enable signal REB, and read address AB are all ready, which enables both the read and write operations. The rising edge of clock CLK at time T3triggers the generation of the rising edge ER5of internal clock signal CKP1, which in turn triggers the generation of rising edge ER6of word-line WL. The read operation on the selected SRAM cell30inFIG. 1is thus performed. After the read operation is finished, the falling edge EF1of internal clock signal CKP1triggers the generation of rising edge ER7of internal clock signal CKP2, which in turn triggers the generation of the rising edge ER8of word-line WL. The write operation on the selected SRAM cell30inFIG. 1is thus performed. Therefore, in the illustrated example, the write operation is performed immediately after the read operation, and both read and write operations are performed in the same clock cycle trwcyc. Accordingly, in this exemplary embodiment, a same rising edge (at time T3) of a single clock signal CLK drives the read and write operations in the same clock cycle trwcyc, which is considered as the simultaneous read and write operations. The respective SRAM cell30is hence operated similar to a two-/dual-port 6T SRAM cell. In the other words, CKP1may be treated as write internal clock signal, and CKP2be treated as a read internal clock signal.

FIG. 5illustrates an exemplary read/write clock generator12in accordance with alternative embodiments. Read/write clock generator12in accordance with these embodiments receives clock signal CLK, and generates internal clock signal CKP1and clock signal CKP1A. Internal clock signal CKP1is used for the read operation. Internal clock signal CKP1A is not used for the read operation and write operation. The falling edge of internal clock signal CKP1A, however, triggers the generation of the rising edge of internal clock signal CKP2, which is used to trigger a write operation.

FIG. 6illustrates an exemplary sequence diagram of the signals generated using the circuit inFIG. 5. Illustrated are three examples including a read operation in clock cycle trcyc, a write operation in clock cycle twcyc, and a simultaneous read and write operation in clock cycle trwcyc. The read operation in clock cycle trcyc and the simultaneous read and write operations in clock cycle trwcyc are essentially the same as inFIG. 4, and hence the detailed operations are not repeated herein. For the write operation in clock cycle twcyc, at time T2, write enable signal WEB and write address AA are already ready, which enables the write operation. The rising edge of clock signal CLK at time T2results in the generation of the rising edge ER9of internal clock signal CKP1A, which is used to delay the write operation. The falling edge EF2of internal clock signal CKP1A triggers the generation of the rising edge ER10of internal clock signal CKP2(the internal write signal), which in turn triggers the generation of the rising edge ER11of word-line WL. The write operation on the selected SRAM cell30(FIG. 1) is thus started. As occurring in clock cycle twcyc, the rising edge ER10of internal clock signal CKP2is delayed by time tdelay, which is the period of the high pulse of internal clock signal CKP1A. This is different from the embodiments shown inFIG. 4, in which rising edge ER3for the write operation does not have such delay.

In the exemplary embodiments inFIGS. 4 and 6, and in clock cycle trwcyc, the read operations are illustrated as being performed before the respective write operations. In alternative embodiments, the read operations may be performed after the respective write operations. To make the write operations performed before the read operations, internal signal CKP1is used for write operations, and internal clock signal CKP2is used for read operations.

In clock cycle trwcyc (FIGS. 4 and 6), since the read and write operations are performed sequentially, an adequate bit-line pre-charging time needs to be reserved for pre-charging bit-lines BL and BLB (FIG. 1) to a desirable level (such as VDD). The bit-line pre-charging time is approximately time tpre, which is approximately from the middle point of falling edge EF1to the middle point of rising edge ER7(FIGS. 4 and 6). The needed bit-line pre-charging time needs to be long enough so that the bit-lines are adequately charged and short enough so that it does not result in the clock cycle time trwcyc to be unnecessarily extended, which unnecessary extension causes the speed of the SRAM operations to be reduced.

The control of the bit-line pre-charging time is achieved by inserting delay element34(FIGS. 3 and 5) into read/write clock generator12, and between the generation of internal clock signal CKP1and the generation of internal clock signal CKP2.FIG. 7illustrates an exemplary implementation of delay element34. Delay element34receives input signal Sin, and generates output signal Sout, which may be internal clock signal CKP2. In some exemplary embodiments, delay element34includes pull-up device PU, which may include one or a plurality of pull-up devices (PMOS devices, for example). Delay element34further includes resistor Rbl and capacitor Cbl. Device PU is designed to track the performance (for example, by matching the size) of the pull up device (not shown) in the bit-line pre-charge circuit. Capacitor Cbl is designed to have the capacitance tracking the capacitance of normal bit-lines BL and BLB (FIG. 1). This may be achieved by forming a dummy bit-line41(FIG. 1), which may have the same length as normal bit-lines BL and BLB (FIG. 1). The capacitance of dummy bit-line41is used as the capacitance of Cbl. Similarly, resistor Rbl is designed to have the resistance tracking the resistance of normal bit-lines BL and BLB (FIG. 1). This may also be achieved by forming dummy bit-line41, which may have the same length and the same width as normal bit-lines BL and BLB, wherein dummy bit-line41is used as resistor Rbl. Since devices PU, Rbl, and Cbl all track the performance and the load of the actual bit-line pre-charge circuit, when the bit-line pre-charging takes long time due to, for example, long bit-lines BL and BLB, delay element34also has an increased delay, and vice versa. The resulting read/write clock generator12is thus has an optimized bit-line pre-charging time, and the frequencies of read and write operations may be increased.

FIG. 8illustrates portions of the sequence diagram shown inFIG. 6, wherein CKPR represents the one of internal clock signals CKP1and CKP2that is used for the read operations, and CKPW represents the one of internal clock signals CKP1and CKP2that is used for the write operations. As shown inFIG. 8, which is also shown inFIG. 4, rising edge ER10, which is for the write operation, is delayed by delay time tdelay, which is the high pulse width of CKP1A. Such delay time is utilized in the pre-decoding of write address AA and read address AB (FIGS. 1,2, and3) to reduce the sizes of write latches & pre-decoder14and read latches & pre-decoder16.

FIG. 9illustrates the block diagram of exemplary write address latches & pre-decoder14and read address latches & pre-decoder16in accordance with embodiments. As shown inFIG. 9, write address AA and read address AB are latched by latches40and42, respectively. Portions of the bits in write address AA, such as high bits, are pre-decoded as WDEC_X1and WDEC_X2using level pre-decoder44. The remaining portions of the bits in write address AA, such as lower bits including Least Significant Bit (LSB) bit, are pre-decoded as WDEC_X0using pulse pre-decoder46. Similarly, read address AB is decoded by level pre-decoder48and pulse pre-decoder50. Latches40, level pre-decoder44, and pulse pre-decoder46form write latches & pre-decoder14(also seeFIG. 1). Latch42, level pre-decoder48, and pulse pre-decoder50form write latches & pre-decoder16inFIG. 1.

Level pre-decoders44and48may start decoding as soon as the preceding latches latch an address. On the other hand, pulse pre-decoders46and50start decoding addresses in response to the rising edges of internal read clock signal CKPW (also seeFIG. 8) and internal write clock signal CKPR (also seeFIG. 8), respectively. Generally, the level pre-decoders occupy smaller chip areas than pulse pre-decoders, but the decoding takes longer time than pulse pre-decoders. In the embodiments, by combining level pre-decoder44/48with pulse pre-decoder46/50, the chip area occupied by the pre-decoders14and16may be reduced without sacrificing decoding time. The delay time tdelay (FIGS. 6 and 8) extends the time the can be used for level pre-decoding and further reducing chip area. For example, referring toFIG. 4, the time that can be used by level pre-decoder44(FIG. 8) is taas. InFIG. 6, however, the time that can be used by level pre-decoder44is increased to (taas+tdelay). Therefore, by adopting the design inFIGS. 5 and 6, more bits in addresses AA and AB can be assigned to level pre-decoders44and48, so that the overall chip area usage of write latches & pre-decoder14and read latches & pre-decoder16is reduced.

In the embodiments, simultaneously read and write operations may be performed in a same clock cycle, and one clock CLK, rather than two, is used for the simultaneously read and write operations of 6T SRAM cells. Furthermore, although a single clock CLK is used, either the rising edges or the falling edges, but not both, of the clock signal CLK is used for triggering read and write operations. This reduces the difficult in tuning the performance of the reading and the writing of the 6T SRAM cells.

In accordance with embodiments, a method includes generating a first and a second internal clock signal from a clock signal, wherein a first internal clock signal edge of the first internal clock signal and a second internal clock signal edge of the second internal clock signal are generated from a same edge of the clock signal. A first one of the first and the second internal clock edges is used to trigger a first operation on a 6T SRAM cell of a SRAM array. A second one of the first and the second internal clock edges is used to trigger a second operation on the 6T SRAM cell, wherein the first and the second operations include a read operation and a write operation. The read operation and the write operation are performed within a same clock cycle of the clock signal.

In accordance with other embodiments, a method includes triggering generation of a first internal clock signal from a clock signal, wherein a first internal clock signal edge and a second internal clock edge of the first internal clock signal are generated from an edge of the clock signal. The second internal clock edge has a direction opposite to a direction of the first internal clock signal edge. The second internal clock edge is immediately after the first internal clock signal edge, with no other edges therebetween. The method further includes triggering generation of a second internal clock signal, wherein a third internal clock signal edge of the second internal clock signal is generated from the second internal clock edge of the first internal clock signal. A write operation is performed on a 6T SRAM cell of a SRAM array using the third internal clock signal edge.

In accordance with yet other embodiments, a device includes a read/write clock generator having an input, a first output, and a second output. The read/write clock generator is configured to generate from an edge of a clock signal received from the input, and output a first internal clock signal and a second internal clock signal to the first output and the second output, respectively. A read pre-decoder has a first input connected to the first output of the read/write clock generator. The read pre-decoder is configured to, upon the first internal clock signal, pre-decoding a row address of a 6T SRAM cell of an SRAM array. A write pre-decoder has a second input connected to the second output of the read/write clock generator. The write pre-decoder is configured to, upon the second internal clock signal, pre-decoding the row address of the 6T SRAM cell. A read/write row decoder is connected to an output of the read pre-decoder and an output of the write pre-decoder, wherein the read/write row decoder is configured to select a word-line of the SRAM array using addresses decoded by the read pre-decoder and the write pre-decoder.