Method for manufacturing image display device and image display device

A method for manufacturing an image display device includes: preparing a substrate, the substrate comprising a semiconductor layer, the semiconductor layer comprising a light emitting layer, the semiconductor layer being formed on a first substrate; bonding the semiconductor layer to a second substrate, the second substrate comprising a circuit that comprises a circuit element; forming a light emitting element by etching the semiconductor layer; forming an insulating film covering the light emitting element; forming a via reaching the circuit through the insulating film; and electrically connecting the light emitting element and the circuit element through the via, the via connecting the light emitting element and the circuit element provided in different layers.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims priority to Japanese Patent Application No. 2019-055382, filed on Mar. 22, 2019, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments of the invention described herein relate to a method for manufacturing an image display device and the image display device.

BACKGROUND

It is desired to realize a thin image display device with high luminance, wide viewing angle, high contrast, and low power consumption. In order to respond to such market demand, development of a display device using a self-light emitting element is in progress.

The appearance of a display device using a micro LED, which is a fine light emitting element, is expected as a self-light emitting element. As a method for manufacturing a display device using micro LEDs, a method of sequentially transferring individually formed micro LEDs to a drive circuit has been introduced. However, as the number of micro LED elements increases as the image quality increases to full HD, 4K, 8K, etc., a large number of micro LEDs are individually formed and sequentially transferred to the substrate on which the drive circuit and the like are formed. An enormous amount of time is required for the transfer process. In addition, poor connection between the micro LED and the drive circuit or the like may occur, resulting in a decrease in yield.

A technique is known in which a semiconductor layer including a light emitting layer is grown on a Si substrate, and electrodes are formed on the semiconductor layer and then bonded to a circuit substrate on which a drive circuit is formed (for example, JP 2002-141492 A (Kokai)).

SUMMARY

According to one embodiment of the invention, a method for manufacturing an image display device and the image display device are provided, in which transferring process of a light emitting element is reduced and a yield is improved.

According to one embodiment of the invention, a method for manufacturing an image display device is disclosed. The method includes preparing a substrate that includes a semiconductor layer. The semiconductor layer includes a light emitting layer. The semiconductor layer is formed on a first substrate. The method can include bonding the semiconductor layer to a second substrate. The second substrate has a circuit that includes a circuit element. The method can include forming a light emitting element by etching the semiconductor layer, forming an insulating film covering the light emitting element, and forming a via reaching the circuit through the insulating film. Additionally, the method can include electrically connecting the light emitting element and the circuit element through the via. The via connects the light emitting element and the circuit element provided in different layers.

According to another embodiment of the invention, an image display device includes a circuit element, a first interconnect layer electrically connected to the circuit element, a first insulating film covering the circuit element and the first interconnect layer, a light emitting element disposed on the first insulating film, a second insulating film covering at least a part of the light emitting element, a second interconnect layer electrically connected to the light emitting element and disposed on the second insulating film; and a first via extending through the first insulating film and the second insulating film, and electrically connecting the first interconnect layer and the second interconnect layer.

According to another embodiment of the invention, an image display device includes a plurality of transistors, a first interconnect layer electrically connected to the plurality of transistors, a first insulating film covering the plurality of transistors and the first interconnect layer, a first semiconductor layer of a first conductivity type disposed on the first insulating film, a light emitting layer disposed on the first semiconductor layer, a second semiconductor layer of a second conductivity type different from the first conductivity type disposed on the light emitting layer, a second insulating film covering the first insulating film, the light emitting layer and the first semiconductor layer, and covering at least a part of the second semiconductor layer, a second interconnect layer connected to a transparent electrode that is disposed on a plurality of exposed surfaces of the second semiconductor layer, the plurality of exposed surfaces being exposed from the second insulating film and corresponding to the plurality of transistors respectively, and a first via extending through the first insulating film and the second insulating film, and electrically connecting a first conductor of the first interconnect layer and a second conductor of the second interconnect layer.

DETAILED DESCRIPTION

In the specification and drawings, components similar to those described previously or illustrated in antecedent previous drawing are marked with the same reference numerals, and a detailed description is omitted as appropriate.

First Embodiment

FIG. 1is a schematic cross sectional view illustrating a portion of an image display device according to a first embodiment.

FIG. 1schematically shows the configuration of a subpixel20of the image display device of the present embodiment. A subpixel10forming the image displayed in the image display device is configured from multiple subpixels20. The following description may be made using an XYZ three-dimensional coordinate system. The subpixels20are arranged on a two-dimensional plane. The two-dimensional plane in which the subpixels20are arranged is defined as an XY plane. The subpixels20are arranged along the X-axis direction and the Y-axis direction.

The subpixel20has a light emitting surface153S substantially parallel to the XY plane. The light emitting surface153S mainly outputs light in the positive direction of the Z-axis orthogonal to the XY plane.

FIG. 1schematically shows a cross section when the subpixel20is cut along a plane parallel to the XZ plane. This cross-sectional view is an arrow cross-section taken along the line A-A′ ofFIG. 4described later.

As shown inFIG. 1, the subpixel20of the image display device includes a transistor103, a first interconnect layer110, a first interlayer insulating film (first insulating film)112, a light emitting element150, and a second interlayer insulating film (second insulating film)156, a second interconnect layer160, and a via161d. The subpixel20further includes a color filter180. The color filter (wavelength conversion member)180is provided on the surface resin layer170via a transparent thin film adhesive layer188. The surface resin layer170is provided on the light emitting element150, the interlayer insulating film156, and the interconnect layer160.

The transistor103is formed on the substrate102. As shown inFIG. 3andFIG. 12to be described later, in addition to the transistor103, circuit elements such as other transistors, resistors, and capacitors are formed on the substrate102, and the circuit101is formed by interconnects and the like. Hereinafter, the circuit101includes an element formation region104in which circuit elements are formed, an insulating layer105, the interconnect layer110, vias that connect the interconnect layer110and the circuit elements, and an insulating film108that insulates between the circuit elements. Other components such as the substrate102, the circuit101, and the interlayer insulating film112may be referred to as a circuit board100.

The transistor103includes a p-type semiconductor region104b, n-type semiconductor regions104sand104d, and a gate107. The gate107is provided on the p-type semiconductor region104bwith the insulating layer105interposed therebetween. The insulating layer105is provided to insulate the element formation region104from the gate107and sufficiently insulate from other adjacent circuit elements. When a voltage is applied to the gate107, a channel can be formed in the p-type semiconductor region104b. The transistor103is an n-channel MOSFET.

The element formation region104is provided in the substrate102. The substrate102is, for example, a Si substrate. The element formation region104includes a p-type semiconductor region104band n-type semiconductor regions104sand104d. The p-type semiconductor region104bis provided near the surface of the substrate102. The n-type semiconductor regions104sand104dare provided spaced from each other in the vicinity of the surface of the p-type semiconductor region104bin the p-type semiconductor region104b.

The insulating layer105is provided on the surface of the substrate102. The insulating layer105also covers the element formation region104and covers the surfaces of the p-type semiconductor region104band the n-type semiconductor regions104sand104d. The insulating layer105is made of, for example, SiO2. The insulating layer105may be a multi-layered insulating layer including SiO2, Si3N4or the like depending on the covered region. The insulating layer105may include a layer of an insulating material having a high dielectric constant.

The gate107is provided on the p-type semiconductor region104bwith the insulating layer105interposed therebetween. The gate107is provided between the n-type semiconductor regions104sand104d. The gate107is made of, for example, polycrystalline Si. The gate107may include silicide having a lower resistance than polycrystalline Si.

In this example, the gate107and the insulating layer105are covered with the insulating film108. The insulating film108is made of, for example, SiO2or Si3N4. In order to flatten the surface for forming the interconnect layer110, an organic insulating film such as PSG (Phosphorus Silicon Glass) or BPSG (Boron Phosphorus Silicon Glass) may be further provided.

Vias111sand111dare formed in the insulating film108. The first interconnect layer (first interconnect layer)110is formed on the insulating film108. The first interconnect layer110includes multiple interconnects having different potentials, and includes interconnects110sand110d. In this way, in each of the cross sectional views ofFIG. 1and subsequent figures, the symbol of the interconnect layer is displayed at a position next to one interconnect included in the interconnect layer. The vias111sand111dare provided between the interconnects110sand110dof the interconnect layer110and the n-type semiconductor regions104sand104d, respectively, and electrically connect them. The interconnect layer110and the vias111sand111dare formed of a metal such as Al or Cu, for example. The interconnect layer110and the vias111sand111dmay include a refractory metal or the like.

The first interlayer insulating film112is further provided as a planarized film on the insulating film108and the interconnect layer110. The interlayer insulating film (first insulating film)112is an organic insulating film such as PSG or BPSG. The first interlayer insulating film112also functions as a protective film that protects the surface of the circuit board100.

A buffer layer140is provided over the interlayer insulating film112. The buffer layer (buffer layer)140includes a nitride such as AlN. By providing the buffer layer140, it can be expected that crystal defects generated when the light emitting element150is epitaxially grown are reduced. As described above, the light emitting element150may be provided directly on the first interlayer insulating film112, not only when the buffer layer140is provided between the light emitting element150and the first interlayer insulating film112.

The interconnect (first conductor)110sin the circuit board100is provided so as to extend in the X-axis direction to the position where the light emitting element150is placed. As shown inFIG. 4to be described later, the interconnect110sextends in the Y-axis direction about the length of the light emitting element in the Y-axis direction or longer than that.

In other words, the outer periphery of the interconnect110sincludes the outer periphery of the light emitting element150when the light emitting element150is projected from above the Z axis in the XY plan view. Accordingly, the interconnect110scan block light from being scattered below the light emitting element150so that the interconnect110sdoes not reach the transistor103. By appropriately selecting the material of the interconnect110s, the downward scattering of the light emitting element150can be reflected to the light emitting surface153S side, and the light emission efficiency can be improved. In addition, because the interconnect110sblocks scattered light from below the light emitting element150, arrival of light to the transistor103is suppressed, and malfunction of the transistor103can be prevented.

The light emitting element150includes an n-type semiconductor layer (first semiconductor layer)151, a light emitting layer152, and a p-type semiconductor layer (second semiconductor layer)153. The n-type semiconductor layer151, the light emitting layer152, and the p-type semiconductor layer153are stacked in this order from the interlayer insulating film112of the circuit board100toward the positive direction of the Z-axis, that is, toward the light emitting surface153S. The light emitting element150has, for example, a substantially square or rectangular shape in the XY plan view, but the corners may be rounded. The light emitting element150may have, for example, an elliptical shape or a circular shape in the XY plan view. By appropriately selecting the shape and arrangement of the light emitting elements in the plan view, the degree of freedom in layout is improved. In this example, the n-type semiconductor layer151has a stepped portion151aextending on the buffer layer140in the X-axis direction.

For the light emitting element150, for example, a nitride semiconductor such as InXAlYGa1-X-YN (0≤X, 0≤Y, X+Y<1) and the like is preferably used. The light emitting element150is a so-called blue light emitting diode, and the wavelength of light emitted from the light emitting element150is, for example, about 467 nm±20 nm. The wavelength of the light emitted from the light emitting element150may be blue-violet light emission of about 410 nm±20 nm. The wavelength of light emitted from the light emitting element150is not limited to the above value, and may be appropriate.

The second interlayer insulating film (second insulating film)156covers the buffer layer140and the light emitting element150. The second interlayer insulating film156is made of a transparent resin. The interlayer insulating film156has a function of protecting the light emitting element150and planarizing a surface for the interconnect layer160formed over the second interlayer insulating film156.

A via (second via)161kis provided to extend through the second interlayer insulating film156. A first end of the via161kis connected to the stepped portion151a.

The via (first via)161dis provided to extend through the interlayer insulating films112and156. A first of the via161dis connected to the interconnect110d.

The interconnect layer160is provided on the planarized interlayer insulating film156. The interconnect layer160includes interconnects160aand160k. The interconnect160ais connected to the p-type semiconductor layer153through a contact hole opened in the interlayer insulating film156. Although not shown in the drawing, the interconnect160ais connected to a power supply line that supplies power to the subpixel20.

The interconnect160kis connected to second ends of the vias161kand161d. Therefore, the n-type semiconductor layer151of the light emitting element150is electrically connected to the main electrode of the transistor103through the vias161kand161dand the interconnects160kand110d.

The surface resin layer170covers the second interlayer insulating film156and the second interconnect layer160. The surface resin layer170is made of a transparent resin, and protects the interlayer insulating film156and the interconnect layer160and provides a planarized surface for bonding the color filter180.

The color filter180includes a light block portion181and a color conversion portion182. The color conversion portion182is provided immediately above the light emitting surface153S of the light emitting element150according to the shape of the light emitting surface153S. In the color filter180, the portion other than the color conversion portion182is a light block portion181. The light block portion181is a so-called black matrix, which reduces blurring due to color mixing of light emitted from the adjacent color conversion portion182and makes it possible to display a sharp image.

The color conversion portion182has one layer or two layers.FIG. 1shows a two-layer color conversion portion182. Whether it is one layer or two layers is determined by the color of light emitted from the subpixel20, that is, the wavelength. In the case in which the emission colors of the subpixels20are red or green, the color conversion portion182preferably has two layers. When the emission color of the subpixel20is blue, it is preferably a single layer.

When the color conversion portion182has two layers, the first layer closer to the light emitting element150is a color conversion layer183and the second layer is a filter layer184. That is, the filter layer184is stacked on the color conversion layer183.

The color conversion layer183is a layer that converts the wavelength of light emitted from the light emitting element150to a desired wavelength. In the case of the subpixel20that emits red light, light having a wavelength of 467 nm±20 nm, which is the wavelength of the light emitting element150, is converted to light having a wavelength of about 630 nm±20 nm, for example. In the case of the subpixel20that emits green light, light having a wavelength of 467 nm±20 nm, which is the wavelength of the light emitting element150, is converted to light having a wavelength of about 532 nm±20 nm, for example.

The filter layer184blocks the wavelength component of blue light emission remaining without being color-converted by the color conversion layer183.

When the color of light emitted from the subpixel20is blue, the subpixel20may output the light through the color conversion layer183or may output the light as it is without the color conversion layer183. When the wavelength of light emitted from the light emitting element150is about 467 nm±20 nm, the subpixel20may output the light without passing through the color conversion layer183. In the case in which the wavelength of light emitted from the light emitting element150is set to 410 nm±20 nm, it is preferable to provide one color conversion layer183in order to convert the wavelength of output light to about 467 nm±20 nm.

Even in the case of the blue subpixel20, the subpixel20may have the filter layer184. By providing the filter layer184on the blue subpixel20, minute external light reflection generated on the surface of the light emitting element150is suppressed.

A modification of the subpixel configuration will be described.

FIG. 2AtoFIG. 2Care schematic cross sectional views illustrating modifications of the image display device according to the present embodiment.

In the cross-sectional views of the subpixels afterFIG. 2A, the display of the surface resin layer170and the color filter180is omitted to avoid complexity. Unless otherwise specified, a surface resin layer and a color filter are provided on the second interlayer insulating film and the second interconnect layer. The same applies to other embodiments described later and modifications thereof.

In the case ofFIG. 2AandFIG. 2B, the subpixels20aand20bare different in the configuration of a light emitting element150afrom that in the first embodiment. Other components are the same as those in the above-described first embodiment, and detailed descriptions thereof will be omitted as appropriate.

As shown inFIG. 2A, the subpixel20aincludes the light emitting element150a. The light emitting element150ais covered with a second interlayer insulating film (second insulating film)256. The second interlayer insulating film256is made of preferably a white resin. When the interlayer insulating film256is made of the white resin, light emitted from the light emitting element150ain the lateral direction or the downward direction can be reflected, and the luminance of the light emitting element150acan be substantially improved.

The second interlayer insulating film256may be made of a black resin. By using the black resin for the interlayer insulating film256, light scattering in the subpixel is suppressed, and stray light is more effectively suppressed. The image display device in which stray light is suppressed can display a sharper image.

The second interlayer insulating film256has an opening158. The opening158is formed by removing a part of the interlayer insulating film256above the light emitting element150a. The interconnect160a1is connected to the p-type semiconductor layer153aexposed through the opening158.

The p-type semiconductor layer153ahas a light emitting surface153S exposed through the opening158. The light emitting surface153S is a surface facing a surface in contact with the light emitting layer152among the surfaces of the p-type semiconductor layer153a. The light emitting surface153S is preferably roughened. The light emitting element150acan improve the light extraction efficiency when the light emitting surface153S is a rough surface.

As shown inFIG. 2B, in the subpixel20b, transparent electrodes159aand159kare provided on interconnects160a2and160k, respectively. The transparent electrode159ais provided on the light emitting surface153S of the opened p-type semiconductor layer153a, and electrically connects the interconnect160a2and the p-type semiconductor layer153a.

By providing the transparent electrode159aon the light emitting surface153S, the connection area with the p-type semiconductor layer153acan be increased, and the light emission efficiency can be improved. When the light emitting surface153S is a rough surface, the connection area between the light emitting surface153S and the transparent electrode159acan be increased, and the contact resistance can be reduced.

FIG. 2Cshows a case in which the positions of the circuit element such as the transistor103and the light emitting element150are shifted from each other on the XY plane.

For the following reasons, the light emitting element150and the transistor130may be arranged so as not to overlap in a plan view. A depletion layer region is generated between the p-type semiconductor region104band the n-type substrate102, and this depletion layer region may function as a parasitic photodiode. It is preferable that the parasitic photodiode does not overlap a light irradiated region generated immediately below the light emitting element150. In that case, it is preferable that the distance between the end when the light emitting layer152is projected on the surface of the substrate102in the XY plan view and the boundary of the p-type semiconductor region104bis separated by at least about 1 μm or more.

As shown inFIG. 2C, in the subpixel20c, an interconnect110s3does not extend to the position where the light emitting element150is placed. That is, the interconnect110s3does not necessarily include the outer peripheral portion of the light emitting element150when projected from above the Z-axis in the XY plan view. On the other hand, the interconnect160k3extends longer in the X-axis direction than in the case of the above-described embodiment and other modifications.

As described above, when the light emitting element150is arranged sufficiently away from the circuit element, scattered light traveling in the negative direction of the Z-axis is reduced, so that malfunction of the circuit element such as the transistor103due to light becomes less likely to occur. When it is not necessary to block light by the interconnect in the circuit board100, because the interconnect is not used for light block, the degree of freedom in circuit arrangement is improved and the integration density can be improved.

The present embodiment can include any of the configurations of the subpixels20to20cdescribed above.

FIG. 3is a schematic block diagram illustrating the image display device according to the present embodiment.

As shown inFIG. 3, the image display device1of the present embodiment includes a display area2. Subpixels20are arranged in the display area2. The subpixels20are arranged in a lattice pattern, for example. For example, n subpixels20are arranged along the X-axis, and m subpixels20are arranged along the Y-axis.

The pixel10includes multiple subpixels20that emit light of different colors. The subpixel20R emits red light. The subpixel20G emits green light. The subpixel20B emits blue light. The three types of subpixels20R,20G, and20B emit light with desired luminance, whereby the emission color and luminance of one pixel10are determined.

One pixel10includes three subpixels20R,20G, and20B, and the subpixels20R,20G, and20B are linearly arranged on the X-axis as in this example, for example. In each pixel10, subpixels of the same color may be arranged in the same column, or subpixels of different colors may be arranged in the same column as in this example.

The image display device1further includes a power line3and a ground line4. The power supply line3and the ground line4are laid out in a lattice pattern along the arrangement of the subpixels20. The power supply line3and the ground line4are electrically connected to each subpixel20, and supply power to each subpixel20from a DC power supply connected between the power supply terminal3aand the GND terminal4a. The power supply terminal3aand the GND terminal4aare provided at the ends of the power supply line3and the ground line4, respectively, and are connected to a DC power supply circuit provided outside the display area2. The power supply terminal3ais supplied with a positive voltage with respect to the GND terminal4a.

The image display device1further includes a scanning line6and a signal line8. The scanning line6is laid out in a direction parallel to the X-axis. In other words, the scanning line6is laid out along the array of the subpixels20in the row direction. The signal line8is laid out in a direction parallel to the Y-axis. That is, the signal line8is laid out along the column-direction arrangement of the subpixels20.

The image display device1further includes a row selection circuit5and a signal voltage output circuit7. The row selection circuit5and the signal voltage output circuit7are provided along the outer edge of the display area2. The row selection circuit5is provided along the Y-axis direction of the outer edge of the display area2. The row selection circuit5is electrically connected to the subpixels20in each column via the scanning line6and supplies a selection signal to each subpixel20.

The signal voltage output circuit7is provided along the outer edge of the display area2. The signal voltage output circuit7is provided along the X-axis direction of the outer edge of the display area2. The signal voltage output circuit7is electrically connected to the subpixels20in each row via the signal line8and supplies a signal voltage to each subpixel20.

The subpixel20includes a light emitting element22, a selection transistor24, a drive transistor26, and a capacitor28. InFIG. 3, the select transistor24may be displayed as T1, the drive transistor26may be displayed as T2, and the capacitor28may be displayed as Cm.

The light emitting element22is connected in series with the drive transistor26. In the present embodiment, the drive transistor26is an n-channel MOSFET, and a cathode electrode that is an n-electrode of the light-emitting element22is connected to a drain electrode that is a main electrode of the drive transistor26. A series circuit of the light emitting element22and the driving transistor26is connected between the power supply line3and the ground line4. The drive transistor26corresponds to the transistor103inFIG. 1and the like, and the light emitting element22corresponds to the light emitting element150inFIG. 1and the like. The current flowing through the light emitting element22is determined by the voltage applied between the gate and the source of the drive transistor26, and the light emitting element22emits light with luminance corresponding to the flowing current through the light emitting element22.

The selection transistor24is connected between the gate electrode of the drive transistor26and the signal line8via the main electrode. The gate electrode of the selection transistor24is connected to the scanning line6. The capacitor28is connected between the gate electrode of the drive transistor26and the ground line4.

The row selection circuit5selects one row from the array of m subpixels20and supplies a selection signal to the scanning line6. The signal voltage output circuit7supplies a signal voltage having a necessary analog voltage value to each subpixel20in the selected row. The signal voltage is applied between the gate and source of the drive transistor26of the subpixel20in the selected row. The signal voltage is held by the capacitor28. The drive transistor26causes a current corresponding to the signal voltage to flow through the light emitting element22. The light emitting element22emits light with luminance according to the flowing current.

The row selection circuit5supplies a selection signal by sequentially switching the rows to be selected. That is, the row selection circuit5scans the row in which the subpixels20are arranged. A current corresponding to the signal voltage flows through the light emitting elements22of the subpixels20that are sequentially scanned to emit light. Each pixel10emits light with the light emission color and luminance determined by the light emission color and luminance emitted by the RGB subpixels20and an image is displayed in the display area2.

FIG. 4is a schematic plan view illustrating a portion of the image display apparatus of the present embodiment.

In the present embodiment, as described inFIG. 1, the light emitting element22(150) and the drive transistor26(103) are stacked in the Z-axis direction, and the cathode electrode of the light emitting element22(150) and the drain electrode of the drive transistor26(103) are electrically connected by the via161d.

A plan view of the layer I is schematically displayed in the upper part ofFIG. 4, and a plan view of the layer II is schematically displayed in the lower part. InFIG. 4, the layer I is denoted as “I” and the second layer is denoted as “II”. The layer I is a layer in which the light emitting element22(150) is formed. That is, inFIG. 1, the layer I includes layers from the buffer layer140to the second interconnect layer160in the positive direction of the Z-axis. InFIG. 4, the buffer layer140and the second interlayer insulating film156are not shown. InFIG. 1, the layer II includes layers from the substrate102to the first interlayer insulating film112in the positive direction of the Z-axis. InFIG. 4, the substrate102, the insulating layer105, the insulating film108, and the first interlayer insulating film112are not shown. In this figure, a channel region104cis shown as the element formation region104.

The cross section inFIG. 1is an arrow cross sectional view taken along the line AA′ at the portion indicated by the dash-dot line in each of the layer I and the layer II.

As shown inFIG. 4, the interconnect160kis connected to the n-type semiconductor layer151serving as a cathode electrode of the light emitting element150through the via161k(FIG. 1) and its contact hole161k1. The interconnect160kis connected to a first end of the via161dthrough a contact hole161d1provided in the second interlayer insulating film156. The via161dis schematically indicated by a two-dot chain line in the drawing.

A second end of the via161dis connected to the interconnect110dthrough a contact hole161d2provided in the first interlayer insulating film112. The interconnect110dis connected to the via111d(FIG. 1) through the contact hole111c1opened in the insulating film108and is connected to the drain electrode of the transistor103. In this manner, the light emitting element150and the transistor103formed in the layer I and the layer II, respectively, which are different layers, can be electrically connected by the via161dextending through the interlayer insulating films156and112.

An arrangement in which the light emission of the light emitting element150is blocked by the interconnect110swill be described with reference toFIG. 4.

The interconnect110shas a light block portion110s1. The light block portion (portion)110s1is a rectangular portion having a length L2in the X-axis direction and a length W2in the Y-axis direction. The light block portion110s1is provided directly below the light emitting element150. The light emitting element150has a rectangular bottom surface having a length L1in the X-axis direction and a length W1in the Y-axis direction.

The length of each portion is set to satisfy L2>L1and W2>W1. Because the light block portion110s1is provided immediately below the light emitting element150, the outer periphery of the light block portion110s1includes the outer periphery of the light emitting element150. The outer periphery of the light block portion110s1only needs to include the outer periphery of the light emitting element150, and the shape of the light block portion110s1is not limited to a square, and can be any appropriate shape.

The light emitting element150emits light upward, and there exist downward light, reflected light or scattered light or the like at the interface between the interlayer insulating film112and the surface resin layer170. Therefore, preferably, the outer periphery of the light block portion110s1is set to include the outer periphery of the light emitting element150projected onto the light block portion110s1in the XY plan view. By setting the light block portion110s1in this way, it is possible to suppress the arrival of light below the light emitting element150and reduce the influence of light on the circuit element.

A method for manufacturing the image display device1of the present embodiment will be described.

FIG. 5AtoFIG. 6Care schematic cross sectional views illustrating the method for manufacturing the image display device of the present embodiment.

As shown inFIG. 5A, a semiconductor growth substrate1194is prepared. The semiconductor growth substrate1194has a semiconductor layer1150grown on a crystal growth substrate (first substrate)1001. The crystal growth substrate1001is, for example, a Si substrate or a sapphire substrate. Preferably, a Si substrate is used.

In this example, a buffer layer1140is formed on one surface of the crystal growth substrate1001. For the buffer layer (buffer layer)1140, a nitride such as AIN is preferably used. The buffer layer1140is used to alleviate mismatch at the interface between the GaN crystal and the crystal growth substrate1001when GaN is epitaxially grown.

In the semiconductor growth substrate1194, an n-type semiconductor layer1151, a light emitting layer1152, and a p-type semiconductor layer are stacked on the buffer layer1140in this order from the buffer layer1140side. For the growth of the semiconductor layer1150, for example, a vapor deposition method (Chemical Vapor Deposition, CVD method) is used, and a metal organic chemical vapor deposition method (MOCVD method) is suitably used. The semiconductor layer1150is, for example, InXAlYGa1-X-YN (0≤X, 0≤Y, X+Y<1) or the like.

As shown inFIG. 5B, after the semiconductor layer1150is formed, a support substrate1190is bonded to the open surface of a p-type semiconductor layer1153on the side opposite to the side on which the crystal growth substrate1001is provided. The support substrate1190is made of, for example, Si or quartz. Thereafter, the crystal growth substrate1001is removed. For example, a laser is used to remove the crystal growth substrate1001.

A circuit board1100is prepared. The circuit board (second substrate)1100includes the circuit101described with reference toFIG. 1or the like.

As indicated by the arrows in the figure, one surface of the circuit board1100and the surface of the buffer layer1140of the semiconductor layer1150are aligned and bonded together. The bonding surface of the circuit board1100is an exposed surface of the interlayer insulating film112formed on the interconnect layer110.

In wafer bonding in which two substrates are bonded together, for example, the two substrates are heated and bonded together by thermocompression bonding. In the thermocompression bonding, a low-melting point metal or a low-melting point alloy may be used. The low-melting point metal is, for example, Sn or In, and the low-melting point alloy can be, for example, an alloy mainly composed of Zn, In, Ga, Sn, Bi, or the like.

In wafer bonding, in addition to the above, the bonding surfaces of the respective substrates are flattened using chemical mechanical polishing (CMP), etc., and then the bonding surfaces may be cleaned and adhered in a vacuum by plasma treatment.

As shown inFIG. 5C, in the wafer bonding, the semiconductor layer1150may be attached to the supporting substrate1190and the crystal growth substrate1001may be removed, and then the buffer layer1140may be removed. The semiconductor layer1150supported by the support substrate1190is bonded to the circuit board1100with the surface of the n-type semiconductor layer1151opened after the buffer layer1140is removed. Alternatively, a semiconductor growth substrate in which the semiconductor layer1150is crystal-grown without providing the buffer layer1140may be used. Hereinafter, a case in which wafer bonding is performed in a state where the buffer layer1140is provided will be described. However, even when the buffer layer1140is omitted, the same manufacturing can be performed.

As shown inFIG. 6AandFIG. 6B, the circuit board1100is bonded to the semiconductor layer1150through the buffer layer1140by wafer bonding. The semiconductor layer1150is formed into the shape of the light emitting element150. For forming the light emitting element150, for example, a dry etching process is used, and preferably, anisotropic plasma etching (Reactive Ion Etching, RIE) is used.

As shown inFIG. 6C, the interlayer insulating film156is formed to cover the light emitting element150. A via hole is formed in the interlayer insulating film156. Thereafter, the via hole is filled with a conductive metal material. Either wet etching or dry etching can be used to form the via hole.

Thereafter, a conductive layer is formed in the via hole by sputtering or the like, and the interconnect layer160is formed by photolithography. After forming the via hole, the via and the interconnect layer may be formed at the same time.

A portion of the circuit other than the subpixel20is formed in the circuit board100. For example, the row selection circuit5(FIG. 3) can be formed in the circuit board100together with a drive transistor, a selection transistor, and the like. That is, the row selection circuit5may be incorporated at the same time by the above manufacturing process. On the other hand, the signal voltage output circuit7is mounted on another substrate together with the CPU and other circuit elements. For example, the signal voltage output circuit7is mutually connected to the interconnect of the circuit board100before or after the incorporation of the color filter described later.

Preferably, the circuit board1100is a wafer including the circuit101. The circuit board1100is formed with the circuit101for one or multiple image display devices. Alternatively, in the case of a larger screen size or the like, the circuit101for constituting one image display device is divided into multiple circuit boards1100, and all the divided circuits are combined and one image display device may be configured.

Preferably, the crystal growth substrate1001is a wafer having the same size as the wafer-like circuit board1100.

Alternatively, the semiconductor layer1150formed on the multiple crystal growth substrates1001may be bonded to one circuit board1100.

FIG. 7AandFIG. 7Bare schematic cross sectional views illustrating a method for manufacturing a modification of the image display device according to the present embodiment.

FIG. 7AandFIG. 7Bshow a manufacturing process for forming the subpixel20aofFIG. 2A. In the modification, the same steps as those in the first embodiment are performed until the second interlayer insulating film256(156) is formed. In the following description, it is assumed that the process ofFIG. 7AandFIG. 7Bis performed after the process ofFIG. 6BorFIG. 6C.

As shown inFIG. 7A, an opening158is formed by etching the second interlayer insulating film256(156), and the surface of the p-type semiconductor layer153is exposed. Etching may be wet etching or dry etching.

Thereafter, the light emitting surface153S of the exposed p-type semiconductor layer153is roughened to improve the light emission efficiency.

As shown inFIG. 7B, the interconnect layer is formed with including the opening158, and the interconnects160a1and160kare formed by photolithography. The interconnect160a1is formed so as to be connected to the light emitting surface153S of the exposed p-type semiconductor layer153.

In this way, the modified subpixel20ais formed.

FIG. 8AandFIG. 8Bare schematic cross sectional views illustrating ae manufacturing method of one modification of the image display device of the present embodiment.

FIG. 8AandFIG. 8Bshow a manufacturing process for forming the subpixel20bshown inFIG. 2B. In the modification, the same processes as those in the above-described modification are performed until the opening158is formed. Therefore, the following description will be made assuming that the processes ofFIG. 8AandFIG. 8Bare executed afterFIG. 7A.

As shown inFIG. 8A, after forming the opening158so as to expose the light emitting surface153S of the p-type semiconductor layer153, the interconnects160a2and160kare formed. The interconnect160a2is not connected to the light emitting surface153S of the p-type semiconductor layer153.

As shown inFIG. 8B, a transparent conductive film is formed to cover the interconnect layer160, the second interlayer insulating film256(156), and the light emitting surface153S of the p-type semiconductor layer153. As the transparent conductive film, an ITO film, a ZnO film, or the like is preferably used. Necessary transparent electrodes159aand159kare formed by photolithography. The transparent electrode159ais formed on the interconnect160a2and also on the light emitting surface153S of the p-type semiconductor layer153. Therefore, the interconnect160a2and the p-type semiconductor layer153are electrically connected. Preferably, the transparent electrode159ais provided so as to cover the entire surface of the exposed light emitting surface153S, and is connected to the light emitting surface153S.

In this way, the subpixel20bof the modification is formed.

FIG. 9is a schematic cross sectional view illustrating the method for manufacturing the image display device of the present embodiment.

InFIG. 9, in order to avoid complication, the display of the interconnect in the circuit board100and the interlayer insulating films112and156is omitted. InFIG. 9, a portion of the color conversion member such as the color filter180is displayed. Here, a structure including the buffer layer140, the light emitting element150, the vias161kand161d, the interconnect layer160, the interlayer insulating film156, and the surface resin layer170is referred to as a light emitting circuit portion172. A structure in which the light emitting circuit portion172is provided over the circuit board100is referred to as a structure body1192.

As shown inFIG. 9, a first surface of the color filter180is adhered to the structure body1192. A second surface of the color filter180is adhered to a glass substrate186. A transparent thin film adhesive layer188is provided on a first surface of the color filter180, and the color filter180is adhered to the surface of the structure body1192on the light emitting circuit portion172side through the transparent thin film adhesive layer188.

In this example, the color filter180includes color conversion portion arranged in the positive direction of the X-axis in the order of red, green, and blue. For red and green, a red color conversion layer183R and a green color conversion layer183G are provided in the first layer, and a filter layer184is provided in the second layer. For blue, a color conversion layer183B of a monolayer is provided. A light block portion181is provided between the color conversion portions.

The color filter180is attached to the structure body1192so that the color conversion layers183R,183G, and183B of the respective colors are aligned with the position of the light emitting element150.

FIG. 10AtoFIG. 10Dare schematic cross sectional views showing a modification of the manufacturing method of the modification of the image display device of the present embodiment.

FIG. 10AtoFIG. 10Dshow a method for forming a color filter by ink jetting.

As shown inFIG. 10A, a structure body1192in which a light emitting circuit portion172is attached to a circuit board100is prepared.

As shown inFIG. 10B, a light block portion181ais formed over the structure body1192. The light block portion181ais formed by using, for example, screen printing or photolithography technology.

As shown inFIG. 10C, the phosphor183acorresponding to the emission color is ejected from the inkjet nozzle. The phosphor183acolors a region where the light block portion181ais not formed. As the phosphor183a, for example, a fluorescent paint using a general phosphor material or a quantum dot phosphor material is used. The use of a quantum dot phosphor material is preferable because each emission color can be realized, monochromaticity is high, and color reproducibility can be enhanced. After drawing with an inkjet nozzle, a drying process is performed at an appropriate temperature and time. The thickness of the coating film at the time of coloring is set to be thinner than the thickness of the light block portion181a.

As already described, because the color conversion portion may not be formed for the blue light emitting subpixel, the phosphor is not ejected. Further, in the case of forming a blue color conversion layer for the blue light emitting subpixel, the color conversion portion may be a single layer. Therefore, preferably, the thickness of the coating film of the blue phosphor is set to the same level as thickness of the light block portion181a.

As shown inFIG. 10D, the paint184afor the filter layer is ejected from the inkjet nozzle. The paint184ais applied to overlap the coating film of the phosphor183a. The total thickness of the coating film of the phosphor183aand the paint184ais set to the same level as the thickness of the light block portion181a.

In this way, the image display device1can be manufactured.

The effect of the image display device1of this embodiment is demonstrated.

In the method for manufacturing the image display device1according to the present embodiment, the semiconductor layer1150including the light emitting layer1152for the light emitting element150is bonded together the circuit board1100(100) including the circuit elements such as the transistor103that drives the light emitting element150. After that, the light emitting element150is formed by etching the semiconductor layer1150. Therefore, the process of transferring the light emitting elements can be significantly shortened as compared with the case of individually transferring the individualized light emitting elements on the circuit board1100(100).

For example, in a 4K image display device, the number of subpixels exceeds 24 million, and in the case of an 8K image display device, the number of subpixels exceeds 99 million. Mounting such a large number of light emitting elements individually on the circuit board requires an enormous amount of time, and it is difficult to realize an image display device using micro LEDs at a realistic cost. Further, if a large number of light emitting elements are individually mounted, the yield due to poor connection at the time of mounting or the like is lowered, and further cost increase is inevitable.

On the other hand, in the method for manufacturing the image display device1of the present embodiment, the entire semiconductor layer1150is attached to the circuit board1100(100) before the semiconductor layer1150is separated into individual pieces, so that the transfer process is completed once.

After the light emitting element is directly formed on the circuit board by etching or the like, the light emitting element and the circuit element in the circuit board1100(100) are electrically connected by forming a via, so that a uniform connection structure is realized. And a decrease in yield can be suppressed.

Furthermore, because the semiconductor layer1150is attached to the circuit board1100(100) at a wafer level without individualizing the semiconductor layer1150in advance or forming electrodes at positions corresponding to the circuit elements, alignment is not necessary. Therefore, it is possible to easily perform the attaching process in a short time. Because it is not necessary to align at the time of attachment, the light emitting element150can be easily downsized and is suitable for a high-definition display.

Second Embodiment

FIG. 11is a schematic cross-sectional view illustrating a portion of the image display device according to the present embodiment.

In the present embodiment, the configuration of a light emitting element250and the configuration of a transistor203that drives the light emitting element250are different from those in the other embodiments described above. The same components as those in the other embodiments described above are denoted by the same reference numerals, and detailed descriptions thereof is omitted as appropriate.

As shown inFIG. 11, a subpixel220of the image display device according to the present embodiment includes a transistor203and a light emitting element250. The transistor203is formed in an element formation region204formed in the substrate102. The element formation region204includes an n-type semiconductor region204band p-type semiconductor regions204sand204d. The n-type semiconductor region204bis provided near the surface of the substrate102. The p-type semiconductor regions204sand204dare provided in the n-type semiconductor region204bnear the surface of the n-type semiconductor region204bso as to be separated from each other.

A gate107is provided on the n-type semiconductor region204bwith the insulating layer105interposed therebetween. The gate107is provided between the p-type semiconductor regions204sand204d.

The structure of the upper portion of the transistor203and the structure of the interconnect are the same as those in the other embodiments described above. In the present embodiment, the transistor203is a p-channel MOSFET.

The light emitting element250includes a p-type semiconductor layer (first semiconductor layer)253, a light emitting layer252, and an n-type semiconductor layer (second semiconductor layer)251. The p-type semiconductor layer253, the light emitting layer252and the n-type semiconductor layer251are stacked in this order from the first interlayer insulating film112of the circuit board100toward a light emitting surface251S. The light emitting element250has, for example, a substantially square or rectangular shape in the XY plan view, but the corners may be rounded. The light emitting element250may have, for example, an elliptical shape or a circular shape in the XY plan view. By appropriately selecting the shape and arrangement of the light emitting elements in the plan view, the degree of freedom in layout is improved. In this example, the p-type semiconductor layer253has a stepped portion253aextending on the first interlayer insulating film112in the X-axis direction.

The light emitting element250may be made of the same material as in the other embodiments described above. The light emitting element250emits, for example, blue light having a wavelength of about 467 nm±20 nm or blue-violet light having a wavelength of 410 nm±20 nm.

In the present embodiment, the light emitting element250is provided on the interlayer insulating film (first insulating film)112without using a buffer layer.

The second interlayer insulating film (second insulating film)256covers the first interlayer insulating film112and the light emitting element250. The second interlayer insulating film256has an opening258. The opening258is formed on the light emitting element250, and the interlayer insulating film256is not provided on the light emitting surface251S of the light emitting element250. The interlayer insulating film256is preferably made of a white resin so that the light emitted from the light emitting element250is reflected and is effectively output from the opening258.

The light emitting surface251S is a surface facing the surface in contact with the light emitting layer252among the surfaces of the n-type semiconductor layer251. The light emitting surface251S is roughened.

A via (second via)261ais provided through the interlayer insulating film256. A first end of the via261ais connected to the stepped portion253a.

The via (first via)161dis provided through the interlayer insulating films112and256. A first end of the via161dis connected to the interconnect110d.

An interconnect layer260is provided on the interlayer insulating film256. The interconnect layer260includes interconnects260kand260a. The interconnect260ais connected to second ends of the vias261aand161d. Therefore, the p-type semiconductor layer253of the light emitting element250is electrically connected to the main electrode of the transistor203through the vias261aand161d.

Although not shown, the interconnect260kis connected to a ground line. A transparent electrode259kis provided on the interconnect260k. The transparent electrode259kextends to the light emitting surface251S and is provided over the entire surface of the light emitting surface251S. Therefore, the n-type semiconductor layer251is connected to the ground line via the transparent electrode259kand the interconnect260k.

A transparent electrode259ais also disposed on the interconnect260a.

A surface resin layer170is provided on the interlayer insulating film256and the transparent electrodes259kand259a.

FIG. 12is a schematic block diagram illustrating the image display device according to the present embodiment.

As shown inFIG. 12, the image display device201of the present embodiment includes the display area2, a row selection circuit205, and a signal voltage output circuit207. In the display area2, for example, the subpixels220are arranged in a lattice pattern as in the case of the other embodiments described above.

In the present embodiment, a light emitting element222is provided on the ground line4side, and a drive transistor226connected in series to the light emitting element222is provided on the power supply line3side. That is, the drive transistor226is connected to a higher potential side than the light emitting element222. The drive transistor226is a p-channel MOSFET.

A selection transistor224is connected between the gate electrode of the drive transistor226and a signal line208. A capacitor228is connected between the gate electrode of the drive transistor226and the power supply line3.

The row selection circuit205and the signal voltage output circuit207supply a selection signal and a signal voltage having different polarities from those of the other embodiments described above to a scanning line206and the signal line208in order to drive the drive transistor226which is the p-channel MOSFET.

In the present embodiment, because the polarity of the drive transistor226is a p-channel, the polarity of the selection signal and the signal voltage is different from those in the other embodiments described above. That is, the row selection circuit205supplies a selection signal to the scanning line206so as to sequentially select one row from the arrangement of the m rows of subpixels220. The signal voltage output circuit207supplies a signal voltage having a necessary analog voltage value to each subpixel220in the selected row. The drive transistor226of the subpixel220in the selected row passes a current corresponding to the signal voltage to the light emitting element222. The light emitting element222emits light with luminance according to the flowing current.

A method for manufacturing the image display device201of the present embodiment will be described.

FIG. 13AandFIG. 13Bare schematic cross-sectional views illustrating the method for manufacturing the image display device according to the present embodiment.

In the present embodiment, the semiconductor growth substrate1194already described with reference toFIG. 5Ais used. Hereinafter, processes after the semiconductor growth substrate1194having the semiconductor layer1150epitaxially grown on the crystal growth substrate1001via the buffer layer1140is prepared will be described.

As shown inFIG. 13A, in the present embodiment, without removing the crystal growth substrate1001from the semiconductor growth substrate1194, the semiconductor growth substrate1194is turned upside down and attached to the circuit board1100. That is, the exposed surface of the p-type semiconductor layer1153opposite to the crystal growth substrate1001is attached to the planarized surface of the interlayer insulating film112of the circuit board1100by wafer bonding, as indicated by the arrows in the figure. Wafer bonding can be performed in the same manner as in the other embodiments described above.

As shown inFIG. 13B, the crystal growth substrate1001is removed by laser irradiation or the like.

As shown inFIG. 14A, the semiconductor layer1150is etched together with the buffer layer1140to form the light emitting element250. Because a buffer layer240remains on the light emitting element250, the buffer layer240is removed by further etching. The buffer layer240may be removed before the light emitting element250is formed.

As shown inFIG. 14B, the second interlayer insulating film256that covers the first interlayer insulating film112and the light emitting element250is formed. Thereafter, a via hole is formed so as to extend through the second interlayer insulating film256. A conductive metal material is filled in the via hole.

The opening258is formed in the second interlayer insulating film256, and the light emitting surface251S of the n-type semiconductor layer251is exposed. The opening258is formed by either a wet or dry etching method.

Thereafter, the light emitting surface251S of the exposed n-type semiconductor layer251is roughened to improve the light emission efficiency.

A interconnect layer is formed with including the opening258, and the interconnects260kand260aare formed by photolithography. The interconnect260ais connected to the vias261aand161d. The interconnect260kis connected to a ground line (not shown).

Thereafter, transparent electrodes259aand259kare provided on the interconnects260aand260k, respectively. The transparent electrode259kis provided extending to the light emitting surface251S. The transparent electrode259kis provided over the entire surface of the light emitting surface251S. Therefore, the n-type semiconductor layer251is connected to the ground line4via the transparent electrode259kand the interconnect260k.

FIG. 15is a schematic cross-sectional view illustrating a portion of a modification of the image display device according to the modification of the present embodiment.

As shown inFIG. 15, in the modification, the interconnect and the light emitting surface are electrically connected without using the transparent electrode. In a subpixel220a, an interconnect260k1is patterned so as to be directly connected to the n-type semiconductor layer251without passing through the transparent electrode.

In the present embodiment, from the viewpoint of light emission efficiency, it is preferable to roughen the light emitting surface of the n-type semiconductor layer. As in the case of the first embodiment, light may be emitted through the transparent interlayer insulating film156without roughening the surface.

The effect of the image display device201of the present embodiment will be described.

The present embodiment also has the same effects as those of the other embodiments described above. That is, because the individual light emitting elements250are formed by etching after the semiconductor layer1150is bonded together the circuit board1100, the transfer process of the light emitting elements can be significantly shortened.

In addition to the effects of the other embodiments described above, in the present embodiment, the n-type semiconductor layer251can be used as the light emitting surface251S, so that the surface can be more easily roughened. By connecting the interconnect260k1to the light emitting surface251S, subpixels with high light emission efficiency can be formed.

Third Embodiment

In the present embodiment, an image display device with higher light emission efficiency is realized by forming multiple light emitting surfaces corresponding to multiple light emitting elements in a single semiconductor layer including a light emitting layer. In the following description, the same components as those in the other embodiments described above are denoted by the same reference numerals, and detailed descriptions thereof is omitted as appropriate.

FIG. 16is a schematic cross sectional view illustrating a portion of the image display device according to the present embodiment.

As shown inFIG. 16, the image display device includes a subpixel group320. The subpixel group320includes transistors103-1,103-2, a first interconnect layer310, a first interlayer insulating film112, a semiconductor layer350, a second interlayer insulating film356, a second interconnect layer360, and vias361d1and361d2.

The semiconductor layer350includes two light emitting surfaces351S1and351S2, and the subpixel group320includes substantially two subpixels. In the present embodiment, as in the other embodiments described above, the display area is formed by arranging subpixel groups320including substantially two subpixels in a lattice pattern.

The transistors103-1and103-2are formed in the element formation regions104-1and104-2, respectively. In this example, the element formation regions104-1and104-2are n-type semiconductor layers, and a p-type semiconductor layer formed separately from the n-type semiconductor layer is formed. The n-type semiconductor layer includes a channel region, and the p-type semiconductor layer includes a source region and a drain region, respectively.

The insulating layer105is formed over the element formation regions104-1and104-2, and gates107-1and107-2are formed via the insulating layer105, respectively. Gates107-1and107-2are the gates of the transistors103-1and103-2. In this example, the transistors103-1and103-2are p-channel MOSFETs.

The insulating film108covers the two transistors103-1and103-2. The interconnect layer (first interconnect layer)310is formed on the insulating film108.

Vias111s1and111d1are provided between the p-type semiconductor layer of the transistor (first transistor)103-1and the interconnect layer310, respectively. Vias111s2and111d2are provided between the p-type semiconductor layer of the transistor (second transistor)103-2and the interconnect layer310.

The first interconnect layer310includes interconnects310s,310d1, and310d2. The interconnect310sis electrically connected to the p-type semiconductor layer corresponding to the source electrodes of the transistors103-1and103-2through the vias111s1and111s2. Although not shown, the interconnect310sis connected to a power supply line.

The interconnect310d1is connected to the p-type semiconductor layer corresponding to the drain electrode of the transistor103-1via the via111d1. The interconnect310d2is connected to the drain electrode of the transistor103-2through the via111d2.

The first interlayer insulating film (first insulating film)112covers the transistors103-1and103-2and the interconnect layer310. The semiconductor layer350is provided above the interlayer insulating film112. The single semiconductor layer350is provided between two drive transistors103-1and103-2arranged along the X-axis direction.

The semiconductor layer350includes a p-type semiconductor layer (first semiconductor layer)353, a light emitting layer352, and an n-type semiconductor layer (second semiconductor layer)351. The semiconductor layer350is stacked in the order of the p-type semiconductor layer353, the light emitting layer352, and the n-type semiconductor layer351from the interlayer insulating film112side toward the light emitting surfaces351S1and351S2. The p-type semiconductor layer353has stepped portions353a1and353a2. The stepped portion353a1is provided on the transistor103-1side, and the stepped portion353a2is provided on the transistor103-2side.

The second interlayer insulating film (second insulating film)356covers the first interlayer insulating film112and the semiconductor layer350. The interlayer insulating film356covers a portion of the semiconductor layer350. Preferably, the interlayer insulating film356covers the surface of the n-type semiconductor layer351except for the light emitting surface (exposed surface)351S1and351S2of the semiconductor layer350. The interlayer insulating film356covers the side surface of the semiconductor layer350and the stepped portions353a1and353a2. The interlayer insulating film356is preferably a white resin.

A portion of the semiconductor layer350that is not covered with the interlayer insulating film356is covered with the transparent electrode359k. The transparent electrode359kis provided on the light emitting surfaces351S1and351S2of the n-type semiconductor layer351exposed from the openings358-1and358-2of the interlayer insulating film356, respectively. The transparent electrode359kis electrically connected to the n-type semiconductor layer351.

Vias361a1and361a2are provided through the interlayer insulating film356. One end of each of the vias361a1and361a2is connected to the stepped portions353a1and353a2.

The vias361d1and361d2are provided through the interlayer insulating films356and112. One end of each of the vias361d1and361d2are connected to the interconnects310d1and310d2, respectively.

The second interconnect layer (second interconnect layer)360is provided on the interlayer insulating film356. The interconnect layer360includes interconnects360a1and360a2. The via (first via)361d1is provided between the interconnect (first conductor)310d1and the interconnect (second conductor)360a1. The via (second via)361d2is provided between the interconnect (third conductor)310d2and the interconnect (fourth conductor)360a2.

The interconnect360a1is connected to the p-type semiconductor layer353through the via361a1. The interconnect360a2is connected to the p-type semiconductor layer353through the via361a2. Therefore, the p-type semiconductor layer353is connected to the drain electrode of the transistor103-1through the interconnect360a1, the via361d1, and the interconnect310d1. The p-type semiconductor layer353is connected to the drain electrode of the transistor103-2through the interconnect360a2, the via361d2, and the interconnect310d2.

The interconnect layer360includes an interconnect360k. The transparent electrode359kis provided on the interconnect360k, and the interconnect360kand the transparent electrode359kare electrically connected. The transparent electrode359kextends to the openings358-1and358-2. The transparent electrode359kis provided over the entire surface of the light emitting surfaces351S1and351S2exposed from the openings358-1and358-2, and is electrically connected. Transparent electrodes359a1and359a2are also provided on the interconnects360a1and360a2, respectively, and are electrically connected to each other.

The opening358-1is provided between the interconnects360a1and360k. The opening358-2is provided between the interconnects360kand360a2. In this example, the interconnect360kis provided between the openings358-1and358-2. The openings358-1and358-2are, for example, square or rectangular in the XY plan view. The shape is not limited to a square, and may be a circle, an ellipse, or a polygon such as a hexagon. The light emitting surfaces351S1and351S2are also square or rectangular, other polygons or circles, etc. in the XY plan view. The shapes of the light emitting surfaces351S1and351S2may be similar to the shapes of the openings358-1and358-2, or may be different.

As described above, the transparent electrode359kis connected to the light emitting surfaces351S1and351S2exposed from the openings358-1and358-2, respectively. Therefore, electrons supplied from the transparent electrode359kare injected into the n-type semiconductor layer351from the exposed light emitting surfaces351S1and351S2. On the other hand, holes are injected into the p-type semiconductor layer353from the transistor103-1through the interconnect360a1, the via361d1, and the interconnect310d1. Further, holes are injected from the transistor103-2into the p-type semiconductor layer353through the interconnect360a2, the via361d2, and the interconnect310d2.

Transistors103-1and103-2are drive transistors of adjacent subpixels, and are sequentially driven. Therefore, holes injected from one of the two transistors103-1and103-2are injected into the light emitting layer352, and electrons injected from the interconnect360kare injected into the light emitting layer352to emit light.

Here, because the opening358-1is provided between the interconnect360kand the interconnect360a1, when the transistor103-1is turned on, light is emitted from the light emitting surface351S1exposed from the opening358-1. On the other hand, because the opening358-2is provided between the interconnect360kand the interconnect360a2, when the transistor103-2is turned on, light is emitted from the light emitting surface351S2exposed from the opening358-2.

A method for manufacturing the image display device of the present embodiment will be described.

FIG. 17AtoFIG. 18Bare schematic cross sectional views illustrating the method for manufacturing the image display device according to the present embodiment.

As shown inFIG. 17A, a semiconductor growth substrate1194including a crystal growth substrate1001on which a semiconductor layer1150is epitaxially grown is bonded to a circuit board3100each other by wafer bonding. The semiconductor layer1150and the like on the crystal growth substrate1001are the same as those already described in the case of the other embodiments described above, and detailed descriptions thereof is omitted. The circuit board3100is also similar in structure to that already described in most other parts, although the circuit configuration is different from that of the other embodiments described above. Hereinafter, only the reference numerals are changed, and detailed description is omitted as appropriate.

As shown inFIG. 17B, in this example, the surface of the semiconductor layer1150opposite to the surface on which the crystal growth substrate1001is provided is bonded to the flat surface of the interlayer insulating film112of the circuit substrate3100. That is, the exposed surface of the p-type semiconductor layer1153of the semiconductor layer1150is bonded to the interlayer insulating film112.

As shown inFIG. 18A, the semiconductor layer1150is etched to form an end portion of the p-type semiconductor layer353. Stepped portions353a1and353a2for via connection are formed at the end of the p-type semiconductor layer353. The light emitting layer352and the n-type semiconductor layer351are formed on the p-type semiconductor layer353other than the stepped portion.

Thereafter, an interlayer insulating film covering the interlayer insulating film356and the semiconductor layer350is formed, and a via is formed. Further, the interconnect layer360is formed, and the interconnects360a1,360kand the like are formed by etching.

As shown inFIG. 18B, the openings358-1and358-2are formed in a portion between the interconnects360a1and360kand a portion between the interconnects360a2and360k, respectively. The light emitting surfaces351S1and351S2of the n-type semiconductor layer exposed by the openings358-1and358-2are roughened, respectively. Thereafter, the transparent electrodes359a1,359a2, and359kare formed.

In this way, a subpixel having the semiconductor layer350sharing the two light emitting surfaces351S1and351S2is formed.

In the present embodiment, the two light emitting surfaces351S1and351S2are provided in one semiconductor layer350. However, the number of light emitting surfaces is not limited to two, and it is possible to provide three or more light emitting surfaces on one semiconductor layer350. As an example, one column or two columns of subpixels may be realized by a single semiconductor layer350. As a result, as will be described later, the recombination current that does not contribute to light emission per light emitting surface can be reduced, and the effect of realizing a finer light emitting element can be increased.

FIG. 19is a schematic cross sectional view illustrating a portion of a modification of the image display device according to the modification of the present embodiment.

The modification is different from the above-described third embodiment in that two n-type semiconductor layers3351a1and3351a2are provided on the light emitting layer352. The other points are the same as those in the third embodiment.

As shown inFIG. 19, the image display device according to the modification includes a subpixel group320a. The subpixel group320aincludes a semiconductor layer350a. The semiconductor layer350aincludes the p-type semiconductor layer353, the light emitting layer352, and n-type semiconductor layers3351a1and3351a2. The p-type semiconductor layer353, the light emitting layer352, and the n-type semiconductor layers3351a1and3351a2are stacked in this order from the interlayer insulating film356toward the light-emitting surfaces3351S1and3351S2.

The n-type semiconductor layers3351a1and3351a2are arranged on the light emitting layer352so as to be separated along the X-axis direction. The interlayer insulating film356is provided between the n-type semiconductor layers3351a1and3351a2, and the n-type semiconductor layers3351a1and3351a2are separated by the interlayer insulating film356. On the interlayer insulating film356, the interconnect360kis provided.

The n-type semiconductor layers3351a1and3351a2have substantially the same shape in the XY plan view, and the shape thereof is substantially square or rectangular, and may be other polygonal shapes, circles, or the like.

The n-type semiconductor layers3351a1and3351a2have light emitting surfaces3351S1and3351S2, respectively. The light emitting surfaces3351S1and3351S2are surfaces of the n-type semiconductor layers3351a1and3351a2exposed through the openings358-1and358-2, respectively.

The shape of the light emitting surfaces3351S1and3351S2in the XY plan view has substantially the same shape as the shape of the light emitting surface in the third embodiment, and has a shape such as a substantially square shape. The shape of the light emitting surfaces3351S1and3351S2is not limited to a square shape as in the present embodiment, but may be a polygon such as a circle, an ellipse, or a hexagon. The shapes of the light emitting surfaces3351S1and3351S2may be similar to the shapes of the openings358-1and358-2, or may be different.

The transparent electrode359kis provided on the light emitting surface3351S1. The transparent electrode359kis also provided on the light emitting surface3351S2. The transparent electrode359kis also provided on the interconnect360k, and the n-type semiconductor layers3351a1and3351a2are connected to the interconnect360kvia the transparent electrode359kconnected to the light emitting surfaces3351S1and3351S2. Although not shown, the interconnect360kis connected to the GND line.

FIG. 20AandFIG. 20Bare schematic cross sectional views illustrating the method for manufacturing the image display device according to the modification.

In the modification, until the semiconductor layer1150is formed, processes similar to those described inFIG. 17AtoFIG. 18Ain the case of the third embodiment are employed. Below, the process after that is demonstrated.

As shown inFIG. 20A, in the modification, after the buffer layer1140, the n-type semiconductor layer1151, the light-emitting layer1152, and the p-type semiconductor layer1153are etched to form the light emitting layer352and the p-type semiconductor layer353, further, two n-type semiconductor layers3351a1and3351a2are formed by etching. A buffer layer340aon the two n-type semiconductor layers3351a1and3351a2is then removed. The buffer layer340amay be removed before the n-type semiconductor layers3351a1and3351a2are etched, depending on the state of the manufacturing process to be used.

The n-type semiconductor layers3351a1and3351a2may be formed by etching more deeply. For example, the etching for forming the n-type semiconductor layers3351a1and3351a2may be performed until reaching the depth in the light emitting layer352or the p-type semiconductor layer353. Thus, when the n-type semiconductor layer is etched deeply, it is desirable that the etching position of the n-type semiconductor layer351is separated from the light emitting surfaces3351S1and3351S2of the n-type semiconductor layer described later by 1 μm or more. The recombination current can be suppressed by separating the etching position from the light emitting surfaces3351S1and3351S2.

As shown inFIG. 20B, an interlayer insulating film covering interlayer insulating film112and semiconductor layer3350ais formed, and then a via is formed. Further, the interconnect layer360is formed, and the interconnects360a1,360kand the like are formed by etching.

The openings358-1and358-2are formed in the interlayer insulating film, respectively. The light emitting surfaces3351S1and3351S2of the n-type semiconductor layer exposed by the openings358-1and358-2are roughened, respectively. Thereafter, the transparent electrodes359a1,359a2, and359kare formed.

In this manner, the subpixel group320ahaving two light emitting surfaces3351S1and3351S2is formed.

Also in the case of the modification, the number of light emitting surfaces is not limited to two as in the case of the third embodiment, and three or more light emitting surfaces may be provided in one semiconductor layer3350.

The effect of the image display device of the present embodiment will be described.

FIG. 21is a graph illustrating characteristics of the pixel LED.

The vertical axis inFIG. 21represents light emission efficiency [%]. The horizontal axis represents the current density of a current flowing through the pixel LED as a relative value.

As shown inFIG. 21, in the region where the relative value of the current density is smaller than 1.0, the light emission efficiency of the pixel LED is almost constant or increases monotonously. In the region where the relative value of the current density is larger than 1.0, the light emission efficiency decreases monotonously. That is, the pixel LED has an appropriate current density that maximizes the light emission efficiency.

It is expected that a highly efficient image display device can be realized by suppressing the current density to such an extent that sufficient luminance can be obtained from the light emitting element. However,FIG. 21shows that the light emission efficiency tends to decrease as the current density decreases at a low current density.

As described in the first embodiment and the second embodiment, the light emitting element is formed by individually separating all layers of the semiconductor layer1150including the light emitting layer by etching or the like. At this time, the bonding surface between the light emitting layer and the n-type semiconductor layer is exposed at the end portion. Similarly, the bonding surface between the light emitting layer and the p-type semiconductor layer is exposed at the end portion.

When such an end exists, electrons and holes recombine at the end portion. On the other hand, such recombination does not contribute to light emission. The recombination at the end portion occurs almost independently of the current flowing through the light emitting element. The recombination is considered to occur according to the length of the bonding surface that contributes to the light emission at the end portion.

When two light emitting elements having a cubic shape having the same size are caused to emit light, the end portions are formed in four directions for each light emitting element, and therefore, recombination may occur at a total of eight end portions.

In contrast, in the present embodiment, the semiconductor layers350,350a, and3350ahaving two light emitting surfaces have four end portions. The region between the openings358-1and358-2has few injections of electrons and holes and hardly contributes to light emission. Therefore, it can be considered that there are six end portions contributing to light emission. Thus, in the present embodiment, the number of end portions is substantially reduced, so that recombination that does not contribute to light emission can be reduced, and it becomes possible to reduce the drive current accordingly.

When the distance between subpixels is shortened or the current density is relatively high for high definition or the like, in the subpixel group320of the third embodiment, the distance between the light emitting surfaces351S1and351S2becomes shorter. In this case, if the n-type semiconductor layer351is shared, a portion of the electrons injected to the adjacent light emitting surface may be diverted, and the light emitting surface on the side that is not driven may slightly emit light. In the modification, because the n-type semiconductor layer is separated for each light emitting surface, generation of slight light emission on the light emitting surface that is not driven can be reduced.

In the present embodiment, the semiconductor layer including the light emitting layer is formed by stacking the p-type semiconductor layer, the light emitting layer, and the n-type semiconductor layer in this order from the interlayer insulating film side, and the exposed surface of the n-type semiconductor layer is roughened. This is preferable from the viewpoint of improving the light emission efficiency. As in the case of the first embodiment, the stacking order of the p-type semiconductor layer and the n-type semiconductor layer may be changed, and the n-type semiconductor layer, the light emitting layer, and the p-type semiconductor layer may be stacked in this order.

Fourth Embodiment

The image display device described above can be, for example, a computer display, a portable terminal such as a TV or a smartphone, or a car navigation as an image display module having an appropriate number of pixels.

FIG. 22is a block diagram illustrating an image display device according to the present embodiment.

FIG. 22shows a main part of the configuration of the computer display.

As shown inFIG. 22, an image display device401includes an image display module402. The image display module402is an image display device having the configuration of the first embodiment described above, for example. The image display module402includes the display area2in which the subpixels20are arranged, the row selection circuit5, and the signal voltage output circuit7.

The image display device401further includes a controller470. The controller470receives control signals separated and generated by an interface circuit (not shown), and controls the drive and drive sequence of the subpixels with respect to the row selection circuit5and the signal voltage output circuit7.

FIG. 23is a block diagram illustrating an image display device according to the modification.

FIG. 23shows the configuration of a high-definition thin TV.

As shown inFIG. 23, an image display device501includes an image display module502. The image display module502is, for example, the image display device1having the configuration in the case of the first embodiment described above. The image display device501includes a controller570and a frame memory580. The controller570controls the driving order of the subpixels in the display area2based on the control signal supplied by a bus540. The frame memory580stores display data for one frame and is used for processing such as smooth moving image reproduction.

The image display device501has an I/O circuit510. The I/O circuit510provides an interface circuit or the like for connecting to an external terminal or device. The I/O circuit510includes, for example, a USB interface for connecting an external hard disk device or the like, an audio interface, or the like.

The image display device501includes a tuner520and a signal processing circuit530. An antenna522is connected to the tuner520, and a necessary signal is separated from a radio wave received by the antenna522and generated. The signal processing circuit530includes a DSP (Digital Signal Processor), a CPU (Central Processing Unit), and the like. The signal separated and generated by the tuner520is separated into image data, audio data, and the like by the signal processing circuit530, and generated.

By using the tuner520and the signal processing circuit530as a high-frequency communication module such as a cellular phone transmission/reception device, WiFi device, or GPS receiver, another image display device can be obtained. For example, an image display device including an image display module having an appropriate screen size and resolution can be a portable information terminal such as a smartphone or a car navigation system.

The image display module in the case of the present embodiment is not limited to the configuration of the image display device in the case of the first embodiment, and may be modified examples thereof or other embodiments.

FIG. 24is a perspective view illustrating each of the image display devices of the first to the third embodiment and the modifications.

As shown inFIG. 24, in each of the image devices of the first to the third embodiment, the light emitting circuit portion172which has a lot of subpixels is provided on the circuit substrate100. The color filter180is provided on the circuit substrate100. In the fourth embodiment and the modification, structures including the circuit substrates100, the light emitting circuit portions172and the color filters180are image display modules402,502, which are built in the image displays respectively.

According to the embodiment described above, it is possible to realize a method of manufacturing an image display device and an image display device that shorten the transfer process of the light emitting elements and improve the yield.