DETECTOR OF TERAHERTZ BAND, RECEIVER HAVING THE SAME, AND IMAGING SYSTEM USING THE SAME

A receiver according to an embodiment is a terahertz band receiver including an antenna configured to receive a terahertz band signal reflected or transmitted from a measurement target, a detector configured to receive a differential signal including a first input signal VTHz and a second input signal −VTHz with phase difference of 180° to each other from the antenna to detect a voltage, and operate in a concurrent mode, and a buffer amplifier configured to amplify and output a signal detected by the detector.

PRIORITY

This application claims the benefit under 35 USC § 119 of Korean Patent Application No. 10-2022-0069649 filed on Jun. 8, 2022 in the Korean Intellectual Property Office (KIPO), the entire disclosure of which is incorporated herein by reference for all purposes.

BACKGROUND

Embodiments of the present disclosure relate to a receiver of terahertz band.

2. Description of Related Art

Terahertz (THz) waves refer to electromagnetic waves with frequencies in a band ranging from 0.1 THz to 10 THz. Since terahertz waves are lying between radio waves and light waves and have high transmittance and directivity, they are expected to be widely used in security imaging, radio astronomy, and medical imaging. In particular, the terahertz imaging system is capable of non-destructive inspection due to its low ionization energy for frequency, and terahertz waves are attracting attention as a frequency resource to replace millimeter waves as they can be used for communication beyond the limits of short wavelengths.

The performance of a THz imaging system can be expressed as a signal-to-noise ratio (SNR) in which a receiver detects and outputs a signal reflected or transmitted from a measurement target while the measurement target is placed independently between a transmitter and the receiver. The signal-to-noise ratio, which represents an image quality factor, can be calculated as a ratio between an output signal when a transmitted signal is reflected by a metal target and an output signal when the transmitted signal passes through a non-reflective target.

Meanwhile, a receiver with high sensitivity improves the performance of the imaging system, and the sensitivity of the receiver is measured based on voltage responsivity and noise equivalent power. Here, the voltage responsivity represents the magnitude of an output voltage as a function of input signal power, and the noise equivalent power represents noise characteristic of the receiver. Since the voltage responsivity and the noise equivalent power are in inverse proportion, increasing the voltage responsivity reduces the noise equivalent power, thereby enabling high sensitivity characteristics of the receiver to be achieved.

SUMMARY

An embodiment of the present disclosure is to provide a detector of terahertz band capable of realizing high sensitivity, a receiver having the same, and an imaging system using the same.

A receiver according to the disclosed embodiment is a receiver of terahertz band including an antenna configured to receive a terahertz band signal reflected or transmitted from a measurement target, a detector configured to receive differential signals including a first input signal VTHzand a second input signal −VTHzwith phase difference of 180° to each other from the antenna to detect a voltage, and operate in a concurrent mode, and a buffer amplifier configured to amplify and output a signal detected by the detector.

The detector may include a first CMOS of which a gate is connected to a first input terminal to which the first input signal VTHzis input, a drain is connected to a first output terminal, and a source is connected to ground, a second CMOS of which a gate is connected to a second input terminal to which a second input signal −VTHzis input, a drain is connected to a second output terminal, and a source is connected to ground, a first capacitor provided between the gate of the first CMOS and the second output terminal, and a second capacitor provided between the gate of the second CMOS and the first output terminal.

One end of the first capacitor may be connected to the gate of the first CMOS and the first input terminal, and the other end of the first capacitor may be connected to the drain of the second CMOS and the second output terminal, and one end of the second capacitor may be connected to the gate of the second CMOS and the second input terminal, and the other end of the second capacitor may be connected to the drain of the first CMOS and the first output terminal.

Each of the first CMOS and the second CMOS may have operating speeds slower than frequencies of the first input signal VTHzand the second input signal −VTHz.

In the detector, through the operation in the concurrent mode, an output by gate input and an output by drain input may be combined and appears at the first output terminal and the second output terminal, respectively.

When the first input signal VTHzand the second input signal −VTHzare respectively input to the gates of the first CMOS and the second CMOS, the output by the gate input may include a first gate output signal which is output from the first output terminal and has a phase difference of 180° from the first input signal VTHzand a second gate output signal which is output from the second output terminal and has a phase difference of 180° from the second input signal −VTHz.

When the first input signal VTHzand the second input signal −VTHzare respectively input to the gates of the first CMOS and the second CMOS, the output by the drain input may include a second drain output signal which is output from the first output terminal through the second capacitor and has the same phase as the second input signal −VTHz, and a first drain output signal which is output from the second output terminal through the first capacitor and has the same phase as the first input signal VTHz.

The first gate output signal and the second drain output signal may be combined and output at the first output terminal, and the second gate output signal and the first drain output signal may be combined and output at the second output terminal.

The buffer amplifier may include a signal combiner configured to combine signals output from the first output terminal and the second output terminal of the detector, a first amplifier configured to firstly amplify a magnitude of the signal combined by the signal combiner, a second amplifier connected to the first amplifier and configured to secondarily amplify the signal firstly amplified by the first amplifier, and a voltage buffer connected between the second amplifier and an output terminal of the buffer amplifier and configured to maintain an output voltage of the buffer amplifier constant.

The signal combiner may include a first transistor and a second transistor, a gate of the first transistor may be connected to the first output terminal and a gate of the second transistor may be connected to the second output terminal, and sources of the first transistor and the second transistor may be respectively connected to ground, and a drain of the first transistor and a drain of the second transistor may be connected to each other to configure a first node.

The signal combiner, at the first node, may combine signals that are respectively output from the first output terminal and the second output terminal of the detector, and may cancel and remove the differential signals input to the signal combiner without passing through the detector.

The first amplifier may include a third transistor and a fourth transistor connected in series between a power supply voltage of the receiver and the signal combiner, a source of the third transistor may be connected to the power supply voltage, and a source of the fourth transistor may be connected to the first node, and a drain of the third transistor and a drain of the fourth transistor may be connected to each other to configure a second node, and a predetermined bias voltage may be applied to a gate of the third transistor and a gate of the fourth transistor.

The second amplifier may include an isolation amplifier connected to the first amplifier and provided to block external noise while secondarily amplifying the firstly amplified signal, and a current supplier including a fifth transistor provided between the power supply voltage and the isolation amplifier and configured to supply a current to the isolation amplifier.

The isolation amplifier may include sixth to ninth transistors, the sixth transistor and the eighth transistor may be connected in series between the current supplier and ground, the seventh transistor and the ninth transistor may be connected in series between the current supplier and ground, and the sixth transistor and the eighth transistor may be connected in parallel with the seventh transistor and the ninth transistor.

A gate of the sixth transistor may be connected to the second node, a drain of the sixth transistor and a drain of the eighth transistor may be connected to each other, and a source of the sixth transistor and a source of the seventh transistor may be connected to each other and may also be connected to the drain of the fifth transistor, a drain of the seventh transistor and a drain of the ninth transistor may be connected to each other to configure a third node, and a gate of the eighth transistor and a gate of the ninth transistor may be connected to each other and a source of the eighth transistor and a source of the ninth transistor may be respectively connected to ground, and a gate of the eighth transistor may be connected to the drain of the sixth transistor and the drain of the eighth transistor.

A gate of the seventh transistor may be connected to the output terminal of the buffer amplifier, the voltage buffer may include a tenth transistor and an eleventh transistor connected in series between the power supply voltage and ground, a gate of the tenth transistor may be connected to the third node, and a drain of the tenth transistor may be connected to the power supply voltage, a source of the tenth transistor may be connected to the output terminal of the buffer amplifier, a drain of the eleventh transistor may be connected to a source of the tenth transistor, and a source of the eleventh transistor may be connected to ground, and a preset bias voltage may be applied to a gate of the eleventh transistor.

An imaging system of terahertz band according to the disclosed embodiment includes a transmitter configured to transmit a terahertz band signal to a measurement target, and a receiver configured to receive a signal reflected or transmitted from the measurement target, and the receiver includes an antenna configured to receive the terahertz band signal reflected or transmitted from the measurement target, a detector configured to receive a differential signal including a first input signal VTHzand a second input signal −VTHzwith phase difference of 180° to each other from the antenna to detect a voltage, and operate in a concurrent mode, and a buffer amplifier configured to amplify and output a signal detected by the detector.

A detector according to the disclosed embodiment is a detector mounted on a receiver of the terahertz band, and the detector is configured to receive differential signals including a first input signal and a second input signal with phase difference of 180° to each other from an antenna that receives a terahertz band signal, detect a voltage, and operate in a concurrent mode.

The detector may include a first CMOS of which a gate is connected to a first input terminal to which the first input signal VTHzis input, a drain is connected to a first output terminal, and a source is connected to ground, a second CMOS of which a gate is connected to a second input terminal to which a second input signal −VTHzis input, a drain is connected to a second output terminal, and a source is connected to ground, a first capacitor provided between the gate of the first CMOS and the second output terminal, and a second capacitor provided between the gate of the second CMOS and the first output terminal.

According to the disclosed embodiment, one end of the first capacitor is connected to the gate of the first CMOS, the other end of the first capacitor is connected to the drain of the second CMOS, one end of the second capacitor is connected to the gate of the second CMOS, and the other end of the second capacitor is connected to the drain of this first CMOS, so that when input signals VTHz, and −VTHzare input to the first CMOS and the second CMOS of the detector, the output by gate input (output by the first mode) and the output by drain input (output by the second mode) are combined and appear at the output terminals VOUTPand VOUTNof the detector, respectively. Therefore, the magnitude of the voltage output from the detector can be raised. As a result, it is possible to implement a receiver with high sensitivity characteristics by increasing the voltage responsivity of the detector and lowering the noise equivalent power.

DETAILED DESCRIPTION

Hereinafter, a specific embodiment of the present disclosure will be described with reference to the drawings. The following detailed description is provided to aid in a comprehensive understanding of the methods, apparatus and/or systems described herein. However, this is illustrative only, and the present disclosure is not limited thereto.

In describing the embodiments of the present disclosure, when it is determined that a detailed description of related known technologies may unnecessarily obscure the subject matter of the present disclosure, a detailed description thereof will be omitted. In addition, terms to be described later are terms defined in consideration of functions in the present disclosure, which may vary according to the intention or custom of users or operators. Therefore, the definition should be made based on the contents throughout this specification. The terms used in the detailed description are only for describing embodiments of the present disclosure, and should not be limiting. Unless explicitly used otherwise, expressions in the singular form include the meaning of the plural form. In this description, expressions such as “comprising” or “including” are intended to refer to certain features, numbers, steps, actions, elements, some or combination thereof, and it is not to be construed to exclude the presence or possibility of one or more other features, numbers, steps, actions, elements, some or combinations thereof, other than those described.

Further, terms such as first, second, etc., may be used to describe various components, but the components are not limited by the terms. The above terms may be used for the purpose of distinguishing one component from another. For example, a first component may be termed a second component, and similarly, a second component may be termed a first component, without departing from the scope of the present invention.

FIG.1is a diagram illustrating a receiver of terahertz band according to an embodiment of the present disclosure.

Referring toFIG.1, a terahertz band receiver100may include an antenna102, a detector104, and a buffer amplifier106. Hereinafter, the receiver100is described as an example of a receiver of a terahertz imaging system, but the application range of the receiver100is not limited thereto. In this specification, terahertz includes not only the band of ranging from 01 THz to 10 THz, but also a sub-terahertz band ranging from tens of GHz to hundreds of GHz.

The antenna102can receive a signal reflected or transmitted from a measurement target. In this case, the antenna102may be designed to receive a signal of a frequency higher than an operating frequency of the detector104. For example, antenna102may have an operating frequency of 200 GHz. Further, the antenna102may be a differential integrated antenna.

In an exemplary embodiment, the antenna102may be formed of a folded dipole antenna to assume a mode of operation of the detector104by applying a gate bias via a virtual ground. However, a shape and type of the antenna102is not limited thereto. The terahertz signal received by the antenna102may be input to the detector104.

The detector104may be provided to detect a voltage of a terahertz signal (hereinafter referred to as an input signal) input from the antenna102. The input signal is a differential signal and may include a first input signal VTHzand a second input signal −VTHzwith phase difference of 180° to each other.

The detector104may include a circuitry for concurrent-mode operation. To this end, the detector104may include a cross coupled capacitor.

FIG.2is a diagram illustrating a circuit of the detector104according to an embodiment of the present invention. Referring toFIG.2, the detector104may include a first complementary metal oxide semiconductor (CMOS)111, a second CMOS113, a first capacitor115, and a second capacitor117.

A gate of the first CMOS111may be connected to a first input terminal A. A drain of the first CMOS111may be connected to a first output terminal VOUTP. A source of the first CMOS111may be connected to ground. A first input signal VTHzmay be input to the first input terminal A.

A gate of the second CMOS113may be connected to a second input terminal B. A drain of the second CMOS113may be connected to a second output terminal VOUTN. A source of the second CMOS113may be connected to ground. A second input signal −VTHzmay be input to the second input terminal B.

Here, frequencies of the first input signal VTHzand the second input signal −VTHzmay be higher than current gain cut-off frequencies of the first CMOS111and the second CMOS113. That is, the frequencies of the first input signal VTHzand the second input signal −VTHzmay be higher than operating speeds of the first CMOS111and the second CMOS113.

The first capacitor115may be provided between the gate of the first CMOS111and the second output terminal VOUTN. That is, one end of the first capacitor115may be electrically connected to the gate of the first CMOS111and the first input terminal A. The other end of the first capacitor115may be electrically connected to the drain of the second CMOS113and the second output terminal VOUTN.

The second capacitor117may be provided between the gate of the second CMOS113and the first output terminal VOUTP. That is, one end of the second capacitor117may be electrically connected to the gate of the second CMOS113and the second input terminal B. The other end of the second capacitor117may be electrically connected to the drain of the first CMOS113and the first output terminal VOUTP.

In this way, the first capacitor115and the second capacitor117are provided by being cross coupled to each other between the first CMOS113, the first input terminal (A), and the first output terminal VOUTPand the second CMOS115, the second input terminal (B), and the second output terminal VOUTN, so that the detector104can operate in a concurrent mode.

That is, one end of the first capacitor115is connected to the gate of the first CMOS111, the other end of the first capacitor115is connected to the drain of the second CMOS113, one end of the second capacitor117is connected to the gate of the second CMOS113, and the other end of the second capacitor117is connected to the drain of the first CMOS111, so that when the input signals VTHz, and −VTHzare input to the first CMOS111and the second CMOS113, the output by the gate input (output by the first mode) and the output by the drain input (output by the second mode) are combined and appear at the output terminals VOUTPand VOUTN, respectively. Therefore, the magnitude of the voltage output from the detector can be raised. This will be described in more detail with reference toFIGS.3to5.

FIG.3is a diagram illustrating an output by the gate input in the detector104according to an embodiment of the present disclosure. Referring toFIG.3, when the first input signal VTHzand the second input signal −VTHzare respectively input to the gates of the first CMOS111and the second CMOS113, a signal S1G(hereinafter, may be referred to as a first gate output signal) having a phase difference of 180° from the first input signal VTHzis output from the first output terminal VOUTPconnected to the drain of the first CMOS111. Also, a signal S2G(hereinafter, may be referred to as a second gate output signal) having a phase difference of 180° from the second input signal −VTHzis output from the second output terminal VOUTNconnected to the drain of the second CMOS113.

FIG.4is a diagram illustrating an output by the drain input in the detector104according to the embodiment of the present disclosure. Referring toFIG.4, when the first input signal VTHzand the second input signal −VTHzare respectively input to the gates of the first CMOS111and the second CMOS113, a signal S2D(hereinafter, may be referred to as a second drain output signal) having the same phase as the second input signal −VTHzis output from the first output terminal VOUTPthrough the second capacitor117. Also, a signal S1D(hereinafter, may be referred to as a first drain output signal) having the same phase as the first input signal VTHzis output through the first capacitor115from the second output terminal VOUTN.

FIG.5is a diagram illustrating an output according to the concurrent-mode operation in the detector104according to the embodiment of the present disclosure. Referring toFIG.5, when the first input signal VTHzand the second input signal −VTHzare respectively input to the gates of the first CMOS111and the second CMOS113, the first gate output signal S1Gand the second drain output signal S2Dare combined at the first output terminal VOUTPand output therefrom. Also, the second gate output signal S2Gand the first drain output signal SID are combined at the second output terminal VOUTNand output therefrom.

Here, since the first gate output signal SIG and the second drain output signal S2Dare in phase (a phase different from the first input signal VTHzby 180°), and the second gate output signal S2Gand the first drain output signal SID are in phase (same phase as the first input signal VTHz), the magnitude of the output voltage when the signals are combined at the first output terminal VOUTPand the second output terminal VOUTNcan be increased.

FIG.6is a graph in which the voltage responsivity according to the detector104operating in a concurrent mode according to an embodiment of the present disclosure and that of the previous detector are compared. Referring toFIG.6, it can be seen that the voltage responsivity of the detector104operating in the concurrent mode is about 15 to 33 times higher than that of the previous detector.

Referring back toFIG.1, the buffer amplifier106may serve amplify and output the signal detected by the detector104and block noise introduced from the outside.FIG.7is a circuit diagram illustrating a configuration of the buffer amplifier106according to an embodiment of the present disclosure. Referring toFIG.7, the buffer amplifier106may include a signal combiner121, a first amplifier123, a second amplifier125, and a voltage buffer127.

The signal combiner121may combine signals output from the first output terminal VOUTPand the second output terminal VOUTNof the detector104. The signal combiner121may include a first transistor M1and a second transistor M2.

A gate of the first transistor M1may be connected to the first output terminal VOUTPof the detector104, and a gate of the second transistor M2may be connected to the second output terminal VOUTNof the detector104. Accordingly, the signal output from the first output terminal VOUTPis input to the gate of the first transistor M1, and the signal output from the second output terminal VOUTNis input to the gate of the second transistor M2.

Sources of the first transistor M1and the second transistor M2may be respectively connected to ground. Drains of the first transistor M1and the second transistor M2may be provided to be connected to each other. In this case, the signals of the first output terminal VOUTPand the second output terminal VOUTNof the detector104may be combined at a first node N1where the drain of the first transistor M1and the drain of the second transistor M2are connected. Also, the differential signals VTHzand −VTHzcoming through the detector104may be canceled at the first node N1and removed.

That is, the components input to the gates of the first transistor M1and the second transistor M2include DC components and AC components. Here, the DC components are signals detected through the detector104and output from the first output terminal and the second output terminal, and are combined at the first node N1. Also, the AC components are the VTHzand −VTHzinput to the detector104and are a kind of leakage component directly input to the signal combiner121without passing through the detector104, which are canceled with each other (canceled with each other because they have a phase difference of 180° to each other) at the first node N1and are removed.

The first amplifier123may firstly amplify the magnitude of the signal combined in the signal combiner121. In an exemplary embodiment, the first amplifier123may include a third transistor M3and a fourth transistor M4. The third transistor M3and the fourth transistor M4may be connected in series between a power supply voltage VDDand the signal combiner121. A source of the third transistor M3may be connected to the power supply voltage VDD, and a source of the fourth transistor M4may be connected to the first node N1. Also, a drain of the third transistor M3and a drain of the fourth transistor M4may be connected to each other.

The second amplifier125may be connected to the first amplifier123and may secondarily amplify the signal firstly amplified by the first amplifier123. The second amplifier125may serve to block noise introduced from the outside in the process of outputting the secondarily amplified signal to the output terminal VOUTof the buffer amplifier106. That is, the second amplifier125may be a kind of isolation amplifier.

The second amplifier125may include a current supplier125aand an isolation amplifier125b. The current supplier125amay include a fifth transistor M5. The fifth transistor M5may be connected between the power supply voltage VDDand the isolation amplifier125b. The fifth transistor M5may serve to supply a current to the isolation amplifier125b.

The isolation amplifier125bmay be connected to the first amplifier123. Further, the isolation amplifier125bmay be connected between the current supplier125aand the ground. The isolation amplifier125bmay include a sixth transistor M6to a ninth transistor M9.

The sixth transistor M6and the eighth transistor M8may be connected in series between the current supplier125aand the ground. The seventh transistor M7and the ninth transistor M9may be connected in series between the current supplier125aand the ground. The sixth transistor M6and the eighth transistor M8may be connected in parallel with the seventh transistor M7and the ninth transistor M9.

A gate of the sixth transistor M6may be connected to a second node N2to which the drain of the third transistor M3and the drain of the fourth transistor M4are connected. Here, the signal firstly amplified by the first amplifier123is input to the sixth transistor M6. A drain of the sixth transistor M6and a drain of the eighth transistor M8may be connected to each other.

A source of the sixth transistor M6and a source of the seventh transistor M7may be connected to each other, and also connected to the drain of the fifth transistor M5. A gate of the seventh transistor M7may be connected to an output terminal VOUT. A drain of the seventh transistor M7and a drain of the ninth transistor M9may be connected to each other.

A gate of the eighth transistor M8and a gate of the ninth transistor M9may be connected to each other. A source of the eighth transistor M8and a source of the ninth transistor M9may be connected to ground, respectively. Also, the gate of the eighth transistor M8may be connected to the drains of the sixth transistor M6and the eighth transistor M8. In this case, the eighth transistor M8and the ninth transistor M9serve as a current mirror.

That is, since the gate of the eighth transistor M8is connected to the drains of the sixth transistor M6and the eighth transistor M8, the gate voltage and drain voltage of the eighth transistor M8become the same. Since the gate of the eighth transistor M8and the gate of the ninth transistor M9are connected to each other, the gate voltage of the eighth transistor M8and the gate voltage of the ninth transistor M9become the same. Through this, the current flowing through the sixth transistor M6and the eighth transistor M8and the current flowing through the seventh transistor M7and the ninth transistor M9can be equalized (within an error range).

The voltage buffer127may be connected between the second amplifier125and the output terminal VOUTof the buffer amplifier106. The voltage buffer127may serve to maintain the voltage output from the buffer amplifier106(i.e., the voltage of the output terminal VOUT) constant. In an exemplary embodiment, the voltage buffer127may be implemented as a source follower. The voltage buffer127may include a tenth transistor M10and an eleventh transistor M11.

The tenth transistor M10and the eleventh transistor M11may be connected in series between the power supply voltage VDDand the ground. A gate of the tenth transistor M10may be connected to a third node N3to which the drain of the seventh transistor M7and the drain of the ninth transistor M9are connected. A drain of the tenth transistor M10may be connected to the power supply voltage VDD, and a source of the tenth transistor M10may be connected to an output terminal VOUT.

A drain of the eleventh transistor M11may be connected to the source of the tenth transistor M10, and a source of the eleventh transistor M11may be connected to ground. The eleventh transistor M11may serve to supply a current to the tenth transistor M10.

Here, the gate of the seventh transistor M7is connected to the output terminal VOUT, the drain of the seventh transistor M7is connected to the gate of the tenth transistor M10, and the source of the tenth transistor M10is connected to the output terminal VOUTto form a feedback loop.

In this case, when the voltage of the output terminal VOUTincreases, the current flowing into the seventh transistor M7increases, and thus the voltage input to the tenth transistor M10decreases and the voltage of the output terminal VOUTdecreases. In contrast, when the voltage of the output terminal VOUTdecreases, the current flowing into the seventh transistor M7decreases, t and thus the voltage input to the tenth transistor M10increases and the voltage of the output terminal VOUTincreases.

That is, when the voltage of the output terminal VOUTincreases, the voltage of the output terminal VOUTdecreases through the feedback loop of the seventh transistor M7and the tenth transistor M10, and when the voltage of the output terminal VOUTdecreases, the voltage of the output terminal VOUTincreases through the feedback loop of the seventh transistor M7and the tenth transistor M10.

In this way, since the voltage of the output terminal VOUTis maintained at a constant voltage through the feedback loop of the seventh transistor M7and the tenth transistor M10, even if the voltage of the output terminal VOUTchanges momentarily due to the inflow of external noise through the output terminal VOUT, it is possible to block the voltage change caused by external noise and maintain a constant voltage.

Meanwhile, first to fourth bias voltages VB1to VB4may be respectively applied to the gates of the third transistor M3, the fourth transistor M4, the fifth transistor M5, and the eleventh transistor M11.

FIG.8is a graph illustrating voltage responsivity (RV) and noise equivalent power (NEP) measured in the detector according to the embodiment of the present disclosure.

Referring toFIG.8, it can be seen that the voltage responsivity (RV) and noise equivalent power (NEP) measured by the detector104are 1413 MV/W and 3442 pW/√Hz, respectively, under the gate bias condition of 150 mV. That is, it can be seen that the voltage responsivity (RV) measured by the detector104is high and the noise equivalent power (NEP) is low.

Although representative embodiments of the present disclosure have been described in detail, a person skilled in the art to which the present disclosure pertains will understand that various modifications may be made thereto within the limits that do not depart from the scope of the present disclosure. Therefore, the scope of rights of the present disclosure should not be limited to the described embodiments, but should be defined not only by claims set forth below but also by equivalents to the claims.