Programmable signal slicer

Disclosed are various embodiments of a programmable slicer in a digital signal processing system and/or software radio system. In one embodiment, a plurality of demodulation schemes and a plurality of channel definitions are stored in a channel allocation table. An analog waveform is received and converted into at least one digital waveform. A specified frequency range is isolated from the at least one digital waveform. The magnitude of tones within the specified frequency range is measured and stored in a signal magnitude table. Symbols and/or bits are decoded from the signal magnitude table by applying a demodulation schemes and channel definitions to the magnitudes stored in the signal magnitude table.

TECHNICAL FIELD

The disclosure relates generally to a power distribution system, and more specifically, to communications over distribution lines in a power distribution system.

BACKGROUND

In a power distribution system, usage metering data may be transmitted over a distribution line or a communications link to a power distribution substation, central office, billing center, or the like. Various modulation schemes may be employed between an endpoint and a distribution substation, central office, billing center, or the like.

DETAILED DESCRIPTION

Disclosed are systems and methods for a programmable and dynamically configurable slicer in a software radio system. The programmable slicer facilitates the use of multiple modulation schemes with respect to a carrier wave on which digital data is encoded. The programmable slicer allows various transceivers and/or endpoints in a system to communicate with other endpoints in a system using various modulation schemes.

A system including the programmable slicer demodulates a carrier wave using various demodulation schemes that can be dynamically changed and/or configured. As a non-limiting example, the programmable slicer can allow an endpoint to communicate with another endpoint via a carrier wave encoded using a binary frequency shift keying modulation scheme. The endpoint may then communicate with another endpoint in the system using a 32 tone (e.g., 5 bit) frequency shift keying modulation scheme that is linked with a symbol lookup table stored in a memory in order to determine the data being transmitted. Accordingly, this flexibility facilitates various software radio applications, as endpoints equipped with a programmable slicer in accordance with an embodiment of the disclosure can also communicate with other endpoints at various speeds and bandwidth utilization levels.

Therefore, with reference toFIG. 1, shown is a block diagram of one link of an exemplary power distribution system100distributing power between a distribution substation103and an endpoint104, which can be incorporated with a customer device and/or electrical system at a power consumer's premises or site. The power distribution system100, or distribution plant as it is sometimes referred to, can be that part of an electric power system that receives power from a power generator via high-voltage transmission lines, reduces or steps down the voltage, and then distributes the power to an endpoint104at the premises of a power consumer. Within the power distribution system100, distribution lines may conduct electricity from the distribution substation to the endpoints. Distribution lines may include underground cable, aerial cable, or overhead open-wire conductors carried on poles, or some combination thereof.

Depending on the particular configuration, there may be one or more layers of distribution substations103connected in series between the power generator and the endpoint104, where each consecutive distribution substation further steps down the voltage of the electricity being transmitted. Additionally, the depicted distribution substation103can also represent any other central office, data center, and/or other supplier infrastructure used to deliver electricity, telecommunications services, phone, internet, or other services. As a non-limiting example, the depicted distribution substation103can be replaced and/or supplemented with a digital subscriber line access multiplexer (DSLAM) implemented in accordance with the same or analogous principles as disclosed herein.

Additionally, the power generators, distribution substations103, and endpoints104may be organized in a network where the various power generators supplying power can be taken on or off line and the distribution substation (through which a particular endpoint receives its electricity) can be changed without a loss or interruption of power. Distribution transformers (not shown) may be connected in the distribution line between the distribution substation103and the endpoint104, which the distribution transformers serve to further step-down the voltage to a level that is used by consumers. These step-down transformers, often referred to as pole transformers may be configured to supply a consumer or group of consumers with electricity over a secondary circuit. Each consumer may be connected to the secondary circuit through its service leads and meter.

The distribution substation103shown inFIG. 1may be configured to provide power to a consumer device (not shown) and/or endpoint104via a distribution line106. The distribution line106may be coupled to one or more step-down transformers before reaching the depicted endpoint104. The distribution line106may be configured to receive power from the distribution substation103and provide at least a portion of that power to the endpoint104.

For a variety of reasons, it may be desirable to communicate information from the distribution substation103to one or more endpoints, such as the endpoint104. As a non-limiting example, it may be desirable to control and/or monitor a usage metering device, which may be located at or near the endpoint104to determine the power consumption at the endpoint104. Additionally, control information may be configured to provide the ability to control and/or alter the operation of the usage metering device and/or individual loads at the customer premise. As an additional non-limiting example, other services aside from power, such as telecommunications, internet, and/or other data services can also be provided via the distribution line and may utilize bi-directional communication between the distribution substation103and endpoint104.

Other more general information, including, but not limited to, information to display or store the price of power at the customer premise, the date and time, the temperature and/or other information capable of being received and translated at the customer premise may also be transmitted along the distribution line. As a non-limiting example, the time displayed on an electronic device at the customer premise could be periodically adjusted to display an accurate time as transmitted by the utility station.

As three phase electronic power systems can be frequently employed for power distribution, such power systems can include three conductors carrying time offset waveforms. Accordingly, data can be transmitted via three substantially similar waveforms that can be reconciled by a transceiver, and/or data can be separately transmitted in each of the three waveforms. It should also be appreciated that a single phase waveform or combinations of any number of wave forms can be employed as well. Data can be embedded in any or all of the waveforms by employing various modulation schemes, which can include, but are not limited to: frequency-shift keying (FSK), on-off keying, amplitude shift keying, phase shift keying, quadrature amplitude modulation, minimum shift keying, continuous phase modulation, pulse position modulation, trellis modulation, and orthogonal frequency division multiplexing or other modulation schemes that should be appreciated whereby digital information can be transmitted on any or all of the waveforms employed in a power distribution system that may act as a carrier wave in such a scheme.

Various embodiments disclosed herein may be configured to communicate control signals and general information signals to endpoints104via the distribution line106to control customer devices and provide more general information to the customer. Information from the customer device also may be sent via the distribution line106to the distribution substation103, thereby creating a two-way or bidirectional communications link via the distribution line106. The aforementioned examples of control signal applications where control signals (and/or general information signals) are provided by the distribution substation to an endpoint104are merely representative of the various uses that such control signals provide. Therefore, the examples provided herein are merely exemplary, as the disclosed embodiments are not limited to the transmission of any particular signal or service.

In providing control information and/or other data at the distribution substation103, a power line carrier (PLC) transceiver109is used to drive control signals and/or other data along the distribution line106to an endpoint transceiver112at the endpoint104. The endpoint transceiver112may be configured to recognize the signals transmitted by the PLC transceiver109. Similarly, the PLC transceiver109may be configured to receive information transmitted on the distribution line106from the endpoint transceiver112.

The power distribution system100including the distribution line106may be configured to provide a full-duplex or bidirectional link between the distribution substation103and the endpoint104. Full duplex in this non-limiting example may refer to simultaneous (and/or substantially simultaneous) communications in both directions, although the information sent in one direction may travel at a speed different from that of the information provided in the opposite direction. This full-duplex link via the distribution line106may be configured to provide for transmission of control information, without the need for additional wiring over and above such a distribution line106that may be utilized for the transmission of electrical power.

It should be appreciated that the depicted power distribution system100ofFIG. 1is merely a depiction of a single exemplary link in such a system. It should further be appreciated that additional complexities utilized for the bulk distribution of electricity or other services can be incorporated into an embodiment of the present disclosure. It should also be appreciated that systems and methods disclosed herein may not be limited to use in a power distribution system100, and that the depicted power distribution system100is but one example in which embodiments of the disclosure can be implemented. For example, systems and methods of an embodiment can be implemented in a software radio system other system employing a carrier wave and/or multiple modulation/demodulation schemes. Additional non-limiting examples are discussed herein.

With reference toFIG. 2, shown is an alternative depiction of a distribution substation103in accordance with the disclosure. It should be noted, as is depicted inFIG. 2, that in operation, a distribution substation103can be coupled to more than one endpoint104. As a non-limiting example, a distribution substation103may be coupled to hundreds or thousands of endpoints104configured in a unidirectional or bidirectional communications link over a distribution line106. It should also be noted that in a multiple endpoint104configuration, various wiring configurations can be employed to connect a distribution substation103to endpoints104. As a non-limiting example, in the depicted environment ofFIG. 2, a main distribution line106as well as various spoke distribution lines201are employed to connect endpoints104to the distribution substation103. However, alternative wiring schemes may also be employed. As an additional non-limiting example, the distribution substation103as well as endpoints104may be connected serially.

As the distribution substation103and multiple endpoints104can be configured to form a communication link therebetween via distribution line106, a communications protocol can be established to substantially ensure that signals originating from one endpoint104ado not interfere with those originating from another endpoint104b. Accordingly, each endpoint104in such an environment can be assigned a channel in a frequency modulation scheme in which it may transmit data. As a non-limiting example, an endpoint104can be assigned an approximate 2-3 mHz channel within approximately 50 Hz to 60 Hz of bandwidth that is typically employed for power distribution.

Accordingly, the PLC transceiver109can communicate with each endpoint104individually by sending and/or receiving signals in a particular channel or frequency assigned to an endpoint104. As noted above, there may be hundreds or thousands of endpoints104coupled to a distribution substation103. A PLC transceiver109in accordance with embodiments of this disclosure are capable of interpreting and processing data that may be sent from multiple endpoints104. Such processing of a three phase analog waveform can utilize substantial digital signal processing resources. Accordingly, the PLC transceiver109may include at least one advanced digital signal processing card (ADC)204, which is configured to receive the three offset phases of a three phase signal from various endpoints104that are coupled to the distribution substation103or a subset thereof. The ADC204may be configured to receive, filter, and/or separate a predetermined frequency range (e.g. approximately a 60 Hz and/or 50 Hz range) into one or more channels that are assigned to various endpoints104.

In one embodiment, the ADC204can include one or more digital signal processors that are configured to receive and/or process channels assigned to endpoints104that are encoded in an analog waveform. A programmable slicer can be implemented in one or more digital signal processors on an ADC204. In addition, a correlator can also be implemented to facilitate demodulation of a signal by the programmable slicer. As another non-limiting example, an ADC204can include a plurality of digital signal processors that can receive the various phases of a waveform embedded with encoded data from a plurality of endpoints104and extract at least one channel of data corresponding to the various endpoints104in an environment such as depicted inFIG. 2. As the communications theories employed to extract such channels of digital data from an analog waveform by employing various modulation/demodulation schemes should be appreciated by one of ordinary skill in the art, further detail need not be discussed herein.

A PLC transceiver109can further include one or more ADC's204to perform digital signal processing to receive and/or process signals received from other and/or additional endpoints104. As a non-limiting example, the distribution substation103and PLC transceiver109may be coupled to a number of endpoints104that is greater than can be handled by a single ADC204; therefore, additional ADCs204may be incorporated into a PLC transceiver109.

A PLC transceiver109may further include a single board computer (SBC)206and/or other device that can handle higher level tasks of a distribution substation103aside from the digital signal processing operations of the ADC's204. As a non-limiting example, the SBC206may be configured to receive digital signals extracted by the ADC's204corresponding to each endpoint104coupled to a distribution substation103. Such data can include, but is not limited to: metering data, outage data, status information and other data. Accordingly, the SBC206can process such data for billing, maintenance or other purposes. As an alternative non-limiting example, SBC206can forward such data to central billing and/or operations systems for such processing.

Additionally, SBC206can issue commands to ADC's204of the PLC transceiver109. As a non-limiting example, an SBC206can configure digital signal processing resources of an ADC204by initiating a software flash and/or other programming processes of one or more digital signal processors or other programmable components residing on an ADC204. As another example, an SBC206can configure a programmable slicer implemented in the digital signal processing resources of an ADC204by updating and/or modifying the modulation schemes and/or channel allocation configuration under which a distribution substation103and various endpoints104communicate.

Reference is now made toFIG. 3, which depicts a non-limiting exemplary embodiment of an ADC204in which a programmable slicer can be implemented. The depicted ADC204includes multiple digital signal processors302that are coupled to a corresponding memory304. One or more of the digital signal processors302may be configured to act as a programmable slicer for receiving and processing data from various endpoints104(FIG. 1) in a power distribution system. Additionally, each digital signal processor302may possess an internal memory or can be configured with an external memory for the purpose of assisting with the digital signal processing of signals received from a distribution line106(FIG. 1).

Because various digital signal processing tasks may be divided in the ADC204among the digital signal processors (DSPs)302, the various digital signal processors302may also be configured to communicate data among one another. As a non-limiting example, if the DSPs302of an ADC204are configured to perform piecewise processing of a signal in an assembly line fashion in order to isolate channels embedded therein, it may be desired to transmit data from one DSP (e.g.302a) to another DSP (e.g.302b) in the ADC204. Consequently, the DSPs302of the ADC204can transmit data among one another to facilitate digital signal processing necessary to process signals on a distribution line106.

Therefore, in order to implement a programmable slicer and correlator in accordance with an embodiment of the disclosure, one or more DSPs302in the depicted ADC204can be configured to process a signal received by the ADC204. To facilitate processing of a signal, the digital signal processors302may be configured to access the memory304of other digital signal processors302in an ADC204. As a non-limiting example, the DSP302acan be configured to access the memory304bthat is coupled to the DSP302b. Such access can include writing and/or reading data from or to the memory304b. In the above non-limiting example, the DSP302ais configured to act as a master processor with reference to the DSP302b, as it has access to the memory of the DSP302b. Additionally, the DSP302bcan be likewise configured to access the memory304athat is coupled to DSP302a. Therefore, DSPs302aand302b(or any of the DSPs in the ADC204) can be configured as a master processor and a slave processor by accessing memory of another DSP while substantially simultaneously providing access to its own memory.

As an additional non-limiting example, DSP302amay be configured as a master processor relative to DSP302band a slave processor relative to a third DSP, such as DSP302c. Whether a DSP requires configuration as a master processor and/or a slave processor relative to another DSP may be dependent on configuration or programming of the DSPs and the tasks performed by each in order to process a waveform in a power distribution system or other software radio application. In other words, each DSP302in an ADC204can be configured to act as a master processor and/or a slave processor relative to any other DSP302in the system. In addition, a DSP configured as a slave processor relative to a first DSP may not be simultaneously configured as a slave processor relative to a second DSP. In other words, a master processor should have exclusive access to the memory of a slave processor relative to other potential master processors in the system.

Because each DSP302of the ADC204can be configured as a master processor or a slave processor relative to any other DSP302in the system, fabrication of such a system can be facilitated with the use of a memory arbiter306that can arbitrate and/or route such requests and data transfers among the DSPs302. Rather than wiring individual DSPs302to one another directly, the ADC204employs memory arbiter306and bus307to facilitate the flexible master-slave architecture of the ADC204disclosed herein. To this end, the memory arbiter306maintains DSP status308, which, for at least one of the DSPs302in an ADC204, includes data regarding whether a DSP is presently claimed as a slave processor by another DSP in the ADC204. In other words, if a particular DSP302is claimed as a slave processor, the DSP can cause the memory arbiter306to reflect that it is presently exclusively claimed as a slave processor by another DSP acting as a master processor. Additionally, the DSP status308includes data regarding which DSP302in the ADC204has exclusively claimed a DSP as a slave processor. The above non-limiting example of an ADC204in which a programmable slicer and/or correlator can be implemented is merely exemplary and other permutations of DSPs or any computing system or resources can be employed.

Reference is now made toFIG. 4, which depicts an alternative illustration of an advanced digital signal processing card (ADC)404. The depicted ADC404illustrates one non-limiting example of an implementation in a power distribution system100(FIG. 1), whereby the ADC404divides processing tasks necessary to receive and process a signal. As noted above, the ADC404can be configured to process a waveform having data from various endpoints in a power distribution system100embedded thereon. Because such a power distribution system may have hundreds or thousands of endpoints in communication with an ADC404residing in a distribution substation103and/or PLC transceiver109, considerable digital signal processing tasks may be required in order to extract data from such a number of endpoints that can potentially transmit data embedded in a three phase waveform.

In the depicted non-limiting embodiment DSP405is configured to communicate with an RS-232 interface450with an SBC206that can be in a PLC transceiver109. As noted above, the SBC206can perform various functions such as communicating with a central billing system, issuing commands and/or other directives to the ADCs in a PLC transceiver109, and other tasks. In addition, the SBC206can configure and/or program the ADC404as well as the DSPs (405-413) and memory arbiter420residing thereon. This configuration and/or programming which can include issuing new software for flashing on a hardware device, information regarding endpoints, distribution line106conditions, modulation/demodulation schemes for a programmable slicer, channel allocations for a programmable slicer, and other data. It should also be noted that the DSP405may communicate with the SBC206via interfaces other than RS-232 interface450, which may include, but are not limited to Ethernet or other serial and/or parallel data interfaces.

Accordingly, DSP405may be configured to act as a gateway to the SBC206for the ADC404as well as other hardware and software components thereon. Consequently, the DSP405may be configured to understand and/or execute a command set or other protocol necessary for such gateway communications. Additionally, the DSP405is further configured to translate and/or forward commands or data from the SBC206to other DSPs in the ADC404, which can include but is not limited software to execute in the memory or flash memory of a DSP (405-413) or configuration data. Accordingly, DSP405may be configured to use the master-slave architecture facilitated by the memory arbiter420that allows it to claim other DSPs (407-413) in the ADC404as slave processors for the purpose of accessing memory of the DSPs (407-413). In addition, the DSP405can transmit digital data extracted from various channels of a waveform received on a distribution line106or any other communication line to the SBC206via the RS-232 interface450.

DSP413in the depicted ADC404is configured to receive a waveform on a distribution line106that is converted into digital signals by an analog to digital converter (A/D)460. In the case of a three phase waveform, the A/D460is configured to receive three phases and convert the phases into a digital signal for processing by the ADC404. The DSP413can perform digital signal processing tasks to begin the channel extraction process. As a non-limiting example, the DSP413can combine the three phases of the three phase waveform and filter the combined waveform such that extraneous data at frequencies above and below an area of interest are removed. As a non-limiting example, in a 60 Hz power distribution system, frequencies above and below a 60 Hz area of interest can be filtered from the combined waveform by DSP413so that channels can be extracted therefrom. Likewise, the same principle can be applied in a 50 Hz power distribution system, as frequencies above and below a 50 Hz area of interest can be filtered from the combined waveform. In this way, DSP413can perform such pre-processing so that additional DSPs in the ADC404can further process the waveform to extract data from channels corresponding to endpoints in a power distribution system.

In the depicted example, one or more of the remaining DSPs in the ADC404can implement a correlator and/or programmable slicer to extract data from channels in a waveform preprocessed by DSP413. The correlator can measure various characteristics of tones in a preprocessed waveform and store the characteristics of each tone in a table. These characteristics can include, but are not limited to the amplitude, phasing, frequency, and other characteristics that should be appreciated. In one embodiment, the correlator can measure the magnitude and/or amplitude of each tone in a preprocessed waveform and store the magnitudes and/or amplitudes in a signal magnitude table that can be stored in a corresponding DSP memory. A programmable slicer can process the signal magnitude table to extract bits and/or symbols encoded in the waveform that correspond to various channels of the waveform.

The programmable slicer can employ various demodulation schemes and channel configurations that can be stored and/or retrieved from a DSP memory in a channel allocation table or other data structure. As a non-limiting example, the channel allocation table can define a first channel as including a “zero” tone, a “one” tone, and a guard tone. In the above example, the channel allocation table can further associate a demodulation scheme such as binary frequency shift keying with the channel definition so that the programmable slicer can extract a bit and/or symbol from the first channel. Accordingly, in the example of the first channel noted above, the programmable slicer can determine whether a “zero” or “one” is encoded therein by examining the signal magnitude table by determining whether the “zero” tone or “one” tone has a greater magnitude in the signal magnitude table.

To further demonstrate the operation of the programmable slicer, in the above non-limiting example, the channel allocation table can define a second channel in a channel definition as including 32 tones. In addition, the channel allocation table can define a demodulation scheme associated with the 32 tone channel. As a non-limiting example, the demodulation scheme can instruct the programmable slicer to determine which of the 32 tones has the greatest magnitude and/or amplitude by examining the signal magnitude table. The programmable slicer can subsequently retrieve a symbol associated with the tone from a symbol table associated with the channel and/or demodulation scheme. For example, if the third tone has the greatest magnitude, the programmable slicer can determine that data in a symbol table associated with the third tone is associated with the second channel of the waveform.

Additionally, the programmable slicer can determine a plurality of tones that have the greatest magnitude and/or amplitude relative to other tones in a channel and assign a value and/or symbol based on the identity of such tones. Further, as noted above, the correlator may populate the signal magnitude table with values corresponding to other characteristics of a tone, which can include, but are not limited to: phase/phasing, amplitude, frequency and other characteristics which should be appreciated. Accordingly, the programmable slicer can assign a value to a channel based on any values populated in the signal magnitude table, and may operate according to a demodulation scheme instructing the programmable slicer to examine one or a plurality of values in the table.

The above scenario is merely exemplary, and is given to demonstrate the configurability and flexibility of the programmable slicer in that it is capable of decoding a signal that may have various modulation/demodulation schemes associated with various channels. The above scenario is further discussed with reference toFIG. 8. Other demodulation schemes can be employed as noted above, which can include QAM, FSK, MFSK, BPSK, CPFSK, MPSK, differential phase schemes such as DPSK, modulation schemes using phasing as an information carrier such as PSK, and others as can be appreciated. It should be appreciated that the programmability of the slicer allows a signal to be decoded that includes multiple types of modulation of a given signal. The programmable slicer may also be employed with schemes involving coherent and non-coherent detection.

Accordingly, the DSP413can employ the master-slave architecture to send the filtered data to one or more of the remaining DSPs407,409,411to perform the correlator and/or programmable slicer functions in order to extract data corresponding to endpoints. As there may be hundreds or thousands of endpoints in a power distribution system, the DSPs407,409,411may be assigned various distinct portions of the filtered waveform received from DSP413to extract such data. As a non-limiting example, an endpoint can be assigned a channel representing a subset of a total bandwidth in order to transmit data using a first modulation scheme. For certain periods or data transmission scenarios, the endpoint can be assigned a larger or smaller channel of the total bandwidth to transmit data using a different modulation scheme. In this way, the system allows dynamic apportionment of available bandwidth of the transmission medium among endpoints on an as needed basis. Therefore, the programmable slicer and correlator allows decoding of data from an endpoint using common hardware and software, as the slicer is capable of handling various channel sizes and modulation schemes as defined by the channel allocation table.

With reference toFIG. 5, shown is one example of a DSP509according to one embodiment of the disclosure. The depicted DSP509can exist in an ADC404(FIG. 4) or in any computing system, or as a standalone signal decoder. The DSP509can include a bus interface553that provides access to a data bus, shared memory system, master processor, slave processor, transmission line, communication medium, or other external resources. The DSP509can further be configured with a correlator557and a programmable slicer559. The DSP509can also optionally be configured with a dedicated memory561structure in which channel allocation tables, signal magnitude tables, or other data structures can be stored and/or accessed.

The correlator557is configured to preprocess a data signal on behalf of a programmable slicer559. In one embodiment, the correlator557can detect the magnitude and/or energy level of various tones in a waveform and store the magnitudes in a signal magnitude table. Accordingly, as described above, the programmable slicer559can decode the various channels encoded in the waveform by processing the signal magnitude table according to a channel allocation table that contains channel definitions and demodulation schemes associated with the various channel definitions.

Reference is now made toFIG. 6, which depicts a functional block diagram of a software radio system600. It should be noted that some components not essential for understanding (by persons skilled in the art) of the software radio system600are omitted for purposes of brevity and ease of depiction. The software radio system600can be implemented as a software program in a computing system for the purposes of transmitting and/or receiving data signals encoded in one or more waveforms.

The software radio system600can include a correlator602and programmable slicer604. As described above with reference to previously disclosed embodiments of the disclosure, the correlator602is configured to preprocess a data signal on behalf of a programmable slicer604. In one embodiment, the correlator602can detect the magnitude and/or energy level of various tones in a waveform and store the magnitudes in a signal magnitude table. Accordingly, as described above, the programmable slicer559can decode the various channels encoded in the waveform by processing the signal magnitude table according to a channel allocation table that contains channel definitions and demodulation schemes associated with the various channel definitions.

Reference is now made toFIG. 7, which is an exemplary embodiment of the software radio system600fromFIG. 1. For some embodiments, the software radio system600may be incorporated as some type of computing device. Generally speaking, the software radio system600may be any one of a wide variety of wired and/or wireless computing devices, such as an embedded system, digital signal processing system, desktop computer, portable computer, dedicated server computer, multiprocessor computing device and so forth. Irrespective of its specific arrangement, the software radio system600may comprise, among other components, a processing device720, input/output interfaces730, a network interface740, and, optionally, a display702connected across a data bus712. One of ordinary skill in the art will appreciate that the software radio system600can, and typically will, comprise other components, which have been omitted for purposes of brevity.

The processing device720can include a custom-made or commercially available processor, a central processing unit (CPU) or an auxiliary processor among several processors associated with digital signal processing, a semiconductor based microprocessor (in the form of a microchip), a macroprocessor, one or more application specific integrated circuits (ASICs), a plurality of suitably configured digital logic gates, and other well known electrical configurations comprising discrete elements both individually and in various combinations to coordinate the overall operation of the computing system.

The memory760shown inFIG. 7can include any one of a combination of volatile memory elements (e.g., random-access memory RAM, such as DRAM, and SRAM, etc.) and nonvolatile memory elements (e.g., ROM, hard drive, tape, CDROM, etc.). The memory760may store a native operating system370, one or more native applications, emulation systems, or emulated applications for any of a variety of operating systems and/or emulated hardware platforms, emulated operating systems, etc. Again, one of ordinary skill in the art will appreciate that the memory760can, and typically will, comprise other components, which have been omitted for purposes of brevity. The software radio system600may further comprise mass storage790. The mass storage790may be, for example, a disk drive, flash memory, or any other of a wide variety of storage devices capable of storing data.

As noted in the functional block diagram ofFIG. 6, the software radio system600may include a correlator602and programmable slicer604, the functionality of which are described herein. When implemented in software, it should be noted that any of the above modules can be stored on a variety of computer-readable medium for use by, or in connection with, a variety of computer-related systems or methods. In the context of this document, a computer-readable medium may comprise electronic, magnetic, optical, or other physical device or apparatus that can contain or store a computer program for use by or in connection with a computer-related system or method. The interface can be embedded in a variety of computer-readable medium for use by, or in connection with, an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.

In the context of this disclosure, a “computer-readable medium” stores, communicates, propagates, or transports the program for use by or in connection with the instruction execution system, apparatus, or device. The computer readable medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. More specific examples (a non-exhaustive list) of the computer-readable medium may include the following: an electrical connection (electronic) having one or more wires, a portable computer diskette (magnetic), a random access memory (RAM) (electronic), a read-only memory (ROM) (electronic), an erasable programmable read-only memory (EPROM, EEPROM, or Flash memory) (electronic), an optical fiber (optical), a portable compact disc read-only memory (CDROM) (optical), a digital versatile disc (optical), a high definition digital versatile disc (optical), and a Blu-ray Disc (optical).

Input/output interfaces730comprise any number of interfaces for the input and output of data. For example, where the software radio system600comprises a personal computer, the components within the system may interface with a user input device such as a keyboard, a mouse, or a remote controller. In addition, the software radio system600may communicate via the input/output interfaces730with an antenna, radio system, communication line, or other communication medium for the purposes of receiving and/or sending a data signal. The software radio system600may also include a network interface740for transmitting and/or receiving data over a network. As a non-limiting example, the network interface740may include a modulator/demodulator (e.g., a modem), wireless (e.g., radio frequency (RF)) transceiver, a telephonic interface, a bridge, a router, network card, etc.

With reference toFIG. 8, shown is an alternative depiction of a correlator802and programmable slicer804in accordance with an embodiment of the disclosure. As noted above, the correlator802is configured to measure the magnitude of tones of a carrier wave and store the magnitude of each tone (or a subset thereof) in a signal magnitude table806. The programmable slicer804can be configured to decode a signal encoded in the carrier wave by examining the signal magnitude table806. To that end, the programmable slicer804can employ a channel allocation table808, which can be stored in memory accessible by the programmable slicer804. The channel allocation table808can define a plurality of channels embedded in a carrier wave. In the depicted non-limiting example, a first channel809can include a first series of tones813that include binary frequency shift keyed tones that can include a “zero” tone, a “one” tone, and a “guard” tone. The programmable slicer808can determine which of the “zero” tone and “one” tone has a greater magnitude as defined by the signal magnitude table. In the depicted example, because the “one” tone is greater than the “zero” tone, the programmable slicer can extract a “one” bit and/or symbol from the first channel809.

Continuing the above example, a second channel811can define a series of eight frequency shift keyed tones. The second channel811can include a demodulation scheme instructing the programmable slicer804to assign a symbol and/or bit associated with the tone having the greatest magnitude. It should again be noted that the above scenario is merely exemplary, and is given to demonstrate the configurability and flexibility of the programmable slicer in that it is capable of decoding a signal that may have various modulation/demodulation schemes associated with various channels. Other demodulation schemes can be employed as noted above, which can include QAM, FSK, MFSK, BPSK, CPFSK, MPSK, differential phase schemes such as DPSK, modulation schemes using phasing as an information carrier such as PSK, and others as can be appreciated. It should be appreciated that the programmability of the slicer allows a signal to be decoded that includes multiple types of modulation of a given signal. The programmable slicer may also be employed with schemes involving coherent and non-coherent detection.

With reference toFIG. 9, shown is one example of a process900in accordance with the disclosure. The depicted process900illustrates operation of a programmable slicer and correlator. The process900can be implemented in an ADC204, a software radio system600, or any computing system or digital signal processing system. In box902and704, an analog waveform is received and converted into at least one digital waveform. In box906, a specified frequency range is isolated from the digital waveform. As a non-limiting example, as many power distribution systems may operate at either 50 Hz and/or 60 Hz, the signals in frequency ranges above or below such an area of interest can be considered extraneous and it may be unnecessary to process such extraneous data. As noted above, channels can be defined across the frequency range and can correspond to at least one endpoint104in a power distribution system100. Because there may be hundreds or thousands of endpoints104in such a system, in one embodiment, each endpoint104can be assigned a channel that can be approximately 2-3 mHz.

In box908a correlator can measure the magnitude of tones across the isolated frequency range. In box910, the correlator can store the magnitudes in a signal magnitude table for processing by a programmable slicer. In box910, the programmable slicer can decode symbols and/or bits from channels defined by a channel allocation table by applying a demodulation scheme to the defined channels that is associated with each channel definition.

With reference toFIG. 10, shown is one additional example of an ADC204and/or software radio system600implementing a programmable slicer and/or correlator that includes an embedded system, one or more digital signal processors, computer, and/or equivalent device according to an embodiment of the present disclosure. In implementing the above described embodiments, the ADC204and/or software radio system600implementing a programmable slicer may include one or more processor circuits having a processor1003, a memory1006, and a Memory arbiter1007which are coupled to a local interface or bus1009. In this respect, the local interface or bus1009may comprise, for example, a data bus with an accompanying control/address bus as can be appreciated.

Stored on the memory1006and executable by the processor1003are various components such as an operating system1013. In addition, it is understood that many other components may be stored in the memory1006and executable by the processor(s)1003. Also, such components may reside in a memory that is external from the distribution substation103as can be appreciated. It should also be noted that DSPs in an ADC204, for example, may also include additional ports that for additional external connectivity, memory interfaces, or other ports that are not shown as they are not necessary for an appreciation of the disclosed ADC204architecture.

As set forth above, a number of components are stored in the memory906and are executable by the processor1003. In this respect, the term “executable” refers to a program file that is in a form that can ultimately be run by the processor1003. Examples of executable programs may be, for example, a compiled program that can be translated into machine code in a format that can be loaded into a random access portion of the memory1006and run by the processor903, or source code that may be expressed in proper format such as object code that is capable of being loaded into a random access portion of the memory1006and executed by the processor1003. An executable program may be stored in any portion or component of the memory1006including, for example, random access memory, read-only memory, a hard drive, compact disk (CD), floppy disk, or other memory components.

In addition, the processor1003may represent multiple processors and the memory1006may represent multiple memories that operate in parallel. In such a case, the local interface1009may be an appropriate network that facilitates communication between any two of the multiple processors, between any processor and any one of the memories, or between any two of the memories, etc. The processor1003may be of electrical, optical, or of some other construction as can be appreciated by those with ordinary skill in the art.

The operating system1013is executed to control the allocation and usage of hardware resources such as the memory and processing time in the ADC or software radio system. In this manner, the operating system1013serves as the foundation on which applications depend as is generally known by those with ordinary skill in the art.

The flow chart ofFIG. 9show the functionality and operation of an implementation of an ADC300and/or software radio system600implementing a programmable slicer and correlator. If embodied in software, each block may represent a module, segment, or portion of code that comprises program instructions to implement the specified logical function(s). The program instructions may be embodied in the form of source code that comprises human-readable statements written in a programming language or machine code that comprises numerical instructions recognizable by a suitable execution system such as a processor in a computer system or other system. The machine code may be converted from the source code, etc. If embodied in hardware, each block may represent a circuit or a number of interconnected circuits to implement the specified logical function(s).

Also, where the functionality of the disclosed systems is expressed in the form of software or code, it can be embodied in any computer-readable medium for use by or in connection with an instruction execution system such as, for example, a processor in a computer system or other system. In this sense, the functionality may comprise, for example, statements including instructions and declarations that can be fetched from the computer-readable medium and executed by the instruction execution system.

Although the functionality of various embodiments are described above with respect to the drawings as being embodied in software or code executed by general purpose or digital signal processing hardware as discussed above, as an alternative the same may also be embodied in dedicated hardware or a combination of software/general purpose hardware and dedicated hardware. If embodied in dedicated hardware, the functionality of these components can be implemented as a circuit or state machine that employs any one of or a combination of a number of technologies. These technologies may include, but are not limited to, discrete logic circuits having logic gates for implementing various logic functions upon an application of one or more data signals, application specific integrated circuits having appropriate logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), or other components, etc. Such technologies are generally well known by those skilled in the art and, consequently, are not described in detail herein.