Semiconductor storage device

A semiconductor storage device includes a substrate, a first wiring, a second wiring, a third wiring, a fourth wiring, a charge storage unit. The first wiring extends in a first direction along a surface of the substrate. The second wiring is aligned with the first wiring in a second direction intersecting with the first direction and extends in the first direction. The third wiring is in contact with the first wiring and the second wiring and includes a semiconductor. The fourth wiring is located between the first wiring and the second wiring, extends in a third direction intersecting with the first direction and the second direction, and is aligned with the third wiring in at least the first direction. The charge storage unit is located between the third wiring and the fourth wiring.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-154398, filed on Sep. 15, 2020, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor storage device.

BACKGROUND

A semiconductor storage device including a stacked body in which insulating films and word lines are alternately stacked in the thickness direction of a substrate and a channel portion penetrating the stacked body in the thickness direction of the substrate is known.

DETAILED DESCRIPTION

At least one embodiment provides a semiconductor storage device capable of shortening read time.

In general, according to at least one embodiment, the semiconductor storage device includes a substrate, a first wiring, a second wiring, a third wiring, a fourth wiring, and a charge storage unit. The first wiring extends in a first direction along a surface of the substrate. The second wiring is aligned with the first wiring in a second direction intersecting with the first direction and extends in the first direction. The third wiring is in contact with the first wiring and the second wiring and includes a semiconductor. The fourth wiring is located between the first wiring and the second wiring, extends in a third direction intersecting with the first direction and the second direction, and is aligned with the third wiring in at least the first direction. The charge storage unit is located between the third wiring and the fourth wiring.

Hereinafter, the semiconductor storage device of at least one embodiment will be described with reference to the drawings. In the following description, configurations having the same or similar functions are designated by the same reference numerals. Then, the redundant descriptions of those configurations may be omitted. In the present specification, the term “parallel” includes the case of “substantially parallel”. In the present specification, the term “orthogonal” includes the case of “substantially orthogonal”. As used herein, the term “connection” includes not only the case where two members are adjacent to each other without any intervention between them, but also the case where another member is interposed between the two members. As used herein, the term “annular” is not limited to an annular shape, but includes a rectangular or triangular annular shape. In the present specification, the phrase “XX is provided on YY” is not limited to the case where XX is in contact with YY, but includes the case where another member is interposed between XX and YY.

First, the +X direction, the −X direction, the +Y direction, the −Y direction, the +Z direction, and the −Z direction are defined. The +X direction, the −X direction, the +Y direction, and the −Y direction are directions along a surface10a(seeFIG.1) of a silicon substrate10(to be described later). The +X direction is the direction in which a source line SL and a drain line DL (seeFIG.2), which will be described later, extend. The −X direction is opposite to the +X direction. When the +X direction and the −X direction are not distinguished from each other, the directions are simply referred to as an “X direction”. The +Y direction and the −Y direction are directions that intersect (e.g., are orthogonal to each other) with the X direction. The +Y direction is the direction in which the bit line BL (seeFIG.3), which will be described later, extends. The −Y direction is opposite to the +Y direction. When the +Y direction and the −Y direction are not distinguished from each other, the directions are simply referred to as a “Y direction”. The +Z direction and the −Z direction are directions that intersect (e.g., are orthogonal to each other) with the X and Y directions, and are the thickness directions of the silicon substrate10(seeFIG.1). The +Z direction is a direction from the silicon substrate10toward a stacked body20(to be described later). The −Z direction is opposite to the +Z direction. When the +Z direction and the −Z direction are not distinguished from each other, the directions are simply referred to as a “Z direction”. In the present specification, the “+Z direction” may be referred to as “upward” and the “−Z direction” may be referred to as “downward”. However, these expressions are for convenience only and do not specify the direction of gravity. The +X direction is an example of a “first direction”. The +Y direction is an example of a “second direction”. The +Z direction is an example of a “third direction”.

First Embodiment

<1. Configuration of Semiconductor Storage Device>

First, the configuration of the semiconductor storage device1A of the first embodiment will be described. The semiconductor storage device1A is, for example, anon-volatile semiconductor storage device. In the drawings described below, the insulating portion not related to the description may not be illustrated.

FIG.1is a cross-sectional view illustrating the semiconductor storage device1A.FIG.1is a cross-sectional view taken along line F1-F1of the semiconductor storage device1A illustrated inFIG.2. The semiconductor storage device1A includes, for example, a silicon substrate10, an insulating layer11, a semiconductor layer12, a stacked body20, an insulating portion25, a plurality of pillars (columnar bodies)30, an insulating portion STH (seeFIG.2), and an upper structure70, a plurality of contacts80, and a plurality of bit lines BL (only one bit line is illustrated inFIG.1).

<1.1 Lower Structure of Semiconductor Storage Device>

The silicon substrate10is a substrate on which the semiconductor storage device1A is based. At least a part of the silicon substrate10has a plate shape along the X direction and the Y direction. The silicon substrate10has a surface10afacing the stacked body20. The silicon substrate10is formed of a semiconductor material containing silicon (Si). The silicon substrate10is an example of a “substrate”.

The insulating layer11is provided on the surface10aof the silicon substrate10. The insulating layer11has a layer shape along the X direction and the Y direction. The insulating layer11is formed of an insulating material such as silicon oxide (SiO2). A part of a peripheral circuit may be provided between the silicon substrate10and the insulating layer11to operate the semiconductor storage device1A.

The semiconductor layer12is provided on the insulating layer11. The semiconductor layer12has a layer shape along the X direction and the Y direction. The semiconductor layer12is a stopper layer that prevents a memory trench MT from extending deeply (seeFIG.5) in the manufacturing process of the semiconductor storage device1A (to be described later). The semiconductor layer12is formed of a semiconductor material such as polysilicon (poly-Si). When the depth of the memory trench MT is controlled by another factor, the semiconductor layer12may be omitted.

Next, the stacked body20will be described. The stacked body20is provided on the semiconductor layer12. The stacked body20includes a plurality of functional layers21(e.g., functional layers21A to21D) and a plurality of insulating layers22(e.g., insulating layers22A to22D). The plurality of functional layers21and the plurality of insulating layers22are alternately stacked one by one in the Z direction. InFIG.1, for convenience of explanation, four functional layers21and four insulating layers22are illustrated, but in actuality, more functional layers21and insulating layers22may be stacked.

FIG.2is a cross-sectional view taken along line F2-F2of the semiconductor storage device1A illustrated inFIG.1.FIG.2is a cross-sectional view illustrating a first functional layer21A. The first functional layer21A includes a plurality of source lines SL (e.g., source lines SL1to SL3), a plurality of drain line DLs (e.g., drain lines DL1and DL2), and a plurality of insulating portions23. The source line SL is an example of a “first wiring”. The drain line DL is an example of a “second wiring”.

Each of the plurality of source lines SL extends linearly in the X direction. The plurality of source lines SL are arranged in the Y direction at intervals from each other. Each of the plurality of drain lines DL extends linearly in the X direction. The plurality of drain lines DL are arranged in the Y direction at intervals from each other. The plurality of source lines SL and the plurality of drain lines DL are alternately arranged one by one in the Y direction. For example, the drain line DL1is located between the source line SL1and the source line SL2in the Y direction. Another drain line DL2is located between the source line SL2and the source line SL3in the Y direction. In other words, the source line SL2is located on the opposite side to the source line SL1in the Y direction with respect to the drain line DL1. The drain line DL2is located on the opposite side to the drain line DL1in the Y direction with respect to the source line SL2. The source line SL1is an example of a “first source line”. The source line SL2is an example of a “second source line”. The drain line DL1is an example of a “first drain line”. The drain line DL2is an example of a “second drain line”.

The plurality of source lines SL and the plurality of drain lines DL are conductive portions provided in the stacked body20, and are wirings extending in the stacked body20. The plurality of source lines SL and the plurality of drain lines DL are formed of a conductive material such as tungsten (W). In at least one embodiment, the phrase “drain line” means a wiring in which a current flows toward a channel portion50(to be described later). The drain line DL is connected to a sense amplifier circuit SA which is a part of the peripheral circuit of the semiconductor storage device1A. The operation of the sense amplifier circuit SA will be described later. Meanwhile, in at least one embodiment, the phrase “source line” means a wiring in which a current flow through the channel portion50(to be described later). The source line SL is connected to the ground of the semiconductor storage device1A. Meanwhile, the definitions of the “drain line” and the “source line” are not limited to the above examples. For example, the definitions of the “drain line” and the “source line” may be reversed from the above examples.

The insulating portion23is provided between the adjacent source line SL and drain line DL in the Y direction, and electrically insulates the adjacent source line SL and drain line DL. From another point of view, the insulating portion23is provided among a plurality of pillars30(to be described later) adjacent to each other in the X direction, and electrically insulates the plurality of pillars30. The insulating portion23is formed of an insulating material such as silicon oxide (SiO2).

The second to fourth functional layers21B,21C, and21D also have the same configuration as the first functional layer21A. That is, each of the second to fourth functional layers21B,21C, and21D includes a plurality of source lines SL1to SL3, a plurality of drain lines DL1and DL2, and a plurality of insulating portions23.

As illustrated inFIG.1, the source lines SL of the first to fourth functional layers21A to21D are arranged in the Z direction at intervals from each other. The drain lines DL of the first to fourth functional layers21A to21D are arranged in the Z direction at intervals from each other. In other words, the plurality of source lines SL and the plurality of drain lines DL are arranged in a matrix at intervals in the Y direction and the Z direction. The source line SL1in the second functional layer21B is an example of a “third source line”. The drain line DL1in the second functional layer21B is an example of the “third drain line”.

The insulating layer22in the stacked body20is provided between two functional layers21adjacent to each other in the Z direction. The insulating layer22has a layer shape along the X direction and the Y direction. The insulating layer22is formed of an insulating material such as silicon oxide (SiO2). The insulating layer22electrically insulates a plurality of source lines SL parallel to each other in the Z direction. The insulating layer22electrically insulates a plurality of drain lines DL parallel to each other in the Z direction.

The insulating portion25is provided on the uppermost functional layer21in the stacked body20. The insulating portion25is located at the same height as the upper end of the pillar30(to be described later). The insulating portion25is provided among the plurality of pillars30in the X direction and the Y direction.

As illustrated inFIG.2, the plurality of pillars30are arranged in a matrix in the X direction and the Y direction. Each pillar30extends in the Z direction through the stacked body20and the insulating portion25(seeFIG.1). The plurality of pillars30include, for example, a plurality of pillars30A in a first row, a plurality of second pillars30B in a second row, a plurality of third pillars30C in a third row, and a plurality of fourth pillars30D in a fourth row. InFIG.2, for convenience of explanation, the outer shape of each pillar30is illustrated as a rectangular parallelepiped shape. However, the pillar30may be columnar or conical.

The plurality of pillars30A in the first row are provided between the source line SL1and the drain line DL1in the Y direction. The plurality of pillars30A in the first row are arranged in the X direction at intervals from each other. The plurality of pillars30B in the second row are provided between the drain line DL1and the source line SL2in the Y direction. The plurality of pillars30B in the second row are arranged in the X direction at intervals from each other. The plurality of pillars30B in the second row are disposed at positions displaced in the +X direction with respect to the plurality of pillars30A in the first row in the X direction. For example, in the plurality of pillars30A in the first row and the plurality of pillars30B in the second row, the pillars30A in the first row and the pillars30B in the second row are alternately positioned with respect to the X direction.

The plurality of pillars30C in the third row are provided between the source line SL2and the drain line DL2in the Y direction. The plurality of pillars30C in the third row are arranged in the X direction at intervals from each other. For example, the plurality of pillars30A in the first row and the plurality of pillars30C in the third row are located at the same position in the X direction. The plurality of pillars30D in the fourth row are provided between the drain line DL2and the source line SL3in the Y direction. The plurality of pillars30D in the fourth row are arranged in the X direction at intervals from each other. The plurality of pillars30D in the fourth row are disposed at positions displaced in the +X direction with respect to the plurality of pillars30C in the third row in the X direction. For example, in the plurality of pillars30C in the third row and the plurality of pillars30D in the fourth row, the pillars30C in the third row and the pillars30D in the fourth row are alternately positioned with respect to the X direction. For example, the plurality of pillars30B in the second row and the plurality of pillars30D in the fourth row are located at the same position in the X direction. In other words, the plurality of pillars30B in the second row are provided between the plurality of pillars30A in the first row and the plurality of pillars30C in the third row in the Y direction, and are provided at different positions from the plurality of pillars30A in the first row and the plurality of pillars30C in the third row in the X direction.

In at least one embodiment, each pillar30includes a gate wiring31, a block insulating film32, a memory film33, a tunnel insulating film34, a semiconductor layer35, and an upper insulating portion36(seeFIG.1).

The gate wiring31extends in the Z direction so as to extend over the entire length (total height) of the pillar30in the Z direction. The gate wiring31forms the core of the pillar30(the central portion when viewed in the Z direction). The gate wiring31is a conductive portion that penetrates the stacked body20and the insulating portion25in the Z direction. The gate wiring31is formed of a conductive material such as polysilicon (poly-Si) doped with impurities. In the present embodiment, the phrase “gate wiring” means a wiring to which a voltage is applied during a data write operation or a data read operation. According to another definition, the gate wiring31means a wiring to which a voltage is applied to change the charge state of a charge storage unit40(to be described later). The gate wiring31is connected to the bit line BL via a contact80(to be described later). The gate wiring31is an example of a “fourth wiring”.

The block insulating film32is formed in an annular shape surrounding the gate wiring31when viewed in the Z direction. The block insulating film32is provided between the gate wiring31and the memory film33(to be described later). The block insulating film32is an insulating film that prevents back tunneling. Back tunneling is a phenomenon in which electric charge returns from the gate wiring31to the memory film33(charge storage unit40). The block insulating film32extends in the Z direction so as to cover most of the pillar30in the Z direction. The block insulating film32is, for example, a stacked structure film on which a silicon oxide film, a metal oxide film, and a plurality of insulating films are stacked. An example of a metal oxide is an aluminum oxide (Al2O3). The block insulating film32may contain a high dielectric constant material (high-k material) such as silicon nitride (SiN) or hafnium oxide (HfO).

The memory film33is formed in an annular shape surrounding the block insulating film32when viewed in the Z direction. In other words, the memory film33is formed in an annular shape surrounding the gate wiring31when viewed in the Z direction. The memory film33is provided between the block insulating film32and the tunnel insulating film34(to be described later). In at least one embodiment, the memory film33extends in the Z direction so as to cover most of the pillars30. In at least one embodiment, the memory film33is a charge trap film capable of accumulating electric charges in crystal defects. The charge trap film is formed of, for example, silicon nitride (Si3N4).

In at least one embodiment, the memory film33includes a plurality of charge storage units (charge storages)40(seeFIG.1). Each charge storage unit40is a region located at the same height as the source line SL and the drain line DL in the memory film33. In other words, the charge storage unit40is a region of the memory film33that is aligned with one of the first to fourth functional layers21A to21D in the Y direction. The charge storage unit40is a storage unit that may store data by storing a state of electric charge (e.g., the amount of electric charge or the direction of polarization). The charge storage unit40changes the state of electric charge (e.g., the amount of charge or the direction of polarization) when a voltage satisfying a predetermined condition is applied to the gate wiring31. As a result, the charge storage unit40stores the data in a non-volatile manner. For example, the charge storage unit40composed of a charge trap film stores the data in a non-volatile manner according to the amount of electric charge.

As illustrated inFIG.2, the charge storage unit40includes a first portion40aand a second portion40b. The first portion40aof the charge storage unit40is located on the +X direction side with respect to the gate wiring31. The first portion40aof the charge storage unit40is located between the gate wiring31and a first portion50aof the channel portion50(to be described later). Meanwhile, the second portion40bof the charge storage unit40is located on the −X direction side with respect to the gate wiring31. The second portion40bof the charge storage unit40is located between the gate wiring31and a second portion50bof the channel portion50(to be described later).

The tunnel insulating film34is formed in an annular shape surrounding the memory film33when viewed in the Z direction. In other words, the block insulating film32is provided between the memory film33and the semiconductor layer35(to be described later). The tunnel insulating film34is a potential barrier between the charge storage unit40and the semiconductor layer35. The tunnel insulating film34extends in the Z direction so as to cover most of the pillars30. The tunnel insulating film34is formed of silicon oxide (SiO2) or an insulating material containing silicon oxide (SiO2) and silicon nitride (SiN).

The semiconductor layer35is formed in an annular shape surrounding the tunnel insulating film34when viewed in the Z direction. In other words, the semiconductor layer35is provided between the memory film33(charge storage unit40) and the insulating portion23, between the memory film33(charge storage unit40) and the source line SL, and between the memory film33(charge storage unit) and the drain line DL. In at least one embodiment, the semiconductor layer35extends in the Z direction so as to cover most of the pillars30. That is, the semiconductor layer35extends in the Z direction along the gate wiring31. The semiconductor layer35is made of a semiconductor material such as amorphous silicon (a-Si) or polysilicon (poly-Si). The semiconductor layer35may be doped with impurities. The impurities contained in the semiconductor layer35are, for example, anyone selected from the group consisting of carbon, phosphorus, boron, and germanium.

In at least one embodiment, the semiconductor layer35includes a plurality of channel portions50(seeFIG.1). Each channel portion50is a region located at the same height as the source line SL and the drain line DL in the semiconductor layer35. In other words, the channel portion50is a region in the semiconductor layer35that is aligned with one of the first to fourth functional layers21A to21D in the Y direction. The channel portion50includes a semiconductor and is in contact with the source line SL and the drain line DL. In at least one embodiment, the phrase “channel portion” means a region in which a channel is formed when a voltage is applied to the gate wiring31. In at least one embodiment, the channel portion50is a region in which a current (channel current) flows from the drain line DL to the source line SL when a predetermined voltage is applied to the gate wiring31. The channel portion50is an example of the “third wiring”.

In at least one embodiment, each channel portion50includes a first portion50aand a second portion50bdivided on both sides of the gate wiring31in the X direction. The first portion50ais located on the +X direction side with respect to the gate wiring31. The first portion50aextends in the Y direction and is in contact with the source line SL and the drain line DL. The first portion50ais a part of the channel portion50that is aligned with the first portion40aof the charge storage unit40and the gate wiring31in the X direction. The second portion50bis located on the opposite side to the first portion50awith respect to the gate wiring31in the X direction. That is, the second portion50bis located on the −X direction side with respect to the gate wiring31. The second portion50bextends in the Y direction and is in contact with the source line SL and the drain line DL. The second portion50bis a part of the channel portion50that is aligned with the second portion40bof the charge storage unit40and the gate wiring31in the X direction.

In at least one embodiment, the MANOS (Metal-Al-Nitride-Oxide-Silicon) type memory cell MC is formed by the gate wiring31, the block insulating film32, the charge storage unit40, the tunnel insulating film34, and the channel portion50described above. As illustrated in FIGS. and2, the plurality of memory cells MC are three-dimensionally disposed at intervals in the X direction, the Y direction, and the Z direction.

Next, other structures of the stacked body20and the pillar30will be described.

As illustrated inFIG.1, the gate wiring31has an enlarged diameter portion31athat is connected to a select transistor ST (to be described later) at the upper end of the pillar30. The enlarged diameter portion31aprojects in the X direction and the Y direction, and the size in the X direction and the Y direction is enlarged as compared with the other portions of the gate wiring31. The upper end of the semiconductor layer35is located on the −Z direction side with respect to the enlarged diameter portion31aof the gate wiring31. An upper insulating portion36is provided on the semiconductor layer35. The upper insulating portion36is provided between the semiconductor layer35and the enlarged diameter portion31aof the gate wiring31, and electrically insulates the semiconductor layer35and the gate wiring31.

As illustrated inFIG.2, the stacked body20includes an insulating portion STH locally provided in the X direction and the Y direction. The insulating portion STH extends in the Z direction and penetrates the stacked body20to reach the semiconductor layer12. The insulating portion STH is formed by filling the holes provided in the stacked body20with an insulating material in the manufacturing process (replacement process) of the semiconductor storage device1A (to be described later). This content will be described in detail later.

<1.4 Upper Structure of Semiconductor Storage Device>

Next, the upper structure of the semiconductor storage device1A will be described.

As illustrated inFIG.1, an upper structure70is provided on the insulating portion25. The upper structure70includes, for example, a plurality of select transistors ST, a plurality of select gate lines SGL, and an insulating portion75.

The select transistor ST is a vertical transistor located between the contact80(to be described later) and the gate wiring31of the pillar30in the Z direction. The select transistor ST is a switching element that switches the electrical connection state between the contact80and the gate wiring31of the pillar30. The plurality of select transistors ST are arranged in a matrix at positions corresponding to the pillars30in the X direction and the Y direction. An insulating portion75(seeFIG.1) is provided among the plurality of select transistors ST. Each select transistor ST includes, for example, a semiconductor layer71, an insulating layer72, a core insulating portion73, and a gate electrode74.

The semiconductor layer71extends in the Z direction and is in contact with the contact80and the gate wiring31of the pillar30. The semiconductor layer71is formed of a semiconductor material such as amorphous silicon (a-Si) or polysilicon (poly-Si). The semiconductor layer71may be doped with impurities. The impurities contained in the semiconductor layer71are, for example, anyone selected from the group consisting of carbon, phosphorus, boron, and germanium. When a predetermined voltage is applied to the gate electrode74(to be described later), the semiconductor layer71forms a channel to electrically connect the contact80and the gate wiring31of the pillar30. In the present embodiment, the semiconductor layer71is annular when viewed in the Z direction.

The semiconductor layer71has an enlarged diameter portion71aconnected to the contact80(to be described later) at the upper end of the select transistor ST. The enlarged diameter portion71aprojects in the X direction and the Y direction, and the size in the X direction and the Y direction is enlarged as compared with the other portions of the semiconductor layer71.

The insulating layer72is formed in an annular shape surrounding the semiconductor layer71when viewed in the Z direction. At least a part of the insulating layer72is located between the semiconductor layer71and the gate electrode74. The insulating layer72is formed of an insulating material such as silicon oxide (SiO2). The core insulating portion73is provided inside the annular semiconductor layer71. The core insulating portion73is formed of an insulating material such as silicon oxide (SiO2).

The gate electrode74is aligned with the semiconductor layer71in the Y direction. In at least one embodiment, the select transistor ST includes two gate electrodes74. The two gate electrodes74are disposed at different positions in the Z direction. The gate electrode74is provided integrally with, for example, the select gate line SGL (to be described later). In other words, the part of the select gate line SGL that is aligned with the semiconductor layer35in the Y direction functions as the gate electrode74.

FIG.3is a cross-sectional view taken along line F3-F3of the semiconductor storage device1A illustrated inFIG.1. The plurality of select gate lines SGL (e.g., select gate lines SGL1and SGL2) extend in the X direction, respectively. Each select gate line SGL is commonly provided for a plurality of select transistors ST.

For example, the first select gate line SGL1is located between a plurality of select transistors ST corresponding to a plurality of pillars30A in the first row and a plurality of select transistors ST corresponding to a plurality of pillars30B in the second row in the Y direction. The first select gate line SGL1is connected to a gate electrode74of a plurality of select transistors ST corresponding to a plurality of pillars30A in the first row and a gate electrode74of a plurality of select transistors ST corresponding to a plurality of pillars30B in the second row in the Y direction. When a voltage is applied to the first select gate line SGL1, the plurality of select transistors ST corresponding to the plurality of pillars30A in the first row and the plurality of select transistors ST corresponding to the plurality of pillars30B in the second row are in a conductive state.

The second select gate line SGL2is located between the plurality of select transistors ST corresponding to the plurality of pillars30C in the third row and the plurality of select transistors ST corresponding to the plurality of pillars30D in the fourth row in the Y direction. The second select gate line SGL2is connected to the gate electrode74of the plurality of select transistors ST corresponding to the plurality of pillars30C in the third row and the gate electrode74of the plurality of select transistors ST corresponding to the plurality of pillars30D in the fourth row in the Y direction. When a voltage is applied to the second select gate line SGL2, the plurality of select transistors ST corresponding to the plurality of pillars30C in the third row and the plurality of select transistors ST corresponding to the plurality of pillars30D in the fourth row are in a conductive state.

Each contact80is provided between the semiconductor layer71of the select transistor ST and the bit line BL (to be described later) in the Z direction. The contact80connects the semiconductor layer71of the select transistor ST and the bit line BL. The contact80is formed of a conductive material such as tungsten (W).

The plurality of bit lines BL extend in the Y direction. The plurality of bit lines BL include, for example, bit lines BL1to BL6. Each bit line BL is commonly provided for a plurality of pillars30. For example, the bit line BL1is provided above one pillar30A in the first row and one pillar30C in the third row, and is connected to the contact80corresponding to the pillar30A and the contact80corresponding to the pillar30C. When a voltage is applied to the bit line BL1, a voltage is applied to the contact80corresponding to one pillar30A and the contact80corresponding to one pillar30C.

Similarly, the bit lines BL2to BL6are commonly provided for each of the two pillars30. As for the description of the bit lines BL2, BL4, and BL6, the “pillars30A and30C” may be replaced with “pillars30B and30D” in the above description of the bit line BL1. Meanwhile, as for the description of the bit lines BL3and BL5, the “pillars30A and30C” may be read as “pillars30A and30C” as it is in the above description of the bit line BL1. The bit line BL1is an example of a “first bit line”. The bit line BL3is an example of a “second bit line”. One select transistor ST corresponding to the bit line BL1is an example of a “first select transistor”. Another select transistor ST corresponding to the bit line BL1is an example of a “third select transistor”. One select transistor ST corresponding to the bit line BL3is an example of a “second select transistor”.

The configuration of the semiconductor storage device1A has been described above. The charge storage unit40and the channel portion50in the pillar30A at a height corresponding to the first functional layer21A are examples of a “first charge storage unit” and a “first channel portion”. The gate wiring31in the pillar30A is an example of a “first gate wiring”. The charge storage unit40and the channel portion50in another pillar30A at a height corresponding to the first functional layer21A are examples of a “second charge storage unit” and a “second channel portion”. The gate wiring31in the other pillar30A is an example of a “second gate wiring”.

The charge storage unit40and the channel portion50in the pillar30B at a height corresponding to the first functional layer21A are examples of a “third charge storage unit” and a “third channel portion”. The gate wiring31in the pillar30B is an example of a “third gate wiring”. The charge storage unit40and the channel portion50in another pillar30B at a height corresponding to the first functional layer21A are examples of a “fourth charge storage unit” and a “fourth channel portion”. The gate wiring31in the other pillar30B is an example of a “fourth gate wiring”.

The charge storage unit40and the channel portion50in the pillar30A at a height corresponding to the second functional layer21B are examples of a “fifth charge storage unit” and a “fifth channel portion”.

<2. Operation of Semiconductor Storage Device>

Next, the operation of the semiconductor storage device1A will be described.

FIG.4is a cross-sectional view illustrating the operation of the semiconductor storage device1A. In the semiconductor storage device1A, any memory cell MC may be selected as a data write or data read target by combining the select gate line SGL and the bit line BL.

The example illustrated inFIG.4represents a case where a voltage is applied to the select gate line SGL2and a voltage is applied to the bit line BL5. In this case, a voltage is applied to the gate wiring31of one pillar30(hereinafter, referred to as a “select pillar S”) corresponding to the intersection of the select gate line SGL2and the bit line BL5. As a result, a channel is formed in the channel portion50of the select pillar S, and a current I flows from the drain line DL2adjacent to the select pillar S to the source line SL2. For example, the current I flows separately from the first portion50aand the second portion50bof the channel portion50. Meanwhile, no channel is formed in the channel portion50of the pillar30(hereinafter, referred to as a “non-select pillar NS”) other than the select pillar S. As a result, the electrical insulation state between the drain line DL and the source line SL adjacent to the non-select pillar NS is maintained.

The semiconductor storage device1A of at least one embodiment uses the above operations to perform a data write operation and a data read operation on the memory cell MC. For example, in the write operation, the peripheral circuit of the semiconductor storage device1A selects only the pillar30corresponding to the memory cell MC to be written as the select pillar S. Then, the peripheral circuit applies a programming pulse to the gate wiring31of the select pillar S via the bit line BL. The programming pulse is a pulse in which the voltage gradually increases with each cycle. As a result, a current flows through the channel portion50corresponding to the memory cell MC to be written, and the electric charges are accumulated in the charge storage unit40of the memory cell MC to be written. As a result, the threshold voltage of the charge storage unit40rises. The sense amplifier circuit SA determines whether the threshold voltage of the memory cell MC to be written reaches a voltage preset according to the data to be written (hereinafter, referred to as “write data”) for each cycle of the programming pulse. The peripheral circuit continues to apply the programming pulse until the threshold voltage of the memory cell MC reaches the voltage corresponding to the write data according to the determination result by the sense amplifier circuit SA. In the write operation, a predetermined voltage is applied to the drain line DL of the functional layer21that does not include the memory cell MC to be written. As a result, no current flows through the channel portion50corresponding to the memory cell MC other than the write target.

In the read operation, the sense amplifier circuit SA precharges a power supply potential Vcc to the drain line DL adjacent to the memory cell MC to be read. The peripheral circuit selects the pillar30corresponding to the memory cell MC to be read as the select pillar S. Then, the peripheral circuit sequentially applies a plurality of types of determination potentials (threshold determination voltages) that determines the threshold voltage of the memory cell MC to the gate wiring31of the select pillar S. The sense amplifier circuit SA determines the data stored in the memory cell MC to be read by detecting which determination voltage is applied when the electric charges accumulated by the precharge flow out to the source line SL.

<3. Manufacturing Method of Semiconductor Storage Device>

Next, a method of manufacturing the semiconductor storage device1A will be described.FIGS.5to8are cross-sectional views illustrating a method of manufacturing the semiconductor storage device1A. The materials described below are merely examples, and do not limit the contents of the embodiments.

As illustrated in part (a) ofFIG.5, the insulating layer11and the semiconductor layer12are formed on the silicon substrate10. Next, the insulating layer22made of silicon oxide (SiO2) and an insulating layer91made of silicon nitride (SiN) are alternately stacked on the semiconductor layer12. As a result, an intermediate stacked body20A is formed. The insulating layer91is a sacrificial layer that is replaced with the functional layer21in a later process. Next, the insulating portion25is provided on the intermediate stacked body20A. Next, a mask M1is provided on the intermediate stacked body20A and the insulating portion25. Next, the memory trench MT is provided by etching using the mask M1. The memory trench MT is a groove which extends in the Z direction and extends in the X direction. In at least one embodiment, the semiconductor layer12prevents the memory trench MT from extending excessively deeply.

Next, as illustrated in part (b) ofFIG.5, the memory trench MT is filled with an insulating material92made of silicon oxide (SiO2). The insulating material92forms an insulating portion23(seeFIG.2) located among the plurality of pillars30in a later process.

Next, as illustrated in part (c) ofFIG.5, a memory hole MH is provided by etching at a position where the pillar30is formed in a later process. The memory hole MH is a hole extending in the Z direction.

Next, as illustrated in part (d) ofFIG.5, the material of the semiconductor layer35, the material of the tunnel insulating film34, the material of the memory film33, and the material of the block insulating film32are sequentially supplied to the inner surface of the memory hole MH. As a result, the semiconductor layer35, the tunnel insulating film34, the memory film33, and the block insulating film32are formed. Next, polysilicon (poly-Si) is supplied to the inside of the block insulating film32, and impurities are doped. As a result, the gate wiring31is formed. Next, the upper end of the gate wiring31is removed by etch back.

Next, as illustrated in part (e) ofFIG.6, unnecessary portions of the semiconductor layer35, the tunnel insulating film34, the memory film33, and the block insulating film32are removed by etch back, for example. Next, as illustrated in part (f) ofFIG.6, silicon nitride (SiN) is supplied on the semiconductor layer35, the tunnel insulating film34, the memory film33, the block insulating film32, and the gate wiring31, and an upper insulating portion93is formed. Next, a mask M2is provided to remove the central portion of the upper insulating portion93. Next, the central portion of the upper insulating portion93is removed by etching using the mask M2. As a result, the upper insulating portion36is formed.

Next, as illustrated in part (g) ofFIG.6, amorphous silicon (a-Si) is supplied and the enlarged diameter portion31aof the gate wiring31is formed. Next, an insulating layer101made of silicon oxide (SiO2) and an insulating layer102made of silicon nitride (SiN) are alternately stacked. As a result, an intermediate stacked body100is formed. The insulating layer101forms an insulating portion75in a later process. The insulating layer102is a sacrificial layer that is replaced with the gate electrode74of the select transistor ST and the select gate line SGL in a later process. Next, as illustrated in part (h) ofFIG.6, unnecessary portions of the intermediate stacked body100are removed.

Next, as illustrated in part (i) ofFIG.7, the insulating material made of silicon oxide (SiO2) is supplied to the region where the unnecessary portions of the intermediate stacked body100are removed, and an insulating portion105is formed. Next, as illustrated in part (j) ofFIG.7, a hole106in which the semiconductor layer71, the insulating layer72, and the core insulating portion73of the select transistor ST are provided is formed in the intermediate stacked body100and the insulating portion105.

Next, as illustrated in part (k) ofFIG.7, the material of the insulating layer72of the select transistor ST and the material of the semiconductor layer71are supplied to the inner peripheral surface of the hole106. As a result, the insulating layer72and a semiconductor cover layer71bare formed. The semiconductor cover layer71bis a protective layer that protects the insulating layer72. Next, a mask (not illustrated) is used to provide holes in the bottoms of the insulating layer72and the semiconductor cover layer71b.

Next, as illustrated in part (1) ofFIG.7, the material of the semiconductor layer71and the material of the core insulating portion73are supplied to the inner surface of the hole106, and the semiconductor layer71and the core insulating portion73are formed. Next, as illustrated in part (m) ofFIG.8, unnecessary portions of the insulating layer72and the semiconductor layer71are removed. Next, as illustrated in part (n) ofFIG.8, the upper end of the insulating layer72is removed, and the enlarged diameter portion71aof the semiconductor layer71is formed.

Next, as illustrated in part (1) ofFIG.8, an insulating portion107is provided on the select transistor ST. Next, holes (not illustrated) penetrating the intermediate stacked body20A, the insulating portion25, and the intermediate stacked body100in the Z direction are provided, and silicon nitride (SiN) forming the insulating layers91and102is removed through the holes. Next, a conductive material made of tungsten (W) is supplied to the space from which the insulating layers91and102have been removed, and the source line SL, the drain line DL, the gate electrode74, and the select gate line SGL are formed. Next, as illustrated in part (o) ofFIG.8, the contact80is provided in the insulating portion107. Thereafter, the bit line BL is provided. As a result, the semiconductor storage device1A is manufactured.

As a comparative example, a semiconductor storage device is considered which has a stacked body in which insulating films and word lines are alternately stacked in the thickness direction of the substrate, and a channel portion that penetrates the stacked body in the thickness direction of the substrate. In such a semiconductor storage device, the length of the channel portion becomes longer as the number of layers increases. As a result, the read current decreases and the noise during the read operation increases. Therefore, the read time required for reading data may increase.

Further, in the semiconductor storage device of the above comparative example, a sequential read is fast, while the read by a random read takes a longer time. The sequential read means read in word line units. Meanwhile, the random read means an operation of reading data from a plurality of memory cells, not from a specific wiring unit.

The semiconductor storage device of at least one embodiment includes a source line SL and a drain line DL extending in a direction along the surface of the silicon substrate10, a channel portion50provided between the source line SL and the drain line DL, a gate wiring31extending in the thickness direction of the silicon substrate10and aligned with the channel portion50, and a charge storage unit40provided between the channel portion50and the gate wiring31. According to such a configuration, the channel portion50is formed in the direction parallel to the surface of the silicon substrate10, and the length of the channel portion50is shortened. As a result, the decrease in read current and the noise during the read operation are prevented. Therefore, the read time may be shortened.

In the present embodiment, the channel portion50includes a first portion50aand a second portion50bdivided on both sides of the gate wiring31. The charge storage unit40includes a first portion40alocated between the first portion50aof the channel portion50and the gate wiring31, and a second portion40blocated between the second portion50bof the channel portion50and the gate wiring31. According to such a configuration, two paths through which the channel current flows may be secured for one gate wiring31, so that data may be written and read more stably.

As illustrated inFIG.2, the semiconductor storage device1A includes a channel portion50and a charge storage unit40in one pillar30A, and a channel portion50and a charge storage unit40in another pillar30A. These channel portions50are connected in parallel to the same source line SL and drain line DL. According to such a configuration, even when a random read is performed, the memory cell MC may be accessed in a short read time. This enables reading with low latency.

Second Embodiment

Next, a second embodiment will be described. The second embodiment is different from the first embodiment in that the semiconductor layer35is not located in the pillar30B and the semiconductor layer35is divided into several parts in the Z direction. The configuration other than that described below is the same as the configuration of the first embodiment.

FIG.9is a cross-sectional view illustrating the semiconductor storage device1B of the second embodiment. In at least one embodiment, the pillar30B includes a gate wiring31, a block insulating film32, a memory film33, and a tunnel insulating film34, but does not include the semiconductor layer35. In at least one embodiment, the semiconductor layer35is provided in a region aligned with the source line SL and the drain line DL in the Y direction.

In other words, a part of an insulating layer22B is provided between the channel portion50corresponding to the first functional layer21A and the channel portion50corresponding to the second functional layer21B. Similarly, a part of an insulating layer22C is provided between the channel portion50corresponding to the second functional layer21B and the channel portion50corresponding to the third functional layer21C. A part of an insulating layer22D is provided between the channel portion50corresponding to the third functional layer21C and the channel portion50corresponding to the fourth functional layer21D.

FIGS.10and11are cross-sectional views illustrating a method of manufacturing the semiconductor storage device1B of the second embodiment. As illustrated in part (a) ofFIG.10, the insulating layer11and the semiconductor layer12are formed on the silicon substrate10. Next, the insulating layer22made of silicon oxide (SiO2) and the insulating layer91made of silicon nitride (SiN) are alternately stacked on the semiconductor layer35. As a result, the intermediate stacked body20A is formed. The insulating layer91is a sacrificial layer that is replaced with the functional layer21in a later process. Next, the insulating portion25is provided on the intermediate stacked body20A. Next, a mask MB is provided on the insulating portion25. Next, the memory hole MH is provided by etching using the mask MB. The present embodiment is different from the first embodiment in that the memory hole MH is provided instead of the memory trench MT.

Next, as illustrated in part (b) ofFIG.10, the end of the insulating layer91exposed to the memory hole MH in the intermediate stacked body20A is removed by etch back. As a result, a recess111is formed among the plurality of insulating layers22. Next, as illustrated in part (c) ofFIG.10, the material of the semiconductor layer35is supplied to the inner surface of the memory hole MH. Next, the unnecessary portions of the supplied material of the semiconductor layer35are removed by etch back. As a result, the intermediate stacked body20A in which the channel portion50is provided in the recess111among the plurality of insulating layers22is obtained. The plurality of channel portions50arranged in the Z direction are separated by the insulating layer22.

Next, as illustrated in part (d) ofFIG.10, the material of the tunnel insulating film34, the material of the memory film33, and the material of the block insulating film32are sequentially stacked on the inner surface of the memory hole MH. As a result, the tunnel insulating film34, the memory film33, and the block insulating film32are formed. Next, polysilicon (poly-Si) is provided inside the block insulating film32, and impurities are doped. As a result, the gate wiring31is formed. Next, the upper end of the gate wiring31is removed by etch back.

Next, as illustrated in part (e) ofFIG.11, unnecessary portions of the tunnel insulating film34, the memory film33, and the block insulating film32are removed by etch back. Next, as illustrated in part (f) ofFIG.11, amorphous silicon (a-Si) is supplied and the enlarged diameter portion31aof the gate wiring31is formed. Next, as illustrated in part (g) ofFIG.11, a hole112extending in the Z direction is provided in the region between the adjacent pillars30B in the X direction. Next, as illustrated in part (h) ofFIG.11, an insulating material made of silicon oxide (SiO2) is supplied to the hole112and the insulating portion113is formed. The insulating portion113includes the insulating portion23described with respect to the first embodiment.

With such a configuration, it is possible to provide the semiconductor storage device1B capable of shortening the read time as in the first embodiment. In at least one embodiment, the semiconductor layer35is divided in the Z direction, and the channel portion50is provided in a region aligned with the source line SL and the drain line DL. According to such a configuration, the influence of the fringe electric field is smaller than that when the semiconductor layers35are connected in the Z direction. As a result, the data write operation and the data read operation become more stable.

Third Embodiment

Next, a third embodiment will be described. The third embodiment is different from the first embodiment in that the memory film33and the tunnel insulating film34are divided in the Z direction in addition to the semiconductor layer35. The configuration of the third embodiment other than that described below is the same as the configuration of the first embodiment.

FIG.12is a cross-sectional view illustrating the semiconductor storage device1C of the third embodiment, and illustrates an enlarged portion of the memory cell MC. In at least one embodiment, the semiconductor storage device1C includes, for example, a plurality of pillars30C (only one pillar is illustrated in the drawing), a plurality of charge storage units40, a plurality of tunnel insulating films34C, and a plurality of channel portions50.

Each pillar30C includes a gate wiring31and a block insulating film32. The configuration of the gate wiring31and the block insulating film32is the same as that of the first embodiment. That is, the block insulating film32extends in the Z direction along the gate wiring31.

Meanwhile, the charge storage unit40, the tunnel insulating film34C, and the channel portion50are provided between two insulating layers22adjacent to each other in the Z direction. That is, the charge storage unit40, the tunnel insulating film34C, and the channel portion50are insulated for each functional layer21. In at least one embodiment, the channel portion50has a region in the channel portion50that does not overlap with the charge storage unit40in the Y direction and the X direction (i.e., the upper end and the lower end of the channel portion50inFIG.12; hereinafter, referred to as a “specific region”). A tunnel insulating film34C is provided between the specific region of the channel portion50and the block insulating film32in the Y direction and the X direction. As a result, the channel portion50is provided apart from the block insulating film32and is not in contact with the block insulating film32.

FIG.13is a cross-sectional view taken along the line F13-F13of the semiconductor storage device1C illustrated inFIG.12. As illustrated inFIG.13, the charge storage unit40, the tunnel insulating film34C, and the channel portion50are formed in an annular shape surrounding the gate wiring31.

With such a configuration, it is possible to provide the semiconductor storage device1C capable of shortening the read time as in the first embodiment.

Fourth Embodiment

Next, a fourth embodiment will be described. The fourth embodiment is different from the first embodiment in that the memory cell MC has a charge storage unit40D which is a floating gate electrode. The configuration of the fourth embodiment other than that described below is the same as the configuration of the first embodiment.

FIG.14is a cross-sectional view illustrating the semiconductor storage device1D of the fourth embodiment, and illustrates an enlarged portion of the memory cell MC. In at least one embodiment, the semiconductor storage device1D includes, for example, a plurality of pillars30D (only one pillar is illustrated in the drawing), a plurality of charge storage units40D, a plurality of tunnel insulating films34D, and a plurality of channel portions50.

Each pillar30D includes a gate wiring31and a block insulating film32. The configuration of the gate wiring31and the block insulating film32is the same as that of the first embodiment. That is, the block insulating film32extends in the Z direction along the gate wiring31.

Meanwhile, the charge storage unit40D, the tunnel insulating film34D, and the channel portion50are provided between two insulating layers22adjacent to each other in the Z direction. That is, the charge storage unit40D, the tunnel insulating film34D, and the channel portion50are insulated for each functional layer21. The charge storage unit40D is a floating gate electrode and stores data according to the amount of accumulated electric charges. In at least one embodiment, the channel portion50has a region in the channel portion50that does not overlap with the charge storage unit40in the Y direction and the X direction (i.e., the upper end and the lower end of the channel portion50inFIG.14; hereinafter, referred to as a “specific region”). A tunnel insulating film34D is provided between the specific region of the channel portion50and the block insulating film32in the Y direction and the X direction. As a result, the channel portion50is provided apart from the block insulating film32and is not in contact with the block insulating film32.

With such a configuration, it is possible to provide the semiconductor storage device1D capable of shortening the read time as in the first embodiment.

Fifth Embodiment

Next, a fifth embodiment will be described. The fifth embodiment is different from the first embodiment in that the memory cell MC has a charge storage unit40E which is a ferroelectric substance. The configuration other than that described below is the same as the configuration of the first embodiment.

FIG.15is a cross-sectional view illustrating the semiconductor storage device1E of the fifth embodiment, and illustrates an enlarged portion related to the memory cell MC. In at least one embodiment, the semiconductor storage device1E includes, for example, a plurality of pillars30E and a plurality of channel portions50. As in the second embodiment, the channel portion50is provided between two insulating layers22adjacent to each other in the Z direction.

Each pillar30E includes a gate wiring31and a memory film33E. The memory film33E extends in the Z direction along the gate wiring31. The memory film33E is formed in an annular shape surrounding the gate wiring31when viewed in the Z direction. The memory film33E is provided between the gate wiring31and the channel portion50. In at least one embodiment, the memory film33E extends in the Z direction so as to cover most of the pillars30E. In at least one embodiment, the memory film33E is a ferroelectric film constituting a ferroelectric memory (FeFET: Ferroelectric Field Effect Transistor). The charge storage unit40E by the ferroelectric film stores data according to the direction of polarization (state of polarization reversal). The ferroelectric film is formed of a high dielectric constant material such as hafnium oxide (HfO).

In at least one embodiment, the memory film33E includes a plurality of charge storage units40E. Each charge storage unit40E is a region located at the same height as the source line SL and the drain line DL in the memory film33E. In other words, the plurality of charge storage units40E are regions in the memory film33E that are aligned with the first to fourth functional layers21A to21D in the Y direction. The charge storage unit40E is a storage unit that can store data by storing the state of electric charge (e.g., the direction of polarization). The charge storage unit40E changes the state of electric charge (e.g., the direction of polarization) when a voltage satisfying a predetermined condition is applied to the gate wiring31. As a result, the charge storage unit40E stores the data in a non-volatile manner.

With such a configuration, it is possible to provide the semiconductor storage device1E capable of shortening the read time as in the first embodiment. Here, while the ferroelectric memory may be expected to operate at a high speed at a constant voltage, the resistance to disturbance is an issue. However, in at least one embodiment, since no current flows through the channel portion50of the memory cell MC other than the write target or the read target, the problem of disturbance is less likely to occur. As a result, the reliability of the semiconductor storage device1E using the ferroelectric memory may be improved.

In at least one embodiment, the charge storage unit40E may be provided between the two insulating layers22adjacent to each other in the Z direction, as in the third embodiment. Meanwhile, the channel portion50may be formed by the semiconductor layer35extending in the Z direction as in the first embodiment.

According to at least one embodiment described above, the semiconductor storage device includes a substrate, a first wiring, a second wiring, a third wiring, a fourth wiring, and a charge storage unit. The first wiring extends in a first direction along the surface of the substrate. The second wiring is aligned with the first wiring in a second direction intersecting with the first direction and extends in the first direction. The third wiring is in contact with the first wiring and the second wiring, and includes a semiconductor. The fourth wiring is located between the first wiring and the second wiring, extends in a third direction intersecting with the first direction and the second direction, and is aligned with the third wiring in at least the first direction. The charge storage unit is located between the third wiring and the fourth wiring. According to such a configuration, the read time may be shortened.