Beam tracking for 5G millimeter-wave systems

Aspects of mmWave beam tracking and beam sweeping are described, for example, an apparatus can include an antenna array including sub-arrays and processing circuitry configured to perform beamforming, beam tracking, and management thereof at the antenna sub-arrays. The processing circuitry can further be configured to determine the angle of arrival of a received signal received in response to performing the beamforming function and adjust phase shifters of the apparatus according to the angle of arrival. Other apparatuses, systems and methods are described.

TECHNICAL FIELD

Aspects pertain to wireless communications. Some aspects relate to wireless networks including 3GPP (Third Generation Partnership Project) networks, 3GPP LTE (Long Term Evolution) networks, 3GPP LTE-A (LTE Advanced) networks, and fifth-generation (5G) networks including new radio (NR) networks. Other aspects are directed to techniques, methods and apparatuses for beamforming and beam tracking operations.

BACKGROUND

Next-generation (5G and beyond) systems will make use of Massive Multiple Input Multiple Output (MIMO) architecture and millimeter wave (mmWave) operations. One of the main challenges of Massive MIMO systems is power consumption. Another challenge arises in beamforming, because of the increased latency associated with beamforming using all antenna elements present in Massive MIMO systems.

Furthermore, solutions proposed for beam tracking in mmWave systems are non-blind and require pilot signals to be sent in order to acquire beam direction. Such beam tracking can be time consuming and rely on Tx scanning across the beam space and Rx feedback. Because of the time used, such beam tracking may not be helpful in high-speed vehicular applications.

DETAILED DESCRIPTION

FIG. 1illustrates an exemplary user device according to some aspects. The user device100may be a mobile device in some aspects and includes an application processor105, baseband processor110(also referred to as a baseband sub-system), radio front end module (RFEM)115, memory120, connectivity sub-system125, near field communication (NFC) controller130, audio driver135, camera driver140, touch screen145, display driver150, sensors155, removable memory160, power management integrated circuit (PMIC)165, and smart battery170.

In some aspects, application processor105may include, for example, one or more central processing unit (CPU) cores and one or more of cache memory, low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as SPI, I2C or universal programmable serial interface subsystem, real time clock (RTC), timer-counters including interval and watchdog timers, general purpose IO, memory card controllers such as SD/MMC or similar, USB interfaces, MIPI interfaces, and/or Joint Test Access Group (JTAG) test access ports.

In some aspects, baseband processor110may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board, and/or a multi-chip module including two or more integrated circuits.

Applications of mmWave technology can include, for example, WiGig and future 5G, but the mmWave technology can be applicable to a variety of telecommunications systems. The mmWave technology can be especially attractive for short-range telecommunications systems. WiGig devices operate in the unlicensed 60 GHz band, whereas 5G mmWave is expected to operate initially in the licensed 28 GHz and 39 GHz bands. A block diagram of an example baseband sub-system110and RFEM115in a mmWave system is shown inFIG. 1A.

FIG. 1Aillustrates a mmWave system100A, which can be used in connection with the device100ofFIG. 1according to some aspects of the present disclosure. The system100A includes two components: a baseband sub-system110and one or more radio front end modules (RFEMs)115. The RFEM115can be connected to the baseband sub-system110by a single coaxial cable190, which supplies a modulated intermediate frequency (IF) signal, DC power, clocking signals and control signals.

The baseband sub-system110is not shown in its entirety, butFIG. 1Arather shows an implementation of analog front end. This includes a transmitter (TX) section191A with an upconverter173to intermediate frequency (IF) (around 10 GHz in current implementations), a receiver (RX) section191B with down-conversion175from IF to baseband, control and multiplexing circuitry177including a combiner to multiplex/demultiplex transmit and receive signals onto a single cable190. In addition, power tee circuitry192(which includes discrete components) is included on the baseband circuit board to provide DC power for the RFEM115. In some aspects, the combination of the TX section and RX section may be referred to as a transceiver, to which may be coupled one or more antennas or antenna arrays of the types described herein.

The RFEM115can be a small circuit board including a number of printed antennas and one or more RF devices containing multiple radio chains, including up-conversion/down-conversion174to millimeter wave frequencies, power combiner/divider176, programmable phase shifting178and power amplifiers (PA)180, low noise amplifiers (LNA)182, as well as control and power management circuitry184A and184B. This arrangement can be different from Wi-Fi or cellular implementations, which generally have all RF and baseband functionality integrated into a single unit and only antennas connected remotely via coaxial cables.

This architectural difference can be driven by the very large power losses in coaxial cables at millimeter wave frequencies. These power losses can reduce the transmit power at the antenna and reduce receive sensitivity. To avoid this issue, in some aspects, PAs180and LNAs182may be moved to the RFEM115with integrated antennas. In addition, the RFEM115may include up-conversion/down-conversion174so that the IF signals over the coaxial cable190can be at a lower frequency. Additional system context for mmWave 5G apparatuses, techniques and features is discussed herein below.

FIG. 2illustrates an exemplary base station or infrastructure equipment radio head according to some aspects. A base station may be termed, for example, an Evolved Node-B (eNB, eNodeB), or a New Radio Node-B (gNB, gNodeB). In some aspects, the base station radio head200may include one or more of application processor205, baseband processors210, one or more radio front end modules215, memory220, power management integrated circuitry (PMIC)225, power tee circuitry230, network controller235, network interface connector240, satellite navigation receiver (e.g., GPS receiver)245, and user interface250.

In some aspects, application processor205may include one or more CPU cores and one or more of cache memory, low drop-out voltage regulators (LDOs), interrupt controllers, serial interfaces such as SPI, I2C or universal programmable serial interface, real time clock (RTC), timer-counters including interval and watchdog timers, general purpose IO, memory card controllers such as SD/MMC or similar, USB interfaces, MIPI interfaces and Joint Test Access Group (JTAG) test access ports.

In some aspects, baseband processor210may be implemented, for example, as a solder-down substrate including one or more integrated circuits, a single packaged integrated circuit soldered to a main circuit board or a multi-chip sub-system including two or more integrated circuits.

In some aspects, memory220may include one or more of volatile memory including dynamic random access memory (DRAM) and/or synchronous DRAM (SDRAM), and nonvolatile memory (NVM) including high-speed electrically erasable memory (commonly referred to as Flash memory), phase-change random access memory (PRAM), magneto-resistive random access memory (MRAM), and/or a three-dimensional cross point memory. Memory220may be implemented as one or more of solder down packaged integrated circuits, socketed memory modules and plug-in memory cards.

In some aspects, power management integrated circuitry225may include one or more of voltage regulators, surge protectors, power alarm detection circuitry and one or more backup power sources such as a battery or capacitor. Power alarm detection circuitry may detect one or more of brown out (under-voltage) and surge (over-voltage) conditions.

In some aspects, power tee circuitry230may provide for electrical power drawn from a network cable. Power tee circuitry230may provide both power supply and data connectivity to the base station radio head200using a single cable.

In some aspects, network controller235may provide connectivity to a network using a standard network interface protocol such as Ethernet. Network connectivity may be provided using a physical connection which is one of electrical (commonly referred to as copper interconnect), optical or wireless.

In some aspects, satellite navigation receiver245may include circuitry to receive and decode signals transmitted by one or more navigation satellite constellations such as the global positioning system (GPS), Globalnaya Navigatsionnaya Sputnikovaya Sistema (GLONASS), Galileo and/or BeiDou. The receiver245may provide, to application processor205, data which may include one or more of position data or time data. Time data may be used by application processor205to synchronize operations with other radio base stations or infrastructure equipment.

In some aspects, user interface250may include one or more of buttons. The buttons may include a reset button. User interface250may also include one or more indicators such as LEDs and a display screen.

FIG. 3Aillustrates exemplary mmWave communication circuitry according to some aspects;FIGS. 3B and 3Cillustrate aspects of transmit circuitry shown inFIG. 3Aaccording to some aspects;FIG. 3Dillustrates aspects of radio frequency circuitry shown inFIG. 3Aaccording to some aspects;FIG. 3Eillustrates aspects of receive circuitry inFIG. 3Aaccording to some aspects. Millimeter wave communication circuitry300shown inFIG. 3Amay be alternatively grouped according to functions. Components illustrated inFIG. 3Aare provided here for illustrative purposes and may include other components not shown inFIG. 3A.

Millimeter wave communication circuitry300may include protocol processing circuitry305(or processor) or other means for processing. Protocol processing circuitry305may implement one or more of medium access control (MAC), radio link control (RLC), packet data convergence protocol (PDCP), radio resource control (RRC) and non-access stratum (NAS) functions, among others. Protocol processing circuitry305may include one or more processing cores to execute instructions and one or more memory structures to store program and data information.

Millimeter wave communication circuitry300may further include digital baseband circuitry310. Digital baseband circuitry310may implement physical layer (PHY) functions including one or more of hybrid automatic repeat request (HARQ) functions, scrambling and/or descrambling, coding and/or decoding, layer mapping and/or de-mapping, modulation symbol mapping, received symbol and/or bit metric determination, multi-antenna port pre-coding and/or decoding which may include one or more of space-time, space-frequency or spatial coding, reference signal generation and/or detection, preamble sequence generation and/or decoding, synchronization sequence generation and/or detection, control channel signal blind decoding, and other related functions.

Millimeter wave communication circuitry300may further include transmit circuitry315, receive circuitry320and/or antenna array circuitry330. Millimeter wave communication circuitry300may further include RF circuitry325. In some aspects, RF circuitry325may include one or multiple parallel RF chains for transmission and/or reception. Each of the RF chains may be connected to one or more antennas of antenna array circuitry330.

In some aspects, protocol processing circuitry305may include one or more instances of control circuitry. The control circuitry may provide control functions for one or more of digital baseband circuitry310, transmit circuitry315, receive circuitry320, and/or RF circuitry325.

FIGS. 3B and 3Cillustrate aspects of transmit circuitry shown inFIG. 3Aaccording to some aspects. Transmit circuitry315shown inFIG. 3Bmay include one or more of digital to analog converters (DACs)340, analog baseband circuitry345, up-conversion circuitry350and/or filtering and amplification circuitry355. DACs340may convert digital signals into analog signals. Analog baseband circuitry345may perform multiple functions as indicated below. Up-conversion circuitry350may up-convert baseband signals from analog baseband circuitry345to RF frequencies (e.g., mmWave frequencies). Filtering and amplification circuitry355may filter and amplify analog signals. Control signals may be supplied between protocol processing circuitry305and one or more of DACs340, analog baseband circuitry345, up-conversion circuitry350and/or filtering and amplification circuitry355.

Transmit circuitry315shown inFIG. 3Cmay include digital transmit circuitry365and RF circuitry370. In some aspects, signals from filtering and amplification circuitry355may be provided to digital transmit circuitry365. As above, control signals may be supplied between protocol processing circuitry305and one or more of digital transmit circuitry365and RF circuitry370.

FIG. 3Dillustrates aspects of radio frequency circuitry shown inFIG. 3Aaccording to some aspects. Radio frequency circuitry325may include one or more instances of radio chain circuitry372, which in some aspects may include one or more filters, power amplifiers, low noise amplifiers, programmable phase shifters and power supplies.

Radio frequency circuitry325may also in some aspects include power combining and dividing circuitry374. In some aspects, power combining and dividing circuitry374may operate bidirectionally, such that the same physical circuitry may be configured to operate as a power divider when the device is transmitting, and as a power combiner when the device is receiving. In some aspects, power combining and dividing circuitry374may include one or more wholly or partially separate circuitries to perform power dividing when the device is transmitting and power combining when the device is receiving. In some aspects, power combining and dividing circuitry374may include passive circuitry including one or more two-way power divider/combiners arranged in a tree. In some aspects, power combining and dividing circuitry374may include active circuitry including amplifier circuits.

In some aspects, radio frequency circuitry325may connect to transmit circuitry315and receive circuitry320inFIG. 3A. Radio frequency circuitry325may connect to transmit circuitry315and receive circuitry320via one or more radio chain interfaces376and/or a combined radio chain interface378. In some aspects, one or more radio chain interfaces376may provide one or more interfaces to one or more receive or transmit signals, each associated with a single antenna structure. In some aspects, the combined radio chain interface378may provide a single interface to one or more receive or transmit signals, each associated with a group of antenna structures.

FIG. 3Eillustrates aspects of receive circuitry inFIG. 3Aaccording to some aspects. Receive circuitry320may include one or more of parallel receive circuitry382and/or one or more of combined receive circuitry384. In some aspects, the one or more parallel receive circuitry382and one or more combined receive circuitry384may include one or more Intermediate Frequency (IF) down-conversion circuitry386, IF processing circuitry388, baseband down-conversion circuitry390, baseband processing circuitry392and analog-to-digital converter (ADC) circuitry394. As used herein, the term “intermediate frequency” refers to a frequency to which a carrier frequency (or a frequency signal) is shifted as in intermediate step in transmission, reception, and/or signal processing. IF down-conversion circuitry386may convert received RF signals to IF. IF processing circuitry388may process the IF signals, e.g., via filtering and amplification. Baseband down-conversion circuitry390may convert the signals from IF processing circuitry388to baseband. Baseband processing circuitry392may process the baseband signals, e.g., via filtering and amplification. ADC circuitry394may convert the processed analog baseband signals to digital signals.

FIG. 4illustrates exemplary RF circuitry ofFIG. 3Aaccording to some aspects. In an aspect, RF circuitry325inFIG. 3A(depicted inFIG. 4using reference number425) may include one or more of the IF interface circuitry405, filtering circuitry410, up-conversion and down-conversion circuitry415, synthesizer circuitry420, filtering and amplification circuitry424, power combining and dividing circuitry430, and radio chain circuitry435.

FIG. 5AandFIG. 5Billustrate aspects of a radio front end module useable in the circuitry shown inFIG. 1andFIG. 2, according to some aspects.FIG. 5Aillustrates an aspect of a radio front end module (RFEM) according to some aspects. RFEM500incorporates a millimeter wave RFEM505and one or more above-six gigahertz radio frequency integrated circuits (RFIC)515and/or one or more sub-six gigahertz RFICs522. In this aspect, the one or more sub-six gigahertz RFICs515and/or one or more sub-six gigahertz RFICs522may be physically separated from millimeter wave RFEM505. RFICs515and522may include connection to one or more antennas520. RFEM505may include multiple antennas510.

FIG. 5Billustrates an alternate aspect of a radio front end module, according to some aspects. In this aspect both millimeter wave and sub-six gigahertz radio functions may be implemented in the same physical radio front end module (RFEM)530. RFEM530may incorporate both millimeter wave antennas535and sub-six gigahertz antennas540.

FIG. 6illustrates a multi-protocol baseband processor600useable in the system and circuitry shown inFIG. 1orFIG. 2, according to some aspects. In an aspect, baseband processor may contain one or more digital baseband subsystems640A,640B,640C,640D, also herein referred to collectively as digital baseband subsystems640.

In an aspect, the one or more digital baseband subsystems640A,640B,640C,640D may be coupled via interconnect subsystem665to one or more of CPU subsystem670, audio subsystem675and interface subsystem680. In an aspect, the one or more digital baseband subsystems640may be coupled via interconnect subsystem645to one or more of each of digital baseband interface660A,660B and mixed-signal baseband subsystem635A,635B.

In an aspect, interconnect subsystem665and645may each include one or more of each of buses point-to-point connections and network-on-chip (NOC) structures. In an aspect, audio subsystem675may include one or more of digital signal processing circuitry, buffer memory, program memory, speech processing accelerator circuitry, data converter circuitry such as analog-to-digital and digital-to-analog converter circuitry, and analog circuitry including one or more of amplifiers and filters.

FIG. 7illustrates an exemplary of a mixed signal baseband subsystem700, according to some aspects. In an aspect, mixed signal baseband subsystem700may include one or more of IF interface705, analog IF subsystem710, down-converter and up-converter subsystem720, analog baseband subsystem730, data converter subsystem735, synthesizer725and control subsystem740.

FIG. 8Aillustrates a digital baseband processing subsystem801, according to some aspects.FIG. 8Billustrates an alternate aspect of a digital baseband processing subsystem802, according to some aspects.

In an aspect ofFIG. 8A, the digital baseband processing subsystem801may include one or more of each of digital signal processor (DSP) subsystems805A,805B, . . .805N, interconnect subsystem835, boot loader subsystem810, shared memory subsystem815, digital I/O subsystem820, and digital baseband interface subsystem825.

In an aspect ofFIG. 8B, digital baseband processing subsystem802may include one or more of each of accelerator subsystem845A,845B, . . .845N, buffer memory850A,850B, . . .850N, interconnect subsystem835, shared memory subsystem815, digital I/O subsystem820, controller subsystem840and digital baseband interface subsystem825.

In an aspect, boot loader subsystem810may include digital logic circuitry configured to perform configuration of the program memory and running state associated with each of the one or more DSP subsystems805. Configuration of the program memory of each of the one or more DSP subsystems805may include loading executable program code from storage external to digital baseband processing subsystems801and802. Configuration of the running state associated with each of the one or more DSP subsystems805may include one or more of the steps of: setting the state of at least one DSP core which may be incorporated into each of the one or more DSP subsystems805to a state in which it is not running, and setting the state of at least one DSP core which may be incorporated into each of the one or more DSP subsystems805into a state in which it begins executing program code starting from a predefined memory location.

In an aspect, shared memory subsystem815may include one or more of read-only memory (ROM), static random access memory (SRAM), embedded dynamic random access memory (eDRAM) and/or non-volatile random access memory (NVRAM).

In an aspect, digital I/O subsystem820may include one or more of serial interfaces such as Inter-Integrated Circuit (I2C), Serial Peripheral Interface (SPI) or other 1, 2 or 3-wire serial interfaces, parallel interfaces such as general-purpose input-output (GPIO), register access interfaces and direct memory access (DMA). In an aspect, a register access interface implemented in digital I/O subsystem820may permit a microprocessor core external to digital baseband processing subsystem801to read and/or write one or more of control and data registers and memory. In an aspect, DMA logic circuitry implemented in digital I/O subsystem820may permit transfer of contiguous blocks of data between memory locations including memory locations internal and external to digital baseband processing subsystem801.

In an aspect, digital baseband interface subsystem825may provide for the transfer of digital baseband samples between baseband processing subsystem and mixed signal baseband or radio-frequency circuitry external to digital baseband processing subsystem801. In an aspect, digital baseband samples transferred by digital baseband interface subsystem825may include in-phase and quadrature (I/Q) samples.

In an aspect, controller subsystem840may include one or more of each of control and status registers and control state machines. In an aspect, control and status registers may be accessed via a register interface and may provide for one or more of: starting and stopping operation of control state machines, resetting control state machines to a default state, configuring optional processing features, and/or configuring the generation of interrupts and reporting the status of operations. In an aspect, each of the one or more control state machines may control the sequence of operation of each of the one or more accelerator subsystems845. There may be examples of implementations of bothFIG. 8AandFIG. 8Bin the same baseband subsystem.

FIG. 9illustrates a digital signal processor (DSP) subsystem900according to some aspects.

In an aspect, DSP subsystem900may include one or more of each of DSP core subsystem905, local memory910, direct memory access (DMA) subsystem915, accelerator subsystem920A,920B . . .920N, external interface subsystem925, power management circuitry930and interconnect subsystem935.

In an aspect, local memory910may include one or more of each of read-only memory, static random access memory or embedded dynamic random access memory.

In an aspect, the DMA subsystem915may provide registers and control state machine circuitry adapted to transfer blocks of data between memory locations including memory locations internal and external to DSP subsystem900.

In an aspect, external interface subsystem925may provide for access by a microprocessor system external to DSP subsystem900to one or more of memory, control registers and status registers which may be implemented in DSP subsystem900. In an aspect, external interface subsystem925may provide for transfer of data between local memory910and storage external to DSP subsystem900under the control of one or more of the DMA subsystem915and the DSP core subsystem905.

FIG. 10Aillustrates an example of an accelerator subsystem1000according to some aspects.FIG. 10Billustrates an example of an accelerator subsystem1000according to some aspects.

In an aspect, accelerator subsystem1000may include one or more of each of control state machine1005, control registers1010, memory interface1020, scratchpad memory1025, computation engine1030A . . .1030N and dataflow interface1035A,1035B.

In an aspect, control registers1010may configure and control the operation of accelerator subsystem1000, which may include one or more of: enabling or disabling operation by means of an enable register bit, halting an in-process operation by writing to a halt register bit, providing parameters to configure computation operations, providing memory address information to identify the location of one or more control and data structures, configuring the generation of interrupts, or other control functions.

In an aspect, control state machine1005may control the sequence of operation of accelerator subsystem1000.

Joint Analog and Digital Beam Tracking with Hybrid Phased Array

A mmWave communication system has been regarded as a promising technology for the next generation of cellular systems. MmWave communication systems can include multiple receive antennas. The small wavelength of mmWave frequencies allows for a large number of antennas to be included in a small area. The beamforming gain realized in systems with multiple antennas provides less inter-cell and intra-cell interference, high data rate and more cellular capacity.

However, one challenge with mmWave communication systems is power consumption in devices having multiple antennas. In order to reduce power costs, a hybrid phase array can be used, which combines received signals from different antennas in the analog domain after adjusting relative phases using phase shifters. This architecture reduces hardware cost of ADCs (RF-chain) and subsequent digital processing.

Analog phased arrays can combine signals in analog domain using phase shifters and requires only one pair of ADCs (RF-chain). However, analog combining may limit beamforming and beam tracking capability of a mmWave communication system. To support multi-user/multi-beamforming, a hybrid phased array architecture using more than one RF-chain can be provided.

Systems, methods and apparatuses according to aspects can perform joint analog and digital beam tracking using smaller arrays. Apparatuses, systems and methods according to aspects can use antenna arrays of a reduced size to perform quicker beam sweeping in the digital domain. After finding the best beam direction in the digital domain, apparatuses according to some aspects adjust the analog beamforming vector to have the largest beamforming gain. Aspects can further improve accuracy of angle of arrival estimations.

FIG. 11illustrates a sub-array type hybrid architecture1100according to some aspects. Radio frequency front end (RFFE)1102provides multiple antenna inputs1104. Phase shifters1106can be used to combine the antenna signals in the analog domain, and ADCs1108convert the combined signals to the digital domain before providing to baseband processor1110. However, it will be appreciated that algorithms provided herein can be applied to digital and fully connected hybrid beamforming architectures.

Combining received signals in the analog domain (as shown inFIG. 11) limits initial access latency and beam tracking capability. For mobile users, this leads to frequent communication link failure. In aspects, a joint analog and digital beam tracking method is proposed for subarray type hybrid phase array architectures as depicted inFIG. 11. In aspects, operations of the joint analog and digital beam tracking method can be performed by processing circuitry (e.g., baseband processor110(FIG. 1)).

Consider a uniform array1200with Nrantennas1202and NrrfRF-chains1204at the receiver as shown inFIG. 12. Results can also be extended to rectangular arrays. Assume antenna spacing d between antennas1202.

a⁡(θ)=[1,ej⁢2⁢π⁢⁢dcos⁡(θ)λ,…⁢,ej⁢2⁢π⁢⁢d⁡(Nr-1)⁢cos⁡(θ)λ](1)
where λ is the wavelength of the carrier frequency.

For mobile users, the angle of arrival will change over time and beamforming gain will degrade if w is not adapted to time varying θ. Algorithms according to some aspects track the time varying azimuth angle θ(t) and maximize beamforming gain according to the estimated angle of arrival.

The corresponding beamforming gain optimization problem can be written as follows:

To reduce complexity, a discrete set of beam steering angles are predefined in a codebook according to, for example, a standard of the Institute of Electrical and Electronics Engineers (IEEE) 802.11ad family of standards, and w(t) is set to one of the codebook vectors that maximizes beamforming gain. However, following this approach means that beam sweeping time becomes large when using analog phase shifters because an analog antenna array can look at only one beam direction in the codebook at a time. In addition, due to quantization of the steering angle, systems can experience beam steering mismatch.

However, beam steering latency and beam steering error can be reduced by dividing the antenna array into small subarrays. Systems and algorithms according to some aspects can perform beam steering with wide beam patterns using subarrays of a hybrid phased array to find the exact angle of arrival using a digital RF-chain. Then, the analog phase shifters can be adjusted according to the estimated angle of arrival, according to algorithms provided below, implemented in processing circuitry (e.g., baseband processor110(FIG. 1)).

Because systems according to aspects are based on a hybrid phased array, the received signals of each subarray (or in general received signals corresponding to an RF chain) are combined in the analog domain after phase shifters and before ADC/DAC. For a given phase shifter excitation, w, the beam formed signal at the receiver is observed as follows:

r⁡(t)=[w0,w1,…⁢,wNrNrrf-1000⋱000wNr-NrNrrf-1,wNr-NrNrrf,…⁢,WNr-1]⁢a⁡(θ⁡(t))⁢s+n(3)
where r(t) is received signal, s is transmitted signal, n is additive white Gaussian noise.

A blind angle of arrival estimation algorithm could be used to estimate θ(t). However, as the accuracy of angle of arrival estimation depends on w and processing circuitry in some aspects can implement a method outlined below to find the analog beam steering vector w.

FIG. 13illustrates how equivalent antenna arrays can be defined according to some aspects. In an initial operation for finding the analog beam steering vector w, processing circuitry can set the initial sub-array beamforming vectors. In aspects, the processing circuitry uses the same beamforming vector for each sub-array in order to cause an equivalent sub-array to have the same array pattern, as shown inFIG. 13. However, the results can be generalized to different array patterns. With reference toFIG. 13, if the same beamforming vector is applied to each subarray1302,1304,1306,1308, the equivalent antenna array1310,1312,1314,1316can be considered to be a Nrrfantenna array with antenna patterns equal to array pattern of subarrays1302,1304,1306,1308as depicted.

However, after the processing circuitry implements subarray beamforming, using the initial sub-array beamforming vectors, when current angle of arrival estimation algorithms are applied to received signal

r⁡(t),NrNrrf⁢2⁢dλ
ambiguous (grating) arrival angles are observed at receiver circuitry. This is because the effective inter-element spacing becomes

NrNrrf⁢d,
which is larger than λ/2. For example, if

d=λ/2⁢⁢and⁢⁢NrNrrf=4,
four grating angle of arrival estimations become necessary, and it is not possible to find correct angle of arrival. Therefore, to find correct angle of arrival, processing circuitry will steer the beam of subarrays towards these four grating directions in some aspects, and measure power gain of each grating direction. The processing circuitry will select the grating direction having the highest gain according to Equation (4), which uses a discrete Fourier transform (DFT) codebook with size

This codebook has

NrNrrf
beam directions which is sufficient to steer the beam all grating directions. It is sufficient to use DFT codebook to steer beam towards grating directions, according to a mathematical proof provided below.

Given grating direction θg1we can write:

ej⁢2⁢π⁢⁢dNr⁢cos(θg⁢⁢1)λ⁢⁢Nrrf=ej⁢⁢2⁢π⁢⁢k+φ,k=0,1,2,3⁢…⁢⁢and⁢⁢φ∈[0,2⁢π)(5)
where the left hand side of equation is obtained from array vector of equivalent antenna array, i.e.

aequivalent⁢⁢array⁡(θg⁢⁢1)[1,ej⁢2⁢π⁢⁢dNr⁢cos⁡(θg⁢⁢1)λ⁢⁢Nrrf,…⁢,ej⁢2⁢π⁢⁢dNr⁡(NrNrrf-1)⁢cos⁡(θg⁢⁢1)λ⁢⁢Nrrf](6)
and the right hand side of equation follows from the periodicity of the complex exponential function.

Grating angles are given according to:

θgk=cos-1⁡(k⁢⁢λ⁢⁢Nrrfd⁢⁢Nr+ψ),k=1,2,3,…(7)
where ψ is auxiliary variable for

If the steering angle θ of array vector of subarray is replaced with the grating angles in (7):

Above, it was proven that the DFT codebook at subarrays is sufficient to have beamforming gain towards the direction of grating angle. However, for each DFT direction, φ needs to be estimated to find accurate θgk, k=1, 2 . . . .

To estimate φ, processing circuitry applies one of the rows of the DFT beamforming codebook to each subarray sequentially, and for each case the processing circuitry estimates the angle of arrival using digital angle of arrival estimation algorithms. The estimation of angle of arrivals can be extended to pilot-based methods in which beam tracking is performed only subsequent to receiving a pilot sequence. The procedure can be written as follows: first, the processing circuitry applies DFTkTbeamforming vector to each sub-array. Next, the processing circuitry estimates angle of arrival θ with any blind algorithm such that

fk=maxθk⁢aH⁡(θk)⁢WH⁢r⁡(t)2(10)
such that

Subsequent to executing Equations (10)-(12), for each direction, the processing circuitry measures received signal strength and selects the strongest {circumflex over (θ)}=θk*, where

Setting final phase values according to estimated angle of arrival: After selecting best DFT direction for subarray and finding correct angle of arrival, the processing circuitry sets final phase values according to the estimated angle of arrival. For example, the processing circuitry sets w as follows:
w←a({circumflex over (θ)})  (14)
where a({circumflex over (θ)}) was defined in (1) above.

The above process can be summarized using examples based on different scenarios. A first scenario, implementing beam tracking algorithms for fast varying channels, can be summarized according to the below.

Given as inputs: total number of antennas Nr, and RF-chains Nrrf

k=0⁢⁢to⁢⁢NrNrrf-1,
the processing circuitry applies beamforming vector DFTkTto each sub-array. Next, the processing circuitry estimates the angle of arrival θ with any blind algorithm such that

fk,k=0,…⁢,NrNrrf-1.
Finally, set w←a({circumflex over (θ)}), where a({circumflex over (θ)}) is defined in (1).

Similarly, a second scenario applies to beam tracking algorithms for slow-varying channels. In this case, assuming the best DFT beam direction, DFTkT, is known for subarrays. The processing circuitry adjust w for better beamforming towards the direction of the new channel:

Given as inputs: total number of antennas N, and RF-chains Nrrf, and DFTk*T, apply DFTk*Tbeamforming vector to each sub-array. Next the processing circuitry estimates angle of arrival θ with any blind algorithm such

that⁢⁢θ^=arg⁢⁢maxθ⁢aH⁡(θ)⁢WH⁢r⁡(t)2⁢such⁢⁢that⁢⁢cos-1⁡(k*⁢λ⁢⁢Nrrfd⁢⁢Nr)≤θ<cos-1⁡((k*+1)⁢λ⁢⁢Nrrfd⁢⁢Nr),⁢and⁢⁢where⁢⁢W=[DFTk*T…0⋮⋱⋮0…DFTkT].
Finally set w←a({circumflex over (θ)}), where a({circumflex over (θ)}) defined in (1).

FIG. 14illustrates a method1400of joint analog and digital beam tracking with a hybrid phased array according to some aspects. Some operations of the method1400can be performed by a processing circuitry such as baseband processor110(FIG. 1).

Method1400begins with operation1402with the processing circuitry performing a beamforming function at antenna sub-arrays. For example, beamforming can be performed at

NrNrrf
where Nris the number of antennas (e.g., antennas1202) and Nrrfis the number of RF-chains (e.g., RF-chain1204) of the apparatus (e.g., user device100(FIG. 1). The beamforming can be performed using a beamforming vector that has been applied to each antenna sub-array of the

NrNrrf
sub-arrays such that an array pattern of each antenna sub-array is substantially the same, as illustrated inFIG. 13.

Method1400can continue with operation1404with the processing circuitry determining the angle of arrival of a received signal received in response to performing the beamforming function. The angle of arrival can be determined by steering each sub-array toward each of

NrNrrf⁢2⁢dλ
grating angles, where d is the distance between each sub-array and λ is the wavelength of the received signal, and then selecting the grating angle having the largest measured power gain as the angle of arrival, as discussed above with reference to Equations (4). The steering can be performed using a DFT codebook with a size of

Method1400can continue with operation1406with the processing circuitry adjust phase shifters of the apparatus according to the angle of arrival.

A Low Power/Complexity Beam Tracking Method Using Multi-Finger Beam

Analog phased arrays can be used in massive MIMO and mmWave systems to reduce hardware costs associated with ADCs. An analog phased array architecture combines signals received in the analog domain using phase shifters and uses only one pair of ADCs (RF-chain). However, analog combining may limit beamforming and beam tracking capability of a mmWave communication system when narrow beams (e.g. DFT beamforming codebook) are considered to maximize main beam power. Aspects provide a power-efficient and fast beam tracking method in devices using a single-RF-chain (analog beamforming) mmWave communication system. Aspects provide apparatuses and methods to perform beamforming in an analog beamforming architecture. In aspects, two sets of codebooks are used in beamforming and, by switching between code words and codebooks, an apparatus can find a best beam direction without changing the effective channel of operation and disrupting communication.

FIG. 15illustrates an analog beamforming architecture1500in accordance with some aspects. In at least some aspects, the architecture1500uses phase shifters1502connected to antenna elements1504to combine a signal received in the analog domain. The architecture uses one DAC/ADC pair (RF-chain1506). By using the phase shifters1502, one beam1508can be generated, with different beam patterns and various beam steering directions.

FIG. 16illustrates the impact of mobility on beam steering according to some aspects. Narrow beamforming can produce the highest gains for stationary users. However, narrow beamforming can lead to beam steering errors and loss of communication links for mobile users, particular mobile users who move at high speeds (e.g., vehicles). For example, base station1602can transmit a beam1604to reach user1606. However, if user1606moves to a new position as shown, the beam1604can no longer be received by the user1606.

FIG. 17illustrates multi-finger asymmetrical beamforming according to some aspects. In aspects implementing multi-finger asymmetrical beamforming, each user equipment (UE)1700can generate one main lobe1702having a larger beamforming gain, and one secondary lobe1704with lower beamforming gain adjacent to main lobe1702. Multi-finger beamforming patterns can be symmetrical with respect to main lobe as shown inFIG. 17. In addition, the two beamforming patterns can be designed such that the received signal after beamforming has a similar beamforming gain if direction of arrival is within half power beam width of main lobe1702.

FIG. 18Aillustrates multi-finger asymmetrical beamforming for beam tracking when a UE is stationary according to some aspects.FIG. 18Billustrates multi-finger asymmetrical beamforming for beam tracking when a user equipment (UE) is mobile according to some aspects. In order to track the channel, the UE processing circuitry (e.g., baseband processor110, (FIG. 1)) switches the beamforming vector back and forth between the patterns as shown inFIGS. 18A and 18B. The UE processing circuitry can change the beam at the beginning of each frame such that the UE can estimate the channel with the switched beamforming pattern.

In the non-mobile (stationary) situation illustrated inFIG. 18A, the angle of arrival1800of the received signal will remain the same. The beams1802and1804are designed to have similar beamforming gain, and the UE will not observe any change in the channel gain. Therefore, the UE can continue communication without disruption using the same (current) beam direction.

In the high-mobility situation illustrated inFIG. 18B, when angle of arrival1806of the received signal changes quickly, the UE will observe two different channel gains. If the beamforming pattern of the secondary lobe is in the direction of new angle of arrival, the received signal power will be larger as compared to other beamforming pattern. For example, as illustrated, if the beamforming pattern of the secondary lobe1808is in the direction of the new angle of arrival1810, the received signal power of beamforming pattern1812will be larger as compared to other beamforming pattern1814. Then, the UE steers its beam1816towards the direction of secondary beam1808of the beam pattern1812that has highest channel gain as shown inFIG. 18B.

FIG. 19illustrates a uniform linear antenna array1900according to some aspects. While a linear antenna array1900is depicted, other array types (e.g., rectangular) can be used. Antenna elements1902can be spaced by an amount1904given by d=λ/2 where λ is wavelength of carrier frequency.

The beamforming vector can be designed as described below.

The far field radiation pattern at azimuth angle θ is given by
d(θ)=aH(θ)w(16)
wherea(θ)=[1,ej(π cos(θ), . . . ,ej((N-1)cos(θ))]T(17)

An antenna radiation pattern function ƒ(θ) can also be defined wherein 0≤θ≤180°.

Next, defining the main lobe angle and secondary lobe angle as θl,1and θl,2, respectively, a set of angles can be defined to apply an upper bound on side lobes:
θp,i,i=1, . . . ,L(18)

The desired radiation pattern for azimuth angles θl,1and θl,2can be given as d1=d(θl,1) and d2=d(θl,2), respectively.

Next, a least square minimization problem for the azimuth angles θl,i, i=1, . . . , K can be given as:

Note that the above problem in (19) is an NP hard problem. The solution of the optimization problem (19) provides a multi-finger beamforming vector w that generates desired main and secondary lobes and reduced side lobes.

FIG. 20illustrates direction of an optimized beam forming vector according to some aspects. Although the above optimization problem is flexible to generate beams in any direction, methods and apparatuses according to aspects will generate a single optimized beam forming vector woptthat has main lobe at the broadside angle, i.e., 0° as shown inFIG. 20.

Aspects also provide a DFT matrix as a beam steering codebook. A DFT matrix can be given as follows:

akT=[1,ej⁢2⁢⁢πkNO,…⁢,ej⁢2⁢⁢π⁡(N-1)⁢kNO]
Here, DFT codebook index k corresponding to desired steering angle θ is given by k=

⌊NO2⁢cos⁡(θ)⌋
where └⋅┘ is an operator to find closest integer.

Assuming that the UE processing initially knows the best beamforming direction and DFT codeword index k*, UE processing circuitry can then obtain steered beamforming vectors by multiplying woptby ak*elementwise as follows
s1=woptdiag(ak*)  (21)
s2=woptdiag(ak*)  (22)
where (.)His conjugate operation and diag(.) is diagonalization of the beamforming vector.

Given received signal by r, UE processing circuitry can check the following conditions: First, if received signal strength after beamforming vector s1is larger than s2, according to (23), then the DFT codebook index is increased by 1 (k*←k*+1) to steer the beam towards direction of secondary beam of s1. In (21), ∈ is a threshold to prevent frequent beam switching.
∥s1Tr∥22>∥s2Tr∥22+∈  (23)

Second, if received signal strength after beamforming vector s2is larger than s1according to (24),
∥s2Tr∥22>∥s1Tr∥22+∈  (24)

Then, we decrease DFT codebook index by 1 (k*←k*−1) to steer the beam towards the direction of secondary beam of s2.

Otherwise, if neither the first nor the second condition holds, the UE processing circuitry keeps the beamforming index k* the same.

By implementing beamforming as described above with reference to Equations (15)-(19), and then beam steering in the direction of the strongest received signal strength, the UE processing circuitry can maintain communications even during high-mobility situations such as in vehicular applications.

FIG. 21illustrates a method2100for bream tracking using a multi-finger beam according to some aspects. The method2100can be performed by UE processing circuitry (e.g. baseband processor110(FIG. 1)).

The method2100begins with operation2102with the processing circuitry performing a beamforming function at a first subframe of a first frame, using a multi-finger beam forming vector to generate a first multi-finger beamforming pattern. The first multi-finger beamforming pattern can include a main beam and a first secondary beam. In aspects, the first secondary beam has lower beamforming gain than the main beam.

The method2100continues with operation2104with the processing circuitry performing the beamforming function at a first subframe of a second frame subsequent to the first frame, using a multi-finger beam forming vector to generate a second multi-finger beamforming pattern. The second multi-finger beamforming pattern can include the same main beam from operation2102and a different secondary beam. In aspects, the first secondary beam is at a first azimuthal angle from the main beam and the second secondary beam is at a second azimuthal angle from the main beam symmetrical to the first secondary beam about an axis going through the main beam. In aspects, the processing circuitry is configured to determine the azimuthal angles according to a least square minimization problem as described earlier herein at least with reference to Equations (16)-(19).

The method2100continues with operation2106with the processing circuitry changing azimuthal angle of the main beam in subsequent frames responsive to detecting a change in received power between the first frame and the second frame. In aspects, the azimuthal angle of the main beam is changed to correspond to a direction of either of the first secondary beam or the second secondary beam, depending on whether the processing circuitry detected higher gain in the corresponding first frame or second frame. In aspects, the azimuthal angle is changed by incrementing or decrementing an index of a DFT codebook as described above with reference to Equations (20)-(23).

Blind Beam Tracking for Multiple Beams in 5G mmWave for Improved SNR and Interference Mitigation

Beam tracking algorithms are used in current systems to acquire beams. Some beam tracking algorithms include blind tracking algorithms in high-speed (e.g., vehicular) applications. However, such blind tracking algorithms are currently limited to the ability to track one beam at a time. It would be helpful to be able to track two or more beams quickly, to use the two or more beams for improved signal to noise ratio (SNR). Further, multiple beam tracking can improve beam acquisition in the presence of a strong interferer by allowing UEs to track the interferer in parallel and remove interferer transmit power. Finally, multiple beam tracking is useful in a multi-use MIMO setting on the base station side to help base stations track multiple users.

Methods and apparatuses according to aspects can reduce hardware complexity by reducing the number of FFTs at the receiver. The algorithms provided according to some aspects can scale to multiple users through multiple parallel tracking chains, one for each user. Algorithms according to aspects can track the strongest beam, determine the weights corresponding to the strongest beam, project the received signal in the orthogonal direction corresponding to the strongest beam, and repeat the process to track multiple parallel beams in an order according to received signal power.

Multiple beams can be tracked in high mobility situations, even when angle of arrival changes frequently. The tracking capability is a function of sampling frequency, meaning that for faster tracking, higher sampling frequency can still be used to track accurately, regardless of signal bandwidth or signal properties and without timing or frequency synchronization.

Blind algorithms can also track in the presence of interference because the interfering beam can be tracked. This is because blind algorithms operate in the time domain and are agnostic to the signal, and do not depend on pilots. By projecting on the orthogonal direction, blind tracking algorithms minimize interference.

Assume a fully digital mmWave architecture, where apparatuses and methods according to aspects can access the signals after ADC at the output of each RF chain for every antenna. A simple flat fading scenario wherein the signal received at the k-th antenna is given as follows:
yk(t)=hkx(t)+n(t)  (25)
where yk(t) is the signal received at the k-th antenna.

In vector form (25) can be written as
y(t)=hx(t)+n(t)  (26)
where channel matrixh=ΣcΣmgcma(θm)  (27)
a(θ)=[1ejπ sin θ. . . ej(K-1)π sin θ]  (28)
and where gcmis the complex gain of the m-th element in the c-th cluster, c is the number of clusters, m is the number of angles in a cluster, and θmis the angle of the different reflections.

Assume a blind algorithm that provides the weights wk* to track a single beam, where zk(t) is a single output signal.
zk(t)=wk*yk(t)=wk*hkx(t)+wk*n(t)  (29)

The weights are determined by the algorithm that maximizes the output power:

An example of such an algorithm is using an Equal Gain Combining technique that maximizes the output power, where μ is a learning rate:
wk=ejθk(31)
θk=θk−μ Im{zi(t)zk*(t)}  (32)

Because the above blind technique has no knowledge of the channel, it is not known how many clusters exist. Given this degree of freedom, the blind technique will converge in a way to maximize combined output power. In other words, θkwill converge to the beam in the strongest direction. For example, assuming multiple clusters with one cluster having significantly higher power than the others, then the blind algorithm described at Equation (29) is likely to converge to the main (maximum combined power) cluster. This can be useful for tracking one beam, but if there are multiple reflections and multiple beams, tracking can become difficult or unattainable for those other reflections/beams.

To build the second (lower-power) beam for the second cluster (e.g., to discover θ2for a next-strongest beam subsequent to having discovered θ1for the strongest beam), methods according to aspects will remove the cluster effect of the first cluster before re-converging is performed. Without removing the first cluster effect, attempts to track the second beam will instead converge on a degenerated version of the first beam, rather than on the actual second beam. To remove the cluster effect of the first cluster, it is first assumed that the first beam (corresponding to highest power) has converged such that θ has been obtained as the angle of the first beam. Then, algorithms according to aspects use the first beam weight vector to suppress energy from the first beam, leaving the residual energy for the rest of the beams. Next, algorithms according to aspects can then re-apply the blind technique to find the second cluster. The suppression can be achieved by projecting the signal on to the orthogonal space to the original beam direction. Convergence speed can be increased by properly initializing the M multiple beams.

An algorithm for multiple beam tracking, according to some aspects, can first initialize M beams in M different directions (with a small correlation between beams or orthogonal beams) such that:
wm≠wlform≠l(33)

Further denote Sm⊥as the orthogonal complement subspace of Sm.

The overall received signal y(t) can be decomposed into two orthogonal components: one component lying in Subspace Smand the other component in Sm⊥
y(t)=PSmy(t)+PSm⊥y(t)  (35)
where
PSm=Wm(WmHWm)−1WmH(36)
is a projection matrix onto subspace Sm
PSm⊥=I−PSm(37)
is a projection matrix onto subspace Sm⊥.

wmis updated based on {tilde over (y)}m(t) and given that wm,k=ejθm,k=k-th element of wm.

To update wm, systems and methods according to aspects can use a single beam tracking blind algorithm:
θm,k=θm,k+μ Im{zm,k(t)rm*(t)}  (38)
where

Next systems and methods according to aspects update all the projection matrices PSm⊥.

Example projection matrices for two beams can be given as:

The above processing can then be repeated for a third beam, or until no more beams are detected. Processing can be limited to a certain number of beams, or to detection of a beam with a power threshold, for example.

FIG. 22illustrates an architecture2200for blind beam tracking of multiple beams according to some aspects. Some elements of architecture2200can be implemented by processing circuitry (e.g., baseband processor110(FIG. 1)). Signals are received at2202from k antennas and provided to ADC2204, which generates signal y(t) at2206. Processing circuitry then generates projection matrices similarly to Equation (35) above, at blocks2206and2208. Up to M projection matrices may be generated.

Next the processing circuitry applies M projection matrices to signal y(t) to generate up to M {tilde over (y)}m(t) signals. Next, at blocks2210and2212, weights matrices are updated using, for example, single beam tracking blind algorithm of Equation (38). Each individual beam that has been tracked is then provided at FFTs2214and2216for further processing.

FIG. 23illustrates a block diagram of an example machine2300upon which any one or more of the techniques (e.g., methodologies) discussed herein may be performed, for example, any of a beam sweeping and beam tracking operation.

The machine (e.g., computer system)2300may include a hardware processor2302(e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory2304, a static memory (e.g., memory or storage for firmware, microcode, a basic-input-output (BIOS), unified extensible firmware interface (UEFI), etc.)2306, and mass storage2308(e.g., hard drive, tape drive, flash storage, or other block devices) some or all of which may communicate with each other via an interlink (e.g., bus)2330. The machine2300may further include a display unit2310, an alphanumeric input device2312(e.g., a keyboard), and a user interface (UI) navigation device2314(e.g., a mouse). In an example, the display unit2310, input device2312and UI navigation device2314may be a touch screen display. The machine2300may additionally include a storage device (e.g., drive unit)2308, a signal generation device2318(e.g., a speaker), a network interface device2320, and one or more sensors2316, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine2300may include an output controller2328, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

Registers of the processor2302, the main memory2304, the static memory2306, or the mass storage2308may be, or include, a machine readable medium2322on which is stored one or more sets of data structures or instructions2324(e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions2324may also reside, completely or at least partially, within any of registers of the processor2302, the main memory2304, the static memory2306, or the mass storage2308during execution thereof by the machine2300. In an example, one or any combination of the hardware processor2302, the main memory2304, the static memory2306, or the mass storage2308may constitute the machine readable media2322. While the machine readable medium2322is illustrated as a single medium, the term “machine readable medium” may include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) configured to store the one or more instructions2324.

EXAMPLES

Example 1 is an apparatus for a wireless communication device, comprising: an antenna array including Nrantennas and

NrNrrf
antenna sub-arrays, where Nrrfis the number of RF-chains of the apparatus; and processing circuitry configured to perform a beamforming function at the

NrNrrf
antenna sub-arrays; determine the angle of arrival of a received signal received in response to performing the beamforming function; and adjust phase shifters of the apparatus according to the angle of arrival.

Example 2 can include the subject matter for Example 1, wherein the angle of arrival is determined by: steering each sub-array toward each of

NrNrrf⁢2⁢dλ
grating angles, where d is the distance between each sub-array and λ is the wavelength of the received signal; and selecting the grating angle having the largest measured power gain as the angle of arrival.

Example 3 can include the subject matter for Examples 1-2, wherein the steering is performed using a discrete Fourier transform (DFT) codebook.

Example 4 can include the subject matter for Examples 1-3, wherein the DFT codebook has a size of

Example 5 can include the subject matter for Examples 1-4, wherein the beamforming function is performed using beamforming vector that has been applied to each antenna sub-array of the

NrNrrf
sub-arrays such that an array pattern of each antenna sub-array is substantially the same.

Example 6 is an apparatus of a wireless communication device comprising an antenna array; and processing circuitry coupled to the antenna array and configured to: perform a beamforming function at a first subframe of a first frame, using a multi-finger beam forming vector to generate a first multi-finger beamforming pattern, the first multi-finger beamforming pattern including a main beam and a first secondary beam; perform the beamforming function at a first subframe of a second frame subsequent to the first frame, using a multi-finger beam forming vector to generate a second multi-finger beamforming pattern, the second multi-finger beamforming pattern including the main beam and a second secondary beam; and change azimuthal angle of the main beam in subsequent frames responsive to detecting a change in received power between the first frame and the second frame.

Example 7 can include the subject matter of Example 6, wherein the first secondary beam has lower beamforming gain than the main beam.

Example 8 can include the subject matter of Examples 6-7, wherein the first secondary beam being at a first azimuthal angle from the main beam and wherein the second secondary beam is at a second azimuthal angle from the main beam symmetrical to the first secondary beam about an axis going through the main beam.

Example 9 can include the subject matter of Examples 6-8, wherein the azimuthal angle of the main beam is changed to correspond to a direction of either of the first secondary beam or the second secondary beam.

Example 10 can include the subject matter of Examples 6-9, wherein the azimuthal angle of the main beam is changed to correspond to a beam direction during the frame at which the apparatus detected highest channel gain.

Example 11 can include the subject matter of Examples 1-10, wherein the azimuthal angle is changed to correspond to a beam direction of a corresponding secondary beam during the frame at which the apparatus detected highest channel gain.

Example 12 can include the subject matter of Examples 1-11, wherein the azimuthal angle is changed by incrementing or decrementing an index of a discrete Fourier transform (DFT) codebook.

Example 13 can include the subject matter of Examples 1-12, wherein the processing circuitry is configured to determine the azimuthal angle of the main beam according to a least square minimization problem.

Example 14 is an apparatus of a wireless communication device, comprising: an antenna array configured to receive a signal including a plurality of beams; and processing circuitry coupled to the antenna array and configured to detect a first beam of the plurality of beams received at the antenna array; suppress energy from the first beam within the received signal based on a weight vector corresponding to the first beam; and detect a second beam within the received signal subsequent to having suppressed energy from the first beam within the received signal.

Example 15 includes the subject matter of Example 14, wherein the processing circuitry is further configured to: suppress energy from the second beam within the received signal based on a weight vector corresponding to the second beam; and detect a third beam within the received signal subsequent to having suppressed energy from the second beam within the received signal.

Example 16 includes the subject matter of Examples 14-15, wherein the processing circuitry suppresses energy from the first beam by projecting the received signal onto a space orthogonal to a direction of the first beam.

Example 17 includes the subject matter of Examples 14-16, wherein the processing circuitry detects the first beam and the second beam using a blind algorithm and in the absence of a pilot signal.

Example 18 includes the subject matter of Examples 14-17 wherein the blind algorithm includes an Equal Gain Combining technique to maximize output power.

Example 19 can include methods for performing operations described in any of Examples 1-18.

Example 20 can include a system having means for performing operations described in any of Examples 1-18.

Example 21 can include computer-readable media including instructions for performing operations described in any of Examples 1-18.

Although an aspect has been described with reference to specific example aspects, it will be evident that various modifications and changes may be made to these aspects without departing from the broader spirit and scope of the present disclosure. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. The accompanying drawings that form a part hereof show, by way of illustration, and not of limitation, specific aspects in which the subject matter may be practiced. The aspects illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other aspects may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of this disclosure. This Detailed Description, therefore, is not to be taken in a limiting sense, and the scope of various aspects is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.

Such aspects of the inventive subject matter may be referred to herein, individually and/or collectively, by the term “aspect” merely for convenience and without intending to voluntarily limit the scope of this application to any single aspect or inventive concept if more than one is in fact disclosed. Thus, although specific aspects have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific aspects shown. This disclosure is intended to cover any and all adaptations or variations of various aspects. Combinations of the above aspects, and other aspects not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description.

The following describes various examples of methods, machine-readable media, and systems (e.g., machines, devices, or other apparatus) discussed herein.