Nonvolatile semiconductor memory device and method for manufacturing same

Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based on and claims the benefit of priority from prior Japanese Patent Application No. 2011-40918, filed on Feb. 25, 2011, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a nonvolatile semiconductor memory device and a method for manufacturing the same.

BACKGROUND

Description of the Related Art

NAND type flash memories are known as electrically rewritable and highly integrable nonvolatile semiconductor memory devices. Memory transistors of conventional NAND type flash memories have a stacked-gate structure in which a charge accumulation layer (floating gate) and a control gate are stacked via an insulation film. A NAND cell unit is configured by a plurality of memory transistors connected in series in a column direction with adjoining ones sharing their source and drain, and select gate transistors provided at the ends of the column of memory transistors. One end of the NAND cell unit is connected to a bit line, and the other end thereof is connected to a source line. A memory cell array is configured by NAND cell units arranged in a matrix. NAND cell units arranged in a row direction are referred to as a NAND cell block. The gates of select gate transistors arranged in the same row are connected to the same select gate line, and the control gates of memory transistors arranged in the same row constitute a word line. When N memory transistors are connected in series in a NAND cell unit, the number of word lines included in one NAND cell block is N.

Miniaturization of the NAND type flash memories has reduced the gate length and the interval between adjoining transistors, which has brought about various problems described below. For example, these problems are (a) reduction in drain current controllability based on an electric field of the control gate due to increase in parasitic capacitance between adjoining gates, etc., short channel effect (SCE), etc., (b) increase in an interference effect between adjoining gates, (c) increase in a leak current between adjoining electrodes, (d) leaning or collapsing of patterns during fabrication of the gates because of an increasing aspect ratio of the gate electrodes, (e) deterioration of data retention characteristics due to a significant reduction in the number of electrons that can be accumulated in the charge accumulation layer (the number of electrons per bit), etc. Hence, conventional NAND type flash memories have almost reached the physical limit of miniaturization, with a significantly narrowed writing/erasing window of the memory cells.

“Three-dimensionally stacked” memories, in which memory cell transistors are stacked sterically to form many layers, are considered to be the main method for future integration. Specifically, a structure in which nitride film trap type (SONOS, MONOS) cells are stacked is proposed in many papers, etc. The nitride film trap type cell structure has a merit in that it can be manufactured (stacked) easily, but its major problem is that its erasing characteristic and data retention characteristic are poorer than those of the floating gate type cell because of its nature of trapping electrons in the nitride film.

On the other hand, the conventional floating gate type memory cell structure for accumulating charges in the floating gate electrode is difficult to manufacture and stack, because it has an EB (Etch Back) structure in which a control gate electrode and an IPD film (Inter-Poly-Dielectric film or inter-gate insulating film) are provided not only over the upper surface of the floating gate electrode but also over the side surfaces thereof for securing a drive power (coupling ratio) of the control gate electrode. Further, according to one method for increasing the coupling ratio in order to widen the writing/erasing window of the memory cells, it is necessary to increase the thickness of the floating gate electrode. However, if the thickness of the floating gate electrode is increased in the EB structure in which the IPD film and the control gate electrode are stacked above the floating gate electrode, the word line is consequently raised upward and the aspect ratio is increased, exposing the problem (d) described above. Therefore, it is not easy to improve the coupling ratio.

Hence, as a cell structure for securing coupling ratio without extreme difficulty of manufacture, other than the stacked gate structure, the following structure has already been proposed. That is, in this structure, each control gate electrode is embedded between floating gates via an inter-gate insulating film such that the control gate electrode extends along the word line direction. This structure secures the coupling ratio by raising the potential of a writing target cell through the control gate electrodes on both sides of the target cell.

However, as for these memory cells, simply stacking them means a simple increase in the number of manufacturing steps, and it is hence difficult to reduce the bit cost while ensuring an increase in the cell capacity that is balanced with the cost increase. Simple stacking is effective only by a bit cost shrink ratio=1/the number of stacked layers, i.e., the division by the number of layers, which means that the shrink ratio is small when the number of layers is large, leading to a high bit cost. Therefore, in the cell structure seeking a shrink by stacking, an object from a practical standpoint is to restrict the number of steps and the cost.

DETAILED DESCRIPTION

A nonvolatile semiconductor memory device according to an embodiment includes a first memory cell array layer, a first insulating layer formed above the first memory cell array layer, and a second memory cell array layer formed above the first insulating layer. The first memory cell array layer includes first NAND cell units each including a plurality of first memory cells connected in series in a first direction. The first memory cell includes a first semiconductor layer, a first gate insulating film formed above the first semiconductor layer, and a first charge accumulation layer formed above the first gate insulating film. The second memory cell array layer includes second NAND cell units each including a plurality of second memory cells connected in series in the first direction. The second memory cell includes a second charge accumulation layer, a second gate insulating film formed above the second charge accumulation layer, and a second semiconductor layer formed above the second gate insulating film. Control gate are formed on the first-direction both sides of the first and second charge accumulation layers which are positioned the latter above the former via the first insulating layer, with an inter-gate insulating film provided between the control gate and the charge accumulation layers. The control gates extend in a second direction perpendicular to the first direction.

The embodiment will now be explained with reference to the attached drawings.

[Basic Memory Cell Array Structure]

Before a first embodiment will be explained, a memory cell structure of a NAND type flash memory which forms the basis of the nonvolatile semiconductor memory device according to the present embodiment will be explained.

As a cell structure for securing coupling between a floating gate (charge accumulation layer) and a control gate, the present embodiment has not the stacked-gate structure but a gate structure in which control gates are embedded at both sides of a floating gate to let the floating gate couple with the control gates on both sides thereof.

FIG. 43is a diagram showing the structure of a memory cell array1of a NAND type flash memory according to a comparative example which employs this structure.FIG. 44is a circuit diagram of this memory cell array1.

A memory cell array50includes a plurality of NAND cell units NU each including: a NAND string configured by M number of electrically-rewritable nonvolatile memory cells MC0to MCM-1connected in series; and select gate transistors S1and S2connected to both ends of the NAND string. One end of the NAND cell unit NU (that is on the select gate transistor S1side) is connected to a bit line BL, and the other end thereof (that is on the select gate transistor S2side) is connected to a common source line CELSRC. The gate electrodes of the select gate transistors S1and S2are connected to select gate lines SGD and SGS. The control gate electrodes provided on both sides of the memory cells MC0to MCM-1are connected to word lines WL0to WLMrespectively. The bit lines BL are connected to a sense amplifier circuit60, and the word lines WL0to WLMand the select gate lines SGD and SGS are connected to a row decoder circuit70.

n type diffusion layers52to function as sources and drains of MOSFETs constituting the memory cells MC are formed in a p-type well51formed in a substrate. Floating gates (FG)54are formed above the well51via a gate insulating film53functioning as a tunnel insulating film. The floating gates54function as charge accumulation layers. Control gates (CG)56are formed on both sides of the floating electrodes54via an inter-gate insulating film (IPD)55. The control gates56constitute the word lines WL. The select gate transistors S1and S2have select gates57above the well51via the gate insulating film53. The select gates57constitute the select gate lines SGS and SGD. The memory cells MC and the select gate transistors S1and S2are NAND-connected such that adjoining ones share their drain and source.

In the case of 1 bit/cell where data of 1 bit is stored in one memory cell MC, data of 1 page is stored in the memory cells MC formed along a pair of word lines WL perpendicular to a NAND cell unit NU. In the case of 2 bits/cell where data of 2 bits is stored in one memory cell MC, data of 2 pages (an upper page UPPER and a lower page LOWER) is stored in the memory cells MC formed along a word line WL.

One block BLK includes a plurality of NAND cell units NU that share word lines WL. One block BLK forms a unit of data erasing operation. In one memory cell array1, the number of word lines WL in one block BLK is M+1, and the number of pages in one block is M×2=128 pages in the case of two bits/cell (in case of M=64).

When writing data into a writing target memory cell MC, the voltage of the control gates56on both sides of the floating gate54is raised to a certain writing voltage, and other control gates56in the NAND cell unit NU are set to alternate low and high voltages which decrease toward both ends of the NAND cell unit NU, to thereby prevent non-selected memory cells from being written erroneously.

First Embodiment

[Memory Cell Array Structure According to Fist Embodiment]

Next, the memory cell array structure according to the first embodiment will be explained.

FIG. 1is a perspective diagram of the memory cell array structure according to the first embodiment.FIG. 2is a cross-sectional diagram ofFIG. 1seen from the GC (gate) direction.FIG. 3are cross-sectional diagrams ofFIG. 2taken along lines A-A′, B-B′, and C-C′ and seen from the AA (active area) direction ofFIG. 1. Note that the drawings are illustrated with some components omitted, in order to make the internal structure visible.

In this memory cell array structure, memory cell arrays shown inFIG. 43are stacked head-to-head, and control gates are shared by these upper and lower memory cell array layers.

That is, as shown inFIG. 1, a lower first semiconductor layer11and an upper second semiconductor layer21to constitute bodies to form channels are provided above an insulating base30, and between them, a first floating gate13(charge accumulation layer) to face the upper surface of the first semiconductor layer11via a first tunnel insulating film (first gate insulating film)12and a second floating gate (charge accumulation layer)23to face the lower surface of the second semiconductor layer21via a second tunnel insulating film (second gate insulating film)22are stacked the latter above the former via a first insulating layer31. As is clear from the A-A′ cross section ofFIG. 3A, the semiconductor layers11or21, the tunnel insulating films12or22, and the floating gates13or23are insulated and isolated from each other in the GC direction (second direction) via element isolating insulating films15or25extending in the AA direction (first direction).

A plurality of stacks of floating gates13and23are formed at certain intervals in the AA direction along the semiconductor layers11and21so as to form a NAND array. Control gates33extending in the GC direction are formed on AA-direction both sides of each stack of floating gates13and23via an inter-gate insulating film (IPD: Inter-Poly Dielectric film)32. The control gate33is provided commonly for the lower and upper floating gates13and23so as to couple with these floating gates13and23from their side. A mask material33mis provided between the control gate33and the second tunnel insulating film22. The lower first semiconductor layer11, the first tunnel insulating film12, the first floating gate13, the inter-gate insulating film32, and the control gates33are included in the configuration of a lower first memory cell MC1. The upper second semiconductor layer21, the second tunnel insulating film22, the second floating gate23, the inter-gate insulating film32, and the control gates33are included in the configuration of an upper second memory cell MC2.

First select gates16and second select gates26to form select gate transistors S11and S12, and S21and S22are provided at positions adjoining the control gates33which are located at both ends of the arrangement of stacks of floating gates13and23. The select gates16and26are stacked the latter above the former via the first insulating layer31, and face the semiconductor layers11and21via the tunnel insulating films12and22respectively. First select gate lines17extending in the GC direction are embedded in the first select gates16, and second select gate lines27and mask materials27mextending in the GC direction are embedded in the second select gates26. The select gate line17and the select gate line27are insulated and isolated from each other via a second insulating layer34.

A lower first NAND cell unit NU1includes lower NAND-connected memory cells MC1and the select gate transistors S11and S21, and a first memory cell array layer10includes a plurality of NAND cell units NU1which are arranged in the GC direction. An upper second NAND cell unit NU2includes the upper NAND-connected memory cells MC2and the select gate transistors S12and S22, and a second memory cell array layer20includes a plurality of NAND cell units NU2which are arranged in the GC direction.

A bit line contact35shared between the NAND cell units NU1and NU2and extending vertically to connect to an unillustrated bit line is formed in the semiconductor layers11and21at one end of the NAND cell units NU1and NU2. A source line contact36shared between the NAND cell units NU1and NU2and extending vertically to connect to an unillustrated source line is formed in the semiconductor layers11and21at the other end of the NAND cell units NU1and NU2. A word line contact37is formed at an end of the control gate33, and a select gate line contact38is formed at an end of the select gate lines17and27.

According to the above configuration, the floating gates23of vertically corresponding memory cells MC1and MC2of the lower and upper NAND cell units NU1and NU2are simultaneously driven by coupling with the word lines WL on both sides to be connected to a common bit line, as their equivalent circuit is shown inFIG. 4. In contrast, the select gate transistors S11to S22are provided independently for the lower and upper bit lines, and can selectively activate the NAND cell unit NU1or NU2by either one being selected.

As can be understood from the above, the present embodiment employs a method for executing writing by raising the potential of the floating gates13and23through the control gates33on both sides of the floating gates13and23, and hence does not have such an EB (Etch Back) structure as that of the floating gate type cells of the comparative example that is difficult to manufacture. Therefore, the present embodiment is less difficult to manufacture, and thus realizes a cell structure that is suitable for stacking.

When a higher coupling ratio is needed to widen the writing/erasing window of the memory cells MC, it is necessary to increase the thickness of the floating gate. According to the present embodiment, the control gates33are provided on both sides of the floating gates13and23via the inter-gate insulating film32, and the floating gate and the control gate are not provided in a stacked structure. Therefore, thickening of the floating gate is easy, and the coupling ratio can be increased while the word lines are maintained at a low aspect. This is advantageous for the problem of pattern leaning and collapsing, etc. during fabrication of the gates. As regards the bit cost problem too, because the word lines for the upper cells and lower cells can be manufactured simultaneously as will be shown in the following manufacturing flow, it is possible to reduce the number of steps and to reduce critical lithography steps of which unit process price is high, making it possible to restrict the bit cost. Hence, the structure proposed here is advantageous for the various problems of stacking.

[Method for Manufacturing Memory Cell Array Structure according to First Embodiment]

Next, a method for manufacturing the memory cell array according to the present embodiment will be explained.

First, there are some conceivable variations regarding the formation of a peripheral circuit region. When the formation is on a bulk silicon substrate, it is necessary to form the peripheral circuits first. At this time, it is also possible to simultaneously form the memory cell arrays according to the present embodiment on the bulk silicon substrate. In the present embodiment, the NAND cell units NU1and NU2are provided sterically. Hence, an example of forming NAND cell units NU1and NU2above a silicon substrate will be explained. The method for forming peripheral circuit transistors is the same as an ordinary method. That is, first, a channel is formed above a silicon substrate. Then, gate oxide films (both a Low Voltage oxide film and a High Voltage oxide film) are formed above the silicon substrate. Then, after a gate electrode and a mask material for AA (active area) formation are stacked, an STI trench is formed. Then, after the STI trench is filled, a mask material for GC (gate) formation is stacked, GC electrodes are formed, and a side wall insulating film is formed. After this, a source/drain diffusion layer is formed, an inter-GC insulating film is embedded, and the surface is planarized.

After the peripheral circuits are formed, the memory cell array according to the present embodiment is formed as their overlying layer.FIG. 5toFIG. 20are diagrams showing the method for manufacturing the memory cell array according to the present embodiment.

First, as shown inFIG. 5, an insulating layer30A made of SiO2is formed above an unillustrated silicon substrate, and above them, a first semiconductor layer11A made of polysilicon, a first tunnel insulating film (gate insulating film)12A made of SiO2, and a first floating gate forming layer13A made of polysilicon are stacked sequentially. The first semiconductor layer11A to become a channel (body) is basically made of polysilicon, but may be made of monocrystal silicon. In the present embodiment, by using polysilicon for the channel (body) so as to form an SOI structure, it becomes unnecessary to form an STI in the silicon substrate, which realizes a cell structure that is more suitable for stacking. Since formation of the tunnel insulating film12A is carried out above the semiconductor layer11A made of polysilicon, it is done by using not a thermally-oxidized film, but a CVD (Chemical Vapor Deposition) or an ALD (Atomic Layer Deposition) oxide film. Note that although the first semiconductor layer11A is provided by film formation as described above, it may instead be a silicon substrate as it is.

After the layers up to the first floating gate forming layer13A are formed, mask materials41and42for AA pattern formation made of, e.g., SiN and SiO2are patterned onto the first floating gate forming layer13A. RIE (Reactive Ion Etching) using the mask materials41and42is carried out to selectively etch the stack of layers to the bottom of the insulating layer30A to form first trenches to thereby form the AA pattern as shown inFIG. 6. As a result, a first floating gate forming layer13B, a first gate insulating film12, a first semiconductor layer11, and an insulating layer30are formed.

Next, as shown inFIG. 7, the trenches formed by the AA pattern formation are filled with a first element isolating insulating layer15made of SiO2, and then planarization is carried out by CMP (Chemical Mechanical Polishing) using the polysilicon forming the first floating gate forming layer13B as the stopper. Then, the upper surface of the first element isolating insulating layer15is set back by etch back. Next, as shown inFIG. 8, a first insulating layer31for isolating the upper layer from the lower layer is formed above the first element isolating insulating layer15and the first floating gate forming layer13B, and a second floating gate forming layer23A made of polysilicon is formed above the first insulating layer31.

Then, as shown inFIG. 9, mask materials43and44for GC pattern formation made of, e.g., SiN and SiO2are patterned onto the second floating gate forming layer23A. Then, as shown inFIG. 10, the stack of layers is selectively etched to the top of the tunnel insulating film12by RIE using the mask materials43and44, to form second trenches and thereby form the GC pattern. As a result, a first floating gate13, a second floating gate forming layer23B, a first select gate forming layer16A, and a second select gate forming layer26A are formed. It is preferable that this GC pattern formation be carried out by an etching process having a high selectivity toward the tunnel insulating film12of the lower layer and that the first semiconductor layer11of the lower layer be not etched.

Then, as shown inFIG. 11, after an inter-gate insulating film (IPD)32made of SiO2is formed, the trenches of the GC pattern are filled with a control gate forming layer33A. The control gate forming layer33A may be made of polysilicon or metal (W, etc.)

Next, as shown inFIG. 12, the control gate forming layer33A is etched back by RIE to form control gates33. Then, as shown inFIG. 13, a mask material33mand an insulating layer39made of a CVD oxide film, a coated oxide film, or the like are embedded above the control gates33, and the uppermost surface is planarized by CMP using the mask43made of SiN as a stopper. After this, in order to form the select gate forming layers16A and26A and transistors of an unillustrated row decoder region, select gate trenches equivalent to EI (Etching Inter Poly) trenches are formed by RIE or the like. As a result, select gate trenches17A which reach down to the first select gate16through a second select gate forming layer26B and the first insulating layer31are formed as shown inFIG. 14.

Next, as shown inFIG. 15, in order to form select gate transistors S11to S22independently for lower cells and upper cells, a first select gate line17, a second insulating layer34, and a second select gate line27are sequentially formed in the select gate trenches17A by repeating embedding and etch back. The select gate lines17and27may be made of polysilicon or metal (W, etc.) like the control gate33. A cap insulating film39A is embedded in the etched-back portion of the second select gate line27, and the upper surface of the cap insulating film39A is planarized by CMP using the mask material43as a stopper.FIGS. 16A,16B, and16C are an A-A′ cross section, a B-B′ cross section, and a C-C′ cross section ofFIG. 15respectively.

Next, as shown inFIG. 17, planarization is carried out by CMP using the second floating gate forming layer23B or the control gate33as the stopper, and a second tunnel insulating film (gate insulating film)22A made of SiO2and a second semiconductor layer21A made of polysilicon are sequentially formed above the planarized surface.FIGS. 18A,18B, and18C are an A-A′ cross section, a B-B′ cross section, and a C-C′ cross section ofFIG. 17respectively.

Then, as shown inFIG. 19, in order to form AA pattern into the second semiconductor layer21A, the second tunnel insulating film22A, the second floating gate forming layer23B, and the second select gate forming layer26B of the upper layer, a mask material45for AA pattern formation made of SiN is patterned onto the second semiconductor layer21A, and RIE is carried out to form the AA pattern to thereby form third trenches. This AA pattern formation is carried out by an etching process having a high selectivity toward the mask materials27mand33m, and the control gate33and the select gate line27are not etched.FIGS. 20A,20B, and20C are an A-A′ cross section, a B-B′ cross section, and a C-C′ cross section ofFIG. 19respectively. Through this step, the second floating gate23is formed, and the second tunnel insulating film22and the second semiconductor layer21are formed self-aligned with the second floating gate23.

Then, a second element isolating insulating layer25(FIG. 3) is embedded in the trenches of the upper layer AA pattern. Finally, through-holes are formed in end portions of the semiconductor layers11and21, control gates33and select gate lines17and27to form contacts35to38and thereby complete two memory cell array layers10and20. The material of the contacts35to38may be polysilicon, metal (W, etc.), etc. which are used commonly.

According to this embodiment, since the AA pattern is formed in the lower layer first floating gate13and in the upper layer second floating gate23at different timings, the first floating gate13and the second floating gate23might be misaligned in the GC direction. However, this will not hinder the operation because they are different memory cells MC1and MC2.

In contrast, any misalignment between the first floating gate13and the channel of the first semiconductor layer11or between the second floating gate23and the channel of the second semiconductor layer21would greatly influence the operations of the memory cells MC1or MC2. In this regard, according to the memory cell array structure of the present embodiment, the first semiconductor layer11, the first tunnel insulating film12, and the first floating gate13of the lower layer are simultaneously subjected to AA pattern formation, and the second semiconductor layer21, the second tunnel insulating film22, and the second floating gate23of the upper layer are simultaneously subjected to AA pattern formation. Hence, it is possible to prevent misalignment between the memory cells MC1or MC2and the channel of the semiconductor layer11or21in each layer. Therefore, the memory cells MC1and MC2can operate without fault.

Furthermore, according to the present embodiment, it is possible to shorten the manufacturing process because the control gates33are shared between the lower and upper memory cells MC1and MC2, and the upper layer and the lower layer are simultaneously subjected to GC pattern formation.

Second Embodiment

[Memory Cell Array Structure According to Second Embodiment]

Next, a memory cell array structure according to the second embodiment will be explained.FIG. 21is a perspective diagram of the memory cell array structure according to the second embodiment.FIG. 22is a cross-sectional diagram ofFIG. 21seen from the GC direction.FIG. 23are cross-sectional diagrams ofFIG. 22taken along lines A-A′, B-B′, and C-C′ and seen from the AA direction ofFIG. 21.

The present embodiment is different from the first embodiment in that it comprises two-layered second floating gates23and29made of polysilicon as the upper layer floating gate (charge accumulation layer), and two-layered second select gates26and28made of polysilicon as the upper layer second select gate.

In the first embodiment, the upper surface of the second select gate line directly contacts the second tunnel insulating film22. Hence, a flat interface is hardly formed between the second select gate line27and the second tunnel insulating film22, and there might be produced dispersion between the characteristic of the lower select gate transistor S11or S21and that of the upper select gate transistor S12or S22.

According to the present embodiment, since the second select gate28made of polysilicon is interposed between the second select gate line27and the second tunnel insulating film22, it becomes easier to maintain the second tunnel insulating film22flat and to reduce dispersion between the characteristic of the lower select gate transistor S11or S21and that of the upper select gate transistor S12or S22.

[Method for Manufacturing Memory Cell Array Structure according to Second Embodiment]

Next, a method for manufacturing the memory cell array structure according to the present embodiment will be explained.

FIG. 24toFIG. 41are diagrams showing the method for manufacturing the memory cell array according to the present embodiment. The process of the present method up to the AA pattern formation is substantially the same as the steps ofFIG. 5toFIG. 7of the first embodiment. Hence, a detailed explanation will not be given about this process. The present embodiment is different from the first embodiment in that the select gate lines17and27of the select gate transistors S11to S12are formed before GG pattern formation.

Namely, once the process up to the AA pattern formation into the lower layer has been completed and the AA pattern trenches have been filled with the first element isolating insulating layer15, a first insulating layer31is formed as shown inFIG. 24, and RIE or the like is carried out to form trenches (EI trenches) at positions at which the select gate transistors S11to S22having a stacked structure are to be formed, to thereby form first select gate trenches17A as shown inFIG. 25.

Next, a conductor made of polysilicon or metal (W, etc.) to serve as first select gate lines17is embedded in the first select gate trenches17A and etched back to a position roughly corresponding to the lower surface of the first insulating layer31, and as shown inFIG. 26, a second insulating layer34made of SiO2is formed above the etched-back surface of the first select gate lines17, and a second floating gate forming layer23A made of polysilicon is formed thereabove. Here, the second floating gate forming layer23A is restricted to approximately 60 to 80% of the objective floating gate thickness, because the floating gate thickness is further increased in a later step.

Next, as shown inFIG. 27, RIE or the like is carried out to form trenches (EI trenches) in the second floating gate forming layer23A above the positions where the first select gate lines17are formed, to thereby form second select gate trenches27A. At this time, it is necessary that the second insulating layer34be present between the bottom of the second select gate trenches27A and the first select gate lines17.

Then, as shown inFIG. 28andFIG. 29, second select gate lines27are embedded in the second select gate trenches27A and etched back to the top of the floating gate forming layer23A, and a mask material27mis formed. A third floating gate forming layer29A made of polysilicon is formed above the floating gate forming layer23A. This makes the floating gates of the upper and lower layers substantially the same in thickness.

Next, as shown inFIG. 30, mask materials43and44for GC pattern formation made of SiN and SiO2are patterned onto the third floating gate forming layer29A. Then, as shown inFIG. 31, RIE is carried out by using the mask materials43and44to selectively etch the stack of layers to the top of the first tunnel insulating film12to form second trenches to thereby form the GC pattern. As a result, the first floating gate13, the second floating gate forming layer23B, the third floating gate forming layer29B, the first select gate forming layer16, and second select gate forming layers26B and28B are formed. It is preferred that this GC pattern formation be carried out by an etching process having a high selectivity toward the first tunnel insulating film12of the lower layer and that the semiconductor layer11of the lower layer be not etched.

Then, as shown inFIG. 32, after an inter-gate insulating film (IPD)32is formed, a control gate forming layer33A is embedded in the trenches of the GC pattern. Polysilicon or metal (W, etc.) can be used as the control gate forming layer33A.

Next, as shown inFIG. 33, the control gate forming layer33A is etched back by RIE to thereby form the control gate33. Then, as shown inFIG. 34, a mask material33mand an insulating layer39made of a CVD oxide film, a coated oxide film, or the like are embedded above the control gate33, and the upper surface is planarized by CMP using the mask43made of SiN as the stopper. Then, as shown inFIG. 35, planarization is carried out by CMP using the layers made of polysilicon (the third floating gate forming layer29B and the second select gate forming layer28B) as the stopper, and as shown inFIG. 36, a second gate insulating film22A made of SiO2and a second semiconductor layer21A made of polysilicon are sequentially formed above the planarized surface.FIGS. 37A,37B, and37C are an A-A′ cross section, a B-B′ cross section, and a C-C′ cross section ofFIG. 36respectively.

Then, as shown inFIG. 38, in order to form AA pattern into the second semiconductor layer21A, the second tunnel insulating film22A, the second floating gate forming layer23B, the third floating gate forming layer29B, and the second select gate forming layers26B and28B of the upper layer, a mask material45for AA pattern formation made of SiN is patterned onto the second semiconductor layer21A, and RIE is carried out to form the AA pattern to thereby form third trenches.FIGS. 39A,39B, and39C are an A-A′ cross section, a B-B′ cross section, and a C-C′ cross section ofFIG. 38respectively. Through this step, the second floating gates23and29are formed, and at the same time, the second tunnel insulating film22and the second semiconductor layer21are formed self-aligned with the second floating gates23and29.

Then, as shown inFIG. 40andFIG. 41, a second element isolating insulating layer25is embedded in the trenches (third trenches) of the upper layer AA pattern. Finally, through-holes are formed in end portions of the semiconductor layers11and22, control gates33, and select gate lines17and27to form contacts35to38, to thereby complete two memory cell array layers10and20. The material of the contacts35to38may be polysilicon and metal (W, etc.) that are used commonly.

According to the second embodiment, in addition to the effect achieved by the first embodiment, it becomes easier to maintain a flat interface between the second select gate28and the second tunnel insulating film22in the upper layer, and to give a uniform characteristic to the lower and upper select gate transistors S11and S12, and S21and S22because the second select gate28is interposed between the second select gate line27and the second tunnel insulating film22in the upper layer.

Third Embodiment

FIG. 42is a perspective diagram showing a memory cell array structure according to the third embodiment. Multilayer stacking is available by repeating the flow up to the contact formation, which is included in the above-described two-layer formation process. In the present embodiment, four memory cell array layers10A,20A,10B, and20B are stacked. Such multilayer interconnection is advantageous in that it can share the platform with a floating gate type NAND flash memory, because it can do with the three layers of bit lines, a source line, and global lines as with a single-layer floating gate type NAND flash memory, and needs no significant changes in the peripheral circuits. Note that the first semiconductor layer of the upper layer and the second semiconductor layer of the lower layer may be formed commonly.

Other Embodiments

The embodiments described above have a structure in which the control gate33is shared between the lower and upper memory cells MC1and MC2. Therefore, the manufacturing process becomes simple, and wiring can be simplified. However, it is also possible to divide the control gate33to lower and upper portions so as to enable the lower and upper memory cells MC1and MC2to be controlled independently. In this case, the control gate formation process may be carried out in the same manner as the select gate formation process described above.

In the first embodiment, the second select gate line27of the upper layer needs not be formed in one process, but instead, the select gate line27may be etched back rather deeply, and polysilicon may be added thereabove as in the second embodiment. In this way, it is possible to obtain the same effect as the second embodiment.

When forming a multilayer structure, it is possible to form the AA pattern and the GC pattern alternately into two layers at a time as in an order of first layer→(second layer+third layer)→(fourth layer+fifth layer) . . . as for the AA pattern, and (first layer+second layer)→(third layer+fourth layer)→(fifth layer+sixth layer) . . . as for the GC pattern. This would further shorten the manufacturing process.

Furthermore, another method for self-alignment between the floating gate and the channel is conceivable than the method described above. For example, when forming the AA pattern, the floating gate is etched together with a sacrifice film such as a nitride film formed above the floating gate. Then, after an oxide film is embedded in the formed trenches, the sacrifice film is removed by a hot phosphoric acid treatment. Then, a second tunnel insulating film22and a second semiconductor layer21are embedded where the sacrifice film has been, and the top surface is planarized by CMP or RIE. This method can also realize self-alignment between the floating gate and the channel.