Failsafe, ultra-wide voltage input output interface using low-voltage gate oxide transistors

A wide-voltage range, failsafe output interface module including a low-voltage, drain extended MOSFETs has been proposed to prevent the flow of reverse current during a failsafe operation while ensuring the MOSFETs are not subject to voltage over their voltage tolerance levels, improving reliability of an output interface module without resorting to more costly transistors with thicker films.

RELATED APPLICATIONS

This application claims priority to Indian Provisional Application No. 201841041540, filed Nov. 2, 2018, which is hereby incorporated by reference.

BACKGROUND

In integrated chip (IC) designs, hot-swapping refers to an ability of an IC interface to handle external interruptions, such as interruptions due to adding of a device to a bus on a fly. ICs supporting hot-swap require an output interface driving an output pin connected to a bus to be failsafe. In other words, the output interface shall not draw current from the output pin or the bus when a current or voltage supply to the output interface is down and the output pin is driven externally by another device connected to the bus.

ICs may employ low-voltage thin-film transistors with low voltage tolerance (e.g., 5V) for cost saving. These ICs are nonetheless expected to support legacy interfaces with high-voltage supplies (e.g., 10V). Other families of ICs, such as voltage supervisors, expect to its output interface to monitor and be driven by a wide-range high-voltage supply (e.g., 1.5V˜10V). Accordingly, there is a need for an IC interface design to withstand high-voltage applications and avoid voltage stress on its low-voltage thin-film transistors.

SUMMARY

An aspect of the present invention provides an output interface module including a pull-up circuitry coupled to a level shifter, which provides at least two different levels of turn-on voltage to the pull-up circuitry depending on a level of voltage supplied to the pull-up circuitry. The difference between the turn-on voltage and voltage supplied to the pull-up circuitry is regulated to avoid voltage stress on transistors included in the output interface module.

Yet another aspect of the present invention provides an output interface module including a pull-up circuitry coupled to a pull-down circuitry, which is coupled to an output pin of the output interface module. The pull-up circuitry incorporates a PMOS transistor and the pull-down circuitry incorporates a NMOS transistor. The PMOS transistor of the pull-up circuitry is coupled to the NMOS transistor of the pull-down circuitry in push-pull configuration to generate a data signal and output corresponding levels of voltage to the output pin. The PMOS transistor and NMOS transistor may comprise a drain extended transistor that can withstand higher voltage across its drain-gate, drain-source, and drain-bulk nodes, while maintaining a thin-film architecture.

DETAILED DESCRIPTION

In this description, the term “couple” or “couples” means either an indirect or direct wired or wireless connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. The recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, X may be a function of Y and any number of other factors.

Further, in the following detailed description, reference is made to certain examples of the present invention. These examples are described with sufficient detail to enable those skilled in the art to practice them. It is to be understood that other examples may be employed and that various structural, logical, and electrical changes may be made. Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

FIG. 1illustrates an exemplary IC output interface architecture. As illustrated, each of IC output interfaces, Interface A, Interface B, and Interface C, is coupled to processor101through multiple buses, Data, Address, and Control. Each of IC output interfaces, Interface A, Interface B, and Interface C, is driven by its respective voltage supply, VDD1, VDD2, and VDD3. On the right is a scaled illustration of IC output interface, Interface C.

Interface C comprises PMOS transistor MP101and NMOS transistor MN101coupled to each other to form a push-pull configuration driving pin PAD connected to one of buses Data, Address, and Control. The pin PAD is driven based on an incoming data signal with high and low values. When voltage supply VDD3is down and pin PAD is driven externally, body diode D101of PMOS transistor MP101is forward biased, creating reverse current path CP101from pin PAD to voltage supply VDD3. A failsafe operation prevents such forward bias to body diode D101of PMOS transistor MP101, preventing a reverse current and/or voltage flow.

FIG. 2illustrates an IC output interface architecture according to prior art to failsafe the output interface. In the prior art output interface ofFIG. 2, supplementary voltage comparison circuit210selects the higher of supply voltage VDDIO and voltage applied to pin PAD, and biases PMOS transistor MP201of output interface201at all times. During a normal operation of output interface201when voltage supply VDDIO supplies voltage to PMOS transistor MP201, the supplied voltage is output to pin PAD through a push-pull configuration of coupled PMOS transistor MP201and NMOS transistor MN201, and resistor R201. Because voltage supply VDDIO is on, PMOS transistor MP212of supplementary voltage comparison circuit210is turned off, and bulk PBULK of supplementary voltage comparison circuit210outputs the VDDIO's voltage supplied to supplementary voltage comparison circuit210to bulk PBULK of output interface201.

During a failsafe operation, when voltage supply VDDIO is off and pin PAD of output interface201is driven externally, PMOS transistor MP211of supplementary voltage comparison circuit210turned off and PMOS transistor MP212of supplementary voltage comparison circuit210is turned on. As a result, supplementary voltage comparison circuit210outputs voltage supplied via pin PAD to bulk PBULK of supplementary voltage comparison circuit210, which in turn is provided to bulk PBULK of output interface201. Accordingly, the internal body diode of PMOS transistor MP201of output interface201is turned off, and any potential channel current from pin PAD of output interface201to its voltage supply VDDIO is blocked. The architecture ofFIG. 2, however, suffers from reliability issues in high-voltage application. For example, where voltage at pin PAD of supplementary voltage comparison circuit210is 10V, PMOS transistors MP211and MP212respectively experience a gate-source and gate-bulk stress of 10V. To replace PMOS transistors to expensive transistors with thicker oxide films increases manufacturing costs.

FIG. 3illustrates an IC output interface architecture according to yet another prior art. InFIG. 3, a prior art IC output interface301includes a cascoded configuration of two series PMOS transistors MP301and MP302whose bulks are tied to each other and their respective source and drain nodes. PMOS transistor MP302is driven internally to forward voltage supplied by voltage supply VDDIO to pin PAD as data signal output. PMOS transistor MP301is driven by NMOS transistor MN301controlled by signal ENABLE of output interface301. Pass PMOS transistor MN303connected the gate and drain of PMOS transistor MP301.

During a normal operation, when output interface301is enabled via signal ENABLE, pass PMOS transistor MP303is turned off, and NMOS transistor MN301is turned on, pulling the gate of PMOS transistor MP301to 0V to turn it on. This effectively turns PMOS transistor MP301into a switch, the switching of which is controlled by PMOS transistor MP302, and NMOS transistor MN302coupled to PMOS transistor MP302in a push-pull configuration. The voltage supplied to output interface301by voltage supply VDDIO is provided to pin PAD via resistor R301as data signal output.

During a failsafe operation, voltage supply VDDIO is down, and signals ENABLE and signals provided to PMOS transistor MP302and NMOS transistor302are at 0V. Accordingly, NMOS transistor MN301is turned off and PMOS transistor MP303is turned on, which in turn connects the gate of PMOS transistor MP301to its drain and effectively turns PMOS transistor MP301to act as its body diode D1. When pin PAD is driven high, the reverse-biased body diode D1of PMOS transistor MP301blocks any channel current through body diode D2of PMOS transistor MP302. Additionally, connecting the bulks of PMOS transistors MP301and MP302places their respective body diodes D1and D2out of phase with each other, effectively cutting off current from pin PAD.

The prior art output interface ofFIG. 3, however, also suffers reliability issues in high-voltage application, such as when pin PAD is driven by an external voltage higher than the voltage the oxides of PMOS transistors MP301and MP302can withstand. For instance, when voltage supply VDDIO is down and pin PAD is driven by an external voltage of 10V, the oxide of PMOS transistor MP302designed to withstand only 5V will be subject to 10V stress across its gate and source, and its gate and drain. Similar to output interface201ofFIG. 2, replacing the transistors of output interface301ofFIG. 3would increase its manufacturing costs.

An aspect of the present invention provides an output interface module with a circuitry design to prevent application of high-voltage on the transistors of the output interface module. According to an aspect of the present invention, a level shifter is configured to provide at least two different ranges of voltages to an output interface module to regulate the level of voltage applied to the output interface module's transistors. One of at least two different ranges of voltage is selected to be applied to the output interface module based on a level of voltage supplied to the output interface module by a voltage supply.

According to yet another aspect of the present invention, an output interface module employs a drain-extended MOSFET (De-MOS). De-MOS are asymmetric transistors whose drains have been extended by the addition of an isolated compensated p-well (or n-well in case of drain-extended NMOS). This increases the breakdown voltage and hence the voltage withstanding capacity of the transistor across its drain-gate, drain-source and drain-bulk nodes. As a result, a thin oxide MOSFET can operate reliably when a voltage higher than its rating is applied at its drain. For example, a 5V De-MOS can withstand only 5V across gate-bulk and gate-source, but 12V across drain-gate, drain-source and drain-bulk nodes. The construction of this device necessitates no additional mask and hence translates to savings in manufacturing cost and die area.

FIG. 4illustrates an IC output interface module according to an aspect of the present invention. The output interface module400ofFIG. 4includes pull-up circuitry410, level shifter430, voltage regulating circuitry450, and pull-down circuitry470. Pull-up circuitry410and pull-down circuitry470, which are coupled to each other, are each coupled to output pin PAD. Based on data incoming to output interface module400, pull-up circuitry410and pull-down circuitry470respectively outputs high voltage and low voltage to output pin PAD. The high voltage output from output pin PAD corresponds to high logic signal and the low voltage output corresponds to low logic signal.

The transistors of pull-up circuitry410and pull-down circuitry470may be De-MOS to withstand voltage stress of over 5V across their gate-drain, gate-source, and gate-bulk nodes. The operations of these transistors will be further explained below in relation toFIGS. 6-10.

Voltage supply VDDIO to output interface module400may provide a voltage of wide-range. For instance, it may provide a voltage within a range of 0V˜10V. Signal LMODE is provided to pull-up circuitry410based on a level of voltage output from voltage supply VDDIO and a voltage tolerance level of one or more transistors of output interface module400. In the example ofFIG. 4, one or more transistors of output interface module has a voltage tolerance VSAFE of 5V. When voltage from voltage supply VDDIO swings within a range of 0V˜5V, the value of signal LMODE is “1”. When voltage from voltage supply VDDIO is over 5V and equal to or less than 10V, the value of signal LMODE is “0”.

Signal LMODE may be externally supplied through a pin of output interface module400based on the level of voltage operating output interface module400or voltage supply VDDIO. Alternatively, signal LMODE may be generated on chip using a comparator topology that sets signal LMODE to “0” as soon as voltage from voltage supply VDDIO goes beyond a transistor's voltage tolerance level VSAFE.

Level shifter430is configured to provide at least two different ranges of voltage to pull-up circuitry410based on the voltage level of voltage supply VDDIO.FIG. 5illustrates level shifter430with voltage outputs thereof. When the voltage of voltage supply VDDIO is above zero but equal to or less than a transistor's voltage tolerance level, signal LMODE is set to “1”. When signal LMODE is set to “1”, level shifter430outputs voltage that swings between 0V and voltage of voltage supply VDDIO as illustrated in signal form (a) ofFIG. 5.

When the voltage of voltage supply VDDIO is above a transistor's voltage tolerance level, signal LMODE is set to “0”. When signal LMODE is set to “0”, level shifter430outputs voltage that swings between voltage VREF and voltage of voltage supply VDDIO as illustrated in signal form (b) ofFIG. 5. Voltage VREF is a reference voltage chosen to prevent voltage exceeding a voltage tolerance level of a transistor of pull-up circuitry410from applying to the transistor. For instance, voltage VREF may be 5V when voltage supply VDDIO outputs 5V and a transistor of pull-up circuitry410is 5V De-MOS. By shifting the level of low voltage provided to pull-up circuitry410when voltage of voltage supply VDDIO is 10V, level shifter430prevents a voltage above a voltage tolerance level VSAFE from being applied to a transistor of pull-up circuitry, such as 5V De-MOS. Accordingly, a reliable operation is ensured.

Level shifter430may be implemented with a conventional level-shifting topology with auxiliary arms for low-voltage operations.

Signal LMODE_VDDIO is also provided to pull-up circuitry410to turn on a transistor of pull-up circuitry410based on the voltage level of voltage supply VDDIO. The waveform of signal LMODE-VDDIO follows signal LMODE, but it is shifted to a voltage level sufficient to operate a transistor of pull-up circuitry when voltage of voltage supply VDDIO is above voltage VSAFE. In one example, level shifter430level shifts signal LMODE to correspond to the voltage level of voltage supply VDDIO and provides to pull-up circuitry410as signal LMODE_VDDIO.

FIG. 6illustrates the voltage and signals of IC output interface module ofFIG. 4during a regular operation, andFIGS. 7-8illustrate signals of the IC output interface module ofFIG. 4during the operation. Pull-up circuitry410of output interface module400includes three cascoded PMOS transistors MP411, MP412, and MP413to drive high output pin PAD. In one example, PMOS transistors MP411, MP412, and MP413may be De-PMOS. Pull-down circuitry470of output interface module400includes NMOS transistor MN471to drive low output pin PAD.

PMOS transistor MP412is driven by level shifter430based on signal Incoming Data of highs and lows. When signal Incoming Data is high, PMOS transistor MP412is turned on, and when signal Incoming Data is low, PMOS transistor MP412is turned off. Pull-up circuitry410further includes NMOS transistors MN411and MN412driven by signal LMODE. NMOS transistor MN411and MN412, in turn, respectively drives PMOS transistors MP411and MP413. The bulks of PMOS transistors MP411and MP412are tied to each other and to a common source-drain node N1. The bulk of PMOS transistor MP413is connected to its own drain.

Pull-up circuitry410further includes PMOS transistor MP414connecting the gate of PMOS transistor MP411to its drain when turned on. The gate of PMOS transistor MP413is connected through resistor R411to its drain.

The gate of PMOS transistor MP414is driven by signal LMODE_VDDIO from level shifter430. Signal LMODE_VDDIO swings between 0V and voltage of voltage supply VDDIO when signal LMODE is “1”. Signal LMODE_VDDIO swings between VREF and voltage of voltage supply VDDIO when signal LMODE is “0”. When LMODE is “1”, PMOS transistor MP414is turned on when LMODE_VDDIO signal is close to 0V and turned off when LMODE_VDDIO signal is close to voltage of voltage supply VDDIO. When LMODE is “0”, PMOS transistor MP414is turned on when LMODE_VDDIO signal is close to VREF and turned off when LMODE_VDDIO signal is close to voltage of voltage supply VDDIO. By shifting the levels of voltage supplied to PMOS transistor MP414based on the voltage level of supply voltage VDDIO, output interface module410maintains voltage applied to PMOS transistor MP414within its voltage tolerance range.

NMOS transistor471of Pull-down circuitry470is turned on and off based on signal Incoming Data of highs and lows. When signal Incoming Data is high, NMOS transistor MP471is turned off, and when signal Incoming Data is low, NMOS transistor MP471is turned on.

Voltage regulating circuitry450includes resistors R451and R452, which are connected in series between voltage supply VDDIO and output pin PAD. Resistors R451and R452are high-valued resistors. Resistors R451and R452bias common source-drain node N1as further described below during normal and failsafe operations.

InFIG. 6, voltages and signal values of output interface module400is reflected next to their respective node or signal reference. For instance, inFIG. 6, signal LMODE is set to either “1” or “0”.

When signal LMODE is set to “1”, or when voltage supplied by voltage supply VDDIO is below voltage VSAFE, NMOS transistors MN411and MN412are turned on. Further signal LMODE_VDDIO is set to the voltage provided by voltage supply VDDIO, which turns off PMOS transistor MP414. Output interface module400further includes high value resistor411. Accordingly, both node G1and node G2are pulled to 0V, which respectively turns on PMOS transistors MP411and MP413.

When signal LMODE is set to “1”, PMOS transistor MP412is driven by a full-swing level-shifter430whose output swings between 0V and voltage of voltage supply VDDIO based on signal Incoming Data. Inverter405inverts signal Incoming Data to provide to level shifter430. Where signal Incoming Data is a high, as illustrated in section710ofFIG. 7, inverter405outputs 0V to level shifter430. In response, level shifter430outputs 0V to PGATE and PMOS transistor MP412is turned on. Accordingly, voltage at node N1and node N2is equal to voltage supplied by voltage supply VDDIO. Inverter405also outputs the inverted signal to NMOS transistor MN471of pull-down circuitry470via NGATE, which turns off NMOS transistor MN471. As PMOS transistor MP412is turned on and NMOS transistor MN471is turned off, pull-up circuitry410outputs voltage provided by voltage supply VDDIO to output pin PAD via resistor401as high logic data, as illustrated in section710ofFIG. 7.

Conversely, when signal Incoming Data is low, NMOS transistor MN471of pull-down circuitry470is turned on and PMOS transistor MP412of pull-up circuitry is turned off and low voltage of 0V is provided to output pin PAD as low logic signal. VREF output of level shifter430is negligible to the operation of output interface module400when signal LMODE is set to “1”.

When signal LMODE is set to “0”, or when voltage supplied by voltage supply VDDIO is over voltage VSAFE, NMOS transistors MN411and MN412of pull-up circuitry410are turned off, and signal LMODE_VDDIO is set to voltage VREF, which is provided by level shifter430. Accordingly, PMOS transistor MP414is turned on and PMOS transistors MP411and MP413are connected in diode configuration respectively through the turned on PMOS transistor MP414and resistor R411. Voltage at node N1is equal to the voltage supplied by voltage supply VDDIO minus the threshold voltage of PMOS transistor MP411, VtMP411, and the voltage at node G1is equal to the voltage at N1.

When signal LMODE is set to “0”, PMOS transistor MP412of pull-up circuitry410is driven by a voltage output from a reduced-swing level shifter430, the voltage output of which only swings between VREF and the voltage of voltage supply VDDIO. Accordingly, when signal Incoming Data is a high, as illustrated in section810ofFIG. 8, level shifter430outputs voltage VREF to PGATE, which turns on PMOS transistor MP412.

When PMOS transistor MP412is on, voltage at node N2is equal to the voltage supplied by voltage supply VDDIO minus the threshold voltage of PMOS transistor MP411, VtMP411. Further, when PMOS transistor MP412is on, voltage at the drain of PMOS transistor MP413is equal to the voltage supplied by voltage supply VDDIO minus the threshold voltage of PMOS transistor MP411, VtMP411, and the threshold voltage of PMOS transistor MP413, VtMP413. The voltage at node G2is equal to the voltage at the drain of PMOS transistor MP413.

Also, when signal Incoming Data is high, 0V is applied to NGATE, which turns off NMOS transistor471of pull-down circuitry470. As a result, pull-up circuitry410outputs the voltage provided by voltage supply VDDIO minus VtMP411and VtMP413to output pin PAD as high logic data, as illustrated in section810ofFIG. 8. Conversely, when signal Incoming Data is low, NMOS transistor MN471of pull-down circuitry470is turned on and PMOS transistor MP412of pull-up circuitry is turned off and low voltage of 0V is provided to output pin PAD as low logic signal.

FIG. 9illustrates the voltages and signals of IC output interface module ofFIG. 4during a failsafe operation, andFIG. 10illustrates signals of the IC output interface module ofFIG. 4during a failsafe operation. During a failsafe operation, voltage supply VDDIO is down and output pin PAD is driven to a high voltage (e.g., VPAD=10V) by an external device or a bus. Signal LMODE and LMODE_VDDIO are all low during a failsafe operation as illustrated inFIG. 10. Accordingly, NMOS transistor MN411and MN412are off, allowing PMOS transistors MP411and MP413to be connected in diode configuration respectively through PMOS transistor MP414and resistor R411. The diode configuration of PMOS transistors MP411and MP413are illustrated in dotted lines inFIG. 9.

When output pin PAD is driven externally, the diode configuration of PMOS transistors MP411and MP413are reverse biased, preventing reverse current to voltage supply VDDIO. High-value resistors R451and R452may be chosen based on a design's pin budget and act as a voltage divider between output pin PAD and voltage supply VDDIO, biasing node N1to VPAD (R451)/(R451+R452). Voltage at PGATE and NGATE is 0V, and voltage at node N2is the same as the voltage of N1, VPAD (R451)/(R451+R452). In the absence of such biasing, voltage at node N1will be 0V, causing voltage stress on PMOS transistor MP412across its gate and source.

When output pin PAD is driven externally, voltage at node G2follows VPAD because of PMOS transistor MP412is configured to function as a diode. Current from output pin PAD to voltage supply VDDIO, IFAILSAFE, is limited due to resistors R451and R452. The current of IFAILSAFE during a failsafe operation is VPAD/(R451+R452) and may be limited to be under 20 nA.

According to the design of output interface module400ofFIG. 4, none of PMOS transistors MP411, MP412, and MP413is subject to a voltage more than VPAD (R451)/(R451+R452), which can be ensured to be less than voltage VSAFE with proper selection of resistor R451and R452. For instance, when voltage at output pin PAD, VPAD, is 10V, values of resistors R451and R452can be equal so that no PMOS transistors MP411, MP412, and MP413is subject to more than 5V across its terminals.

Below table 1 shows a comparison of prior art designs and a design according toFIG. 4. Both prior art designs ofFIGS. 3 and 4, and a design ofFIG. 4were subject to gate oxide stress analysis during a failsafe operation (e.g., voltage supply VDDIO is down, voltage at output pin PAD is 10V). The below table shows a comparison of the resulting failure-in-time (FIT) rate, a metric quantifying the dielectric degradation of a circuit over its entire lifetime of operation.

It is to be understood that other examples may be employed and that various structural, logical, and electrical changes may be made. Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.