Output device and test apparatus

An output device includes a main driver that outputs an output signal in accordance with an input signal input thereto, a noise driver that outputs a noise signal containing a noise waveform, a combiner that outputs a combined signal obtained by combining together the output signal and the noise signal, and a controller. The noise driver (i) sets an output end thereof at high impedance when not supplied with an enable signal, and (ii) varies an voltage level of the noise signal to be output therefrom in accordance with how a control signal supplied thereto varies when supplied with the enable signal. The controller controls the noise driver to output the noise signal containing the noise waveform that occurs when the output signal travels through a predetermined transmission line, by controlling a timing at which the control signal varies and a timing at which the enable signal is switched.

BACKGROUND

1. Technical Field

The present invention relates to an output device for outputting a signal and to a test apparatus for testing a device under test.

2. Related Art

A test apparatus is connected to a device under test by means of a substantially ideal transmission line having low L and C components. Thus, less noise is added to the signal output from the test apparatus while the signal travels through the transmission line. Here, a known test apparatus applies to a device under test a test signal that contains noise (see Patent Documents 1 and 2).Patent Document 1: Japanese Patent Application Publication No. 2004-012225Patent Document 2: Japanese Patent Application Publication No. 2004-309153

Here, when the device under test is actually utilized, a signal directed at the device under test travels through a transmission line formed in a printed circuit board, for example. Therefore, more noise is added to the signal during its travel through the transmission line than when the device under test is tested. For this reason, when actually used, the device under test may turn out to be defective even if the device under test has been judged to be acceptable by the test apparatus.

SUMMARY

To address the above-described issue, a first embodiment of the present invention provides an output device including a main driver that outputs an output signal in accordance with an input signal input thereto, a noise driver that outputs a noise signal containing a noise waveform, and a combiner that outputs a combined signal obtained by combining together the output signal and the noise signal. The first embodiment of the present invention also provides a test apparatus. The noise driver (i) may set an output end thereof at high impedance when not supplied with an enable signal, and (ii) vary an voltage level of the noise signal to be output therefrom in accordance with how a control signal supplied thereto varies when supplied with the enable signal. The output device may further include a controller that controls the noise driver to output the noise signal containing the noise waveform that occurs when the output signal travels through a predetermined transmission line, by controlling a timing at which the control signal varies and a timing at which the enable signal is switched.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1illustrates the configuration of an output device10relating to an embodiment of the present invention. The output device10relating to the present embodiment outputs a combined signal obtained by combining together an output signal that is generated in accordance with an input signal input to the output device10and a noise signal containing a noise waveform.

For example, the output device10is used as a signal source of a test apparatus. In this case, the output device10outputs, as a test signal, a combined signal that is obtained by combining together an output signal that is generated in accordance with a test pattern supplied to the output device10and a noise signal containing a noise waveform. The noise waveform may be determined in accordance with the noise that may occur when the output signal generated in accordance with the test pattern travels through a transmission line of the actual usage environment of a device under test. Such a test apparatus including the output device10will be described later with reference toFIG. 9.

The output device10includes a main driver22, a noise driver24, a first output resistance26-1, a second output resistance26-2, a first signal line28-1, a second signal line28-2, a combiner30, and a controller32.

The main driver22receives an input signal representing a logic value, and outputs an output signal in accordance with the received input signal. For example, the main driver22outputs an output signal whose voltage level is set to represent the L logic when the received input signal represents the L logic. As an alternative example, the main driver22outputs an output signal whose voltage level is set to represent the H logic when the received input signal represents the H logic.

The noise driver24is controlled by the controller32so as to output a noise signal containing a noise waveform. Specifically speaking, the noise driver24outputs a noise signal containing a noise waveform that is determined in accordance with a control signal and an enable signal received from the controller32.

The noise driver24sets its output at high impedance, while the enable signal is not supplied to the noise driver24. The noise driver24varies the voltage level of the noise signal output therefrom, in accordance with the varying control signal supplied thereto, while the enable signal is supplied to the noise driver24.

Specifically speaking, the noise driver24varies the voltage level of the noise signal from the voltage level corresponding to the L logic to the voltage level corresponding to the H logic, when supplied with the enable signal and the control signal varies from the L logic to the H logic. The noise driver24varies the voltage level of the noise signal from the voltage level corresponding to the H logic to the voltage level corresponding to the L logic, when supplied with the enable signal and the control signal varies from the H logic to the L logic.

The first output resistance26-1is connected at one end thereof to the output end of the main driver22. The first signal line28-1is connected at one end thereof to the end of the first output resistance26-1that is not connected to the main driver22. The end of the first signal line28-1that is not connected to the first output resistance26-1is connected to the combiner30. Thus, the first output resistance26-1and the first signal line28-1are connected in series to each other, and can pass the output signal output from the main driver22to the combiner30.

The second output resistance26-2is connected at one end thereof to the output end of the noise driver24. The second signal line28-2is connected at one end thereof to the end of the second output resistance26-2that is not connected to the noise driver24. The end of the second signal line28-2that is not connected to the second output resistance26-2is connected to the combiner30. Thus, the second output resistance26-2and the second signal line28-2are connected in series to each other, and can pass the noise signal output from the noise driver24to the combiner30.

The combiner30receives the output signal output from the main driver22and the noise signal output from the noise driver24, and combines together the output signal and the noise signal to generate a combined signal. For example, the combiner30outputs a combined signal obtained by adding together the output signal and the noise signal. The combiner30then outputs the combined signal obtained by combining together the output signal and the noise signal from an output terminal12.

For example, the combiner30may be configured such that the signal line through which the output signal from the main driver22travels and the signal line through which the noise signal from the noise driver24travels are merged together into a single signal line. As an alternative example, the combiner30may be configured such that the signal line through which the output signal from the main driver22travels and the signal line through which the noise signal from the noise driver24travels are connected together via resistances. In this case, the values of the respective resistances are selected so that the value of the resistance of the combiner30when seen from the output terminal12is equal to the value of the terminating resistance (for example, 50Ω, 75Ω or the like), for example.

Alternatively, the combiner30may be configured so as to receive the output signal and the noise signal directly from the main driver22and the noise driver24, without the output resistances26and the signal lines28. In this case, the output resistances26and the signal lines28, which are connected to each other in series, are provided between the output end of the combiner30and the output terminal12of the output device10.

The controller32controls the timing at which the logic value of the control signal supplied to the noise driver24varies (varying timing) and the timing at which the enable signal is applied/stopped (switching timing), in accordance with the timing at which the logic value of the input signal supplied to the main driver22varies. The controller32thus controls the noise driver24to output the noise signal containing the noise waveform.

For example, the controller32causes the noise driver24to output a noise signal containing a noise waveform that corresponds to the noise that may occur when the output signal output from the main driver22travels through a transmission line of the actual usage environment of the device under test. For example, the controller32controls the varying timing for the control signal and the switching timing for the enable signal in such a manner that the noise driver24generates a noise waveform corresponding to the above-described noise that is obtained through measurement or simulation.

FIGS. 2A to 2Fillustrate exemplary signals generated by the output device10relating to the present embodiment. The main driver22receives an input signal whose logic value varies at a designated timing as shown inFIG. 2A.

The main driver22varies the voltage level of the output signal from the voltage level corresponding to the L logic to the voltage level corresponding to the H logic as shown inFIG. 2B, when the waveform of the input signal varies from the L logic to the H logic. On the other hand, the main driver22varies the voltage level of the output signal from the voltage level corresponding to the H logic to the voltage level corresponding to the L logic as shown inFIG. 2B, when the waveform of the input signal varies from the H logic to the L logic.

The controller32varies the logic value of the control signal in a predetermined direction at the timing that is delayed or advanced by a predetermined amount from the varying timing of the input signal, for example, as shown inFIG. 2C. The controller32switches the state of the enable signal to a predetermined state at the timing that is delayed or advanced by a predetermined amount from the varying timing of the input signal, for example, as shown inFIG. 2D.

The noise driver24outputs a noise signal containing a noise waveform that is shaped in accordance with the timing at which and the direction in which the control signal varies and the timing at which and the direction in which the enable signal is switched, for example, as shown inFIG. 2E. For example, the noise driver24generates a triangular noise waveform, whose peak level varies in accordance with the timing at which and the direction in which the control signal varies and the timing at which and the direction in which the enable signal is switched.

The combiner30outputs a combined signal obtained by adding together the output signal shown inFIG. 2Band the noise signal shown inFIG. 2E, as shown inFIG. 2F. Note that the vertical variation range (the variation in level) for the noise signal is enlarged inFIG. 2E.

FIGS. 3A to 3Gillustrates exemplary noise waveforms in association with the respective temporal differences between the varying timing for the control signal and the switching timing for the enable signal, when the control signal supplied to the noise driver24varies from the L logic to the H logic and the enable signal is switched from the supplied state (enabled state) to the non-supplied state (high-impedance state). For example, the control signal supplied from the controller32to the noise driver24varies from the L logic to the H logic as shown inFIG. 3A.

In a certain case, the controller32switches the enable signal from the supplied state to the non-supplied state, at a timing t12that is a short period of time after a timing t11at which the control signal starts varying (the timing t12is at least before the control signal reaches the H logic level) as shown inFIG. 3B. In this manner, the noise driver24can output a noise signal including a triangular noise waveform whose level increases from the timing t11to the timing t12and decreases from the timing t12until reaching the L logic level, as shown inFIG. 3C.

In a different case, the controller32switches the enable signal from the supplied state to the non-supplied state at a timing t13that is a certain period of time after the timing t11at which the control signal starts varying and comes after the timing t12(the timing t13is at least before the control signal reaches the H logic level), as shown inFIG. 3D. In this manner, the noise driver24can output a noise signal including a triangular noise waveform whose level increases from the timing t11to the timing t13and decreases from the timing t13until reaching the L logic level, as shown inFIG. 3E. In this case, the noise driver24generates a triangular wave with a higher peak level than that of the triangular wave shown inFIG. 3C.

In a further different case, the controller32switches the enable signal from the supplied state to the non-supplied state at a timing t14at which the control signal reaches the H logic level, as shown inFIG. 3F. In this manner, the noise driver24can output a noise signal including a triangular noise waveform whose level increases from the timing t11to the timing t14and decreases from the timing t14until reaching the L logic level, as shown inFIG. 3G.

FIGS. 4A to 4Gillustrate exemplary noise waveforms in association with the respective temporal differences between the varying timing for the control signal and the switching timing for the enable signal, when the control signal supplied to the noise driver24varies from the H logic to the L logic and the enable signal is switched from the non-supplied state (high-impedance state) to the supplied state (enabled state). For example, the control signal supplied from the controller32to the noise driver24varies from the H logic to the L logic as shown inFIG. 4A.

In a certain case, the controller32switches the enable signal from the non-supplied state to the supplied state, at a timing t29that is a short period of time before a timing t30at which the control signal finishes varying as shown inFIG. 4B. In this manner, the noise driver24can output a noise signal including a triangular noise waveform whose level increases from the timing t29to an intermediate timing between the timing t29and the timing t30and decreases from the intermediate timing until reaching the L logic level, as shown inFIG. 4C.

In a different case, the controller32switches the enable signal from the non-supplied state to the supplied state at a timing t28that is a certain period of time before the timing t30at which the control signal finishes varying and comes before the timing t29, as shown inFIG. 4D. In this manner, the noise driver24can output a noise signal including a triangular noise waveform whose level increases from the timing t28to an intermediate timing between the timing t28and the timing t30and decreases from the intermediate timing until reaching the L logic level, as shown inFIG. 4E. In this case, the noise driver24can generate a triangular wave with a higher peak level than that that of the triangular wave shown inFIG. 4C.

In a further different case, the controller32switches the enable signal from the non-supplied state to the supplied state at a timing t27that is before the timing t30at which the control signal finishes varying by a period of time twice as long as the period of time necessary for the control signal completes varying from the H logic level to the L logic level (the timing t27is at least before the timing t28), as shown inFIG. 4F. In this manner, the noise driver24can output a noise signal including a triangular noise waveform whose level increases from the timing t27until reaching the H logic level and decreases from the H logic level to the L logic level, as shown inFIG. 4G.

As described above, the controller32can control the noise waveform generated by the noise driver24, by controlling the timing at which and the direction in which the control signal varies and the timing at which and the direction in which the enable signal is switched. For example, the controller32can control the peak level of the triangular noise waveform by controlling the timing at which and the direction in which the control signal varies and the timing at which and the direction in which the enable signal is switched.

FIG. 5illustrates, as an example, an output signal with a rectangular waveform, observed after the output signal has traveled through the transmission line of the actual usage environment of the device under test.FIG. 6illustrates an exemplary combined signal obtained by combining together an output signal and a noise signal that contains a noise waveform corresponding to ringing noise and a noise waveform corresponding to mismatch-induced reflection.

As shown inFIG. 5, the noise that occurs in the signal while the signal travels through the transmission line includes, for example, ringing noise. The ringing noise is generated by the L and C components of the transmission line. For example, the controller32controls the noise driver24to output a noise signal including a noise waveform corresponding to the ringing noise that may occur when the output signal output from the main driver22travels through a predetermined transmission line.

For example, the controller32controls the noise driver24to generate a triangular noise waveform having a predetermined peak level, at a timing that is delayed by a predetermined period of time from the timing at which the input signal varies. In this manner, the controller32can add to the output signal the noise waveform corresponding to the ringing noise. For example, the controller32may determine the peak level of the noise and the timing at which the noise is generated relative to the timing at which the input signal varies, based on the measured or simulated ringing noise that may occur when the output signal output from the main driver22travels through the transmission line of the actual usage environment.

As shown inFIG. 5, the noise that occurs in the signal while the signal travels through the transmission line includes, for example, mismatch-induced reflection. The mismatch-induced reflection occurs when the signal travels through a connector or the like within the transmission line. For example, the controller32may control the noise driver24to output a noise signal containing a noise waveform corresponding to the mismatch-induced reflection that may occur when the output signal travels through a predetermined transmission line.

For example, the controller32controls the noise driver24to generate a triangular noise waveform with a predetermined peak level, at a timing that is delayed by a predetermined period of time from the timing at which the pulse of the input signal is generated. In this manner, the controller32can add to the output signal the noise waveform corresponding to the mismatch-induced reflection. For example, the controller32may determine the peak level of the noise and the timing at which the noise is generated relative to the timing at which the pulse of the input signal is generated, based on the measured or simulated mismatch-induced reflection that may occur when the output signal output from the main driver22travels through the transmission line of the actual usage environment.

The noise that occurs in the signal while the signal travels through the transmission line includes, for example, crosstalk. The crosstalk results from leakage of a signal from an adjacent transmission line. The controller32may control the noise driver24to output a noise signal containing a noise waveform corresponding to the crosstalk that may occur when the output signal travels through a predetermined transmission line, for example.

For example, the controller32controls the noise driver24to generate a triangular wave with a predetermined peak level at a timing that is delayed by a predetermined period of time from the timing at which the pulse of the input signal to be transmitted through the adjacent transmission line is generated. In this way, the controller32can add to the output signal the noise waveform corresponding to the crosstalk.

As described above, the output device10relating to the present embodiment can add a noise waveform to the output signal generated in accordance with the input signal. Furthermore, the output device10relating to the present embodiment can generate a designated noise waveform by controlling the noise driver24with the use of the enable signal, thereby generating a noise waveform having a shorter duration than the minimum duration that can be achieved by the logic pattern of the input signal supplied to the main driver22.

FIG. 7illustrates the configuration of an output device10relating to a modification example of the embodiment. The output device10relating to the modification example has substantially the same configuration and functionality as the output device10relating to the embodiment described with reference toFIGS. 1 to 6. Therefore, the constituents having substantially the same configuration and functionality as the corresponding constituents of the output device10relating to the embodiment are assigned with the same reference numerals as in the embodiment. The following description of the modification example is made with focus on the differences from the embodiment.

The output device10relating to the modification example additionally includes a calibrating section42, a table storage44, and a power supply46. The calibrating section42measures a noise waveform (for example, measures a peak level and a delay time in the case of a triangular noise waveform) generated by the noise driver24, in association with each combination of the varying timing for the control signal and the switching timing for the enable signal.

The table storage44stores, in association with each noise waveform (for example, each set of a peak level and a delay time in the case of a triangular waveform), a timing at which the control signal varies and a timing at which the enable signal is switched to generate the noise waveform. For example, the table storage44may store the result of the measurement done by the calibrating section42.

The power supply46supplies a power supply voltage to the noise driver24. The controller32controls the power supply voltage generated by the power supply46to control the voltage level of the noise signal output from the noise driver24.

The controller32receives waveform data representing the noise waveform that may occur when the output signal travels through a predetermined transmission line (for example, the transmission line of the actual usage environment of the device under test). For example, the controller32receives waveform data representing measured or simulated noise waveform that may occur in the predetermined transmission line.

The controller32determines the noise waveform in accordance with the waveform data received from outside. For example, the controller32determines the peak level of a triangular noise waveform and the delay time representing the time interval from the timing at which the output signal varies to the peak of the triangular noise waveform, in accordance with the waveform data received from outside.

The controller32selects, from the table storage44, the timing at which the control signal should vary and the timing at which the enable signal should be switched to generate the determined noise waveform. The controller32then adjusts the control signal and the enable signal, based on the timing at which and the direction in which the logic value of the input signal supplied to the main driver22varies and the selected timings. In this manner, the controller32can control the noise driver24to output the noise waveform that may occur in the signal while the signal travels through the predetermined transmission line.

The controller32may control the voltage level of the noise signal output from the noise driver24, in accordance with the level of the noise waveform that may occur when the output signal output from the main driver22travels through the predetermined transmission line. In this manner, the controller32can also control the noise driver24to output the noise waveform that may occur in the signal while the signal the predetermined transmission line.

Alternatively, the output device10may include a plurality of noise drivers24. In this case, the output device10can combine together the noise waveforms generated by the noise drivers24, thereby creating a more complex noise waveform.

The output device10may include a plurality of noise drivers24that respectively generate different noise waveforms. For example, the controller32may include a noise driver24that generates a triangular wave whose peaks are positioned on the positive side and another noise driver24that generates a triangular wave whose peaks are positioned on the negative side. In this manner, the output device10can add to the output signal a noise waveform whose polarity varies depending on the direction in which the input signal varies, for example.

The output end of the controller32may be connected to a capacitor or the like. In this way, the controller32can cause the noise driver24to generate a differentiated or integrated noise waveform.

FIGS. 8A to 8Gillustrate exemplary signals generated by the output device10relating to the modification example. For example, the output device10may include a first noise driver24and a second noise driver24.

The noise signal output from the first noise driver24has a negative voltage (for example, −0.5 V) when the enable signal is not applied and the control signal has the L logic, as shown inFIGS. 8A to 8C. The noise signal output from the first noise driver24has a voltage equal to or higher than 0 V (for example, 2 V) when the control signal has the H logic.

The controller32switches the enable signal for the first noise driver24to the supplied state while the control signal has the H logic. In this way, the first noise driver24can output a noise signal having a rectangular wave in which the voltage is alternately switched between the negative voltage (for example, −0.5 V) and the voltage equal to or higher than 0 V (for example, 2 V).

The noise signal output from the second noise driver24has a negative voltage (for example, −0.5 V) when the enable signal is not applied and the control signal has the L logic, as shown inFIGS. 8D to 8F. The noise signal output from the second noise driver24has a voltage equal to or higher than 0 V (for example, 0 V) when the control signal has the H logic.

The controller32switches the enable signal for the second noise driver24to the supplied state while the control signal has the H logic. In this way, the second noise driver24can output a noise signal having a rectangular wave in which the voltage is alternately switched between the negative voltage (for example, −0.5 V) and the positive voltage (for example, 0 V).

Here, the controller32supplies to the first and second noise drivers24, control signals whose phases are shifted by 180 degrees (or which are inverted) with respect to each other. Thus, the output device10relating to the modification example can generate a combined noise signal including a noise waveform having a peak on the negative side at the timing at which the control signals are switched, as shown inFIG. 8G.

FIG. 9illustrates the configuration of a test apparatus100relating to an embodiment of the present invention, together with a device under test (DUT)200. The test apparatus100has the constituents of the output device10described with reference toFIGS. 1 to 8. The constituents of the test apparatus100that have substantially the same configuration and functionality as the corresponding constituents of the output device10are assigned with the same reference numerals as inFIGS. 1 to 8. The following description of the test apparatus100is made with a focus on the differences from the output device10shown inFIGS. 1 to 8.

The test apparatus100tests the DUT200. The test apparatus100includes a main portion102and a performance board104. The main portion102supplies a signal to the DUT200and acquires a signal from the DUT200.

The performance board104has the DUT200mounted thereon. The performance board104is connected to the main portion102via a signal line28.

The main portion102includes a pattern generator110, a timing generator112, a first waveform generator114-1, a second waveform generator114-2, a main driver22, a noise driver24, a first output resistance26-1, a second output resistance26-2, a level comparator118, a comparator section120, and a judging section122.

The pattern generator110generates a logic pattern representing the waveform of the signal to be generated by the main portion102and the generation timing at which the signal is to be generated. The pattern generator110also generates an expected pattern representing the expected value of a signal to be received at the main portion102from the DUT200and the acquisition timing at which the signal from the DUT200is to be acquired. The pattern generator110supplies the logic pattern to the first and second waveform generators114-1and114-2. The pattern generator110also supplies the expected value to the judging section122and supplies the acquisition timing to the comparator section120.

The timing generator112generates a timing signal representing the timing at which the main portion102outputs a signal. The timing generator112also generates a strobe signal representing the timing at which the main portion102acquires the value of a signal. The timing generator112supplies the timing signal to the first and second waveform generators114-1and114-2and supplies the strobe signal to the comparator section120.

The first and second waveform generators114-1and114-2delay the supplied timing signal by a delay amount determined according to the generation timing designated by the pattern generator110. The first waveform generator114-1generates an input signal having a waveform designated by the pattern generator110at the timing indicated by the delayed timing signal. The first waveform generator114-1supplies the generated input signal to the main driver22.

The second waveform generator114-2generates an enable signal and a control signal having a waveform designated by the pattern generator110at the timing indicated by the delayed timing signal. The second waveform generator114-2supplies the generated control signal and enable signal to the noise driver24.

The main driver22supplies an output signal having a voltage level determined according to the input signal supplied thereto from the first waveform generator114-1, to the performance board104via the first output resistance26-1and a first signal line28-1. The noise driver24supplies a noise signal having a noise waveform shaped in accordance with the enable signal and the control signal supplied thereto from the second waveform generator114-2, to the performance board104via the second output resistance26-2and a second signal line28-2.

The level comparator118receives a signal from a corresponding terminal of the DUT200via a third signal line28-3and generates a logic signal whose logic value varies according to the voltage level of the received signal. The level comparator118supplies the generated logic signal to the comparator section120.

The comparator section120delays the strobe signal supplied thereto from the timing generator112by a delay time determined according to the acquisition timing designated by the pattern generator110. The comparator section120acquires the logic value of the logic signal output from the level comparator118at the timing indicated by the delayed strobe signal. The comparator section120supplies the acquired logic value to the judging section122.

The judging section122compares the logic value acquired by the comparator section120against the expected value designated by the pattern generator110and examines whether they match. The comparator section120supplies the result of the comparison to an external controller. The judging section122may write the result of the comparison into a memory or the like.

In the present embodiment, the performance board104includes a combiner30. The combiner30adds together the output signal output from the main driver22and the noise signal output from the noise driver24, to generate a combined signal. The combiner30then supplies the combined signal, as a test signal, to a predetermined terminal of the DUT200.

The main driver22, the noise driver24, the first output resistance26-1, the second output resistance26-2, the first signal line28-1, the second signal line28-2, and the combiner30of the test apparatus100have the same functions as the corresponding constituents of the output device10. The second waveform generator114-2of the test apparatus100has the same function as the controller32of the output device10. The above-described test apparatus100can supply to the DUT200a test signal having a designated noise waveform added thereto.

The claims, specification and drawings describe the processes of an apparatus, a system, a program and a method by using the terms such as operations, procedures, steps and stages. When a reference is made to the execution order of the processes, wording such as “before” or “prior to” is not explicitly used. The processes may be performed in any order unless an output of a particular process is used by the following process. In the claims, specification and drawings, a flow of operations may be explained by using the terms such as “first” and “next” for the sake of convenience. This, however, does not necessarily indicate that the operations should be performed in the explained order.