Liquid-crystal display device

A display device includes an array substrate having a first data line along a first direction. The array substrate further includes a first insulating layer and a common electrode. The insulating layer disposes on the first data line. The common electrode disposes on the insulating layer and includes a plurality of sub-common electrode rows disposed along the second direction which is different from the first direction. The sub-common electrode rows extend along the second direction. The sub-common electrode rows include a first portion, a second portion separated from the first portion, and a connection portion connecting the first and second portions. The first data line overlapping the sub-common electrode rows, and the number of first portions overlapping the first data line is greater than the number of connection portions overlapping the first data.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of China Patent Application No. 201610289327.4, filed on May 4, 2016, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The present disclosure relates to display devices, and in particular to display devices having less overlap between common electrodes and data lines.

Description of the Related Art

Due to fulfill the requirements of high-speed image processing and high-quality image displays, flat-panel displays, such displays device have become popular.

Thin film transistors (TFTs) are typically formed on the lower substrate as switching devices. Each TFT has a gate electrode connected to a scanning line, a source electrode connected with a data line, and a drain electrode connected to a pixel electrode.

However, as the trend towards better image resolution and larger display devices continues, the length of conductive lines such as data lines and scanning lines used in display devices increases. As the length of conductive lines increases, parasitic capacitance related to the conductive lines such as data lines and scanning lines used in display devices also increases. As a result, undesired resistance-capacitance (RC) time delays will affect the proper operation of the display devices. Therefore, images and relative electrical properties of the display devices are affected.

BRIEF SUMMARY OF THE INVENTION

An exemplary display device comprises an array substrate. The array substrate comprises a substrate and a first data line disposed on the substrate and extending along a first direction. The array substrate further comprises a first insulating layer disposed on the substrate, covering the first data line, and a common electrode disposed on the first insulating layer. The common electrode comprises a plurality of sub-common electrode rows. The sub-common electrode rows extend along the second direction which is different from the first direction. The sub-common electrode rows comprise a first portion extending along the second direction, a second portion extending along the second direction, and at least one connection portion connecting the first portion and the second portion. The second potion is separated from the first portion. The first data line overlaps the sub-common electrode rows. The number of first portions overlapping the first data line is greater than the number of connection portions overlapping the first data line.

DETAILED DESCRIPTION OF THE INVENTION

The following description is of the best-contemplated mode of carrying out the disclosure. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the disclosure is best determined by reference to the appended claims.

This description of the exemplary embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. The drawings are not drawn to scale. In addition, structures and devices are shown schematically in order to simplify the drawing.

The term “substrate” refers to the substrate itself, or to a composite object that includes various elements, various electrical wires and various films formed on a substrate. However, the substrate is represented by a flat surface in order to simplify the drawing. The term “substrate surface” is meant to include the uppermost exposed layers on the substrate, such as a glass surface, an organic polymer surface, and insulating layers and/or metal lines. The substrate may comprise glass, organic polymer, inorganic material, silicon, metal, or any other suitable materials.

In some embodiment of the present disclosure, the parasitic capacitance derived from overlaps between the data lines and the common electrode can be decreased by reducing overlap between the common electrode and the data lines, thereby reducing resistance-capacitance (RC) time delays in the display devices. Moreover, in some embodiments of the present disclosure, overlaps between various data lines and the common electrode can be the same or similar, such that various data lines and the common electrode show the same or similar electrical properties, thereby improving image performance of the sub-pixels controlled by the data lines.

FIG. 1shows a schematic top view showing an array substrate102of a display device100according to an embodiment of the present disclosure.FIG. 2shows an enlargement diagram ofFIG. 1.FIG. 3shows a schematic cross-sectional view along line3-3′ inFIG. 2. In addition, the display device could be an organic light emitting diode display (OLED display), a liquid-crystal display (LCD) or an inorganic light emitting diode display with micrometer size (micro LED display).

InFIG. 1, the array substrate102comprises a plurality of parallel scanning lines (gate lines)104extending along a first direction A1and a plurality of parallel data lines (source lines)106extending along a second direction A2. The scanning lines104and the data lines106are disposed on a substrate102a(seeFIG. 3). Herein, the scanning lines104interlace the data lines106. The first direction A1and the second direction A2are substantially perpendicular or orthogonal with each other. In other words, the first direction A1can be the X-axis and the second direction A2can be the Y-axis, but the first direction A1and the second direction A2can be not perpendicular or orthogonal with each other, having an inclined angle that is not 90 degrees.

In addition, the plurality of the scanning lines104and the plurality of the data lines106define a plurality of sub-pixels108. Herein, the plurality of sub-pixels108are arranged in a three-by-three (3×3) array as illustrated on the array substrate102shown inFIG. 1, illustrating four scanning lines comprising a first scanning line104-1, a second scanning line104-2, a third scanning line104-3, and a fourth scanning line104-4, and four data lines comprising a first data line106-1, a second data line106-2, a third data line106-3, and a fourth data line106-4.

The array substrate102further comprises a plurality of thin-film transistors (TFTs, not shown inFIG. 1, seeFIGS. 3-4) disposed corresponding to the sub-pixels108. Two terminals of the TFTs are electrically connected with the scanning line104and the data line106. Herein, the plurality of sub-pixels108(e.g. the three sub-pixels108illustrated herein) disposed along the first direction A1form a pixel600.

The data lines106provide source signals to the sub-pixels108via the TFTs (not shown inFIG. 1, seeFIGS. 3-4), and the scanning lines104provide scanning pulse-signals to the sub-pixels108via the TFTs (not shown inFIG. 1, seeFIGS. 3-4) to control the sub-pixels108together with the above source signals.

InFIGS. 1 and 3, the array substrate102further comprises a planarization layer140disposed on the substrate102afor overlapping the scanning lines104and the data lines106, and a common electrode300disposed on the planarization layer140. A planarization layer140is defined as the first insulating layer. Herein, the common electrode300comprises a plurality of sub-common electrode rows300R extending along the first direction A1. The sub-common electrode rows300R are sequentially arranged along the second direction A2. For example, three sub-common electrode rows300R extending along the first direction A1are illustrated inFIG. 1, comprising a first sub-common electrode row300-1, a second sub-common electrode row300-2, and a third sub-common electrode row300-3sequentially arranged along the second direction A2. The first, second, and third sub-common electrodes300-1,300-2, and300-3are disposed adjacent to each other. In some embodiments, the sub-common electrode row corresponds to one row of the plurality of sub-pixels.

The sub-common electrode rows300R respectively comprises a first portion300A1and a second portion300A2separated, and a connection portion300A3disposed between the first portion300A1and the second portion300A2for connecting the first portion300A1and the second portion300A2. The first portion300A1and the second portion300A2may extend along the first direction A1.

As shown inFIG. 1, the second portion300A1of one of the sub-common electrode rows300R is connected to the first portion300A1of the sub-common electrode row300adjacent thereto. For example, the second portion300A2of the first sub-common electrode row300-1is connected to the first portion300A1of the second sub-common electrode row300-2. As shown inFIG. 1, the first sub-common electrode row300-1comprises two connection portions300A3, and the second and third sub-common electrode rows300-2and300-3respectively comprises a connection portion300A3. However,FIG. 1only shows a portion of the entire sub-pixel, namely, only shows a plurality of sub-pixels108arranged in a three-by-three (3×3) array. Thus, in the entire sub-pixel of the display device, a sub-common electrode row may have a plurality of connection portions to connect the first portion and the second portion. As shown inFIG. 1, the first data line106-1overlaps the first sub-common electrode row300-1, the second sub-common electrode row300-2, and the third sub-common electrode row300-3. The first data line106-1overlaps the first portion300A1, the second portion300A2, and the connection portion300A3of the first sub-common electrode row300-1. An overlap area from a top view between the first data line106-1and the second and third sub-common electrode row300-2,300-3are different from the overlap area from a top view between the first data line106-1and the first sub-common electrode row300-1. A top view which is viewing from a direction perpendicular to the substrate. In the second sub-common electrode row300-2, the first data line106-1overlaps the first portion300A1and the second portion300A2, but does not overlap the connection portion300A3. Similarly, in the third sub-common electrode row300-3, the first data line106-1overlaps the first portion300A1and the second portion300A2, but does not overlap the connection portion300A3.

Therefore, taking the three-by-three (3×3) sub-pixel array shown inFIG. 1as an example, the number of first portions overlapping the first data line106-1is three, and the number of connection portions overlapping the first data line106-1is one. Namely, the number of first portions overlapping the first data line106-1is greater than the number of connection portions overlapping the first data line106-1.

According to some embodiments, the sub-common electrode rows300R comprise an opening extending along the first direction A1for separating the first portion300A1and the second portion300A2of the sub-common electrode rows300R where it is located. For example, as shown inFIG. 1, the first portion300A1and the second portion300A2in the first sub-common electrode row300-1are separated by a first opening500-1, and connection portions300A3are respectively disposed on a first side and a second side of the first opening500-1. The first side is opposite to the second side. From a top view which is viewing from a direction perpendicular to the substrate, the first opening500-1has a rectangular shape, and the first opening500-1exposes a portion of the underlying planarization layer140. The first opening500-1extends along the first direction and crosses three sub-pixels108disposed between the first data line106-1and the fourth data line106-4, and partially overlaps the second data line106-2and the third data line106-3.

In addition, in the second sub-common electrode row300-2, the first portion300A1and the second portion300-A2are separated by two second openings500-2disposed between the first portion300A1and the second portion300A2, and the connection portion300A3is located between the second openings500-2. The second openings500-2also expose a portion of the planarization layer140. From a top view, the second openings500-2also have a rectangular shape. Similarly, in the third sub-common electrode row300-3, the first portion300A1and the second portion300-A2are separated by two third openings500-3disposed between the first portion300A1and the second portion300A2, and the connection portion300A3is located between the two third openings500-3. The third openings500-3also expose a portion of the planarization layer140. From a top view, the third openings500-3also have a rectangular shape.FIG. 1only illustrates sub-pixels having a three-by-three (3×3) array, thus the second openings500-2illustrated in the second sub-common electrode row300-2are partially illustrated, and the third openings500-3illustrated in the third sub-common electrode row300-3are partially illustrated. Similar with the first opening500-1, in the sub-pixel of the display device, the second opening500-2may also cross three sub-pixels108, and the third opening500-3may also cross three sub-pixels108.

In some embodiments of the present disclosure, the openings in various sub-common electrode rows may be misaligned in respect to the second direction A2. Namely, the openings in at least two sub-common electrode rows are misaligned in respect to the second direction A2. For example, taking the openings500-1and500-2in the first and second sub-common electrode rows300-1and300-2as an example, the first opening500-1is misaligned with the second opening500-2in respect to the second direction (e.g. the second data line106-2). Namely, the first opening500-1and the second opening500-2are misaligned in respect to the second direction A2.

For example, the first opening500-1may be disposed between the first data line and the (l+p)thdata line, the second opening500-2may be disposed between the (l+q)thdata line and the (l+p+q)thdata line, and the third opening500-3may be disposed between the (1+2q)thdata line and the (1+2q+p)thdata line, wherein n, p, and q are positive integers. More specifically, the first opening500-1may be disposed between the first data line106-1and the fourth data line106-4(p=3, q=1), crossing the second data line106-2and the third data line106-3. The second opening500-2may be disposed between the second data line106-2and the fifth data line106-5(not shown), crossing the third data line106-3and the fourth data line106-4. The third opening500-3is disposed between the third data line106-3and the sixth data line (not shown). The first, second and third openings respectively cross three sub-pixels. The symbol “p” represents the number of sub-pixels that the opening may cross. The symbol “q” represents the number of misaligned data lines between two openings. For example, as the first opening500-1crosses the second data line106-2and the third data line106-3, the second opening500-2crosses the third data line106-3and the fourth data line106-4, and the number of misaligned data lines between the first and second openings is 1. The above situation wherein p=3 and q=1 is used only as an example, and the number of “p” symbols can be changed to adjust the number of sub-pixels crossed by the opening, and also to adjust the number of misaligned data lines between two openings.

Through the misaligned configuration of the openings in various sub-common electrode rows, an overlapping area between each of the data lines and the common electrode can be substantially reduced to the same level, such that loading on the data lines can be more even. As shown inFIG. 1, the first data line106-1partially overlaps the second opening500-2in the second sub-common electrode row300-2, but does not overlap the first opening500-1in the first sub-common electrode row300-1. The second data line106-6partially overlaps the first opening500-1in the first sub-common electrode row300-1, but does not overlap the second opening500-2in the second sub-common electrode row300-2. The first data line106-1and the second data line106-2can be disposed adjacent to each other.

As shown inFIG. 1, the respective data lines106partially overlap the first portion300A1and the second portion300A2of the sub-common electrode300A along the second direction A2, but they partially overlap one connection portion300A3of one of the sub-common electrode rows300A. For example, the first data line106-1partially overlaps the first portion300A1and the second portion300A2of the first sub-common electrode row300-1, the second sub-common electrode row300-2, and the third sub-common electrode row300-3, but partially overlaps the connection portion300A3of the first sub-common electrode300-1. Also for example, the second data line106-2partially overlaps the first portion300A1and the second portion300A2of the first sub-common electrode row300-1, the second sub-common electrode row300-2, and the third sub-common electrode row300-3, but partially overlaps the connection portion300A3of the second sub-common electrode row300-2. The other data lines may have a similar configuration and are not described here for simplicity.

In addition, various data lines and the common electrode may have the same or a similar overlapping configuration along the second direction A2. In one embodiment, taking a predetermined number of sub-common electrode rows as the baseline (for example, taking the three sub-common electrode rows shown inFIG. 1as the baseline), an overlapping region between the first data line106-1and the sub-common electrode row300R is substantially equal to an overlapping region between the second data line106-2and the sub-common electrode row300R. In other words, taking a predetermined number of sub-common electrode rows as the baseline, a total area between the openings in the common electrode and the first data line106-1substantially equals to a total area between the openings in the common electrode and the second data line106-2. For example, the total area between the first, second, and third openings500-1,500-2, and500-3, and the first data line106-1is substantially the same with a total area between the first, second, and third openings500-1,500-2, and500-3, and the second data line106-2.

According to an embodiment, the common electrode may comprise “N” sub-common electrode rows, and each of the sub-common electrode rows comprises at least one opening to form “N” openings, wherein “N” is an integer. The openings extend along the first direction. A total overlapping region between these “N” openings and the first data line is substantially the same as the total overlapping region between these N openings and the second data line.

Generally, since the common electrode300overlaps the scanning lines104and the data lines106, parasitic capacitors are formed. In some embodiments of the present disclosure, as shown inFIG. 1, the overlapping region between the data lines and the common electrode may be reduced. More specifically, the number of first portions300A1of the common electrode overlapping the first data line106-1is greater than the number of connection portions300A3of the common electrode overlapping the first data line106-1. This helps to reduce the parasitic capacitance between the common electrode and the data lines106. In some embodiments, by forming an opening in the common electrode300along the second direction A2, the data lines106respectively overlap the opening (500-1and/or500-2and/or500-3), and the overlaps between the data lines106and the opening contributes to reducing the parasitic capacitance between the common electrode300and the data lines106, thereby reducing the resistance-capacitance (RC) time delay that can happen to each of the data lines106. In addition, the overlapping area between various data lines106and the sub-common electrode rows300R are the same or similar, allowing various data lines to have the same or similar levels of electrical performance, thereby improving the image performance of the related sub-pixels108controlled by the data lines106.

In addition, it should be noted that to clearly describe the present disclosure, other components such as the dielectric layer, the pixel electrode, the liquid-crystal layer and the second substrate that are sequentially formed are not illustrated here. In other embodiments, the display device could be an organic light emitting diode display (OLED display) or an inorganic light emitting diode display with micrometer size (micro LED display), but is not limited thereto.

SeeFIG. 2, a schematic top view of a plurality of sub-pixels108(e.g. three sub-pixels108) in a pixel600(e.g. the upmost pixel600along the second direction A2) is illustrated.FIG. 3illustrates a schematic cross-sectional view along line3-3′ inFIG. 2, andFIG. 4illustrates a schematic cross-sectional view along line4-4′ inFIG. 2.

FIG. 3illustrates a cross-sectional structure of the first pixel108-1of the pixel600inFIG. 2. SeeFIGS. 1-3, the pixel600mainly comprises a substrate102a, and a plurality of U-shaped semiconductor layer110separately disposed a portion of the substrate102a. The shape of the semiconductor layer110is not limited to having a U shape, and can have another shape. An insulating layer103is disposed on the substrate102aand the U-shaped semiconductor layer110. A plurality of scanning lines104extending along the first direction A1are separately disposed on a portion of the insulating layer103and respectively cover a portion of the semiconductor layer110. An insulating layer112is disposed on the substrate102a, the semiconductor layers110, and the scanning lines104. A plurality of data lines106extending along the second direction are separately disposed on the insulating layer112and partially cover a portion of one of the semiconductor layers110. A plurality of conductive layers106′ are respectively disposed on a portion of the insulating layer112between two adjacent data lines106to partially cover another portion of one of the semiconductor layer110. A plurality of contact holes114are separately disposed in the insulating layer112to respectively expose a top surface of several portions of the semiconductor layer110. Herein, the data line106and a portion of the conductive line106′ respectively fills in one of the first contact holes114to form electrical connections to the semiconductor layer102. A planarization layer140is blanketly formed on the substrate102a, the data lines106and the conductive layer106′, and the insulating layer112. A common electrode300made of transparent conductive materials is formed on the planarization layer140. The common electrode300comprises a plurality of sub-common electrode rows300R. The sub-common electrodes300R comprise the openings500. A dielectric layer145is defined as the second insulating layer. A dielectric layer145is disposed on the planarization layer140and the common electrode300, and fills in the opening500. A plurality of second contact holes147are separately disposed in a portion of the dielectric layer145and the planarization layer140to respectively expose a top surface of a portion of the conductive layer106′ and partially overlaps one of the first contact holes114thereunder. A plurality of comb-like-shaped transparent electrodes150having a plurality of slits152therein are respectively disposed on the dielectric layer145in each of the sub-pixels108, and a portion of the transparent electrode150fills in one of the second contact holes147to contact the conductive layer106′. A pixel structure is formed in the sub-pixel area108.

As shown inFIG. 2, the portion of the transparent electrode150formed in the second contact holes147is used to electrically connect a drain of a thin-film transistor device (composed of portions of the scanning line104, the insulating layer103and the semiconductor layer110) and functions as a pixel electrode, and the second contact hole147partially overlaps one of the first contact holes114, thereby exposing a portion of the conductive layer106′. The transparent electrode120formed in the second contact hole147partially overlaps and contacts the conductive layer106′, thereby forming electrical connections.

As shown inFIG. 3, in some embodiments, the transparent electrodes150connected to the conductive layer106′ can be a patterned electrode comprising a plurality of slits152. Moreover, the display device100comprises an array substrate102, an opposing substrate604, and a liquid-crystal layer602disposed between the opposing substrate604and the array substrate102. Herein, formation of the slits152of the transparent electrode150(functioning as pixel electrodes) and the common electrode allows the display device100to function as a fringe-field-switching (FFS) type liquid-crystal display (LCD) panel.

As shown inFIG. 3, since the first sub-common electrode row300-1overlaps the underlying first data line106-1, components such as the sub-common electrode row300-1, the first data line106-1and the planarization layer140in the sub-pixel108still form a parasitic capacitor that has a parasitic capacitance.

Moreover,FIG. 4illustrates a schematic cross-sectional view of the second sub-pixel108-2of the pixel600shown inFIG. 2, which is a cross-sectional view along line4-4′ inFIG. 2. Unlike the cross sectional view shown inFIG. 3, in the second sub-pixel108-2, the sub-common electrode row300-1on the second data line106-2is partially removed to form the opening500-1. That is, the second data line106-2partially overlaps the opening500-1. Thus, a portion of the first sub-common electrode row300-1does not overlap the second data line106-2in the second sub-pixel108-2. Corresponding to the first sub-pixel108-1shown inFIG. 3, the first common electrode row300-1overlaps the first data line106-1. Thus, in the second sub-pixel108-2, the parasitic capacitance between the common electrode and the data line106-2can be reduced.

In some embodiments, the TFTs in the display device100disclosed above are illustrated with a top-gate structure, as shown inFIGS. 3-4, and the scanning line (gate line)104is located on the semiconductor layer110. In other embodiments, the TFTs in the display device100can be formed with a bottom-gate structure, and the scanning line (gate)104is located under the semiconductor layer110.

The above embodiments are provided with an example having a plurality of sub-pixels arranged in a three by three array, and the openings in the sub-common electrode rows may cross three sub-pixels, but the disclosure is not limited thereto. According to need, a plurality of sub-pixels arranged in an m by m array can be designed (wherein m is a positive integer), and the openings in the sub-common electrode row may cross m sub-pixels.

For example,FIG. 5illustrates another exemplary display device100S. The structure shown inFIG. 5is substantially the same with that shown inFIG. 1, butFIG. 5is provided with a plurality of sub-pixels arranged in a six by six (m×m, m=6) array. The common electrode300comprises six sub-common electrode rows300R, respectively extending along the first direction A1. Each of the sub-common electrode rows300R comprises a first portion300A1and a second portion300A2, and a connection portion300A3connecting the first portion300A1and the second portion300A2. The opening500in the sub-common electrode row300R crosses six (m) sub-pixels. The number of first portions300A1overlapping the first data line106-1is six, and the number of connection portions300A3overlapping the first data line106-1is one. That is, the number of first portions300A1overlapping the first data line106-1is greater than the number of connection portions300A3overlapping the first data line106-1.

Similar with that illustrated inFIG. 1, the opening formed in various sub-common electrode rows may be misaligned along the second direction. That is, the openings in at least two of the sub-common electrode rows are misaligned along the second direction A2. For example, the first opening500-1in the first sub-common electrode row300-1is disposed between the first data line and the (l+p)thdata line, the second opening500-2is disposed between the (l+q)thdata line and the l+p+qth data lone, and the 3rdopening500-3is disposed between the 1+2qth data line and the (1+2q+p)thdata line, . . . and the sixth opening500-6is disposed between the (1+5q)thdata line and the (1+5q+p)thdata line, wherein n, p, and q are positive integers. More specifically, the first opening500-1is disposed between the first data line106-1and the 7thdata line106-7(p=6, q=1). The second opening500-2is disposed between the second data line106-2and the 8thdata line (not shown), etc., and the sixth opening500-6may be disposed between the second data line106-2and the eighth data line (not shown). The first, second, . . . . , sixth openings respectively cross six sub-pixels. The symbol “p” represents the number of sub-pixels that the opening crosses. The symbol “q” represents the number of data lines misaligned between the two openings. For example, the first opening500-1crosses the second data line106-2to the sixth data line106-6, and the second opening500-2crosses the third data line106-3to the seventh data line106-7. This represents that the number of data lines misaligned between the first and second openings is one. The above situation that p=6 and q=1 is only as an example. In other embodiments, the number of “q” symbols can be changed to adjust the number of sub-pixels to be crossed, and the number of “q” symbols can be changed to adjust the number of misaligned data lines between two openings.

As described above, in some embodiments, the common electrode is partially removed to form openings in the sub-common electrode rows to reduce overlaps between the common electrode and the data lines and reduce the parasitic capacitance issue derived by overlaps between the common electrode and the data lines, thereby reducing the resistance-capacitance (RC) time delay in the display device. In addition, in some embodiments of the present disclosure, various data lines and the common electrode are provided with the same or similar overlapping configurations, such that allowing the same or similar electrical properties of the various data line, and improving the image performance controlled by the various data lines.