Frequency doubling apparatus and method thereof

An apparatus is provided that includes a frequency doubler circuit and a duty cycle adjusting circuit. The frequency doubler circuit includes a multiplexer, a variable delay circuit and a divide-by-2 circuit. The multiplexer selects one of a first and a second clock signals having opposite phases according to a selection signal to generate a frequency doubled clock signal. The variable delay circuit delays the frequency doubled clock signal. The divide-by-2 circuit divides a frequency of the frequency doubled clock signal to generate the selection signal. The duty cycle adjusting circuit includes an average voltage generation circuit and a comparison circuit. The average voltage generation circuit generates an average voltage value of the frequency doubled clock signal. The comparison circuit generates a control signal according to a comparison result of the average voltage value and a reference voltage to control the duty cycle of the frequency doubled clock signal.

RELATED APPLICATIONS

This application claims priority to Taiwan Application Serial Number 108101875, filed Jan. 17, 2019, which is herein incorporated by reference.

BACKGROUND

Field of Invention

The present invention relates to a frequency doubling technology. More particularly, the present invention relates to a frequency doubling apparatus and a frequency doubling method.

Description of Related Art

In general, a frequency doubling apparatus can be implemented by a phase lock loop (PLL) device. Though such a method can generate a clock signal having a doubled frequency accurately, there can be a tiny difference between the transient time and the ideal time called jitter. In order to make the jitter of the clock signal generated by the phase lock loop device smaller, a power source having lower noise or an increasing of the power dissipation can be used to lower the noise generated by the phase lock loop itself. As a result, a higher cost, a higher power dissipation or both of higher cost and power dissipation are required in such application.

Accordingly, what is needed is a frequency doubling apparatus and a frequency doubling method to address the issues mentioned above.

SUMMARY

An aspect of the present invention is to provide an apparatus that includes a frequency doubler circuit and a duty cycle adjusting circuit. The frequency doubler circuit includes a multiplexer, a variable delay circuit and a divide-by-2 circuit. The multiplexer is configured to receive a selection signal and select one of a first clock signal and a second clock signal having opposite phases according to the selection signal to generate a frequency doubled clock signal that has a frequency that is twice of the frequency of the first clock signal and the second clock signal. The variable delay circuit is configured to delay the frequency doubled clock signal for a predetermined time to generate a delayed frequency doubled clock signal. The divide-by-2 circuit is configured to divide a frequency of the delayed frequency doubled clock signal to generate the selection signal. The duty cycle adjusting circuit includes an average voltage generation circuit and a comparison circuit. The average voltage generation circuit is configured to receive the frequency doubled clock signal to generate an average voltage value of the frequency doubled clock signal. The comparison circuit is configured to receive the average voltage value and a reference voltage to generate a control signal according to a comparison result of the average voltage value and the reference voltage to control a duty cycle of the frequency doubled clock signal.

Another aspect of the present invention is to provide a method that includes the steps outlined below. A selection signal is received and one of a first clock signal and a second clock signal having opposite phases is selected according to the selection signal to generate a frequency doubled clock signal that has a frequency that is twice of the frequency of the first clock signal and the second clock signal by a multiplexer of a frequency doubler circuit. The frequency doubled clock signal is delayed for a predetermined time to generate a delayed frequency doubled clock signal by a variable delay circuit of the frequency doubler circuit. A frequency of the delayed frequency doubled clock signal is divided to generate the selection signal by a divide-by-2 circuit of the frequency doubler circuit. The frequency doubled clock signal is received to generate an average voltage value of the frequency doubled clock signal by an average voltage generation circuit of a duty cycle adjusting circuit. The average voltage value and a reference voltage are received to generate a control signal according to a comparison result of the average voltage value and the reference voltage by a comparison circuit of the duty cycle adjusting circuit to control a delay time of the variable delay circuit and to further control a duty cycle of the frequency doubled clock signal.

DETAILED DESCRIPTION

Reference is made toFIG. 1.FIG. 1is a block diagram of a frequency doubling apparatus1in an embodiment of the present invention. The a frequency doubling apparatus1is configured to receive a clock signal, such as a first clock signal CLK1and a second clock signal CLK2and generate a frequency doubled clock signal DFCLK that has a frequency twice of the frequency of the first clock signal CLK1and the second clock signal CLK2. The frequency doubling apparatus1includes a frequency doubler circuit100and a duty cycle adjusting circuit120.

Reference is now made toFIG. 2at the same time.FIG. 2is a diagram of waveforms of signals of the frequency doubling apparatus1in an embodiment of the present invention. The configuration and operation of the frequency doubling apparatus1are described in detail in accompany withFIG. 1andFIG. 2.

The frequency doubler circuit100includes a multiplexer102, a variable delay circuit104and a divide-by-2 circuit106.

The multiplexer102is configured to receive a selection signal CLK3and select one of the first clock signal CLK1and the second clock signal CLK2according to the selection signal CLK3to generate a frequency doubled clock signal DFCLK that has a frequency that is twice of the frequency of the first clock signal CLK1and the second clock signal CLK2. The first clock signal CLK1and the second clock signal CLK2have opposite phases. InFIG. 2, the first clock signal CLK1is illustrated by a solid line and the second clock signal CLK2is illustrated by a dashed line.

The variable delay circuit104is configured to delay the frequency doubled clock signal DFCLK for a predetermined time to generate a delayed frequency doubled clock signal DLCLK. In an embodiment, the period of both of the first clock signal CLK1and the second clock signal CLK2is T. The period of the frequency doubled clock signal DFCLK is T/2, and the predetermined time is T/4. As a result, the period of the delayed frequency doubled clock signal DLCLK is still T/2. However, the delayed frequency doubled clock signal DLCLK has a phase difference T/4 relative to the frequency doubled clock signal DFCLK.

In an embodiment, the divide-by-2 circuit106includes a data flip-flop having a negative feedback configuration. The technology of the data flip-flop and the negative feedback configuration that can be used to implement the function of division by 2 is well known to the skill of the art. As a result, the detail of the data flip-flip is not described herein. The divide-by-2 circuit106is configured to divide a frequency of the delayed frequency doubled clock signal DLCLK to generate the selection signal CLK3. As a result, relative to the delayed frequency doubled clock signal DLCLK, the period of the selection signal CLK3is T.

As a result, during the time interval T0illustrated inFIG. 2, since the selection signal CLK3is at a low state, the multiplexer102inFIG. 1selects the first clock signal CLK1to be outputted. Under such a condition, the positive edge of the frequency doubled clock signal DFCLK in the time interval T0is equivalent to the positive edge of the first clock signal CLK1. Further, in time interval T0, the frequency doubled clock signal DFCLK is illustrated as the solid line corresponding to the first clock signal CLK1.

In the time intervals T1and T2inFIG. 2, since the selection signal CLK3is at a high state, the multiplexer102inFIG. 1selects the second clock signal CLK2to be outputted. Under such a condition, the positive edge of the frequency doubled clock signal DFCLK in the time intervals T1and T2is equivalent to the positive edge of the second clock signal CLK2. Further, in time intervals T1and T2, the frequency doubled clock signal DFCLK is illustrated as the dashed line corresponding to the second clock signal CLK2.

Similarly, in the time intervals T3and T4inFIG. 2, since the selection signal CLK3is at the low state, the multiplexer102inFIG. 1selects the first clock signal CLK1to be outputted. Under such a condition, the positive edge of the frequency doubled clock signal DFCLK in the time intervals T3and T4. The negative edge of the frequency doubled clock signal DFCLK in the time intervals T3and T4is the signal transition caused by the switching of the multiplexer102. Further, in time intervals T3and T4, the frequency doubled clock signal DFCLK is illustrated as the solid line corresponding to the first clock signal CLK1.

In the time intervals T5and T6inFIG. 2, since the selection signal CLK3is at a high state, the multiplexer102inFIG. 1selects the second clock signal CLK2to be outputted. Under such a condition, the positive edge of the frequency doubled clock signal DFCLK in the time intervals T5and T6is equivalent to the positive edge of the second clock signal CLK2. The negative edge of the frequency doubled clock signal DFCLK in the time intervals T5and T6is the signal transition caused by the switching of the multiplexer102. Further, in time intervals T5and T6, the frequency doubled clock signal DFCLK is illustrated as the dashed line corresponding to the second clock signal CLK2.

As a result, by using the mechanism described above, the frequency doubler circuit100can generate the frequency doubled clock signal DFCLK according to the first clock signal CLK1and the second clock signal CLK2, in which the frequency of the frequency doubled clock signal DFCLK is twice of the frequency of the first clock signal CLK1and the second clock signal CLK2.

The duty cycle adjusting circuit120includes an average voltage generation circuit122and a comparison circuit124.

The average voltage generation circuit122is configured to receive the frequency doubled clock signal DFCLK to generate an average voltage value Vave of the frequency doubled clock signal DFCLK.

In an embodiment, the average voltage generation circuit122includes a resistor R and a capacitor C. The resistor R includes a first terminal configured to receive the frequency doubled clock signal DFCLK and a second terminal configured to generate the average voltage Vave of the frequency doubled clock signal DFCLK. The capacitor C is electrically coupled between the second terminal of the resistor R and a ground terminal GND. The resistor R and the capacitor C function together as an integration circuit to generate the average voltage Vave of the frequency doubled clock signal DFCLK. In an embodiment, when the duty cycle of the of the frequency doubled clock signal DFCLK is 50%, in which the durations of the high state and the low state of the of the frequency doubled clock signal DFCLK are the same, and when the high state voltage level is VDD, the average voltage Vave is VDD/2.

The comparison circuit124is configured to receive the average voltage value Vave and a reference voltage Vref to generate a control signal CTL according to a comparison result of the average voltage value Vave and the reference voltage Vref to control the duty cycle of the frequency doubled clock signal DFCLK.

In an embodiment, the reference voltage Vref is set to be VDD/2. A positive terminal of the comparison circuit124receives the reference voltage Vref, and a negative terminal of the comparison circuit124receives the average voltage value Vave. As a result, the condition that the average voltage value Vave is smaller than the reference voltage Vref indicates that the duty cycle of the frequency doubled clock signal DFCLK is smaller than 50%. The comparison circuit124can generate the control signal CTL to increase the delay time of the variable delay circuit104such that the delay time approaches T/4 (the half period of the delayed frequency doubled clock signal DLCLK) and the duty cycle approaches 50%.

On the contrary, the condition that the average voltage value Vave is larger than the reference voltage Vref indicates that the duty cycle of the frequency doubled clock signal DFCLK is larger than 50%. The comparison circuit124can generate the control signal CTL to decrease the delay time of the variable delay circuit104such that the delay time approaches T/4 (the half period of the delayed frequency doubled clock signal DLCLK) and the duty cycle approaches 50%.

As a result, by disposing the duty cycle adjusting circuit120, the mechanism to stabilize the duty cycle of the frequency doubled clock signal DFCLK can be provided.

Further, when the reference voltage Vref changes, the duty cycle adjusting circuit120can generate the control signal CTL to adjust the duty cycle of the frequency doubled clock signal DFCLK. For example, when the reference voltage Vref is set to be VDD/4, the delay time can be set to be T/8 such that the duty cycle of the frequency doubled clock signal DFCLK is controlled to be 25%. When the reference voltage Vref is set to be (¾) VDD, the delay time can be set to be (⅜)T such that the duty cycle of the frequency doubled clock signal DFCLK is controlled to be 75%.

As a result, the relative relation between the amount of the reference voltage Vref and the high state voltage level determines the duty cycle of the frequency doubled clock signal DFCLK.

In conclusion, the frequency doubling apparatus1can use the frequency doubler circuit100with a simple circuit configuration to generate the frequency doubled clock signal DFCLK and use the duty cycle adjusting circuit120to control and adjust the duty cycle of the frequency doubled clock signal DFCLK with stability and accuracy.

In an embodiment, if the components in the frequency doubler circuit100receive power from external power module in operation, the frequency doubler circuit100is easily affected by the jitter of the high frequency of the power and is not able to be adjusted by the duty cycle adjusting circuit120. In an embodiment, the comparison circuit124can be implemented by a low dropout regulator (LDO) circuit to generate the control signal CTL that is in the form of the voltage signal. The control signal CTL can be provided to the multiplexer102and the divide-by-2 circuit106such that the multiplexer102and the divide-by-2 circuit106operate according to the control signal CTL.

Under such a design, the frequency doubling apparatus1can provide the frequency doubler circuit100a voltage stabilizing mechanism without increasing additional area and cost of the stabilizing circuit. The frequency doubled clock signal DFCLK generated therefrom can more stable and accurate.

Further, in an embodiment, the frequency doubled clock signal DFCLK generated by the frequency doubling apparatus1of the present invention can be outputted to one or more than one frequency doubling circuits connected in series (such as but not limited to the circuits implemented also by the frequency doubling apparatus1or by other frequency doubling circuits) to generate the clock signals having the frequency of power of 2 (e.g. 4 times, 8 times and 16 times, etc).

Reference is now made toFIG. 3.FIG. 3is a block diagram of a frequency doubling apparatus3in an embodiment of the present invention. Similar to the frequency doubling apparatus1illustrated inFIG. 1, the frequency doubling apparatus3includes the frequency doubler circuit100and the duty cycle adjusting circuit120. As a result, the identical components are not described herein. The difference between the frequency doubling apparatus3and the frequency doubling apparatus1inFIG. 1is that the frequency doubling apparatus3further includes a reference voltage generation circuit300.

The reference voltage generation circuit300includes an inverter302and a voltage generation circuit304. The inverter302is configured to receive the frequency doubled clock signal DFCLK to generate an inverse frequency doubled clock signal IDFCLK. The configuration of the voltage generation circuit304is identical to the average voltage generation circuit122and includes a resistor R′ and a capacitor C′. The voltage generation circuit304is configured to receive the inverse frequency doubled clock signal IDFCLK to generate an average voltage value of the inverse frequency doubled clock signal IDFCLK such that the average voltage value is fed to the comparison circuit124as the reference voltage Vref.

Under such a configuration, due to the characteristic that the phases of the frequency doubled clock signal DFCLK and the inverse frequency doubled clock signal IDFCLK are opposite, the average voltage value of the inverse frequency doubled clock signal IDFCLK can be used as the reference voltage Vref such that the duty cycle of the frequency doubled clock signal DFCLK can be adjusted to 50%. An additional reference voltage generation circuit is not required.

Reference is now made toFIG. 4.FIG. 4is a flow chart of a frequency doubling method400in an embodiment of the present invention. The frequency doubling method400can be used in the frequency doubling apparatus1illustrated inFIG. 1.

The frequency doubling method400includes the steps outlined below (The steps are not recited in the sequence in which the operations are performed. That is, unless the sequence of the steps is expressly indicated, the sequence of the operations is interchangeable, and all or part of the steps may be simultaneously, partially simultaneously, or sequentially performed).

In step401, a selection signal CLK3is received and one of the first clock signal CLK1and the second clock signal CLK2having opposite phases is selected according to the selection signal CLK3to generate the frequency doubled clock signal DFCLK that has the frequency that is twice of the frequency of the first clock signal CLK1and the second clock signal CLK2by the multiplexer102of the frequency doubler circuit100.

In step402, the frequency doubled clock signal DFCLK is delayed for the predetermined time by the variable delay circuit104of the frequency doubler circuit100.

In step403, the frequency of the delayed frequency doubled clock signal DLCKL is divided to generate the selection signal CLK3by the divide-by-2 circuit106of the frequency doubler circuit100.

In step404, the frequency doubled clock signal DFCLK is received to generate the average voltage value Vave of the frequency doubled clock signal DFCLK by the average voltage generation circuit122of the duty cycle adjusting circuit120.

In step405, the average voltage value Vave and the reference voltage Vref are received to generate the control signal CTL according to the comparison result of the average voltage value Vave and the reference voltage Vref by the comparison circuit124of the duty cycle adjusting circuit120to control the delay time of the variable delay circuit104and to further control the duty cycle of the frequency doubled clock signal DFCLK.