Addition circuit for digital data with a delayed saturation operation for the most significant data bits

An addition circuit for digital data includes a digital adder for the addition of digital input data values present at data inputs of the digital adder to form a summation output data value, at an output of the digital adder. The data inputs have a predetermined data bit width n. A saturation circuit for limits the summation output data value present at a data input of the saturation circuit to be within a range determined by an upper threshold data value and a lower threshold data value. The n−m least significant data bits of the summation output data value are present directly at the data input of the saturation circuit, whereas the m most significant data bits of the summation output data value are switched through to the data input of the saturation circuit via a clock-state-controlled latch register.

FIELD OF INVENTION

The invention relates to a power-saving addition circuit for digital data with a saturation circuit for limiting the output data value range delivered by the addition circuit.

BACKGROUND

DE 40 10 735 C 2 discloses a digital word-serial multiplying circuit. This serves for generating products of two bit-parallel binary signal values, which respectively contain bits of ascending order of significance, including a least significant bit and a most significant bit.

FIG. 1shows an addition circuit for digital data with a saturation circuit. The addition circuit serves for the digital addition of two digital data values A, B. The data values A, B are in each case written to a clocked input register and have a predetermined data bit width n. The input registers A, B serve for the buffer storage of the input data A, B to be added and are respectively connected via n data lines to a data input of a digital adder ADD. The digital adder ADD is based on n full adders and has an n-bit-wide summation output to deliver the summation output data value formed by addition to a saturation circuit SAT. The saturation circuit SAT limits the present summation output data value within a data value range which is determined by an upper and a lower digital threshold value Smin, Smax. This achieves a clipping of the digital output signal. The summation output data value limited by the saturation circuit SAT is buffer-stored in a clocked output register and delivered for further data processing. The two input registers A, B and the output register are clocked by a clock signal CLK via a common clock line.

FIG. 2shows timing diagrams of the signals within the conventional addition circuit, as it is represented in FIG.1.

The conventional addition circuit receives the clock signal CLK with a predetermined clock period Tclkvia a clock signal circuit. With the rising edge at the time t0, a data change takes place in the input data registers A, B, which are summed in the adder ADD. After a signal transit time, the summation output data value occurs at the output of the adder ADD as from the time t2. At the same time, a “glitching” takes place at the output of the adder ADD, i.e. the output data value fluctuates or changes until the final summation output data value has established itself. Glitches are disruptive pulses of short duration. The saturation circuit SAT receives the digital output signal, affected by disruptive pulses, from the adder ADD and delivers the unstable data to the output register between the times t3and t5. The limited summation output data value fluctuates back and forth (“toggling”) during the time ΔT between the upper threshold value, the lower threshold value and the summation output value of the digital adder. Switching over between the upper threshold value and the minimum threshold value causes the data delivered by the saturation circuit SAT to have undergone a very high number of switching operations, resulting in a very high power loss in the saturation circuit SAT.

SUMMARY

It is therefore the object of the present invention to provide an addition circuit for digital data with a saturation circuit in which the power loss caused by switching operations within the saturation circuit is minimal.

The invention provides an addition circuit for digital data with a digital adder for the addition of digital input data values which are present at data inputs of the digital adder to form a summation output data value, which is output at an output of the digital adder, the data inputs having a predetermined data bit width n, a saturation circuit for limiting the summation output data value present at a data input of the saturation circuit within a data value range which is determined by an upper threshold value and a lower threshold value, the n−m least significant data bits.

The addition circuit preferably has input registers for buffer-storing the digital input data values.

The addition circuit preferably has, in addition, an output register for buffer-storing the summation output data value limited by the saturation circuit.

In a preferred embodiment of the addition circuit according to the invention, the input registers and the output register are connected to a clock signal line for applying a clock signal CLK.

The clock-state-controlled latch register preferably has a control input, which is connected to the clock signal line via an inverter circuit.

The upper and lower threshold data values are preferably settable.

In a particularly preferred embodiment of the addition circuit according to the invention, the saturation circuit has a first comparator for comparing the present summation output data value with the upper threshold data value and a second comparator for comparing the present summation output data value with the lower threshold data value.

DETAILED DESCRIPTION

AsFIG. 3reveals, the addition circuit1according to the invention has a first data input2and a second data input3for applying digital input data values. The present input data values are written to input registers6,7, n bits wide in each case, via n parallel data lines4,5for buffer storage. The input registers6,7have in each case a clock signal input8,9. The clock signal inputs8,9of the two input registers6,7are connected via clock lines10,11,12to a clock-signal branching node13of the addition circuit1. The clock-signal branching node13is connected via an internal clock line14to a clock-signal input15of the addition circuit1. The data outputs of the input registers6,7are connected via n parallel data lines16,17to data inputs18,19of a digital adder20. The digital adder20is preferably composed of full-adder components. The digital adder20adds the two digital input data values present at the digital data inputs18,19and delivers a summation output data value via a data output21.

The n−m least significant data bits of the summation output data value formed are applied via n−m parallel data bit lines22directly to a data input23of a downstream saturation circuit24.

The m most-significant data bits of the summation output data value formed are applied via m parallel data bit line25to a data input26of a clock-state-controlled latch register27. The clock-state-controlled latch register27has a control input28, which is connected via a control line29to an output30of an inverter circuit31. The inverter circuit31has an input32, which is connected via a signal line33to the clock-signal branching node13. The inverter circuit31inverts the clock signal CLK present at its input32and delivers it as control signal EN to the control input28of the clock-state-controlled latch register27. The clock-state-controlled latch register27has a data output34, which is connected via m data bit lines35to the data input23of the downstream saturation circuit24.

The saturation circuit24serves for limiting the summation output data value present at the data input23within a data value range which is determined by an upper threshold data value Smaxand a lower threshold data value Smin. In a preferred embodiment, the upper and lower threshold data values Smax, Smincan be set via setting lines36,37and setting connections38,39of the addition circuit1. The saturation circuit24has a data output40, which is connected via n parallel data bit lines41to an input42of the data output register43of the addition circuit1. The data output register43has a clock input44, which is connected via a clock-signal line45to the clock-signal branching node13. The output register43buffer-stores the summation output data value limited by the saturation circuit24and delivers it via n parallel-connected data bit lines46to a data output47of the addition circuit1.

FIG. 4shows a preferred embodiment of the saturation circuit24contained in the addition circuit1. The saturation circuit24contains a first comparator48for comparing the summation output data value present at the data input23with the upper threshold data value Smaxpresent on the setting line36. For this purpose, the first comparator48has a first input49and a second input50for receiving the summation output data value output by the adder20via a line51and for receiving the upper threshold data value Smaxvia a line52. The first comparator48controls, via a control line53, a multiplexer54, which receives the upper data threshold value Smaxvia a first data input55and a data line56and receives the summation output data value ADDoutvia a second data input57and a data line58.

The output value of the first multiplexer54is applied via a data line59to a first signal input60of a second comparator61of the saturation circuit. The second comparator61has a second signal input62, which receives the present settable lower threshold data value Sminvia a line63. The second comparator61controls via a control line64a second multiplexer65, which receives the lower threshold data value Sminvia a first signal input66and a line67. The multiplexer65has a second input68, at which the data value delivered by the first multiplexer54is present via a line69. The second multiplexer65is connected on the output side via a line70to the output40of the saturation circuit24.

If the comparator48detects that the summation output data value ADDputgenerated by the adder20is greater than the set upper threshold data value Smax, the comparator48is driven via the control line33in the first multiplexer54in such a way that the first data output55is switched through to the output lines59. If, in the converse case, the first comparator48detects that the summation output data output value ADDoutis less than the upper threshold value Smax, the multiplexer54is driven via the control line33in such a way that the second data input57, and consequently the present summation output data value, are switched through to the lines59.

The second comparator61compares the data value present on the data lines59with the lower threshold data value Sminand drives the second multiplexer65correspondingly via the control line64. If the data value present on the lines59is less than the minimum threshold value Smin, the data input66of the second comparator65is switched through to the data output40of the saturation circuit24. If the intermediate data value present on the lines59is greater than the minimum threshold data value Smin, the second input68of the second multiplexer65is switched through to the data output40of the saturation circuit24.

In the preferred embodiment shown inFIG. 4, the saturation circuit24is realized by two comparator circuits48,61and two multiplexer circuits54,65.

The two threshold data values Smin, Smaxare preferably chosen as follows:
Smax=2(n−1)−1
Smin=−[2(n−1)]

The upper threshold value Smut includes at least one zero as most significant data bits MSB and n−1 ones as least significant data bits. Therefore, Smaxis:
Smax=2(n−1)−1

The lower threshold value Sminincludes a series of 1 ones as most significant data bits MSB and n−1 zeros as least significant data bits LSB.

The lower threshold data value Sminis consequently:
Smin=−[2(n−1)]

FIG. 5shows timing diagrams of the signals which occur within the addition circuit1according to the invention, as it is represented in FIG.3. At the clock-signal input15there is a common clock signal CLK for the addition circuit1. At the time t0, the input data values lying in the input data registers6,7are switched through by the rising clock edge of the clock signal CLK after a specific signal transit time with respect to the time t1to the data inputs18,19of the digital adder20. As from the time t2, the digital output signal occurs at the output21of the digital adder20. The output data value establishing itself at the output21fluctuates or toggles until the time t4.

The clock signal CLK inverted by the inverter circuit31is present at the control input28of the latch circuit29as enabling signal EN (enable). Between the times t0and t6, no most significant data bits MSB are switched through to the saturation circuit24by the latch circuit27. Between the times t2and t4, the data bits fluctuate back and forth at the output21of the digital adder20.

Between the times t3and t4, glitching of the least significant data bits LSB occurs at the output40of the saturation circuit24. Since the most significant data bits MSB-SAToutare stable at the input23of the saturation circuit24, fluctuation back and forth between the maximum threshold value Smaxand the minimum threshold value Smin(toggling) is avoided, with the result that the number of bit switching operations occurring is minimized. The switching power loss within the saturation circuit24is minimized in the case of the addition circuit1according to the invention by the latch register27for the most significant data bits MSB.

In order that the toggling or fluctuation back and forth at the output40of the saturation circuit24is avoided to the greatest extent, the number m of latched most significant data bits MSB is preferably chosen such that:
m>1

Although the switching power loss within the saturation circuit24falls with increasing values for m, the switching power loss due to the switching operations within the latch register27increases. The minimum switching power loss within the addition circuit1is achieved for:
m=1+2

The data bit width n of the input data to be added is typically in excess of 20 data bits. Dependent on the chosen threshold values Smin, Smax, a value of 4 or 5 data bits is preferably chosen for m.