SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

A method of manufacturing a semiconductor package includes forming an insulating layer; forming a seed layer on the insulating layer; forming a photoresist layer on the seed layer; forming a plurality of line pattern holes by patterning the photoresist layer, a horizontal length of a middle portion of each of the plurality of line pattern holes being less than a horizontal length of an upper portion of each of the plurality of line pattern holes and a horizontal length of a lower portion of each of the plurality of line pattern holes; and forming a redistribution line pattern by performing a plating process using a portion of the seed layer exposed by the plurality of line pattern holes.

CROSS-REFERENCE TO RELATED APPLICATION

A claim of priority under 35 U.S.C. § 119 is made to Korean Patent Application No. 10-2021-0102667, filed on Aug. 4, 2021, in the Korean Intellectual Property Office, the entirety of which is hereby incorporated by reference.

BACKGROUND

The present disclosure relates to semiconductor packages and methods of manufacturing the same.

With the increase in storage capacity of semiconductor chips, semiconductor packages including a semiconductor chip are required to be thin and light. There has recently been interest in including semiconductor chips having various functions in a semiconductor package while providing the capability of driving the semiconductor chips quickly and efficiently. Consequently, the placement of redistribution patterns connected to semiconductor chips has become increasingly complex, and the size of and the distance between the redistribution patterns have been decreasing.

SUMMARY

Embodiments of the inventive concepts provide a semiconductor package with increased structural reliability and improved electromigration.

Embodiments of the inventive concepts also provide a method of manufacturing a semiconductor package including a redistribution pattern with increased structural reliability.

Embodiments of the inventive concepts provide a method of manufacturing a semiconductor package that includes forming an insulating layer on a semiconductor chip; forming a via pattern hole in the insulating layer by etching at least a portion of the insulating layer, the via pattern hole exposing at least a portion of the semiconductor chip; forming a seed layer on the insulating layer and on the portion of the semiconductor chip exposed in the via pattern hole; forming a photoresist layer on the seed layer; exposing the photoresist layer such that an amount of hardening of a middle portion of the photoresist layer is greater than an amount of hardening of an upper portion of the photoresist layer and an amount of hardening of a lower portion of the photoresist layer; forming a photoresist pattern having a plurality of line pattern holes by developing the photoresist layer; and forming a redistribution pattern by filling the via pattern hole of the insulating layer and the plurality of line pattern holes of the photoresist pattern.

Embodiments of the inventive concept further provide a method of manufacturing a semiconductor package that includes forming an insulating layer; forming a seed layer on the insulating layer; forming a photoresist layer on the seed layer; forming a plurality of line pattern holes by patterning the photoresist layer, a horizontal length of a middle portion of each of the plurality of line pattern holes being less than a horizontal length of an upper portion of each of the plurality of line pattern holes and a horizontal length of a lower portion of each of the plurality of line pattern holes; and forming a redistribution line pattern by performing a plating process using a portion of the seed layer exposed by the plurality of line pattern holes.

Embodiments of the inventive concepts still further provide a semiconductor package including a semiconductor chip; an insulating layer on the semiconductor chip; and a redistribution pattern extending in the insulating layer and connected to the semiconductor chip, the redistribution pattern including a plurality of redistribution via patterns and a plurality of redistribution line patterns, the plurality of redistribution via patterns vertically extending in the insulating layer, and the plurality of redistribution line patterns horizontally extending in the insulating layer. A cross-section of each of the plurality of redistribution line patterns includes a lower portion having a horizontal length that increases approaching towards the semiconductor chip, a middle portion on the lower portion and having a side wall that is concave towards a center of the plurality of redistribution line patterns, and an upper portion on the middle portion and having an upper surface that is convex.

According to embodiments of the inventive concepts, a lower portion of a redistribution line pattern of a semiconductor package may have a structure having a horizontal length increasing downwards, and accordingly, a contact area between the redistribution line pattern and an insulating layer may increase. As a result, the adhesion between the redistribution line pattern and the insulating layer may be enhanced, and delamination between the redistribution line pattern and the insulating layer may be decreased. In other words, the structural reliability of the redistribution line pattern may be increased.

According to embodiments of the inventive concepts, because a middle portion of the redistribution line pattern may have a side wall that is concave towards the center of the redistribution line pattern, stress applied to the redistribution line pattern may be dispersed, and accordingly, the structural reliability of the redistribution line pattern may be increased.

According to embodiments of the inventive concepts, because an upper portion of the redistribution line pattern may have an upper surface that is convex upwards, a contact area between the upper portion and the insulating layer may increase.

DETAILED DESCRIPTION

Hereinafter, embodiments are described in detail with reference to the accompanying drawings. Herein, like reference numerals will denote like elements, and redundant descriptions thereof will be omitted for conciseness. Throughout the description, relative locations of components may be described using terms such as “vertical”, “horizontal”, “over”, “higher” and so on. These terms are for descriptive purposes only, and are intended only to describe the relative locations of components assuming the orientation of the overall device is the same as that shown in the drawings. The embodiments however are not limited to the illustrated device orientations.

FIG.1illustrates a cross-sectional view of a semiconductor package10according to embodiments of the inventive concepts.FIG.2illustrates a cross-sectional view of a redistribution line pattern235according to embodiments of the inventive concepts.

Referring toFIGS.1and2, the semiconductor package10may include a semiconductor chip100, a molding layer120, a conductive pillar130, a pillar connection pad150, an insulating layer210, a seed layer220, a redistribution pattern230, a package connection pad250, and a package connection terminal270.

In an example embodiment, the semiconductor chip100may include a logic semiconductor chip. The semiconductor chip100may include a logic semiconductor chip, such as for example, a central processor unit (CPU), a microprocessor unit (MPU), a graphics processor unit (GPU), an application processor (AP) or the like.

However, embodiments are not limited thereto, and in other embodiments the semiconductor chip100may include a memory semiconductor chip. For example, the semiconductor chip100may include a volatile memory semiconductor chip including for example dynamic random access memory (DRAM) or static RAM (SRAM), or a non-volatile memory semiconductor chip including for example phase-change RAM (PRAM), magneto-resistive RAM (MRAM), ferroelectric RAM (FeRAM), or resistive RAM (RRAM).

The semiconductor chip100may include a semiconductor substrate110having an active layer AL, a chip pad114, and a passivation layer118.

The semiconductor substrate110may include silicon (Si). The semiconductor substrate110may include a semiconductor element, e.g., germanium (Ge), or a compound semiconductor such as for example silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP).

The semiconductor substrate110may have an upper surface110_US, which is adjacent to the insulating layer210, and a lower surface110_LS opposite the upper surface110_US. The semiconductor substrate110may have the active layer AL in a portion adjacent to the upper surface110_US of the semiconductor substrate110. In other words, the semiconductor substrate110may have the active layer AL in a portion adjacent to the insulating layer210.

The active layer AL may include various kinds of individual devices. For example, the individual devices may include various microelectronic devices, e.g., complementary metal-oxide-semiconductor (CMOS) transistors, metal-oxide-semiconductor field effect transistors (MOSFETs), system large scale integration (LSI), image sensors such as CMOS image sensors (CIS), micro-electro-mechanical systems (MEMS), active elements, and passive elements.

The chip pad114may be on the upper surface110_US of the semiconductor substrate110and electrically connected to the individual devices of the active layer AL. In an example embodiment, the chip pad114may include at least one material selected from aluminum (Al), copper (Cu), silver (Ag), tin (Sn), and gold (Au).

In an example embodiment, an upper surface of the chip pad114may be in contact with a redistribution via pattern233of the redistribution pattern230. A lower surface of the chip pad114may be in contact with the upper surface110_US of the semiconductor substrate110.

The passivation layer118may be on the upper surface110_US of the semiconductor substrate110and may surround the chip pad114. In an example embodiment, the material of the passivation layer118may include silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), or a combination thereof.

In an example embodiment, an upper surface of the passivation layer118may be coplanar with the upper surface of the chip pad114. In other words, the upper surface of the passivation layer118may expose the upper surface of the chip pad114.

The molding layer120may surround the side of the semiconductor chip100. In an example embodiment, the material of the molding layer120may include an epoxy molding compound (EMC). However, the material of the molding layer120is not limited thereto.

In an example embodiment, an upper surface of the molding layer120may be in contact with a lower surface of the insulating layer210. A lower surface of the molding layer120may be coplanar with the lower surface110_LS of the semiconductor substrate110.

The conductive pillar130may be at an outer side of the semiconductor chip100and may pass through the molding layer120in a vertical direction (e.g., the Z direction). Hereinafter, the vertical direction may be defined as being perpendicular to a direction in which the upper and lower surfaces110_US and110_LS of the semiconductor substrate110extend, and a horizontal direction (e.g., the X direction) may be defined as being parallel with the direction in which the upper and lower surfaces110_US and110_LS of the semiconductor substrate110extend.

In an example embodiment, according to a top view of the semiconductor package10, the conductive pillar(s)130may be around the edge of the semiconductor chip100. The material of the conductive pillar130may include for example at least one selected from Cu, Sn, Ag, and Al. For example, the material of the conductive pillar130may include Cu.

In an example embodiment, an upper surface of the conductive pillar130may be connected to the redistribution via pattern233of the redistribution pattern230, and a lower surface of the conductive pillar130may be connected to the pillar connection pad150.

The pillar connection pad150may include a conductive material and may be attached to the lower surface of the conductive pillar130. In an example embodiment, the material of the pillar connection pad150may include for example at least one selected from Al, Cu, Ag, Sn, and Au.

In an example embodiment, the pillar connection pad150may electrically connect another semiconductor package (not shown), which is mounted on the molding layer120of the semiconductor package10, to the redistribution pattern230. In other words, another semiconductor package mounted on the molding layer120may be electrically connected to the redistribution pattern230through the pillar connection pad150and the conductive pillar130.

In an example embodiment, the pillar connection pad150may be surrounded by the molding layer120. A lower surface of the pillar connection pad150may be coplanar with and exposed from the lower surface of the molding layer120.

However, embodiments are not limited thereto, and in other embodiments the pillar connection pad150may be attached to the lower surface of the molding layer120and protrude therefrom.

The insulating layer210may be on the upper surfaces of the semiconductor chip100and the molding layer120, and may surround the redistribution pattern230. In an example embodiment, the insulating layer210may include oxide or nitride. For example, the insulating layer210may include silicon oxide or silicon nitride. The insulating layer210may include a photo-imageable dielectric (PID) material on which a photolithography process may be performed. For example, the insulating layer210may include photosensitive polyimide (PSPI).

The redistribution pattern230may extend in the insulating layer210and connect the conductive pillar130to the package connection pad250, the semiconductor chip100to the package connection pad250, or the semiconductor chip100to the conductive pillar130.

In an example embodiment, the material of the redistribution pattern230may include Cu. However, embodiments are not limited thereto, and in other embodiments the material of the redistribution pattern230may include metal such as for example nickel (Ni), Au, Ag, Al, tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), Sn, magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), or ruthenium (Ru), or an alloy thereof.

The redistribution pattern230may include the redistribution via pattern233which extends in the vertical direction in the insulating layer210, and the redistribution line pattern235which extends in the horizontal direction in the insulating layer210.

In an example embodiment, the redistribution via pattern233may connect a plurality of redistribution line patterns235to each other in the insulating layer210, or connect a redistribution line pattern235to the conductive pillar130or the chip pad114of the semiconductor chip100.

A plurality of redistribution line patterns235may form a plurality of layers in the insulating layer210. For example, the redistribution line patterns235may form three layers in the vertical direction inFIG.1. However, the number of layers of the redistribution line patterns235is not limited thereto.

The structure and shape of a redistribution line pattern235are described in detail with reference toFIG.2hereinafter.

The seed layer220may be between the insulating layer210and the redistribution pattern230. In detail, the seed layer220may be between the insulating layer210and the redistribution via pattern233as should be understood in view ofFIG.1for example, and between the insulating layer210and the redistribution line pattern235. The seed layer220may be between the redistribution via pattern233and the conductive pillar130, and between the redistribution via pattern233and the chip pad114.

In an example embodiment, the seed layer220may be formed on the insulating layer210using physical vapor deposition, and the redistribution via pattern233and the redistribution line pattern235may be formed on the insulating layer210by performing a plating process using the seed layer220.

In an example embodiment, the material of the seed layer220may include Ti, titanium tungsten (TiW), titanium nitride (TiN), Ta, tantalum nitride (TaN), chrome (Cr), Al, or a combination thereof. For example, the seed layer220may have a structure in which Cu is stacked on Ti, or a structure in which Cu is stacked on TiW. However, the material of the seed layer220is not limited to the above mentioned materials.

The package connection pad250may include a conductive material and connect the package connection terminal270to the redistribution pattern230. An upper surface of the package connection pad250may be exposed from an upper surface of the insulating layer210and be in contact with the package connection terminal270.

In an example embodiment, the material of the package connection pad250may include for example at least one selected from Al, Cu, Ag, Sn, and Au.

The package connection terminal270may be mounted on the package connection pad250and configured to electrically connect the semiconductor package10to an external device. For example, the package connection terminal270may include a metal solder ball including at least one selected from Sn, Ag, Cu, and Al.

Hereinafter, the shape of the redistribution line pattern235is described in detail with reference toFIG.2.

FIG.2may be a cross-sectional view of the redistribution line pattern235in the region A inFIG.1. In detail,FIG.2may be a cross-sectional view of the redistribution line pattern235in the region A inFIG.1along a Y-Z plane.

The redistribution line pattern235may include a lower portion235L, a middle portion235M, and an upper portion235U. Hereinafter, the lower portion235L of the redistribution line pattern235may be a portion of the redistribution line pattern235that is close to (or faces) the semiconductor chip100. The upper portion235U of the redistribution line pattern235may be a portion of the redistribution line pattern235that is close to (or faces) the package connection terminal270.

A height235dof the redistribution line pattern235may be defined as the length of the redistribution line pattern235in the vertical direction (e.g., the Z direction). In an example embodiment, the height235dof the redistribution line pattern235may be about 3 micrometers to about 5 micrometers.

The lower portion235L of the redistribution line pattern235may span a first distance d1from a lower surface235_LS of the redistribution line pattern235. In other words, the first distance d1may correspond to the height of the lower portion235L of the redistribution line pattern235as measured from the top surface of the seed layer220.

In an example embodiment, the first distance d1may be about 20% to about 40% of the height235dof the redistribution line pattern235. For example, the first distance may be about ⅓ of the height235dof the redistribution line pattern235.

For example, when the height235dof the redistribution line pattern235is about 4.2 micrometers, the height of the lower portion235L of the redistribution line pattern235(i.e., the first distance d1) may be about 1.4 micrometers. However, the height of the lower portion235L is not limited to above mentioned height.

The lower portion235L of the redistribution line pattern235may have a structure having a length in the horizontal direction (e.g., the Y direction) increasing downwards (i.e., toward the seed layer220). For example, the lower portion235L of the redistribution line pattern235may have a tapered shape having an X-Y plane cross-sectional area increasing downwards.

A longest length235_Ld of the lower portion235L of the redistribution line pattern235may be defined as the greatest length among the lengths of the lower portion235L in the horizontal direction (e.g., the Y direction). Accordingly, the longest length235_Ld of the lower portion235L of the redistribution line pattern235may correspond to the length of the lower surface235_LS of the redistribution line pattern235in the horizontal direction (e.g., the Y direction).

In an example embodiment, the longest length235_Ld of the lower portion235L of the redistribution line pattern235may be the greatest among the lengths in the horizontal direction (e.g., the Y direction) of the lower portion235L, the middle portion235M, and the upper portion235U of the redistribution line pattern235.

In an example embodiment, the longest length235_Ld of the lower portion235L of the redistribution line pattern235may be about 2 micrometers to about 10 micrometers. However, the longest length235_Ld of the lower portion235L of the redistribution line pattern235is not limited to the above mentioned lengths.

In an example embodiment, the middle portion235M of the redistribution line pattern235may span a second distance d2from the top of the lower portion235L of the redistribution line pattern235. In other words, the second distance d2may correspond to the height of the middle portion235M of the redistribution line pattern235as measured from the top of the lower portion235L.

The middle portion235M of the redistribution line pattern235may connect the upper and lower portions235U and235L of the redistribution line pattern235to each other. A first virtual interface235M_S1may be between the middle portion235M and the lower portion235L of the redistribution line pattern235, and a second virtual interface235M_S2may be between the middle portion235M and the upper portion235U of the redistribution line pattern235. In other words, the middle portion235M of the redistribution line pattern235may be between the first virtual interface235M_S1and the second virtual interface235M_S2.

The middle portion235M of the redistribution line pattern235may have a structure having a length in the horizontal direction (e.g., the Y direction) decreasing and then increasing downwards (i.e., towards the seed layer220). In other words, the middle portion235M of the redistribution line pattern235may have a structure having a horizontal length decreasing and then increasing from the second virtual interface235M_S2toward the first virtual interface235M_S1. For example, the middle portion235M may have a structure having an X-Y plane cross-section area decreasing and then increasing downwards (e.g., the —Z direction).

In an example embodiment, a side wall235M_SS of the middle portion235M of the redistribution line pattern235may have a shape that is concave towards a virtual centerline C passing through the center of the redistribution line pattern235in the vertical direction (e.g., the Z direction).

In an example embodiment, a shortest length235_Md of the middle portion235M of the redistribution line pattern235may be defined as the least (i.e., smallest) length among the lengths in the horizontal direction (e.g., the Y direction) of the middle portion235M.

In an example embodiment, the shortest length235_Md of the middle portion235M of the redistribution line pattern235may have the least (i.e., smallest) value among the lengths in the horizontal direction (e.g., the Y direction) of the lower portion235L, the middle portion235M, and the upper portion235U of the redistribution line pattern235.

In an example embodiment, the shortest length235_Md of the middle portion235M of the redistribution line pattern235may be in a range from about 0.4 micrometers to about 2 micrometers, and less than the longest length235_Ld of the lower portion235L.

The upper portion235U of the redistribution line pattern235may span a third distance d3from the middle portion235M of the redistribution line pattern235. In other words, the third distance d3may correspond to a height of the upper portion235U of the redistribution line pattern235as measured from the top of the middle portion235M.

In an example embodiment, the third distance d3may be about 20% to about 40% of the height235dof the redistribution line pattern235. For example, the third distance d3may be about ⅓ of the height235dof the redistribution line pattern235.

For example, when the height235dof the redistribution line pattern235is about 4.2 micrometers, the height of the upper portion235U of the redistribution line pattern235(i.e., the third distance d3) may be about 1.4 micrometers. However, the height of the upper portion235U of the redistribution line pattern235is not limited to above mentioned heights.

The upper portion235U of the redistribution line pattern235may have a structure having a length in the horizontal direction (e.g., the Y direction) decreasing upwards (i.e., away from the seed layer220).

In an example embodiment, a longest length235_Ud of the upper portion235U of the redistribution line pattern235may be defined as the greatest length among the lengths in the horizontal direction (e.g., the Y direction) of the upper portion235U. The longest length235_Ud of the upper portion235U of the redistribution line pattern235may be greater than the shortest length235_Md of the middle portion235M of the redistribution line pattern235.

In an example embodiment, an upper surface235_US of the redistribution line pattern235may be rounded. In detail, the upper portion235U of the redistribution line pattern235may have the upper surface235_US that is convex upwards. For example, the upper surface235_US of the redistribution line pattern235may have a concave-convex structure (not shown) in which concavities and convexities are repeated.

In an example embodiment, a centerline average height roughness (Ra), or in other words the arithmetic average roughness height (AARH), of the upper surface235_US of the redistribution line pattern235may be about 0.03 micrometers to about 0.09 micrometers. For example, the centerline average height roughness of the upper surface235_US of the redistribution line pattern235may be about 0.05 millimeters.

In a state in which a curve of the upper surface235_US of the redistribution line pattern235in a section having a certain length (e.g., L) is folded around a virtual centerline, the centerline average height roughness may be defined as a value obtained by dividing an area, which is formed by the curve apart from the virtual centerline in the section, by the certain length L.

In a comparative example, a method of forming a redistribution line pattern may include chemically etching at least a portion of the redistribution line pattern. In this case, the centerline average height roughness of the surface of the redistribution line pattern may exceed about 0.5 micrometers.

According to an example embodiment, a method of forming the redistribution line pattern235may skip a stage of chemically etching at least a portion of the redistribution line pattern235, and accordingly, the roughness of the upper surface235_US of the redistribution line pattern235may be about 0.03 micrometers to about 0.09 micrometers.

According to an example embodiment, the lower portion235L of the redistribution line pattern235may have a structure having a horizontal length increasing downwards, and accordingly, a contact area between the redistribution line pattern235and the insulating layer210may increase. As a result, the adhesion between the redistribution line pattern235and the insulating layer210may be enhanced, and delamination between the redistribution line pattern235and the insulating layer210may be decreased.

In addition, because the lower portion235L of the redistribution line pattern235may have a structure having a horizontal length increasing downwards, the center of gravity of the redistribution line pattern235may be more adjacent to the lower portion235L than to the upper portion235U. Accordingly, the structural reliability of the redistribution line pattern235may be increased, and shifting of the redistribution line pattern235may be decreased.

According to an example embodiment, because the middle portion235M of the redistribution line pattern235may have the side wall235M_SS having a shape that is concave towards the virtual centerline C passing through the center of the redistribution line pattern235in the vertical direction, stress applied to the redistribution line pattern235may be dispersed, and accordingly, the structural reliability of the redistribution line pattern235may be increased.

In addition, because the upper portion235U of the redistribution line pattern235may have the upper surface235_US that is convex upwards, a contact area between the upper portion235U and the insulating layer210may increase.

Moreover, the upper surface235_US of the redistribution line pattern235may have a concave-convex structure in which concavities and convexities are repeated, and accordingly, the area of the redistribution line pattern235may be increased. Accordingly, a contact area between the redistribution line pattern235and the insulating layer210may be further increased.

FIG.3illustrates a diagram of a plurality of redistribution line patterns, e.g., first and second redistribution line patterns235_I and235_II, according to embodiments of the inventive concepts.

In an example embodiment, the first and second redistribution line patterns235_I and235_II may extend in an X direction. The first and second redistribution line patterns235_I and235_II may be separated from each other in the Y direction.

The first redistribution line pattern235_I may include a first lower portion235L_I, a first middle portion235M_I, and a first upper portion235U_I. The second redistribution line pattern235_II may include a second lower portion235L_II, a second middle portion235M_II, and a second upper portion235U_II.

In an example embodiment, a lower separation distance sd1between the first lower portion235L_I of the first redistribution line pattern235_I and the second lower portion235L_II of the second redistribution line pattern235_II in the horizontal direction (e.g., the Y direction) may be about 3 micrometers to about 4 micrometers. The lower separation distance sd1may correspond to a distance between a lower surface235_I_LS of the first redistribution line pattern235_I and a lower surface235_II LS of the second redistribution line pattern235_II. The lower separation distance sd1may correspond to the least (or smallest) distance among the distances between the first lower portion235L_I of the first redistribution line pattern235_I and the second lower portion235L_II of the second redistribution line pattern235_II in the horizontal direction (e.g., the Y direction).

In an example embodiment, the lower separation distance sd1between the first redistribution line pattern235_I and the second redistribution line pattern235_II may be about 3.41 micrometers. However, the lower separation distance sd1is not limited to the above mentioned distances.

In an example embodiment, a middle separation distance sd2between the first middle portion235M_I of the first redistribution line pattern235_I and the second middle portion235M_II of the second redistribution line pattern235_II in the horizontal direction (e.g., the Y direction) may be greater than the lower separation distance sd1.

The middle separation distance sd2may correspond to the greatest distance among the distances between the first middle portion235M_I of the first redistribution line pattern235_I and the second middle portion235M_II of the second redistribution line pattern235_II in the horizontal direction (e.g., the Y direction).

In an example embodiment, the middle separation distance sd2may be about 3.3 micrometers to about 4.7 micrometers. In an example embodiment, the middle separation distance sd2between the first redistribution line pattern235_I and the second redistribution line pattern235_II may be about 4.21 micrometers. However, the middle separation distance sd2is not limited to the above mentioned distances.

In an example embodiment, an upper separation distance sd3between the first upper portion235U_I of the first redistribution line pattern235_I and the second upper portion235U_II of the second redistribution line pattern235_II in the horizontal direction (e.g., the Y direction) may be about 4 micrometers to about 6 micrometers. The upper separation distance sd3may correspond to a horizontal distance between the peak of an upper surface235_I_US of the first redistribution line pattern235_I and the peak of an upper surface235_II US of the second redistribution line pattern235_II.

The upper separation distance sd3may correspond to the greatest distance among the distances between the first upper portion235U_I of the first redistribution line pattern235_I and the second upper portion235U_II of the second redistribution line pattern235_II in the horizontal direction (e.g., the Y direction).

In an example embodiment, the upper separation distance sd3may be greater than the middle separation distance sd2. The upper separation distance sd3may be greater than the lower separation distance sd1.

In an example embodiment, the upper separation distance sd3between the first redistribution line pattern235_I and the second redistribution line pattern235_II may be about 4.5 micrometers. However, the upper separation distance sd3is not limited to the above mentioned distances.

According to an example embodiment, the first middle portion235M_I of the first redistribution line pattern235_I and the second middle portion235M_II of the second redistribution line pattern235_II may each have a concave side wall, and accordingly, the middle separation distance sd2may be greater than the lower separation distance sd1. As a result, the occurrence of an electrical short between the first and second redistribution line patterns235_I and235_II may be reduced.

According to an example embodiment, because the middle separation distance sd2between the first and second redistribution line patterns235_I and235_II may be greater than the lower separation distance sd1therebetween, electromigration may be improved.

FIG.4illustrates a cross-sectional view of a redistribution line pattern235_III according to embodiments of the inventive concepts.

Hereinafter, description of the redistribution line pattern235_III ofFIG.4that is redundant to description of the redistribution line pattern235inFIG.2may hereinafter be omitted, and the following description of the redistribution line pattern235_III ofFIG.4will focus on differences with respect to the redistribution line pattern235.

Referring toFIG.4, the redistribution line pattern235_III may include a lower portion235L_III, a middle portion235M_III, and an upper portion235U_III.

The middle portion235M_III of the redistribution line pattern235_III may substantially have a uniform length in the horizontal direction (e.g., the Y direction) along the vertical direction (e.g., the Z direction). In other words, the cross-section of the middle portion235M_III of the redistribution line pattern235_III may have a rectangular shape. For example, in the cross-section of the middle portion235M_III, a side wall235M_SS_III of the middle portion235M_III may have a straight line shape.

Hereinafter, a method S100of manufacturing the semiconductor package10according to an example embodiment is described in detail. Specifically, the method S100of manufacturing the semiconductor package10including the redistribution line pattern235described with reference toFIGS.1to4is described in detail below.

FIG.5illustrates a flowchart of the method S100of manufacturing the semiconductor package10, according to embodiments of the inventive concepts.FIGS.6to17are diagrams of stages in the method S100of manufacturing the semiconductor package10, according to an example embodiment.

Referring toFIG.5, the method S100of manufacturing the semiconductor package10includes forming the insulating layer210on the semiconductor chip100in operation S1100; forming a via pattern hole (H_V inFIG.7), which exposes a portion of the semiconductor chip100, by etching at least a portion of the insulating layer210in operation S1200; forming the seed layer220on the insulating layer210in operation S1300; forming a photoresist layer (PR_L inFIG.9) on the seed layer220in operation S1400; exposing the photoresist layer PR_L such that the amount of hardening of a middle portion of the photoresist layer PR_L is greater than the amount of hardening of the upper portion of the photoresist layer PR_L and the amount of hardening of the lower portion of the photoresist layer PR_L in operation S1500; forming a photoresist pattern (PR_P inFIG.13) having a plurality of line pattern holes (H_L inFIG.13) by developing the photoresist layer PR_L in operation S1600; forming the redistribution pattern230by filling the via pattern hole H_V of the insulating layer210and the line pattern holes H_L of the photoresist pattern PR_P in operation S1700; removing the photoresist pattern PR_P in operation S1800; and removing at least a portion of the seed layer220in operation S1900.

FIG.6illustrates a diagram of operation S1100of forming the insulating layer210on the semiconductor chip100, according to embodiments of the inventive concepts.

Referring toFIGS.5and6, according to an example embodiment, the method S100of manufacturing the semiconductor package10includes forming the insulating layer210on the semiconductor chip100in operation S1100.

In operation S1100, the insulating layer210may cover the chip pad114of the semiconductor chip100. In detail, the semiconductor chip100may be conformally coated with the insulating layer210through spin coating.

In an example embodiment, the insulating layer210may include oxide or nitride. For example, the insulating layer210may include silicon oxide or silicon nitride.

FIG.7illustrates a diagram of operation S1200of forming the via pattern hole H_V by etching at least a portion of the insulating layer210, according to embodiments of the inventive concepts.

Referring toFIGS.5and7, according to an example embodiment, the method S100of manufacturing the semiconductor package10includes forming the via pattern hole H_V, which exposes a portion of the semiconductor chip100, by etching at least a portion of the insulating layer210in operation S1200.

In operation S1200, the insulating layer210may be at least partially etched such that the chip pad114of the semiconductor chip100is exposed. In an example embodiment, a portion of the insulating layer210, which overlaps with the chip pad114in the vertical direction, may be etched in operation S1200.

In an example embodiment, the via pattern hole H_V exposing the chip pad114may be usually formed using a photolithography process or an etching process. However, embodiments are not limited to using a photolithography process or an etching process, and the via pattern hole H_V may be formed using a laser drilling process.

FIG.8illustrates a diagram of operation S1300of forming the seed layer220on the insulating layer210, according to embodiments of the inventive concepts.

Referring toFIGS.5and8, according to an example embodiment, the method S100of manufacturing the semiconductor package10includes forming the seed layer220on the insulating layer210in operation S1300.

In operation S1300, the seed layer220may be conformally formed on a surface of the insulating layer210. In an example embodiment, the seed layer220may be formed on the surface of the insulating layer210using a physical vapor deposition process.

In an example embodiment, operation S1300may include conformally forming a first seed layer on the surface of the insulating layer210and conformally forming a second seed layer on a surface of the first seed layer. In this case, the material of the first seed layer may be different from the material of the second seed layer.

In an example embodiment, the seed layer220may include a plurality of layers. For example, the seed layer220may have a structure in which Cu is stacked on Ti or TiW. However, the material of the seed layer220is not limited to the above mentioned materials.

FIG.9illustrates a diagram of operation S1400of forming the photoresist layer PR_L on the seed layer220, according to embodiments of the inventive concepts.

Referring toFIGS.5and9, according to an example embodiment, the method S100of manufacturing the semiconductor package10includes forming the photoresist layer PR_L on the seed layer220in operation S1400.

In an example embodiment, the photoresist layer PR_L may include a positive photoresist of which the exposed region is removed during a photolithography process. In other words, a portion of the photoresist layer PR_L which is exposed during a photolithography process may be removed during a development process, and an unexposed portion of the photoresist layer PR_L is not removed during the development process.

In operation S1400, the photoresist layer PR_L may be deposited on the insulating layer210as having a uniform thickness using a spin coating process. The photoresist layer PR_L may fill the via pattern hole H_V of the insulating layer210.

In an example embodiment, the photoresist layer PR_L may include a lower portion PR_LL, a middle portion PR_LM, and an upper portion PR_LU, which are sequentially stacked.

FIG.10illustrates a diagram of operation S1500of exposing the photoresist layer PR_L, according to embodiments of the inventive concepts.

Referring toFIGS.5and10, according to an example embodiment, the method S100of manufacturing the semiconductor package10includes exposing the photoresist layer PR_L such that the amount of hardening of the middle portion PR_LM of the photoresist layer PR_L is greater than the amount of hardening of the upper portion PR_LU of the photoresist layer PR_L and the amount of hardening of the lower portion PR_LL of the photoresist layer PR_L in operation S1500.

The photoresist layer PR_L may include the lower portion PR_LL, the middle portion PR_LM, and the upper portion PR_LU. The lower portion PR_LL of the photoresist layer PR_L may correspond to a portion of the photoresist layer PR_L for forming a lower portion (235L inFIG.15) of the redistribution line pattern235. The middle portion PR_LM of the photoresist layer PR_L may correspond to a portion of the photoresist layer PR_L for forming a middle portion (235M inFIG.15) of the redistribution line pattern235. The upper portion PR_LU of the photoresist layer PR_L may correspond to a portion of the photoresist layer PR_L for forming an upper portion (235U inFIG.15) of the redistribution line pattern235.

In an example embodiment, the thicknesses of each of the lower, middle, and upper portions PR_LL, PR_LM, and PR_LU of the photoresist layer PR_L may be about ⅓ of the total thickness of the photoresist layer PR_L. However, the thicknesses of each of the lower, middle, and upper portions PR_LL, PR_LM, and PR_LU of the photoresist layer PR_L are not limited thereto.

In operation S1500, at least a portion of a surface of the photoresist layer PR_L may be exposed by a photomask PM and hardened by light from a light source1100that reaches the photoresist layer PR_L sequentially through the photomask PM and a lens1200.

In this case, the photoresist layer PR_L may be exposed such that the amount of hardening of the middle portion PR_LM of the photoresist layer PR_L is greater than the amount of hardening of the upper portion PR_LU of the photoresist layer PR_L and the amount of hardening of the lower portion PR_LL of the photoresist layer PR_L.

In an example embodiment, the amount of light reaching the middle portion PR_LM of the photoresist layer PR_L may be greater than the amount of light reaching the upper portion PR_LU of the photoresist layer PR_L in operation S1500. In addition, the amount of light reaching the middle portion PR_LM of the photoresist layer PR_L may be greater than the amount of light reaching the lower portion PR_LL of the photoresist layer PR_L in operation S1500.

In an example embodiment, a diffraction radius of light reaching the middle portion PR_LM of the photoresist layer PR_L may be greater than a diffraction radius of light reaching the upper portion PR_LU of the photoresist layer PR_L in operation S1500. In addition, the diffraction radius of light reaching the middle portion PR_LM of the photoresist layer PR_L may be greater than a diffraction radius of light reaching the lower portion PR_LL of the photoresist layer PR_L in operation S1500.

The diffraction radius of light may be defined as a distance, by which light incident to the photoresist layer PR_L is diffracted in the horizontal direction in the photoresist layer PR_L.

In an example embodiment, to control the amount of hardening of the middle portion PR_LM of the photoresist layer PR_L, the shift of the light source1100in the vertical direction (e.g., the Z direction) may be controlled in operation S1500. In other words, the focus of light from the light source1100may be controlled.

FIG.11illustrates a diagram of a stage of exposing the photoresist layer PR_L, according to a comparative example.

Referring toFIG.11, light L′ provided from a light source1100′ may pass through a photomask PM′ and a lens1200′ and reach the photoresist layer PR_L. The light L′ may uniformly harden the middle, upper, and lower portions PR_LM, PR_LU, and PR_LL of the photoresist layer PR_L.

In other words, the amount of light L′ reaching the middle portion PR_LM of the photoresist layer PR_L may be substantially equal to the amount of light L′ reaching the upper portion PR_LU of the photoresist layer PR_L and the amount of light L′ reaching the lower portion PR_LL of the photoresist layer PR_L. In addition, the diffraction radius of the light L′ reaching the middle portion PR_LM of the photoresist layer PR_L may be substantially the same as the diffraction radius of the light L′ reaching the upper portion PR_LU of the photoresist layer PR_L and the diffraction radius of the light L′ reaching the lower portion PR_LL of the photoresist layer PR_L.

A plane, in which a focus P′ of the light L′ is located when the light L′ uniformly hardens the middle, upper, and lower portions PR_LM, PR_LU, and PR_LL of the photoresist layer PR_L, may be defined as a reference plane S′. In other words, when the focus P′ of the light L′ from the light source1100′ is in the reference plane S′, the middle, upper, and lower portions PR_LM, PR_LU, and PR_LL of the photoresist layer PR_L may be uniformly hardened.

FIG.12illustrates a diagram of a stage of exposing the photoresist layer PR_L, according to embodiments of the inventive concepts.

Referring toFIG.12, first light L1and second light L2provided from the light source1100may expose the photoresist layer PR_L such that the amount of hardening of the middle portion PR_LM of the photoresist layer PR_L is greater than the amount of hardening of the upper portion PR_LU of the photoresist layer PR_L and the amount of hardening of the lower portion PR_LL of the photoresist layer PR_L.

In an example embodiment, a focus P1of the first light L1and a focus P2of the second light L2may have an offset from the reference plane S′, which is described with reference toFIG.11, in the vertical direction (e.g., the Z direction). The focus P1of the first light L1may be above the reference plane S′. In other words, the focus P1of the first light L1may have an offset from the reference plane S′ in a +Z direction. The focus P2of the second light L2may be below the reference plane S′. In other words, the focus P2of the second light L2may have an offset from the reference plane S′ in the −Z direction.

In an example embodiment, the position of the focus P1of the first light L1and the position of the focus P2of the second light L2may be controlled by shifting the light source1100in the vertical direction (the Z direction).

In an example embodiment, because each of the focuses P1and P2of the first light L1and second light L2from the light source1100may have an offset from the reference plane S′ in the vertical direction (the Z direction), the amount of first light L1and second light L2reaching the middle portion PR_LM of the photoresist layer PR_L may be greater than the amount of first light L1and second light L2reaching the upper portion PR_LU of the photoresist layer PR_L and the amount of first light L1and second light L2reaching the lower portion PR_LL of the photoresist layer PR_L.

In addition, because each of the focuses P1and P2of the first light L1and second light L2from the light source1100may have an offset from the reference plane S′ in the vertical direction (the Z direction), the diffraction radius of the first light L1and second light L2reaching the middle portion PR_LM of the photoresist layer PR_L may be greater than the diffraction radius of the first light L1and second light L2reaching the upper portion PR_LU of the photoresist layer PR_L and the diffraction radius of the first light L1and second light L2reaching the lower portion PR_LL of the photoresist layer PR_L.

Accordingly, the amount of hardening of the middle portion PR_LM of the photoresist layer PR_L may be greater than the amount of hardening of the upper portion PR_LU of the photoresist layer PR_L and the amount of hardening of the lower portion PR_LL of the photoresist layer PR_L.

FIG.13illustrates a diagram of operation S1600of a stage of developing the photoresist layer PR_L, according to embodiments of the inventive concepts.FIG.14illustrates an enlarged view of region B inFIG.13.

Referring toFIGS.5,13, and14, according to an example embodiment, the method S100of manufacturing the semiconductor package10includes forming the photoresist pattern PR_P having the line pattern holes H_L by developing the photoresist layer PR_L in operation S1600.

The portion of the photoresist layer PR_L exposed by the photolithography process may be removed by a development process in operation S1600. For example, a developer may be provided to the photoresist layer PR_L and may remove hardened portions of the photoresist layer PR_L. Accordingly, the photoresist pattern PR_P having the line pattern holes H_L may be formed.

In an example embodiment, each of the line pattern holes H_L of the photoresist layer PR_L may overlap in the vertical direction with the via pattern hole V_H of the insulating layer210.

As described above, because the amount of hardening of the middle portion PR_LM of the photoresist layer PR_L may be greater than the amount of hardening of the upper portion PR_LU of the photoresist layer PR_L and the amount of hardening of the lower portion PR_LL of the photoresist layer PR_L, a removal amount of the photoresist layer PR_L during the development process may be less in the middle portion PR_LM than in the upper portion PR_LU and the lower portion PR_LL.

In an example embodiment, a length d_LM of a middle portion H_LM of a line pattern hole H_L may be less than a length d_LU of an upper portion H_LU of the line pattern hole H_L. The length d_LM of the middle portion H_LM of the line pattern hole H_L may be less than a length d_LL of a lower portion H_LL of the line pattern hole H_L.

In other words, a first photoresist pattern PR_P1between two adjacent line pattern holes H_L may include an upper portion PR_P1U, a middle portion PR_P1M, and a lower portion PR_P1L.

In an example embodiment, a horizontal length of the middle portion PR_P1M of the first photoresist pattern PR_P1may be greater than a horizontal length of the upper portion PR_P1U of the upper portion PR_P1U and a horizontal length of the lower portion PR_P1L of the first photoresist pattern PR_P1.

In an example embodiment, the flow rate of a developer provided to develop the photoresist layer PR_L may also be controlled in operation S1600.

In an example embodiment, operation S1600may include forming the upper portion H_LU of the line pattern hole H_L by providing a developer to the upper portion PR_LU (inFIG.10) of the photoresist layer PR_L (inFIG.10) at a first flow rate, forming the middle portion H_LM of the line pattern hole H_L by providing the developer to the middle portion PR_LM (inFIG.10) of the photoresist layer PR_L at a second flow rate that is less than the first flow rate, and forming the lower portion H_LL of the line pattern hole H_L by providing the developer to the lower portion PR_LL (inFIG.10) of the photoresist layer PR_L at a third flow rate.

The second flow rate of a developer for removing the middle portion PR_LM of the photoresist layer PR_L may be less than the first flow rate of a developer for removing the upper portion PR_LU of the photoresist layer PR_L, and accordingly, a removal amount of the middle portion PR_LM of the photoresist layer PR_L by the developer may be less than a removal amount of the upper portion PR_LU of the photoresist layer PR_L by the developer.

In an example embodiment, the third flow rate of a developer for removing the lower portion PR_LL of the photoresist layer PR_L may be substantially equal to the second flow rate of a developer for removing the middle portion PR_LM of the photoresist layer PR_L. In this case, the amount of hardening of the lower portion PR_LL of the photoresist layer PR_L may be less than the amount of hardening of the middle portion PR_LM of the photoresist layer PR_L, and accordingly, a removal amount of the lower portion PR_LL of the photoresist layer PR_L may be greater than a removal amount of the middle portion PR_LM of the photoresist layer PR_L.

FIG.15illustrates a diagram of operation S1700of forming the redistribution pattern230, according to embodiments of the inventive concepts.

Referring toFIGS.5and15, according to an example embodiment, the method S100of manufacturing the semiconductor package10includes forming the redistribution pattern230by filling a plurality of via pattern holes H_V of the insulating layer210and a plurality of line pattern holes H_L of the photoresist pattern PR_P in operation S1700.

In an example embodiment, operation S1700may include forming a redistribution via pattern233(seeFIG.1) by filling a via pattern hole H_V of the insulating layer210, and forming a redistribution line pattern235by filling a line pattern hole H_L of the photoresist pattern PR_P.

In an example embodiment, the forming of the redistribution line pattern235may include performing a plating process using at least a portion of the seed layer220, which is exposed by the photoresist pattern PR_P.

As described above with reference toFIGS.2and3, the redistribution line pattern235formed in operation S1700may include the lower portion235L, the middle portion235M, and an upper portion235U.

According to an example embodiment, the lower portion235L of the redistribution line pattern235may have a structure having a horizontal length increasing downwards, and accordingly, a contact area between the redistribution line pattern235and the insulating layer210may increase. As a result, the adhesion between the redistribution line pattern235and the insulating layer210may be enhanced, and delamination between the redistribution line pattern235and the insulating layer210may be decreased.

In addition, because the lower portion235L of the redistribution line pattern235may have a structure having a horizontal length increasing downwards, the center of gravity of the redistribution line pattern235may be more adjacent to the lower portion235L than to the upper portion235U. Accordingly, the structural reliability of the redistribution line pattern235may be increased, and the shift of the redistribution line pattern235may be decreased.

According to an example embodiment, because the middle portion235M of the redistribution line pattern235may have the side wall235M_SS having the shape that is concave towards the virtual centerline C passing through the center of the redistribution line pattern235in the vertical direction, stress applied to the redistribution line pattern235may be dispersed, and accordingly, the structural reliability of the redistribution line pattern235may be increased.

In addition, because the upper portion235U of the redistribution line pattern235may have the upper surface235_US that is convex upwards, a contact area between the upper portion235U and the insulating layer210may increase.

Moreover, the upper surface235_US (seeFIG.2) of the redistribution line pattern235may have the concave-convex structure in which concavities and convexities are repeated, and accordingly, the area of the redistribution line pattern235may be increased. Accordingly, a contact area between the redistribution line pattern235and the insulating layer210may be further increased.

FIG.16illustrates a diagram of operation S1800of removing the photoresist pattern PR_P, according to embodiments of the inventive concepts.

Referring toFIGS.5and16, according to an example embodiment, the method S100of manufacturing the semiconductor package10includes removing the photoresist pattern PR_P in operation S1800.

In an example embodiment, the photoresist pattern PR_P may be removed by an ashing process and a stripping process. However, the method of removing the photoresist pattern PR_P is not limited to ashing and stripping.

FIG.17illustrates a diagram of operation S1900of removing at least a portion of the seed layer220, according to embodiments of the inventive concepts.

Referring toFIGS.5and17, according to an example embodiment, the method S100of manufacturing the semiconductor package10includes removing at least a portion of the seed layer220in operation S1900.

A portion of the seed layer220which does not vertically overlap with the redistribution pattern230may be removed in operation S1900. In other words, the seed layer220that vertically overlaps with the redistribution pattern230may not be removed.

While the inventive concepts have been particularly shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the following claims.