Quantum device fabrication method

The present invention is directed to a method of fabricating quantum devices such as quantum boxes and quantum wires measuring as small as several tens of nanometers utilizing selectivity based on crystal plane orientation. A substrate is provided with a surface having an (100) crystal plane orientation. A first layer of a semiconductor material, such as AlGaAs or GaAs, is epitaxially grown on the surface of the substrate as a trapezoid having a (100) crystal plane orientation top surface and a (111)B crystal plane orientation side surface around the top surface. An As.sub.2 beam is used for MBE growth of a second layer of GaAs or InGaAs on the (100) surface of the first layer. The growth of the third layer on the (111)B crystal plane orientation region is prevented by an As trimer structure such that growth only takes place at the (100) crystal plane orientation region.

FIELD OF THE INVENTION 
The present invention relates to a quantum device fabrication method, and, 
more particularly, to a method of using crystal growth to fabricate 
quantum devices such as quantum wires and quantum boxes. 
BACKGROUND OF THE INVENTION 
In recent years attention has focussed on quantum devices with ultrafine 
structures, such as quantum wires and quantum boxes, and on methods of 
fabricating such devices. Quantum devices are well known and are devices 
in which carriers (electrons and/or holes) are confined into a small part 
of the device in one, two and three dimensions, respectively. The 
dimensions of such devices are sufficiently small, in the order of 10 nm, 
so as to be comparable to the wavelength of electrons and holes. Thus, the 
electrons and holes behave not only as particles, but also as waves. 
Fabricating methods that have been used include those involving 
combinations of wet and dry etching techniques. Ion-beam technology has 
also been used to fabricate submicron quantum devices. 
The application of selective epitaxial growth techniques for the 
fabrication of nanometric-scale capillary tubes and boxes has been 
disclosed, for example in an article in APPLIED PHYSICS LETTERS, Vol. 56, 
Pg. 2642 (1990), by J. A. Lebens, C. S. Tsai, K. J. Vabala and T. F. 
Kuech. This article describes using metal-organic vapor-phase epitaxy to 
grow a layer of AlGaAs on a GaAs substrate with a (100) oriented surface, 
and using a SiN mask layer and electron-beam lithography and etching to 
form tubes from 90 nm to 300 nm wide and boxes 70 nm to 300 nm in 
diameter. However, constraints relating to etching ratios and the size of 
the ion beam impose limits on the degree of submicron fabrication 
achievable with such techniques. This makes it difficult to fabricate 
quantum wires and boxes that are finer and have a good interface. 
SUMMARY OF THE INVENTION 
The present invention provides a method of fabricating ultrafine quantum 
devices that are as small as several tens of nanometers and also have a 
good interface structure. 
The method of the present invention for making a quantum device comprises 
forming on a surface of a substrate of a semiconductor material a first 
semiconductor layer having an ultrafine region. The first layer has a 
first surface of a first crystalline plane orientation and a second 
surface of a second crystalline plane orientation around the first 
surface. A second semiconductor layer is formed only on the first surface 
of the first semiconductor layer using an epitaxy deposition technique 
which substantially grows the second semiconductor layer only on the first 
surface with the first crystalline plane orientation based on differences 
in selectivity between the first and second crystalline plane orientation. 
The invention will be better understood from the following more detailed 
description taken with the accompanying drawings and claims.

DETAILED DESCRIPTION 
Referring initially to FIGS. 1-4, there are shown cross-sectional views 
illustrating steps of a method in accordance with the present invention. 
With reference first to FIG. 1, using dry etching or the like, a region 1a 
0.5 um wide and 1 .mu.m high in a reverse mesa direction is formed on a 
GaAs substrate 1 having a surface lb with a (100) crystal plane 
orientation. The method continues as shown in FIG. 2. Using this GaAs 
substrate 1 with the (100) crystal plane orientation, molecular beam 
epitaxy (MBE) with a As.sub.4 beam, which is produced by means of a normal 
K cell, is used to form on the substrate surface lb a first semiconductor 
layer 2 of A1.sub.0.3 Ga.sub.0.7 As which is about 200 nm in thickness. 
The A10.3Ga.sub.0.7 As first layer 2 is formed as a trapezoid bounded by a 
(111)B crystal plane orientation side surface region 2a around a (100) 
crystal plane orientation top surface region 2b. The (111)B surface is the 
(111) oriented plane of the topmost GaAs surface on which Ga appears. 
As shown in FIG. 3, a second layer 3 of GaAs having a thickness of about 20 
nm is then formed on the surface region 2b. This is achieved by MBE with 
an As.sub.2 beam, for example, obtained by using a solid As source cracker 
cell to crack an As.sub.4 beam, and a beam of Ga. As the surface of the 
(111)B crystal plane orientation surface region 2a of the A10.3Ga.sub.0.7 
As layer 2 is stabilized by an As trimer structure, no growth of GaAs 
takes place on the surface region 2a during the MBE process because of the 
very small coefficient of adhesion of Ga atoms. 
The As trimer structure formed on the GaAs (111)B surface is described in 
an article in PHYSICAL REVIEW LETTERS, Vol. 65, Pg. 452 (1990) by D. K. 
Biegelsen, R. D. Bringans, J. E. Northrop, and L. E. Swarts. This article 
describes an As-rich (2.times.2) structure constituted by an 
As-atom-attractive trimer. Ga atoms adhere to the A1.sub.0.3 Ga.sub.0.7 As 
layer 2 top surface region 2b with the (100) crystal plane orientation. 
This produces a growth of GaAs. The result is the formation of a GaAs 
layer 3 only over the top surface region 2b. Finally, as shown in FIG. 4, 
a switchover A1.sub.0.3 Ga.sub.0.7 As over the GaAs second layer 3 and the 
side surface region 2a of the layer 2. The third layer 4 produces with the 
GaAs second layer 3 a quantum device. A quantum wire is obtained by 
extending the GaAs second layer 3 perpendicularly relative to the drawing 
sheet. 
By adjusting the growth time of the A1.sub.0.3 Ga.sub.0.7 As first layer 2, 
the width W of the (100) crystal plane orientation top surface region 2b 
can be reduced to below 0.5 um, to 50 nm for example. These conditions 
therefore can produce a GaAs wire 50 nm wide and 20 nm thick. However, the 
size of the ultrafine region can be changed in accordance with 
requirements by changing the thickness of the A1.sub.0.3 Ga.sub.0.7 As 
first layer 2. Also, while this embodiment has been described with 
reference to GaAs, examples of other materials that can be used include 
InGaAs, InAlGaP, and InGaAsP. 
Instead of an As.sub.2 beam obtained by means of a solid cracker cell, the 
quantum devices can also be fabricated using an As.sub.2 or As beam 
obtained from a base material such as AsH.sub.3 or the like. When in this 
case P system material is used, a P.sub.2 beam may be used in place of an 
As.sub.2 beam and a P.sub.4 beam in place of an As.sub.4 beam. While such 
group V element beams are derived from a solid source, it is also possible 
to use a metal-organic or other such gas source. In the case of both a 
group III or group V element, when a gas source is used the elimination 
reaction from the surface is enhanced. This increases the 
crystal-orientation-based selectivity, enabling devices with an even 
better interface to be obtained. 
Referring now to FIGS. 5-8, there are shown cross-sectional views 
illustrating steps of another method in accordance with the present 
invention. With reference first to FIG. 5, a 50 nm thick SiN.sub.x masking 
layer 22 is formed on a surface 21a of a GaAs substrate 21 with the 
surface 21a having a (100) crystal plane orientation. The masking layer 22 
is then patterned and etched in a conventional manner to provide it with 
an opening 22a therein which leaves a region 0.5 um wide of the surface 
21a exposed in a reverse mesa direction. As is shown in FIG. 6, using this 
GaAs substrate 21 with the (100) crystal plane orientation surface 21a, 
MBE using an As.sub.4 beam is used to form a 200 nm thick GaAs first layer 
23. This growth produces the layer 23 having a portion in the form of a 
trapezoidal like structure which is bounded by a (111)B crystal plane 
orientation side surface region 23a and a (100) crystal plane orientation 
top surface region 23b. 
As shown in FIG. 7, a 10 nm thick In.sub.0.2 Ga.sub.0.8 As second layer 24 
is then formed on the surface region 23b by MBE with an As.sub.2 beam 
obtained by cracking AsH.sub.3 and beams of Ga and In. As the surface of 
the (111)B crystal plane orientation side surface region 23a of the GaAs 
layer 23 is stabilized by an As trimer structure, there is no growth of 
In.sub.0.2 Ga.sub.0.8 As thereon. MBE growth of InGaAs does take place at 
the (100) crystal plane orientation top surface region 23b. This forms the 
InGaAs layer 24 only over the (100) crystal plane orientation top surface 
region 23b. As is shown in FIG. 8, a switchover is made to an As.sub.4 
beam to form a GaAs third layer 25 over the InGaAs second layer 24 and the 
side surface region 23a of the GaAs first layer 23. This produces a 
quantum device with In.sub.0.2 Ga.sub.0.8 As layer 24. 
In the same way as in the method illustrated in FIGS. 1-4, by adjusting the 
growth time of the GaAs first layer 23 the width of the In.sub.0.2 
Ga.sub.0.8 As layer 24 can be reduced to around 50 nm, providing a quantum 
wire with an extremely good interface. Although the method illustrated in 
FIGS. 5-8 has been described with reference to a SiN.sub.x 22 having a 
thickness of 50 nm, the thickness can be changed as required. Similarly, 
the invention is not limited to the use of SiN.sub.x but may use other 
materials such as SiO.sub.2, for example. The size of the ultrafine region 
may be changed as required by suitably adjusting the thickness of the GaAs 
layer 23 or the width of the opening 22a formed by the SiN.sub.x masking 
layer 22 and the thickness of the SiN.sub.x masking layer 22 itself. 
Referring now to FIGS. 9-12, there are shown cross-sectional views 
illustrating the steps of still another method in accordance with the 
present invention. As shown in FIG. 9, first, a region 31a 0.5 .mu.m wide 
and 1 .mu.m high in a reverse mesa direction is formed on a GaAs substrate 
31 having a surface 31b with a (100) crystal plane orientation. As shown 
in FIG. 10, using this GaAs substrate 31 with the surface 31b having a 
(100) crystal plane orientation, a 200 nm thick A1.sub.0.3 Ga.sub.0.7 As 
first layer 32 is then formed on the surface 31b. This can be achieved by 
migration enhancement epitaxy (MEE) with an As.sub.2 beam, for example, 
obtained by using a solid As source cracker cell to crack an As.sub.4 
beam. Thus, the A1.sub.0.3 Ga.sub.0.7 As first layer 32 is formed as a 
trapezoid bounded by a (111)B crystal plane orientation side surface 
region 32a and a (100) crystal plane orientation top surface region 32b. 
As shown in FIG. 11, a 20 nm thick GaAs second layer 33 is then formed on 
the surface region 32b by As.sub.2 beam MBE. As the surface of the (111)B 
crystal plane orientation side surface region 32a of the A1.sub.0.3 
Ga.sub.0.7 As first layer 32 is stabilized by an As trimer structure, no 
growth of GaAs takes place on the side surface region 32a during the MBE 
process because of the very small coefficient of adhesion of Ga atoms. On 
the other hand, GaAs does grow on the top surface region 32b of the 
A1.sub.0.3 Ga.sub.0.7 As first layer 32 with the (100) crystal plane 
orientation. The result, as shown in FIG. 11, is that the GaAs second 
layer 33 forms only over the top surface region 32b of the A1.sub.0.3 
Ga.sub.0.7 As 32 having the (100) crystal plane orientation. 
As shown in FIG. 12, an As.sub.2 beam MEE is used to form an A1.sub.0.3 
Ga.sub.0.7 As third layer 34. No growth of GaAs takes place on the side 
surface region 32a. No, growth of GaAs takes place on the side surface 
region 32a. With this MEE process the use of a group III element 
alternates with the use of a group V element. Therefore, the surface of 
the (1114)B crystal plane orientation side surface region of the 
A1.sub.0.3 Ga.sub.0.7 As first layer 32 is not stabilized by an As trimer 
structure formed thereon. As a result, A1.sub.0.3 Ga.sub.0.7 As grows on 
the (111)B crystal plane orientation side surface region 32a as well as 
over the GaAs second layer 33. This forms a quantum device enclosed by the 
A1.sub.0.3 Ga.sub.0.7 As third layer 34 as shown in FIG. 12. Details of 
the MEE process are provided in the JAPANESE JOURNAL OF APPLIED PHYSICS, 
Vol. 28 (1989), pp 200-209. 
By adjusting the growth time of the A1.sub.0.3 Ga.sub.0.7 As first layer 
32, the width W of the (100) crystal plane orientation top surface region 
32b can be reduced to 50 nm or so. This enables the production of a 
quantum wire having a good interface 50 nm wide and 20 nm thick. 
It is to be appreciated and understood that the specific embodiments of the 
invention are merely illustrative of the general principles of the 
invention. Various modifications may be made consistent with the 
principles set forth. For example, as previously indicated, the 
composition of the various layers may be changed as well as the specific 
epitaxy techniques for growing the layers.