Liquid crystal display backplane layouts and addressing for non-standard subpixel arrangements

Liquid crystal display backplane layouts and addressing for non-standard subpixel arrangements are disclosed. A liquid crystal display comprises a panel and a plurality of transistors. The panel substantially comprises a subpixel repeating group having an even number of subpixels in a first direction. Each thin film transistor connects one subpixel to a row and a column line at an intersection in one of a group of quadrants. The group comprises a first quadrant, a second quadrant, a third quadrant and a fourth quadrant, wherein the thin film transistors are formed in a backplane structure adjacent to intersections of the row and column lines. The thin film transistors are also substantially formed in more than one quadrant in the backplane structure.

RELATED APPLICATIONS

The present application is related to commonly owned (and filed on even date) United States Patent Applications: (1) U.S. Patent Publication No. 2004/0246213 (“the '213 application”) entitled “DISPLAY PANEL HAVING CROSSOVER CONNECTIONS EFFECTING DOT INVERSION”; (2) U.S. Patent Publication no. 2004/0246381 (“the '381 application”), entitled “SYSTEM AND METHOD OF PERFORMING DOT INVERSION WITH STANDARD DRIVERS AND BACKPLANE ON NOVEL DISPLAY PANEL LAYOUTS”; (3) U.S. Patent Publication No. 2004/0246278 (“the '278 application”), entitled “SYSTEM AND METHOD FOR COMPENSATING FOR VISUAL EFFECTS UPON PANELS HAVING FIXED PATTERN NOISE WITH REDUCED QUANTIZATION ERROR”; (4) U.S. Patent Publication No. 2004/0246279 (“the '279 application”), entitled “DOT INVERSION ON NOVEL DISPLAY PANEL LAYOUTS WITH EXTRA DRIVERS”; and (5) U.S. Patent Publication No. 2004/0246280 (“the '280 application”), entitled “IMAGE DEGRADATION CORRECTION IN NOVEL LIQUID CRYSTAL DISPLAYS,” which are hereby incorporated herein by reference.

BACKGROUND

DETAILED DESCRIPTION

Reference will now be made in detail to implementations and embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

FIG. 1Ashows a conventional RGB stripe structure on panel100for an Active Matrix Liquid Crystal Display (AMLCD) having thin film transistors (TFTs)116to activate individual colored subpixels—red104, green106and blue108subpixels respectively. As may be seen, a red, a green and a blue subpixel form a repeating group of subpixels102that comprise the panel.

As also shown, each subpixel is connected to a column line (each driven by a column driver110) and a row line (e.g.112and114). In the field of AMLCD panels, it is known to drive the panel with a dot inversion scheme to reduce crosstalk and flicker.FIG. 1Adepicts one particular dot inversion scheme—i.e. 1×1 dot inversion—that is indicated by a “+” and a “−” polarity given in the center of each subpixel. Each row line is typically connected to a gate (not shown inFIG. 1A) of TFT116. Image data—delivered via the column lines—are typically connected to the source of each TFT. Image data is written to the panel a row at a time and is given a polarity bias scheme as indicated herein as either ODD (“O”) or EVEN (“E”) schemes. As shown, row112is being written with ODD polarity scheme at a given time while row114is being written with EVEN polarity scheme at a next time. The polarities alternate ODD and EVEN schemes a row at a time in this 1×1 dot inversion scheme.

FIG. 1Bdepicts another conventional RGB stripe panel having another dot inversion scheme—i.e. 1×2 dot inversion. Here, the polarity scheme changes over the course of two rows—as opposed to every row, as in 1×1 dot inversion. In both dot inversion schemes, a few observations are noted: (1) in 1×1 dot inversion, every two physically adjacent subpixels (in both the horizontal and vertical direction) are of different polarity; (2) in 1×2 dot inversion, every two physically adjacent subpixels in the horizontal direction are of different polarity; (3) across any given row, each successive colored subpixel has an opposite polarity to its neighbor. Thus, for example, two successive red subpixels along a row will be either (+,−) or (−,+). Of course, in 1×1 dot inversion, two successive red subpixels along a column with have opposite polarity; whereas in 1×2 dot inversion, each group of two successive red subpixels will have opposite polarity. This changing of polarity decreases noticeable visual defects that occur with particular images rendered upon an AMLCD panel.

FIG. 2shows a panel comprising a repeat subpixel grouping202, as further described in the '225 application. As may be seen, repeat subpixel grouping202is an eight subpixel repeat group, comprising a checkerboard of red and blue subpixels with two columns of reduced-area green subpixels in between. If the standard 1×1 dot inversion scheme is applied to a panel comprising such a repeat grouping (as shown inFIG. 2), then it becomes apparent that the property described above for RGB striped panels (namely, that successive colored pixels in a row and/or column have different polarities) is now violated. This condition may cause a number of visual defects noticed on the panel—particularly when certain image patterns are displayed. This observation also occurs with other novel subpixel repeat grouping—for example, the subpixel repeat grouping in FIG. 1 of the '179 application—and other repeat groupings that are not an odd number of repeating subpixels across a row. Thus, as the traditional RGB striped panels have three such repeating subpixels in its repeat group (namely, R, G and B), these traditional panels do not necessarily violate the above noted conditions. However, the repeat grouping ofFIG. 2in the present application has four (i.e. an even number) of subpixels in its repeat group across a row (e.g. R, G, B, and G). It will be appreciated that the embodiments described herein are equally applicable to all such even modulus repeat groupings.

In order to affect improved performance, several embodiments are herein described. A first embodiment of an AMLCD panel300is shown inFIG. 3. Box302encloses four TFTs116that drive their associated four colored subpixels. As may be seen, the gates of each TFT116are connected to a row line in such a manner as to have same colored subpixels—successively staggered—across each row affect opposite polarity. This effect is shown inFIG. 4, for example, with red subpixels408,410, and412, etc. receiving (−, +, −, . . . ) polarities during a row write to line404. The same effect is shown for blue subpixels across line404. One possible benefit of this condition is that any parasitic capacitances (for example, as between the gate and the drain of the TFT, CGD, and as between the pixel and the gate line, CG-Pixel·) that occur across a row/gate line with are minimized by having the same number of “+” and “−” polarities connected to the row/gate line.

It is further seen inFIG. 3that the TFTs116in repeating group302are formed at the intersection of a pair of row and column lines at a given quadrant of the subpixel. For example, the upper red subpixel in group302has its TFT formed in the first quadrant; while the upper green subpixel has its TFT formed in the third quadrant. To affect a dot inversion scheme on a subpixel repeating group of an even number of subpixels in a row or column direction, one embodiment is to find a suitable remapping of the TFT backplane from their usual placement in one quadrant, so that the remapping may use any number of quadrants greater than one.

FIG. 4depicts how panel300operates over the course of two successive row-writes. During the first row-write (panel300on the left hand side), row402sends an active gate signal down to the connected TFTs and their associated subpixels (shown in BOLD hatching) on an EVEN cycle. In this case, all of the green subpixels in two rows are activated. However, as may be seen, the TFTs have been advantageously replaced so that two bordering green TFTs in the vertical direction has opposite polarities. So, for example, green subpixel406has a “+” polarity; while green subpixel408has a “−” polarity. Additionally, as may be seen, the polarities of all of the green subpixels connected to row line402are balanced—i.e. the number of “+” polarity green subpixels equals the number of “−” polarity green subpixels.

During the next row-write (as shown in panel300on the right hand side), row line404sends an active gate signal to its connected TFTs and their associated subpixels (also shown in BOLD hatching) on an ODD cycle. Again, given the replacement of the TFTs, each two adjacent subpixels in the vertical direction have opposite polarity. Additionally, as described above, same colored subpixels that are successively staggered along a row line are of opposite polarity.

Yet another embodiment comprising a TFT replacement (i.e. off from the traditional manner of consistently placing TFTs in a single position relative to the subpixels—such as the upper left hand corner) is shown inFIG. 5. The repeat grouping of TFTs in this arrangement are shown as block502. With this arrangement, similar corrective polarity conditions as noted forFIGS. 3 and 4are found with the TFT placement ofFIG. 5. For example, along row/gate line504, every two red subpixels alternate polarity—e.g. red subpixels510and512have “+” polarity; while red subpixels514and516have “−” polarity. As will be discussed in greater detail below, there are a number of different TFT placements that will achieve the same effects. Each such TFT placement (or TFT “remapping”) is contemplated within the scope of the present invention and, as such, the present invention should not be limited to any particular TFT placement or remapping.

FIG. 6is yet another embodiment of TFT remapping on panel600that may take into account additional parasitic capacitance effects between pixel and the CSelectrode602. In this case, two successive row/gate lines are driven by a given polarity scheme (O or E). The polarity of each subpixel is shown in its center. It will be noted that along any given row (and hence along a given CSline), successive same colored subpixels alternate polarity.

Another TFT remapping that may produce similar beneficial effects is shown inFIG. 7. In this case, the panel700is partitioned into sections (e.g.702,704) that place the TFTs of their associated subpixels in corners such that the polarity at the two columns at the partition line repeats. Thus, for example, column710and712have the same polarities of subpixels going down the respective columns. If the number of subpixels across a row defining a given partition is small enough, the accumulated parasitic capacitances in that partition may be sufficiently below a visually detectable (or at least manageable) level. This partitioning across a panel might occur a number of times in order to keep those parasitics at a low enough level. As an alternative embodiment, this panel could have a 1×2 dot inversion scheme—thereby effectively solving vertical crosstalk (i.e. whereby same colored subpixels have same polarity in a given column).

FIGS. 8 through 15outline a general procedure for developing many different embodiments of TFT remappings that may effect reduced parasitic capacitance in an panel having even modulus for a subpixel repeating group. Starting with a basic grid800ofFIG. 8, a repeating subpixel grouping902is placed upon the grid inFIG. 9. It will be appreciated that, as noted above, any repeating group would suffice here; but preferably one with an even number of subpixels across a row. A dot inversion scheme is selected in FIG.10—in this case, a 1×2 dot inversion scheme is selected with two polarity schemes or “phases”—O and E. Additionally, these two phases are repeated for every two row/gate lines—O, O, E, E, etc. If 1×1 dot inversion were desired, then the phases would alternate every row/gate line.

Any symmetries in the repeat grouping are now to be considered. For example, inFIG. 11, it is noted that every other column is a line of blue subpixels. Thus, a possible symmetry to consider is in the other columns of alternating red and green subpixels. Now, consider all possible combinations of polarities for the first two subpixel in the columns of interest. InFIG. 11for example, the first two red and green subpixels could assume a set of four possible polarity values. In general, if the first N subpixels in relevant rows or columns are considered, then 2Ncombinations of polarities may or should be considered.

Other symmetries may also be taken into consideration. InFIG. 12, the polarities in one of the columns of same colored subpixels are considered. A listing of possible polarities are shown in list1202for the second column of blue subpixels—and the first four such blue subpixels in the column are considered. The list could be exhaustive of the possibilities of polarities and certainly another number other than four may be considered. As it may be advantageous to balance the polarities down a given column—all of those possibilities with a balanced number of polarities are noted as “OK”. One OK combination1204is selected, solely for exemplary purposes, for grid1206.

FIG. 13shows an initial selection of TFT placements on the grid. Initially, for optional visual aiding, the polarities accorded to each intersection of a row/gate line and a column/data line are placed on the grid—as either a “+” or a “−”. It is noted that any TFT placed in any quadrant around an intersection point will effect the same polarity on its associated subpixel. As for the subpixels inFIG. 12that have been assigned a polarity, there is a degree of freedom in selecting which intersection to place the TFT. For example, red subpixel1302has been assigned a “+” polarity and there are two possible intersections1304and1306at which to place its associated TFT. For exemplary purposes, the TFT is selected to be placed at intersection1304. Of course, the placement of TFTs could be affected by many possible factors—for example, the desire to minimally impact design rules, to minimize ill effect (e.g. parasitic capacitances), etc. As may be seen, the other TFTs for the polarity-assigned subpixels inFIG. 13have also been placed—as one possible embodiment and selection thereof. Of course, other embodiments/selections are also possible.

FIG. 14extends this process of TFT placement to the remaining blue subpixels on the grid. Although there are other selections possible, this particular selection was made with the idea of balancing the polarities across any given row. As may be seen, the blue subpixels polarities balance out across any given row/gate line.FIG. 15fills in the remaining red and green subpixel TFT placements. One possible goal is to assign the remaining TFTs in a grouping that may be repeated across the entire panel to form the backplane. One such repeat grouping is1502inFIG. 15. Grouping1502is an 8×4 subpixel grouping that seeks to balance polarities across all subpixels in the row and column directions, as well as balancing polarities within each single color subpixel sub-grid in the row and column directions. It will be appreciated that by following the general procedure outlined above and exploiting the various degrees of freedom in design choice, many possible TFT placements or remappings are possible to develop a suitable TFT grid.

FIG. 16Ashows one possible TFT remapping grid effecting a 1×2 dot inversion scheme.FIG. 16Bshows how the remapping grid might be implemented on a panel with a little greater detail. TFT1602and1604—with TFT1602implemented at the bottom of a pixel area and TFT1604at the top of a pixel area—are possibly susceptible to some uneven effects that might be introduced during the manufacturing process. For example, if the gate metal or pixel electrode masks are translated upwards during manufacturing, then it may be possible for reduced parasitic capacitance for TFT1602and its associated pixel and for increased parasitic capacitance for TFT1604and its associated pixel. If the errors in parasitics are out of tolerance bounds, then the yield of manufacturing such panels with unconventional TFT remappings might decrease. Thus, it may desirable to redesign the TFT structure as designed below in order to abate any uneven effects as noted above.

FIG. 16Cshows another embodiment of a panel having a novel subpixel repeating group1650. In this group, the pattern looks like:R G B GR G B GB G R GB G R G

When a 1×1 dot inversion scheme is applied to this repeat grouping, vertical crosstalk problems are solved. Additionally, all the TFTs may be place on the same side of the pixel structure—which may reduce some parasitic effects or imbalances.

One known attempt to correct for TFT misalignments and any associated increase in parasitic capacitance is found in U.S. Pat. No. 5,191,451 to Katayama et al.FIG. 17Adepicts the “double TFT” arrangement1700of the '451 patent. Source line1704connects to the TFT via source electrode1706. Two gate electrodes1708are connected to gate line1702. Two drain electrodes1710connect to the pixel and are formed such that the two gate electrodes1708affect conduction from the source electrode to the drain electrodes when activated. It is noted that there are two crossover regions1712that are connected to TFT may produce additional parasitic capacitance between the gate and the source. As discussed in the '451 patent, any vertical misalignment of the TFT placement is somewhat corrected by this double TFT arrangement as is discussed therein.FIGS. 17B and 17Cprovide different alternative embodiments for the double TFT structure to the one shown inFIG. 17A. This structure will enable reduced source to gate capacitance, which can cause crosstalk in certain images. The gate to drain crossover will be less damaging to image quality. One advantage of the embodiment ofFIG. 17Cis that there is only one crossover1732that may reduce parasitic capacitance.

Another manner of reducing the ill effects of TFT misalignment is shown in U.S. Pat. No. 5,097,297 to Nakazawa.FIG. 18depicts a TFT1800made in the manner taught in the '297 patent. As may be seen inFIG. 18, gate line1802delivers the gate signal to gate electrode1808. Source line1804sends image data to source electrodes1806. When the gate electrode is activated, the image data is transferred to the pixel via the drain electrode1810. It is noted that this TFT embodiment contains only one gate crossover1812which aids in reducing parasitic capacitance.

Another set of TFT redesigns are shown inFIGS. 19A and 19B,20A and20B, and21A and21B to handle the unevenness of parasitic capacitance that might be introduced by the above described TFT remapping. As TFTs are remapped on the panel, it is possible for some TFTs on the panel to be implemented in different corners or quadrants of a pixel area. For example, some TFTs may be constructed in the upper left hand corner of the pixel area, some in the upper right hand corner of the pixel area and so on. If all such TFTs were constructed the same way, then it would be likely that the source-drain orientation would be reversed for left hand corner and right hand corner implementation. Such non-uniformity of construction might introduce uneven parasitic capacitance in the case of a given TFT misalignment.

FIGS. 19A and 19Bshow TFT structures in a reverse orientation and a normal orientation, respectively. For exemplary purposes, TFT1904is constructed within the upper left hand corner of its associated pixel in the usual manner—i.e. without any crossovers to avoid any introduced parasitic capacitance. It is noted that the source (S) and drain (D) electrodes are placed in a left-to-right fashion. TFT1902is shown constructed in the upper right hand corner of a pixel area in a reverse orientation—i.e. a crossover1914from source line1906is constructed so that the source electrode1910and drain electrode1912are also in left-to-right fashion. Thus, if there is a TFT misalignment in the horizontal direction, the TFTs1902and1904will receive the same amount of added parasitic capacitance—thus, keeping the panel's defects uniform. It will be appreciated that although TFT1902and TFT1904are depicted side-by-side and connected to the same column, this is primarily for explanatory purposes. It is unlikely that two adjoining subpixels would share the same column/data line—thus, TFT1904and its associated pixel is provided to show the distinction between a normal TFT orientation and TFT1902in a reverse orientation.

FIGS. 20A and 20B, and21A and21B show show other embodiments of TFTs1902and1904.FIGS. 20A and 20Bshow TFT structures in a reverse orientation and a normal orientation, respectively, with an added gate crossover in the normal orientation to balance any parasitic capacitance found in the reverse orientation. As can be seen fromFIGS. 20A and 20B, a new crossover2002is added to TFT1904so as to balance the added parasitic capacitance via crossover1914.FIGS. 21A and 21Bshow TFT structures in a reverse orientation and a normal orientation, respectively, with one fewer gate crossover in the reverse orientation to match any parasitic capacitance in the normal orientation. As may be seen fromFIGS. 21A and 21B, the gate electrode crossover1914has been removed in favor of a gate line crossover2102which may have a lesser impact on individual pixel elements.

FIGS. 22 and 23are embodiments of pixel elements with corners2210and2310removed to match the one corner removed containing the TFT structure. These pixel elements as designed here may balance the parasitic capacitances more than a normal pixel structure.

FIG. 24is another embodiment of a pixel structure that employs at least one extra metal line2410that may help to shield the pixel element from the parasitic capacitances between the gate lines and the pixel element. Additionally, if a dot inversion scheme is employed, then the opposing polarities on both lines2410will also help to balance any parasitic capacitance between the source lines and the pixel elements.