Apparatus and method for unified system power button behavior across different information handling system architectures

An information handling system includes a chipset component configured to implement one of two hardware architectures, and a power button circuit coupled to the chipset component. The power button circuit receives an input signal from an assertion of a power button. The power button circuit further determines that the chipset implements the first hardware architecture and provides a first output signal to the chipset component in response. The first output signal is based on the input signal. The power button circuit further determines that the chipset component implements the second hardware architecture, and provides a second output signal to the chipset component in response. The second output signal is based on the input signal for a first predetermined time, followed by a pulse to the chipset component for a second predetermined time.

FIELD OF THE DISCLOSURE

This disclosure generally relates to information handling systems, and more particularly relates to unified system power button behavior across different information handling system architectures.

BACKGROUND

SUMMARY

An information handling system may be based on one of two hardware architectures. The information handling system may include a chipset component configured to implement one of two hardware architectures, and a power button circuit coupled to the chipset component. The power button circuit may receive an input signal from an assertion of a power button. The power button circuit may further determine that the chipset implements the first hardware architecture and provide a first output signal to the chipset component in response. The first output signal may be based on the input signal. The power button circuit may further determine that the chipset component implements the second hardware architecture, and provide a second output signal to the chipset component in response. The second output signal may be based on the input signal for a first predetermined time, followed by a pulse to the chipset component for a second predetermined time

DETAILED DESCRIPTION OF DRAWINGS

FIG. 1illustrates an embodiment of an information handling system100including processors102and104, a chipset110, a memory120, a graphics adapter130connected to a video display134, a non-volatile RAM (NV-RAM)140that includes a basic input and output system/extensible firmware interface (BIOS/EFI) module142, a disk controller150, a hard disk drive (HDD)154, an optical disk drive156, a disk emulator160connected to a solid state drive (SSD)164, an input/output (I/O) interface170connected to an add-on resource174and a trusted platform module (TPM176, a network interface180, and a baseboard management controller (BMC)190. Processor102is connected to chipset110via processor interface106, and processor104is connected to the chipset via processor interface108. In a particular embodiment, processors102and104are connected together via a high-capacity coherent fabric, such as a HyperTransport link, a QuickPath Interconnect, or the like.

Chipset110represents an integrated circuit or group of integrated circuits that manages the data flows between processors102and104and the other elements of information handling system100. In a particular embodiment, chipset110represents a pair of integrated circuits, such as a northbridge component and a southbridge component. In another embodiment, some or all of the functions and features of chipset110are integrated with one or more of processors102and104. Memory120is connected to chipset110via a memory interface122. An example of memory interface122includes a Double Data Rate (DDR) memory channel and memory120represents one or more DDR

Dual In-Line Memory Modules (DIMMs). In a particular embodiment, memory interface122represents two or more DDR channels. In another embodiment, one or more of processors102and104include a memory interface that provides a dedicated memory for the processors. A DDR channel and the connected DDR DIMMs can be in accordance with a particular DDR standard, such as a DDR3 standard, a DDR4 standard, a DDR5 standard, or the like. Memory120may further represent various combinations of memory types, such as Dynamic Random Access Memory (DRAM) DIMMs, Static Random Access Memory (SRAM) DIMMs, non-volatile DIMMs (NV-DIMMs), storage class memory devices, Read-Only Memory (ROM) devices, or the like.

Graphics adapter130is connected to chipset110via a graphics interface132, and provides a video display output136to a video display134. An example of a graphics interface132includes a Peripheral Component Interconnect-Express (PCIe) interface and graphics adapter130can include a four lane (×4) PCIe adapter, an eight lane (×8) PCIe adapter, a 16-lane (×16) PCIe adapter, or another configuration, as needed or desired. In a particular embodiment, graphics adapter130is provided down on a system printed circuit board (PCB). Video display output136can include a Digital Video Interface (DVI), a High-Definition Multimedia Interface (HDMI), a DisplayPort interface, or the like, and video display134can include a monitor, a smart television, an embedded display such as a laptop computer display, or the like.

NV-RAM140, disk controller150, and I/O interface170are connected to chipset110via an I/O channel112. An example of I/O channel112includes one or more point-to-point PCIe links between chipset110and each of NV-RAM140, disk controller150, and I/O interface170. Chipset110can also include one or more other I/O interfaces, including an Industry Standard Architecture (ISA) interface, a Small Computer Serial Interface (SCSI) interface, an Inter-Integrated Circuit (I2C) interface, a System Packet Interface (SPI), a Universal Serial Bus (USB), another interface, or a combination thereof. NV-RAM140includes BIOS/EFI module142that stores machine-executable code (BIOS/EFI code) that operates to detect the resources of information handling system100, to provide drivers for the resources, to initialize the resources, and to provide common access mechanisms for the resources. The functions and features of BIOS/EFI module142will be further described below.

Network interface180represents a network communication device disposed within information handling system100, on a main circuit board of the information handling system, integrated onto another component such as chipset110, in another suitable location, or a combination thereof. Network interface device180includes a network channel182that provides an interface to devices that are external to information handling system100. In a particular embodiment, network channel182is of a different type than peripheral channel172and network interface180translates information from a format suitable to the peripheral channel to a format suitable to external devices. In a particular embodiment, network interface180includes a network interface card (NIC) or host bus adapter (HBA), and an example of network channel182includes an InfiniBand channel, a Fibre Channel, a Gigabit Ethernet channel, a proprietary channel architecture, or a combination thereof. In another embodiment, network interface180includes a wireless communication interface, and network channel182includes a WiFi channel, a near-field communication (NFC) channel, a Bluetooth or Bluetooth-Low-Energy (BLE) channel, a cellular based interface such as a Global System for Mobile (GSM) interface, a Code-Division Multiple Access (CDMA) interface, a Universal Mobile Telecommunications System (UMTS) interface, a Long-Term Evolution (LTE) interface, or another cellular based interface, or a combination thereof. Network channel182can be connected to an external network resource (not illustrated). The network resource can include another information handling system, a data storage system, another network, a grid management system, another suitable resource, or a combination thereof.

BMC190is connected to multiple elements of information handling system100via one or more management interface192to provide out of band monitoring, maintenance, and control of the elements of the information handling system. As such, BMC190represents a processing device different from processor102and processor104, which provides various management functions for information handling system100. For example, BMC190may be responsible for power management, cooling management, and the like. The term baseboard management controller (BMC) is often used in the context of server systems, while in a consumer-level device a BMC may be referred to as an embedded controller (EC). A BMC included at a data storage system can be referred to as a storage enclosure processor. A BMC included at a chassis of a blade server can be referred to as a chassis management controller and embedded controllers included at the blades of the blade server can be referred to as blade management controllers. Capabilities and functions provided by BMC180can vary considerably based on the type of information handling system. BMC190can operate in accordance with an Intelligent Platform Management Interface (IPMI). Examples of BMC190include an Integrated Dell Remote Access Controller (iDRAC). Management interface192represents one or more out-of-band communication interfaces between BMC190and the elements of information handling system100, and can include an Inter-Integrated Circuit (I2C) bus, a System Management Bus (SMBUS), a Power Management Bus (PMBUS), a Low Pin Count (LPC) interface, a serial bus such as a Universal Serial Bus (USB) or a Serial Peripheral Interface (SPI), a network interface such as an Ethernet interface, a high-speed serial data link such as a Peripheral Component Interconnect-Express (PCIe) interface, a Network Controller Sideband Interface (NC-SI), or the like. As used herein, out-of-band access refers to operations performed apart from a BIOS/operating system execution environment on information handling system100, that is apart from the execution of code by processors102and104and procedures that are implemented on the information handling system in response to the executed code.

BMC190operates to monitor and maintain system firmware, such as code stored in BIOS/EFI module142, option ROMs for graphics interface130, disk controller150, add-on resource174, network interface180, or other elements of information handling system100, as needed or desired. In particular, BMC190includes a network interface194that can be connected to a remote management system to receive firmware updates, as needed or desired. Here, BMC190receives the firmware updates, stores the updates to a data storage device associated with the BMC, transfers the firmware updates to NV-RAM of the device or system that is the subject of the firmware update, thereby replacing the currently operating firmware associated with the device or system, and reboots information handling system, whereupon the device or system utilizes the updated firmware image. BMC190utilizes various protocols and application programming interfaces (APIs) to direct and control the processes for monitoring and maintaining the system firmware. An example of a protocol or API for monitoring and maintaining the system firmware includes a graphical user interface (GUI) GUI associated with BMC190, an interface defined by the Distributed Management Taskforce (DMTF) (e.g., a Web Services Management (WS-MAN) interface, a Management Component Transport Protocol (MCTP) or, a Redfish interface), various vendor defined interfaces (e.g., a Dell EMC Remote Access Controller Administrator (RACADM) utility, a Dell EMC OpenManage Server Administrator (OMSS) utility, a Dell EMC OpenManage Storage Services (OMSS) utility, or a Dell EMC OpenManage Deployment Toolkit (DTK) suite), a BIOS setup utility such as invoked by a “F2” boot option, or another protocol or API, as needed or desired.

In a particular embodiment, BMC190is included on a main circuit board (e.g., a baseboard, a motherboard, or any combination thereof) of information handling system100, or is integrated onto another element of the information handling system such as chipset110, or another suitable element, as needed or desired. As such, BMC190can be part of an integrated circuit or a chip set within information handling system100. An example of BMC190includes an integrated Dell remote access controller (iDRAC), or the like. BMC190may operate on a separate power plane from other resources in information handling system100. Thus BMC190can communicate with the management system via network interface194while the resources of information handling system100are powered off. Here, information can be sent from the management system to BMC190and the information can be stored in a RAM or NV-RAM associated with the BMC. Information stored in the RAM may be lost after power-down of the power plane for BMC190, while information stored in the NV-RAM may be saved through a power-down/power-up cycle of the power plane for the BMC.

Information handling system100is characterized by the fact that major components of the information handling system (e.g., processors102and104and chipset110) are typically manufactured by a common manufacturer. Different manufacturers may provide commonalities in their respective architectures such that code written for one manufacturer's components will operate on another manufacturer's components. In such cases, the various manufacturers' components may be said to implement a common architecture. An example of an architecture may include an x86 architecture, a 64-bit Intel Architecture (IA-64), an ARM architecture, or the like. However, even within a particular common architecture, different manufacturers may provide differences in the way that the components are utilized or designed to interact with each other and the other components of an information handling system. Thus the circuitry, layout, and design of a particular information handling system may include glue logic that permits the components associated with a first manufacturer to work seamlessly together, but such glue logic may be different from the glue logic needed to implement an information handling system that utilizes components associated with a different manufacturer.

Some differences in the glue logic between different manufacturers' components are not generally detectable by a user of the different information handling systems. For example, differences in the terminal impedance for signal traces between different manufacturers would not result in different user experiences with information handling systems that utilize different manufacturers' component. On the other hand, other differences in the glue logic between different manufactures, or differences in the behavior of one manufacture's components, vis a vis another manufacturers' components may result in different user experiences in utilizing the different information handling systems.

An example of a user-detectable difference in behavior includes the way in which components manufactured by the Intel Corporation (hereinafter “Intel”) respond to the use of a power button, and the way in which components manufactured by Advanced Micro Devices, Incorporated (hereinafter “AMD”) respond to the use of a power button. In particular, in an information handling system including components manufactured by Intel, the pressing of the power button (hereinafter referred to as “asserting” the power button) results in a logic “0” signal being detected by the chipset, and the chipset initiates a shutdown of the information handling system via an orderly process of closing applications and terminating the operating system before shutting off the DC power supply (hereinafter referred to as a “graceful shutdown”). In contrast, in an information handling system including components manufactured by AMD, the assertion of the power button similarly results in a logic “0” signal being provided to the chipset, but the chipset does not immediately initiate a graceful shutdown of the information handling system until the power button is de-asserted, thereby providing a logic “1” signal to the chipset.

While this may seem to be a trivial difference, the situation is complicated by whether or not the operating system (OS) instantiated on the information handling system supports the Advanced Configuration and Power Interface (ACPI) standard. In information handling systems with OS' that implement the ACPI standard, the assertion of the power button for a duration that is longer than a Power Button Override (PBO) results in the information handling system being forced into an immediate shutdown by shutting off the DC power supply (hereinafter referred to as a “hard shutdown”). The PBO is typically set at −4 seconds for AMD-based information handling systems, and at −5 seconds for Intel-based information handling systems. Thus, in an information handling system including components manufactured by Intel, the long assertion of the power button immediately results in the chipset attempting to perform a graceful shutdown before the expiration of the BPO, after which time the information handling system experiences a hard shutdown. In contrast, in an information handling system including components manufactured by AMD, the long assertion of the power button only results in the information handling system experiencing a hard shutdown, and no attempt will be made to perform a graceful shutdown.

FIG. 2illustrates a power button circuit200that provides common power button functionality on information handling systems that utilize either an Intel-based architecture or an AMD-based architecture. The power button functionality provided by power button circuit200provides Intel-like power button functionality. Power button circuit200includes a timer210, a rising-edge detector212, a pulse stretch circuit214, an AMD architecture setting216, a delay line218, an AND-gate220, a NOR-gate222, an OR-gate224, a falling-edge detector226, and reset logic228. Power button circuit200operates to receive a power on request input (PowerOnRequest), an external push button input (PBExternal), and a push button register input (PBRegister), to provide an active-low push button output (PBOut_N), an active-high push button assert reset output (PBAssertRst), and an active-high stay off output (StayOff). Reset logic228may represent a complex programmable logic device (CPLD) or another programmable logic device, as needed or desired, and may be represented by add-on resource174inFIG. 1.

NOR-gate222has two inputs to receive PBExternal and PBRegister, and has an output to provide an active-low push button internal output (PBInternal_N). Timer210has an input to receive PBInternal_N, and has an output to provide a push button mask timeout output (PBMaskTimeout). Rising-edge detector212has an input to receive PBMaskTimeout, and has an output to provide a push button mask timeout rising-edge output (PBMaskTimeoutRE). Pulse stretch circuit214has an input to receive PBMaskTimeoutRE, and has an output to provide a push button mask pulse output (PBMaskPulse). Delay line218has an input to receive PowerOnRequest, and has an output. AMD architecture setting216is a single bit that is set to a logic “0” when the information handling system that includes power button circuit200utilizes Intel-based components, and that is set to a logic “1” when the information handling system utilizes AMD-based component. Thus AMD architecture setting216has an output to provide the single bit information. AND-gate220has three inputs to receive PBOutMaskPulse, the output from AMD architecture setting216, and the output from delay line218, and has an output. OR-gate224has three inputs to receive PBInternal_N, the output from AND-gate220, and a StayOffMask output from reset logic228, and has an output to provide PBOut_N. Falling-edge detector226has an input to receive PowerOnRequest, and has an output. Reset logic228has four inputs to receive PBInternal_N, the ouput from AND-gate220, the output from AMD architecture setting216, and the output from falling-edge detector226, and has three outputs to provide PBAssertRst, StayOff, and StayOffMask.

Power button circuit200operates in one of two modes: an Intel-based mode and an AMD-based mode. When AMD architecture setting216stores “0,” power button circuit200operates in the Intel-based mode. Here, AMD architecture setting216provides “0” to the input of AND-gate220, ensuring that the input of OR-gate224remains de-asserted, and further ensuring that PBInternal_N from NOR-gate222is passed on as the output PBOut_N. Here, under normal circumstances, both PBExternal and PBRegister are normally low (“0”) and PBInternal_N is provided at the output of NOR-gate222at “1.” Then, when either of PBExternal or PBRegister are asserted, PBInternal_N is asserted, that is, transitioned from a “1” to a “0,” and the output of NOR-gate222is likewise asserted from a “1” to a “0.” Here OR-gate224provides the output PBOut_N, which is detected by the associated Intel-based chipset as an assertion of the power button, and the chipset initiates the graceful shutdown. Here further, the Intel-based chipset is configured to detect the assertion of either PBExternal or PBRegister for longer than the PBO level and provides the hard shutdown as desired. Further, in the Intel-based mode, “0” is provided by AMD architecture setting216to reset logic228, which is configured to provide Intel-like reset functions based upon PowerOnRequest and on the assertions of either PBExternal or PBRegister, as are known in the art.

When AMD architecture setting216is stored with “1,” power button circuit200operates in the AMD-based mode. Here, AMD architecture setting216provides the “1” to the input of AND-gate220. In the steady operating state, PowerOnRequest is asserted (“1”), and delay line218has timed out such that the output of the delay line is likewise asserted. As such, the signal provided by AND-gate220is based upon the status of PBOutMaskPulse, which, in the steady state, is de-asserted. Thus, in the steady state, the output of AND-gate220and StayOffMask are de-asserted, and, as described above, the output of OR-gate224is dependent upon the status of PBInternal_N. Again, both PBExternal and PBRegister are normally de-asserted and PBInternal_N remains de-asserted. Then, when either of PBExternal or PBRegister are asserted, PBInternal_N is asserted. Here OR-gate224asserts the output PBOut_N, which is not detected by the associated AMD-based chipset as an assertion of the power button circuit, and the chipset does not initiate a graceful shutdown. However, the assertion of PBInternal_N is also seen by timer210and starts the timer. Timer210may be set for a duration that is much shorter than the PBO time, such as 15 ms. After timer210times out, PBMaskTimeout is asserted and the assertion is detected by rising-edge detector212which causes the rising-edge detector to assert PBMaskTimeoutRE to pulse stretch circuit214. Pulse stretch circuit214is configured to detect the assertion of PBMaskTimeoutRE, and in response to assert PBOutMaskPulse for a short duration, such as 180 ms. Here, the pulse assertion of PBOutMaskPulse is provided to the input of AND-gate220which causes a similar pulse signal on the input of OR-gate224, which further causes a similar pulse signal on PBOut_N. Here, the rising edge of the pulse signal is detected by the chipset, and the chipset initiates the graceful shutdown of the information handling system. Finally, the AMD-based chipset is also configured to detect the assertion of either PBExternal or PBRegister for longer than the PBO level and provides the hard shutdown as desired.

FIG. 3illustrates waveforms for the implementation of power button circuit200when the circuit is configured in the AMD-based mode. In particular, PBInternal_N is shown as being asserted (active low) for greater than 4.195 seconds, that is, for greater that 195 ms, as described below, plus the PBO duration, assumed herein to be four (4) seconds. Here, the assertion of PBInternal_N is followed by the immediate assertion (active low) of PBOut_N. As used herein, the immediate following of one event by another will be understood to not necessarily denote a particular time limit, but will be understood to be determined as a circuit delay that is provided by the particular implementation of power button circuit200. The assertion of PBInternal is detected by timer210, rising-edge detector212, and pulse stretch circuit214, which together operate to de-assert PBOut_N five (15) ms after the assertion of PBInternal_N for a period of 180 ms, after which time PBOut_N is reasserted. In this way, a constantly held assertion of a power button results in a rising edge signal on PBOut_N that is detected by the AMD-based chipset, which operates to initiate a graceful shutdown of the information handling system. Then, because PBInternal_N is asserted for greater than the PBO duration, when PBInternal_N has been asserted for four (4) seconds, PowerOnRequest is de-asserted to cause the hard shutdown of the information handling system. Finally, after the information handling system is fully shut down, the reassertion of PBInternal_N is followed by the immediate assertion of PBOut_N which results in the reassertion of PowerOnRequest to reboot the information handling system.

FIG. 4illustrates waveforms for the implementation of power button circuit200when the circuit is configured in the AMD-based mode, and when the information handling system has a non-ACPI OS. In particular, PBInternal_N is shown as being asserted (active low) for less than the PBO duration, assumed herein to be four (4) seconds. Here, as above, the assertion of PBInternal_N is followed by the immediate assertion (active low) of PBOut_N. The assertion of PBInternal is detected by timer210, rising-edge detector212, and pulse stretch circuit214, which together operate to de-assert PBOut_N five (15) ms after the assertion of PBInternal_N for a period of 180 ms, after which time PBOut_N is reasserted. In this way, a constantly held assertion of a power button results in a rising edge signal on PBOut_N that is detected by the AMD-based chipset, which operates to initiate a graceful shutdown of the information handling system. However, here it is further assumed that the graceful shutdown results in the de-assertion of PowerOnRequest prior to the completion of the pulse on PBOut_N. Here, in the non-ACPI OS, the subsequent rise in PBOut_N when PBInternal_N is de-asserted (active low) could be interpreted by the AMD-based chipset as a request to reboot the information handling system. As such, reset logic228is configured to detect AMD architecture setting216to indicate that power button circuit200is in the AMD-based mode. Thus, in response to the de-assertion of PowerOnRequest, reset logic228is configured to assert PBAssetRst until after the second rising edge of PBOut_N to prevent the chipset from performing a spurious reboot of the information handling system. Finally, after the information handling system is fully shut down, the reassertion of PBInternal_N is followed by the immediate assertion of PBOut_N which results in the reassertion of PowerOnRequest to reboot the information handling system.

Here, StayOffMask operates to block PBOut_N from being asserted and preventing the AMD-based chipset from falsely interpreting the previous rising-edge of PBinternal_N to be a request to turn back on, thereby de-asserting PowerOnRequest prior to a subsequent power button event. Further, the information handling system can be configured by user policy to behave in one of several desired ways if AC power is lost (ACPI G3 State). Typically the information handling system is configured to “Turn On” when AC power is restored. Other options include “Turn Off” or “Last State.” Here, reset logic228asserts PBAssertRst to the chipset and the chipset follows the After_G3 execution path. Here, StayOffMask is asserted to keep the information handling system from turning back on at the rising edge of PBInternal_N. StayOff is an internal signal that prevents the information handling system power controls from turning ON the information handling system even if the chipset asserts PowerOnRequest. Reset logic228thus asserts or does not assert StayOffMask to block the subsequent power button event from being received by the chipset on PBOut_N.

The device or module can include software, including firmware embedded at a device, such as a Pentium class or PowerPC™ brand processor, or other such device, or software capable of operating a relevant environment of the information handling system. The device or module can also include a combination of the foregoing examples of hardware or software. Note that an information handling system can include an integrated circuit or a board-level product having portions thereof that can also be any combination of hardware and software.