Semiconductor package and electromagnetic interference shielding structure for the same

A semiconductor package includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and electrically connected to the one or more redistribution layers, an encapsulant disposed on the connection structure and covering at least a portion of the semiconductor chip, and a shielding structure covering at least a portion of the encapsulant. The shielding structure includes a conductive pattern layer having a plurality of openings, a first metal layer covering the conductive pattern layer and extending across the plurality of openings, and a second metal layer covering the first metal layer. The second metal layer has a thickness greater than a thickness of the first metal layer.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims benefit of priority to Korean Patent Application No. 10-2018-0137197 filed on Nov. 9, 2018 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to a semiconductor package and an electromagnetic interference shielding structure for electromagnetic interference shielding of the semiconductor package.

Semiconductor packages are becoming smaller and thinner as users demand slim, high-end devices to provide users with improved gripping characteristics and improved designs. As electromagnetic waves generated by such components cause interference with other components in close proximity thereto, malfunctions may occur. To address the issue, electromagnetic interference (EMI) shielding technology has been more actively developed.

According to a shielding technique employed in recent years, a metal coating layer for electromagnetic interference shielding is formed on a semiconductor package itself. However, an external surface of the semiconductor package, on which the metal coating layer is formed, is generally not flat. Moreover, adhesion and reliability become problematic when the metal coating layer is formed.

SUMMARY

An aspect of the present disclosure is to provide a semiconductor package, to which a shielding structure having improved adhesion and reliability is applied, and an electromagnetic interference shielding structure for the semiconductor package.

One proposal of the present disclosure is to introduce an electromagnetic interference shielding structure to an external surface of the semiconductor package. The electromagnetic interference shielding structure is formed by forming a conductive pattern having a plurality of openings on a base layer, forming a first metal layer to cover the conductive pattern layer and the surface of the base layer exposed by the plurality of openings, and forming a second metal layer having a significant thickness using the first metal layer as a seed layer to cover the first metal layer.

According to an aspect of the present disclosure, a semiconductor package includes a connection structure including one or more redistribution layers, a semiconductor chip disposed on the connection structure and electrically connected to the one or more redistribution layers, an encapsulant disposed on the connection structure and covering at least a portion of the semiconductor chip, and a shielding structure covering at least a portion of the encapsulant. The shielding structure includes a conductive pattern layer having a plurality of openings, a first metal layer covering the conductive pattern layer and extending across the plurality of openings, and a second metal layer covering the first metal layer. The second metal layer has a thickness greater than a thickness of the first metal layer.

According to another aspect of the present disclosure, an electromagnetic interference shielding structure includes a conductive pattern layer disposed on a base layer and having a plurality of openings each exposing at least a portion of a surface of the base layer, a first metal layer covering a surface of the conductive pattern layer and the surface of the base layer exposed by the plurality of openings, and a second metal layer covering the first metal layer. The second metal layer has a thickness greater than a thickness of the first metal layer.

According to a further aspect of the present disclosure, a semiconductor package includes a semiconductor chip having opposing first and second surfaces, the first surface having one or more connection pads disposed thereon, an encapsulant covering at least a portion of the second surface of the semiconductor chip, and a shielding structure disposed on the encapsulant and comprising a conductive pattern layer contacting the encapsulant and formed of an adhesive resin having metal nanoparticles dispersed therein.

DETAILED DESCRIPTION

Electronic Device

Referring toFIG. 1, an electronic device1000may accommodate a mainboard1010therein. The mainboard1010may include chip related components1020, network related components1030, other components1040, and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal lines1090.

FIG. 2is a schematic perspective view illustrating an example of an electronic device.

Referring toFIG. 2, a semiconductor package may be used for various purposes in the various electronic devices1000as described above. For example, a motherboard1110may be accommodated in a body1101of a smartphone1100, and various electronic components1120may be physically or electrically connected to the motherboard1110. In addition, other components that may or may not be physically or electrically connected to the motherboard1110, such as a camera module1130, may be accommodated in the body1101. Some of the electronic components1120may be the chip related components, for example, a semiconductor package1121, but are not limited thereto. The electronic device is not necessarily limited to the smartphone1100, but may be other electronic devices as described above.

Semiconductor Package

Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a finished semiconductor product in itself, and may be damaged due to external physical or chemical impacts. Therefore, the semiconductor chip itself may not be used, but may be packaged and used in an electronic device, or the like, in a packaged state.

Here, semiconductor packaging is provided due to the existence of a difference in a circuit width between the semiconductor chip and a mainboard of the electronic device in terms of electrical connections. In detail, a size of connection pads of the semiconductor chip and an interval between the connection pads of the semiconductor chip are very fine, but a size of component mounting pads of the mainboard used in the electronic device and an interval between the component mounting pads of the mainboard are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the mainboard, and packaging technology for buffering a difference in a circuit width between the semiconductor chip and the mainboard may therefore be provided.

A semiconductor package manufactured by the packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on a structure and a purpose thereof.

The fan-in semiconductor package and the fan-out semiconductor package will hereinafter be described in more detail with reference to the drawings.

Fan-in Semiconductor Package

FIGS. 3A and 3Bare schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged.

FIG. 4is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package.

Referring toFIGS. 3A to 4, a semiconductor chip2220may be, for example, an integrated circuit (IC) in a bare state, including a body2221including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads2222formed on one surface of the body2221and including a conductive material such as aluminum (Al), or the like, and a passivation layer2223such as an oxide layer, a nitride layer, or the like, formed on one surface of the body2221and covering at least portions of the connection pads2222. In this case, since the connection pads2222may be significantly small, it may be difficult to mount the integrated circuit (IC) on an intermediate level printed circuit board (PCB) as well as on the mainboard of the electronic device, or the like.

Therefore, a connection member2240may be formed depending on a size of the semiconductor chip2220on the semiconductor chip2220in order to redistribute the connection pads2222. The connection member2240may be formed by forming an insulating layer2241on the semiconductor chip2220using an insulating material such as a photoimageable dielectric (PID) resin, forming via holes2243hopening the connection pads2222, and then forming wiring patterns2242and vias2243. Then, a passivation layer2250protecting the connection member2240may be formed, an opening2251may be formed, and an underbump metal layer2260, or the like, may be formed. That is, a fan-in semiconductor package2200including, for example, the semiconductor chip2220, the connection member2240, the passivation layer2250, and the underbump metal layer2260may be manufactured through a series of processes.

As described above, the fan-in semiconductor package may have a package form in which all of the connection pads, for example, input/output (I/O) terminals, of the semiconductor chip are disposed inside the semiconductor chip, and may have excellent electrical characteristics and be produced at a low cost. Therefore, many elements mounted in smartphones have been manufactured in a fan-in semiconductor package form. In detail, many elements mounted in smartphones have been developed to implement a rapid signal transfer while having a compact size.

However, since all I/O terminals need to be disposed inside the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has significant spatial limitations. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a compact size. In addition, due to the disadvantage described above, the fan-in semiconductor package may not be directly mounted and used on the mainboard of the electronic device. The reason is that even though a size of the I/O terminals of the semiconductor chip and an interval between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip are not enough to directly mount the fan-in semiconductor package on the mainboard of the electronic device.

FIG. 5is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on a ball grid array (BGA) substrate and is ultimately mounted on a mainboard of an electronic device.

FIG. 6is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in a BGA substrate and is ultimately mounted on a mainboard of an electronic device.

Referring toFIGS. 5 and 6, in a fan-in semiconductor package2200, connection pads2222, that is, I/O terminals, of a semiconductor chip2220may be redistributed through a BGA substrate2301, and the fan-in semiconductor package2200may be ultimately mounted on a mainboard2500of an electronic device in a state in which it is mounted on the BGA substrate2301. In this case, solder balls2270, and the like, may be fixed by an underfill resin2280, or the like, and an outer side of the semiconductor chip2220may be covered with a molding material2290, or the like. Alternatively, a fan-in semiconductor package2200may be embedded in a separate BGA substrate2302, connection pads2222, that is, I/O terminals, of the semiconductor chip2220may be redistributed by the BGA substrate2302in a state in which the fan-in semiconductor package2200is embedded in the BGA substrate2302, and the fan-in semiconductor package2200may be ultimately mounted on a mainboard2500of an electronic device.

As described above, it may be difficult to directly mount and use the fan-in semiconductor package on the mainboard of the electronic device. Therefore, the fan-in semiconductor package may be mounted on the separate BGA substrate and be then mounted on the mainboard of the electronic device through a packaging process or may be mounted and used on the mainboard of the electronic device in a state in which it is embedded in the BGA substrate.

Fan-Out Semiconductor Package

Referring toFIG. 7, in a fan-out semiconductor package2100, for example, an outer side of a semiconductor chip2120may be protected by an encapsulant2130, and connection pads2122of the semiconductor chip2120may be redistributed outwardly of the semiconductor chip2120by a connection member2140. In this case, a passivation layer2150may further be formed on the connection member2140, and an underbump metal layer2160may further be formed in openings of the passivation layer2150. Solder balls2170may further be formed on the underbump metal layer2160. The semiconductor chip2120may be an integrated circuit (IC) including a body2121, the connection pads2122, a passivation layer (not illustrated), and the like. The connection member2140may include an insulating layer2141, redistribution layers2142formed on the insulating layer2141, and vias2143electrically connecting the connection pads2122and the redistribution layers2142to each other.

As described above, the fan-out semiconductor package may have a form in which I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip need to be disposed inside the semiconductor chip. Therefore, when a size of the semiconductor chip is decreased, a size and a pitch of balls need to be decreased, such that a standardized ball layout may not be used in the fan-in semiconductor package. On the other hand, the fan-out semiconductor package has the form in which the I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip as described above. Therefore, even in a case in which a size of the semiconductor chip is decreased, a standardized ball layout may be used in the fan-out semiconductor package as it is, such that the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using a separate BGA substrate, as described below.

FIG. 8is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a mainboard of an electronic device.

Referring toFIG. 8, a fan-out semiconductor package2100may be mounted on a mainboard2500of an electronic device through solder balls2170, or the like. That is, as described above, the fan-out semiconductor package2100includes the connection member2140formed on the semiconductor chip2120and capable of redistributing the connection pads2122to a fan-out region that is outside of a size of the semiconductor chip2120, such that the standardized ball layout may be used in the fan-out semiconductor package2100as it is. As a result, the fan-out semiconductor package2100may be mounted on the mainboard2500of the electronic device without using a separate BGA substrate, or the like.

As described above, since the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using the separate BGA substrate, the fan-out semiconductor package may be implemented at a thickness lower than that of the fan-in semiconductor package using the BGA substrate. Therefore, the fan-out semiconductor package may be miniaturized and thinned. In addition, the fan-out electronic component package has excellent thermal characteristics and electrical characteristics, such that it is particularly appropriate for a mobile product. Therefore, the fan-out electronic component package may be implemented in a form more compact than that of a general package-on-package (POP) type using a printed circuit board (PCB), and may solve a problem due to the occurrence of a warpage phenomenon.

Meanwhile, the fan-out semiconductor package refers to package technology for mounting the semiconductor chip on the mainboard of the electronic device, or the like, as described above, and protecting the semiconductor chip from external impacts, and is a concept different from that of a printed circuit board (PCB) such as a BGA substrate, or the like, having a scale, a purpose, and the like, different from those of the fan-out semiconductor package, and having the fan-in semiconductor package embedded therein.

Hereinafter, a semiconductor package, to which a shielding structure having improved adhesion and reliability is applied, and an electromagnetic interference shielding structure for the semiconductor package will be described with reference to accompanying drawings.

FIG. 9is a schematic cross-sectional view illustrating an example of a semiconductor package.

Referring toFIG. 9, a fan-out semiconductor package according to an example includes a frame110having a through-hole110H, a semiconductor chip120, disposed in the through-hole110H, having an active surface on which a connection pad122is disposed and an inactive surface disposed to oppose the active surface, an encapsulant130covering at least a portion of each of the frame110and the inactive surface of the semiconductor chip120and filling at least a portion of the through-hole110H, at least one connection structure140, disposed on the frame110and the active surface of the semiconductor chip120, having at least one redistribution layer142electrically connected to the connection pad122, a passivation layer150disposed on the connection structure140, a plurality of underbump metal portions160respectively connected to a plurality of openings of the passivation layer150, and a shielding structure180covering a top surface of the encapsulant130and extending to cover a side surface of the encapsulant130, a side surface of the frame110, and a side surface of the connection structure140.

The shielding structure180includes a conductive pattern layer181having a plurality of openings181h, a first metal layer182covering the conductive pattern layer181and blocking or extending integrally across the plurality of openings181h, and a second metal layer183covering the first metal layer182. The first metal layer182may be formed to have a small thickness by electroless plating such as sputtering to block all of the plurality of openings181h, and the second metal layer183may be formed to have a great thickness by electrolytic plating to have an improved electromagnetic interference shielding effect. Accordingly, the second metal layer183may have a thickness greater than a thickness of the first metal layer182.

According to a shielding technique employed in recent years, a metal coating layer for electromagnetic interference shielding is formed on a semiconductor package itself. However, an external surface of the semiconductor package, on which the metal coating layer is formed, is generally not flat. Moreover, adhesion and reliability become problematic when the metal coating layer is formed. For example, after a plurality of semiconductor packages are simultaneously formed at a wafer or panel level, they are singulated by dicing. After the dicing, a molding material or a panel material may be disposed in a region, from which an inorganic filler is removed, or an external surface to which a glass fiber is exposed. Accordingly, when a metal coating layer is formed there, adhesion between the molding material and the metal coating layer may be reduced to cause lifting. In addition, since surface unevenness results from the exposure of the glass fiber to the panel material and outflow of the inorganic filler, there may be a region in which formation of the metal coating layer using metal sputtering and plating is not appropriately performed. For example, a coverage issue may occur.

Meanwhile, in the package100A according to an example embodiment, the conductive pattern layer181, having a plurality of openings181h, is formed on the external surface of the package100A. In this case, since the conductive pattern layer181may have a conductive mesh structure in which metal nanoparticles are dispersed in an adhesive resin, the package100A may have improved adhesion and reliability even when the external surface of the package100A is uneven. Next, the first metal layer182is formed by metal sputtering or the like. The first metal layer182covers the conductor pattern layer181, and may be formed to have a small thickness to block the plurality of openings181h. Since the first metal layer182is formed in the case in which the conductive pattern layer181was already formed, the first metal layer182may also have improved adhesion and reliability although the external surface of the package100A is uneven, as set forth above. Next, the second metal layer183is formed using the first metal layer182as a seed layer by electrolytic plating or the like. The second metal layer183covers the first metal layer182. The second metal layer183may be disposed on the first metal layer182, and may also have improved adhesion and reliability. The second metal layer183may have a significant thickness, and may have an improved electromagnetic interference shielding effect and may also have a heat dissipation effect.

The package100A according to an example has an external surface as a base layer on which an electromagnetic interference shielding structure is disposed. The electromagnetic interference shielding structure includes the conductive pattern layer181having a plurality of openings181h, each exposing at least a portion of a surface of the base layer, the first metal layer182covering the surface of the base layer exposed by the plurality of openings181h, and the second metal layer183covering the first metal layer182and having a thickness greater than a thickness of the first metal layer182. The package100A, including the electromagnetic interference shielding structure, may have adhesion and reliability and effectively shield electromagnetic interference and, furthermore, may have a heat dissipation effect.

Hereinafter, the components included in the package100A according to an example embodiment will be described in further detail.

The frame110may further improve rigidity of the package100A depending on certain materials and may serve to secure thickness uniformity and the like of the encapsulant130. The frame110has a through-hole110H. In the through-hole110H, the semiconductor chip120is disposed to be spaced apart from the frame110by a predetermined distance. Side surfaces of the semiconductor chip120may be surrounded by the frame110. However, such a form is only an example and may be variously modified to have other forms, and the frame110may perform another function depending on such a form. As appropriate, the frame110may be omitted.

The frame110includes an insulating layer111. An insulating material may be used as a material of the insulating layer111. The insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. When a high-rigidity material such as prepreg including a glass fiber or the like is used, the frame110may be used as a support member for controlling warpage of the package100A or a core member. The through-hole110H may extend through the insulating layer111.

The semiconductor chip120may be an integrated circuit (IC) providing several hundred to several million or more elements integrated in a single chip. The semiconductor chip120may be, for example, a processor chip such as a central processor (for example, a central processing unit (CPU)), a graphics processor (for example, a graphics processing unit (GPU)), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like, in detail, an application processor (AP). However, the semiconductor chip120is not limited thereto, and may be a logic chip such as an analog-to-digital converter, an application-specific integrated circuit (ASIC), or a memory chip such as a volatile memory (for example, a DRAM), a nonvolatile memory (for example, a ROM), a flash memory, or the like. In addition, two or more of the abovementioned elements may be combined with each other and be disposed in the through-hole110H of the package100A.

The semiconductor chip120may be an IC formed based on an active wafer. In this case, a base material of a body121may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body121. The connection pad(s)122may electrically connect the semiconductor chip120to other components. A material of the connection pad(s)122may be a metal such as aluminum (Al), but is not limited thereto. A passivation layer123may be disposed on the body121to expose the connection pad(s)122, and may be an oxide layer, a nitride layer, or the like. Alternatively, the passivation layer123may be a double layer of an oxide layer and a nitride layer. A bottom surface of the connection pad122may have a step with respect to (or be spaced apart from) a bottom surface of the encapsulant130through the passivation layer123, and the encapsulant130may thereby be prevented from bleeding into the bottom surface of the connection pad122to some extent. An insulating layer, not illustrated, and the like, may be further disposed in other appropriate positions. The semiconductor chip120may be a bare die. A redistribution layer, not illustrated, may be further disposed on the active surface of the semiconductor chip120, and bumps, not illustrated, or the like, may be connected to the connection pad122.

The encapsulant130may protect the frame110and the semiconductor chip120. An encapsulation form is not limited as long as the encapsulant130covers at least a portion of the frame110and at least a portion of the semiconductor chip120. For example, the encapsulant130may cover at least a portion of each of the frame110and the inactive surface of the semiconductor chip120, and may fill at least a portion of the through-hole100H. The encapsulant130may fill the through-hole100H to serve as an adhesive depending on certain materials and to reduce buckling.

A material of the encapsulant130is not limited. For example, an insulating material may be used as a material of the encapsulant130. The insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber, for example, prepreg, Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. As appropriate, a photoimageable dielectric material such as a photoimageable encapsulant (PIE) may be used as a material of the encapsulant230.

The connection structure140may redistribute the connection pad(s)122of the semiconductor chip120. Several tens to several hundreds of connection pads122, having various functions, may be redistributed through the connection structure140and may be physically and/or electrically connected through the electrical connection metal170depending on the functions thereof. The connection structure140includes an insulating layer141disposed on the active surface of the semiconductor chip120, one or more redistribution layer(s)142disposed on the insulating layer141, and one or more connection via(s)143penetrating through the insulating layer141and electrically connecting the connection pad122of the semiconductor chip120to the redistribution layer142. The insulating layer141, the redistribution layer142, and the connection vias143of the connection structure140may include a larger number of layers and/or vias than those illustrated in the drawings.

A material of the insulating layers141may be an insulating material. In this case, a photoimageable dielectric (PID) material such as a PID resin may also be used as the insulating material in addition to the above-described insulating materials. For example, the insulating layers141may be a photosensitive insulating layer. When the insulating layer141has photosensitive properties, a fine pitch of the connection via143may be achieved more easily. The insulating layer141may be a photosensitive insulating layer including an insulating resin and an inorganic filler. When the insulating layer141includes multiple layers, materials of the multiple layers may be identical to each other or, as appropriate, may be different from each other. When the insulating layer141includes multiple layers, the multiple layers are integrated with each other, such that boundaries therebetween may not be readily apparent.

The redistribution layer(s)142may redistribute the connection pad(s)122of the semiconductor chip120to electrically connect the redistributed connection pad(s)122to the electrical connection metal170. A material of the redistribution layer142may also be a metal such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layer142may perform various functions depending on a design of a corresponding layer. For example, the redistribution layer142may include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. The ground (GND) pattern and the power (PWR) pattern may be identical to each other. The redistribution layer142may include various types of via pad(s), electrical connection metal pad(s), or the like. The redistribution layer142may also be formed by a plating process and may include a seed layer and a plating layer.

The connection via(s)143may electrically connect the redistribution layer(s)142, the connection pad(s)122, and the like, disposed on different layers. As a result, an electrical path is formed in the package100A. A material of the connection via(s)143may also be a metal such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The connection via(s)143may include a via for signal, a via for power, a via for ground, or the like, and the via for power and the via for ground may be identical to each other. The connection via143may be a filled-type via filled with a metal, or a conformal-type via formed along a wall surface of a via hole. Moreover, the connection via143may have a tapered cross-sectional shape. The connection via143may also be formed by a plating process, and may include a seed layer and a plating layer.

The passivation layer150may be additionally configured to protect the connection structure140from external physical and chemical damage and the like. The passivation layer150may have an opening exposing at least a portion of the redistribution layer142. Several tens to several tens of thousands of openings may be formed in the passivation layer150. A material of the passivation layer150is not limited. For example, the material of the passivation layer150may be an insulating material. The insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, ABF, FR-4, BT, or the like. Alternatively, the material of the passivation layer150may be a solder resist.

The underbump metal160may be additionally configured to improve connection reliability of the electrical connection metal170and to improve board level reliability of the package100A. The underbump metal160is connected to the redistribution layer142exposed through the opening of the passivation layer150. The underbump metal160may be formed in the openings of the passivation layer150by a known metallization method using a known conductive material such as a metal, but is not limited thereto.

The connection terminals170may also be additionally configured to physically and/or electrically connect the semiconductor package100A to an external component. For example, the semiconductor package100A may be mounted on a mainboard of an electronic device through the connection terminals170. Each of the connection terminals170may be formed of a low melting-point metal, for example, tin (Sn) or a Sn-containing ally. More specifically, each of the connection terminals170may be formed of a solder or the like, but a material of the connection terminals170is not limited thereto.

Each of the connection terminals170may be a land, a ball, a pin, or the like. The connection terminals170may be formed as a multilayer structure or a single-layer structure. When the connection terminals170are formed as a multilayer structure, the connection terminals170may include a copper (Cu) pillar and a solder. When the connection terminals170are formed as a single-layer structure, the connection terminals170may include a tin-silver solder or copper (Cu). However, these are merely examples, and a structure and a material of the electrical connection metal170are not limited thereto. The number, interval, dispositional form, and the like, of the electrical connection metal170are not limited, but may be sufficiently modified depending on design. For example, several tens to several tens of thousands of electrical connection metals170may be provided according to the number of connection pads122. The number of electrical connection metals170may be greater than or smaller than several tens to several tens of thousands.

At least one of the electrical connection metals170may be disposed in a fan-out region. The term “fan-out region” refers to a region except for (or outside of) a region in which the semiconductor chip120is disposed (e.g., outside of a region of overlap with the semiconductor chip120along a stacking direction of the semiconductor chip120on the connection structure140). The fan-out package may have improved reliability as compared to a fan-in package, may allow a plurality of input/output (I/O) terminals to be implemented, and may facilitate a three-dimensional (3D) interconnection. Moreover, as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package may be manufactured to have a small thickness, and may be superior in price competitiveness.

The shielding structure180may implement electromagnetic interference shielding of the semiconductor package100A and may improve a heat dissipation effect. The shielding structure180may cover a top surface of the encapsulant130and extend to cover a side surface of the encapsulant130, a side surface of the frame110, and a side surface of the connection structure140. The shielding structure180includes a conductive pattern layer181having a plurality of openings181h, a first metal layer182covering the conductive pattern layer181and blocking the plurality of openings181h, and a second metal layer183covering the first metal layer182. Accordingly, the package100A may have improved adhesion between the shielding structure180and the top surface and the side surface of the encapsulant130, serving as abase layer, the side surface of the frame110, and the side surface of the connection structure140, and improved reliability such as full area coverage.

The conductive pattern layer181may be formed by a self-aligning manner using a metal nanoparticle coating solution, such as a silver nanoparticle coating solution, which may have a plurality of openings181h. The metal nanoparticle coating solution may include metal nanoparticles and an adhesive resin. The metal nanoparticles may be metal nanoparticles of silver, a silver-copper alloy, a silver-palladium alloy, or other silver alloy, but is not limited thereto and metal nanoparticles of other metals may be used. The adhesive resin may be a known insulating resin such as an acrylic resin or an epoxy resin, in detail, an insulating resin including an acrylic monomer, but is not limited thereto. The metal nanoparticle coating solution may contain another additive such as a surfactant and a solvent in addition to the metal nanoparticles and the binder resin. The coating may be performed using a coating method selected from spray coating, spin coating, slit coating, or any other appropriate coating method.

As described above, the metal nanoparticle coating solution may be used to rapidly and easily form the conductive pattern layer181having a conductive mesh structure. In detail, a coating process may be performed to the conductor pattern layer181having a large-area conductive mesh structure. Moreover, since low-viscosity spray coating may be performed, the conductive pattern layer181may be easily formed even when the base layer is an inclined surface or a side surface, similarly to the side surface of the encapsulant130, the side surface of the frame110, and the side surface of the connection structure140.

The first metal layer182is formed to have a small thickness along a surface of the conductive pattern layer181and a surface of the base layer exposed by the plurality of openings181h, and thus, may serve as a seed layer. The first metal layer182may be formed by electroless plating, in detail, metal sputtering. Since the first metal layer182may be formed to have a small thickness, the first metal layer182may easily block the plurality of openings181hwithout voids. The first metal layer182may include a metal such as at least one of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. For example, the first metal layer182may be a titanium (Ti) layer or a double layer of titanium (Ti)/copper (Cu), but is not limited thereto. Since the first metal layer182may be formed to have a small thickness by metal sputtering or the like along the surface of the conductive pattern layer181and the surface of the base layer exposed by the plurality of openings181h, the first metal layer182may have a concave portion182hdisposed in each of the openings181h.

The second metal layer183is formed on the first metal layer to have a significant thickness to cover the first metal layer182using the first metal layer182as a seed layer. Thus, the second metal layer performs not only an electromagnetic interference shielding function but also a heat dissipation function. The second metal layer183may be formed by electrolytic plating and may be formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), Titanium (Ti), or alloys thereof. For example, the second metal layer183may be a copper (Cu) electrolytic plating layer, but is not limited thereto. The second metal layer183may fill each concave portion182hof the first metal layer182.

Depending on the thickness of the second metal layer183, the second metal layer183may also have a concave portion on its outer surface in a region corresponding to the concave portion182hof the first metal layer182. In this case, the concave portion of the second metal layer183may have a depth smaller than a depth of the concave portion182hof the first metal layer182. In other embodiments, however, the second metal layer183may have a substantially planar outer surface.

Although not illustrated in the drawing, a metal thin film may be formed on a wall surface of the through-hole110H to achieve heat dissipation and electromagnetic interference shielding. As appropriate, a plurality of semiconductor chips120, performing the same function or different functions, may be disposed in the through-hole110H, and/or multiple through-holes110H may be provided each with one or more semiconductor chips120disposed therein. As appropriate, an additional passive component such as an inductor or a capacitor may be disposed in the through-hole110H. As appropriate, a surface-mount (SMT) component, including a passive component such as an inductor, capacitor, and the like, may be disposed on a surface of the passivation layer150.

FIG. 10Ais a schematic cross-sectional view illustrating that a conductive pattern layer is formed on an external surface of a semiconductor package, andFIG. 10Bis a schematic plan view of the conductive pattern layer inFIG. 10Awhen viewed from above.

Referring toFIGS. 10A and 10B, the above-mentioned metal nanoparticle coating solution is coated on a top surface and a side surface of an encapsulant130, provided as a base layer, a side surface of a frame110, and a side surface of a connection structure140by spray coating, or the like, to forma coating layer, in detail, a conductive pattern layer181.

FIG. 11Ais a schematic cross-sectional view illustrating a plurality of openings are formed in a conductive pattern layer disposed on an external surface of a semiconductor package, andFIG. 11Bis a schematic plan view of the conductive pattern layer inFIG. 11Awhen viewed from above.

Referring toFIGS. 11A and 11B, a plurality of openings181hare formed in the conductive pattern layer181using a self-aligning manner to respectively expose a surface of a base layer (e.g., a base layer of the top surface of the encapsulant130, the side surface of the encapsulant130, the side surface of the frame110, and/or the side surface of the connection structure140). In detail, a conductive pattern layer181having a conductive mesh structure is implemented.

FIG. 12Ais a schematic cross-sectional view illustrating that a first metal layer is further disposed on an external surface of a semiconductor package, andFIG. 12Bis a schematic plan view of the first metal layer inFIG. 12Awhen viewed from above (and in which the first metal layer is shown as being semi-transparent for illustrative purposes).

Referring toFIGS. 12A and 12B, a first metal layer182is formed by electroless plating, for example, metal sputtering, or the like, to cover a surface of the conductive pattern layer181and a surface of the base layer exposed by the plurality of openings181h. The first metal layer182is formed to have a relatively small thickness and to block all the plurality of openings181hof the conductive pattern layer181. As a result, the first metal182has a concave portion182hin each of the openings181h.

FIG. 13Ais a schematic cross-sectional view illustrating that a second metal layer is further disposed on an external surface of a semiconductor package, andFIG. 13Bis a schematic plan view of the second metal layer inFIG. 13Awhen viewed from above.

Referring toFIGS. 13A and 13B, a second metal layer183is formed by electrolytic plating, or the like, using the first metal layer182as a seed layer to cover the first metal layer182. The second metal layer183is formed to have a relatively great thickness, and fills each concave portion182hof the first metal layer182. As a result, a metal shielding layer is formed on an entire surface of the base layer.

FIG. 14is a schematic cross-sectional view illustrating an example of a semiconductor package according to another example.

Referring toFIG. 14, a semiconductor package100B according to another example includes a frame110in contact with a connection structure140, the frame110including a first insulating layer111a, a first wiring layer112aembedded in the first insulating layer111awhile being in contact with the connection structure140, a second wiring layer112bdisposed on a side of the first insulating layer111aopposing a side in which the first wiring layer112ais embedded, a second insulating layer disposed on the first insulating layer111ato cover the second wiring layer112b, and a third wiring layer112cdisposed on the second insulating layer111b. The first to third wiring layers112a,112b, and112care electrically connected to a connection pad122. The first wiring layers112aand the second and third wiring layers112band112care electrically connected to each other through first and second wiring vias113aand113bpenetrating through the first and second insulating layers111aand111b, respectively. Since the frame110includes a great number of wiring layers112a,112b, and112c, the connection structure140may be simplified. As a result, a decrease in yield, occurring during formation of the connection structure140, may be prevented.

A material of the insulating layers111aand111bis not limited. For example, an insulating material may be used as a material of the insulating layers111aand111b. The insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. As appropriate, PID may be used as the insulating material.

The wiring layers112a,112b, and112cmay redistribute the connection pad(s)122of the semiconductor chip120. A material of the wiring layers112a,112b, and112cmay also be a metal such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The wiring layers112a,112b, and112cmay perform various functions depending on a design of a corresponding layer. For example, the wiring layers112a,112b, and112cmay include a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, and the like. The ground (GND) pattern and the power (PWR) pattern may be identical to each other. The redistribution layer142may include various types of via pad, electrical connection metal pad, or the like. The wiring layers112a,112b, and112cmay also be formed by a plating process and may include a seed layer and a plating layer.

When the first wiring layer112ais embedded in the first insulating layer111a, a step, caused by the thickness of the first wiring layer112a, may be significantly reduced to maintain an insulation distance constant. For example, a difference between a distance from the redistribution layer142to a bottom surface of the first insulating layer111aand a distance from the redistribution layer142to the connection pad of the semiconductor chip120may be smaller than a thickness of the first wiring layer112a. Thus, a high-density wiring design of the connection structure140may be readily performed. The first wiring layer112amay be recessed into the insulating layer111. In this case, a bottom surface of the first insulating layer111aand a bottom surface of the first wiring layer112amay have a step. Accordingly, bleeding of a material of the encapsulant130may be suppressed to prevent the first wiring layer112afrom being contaminated by the material of the encapsulant130. The second wiring layer112bmay be disposed between an active surface and an inactive surface of the semiconductor chip120. The frame110may be formed to have a thickness corresponding to a thickness of the semiconductor chip120. Accordingly, the second wiring layer112b, formed inside the frame110, may be disposed at a level between the active surface and the inactive surface of the semiconductor chip120in a thickness direction of the semiconductor chip120. Each of the wiring layers112a,112b, and112cmay have a thickness greater than a thickness of the redistribution layer142. This is because the wiring layers112a,112band112cmay be formed to have a larger scale depending on the thickness of the frame110, while the redistribution layer142may be finely designed and thinned.

The wiring vias113aand113belectrically connect the wiring layers112a,112b, and112c, disposed on different layers, to form an electrical path in the frame110. The above-mentioned metal may also be used as a material forming the wiring vias113aand113b. Each of the wiring vias113aand113bmay include a via for signals, a via for power, a via for a ground, or the like, and the via for power and the via for a ground may be identical to each other. The wiring vias113aand113bmay be completely filled with a metal or may be a via in which a metal is formed along a wall surface of a connection via hole. Each of the wiring vias113aand113bmay also be a filled-type via filled with a metal, or a conformal-type via in which a metal is formed along a wall surface of a via hole. Moreover, the connection via143may have a tapered cross-sectional shape. The connection via143may also be formed by a plating process, and may include a seed layer and a plating layer.

When a hole for the first wiring via113ais formed, some pads of the first wiring layer112amay serve as a stopper. Accordingly, it is advantageous in terms of process that a first wiring via113ahas a tapered shape in which an upper side has a width larger than a width of a lower side. In this case, the first wiring via113amay be integrated with a pad pattern of the second wiring layer112b. Similarly, when a hole for the second wiring via113bis formed, some pad of the second wiring layer112bmay serve as a stopper. Accordingly, it is advantageous in process that a second wiring via113bhas a tapered shape in which an upper side has a width larger than a width of a lower side. In this case, the second wiring via113bmay be integrated with a pad pattern of the third wiring layer112c.

The other descriptions, for example, descriptions of the shielding structure180are substantially the same as the above descriptions, and will be omitted herein.

FIG. 15is a schematic cross-sectional view illustrating another example of a semiconductor package.

Referring toFIG. 15, a semiconductor package100C according to another example includes a frame110including a first insulating layer111a, a first wiring layer112aand a second wiring layer112brespectively disposed on opposing surfaces of the first insulating layer111a, a second insulating layer111bdisposed on the first insulating layer111ato cover the first wiring layer112a, a third redistribution layer112cdisposed on the second insulating layer111b, a third insulating layer111cdisposed on the first insulating layer111ato cover the second wiring layer112b, and a fourth wiring layer112ddisposed on the third insulating layer111c. The first to fourth wiring layers112a,112b,112c, and112dare electrically connected to a connection pad122. Since the frame110includes a greater number of wiring layers112a,112b,112c, and112d, a connection structure140may be further simplified. The first to fourth wiring layers112a,112b,112c, and112dmay be electrically connected to each other through first to third wiring vias113a,113b, and113crespectively penetrating through the first to third insulating layers111a,111b, and111c.

The first insulating layer111amay have a thickness greater than a thickness of the second insulating layer111band a thickness of the third insulating layer111c. The first insulating layer111amay have a relatively great thickness to maintain rigidity, and the second and third insulating layers111band111cmay be introduced to form a greater number of wiring layers112cand112d. From a similar point of view, a wiring via of the first wiring via layer113apenetrating through the first insulating layer111amay have an average diameter and a height greater than an average diameter and a height of each of the second and third wiring via layers113band113cpenetrating through the second and third insulating layers111band111c. The first wiring113amay have an hourglass shape or a cylindrical shape, and the second and third wiring vias113band113cmay have tapered shapes of opposite directions. Each of the wiring layers112a,112b,112c, and112dmay have a thickness greater than a thickness of the redistribution layer142.

The other descriptions, for example, descriptions of the shielding structure180are substantially the same as the above descriptions, and will be omitted herein.

The shielding structure180, described in the present disclosure, may be applied to various types of semiconductor packages other than the above-described semiconductor packages100A,100B, and100C. For example, the shielding structure180may be applied to an epoxy molding compound (EMC) of a package in which semiconductor chips and various components are molded using the EMC. In addition to the semiconductor package, the shielding structure180may be applied to various components or substrates to provide electromagnetic interference shielding.

As described above, a semiconductor package, to which a shielding structure having improved adhesion and reliability is applied, and an electromagnetic interference shielding structure for the semiconductor package may be provided.

In the present disclosure, the terms “lower side”, “lower portion”, “lower surface,” and the like, have been used to indicate a direction toward a mounted surface of the electronic component package in relation to cross sections shown in the drawings, the terms “upper side”, “upper portion”, “upper surface,” and the like, have been used to indicate an opposite direction to the direction indicated by the terms “lower side”, “lower portion”, “lower surface,” and the like. However, these directions are defined for convenience of explanation only, and the claims are not particularly limited by the directions defined, as described above.

The term “an example embodiment” used herein does not always refer to the same example embodiment, and is provided to emphasize a particular feature or characteristic different from that of another example embodiment. However, example embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with another. For example, one element described in a particular example embodiment, even if it is not described in another example embodiment, may be understood as a description related to another example embodiment, unless an opposite or contradictory description is provided therein.

Terms used herein are used only in order to describe an example embodiment rather than to limit the present disclosure. In this case, singular forms include plural forms unless necessarily interpreted otherwise, based on a particular context.