Bipolar transistor device

A bipolar transistor device includes a substrate and at least one first transistor unit. The first transistor unit includes a first doped well of first conductivity type, at least one first fin-based structure and at least one second fin-based structure. The first fin-based structure includes a first gate strip and first doped fins arranged in the first doped well, and the first gate strip is floating. The second fin-based structure includes a second gate strip and second doped fins arranged in the first doped well, and the second gate strip is floating. The first doped fins, the second doped fins and the first doped well form first BJTs, and the first doped fins and the second doped fins are respectively coupled to high and low voltage terminals.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to a transistor device, particularly to a bipolar transistor device.

Description of the Related Art

The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.).

For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. However, the smaller feature size may lead to more leakage current. As the demand for even smaller electronic devices has grown recently, there has grown a need for reducing leakage current of semiconductor devices.

As semiconductor technologies evolve, fin field effect transistors (FinFETs) have emerged as an effective alternative to further reduce leakage current in semiconductor devices. In a FinFET, an active region including the drain, the channel region and the source protrudes up from the surface of the semiconductor substrate upon which the FinFET is located. The active region of the FinFET, like a fin, may be rectangular in shape from a cross section view. In addition, the gate structure of the FinFET wraps the active region around three sides like an upside-down U. As a result, the gate structure's control of the channel has become stronger. The short channel leakage effect of conventional planar transistors has been reduced. As such, when the FinFET is turned off, the gate structure can better control the channel so as to reduce leakage current. Semiconductor devices including FinFETs are susceptible to extremely high voltage spikes such as an electrostatic discharge (ESD) transient. ESD is a rapid discharge that flows between two objects due to the built-up of static charge. ESD may destroy semiconductor devices because the rapid discharge can produce a relatively large current.

To overcome the abovementioned problems, the present invention provides a bipolar transistor device, so as to solve the afore-mentioned problems of the prior art.

SUMMARY OF THE INVENTION

A primary objective of the present invention is to provide a bipolar transistor device, which uses two fin-based structures arranged in a doped well to establish BJTs which discharge uniform electrostatic discharge (ESD) currents, so as to reduce the semiconductor failures due to ESD.

To achieve the abovementioned objectives, the present invention provides a bipolar transistor device, which comprises a substrate and at least one first transistor unit. For example, the substrate is a semiconductor substrate. The first transistor unit further comprises a first doped well of first conductivity type arranged in the substrate, at least one first fin-based structure and at least one second fin-based structure.

The first fin-based structure further comprises a first gate strip, a plurality of first doped fins and two first contacts. The first gate strip comprises polysilicon. The first doped fins are uniformly arranged in the first doped well, and arranged along a first direction, and each first doped fin has a first doped region of the first conductivity type and two first heavily doped regions of second conductivity type, and each first doped region is arranged between the two first heavily doped regions corresponded thereof, and the first doped regions and the first heavily doped regions are arranged in the first doped well and protruded up from a surface of the substrate. The first gate strip is arranged on tops and sidewalls of the first doped regions and the surface of the substrate, and arranged along a second direction intersecting the first direction, and the first gate strip is floating. For example, the second direction is perpendicular to the first direction. Besides, the first conductivity type is a P type and the second conductivity type is an N type. Alternatively, the first conductivity type is an N type and the second conductivity type is a P type. The first contacts are respectively arranged on sidewalls and tops of the first heavily doped regions at two opposite sides of the first doped regions and the surface of the substrate, and arranged along the second direction, and the first heavily doped regions are coupled to a high voltage terminal via the first contacts.

The second fin-based structure further comprises a second gate strip, a plurality of second doped fins and two second contacts. The second gate strip comprises polysilicon. The second doped fins are uniformly arranged in the first doped well, and arranged along the first direction, and each second doped fin has a second doped region of the first conductivity type and two second heavily doped regions of the second conductivity type, and each second doped region is arranged between the two second heavily doped regions corresponded thereof, and the second doped regions and the second heavily doped regions are arranged in the first doped well and protruded up from the surface of the substrate. The second gate strip is arranged on tops and sidewalls of the second doped regions and the surface of the substrate, and arranged along the second direction, and the second gate strip is floating. The second contacts are respectively arranged on sidewalls and tops of the second heavily doped regions at two opposite sides of the second doped regions and the surface of the substrate, and arranged along the second direction, and the second heavily doped regions are coupled to a low voltage terminal via the second contacts.

The first heavily doped regions, the second heavily doped regions and the first doped well form a plurality of first bipolar junction transistors (BJTs). Voltages of the high voltage terminal and the low voltage terminal bias the first BJTs to generate a plurality of first electrostatic discharge (ESD) currents through the first BJTs.

In the first embodiment, the amount of the first transistor unit, the first fin-based structure and the second fin-based structure are respectively one, one, and one.

In the second embodiment, there are a plurality of the first fin-based structures and a plurality of the second fin-based structures. The first fin-based structures and the second fin-based structures are arranged in an alternate way.

In the third embodiment, the amounts of the first transistor unit, the first fin-based structure and the second fin-based structure are respectively one, two, and one. The first transistor unit further comprises a first doped area of the second conductivity type arranged in the first doped well. For example, the first doped area is a doped well. The second fin-based structure is arranged between the first fin-based structures. The second heavily doped regions and the second doped regions are arranged in the first doped area, and the second gate strip is arranged between the first gate strips, and the second gate strip is connected with the first gate strips.

In the fourth embodiment, the amounts of the first transistor unit, the first fin-based structure and the second fin-based structure are respectively two, two, and one. The first transistor unit of the third embodiment is the same to that of the fourth embodiment. Compared with the third embodiment, the fourth embodiment further comprises at least one second transistor unit. The second transistor unit further comprises a second doped well of the second conductivity type, a second doped area of the first conductivity type, two third fin-based structures and a fourth fin-based structure. For example, the second doped area is a doped well. The second doped well is arranged in the substrate, and the second doped area is arranged in the second doped well.

Each third fin-based structure comprises a third gate strip, a plurality of third doped fins and two third contacts. The third gate strip comprises polysilicon. The third doped fins are uniformly arranged in the second doped well, and arranged along the first direction, and each third doped fin has a third doped region of the second conductivity type and two third heavily doped regions of the first conductivity type, and each third doped region is arranged between the two third heavily doped regions corresponded thereof, and the third doped regions and the third heavily doped regions are arranged in the second doped well and protruded up from the surface of the substrate, and the third heavily doped regions are coupled to the low voltage terminal. The third gate strip is arranged on tops and sidewalls of the third doped regions and the surface of the substrate, and arranged along the second direction, and the third gate strip is floating. The third contacts are respectively arranged on sidewalls and tops of the third heavily doped regions at two opposite sides of the third doped regions and the surface of the substrate, and arranged along the second direction, and the third heavily doped regions are coupled to the low voltage terminal via the third contacts.

The fourth fin-based structure comprises a fourth gate strip, a plurality of fourth doped fins and two fourth contacts. The fourth gate strip comprises polysilicon. The fourth doped fins are uniformly arranged in the second doped area, and arranged along the first direction, and each fourth doped fin has a fourth doped region of the first conductivity type and two fourth heavily doped regions of the second conductivity type, and each fourth doped region is arranged between the two fourth heavily doped regions corresponded thereof, and the fourth doped regions and the fourth heavily doped regions are arranged in the second doped area and protruded up from the surface of the substrate, and the fourth heavily doped regions are coupled to the high voltage terminal. The fourth gate strip is arranged on tops and sidewalls of the fourth doped regions and the surface of the substrate, and arranged along the second direction, and the fourth gate strip is floating. The fourth contacts are respectively arranged on sidewalls and tops of the fourth heavily doped regions at two opposite sides of the fourth doped regions and the surface of the substrate, and arranged along the second direction, and the fourth heavily doped regions are coupled to the high voltage terminal via the fourth contacts.

The fourth gate strip is arranged between the third gate strips, and the fourth gate strip is connected with the third gate strips. The third heavily doped regions, the fourth heavily doped regions, the second doped well and the second doped area form a plurality of second BJTs, and the voltages of the high voltage terminal and the low voltage terminal bias the second BJTs to generate a plurality of second ESD currents through the second BJTs. The first doped wells are adjacent to the second doped well in an alternate way, and the first doped areas are adjacent to the second doped area in an alternate way.

In addition, there are also a plurality of first transistor units and a plurality of second transistor units in the fourth embodiment. Each second transistor unit corresponds to two first transistor units.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to embodiments illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. In the drawings, the shape and thickness may be exaggerated for clarity and convenience. This description will be directed in particular to elements forming part of, or cooperating more directly with, methods and apparatus in accordance with the present disclosure. It is to be understood that elements not specifically shown or described may take various forms well known to those skilled in the art. Many alternatives and modifications will be apparent to those skilled in the art, once informed by the present disclosure.

The bipolar transistor device of the present invention is used as an electrostatic discharge (ESD) protection structure needed for integrated circuits. In ESD protection, an ESD circuit is formed near integrated circuit terminals such as input and output pads, and also for power supply terminals. ESD protection circuits may provide a current discharge path so as to reduce the semiconductor failures due to ESD.

Refer toFIG. 1,FIG. 2,FIG. 3andFIG. 4. The first embodiment of the bipolar transistor device of the present invention is introduced as below. The first embodiment of the present invention comprises a substrate10and at least one first transistor unit12. For example, the substrate10is a semiconductor substrate. The first transistor unit12further comprises a first doped well14of first conductivity type arranged in the substrate10, at least one first fin-based structure16and at least one second fin-based structure18. The first fin-based structure16and the second fin-based structure18are independent devices. There is no electrode shared between the first fin-based structure16and the second fin-based structure18.

The first fin-based structure16further comprises a first gate strip20, a plurality of first doped fins22and two first contacts24. The first gate strip20comprises polysilicon. The first doped fins22are uniformly arranged in the first doped well14, and arranged along a first direction, and each first doped fin22has a first doped region221of the first conductivity type and two first heavily doped regions222of second conductivity type, and each first doped region221is arranged between the two first heavily doped regions222corresponded thereof, and the first doped regions221and the first heavily doped regions222are arranged in the first doped well14and protruded up from a surface of the substrate10. The first gate strip20is arranged on tops and sidewalls of the first doped regions221and the surface of the substrate10, and arranged along a second direction intersecting the first direction, and the first gate strip20is floating. For example, the second direction is perpendicular to the first direction. The first contacts24are respectively used as a source and a drain. The first contacts24are respectively arranged on sidewalls and tops of the first heavily doped regions222at two opposite sides of the first doped regions221and the surface of the substrate10, and arranged along the second direction, and the first heavily doped regions222are coupled to a high voltage terminal VH via the first contacts24.

The second fin-based structure18further comprises a second gate strip26, a plurality of second doped fins28and two second contacts30. The second gate strip26comprises polysilicon. The second doped fins28are uniformly arranged in the first doped well14, and arranged along the first direction, and each second doped fin28has a second doped region281of the first conductivity type and two second heavily doped regions282of the second conductivity type, and each second doped region281is arranged between the two second heavily doped regions282corresponded thereof, and the second doped regions281and the second heavily doped regions282are arranged in the first doped well14and protruded up from the surface of the substrate10. The second gate strip30is arranged on tops and sidewalls of the second doped regions281and the surface of the substrate10, and arranged along the second direction, and the second gate strip30is floating. The second contacts30are respectively used as a source and a drain, respectively arranged on sidewalls and tops of the second heavily doped regions282at two opposite sides of the second doped regions281and the surface of the substrate10, and arranged along the second direction, and the second heavily doped regions282are coupled to a low voltage terminal VL via the second contacts30.

In the first embodiment, the amount of the first transistor unit12, the first fin-based structure16and the second fin-based structure18are respectively one, one, and one.

Besides, the first conductivity type is an N type and the second conductivity type is a P type. In such a case, the first fin-based structure16cooperates with the first doped well14to form a PMOSFET32, and the second fin-based structure18cooperates with the first doped well14to form a PMOSFET34, as shown inFIG. 5. Alternatively, the first conductivity type is a P type and the second conductivity type is an N type. In such a case, the first fin-based structure16cooperates with the first doped well14to form an NMOSFET36, and the second fin-based structure18cooperates with the first doped well14to form an NMOSFET38, as shown inFIG. 6. The first heavily doped regions222, the second heavily doped regions282and the first doped well14form a plurality of first bipolar junction transistors (BJTs). Voltages of the high voltage terminal VH and the low voltage terminal VL bias the first BJTs to generate a plurality of first electrostatic discharge (ESD) currents through the first BJTs. In the first embodiment, the first ESD currents flow in a single direction.

Refer toFIG. 1,FIG. 2,FIG. 3,FIG. 4andFIG. 7. The second embodiment of the bipolar transistor device of the present invention is introduced as below. The second embodiment of the present invention is different from the first embodiment in the amounts of the first fin-based structures16and a plurality of the second fin-based structures18. In the second embodiment, there are a plurality of the first fin-based structures16and a plurality of the second fin-based structures18. The first fin-based structures16and the second fin-based structures18are arranged in an alternate way. In the second embodiment, the first ESD currents flow in up, down, left and right directions.

Refer toFIG. 1,FIG. 8,FIG. 9,FIG. 10, andFIG. 11. The third embodiment of the bipolar transistor device of the present invention is introduced as below. The difference between the first embodiment and the third embodiment is described as below. In the third embodiment, the amounts of the first transistor unit12, the first fin-based structures16and the second fin-based structure18are respectively one, two, and one. Compared with the first embodiment, the first transistor unit12of the third embodiment further comprises a first doped area40of the second conductivity type arranged in the first doped well14. For example, the first doped area40is a heavily doped well. The second fin-based structure18is arranged between the two first fin-based structures16. The second heavily doped regions282and the second doped regions281are arranged in the first doped area40, and the second gate strip26is arranged between the first gate strips20, and the second gate strip26is connected with the first gate strips20.

In addition, the first conductivity type is an N type and the second conductivity type is a P type. In such a case, the first fin-based structures16cooperates with the first doped well14to form two PMOSFETs42, and the second fin-based structure18cooperates with the first doped area40to form an P-type heavily doped area44, as shown inFIG. 12. Alternatively, the first conductivity type is a P type and the second conductivity type is an N type. In such a case, the first fin-based structures16cooperates with the first doped well14to form an NMOSFETs46, and the second fin-based structure18cooperates with the first doped area40to form an N-type heavily doped area48, as shown inFIG. 13. The first heavily doped regions222, the second heavily doped regions282, the first doped well14and the first doped area40form a plurality of first BJTs. Voltages of the high voltage terminal VH and the low voltage terminal VL bias the first BJTs to generate a plurality of first ESD currents through the first BJTs. In the third embodiment, the first ESD currents flow in up and down directions.

Refer toFIG. 8,FIG. 9,FIG. 10, andFIG. 11,FIG. 14,FIG. 15andFIG. 16. The fourth embodiment of the bipolar transistor device of the present invention is introduced as below. The difference between the fourth embodiment and the third embodiment is described as below. In the fourth embodiment, the amounts of the first transistor units12, the first fin-based structures16and the second fin-based structure18are respectively two, two, and one. The first transistor unit12of the third embodiment is the same to that of the fourth embodiment. Compared with the third embodiment, the fourth embodiment further comprises at least one second transistor unit50. In the fourth embodiment, the amount of the second transistor unit50is one. The second transistor unit50further comprises a second doped well52of the second conductivity type, a second doped area54of the first conductivity type, two third fin-based structures56and a fourth fin-based structure58. For example, the second doped area54is a heavily doped well. The second doped well52is arranged in the substrate10, and the second doped area54is arranged in the second doped well52.

Each third fin-based structure56comprises a third gate strip60, a plurality of third doped fins62and two third contacts64. The third gate strip60comprises polysilicon. The third doped fins62are uniformly arranged in the second doped well52, and arranged along the first direction, and each third doped fin62has a third doped region621of the second conductivity type and two third heavily doped regions622of the first conductivity type, and each third doped region621is arranged between the two third heavily doped regions622corresponded thereof, and the third doped regions621and the third heavily doped regions622are arranged in the second doped well52and protruded up from the surface of the substrate10. The third gate strip60is arranged on tops and sidewalls of the third doped regions621and the surface of the substrate10, and arranged along the second direction, and the third gate strip60is floating. The third contacts64are respectively used as a source and a drain. The third contacts64are respectively arranged on sidewalls and tops of the third heavily doped regions622at two opposite sides of the third doped regions621and the surface of the substrate10, and arranged along the second direction, and the third heavily doped622regions are coupled to the low voltage terminal VL via the third contacts64.

The fourth fin-based structure58comprises a fourth gate strip66, a plurality of fourth doped fins68and two fourth contacts70. The fourth gate strip66comprises polysilicon. The fourth doped fins68are uniformly arranged in the second doped area54, and arranged along the first direction, and each fourth doped fin68has a fourth doped region681of the first conductivity type and two fourth heavily doped regions682of the second conductivity type, and each fourth doped region681is arranged between the two fourth heavily doped regions682corresponded thereof, and the fourth doped regions681and the fourth heavily doped regions682are arranged in the second doped area54and protruded up from the surface of the substrate10. The fourth gate strip66is arranged on tops and sidewalls of the fourth doped regions681and the surface of the substrate10, and arranged along the second direction, and the fourth gate strip66is floating. The fourth contacts70are respectively used as a source and a drain. The fourth contacts70are respectively arranged on sidewalls and tops of the fourth heavily doped regions682at two opposite sides of the fourth doped regions681and the surface of the substrate10, and arranged along the second direction, and the fourth heavily doped regions682are coupled to the high voltage terminal VH via the fourth contacts70.

The fourth gate strip66is arranged between the third gate strips60, and the fourth gate strip66is connected with the third gate strips60. The third heavily doped regions622, the fourth heavily doped regions682, the second doped well52and the second doped area54form a plurality of second BJTs, and the voltages of the high voltage terminal VH and the low voltage terminal VL bias the second BJTs to generate a plurality of second ESD currents through the second BJTs. The first doped wells14are adjacent to the second doped well52in an alternate way, and the first doped areas40are adjacent to the second doped area54in an alternate way. In the fourth embodiment, the first ESD currents and the second ESD current flow in up, down, left and right directions.

In addition, there are also a plurality of first transistor units12and a plurality of second transistor units50in the fourth embodiment. Each second transistor unit50corresponds to two first transistor units12.

In conclusion, the present invention uses the fin-based structures to establish BJTs which discharge uniform ESD currents, so as to reduce the semiconductor failures due to ESD.