Soft error detection and correction by 2-dimensional parity

The parity of this invention includes two arrays of parities surrounding the memory. One array is generated in parallel. The other array is generated in serial. The two dimensional parity is used to protect, locate and correct errors automatically. The second parity is provided for only a subset of the address range of the memory. The memory controller does not compare the second parities unless there is a soft error in the first parity. The second parities are calculated upon command and not upon each memory write as the first parity.

CLAIM OF PRIORITY

TECHNICAL FIELD OF THE INVENTION

The technical field of this invention is memory error correction.

BACKGROUND OF THE INVENTION

Due to the decreasing size of memory elements their susceptibility to value corruption due to radiation induced effects from cosmic radiation is becoming a noticeable problem in some critical applications. Even within these applications, some memory uses are more vulnerable than others. Errors to the operating program can be very serious as they can lead to indefinite malfunctioning of the equipment. Such errors often require the device to be reset. Other errors in the data memory are considerably less dangerous for some applications because there is often some ambiguity as to the data anyway. In these cases the soft-error only causes a marginal increase in this ambiguity. This may be undetectable. This invention is a method for protecting the critical program memory for these types of applications. This invention also gives some limited protection to other memory uses like constant data.

Traditionally memories are protected by generating a number of parallel bits based on Hamming codes on a one-dimensional array of data bits often referred to as a memory line. This invention is a method of reducing the overhead of protecting memory from the rare radiation induced memory events. This invention employs just one bit of traditional parallel generated parity per memory line and a second serially generated parity bit per location in the memory line.

SUMMARY OF THE INVENTION

Two arrays of parities surround the memory. One array is generated in parallel. The other array is generated in serial. This increases the memory size by 0.5%. The two dimensional parity is used to protect, locate and correct the errors automatically. The incidence of digital signal processors crashing in remote locations due to radiation induced soft errors is reduced by about 99% using this technique.

This invention uses less extra logic than conventional techniques for relatively high speed correction. This extra logic requires approximately 0.5% overhead. This invention uses smaller and cheaper circuits than conventional techniques.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

FIG. 1illustrates a memory employing this invention. Memory100as a 2-dimensional array of bits arranged in rows and columns. Read and write accesses to memory100are controlled by memory manager110. Address decoder120receives the accessed address from memory manager110and selects a corresponding row of memory100for access. This row access also access parity data stored in parallel generated parities130. On read accesses parallel generated parities130generates a new parity from the just accessed data line. Parallel generated parities130compares this newly calculated parity with the corresponding stored parity. Parallel generated parities130transmits an active soft error (SER) signal to memory manager110if these do not match.

When this SER signal is detected, memory manager110produces a non maskable interrupt (NMI) or other high priority event to the data processor. Error bit register135stores a reduced address of the memory line upon receipt of the soft error signal form parallel generated parities103. For example, for a 256-bit memory line, all bits except the 5 least significant bits are written to this register. Memory manager110responds to the SER signal differently depending on the address accessed. Serial generated parities140generates a parity for individual columns of memory100if the accessed address is within a range of addresses having pre-calculated parties stored in pre-calculated parities145. Limitation to a subset range of addresses limits the amount of serial parity data that must be stored in pre-calculated parities145.

FIG. 2illustrates process200for generating the parity stored in pre-calculated parities145. Process200begins at start block201. Process200receives an indication of the address range (processing block202). This indication could be: a start address and an end address; a start address and a range length; or other means to designate a range of addresses. This range of addresses need not be contiguous. Process200then calculates the parity for each column for the rows within the range of addresses (processing block203). Process200then stores these parities (processing block204). Process200then completes (end block205).

In the preferred embodiment the range of addresses selected corresponds to critical stored information. As an example, this range of addresses could be selected to include the data processor program instructions or at least a critical subset of these instructions. Alternatively, the range of addresses may be selected to include critical data such as constants used in the program.

Parallel generated parities130produces parallel horizontal parities across the 256-bit word width of the memory. Parallel generated parities130produces a parity error when at least one bit of the memory line is corrupted by radiation. Serial generated parities140provides a separate vertical parity, because these bits go vertically through the memory. Thus each bit in the memory is effectively protected by 2 parity bits, the parallel horizontal bit and the serial vertical bit.

FIG. 3illustrates process300for memory reads including the horizontal and vertical parity of this invention. Process300begins at start block301. Process300recalls the addressed data and the corresponding parity (processing block302) Process300calculates the parity of the just recalled data (processing block303).

Process300checks to determine if the recalled parity matches the newly calculated parity (decision block304). If they match (Yes at decision block304), the data is assumed to be correct. Process300continues at block305. This would involve the use of the just recalled data by the data processor.

If they do not match (No at decision block304), then process300checks to determine if the accessed data is within the address range covered by the serial parity (decision block306). As previously described, the pre-calculated parities145cover only a subset of the address range of memory100. If the accessed address is outside the address range (No at decision block306), then this error cannot be corrected by this invention (processing block307). Process300enters an error recovery routine (processing block308). The exact nature of this error recovery routine is beyond the scope of this invention. However, this could involve reloading the accessed data from another memory, reloading the accessed data from a non-volatile memory such as a magnetic or optical disk and restarting the current program running on the data processor. Process300continues at block305following error recovery.

If the accessed data was within the address range (Yes at decision block306), then process300calculates the parity along the other dimension for each bit within the address range (processing block309). This calculation takes place in serial generated parities140. Process300next compares these newly generated parities against pre-calculated parties145(decision block310). There are three types of comparison outcomes. It is possible that plural parity bits do not match (Plural Bits at decision block310). This indicates that plural bits of the originally accessed data have changed. Process300judges this an uncorrectable error (processing block307). This error cannot be corrected by this invention (processing block307). Process300enters an error recovery routine (processing block308) and continues at block305following error recovery.

The second possible result of the parity comparison is one bit does not match (One Bit at decision block310). This indicates an error in a single bit which can be corrected by this invention (processing block311). The vertical/serial parity showing the non-match identifies the column of the memory error. The original access address identifies the row of the memory error. Thus process300identifies and corrects this data error (processing block312). Process300continues at block305following this data correction.

The third possible result of the parity comparison is that no bits fail to match (No Bits at decision block310). This indicates that there are no data errors in the vertical parity data. This would generally occur only if the soft error was in the horizontal parity bit itself (processing block313). Thus the original data was correct but an error in the parity bit caused the parity mismatch (No at decision block304). Process300corrects this at processing block314. This correction could be recalculation of the parity of the horizontal memory line or simple inversion of the parity bit. Process300continues at block305following this parity correction.