Memory modules and methods of operating same

A memory module includes a first memory device, a second memory device, and a processing buffer circuit that is connected to the first memory device and the second memory device (independently of each other) and a host. A processing buffer circuit is provided, which includes a processing circuit and a buffer. The processing circuit processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host. The buffer is configured to store data processed by the processing circuit. The processing buffer circuit is configured to communicate with the host in compliance with a DDR SDRAM standard.

REFERENCE TO PRIORITY APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0070658, filed Jun. 11, 2020, the disclosure of which is hereby incorporated herein by reference.

BACKGROUND

Embodiments of the inventive concept described herein relate to memory modules and methods of operating same, and, more particularly, to memory modules capable of performing an offloaded operation through a standard memory interface and methods of operating same.

A memory device may store data input from an external host. Also, the memory device may output data stored therein in response to a request from the external host. A substrate on which one or more memory devices and one or more parts associated with the memory devices are mounted may be referred to as a “memory module”. A memory module including a processor capable of processing data may perform an operation on data stored in the memory module, based on a command received from the host. In other words, the memory module may have a near data processing (NDP) structure.

SUMMARY

Embodiments of the inventive concept provide a memory module, which includes a processor that supports an offloaded operation(s) using a standard DDR memory interface, and which is capable of accessing data in the memory module without intervention of a host, and methods of operating same.

According to an exemplary embodiment, a memory module may include a first memory device, a second memory device, and a processing buffer circuit. This processing buffer circuit is connected to the first memory device and the second memory device (independently of each other) and is connected to a host. The processing buffer circuit may include a processing circuit that processes at least one of data received from the host, data stored in the first memory device, or data stored in the second memory device based on a processing command received from the host, and a buffer that stores data processed by the processing circuit. The processing buffer circuit may communicate with the host in compliance with a DDR SDRAM standard.

According to an exemplary embodiment, an operating method may be provided for a memory module, which includes a normal memory channel and a processing memory channel, and with each of the normal memory channel and the processing memory channel sharing a router of a processing buffer circuit (and including a memory cell array). This method may include setting an operating mode of the router to one of an extension mode or a mirror mode, based on a mode register set command received from a host. In addition, data stored in the normal memory channel and the processing memory channel is accessed based on an address and a command received from the host and the set operating mode of the router (i.e., extension mode or mirror mode). Then, the accessed data is processed at a processing circuit included in the processing buffer circuit, based on a processing command received from the host. The mode register set command, the address, the command, and the processing command may be transmitted from the host to the memory module in compliance with a DDR SDRAM standard.

According to another exemplary embodiment, a memory module may include a processing buffer chip, and one or more DRAM chips that store data. The one or more DRAM chips may form a normal memory channel and a processing memory channel. The processing buffer chip may include a physical layer that receives a command/address signal and a data signal from a host, as well as a first memory controller and a second memory controller that respectively access the normal memory channel and the processing memory channel based on the command/address signal. A processing circuit is also provided that processes at least a portion of data stored in the normal memory channel accessed through the first memory controller and data stored in the processing memory channel accessed through the second memory controller, based on a processing command included in the data signal. In addition, a buffer is provided that stores data processed by the processing circuit, and a router is provided that receives the command/address signal and the data signal from the physical layer and transmits the command/address signal and the data signal to the first memory controller and the buffer. The processing buffer circuit communicates with the host in compliance with a DDR SDRAM standard.

DETAILED DESCRIPTION

Below, embodiments of the inventive concept may be described in detail and clearly to such an extent that an ordinary one in the art easily implements the inventive concept. Hereinafter, the best embodiment of the inventive concept will be described in detail with reference to accompanying drawings. With regard to the description of the inventive concept, to make the overall understanding easy, similar components will be marked by similar reference signs/numerals in drawings, and thus, additional description will be omitted to avoid redundancy.

FIG.1illustrates a memory system according to an embodiment of the inventive concept. Referring toFIG.1, a memory system10may include a memory module100, a host200, and a connecting line300. The memory module100may include a processing buffer circuit110and one or more memory devices120. The processing buffer circuit110may be connected to the memory devices120. The processing buffer circuit110may access storage spaces of the memory devices120. The processing buffer circuit110may process data stored in the memory devices120or data received from the host200, based on a request of the host200. An operation of the processing buffer circuit110will be more fully described later. In an embodiment, the memory module100may include a structure capable of performing near data processing (NDP). The memory module100may be also referred to as a “process-in-memory (PIM)” or a function-in-memory (FIM)”.

An embodiment is illustrated as the number of memory devices120is “n” (n being a positive integer greater than one). In other words, the memory module100may include first to n-th memory devices121to12n. The number of memory devices120included in the memory module100is not limited to the illustrated embodiment. Each of the memory devices120may include a memory cell array including a plurality of memory cells. In an embodiment, each of the first to n-th memory devices121to12nmay be implemented with a dynamic random access memory (DRAM).

The host200may be also referred to as a “central processing unit (CPU)”. The host200may include a memory controller (MC)210. The host200may issue or generate signals for accessing the memory devices120. For example, the host200may generate data to be stored in the memory devices120or a data signal DQ indicating an operation to be performed by the processing buffer circuit110, a command signal CMD directing the memory devices120to perform a specific operation such as a read or write operation, and an address signal ADD indicating a physical address of a storage space of each of the memory devices120. The command signal CMD and the address signal ADD may be collectively referred to as a “command/address signal CA”.

A memory controller210may transmit the data signal DQ, the command signal CMD, the address signal ADD, etc. generated by the host200to the memory module100through the connecting line300. The memory controller210may include an address mapping table (not illustrated). The address mapping table of the memory controller210may map a virtual address, which the host200allocates to the memory module100, and a physical address of the memory module100. For example, the address mapping table may store physical addresses respectively corresponding to the first to n-th memory devices121to12nand virtual addresses respectively corresponding to the physical addresses. The host200may generate the address signal ADD, based on an address stored in the address mapping table of the memory controller210.

The memory module100may communicate with the memory controller210of the host200through the connecting line300. For example, the memory controller210may transmit the data signal DQ, the command signal CMD, and the address signal ADD generated by the host200to the memory module100through the connecting line300. The connecting line300may be implemented in compliance with the double data rate (DDR) standard. For example, the connecting line300may satisfy the DDR synchronous DRAM (SDRAM) standard defined by the JEDEC (Joint Electron Device Engineering Council).

In an embodiment, the processing buffer circuit110of the memory module100may perform an operation directed by a processing command (e.g., CMDP ofFIG.2) included in the data signal DQ received from the host200through the connecting line300. As such, the host200may offload an operation to be performed to the processing buffer circuit110of the memory module100through the connecting line300satisfying the DDR SDRAM standard. According to the above description, the memory module100may receive a request associated with performing the operation from the host200without a separate hardware change.

FIG.2illustrates a block diagram of a memory module ofFIG.1in detail. Referring toFIGS.1and2, the memory module100may include the processing buffer circuit110and the first to fourth memory devices121to124. Some components belonging to the memory module100may be included in a normal channel (or a normal memory channel) C1, and other components thereof may be included in a processing memory channel C2. Other components included in the memory module100may be included in an interface unit IF. Components of the normal memory channel C1, the processing memory channel C2, and the interface unit IF will be more fully described hereinbelow.

In an embodiment, at least one memory device of the first to fourth memory devices121to124may be classified as (or allocated to) the normal memory channel C1, and the other memory devices may be classified as (or allocated to) to the processing memory channel C2. An embodiment is illustrated as including the first and second memory devices121and122within the normal memory channel C1and the third and fourth memory devices123and124within the processing memory channel C2. However, a way to classify the first to fourth memory devices121to124is not limited thereto. For example, the first to fourth memory devices121to124may be differently classified by a mode register113. An operation of the mode register113will be described more fully hereinbelow.

In an embodiment, each of the normal memory channel C1and the processing memory channel C2may include a memory cell array, and the normal memory channel C1and the processing memory channel C2may share some components (e.g., the interface unit IF) of the processing buffer circuit110. In another embodiment, each of the normal memory channel C1and the processing memory channel C2may include at least one or more memory devices and at least some components of the processing buffer circuit110. For example, the processing memory channel C2may include the mode register113, a buffer114, a processing circuit115, a master physical layer116p, and memory devices120pclassified as the processing memory channel C2. For another example, the normal memory channel C1may include a master physical layer116nand memory devices120nclassified as the normal memory channel C1. The memory devices120nand120pmay be disposed at ends of the normal memory channel C1and the processing memory channel C2, respectively.

The processing buffer circuit110may include a slave physical layer111, a router112, the mode register113, the buffer114, and one or more master physical layers116nand116p. The master physical layers116nand116pmay be also referred to as a “memory controller”. The interface unit IF of the processing buffer circuit110may include the slave physical layer111and the router112.

The slave physical layer111may be connected to the memory controller210of the host200through the connecting line300. The slave physical layer111may receive the data signal DQ, the command signal CMD, and the address signal ADD from the memory controller210of the host200. The slave physical layer111may remove signal noise included in the data signal DQ, the command signal CMD, and the address signal ADD thus received. For example, the slave physical layer111may perform retiming or sampling on the data signal DQ, the command signal CMD, and the address signal ADD thus received. The slave physical layer111may transmit noise-free signals to the router112and the mode register113.

The router112may allow the host200to access the memory devices120nclassified as the normal memory channel C1and the memory devices120pclassified as the processing memory channel C2, based on the address signal ADD, the noise of which is removed by the slave physical layer111. For example, the router112may provide the host200with storage spaces of the memory devices120nand120pand the buffer114as an access target. With regard to data stored in one of the memory devices120, the router112may determine whether a normal operation such as a data read/write operation is performed or whether a separate operation (or data processing) is performed using the processing circuit115.

In an embodiment, the router112may operate in one of an extension mode or a mirror mode. An operating mode of the router112will be more fully described later.

The mode register113may store information about an operating condition of the memory module100depending on a request of the host200. The host200may set the operating mode of the memory module100by issuing the command signal CMD including a mode register set command MRS for setting an operation of the mode register113. The mode register set command MRS may be transmitted to the mode register113through the slave physical layer111in the form of a digital signal.

In an embodiment, the mode register113may further include a register circuit for storing information about a normal command (e.g., a burst length set command) for controlling a memory module including a DRAM and a register circuit for storing information about an operating mode of the processing circuit115. In this case, the mode register set command MRS may further include a command for setting an operating mode of the router112, a command for setting an operating mode of the processing circuit115or for permitting all or a part of operations of the processing circuit115, etc.

The processing circuit115may read an operating signal OP stored in the mode register113through the mode register set command MRS. The operating signal OP may be a signal associated with a command for setting an operating mode of the processing circuit115. In an embodiment, the processing circuit115may activate or deactivate the whole processing circuit115or a portion of the processing circuit115in response to information stored in the mode register113through the mode register set command MRS. An operation of the processing circuit115will be more fully described later.

The router112may operate in one of the extension mode or the mirror mode, based on information stored in the mode register113through the mode register set command MRS. An embodiment is illustrated, for ease of illustration, as a connecting line between the router112and the mode register113is omitted. In an embodiment, the router112may reconfigure (or change) settings (or configurations) of the memory devices120nand120pcapable of being accessed by the host200depending on information stored in the mode register113through the mode register set command MRS. For example, the router112may classify at least one of the first to fourth memory devices121to124as the normal memory channel C1and the remaining memory devices as the processing memory channel C2, in response to the information stored in the mode register113. According to the above description, the host200may change a configuration of the normal memory channel C1and the processing memory channel C2by issuing the mode register set command MRS.

The buffer114may store information about an operation to be performed by the processing circuit115, data MDN stored in the memory devices120nclassified as the normal memory channel C1, and data PMD processed by the processing circuit115. For example, the buffer114may receive a processing command CMDP and the data MDN from the router112. And, in response, the buffer114may provide the processing circuit115with the processing command CMDP and the data MDN thus received. In an embodiment, the processing command CMDP that is included in the data signal DQ may be transmitted from the host200to the memory module100. This processing command CMDP may be included in a burst of the data signal DQ in the form of a series of packets complying with a given format.

For example, the processing command CMDP may include an operation code (OP code) indicating a kind of an operation to be performed by the processing circuit115, a code src indicating an address of a source, a code dest (or dst) indicating an address of a destination, etc. According to the above description, the host200may offload an operation to be performed by the processing circuit115to the processing circuit115by requesting an operation of writing the processing command CMDP in the buffer114(or issuing the command signal CMD including a write command) without further transmitting a separate command signal to the memory module100.

The processing circuit115may process at least one of data received from the host200or data stored in the memory devices120nand120pbased on the processing command CMDP stored in the buffer114. The processing circuit115may be also referred to as a “processor”. The processing circuit115may include a decoder circuit DEC, a communication circuit CC, and a logic circuit LC, in some embodiments.

The decoder circuit DEC may decode the processing command CMDP received from the host200. The communication circuit CC may perform data (or signal) communication. For example, the communication circuit CC may receive data stored in the buffer114from the buffer114. The communication circuit CC may receive the data MDP stored in the memory devices120p. The communication circuit CC may transmit the data PMD processed by the processing circuit115to the buffer114or the master physical layer116p. The communication circuit CC may transmit the data MDP received from the memory devices120pto the buffer114.

The logic circuit LC may perform an operation based on the processing command CMDP. For example, the logic circuit LC may include a logic circuit such as a multiply-accumulate operation (MAC) unit, a rectified linear unit (ReLu), or an arithmetic logic unit (ALU). The logic circuit LC may perform an operation requested from the host200, based on a result of decoding the processing command CMDP.

In an embodiment, the processing circuit115may access the data MDN stored in the memory devices120nclassified as the normal memory channel C1. For example, the router112may provide the processing circuit115with the data MDN stored in the memory devices120nclassified as the normal memory channel C1, based on the command signal CMD and the address signal ADD received from the host200. Accordingly, without any additional data handling of the host200, the processing circuit115may perform operations on data stored in the memory devices120nclassified as the normal memory channel C1, as well as data stored in the memory devices120pclassified as the processing memory channel C2.

In another embodiment, the processing circuit115may scrub the memory devices120. For example, the processing circuit115may scrub the memory devices120in response to a scrub request received from the host200in a state of being included in the processing command CMDP. For another example, the processing circuit115may periodically scrub the memory devices120. In this case, a period where the processing circuit115scrubs the memory devices120may be determined in advance when the memory module100is manufactured or may be determined by the host200.

The processing circuit115may transmit the data PMD processed by the logic circuit LC to the buffer114. The host200may access the data PMD processed by the processing circuit115by transmitting a read request for the processed data PMD stored in the buffer114to the memory module100. The processed data PMD stored in the buffer114may be transmitted to the router112in response to a read request of the host200. The router112may provide the host200with a storage space of the buffer114as an access target.

The master physical layers116nand116pmay be respectively connected to the memory devices120nand120p. The master physical layers116nand116pmay receive the data signal DQ, the command signal CMD, and the address signal ADD from the router112through the processing circuit115, based on an operating mode of the router112. The master physical layers116nand116pmay transmit at least a part of digital signals used by respective components of the processing buffer circuit110to the memory devices120nand120p, respectively.

The master physical layers116nand116pmay receive signals associated with data stored in the memory devices120nand120pfrom the memory devices120nand120p, respectively. The master physical layers116nand116pmay receive noise associated with the received signals. The master physical layers116nand116pmay transmit noise-free signals to at least a part of the components of the processing buffer circuit110. As such, the host200and the processing circuit115may access storage spaces of the memory devices120nand120pdisposed at the ends of the normal memory channel C1and the processing memory channel C2through the master physical layers116nand116p, respectively.

FIG.3is a flowchart illustrating an operating method of a memory system ofFIG.1. Referring toFIGS.1to3, the host200of the memory system10may perform operation S100and operation300, and the memory module100of the memory system10may perform operation S200and operation S400. In operation S100, the host200may transmit the mode register set command MRS for setting the mode register113to the memory module100. In an embodiment, operation S100may be performed in an initialization operation after a power-on of the host200.

In operation S200, the memory module100may set an operating mode of the processing circuit115and the router112of the processing buffer circuit110. For example, the memory module100may store the mode register set command MRS in the mode register113. The processing circuit115may read the operating signal OP that is stored in the mode register113through the mode register set command MRS and is used to activate or deactivate a part of the processing circuit115. The router112may operate in the extension mode or the mirror mode, based on an active state of the processing circuit115and a request of the host200.

In operation S300, the host200may transmit the data signal DQ, the command signal CMD, and the address signal ADD to the memory module100. In operation S400, the memory module100may operate on the memory devices120. For example, the memory module100may access the memory devices120, based on the operating mode of the processing circuit115and the router112set in operation S200and the request of the host200. The memory module100may perform an operation requested by the host200on at least a part of the memory devices120, based on the data signal DQ, the command signal CMD, and the address signal ADD received from the host200.

FIG.4Aillustrates a memory map of a memory controller ofFIG.1when a router ofFIG.2is in the mirror mode.FIG.4Billustrates a memory map of a memory controller ofFIG.1when a router ofFIG.2is in the extension mode. In other words,FIGS.4A and4Billustrate memory maps of the memory devices120seen from the host200in the mirror mode and the extension mode, respectively.FIGS.4A and4Bwill be described with reference toFIGS.1to3.

When the router112operates in the mirror mode, the router112may provide the host200with storage spaces of the memory devices120nclassified as the normal memory channel C1and a storage space of the buffer114as an access target. As such, the memory map stored in the memory controller210may include a region401afor the storage space of the buffer114and a region402afor the storage spaces of the memory devices120nclassified as the normal memory channel C1, as illustrated inFIG.4A. An operation of the memory system10when the router112operates in the mirror mode will be more fully described with reference toFIGS.5and7.

When the router112operates in the extension mode, the router112may provide the host200with a storage space of at least a part (e.g.,123) of the memory devices120pclassified as the processing memory channel C2and the storage space of the buffer114, as an access target, as well as the storage spaces of the memory devices120nclassified as the normal memory channel C1. As such, the memory map stored in the memory controller210may include a region401bfor the storage space of the buffer114, a region402bfor the storage spaces of the memory devices120nclassified as the normal memory channel C1, and a region403bfor the storage spaces of the memory devices120pclassified as the processing memory channel C2, as illustrated inFIG.4B. An operation of the memory system10when the router112operates in the extension mode will be more fully described with reference toFIG.6.

FIG.5is a flowchart illustrating an operating method of a memory system ofFIG.1when an operating mode of a router ofFIG.2is determined as a mirror mode. Referring toFIGS.1to3and6, the host200may perform operation S100aand operation S310a, and the memory module100may perform operation S200a, operation S320a, operation S411a, operation S412a, operation S420a, and operation S430a. In the mirror mode, the same data as data to be stored in the storage spaces of the memory devices120nclassified as the normal memory channel C1may be stored in the storage spaces of the memory devices120pclassified as the processing memory channel C2. Data that correspond to data stored in the memory devices120nclassified as the normal memory channel C1and are stored in the memory devices120pclassified as the processing memory channel C2may be also referred to as “mirror data”.

In operation S100a, the host200may transmit the mode register set command MRS, which directs the router112to operate in the mirror mode, to the memory module100. For example, the mode register set command MRS may include a command that allows the router112to operate in the mirror mode and allows the memory devices120to be classified as one of the normal memory channel C1or the processing memory channel C2.

In operation S200a, the memory module100may set an operating mode of the processing circuit115and the router112of the processing buffer circuit110. The router112may operate in the mirror mode in response to the mode register set command MRS. In other words, the router112may provide the host200only with storage spaces of the memory devices120nclassified as the normal memory channel C1and a storage space of the buffer114as an access target.

In operation S310a, the host200may generate a first data signal DQ1, a write command signal CMDW, and the address signal ADD and may transmit the first data signal DQ1, the write command signal CMDW, and the address signal ADD to the memory module100. For example, the write command signal CMDW may include a command directing writing data included in the first data signal DQ1in at least a part of the memory devices120. In operation S320a, the memory module100may be configured to deliver an access of the host200to data stored in the memory devices120nclassified as the normal memory channel C1to the processing memory channel C2.

In an embodiment, the router112may receive a request for accessing the storage spaces of the memory devices120nclassified as the normal memory channel C1from the host200. In this case, the router112may transmit the received request (e.g., the first data signal DQ1, the write command signal CMDW, and the address signal ADD) of the host200to the processing memory channel C2. The processing memory channel C2may write the first data signal DQ1, the write command signal CMDW, and the address signal ADD in the buffer114.

In operation S411a, the normal memory channel C1may perform a write operation based on the first data signal DQ1, the write command signal CMDW, and the address signal ADD thus received. For example, data based on the first data signal DQ1may be written in the storage spaces of the memory devices120n, which corresponds to the address signal ADD.

In operation S412a, the processing memory channel C2may perform a write operation based on the first data signal DQ1, the write command signal CMDW, and the address signal ADD thus received. For example, data based on the first data signal DQ1may be written in the storage spaces of the memory devices120p, which corresponds to the address signal ADD. As such, data that are requested from the host200so as to be written may be stored in each of the normal memory channel C1and the processing memory channel C2.

In operation S420a, the memory module100may perform an operation on the mirror data, based on the processing command CMDP. For example, the processing circuit115may read, write, or process the mirror data stored in the memory devices120p, based on a result of decoding the processing command CMDP written in the buffer114. Moreover, even though the host200accesses the storage spaces of the memory devices120nclassified as the normal memory channel C1, the processing circuit115may simultaneously access the mirror data. In other words, by using a bandwidth in the memory module100, which is independent of the host200, the processing circuit115may access the same data as data accessed by the host200and may perform processing on the same data.

In operation S430a, the memory module100may write the data processed in operation420ain the buffer114. For example, the processing circuit115may transmit the processed data PMD, which are generated as a result of processing the mirror data, to the buffer114. The buffer114may store the processed data PMD received from the processing circuit115, and may provide the stored processed data PMD to the host200in response to a read request for the processed data PMD. As such, the host200may read the data PMD processed by the processing circuit115by accessing a specific storage space of the buffer114.

FIG.6is a flowchart illustrating an operating method of a memory system ofFIG.1when an operating mode of a router ofFIG.2is determined as an extension mode. Referring toFIGS.1to3and6, the host200of the memory system10may perform operation S100b, operation S311b, and operation S312b, and the memory module100of the memory system10may perform operation S200b, operation S411b, and operation S412b.

In operation S100b, the host200may transmit the mode register set command MRS, which directs the router112to operate in the extension mode, to the memory module100. For example, the mode register set command MRS may include a command that allows the router112to operate in the extension mode, allows the memory devices120to be classified as one of the normal memory channel C1or the processing memory channel C2, and is used to control an operating time and an active state of the logic circuit LC of the processing circuit115.

In operation S200b, the memory module100may set an operating mode of the processing circuit115and the router112of the processing buffer circuit110. The router112may operate in the extension mode in response to the mode register set command MRS. An operation of the processing circuit115may be determined depending on the amount of storage spaces of the memory devices120pexposed to the host200through the router112. In an embodiment, the router112may provide the host200with all the storage spaces of the memory devices120pas an access target. In other words, through the router112, the first to n-th memory devices121to12nmay be exposed to or recognized by the host200as one integrated high-capacity memory. In this case, the host200may monopolize the first to n-th memory devices121to12n, or the host200may share the first to n-th memory devices121to12nwith the processing circuit115.

In the case where the first to n-th memory devices121to12nare monopolized by the host200, the mode register113may deactivate the logic circuit LC of the processing circuit115. For example, a power that is supplied to the logic circuit LC of the processing circuit115may be blocked by the operating signal OP that is readable by the processing circuit115. As such, an operation that the processing circuit115performs on data stored in the memory devices120may be inhibited. However, even in this case, a path (e.g., the communication circuit CC) for data communication of the processing circuit115may be still activated. Accordingly, data stored in the memory devices120pmay be provided to the host200through the path for the data communication of the processing circuit115, the buffer114, and the router112.

In another embodiment, in the case where the memory devices120are shared by the host200and the processing circuit115, a time interval where the logic circuit LC of the processing circuit115is activated may be determined based on the mode register set command MRS. In this case, the processing circuit115may perform calculation appointed (or determined or stored) in advance on data stored in the memory devices120. For example, the host200may provide the processing circuit115with the mode register set command MRS including a command that permits the logic circuit LC of the processing circuit115and the host200to access the storage spaces of the memory devices120at different times. As such, the processing circuit115may access the storage spaces of the memory devices120only in a time interval permitted by the host200.

The time interval where the processing circuit115is capable of accessing the storage spaces of the memory devices120may be determined by the host200when an operating mode of the router112is determined. Alternatively, the host200may control an operation of the processing circuit115by issuing the command signal CMD including information about a time interval where the processing circuit115is capable of accessing the storage spaces of the first to n-th memory devices121to12n.

In another embodiment, the router112may provide the host200with all the storage spaces of the memory devices120nand only a portion of the storage spaces of the memory devices120pas an access target. In this alternative case, the remaining storage spaces of the memory devices120p, which is not provided to the host200as an access target, may be accessed only by the processing circuit115. The processing circuit115may access the remaining storage spaces of the memory devices120p, which is not provided to the host200as an access target, based on the processing command CMDP. In this case, a partial storage space of the memory devices120, which is accessed by the host200, may be monopolized by the host200or may be shared by the processing circuit115and the host200.

In the case where the partial storage space of the memory devices120, which is capable of being accessed by the host200, is monopolized by the host200, the processing circuit115may restrictively access the storage space monopolized by the host200. For example, when the host200accesses the storage space monopolized by the host200, the processing circuit115may fail to access the monopolized storage space at the same time with the host200. In other words, the processing circuit115may access the storage space monopolized by the host200only in a time interval permitted by the host200. In this case, the host200may permit the use of the logic circuit LC of the processing circuit115by requesting the buffer114to write the processing command CMDP. Accordingly, in the case where the use of the logic circuit LC of the processing circuit115is permitted by the host200, the processing circuit115may access the storage space monopolized by the host200, based on the processing command CMDP written in the buffer114.

In the case where a partial storage space of the memory devices120, which is capable of being accessed by the host200, is shared by the processing circuit115and the host200, in a scheme similar to that in the case where all the storage spaces of the memory devices120are shared, the processing circuit115may access the partial storage space of the memory devices120, which is capable of being accessed by the host200. For example, the processing circuit115may access the partial storage space of the memory devices120, which is capable of being accessed by the host200, at a time different from that of the host200. In other words, the processing circuit115may access the shared storage space in a time interval permitted by the host200, so that the processing circuit115may perform calculation appointed in advance on data stored in the shared storage space.

In operation S311b, the host200may generate a second data signal DQ2, the command signal CMD, and the address signal ADD and may transmit the second data signal DQ2, the command signal CMD, and the address signal ADD to the memory module100. The second data signal DQ2, the command signal CMD, and the address signal ADD received from the host200may be provided to the memory devices120nclassified as the normal memory channel C1. And, in operation S312b, the host200may generate a third data signal DQ3and may transmit the third data signal DQ3, the command signal CMD, and the address signal ADD to the memory module100. The third data signal DQ3, the command signal CMD, and the address signal ADD received from the host200may be provided to the memory devices120pclassified as the processing memory channel C2. In this case, memory devices to which the third data signal DQ3, the command signal CMD, and the address signal ADD received from the host200are provided may be included in memory devices permitted by the host200so as to be accessed. In an embodiment, operation S311band operation S312bmay be performed at the same time.

In operation S411b, the memory module100may perform an operation based on the second data signal DQ2, the command signal CMD, and the address signal ADD, on the memory devices120nclassified as the normal memory channel C1. For example, the memory module100may write data included in the second data signal DQ2in the storage spaces of the memory devices120n, which corresponds to the address signal ADD. For another example, the memory module100may read data stored in the storage spaces of the memory devices120n, which corresponds to the address signal ADD.

In operation S412b, the memory module100may perform an operation based on the third data signal DQ3, the command signal CMD, and the address signal ADD, on the memory devices120pclassified as the processing memory channel C2. For example, the memory module100may write data included in the third data signal DQ3in the storage spaces of the memory devices120p, which corresponds to the address signal ADD. For another example, the memory module100may read data stored in the storage spaces of the memory devices120p, which corresponds to the address signal ADD.

For another example, the processing buffer circuit110of the memory module100may perform an operation on the data MDN/MDP stored in the memory module100or the data included in the third data signal DQ3, based on the processing command CMDP included in the command signal CMD.

In operation S412b, a storage space capable of being accessed by the processing circuit115may be extended to the memory devices120nclassified as the normal memory channel, in addition to the memory devices120pclassified as the processing memory channel. As such, the processing circuit115may perform an operation on a larger data set than in the case where the storage space capable of being accessed by the processing circuit115is limited to the memory devices120pclassified as the processing memory channel.

FIG.7illustrates a flowchart of an operating method of a memory module ofFIG.1according to an embodiment of the inventive concept. In detail, according to an embodiment of the inventive concept, a flowchart of a method in which the memory module100pre-processes data to accelerate a convolutional neural network (CNN) operation is illustrated inFIG.7. Referring toFIGS.1to3and5to7, the memory module100may perform operation S401cto operation S403c.

In operation S401c, the memory module100may store data received from the host200in a memory device permitted to be accessed by the host200. For example, in the case where the router112operates in the extension mode, the memory module100may store the data received from the host200in a storage space permitted to be accessed by the host200. For another example, in the case where the router112operates in the mirror mode, the memory module100may store the data received from the host200in the memory devices120nclassified as the normal memory channel C1.

In operation S402c, the memory module100may transpose all or a part of the data received from the host200. For example, the processing circuit115may transpose data that are determined by the host200as pre-processing is required.

In operation S403c, the transposed data may be stored in the memory devices120pclassified as the processing memory channel C2or in the buffer114. For example, when the router112operates in the extension mode, all the storage spaces of the memory devices120may be provided to the host200and the processing circuit115as an access target. In this case, the processing circuit115may store the transposed data in any storage space of the memory devices120or in the buffer114.

Alternatively, when the router112operates in the extension mode, only a portion of the storage spaces of the memory devices120pclassified as the processing memory channel C2may be provided to the host200as an access target. In this case, the processing circuit115may store the transposed data in a storage space, which is monopolized by the processing circuit115, from among the storage spaces of the memory devices120p. The transposed data stored in the storage space monopolized by the processing circuit115may be stored in the buffer114in response to a read request for the pre-processed data, which is provided from the host200. The host200may read the transposed data by accessing the storage space of the buffer114.

According to another embodiment, when the router112operates in the extension mode, the processing circuit115may store the transposed data in the buffer114. The host200may read the transposed data by accessing the storage space of the buffer114. Also, when the router112operates in the mirror mode, only a portion of the storage spaces of the memory devices120nclassified as the normal memory channel C1may be provided to the host200as an access target. In this case, the processing circuit115may store the transposed data in storage spaces of the memory devices120pclassified as the processing memory channel C2. The pre-processed data stored in the storage spaces of the memory devices120pmay be stored in the buffer114in response to a read request for the transposed data, which is provided from the host200. The host200may read the transposed data by accessing the storage space of the buffer114. When the router112operates in the mirror mode, data may be transposed by the processing circuit115regardless of whether the host200accesses the memory devices120n. Accordingly, a speed at which data are pre-processed may be improved compared to when the router112operates in the extension mode.

FIG.8Aillustrates cells of a first memory device ofFIG.2, in which data are stored, when complying with the flowchart ofFIG.7.FIG.8Billustrates cells of a third memory device ofFIG.2, in which data are stored, when complying with the flowchart ofFIG.7. Referring toFIGS.1to3,5to7,8A, and8B, a first memory device121amay be one of the memory devices120nclassified as the normal memory channel C1. A third memory device123amay be one of the memory devices120pclassified as the processing memory channel C2.

Data received from the host200may be stored in a memory cell array of the first memory device121ain the form of a matrix as illustrated inFIG.8A. The processing circuit115may transpose data of a matrix form illustrated inFIG.8A. That is, a data cell D12and a data cell D21ofFIG.8Amay be stored in the memory cell array of the third memory device123asuch that locations thereof are changed, as illustrated inFIG.8B. Afterwards, the processing circuit115may provide the transposed data to the host200through the buffer114in response to a read request of the host200.

Data received from the host200may be in the form of a k×l matrix, where k and l are positive integers. In this case, to perform the CNN operation on data stored in a memory device, there may be a need to an access data of a p-th row (p being a positive integer equal to or less than k) and data of a q-th column (q being a positive integer equal to or less than l). The host200may read data a total of k times for the purpose of accessing the data of the q-th column. In contrast, as illustrated inFIG.8B, in the case where data are transposed, the data of the q-th column illustrated inFIG.8Amay be accessed by accessing data of a q-th row belonging to the transposed data. As a result, the host200may read desired data through only one access. This may mean that the performance of the CNN operation performed by the host200is improved by the memory module100.

In an embodiment, the processing circuit115may perform the CNN operation by using the transposed data. The processing circuit115may read at least a portion of the data MDN stored in the memory devices120nclassified as the normal memory channel C1and the data MDP stored in the memory devices120pclassified as the processing memory channel C2. The processing circuit115may perform the CNN operation on the read data and the transposed data. The processing circuit115may store a result of the CNN operation in the buffer114. The memory module100may output the result of the CNN operation stored in the buffer114in response to a read request of the host200. In the above example, the host200may transmit, to the memory module100, data targeted for the CNN operation and the processing command CMDP directing performing the CNN operation. As such, the host200may offload the CNN operation to the processing circuit115.

FIG.9Ais a flowchart illustrating a portion of an operating method of a memory module, when an operating mode of a router ofFIG.2is determined as a mirror mode. Referring toFIGS.1,2, and9A, the memory module100may perform operation S510ato operation S530a. In operation S510a, the memory module100may detect one or more faulty memory cells of the memory devices120nclassified as the normal memory channel C1. For example, the memory module100may continuously receive read requests, the number of which is given, from the host200with regard to any storage space. In this case, the read request that is received from the host200with regard to a storage space of the normal memory channel C1may be transferred to the processing memory channel C2. As such, the processing circuit115may identically receive the read request provided from the host200. The processing circuit115may detect whether a read request associated with the same address is repeatedly received from the host200as much as the given number of times or more. As a result, the processing circuit115may determine that faulty memory cells included in a memory cell array corresponding to a physical address of the corresponding storage space is one or more.

In operation S520a, the memory module100may read data from the storage space of the memory devices120pcorresponding to the storage space of the memory devices120nin which the faulty memory cells are included. For example, the processing circuit115may access the storage space of the memory devices120pclassified as the processing memory channel C2in response to read requests continuously received from the host200. In other words, the processing circuit115may access mirror data corresponding to data stored in the storage space in which the faulty memory cells are included. The processing circuit115may provide the mirror data to the buffer114.

In operation S530a, the memory module100may transmit the mirror data to the host200instead of the data stored in the storage space in which the faulty memory cells are included. For example, in the case where the host200transmits the address signal ADD indicating the storage space of the memory devices120nin which the faulty memory cells are included, to the memory module100, the router112may provide the mirror data stored in the buffer114to the host200. As such, the performance of the memory module100may be improved.

FIG.9Bis a flowchart illustrating a portion of an operating method of a memory module, when an operating mode of a router ofFIG.2is set in a mirror mode of operation. In an embodiment, the memory module100may include a plurality of normal memory channels and a plurality of processing memory channels. Referring toFIGS.1,2, and9B, the memory module100may perform operation S510bto operation S540b.

In operation S510b, the memory module100may copy data stored in memory devices classified as a first normal memory channel to memory devices classified as first to m-th processing memory channels (m being a positive integer) among the plurality of processing memory channels. For example, the router112may transfer an access request for memory devices classified as the first normal memory channel to the memory devices classified as the first to m-th processing memory channels. As such, data received from the host200may be stored in the memory devices classified as the first to m-th processing memory channels. As a result, compared toFIG.9A, the number of copies of the data received from the host200may increase.

In operation S520b, the memory module100may detect the existence of faulty memory cells included in the memory devices classified as the first normal memory channel. In other words, the memory module100may detect a fault of the first normal memory channel. For example, as in the way described in operation S510aofFIG.9, the memory module100may detect the existence of faulty memory cells.

In operation S530b, the memory module100may vote between the memory devices classified as the first to m-th processing memory channels. For example, the memory module100may receive a read request for a storage space, in which faulty memory cells are included, from the host200. The processing circuit115may access the storage spaces of the first to m-th processing memory channels, which corresponds to the storage space in which the faulty memory cells are included, in response to the read request from the host200. The processing circuit115may read first to m-th candidate data respectively stored in the first to m-th processing memory channels.

The processing circuit115may compare the first to m-th candidate data with each other and may determine mirror data corresponding to data stored in the storage space in which the faulty memory cells are included, depending on the majority rule. In an embodiment, when m is 3, the processing circuit115may compare first to third candidate data with each other. In this case, the first and second candidate data may be identical, and the first candidate data may be different from the third candidate data. The processing circuit115may determine or select the first candidate data as the mirror data based on a result of the comparison.

In operation S540b, the memory module100may transmit data associated with a result of the voting performed in operation S530bto the host200. For example, the memory module100may store the mirror data determined in operation S530bin the buffer114. The memory module100may transmit the mirror data stored in the buffer114in response to a read request provided from the host200with regard to the storage space of the memory device in which the faulty memory cells are includes.

FIG.10is a flowchart illustrating an operating method of a memory module ofFIG.1. Referring toFIGS.1to3and10, the memory module100may further perform operation S610to operation S630. In operation S610, the memory module100may receive the mode register set command MRS including an access code ACCKEY from the host200. In an embodiment, the access code ACCKEY may be a code that is determined in advance when the host200or the memory module100is manufactured. The memory module100may store the received access code ACCKEY in the mode register113.

In operation S620, the memory module100may compare the access code ACCKEY received from the host200with an access code ACCKEY_p stored in advance in the processing buffer circuit110. For example, the processing circuit115may receive the access code ACCKEY from the router112. The processing circuit115may compare the received access code ACCKEY with the access code ACCKEY_p stored in advance. When the received access code ACCKEY is identical to the access code ACCKEY_p stored in advance, the memory module100may perform operation S631. When the received access code ACCKEY is different from the access code ACCKEY_p stored in advance, the memory module100may perform operation S632.

In operation S631, the memory module100may perform an operation on the memory devices120, based on the command signal CMD received from the host200. For example, the router112may permit the host200to access a storage space of the memory devices120or the buffer114, based on an operating mode of the router112. As such, the host200may read data stored in the memory module100or may write data in the memory module100. In step S632, the memory module100may ignore the command signal CMD received from the host200. In other words, an access request for the memory devices120received from the host200may be ignored by the memory module100. As such, the memory module100having improved security may be provided.

FIG.11illustrates a block diagram of a memory module according to an embodiment of the inventive concept. Referring toFIGS.1,2, and11, a memory module1000may include first to eighth memory chips MD1to MD8, a processing buffer chip PB, and a serial presence detect (SPD) chip. The first to eighth memory chips MD1to MD8may be DRAM chips, respectively. The first to eighth memory chips MD1to MD8may store data. The first to eighth memory chips MD1to MD8may be connected to the processing buffer chip PB. An embodiment is illustrated as the memory module1000includes eight memory chips, but the number of memory chips that the memory module1000is capable of including is not limited thereto.

The processing buffer chip PB may receive the data signal DQ, the address signal ADD, and the command signal CMD from the host200through a memory interface complying with the DDR SDRAM standard. In an embodiment, the processing buffer chip PB may include the processing buffer circuit110ofFIG.2. The processing buffer chip PB may perform an operation on the first to eighth memory chips MD1to MD8based on the data signal DQ, the address signal ADD, and the command signal CMD thus received.

For example, the processing buffer chip PB may read data stored in the first to eighth memory chips MD1to MD8or may write data received from the host200in the first to eighth memory chips MD1to MD8. The processing buffer chip PB may process a portion of data stored in the first to eighth memory chips MD1to MD8.

The SPD chip SPD may store information associated with the memory module1000. The SPD chip SPD may transmit a module information signal INFO including the information associated with the memory module1000to the host200through the memory interface complying with the DDR SDRAM standard. An operation of the SPD chip SPD will be more fully described later.

In an embodiment, the memory module1000may be implemented with a dual in-line memory module (DIMM) complying with the JEDEC standard. In this case, memory chips included in the memory module1000may be classified into a normal memory channel and/or a processing memory channel in various schemes.

For example, in the case where the memory module1000is implemented with the DIMM, memory chips disposed on one surface (e.g., a front surface) of the memory module1000may be classified as the normal memory channel, and memory chips disposed on another surface (e.g., a back surface) of the memory module1000may be classified as the processing memory channel.

For another example, in the case where the memory module1000is implemented with the DIMM, the memory chips may form ranks. Memory chips included in some ranks of a plurality of ranks included in the memory module1000may be classified as the normal memory channel, and memory chips included in the remaining ranks may be classified as the processing memory channel. For example, in the case where memory chips form first to fourth ranks, memory chips belonging to the first and second ranks may be classified as the normal memory channel, and memory chips belonging to the third and fourth ranks may be classified as the processing memory channel. However, a way to classify memory chips is not limited to the above example.

FIG.12is a flowchart illustrating an operating method of a memory system including a memory module ofFIG.11. Referring toFIGS.1,2,11, and12, the memory system10including the memory module1000ofFIG.11may perform operation S110cto operation S130c, operation S200c, operation S300c, and operation400c. In operation S110c, the memory module1000of the memory system10may transmit the module information signal INFO to the host200. In some embodiments, this module information signal INFO may include a variety of information about the memory module1000, such as information indicating that the memory module1000includes the processing buffer chip PB, a kind of an operating mode of the processing buffer chip PB, and a kind of an operation capable of being performed by the processing buffer chip PB. The SPD chip SPD may transmit the module information signal INFO to the host200through the memory interface complying with the DDR SDRAM standard.

In operation S120c, the host200of the memory system10may determine an operating mode of the processing buffer chip PB in the memory module1000. For example, the host200may check that the memory module1000is capable of receiving a command for an offload through the DDR SDRAM standard interface, based on the received module information signal INFO. The host200may determine how components included in the processing buffer chip PB of the memory module1000operate. For example, the host200may determine an operating mode of the router112or the processing circuit115of the processing buffer circuit110included in the processing buffer chip PB.

In operation S130c, the host200of the memory system10may transmit the command signal CMD to the memory module1000. For example, the host200may issue the command signal CMD comprising mode register set command MRS associated with an operation of the processing buffer chip PB, based on a result of operation S120c. The host200may transmit the command signal CMD to the memory module1000through a memory interface complying with the DDR standard.

In operation S200c, the memory module1000of the memory system10may select an operating mode of the processing buffer chip PB. For example, the memory module1000may determine an operating mode of the router112and the processing circuit115and a storage space capable of being accessed by the host200, based on the command signal CMD received in operation S130c.

In operation S300c, the host200of the memory system10may transmit the data signal DQ, the command signal CMD and the address signal ADD to the memory module1000. In operation S400c, the memory module1000of the memory system10may operate on memory devices depending on the selected operating mode of the processing buffer chip PB. For example, the processing buffer chip PB may operate based on the operating mode of the router112and the processing circuit115determined in operation S200cand the storage space capable of being accessed by the host200. The processing buffer chip PB may access at least a part of the first to eighth memory chips MD1to MD8based on the data signal DQ, the command signal CMD, and the address signal ADD.

According to an embodiment of the inventive concept, there may be provided a PIM or FIM capable of accessing data at a memory module level without additional intervention of a host or a CPU. For example, a PIM or FIM having a separate bandwidth for processing data may be provided within a memory module. As such, the performance of data processing of the memory module may be improved.

As a memory module according to an embodiment of the inventive concept is used, the performance of an application using a machine learning or deep learning algorithm may be improved. For example, in the case of processing data based on an algorithm such as a recurrent neural network (RNN), multilayer perceptron (MLP), or a CNN having a fully-connected layer structure, because the amount of data to be processed is large, a memory device may be frequently accessed. The memory module according to an embodiment of the inventive concept may provide a separate internal bandwidth for data processing, and thus, the throughput of the above applications may be improved.

According to an embodiment of the inventive concept, a deep learning accelerator based on a DDR memory channel may be provided. According to another embodiment of the inventive concept, a memory module including a pre-processor for acceleration of a CNN operation may be provided. For example, the memory module may transpose data of a matrix form received from a host, by using an internal processor. As the memory module stores the transposed data, the speed of the CNN operation may be improved.

According to another embodiment of the inventive concept, there may be provided a memory module that improves the reliability of data stored therein by mirroring data within the memory module. According to another embodiment of the inventive concept, there may be provided a memory module that is capable of providing a dual security function for data by verifying an access code received from a host by using an internal processor.

According to an embodiment of the inventive concept, data processing may be offloaded from a host to a memory module through a memory interface complying with the DDR standard. A memory module according to another embodiment of the inventive concept may include a processor capable of accessing storage spaces of different memory devices in the memory module without intervention of a host. As such, the performance of data processing and the compatibility of the memory module may be improved.