Image sensor having improved sensitivity and decreased crosstalk and method of fabricating same

An image sensor is provided. The image sensor includes a substrate; a first isolation region, a second isolation region, a plurality of photoelectric transducer devices, a read element and a floating diffusion region. The second isolation region has a depth that is less than that of the first isolation region. The plurality of photoelectric transducer devices is isolated from one another by the first isolation region. The read element and the floating diffusion region are isolated from the photoelectric transducer devices by the second isolation region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an image sensor. More particularly, the invention relates to an image sensor having improved sensitivity and decreased crosstalk, as well as a method of fabricating such an image sensor.

This application claims priority from Korean Patent Application No. 10-2006-0009372 filed on Jan. 31, 2006, the subject matter of which is hereby incorporated by reference in its entirety.

2. Description of the Related Art

An image sensor converts optical images into electrical signals. Recent evolution in various consumer products (e.g., digital cameras, camcorders, Personal Communication Systems (PCSs), game equipment, surveillance cameras and medical micro-cameras) has resulted in a sharp increase in the demand for image sensors having improved performance characteristics.

Conventionally, Metal Oxide Semiconductor (MOS) image sensors have been used within a variety of optical imaging products and scanning schemes. MOS image sensors are advantageous because their related signal processing circuits may be integrated on a signal chip so that incorporating products may be miniaturized. MOS processing technologies are also well developed and may be used at reduced cost. Power consumption is also very low, so that the MOS image sensors may be applied to power conscious and battery powered products. Given the excellent resolution and quality performance provided by MOS image sensors, numerous emerging applications are being identified.

However, as the degree of fabrication integration increases for MOS image sensors in order to satisfy demands for finer image resolution capabilities, the size of the constituent photoelectric transducer device, (e.g., a photodiode) in each unit pixel becomes smaller. Unfortunately, reduction in the physical size of the photoelectric transducer device results in a corresponding reduction in the sensitivity of the MOS image sensor.

Furthermore, as pixel density increases in various products, the corresponding inter-pixel distance decreases. This decrease in active device separation leads to crosstalk between adjacent pixels. Inter-pixel crosstalk may be classified into optical crosstalk “A” and electrical crosstalk “B” which are conceptually illustrated in Figure (FIG.)1.

In optical crosstalk, light incident through a micro-lens and/or a color filter (not shown) is not transmitted to an intended photodiode4. Instead, the incident light may be transmitted to an adjacent photodiode4. This result may occur, in part, because incident light6ais reflected from the top and/or side surfaces of metal wires M1, M2and M3. In may also occur because incident light6bis refracted as it passed from the surface of a multilayer structure through inter-layer dielectric films5a,5band5cwhich have different refractive indices. This phenomenon is particularly prevalent where the inter-layer dielectric films have non-uniform surfaces.

In electrical crosstalk, an Electron Hole Pair (EHP) formed outside the depletion region of a photoelectric transducer device2by long-wavelength incident light7is transmitted into an adjacent photodiode2through diffusion.

When crosstalk occurs, the resolution is degraded in the case of a gray image sensor to the point where the resulting image is distorted. Furthermore, in the case of a color image sensor (e.g., an image sensor incorporating a Color Filter Array (CFA) of red, green and blue), crosstalk due to red (e.g., relatively long wavelength light) incident light may occur, thereby degrading the resulting image with a tint.

As shown inFIG. 1, a Shallow Trench Isolation (STI) region3ais typically provided between adjacent photodiodes4in the conventional image sensor. STI region3amay be provided in a p-type doping region3band is designed to reduce the possibility of electrical crosstalk. The p-type doping region3bis formed using an ion implantation process. However, there is a limitation to the depth at which p-type doping regions3bmay be formed under STI region3a. Thus, it is not possible to satisfactorily provide an electrical crosstalk barrier. Furthermore, the p-type doping region3bdoes not provide an effective optical crosstalk barrier.

SUMMARY OF THE INVENTION

Accordingly, embodiments of the present invention have been made keeping in mind at least the above problems and such embodiments provide an image sensor having improved sensitivity and decreased crosstalk. Embodiments of the invention also provide a method of fabricating such an image sensor.

In one embodiment, the invention provides an image sensor comprising; a first isolation region formed in a substrate, a second isolation region formed with a depth less than a depth of the first isolation region, a plurality of photoelectric transducer devices isolated from one another by the first isolation region, and a read element and a floating diffusion region isolated from the photoelectric transducer devices by the second isolation region.

In another embodiment, the invention provides an image sensor comprising; a first conductive type impurity layer formed in a substrate and spaced apart from a surface of the substrate, a trench isolation region extending from the surface of the substrate to the first conductive type impurity layer, and a plurality of photoelectric transducer devices optically and electrically isolated from one another by the trench isolation region and the first conductive type impurity layer.

DESCRIPTION OF EMBODIMENTS

Merits and characteristics of the invention, and methods for accomplishing them will become more apparent from the following embodiments taken in conjunction with the accompanying drawings. However, the present invention is not limited to the disclosed embodiments, but may be implemented in various manners. The embodiments are provided to complete the disclosure of the present invention and to allow those having ordinary skill in the art to understand the scope of the present invention. The present invention is defined by the category of the claims. In some embodiments, well-known processes, well-known device structures and well-known technologies will not be described in detail to avoid obscuring the present invention.

The same reference numerals in different drawings denote the same or similar elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It is emphasized that the term “comprises” or “comprising” is used in this specification to specify the presence of stated features, steps or components, but does not preclude the addition of one or more further features, steps or components, or groups thereof. Furthermore, terms in the description are used not to restrict the present invention but to describe embodiments.

CMOS Image Sensors (CISs) are disclosed as examples with reference to the accompanying drawings. The disclosed exemplary CISs include isolation regions capable of reducing electrical and optical crosstalk, and improving the sensitivity of photoelectric transducer devices.

FIGS. 3 through 10Dare various views illustrating CMOS Image Sensors (CISs) according to embodiments of the present invention, in which an active pixel sensor array is constructed using a 4-shared pixel in which 4 photoelectric transducer devices share a read element, as a unit pixel. Those of ordinary skill in the art will recognize this description as merely being exemplary of many other embodiments of the invention.

The photoelectric transducer device may be a photo transistor, a photo gate, a photodiode (hereinafter referred to as a “PD”), a pinned photodiode (hereinafter referred to as a “PPD”), and/or a combination thereof. In certain embodiments of the invention, a PD or PPD is used within a CIS. In the following description, the photoelectric transducer device is referred to as a PD when it can be realized as a PD or PPD, and it is separately referred to as a PPD when only a PPD is specifically illustrated.

A unit pixel includes a floating diffusion region (hereinafter referred to as a “FD”) for reading a charge from the PD, and a plurality of read elements. A read element may include a select element, a drive element and a reset element.

Since four PDs share the select element, the drive element and the reset element, a 4-shared pixel can reduce the area of the read element and then increase the size of the PD using the reduced read element area. Accordingly, it is possible to increase light reception efficiency and improve photo sensitivity and the number of saturated signals.

FIG. 2is an equivalent circuit diagram of an APS array for a 4-shared pixel image sensor according to an embodiment of the invention.

Referring toFIG. 2, a 4-shared pixel P includes four PDs11a,11b,11cand11d. The four PDs11a,11b,11cand11dreceive incident light and accumulate charges corresponding to the intensity of light. The four PDs11a,11b,11cand11dare respectively coupled with charge transmission elements15a,15b,15cand15dthat transmit accumulated charges to an FD13. A floating diffusion region13includes a first FD13awhich is shared by two PDs11aand11b, and a second FD13bwhich is shared by other two PDs11cand11dand is electrically coupled with the first FD13a. Since the parasitic capacitance of the first FD13aand the parasitic capacitance of the second FD13bare serially connected, the total parasitic capacitance of the FD13can be minimized. Therefore the charge in FDs (13a,13b) can be used as the driving voltage of sufficient volume of drive elements17.

The 4-shared pixel P has four PDs11a,11b,11cand11dwhich share a drive element17, a reset element18and a select element19.

The drive element17illustrated as a source follower amplifier amplifies a change in the electrical potential of the FD13which has received charge accumulated in each of the PDs11a,11b,11cand11d, and outputs it to an output line Vout.

The reset element18periodically resets the FD13to a reference value. The reset element18may be comprised of a single MOS transistor driven by a bias provided by a reset line RX(i) which applies a desired bias. When the reset element18is turned on by the bias provided by the reset line RX(i), a desired electrical potential provided to the reset element18, for example, a power voltage VDD, is transmitted to the FD13.

The select element19serves to select the 4-shared pixel P to be read on a row basis. The select element19may be comprised of a MOS transistor driven by a bias which is provided by a row select line SEL(i). When the select element19is turned on by the bias provided by the row select line SEL(i), a predetermined electrical potential provided to a drain of the select element19, for example, a power voltage VDD, is transmitted to the drain region of the drive element17.

Transmission lines TX(i)a, TX(i)b, TX(i)c and TX(i)d which apply biases to charge transmission elements15a,15b,15cand15d, a reset line RX(i) which applies a bias to the reset element18, and a row select line SEL(i) which applies a bias to the select element19, can be extended and arranged substantially in the row direction and in parallel with one another.

A layout for an APS array of a 4-shared pixel CIS according to an embodiment of the invention is shown inFIG. 3.

Referring toFIG. 3, the APS array of the 4-shared pixel CIS according to an embodiment of the invention is formed in such a way that a pair of first active area A1and second active area A2is repeatedly arranged in a matrix. The first active area A1includes PD1and PD2sharing a first FD FD1. The second active area A2includes PD3and PD4sharing a second FD FD2. Each pair of first and second active areas A1and A2is associated with corresponding third and fourth active areas A3and A4—independent read element active areas. That is, the first through fourth active areas A1, A2, A3and A4constitute one unit active area of the 4-shared pixel.

The first active area A1is a one axis merged dual lobe type active area, and the second active area A2is a no axis merged dual lobe type active area.

In some additional detail, for the first active area A1, a dual lobe active area “a” is merged with an axis active area “b” through a connection active area “c”. The dual lobe active area “a” is symmetrical with respect to the axis active area “b” in the column direction. The dual lobe active area “a” is an active area including PD1and PD2, and the connection active area “c” includes first FD FD1.

For the second active area A2, each dual lobe active area “a” is merged with one through a connection active area “c” without any axis. The dual lobe active area is symmetrical in the column direction. The dual lobe active area “a” is an active area including two PDs, and the connection active area “c” includes second FD FD2.

For efficient wiring, it may be advantageous to dispose a reset gate RG in an axis active area “b” so as to form a reset element. Since the reset element serves to periodically reset the floating diffusion region FD, it may be advantageous to form the junction of the floating diffusion region FD and the reset element as one from the point of view of minimized wiring. However, the element formed in the axis active area “b” is not limited to the reset element. In order to facilitate repetition of this arrangement, a dummy gate DG having substantially the same shape as the reset gate RG may be disposed in a region adjacent to the connection portion of the second active area A2.

The third and fourth active areas A3and A4are respectively provided with read elements. In the case where the reset element is formed in the axis active area “b”, the third active area A3may be provided with a drive element, and the fourth active area A4may be provided with a select element. Accordingly, the third active area A3may be provided with the source follower gate SFG of the drive element, and the fourth active area A4may be provided with the select gates RSGs of the select element. However, depending on how the wiring is formed, the third active area A3may be provided with the select element and the fourth active area A4may be provided with the drive element.

FIG. 4is a sectional view further illustrating an embodiment of a 4-shared pixel CIS formed according to the circuit diagram and the layout respectively shown inFIGS. 2 and 3.

Referring toFIG. 4, the CIS includes two different isolation regions121and123in an APS array.

A first isolation region121is an element isolation region which isolates PDs from each other. The first isolation region121is an electrical and optical crosstalk barrier as well as an element isolation region. The second isolation region123is an element isolation region which isolates the PD and the read element from each other.

In the case of using the layout ofFIG. 3, the first isolation region121may be formed between the row and column parallel lines of adjacent PD active areas “a”. The PD or PPD comprised an n-type doping region may be formed in the PD active area.

FIG. 4illustrates a PPD comprising a first conductive type doping region, for example, a p-type doping region143, and a second conductive type doping region, for example, an n-type doping region141, under the first conductive type doping region and a p-type epitaxial layer101b. The PPD is generally realized in an APS array design due to performance advantages related to reduction of dark current noise.

Since the absorption wavelengths corresponding to blue, green and red light in substrate100are 0-0.4 μm, 0.15-1.5 μm, and 0.4-5 μm, respectively, the PPD should be more than 2 μn in depth. Furthermore, in order to improve sensitivity by capturing most of the absorbed red light, it is preferable in certain embodiments of the invention that the PPD have a depth up to 5 μm, if possible.

Generally, when the n-type doping region141is formed by ion-implantation of n-type impurities into the p-type epitaxial layer101bthe ion concentration of which may range from 1013to 1017/cm3, in a dose of 1011to 1012ions/cm2and in an Rp (Projection Range) of about 2000 Å, a depletion layer144is formed in the substrate at a depth more than about 2 μm from the surface of the substrate.

The first isolation region121may sufficiently serve as an electrical crosstalk barrier only when the first isolation region121is formed deeper than the depletion layer144formed by the n-type doping region141. In other words, when the first isolation region121, which is an electrically insulating material, encloses the depletion region144of the PPD and the P-type epitaxial layer101b, an EHP generated under the depletion region144of the PPD thermally diffuses and prevents electrical crosstalk which can affect an adjacent PPD. Furthermore, as the first isolation region121becomes deeper than the PPD, its function as an electrical crosstalk barrier may be more readily achieved. Accordingly, it is preferable in certain embodiments of the invention that the first isolation region121be formed deeper than the n-type doping region141by, for example, 2 μm or more. In the case where the PPD is formed up to 5 μm in depth by controlling the formation dose and Rp of n-type doping region141in order to improve the sensitivity of the PPD, it is apparent that the first isolation region121also should be formed deeper than 5 μm. Such a depth relationship can be applied to the PD which is comprised only an n-type doping region141, as well as the PPD, in the same manner.

Further, in the case where the first isolation region121comes into contact with a p-type deep well103, an electrical crosstalk barrier may be effectively implemented. The p-type deep well103is a first conductive type (p-type) impurity layer spaced apart from the surface of the substrate100and formed inside the substrate100, in more detail (e.g.,), in the p-type epitaxial layer101b. The p-type deep well103is an electrical crosstalk barrier which forms a potential barrier to prevent the EHP generated in the substrate101aor the p-type epitaxial layer101bfrom thermally diffusing into the PPD, and decreases electrical crosstalk occurring due to random drift of electrons by increasing the recombination of electrons and holes. Accordingly, when the bottom of the first isolation region121is in contact with the p-type deep well103, it is possible to form a minimum closed electrical crosstalk barrier. When the bottom of the first isolation region121is formed deeper than that of the p-type deep well103, that is, the sidewalls of the first isolation region121are in contact with the p-type deep well103, a more reliable electrical crosstalk barrier can be formed.

As described above, according to embodiments of the present invention, since the position at which the p-type deep well103is formed can be controlled depending on the depth of the first isolation region121, it is possible to sufficiently increase the sensitivity of the PPD by maximizing the size (e.g.,) volume of the PPD. When it is desired to increase the sensitivity of the PPD, the depth of the first isolation region121may be more than 2 μm, and approximately 5 μm. If this process approach is implemented, the size of the PPD may be maximized by increasing the depth of the first isolation region121to greater than 5 μm and forming the p-type deep well103contacting the first isolation region121, so that the sensitivity of the PPD may be maximized.

Meanwhile, in the case where the trench109is filled with a material having a refractive index which is lower than that of the substrate101, (e.g., a silicon oxide film, a silicon nitride film, or air), the first isolation region121may also function as an optical crosstalk barrier.

With reference toFIG. 4, most of the refracted light155is formed when incident light is refracted by the (potentially non-uniform) surface(s) found in the multilayer structure formed by dielectric films150a,150b,150cand150d, each potentially having a different refractive index. The reflected light156is formed when incident light is reflected from the upper and/or side surfaces of the metal wiring M1, M2and M3, as well as the light reflected by the interface between the substrate100and the first isolation region121. These two components, refracted light155and/or reflected light156, account for most of the optical crosstalk potentially interfering with operation of an adjacent PPD.

FIG. 4illustrates an embodiment where the substrate100is formed from a p-type bulk substrate101aand a p-type epitaxial layer101bhaving a thickness ranging from about from 2 to 10 μm. Each of these materials responds similarly to optical wavelengths in the infrared or near infrared bands. In one more specific embodiment, the p-type epitaxial layer101bis formed to a thickness ranging from about 3 to 5 μm. Where a p-type epitaxial layer101bis used, an effective potential barrier may be formed by controlling its doping concentration in relation to the p-type deep well103, thereby improving overall electron accumulation capabilities. Accordingly, where the p-type epitaxial layer101bis used, an n-type bulk substrate may alternately be used as the bulk substrate101a.

Indeed, the substrate100may be variously formed from a variety of combinations, such as those listed below in Table 1.

The particular case ** indicated above, instead of an epitaxial layer, a p-type well may be formed in an n-type bulk substrate. Further, a substrate formed from an organic plastic substrate may be used instead of the semiconductor substrate variations illustrated in Table 1.

FIGS. 5A to 5Dare sectional views illustrating the various exemplary embodiments of the first isolation region121(deep trench isolation region) shown inFIG. 4.

FIG. 5Aillustrates an embodiment where the first isolation region121comprises a trench isolation region formed by the sequentially deposition of a thermal oxide film111and a silicon nitride film liner112on the bottom and sidewall surfaces of a trench109. The trench109is then filled with a filler material113, such as an oxide film.

FIG. 5Billustrates an embodiment where the first isolation region121comprises a trench isolation region formed by forming thermal oxide layer111on the bottom and sidewalls of trench109, forming silicon nitride liner112on thermal oxide film111, partially filling the trench109with silicon oxide film113, and then filling the remaining portion of the trench109with an un-doped poly-silicon114having good gap-filling properties.

FIG. 5Cillustrates an embodiment where the first isolation region121comprises a trench isolation region formed by filling a lower portion of the trench109with un-doped poly silicon114having a good gap-filling property, and then filling an upper portion of the trench109with oxide film113or the like.

FIG. 5Dillustrates an embodiment where the first isolation region121comprises a trench isolation region having an interior portion partially filled with air115.

Furthermore, as illustrated inFIGS. 5A and 5B, a p-type shallow doping region117may be formed around the first isolation region121to inhibit dark current from flowing to the surface portions of the trench109where dangling bonds or similar atomic discontinuities may be exposed during the etching process used to form the trench109.

Referring again toFIG. 4, the APS array9of the CIS according to embodiments of the invention may further comprise a second isolation region123formed more shallowly than the first isolation region121. The second isolation region123may be a STI region isolating the PD from the read element. Accordingly, the second isolation region123may be formed in the active area “a”, the read element active areas “b”, A3and A4, and/or the floating diffusion region active area “c”. As illustrated in the layout diagram ofFIG. 3, the gap between the PD active area “a” and the read element active areas (“b”, “c”, A3and A4) is smaller than that between the PD active area “a” and the PD active area “a”. Accordingly, it may be difficult to form an isolation region in the form of a deep trench between these structures similar to the first isolation region121. The read element active areas “b”, A3and A4and the floating diffusion region active area “c” may fall, and the spacing distance D1between the PD active area “a” and the PD active area “a” facing each other with respect to the read element active areas “b”, A3and A4and the floating diffusion region active area “c” is larger than the spacing distance D2between the PD active area “a” and the PD active area “a”, facing each other directly, therefore the crosstalk path “C” through this portion may be negligible.

Accordingly, the PD active area “a”, the read element active areas “b”, A3and A4and the floating diffusion region active area “c” may be isolated by the second isolation region123which is shallower than the first isolation region121. Further, as illustrated in the layout diagram ofFIG. 3, a portion of the second isolation region123isolates the read element active areas A3and A4in a first pixel from the PD active area “a” in the first pixel, and the remaining portion of the second isolation region123isolates the read element active area “b” and the floating diffusion region active area “c” in the first pixel from the PD active area “a” in the second pixel subsequent to the first pixel.

The second isolation region123may be formed by filling the inside of the trench110with a material having a refractive index lower than that of the substrate101, (e.g., a silicon oxide film, a silicon nitride film, a poly-silicon, or air), as in the first isolation region121illustrated inFIGS. 5A through 5D.

Further, the second isolation region123may be implemented as a STI region similar to that of the third isolation region125defining the active area on which the circuit elements of a peripheral circuit are formed. In certain embodiments, the second and third isolation regions123and125may be formed to a depth ranging from between about 2000 to 4000 Å.

InFIG. 4, reference numeral160denotes a silicon oxide film and/or transparent resin used to fill various light transmission portions of the structure. References numerals170,180and190respectively denote a flattening layer, a color filter, and a micro-lens. In the drawing, although wiring layers M1, M2and M3are shown as three layers, they may be comprised two layers depending on the actual design of the CIS.

Given that a read element may be formed integral to the APS array, corresponding CMOS elements (e.g., resistors and capacitors) may be simultaneously formed in the peripheral circuit portion of the device. Since these elements can be embodied in a variety of forms well known to those skilled in the art, these elements will not be individually described.

FIGS. 6A and 6Bare sectional views illustrating additional embodiments of the second isolation region123shown inFIG. 4. The upper structure of the substrate100is omitted inFIGS. 6A and 6Bfor simplicity of illustration.

FIG. 6Aillustrates an embodiment where the second isolation region is formed from a p-type doping region123′.FIG. 6Billustrates an embodiment where the second isolation region is formed from a Field Oxide (FOX) structure123″ using a LOCOS method. In these embodiments, various isolation region(s) in the peripheral circuit region may also be formed from the p-type doping region125′, or FOX structure123″ together with the second isolation region.

FIG. 7is a sectional view of a 4-shared pixel image sensor according to another embodiment of the present invention.FIG. 8is an enlarged sectional view of the first isolation region221shown inFIG. 7.

Referring toFIGS. 7 and 8, a first isolation region221is different from the first isolation region121shown inFIG. 4in that the former is formed of a lower trench isolation region222and an upper wide isolation region223. The upper wide isolation region223can be embodied as a shallow trench isolation region. The upper wide isolation region223is connected to the top of the lower trench isolation region222and widens outside the sidewall of the lower trench isolation region222. With the upper wide isolation region223is placed on the lower trench isolation region222, a buffer region224is formed under an eave portion (i.e., the outwardly extending portion of upper wide isolation region223) of the upper wide isolation region223.

Referring toFIG. 8, the buffer region224is formed to effectively prevent the p-type shallow doping region217, which was formed to inhibit dark current flowing to the surface of the trench209, from reducing the effective area of the n-type doping region141of a PPD and thus the sensitivity of the PPD. As illustrated inFIG. 8, when the width of the upper wide isolation region223is formed substantially the same as that of the first isolation region121illustrated inFIG. 4, the width of the lower isolation region222is formed smaller than the first isolation region121illustrated inFIG. 4, and a p-type shallow doping region217having the same width as that ofFIG. 4is formed, it is possible to increase the size of the n-type doping region141by the size of the buffer region224, compared to the CIS using the first isolation region121.

A description of remaining elements will be omitted since they are substantially the same elements as those described in the embodiment ofFIG. 4.

FIGS. 9A to 9Care sectional views illustrating additional embodiments of the first isolation region221of the 4-shared pixel image sensor illustrated inFIG. 7.

FIG. 9Aillustrates an embodiment where a LOCOS region233instead of an upper trench isolation region is formed on a lower trench isolation region222so as to provide a buffer region224.FIG. 9Billustrates an embodiment where an expansion portion234, which is the lower trench isolation region222having an expanded opening formed through a wet etching or cleaning process, provides a buffer region224, andFIG. 9Cillustrates the case where a p-type junction235is formed on the upper portion of a sidewall of the lower trench isolation region222so as to provide the buffer region224. Also in the embodiments illustrated inFIGS. 7 through 9C, it is possible to replace the second isolation region123with the p-type doping region or the FOX based on the LOCOS method, as shown inFIGS. 6A and 6B.

FIGS. 10A to 10Care alternate layout diagrams to that ofFIG. 4.

In the layout illustrated inFIG. 10A, both of a first active area A1having two PDs PD1and PD2which share a first FD FD1and a second active area A2having two PDs PD3and PD4which share a second FD FD2, are one axis merged dual lobe type active areas, unlike the layout illustrated inFIG. 3.

In an embodiment where the second active area A2is formed of a one axis merged dual lobe type active area, it is possible to embody an MOS capacitor using a dummy gate DG on an axis active area b extended from a connection active area “c” in which the second FD(FD2) is formed.

A more detailed description of this alternative may be found, for example, in commonly assigned Korean Patent Application No. 10-2006-0004116, the subject matter of which is hereby incorporated by reference.

In the layout illustrated inFIG. 10B, four PDs PD1, PD2, PD3and PD4are formed on a pair of two axis merged dual lobe type active areas A2, unlike the layout illustrated inFIG. 3. Accordingly, since three read elements may be separately formed on two independent read element active areas A5and A6, there is a difference in that two read elements must be formed on either one of the two independent read element active areas A5and A6, for example, A6.

A reset element may be formed in the first independent read element active area A5, and a select element and a drive element formed therein may be formed in a second independent read element active area A6. Accordingly, a reset element gate RG may be placed in the first independent read element active area A5, and a select element gate RSG and a drive element gate SFG may be placed in the second independent read element active area A6.

Those of ordinary skill in the art will recognize that the type of element formed in each of the first and second independent read element active areas A5and A6may be varied by changing the type of wiring communicating electrical signals to the element formed in each of the active areas A5and A6.

In the layout illustrated inFIG. 10C, all of the reset element, the drive element and the select element are formed on the axis active area “b” of the first active area A1, that is, a one axis merged dual lobe type active area, without independent read element active areas A3and A4, unlike the layout illustrated inFIG. 4.

Also in the embodiments of a CIS using the 4-shared pixel layout illustrated inFIGS. 10A to 10C, respective active areas are defined by the first and second isolation regions having various shapes illustrated inFIGS. 4 through 9C. In detail, a first isolation region is formed between the PD active area “a” and the PD active area, facing each other without any read element active area therebetween, and a second isolation region is formed among the PD active area “a”, the read element active areas “b”, A3, A4, A5, A6, A7, A8and A9and the floating diffusion region active area “c”. Further, part of the second isolation region isolates the read element active area “b” and the floating diffusion region active area “c” in the first pixel from a PD active area “a” in a second pixel subsequent to the first pixel.

FIG. 11is an equivalent circuit of the APS array of a 2-shared pixel image sensor according to embodiments of the present invention.

Referring toFIG. 11, 2-shared pixels P are arranged in a matrix, thus forming the APS array. In each of the 2-shared pixels P, two PDs adjacent to each other in the column direction share the same read element.

In some additional detail, each of the 2-shared pixels P includes two PDs11aand11badjacent to each other in the column direction and the two PDs11aand11bshare a drive element17, a reset element18, and a select element19. A charge accumulated in each of PDs11aand11bis transmitted to a common FD13by each of the charge transmission elements15aand15b.

FIGS. 12A and 12Bare layout diagrams for a 2-shared pixel image sensor according to embodiments of the present invention.

Referring toFIG. 12A, first active areas A1each formed of two PDs PD1and PD2which share the floating diffusion region FD are arranged in a matrix, and an APS array9is configured in such a way that each first active area A1is assigned with an independent read element active area A2. That is, the first and second active areas A1and A2constitute a unit active area of the 2-shared pixel.

The first active area A1is a one axis merged dual lobe type active area. In detail, for the first active area A1, a dual lobe active area “a” is merged with an axis active area “b” through a connection active area “c”. Each dual lobe active area is symmetrical with respect to the axis active area “b” in the column direction.

Two PDs PD1and PD2are formed in the dual lobe active area “a”, and an FD and a reset element are formed in the connection active area “c” and the axis active area “b”, respectively. A drive element and a select element are formed in the independent read element active area A2.

The layout illustrated inFIG. 12Bis formed only of first active areas A1, that is, one axis merged dual lobe type active areas, without independent read element active areas, unlike the layout illustrated inFIG. 12A. A reset element, a drive element and a select element are formed in the axis active area “b” of the first active area A1.

FIGS. 13A through 13Eare sectional views illustrating additional embodiments of the first isolation region constituting a 2-shared pixel image sensor according to embodiments of the present invention.FIGS. 14A through 14Care sectional views illustrating additional embodiment of the second isolation region constituting a 2-shared pixel image sensor according to embodiments of the present invention.

Like the sectional view of the 4-shared pixel image sensor, respective active areas are defined by various combinations of the first and second isolation regions having various shapes illustrated inFIGS. 4 through 9C. In detail, each of first isolation regions121,221,221′,221″ and221′″ may be formed between the PD active area “a” and the PD active area “a” facing each other without the read element active area therebetween, as illustrated inFIGS. 13A through 13E, and each of second isolation regions123,123′ and123″ may be formed among the PD active area “a”, the read element active areas “b” and A2and the floating diffusion region active area “c”, as illustrated inFIGS. 14A through 14C.

FIG. 15is an equivalent circuit diagram of the active pixel sensor array of a non-shared pixel image sensor according to embodiments of the present invention.

Referring toFIG. 15, non-shared pixels P are arranged in the matrix, thus constituting an APS array9. Each of the non-shared pixels P is provided with a drive element17, a reset element18and a select element19for each PD11, and a charge accumulated in each PD11is transmitted to an FD13by each charge transmission element15.

FIG. 16is a layout diagram of a non-shared pixel image sensor according to embodiments of the present invention. Referring toFIG. 16, an active area A11constitutes a unit active area of the non-shared pixel. The active area A11includes a PD active area “a” in which each PD is formed, and a read element active area “d” which extends from the PD active area “a” and in which an FD, a reset element, a drive element and a select element are formed.

Although not shown in the drawing, respective active areas may be defined by the first and second isolation regions having various shapes illustrated inFIGS. 5A through 10C, like the sectional views of the 4-shared pixel image sensor. That is, a first isolation region may be formed between the PD active area “a” and the PD active area directly facing each other, and a second isolation region may be formed between the PD active area “a” and the floating diffusion region and read element active area “d”.

FIG. 17is a partial perspective view of an image sensor according to embodiments of the present invention.FIG. 17illustrates am embodiment where all isolation regions are formed only of first isolation regions121illustrated inFIGS. 4 through 5D.

In the case where the gap between a PD active area and a read active area is sufficient or a processing margin for deep trench isolation region formation is sufficiently large, a PPD is completely enclosed by the first isolation region121and the p-type deep well103when all active areas are defined only by the first isolation region. Accordingly, it is possible to completely inhibit electrical and optical crosstalk. That is, adjacent PPDs are isolated from each other by the first isolation region121and the p-type deep well103. The electrical and optical crosstalk is decreased and optical sensitivity is increased by combining a potential barrier comprised a first conductive type, for example, a p-type deep well103with first isolation regions121and221which are in contact with the potential barrier and function as electrical and optical crosstalk barriers.

Although not shown in the drawings, the first isolation regions221,221′,221″ and221′″ illustrated inFIGS. 7 and 9Athrough9C can be employed in the same manner as shown inFIG. 18.

FIG. 18is a schematic view showing a processor based system including a CIS according to embodiments of the present invention.

Referring toFIG. 18, the processor based system301is a system which processes an output image of the CIS310. Although the system301may be exemplified as a computer system, a camera system, a scanner, a mechanical clock system, a navigation system, a video phone system, a monitoring system, an automatic focus system, a tracking system, an operation monitoring system, an image stabilization system, and the like, it is not limited to them.

The processor based system301, such as a computer system, includes a central processing unit CPU320such as a microprocessor, which can communicate with an input/output device330through a bus305. The CIS310can communicate with the system through the bus305or other communication links. Further, the processor based system301can further include RAM340, a floppy disk drive350and/or a CD ROM drive355, and a port360which can communicate with the CPU320through the bus305. The port360may be a port which can couple a video card, a sound card, a memory card, and a USB device, or exchange data with another system. The CIS310can be integrated with a CPU, a Digital Signal Processor (DSP), or a microprocessor. Further, the CIS310can be integrated with memory. Of course, the CIS310may be provided on a separate chip different from the processor depending on the circumstances.

According to the CIS as described above, there are one or more of the following effects.

First, the sensitivity of the PD can be effectively increased by increasing the depth of the first isolation region because the depth of the first isolation region is the only parameter controlling the sensitivity.

Second, the crosstalk can be effectively reduced because the first isolation region can function as an electrical and optical crosstalk barrier.