Voltage stress testing of core blocks and regulator transistors

An apparatus and method for disabling an internal voltage regulator of a circuit to voltage stress test the circuit. The apparatus may include a circuit having an internal voltage regulator and a design-for-test circuit coupled to the circuit to disable the internal voltage regulator to voltage stress test the circuit in a test mode.

TECHNICAL FIELD

This invention relates generally to a switch and, more particularly, to controlling a high-voltage switch.

BACKGROUND

When devices, such as packaged integrated circuits (or “chips”) are built, it is conventional to stress test either each device or a sample of the devices that are built before shipping the devices to the customer.

One type of device is a programmable system on a chip device, for example, a PSoC® device manufactured by Cypress Semiconductor Corporation. A majority of internal logic components of a programmable system on a chip device are protected from a high-voltage supply by internal voltage regulators. The internal voltage regulators allow circuit designers to build the logic circuits with low-voltage transistors, as opposed to costly high-voltage transistors (also referred to as high-voltage switches). However, currently there are no external mechanisms to stress test these internal voltage regulated areas of the chip. Circuits that do not have internal voltage regulators can be run at higher voltages to determine problems with the circuit. However, areas of a chip that are regulated by an internal voltage regulator can not be run at higher voltages because the internal voltage regulator is designed to protect the circuitry from higher voltages.

Design for testing (DFT) is one means for chip manufacturers to supplement or supplant traditional functional testing role in which chips are tested at their input/outputs (I/O) for functional performance. The tests generally are driven by test programs that execute in automatic test equipment or inside the assembled chip itself. Conventional DFT methodologies include on-chip testing of device sub-blocks to indicate the presence of defects (i.e., the test fails) of circuitry within a chip. However, currently there are no DFT circuits to stress test areas of the chip (e.g., internal logic components) that are protected from the high-voltage supply by internal voltage regulators.

Conventional internal voltage regulators can include a high-voltage transistor, such as a regulator FET. High voltages are usually measured by dividing the high voltage down for comparison with lower voltage references. Resistive or capacitive dividers are commonly used. If the high voltage to be measured is also high impedance, then resistive dividers must use large valued resistors which are expensive in terms of die area. Capacitive dividers can perform the same function in less die area, but require high-voltage switches. High-voltage switches commonly require high-voltage control signals. The generation of these high-voltage control signals usually involves creating a high-voltage power supply with a charge pump and using level shifters to shift logic level control signals up to high voltages.

DETAILED DESCRIPTION

Described herein is an apparatus and method for disabling an internal voltage regulator of a circuit to voltage stress test the circuit. Also, described herein is an apparatus and method for controlling a high-voltage switch with low-voltage control signals. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques are not shown in detail or are shown in block diagram form in order to avoid unnecessarily obscuring an understanding of this description.

Reference in the description to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment. The term “coupled” as used herein may include both directly coupled and indirectly coupled through one or more intervening components. It should be noted that although the apparatus and methods may be described herein in relation to a programmable system on a chip device for ease of explanation, the apparatus and methods described herein may be applied to the development of other devices (e.g., controllers). As used herein, “high voltage” may be approximately in a range of 5 to 36V and “low voltage” may be approximately in a range of 0 to 5V.

The embodiments described below may be configured to voltage stress test internally regulated core circuitry and the gate oxide of the internal regulator FET itself. Testing can be performed quickly and inexpensively. The testing may be implemented using a selectable divider circuit, which manipulates a regulator gate control feedback loop to disable the regulator FET from protecting the internally regulated circuitry. Also, as described above, the normal mode or the test mode may be selectable via a microprocessor's or microcontroller's programmable register.

Also described below are embodiments for controlling a high-voltage switch with low-voltage control signals. While it may be readily apparent to turn a high-voltage PFET “on” by driving its gate to ground, turning a high-voltage PFET “off” with low-voltage control signals is not so apparent. It should be noted that the high-voltage transistors (also known as high-voltage switches) as described herein may have the same threshold voltage (e.g., gate-to-source voltage required to turn the transistor on) as low-voltage transistors. However, the high-voltage transistors are configured to tolerate a much higher maximum allowable drain-to-source voltage than low-voltage transistors. In addition, the high-voltage transistors, such as the PMOS transistor often have their source connected to high voltages so the gate voltage (Vg) to control these high-voltage transistors must also be a high voltage. For example, a “turned on” high-voltage PMOS transistor might have a voltage at the source of approximately 35V, a voltage on the drain of approximately 30V, a voltage at the gate of approximately 30V, and the gate-to-source voltage Vgs is approximately −5V; and a “turned off” high-voltage PMOS transistor might have a voltage at the source of approximately 35V, a voltage at the drain of approximately 0V, a voltage at the gate of approximately 35V, and the gate-to-source voltage Vgs is approximately 0V.

An apparatus and a method of voltage stress testing internal circuitry, such as core blocks, that are internally voltage regulated and a regulator field-effect-transistor (FETs) of the internal voltage regulator are described. The embodiments described herein are configured to disable the internal voltage regulator in order to stress tests circuits that are otherwise protected by the internal voltage regulator. Once the internal voltage regulator has been disabled, a voltage can be applied to the core block that is higher than a maximum voltage allowed by the internal voltage regulator. The embodiments described herein are also configured to stress test the circuitry that is protected by the internal voltage regulator (e.g., core block), as well as the internal voltage regulator itself (e.g., applying a higher gate-to-source voltage on a regulator FET of the internal voltage regulator). The circuits that are protected by an internal voltage regulator may be a processing device, such as the PSoC® device manufactured by Cypress Semiconductor Corporation of San Jose, Calif., an analog-to-digital converter, a digital-to-analog converter, a random access memory (RAM) cell, or other circuits that use an internal voltage regulator.

The apparatus may be implemented as a DFT circuit. In one embodiment, the DFT circuit enables voltage stress testing of core blocks that are internally voltage regulated. The DFT circuit provides a test mode that enables insertion of higher voltages into the core block than internal regulators allow during normal operation. The DFT circuit provides external control (e.g., external mechanism, such as knobs/handles) for voltage stress testing internal circuitry that otherwise would not be accessible for such testing. The DFT circuit also may be configured to voltage stress tests the internal voltage regulator FET itself.

The embodiments described herein may provide an economical method of controlling high-voltages switches with low-voltage control signals.

FIG. 1illustrates one embodiment of a DFT circuit for voltage stress testing a core block110within a device using a linear regulator. DFT circuit100includes an operational amplifier (opamp)101that is configured to receive two inputs at the non-inverting input terminal (indicated by a ‘+’ sign) and inverting input terminals (indicated by a ‘−’ sign) for each mode, test mode130, and normal mode140. At both the inverting and non-inverting input terminals of the opamp101, the DFT circuit100includes two switches that are configured to switch between input voltages for the test mode130and normal mode140. During test mode130, the non-inverting input terminal of the opamp101is coupled to the source of the regulator FET120, and the inverting input terminal of the opamp101is coupled to the gate of the regulator FET120(by way of the resistive divider). During normal mode140, the non-inverting input terminal of the opamp101is coupled to a reference voltage107, and the inverting input terminal of the opamp101is coupled to the source of the regulator FET120(by way of the resistive divider). The opamp101is supplied a rail voltage of an output voltage (Vpump)102of a charge pump (not illustrated) with respect to a ground potential103. The output of the opamp101is coupled to a gate of a regulator FET120(labeled REG inFIG. 1). The drain of the regulator FET120is coupled to a high-voltage power source105(HVPWR). The source of the regulator FET120is coupled to the input of the core block110and provides an output voltage Vdd106to the core block110. The voltage at the source of the regulator FET120is the regulated, output voltage106(Vdd) during normal mode140, and the unregulated, output voltage106(Vdd) during test mode130. In one embodiment, the regulated, output voltage106(Vdd) is approximately 5.0V during normal mode140, and the unregulated, output voltage106can be greater than 5.0V during test mode130. In one embodiment, the unregulated, output voltage106can be in an approximate range of 5.0V to 40.0V. Alternatively, the unregulated, output voltage106may be other values based on the HWPWR105.

The output voltage Vdd106is coupled to non-inverting input terminal of the opamp101when in test mode130; when in normal mode, the non-inverting input terminal of the opamp101is coupled to a reference voltage107(e.g., 1.3V). The inverting input terminal of the opamp101, which also depends on in which mode the DFT circuit100is operating, receives a fraction of either the output voltage Vg108of the opamp101or the output voltage Vdd106at the source of the regulator FET120. In one embodiment, the non-inverting input terminal of the opamp101receives half of the output voltage Vg108of the opamp101(e.g., Vg/2) while in test mode130, or a voltage that is approximately Vdd/3.8V (i.e., Vdd106divided by 3.8V). In one embodiment, these fractions are generated using voltage dividers, such as illustrated inFIG. 1. In this embodiment, two resistors are disposed between the output voltage Vdd106and the ground potential103, and the first resistor112is approximately 2.8 larger than the second resistor113. When in normal mode140, the switch connects a line between the inverting input terminal of the opamp101and a node109between these two resistors112and113, resulting in a voltage equal to approximately Vdd/3.8V at the inverting input terminal of the opamp101. Two additional resistors are disposed between the output voltage Vg108and the ground potential, and the third resistor114is approximately equal in value to the fourth resistor115. In this embodiment, the value of the second, third, and fourth resistors113,114, and115are approximately equal (e.g., R), while the first resistor112is approximately 2.8 R. However, when in test mode130, the switch connects a line between the inverting input terminal of the opamp101and a node111between the third and fourth resistors114and115, resulting in a voltage equal to approximately Vg/2V at the inverting input terminal of the opamp101.

In normal mode140, the opamp101forces the output voltage Vg108such that Vdd/3.8V (e.g., the voltage that is feedback to the input of the opamp101during normal mode140) is approximately equal to 1.3V. It should be noted that the opamp101is designed to operate at high voltages and the charge pump must be sized to provide large currents. The supply current of the opamp101is the sum of the current provided to the resistive divider, for example, 5 to 50 micro Amps (IA), and the bias current of the opamp101, for example, 5 to 50 μA. Accordingly, the total current the charge pump needs to provide is in the approximate range of 10 to 100 μA. However, in test mode130, the opamp101forces the output voltage Vg108such that Vg/2 (e.g., the voltage that is feedback to the input of the opamp101during test mode130) is approximately equal to Vdd, which is the output voltage106at the source of the regulator FET120. Because Vg is approximately equal to 2 times Vdd, the gate-to-source voltage106(Vgs) is approximately equal to Vdd, the output voltage108(e.g., Vgs=Vg−Vdd=2*Vdd−Vdd=Vdd).

In test mode130, the Vgs106is approximately equal to Vdd108, causing the gate-to-source of the regulator FET120to be stress tested at approximately HVPWR105. Similarly, a core block (e.g., circuit that is voltage regulated by the regulator FET120during normal mode140) that is coupled to the output voltage Vdd108is voltage stress tested at approximately HVPWR105, while in test mode130. Accordingly, the regulator FET120can be stress tested itself, and the voltage regulator can be disabled to tests circuits that are otherwise protected by the voltage regulator.

The embodiments described above are described with respect to a linear voltage regulator having a test mode and a normal mode of operation. The linear voltage regulator, however, has the following disadvantages: First, the output of the opamp101needs to be capable of outputting high voltages; and second, the opamp101requires high current from the high voltage supply (charge pump), as described above.

The embodiments described herein of voltage stress testing a core block that is internally voltage regulated may also be implemented without the use of an operational amplifier, as described below with respect toFIG. 2.

FIG. 2illustrate a block diagram of one embodiment of a DFT circuit200for voltage stress testing of a core block210within a device. The device includes DFT circuit200and the core block210(labeled CORE inFIG. 2). In this embodiment, the device is a programmable system on a chip device, for example, the PSoC® device, manufactured by Cypress Semiconductor Corporation of San Jose, Calif. Alternatively, the core blocks may reside within other types of devices, such as an analog-to-digital converter, a digital-to-analog converter, a random access memory (RAM) cell, or other circuits that use an internal voltage regulator to protect circuitry against high voltages.

In this embodiment, the core block210of the device is internally regulated by a regulator FET220(labeled REG inFIG. 2). In one embodiment, the regulator FET220is a high-voltage voltage NMOS FET with a threshold voltage of around 1V. The regulator FET220can tolerate up to approximately 40V drain-to-source voltage, but only up to approximately 5.5V gate-to-source voltage. Alternatively, PMOS FETs may be used, and the regulator FET220may have other values for the threshold voltage and drain-to-source and gate-to-source voltage tolerances (e.g., maximum allowable drain-to-source and gate-to-source voltages). The drain of the regulator FET220is coupled to a high-voltage power source205(HVPWR). In one embodiment, the HVPWR205is approximately in a range of 2.5V and 36V. Alternatively, other values may be used for HVPWR205. The source of the regulator FET220is coupled to the input of the core block210and provides an output voltage Vdd206to the core block210. The voltage at the source of the regulator FET220is the regulated, output voltage206(Vdd) during normal mode260, and the unregulated, output voltage206(Vdd) during test mode250. In one embodiment, the regulated, output voltage206(Vdd) is approximately 5.0V during normal mode260, and the unregulated, output voltage106can be greater than 5.0V during test mode250. In one embodiment, the unregulated, output voltage206can be in an approximate range of 5.0V to 40.0V. Alternatively, the unregulated, output voltage206may be other values based on the HWPWR205.

As described below, the DFT circuit200enables voltage stress testing of the core block210that is otherwise internally regulated, and further enables voltage stress testing of the gate oxide of the regulator FET220itself.

In this embodiment, during normal operation260, the upper divider circuit230is set to divide the gate-to-source voltage by a first fraction (e.g., approximately 3.2), while the lower divider circuit240divides by a second fraction (e.g., approximately 3.8). The divider circuits230and240are each configured to provide an output voltage that is the input voltage (e.g., differential voltage Vgs216or Vdd206) divided by the given fraction (e.g., approximately 3.2 or 3.8), for example, an input voltage of 4V gives an output voltage of 1.25V for the fraction of approximately 3.2. The comparator circuits, comparators250and260, are each set to compare outputs of the divider circuit against a reference voltage (e.g., 1.3V). The comparators250and260provide feedback to the charge pump280for regulating the voltage applied to the gate of the regulator FET220. The normal mode divisor ratio results in the regulator FET220shielding the core block210from the high-voltage power (HVPWR)205and sets a normal operating value for the output voltage206Vdd applied to the core block210. The comparators230and240are configured to provide feedback to the charge pump380to regulate the gate voltage Vg208of the regulator FET220, which is configured to prevent the voltage Vdd206applied to the internal core block210to not be higher than a maximum voltage allowed by the internal voltage regulator in the normal mode260of operation, and to allow the voltage Vdd206applied to the internal core block210to be higher than the maximum voltage allowed by the internal voltage regulator in the test mode250of operation.

During test operation250, the upper divider circuit230is set to divide a third fraction (e.g., approximately 3.8) that is the same as the second fraction of the lower divider circuit240. The upper comparator circuit250is switched to compare the outputs of the two divider circuits230and240, instead of the outputs of the divider circuits and the reference voltage207as done in normal mode260. The test mode configuration sets the regulator's gate-to-source voltage208Vgs to be approximately equal to the output voltage206Vdd that is applied to the core block210. Since the gate-to-source voltage208Vgs is approximately equal to the output voltage206Vdd (i.e., Vgs=Vdd), the regulator FET220is essentially turned on, resulting in the high-voltage power205(HVPWR) being applied to the core block210(i.e., Vgs=Vdd=HVPWR). With the higher voltage HVPWR205applied, the core block210can then be voltage stress tested to see if failure occurs. The stress test voltages can be varied simply by varying the value of HVPWR.

In one embodiment, the outputs of the comparators250and260are coupled to logic270to determine whether to enable the charge pump280. In one embodiment, logic270includes an inverter271, a gate272(e.g., NOR gate), and a gate273(e.g., NOR gate). The output of comparator260is coupled to the inverter271. The output of the inverter is coupled to an input of the gate272. The other input of gate272is coupled to a control signal that indicates whether the device is in test mode250or normal mode260. The output of gate272is coupled to an input of the gate273. The other input of the gate273is coupled to the output of the comparator250. The output of the gate273is coupled to the charge pump280, and provides as an output an enable signal281. The charge pump280is configured to increment the gate voltage Vg208(voltage that is applied to the gate of the regulator FET220) upon each edge of the clock signal282when the enable signal281is active.

Although logic270has been illustrated and described as having the inverter271, and gates272and273, the logic270may include other logic to control the enable signal281of the charge pump280as known by one of ordinary skill in the art.

The following tables include the drain-to-source voltage Vds, gate-to-source voltage Vgs, gate voltage Vg of the regulator FET220, and the output voltage Vdd, and the parameter that is actively controlled, such as Vdd or Vgs. Table 1 includes various values of the voltages of the device for differing values of the HVWPR205during normal mode260of operation.

Table 2 includes various values of the voltages of the device for differing values of the HVWPR205during test mode250of operation.

In one embodiment, the test mode250may be register activated and, therefore, is a microprocessor controlled mode of operation. Alternatively, the test mode250may be activated using other techniques that are known by one of ordinary skill in the art.

The voltage converter231is configured to convert a differential voltage to a single-ended voltage referenced to a ground potential, for example, if the gate voltage Vg208is equal to approximately 7.9V and the output voltage Vdd206is approximately 3.9V, then the single-ended output voltage is 4.0V with respect to the ground potential. In particular, voltage converter231is configured to sense the gate-to-source voltage Vgs216of the regulator FET220. The Vgs216is a differential voltage between the gate voltage Vg208and the output voltage206Vdd. The differential voltage is not with respect to a ground potential. In order to convert the differential voltage to be with respect to the ground potential, the voltage converter231converts the Vgs216to be the differential value with respect to the ground potential. The differential value with respect to the ground potential is input into the divider circuit230and divided by a fraction, such as approximately 3.2 or 3.8, as described above.

In one embodiment, the voltage converter231includes a resistive voltage divider to divide down the gate-to-source voltage (Vgs)216. In another embodiment, the voltage converter231includes a capacitive voltage divider to divide down the Vgs216. In one embodiment, the capacitive divider includes a high-voltage switch that is controlled using high-voltage control signals. In another embodiment, the capacitive divider includes a high-voltage switch that is controlled using low-voltage control signals. Embodiments of divider circuits that perform the differential-to-single-ended conversions are described below with respect toFIGS. 3,4, and6. It should also be noted that although the voltage converter231is illustrated as a separate block than the divider circuit230, the voltage converter231and divider circuit230may be integrated into a single block of the DFT circuit300.

The above embodiments described with respect toFIG. 2are configured to disable the internal voltage regulator to voltage stress test the core block210of the device. These embodiments are configured to allow selection of a test voltage for stress testing at the time of testing, rather than being a fixed voltage designed into the device.

FIG. 3illustrates a schematic of one embodiment of a circuit300having a resistive divider301and a voltage converter302. The circuit300is configured to sense the differential voltage between Vg206and Vdd208by voltage dividing the voltages using the resistive divider301. Different values of resistances may be used for the resistors of the resistor dividers in order to divide down the respective voltages by fractions, such as described above with respect to the divider circuits230and240. The circuit300is also configured to perform the differential-to-single-ended conversion using switched capacitor. In particular, a first transistor T1311is coupled to node303of the divided voltage of Vg208, and is configured to receive an inverted signal305(P1B) of a first control signal306(P1) at a gate of the first transistor T1311. A second transistor T2312is coupled to node304of the divided voltage of Vdd206, and is configured to receive the inverted signal305(P1B) at a gate of the second transistor T2312. When the first and second transistors are activated by the inverted signal305, a first capacitor321is switched in between the voltage at node303and the voltage at node304, resulting in the differential voltage between Vg206and Vdd208.

This differential voltage on C1321can be converted to a single-ended voltage referenced to ground using the voltage converter302. The voltage converter302includes a third transistor, a fourth transistor and a second capacitor C2322. The third transistor T3313is coupled to one end of C1321and one end of the C2322. The fourth transistor T4314is coupled to the other end of C1321and ground203. The second capacitor C2322is coupled between the third transistor T3313and ground203. The third and fourth transistors are both configured to receive a second control signal at each of their gates, activating the third and fourth transistors to convert the differential voltage on C1321to a single-ended voltage on the second capacitor C2322at the output node330, which is referenced to ground203.

One disadvantage of the circuit300may be the size of the layout of the circuit300. The resistive divider301on Vg208would have to be at least 20 Mega Ohms (MOhms) to limit the load on Vg208to the same range as the switched capacitor sampling of Vg208illustrated in the circuit700ofFIG. 6, resulting in a layout that is more than 50 times larger than the circuit700, for example.

Alternatively, instead of using a resistive divider, a capacitive divider may be used, such as illustrated in and described with respect toFIG. 4.

FIG. 4illustrates a schematic of one embodiment of a circuit400having a capacitive divider401and a voltage converter402. The circuit400is configured to sense the differential voltage between Vg206and Vdd208by voltage dividing the voltages using the capacitive divider401. The circuit400is also configured to perform the differential-to-single-ended conversion using switched capacitors.

In this embodiment, a first transistor T1411is coupled between node403and the voltage Vg208. However, unlike the transistors described with respect toFIG. 3, the first transistor T1411is a high-voltage transistor. A high-voltage transistor is a transistors that is configured to tolerate a high voltage drain-to-source voltage, such as greater than 5.0V. High-voltage transistors include a maximum allowable drain-to-source voltage that is greater than approximately 5.0V. High-voltage transistors and high voltage signals have been labeled as (HV) in the corresponding figures; otherwise, if the transistors or control signals do not include the (HV) label, the transistors or control signals are not high-voltage transistors or high voltages. In one embodiment, the high-voltage transistors are configured to tolerate up to approximately 40V drain-to-source voltage. Alternatively, other values may be used. The first transistor T1(HV)411is configured to receive a high-voltage, inverted signal405(P1B (HV)) of a first control signal406(P1) at a gate of the high-voltage, first transistor T1411. The inverted signal405(P1B (HV)) is a high-voltage control signal. A low-voltage control signal (P1B) is translated to a high-voltage control signal (P1B (HV)).

The circuit400also includes a second transistor T2412that is coupled between the node404and the voltage Vdd206, and is configured to receive the inverted signal406(P1B) at a gate of the second transistor T2412. When the first and second transistors are activated by the inverted signal405(HV) and the inverted signal406, a first capacitor421is switched in between the voltages Vg206and Vdd208, resulting in the differential voltage between Vg206and Vdd208on capacitor C1421. The differential voltage Vg206with respect to Vdd208is sampled on C2and then referenced to ground (a differential-to-single-ended conversion). The signal is divided down by charge sharing with C2. Then the output capacitor, C3, is updated.

This differential voltage on C1421can be converted to a single-ended voltage referenced to ground using the voltage converter402. The voltage converter402includes a fourth transistor T4414coupled between the node404and ground203. The fourth transistor T4414is configured to receive a second control signal407(P2) at a gate of the fourth transistor T4414. The control signal407activates the fourth transistors to reference the differential voltage between Vg206and Vdd208to ground203.

The voltage at403with respect to ground203, which represents the value of the differential voltage between Vg206and Vdd208, is divided down using the capacitive divider401. The capacitive divider401includes a third transistor T3(HV)413disposed between node403and one end of a second capacitor C2422that has the other end coupled to ground203. The third transistors T3(HV)413is a high-voltage transistors similar to the first transistor. The third transistors T3(HV)413is configured to receive the second control signal407(P2) at a gate of the third transistor. When the third transistor is activated, charge is shared with the second capacitor C2422. By charge sharing the voltage on the first capacitor C1421with the second capacitor C2422, the differential voltage can be divided by a fraction. The value of the capacitors can be selected to determine the fraction by which the voltage at403is divided.

After the charge is shared between the first and second capacitors421and422, the output capacitor C3423is updated using a fifth transistor T5415and a sixth transistor T6416. The fifth transistor415is configured to receive the first control signal408(P1) to activate the fifth transistor, and the sixth transistor416is configured to receive the second control signal407(P2) to activate the sixth transistor. When the sixth transistor416is activated, the voltage on the second capacitor422is updated on the third capacitor C3423at the output node430, which is referenced to ground203.

One disadvantage of the circuit400may be the generation of high-voltage control signals, such as the inverted signal405(P1B (HV)) of the first control signal408(P1), because a low-voltage control signal needs be translated into a high-voltage control signal. Additional circuitry may be used to translate the low-voltage control signal into a high-voltage control signal. The additional circuitry that translates the low-voltage control signal (P1B) into a high-voltage control signal (P1B (HV)) should not draw too much current from Vg208, otherwise, the charge pump (e.g., charge pump280) that supplies Vg208will need to be increased in size to accommodate the increased load. In addition, the translation circuit must work for all possible values of Vg208, and the high-voltage control signal405needs to closely track Vg208. When the high-voltage transistor (e.g., PMOS FET)411, controlled by the control signal405(e.g., P1B (HV)) is off, the control signal405needs to be equal to approximately Vg208. When the high-voltage transistor (e.g., PMOS FET)411is to be on, the control signal405needs to be more than 1V below Vg208, but not more than 5.5V below Vg208to prevent damage to the high-voltage transistor411(e.g., high-voltage switch).

Although the layout of circuit400ofFIG. 4may be smaller than the layout of circuit400ofFIG. 3using capacitive divider, the circuit400ofFIG. 4still includes the disadvantage of controlling a high-voltage transistor using high-voltage control signals, such as control signal405(P1B (HV)). Embodiments described below with respect toFIGS. 5 and 6are directed to controlling a high-voltage transistor (also referred to as high-voltage switch) using low-voltage control signals, instead of high-voltage control signals as described inFIG. 4.

FIG. 5illustrates a schematic of one embodiment of a circuit500for controlling a high-voltage switch with low-voltage control signals. In this embodiment, the illustrated circuit controls a high-voltage transistor (e.g., PFET) with low-voltage control signals508(P1) and507(P2). The circuit500includes a first transistor T1511, which has its source coupled to a voltage supply of the voltage Vg208. In one embodiment, the voltage supply is the charge pump280. Alternatively, other voltage supplies may be used to supply the voltage Vg208ofFIG. 5. The circuit500also includes a second transistor T2512, which has its source also coupled to the voltage Vg208. The circuit500also includes a third transistor T3, which has a source coupled to the gates of the first and second transistors511and512. The first transistor T1511, second transistor T2512, and third transistor T3513are high-voltage transistors, and each has a maximum allowable drain-to-source voltage greater than approximately 5.0 volts. The third transistor T3513is configured to receive a first control signal508(P1) at a gate of the third transistor to turn the first and second transistors511and512on and off. In one embodiment, the first control signal508(P1), as well as the second control signal507(P2), are low-voltage control signals, in that the voltage of the first control signal508(P1) can be produced by logic operating at a low voltage. In this embodiment, the first, second, and third transistors are high-voltage transistors, having a maximum allowable drain-to-source voltage greater than approximately 5.0V; however, unlike the high-voltage transistors ofFIG. 4, the high-voltage transistors ofFIG. 5are controlled using low-voltage control signals (e.g., are less than or equal to approximately 5.0V).

The circuit500also includes a first capacitor C1521coupled between a ground potential203and a drain of the third transistor T3513, and a second capacitor C2522coupled between the ground potential203and a drain of the first transistor T1511. The second capacitor522is configured to be charged faster than the first capacitor521.

At time T=0, capacitors C1521and C2522are discharged and T2512and T3513are OFF. At T=1, the low-voltage control signal508(P1) is activated (e.g., goes HIGH), turning on T3513. With T3513on, current flows from gate voltage Vg208through T2512and T3513onto capacitor C1521. Since the gates of transistors T1511and T2512are connected, transistor T1511(e.g., the high-voltage PFET to be controlled) is also turned on. A current twice the size of the first current flows into capacitor C2522due to the 1:2 current mirror configuration. In one embodiment, the capacitance of the first and second capacitor521and522are the same, the second capacitor C2522is charged up to the gate voltage Vg208before current stops flowing into the first capacitor C1521. Alternatively, the first and second capacitors can be configured to be different capacitances so long as the voltage on the second capacitor C2522charges to the gate voltage Vg208before current stops flowing into the first capacitors C1521.

At time T=3, the first control signal508is de-activated (e.g., P1goes LOW), open circuiting T3513, cutting off current through both branches of the current mirror circuit and turning off T1511and T2512. At T=4, the second control signal507P2) is activated (e.g., P2goes HIGH) to discharge the first capacitor C1521, preparing the circuit500ready for the next time the first control signal (P1) is activated (e.g., asserted HIGH) to turn on transistors T1511and T2512. Accordingly, low-voltage control signals are used to control the switching of a high-voltage switch (e.g., turning on and off the high-voltage transistors.

In another embodiment, the circuit500also includes a fifth transistor T5515coupled between the second capacitor C2522and a third capacitor C3523. The third capacitor523is coupled to the drain of the fifth transistor T5515and the ground potential203. The fifth transistor T5515is configured to receive the second control signal507(P2) at a gate of the fifth transistor to divide a charge on the capacitor C2522at node503between the capacitor C2522and the third capacitor C3523.

Also, at T=4, the second control signal507(P2) is activated (e.g., P2goes HIGH) to divide down the voltage on the second capacitor C2522by charge sharing with a third capacitor C3523, as described above with respect to the fifth transistor T5515. By charge sharing the voltage on the second capacitor C2522with the third capacitor C3523, the gate voltage Vg208can be divided by a fraction. The value of the capacitors can be selected to determine the fraction by which the voltage at503is divided. The voltage at node504is the divided down voltage using the capacitive voltage divider502.

In another embodiment, the circuit500also includes a sixth transistor T6516coupled between the capacitor C3523and the ground potential203. The sixth transistor T6516is configured to receive the first control signal508at a gate of the sixth transistor T6516to reset the third capacitor C3523for the subsequent turn on of the sixth transistor node.

FIG. 5also illustrates a timing diagram of the first and second control signals508and507, respectively. The first control signal508is activated and de-activated first and then the second control signal507is activated and de-activated. This process repeats, alternating between activating and de-activating the first and second control signals508and507, respectively. Alternatively, other timing may be accomplished as known by one of ordinary skill in the art.

The circuit described herein may place a relatively small load current on the gate voltage Vg208to obtain control of the high-voltage switch (e.g., first transistor T1511). The circuit achieves control of high-voltage switches with relatively few circuit elements.

Embodiments of the present have been illustrated with metal-oxide-semiconductor field-effect-transistor (MOSFET) technology (e.g., NMOS or n-channel MOSFET or PFET or p-channel FET for the high-voltage switch) for ease of discussion. In alternative embodiments, other device types (e.g., Bipolar and BiCMOS, PMOS and CMOS) and process technologies, for example, Bipolar and BiCMOS, may be used. It should be noted that the circuits described herein may be designed utilizing various voltages.

FIG. 6illustrates a schematic of one embodiment of a circuit600having a capacitive divider601and a voltage converter602and a circuit603for controlling high-voltage transistors using low-voltage control signals. Circuit603is a similar circuit as described with respect toFIG. 5, which includes the transistors T1-T4511-514and the first and second capacitors521and522. In particular, the circuit600is similar to the circuit500, except circuit600also includes a switch and a capacitor for sampling and holding the output at node605. The output at node605is available at all times whereas the output at node505ofFIG. 5is only accurate at the end of cycle of the second control signal507(P2) at time=5. The output at node605ofFIG. 5is at ground potential203while the first control signal508(P1) is HIGH.

The circuit603is coupled to the voltage converter602, which include the fifth and sixth transistors T5615and T6616coupled to the other end of the second capacitor622. The fifth transistor615is configured to receive an inverted signal609of the first control signal608at a gate of the fifth transistor to couple the second capacitor to a voltage potential. In this embodiment, the voltage potential is the output voltage Vdd206, as described with respect toFIG. 2above. Alternatively, other voltages may be used. The sixth transistor616is coupled between the second capacitor622and the ground potential203. The sixth transistor616is configured to receive the second control signal607to convert a differential voltage (Vg-Vdd) between a drain voltage (e.g., Vg208) of the first transistor611and the voltage potential (e.g., Vdd206) to a voltage, having a value of the differential voltage, referenced to the ground potential203.

The circuit603is also coupled the capacitive divider circuit601. The capacitive divider circuit601includes a seventh transistor T7617coupled to the drain of the first transistor T1611at node603and a third capacitor C3623, which is coupled to the ground potential203. The seventh transistor T7617is configured to receive the second control signal607to divide a charge on the second capacitor C2622between the second capacitor622and the third capacitor623.

In another embodiment, the circuit600includes an eighth transistor T8618coupled between the node604and the ground potential203. The eighth transistor T8618is configured to receive the first control signal608at a gate of the eighth transistor to reset the third capacitor C3623for the subsequent turn on of the seventh transistor T7617.

In another embodiment, the circuit600includes a ninth transistor T9619coupled between the node604(one end of the third capacitor C3623) and the output node605, which is at the one end of the fourth capacitor C4624, while the other end is coupled to the ground potential203. The ninth transistor T9619is configured to receive the second control signal607at a gate of the ninth transistor to transfer a charge on the third capacitor C3623to the fourth capacitor C4624. The fourth capacitor C4624is configured to store a charge of a previous cycle. Accordingly, when the ninth transistor T9619receives the second control signal607at the gate, the ninth transistor T9619is configured to adjust up or adjust down a charge on the fourth capacitor C4624based on the charge of the previous cycle.

FIG. 6also illustrates a timing diagram of the first and second control signals608and607, and the inverted control signal609, respectively. The first control signal608is activated and de-activated first and then the second control signal607is activated and de-activated. The inverted control signal609is the inverted signal of the first control signal608. At time period1, P2607is HIGH and P1608is LOW. The capacitor C1621is discharged to ground. At time period2, P1608is HIGH and P2607is LOW. Current flows into C1621until the voltage on C1621is high enough to turn off the high voltage transistor611(e.g., PMOS FET) connected to Vg208in branch having the first capacitor C1of the circuit600. The current is mirrored into the capacitor C2622. Since the ratio of the current mirror is two and the capacitance C1is greater than C2, C2is fully charged to Vg208. This allows the high-voltage transistor T1611to be turned on and off using low-voltage control signals. Since the second capacitor's622bottom plate is connected to the voltage Vdd206, the C2622is charged with the differential voltage (e.g., Vgs216) of Vg208less Vdd206(e.g., Vg−Vdd). The voltage Vgs216is gate-to-source voltage of the regulator FET220ofFIG. 2. The capacitor C3623is discharged to ground. The fourth capacitor C4624remains charged to the result of the previous cycle. At time period3, the P2607is HIGH and P1608is LOW. The current mirror is off and the C2622is referenced to ground. This performs a differential-to-single-ended conversion. Since P2607is HIGH, the top plates of the C2622and C3623are connected. Since C3623was previously discharged, the charge on C2622is shared between C2622and C3623. If C2622and C3623are sized properly, the sampled voltage Vgs216is divided by a fraction, such as approximately 3.2, as described above. Also during this clock phase, the C4624is connected to the divided down voltage Vgs216at node604. Since the C4624was charged to the previous output, the output is adjusted up or down depending on the sampled divided down voltage Vgs216at node604. This process repeats, alternating between activating and de-activating the first and second control signals608and607, respectively. Alternatively, other timing may be accomplished as known by one of ordinary skill in the art.

The embodiments described above for controlling high-voltage transistors using low-voltage control signals may be used to reduce a current load on the voltage source, such as the charge pump280. The embodiments described above for controlling high-voltage transistors using low-voltage control signals may be used to reduce die area of the circuit.

FIG. 7illustrates a flow chart of one embodiment of a method700for disabling an internal voltage regulator of a circuit to voltage stress test the circuit. Method700includes providing a circuit having an internal voltage regulator, operation701, and disabling the internal voltage regulator to voltage stress test the circuit, operation702. In operation702, although the internal voltage regulator is no longer regulating, the internal voltage regulator functions as a switch connecting the high voltage supply to the internal supply voltage and causes the gate-to-source voltage of the regulating FET to be equal to the internal supply voltage. The method700may also include voltage stress testing the circuit, operation703, and/or voltage stress testing a gate oxide of the regulator FET of the internal voltage regulator, operation704. As part of voltage stress testing the internal core block, the method includes applying a voltage to the internal core block that is higher than a maximum voltage allowed by the internal voltage regulator.

In one embodiment, the operation of disabling the internal voltage regulator includes sensing the gate-to-source voltage Vgs of the regulator FET, sensing a voltage (Vdd) applied to the internal core block, comparing the voltage Vdd and the Vgs, and controlling the Vgs of the regulator FET, based on the comparison of the voltage Vdd and the Vgs, to allow the voltage Vdd applied to the internal core block to be higher than a maximum voltage allowed by the internal voltage regulator.

In another embodiment, the method700includes selecting at least one of a test mode of operation or a normal mode of operation. The operation of disabling the internal voltage regulator of the circuit includes disabling the internal voltage regulator while in the test mode.

FIG. 8illustrates a flow chart of one embodiment of a method800for controlling a high-voltage transistor using low-voltage control signals. Method800includes providing a first transistor having a source coupled to a first voltage supply (e.g., high-voltage supply that is greater than 5.0V), operation801. The first transistor has a maximum allowable drain-to-source voltage greater than approximately 5.0 volts. The method800also includes controlling (e.g., turning on and off) the first transistor with first and second low-voltage control signals (e.g., less than or equal to 5.0V), operation802. The first and second low-voltage control signals may be produced by logic operating on a second voltage supply that is a low-voltage supply (e.g., 5V or less) relative to the first voltage supply (e.g., high-voltage supply). The maximum voltage of the first and second control signals is less than the maximum allowable drain-to-source voltage of the first transistor.

The method800also includes turning on the first transistor by providing a second transistor (high-voltage transistor) having a source coupled to the first voltage supply (e.g., high-voltage supply), operation803. The operation of turning on the first transistor includes receiving the first control signal at a gate of a third transistor, which is coupled to the gates of the first and second transistors, to turn on the first and second transistors, operation804. The operation of turning on the first transistor includes charging a first capacitor at a first rate while the first transistor is turned on, operation805. The operation of turning on the first transistor also includes charging a second capacitor at a second rate, which is faster than the first rate, while the second transistor is turned on, operation806.

The method800also includes turning off the first transistor by de-asserting the first control signal at the gate of the third transistor to turn off the first and second transistors, operation807. The operation of turning off the first transistor also includes receiving the second control signal at a gate of a fourth transistor having a source coupled to the drain of the third transistor, operation808, and discharging the first capacitor for a subsequent turn on of the first and second transistors while the fourth transistor is turned on, operation809.

The operation of turning off the first transistor may also include receiving an inverted signal of the first control signal at a gate of a fifth transistor to couple the second capacitor to a voltage potential, receiving the second control signal at a gate of a sixth transistor to activate the sixth transistor, and converting a differential voltage between a drain voltage of the first transistor and the voltage potential to a voltage with respect to ground when the sixth transistor is activated. The inverted signal may be produced by logic operating on the second voltage supply (e.g., low-voltage supply).

The operation of turning off the first transistor may also include receiving the second control signal at a gate of a seventh transistor to activate the seventh transistor, and dividing a charge on the second capacitor between the second capacitor and a third capacitors that is coupled to a drain of the seventh capacitor and the ground potential when the seventh transistor is activated.

The embodiments described above with respect to controlling a high-voltage transistor using low-voltage control signals may be used to reduce a current load on a voltage supply, such as a charge pump. The embodiments described above may be used to reduce the die area of the circuit.

Embodiments of the present invention, described herein, include various operations. These operations may be performed by hardware components, software, firmware, or a combination thereof. As used herein, the term “coupled to” may mean coupled directly or indirectly through one or more intervening components. Any of the signals provided over various buses described herein may be time multiplexed with other signals and provided over one or more common buses. Additionally, the interconnection between circuit components or blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be one or more single signal lines and each of the single signal lines may alternatively be buses.