Quadrature sampling system and hybrid equalizer

A quadrature sampling system and method (BQS) and a hybrid quadrature sampling and channel equalization system and method (BQS/EQ) which convert input signals to baseband inphase and quadrature signal components. The BQS system includes an inphase signal channel including a first set of K filters, and a signal summer which sums the outputs of the first set of K filters to produce the inphase signal component; a quadrature signal channel including a second set of K filters, and a signal summer which sums the outputs of the second set of K filters to produce the quadrature signal component; and a controlled switch which provides input samples to the inphase and quadrature signal channels so that each filter of both channels receives one input sample of each sequence. The BQS/EQ system includes first and second sets of signal processing filter pairs, each pair including an inphase and a quadrature filter. A controlled switch alternately switches input samples between the first and second sets of signal processing filter pairs and applies selected ones of the input samples to each filter pair so that each filter pair receives one input sample of each sequence. The outputs of the filters pairs of each set are selectively provided to the inphase and quadrature signal summers.

BACKGROUND OF THE INVENTION 
In many coherent sonar, radar, and communication applications, it is useful 
for the receiver outputs to be converted to baseband inphase and 
quadrature (denoted by I and Q) signal components. This process is 
referred to as quadrature sampling. When the application uses Digital 
Signal Processing (DSP), the I and Q signals are converted to digital 
signals by analog to digital (A/D) converters. 
FIG. 1 shows a conventional analog quadrature sampler 10. The intermediate 
frequency (IF) input centered around the carrier frequency 
.function..sub.c is mixed down to baseband via mixers 11, 12 by 
cos2.pi..function..sub.c t and sin2.pi..function..sub.c t local oscillator 
signals. The results are lowpass filtered by filters 13, 14 to eliminate 
the image signal generated while mixing, and then are passed to A/D 
converters 15, 16 to produce digital baseband I and Q signals. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a digital baseband 
quadrature sampling (BQS) system, which is configured with finite impulse 
response (FIR) filters. 
It is another object of the present invention to provide efficient BQS 
module architecture, which has half the computational requirement of the 
conventional architectures. 
It is yet another object of the present invention to provide a new hybrid 
filter architecture, which combines the BQS and EQ filter into one hybrid 
filter, and which is far more efficient than the conventional hybrid 
filter architectures. 
According to one embodiment of the present invention there is provided a 
quadrature sampling system and method which converts input signals to 
baseband inphase and quadrature signal components. The system includes 
circuitry which receives the input signal having a frequency centered 
around a predetermined carrier frequency. A signal processor such as an 
analog to digital converter continuously samples the input signal at a 
carrier frequency which is centered around a selected ratio, for example 
(2N+1)/4, of the sampling rate to produce discrete sequences of 2K input 
samples. An inphase signal channel includes a first set of K filters each 
having respective filter coefficients, and a signal summer which sums the 
outputs of the first set of K filters to produce the inphase signal 
component. A quadrature signal channel includes a second set of K filters 
each having respective filter coefficients, and a signal summer which sums 
the outputs of the second set of K filters to produce the quadrature 
signal component. The input samples are provided to the inphase and 
quadrature signal channels so that each filter of both channels receives 
one input sample of each sequence. 
According to another embodiment of the present invention there is provided 
a hybrid quadrature sampling and channel equalization system and method 
which converts input signals to equalized baseband inphase and quadrature 
signal components. The system includes circuitry which receives the input 
signal having a frequency centered around a predetermined carrier 
frequency. A signal processor such as an analog to digital converter 
continuously samples the input signal at a carrier frequency which is 
centered around a selected ration, for instance (2N+1)/4, of the sampling 
rate to produce discrete sequences of 2K digital input samples. There is 
provided first and second sets of signal processing filter pairs each 
including an inphase filter having an inphase filter coefficient and a 
quadrature filter having a quadrature filter coefficient. The input 
samples are alternately switched between the first and second sets of 
signal processing filter pairs and selected ones of the input samples are 
applied to each filter pair so that each filter pair receives one digital 
input sample of each sequence. An inphase signal summer is operable for 
summing the outputs of selected filters from each of the signal processing 
filter sets to produce the inphase signal component. A quadrature signal 
summer is operable for summing the outputs of selected filters from each 
of the signal processing filter sets to produce the inphase signal 
component. The outputs of the filters pairs of each set are selectively 
provided to the inphase and quadrature signal summers.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS 
With reference now to FIG. 2, there is shown an exemplary architecture of 
an adaptive radar system 20 which represents one example of system 
application for the present invention. The RF signal received by the 
antenna 21 is converted to IF signal by the receiver 22. The IF signal is 
converted by A/D converter 23, and then passed to a baseband quadrature 
sampler (BQS) module 24 which digitally generates in-phase (I) and 
quadrature (Q) parts from the A/D output. The I/Q pair is then channel 
equalized by channel equalizer 25, pulse compressed at pulse compressor 
26, and provided to an adaptive processor such as space time adaptive 
processor (STAP processor) 27. 
There are numerous alternative approaches for implementing the quadrature 
sampling technique. FIG. 3 shows an exemplary functional block diagram of 
a digital BQS in accordance with the present invention. The quadrature 
sampler 30 has one A/D converter and digital mixers 32, 33. The lowpass 
filtering is carried out digitally as well with finite impulse response 
(FIR) filters 34, 35. Assuming the A/D sampling rate .function..sub.s is 
equal to 4/(2N+1).function..sub.c, i.e., the input IF signal is centered 
around (2N+1)/4 of the A/D sampling rate, then digital 1, 0 and -1 values 
can be used for the local oscillator signals cos2.pi..function..sub.c t 
and sin2.pi..function..sub.c t. This configuration greatly simplifies the 
digital mixing operations to produce the baseband in-phase (I) and 
quadrature (Q) components. The digital N-tap FIR lowpass filters 34, 35 
reject the signal beyond .+-..function..sub.c /2 in order to eliminate the 
negative frequency sideband and the DC component. The filter output is 
decimated by a factor of 4 by decimation circuits 36, 37 to produce the 
digital baseband signal (Nyquist output). 
The quadrature sampler 10 in FIG. 1 requires that the inphase and 
quadrature channels be closely matched. The quadrature sampler 30 
utilizing one A/D and digital mixing as in FIG. 3 eliminates the channel 
matching requirement. The disadvantage of the quadrature sampler in FIG. 3 
is that it requires the A/D to run at four times the rate of the device 
shown in FIG. 1. However, as high speed A/D's are now readily available, 
this is becoming less significant. 
When 1, 0 and -1 values are to be used for the mixing signals 
cos2.pi..function..sub.c t and sin2.pi..function..sub.c t in FIG. 3, half 
of the filter inputs are zeros. Accordingly, a quadrature sampling system 
40 can be configured as shown in FIG. 4 for simplification. The system 40 
includes A/D converter 41, a processor controlled switch 42, FIR filters 
43, 44, and decimation circuits 45, 46. The h(n) is the original N-tap 
filter coefficients, and h.sub.I (n) and h.sub.Q (n) are N/2 tap filter 
coefficients related to h(n) by, for example: 
EQU h.sub.I (n)=(-1).sup.n+1 h(2n+1) 
EQU h.sub.Q (n)=(-1).sup.n+1 h(2n)n=0,1 . . . ,(N/2)-1 
It will be appreciated that since h.sub.I (n) and h.sub.Q (n) are followed 
by a decimation by a factor of two, half the filter outputs are discarded. 
The even numbered samples are switched to go to the h.sub.I (n) filter and 
the odd numbered samples go to the h.sub.Q (n) filter. The "odd" and 
"even" can be reversed in FIG. 4, and the system operates just as well. 
This quadrature sampling technique has half the computational requirement 
as the scheme shown in FIG. 3. 
FIG. 5 shows an exemplary embodiment of a quadrature sampling system 50 in 
accordance with the present invention which reduces the digital 
computation requirement by a factor of two compared to the scheme in FIG. 
4. Since h.sub.I (n) and h.sub.Q (n) filters of FIG. 4 are followed by the 
decimation by a factor of two, 50% of the filter outputs are discarded. 
Assume now that only the even numbered points form the outputs I(n) and 
Q(n) are used. That means I(2n) and Q(2n) need to be computed but I(2n+1) 
and Q(2n+1) don't need to be computed, where n=0,1,2, . . . ,(N/4)-1. The 
I(2n) and Q(2n) can be rewritten as 
##EQU1## 
where x.sub.I (n) and X.sub.Q (n) are the inputs to the filters h.sub.I 
(n) and h.sub.Q (n) respectively. The output of the A/D converter will be 
referred to as x(n). Notice that each of I(2n) and Q(2n) is equivalent to 
the sum of two FIR filter outputs whose throughput is half the rate. Using 
a polyphase filtering technique, further optimization can be made to 
result in the system as shown in FIG. 4. The inputs are alternately routed 
to the four filters whose coefficients are 
EQU h.sub.Ia (n)=h.sub.I (2n+1) 
EQU h.sub.Ib (n)=h.sub.I (2n)n=0,1, . . . (N/4)-1 
and 
EQU h.sub.Qa (n)=h.sub.Q (2n+1) 
EQU h.sub.Qb (n)=h.sub.Q (2n)n=0,1, . . . (N/4)-1 
Accordingly, the input x(n) from A/D converter 51 is alternately directed 
by processor controlled switch 52 to four different filters 53-56 as shown 
in FIG. 5. The two (N/2)-tap filters of FIG. 3 running at 
2.function..sub.c Hz are now replaced by four (N/4)-tap filters running 
1/4 as fast, or at .function..sub.c Hz. The total number of taps do not 
change from FIG. 4 to FIG. 5, but the filter throughput requirement 
decreases by a factor of two. 
It will be appreciated that in the illustrated exemplary embodiment of FIG. 
5, N is a multiple of 4. That makes all the filters in FIG. 5 symmetrical 
and easy to design. If N is not a factor of 4, h(n) can be padded with 
zero's to make it a multiple of 4 in length. In addition, a system using 
2K number of (N/2K)-tap filters can easily be configured. 
The cos and sin functions in FIG. 3 can have arbitrary initial phase. In a 
more general form, these functions would be written as 
cos(2.pi..function..sub.c t+.phi.) and sin(2.pi..function..sub.c t+.phi.), 
where .phi. is the initial phase value. There are four possible values of 
.phi. that allow the cos and sin functions to be 1, 0, and -1. These 
initial values are 0, .pi./2, .pi., and 3.pi./2. Accordingly, this will 
set the stage for the possible sets of coefficients for the filters of 
FIG. 5. 
The quadrature sampling system 50 of FIG. 5 accepts discrete sets of four 
input samples at a time and produces the corresponding output sample. An 
output sample consists of an I value and a Q value. It is important to 
ensure which four input samples are processed to produce an output sample. 
This is due to the fact that the additions by summation circuits 57, 58 in 
FIG. 5 have to be performed on correct filter outputs. The corresponding 
filter outputs are added to produce an output sample. 
Once the set of filter coefficients are chosen, the four input samples, 
that are being processed to produce one output sample, should go to the 
filters in a predetermined order. There are various ways to group the 
input x(n) into sets for the four samples mentioned above. For example, in 
the input grouping, the first sample can be n(mod4)=0, n(mod4)=1, 
n(mod4)=2, or n(mod4)=3. Choosing which sample is the first of four input 
samples is equivalent to choosing which output values are kept after 
decimation in the scheme of FIG. 3. Once the first of four samples is 
chosen, the next input can be the second sample and so on. Therefore, the 
mapping of the input x(n) to the filters shown in FIG. 5 is only one of 
several possible mappings. 
The critical advantage of the quadrature sampler 50 of FIG. 5 over the 
sampler 40 shown in FIG. 4 is that the sampler 50 has approximately half 
the computational requirement. Although the number of total taps used in 
FIR filters is the same, the proposed filter has half the throughput 
requirement on the filters. The reduced computational requirement can 
reduce the size, weight, power, and cost approximately by a factor of two 
while keeping the sampler size, weight, power, and cost requirement about 
the same as the conventional sampler. 
FIG. 6 shows an exemplary generalized embodiment of a quadrature sampling 
system 60 with a decimation factor of 2K in accordance with the present 
invention. Each filter bank 63, 64 includes K filters 63a-63c, 64a-64c 
with N/2K taps. The input x(n) from A/D 61 is alternatively routed by 
processor controlled switch 62 so that all 2K filters receive one input of 
the 2K consecutive input samples. The input x(n) is also routed so that 
the input sample alternates between the I set of K filters 63 and the Q 
set of filters 64. The computational savings over that of FIG. 3 is equal 
to a factor of 4K, while the computational savings over that of FIG. 4 is 
equal to a factor of K. 
A very useful feature of the proposed quadrature sampler is that its 
computations are done mostly in FIR filters. The FIR filter computation 
can be very efficiently implemented in VLSI structures. It is also 
possible to implement FIR filter using Discrete Fourier Transform (DFT) or 
Fast Fourier Transform (FFT). 
In some applications involving relatively low data rates, the quadrature 
sampler can be implemented mostly in software. Even in software 
implementation, the proposed quadrature sampler reduces the computation 
requirement by 50% over the conventional samplers. 
Now for illustrative purposes and assuming a radar application where 
.function..sub.s =4.function..sub.c, the following description pertains to 
the operation of the BQS of FIG. 3. FIGS. 7A-7G show the frequency domain 
illustration of the BQS process. FIG. 7A shows the frequency spectrum at 
the input of the A/D converter. FIG. 7B shows the frequency response of an 
analog anti-aliasing filter (not shown) which is coupled at the front end 
of the A/D converter. The exemplary 4:1 down-sampling BQS scheme has the 
advantage that the analog anti-aliasing filter does not require very sharp 
transition bands. The lenient transition band requirement makes it easier 
for the analog anti-aliasing filter to be very flat and well behaved in 
the passband and to also have the high stopband rejection. The well 
behaved filter response is easier to equalize, and the high stopband 
rejection increases the signal to noise ratio. The filter's passband can 
be extended slightly beyond the signal band to provide some safety margin 
to make sure that the filter response is well behaved at the signal band 
edges. 
FIG. 7C shows the frequency spectrum at the output of the A/D converter. 
FIG. 7D is the frequency spectrum after the digital baseband conversion. 
FIG. 7E shows the frequency response of the BQS filter. FIG. 7F shows the 
frequency spectrum after BQS filtering, and FIG. 7G shows the frequency 
spectrum after decimation by 4:1. 
FIG. 8 shows enlarged versions of the output shown in FIG. 7G with the 
effect of BQS filter superimposed. The filter shape is plotted in dotted 
lines. Because the BQS filter is implemented digitally, the filter 
responses are identically matched in all the channels. In order to prevent 
aliasing into the passband, the filter gain should be sufficiently low at 
the ends of the transition bands. It will be appreciated that the 
transition band is from the passband edge to the passband edge, and not 
from the passband edge to Nyquist frequency of .function..sub.c /2. This 
is due to interest only in preventing aliasing into the passband. 
The number of taps needed for the lowpass BQS FIR filter depends on the 
requirements on passband ripple, stopband rejection, and transition width. 
Generally, low passband ripple, high stopband rejection, and low 
transition width are desired. Also desired is low passband signal loss, 
which depends on the passband shape. 
Although low passband ripple is generally desired in a BQS filter, it is 
usually not the limiting factor in, for example, applications involving 
radar performance. The passband ripples are exactly matched in all the 
channels because the BQS filters are implemented digitally. Therefore, the 
passband ripple does not effect the cancellation ratio. However, very 
large passband ripple will result in signal distortion. A reasonable 
practice is to keep the passband ripple below a few tenths of a dB. 
The stopband rejection is more critical to the BQS filter operation. 
Insufficient stopband rejection causes aliasing. However, very high 
stopband rejection requires too many taps on the filter. How much stopband 
rejection is required depends very heavily on the system specifications. 
The low transition width results in low I/Q output sampling rate. Reduced 
data rate reduces computational requirement in subsequent processing tasks 
such as channel equalization, pulse compression, adaptive nulling, etc. 
The lower transition width also results in lower A/D sampling rate, since 
the A/D sampling rate is equal to four times the I/Q sampling rate. 
However, making transition width very small requires many filter taps, and 
one has to make tradeoffs between transition width and hardware 
complexity. 
One can also reduce the number of filter taps without increasing I/Q 
sampling rate by accepting some passband signal loss. For example, the 
passband edge can be defined as the 3dB point of the filter instead of 
having all of the passband within the passband ripple. In general, the 
filter design has to make proper tradeoffs between passband ripple, 
stopband rejection, transition width, passband signal loss, and hardware 
complexity. 
The channel equalization (EQ) of the I and Q components requires a complex 
FIR filter configuration with programmable coefficients. FIG. 9 shows an 
exemplary complex FIR filter 100 which is implemented using four FIRs 
101-104 with their outputs combined with summation circuits 105, 106 as 
shown in FIG. 8. Two of the integer filters 101, 102 contain the in-phase 
part of coefficients and the other two filters 103,104 contain the 
quadrature coefficients. 
For example, in conventional UHF radar applications, the channel 
equalization filter equalizes channel responses of the receiver and an A/D 
converter. A test signal is injected at the front of the receiver and the 
A/D output data is used to compute the equalization coefficients. The 
equalization filter equalizes everything in the injection path including 
filters, circulators, amplifiers, connectors, cables, A/D, etc. 
Normally, the most critical element to be equalized is the anti-aliasing 
filter. The reason being that the anti-aliasing filter has relatively 
sharp frequency cutoff characteristics. In the process of achieving sharp 
cutoff characteristics, the anti-aliasing filter can end up with a 
significant channel mismatch. Other components generally have relatively 
flat frequency response around the passband and do not cause as 
significant mismatches. Therefore, how many taps are needed for channel 
equalization depends on what kind of analog filter is used as the 
anti-aliasing filter. 
It is possible to combine BQS and EQ filters into one hybrid complex FIR 
filter. Accordingly, an efficient hybrid filter architecture, which 
reduces the computational requirement by several fold, is described 
hereinafter. The functional block diagram of an exemplary hybrid BQS/EQ 
system 110 is shown in FIG. 10. The input IF signal, which is centered 
around (2N+1)/4 of the A/D sampling rate, is sampled by an A/D converter 
111. The sampled data is then digitally mixed to produce the baseband 
in-phase and quadrature components by respective digital mixers 112, 113. 
The I/Q signals are then N-tap complex FIR filtered with FIRs 114a, 114b, 
115a, 115b to eliminate the negative frequency sideband and the DC 
component as well as to equalize the passband response. The filter outputs 
are then decimated by a factor of 4 by decimation circuits 118, 119 to 
produce the equalized digital baseband signal. 
Four N-tap FIR filters are used to implement one N-tap complex FIR filter. 
Since half the filter inputs in FIG. 10 are zeroes, a simplification of the 
system is shown by exemplary system 120 in FIG. 11. The system 120 
includes an A/D converter 121, a processor controlled switch 122 for 
switching odd and even values between the FIR filters 123a, 123b, 124a, 
124b, summation circuits 125, 126, and decimation circuits 127, 128. The 
h.sub.I (n) and h.sub.Q (n) are the original N-tap filter coefficients. 
The h.sub.Ia (n) h.sub.Ib (n) h.sub.Qa (n) and h.sub.Qb (n) are the N/2 
tap filter coefficients related to h.sub.I (n) and h.sub.Q (n) by, for 
example: 
EQU h.sub.Ia (n)=(-1).sup.n+1 h.sub.I (2n+1) 
EQU h.sub.Ib (n)=(-1).sup.n+1 h.sub.I (2n) 
EQU h.sub.Qa (n)=(-1).sup.n+1 h.sub.Q (2n+1) 
EQU h.sub.Qb (n)=(-1).sup.n+1 h.sub.Q (2n)n=0,1, . . . ,(N/2)-1 
At this point, it will be appreciated that since h.sub.I (n) and h.sub.Q 
(n) are followed by a decimation by a factor of two, half of the filter 
outputs are discarded. Using a polyphase filtering technique, further 
optimization can be made to configure an exemplary hybrid BQS/EQ system 
130 in accordance with the present invention as is shown in FIG. 12. The 
discrete sets of inputs from A/D converter 131 are alternately routed by 
processor controlled switch 132 to the eight filters 133a-b, 134a-b, 
135a-b, 136a-b, whose respective coefficients are, for example: 
EQU h.sub.Ia1 (n)=h.sub.Ia (2n) 
EQU h.sub.Ia2 (n)=h.sub.Ia (2n+1) 
EQU h.sub.Ib1 (n)=h.sub.Ib (2n) 
EQU h.sub.Ib2 (n)=h.sub.Ib (2n+1) 
EQU h.sub.Qa1 (n)=h.sub.Qa (2n) 
EQU h.sub.Qa2 (n)=h.sub.Qa (2n+1) 
EQU h.sub.Qa1 (n)=h.sub.Qb (2n) 
EQU h.sub.Qa2 (n)=h.sub.Qb (2n+1)n=0, 1, . . . ,(N/4)-1 
The four N-tap filters in FIG. 10 are now replaced by eight (N/4)-tap 
filters running 1/4 as fast. The outputs of the filters are alternately 
applied to summation circuits 137, 138 to produce the I and Q components. 
For example, with consecutive mapping values n mod4=2, n mod4=0, n mod4=3, 
and n mod4=1, the output is switched such that the upper filter bank has 
the outputs from the FIRs with an I coefficient applied to the I summation 
circuit 137, and the outputs from the FIRs with a Q coefficient are 
applied to the Q summation circuit 138. The lower filter bank alternates 
such that the outputs from the FIRs with the I coefficient are applied to 
the Q summation circuit, and the negative value of the outputs from the 
filters with the Q coefficient are applied to the I summation circuit. It 
will be appreciated by those skilled in the art that other switching 
schemes are possible. 
The total number of taps do not change from FIG. 11 to FIG. 12, but the 
filter throughput requirement decreases by a factor of two. Overall, the 
computational requirements required is reduced by a factor of eight from 
FIG. 10 to FIG. 12. 
FIG. 13 shows another alternative embodiment of an exemplary generalized 
hybrid BQS/EQ system 140 with a decimation factor of 2K in accordance with 
the present invention. Each filter bank 143, 144 includes K I filters 
143a-c, 144a-c and K Q filters 143d-f, 144d-f, each with N/2K taps. The 
input x(n) from A/D 141 is alternatively routed by processor controlled 
switch 142 so that all 4K filters receive one input of the 2K consecutive 
input samples. The input x(n) is also routed so that two of the filters 
receive identical input, and so that the input sample alternates between 
the upper bank of K filters 143 and the lower bank of filters 144. The 
computational savings over that of FIG. 10 is equal to a factor of 4K, 
while the computational savings over that of FIG. 11 is equal to a factor 
of K. 
In comparing the efficiency of the separate BQS/EQ filters versus the 
efficiency of the hybrid filter in a case where k=2, a system with N BQS 
taps and M EQ taps will be considered. Most of the degrees of freedom in 
the BQS filter are used to reject the stopband. Therefore, the equivalent 
hybrid filter would need approximately N taps for stopband attenuation. 
For the EQ filter, most of the degrees of freedom can be made to equalize 
the passband by appropriate weighting. Therefore, the equivalent hybrid 
filter would need approximately M taps for passband equalization. 
Therefore, the equivalent hybrid filter would need N+M total taps. A 
system with N-tap BQS filter and M-tap EQ filter needs N+4M real taps 
running at the I/Q sampling rate. An equivalent hybrid filter with N+M 
complex taps needs 2(N+M) real taps running at the I/Q sampling rate. 
Therefore, if the BQS tap-count is much larger than the EQ tap-count, the 
separate filter approach is more efficient. However, if the EQ tap-count 
is much larger than the BQS tap-count, then the hybrid filter approach is 
more efficient. When the BQS filter tap-count is approximately twice the 
EQ filter tap-count (N=2M), the separate and hybrid approaches would be 
comparable. 
However, the hybrid filter will probably perform slightly better than the 
separate filters when N=2M. This is because several degrees of freedom in 
the BQS filter were used on the passband even though most of the degrees 
of freedom were used in the stopband. These several degrees of freedom do 
not perform passband equalization or stopband rejection. Therefore, the 
hybrid filter may use these several extra degrees of freedom for 
additional stopband attenuation and/or passband equalization. Whether the 
hybrid filter actually performs better needs to be verified by 
experiments. In addition, computing the hybrid filter coefficients 
requires more computation than computing the EQ filter coefficients, since 
the EQ filter has much fewer taps. 
The foregoing description has been set forth to illustrate the invention 
and is not intended to be limiting. Since modifications of the described 
embodiments incorporating the spirit and substance of the invention may 
occur to persons skilled in the art, the scope of the invention should be 
limited solely with reference to the appended claims and equivalents 
thereof.