SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

According to one embodiment, a semiconductor memory device includes a stacked film in which a plurality of silicon oxide layers, one of which having a film density of 2.3 g/cm3 or more, and a plurality of conductive layers, are alternately stacked in a first direction, and a memory pillar that penetrates the stacked film in the first direction, wherein a plurality of memory cells is provided in the memory pillar.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-041497, filed Mar. 16, 2023, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor memory device and a method for manufacturing the same.

BACKGROUND

A large-capacity non-volatile memory has been developed. This large-capacity non-volatile memory is capable of low-voltage and low-current operation, high-speed switching, and miniaturization and high integration of memory cells.

In a memory cell array provided in a large-capacity non-volatile memory, a large number of metal wirings called bit lines and word lines are arranged. A voltage is applied to a bit line and a word line connected to the cell, and data is written into one memory cell corresponding to the bit line and the word line. A semiconductor memory device has been proposed in which memory cells are arranged three-dimensionally and includes a stacked film in which conductive layers and insulating layers are alternately stacked to serve as such word lines.

DETAILED DESCRIPTION

Embodiments provide a semiconductor memory device having high reliability.

In general, according to embodiments, a semiconductor memory device includes a stacked film in which a plurality of silicon oxide layers, one of which having a film density of 2.3 g/cm3or more, and a plurality of conductive layers, are alternately stacked in a first direction, and a memory pillar that penetrates the stacked film in the first direction, wherein a plurality of memory cells is provided in the memory pillar.

Hereinafter, embodiments will be described with reference to the accompanying drawings. In the drawings, the same or similar parts are denoted by the same or similar reference numerals.

In the present specification, in order to indicate a positional relationship of components and the like, an upper direction of a drawing is described as “up”, and a lower direction of the drawing is described as “down”. In the present specification, the concepts of “up” and “down” are not necessarily terms indicating a relationship with the direction of gravity.

First Embodiment

A semiconductor memory device of the present embodiment includes a stacked film in which a plurality of silicon oxide layers having a film density of 2.3 g/cm3or more and a plurality of conductive layers are alternately stacked one layer at a time in a first direction, and a memory pillar that penetrates the stacked film in the first direction in which a plurality of memory cells is provided.

A method for manufacturing a semiconductor memory device of the present embodiment, the method includes forming a stacked film in which a plurality of first layers containing silicon and a plurality of second layers containing silicon nitride are alternately stacked one layer at a time in a first direction, forming an opening that penetrates the stacked film and extends in the first direction, and forming a plurality of silicon oxide layers between each of the plurality of second layers by oxidizing the plurality of first layers.

The overall configuration of the semiconductor memory device100will be described. The semiconductor memory device100according to the present embodiment is a NAND flash memory capable of storing data non-volatilely.FIG.1is a block diagram of a semiconductor memory device100according to the present embodiment.

The semiconductor memory device100includes a memory cell array90, a row decoder91, a column decoder98, a sense amplifier99, an input/output circuit94, a command register95, an address register96, a sequencer (which is generally a control circuit)97, and the like.

The memory cell array90includes j blocks BLK0 to BLK(j−1). j is an integer of 1 or more. Each of the plurality of blocks BLK includes a plurality of memory cell transistors. The memory cell transistor includes a memory cell configured to be electrically rewritten. The memory cell array90includes a plurality of bit lines, a plurality of word lines, a source line, and the like in order to control a voltage applied to the memory cell transistor. The specific configuration of the block BLK will be described later.

The row decoder91receives a row address from the address register96and decodes the row address. The row decoder91performs a selection operation of the word line or the like based on the decoded row address. The row decoder91transfers a plurality of voltages required for a write operation, a read operation, and an erasing operation to the memory cell array90.

The column decoder98receives a column address from the address register96and decodes the column address. The column decoder98performs a selection operation of the bit line based on the decoded column address.

The sense amplifier99detects and amplifies the data read from the memory cell transistor into the bit line during the read operation. In addition, the sense amplifier99transfers the write data to the bit line during the write operation.

The input/output circuit94is connected to an external device (e.g., host device) via a plurality of input/output lines (e.g., DQ lines). The input/output circuit94receives a command CMD and an address ADD from the external device. The command CMD received by the input/output circuit94is sent to the command register95. The address ADD received by the input/output circuit94is sent to the address register96. The input/output circuit94transmits and receives data DAT to and from the external device.

The sequencer97receives a control signal CNT from the external device. The control signal CNT includes a chip enable signal CEn, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WEn, a read enable signal REn, and the like. The “n” added to the signal name indicates the active low. The sequencer97controls the operation of the entire semiconductor memory device100based on the command CMD stored in the command register95and the control signal CNT.

FIG.2is an equivalent circuit diagram of the semiconductor memory device100according to the present embodiment.

As shown inFIG.2, the semiconductor memory device100includes a plurality of word lines WL, a common source line CSL, a source select gate line SGS, a plurality of drain select gate lines SGD, a plurality of bit lines BL, and a plurality of memory strings MS.

The memory string MS includes a source select transistor STS, a plurality of memory cell transistors MT, and a drain select transistor STD, which are connected in series between the common source line CSL and the bit line BL.

The number of word lines WL, the number of bit lines BL, the number of memory strings MS, and the number of drain select gate lines SGD are not limited to those inFIG.2.

FIG.3is a schematic cross-sectional view of a main part of the semiconductor memory device100according to the present embodiment.

The substrate11is, for example, a semiconductor layer containing single crystal silicon. For example, a semiconductor wafer or an SOI wafer may be used as the substrate11.

Here, an X direction, a Y direction that intersects perpendicularly to the X direction, and a Z direction that intersects perpendicularly to the X and Y directions are defined. The substrate11is provided parallel to the XY plane.

A plurality of first silicon oxide layers14and a plurality of conductive layers6bare alternately stacked one layer at a time on the substrate11in the Z direction. Accordingly, the stacked film S2is provided on the substrate11.

The film density of the plurality of first silicon oxide layers14is 2.3 g/cm3or more. For example, the film density may be 2.4 g/cm3.

The film density of the plurality of first silicon oxide layers14may be evaluated using, for example, X-ray reflectometry (XRR).

The film thickness of the plurality of first silicon oxide layers14in the Z direction is preferably 10 nm or more.

The hydrogen concentration of the plurality of first silicon oxide layers14is preferably 1×1020atoms/cm3or less.

The memory pillar H1penetrates the stacked film S2in the Z direction. A core insulating film1, a channel semiconductor layer2, a tunnel insulating film3, a charge storage film4, and an insulating film5aare provided in the memory pillar H1.

The core insulating film1is provided in the memory pillar H1. The core insulating film1contains silicon oxide, for example.

The channel semiconductor layer2is provided around the core insulating film1in the memory pillar H1. The channel semiconductor layer2functions as a channel of the memory pillar H1. The channel semiconductor layer2is a pillar containing a semiconductor material such as polysilicon.

The tunnel insulating film3is provided around the channel semiconductor layer2. Although the tunnel insulating film3is insulating, it is an insulating film that allows current to flow when a predetermined voltage is applied. The tunnel insulating film3contains, for example, silicon oxynitride.

The charge storage film4is provided around the tunnel insulating film3. The charge storage film4is a film containing a material capable of storing charges. The charge storage film4contains, for example, silicon nitride.

The insulating film5ais provided around the charge storage film4. The insulating film5acontains, for example, silicon oxide. The film density of the insulating film5ais less than the film density of the first silicon oxide layer14, for example, less than 2.3 g/cm3.

The insulating film5b, the barrier metal layer6a, and the conductive layer6bare provided between the first silicon oxide layers14adjacent to each other.

The insulating film5bis provided around each of the barrier metal layers6a(on the lower surface of each first silicon oxide layer14, the upper surface of each first silicon oxide layer14, and the side surface of the insulating film5a). The insulating film5bcontains a metal insulating material such as aluminum oxide.

The barrier metal layer6ais provided around each of the conductive layers6b(on the lower surface of the upper insulating film5b, the upper surface of the lower insulating film5b, and the side surface of the insulating film5bprovided on the side surface of the insulating film5a). The barrier metal layer6acontains, for example, titanium nitride.

The conductive layer6bis provided in the barrier metal layer6a. The conductive layer6bcontains, for example, tungsten (W). The conductive layer6bcorresponds to the word line WL.

A memory cell MC is provided in each of portions of the memory pillar H1facing the conductive layer6b. A plurality of memory cells MC provided in one memory pillar H1are provided in one memory string MS. Each memory cell MC includes a memory cell transistor MT.

InFIG.3, one memory string MS of the memory strings MS shown inFIG.2is shown. The semiconductor memory device100includes a plurality of memory pillars H1, a plurality of memory cells MC being provided in each of the memory pillars H1.

In addition, a common source line CSL (not shown), a source select gate line SGS (not shown), and a plurality of source select transistors STS (not shown) are provided between the stacked film S2and the substrate11.

In addition, a plurality of drain select gate lines SGD (not shown), a plurality of bit lines BL (not shown), and a plurality of drain select transistors STD (not shown) are provided on the stacked film S2.

FIGS.4to7are schematic cross-sectional views showing the method for manufacturing a semiconductor memory device100according to the present embodiment.

The common source line CSL (not shown), the source select gate line SGS (not shown), and the plurality of source select transistors STS (not shown) are formed on the substrate11.

Next, the plurality of first layers15containing silicon and the plurality of second layers13containing silicon nitride are formed by alternately stacking the first layers15and the second layers13one layer at a time in the Z direction, by a plasma-enhanced chemical vapor deposition (plasma CVD) method for example. As a result, the stacked film S1is formed. Here, the plurality of first layers15contain silicon as a main component and are, for example, amorphous silicon layers. In other words, the plurality of first layers15each contain, for example, amorphous silicon.

Next, as shown inFIG.4, an opening H2that penetrates the stacked film S1in the Z direction and that extends in the Z direction is formed by, for example, a reactive ion etching (RIE) method.

Next, as shown inFIG.5, a part of each of the plurality of first layers15exposed in the opening H2is removed by wet etching using an etchant including hydrofluoric acid. A recessed portion15ais formed at each of the end portions of the plurality of first layers15exposed to the opening H2.

Next, as shown inFIG.6, a first silicon oxide layer14is formed between each of the sets of adjacent ones of the second layers13by oxidizing the plurality of first layers15. Due to the oxidation, the plurality of first silicon oxide layers14expand with respect to both the XY plane and the Z direction as compared with the plurality of first layers15.

A length of any of the second layers13between any adjacent two of the plurality of openings H2in the plane (XY plane) intersecting perpendicularly to the first direction is desirably 1.15 times or more and 1.35 times or less than a length of any of the first layers15between the respective adjacent two of the plurality of openings H2in the plane intersecting perpendicularly to the first direction.

The oxidation of the plurality of first layers15is preferably wet oxidation (for example, H2O annealing) under high pressure conditions. Here, the wet oxidation is performed, for example, by using a hydrogen gas and an oxygen gas and supplying water vapor (H2O) generated by a combustion reaction of the hydrogen gas and the oxygen gas into a reaction chamber in which the semiconductor memory device100is manufactured.

A partial pressure of water vapor (H2O) in the reaction chamber is preferably higher than the atmospheric pressure, and 25 atmospheres or less. The partial pressure of water vapor (H2O) in the reaction chamber is even more preferably 5 atmospheres or more and 25 atmospheres or less. The partial pressure of water vapor (H2O) in the reaction chamber is even more preferably yet 20 atmospheres or more and 25 atmospheres or less.

A time interval during which the wet oxidation is performed is preferably 10 minutes or longer and 1 hour or shorter. A temperature at which the wet oxidation is performed is preferably 750° C. or higher and 1000° C. or lower.

The film density of each of the plurality of first silicon oxide layers14formed by wet oxidation is preferably 2.3 g/cm3or more.

The film thickness of each of the plurality of first silicon oxide layers14formed by wet oxidation in the Z direction is preferably 10 nm or more.

Next, as shown inFIG.7, the insulating film5a, the charge storage film4, the tunnel insulating film3, and a part of the channel semiconductor layer2are formed in the opening H2in this order by, for example, an atomic layer deposition (ALD) method. Next, the insulating film5a, the charge storage film4, the tunnel insulating film3, and a part of the channel semiconductor layer2are removed from the bottom of the opening H2by, for example, etching. Next, the remainder of the channel semiconductor layer2and the core insulating film1are formed in the opening H2in this order by, for example, an atomic layer deposition (ALD) method. As a result, the insulating film5a, the charge storage film4, the tunnel insulating film3, the channel semiconductor layer2, and the core insulating film1are formed in the opening H2in this order.

Next, a slit (not shown) is formed in the stacked film S1. Next, a chemical solution such as phosphoric acid is supplied using such a slit, and a plurality of second layers13are removed. Next, the insulating film5b, the barrier metal layer6a, and the conductive layer6bare formed in this order on the portion from which the plurality of second layers13are removed. As a result, the stacked film S2is formed.

In addition, a plurality of drain select gate lines SGD (not shown), a plurality of bit lines BL (not shown), and a plurality of drain select transistors STD (not shown) are formed on the stacked film S2. As a result, the semiconductor memory device100of the present embodiment is manufactured.

Next, the operation and effect of the semiconductor memory device100of the present embodiment will be described.

In the semiconductor memory device100of the present embodiment, the insulating layer provided between each of conductive layers6bis required to have high breakdown voltage. For example, when an insulating film having a high breakdown voltage is formed, the size of the semiconductor memory device100is reduced by thinning of the insulating layer. In addition, when an insulating film having a high breakdown voltage is formed, since dielectric breakdown is less likely to occur, a semiconductor memory device100having high reliability is manufactured.

As a comparative example, a silicon oxide layer formed by a plasma-enhanced chemical vapor deposition (plasma CVD) method is used as an insulating layer provided between each of the conductive layers6b. However, the silicon oxide layer formed by the plasma CVD method has a low film quality, and thus it is difficult to achieve sufficient breakdown voltage.

Therefore, a semiconductor memory device100of the present embodiment includes a stacked film in which a plurality of first silicon oxide layers having a film density of 2.3 g/cm3or more and a plurality of conductive layers are alternately stacked one layer at a time in a first direction, and includes a memory pillar that penetrates the stacked film in the first direction in which a plurality of memory cells is provided.

By using the plurality of first silicon oxide layers14having the film density of 2.3 g/cm3or more as the insulating layer, the film quality of the insulating layer is improved. As a result, an insulating layer such as a silicon oxide layer formed by a thermal oxidation method is formed, which is a good insulating layer. Therefore, a semiconductor memory device100having high reliability is manufactured.

The film thickness of the plurality of each of the first silicon oxide layers14in the Z direction is preferably 10 nm or more. This is to maintain sufficient insulation between the adjacent conductive layers6b.

The hydrogen concentration of each of the plurality of first silicon oxide layers14is preferably 1×1020atoms/cm3or less. A layer having a low hydrogen concentration can be formed by the plurality of first silicon oxide layers14formed by the above-described manufacturing method.

A method for manufacturing a semiconductor memory device100of the present embodiment includes forming a stacked film in which a plurality of first layers containing silicon and a plurality of second layers containing silicon nitride are alternately stacked in a first direction, forming an opening that penetrates the stacked film and extends in the first direction, and forming a plurality of first silicon oxide layers between each of the plurality of second layers by oxidizing the plurality of first layers.

By forming a plurality of first layers15containing silicon and then oxidizing the plurality of first layers15, an insulating film having a high breakdown voltage is formed.

The oxidation of the plurality of first layers15containing silicon as described above can be performed by wet oxidation. In this wet oxidation, it is preferable to use water vapor (H2O) generated by a combustion reaction of hydrogen gas and oxygen gas in order to form a high-quality film.

When the wet oxidation is performed, the partial pressure of the water vapor (H2O) in the reaction chamber in which the semiconductor memory device100is manufactured is preferably higher than the atmospheric pressure and 25 atmospheres or less. By using such a water vapor having a high-partial pressure, the plurality of first layers15containing silicon is oxidized and the plurality of first silicon oxide layers14is formed. The partial pressure of the water vapor (H2O) in the reaction chamber is even more preferably 5 atmospheres or more and 25 atmospheres or less, in order to form a plurality of first silicon oxide layers14having a higher quality. In addition, the partial pressure of the water vapor (H2O) in the reaction chamber is even more preferably yet 20 atmospheres or more and 25 atmospheres or less, in order to form a plurality of first silicon oxide layers14having a higher quality yet.

A time interval during which the wet oxidation is performed is preferably 10 minutes or longer and 1 hour or shorter. When the wet oxidation is performed for a time shorter than 10 minutes, it is not possible to sufficiently oxidize the plurality of first layers15containing silicon. In addition, when the wet oxidation is performed for a time longer than 1 hour, the time is too long, and thus the productivity of the semiconductor memory device100is reduced.

After the opening H2is formed, it is preferable to remove a part of each of the plurality of first layers15exposed in the opening H2before the oxidation of the plurality of first layers15is performed. Since the plurality of first layers15expand in the XY plane and the Z direction due to oxidation, the plurality of first layers15protrude into the opening H2. This protruding portion may hinder the formation of the film contained in the memory pillar H1. Therefore, before oxidizing the plurality of first layers15, a part of each of the plurality of first layers15is removed to an extent that it does not hinder the formation of the film contained in the memory pillar H1. This includes removing from each of the plurality of first layers15, parts that are exposed to any of a plurality of openings H2(thus removing parts on both sides of the first layers15in the X direction).

In addition, a length of any of the second layers13between any adjacent two of the plurality of openings H2in the plane (XY plane) intersecting perpendicularly to the first direction is desirably 1.15 times or more and 1.35 times or less than a length of any of the first layers15between the respective adjacent two of the plurality of openings H2in the plane intersecting perpendicularly to the first direction. This is to ensure that the side surface of the opening H2becomes sufficiently smooth in the Z direction to an extent that it does not hinder the formation of the memory pillar H1due to the expansion caused by the oxidation of the plurality of first layers15.

According to the semiconductor memory device100of the present embodiment, it is possible to provide a highly integrated semiconductor memory device100.

Second Embodiment

The semiconductor memory device100of the present embodiment is different from the semiconductor memory device100of the first embodiment in that the semiconductor memory device100of the present embodiment further includes a plurality of third layers provided between each of the plurality of conductive layers and the memory pillar that contain silicon oxynitride. Here, description of content that overlaps with the first embodiment will be omitted.

FIG.8is a schematic cross-sectional view of a main part of the semiconductor memory device100according to the present embodiment. The third layers16are provided between each of the conductive layers6band the memory pillar H1. The third layer16contains silicon oxynitride.

FIG.9is a schematic cross-sectional view showing the method for manufacturing a semiconductor memory device100according to the present embodiment. By oxidizing the plurality of first layers15, the plurality of third layers16each containing silicon oxynitride are formed between each of the second layers13and the opening H2when the plurality of first silicon oxide layers14. The plurality of third layers16are formed by oxidizing the portions of the second layer13exposed in the opening H2.

The semiconductor memory device100of the present embodiment provides a highly integrated semiconductor memory device100.