Distortion reduction circuit

An apparatus includes a sampling circuit, a sense circuit, and a tuning circuit. The sampling circuit samples an input signal according to a sampling clock signal to produce a sampled signal. The sense circuit determines a scaling factor based on a distortion in the sampled signal caused by the sampling clock signal. The tuning circuit generates an offset signal based on the sampling clock signal and the scaling factor. The offset signal reduces the distortion in the sampled signal caused by the sampling clock signal.

BACKGROUND

The present disclosure relates to digital signal processing (DSP), and more specifically, to reducing distortions in sampled signals. In digital signal processing, generating high-fidelity waveforms is often accomplished using devices such as a high-speed digital-to-analog converter (DAC). The fidelity of a DAC-based waveform is determined by several metrics (e.g., spurious free dynamic range (SFDR), signal to noise ratio (SNR), signal to noise and distortion (SINAD), and total harmonic distortion (THD)), each measuring different spectral relationships of the output waveform. The general strategy for designing a DAC-based waveform generator includes choosing an ideal sampling frequency for the application. This sampling frequency influences the fidelity of the output waveform for some applications.

The typical practice for selecting a sampling frequency is to select a frequency outside the desired output frequency bandwidth. This practice allows the designer to apply a low pass filter (LPF) on the output of the DAC to remove the distortion (e.g., undesired spectral content) that may be introduced by the sampling frequency. However, one or more problems may arise when the desired output frequency bandwidth is large or wide. For example, the standard practice of using an LPF on a wideband radio frequency application may affect output waveform fidelity if the sampling frequency cannot be placed with enough margin from the designed output frequency bandwidth. Additionally, the standard practices and solutions above may not be ideal in certain applications (e.g., low temperature applications, quantum computing, and high bandwidth analog design).

SUMMARY

According to an embodiment, an apparatus includes a sampling circuit, a sense circuit, and a tuning circuit. The sampling circuit samples an input signal according to a sampling clock signal to produce a sampled signal. The sense circuit determines a scaling factor based on a distortion in the sampled signal caused by the sampling clock signal. The tuning circuit generates an offset signal based on the sampling clock signal and the scaling factor. The offset signal reduces the distortion in the sampled signal caused by the sampling clock signal. Other embodiments include a method performed by the apparatus.

According to another embodiment, an apparatus includes a sense circuit and a tuning circuit. The sense circuit determines a scaling factor based on a distortion in a sampled signal caused by a sampling clock signal used to generate the sampled signal. The tuning circuit generates an offset signal based on the sampling clock signal and the scaling factor. The offset signal reduces the distortion in the sampled signal caused by the sampling clock signal. Other embodiments include a method performed by the apparatus.

DETAILED DESCRIPTION

This disclosure describes a system that reduces distortions in sampled signals using a feedback loop. Specifically, the system includes a sense circuit and a tuning circuit that operate together to offset or reduce distortions in a sampled signal caused by a sampling clock signal. The sense circuit analyzes the sampled signal to determine a scaling factor for offsetting the distortion. The tuning circuit then uses the scaling factor to generate an offset signal. For example, the tuning circuit may apply the scaling factor to a phase shifted version of the sampling clock signal. As another example, the tuning circuit may apply the scaling factor to an oscillating signal generated according to the sampling clock signal. The system then applies the offset signal to a sampled signal (e.g., using a mixer) to reduce the distortion in the sampled signal, in certain embodiments. In some embodiments, the system is a circuit designed on a digital-to-analog converter (DAC) chip (e.g., on the same silicon as the DAC) that utilizes a feedback loop architecture to create an amplitude-tuned and phase-shifted sampling clock to achieve compensatory sampling content cancellation.

FIG.1illustrates an example system100. As seen inFIG.1, the system100includes a sampling circuit102, a sense circuit104, a tuning circuit106, and a mixer108. Generally, the sampling circuit102samples an input signal according to a sampling clock signal. The sense circuit104and the tuning circuit106operate together to generate an offset signal based on the sampled signal and the sampling clock signal. The offset signal is then combined with the sampled signal to reduce or offset a distortion caused by the sampling clock signal, in certain embodiments. This offset or cancellation routine may be performed during startup or when temperature or other effects (e.g., voltage drift) are detected. In some embodiments, the system100is an integrated circuit or the components of the system100are implemented on the same piece of semiconductor (e.g., silicon).

The sampling circuit102is a circuit (e.g., a DAC) that samples an input signal to the system100according to a sampling clock signal provided to the system100. For example, the sampling circuit102may sample a value of the input signal at the zero crossings of the sampling clock signal or when the sampling clock signal periodically reaches a certain value. The sampled signal may include distortions caused by the sampling clock signal. For example, the sampled signal may include distortions at the frequency of the sampling clock signal. Other components of the system100may analyze the sampled signal to generate an offset signal that reduces or offsets the distortion caused by the sampling clock signal.

The sense circuit104and the tuning circuit106form a feedback loop that provides an offset signal to the sampled signal. The mixer108combines the sampled signal with the offset signal to generate an output signal. Prior to the sense circuit104and the tuning circuit106providing the offset signal to the mixer108, the output signal from the mixer108is mainly the sampled signal. The sense circuit104analyzes the sampled signal to determine a scaling factor. For example, the sense circuit104may detect or measure the power of the sampled signal at the frequency of the sampling clock signal (e.g., using circuitry that measures the power level of the peak amplitude at the frequency of the sampling clock signal). The sense circuit104then uses the measured power to produce a scaling factor that may be used to offset the distortion caused by the sampling clock signal. In some embodiments, the scaling factor is the multiplicative inverse of the measured power of the sampled signal at the frequency of the sampling clock signal. The sense circuit104communicates the scaling factor to the tuning circuit106.

The tuning circuit106generates the offset signal using the sampling clock signal and the scaling factor. In some embodiments, the tuning circuit106shifts the sampling clock signal and then applies the scaling factor directly to the shifted clock signal to produce the offset signal. In other embodiments, the tuning circuit106includes a numerically controlled oscillator or a phase locked loop that generates an oscillating signal based on the sampling clock signal. The tuning circuit106then applies the scaling factor directly to the oscillating signal to generate the offset signal. The tuning circuit106communicates the offset signal to the mixer108.

The mixer108combines the offset signal with the sampled signal to update the output signal (e.g., to destructively interfere with the distortion caused by the sampling clock signal). In some embodiments, the mixer108adds the offset signal to the sampled signal or subtracts the offset signal from the sampled signal to update the output signal. In other embodiments, the mixer108multiplies the sampled signal with the offset signal (e.g., through a convolution) or divides the sampled signal by the offset signal to update the output signal. By combining the sampled signal and the offset signal, the mixer108reduces or offsets the distortion in the sampled signal caused by the sampling clock signal. As a result, the mixer108may remove the distortion from the output signal. In some embodiments, the system100uses a circuit other than the mixer108(e.g., an adder) to combine the sampled signal with the offset signal.

In certain embodiments, a user may provide one or more of signals to the system100. For example, the user may provide the input signal and the sampling clock signal to the system100. As another example, the user may provide a cancellation signal that the system100uses to generate the offset signal. In this manner, the user has control over the offset signal and the destructive interference provided by the system100.

FIG.2illustrates an example tuning circuit106in the system100ofFIG.1. As seen inFIG.2, the tuning circuit106includes a delay element202and a variable attenuator204. Generally, the delay element202and the variable attenuator204operate together to produce an offset signal based on a received scaling factor and a received sampling clock signal.

The delay element202operates as a phase shifter in the tuning circuit106. The delay element202receives the sampling clock signal and phase shifts the sampling clock signal by introducing delay into the sampling clock signal. In some embodiments, the delay element202introduces a 180 degrees phase shift to the sampling clock signal. After adding the phase shift, the delay element202produces a shifted sampling clock signal. The delay element202communicates the shifted sampling clock signal to the variable attenuator204.

The variable attenuator204receives the scaling factor from the sense circuit104(shown inFIG.1) and the shifted sampling clock signal from the delay element202. The variable attenuator204then applies the scaling factor to the shifted sampling clock signal. For example, the variable attenuator204may multiply the shifted sampling clock signal by the scaling factor to produce the offset signal. As a result, the offset signal is a scaled and phase shifted version of the sampling clock signal. The offset signal may then be combined with a sampled signal to remove a distortion at the frequency of the sampling clock signal.

FIG.3illustrates an example tuning circuit106in the system100ofFIG.1. As seen inFIG.3, the tuning circuit106includes a clock divider302and a numerically controlled oscillator304. Generally, the clock divider302and the numerically controlled oscillator304operate together to produce the offset signal based on a received sampling clock signal and a received scaling factor. The embodiment of the tuning circuit106shown inFIG.3is an alternative to the embodiment shown inFIG.2.

The clock divider302receives the sampling clock signal and divides the sampling clock signal to produce a divided sampling clock signal. For example, the clock divider302may reduce the frequency of the sampling clock signal by producing a divided sampling clock signal with a frequency that is half, a quarter, or any suitable fraction of the frequency of the sampling clock signal. The clock divider302communicates the divided sampling clock signal to the numerically controlled oscillator304.

The numerically controlled oscillator304uses the divided sampling clock signal to generate an oscillating signal. For example, the frequency of the divided sampling clock signal may instruct the numerically controlled oscillator304to generate an oscillating signal with a particular frequency. In some embodiments, the numerically controlled oscillator adjusts the phase of the divided sampling clock signal before using the divided sampling clock signal to generate the oscillating signal. The numerically controlled oscillator304also receives the scaling factor from the sense circuit104. The numerically controlled oscillator304applies the scaling factor directly to the oscillating signal to produce the offset signal. For example, the numerically controlled oscillator304may multiply the oscillating signal by the scaling factor to produce the offset signal. The offset signal is then combined with a sampled signal to reduce or offset a distortion caused by the sampling clock signal.

In some embodiments, the numerically controlled oscillator304allows the tuning circuit106to generate an offset signal that reduces or offsets distortions at any frequency, including the frequency of the sampling clock signal. By using the numerically controlled oscillator304, the tuning circuit106can generate an offset signal that destructively interferes with signals of any suitable frequency.

FIG.4illustrates an example portion of the system100ofFIG.1. As seen inFIG.4, the portion of the system100includes the sampling circuit102, a mixer108, the variable attenuator204, and a Wilkinson power divider402. The Wilkinson power divider402receives and splits the sampling clock signal. The Wilkinson power divider402communicates the sampling clock signal to the sampling circuit102and to the variable attenuator204. The sampling circuit102then samples an input signal according to the sampling clock signal from the Wilkinson power divider402to produce the sampled signal. The sampling circuit102communicates the sampled signal to a radio frequency (RF) port on the mixer108.

The variable attenuator204receives the sampling clock signal from the Wilkinson Power Divider402and applies a scaling factor to the sampling clock signal to produce the offset signal. The variable attenuator204communicates the offset signal to the local oscillator (LO) port on the mixer108. In some embodiments, a delay element202is positioned between the Wilkinson power divider402and the variable attenuator204. The delay element202adds a phase shift to the sampling clock signal before the variable attenuator204scales the sampling clock signal. As a result, the offset signal from the variable attenuator204is a scaled and phase shifted version of the sampling clock signal.

The mixer108combines the sampled signal with the offset signal to produce the output signal over an intermediate frequency (IF) port (e.g., port IF2in the example ofFIG.4). In some embodiments, the mixer108multiplies the sampled signal by the offset signal. In some embodiments, a resistor (e.g., a 50 ohm termination404in the example ofFIG.4) is connected to another IF port of the mixer108(e.g., port IF1in the example ofFIG.4). By combining the sampled signal and the offset signal, the mixer108reduces a distortion in the sampled signal caused by the sampling clock signal.

FIG.5illustrates an example system500. As seen inFIG.5, the system500includes a cancellation circuit502and one or more sampling circuits (e.g., DACs504,506and508). Generally, the cancellation circuit502may include one or more components of the system100that operate together to generate offset signals. The cancellation circuit502generates an offset signal used by the DACs504,506and508to reduce or offset distortions caused by a sampling clock signal. As a result, the DACs504,506and508may sample different input signals according to a sampling clock signal to produce sampled signals. The sampled signals are then combined with the offset signal produced by the cancellation circuit502to produce output signals. Distortions in the sampled signals at the frequency of the sampling clock signal may be reduced or offset by the offset signal from the cancellation circuit502. The example ofFIG.5shows that the components and functions described with respect to the system100inFIG.1may be applied to more than one sampling circuit (e.g., DAC) simultaneously to produce multiple output signals.

In certain embodiments where an analog signal is being provided by an external source, there may be many ways to ensure timing. For example, a scope limited application may be used so that on-chip timing analysis lines up with a frequency range. As another example, phase delay circuitry may be used to add a tunable phase delay. During a calibration routine, a user could adjust the delay to the signal to achieve the desired result. As another example, delay may be shifted at the source. In the case of an on-chip offset signal, the phase shift can be performed in a more automated fashion (e.g., using a numerically controlled oscillator or a phase locked loop).

FIGS.6A and6Billustrate an example operation of the system100ofFIG.1. Various components of the system100shown inFIG.1may perform the process shown inFIGS.6A and6B. As seen inFIG.6A, the process begins with the sampling circuit102sampling an input signal according to a sampling clock signal to produce a sampled signal. The sampled signal includes a sampled portion indicated by the triangular region604in the graph602and a distortion indicated by an arrow606on the right side of the graph602. Notably, the distortion is introduced by the sampling clock signal and has the same frequency as the sampling clock signal. After the sampling circuit102provides the sampled signal, the tuning circuit106produces a shifted sampling clock signal or oscillating signal. For example, the tuning circuit106may add a phase shift to the sampling clock signal to produce a shifted sampling clock signal, or the tuning circuit106may include a numerically controlled oscillator that generates an oscillating signal based on the sampling clock signal. As seen inFIG.6A, the shifted sampling clock signal or the oscillating signal have the same frequency as the distortion (as indicated by the arrow610in the graph608). However, the shifted sampling clock signal or the oscillating signal is out of phase with the distortion.

The process continues inFIG.6Bwith the tuning circuit106applying a scaling factor to the shifted sampling clock signal or the oscillating signal to produce a scaled signal (represented by the arrow614in the graph612). For example, the tuning circuit106may receive a scaling factor from the sense circuit104. The sense circuit104may have determined the scaling factor by determining the power of the sampled signal at the frequency of the sampling clock signal. By applying the scaling factor to the shifted sampling clock signal or the oscillating signal, the tuning circuit106produces the scaled signal, which has a magnitude near or similar to the magnitude of the distortion.

The scaled signal is then combined with the sampled signal to produce the output signal (represented by the graph616). As seen inFIG.6B, the scaled signal reduces or offsets the distortion when combined with the sampled signal. In some embodiments, the scaled signal offsets the distortion such that the output signal does not include the distortion. In some embodiments, a mixer108combines the scaled signal with the sampled signal to reduce or offset the distortion.

FIG.7is a flowchart of an example method700performed in the system100ofFIG.1. In particular embodiments, various components of the system100perform the method700. By performing the method700, the system100uses a feedback loop to reduce or offset the distortion in a sampled signal caused by a sampling clock signal.

In block702, a sampling circuit102samples an input signal according to a sampling clock signal. For example, the sampling circuit102may be a DAC that samples the value of the input signal at the zero crossings of the sampling clock signal. The sampled signal produced by the sampling circuit102may include a distortion at the frequency of the sampling clock signal.

In block704, a sense circuit104determines a scaling factor based on the distortion caused by the sampling clock signal. For example, the sense circuit104may analyze the sampled signal from the sampling circuit102to measure a power of the sampled signal at the frequency of the sampling clock signal. This power may be the power of the distortion introduced by the sampling clock signal. The sampling circuit then produces the scaling factor based on this measured power. For example, the scaling factor may be the multiplicative inverse of the measured power.

In block706, a tuning circuit106generates an offset signal, based on the sampling clock signal and the scaling factor. In some embodiments, the tuning circuit106includes a delay element202and a variable attenuator204. The delay element202adds a phase shift to the sampling clock signal, and the variable attenuator204applies the scaling factor to the shifted sampling clock signal (e.g., multiplying the shifted sampling clock signal by the scaling factor) to produce the offset signal. In some embodiments, the tuning circuit106includes a clock divider302and a numerically controlled oscillator304. The clock divider302produces a divided sampling clock signal with a reduced frequency relative to the sampling clock signal. The numerically controlled oscillator304generates an oscillating signal according to the divided sampling clock signal and applies the scaling factor directly to the oscillating signal (e.g., multiplies the oscillating signal by the scaling factor) to generate the offset signal.

In block708, a mixer108applies the offset signal to the sampled signal to reduce the distortion. The mixer108may combine the sampled signal with the offset signal (e.g., through adding, subtracting, multiplying, or dividing the signals). In particular embodiments, combining the sampled signal with the offset signal reduces or offsets the distortion in the sampled signal caused by the sampling clock signal.

In summary, a system100reduces distortions in sampled signals using a feedback loop. Specifically, the system100includes a sense circuit104and a tuning circuit106that operate together to offset or reduce distortions in a sampled signal caused by a sampling clock signal. The sense circuit104analyzes the sampled signal to determine a scaling factor for offsetting the distortion. The tuning circuit106then uses the scaling factor to generate an offset signal. For example, the tuning circuit106may apply the scaling factor to a phase shifted version of the sampling clock signal. As another example, the tuning circuit106may apply the scaling factor to an oscillating signal generated according to the sampling clock signal. The system100then applies the offset signal to a sampled signal (e.g., using a mixer108) to reduce the distortion in the sampled signal, in certain embodiments.