WAFER AND CHIP THEREOF

A wafer includes chips, a scribe lane, a metal layer and an inhibitor made of a nonconductive material. The metal layer is provided on the scribe lane and the chip located next to the scribe lane. The inhibitor covers the scribe lane and the chip next to the scribe line and includes a first removed part and an inhibition part which are located above a second removed part and a residual part of the metal layer, respectively. The scribe lane, the first and second removed parts are removed, and the inhibition part and the residual part are retained on each of the chips after a wafer cutting process. The inhibitor is provided to prevent the residual part of the metal layer from being lifted up or generating a metal burr during the wafer cutting process.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to R.O.C Patent Application No. 112127821 filed Jul. 25, 2023, the disclosure of which is hereby incorporated by reference in its entirety.

FIELD OF THE INVENTION

This invention relates to a wafer and a chip thereof, and more particularly to a wafer and a chip able to prevent a metal layer from being lifted up or generating a metal burr during a wafer cutting process.

BACKGROUND OF THE INVENTION

With reference toFIGS.1to3, a conventional wafer10includes chips11, scribe lanes12and at least one metal layer13. Each of the scribe lanes12is located between the adjacent chips11, and the metal layer13which may be test pad(s), mark(s) or circuit line(s) is located on the scribe lanes12and extended to the chips11located next to the scribe lanes12.

The wafer10is cut along the scribe lanes12to separate the chips11in a cutting process, but a part13aof the metal layer13may be remained on the chips11. The metal layer13has ductility so the residual part13amay be lifted up or generate a metal burr13b.

Referring toFIG.3, while a lead21on a circuit board is bonded to a bump14of the chip11, the lead21may contact the residual part13awhich is lifted up or contact the metal burr13bto bring short circuit or electrical error problem to the chips11and the circuit board.

SUMMARY OF THE INVENTION

One object of the present invention is to provide a wafer and a chip of the wafer which includes an inhibitor covering a scribe lane and a chip located next to the scribe lane. The inhibitor is provided to improve tensile strength of a metal layer located on the scribe lane and the chip so as to prevent a residual part of the metal layer generated after cutting from being lifted up or generating a metal burr.

A wafer of the present invention includes chips, a scribe lane located between the adjacent chips, a metal layer and an inhibitor. The metal layer is provided on the scribe lane and extended to be on the chip which is located next to the scribe lane, and the metal layer includes a second removed part and a residual part. The inhibitor which is made of a nonconductive material covers the scribe lane and the chip next to the scribe lane and includes a first removed part located above the second removed part of the metal layer and an inhibition part located above the residual part of the metal layer. After a cutting process of the wafer, the scribe lane, the first and second removed parts located on the scribe lane are removed, and the inhibition part and the residual part are still located on the chip.

A chip of the present invention includes a residual part and an inhibition part which is located above the residual part and made of a nonconductive material. The inhibition part includes a first cut surface and a first side wall which are opposite to each other, the first cut surface is visible from a side wall of the chip. The inhibition part is retained on an active surface of the chip after removing a first removed part of an inhibitor. The residual part includes a second cut surface and a second side wall which are opposite to each other, the second cut surface is visible from the side wall of the chip. The residual part is retained on the chip after removing a second removed part of a metal layer.

The inhibitor covering the scribe lane and the chip located next to the scribe lane is provided to increase tensile strength of the metal layer. Because of the inhibitor, the residual part of the metal layer, which is retained on the chip, will not be lifted up or generate a metal burr during removing the scribe lane, the first and second removed parts located on the scribe lane. In addition, the inhibition part retained on the chip can support a lead of a circuit board (not shown) bonded to the chip to prevent the lead from contacting the first cut surface of the inhibition part and/or the second cut surface of the residual part to cause short circuit or electrical abnormality.

DETAILED DESCRIPTION OF THE INVENTION

With reference toFIGS.4to6, a wafer100in accordance with one embodiment of the present invention includes chips110, at least one scribe lane120located between the adjacent chips110, a metal layer130and at least one inhibitor140which is made of a nonconductive material, e.g. polymeric material or other nonconductive material. Each of the chips110includes a protective layer111, at least one conductive pad112, a seal ring113surrounding the conductive pad112and at least one bump114. An active surface110aof each of the chips110is the surface of the protective layer111, the protective layer111covers the seal ring113but not cover the conductive pad112which is located on a bump arrangement area110bdefined on the active surface110a, and the bump140is electrically connected to the conductive pad112.

With reference toFIGS.5and6, the metal layer130is provided on the scribe lane120and extended to be on the chip110located next to the scribe lane120. The metal layer130may be a test pad or mark as shown inFIG.5, and it may be a circuit line as shown inFIG.6. The metal layer130includes a second removed part131located on the scribe lane120and a residual part132located on the chip110and covered by the protective layer111. Referring toFIG.5, the second removed part131of the metal layer130which is the test pad or mark is not covered by the protective layer111, and referring toFIG.6, the second removed part131of the metal layer130which is the circuit line is covered by the protective layer111.

With reference toFIGS.4to6, the inhibitor140covers the scribe lane120and the chip110located next to the scribe lane120. Preferably, the wafer100includes a plurality of inhibitors140as shown inFIG.4, and there is an opening143which is located between the adjacent inhibitors140and communicates with the bump arrangement area110bdefined on the active surface110aof the chip110. An underfill (not shown) can flow to the bump arrangement area110bvia the opening143to seal the bump114and a lead (not shown) bonded to the bump114. Along the direction of an axis line X extending from the bump arrangement area110btoward the inhibitor140, a first width W1 of the scribe lane120is less than a second width W2 of the metal layer130, and the second width W2 of the metal layer130is less than a third width W3 of the inhibitor140. Along the direction perpendicular to the axis line X, the inhibitor140is designed to have a length L greater than or equal to 60 μm in order to improve the adhesive strength of the inhibitor140to the wafer100.

With reference toFIGS.5and6, the inhibitor140includes a first removed part141and an inhibition part142, the first removed part141is located above the second removed part131of the metal layer130and the inhibition part142is located above the residual part132of the metal layer130. While the metal layer130is the test pad or mark as shown inFIG.5, the first removed part141of the inhibitor140covers the second removed part131of the metal layer130. If the metal layer130is the circuit line as shown inFIG.6, the first removed part141of the inhibitor140covers the protective layer111, and the protective layer111covers the second removed part131of the metal layer130. The protective layer111is covered by the inhibitor140and located between the inhibition part142of the inhibitor140and the residual part132of the metal layer130.

With reference toFIGS.5and6, a first height H1 of the inhibition part142of the inhibitor140is higher than a second height H2 of the protective layer111such that the inhibition part142can increase flexural strength of the protective layer111. A third height H3 of the bump114protruding from the protective layer111is not less than the first height H1 of the inhibition part142, and preferably, the third height H3 is higher than the first height H1, and the difference between the third height H3 and the first height H1 is less than or equal to 7 μm.

With reference toFIGS.5and6, the inhibition part142of the inhibitor140has a first side wall142aclose to the seal ring113, and the residual part132of the metal layer130has a second side wall132aclose to the seal ring113. A first distance D1 between a first imaginary line S1 extending from the first side wall142aand a second imaginary line S2 extending from the second side wall132ais greater than or equal to 5 μm, and a second distance D2 between the seal ring113and the first imaginary line S1 is greater than or equal to 1 μm.

With reference toFIGS.5to8, a cutting tool (not shown) is used to cut the wafer100into the chips110along the scribe lane120during a cutting process, as a result, each of the chips110has a side wall110c. Referring toFIGS.7and8, during the wafer cutting process, the scribe lane120, the first removed part141and the second removed part131located on the scribe lane120are removed by the cutting tool, and the inhibition part142and the residual part132are retained on the chip110. The inhibition part142covers the protective layer111and has a first cut surface142bwhich is opposite to the first side wall142aand exposed on the side wall110cof the chip110. The residual part132has a second cut surface132bwhich is opposite to the second side wall132aand exposed on the side wall110cof the chip110. The first cut surface142bof the inhibition part142and the second cut surface132bof the residual part132are flush with the side wall110cof the chip110. Preferably, each of the chips110includes multiple inhibition parts142, and the opening143is located between the adjacent inhibition parts142.

With reference toFIGS.7and8, during the wafer cutting process, the first removed part141is removed and the inhibition part142is retained on the active surface110aof the chip110, thus, the inhibition part142has a length as same as the length L of the inhibitor140. The inhibitor140is provided to cover the scribe lane120and the chip110located next to the scribe lane120to improve tensile strength of the metal layer130and further prevent the residual part132located on the chip110from being lifted up or generating a metal burr. Because the inhibition part142is retained on the chip110and its first height H1 is not higher than the third height H3 of the bump114, the inhibition part142can support a lead210of a circuit board (not shown) bonded to the bump114and prevent the lead210from contacting the first cut surface142bof the inhibition part142and/or the second cut surface132bof the residual part132to cause short circuit or electrical abnormality.

While this invention has been particularly illustrated and described in detail with respect to the preferred embodiments thereof, it will be clearly understood by those skilled in the art that is not limited to the specific features shown and described and various modified and changed in form and details may be made without departing from the scope of the claims.