Gate circuit for bus signal lines

A failure detecting gate circuit for bus signal lines. The gate circuit include gate elements connected to each bus line and controlled by control signal, and a processing unit which controls any one of the gate elements. The processing unit operates to switch the gate elements to an "ON" state when the control signals are supplied to the gate elements of each gate. The failure detecting circuit outputs an indication signal of a failure condition in the processing unit. This occurs when control signals are supplied, such that at least two gate elements are to be switched to the "ON" state simultaneously. The improvement of the present invention over previous devices is a multiplexer which outputs one of two signals indicating either a failure condition or a normal signal provided by the microcontroller.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a gate circuit for bus signal lines used 
upon a LSI (Large Scale Integration) device. More particularly, the 
present invention relates to a gate circuit having a failure detecting 
circuit for making the choice of bus signal lines when a processing unit 
controls the gates of the gate elements. 
2. Description of the Prior Art 
FIG. 5 shows a gate circuit for bus signal lines with a tri-status bus 
circuit which has been broadly used upon a LSI device of a conventional 
microcontroller. 
In the drawing, a gate circuit for bus signal lines includes the tri-status 
gates as gate elements 1-3, bus signal lines 1a-3a, gate signal lines 
1b-3b, functional block of a microcontroller F0-F5 showing Micro Read Only 
Memory F0, Data Path F1, Interrupt Controller F2, Timer F3, Random Access 
Memory F4, and Universal Asynchronous Receiver Transmitter F5 
respectively, inner bus IBUS which mutually connects with F0-F5, and 
control circuits G1-G3. 
Referring to FIG. 5, the gate circuit for bus signal lines includes three 
tri-status gates. 
These tri-status bus circuits supply the control signals C1-C3 to the gates 
of the said tri-status gates through the gate signal lines 1b-3b for 
making the choice of input signals provided through bus signal lines 1a-3a 
and control each of the states of the tri-status bus gates 1-3. 
Then, for example, in the case that the control signals, C1-C3, are 
switched to the "1" state, the tri-status gates 1-3 turn to the "ON" state 
control micro code signal MIC, output from micro ROM F0, is designed not 
to provide two control signals at the same time and also not to turn a 
plurality of the tri-status gates 1-3 to the "ON" state. FIG. 6 shows an 
example of a PLA circuit consisting of control circuits G1-G3 as shown in 
FIG. 5. These circuits decode micro code signal MIC from micro ROM F0 and 
thereby output control signals C1-C3. 
The above mentioned tri-status bus circuit does not include any detecting 
circuit for each of the tri-status gates 1-3. Any failure occurring in 
control circuits G1-G3 etc. provide error control signals C1-C3 to gate 
signal lines 1b-3c. Even when a plurality of tri-status gates 1-3 have 
turned to the "ON" state simultaneously, any failure that has not been 
detected, causes the problem that the reliability of data to be output to 
inner bus IBUS is decreased. 
SUMMARY OF THE INVENTION 
The primary object of the present invention is to provide a failure 
detecting gate circuit wherein the elements of each gate, for example, a 
tri-status gate, are under the control of the control signals. 
Another object of the present invention is to provide a failure detecting 
circuit composed of a simple circuit though the number of gate signal 
lines which control the gate of the gate elements may be increased. 
For the accomplishment of the above mentioned objects of the present 
invention, there is included a failure detecting circuit providing an 
output signal which indicates a failure when a plurality of the tri-status 
gates turn into "ON" state at the same time. 
The above and other objects, features, and advantages of the invention will 
become more apparent from the following description when taken in 
conjunction with the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
FIG. 1 shows an embodiment of a microcontroller LSI using the bus signal 
lines of the present invention. 
In the drawing, the same reference numerals designate like parts. The 
reference numeral 4 is a memory composed of ROM as a failure detecting 
circuit, and the ROM is supplied control signals for the address signals 
C1-C3 to the input terminals A1-A3 for the tri-status gates. The ROM 4 as 
illustrated in FIG. 2, reads out its memorized contents at the address 0-7 
in response to the address signals supplied to the input terminals A1-A3. 
When a plurality of the control signal C1-C3 are in the state "1", a 
plurality of the tri-status gates 1-3 go to the "ON" state, and output 
signal CHK indicating failure state "ON" is available to read out. For 
instance, at the time the control signal C1 and C2 on "1" state are 
respectively supplied to the input terminals A1 and A2. Control signal C3 
are in the "0" state, the is supplied to the input terminal A3. The 
memorized content "1" at the sixth address is read out, so any failure in 
the processing unit is detected. Referring to the tri-status bus circuit 
illustrated in FIG. 1, when any failure has occurred on the control signal 
C1-C3 and a plurality of the tri-status gates 1-3 go to the "ON " state, 
output signal CHK "1" appears and a failure on control signals C1-C3 is 
detected. 
According to the above description of the failure detecting circuit, the 
ROM is used in the detecting circuit. Even when the number of gate signal 
lines which gate the gate elements of tri-status gates has been increased, 
only the increase of the capacity of the ROM should be required and a 
simple failure detecting circuit may be obtained. 
While there has been described what is, at present, considered to be a 
preferred embodiment of the present invention, it will be understood that 
the number of the tri-status gates may be available more than three. 
Although in the above mentioned description a ROM is used in a failure 
detecting circuit, it will also be understood that various modifications 
of the circuit may be available without using a ROM. FIG. 3 illustrates an 
example of the embodiment of logic element as a failure detecting circuit. 
In this circuit, when an input signal to either any two of input terminals 
A1-A3 goes to the "ON" state, output signal CHK is output. In short, a 
detecting function will be required to detect the "ON" state of a 
plurality of the tri-status gates caused by control signals C1-C3. 
It is to be understood that in the above mentioned embodiment of the 
present invention, tri-status gates are used as the gate elements. The 
above embodiment is applicable to the other circuit elements, for 
instance, transfer gates, controlling the state of gate elements by 
supplying a control signal to the logic element. And as to an output 
signal, CHK, indicating a failure condition as shown in FIG. 4, both an 
output signal CHK and a normal signal of a microcontroller LSI are 
designed to be input to a multiplex circuit 5. The output of multiplex 
circuit 5 is the CHK signal which issued as a test mode signal, TM, in 
case of H-level signal. In case of L-level signal a normal signal is 
output. Consequently a failure in a LSI device of bus signal lines is to 
be detected without large additional increases in hardware.