Semiconductor device and method for forming the same

A semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a semiconductor device and method for forming the same. More particularly, the present invention relates to a semiconductor device comprising source/drain stressors and method for forming the same.

2. Description of the Prior Art

In advanced semiconductor manufacturing, to boost the carrier mobility, one conventional attempt has been made by forming a strained silicon channel. The strained silicon channel can increase the carrier mobility, thereby improving the operation speed of the semiconductor device. One method for forming a strained silicon channel is forming the source/drain regions as the stressors at two sides of the channel by selective epitaxial growth (SEG). The epitaxial layers of the source/drain regions may have a lattice arrangement different from the lattice constant of the substrate (the channel) by comprising dopants. The mismatch of the lattice constants between the source/drain regions and the substrate may induce a desired type and magnitude of stress to the channel region to improve the drive current.

Raised source/drain (RSD) regions are also proposed to reduce the leakage current between the source/drain regions when the channel is off. Conventionally, a raised source/drain region may be formed by overgrow the epitaxial layer to form a raised portion above the upper surface of the substrate. However, the raised portion tends to grow along the sidewall of the spacer and consequently directly covers a lower sidewall of the spacer. This will adversely cause a higher parasitic capacitance between the source/drain region and the gate.

SUMMARY OF THE INVENTION

In light of the above, the present invention is directed to provide a semiconductor device and method for forming the same which may reduce the parasitic capacitance between the source/drain region and the gate.

According to one embodiment of the present invention, a semiconductor device is disclosed. The semiconductor device comprises a substrate, a gate structure disposed on the substrate, a spacer disposed on the substrate and covering a sidewall of the gate structure, an air gap sandwiched between the spacer and the substrate, and a source/drain region disposed in the substrate and having a faceted surface exposed from the substrate, wherein the faceted surface borders the substrate on a boundary between the air gap and the substrate.

According to another embodiment of the present invention, a method for forming a semiconductor device is disclosed, which comprises the following steps. First, a substrate is provided. Agate structure is formed on the substrate. A shallow doped region is then formed in the substrate adjacent to the gate structure. A spacer is then formed on the shallow doped region in substrate and on a sidewall of the gate structure. Subsequently, an etching process is performed to form a deep recess in the substrate adjacent to the spacer and an air gap between the spacer and the substrate. After that, an epitaxial process is performed to form a source/drain region completely filling the deep recess, wherein an edge of the faceted surface is on a boundary between the air gap and the substrate

It is one feature of the present invention that a narrow air gap is purposely formed between the spacer and the substrate to force the raised portion of the source/drain region to grow along direction away from the spacer. Therefore, the raised portion of the source/drain region will not cover on the spacer, and the parasitic capacitance between the source/drain region and the gate is reduced.

DETAILED DESCRIPTION

To provide a better understanding of the present invention to those of ordinary skill in the art, several exemplary embodiments of the present invention will be detailed as follows, with reference to the accompanying drawings using numbered elements to elaborate the contents and effects to be achieved. The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute a part of this specification. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention.

Please refer toFIG. 1toFIG. 9, which are schematic cross-sectional diagrams illustrating successive steps for forming a semiconductor device according to a preferred embodiment of the present invention. As shown inFIG. 1, a substrate110is provided. The substrate110may comprise a silicon substrate, a silicon-in-insulator (SOI) substrate or other semiconductor substrate, but not limited thereto. A gate structure120is formed on the substrate110. According to an embodiment, the gate structure120may include, from bottom to top, a gate dielectric layer122, a sacrificial gate layer124, a pad layer126and a cap layer128. The gate dielectric layer122may be made of silicon oxide, but not limited thereto. The sacrificial gate layer124may be made of polysilicon, but not limited thereto. The pad layer126may be made of silicon nitride, but not limited thereto. The cap layer128may be made of silicon oxide, but not limited thereto. The gate structure120may be a dummy gate structure which is to define the position of a replacement metal gate structure (shown inFIG. 9). In other embodiments, the gate structure120may be a polysilicon gate and will not be substituted by a metal gate structure.

Subsequently, as shown inFIG. 2, a first spacer132is formed on the substrate110and covering the sidewall of the gate structure120. According to an embodiment, the material of the first spacer132may comprise SiO2, SiN, SiON or SiCN, but not limited thereto. Preferably, the first spacer132comprises SiCN. The first spacer132may be formed by first forming a first spacer material layer conformally covering the substrate110and the top surface and sidewall of the gate structure120, and then performing an anisotropic etching process to remove the first spacer material layer on the substrate110and on the top surface of the gate structure120. The remaining first spacer material layer on the sidewall of the gate structure120becomes the first spacer132.

After forming the first spacer132, as shown inFIG. 3, by using the gate structure120and the first spacer132as an implanting mask, a first implanting process P1is performed to implant amorphizing ions at a first tilt angle into the substrate110to form a shallow doped region134in the substrate110. The shallow doped region134is formed at two sides of the gate structure120and adjacent to the gate structure120. According to an embodiment, the species of the amorphizing ionsmay include silicon (Si), carbon (C), germanium (Ge), phosphorous (P), arsenic (As), or inert gas such as argon (Ar) or xenon (Xe), but not limited thereto. Preferably, the species of the amorphizing ions is Xe. The shallow doped region134is an at least partially amorphized region of the substrate110.

The depth of the shallow doped region134may vary by adjusting the power and tilt angle of the first implanting process P1. According to an embodiment, the amorphizing ions may be implanted into the substrate110in a dosage between 1E12 to 1E14 atoms/cm2and at a tilt angle of about 5 degrees against an axis perpendicular to the upper surface of the substrate110and at an energy of about 1 to 5 keV. Preferably, the shallow doped region134may have a depth D1between 10 to 40 angstroms. According to an embodiment, the shallow doped region134may have an extending portion underlying the first spacer132.

Please refer toFIG. 4. Optionally, also by using the gate structure120and the first spacer132as an implanting mask, a second implanting process P2may be performed to implant conductive dopants into the substrate110to form a lightly-doped region136in the substrate110at two sides of the gate structure120and adjacent to the gate structure120. The species of the conductive dopants is chosen depending on the conductive type of the semiconductor device. For example, when the semiconductor device is n-type, the conductive dopants may include P, As, Sb, or other suitable n-type conductive dopants. On the other hand, when the semiconductor device is p-type, the conductive dopants may include B, BF2, or other suitable p-type conductive dopants.

Similarly, the depth of the lightly-doped region136may vary by adjusting the power and tilt angle of the second implanting process P2. According to an embodiment, preferably, the conductive dopants of the second implanting process P2may be implanted into the substrate110at tilt angle larger than the tilt angle of the amorphizing ions in the first implanting process P1, such as between 7 to 8 degrees against the axis perpendicular to the upper surface of the substrate110, and at an energy larger than the energy of the amorphizing ions in the first implanting process P1, such as between 1 to 30 keV. The depth D2of the lightly-doped region136is deeper than the depth D1of the shallow doped region134. The lightly-doped region136may also as an extending portion, extending laterally farther than the shallow doped region134and underlying the first spacer132and a portion of the gate structure120. As shown inFIG. 4, the lightly-doped region136may completely encompass the shallow doped region134. The sequence of forming the shallow doped region134and the lightly-doped region136may exchange. For example, the second implanting process P2may be performed before performing the first implanting process P2.

Please refer toFIG. 5. Subsequently, a second spacer138is formed on the on the substrate110and covering the first spacer132. According to an embodiment, the material of the second spacer138may include SiO2, SiN, SiON or SiCN, but not limited thereto. Preferably, the second spacer comprises SiN. Similar to the process of forming the first spacer132, the second spacer138may be formed by first forming a second spacer material layer conformally covering the substrate110, the top surface of the gate structure120and the first spacer132on the sidewall of the gate structure120, and then performing an anisotropic etching process to remove the second spacer material layer on the substrate110and on the top surface of the gate structure120. The remaining second spacer material layer on the first spacer132becomes the second spacer138. Notably, the bottom surface of the second spacer138is completely overlapping on the shallow doped region134. The first spacer132and the second spacer138collectively form the spacer139, which may be used as an etching mask to define the region of a deep recess for forming the source/drain region.

Please refer toFIG. 6andFIG. 7, which sequentially illustrate the process of forming a deep recess144in the substrate110at two sides of the gate structure120by performing an etching process. Preferably, the etching process may include multiple etching steps to form the deep recess144with a pre-determined shape. For example, as shown inFIG. 6, a dry etching process E1may first be performed, using the gate structure120and the spacer139as an etching mask to anisotropically etching the substrate110thereby defining a first recess142in the substrate110at two sides of the gate structure120and adjacent to the spacer139. The first etching process E1may be a reactive ion etching (RIE) process using etchant gas including Cl2, HBr, SF6, or a mixture thereof, but not limited thereto. As shown inFIG. 6, the substrate110exposed from the first recess142may have a sidewall142athat is vertical to the upper surface of the substrate110and aligned with the bottom edge of the second spacer138. The shallow doped region134and the lightly doped region136are exposed from the sidewall142aof the substrate110.

Following, as shown inFIG. 7, a wet etching process E2is performed to further etch the substrate110through the first recess142, thereby expanding the first recess142into the deep recess144. The wet etching process E2may use alkaline etching solution including KOH, NaOH, N2H4, CsOH, TMAH, or EDP, or a mixture thereof to etch the substrate110. Preferably, the alkaline etching solution of the second etching process E2comprises TMAH. The wet etching process E2may have different etching rates for different crystal surfaces of the substrate110. For example, the wet etching process E2may etch the substrate110much slower on a <111> crystal surface than on a <100> or <110> crystal surface of the substrate110. Due to the crystal orientation selectivity of the wet etching process E2, the vertical sidewall142aof the substrate110may be etched into an inclined sidewall that is the crystal surface of the substrate110having slower etching rate during the second etching process E2and may not be vertical to the upper surface of the substrate110, such as a <111> crystal surfaces of the substrate110. Accordingly, after the wet etching process E2, the first recess142is expanded into the deep recess144having a desired diamond-shaped cross-sectional profile.

Notably, the shallow doped region134, which is substantially an at least partially amorphized region of the substrate110, may have a relatively faster etching rate with respective to other regions of the substrate110during the wet etching process E2. Therefore, after the wet etching process E2, the shallow doped region134may be removed and an air gap146may be formed between the spacer139and substrate110. As shown inFIG. 7, the air gap146has an opening exposed from the deep recess144and having a width T1. The air gap146has a length extending from the opening toward the gate structure120and between the spacer139and the substrate110. As shown inFIG. 7, the air gap146may extends to reach the sidewall of the gate structure110and completely intervenes between the spacer139and the substrate110. In this case, the bottom of the spacer139may be completely overlapped on the air gap146and not in direct contact with the substrate110. In other embodiments, the air gap146may not extend to reach the sidewall of the gate structure120. For example, the air gap146may only extend to a point directly under the first spacer132and completely intervenes between the second spacer138and the substrate110while partially intervenes between the first spacer132and the substrate110. In this case, only the bottom of the second spacer138is completely overlapped on the air gap146and not in direct contact with the substrate110. The bottom of the first spacer132not overlapped on the air gap146may directly contact the substrate110. Preferably, the width T1of the opening of the air gap146is between 10 to 40 angstroms. As shown inFIG. 7, the boundary between the air gap146and the substrate110may be encompassed by the lightly-doped region136. The lightly-doped region136is in direct contact with the source/drain region150.

Please refer toFIG. 8. After forming the deep recess144and the air gap146, an epitaxial growing process may be performed to form a source/drain region150in the deep recess144. During the epitaxial growing process, the epitaxial layer may grow from the exposed surface of the substrate110exposed in the deep recess144until completely filling the deep recess144and then overgrow to form a raised portion higher than the upper surface of the substrate110. It is one feature of the present invention that, by forming the air gap146having a very small opening, such as only between 10 to 40 angstroms in width T1, the epitaxial layer will not grow in the air gap146. Rather, the air gap146may create a heterogeneous interface between the exposed surface of the substrate110and the sidewall of the second spacer138, which is not preferable for the epitaxial growth and may force the epitaxial layer to grow along a direction away from the air gap146when the epitaxial layer meets the boundary160between the air gap146and the substrate110. A faceted surface152of the raised portion of the source/drain region150is therefore formed. According to an embodiment, the faceted surface152may be a <311> crustal surface of the source/drain region150. In this way, the raised portion of the source/drain region150will not cover on the sidewall of the second spacer138. As shown inFIG. 8, the faceted surface152is an exterior surface of the source/drain region150that is exposed from the substrate110and borders the substrate110on the boundary160between the air gap146and the substrate110. The source/drain region150may further have an interior surface153that is completely embedded in the substrate110and adjoins the faceted surface150on the boundary160between the air gap146and the substrate110.

According to an embodiment, the source/drain region150may comprise dopants and have a lattice constant different from a lattice constant of the substrate110to provide stress to the channel region of the semiconductor device. The dopants may be in-situ added to the source/drain region150during the epitaxial growing process. According to an embodiment, the material of the dopants may be chosen from a group comprising P, C, As, InGaAs, Ge, InAs, InP or Group III-V semiconductor compound, depending on the conductive type of the semiconductor device. Furthermore, the source/drain region150may comprise conductive dopants to increase drive current of the semiconductor device. According to an embodiment, the conductive dopants may comprise P, As or Sb when the semiconductor device is a n-type transistor. On the other hand, the conductive dopants may comprise B or BF2when the semiconductor device is a p-type transistor. The conductive dopants may be in-situ added to the source/drain region150during the epitaxial growing process, or by performing an ion implantation process after the epitaxial growing process.

Please refer toFIG. 9. Subsequently, an interlayer dielectric layer166is deposited on the substrate110, covering the gate structure120, the spacer139and the source/drain region150. After planarizing the interlayer dielectric layer166and exposing a top surface of the gate structure120, such as a surface of the pad layer126, a replacement metal gate (RMG) process is performed to replace the gate structure120with a metal gate structure170. The replacement metal gate (RMG) process may be conventional and would not be illustrated herein for the sake of simplicity. The interlayer dielectric layer166may comprise multiple layers made of different materials. For example, the interlayer dielectric layer166may have a contact etching stop layer (not shown) made of silicon nitride to serve as an etching stop layer for defining the contact holes (not shown) in the interlayer dielectric layer166, and a dielectric layer (not shown) on the contact etching stop layer and made of silicon oxide or low-k dielectric material. According to an embodiment, the interlayer dielectric layer166will not fill into the air gap146when the width T1of the opening of the air gap146is small, and sealing the air gap146between the spacer139and the substrate110.

As shown inFIG. 9, the metal gate structure170may include an interfacial layer172, a high-k dielectric layer174, a work-function metal layer176, a low-resistance metal layer178and a cap layer179. The material of the interfacial layer172may comprise silicon oxide, but not limited thereto. The material of the high-k dielectric layer174may include hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (AlO), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), tantalum oxide (TaO), zirconium oxide (ZrO), strontium zirconium silicon oxide (ZrSiO), or hafnium zirconium oxide (HfZrO), but not limited thereto. The material of the work-function metal layer176is chosen depending on the conductive type of the semiconductor device. For example, when the semiconductor device is an n-typed transistor, the work function metal layer176may comprise titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), or hafnium aluminide (HfAl), but not limited thereto. On the other hand, when the semiconductor device is a p-typed transistor, the work function metal layer176may comprise TiN, TaN, titanium carbide (TiC), tantalum carbide (TaC), tungsten carbide (WC), or aluminum titanium nitride (TiAlN), but not limited thereto. The material of the low-resistance metal layer178may include Al, Ti, Ta, W, Nb, Mo, Cu, TiN, TiC, TaN, Ti/W and Ti/TiN, but not limited thereto. The material of the cap layer179may include silicon nitride, but not limited thereto.

Please refer toFIG. 10, which is a schematic cross-sectional diagram illustrating a variant of the preferred embodiment previously illustrated. The step shown inFIG. 10corresponds to the step shown inFIG. 8. During the wet etching process E2, more substrate110may be removed and the etched inclined sidewall of the substrate110exposed in the deep recess144may be laterally shifted to be closer to the channel region under the gate structure120. Consequently, as shown inFIG. 10, after the epitaxial growing process, the faceted surface152of the source/drain region150may touch the bottom edge of the second spacer138. In this case, the air gap146may be sealed between the spacer139and the substrate110by the source/drain region150before forming the interlayer dielectric layer166.

Overall, the present invention provides an improved semiconductor device and manufacturing process thereof, which particularly forms a small air gap between the spacer and the substrate before performing the epitaxial growing process for forming the source/drain region. The small air gap may force the epitaxial layer to grow along a direction away from the spacer, thereby preventing the epitaxial layer from covering on the bottom sidewall of the spacer. The parasitic capacitance between the source/drain region and the gate of the semiconductor device is therefore reduced.