Metal strap for DRAM/FinFET combination

A metal strap is formed in a middle-of-line (MOL) process for communication between an eDRAM and a FinFET. An oxide is deposited in a trench over the eDRAM to prevent development of an epitaxial film prior to formation of the metal strap. The result is an epiless eDRAM strap in a FinFET.

FIELD OF THE INVENTION

This disclosure relates generally to memory in semiconductor devices and, more specifically, to a structure for a combined FinFET and DRAM device.

BACKGROUND OF THE INVENTION

The fabrication of semiconductor devices involves forming electronic components in and on semiconductor substrates, such as silicon wafers. These electronic components may include one or more conductive layers, one or more insulation layers, and doped regions formed by implanting various dopants into portions of a semiconductor substrate to achieve specific electrical properties. Semiconductor devices include transistors, resistors, capacitors, and the like, with intermediate and overlying metallization patterns at varying levels, separated by dielectric materials, which interconnect the semiconductor devices to form integrated circuits.

A complementary metal oxide semiconductor device (CMOS) uses symmetrically-oriented pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) arranged on substrate, such as bulk silicon or silicon or silicon-on-insulator (SOI) substrates. Source and drain regions associated with the MOSFET are connected by a channel. A gate disposed over the channel controls the flow of current between the source and drain regions. The channel may be defined by a thin “fin” that provides more than one surface through which the gate controls the flow of current, thereby making the MOSFET a “FinFET” device.

Dynamic random access memory (DRAM) employs memory cells having a FinFET (or other type of transistor) and a storage capacitor arranged in series. Embedded DRAM (eDRAM) embeds these memory cells into the same semiconducting material that contains a microprocessor, which allows for wider buses and faster operating speeds (as compared to DRAM) in an integrated circuit (IC) chip. Many of these embedded memory cells comprising FinFETs and storage capacitors can be arranged on a single chip or within a single package to define an array. Operation of the memory cells is controlled by various circuits, many of which are structurally different from each other, and warrant different manufacturing techniques.

SUMMARY

One aspect of an embodiment of the present invention discloses a method that comprises providing a semiconductor substrate having a storage capacitor formed in a deep trench. The method further comprises depositing a dielectric layer into a recess adjacent to a conductive region of the storage capacitor. The method further comprises forming a fin of a transistor, including a portion of the dielectric layer deposited into the recess. The method further comprises etching an opening through the dielectric layer over the conductive region. Subsequently, the method comprises depositing a metal layer into the opening and onto the conductive region.

Another aspect of an embodiment of the present invention discloses an electrical structure. The electrical structure comprises a storage capacitor formed in a deep trench of a semiconductor substrate; a transistor formed on the semiconductor substrate; a fin of a transistor, formed with an adjacent oxide deposit; an epitaxial film grown on the fin of the transistor; a metal strap deposited in an opening, the metal strap connecting the transistor to the storage capacitor; and the adjacent oxide deposit is located above, and in contact with, a conductive region of the storage capacitor.

DETAILED DESCRIPTION

A metal strap is formed in a middle-of-line (MOL) process for communication between a trench capacitor of an eDRAM and a FinFET. An oxide is deposited in a trench over the eDRAM capacitor to prevent development of an epitaxial film prior to formation of the metal strap. The result is an epiless eDRAM strap in a FinFET.

In exemplary embodiments of the present invention, an eDRAM metal strap connection structure for a FinFET provides communication between a storage capacitor and a first end of a fin of the FinFET. The storage capacitor is located in a deep trench formed in a substrate, and the fin is formed on a surface of the substrate. As is known by those of skill in the art, a deep trench is one in which the depth from an upper edge of the trench to a bottom of the trench is about 1-5 micrometers (μm). The eDRAM metal strap connection structure allows for electrical connection of the fin to the storage capacitor in the deep trench.

Some embodiments of the present invention recognize the following facts, potential problems, and/or potential areas for improvement with respect to the current state of the art: (i) combining the FinFET technology with an eDRAM is a desirable, yet difficult to practice, technology; (ii) conventional approaches that use polysilicon strap technology for communication suffer from high resistance; (iii) trench topology tends to cause bad polysilicon profile; (iv) conventional practices result in epitaxial film present within the deep trench (DT) causing shorts to occur; and/or (v) conventionally, the top oxide layer, sometimes referred to as the trench top oxide (TTO), introduces concerns of oxide thickness and/or buried oxide (BOX) layer corrosion.

For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. The terms “overlying”, “atop”, “on”, “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure may be present between the first element and the second element. The term “direct contact” means that a first element and a second element are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.

FIGS. 1A and 1Bdepict the top view and cross-sectional view of an exemplary semiconductor device where metal strap104is used in a low-resistance eDRAM strap FinFET. FinFET100includes semiconductor substrate102. Semiconductor substrate102may be composed of a silicon containing material. Silicon containing materials include, but are not limited to, Si, single crystal Si, polycrystalline Si, SiGe, single crystal silicon germanium, polycrystalline silicon germanium, or silicon doped with carbon, amorphous Si and combinations and multi-layers thereof. Semiconductor substrate102may also be composed of other semiconductor materials, such as germanium and compound semiconductor substrates, such as type III/V semiconductor substrates, e.g., GaAs. Although semiconductor substrate102is depicted as a bulk semiconductor substrate, semiconductor on insulator (SOI) substrate arrangements, such as silicon on insulator substrates, are also suitable for semiconductor substrate102.

In this embodiment, metal strap104is a low resistance metal deposited after FinFET device processing, such that it does not see the epitaxy process of the FinFET device. The metal strap provides communication between storage capacitor106and fin108of finFET100. The storage capacitor is disposed in a deep trench110formed in buried oxide (BOX) layer112, as well as in any underlying bulk substrate material of substrate102. The fin is formed from a silicon-on-insulator (SOI) material at an upper surface of substrate102. Communication between the storage capacitor and the fin is effected through the metal strap.

FinFET100has three terminals, i.e., gate stack114, source region120, and drain region122. Gate stack114is a structure used to control output current, i.e., flow of carriers in a channel, below gate stack114through electrical or magnetic fields. The channel is the region between source region120and drain region122that becomes conductive when FinFET100is turned on. Source region120, is a doped region in the transistor from which majority carriers are flowing into the channel. Drain region122is a doped region in the transistor located at the end of the channel in which carriers are flowing into from source region120via the channel and out of FinFET100. In an alternative embodiment, source region120and drain region122may be “raised” source/drain regions, wherein a portion of the respective source/drain region is formed through epitaxial growth of semiconductor material embedded in semiconductor substrate102. The respective source/drain regions can then rise out of semiconductor substrate102, while another portion of the respective source/drain regions resides within semiconductor substrate102.

Gate stack114includes at least a gate dielectric116atop a gate conductor118. Gate conductor118may be a metal gate electrode. Gate conductor118may be composed of any conductive metal including, but not limited to, W, Ni, Ti, TiN, Mo, Ta, Cu, Pt, Ag, Au, Ru, Ir, Rh, and Re, and alloys that include at least one of the aforementioned conductive elemental metals. In another embodiment, gate conductor118may also be composed of a doped semiconductor material, such as n-type doped polysilicon.

Although not depicted inFIG. 1, gate conductor118may be a multi-layered structure. For example, gate conductor118may include a second conductive material atop a metal gate electrode. In one example, the second conductive material may be a doped semiconductor material, such as a doped silicon containing material, e.g., n-type doped polysilicon. When a combination of conductive elements is employed, an optional diffusion barrier material such as TaN or WN may be formed between the conductive materials.

Gate dielectric116of gate stack114is typically present on a gate conductor118. Gate dielectric116may be a dielectric material, such as SiO2, or alternatively a high-k dielectric, such as oxides of Hf, Ta, Zr, Al, or combinations thereof. In another embodiment, gate dielectric116is comprised of an oxide, such as ZrO2, Ta2O5, or Al2O3. In one embodiment, gate dielectric116has a thickness ranging from 1 nm to 10 nm. In another embodiment, the gate dielectric116has a thickness ranging from 1.0 nm to 2.0 nm.

Spacer124is in direct contact with the sidewalls of gate stack114. The spacer typically has a width ranging from 2.0 nm to 15.0 nm, as measured from the sidewall of gate stack114. The spacer is generally composed of a dielectric, such as a nitride, oxide, oxynitride, or a combination thereof.

Gate dielectric116and gate conductor118of gate stack114are present over the channel. Source region120and drain region122are on opposing sides of the channel. The conductivity-type of source region120and drain region122determines the conductivity of FinFET100. Conductivity-type denotes whether source region120and drain region122have been doped with a p-type or n-type dopant. N-type dopant in a silicon containing material includes type V elements from the Periodic Table of Elements, such as phosphorus and arsenic. P-type dopant in a silicon containing material includes type III elements from the Periodic Table of Elements, such as boron.

Each of source region120and drain region122may include an extension dopant region (not shown) and a deep dopant region. The deep dopant region is usually formed either through implantation or epitaxial growth, wherein the source and drain regions are doped in situ during formation.

Although only one semiconductor device (FinFET100) is shown on substrate102, any number of semiconductor devices may be formed on substrate102in various embodiments. Where multiple devices exist, device regions are preferably separated via dielectric trench isolation (not shown). This prevents electrical current leakage between adjacent semiconductor device components. In various embodiments, isolation regions may be at varying depths to form embodiments of shallow trench isolation or deep trench isolation.

FIGS. 2-9depict one exemplary method of fabricating FinFET100, according to an embodiment of the present invention. Referring now toFIG. 2, the semiconductor substrate102is provided as the bulk substrate material into which oxygen ions are implanted to form BOX layer112of silicon dioxide (SiO2) that defines SOI layer202at the surface of substrate102. Alternatively, BOX layer112and SOI layer202are formed using a conventional deposition process such as, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), chemical solution deposition, sputtering, atomic layer deposition (ALD), physical vapor deposition (PVP), spin-on coating, epitaxial growth and other like deposition processing. Nitride layer208is located above the SOI layer. Deep trench110is formed in the substrate using any suitable method, such as etching.

Continuing withFIG. 2, storage capacitor106is formed in deep trench110. In forming the storage capacitor, a film of high k dielectric material, referred to as dielectric film204, is first deposited on at least the sidewalls of the opening forming the deep trench. The dielectric film may comprise one or more of the following materials: (i) hafnium silicate; (ii) zirconium silicate; (iii) hafnium dioxide; and/or (iv) zirconium dioxide. Deposition of the dielectric film may be by chemical vapor deposition or atomic layer deposition. After deposition of the dielectric film, the deep trench is filled with conductor206, to form storage capacitor106. The conductor may be a poly conductor, such as polysilicon, or a metal.

Referring now toFIG. 3, recess308is formed according to an embodiment of the present invention. Any suitable anisotropic etching technique (e.g., dry etching) may be employed for form the recess. In one embodiment, the etching process is a timed etch process, to reach a specified depth.

InFIG. 4, oxide layer402, which may be referred to as TTO, is deposited in recess308. The TTO deposition process may be accomplished, for example, with CVD (Chemical Vapor Deposition), plasma enhanced CVD, or other suitable method.

FIG. 5depicts a state during fabrication of FinFET100when nitride layer208(seeFIG. 4) is stripped and nitride layer502is deposited such that oxide layer402, among other top surface regions, is covered by the nitride layer.

InFIGS. 6A and 6B, nitride layer502is removed and fin108is patterned and etched.FIG. 6Bis the top view of the structure as-developed when the fin is patterned, before the gate(s) are formed. Typically, patterning is accomplished with oxide sidewall image transfer (SIT) process. Alternatively, other appropriate lithographic processes are employed to pattern fin108.

When the nitride layer is removed during patterning, it should be noted that oxide layer402over conductor206is both self-aligned and thick. The self-aligned process is obtained from the fill and recess process of oxide layer402. In that way, no separate mask operation is needed.

Referring now toFIG. 7, gate stack114is patterned and spacers124a,124bare formed. Additionally gate stack702is patterned in the illustrated state of manufacture. Note that there is no deep topography in a trench at this stage of manufacture. The trench extends only to BOX layer112. In that way, the profile of fin108is easier to control than using conventional practices.

InFIG. 8, epitaxial layer802is developed for only fin108, adding no epitaxial material at top oxide layer402, or TTO. Selective epitaxial growth assures that the epitaxial layer is gown only on the fin. This process assures that no epitaxial film is deposited in the deep trench where capacitor106is located and where the metal strap will be deposited, as shown inFIG. 1.

FIG. 9illustrates the manufacturing stage just before the metal strap is deposited and FinFET100is complete. InFIG. 9, middle-of-line (MOL) wafer planarization occurs after deposition of oxide layer902. The “gate last” approach is illustrated, following replacement metal gate (RMG) process flow.

Also shown inFIG. 9, after planarization, recess904is formed. Any suitable anisotropic etching technique (e.g., dry etching) may be employed to form the recess. The recess can be formed by patterning the hole using a standard photo lithography process. This recess can also be formed together with other contact to another FinFET device on the wafer; hence, no additional lithography steps are needed.

Any use of the terms “connected,” “coupled,” or variants thereof, should be interpreted to indicate any such connection or coupling, direct or indirect, between the identified elements. As a non-limiting example, one or more intermediate elements may be present between the “coupled” elements. The connection or coupling between the identified elements may be, as non-limiting examples, physical, electrical, magnetic, logical, or any suitable combination thereof, in accordance with the described exemplary embodiments. As non-limiting examples, the connection or coupling may comprise one or more printed electrical connections, wires, cables, mediums, or any suitable combination thereof.

FIG. 10depicts the steps of a flowchart for process1000for forming a metal strap connection between a DRAM and a FinFET, according to an embodiment of the present invention.

FIG. 10also depicts the steps for process1000of forming a metal strap connection between a FinFET and an embedded capacitor, such as an eDRAM. The first step in this exemplary process flow is to etch a recess through a silicon-on-insulator (SOI) substrate into a corresponding buried oxide (BOX) layer (step1002). The recess exposes a conductor of the embedded capacitor, such as polysilicon, at a depth below the top surface of the substrate. In some embodiments, as illustrated inFIG. 3, the depth is at a level within the BOX layer. Subsequent to etching the recess, an oxide is deposited into the recess (step1004). This oxide layer deposited into the recess may be referred to as the TTO layer. In subsequent steps, the oxide will self-align during fin formation in the SOI substrate. Subsequent processing includes: stripping a nitride layer from the SOI layer (step1006); and (ii) re-depositing a nitride layer (step1008) prior to step1010, where a fin of a transistor is formed on the semiconductor substrate. Typically, this forming process is achieved with an oxide sidewall image transfer (SIT) process. It should be noted that in this step, the oxide layer deposited in step1004is self-aligned, such that no separate mask is needed. Subsequent to forming the fin, a gate structure is patterned to contact the fin (step1012). In this patterning step, there is no deep topography in the trench, which only reaches the BOX, just like the fin. In that way, profiling the gate is easier to control, compared to conventional practices. Subsequent processing includes: (i) forming spacer(s) on the gate (step1014); (ii) growing an epitaxial layer at the fin only, that is, no epitaxial film is placed in a trench or otherwise in contact with the storage capacitor (step1016); and (iii) middle-of-line (MOL) wafer planarization (step1018), where a replacement metal gate (RMG) process flow occurs. Subsequent to patterning the gate structure and the MOL planarization, a recess is etched through the oxide layer to the storage capacitor (step1020). A low-resistance metal is deposited into the etched recess (step1022), referred to a “metallization.” The metallization step may occur at the same time as contact is made to a logic device.

Some embodiments of the present invention may include one or more of the following features, characteristics, and/or advantages: (i) a low resistance metal strap provides for improved communication over conventional polysilicon structures, where the metal strap is formed after FIN device processing at middle-of-line (MOL); (ii) conventional trench topography is eliminated; (iii) no epitaxial film in the deep trench; and/or (iv) the top oxide layer, or TTO, where the TTO completely covers the trench capacitor, is self-aligned when the fin is formed.

Having described preferred embodiments of a method for forming a liner free tungsten contact and the resulting structure (which are intended to be illustrative and not limiting), it is noted that modifications and variations may be made by persons skilled in the art in light of the above teachings. It is, therefore, to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims.