Fully silicided gate formed according to the gate-first HKMG approach

When forming field-effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art, which may overcome this problem. However, formation of a fully silicided gate is hindered by the fact that silicidation of the source and drain regions and of the gate electrode are normally performed simultaneously. The claimed method proposes two consecutive silicidation processes which are decoupled with respect to each other. During the first silicidation process, a metal silicide is formed forming an interface with the source and drain regions and without affecting the gate electrode. During the second silicidation, a metal silicide layer having an interface with the gate electrode is formed, without affecting the transistor source and drain regions.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors comprising a gate with a metal layer.

2. Description of the Related Art

Transistors are the dominant components in modern electronic devices. Currently, several hundred millions of transistors may be provided in presently available complex integrated circuits, such as microprocessors, CPUs, storage chips and the like. It is then crucial that the typical dimensions of the transistors included in an integrated circuit have as small as possible typical dimensions, so as to enable a high integration density.

One of the most widespread technologies is the complementary metal-oxidesemiconductor (CMOS) technology, wherein complementary field effect transistors (FETs), i.e., P-channel FETs and N-channel FETs, are used for forming circuit elements, such as inverters and other logic gates, to design highly complex circuit assemblies.

Transistors are usually formed in active regions defined within a semiconductor layer supported by a substrate. Presently, the layer in which most integrated circuits are formed is made out of silicon, which may be provided in crystalline, polycrystalline or amorphous form. Other materials, such as, for example, dopant atoms or ions, may be introduced into the original semiconductor layer.

When fabricating transistors with typical gate dimensions below 50 nm, the so-called “high-k/metal gate” (HKMG) technology has by now become the new manufacturing standard. According to the HKMG manufacturing process flow, the insulating layer included in the gate electrode is comprised of a high-k material. This is in contrast to the conventional oxide/polysilicon (poly/SiON) method, whereby the gate electrode insulating layer is typically comprised of an oxide, preferably silicon dioxide or silicon oxynitride in the case of silicon-based devices.

Currently, two different approaches exist for implementing HKMG in the semiconductor fabrication process flow. In the first approach, called gate-first, the fabrication process flow is similar to that followed during the traditional poly/SiON method. Formation of the gate electrode, including the high-k dielectric film and the work function metal film, is initially performed, followed by the subsequent stages of transistor fabrication, e.g., definition of source and drain regions, silicidation of portions of the substrate surface, metallization, etc. On the other hand, according to the second scheme, also known as gate-last or replacement gate, fabrication stages such as dopant ion implantation, source and drain region formation and substrate silicidation are performed in the presence of a sacrificial dummy gate. The dummy gate is replaced by the real gate after the high-temperature source/drain formation and all silicide annealing cycles have been carried out.

HKMG enables increasing the thickness of the insulation layer in the gate electrode, thereby significantly reducing leakage currents through the gate, even at transistor channel typical sizes as low as 30 nm or smaller. However, implementation of HKMG brings about new technological challenges and requires new integration schemes with respect to the conventional poly/SiON technology.

For example, new materials have to be found in order to tune the work function of gate electrode species, so as to adjust the transistor threshold voltage to a desired level.

In the gate-first HKMG approach, a thin film of a silicon/germanium (SiGe) alloy is deposited on the surface of the silicon layer in order to adjust the transistor threshold voltage to a desired level. Since a portion of this thin film is included in the channel region of the FET, this SiGe thin film is also commonly referred to as “channel SiGe.”

Since epitaxial SiGe epitaxially grown on silicon experiences a compressive stress, SiGe alloys may also be used to introduce a desired stress component into the channel region of a P-channel FET. This is a desirable effect since the mobility of holes in the channel region of a P-channel FET is known to increase when the channel region experiences a compressive stress. Thus, trenches may be formed in portions of the source and drain regions of a FET adjacent to the channel region. An SiGe alloy may be subsequently epitaxially grown in the trenches. This SiGe is also commonly referred to as “embedded SiGe.”

Furthermore, in the HKMG technology, a thin “work function metal” layer is inserted between the high-k dielectric and the gate material placed above the high-k dielectric. The threshold voltage may thus be adjusted by varying the thickness of the metal layer. The gate metal layer may comprise, for example, tantalum (Ta), tungsten (W), titanium nitride (TiN) or tantalum nitride (TaN). A work function metal, such as, for example, aluminum, may also be included in the gate metal layer.

Since the gate material formed on top of the gate metal layer is usually a semiconductor, for example poly-Si, a Schottky barrier is established at the interface between the gate metal layer and the gate semiconductor material. This undesirably degrades the AC performance by limiting the circuit switching speed.

FIGS. 1a-1cshow some aspects of a transistor manufacturing flow according to the known gate-first HKMG approach.

FIG. 1aschematically illustrates a cross-sectional view of a semiconductor structure100in an advanced manufacturing stage. The semiconductor structure100has been obtained after forming insulation regions102bin a semiconductor layer102. Insulation regions102bmay have been formed as shallow trench isolations. The semiconductor layer102, typically comprising monocrystalline silicon, is formed on a substrate101, which may be comprised of any appropriate carrier.

Active regions102aare subsequently formed in the semiconductor layer102. This may comprise performing one or more well implantations. Active regions are to be understood as semiconductor regions in and above which one or more transistors are to be formed. For convenience of display, a single active region102ais illustrated, which is laterally limited by insulation regions102b.

FIG. 1ashows that a FET150has been formed after defining the active region102a. In the gate-first HKMG, a gate structure160is formed on the upper surface of the active region102a. Although not shown, a thin channel SiGe film may have been deposited on the surface of the active region102abefore forming the gate structure160.

The gate structure160is formed by sequentially stacking layers of different materials, which are subsequently patterned so as to obtain the desired gate structure size and dimensions. The stack making up the gate structure160comprises: insulation layer161formed on the surface of the active region102a; gate metal layer164; gate material162; and a cap layer (not shown) formed adjacent to the gate material162and exposing an upper surface to the outside. The gate stack is usually laterally delimited by a spacer structure163, which may be advantageously used as an implantation mask in subsequent manufacturing stages.

The insulation layer161, formed on the surface of the active region102a, comprises a high-k material. The gate metal layer164is formed between the insulation layer161and the gate material162so as to adjust the transistor threshold voltage. The gate material162, formed directly on the upper surface of the gate metal layer164, typically comprises a semiconductor, such as poly Si. The cap layer is formed at the top of the gate stack and usually is comprised of an insulating, relatively tough material such as, for example, silicon nitride (Si3N4).

Where needed, embedded SiGe alloy layers may be formed in the active region102aafter forming the gate structure160.

Thereafter, several implantations are carried out in order to define source and drain regions151of the transistor150. The implantations may comprise halo/extension implants, giving rise to extension regions151eand halo regions (not shown) in the active region102a. After performing halo/extension implantations, the spacer structure160may be broadened and an additional series of implantations may be carried out in order to form deep regions151dof the source and drain regions151.

According to the conventional manufacturing flow, the insulating cap layer is removed from the top of the gate structure160before performing these implantations. Typically, the cap layer is removed after forming the gate structure160and before performing the halo/extension implantations. After removing the cap layer, the gate structure160exposes the gate material162to the outside, as shown inFIG. 1a.

An annealing step follows the series of implantations defining source and drain regions151. Annealing is performed in order to activate the implanted dopant ions and to allow the crystalline structure to recover from implantation damage.

After the annealing step, a metal silicide layer is formed in order to decrease the contact resistance to the electrodes of the transistor150. The process of metal silicide formation is schematically illustrated inFIGS. 1band1c.

As shown inFIG. 1b, a refractory metal layer108is deposited onto the exposed face of the semiconductor structure100. The refractory metal layer108may comprise, for example, a metal, such as nickel, titanium, cobalt and the like. Preferably, the refractory metal layer108comprises nickel. The refractory metal layer108may also comprise platinum, which, in some cases, may promote a more homogeneous formation of nickel monosilicide.

A heat treatment is then applied to the semiconductor structure100in order to promote a chemical reaction between the metal atoms of the layer108and the silicon atoms of the exposed surface of the semiconductor structure100.

FIG. 1cshows that, as a result of the heat treatment, nickel silicide regions153and162aare formed, that substantially comprise low-resistivity nickel monosilicide. More specifically, the metal silicide layer153has formed partly in and partly on top of the active region102a, thus forming an interface with the source and drain regions151. On the other hand, the metal silicide layer162ahas formed on top of the gate structure160, thus forming an interface with the gate material162exposed before the deposition of the metal layer108. It should be noted that the silicon material contained in the sidewall spacer structure163and the insulating regions102bdoes not substantially take part in the chemical reaction induced during the heat treatment process, as it is present in those features only as a thermally stable silicon dioxide and/or silicon nitride material.

As said above, the transistor resulting from the above-described manufacturing flow is affected by the drawback of the Schottky barrier forming at the interface between the gate metal layer164and the gate material162. In order to get rid of this Schottky barrier, it would be convenient to form a metal silicide layer162aof a thickness sufficient for directly forming an interface with the gate metal layer164.

One method of achieving this goal is forming so-called “fully silicided” gates, wherein the metal silicide layer162atotally replaces the gate material162so as to directly contact the gate metal layer164. An example of a method of forming a fully silicided gate structure may be found in U.S. Pat. No. 6,821,887. In this application, the height of the gate structure is appropriately chosen so as to permit the reaction of all gate material with the refractive metal during the silicidation process described above.

However, the methods of forming a fully silicided gate known from the prior art use the same silicidation step for forming the metal silicide layer153on the source/drain regions and the metal silicide layer162aon top of the gate, as described above. Thus, the thickness of the gate metal silicide layer162ais correlated to the thickness of the source/drain metal silicide layer153. This is a serious limitation, since the thickness of the source/drain metal silicide layer153may not be increased beyond a maximum. In general, the thickness of the source/drain metal silicide layer153must be considerably smaller than the thickness of the semiconductor layer102. This problem becomes more and more urgent as the typical device sizes decrease, since reducing, for example, the gate length also requires a corresponding scaling of source and drain regions151in the vertical direction.

By using known methods, it is, thus, particularly difficult to obtain a fully silicided gate while maintaining the thickness of the source/drain metal silicide layer at a sufficiently low value. Therefore, a need arises for an improved transistor manufacturing method permitting formation of a source/drain metal silicide layer and a gate metal/silicide layer of desired thicknesses.

SUMMARY OF THE INVENTION

The present disclosure is based on the new and inventive idea that the manufacturing process of a transistor may be improved by decoupling the silicidation process of the source and drain regions from the silicidation process of the gate electrode. Based on this idea, one method of forming a transistor includes forming a gate structure onto a semiconductor layer, the gate structure exposing on its upper surface a top insulating layer formed on a gate material, forming source and drain regions of the transistor in the semiconductor layer, forming a first metal silicide layer having an interface with the source and drain regions, the first metal silicide layer being formed in the presence of the top insulating layer, removing the top insulating layer from the gate structure so as to expose the gate material after forming the first metal silicide layer, and forming a second metal silicide layer in the gate structure after removing the insulating layer, the second metal silicide layer being formed so as to at least partially replace the gate material. When forming the first metal silicide layer on the source/drain region, the gate is screened by the top insulating layer, thus preventing metal silicide from forming on top of the gate. A second metal silicide layer is subsequently formed on top of the gate structure after removing the top insulating layer. Thus, the first and the second silicidation processes are decoupled from each other. This enables independent optimization of the thickness of the first and second metal silicide layers. In particular, a fully silicided gate may be obtained without having to concurrently increase the thickness of the source/drain metal silicide layer.

Advantageously, the surface of the source and drain regions may be screened while forming the second metal silicide layer on top of the gate. In this manner, the first metal silicide layer already formed in the source/drain regions is not affected by the second silicidation process, i.e., the process resulting in formation of the second metal silicide layer on the gate. This completely decouples the first and second silicidation processes from each other.

DETAILED DESCRIPTION

It should be noted that, where appropriate, the reference numbers used in describing the various elements illustrated inFIGS. 2a-2jsubstantially correspond to the reference numbers used in describing the corresponding elements illustrated inFIGS. 1a-1cabove, except that the leading numeral for corresponding features has been changed from a “1” to a “2.” For example, semiconductor device “100” corresponds to semiconductor device “200,” gate insulation layer “161” corresponds to gate insulation layer “261,” gate electrode “160” corresponds to gate electrode “260,” and so on. Accordingly, the reference number designations used to identify some elements of the presently disclosed subject matter may be illustrated in theFIGS. 2a-2jbut may not be specifically described in the following disclosure. In those instances, it should be understood that the numbered elements shown inFIGS. 2a-2jwhich are not described in detail below substantially correspond with their like-numbered counterparts illustrated inFIGS. 1a-1c, and described in the associated disclosure set forth above.

Furthermore, it should be understood that, unless otherwise specifically indicated, any relative positional or directional terms that may be used in the descriptions below—such as “upper,” “lower,” “on,” “adjacent to,” “above,” “below,” “over,” “under,” “top,” “bottom,” “vertical,” “horizontal” and the like—should be construed in light of that term's normal and everyday meaning relative to the depiction of the components or elements in the referenced figures. For example, referring to the schematic cross-section of the semiconductor device200depicted inFIG. 2a, it should be understood that the gate electrode structure260is formed “above” the active region202aand that the gate metal layer264is formed “below” or “under” the gate material262.

FIG. 2ashows a cross-section of a semiconductor structure200during an advanced manufacturing stage substantially corresponding to the fabrication method according to the prior art shown inFIG. 1a.

The semiconductor structure200comprises a semiconductor layer202in which isolation regions202bhave been formed. Isolation regions202bmay comprise, for example, shallow trench isolations. Isolation regions202blaterally define an active region202a. A plurality of active regions202amay be formed in the semiconductor layer202, although only one is shown inFIG. 2a. One or a series of implantations, e.g., well implantations, may have been performed in order to provide the active region202awith a desired doping profile.

According to one embodiment, the semiconductor layer202comprises silicon. According to a particular embodiment, the semiconductor layer202comprises monocrystalline silicon.

The semiconductor layer202is formed attached to a substrate201. The substrate201, which may represent any appropriate carrier material, and the semiconductor layer202may form a silicon-on-insulator (SOI) configuration. Alternatively, the semiconductor layer202may be formed in the bulk of the substrate201.

Although not shown, a thin film of a semiconductor alloy, e.g., a channel SiGe film, may have been epitaxially formed on the surface of the semiconductor layer202.

The semiconductor structure200comprises a transistor250formed partly in and partly on the semiconductor layer202. The transistor250may be a FET, for example an N-channel FET or a P-channel FET. For example, the transistor250may form with a second transistor of an opposite polarity (not shown) a pair used in the CMOS technology.

The transistor250comprises a gate structure260, formed on the surface of the semiconductor layer202after having defined the active region202aand, where needed, after forming the channel SiGe film. The gate structure260is preferably formed according to the HKMG technology. According to a particular embodiment, the gate structure260is performed according to the gate-first HKMG approach.

Thus, the gate structure260comprises a gate insulating layer261comprising a high-k material. By high-k material, it is referred to a material with a dielectric constant “k” higher than 10. Examples of high-k materials used as insulating layers in gate electrodes are tantalum oxide (Ta2O5), strontium titanium oxide (SrTiO3), hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), zirconium oxide (ZrO2) and the like.

The gate structure260further comprises a gate metal layer264formed on the gate insulating layer261in order to permit threshold voltage adjustment. The gate metal layer264may comprise a metal such as tantalum or tungsten. Preferably, the gate metal layer264comprises a nitride such as, for example, titanium nitride or tantalum nitride. A certain percentage of a work function metal species, such as aluminum and the like, may be included in the gate metal layer264, in combination with other materials.

A gate material262is then formed on the gate metal layer264. Typically, the gate material262comprises a semiconductor. In some embodiments, the gate material262comprises polysilicon. As said above, a Schottky barrier is undesirably established at the interface between the gate metal layer264and the gate material262.

A cap layer266is finally formed on top of the gate material262. The cap layer266comprises an upper surface exposed towards the outside of the gate structure260. The cap layer266typically comprises a tough insulator such as, for example, silicon nitride.

According to one embodiment, the length of the gate structure260, i.e., the extension of gate material262along the horizontal direction inFIG. 2a, is less than 50 nm. According to a particular embodiment, the length of the gate structure260is 28 nm or smaller.

After forming the gate structure260, trenches may be formed besides the gate structure260which may be epitaxially filled with a semiconductor alloy, e.g., an SiGe alloy. The semiconductor alloy may be embedded in the active region202ain order to apply a predetermined stress to the channel region of the transistor250. This may be desirable in the case of a P-channel FET, wherein a compressive strain component is known to advantageously increase the mobility of holes in the channel region.

After forming the gate structure260and, where needed, after embedding the semiconductor alloy in the active region202a, source and drain regions251of the transistor250are defined. This is achieved by carrying out a series of ion implantations.

During the first implantation stage, halo regions (not shown) and extension regions251eof the source/drain regions251are formed. The extension regions251edefine the length of the channel region255of the transistor250. Advantageously, the spacer structure263may be used as an implantation mask during halo/extension implantations. The spacer structure263is formed on or adjacent to the sidewalls of the gate structure260. The spacer structure263also carries out the task of protecting sensitive materials included in the gate stack, such as, for example, the materials included in the gate metal layer264.

According to the method known from the prior art, the cap layer266of the gate structure260is removed before performing the halo/extension implantations. Conversely, according to the present disclosure, the cap layer266is maintained during halo/extension implantations.

After performing halo/extension implantations, a further implantation stage is performed in order to form deep regions251dof the source/drain regions251. Conveniently, the spacer structure263may have been broadened between the halo/extension implantations and deep implantations, so as to serve as an implantation mask of a proper thickness when performing deep implantations. Also, deep implantations are performed in the presence of the cap layer266.

After performing halo/extension implantations and deep source/drain implantations, an annealing step is performed in order to activate the doping species and to allow the crystal lattice of the semiconductor layer202to recover after implantation damage.

After defining source/drain regions251and performing the activation annealing, a first silicidation process is carried out on the semiconductor structure200in order to form a metal silicide layer electrically contacting the source and drain regions251. The first silicidation process is schematically shown inFIGS. 2band2c.

FIG. 2bshows the semiconductor structure200during a stage of the manufacturing process flow subsequent to the stage shown inFIG. 2a. A refractory metal layer208ahas been deposited on the surface of the semiconductor structure200. The refractory metal layer208acomprises any of the metals mentioned above when describing layer108. Preferably, the refractory metal layer208acomprises nickel. In contrast to the method according to the prior art, deposition of the refractory metal layer208ais performed in the presence of the gate cap layer266.

After depositing the refractory metal layer208a, a first heat treatment is applied to the semiconductor structure200in order to initiate a chemical reaction between the metal atoms in layer208aand the silicon atoms in those areas of the source and drain regions251that are in contact with the metal layer208a, thereby forming metal silicide regions that substantially comprise low-resistivity nickel monosilicide. Non-reacted metal atoms of the layer208aare removed after the first heat treatment.

FIG. 2cshows the result of the application of the first heat treatment. A metal silicide layer253has formed in and on top of the active region202aso as to form an interface with the source and drain regions251. The metal silicide layer253preferably comprises nickel silicide. The thickness of the refractory metal layer208aand the parameters of the first heat treatment, such as the temperature and the heating time, are chosen so as to obtain a desired thickness of the metal silicide layer253.

It should be noted that, during the first heat treatment, the silicon atoms in the spacer structure263and in the cap layer266do not take part in the chemical reaction with the metal of layer208a, since they contribute to formation of thermally stable silicon dioxide or silicon nitride layers. Thus, since the first silicidation process is carried out in the presence of the spacer structure263and the gate cap layer266, no metal silicide region is formed on top of the gate structure260after depositing the refractory metal layer208aand applying the first heating treatment. In this manner, the parameters of the first silicidation process may be chosen in order to obtain the desired thickness of the metal silicide layer253, without affecting the characteristics of the metal silicide layer to be subsequently formed on top of the gate structure260.

After completing the first silicidation process described above, the gate cap layer266is removed and a second silicidation step is performed on the semiconductor structure200in order to form a metal silicide layer electrically contacting the gate electrode260of the transistor250.FIGS. 2d-2ischematically show the cap layer removal step and the second silicidation process according to one embodiment.

As shown inFIG. 2d, a coating layer270is deposited on the surface of the semiconductor structure200after performing the first silicidation process. The coating layer270preferably comprises a malleable material. Materials from which the coating layer270may be formed include: epoxies, acrylics, vinyl-based chemistries and silicon- or metal-containing organometallics. The coating layer270may also be a dielectric material such as butylcyclobutene (BCB), various polyimides or a low-k material. According to one advantageous embodiment, the coating layer270may comprise a spin-on glass.

The coating layer270may be deposited by using well-established film deposition techniques. According to one embodiment, the coating layer270is spin-coated on the surface of the semiconductor layer200. This embodiment is preferred when the coating layer270comprises a spin-on glass. Preferably, the coating layer270is initially deposited so as to fully cover the semiconductor structure200without leaving any portions thereof exposed.

After being deposited, the coating layer270may be planarized. According to one advantageous embodiment, the coating layer270comprises an optical planarization layer (OPL). In this case, the coating layer270may be effectively planarized by pressing it against a rigid, transparent, flat surface and curing it. Curing of the coating layer270may be achieved by transmitting ultraviolet radiation to the coating layer270through the transparent surface or by heating. As a result of the planarization step, the upper surface270sof the coating layer270is substantially flat and lies on a substantially horizontal plane, as shown inFIG. 2d.

As shown inFIG. 2e, the coating layer270may be back-etched after being planarized as described above with reference toFIG. 2d. The back-etch281may be an isotropic or anisotropic etch. The back-etch281is performed in order to remove an upper portion of the coating layer270. In particular, the back-etch281removes a top portion of the coating layer270which is thick enough to expose an upper portion of the gate structure260. The back-etch281is then carried out until the desired portion of the gate structure260is exposed. The portions of the surface of the semiconductor structure220not occupied by the gate structure260are still covered by the coating layer270after performing the back-etch281.

Although a process has been described above wherein the coating layer270is planarized and back-etched, it should be understood that any process may be used resulting in a coating layer270screening all portions of the surface of the semiconductor structure200with the exception of an upper portion of the gate structure260, as shown inFIG. 2e. For example, a photoresist may also be used as the coating layer270, which could be deposited and appropriately patterned so as to only expose an upper portion of the gate structure260.

FIG. 2fshows that, after exposing the top portion of the gate structure260, a further etch process283is performed in order to remove the cap layer266from the gate structure260. The etch283may comprise any well-established technique which is able to remove an insulating layer such as, for example, an oxide or a nitride. After completing the etch283, the gate material262is exposed towards the outside, as shown inFIG. 2f. It should be observed that, due to the presence of the coating layer270, portions of the surface of the semiconductor structure200not included in the gate structure260are not affected by the etch283.

After removing the cap layer266from the top of the gate structure260, a second silicidation process is carried out, as schematically shown inFIGS. 2gand2h. With reference toFIG. 2g, a second refractory metal layer208bis deposited on the surface of the semiconductor structure200. Preferably, the second refractory metal layer208bcomprises the same materials as the first refractory metal layer208a. However, the second refractory metal layer208bmay have a different thickness from that of the first metal layer208a. The second refractory metal layer208bforms an interface with the gate material262. However, due to the presence of the coating layer270, the metal layer208bis not in contact with the surface of the active region202aand is isolated from the metal silicide layer253.

After depositing the second metal layer208b, a second heat treatment is applied to the semiconductor structure200in order to promote a chemical reaction between the metal atoms in the layer208band the semiconductor atoms, typically silicon, in the gate material262.

FIG. 2hshows the semiconductor structure200after completion of the second heat treatment. The chemical reaction results in the formation of a metal silicide layer262apartly in and partly on top of the gate structure260. The metal silicide layer262apreferably comprises nickel silicide and decreases the contact resistance to the gate electrode. Due to the presence of the coating layer270, the second silicidation process affects neither the metal silicide layer253, nor the source/drain regions251. After completing the second silicidation process, all non-reacted metal of the metal layer208bis removed.

The parameters of the second silicidation process, such as, for example, the thickness of the second refractory metal layer208band the temperature and time of the second heat treatment, are advantageously chosen so that a metal silicide layer262aof a desired thickness is obtained.

Formation of the metal silicide layer262aoccurs at the expense of the gate material262. Thus, an increase in thickness of the metal silicide layer262ausually causes a decrease in thickness of the gate material262.FIG. 2hshows a particular embodiment wherein the thickness of the metal layer208bis large enough and the second heat treatment is applied for a long enough time and at a high enough temperature that all semiconductor atoms in the gate material262react with the refractory metal layer208b. The metal silicide layer262aresulting from this process completely replaces the gate material262, thereby forming an interface with the gate metal layer264. According to the embodiment shown inFIG. 2h, the second silicidation process thus results in a fully silicided gate. This is advantageous in that the Schottky barrier between the gate material262and the gate metal layer264is removed, since the metal silicide layer262aelectrically contacts the gate metal layer264.

After performing the second silicidation process, the coating layer270may be removed.FIG. 2ishows the semiconductor structure200after the coating layer270has been removed. Metal silicide layers253and262aare exposed to the outside for permitting electrical contact to the source/drain regions251and to the gate electrode260, respectively.

Thus, according to the proposed method, the first silicidation and the second silicidation process may be decoupled from each other. Since the first silicidation process is performed in the presence of the gate cap layer266, no metal silicide layer is formed on the gate structure260in the course of the first silicidation process, resulting in formation of the metal silicide layer253. Furthermore, the second silicidation process resulting in formation of the metal silicide layer262ain the gate260does not affect the metal silicide layer253previously formed, due to the presence of the coating layer270. In this manner, the parameters of the first and second silicidation process may be adjusted independently of each other. This results in the possibility of forming the metal silicide layer262awith different characteristics from the metal silicide layer253. For example, the thicknesses of the metal silicide layers253and262amay be adjusted independently. In particular, a fully silicided gate may be obtained, while maintaining the metal silicide layer253at an appropriately low thickness.

After forming metal silicide layers253and262a, the manufacturing process flow continues in a conventional manner.FIG. 2jshows the semiconductor structure200in an advanced manufacturing process stage following that shown inFIG. 2i.

As shown inFIG. 2j, after formation of the silicide layers253and262a, a stressed material layer220is deposited onto the surface of the semiconductor structure200. Subsequently, a UV curing process is applied at a temperature ranging from 400-500° C.

An interlayer dielectric layer230is then deposited onto the stressed material layer220. An etching process is then applied, for example, through a patterned mask234, in order to form via openings272and274. The openings272expose predetermined portions of the metal silicide layer253contacting the source and drain regions251. On the other hand, via openings274expose predetermined portions of the metal silicide layer262acontacting the gate260.

Finally, via openings272and274may be filled with a metal, for example tungsten or copper, so as to form electrical contacts to the source and drain regions and to the gate electrode material of the transistor250.

The present invention provides a convenient method for forming metal silicide layers contacting the source and drain regions and the gate electrode of a transistor, which may, for example, be a FET. The method finds an advantageous application in sub-50 nm fabrication technologies. The method may be advantageously applied in conjunction with the HKMG technology, particularly within the framework of the gate-first HKMG approach.