TFT array substrate and manufacturing method of the same

A TFT array substrate and a manufacturing method of the same are disclosed by the present disclosure. The TFT array substrate includes a base, a light shielding layer, and a low hydrogen layer. The light shielding layer includes a silicon nitride layer formed on the base, and an amorphous silicon light shielding layer formed on the silicon nitride layer. The low hydrogen layer includes a silicon oxide layer formed on the amorphous silicon light shielding layer of the light shielding layer, and a low hydrogen Poly-Si layer formed on the silicon oxide layer. The layer number of the light shielding layer is equal to that of the low hydrogen layer. The time of manufacturing the light shielding layer matched that of manufacturing the low hydrogen layer, which enhances whole capacity of the TFT array substrate dramatically, and reduces risk of the manufacturing process.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the priority to and the benefit of Chinese Patent Application No. 201410172743.7,filed Apr. 25, 2014 and entitled “TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD OF THE SAME,” which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates generally to the technical field of microelectronics, particularly to TFT (thin-film transistor) array substrate and manufacturing method of the same.

BACKGROUND

A TFT array substrate is one of indispensability parts for manufacturing TFT panel. As shown inFIG. 1, a conventional TFT array substrate comprises a glass base1, a light shielding layer2formed on the glass base1, and a low hydrogen layer3formed on the light shielding layer2. The light shielding layer2is an amorphous silicon light shielding layer21. The low hydrogen layer3comprises a first silicon oxide layer31, silicon nitride layer32, a second silicon oxide layer33, and a low hydrogen amorphous silicon layer34which are formed on the light shielding amorphous silicon layer21in turns.

A short time is taken to form the light shielding layer2because it only comprises one layer of amorphous silicon light shielding layer21, while a long time is taken to form the low hydrogen layer3because it comprises four layers. Therefore, during manufacturing of the above conventional TFT array substrate, the device for forming the light shielding layer2is always lying idle, while the device for forming the low hydrogen layer3is always face a bottleneck in production, such that the production of the light shielding layer2does not match that of the low hydrogen layer3, which leads to low production capacity of TFT array substrate. Moreover, many types of layers in the low hydrogen layer3are formed by the same machine, which will cause risks such as cross contamination.

In addition, in the conventional TFT array substrate, the second silicon oxide layer33under the low hydrogen amorphous silicon layer34is thin, which is unstable to be converged. The amorphous silicon light shielding layer21is directly formed on the glass base1, which has poor anti-static electric capacity.

The foregoing information is only used for easily understanding the background of the present disclosure, which may include information in the prior art not well known by the person skilled in the art.

SUMMARY

The embodiments of the present disclosure provide a TFT array substrate, in which the quantity of layers in the light shielding layer is substantially the same with that in the low hydrogen layer, thereby beneficial to improve production capacity.

The embodiments of the present disclosure provide a manufacturing method of the TFT array substrate.

In one aspect, the present disclosure provides a TFT array substrate comprising a base, a light shielding layer, and a low hydrogen layer. the light shielding layer comprises a silicon nitride layer formed on the base, and an amorphous silicon light shielding layer formed on the silicon nitride layer. The low hydrogen layer comprises a silicon oxide layer formed on the amorphous silicon light shielding layer of the light shielding layer, and a low hydrogen poly-Si layer formed on the silicon oxide layer.

In another aspect, the present disclosure provides a manufacturing method of a TFT array substrate, comprising the steps of:

providing a base;

forming a light shielding layer on the base; and

forming a low hydrogen layer on the light shielding layer.

DETAILED DESCRIPTION

A TFT Array Substrate

As shown inFIG. 2, the TFT array substrate according to the present disclosure comprises a base4, a light shielding layer5and a low hydrogen layer6.

The base4may adopt a conventional structure, such as glass base.

The light shielding layer5comprises a silicon nitride layer51and an amorphous silicon light shielding layer52formed on the silicon nitride layer51.

The silicon nitride layer51has the following properties and advantages: considerable breakdown voltage, relatively higher permittivity, high blocking ability so as to effectively block harmful substance in the base4, such as alkali metal and so on; good chemical stability which allows the silicon nitride layer51to hardly react with other acid besides hydrofluoric acid and hot phosphoric acid; good anti-gas penetration ability which effectively reduces effect to the device due to gas and fluid penetration. Consequently, the silicon nitride layer51directly formed on the base4can work at full capacity.

The low hydrogen layer6comprises a silicon oxide layer61formed on the amorphous silicon light shielding layer52of the light shielding layer5and a low hydrogen poly-Si layer62formed on the silicon oxide layer61. The low hydrogen poly-Si layer62of the low hydrogen layer6is located above the amorphous silicon light shielding layer52of the light shielding layer5, and a pattern is formed on the low hydrogen poly-Si layer62of the low hydrogen layer6, in particular, the pattern of the low hydrogen poly-Si layer of the low hydrogen layer6is located over the amorphous silicon light shielding layer52of the light shielding layer5, such that the amorphous silicon light shielding layer52of the light shielding layer5may provide good light shielding effect to the low hydrogen poly-Si layer62of the low hydrogen layer6.

The layer number of the light shielding layer5and low hydrogen layer6is redesigned to be the same or almost the same, such that the time for manufacturing the light shielding layer5matches that of the low hydrogen layer6, which enhances whole production. Meanwhile, the type and sequence of films could be reasonably chosen according to the material property of the film, thusly optimizing the capacity and quality of the TFT array substrate.

In an embodiment of the present disclosure, the thickness of the silicon oxide layer61is 2 times larger than that of the low hydrogen poly-Si layer62of the low hydrogen layer6.

In an embodiment of the present disclosure, the thickness of each film may be designed depending on requirement, for example, the thickness of the amorphous silicon light shielding layer52of the light shielding layer5is 60-100 nm, the thickness of the silicon nitride layer51is 50-100 nm, the thickness of the silicon oxide layer61is 200-400 nm, and the thickness of the low hydrogen poly-Si layer62of the low hydrogen layer6is 30-60 nm.

A Manufacturing Method of the TFT Array Substrate

The manufacturing method of the TFT array substrate comprises the following steps:

S1: providing a base4, such as glass base. The glass base, for example, has the following properties: high transparency, low reflectivity, good thermal stability, corrosion resistance, electric insulation, mechanical strength and mechanical processing characteristic. The glass base is cleaned, for example, by initial cleaning process.

S2: forming a light shielding layer5on the base4.

For example, the step of forming a light shielding layer5on the base4comprises the steps of forming a silicon nitride layer51on the base4; and forming an amorphous silicon light shielding layer51on the silicon nitride layer51.

the light shielding layer5comprises a silicon nitride layer51and an amorphous silicon light shielding layer52formed on the silicon nitride layer51. The silicon nitride layer51may be used as a buffer layer, which is capable of inhibiting effect resulted by the harmful substance in the glass base, such as metal ions.

In an embodiment, conducting an annealing process after finishing the silicon nitride layer so as to optimize the quality of the buffer layer. And then depositing the amorphous silicon light shielding layer52on the silicon nitride layer51. The silicon nitride layer51cooperates with the amorphous silicon light shielding layer52in the Step S2to constitute the light shielding layer5.

S3: forming a low hydrogen layer6on the light shielding layer5.

For example, the step of forming a low hydrogen layer on the light shielding layer5comprises the steps of forming a silicon oxide layer61on the amorphous silicon light shielding layer52of the light shielding layer5; and forming an amorphous silicon low hydrogen layer on the silicon oxide layer.

forming a silicon oxide layer61on the amorphous silicon light shielding layer52of the light shielding layer5for example by a manner of PECVD For example, the layer of amorphous silicon may be treated with a dehydrogenation such as being treated in a high temperature oven so as to form a low hydrogen amorphous silicon layer.

conducing a crystallization process to the amorphous silicon low hydrogen layer. For example, treating a crystallization process to the amorphous silicon low hydrogen layer to form a low hydrogen poly-Si layer62in a manner of crystallization treatment, such as Excimer Laser Annealing (ELA), Metal Induced Crystallization (MIC), or Solid phase Crystallization (SPC).

Furthermore, after the crystallization, cleaning the layer of poly-Si film by Dimethyl dihydroxyfumarate (DHF) with a concentration of 1-20%, so as to reduce the surface roughness of the layer of poly-Si film, and remove gauffer or protrusion brought about by crystallization, thusly enabling the layer of poly-Si film to contact with the succedent films well, and thereby promoting the performance of the whole device.

The silicon oxide layer61cooperates with the low hydrogen poly-Si layer62of the low hydrogen layer6to constitute the low hydrogen layer6.

In an embodiment, the manufacturing method further comprises a step of patterning the low hydrogen poly-Si layer62of the low hydrogen layer6to form a pattern. Furthermore, the pattern of the low hydrogen poly-Si layer62of the low hydrogen layer6is located above the amorphous silicon light shielding layer52.

A TFT array substrate can be obtained by forming gate electrode, drain electrode and source electrode and so on based on the TFT array substrate according to the present disclosure.

Based on the technical solutions of the present disclosure, some advantageous effects of the TFT array substrate according to the present disclosure may include the following:

In the present disclosure, the light shielding layer comprises two layers of films, i.e. a silicon nitride layer and an amorphous silicon light shielding layer; and the low hydrogen layer comprises two layers of films, i.e. a silicon oxide layer and a low hydrogen polysilicon layer, that is to say, the layer number of the light shielding layer is equal to the layer number of the low hydrogen layer, therefore, the time of manufacturing the light shielding layer is almost equal to that of manufacturing the low hydrogen layer, which production capacity of the light shielding layer matches that of the low hydrogen layer, and enhances whole capacity of the TFT array substrate dramatically, which lower risk of the manufacturing process.

Compared with the prior art, the TFT array substrate according to the present disclosure may reduce the layer number of the low hydrogen layer, thusly allowing to easily control the temperature of each film in the low hydrogen layer to be uniformity, decrease stress of each film in the low hydrogen layer, and lower probability of film stripping or peeling.

In the present disclosure, the silicon oxide layer with a relative larger thickness is located under the amorphous silicon low hydrogen layer, which is able to reduce heat conduction in the subsequent excimer laser annealing process, and moderate cooling rate of Si heated by laser, and is helpful to form relative larger poly-Si grains. Moreover, the silicon oxide layer with a relative larger thickness is located above the silicon nitride layer at the lowest layer, which provides a second protection for the poly-Si, and blocks the metal ions in the glass base diffusing into the poly-Si, and thereby rendering a more stable convergence.

The stress of the silicon nitride is larger than that of the silicon oxide. In the present disclosure, the silicon nitride layer is located under the silicon oxide layer, i.e, the film with the largest stress is provided at the lowest layer to connect with the base, and amorphous silicon light shielding layer of the light shielding layer is located above the silicon nitride layer, which is capable of increasing connection strength between each layer and effectively preventing film stripping.

the silicon nitride layer is located above the base, which may directly block ions in the base, such as Na, K, P and so on during a high temperature process of Low Temperature poly-Si (LTPS), without effecting the uniformity and pureness of the light shielding layer, and the quality of the amorphous silicon light shielding layer of the light shielding layer, thereby optimizing the characterize of the TFT array substrate. Meanwhile, the light shielding layer is prevented from electrostatic damage because the silicon nitride is provided on the base.

It should be noted that the above embodiments are only illustrated for describing the technical solution of the disclosure and not restrictive. On the contrary, the present disclosure intends to encompass such changes and modifications provided that those changes and modifications fall within the scope of claims of the present invention and equivalents thereof.