Active device and fabricating method thereof

An active device and a fabricating method thereof are provided. The active device includes a buffer layer, a channel, a gate, a gate insulation layer, a source and a drain. The buffer layer is disposed on a substrate and has a positioning region. A thickness of a portion of the buffer layer in the positioning region is greater than a thickness of a portion of the buffer layer outside the positioning region. The channel is disposed on the buffer layer and in the positioning region. The gate is disposed above the channel. The gate insulation layer is disposed between the channel and the gate. The source and the drain are disposed above the channel and electrically connected to the channel.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an active device and a fabricating method thereof.

2. Description of Related Art

A thin film transistor liquid crystal display (TFT LCD) panel mainly consists of an active device array structure, a color filter array structure and a liquid crystal layer. The active device array structure includes multiple active devices arranged in array, i.e. an array of thin film transistors (TFTs), and a pixel electrode disposed in correspondence with each TFT. The TFT includes a gate, a channel, a drain and a source. The TFT serves as a switch element for a liquid crystal display unit.

An oxide semiconductor is a common material for fabricating the TFT. When the oxide semiconductor TFT is used as the switch element for the liquid crystal display unit, because the channel of the oxide semiconductor material has a high light transmittance, there has been an alignment difficulty in stacking other materials in subsequent processes. Although increasing the thickness of the channel of the oxide semiconductor material may decrease its light transmittance, it causes a threshold voltage shift of the channel. Therefore, when the oxide semiconductor TFT is used as the switch element, it is desired to achieve high alignment accuracy in the process without increasing the thickness of the oxide semiconductor.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to an active device having a buffer layer with a positioning region, and a channel disposed in the positioning region and a portion of the buffer layer in the positioning region can serve as a positioning mark used in the fabrication process of the active device.

The present invention is also directed to a method for fabricating an active device. The active device has a buffer layer with a positioning region. A channel disposed in the positioning region and a portion of the buffer layer in the positioning region can facilitate alignment in subsequent processes.

The present invention provides an active device including a buffer layer, a channel, a gate, a gate insulation layer, a source and a drain. The buffer layer is disposed on a substrate and has a positioning region. A thickness of a portion of the buffer layer in the positioning region is greater than a thickness of a portion of the buffer layer outside the positioning region. The channel is disposed on the buffer layer and in the positioning region. The gate is disposed above the channel. The gate insulation layer is disposed between the channel and the gate. The source and the drain are disposed above the channel and electrically connected with the channel.

In one embodiment, the thickness of the portion of the buffer layer in the positioning region is X1, the thickness of the portion of the buffer layer outside the positioning region is X2, the thickness of the channel is Y, and the result of subtracting X2 from the sum of X1 and Y is equal to or greater than 40 or 60 nanometers. In addition, the result of subtracting X2 from X1 is, for example, equal to or greater than 20 nanometers.

In one embodiment, the thickness of the channel is equal to or less than 70 or 120 nanometers.

In one embodiment, the material of the buffer layer is silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride-oxide (SiON), silicon carbide (SiC), silicon carbonitride (SiCN) or aluminum oxide (AlO).

In one embodiment, the active device further includes a first insulation layer covering the gate and the gate insulation layer. The source and the drain are disposed on the first insulation layer, and the source and the drain pass through the first insulation layer and the gate insulation layer to be electrically connected with the channel.

In one embodiment, the material of the channel is an oxide semiconductor.

In one embodiment, the gate insulation layer includes a primary insulation layer and a secondary insulation layer. The primary insulation layer covers the channel and the buffer layer, and the secondary insulation layer covers the channel.

In one embodiment, the thickness of the secondary insulation layer is equal to or greater than 20 nanometers. The thickness of the secondary insulation layer is, for example, X3, the thickness of the portion of the buffer layer in the positioning region is X1, and the sum of X3 and X1 is equal to or greater than 20 nanometers. Alternatively, the thickness of the secondary insulation layer is, for example, X3, the thickness of the portion of the buffer layer in the positioning region is X1, the thickness of the portion of the buffer layer outside the positioning region is X2, and the result of subtracting X2 from the sum of X3 and X1 is equal to or greater than 20 nanometers.

The present invention provides a method for fabricating an active device. In this method, a buffer layer is first formed on a substrate. A channel material layer is then formed on the buffer layer, and this channel material layer is patterned to form a channel later. The buffer layer has a positioning region, and a thickness of a portion of the buffer layer in the positioning region is greater than a thickness of a portion of the buffer layer outside the positioning region. The channel is disposed on the buffer layer and in the positioning region. After the channel and the buffer layer with two thicknesses, a gate insulation layer is then formed on the channel. A gate is then formed on the gate insulation layer, with the channel and the portion of the buffer layer below the channel being used as an alignment mark. Finally, a source and a drain are formed which are above the channel and electrically connected to the channel.

In one embodiment of the fabricating method of the active device, the step of forming the channel includes patterning the channel material layer to form the channel, and thinning the portion of the buffer layer that is not covered by the channel, such that the thickness of the portion of the buffer layer below the channel is greater than the thickness of the portion of the buffer layer that is not covered by the channel.

In one embodiment of the fabricating method of the active device, the method of forming the channel and thinning the portion of the buffer layer that is not covered by the channel include the following steps. An etch mask is formed on a region of the channel material layer where the channel is to be formed. The portion of the channel material layer that is not covered by the etch mask is etched to form the channel, and then the portion of the buffer layer that is not covered by the channel is etched. Finally, the etch mask is removed.

In one embodiment of the fabricating method of the active device, the step of forming the channel includes patterning the channel material layer and the buffer layer simultaneously to form the channel layer and the buffer layer having two thicknesses.

In one embodiment of the fabricating method of the active device, the method further includes, after the gate is formed and before the source and the drain are formed, forming a first insulation layer to cover the gate and the gate insulation layer, with the source and the drain passing through the first insulation layer and the gate insulation layer to be electrically connected with the channel.

The present invention provides another active device including a channel, a gate, a gate insulation layer, a source and a drain. The channel is disposed on a substrate. The gate is disposed above the channel. The gate insulation layer includes a primary insulation layer and a secondary insulation layer, and is disposed between the channel and the gate. The source and the drain are disposed above the channel and electrically connected to the channel.

In one embodiment, the primary insulation layer covers the channel and the substrate, and the secondary insulation layer covers the channel.

In one embodiment, the thickness of the secondary insulation layer of the active device is equal to or greater than 20 nanometers.

In one embodiment, the active device further includes a buffer layer disposed on the substrate. The channel is disposed on the buffer layer. In addition, the buffer layer, for example, has a positioning region. The channel is located in the positioning region. A thickness of a portion of the buffer layer in the positioning region is greater than a thickness of a portion of the buffer layer outside the positioning region.

In one embodiment, the thickness of the portion of the buffer layer in the positioning region is, for example, X1, the thickness of the portion of the buffer layer outside the positioning region is X2, the thickness of the channel is Y, and the result of subtracting X2 from the sum of X1 and Y is equal to or greater than 40 or 60 nanometers. In addition, the result of subtracting X2 from X1 is, for example, equal to or greater than 20 nanometers.

In one embodiment, the thickness of the secondary insulation layer is X3, the thickness of the portion of the buffer layer in the positioning region is X1, and the sum of X3 and X1 is equal to or greater than 20 nanometers. Alternatively, the thickness of the secondary insulation layer is, for example, X3, the thickness of the portion of the buffer layer in the positioning region is X1, the thickness of the portion of the buffer layer outside the positioning region is X2, and the result of subtracting X2 from the sum of X3 and X1 is equal to or greater than 20 nanometers.

In one embodiment, the material of the buffer layer is silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride-oxide (SiON), silicon carbide (SiC), silicon carbonitride (SiCN) or aluminum oxide (AlO).

In one embodiment, the thickness of the channel is equal to or less than 70 or 120 nanometers.

In one embodiment, the active device further includes a first insulation layer covering the gate. The source and the drain are disposed on the first insulation layer, and the source and the drain pass through the first insulation layer to be electrically connected with the channel.

In one embodiment, the material of the channel is an oxide semiconductor.

The present invention provides another method for fabricating an active device. In this method, a channel material layer and an insulation photoresist material layer are first formed on a substrate in sequence. Then, the insulation photoresist material layer is patterned to form a secondary insulation layer. Afterward, the channel material layer is patterned to form a channel by using the secondary insulation layer as a mask. Then, a primary insulation layer is formed to cover the secondary insulation layer and the substrate. In particular, the primary insulation layer and the secondary insulation layer constitute a gate insulation layer. Then, a gate is formed on the gate insulation layer, with the channel and the secondary insulation layer being used as an alignment mark. Thereafter, a source and a drain are formed which are above the channel and electrically connected to the channel.

In one embodiment of the fabricating method of the active device, the method further includes forming a buffer layer before the channel material layer is formed.

In one embodiment of the fabricating method of the active device, the method further includes, after the channel is formed and before the primary insulation layer is formed, thinning the portion of the buffer layer that is not covered by the channel, such that the thickness of the portion of the buffer layer below the channel is greater than the thickness of the portion of the buffer layer that is not covered by the channel. In addition, the steps of forming the channel and thinning the buffer layer are, for example, completed simultaneously by using the secondary insulation layer as a mask.

In one embodiment of the fabricating method of the active device, the method further includes, after the gate is formed and before the source and the drain are formed, forming a first insulation layer to cover the gate, with the source and the drain passing through the first insulation layer to be electrically connected with the channel.

In view of the foregoing, in the present active device and the fabricating method thereof, the thickness of the portion of the buffer layer below the channel is greater than the thickness of the rest part of the buffer layer. Therefore, the channel and the buffer layer below the channel can serve as an alignment mark used in the fabrication process. In addition, when the gate insulation layer includes the secondary insulation layer, a relatively flat surface can be obtained to avoid plasma damage.

In order to make the aforementioned features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1AtoFIG. 1Iare cross-sectional views illustrating a flow of a method for manufacturing an active device according to one embodiment of the present invention. Referring first toFIG. 1A, a substrate101is provided, which is, for example, a glass substrate or a plastic substrate. A buffer layer110is then formed on the substrate101. Referring toFIG. 1B, a channel material layer120′ is then formed on the buffer layer110. The buffer layer110can prevent impurities in the substrate101from diffusing into the channel material layer120′ which would contaminate the channel material layer120′ or even further affect the electricity of the active device100when driven. In addition, since the buffer layer110covers the entire substrate101, the buffer layer110can also suppress the degree of warp of the substrate101.

Referring toFIG. 1C, the channel material layer120′ may be patterned to form a channel120after the buffer layer110and the channel material layer120′ are formed on the substrate101. The buffer layer110includes a positioning region110a, and a thickness of the portion of the buffer layer110in the positioning region110ais greater than a thickness of the portion of the buffer layer110outside the positioning region110a. The channel120formed from the channel material layer120′ is disposed on the buffer layer110and located in the positioning region110a.

Referring toFIG. 1D, after the channel120and the buffer layer110with two thicknesses are formed, a gate insulation layer130is formed over the channel120. The gate insulation layer130has insulation result and can isolate the channel120from a gate140to be formed later (shown inFIG. 1E). The method for forming the gate insulation layer130may be, but not limited to, chemical vapor deposition (CVD). The gate insulation layer130may also be formed using other methods, such as, screen printing, coating, ink-jetting, energy source processing, or the like. The present invention has no limits as to the formation of the gate insulation layer130.

Referring toFIG. 1E, a gate140is formed on the gate insulation layer130. In comparison with the buffer layer110outside the positioning region110a, the stacked channel120in the positioning region110aand the buffer layer110in the positioning region110ahave a relatively greater thickness and therefore has a different light transmittance than that of the buffer layer110outside the positioning region110a. In forming the gate140on the gate insulation layer130, the channel120and the portion of the buffer layer110below the channel120may serve as an alignment mark by taking advantage of this difference in light transmittance. In other words, in forming the gate140in the subsequent process, alignment of the gate140can be achieved without using additional alignment pattern.

Referring toFIG. 1F, after the gate140is formed, a first insulation layer150is then formed. The first insulation layer150covers both the gate140and the gate insulation layer130. Referring again toFIG. 1G, a source160and a drain170are formed above the channel120and are electrically connected with the channel120. The source160and the drain170are spaced a distance and pass through the first insulation layer150and the gate insulation layer130to be electrically connected with the channel120therebelow. The active device of this embodiment is thus generally accomplished. Discussed below are some other optional steps.

Referring toFIG. 1H, after the source160and the drain170are formed, a second insulation layer180is then formed to cover the source160and the drain170. Referring toFIG. 1I, a pixel electrode190is formed on the second insulation layer180, and the pixel electrode190and the drain170are electrically connected.

FIG. 2AtoFIG. 2Fare cross-sectional views illustrating the flow of the method of fabricating the channel and the buffer layer ofFIG. 1C. Referring toFIG. 2AandFIG. 2B, after obtaining the semi-finished product shown inFIG. 1B, a photoresist material layer102may be coated on the channel material layer120′ using a coating method such as spin coating or slot die coating, such that the photoresist material layer102covers the channel material layer120′.

Referring toFIG. 2C, the photoresist material layer102is exposed to an ultraviolet light103through a photo mask104. The design of the pattern (distribution of the shielding region and the transparent region) of the photo mask104may vary according to photosensitivity of the photoresist material layer102. For example, the pattern design of the photo mask104for the photoresist material layer102having a positive photosensitivity is inverted with respect to the mask pattern design for the photoresist material layer102having a negative photosensitivity.

Referring toFIG. 2CandFIG. 2D, a development step is executed using a developing solution such that part of the photoresist material layer102is removed. In the present embodiment, the photoresist material used has a positive photosensitivity. Therefore, the exposed part of the photoresist material layer102is dissolved in the developing solution so as to be removed and the rest part remains on the channel material layer120′ to form an etch mask105in the region where the channel120is to be formed.

Referring toFIG. 2E, after the etch mask105is formed, an etch operation may be performed on the underlying channel material layer120′ and the buffer layer110through the etch mask105. Notably, etch can be performed in two manners. The first manner is layered etch. The part of the channel material layer120′ that is not covered by the etch mask105is etched to form the channel120. After the channel120is formed, a second etch is performed to remove the part of the buffer layer110that is not covered by the etch mask105. In the second manner, the channel material layer120′ and the buffer layer110are patterned simultaneously to form the channel120and the buffer layer110having two thicknesses. At the step shown inFIG. 2E, the channel material layer120′ is etched to form the channel120, and the buffer layer110that originally had a uniform thickness is etched to have two portions with different thicknesses. The thickness of the portion of the buffer layer110in the positioning region110ais greater than the thickness of the portion of the buffer layer110outside the positioning region110a.

Referring toFIG. 2F, finally, the etch mask105disposed on and contacting the channel120shown inFIG. 2Eis removed, and a structure on the substrate101that includes the buffer layer110with the positioning region110aand the channel120is thus obtained. This structure may serve as the alignment mark for the formation of the gate140in a subsequent process.

In addition, inFIG. 1E,FIG. 1GandFIG. 1I, the gate140, source160, drain170and pixel electrode190are likewise formed using a photo process similar to that illustrated inFIG. 2AtoFIG. 2F. The only difference is that the pattern of the photo mask104used inFIG. 2Cneeds to change according to the desired shape of the gate140, source160, drain170and pixel electrode190. Therefore, further explanation of the photo process is not repeated herein.

FIG. 1Iillustrates an active device according to one embodiment of the present invention. Referring toFIG. 1I, the active device100includes a buffer layer110, a channel120, a gate140, a gate insulation layer130, a source160and a drain170. The buffer layer110is disposed on a substrate101. The buffer layer110has a positioning region110a. A thickness of a portion of the buffer layer110in the positioning region110ais greater than a thickness of a portion of the buffer layer110outside the positioning region110a. The channel120is disposed on the buffer layer110and in the positioning region110a. The gate140is disposed above the channel120. A gate insulation layer130is disposed between the channel120and the gate140. The source160and the drain170are disposed above the channel120and electrically connected with the channel120.

In the active device100of the present embodiment, the buffer layer110and the channel120in the positioning region110acan collectively serve as a positioning mark. Therefore, even if the thickness of the channel120is controlled to be less than 70 or 120 nanometers, it would not cause the alignment difficulty in subsequent processes due to the over-thin thickness. In addition, when the material of the channel120is an oxide semiconductor, controlling the channel120to have a suitable thickness can also avoid the threshold voltage shift issue of the channel120.

The thickness of the portion of the buffer layer110in the positioning region110ais X1, the thickness of the portion of the buffer layer110outside the positioning region110ais X2, and the thickness of the channel120is Y. The result of subtracting X2 from the sum of X1 and Y is equal to or greater than 40 or 60 nanometers. In other words, the sum of the thickness of the portion of the buffer layer110in the positioning region110aand the thickness of the channel120must be greater than the thickness of the portion of the buffer layer110outside the positioning region110a, such that the light transmittance of the positioning region110aand the light transmittance of the portion outside the positioning region110ahave a sufficient difference for the fabrication equipment to identify to achieve the positioning result. In addition, the result of subtracting X2 from X1 is, for example, equal to or greater than 20 nanometers, such that the thickness of the portion of the buffer layer110in the positioning region110ais significantly different from the thickness of the portion of the buffer layer110outside the positioning region110a. The thickness of the channel120can be equal to or less than 70 nanometers. The material of the buffer layer110is an insulation material, for example, a metal oxide material such as, silicon oxide (SiOx), silicon nitride (SiNx), silicon nitride-oxide (SiON), silicon carbide (SiC), silicon carbonitride (SiCN) or aluminum oxide (AlO). The material of the channel120may be an oxide semiconductor, such as, indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO), tin oxide (SnO), indium-zinc oxide (IZO), gallium-zinc oxide (GZO), zinc-tin oxide (ZTO), indium-gallium oxide (IGO), indium-tin-zinc oxide (ITZO), or indium-tin oxide (ITO).

As shown inFIG. 1I, the active device100of the present embodiment further includes a first insulation layer150. The first insulation layer150covers the gate140and the gate insulation layer130. The source160and the drain170are disposed on the first insulation layer150, and the source160and the drain170pass through the first insulation layer150and the gate insulation layer130to be electrically connected with the channel120.

The material of the gate140, source160and drain170may be a metal such as aluminum (Al), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), gold (Au) or silver (Ag) or any alloy thereof, an alloy such as Al—Nd, APC, or a conductive metal oxide such as tin oxide (SnO), zinc oxide (ZnO), indium oxide, indium-tin oxide (ITO) or indium-zinc oxide (IZO). It is noted, however, the present invention is not intended to limit the material of the gate140, source160and drain170to any particular material.

Referring toFIG. 1I, the active device100of the present embodiment may further include a second insulation layer180and a pixel electrode190. The material of the pixel electrode190may be, for example, indium-tin oxide (ITO) or aluminum zinc oxide (AZO). It is noted, however, that the present invention is not intended to limit the material of the pixel electrode190to any particular material.

Additional embodiments are discussed below. It should be mentioned that, the embodiments below use the same device labels and portions of the content from previous embodiments. Specifically, the same labels are used to represent the same or similar devices, and the descriptions for the same techniques are omitted. The omitted portions have been discussed in the previous embodiments, and are not repeated herein.

FIG. 3is an active device according to another embodiment of the present invention. Referring toFIG. 3, the gate insulation layer130of the active device300of the present embodiment includes a primary insulation layer132and a secondary insulation layer134. The primary insulation layer132covers the channel120and the buffer layer110, and the secondary insulation layer134covers the channel120. The material of the secondary insulation layer134of the present embodiment is exemplified by a photoresist material, and the secondary insulation layer134can be used as an etch mask to define the channel120and the positioning region110aof the buffer layer110. The secondary insulation layer134can further differentiate the light transmittance between the positioning region110aand the area outside the positioning region110a, and be used as an alignment pattern to form the gate140in a subsequent process. In addition, the present embodiment is exemplified by the secondary insulation layer134completely covering the channel120, but the secondary insulation layer134can also cover the portion of the buffer layer110outside the positioning region110a. The configuration of the secondary insulation layer134makes the interface between the secondary insulation layer134and the channel120relatively flat. In addition, when the secondary insulation layer134is made of a photoresist material, plasma damage to the surface of the channel120can be avoided. When the material of the secondary insulation layer134is an inorganic material, since the film thickness of the secondary insulation layer134is less than the film thickness of the primary insulation layer132, the degree of plasma damage can still be lowered when the channel120directly covers the primary insulation layer132.

In one embodiment, the thickness of the secondary insulation layer134is equal to or greater than 20 nanometers. In addition, the thickness of the secondary insulation layer134is, for example, X3, the thickness of the portion of the buffer layer110in the positioning region110ais X1, and the sum of X3 and X1 is equal to or greater than 20 nanometers. Alternatively, the thickness of the secondary insulation layer134is, for example, X3, the thickness of the portion of the buffer layer110in the positioning region110ais X1, the thickness of the portion of the buffer layer110outside the positioning region110ais X2, and the result of subtracting X2 from the sum of X3 and X1 is equal to or greater than 20 nanometers. The material of the secondary insulation layer134can also be an inorganic thin film, for example, an insulation material such as silicon oxide (SiOx), silicon nitride (SiNx) or aluminum oxide (AlOx). The primary insulation layer132can also be an inorganic thin film. The material of the primary insulation layer132and the secondary insulation layer134can be the same or different.

FIG. 4is an active device according to yet another embodiment of the present invention. Referring toFIG. 4, the active device400of the present embodiment is similar to the active device300ofFIG. 3, with the difference being that the active device400of the present embodiment does not have a buffer layer. Although the buffer layer110ofFIG. 3is absent, the secondary insulation layer134of the gate insulation layer130can still be used as an alignment pattern to form the gate140in a subsequent process. In addition, the secondary insulation layer134can be used as an etch mask to define the channel120.

FIG. 5AtoFIG. 5Fare cross-sectional views illustrating the flow of the method for manufacturing an active device according to another embodiment of the present invention. Referring toFIG. 5A, in the method of the present embodiment for fabricating an active device, a buffer layer110is first optionally formed on a substrate101. Then, a channel material layer120′ and an insulation photoresist material layer134′ are formed on the buffer layer110in sequence.

Then, referring toFIG. 5AandFIG. 5B, the insulation photoresist material layer134′ is patterned to form a secondary insulation layer134, and a channel120is formed by patterning the channel material layer120′ and by using the secondary insulation layer134as a mask. Since the insulation photoresist material layer134′ is itself a photoresist material, when the insulation photoresist material layer134′ is patterned, the development of the insulation photoresist material layer134′ via exposure can be completed using only a photo mask. Later, when the channel material layer120′ is patterned, a photo mask will no longer be needed.

Then, referring toFIG. 5C, a primary insulation layer132is formed to cover the secondary insulation layer134, buffer layer110, and substrate101. In particular, the primary insulation layer132and the secondary insulation layer134constitute a gate insulation layer130.

Then, referring toFIG. 5D, a gate material layer140′ is formed on the gate insulation layer130.

Then, referring toFIG. 5E, a gate140is formed on the gate insulation layer130, with the channel120and the secondary insulation layer134being used as an alignment mark. In addition, after the gate140is formed, by optionally using the gate140as an etch mask, the portion of the gate insulation layer130not covered by the gate140can be etched to expose a portion of the channel120.

Next, referring toFIG. 5F, a first insulation layer150is optionally formed to cover the gate140. If the portion of the gate insulation layer130not covered by the gate140was not removed in the previous step, then the first insulation layer150also covers the gate insulation layer130. Then, a source160and a drain170are formed on the first insulation layer150above the channel120, and the source160and the drain170pass through the first insulation layer150to be electrically connected with the channel120.

FIG. 6andFIG. 7are cross-sectional views illustrating steps for forming a channel in the method for manufacturing an active device according to two other embodiments of the present invention. Referring toFIG. 6, in the method of the present embodiment for fabricating an active device, when the channel120is formed by using the secondary insulation layer134as a mask, the portion of the buffer layer110not covered by the channel120can be removed at the same time to expose the substrate101. Then, the subsequent steps of, for example,FIG. 5CtoFIG. 5Fare performed. Next, referring toFIG. 7, in the method of the present embodiment for fabricating an active device, when the channel is formed by using the secondary insulation layer134as a mask, the portion of the buffer layer110not covered by the channel120can be thinned at the same time, such that the thickness of the portion of the buffer layer110below the channel120is greater than the thickness of the portion of the buffer layer110not covered by the channel120. Then, the subsequent steps of, for example,FIG. 5CtoFIG. 5Fare performed.

In summary, in the active device of the present invention, the stacked structure itself can serve as a positioning mark for use in the fabricating process of the active device. This positioning mark consists of the buffer layer and the channel in the positioning region. The thickness of the stacked buffer layer and channel in the positioning region is greater than the thickness of the portion of the buffer layer outside the positioning region. Therefore, the stacked buffer layer and channel in the positioning region and the buffer layer outside the positioning region have different light transmittance. The stacked structure may serve as the positioning mark for use in subsequent processes by taking advantage of the difference in light transmittance.