Solid-state imaging device

A solid-state imaging device comprises a photodetecting section, an unnecessary carrier capture section, and a vertical shift register. The unnecessary carrier capture section has carrier capture regions arranged in a region between the photodetecting section and the vertical shift register for respective rows. Each of the carrier capture regions includes a transistor and a photodiode. The transistor has one terminal connected to the photodiode and the other terminal connected to a charge elimination line. The charge elimination line is short-circuited to a reference potential line.

TECHNICAL FIELD

The present invention relates to a solid-state imaging device.

BACKGROUND ART

Patent Literature 1 describes a technique concerning a radiation imaging device. The device comprises a sensor array constructed by two-dimensionally arraying a plurality of pixels each including a conversion element for converting a radiation from an object into an electric signal and a transfer switch for transferring the electric signal to the outside. The device also comprises a plurality of gate lines connecting the pixels of the sensor array in the row direction, a gate drive device for driving the gate lines in order to read out the electric signals of the pixels connected to each gate line, a plurality of signal lines for connecting the pixels of the sensor array in the column direction, and a plurality of amplifiers, provided so as to correspond to the respective signal lines, for amplifying and reading out the electric signals transferred from the respective transfer switches.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

A solid-state imaging device has a photodetecting section in which a plurality of pixels are arrayed two-dimensionally over a plurality of rows and a plurality of columns. A photodiode for converting light incident thereon into an electron is arranged in each pixel. The photodiodes of the pixels are connected through switch circuits (e.g., transistors) to a readout line provided for each column, while the charges accumulated within the photodiode flow out to the readout line when the switch circuit is turned on. The charges reach an integration circuit through the readout line and are converted into a voltage signal in the integration circuit. A control terminal (e.g., gate terminal) for controlling the conduction state of the switch circuit in each pixel is connected to a row selection line provided for each row. A signal from a shift register is supplied to the control terminal of each switch circuit through the row selection line, whereby the charges are read out from the pixels for each row.

In the solid-state imaging device having such a configuration, light is incident on not only the photodetecting section but its surrounding regions as well. When the regions surrounding the photodetecting section are covered with a scintillator in the case where the solid-state imaging device is used as an X-ray imaging device, for example, X-rays transmitted through the scintillator and scintillation light from the scintillator are incident on the regions surrounding the photodetecting section. This generates unnecessary charges (carriers) in the regions surrounding the photodetecting section. Since the shift register juxtaposed with the photodetecting section has a substantial area, a large number of unnecessary carriers occur in the region formed with the shift register in particular.

When unnecessary carriers generated in the shift register flow into the photodetecting section, noise is superimposed on outputs from pixels adjacent to the shift register. For avoiding such a phenomenon, a photodiode (dummy photodiode) for absorbing unnecessary carriers may be arranged in a region between the shift register and photodetecting section and short-circuited to a reference potential line (grounding line).

However, the following problem exists in this scheme. Typically, between pixels adjacent to each other in the photodetecting section, crosstalk exists because of coupling capacitance occurring between their photodiodes and the like. In each pixel, parasitic capacitance also exists between the photodiode and row selection line connected to each other through the switch circuit and also affects the crosstalk. However, the above-described dummy photodiode is provided with no switch circuit and thus does not generate such parasitic capacitance. Therefore, pixels adjacent to the dummy photodiode have different degrees of crosstalk as compared with other pixels, whereby output characteristics and magnitudes of noise from pixels adjacent to the dummy photodiode differ from those of the other pixels.

In view of the above problem, it is an object of the present invention to provide a solid-state imaging device which enables pixels adjacent to a dummy photodiode to have output characteristics and magnitudes of noise closer to those of the other pixels.

Solution to Problem

In order to solve the above-described problem, the solid-state imaging device in accordance with the present invention comprises a photodetecting section having M×N pixels (each of M and N being an integer of 2 or more), each including a first photodiode and a first switch circuit having one terminal connected to the first photodiode, two-dimensionally arrayed in M rows and N columns; N readout lines provided for the respective columns and connected to the other terminals of the first switch circuits included in the pixels of the corresponding columns; a readout circuit section connected to the N readout lines; a shift register, juxtaposed with the photodetecting section in a row direction, for controlling an open/closed state of the first switch circuits for each row; M dummy photodiodes arranged in a region between the shift register and the photodetecting section for the respective rows; M second switch circuits having respective one terminals connected to the M dummy photodiodes; and a charge elimination line connected to the other terminals of the M second switch circuits and short-circuited to a reference potential line.

In this solid-state imaging device, M dummy photodiodes are arranged for the respective rows in a region between a shift register and a photodetecting section. Unnecessary carriers occurring in the shift register are absorbed by the dummy photodiodes. This can effectively prevent noise caused by unnecessary carriers generated in the shift register from being superimposed on outputs from pixels in the photodetecting section.

In the solid-state imaging device, the dummy photodiode and a charge elimination line are connected to each other through a second switch circuit, and when the second switch circuit is turned on, unnecessary carriers are discharged from the dummy photodiode to a reference potential line through the charge elimination line. Thus, in the above-described solid-state imaging device, the dummy photodiode is provided with the second switch circuit as with the first switch circuit in each pixel in the photodetecting section. Therefore, the above solid-state imaging device enables pixels adjacent to the dummy photodiode to have crosstalk with a magnitude close to that of crosstalk in other pixels, thereby making it possible for pixels adjacent to the dummy photodiode to have output characteristics and magnitudes of noise closer to those of the other pixels.

Advantageous Effects of Invention

The solid-state imaging device in accordance with the present invention enables pixels adjacent to a dummy photodiode to have output characteristics and magnitudes of noise closer to those of the other pixels.

DESCRIPTION OF EMBODIMENTS

An embodiment of the solid-state imaging device in accordance with the present invention will be described below in detail with reference to the accompanying drawings. In the explanation of the drawings, the same elements will be denoted by the same reference signs, while omitting their overlapping descriptions.

The solid-state imaging device in accordance with an embodiment is used for a medical X-ray imaging system, for example.FIG. 1andFIG. 2are diagrams illustrating a configuration of a solid-state imaging device1A in this embodiment.FIG. 1is a plan view illustrating the solid-state imaging device1A, whileFIG. 2is a plan view enlarging a part of the solid-state imaging device1A.FIG. 1andFIG. 2also depict an XYZ orthogonal coordinate system for easier understanding.

As illustrated inFIG. 1, the solid-state imaging device1A comprises a photodetecting section20, an unnecessary carrier capture section30, a readout circuit section40, and a vertical shift register60. The photodetecting section20, unnecessary carrier capture section30, readout circuit section40, and vertical shift register60are formed on a principal surface of a substrate12. The vertical shift register60is juxtaposed with the photodetecting section20in the X-axis direction. A part of the unnecessary carrier capture section30is arranged in a region between the photodetecting section20and the vertical shift register60, while the remaining part of the unnecessary carrier capture section30is juxtaposed with the photodetecting section20in the Y-axis direction and located in a region between the photodetecting section20and readout circuit section40.

The readout circuit section40includes a plurality of integration circuits provided so as to correspond to respective columns of the photodetecting section20, while the integration circuits respectively generate voltage values corresponding to amounts of charges output from the pixels in the corresponding columns. The readout circuit section40holds the voltage values output from the respective integration circuits and successively outputs the held voltage values.

The photodetecting section20is constructed by two-dimensionally arranging a plurality of pixels P1,1to PM,Nover M rows and N columns (where each of M and N is an integer of 2 or more).FIG. 2depicts four pixels Pm,N−1, Pm,N, Pm+1,N−1, Pm+1,Nas representative of the plurality of pixels P1,1to PM,N. For example, the pixel Pm,Nis the one located on the m-th row and the N-th column (where m is an integer of 1 or more and M or less). InFIG. 1andFIG. 2, the column direction coincides with the Y-axis direction, and the row direction coincides with the X-axis direction.

Each of the pixels P1,1to PM,Nincluded in the photodetecting section20comprises a transistor21and a photodiode22. Each of the transistors21in the pixels P1,1to PM,Nis a first switch circuit in this embodiment. The transistor21is preferably constituted by a field-effect transistor (FET) but may also be constituted by a bipolar transistor. The following explanation will assume the transistor21to be an FET. In this case, by control terminal is meant a gate. When the transistor21is a bipolar transistor, by control terminal is meant a base.

Each of the photodiodes22in the pixels P1,1to PM,Nis a first photodiode in this embodiment. The photodiode22, which is constituted by a semiconductor region including a p-n junction or p-i-n junction, generates charges by an amount corresponding to the intensity of light incident thereon and accumulates thus generated charges in a junction capacitance part. The transistor21has one terminal (e.g., a source region) electrically connected to the photodiode22. An undepicted scintillator is disposed on the photodetecting section20. The scintillator generates scintillation light according to X-rays incident thereon, converts an X-ray image into a light image, and outputs the light image to the photodiodes22.

The solid-state imaging device1A further comprises a plurality of row selection lines Q1to QM(represented by Qmand Qm+1inFIG. 2) provided for the respective rows and a plurality of readout lines R1to RN(represented by RNand RN−1inFIG. 2) provided for the respective columns.

The row selection line Qmof the m-th row electrically connects the control terminals (e.g., gate terminals) for controlling the open/closed state of the transistors21included in the pixels Pm,1to Pm,Nof the corresponding row and the vertical shift register60for controlling the open/closed state of the transistors21for each row to each other. The readout line Rnof the n-th column (where n is an integer of 1 or more and N or less) is electrically connected to the other terminals (e.g., drain regions) of the transistors21included in the pixels P1,nto PM,nof the corresponding column. The plurality of row selection lines Q1to QMand plurality of readout lines R1to RNare made of a metal, for example.

The unnecessary carrier capture section30has M carrier capture regions DA1to DAM. The carrier capture regions DA1to DAMare arranged in a region between the photodetecting section20and vertical shift register60for the respective rows.FIG. 2illustrates two carrier capture regions DAm, DAm+1as representative of the carrier capture regions DA1to DAM. For example, the carrier capture region DAmis the carrier capture region located at the m-th row. As with the above-described pixels P1,1to PM,N,each of the M carrier capture regions DA1to DAMcomprises a transistor21and a photodiode22.

Each of the M transistors21in the carrier capture regions DA1to DAMis a second switch circuit in this embodiment. The M photodiodes22in the carrier capture regions DA1to DAM, each of which is a dummy photodiode in this embodiment and constituted by a semiconductor region including a p-n junction or p-i-n junction, are arranged in a region between the photodetecting section20and vertical shift register60for the respective rows. The transistor21has one terminal (e.g., a source region) electrically connected to the photodiode22.

A control terminal (e.g., gate terminal) for controlling the open/closed state of the transistor21included in the carrier capture region DAmis electrically connected to the row selection line Qmof the corresponding row. The solid-state imaging device1A further comprises a charge elimination line Rd. The charge elimination line Rdis electrically connected to the other terminals (e.g., drain regions) of the transistors21included in the carrier capture regions DA1to DAM. The charge elimination line Rdis made of a metal. Light is incident on the carrier capture regions DA1to DAM, which are not light-shielded, as on the normal pixels P1,1to PM,N. However, the carrier capture regions DA1to DAMmay partly or wholly be light-shielded.

The unnecessary carrier capture section30further has (N+1) carrier capture regions DB1to DBN+1arranged for the respective columns. The carrier capture regions DB1to DBN+1are constructed as with the above-described pixels P1,1to PM,N. That is, each of the carrier capture regions DB1to DBN+1comprises a transistor21and a photodiode22.

The transistor21has one terminal (e.g., source region) electrically connected to the photodiode22. Control terminals of the transistors21included in the carrier capture regions DB1to DBN+1are electrically connected to a row selection line Qdwhich will be explained later. The other terminals (e.g., drain regions) of the transistors21included in the carrier capture regions DB1to DBNare electrically connected to the readout lines R1to RNof the respective columns. The other terminal of the transistor21included in the carrier capture region DBN+1of the (N+1)-th column is electrically connected to the charge elimination line Rd.

A circuit configuration of the solid-state imaging device1A will now be explained in detail.FIG. 3is a diagram illustrating an inner configuration of the solid-state imaging device1A. As described above, the photodetecting section20is constructed by two-dimensionally arraying M×N pixels P1,1to PM,Nin M rows and N columns. The unnecessary carrier capture section30includes the M carrier capture regions DA1to DAMand (N+1) carrier capture regions DB1to DBN+1. The m-throw selection line Qmconnected to the N pixels Pm,1to Pm,Nand carrier capture region DAmof the m-th row is connected to the vertical shift register60. The row selection line Qdconnected to the carrier capture regions DB1to DBN+1is also connected to the vertical shift register60.

The readout circuit section40is a circuit for successively outputting electric signals corresponding to amounts of charges output for the respective columns through the readout lines R1to RN. The readout circuit section40has N integration circuits42provided for the respective columns and N holding circuits44. The integration circuit42and holding circuit44are connected in series to each other for each column. The N integration circuits42have a configuration in common. The N holding circuits44have a configuration in common.

The N integration circuits42have respective input terminals connected to the readout lines R1to RN, accumulate charges input from the readout lines R1to RN, and output respective voltage values corresponding to the amounts of accumulated charges from output terminals to the N holding circuits44. Here, the charge elimination line Rdis provided with no integration circuit, but is short-circuited to a reference potential line (a potential line connected to the ground potential in this embodiment) GND. Therefore, the charges having passed through the charge elimination line Rdis discharged to the reference potential line GND. Thus, unlike the signals output from the photodiodes22of the pixels P1,1to PM,Nand input to the readout circuit section40, the signals output from the respective dummy photodiodes22of the carrier capture regions DA1to DAMare not output from the solid-state imaging device1A.

The N integration circuits42are respectively connected to a reset line46provided in common for the N integration circuits42. The N holding circuits44have respective input terminals connected to the output terminals of the integration circuits42, hold the voltage values input to the input terminals, and output the held voltage values from the output terminals to a voltage output line48. The N holding circuits44are respectively connected to a hold line45provided in common for the N holding circuits44. The N holding circuits44are also respectively connected to a horizontal shift register61through a first column selection line U1to an N-th column selection line UN.

The vertical shift register60provides the N pixels Pm,1to Pm,Nat the m-th row with an m-th row selection control signal VSmthrough the m-th row selection line Qm. In addition, the vertical shift register60provides the (N+1) carrier capture regions DB1to DBN+1with a row selection control signal VSdthrough the row selection line Qd. In the vertical shift register60, the row selection control signals VSd, VS1to VSMsequentially become significant values.

The horizontal shift register61provides the N holding circuits44with column selection control signals HS1to HSNthrough the column selection lines U1to UN, respectively. The column selection control signals HS1to HSNsequentially become significant values. Each of the N integration circuits42is provided with a reset control signal RE through the reset line46. Each of the N holding circuits44is provided with a hold control signal Hd through the hold line45.

FIG. 4is a diagram illustrating a detailed circuit configuration example of the pixel Pm,n, integration circuit42, holding circuit44, and carrier capture region DAm. Here, a circuit diagram of the pixel Pm,non the m-th row and the n-th column is illustrated as a representative of the M×N pixels P1,1to PM,N, and a circuit diagram of the carrier capture region DAmat the m-th row is illustrated as a representative of the M carrier capture regions DA1to DAM.

As illustrated inFIG. 4, the photodiode22of the pixel Pm,nhas a grounded anode terminal and a cathode terminal connected to the readout line Rnthrough the transistor21. Similarly, the photodiode22of the carrier capture region DAmhas a grounded anode terminal and a cathode terminal connected to the charge elimination line Rdthrough the transistor21. The transistors21of the pixel Pm,nand carrier capture region DAmare provided with the m-th row selection control signal VSmfrom the vertical shift register60through the m-th row selection line Qm. The m-th row selection control signal VSminstructs the transistors21included in the N pixels Pm,1to Pm,Nand carrier capture region DAmat the m-th row to open/close.

When the m-th row selection control signal VSmis a non-significant value (off-voltage of the control terminal of the transistor21), for example, the transistor21is turned off. At this time, the charges generated in the photodiode22are accumulated in the junction capacitance part of the photodiode22without being output to the readout line Rn(or the charge elimination line Rd). When the m-th row selection control signal VSmis a significant value (on-voltage of the control terminal of the transistor21), on the other hand, the transistor21is turned on. At this time, the charges accumulated in the junction capacitance part of the photodiode22are output to the readout line Rn(or charge elimination line Rd) through the transistor21. The charges output from the photodiode22of the pixel Pm,nare sent to the integration circuit42through the readout line Rn. On the other hand, the charges output from the photodiode22of the carrier capture region DAmare sent to the reference potential line GND through the charge elimination line Rd.

The integration circuit42has a so-called charge integration type configuration including an amplifier42a, a capacitive element42b, and a discharge switch42c. The capacitive element42band discharge switch42care connected in parallel with each other between the input terminal and output terminal of the amplifier42a. The amplifier42ahas an input terminal connected to the readout line Rn. The discharge switch42cis provided with the reset control signal RE through the reset line46.

The reset control signal RE instructs the respective discharge switches42cof the N integration circuits42to open/close. For example, when the reset control signal RE is a non-significant value (e.g., high level), the discharge switch42ccloses, so as to discharge the capacitive element42b, thereby initializing the output voltage value of the integration circuit42. When the reset control signal RE is a significant value (e.g., low level), the discharge switch42copens, so that the charges input to the integration circuit42are accumulated in the capacitive element42b, whereby a voltage value corresponding to the amount of accumulated charges is output from the integration circuit42.

The holding circuit44includes an input switch44a, an output switch44b, and a capacitive element44c. One end of the capacitive element44cis grounded. The other end of the capacitive element44cis connected to the output terminal of the integration circuit42through the input switch44aand also connected to the voltage output line48through the output switch44b. The input switch44ais provided with the hold control signal Hd through the hold line45. The hold control signal Hd instructs the respective input switches44aof the N holding circuits44to open/close. The output switch44bof the holding circuit44is provided with the n-th column selection control signal HSnthrough the n-th column selection line Un. The selection control signal HSninstructs the output switch44bof the holding circuit44to open/close.

When the hold control signal Hd changes from the high level to the low level, for example, the input switch44achanges from the closed state to the open state, whereupon the voltage value input to the holding circuit44is held by the capacitive element44c. When the n-th column selection control signal HSnchanges from the low level to the high level, the output switch44bis closed, whereupon the voltage value held by the capacitive element44cis output to the voltage output line48.

FIG. 5is a timing chart of respective signals.FIG. 5illustrates, successively from the upper side, (a) reset control signal RE, (b) row selection control signal VSd, (c) first row selection control signal VS1, (d) second row selection control signal VS2, (e) third row selection control signal VS3, (f) fourth row selection control signal VS4, (g) M-th row selection control signal VSM, (h) hold control signal Hd, and (i) first column selection control signal HS1to N-th column selection control signal HSN.

First, during a period from time t10to time t11, the reset control signal RE is set to the high level. This closes the discharge switch42cin each of the N integration circuits42, so as to discharge the capacitive element42b.

During a period from time t12after time t11to time t13, the vertical shift register60sets the row selection control signal VSdto the high level. This turns the transistors21in the carrier capture regions DB1to DBN+1into connected states, whereby the charges accumulated in the respective photodiodes22of the carrier capture regions DB1to DBN+1are output through the readout lines R1to RNto the integration circuits42and accumulated in the capacitive elements42b. Thereafter, during a period from time t14after time t13to time t15, the reset control signal RE is set to the high level. This closes the discharge switch42cin each of the N integration circuits42, so as to release the charges accumulated in the capacitive element42b.

Subsequently, during a period from time t16after time t15to time t17, the first row selection control signal VS1is set to the high level. This turns the transistors21in the pixels P1,1to P1,Nat the first row and the carrier capture region DA1into connected states. The charges accumulated in the photodiodes22of the pixels P1,1to P1,Nare output through the readout lines R1to RNto the respective integration circuits42, so as to be accumulated in their capacitive elements42b. The integration circuits42output respective voltage values having magnitudes corresponding to the amounts of charges accumulated in the capacitive elements42b. On the other hand, the charges accumulated in the photodiode22of the carrier capture region DA1are released to the reference potential line GND through the charge elimination line Rd.

Then, during a period from time t18after time t17to time t19, the hold control signal Hd is set to the high level, whereby the input switch44ain each of the N holding circuits44is turned into the connected state, whereby the voltage value output from the integration circuit42is held by the capacitive element44c.

Thereafter, during a period from time t20after time t19to time t21, the horizontal shift register61turns the first column selection control signal HS1to N-th column selection control signal HSNinto the high levels in sequence. This successively closes the output switches44bof the N holding circuits44, whereby the voltage values held by the capacitive elements44care sequentially output to the voltage output line48. During this period, the reset control signal RE is set to the high level, whereby the capacitive element42bof each integration circuit42is discharged.

Next, during a period from time t22after time t21to time t23, the vertical shift register60sets the second row selection control signal VS2to the high level. This turns the transistors21in the pixels P2,1to P2,Nat the second row and the carrier capture region DA2into connected states. The charges accumulated in the respective photodiodes22in the pixels P2,1to P2,Nare output through the readout lines R1to RNto the integration circuits42and accumulated in the capacitive elements42b. On the other hand, the charges accumulated in the photodiode22of the carrier capture region DA2are released to the reference potential line GND through the charge elimination line Rd.

Subsequently, an operation similar to that at the first row successively outputs the voltage values having magnitudes corresponding to the amounts of charges accumulated in the capacitive elements42bfrom the N holding circuits44to the voltage output line48. Then, operations similar to that at the first row also convert the charges accumulated in the pixels at the third to M-th rows into voltage values and output them successively to the voltage output line48. This completes the readout of image data by one image frame from the photodetecting section20.

Effects exhibited by the solid-state imaging device1A of this embodiment explained in the foregoing will now be explained. In the solid-state imaging device1A of this embodiment, light is incident on not only the photodetecting section20but its surrounding regions as well. While the solid-state imaging device1A is used as an X-ray imaging device, even when the regions surrounding the photodetecting section20are covered with a scintillator, X-rays transmitted through the scintillator and scintillation light from the scintillator are incident on the regions surrounding the photodetecting section20. This generates unnecessary charges (unnecessary carriers) in the regions surrounding the photodetecting section20. Since the vertical shift register60juxtaposed with the photodetecting section20has a substantial area, a large number of unnecessary carriers occur in the region formed with the vertical shift register60in particular.

When unnecessary carriers generated in the vertical shift register60flow into the photodetecting section20, noise is superimposed on outputs from pixels P1,Nto PM,Nadjacent to the vertical shift register60.FIG. 6is a plan view illustrating an example in which a photodiode (dummy photodiode)81for absorbing unnecessary carriers is arranged in a region between the vertical shift register60and photodetecting section20in order to avoid the phenomenon described above. The dummy photodiode81is formed over a plurality of rows continuously from the first row to M-th row (i.e., continuous in the column direction). Short-circuiting the dummy photodiode81to the reference potential line (grounding line) GND can release the unnecessary carriers generated in the vertical shift register60to the reference potential line GND, so as to prevent them from flowing into the photodetecting section20.

However, the following problem exists in this scheme. Typically, between pixels adjacent to each other in the photodetecting section20, crosstalk exists because of coupling capacitance occurring between their photodiodes22and the like. In each pixel, parasitic capacitance also exists between the photodiode22and row selection line Qmconnected to each other through the transistor21and this parasitic capacitance also affects the crosstalk. However, the above-described dummy photodiode81is provided with no transistor and thus does not generate such parasitic capacitance. Therefore, the pixels P1,Nto PM,Nadjacent to the dummy photodiode81have different degrees of crosstalk as compared with the other pixels, whereby output characteristics and magnitudes of noise from the pixels P1,Nto PM,Nadjacent to the dummy photodiode81differ from those of the other pixels.

In view of such problems, the solid-state imaging device1A of this embodiment arranges the M photodiodes (dummy photodiodes)22for the respective rows in the carrier capture regions DA1to DAMbetween the vertical shift register60and photodetecting section20. The unnecessary carriers generated in the vertical shift register60are absorbed by these photodiodes22. This can effectively prevent noise caused by unnecessary carriers generated in the vertical shift register60from being superimposed on outputs from pixels in the photodetecting section20.

In this solid-state imaging device1A, the photodiodes22of the earner capture regions DA1to DAMand the charge elimination line Rdare connected to each other through the transistors21, and when the transistors21are turned on, unnecessary carriers are eliminated from the photodiodes22to the reference potential line GND through the charge elimination line Rd. Thus, in the solid-state imaging device1A, the photodiodes22of the carrier capture regions DA1to DAMare provided with the transistors21as in the pixels P1,1to PM,Nin the photodetecting section20. Since the photodiodes22are provided for the carrier capture regions DA1to DAMof the respective rows, the photodiodes22of the carrier capture regions DA1to DAMadjacent to each other in the column direction are separated from each other.

Therefore, the solid-state imaging device1A of this embodiment enables the pixels P1,Nto PM,Nadjacent to the carrier capture regions DA1to DAMto have crosstalk with a magnitude close to that of crosstalk in other pixels, thereby making it possible for the pixels P1,Nto PM,Nto have output characteristics and magnitudes of noise closer to those of the other pixels. When the carrier capture regions DA1to DAMare light-shielded only partly or not at all, light is incident on the photodiodes22of the carrier capture regions DA1to DAMas in the other pixels P1,1to PM,N, so as to generate carriers, whereby they can accumulate carriers by amounts closer to those in the other pixels.

As in this embodiment, the vertical shift register60and photodetecting section20may be formed on the common substrate12. While unnecessary carriers generated in the vertical shift register60are likely to flow into the photodetecting section20in such a case, the solid-state imaging device1A of this embodiment can effectively prevent the unnecessary carriers from flowing into the photodetecting section20.

Preferably, as in this embodiment, the control terminals of the transistors21of the carrier capture regions DA1to DAMare connected to the row selection lines Q1to QMin common with the control terminals of the transistors21of the pixels P1,1to PM,N. As a consequence, the parasitic capacitance values between the photodiodes22of the carrier capture regions DA1to DAMand the row selection lines Q1to QMcan be made closer to the parasitic capacitance values between the photodiodes22of the pixels P1,1to PM,Nand the row selection lines Q1to QM. Therefore, the magnitude of crosstalk in the pixels P1,Nto PM,Nadjacent to the carrier capture regions DA1to DAMcan be made further closer to the magnitude of crosstalk in the other pixels.

An exposure method in a process of manufacturing the solid-state imaging device1A in accordance with this embodiment will now be explained. When manufacturing the solid-state imaging device1A, a number of pixels P1,1to PM,Nand carrier capture regions DA1to DAM, DB1to DBN+1are made by a photolithography technique while using a reticle including a predetermined pattern. At this time, since the pixels P1,1to PM,Nhave a configuration in common, so-called joint exposure is performed, in which the reticle including the predetermined pattern is exposed to light a plurality of times while moving its position.

(a) inFIG. 7is a plan view of the photodetecting section20and illustrates an example of boundaries (joints) LA of joint exposure. In the example illustrated in (a) inFIG. 7, lines passing the center of a rectangular photodiode22are referred to as boundaries LA, LB. In this case, as illustrated in (b) inFIG. 7, the photodiodes22in the carrier capture regions DA1to DAM, DB1to DBN+1have a size substantially equivalent to that of the photodiodes22in the pixels P1,1to PM,N.

(a) inFIG. 8is a plan view of the photodetecting section20and illustrates another example of boundaries LA of joint exposure. In the example illustrated in (a) inFIG. 8, the boundary LA in the column direction is shifted to the left side (i.e., away from the carrier capture regions DA1to DAM) from the center of the rectangular photodiode22, and the boundary LB in the row direction is shifted to the upper side (i.e., away from the carrier capture regions DB1to DBN) from the center of the rectangular photodiode22. In this case, as illustrated, in (b) inFIG. 8, the size of the photodiodes22in the carrier capture regions DA1to DAM, DB1to DBN+1can be made smaller than the size of the photodiodes22in the pixels P1,1to PM,N.

Specifically, the width of the photodiodes22of the carrier capture regions DA1to DAMin the row direction can be made shorter than the width of the photodiodes22of the pixels P1,1to PM,Nin this direction. The width of the photodiodes22of the carrier capture regions DB1to DBNin the column direction can also be made shorter than the width of the photodiodes22of the pixels P1,1to PM,Nin this direction. Therefore, the region required for surrounding the photodetecting section20can be made narrower.

The following advantages are obtained by making the photodiodes22of the carrier capture regions DA1to DAM, DB1to DBN+1smaller as described above.FIG. 9is a plan view schematically illustrating an example in which two glass substrates12are juxtaposed with each other. Formed on the glass substrates12are the pixels P1,1to PM,Nof the photodetecting section20and the carrier capture regions DA1to DAM, DB1to DBN+1. Thus juxtaposing a plurality of glass substrates12with each other is effective in further increasing the area of the photodetecting section in the solid-state imaging device as a whole.

At this time, arranging the pixels P1,1to PM,Nand carrier capture regions DA1to DAMand DB1to DBNidentically on the two glass substrates12enables parts to be used in common, thereby suppressing the manufacturing cost. In this case, however, the carrier capture regions DA1to DAMare located between the two photodetecting sections20, thus yielding an insensitive region (dead area) in which the image is not obtained. In such a case, the above-described insensitive region can be narrowed by making the width of the photodiodes22of the carrier capture regions DA1to DAMin the row direction smaller than the width of the photodiodes22in the pixels P1,1to PM,Nin this direction.

Referring to (a) inFIG. 8, in a normal pixel Pm+1,n, a transistor is formed on the side closer to Pm+1,n+1. The joint (boundary LA) of the pixel Pm+1,nis located on the side closer to the pixel Pm+1,n−1. That is, with respect to the center of the pixel Pm+1,n, the transistor and joint (boundary LA) exist on one side and the other side of the pixel, respectively, thereby increasing the distance between the joint and transistor in the row direction. Thus, the joint and transistor can physically be separated from each other, whereby manufacturing defects can be reduced.

The solid-state imaging device in accordance with the present invention is not limited to the above-described embodiment, but can be modified in various ways. For example, the photodetecting section illustrated in the above-described embodiment may comprise a configuration in which a film of amorphous silicon or polycrystalline silicon is formed on a glass substrate. In this case, the transistor21is favorably realized by a thin-film transistor. The photodetecting section may also be produced on a monocrystalline silicon substrate.

Though the above-described embodiment employs the present invention in a so-called passive pixel sensor (PPS) in which each pixel has no amplifier circuit while integration circuits are provided for respective readout lines of columns, the present invention is also applicable to a so-called active pixel sensor (APS) in which each pixel has an amplifier circuit.

While the above-described embodiment illustrates an example in which the carrier capture regions DB1to DBN+1are juxtaposed with the photodetecting section in the column direction, the carrier capture regions DB1to DBN+1may be omitted.

The solid-state imaging device in accordance with the above-described embodiment uses a configuration comprising a photodetecting section having M×N pixels (each of M and N being an integer of 2 or more), each including a first photodiode and a first switch circuit having one terminal connected to the first photodiode, two-dimensionally arrayed in M rows and N columns; N readout lines provided for the respective columns and connected to the other terminals of the first switch circuits included in the pixels of the corresponding columns; N integration circuits for outputting respective voltage values corresponding to amounts of charges input through the N readout lines; a shift register, juxtaposed with the photodetecting section in a row direction, for controlling an open/closed state of the first switch circuits for each row; M dummy photodiodes arranged in a region between the shift register and the photodetecting section for the respective rows; M second switch circuits having respective one terminals connected to the M dummy photodiodes; and a charge discharge line connected to the other terminals of the M second switch circuits and short-circuited to a reference potential line.

The solid-state imaging device may have a configuration in which the dummy photodiode has a width in the row direction shorter than that of the first photodiode in the row direction. In the above solid-state imaging device, the size of the dummy photodiode is not always required to be equal to that of the first photodiode. Therefore, thus making the width of the dummy photodiode shorter than that of the first photodiode can narrow regions surrounding the photodetecting section, whereby an insensitive region occurring between solid-state imaging devices when a plurality of solid-state imaging devices are juxtaposed with each other, for example, can be made narrower.

The solid-state imaging device may also have a configuration in which the shift register and the photodetecting section are formed on a common substrate. While unnecessary carriers generated in the shift register are likely to flow into the photodetecting section in such a case, the above-described solid-state imaging device can effectively prevent the unnecessary carriers from flowing into the photodetecting section.

The solid-state imaging device may have a configuration further comprising M row selection lines, provided for the respective rows, for electrically connecting control terminals of the first and second switch circuits for controlling the open/closed state and the shift register to each other. Thus providing the row selection lines in common for the first and second switch circuits enables pixels adjacent to the dummy photodiode to have crosstalk with a magnitude further closer to that of crosstalk in the other pixels.

INDUSTRIAL APPLICABILITY

The present invention can be utilized as a solid-state imaging device which enables pixels adjacent to a dummy photodiode to have output characteristics and magnitudes of noise closer to those of the other pixels.

REFERENCE SIGNS LIST