SEMICONDUCTOR PACKAGE

A semiconductor package includes a buffer die, semiconductor chip stacks stacked on the buffer die, each of the semiconductor chip stacks including a plurality of first semiconductor chips and a second semiconductor chip on the plurality of first semiconductor chips, and a mold layer covering an upper surface of the buffer die and side surfaces of the semiconductor chip stacks. Each of the first semiconductor chips and the second semiconductor chip includes a wiring part including multilayer wirings, an upper connection structure on the wiring part and having a plurality of upper conductive pads and a lower connection structure under the wiring part and having a plurality of lower conductive pads, and the second semiconductor chip further includes a redistribution layer on the upper connection structure and having an insulating layer and a plurality of redistribution pads in the insulating layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0127582, filed on Oct. 6, 2022, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND

The inventive concepts relate to a semiconductor package, and more particularly, relates to a semiconductor package including a semiconductor chip stack.

An integrated circuit chip is provided with a semiconductor package so as to be suitably applied to an electronic product. In a general semiconductor package, an integrated circuit chip is mounted on a printed circuit board (PCB) and is electrically connected to the PCB through bonding wirings or bumps. Research for improving reliability and/or durability of a semiconductor package have been conducted with the development of an electronic industry.

SUMMARY

An aspect of the inventive concepts is to provide a semiconductor package with improved reliability and stability.

A semiconductor package according to some example embodiments of the inventive concepts includes a buffer die, semiconductor chip stacks stacked on the buffer die, each of the semiconductor chip stacks including a plurality of first semiconductor chips and at least one second semiconductor chip on the plurality of first semiconductor chips, and a mold layer covering an upper surface of the buffer die and side surfaces of the semiconductor chip stacks. Each of the first semiconductor chips and the second semiconductor chip includes a wiring part including multilayer wirings, an upper connection structure on the wiring part and having a plurality of upper conductive pads, and a lower connection structure under the wiring part and having a plurality of lower conductive pads, and the at least one second semiconductor chip further includes a redistribution layer on the upper connection structure and having an insulating layer and a plurality of redistribution pads in the insulating layer.

A semiconductor package according to some example embodiments of the inventive concepts includes semiconductor chip stacks stacked on each other, each of the semiconductor chip stacks including a plurality of first semiconductor chips and at least one second semiconductor chip on the plurality of first semiconductor chips. Each of the first semiconductor chips and the at least one second semiconductor chips includes a wiring part including multilayer wirings, an upper connection structure on the wiring part and having a plurality of upper conductive pads, and a lower connection structure under the wiring part and having a plurality of lower conductive pads, the at least one second semiconductor chip further includes a redistribution layer on the upper connection structure and having an insulating layer and a plurality of redistribution pads in the insulating layer, and each of the semiconductor chip stacks includes the same number of first semiconductor chips as each other.

A semiconductor package according to some example embodiments of the inventive concepts includes a buffer die, semiconductor chip stacks stacked on the buffer die, each of the semiconductor chip stacks including a plurality of first semiconductor chips and at least one second semiconductor chip on the plurality of first semiconductor chips, and a mold layer covering an upper surface of the buffer die and side surfaces of the semiconductor chip stacks. Each of the first semiconductor chips and the at least one second semiconductor chip includes a wiring part including multilayer wirings, a lower connection structure under the wiring part and having a plurality of lower conductive pads, and an upper connection structure on the wiring part and having a plurality of upper conductive pads, the at least one second semiconductor further includes a redistribution layer on the upper connection structure and having an insulating layer and a plurality of redistribution pads in the insulating layer, and the upper connection structure includes a first passivation layer covering an upper surface of the wiring part and having the plurality of upper conductive pads therein and first conductive pads provided on the plurality of upper conductive pads in the first passivation layer and having a recessed upper region.

DETAILED DESCRIPTION

Hereinafter, to explain the inventive concepts in more detail, example embodiments according to the inventive concepts will be described in more detail with reference to the accompanying drawings.

FIG.1is a schematic diagram of a semiconductor package according to example embodiments of the inventive concepts,FIG.2is a cross-sectional view of a semiconductor package according to example embodiments of the inventive concepts,FIG.3is a cross-sectional view illustrating a first semiconductor chip of the semiconductor package ofFIG.2,FIG.4is a cross-sectional view illustrating a second semiconductor chip of the semiconductor package ofFIG.2,FIG.5is an enlarged view illustrating an enlarged portion ‘A’ ofFIG.2.

First, referring toFIGS.1and2, a semiconductor package according to example embodiments may be a high bandwidth memory (HBM) chip. The semiconductor package according to example embodiments may include first and second semiconductor chip stacks ST1and ST2sequentially stacked on a buffer die10, and an uppermost semiconductor chip stack ST3stacked on the first and second semiconductor chip stacks ST1and ST2.

The buffer die10may be an interposer or a logic circuit chip. The buffer die10includes a buffer semiconductor substrate1. The buffer semiconductor substrate1has a first surface1aand a second surface1bwhich are opposite to each other. A buffer interlayer insulating layer3is disposed on the first surface1aof the buffer semiconductor substrate1. Buffer wirings5are disposed in the buffer interlayer insulating layer3. First buffer conductive pads7are disposed under the buffer interlayer insulating layer3. The first buffer conductive pads7and the buffer interlayer insulating layer3are covered with a first buffer passivation layer9. Second buffer conductive pads27are disposed in the first buffer passivation layer9and are in contact with the first buffer conductive pads7. Solder balls33are bonded to the second buffer conductive pads27. The second surface1bof the buffer semiconductor substrate1is covered with a buffer protective layer15. A buffer through-via11may pass through portions of the buffer semiconductor substrate1, the buffer protective layer15, and the buffer interlayer insulating layer3to become in contact with one of the buffer wirings5. A buffer via insulating layer13is interposed between the buffer through-via11and the buffer semiconductor substrate1. The buffer protective layer15is covered with a second buffer passivation layer19. A third buffer conductive pad35is disposed in the second buffer passivation layer19and connected to the buffer through-via11.

The first and second semiconductor chip stacks ST1and ST2may each have the same structure. In example embodiments, the semiconductor package is illustrated as including two semiconductor chip stacks (first and second semiconductor chip stacks ST1and ST2), but the number of semiconductor chip stacks is not limited thereto and is variable.

Each of the first and second semiconductor chip stacks ST1and ST2may include a plurality of first semiconductor chips CH1A and a second semiconductor chip CH1B disposed on the plurality of first semiconductor chips CH1A. Each of the first and second semiconductor chip stacks ST1and ST2may include two or more first semiconductor chips CH1A. Each of the first and second semiconductor chip stacks ST1and ST2may include the same number of first semiconductor chips CH1A.

In example embodiments, although it is illustrated that each of the first and second semiconductor chip stacks ST1and ST2has a structure in which two first semiconductor chips CH1A and one second semiconductor chip CH1B are stacked, the number of the first semiconductor chip CH1A is not limited thereto and is variable.

The first semiconductor chip CH1A and the second semiconductor chip CH1B may be memory chips. The memory chip may be, for example, DRAM, NAND Flash, SRAM, MRAM, PRAM, or RRAM.

A mold layer MD may cover an upper surface of the buffer die10, side surfaces of the first and second semiconductor chip stacks ST1and ST2, and the uppermost semiconductor chip stack ST3. The mold layer MD may include, for example, an insulating resin such as an epoxy-based molding compound (EMC). The mold layer MD may further include a filler, and the filler may be dispersed in the insulating resin. The filler may include, for example, silicon oxide (SiO2).

An upper surface of the mold layer MD may be stacked on the semiconductor chip stacks ST1and ST2to form a coplanar surface with an upper surface of the uppermost semiconductor chip stack ST3.

Referring toFIG.3, the first semiconductor chip CH1A according to example embodiments may include a semiconductor substrate101. The semiconductor substrate101may include, for example, a semiconductor material. The semiconductor substrate101may be a silicon single crystal substrate. The semiconductor substrate101may include a first surface101aand a second surface101bthat are opposite to each other. Although not shown, capacitors or memory cells may be disposed on the second surface101bof the semiconductor substrate101.

The second surface101bmay be covered with a first interlayer dielectric ILD. The first interlayer insulating layer ILD may have a single layer or multilayer structure of at least one of silicon oxide, silicon nitride, silicon oxynitride, and a porous insulating layer.

An upper surface of the first interlayer dielectric ILD may be covered with a second interlayer dielectric IMD. The second interlayer insulating layer IMD may have a single layer or multilayer structure of at least one of silicon oxide, silicon nitride, silicon oxynitride, and a porous insulating layer.

Multilayer wirings105may be disposed in the second interlayer dielectric IMD. Each of the wirings105may include at least one of copper, tungsten, aluminum, titanium, titanium nitride, and tungsten nitride. Internal vias VA are disposed in the second interlayer insulating layer IMD and may be connected to the wirings105. The second interlayer insulating layer IMD, the inner vias VA, and the wirings105may constitute a wiring part MR. The internal vias VA may include a conductive material same as a material of the wirings105.

Upper conductive pads107may be disposed on the second interlayer insulating layer IMD. The upper conductive pads107may be formed of metal such as aluminum. Upper surfaces of the upper conductive pads107and the second interlayer insulating layer IMD may be covered with a first passivation layer PL1. The first passivation layer PL1may have a single layer structure or a multilayer structure of at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonide nitride.

First conductive pads TE1may be disposed in the first passivation layer PL1. The first conductive pads TE1may be provided on the upper conductive pad107. The first conductive pads TE1may include, for example, a metal such as copper. The upper conductive pads107, the first conductive pads TE1, and the first passivation layer PL1may constitute an upper connection structure US.

Each of the first conductive pads TE1may have a recessed upper region RC (refer toFIG.5). The recessed upper region RC of the first conductive pads TE1may have a concave shape.

Dummy pads DP may be disposed between the first conductive pads TE1in the first passivation layer PL1. The dummy pads DP may be positioned at the same level as the first conductive pads TEL Each of the dummy pads DP may have the recessed upper region RC like the first conductive pads TE1as shown inFIG.5.

The first surface101aof the semiconductor substrate101may be covered with a protective layer110and a second passivation layer PL2. The protective layer110may have, for example, a single layer structure or a multilayer structure of at least one of silicon oxide and silicon nitride. The second passivation layer PL2may have a single layer structure or a multilayer structure of at least one of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbonide nitride.

A through-via TSV may pass through the protective layer110, the semiconductor substrate101, and the first interlayer insulating layer ILD to become in contact with one of the wirings105. A via insulation layer TVL may be disposed between the through-via TSV and the semiconductor substrate101. The via insulation layer TVL may include silicon oxide.

Lower conductive pads TE2may be disposed in the second passivation layer PL2and may be connected to the through-vias TSV, respectively. The semiconductor substrate101, the through-via TSV, the via insulating layer TVL, the protective layer110, the second passivation layer PL2, and the lower conductive pads TE2may constitute a lower connection structure BS. The lower conductive pads TE2may overlap the first conductive pads TE1, respectively. The lower conductive pads TE2may also be referred to as ‘upper conductive pads’.

A thickness T1of the first semiconductor chip CHIA may be 20 μm to 25 μm.

Referring toFIG.4, the second semiconductor chip CH1B according to example embodiments is the same as the first semiconductor chip CH1A described with reference toFIG.3, and thus the same reference numbers are used and overlapping descriptions are omitted, except for a redistribution layer RDL formed on the first passivation layer PL1.

The redistribution layer RDL includes an insulating layer120, and a plurality of redistribution pads RP and a plurality of redistribution vias RV which are disposed in the insulating layer120.

Referring toFIG.5, the insulating layer120may cover the first conductive pads TE1and the first passivation layer PL1. The insulating layer120may fill the recessed upper region RC of the first conductive pads TEL The insulating layer120may include at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), and silicon carbonide (SiCN).

The plurality of redistribution pads RP may be formed to be in contact with the first conductive pads TE1within the insulating layer120. The redistribution pads RP may include copper (Cu).

Each of the plurality of redistribution vias RV may be connected under each of the plurality of redistribution pads RP. The redistribution pad RP and the redistribution via RV may be integrally connected to each other to have a ‘T’-shaped cross section.

The redistribution via RV may be in contact with the recessed upper region RC of the first conductive pad TE1, and thus a lower end of the redistribution via RV may be positioned at a lower level than an upper end of the upper conductive pad (refer toFIG.5). The upper end of the first conductive pad TE1may be positioned at a first level LV1, and the lower end of the redistribution via RV may be positioned at a second level LV2lower than the first level LV1.

In example embodiments, although it is illustrated that the redistribution layer RDL is formed in a single layer structure, the redistribution layer RDL may be formed in a multilayer structure including a plurality of insulating layers and the redistribution pads RP and redistribution vias RV in the plurality of insulating layers.

A thickness T2of the second semiconductor chip CH1B may be 30 μm to 40 μm, and a thickness T3of the redistribution layer may be 10 μm to 5 μm.

Referring back toFIG.1, the first chip CH1positioned at a bottom of the first semiconductor chip stack ST1stacked on the buffer die10has a first recess region RC1including a curved surface. The second chip CH2stacked on the first chip CH1of the first semiconductor chip stack ST1has a second recess region RC2including a curved surface. The third chip CH3stacked on the second chip CH2of the first semiconductor chip stack ST1has a third recess region RC3including a curved surface.

Here, the first chip CH1and the second chip CH2may be the first semiconductor chips CH1A described above, respectively, and the third chip CH3may be the second semiconductor chip CH1B.

When the second chip CH2is stacked on the first chip CH1, the second passivation layer PL2of the second chip CH2may be disposed on the first passivation layer PL1of the first chip CH1. In some example embodiments, the first passivation layer PL1of the first chip CH1includes a first recess region including the recessed upper region RC of the first conductive pads TEL A space may be between the second passivation layer PL2of the second chip CH2and the first passivation layer PL1of the first chip CH1by the first recess region RC1of the first chip CH1. Accordingly, when the second chip CH2is stacked on the first chip CH1, the second recess region RC2of the second chip CH2may be formed in a more curved shape than the first recess region RC1to complement the first recess region RC1of the first chip CH1.

Similarly, when the third chip CH3is stacked on the second chip CH2, the third recess region RC3of the third chip CH3may be formed in a more curved shape than the second recess region RC2to complement the second recess RC2region of the second chip CH2.

The second semiconductor chip stack ST2may be stacked on the first semiconductor chip stack ST1.

A fourth chip CH4positioned at a bottom of the second semiconductor chip stack ST2has a fourth recess region RC4including a curved surface. A fifth chip CH5stacked on the fourth chip CH4of the second semiconductor chip stack ST2has a fifth recess region RC5including a curved surface. The sixth chip CH6stacked on the fifth chip CH5of the second semiconductor chip stack ST2has a sixth recess region RC6including a curved surface. Here, the fourth chip CH4and the fifth chip CH5may be the first semiconductor chip CH1A described above, respectively, and the sixth chip CH6may be the second semiconductor chip CH1B.

The redistribution layer RDL may be formed on the third recess region RC3of the third chip CH3, and thus the fourth chip CH4may relatively less complement the third recess region RC3of the third chip CH3when the fourth chip CH4is stacked on the third chip CH3. Accordingly, the fourth recess region RC4of the fourth chip CH4may have a less curved shape than the third recess region RC3of the third chip CH3. The fourth recess region RC4of the fourth chip CH4may have a curvature of a less than a curvature of the first recess region RC1of the first chip CH1. Accordingly, a curvature of the fifth chip CH5stacked on the fourth chip CH4may be similar to that of the second chip CH2, and a curvature of the sixth chip CH6stacked on the fifth chip CH5may be similar to that of the third chip CH3.

The uppermost semiconductor chip stack ST3positioned on the second semiconductor chip stack ST2may include a seventh chip CH7, an eighth chip CH8, and a ninth chip CH9, and the seventh chip CH7, the eighth chip CH8, and the ninth chip CH9may include a seventh recess region RC7, an eighth recess region RC8, and a ninth recess region RC9, respectively. Here, voids may not be generated on an upper surface of the uppermost semiconductor chip stack ST3because another semiconductor chip stack is not stacked on the uppermost semiconductor chip stack ST3, and thus the uppermost semiconductor chip stack ST3may include only the first semiconductor chip CH1A. That is, the seventh chip CH7, the eighth chip CH8, and the ninth chip CH9may be the first semiconductor chip CH1A, respectively. Here, although illustrated that the uppermost semiconductor chip stack ST3includes three first semiconductor chips CH1A, the uppermost semiconductor chip stack ST3may include one first semiconductor chip CH1A or two or more first semiconductor chips CH1A.

As described above, when the semiconductor chip stacks ST1and ST2are stacked on the buffer die10, each of the semiconductor chip stacks ST1and ST2may include the second semiconductor chip CH1B including the redistribution layer RDL and the insulating layer120of the redistribution layer RDL may fill the recessed upper region RC to provide the flat upper surface. Accordingly, the voids between the semiconductor stacks ST1and ST2may be reduced or prevented. This improves the reliability of the finally manufactured semiconductor package.

In addition, each of the semiconductor chip stacks ST1and ST2may be formed by disposing one second semiconductor chip CH1B including the redistribution layer RDL on the plurality of first semiconductor chips CH1A, thereby reducing overall vertical size of the semiconductor package. The process of forming the redistribution layer may be reduced or minimized, thereby reducing or minimizing increase in cost.

FIGS.6A to6Jare cross-sectional views sequentially illustrating a process of manufacturing the second semiconductor chip ofFIG.4.

Referring toFIG.6A, a wafer structure WF1is prepared. A semiconductor substrate101may have device regions R1and a scribe lane region SR1therebetween. Transistors (not shown) are formed on a second surface101bof the semiconductor substrate101. A first interlayer dielectric ILD is formed on the semiconductor substrate101to cover the second surface101bof the semiconductor substrate101. The first interlayer insulating layer ILD and the semiconductor substrate101are etched to form a through-via hole, and a via insulating layer TVL is formed to conformally cover an inner wall thereof. After filling the through-via hole with a conductive material, a CMP process or an etch-back process is performed to form a through-via TSV. A multilayer wiring105, an internal via VA, and a second interlayer dielectric IMD are formed on the first interlayer dielectric ILD. Upper conductive pads107are formed on the second interlayer dielectric IMD. A first passivation layer PL1is formed on the second interlayer dielectric layer IMD. An etching process is performed to form a first trench TC in the first passivation layer PL1. The first trench TC exposes some of the upper conductive pads107.

Referring toFIG.6B, a conductive layer is stacked on the first passivation layer PL1to fill the first trench TC. Then, a CMP process or an etch-back process is performed to expose an upper surface of the first passivation layer PL1while first conductive pads TE1are formed in the first trench TC, simultaneously. In some example embodiments, the upper surfaces of the first passivation layer PL1and the first conductive pads TE1are shown as flat, but the upper surface of the first passivation layer PL1and the first conductive pads TE1may not be flat because the first passivation layer PL1and the first conductive pads are formed by the CMP process and the etch-back process (referFIG.6G).

Referring toFIG.6C, a first carrier substrate CR1is bonded on the first passivation layer PL1with a first adhesive layer BL1interposed therebetween. The wafer structure WF1is inverted and a back grinding process is performed on a first surface101aof the semiconductor substrate101. As a result, an upper surface and an upper sidewall of the via insulation layer TVL may be exposed.

Referring toFIG.6D, a protective layer110is stacked on the first surface101aof the semiconductor substrate101. The protective layer110may also cover the upper surface and the upper sidewall of the via insulating layer TVL.

Referring toFIG.6E, an etch-back process is performed on the protective layer110to remove a portion of the protective layer110and a portion of the via insulating layer TVL to expose the through-vias TSV.

Referring toFIG.6F, a second passivation layer PL2is formed on the protective layer110. A second trench exposing the through-via TSV is formed by etching the second passivation layer PL2. A conductive layer is deposited to fill the second trench, and a CMP process or an etch-back process is performed on the conductive layer to form lower conductive pads TE2.

The first adhesive layer BL1and the first carrier substrate CR1are removed.

Referring toFIG.6G, after the wafer structure WF1is turned over, a second carrier substrate CR2is bonded on the second passivation layer PL2with a second adhesive layer BL2interposed therebetween.

After a liquid composition is coated on the first passivation layer PL1and cured, an insulating layer120is formed. As a result, the insulating layer120may be formed to have a flat upper surface. An upper surface of the first passivation layer PL1may be covered by the insulating layer120.

As described above, the insulating layer120may have a flat upper surface, and thus when stacking a plurality of semiconductor chip stacks ST1and ST2, voids in a recessed upper region RC of each of semiconductor chips CH1and CH2may be reduced. That is, among the semiconductor chips of one semiconductor chip stack, one of the insulating layers120may provide a flat upper surface, and thus the voids in the recessed upper region between the respective semiconductor chips may be reduced.

Referring toFIG.6H, an etching process is performed to form a third trench TC3in the insulating layer120. The third trench TC3may have a dual damascene hole shape. The third trench TC3exposes portions of the first conductive pads TEL

Referring toFIG.6I, a conductive layer130is stacked on the insulating layer120to fill the third trench TC3. Then, a CMP process or an etch-back process is performed to expose an upper surface of the insulating layer120while forming redistribution pads RP and redistribution vias RV in the third trench TC3, simultaneously.

Referring toFIG.6J, a singulation process (or a sawing process) is performed to irradiate the scribe lane region SR1with a laser or to cut the wafer structure WF1using a blade, thereby manufacturing individual semiconductor chips.

As a result, the second semiconductor chip CH1B ofFIG.4may be manufactured.

Meanwhile, the first semiconductor chip CH1A ofFIG.3may be manufactured by performing the sawing process after the manufacturing process ofFIGS.6A to6Fdescribed above, and a description thereof will be omitted.

In a semiconductor package according to example embodiments of the inventive concepts, when the semiconductor chip stacks are stacked on the buffer die, each semiconductor chip stack may include the second semiconductor chip including the redistribution layer, and the insulating layer of the redistribution layer may fill the recessed upper region to provide the flat upper surface. Accordingly, the voids between the semiconductor chip stacks may be reduced or prevented. This improves the reliability of the finally manufactured semiconductor package.

In addition, each of the semiconductor chip stacks is formed by disposing one second semiconductor chip including the redistribution layer on the plurality of first semiconductor chips, thereby reducing the overall vertical size of the semiconductor package. The process of forming the redistribution layer maybe reduced or minimized, thereby reducing or minimizing the increase in cost.

While example embodiments are described above, a person skilled in the art may understand that many modifications and variations are made without departing from the spirit and scope of the inventive concepts defined in the following claims. Accordingly, the example embodiments of the inventive concepts should be considered in all respects as illustrative and not restrictive, with the spirit and scope of the inventive concepts being indicated by the appended claims.