Layered chip package and method of manufacturing same

A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions stacked; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. The plurality of layer portions include a first-type layer portion and a second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, and a plurality of first-type electrodes that are connected to the semiconductor chip and the wiring. The second-type layer portion includes a defective semiconductor chip, and a plurality of second-type electrodes that are connected to the wiring and not to the semiconductor chip.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a layered chip package that includes a plurality of semiconductor chips stacked, and to a method of manufacturing the same.

2. Description of the Related Art

In recent years, lighter weight and higher performance have been demanded of portable devices typified by cellular phones and notebook personal computers. Accordingly, there has been a need for higher integration of electronic components for use in the portable devices. With the development of image- and video-related equipment such as digital cameras and video recorders, semiconductor memories of larger capacity and higher integration have also been demanded.

As an example of highly integrated electronic components, a system-in-package (hereinafter referred to as SiP), especially an SiP utilizing a three-dimensional packaging technology for stacking a plurality of semiconductor chips, has attracting attention in recent years. In the present application, a package that includes a plurality of semiconductor chips (hereinafter, also simply referred to as chips) stacked is called a layered chip package. Since the layered chip package allows a reduction in wiring length, it provides the advantage of allowing quick circuit operation and a reduced stray capacitance of the wiring, as well as the advantage of allowing higher integration.

Major examples of the three-dimensional packaging technology for fabricating a layered chip package include a wire bonding method and a through electrode method. The wire bonding method stacks a plurality of chips on a substrate and connects a plurality of electrodes formed on each chip to external connecting terminals formed on the substrate by wire bonding. The through electrode method forms a plurality of through electrodes in each of chips to be stacked and wires the chips together by using the through electrodes.

The wire bonding method has the problem that it is difficult to reduce the distance between the electrodes so as to avoid contact between the wires, and the problem that the high resistances of the wires hamper quick circuit operation.

The through electrode method is free from the above-mentioned problems of the wire bonding method. Unfortunately, however, the through electrode method requires a large number of steps for forming the through electrodes in chips, and consequently increases the cost for the layered chip package. According to the through electrode method, forming the through electrodes in chips requires a series of steps as follows: forming a plurality of holes for the plurality of through electrodes in a wafer that is to be cut later into a plurality of chips; forming an insulating layer and a seed layer in the plurality of holes and on the top surface of the wafer; filling the plurality of holes with metal such as Cu by plating to form the through electrodes; and removing unwanted portions of the seed layer.

According to the through electrode method, the through electrodes are formed by filling metal into holes having relatively high aspect ratios. Consequently, voids or keyholes are prone to occur in the through electrodes due to poor filling of the holes with metal. This tends to reduce the reliability of wiring formed by the through electrodes.

According to the through electrode method, vertically adjacent chips are physically joined to each other by connecting the through electrodes of the upper chip and those of the lower chip by soldering, for example. The through electrode method therefore requires that the upper and lower chips be accurately aligned and then joined to each other at high temperatures. When the upper and lower chips are joined to each other at high temperatures, however, misalignment between the upper and lower chips can occur due to expansion and contraction of the chips, which often results in electrical connection failure between the upper and lower chips.

U.S. Pat. No. 5,953,588 discloses a method of manufacturing a layered chip package as described below. In the method, a plurality of chips cut out from a processed wafer are embedded into an embedding resin and then a plurality of leads are formed to be connected to each chip, whereby a structure called a neo-wafer is fabricated. Next, the neo-wafer is diced into a plurality of structures each called a neo-chip. Each neo-chip includes one or more chips, resin surrounding the chip(s), and a plurality of leads. The plurality of leads connected to each chip have their respective end faces exposed in a side surface of the neo-chip. Next, a plurality of types of neo-chips are laminated into a stack. In the stack, the respective end faces of the plurality of leads connected to the chips of each layer are exposed in the same side surface of the stack.

Keith D. Gann, “Neo-Stacking Technology”, HDI Magazine, December 1999, discloses fabricating a stack by the same method as that disclosed in U.S. Pat. No. 5,953,588, and forming wiring on two side surfaces of the stack.

The manufacturing method disclosed in U.S. Pat. No. 5,953,588 requires a large number of steps and this raises the cost for the layered chip package. According to the method, after a plurality of chips cut out from a processed wafer are embedded into the embedding resin, a plurality of leads are formed to be connected to each chip to thereby fabricate the neo-wafer, as described above. Accurate alignment between the plurality of chips is therefore required when fabricating the neo-wafer. This is also a factor that raises the cost for the layered chip package.

U.S. Pat. No. 7,127,807 B2 discloses a multilayer module formed by stacking a plurality of active layers each including a flexible polymer substrate with at least one electronic element and a plurality of electrically-conductive traces formed within the substrate. U.S. Pat. No. 7,127,807 B2 further discloses a manufacturing method for a multilayer module as described below. In the manufacturing method, a module array stack is fabricated by stacking a plurality of module arrays each of which includes a plurality of multilayer modules arranged in two orthogonal directions. The module array stack is then cut into a module stack which is a stack of a plurality of multilayer modules. Next, a plurality of electrically-conductive lines are formed on the respective side surfaces of the plurality of multilayer modules included in the module stack. The module stack is then separated from each other into individual multilayer modules.

With the multilayer module disclosed in U.S. Pat. No. 7,127,807 B2, it is impossible to increase the proportion of the area occupied by the electronic element in each active layer, and consequently it is difficult to achieve higher integration.

For a wafer to be cut into a plurality of chips, the yield of the chips, that is, the rate of conforming chips with respect to all chips obtained from the wafer, is 90% to 99% in many cases. Since a layered chip package includes a plurality of chips, the rate of layered chip packages in which all of the plurality of chips are conforming ones is lower than the yield of the chips. The larger the number of chips included in each layered chip package, the lower the rate of layered chip packages in which all of the chips are conforming ones.

A case will now be considered where a memory device such as a flash memory is formed using a layered chip package. For a memory device such as a flash memory, a redundancy technique of replacing a defective column of memory cells with a redundant column of memory cells is typically employed so that the memory device can normally function even when some memory cells are defective. The redundancy technique can also be employed in the case of forming a memory device using a layered chip package. This makes it possible that, even if some of memory cells included in any chip are defective, the memory device can normally function while using the chip including the defective memory cells. Suppose, however, that a chip including a control circuit and a plurality of memory cells has become defective due to, for example, a wiring failure of the control circuit, and the chip cannot function normally even by employing the redundancy technique. In such a case, the defective chip is no longer usable. While the defective chip can be replaced with a conforming one, it increases the cost for the layered chip package.

U.S. Patent Application Publication No. 2007/0165461 A1 discloses a technique of identifying one or more defective flash memory dies in a flash memory device having a plurality of flash memory dies, and disabling memory access operations to each identified die.

In the case of forming a memory device using a layered chip package, one or more defective chips included in the layered chip package may be identified and access to such defective chips may be disabled in the same way as the technique disclosed in U.S. Patent Application Publication No. 2007/0165461 A1.

Disabling access to a defective chip in a layered chip package, however, gives rise to the following two problems. A first problem is that the defective chip is electrically connected to a plurality of terminals of the layered chip package by wiring, and such a connection can possibly cause malfunction of the layered chip package.

A second problem is that, for a layered chip package that includes a predetermined number of chips and is able to implement a memory device having a desired memory capacity when all the chips included in the layered chip package are conforming, simply disabling access to any defective chip included in the layered chip package is not sufficient for implementing the memory device having the desired memory capacity.

OBJECT AND SUMMARY OF THE INVENTION

It is an object of the present invention to provide a layered chip package including a plurality of semiconductor chips stacked, and a composite layered chip package and methods of manufacturing the same that make it possible to easily implement a package that provides, even if it includes a malfunctioning semiconductor chip, the same functions as those for the case where no malfunctioning semiconductor chip is included.

A layered chip package of the present invention includes: a main body having a top surface, a bottom surface, and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body. The main body includes: a main part that includes a plurality of layer portions stacked and has a top surface and a bottom surface; and a plurality of first terminals that are disposed on the top surface of the main part and electrically connected to the wiring.

The plurality of layer portions include at least one first-type layer portion and at least one second-type layer portion. Each of the first-type and second-type layer portions includes a semiconductor chip. The first-type layer portion further includes a plurality of first-type electrodes that are electrically connected to the semiconductor chip and to the wiring. The second-type layer portion further includes a plurality of second-type electrodes that are electrically connected to the wiring and not to the semiconductor chip. The plurality of first terminals are formed by using the plurality of first-type or second-type electrodes of the uppermost one of the layer portions.

In the layered chip package of the present invention, the semiconductor chip of the first-type layer portion may be a normally functioning one, whereas the semiconductor chip of the second-type layer portion may be a malfunctioning one.

In the layered chip package of the present invention, the semiconductor chip may have a plurality of electrode pads. In such a case, the first-type layer portion may further include a first-type insulating layer disposed around the plurality of electrode pads. The first-type insulating layer may have a plurality of openings for exposing the plurality of electrode pads. The plurality of first-type electrodes may be electrically connected to the plurality of electrode pads through the plurality of openings. The second-type layer portion may further include a second-type insulating layer that covers the plurality of electrode pads so as to avoid exposure.

In the layered chip package of the present invention, the main body may further include a plurality of second terminals that are disposed on the bottom surface of the main part and electrically connected to the wiring. In such a case, at least either the first terminals or the second terminals may each include a solder layer made of a solder material, the solder layer being exposed in a surface of each of the first terminals or each of the second terminals.

In the layered chip package of the present invention, the semiconductor chip may have four side surfaces. Each of the first-type and second-type layer portions may further include an insulating portion that covers at least one of the four side surfaces of the semiconductor chip. In such a case, the insulating portion may have at least one end face that is located in the at least one of the side surfaces of the main body on which the wiring is disposed.

A method of manufacturing layered chip packages of the present invention is a method by which a plurality of layered chip packages of the invention are manufactured. The manufacturing method includes the steps of fabricating a layered substructure by stacking a plurality of substructures each of which includes an array of a plurality of preliminary layer portions, each of the preliminary layer portions being intended to become any one of the layer portions included in the main part, the substructures being intended to be cut later at positions of boundaries between every adjacent ones of the preliminary layer portions; and forming the plurality of layered chip packages from the layered substructure.

In the method of manufacturing the layered chip packages of the present invention, the semiconductor chip of the first-type layer portion may be a normally functioning one, whereas the semiconductor chip of the second-type layer portion may be a malfunctioning one. In such a case, the semiconductor chip may have a plurality of electrode pads. The first type layer portion may further include a first-type insulating layer disposed around the plurality of electrode pads. The first-type insulating layer may have a plurality of openings for exposing the plurality of electrode pads. The plurality of first-type electrodes may be electrically connected to the plurality of electrode pads through the plurality of openings. The second-type layer portion may further include a second-type insulating layer that covers the plurality of electrode pads so as to avoid exposure.

If the layered chip packages are configured as described above, the step of fabricating the layered substructure may include, as a series of steps for forming each of the substructures, the steps of fabricating a pre-substructure wafer that includes an array of a plurality of pre-semiconductor-chip portions, the pre-semiconductor-chip portions being intended to become the semiconductor chips, respectively; distinguishing the plurality of pre-semiconductor-chip portions included in the pre-substructure wafer into normally functioning pre-semiconductor-chip portions and malfunctioning pre-semiconductor-chip portions; and forming the first-type insulating layer and the first-type electrodes in the normally functioning pre-semiconductor-chip portions while forming the second-type insulating layer and the second-type electrodes in the malfunctioning pre-semiconductor-chip portions, so that the pre-substructure wafer is made into the substructure.

A composite layered chip package of the present invention includes a plurality of subpackages stacked, every vertically adjacent two of the subpackages being electrically connected to each other. Each of the plurality of subpackages includes: a main body having a top surface, a bottom surface and four side surfaces; and wiring disposed on at least one of the side surfaces of the main body. The main body includes: a main part that includes at least one first-type layer portion and has a top surface and a bottom surface; and a plurality of first terminals that are disposed on the top surface of the main part and electrically connected to the wiring. In at least one of the plurality of subpackages, the main part further includes at least one second-type layer portion.

Each of the first-type and second-type layer portions includes a semiconductor chip. The first-type layer portion further includes a plurality of first-type electrodes that are electrically connected to the semiconductor chip and to the wiring. The second-type layer portion further includes a plurality of second-type electrodes that are electrically connected to the wiring and not to the semiconductor chip. The plurality of first terminals are formed by using the plurality of first-type or second-type electrodes of the uppermost one of the layer portions in each of the subpackages. For any vertically adjacent two of the subpackages, the main body of the upper one of the subpackages further includes a plurality of second terminals that are disposed on the bottom surface of the main part and electrically connected to the wiring. The plurality of second terminals of the upper one of the subpackages are electrically connected to the plurality of first terminals of the lower one of the subpackages.

In the composite layered chip package of the present invention, the semiconductor chip of the first-type layer portion may be a normally functioning one, whereas the semiconductor chip of the second-type layer portion may be a malfunctioning one.

In the composite layered chip package of the present invention, the semiconductor chip may have a plurality of electrode pads. In such a case, the first-type layer portion may further include a first-type insulating layer disposed around the plurality of electrode pads. The first-type insulating layer may have a plurality of openings for exposing the plurality of electrode pads. The plurality of first-type electrodes may be electrically connected to the plurality of electrode pads through the plurality of openings. The second-type layer portion may further include a second-type insulating layer that covers the plurality of electrode pads so as to avoid exposure.

In the composite layered chip package of the present invention, for any vertically adjacent two of the subpackages, at least either the second terminals of the upper one of the subpackages or the first terminals of the lower one of the subpackages may each include a solder layer made of a solder material, the solder layer being exposed in a surface of each of the first terminals or each of the second terminals.

In the composite layered chip package of the present invention, the semiconductor chip may have four side surfaces. Each of the first-type and second-type layer portions may further include an insulating portion that covers at least one of the four side surfaces of the semiconductor chip. In such a case, the insulating portion may have at least one end face that is located in the at least one of the side surfaces of the main body on which the wiring is disposed.

A method of manufacturing the composite layered chip package of the present invention includes the steps of fabricating the plurality of subpackages; and stacking the plurality of subpackages and, for any vertically adjacent two of the subpackages, electrically connecting the plurality of second terminals of the upper one of the subpackages to the plurality of first terminals of the lower one of the subpackages.

For any vertically adjacent two of the subpackages, at least either the second terminals of the upper one of the subpackages or the first terminals of the lower one of the subpackages may each include a solder layer made of a solder material, the solder layer being exposed in a surface of each of the first terminals or each of the second terminals. In such a case, in the step of electrically connecting the plurality of second terminals of the upper one of the subpackages to the plurality of first terminals of the lower one of the subpackages, the solder layer may be heated to melt and then solidified to electrically connect the plurality of second terminals to the plurality of first terminals.

In the layered chip package of the present invention, the plurality of layer portions include at least one first-type layer portion and at least one second-type layer portion. The first-type layer portion includes a plurality of first-type electrodes that are electrically connected to the semiconductor chip and to the wiring. The second-type layer portion includes a plurality of second-type electrodes that are electrically connected to the wiring and not to the semiconductor chip. The plurality of first terminals are formed by using the plurality of first-type or second-type electrodes of the uppermost one of the layer portions. According to the layered chip package and the method of manufacturing the same of the present invention, it is possible to prevent malfunctioning semiconductor chips from being electrically connected to the wiring. The plurality of first terminals of the layered chip package of the present invention can be used to electrically connect the layered chip package with another layered chip package. This makes it possible to easily implement a package that includes a plurality of semiconductor chips stacked and that is capable of providing, even if it includes a malfunctioning semiconductor chip, the same functions as those for the case where no malfunctioning semiconductor chip is included.

According to the composite layered chip package and the method of manufacturing the same of the present invention, a plurality of subpackages can be stacked to easily implement a package that includes a plurality of semiconductor chips stacked and that is capable of providing, even if it includes a malfunctioning semiconductor chip, the same functions as those for the case where no malfunctioning semiconductor chip is included.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

Preferred embodiments of the present invention will now be described in detail with reference to the drawings. First, reference is made toFIG. 1toFIG. 5to describe the configuration of a composite layered chip package according to a first embodiment of the invention.FIG. 1is a perspective view of the composite layered chip package according to the first embodiment of the invention.FIG. 2is a perspective view showing the composite layered chip package ofFIG. 1as viewed from below.FIG. 3is an exploded perspective view of the composite layered chip package ofFIG. 1.FIG. 4is an exploded perspective view of the composite layered chip package ofFIG. 2.FIG. 5is a side view of the composite layered chip package ofFIG. 1.

The composite layered chip package1according to the present embodiment includes a plurality of subpackages stacked, every two vertically adjacent subpackages being electrically connected to each other.FIG. 1toFIG. 5show an example where the composite layered chip package1includes two subpackages1A and1B, the subpackage1B lying on the top of the subpackage1A.FIG. 3andFIG. 4show the state where the subpackages1A and1B are separated from each other. In the following description, any subpackage will be designated by reference symbol1S.

Each of the subpackages1A and1B includes a main body2having a top surface2a, a bottom surface2b, and four side surfaces2c,2d,2eand2f. The side surfaces2cand2dare mutually opposite to each other. The side surfaces2eand2fare mutually opposite to each other. Each of the subpackages1A and1B further includes wiring3disposed on at least one of the side surfaces of the main body2. In the example shown inFIG. 1toFIG. 5, the wiring3is disposed on the two mutually opposite side surfaces2cand2d. The main body2has a main part2M. The main part2M includes at least one first-type layer portion10A, and has a top surface2Ma and a bottom surface2Mb.

The main body2further has a plurality of first terminals4that are disposed on the top surface2Ma of the main part2M and electrically connected to the wiring3. Of the subpackages1A and1B, at least the upper subpackage1B has its main body2further having a plurality of second terminals5. The second terminals5are disposed on the bottom surface2Mb of the main part2M and electrically connected to the wiring3. In the example shown inFIG. 1toFIG. 5, the main bodies2of both the subpackages1A and1B each have the plurality of first terminals4and the plurality of second terminals5. The plurality of second terminals5of the upper subpackage1B are electrically connected to the plurality of first terminals4of the lower subpackage1A.

The composite layered chip package1may include a sealing part that is made of an insulating material and fills the gap between the subpackages1A and1B.

When the composite layered chip package1includes three or more subpackages1S stacked, any two vertically adjacent subpackages1S shall be configured so that the main body2of at least the upper subpackage1S has the plurality of second terminals5, and the plurality of second terminals5of the upper subpackage1S are electrically connected to the plurality of first terminals4of the lower subpackage1S.

In a subpackage1S, at least either the terminals4or the terminals5may each include a solder layer made of a solder material, the solder layer being exposed in the surface of each of the terminals4or each of the terminals5. In particular, given any two vertically adjacent subpackages1S, it is preferred that at least either the second terminals5of the upper subpackage1S or the first terminals4of the lower subpackage1S each include the solder layer that is exposed in the surface of each of the terminals4or each of the terminals5. In such a case, the solder layer is heated to melt and then solidified, whereby the plurality of second terminals5of the upper subpackage1S are electrically connected to the plurality of first terminals4of the lower subpackage1S.

The main part2M of the main body2of at least one of the plurality of subpackages1S further includes at least one second-type layer portion10B. As will be described in detail later, each of the first-type layer portion10A and the second-type layer portion10B includes a semiconductor chip. The semiconductor chip of the first-type layer portion10A is a normally functioning one, whereas the semiconductor chip of the second-type layer portion10B is a malfunctioning one.

The first-type layer portion10A further includes a plurality of first-type electrodes that are electrically connected to the semiconductor chip and to the wiring3. The second-type layer portion10B further includes a plurality of second-type electrodes that are electrically connected to the wiring3and not to the semiconductor chip. Each of the first-type and second-type electrodes has an end face located in the at least one of the side surfaces of the main body2on which the wiring3is disposed. Hereinafter, any layer portion will be designated by reference numeral10. The plurality of first terminals4are formed by using the plurality of first-type or second-type electrodes of the uppermost layer portion10of the subpackage1S.

In the example shown inFIG. 1toFIG. 5, the main part2M of the main body2of the subpackage1A includes six first-type layer portions10A and two second-type layer portions10B, whereas the main part2M of the main body2of the subpackage1B includes two first-type layer portions10A and no second-type layer portion10B.

When the main part2M of the main body2includes a plurality of layer portions regardless of the types of the layer portions, the plurality of layer portions are stacked on each other between the top surface2Ma and the bottom surface2Mb of the main part2M. Every two vertically adjacent layer portions are bonded to each other with an adhesive, for example.

With a plurality of layer portions10included in the main part2M of its main body2, a subpackage1S itself is a layered chip package, which is combined with one or more other subpackages1S to form the composite layered chip package1.

FIG. 6is a perspective view showing a part of a single layer portion10. As shown inFIG. 6, the layer portion10includes a semiconductor chip30. The semiconductor chip30has: a first surface30awith a device formed thereon; a second surface30bopposite to the first surface30a; a first side surface30cand a second side surface30dthat are mutually opposite to each other; and a third side surface30eand a fourth side surface30fthat are mutually opposite to each other. The side surfaces30c,30d,30e, and30fface toward the side surfaces2c,2d,2e, and2fof the main body2, respectively.

The layer portion10further includes an insulating portion31and a plurality of electrodes32. The insulating portion31covers at least one of the four side surfaces of the semiconductor chip30. The insulating portion31has at least one end face31athat is located in the at least one of the side surfaces of the main body2on which the wiring is disposed. In the example shown inFIG. 6, the insulating portion31covers all of the four side surfaces of the semiconductor chip30, and has four end faces31alocated in the four side surfaces of the main body2.

In the first-type layer portion10A, the plurality of electrodes32are electrically connected to the semiconductor chip30and to the wiring3. In the second-type layer portion10B, on the other hand, the plurality of electrodes32are electrically connected to the wiring3and not to the semiconductor chip30. The electrodes32have their respective end faces32clocated in the at least one of the side surfaces of the main body2on which the wiring3is disposed. The wiring3is electrically connected to the end faces32c. The plurality of electrodes32of the first-type layer portion10A correspond to the first-type electrodes described above. The plurality of electrodes32of the second-type layer portion10B correspond to the second-type electrodes described above. Hereinafter, the first-type electrodes will be designated by reference symbol32A, and the second-type electrodes will be designated by reference symbol32B.

As previously mentioned, the semiconductor chip30of the first-type layer portion10A is a normally functioning one whereas the semiconductor chip30of the second-type layer portion10B is a malfunctioning one. Hereinafter, a normally functioning semiconductor chip30will be referred to as a conforming semiconductor chip30, and a malfunctioning semiconductor chip30will be referred to as a defective semiconductor chip30.

In each of the layer portions10other than the uppermost layer portion10in a main body2, the insulating portion31also covers the first surface30aof the semiconductor chip30and the plurality of electrodes32. In the uppermost layer portion10in a main body2, the insulating portion31covers neither the first surface30aof the semiconductor chip30nor the plurality of electrodes32. The plurality of electrodes32of the uppermost layer portion10are thus exposed. The first terminals4are formed by using the plurality of electrodes32, i.e., the plurality of first-type electrodes32A or second-type electrodes32B, of the uppermost layer portion10.

The semiconductor chip30may be a memory chip that constitutes a memory such as a flash memory, DRAM, SRAM, MRAM, PROM, or FeRAM. In such a case, it is possible to implement a large-capacity memory by using the composite layered chip package1including a plurality of semiconductor chips30. With the composite layered chip package1according to the present embodiment, it is also possible to easily implement a memory of various capacities such as 64 GB (gigabytes), 128 GB, and 256 GB, by changing the number of the semiconductor chips30to be included in the composite layered chip package1.

Suppose that the semiconductor chip30includes a plurality of memory cells. In this case, even if one or more of the memory cells are defective, the semiconductor chip30is still conforming if it can function normally by employing the redundancy technique.

The semiconductor chips30are not limited to memory chips, and may be used for implementing other devices such as CPUs, sensors, and driving circuits for sensors. The composite layered chip package1according to the present embodiment is particularly suitable for implementing an SiP.

Reference is now made toFIG. 7to describe an example of device included in the semiconductor chip30. By way of example, the following description will be given for a case where the device included in the semiconductor chip30is a circuit including a plurality of memory cells that constitute a memory.FIG. 7shows one of the plurality of memory cells. The memory cell40includes a source42and a drain43formed near a surface of a P-type silicon substrate41. The source42and the drain43are both N-type regions. The source42and the drain43are disposed at a predetermined distance from each other so that a channel composed of a part of the P-type silicon substrate41is provided between the source42and the drain43. The memory cell40further includes an insulating film44, a floating gate45, an insulating film46, and a control gate47that are stacked in this order on the surface of the substrate41at the location between the source42and the drain43. The memory cell40further includes an insulating layer48that covers the source42, the drain43, the insulating film44, the floating gate45, the insulating film46and the control gate47. The insulating layer48has contact holes that open in the tops of the source42, the drain43and the control gate47, respectively. The memory cell40includes a source electrode52, a drain electrode53, and a control gate electrode57that are formed on the insulating layer48at locations above the source42, the drain43and the control gate47, respectively. The source electrode52, the drain electrode53and the control gate electrode57are connected to the source42, the drain43and the control gate47, respectively, through the corresponding contact holes.

Next, a description will be given of a method of manufacturing the composite layered chip package1according to the present embodiment. The method of manufacturing the composite layered chip package1according to the embodiment includes the steps of fabricating a plurality of subpackages1S; and stacking the plurality of subpackages1S and, for any two vertically adjacent subpackages1S, electrically connecting the plurality of second terminals5of the upper subpackage1S to the plurality of first terminals4of the lower subpackage1S.

The step of fabricating a plurality of subpackages1S includes, as a series of steps for forming each subpackage1S, the steps of fabricating at least one substructure that includes an array of a plurality of preliminary layer portions, each of the preliminary layer portions being intended to become any one of the layer portions10included in the main part2M, the substructure being intended to be cut later at the positions of the boundaries between adjacent preliminary layer portions; and forming the subpackage1S from the at least one substructure.

Now, with reference toFIG. 8toFIG. 22, a detailed description will be given of the step of fabricating at least one substructure. The following description will be given for a case where a plurality of substructures are fabricated. In the step of fabricating at least one substructure, a pre-substructure wafer101is initially fabricated. The pre-substructure wafer101includes an array of a plurality of pre-semiconductor-chip portions30P that are intended to become individual semiconductor chips30.FIG. 8is a plan view of the pre-substructure wafer101.FIG. 9is a magnified plan view of a part of the pre-substructure wafer101shown inFIG. 8.FIG. 10shows a cross section taken along line10-10ofFIG. 9.

Specifically, in the step of fabricating the pre-substructure wafer101, a semiconductor wafer100having two mutually opposite surfaces is subjected to processing, such as a wafer process, at one of the two surfaces. This forms the pre-substructure wafer101including an array of a plurality of pre-semiconductor-chip portions30P, each of the pre-semiconductor-chip portions30P including a device. In the pre-substructure wafer101, the plurality of pre-semiconductor-chip portions30P may be in a row, or in a plurality of rows such that a number of pre-semiconductor-chip portions30P are arranged both in vertical and horizontal directions. In the following description, assume that the plurality of pre-semiconductor-chip portions30P in the pre-substructure wafer101are in a plurality of rows such that a number of pre-semiconductor-chip portions30P are arranged both in vertical and horizontal directions. The semiconductor wafer100may be a silicon wafer, for example. The wafer process is a process in which a semiconductor wafer is processed into a plurality of devices that are not yet separated into a plurality of chips. For ease of understanding,FIG. 8depicts the pre-semiconductor chip portions30P larger relative to the semiconductor wafer100. For example, if the semiconductor wafer100is a 12-inch wafer and the top surface of each pre-semiconductor-chip portion30is 8 to 10 mm long at each side, then 700 to 900 pre-semiconductor-chip portions30P are obtainable from a single semiconductor wafer100.

As shown inFIG. 10, the pre-semiconductor-chip portions30P include a device-forming region33that is formed near one of the surfaces of the semiconductor wafer100. The device-forming region33is a region where devices are formed by processing the one of the surfaces of the semiconductor wafer100. The pre-semiconductor-chip portions30P further include a plurality of electrode pads34disposed on the device-forming region33, and a passivation film35disposed on the device-forming region33. The passivation film35is made of an insulating material such as phospho-silicate-glass (PSG), silicon nitride, or polyimide resin. The passivation film35has a plurality of openings for exposing the top surfaces of the plurality of electrode pads34. The plurality of electrode pads34are located in the positions corresponding to the plurality of electrodes32to be formed later, and are electrically connected to the devices formed in the device-forming region33. Hereinafter, the surface of the pre-substructure wafer101located closer to the plurality of electrode pads34and the passivation film35will be referred to as a first surface101a, and the opposite surface will be referred to as a second surface101b.

In the step of fabricating at least one substructure, next, a wafer sort test is performed to distinguish the plurality of pre-semiconductor-chip portions30P included in the pre-substructure wafer101into normally functioning pre-semiconductor-chip portions and malfunctioning pre-semiconductor-chip portions. In this step, a probe of a testing device is brought into contact with the plurality of electrode pads34of each pre-semiconductor-chip portion30P so that whether the pre-semiconductor-chip portion30P functions normally or not is tested with the testing device. InFIG. 8, the pre-semiconductor-chip portions30P marked with “NG” are malfunctioning ones, and the other pre-semiconductor-chip portions30P are normally functioning ones. This step provides location information on the normally functioning pre-semiconductor-chip portions30P and the malfunctioning pre-semiconductor-chip portions30P in each pre-substructure wafer101. The location information is used in a step to be performed later. The passivation film35may be formed after the wafer sort test, and may thus be yet to be formed at the time of performing the wafer sort test.

FIG. 11is a plan view showing a step that follows the step shown inFIG. 9.FIG. 12shows a cross section taken along line12-12ofFIG. 11. In this step, a protection layer103is initially formed to cover the first surface101aof the pre-substructure wafer101. The protection layer103is formed of a photoresist, for example. Next, a plurality of grooves104that open in the first surface101aof the pre-substructure wafer101are formed in the pre-substructure wafer101so as to define the respective areas of the plurality of pre-semiconductor-chip portions30P. Note that the protection layer103is omitted inFIG. 11.

In the positions of the boundaries between every two adjacent pre-semiconductor-chip portions30P, the grooves104are formed to pass through the boundaries between every two adjacent pre-semiconductor-chip portions30P. The grooves104are formed such that their bottoms do not reach the second surface101bof the pre-substructure wafer101. The grooves104have a width in the range of 50 to 150 μm, for example. The grooves104have a depth in the range of 20 to 80 μm, for example.

The grooves104may be formed using a dicing saw or by performing etching, for example. The etching may be reactive ion etching or anisotropic wet etching using KOH as the etching solution, for example. When forming the grooves104by etching, the protection layer103made of photoresist may be patterned by photolithography to form the etching mask. The protection layer103is removed after the formation of the grooves104. A pre-polishing substructure main body105is thus formed by the pre-substructure wafer101with the plurality of grooves104formed therein.

FIG. 13shows a step that follows the step shown inFIG. 12. In this step, an insulating film106P is formed to fill the plurality of grooves104of the pre-polishing substructure main body105and to cover the plurality of electrode pads34and the passivation film35. The insulating film106P is to become a part of the insulating portion31later. The insulating film106P may be formed of a resin such as an epoxy resin or a polyimide resin. The insulating film106P may also be formed of a photosensitive material such as a sensitizer-containing polyimide resin. The insulating film106P may also be formed of an inorganic material such as silicon oxide or silicon nitride.

The insulating film106P is preferably formed of a resin having a low thermal expansion coefficient. If the insulating film106P is formed of a resin having a low thermal expansion coefficient, it becomes easy to cut the insulating film106P when it is cut later with a dicing saw.

The insulating film106P is preferably transparent. If the insulating film106P is transparent, alignment marks that are recognizable through the insulating film106P can be formed on the insulating film106P. Such alignment marks facilitates alignment of a plurality of substructures to be stacked.

The insulating film106P may include a first layer that fills the plurality of grooves104and a second layer that covers the first layer, the plurality of electrode pads34and the passivation film35. In such a case, the first layer and the second layer may be formed of the same material or different materials. The first layer is preferably formed of a resin having a low thermal expansion coefficient. The second layer may be formed of a photosensitive material such as a sensitizer-containing polyimide resin. The first layer may be flattened at the top by, for example, ashing or chemical mechanical polishing (CMP), before forming the second layer on the first layer.

If the passivation film35is not formed by the time of performing the wafer sort test, the second layer of the insulating film106P may be used as the passivation film. In such a case, the second layer may be formed of an inorganic material such as silicon oxide or silicon nitride. If the second layer of the insulating film106P is to be used as the passivation film, the plurality of openings for exposing the top surfaces of the plurality of electrode pads34are not formed in the second layer as initially formed.

Reference is now made toFIG. 14andFIG. 15to describe the step of forming the plurality of openings for exposing the plurality of electrode pads34in the insulating film106P in the normally-functioning pre-semiconductor-chip portions30P.FIG. 14shows a step that follows the step shown inFIG. 13.FIG. 15shows a step that follows the step shown inFIG. 14.

Here, a description will initially be given of a case where the entire insulating film106P or the second layer of the insulating film106P is formed of a negative photosensitive material and the openings are formed in the insulating film106P by photolithography. In this case, all the pre-semiconductor-chip portions30P are simultaneously subjected to the exposure of the insulating film106P by using a mask201A shown inFIG. 14. The mask201A has such a pattern that the areas of the insulating film106P where to form the openings are not irradiated with light while the other areas are irradiated with light. The non-irradiated areas of the insulating film106P are soluble in a developing solution, and the irradiated areas become insoluble in the developing solution.

Next, using a stepping projection exposure apparatus, or a so-called stepper, the insulating film106P is selectively exposed in the malfunctioning pre-semiconductor-chip portions30P only, using a mask201B shown inFIG. 14. This exposure process uses the location information on the normally functioning pre-semiconductor-chip portions30P and the malfunctioning pre-semiconductor-chip portions30P in each pre-substructure wafer101which was obtained by the wafer sort test. InFIG. 14, the pre-semiconductor-chip portion30P on the left is a normally functioning one, whereas the pre-semiconductor-chip portion30P on the right is a malfunctioning one. The mask201B entirely transmits light. As a result of this exposure process, the entire insulating film106P in the malfunctioning pre-semiconductor-chip portions30P becomes insoluble in the developing solution.

Next, the insulating film106P is developed with the developing solution. As a result, as shown inFIG. 15, a plurality of openings106afor exposing the plurality of electrode pads34are formed in the insulating film106P in the normally functioning pre-semiconductor chip portion30P (the left side). On the other hand, no openings106P are formed in the insulating film106P in the malfunctioning pre-semiconductor chip portion30P (the right side). After the development, the area of the insulating film106P corresponding to the normally functioning pre-semiconductor chip portion30P becomes a first-type insulating layer106A, and the area corresponding to the malfunctioning pre-semiconductor chip portion30P becomes a second-type insulating layer106B. The first-type insulating layer106A has the plurality of openings106afor exposing the plurality of electrode pads34, and is disposed around the plurality of electrode pads34. The second-type insulating layer106B covers the plurality of electrode pads34so as to avoid exposure.

Now, an example of the method for forming the plurality of openings106ain the insulating film106P will be described for the case where the entire insulating film106P or the second layer of the insulating film106P is formed of a non-photosensitive material. In the example, a negative photoresist layer is initially formed on the insulating film106P. The photoresist layer is then exposed and developed by the same method as with the exposure and development of the foregoing insulating film106P. Consequently, in the normally functioning pre-semiconductor-chip portions30P, a plurality of openings are formed in the photoresist layer at positions corresponding to the plurality of electrode pads34. Meanwhile, no opening is formed in the photoresist layer in the malfunctioning pre-semiconductor-chip portions30P. Next, the insulating film106P is selectively etched by using the photoresist layer as the etching mask, whereby the plurality of openings106aare formed in the insulating film106P. The photoresist layer may be subsequently removed, or may be left and used as part of the insulating layers106A and106B.

FIG. 16andFIG. 17show a step that follows the step shown inFIG. 15. In this step, the plurality of electrodes32are formed on the insulating layers106A and106B by plating, for example. In the normally functioning pre-semiconductor chip portions30P, the plurality of electrodes32are electrically connected to the respective corresponding electrode pads34through the plurality of openings106aof the insulating layer106A. The plurality of electrodes32in the normally functioning pre-semiconductor-chip portions30P become the first-type electrodes32A. In the malfunctioning pre-semiconductor-chip portions30P, on the other hand, the plurality of electrodes32are not electrically connected to the corresponding electrode pads34since no openings106aare formed in the insulating layer106B. The plurality of electrodes32in the malfunctioning pre-semiconductor-chip portions30P become the second-type electrodes32B. A pre-polishing substructure109shown inFIG. 16andFIG. 17is fabricated thus. The pre-polishing substructure109has a first surface109acorresponding to the first surface101aof the pre-substructure wafer101, and a second surface109bcorresponding to the second surface101bof the pre-substructure wafer101.

The electrodes32are formed of a conductive material such as Cu. In the case of forming the electrodes32by plating, a seed layer for plating is initially formed. Next, a photoresist layer is formed on the seed layer. The photoresist layer is then patterned by photolithography to form a frame that has a plurality of openings for the plurality of electrodes32to be accommodated in later. Next, plating layers that are intended to constitute respective portions of the electrodes32are formed by plating on the seed layer in the openings of the frame. The plating layers are 5 to 15 μm thick, for example. Next, the frame is removed, and portions of the seed layer other than those lying under the plating layers are also removed by etching. The plating layers and the remaining portions of the seed layer under the plating layers thus form the electrodes32.

FIG. 18shows a step that follows the step shown inFIG. 16. In this step, using an insulating adhesive, the pre-polishing substructure109is bonded to a plate-shaped jig112shown inFIG. 18, with the first surface109aof the pre-polishing substructure109arranged to face a surface of the jig112. The pre-polishing substructure109bonded to the jig112will hereinafter be referred to as a first pre-polishing substructure109. InFIG. 18, the reference numeral113indicates an insulating layer formed by the adhesive.

FIG. 19shows a step that follows the step shown inFIG. 18. In this step, the second surface109bof the first pre-polishing substructure109is polished. This polishing is performed until the plurality of grooves104are exposed. The broken line inFIG. 18indicates the level of the second surface109bafter the polishing. By polishing the second surface109bof the first pre-polishing substructure109, the first pre-polishing substructure109is thinned. This forms a substructure110in the state of being bonded to the jig112. The substructure110has a thickness of 20 to 80 μm, for example. Hereinafter, the substructure110bonded to the jig112will be referred to as a first substructure110. The first substructure110has a first surface110acorresponding to the first surface109aof the first pre-polishing substructure109, and a second surface110bopposite to the first surface110a. The second surface110bis the polished surface. By polishing the second surface109bof the first pre-polishing substructure109until the plurality of grooves104are exposed, the plurality of pre-semiconductor-chip portions30P are separated from each other into individual semiconductor chips30.

FIG. 20shows a step that follows the step shown inFIG. 19. In this step, using an insulating adhesive, a pre-polishing substructure109is initially bonded to the first substructure110bonded to the jig112. The pre-polishing substructure109is bonded to the first substructure110with the first surface109aarranged to face the polished surface, i.e., the second surface110b, of the first substructure110. Hereinafter, the pre-polishing substructure109to be bonded to the first substructure110will be referred to as a second pre-polishing substructure109. The insulating layer113formed by the adhesive between the first substructure110and the second pre-polishing substructure109covers the plurality of electrodes32of the second pre-polishing substructure109, and is to become part of the insulating portion31later.

Next, although not shown, the second surface109bof the second pre-polishing substructure109is polished. This polishing is performed until the plurality of grooves104are exposed. By polishing the second surface109bof the second pre-polishing substructure109, the second pre-polishing substructure109is thinned. This forms a second substructure110in the state of being bonded to the first substructure110. The second substructure110has a thickness of, for example, 20 to 80 μm, as does the first substructure110.

The same step as shown inFIG. 20may subsequently be repeated to form three or more substructures110into a stack.FIG. 21shows the case where four substructures110are formed into a stack.

FIG. 22shows a step that follows the step shown inFIG. 21. After the same step as shown inFIG. 20is repeated to form a predetermined number of substructures110into a stack, the stack of the predetermined number of substructures110is released from the jig112.FIG. 22shows an example where a stack of eight substructures110is formed.

Next, as shown inFIG. 22, the insulating layer113is removed from the uppermost substructure110of the stack. This exposes the plurality of electrodes32of the uppermost substructure110. The plurality of first terminals4are formed by using the plurality of electrodes32thus exposed.

The plurality of second terminals5are formed on the bottom surface of the lowermost substructure110of the stack. The terminals5are formed of a conductive material such as Cu or Au. The terminals5are formed by the same method as for the electrodes32, i.e., by plating.

At least either the terminals4or the terminals5may each include a solder layer made of a solder material, the solder layer being exposed in the surface of each of the terminals4or each of the terminals5. An example of the solder material is AuSn. The solder layer has a thickness in the range of 1 to 2 μm, for example. If the terminals4are to include the solder layer, the solder layer is formed on the surface of each of the electrodes32of the uppermost substructure110directly or via an underlayer. The solder layer is formed by plating, for example. If the terminals5are to include the solder layer, a conductor layer that is to become portions of the terminals5is formed on the bottom surface of the lowermost substructure110of the stack, using a conductive material such as Cu or Au. The solder layer is then formed on the surface of the conductor layer directly or via an underlayer by plating, for example.

AuSn is highly adhesive to Au. When either the terminals4or the terminals5each include a solder layer made of AuSn, it is preferred that the other of the terminals4and5each include an Au layer that is exposed in the surface of each of the terminals4or5. The Au layer is formed by plating or sputtering, for example. The melting point of AuSn varies according to the ratio between Au and Sn. For example, if the ratio between Au and Sn is 1:9 by weight, AuSn has a melting point of 217° C. If the ratio between Au and Sn is 8:2 by weight, AuSn has a melting point of 282° C.

Consequently, there is formed a first layered substructure115including a plurality of substructures110stacked. Each of the substructures110includes an array of a plurality of preliminary layer portions10P. Each of the preliminary layer portions10P is to become any one of the layer portions10included in the main part2M of the main body2. The substructures110are to be cut later in the positions of the boundaries between every adjacent preliminary layer portions10P. InFIG. 22, the reference symbol110C indicates the cutting positions in the substructures110. The first layered substructure115includes an array of a plurality of pre-separation main bodies2P that are to be separated from each other into individual main bodies2later. In the example shown inFIG. 22, each of the pre-separation main bodies2P includes eight preliminary layer portions10P.

Now, the process for fabricating a subpackage by using at least one substructure will be described in detail with reference toFIG. 23toFIG. 33. The following will describe an example where the first layered substructure115ofFIG. 22, which includes eight substructures110stacked, is used to fabricate a plurality of subpackages each including eight layer portions10.

FIG. 23andFIG. 24show a step that follows the step shown inFIG. 22. In this step, a plurality of first layered substructures115are stacked and every two vertically adjacent first layered substructures115are bonded to each other, whereby a second layered substructure120is fabricated.FIG. 23andFIG. 24show an example where ten first layered substructures115are stacked to fabricate the second layered substructure120. Every two vertically adjacent first layered substructures115are bonded to each other with an adhesive so as to be easily detachable. In this example, as shown inFIG. 24, the second layered substructure120includes ten first layered substructures115stacked, each of the first layered substructures115including eight substructures110stacked. That is, the second layered substructure120includes 80 substructures110stacked. Suppose that each individual substructure110has a thickness of 50 μm. Ignoring the thickness of the adhesive that bonds every two vertically adjacent substructures110to each other and the thickness of the adhesive that bonds every two vertically adjacent first layered substructures115to each other, the second layered substructure120has a thickness of 50 μm×80, i.e., 4 mm.

FIG. 25shows a step that follows the step shown inFIG. 23andFIG. 24. In this step, the second layered substructure120is cut into at least one block121in which a plurality of pre-separation main bodies2P are arranged both in the direction of stacking of the first layered substructures115and in a direction orthogonal thereto.FIG. 25shows an example of the block121. In the block121shown inFIG. 25, ten pre-separation main bodies2P are arranged in the direction of stacking of the first layered substructures115, and four are arranged in the direction orthogonal to the direction of stacking of the first layered substructures115. In this example, the block121includes 40 pre-separation main bodies2P.

FIG. 26shows a step that follows the step shown inFIG. 25. In this step, a plurality of jigs122are used to arrange two or more blocks121to form a block assembly130. The plurality of jigs122are combined to form a frame for surrounding the block assembly130.FIG. 26shows an example where 19 blocks121shown inFIG. 25are arranged to form the block assembly130. In this example, the block assembly130includes 19 blocks121, each of the blocks121includes 40 pre-separation main bodies2P, and each of the pre-separation main bodies2P includes 8 preliminary layer portions10P. That is, the block assembly130includes 19×40, i.e., 760 pre-separation main bodies2P, and 19×40×8, i.e., 6080 preliminary layer portions10P. All the pre-separation main bodies2P included in the block assembly130are arranged so that their respective surfaces on which the wiring3is to be formed later face toward the same direction, i.e., upward.

FIG. 27shows a step that follows the step shown inFIG. 26. In this step, a plurality of block assemblies130are arranged in one plane by using a plurality of jigs122. Here, all the pre-separation main bodies2P included in the plurality of block assemblies130are arranged so that their respective surfaces on which the wiring3is to be formed later face toward the same direction, i.e., upward.FIG. 27shows an example where 16 block assemblies130are arranged in one plane. In such a case, the 16 block assemblies130include 760×16, i.e., 12160 pre-separation main bodies2P, and 6080×16, i.e., 97280 preliminary layer portions10P.

In the present embodiment, the wiring3is then simultaneously formed on all the pre-separation main bodies2P that are included in the plurality of block assemblies130arranged as shown inFIG. 27. The step of forming the wiring3will be described with reference toFIG. 28toFIG. 32.

In the step of forming the wiring3, as shown inFIG. 28, the plurality of jigs122and the plurality of block assemblies130shown inFIG. 27are placed on a flat top surface of a jig132. The plurality of block assemblies130are thereby arranged in one plane. In such a state, the top surfaces of the jigs122are located at a level slightly lower than that of the top surfaces of the block assemblies130.

In the step of forming the wiring3, a resin layer133is then formed to cover the top surfaces of the jigs122and the top surfaces of the block assemblies130. The resin layer133may be formed by applying an uncured resin and then curing the resin, or by using a dry film.

FIG. 29shows a step that follows the step shown inFIG. 28. In this step, the resin layer133is polished by, for example, CMP, until the top surfaces of the plurality of block assemblies130are exposed. The top surfaces of the plurality of block assemblies130and the top surface of the resin layer133are thereby made even with each other.

FIG. 30shows a step that follows the step shown inFIG. 29. In this step, a seed layer134for plating is initially formed over the top surfaces of the plurality of block assemblies130and the resin layer133. Next, a photoresist layer is formed on the seed layer134. The photoresist layer is then patterned by photolithography to form a frame135. The frame135has a plurality of openings in which a plurality of units of wiring3corresponding to the plurality of pre-separation main bodies2P are to be accommodated later. Although not shown inFIG. 30, the frame135includes a plurality of portions located above the respective surfaces of all the pre-separation main bodies2P included in the plurality of block assemblies130on which the wiring3is to be formed. These plurality of portions have the respective openings to accommodate the wiring3later.

FIG. 31shows a step that follows the step shown inFIG. 30. In this step, a plating layer136to constitute part of the wiring3is initially formed in each of the openings of the frame135by plating. Next, the frame135is removed. For the sake of convenience,FIG. 31shows the plating layer136in a rectangular shape for each of the blocks121. Actually, however, the plating layer136is formed in a shape corresponding to the wiring3for each of the pre-separation main bodies2P.

FIG. 32shows a step that follows the step shown inFIG. 31. In this step, portions of the seed layer134other than those lying under the plating layers136are initially removed by etching. The plating layers136and the remaining portions of the seed layer134under the plating layers136thus form the wiring3. The wiring3is formed on each of the pre-separation main bodies2P. Next, the jigs122and the resin layer133remaining on the jigs122are removed.

If the wiring3is to be disposed on one of the side surfaces of the main body2, the process for forming the wiring3is completed by the steps shown inFIG. 28toFIG. 32. If the wiring3is to be disposed on two mutually opposite side surfaces of the main body2, the process shown inFIG. 28toFIG. 32can be repeated twice to form the wiring3on the two side surfaces.

The process for fabricating a subpackage1S then proceeds to the step of separating the plurality of pre-separation main bodies2P from each other. Here, the pre-separation main bodies2P each provided with the wiring3are separated from each other so that a plurality of subpackages1S are formed. This step will be described with reference toFIG. 33. In the step, the block121is initially cut in the positions of the boundaries between every two pre-separation main bodies2P that are adjacent to each other in the direction orthogonal to the direction of stacking of the pre-separation main bodies2P. This produces a plurality of stacks shown in portion (a) ofFIG. 33. Each of the stacks includes a plurality of pre-separation main bodies2P stacked. In each of the stacks, every two adjacent pre-separation main bodies2P are easily detachably bonded to each other by the adhesive that was used to bond every two vertically adjacent first layered substructures115when fabricating the second layered substructure120in the step shown inFIG. 23andFIG. 24. Next, the plurality of pre-separation main bodies2P included in the stack shown in portion (a) ofFIG. 33are separated from each other. This makes the pre-separation main bodies2P into main bodies2, whereby a plurality of subpackages1S, each of which includes the main body2and the wiring3, are formed. Portion (b) ofFIG. 33shows one of the subpackages1S.

A plurality of subpackages1S are thus formed through the series of steps that have been described with reference toFIG. 8toFIG. 33. So far the description has dealt with the case where a plurality of subpackages (layered chip packages)1S each including eight layer portions10are formed by using the first layered substructure115that includes eight stacked substructures110shown inFIG. 22. In the present embodiment, however, the number of the substructures110to be included in the first layered substructure115can be changed to form a plurality of types of subpackages (layered chip packages)1S with different numbers of layer portions10. Moreover, in the present embodiment, a structure composed of a single substructure110and a plurality of terminals5formed on its the bottom surface may be fabricated instead of the first layered substructure115, and such a structure may be used instead of the first layered substructure115to form a plurality of subpackages1S through the series of steps described with reference toFIG. 23toFIG. 33. In this case, each of the subpackages1S includes only a single layer portion10.

FIG. 34toFIG. 38show examples of a plurality of types of subpackages1S having different numbers of layer portions10that can be fabricated according to the present embodiment.FIG. 34shows a subpackage1S that includes eight layer portions10.FIG. 35shows a subpackage1S that includes only a single layer portion10.FIG. 36shows a subpackage1S that includes two layer portions10.FIG. 37shows a subpackage1S that includes three layer portions10.FIG. 38shows a subpackage1S that includes four layer portions10.

The subpackage1S of the present embodiment has the wiring3disposed on at least one of the side surfaces of the main body2. The main body2has the plurality of first terminals4disposed on the top surface2Ma of the main part2M. For any two vertically adjacent subpackages1S, the main body2of at least the upper subpackage1S further includes the plurality of second terminals5disposed on the bottom surface2Mb of the main part2M. Both the first terminals4and the second terminals5are electrically connected to the wiring3. With the subpackage1S of such a configuration, the first terminals4of one subpackage1S can be used to electrically connect the subpackage1S with another subpackage1S. For example, according to the present embodiment, it is possible to establish electrical connection between two or more subpackages1S by stacking the two or more subpackages1S on each other and electrically connecting the second terminals5of the upper one of two adjacent subpackages1S to the first terminals4of the lower one of the two adjacent subpackages1S.

According to the present embodiment, a plurality of subpackages1S can be mounted on a wiring board and electrical connection between the plurality of subpackages1S can be established by using the wiring of the wiring board and the second terminals5of the plurality of subpackages15. In such a case, the first terminals4of one of the subpackages1S can be electrically connected to those of another one of the subpackages1S by wire bonding, for example.

According to the present embodiment, it is possible to stack three or more subpackages1S and establish electrical connection therebetween.FIG. 39shows an example where four subpackages1S are stacked and electrically connected to each other.

Moreover, the present embodiment facilitates the alignment between every two vertically adjacent subpackages1S when stacking a plurality of subpackages1S. This advantageous effect will now be described with reference toFIG. 40andFIG. 41.FIG. 40is a side view showing connecting parts of the terminals of two vertically adjacent subpackages1S.FIG. 41is an explanatory diagram for explaining misalignment between the terminals of two vertically adjacent subpackages1S.

In the example shown inFIG. 40andFIG. 41, the terminal4includes a conductor pad4A of rectangular shape and an Au layer4B that is formed on the surface of the conductor pad4A. The conductor pad4A constitutes a part of the electrode32, and is made of Cu, for example. The terminal5includes a conductor pad5A of rectangular shape, an underlayer5B formed on the surface of the conductor pad5A, and a solder layer5C formed on the surface of the underlayer5B. For example, the conductor pad5A is made of Cu, the underlayer5B is made of Au, and the solder layer5C is made of AuSn. Alternatively, contrary to this example, it is possible that the terminal4includes a conductor pad, an underlayer and a solder layer, while the terminal5includes a conductor pad and an Au layer. Both of the terminals4and5may include a solder layer. Here, the lengths of two orthogonal sides of the conductor pad4A will be represented by L1and L2. L1and L2are both 40 to 80 μm, for example. The conductor pad5A has the same shape as that of the conductor pad4A.

In the example shown inFIG. 40, the corresponding terminals4and5of the two vertically adjacent subpackages1S are electrically connected in the following way. The Au layer4B and the solder layer5C of the corresponding terminals4and5are put into contact with each other. By applying heat and pressure, the solder layer5C is melted, and then solidified to bond the terminals4and5to each other.

FIG. 41shows a state where the terminals4and5are out of alignment. The state where the terminals4and5are out of alignment refers to the state where the edges of the conductor pad4A and those of the conductor pad5A do not coincide in position with each other when viewed in a direction perpendicular to the plane of the conductor pads4A and5A. In the present embodiment, the corresponding terminals4and5may be out of alignment as long as the terminals4and5can be bonded with a sufficiently small resistance at the interface between the terminals4and5. Assuming that L1and L2are 30 to 60 μm, the maximum permissible misalignment between the terminals4and5is smaller than L1and L2yet several tens of micrometers.

According to the present embodiment, some misalignment between the terminals4and5is thus acceptable when stacking a plurality of subpackages1S. This facilitates the alignment between two vertically adjacent subpackages1S. Consequently, according to the present embodiment, it is possible to reduce the manufacturing cost of an electronic component (including the composite layered chip package1according to the embodiment) that includes a plurality of subpackages1S stacked.

FIG. 42shows an example of a method of manufacturing an electronic component that includes a plurality of subpackages1S stacked. The method shown inFIG. 42uses a heatproof container141. The container141has an accommodating part141ain which a plurality of subpackages1S can be stacked and accommodated. The accommodating part141ahas such a size that the side surfaces of the subpackages1S accommodated in the accommodating part141aand the inner walls of the accommodating part141aleave a slight gap therebetween. In the method, a plurality of subpackages1S are stacked and accommodated in the accommodating part141aof the container141, and then the container141and the plurality of subpackages1S are heated at temperatures at which the solder layer melts (for example, 320° C.). This melts the solder layer, whereby the terminals4and5of every two vertically adjacent subpackages1S are bonded to each other. According to the method, a plurality of subpackages1S are stacked and accommodated in the accommodating part141aof the container141, whereby the plurality of subpackages1S can be easily aligned with each other. This makes it easy to manufacture an electronic component that includes a plurality of subpackages1S stacked.

The composite layered chip package1according to the present embodiment includes a plurality of subpackages1S stacked. For any two vertically adjacent subpackages1S of the composite layered package1, the plurality of second terminals5of the upper subpackage1S are electrically connected to the plurality of first terminals4of the lower subpackage1S. The main part2M of the main body2of each of the plurality of subpackages1S includes at least one first-type layer portion10A. The main part2M of the main body2of at least one of the plurality of subpackages1S further includes at least one second-type layer portion10B.

The first-type layer portion10A includes a conforming semiconductor chip30. The first-type layer portion10A includes a first-type insulating layer106A and a plurality of first-type electrodes32A. The first-type insulating layer106A has a plurality of openings106afor exposing a plurality of electrode pads34of the semiconductor chip30. The plurality of first-type electrodes32A are electrically connected to the semiconductor chip30and to the wiring3. The plurality of first-type electrodes32A are electrically connected to the plurality of electrode pads34of the semiconductor chip30through the plurality of openings106A of the first-type insulating layer106A. The conforming semiconductor chip30in the first-type layer portion10A is thus electrically connected to the wiring3through the plurality of first-type electrodes32A.

The second-type layer portion10B includes a defective semiconductor chip30. The second-type layer portion10B includes a second-type insulating layer106B and a plurality of second-type electrodes32B. The second-type insulating layer106B covers the plurality of electrode pads34of the semiconductor chip30so as to avoid exposure. The plurality of second-type electrodes32B are electrically connected to the wiring3and not to the semiconductor chip30. The defective semiconductor chip30in the second-type layer portion10B is not electrically connected to the wiring3.

The method of manufacturing the composite layered chip package1according to the present embodiment includes the steps of: fabricating a plurality of subpackages1S; and stacking the plurality of subpackages1S and, for any two vertically adjacent subpackages1S, electrically connecting the plurality of second terminals5of the upper subpackage1S to the plurality of first terminals4of the lower subpackage1S.

The step of fabricating a plurality of subpackages1S includes, as a series of steps for forming each of the subpackages1S, the steps of: fabricating at least one substructure110that includes an array of a plurality of preliminary layer portions10P, each of the preliminary layer portions10P being intended to become any one of the layer portions10included in the main part2M, the substructure110being intended to be cut later at the positions of the boundaries between every adjacent preliminary layer portions10P; and forming the subpackage1S from the at least one substructure110. The step of fabricating the at least one substructure110includes the steps of fabricating a pre-substructure wafer101that includes an array of a plurality of pre-semiconductor-chip portions30P, the pre-semiconductor-chip portions30P being intended to become the semiconductor chips30, respectively; and distinguishing the plurality of pre-semiconductor-chip portions30P included in the pre-substructure wafer101into normally functioning pre-semiconductor-chip portions30P and malfunctioning pre-semiconductor-chip portions30P. The step of fabricating the at least one substructure110further includes the step of forming the first-type insulating layer106A and the first-type electrodes32A in the normally functioning pre-semiconductor-chip portions30P while forming the second-type insulating layer106B and the second-type electrodes32B in the malfunctioning pre-semiconductor-chip portions30P, so that the pre-substructure wafer101is made into the substructure110.

According to the present embodiment, by stacking a plurality of subpackages1S, it is possible to easily implement a package that includes a plurality of semiconductor chips30stacked and that is capable of providing, even if it includes a defective semiconductor chip30, the same functions as those for the case where no defective semiconductor chip30is included. This advantageous effect will now be described in detail.

By way of example, a description will be given of a case where a layered chip package that includes eight conforming semiconductor chips30is required. In this case, if there is fabricated a layered chip package including only eight semiconductor chips30and if one or more of the eight semiconductor chips30are defective, simply disabling the defective semiconductor chip(s)30cannot make the layered chip package meet the above requirement. The defective semiconductor chip(s)30can be replaced with conforming semiconductor chip(s)30to remake the layered chip package, but this raises the manufacturing cost for the layered chip package.

According to the present embodiment, if, for example, a first subpackage1S includes eight semiconductor chips30and one or more of the eight semiconductor chips30are defective, a second subpackage1S having as many conforming semiconductor chip(s)30as the foregoing defective semiconductor chip(s)30can be stacked with the first subpackage1S to form a composite layered chip package1. The resulting composite layered chip package1provides the same functions as those of a layered chip package that includes eight conforming semiconductor chips30and no defective semiconductor chip30.

For example, in the composite layered chip package1shown inFIG. 1toFIG. 5, the subpackage1A includes six first-type layer portions10A and two second-type layer portions10B, while the subpackage1B includes two first-type layer portions10A. The composite layered chip package1thus includes eight first-type layer portions10A and two second-type layer portions10B. The two defective semiconductor chips30included in the two second-type layer portions10B are not electrically connected to the wiring3, and are thus disabled. The composite layered chip package1shown inFIG. 1toFIG. 5therefore provides the same functions as those of a layered chip package that includes eight conforming semiconductor chips30stacked and no defective semiconductor chip30.

As previously described, according to the present embodiment, a plurality of subpackages1S can be easily stacked and electrically connected to each other. Consequently, according to the present embodiment, a composite layered chip package1including a plurality of semiconductor chips30stacked can be easily implemented by stacking a plurality of subpackages1S, the composite layered chip package1being capable of providing, even if it includes a defective semiconductor chip30, the same functions as those for the case where no defective semiconductor chip30is included.

In the present embodiment, a composite layered chip package1including a required number of conforming semiconductor chips30can be formed by combining a plurality of subpackages1S in various configurations.FIG. 43andFIG. 44show examples where a composite layered chip package1including eight conforming semiconductor chips30is formed by combining a plurality of subpackages1S in different configurations from the configuration of the example ofFIG. 1toFIG. 5.

The composite layered chip package1shown inFIG. 43includes two subpackages1C and1D that are stacked and electrically connected to each other. The subpackage1C includes seven first-type layer portions10A and a single second-type layer portion10B. The subpackage1D includes only a single first-type layer portion10A. This composite layered chip package1thus includes eight first-type layer portions10A and a single second-type layer portions10B.

The composite layered chip package1shown inFIG. 44includes three subpackages1E,1F, and1G that are stacked and electrically connected to each other. The subpackage1E includes three first-type layer portions10A. The subpackage1F includes two first-type layer portions10A and a single second-type layer portion10B. The subpackage1G includes three first-type layer portions10A. This composite layered chip package1thus includes eight first-type layer portions10A and a single second-type layer portion10B.

Both the composite layered chip package1shown inFIG. 43and that shown inFIG. 44provide the same functions as those of a layered chip package that includes eight conforming semiconductor chips30stacked and no defective semiconductor chip30.

Although not shown in the drawings, there are many configurations that can form a composite layered chip package1having eight conforming semiconductor chips30, aside from the illustrated configurations.

Suppose, in the present embodiment, that the plurality of semiconductor chips30included in the composite layered chip package1are memory chips with a capacity of N bits each (N is a natural number). Suppose also that the number of the first-type layer portions10A included in the composite layered chip package1, i.e., the number of conforming semiconductor chips30included in the composite layered chip package1, is eight. In such a case, the composite layered chip package1can implement a memory of N bytes in capacity. Here, it is easy to recognize the capacities of the memory chips and the capacity of the memory to be implemented by the composite layered chip package1. This advantageous effect is also obtainable when the number of the first-type layer portions10A included in the composite layered chip package1is a multiple of 8.

In the present embodiment, as previously described, defective semiconductor chips30are not electrically connected to the wiring3. The defective semiconductor chips30may thus be regarded as a mere insulating layer. Consequently, according to the present embodiment, it is possible to disable the defective semiconductor chips30and to prevent the defective semiconductor chips30from causing malfunction of the layered chip package.

In the present embodiment, in a single subpackage1S, the plurality of first terminals4are formed by using the plurality of electrodes32, i.e., the plurality of first-type electrodes32A or second-type electrodes32B, of the uppermost layer portion10. In the present embodiment, the second-type layer portion10B which includes a defective semiconductor chip30has the plurality of second-type electrodes32B which are electrically connected to the wiring3and not to the semiconductor chip30. Consequently, according to the present embodiment, even if the second-type layer portion10B is the uppermost in a single subpackage1S, the plurality of second-type electrodes32B can be used to form the plurality of first terminals4. Therefore, according to the present embodiment, even if the second-type layer portion10B is the uppermost in a single subpackage1S, it is possible to stack another subpackage1S on the subpackage1S and electrically connect the two subpackages1S to each other. That is, the second-type electrodes32B do not have the function of electrically connecting the semiconductor chip30to the wiring3but have an interposer function of electrically connecting two subpackages1S to each other.

According to the present embodiment, in a layered chip package, i.e., a subpackage1S including a plurality of semiconductor chips30stacked, the stacked semiconductor chips30are electrically connected to each other by the wiring3which is disposed on at least one of the side surfaces of the main body2. Consequently, the present embodiment is free from the problems of the wire bonding method, that is, the problem that it is difficult to reduce the distance between the electrodes so as to avoid contact between the wires, and the problem that the high resistances of the wires hamper quick circuit operation.

As compared with the through electrode method, the present embodiment has the following advantages. First, the present embodiment does not require the formation of through electrodes in each chip and consequently does not require a large number of steps for forming through electrodes in each chip.

According to the present embodiment, electrical connection between the plurality of semiconductor chips30is established by the wiring3disposed on at least one of the side surfaces of the main body2. The present embodiment thus provides higher reliability of electrical connection between chips as compared with the case where through electrodes are used to establish electrical connection between the chips.

Furthermore, according to the present embodiment, it is possible to easily change the line width and thickness of the wiring3. Consequently, it is possible to easily cope with future demands for finer wiring3.

The through electrode method requires that the through electrodes of vertically adjacent chips be connected to each other by means of, for example, soldering at high temperatures. In contrast, according to the present embodiment, it is possible to form the wiring3at lower temperatures since the wiring3can be formed by plating. According to the present embodiment, it is also possible to bond the plurality of layer portions10to each other at low temperatures. Consequently, it is possible to prevent the chips30from suffering damage from heat.

The through electrode method further requires accurate alignment between vertically adjacent chips in order to connect the through electrodes of the vertically adjacent chips to each other. In contrast, according to the present embodiment, electrical connection between a plurality of semiconductor chips30is established not at an interface between two vertically adjacent layer portions10but through the use of the wiring3disposed on at least one of the side surfaces of the main body2. The alignment between a plurality of layer portions10therefore requires lower accuracy than that required for the alignment between a plurality of chips in the through electrode method.

In the present embodiment, the method of manufacturing a subpackage1S including a plurality of semiconductor chips30stacked, i.e., the method of manufacturing a layered chip package, includes the steps of fabricating a plurality of substructures110; fabricating a plurality of first layered substructures115by using the plurality of substructures110, each of the plurality of first layered substructures115including a plurality of substructures110stacked; and forming a plurality of layered chip packages from the plurality of first layered substructures115. Each of the first layered substructures115includes an array of a plurality of pre-separation main bodies2P. The plurality of pre-separation main bodies2P are to be separated from each other into individual main bodies2later.

The step of forming a plurality of layered chip packages includes the steps of fabricating a second layered substructure120by stacking the plurality of first layered substructures115and bonding every two adjacent first layered substructures115to each other; cutting the second layered substructure120into at least one block121that includes a plurality of pre-separation main bodies2P arranged both in the direction of stacking of the first layered substructures115and in a direction orthogonal thereto; forming the wiring3on the plurality of pre-separation main bodies2P included in the at least one block121simultaneously; and separating the plurality of pre-separation main bodies2P each provided with the wiring3from each other so as to form the plurality of layered chip packages.

Such a manufacturing method for the layered chip packages makes it possible to simultaneously form a plurality of sets of the terminals4and5corresponding to the plurality of layered chip packages in the step of fabricating the first layered substructures115. Moreover, according to the manufacturing method, the wiring3is formed simultaneously on the plurality of pre-separation main bodies2P included in one or more blocks121. This makes it possible to form a plurality of units of wiring3corresponding to the plurality of layered chip packages simultaneously. Here, it is unnecessary to perform alignment between the plurality of pre-separation main bodies2P included in each block121. Consequently, according to the manufacturing method, it is possible to mass-produce the layered chip packages that are capable of being electrically connected to each other easily, at low cost in a short time.

In the step of forming the wiring3in the foregoing manufacturing method, two or more blocks121may be arranged such that all the pre-separation main bodies2P included in the two or more blocks121are directed with their surfaces for the wiring3to be formed on toward the same direction. Then, the wiring3may be formed simultaneously on all the pre-separation main bodies2P included in the two or more blocks121. This makes it possible to simultaneously form the wiring3for a larger number of pre-separation main bodies2P.

The foregoing method of manufacturing the layered chip packages allows a reduction in the number of steps and consequently allows a reduction in cost for the layered chip packages, as compared with the manufacturing method for a layered chip package disclosed in U.S. Pat. No. 5,953,588.

According to the method of manufacturing the layered chip packages of the present embodiment, the first layered substructure115is fabricated by the method described with reference toFIG. 19toFIG. 22. This makes it possible to easily reduce the thickness of a plurality of substructures110that constitute the first layered substructure115while preventing damage to the substructures110. The present embodiment thus allows a high-yield manufacture of the layered chip packages that achieve a smaller size and higher integration.

In the present embodiment, the first layered substructure115can be fabricated by a method other than that described with reference toFIG. 19toFIG. 22. For example, the first layered substructure115may be fabricated by bonding two pre-polishing substructures109to each other with their respective first surfaces109aarranged to face each other, polishing the two second surfaces109bof the two pre-polishing substructures109to fabricate a stack including two substructures110, and laminating a plurality of such stacks. Alternatively, the first layered substructure115may be fabricated by bonding two substructures110to each other with their respective second surfaces110barranged to face each other to thereby fabricate a stack including the two substructures110, and laminating a plurality of such stacks.

Second Embodiment

A second embodiment of the invention will now be described.FIG. 45is an exploded perspective view of the composite layered chip package according to the present embodiment.FIG. 46is a perspective view showing the composite layered chip package ofFIG. 45as viewed from below. The composite layered chip package according to the present embodiment includes wiring3, electrodes32, and terminals4and5of different configurations from those in the first embodiment.

The wiring3of the present embodiment includes a plurality of wires3athat are disposed on at least one of the side surfaces of the main body2. In the example shown inFIG. 45andFIG. 46, a number of wires3aare disposed on each of two side surfaces2cand2dof the main body2. The electrodes32of the present embodiment each have two branched parts. The end faces of the two branched parts are exposed in the side surface2cor2d. Each of the wires3ais sandwiched between and in contact with the two branched parts of an electrode32. The first terminals4which are formed by using the electrodes32of the uppermost layer portion10have the same shape as that of the electrodes32. In the present embodiment, the second terminals5also have the same shape as that of the electrodes32.

A method of manufacturing the composite layered chip package according to the present embodiment will now be described with reference toFIG. 47toFIG. 52. In the method of manufacturing the composite layered chip package according to the embodiment, a plurality of substructures110are initially stacked to fabricate a layered substructure215. The step of fabricating the layered substructure215is the same as the step of forming the first layered substructure115of the first embodiment except that the electrodes32and the terminals4and5have different shapes. The layered substructure215of the present embodiment corresponds to the first layered substructure115of the first embodiment.FIG. 47is a plan view showing a part of the layered substructure215of the present embodiment.FIG. 48is a cross-sectional view of the part of the layered substructure215shown inFIG. 47.

As mentioned above, the electrodes32of the present embodiment each have two branched parts. In the present embodiment, each of the plurality of substructures110that constitute the layered substructure215includes two sets of electrodes32that are aligned along two mutually-opposed sides of two adjacent pre-semiconductor-chip portions30P. The two sets of electrodes32are connected to each other on a one-to-one basis. Specifically, in a pair of electrodes32, the two branched parts of one of the electrodes32are connected to those of the other by two connecting portions32C. The pair of electrodes32and the two connecting portions32C are respective different parts of a single conductor layer232. The conductor layer232has an opening232athat is surrounded by the pair of electrodes32and the two connecting portions32C.

In the layered substructure215, the plurality of second terminals5have the same configuration as the plurality of electrodes32describe above. That is, two sets of terminals5that are aligned along two mutually-opposed sides of two adjacent pre-semiconductor-chip portions30P are connected to each other on a one-to-one basis. Specifically, in a pair of terminals5, the two branched parts of one of the terminals5are connected to those of the other by two connecting portions. The pair of terminals5and the two connecting portions are respective different parts of a single conductor layer235. The conductor layer235has an opening235athat is surrounded by the pair of terminals5and the two connecting portions.

FIG. 49is a cross-sectional view showing a step that follows the step shown inFIG. 47.FIG. 50is a perspective view showing the plurality of electrodes32after the step shown inFIG. 49. In this step, a plurality of holes233for accommodating a plurality of preliminary wires to be described later are formed in the layered substructure215at the positions between two adjacent pre-separation main bodies2P. InFIG. 50, the boundary positions between the electrodes32and the connecting portions32C are shown by broken lines. The plurality of holes233are formed in the insulating layers106A or106B in a plurality of substructures110. The holes233can be formed by, for example, laser processing or reactive ion etching. If the insulating layers106A or106B are formed of resin, the holes233can be formed easily in a short time by laser processing or reactive ion etching. Each single hole133is formed to pierce through the layered substructure215, passing through the opening235aof the conductor layer235and the openings232aof a plurality of conductor layers232that are arranged in the direction in which the plurality of substructures110are stacked. The electrodes32and the terminals5are exposed in the wall faces of the hole233.

FIG. 51is a cross-sectional view showing a step that follows the step shown inFIG. 49. In this step, a seed layer241for plating is bonded to the bottom surface of the lowermost substructure110of the layered substructure215having the plurality of holes233therein. The seed layer241is formed of a metal such as copper. The seed layer241may be a metal film supported by a plate242of resin or the like. Alternatively, the seed layer241may be a metal plate. In such a case, there is no need for the plate242for supporting the seed layer241.

Next, preliminary wires243that are respectively made of plating films are formed in the plurality of holes233of the layered substructure215by electroplating. Here, the seed layer241is energized so that the plating films grow from the surface of the seed layer241to fill the holes233. Each single preliminary wire243is in contact with the plurality of electrodes32and terminals5that are arranged in the direction in which the plurality of substructures110are stacked. In this step, prior to forming the plating films in the holes233by electroplating, seed layers each made of a metal film may be formed on the wall faces of the holes233by electroless plating. Subsequently, the plating films may be formed in the holes233by electroplating. When forming the plating films, the seed layers are energized so that the plating films grow from the surfaces of the seed layers to fill the holes233. In such a modification example, the seed layers and the plating films constitute the preliminary wires243. Instead of such a modification example, the preliminary wires243may be formed by electroless plating only.

FIG. 52shows a step that follows the step shown inFIG. 51. In this step, the layered substructure215is cut so that the plurality of pre-separation main bodies2P are separated from each other and the plurality of preliminary wires243are split into two sets of a plurality of wires3aof two separate main bodies2, whereby a plurality of layered chip packages (subpackages1S) are formed. When separated from each other, the plurality of pre-separation main bodies2P become individual main bodies2. In this step, the respective plurality of electrodes32of two pre-separation main bodies2P connected to each other are separated from each other into the respective plurality of electrodes32of two separate main bodies2when the layered substructure215is cut. Similarly, the respective plurality of terminals5of two pre-separation main bodies2P connected to each other are separated from each other into the respective plurality of terminals5of two separate main bodies2when the layered substructure215is cut. The wires3aare electrically connected to the plurality of electrodes32(including the electrodes32that form the terminals4) and terminals5that are arranged in the direction of stacking of a plurality of layer portions10in each main body2.

According to the present embodiment, the preliminary wires243are formed in the plurality of holes233of the layered substructure215before the layered substructure215is cut. This allows manufacturing, through a small number of steps, a plurality of layered chip packages (subpackages1S) each having a plurality of wires3adisposed on at least one of the side surfaces of the main body2. According to the present embodiment, it is thus possible to mass-produce the layered chip packages at low cost in a short time.

If the respective plurality of electrodes32of two adjacent pre-semiconductor-chip portions30P are connected to each other in each of a plurality of substructures110that constitute the layered substructure215, the present embodiment further provides the following advantageous effect. That is, in such a case, the electrodes32and the wire3ahave large contact areas therebetween after the cutting of the layered substructure215. This can improve the reliability of the electrical connection between the electrodes32and the wire3a.

The present invention is not limited to the foregoing embodiments, and various modifications may be made thereto. For example, in the first embodiment, a plurality of blocks121are arranged to form a block assembly130, and further, a plurality of block assemblies130are arranged so that the wiring3is formed simultaneously on all of the pre-separation main bodies2P that are included in the plurality of block assemblies130. However, the wiring3may be simultaneously formed on all of the pre-separation main bodies2P that are included in a single block assembly130, or all of the pre-separation main bodies2P that are included in a single block121. After the plurality of pre-separation main bodies2P each provided with the wiring3are separated from each other into a plurality of main bodies2, additional wiring may be formed on the main bodies2.

In the second embodiment, the respective plurality of electrodes32of two adjacent pre-semiconductor-chip portions30P need not necessarily be connected to each other in each of the plurality of substructures110constituting the layered substructure215.

In the second embodiment, the method of forming the preliminary wires243is not limited to plating, and may use other techniques. For example, the preliminary wires243may be formed by initially filling the holes233with a conductive paste that contains silver, copper or other metal powder and a binder, and then heating the conductive paste to decompose the binder and sinter the metal. Alternatively, the preliminary wires243may be formed by pressing silver, copper or other metal powder into the holes233and then heating the metal powder to sinter the metal.

It is apparent that the present invention can be carried out in various forms and modifications in the light of the foregoing descriptions. Accordingly, within the scope of the following claims and equivalents thereof, the present invention can be carried out in forms other than the foregoing most preferred embodiments.