MEMORY DEVICE INCLUDING SWITCHING PATTERN

A memory device includes a first conductive line, a second conductive line, and a memory cell disposed between the first and second conductive lines. The memory cell includes a lower electrode layer, a switching pattern, and an upper electrode layer. The switching pattern includes a main region including a pair of first side walls and a pair of second walls, and a corner region at four corners of the main region. The switching pattern includes a chalcogenide layer including a Group VI chalcogen element, an element of Group IV and an element of Group V, and the concentration of the Group IV element in the corner region is greater than that of the Group IV element in the main region, or the concentration of the Group V element in the corner region is greater than that of the Group V element in the main region.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0104353, filed on Aug. 9, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

The inventive concept relates to a memory device, and more particularly, to a memory device having a switching pattern.

DISCUSSION OF THE RELATED ART

As electronic products become lighter, thinner, and smaller, the demand for high integration of memory devices is increasing. A memory device with a three-dimensional cross point structure, in which memory cells are placed at the intersection between two electrodes that intersect each other, has been proposed. A memory device with a cross point array structure may provide for high-speed operation and high operation reliability.

SUMMARY

A memory device includes a first conductive line extending in a first horizontal direction, a second conductive line extending in a second horizontal direction, and a memory cell disposed between the first conductive line and the second conductive line and extending in a vertical direction. The memory cell includes a lower electrode layer, a switching pattern, and an upper electrode layer sequentially stacked on the first conductive line. The switching pattern includes a main region extending in the vertical direction on the lower electrode layer. The main region includes a pair of first side walls spaced apart from one another in the first horizontal direction and a pair of second walls spaced apart from one another in the second horizontal direction, and a corner region at four corners of the main region and extending in the vertical direction. The switching pattern includes a chalcogenide layer including a Group VI chalcogen element of a periodic table, and an element of Group IV and an element of Group V of the periodic table, which are chemically bonded to the Group VI chalcogen element. The concentration of the Group IV element, by atomic percent, in the corner region is greater than the concentration of the Group IV element, by atomic percent, in the main region, or the concentration of the Group V element, by atomic percent, in the corner region is greater than the concentration of the Group V element, by atomic percent, in the main region.

A memory device includes a first conductive line extending in a first horizontal direction, a second conductive line extending in a second horizontal direction, and a memory cell disposed between the first conductive line and the second conductive line and extending in a vertical direction. The memory cell includes a lower electrode layer, a switching pattern, and an upper electrode layer sequentially stacked on the first conductive line. The switching pattern includes a main region disposed on the lower electrode layer and extending in the vertical direction. The main region includes a pair of first side walls spaced apart from one another in the first horizontal direction and a pair of second walls spaced apart from one another in the second horizontal direction. A pair of first shell regions is disposed on the pair of first side walls of the main region, a pair of second shell regions is disposed on the pair of second side walls of the main region, and a corner region extends in the vertical direction at four corners of the main region. The switching pattern includes a chalcogenide layer including a Group VI chalcogen element of the periodic table and an element of Group IV and an element of Group V of the periodic table, which are chemically bonded to the Group VI chalcogen element. The concentration of the Group IV element, by atomic percent, in the corner region is greater than the concentration of the Group IV element, by atomic percent, in the main region, or the concentration of the Group V element, by atomic percent, in the corner region is greater than the concentration of the Group V element, by atomic percent, in the main region.

A memory device includes a first conductive line extending in a first horizontal direction, a second conductive line extending in a second horizontal direction, a memory cell extending in a vertical direction and disposed between the first conductive line and the second conductive line. The memory cell includes a lower electrode layer, a switching pattern, and an upper electrode layer sequentially stacked on the first conductive line. A first spacer is disposed on the pair of first side walls of the memory cell. A first encapsulation layer is disposed on the first spacer. A second spacer is disposed on the pair of second side walls of the memory cell. A second encapsulation layer is disposed on the second spacer. The switching pattern includes a main region extending in the vertical direction and disposed on the lower electrode layer. The main region includes a pair of first side walls spaced apart from one another in the first horizontal direction and a pair of second walls spaced apart from one another in the second horizontal direction. A pair of first shell regions is disposed on the pair of first side walls of the main region. A pair of second shell regions is disposed on the pair of second side walls of the main region. A corner region extends in the vertical direction at four corners of the main region. The switching pattern includes a chalcogenide layer including a Group VI chalcogen element of the periodic table, and an element of Group IV and an element of Group V of the periodic table, which are chemically bonded to the Group VI chalcogen element. The concentration of the Group IV element, by atomic percent, in the corner region is greater than the concentration of the Group IV element, by atomic percent, in the main region, or the concentration of the Group V element, by atomic percent, in the corner region is greater than the concentration of the Group V element, by atomic percent, in the main region.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Hereinafter, with reference to the accompanying drawings, embodiments of the inventive concept will be described in detail.

FIG.1is a schematic perspective of a memory device100according to some embodiments of the present disclosure.FIG.2is a cross-sectional view of the memory device taken along line A1-A1′ inFIG.1, andFIG.3is a cross-sectional view of the memory device taken along line A2-A2′ inFIG.1.FIG.4is a plan view of the memory device at a first vertical level LV1inFIGS.2and3.

Referring toFIGS.1to4, the memory device100may include plurality of first conductive lines130, a plurality of second conductive lines160disposed at a vertical level that is higher than the plurality of first conductive lines130, and a plurality of memory cells MCs located at the points where the plurality of first conductive lines130intersect the plurality of second conductive lines160. The plurality of memory cells MCs may be an array structure spaced apart from each other in a first horizontal direction X and a second horizontal direction Y. The memory device100may include a memory cell MC located at an upper portion of a substrate110as shown inFIG.2.

The substrate110may include semiconductor materials such as Group IV semiconductor materials, Group III-V semiconductor materials, or Group II-VI semiconductor materials. The Group IV semiconductor material may include, for example, silicon (Si), germanium (Ge), or silicon-germanium (Si—Ge). The Group III-V semiconductor material may include, for example, GaAs, InP, GaP, InAs, InSb, or InGaAs. The Group II-VI semiconductor material may include, for example, ZnTe or CdS.

A lower structure120may be disposed between the substrate110and the plurality of first conductive lines130. The lower structure120may include an insulation material that electrically insulates the plurality of first conductive lines130from the substrate110. In some embodiments of the present disclosure, the lower structure120may include a peripheral circuit PTR (seeFIG.6) for driving the plurality of memory cells MCs, and for example, may further include a wiring structure for electrically connect the peripheral circuit PTR placed on the substrate110to the plurality of first conductive lines130and the plurality of second conductive lines160.

The plurality of first conductive lines130may extend parallel to each other in the first horizontal direction X, and the plurality of second conductive lines160may extend parallel to each other in the second horizontal direction Y that intersects the first horizontal direction X at a vertical level that is higher than the plurality of first conductive lines130. Here, the vertical level may be defined based on a top surface of the substrate110. For example, the expression that the plurality of second conductive lines160are disposed at the vertical level that is higher than the plurality of first conductive lines130means that the distance from the plurality of second conductive lines160to the top surface of the substrate110is greater than the distance from the plurality of first conductive lines130to the top surface of the substrate110.

In some embodiments of the present disclosure, the plurality of first conductive lines130may be referred to as word lines, and the plurality of second conductive lines160may be referred to as bit lines.

In some embodiments of the present disclosure, the plurality of first conductive lines130and the plurality of second conductive lines160may each include a metal, conductive metal nitrides, conductive metal oxides, or combinations thereof. In some examples, the plurality of first conductive lines130and the plurality of second conductive lines160may each include W, WN, Au, Ag, Cu, A1, TiAlN, Ir, Pt, Pd, Ru, Zr, Rh, Ni, Co, Cr, Sn, Zn, ITO, alloys thereof, or combinations thereof. In some examples, the plurality of first conductive lines130and the plurality of second conductive lines160may each include a metal film and a conductive barrier layer that covers at least a part of the metal film. The conductive barrier layer may include, for example, Ti, TiN, Ta, TaN, WSiN, WN, or combinations thereof.

The plurality of memory cells MC1may be disposed between the plurality of first conductive lines130and the plurality of second conductive lines160, and may extend to a predetermined height in a vertical direction Z that is perpendicular to the top surface of the substrate110. For example, the plurality of first conductive lines130may extend in the first direction X at the first vertical level, and the plurality of second conductive lines160may extend in the second direction Y at the second vertical level that is different from the first vertical level. The plurality of memory cells MC1may be disposed at cross points or overlap positions of the plurality of first conductive lines130and the plurality of second conductive lines160in the plan view. The plurality of memory cells MC1may be disposed on the plurality of first conductive lines130and below the plurality of second conductive lines160, and may be spaced apart from one another in the first direction X and the second direction Y. This arrangement of the plurality of memory cells MC1may be referred to as a cross point type configuration. For example, the memory device100disclosed inFIGS.1to4may have the cross point type configuration of one layer stack in which the plurality of memory cells MC1are disposed at the same vertical level.

The plurality of memory cells MC1may include a lower electrode layer142, a switching pattern144, and an upper electrode layer146sequentially disposed in the vertical direction Z on the plurality of first conductive lines130.

The lower electrode layer142may include a metal, conductive metal nitrides, conductive metal oxides, or carbon-based materials. For example, the lower electrode layer142may include a carbon electrode or a carbon nitride electrode.

The switching pattern144may include a material layer of which electrical resistance may vary depending on the magnitude of the voltage applied on both ends of the switching pattern144. The switching pattern144may include a material having ovonic threshold switching (OTS) characteristics. In some embodiments of the present disclosure, when a voltage that is less than the threshold voltage is applied to the switching pattern144, the switching pattern144may be in a high resistance state in which little or no current flows. When the voltage that is greater than the threshold voltage is applied to the switching pattern144, the switching pattern144may be in a low resistance state in which the current may flow.

The switching pattern144may be a selector only memory element, where the selector only memory element may indicate a device component that performs a switching function component and a memory storage component at the same time. For example, the switching pattern144may include a chalcogenide material capable of a bidirectional write operation, and the chalcogenide material may include a material whose threshold voltage changes in the bidirectional write operation.

The switching pattern144may be composed of a single film. In some embodiments of the present disclosure, the switching pattern144may include a chalcogenide layer including a Group VI chalcogen element of the periodic table, and an element of Group IV and an element of Group V of the periodic table that are chemically bonded to the Group VI chalcogen element. The Group VI chalcogen element may include Te, Se, and/or S. The Group V element may include As, Sb, and/or P. The Group IV element may include Si and/or Ge.

In some embodiments of the present disclosure, the switching pattern144may further include a doped element of Group III of the periodic table that is doped into the switching pattern144in addition to the previous elements. The doped element of Group III may include In, Ga, and/or Al.

In some embodiments of the present disclosure, the switching pattern144may include a main region144M, a shell region144S, and a corner region144C.

The main region144M may extend in the vertical direction Z on the lower electrode layer142and may have a square or a rectangular cross-sectional shapes in the plan view. The main region144M may have a pair of first side walls S11spaced apart from one another in the first horizontal direction X and a pair of second side walls S12spaced apart from one another in the second horizontal direction Y. The pair of first side walls S11may be spaced apart from each other in the first horizontal direction X and extend in the second horizontal direction Y, and the pair of second side walls S12may be spaced apart from each other in the second horizontal direction Y and extend in the first horizontal direction X.

The shell region144S may be disposed on the pair of first side walls S11and the pair of second side walls S12of the main region144M. The shell region144S may be extended in the vertical direction Z, while covering substantially the entire surface of the pair of first side walls S11and the pair of second side walls S12. For example, as shown inFIG.4, a pair of first shell regions144S1may be disposed on the pair of first side walls S11of the main region144M and a pair of second shell regions144S2may be disposed on the pair of second side walls S12of the main region144M.

The corner region144C may be disposed at four corners of the main region144M having a square or rectangular plane cross-sectional shape and may extend in the vertical direction Z. For example, four corner regions144C may be spaced apart from each other at four corners of one main region144M, and any one corner region144C may be located at a point where one of the pair of first side walls S11and one of the pair of second side walls S12of the main region144M meet. For example, two of the four corner regions144C may be spaced apart from one another in a first diagonal direction with one main region144M therebetween, and the other two of the four corner regions144C may be spaced apart from one another in a second diagonal direction that intersects the first diagonal direction with one main region144M therebetween.

As shown inFIG.4, one corner region144C may be disposed between one first shell region144S1of the pair of first shell regions144S1and one second shell region144S2of the pair of second shell regions144S2, and may contact the one first shell region144S1of the pair of first shell regions144S1and the one second shell region144S2of the pair of second shell regions144S2.

The main region144M, the shell regions144S, and the corner regions144C may extend in the vertical direction Z across the entire height of the switching pattern144. For example,FIG.4is shown as a planar shape of the switching pattern144observed at the first vertical level LV1, and the planar shape taken at any vertical level over the entire height of the switching pattern144may also be substantially the same or similar to that shown inFIG.4.

In some embodiments of the present disclosure, the concentration of Group IV elements or Group V elements, by atomic percent, contained in the corner region144C may be different from the concentration of Group IV elements or Group V elements, by atomic percent, contained in the main region144M. For example, as shown inFIG.4, when comparing the composition of the chalcogenide layer at a part of the corner region144C with the composition of the chalcogenide layer at a part of the main region144M disposed at the same vertical level, the concentration of Group IV elements, by atomic percent, in the corner region144C may be greater than the concentration of Group IV elements, by atomic percent, in the main region144M, and/or the concentration of Group V elements, by atomic percent, in the corner region144C may be greater than the concentration of Group V elements, by atomic percent, in the main region144M.

In some embodiments of the present disclosure, the concentration of Group IV elements or Group V elements, by atomic percent, contained in the shell region144S may be different from the concentration of Group IV elements or Group V elements, by atomic percent, contained in the main region144M. For example, as shown inFIG.4, when comparing the composition of the chalcogenide layer at a part of the shell region144S with the composition of the chalcogenide layer at a part of the main region144M disposed at the same vertical level, the concentration of Group IV elements, by atomic percent, in the shell region144S may be greater than the concentration of Group IV elements, by atomic percent, in the main region144M, and/or the concentration of Group V elements, by atomic percent, in the shell region144S may be greater than the concentration of Group V elements, by atomic percent, in the main region144M.

In some embodiments of the present disclosure, the concentration of Group IV elements or Group V elements, by atomic percent, contained in the shell region144S may be different from the concentration of Group IV elements or Group V elements, by atomic percent, contained in the corner region144C. For example, as shown inFIG.4, when comparing the composition of the chalcogenide layer at a part of the shell region144S with the composition of the chalcogenide layer at a part of the corner region144C disposed at the same vertical level, the concentration of Group IV elements, by atomic percent, in the shell region144S may be less than the concentration of Group IV elements, by atomic percent, in the corner region144C, and/or the concentration of Group V elements, by atomic percent, in the shell region144S may be less than the concentration of Group V elements, by atomic percent, in the corner region144C.

In some embodiments of the present disclosure, the main region144M included in the switching pattern144may include Group IV elements of 15 to 25 atomic % (at %), Group V elements of 20 to 30 at %, and Group VI elements of 45 to 65 at %. The corner region144C included in the switching pattern144may include Group IV elements of 10 to 20 at %, Group V elements of 25 to 40 at %, and Group VI elements of 40 to 65 at %.

In some embodiments of the present disclosure, the ratio of the concentration of Group VI elements, by atomic percent, to the concentration of the Group IV elements, by atomic percent, in the corner region144C included in the switching pattern144may be greater than 0.5 and less than 1. In some embodiments of the present disclosure, the ratio of the concentration of Group VI elements, by atomic percent, to the concentration of the Group V elements, by atomic percent, in the corner region144C included in the switching pattern144may be greater than 0.6 and less than 1.4.

The upper electrode layer146may include a metal, conductive metal nitrides, conductive metal oxides, or carbon-based materials. For example, the upper electrode layer146may include a carbon electrode or a carbon nitride electrode.

A first insulating layer132that fills a space between the plurality of first conductive lines130may be disposed on the lower structure120. In addition, a second insulating layer162that fills a space between the plurality of second conductive lines160may be disposed. The first insulating layer132and the second insulating layer134may include silicon oxide.

A first spacer152A may be disposed on side walls of the pair of first shell regions144S1of the switching pattern144. The first spacer152A may extend from the side walls of the first shell regions144S1to side walls of the upper electrode layer146, and bottom surfaces of the first spacer152A may be placed on a top surface of the lower electrode layer142. For example, one side wall of the first spacer152A may contact the side wall of the first shell region144S1and the side wall of the upper electrode layer146.

A first encapsulation layer154A may be disposed on the other side wall of the first spacer152A. The first encapsulation layer154A may extend in the vertical direction Z over the entire height of the upper electrode layer146, the switching pattern144, and the lower electrode layer142, and portions of the first encapsulation layer154A may be disposed on the upper surface of the first conductive line130and the first insulating layer132. A first buried insulating layer156A may be disposed on the side wall of the first encapsulation layer154A.

A second spacer152B may be disposed on side walls of the pair of second shell regions144S2of the switching pattern144. The second spacer152B may extend from the side walls of the second shell regions144S2onto side walls of the upper electrode layer146, and bottom surfaces of the second spacer152B may be placed on the top surface of the lower electrode layer142. For example, one side wall of the second spacer152B may contact the side wall of the second shell region144S2and the side wall of the upper electrode layer146.

A second encapsulation layer154B may be disposed on the other side wall of the second spacer152B. The second encapsulation layer154B may extend in the vertical direction Z over the entire height of the upper electrode layer146, the switching pattern144, and the lower electrode layer142, and portions of the second encapsulation layer154B may be disposed on the upper surface of the first conductive line130and the first insulating layer132. A second buried insulating layer156B may be disposed on the side wall of the second encapsulation layer154B.

In embodiments of the present disclosure, the first spacer152A, the first encapsulation layer154A, the first buried insulating layer156A, the second spacer152B, the second encapsulation layer154B, and the second buried insulating layer156B may each include silicon nitride, silicon oxide, silicon oxynitride, and/or a low-k dielectric material. As used herein, the term “low-k” may be understood to mean a material having a dielectric constant that is less than or equal to that of silicon oxide. In some embodiments of the present disclosure, the first spacer152A and the second spacer152B may include silicon nitride, and the first encapsulation layer154A and the second encapsulation layer154B may include silicon nitride, and the first buried insulating layer156A and the second buried insulating layer156B may include silicon oxide. In some other embodiments of the present disclosure, the first spacer152A and the second spacer152B may include silicon nitride, and the first encapsulation layer154A and the second encapsulation layer154B may include silicon nitride, and the first buried insulating layer156A and the second buried insulating layer156B may include low-k dielectric material. In some other embodiments of the present disclosure, the first buried insulating layer156A and the second buried insulating layer156B may include an air gap or a void therein.

FIG.5is a schematic diagram and graph showing voltage-current characteristics of the memory device100according to some embodiments of the present disclosure.

Referring toFIG.5, the memory cell MC1described with reference toFIGS.1to4may show a bidirectional threshold voltage characteristic as shown inFIG.5. For example, when the positive voltage is applied to the memory cell MC1, switching characteristics may appear in the positive threshold voltage +Vth. In addition, when the negative voltage is applied to the memory cell MC1, switching characteristics may appear in the negative threshold voltage −Vth.

For example, in the memory device100described with respect toFIGS.1to4, the switching pattern144(e.g., the main region144M included in the switching pattern144) between the lower electrode layer142and the upper electrode layer146may have the concentration gradient of Group IV elements, the concentration gradient of Group V elements, and/or the concentration gradient of Group VI elements of a chalcogenide material in the vertical direction, and accordingly, the switching pattern144may have a structure in which an n-type semiconductor, a p-type semiconductor, and an n-type semiconductor are arranged in series in the vertical direction, so the switching pattern144may exhibit switching characteristics capable of bidirectional rectification.

FIG.6is a schematic diagram for illustrating positive writing characteristics of a memory cell according to some embodiments of the present disclosure.

Referring toFIG.6, a positive write voltage +Vwr may be applied to the upper electrode layer146to perform a set operation. When the positive write voltage +Vwr is applied to the upper electrode layer146, the concentration gradient of Group IV elements, the concentration gradient of Group V elements, and/or Group VI group elements in the main region144M of the switching pattern144may remain the same without changing. In addition, when the positive write voltage +Vwr is applied to the upper electrode layer146, there is no change in the microstructure of the main region144M of the switching pattern144and an amorphous structure may be maintained.

On the other hand, when the positive write voltage +Vwr is applied to the upper electrode layer146, the same type of elements may be locally aligned in the corner region144C. For example, Group IV elements such as germanium or Group V elements such as arsenic may be aligned in the corner region144C, and therefore, a localized electrical path TRP by trap sites may be generated within the corner region144C.

FIGS.7and8are schematic diagrams and graphs for illustrating read characteristics of a memory cell according to some embodiments of the present disclosure.

Referring toFIG.7, the positive read voltage +Vread may be applied to the upper electrode layer146of the memory cell MC1on which the set operation has been performed by applying the positive write voltage +Vwr (seeFIG.6). In this case, the forward bias may be applied to the switching pattern144and the built-in potential of the switching pattern144may decrease, so the memory cell MC1may exhibit switching characteristics at low positive threshold voltage Low +Vth. Herein, the low positive threshold voltage Low +Vth means that the threshold voltage has the positive value and the magnitude or absolute value of the threshold voltage is relatively small.

Referring toFIG.8, the negative read voltage −Vread may be applied to the upper electrode layer146of the memory cell MC1on which the set operation has been performed by applying the positive write voltage +Vwr (seeFIG.6). In this case, the reverse bias may be applied to the switching pattern144and the built-in potential of the switching pattern144may increase, so the memory cell MC1may exhibit switching characteristics at high negative threshold voltage High −Vth. Herein, the high negative threshold voltage High −Vth means that the threshold voltage has the negative value and the magnitude or absolute value of the threshold voltage is relatively large.

FIG.9is a schematic diagram for illustrating negative write characteristics of a memory cell according to some embodiments of the present disclosure.

Referring toFIG.9, the negative write voltage −Vwr may be applied to the upper electrode layer146to perform a reset operation. When the negative write voltage −Vwr is applied to the upper electrode layer146, the concentration gradient of Group IV elements, the concentration gradient of Group V elements, and/or Group VI group elements in the main region144M of the switching pattern144may remain the same without changing. In addition, when the negative write voltage −Vwr is applied to the upper electrode layer146, there is no change in the microstructure of the main region144M of the switching pattern144and the amorphous structure may be maintained.

On the other hand, when the negative write voltage −Vwr is applied to the upper electrode layer146, the same type of elements may be locally relocated or dispersed in the corner region144C. For example, Group IV elements such as germanium or Group V elements such as arsenic may be relocated or dispersed in the corner region144C, and therefore, a localized switching path by trap sites may be removed or lost within the corner region144C.

FIGS.10and11are schematic diagrams and graphs for illustrating read characteristics of a memory cell according to some embodiments of the present disclosure.

Referring toFIG.10, the positive read voltage +Vread may be applied to the upper electrode layer146of the memory cell MC1on which the reset operation has been performed by applying the negative write voltage −Vwr. In this case, the reverse bias may be applied to the switching pattern144and the built-in potential of the switching pattern144may increase, so the memory cell MC1may exhibit switching characteristics at high positive threshold voltage High +Vth. Herein, the high positive threshold voltage High +Vth means that the threshold voltage has the positive value and the magnitude or absolute value of the threshold voltage is relatively large.

Referring toFIG.11, the negative read voltage −Vread may be applied to the upper electrode layer146of the memory cell MC1on which the reset operation has been performed by applying the negative write voltage −Vwr. In this case, the forward bias may be applied to the switching pattern144and the built-in potential of the switching pattern144may decrease, so the memory cell MC1may exhibit switching characteristics at low negative threshold voltage Low-Vth. Herein, the low negative threshold voltage Low-Vth means that the threshold voltage has the negative value and the magnitude or absolute value of the threshold voltage is relatively small.

As described with reference toFIGS.5to11, the switching pattern144may function as a selector-only memory element having bidirectional rectification characteristics, and the same type of elements may be locally aligned through the corner region144C of the switching pattern144and the trap sites may be connected to each other, so the threshold voltage distribution of the memory cell MC1may be reduced or the window of the threshold voltage may be narrowed.

FIG.12is a graph showing the composition ratio of Group IV elements to Group VI elements in a memory cell according to some embodiments of the present disclosure.

Referring toFIG.12, the composition ratios of Group IV elements to Group VI elements scanned along lines A3-A3′ in the diagonal direction of the switching pattern144in the memory cell MC1, according to some embodiments of the present disclosure, and a memory cell MC2according to the comparative example, respectively, is shown.

According to the memory cell MC1according to some embodiments of the present disclosure, the composition ratio of Group IV elements to Group VI elements, by atomic percent, in the corner region144C may be relatively large, for example, with a value of 0.5 or more and 1 or less, and the composition ratio of Group IV elements to Group VI elements in the main region144M may be relatively small.

On the other hand, the memory cell MC2, according to the comparative example, has a structure in which a corner region is not formed and a shell region144SC surrounds the entire side wall of a main region144MC. According to the memory cell MC2, according to the comparative example, the composition ratio of the composition ratio of Group IV elements to Group VI elements in the shell region144SC may be greater than the composition ratio of Group IV elements to Group VI elements in the main region144MC. However, the composition ratio of Group IV elements to Group VI elements in the shell region140SC of the memory cell MC2of the comparative example may be less than the composition ratio of Group IV elements to Group VI elements in the corner region144C of the memory cell MC1of the embodiments of the present disclosure.

FIG.13is a graph showing the composition ratio of Group V elements to Group VI elements in a memory cell according to some embodiments of the present disclosure.

Referring toFIG.13, the composition ratios of Group V elements to Group VI elements scanned along lines A3-A3′ in the diagonal direction of the switching pattern144in the memory cell MC1, according to some embodiments of the present disclosure, and the memory cell MC2, according to the comparative example, respectively, is shown.

According to the memory cell MC1, according to some embodiments of the present disclosure, the composition ratio of Group V elements to Group VI elements, by atomic percent, in the corner region144C may be relatively large, for example, with a value of 0.6 or more and 1.4 or less, and the composition ratio of Group V elements to Group VI elements in the main region144M may be relatively small.

On the other hand, the memory cell MC2, according to the comparative example, has a structure in which a corner region is not formed and a shell region144SC surrounds the entire side wall of a main region144MC. According to the memory cell MC2, according to the comparative example, the composition ratio of the composition ratio of Group V elements to Group VI elements in the shell region144SC may be less than the composition ratio of Group V elements to Group VI elements in the main region144MC. In addition, the composition ratio of Group V elements to Group VI elements in the shell region140SC of the memory cell MC2of the comparative example may be less than the composition ratio of Group V elements to Group VI elements in the corner region144C of the memory cell MC1of the embodiments of the present disclosure.

FIG.14is a graph showing the threshold voltage distribution of a memory cell according to some embodiments of the present disclosure.

Referring toFIG.14, the threshold voltage distributions of the memory cell MC1, according to some embodiments of the present disclosure, and the memory cell MC2, according to the comparative example, are shown, respectively. As shown inFIGS.12and13, the memory cell MC2, according to the comparative example, has a structure in which the corner region is not formed and the shell region144SC surrounds the entire side wall of the main region144MC.

As shown inFIG.14, it may be confirmed that the threshold voltage distribution of the memory cell MC1, according to some embodiments of the present disclosure, is less (narrower threshold voltage window) than that of the memory cell MC2, according to the comparative example.

FIG.15is a plan view showing a switching pattern144of a memory cell MC1according to some embodiments of the present disclosure.

Referring toFIG.15, the switching pattern140may have curved side walls that are recessed inward. For example, both a pair of first side walls S11and a pair of second side walls S12of the main region144M may have curved shapes that are recessed inward, for example, in a direction toward the main region144M. In addition, the shell region144S disposed on the pair of first side walls S11and the pair of second side walls S12of the main region144M may also have outer walls of curved shape that conform to the curved shapes of the pairs of first and second side walls S11and S12.

In embodiments of the present disclosure, in a patterning process of forming the switching pattern140, central parts of the side walls of the switching pattern140may be more exposed to the etching atmosphere than edges of the side walls of the switching pattern140, so the central parts of the side walls of the switching pattern140may be recessed inward. In this case, as shown inFIG.15, the switching pattern140may have the curved side walls that is recessed inward.

FIGS.16,17,18A,18B,19to21,22A,22B,23,24,25A, and25Bare schematic diagrams showing a method of manufacturing the memory device100, according to some embodiments of the present disclosure.FIGS.16,17,18A,19to21,22A,23,24, and25Aare cross-sectional views of the memory device100taken along lines A1-A1′ and A2-A2′ inFIG.1, andFIGS.18B,22B, and25B are plan views of the memory device100at a first vertical level LV1inFIGS.18A,22A, and25A, respectively.

Referring toFIG.16, a lower structure120may be formed on a substrate110. A first conductive layer may be formed on the lower structure120and the first conductive layer may be patterning to form a plurality of first conductive lines130. Thereafter, an insulating layer may be formed on the plurality of first conductive lines130and the lower structure120, and a top surface of the insulating layer may be planarized until a top surface of the plurality of first conductive lines130is exposed, thereby forming a first insulating layer132.

Referring toFIG.17, a memory cell stack MCS may be formed on the plurality of first conductive lines130and the first insulating layer132, in which the memory cell stack MCS may sequentially include a lower electrode material layer142L, a switching material layer144L, and an upper electrode material layer146L.

In embodiments of the present disclosure, a process of forming the switching material layer142L may include a physical vapor deposition (PVD) process and/or a chemical vapor deposition (CVD) process.

Referring toFIGS.18A and18B, a first mask pattern M1may be formed on the memory cell stack MCS, and then the first mask pattern M1may be used as an etch mask to pattern a portion of the memory cell stack MCS. At this time, the switching material layer144L and the upper electrode material layer146L may be patterned to form a switching material line144L1and an upper electrode line146L1.

In embodiments of the present disclosure, the first mask pattern M1may be a pattern of line shape that may extend in the first horizontal direction X and may be spaced apart from one another in the second horizontal direction Y.

In embodiments of the present disclosure, an etching process using a reactive gas containing hydrogen may be used in the process that patterns the portion of the memory cell stack MCS. For example, the etching process may be a reactive ion etching process. In some embodiments of the present disclosure, the reactive gas containing hydrogen may include CH4, H2, etc. In some embodiments of the present disclosure, the reactive gas containing hydrogen may have an etching selectivity (having relatively high etching rate) for Group VI elements contained in the chalcogenide material layer.

As the switching material line144L1is formed, a shell region144S may be formed at the side wall of the switching material line144L1with a predetermined depth. For example, as the switching material line144L1extends in the first horizontal direction X, a pair of second shell regions144S2may be formed on both side walls of the switching material line144L1.

The shell region144S may be a region where some of Group VI elements, such as selenium (Sc), has been removed from the side wall of the switching material line144L1by the reactive ion etching process having a relatively high etching rate for Group VI elements. The shell region144S may indicate the region where the composition of Group VI elements changed in comparison with an internal region (bulk region) of the switching material line144L1.

Referring toFIG.19, a second spacer152B may be formed on the side walls of the switching material line144L1and the upper electrode line146L1. The second spacer152B may be conformally formed with a relatively thin thickness, on the side walls of the switching material line144L1, the upper electrode line146L1, and the first mask pattern M1.

Referring toFIG.20, lower electrode lines142L1may be formed by patterning the lower electrode material layer142L using the first mask pattern M1and the second spacer152B as an etch mask.

In embodiments of the present disclosure, etching gases containing oxygen may be used in the process of forming the lower electrode lines142L1. In the etching atmosphere for forming the lower electrode lines142L1, the side wall of the switching material line144L1may be covered by the second spacer152B and thus might not be exposed to the etching atmosphere.

Herein, the lower electrode line142L1, the switching material line144L1, and the upper electrode line146L1may be referred to as a memory cell line MCL. The memory cell lines MCL may extend in the first horizontal direction X and may be spaced apart from each other in the second horizontal direction Y.

Referring toFIG.21, second encapsulation layers154B may be formed on the side walls of the lower electrode lines142L1, the switching material lines144L1, and the upper electrode lines146L1(i.e., on the side walls of the memory cell lines MCL). Thereafter, second buried insulating layers156B may be formed on the second encapsulation layers154B to fill spaces between adjacent memory cell lines MCL. The first mask pattern M1may also be removed in a process of planarizing upper portions of the second buried insulating layers156B.

Referring toFIGS.22A and22B, a second mask pattern M2may be formed on the memory cell line MCL, and then the second mask pattern M2may be used as an etch mask to pattern a portion of the memory cell line MCL. At this time, the switching material line144L1and the upper electrode material line146L1may be patterned to form a switching pattern144and an upper electrode layer146.

In embodiments of the present disclosure, the second mask pattern M2may be a pattern of line shape that may extend in the second horizontal direction Y and may be spaced apart from one another in the first horizontal direction X.

In embodiments of the present disclosure, an etching process using a reactive gas containing hydrogen may be used in the process that patterns a portion of the memory cell line MCL. For example, the etching process may be the reactive ion etching process. In some embodiments of the present disclosure, the reactive gas containing hydrogen may include CH4, H2, etc. In embodiments of the present disclosure, the reactive gas containing hydrogen may have an etching selectivity (having relatively high etching rate) for Group VI elements contained in the chalcogenide material layer.

As the switching pattern144is formed, a shell region144S may be formed at the side walls of the switching pattern144with a predetermined depth. The shell region144S may be a region where some of Group VI elements, such as selenium (Se), has been removed from the side wall of the switching pattern144by the reactive ion etching process having a relatively high etching rate for Group VI elements. The shell region144S may indicate the region where the composition of Group VI elements changed in comparison with an internal region (bulk region) of the switching pattern144.

For example, as the second mask pattern M2has a shape extending in the second horizontal direction Y, a pair of first shell regions144S1may be formed on both side walls (i.e., on both side walls newly exposed in the patterning process) that are spaced apart from each other in the second horizontal direction Y of the switching pattern144. On the other hand, a corner region144C may be formed at the four corners of the switching pattern144. The corner region144C may be a region that is formed after a portion of the pair of second shell regions144S2is exposed again in the patterning process using the second mask pattern M2as an etch mask. For example, the corner region144C may be a region in which some of Group VI elements, such as selenium (Se), has been removed from the side walls of the switching pattern144in the reactive ion etching process having a relatively high etching rate for Group VI elements.

The corner region144C was exposed to patterning processes twice, and therefore, the corner region144C may have the composition ratio of Group VI elements that is less than that of the pair of first shell regions144S1, less than that of the pair of second shell regions144S2, and less than that of the internal region (i.e., a bulk region) of the switching pattern144.

After the corner region144C and the pair of first shell regions144S1are formed, the internal region of the switching pattern144may be referred to as the main region144M.

Referring toFIG.23, a first spacer152A may be formed on the side walls of the switching pattern144and the upper electrode layer146. The first spacer152A may be conformally formed with a relatively thin thickness, on the side walls of the switching pattern144, the upper electrode146, and the second mask pattern M2.

Referring toFIG.24, a lower electrode layer142may be formed by patterning the lower electrode line142L1using the second mask pattern M2and the first spacer152A as an etch mask.

In embodiments of the present disclosure, etching gases containing oxygen may be used in the process of forming the lower electrode layer142. In the etching atmosphere for forming the lower electrode layer142, the side wall of the switching pattern144may be covered by the first spacer152A and thus might not be exposed to the etching atmosphere.

Herein, a plurality of memory cells MC1that each includes the lower electrode layer142, the switching pattern144, and the upper electrode layer146, may be formed. The plurality of memory cells MC1may be spaced apart from each other in the first horizontal direction X and in the second horizontal direction Y.

Referring toFIGS.25A and25B, a first encapsulation layer154A may be formed on the side walls of the plurality of memory cells MC1. Thereafter, first buried insulating layers156A may be formed on the first encapsulation layers154B to fill spaces between adjacent memory cell MC1. The second mask pattern M2may also be removed in the process of planarizing upper portions of the first buried layers156A.

Referring toFIGS.2and3, second conductive lines160may be formed on the plurality of memory cells MC1and a second insulating layer162may be formed to fill spaces between the second conductive lines160.

The memory device100may be manufactured by the above processes.

In the manufacturing process of the memory device100, the shell region144S and the corner region144C may be formed on the side wall of the switching pattern144, and the shell region144S and the corner region144C may have a decreased composition ratio of Group VI elements or increased composition ratios of Group IV elements and Group V elements compared to the bulk region or the internal region. Accordingly, an electrical path due to a local trap site may be formed through the corner region144C of the switching pattern144, and thus the memory device100may have fast operation speed and excellent operation reliability.

FIG.26is a configuration diagram of a memory device according to some embodiments of the present disclosure.

Referring toFIG.26, a memory device400, according to some embodiments of the present disclosure, may include a memory cell array410, a decoder420, a read/write circuit430, an input/output buffer440and a controller450. The memory cell array410may have similar characteristics to the memory device100described with reference toFIGS.1to15.

A plurality of memory cells in the memory cell array410may be connected to the decoder420through a word line WL and may be connected to the read/write circuit430via a bit line BL.

The decoder420may receive an external address ADD and decode a low address and a column address to be accessed in the memory cell array410under the control of the controller450operating according to a control signal CTRL.

The read/write circuit430may receive data DATA from the input/output buffer440and a data line DL and write the data on the selected memory cell of the memory cell array410under the control of the controller450, or provide the data read from a selected memory cell of the memory cell array410to the input/output buffer440under the control of the controller450.

FIG.27is a configuration diagram of a data processing system including a memory device, according to some embodiments of the present disclosure.

Referring toFIG.27, a data processing system500may include a memory controller520between a host and a memory device400. The memory controller520may be configured to access the memory device400in response to needs of the host. The memory controller520may include a processor5201, an operation memory5203, a host interface5205, and a memory interface5207.

The processor5201may control the overall operation of the memory controller520, and the operating memory5203may store the application, data, and control signals to be required for the operation of the memory controller520. The host interface5205may perform the protocol conversion for data/control signal exchange between the host and the memory controller520. The memory interface5207may perform the protocol conversion for data/control signal exchange between the memory controller520and the memory device400. The memory device400may be the same as described above, and to the extent that an element is not described in detail with respect to this figure, it may be understood that the element is at least similar to a corresponding element that has been described elsewhere within the present disclosure. The data processing system500may be a memory card, but is not necessarily limited thereto.

FIG.28is a configuration diagram of a data processing system including a memory device, according to some embodiments of the present disclosure.

Referring toFIG.28, the data processing system600may include a memory device400, a processor620, an operation memory630, and a user interface640, and further include a communication module650as needed. The processor620may be a central processing device.

The operation memory630may store the application, data, and control signals to be required for the operation of the data processing system600. The user interface640may provide an environment in which the user may access the data processing system600and provide the data processing process and results of the data processing system600.

The memory device400may be the same as described above. The data processing system may be used as a disk device, as an internal/external memory card of a portable electronic device, or as an image processor and an application chipset.