Floating taps for decision feedback equalizer

Described are apparatuses and methods for generating floating taps for decision feedback equalizers. An apparatus may include a first delay cell including a first group of binary weighted sets of flip-flops to output a first signal, and a second delay cell including a second group of binary weighted sets of flip-flops to output a second signal. The apparatus may further include a multiplexer coupled to the first delay cell and the second delay cell to output a tap signal based on the first signal and the second signal. Other embodiments may be described and/or claimed.

TECHNICAL FIELD

This disclosure relates generally to electronic circuits. More particularly but not exclusively, the present disclosure relates to apparatuses and methods for generating floating taps for decision feedback equalizers.

BACKGROUND

Decision feedback equalizers (DFEs) may be used to remove interference on received signals, e.g., due to the channel's impulse response. The traditional DFE may remove interference directly after the initial pulse. However, in certain channels there can be more interference, or reflections, farther away that are caused by discontinuities in the channel. These reflections may occur at various locations depending on the channel or board used.

DETAILED DESCRIPTION

The embodiments described herein include apparatuses and methods generating floating taps for decision feedback equalizers (DFEs). In one embodiment, an apparatus may include a first delay cell including a first group of binary weighted sets of flip-flops to output a first signal, and a second delay cell including a second group of binary weighted sets of flip-flops to output a second signal. The apparatus may further include a multiplexer coupled to the first delay cell and the second delay cell to output a tap signal based on the first signal and the second signal. These embodiments will be described in more detail below. Other technical effects will also be evident from the descriptions to follow.

In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. However, it will be apparent to one skilled in the art that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

The terms “substantially,” “close,” “approximately,” “near,” and “about” generally refer to being within +/−20% of a get value. The term “scaling” generally refers to converting a design (schematic and layout) from one process technology to another process technology. The term “scaling” generally also refers to downsizing layout and devices within the same technology node. The term “scaling” may also refer to adjusting (e.g., slowing down) a signal frequency relative to another parameter, for example, power supply level.

FIG. 1is a block diagram that illustrates an example apparatus for generating floating taps fir decision feedback equalizers. In various embodiments, apparatus100may include DFE120coupled with clock circuitry110and training circuitry130. In various embodiments, DFE120may be used to remove interference on received data140. The received data140may be encoded iii a signal received on a channel.

In various embodiments, the signal received on the channel may suffer from interference. As an example, inter-symbol interference (ISI) may occur when a transmitted pulse broadens over more than one unit internal (UI). The UI is the minimum time interval between condition changes of a data transmission signal, also known as the pulse time or symbol duration time. One UI may or may not correspond to one cycle of an associated clock signal. As an example, in half-rate architecture, one clock cycle can be two UIs.

With interference, signal may be significantly degraded, e.g., even over a short distance of transmission within a circuit board. The amount of ISI that a DFE may correct is related to the number of taps that the DFE has. As an example, ISI may be characterized by the channel's impulse response, which usually starts as an initial pulse (also known as the cursor), followed by several smaller pulses. The number of pulses after the cursor and their respective severity may dependent on the channel. Thus, a DFE with a large number of taps may be used to reduce ISI in various channels. However, such a DFE may consume a lot of power and space.

In various embodiments, DFE120may generate floating taps to equalize the channel and reduce ISI in a wide range of symbols. The floating taps may correspond to respective delayed versions of the received signal, and may be used to remove reflections. DFE120may move taps around (e.g., as floating taps) depending on the channel (e.g., one channel might have a reflection 5 UI later while another might be 10 UI later). The tap positions in DEE120may be controlled by training circuitry130, e.g., using respective binary numbers. The locations of reflections may vary among different channels or in a same channel (e.g., based on temperature variations). In various embodiments, training circuitry130may enable DFE120to find a suitable floating tap position based on where reflections occur. Subsequently, DFE120may adjust the magnitudes and polarities of the tap weights (e.g., the amount of voltage/current used to remove the ISI) to match the channel characteristics, either manually or automatically based on a suitable adaptive algorithm. Then, the selected tap with its associated tap weight may be used to remove interference in the data signal.

In some embodiments, DFE120may be used to cancel interference without amplifying noise or crosstalk as a nonlinear equalizer. Thus, apparatus100may add equalization functions to input/output (I/O) circuitry even with significant channel losses, e.g., greater than 20 dB.

In various embodiments, clock circuitry110array generate a clock to be a half-rate of a data rate of the data140, and facilitate DFE120to operate in a half-rate architecture. As an example, if data140is received by apparatus100is a 10 Gbps signal, then clock circuitry110may generate a 5 GHz clock for DFE120. In various embodiments, DFE120may use two paths of flip-flops to save and delay the data signal. For example, DFE120may activate the odd path of flip-flops to sample the incoming data signal on every rising edge of the clock signal and propagate the signal ire the odd path. On the other hand, DFE120may activate the even path of flip-flops to sample the incoming data signal on every falling edge of the clock signal and propagate the signal in the even path. However, the odd path and even path may not be activated simultaneously. Therefore, the delay from one flip-flop to the next in the same odd or even path is two UI in this half-rate architecture.

FIG. 2is a schematic diagram of an example circuit200for generating floating taps for decision feedback equalizers, incorporating aspects of the present disclosure, in accordance with various embodiments. In some embodiments, circuit200may be a part of DFE120ofFIG. 1. In various embodiments, circuit200may include a plurality of pairs of delay blocks and respective multiplexers to multiplex the output from respective pairs of delay blocks. One multiplexer may output one or more tap signals based on complementary signals provided by any one pair of delay blocks.

In various embodiments, each delay block may have a binary weighted delay path based on binary weighted sets of flip-flops in the delay path. Such delay path may be controlled by a binary number that corresponds to a specific delay path. Flip-flops in the delay path may be added or removed, based on the binary number, to increase or decrease the total delay of the delay path.

In one embodiment, circuit200may have three pairs of delay blocks, namely the first pair of delay212and delay214, the second pair of delay242and delay244, and the third pair of delay272and delay274. Although only three pairs of delay blocks are shown inFIG. 2, in other embodiments, there may be more or fewer delay blocks as shown.

In one embodiment, the incoming data signal202may be first provided to the first pair of delay blocks, i.e., delay212and delay214. Meanwhile, a clock204may be provided to all delay blocks. However, delay214, delay244, and delay274may receive the clock204; while delay212, delay242, and delay272may receive an inverse version of the clock204. Therefore, delay214, delay244, and delay274may be activated on the rising edges of the clock204; and delay212, delay242, and delay272may be activated on the falling edges of the clock204.

In various embodiments, a pair of delay blocks, e.g., delay212and delay214, may output complementary signals that may be multiplexed into one or more taps, where each tap may be a delayed version of the data signal202. Hereinafter, complementary signals may also be referred to as even and odd signals. For example, the output signals from the delay blocks may be referred to as even signals if they are generated based on the falling edges of the clock204. Additionally, the output signals from the delay blocks may be referred to as odd signals if they are generated based on the rising edges of the clock204.

As an example, delay212may output the even part of the three taps, namely tap219, tap229, and tap239. On the other hand, delay214may output the odd part of the same three taps. In some embodiments, multiplexers218,228, and238may also receive the clock204and output the odd signal during a first half cycle of the clock signal and the even signal during a second half cycle of the clock signal. For example, when the clock204is high, these multiplexers may select the odd signal, e.g., outputted from delay214; when the clock204is low, these multiplexers may select the even signal, e.g., outputted from delay212. In this way, multiplexers218,228, and238may then multiplex the respective even and odd part of the tap signals to generate the complete tap signals, e.g., tap219, tap229, and tap239.

Similarly, the output signals from the pair of delay242and delay244may be used to generate another three taps, e.g., tap249, tap259, and tap269. Similarly, the output signals from the pair of delay272and delay274may be used to generate yet another three taps, e.g., tap279, tap289, and tap299.

In various embodiments, the delay in one delay block may be controlled or programmed based on the selection signal coupled with the delay block. As an example, the selection signal SS213may be used to control the delay in delay212, and the selection signal SS215may be used to control the delay in delay214. Similarly, the selection signal SS243may be used to control the delay in delay242, and the selection signal SS245may be used to control the delay in delay244. Similarly, the selection signal SS273may be used to control the delay in delay272, and the selection signal SS275may be used to control the delay in delay274. In some embodiments, the selection signal may be the same to a pair of delay blocks. As an example, SS213may be the same as SS215. Thus, the pair of delay blocks may generate complementary signals for the build-up of a complete tap. In some embodiments, the selection signals may be different, but they may carry the same binary control number. Thus, the pair of delay blocks may select similar delay paths in order to generate the same amount of delays for their complementary signals.

In some embodiments, the delay from one delay block may be based on the delay from its previous delay block. As an example, delay242receives the tap3even signal from delay212, which is a delayed version of the data202. After delay242adds more delays to its incoming signal, each output signal from delay242will have longer delay than any output signal from delay212. By the same reason, each output signal from delay272will have longer delay than any output signals from delay242. Therefore, the circuit200may output three sets of tap signals with different delays. As an example, tap219, tap229, and tap239may form the first set; tap249, tap259, and tap269may form the second set; and tap279, tap289, and tap299may form the third set. Each set of tap signals may be respectively controlled by their respective selection signals. Thus, different taps in one group may have different delays, while different sets of tap signals may also have different delays.

In various embodiments, the clock204may be a half-rate of the data rate of the data202, thus enable the circuit200to operate in a half-rate architecture. As an example, if data202is received as a 10 Gbps signal, then the clock204may be operate at 5 GHz. In this half-rate architecture, delay212or delay214runs at half the speed of the data signal202. Delay214may be active on the rising edge of the clock204, while the delay212may be active on the falling edge of the clock204. Thus, even though the incoming data202is coming in at twice the speed of the clock204, delay212and delay214may each pick up half of the data202. This allows a multiplexer, e.g., multiplexer218, to multiplex the complementary output signals from delay212and delay214to form a complete tap, which is a delayed version of data202. Therefore, circuit200may still offer the same performance of a circuit that would use a full-rate clock, but circuit200may save power for operating with the half-rate architecture.

FIG. 3is a schematic diagram of an example circuit300for a delay block, e.g., the delay212ofFIG. 2. Those elements ofFIG. 3having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments, elements and features discussed previously may not be repeated.

In this embodiment, circuit300may use a collection of flip-flops and multiplexers to create three programmable delays needed to save the data202for reflection cancellation. The flip-flops are used to store the information, while the multiplexers are used to select the path that the data202travels. The delay is programmable by changing the control signals for the multiplexers such that a different path may be selected. In various embodiments, circuit300may be used in DFEs to save power.

In various embodiments, circuit300may include multiplexers310,320,330, and340coupled in series, with respective binary weighted sets (BWS) of flip-flops BWS301, BWS302, BWS304, and BWS308, coupled between successive pairs of the multiplexers. BWS301, BWS302, BWS304, and BWS308may be binary weighted with respect to one another. As an example, BWS301, the set of flip-flops before multiplexer310, may only include one (1=20) flip-flop. As another example, BWS302, the set of flip-flops between multiplexers310and320, may include two (2=21) flip-flops. As another example, BWS304, the set of flip-flops between multiplexers320and330, may include four (4=22) flip-flops. As another example, BWS308, the set of flip-flops between multiplexers330and340, may include eight (8=23) flip-flops. In some embodiments, circuit300may be further extended to have a binary number (e.g., 2n) of flip-flops interpolating two multiplexers, e.g., sixteen (16=24) flip-flops after multiplexer340if circuit300is further to be extended.

In various embodiments, a binary control number may be used to program the length of delay in circuit300, and the delay may be changed based on whether the binary weighted sets of flip-flops are included or excluded from the delay path. In some embodiments, a binary number may set respective selection signals to multiplexers, so that respective flip-flops in BWS301,302,304, or308may be selected. Subsequently, the delay may be increased or decreased by adding or removing 2N-1flip-flops from the delay path based on whether the Nthbit is set in the binary control number.

As an example, the binary control number “1001” may enable SS312and SS342, but disable SS322and332. Consequently, data202will go through BWS301and BWS308, but bypass BWS302and BWS304. Thus, the binary control number “1001” may use nine flip-flops in circuit300, which is 1001 in binary.

Because of the simplification of the delay path based on binary weighted sets of flip-flops, the binary control number may determine which flip-flops are being used in the delay path. In various embodiments, if a set of flip-flops are not being used in the selected delay path, then this set of flip-flops may be turned off so that they are not contributing to the total power consumption. In various embodiments, a selection signal may be input to a control unit connected to a set of flip-flops to deactivate the set of flip-flops. As an example, logic gate314,324,334, or344may implement logical conjunctions, and each may receive input from a respective selection signal as well as the clock204. In the example of using “1001” as the binary control number, SS322and SS332are to be deactivated, e.g., to be set as zero. In this case, the logic gates324and334will turn off BWS302and BWS304respectively.

In this embodiment, the delayed data signal from multiplexer340is sent to the three flip-flops,362,372, and382to create three separate output signals TE364, TE374, and TE384that are delayed by one UI from one another (e.g., TE374is delayed by one UI from TE364and TE384is delayed by one UI from TE374). TE364, TE374, or TE384may include either the odd part or the even part of a complete tap signal. Referring back toFIG. 2, the output signals TE364, TE374, and TE384may be multiplexed with their respective complementary signals to form complete tap signals. As an example, an individual multiplexer may receive the pair of complementary signals and generate an output signal that switches between the complementary signals based on the clock signal.

In some embodiments, clock204may be a half-rate clock comparing to the rate associated with data202. In this a half-rate design, each flip-flop among the binary weighted sets of flip-flops may cause a two-UI delay. In order to make a delay of one-UI apart among TE364, TE374, or TE384in some embodiments, flip-flop372may use an inverse version of the clock signal coming to flip-flop362and flip-flop382. Further, the multiplexer350may receive another selection signal of SS352and output the clock signal204or an inversed version of the clock204depending on the additional delay needed at TE364, TE374, or TE384. As an example, for getting a 10-UI delay at TE364, BWS301, BWS302and BWS308may be bypassed, but BWS304may be used, which gives a total delay of 8 UI as the output from multiplexer340to flip-flop362. Because this is a half-rate design, flip-flop362may add the remaining two UI to the delay path if the clock for flip-flop362is the same as the clock used for BWS304. Resultantly, circuit300may generate a 10-UI delay at TE364, 11-UI delay at TE374, and 12-UI delay at TE384. As another example, for getting a 9-UI delay at TE364, BWS304may be used and the rest of binary weighted sets of flip-flops may be bypassed, similar to the previous example. Because this is a half-rate design, flip-flop362may add the remaining one UI to the delay path if the clock for flip-flop362is inversed from the clock used for BWS304, which may be obtained if multiplexer350is adjusted to output the inversed version of clock204.

In circuit300, the delay path may be determined by a binary control number and does not require a complicated encoder. Without any encoders, the number of blocks in the circuit may be reduced. Moreover, certain sets of flip-flops may be disabled if they are not used for the delay, thus introducing more power-savings. Further, power may be reduced because circuit300may be used in a half-rate architecture.

In various embodiments, in order to calibrate circuit300, a training sequence may be used. This sequence may be used to determine the delay for each set of taps. As an example, all of the possible tap positions may be cycled through and a respective amount of interference removed based on each tap position may be determined. In this way, the training sequence may be used to calibrate circuit300to a suitable tap position to remove the most amount of interference. In some embodiments, the floating tap based on circuit300may be used together with fixed taps that the standard DFE may have to remove even more amount of interference.

FIG. 4is a schematic diagram of an example circuit for a flip-flop, e.g., any one among the binary weighted sets of flip-flops depicted inFIG. 3. Those elements ofFIG. 4having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such. So as not to obscure the embodiments, elements and features discussed previously may not be repeated.

In various embodiments, flip-flop400may include a first inverter420to receive the clock204and a second inverter410to receive an inverted version of the clock204. In various embodiments, inverter410and inverter420may be controlled by their respective clock signals. As an example, the inverter420may perform normal functions when the clock204is high for inverter420. However, inverter420may not pass through any information when the clock204is low for inverter420.

In various embodiments, flip-flop400may not include additional “keepers,” which are a group of additional inverters (e.g., cross-coupled inverters) commonly used in traditional flip-flops to save the data. Thus, flip-flop400may further reduce the number of devices in the circuit, thus saving more power and area. Without any additional keepers, data in flip-flop400is still unlikely to be disturbed by other devices because the amount of load for flip-flop400is usually minimal.

In various embodiments, the power saving features associated with the circuit design in flip-flop400, in combination with the power saving features in connection with the binary weighted sets of flip-flops in the delay blocks operated in a half-rate architecture, may allow for a low power solution for creating a programmable delay for several sets of floating taps, e.g., as with circuit200. In one embodiment, the worst-case power consumption of circuit200may range from between 1.65 mW to 2.61 mW depending on the length of the delay, which may be translated to at least 80% or more power savings compared to traditional designs. Therefore, the design principles as disclosed herein may be appealing for use in chips that have strict power requirements.

FIG. 5is a flow diagram of an example process executable by an example apparatus for generating a floating tap. As shown, process500may be performed by a circuit (e.g., circuit200) utilizing the design principal as disclosed herein to implement one or more embodiments of the present disclosure.

In embodiments, at510, the process500may include receiving a data signal, e.g., by delay212and delay214ofFIG. 2. At520, the process500may include selecting a first delay path based on a first group of binary-weighted sets of flip-flops. As an example, delay212may include a binary weighted sets of flip-flops, e.g., such as those illustrated inFIG. 3. In various embodiments, the first delay path may be controlled by a binary number in the selection signal of SS213.

In various embodiments, at530, the process500may include activating the first delay path responsive to a rising edge of a clock signal to pass the data signal through the first delay path to generate a first signal. As an example, the clock signal may be generated by clock circuitry110ofFIG. 1, and the clock signal may be at a half-rate of the rate of the data signal. During the rising edge of the clock signal, the first delay path may be activated to add delays to the data signal. In various embodiments, some flip-flops in the binary weighted sets of flip-flops may be deactivated if they are excluded from the first delay path to further save power for the circuit.

In embodiments, at540, the process500may include selecting a second delay path from a second group of binary weighted sets of flip-flops. As an example, delay214may include a binary weighted sets of flip-flops, e.g., such as those illustrated inFIG. 3. In various embodiments, the second delay path may be controlled by a binary number, e.g., in the selection signal of SS215. In various embodiments, the controlling binary number for selecting the second delay path may be the same as the controlling binary number for selecting the first delay path. Thus, the second delay path may provide the odd part of a tap signal while the first delay path may provide the even part of the tap signal.

In embodiments, at550, the process500may include activating the second delay path responsive to a falling edge of the clock to pass the data signal through the second delay path to generate a second signal. As previously discuss in connection with block530, the clock signal may be at a half-rate of the rate of the data signal. During the falling edge of the clock signal, the second delay path may be activated to add delays to the data signal. Similarly, some flip-flops in the binary weighted sets of flip-flops may be deactivated if they are excluded from the second delay path to further save power for the circuit. It may be noted that since the rising edges and the falling edges alternate in the clock signal, the first and second delay paths may not be activated simultaneously.

In embodiments, at560, the process500may include combining the first signal and the second signal to obtain a tap signal. In various embodiments, the first signal and the second signal may be complementary to each other as they represent even and odd parts of a delayed data signal. These two signals may be combined, e.g., through multiplexer218ofFIG. 2, into a tap signal, e.g., tap219ofFIG. 2. Such tap signal may be used to remove interference (e.g., ISI) of the data signal.

In various embodiments, it may be desirable to remove as much interference as possible. However, reflections may occur at various locations, e.g., depending on the channel or board used. Thus, the process500may further include preparing various tap signals with different tap positions and different delay paths (e.g., via blocks520,530,540,550, and560). Subsequently, respective amounts of interference removed from the data signal may be obtained based on these tap positions. Thus, a DFE may be calibrated to use a suitable tap position based on the respective amounts of interference removed from the data signal. Even further, a DFE with floating taps may work in synergy with the fixed taps that a standard DFE may have to remove the most amount of interference in some embodiments.

FIG. 6is a set of plots showing various tap signals, e.g., generated by DFE120ofFIG. 1or circuit200ofFIG. 2. Plot640shows the data signal coming to the DFE. Plot650shows the clock signal generated for the DFE. In this embodiment, the clock signal may be at a half-rate of the clock associated with the data signal. Plots611,612, and613shows three tap signals from one delay block with one UI apart, e.g., corresponding to tap219, tap229, and tap239ofFIG. 2. Plots621,622, and623shows three tap signals from another delay block with one UI apart, e.g., corresponding to tap249, tap259, and tap269ofFIG. 2. Similarly, Plots631,632, and633shows three tap signals from yet another delay block with one UI apart, e.g., corresponding to tap279, tap289, and tap299ofFIG. 2.

In various embodiments, each set of taps may be independently controlled. As shown, the tap signal in plot611has a programmable delay from the data signal in plot640, while the tap signal in plot621has another programmable delay from the data signal in plot640. However, the tap signal in plot631has another prolonged delay from the data signal in plot640. Also, it may be noted that the delay between respective tap signals in plot611and plot621is substantially different from the delay between respective tap signals in plot621and plot631because each delay block (e.g., the pair of delay212and214, the pair of delay242and244, and the pair of delay272and274ofFIG. 2) may be independently controlled, e.g., based on the controlling binary number conveyed in their respective selection signals (e.g., SS213, SS243, and SS273ofFIG. 2). Therefore, DFEs as disclosed herein may effectively control the limited number of delay blocks to strategically select floating tap position based on where the reflections occur.

FIG. 7is another set of plots showing various tap signals, e.g., generated by DFE120ofFIG. 1or circuit200ofFIG. 2. Similar toFIG. 6, plot740shows the data signal coming to the DFE, and plot750shows the clock signal generated for the DFE, which may be at a half-rate of the clock associated with the data signal. Plots711,712, and713show three tap signals from one delay block with one UI apart, e.g., corresponding to tap219, tap229, and tap239ofFIG. 2. Plots721,722, and723show three tap signals from another delay block with one UI apart, e.g., corresponding to tap249, tap259, and tap269ofFIG. 2. Similarly, Plots731,732, and733show three tap signals from yet another delay block with one UI apart, e.g., corresponding to tap279, tap289, and tap299ofFIG. 2.

InFIG. 7, a common delay schema is selected for all three sets of taps. As shown, output tap signals are slightly delayed versions of the input data signal in plot740, and all tap signals are follow each other closely. With this configuration, a DFE as disclosed herein may cover a range of tap positions to calibrate the DFE to target where the reflections occur.

FIG. 8is a block diagram that illustrates an example computer system800suitable for practicing the disclosed embodiments with any of the design principles described with reference toFIGS. 1-5, in accordance with various embodiments. In one embodiment, compute system800represents a mobile computing device, such as a computing tablet, a mobile phone or smartphone, a wireless-enabled e-reader, or another wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing system800.

As shown, computer system800may include a power management820; a number of processors or processor cores810, a system memory830having processor-readable and processor-executable instructions880stored therein, a non-volatile memory (NVM)/storage840, an I/O controller850, and a communication controller860. For the purpose of this application, including the claims, the terms “processor” and “processor cores” may be considered synonymous, unless the context clearly requires otherwise. Those elements ofFIG. 8having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

In one embodiment, processors810may include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processors810may include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations may include operations related to input/output (I/O) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing system800to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

The one or more NVM/storage840and/or the system memory830may comprise a tangible, non-transitory computer-readable storage device (such as a diskette, hard drive, compact disc read only memory (CD-ROM), hardware storage unit, flash memory, phase change memory (PCM), solid-state drive (SSD) memory, and so forth). Instructions880stored in system memory830and/or NVM/storage840may be executable by one or more of the processors810. Instructions880may contain particular instructions of an operating system and one or more applications.

Computer system800may also include input/output devices (not shown) coupled to computer system800via I/O controller850. I/O controller850illustrates a connection point for additional devices that connect to computing system800through which a user might interact with the system. For example, various devices that may be coupled to the computer system800via I/O controller850may include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

In various embodiments, I/O controller850may include apparatus100ofFIG. 1, circuit200ofFIG. 2, circuit300ofFIG. 3, and/or flip-flop400ofFIG. 4. In various embodiments, I/O controller850may include a DFE (e.g., like DFE120ofFIG. 1) to generate floating taps to equalize an I/O channel and reduce ISI in a wide range of symbols.

In embodiments, communication controller860may provide an interface for computing system800to communicate over one or more network(s) and/or with any other suitable device. Communication controller860may include any suitable hardware and/or firmware, such as a network adapter, one or more antennas, wireless interface(s), and so forth. In various embodiments, communication controller860may include an interface for computing system800to use near field communication (NFC), optical communications, or other similar technologies to communicate directly (e.g., without an intermediary) with another device. In various embodiments, communication controller860may interoperate with radio communications technologies such as, for example, Wideband Code Division Multiple Access (WCDMA), Global System for Mobile Communications (GSM), Long Term Evolution (LTE), WiFi, Bluetooth®, Zigbee, and the like.

In various embodiments, communication controller860may include apparatus100ofFIG. 1, circuit200ofFIG. 2, circuit300ofFIG. 3, and/or flip-flop400ofFIG. 4. In various embodiments, communication controller860may include a DFE (e.g., like DFE120ofFIG. 1) to generate floating taps to equalize even a high-loss communication channel and reduce ISI in a wide range of symbols.

The various elements ofFIG. 8may be coupled to each other via a system bus870, which represents one or more buses. In the case of multiple buses, they may be bridged by one or more bus bridges (not shown). Data may pass through the system bus870through the I/O controller850, for example, between an output terminal and the processors810.

System memory830and NVM/storage840may be employed to store a working copy and a permanent copy of the programming instructions implementing one or more operating systems, firmware modules or drivers, applications, and so forth, herein collectively denoted as instructions880. In embodiments, instructions880may include logic for generating floating taps for decision feedback equalizers described in this disclosure. The permanent copy of the programming instructions may be placed into permanent storage in the factory, or in the field, via, for example, a distribution medium (not shown), such as a compact disc (CD), or through the communication controller860(from a distribution server (not shown)).

In some embodiments, at least one of the processor(s)810may be packaged together with I/O controller850to form a System in Package (SiP). In some embodiments, at least one of the processor(s)810may be integrated on the same die with I/O controller850. In some embodiments, at least one of the processor(s)810may be integrated on the same die with I/O controller850to form a System on Chip (SiC).

According to various embodiments, one or more of the depicted components of the system800and/or other element(s) may include a keyboard, LCD screen, non-volatile memory port, multiple antennas, graphics processor, application processor, speakers, or other associated mobile device elements, including a camera. The remaining constitution of the various elements of the computer system800is known, and accordingly will not be further described in detail.

The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to be limited to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various modifications are possible. For example, the configuration and connection of certain elements in various embodiments that have been described above may be modified without departing from the teachings in connection withFIGS. 1-5. These and other modifications can be made in light of the above detailed description. The terms used in the following claims should not be construed to be limited to the specific embodiments disclosed in the specification.

only one of the elements. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element.

Example 1 is a decision feedback equalizer (DFE). The DFE may include a first delay cell including a first group of binary weighted sets of flip-flops, the first delay cell to receive a data signal and output a first signal based on a first sample of the data signal on a falling edge of a clock signal and a first delay path selected from the first group of binary weighted sets of flip-flops; a second delay cell coupled to the first delay cell and including a second group of binary weighted sets of flip-flops, the second delay cell to receive the data signal and to output a second signal based on a second sample of the data signal on a rising edge of the clock signal and a second delay path selected from the second group of binary weighted sets of flip-flops; and a multiplexer coupled to the first delay cell and the second delay cell to receive the first signal and the second signal, the multiplexer to output a tap signal based on the first signal and the second signal.

Example 2 may include the subject matter of Example 1, and may further include a clock circuitry to generate the clock signal to be a half-rate of a data rate of the data signal.

Example 3 may include the subject matter of Example 1 or 2, and may further include control circuitry to power off one or more flip-flops of the first group of binary weighted sets of flip-flops when the one or more flip-flops are excluded from the first and second delay paths.

Example 4 may include the subject matter of Example 3, and may further specify that the control circuitry comprises a logic gate to receive the clock signal and a selection signal, and a selection multiplexer coupled to the logic gate to receive the selection signal; and wherein the control circuitry is to power off one of the one or more flip-flops when the selection signal has a first logic value.

Example 5 may include any subject matter of Examples 1-4, and may further specify that wherein the first delay cell is to select the first delay path based on a binary number, and wherein the second delay cell is to select the second delay path based on the same binary number.

Example 6 may include any subject matter of Examples 1-5, and may further specify that the multiplexer is to output the tap signal as a delayed version of the data signal, and the multiplexer is to output the first signal during a first half cycle of the clock signal and to output the second signal during a second half-cycle of the clock signal.

Example 7 may include any subject matter of Examples 1-6, and may further specify that at least one flip-flop of the first or second groups of binary weighted sets of flip-flops includes only two inverters, including a first inverter to receive the clock signal and a second inverter to receive an inverted version of the clock signal.

Example 8 may include any subject matter of Examples 1-7, and may further specify that the first group of binary weighted sets of flip-flops comprises a plurality of selecting multiplexers coupled in series, and wherein respective sets of flip-flops of the first group of binary weighted sets of flip flops are coupled between successive pairs of the selecting multiplexers.

Example 9 is a receiver circuitry. The receiver circuitry may include a decision feedback equalizer (DFE) to output floating tap signals for equalizing a data signal, the DFE having: a first pair of delay cells to output a first set of tap signals based on the data signal, wherein the first set of tap signals are delayed from one another by one unit interval (UI) of a clock signal, and an initial tap signal of the first set of tap signals has a first programmable delay from the data signal; and a second pair of delay cells, coupled to the first pair of delay cells, to output a second set of tap signals based at least in part on the first set of tap signals, wherein the second set of tap signals are delayed from one another by one UI, and an initial tap signal of the second set of tap signals has a second programmable delay from the data signal; wherein the first and second programmable delays are based at least in part on respective delay paths selected from respective binary-weighted sets of flip-flops in the first and second pairs of delay cells.

Example 10 may include the subject matter of Example 9, and may further include a clock circuitry to generate the clock signal to be a half-rate of a data rate of the data signal.

Example 11 may include the subject matter of Example 9 or 10, and may further include a training circuitry, coupled to the DFE, to calibrate the first or second programmable delay based on respective amounts of interference removed from the data signal by the first and second sets of tap signals.

Example 12 may include any subject matter of Examples 9-11, and may further specify that the first and second pairs of delay cells are to select the respective delay paths based on respective binary numbers.

Example 13 may include any subject matter of Examples 9-12, and may further specify that wherein the first pair of delay cells comprise: an even delay cell to output an even part of the initial tap signal of the first set of tap signals based on a first sample of the data signal on a falling edge of the clock signal; and an odd delay cell to output an odd part of the initial tap signal of the first set of tap signals based on a second sample of the data signal on a rising edge of the clock signal; wherein the clock signal is at a half-rate of a rate of the data signal.

Example 14 may include the subject matter of Example 13, and may further specify that wherein the even delay cell is to select a first delay path based on a binary number; and wherein the odd delay cell is to select a second delay path based on the same binary number.

Example 15 may include the subject matter of Example 13 or 14, and may further specify that wherein the first pair of delay cells further comprise a multiplexer, coupled to the even delay cell and the odd delay cell, to output the first set of tap signals.

Example 16 may include the subject matter of Example 15, and may further specify that wherein the multiplexer is to output signals from the even delay cell during a first half cycle of the clock signal and to output signals from the odd delay cell during a second half-cycle of the clock signal.

Example 17 is a method for decision feedback equalization, which may include receiving a data signal; selecting a first delay path for a first group of binary weighted sets of flip-flops; activating the first delay path responsive to a rising edge of a clock signal to pass the data signal through the first delay path to generate a first signal; selecting a second delay path from a second group of binary weighted sets of flip-flops; activating the second delay path responsive to a falling edge of the clock to pass the data signal through the second delay path to generate a second signal; and combining the first signal and the second signal to obtain a tap signal.

Example 18 may include the subject matter of Example 17, and may further include deactivating one or more flip-flops in the first or second groups of binary weighted sets of flip-flops when the one or more flip-flops are excluded from the first and second delay paths.

Example 19 may include the subject matter of Example 17 or 18, and may further include preparing a plurality of tap positions with different delay paths; obtaining respective amounts of interference removed from the data signal based on the plurality of tap positions; and determine a calibrated tap position based on the respective amounts of interference removed from the data signal.

Example 20 may include any subject matter of Examples 17-19, and may further include removing interference of the data signal based on the tap signal.

Example 21 is at least one storage medium having instructions configured to cause an apparatus, in response to execution of the instructions by the apparatus, to practice any subject matter of Examples 17-20.

Example 22 is an apparatus, which may include means to practice any subject matter of Examples 17-20.