Self-aligned nano-cross-point phase change memory

One embodiment is a phase change memory that includes a heater element transversely contacting a storage element of phase change material. In particular, an end of the storage element contacts an end of the heater element. A first pair of dielectric spacers is positioned on opposite sides of the first heater element and a second pair of dielectric spacers is positioned on opposite sides of the first storage element. The storage element, heater element, and first and second pairs of dielectric spacers can be made by a spacer patterning technique.

BACKGROUND

1. Technical Field

The present invention relates generally to phase change memories.

2. Description of the Related Art

As is known, phase change memories use a class of materials that have the property of switching between two phases having distinct electrical characteristics, associated to two different crystallographic structures of the material, and precisely an amorphous, disorderly phase and a crystalline or polycrystalline, orderly phase. The two phases have resistivities of considerably different values.

Currently, the alloys of elements of group VI of the periodic table, such as Te or Se, referred to as chalcogenides or chalcogenic materials, can be used advantageously in phase change memory cells. The currently most promising chalcogenide is formed from an alloy of Ge, Sb and Te (Ge2Sb2Te5), which is now widely used for storing information on overwritable disks and has been also proposed for mass storage.

In the chalcogenides, the resistivity varies by two or more orders of magnitude when the material passes from the amorphous (more resistive) phase to the crystalline (more conductive) phase, and vice versa.

Phase change can be obtained by locally increasing the temperature. Below 150° C., both phases are stable. Starting from an amorphous state, and rising the temperature above 200° C., there is a rapid nucleation of the crystallites and, if the material is kept at the crystallization temperature for a sufficiently long time, it undergoes a phase change and becomes crystalline. To bring the chalcogenide back to the amorphous state it is necessary to raise the temperature above the melting temperature (approximately 600° C.) and then rapidly cool off the chalcogenide.

In a phase change memory, a plurality of memory cells are arranged in rows and columns to form an array. Each memory cell is coupled to a respective selection element, which may be implemented by any switching device, such as an ovonic threshold switch (OTS), a PN diode, a bipolar junction transistor or a MOS transistor. Each memory cell includes a memory region of a chalcogenide material in contact with a resistive electrode, also called heater. A storage element is formed at a contact area between the chalcogenide region and the heater. The heater is connected to a conduction terminal of the selection element.

In fact, from an electrical point of view, the crystallization temperature and the melting temperature are obtained by causing an electric current to flow through the resistive electrode in contact or close proximity with the chalcogenic material and thus heating the chalcogenic material by Joule effect. In particular, when the chalcogenic material is in the amorphous, high resistivity state (also called the reset state), applying a voltage/current pulse of a suitable length and amplitude and allowing the chalcogenic material to cool slowly causes the chalcogenic material changes its state and switch from a high resistivity to a low resistivity state (also called the set state). Vice versa, when the chalcogenic material is in the set state, applying a voltage/current pulse of suitable length and high amplitude causes the chalcogenic material to switch to the amorphous phase.

BRIEF SUMMARY

One embodiment is a phase change memory that includes a first heater element transversely contacting a first storage element of phase change material. In particular, an end of the storage element contacts an end of the heater element. A first pair of dielectric spacers is positioned on opposite sides of the first heater element and a second pair of dielectric spacers is positioned on opposite sides of the first storage element.

One embodiment is a method that deploys a self-aligned scheme between heaters and PCM storage elements using a pitch multiplication patterning method. A sub-lithography patterning for the interface between heater and storage element is possible due to the following two features:

1) with a pitch multiplication method, the heaters and PCM storage elements are formed as spacers of the pitch-multiplied pattern;

2) with the self-aligned scheme between heaters and storage elements, no registration overlay is required. This reliably creates a sub-lithographic device feature. These two features reliably create a sub-lithographic cross-point phase change memory at lower cost of patterning tools.

DETAILED DESCRIPTION

One embodiment is a phase change memory (PCM) device10A shown inFIG. 1. The PCM device10A includes an array of PCM cells12A. Only three PCM cells are shown for convenience of illustration. Those skilled in the art will understand that the PCM device10A could include an array of much more such PCM cells.

Each PCM cell12A includes a PCM storage element14made of a phase change material. Preferably, the storage element has a sublithographic thickness, and in one embodiment is in the range of 5-20 nm. The phase change material is a phase change material suitable for non-volatile memory data storage having electrical properties (e.g., resistance) that may be changed through the application of energy such as, for example, heat, light, voltage potential, or electrical current. An example of a phase change materials include a chalcogenide material, which is a material that includes at least one element from column VI of the periodic table or that includes one or more of the chalcogen elements, e.g., any of the elements of tellurium, sulfur, or selenium. In one embodiment, the memory material is a chalcogenide element composition from the class of tellurium-germanium-antimony material or a GeSbTe alloy ((TexGeySbz, such as x=2, y=2, z=5), although the scope of the present disclosure is not limited to just these materials.

The storage elements14are formed on respective conductive bottom electrodes16that could simply correspond on a 1 to 1 basis with the storage elements14as shown inFIG. 1. Alternatively, each bottom electrode16can be an elongated strip on which an entire row or column of storage elements14can be formed. In one embodiment, the bottom electrodes16are extend entirely along a conductive wordline or bitline (not shown) of the array of the PCM device10A.

Extending transversely on and in contact with the storage elements14respectively are heaters18of a resistive material. Preferably, the each heater18has a sublithographic thickness such that the heater18and the corresponding storage element14contact one another at a contact surface that is sublithographic in two dimensions. In one embodiment the thickness of each heater is in the range of 5-20 nm. The heaters18may be formed, for example, from titanium silicon nitride. However, other heater materials may also be used.

A top electrode20extends transversely on the heaters18and a conductive line22extends along the length of the top electrode20. The conductive line22can be a bitline or a wordline of the array of the PCM device10A.

In the embodiment shown inFIG. 1, each of the storage elements14is sandwiched by a pair of dielectric spacers26and each of the heater elements is sandwiched by a pair of dielectric spacers28. Like the storage elements14and heaters18, each of the dielectric spacers26,28preferably has a sublithographic thickness that in one embodiment is in the range of 5-20 nm. As discussed in more detailed below, in one embodiment all of the storage elements14, heaters18, and dielectric spacers26,28are formed using a spacer patterning technique in which spacer layers are formed along sidewalls of structures and then anisotropically etched to leave spacer structures have sublithographic thicknesses.

FIG. 2shows an alternative PCM device10B. This alternative embodiment, and those alternative embodiments and other alternatives described herein, are substantially similar to previously described embodiments, and common acts and structures are identified by the same reference numbers. Only significant differences in operation and structure are described below.

The PCM device10B shown inFIG. 2is similar to the PCM device10A ofFIG. 1except that the heaters18are positioned on the bottom electrodes16and the storage elements14are positioned between the heaters18and the top electrode20. As such, the PCM device10B includes a set of PCM cells12B that each include one of the heaters18in contact with a corresponding one of the storage elements14. It will be immediately apparent to those skilled in the art that the same method may be used to make both of the PCM devices10A,10B except for the change in positioning of the storage elements14and heaters18.

A PCM device10C according to one embodiment is shown inFIG. 3. The PCM device10C is like the PCM device10A ofFIG. 1except that the PCM device10C includes an ovonic threshold switch (OTS) layer26positioned between the heaters18and the top electrode20. In one embodiment, the OTS layer26is a switch material such as a chalcogenide alloy or a pnictide alloy. In effect, the OTS layer26forms ovonic threshold switches28at the intersections of the OTS layer26and the heaters18, respectively. As a result, the PCM device10C includes a plurality of PCM cells12C each including one of the storage elements14, one of the heaters18, and one of the OTS28.

An ovonic threshold switch is either on or off depending on the amount of voltage potential applied across the switch and, more particularly, whether the current through the switch exceeds its threshold current or voltage, which then triggers the device into an on state. The off state may be substantially electrically non-conductive and the on state may be a substantially conductive state with less resistance than the off state.

The switch material may be a material in a substantially amorphous state, positioned between two electrodes, that may be repeatedly and reversibly switched between a higher resistance off state that is greater than about 10 megaOhms and a relatively lower resistance on state that is about 1000 Ohms in series with the holding voltage by the application of electrical current or potential.

Each switch has an IV curve similar to that of a phase change memory element that is in an amorphous state. However, unlike a phase change memory element, the ovonic threshold switch does not change phase. That is, the switching material of the ovonic threshold switch is not a programmable material and, as a result, the switch may not be a memory device capable of storing information. For example, the switching material may remain permanently amorphous and the IV characteristics may remain the same throughout the operating life.

In the low voltage, a low electric field mode, where the voltage applied across the switch is less than the threshold voltage Vth, the switch may be off or non-conducting and exhibits a relatively high resistance (greater than about 10 megaOhms). The switch may remain in the off state until its sufficient voltage, namely, the threshold voltage, is applied or a sufficient current is applied, namely, the threshold current, that switches the device to a conductive relatively low resistance on state. After a voltage potential of greater than about the threshold voltage is applied across the device, the voltage potential across the device may drop or snapback to a holding voltage Vhold. Snapback may refer to the voltage difference between the threshold voltage and the holding voltage of the switch.

In the on state, the voltage potential across the switch may remain close to the holding voltage as current passing through the switch is increased. The switch may remain on until the current through the switch drops below a holding current. Below this value, the switch may turn off and return to a relatively high resistance, non-conductive off state, until the threshold voltage and current are again exceeded.

The PCM devices10A-10C ofFIGS. 1-3can be manufactured according to a method that deploys a self-aligned scheme between the heaters18and PCM storage elements14using a pitch multiplication patterning method. A sub-lithography patterning for the interface between the heaters and storage elements is possible.

In one embodiment, the heaters are first aligned on conduction contacts of respective selection elements. Since minimization of the contact area between the heaters and the chalcogenic regions is desired in phase change memory cells, the heaters are normally in the form of walls or rods having sub-lithographic cross-dimensions, i.e., thickness or diameter (“sublithographic” means here a linear dimension smaller than the minimum dimension achievable with current UV lithographic techniques, and hence smaller than 50 nm). In one embodiment, the sub-lithographic cross-dimensions of the heaters and storage elements are approximately 5-20 nm. Structures having such small dimensions can be made by controlled layer deposition steps.

FIGS. 4-13show various steps of a process for manufacturing a PCM device10according to one embodiment.FIG. 4shows a series of strip-shaped bottom electrodes16alternately positioned with a series of first dielectric strips30. The first dielectric strips30may be formed of a first dielectric material, such as silicon oxide or silicon nitride.

The order in which the bottom electrodes16and first dielectric strips30are formed is not important. One could first form a dielectric layer, etch the dielectric layer using a mask into the series of first dielectric strips30spaced apart from one another, and then form the bottom electrodes16between the first dielectric strips. For example, one could deposit a conductive layer on the first dielectric strips and etch back until the electrodes and first dielectric strips have the same height. Alternatively, one could first form a conductive layer, etch the conductive layer using a mask into the series of strip-shaped bottom electrodes16spaced apart from one another, and then form the first dielectric strips30between the bottom electrodes, such as by depositing a dielectric layer on the bottom electrodes and etching back until the bottom electrodes and first dielectric strips have the same height.

Next, a series of second dielectric strips32is formed transversely on the bottom electrodes16and the first dielectric strips30. In one embodiment, the second dielectric strips32are spaced apart from each other at a pitch that is twice the pitch at which the PCM storage elements18will be formed. Like the first dielectric strips30, the second dielectric strips32can be formed by depositing a dielectric sheet layer, and then etching back using a strip-shaped mask.

In one embodiment, the second dielectric strips32are formed of a second dielectric material that is different than the first dielectric material used to form the first dielectric strips30. For example, if the first dielectric material is silicon oxide, the second dielectric material can be silicon nitride or various other dielectric materials. The use of such different dielectric materials enables the second dielectric strips32to be etched without etching the first dielectric strips30. Alternatively, the same dielectric materials could be used for the first and second dielectric strips30,32and an etch stop layer, of a different material than the second dielectric strips32, could be employed between the first and second dielectric strips30,32to accomplish the same selective etching function. Another alternative is to use the same dielectric materials for the first and second dielectric strips30,32with the etch stop layer, and stop the etching of the dielectric layer used to make the second dielectric strips32when the underlying bottom electrodes16are reached.

Next, as shown inFIG. 5, a series of phase change spacer layers14A and dielectric spacer layers26A are formed on opposite sidewalls of the second dielectric strips32. In one embodiment, the dielectric spacer layers26A are formed with a third dielectric material that is selectively etchable with respect to the first and second dielectric strips30,32. The phase change spacer layers14A and dielectric spacer layers26A can be formed using known spacer patterning techniques. For example, first ones of the dielectric spacer layers26A can be formed by conformally depositing a dielectric layer one the exposed top surface portions of the first electrodes16and the first dielectric strips30and on the top and side walls of the second dielectric strips32and anisotropically etching the deposited dielectric layer until the first electrodes16and first dielectric strips30are exposed, which leaves the dielectric spacer layers26A on the sidewalls of the second dielectric strips32. A similar process is performed to form the phase change spacer layers14A using a conformally deposited and anisotropically etch phase change layer. Another similar process is performed to form the second ones of the dielectric spacer layers26A on the phase change spacer layers14A, thereby sandwiching the phase change spacer layers14A between the dielectric spacer layers26A.

InFIG. 6, first dielectric filler strips34are formed between the structures formed by the second dielectric strips32, dielectric spacer layers26A, and phase change spacer layers14A. Such dielectric filler strips34can be formed by conformally depositing another dielectric layer and planarizing, such as by CMP, the dielectric layer until the dielectric filler strips34have the same height as the second dielectric strips32, dielectric spacer layers26A, and phase change spacer layers14. In one embodiment, the dielectric filler strips34are of the same dielectric material as the second dielectric strips32, although other dielectric materials could also be employed.

Next, a series of third dielectric strips36is formed transversely on the dielectric filler strips34, second dielectric strips32, dielectric spacer layers26A, and phase change spacer layers14A, as shown inFIG. 7. In one embodiment, the third dielectric strips36are spaced apart from each other at a pitch that is twice the pitch at which the PCM storage elements18will be formed. The third dielectric strips36can be formed of the same second dielectric material as the second dielectric strips32, or a different dielectric material can be used. The third dielectric strips36can be formed by the same process as is used to form the first and second dielectric strips30,32, or other know techniques could be employed.

Next, as shown inFIG. 8, a series of heater spacer layers18A and second dielectric spacer layers28A are formed on opposite sidewalls of the third dielectric strips36. The heater spacer layers18A can be made of any resistive material, such as titanium silicon nitride. In one embodiment, the dielectric spacer layers26A are formed with a fourth dielectric material that is selectively etchable with respect to the third dielectric strips36and the underlying second dielectric strips32and first dielectric spacer layers26A. The fourth dielectric material can be the same as the first dielectric material, or different. The heater spacer layers18A and dielectric spacer layers28A can be formed using known spacer patterning techniques, such as those described above for the phase change spacer layers14A and dielectric spacer layers26A. The resulting structure includes first and second sandwich structures, each including heater spacer layers18A sandwiched by spacer layers28A, on opposite sides of the third dielectric strips36.

InFIG. 9, second dielectric filler strips38are formed between the structures formed by the third dielectric strips32, second dielectric spacer layers28A, and heater spacer layers18A. Like the first dielectric filler strips34, the second dielectric filler strips38can be formed by conformally depositing another dielectric layer and planarizing, such as by CMP, the dielectric layer until the dielectric filler strips38have the same height as the third dielectric strips36, dielectric spacer layers28A, and heater spacer layers18A. In one embodiment, the dielectric filler strips38are of the same dielectric material as the third dielectric strips36, although other dielectric materials could also be employed.

InFIG. 10, a self-aligned etch is performed using the second dielectric spacer layers28A and heater spacer layers18A as a mask. The self-aligned etch etches all of the way down to the first dielectric strips30, which segments the phase change spacer layers14A into the PCM storage elements14and segments the first dielectric spacer layers26A into the first dielectric spacers26.

InFIG. 11, third dielectric filler strips42are formed between the structures formed by the second dielectric spacer layers28A, heater spacer layers18A, PCM storage elements14, first dielectric spacers26, and remaining portions of the second dielectric strips32. Like the first and second dielectric filler strips34,38, the third dielectric filler strips42can be formed by conformally depositing another dielectric layer and planarizing, such as by CMP, the dielectric layer until the dielectric filler strips42have the same height as the dielectric spacer layers28A and heater spacer layers18A.

InFIG. 12, a strip-shaped mask (not shown) is used to etch the second dielectric spacer layers28A, heater spacer layers18A, and upper strips of the third dielectric filler strips42. That segments the heater spacer layers18A into the heaters18and segments the second dielectric spacer layers28A into the second dielectric spacers28.

FIG. 13shows the formation of top electrodes20on the heaters18and second dielectric spacers28. The top electrodes20can be formed after segmenting the heater spacer layers18A and second dielectric spacer layers28A into the heaters18and second dielectric spacers28, as shown inFIGS. 12-13. Alternatively, the top electrodes20can be formed first and then the heater spacer layers18A and second dielectric spacer layers28A can be segmented into the heaters18and second dielectric spacers28using the top electrodes as a mask. Similarly, the conductive lines22, such as bitlines or wordlines, can also be formed on the top electrodes20, either before or after forming the top electrodes20, heaters18, and second dielectric spacers28.

Turning toFIG. 14, a portion of a system500in accordance with an embodiment of the present invention is described. System500may be used in wireless devices such as, for example, a personal digital assistant (PDA), a laptop or portable computer with wireless capability, a web tablet, a wireless telephone, a pager, an instant messaging device, a digital music player, a digital camera, or other devices that may be adapted to transmit and/or receive information wirelessly. System500may be used in any of the following systems: a wireless local area network (WLAN) system, a wireless personal area network (WPAN) system, a cellular network, although the scope of the present invention is not limited in this respect.

System500may include a controller510, an input/output (I/O) device520(e.g., a keypad, display), static random access memory (SRAM)560, a memory530, and a wireless interface540coupled to each other via a bus550. A battery580may be used in some embodiments. It should be noted that the scope of the present invention is not limited to embodiments having any or all of these components.

Controller510may comprise, for example, one or more microprocessors, digital signal processors, microcontrollers, or the like. Memory530may be used to store messages transmitted to or by system500. Memory530may also optionally be used to store instructions that are executed by controller510during the operation of system500, and may be used to store user data. Memory530may be provided by one or more different types of memory. For example, memory530may comprise any type of random access memory, a volatile memory, a non-volatile memory such as a flash memory and/or a memory discussed herein.

I/O device520may be used by a user to generate a message. System500may use wireless interface540to transmit and receive messages to and from a wireless communication network with a radio frequency (RF) signal. Examples of wireless interface540may include an antenna or a wireless transceiver, although the scope of the present invention is not limited in this respect.