Nonvolatile memory device and method for fabricating the same

Provided are a nonvolatile memory device and a method for fabricating the same, which can secure the structural stability of a three-dimensional nonvolatile memory device. The nonvolatile memory device includes one or more columnar channel plugs, a plurality of word lines and a plurality of dielectric layers stacked alternately to surround the columnar channel plug, a memory layer disposed between the word line and the columnar channel plug, a plurality of word line connection portions, each of the word line connection portions connecting ends of word lines of a common layer from among the plurality of word lines, and a plurality of word line extension portions extending from the word line connection portions.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2010-0140510, filed on Dec. 31, 2010, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field of the Invention

Exemplary embodiments of the present invention relate to a semiconductor device and a method for fabricating the same, and more particularly, to a nonvolatile memory device and a method for fabricating the same.

2. Description of the Related Art

In order to use a word line as a metal in a three-dimensional flash device, after a channel plug is formed as in Terabit Cell Array Transistors (TCAT), a sacrificial layer is stripped and an oxide/nitride/oxide (ONO) layer and a metal are deposited thereon. Thereafter, a word line is formed through an isolation process.

FIG. 1Ais a perspective view of a conventional nonvolatile memory device.FIG. 1Bis a layout view ofFIG. 1A.

Referring toFIGS. 1A and 1B, a plurality of channel plugs11is formed on a substrate (not illustrated). Each of the channel plugs11pierces a word line12. A plurality of word lines12are stacked in a plurality of layers. Both ends of the word lines12are trimmed in a trimmed region13to have a stepwise configuration. The word lines12have a stepwise configuration in which the uppermost word line12is shortest and the lowermost word line12is longest. That is, the word lines12are stacked and form rows extending across a cell region100. However, once outside the cell region100, the word lines12are trimmed to form the stepwise configuration, and the ends of the word lines12are connected to word line contacts14.

Thus, the trimmed region13is a region in which the word line contacts14are connected. The trimmed region13generally has a width of approximately 500 nm.

The conventional technology ofFIGS. 1A and 1Balternately stacks dielectric layers and sacrificial layers several times, selectively removes the sacrificial layers, and forms the word lines12in the portions cleared of the sacrificial layers. For example, in a 128-giga class flash memory, dielectric layers and sacrificial layers are stacked in 16 layers. For example, the dielectric layers may be formed using oxide, and the sacrificial layers may be formed using nitride. In this structure, in the case of the lowermost word line12, an approximately 9000 nm (=16×500 nm) empty space from a trimming start region101to a trimming end region102must be supported by a dielectric layer (e.g., an oxide layer).

However, there is a high probability that the trimming region collapses due to a thermal stress in the sacrificial layer (nitride layer) stripping process and the subsequent ONO process. Consequently, the word lines12are not properly formed, thus making it difficult to form the device.

SUMMARY

Exemplary embodiments of the present invention are directed to a nonvolatile memory device and a method for fabricating the same, which can secure the structural stability of a three-dimensional nonvolatile memory device.

In accordance with an exemplary embodiment of the present invention, a nonvolatile memory device includes one or more columnar channel plugs, a plurality of word lines and a plurality of dielectric layers stacked alternately to surround the columnar channel plug, a memory layer disposed between the word line and the columnar channel plug, a plurality of word line connection portions, each of the word line connection portions connecting ends of word lines of a common layer from among the plurality of word lines, and a plurality of word line extension portions extending from the word line connection portions. The word line extension portions may be formed in a stepwise configuration. The word line extension portion may extend in one direction from an approximately center portion of a respective one of the word line connection portions. The word line extension portions may extend from both edges of the word line connection portions. The word line extension portion may extend in an oblique direction from one edge of the word line connection portions. The word line connection portions and the word line extension portions may include a first word line connection portion connecting the ends of some of the word lines, a plurality of first word line extension portions extending in an oblique direction from the first word line connection portion and having a stepwise configuration, a second word line connection portion connecting the ends of the other word lines, and a plurality of second word line extension portions extending in an oblique direction from the second word line connection portion and having a stepwise configuration.

In accordance with another exemplary embodiment of the present invention, a method for fabricating a nonvolatile memory device includes forming one or more channel plugs piercing an alternate stack body of a plurality of dielectric layers and a plurality of sacrificial layers, trimming one end of the alternate stack body to form a plurality of step structures, forming a first slit dividing the alternate stack body into memory string units and a second slit dividing the step structures, selectively removing the sacrificial layer to form undercuts, and forming word lines in the undercuts, word line connection portions to connect ends of the word lines, and one or more word line extension portions extending from the word line connection portion to form a stepwise configuration.

DETAILED DESCRIPTION

FIG. 2Ais a cross-sectional view of a nonvolatile memory device in accordance with a first exemplary embodiment of the present invention.FIG. 2Bis a layout view ofFIG. 2A.FIG. 2Cis a perspective view of a word line and a word line extension portion.FIG. 2Dis a perspective view of a trimming region including the word line extension portion.

Referring toFIGS. 2A to 2D, a plurality of columnar channel plugs24are formed on a substrate21. A plurality of word lines28A surrounding the channel plugs24are formed in a plurality of layers that are stacked in a vertical direction, and a memory layer27is formed between the word lines28A and the channel plugs24. A word line connection portion28B is formed to connect the ends of the word lines28A formed in the same layer. A plurality of word line extension portions28C are formed to extend in one direction from the word line connection portions28B. The word line extension portions28C are provided in each layer of the word lines28A. The word line extension portions28C have variable lengths, which increase from an upper layer to the lower layer to provide a stepwise configuration. Also, as shown inFIG. 2C, more than one word line extension portions28C may be formed in the same layer. For isolation between the word lines28A formed in the vertical direction, a plurality of dielectric layers22A are formed to surround the channel plugs24. The word lines28A fill undercuts between the dielectric layers22A. A plurality of support layers23B are formed between the dielectric layers to contact the word line extension portions28C. The word lines28A, the word line connection portions28B, and the word line extension portions28C are formed of the same conductive layer to form one congruent body. Herein, the conductive layer may include a metal. The word lines28A formed in the same layer are isolated by a slit302. The dielectric layer22A may be formed of an oxide layer, and the support layer23B may be formed of a nitride layer.

Word line contacts305are disposed on the word line extension portions28C of each layer. The word line contacts305pierce the dielectric layers22A to connect to the respective word line extension portions28C.

Referring toFIGS. 2A to 2D, a plurality of word lines28A extending in a row direction are arranged in a column direction at predetermined intervals. Layers of the word lines28A are stacked sequentially from the lowermost layer. The word lines28A of one layer are connected by the respective word line connection portions28B. The length of the word line extension portions28C decreases from the lowermost layer to the uppermost layer. That is, the ends of the word line extension portions28C are trimmed to provide a stepwise configuration.

According to the first exemplary embodiment of the present invention, in the forming of the word lines28A, the word lines28A are completely isolated in a cell region200and a select transistor channel hole region201having a channel hole of a select transistor, and it is isolated from the word lines28A of the cell region200in a trimming region202. The word lines28A formed in the trimming region202become the word line extension portions28C extending from the word line connection portions28B connecting the ends of the word lines28A arranged in the column direction. Accordingly, the number of the word line extension portions28C formed in the trimming region202may be smaller than the number of the word lines in the cell region200. Herein, the word line extension portions28C formed in the trimming region202serve as a connection line that connects a metal interconnection and the word lines28A of the cell region200. In the conventional art, a pattern collapse may occur in the trimming region after the stripping of the sacrificial layer. If the present invention uses a replacement process as in TCAT (Terabit Cell Array Transistors), the lines of two regions have a layout to overlap nitride layers stripped on a replacement pattern for forming a word line in order to electrically connect the word lines28A of the cell region200and the word line extension portions28C formed in the trimming region202.

Consequently, according to the first exemplary embodiment of the present invention, it is possible to strip the nitride layer of the trimming region202, which is vulnerable to collapse, only as much as is needed, after the stripping of the sacrificial layer. Accordingly, because the remaining nitride layer is used as the support layer23B, a pattern collapse is less likely to occur.

Also, in the case of the first exemplary embodiment of the present invention, because it is possible to increase the width of the word line extension portions28C more than the interval between the word lines28A formed in the cell region200, it is also advantageous in terms of the pattern alignment with the word line contacts305.

Due to the characteristics of a replacement process, the word line extension portions28C formed in the trimming region202may have two lines for one connection slit and the number of lines may increase to avoid a pattern collapse.

FIGS. 3A to 3Gare cross-sectional views illustrating a method for fabricating a nonvolatile memory device in accordance with the first exemplary embodiment of the present invention.FIG. 4Ais a layout view of forming a connection slit.FIG. 4Bis a layout view of forming a word line and a word line extension portion.FIG. 4Cis a layout view of forming a word line contact.FIGS. 5A and 5Bare a cross-sectional view and a perspective view, respectively, showing a method of forming an undercut.FIGS. 6A and 6Bare a cross-sectional view and a perspective view, respectively, showing a method of forming a word line extension portion.FIG. 6Cis a perspective view of forming a word line contact.FIGS. 5A and 5BandFIGS. 6A to 6Care detailed views of a portion A ofFIG. 4A.

Referring toFIG. 3A, dielectric layers22and sacrificial layers23are alternately stacked to form a stack body300on a substrate21. The sacrificial layers23may include a nitride layer such as a silicon nitride layer. The uppermost layer and the lowermost layer of the stack body300are formed of the dielectric layers22. The dielectric layers22are used as a dielectric layer between the word lines, and may comprise an oxide layer such as a silicon oxide layer. The sacrificial layers23and the dielectric layers22are formed alternately according to the number of memory cells to be stacked. For the convenience of description, the first exemplary embodiment of the present invention illustrates a case where four memory cells are stacked in one memory string.

Referring toFIG. 3B, through a trimming etch process, one end of the stack body300is formed in a stepwise configuration. Herein, one end of the stack body300is a trimming region, that is, a region except a cell region and a select transistor region. A word line contact is formed in the trimming region. The trimming region has a trimming start region and a trimming end region. The trimming etch process may be performed before a slit etching process.

The stack body300is etched to form a plurality of channel holes301exposing the surface of the substrate21. That is, the channel holes301are formed by performing an etching process that perforates the stack body300to expose the substrate21. As a result of forming the channel holes301in the stack body300, dielectric patterns22A and sacrificial patterns23A are formed.

Referring toFIG. 3C, channel plugs24and gap-fill layers25are formed in the channel holes301. A first conductive layer serving as the channel plugs24is formed on the entire surface of the stack body300including the channel holes301, and the resulting structure is planarized through, for example, a chemical mechanical polishing (CMP) process. The first conductive layer includes a polysilicon layer (e.g., an undoped polysilicon layer). If the first conductive layer does not fill each of the channel holes301, the gap-fill layer25may be formed. Thus, the gap-fill layer25is also planarized in the CMP process and is left only in the channel holes301.

Due to the planarization process, a columnar channel plug24is formed in each of the channel holes301.

Referring toFIG. 3D, a slit etching process is performed to form a word line isolation slit302. The word line isolation slit302serves to divide the stack body300and the channel plugs24into memory string units. The bottom of the word line isolation slit302reaches the dielectric pattern22A of the lowermost layer.

The slit etching process for forming the word line isolation slit302may be stopped after etching through the sacrificial pattern23A of the lowermost layer formed of a nitride layer. Accordingly, damage to the substrate21is prevented.

While forming the word line isolation slit302, an etching process for forming a connection line may be performed simultaneously. Accordingly, a connection slit303is formed in a trimming region, that is, a region except the cell region and the select transistor region (refer toFIG. 4A).

The word line isolation slit302and the connection slit303are line-type trench patterns as shown in the plan view ofFIG. 4A.

The start point and the end point of the word line isolation slit302are formed at points between the edge of a select transistor region401and a trimming start region402(i.e., a region including the uppermost word line contact). That is, the ends of the word line isolation slits302are between the edge of the select transistor region401and the trimming start region402.

The connection slit303is formed to extend from a trimming end region403(i.e., a region including the lowermost word line contact) to a point between the edge of the select transistor region401and the trimming start region402(i.e., a region including the uppermost word line contact). The connection slit303has two ends. One end of the connection slit303defines the trimming end region403, and the other end of the connection slit303extends to a point between the edge of the select transistor region401and the trimming start region402.

The word line isolation slit302and the connection slit303extend in the same direction. The word line isolation slit302may be longer than the connection slit303. The width of the word line isolation slit302may be equal to or smaller than the width of the connection slit303.

Referring toFIG. 3E, the sacrificial patterns23A are selectively removed. As a result of the removal of the sacrificial patterns23A, first undercuts26are formed between the dielectric patterns22A. If the sacrificial patterns23A are formed of a nitride layer, a wet etching process may be performed. In particular, a wet etching process using phosphoric acid may be performed. When removing the sacrificial patterns23A, all of the sacrificial patterns23A around the channel plug24are removed, while the removing width of the sacrificial pattern is controlled in the connection slit303. Accordingly, in the trimming region, a pattern collapse can be prevented because the sacrificial pattern23B is left. Hereinafter, the undercuts formed in the trimming region will be referred to as second undercuts26(refer toFIGS. 5A and 5B).

Referring toFIG. 3F, a memory layer27is formed on the entire surface including the first and second undercuts26. The memory layer27includes a blocking layer, a charge trapping layer, and a tunnel insulating layer. That is, a blocking layer, a charge trapping layer, and a tunnel insulating layer are sequentially stacked. The blocking layer functions to prevent an electric charge from passing through the charge trapping layer and moving toward a gate electrode. The blocking layer may include an oxide layer that is formed through a thermal oxidation process or a deposition process. The blocking layer may be formed using a material with a high dielectric constant. The charge trapping layer is used as a data storage. The charge trapping layer comprises a charge trapping layer that traps an electric charge at a deep-level trap site. The charge trapping layer may include a nitride layer. Alternatively, the charge trapping layer may be formed using a polysilicon layer. The tunnel insulating layer may include an oxide layer that is formed through a terminal oxidation process or a deposition process. The memory layer27includes an ONO structure.

A second conductive layer28is formed on the memory layer27. The second conductive Layer28includes a silicon layer. The second conductive layer28may be formed of a polysilicon layer or a metal layer. The second conductive layer28is used as a word line (or a control gate electrode) of a memory cell.

Referring toFIG. 3G, the second conductive layer28is selectively isolated to form word lines28A. The word lines28A fill the first and second undercuts26and surround the channel plug24. Consequently, the channel plug24has the shape of a pillar piercing the word lines28A, and the memory layer27is formed between the channel plug24and the word lines28A. An etch-back process is performed to form the word lines28A. The use of an etch-back process allows the word lines28A to be separated. The process of forming the word lines28A in the undercuts is called a replacement process.

When the word lines28A are formed, dielectric patterns22A and word lines28A are stacked alternately in the vertical direction. Accordingly, a memory string, having memory cells connected in series in the vertical direction, is formed.

A plurality of word line extension portions28C are formed in a connection slit303(refer toFIGS. 4B,6A and6B). The word line extension portions28C extend in one direction (e.g., in a perpendicular direction) from the word line connection portions28B, which connect the ends of the word lines28A in a common layer. Accordingly, the number of word line extension portions28C corresponds to the number of layers of stacked word lines28A. The word line extension portions28C are also stacked in the vertical direction like the word lines28A. In addition, the word line extension portions28C form a stepwise structure in which the length of the word line extension portions28C decreases from a lowermost word line extension portion to an uppermost word line extension portion. That is, a step portion ST is provided such that the positions of the ends of the word line extension portions28C in the trimming region202are different from each other.

The width of the word line extension portion28C may be larger than the interval between the word lines28A formed in the cell region.

Due to the characteristics of the replacement process, the word line extension portions28C formed in the trimming region202have two connection lines extending from each of the word line connection portions28B. Further, the number of lines may increase to prevent patterns from collapsing.

A mask process and an etching process are performed to isolate a select transistor gate line. The contact hole formed on a select transistor is formed at the end of the select transistor gate line.

Subsequently, an integration process is performed. For example, a plurality of word line contacts305are formed (refer toFIGS. 4C and 6C).

The present invention is also applicable to a structure in which dielectric layers and word lines are stacked alternately in a vertical direction.

FIG. 7Ais a cross-sectional view of a nonvolatile memory device in accordance with a second exemplary embodiment of the present invention.FIG. 7Bis a layout view ofFIG. 7A.FIG. 7Cis a perspective view of a word line and a connection line in accordance with the second exemplary embodiment of the present invention.FIG. 7Dis a layout view of forming a connection slit in accordance with the second exemplary embodiment of the present invention.

Referring toFIGS. 7A to 7D, a pair of channel plugs500extend in a vertical direction with respect to a substrate31. A pipe channel501connects the bottom portions of the channel plugs500. A pipe gate33surrounds the bottom portions of the channel plugs500. Word lines508surround the channel plugs500. Word lines508surrounding different channel plugs500are isolated by a slit509.

The substrate31may include a silicon substrate. A first dielectric layer32is formed between the substrate31and the pipe gate33, and a second dielectric layer34is formed over the pipe gate33. The pipe gate33has a pipe channel hole35. A pipe gate insulating layer36is formed between the pipe gate33and the pipe channel501.

The channel plug500and the pipe channel501are formed of the same material. For example, the channel plug500and the pipe channel501may include a polysilicon layer, and in particular, may be formed of an undoped polysilicon layer. The channel plug500and the pipe channel501together have a U-shaped structure.

The channel plug500is surrounded by word lines508and third dielectric layers37that are stacked alternately. The sidewalls of the channel plug500are surrounded by a memory layer38. The memory layer38includes a blocking layer, a charge trapping layer, and a tunnel insulating layer. The word line508is buried in an undercut39between the third dielectric layers37, which are stacked in the vertical direction.

Two memory strings are formed by a slit509. A pipe channel transistor (PCTR) is formed by the pipe gate33and the pipe channel501. The two memory strings are connected to the pipe channel transistor (PCTR). Consequently, the two memory strings constitute memory cell strings that are connected in series through the pipe channel transistor (PCTR). For example, where four memory cells are formed in each memory string, one memory cell string includes eight memory cells.

Referring toFIGS. 7B and 7C, columnar channel plugs500are formed on the substrate. A first word line connection portion504C is formed to connect the ends of some of the word lines508. A plurality of first word line extension portions504A, having a stepwise configuration, are formed to extend from the first word line connection portion504C. A second word line connection portion504D is formed to connect the ends of the other word lines508. A plurality of second word line extension portions504B, having a stepwise configuration, are formed to extend from the second word line connection portion504D. A plurality of support layers (not illustrated) are formed between dielectric layers to contact the first and second word line extension portions504A and504B. The first word line extension portions504A and the second word line extension portions504B are formed in the undercuts through the connection slit510illustrated inFIG. 7D.

A plurality of word line contacts507are disposed on the first and second word line extension portions504A and504B.

FIG. 7Eis a cross-sectional view of a nonvolatile memory device in accordance with a modification of a second exemplary embodiment of the present invention.

Referring toFIG. 7E, unlike the structure ofFIG. 7Ain which the word lines508are buried in the undercut between the third dielectric layers37, a cell channel hole is formed to isolate the word lines508, and a channel plug500and a memory layer38are formed in the cell channel hole. That is, conductive layers (e.g., polysilicon layers) used as the word lines508are stacked, and the stack structure is etched to form a cell channel hole. A memory layer38and a channel plug500are formed in the cell channel hole, and a slit509is formed to isolate the word lines508.

Also, like the resulting structure ofFIG. 7Eillustrating a modification of the second exemplary embodiment, the present invention may stack second dielectric layers37and sacrificial layers (not illustrated) alternately with a memory layer38and a channel plug500disposed therebetween, and may form word lines508in the space cleared of the sacrificial layers.

The layout of a modification of the second exemplary embodiment illustrated inFIG. 7Eis substantially identical to the layout illustrated inFIG. 7B.

FIGS. 8A and 8Bare layout views of a nonvolatile memory device in accordance with a third exemplary embodiment of the present invention.FIG. 8Cis a layout view of a word line contact in accordance with a third exemplary embodiment of the present invention.

Referring toFIGS. 8A and 8B, a plurality of word lines603surrounding a plurality of channel plugs600are formed. The plurality of word lines603extending in the row direction are isolated by a slit601and are arranged in the column direction at certain intervals. Layers of the word lines603are stacked sequentially from the lowermost layer. The word lines603of one layer are connected by word line connection portions604A and604B of a corresponding layer. Word line extension portions605A and605B extend from both edges of the word line connection portions604A and604B. The word line extension portions605A and605B are formed in undercuts through a connection slit602. The row-direction length of the word line extension portions605A and605B decreases toward the uppermost layer. That is, the ends of the row-direction layers are trimmed to provide a stepwise configuration. Referring toFIG. 8C, a plurality of word line contacts606are disposed at the word line extension portions605A and605B. A reference numeral ‘607’ denotes a metal interconnection.

FIGS. 9A and 9Bare layout views of a nonvolatile memory device in accordance with a fourth exemplary embodiment of the present invention.FIG. 9Cis a layout view of a word line contact in accordance with the fourth exemplary embodiment of the present invention.

Referring toFIGS. 9A and 9B, a plurality of word lines703surrounding channel plugs700are formed. The plurality of word lines703extending in the row direction are isolated by a slit701and are arranged in the column direction at certain intervals. Layers of the word lines703are stacked sequentially from the lowermost layer. The word lines703of one layer are connected by word line connection portions704A and704B of a corresponding layer. Word line extension portions705A and705B extend from one edge of the word line connection portions704A and704B in an oblique direction. The word line extension portions705A and705B are formed in undercuts through a connection slit702. The row-direction length of the word line extension portions705A and705B decreases toward the uppermost layer. That is, the ends of the row-direction layers are trimmed to provide a stepwise configuration. Referring toFIG. 9C, a plurality of word line contacts706are disposed on the word line extension portions705A and705B. A reference numeral ‘707’ denotes a metal interconnection.

FIGS. 10A and 10Bare layout views of a nonvolatile memory device in accordance with a fifth exemplary embodiment of the present invention.FIGS. 10C and 10Dare layout views of a word line contact in accordance with the fifth exemplary embodiment of the present invention.

Referring toFIGS. 10A and 10B, a plurality of word lines802surrounding channel plugs800are formed. A plurality of word lines802extending in the row direction are isolated by a slit801and are arranged in the column direction at certain intervals. Layers of the word lines802are stacked sequentially from the lowermost layer. The word lines802of one layer are connected by a word line connection portion803of a corresponding layer. The row-direction length of one end of the word line connection portion803decreases toward the uppermost layer. That is, the ends of the row-direction layers are trimmed to provide a stepwise configuration. Referring toFIG. 10C, a plurality of word line contacts804are disposed at one end of the word line connection portion803. A reference numeral ‘805’ denotes a metal interconnection.

The word line contact of the fifth embodiment may also have a layout illustrated inFIG. 10D.

FIGS. 11A and 11Bare layout views of a nonvolatile memory device in accordance with a sixth exemplary embodiment of the present invention.FIG. 11Cis a layout view of a word line contact in accordance with the sixth exemplary embodiment of the present invention.

Referring toFIGS. 11A and 11B, a plurality of word lines903surrounding channel plugs900are formed. A plurality of word lines903extending in the row direction are isolated by a slit901and are arranged in the column direction at certain intervals. A first word line connection portion904A is formed to connect the ends of some of the word lines903, and a first word line extension portion905A is formed to extend in an oblique direction from the first word line connection portion904A and have a stepwise configuration. A second word line connection portion904B is formed to connect the ends of the other word lines903, and a second word line extension portion905B is formed to extend in an oblique direction from the second word line connection portion904B and have a stepwise configuration. The word line extension portions905A and905B are formed in undercuts through a connection slit902. A plurality of support layers (not illustrated) are formed between dielectric layers to contact the first and second word line extension portions905A and905B. Referring toFIG. 11C, a plurality of word line contacts906are disposed at the first and second word line extension portions905A and905B. A reference numeral ‘907’ denotes a metal interconnection.

As described above, the present invention can strip the sacrificial layer of the trimming region, which is vulnerable to collapse, only as much as is needed, thus making it possible to improve the structural stability of a three-dimensional nonvolatile memory device.

Also, the present invention can increase the width of the connection line more than the spacing distance between the word lines formed in the cell region, thus making it possible to provide an advantage in terms of the pattern alignment with the word line contact and to improve the mass productivity.