Memory circuit and a tracking circuit thereof

Memory circuit and a tracking circuit thereof. The tracking circuit includes a dummy bit line (DBL). The tracking circuit further includes a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal. The wordline activation signal causes activation of a memory cell. The tracking circuit also includes a second circuit which is responsive to discharge of the dummy bit line to enable access to the memory cell.

TECHNICAL FIELD

Embodiments of the disclosure relate to a memory circuit and a tracking circuit thereof.

BACKGROUND

A clock signal may reach different parts of a memory circuit through different paths and hence at different times. Process variations and variations in associated voltage supply can add to these time differences. Such time differences can cause incorrect read or write operations. Tracking circuits have been used to compensate for these time differences. However, the tracking circuits operate on a worst-case basis and hence the tracking circuits degrade performance of the memory circuit. In a retention-till-access (RTA) memory, an RTA mode of operation accounts for worst-case timing differences. The tracking circuit operates on the worst-case basis even when the memory circuit is not being operated in the RTA mode. Hence, there is a need for a way to compensate for the timing differences in the memory circuit, in one or more modes of operation, with minimal performance degradation.

SUMMARY

An example of a tracking circuit includes a dummy bit line (DBL). The tracking circuit further includes a first circuit to discharge the dummy bit line in response to a first signal and a wordline activation signal. The wordline activation signal causes activation of a memory cell. The tracking circuit also includes a second circuit which is responsive to discharge of the dummy bit line to enable access to the memory cell.

An example of a memory circuit includes a clock circuit to generate a first clock signal and a second clock signal. The memory circuit also includes a retention-till-access switch responsive to the second clock signal to generate a first signal and a wordline header signal. Further, the memory circuit includes a wordline driver responsive to the first clock signal and to the wordline header signal to drive a wordline to render a memory cell to be ready for access. The memory circuit also includes a first circuit responsive to the second clock signal and to the wordline header signal to track a wordline path from the clock circuit to the wordline and to generate a wordline activation signal. The memory circuit further includes a dummy bit line responsive to a logical combination of the first signal and the wordline activation signal to discharge through the first circuit. Moreover, the memory circuit includes a second circuit responsive to discharge of the dummy bit line to generate a second signal based on peripheral voltage supply variations. The memory circuit also includes a pulse generator responsive to the second signal to generate an enable signal. Furthermore, the memory circuit includes a sense amplifier responsive to the enable signal to access the memory cell.

An example of a method includes generating a wordline activation signal in response to activation of a wordline. The method also includes discharging a dummy bit line based on a logical combination of a first signal and the wordline activation signal. The method further includes enabling access to a memory cell in response to the discharging. The memory cell is coupled to the wordline.

DETAILED DESCRIPTION OF THE EMBODIMENTS

FIG. 1illustrates a memory circuit100. The memory circuit100can be a retention-till-access (RTA) type of memory. An RTA memory is a memory that employs a technique of reducing power leakage in memory cells by automatically lowering the power being supplied to the memory cells when the memory cells are not being accessed. This is done by reducing voltage. Even though the voltage is lowered, data in the memory cells is maintained. The RTA memory has two modes of operation, an RTA mode and a non-RTA mode. In the non-RTA mode, voltages are maintained at the same level whether or not the memory cells are being accessed.

This disclosure describes embodiments that use the RTA type of memory, but the principles of the invention are applicable to non-RTA memories also.

The memory circuit100can be included in a static random access memory (SRAM) along with other control circuitry for the SRAM. The memory circuit100can also be included in a microprocessor memory cache such as a small and fast Level One (L1) cache or a larger but slower Level Two (L2) cache.

The memory circuit100receives power from each of two power supplies. One supply is an array power supply that provides power at an array voltage (VDDAR) and the other supply is a peripheral power supply that provides power at a peripheral voltage (VDDPR). VDDPRis subject to more variation than VDDAR. The power supplies provide power to, respectively, an array header (not shown) and a peripheral circuitry140.

The memory circuit100includes a clock circuit105that is coupled to an RTA switch165and a plurality of wordline drivers, for example a wordline driver120A1to a wordline driver120AM. The RTA switch165is coupled to a plurality of memory arrays, for example a memory array130A1to a memory array130AM. The memory arrays are coupled to the peripheral circuitry140and a sense amplifier circuit150. Each wordline driver is also coupled to a respective memory array through a respective wordline. For example, the wordline driver120A1is coupled to the memory array130A1through a wordline125A1.

The RTA switch165is also coupled to a tracking circuit170. The tracking circuit170is coupled to a pulse generator190. The pulse generator190is coupled to the clock circuit105and the sense amplifier circuit150.

The clock circuit105includes a clock generator110coupled to a predecoder clock circuit115. Two inverters, for example an inverter195and an inverter196are also coupled in series connection between the clock generator110and the RTA switch165. The predecoder clock circuit115is coupled to the wordline drivers. The clock generator110is also coupled to the pulse generator190.

The RTA switch165receives VDDARand is also coupled to the wordline drivers.

The tracking circuit170includes a first circuit175which is coupled to a second circuit185through a dummy bit line180. The first circuit170is coupled to the RTA switch165, to the wordlines, and to the inverter196. The second circuit185receives VDDPRand is coupled to the pulse generator190.

The peripheral circuitry140receives VDDPRand is coupled to the memory arrays. Each memory array includes a plurality of memory cells (also referred to as bit cells). For example, the memory array130A1includes a memory cell135A1to135AN. The memory arrays include the memory cells that are arranged in one or more rows and columns. The memory circuit100can include M rows of memory cells. In one example, M can be 16 or 32. 16 memory rows can be grouped into a block. There can be several blocks present in the memory circuit100. One wordline is present corresponding to one row. Each memory cell can have one or more transistors. In one embodiment, the tracking circuit170can be present for 32 memory rows.

The sense amplifier circuit150includes a plurality of sense amplifiers, for example a sense amplifier160A1to a sense amplifier160AN, and a plurality of multiplexers, for example a multiplexer155A1to a multiplexer155AN. Each memory cell is coupled to a sense amplifier through a multiplexer. For example, the memory cell135A1is coupled to the sense amplifier160A1through the multiplexer155A1. The memory cell135A1is coupled to the multiplexer155A1through a pair of bit lines (BL1and BLB1). Each sense amplifier defines a corresponding global bit line (GBL). For example, the sense amplifier160A1defines a GBL1.

An exemplary operation of the memory circuit100is now explained. The memory circuit100has two active paths. An active path is defined as flow of current or signal. One path includes flow of signal from the clock circuit105to the memory array130A1through the wordline driver120A1and the wordline125A1. Another path includes flow of signal from the clock circuit105to the memory array130A1through the tracking circuit170, the pulse generator190and the sense amplifier circuit150. The operation of the memory circuit100is explained using the wordline driver120A1, the wordline125A1, and the memory array130A1as an example.

In illustrated example, the memory cell135A1of the memory array130A1needs to be accessed for a read operation. It is noted that the operation of the memory circuit100is explained using the read operation but is applicable to a write operation also. Performing the read operation or the write operation on the memory cell135A1is referred to as accessing the memory cell135A1.

An external clock signal (CLK) enables the clock generator110to initiate a read operation. The clock generator110generates an internal clock signal (ICLK). ICLK is also referred to as the clock signal. Initially, for the first time the ICLK is generated in response to the external clock signal and is subsequently generated based on a RESET signal (second signal). The predecoder clock circuit115generates a plurality of predecoder clock signals in response to the ICLK. The predecoder clock signals drive the wordline driver120A1. The wordline driver120A1in turn drives the wordline125A1. Driving of the wordline125A1indicates activation of the wordline125A1.

The wordline125A1in the memory circuit100can become active due to the predecoder clock signals or due to charging of the array header of the memory circuit100. The RTA switch165controls charging of the array header and causes a voltage of the array header to settle at a predefined voltage in the RTA mode. Initially, when the memory cells are not accessed, the voltage of the array header is at a diode supply which is equal to VDDAR−VT, where VTis a diode drop across a positive metal oxide semiconductor (PMOS) based diode (not shown) of the RTA switch165. A signal indicative of the voltage of the array header is referred to as ARHDR (first signal). The array header of the memory circuit100is charged using a PMOS transistor switch (not shown) of the RTA165. A gate of the PMOS transistor switch is driven by a signal at a logic level, for example a logic level HIGH or a logic level LOW. When the memory cells are to be accessed, the logic level at the gate of the PMOS transistor is at logic level LOW resulting in precharging of the array header to VDDAR. The PMOS transistor switch can be driven by a component of the ICLK which can be obtained by delaying the ICLK using the two inverters.

The RTA switch165also precharges a wordline header (not shown), in response to the component of the ICLK, to generate a wordline header signal (WLHDR). The precharging of wordline header is performed in a method similar to the precharging of the array header. A signal indicative of the voltage of the wordline header is referred to as the WLHDR. ARHDR is different than the WLHDR. The RTA switch165generates the ARHDR before the WLHDR to prevent reduction of noise margin of the memory cells.

The wordline driver120A1drives the wordline125A1in response to the predecoder clock signals and the WLHDR. The WLHDR is a supply to the wordline driver120A1. The wordline125A1is driven HIGH and a desired memory cell, for example the memory cell135A1, coupled to the wordline125A1and the pair of bit lines, is then ready for access. The driving of the wordline125A1renders the memory cell135A1to be ready to be accessed. The memory cell135A1also requires inputs in terms of power supply through the peripheral circuitry140. Hence, access to the memory cell135A1is also dependent on VDDPR. Data in the memory cell135A1is reflected onto the pair of bit lines, the BL1and the BLB1. If the data stored in the memory cell135A1is at logic LOW, then the BL1is discharged from a precharged logic HIGH state to a logic LOW state. If the data stored in the memory cell135A1is at logic HIGH, then BLB1is discharged from a precharged logic HIGH state to a logic LOW state. The discharging develops a differential voltage between the BL1and the BLB1.

The sense amplifier160A1senses the differential voltage, using the MUX155A1, in response to an enable signal also referred to as a sense amplifier enable signal (ENSA). Hence, it is desired that the ENSA is generated at the correct time to sense the differential voltage. The correct time can be defined as a time at which the differential voltage develops between the pair of bit lines. The differential voltage is amplified by the sense amplifier160A1and transferred onto the GBL1.

The ENSA is generated at the correct time by the pulse generator190based on tracking by the tracking circuit170.

The tracking circuit170tracks a wordline path using the dummy bit line180. The wordline path can be defined as a path from the clock circuit105to the wordline125A1. In other aspect, the wordline path can be defined as the path from the clock generator110to the predecoder clock circuit145then to the wordline driver120A1then to the wordline125A1. The tracking circuit170tracks the wordline125A1by generating the wordline driver signal in response to the wordline125A1going HIGH. When the wordline125A1is activated the first circuit175discharges the dummy bit line180using the first signal (ARHDR) and the wordline activation signal. The discharge of the dummy bit line180is indicative of the wordline125A1being driven HIGH. The tracking circuit170by tracking enables timely triggering of the sense amplifier160A1.

The second circuit185generates the RESET signal (second signal) based on discharge of the dummy bit line180. The second circuit185tracks discharging of the dummy bit line180across peripheral voltage supply variations to generate the RESET signal to enable generation of the enable signal and hence, to enable accessing of the memory cell135A1. The RESET signal is also sent to the clock generator110to reset the ICLK and to reset the clock generator110for another read operation. The tracking circuit170also tracks a path from the RTA switch155to the wordline driver120A1and to the memory cells. The tracking enables triggering of the sense amplifier circuit150to read the memory cells correctly. The pulse generator190receives the RESET signal and is responsive to the RESET signal to generate the enable signal (ENSA). The sense amplifier160A1then receives the ENSA and is responsive to the ENSA to sense the differential voltage.

The tracking circuit170enables timely triggering of the sense amplifier160A1in order to read the data accurately. Inaccurate reading of the data occurs if the differential voltage detected is below a certain threshold voltage. The tracking circuit170delays enabling of the sense amplifier160A1in order to allow accurate reading of the data by developing sufficient differential voltage across the pair of bit lines. In order to time the triggering of the sense amplifier160A1, the tracking circuit170detects when the wordline125A1and the pair of bit lines are selected. The dummy bit line180which is precharged prior to start of the read operation starts discharging once the wordline125A1and the pair of bit lines is selected. The second circuit185detects if a voltage on the dummy bit line180falls below a certain level. When the voltage on the dummy bit line180falls below a certain level, the second circuit185resets the pulse generator190to generate the ENSA. The MUX155A1is used to select BL1and BLB1. The sense amplifier160A1detects the differential voltage across BL1and BLB1, and amplifies the differential voltage. The differential voltage can also be referred to as a read margin. Amplified differential voltage is further outputted on the GBL1.

Referring toFIG. 2now, the RTA switch165is explained. The RTA switch165includes a PMOS transistor210, a PMOS transistor based diode215, and a PMOS transistor225. Sources of the PMOS transistor210and the PMOS transistor based diode215are coupled to the array power supply. Drains of the PMOS transistor210and the PMOS transistor based diode215are coupled to an array header205. A source of the PMOS transistor225is also coupled to the array header205. A drain of the PMOS transistor225is coupled to a wordline header220. ARHDR is different than the WLHDR due to difference in load due to the array header205and the wordline header220.

Referring toFIG. 3now, a section300of the memory circuit100is provided. The section300includes the clock generator110, the predecoder clock circuit115, the wordline driver120A1, the wordline125A1, the memory cell135A1, the peripheral circuitry140, the tracking circuit170, and the RTA switch165.

The clock generator110includes a delay circuit305, a positive metal oxide semiconductor (PMOS) transistor310, a negative metal oxide semiconductor (NMOS) transistor315A, and an NMOS transistor315B. The delay circuit305receives the external clock signal (CLK) and has an output terminal coupled to a gate of the transistor315B. The transistor310has a source coupled to the array power supply, and a gate that receives the reset signal (RESET). The NMOS transistor315A has a drain coupled to a drain of the PMOS transistor310and a source coupled to a drain of the NMOS transistor315B. The NMOS transistor315B has a source coupled to a ground supply (VSS).

The delay circuit305may have an architecture equivalent to existing delay circuits and can include various components, for example inverters.

The predecoder clock circuit115includes a NOR gate320and an inverter325. The NOR gate320has two input terminals. One input terminal is configured to receive a plurality of address lines and other input terminal is coupled to drains of the PMOS transistor310and the NMOS transistor315A to receive the clock signal. An output terminal of the NOR gate320is coupled to an input terminal of the inverter325. An output terminal of the inverter325is coupled to the wordline driver120A1. The wordline driver120A1is coupled to the wordline125A1which in turn is coupled to the memory cell135A1.

In one example, there are 16 wordlines (not shown but indicated by arrows399). The wordlines are in turn coupled to respective memory cells. There are also16wordline drivers present (not shown but indicated by arrows399). Each word line driver includes a NOR gate having an output terminal coupled to an inverter which in turn has an output terminal coupled to another inverter. For example, the wordline driver120A1includes a NOR gate340having the output terminal coupled to an inverter345which in turn has the output terminal coupled to an inverter350. The inverter345and the inverter350are supplied with the WLHDR.

For 32 wordlines, two blocks can be present. Each block can include 16 wordlines and corresponding memory cells.

To track the wordline path from the clock generator110to the wordlines, it is desired to have a replica path similar to that of the wordline path. The replica path includes an inverter195having input terminal coupled to the drains of the PMOS transistor310and the NMOS transistor315A. The inverter196is coupled to output terminal of the inverter195. The inverter195delays the clock signal by a delay equivalent to that generated by the NOR gate320. The inverter196also generates a delay similar to that by the inverter325. The inverter195and the inverter196receive the VDDPR.

The tracking circuit170includes the second circuit185, a circuit358(third circuit), the dummy bit line180, and a pair of NMOS transistors, for example an NMOS transistor375and an NMOS transistor370. In some embodiments, the tracking circuit170can also include an NMOS transistor367. The circuit358and the pair of NMOS transistors form the first circuit175. The circuit358includes a circuit365(fourth circuit).

The tracking circuit170also includes one NMOS transistor for one wordline. Hence, the tracking circuit170includes 32 NMOS transistors for 32 wordlines. Gates of each of such NMOS transistors are coupled to a corresponding wordline. For example, an NMOS transistor356(first NMOS transistor) having a gate coupled to the wordline125A1. The tracking circuit170further includes electrical lines, for example an electrical line357for 16 wordlines. The electrical line357is coupled to drains of 16 NMOS transistors.

A circuit360(fifth circuit) is similar to the wordline drivers, for example, the wordline driver120A1. The circuit360includes a NOR gate361. The circuit360also includes an inverter362having an input terminal coupled to an output terminal of the NOR gate361. Further, the circuit360includes an inverter363having an input terminal coupled to an output terminal of the inverter362and having an output terminal coupled to a circuit365(fourth circuit). The NOR gate361is similar to the NOR gate340, the inverter362is similar to the inverter345, and the inverter363is similar to the inverter350.

The circuit365includes two pairs of cross-coupled PMOS transistors. A first pair includes a PMOS transistor364A (first PMOS transistor) and a PMOS transistor364B (second PMOS transistor). The PMOS transistor364A has a source coupled to the RTA switch165to receive the WLHDR, has a gate coupled to the output terminal of the inverter363, and has a drain coupled to the electrical line357and an input terminal of a NAND gate366. The PMOS transistor364B has a source coupled to the RTA switch165to receive the WLHDR, has a gate coupled to the drain of the PMOS transistor364A, to the electrical line357and to the input terminal of the NAND gate366, and has a drain coupled to another input terminal of the NAND gate366and to an additional electrical line367. The drain of the PMOS transistor364A defines output of the first pair. Similarly, another pair of PMOS transistors includes a PMOS transistor364C (first transistor) and a PMOS transistor364D (second transistor). A drain of the PMOS transistor364C defines the output of the second pair. The PMOS transistor364C has a source coupled to the RTA switch165to receive the WLHDR, has a gate coupled to the output terminal of the inverter363, and has a drain coupled to the additional electrical line367and to the NAND gate366. The PMOS transistor364D has a source coupled to the RTA switch165to receive the WLHDR, has a gate coupled to the drain of the PMOS transistor364C, to the additional electrical line367and to the NAND gate366, and has a drain coupled to the NAND gate366and to the electrical line357.

The NMOS transistor375is coupled in series connection with the NMOS transistor370. A drain of the NMOS transistor375is coupled to the dummy bit line180and a source of the NMOS transistor370is coupled to the ground supply (Vss).

The second circuit185includes two pairs of NMOS transistors in series connection. A first pair of NMOS transistors in series connection includes an NMOS transistor381A (first NMOS transistor) and an NMOS transistor381B (second NMOS transistor). A drain of the NMOS transistor381A is coupled to the dummy bit line180and a source of the NMOS transistor381B is coupled to an input terminal of an inverter385. The gates of the NMOS transistor381A and of the NMOS transistor381B are coupled to the peripheral voltage supply. Similarly, a second pair of NMOS transistors in series connection includes an NMOS transistor381C and an NMOS transistor381D. A drain of the NMOS transistor381C is coupled to the dummy bit line180and a source of the NMOS transistor381D is coupled to the input terminal of the inverter385. The gates of the NMOS transistor381C and of the NMOS transistor381D are coupled to the array voltage supply.

The second circuit185further includes a testing circuit390, for example a discrete Fourier transform delay circuit, having an input terminal coupled to an output terminal of the inverter385. An output terminal of the testing circuit390is coupled to an input terminal of a NAND gate395. Another input terminal of the NAND gate395is configured to receive a disable signal (ST_DISABLE). An output terminal of the NAND gate395is coupled to the pulse generator190(not shown inFIG. 3).

The operation of the section300is now explained.

Initially, the external clock signal (CLK) is received to generate the clock signal (ICLK) and initiate a read operation. The NMOS transistor315A and the NMOS transistor315B are active to generate the clock signal at logic level LOW. The NOR gate320generates an output signal at logic level HIGH. Output of the inverter325is at logic level LOW which selects a wordline driver, for example the wordline driver120A1, corresponding to a desired memory cell, for example the memory cell135A1, that needs to be accessed. The wordline driver120A1drives the wordline125A1to logic level HIGH. The output of the inverter325is referred to as “a first clock signal”.

A second clock signal is also generated at logic level LOW by delaying the clock signal using the inverter195and the inverter196. Output of the inverter196is referred to as “the second clock signal”. The RTA switch165generates the ARHDR (first signal) and the WLHDR in response to the second clock signal. The ARHDR is initially precharged to VDDAR.

The NOR gate361generates an output at logic level HIGH in response to the second clock signal and a block select signal (BLK_SEL). The block select signal enables selection of a desired block, for example the block including the wordline125A1and the memory cell135A1. The PMOS transistor364A and the PMOS transistor364C are inactive as the output of the inverter363is at logic level HIGH. Initially, the electrical line357and the additional electrical line367are charged to logic level HIGH using the PMOS transistor364A and the PMOS transistor364C.

The wordline driver120A1drives the wordline125A1to logic level HIGH in response to the first clock signal and the WLHDR. Driving of the wordline125A1to the logic level HIGH renders the memory cell135A1ready for access. When the wordline125A1is driven at logic HIGH, the NMOS transistor356becomes active and provides a discharge path to the electrical line357. The electrical line357discharges through the NMOS transistor356to logic level LOW. As the electrical line357reaches the logic level LOW, the PMOS transistor364B becomes active to maintain the additional electrical line367at logic level HIGH. The NAND gate366is responsive to the discharge of the electrical line357to generate a wordline activation signal at logic level HIGH. The discharge of the electrical line357is indicative of the wordline125A1being driven HIGH. Hence, the wordline path from the clock generator110to the wordline125A1is tracked accurately. Even if precharging of the wordline125A1is slow due to variation in the WLHDR, the variation is tracked. The variation is tracked as precharging of the electrical line357and the additional electrical line367are also slow, due to the inverter362and the inverter363receiving the WLHDR. Hence, the tracking circuit170also tracks an RTA path by tracking variation in the WLHDR. The RTA path can be defined as a path from the clock generator110to the inverter195to the inverter196to the RTA switch165to generation of the WLHDR. Similarly, the ARHDR is also tracked by the tracking circuit170. A replica path of the wordline path is also provided by the tracking circuit170.

The NAND gate366generates the wordline activation signal in conjunction with the circuit365and the circuit360. The circuit360aids generation of the wordline activation signal in response to the WLHDR. The wordline activation signal generated at the logic level HIGH activates the NMOS transistor375. The NMOS transistor370is also active in response to the ARHDR (first signal). The dummy bit line180then discharges through the NMOS transistor375and the NMOS transistor370based on the logical AND combination of the ARHDR and the wordline activation signal. In some embodiments, the section300also includes an NMOS transistor367having a gate configurable to receive a signal (Y) to aid discharge of the dummy bit line180. The signal Y can be received from an address comparator (not shown) in order to prevent an out of bound address condition.

The dummy bit line180is precharged using a PMOS transistor382. The dummy bit line180is coupled to a drain of a PMOS transistor382. The PMOS transistor382has a source coupled to the peripheral voltage supply and has a gate configurable to receive a delayed version of the second clock signal to precharge the dummy bit line180.

The operation of the second circuit185is now explained in further detail. The second circuit185tracks discharging of the dummy bit line180across peripheral voltage supply variations and generates the second signal based on the peripheral voltage supply variations and the array voltage supply variations. The second circuit185works on the peripheral voltage supply (VDDPR) and hence, is able to track variations in the peripheral voltage supply. The second circuit185is also able to track variations in the array voltage supply (VDDAR). The NMOS transistor381A and the NMOS transistor381B pass the logic level LOW of the dummy bit line180to the inverter385. The NMOS transistor381A and the NMOS transistor381B pass the logic level LOW based on peripheral voltage supply variations. Similarly, the NMOS transistor381C and the NMOS transistor381D pass the logic level LOW based on array voltage supply (VDDAR) variations.

The inverter385is operable to invert logic level LOW of the dummy bit line180for generating the reset signal (RESET, second signal). In some embodiments, the testing circuit390tests delay in the reset signal and can add further delay to the reset signal. The NAND gate395then outputs the reset signal at logic level HIGH. The reset signal is supplied to the clock generator110to switch OFF operation of the wordline drivers and other circuitry. The reset signal is also supplied to the pulse generator190(not shown) that generates the enable signal (ENSA) to enable the sense amplifier160A1(not shown) to access the memory cell135A1. Driving of the wordline125A1to logic level HIGH enables the memory cell135A1to generate a differential voltage across the bit lines BL1and BLB1. The generation of the enable signal is delayed by a time that the memory cell135A1requires to generate the differential voltage from generation of the clock signal. The delay is enabled by tracking the entire path from the clock generator110to the memory cell135A1using the tracking circuit170. The sense amplifier160A1(not shown inFIG. 3) is responsive to the enable signal to sense the differential voltage and hence, access the memory cell135A1at a time when the memory cell135A1is ready to be accessed. The second circuit185enables access to the memory cell135A1at a desired time by introducing a delay between time of discharge of the dummy bit line180and time to access the memory cell135A1based on the voltage peripheral supply variations and the array voltage supply variations.

The tracking can be affected with variations in the VDDARand the VDDPR. However, as a circuit380is supplied with both the VDDARand the VDDPR, effect due to variations in the VDDARor the VDDPRare eliminated.

The effect of the second circuit185can be controlled using the ST_disable signal supplied to an input terminal of the NAND gate395.

The tracking circuit170works in both the RTA mode and the non-RTA mode, and hence no fixed delay or worst case delay needs to be present in generation of the enable signal to access the memory cell. Hence, there is no penalty in terms of performance of the memory circuit100. The tracking circuit170tracks the wordline path in both the RTA mode and the non-RTA mode, and hence, aids in generation of the enable signal with a delay that is appropriate to enable accurate reading of the memory cell. The tracking circuit170thus enables the memory circuit100to have self-time generation of the enable signal to perform accurate read or write operation.

Referring toFIG. 4now, a section400of the memory circuit100is illustrated. The section400includes several blocks of wordlines and memory rows. Examples of the blocks include a block405A1to405AX. Each block includes 16 wordlines and memory cells. For example, the block405A1includes wordlines form a wordline125A1to a wordline125AM, and several memory cells (not shown), for example the memory cell135A1to the memory cell135AN.

There may be one first circuit for one block. For example, the first circuit175for the block405A1and a first circuit445for the block405AX. Each first circuit, according to this example, includes 16 NMOS transistors, an electrical line, a pair of NMOS transistors and an inverter. For example, the first circuit175includes an NMOS transistor356A1(first transistor) having a gate coupled to the wordline125A1and a drain coupled to the electrical line357(first electrical line). The electrical line357is then coupled to an inverter410A1. An output terminal of the inverter410A1is coupled to the gate of the NMOS transistor375. The drain of the NMOS transistor375is coupled to the dummy bit line180. The NMOS transistor375is coupled in series connection to the NMOS transistor370. The gate of the NMOS transistor370is configured to receive the ARHDR (first signal). The dummy bit line180is coupled to the second circuit185. Structure similar to that of the first circuit175exists for the first circuit445.

The operation of the section400is now explained. The driving of the wordline125A1remains similar to that explained above with reference toFIG. 3. The NMOS transistor356A1becomes active in response to the wordline125A1driven to the logic level HIGH. The electrical line357which is precharged to logic level HIGH then starts discharging through the NMOS transistor356A1. The inverter410A1inverts the logic of the electrical line357to generate inverted logic. The NMOS transistor375is activated in response to the inverted logic and the NMOS transistor370is also active in response to the ARHDR (first signal). The dummy bit line180discharges to logic level LOW through the NMOS transistor375and the NMOS transistor370. The discharge of the dummy bit line180is then tracked across the peripheral voltage supply variations using the second circuit185(explained inFIG. 3). The accessing of the memory cell135A1using the section400and generation of the reset signal by the second circuit185is similar to that explained in theFIG. 3using the section300.

Referring toFIG. 5now, a method for tracking a memory circuit, for example the memory circuit100, is provided.

At step505, a wordline activation signal is generated in response to activation of a wordline. The wordline activation signal indicates that a memory cell coupled to wordline is ready for access.

At step510, a dummy bit line coupled to the wordline is discharged based on a logical combination of a first signal, for example ARHDR, and the wordline activation signal. The first signal is indicative of a voltage of an array header of the memory circuit. In one embodiment, the dummy bit line is discharged based on a logical AND operation between the first signal and the wordline activation signal.

At step515, access to the memory cell, coupled to the wordline, is enabled in response to discharging of the dummy bit line. In one embodiment, a voltage of the dummy bit line is inverted based on the peripheral voltage supply variations and the array voltage supply variations to cause access to the memory cell based on inverted voltage signal.

Referring toFIG. 6now, a method for accessing a memory cell, for example the memory cell135A1ofFIG. 1, in a memory circuit, for example the memory circuit100ofFIG. 1, is provided.

At step605, a clock signal, also referred to as internal clock signal (ICLK), is generated in response to an external clock signal (CLK). The ICLK is generated in response to a rising edge of the CLK. A read operation is initiated on generation of the ICLK. The ICLK is generated, for example, by using the clock generator110. A first clock signal and a second clock signal are then generated in response to the ICLK.

At step610, a first signal and a wordline header signal are generated in response to the second clock signal. The first signal (ARHDR) is a voltage signal of an array header of the memory circuit. The second signal (WLHDR) is a voltage signal of a wordline header of the memory circuit. The first signal and the wordline header signal can be generated, for example, by using the RTA switch165.

At step615, a wordline, for example the wordline125A1, is driven HIGH in response to the wordline header signal and the first clock signal. The wordline can be driven HIGH, for example, by using the wordline driver120A1. The driving of the wordline renders the memory cell ready for access.

At step620, an electrical line is discharged in response to driving of the wordline. The electrical line, for example the electrical line357, can be discharged, for example, by using the NMOS transistor356. The discharge of the first electrical line is indicative of the wordline being driven.

The electrical line is precharged, for example, by using the circuit365and the circuit360.

At step625, a wordline activation signal is generated in response to the discharge of the first electrical line. The wordline activation signal is generated, for example, by using the circuit365. The wordline activation signal is at logic level HIGH.

At step630, a dummy bit line, for example the dummy bit line180, is discharged in response to the logical AND operation on the wordline activation signal and the first signal. The dummy bit line can be discharged, for example, by using the NMOS transistor375and the NMOS transistor370.

The dummy bit line can be precharged in response to a delayed version of the second clock signal.

At step635, the discharge of the dummy bit line is tracked across peripheral voltage supply (VDDPR) variations, for example, by using the second circuit185.

At step640, a reset signal (RESET) is then generated, for example by using the inverter385in conjunction with the testing circuit390and the NAND gate395. The reset signal is generated by adding a delay that is sufficient to enable the memory cell to be accessed at a time when the memory cell is ready to be accessed.

At step645, an enable signal is generated in response to the reset signal, for example, by using the pulse generator190.

At step650, the memory cell is accessed in response to the enable signal, for example by using the sense amplifier160A1.

The reset signal is also provided to the clock generator110to deactivate the clock signal. However, the second clock signal is generated continuously to enable self-timing by the memory circuit.

In some embodiments, step620and step625can be referred to as tracking a wordline path from a clock circuit, for example the clock circuit105, to the wordline.

In the foregoing discussion, the term “coupled” refers to either a direct electrical connection between the devices connected or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means at least either a single component or a multiplicity of components, that are connected together to provide a desired function. The term “signal” means at least one current, voltage, charge, data, or other signal.

The foregoing description sets forth numerous specific details to convey a thorough understanding of embodiments of the disclosure. However, it will be apparent to one skilled in the art that embodiments of the disclosure may be practiced without these specific details. Some well-known features are not described in detail in order to avoid obscuring the disclosure. Other variations and embodiments are possible in light of above teachings, and it is thus intended that the scope of disclosure not be limited by this Detailed Description, but only by the Claims.