Frequency counter and method

An averaging frequency counter for determining the frequency of recurrence of input signals has an event counter for counting a number of the input signals, a gate counter for counting a number of time intervals during which the input signals are counted, and a time interval measurement circuit for measuring the cumulative duration of the time intervals. A systematic error associated with the measurement of the duration of each time interval is determined during an application of a calibrated frequency to the averaging frequency counter by dividing a calculated total time error by the number of time intervals. The systematic error is subsequently used to correct a measurement of an unknown frequency during an application of the unknown frequency to the averaging frequency counter by subtracting a product of the number of the time intervals and the systematic error from the cumulative duration.

BACKGROUND 
Typical averaging frequency counters are described in U.S. Pat. No. 
3,609,326 entitled "Counting Apparatus and Method Using Separate Counters 
for Reference and Unknown Signal", issued to Alan S. Bagley and France 
Rode on Sept. 28, 1971, and by James L. Sorden in "A New Generation in 
Frequency and Time Measurements", Hewlett-Packard Journal, June 1974. In 
these counters a number of signals recurring at an unknown frequency are 
gated to an event counter for a number of time intervals. A cumulative 
time interval measurement circuit is activated synchronously with the 
event counter to measure a cumulative duration of the number of time 
intervals comprising a desired measurement. The number of events counted 
by the event counter divided by the cumulative duration of the time 
intervals represents the value of the unknown frequency. However, a 
systematic error is associated with the measurement of each time interval 
due to mismatches in the start and stop functions of the cumulative time 
interval measurement circuit. For reciprocal frequency measurement 
techniques using short time intervals this error causes especially 
undesirable errors in the determination of the unknown frequency. 
SUMMARY 
An averaging frequency counter determines a frequency of recurrence of 
input signals by dividing a number of input signals by a cumulative 
duration of a number of time-related time intervals counted by an interval 
counter means. Calibration means selectively apply input signals recurring 
at a known frequency to the averaging frequency counter and determine a 
systematic error associated with a time measurement of a duration of a 
time interval. The systematic error is used to correct the measurement of 
the cumulative duration of a number of time intervals during a selective 
application of input signals recurring at an unknown frequency to the 
averaging frequency counter.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
A block diagram of the preferred embodiment of the present invention is 
illustrated in FIG. 1. A switch 10 selects either a frequency signal 15 or 
an input signal 20 and applies the selected signal 25 to a clock input of 
a flip-flop 30. A data input of the flip-flop 30 is coupled to receive a 
selected arming signal 35 which is selected by a switch 40 from either an 
external arming signal 45 or an internal arming signal 50. The selected 
signal 25 and a gate signal 32 from a Q output of the flip-flop 30 are 
applied to first and second inputs of AND gate 55 respectively. AND gate 
55 generates pulses 57 in response to the signals applied to the inputs 
thereof. 
The operating waveforms of a synchronizer circuit 90 comprising the 
flip-flop 30 and the AND gate 55 are shown in FIG. 2. Flip-flop 30 is 
armed by application of the selected arming signal 35 to the data input 
thereof. While armed, the flip-flop 30 produces the gate signal 32 on the 
Q output in response to a next occurring leading edge of a pulse of the 
selected signal 25. Similarly, after the selected arming signal 35 from 
the data input is removed, the gate signal 32 on the Q output is 
terminated in response to a next occurring leading edge of a pulse of 
selected signal 25. In this way the pulses 57 generated by AND gate 55 are 
all integral clock pulses and the gate signal 32 is synchronized with the 
integral clock pulses. The synchronizer circuit 90 thus avoids a bias in a 
measurement of a duration of a gate signal 32 caused by truncating clock 
pulses. Synchronizer circuits of this type and their operating 
characteristics are described by David C. Chu in "Time Interval Averaging: 
Theory, Problems, and Solutions", Hewlett-Packard Journal, June 1974. 
Synchronizing circuits of this type are also discussed in U.S. Pat. No. 
3,631,343 entitld "Time Interval Averaging Circuit" issued to Rolf 
Schmidhauser on Dec. 28, 1971. 
An event counter 60, illustrated in FIG. 1, is coupled to AND gate 55 for 
counting a number EC of the pulses 57. A gate counter 65 is coupled to the 
Q output of the flip-flop 30 to receive the gate signal 32 for counting a 
number N of gate signals 32. A time interval measurement circuit 70 is 
coupled to the Q and Q outputs of the flip-flop 30 for measuring a 
cumulative time T during which the gate signal 32 is present. Suitable 
time interval measurement circuits operational in this embodiment are 
described in the referenced article by James L. Sorden and in an article 
entitled "Ovenless Oscillators will Resolve 20-Picoseconds Pulses" in Nov. 
10, 1977, Electronics by David C. Chu and Keith M. Ferguson. 
A calculator-controller 75 is coupled to the event counter 60, the gate 
counter 65 and the time interval measurement circuit 70 for receiving the 
counts EC and N, and the cumulative time T. The calculator-controller 75 
is further coupled to the switches 10 and 40 for controlling operation as 
described in detail below. 
To calculate a systematic error .DELTA.T associated with the measurement of 
the time duration of each gate signal 32, calculator-controller 75 causes 
switch 10 to select the frequency reference signal 15 and to apply the 
selected signal 25 to the flip-flop 30 and to the AND gate 55. After a 
measurement is completed, as determined by elapse of a preselected time, 
the calculator-controller 75 receives the counts EC and N and the time T 
from the event counter 60, the gate counter 65 and the time interval 
measurement circuit 70 respectively. Since the frequency f.sub.REF of the 
frequency reference signal 20 is known, the systematic error .DELTA.T 
associated with a measurement of a duration of each gate signal 32 equals 
the difference between the time T and the quotient of the count EC divided 
by the frequency f.sub.REF, divided by the count N. In formula: 
EQU .DELTA.T=T-EC/f.sub.REF /N 
a measurement of a frequency f.sub.IN of the input signal 20 is 
subsequently achieved by calculator-controller 75 causing switch 10 to 
select the input signal 20 and apply the selected signal 25 to the 
flip-flop 30 and the AND gate 55. The frequency of the input signal 20, 
f.sub.IN, is then calculated by dividing the count EC by the difference 
between the time T and the product of the count N and the systematic error 
.DELTA.T. In formula: 
EQU f.sub.IN =EC/T-(N.multidot..DELTA.T) 
one embodiment of the calculator-controller 75 is illustrated in FIG. 3. A 
state selector 100 selects one of a first and second operating states 
corresponding to the calculation of the systematic error .DELTA.T and the 
measurement of the frequency f.sub.IN respectively. In the first operating 
state the state selector 100 causes switches 105, 110 and 115 to couple 
counts EC and N and the time T to dividers 120 and 140 and a subtractor 
130 respectively, in timed relationship with the selection of the 
frequency reference signal 15 by the switch 10. A value of the frequency 
f.sub.REF stored in a memory 25 is applied to the divider 120 for dividing 
the count EC by the frequency f.sub.REF. The resulting quotient is 
subtracted from the time T in the subtractor 130 to produce a difference 
signal which is divided by count N in the divider 140 to produce a 
quotient signal. The quotient signal from the divider 140 is applied to 
and stored in a memory 145 and represents the systematic error .DELTA.T. 
The state selector 100 subsequently selects the second operating state and 
causes the switches 105, 110 and 115 to couple counts EC and N and time T 
to a divider 160, a multiplier 150, and a subtractor 155 respectively in 
timed relationship with the selection of the input signal 20 by the switch 
10. The count N is multiplied by the systematic error .DELTA.T in the 
multiplier 150 to produce a product which is subtracted from the time T by 
the subtractor 155 to produce a difference signal. The count EC is divided 
by the difference signal from subtractor 155 to produce a display signal 
representative of the input frequency f.sub.IN by a divider 160. The 
display signal is coupled to a display 80 to provide a visual indication 
of a magnitude of the input frequency f.sub.IN. 
In an alternative embodiment the calculator-controller 75 is replaced by a 
microprocesser under the control of a software program designed to 
implement the equivalent logic operations. 
The present invention may comprise the implementation of the gate counter 
65 as software in the calculator-controller 75. In this alternative 
embodiment, switch 40 selects the internal gate signal 50 generated by the 
calculator-controller 75. A number of internal gate signals 50 are 
generated and used in the computations of the systematic error .DELTA.T 
and input frequency f.sub.IN. Further, a measurement can be terminated 
upon the generation of the preselected number of the gate signals 50 
rather than upon the elapse of a preselected time. However, this technique 
is not preferred for counting a high-speed pulsed RF signal such as 
commonly used in short range radar because of the comparatively lower 
speed of a software counter. 
In place of a synchronizer circuit 90, a typical synchronizer circuit or 
direct gating circuit such as the circuits described on page 8 of the 
Hewlett-Packard Application Note 162-1 could be substituted. However, the 
use of the synchronizer circuit 90, or of an equivalent circuit as 
described in the aforementioned patent issued to Rolf Schmidhauser, is 
preferred because such a synchronizer circuit avoids the biasing errors 
otherwise present.