Signal transmission apparatus and signal transmission method

According to one embodiment, a signal transmission apparatus being AC-coupled with a receiving apparatus through a digital transmission line includes a transmitting module configured to transmit a differential signal based on an encoded bit serial input signal such that a low frequency component of the differential signal to be transmitted is maintained at a constant level when the differential signal based on the encoded bit serial input signal is transmitted to the digital transmission line where the encoded bit serial input signal includes a ratio of the number of logic 1 to the number of logic 0 which is different from 5:5.

CROSS-REFERENCE TO RELATED APPLICATION(S)

The application is based upon and claims the benefit of priority from Japanese Patent Applications No. 2012-115096 filed on May 18, 2012, and No. 2012-175452 filed on Aug. 7, 2012, the entire content of which are incorporated herein by reference.

FIELD

Embodiments of the present invention relate to a signal source device and a signal transmission method that transmits a differential signal.

BACKGROUND

In the High-Definition Multimedia Interface (HDMI) specification (e.g., version 1.4b released on Oct. 11, 2011) of image source devices such as DVD/STB or image sink devices such as TV that transmits or receives the signals through three digital transmission lines, eight bits for each pixel signal of three colour components (R, G, B) of an image signal and two bits for each of control signals to be transmitted during a blanking period of the image signal are converted (encoded) into ten bits, respectively, to be transmitted serially over the three-channel transmission lines. This encoding scheme is referred to as Transmission Minimized Differential Signal (TMDS).

Large-scale integrated circuits manufactured by employing a micro-lithography can be preferably utilized so as to reduce the cost of a high-speed serial driving circuit of a HDMI transmitting module.

However, in the HDMI specification, when transmitting signals serially between an HDMI transmitting module and an HDMI receiving module, which are connected via an HDMI cable, a scheme of DC coupling between a termination resistor of the HDMI receiving module pulled up to 3.3V and the HDMI transmitting module is utilized. The high speed serial driving circuit of the HDMI transmitting module is required to withstand the voltage characteristics corresponding to the pulled up voltage.

Therefore, it is difficult to utilize a large scale integrated circuit having a low withstand voltage characteristics as the high speed serial driving circuit of the HDMI transmitting module.

Accordingly, the embodiments of the present invention intend to provide a signal transmission apparatus and a signal transmission method in which the signals can be transmitted to a signal receiving device with suppressing the influence of the voltage of the signal receiving device which is pulled up to a predetermined voltage.

DETAILED DESCRIPTION

Hereinafter, the embodiment will be described with reference to the accompanying drawings.

According to one embodiment, a signal transmission apparatus being AC-coupled with a receiving apparatus through a digital transmission line includes a transmitting module configured to transmit a differential signal based on an encoded bit serial input signal such that a low frequency component of the differential signal to be transmitted is maintained at a constant level when the differential signal based on the encoded bit serial input signal is transmitted to the digital transmission line where the encoded bit serial input signal includes a ratio of the number of logic 1 to the number of logic 0 which is different from 5:5.

FIG. 1illustrates an overview of an exemplary configuration of the HDMI system according to an embodiment of the present invention. Further, the configuration overview ofFIG. 1is similar to that of a conventional HDMI system. Also, the same HDMI system as the conventional HDMI system is also utilized in the embodiment.

In the HDMI system ofFIG. 1, an HDMI source device101, for example, a DVD player, and an HDMI sink device201, for example, a TV receiver, are connected with each other through a HDMI cable301.

The HDMI source device101is composed of an HDMI transmitting module102, an HDMI terminal103, a TMDS transmitting module104and a microcomputer105. The HDMI terminal103contains a plurality of terminals, and each of which is connected to each of the transmission lines of the HDMI cable301.

The microcomputer105has functions of detecting the connection of HDMI sink device201with the HDMI cable301through the voltage variation of HPD (Hot Plug Detect) signal line within the HDMI cable301, of reading-out data from an EDID memory207of the HDMI sink device201using the DDC (Display Data Channel) line of the HDMI cable301, and of communicating using a CEC (Consumer Electronics Control) line of the HDMI cable301.

The HDMI sink device201includes an HDMI receiving module202, an HDMI terminal203, a TMDS receiving module204, a microcomputer205and an EDID memory207having encoded and stored a display characteristic capability of the HDMI sink device therein.

The microcomputer205has functions of detecting a state, at which the HDMI source device101is connected with the HDMI cable301and activated by being supplied with electrical power, through 5V line of the HDMI cable301, and function of communicating using CEC line of the HDMI cable301.

FIG. 2is a block diagram illustrating an example of a configuration of the TMDS transmitting module104.

The TMDS transmitting module104is composed of TMDS signal driving modules401,402and403, a CK driving module404, TMDS encoder/parallel-to-serial converters405,406and407, and PLL (Phase Locked Loop)408. The TMDS transmitting module104corresponds to a TMDS transmitter 1 depicted in FIG. 1 of Japanese Patent Application Laid-Open Publication No. 2005-514873. The TMDS encoder/parallel-to-serial converters405,406and407correspond to encoder/parallel-to-serial converters 2, 4 and 6 depicted in FIG. 1 of Japanese Patent Application Laid-Open No. 2005-514873. Additionally, the TMDS signal driving modules401,402and403, a CK driving module404, and PLL408are depicted inFIG. 2of the embodiment of the present invention. A portion of the HDMI cable is also depicted inFIG. 2enabling easy to understand an overview of the TMDS transmitting module.

In the HDMI specification, each 8-bit data of the three-color components (B[7:0]), G[7:0], R[7:0]) of pixels of an image signal to be transmitted is converted into (TMDS encoded) 10-bit data, respectively, by the TMDS encoder/parallel-to-serial converters405,406and407to be converted into a serial data. This encoding scheme is referred to as Transition Minimized Differential Signal (TMDS). Each of the three-color components (R, G, B) of pixels of the image signal converted into the serial data is input to each of TMDS signal driving modules401,402and403as TMDS-Ch0, TMDS-Ch1 and TMDS-Ch2, respectively. The TMDS signal driving modules401,402and403generate differential signals based on the input bit serial data and output the differential signals to the transmission lines of the each channel (drive the transmission line of the each channel).

An blanking signal (containing Horizontal synchronization signal (H-Sync) and Vertical synchronization signal (V-Sync)) along with each of the control signals CTL0, CTL1, CTL2and CTL3composes the image signal. When the image signal is transmitted, the blanking signal or the respective control signals and the pixel signals (B[7:0], G[7:0], R[7:0]) are discriminated by a data enable (DE) signal. That is, as illustrated inFIG. 6described below, in the case where the blanking signal and various control signals have been transmitted when the DE signal becomes 0, and in the case where the pixel signal has been transmitted when the DE signal becomes 1.

Herein, 2-bit of H-Sync and V-Sync is converted into 10-bit serial data by the TMDS encoder/parallel-to-serial converter405and becomes the differential signal at the TMDS signal driving module401to drive the Ch0 transmission line304. 2-bit of CTL0and CTL1is converted into 10-bit serial data by the TMDS encoder/parallel-to-serial converter406and becomes the differential signal at the TMDS signal driving module402to drive the Ch1 transmission line305. Further, 2-bit CTL2and CTL3is converted into 10-bit serial data by the TMDS encoder/parallel-to-serial converter407and becomes differential signal at TMDS signal driving module403to drive the Ch2 transmission line306.

FIG. 3is a view illustrating an example of a conventional HDMI connection aspect. In the conventional HDMI system, a TMDS transmitting module104aand a TMDS receiving module204are DC-coupled through the HDMI cable. The TMDS transmitting module104acontains a TMDS signal driving modules401a. The TMDS transmitting module104acorresponds to the TMDS transmitting module104according to the embodiment and the TMDS signal driving module401ais a module corresponding to the TMDS signal driving module401. However, details of the configuration of the TMDS transmitting module104ais different from that of the TMDS transmitting module104, and further, details of the configuration of the TMDS signal driving module401ais different from that of the TMDS signal driving module401.

The TMDS signal driving module401acontained in the TMDS transmitting module104ais coupled to a TMDS signal detecting module501contained in the TMDS receiving module204illustrated inFIG. 1through the Ch0 transmission line304of the HDMI cable301.

Further, the configurations of the TMDS signal driving modules connected to other transmission lines (Ch1 transmission line (305), Ch2 transmission line (306), Ch3 transmission line (307)) are similar to that of the TMDS signal driving module401a, and the descriptions thereof will be omitted. Also, the descriptions regardingFIGS. 4 to 13will be made based on the Ch0 transmission line304and a module according to the Ch0 transmission line304, however, the descriptions of the Ch0 transmission line304and the module are the same as those in other transmission lines and modules according to the transmission lines.

The TMDS signal driving module401acontains a switch502, switch503and a current source504. The switch502switches ON and OFF the connection of the current source504with the transmission line304, and the switch503switches ON and OFF the connection of the current source504with the transmission line304. The switch102and the switch103are operated mutually in an invert phase. The TMDS signal driving module401aswitches ON and OFF of the switches502and503in accordance with an input signal logic of the TMDS-Ch0 signal of bit serial data input from the TMDS encoder/parallel-to-serial converter405. The current source current I1alternately turned ON/OFF in accordance with the input logic of the TMDS-Ch0 signal of the bit serial data is transmitted to the TMDS signal detecting module501of the TMDS receiving module204of the HDMI receiving module202through the Ch0 transmission line304of the HDMI cable301. In other words, the current source504is connected to the differential inputs of a resistor506, a resistor507, and an amplifier508through the Ch0 transmission line304.

By doing this, the bit serial data of the TMDS-Ch0 signal of the TMDS transmitting module104is detected by an amplifier508of the TMDS signal detecting module501of the TMDS receiving module204. That is, the bit serial data of the TMDS-Ch0 signal input to the TMDS signal driving module401ais transmitted to the TMDS receiving module204as the bit serial data of the TMDS-Ch0 signal output from the amplifier508.

Further, the voltage AVcc505of the HDMI receiving module202has been applied to the terminals of the S1+ signal and S1− signal output from the TMDS signal driving module401a. The voltage of the AVcc505is set to 3.3 V according to the interface standards. The TMDS transmitting module104ais implemented by an integrated circuit, but since the withstand voltage characteristics corresponding to the voltage of 3.3 V, a large scale integrated circuit which does not satisfy the withstand voltage characteristics cannot be employed in the conventional TMDS signal driving module.

FIG. 4is a view illustrating an example of the HDMI system aspect in the case where the HDMI source device and the HDMI sink device are AC-coupled. Furthermore, the configuration of the HDMI system illustrated inFIG. 4is different from that of the conventional HDMI, unlike the HDMI system illustrated inFIG. 3. In the HDMI system illustrated inFIG. 4, a TMDS transmitting module104band a TMDS receiving module204are AC-coupled through the HDMI cable. The TMDS transmitting module104bcontains a TMDS signal driving module401b. The TMDS transmitting module104bcorresponds to the TMDS transmitting modules104illustrated inFIGS. 1 and 2, and the TMDS signal driving module401bis a module corresponding to the TMDS signal driving module401ofFIGS. 1 and 2. However, details of the configurations of the TMDS transmitting module104band the TMDS signal driving modules401bare different from those of the TMDS transmitting module104and the TMDS signal driving modules401, respectively. Furthermore, the components illustrated inFIG. 4to which the same reference numerals as those ofFIG. 3are given have the same functions as those described in the description ofFIG. 3.

The TMDS transmitting module104bofFIG. 4is AC-coupled with the TMDS receiving module204by inserted of the capacitors512and513to the connection path between the Ch0 transmission line304and the TMDS transmitting module104b, in addition to the respective components of the TMDS transmitting module104ainFIG. 3. Further, the capacitors512and513are installed outside the TMDS transmitting module104b, but, the positions of the capacitors512and513are not limited thereto and, for example, may be installed inside the TMDS transmitting module104bor the TMDS signal driving module401b. That is, the capacitors512and513may be installed at any position between the TMDS signal detecting module501and the TMDS signal driving module401bthat are not composed of DC-coupled (AC-coupled).

The TMDS signal driving module401bofFIG. 4is additionally provided with a power source AVcc2509, a pull up resistor510, a pull up resistor511and a circuit connected to the power source AVcc2509through the pull up resistors510and511, in addition to the respective components of the TMDS signal driving module401aofFIG. 3. Since the voltage of the AVcc2509can determined independently of the AVcc505, when the voltage of the AVcc2509is set to a low voltage, it is possible to utilize a large-scale integrated circuit being adopted a micro-lithography to TMDS signal driving module which has capable of higher speed operation and larger scale integrated circuit.

However, the ratio of the number of logic 1 (one) to the number of logic 0 (zero) among the serial data of 10-bit is not a ratio of 5:5, so that a DC unbalance between the S2+ signal and S2− signal occurs in the differential transmission lines of the HDMI receiving module202side after passing through the capacitors512or513and deteriorates the transmission characteristics. This deterioration will be described with reference toFIGS. 5 to 7.

FIG. 5is a view illustrating examples of TMDS-Ch0 data which is the serial input signal to the TMDS signal driving modules401,401aand401b, and the waveforms examples of the signals S1+ and S1− output from the TMDS signal driving modules401aand401bbefore and after the H-Sync signal transmitted in a blanking period of the image signal varies. Further, DE is at L level in a period during which the H-Sync signal having been input, but, the description thereof will be omitted. The waveform examples of the signals S1+ and S1− output from the TMDS signal driving modules401will be described in conjunction with the description ofFIGS. 12 and 13.

V-Sync illustrated inFIG. 5, (1) is a vertical synchronization signal of the image signal, and H-Sync illustrated inFIG. 5, (2) is a horizontal synchronization signal of the image signal. These signals are input to the TMDS encoder/parallel-to-serial converter405as input signals to the TMDS transmitting modules104,104aand104b.

FIG. 5, (3) illustrates the TMDS-Ch0 data of the bit serial data, a range of a module of 10-bit code and a logic value of each bit and 1-bit waveform. The waveform output from the TMDS encoder/parallel-to-serial converter405becomes a waveform pursuant to the TMDS-Ch0 data. This waveform data is input to the TMDS signal driving modules401,401aand401b. Further, the value of the each bit of the TMDS-Ch0 data is determined by a table ofFIG. 6Bwhich will be described in below.

That is, since the V-Sync=H as well as the H-Sync=H during a period of T1illustrated inFIG. 5, the state of the transmission path state becomes state 3 illustrated inFIG. 6B, and the 10-bit code becomes 1101010101. Similarly, the V-Sync=H and H-Sync=L during a period of T2illustrated inFIG. 5, the state of transmission path becomes state 2 illustrated inFIG. 6B, and the 10-bit code becomes 0010101010.

The waveform P1illustrated inFIG. 5, (4) represents a waveform of S1+ signal output from the TMDS signal driving modules401aand401b, and the waveform P2represents a waveform of DC component (low frequency component) of S1+ signal. The waveform P3illustrated inFIG. 5, (5) represents a waveform of S1− signal output from the TMDS signal driving modules401aand401b, and the waveform P4represents a waveform of DC component of S1− signal.

When the switch502is turned OFF, the TMDS-Ch0 data becomes H level of the logic value 1, and in this case, a level of the output driving data S1+ represents potential of the AVcc505included in the TMDS signal detecting module501ofFIG. 3. When the switch502is turned ON, the TMDS-Ch0 data becomes L level corresponding to logic 0, and in this case, the level of the output driving data S1+ becomes approximately potential of the AVcc-R1*I1. Further, since the ratio of the number of logic 1 to the number of logic 0 per 10-bit varies from 6:4 to 4:6 as a period varies from T1to T2, an average level of the output driving data S1+ becomes “AVcc−((AVcc−R1*I1)*6/10)” during H-Sync=H and “AVcc−((AVcc−R1*I1)*4/10)” during H-Sync=L. The average level is illustrated inFIG. 5, (4) as a DC component.

FIG. 6Aillustrates a corresponding relationship between each transmitting channel of Ch0 to Ch2 and the input and output signals of the TMDS encoder/parallel-to-serial converters.FIG. 6Billustrates a corresponding relationship between signals regarding Ch0 to Ch2 transmission lines and the encoded values when the signals have been encoded by the TMDS encoder/parallel-to-serial converters (signals (10-bit serial signals) output from the TMDS encoder/parallel-to-serial converters). When V-Sync=H as well as H-Sync=H, the TMDS-Ch0 data is 1101010101 corresponding to the 10-bit code in state 3 ofFIG. 6B. Further, when V-Sync=H and H-Sync=L, the TMDS-Ch0 data is 0010101010 corresponding to the 10-bit code in state 2 ofFIG. 6B. In the case where V-Sync=H, since the serial data can be obtained from the 10-bit codes for the case where the value of the H-Sync is varied from High (H) to Low (L) or from Low to High, it is possible to draw the TMDS-Ch0 data or the output driving data S1+ and S1− as depicted inFIG. 5.

FIG. 7, (1) illustrates a level of the H-Sync signal. InFIG. 7, (1), the H-Sync being in H level corresponds to the state 3 inFIG. 6Band the H-Sync being in L level corresponds to the state 2 inFIG. 6B.FIG. 7, (2) illustrates a waveform of the S1+ signal as the waveforms at a driving terminal, a waveform of DC component of the S1+ signal, a waveform of the S1− signal, and a waveform of DC component of the S1− signal. Further, the waveform P5of the S1+ signal and the waveform P6of DC component of the S1+ signal are depicted as a solid line, and the waveform P7of the S1− signal and the waveform P8of DC component of the S1− signal are depicted as a dotted line. These driving terminal waveforms are, for example, waveforms at the TMDS signal driving modules401aand401b.

The ratio of the DC component levels of the S1+ signal waveform and the S1− signal waveform at the driving terminal against to the 100% level of the S1+ signal and the S1− signal to be transmitted are four-tenths (40%) and six-tenths (60%), respectively, that is, shifted to level of ±10% based on the 50% level corresponding to a common voltage of the differential signal, respectively.

FIG. 7, (3) illustrates a waveform at a receiving terminal when the transmitting side and the receiving side are DC-coupled, that is, for example, illustrates a receiving terminal waveform at the TMDS signal detecting module501illustrated inFIG. 3. Here,FIG. 7, (3) illustrates a waveform of the S2+ signal as the waveforms at a receiving terminal, a waveform of DC component of the S2+ signal, a waveform of the S2− signal, and a waveform of DC component of the S2− signal. Further, the waveform P9of the S2+ signal and the waveform P10of DC component of the S2+ signal are depicted as a solid line, and the waveform P11of the S2− signal and the waveform P12of DC component of the S2− signal are depicted as a dotted line.

In the case of DC-coupled, the signal waveform at the receiving terminal will be described. Since the DC component at the receiving end is a low frequency component good for a signal transmission characteristic of the cable, amplitude of the DC component is the same as that of the transmitting end. Meantime, the high frequency components of the S2+ signal and S2− signal are deteriorated depending on the signal transmission characteristic of the cable and the amplitudes thereof become smaller. Here, the high frequency components are put reduced to 60% in a level where logic 1 is continued with three times.

FIG. 7, (4) illustrates a waveform at a receiving terminal for the case where the transmitting side and the receiving side are AC-coupled, that is, for example, a receiving terminal waveform at the TMDS signal detecting module501inFIG. 4. Here,FIG. 7, (4) illustrates a waveform of the S2+ signal as the waveforms at a receiving terminal, a waveform of DC component of the S2+ signal, a waveform of the S2− signal, and a waveform of DC component of the S2− signal. Further, the waveform P13of S2− signal and the waveform P16of DC component of the S2− signal are depicted as a solid line, and the waveform P15of the S2+ signal and the waveform P14of DC component of the S2+ signal are depicted as a dotted line.

For the case where being AC-coupled, the signal waveform at the receiving terminal will be described. When AC-coupled, the levels of the DC components of the S2+ signal and S2− signal are converged to a voltage level of the pull-up voltage AVcc505inFIG. 4by a capacitor utilized in the AC-coupling. Further, inFIG. 7, (4), the convergence level of the DC components is represented as 50% level, and a state of the convergence level in a period during which the H-Sync is in H level is illustrated. The DC component of the S1+ signal of which level at the driving terminal was 60% becomes 50% level as the DC component of the S2+ signal at the receiving terminal, and the DC component of the S1− signal of which level at the driving terminal was 40% becomes 50% level as the DC component of the S2− signal at the receiving terminal, so that the DC components of the S2+ signal and S2− signal become equal to each other.

InFIG. 7, (4), right after the H-Sync is varied from High state to Low state, the DC component also varies, and the S2− signal increases from a level of 50% by an varying amount of 20% and the S2+ signal decreases from a level of 50% by a varying amount of 20%, so that the S2− signal and the S2+ signal becomes 70% level and 30% level, respectively. The increased amount and the decreased amount of which converging time is determined by the value of the capacitor or the pull up resistor value are eventually converged to the pull up voltage AVcc505(as the 50% level).

During a period under transition state before being converged to the pull up voltage, a differential input to a differential amplifier508becomes small (eye pattern becomes narrower) as compared to the case of DC-coupled, so that a signal may not be detected. That is, during an AC-coupled state, when the DC component included in the signal varies, the signal may not be able to be detected as compared to the case of DC-coupled. Otherwise, a detection error rate increases. Further, the DC component varies when a state is changed from state 0 or state 1 to state 2 or state 3, from state 2 or state 3 to state 0 or state 1, from state 2 to state 3, or from state 3 to state 2, inFIG. 6(B). In other words, in the case where a 10-bit code input to the TMDS signal driving module is changed, when a ratio of the number of logic 1 and the number of logic 0 is not 5:5 in the 10-bit code of either one of before or after the 10-bit code is changed, the DC component is changed.

As described above, in the case where the bit serial signals input to the TMDS signal driving module includes a bit serial signal whose ratio of the number of logic 1 to the number of logic 0 per 10-bit is not 5:5, when the differential signal based on the bit serial signal is transmitted to the transmission path by the AC-coupling method, the respective midpoint levels of the differential signals are varied in transient at a time when the DC component contained in the differential signal itself is changed. Accordingly, the TMDS signal detecting module501at the receiving side becomes unable to normally detect the differential signals as compared to the case where the transmitting side and the receiving side are DC-coupled, or the detection error rate increases.

Accordingly, in the case where a ratio of the number of logic 1 to the number of logic 0 of the encoded bit serial input signal is not 5:5, when transmitting the encoded bit serial input to the digital signal transmission line as the differential signal, the TMDS signal driving module401compensates the waveforms of the signal so that the DC component of the bit serial differential signal to be transmitted becomes a constant level.

As illustrated inFIGS. 6(A) and 6(B), the ratio of the number of logic 1 to the number of logic 0 of the encoded 10-bit code itself is definite, and the DC component contained in the serial data signal becomes a constant ratio to the amplitude of the serial data signal. Therefore, the DC level of the signal to be transmitted is compensated so that the change in DC component of the serial data signal is not occurred in the TMDS signal driving module401.

FIG. 8illustrates a compensation level by the TMDS signal driving module401. The TMDS signal driving module401reduces the DC component level by 10% when the level is 50%, the DC component level by 20% when the level is 60% and does not correct the DC component level (the correction amount is 0%) when the level is 40%, such that DC component levels of the S1+ and S1− signals after compensation becomes 40% of a predetermined value. Where, the DC component level of 100% is a wave height value of the waveform of the 10-bit serial output signal, and a current value I1of the current source1of the driving circuit inFIG. 4.

FIG. 9illustrates an example of a circuit configuration of the TMDS signal driving module401according to the embodiment. Further, the functions of the components given to like reference numerals are the same as those described in theFIGS. 3 and 4.

The TMDS signal driving module401has a DC component correction circuit601in addition to the respective components included in the TMDS signal driving module401billustrated inFIG. 4. Herein, the H-sync, V-sync and the DE input to the TMDS transmitting module104are input to the DC component compensation circuit601. The DC component compensation circuit601switches the current to be corrected based on the signal inputted thereto. Further, the control signals are input and the DC component compensation circuits are added to the TMDS signal driving modules402and403as well, but, the description thereof is omitted. InFIG. 9, though the HDMI sink device201is not illustrated, the HDMI source device101is also connected to the HDMI sink device201.

The DC component compensation circuit601contains a logic circuit602, a current source603, a current source604, a current source605and a current source606, and a switch607, a switch608, a switch609and a switch610which are switching ON and OFF the currents from these current sources, respectively. The logic circuit602switches the currents of the current sources in accordance with the input logic as illustrated inFIG. 8depending on the input control signals (H-Sync, V-Sync and DE).

The current value I2of each of the current source603, current source604, current source605and a current source606is 10% (one-tenth) of a current value I1of the current source504.

The current values switched by the switches607and608are combined to be added to an amount of the current switched ON/OFF by the switch502, the resultant current is converted into a voltage by a resistor510and the voltage drives a positive (+) terminal of the Ch0 transmission line304of the HDMI cable through the capacitor512. Further, the current values switched by the switches609and610are combined to be added to a current amount of the current source504switched ON/OFF by the switch503, the resultant current is converted into a voltage by the resistor511and the voltage drives the negative (−) terminal of the Ch0 transmission line304of the HDMI cable through the capacitor513.

FIG. 10illustrates signal waveforms at the driving terminal and at the receiving terminal when the DC components are compensated at the TMDS signal driving module401as described inFIG. 9. Here,FIG. 10(1) represents a level of the H-sync.FIG. 10(2) represents the bit serial signal waveforms of the S1+ and S1− signals at the driving terminal of the HDMI cable and the waveforms of the DC components of the S1+ and S1− signals. Further, the waveform P17of the S1+ signal and the waveform P18of the DC component of the S1+ signal are represented by a solid line, and the waveform P19of the S1− signal and the waveform P20the DC component of the S1− signal are represented by a dotted line.

The DC component compensation circuit601reduces the S1+ level of which the DC component level was 60% inFIG. 7, (2) by 20% to become 40% in a period during which the H-Sync is in H. Further, the DC component compensation circuit601maintains the S1− level of which DC component level was 40% inFIG. 7, (2) at 40% without compensating the S1− level in the period during which the H-Sync is in H.

When a period during which the H-Sync is L comes, the DC component compensation circuit601maintains the S1+ level of which the DC component level was 40% inFIG. 7, (2) at 40% without compensating the S1+ level. Further, when the period during which the H-Sync is L comes, the DC component correction circuit601performs a compensation to reduce the S1− level of which the DC component level was 60% inFIG. 7, (2) by 20% to become 40%. By doing this, the DC component compensation circuit601maintains the DC component level to a level of 40% at all the periods.

FIG. 10(3) illustrates examples of the signal waveforms at the receiving terminal in the case where the correction described above is performed. Further, the waveform P21of the S2+ and the waveform P22of the DC component of the S1+ are represented by a solid line, and the waveform P23of the S2− and the waveform P24of the DC component of the S1− are represented by a dotted line. Since the DC component levels of the S1+ and S1− at the driving terminal are always constant, the bit serial signals of the S2+ and S2− at the receiving terminal do not vary, and a deterioration degree thereof is small as compared with the case where the compensation of the DC component is not performed for the AC-coupling as illustrated inFIG. 7, (4).

FIG. 11is a view illustrating examples of timing charts in the case where a compensation is performed so that amplitude of the entire bit serial signal waveform becomes larger, in addition to the operations performed for the DC component correction inFIG. 10. InFIG. 10, the amplitude of the AC component is 100%. However, since the DC level shifting down by 20% is performed on the AC component (high frequency component) of the S1+ signal, the amplitudes of the differential signals of the S1+ signal and S1− signal have resulted in 80% of the original signal amplitude (amplitude illustrated inFIG. 7, (2)). In order to make the differential signal amplitude of 80% to be the differential signal amplitude of 100%, the TMDS signal driving modules401performs a correction to increase the entire amplitude to 125%. That is, the TMDS signal driving modules401performs the DC level shifting down by 20% on the AC component of the S1+ signal which represents 100% level in a period during which the H-Sync=H inFIG. 7, (2) to obtain the differential amplitude of 80% as inFIG. 10(2). In order to make the differential signal amplitude of 80% to be increased to a differential signal amplitude of 100%, the TMDS signal driving modules401performs a correction on both the S1+ signal and S1− signal to make the amplitudes of the AC components of the S1+ signal and S1− signal to 1.25-fold as large as those of the original S1+ and S1− signals.

In order to perform a 1.25-fold amplification of the AC components described above, the current value I1of the current source504inFIG. 9is set to a value of 1.25-fold as large as that when being DC-coupled. Accordingly, the current values I2of the current source603, the current source604, the current source605and the current source606also varies to a value of 1.25-fold as large as those when being DC-coupled, but, the setting of I2to 10% (one-tenth) of the current value I1is not varied.

With the amplification described above, the input differential amplitude at the receiving terminal illustrated inFIG. 11(3) becomes 75%, and the same amount as that in the receiving terminal when being DC-coupled as inFIG. 7, (3) can be obtained. Strictly speaking, in the above-described example, the level becomes equivalent to those ofFIG. 7, but the waveforms are different from those ofFIG. 7. Since the received signal level depends on the characteristics of a cable serving as the signal transmission path, a much more accurate compensation amount is obtained by performing, first of all, increasing and correcting the amplitude to a minimum value of the transmission characteristics defined by a standard as a target value and then, the DC-shifting with a predetermined amount as an alternative for amplifying the amplitude. In the actual devices, since various compensation processing (e.g., waveform equalization) for the received signals are performed at the sink apparatus side, the matters illustrated inFIG. 11(2) are sufficient for the compensation to be performed at the transmitting side.

FIG. 12is a view illustrating a use-case example of the HDMI source device101and the HDMI sync device201according to the embodiment.

Here, the HDMI source device101is realized by, such as for example, a set top box or DVD player, while the HDMI sink device201is realized by, for example, TV or a monitor having, for example, a tuner.

FIG. 13is a view illustrating a configuration example of a system of the HDMI source device101and the HDMI sink device201.

The HDMI source device101includes a reading module1001, a receiving module1002, storage1003, a decoding module1004, and the HDMI transmitting module102. The reading module1001reads-out the encoded image data stored in an optical disk to output the encoded image data to the decoding module1004. Further, the receiving module1002has a function of receiving an encoded image data of, for example, terrestrial digital broadcasting wave or satellite digital broadcasting wave, as the tuner, or receiving an encoded image data of IP TV delivered via the Internet, and outputs the received data to the decoding module1004. The storage1003stores, for example, the recorded encoded image data, and outputs the encoded image data having recorded therein to the decoding module1004. The decoding module1004decodes the inputted encoded image data into, for example, an image data of the respective 8-bit RGB components. Further, the decoding module1004outputs a base band data of the 8-bit RGB to HDMI transmitting module102. The HDMI transmitting module102converts the decoded image data into a predetermined transmission format to output the converted image to the HDMI sink device201via the HDMI cable301.

The HDMI sink device201contains the HDMI receiving module202, a display processing module2001, a displaying module2002, a tuner2003, and a signal processing module2004. The HDMI receiving module202receives a signal representing an image and converts into an image data in a format (e.g., base band data of the respective 8-bit RGB components) capable of being processed by the display processing module2001. Further, the display processing module2001converts the image data input from the HDMI receiving module202or the display processing module2001into an image signal in a format capable of being displayed by the display processing module2001and outputs the converted image signal to the displaying module2002. The displaying module2002displays the image using the input image signal.

The tuner2003receives the encoded image data of the terrestrial digital broadcasting wave or BS digital broadcasting wave. The signal processing module2004decodes the encoded image data and converts the decoded image data into an image data to be output to the display processing module2001.

Second Embodiment

Next, the second embodiment of the present invention will be explained. In the first embodiment, the HDMI source device101compensates the levels of the differential signal so that the DC components of the differential signal to be outputted maintain the constant values. An HDMI source device101caccording to this embodiment compensates the levels of the differential signal so that the DC components of the differential signal to be outputted have waveforms similar to those of the DC components of the differential signal outputted in the HDMI configuration of the related art illustrated inFIG. 3. In other words, the HDMI source device101caccording to this embodiment corrects the levels of the differential signal in a manner that the DC component of the signal outputted from the positive (+) side of a differential signal line has a waveform similar to that of the waveform P6illustrated inFIG. 7, (2) and the DC component of the signal outputted from the negative (−) side of the differential signal line has a waveform similar to that of the waveform P8illustrated inFIG. 7, (2).

FIGS. 14A and 14Bare views for illustrating an example of a circuit configuration of the HDMI source device101caccording to the second embodiment. The HDMI source device101ccorresponds to the HDMI source device101explained in the first embodiment. Thus, inFIG. 14, portions operating in the similar manner to those explained in the first embodiment are referred to by the common symbols, respectively.

A TMDS signal driving module401cincludes a DC component compensation circuit620having the similar configuration to that of the DC component compensation circuit601, in addition to the respective configuration of the TMDS signal driving module401explained inFIG. 9of the first embodiment. The DC component compensation circuit620has a function of, together with the DC component compensation circuit601explained in the first embodiment, correcting the DC component of each of the single ended signals (the positive (+) side signal and the negative (−) side signal of the differential signal line) of the differential signal outputted to the Ch0 transmission line304.

The DC component compensation circuit601is connected to the switch502,503side when seen from the capacitors512,513. This DC component compensation circuit corrects the levels of the single ended signals (the positive (+) side signal and the negative (−) side signal of the differential signal line) of the differential signal supplied to the differential signal line (internal signal line) within the HDMI source device101cby using the current source1and the switches501,503to thereby generate signals S1+ and S1−, respectively. On the other hand, the DC component correction circuit620is connected to the HDMI cable side when seen from the capacitors512,513of the differential signal line (internal signal line). In other words, the DC component correction circuit601is connected to the one sides of the capacitors512,513and the DC component correction circuit620is connected to the other sides of the capacitors512,513. The DC component compensation circuit620supplies predetermined driving currents to the signals S1+, S1− passed through the capacitors512,513to thereby generate signals S1+A, S1−A, respectively. These signals S1+A, S1−A are outputted to the HDMI cable which is connected to the differential signal line (internal signal line) within the HDMI source device101c.

Each of the DC component compensation circuits601,620is supplied with the H-Sync, V-sync and the DE which are inputted into the TMDS transmitting module104. The DC component compensation circuits601and620switch the driving currents to be applied to S1+, S1− and S1+A, S1−A at the timings based on the signals inputted thereto, respectively. Although configuration similar to this configuration is added to each of the TMDS signal driving modules402,403, the description thereof is omitted. InFIG. 14, although the HDMI sink device201is not illustrated, the HDMI source device101is also connected to the HDMI sink device201inFIG. 14.

As explained in the first embodiment, the DC component compensation circuit601contains the logic circuit602, the current source603, the current source604, the current source605and the current source606, and the switch607, the switch608, the switch609and the switch610etc. which perform the ON/OFF switching of the currents from these current sources, respectively. The logic circuit602switches the currents of the current sources in accordance with the states (state 0 to state 3) of the input control signals H-Sync, V-Sync and DE to thereby perform the compensation of the first compensation level illustrated inFIG. 15with respect to the respective levels of the single ended signals (the positive (+) side signal and the negative (−) side signal of the differential signal line) supplied to the differential signal line from the current source1via the switches502and503. The current value of each of the current source603, the current source604, the current source605and the current source606is I2.

The current values switched by the switches607and608are combined and added to an amount of the current from the current source504which is ON/OFF switched by the switch502. Then the resultant current is converted into a voltage by the resistor510and the voltage drives the positive (+) terminal of the Ch0 transmission line304of the HDMI cable through the capacitor512. Further, the current values switched by the switches609and610are combined and added to an amount of the current from the current source504which is ON/OFF switched by the switch503. Then, the resultant current is converted into a voltage by the resistor511and the voltage drives the negative (−) terminal of the Ch0 transmission line304of the HDMI cable through the capacitor513.

The DC component compensation circuit620has the similar configuration as the DC component correction circuit601. This DC component correction circuit includes the logic circuit622, the current source623, the current source624, the current source625and the current source626, and the switch627, the switch628, the switch629and the switch630etc. which perform the ON/OFF switching of the currents from these current sources, respectively. The logic circuit622switches the currents of the current sources in accordance with the states (state 0 to state 3) of the input control signals H-Sync, V-Sync and DE to thereby perform the correction of the second correction level illustrated inFIG. 15with respect to the respective levels of the signals passed through the capacitors512and513. The current value of each of the current source623, the current source624, the current source625and the current source626is I3.

The current values switched by the switches607and608are combined and added to the signal S1+ passed through the capacitor512, and the resultant signal (S1+A) drives the positive (+) terminal of the Ch0 transmission line304of the HDMI cable. Further, the current values switched by the switches629and630are combined and added to the signal S1− passed through the capacitor513, and the resultant signal (S1−A) drives the negative (−) terminal of the Ch0 transmission line304of the HDMI cable.

FIG. 15is a view illustrating the compensation levels performed by the DC component compensation circuits601and620. The first compensation level is the correction level performed by the DC component compensation circuit601and the second compensation level is the compensation level performed by the DC component compensation circuit620.

When the ratio of the number of the logic 1 to the number of the logic 0 within 10 bits of the TMDS signal (bit serial data) inputted into the TMDS signal driving module401cis 5:5 (states 0 and 1), the DC component compensation circuit601reduces the levels of the DC components of the TMDS signals inputted into the differential signal line by 5% to thereby generate the S1+ and S1−, respectively. In this case, the DC component compensation circuit620reduces the levels of the DC components of the signals S1+ and S1− passed through the capacitors512and513by 5% to thereby generate the S1+A and S1−A, respectively.

When the ratio of the number of the logic 1 to the number of the logic 0 within 10 bits of the TMDS signal inputted into the TMDS signal driving module401cis 4:6 (state 2), the DC component correction circuit601does not compensate the levels of the DC components of the TMDS signals inputted into the differential signal line. That is, in this case, the TMDS signals inputted into the differential signal line become the S1+ and S1−, respectively. Then, the DC component correction circuit620reduces the levels of the DC components of the signals S1+ and S1− passed through the capacitors512and513by 10% to thereby generate the S1+A and S1−A, respectively.

When the ratio of the number of the logic 1 to the number of the logic 0 within 10 bits of the TMDS signal inputted into the TMDS signal driving module401cis 6:4 (state 3), the DC component compensation circuit601reduces the levels of the DC components of the TMDS signals inputted into the differential signal line by 10% to thereby generate the S1+ and S1−, respectively. In this case, the DC component compensation circuit620does not perform the level compensation.

FIG. 16Ais a circuit diagram for illustrating the concept of the basic operation ofFIGS. 14A and 14Baccording to the second embodiment.FIGS. 16B,16C, and16D are timing charts for illustrating the concept of the basic operation ofFIGS. 14A and 14Baccording to the second embodiment.

The circuit diagram illustrated inFIG. 16Ashows a part of the circuit relating to the negative (−) side of the differential signal line. Further, in the actual configuration, the resistor507(R2) pulling up the signal from the switch503to the AVcc corresponds to the resistor507(R2) pulled up to the AVcc505inFIG. 4. Also, the resistor R4pulled up to the AVcc2corresponds to the resistor511(R4) pulled up to the AVcc2509inFIG. 4. The resistor507(R2) and the resistor511(R4) are coupled via the capacitor513. The resistance value of each of the resistors507and511is 50Ω. Although this circuit differs from the actual circuit, this circuit can be explained simply in this manner since the signal band under consideration is the change of the DC component. However, the operation explained with reference toFIGS. 16A,16B,16C, and16D relates to the basic operational concept and contains a part different from the actual operation of the HDMI source device101c. The operation of the HDMI source device101cwill be explained later with reference toFIGS. 17A,17B, and17C.

The current source I2inFIG. 16Ais a representative one of the current sources2to5within the DC component correction circuit601inFIG. 14, and also the current source I3is a representative one of the current sources I3within the DC component correction circuit620inFIG. 14. In other words, I2represents the driving current outputted to the negative (−) side of the differential signal line from the DC component compensation circuit601, and I3represents the driving current outputted to the negative (−) side of the differential signal line from the DC component compensation circuit620.

FIG. 16Bshows the waveforms of the current sources I2and I3. In this figure, a section from a time point 0 to a time point t1represents the state 2, and a section from the time point t1to a time point t2represents the state 3. Further, in this figure, minus means the drawing current. During the time period 0˜t1˜t2, although I2is −2 mA during the time period from 0 to t1, I3is 0 or −2 mA during this time period. −2 mA corresponds to the 10% shown as the first compensation level and the second reduction level shown inFIG. 15, and also corresponds to 10% of the output value 20 mA of I1of the current source1inFIGS. 3,4and9. During the time period t1˜t2, each of I2and I3is 0.

FIG. 16Cshows the response waveforms at the S1− terminal and the S1−A terminal in the case where I2is −2 mA and I3is 0 during the time period from 0 to t1, and each of I2and I3is 0 during the time period from t1to t2. That is, this figure represents the waveforms in the case where the DC component correction circuit601is driven but the DC component correction circuit620is not driven. According to another point of view,FIG. 16Cshows the waveforms of the DC components in the case of performing the AC coupling without compensating the DC component likeFIG. 4although the signal amplitude differs therefrom. In other words, according to this point of view, the waveform S1−A ofFIG. 16Ccorresponds to the DC component waveform P14at the receiving terminal shown inFIG. 7, (4).

Supposing that the output state changes to the state 2 from the state 3 at the time point t=0, since I2changes from 0 mA to −2 mA at the time point t=0, the S1−A terminal waveform (steady line) at the time point t=0 becomes AVcc−2 mA×(resistance value of the parallel arrangement of R2and R4)=3.3V−2 mA×2.5Ω=3.3V−0.05V=3.25V. Then the S1−A terminal waveform (steady line) gradually approaches to AVcc=3.3V with time. The S1− terminal waveform (dotted line) at the time point t=0 becomes AVcc−2 mA×(resistance value of the parallel arrangement of R2and R4)=3.25V and gradually approaches to AVcc2−2 mA×50Ω=3.3V−100 mV=3.2V with time.

During the time period from t1to t2inFIG. 16C, since I2changes to 0 mA from −2 mA at the time point t=t1, the S1−A terminal waveform and the S1− terminal waveform gradually approach to the voltage AVcc and AVcc2, that is, 3.3V with time, respectively.

In the case where I2is 0 A and I3is −2 m A during the time period from 0 to t1, and each of I2and I3is 0 during the time period from t1to t2, the S1−A terminal waveform and the S1− terminal waveform in this case will be the S1− terminal waveform and the S1−A terminal waveform ofFIG. 16C, respectively. This is because the resistance value of R2is same as that of R4and the current value of I2is same as that of I3.

FIG. 16Dshows the response waveforms at the S1− terminal and the S1−A terminal in the case where I2is −2 mA and I3is −2 mA during the time period from 0 to t1, and each of I2and I3is 0 during the time period from t1to t2. In this case, each of the waveforms at the S1− terminal and the S1−A terminal becomes the sum of the S1−A voltage waveform and the S1− voltage waveform inFIG. 16C. That is, since the signals each having the same current value and the same waveform are simultaneously applied to the both terminals of the coupling capacitor, the voltages at the both terminals thereof become always same.

In this manner, the S1− waveform shown inFIG. 16Dis the objective waveform having the DC component same as the DC component (not appearing transient phenomenon), except for the offset level, at the time of the DC coupling at the S1− terminal in the timing chart (5) of the TMDS signal driving module inFIG. 5.

FIG. 17Ais a circuit diagram for illustrating an example of the operation of the HDMI source device shown inFIGS. 14A and 14Baccording to the second embodiment.FIGS. 17B and 17Care timing charts for illustrating the example of the operation of the HDMI source device shown inFIGS. 14A and 14Baccording to the second embodiment.

FIG. 17Ashows a part of the circuit configuration, in the configuration shown inFIG. 14, relating to the negative (−) side of the single ended signal line of the differential signal. Although a current source I0not shown inFIG. 14is added, this current source is supposed to output the DC component of the current of the TDMS signal inputted into the single ended signal line of the differential signal. In other words, the DC component P8of the S1− waveform inFIG. 7, (2) is equivalently represented as this current source.

FIG. 17Bis the timing charts showing the operations of the DC component compensation circuits601and620of this embodiment. These timing charts show the case where the section from the time point 0 to the time point t1represents the state 3, and the section from the time point t1to the time point t2represents the state 2.

I0represents the waveform of the DC component contained in the TMDS signal inputted into the negative (−) side of the differential signal line and the changing level thereof is 20% as also shown inFIG. 7, (2). In these timing charts, minus means the drawing current. Supposing that the peak value (PP value) of the TMDS waveform is 500 mVpp, the changing value 20% thereof corresponds to 100 mVpp. When this value is converted into a current value for driving the parallel arrangement of the resistors507(R2) and511(R4) having a composite resistance value of 25Ω, the absolute value of the level of the driving current of the current source I0becomes 100 mVpp/25Ω=4 mA. The current source I0changes the driving current value into either one of −2 mA and 2 mA, and the changing timing thereof is a timing where H-Sync changes, for example, as clear fromFIG. 7.

I2represents the waveform of the driving current outputted to the negative (−) side (single ended) of the differential signal line from the DC component compensation circuit601. That is, as shown by the first compensation level inFIG. 15, the DC component is not compensated in the state 2, whilst the DC component is reduced by 10% (50 mVpp) in the state 3. In other words, the DC component compensation circuit601supplies, to the negative (−) side of the differential signal line, the driving current of 0 mA during the time period from 0 to t1, and the driving current of −2 mA during the time period from t1to t2.

I0+I2represent the current waveform showing the DC component of the S1− signal inFIG. 14. This current waveform has a changing amount of 2 mApp in total from −2 mA to 0 mA.

I3represents the waveform of the driving current outputted to the negative (−) side (single ended) of the differential signal line from the DC component compensation circuit620. That is, as shown by the second compensation level inFIG. 15, the DC component is reduced by 10% (50 mVpp) in the state 2, whilst the DC component is not corrected in the state 3. In other words, the DC component compensation circuit620supplies, to the negative (−) side of the differential signal line, the driving current of −2 mA during the time period from 0 to t1, and the driving current of 0 mA during the time period from t1to t2.

FIG. 17Cshows the response waveforms at the S1− terminal and the S1−A terminal in the case where I0+I2is −2 mA and I3is −2 mA during the time period from 0 to t1, and each of I0, I2and I3is 0 during the time period from t1to t2. In this case, since the signals each having the same current value and the same waveform are simultaneously applied to the both pins of the capacitor, the voltages at the both pins of the coupling capacitor become always the same.

Each of the waveforms shown in the timing charts inFIG. 17Cis the objective waveform having the DC component same as the DC component (DC component in the case where the transient phenomenon at the time of the AC coupling does not appear), except for the offset level, at the time of the DC coupling at the S1− terminal in the timing chart (5) of the TMDS signal driving module inFIG. 5.

In this manner, in the HDMI source device101caccording to this embodiment, since the current waveform (I0+I2) having the DC component obtained by the first compensation and the current waveform (I3) subjected to the second compensation and having the same DC component as the aforesaid current waveform are applied to the both sides of the coupling capacitor, respectively, the differential signal having the DC component similar to that obtained at the time of the DC coupling can be outputted to the external device despite of performing the AC coupling.

In other words, according to the HDMI source device101c, the DC component compensation circuit601suppresses the level of the DC component originally contained in the TMDS signal to a half thereof, and the DC component compensation circuit620extends the level of the DC component thus suppressed by an amount corresponding to a half of the DC component originally contained in the TMDS signal

As a result, the transient of the DC component at the terminals S1+A and S1−A appeared inFIG. 7, (4) can be suppressed, and the waveform of the DC component at the time of the DC coupling appeared inFIG. 7, (3) can be obtained. In this manner, according to the configuration ofFIG. 14, despite of performing the AC coupling, the DC component level at each of the S1+A and S1−A terminals is almost the same as the DC component level at the time of performing the DC coupling. Thus, as compared with the case of not performing the compensation of the DC component (FIG. 4andFIG. 7, (4)) and the case of partially performing the compensation of the DC component (FIG. 9andFIG. 10), the signal transmission having no deterioration can be performed even with respect to the sink devices designed according to the DC coupling specification of the related art.

InFIGS. 17A,17B and17C, although the explanation is made as to the negative (−) side of the differential signal line, the HDMI source device101calso performs the similar correction as to the positive (+) side thereof. That is, when I0is imputed into the positive (+) side of the differential signal line, the DC component correction circuit601and the DC component compensation circuit620supply I2and I3to the positive (+) side of the differential signal line, respectively.

Further, inFIGS. 17A,17B and17C, although the explanation is made that the signals each having the same current value and the same waveform are simultaneously applied to the both terminals of the capacitor, the current values and the waveforms at the both terminals of the capacitor do not necessarily become the same since each of the sink device side resistor R2, the source device side resistor R4, and the current values I0, I2and I3varies. However, the degree of the coincidence of the current values and the waveforms at the both terminals of the capacitor may be such a degree that the sink device designed according to the DC coupling specification of the related art can perform the differential detection without causing error as to the differential signal outputted from the HDMI source device101c. To be more concrete, each of R4, I1, I2and I3has the variance of about 5% relatively due to the variance within the same LSI, and R2is permitted to have a variance of 35% according to the standard thereof. Thus, the current values at the both terminals of the capacitor cause the error of about 40% at the maximum, for example. The influence of the error will be explained as to the waveform in the following manner. That is, when there is the influence of the aforesaid error of 40% with respect to the peak value 100 mVpp of the rectangular waveform component shown inFIG. 16D, the rectangular waveform component becomes 60 mVpp. In other words, when there is the influence of the error of 40% with respect to the changing value 50 mVpp of the transient component shown inFIG. 16C, the rectangular transient component becomes 20 mVpp. This resultant transient component does not raise a practical problem. In short, even when the DC component compensation circuit601and the DC component compensation circuit620perform the correction with the driving voltage amounts shown inFIG. 15andFIG. 17Bin the case where there is the maximum error to be supposed, it is considered that there does not arise a practical problem.

Such a configuration may be incorporated that the DC component at the S1+A or S1−A terminal as the output terminal of the HDMI source device101cis automatically measured, and the correction amount due to the variances of the pull-up resistors R1, R2on the sink side having large variances is adjusted by automatically adjusting the current value of the current source I3(623to626) of the DC component compensation circuit620. In other words, the HDMI source device101cmay incorporate a circuit for detecting the DC component at the S1+A or S1−A terminal at the time of being coupled to the sink device and a circuit for controlling the current value of the current source I3of the DC component correction circuit620in accordance with the detected DC component so that the voltage difference between the both terminals of the capacitor becomes small. Alternatively, DC component compensation circuit620may incorporate the circuit for detecting the DC component.

While the embodiments of the present invention have been described, the embodiments are exemplary, and are not intended to limit the scope of the invention. The embodiments can be embodied in various types in addition to the above-described embodiments, and various omissions, substitutions and modifications thereof can be made without departing from the gist of the invention. The embodiments, modifications thereof, and combination of the embodiments are included in the scope of the appended claims and equivalent ranges thereof, similarly as being included in the scope or gist of the invention.