SEMICONDUCTOR DEVICE

Provide is a highly reliable semiconductor device in which stress generated in a semiconductor chip is reduced and an increase in thermal resistance is suppressed. The semiconductor device includes: a semiconductor chip including a first main electrode on one surface thereof and a second main electrode and a gate electrode on the other surface thereof; a first electrode connected to the one surface of the semiconductor chip via a first bonding material; and a second electrode connected to the other surface of the semiconductor chip via a second bonding material. The first electrode is a plate-shaped electrode and has a groove in a region overlapping with the semiconductor chip. The groove penetrates in a thickness direction of the first electrode and reaches an end portion of the first electrode when viewed in a plan view.

CLAIM OF PRIORITY

The present application claims priority from Japanese Patent application serial No. 2021-145310, filed on Sep. 7, 2021, the content of which is hereby incorporated by reference into this application.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device.

2. Description of the Related Art

With spread of power semiconductors worldwide, in semiconductor devices used for switching circuits and rectifier circuits, a mounting technique for various requirements such as a large current, high heat dissipation, and high reliability has been developed.

As the mounting technique of the power semiconductor, there is a double-sided mounting structure in which electrodes are provided on an upper surface and a lower surface of a semiconductor chip, and at least one electrode on both the upper surface and the lower surface is connected to an external electrode. Examples of the semiconductor chip having electrodes on the upper surface and the lower surface include a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), and the like.

The MOSFET includes a source electrode and a gate electrode on one surface thereof and a drain electrode on the other surface thereof.

The IGBT includes an emitter electrode and a gate electrode on one surface thereof and a collector electrode on the other surface thereof. A surface protective film is usually formed on an outer peripheral portion of either surface of a power semiconductor chip. The surface protective film is formed on a source electrode side in the MOSFET and on an emitter electrode side in the IGBT. In the case of the IGBT, if the IGBT includes a diode, the surface protective film is formed on either a P pole side or an N pole side.

As an example of such a semiconductor device having the double-sided mounting structure, JP-A-2014-107506 (Patent Literature 1) discloses a semiconductor module including a semiconductor chip including electrodes on both electrode surfaces, and a pair of module substrates each disposed on each electrode surface of the semiconductor chip and having a surface wiring layer including the electrode on a substrate surface, in which a groove is formed in the electrode of the surface wiring layer of the module substrate. Patent Literature 1 discloses an example in which a lattice-shaped groove is formed in a back surface wiring layer of the module substrate. Patent Literature 1 also describes an effect of reducing a thermal stress caused by a difference in thermal expansion coefficient of a material forming the module substrate.

JP-A-2007-173680 (Patent Literature 2) discloses a semiconductor device including a pair of metal electrodes provided such that inner surfaces thereof face each other and having heat dissipation, a semiconductor chip provided so as to be sandwiched between the two metal electrodes and electrically connected to inner surfaces of the two metal electrodes, ceramic insulating substrates each provided on an outer surface of each metal electrode and having heat dissipation, in which at least one of the pair of metal electrodes has a stacked structure in which a plurality of layers are stacked in ascending order of a thermal expansion coefficient from an outer surface side toward the inner surface side. Patent Literature 2 discloses an example in which a slit is provided in at least one of the pair of metal electrodes. Patent Literature 2 also describes an effect of reducing the thermal stress generated in the metal electrodes by the slit.

Since Pb has a low melting point and low elasticity, in the related art, a solder containing Pb as a main component has been widely used as a bonding material for the semiconductor device. However, in recent years, due to consideration for the environment, restrictions on the use of Pb have been tightened, and the development of Pb-free materials is being promoted. As the Pb-free materials, for example, a solder containing Sn as the main component such as Sn—Sb or Sn—Ag—Cu, or a bonding material that uses Cu or Ag and is sintered at a high temperature is generally used.

These Pb-free materials have higher elasticity than the solder containing Pb, and have a problem that the stress of the semiconductor chip increases due to heating and cooling in a bonding step.

In order to prevent the occurrence of cracks in the semiconductor chip, it is important to reduce stress. In particular, in the double-sided mounting structure which is often used in the power semiconductor, it is necessary to increase a joining area as much as possible in order to flow a large current, and stress tends to increase.

When the stress is reduced, a shape of the electrode to be bonded to the semiconductor chip is devised so as to reduce thermal deformation of the semiconductor chip at the time of solder connection. In general, the thermal deformation of the semiconductor chip can be reduced by reducing an area of the electrode bonded to the semiconductor chip. However, a heat transfer area between the semiconductor chip and the electrode becomes small, thermal resistance at the time of using a product increases, and heat dissipation performance decreases. Therefore, there is a problem of suppressing an increase in the thermal resistance while reducing the stress of the semiconductor chip in the bonding step.

In the semiconductor module described in Patent Literature 1, as shown inFIGS.4and9of Patent Literature 1, a substrate electrode (52) bonded to a gate electrode (30) is provided with a groove (55) having a thickness smaller than that of other portions, and a lattice-shaped groove (80) is formed in back surface wiring layers (70,71). However, the grooves (55,80) are not formed in substrate electrodes (51,61) bonded to a source electrode (31) and a drain electrode (32) in which an area of a bonded portion is large. Therefore, it is considered that an effect of reducing the thermal stress cannot be sufficiently obtained.

In the semiconductor device described in Patent Literature 2, since a slit (16) does not reach an end portion of a metal electrode as shown in FIGS. 7 and 8 of Patent Literature 2, when the semiconductor chip is bonded to the end portion without the slit, it is considered that the thermal stress transmitted to the semiconductor chip cannot be reduced in the vicinity of the end portion.

SUMMARY OF THE INVENTION

An object of the invention is to provide a highly reliable semiconductor device in which a stress generated in a semiconductor chip is reduced and an increase in thermal resistance is suppressed.

The invention is a semiconductor device including: a semiconductor chip including a first main electrode on one surface thereof and a second main electrode and a gate electrode on the other surface thereof; a first electrode connected to the one surface of the semiconductor chip via a first bonding material; and a second electrode connected to the other surface of the semiconductor chip via a second bonding material, in which the first electrode is a plate-shaped electrode and has a groove in a region overlapping with the semiconductor chip, the groove has a structure that penetrates in a thickness direction of the first electrode and has a shape that reaches an end portion of the first electrode when viewed in a plan view.

According to the invention, it is possible to provide a highly reliable semiconductor device in which the stress generated in the semiconductor chip is reduced and the increase in thermal resistance is suppressed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present disclosure relates to a structure of a semiconductor device, and particularly, to a technique effectively applied to a mounting structure of a power semiconductor for power control. The technique is particularly effective for the semiconductor device having a double-sided mounting structure.

Hereinafter, embodiments of the semiconductor device according to the present disclosure will be described in detail with reference to the drawings. The content of the present disclosure is not limited to the embodiments.

First Embodiment

FIG.1is a schematic vertical sectional view showing a semiconductor device according to a first embodiment.

A semiconductor device200shown inFIG.1is used as a rectifier element of an on-vehicle AC generator (alternator).

InFIG.1, the semiconductor device200includes an electronic circuit body100, a base2including a pedestal2aat an upper portion thereof, and a lead3including a lead header3aat a lower portion thereof. The electronic circuit body100has a rectifying function. A range covered by the electronic circuit body100is shown by a dotted line. The base2and the lead3are terminals through which the electronic circuit body100is electrically connected to an external circuit. Further, the pedestal2aand a part located on the upper portion of the base2, the lead header3aand a part located on the lower portion of the lead3, and the electronic circuit body100are covered and sealed with a mold resin5.

The electronic circuit body100includes a semiconductor chip1a(semiconductor chip), a capacitor1b,and a control circuit chip1c.In addition, the electronic circuit body100includes a lower electrode1g,an upper electrode1d(source block), and a lead frame1i.

The pedestal2aand the lower electrode1gof the electronic circuit body100are connected via a conductive bonding material4a.The lead header3aand the upper electrode1dof the electronic circuit body100are connected via a conductive bonding material4b.In the present specification, the lower electrode1gis also referred to as a “first electrode”, and the upper electrode1dis also referred to as a “second electrode”.

In the present embodiment, the semiconductor chip1ais a MOSFET. The MOSFET includes a drain electrode D and a source electrode S. InFIG.1, the drain electrode D is provided on a lower surface portion, and the source electrode S is provided on an upper surface portion. That is, the semiconductor chip1ahas the double-sided mounting structure. A surface of the semiconductor chip1aon a side where the drain electrode D is provided is referred to as a “first main surface” of the semiconductor chip1a,and a surface of the semiconductor chip1aon a side where the source electrode S is provided is referred to as a “second main surface” of the semiconductor chip1a.

The drain electrode D is connected to an upper surface portion of the lower electrode1g,which is a first internal electrode, via a conductive bonding material1p.However, when the conductive bonding material1pis not used, the drain electrode D may be connected by ultrasonic bonding or the like.

The source electrode S is connected to a lower surface portion of the upper electrode1d,which is a second internal electrode, via a conductive bonding material1q.However, when the conductive bonding material1qis not used, the source electrode S may be connected by ultrasonic bonding or the like.

The control circuit chip1cis connected to an upper surface portion of the lead frame1i,which is a support, via a conductive bonding material.

The capacitor1bthat supplies power to the control circuit chip1cis also connected to the upper surface portion of the lead frame1ivia the conductive bonding material. As the capacitor1b,for example, a ceramic capacitor can be used.

A lower surface portion of the lower electrode1gis exposed from a lower surface portion of the electronic circuit body100without being covered with the mold resin5. The lower surface portion of the lower electrode1gis connected to the pedestal2avia the conductive bonding material4a.

An upper surface portion of the upper electrode1dis exposed from an upper surface portion of the electronic circuit body100. The upper surface portion of the upper electrode1dis connected to the lead header3avia the conductive bonding material4b.

Materials of the conductive bonding materials1p,1q,4a,4b,and the like are commonly used solders, alloys containing Au, Ag, or Cu, conductive adhesive materials, and the like. As the solder, a general high-lead solder, a eutectic solder, a lead-free solder, and the like are used. As the conductive adhesive material, a material in which a metal filler such as Ag, Cu, or Ni is mixed with a resin, or a material composed only of metal is used. The materials of the conductive bonding materials1p,1q,4a,4b,and the like may be the same material or different materials. The conductive bonding materials1pand1qmay be form of the same material or different materials above and below the semiconductor chip1a.The conductive bonding materials4aand4bmay be formed of the same material or different materials above and below the electronic circuit body100.

As the materials of the base2, the lead3, and the lower electrode1g,the upper electrode1d,and the lead frame1iinside the electronic circuit body100, Cu having high thermal conductivity and excellent conductivity is mainly used, and CuMo, 42 alloy, Al, Au, Ag, or the like may be used. At this time, in order to improve connection stability, it is desirable to plate Au, Pd, Ag, Ni, or the like on a connection portion with the conductive bonding material.

The control circuit chip1cis electrically connected to the semiconductor chip1avia a wire1f.For example, when the semiconductor chip1ais a power MOSFET, the gate electrode formed on the semiconductor chip1aand the control circuit chip1care connected via the wire1f,and the control circuit chip1ccontrols a gate voltage of the power MOSFET. Accordingly, a large current can flow through the semiconductor chip1ahaving a switching function.

Further, the capacitor1bis electrically connected to the semiconductor chip1aand the control circuit chip1cby the lead frame1iand the wire1f.The capacitor1bhas a function of supplying power necessary for driving the control circuit chip1c.

The semiconductor chip1ahas a function of switching the large current. For example, the semiconductor chip (switching circuit chip)1ahaving the switching function is a semiconductor chip including an IGBT, a gate turn-off thyristor (GTO), and a power MOSFET. The semiconductor chip1ais a thyristor or the like that performs on/off control of the large current, and may be made of Si, SiC, SiN, GaAs, or the like.

The control circuit chip1cis a semiconductor chip that controls the semiconductor chip1athat switches the large current. The control circuit chip1citself is a semiconductor chip that does not include the semiconductor chip that switches the large current. That is, the control circuit chip1cis a semiconductor chip in which, for example, a plurality of logic circuits, analog circuits, driver circuits, and the like are provided, and a microprocessor and the like are formed as necessary. The control circuit chip1cmay also have a function of controlling a large current flowing through the semiconductor chip1a.

The semiconductor chip1a,the control circuit chip1c,the capacitor1b,the lower electrode1g,the upper electrode1d,and the conductive bonding materials1pand1qare entirely covered and sealed with a resin1h.Thereby, the electronic circuit body100is formed.

The lower surface portion of the lower electrode1gand the upper surface portion of the upper electrode1dare exposed to an outside of the electronic circuit body100without being covered with the resin1hof the electronic circuit body100.

Therefore, the upper surface portion of the upper electrode1dof the electronic circuit body100can be electrically connected to the lead header3avia the conductive bonding material4b.The lower surface portion of the lower electrode1gof the electronic circuit body100can be electrically connected to the pedestal2avia the conductive bonding material4a.

As described above, the electronic circuit body100is sealed with the resin1hand is integrally formed. An exposed portion of the lower electrode1gis electrically connected to the pedestal2aof the base2via the conductive bonding material4a.An exposed portion of the upper electrode1dis electrically connected to the lead header3aof the lead3via the conductive bonding material4b.The semiconductor device200is formed by covering the entire electronic circuit body100and a part of the base2and the lead3with the mold resin5.

The electronic circuit body100is reversed upside down at the time of manufacturing so that P and N polarities of the semiconductor device200can be switched.

As shown inFIG.1, it is desirable that the upper electrode1dconnected to the source electrode S of the semiconductor chip1ais thicker than the lower electrode1g.Here, increasing a thickness means increasing a length in a direction from the pedestal2ato the lead header3a.

Since a heat capacity of the upper electrode1dbecomes larger by increasing a thickness of the upper electrode1d,heat generated due to a loss when a current flows through the source electrode S can be absorbed on an upper electrode1dside. Accordingly, an increase in temperature of the semiconductor chip1acan be prevented.

By increasing the thickness of the upper electrode1d,the upper electrode1dcan be higher than the capacitor1b,and the upper electrode1dcan be connected to the lead header3aas a terminal of the electronic circuit body100.

FIG.2is an enlarged vertical sectional view showing the semiconductor chip1aofFIG.1and components located above and below the semiconductor chip1a.

As shown inFIG.2, the semiconductor chip1a(semiconductor chip) includes the drain electrode D (first main electrode) on a surface (one surface) on a lower electrode1gside, and a gate electrode C (not shown, seeFIG.3) and the source electrode S (second main electrode) on a surface (the other surface) on the upper electrode1dside. The semiconductor chip1aincludes a surface protective film L (guard ring) on an outer peripheral portion of a surface on a gate electrode C side.

The lower electrode1gis a plate-shaped electrode.

A surface of the semiconductor chip1aon a source electrode S side is connected to the lower surface portion of the upper electrode1dvia the conductive bonding material1q.A surface on a drain electrode D side is connected to the upper surface portion of the lower electrode1gvia the conductive bonding material1p.The conductive bonding materials1pand1qare also simply referred to as “bonding materials”. The conductive bonding material1pmay be referred to as a “first bonding material” and the conductive bonding material1qmay be referred to as a “second bonding material” so as to be distinguished from each other.

A length of the upper electrode1dis shorter than that of the semiconductor chip1a.Both an end portion of the upper electrode1dand an end portion of a connection portion between the upper electrode1dand the semiconductor chip1aare inside the semiconductor chip1a.An end portion of the lower electrode1gconnected to the semiconductor chip1ais located outside an end portion of the semiconductor chip1a.The lower electrode1gis provided with grooves T. The grooves T each penetrate in a thickness direction of the lower electrode1g.At least a part of the groove T of the lower electrode1goverlaps the semiconductor chip1a.The groove T can be formed by press working or etching.

In summary, the lower electrode1gis the plate-shaped electrode and has the groove T in a region overlapping with the semiconductor chip1a.

FIG.3is a plan view partially showing the electronic circuit body100ofFIG.1. A cross-section taken along a line A-A′ inFIG.3corresponds to the cross-section inFIG.2.

As shown inFIG.3, the semiconductor chip1a(semiconductor chip) includes the gate electrode C on the surface (the other surface) on the upper electrode1dside.

Four grooves T are provided along a longitudinal direction of the lower electrode1g,and each have a shape that reaches the end portion of the lower electrode1g.In other words, the grooves T penetrate in the thickness direction of the first electrode, and each have the shape that reaches the end portion of the first electrode when viewed in a plan view.

The grooves T provided in the lower electrode1greach an outer peripheral line G of the lower electrode1g(emphasized by a broken line inFIG.3). When the grooves T reach the end portion of the lower electrode1g,deformation of the semiconductor chip1adue to a thermal stress can be suppressed as described later.

Next, a method of manufacturing the electronic circuit body100, which is a component of the semiconductor device200, will be described.

First, the lower electrode1g,one conductive bonding material, the semiconductor chip1a,the other conductive bonding material, and the upper electrode1dare stacked in this order. The stacked layers are heated to melt the conductive bonding materials to form layers of the conductive bonding materials1pand1q.Then, the stacked layers are cooled to room temperature.

In a cooling step, thermal strain is generated in all of the upper electrode1d,the lower electrode1g,and the semiconductor chip1a.Since when the upper electrode1dand the lower electrode1gare Cu and the semiconductor chip1ais Si, respective thermal expansion coefficients are 16.8×10−6[K−1] and 2.4×10−6[K−1], the upper electrode1dand the lower electrode1gshrink more than the semiconductor chip1a.Accordingly, bending deformation occurs in the upper electrode1d,the lower electrode1g,and the semiconductor chip1a,and the thermal stress is generated in each member.

FIG.4is a partial vertical sectional view showing a semiconductor device having a structure of the related art.

InFIG.4, a portion corresponding to a region Y inFIG.2is enlarged and shown.

As shown inFIG.4, in the structure of the related art, a length of the lower electrode1gis longer than that of the semiconductor chip1a.The length of the upper electrode1dis shorter than that of the semiconductor chip1a.Therefore, the length of the conductive bonding material1pprovided between the lower electrode1gand the semiconductor chip1ais longer than that of the conductive bonding material1qprovided between the upper electrode1dand the semiconductor chip1a.

Since the lower electrode1gand the upper electrode1dshrink more than the semiconductor chip1aduring cooling, a force applied to the semiconductor chip1afrom the conductive bonding material1pis larger than a force applied to the semiconductor chip1afrom the conductive bonding material1q.Therefore, the semiconductor chip1aafter cooling has an upward-convex shape.

At a point p1shown inFIG.4, due to the bending deformation of the semiconductor chip1a,tensile stress of an arrow Tb is generated, and tensile stress of an arrow Tj is also generated from the conductive bonding material1pat the same time, so that the stress is concentrated at the point p1. When a highly rigid bonding material such as the lead-free solder or a sintered material is used for the conductive bonding materials1pand1q,the stress at the point p1increases, and a risk of cracking in the semiconductor chip1aincreases.

FIG.5is a partial vertical sectional view showing the semiconductor device according to the present embodiment.

InFIG.5, the portion corresponding to the region Y inFIG.2is enlarged and shown.

InFIG.5, the groove T is provided in the lower electrode1g.The groove T penetrates in the thickness direction of the lower electrode1g.By the groove T, the stress in regions D1and D2of the semiconductor chip1ais generated separately. Therefore, the stress is smaller than that of the structure of the related art. Accordingly, the stress at the point p1can be greatly reduced.

When the groove T does not penetrate, influence of a continuous portion of the lower electrode1gremains, so that an effect of reducing the stress generated in the regions D1and D2cannot be sufficiently obtained.

It is desirable that a width U of the groove T is wider than a thickness of the conductive bonding material1p.When the width U of the groove T is narrow, the conductive bonding material1pgets wet and spreads during manufacture, so that the groove T is filled with the conductive bonding material1p,and since the lower electrode1gis bonded between the regions D1and D2, the stress is transmitted through a bonding portion thereof. Such a configuration is not desirable because a stress reducing effect is lost.

By providing the groove T in the lower electrode1g,a highly reliable semiconductor device can be manufactured even when a highly rigid lead-free bonding material such as the lead-free solder or the sintered material is used as the conductive bonding material1p.

Further, by working out a position of the groove T, for example, aligning the groove T with the end portion of the upper electrode1din a vertical direction, a heat dissipation path of the semiconductor chip1acan be secured, and an increase in thermal resistance can be suppressed. In other words, it is desirable that the groove T is provided at a position overlapping with the upper electrode1d.In this case, it is desirable that the groove T and the semiconductor chip1aoverlap each other, and the upper electrode1doverlaps above the groove T.

Next, an effect of reducing the thermal stress and a change in the thermal resistance will be quantitatively described with reference toFIGS.6to8.

FIG.6is a vertical sectional view geometrically showing the same portion as the semiconductor device shown inFIG.5.

FIG.6shows the definitions of coordinates and parameters used when examining the thermal stress and the thermal resistance generated in the manufactured semiconductor chip1a.

InFIG.6, a direction parallel to an upper surface of the semiconductor chip1aand orthogonal to a longitudinal direction of the groove T is set as an x-axis. A distance from an end portion E-E′ (a right end of the upper electrode1dinFIG.6) of a connection surface of the upper electrode1dwith the semiconductor chip1ato the end portion of the semiconductor chip1ais set to W. A distance from the end portion E-E′ to a center line F-F′ of the groove T (an axis of symmetry of the width of the groove T in a lateral direction) is set to J. In order to examine the case where the position of the groove T is changed, J is used as a parameter. When the center line F-F′ of the groove T is closer to a center of the semiconductor chip1a(on a left side inFIG.6) than the end portion E-E′ of the upper electrode1d,J takes a negative value. Herein, a parameter normalized by dividing J by W is defined as X.

In the example shown inFIG.6, X=−0.4.

FIG.7is a graph showing an example of a result of estimating the thermal stress generated in the semiconductor chip1aby a finite element analysis. A horizontal axis is X, and a vertical axis is a normalized thermal stress G.

The material of the upper electrode1dand the lower electrode1gis Cu, and the material of the semiconductor chip1ais Si. The material of the conductive bonding material1pis a solder containing Sn as a main component, which is a general lead-free bonding material. X is changed in a range of −2 to 2. σ on the vertical axis is a value normalized by using, as a numerator, a thermal stress generated at the point p1(a stress concentration position) of the semiconductor chip1ainFIG.6, and using, as a denominator, a stress generated at the point p1when soft lead solder is used for the conductive bonding material1pin the structure of the related art shown inFIG.4. Therefore, in the figure, σ=1 is indicated by a symbol Pb. In the solder containing Sn as the main component, a content of Sn is larger than a content of any other metal element in the metal elements contained in the solder.

As shown inFIG.7, the stress becomes minimum when X is −0.4 and increases as X moves away from −0.4. When X is 0.3 and −1.2, the stress rises to the same level as the stress of the structure of the related art.

In summary, a distance from an end portion of a connection surface of the second electrode with the semiconductor chip to an end portion of the semiconductor chip is set to W, a distance from the end portion of the connection surface of the second electrode with the semiconductor chip to a center line of the groove T is set to J, and when J/W is defined as X, a position of the center line of the groove T satisfies the following Equation (1).

FIG.8is a graph showing an example of a result of estimating the thermal resistance by the finite element analysis. The horizontal axis is X, and the vertical axis is a normalized thermal resistance θ. X is changed in a range of −2 to 1. θ on the vertical axis is values obtained by normalizing the thermal resistances of the semiconductor device200shown inFIG.6using, as the denominator, the thermal resistance of the semiconductor device200including the electronic circuit body100of the structure of the related art shown inFIG.4. Therefore, inFIG.8, θ=1 is indicated by a symbol CS. Here, the thermal resistance is defined by an increment from an initial state of the heat amount calculated from the temperature distribution of the semiconductor device200in a steady state in which the semiconductor chip1aoperates and generates a predetermined heat generation amount. This is because it is considered that the larger this increment is, the smaller the heat dissipation to the outside is.

It can be seen fromFIG.8that the larger X is, that is, the closer the position of the groove T is to the end portion of the lower electrode1g,the larger the thermal resistance is. Therefore, in the range of X shown inFIG.8, it is desirable that the position of the groove T is located inside the lower electrode1gbecause the thermal resistance is suppressed to be low.

Considering the thermal stress shown inFIG.7and the thermal resistance shown inFIG.8, it can be seen that when X is −0.4, the thermal stress is the minimum and the thermal resistance is also suppressed to be low.

By providing the groove T at the position where X=−0.4 as shown inFIG.6, it is possible to suppress the concentration of the stress at the point p1and minimize the amount of deformation. Further, since the upper electrode1dis disposed directly above the groove T, it is possible to secure the heat dissipation path upward from the semiconductor chip1aand suppress the thermal resistance from the semiconductor chip1a.

In the present embodiment, the solder containing Sn as the main component is used as the conductive bonding material1p.Since the solder containing Sn as the main component has a high modulus of elasticity and a high thermal conductivity as compared with a solder containing Pb as the main component, it is considered that when the solder containing Sn as the main component is applied to the structure of the related art as shown inFIG.4, the stress generated in the semiconductor chip1aincreases and the thermal resistance decreases. Here, the stress needs to be considered, and by providing the groove T as in the present embodiment, the stress generated in the semiconductor chip1acan be suppressed to the same level as or less than that of the structure of the related art using the solder containing Pb as the main component. In the present embodiment, the thermal resistance is increased by providing the groove T, and since the solder containing Sn as the main component is used, the thermal resistance can also be suppressed. Even when another Pb-free bonding material such as a sintered metal using Cu or Ag is used, it is expected that the same tendency is qualitatively obtained when the elastic modulus of the Pb-free bonding material is higher than that of Pb and the thermal conductivity thereof is higher than that of Pb.

The effect of the present embodiment is not limited to X=−0.4.

FIG.9is a vertical sectional view partially showing the semiconductor device in which the position of the groove T is changed.

InFIG.9, the groove T is disposed such that the center line F-F′ of the groove T is located outside the end portions E-E′. That is, in the example, X=0.25. Also, in this example, it can be said that the groove T is provided at a position overlapping with the second electrode.

InFIG.9, since a region where the upper electrode1doverlaps is small just above the groove T, the heat dissipation path upward from the semiconductor chip1ais smaller than that when X=−0.4 shown inFIG.6, but the increase amount of the thermal resistance is small as shown inFIG.8.

It can be seen fromFIG.7that even if X=0.25 as in the example ofFIG.9, the stress can be the same as that of the structure of the related art. Therefore, the stress reducing effect can be obtained even when X=−0.4 cannot be realized due to the restrictions of the electronic circuit body100.

Next, the necessity that the groove T reaches the end portion of the lower electrode1gwill be described.

FIG.10is a plan view partially showing an electronic circuit body according to a comparative example.

InFIG.10, the grooves T do not reach the outer peripheral line G of the lower electrode1g.The configuration other than the grooves T is the same as that inFIG.3. The lower electrode1gis connected by an outer peripheral region H (a rectangle shown by a broken line in contact with the end portion of the lower electrode1ginFIG.10). Therefore, the stress generated on both sides of the outer peripheral region H is transmitted without being divided, and an effect of reducing the stress applied to the semiconductor chip1acannot be obtained. Therefore, thermal deformation of the semiconductor chip1atends to be large.

FIG.11is a graph showing a result of a thermal stress analysis obtained by comparing the embodiment shown inFIG.3with the comparative example shown inFIG.10. In both the embodiment and the comparative example, the solder containing Sn as the main component, which is the lead-free bonding material, is used. The vertical axis represents the normalized stress σ as inFIG.7. A stress when the lead solder is used for the conductive bonding material1pis used as the denominator when the stress is normalized.

As shown inFIG.11, the stress σ is as high as 1.48 in a comparative example Cm compared with 1.22 in an embodiment Ex. From this result, it can be seen that it is desirable that the groove T reaches the end portion of the lower electrode1g.

Second Embodiment

Next, a semiconductor device according to a second embodiment will be described with reference toFIGS.12to14.

FIG.12is a plan view partially showing an electronic circuit body according to the present embodiment.

InFIG.12, a width of the lower electrode1gis small, and an end portion Te thereof is located inside the semiconductor chip1a.The lower electrode1gis provided with the grooves T.

FIG.13is a cross-sectional view taken along a line B-B′ inFIG.12.

InFIG.13, the end portion of the lower electrode1gis located inside the semiconductor chip1a.

FIG.14is a partial vertical sectional view showing the vicinity of an end portion of the semiconductor chip according to the present embodiment.

As shown inFIG.14, the lower electrode1gis not bonded in the region D2located at the end portion of the semiconductor chip1a.Therefore, for example, when the lower electrode1gis thermally shrunk in a cooling process of a reflow step or a flow step, the end portion of the semiconductor chip1ais not subjected to the stress from the lower electrode1g.Accordingly, the stress at the point p1can be reduced.

A configuration in which the end portion of the lower electrode1gis located inside the end portion of the semiconductor chip1acan also be applied to the configuration in which the grooves T are provided. The stress at the point p1can be further reduced as compared with a configuration in which the grooves T are only provided in the lower electrode1g.

Third Embodiment

FIG.15is a plan view partially showing an electronic circuit body according to a third embodiment.

InFIG.15, grooves T that reach the end portion along the longitudinal direction of the lower electrode1gare provided, and grooves T2are provided in two of the four grooves T. The grooves T2are provided along the lateral direction of the lower electrode1g.The grooves T2are provided so as to communicate with the grooves T in the middle of the grooves T. In other words, the grooves T include branched grooves T2.

The configuration of the present embodiment is a configuration of the first embodiment shown inFIG.3with the grooves T2added.

With such a configuration, the thermal deformation of the semiconductor chip1ain both the longitudinal direction and the lateral direction of the lower electrode1gcan be suppressed, and the stress generated in the semiconductor chip1acan be further reduced.

FIG.16is a graph showing an effect of a configuration ofFIG.15. Conditions are similar to those inFIG.11.

As shown inFIG.16, the thermal stress σ of the present embodiment (Ex3) is 1.17, which is smaller than that of the first embodiment (Ex1). Therefore, if the grooves T2are added to the grooves T, an effect of further reducing the thermal stress can be obtained.

Hereinafter, the effects obtained by the semiconductor device of the present disclosure will be collectively described.

According to the semiconductor device of the present disclosure, it is possible to reduce the stress generated in the semiconductor chip, suppress the increase in the thermal resistance, and improve reliability.

Since the stress can be reduced, damage to the semiconductor chip can be prevented.

Since the increase in the thermal resistance can be suppressed, the failure of the semiconductor chip can be prevented.

Not only in a semiconductor device having a single-sided mounting structure but also in a semiconductor device having the double-sided mounting structure, it is possible to suppress the increase in temperature and prevent failure even if the current during use is increased.