Transistor device having asymmetric embedded strain elements and related manufacturing method

Semiconductor transistor devices and related fabrication methods are provided. An exemplary transistor device includes a layer of semiconductor material having a channel region defined therein and a gate structure overlying the channel region. Recesses are formed in the layer of semiconductor material adjacent to the channel region, such that the recesses extend asymmetrically toward the channel region. The transistor device also includes stress-inducing semiconductor material formed in the recesses. The asymmetric profile of the stress-inducing semiconductor material enhances carrier mobility in a manner that does not exacerbate the short channel effect.

TECHNICAL FIELD

Embodiments of the subject matter described herein relate generally to semiconductor devices. More particularly, embodiments of the subject matter relate to fabrication of semiconductor transistors having embedded strain elements.

BACKGROUND

The prior art is replete with different techniques and processes for fabricating semiconductor devices such as metal oxide semiconductor (MOS) transistors. In accordance with typical fabrication techniques, a MOS transistor is formed by creating a device structure on a semiconductor substrate, where the device structure includes a gate stack formed on a layer of semiconductor material, and source and drain regions formed in the semiconductor material to define a channel region under the gate stack. In addition, embedded strain elements (i.e., doped/undoped semiconductor material that strains the channel region) can be used to improve the performance of MOS transistors. In this regard,FIG. 1is a cross sectional view of a MOS transistor device structure100having such embedded strain elements102located within a layer of semiconductor material104.FIG. 1depicts MOS transistor device structure100at an intermediate stage in the overall fabrication process.

For maximum channel stress, it is desirable to locate the embedded strain elements as close to the edge of the gate region as possible. However, the minimum distance between doped embedded strain elements in the semiconductor material (near the channel region) is limited due to the out-diffusion of the doped species into the channel region. Such out-diffusion exacerbates the short channel effect (SCE) that occurs in MOS transistors fabricated using modern small scale process nodes, for example, 45 nm nodes and beyond. To better control SCE, MOS transistor device structure100employs embedded strain elements102having a symmetric and stepped profile, as shown inFIG. 1. In this regard, embedded strain elements102are symmetric relative to the channel region. The stepped profile results in a relatively narrow separation between the upper portions106of embedded strain elements102, and a relatively wide separation between the lower portions108of embedded strain elements102. This structure facilitates the realization of shallow junctions for better SCE control.

BRIEF SUMMARY

A semiconductor transistor device is provided with asymmetric stress-inducing regions. The device includes a layer of semiconductor material having a channel region defined therein, and a gate structure overlying the channel region. The device also includes recesses formed in the layer of semiconductor material and adjacent to the channel region. The recesses extend asymmetrically toward the channel region. The device also includes stress-inducing semiconductor material formed in the recesses.

The above and other aspects may be found in an embodiment of a semiconductor transistor device having a layer of semiconductor material, a gate structure overlying the layer of semiconductor material, a source region in the layer of semiconductor material, and a drain region in the layer of semiconductor material. The gate structure has a source sidewall and a drain sidewall, the source region includes a stress-inducing semiconductor material, and the drain region also includes the stress-inducing semiconductor material. The minimum distance between the stress-inducing semiconductor material of the source region and a projection of the source sidewall into the layer of semiconductor material is less than the minimum distance between the stress-inducing semiconductor material of the drain region and a projection of the drain sidewall into the layer of semiconductor material.

A method of fabricating a semiconductor transistor device is also provided. The method forms a gate structure overlying a channel region of a layer of semiconductor material, and forms a source-side spacer and a drain-side spacer adjacent sidewalls of the gate structure. The method also involves the implanting of ions of an amorphizing species at a tilted angle toward the source-side spacer and into the semiconductor material, using the gate structure and the spacers as an implantation mask to shadow the semiconductor material proximate the drain-side spacer, to form asymmetric amorphized regions in the semiconductor material. Thereafter, the method selectively removes the asymmetric amorphized regions, resulting in corresponding recesses in the semiconductor material, the recesses extending asymmetrically toward the channel region, and at least partially fills the recesses with stress-inducing semiconductor material.

DETAILED DESCRIPTION

For the sake of brevity, conventional techniques related to semiconductor device fabrication may not be described in detail herein. Moreover, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor based transistors are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well known process details.

The techniques and technologies described herein may be utilized to fabricate MOS transistor devices, including NMOS transistor devices, PMOS transistor devices, and CMOS transistor devices. Although the term “MOS device” properly refers to a device having a metal gate electrode and an oxide gate insulator, that term will be used throughout to refer to any semiconductor device that includes a conductive gate electrode (whether metal or other conductive material) that is positioned over a gate insulator (whether oxide or other insulator) which, in turn, is positioned over a semiconductor substrate.

The proximity of embedded stress-inducing regions for semiconductor transistor devices (such as in situ phosphorus-doped eSi:C in NMOS source/drain regions, or in situ Boron-doped eSiGe in PMOS source/drain regions) is limited by the diffusion length from the stress-inducing regions to the edge of the gate region. The diffusion length is determined by the type of species (e.g., phosphorus or boron), and the thermal treatment process (e.g., rapid thermal annealing). For maximum channel stress, it is desirable to locate the embedded stress-inducing regions as close to the gate region as possible. However, if the stress-inducing regions are too close to the gate edge, then the short channel effect (SCE) in the transistor device will be exacerbated, due to the deeper junctions related to the in situ phosphorus-doped eSi:C epitaxial source/drain or in situ boron-doped eSiGe epitaxial source/drain, resulting in performance degradation.

It has been discovered that the sensitivities of both the channel mobility and SCE to stressor proximity (i.e., proximity of the stress-inducing region to the gate region) are not equal on the source side and the drain side. It has been observed that the channel mobility is more sensitive to the proximity of the source side stressor than that to the drain side (closer source side proximity is preferred for high mobility), while the SCE is much more sensitive to the proximity of the stressor on the drain side than that to the source side (larger proximity to the drain side is required for better SCE). Therefore, it would be desirable to have a transistor device having a stress-inducing region on the source side that is relatively close to the gate region, compared to the stress-inducing region on the drain side. In other words, asymmetric stress-inducing regions, relative to their proximity to the gate region, is desirable to enhance device performance while reducing the SCE.

There are fundamental reasons why closer proximity to the source side is preferred than that to the drain side. First, from a channel mobility point of view, only the source side of mobility-enhancement contributes to the device performance gain, while the drain side mobility is essentially insensitive to the device performance. This is because, on the source side, the electric filed intensity is low and it takes higher carrier mobility to achieve the desired velocity (where velocity=mobility×field intensity), therefore, higher stress on the source side by closer proximity enhances device mobility and performance. However, on the drain side, since the field intensity has already exceeded velocity saturation, increasing stress on the drain side by closer proximity does not help device mobility and performance. Second, from an SCE point of view, only the drain side requires shallow junction (shallow junction is good for SCE), while the source side prefers a deeper junction to reduce source resistance and hence higher drive current. This is because only the drain side junction is reversely biased and a shallow drain side junction helps the gate to turn on the transistor off and on more efficiently (i.e., better SCE), while the source side of the junction is forward biased, it does not influence device short channel control.

The semiconductor transistor devices described herein employ a structure having asymmetric recesses with embedded strain elements flanking the gate region. The semiconductor device manufacturing process described herein is suitable for use with 45 nm node technology, 32 nm node technology, and beyond, however, the use of such node technologies is not a requirement. The manufacturing process creates asymmetric cavities having different profiles that extend toward the gate region, as generally depicted inFIGS. 2-4.

FIG. 2is a cross sectional view of a MOS transistor device structure200configured in accordance with a first exemplary embodiment. MOS transistor device structure200may ultimately take the form of an NMOS transistor device or a PMOS transistor device. The description of well known and conventional features and aspects of semiconductor transistor devices may be briefly summarized or omitted entirely without providing the well known details.

MOS transistor device structure200generally includes a layer of semiconductor material202, a gate structure204overlying semiconductor material202, and stress-inducing semiconductor material206/208. The semiconductor material202is preferably a silicon material as typically used in the semiconductor industry, e.g., relatively pure silicon as well as silicon admixed with other elements such as germanium, carbon, and the like. Alternatively, semiconductor material202can be germanium, gallium arsenide, or the like. Semiconductor material202can be either N-type or P-type, but is typically P-type, with wells of the appropriate type formed therein. Moreover, semiconductor material202may be part of a bulk semiconductor wafer, or it may be realized as a thin layer of semiconductor material on an insulating substrate (commonly known as semiconductor-on-insulator or SOI) that, in turn, is supported by a carrier wafer.

Gate structure204may include a gate insulator210, a gate electrode212overlying gate insulator210, and a contact area214. Gate insulator210can be formed from a layer of thermally grown silicon dioxide or a deposited insulator such as a silicon oxide, silicon nitride, or the like. Gate insulator210preferably has a thickness of about 1-10 nm, although the actual thickness can be determined based on the application of the transistor in the circuit being implemented. In accordance with one embodiment, gate electrode212is formed from doped polycrystalline silicon. Contact area214is preferably realized as a metal silicide area formed on gate electrode212.

Gate structure204includes two sidewalls: a source sidewall216that is proximate the source side of MOS transistor device structure200; and a drain sidewall218that is proximate the drain side of MOS transistor device structure200. The illustrated embodiment of MOS transistor device structure200includes a spacer220on source sidewall216and a spacer222on drain sidewall218. Spacers220/222are formed from a suitable dielectric material such as silicon oxide and/or silicon nitride, preferably silicon nitride.

MOS transistor device structure200includes a source region224and a drain region226in semiconductor material202. Source region224includes or is defined by stress-inducing semiconductor material206, and drain region226includes or is defined by stress-inducing semiconductor material208. For ease of description, it is assumed that the stress-inducing semiconductor material206defines the boundary of source region224, and that the stress-inducing semiconductor material208defines the boundary of drain region226.

MOS transistor device structure200also includes a channel region228defined in semiconductor material202. When biased properly, a conductive channel is formed in channel region228between source region224and drain region226, as is understood by those familiar with semiconductor transistor operation. As shown inFIG. 2, gate structure204is aligned with channel region228; gate structure204overlies channel region228. Channel region228is generally flanked by source region224and drain region226and, consequently, by stress-inducing semiconductor material206and208. For purposes of illustration and ease of description,FIG. 2shows the projection230of source sidewall216into semiconductor material202, and the projection232of drain sidewall218into semiconductor material202. These imaginary projections230/232may be considered reference boundaries for channel region228, although in reality channel region228need not defined as such.

During fabrication of MOS transistor device structure200, recesses are formed in the layer of semiconductor material202. These recesses (e.g., a source recess234and a drain recess236) are positioned adjacent and proximate to channel region228. After creation of the recesses, stress-inducing semiconductor material206is formed in source recess234, and stress-inducing semiconductor material208is formed in drain recess236. Accordingly, for purposes of this description, the boundaries of stress-inducing semiconductor material206, source region224, and source recess234correspond to one another, and the boundaries of stress-inducing semiconductor material208, drain region226, and drain recess236correspond to one another.

Notably, the recesses234/236(and stress-inducing semiconductor material206/208contained therein) extend asymmetrically toward channel region228relative to each other. In particular, source recess234(and, therefore, stress-inducing semiconductor material206) extends further toward channel region228than drain recess236(and, therefore, stress-inducing semiconductor material208). In other words, the minimum distance between stress-inducing semiconductor material206and projection230is less than the minimum distance between stress-inducing semiconductor material208and projection232. This asymmetric positioning of the stress-inducing semiconductor material takes advantage of the relatively low SCE sensitivity on the source side of MOS transistor device structure200, and the relatively high SCE sensitivity on the drain side of MOS transistor device structure200.

For this particular embodiment of MOS transistor device structure200, source recess234is shaped as a stepped recess having an upper portion238and a lower portion240. Source recess234is formed such that its upper portion238extends further toward channel region228than its lower portion240(i.e., upper portion238is closer to projection230than lower portion240). Again, because stress-inducing semiconductor material206follows the contour of source recess234, the upper portion of stress-inducing semiconductor material206extends further toward projection230than the lower portion of stress-inducing semiconductor material206.

Although not a requirement, drain recess236is also shaped as a stepped recess having an upper portion242and a lower portion244. Drain recess236is formed such that its upper portion242extends further toward channel region228than its lower portion244(i.e., upper portion242is closer to projection232than lower portion244). Again, because stress-inducing semiconductor material208follows the contour of drain recess236, the upper portion of stress-inducing semiconductor material208extends further toward projection232than the lower portion of stress-inducing semiconductor material208. Notably, the minimum distance between upper portion238(of source recess234and stress-inducing semiconductor material206) and projection230is less than the minimum distance between upper portion242(of drain recess236and stress-inducing semiconductor material208) and projection232.

In preferred embodiments, the stress-inducing semiconductor material206/208is a doped silicon-based material, and stress-inducing semiconductor material206/208is formed by selectively epitaxially growing an in situ doped silicon material in recesses234/236. As used here, “in situ doped” means that a suitable dopant is introduced into a host material as that host material is grown. Epitaxially grown in situ doped silicon material is utilized here such that the material need not be subjected to ion implantation for purposes of doping.

For an NMOS transistor device, the in situ doped semiconductor material is an N-type semiconductor material, such as in situ phosphorus doped silicon carbon, or other materials that have a smaller lattice constant than silicon, such as a compound semiconductor, or the like. This results in a tensile longitudinal stress applied to channel region228and increased electron mobility. In contrast, for a PMOS transistor device, the in situ doped semiconductor material is a P-type semiconductor material, such as in situ boron doped silicon germanium, or other materials that have a greater lattice constant than silicon, such as a compound semiconductor, or the like. This results in a compressive longitudinal stress applied to channel region228and increased hole mobility. When fabricating CMOS devices, the recesses of PMOS devices will be masked during the growth of the epitaxial material for NMOS devices, and vice versa. The asymmetric profile of stress-inducing semiconductor material206and208enables the transistor device to strike a good balance between increased carrier mobility and SCE. In other words, the asymmetric profile achieves increased carrier mobility without exacerbating the undesired SCE.

FIG. 3is a cross sectional view of a MOS transistor device structure300configured in accordance with a second exemplary embodiment. MOS transistor device structure300shares many features and characteristics with MOS transistor device structure200and common features, characteristics, and aspects will not be redundantly described in detail here in the context of MOS transistor device structure300.

MOS transistor device structure300generally includes a layer of semiconductor material302, stress-inducing semiconductor material306for a source region324, stress-inducing semiconductor material308for a drain region326, and a channel region328. Stress-inducing semiconductor material306includes an upper portion338and a lower portion340; upper portion338extends further toward channel region328than lower portion340. Notably, stress-inducing semiconductor material308has a straight side profile that does not extend under spacer322. MOS transistor device structure300depicts a state after temporary spacers (used to create the recesses) have been removed and replaced with spacers320/322.

Stress-inducing semiconductor material308(on the drain side) has a relatively straight profile rather than a stepped profile. Nonetheless, the minimum distance between stress-inducing semiconductor material306and the projection330is still less than the minimum distance between stress-inducing semiconductor material308and the projection332. Accordingly, the benefits described above for MOS transistor device structure200can also be obtained using MOS transistor device structure300.

FIG. 4is a cross sectional view of a MOS transistor device structure400configured in accordance with a third exemplary embodiment. MOS transistor device structure400shares many features and characteristics with MOS transistor device structure200and common features, characteristics, and aspects will not be redundantly described in detail here in the context of MOS transistor device structure400.

MOS transistor device structure400generally includes a layer of semiconductor material402, stress-inducing semiconductor material406for a source region424, stress-inducing semiconductor material408for a drain region426, and a channel region428. Stress-inducing semiconductor material406includes an upper portion438and a lower portion440; upper portion438extends further toward channel region428than lower portion440. Similarly, stress-inducing semiconductor material408includes an upper portion442and a lower portion444; upper portion442extends further toward channel region428than lower portion444.

Notably, both upper portions438/442extend under their respective spacers420/422(in contrast, upper portion242of MOS transistor device structure200does not extend beneath spacer222). Stress-inducing semiconductor material406has a stepped profile, as described above for MOS transistor device structure200. Stress-inducing semiconductor material408has a similar stepped profile, however, its upper portion442does not extend toward channel region428as far as upper portion438of stress-inducing semiconductor material406. In other words, the minimum distance between stress-inducing semiconductor material406and the projection430is still less than the minimum distance between stress-inducing semiconductor material408and the projection432. Accordingly, the benefits described above for MOS transistor device structure200can also be obtained using MOS transistor device structure400.

FIGS. 5-12are cross sectional views that illustrate an exemplary MOS transistor device structure500and a method of fabricating it—MOS transistor device structure500may ultimately take the form of an NMOS transistor device or a PMOS transistor device. The illustrated process can be utilized to manufacture MOS transistor device structure200(seeFIG. 2). The description of well known and conventional steps related to the fabrication of semiconductor devices may be briefly summarized or omitted entirely without providing the well known process details.

Referring toFIG. 5, the fabrication process begins by forming a gate insulator material502overlying a layer of semiconductor material504. The semiconductor material504is preferably a silicon material as typically used in the semiconductor industry, e.g., relatively pure silicon as well as silicon admixed with other elements such as germanium, carbon, and the like. Alternatively, semiconductor material504can be germanium, gallium arsenide, or the like. Semiconductor material504can be either N-type or P-type, but is typically P-type. Moreover, semiconductor material504may be part of a bulk semiconductor wafer, or it may be realized as a thin layer of semiconductor material on an insulating substrate (commonly known as semiconductor-on-insulator or SOI) that, in turn, is supported by a carrier wafer.

Gate insulator material502can be a layer of thermally grown silicon dioxide or, alternatively (as illustrated), a deposited insulator such as a silicon oxide, silicon nitride, or the like. Deposited insulators can be deposited, for example, by chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), or plasma enhanced chemical vapor deposition (PECVD). Gate insulator material502preferably has a thickness of about 1-10 nm, although the actual thickness can be determined based on the application of the transistor in the circuit being implemented.

A layer of gate electrode material506is formed overlying gate insulator material502. In accordance with one embodiment, gate electrode material506is polycrystalline silicon. The layer of polycrystalline silicon is preferably deposited as undoped polycrystalline silicon and is subsequently impurity doped by ion implantation. The polycrystalline silicon can be deposited by LPCVD by the hydrogen reduction of silane. A layer of hard mask material (not shown), such as silicon nitride or silicon oxynitride, can be deposited onto the surface of the polycrystalline silicon. The hard mask material can be deposited to a thickness of about 50 nm, also by LPCVD.

The hard mask layer is photolithographically patterned and the underlying gate electrode material506and gate insulator material502are etched to form a gate structure (also referred to as a gate stack)508having a gate insulator510and a gate electrode512, as illustrated inFIG. 6. The polycrystalline silicon can be etched in the desired pattern by, for example, reactive ion etching (RIE) using a chlorine or HBr/O2chemistry and the hard mask and gate insulating material can be etched, for example, by RIE in a CHF3, CF4, or SF6chemistry.

Referring toFIG. 7, a layer514of dielectric material is conformally deposited overlying gate structure508. The dielectric material is an appropriate insulator, such as silicon oxide and/or silicon nitride, preferably silicon nitride. The dielectric material can be deposited in a known manner by, for example, atomic layer deposition (ALD), CVD, LPCVD, semi-atmospheric chemical vapor deposition (SACVD), or PECVD. Layer514is deposited to a thickness so that, after anisotropic etching, spacers formed from layer514have a thickness that is appropriate for the subsequent ion implantation and etching steps described below. In typical implementations, the layer514of dielectric material is deposited to a thickness of about 5-50 nm.

The process continues, in accordance with an exemplary embodiment, with anisotropic etching of the layer514of dielectric material to form spacers516, as illustrated inFIG. 8. The layer514of dielectric material can be etched by, for example, RIE using a suitable etching chemistry. As shown, the resulting spacers516are formed such that they are adjacent to the sidewalls of gate structure508. The arrows inFIG. 8schematically represent the implantation of ions518at a tilted angle relative to the surface of semiconductor material504, and toward gate structure204. In particular, ions518are directed at an angle toward the source-side spacer516s.Gate structure508and spacers516are used as an implantation mask to shadow semiconductor material504that is proximate to the drain-side spacer516d.This facilitates the use of a single ion implantation step to amorphize semiconductor material504.

Notably, the ions518are of an amorphizing species having properties and characteristics that enable it to amorphize semiconductor material504. In other words, when the ions518are implanted into semiconductor material504, they alter or damage the normally regular and consistent crystalline lattice structure of semiconductor material504. For this particular embodiment, the species can be xenon (Xe), germanium (Ge), silicon (Si), or the like, which demonstrates an ability to amorphize silicon material in the manner described here.

The use of a tilted ion implantation technique is desirable to change portions of semiconductor material504into amorphized regions520having the desired shape, dimensions, and profile in semiconductor material504. In practice, the tilted angle and dosage of the ions518are controlled such that amorphized region520sextends under spacer516sand toward gate structure508, as shown inFIG. 8. In practice, the angle of incidence of ions518, relative to the surface of semiconductor material504, can be within the range of about 0-40 degrees, but will depend on the depth and width (under the spacer) of amorphization desired. The dosage of ions518may be within the range of 1013atoms/cm2to 1014atoms/cm2, but will depend on the depth and width (under the spacer) of amorphization desired. The tilted angle promotes amorphizing of semiconductor material504under spacer516ssuch that the end of amorphized region520sextends toward the channel region.

The shadowing caused by gate structure508and spacers516, along with the angle of ions518, causes slight offsetting of amorphized region520d, relative to spacer516d.In other words, amorphized region520d is spaced away from spacer516d, while amorphized region520sreaches (and actually extends under) spacer516s. The creation of such asymmetric amorphized regions520in this manner is important, for the reasons discussed below.

Although other fabrication steps or sub-processes may be performed after the formation of amorphized regions520(e.g., a breakthrough etch step to remove native oxide), this example continues with an etching step that selectively removes amorphized regions520, while leaving the remainder of semiconductor material504substantially intact. This etching step results in recesses522being formed in semiconductor material504, as shown inFIG. 9. Notably, the source recess522sand the drain recess522dextend asymmetrically toward the channel region. For this embodiment, the process employs an isotropic etch technique to etch away amorphized regions520. This isotropic etch step may utilize plasma etching with a chlorine based chemistry to achieve the desired shallow recess profile. As a result of this etch, source recess522sincludes a pocket524under spacer516s,and at least a portion of spacer516soverhangs pocket524(seeFIG. 9).

Although other fabrication steps or sub-processes may be performed after the formation of recesses522, this example continues by increasing the depth of recesses522. In accordance with the illustrated embodiment, selected portions of the semiconductor material504are further etched to increase the depth of recesses522. In this regard, a breakthrough etch may be followed by an anisotropic etch using, for example, a CF4based chemistry. Thus, semiconductor material504is directionally etched, using gate structure508and spacers516as a self-aligned etch mask, to deepen and extend recesses522(seeFIG. 10). This etching step is controlled to form stepped recesses526in semiconductor material504, where stepped recesses526have the desired overall depth. Stepped recess526d(on the drain side) is created by extending the depth of recess522dwhile also etching down the “shelf” portion between spacer516dand the edge of recess522d(seeFIG. 9). Notably, stepped recesses526are formed without any photolithography or etching steps related to the formation of additional spacers.

Although other fabrication steps or sub-processes may be performed after the formation of stepped recesses526, this example continues by at least partially filling stepped recesses526with a stress-inducing semiconductor material, preferably a doped silicon based material.FIG. 11shows stepped recess526after they have been filled with stress-inducing semiconductor material. In this embodiment, the stress inducing semiconductor material is formed by selectively epitaxially growing an in situ doped silicon material in stepped recesses526. As used here, “in situ doped” means that a suitable dopant is introduced into a host material as that host material is grown. Epitaxially grown in situ doped silicon material is utilized here such that the material need not be subjected to ion implantation for purposes of doping. As mentioned previously, for an NMOS transistor device, the in situ doped semiconductor material may be phosphorus doped silicon carbon, and for a PMOS transistor device, the in situ doped semiconductor material may be boron doped silicon germanium.

InFIG. 11, stress-inducing semiconductor material528represents the source region, while stress-inducing semiconductor material529represents the drain region. The embodiment depicted inFIG. 11employs a non-uniform doping profile for the stress-inducing semiconductor material528/529. For example, the deeper regions of the stress-inducing semiconductor material (identified by reference numbers528aand529a) may have relatively high doping, while the shallower regions of the stress-inducing semiconductor material (identified by reference numbers528band529b) may have relatively low doping. Such non-uniform doping can be controlled and achieved while the material is being epitaxially grown.

Although other fabrication steps or sub-processes may be performed at this time (e.g., thermal annealing, formation of additional spacers, etc.), this example continues by forming metal silicide contact areas530on the stress-inducing semiconductor material528/529. In addition, a metal silicide contact area532may be formed on polycrystalline silicon gate electrode512, as depicted inFIG. 12. It should be apparent thatFIG. 12depicts a device structure534after a number of known process steps have been performed. For the sake of brevity, these intermediate steps will not be described in detail. In practice, an appropriate silicidation process is performed to create metal silicide contact areas530and532. For example, a layer of silicide-forming metal (not shown) is deposited onto the surfaces of stress-inducing semiconductor material528/529and onto the surface of gate electrode512. The silicide-forming metal can be deposited, for example, by sputtering to a thickness of about 5-50 nm and preferably to a thickness of about 10 nm. The wafer is then heated, for example by rapid thermal annealing, to form metal silicide contact areas530and532. The silicide-forming metal can be, for example, cobalt, nickel, rhenium, ruthenium, or palladium, or alloys thereof. Any silicide-forming metal that is not in contact with exposed silicon does not react during heating and, therefore, does not form a silicide. This excess metal may be removed by wet etching or any suitable procedure.

Thereafter, any number of known process steps can be performed to complete the fabrication of the MOS transistor device. For the sake of brevity, these process steps and the resulting MOS transistor device are not shown or described here. A MOS transistor device can be manufactured in this manner such that it has stepped recesses for strain elements, without having to carry out the additional process steps associated with the conventional process.

Referring back toFIG. 4, the stepped profile of stress-inducing semiconductor material408(on the drain side) can be created using tilted ion implantation directed toward the drain side of gate structure508, similar to that described above with reference toFIG. 8. However, the tilted angle and dosage of the ions will be selected such that the amorphized source-side region and the amorphized drain-side region are asymmetric. In other words, the amorphized source-side region will extend further toward the channel region than the amorphized drain-side region. Ultimately, the asymmetric amorphized regions will facilitate the creation of the asymmetric stress-inducing regions as depicted inFIG. 4.