METAL-INSULATOR-METAL DEVICE WITH HIGH-K LAYER CAPPING STRUCTURE

A metal-insulator-metal (MIM) device includes a first metal, a first cap layer disposed on the first metal, an insulator layer disposed on the first cap layer, a second cap layer disposed on the insulator layer, and a second metal disposed on the second cap layer. The first and second cap layers each comprise a dielectric material having a tetragonal crystal phase. In some embodiments, the tetragonal phase percentage of the cap layers is at least 80%. In some embodiments, the insulator layer is a ferroelectric material, such as Hf1-xZrxO2 with an orthorhombic phase percentage of at least 70%. In some such embodiments, the cap layers are ZrO2 or Hf1-xZrxO2 with a higher Zr fraction than the insulator layer. In some embodiments, the cap layers are doped with a dopant that causes the tetragonal phase percentage of the cap layers to be at least 80%.

BACKGROUND

The following relates to metal-insulator-metal (MIM) devices, the integrated circuit (IC) arts, ferroelectric device arts, and related arts.

DETAILED DESCRIPTION

The term “about” can be used to include any numerical value that can vary without changing the basic function of that value. When used with a range, “about” also discloses the range defined by the absolute values of the one or two endpoints, e.g., “about 0.2 nanometers to about 5nanometers” also discloses the range “0.2 nanometers to 5 nanometers”, and similarly the range “at least about 25% lower” also disclosed the range “at least 25% lower”. The term “about” may refer to plus or minus 10% of the indicated number.

Metal-insulator-metal (MIM) devices are used in various integrated circuit (IC) designs. The basic MIM structure includes an insulator layer sandwiched between first and second metal layers, and can for example serve as a capacitor for frequency filtering, noise reduction, DC isolation, or so forth. To provide the MIM structure with a high capacitance, it can be beneficial for the insulator layer to have a high dielectric constant. In a common notation, a high-k (or high-κ, or high relative permittivity ϵr) dielectric material is a dielectric material that has a dielectric constant κ(=Er) that is larger than the dielectric constant of silicon dioxide (SiO2, κ=3.9). The capacitance C of an MIM

structure is given by where K and t are the dielectric constant and thickness, respectively, of the insulator layer, and ϵ0is the permittivity of free space (i.e. vacuum). It can be seen that the capacitance C can thus be increased (for a given area A of the MIM) by reducing the thickness d of the insulator layer, and/or by increasing its dielectric constant κ, thus motivating toward MIM structures having a high-k insulator layer with reduced thickness d.

In some applications, the insulator layer of the MIM structure may be desired to be a ferroelectric material. For example, an MIM with a ferroelectric insulator layer can be used to implement a ferroelectric memory (i.e., storage) device. For example, an array of MIM devices with ferroelectric insulator layers and suitable transistor-based driving circuitry can thus serve as a compact ferroelectric memory array. A suitable high-k dielectric material that can be manufactured as a ferroelectric material is hafnium-zirconium-oxide (Hf1-xZrxO2), also denoted herein as HZO. The x in Hf1-xZrxO2denotes the zirconium fraction, and 0<x<1. The binary oxide ZrO2corresponds to x=1, and the binary oxide HfO2corresponds to x=0. The orthorhombic phase of HZO is non-centrosymmetric with oxygen atoms are arranged to be able to respond to form polarizations in response to external electric fields, thereby being capable of being switched by application of electric field between positive and negative polarization states. The ferroelectric behavior of the orthorhombic crystal phase of HZO is a consequence of its non-centrosymmetric crystal structure.

Performance of an MIM structure is commonly characterized by metrics such as the breakdown voltage (VBD), time-dependent dielectric breakdown (TDDB), and leakage (LK). The MIM structure performance by such metrics can degrade in response to thermal annealing of the MIM structure. Such annealing may however occur, for example due to high temperature processing performed after formation of the MIM structure, or annealing to induce orthorhombic crystallization in the case of an MIM structure intended to perform as a ferroelectric device.

In MIM structures and corresponding fabrication methods disclosed herein, such degradation is mitigated by use of capping layers with predominantly tetragonal crystal phase. As disclosed herein, such capping layers improve metrics of the MIM structure (e.g., TDDB, VBD, LK), and thus improve device yield. The capping layers with predominantly tetragonal crystal phase mitigate degradation of during annealing. In the case of ferroelectric MIM structures, the MIM structure is more robust against the orthorhombic crystallization anneal.

With reference toFIG.1, a side sectional view is shown of an MIM device according to a first embodiment. The MIM structure includes a first metal10, a first cap layer12disposed on the first metal10, a high-k insulator layer (HK layer)14disposed on the first cap layer12, a second cap layer16disposed on the HK layer14, and a second metal18disposed on the second cap layer16. In one suitable fabrication process (seeFIG.8), the order of formation is: formation of the first metal10; followed by formation of the first cap layer12; followed by formation of the HK layer14; followed by formation of the second cap layer16; followed by formation of the second metal18. Hence, the first metal10is also referred to herein as first metal10; the first cap layer12is also referred to herein as bottom cap layer12; the second cap layer16is also referred to herein as top cap layer16; and the second metal18is also referred to herein as top metal18. The use of “top” and “bottom” do not denote any particular spatial orientation.

The bottom metal10suitably comprise an electrically conductive material such as: titanium nitride (TiN); tantalum nitride (TaN); an elemental metal such as titanium (Ti), aluminum (Al), tungsten (W), platinum (Pt), molybdenum (Mo), or alloys thereof; or so forth. As shown by these nonlimiting illustrative examples, the term “metal” as used herein is not limited to elemental metals or alloys thereof: rather, the term “metal” as used herein also encompasses other materials commonly used as electrical conductors in the semiconductor industry, such as TiN or TaN. The top metal18also suitably comprises an electrically conductive material such as TiN, TaN, an elemental metal such as Ti, Al, W, Pt, Mo, alloys thereof, or so forth. The top metal18may be the same type of metal as the bottom metal10(e.g., both TiN); or alternatively the top metal18and the bottom metal10may be different types metals (e.g., the bottom metal10could be W while the top metal18could be TaN).

The top and bottom cap layers12and16each comprise a dielectric material that has a tetragonal crystal phase. For example, in some embodiments, the percentage of the top and bottom cap layers12and16that is in the tetragonal phase is at least80%; or said another way, the tetragonal phase percentage of the top and bottom cap layers12and16is at least 80%. In various embodiments, this can be achieved by suitable selection of the composition of the top and bottom cap layers12and16, or by suitable doping of the top and bottom cap layers12and16. The tetragonal phase has a unit cell with sides a, b, and c that are mutually orthogonal (i.e., mutually perpendicular), and with two sides (e.g., sides a and b) of equal length. If all three sides are of the same length (that is, a=b=c), then the tetragonal phase is more specifically a cubic phase. A cubic phase is also a tetragonal phase, that is, a cubic phase is an example of a tetragonal phase.

The insulator layer14comprises a high-k dielectric material, and hence is also referred to herein as an HK layer14. The insulator layer14has a dielectric constant κ (=ϵr) that is larger than the dielectric constant of silicon dioxide (SiO2, κ=3.9). In some nonlimiting illustrative embodiments, the insulator layer14is a high-k dielectric material with a dielectric constant κ in a range of 30≤κ≤40. In some nonlimiting illustrative examples, the insulator layer14has an orthorhombic phase percentage of at least 70%. In some nonlimiting illustrative embodiments, the insulator layer is a ferroelectric material (which in some cases is obtained by having an orthorhombic phase percentage of at least 70%). In some nonlimiting illustrative embodiments, the bottom cap layer12has a thickness dbot that is less than or equal to 0.1 times a thickness dHK of the insulator layer14

and the top cap layer16has a thickness dtopthat is less than or equal to 0.1 times the thickness dHKof the insulator layer14

An advantage of having

is that these relatively thin cap layers reduces the overall thickness of dielectric material disposed between the bottom metal10and the top metal18, thus keeping the total thickness d of the capacitance

low and hence keeping the capacitance C high.

In some embodiments, the cap layers12and16are made of the same high-k dielectric material as the HK layer14, albeit possibly with a different fractional composition, and/or with doping of the cap layers12and16to enhance the tetragonal phase percentage as described in some illustrative embodiments herein. For example, in one nonlimiting illustrative example the cap layers12and16and the HK layer14may all be made of hafnium zirconium oxide, with the same or different zirconium fractions.

Without being limited to any particular theory of operation, the bottom cap layer12is believed to improve the properties of the insulator layer14(e.g., TDDB, VBD, LK) by at least one or more of the following mechanisms. If the insulator layer14is a binary or ternary or quaternary oxide and the bottom cap layer12is also a (possibly different) binary or ternary or quaternary oxide, then the bottom cap layer12is believed to reduce defects in the insulator layer14caused by oxygen deficiencies or holes. The bottom cap layer12may also provide an improved crystallographic template for the subsequent formation of the insulator layer14, especially if the bottom layer12and the insulator layer14are made of materials with similar crystallographic structure (e.g., the bottom cap layer12being ZrO2or Hf1-xZrxO2and the insulator layer14being Hf1-xZrxO2, as a nonlimiting illustrative example). In some embodiments, the bottom cap layer12has a thickness of at least 0.4 nanometers to provide a stable and uniform film.

Without being limited to any particular theory of operation, the top cap layer16is believed to improve the properties of the insulator layer14(e.g., TDDB, VBD, LK) at least by protecting the insulator layer14during one or more thermal processes performed after formation of the MIM structure. For example, if the MIM structure is intended to be ferroelectric then these thermal processes could include an anneal to crystallize the insulator layer in a predominantly ferroelectric orthorhombic phase. In other examples, the one or more thermal processes could include elevated temperatures employed in depositing materials after formation of the MIM structure.

Because the bottom cap layer12and the top cap layer16perform different functions, it is contemplated for the bottom cap layer12and the top cap layer16to have different thicknesses, and/or for the bottom cap layer12and the top cap layer16to have different compositions. As just one nonlimiting illustrative example, in one embodiment the bottom cap layer12has a thickness of 0.4 nanometers and the top cap layer16has a thickness of 1.0 nanometers.

In operation, the MIM structure such as that ofFIG.1or other MIM structure embodiments herein can serve as a capacitor for frequency filtering, noise reduction, DC isolation, or so forth. In some embodiments, the MIM structure may be formed during back end-of-line (BEOL) processing of an IC chip, although it is not limited to this setting. The bottom metal10and top metal18serve as electrodes or plates of the capacitive MIM structure, while the insulator layer14(and secondarily the dielectric cap layers12and16) serve as the insulator structure of the MIM capacitor. In embodiments in which the insulator layer14is a ferroelectric material, the MIM structure can for example serve as a ferroelectric tunnel junction (FTJ), which can in turn, for example, serve as the storage element of a ferroelectric random access memory (FeRAM) that includes the FTJ and a transistor. The transistor can, for example, be a field-effect transistor (FET), and is suitably used to read and write bit values to the FTJ which serves as nonvolatile storage for the FeRAM.

With reference toFIG.2, an embodiment of an MIM structure is described which includes the bottom metal10, bottom cap layer12, top cap layer16, and top metal18, as previously described with respect to the embodiment ofFIG.1; and further includes the insulator layer14as previously described with reference toFIG.1but which in the embodiment ofFIG.2is specifically a ferroelectric insulator layer14FE. The ferroelectric insulator layer14FEcomprises a ferroelectric phase, such as a non-centrosymmetric orthorhombic phase with oxygen atoms arranged to be able to respond to form polarizations in response to external electric fields, thereby being capable of being switched by application of electric field between positive and negative polarization states. The ferroelectric behavior of such an orthorhombic crystal phase is a consequence of its non-centrosymmetric crystal structure. In some nonlimiting illustrative embodiments, the ferroelectric insulator layer14FEmay comprise an oxide selected from a group consisting of Hf1-xZrxO2, SrBi2Ta2O9, PbZrxTi1-x)3, or BaTiO3. In some embodiments, the insulator layer14FEcomprises a ternary or quaternary oxide having a ferroelectric orthorhombic phase whose phase percentage in the insulator layer14FEis at least 70%, the bottom cap layer12comprises the ternary or quaternary oxide doped with a dopant, and top cap layer16comprises the ternary or quaternary oxide doped with the dopant; in which the dopant causes a tetragonal phase percentage of the bottom cap layer12to be at least 80% and causes the tetragonal phase percentage of the top cap layer16to be at least 80%.

With reference toFIG.3, an embodiment of an MIM structure is described in which the insulator layer is a hafnium-zirconium-oxide (Hf1-xZrxO2) layer14HZO, the bottom cap layer is a bottom (or first) cap layer12Zr-richcomprising HZO with a higher zirconium fraction (i.e. larger value of x) than the HZO layer14HZO, and the top cap layer is a top (or second) cap layer16Zr-richcomprising HZO with a higher zirconium fraction (i.e. larger value of x) than the HZO layer14HZO. Put another way, the bottom and top cap layers12Zr-richand16Zr-richare HZO material that is zirconium-rich compared with the HZO layer14HZO. As previously noted, in some embodiments the bottom and top cap layers12Zr-richand16Zr-richeach have a thickness that is 1/10thor less than the thickness of the HZO layer14HZO.

With continuing reference toFIG.3and with further reference toFIG.4, it is explained why making the bottom and top cap layers12Zr-richand16Zr-richzirconium-rich compared with the HZO layer14HZOpromotes the desired crystalline structures of the respective layers.FIG.4diagrammatically shows the stable crystal structure as a function of zirconium fraction, ranging from x=0(the binary oxide HfO2) to x=1 (the binary oxide ZrO2). For the ternary compositions (HZO, where 0<x<1), these can be conceptually viewed as mixtures of HfO2and ZrO2. As diagrammatically shown inFIG.4, the stable crystal phase of ZrO2is a tetragonal crystal phase, while the stable crystal phase of HfO2is a monoclinic crystal phase. For intermediate values of the zirconium composition (i.e., intermediate mixtures of HfO2and ZrO2), the stable phase of the ternary oxide HZO is an orthorhombic phase.

The stable orthorhombic phase of HZO is non-centrosymmetric with oxygen atoms are arranged to be able to respond to form polarizations in response to external electric fields, thereby being capable of being switched by application of electric field between positive and negative polarization states. The ferroelectric behavior of the orthorhombic crystal phase of HZO is a consequence of its non-centrosymmetric crystal structure. On the other hand, by making the HZO more zirconium-rich, as shown inFIG.4, the stable crystal phase shifts to tetragonal. Hence, by employing a zirconium-rich HZO composition for the bottom and top cap layers12Zr-richand16Zr-rich, the bottom and top cap layers12Zr-richand16Zr-richcan be formed with a tetragonal phase percentage of at least 80%. The Zr fractions in the cap layers12Zr-richand16Zr-richand in the insulator layer14HZOto achieve the desired 80% or higher tetragonal phase percentage in the cap layers12Zr-richand16Zr-richand the desired 70% or higher orthorhombic phase (possibly after anneal) in the insulator layer14HZOis suitably determined by experimental test runs that are characterized by X-ray diffraction (XRD), electron backscatter diffraction (EBSD), or another characterization technique to assess the phase percentages of the layers. In some nonlimiting illustrative examples, a zirconium fraction x greater than about 20% is suitable to obtain the desired 80% or higher tetragonal phase percentage in the cap layers12Zr-richand16Zr-rich.

In this regard, the as-deposited HZO layer may be amorphous, or may have an undesirable mixture of crystal phases. In particular, the as-deposited insulator layer14HZOmay not have the desired 70% or higher orthorhombic crystal phase percentage. Hence, in some embodiments the formation of the layers of the MIM structure includes performing an anneal to crystallize the as-deposited insulator layer14HZOin a predominantly orthorhombic phase (e.g., orthorhombic phase percentage 70% or higher). The annealing is performed at a suitably high temperature for a sufficient time interval (e.g., ˜550° C. for about 5 minutes may be sufficient in some cases, as a nonlimiting illustrative example). Depending on the fabrication workflow of the IC containing the MIM structure, IC fabrication steps performed after forming the MIM device with the HZO insulator layer14HZOmay provide sufficient annealing to obtain the desired orthorhombic crystal phase of70% or higher, so that a dedicated anneal step for orthorhombic crystallization of the HZO may not be needed. XRD, EBSD, or other characterization methods can be performed on test runs with different anneal schedules to empirically determine a suitable anneal schedule for the insulator layer14HZO.

With reference toFIG.5, an MIM structure according to a further embodiment is similar to the MIM structure ofFIG.3. However, the MIM structure ofFIG.5replaces the zirconium-rich cap layers12Zr-richand16Zr-richof the embodiment ofFIG.3with a respective bottom (i.e., first) ZrO2cap layer12Zroand top (i.e., second) ZrO2cap layer16Zro. With reference back toFIG.4, this corresponds to the limiting case where the zirconium-rich cap layers are the binary oxide ZrO2(that is, zirconium fraction x=1).

With reference toFIG.6, experimental results are shown for an MIM structure substantially as shown inFIG.5, that is, including an HZO layer14HZOcapped by a bottom ZrO2cap layer12Zroand a top ZrO2cap layer16Zro.FIG.6plots the measured leakage (LK) of the MIM structure as a function of ZrO2thickness. As seen, the leakage decreases with increasing thickness of the ZrO2capping layers, thus demonstrating the effectiveness of the capping layers in improving leakage.

In the embodiments described with reference toFIGS.3-6, the stable tetragonal phase of the cap layers is obtained by making the cap layers zirconium-rich (or pure ZrO2in the case ofFIG.5). Advantageously, this can be achieved in some embodiments in a single deposition chamber in a continuous deposition process, by varying the ratio of the zirconium and hafnium precursors appropriately during the deposition (i.e., higher zirconium precursor/hafnium precursor ratio during the deposition of the zirconium-rich cap layers12Zr-richand16Zr-rich, and lower zirconium precursor/hafnium precursor ratio during the deposition of the insulator layer14HZO. For the embodiment ofFIG.5, the hafnium precursor may be shut off completely during deposition of the ZrO2cap layers12ZrOand16ZrO. The deposition chamber may, for example, be a chemical vapor deposition (CVD) chamber, a physical vapor deposition (PVD) chamber, or so forth. While using a single chamber to deposit both the cap layers and the HZO insulator layer14HZOcan be efficient from a manufacturing viewpoint, it is alternatively contemplated to employ different chambers for depositing the cap layers and the bulk HZO insulator layer14HZO, respectively.

With reference now toFIG.7, in some embodiments doping with a dopant is employed to obtain the bottom and top cap layers with the desired high (e.g. greater than or equal to 70%) tetragonal phase percentage. The MIM structure ofFIG.7is similar to that ofFIG.3, and includes the bottom metal10and top metal18sandwiching an HZO insulator layer14HZO. However, in the embodiment ofFIG.7, the bottom cap layer comprises a doped HZO cap layer12dthat is doped with a dopant that causes the tetragonal phase percentage of the bottom doped HZO cap layer12dto be at least 80%. Similarly, the top cap layer comprises a doped HZO cap layer16dthat is doped with a dopant that causes the tetragonal phase percentage of the top doped HZO cap layer16dto be at least 80%. The dopant used may, for example, be silicon (Si), germanium (Ge), aluminum (Al), yttrium (Y), scandium (Sc), gadolinium (Gd), or a combination thereof. Table1provides the stable phase of HZO predicted to be achieved by the minimum doping concentration (in percent) for these various dopants. As previously noted, the stable cubic phase obtainable using Y, Sc, or Gd is a specific example of a tetragonal phase. The minimum doping concentration values listed in Table 1 are theoretical estimates, and in practice lower concentrations (e.g., closer to about 5%-10%) may be sufficient to obtain the desired tetragonal phase for the bottom and top doped HZO cap layers12dand16d. XRD, EBSD, or other characterization methods can be performed on test runs with different doping levels for the bottom and top doped HZO cap layers12dand16dto empirically determine suitable doping levels for obtaining the desired tetragonal phase for these layers. Moreover, it is to be appreciated that Table 1 provides some illustrative suitable dopants, and other dopant species may be suitable for doping the doped HZO cap layers12dand16dto obtain the desired tetragonal phase. Furthermore, while described with reference to the example ofFIG.7in which the ferroelectric insulator layer14HZOis HZO and the bottom and top doped cap layers12dand16dare also HZO, more generally such doping can be used to obtain tetragonal bottom and top capping layers for MIM structures with other types of ferroelectric material, such as Hf1-xZrxO2, SrBi2Ta2O9, PbZrxTi1-xO3, or BaTiO3.

With reference now toFIG.8, a method of manufacturing an MIM structure such as the illustrative examples ofFIG.1-3,5, or7is presented by way of a flowchart. In an operation30, the bottom (or first) metal10is formed. In some embodiments, the bottom metal10may be deposited, for example, as an electrically conductive material such as TIN, TaN, an elemental metal (e.g., Ti, Al, W, Pt, Mo, et cetera), or alloys thereof. The bottom metal10may be formed, for example, by physical vapor deposition (PVD), atomic layer deposition (ALD), electrolysis, or another suitable technique. In some embodiments in which the MIM structure is fabricated during back end-of-line (BEOL) processing, the bottom metal10may comprise a patterned metallization layer of a metallization stack formed during the BEOL processing. In this case, the operation30may entail forming the patterned metallization by depositing a blanket metal layer on an underlying intermetal dielectric (IMD) material and applying photolithographically patterned etching to form the patterned metallization layer which includes the bottom metal10.

In an operation32, the bottom (or first) cap layer is formed, for example by PVD, ALD, chemical vapor deposition (CVD), or another suitable deposition technique. The detailed formation depends on the type of cap layer. For example, to implement formation of an MIM structure in accordance with the embodiment ofFIG.3, the bottom cap layer32is suitably formed by depositing HZO with a suitably high zirconium fraction as previously discussed with reference toFIG.3. To implement formation of an MIM structure in accordance with the embodiment ofFIG.5, the bottom cap layer32is suitably formed by depositing ZrO2. To implement formation of an MIM structure in accordance with the embodiment ofFIG.7, the bottom cap layer32is suitably formed as HZO doped with the tetragonal phase-inducing dopant.

In an operation34, the high-k insulator layer is formed. For example, to implement formation of an MIM structure in accordance with one of the embodiments ofFIG.3,5, or7, the insulator layer is suitably formed as an HZO layer14HZO, for example by PVD, ALD, CVD, or another suitable deposition technique.

In an operation36, the top (or second) cap layer is formed, for example by PVD, ALD, CVD, or another suitable deposition technique. As with the operation32, the detailed formation depends on the type of cap layer.

The operations32,34, and36may in some embodiments be performed by a single deposition technique (e.g., PVD, ALD, CVD, et cetera) using the same deposition tool (e.g., same PVD chamber, same ALD chamber, same CVD chamber, et cetera). In such embodiments, the implementation of the successive operations32,34, and36entails adjusting or switching on or off precursor flows appropriately. For example, to implement an MIM structure in accordance with the embodiment ofFIG.3, the zirconium precursor flow and/or hafnium precursor flow can be adjusted to control the zirconium fraction of each layer12Zr-rich,16HZO, and18Zr-rich. To implement an MIM structure in accordance with the embodiment ofFIG.5, the zirconium precursor flow can be turned off during deposition of the cap layers12ZrOand18ZrO. To implement an MIM structure in accordance with the embodiment ofFIG.7, the dopant precursor flow can be turned on during deposition of the bottom doped cap layer12d, then turned off for deposition of the HZO insulator layer14HZO, and the dopant precursor flow then turned back on for deposition of the top doped cap layer18d. Using a single deposition tool to perform the three operations32,34, and36has certain advantages such as workflow efficiency and minimizing the potential for surface contamination during wafer transport between deposition tools. However, it is also contemplated to perform the operations32,34, and36using two or even three different deposition tools.

In an operation38, the top (or second) metal18is formed. In some embodiments, the top metal18may be deposited, for example, as an electrically conductive material such as TiN, TaN, an elemental metal (e.g., Ti, Al, W, Pt, Mo, et cetera), or alloys thereof. The top metal18may be formed, for example, by PVD, ALD, electrolysis, or another suitable technique. In embodiments in which the MIM structure is fabricated during BEOL processing, the top metal18may comprise a second patterned metallization layer of the metallization stack formed during the BEOL processing. The bottom (or first) metal10formed in the operation30and the top (or second) metal18formed in the operation38may be formed of the same material, or may be formed of different materials.

With continuing reference toFIG.8, the MIM structure fabrication process may optionally include a thermal anneal40. For example, as previously discussed the formation of certain ferroelectric materials may include the thermal anneal40to crystallize the material (e.g., HZO) in the ferroelectric orthorhombic phase. If the thermal anneal40is performed, it may be a dedicated thermal anneal performed specifically to crystallize the insulator layer in the ferroelectric orthorhombic phase (e.g., so that post-anneal the orthorhombic phase percentage of the HZO insulator layer is at least 70% causing the HZO insulator layer to be ferroelectric). Alternatively, the thermal anneal40could be implemented by way of further processing performed after the operation38in the course of the overall IC fabrication workflow, which includes sufficient heating to perform the desired crystallization in the orthorhombic phase. For example, the thermal anneal40could comprise elevated temperature intervals used for depositing a subsequent layer (e.g. silicon nitride, an oxide insulator, or so forth), as one nonlimiting illustrative example. In general, the thermal anneal40may entail rapid thermal annealing (RTA), forming gas annealing, high pressure anneal (HPA), various combinations thereof, or so forth.

The illustrative MIM structures ofFIGS.1-3,5, and7include the bottom metal10, the bottom cap layer12,12Zr-rich,12ZrO, or12d, the insulator layer14,14FE, or14HZO, the top cap layer16,16Zr-rich,16ZrO, or16d, and the top metal layer18. However, the MIM structure may optionally include additional layers.

With reference toFIG.9, for example, an MIM structure is shown which is similar to the MIM structure ofFIG.1, including the bottom metal10, the bottom cap layer12, the insulator layer14, the top cap layer16, and the top metal layer18. However, the MIM structure ofFIG.9further includes a high-k buffer layer50interposed between the bottom metal10and the bottom cap layer12. The high-k buffer layer50may, for example, provide increased overall thickness of the total dielectric interposed between the metal layers10and18to increase the breakdown voltage (VBD) of the MIM structure. As a more specific example, if the insulator layer14is a ferroelectric layer and the high-k buffer layer50is a non-ferroelectric layer, this combination can provide a larger insulator thickness to increase VBD while keeping the ferroelectric layer14thinner to maintain high switching speed for the FTJ or other ferroelectric device.

As previously noted, in some embodiments the MIM structure may be formed during BEOL processing, for example serving as a BEOL capacitor or a FTJ formed in the BEOL processing.

With reference toFIGS.10and11, two illustrative embodiments by way of sectional view are shown of examples of incorporation of MIM structures into IC devices. A processed semiconductor wafer60is diagrammatically indicated. In front end-of-line (FEOL) processing, a silicon wafer is processed by steps such as dopant diffusion, epitaxy, etching, deposition, and/or so forth controlled by photolithographic patterning to form electronic devices (e.g., transistors, resistors, and so forth) in a silicon wafer, silicon-on-insulator (SOI) wafer, or other semiconductor substrate to form the processed semiconductor wafer60. Thereafter, the BEOL processing forms a metallization stack on the IC chip or wafer60. The BEOL processing typically entails an iterative process of depositing a blanket metal layer, performing photolithographic patterning on the blanket metal layer to form a patterned metallization layer, depositing intermetal dielectric material (IMD), and repeating to form each successive patterned metallization layer of the metallization stack.FIGS.10and11diagrammatically depict only a topmost metallization layer62of the metallization stack, with surrounding dielectric material64. This surface is suitably planarized, for example by chemical-mechanical polishing (CMP).

An under-bump metallization (UBM) is then formed to enable bonding the IC to another chip or to a printed circuit board (PCB) or other electrical or electronic component via a ball grid array (BGA). The UBM includes a dielectric layer66, with MIM structures70embedded in the dielectric material66. Vias72accessing the topmost patterned metallization layer62through the dielectric layer66are formed by etching via openings through the dielectric material66using photolithographically controlled etching and filling the via openings with electrically conductive material such as tungsten as a nonlimiting illustrative example. The MIM structures70are included to provide noise fluctuation suppression for signals passing through the UBM. The UBM further includes a redistribution layer (RDL)74and bonding pads75(one illustrated bonding pad75is shown in each ofFIGS.10and11) formed on the dielectric material66and coated with a further dielectric layer76and passivation layer78.

In the illustrative example ofFIG.10, an illustrative bonding bump (i.e., ball)80is shown bonded to the illustrative bonding pad75through a photolithographically defined etched opening in the dielectric and passivation layers76,78. An optional interfacing material82, such as a pre-solder, flux material, organic solderability preservative, or the like may be applied to the bonding pad75prior to attaching the bonding bump80. In a typical sequence, the bonding bump80comprises solder and is heated to form the bond.

The UBM of the example ofFIG.11is similar to that ofFIG.10, except that an additional polyimide layer84is formed on the passivation layer78. The polyimide layer84may, for example, serve as a solder mask or so forth.

It is to be appreciated that the illustrative noise fluctuation suppression application of the MIM structures of the examples ofFIGS.10and11is merely a nonlimiting illustrative example. More generally, the disclosed MIM structures can be employed in any application that utilizes an MIM structure, and the embodiments that employ a ferroelectric insulator layer may be employed in an FTJ, FE-RAM, or any other application of a ferroelectric MIM structure.

In the following, some further embodiments are described.

In a nonlimiting illustrative embodiment, a method of manufacturing a metal-insulator-metal (MIM) device is disclosed. The method includes: forming a first cap layer on a first metal, the first cap layer comprising a composition including at least zirconium and oxygen and having a tetragonal crystal phase; forming a Hf1-xZrxO2insulator layer on the first cap layer; forming a second cap layer on the Hf1-xZrxO2insulator layer, the second cap layer comprising a composition including at least zirconium and oxygen and having the tetragonal crystal phase; and forming a second metal on the second cap layer.

In a nonlimiting illustrative embodiment, a method of manufacturing a metal-insulator-metal (MIM) device is disclosed. The method includes: forming a first cap layer on a first metal, wherein the first cap layer comprises a dielectric material with a tetragonal phase percentage that is at least 80%; forming an insulator layer on the first cap layer; forming a second cap layer on the insulator layer, wherein the second cap layer comprises a dielectric material with a tetragonal phase percentage that is at least 80%; and forming a second metal on the second cap layer.

In a nonlimiting illustrative embodiment, a metal-insulator-metal (MIM) device includes: a first metal; a first cap layer disposed on the first metal, the first cap layer comprising a dielectric material having a tetragonal crystal phase; an insulator layer disposed on the first cap layer; a second cap layer disposed on the insulator layer, the second cap layer comprising a dielectric material having the tetragonal crystal phase; and a second metal disposed on the second cap layer.