Self-biased charge pump

An apparatus including: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node; a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal; a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node.

BACKGROUND

This invention relates generally to charge pump, and more specifically, to a self-biased charge pump for a phase-locked loop.

A phase-locked loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. The PLL is widely used in radio, telecommunications, computers and other electronic applications. They can be used to demodulate a signal, recover a signal from a noisy communication channel, generate a stable frequency at multiples of an input frequency, or distribute precisely timed clock pulses in digital logic circuits such as microprocessors.

The PLL may include a phase detector, a charge pump, a loop filter, a voltage-controlled oscillator (VCO), and a frequency divider. The VCO generates an output signal. The phase detector receives an input signal, compares the phase of the VCO-generated output signal with the phase of the input signal, and adjusts the VCO to keep the phases matched. The output of the phase detector also acts as a current source to pump current into and out of the loop filter by sending UP and DN signals to the charge pump to turn the charge pump on and off periodically. Since UP/DN current matching in a charge-pump is important to reduce noise and spur, the charge pump uses a replica bias branch for each of the UP circuit and the DN circuit. However, the replica bias branches add additional noise on the charge pump.

SUMMARY

The present disclosure provides for removing the replica bias branches, and using the main branch to calibrate the UP/DN current during off state.

In one embodiment, an apparatus is disclosed. The apparatus includes: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node; a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal; a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node.

In another embodiment, an apparatus is disclosed. The apparatus includes: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node; a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal; a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and a unity gain buffer having a positive input terminal, a negative input terminal, and an output terminal, the positive input terminal configured to receive an input signal, the negative input terminal coupled to the output terminal, wherein the output terminal is coupled to the output node, the first bias circuit and the second bias circuit.

In another embodiment, a phase-locked loop is disclosed. phase-locked loop includes: a phase detector configured to receive a reference signal and a divider output signal and output a control signal and a complementary control signal; a charge pump including: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node; a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal; a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node; a low pass filter configured to receive the current pulse train signal and output a control voltage; a voltage controlled oscillator configured to receive the control voltage and output a corresponding frequency signal; and a frequency divider configured receive the corresponding frequency signal and output the divider output signal for feedback to the phase detector.

Other features and advantages of the present disclosure should be apparent from the present description which illustrates, by way of example, aspects of the present invention.

DETAILED DESCRIPTION

Certain embodiments as described herein provide for removing the replica bias branches, and using the main branch to calibrate the UP/DN current during off state. Since the charge pump is turned on for a very short period of time due to a small phase error when the PLL is locked, the remaining time can be used by the main branch to calibrate the current. Since the main branch is used for the current calibration, there is no matching concern between the replica and main branches. The current matching is only determined by the loop gain. Further, the use of the main branch to calibrate the current results in the reduction of the low frequency noise of the main branch, which enables the use of smaller-sized transistors. The detailed description set forth below is intended as a description of exemplary designs of the present disclosure and is not intended to represent the only designs in which the present disclosure can be practiced. The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other designs. The detailed description includes specific details for the purpose of providing a thorough understanding of the exemplary designs of the present disclosure. It will be apparent to those skilled in the art that the exemplary designs described herein may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the novelty of the exemplary designs presented herein.

FIG. 1is a block diagram of a phase-locked loop (PLL)100, which includes a phase detector110, a charge pump120, a loop filter130, a VCO140, a frequency divider150, and a delta sigma modulator (DSM)160. The VCO140generates an output signal. The phase detector110receives a reference clock signal (fref) at its first input lead from a source such as a crystal oscillator. The phase detector110also receives the divider output signal (fv) at its second input lead. Using these signals, the phase detector110compares and adjusts the VCO140to keep the phases matched. The phase detector110further generates an up charge pump control signal (UP) and a down charge pump control signal (DN). The UP and DN signals are supplied to the charge pump120. Thus, the output of the phase detector110acts as a current source to pump current into and out of the loop filter130using the charge pump120by turning the charge pump on and off periodically. The frequency divider150divides the single-bit VCO output signal (fvco) by a multi-bit digital divisor value generated by the DSM160, and outputs the resulting divided-down single-bit feedback signal (fv) to the second input lead of the phase detector110.

FIG. 2is a schematic diagram of a charge pump200that is one embodiment of the charge pump120ofFIG. 1. InFIG. 2, the charge pump200includes a DN current mirror circuit240, UP current mirror circuit210, a DN replica bias circuit260, an UP replica bias circuit230, a DN current source228, and an UP current source258. The charge pump output node270outputs current pulse signal ICP. In general, a current mirror is a circuit block which functions to produce a copy of the current in one active device by replicating the current in another active device. An important feature of the current mirror is a relatively high output resistance which helps to keep the output current constant regardless of load conditions. Another feature of the current mirror is a relatively low input resistance which helps to keep the input current constant regardless of drive conditions.

The DN current mirror circuit240includes a DN bias circuit242, a DN switching current circuit244, and a capacitor246. The DN bias circuit242further includes an n-channel mirror transistor250and an n-channel switch transistor252. The gate terminal of the mirror transistor250is coupled to a DN bias node256. The gate terminal of the switch transistor252is controlled by the DN signal. The mirror transistor250and the mirror transistor254of the DN switching current circuit244form a current mirror. When the switch transistor252is turned on, the current flowing from supply node272, through current source228, and through the DN switching current circuit244, is mirrored onto the DN bias circuit242and current IDNflows from the output node270through the DN bias circuit242and to the ground node274.

The DN replica bias circuit260further includes a first n-channel transistor262and a second n-channel transistor264. Transistors262,264form a replica bias circuit because their geometries and layout are substantially identical to the transistors of the DN bias circuit242. Thus, the first transistor262has identical width and length dimensions as the mirror transistor250, and the second transistor (or switch transistor)264has identical width and length dimensions as switch transistor252. The gate terminal of the first transistor262is coupled to the bias node256of the current mirror circuit240. The gate terminal of the second transistor264is controlled by the signal DNB, which is a complementary signal to the signal DN. When the signal DNB is asserted high and the voltage at bias node256is sufficient to turn on the first transistor262, a replica current266flows from supply node272, through the first transistor262, through the second transistor264and to the ground node274.

The UP current mirror circuit210includes an UP bias circuit212, an UP switching current circuit214, and a capacitor216. The UP bias circuit212further includes a p-channel mirror transistor222and a p-channel switch transistor220. The gate terminal of the mirror transistor222is coupled to an UP bias node226. The gate terminal of the switch transistor220is controlled by the UPB signal, an inverted version of the UP signal. The UP switching current circuit214further includes a p-channel mirror transistor224. The gate terminal of the mirror transistor224is coupled to the bias node226. The mirror transistors222,224form a current mirror. When the switch transistor220is turned on, the current flowing from the supply node272through the UP switching current circuit214is mirrored onto the UP bias circuit212and current IUPflows from the supply node272, through the UP bias circuit212, and into the charge pump output node270.

The UP replica bias circuit230further includes a first p-channel transistor234and a second p-channel transistor232. The first transistor234and the second transistor232form a replica bias circuit because their geometries and layout are substantially identical to the transistors of the UP bias circuit212. Thus, the first transistor234has identical width and length dimensions as the mirror transistor222, and the second transistor (or switch transistor)232has identical width and length dimensions as the switch transistor220. The source terminal of the first transistor234is coupled to the drain terminal of the second transistor232, and the drain terminal of the first transistor234is coupled to ground node274. The gate terminal of the first transistor234is coupled to the bias node226of the current mirror circuit210. The source terminal of the second transistor232is coupled to supply node272. The gate terminal of the second transistor232is controlled by the UP signal. When the UP signal transitions from a high digital logic level to a low digital logic level, and the voltage at bias node226is sufficiently low to turn on the first transistor234, a replica current236flows from the supply node272, through the second transistor232, through the first transistor234and to the ground node274. AlthoughFIG. 2shows all transistors in the DN current mirror circuit240and the DN replica bias circuit260as n-channel metal oxide semiconductor field-effect transistors (MOSFETs), while all transistors in the UP current mirror circuit210and the UP replica bias circuit230as p-channel MOSFETs, the circuits210,230,240,260can be configured with any combination of n-channel and p-channel MOSFETs or other types of transistors.

In operation, when the DN signal goes high, the current IDNis made to flow through the DN bias circuit242. The magnitude of the current IDNis set by the current flowing through current source228. When the current flows through the DN current mirror circuit240, there are perturbations on the DN bias node256, and when the current stops flowing through the DN current mirror circuit240, there are other perturbations. By providing the DN replica bias circuit260that switches in an opposite fashion to the DN current mirror circuit240, where the transistors of the DN replica bias circuit260are replicas of corresponding transistors in the DN bias circuit242, the voltage disturbance caused by turning on the DN current mirror circuit240are counteracted by opposite voltage disturbances when the DN replica bias circuit260is turned off. Similarly, the UP replica bias circuit230tends to counteract voltage disturbances on the UP bias node226caused by switching the UP current mirror circuit210. Thus, the replica bias circuits260,230are provided to reduce the effect of these voltage disturbances on the bias nodes256,226. However, the replica bias branches add additional noise on the charge pump.

Accordingly, in some embodiments, the replica bias branches can be removed and the main branch is used to calibrate the UP/DN current. Since the charge pump is turned on for a very short period of time due to a small phase error when the PLL is locked, the remaining time can be used by the main branch to calibrate the current. Since the main branch is used for the current calibration, there is no matching concern between replica and main branch. The current matching is only determined by the loop gain. Further, the use of the main branch to calibrate the current results in the reduction of the low frequency noise of the main branch, which enables the use of smaller size transistors.

FIG. 3is a timing diagram300for different configurations of the charge pump in accordance with one embodiment of the present disclosure. The timing diagram300ofFIG. 3shows that when the UP/DN signal310transitions from a high digital logic level to a low digital logic level, Φ1 signal320is asserted to configure the charge pump into a main mode using the main branch. When the UP/DN signal310is at a high digital logic level and Φ1 signal320is not asserted, the charge pump is configured into an UP/DN current calibration mode (see330) using the IUP/DNcalibration branch. Further, when the charge pump is not in the main mode or the UP/DN current calibration mode, the charge pump is placed into an off mode as shown by Φ2 signal340. As stated above, the charge pump can use the main branch during this off mode (with Φ2 signal asserted) to further calibrate the UP/DN current.

FIG. 4is a schematic diagram of a charge pump400configured with replica branches (shown inFIG. 2) removed and the UP/DN current matched using a loop gain in accordance with one embodiment of the present disclosure. In various embodiments, the charge pump400is configured into a dynamic calibration circuit having a calibration loop using a Vtunesignal. In this configuration, the current matching is only determined by the loop gain. Further, dynamically calibrating the current provides improved PLL references spurs and reduced in-band charge pump noise.

InFIG. 4, the UP switching current circuit214, the UP current source258, the UP replica bias circuit230, and the DN replica bias circuit260shown inFIG. 2are removed. Thus, in the illustrated embodiment ofFIG. 4, the operational transconductance amplifier (OTA)410is used to calibrate the current at the UP bias node226. Further, switches450,452,420,426,428,430, a capacitor422, and a unity gain buffer440are used to configure the feedback signals Vtuneand fb, which are input to the OTA410. The unity gain buffer440is configured as a unity-gain voltage follower with a tuning voltage (Vtune) as an input. Switches450,452are controlled by UPB and DNB signals, respectively. Switches420,426are controlled by two complementary signals Φ1 andΦ1, respectively. As stated above, Φ1 signal is asserted when the UP/DN signal310transitions from a high digital logic level to a low digital logic level. Switches430,428are controlled by two complementary signals Φ2 andΦ2. As shown in the timing diagram ofFIG. 3, Φ2 signal is asserted when the charge pump is neither in the main mode (Φ1 signal asserted) nor in the UP/DN current calibration mode to further calibrate the UP/DN current during the off mode.

FIG. 5Ais a schematic diagram of a charge pump500configured into a main mode in accordance with one embodiment of the present disclosure. FromFIG. 4, the charge pump is configured into this mode by asserting Φ1 signal (andΦ2signal) and de-asserting Φ2 signal (andΦ1signal). That is, switches420and428are closed, while switches426and430are open. Switches450and452are also open. Accordingly, in this mode, the charge pump500outputs current at the output node270by controlling currents IUPand IDNusing UPB and DN signals received at the switch transistors220and252, respectively.

FIG. 5Bis a schematic diagram of a charge pump520configured into an UP/DN current calibration mode in accordance with another embodiment. FromFIG. 4, the charge pump is configured into this mode by de-asserting both Φ1 and Φ2 signals (and asserting bothΦ1andΦ2signal). That is, switches420and430are open, while switches426and428are closed. Switches450and452are also open. Accordingly, in this mode, the charge pump520is configured to calibrate the UP/DN current and the UP bias node226using the OTA410with the feedback of the output current at node270.

FIG. 5Cis a schematic diagram of a charge pump530configured into a current calibration mode using the main branch during the off state in accordance with another embodiment of the present disclosure. FromFIG. 4, the charge pump is configured into this mode by asserting Φ2 signal (andΦ1signal) and de-asserting Φ1 signal (andΦ2signal). That is, switches420and428are open, while switches426and430are closed. Switches450and452are also closed. Accordingly, in this mode, the charge pump530is configured to further calibrate the UP/DN current using a unity gain buffer440to compensate for the leakage of the mirror transistors222,250.

Although several embodiments of the present disclosure are described above, many variations of the present disclosure are possible. For example, although the illustrated embodiments described above configure the charge pump with transistors and capacitors, other elements such as buffers, operational amplifiers, and switches can be used to configure the charge pump. Further, features of the various embodiments may be combined in combinations that differ from those described above. Moreover, for clear and brief description, many descriptions of the systems and methods have been simplified. Many descriptions use terminology and structures of specific standards. However, the disclosed systems and methods are more broadly applicable.

Those of skill will appreciate that the various illustrative blocks and modules described in connection with the embodiments disclosed herein can be implemented in various forms. Some blocks and modules have been described above generally in terms of their functionality. How such functionality is implemented depends upon the design constraints imposed on an overall system. Skilled persons can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure. In addition, the grouping of functions within a module, block, or step is for ease of description. Specific functions or steps can be moved from one module or block without departing from the present disclosure.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention described in the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles described herein can be applied to other embodiments without departing from the spirit or scope of the present disclosure. Thus, it is to be understood that the description and drawings presented herein represent presently preferred embodiments of the present disclosure and are therefore representative of the subject matter which is broadly contemplated by the present disclosure. It is further understood that the scope of the present disclosure fully encompasses other embodiments that may become obvious to those skilled in the art and that the scope of the present disclosure is accordingly limited by nothing other than the appended claims.