Semiconductor device and method for controlling semiconductor device

A semiconductor device includes a main switching circuit implemented by a first semiconductor element and a second semiconductor element having a semiconductor region of a first conductivity type as a common region, including respectively a first well region of a second conductivity type and a second well region of a second conductivity type provided in an upper portion of the common region, the first semiconductor element being provided with a first source region of the first conductivity type in an upper portion of the first well region, the second semiconductor element being provided with a second source region of the first conductivity type in an upper portion of the second well region; and a drive circuit configured to independently apply a first drive signal and a second drive signal respectively to a control electrode of the first semiconductor element and a control electrode of the second semiconductor element.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. P2018-173583 filed on Sep. 18, 2018, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a control method of the semiconductor device, more particularly to a power semiconductor device which can be used for a main switching circuit for protection in an electric circuit and a control method of the power semiconductor device.

2. Description of the Related Art

JP 4178331 discloses that a bidirectional power switch is used for a power converter and the like. In a drive circuit for automotive electrical equipment, a semiconductor switch is provided on an upstream side in order to prevent damage to an electronic control unit (ECU), for example. When an abnormality occurs in the drive circuit, the drive circuit is blocked by the semiconductor switch to protect the ECU. In an electric circuit used for a vehicle and the like, since a battery could be accidentally connected inversely a demand for protection against damage to an ECU has increased.

A semiconductor switch in which power semiconductor elements, such as discrete n-type metal-insulator-semiconductor (MIS) transistors, are bidirectionally arranged, is conventionally used in order to prevent destruction of an electric circuit and the like. In such a conventional bidirectional semiconductor switch, a source electrode of a first MIS transistor is connected to a source electrode of a second MIS transistor. In the semiconductor switch, the first and second MIS transistors are in a conduction state in normal use so that a current flows from a drain electrode of the first MIS transistor to a drain electrode of the second MIS transistor. When a large current flows due to an abnormality caused in a load and the like, the first and second MIS transistors are turned off to prevent destruction of the load and the like. When discrete products, such as the MIS transistors and the like, are arranged in a planar manner to implement the semiconductor switch, it is difficult to reduce in size of the electric circuit due to an increase in mounting area.

JP 5990437 discloses a structure in which MIS transistors having a drain electrode in common are provided to form a bidirectional semiconductor switch into one chip. In the semiconductor switch, a current flows from a source electrode of the first MIS transistor to a source electrode of the second MIS transistor via the common drain electrode in normal use. Although the first MIS transistor is connected in a reverse direction, the first MIS transistor can be turned on by increasing the gate voltage. Further, since a body diode of the first MIS transistor is connected in a forward direction, a current can also flow via the body diode. In the case of abnormality in a load and the like or reverse connection of a battery, the first and second MIS transistors are turned off, so as to prevent destruction of the electric circuit or wires connected to a power supply via the semiconductor switch.

In the bidirectional semiconductor switch having the drain electrode in common, a parasitic bipolar transistor is formed in which the respective p-type well regions of the first and second MIS transistors serve as an emitter region and a collector region, and the common drain region serves as a base region. If a drive timing for turning on or turning off the respective first and second MIS transistors is deviated from each other, the parasitic bipolar transistor may operate to lead a decrease in reliability of the semiconductor switch.

SUMMARY OF THE INVENTION

An aspect of the present invention inheres in a semiconductor device, including: (a) a main switching circuit implemented by a first semiconductor element and a second semiconductor element having a semiconductor region of a first conductivity type as a common region, including respectively a first well region of a second conductivity type and a second well region of a second conductivity type provided in an upper portion of the common region, the first semiconductor element being provided with a first source region of the first conductivity type in an upper portion of the first well region, the second semiconductor element being provided with a second source region of the first conductivity type in an upper portion of the second well region; and (b) a drive circuit configured to independently apply a first drive signal and a second drive signal respectively to a control electrode of the first semiconductor element and a control electrode of the second semiconductor element.

Another aspect of the present invention inheres in a method for controlling semiconductor device which includes a main switching circuit implementing by an insulated gate first semiconductor element and an insulated gate second semiconductor element having a semiconductor region of a first conductivity type as a common region, including respectively a first well region of a second conductivity type and a second well region of a second conductivity type formed in an upper portion of the common region, the first semiconductor element being provided with a first surface electrode electrically connected to a power supply terminal on an upper surface of a first source region of the first conductivity type provided in an upper portion of the first well region, the second semiconductor element being provided with a second surface electrode electrically connected to an output terminal on an upper surface of a second source region provided in an upper portion of the second well region, the method encompassing: (a) applying a first drive signal to a control electrode of the first semiconductor element to control a turn-on and a turn-off of the first semiconductor element; and (b) applying a second drive signal, independent of the first drive signal, to a control electrode of the second semiconductor element to control a turn-on and a turn-off of the second semiconductor element, wherein the turn-on and the turn-off by the second drive signal are switched during the first semiconductor element is in the turn-on.

DETAILED DESCRIPTION

First and second embodiments of the present invention will be described below with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, the relationship between the thickness and the planar dimension, the ratio of the thickness of each device and each member, etc. may be different from the actual one. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. In addition, it should also be understood that the respective drawings are illustrated with the dimensional relationships and proportions different from each other.

In the following description, the terms relating to directions, such as “left and right” and “top and bottom” are merely defined for illustration purposes, and thus, such definitions do not limit the technical spirit of the present invention. Therefore, for example, when the paper plane is rotated by 90 degrees, the “left and right” and the “top and bottom” are read in exchange. When the paper plane is rotated by 180 degrees, the “left” is changed to the “right”, and the “right” is changed to the “left”. In the following description, the case where a first conductivity type is n-type and a second conductivity type is p-type will be exemplarily described. However, it is also possible to select the conductivity type in an inverse relationship so that the first conductivity type is p-type and the second conductivity type is n-type. In addition, the superscript “+” or “−” added to the mark “n” or “p” denotes that a semiconductor region has relatively high or low impurity concentration as compared with a region without the superscript “+” or “−” added. It should be noted that semiconductor regions denoted by the same mark, such as “p”, do not necessarily have exactly the same impurity concentration.

A “first or third main-electrode region” of each semiconductor element used in a main switching circuit of a semiconductor device denotes one of a source region and a drain region in a field-effect transistor (FET) or a static-induction transistor (SIT). A “second or fourth main-electrode region” denotes either the source region or the drain region which is not the first or third main-electrode region in FET or SIT. As above, when the “first or third main-electrode region” of each semiconductor element used in the main switching circuit is the drain region, the “second or fourth main-electrode region” denotes the source region. When the bias relationship is exchanged, in a symmetrically structured FET or the like, the function of the “first or third main-electrode region” and the function of the “second or fourth main-electrode region” may be exchanged. A “control electrode” denotes an electrode for controlling a main current flowing between the first main-electrode region and the second main-electrode region or between the third main-electrode region and the fourth main-electrode region. For example, in the FET or the SIT, a gate electrode for controlling a main current flowing between the source region and the drain region corresponds to the control electrode.

First Embodiment

A semiconductor device according to a first embodiment of the present invention includes a power circuit chip3and a control circuit chip5, as illustrated inFIG. 1. The power circuit chip3includes a main switching circuit1and a temperature sensor4. The main switching circuit1is a bidirectional switch including a first semiconductor element2aand a second semiconductor element2b, in which drain electrodes (first and third main electrodes) of the first and second semiconductor elements2aand2bare connected in common to each other in the opposite directions. A source electrode (a second main electrode) of the first semiconductor element2ais connected to a power source node12for power source (VCC) connection, and a source electrode (a fourth main electrode) of the second semiconductor electrode2bis connected to an output node13for output (OUT). The temperature sensor4detects a change in temperature due to a flow of current in the main switching circuit1.

The control circuit chip5includes a drive circuit6, an output circuit7, an overheat detection circuit8, a low-voltage detection circuit10, a logic circuit9, and an internal power supply11. The drive circuit6is connected to the respective gate electrodes (control electrodes) of the first and second semiconductor elements2aand2bto drive the first and second semiconductor elements2aand2b. The output circuit7is connected to the output node13to control the output of the main switching circuit1. The overheat detection circuit8acquires a temperature detected by the temperature sensor4so as to detect overheat in a load connected to the output node13caused by a short circuit and the like. The low-voltage detection circuit10detects a decrease in voltage of an external power source such as a battery connected to the power source node12. The logic circuit9is connected to the drive circuit6, the output circuit7, the overheat detection circuit8, and the low-voltage detection circuit10. The logic circuit9connects to an input node15for input (IN) of a signal and the like. The logic circuit9transmits a drive signal for the main switching circuit1to the drive circuit6. When overheat or a decrease in voltage is detected in the overheat detection circuit8or the low-voltage detection circuit10, the logic circuit9transmits a turn-off signal for the main switching circuit1to the drive circuit6. The internal power supply11supplies a power supply voltage to the logic circuit9. The respective wires for ground (GND) of the power circuit chip3and the control circuit chip5are connected to a ground node14.

The first and second semiconductor elements2aand2bare preferably semiconductor elements having an insulated gate structure, such as a MIS field-effect transistor (FET) and a MIS static-induction transistor (SIT). The first and second semiconductor elements2aand2bmay have a vertical structure or a horizontal structure. As can be understood from the following description, for the first and second semiconductor elements2aand2b, a vertical structure in which a main current flows in the depth direction of the chip may be desirable. Hereinafter, a description will be given by adopting a MISFET having a trench gate structure using silicon (Si) as the first and second semiconductor elements2aand2b. However, it will be obvious to those skilled in the art that the MIS transistor having a planar gate structure exhibit the same effectiveness from understanding the gist of the present invention from the following explanation. For a semiconductor material of the first and second semiconductor elements2aand2b, in addition to silicon (Si), a wide band gap semiconductor material, such as silicon carbide (SiC), gallium nitride (GaN), diamond, or aluminum nitride (AlN), which has a forbidden band width wider than Si of 1.1 eV may be used. Note that the MIS transistor is a concept including a MISFET and a MISSIT.

As illustrated inFIG. 1, a source S and a drain D of a MIS transistor Tr1of the first semiconductor element2aare respectively connected in antiparallel to an anode and a cathode of a body diode Di1. A drain D and a source S of a MIS transistor Tr2of the second semiconductor element2bare respectively connected in antiparallel to a cathode and an anode of a body diode Di2. The gate G of the MIS transistor Tr1and A gate G of the MIS transistor Tr2are connected to the drive circuit6independently of each other. The source S of the MIS transistor Tr2of the second semiconductor element2bis connected to an external load via the output node13.

An operation of driving the main switching circuit1by a control method according to the first embodiment will be given below with reference toFIG. 2toFIG. 4. As illustrated inFIG. 2, the source S of the MIS transistor Tr1of the first semiconductor element2ais connected to an external power supply22, such as a battery for a vehicle, and the source S of the MIS transistor Tr2of the second semiconductor element2bis connected to a load20such as an ECU. A voltage signal of a high (H) level equal to or higher than each threshold of the MIS transistors Tr1and Tr2is applied from the drive circuit6to each of the gates G of the MIS transistors Tr1and Tr2, so as to lead the MIS transistors Tr1and Tr2to be a turn-on state. In such case, a current flows from the external power supply22into the load20through the main switching circuit1, as indicated by the dotted line inFIG. 2. Although the source S and the drain D of the MIS transistor Tr1are connected in a reverse direction, the MIS transistor Tr1can be turned on by increasing the gate voltage. When an abnormality occurs in the load20and a large current flows, a voltage signal of a low (L) level lower than each threshold of the MIS transistors Tr1and Tr2is applied to each of the gates G of the MIS transistors Tr1and Tr2from the drive circuit6so as to turn off the MIS transistors Tr1and Tr2. Although the body diode Di1is in a turn-on state, the current can be turned off since the MIS transistor Tr2is in a turn-off state.

As illustrated inFIG. 3, the main switching circuit1according to the first embodiment includes the first semiconductor element2aand the second semiconductor element2b. A drift region50includes a common drain region51and a semiconductor region52of a first conductivity type (n-type) which is epitaxially grown on a top surface of the common drain region51. In the semiconductor region52, well regions53a,53b,54a,54bof a second conductivity type (p-type) and a channel stopper region55of p-type are formed. The first well region53aand the second well region53bserve as base regions. The third well region54aand the fourth well region54bserve as reduced-surface-field (RESURF) regions. Each depth of the first well region53a, the second well region53b, and the channel stopper region55from the top surface is substantially the same. Each depth of the third well region54aand the fourth well region54bfrom the top surface is greater than each depth of the first well region53aand the second well region53bfrom the top surface.

A first source region (a second main electrode region)57aof n+-type is formed on the top surface of the first well region53a, and a second source region (a fourth main electrode region)57bof n+-type is formed on the top surface of the second well region53b. A trench59ais provided in contact with the first source region57a, the first well region53a, and the semiconductor region52in order from the surface of the semiconductor region52, Also, a trench59bis provided in contact with the first source region57b, the first well region53b, and the semiconductor region52in order from the surface of the semiconductor region52, In the trenches59a, a gate electrode (control electrode)61ais buried via a gate insulating films60aprovided on an inner side wall and a bottom wall of the trench59aso as to implement an insulated gate electrode structure (60a,61a). Also, in a trench59b, a gate electrode (control electrode)61bis buried via a gate insulating film60bprovided on an inner side wall and a bottom wall of the trench59bso as to implement an insulated gate electrode structure (60b,61b). For each of the gate insulating films60aand60b, for example, a silicon oxide (SiO2) film may be used. For each of the gate electrode61aand61b, for example, a polysilicon film may be used. The upper portions of the first well regions53aand the second well region53bare provided with grooves from the surface of the semiconductor region52to reach the first well regions53aand the second well region53b, respectively. In the upper portions of the first well regions53aand the second well region53b, contact regions56aand56bof p+-type, having higher impurity concentration than the first well regions53aand the second well region53b, are provided in contact with the bottoms of the grooves, respectively. Source electrodes64aand64bare buried in the grooves via source contact layers63aand63bprovided inside the grooves, respectively. The upper portions of the third well region54aand the fourth well region Mb are provided with grooves from the surface of the semiconductor region52to reach the third well region54aand the fourth well region54b, respectively. In the upper portions of the third well regions54aand the fourth well region54b, the contact regions56aand56bof p+-type, having higher impurity concentration than the third well regions54aand the fourth well region54b, are provided in contact with the bottoms of the grooves, respectively. Source electrodes64cand64dare buried in the grooves via source contact layers63cand63dprovided inside the grooves, respectively. For each of the source contact layers63cand63d, for example, a nickel silicide (NiSix) film may be used. For each of the source electrodes64aand64b, for example, an aluminum (Al) alloy containing Al as a main component may be used.

The top surface of the semiconductor region52between the third well region54aand the channel stopper region55, and the fourth well region54band the channel stopper region55, is provided with element isolation films58aand58bby local oxidation of silicon (LOCOS) and the like, respectively. A gate extraction electrode61A, electrically connected to the gate electrode61a, is provided on a top surface of the element isolation film58aon a side of the third well region54a. Also, a gate extraction electrode61B, electrically connected to the gate electrode61b, is provided on a top surface of the element isolation film58bon a side of the fourth well region54b. Field plate electrodes61C are provided on the top surfaces of the element isolation films58aand58bon sides of the channel stopper region55, respectively. For each of the gate extraction electrodes61A,61B and the field plate electrodes61C, for example, a polysilicon film and the like may be used.

Interlayer dielectric films62aand62bare deposited on the gate electrodes61aand61b, the gate extraction electrodes61A and61B, and the field plate electrodes61C. The source electrodes64a,64b,64c, and64dexposed between the respective interlayer dielectric films62aand62bare physically in contact with source electrode pads (surface electrodes)65aand65bmade of Al, for example. The gate extraction electrodes61A and61B exposed between the interlayer dielectric films62aand62bare physically in contact with gate electrode pads66aand66bmade of Al, for example. A drain electrode (a bottom electrode)67made of a metal film including an Al alloy containing Al as a main component, gold (Au) and the like, or a laminated film of the above metal films is deposited on a bottom surface of the common drain region51.

As illustrated inFIG. 3, the MIS transistors Tr1and Tr2are trench gate MIS transistors having the insulated gate electrode structures (60a,61a) and (60b,61b). The body diode Di1is implemented by the contact region56aof p+-type, the well region53a,54aof p-type, the semiconductor region52of n-type, and the common drain region51of n+-type. The body diode Dig is implemented by the contact region56bof p+-type, the well region53h,54bof p-type, the semiconductor region52, and the common drain region51. The channel stopper region55is delineated into a ring shape in a planar pattern along the peripheries of the first and second semiconductor elements2aand2b. The channel stopper region55between the first semiconductor element2aand the second semiconductor element2bis a single region common to the first and second semiconductor elements2aand2b.

FIG. 4illustrates voltages at the gates G of the MIS transistors Tr1and Tr2. As illustrated in part (a) ofFIG. 4, signals of the H-level are applied as drive signals to the gates G of the MIS transistors Tr1and Tr2substantially at the same time from the drive circuit6in the normal conductive state. A current in such case flows from the first source region57aa toward the second source region57bvia an inversion layer induced in the first well region53a, the common drain region51, and an inversion layer induced in the second well region53b, as indicated by the dotted line inFIG. 3. When the drive signals change to the L level, the MIS transistors Tr1and Tr2are turned off substantially at the same time.

The MIS transistors Tr1and Tr2are provided to have the common drain region51and the semiconductor region52in common, as illustrated inFIG. 3. Thus, a parasitic bipolar transistor may be implemented by the third well region54aof p-type serving as an emitter E, the common drain region51of n+-type or the semiconductor region52of n-type serving as a base B, and the fourth well region54bof p-type serving as a collector C.

As illustrated in part (b) ofFIG. 4, the MIS transistor Tr2may rise earlier than the MIS transistor Tr1by a delay time Dr to be in the turn-on state, if the drive signals applied from the drive circuit6to the respective MIS transistors Tr1and Tr2are deviated from each other. A conventional semiconductor device has a configuration in which a single signal line is branched from a drive circuit to apply a drive signal to each of the gates G of the MIS transistors Tr1and Tr2. In such a case, the transmission timing of the drive signal from the drive circuit6is not controlled accurately, causing a shift of the drive timing. Further, since the power source voltage VCCis applied from the source S of the MIS transistor Tr1on the upstream side, the voltage applied to the MIS transistor Tr2on the downstream side tends to be decreased as compared with the voltage applied to the MIS transistor Tr1. Thus, the MIS transistor Tr2operates earlier than the MIS transistor Tr1for the transmitted drive signals of the same voltage level. The MIS transistor Tr1is in the turn-off state during the delay time Dr illustrated in part (b) ofFIG. 4, while the body diode Di1is in the turn-on state. Therefore, the parasitic bipolar transistor may operate due to a base potential applied between the emitter E and the base B of the parasitic bipolar transistor.

When the drive signal of the MIS transistor Tr2has substantially the same signal width as the MIS transistor Tr1, as illustrated in part (b) ofFIG. 4, the parasitic bipolar transistor does not operate during a delay time Df in the falling time. However, as illustrated in part (c) ofFIG. 4, when the drive signal to the MIS transistor Tr2is applied later than to the MIS transistor Tr1, the parasitic bipolar transistor operates during the delay time Df in the falling time. In such case, the parasitic bipolar transistor does not operate during the delay time Dr in the rising time. The parasitic bipolar transistor thus starts operating when the MIS transistor Tr1is in the turn-off state and the MIS transistor Tr2is in the turn-on state. When the parasitic bipolar transistor operates, unnecessary current flows to the main switching circuit1, which may lead to a problem of a reduction in reliability.

In the first embodiment, as illustrated inFIG. 1, the respective gates G of the MIS transistors Tr1and Tr2are independently connected to the drive circuit6with separate signal lines. For example, the drive timing is controlled by increasing the signal width of the drive signal applied to the MIS transistor Tr1so that the H-level signal is applied to the MIS transistor Tr2only when the H-level signal is applied to the MIS transistor Tr1, as illustrated inFIG. 5. The parasitic bipolar transistor does not operate either during the delay time Dr in the rising time or during the delay time Df in the falling time.FIG. 5illustrates the voltages to the gates G of the MIS transistors Tr1and Tr2. According to the first embodiment, the drive circuit6can apply the drive signal independently to the respective gates G of the MIS transistors Tr1and Tr2. Thus, the semiconductor device according to the first embodiment can prevent the operation of the parasitic bipolar transistor, and can achieve the bidirectional switch capable of avoiding a loss of reliability.

FIG. 6is a plan view illustrating an example of a structure of the semiconductor device according to the first embodiment.FIG. 6illustrates a resin package130in a perspective state in order to indicate the inside of the semiconductor device. As illustrated inFIG. 6, the semiconductor device according to the first embodiment includes a lead frame (111,112,113,114,115,116), the power circuit chip3, the control circuit chip5, and the resin package130. The power circuit chip3is mounted on the lead frame (111to116). The control circuit chip5is stacked on the power circuit chip3. The lead frame (111to116) has a die pad111, and lead terminals112,113,114,115,116. The die pad111is electrically connected to the drain electrode67of the power circuit chip3. The respective lead terminals112,113,114,115,116are electrically connected to electrode pads of each of the power circuit chip3and the control circuit chip5.

As illustrated inFIG. 7, the power circuit chip3is supported and fixed onto the die pad111via conductive bonding material, such as solder and the like. An insulating protective film69, such as a polyimide film and the like is laminated on a top surface of the power circuit chip3. The protective film69is provided with an opening. For example, the source electrode pad65bof the second semiconductor element2bis exposed to the opening of the protective film69, as illustrated inFIG. 7. In addition, the source electrode pad65aof the first semiconductor element2a, the gate electrode pads66aand66bof the first and second semiconductor elements2aand2b, and the electrode pad of the temperature sensor4are also exposed to the opening of the protective film69. As illustrated inFIG. 6, the source electrode pad65aof the first semiconductor element2acorresponding to the power supply node12illustrated inFIG. 1is electrically connected to the lead terminals (power supply terminals)112via bonding wires125. The source electrode pad65bof the second semiconductor element2bcorresponding to the output node13illustrated inFIG. 1is electrically connected to the lead terminals (output terminals)113via bonding wires126.

As illustrated inFIG. 7, the control circuit chip5is mounted on the protective film69laminated on the top surface of the power circuit chip3via an insulating bonding material. As illustrated inFIG. 6, various kinds of electrode pads corresponding to the power supply node12, the ground node14, and the input node15illustrated inFIG. 1are exposed on the top surface of the control circuit chip5. The electrode pad corresponding to the ground node14is electrically connected to the lead terminals (ground terminals)114via bonding wires123. The electrode pad corresponding to the power supply node12is electrically connected to the lead terminal (power supply terminal)112via a bonding wire122. The electrode pad corresponding to the output node15is electrically connected to the lead terminal (input terminal)115via a bonding wire124. The lead terminal116is electrically connected to the die pad111. A plurality of pads for wiring between the power circuit chip3and the control circuit chip5are electrically connected to each other via bonding wires121.

As described above, in the semiconductor device according to the first embodiment, the first and second semiconductor elements2aand2bimplementing the main switching circuit1share the drift region50in common. The first source region57a, the second source region57b, and the insulated gate electrode structures (60a,61a), (60b,61b) are provided on the first well region53aand the second well region53bprovided on the upper part of the drift region50. Thus, in the first embodiment, it is easy to monolithically integrate the main switching circuit1into one body and it is possible to achieve the reduction in size of the semiconductor device. Further, in the first embodiment, a chip-on-chip (COC) structure is adopted such that the control circuit chip5is stacked on the power circuit chip3to be integrated into a single package. Therefore, the mounting area of the semiconductor device can be reduced. The power circuit chip3and the control circuit chip5may be used in parallel. Alternatively, the control circuit chip5may be provided as an external chip.

In the semiconductor device according to the first embodiment, the drive circuit6includes a processing circuit16to which a drive signal is input, and booster circuits17aand17belectrically and independently connected to the processing circuit16, as illustrated inFIG. 8. The output circuit7includes NOT-logic circuits (inverters)18aand18b, and charge-extracting semiconductor elements19aand19b.

As illustrated inFIG. 8, the booster circuit17ais electrically connected to the gate G of the MIS transistor Tr1of the first semiconductor element2a, The booster circuit17bis electrically connected to the gate G of the MIS transistor Tr2of the second semiconductor element2b. The booster circuits17aand17bare preferably DC/DC converters of charge pump circuits using capacitors. The input side of the NOT-logic circuit18ais electrically connected to the input side of the booster circuit17a, and the output side is electrically connected to a gate G of the charge-extracting semiconductor element19a. A source S and a drain D of a MIS transistor Tra of the charge-extracting semiconductor element19aare respectively connected in antiparallel to a cathode and an anode of a body diode Dia. A drain D and a source S of a MIS transistor Trb of the charge-extracting semiconductor element19bare respectively connected in antiparallel to a cathode and an anode of a body diode Dib. The drain D and the source S of the charge-extracting semiconductor element19aare respectively connected to the output side of the booster circuit17aand the output node13illustrated inFIG. 1. Similarly the input side of the NOT-logic circuit18bis electrically connected to the input side of the booster circuit17b, and the output side is electrically connected to a gate G of the charge-extracting semiconductor element19b. The drain D and the source S of the charge-extracting semiconductor element19bare respectively connected to the output side of the booster circuit17band the output node13illustrated inFIG. 1. The processing circuit16, the booster circuit17a, the booster circuit17b, the NOT-logic circuit18a, and the NOT-logic circuit18bare all connected to the power supply VCCwith the same reference potential VGND(ground (GND) or internal reference potential) as a reference potential.

FIG. 9Ais a circuit diagram illustrating a configuration example of the booster circuit17ain the semiconductor device according to the first embodiment of the present invention.FIG. 9Bis a diagram illustrating a rise of an output voltage GS of the booster circuit17aillustrated inFIG. 9A. The booster circuit17aincludes an oscillation circuit (oscillator)21which oscillates in accordance with a signal output from the processing circuit16, an inverter24which logically inverts the signal oscillated by the oscillation circuit21, and a multistage booster23a, for example, having two stages.

The oscillation circuit21oscillates only when a drive signal of turning on the MIS transistor Tr1is fed from the processing circuit16in the drive signal for turning on or off the MIS transistor Tr1, and then transmits the oscillation signal to the inverter24.

The inverter24inverts the oscillation signal transmitted from the oscillation circuit21, and transmits the inverted signal to an inverter28. The multistage booster23aincludes a capacitor25, and two diodes26and27of the first stage connected to the output of the inverter24, and a capacitor29, and two diodes30and31of the second stage connected to the output of the inverter28.

The input side of the inverter24in the first stage is connected to the output side of the oscillation circuit21, the output side of the inverter24is connected to the one of the terminals of the capacitor25, and the other terminal of the capacitor25is connected to each of a cathode of the diode26and an anode of the diode27. An anode of the diode26is connected to the power supply line of the voltage VCC. The power supply line of the voltage VCCis connected to the terminal VCCof the semiconductor device.

The input side of the inverter28in the second stage is connected to the output side of the inverter24, the output side of the inverter28is connected to the one of the terminals of the capacitor29, and the other terminal of the capacitor29is connected to each of a cathode of the diode30, an anode of the diode31, and the cathode of the diode27. An anode of the diode30is connected to the power supply line of the voltage VCC. A cathode of the diode31composes the output side of the booster circuit17a.

In the booster circuit17ahaving the above configuration, the oscillation circuit21starts oscillating when the drive signal of turning on the MIS transistor Tr1is fed from the processing circuit16. When the signal transmitted from the oscillation circuit21is, for example, in H-level (high-level), the H-level signal is fed to the inverter24in the first stage of the multistage booster23a. Then, the output of the inverter24turns to L-level (low-level) so as to connect one terminal of the capacitor25to VGND, and the capacitor25is charged via the diode26with the voltage Vcc of the power supply line. Thus, the terminal voltage of the capacitor25results in [VCC−Vf] (Vf is a forward voltage of the diode26).

When the signal from the oscillation circuit21turns to L-level, the L-level signal is fed to the inverter24in the first stage of the multistage booster23a. Then, the output of the inverter24turns to H-level, and the voltage VCCof the power supply line is applied to the one terminal of the capacitor25. And the voltage at the other terminal of the capacitor25results in [2(VCC−VGND)−Vf+VGND]. Since the H-level signal is fed to the inverter28in the second stage of the multistage booster23a, the output of the inverter28is in L-level, Thus, one terminal of the capacitor29is connected to VGND, and the voltage of [2(VCC−VGND)−Vf] is applied to the other terminal of the capacitor29via the diode27in the first stage of the multistage booster23a. The terminal voltage of the capacitor29thus results in [2(VCC−VGND)−2Vf+VGND] (Vf is a forward voltage common to the respective diodes26and27).

The above boosted voltage is then transmitted as the output voltage OS of the booster circuit17avia the diode31. The output signal of the boosted voltage is continuously obtained by alternately repeating the L-level and the H-level of the signal fed from the oscillation circuit21, to be applied as the gate voltage of the MIS transistor Tr1. The booster circuit17bhas the same configuration, and the output signal is applied as the gate voltage of the MIS transistor Tr2.

Second Embodiment

FIG. 10is a circuit diagram illustrating an example of a semiconductor device according to a second embodiment of the present invention. As illustrated inFIG. 10, the drive circuit6includes a processing circuit16bto which a drive signal is fed, and booster circuits17cand17delectrically connected in common to the processing circuit16b. The output circuit7includes charge-extracting semiconductor elements19cand19delectrically connected in common to a NOT-logic circuit (inverter)18c. The semiconductor device according to the second embodiment differs from the first embodiment in including the booster circuits17cand17delectrically connected in common to the processing circuit16b, and the charge-extracting semiconductor elements19cand19delectrically connected in common to the NOT-logic circuit (inverter)18c. The other configurations are the same as those of the semiconductor device according to the first embodiment, and overlapping explanations are not repeated below.

The booster circuit17chas a faster rise of the output, voltage than the booster circuit17d. The charge-extracting semiconductor element19chas lower charge extraction capability than the charge-extracting semiconductor element19d. As used herein, the expression “having lower charge extraction capability” denotes that a value of current that can flow through is low. For example, the channel width of the charge-extracting semiconductor element19cmay be shorter than the channel width of the charge-extracting semiconductor element19d. The following three examples can be used as the configuration in which the booster circuit17chas a faster rise of the output voltage than the booster circuit17d.

First Example of Booster Circuit

FIG. 11Ais a circuit diagram illustrating a first example of the booster circuit of the semiconductor device according to the second embodiment, andFIG. 11Bis a diagram illustrating a rise of an output voltage of the booster circuit17cillustrated inFIG. 11A. The booster circuit17dis the same as the booster circuit17aillustrated inFIG. 9A. The booster circuit17cillustrated inFIG. 11Aincludes a multistage booster23bhaving three stages, which is greater number of stages than that in the booster circuit17d. By setting the number of the stages of the multistage booster23bof the booster circuit17cto be greater than that of the booster circuit17d, the rise of the output voltage GS1can be faster than the output voltage OS of the booster circuit17aillustrated inFIG. 9A, as illustrated inFIG. 11B.

When the oscillation signal from the oscillation circuit21turns to H-level, the inverter28in the second stage transmits an H-level signal. The power supply voltage VCCis thus applied to one terminal of the capacitor29. Thus, the voltage VCCis superposed on the voltage [2(VCC−VGND) 2Vf+VGND] to result in [3(VCC−VGND)−2Vf+VGND] at the other terminal of the capacitor29. In such case, an inverter32in the third stage of the booster circuit17ctransmits an L-level signal. Then, one terminal of a capacitor33is connected to the internal potential VGND, and the voltage of [3(VCC−VGND)−2Vf+VGND] is applied to the other terminal of the capacitor33via the diode31at the second stage. Thus, the terminal voltage of the capacitor33results in [3(VCC−VGND)−3Vf+VGND]. The voltage boosted to [3(VCC−VGND)−3Vf+VGND] is fed as a gate signal GS1via a diode35.

FIG. 12is a timing chart for explaining a control method of the semiconductor device according to the second embodiment of the present invention. As illustrated inFIG. 12, the input signal fed to the drive circuit6is transmitted to the respective booster circuits17cand17dvia the processing circuit16b. A drive signal of voltage Vg1is fed to the gate G of the MIS transistor Tr1from the booster circuit17c, and rises during a rising time Dr1. A drive signal of voltage Vg2is fed to the gate G of the MIS transistor Tr2from the booster circuit17d, and rises during a rising time Dr2. The voltage Vg1is higher than the voltage Vg2. The rising time of the output voltage is different between the booster circuit17cand the booster circuit17d, the rising time Dr2is set to be longer than the rising time Dr1. The difference can reliably lead the MIS transistor Tr1to reach the turn-on state faster than the MIS transistor Tr2, so as to prevent the operation of the parasitic bipolar transistor illustrated inFIG. 3.

When the input signal is in H-level, the output of the NOT-logic circuit18cis at the L level, so as to lead the charge-extracting semiconductor elements19cand19dto be in the blocked state. When the input signal is at the L level to block the MIS transistors Tr1and Tr2, the output of the NOT-logic circuit18cis in H-level so that the charge-extracting semiconductor elements19cand19dare in the turn-on state. Therefore, charges accumulated in the booster circuits17cand17dand the gates G of the MIS transistors Tr1and Tr2can be extracted. As illustrated inFIG. 12, a falling time Df1when the MIS transistor Tr1is turned off is longer than a falling time Df2when the MIS transistor Tr2is turned off. Since the MIS transistor Tr1is thus inevitably led to the turn-on state when the MIS transistor Tr2is in the turn-on state, it is possible to prevent the operation of the parasitic bipolar transistor.

Second Example of Booster Circuit

FIG. 13Ais a circuit diagram illustrating a second example of the booster circuit of the semiconductor device according to the second embodiment of the present invention, andFIG. 13Bis a diagram illustrating the rise of the output voltage of the booster circuit illustrated inFIG. 13A. The booster circuit17dis the same as the booster circuit17aillustrated inFIG. 9A. The booster circuit17cillustrated inFIG. 13Aincludes an oscillation circuit21ahaving a higher frequency than that in the booster circuit17d. As illustrated inFIG. 13B, by setting the frequency of the oscillation circuit21aof the booster circuit17cto be higher than the frequency of the oscillation circuit21of the booster circuit17d, the rise of the output voltage GS1can be faster than the output voltage GS of the booster circuit17aillustrated inFIG. 9A, as illustrated inFIG. 13B.

Third Example of Booster Circuit

FIG. 14Ais a circuit diagram illustrating a third example of the booster circuit of the semiconductor device according to the second embodiment of the present invention, andFIG. 14Bis a diagram illustrating the rise of the output voltage of the booster circuit illustrated inFIG. 14A. The booster circuit17dis the same as the booster circuit17aillustrated inFIG. 9A. The booster circuit17cillustrated inFIG. 14Aincludes a capacitor25ahaving a greater capacitance than that in the booster circuit17d. Thus, by setting the capacitance of the capacitor25aof the booster circuit17cto be greater than the capacity of the capacitor25of the booster circuit17d, the rise of the output voltage GS1can be faster than the output voltage GS of the booster circuit17aillustrated inFIG. 9A, as illustrated inFIG. 14B.

FIG. 15is a timing chart for explaining a control method in the second example or the third example according to the second embodiment. As in the case illustrated inFIG. 12, the NHS transistor Tr1is reliably led to reach the turn-on state faster than the MIS transistor Tr2, and the MIS transistor Tr1is turned off later than the MIS transistor Tr2. Since the MIS transistor Tr1is thus inevitably led to the turn-on state when the MIS transistor Tr2is in the turn-on state, it is possible to prevent the operation of the parasitic bipolar transistor.

Other Embodiments

While the present invention has been described above by reference to the embodiments and modified examples, it should be understood that the present invention is not intended to be limited to the descriptions of the Specification and the drawings implementing part of this disclosure. Various alternative embodiments, examples, and technical applications will be apparent to those skilled in the art according to the spirit and scope of the disclosure of the embodiments. It should be noted that the present invention includes various embodiments, which are not disclosed herein, including elements optionally modified as alternatives to those illustrated in the above embodiments and modified examples. Therefore, the scope of the present invention is defined only by the subject matter according to the claims reasonably derived from the description heretofore.