Analog-to-digital converter device

An analog-to-digital converter (ADC) device includes capacitor arrays, a successive approximation register (SAR) circuitry, and a switching circuitry. When a first capacitor array of the capacitor arrays samples an input signal in a first phase, a second capacitor array of the capacitor arrays outputs the input signal sampled in a second phase as a sampled input signal. The SAR circuitry performs an analog-to-digital conversion on a combination of the sampled input signal and a residue signal generated in the second phase according to a conversion clock signal, in order to generate a digital output. The switching circuitry includes a first capacitor that stores the residue signal generated in the second phase. The switching circuitry couples the second capacitor array and the first capacitor to an input terminal of the SAR circuitry, in order to provide the combination of the sampled input signal and the residue signal.

BACKGROUND

Technical Field

The present disclosure relates to an analog-to-digital converter (ADC) device. More particularly, the present disclosure relates to a time interleaved successive approximation register ADC having a noise shaping function.

Description of Related Art

An analog-to-digital converter (ADC) has been widely applied to various electronic devices, in order to covert an analog signal to a digital signal for subsequent signal processing. As the need of processing data with high resolution (for example, video data) rises, the ADC is often the key component in the system. However, in practical applications, performance of the ADC is affected by serval non-ideal factors, such as process variations, quantization noise, thermal noise, and so on.

SUMMARY

Some aspects of the present disclosure are to provide an analog-to-digital converter (ADC) device that includes capacitor arrays, a successive approximation register (SAR) circuitry, and a switching circuitry. The capacitor arrays are configured to sample an input signal by turns, in which when a first capacitor array of the capacitor arrays is configured to sample the input signal in a first phase, a second capacitor array of the capacitor arrays is configured to output the input signal sampled in a second phase as a sampled input signal. The first phase is a current phase, and the second phase is prior to the first phase. The SAR circuitry is configured to perform an analog-to-digital conversion on a combination of the sampled input signal and a residue signal generated in the second phase according to a conversion clock signal, in order to generate a digital output. The switching circuitry includes a first capacitor configured to store the residue signal generated in the second phase. The switching circuitry is configured to couple the second capacitor array and the first capacitor to an input terminal of the SAR circuitry, in order to provide the combination of the sampled input signal and the residue signal.

As described above, the ADC device of embodiments of the present disclosure are able to provide a circuit architecture that has a noise-shaping function and time-interleaved conversion. As a result, the overall performance of the ADC device can be improved.

DETAILED DESCRIPTION

The following embodiments are disclosed with accompanying diagrams for detailed description. For illustration clarity, many details of practice are explained in the following descriptions. However, it should be understood that these details of practice do not intend to limit the present disclosure. That is, these details of practice are not necessary in parts of embodiments of the present embodiments. Furthermore, for simplifying the drawings, some of the conventional structures and elements are shown with schematic illustrations.

In this document, the term “coupled” may also be termed as “electrically coupled,” and the term “connected” may be termed as “electrically connected.” “Coupled” and “connected” may mean “directly coupled” and “directly connected” respectively, or “indirectly coupled” and “indirectly connected” respectively. “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other.

In this document, the term “circuitry” may indicate a system formed with one or more circuits. The term “circuit” may indicate an object, which is formed with one or more transistors and/or one or more active/passive elements based on a specific arrangement, for processing signals.

For ease of understanding, like elements in each figure are designated with the same reference number.

FIG. 1Ais a schematic diagram of an analog-to-digital converter (ADC) device100according to some embodiments of the present disclosure. In some embodiments, the ADC device100operates as a time interleaved successive approximation register (SAR) ADC.

The ADC device100includes binary capacitor arrays CT1and CT2, a switching circuitry120, and a SAR circuitry140. The SAR circuitry140includes a comparator circuit142, control logic circuits144and146, and switches M1-M2. In some embodiments, the binary capacitor arrays CT1and CT2cooperate with the switching circuitry120, in order to provide a noise shaping function to the ADC device100.

The binary capacitor arrays CT1and CT2samples an input signal Vinby turns, in order to provide the sampled input signal Vinto the SAR circuitry140. The SAR circuitry140performs a binary search algorithm based on the sampled input signal Vinand common voltages Vrefnand Vrefp. In some embodiments, the binary search algorithm is performed under control of one of the control logic circuits144and146. The comparator circuit142and the control logic circuits144and146are enabled by a clock signal ϕc(e.g., a conversion clock signal) to perform the binary search algorithm, in order to execute an analog-to-digital (A/D) conversion on the sampled input signal Vinto decide a digital output Dout.

The switch M1is conducted (e.g., closed) in response to an enabling level of a clock signal ϕs1′, in order to transmit the clock signal ϕcto the control logic circuit144. The switch M2is conducted in response to an enabling level of a clock signal ϕs2′, in order to transmit the clock signal ϕcto the control logic circuit146. The clock signal ϕs1′is an inverse of a clock signal ϕs1, and the clock signal ϕs2′is an inverse of a clock signal ϕs2.

Each of the binary capacitor arrays CT1and CT2includes capacitors and switches that are controlled by a corresponding one of the control logic circuits144and146. A first terminal of each of capacitors in the binary capacitor array CT1is configured to receive the input signal Vinand is coupled to a node N1. A second terminal of each of capacitors in the binary capacitor array CT1is configured to selectively receive common mode voltage Vrefnor Vrefpunder the control of the control logic circuit144. A first terminal of each of capacitors in the binary capacitor array CT2is configured to receive the input signal Vinand is coupled to a node N2. A second terminal of each of capacitors in the binary capacitor array CT2is configured to selectively receive common mode voltage Vrefnor Vrefpunder the control of the control logic circuit146.

The switching circuitry120is configured to couple the binary capacitor arrays CT1and CT2to the comparator circuit142according to at least one clock signal.

The switching circuitry120includes switches S1-S9and capacitors C2-C3. A first terminal of the switch S1receives the input signal Vin. A second terminal of the switch S1is coupled to the node N1. The switch S1is closed in response to an enabling level (e.g., high level) of the clock signal ϕs1, in order to transmit the input signal Vinto the binary capacitor array CT1. A first terminal of the switch S2receives the input signal Vin. A second terminal of the switch S2is coupled to the first terminal of the binary capacitor array CT2. The switch S2is conducted in response to an enabling level of the clock signal ϕs2.

The switch S3is coupled between the node N1and a first terminal of the capacitor C2. The switch S3is conducted in response to an enabling level of a clock signal ϕT1C. Under this condition, the sampled input signal Vinis provided from the binary capacitor array CT1to the capacitor C2for the A/D conversion.

The switch S4is coupled between the node N2and the first terminal of the capacitor C2. The switch S4is conducted in response to an enabling level (e.g., high level) of a clock signal ϕT2C. Under this condition, the sampled input signal Vinis provided from the binary capacitor array CT2to the capacitor C2for the A/D conversion.

The switch S5is coupled between the node N1and a first terminal of the capacitor C3. A second terminal of the capacitor C3is coupled to ground. The switch S5is conducted in response to an enabling level of a clock signal ϕs5. Under this condition, a residue signal on the binary capacitor array CT1is transferred to the capacitor C3. In some embodiments, the residue signal on the binary capacitor array CT1is generated in the A/D conversion or after the A/D conversion is completed. In some embodiments, the clock signal ϕs5may be a result of logic AND operation of a clock signal ϕcs0and an inverse of the clock signal ϕs1. For example, as shown inFIG. 1B, when the clock signal ϕcs0has the enabling level, and when the clock signal ϕs1has a disabling level (e.g., a low level), the clock signal ϕs5has the enabling level.

The switch S6is coupled between the node N2and the first terminal of the capacitor C3. The switch S6is conducted in response to an enabling level of a clock signal ϕs6. Under this condition, a residue signal on the binary capacitor array CT2is transferred to the capacitor C3. In some embodiments, the residue signal on the binary capacitor array CT2is generated in the A/D conversion or after the A/D conversion is completed. In some embodiments, the clock signal ϕs6may be a result of logic AND operation of a clock signal ϕcs0and an inverse of the clock signal ϕs2. For example, as shown inFIG. 1B, when the clock signal ϕcs0has the enabling level and the clock signal ϕs2has a disabling level, the clock signal ϕs6has the enabling level.

The switch S7is coupled between the first terminal of the capacitor C2and ground. A second terminal of the capacitor C2is coupled to one input terminal (e.g., positive input terminal) of the comparator circuit142. Another one input terminal (e.g., negative input terminal) of the comparator circuit142is coupled to ground. The switch S8is coupled between the second terminal of the capacitor C2and the first terminal of the capacitor C3. The switches S7-S8are conducted in response to an enabling level of a clock signal ϕcs1. Under this condition, the capacitor C3is coupled to the capacitor C2. After the charge sharing of the capacitors C2-C3is settled, the capacitor C2stores a residue signal Vres2. The residue signal Vres2is a charge sharing result of the capacitor C2and the residue signal previously stored on the capacitor C3.

The switch S9is coupled between the first terminal of the capacitor C3and ground. The switch S9is conducted in response to an enabling level of a clock signal ϕclean, in order to reset the capacitor C3to ground. In some embodiments, the ground mentioned above may be an AC ground.

Reference is made to both ofFIGS. 1A and 1B.FIG. 1Bis a schematic diagram illustrating waveforms of signals inFIG. 1Aaccording to some embodiments of the present disclosure.

As shown inFIG. 1B, in some embodiments, a time interval of the clock signal ϕchaving the enabling level is within a time interval of the clock signal ϕs1or φs2having the enabling level. In other words, when the SAR circuitry140performs the A/D conversion, one of the switches S1-S2is conducted, and the one of the binary capacitor arrays CT1-CT2samples the input signal Vinfor the corresponding A/D conversion.

In some embodiments, in a conversion phase k−1, a time interval of the clock signal ϕT1Chaving the enabling level is within a portion T2-1of the time interval of the clock signal ϕS2having the enabling level. The portion T2-1is overlapped with the time interval of the clock signal ϕchaving the enabling level. Time intervals of the clock signals ϕcs0, ϕs5, ϕcs1, and ϕcleanhaving the enabling levels are within a portion T2-2of the time interval of the clock signal ϕS2having the enabling level. The portion T2-2follows the portion T2-1.

Similarly, in a conversion phase k, a time interval of the clock signal ϕT2Chaving the enabling level is within a portion T1-1of the time interval of the clock signal ϕs1having the enabling level. The portion T1-1is overlapped with the time interval of the clock signal ϕchaving the enabling level. Time intervals of the clock signals ϕcs0, ϕs5, ϕcs1, and ϕcleanhaving the enabling level are within a portion T1-2of the time interval of the clock signal ϕS1having the enabling level. The portion T1-2follows the portion T1-1.

The time interval of the clock signal ϕcs0(or ϕs5/ϕs6) having the enabling level follows the time interval of the clock signal ϕchaving the enabling level. In other words, in phase k−1, after the A/D conversion is completed, the switch S5is conducted to couple the capacitor C3to the binary capacitor array CT1. In phase k, after the A/D conversion is completed, the switch S6is conducted to couple the capacitor C3to the binary capacitor array CT2.

The time interval of the clock signal ϕcs1having the enabling level follows the time interval of the clock signal ϕcs0(or ϕs5/ϕs6) having the enabling level. In other words, in phase k−1, after the charge sharing of the binary capacitor array CT1and the capacitor C3is settled, the switches S7-S8are conducted, such that the capacitors C2-C3are connected. In phase k, after the charge sharing of the binary capacitor array CT2and the capacitor C3is settled, the switches S7-S8are conducted, such that the capacitors C2-C3are connected.

The time interval of the clock signal ϕcleanhaving the enabling level follows the time interval of the clock signal ϕcs1having the enabling level. In other words, after the charge sharing of the capacitors C2-C3is settled, the switches S9is conducted to reset the capacitor C3.

In some embodiments, the clock signal ϕs1is an inverse to the clock signal ϕs2. For example, in phase k, the clock signal ϕs1has the enabling level, and the clock signal ϕs2has the disabling level. Under this condition, as shown inFIG. 1A, the switch S1is conducted, and the binary capacitor array CT1samples the input signal Vinin phase k (hereinafter “Vin(k)”). The switch S2is not conducted, and the switch M2is conducted. Accordingly, the SAR circuitry140performs the A/D conversion, under the control of the control logic circuit146, based on the input signal Vin(k−1) previously sampled on the binary capacitor array CT2and a residue signal Vres2(k−1) previously stored on the capacitor C2. Equivalently, the comparator circuit142quantizes the combination of the input signal Vin(k−1) and the residue signal Vres2(k−1) to generate the corresponding digital output Dout(k). In response to the enabling level of the clock signal ϕcs1, the capacitors C2-C3are connected, and thus the residue signal Vres2(k) is stored by the capacitor C2at the end of phase k−1. In some embodiments, the residue signal Vres2(k) may indicate quantization error(s) corresponding to the A/D conversion in the phase k−1.

In phase k+1, the clock signal ϕs2has the enabling level, and the clock signal ϕs1has the disabling level. Under this condition, the switch S2is conducted, and the binary capacitor array CT2samples the input signal Vin(k+1). The switch S1is not conducted, and the switch M1is conducted. Accordingly, the SAR circuitry140performs the A/D conversion, under the control of the control logic circuit144, based on the input signal Vin(k) sampled on the binary capacitor array CT1and the residue signal Vres2(k). Equivalently, the comparator circuit142quantizes the combination of the input signal Vin(k) and the residue signal Vres2(k) to generate the corresponding digital output Dout(k+1). In response to the enabling level of the clock signal ϕcs1, the capacitors C2-C3are connected, and thus the residue signal Vres2(k+1) is stored by the capacitor C2at the end of phase k+1.

With this analogy, in each conversion phase, the A/D conversion is executed based on a combination of the input signal Vin, and the residue signal Vres2that indicates quantization error(s) in a previous phase. As a result, a noise transfer function having the characteristic of noise shaping of the ADC device100can be obtained. Accordingly, a signal-to-noise ratio of the output of the ADC device100can be increased.

Reference is made toFIG. 2andFIG. 1B.FIG. 2is a schematic diagram of the ADC device100according to some embodiments of the present disclosure.

Compared withFIG. 1A, in this example, the switching circuitry120only utilizes the switches S1-S7and the capacitor C2, and the switch S7is controlled by the clock signal ϕcs0. In this example, as operation(s) of the switches S8-S9are omitted, the time interval of the conversion phase (e.g., phase k−1, k, k+1, . . . ) can be further reduced.

In phase k−1, when the clock signal ϕcs0and the clock signal ϕs5has the enabling level, the switches S5and S7are conducted. Under this condition, the binary capacitor array CT1is connected to the capacitor C2. After the charge sharing of the binary capacitor array CT1and the capacitor C2. The capacitor C2stores the residue signal Vres2(k−1).

In phase k, when the clock signal ϕchas the enabling level, the A/D conversion is performed based on a combination of the sampled input signal Vin(k−1) and the residue signal Vres2(k−1). When the clock signal ϕcs0and the clock signal ϕs6has the enabling level, the switches S6and S7are turned on. Under this condition, the binary capacitor array CT2is connected to the capacitor C2. After the charge sharing of the binary capacitor array CT2and the capacitor C2is settled, the capacitor C2stores the residue signal Vres2(k). In other words, the switch S6is conducted to transfer a residue signal generated in the A/D conversion in phase k from the capacitor array CT2to the capacitor C2. As a result, the capacitor C2stores the residue signal Vres2(k).

In phase k+1, when the clock signal ϕchas the enabling level, the A/D conversion is performed based on a combination of the sampled input signal Vin(k) and the residue signal Vres2(k). As a result, a noise transfer function having the characteristic of noise shaping of the ADC device100can be obtained as well.

In the above embodiments, both of the time interval of the SAR circuitry140performing the A/D conversion (e.g., time interval of the clock signal ϕchaving the enabling level) and the time interval of the switching circuitry120performing the charge sharing (e.g., time intervals of the clock signals ϕcs0, ϕcs1, and ϕcleanhaving the enabling level, or time interval of clock signal ϕcs0) are within the time interval of the conversion phase (e.g., phase k−1, k, k+1, . . . ). In some embodiments, during the charge sharing, the first terminal of the capacitor C2may be open.

The above configurations of each clock signal and the switching circuitry120are given for illustrative purposes, and the present disclosure is not limited thereto.

Reference is made toFIG. 3AtoFIG. 3D.FIG. 3Ais a schematic diagram of the ADC device100in phase k−1 according to some embodiments of the present disclosure.FIG. 3Bis a schematic diagram illustrating waveforms of signals inFIG. 3Aaccording to some embodiments of the present disclosure.FIG. 3Cis a schematic diagram of the ADC device100in phase k according to some embodiments of the present disclosure.FIG. 3Dis a schematic diagram of the ADC device100in phase k+1 according to some embodiments of the present disclosure.

In this example, the switching circuitry120includes switches S1-S4, in which the switch S3is controlled by the clock signal ϕs1′, and the switch S4is controlled by the clock signal ϕs2′. The switching circuitry120further includes switched-capacitors Cex1-Cex3In some embodiments, the switched-capacitors Cex1-Cex3are configured to be coupled to the binary capacitor array CT1, CT2, and the capacitor C2by turns, in order to provide a residue signal in a corresponding phase to the SAR circuitry140. In greater detail, in each conversion phase, two of the switched-capacitors Cex1-Cex3operate as capacitors in the binary capacitor arrays CT1and CT2respectively, and a remaining capacitor of the switched-capacitors Cex1-Cex3is coupled in parallel with the capacitor C2to transfer the residue signal.

For example, as shown inFIG. 3AandFIG. 3B, in phase k−1, the switched-capacitor Cex1is coupled between switch(es) of the binary capacitor array CT1and the node N1for the A/D conversion. The switched-capacitor Cex3is coupled in parallel with the capacitor C2for charge sharing. Under this condition, the switched-capacitor Cex1stores the residue signal Vres2(k−1) in the A/D conversion or after the A/D conversion is completed. The switched-capacitor Cex2is coupled between switch(es) of the binary capacitor array CT2and the node N2, in order to sample the input signal Vin(k−1).

As shown inFIG. 3BandFIG. 3C, in phase k, the switched-capacitor Cex2is coupled between the switch(es) of the binary capacitor array CT2and the node N2for the A/D conversion. The switched-capacitor Cex1is coupled in parallel with the capacitor C2for charge sharing. Under this condition, the A/D conversion is made based on a combination of the sampled input signal Vin(k−1) and the residue signal Vres2(k−1) shared by the switched-capacitor Cex1. The switched-capacitor Cex2stores the residue signal Vres2(k) in the A/D conversion or after the A/D conversion is completed. The switched-capacitor Cex3is coupled between the switch(es) of the binary capacitor array CT1and the node N1, in order to sample the input signal Vin(k).

As shown inFIG. 3BandFIG. 3D, in phase k+1, the switched-capacitor Cex3is coupled between the switch(es) of the binary capacitor array CT1and the node N1for the A/D conversion. The switched-capacitor Cex2is coupled in parallel with the capacitor C2for charge sharing. Under this condition, the A/D conversion is made based on a combination of the sampled input signal Vin(k) and the residue signal Vres2(k) shared by the capacitor Cex2. The switched-capacitor Cex3stores the residue signal Vres2(k+1) in the A/D conversion or after the A/D conversion is completed. The switched-capacitor Cex1is coupled between the switch(es) of the binary capacitor array CT2and the node N2, in order to sample the Vin(k+1).

With this configuration, as shown inFIG. 3B, only the time interval of the SAR circuitry140performing the A/D conversion (e.g., time interval of the clock signal ϕchaving the enabling level) is within the time interval of the conversion phase (e.g., phase k−1, k, k+1, . . . ). Accordingly, the time interval of the conversion phase in this example can be further reduced, and the ADC device100equivalently operates in a higher clock rate.

In some embodiments, the clock signal ϕcmay be a group of synchronous clock signals. In some embodiments, the clock signal ϕcmay be a group of asynchronous clock signals. Various settings of the clock signal ϕcare within the contemplated scope of the present disclosure.

Reference is made toFIG. 4.FIG. 4is a circuit diagram of the switched-capacitor Cex1inFIGS. 3A, 3C, and/or3D according to some embodiments of the present disclosure.

As shown inFIG. 4, the switched-capacitor Cex1includes a capacitor C and a switching circuit410. The switching circuit410operates as a multiplexer circuit based on a combination of the clock signals ϕs1and ϕs2, in order to couple the capacitor C to different terminals of the binary capacitor array CT1or CT2, or the nodes N1or N2, or the capacitor C2. Thus, in different phases, the switched-capacitor Cex1may be set to provide different functions, as discussed inFIGS. 3A, 3C, and 3D.

The implementations of the switched-capacitors Cex2and Cex3can be understood with reference toFIG. 4. The implementations of the switched-capacitors Cex1-Cex3are given for illustrative purposes, and the present disclosure is not limited thereto.

In some embodiments, the comparator circuit142inFIGS. 1A, 2, 3A, 3C, and3D may be implemented with two comparators that are configured to operate with the control logic circuits144and146respectively.

As described above, the ADC devices of embodiments of the present disclosure are able to provide a circuit architecture that has a noise-shaping function and time-interleaved conversion. As a result, the overall performance of the ADC device can be improved.

Various functional components or blocks have been described herein. As will be appreciated by persons skilled in the art, in some embodiments, the functional blocks will preferably be implemented through circuits (either dedicated circuits, or general purpose circuits, which operate under the control of one or more processors and coded instructions), which will typically comprise transistors or other circuit elements that are configured in such a way as to control the operation of the circuitry in accordance with the functions and operations described herein. As will be further appreciated, the specific structure or interconnections of the circuit elements will typically be determined by a compiler, such as a register transfer language (RTL) compiler. RTL compilers operate upon scripts that closely resemble assembly language code, to compile the script into a form that is used for the layout or fabrication of the ultimate circuitry. Indeed, RTL is well known for its role and use in the facilitation of the design process of electronic and digital systems.