Magnetoresistive random access memory device and method of manufacturing the same

A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2015-0126863, filed on Sep. 8, 2015 in the Korean Intellectual Property Office (KIPO), the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

Example embodiments relate to semiconductor devices and methods of manufacturing the same. More particularly, example embodiments relate to magnetoresistive random access memory (MRAM) devices and methods of manufacturing the same.

When an MRAM device is manufactured, a lower electrode may be formed through an insulating interlayer, and a magnetic tunnel junction (MTJ) structure layer may be formed on the lower electrode and the insulating interlayer. The MTJ structure layer may include a noble metal, and may be patterned by a physical etching process to form an MTJ structure. When the physical etching process is performed, the insulating interlayer and the lower electrode under the MTJ structure layer may be also etched, and elements of the lower electrode may be thus re-deposited on a sidewall of the MTJ structure, which may generate an electrical short.

SUMMARY

Example embodiments provide a method of manufacturing an MRAM device having good characteristics.

Example embodiments provide an MRAM device having good characteristics.

According to example embodiments, there is provided a method of manufacturing an MRAM device. In the method, a first insulating interlayer and an etch-stop layer may be sequentially formed on a substrate. A lower electrode may be formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode may be sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer may be patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer may be protected by the etch-stop layer so not to be etched by the physical etching process.

In example embodiments, the etch-stop layer may include a metal oxide, a nitride and/or a ceramic material.

In example embodiments, the metal oxide may include aluminum oxide, magnesium oxide, yttrium oxide and/or erbium oxide.

In example embodiments, the nitride may include boron nitride.

In example embodiments, the ceramic material may include yttrium silicon oxide, zirconium titanium oxide and/or barium titanium oxide.

In example embodiments, the physical etching process may include an ion beam etching (IBE) process.

In example embodiments, the at least a portion of the etch-stop layer may remain on the first insulating interlayer after the physical etching process.

In example embodiments, the MTJ structure may cover the whole upper surface of the lower electrode.

In example embodiments, the MTJ structure may cover a portion of an upper surface of the lower electrode. A recess may be formed at an upper portion of the lower electrode by the physical etching process. A bottom of the recess may not be lower than a lower surface of the etch-stop layer.

In example embodiments, when the lower electrode is formed, a landing pad may be formed through the etch-stop layer and the first insulating interlayer that is spaced apart from the lower electrode.

In example embodiments, when the lower electrode and the landing pad are formed, first and second openings may be formed through the etch-stop layer and the first insulating interlayer. A conductive layer may be formed on the etch-stop layer to fill the first and second openings. The conductive layer may be planarized until an upper surface of the etch-stop layer is exposed.

In example embodiments, upper surfaces of the lower electrode and the landing pad may be substantially coplanar with the upper surface of the etch-stop layer.

In example embodiments, upper surfaces of the lower electrode and the landing pad may be formed at different heights from that of the upper surface of the etch-stop layer.

In example embodiments, a planarization layer may be further formed on the lower electrode, the landing pad and the etch-stop layer. The planarization layer may be etched by the physical etching process to form a planarization pattern under the MTJ structure.

In example embodiments, the planarization layer may include a metal nitride.

In example embodiments, a relatively small amount of an upper portion of the landing pad may be etched when the physical etching process is performed.

In example embodiments, a wiring structure including a via and a first wiring sequentially stacked and integrally formed with each other may be formed. The via may contact an upper surface of the landing pad, and the first wiring may be electrically connected to the upper electrode.

In example embodiments, when the wiring structure is formed, a second insulating interlayer may be formed on the upper electrode, the MTJ structure, the landing pad and the etch-stop layer. The second insulating interlayer may be partially removed to form a via hole exposing the upper surface of the landing pad. The via may be formed to fill the via hole.

In example embodiments, the lower electrode may be formed in a memory cell region, and the landing pad may be formed in a peripheral region.

In example embodiments, both of the lower electrode and the landing pad may be formed in a memory cell region.

In example embodiments, before the first insulating interlayer and the etch-stop layer are sequentially formed on the substrate, a second wiring may be formed on the substrate. The lower electrode may be formed to contact an upper surface of the second wiring.

In example embodiments, when the second wiring is formed on the substrate, a third insulating interlayer may be formed on the substrate. The second wiring and a third wiring may be formed through the third insulating interlayer. When the lower electrode is formed, a landing pad may be formed through the etch-stop layer and the first insulating interlayer that is spaced apart from the lower electrode and contact an upper surface of the third wiring.

In example embodiments, before the first insulating interlayer and the etch-stop layer are sequentially formed, second and third wirings may be formed on the substrate. The lower electrode may contact an upper surface of the second wiring. After the MTJ structure is formed, a wiring structure including a via and a first wiring sequentially stacked and integrally formed with each other may be formed. The via may contact the third wiring, and the first wiring may be electrically connected to the upper electrode.

In example embodiments, the MTJ structure may include a noble metal.

According to example embodiments, there is provided a method of manufacturing an MRAM device. In the method, an insulating interlayer structure including an etch-stop layer may be formed on a substrate. A lower electrode may be formed through the insulating interlayer structure. An MTJ structure layer and an upper electrode may be sequentially formed on the lower electrode and the insulating interlayer structure. The MTJ structure layer may be patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. A portion of the insulating interlayer structure under the etch-stop layer may be protected by the etch-stop layer so not to be etched by the physical etching process.

In example embodiments, the insulating interlayer structure may include a first insulating interlayer, the etch-stop layer and a second insulating interlayer sequentially stacked. The lower electrode may be formed through the first insulating interlayer, the etch-stop layer and the second insulating interlayer.

In example embodiments, the etch-stop layer may remain on the first insulating interlayer after the physical etching process.

In example embodiments, the etch-stop layer may include a metal oxide, a nitride and/or a ceramic material.

In example embodiments, when the lower electrode is formed, a landing pad may be formed through the insulating interlayer structure that is spaced apart from the lower electrode. An upper portion of the landing pad may be partially etched by the physical etching process, and an upper surface of the landing pad may not be lower than a lower surface of the etch-stop layer.

In example embodiments, a wiring structure including a via and a wiring sequentially stacked and integrally formed with each other may be formed. The via may contact an upper surface of the landing pad, and the wiring may be electrically connected to the upper electrode.

In example embodiments, the insulating interlayer structure may include the etch-stop layer and a first insulating interlayer sequentially stacked on the substrate. The lower electrode may be formed through the first insulating interlayer and the etch-stop layer.

In example embodiments, the insulating interlayer structure may include a first insulating interlayer and the etch-stop layer sequentially stacked on the substrate. The lower electrode may be formed through the etch-stop layer and the first insulating interlayer.

According to example embodiments, there is provided an MRAM device. The MRAM device may include an insulating interlayer structure, a lower electrode, a landing pad, an MTJ structure, an upper electrode and a wiring structure. The insulating interlayer structure may be formed on a substrate, and include a first insulating interlayer and an etch-stop layer sequentially stacked. The lower electrode and the landing pad may be formed through the insulating interlayer structure and spaced apart from each other. The MTJ structure may be formed on the lower electrode. The upper electrode may be formed on the MTJ structure. The wiring structure may include a via and a first wiring sequentially stacked and integrally formed with each other. The via may contact an upper surface of the landing pad, and the first wiring may be electrically connected to the upper electrode. The upper surface of the landing pad may not be lower than a lower surface of the etch-stop layer.

In example embodiments, the etch-stop layer may include a metal oxide, a nitride and/or a ceramic material.

In example embodiments, the upper surface of the landing pad may not be lower than an upper surface of the lower electrode.

In example embodiments, the upper surface of the lower electrode may not be higher than an upper surface of the etch-stop layer.

In example embodiments, the lower electrode may protrude from an upper surface of the insulating interlayer structure.

In example embodiments, the MRAM device may further include an insulation pattern covering an upper sidewall of the lower electrode.

In example embodiments, the upper surface of the landing pad may be lower than an upper surface of the lower electrode.

In example embodiments, the MRAM device may further include second and third wirings between the substrate and the insulating interlayer structure. The second and third wirings may respectively contact bottoms of the lower electrode and the landing pad.

According to example embodiments, there is provided an MRAM device. The MRAM device may include an etch-stop layer structure, a lower electrode, an insulation pattern, a landing pad, an MTJ structure, an upper electrode and a wiring structure. The etch-stop layer structure may be formed on a substrate, and include first and second etch-stop layers sequentially stacked. The lower electrode may be formed through the etch-stop layer structure, and protrude from an upper surface of the etch-stop layer structure. The insulation pattern may cover an upper sidewall of the lower electrode. The landing pad may be formed through the first etch-stop layer. The MTJ structure may be formed on the lower electrode. The upper electrode may be formed on the MTJ structure. The wiring structure may include a via and a wiring sequentially stacked and integrally formed with each other. The via may contact an upper surface of the landing pad, and the wiring may be electrically connected to the upper electrode.

In example embodiments, the first etch-stop layer may include silicon nitride, silicon oxynitride, silicon carbonitride, and/or silicon oxycarbonitride, and the second etch-stop layer may include a metal oxide, a nitride, and/or a ceramic material.

According to example embodiments, there is provided an MRAM device. The MRAM device may include an insulating interlayer, an etch-stop layer, a lower electrode, an insulation pattern, an MTJ structure, an upper electrode and a wiring structure. The insulating interlayer may be formed on a substrate, and contain first and second wirings therein. The etch-stop layer may be formed on the first and second wirings and the insulating interlayer, and at least partially expose an upper surface of the second wiring. The lower electrode may be formed through the etch-stop layer. The lower electrode may contact an upper surface of the first wiring, and protrude from an upper surface of the etch-stop layer structure. The insulation pattern may cover an upper sidewall of the lower electrode. The MTJ structure may be formed on the lower electrode. The upper electrode may be formed on the MTJ structure. The wiring structure may include a via and a third wiring sequentially stacked and integrally formed with each other. The via may contact the exposed upper surface of the second wiring, and the third wiring may be electrically connected to the upper electrode.

In example embodiments, the first to third wirings and the lower electrode may include a metal, and the etch-stop layer may include a metal oxide, a nitride and/or a ceramic material.

According to example embodiments, there is provided an MRAM device. The MRAM device may include a first insulating interlayer, an insulating interlayer structure, a lower electrode, an MTJ structure, an upper electrode and a wiring structure. The first insulating interlayer may be formed on a substrate, and contain first and second wirings therein. The insulating interlayer structure may be formed on the first and second wirings and the first insulating interlayer, and include a second insulating interlayer and an etch-stop layer sequentially stacked. The lower electrode may be formed through the insulating interlayer structure, and contact an upper surface of the first wiring. The lower electrode may be formed through the insulating interlayer structure, and contact an upper surface of the first wiring. The MTJ structure may be formed on the lower electrode. The upper electrode may be formed on the MTJ structure. The wiring structure may include a via and a third wiring sequentially stacked and integrally formed with each other. The via may penetrate through the insulating interlayer structure and contact an upper surface of the second wiring. The third wiring may be electrically connected to the upper electrode.

In example embodiments, an upper surface of the lower electrode may not be higher than an upper surface of the insulating interlayer structure.

In example embodiments, an upper surface of the lower electrode may be higher than an upper surface of the insulating interlayer structure.

In example embodiments, the MRAM device may further including an insulation pattern covering an upper sidewall of the lower electrode.

In example embodiments, the etch-stop layer may include a metal oxide, a nitride and/or a ceramic material.

In a method of manufacture an MRAM device in accordance with example embodiments, an etch-stop layer may be formed on an insulating interlayer so that the insulating interlayer may not be etched, but may be protected in an IBE process for forming an MTJ structure. Thus, a lower electrode of which a sidewall may be covered by the insulating interlayer may not be etched so that elements of the lower electrode may not be re-deposited on the sidewall of the MTJ structure. A landing pad of which a sidewall may be covered by the insulating interlayer may not be etched to have a height similar to that of the lower electrode. Accordingly, a via hole exposing an upper surface of the landing pad may not be relatively deep, and a via may be formed to sufficiently fill the via hole with no void or seam therein.

According to example embodiments, a magnetoresistive random access memory (MRAM) device comprises: a substrate in which the substrate comprises a top surface; a first insulating interlayer may be on the top surface substrate in which the first insulating interlayer may comprise a bottom surface and a top surface that is opposite the top surface, the bottom surface of the first insulating interlayer may be proximate to the top surface of the substrate, and the top surface of the first insulating interlayer may be distal to the top surface of the substrate; at least one first wiring structure may be disposed in the first insulating interlayer in which the at least one first wiring structure may comprise a top surface, and at least a portion of the top surface of the at least one first wiring structure may be at substantially a same level at the top surface of the first insulating interlayer; an etch-stop layer may be on the top surface of the first insulating interlayer in which the etch-stop layer may comprise a bottom surface and a top surface that is opposite the top surface, the bottom surface of the etch-stop layer may be proximate to the top surface of the first insulating interlayer, the top surface of the etch-stop layer may be distal to the top surface of the first insulating interlayer, and the bottom surface of the etch-stop layer may not be higher than the top surface of the at least one first wiring structure; a second insulating interlayer may be on the top surface etch-stop layer in which the second insulating interlayer may comprise a bottom surface and a top surface that is opposite the top surface, the bottom surface of the second insulating interlayer may be proximate to the top surface of the etch-stop layer, and the top surface of the first insulating interlayer may be distal to the top surface of the etch-stop layer; at least one lower electrode may be disposed in the second insulating interlayer in which the at least one lower electrode may extend through the second insulating interlayer and may contact a corresponding first wiring structure; and at least one magnetic tunnel junction (MTJ) structure in which each MTJ structure may be electrically connected to a corresponding to a lower electrode.

In example embodiments, the MRAM device may further comprise a plurality of MTJ structures arranged in an array comprising at least one row and at least one column.

In example embodiments, the etch-stop layer may comprise a metal oxide, a nitride and/or a ceramic material.

In example embodiments, the MRAM device may further comprise: a third insulating interlayer on the top surface of the second insulating interlayer in which the third insulating interlayer may comprise a bottom surface and a top surface that is opposite the top surface, the bottom surface of the third insulating interlayer may be proximate to the top surface of the second insulating interlayer, and the top surface of the third insulating interlayer may be distal to the top surface of the second insulating interlayer; and at least one third wiring structure that may be disposed in the third insulating interlayer in which the at least one third wiring structure may be electrically connected to a corresponding MTJ structure.

In example embodiments, the MRAM device may further comprise at least one landing pad disposed in the first insulating interlayer in which the at least one landing pad may comprise a top surface, and at least a portion of the top surface of the at least one landing pad may be at substantially a same level at the top surface of the first insulating interlayer, and in which the bottom surface of the etch-stop layer may be at substantially a same level as the top surface of the at least one landing pad.

In example embodiments, the at least one landing pad may be electrically connected to a corresponding first wiring structure.

In example embodiments, the MRAM device may further comprise a third insulating interlayer on the top surface of the second insulating interlayer in which the third insulating interlayer may comprise a bottom surface and a top surface that is opposite the top surface, the bottom surface of the third insulating interlayer may be proximate to the top surface of the second insulating interlayer, and the top surface of the third insulating interlayer may be distal to the top surface of the second insulating interlayer; and at least one third wiring structure disposed in the third insulating interlayer in which the at least one third wiring structure may be electrically connected to a corresponding landing pad through the third insulating interlayer.

In example embodiments, the upper surface of at least one landing pad may not be lower than an upper surface of the at least one lower electrode.

In example embodiments, the at least one lower electrode may comprise a top surface that is at substantially a same level of the top surface of the etch-stop layer, and the MRAM device may further comprise at least one planarization pattern on at least a portion of the top surface of a corresponding lower electrode between the top surface of the corresponding lower electrode and the MTJ device.

According to example embodiments, a method to form a magnetoresistive random access memory (MRAM) device comprises: forming a first insulating interlayer on a top surface substrate in which the first insulating interlayer may comprise a bottom surface and a top surface that is opposite the top surface, the bottom surface of the first insulating interlayer may be proximate to the top surface of the substrate, and the top surface of the first insulating interlayer may be distal to the top surface of the substrate; forming at least one first wiring structure in the first insulating interlayer in which the at least one first wiring structure may comprise a top surface, and at least a portion of the top surface of the at least one first wiring structure may be at substantially a same level at the top surface of the first insulating interlayer; forming an etch-stop layer on the top surface of the first insulating interlayer in which the etch-stop layer may comprise a bottom surface and a top surface that is opposite the top surface, the bottom surface of the etch-stop layer may be proximate to the top surface of the first insulating interlayer, the top surface of the etch-stop layer may be distal to the top surface of the first insulating interlayer, and the bottom surface of the etch-stop layer may not be higher than the top surface of the at least one first wiring structure; forming a second insulating interlayer on the top surface etch-stop layer in which the second insulating interlayer may comprise a bottom surface and a top surface that is opposite the top surface, the bottom surface of the second insulating interlayer may be proximate to the top surface of the etch-stop layer, and the top surface of the first insulating interlayer may be distal to the top surface of the etch-stop layer; forming at least one lower electrode disposed in the second insulating interlayer in which the at least one lower electrode may extend through the second insulating interlayer and may contact a corresponding first wiring structure; and forming at least one magnetic tunnel junction (MTJ) structure in which each MTJ structure may be electrically connected to a corresponding to a lower electrode.

In example embodiments, the method may further comprise forming a plurality of MTJ structures that may be arranged in an array comprising at least one row and at least one column.

In example embodiments, the etch-stop layer may comprise a metal oxide, a nitride and/or a ceramic material.

In example embodiments, the method may further comprise: forming a third insulating interlayer on the top surface of the second insulating interlayer in which the third insulating interlayer comprises a bottom surface and a top surface that is opposite the top surface, the bottom surface of the third insulating interlayer may be proximate to the top surface of the second insulating interlayer, and the top surface of the third insulating interlayer may be distal to the top surface of the second insulating interlayer; and forming at least one third wiring structure disposed in the third insulating interlayer in which the at least one third wiring structure may be electrically connected to a corresponding MTJ structure.

In example embodiments, the method may further comprise: forming at least one landing pad disposed in the first insulating interlayer in which the at least one landing pad may comprise a top surface, and at least a portion of the top surface of the at least one landing pad may be at substantially a same level at the top surface of the first insulating interlayer, and in which the bottom surface of the etch-stop layer may be at substantially a same level as the top surface of the at least one landing pad.

In example embodiments, the at least one landing pad may be electrically connected to a corresponding first wiring structure.

In example embodiments, the method may further comprise: forming a third insulating interlayer on the top surface of the second insulating interlayer in which the third insulating interlayer may comprise a bottom surface and a top surface that is opposite the top surface, the bottom surface of the third insulating interlayer may be proximate to the top surface of the second insulating interlayer, and the top surface of the third insulating interlayer may be distal to the top surface of the second insulating interlayer; and forming at least one third wiring structure disposed in the third insulating interlayer in which the at least one third wiring structure may be electrically connected to a corresponding landing pad through the third insulating interlayer.

In example embodiments, the upper surface of at least one landing pad may not be lower than an upper surface of the at least one lower electrode.

In example embodiments, the at least one lower electrode may comprise a top surface that is at substantially a same level of the top surface of the etch-stop layer, and the method may further comprise forming at least one planarization pattern on at least a portion of the top surface of a corresponding lower electrode that may be between the top surface of the corresponding lower electrode and the MTJ device.

DESCRIPTION OF EMBODIMENTS

FIGS. 1 to 9are cross-sectional views depicting stages of a method of manufacturing an MRAM device in accordance with example embodiments.

Referring toFIG. 1, a first insulating interlayer110may be formed on a substrate100, and a first wiring structure140and a second wiring structure145may be formed through the first insulating interlayer110.

The substrate100may include first and second regions I and II. In example embodiments, the first region I may include the first wiring structure140, and the second region II may include the second wiring structure145. In example embodiments, the first region I may serve as a cell region in which memory cells may be formed, and the second region II may serve as a peripheral region in which peripheral circuits may be formed and/or a logic region in which logic devices may be formed.

Various types of elements (not shown), e.g., word lines, transistors, diodes, source/drain layers, contact plugs, wirings, etc., and an insulating interlayer covering the elements may be further formed on the substrate100. For example, the first wiring structure140and the second wiring structure145may be formed to contact the contact plugs under the first wiring structure140and the second wiring structure145, and thus may be electrically connected to the source/drain layers on the substrate100, which may contact the contact plugs.

The first insulating interlayer110may be formed of silicon oxide, or a low-k dielectric material having a dielectric constant that is less than the dielectric constant of silicon oxide, i.e., less than about 3.9. For example, the first insulating interlayer110may be formed of silicon oxide doped with carbon (SiCOH) or silicon oxide doped with fluorine (F—SiO2), a porous silicon oxide, spin on organic polymer, or an inorganic polymer, e.g., hydrogen silsesquioxane (HSSQ), methyl silsesquioxane (MSSQ), etc.

In example embodiments, the first wiring structure140and the second wiring structure145may be formed by a dual damascene process or by a single damascene process.

For example, the first wiring structure140and the second wiring structure145may be formed by a dual damascene process, as follows.

First and second masks (not shown) may be sequentially formed on the first insulating interlayer110, and an upper portion of the first insulating interlayer110may be partially removed using the first and second masks as an etching mask. The first mask may be formed of, e.g., a metal nitride, and the second mask may be formed of, e.g., silicon-on-hardmask (SOH).

After removing the second mask, the first insulating interlayer110may be etched with the first mask remaining on the first insulating interlayer110. Thus, a first via hole (not shown) may be formed through a lower portion of the first insulating interlayer110to expose a top surface of the first region I of the substrate100. A first trench (not shown) may be formed through an upper portion of the first insulating interlayer110to be in communication with the first via hole. Additionally, a second via hole (not shown) may be formed through a lower portion of the first insulating interlayer110to expose a top surface of the second region II of the substrate100. A second trench (not shown) may be formed through an upper portion of the first insulating interlayer110to be in communication with the second via hole.

A first barrier layer may be formed on the exposed top surfaces of the substrate100, on the bottoms and sidewalls of the first and second via holes and the first and second trenches, and the first insulating interlayer110, A first conductive layer may be formed on the first barrier layer to fill remaining portions of the first and second via holes and the first and second trenches. The first conductive layer and the first barrier layer may be planarized until an upper surface of the first insulating interlayer110may be exposed to form the first wiring structure140and the second wiring structure145respectively on the first and second regions I and II of the substrate100.

The first conductive layer may be formed by forming a seed layer (not shown) on the first barrier layer, and performing an electroplating process.

The first barrier layer may be formed of a metal nitride, e.g., tantalum nitride, titanium nitride, etc., or a metal, e.g., tantalum, titanium, etc. The first conductive layer may be formed of a metal, e.g., tungsten, copper, aluminum, etc.

In example embodiments, the planarization process may be performed by a chemical mechanical polishing (CMP) process and/or an etch-back process. Upper surfaces of the first wiring structure140and the second wiring structure145may be substantially coplanar with the upper surface of the first insulating interlayer110. In some example embodiments, the upper surfaces of one or more of the first wiring structure140and the second wiring structure145may not be coplanar with the upper surface of the first insulating interlayer110, and in this case, a planarization layer (not shown) may be further formed on the upper surfaces of the first wiring structure140and the second wiring structure145and the first insulating interlayer110.

The first wiring structure140may include a first via141and a first wiring142, which may be sequentially stacked and integrally formed with each other. The second wiring structure145may include a second via143and a second wiring144, which may be sequentially stacked and integrally formed with each other.

The first via141may include a first conductive pattern131and a first barrier pattern121that covers a bottom and a sidewall of the first conductive pattern131. The second via143may include a second conductive pattern133and a second barrier pattern123that covers a bottom and a sidewall of the second conductive pattern133. The first wiring142may include a third conductive pattern132and a third barrier pattern122that covers a portion of a bottom and a sidewall of the third conductive pattern132. The wiring144may include a fourth conductive pattern134and a fourth barrier pattern124that covers a portion of a bottom and a sidewall of the fourth conductive pattern134.

Referring toFIG. 2, a first etch-stop layer150, a second insulating interlayer160and a second etch-stop layer170may be sequentially formed on the first wiring structure140and the second wiring structure145, and the first insulating interlayer110. The sequentially stacked first etch-stop layer150, the second insulating interlayer160and the second etch-stop layer170may be referred to as an insulating interlayer structure161.

The first etch-stop layer150may be formed of a nitride, e.g., silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, etc. The second insulating interlayer160may be formed of silicon oxide or a low-k dielectric material. The second etch-stop layer170may be formed of a material that may be easily etched by a chemical etching process, e.g., a reactive ion etching (RIE) process. The second etch-stop layer may not, however, be easily etched by a physical etching process, e.g., an ion beam etching (IBE) process.

In particular, the second etch-stop layer170may be formed of a metal oxide, a nitride or a ceramic material. For example, the second etch-stop layer170may be formed of a metal nitride, such as aluminum oxide, magnesium oxide, yttrium oxide, erbium oxide, etc., a nitride such as boron nitride, or a ceramic material such as yttrium silicon oxide, zirconium titanium oxide, barium titanium oxide, etc.

Referring toFIG. 3, the insulating interlayer structure161may be partially removed to form first and second openings182and184exposing the respective upper surfaces of the first wiring structure140and the second wiring structure145, i.e., the respective upper surfaces of the first and second wirings142and144.

In example embodiments, a photoresist pattern (not shown) may be formed on the second etch-stop layer170, and the insulating interlayer structure161may be etched by a dry-etching process using the photoresist pattern as an etching mask to form the first and second openings182and184. The dry-etching process may include a chemical etching process, e.g., an RIE process. Thus, the insulating interlayer structure161, which includes the second etch-stop layer170, may be easily etched.

Referring toFIG. 4, a lower electrode212and a landing pad214may be formed on the first and second regions I and II to respectively fill the first and second openings182and184.

In example embodiments, the lower electrode212and the landing pad214may be formed by forming a second barrier layer on the exposed upper surfaces of the first and second wirings142and144, on the sidewalls of the first and second openings182and184, and on an upper surface of the second etch-stop layer170. A second conductive layer may be formed on the second barrier layer to fill remaining portions of the first and second openings182and184. The second conductive layer and the second barrier layer may be planarized until the upper surface of the second etch-stop layer170may be exposed.

The second barrier layer may be formed of a metal nitride, e.g., tantalum nitride, titanium nitride, etc., and/or a metal, e.g. tantalum, titanium, etc. The second conductive layer may be formed of a metal, e.g., tungsten, copper, aluminum, etc.

In example embodiments, the planarization process may be performed by a CMP process and/or an etch-back process. In an example embodiment, upper surfaces of the lower electrode212and the landing pad214may not be formed to be coplanar with the upper surface of the second etch-stop layer170.FIG. 4shows that the upper surface of the lower electrode212is higher than the upper surface of the second etch-stop layer170, and that the upper surface of the landing pad214is lower than that of the second etch-stop layer170. Referring toFIG. 5A, in an alternative embodiment, however, the upper surfaces of the lower electrode212and the landing pad214may be substantially coplanar with the upper surface of the second etch-stop layer170. Referring toFIG. 5B, in another alternative embodiment, the upper surface of the lower electrode212may be lower than the upper surface of the second etch-stop layer170, and the upper surface of the landing pad214may be higher than the upper surface of the second etch-stop layer170.

That is, the planarization process may be performed until the upper surface of the second etch-stop layer170may be exposed, and thus the upper surfaces of the lower electrode212and the landing pad214may be formed to be substantially coplanar with the upper surface of the second etch-stop layer170. However, the second conductive layer and/or the second barrier layer that may form the lower electrode212and the landing pad214and that is removed by the planarization process may have elements that are different from that of the second etch-stop layer170, which may be also removed by the planarization process. Thus, the second conductive layer and/or the second barrier layer may not have upper surfaces that are substantially coplanar with the upper surface of the second etch-stop layer170in an actual planarization process. In particular, when a plurality of lower electrodes212and a plurality of landing pads214are formed, one or more of the lower electrodes212and one or more of the landing pads214may have upper surfaces that are substantially coplanar with the upper surface of the second etch-stop layer170. One or more of the lower electrodes212and one or more the landing pads214may, however, have upper surfaces that may be located at different heights from the upper surface of the second etch-stop layer170.

Even if upper surfaces of one or more of the lower electrodes212and one or more of the landing pad214are located at different heights from the upper surface of the second etch-stop layer170, the differences the different heights may not be so great, and in an example embodiment, the differences may be less than a thickness of the second etch-stop layer170.

Hereinafter, for the convenience of explanation, only the case shown inFIG. 4will be described.

The lower electrode212may include a fifth conductive pattern202and a fifth barrier pattern192that covers a bottom and a sidewall of the fifth conductive pattern202. The landing pad214may include a sixth conductive pattern204and a sixth barrier pattern194that covers a bottom and a sidewall of the sixth conductive pattern204.

Referring toFIG. 6, a planarization layer220may be formed on the lower electrode212, the landing pad214and the second etch-stop layer170. Layers that will form a magnetic tunnel junction (MTJ) structure layer260and an upper electrode layer270may be sequentially formed on the planarization layer220.

The planarization layer220may be formed of a conductive metal nitride, e.g., titanium nitride, tantalum nitride, etc. As described above, when the upper surfaces of the lower electrode212and the landing pad214are formed to be substantially coplanar with the upper surface of the second etch-stop layer170, the planarization layer220may not be formed. That is, the planarization layer220may not be needed if the upper surfaces of the lower electrode212and the landing pad214are formed to be substantially coplanar with the upper surface of the second etch-stop layer170.

The MTJ structure layer260may include a fixed magnetic layer structure230, a tunnel barrier layer240and a free magnetic layer250that are sequentially stacked.

In an example embodiment, the fixed magnetic layer structure230may include a pinning layer (not shown inFIG. 6), a lower ferromagnetic layer (not shown inFIG. 6), an anti-ferromagnetic coupling spacer layer (not shown inFIG. 6) and an upper ferromagnetic layer (not shown inFIG. 6).

The tunnel barrier layer240may be formed of, e.g., aluminum oxide or magnesium oxide.

Referring toFIG. 7, a photoresist pattern (not shown) may be formed on the upper electrode layer270, and the upper electrode layer270may be etched using the photoresist pattern as an etching mask to form an upper electrode272that may at least partially overlaps the lower electrode212.

The MTJ structure layer260and the planarization layer220may be sequentially etched using the upper electrode272as an etching mask to form a planarization pattern222and an MTJ structure262that may be sequentially stacked and may at least partially overlap the lower electrode212. The MTJ structure262may include a fixed magnetic pattern232, a tunnel barrier pattern242and a free magnetic pattern252that are sequentially stacked.

FIG. 7shows that the planarization pattern222covers the entire upper surface of the lower electrode212and is also formed on a portion of the second etch-stop layer170, however, the inventive concepts may not be limited thereto. The scope of the inventive concepts may include a situation in which a bottom surface of at least one planarization pattern222may be formed to at least partially contact the entire upper surface of the lower electrode212. That is, the bottom surface of at least one planarization pattern222may cover only a portion of the upper surface of the lower electrode212. Example embodiments in which the planarization pattern222does not cover the entire upper surface of the lower electrode212will be described later.

In example embodiments, the etching process may include a physical etching process, e.g., an IBE process. The second etch-stop layer170may include a material that may not be easily etched by the IBE process, and thus may remain after the etching process is performed. Thus, the second insulating interlayer160, which is under the second etch-stop layer170, may be protected by the second etch-stop layer170so not to be etched in the etching process. The lower electrode212, which is covered by the second insulating interlayer160, may not be etched either.

The landing pad214, which has been exposed by removing the planarization layer220, may hardly be etched because the second insulating interlayer160, which covers a sidewall of the landing pad214and the second etch-stop layer170on the second insulating interlayer160, may remain. Even if an upper portion of the landing pad214that has been exposed by the etching process may be partially etched, the amount of the landing pad214that may be etched in the etching process may be relatively small, and the upper surface of the remaining landing pad214may not be lower than an upper surface of the second insulating interlayer160. That is, a height of the upper surface of the landing pad214may be substantially coplanar with or lower than the height of the upper surface of the lower electrode212by a small amount.

Referring toFIG. 8, a third insulating interlayer280may be formed on the upper electrode272, the MTJ structure262, the planarization pattern222, the second etch-stop layer170and the landing pad214. A third wiring structure340may be formed through the third insulating interlayer280to commonly contact upper surfaces of the landing pad214and the upper electrode272.

The third insulating interlayer280may be formed of, e.g., silicon oxide or a low-k dielectric material, and the third wiring structure340may be formed by a dual damascene process.

In particular, third and fourth masks (not shown) may be sequentially formed on the third insulating interlayer280, and an upper portion of the third insulating interlayer280may be partially removed using the third and fourth masks as an etching mask. After removing the fourth mask, the third insulating interlayer280may be etched with the third mask remaining on the third insulating interlayer280. Thus, a third via hole (not shown) may be formed through a lower portion of the third insulating interlayer280to expose the upper surface of the landing pad214. A third trench (not shown) may be formed through an upper portion of the third insulating interlayer280to be in communication with the third via hole and to contact the upper surface of the upper electrode272.

Since the landing pad214may be formed on the second wiring structure145and keep an original height thereof in the previous etching process, the third via hole may not be formed to be relatively deep.

A third barrier layer may be formed on the exposed upper surfaces of the landing pad214and the upper electrode272, on the bottoms and sidewalls of the third via hole and the third trench, and on the third insulating interlayer280. A third conductive layer may be formed on the third barrier layer to fill remaining portions of the third via hole and the third trench. The third conductive layer and the third barrier layer may be planarized until an upper surface of the third insulating interlayer280may be exposed to form the third wiring structure340.

The third conductive layer may be formed by forming a seed layer (not shown) on the third barrier layer, and by performing an electroplating process. As described above, the third via hole may not be relatively deep, and thus the third conductive layer may be formed to sufficiently fill the third via hole, and no voids and/or seams may be formed in the third via hole.

The third barrier layer may be formed of a metal nitride, e.g., tantalum nitride, titanium nitride, etc., and/or a metal, e.g., tantalum, titanium, etc. The third conductive layer may be formed of a metal, e.g., tungsten, copper, aluminum, etc.

In example embodiments, the planarization process may be performed by a CMP process and/or an etch-back process.

The third wiring structure340may include a third via314and a third wiring345, which may be sequentially stacked and integrally formed with each other. The third via314may include a seventh conductive pattern304and a seventh barrier pattern294that covers a bottom and a sidewall of the seventh conductive pattern304. The third wiring345may include an eighth conductive pattern335and an eighth barrier pattern325that covers a portion of a bottom and a sidewall of the eighth conductive pattern335.

The MRAM device according to the subject matter disclosed herein may be manufactured by the above processes.

As described above, the second etch-stop layer170may be formed on the second insulating interlayer160so that the second insulating interlayer160may not be etched, but protected in the IBE process that forms the MTJ structure262. Thus, a sidewall of the lower electrode212that may be covered by the second insulating interlayer160may not be etched so that the elements of the lower electrode212may not be redeposited on the sidewall of the MTJ structure262. A sidewall of the landing pad214that may be covered by the second insulating interlayer160may not be etched to have a height that is similar to that of the lower electrode212. Accordingly, the third via hole exposing the upper surface of the landing pad214may not be relatively deep, and the third via314may be formed to sufficiently fill the third via hole with no voids and/or seams therein.

FIG. 9shows that not only the lower electrode,212but also a landing pad214may be formed on a first region I of the substrate100. That is, the inventive concepts may not be limited to a landing pad214on the peripheral region or the logic region of the substrate100, and may include a landing pad214together with the lower electrode212on the cell region of the substrate100.

FIGS. 10 to 14are cross-sectional views depicting stages of another method of manufacturing an MRAM device in accordance with example embodiments. This method may include processes substantially the same as or similar to those described with reference toFIGS. 1 to 9. Thus, like reference numerals refer to like elements, and detailed descriptions about like elements may be omitted below in the interest of brevity.

Referring toFIG. 10, processes that are substantially the same as or similar to those described with reference toFIGS. 1 and 2may be performed.

However, a fourth insulating interlayer165may be further formed on the second etch-stop layer170. The first etch-stop layer150, the second insulating interlayer160, the second etch-stop layer170and the fourth insulating interlayer165sequentially stacked may form an insulating interlayer structure161.

In example embodiments, the insulating interlayer structure161may have a thickness that is substantially equal or similar to a thickness of the insulating interlayer structure161shown inFIG. 2. Thus, the thickness of the insulating interlayer structure161may be less than that of the second insulating interlayer160.

Referring toFIG. 11, processes that are substantially the same as or similar to those described with reference toFIGS. 3 to 5may be performed.

The lower electrode212and the landing pad214may be formed through the sequentially stacked first etch-stop layer150, the second insulating interlayer160, the second etch-stop layer170and the fourth insulating interlayer165. Upper surfaces of the lower electrode212and the landing pad214may be formed to be substantially coplanar with, lower or higher by a small amount than the upper surface of the fourth insulating interlayer165.

Referring toFIG. 12, a process that is substantially the same as or similar to that described with reference toFIG. 6may be performed.

Thus, the planarization layer220may be formed on the lower electrode212, the landing pad214and the fourth insulating interlayer165. The MTJ structure layer260and the upper electrode layer270may be sequentially formed on the planarization layer220.

Referring toFIG. 13, a process that is substantially the same as or similar to that described with reference toFIG. 7may be performed.

Thus, the MTJ structure layer260and the planarization layer220may be sequentially etched using the upper electrode272as an etching mask to form the planarization pattern222and the MTJ structure262that may be sequentially stacked. The planarization pattern222and the MTJ structure262may at least partially overlap the lower electrode212.

The fourth insulating interlayer165may, however, be also etched in the etching process, and thus all portions of the fourth insulating interlayer165except a portion thereof under the planarization pattern222may be removed. As shown inFIG. 13, when the planarization pattern222covers the whole upper surface of the lower electrode212, the remaining portion of the fourth insulating interlayer165may cover a sidewall of the lower electrode212, which may be referred to as an insulation pattern167.

Since the second etch-stop layer170may remain on the second insulating interlayer160, the second insulating interlayer160may not be removed in the etching process. Thus, a sidewall of the lower electrode212may be covered by the insulation pattern167, the second etch-stop layer170and the second insulating interlayer160and not be etched in the etching process.

The landing pad214may be partially removed because most of the fourth insulating interlayer165may be removed. At least a portion of the landing pad214that is covered by the second insulating interlayer160may not, however, be removed, but remains. That is, an upper surface of the landing pad214may not be lower than a lower surface of the second etch-stop layer170or an upper surface of the second insulating interlayer160, and may keep the original height of the upper surface of the landing pad214. Accordingly, the landing pad214may be formed to have a desired height by controlling the thicknesses of the second insulating interlayer160, the second etch-stop layer170and/or the fourth insulating interlayer165.

Referring toFIG. 14, a process that is substantially the same as or similar to that described with reference toFIG. 8may be performed.

Thus, the third insulating interlayer280may be formed on the upper electrode272, the MTJ structure262, the planarization pattern222, the insulation pattern167, the second etch-stop layer170and the landing pad214. The third wiring structure340may be formed through the third insulating interlayer280to commonly contact upper surfaces of the landing pad214and the upper electrode272.

Since the landing pad214having the desired height may be formed on the second wiring structure145, the third via314of the third wiring structure340contacting the upper surface of the landing pad214may have good characteristics with no voids and/or seams therein.

FIGS. 15 to 18are cross-sectional views depicting stages of another method of manufacturing an MRAM device in accordance with example embodiments. This method may include processes that are substantially the same as or similar to those described with reference toFIGS. 1 to 9. Thus, like reference numerals refer to like elements, and detailed descriptions of like elements may be omitted below in the interest of brevity.

Referring toFIG. 15, processes that are substantially the same as or similar to those described with reference toFIGS. 1 and 2may be performed.

However, the first etch-stop layer150, the second etch-stop layer170and the second insulating interlayer160may, however, be sequentially formed on the first wiring structure140and the second wiring structure145and the first insulating interlayer110. Thus, the sequentially stacked first and second etch-stop layers150and170may form an etch-stop layer structure171.

Referring toFIG. 16, processes that are substantially the same as or similar to those described with reference toFIGS. 3 to 6may be performed.

Thus, the lower electrode212and the landing pad214may be formed through the first etch-stop layer150, the second etch-stop layer170and the second insulating interlayer160. Upper surfaces of the lower electrode212and the landing pad214may be formed to be substantially coplanar with, lower than or higher than the second insulating interlayer160by a small amount.

The planarization layer220may be formed on the lower electrode212, the landing pad214and the second insulating interlayer160. The MTJ structure layer260and the upper electrode layer270may be sequentially formed on the planarization layer220.

Referring toFIG. 17A, a process that is substantially the same as or similar to that described with reference toFIG. 7may be performed.

Thus, the MTJ structure layer260and the planarization layer220may be sequentially etched using the upper electrode272as an etching mask to form the planarization pattern222. The MTJ structure262that may be sequentially stacked and at least partially overlap the lower electrode212.

However, the second insulating interlayer160may be also etched in the etching process. That is, the MTJ structure layer260may be patterned by an IBE process, and since the second insulating interlayer160, which is under the planarization layer220, may be easily etched by the IBE process, an upper portion of the second insulating interlayer160may also be etched and transformed into a second insulating interlayer pattern163.

As the upper portion of the second insulating interlayer160is removed, a portion of the landing pad214that is covered by the upper portion of the second insulating interlayer160may be also removed. Thus, an upper surface of the remaining landing pad214may have a height that is lower than the original height.

Referring toFIG. 17B, when the IBE process is performed for a relatively long time, most of the second insulating interlayer160may be removed except for a portion of the second insulating interlayer160under the planarization pattern222. Thus, an upper surface of the landing pad214may have a relatively small height.

However, even in this case, since the second etch-stop layer170may remain, at least the underlying first etch-stop layer150and the first wiring structure140and the second wiring structure145that are covered by the first etch-stop layer150may not be exposed to the etch.

Referring toFIG. 18A, a process that is substantially the same as or similar to that described with reference toFIG. 8may be performed to complete the MRAM device.

Thus, the third insulating interlayer280may be formed on the upper electrode272, the MTJ structure262, the planarization pattern222, the second insulating interlayer pattern163, and the landing pad214. The third wiring structure340may be formed through the third insulating interlayer280to commonly contact upper surfaces of the landing pad214and the upper electrode272.

FIG. 18Bshows a resultant structure after performing the above process on the structure shown inFIG. 17B.

FIG. 18Cshows a resultant structure after the above process when the first etch-stop layer150described with reference toFIG. 15is not formed.

That is, the second etch-stop layer170and the second insulating interlayer160may be sequentially formed on the first wiring structure140and the second wiring structure145and the first insulating interlayer110. The first wiring structure140and the second wiring structure145may be protected by the second etch-stop layer170so not to be exposed or etched by the IBE process.

FIGS. 19 to 20are cross-sectional views depicting stages of another method of manufacturing an MRAM device in accordance with example embodiments. This method may include processes substantially the same as or similar to those described with reference toFIGS. 1 to 9. Thus, like reference numerals refer to like elements, and detailed descriptions of like elements may be omitted below in the interest of brevity.

Referring toFIG. 19A, processes that are substantially the same as or similar to those described with reference toFIGS. 1 and 7may be performed.

However, the planarization pattern222and the MTJ structure262formed by an IBE process may not cover the whole upper surface of the lower electrode212, but may cover only a portion of the upper surface of the lower electrode212, which may occur due to the misalignment and/or the layout of the MTJ structures262.

Thus, an upper portion of the lower electrode212that has been exposed by the IBE process may be also removed. The second etch-stop layer170may, however, still remain on the second insulating interlayer160. Thus, an amount of a re-deposited portion of the exposed lower electrode212on the sidewall of the MTJ structure262due to the removal thereof may be relatively small.

FIG. 19Bshows a comparative example having no second etch-stop layer on the second insulating interlayer160.

As the second etch-stop layer170is not formed, an upper portion of the second insulating interlayer160may be also removed in the IBE process. Thus, an upper portion of the lower electrode, which is covered by the second insulating interlayer160, may be also removed. Thus, an amount of the exposed lower electrode212that is redeposited on the sidewall of the MTJ structure262due to the removal of the exposed lower electrode212may be relatively large.

As a result of the etching process, the lower electrode212may remain as an exposed lower electrode pattern213, and the second insulating interlayer160may be transformed into a second insulating interlayer pattern163. That is, a portion of the exposed lower electrode212may be etched, thereby forming a exposed lower electrode patter213. Similarly, the second insulating interlayer160may be etched, thereby forming a second insulating interlayer pattern163.

A landing pad pattern215having a reduced height may remain in the second insulating interlayer pattern163. The remaining landing pattern215may include a ninth conductive pattern205and a ninth barrier pattern195that covers a bottom and a sidewall of the ninth conductive pattern205.

FIG. 19Cshows a comparative example having no second etch-stop layer on the second insulating interlayer160. In this case, as the IBE process is performed, most of the second insulating interlayer160may be removed except for a portion of the second insulating interlayer160under the planarization pattern222and the first etch-stop layer150may be removed.

Thus, an amount of the exposed lower electrode212may be redeposited on the sidewall of the MTJ structure262due to the removal of the exposed lower electrode212may be relatively large, and the first wiring142of the first wiring structure140may be exposed to cause an electrical short. Additionally, the landing pad214may not remain, but be removed so that voids and/or seams may be formed in a third via of a third wiring structure340.

Referring toFIG. 20A, a process that is substantially the same as or similar to that described with reference toFIG. 8may be performed.

Thus, the third insulating interlayer280may be formed on the upper electrode272, the MTJ structure262, the planarization pattern222, the second etch-stop layer170, the exposed lower electrode212and the landing pad214. A third wiring structure340may be formed through the third insulating interlayer280to commonly contact upper surfaces of the landing pad214and the upper electrode272.

FIG. 20Bshows that the fourth insulating interlayer165may be formed on the second etch-stop layer170and transformed into the insulation pattern167that covers an upper sidewall of the exposed lower electrode212.FIG. 20Cshows that when the second etch-stop layer170and the second insulating interlayer160are sequentially formed on the first etch-stop layer150, the second insulating interlayer pattern163may remain covering a sidewall of the lower electrode212.

FIGS. 21 to 23are cross-sectional views depicting stages of another method of manufacturing an MRAM device in accordance with example embodiments. This method may include processes substantially the same as or similar to those described with reference toFIGS. 1 to 9. Thus, like reference numerals refer to like elements, and detailed descriptions of like elements may be omitted below in the interest of brevity.

Referring toFIG. 21, processes that are substantially the same as or similar to those described with reference toFIGS. 1 and 3may be performed.

However, the second insulating interlayer160may be formed to have a thickness that is less than a thickness of the second insulating interlayer160ofFIG. 2. In an example embodiment, the second insulating interlayer160ofFIG. 21may have a thickness that may be about half of the thickness of the second insulating interlayer160ofFIG. 2.

Only the first opening182that exposes an upper surface of the first wiring structure may be formed, while no second opening that exposes an upper surface of the second wiring structure145may be formed.

Referring toFIG. 22, a process that is substantially the same as or similar to that described with reference toFIGS. 4 to 7may be performed.

The electrode212may, however, be formed through the insulating interlayer structure161to contact an upper surface of the lower electrode212, while no landing pad may be formed through the insulating interlayer structure161to contact an upper surface of the second wiring structure145.

Referring toFIG. 23A, a process that is substantially the same as or similar to that described with reference toFIG. 8may be performed.

The third via314of the third wiring structure340may, however, be formed to directly contact an upper surface of the second wiring144of the second wiring structure145.

That is, no landing pad may be formed on the second wiring structure145, and thus the third wiring structure340may be directly connected to the second wiring structure145. Since the second insulating interlayer160may have a relatively small thickness, even if no landing pad exists, the third via hole may not be formed to have a deep depth. Thus, the third via314may sufficiently fill the third via hole.

If, however, the second etch-stop layer170is not formed when the second insulating interlayer160has a relatively small thickness, as described with reference toFIGS. 19B and 19C, the second insulating interlayer160may be removed in the IBE process to expose upper surfaces of the first wiring structure140and the second wiring structure145, which may cause an electrical short. However, in example embodiments, since the second etch-stop layer170may be formed on the second insulating interlayer160, even if the second insulating interlayer160may have a relatively small thickness, the second insulating interlayer160may not be completely removed. Thus, the upper surfaces of the first wiring structure140and the second wiring structure145may not be exposed.

FIG. 23Bshows that the MTJ structure262may overlap a portion of the upper surface of the lower electrode212.

FIGS. 24 to 25are cross-sectional views depicting stages of another method of manufacturing an MRAM device in accordance with example embodiments. This method may include processes that are substantially the same as or similar to those described with reference toFIGS. 21 to 23. Thus, like reference numerals refer to like elements, and detailed descriptions of like elements may be omitted below in the interest of brevity.

Referring toFIG. 24, processes that are substantially the same as or similar to those described with reference toFIG. 21may be performed.

The first etch-stop layer150, the second etch-stop layer170and the second insulating interlayer160may, however, be sequentially formed on the first wiring structure140and the second wiring structure145and the first insulating interlayer110.

Referring toFIG. 25A, a process that is substantially the same as or similar to that described with reference toFIGS. 22 to 23may be performed.

The lower electrode212may be formed through the first and second etch-stop layers150and170to protrude from an upper surface of the second etch-stop layer170. The second insulation interlayer pattern163may cover a sidewall of the protruding lower electrode212.

FIG. 25Bshows that the MTJ structure262may overlap a portion of an upper surface of the lower electrode212.

FIGS. 26 to 28are cross-sectional views depicting stages of another method of manufacturing an MRAM device in accordance with example embodiments. This method may include processes that are substantially the same as or similar to those described with reference toFIGS. 1 to 9, and detailed descriptions of those processes may be omitted below in the interest of brevity.

Referring toFIG. 26, first and second gate structures442and444may be formed on a substrate400having an isolation layer405. First and second impurity regions401and403may be formed at upper portions of the substrate400that are adjacent to the first gate structure442. A third impurity region407may be formed at an upper portion of the substrate400adjacent to the second gate structure444.

The substrate400may include first and second regions I and II, and in example embodiments, the first region I may serve as a cell region and the second region II may serve as a peripheral region or a logic region. The isolation layer405may be formed of an oxide, e.g., silicon oxide. In example embodiments, the isolation layer405may be formed by a shallow trench isolation (STI) process.

The first gate structure442may include a first gate insulation pattern412, a first gate electrode422and a first gate mask432that are sequentially stacked on the first region I of the substrate400. The second gate structure444may include a second gate insulation pattern414, a second gate electrode424and a second gate mask434that are sequentially stacked on the second region II of the substrate400.

First and second gate spacers452and454may be further formed on the respective sidewalls of the first and second gate structures442and444.

The first to third impurity regions401,403and407may be doped with n-type or p-type impurities. In an example embodiment, the first to third impurity regions401,403and407may be formed by doping impurities into upper portions of the substrate400. Alternatively, the first to third impurity regions401,403and407may be formed by forming recesses at upper portions of the substrate400and performing a selective epitaxial growth (SEG) process to fill the recesses. The first to third impurity regions401,403and407may include single crystalline silicon, single crystalline silicon carbide, or single crystalline silicon-germanium.

The first and second gate structures442and444together with the first to third impurity regions401,403and407may form transistors. In an example embodiment, the transistors may be planar transistors. Although not depicted inFIG. 26, the transistors may alternatively be fin-type field effect transistors (finFETs). As yet another non-depicted embodiment, the transistors may alternatively be vertical-channel transistors.

Referring toFIG. 27, a first insulating interlayer460may be formed on the substrate400to cover the first and second gate structures442and444and the first and second gate spacers452and454. First to third contact plugs471,472and474may be formed through the first insulating interlayer460to respectively contact the first to third impurity regions401,403and407.

The first to third contact plugs471,472and474may be formed of a metal, a metal nitride, doped polysilicon and/or a metal silicide.

A second insulating interlayer480may be formed on the first to third contact plugs471,472and474and the first insulating interlayer460. First to third wirings511,512and514may be formed through the second insulating interlayer480to respectively contact the first to third contact plugs471,472and474.

In example embodiments, the first to third wirings511,512and514may be formed by a single damascene process. Alternatively, the first to third wirings511,512and514may be formed by a dual damascene process.

Accordingly, the first wiring511may include a first conductive pattern501and a first barrier pattern491that covers a bottom and a sidewall of the first conductive pattern501. The second wiring512may include a second conductive pattern502and a second barrier pattern492that covers a bottom and a sidewall of the second conductive pattern502The third wiring514may include a third conductive pattern504and a third barrier pattern494that covers a bottom and a sidewall of the third conductive pattern504.

The first to third conductive patterns501,502and504may be formed of a metal, e.g., tungsten, copper, aluminum, etc. The first to third barrier patterns491,492and494may be formed of a metal nitride, e.g., tantalum nitride, titanium nitride, etc., and/or a metal, e.g., tantalum, titanium, etc.

The first wiring511may serve as a source line of for an MRAM device according to the subject matter disclosed herein.

Referring toFIG. 28, processes that are substantially the same as or similar to those described with reference toFIGS. 1 to 9may be performed.

Thus, a third insulating interlayer610may be formed on the first to third wirings511,512and514and the second insulating interlayer480. A fourth wiring structure642and a fifth wiring structure644may be formed through the third insulating interlayer610.

The fourth wiring structure642may include a first via641and a first wiring632that may be integrally formed with each other. The fifth wiring structure644may include a second via624and a second wiring634that may be integrally formed with each other.

The first via641may include a fourth conductive pattern631and a fourth barrier pattern621that covers a bottom and a sidewall of the fourth conductive pattern631. The second via643may include a fifth conductive pattern633and a fifth barrier pattern623that covers a bottom and a sidewall of the fifth conductive pattern633. The fourth wiring642may include a sixth conductive pattern632and a sixth barrier pattern622that covers a portion of a bottom and a sidewall of the sixth conductive pattern632. The fifth wiring644may include a seventh conductive pattern634and a seventh barrier pattern624that covers a portion of a bottom and a sidewall of the seventh conductive pattern634.

An insulating interlayer structure including a first etch-stop layer650, a fourth insulating interlayer660and a second etch-stop layer670that are sequentially stacked may be formed on the fourth and fifth wiring structures and the third insulating interlayer610, and a lower electrode712. A landing pad714may be formed through the insulating interlayer structure to respectively contact the fourth and fifth wiring structures on the first and second regions I and II.

The lower electrode712may include an eighth conductive pattern702and an eighth barrier pattern692that covers a bottom and a sidewall of the eighth conductive pattern702. The landing pad714may include a ninth conductive pattern704and a ninth barrier pattern694that covers a bottom and a sidewall of the ninth conductive pattern704.

A planarization pattern822, an MTJ structure862and an upper electrode872may be sequentially stacked on the lower electrode712to at least partially overlap the lower electrode712. The MTJ structure862may include a fixed magnetic pattern832, a tunnel barrier pattern842and a free magnetic pattern852that are sequentially stacked. In one embodiment, a plurality of MTJ structures862may be organized in an array that is arranged to have at least one row and at least one column when viewed from a plan view ofFIG. 28. As viewed in the cross-sectional view ofFIG. 28, a portion of one row of an array of MTJ structures862is shown. It should be understood that if a plurality of MTJ structures862are arranged in an array of at least one row and at least one column, the array may be included in a first region I. Similarly, if a plurality of MTJ structures862are arranged in an array of at least one row and at least one column, the structures and features described herein as part of the subject matter disclosed herein may also be included in either a first region I and/or a first region II.

A fifth insulating interlayer880may be formed on the second etch-stop layer670and the landing pad714to cover the upper electrode872, the MTJ structure862and the planarization pattern822. A sixth wiring structure946may be formed through the fifth insulating interlayer880to commonly contact the landing pad714and the upper electrode872.

The sixth wiring structure946may include a third via914and a sixth wiring945that may be integrally formed. In example embodiments, the sixth wiring945may serve as a bit line for a MRAM device according to the subject matter disclosed herein.

The third via914may include a tenth conductive pattern904and a tenth barrier pattern894that covers a bottom and a sidewall of the tenth conductive pattern904. The sixth wiring945may include an eleventh conductive pattern935and an eleventh barrier pattern925that covers a bottom and a sidewall of the eleventh conductive pattern935.

FIG. 29depicts an electronic device2900that comprises one or more integrated circuits (chips) comprising a semiconductor device that includes an MRAM according to embodiments disclosed herein. Electronic device2900may be used in, but not limited to, a computing device, a personal digital assistant (PDA), a laptop computer, a mobile computer, a web tablet, a wireless phone, a cell phone, a smart phone, a digital music player, or a wireline or wireless electronic device. The electronic device2900may comprise a controller2910, an input/output device2920such as, but not limited to, a keypad, a keyboard, a display, or a touch-screen display, a memory2930, and a wireless interface2940that are coupled to each other through a bus2950. The controller2910may comprise, for example, at least one microprocessor, at least one digital signal process, at least one microcontroller, or the like. The memory2930may be configured to store a command code to be used by the controller2910or a user data. Electronic device2900and the various system components comprising a semiconductor device that includes an MRAM according to embodiments disclosed herein. The electronic device2900may use a wireless interface2940configured to transmit data to or receive data from a wireless communication network using a RF signal. The wireless interface2940may include, for example, an antenna, a wireless transceiver and so on. The electronic system2900may be used in a communication interface protocol of a communication system, such as, but not limited to, Code Division Multiple Access (CDMA), Global System for Mobile Communications (GSM), North American Digital Communications (NADC), Extended Time Division Multiple Access (E-TDMA), Wideband CDMA (WCDMA), CDMA2000, Wi-Fi, Municipal Wi-Fi (Muni Wi-Fi), Bluetooth, Digital Enhanced Cordless Telecommunications (DECT), Wireless Universal Serial Bus (Wireless USB), Fast low-latency access with seamless handoff Orthogonal Frequency Division Multiplexing (Flash-OFDM), IEEE 802.20, General Packet Radio Service (GPRS), iBurst, Wireless Broadband (WiBro), WiMAX, WiMAX-Advanced, Universal Mobile Telecommunication Service-Time Division Duplex (UMTS-TDD), High Speed Packet Access (HSPA), Evolution Data Optimized (EVDO), Long Term Evolution-Advanced (LTE-Advanced), Multichannel Multipoint Distribution Service (MMDS), and so forth.

FIG. 30depicts a memory system3000that may comprise one or more integrated circuits (chips) comprising a semiconductor device that includes an MRAM according to embodiments disclosed herein. The memory system3000may comprise a memory device3010for storing large amounts of data and a memory controller3020. The memory controller3020controls the memory device3010to read data stored in the memory device3010or to write data into the memory device3010in response to a read/write request of a host3030. The memory controller3020may include an address-mapping table for mapping an address provided from the host3030(e.g., a mobile device or a computer system) into a physical address of the memory device3010. The memory device3010may comprise one or more semiconductor devices a semiconductor device that includes an MRAM according to embodiments disclosed herein.