Memory device including multiplexed inputs

Systems and methods are described for reducing the number of exterior contacts on a semiconductor package without reducing the number of address, data and control signals used by an integrated circuit interior to the semiconductor package. In some embodiments, two signals may be received at a shared conductor accessible by devices exterior to the semiconductor package and communicated to two contacts on the integrated circuit that are inaccessible to the exterior of the semiconductor package. In various embodiments, signals required to support a full set of features of the JEDEC JESD79E standard or the JEDEC JESD79-2C standard are communicated using a reduced number of exterior contacts.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to semiconductor devices, and more particularly to packaging semiconductor devices.

2. Description of Related Art

Integrated circuits, for example memory, are used in a wide variety of applications. Typically, memory conforms to accepted standards. For example, many memory standards are defined by the Joint Electron Device Engineering Council, also known as the JEDEC Solid State Technology Association (JEDEC). Designs for memory that conform to standards such as JEDEC standards are well known. Moreover, memory layouts and lithographic masks for standard memories are readily available. It is desirable to use such standard memory designs in an application rather than redesigning the memory specifically for a different application. However, the number of external contacts used for standard memory is determined by the standard for the memory design. The minimal size of the package sometimes is limited by the number and pitch of the contacts. This is a disadvantage of the prior art.

FIG. 1illustrates a prior art standard (JESD79C) timing diagram for a memory bank write operation. In this standard, a first set of inputs A0-An, A10, BA0and BA1are used to input an address and a second set of inputs DQ and DM are used to write data values starting at the address. The data values are written several clock cycles after the address as input.

FIG. 2illustrates a timing diagram for a memory bank read operation according to the prior art standard ofFIG. 1. In this operation, inputs A0-An, A10, BA0and BA1are used to input an address and DQ and DQS are used to output data stored starting at that address. The data values are read several clock cycles after the address as output.

FIG. 3illustrates a prior art bond pad layout for a memory device proposed by JEDEC. The illustration includes 79 bottom pads and 44 top pads. A variety of data (DQ, DQS and DM), address (A, BA) pads are illustrated. This particular configuration includes 32 DQ pads and, thus, can handle 32-bit data.

SUMMARY OF THE INVENTION

Various embodiments of the invention include a package having a memory, internal memory contacts on an integrated circuit substrate, and external contacts for communicating signals between the memory contacts and external devices. The internal memory contacts optionally conform to an industry standard such as the JEDEC JESD79E standard or the JEDEC JESD79-2C standard. One or more of the external contacts are shared contacts configured to communicate signals to different members of the memory contacts at different times and/or in different modes. The package may include fewer external contacts than internal memory contacts. By reducing the number of external contacts, smaller package sizes may be achieved.

The package further includes interface circuits disposed between the memory contacts and the shared external contacts. In various embodiments, the interface circuits include latches, multiplexers, PROMs, buffers, and/or the like. In some embodiments, one of the interface circuits is configured to communicate an address signal from an address memory contact to a shared external contact in an address mode, and communicate a data signal between a data memory contact and the shared external contact in a data mode. Alternatively, the interface circuit is configured to communicate an address signal and a control signal, or a data signal and a control signal, between the shared external contact and a respective address memory contact, data memory contact, or control memory contact.

Various embodiments of the invention include a memory device comprising a plurality of memory cells configured to store data, a first memory contact configured to communicate data signals to or from the plurality of memory cells, a second memory contact configured to communicate address signals or command signals to the plurality of memory cells, a shared external contact configured to communicate the data signals in a first mode, and to receive the address signals or the command signals in a second mode, an interface configured to communicate the data signals between the shared external contact and the first memory contact in the first mode, and to communicate the address signals or the command signals from the shared external contact to the second memory contact in the second mode, a control input configured to change a mode of the memory device between the first mode and the second mode, and a semiconductor package including the plurality of memory cells, at least part of the shared electrical conductor, and the interface.

Various embodiments of the invention include a system comprising a semiconductor package, a plurality of memory cells incorporated in the semiconductor package and configured to store data, the memory cells coupled to a first memory contact and a second memory contact, a shared contact at least partially external to the semiconductor package and configured to receive a first signal in a first mode and a second signal in a second mode, a first circuit incorporated in the semiconductor package and configured to communicate the first signal between the shared contact and the first conductor in the first mode, a second circuit incorporated in the semiconductor package and configured to communicate the second signal between the shared contact and the second conductor in the second mode, and a control input to the semiconductor package and configured for changing between the first mode and the second mode.

Various embodiments of the invention include a memory device comprising a plurality of memory cells configured to store data and coupled to a first memory contact and a second memory contact, a shared contact configured to receive a first signal during a first time period and a second signal during a second time period, a circuit configured to communicate the first signal between the shared contact and the first memory contact during the first time period and communicate the second signal between the device contact and the second memory contact during the second time period, and a semiconductor device package including the plurality of memory cells, at least part of the shared contact, and the circuit.

Various embodiments of the invention include a system comprising a semiconductor package containing a memory configured to store data, a first memory contact electronically coupled to the memory, a second memory contact electronically coupled to the memory, a first shared contact external to the memory, the first shared contact configured to communicate with a device external to the semiconductor package, and configured to receive a first signal in a first mode and a second signal in a second mode, and at least one multiplexer circuit configured to convey the first signal from the first terminal to the first memory contact when the memory is in the first mode, and to convey the second signal from the first terminal to the second memory contact when the memory is in the second mode.

DETAILED DESCRIPTION

Multiplexing is used to communicate signals between a memory circuit and external contacts. The memory circuit and external contacts may be associated within a SIP (system-in-package), PoP (package-on-package), or the like. In some embodiments the memory circuit includes the testing interface described in U.S. patent application Ser. No. 11/304,445 entitled “Integrated Circuit Testing Module” and filed Dec. 14, 2005, or the testing interface described in U.S. Pat. No. 6,882,171 issued Apr. 19, 2005 both of which are hereby incorporated herein by reference. In various embodiments, the multiplexed signals communicated between the external contacts and the memory circuits include data, addresses, and/or commands. In various embodiments, the multiplexed signals are configured for accessing memory circuits. For example, in some embodiments, addresses and data are communicated through a shared external contact. In various embodiments, addresses and commands, or data and commands are communicated through a shared external contact.

FIG. 4illustrates a semiconductor package400in accordance with various embodiments of the invention. The semiconductor package400includes a memory420, an interface410and external contacts,430,440and450. Although the semiconductor package400as illustrated includes an interface410, a memory420, and external contacts430,440, and450, the semiconductor package400may include fewer or more components and still fall within the scope of various embodiments.

The memory420includes memory contacts461-464and memory circuitry425internal to the memory420. The memory circuitry includes an array of memory cells and memory interface logic configured to receive signals according to standard communications protocol and provide access to the array of memory cells.

The memory contacts461-464are typically physically inaccessible to external devices and are part of the same wafer as the memory circuitry425. The memory contacts461-464are electronically coupled to the memory circuitry425via a plurality (e.g., “n”) of conductors. The memory contacts461-464are configured to communicate signals1-4respectively between the interface410and the memory circuitry425of the memory420. The memory contacts461-464may include a pad, contact, trace, conductor, bond, test point, solder pad, bond pad, contact pad, and/or the like. Although the memory420is illustrated as having memory circuitry425and memory contacts461-464, fewer or more memory contacts and/or more memory circuits may be included in the memory420and still fall within the scope of various embodiments.

The external contacts430,440and450are accessible from outside the semiconductor package400and are configured for making electrical contact with one or more external devices (not shown). The external contacts430,440and450are not typically part of the wafer on which the memory circuitry425is fabricated. The external contacts430,440and450may include a connector, pin, post, balls, socket, support balls, wire wrap pin, test point, solder pad, contact pad, and/or the like.

The external contact430is configured to communicate a signal1and a signal2between an external device and the interface410. The external contact440is configured to communicate a signal3and a signal4between an external device and the interface410.

External contact450is configured to receive a mode signal and couple the mode signal to the interface410. The mode signal is configured to place the interface410alternatively in a first or a second state. In some embodiments, the interface410is responsive to the logic state of the mode signal. For example, the interface410is placed in the first state when the mode signal is a logical 1 and in the second state when the mode signal is a logical 0. Alternatively, the interface410is in the first state unless a logical 1 is asserted by the mode signal. In some embodiments, the interface410is responsive to a change of state the mode signal. For example, the interface410may default to the first state until receiving a pulse from the mode signal. Then the interface410may be placed in the second state for a predetermined period of time and return the first state. The predetermined period of time may be detected using analog circuitry or digital logic (e.g., a clock, a clock and a counter, a clock and a shift register, and/or the like). Alternatively, the interface may change state between the first state and the second state when receiving a pulse from the mode signal. In some embodiments, a serial bit pattern (e.g., 01010) may place the interface410in the first state and another logical pattern (e.g., 01100) may place the interface410in the second state. Serial bit patterns may be defined that place the interface410in additional states (e.g., 3, 4, 8, 16, or more states).

In some embodiments, external contact450is optional. In these embodiments, the interface410is by default in a first mode and after receipt of signals in the first mode automatically switches to a second mode. After signals are received in the second mode or after a number of clock cycles, the interface410automatically switches back to the first mode. For example, the interface410may be by default in an address mode. After address data and a READ or WRITE command are received by the semiconductor package400, the interface410automatically switches to a data mode in which data is communicated through the same shared external contacts as the address data was received. These modes are discussed further elsewhere herein. While the examples discussed herein refer to a mode signal received through the external contact450, it should be understood that in these examples this mode signal may be generated automatically using circuits within interface410, and that external contact450is optional.

The interface410may be a part of the same wafer as the memory circuitry425. Alternatively, the external contacts430,440, and/or450may be a part of the interface410. In some embodiments, the interface410includes one or more discrete devices separate from the memory420and the external contacts430,440, and/or450. Examples of the interface410include multiplexers, buffers, ASICS, and/or the like.

The interface410receives the mode signal from the external contact450. When the mode signal places the interface410in the first state, the interface410is configured to couple signal1between the external contact430and the memory contact461and couple signal3between the external contact440and the memory contact463. When the mode signal places the interface410in the second state, the interface410is configured to couple signals2and4between the external contacts430and440and the memory contacts462and464respectively. Thus, one external contact430can be shared between the memory contacts461and462. Likewise, one external contact440can be shared between the two memory contacts463and464. Thus, the four signals1-4can be communicated between memory contacts461-464and an external device via two external contacts430and440. In some embodiments, it is assumed that the signal received at external contact430is signal1unless a received command or other signal (e.g. an internally generated signal or a signal received via external contact450) indicates otherwise.

In various embodiments, signals1and3include address signals and signals3and4include data signals. For example, when mode signal places the interface410in the first state, the address signals1and3are input from the external contacts430and440via the interface410to the memory contacts461and463respectively. When the mode signal places the interface410in the second state during a read operation, the data signals2and4are output from the memory contacts462and464via the interface410to the external contacts430and440respectively. Alternatively, during a write operation when the mode signal is in the second state, the data signals2and4are input to the memory contacts462and464via the interface410from the external contacts430and440respectively.

In some embodiments, signals1and3include address signals and signals2and4included control signals. Alternatively, signals1and3include data signals and signals2and4include control signals. In some embodiments, it is assumed that the signal received at external contact430is an address signal unless a received command (e.g., a mode signal) or other signal indicates otherwise. While the interface410is illustrated as being configured to coupling two shared external contacts to two pair of memory contacts, the interface410may be configured to couple more or fewer shared external contacts to pairs of memory contacts and still fall within the scope of various embodiments. For example, the interface410may be configured to couple at least 1, 3, 4, 8, 16 or 32 shared external contacts to pairs of memory contacts.

FIG. 5illustrates the semiconductor package400including an alternative embodiment of the interface410ofFIG. 1.FIG. 5differs fromFIG. 4in that the interface410is shown as two interfaces namely, interface510A and510B. External contact450is configured to couple the mode signal to both the interface510A and interface510B. The mode signal is configured to place the interface510A and interface510B alternatively in a first or a second state. As discussed elsewhere herein, the interface510A and/or510B may be responsive to the logical state of the mode signal, the change in the mode signal, a serial bit pattern of the mode signal, and/or the like.

The interface510A is configured to couple the shared external contact430to the memory contact461while in the first state and couple the shared external contact430to the memory contact462while in the second state. Likewise, the interface510B is configured to couple the shared external contact440to the memory contact463in a first state and to the memory contact464in a second state. Thus, the external contact430may be shared between the memory contacts461and462through the interface510A and the external contact440may be shared between the memory contacts463and464through the interface510B. Examples of the interface510A and510B include gates, multiplexers, latches, buffered latches, ASICS, and/or the like.

In some embodiments, the signals received at external contact450are buffered, interpreted or otherwise processed before being used to control the interface510A. In typical embodiments, the external contacts430and440are part of a plurality of shared external contacts configured for communicating data in parallel to the memory420via a plurality of interfaces510.

FIG. 6illustrates details of the interface510A according to various embodiments of the invention. These embodiments include the external contacts430, external contact450, memory contact461and memory contact462. The external contact440, memory contact463, and memory contact464illustrated inFIGS. 4 and 5are omitted for clarity. As illustrated inFIG. 6, the external contact430is configured to communicate data signals and address signals between an external device (not shown) and the interface510A. In some embodiments, the external contact430is configured to communicate data signals between a first external device and the memory420, and to communicate address signals between a second external device and the memory420.

In some embodiments, the mode signal is configured to place the interface510A in an address mode or a data mode. In the address mode, address signals are communicated from the external device to the memory420. In the data mode, data signals are communicated between the external device and the memory420. As discussed elsewhere herein, data may be read and/or written several clock cycles, after the address is sent to the memory420. Thus, a mode change from the address mode to the data mode may occur one or more clock cycles after the address signals are communicated.

The interface510A is configured to receive a read/write signal that places the interface510A in a read state or a write state for controlling whether the data is read from or written to the memory420. In the read state, data is communicated via the interface510A from the memory420to the external device. In a write state, the data is communicated via the interface510A from the external device to the memory420. In various embodiments, the read/write signal may be received from the memory420, from another circuit within the semiconductor package400or an external device via an external contact (not shown).

The interface510A includes latches610,620and630, and buffers615,625,645and655. In various embodiments, the buffers615,625,645and/or655may be inverting, non-inverting, tri-state, open collector, and/or the like. The latches610,620and/or630may include circuitry (e.g., gates, buffers, counters, multiplexers, and/or the like) for signal manipulation and/or conditioning. The shared external contact430is coupled to one or more buffers in the interface510A, e.g., the buffers615,625and635. The external contact450couples the mode signal to one or more latches610,620, and630.

The mode signal places the interface510A in the address mode by disabling the latches610and620and enabling the latch630. When the interface510A is in the address mode, the buffer635is configured to receive an address signal from the external contact430and provide the address signal into the latch630. The latch630is configured to latch the address signal and provide the address signal to the memory contact461.

After receiving an address signal in the address mode, the mode signal can place the interface510A in the data mode by disabling the latch630and enabling the latches610and620. In the data mode, the interface510A is configured to either communicate data from the memory420to the external device in the read state, or communicate data from the external device to the memory420in the write state.

For reading data, the read/write signal is configured to place the interface510in a read state by disabling the latch620and the leaving latch610enabled. While the interface510A is in the data mode and the read state, the memory contact462is configured communicate a data signal from the memory circuitry425to the buffer645in the interface510A. The buffer645is configured to communicate the data signal to the latch610, which is configured to latch and provide the data signal to the buffer615. The external contact430is configured to communicate the data signal from the buffer615to the external device. During a block read, the interface510A may remain in the data mode for multiple clock cycles while the memory circuitry425provides multiple data signals to the external device through the memory contact462, buffer645, latch610, buffer615and external contact430.

For writing data, the read/write signal is configured to place the interface510in the write state by disabling the latch610and leaving the latch620enabled. While the interface is in the data mode and the write state, the external contact430is configured to communicate a data signal from the external device to the buffer625in the interface510A. The buffer625is configured to provide the data signal to the latch620for output to the buffer655. The memory contact462is configured to communicate the data signal from the buffer655to the memory circuitry425. During a block write, the interface510A may remain in the data mode for multiple clock cycles while the external device provides multiple data signals to the memory circuitry425through the external contact430, buffer625, latch620, buffer655, and memory contact462.

Thus, the external contact430is configured to communicate both address and bidirectional data. The external contact430can communicate address signals while the interface510A is in the address mode, and can communicate both read data and write data while the interface510A is in the data mode.

FIG. 7is a timing diagram illustrating the use of the interface510A for writing data to the memory420, according to various embodiments of the invention. The address signals and the data signals inFIG. 7are both communicated through the external contact430. The signals at the external contact430are illustrated by a Timing Trace710. At a Third Clock Cycle720, an ACT command and row address signals are received. At a Tenth Clock Cycle730a WRITE command and column address signals are received. The WRITE command is configured to set latches610,620and630in a state for receiving data signals rather than address signals. In some embodiments, external contact450is one of the external contacts used to receive the WRITE command. In some embodiments, WRITE command is used by circuitry within semiconductor package400to generate a mode signal. At approximately an Eleventh Clock Cycle740, data signals are received at the external contact430. Interface510A is optionally automatically returned to the address mode after the data signals are received. The various clock cycles discussed herein represent different time periods.

Typically, two or more (e.g., A0-An) instances of external contacts430are configured to receive address signals and data signals in parallel according to the timing diagram ofFIG. 7. For example,FIGS. 4 and 5illustrate two instances of external contacts, namely external contacts430and440. External contacts430and440are configured to receive address signals and data signals in parallel, where signals1and3are address signals and signals2and4are data signals. In some embodiments, there are a greater number of data channels (bits) than address channels and some of the data signals are optionally received at external contacts that are not shared. In some embodiments, there are a greater number of address channels (bits) than data channels and some of the address signals are optionally received at external contacts that are not shared. The parallel address signals and the data signals may be received at (m) instances of shared external contacts (e.g., external contact430) where (m) is the maximum number of address bits and data bits that can be shared.

FIG. 8is a timing diagram illustrating the use of the interface510A for reading data from memory, according to various embodiments of the invention. As illustrated inFIG. 8, an ACT command and a row address is received at the Third Clock Cycle820. The row address is received at the external contact430. At the Eleventh Clock Cycle830a READ command and a column address is received at the external contact430. Receipt of the READ command is optionally used to generate a mode signal configured to change the state of the interface510A to a data state. Starting at approximately a Fifteenth Clock Cycle840, a PRECHARGE command is received and data is sent out of the external contact430to an external device. As in the process illustrated inFIG. 7, each of these communications may include the receipt or transmission of several bits in parallel using multiple shared external contacts (e.g., external contact430).

While the embodiments illustrated inFIGS. 3-8include multiplexing of address and data signals, a similar approach may be used to multiplex data and command signals, and/or address and command signals.

In some embodiments, it is possible that further commands may be received while data is being read from memory. In these embodiments, an independent signal may be used to instruct the circuit ofFIG. 6to stop outputting data and prepare to receive commands. This independent signal may be received through a dedicated external contact, through external contact450, or through another instance of external contact430. For example, in some embodiments a dedicated external contact is used as an interrupt to allow halting of a data read in order to send further commands. In some embodiments, some instances of external contact430are used to communicate command and data signals, while at least one instance of external contact430is used to communicate addresses and the above independent signal.

FIG. 9illustrates an external contact layout900for the semiconductor package400, according to various embodiments of the invention. In this illustration, instances of the external contact430are labeled as being configured to communicate two data types. For example, external contact18on the bottom row910is labeled “XA<1> and XDQ<9> to indicate that it is an emobiment of external contact430configured to receive bit <1> of an address (XA), and to send and receive bit <9> of data (XDQ). In the embodiments illustrated, fourteen external contacts are shared. In some embodiments, the use of shared external contacts (e.g., external contact430) reduces the total number of external contacts and allows for a reduced device size. For example, the elimination of fourteen external contacts with a pitch of 80 microns saves approximately 1.1 mm.

FIG. 10illustrates an alternative external contact layout1000for the semiconductor package400, according to various embodiments of the invention. In this illustration, several instances of external contact430are disposed on the top row1020, e.g., external contact7. In addition, the bottom row1010is split into two sets, Set A and Set B. For example, external contacts4and5(XDQ<0> and XDQ<2>) are included in Set B and shifted slightly to the center of the external contact layout1000. Some of the instances of external contact430illustrated inFIG. 10are configured for alternatively communicating command and address signals. For example, external contact19of the top row1020is configured for communicating the XRAS_T command signal and the XTDQ<4> data signal. External contact430can be configured for communicating test signals in a test mode as well as normal signals in an address or data mode. Some embodiments of external contact layout900and1000include shared external contacts (e.g., external contact430) on both the bottom row910and1010, and the top row920and1020.

FIG. 11illustrates an external contact count chart (Table1110), a multiplex I/O pin definition chart (Table1120) and a multiplex test I/O pin definition chart (Table1130), according to various embodiments of the invention. Column1of Table1110lists the signals required for support of JEDEC features in a standard 256 Mb double data rate (DDR) memory interface. These standards may include, for example, the JESD79E or JESD79-2C standards. Column2of Table1110lists the number of exterior contacts required to support the signals in Column1. The bottom of Column2indicates that the total number of exterior contacts required is 62.

Column3of Table1110lists the signals required to support the same set of JEDEC features as supported by the signals in Column1, using a reduced number of external contacts. Note that 15 address signals of Column1, namely BA0, BA1, and A0-A12have been multiplexed with 15 data signals, e.g., DQ0-DQ14. The multiplexed signals, along with the remaining data signals that are not multiplexed are renamed IO0-IO31in Column3, indicating that data signals multiplexed with address signals are I/O signals.

Column4lists the number of exterior contacts required to support the signals in Column3. The bottom of Column4indicates that the total number of exterior contacts required is 47. Thus, multiplexing the signals BA0, BA1, and A0-A12with DQ0-DQ14reduces by 15 the number of exterior contacts required to support the JEDEC features supported by the signals in Column1.

Column5of Table1110lists the signals required to support a reduced set of JEDEC features using a reduced number of external contacts. Additional signals (e.g., RAS\, CAS\, WE\, DM0, DM1, DM2, DM3) have been multiplexed with DQ15-21. The signals listed in Column5may not support burst stop or any commands while DQ is active, and support data write masking only of a complete burst.

Column6of Table1110lists the number of external contacts required to support the signals in Column5. The bottom of Column6indicates that the total number of exterior contacts required is 40. Thus, multiplexing the additional signals as illustrated in Column5reduces the number of external contacts by 22.

Column7of Table1110illustrates how test mode data signals and test control signals may be multiplexed. Both the test control signals and test data signals are multiplexed through the same shared external contact. (Addresses are generated internally.) The combined signals are labeled TDQ0-TDQ7. Column8illustrates the number of external contacts required to support the signals in Column7.

Table1120illustrates details for multiplexing the data and address signals in Column1of Table1110. A mode signal, namely, active low chip select (CS\) may be provided to the external contact450for placing the interface410in a data mode (CS\=1) or an address mode (CS\=0). When the mode signal places the interface410in the data mode, the I/O signal100(multiplexed DQ0) may be communicated on the external contact430, and the I/O signal101(multiplexed DQ1) may be communicated on the external contact440. Alternatively, when the mode signal places the interface410in the address mode the address signal A0may be communicated on the external contact430, and address signal A1may be communicated on the external contact440. Likewise, the data signals IO2-IO14and the address signals A2-B1respectively may be communicated on additional instances of shared external contacts.

Table1130illustrates a mode signal, namely, active low test chip select (TCS\) that may be coupled to the external contact450for placing the interface510A in a test data mode (TCS\=1) or a control mode (TCS\=0). When the mode signal places the interface510A in a test data mode, the test data signal TDQ0may be communicated on the external contact430. Alternatively, when the mode signal places the interface510A in the control mode the control signal TA10may be communicated on the external contact430. Likewise, the test data signals TCQ1-TDQ7and the control signals TWE-TBA0respectively may be communicated on additional instances of shared external contacts.

FIG. 12illustrates methods of writing data to memory according to various embodiments of the invention. These methods make use of the external contact430to communicate various signals.

In an optional default step1210, the interface510A is placed in a default mode in which the signal expected at one or more shared external contacts, e.g., external contact430, is a row address. In the default mode, the interface510is configured to communicate address signal from the external contact430to the memory contact462. The default mode is optionally the default state of the memory420. In some embodiments, the mode is set by sending an appropriate mode signal to the external contact450.

In a receive row address step1220, a row address and optionally a bank address is received via the one or more shared external contacts, e.g., external contact430. Receive row address step1220may also include receiving an ACT command.

In a receive column address step1230, a column address is received via the one or more shared external contacts, e.g., external contact430. In alternative embodiments, the column address is received prior to the row address.

In a receive command step1240, a WRITE command is received. The WRITE command is optionally received through one or more external contacts. The WRITE command may be received contemporaneously with the column address of receive column address step1230. The WRITE command signal may be gated, buffered, and/or conditioned and communicated to the interface510A for placing the interface510A into a write state.

In a set data mode step1250, the interface510A receives a mode signal from the external contact450that places the interface510A into the data mode and configures the interface510A to communicate data from the external contact430to the memory420. In alternative embodiments, receipt of the WRITE command is used to automatically place the interface510A in the data mode.

In a write data step1260, data is written to the memory420through the external contact430and the interface510A to the memory420. The external contact430communicates the data from the external device to the buffer625in the interface510A. The latch630communicates the data from the buffer625to the buffer655and the memory contact461receives the data from the buffer655.

FIG. 13illustrates methods of reading data from memory according to various embodiments of the invention. In the methods ofFIG. 13, optional Default step1210, receive row address step1220and receive column address step1230are performed as described with respect toFIG. 12.

In a receive command step1340, a READ command is received. The READ command is optionally received through one or more external contacts. The READ command may be received contemporaneously with the column address of receive column address step1230. The READ command signal may be gated, buffered, and/or conditioned and communicated to the interface510A for placing the interface510A into a read state.

In a select data mode step1350, the interface510A receives a mode signal that places the interface510A into a data mode and configures the interface510A to communicate data from the external contact430to the memory420. In alternative embodiments, receipt of the READ command is used to automatically place the interface510A in the data mode.

In a read data step1360, data is read from the memory420through the memory contact461and the interface510A to the external contact430. The memory contact461communicates the data from the memory420to the buffer645in the interface510A. The latch610communicates the data from the buffer645to the buffer615and the external contact430communicates the data from the buffer615to the external device.

In an optional receive interrupt step1370, an interrupt signal is received while data is still being read from the memory420. The interrupt signal is configured to halt the output of data from the memory420and to place the memory420in a mode to receive a command, using an external contact. The interrupt signal received in the receive interrupt step1370is optionally received through a shared external contact, e.g., external contact430, which may also be used for communicating test signals, address signals, command signals, or the like. For example, if a command external contact is not multiplexed with data or address signals then the interrupt signal may share an external contact with the command external contact. In various embodiments, an interrupt signal is used in relation to READ and/or BURST READ commands.

In an optional receive command step1380, a command is received using the one or more shared external contacts that were used to read data in read data step1360, e.g., the external contact430.

Several embodiments are specifically illustrated and/or described herein. However, it will be appreciated that modifications and variations are covered by the above teachings and within the scope of the appended claims without departing from the spirit and intended scope thereof. For example, while “external contacts” are discussed herein for the purposes of example, semiconductor package400may itself be placed in a packaging as part of a system-in-package or package-in-package device. In this case, the external contacts may be coupled to another device, e.g., an ASIC, within the outermost packaging and the external contacts need not be external to the outermost packaging.

The memory devices discussed herein may include other types of RAM in addition to DDR RAM. In some embodiments, e.g., in the case of SDRAM, a latency period may be included between communication of commands and data I/O. Further, while the examples discussed herein are primarily in regard to command, address and data external contacts using in a normal mode, some embodiments include multiplexing of test pins (e.g., /TRAS, and /TCAS may be multiplexed with TDQ). In these embodiments, the TCS external contact or other appropriate external contact is used to control the state of the multiplexed external contacts.