Semiconductor package

A semiconductor package including a substrate; a first semiconductor chip on the substrate; a second semiconductor chip on the first semiconductor chip; and at least one connection terminal between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip includes a first semiconductor chip body; and at least one upper pad on a top surface of the first semiconductor chip body and in contact with the at least one connection terminal, the at least one upper pad includes a recess that is downwardly recessed from a top surface thereof, and a depth of the recess is less than a thickness of the at least one upper pad.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2020-0151768 filed on Nov. 13, 2020 in the Korean Intellectual Property Office, and entitled: “Semiconductor Package,” is incorporated by reference herein in its entirety.

BACKGROUND

Embodiments relate to a semiconductor package.

2. Description of the Related Art

A semiconductor package may be provided to implement an integrated circuit chip for use in electronic products. The semiconductor package may be manufactured by mounting a semiconductor chip on a substrate such as a printed circuit board (PCB) or a redistribution layer (RDL). A plurality of semiconductor chips may be mounted on a single semiconductor package. For example, a plurality of semiconductor chips may be vertically stacked on one substrate. The vertically stacked semiconductor chips may be electrically connected to each other through solder balls or the like.

SUMMARY

The embodiments may be realized by providing a semiconductor package including a substrate; a first semiconductor chip on the substrate; a second semiconductor chip on the first semiconductor chip; and at least one connection terminal between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip includes a first semiconductor chip body; and at least one upper pad on a top surface of the first semiconductor chip body and in contact with the at least one connection terminal, the at least one upper pad includes a recess that is downwardly recessed from a top surface thereof, and a depth of the recess is less than a thickness of the at least one upper pad.

The embodiments may be realized by providing a semiconductor package including a first chip; a second chip on the first chip; and at least one connection terminal between the first chip and the second chip, wherein the first chip includes a first chip body; and at least one upper pad on a top surface of the first chip body and connected to the at least one connection terminal, the at least one upper pad includes an upper pad body; a recess that is downwardly recessed from a top surface of the upper pad body; and an extension aperture that laterally extends from the recess and penetrates in a horizontal direction through the upper pad body, and a portion of the at least one connection terminal is in the recess.

The embodiments may be realized by providing a semiconductor package including a substrate; a first semiconductor chip on the substrate; a second semiconductor chip on the first semiconductor chip; and connection terminals between the first semiconductor chip and the second semiconductor chip, wherein the first semiconductor chip includes a first semiconductor chip body; and upper pads on a top surface of the first semiconductor chip body and connected to the connection terminals, the upper pads include a first upper pad on a first region at a center of the top surface of the first semiconductor chip body; a plurality of second upper pads on a second region outside the first region; and a plurality of third upper pads on a third region outside the second region, the first upper pad includes a first upper pad body; a first recess that is downwardly recessed from a top surface of the first upper pad body; and a first extension aperture that laterally extends from the first recess and penetrates in a horizontal direction through the first upper pad body, each of the second upper pads includes a second upper pad body; a second recess that is downwardly recessed from a top surface of the second upper pad body; and a second extension aperture that laterally extends from the second recess and penetrates in a horizontal direction through the second upper pad body, a width of the first recess is greater than a width of the second recess, the connection terminals include a first connection terminal connected to the first upper pad; a plurality of second connection terminals connected to corresponding second upper pads; and a plurality of third connection terminals connected to corresponding third upper pads, and a portion of the first connection terminal is in the first recess.

DETAILED DESCRIPTION

FIG.1illustrates a cross-sectional view of a semiconductor package according to some example embodiments.FIG.2illustrates an enlarged cross-sectional view of section X of the semiconductor package depicted inFIG.1.

In this description below, symbols D1, D2, and D3ofFIG.1are respectively a first direction, a second direction that intersects the first direction D1, and a third direction that intersects the first direction D1and the second direction D2.

Referring toFIGS.1and2, a semiconductor package P may be provided. The semiconductor package P may include a substrate7, a lower connection terminal9, a first semiconductor chip1, a connection terminal5, and a second semiconductor chip3.

The substrate7may connect the first and second semiconductor chips1and3to the outside. In an implementation, the first and second semiconductor chips1and3may be electrically connected through the substrate7to the outside. The substrate7may include one or more of a printed circuit board (PCB) and a redistribution layer (RDL) substrate. The substrate7may include a substrate body71and a substrate pad73. The substrate body71may have a wiring structure therein. The substrate pad73may be on a top surface71u(e.g., surface facing the first semiconductor chip1) of the substrate body71. The substrate pad73may be bonded to the lower connection terminals9. The substrate pad73may be electrically connected through the lower connection terminal9to the first semiconductor chip1. The substrate pad73may be provided in plural. The plurality of substrate pads73may be spaced apart from each other in the second direction D2and the third direction D3. For convenience, the following will discuss a single substrate pad73.

The lower connection terminal9may be bonded to the substrate pad73. Referring toFIG.2, the lower connection terminal9may include a connection pillar91and a connection ball93. The connection pillar91may extend (e.g., lengthwise) in the first direction D1. The connection pillar91may include a conductive material, e.g., copper (Cu). The connection ball93may be bonded to a bottom surface (e.g., substrate7-facing surface) of the connection pillar91. The connection pillar91may be electrically connected through the connection ball93to the substrate pad73. The connection ball93may include a solder ball or the like. In an implementation, the lower connection terminal9may be provided in plural. In an implementation, the number of a plurality of lower connection terminals9may be substantially identical or similar to that of a plurality of substrate pads73. For convenience, the following will discuss a single lower connection terminal9.

Referring back toFIG.1, the first semiconductor chip1may be on the substrate7. The first semiconductor chip1may be of various kinds. In an implementation, the first semiconductor chip1may include a logic chip. In an implementation, the first semiconductor chip1may be of a different type from that discussed above. The first semiconductor chip1may include a first semiconductor chip body11, a lower pad15, and an upper pad13. The first semiconductor chip body11may have a through silicon via (TSV)111therein. The TSV111may extend (e.g., lengthwise) in the first direction D1. The TSV111may electrically connect the lower pad15to the upper pad13. The lower pad15may be on a bottom surface11b(e.g., substrate7-facing surface) of the first semiconductor chip body11. The lower pad15may be connected to the lower connection terminal9. The upper pad13may be on a top surface11u(e.g., second semiconductor chip3-facing surface) of the first semiconductor chip body11. Referring back toFIG.2, the upper pad13may include a first upper pad131, a second upper pad132, a third upper pad133, a fourth upper pad134, and a fifth upper pad135. The first upper pad131may be in or on an inner side (e.g., relatively toward an interior) of the top surface11uof the first semiconductor chip body11. The first upper pad131may include a first recess1311h. The first recess1311hmay be a space that is downwardly or inwardly recessed from a top surface of the first upper pad131. The first recess1311hmay have a first width w1(e.g., in the second direction D2). The first upper pad131may have a first thickness e1(e.g., in the first direction D1). In an implementation, the first thickness e1may be about 2 μm to about 4 μm. The first recess1311hmay have a depth (e.g., a second thickness) e2in the first direction D1. The depth e2of the first recess1311hmay be less than the first thickness e1of the first upper pad131. The first recess1311hmay not completely penetrate the first upper pad131. In an implementation, the first recess1311hmay not expose the TSV111. In an implementation, a lower portion or bottom of the first recess1311hmay be defined by a first recess surface131b. In an implementation, the first recess surface131bmay be downwardly or inwardly recessed from the top surface of the first upper pad131and may correspond to a lower boundary or bottom of the first recess1311h.

The second upper pad132may be on the top surface11uof the first semiconductor chip body11and outside (e.g., closer to an edge of the first semiconductor chip1in the second direction D2relative to) the first upper pad131. The second upper pad132may include a second recess1321h. The second recess1321hmay be a space that is downwardly recessed from a top surface of the second upper pad132. The second recess1321hmay have a second width w2(e.g., in the second direction D2). The second upper pad132may have a thickness (e.g., in the first direction D1) substantially identical or similar to that of the first upper pad131. In an implementation, the second recess1321hmay have a depth substantially identical or similar to that of the first recess1311h.

The third upper pad133may be on the top surface11uof the first semiconductor chip body11and outside (e.g., at an outer side of) the second upper pad132. The third upper pad133may include a third recess1331h. The third recess1331hmay be a space that is downwardly recessed from a top surface of the third upper pad133. The third recess1331hmay have a third width w3(e.g., in the second direction D2). The third upper pad133may have a thickness substantially identical or similar to that of the first upper pad131. In an implementation, the third recess1331hmay have a depth substantially identical or similar to that of the first recess1311h.

The fourth upper pad134may be on the top surface11uof the first semiconductor chip body11and outside the third upper pad133. The fourth upper pad134may include a fourth recess1341h. The fourth recess1341hmay be a space that is downwardly recessed from a top surface of the fourth upper pad134. The fourth recess1341hmay have a fourth width w4(e.g., in the second direction D2). The fourth upper pad134may have a thickness substantially identical or similar to that of the first upper pad131. In addition, the fourth recess1341hmay have a depth substantially identical or similar to that of the first recess1311h.

The fifth upper pad135may be on the top surface11uof the first semiconductor chip body11and outside the fourth upper pad134. The fifth upper pad135may not include a recess. The fifth upper pad135may have a fifth width w5(e.g., in the second direction D2).

In an implementation, each of the first, second, third, and fourth widths w1, w2, w3, and w4may be about 3 μm to about 15 μm. In an implementation, within about 3 μm to about 15 μm, the first to fourth widths w1to w4may have widths that decrease in the foregoing sequence (e.g., w4<w3<w2<w1). In an implementation, the fifth width w5may be about 15 μm to about 20 μm. A sixth width w6may be a distance between neighboring two of a plurality of upper pads13(e.g., the distance in the second direction D2between facing sides of adjacent ones of the upper pads13). In an implementation, the sixth width w6may be about 20 μm to about 40 μm. The first, second, third, fourth, and fifth upper pads131,132,133,134, and135will be further discussed in detail below.

Referring again toFIG.1, the connection terminal5may be on the upper pad13. The connection terminal5and the upper pad13may be in contact (e.g., direct contact) with each other and electrically connected to each other. The upper pad13may include a solder ball or the like. Referring again toFIG.2, the connection terminal5may include a first connection terminal51, a second connection terminal52, a third connection terminal53, a fourth connection terminal54, and a fifth connection terminal55. The first connection terminal51may be bonded to the first upper pad131. The first connection terminal51may have a portion in the first recess1311h. The first connection terminal51may be in contact (e.g., direct contact) with the first recess surface131bdownwardly recessed from the top surface of the first upper pad131. The second connection terminal52may be bonded to the second upper pad132. The second connection terminal52may have a portion in the second recess1321h. The third connection terminal53may be bonded to the third upper pad133. The third connection terminal53may have a portion in the third recess1331h. The fourth connection terminal54may be bonded to the fourth upper pad134. The fourth connection terminal54may have a portion in the fourth recess1341h. The fifth connection terminal55may be bonded to the fifth upper pad135. Other connection terminals (see5ofFIG.1) will be further discussed in detail below.

Referring once again toFIG.1, the second semiconductor chip3may be on the first semiconductor chip1. In an implementation, the second semiconductor chip3may include a static random access memory (SRAM) or the like. The second semiconductor chip3may include a second semiconductor chip body31and a connection pad33. The connection pad33may be on a bottom surface31bof the second semiconductor chip body31. The connection pad33may be bonded to the connection terminal5. In an implementation, the number of a plurality of connection pads33may be the same as that of a plurality of connection terminals5. However, for convenience, the following will discuss a single connection pad33.

FIG.3illustrates a plan view of a first semiconductor chip of a semiconductor package according to some example embodiments.FIG.4illustrates an enlarged plan view of section Y of the semiconductor package depicted inFIG.3.

Referring toFIG.3, the top surface11uof the first semiconductor chip1may be divided into a plurality of regions including a first region A1, a second region A2, a third region A3, a fourth region A4, and another region (designated by no numeral).

The first region A1may indicate an innermost area including a center of the top surface11uof the first semiconductor chip1. In an implementation, the first region A1may have a tetragonal shape. In an implementation, the first region A1may have a tetragonal shape whose sides are parallel to four sides of the top surface11u. The upper pad13in the first region A1may be the first upper pad131. In an implementation, the first upper pad131may be on in the first region A1. In an implementation, as illustrated inFIG.3, only one first upper pad131may be on the first region A1. In an implementation, a plurality of first upper pads131may be on the first region A1.

On the top surface11uof the first semiconductor chip1, the second region A2may be an area that surrounds the first region A1. In an implementation, the second region A2may be outside (e.g., at outer sides of) the first region A1. The second region A2may have a tetragonal shape. The upper pad13on the second region A2may be the second upper pad132. In an implementation, the second upper pad132may be on the second region A2.

On the top surface11uof the first semiconductor chip1, the third region A3may be an area that surrounds the second region A2. In an implementation, the third region A3may be outside the second region A2. The third region A3may have a tetragonal shape. The upper pad13on the third region A3may be the third upper pad133. In an implementation, the third upper pad133may be on the third region A3.

On the top surface11uof the first semiconductor chip1, the fourth region A4may be an area that surrounds the third region A3. In an implementation, the fourth region A4may be outside the third region A3. The fourth region A4may have a tetragonal shape. The upper pad13on the fourth region A4may be the fourth upper pad134. In an implementation, the fourth upper pad134may be on the fourth region A4.

On the top surface11uof the first semiconductor chip1, another region may be an area that surrounds the fourth area A4. In an implementation, the other region may be outside the fourth region A4. The upper pad13on the other region may be the fifth upper pad135. In an implementation, the fifth upper pad135may be on the other region.

Referring toFIG.4, the first upper pad131may include a first upper pad body1311. The first upper pad131may further include a first extension aperture1313h. The first extension aperture1313hmay outwardly extend from the first recess1311hand may horizontally penetrate the first upper pad body1311(e.g., may be a hole or opening in the sidewall of the first upper pad body1311).

The second upper pad132may include a second upper pad body1321. The second upper pad132may further include a second extension aperture1323h. The second extension aperture1323hmay outwardly extend from the second recess1321hand may horizontally penetrate the second upper pad body1321.

The third upper pad133may include a third upper pad body1331. The third upper pad133may further include a third extension aperture1333h. The third extension aperture1333hmay outwardly extend from the third recess1331hand may horizontally penetrate the third upper pad body1331.

The fourth upper pad134may include a fourth upper pad body1341. The fourth upper pad134may further include a fourth extension aperture1343h. The fourth extension aperture1343hmay outwardly extend from the fourth recess1341hand may horizontally penetrate the fourth upper pad body1341.

In an implementation, the first, second, third, and fourth extension apertures1313h,1323h,1333h, and1343hmay extend or be open in the same direction as each other (e.g., in the third direction D3). In an implementation, the first, second, third, and fourth extension apertures1313h,1323h,1333h, and1343hmay extend or be open in different directions from each other.

In an implementation, one of the first, second, third, and fourth upper pads131,132,133, and134may include a corresponding one of the first, second, third, and fourth extension apertures1313h,1323h,1333h, and1343h. In an implementation, the first upper pad131may include a plurality of extension apertures that extend in various directions. In an implementation, the first upper pad131may include four extension apertures that extend in four directions from the first recess1311h. In an implementation, other upper pads132,133, and134, may each include a plurality of extension apertures.

FIG.5illustrates a flow chart of a semiconductor package fabrication method according to some example embodiments.

Referring toFIG.5, a semiconductor package fabrication method S may be provided. The semiconductor package fabrication method S may fabricate a semiconductor package (see P ofFIG.1) discussed with reference toFIGS.1to4. The semiconductor package fabrication method S may include a step S1of preparing a first semiconductor chip, a step S2of preparing a second semiconductor chip, a step S3of stacking the second semiconductor chip on the first semiconductor chip, a step S4of bonding the first and second semiconductor chips to each other, and a step S5of stacking the first and second semiconductor chip on a substrate. It is described above that the first and second semiconductor chips are bonded to each other and then are stacked on the substrate, but the fabrication sequence may be changed. In an implementation, the first semiconductor chip may be stacked on the substrate, and then the second semiconductor chip may be stacked on and bonded to the first semiconductor chip.

The step S1may include a step S11of forming an upper pad on a first semiconductor chip body and a step S12of forming a recess on or in the upper pad.

The step S4may include a step S41of filling the recess with a connection terminal.

With reference toFIGS.6to17, each step of the semiconductor package fabrication method S will be described in detail.

FIGS.6to17illustrate cross-sectional views of stages in the semiconductor package fabrication method according to the flow chart ofFIG.5.

Referring toFIGS.5and6, the step S1may include preparing a first semiconductor chip1including a TSV111. The TSV111may penetrate a first semiconductor chip body11in the first direction D1.

Referring toFIGS.5and7, the step S11may include forming a seed metal SM on the first semiconductor chip body11. The seed metal SM may be conformally formed on a top surface11uof the first semiconductor chip body11. In an implementation, the seed metal SM may be formed by a deposition process.

Referring toFIG.8, a mask layer PR may be formed on the seed metal SM. The mask layer PR may include a photosensitive polymer or the like. In an implementation, the mask layer PR may include photosensitive polyimide, polybenzoxazole, phenolic polymer, or benzocyclobutene polymer. In an implementation, the mask layer PR may include other suitable materials. The formation of the mask layer PR may be performed by a coating process, e.g., spin coating or slit coating.

Referring toFIG.9, the mask layer PR may be patterned. In an implementation, a mask pattern PRh may be formed on the mask layer PR. The mask pattern Pith may expose a portion of the seed metal SM. The patterning of the mask layer PR may be executed by exposure and development processes. The development process may be a positive tone development process or a negative tone development process. The patterning of the mask layer PR may include aligning a photomask on the mask layer PR, performing an exposure process on the mask layer PR, and performing a development process on the exposed mask layer PR.

Referring toFIG.10, an upper pad13′ may be formed on the seed metal SM exposed by the mask pattern PRh. The formation of the upper pad13′ may be achieved by an electroplating process in which the seed metal SM is used as an electrode.

Referring toFIG.11, the mask layer (see PR ofFIG.10) may be removed. A strip process may be performed to remove the mask layer PR. After the removal of the mask layer PR, a removal action may be performed on the seed metal (see SM ofFIG.1) that is not covered with or used to form the upper pad13′. An etching process may be performed to remove the seed metal SM. In an implementation, a wet etching process may be performed to remove the seed metal SM. The seed metal SM under the upper pad13′ may remain without being etched. For convenience in the following description, the upper pad13′ and its underlying seed metal SM may be collectively called an upper pad13.

Referring toFIGS.5,12, and13, the step S12may include forming first, second, third, and fourth recesses1311h,1321h,1331h, and1341hthat are downwardly recessed from top surfaces of first, second, third, and fourth upper pads131,132,133, and134. Various suitable methods may be used to form the first, second, third, and fourth recesses1311h,1321h,1331h, and1341h. In an implementation, an etching process may be performed to form the first, second, third, and fourth recesses1311h,1321h,1331h, and1341h. In an implementation, suitable methods may be employed to form the first, second, third, and fourth recesses1311h,1321h,1331h, and1341h. One or more extension apertures may be formed simultaneously with the formation of the first, second, third, and fourth recesses1311h,1321h,1331h, and1341h. In an implementation, an etching process may be performed to form the extension apertures simultaneously with the first, second, third, and fourth recesses1311h,1321h,1331h, and1341h. The first, second, third, and fourth upper pads131,132,133, and134may respectively include first, second, third, and fourth upper pad bodies1311,1321,1331, and1341. Referring toFIG.13showing a cross-section viewed from a different side, the upper pad may have an L-shaped cross-section due to the extension aperture that extends (e.g., outwardly) from the recess.

Referring toFIGS.5and14, the step S2may include bonding a connection terminal5′ to a connection pad33of a second semiconductor chip3. Before the bonding to the connection pad33, the connection terminal5′ may have a spherical solder ball shape. The second semiconductor chip3may be placed on the first semiconductor chip1.

Referring toFIGS.5and15, the step S3may include stacking the second semiconductor chip3on the first semiconductor chip1to allow the connection terminal5′ to contact the upper pad13.

Referring toFIG.16, the connection terminal5′ on the third upper pad133may be in contact with a top surface of the third upper pad body1331. The third recess1331hmay cause the connection terminal5′ on the third upper pad133to upwardly separate (e.g., be spaced apart) from a third recess surface133b(e.g., the bottom of the recess). The connection terminal5′ on the fourth upper pad134may be in contact with a top surface of the fourth upper pad body1341. The fourth recess1341hmay cause the connection terminal5′ on the fourth upper pad134to be spaced apart from a fourth recess surface134b. The fifth upper pad135may not include a recess, and the connection terminal5′ on the fifth upper pad135may be in contact with a top surface of the fifth upper pad135without a spacing space between the connection terminal5′ and the fifth upper pad135.

Referring toFIGS.5and17, the step S4may include pressing the second semiconductor chip3against the first semiconductor chip1. In an implementation, in the step S4, a thermo-compression (TC) process may be performed such that heat is applied while downwardly pressing a top surface of the second semiconductor chip3.

The step S41may allow the connection terminal to fill the recess. In an implementation, as the second semiconductor chip3is compressed, a spacing distance may disappear between the connection terminal5′ and the third recess surface133bof the third upper pad133discussed with reference toFIG.16. In an implementation, a portion of the connection terminal5′ may be introduced into the third recess1331h, and thus the connection terminal5′ and the third recess surface133bmay come into contact (e.g., direct contact) with each other. The first upper pad (see131ofFIG.2), the second upper pad (see132ofFIG.2), and the fourth upper pad134may experience an action similar to that mentioned above. Therefore, recesses may be filled with connection terminals.

Referring back toFIG.5, the step S5may include stacking the first and second semiconductor chips on the substrate. Accordingly, a semiconductor package P may be fabricated as discussed with reference toFIG.1.

In a semiconductor package and its fabrication method in accordance with some example embodiments, a recess may be on or in an upper pad, and thus solder balls as connection terminals may be prevented from excessively outwardly spreading during a pressing step of a thermo-compression process. In an implementation, the connection terminal may be introduced into the recess, and the connection terminal may be inhibited from extremely growing left and right (e.g., from flowing outwardly). Thus, it is possible to help prevent contact between neighboring connection terminals. In an implementation, the connection terminals may be free of short-circuit defects. In an implementation, the semiconductor package may increase in yield.

In a semiconductor package and its fabrication method in accordance with some example embodiments, a width of a recess on an upper pad on or at a central region (e.g., toward an interior of) a top surface of a first semiconductor chip may be greater than a width of a recess on an upper pad on or at an outer region, e.g., a region outside the central region. In an implementation, semiconductor chips may have central regions that are bent into a downwardly convex curved shape. In an implementation, a semiconductor chip may be configured such that a connection terminal at a central region thereof is closer than others to the first semiconductor chip. In this case, the connection terminal at the central region may be strongly compressed in a thermo-compression process. When the recess at the central region has a relatively larger width, the connection on the central region may be prevented from excessively protruding outwardly, even when being strongly compressed. In an implementation, the recess at the central region may have a relatively large width, and the connection terminal may be introduced into the recess and may thus be prevented from excessively spreading outwardly. Accordingly, it may be possible to avoid short-circuit between neighboring connection terminals on the central region.

In a semiconductor package and its fabrication method in accordance with some example embodiments, a wide recess may be on the upper pad on the central region, the connection terminal may be prevented from spreading, and the second semiconductor chip may be compressed with a sufficiently large pressure in the thermo-compression process. As the second semiconductor is compressed with a large pressure, it is possible to allow upper pads to uniformly contact connection terminals on the outer region, and before being compressed, which are relatively far from the first semiconductor chip. Thus, non-wet issues may be prevented between pads and solder balls.

In a semiconductor package and its fabrication method in accordance with some example embodiments, short-circuits and non-wet issues may be avoided even when small-pitched upper pads and solder balls are used. In an implementation, fine-pitched solder balls may be used.

In a semiconductor package and its fabrication method in accordance with some example embodiments, the recess may have a depth less than a thickness of the upper pad. In an implementation, after the thermo-compression bonding, the connection terminal may be in contact with a recess surface of the upper pad. In an implementation, the connection terminal may have a surface contact with the recess surface of the upper pad (e.g., the bottom of the recess), and contact defects may be prevented. In an implementation, the connection may not directly contact a through silicon via (TSV) or the like, and therefore, a uniform bonding may be achieved in a bonding step.

In a semiconductor package and its fabrication method in accordance with some example embodiments, the upper pad may have an extension aperture that horizontally extends from the recess. In an implementation, even if the connection terminal and the upper pad were not uniformly bonded due to insufficient compression when the connection terminal shaped like a ball is coupled to the upper pad, it is possible to prevent the occurrence of void between the recess surface and the connection terminal. In such a case, the extension aperture may be spatially connected or open to the outside (e.g., of the recess), and it is possible to avoid the formation of an empty space completely surrounded by the connection terminal and the upper pad. In an implementation, the connection terminal and the upper pad may be prevented from problems such as contact failure resulting from expansion of the void.

FIG.18illustrates a plan view of a first semiconductor chip of a semiconductor package according to some example embodiments.

For convenience, the following may omit repeated descriptions substantially the same as or similar to that discussed with reference toFIGS.1to16.

Referring toFIG.18, a semiconductor package1′ may include a first semiconductor chip that has, on its top surface11u, a first region A1′, a second region A2′, a third region A3′, and a fourth region A4′ whose shapes are different from those discussed with reference toFIG.3. In an implementation, differently from that discussed with reference toFIG.3, each of the first, second, third, and fourth regions A1′, A2′, A3′, and A4′ may have four sides that are not parallel to four sides of the top surface11u. In an implementation, each side of the first, second, third, and fourth regions A1′, A2′, A3′, and A4′ may make an angle of about 45 degrees relative to four sides of the top surface11u.

In an implementation, regions may have shapes as depicted inFIG.3or18. In an implementation, the first to fourth regions may have shapes that are inclined outwardly or are variously changed.

By way of summation and review, a reflow or thermo-compression (TC) process may be employed to use solder balls or the like to connect and couple semiconductor chips to each other. For the thermo-compression process, heat may be applied to the stacked semiconductor chips that are compressed downwardly.

In a semiconductor package of an embodiment, short-circuits may be prevented to help increase reliability.

In a semiconductor package of an embodiment, non-wet issues may be avoided.

In a semiconductor package of an embodiment, fine-pitched solder balls may be used.

In a semiconductor package of an embodiment, the formation of voids may be inhibited between solder balls and upper pads.

One or more embodiments may provide a semiconductor package whose reliability is increased due to the prevention of short-circuit that could occur in a thermo-compression process.

One or more embodiments may provide a semiconductor package capable of preventing short-circuits to increase reliability.

One or more embodiments may provide a semiconductor package capable of preventing non-wet phenomena.

One or more embodiments may provide a semiconductor package capable of using solder balls having fine pitches.

One or more embodiments may provide a semiconductor package capable of preventing the generation of voids between solder balls and upper pads.