High-density non-volatile read-only memory arrays and related methods

In an embodiment, a read-only memory array includes a plurality of word lines, a plurality of bit-lines including first and second bit-lines, and a plurality of memory cells configured to represent data values. Each memory cell can include a transistor having a control terminal coupled to one of the plurality of word lines, a drain terminal, and a source terminal. Connections associated with the drain and source terminals of a particular memory cell can determine a data value represented by the memory cell. The memory cells of the plurality of memory cells that are coupled to less than two bit-lines are configured to represent one values.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is related to co-pending, commonly assigned, U.S. patent application Ser. No. 11/749,428, filed on May 16, 2007, and entitled “HIGH DENSITY NON-VOLATILE MEMORY ARRAY,” and published on Nov. 20, 2008, which application is incorporated herein by reference in its entirety.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to high-density non-volatile read-only memory (ROM) arrays and, more particularly to, high-density non-volatile ROM arrays with reduced numbers of connections on the bit-lines.

BACKGROUND

High-density non-volatile memory arrays can be used to store digital data for computing systems, such as computers, mobile telephones, personal digital assistants, music players, other electronic devices, or any combination thereof. In an example, the memory arrays may include multiple transistor cells, where each transistor cell can include a floating gate adapted to retain an electrical charge representative of a data value when power is removed from the transistor cell. Bit-lines, word lines, and reference lines (i.e., wire traces, active/diffusion reference lines, other electrical interconnections, or any combination thereof, hereinafter generally referred to as “lines”) may be used in various combinations to store data to and retrieve data from the transistor cells.

Unfortunately, as the size of the memory arrays has decreased and the transistor cell density has increased, routing of such lines has become increasingly complex. Further, such lines can contribute to undesired power consumption within a particular array and may adversely impact read margins. In particular, the wire traces may introduce undesired impedances, which can reduce sensed-voltage-level read margins, for example.

Additionally, the transistors within the array may contribute to overall power consumption. For example, charging and discharging of gate and interconnect capacitances can dissipate a significant amount of power. Further, parasitic leakage through the reverse bias P/N junctions and/or through sub-threshold source-to-drain currents of metal-oxide semiconductor (MOS) transistors in an “off” state can also dissipate power.

DETAILED DESCRIPTION

The following detailed description refers to the accompanying drawings that depict various details of examples selected to show how particular embodiments may be implemented. The discussion herein addresses various examples of the subject matter at least partially in reference to these drawings and describes the depicted embodiments in sufficient detail to enable those skilled in the art to practice the embodiments disclosed herein. Many other embodiments may be utilized for practicing the subject matter than the illustrative examples discussed herein, and many structural and operational changes, in addition to the alternatives specifically discussed herein, may be made without departing from the scope of the subject matter.

In this description, references to “one embodiment,” “an embodiment,” “one example,” “an example,” “a particular example,” or any combination thereof mean that the feature being referred to is, or may be, included in at least one embodiment or example. Separate references to “an embodiment” or “one embodiment” or to “one example” or “an example” in this description are not intended to necessarily refer to the same embodiment or example; however, neither are such embodiments mutually exclusive, unless so stated or as will be readily apparent to those of ordinary skill in the art having the benefit of this disclosure. Thus, the present disclosure can include a variety of combinations and/or integrations of the embodiments and examples described herein, as well as further embodiments and examples as defined within the scope of all claims based on this disclosure, as well as all legal equivalents of such claims.

The present disclosure generally relates to memory devices for use within electronic devices, including computers, mobile telephones, music players, programmable electronic devices, or any combination thereof. In a particular example, the memory devices can be read-only memory (ROM) arrays that are formed from a plurality of transistor devices having terminals that are selectively coupled between bit-lines to represent data values and having control terminals coupled to word lines to allow data to be read from the ROM arrays. Such ROM arrays may be embodied in solid-state data storage devices, such as flash ROM devices.

In an aspect of the present disclosure, a memory array includes a plurality of memory cells. Each memory cell can include a transistor selectively configured to represent a data value based on its configuration of source and drain terminals relative to other transistors within the memory array and relative to adjacent bit-lines. In an embodiment, a zero value may be represented by a transistor having its source and drain terminals coupled to different bit-lines, and a one value may be represented by a transistor having its source and drain terminals coupled to a common bit-line or to source and drain terminals of adjacent memory cells.

In an embodiment, a memory array is disclosed that can include a plurality of word lines, a plurality of bit-lines, and a plurality of memory cells configured to represent data values. Each memory cell can include a transistor having a control terminal coupled to one of the plurality of word lines and having drain and source terminals. Connections associated with the drain and source terminals of a particular memory cell can determine a data value represented by the memory cell. The memory cells that are coupled to less than two bit-lines are configured to represent one values (i.e., digital “one” values).

In a particular example, at least some of the memory cells can be configured to represent one values by connecting their source and drain terminals together (as depicted inFIGS. 1B and 1Cbelow) and, in some instances, by connecting them to source and drain terminals of adjacent memory cells without connecting them directly to a bit-line (as depicted inFIGS. 1D and 3below).

FIG. 1Adepicts a schematic diagram of a particular illustrative embodiment of a memory cell100configured to represent a zero value, for example, within a read-only memory (ROM) array. The ROM array may be used within any type of memory device, including a flash memory, for example. The memory cell100can include a transistor108, such as a floating-gate metal oxide semiconductor field effect transistor (MOSFET), an insulated gate MOSFET, another metal oxide semiconductor (MOS) transistor device, or any combination thereof. The transistor108can be an n-channel (NMOS) transistor or a p-channel (PMOS) transistor. In the following discussion, the operation of the transistor108and of transistors within the memory array is described with respect to NMOS transistors; however, it should be understood that an NMOS transistor may be replaced with a PMOS transistor in some configurations and with appropriate modification to word line control signals to provide similar function and benefits.

The transistor108can include a drain terminal110coupled to a first bit-line (Bj−2)102, a gate terminal114coupled to a word line (Ii+1)106, and a source terminal112coupled to a second bit-line (Bj−1)104. In this example, the subscripts (i and j) can refer to rows and columns within the memory array, such as the memory arrays depicted inFIGS. 2 and 3. In an example, the transistor108is configured to represent a zero value within the memory array.

In the embodiment shown, no reference line is used. Instead, the memory cells, such as the memory cell100, can use the bit-lines102or104as reference lines. In an example, during a standby mode when no data is being read from the memory cell100, the bit-lines102and104may be charged to a voltage level (Vdd), set to a ground voltage level, or left floating, such that all of the bit-lines102and104have an equivalent voltage potential. In this instance, the drain-source voltage (Vds) is approximately zero for each cell of the memory array, including the memory cell100. Thus, there is no sub-threshold (sub-Vth) leakage current in the memory array during standby mode.

In an example, assuming each of the bit-lines102and104is initially charged to a first voltage level, a target bit-line, such as the bit-line102, can be read by setting the adjacent bit-line104to a zero voltage level or potential. As used herein, the term “adjacent bit-line” refers to a bit-line that is shared by at least one memory cell of a column of memory cells that are associated with the target bit-line and does not necessarily refer to a proximity of the bit-line to any other bit-line. Also, as used herein, the term “adjacent memory cell” refers to a memory cell that is positioned proximate to or next within a particular column of a memory array, or to memory cells that can be logically understood to be next to one another within the column.

In this instance, setting the adjacent bit-line104to zero causes the drain-source voltage (Vds) across the transistor108to increase. When a voltage greater than or equal to a threshold voltage (Vth) is applied to the word line (Li+1)106, the transistor108is activated, causing a discharge onto the adjacent bit-line104via the transistor108, reducing a voltage on the target bit-line102, which change in voltage level may be sensed using sense circuitry coupled to the plurality of bit-lines102and104. In another example, current may flow from the target bit-line102through the transistor108to the adjacent bit-line104, which current may be sensed by sense circuitry to determine a value represented by the transistor108. In either example, the discharge can indicate a zero value stored at the memory cell100.

FIG. 1Bdepicts a schematic diagram of a particular illustrative embodiment of a memory cell120configured to represent a one value. The memory cell120can include a transistor124that is positioned between the bit-lines102and104. In an example, the transistor124can include drain and source terminals126and128, which can be coupled to the bit-line102and can include a gate terminal130that is coupled to a word line122. In an example, the configuration of the transistor124can represent a one value.

In a particular example, assuming each of the bit-lines102and104is initially charged to a first voltage level, a target bit-line, such as the bit-line102, can be read by setting the adjacent bit-line104to a zero voltage level. In this instance, setting the bit-line104to zero does not affect the drain-source voltage (Vds) of the transistor124. Instead, when a voltage greater than or equal to the threshold voltage (Vth) is applied to the word line (Li)122, the transistor124is activated, but no discharge related to the transistor124can be seen at the bit-line (Bj−1)104. For example, setting the bit-line104to a ground or zero voltage potential and activating the transistor124cannot result in a full discharge related to the transistor124, since the transistor124is not coupled to the bit-line104. Further, since the source and drain terminals126and128are tied to the same voltage potential, even if the transistor124is turned on, only a small amount of current can flow through the transistor124. Accordingly, a value associated with the memory cell120can represent a one value, which can be sensed using sense circuitry coupled to the bit-lines102and104.

FIG. 1Cdepicts a schematic diagram of a particular illustrative embodiment of a memory cell140configured to represent a one value. In this example, the memory cell140can include a transistor142that is positioned between bit-lines (Bj−1) and (Bj),104and150, respectively. The transistor142can include drain and source terminals144and146, which are coupled to each other. Further, the transistor142can include a gate terminal148, which is coupled to the word line (Li)122.

In this particular example, assuming each of the bit-lines104and150is initially charged to a first voltage potential, a target bit-line, such as the bit-line104, can be read by setting the adjacent bit-line150to a zero voltage potential. In this instance, setting the bit-line150to zero has no effect on the drain-source voltage (Vds) across the transistor142. Further, in this instance, when a voltage greater than or equal to the threshold voltage (Vth) is applied to the word line (Li)122, the transistor142is activated, but no discharge related to the transistor142can be seen at the bit-line (Bj)150. Additionally, since the drain and source terminals144and146are coupled to each other (i.e., to the same voltage potential) and not to either bit-line104or150, even if the transistor142is turned on, no current flows through the transistor142. Accordingly, a value associated with the memory cell140can represent a one value, which can be sensed using sense circuitry coupled to the bit-lines104and150.

FIG. 1Ddepicts a schematic diagram of a particular illustrative embodiment of a memory cell160configured to represent a one value. In this example, the memory cell160can include a transistor162that is positioned between bit-lines (Bj) and (Bj−1),150and104, respectively. The transistor162can include drain terminal coupled to bit-line150and source terminal coupled to the drain of adjacent memory cell163. Further, the transistor162can include a gate terminal168, which is coupled to the word line (Li−1)220.

In this particular example, assuming each of the bit-lines104and150is initially charged to a first voltage potential, a target bit-line, such as the bit-line104, can be read by setting the adjacent bit-line150to a zero voltage potential. In this instance, setting the bit-line150to zero has no effect on the drain-source voltage (Vds) across the transistor162. Further, in this instance, when a voltage greater than or equal to the threshold voltage (Vth) is applied to the word line (Li−1)220, the transistor162is activated, but no discharge related to the transistor162can be seen at the bit-line (Bj)104since it is not connected to the memory cell160. Accordingly, a value associated with the memory cell160can represent a one value, which can be sensed using sense circuitry coupled to the bit-lines104and150.

It should be understood that the memory cells100,120,140and160depicted inFIGS. 1A-1Dare representative examples, and that other configurations to represent zeros and ones within a ROM array may be apparent to one skilled in the art in view of this disclosure. In a particular example, the drain and source terminals110and112of the transistor108may be coupled to the bit-lines104and102, respectively, while the transistor124may have its source and drain terminals126and128coupled to the bit-line104. Further, in an alternative embodiment, the one values may be represented by the configuration of the memory cell100depicted inFIG. 1A, and the zero values may be represented by the configuration of the memory cells120,140and160depicted inFIGS. 1B,1C and1D. In this instance, rules for configuring the particular connections within a memory array (as discussed below in detail with respect toFIGS. 3-5) may be adjusted appropriately. Additionally, it should be understood that memory cells, such as the cells100,120,140, and160depicted inFIGS. 1A-1D, may be incorporated within a ROM array, and that multiple memory cells may be accessed at the same time by activating one or multiple word lines depending on the architecture and by appropriately biasing selected bit-lines.

One particular advantage provided by a ROM array having data values represented by the configuration of the transistors that make up the array is that speed of reading the data out of the ROM array can be enhanced, thanks to the reduced number of connections of bit-lines. Also, dynamic power consumption is reduced, thanks to switching capacitance reduction. Additionally, during standby modes, which can represent a significant portion of the usable life of the memory array, since the bit-lines can have the same voltage potential, current leakage through the transistors is reduced.

In the following discussion, reference numbers fromFIGS. 1A-1Dare reused to place the memory cells100,120,140, and160into context within examples of memory arrays. Further, in the following discussion, bit-line and word line numbers are reused for ease of discussion.

FIG. 2depicts a schematic diagram of a portion200of a high-density non-volatile ROM array including memory cells configured according to the embodiments ofFIGS. 1A and 1Bto represent zeros and ones. The portion200can include multiple bit-lines202and word lines216configured to connect various memory cells204within the memory array. The memory cells204can be organized into rows and columns. In the example shown, the word lines216can represent the rows, which are horizontally arranged. The word lines216include first, second, third, fourth, and fifth word lines (Li−2, Li−1, Li, Li+1, and Li+2)218,220,122,106, and226, respectively. Further, the bit-lines202can be vertically arranged, and can include first, second, third, fourth, fifth, and sixth bit-lines (Bh−2, Bj−1, Bj, Bj+1, Bj+2, and Bj+3)102,104,150,208,210, and212.

In the embodiment shown, the portion200can include columns of memory cells204, including first, second, third, fourth, and fifth columns230,232,234,236and238. The bit-lines202are vertically arranged, defining the columns230,232,234,236, and238, and each bit-line202is coupled to one or more source and/or drain terminals on either side of the respective bit-line. Further, each word line218,220,122,106, and226is coupled to gate terminals of transistors within a particular row. As used herein, the terms “row” and “column” are used to designate an arrangement of transistors in an approximate grid, with the connection lines (word lines216and bit-lines202) approximately parallel to the rows and columns, respectively. Further, as used herein, the terms “horizontal” or “horizontally” and “vertical” or “vertically” are relative terms that refer to an arrangement of memory cells relative to one another within the respective figure, and not necessarily in terms of three-dimensional space. Further, the terms “horizontal” and “vertical” or “horizontally” and “vertically” are not used to represent absolute directions. It should be understood that the arrangement of transistors or memory cells204may be provided in different appropriate orientations.

In the embodiment ofFIG. 2, there is one extra bit-line (Bj+3)212, which can be used to bias memory cells within the column238to read from the memory cells via the target bit-line (Bj+2)210. In other embodiments, the extra bit-line212may be in a different location, such as on the left side ofFIG. 2, and it can be used to read from different memory cells.

In the embodiment shown, programming of each memory cell204is dependent on a last adjacent programmed cell in the same column. For example, programming of the memory cell100associated with the word line106depends on the data value represented by the memory cell204associated with the word line226in column230. Similarly, the programming of the memory cell120can depend on the data value represented by the memory cell100, in this example.

In this embodiment, each memory cell204is coupled by its source and drain terminals to one or two different bit-lines202and by its gate terminal to one word line216. The memory cell228can include a transistor240having a drain terminal242coupled to the bit-line (Bj−1)104, a source terminal244coupled to the bit-line (Bj−2)102, and a gate terminal246coupled to the word line (Li−2)218. In this example, the memory cells228and100represent zero values.

Additionally, the memory cell248can include a transistor250having drain and source terminals252and254coupled to the bit-line (Bj)150(i.e., a common bit-line) and having a gate terminal256coupled to the word line (Li+2)226. In this example, the memory cells248and120can represent “one” values.

In the portion200of the ROM array depicted inFIG. 2, the data values represented by the memory cells204are provided below in Table 1.

TABLE 1Data values in the ROM arrays depicted in FIGS. 2 and 3.Bj−2Bj−1BjBj+1Bj+2Li−200010Li−111111Li11011Li+101111Li+200101

With reference again to the memory array ofFIG. 2, the first bit-line (Bj−2)102has four connections, the second bit-line (Bj−1)104has six connections, the third bit-line (Bj) has six connections, the fourth bit-line (Bj+1) has three connections, and the fifth bit-line (Bj+2) has ten connections (five associated with memory cells204of the fourth column236and five associated with memory cells204of the fifth column238). Each connection can add internal impedance and can provide a path for current leakage. Further, each connection contributes to the overall inter-connect, drain capacitances of bit-line and layout and routing complexities of the circuit.

Utilizing the memory cell configurations100,120,140and160depicted inFIGS. 1A-1D, the embodiment ofFIG. 3discussed immediately below can represent the same data values as the portion200of the memory array depicted inFIG. 2and represented in Table 1, but with fewer connections to the bit-lines. Accordingly, overall power consumption due to leakage current and internal impedance is reduced. Further, the layout and routing can be simplified.

FIG. 3depicts a schematic diagram of a portion300of a high-density non-volatile ROM array including memory cells304configured to provide the same data configuration as the ROM array ofFIG. 2, but with fewer connections on the plurality of bit-lines202including the bit-lines102,104,150,208,210, and212. In this embodiment, the memory cells304can be configured as described with respect to the following examples.

In a first example, a memory cell304can be programmed to represent a zero value by coupling the source and drain terminals of the memory cell to different bit-lines, as depicted by the memory cell100inFIG. 1A. Further, one values can be programmed by connecting the source and drain terminals to a common bit-line, such as with the memory cells340in column230. In this example, since the “one” values are programmed between two zero values but are fewer than three consecutive one values, the drain and source terminals are coupled to the same bit-line102.

In an example represented by column232, when more than two consecutive one values are to be programmed between two zero values, from the bottom to the top of the column232, all of the memory cells304from the second memory cell to the memory cell before the last memory cell to be programmed to a one value are coupled with their source and drain terminals in common, as generally indicated at342. In this example, the memory cell140represents both the second memory cell and the memory cell before the last memory cell to be programmed to a one value. Accordingly, the memory cell140has its source and drain terminals in common, which terminals are coupled to a source terminal of a last memory cell and to a drain terminal of a first memory cell to be programmed to a one value.

In an example represented by columns234and238, again referring to programming the values from the bottom to the top of the columns, if one values are to be programmed before a zero value (and not between two zero values), all of the one-value memory cells from the first memory cell to the memory cell before the last memory cell are coupled with their source and drain terminals in common, as generally indicated at344and348. In the example of344, the first memory cell is also the memory cell before the last memory cell to be programmed as a one value. In contrast, the example of348shows three memory cells (three transistors) representing the first memory cell and the memory cell before the last memory cell to be programmed to a one value.

In the example represented by columns234and236, by construction, the last cell programmed to represent a one value in the column234and the first cell programmed to represent a one value in the column236are configured like the example shown inFIG. 1D.

In yet another example represented by the column236, if one values are programmed after a zero value (but not between two zero values), all of the memory cells from the second memory cell to the last memory cell have their source and drain terminals in common, as generally indicated at346. In this particular example, the memory cells indicated at346are not coupled to either bit-line208or bit-line210. Further, in an example (not shown), if one values are to be programmed in all of the memory cells of a given column and not before, after or between zero values, the drain and source terminals of each of the cells to be programmed may be connected in common and not connected to any bit-line.

In the examples depicted inFIG. 3, the data of Table 1 above can be represented by the memory array using fewer connections to the bit-lines102,104,150,208,210, and212than the configuration represented inFIG. 2. In particular, the first bit-line (Bj−2)102has four connections, the second bit-line (Bj−1)104has three connections, the third bit-line (Bj) has four connections, the fourth bit-line (Bj+1) has three connections, and the fifth bit-line (Bj+2) has two connections. Table 2 below summarizes the connections ofFIG. 2versusFIG. 3for each bit-line.

As represented in Table 2, thirteen bit-line connections may be saved using the connection layout technique described herein with respect toFIG. 3. In particular, three, two, and eight bit-line connections are eliminated for the second, third and fifth bit-lines104,150, and212, respectively.

By reducing the number of bit-line connections, the speed of reading the data out of the ROM array can be enhanced. Also, the dynamic power can be reduced, since the drain/source capacitances are reduced and the associated noise is removed from the system (enhancing read margins). Additionally, since reference lines can be omitted, the density of the ROM array can be improved, because the routing of the reference lines can be avoided. Further, some interconnections to couple the source and drain terminals of adjacent memory cells to bit-lines can be omitted, thereby simplifying routing layout for the circuit. Additionally, during standby modes, which can represent a significant portion of the usable life of the memory array, since the bit-lines can have the same voltage potential, current leakage through the transistors is reduced. Moreover, since at least some of the memory cells may be interconnected without connecting to a bit-line, leakage via such memory cells can be eliminated, thereby reducing static power consumption.

FIG. 4depicts a flow diagram400of a particular example of a method of programming a ROM array using the memory cell configurations ofFIGS. 1A-1D. At402, a selected bit to be programmed to a selected memory cell of a read-only memory (ROM) array is determined. Advancing to404, if the value of the selected bit is zero, the method proceeds to406, and the drain and source terminals of the bit-cell (memory cell) can be coupled to different bit-lines. Continuing to408, if the selected bit is the last bit, the method advances to410, and the method is terminated. Otherwise, the method returns to402, and another bit is selected.

Returning to404, if the value of the selected bit is not zero, then the method advances to412, and preceding and next bits to be stored within a column of memory cells can be examined to determine values of bits surrounding the selected bit. In an example, all of the bits to be programmed within a column of the memory array may be examined. At414, if the selected bit is not between two zero values bits, the method advances to416. At416, if the selected bit is being programmed before a zero value, the method proceeds to418, and bit-cells (memory cells) can be programmed to have their source and drain terminals in common from the first bit-cell to the bit-cell before the last bit-cell to be programmed to a one value. The method continues to408, and if the selected bit is the last bit, the method terminates at410. Otherwise, the method returns to402.

Returning to416, if the selected bit is not being programmed in front of (before) a zero value, the method advances to419. At419, if the selected bit is being programmed after a zero, the method advances to420, and the bit-cells can be programmed to have their source and drain terminals in common from the second bit-cell to the last bit-cell to be programmed to a one value. The method moves to408, and if the selected bit is the last bit, the method terminates at410. Otherwise, the method returns to402.

Returning to419, if the selected bit is not being programmed after a zero, the method advances to421, and all the bit-cells of the column can be programmed to have their source and drain in common from the first to the last bit-cell. The method terminates at410.

Returning to414, if the selected bit is being programmed between two zero values, the method advances to422. At422, if the selected bit is to be programmed in a sequence of bits that is less than three consecutive one values, the method proceeds to424, and the drain and source terminals of each memory cell representing a one value can be coupled to the same bit-line. The method continues to408, and if the selected bit is the last bit, the method terminates at410. Otherwise, the method returns to402.

Returning to422, if the selected bit is to be programmed in a sequence that is greater than two consecutive one values, the method advances to426, and the bit-cells can be programmed to have their source and drain terminals in common from the second bit-cell to the bit-cell before the last bit-cell to be programmed to a one value. The method advances to408, and if the selected bit is the last bit, the method terminates at410. Otherwise, the method returns to402.

In general, the embodiment depicted inFIG. 4is provided for illustrative purposes only, and it is not intended to be limiting. In an alternative example, “one” values may be represented by memory cells having source and drain terminals coupled to different bit-lines. Further, in an alternative example, the various decision blocks may be replaced with appropriate decision blocks to connect source and drain terminals of memory cells representing zero values. Further, though the example ofFIG. 4refers to selected bits, in an embodiment, the selected bits can include an entire sequence of bits to be represented by a column within the ROM array. Further, the order of the decision blocks may be rearranged. For example, the method may test if the selected bits follow a zero value first, before testing whether the bits are between two zero values. It should be understood that the example ofFIG. 4represents only one possible, non-limiting example of a method of programming a ROM array, and that other configurations of the method flow may be understood by one of skill in the art based on the present disclosure.

FIG. 5depicts a flow diagram500of a second example of a method of programming a ROM array according to the embodiments of the memory cells100,120,140, and150depicted inFIGS. 1A-1D. At502, a data configuration for the ROM array is received, where the ROM array can include a plurality of word lines, a plurality of bit-lines including first and second bit-lines, and a plurality of transistors arranged in an array, and where each transistor can include a gate terminal coupled to a particular word line.

Advancing to504, a selected transistor of the ROM array is programmed to represent a zero value by connecting a source terminal of the selected transistor to the first bit-line and by connecting a drain terminal of the selected transistor to the second bit-line. Continuing to506, one or more selected transistors of the ROM array can be programmed to represent a corresponding number of “one” values by selectively connecting source and drain terminals of the one or more selected transistors to one of a common bit-line or a terminal of an adjacent transistor within the ROM array.

As discussed above with respect toFIGS. 3 and 4, if less than three consecutive one values are to be programmed between two zero values, each of the one-value transistors has source and drain terminals coupled to the same bit-line. On the other hand, if more than three consecutive one values are to be programmed or if one values are programmed that are not between two zero values within a column of the ROM array, at least some of the sources and drains may be coupled together without being coupled to a bit-line, thereby reducing a number of connections associated with the bit-lines.

In a particular embodiment, programming the one or more selected transistors of the ROM array to represent the corresponding number of one values can include programming the one or more selected transistors to have their source and drain terminals coupled to a common bit-line, when two or fewer one values are to be programmed between two zero values. In another particular embodiment, programming the one or more selected transistors of the ROM array can include programming selected transistors of the one or more selected transistors to have their source and drain terminals coupled in common, when three or more one values are to be programmed between two zero values.

In still another particular embodiment, programming the one or more selected transistors of the ROM array can include programming selected transistors of the one or more selected transistors to have their source and drain terminals in common from a first transistor to a transistor before a last transistor to be programmed to a one value, when the selected transistors are programmed before a zero value but not between two zero values. In yet another particular embodiment, the one or more transistors can be programmed to one values by programming selected transistors of the one or more selected transistors to have their source and drain terminals in common from a second transistor to a last transistor to be programmed to a one value, when selected transistors are programmed after a zero value but not between two zero values. In another particular embodiment, the one or more transistors can be programmed to one value by programming selected transistors of the one or more selected transistors to have their sources and drains terminals in common from a first transistor to a last transistor, when selected transistors are not programmed after a zero neither before a zero and not between two zero values. The method terminates at508.

FIG. 6depicts a flow diagram600of another example of a method of programming a read-only memory (ROM) array. At602, a first gate terminal of a first memory cell is coupled to a first word line of a plurality of word lines. In an example, the ROM array includes a plurality of bit-lines, a plurality of word lines, and a plurality of transistors, where each transistor including a gate terminal, a drain terminal, and a source terminal. Advancing to604, a data value to be represented by the first memory cell within the ROM array is determined.

Continuing to606, a first drain terminal of the first memory cell is coupled to a first bit-line of a plurality of bit-lines and a first source terminal of the first memory cell is coupled to a second bit-line of the plurality of bit-lines when the determined data value comprises a zero value. Proceeding to608, drain and source terminals of the first memory cell are coupled to each other or only the drain (or the source) is connected to a bit-line and the source (or the drain) is in common with adjacent bit-cell when the determined data value comprises a one value. The method terminates at610.

It should be noted that the flow diagrams above are provided for illustrative purposes only, and are not intended to be limiting. Further, it should be noted that the individual activities shown in the flow diagrams do not have to be performed in the order illustrated or in any particular order. Moreover, various activities described with respect to the methods identified herein can be executed in serial or parallel fashion. Some activities may be repeated indefinitely, and others may occur only once. Various embodiments may have more or fewer activities than those illustrated.

In an example, when the determined data value comprises a one value to be programmed between two memory cells representing zero values, the method further includes determining a number of consecutive “one” values to be programmed. Additionally, the method can include coupling the drain and source terminals together from a second memory cell to a memory cell before a last memory cell to be programmed to represent a one value when the determined number of consecutive one values is greater than two and coupling the drain and source terminals of the memory cell together through a common bit-line when the determined number of consecutive one values is not greater than two.

In another example, the source and drain terminals can be coupled together via a common wire trace that is not coupled to a bit-line, when the determined number of consecutive “one” values is greater than two. In another example, when the determined data value is a one value to be programmed before a memory cell representing a zero value, the method can include coupling the source and drain terminals together from a first memory cell to a memory cell before a last memory cell to be programmed to represent a one value.

In still another example, when the determined data value is to be programmed after a memory cell representing a zero value, the method can include coupling the source and drain terminals together from a second memory cell to a last memory cell to be programmed to represent a one value. In still another example, at least some memory cells can be configured to represent consecutive one values within the ROM array by connecting their source and drain terminals together and without connecting them to a bit-line.

In conjunction with the examples of the memory arrays and methods described above with respect toFIGS. 1A-6, a read-only memory array and a technique for configuring the transistor connections to represent particular data values are disclosed, which reduce the number of bit-line connections, simplify routing complexity, increase access speed, and reduce dynamic power consumption. In an example, a ROM array is disclosed, which can include transistors with their source and drain terminals coupled to different bit-lines to represent zero values and having their source and drain terminals coupled to less than two bit-lines to represent one values. In an example, the transistors can be configured to represent one values by connecting their source and drain terminals to a common bit-line, or by connecting the source and drain terminals in common without connecting them to a bit-line, or by connecting the source (or drain) terminal to terminals of an adjacent memory cell configured to represent a one value and drain (or source) terminal to a bit-line. In an example, transistors to be programmed to a one value may be coupled together by their source and/or drain terminals without connecting to a bit-line.

Many additional modifications and variations may be made in the techniques and structures described and illustrated herein without departing from the spirit and scope of the present disclosure. For example, the NMOS transistors can be replaced with PMOS transistors. Additionally, the transistor configurations can be reversed, such that one values are represented by connecting the source and drain terminals of a transistor to different bit-lines, and zero values are represented by connecting the source and drain terminals to the same bit-line or by connecting the source and/or drain terminals to terminals of an adjacent transistor. Further, while the above-examples have generally described the capability of reading a single target cell, it should be understood that, in some instances, multiple target cells may be read at one time. Accordingly, the present disclosure should be clearly understood to be limited only by the scope of the claims and the equivalents thereof.