Non-volatile passive matrix device and method for readout of the same

In a non-volatile passive matrix memory device comprising an electrically polarizable dielectric memory material exhibiting hysteresis between first and second sets of addressing electrodes, the electrodes of the first set are word lines and the electrodes of the second set are bit lines of the memory device. A memory cell with a capacitor-like structure is defined in the memory material at the overlap between a word line and a bit line. The word lines are divided into segments with each segments sharing and being defined by adjoining bit lines and means are provided for connecting each bit line of a segment with a sensing means, thus enabling simultaneous connections of all memory cells of a word line segment for readout via the bit lines of the segment. Each sensing means senses the charge flow in a bit line in order to determine a logical value stored in a memory cell defined by the bit line. In a readout method for a memory device of this kind a word line of a segment is activated according to a protocol by setting its potential to a switching voltage of the memory cell during at least a portion of a read cycle, while keeping the bit lines of the segment at zero potential, during which read cycle a logical value stored in the individual memory cells is sensed by the sensing means. Use in a volumetric data storage apparatus with a plurality of stacked layers which each comprises a non-volatile passive matrix memory device.

Before giving a detailed description of preferred embodiments, the general background of the present invention shall be discussed in order to give a better understanding of how a passive matrix memory, or even a single memory cell in such a memory works. In this connection reference is made to FIG. 1 , which shows a typical so-called “hysteresis loop” of a ferroelectric material, whereas the polarization P of the ferroelectric material is plotted versus the electric field E. The value of the polarization will travel around the loop in the direction indicated. A ferroelectric material with a hysteresis loop as shown in FIG. 1 will change its net polarization direction (“switch”) upon application of an electric field E that exceeds a so-called coercive electric field E c . As the electric field E exceeds the coercive electric field E c , the polarization P changes abruptly to a large positive value &plus;P r (assuming starting at negative polarization at zero electric field). This positive polarization &plus;P r remains until a large negative electric field exceeding a negative coercive electric field −E c changes the polarization again back to negative polarization. In this way, memory devices provided with capacitors comprising ferroelectric material will exhibit a memory effect in the absence of an applied external electric field, making it possible to store non-volatile data by application a potential difference across the ferroelectric material, which evokes a polarization response, the direction (and magnitude) thereof may thus be set and left in a desired state. Likewise, the polarization status can be determined. Storing and determining data will be described in more detail below. Depending on the required switching speed etc., a nominal voltage V s employed for driving the polarization state of the ferroelectric material is typically selected considerably larger than the coercive voltage E c . The nominal voltage V s is generically illustrated with a dashed line in FIG. 1 , but is by no means limited to this particular value. Other values can be applicable. FIG. 2 illustrates a portion of a memory matrix 10 of a passive matrix memory 11 showing two to each other opposing sets of parallel electrodes: word line electrodes WL and bit line electrodes BL. The word line and the bit line electrodes WL;BL are arranged perpendicular to each other, whereby at the intersecting areas, they define side-walls of certain volume elements of an insulating ferroelectric material (described in more detail below) defining the volume of capacitor-like memory cells in the memory matrix 10 . Now it is referred to FIG. 3 , which is an illustration of a cross-sectional view along line A-A in FIG. 2 a. The dielectric of each “capacitor” is the ferroelectric material in a ferroelectric layer 12 , where the thickness of the material defines the height h of the volume elements defining the memory cells 13 . For reasons of simplicity, only three crossing points between the word line and bit line electrodes WL:BL are illustrated in this FIG. 2 . By application of a potential difference V s between two opposing electrodes, the word line WL and the bit line BL in a cell 13 , the ferroelectric material in the cell 13 is subjected to an electric field E which evokes a polarization response, having a direction which may be set and left in one of two stable states, positive or negative polarization, according to what is described for instance in FIG. 1 . The two state represent the binary states of “1” and “0”. Likewise, the polarization status in the cell 13 may be altered or deduced by renewed application of a potential difference between the two opposing electrodes WL and BL addressing that cell 13 , which either causes the polarization to remain unchanged after removal of the potential difference or to flip to the opposite direction. In the former case, a small current will flow in response to the applied voltage, while in the latter case the polarization change causes a large current. The current is compared to a reference, which can be provided in many ways (not shown), to be able to decide if it was a “0” or a “1”. The read is always a destructive read ending up in a “0” and the memory cell must therefore be restored to its initial state (since a “1” or a “0” always ends up in a “0” because of the destructive read). A more detailed description of how a passive matrix memory operates will be given in below when describing a preferred embodiment of the invention. Also in order to improve the understanding of the present invention, reference can be made to FIG. 4 illustrating another readout method for passive matrix memories, hereinafter called “full word read”, whereby an active word line, herein the first word line WL 1 comprising a desired memory cell 13 , is sensed over its entire word length. Full word read per se is a known concept described for instance in U.S. Pat. No. 6,157,578. In said document, however, the solution is directed to an active matrix memory device, with the purpose of increasing the speed of transferring data stored in a relatively large block of a memory matrix. The present invention is on the contrary related to passive matrix memories, whereby prior art knowledge regarding active matrices, such as described in U.S. Pat. No. 6,157,578, is not relevant since active devices does not have the problem with disturbing non-addressed cells. It is important to notice that according to the pulsing protocol for full word read in a passive matrix memory, unused word lines, in this case the second to the n.th word lines WL 2..n can be maintained at the same potential (or essentially the same) as the bit lines BL 1..n . Consequently, there is no disturbing signal on any of the non-addressed cells of the memory matrix 10 . For readout of data (sensing), the active word line, in this case the first word line WL 1 , is brought to a potential causing current I to flow through the cells on the crossing bit lines BL 1..n. The magnitude of the current I depends on the polarization state in each cell 13 and are determined by sense amplifiers SA 1..n , one for each bit line BL 1..n as shown in FIG. 4 . The full word read method provides several advantages such as: that the readout voltage may be chosen much higher than the coercive voltage without incurring partial switching in non-addressed cells, and that it is compatible with a large matrix. The preferred embodiments of the present invention are illustrated in FIGS. 5 - 7 of the drawings. An accompanying timing diagram that accomplish 0V disturb of non-addressed memory cells while providing the switching voltage V s on all cells of the active word line WL 1 during reading of all cells in an active segment is shown in FIG. 7 a and yet another one in FIG. 7 b. With reference now to FIG. 5, a passive ferroelectric matrix memory according to a first preferred embodiment of the invention provided as a 16 Megabit (16 Mb) memory matrix arranged as 256 kilobits by eight organization (256 Kb×8), or in other words, 256 thousand word lines of 64 bits is illustrated. Other organizations including ×9, ×16, ×18, ×32, or the like are also possible memory architectures. In FIG. 5 , there are 6 word lines WL 1 . . . WL n shown. Other word lines are included within the memory matrix 10 but are not shown. Each word line WL 1 . . . WL n is divided into eight (of which only three are shown) segments S 1 , S 2 . . . S 8 of eight bits each, which means that the word length is eight bits (eight memory cells). The word lines WL corresponding to the first word line segment S 1 are labelled WL 1S1 , WL 2S1 . . . WL nS1 . For simplicity, the bit lines BL are not labelled. Unlike conventional passive matrix memories employing partial word read, all memory cells within a word line segment are connected simultaneously to sense amplifiers SA 1..n . Data stored or to be stored in the memory matrix 10 is accessible by means of an associated row decoder and column decoder (not illustrated in this figure) The data maintained within the memory cells of the memory matrix 10 is read out according to a pulsing protocol, with reference to FIG. 6 a by means of a number of sense amplifiers SA 1..n coupled to the bit lines. All of the bit lines (of which two are indicated with arrows) from one word line segment (in this case the first segment) S 1 are routed to different multiplexers 25 , and simultaneously selected when the given word line WL 1 is active. In this manner, all bit lines of the first word line in the segment S 1 are simultaneously read in the “full word configuration”, while maintaining shared usage of a sense amplifier array comprising sense amplifiers SA 1..n through the multiplexers 25 . The matrix memory 10 illustrated in FIG. 5 comprises three word line segments S 1..3 . Preferably, the matrix memory is provided with n multiplexers 25 and a corresponding number of segments S 1..n . According to a preferred embodiment of the invention, the number of memory cells is at least 256 cells per segment. Coupled with 32:1 multiplexers M 1..n this permits an 8192 bits wide memory with only 32 duplications of the word-line drivers. Each word line WL is segmented according to the number of sense amplifiers SA 1..n provided. All of the bit lines BL from one word-line segment S 1..n are routed to multiplexers 25 , and simultaneously selected when the given word line WL is active. In this manner, all bit lines BL of the word-line segment 10 are simultaneously read in the “full word configuration”, while maintaining the shared usage of the sense amplifier array SA 1..n through the multiplexers 25 . In FIG. 6 , there is shown an alternative embodiment of the present invention, wherein the multiplexers are substituted by gate means. The gate means enable the bit lines in the same way as the above-described multiplexers. Preferably, the gate means is a pass gate, preferably arranged under the capacitors making up the matrix. FIGS. 7 a and 7 b depict alternative timing diagrams for a full word read cycle. FIG. 7 a illustrates a full word read timing diagram with a following write/read refresh cycle for a word line segment. This timing diagram is based on a four-level voltage protocol. According to this timing diagram all word and all bit lines are, when no cell in the matrix is read or written, kept at a quiescent voltage equal to zero volts. All memory cells having an addres represented by the crossings formed by an activated word line and by all bit lines within this segment which are to be read. The inactive word lines WL and all bit lines BL follow the same potential curves during the read cycle. During the read cycle the word line contacting the cells to be read is set to switching voltage V S . At the same time interval all bit lines are kept at zero voltage. In the illustrated timing diagram it is provided that application of the switching voltage V S on the word line side of a cell and a zero voltage on the bit line side of the same cell implies that a “0” is written into the cell. According to this, in both timing diagrams shown all cells on the active word lines are set into the zero-state after the read operation performed. Therefore, to restore data of the memory, it will be necessary to write back “1” only on the bit lines that has cells that should contain “1”. This is illustrated in both examples of FIGS. 7 a and 7 b, where reversed polarity of the voltage is applied on the “write 1 ” cells during the read cycle as indicated in the figures. FIG. 7 b illustrates an alternate timing diagram based on a four-level voltage protocol. According to this embodiment all word lines and bit lines are, when no cell in the matrix is read or written, kept at a quiescent voltage Vs/3. The exact values for all timing points illustrated as examples in FIGS. 7 a and 7 b are dependent on the materials of the memory cells and on details in the design. The time intervals 2 - 1 , 4 - 3 in FIG. 7 b, can for instance be zero or negative. The number of voltage levels and the voltage levels themselves in the pulsing protocol may be chosen arbitrarily as long as the requirements to perform future word read is accomplished. Further, the polarity of the voltages according to the protocols shown may as well be reversed. Preferably, the word line drivers can be integrated in the area under the matrix and hence not increase to total area of the device. The segmented word lines could as well be implemented on stacked memory planes, having the bit lines connected vertically to the multiplexers or gate means. This is illustrated in FIG. 8 , which shows schematically and in cross section an embodiment wherein memory devices according to the invention are provided in a stacked arrangement. This realizes a volumetric data storage apparatus wherein each layer or memory plane comprises one memory device. By providing the memory devices in a staggered arrangement, the respective word lines and bit lines can be connected over so-called staggered vias, i.e. alternating horizontal and vertical “over-the-edge” connections with driver and control circuitry in the substrate. The substrate can be inorganic, i.e. silicon-based, and hence the circuitry may be implemented in e.g. a compatible CMOS technology. FIG. 8 shows only two memory planes (note that only a limited number of bit line are shown), but in practice the volumetric data storage apparatus may comprise a very large number of memory planes, from 8 and well beyond 100 or more, realizing a memory with very high capacity and storage density, as each memory plane only will be about 1 &mgr;m thick or even less. Advantages of the passive matrix memory device described above include simplicity of manufacture and high density of cells. Further advantages are: a) During the read cycle all non-addressed memory cells will experience a zero volt potential (or a small potential). This will reduce the number of disturb signals that could result in loss of memory content as well as eliminate all disturbs during a read operation that give rise to sneak currents. b) The data transfer rate will be at the maximum rate as allowed by the number of bit lines within a segment. c) The readout voltage V S may be chosen much higher than the coercive voltage without incurring partial switching in non-addressed cells. This allows for switching speeds approaching the highest possible speed of polarizable material in the cells. d) The readout method is compatible with large matrices. In addition the memory device of the invention can be realized with a reduced number of sense amplifiers, which is an advantage when the memory is large and also with regard to the power consumption of the sense amplifiers. This can be high, but may also be reduced to some extent by appropriate power management of the driving and addressing circuitry. Moreover, a reduction in the number of sense amplifiers implies that real estate devoted to sense means can be balanced to achieve overall area optimization in the memory device. Finally, the segmentation of the word lines implies that errors during readout or addressing will be located in a single word in the event of a single word line fault.