DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

A display device includes: a substrate; a conductive pattern layer disposed on the substrate; a buffer layer disposed on the conductive pattern layer; an active pattern layer disposed on the buffer layer and including a channel region and a conductive region adjacent to the channel region; an insulating pattern layer disposed on the channel region; an oxide pattern layer disposed on the insulating pattern layer; a gate electrode disposed on the oxide pattern layer; and a connecting member electrically connected to the conductive pattern layer and the conductive region. The connecting member and the oxide pattern layer include a same material.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority to and benefits of Korean Patent Application No. 10-2022-0096804 under 35 U.S.C. § 119, filed on Aug. 3, 2022, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

BACKGROUND

1. Technical Field

Embodiments relate to a display device and a manufacturing method of the display device.

2. Description of the Related Art

Display devices such as a liquid crystal display (LCD) and an organic light diode (OLED) display include a display panel including a plurality of pixels for displaying images. Each pixel includes a pixel electrode for receiving a data signal, and the pixel electrode is connected to at least one transistor to receive a data signal.

To manufacture the display device, layers of various types of materials are stacked on a substrate, and the layers are patterned according to a method such as a photolithography process including an exposure method by using optical masks so various electrical devices such as transistors and conductors may be formed.

SUMMARY

Embodiments provide a display device and a manufacturing method of the display device capable of reducing a manufacturing cost and time by reducing the number of masks used for a manufacturing process and by controlling a carrier concentration of a channel region of a transistor of the display device, and capable of reducing deterioration of characteristics of a light-emitting device by reducing contact resistance between conductive layers.

In an embodiment, a display device may include: a substrate; a conductive pattern layer disposed on the substrate; a buffer layer disposed on the conductive pattern layer; an active pattern layer disposed on the buffer layer and including a channel region and a conductive region adjacent to the channel region; an insulating pattern layer disposed on the channel region; an oxide pattern layer disposed on the insulating pattern layer; a gate electrode disposed on the oxide pattern layer; and a connecting member electrically connected to the conductive pattern layer and the conductive region, wherein the connecting member and the oxide pattern layer may include a same material.

The oxide pattern layer and the connecting member may include an oxide semiconductor.

A carrier concentration of the connecting member may be higher than a carrier concentration of the oxide pattern layer.

The display device may further include a first insulating layer disposed between the connecting member and the buffer layer, wherein the first insulating layer and the insulating pattern layer may include a same insulating material.

The first insulating layer and the buffer layer may have a first opening exposing the conductive pattern layer, the conductive region may include a first conductive region adjacent to a first side of the channel region, and the connecting member may include a first connecting member electrically connected to the conductive pattern layer and the first conductive region through the first opening.

The display device may further include a second insulating layer disposed on the gate electrode and the connecting member, wherein the second insulating layer may contact an upper surface of the gate electrode and an upper surface of the connecting member.

The display device may further include a third insulating layer disposed on the second insulating layer; and a pixel electrode disposed on the third insulating layer, wherein the second insulating layer and the third insulating layer may have a second opening exposing the first connecting member, and the pixel electrode may be electrically connected to the first connecting member through the second opening.

The display device may further include a driving voltage line. The driving voltage line and the conductive pattern layer may include a same conductive material. The first insulating layer and the buffer layer may have a third opening exposing the driving voltage line, the conductive region may include a second conductive region adjacent to a second side of the channel region, and the connecting member may include a second connecting member electrically connected to the driving voltage line and the second conductive region through the third opening.

An edge portion of the gate electrode, an edge portion of the oxide pattern layer, and an edge portion of the insulating pattern layer may be aligned with each other.

The edge portion of the insulating pattern layer may be aligned with a boundary area between the channel region and the conductive region.

In an embodiment, a display device may include: a substrate; a first conductive layer including a conductive pattern layer disposed on the substrate; a buffer layer disposed on the first conductive layer; an active pattern layer disposed on the buffer layer and including a channel region and a conductive region adjacent to the channel region; a first insulating layer including an insulating pattern layer disposed on the channel region; an oxide pattern layer disposed on the insulating pattern layer; a connecting member disposed on the first insulating layer; and a gate electrode disposed on the oxide pattern layer, wherein the connecting member may be electrically connected to the conductive pattern layer and the conductive region, and the connecting member and the oxide pattern layer may include a same material.

A carrier concentration of the connecting member may be higher than a carrier concentration of the oxide pattern layer.

The first insulating layer and the buffer layer may have a first opening exposing the conductive pattern layer, the conductive region may include a first conductive region adjacent to a first side of the channel region, and the connecting member may include a first connecting member electrically connected to the conductive pattern layer and the first conductive region through the first opening.

The display device may further include a second insulating layer disposed on the gate electrode and the connecting member, wherein the second insulating layer may contact an upper surface of the gate electrode and an upper surface of the connecting member.

The display device may further include a third insulating layer disposed on the second insulating layer; and a pixel electrode disposed on the third insulating layer, wherein the second insulating layer and the third insulating layer may have a second opening exposing the first connecting member, and the pixel electrode may be electrically connected to the first connecting member through the second opening.

A conductive layer may not be disposed between the second insulating layer and the third insulating layer.

The first conductive layer may further include a driving voltage line. The driving voltage line and the conductive pattern layer may include a same conductive material, and the first insulating layer and the buffer layer may have a third opening exposing the driving voltage line, the conductive region may include a second conductive region adjacent to a second side of the channel region, and the connecting member may include a second connecting member electrically connected to the driving voltage line and the second conductive region through the third opening.

In an embodiment, a method for manufacturing a display device may include: forming a first conductive layer including a conductive pattern layer on a substrate; forming a buffer layer on the first conductive layer; forming a semiconductor layer on the buffer layer; forming a first insulating layer on the semiconductor layer; forming a first opening exposing a part of the first conductive layer and a second opening exposing a part of the semiconductor layer by patterning the first insulating layer and the buffer layer; forming an oxide layer on the first insulating layer; forming a second conductive layer on the oxide layer; forming an oxide pattern layer and a gate electrode disposed on the oxide pattern layer by patterning the second conductive layer and the oxide layer; exposing an upper surface of the oxide layer without exposing an upper surface of the oxide pattern layer by removing the second conductive layer without removing the gate electrode; forming an insulating pattern layer disposed below the oxide pattern layer by patterning the first insulating layer; and making the exposed oxide layer conductive to form a conductive oxide layer.

The conductive oxide layer may be electrically connected to the part of the first conductive layer through the first opening.

The method may further include heat-treating the oxide layer after the forming of the oxide layer.

According to the embodiments, the carrier concentration of the channel region of the transistor of the display device is controlled, and the number of masks used for a manufacturing process is reduced such that a manufacturing cost and time may be reduced. The contact resistance between conductive layers is reduced such that deterioration of characteristics of the light-emitting device may be reduced.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The phrase “in a plan view” means viewing an object portion from the top, and the phrase “in a cross-sectional view” means viewing a cross-section of which the object portion is vertically cut from the side.

A display device according to an embodiment will now be described with reference toFIG.1.

FIG.1shows a schematic top plan view of a display device1000according to an embodiment.

Referring toFIG.1, the display device1000according to an embodiment may include an organic light emitting device, a plasma display device, a field emission display, a quantum dot emissive display device, a micro LED display device, and a liquid crystal display. The disclosure describes the organic light emitting device as the display device1000, but embodiments are not limited thereto.

The display device1000may include a substrate110including a display area DA, in which pixels PX for displaying images are disposed, and a peripheral area PA disposed around the display area DA. The peripheral area PA may include the pixels PX and may display images, or may not include the pixels PX.

The substrate110may have a side that is parallel to a first direction DR1 and a second direction DR2 that is perpendicular to the first direction DR1, and a direction that is perpendicular to the substrate110upward is marked as a third direction DR3. A view on the plane in the first direction DR1 and the second direction DR2 is referred to as a plan view, and a view on a cross-section in its perpendicular direction is referred to as a cross-sectional view.

Signal lines or voltage lines electrically connected to the pixels PX and applying signals or driving voltages may be positioned in the display area DA. The signal lines or the voltage lines may include scan lines151for transmitting scan signals to the pixels PX, data lines171for transmitting data signals to the pixels PX, and driving voltage lines172for transmitting a driving voltage to the pixels PX. The respective pixels PX may include at least one transistor, at least one light-emitting device, and at least one capacitor.

In a plan view, the driving voltage lines172and the data lines171may substantially extend in the second direction DR2, but embodiments are not limited thereto. In a plan view, the scan lines151may substantially extend in the first direction DR1, but embodiments are not limited thereto.

A scan driver400connected to the scan lines151and supplying scan signals and a data driver500connected to the data lines171and supplying data signals may be positioned in the peripheral area PA.

The scan driver400may include transistors formed on the substrate together with the transistors positioned in the display area DA.FIG.1shows an example in which the scan driver400is positioned on respective sides of the display area DA. However, embodiments are not limited thereto, the scan driver400may be positioned on a side.

The data driver500may be made of an integrated circuit (IC), and may be mounted on the substrate or a circuit board connected to the substrate. The data driver500may apply driving voltages to the driving voltage line172.

A structure disposed around the transistors included by the pixels of the display device1000according to an embodiment will now be described with reference toFIG.2andFIG.3together withFIG.1.

FIG.2shows a schematic top plan view of a region in which a transistor is positioned, disposed in a display area of a display device according to an embodiment, andFIG.3shows a schematic cross-sectional view of a display device with respect to a line AA-BB shown inFIG.2.

Referring toFIG.2andFIG.3, the display device1000may include a substrate110. The substrate110may include an insulating material such as glass or plastic, and may have flexibility.

A first conductive layer CL1including a conductive pattern layer111and signal lines and voltage lines may be positioned on the substrate110. The signal lines and voltage lines may include a driving voltage line172, a data line171, a common voltage line, and an initialization voltage line.

The conductive pattern layer111may be positioned on the above-noted pixels PX. The conductive pattern layer111may include various conductive metals or a semiconductor material with a conductive characteristic corresponding to them.

A buffer layer120may be an insulating layer, and may be positioned on the first conductive layer CL1. The buffer layer120may include an inorganic insulating material and/or an organic insulating material such as a silicon nitride (SiNx), a silicon oxide (SiOx), or a silicon oxynitride (SiOxNy).

An active layer may include active pattern layers131, and may be positioned on the buffer layer120. The active pattern layers131positioned on the respective pixels PX may include a channel region134for forming a channel of the transistor T, and conductive regions positioned around (or adjacent to) respective sides of the channel region134. The conductive regions of the active pattern layer131may include a source region133and a drain region135of the transistor T. The positions of the source region133and the drain region135may be exchangeable.

The drain region135may include an opening31aformed in a portion, and the source region133may include an opening31bformed in a portion. However, embodiments are not limited thereto. As shown inFIG.2, the respective openings31aand31bmay be island types formed in the drain region135and the source region133. Hence, carriers (e.g., holes and/or electrons) may move through the portion of the drain region135above and/or below the opening31a, and the carriers may move through the portion of the source region133above and/or below the opening31b.

The active layer may include an oxide semiconductor at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), hafnium (Hf), and titanium (Ti), and oxygen (O). For example, the active layer may include at least one of an ITO, an IGZO, an ITGZO, or an IGTO. The active layer may also be referred to as a first oxide semiconductor layer OS1.

The active pattern layer131may further include a source outer region132positioned outside the source region133, and a drain outer region136positioned outside the drain region135. The source outer region132and the drain outer region136may respectively have a carrier concentration that is less than the carrier concentration of the source region133and the drain region135. In another example, the source outer region132and the drain outer region136may be omitted.

The conductive pattern layer111may overlap the active pattern layer131of the transistor T, e.g., the channel region134, to prevent external light from reaching the channel region134, thereby reducing a leakage current and deterioration of characteristics of the transistor T.

A first insulating layer140may be positioned on the active layer including the active pattern layer131. The first insulating layer140is referred to as a gate insulating layer.

The first insulating layer140may have openings40a,40bb,40cc, and40d.

The opening40amay extend to the buffer layer120and may expose the upper portion of the conductive pattern layer111, e.g., by passing through the first insulating layer140and the buffer layer120. For example, the first insulating layer140and the buffer layer120may have an opening40aoverlapping the conductive pattern layer111.

The opening40bbmay be formed to the upper portion of the active pattern layer131and may expose the upper portion of the drain region135. For example, the first insulating layer140may have an opening40bboverlapping a part of the active pattern layer131, e.g., the drain region135. The opening40bbmay overlap the opening31aof the drain region135in a plan view.

The opening40ccmay expose the upper portion of the active pattern layer131, e.g., the upper portion of the source region133. For example, the first insulating layer140may have an opening40ccoverlapping a part of the active pattern layer131, e.g., the source region133. The opening40ccmay overlap the opening31bof the source region133in a plan view.

The opening40dmay extend to the buffer layer120and may expose the upper portion of the driving voltage line172, e.g., by passing through the first insulating layer140and the buffer layer120. For example, the first insulating layer140and the buffer layer120may have the opening40doverlapping the driving voltage line172.

An insulating pattern layer144positioned in the first insulating layer140may be positioned between the opening40bband the opening40cc. The insulating pattern layer144may be considered to be included in the first insulating layer140, and the insulating pattern layer144may be spaced from the other first insulating layer140. The insulating pattern layer144and the first insulating layer140may be formed of (or may include) a same material (e.g., a same insulating material). The insulating pattern layer144and the first insulating layer140may have different thicknesses. For example, the thickness of the insulating pattern layer144may be smaller than the thickness of the the first insulating layer140.

The insulating pattern layer144may overlap the channel region134of the active pattern layer131, e.g., in a plan view, and may be positioned on the channel region134. The insulating pattern layer144may not substantially overlap the conductive region of the active pattern layer131. An edge portion of the insulating pattern layer144may include an edge portion aligned with a boundary area between the channel region134and the drain region135, and an edge portion aligned with a boundary area between the channel region134and the source region133.

A second oxide semiconductor layer OS2may include an oxide pattern layer164and connecting members161and162. The second oxide semiconductor layer OS2may be positioned on the first insulating layer140including the insulating pattern layer144.

The oxide pattern layer164may be positioned on the insulating pattern layer144. The oxide pattern layer164may overlap the channel region134of the active pattern layer131and the insulating pattern layer144, and may not substantially overlap the conductive region of the active pattern layer131. An edge portion of the oxide pattern layer164may be aligned with the edge portion of the insulating pattern layer144, and may include an edge portion aligned with the boundary area between the channel region134and the drain region135, and an edge portion aligned with the boundary area between the channel region134and the source region133.

The connecting members161and162and the oxide pattern layer164may be positioned in a same layer, and may include a same material (e.g., a same oxide semiconductor material). The connecting member161may be electrically connected to the drain region135and the conductive pattern layer111, and may electrically connect the drain region135and the conductive pattern layer111through the opening40a. The connecting member162may be electrically connected to the source region133and the driving voltage line172, and may electrically connect the source region133and the driving voltage line172through the opening40d.

The connecting members161and162may have carrier concentrations that are higher than the carrier concentration of the oxide pattern layer164to thus have conductivity. For example, the connecting members161and162may include an oxygen depletion region and/or hydrogen having a higher concentration than the oxide pattern layer164.

The oxide pattern layer164may function as an oxygen supplying layer for injecting oxygen to the active pattern layer131through the insulating pattern layer144during the process for manufacturing a display device. An oxygen depletion area may be partly formed on the active pattern layer131in a deposition process, and in case that an insulating layer is deposited on the active pattern layer131, hydrogen (H) may be injected into the oxygen depletion area to increase mobility of the active pattern layer131. However, in case that the carrier concentration is excessively increased, it may be difficult to obtain the driving voltage for the transistor T to drive the respective pixels PX.

According to an embodiment, the oxide pattern layer164may supply oxygen to the adjacent insulating pattern layer144, the oxygen supplied to the insulating pattern layer144may be injected into the channel region134of the active pattern layer131, and the hydrogen permeating into the oxygen depletion area of the active pattern layer131may be discharged again to the insulating pattern layer144. The carrier concentration of the active pattern layer131may be reduced, a range of the driving voltage of the transistor T may be obtained, and dispersion (or distribution) of the initial threshold voltage of the transistor T may be increased.

The second oxide semiconductor layer OS2may include the same material as the first oxide semiconductor layer OS1(e.g., the oxide semiconductor included in the active layer including the active pattern layer131). The first and second oxide semiconductor layers OS1and OS2may include different materials.

The oxide pattern layer164according to an embodiment may include at least one of indium (In), gallium (Ga), zinc (Zn), tin (Sn), and hafnium (Hf), and oxygen (O). For example, the oxide pattern layer164may include at least one of an IGZO, a TZO, a TGO, an ITZO, an ITGO, or an ITZGO.

A second conductive layer CL2including a gate electrode154may be positioned on the oxide pattern layer164. The second conductive layer CL2may further include the above-noted scan line151. The gate electrode154may overlap the channel region134of the active pattern layer131, the insulating pattern layer144, and the oxide pattern layer164.

The gate electrode154may not substantially overlap the conductive region of the active pattern layer131. An edge portion of the gate electrode154may be aligned with the edge portion of the oxide pattern layer164and the edge portion of the insulating pattern layer144, and may include an edge portion aligned with the boundary area between the channel region134and the drain region135and an edge portion aligned with the boundary area between the channel region134and the source region133. In the process for manufacturing a display device, the gate electrode154may be patterned with the oxide pattern layer164disposed therebelow.

A method for manufacturing a display device according to an embodiment will now be described with reference toFIG.4toFIG.14together with the above-noted drawings.

FIG.4shows a schematic cross-sectional view of a display device in a process according to a method for manufacturing a display device according to an embodiment.

Referring toFIG.4, various types of conductive metal or semiconductor materials with conductive characteristics corresponding thereto may be stacked on the substrate110(e.g., an insulative substrate) and may be patterned to form a first conductive layer CL1including a conductive pattern layer111and signal lines and voltage lines such as driving voltage lines172. For example, the conductive pattern layer111and the driving voltage lines172may include a same conductive material or may be formed of a same conductive material. The patterning method may use a photolithography process including an exposure method by using an optical mask.

FIG.5shows a schematic cross-sectional view of a display device in a process according to a method for manufacturing a display device according to an embodiment, after the patterning process shown inFIG.4.

Referring toFIG.5, an insulating material may be stacked on the substrate110and the first conductive layer CL1to form a buffer layer120. A semiconductor material such as an oxide semiconductor may be stacked and patterned on the buffer layer120to form a semiconductor layer130. An insulating material may be stacked on the semiconductor layer130and the buffer layer120to form a first insulating layer140.

FIG.6shows a schematic cross-sectional view of a display device in a process according to a method for manufacturing a display device according to an embodiment, after the process shown inFIG.5.

Referring toFIG.6, the first insulating layer140and the buffer layer120may be patterned according to the photolithography process to form openings40a,40b,40c, and40d. In this instance, a dry etching process may be used.

The opening40amay be formed in the first insulating layer140and the buffer layer120to expose an upper surface of the conductive pattern layer111.

The opening40bmay be formed in the first insulating layer140to expose an upper surface of the semiconductor layer130shown inFIG.5. In case that the opening40bis etched, the oxygen depletion area may be increased in the exposed semiconductor layer130by an etching gas for dry etching and/or plasma, the carrier concentration (n+) of the portion135aof the semiconductor layer130exposed by the opening40bmay be increased to be conductive. The opening40cmay be formed in the first insulating layer140to expose the upper portion of the semiconductor layer130ofFIG.5. In case that the opening40cis etched, the oxygen depletion area may increase in the semiconductor layer130because of physical damage by the etching gas for dry etching and/or plasma, the carrier concentration (n+) of the portion133aof the semiconductor layer130exposed by the opening40cmay increase to be conductive.

Planar shapes of the opening40band the opening40care shown with dotted lines inFIG.2.

The opening40dmay be formed in the first insulating layer140and the buffer layer120to expose the upper portion of the driving voltage line172.

FIG.7shows a schematic cross-sectional view of a display device in a process according to a method for manufacturing a display device according to an embodiment, after the process shown inFIG.6.

Referring toFIG.7, the oxide layer160may be formed on the patterned first insulating layer140. The oxide layer160and the semiconductor layer130may include the same material, or may include a different material. The oxide layer160may be formed by using a sputtering process or a deposition process. In case that the oxide layer160is deposited, oxygen may be injected into the first insulating layer140.

The oxide layer160may then be heat-treated by a heat treatment process. By the heat treatment process, oxygen may be further injected into the first insulating layer140from the oxide layer160, and the oxygen in the first insulating layer140may be prevented by the oxide layer160from being vaporized upward and may be further injected downward into the semiconductor layer130.

FIG.8shows a schematic cross-sectional view of a display device in a process according to a method for manufacturing a display device according to an embodiment, after the process shown inFIG.7, andFIG.9shows a schematic cross-sectional view of a display device in a process according to a method for manufacturing a display device according to an embodiment, after the process shown inFIG.8.

Referring toFIG.8, a conductive material may be stacked on the oxide layer160to form a conductive layer150.

Referring toFIG.9, a photosensitive material layer such as photoresist may be stacked on the conductive layer150, and the photosensitive material layer may be exposed by using a halftone optical mask so the mask pattern layer50may be formed. The mask pattern layer50may include a first portion51and a second portion52that is thinner than the first portion51. The first portion51may include a portion overlapping the channel region134of the active pattern layer131.

FIG.10shows a schematic cross-sectional view of a display device in a process according to a method for manufacturing a display device according to an embodiment, after the process shown inFIG.9.

Referring toFIG.10, the conductive layer150and the oxide layer160may be etched by using the mask pattern layer50as an etching mask to expose the portions133aand135athat are changed to be conductive on the semiconductor layer130. In this instance, the gate electrode154overlapping the first portion51of the mask pattern layer50and an oxide pattern layer164disposed therebelow may be simultaneously patterned.

A partial region of the portion135aof the semiconductor layer130, which is distant from the second portion52of the adjacent mask pattern layer50, may be removed to form the opening31a. A partial region of the portion133aof the semiconductor layer130, which is distant from the second portion52of the adjacent mask pattern layer50, may be removed to form the opening31b. However, embodiments are not limited thereto.

FIG.11shows a schematic cross-sectional view of a display device in a process according to a method for manufacturing a display device according to an embodiment, after the process shown inFIG.10.

Referring toFIG.11, the mask pattern layer50shown inFIG.10may be etched back or ashed to remove the second portion52, and a mask pattern layer51aincluding the first portion51that became thin is formed. The mask pattern layer51amay overlap the gate electrode154and the oxide pattern layer164. For example, an upper surface of the conductive layer150may be exposed, and an upper surface of the gate electrode154may not be exposed.

FIG.12shows a schematic cross-sectional view of a display device in a process according to a method for manufacturing a display device according to an embodiment, after the process shown inFIG.11.

Referring toFIG.12together withFIG.11, the exposed conductive layer150may be etched and removed by using the mask pattern layer51aas an etching mask. In this instance, a wet etching process may be used, and an etchant that has sufficiently great selectivity for the conductive layer150with respect to the oxide layer160may be used. Accordingly, the conductive layer150, which is not covered by the mask pattern layer51abut is exposed, may be removed without removing the gate electrode154, and an upper surface and/or a side surface of the oxide layer160may be exposed without being etched and damaged and without exposing an upper surface of the oxide pattern layer164.

FIG.13shows a schematic cross-sectional view of a display device in a process according to a method for manufacturing a display device according to an embodiment, after the process shown inFIG.12.

Referring toFIG.13together withFIG.12, the exposed first insulating layer140may be etched by using the mask pattern layer51aas an etching mask to form the insulating pattern layer144below the oxide pattern layer164. In this instance, the dry etching process may be used.

The oxide layer160and the semiconductor layer130exposed during the etching process of the first insulating layer140may have a big oxygen depletion area because of the physical damage by the etching gas for a dry etching process and/or by plasma to increase the carrier concentration (n+) and be conductive. Accordingly, the active pattern layer131including the channel region134overlapping the insulating pattern layer144, and the source region133and the drain region135disposed on respective sides thereof may be formed. The conductive oxide layer160may form a connecting member161electrically connected to the drain region135and the conductive pattern layer111, and a connecting member162electrically connected to the source region133and the driving voltage line172.

The active pattern layer131may further include a source outer region132positioned outside the source region133, and a drain outer region136positioned outside the drain region135. In another example, the source outer region132and the drain outer region136may be omitted. The source outer region132and the drain outer region136may be covered by the first insulating layer140.

An opening40bbfor exposing the drain region135of the active pattern layer131and an opening40ccfor exposing the source region133of the active pattern layer131may be formed in the first insulating layer140.

FIG.14shows a schematic cross-sectional view of a display device in a process according to a method for manufacturing a display device according to an embodiment, after the process shown inFIG.13.

Referring toFIG.14together withFIG.13, the mask pattern layer51amay be removed, an insulating material (e.g., an inorganic insulating material) may be stacked on the substrate110to form a second insulating layer169, and an insulating material (e.g., an organic insulating material) may be stacked on the second insulating layer169to form a third insulating layer180. Hydrogen may be further injected into the source region133and the drain region135of the active pattern layer131, and the connecting members161and162by the depositing gas such as silane or ammonia used for a process for stacking the second insulating layer169.

An opening185for exposing the connecting member161may be formed by patterning the third insulating layer180and the second insulating layer169.

A third conductive layer including a pixel electrode191may be formed by stacking a conductive material on the third insulating layer180and patterning the conductive material. The pixel electrode191may be electrically connected to the connecting member161and the drain region135of the transistor T through the opening185. The third conductive layer may include a semi-transmitting conductive material or a reflective conductive material.

A fourth insulating layer350having an opening positioned on the pixel electrode191may be formed by stacking an insulating material on the pixel electrode191and the third insulating layer180and patterning the insulating material. The fourth insulating layer350may include an organic insulating material such as a polyacryl-based resin or a polyimide-based resin.

A light emitting diode ED may be formed by sequentially forming an emission layer370and a common electrode270on the pixel electrode191and the fourth insulating layer350. The common electrode270may include a conductive transparent material. One of the pixel electrode191and the common electrode270may be a cathode and another one may be an anode.

The conductive pattern layer111may be electrically connected to the drain region135of the active pattern layer131and the pixel electrode191so a current change rate in a saturation region in a voltage-current characteristic graph of the transistor T may be reduced, and a range of a certain region of an output current of the transistor T may be increased. Hence, luminance deviation between the pixels according to the output current of the transistor T may be reduced, thereby increasing quality of the images of the display device1000.

In an embodiment, the conductive pattern layer111and the drain region135of the transistor T may be electrically connected to each other through the connecting members161and162patterned by using the oxide pattern layer164and including the semiconductor material, and the driving voltage line172may be electrically connected to the source region133of the transistor T. Therefore, other conductive layers may not be disposed between the connecting members161and162and the second insulating layer169.

Additional conductive layer may not be disposed between the second insulating layer169and the third insulating layer180on the pixel PX. However, embodiments are not limited thereto.

According to an embodiment, the concentration may be reduced by controlling the carrier concentration of the channel region of the transistor of the display device1000. As the step of forming an additional conductive pattern layer for the connecting members161and162is omitted, the number of masks used in the process for manufacturing a display device1000may not be increased, thereby reducing a manufacturing cost and a manufacturing time of the display device1000. Further, in the process for forming the connecting members161and162including the same material as the oxide pattern layer164, the oxygen depletion area may be increased and the hydrogen may be supplied to make the connecting members161and162conductive so that contact resistance for an electrical connection between the conductive pattern layer111and the drain region135and between the driving voltage line172and the source region133may be reduced and deterioration of element characteristics of the transistor T and the light emitting diode ED may be reduced.

A structure of a pixel of a display device according to an embodiment will now be described with reference toFIG.15together with the above-described drawings.

FIG.15shows a schematic diagram of an equivalent circuit of a pixel of a display device according to an embodiment.

A pixel PX of the display device1000may include a pixel circuit including transistors T1, T2, and T3and a capacitor Cst, and at least one light emitting diode ED that is a light-emitting device connected to the pixel circuit. In an embodiment, an example in which one pixel PX includes a light emitting diode ED will be described.

The transistors T1, T2, and T3may include a first transistor T1, a second transistor T2, and a third transistor T3.

A gate electrode G1of the first transistor T1may be connected to a first end portion of the capacitor Cst, a source electrode S1of the first transistor T1may be connected to a driving voltage line for transmitting a driving voltage ELVDD, and a drain electrode D1of the first transistor T1may be connected to an anode of the light emitting diode ED and a second end portion of the capacitor Cst. The first transistor T1may receive a data voltage DAT according to a switching operation of the second transistor T2, and may supply a driving current to the light emitting diode ED according to the voltage stored in the capacitor Cst.

The gate electrode G1of the first transistor T1may face the conductive pattern layer111, and the conductive pattern layer111may be electrically connected to the drain electrode D1of the first transistor T1and the anode of the light emitting diode ED.

A gate electrode G2of the second transistor T2may be connected to a first scan line for transmitting a first scan signal SC, a source electrode S2of the second transistor T2may be connected to a data line171for transmitting a data voltage DAT or a reference voltage, and a drain electrode D2of the second transistor T2may be connected to the first end portion of the capacitor Cst and the gate electrode G1of the first transistor T1. The second transistor T2may be turned on by the first scan signal SC and may transmit the reference voltage or the data voltage DAT to the gate electrode G1of the first transistor T1and the first end portion of the capacitor Cst.

A gate electrode G3of the third transistor T3may be connected to the second scan line for transmitting a second scan signal SS, a source electrode S3of the third transistor T3may be connected to the second end portion of the capacitor Cst, the drain electrode D1of the first transistor T1, and the anode of the light emitting diode ED, and the drain electrode D3of the third transistor T3may be connected to an initialization voltage line for transmitting an initialization voltage INIT. The third transistor T3may be turned on by the second scan signal SS to transmit the initialization voltage INIT to the anode of the light emitting diode ED and the second end portion of the capacitor Cst and may initialize the voltage at the anode of the light emitting diode ED.

The first end portion of the capacitor Cst may be connected to the gate electrode G1of the first transistor T1, and the second end may be connected to the source electrode S3of the third transistor T3and the anode of the light emitting diode ED. A cathode of the light emitting diode ED may be connected to a common voltage line for transmitting a common voltage ELVSS.

The light emitting diode ED may emit light with luminance according to the driving current generated by the first transistor T1.

The first transistor T1may have a structure of the above-described transistor T.

The structure of the pixel PX included by the display device1000according to an embodiment is not limited to the circuit diagram shown inFIG.1, and various types of pixel structures are allowable according to the type of the display device1000.