Semiconductor memory having a barrier transistor between a bit line and a sensing amplifier

In this invention, in a sensing circuit of a dynamic memory, barrier transistors are provided between the bit lines and the sensing amplifier. A circuit is provided that, on sensing and on data transfer, changes the gate potential of the barrier transistors so that during the sensing operation the barrier transistors are temporarily turned OFF, so that sensing can be carried out with high sensitivity, as the sensing system is not affected by the parasitic capacitance of the bit lines, while, on data transfer to the input/output lines, the gate potential of the barrier transistors is raised to a level greater than a value reached by adding the threshold value of the MOS transistors to the power source voltage, so that the conductance of the barrier transistors is increased, thereby speeding up the presensing of the input/output lines in the sensing circuit.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention is concerned with a dynamic semiconductor memory, and in 
particular relates to the use of dynamic RAM (Random Access Memory) 
sensing circuits. 
2. Description of the Prior Art 
In conventional dynamic memory (RAM) sensing circuits, as shown in FIG. 1, 
an arrangement is used in which barrier transistors are provided between 
the bit lines and sensing amplifiers. In the Figure, BL and BL are paired 
bit lines which are respectively connected to flip-flop nodes FF and FF of 
sensing amplifiers through barrier transistors 1 and 2. I/O and I/O are 
paired input/output lines constituting the data transfer nodes to the data 
input buffer and data output buffer, .phi..sub.S1 and .phi..sub.S2 are 
clocks for pre-sensing and main sensing respectively, .phi..sub.C is the 
column select line signal and .phi..sub.p is a pre-charged signal for a 
node .phi..sub.SA. FIG. 2 shows a prior art example of a circuit for 
generating a gate control signal .phi..sub.T of barrier transistors 1 and 
2. FIGS. 3(a), (b), (c) and (d) are charts showing the timing of the 
control clocks and the variation with time of the voltages at the various 
nodes. At first, as shown in FIG. 3(a) and FIG. 3(c), when the precharged 
signal .phi..sub.p is applied to the transistor 9, the node .phi..sub.SA 
is coupled to V.sub.DD potential through the transistor 9, so that node 
.phi..sub.SA is charged up to V.sub.DD -V.sub.TH. 
As shown in FIG. 3(b), before the sensing operation is commenced, signal 
.phi..sub.T is at a level greater than "V.sub.DD +V.sub.TH ", representing 
MOS transistor threshold voltage V.sub.TH added to power source voltage 
V.sub.DD, allowing read data on bit lines BL, BL to be transferred to 
respective nodes FF, FF. As shown in FIG. 3(c) and (d), bit line BL and 
node FF are then at potential V.sub.DD and bit line BL and node FF are a 
little lower than potential V.sub.DD. When the sensing operation is 
performed, as shown in FIG. 1 and FIG. 3(a), transistors 5 and 6 are 
turned ON by the rising edges of .phi..sub.S1 and .phi..sub.S2 and the 
potential of node .phi..sub.SA is thereby lowered. Thanks to the coupling 
with capacitance 11 shown in FIG. 2, potential .phi..sub.T is also 
temporarily lowered to a level below the pre-charge potential of the bit 
line, e.g. potential V.sub.DD, as shown in FIG. 3(b). This results in 
transistors 1 and 2 shown in FIG. 1 being turned OFF, so the effect of the 
parasitic capacitance of the bit lines BL and BL can be excluded from the 
sensing system, enabling the sensing to be of high sensitivity. 
Subsequently, node N1 assumes a potential of greater than "V.sub.DD 
+V.sub.TH " because of the coupling with capacitance 12 shown in FIG. 2, 
thereby turning transistor 10 ON. This results in signal .phi..sub.T 
recovering to source voltage V.sub.DD, and the lower bit line BL being 
connected to earth potential V.sub.SS through transistors 2, 4, 5 and 6. 
Next, when data is transferred to the input/output lines, as shown in FIG. 
1 and FIG. 3(a), the selected signal .phi..sub.C assumes a potential 
greater than "V.sub.DD +V.sub.TH ", and transistors 7 and 8 are turned ON, 
so that the I/O lines, which have already been charged up to potential 
V.sub.DD, and the bit lines, are put into a conductive condition. 
Input/output line I/O connected to the higher bit line BL, which is at 
V.sub.DD level, maintains V.sub.DD level, while the level of input/output 
line I/O connected to the lower bit line BL falls, since the charge 
holding in the input/output lines is redistributed between the parasitic 
capacitance of the input/output lines and the parasitic capacitance of the 
bit lines. To further increase the potential difference which this charge 
redistribution produces between the input/output lines, the input/output 
lines are presensed by connecting the lower input/output line I/O to 
V.sub.SS potential through transistors 8, 2, 4, 5 and 6 using the sensing 
circuit. 
However, in the conventional circuit, as shown in FIG. 3(b), the signal 
.phi..sub.T at this point is V.sub.DD level, so the conductance of 
transistor 2 is low, so that input/output line I/O discharges only slowly. 
Since the input/output line presensing operation in this sensing circuit 
occurs at a slow rate the timing of the rise of the signal .phi..sub.I 
that starts the main input/output line sensing operation in this 
input/output line sensing circuit has to be delayed, as shown in FIG. 
3(a). Thus data can not be transferred at high speed. 
SUMMARY OF THE INVENTION 
In dynamic memory sensing circuits it is required not only to obtain high 
sensitivity of the sensing operation to increase the operating margin, but 
also to speed up data transfer to the data transfer nodes in order to 
provide high-speed access. In a memory provided with barrier transistors 
between sensing amplifiers and bit lines used with the purpose of 
improving the sensitivity of the sensing operation, the object of this 
invention is to make possible an improvement in the speed of data 
transfer, which has to be sacrificed in the prior art. 
In a dynamic memory sensing circuit provided with barrier transistors 
between the bit lines and sensing amplifiers, this invention provides a 
circuit that makes the gate potentials of the barrier transistors change 
with the sensing time and data transfer time, so that, during the sensing 
operation, the barrier transistors are temporarily turned OFF, thus 
ensuring that the sensing system is not affected by the parasitic 
capacitance of the bit lines, and the sensing sensitivity is therefore 
high, while, on data transfer to the input/output lines, it raises the 
gate potential of the barrier transistor to a value greater than the 
threshold voltage of the MOS transistor added to the power source voltage, 
thus increasing the conductance of the barrier transistors so that 
presensing of the input/output lines by the sensing circuit can be speeded 
up.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Embodiments of this invention are described below with reference to the 
drawings. The sensing circuit itself in these embodiments is the same as 
in FIG. 1. An example of a barrier transistor gate potential generating 
circuit is shown in FIG. 4. As shown in these Figures, this circuit 
comprises a MOS transistor 21, MOS transistor 22 and MOS transistor 23. 
MOS transistor 21 connects a power source terminal 25 and a node 
.phi..sub.T constituting the gate input of transistors 1 and 2. MOS 
transistor 22 connects a node N2 and a node .phi..sub.SA. Node N2 is 
connected by means of a capacitance 24 to node .phi..sub.T, and node 
.phi..sub.SA is common to transistors 3 and 4 forming the flip-flop of the 
sensing amplifiers. MOS transistor 23 connects node N2 and power source 
terminal 25. Circuits for ensuring that the voltages of these nodes change 
as shown in FIG. 5(e) is connected to nodes .circle.1 , .circle.2 and 
.circle.3 . 
Before the operation of the sensing circuit is commenced, as shown in FIG. 
5(b), gate control signal .phi..sub.T of the barrier transistors is at a 
potential greater than "V.sub.DD +V.sub.TH ", and node .phi..sub.SA is at 
level "V.sub.DD -V.sub.TH ". As shown in FIG. 4 and FIG. 5(e), node 
.circle.1 is at level V.sub.DD and transistor 21 is OFF. Node .circle.2 
is also at level V.sub.DD, node N2 is charged to a potential greater than 
"V.sub.DD +V.sub.TH ", and transistor 22 is in the cut-off state. Node N2 
is then charged up to a potential greater than "V.sub.DD +V.sub.TH " as 
follows. Specifically, transistor 23 is turned ON so that node N2 is 
charged up to "V.sub.DD -V.sub.TH ". After this, as bit lines BL and BL 
are recharged, node .phi..sub.T is raised to a potential greater than 
"V.sub.DD +V.sub.TH " by the coupling capacitances which are parasitic on 
transistors 1 and 2. Node N2 is then raised to a potential greater than 
"V.sub.DD +V.sub.TH " by a capacitance 24 shown in FIG. 4. As shown in 
FIG. 5(e), node .circle.3 is at level V.sub.SS, so transistor 23 is OFF. 
During sensing operation, as node .phi..sub.SA falls in potential as shown 
in FIG. 5(c), transistor 22 shown in FIG. 4 is turned ON causing the 
potential of node N2 to drop too. Due to the coupling with capacitance 24, 
potential .phi..sub.T also temporarily drops, as shown in FIG. 5(b), to a 
level below the precharging potential of the bit lines. And node 
.circle.1 is made to assume a potential greater than "V.sub.DD +V.sub.TH 
", signal .phi..sub.T therefore recovers through transistor 21 to level 
V.sub.DD. As shown in FIG. 1, transistors 1 and 2 are turned OFF by the 
drop in the potential of .phi..sub.T, so sensing can be performed with 
great sensitivity. At the time-point when the sensing operation is 
completed and the potential of .phi..sub.SA has fallen to level V.sub.SS, 
as shown in FIG. 5(e), node .circle.2 is made to assume potential 
V.sub.SS, thus turning transistor 22 OFF. 
On data transfer to the input/output lines, as shown in FIGS. 5(a) and 
5(e), the potential of node .circle.1 is made to fall, with the timing 
of the rising edge of signal .phi..sub.C, from a level greater than 
"V.sub.DD +V.sub.TH " to level V.sub.DD thereby turning OFF transistor 21 
and then raising the potential of node .circle.3 , so that node N2 is 
again charged through transistor 23. As the potential of node N2 rises as 
shown in FIG. 5(b), due to the coupling with capacitance 24, signal 
.phi..sub.T rises to a potential greater than "V.sub.DD +V.sub.TH ". 
FIG. 6 shows an example in which the source of transistor 22 of FIG. 4 is 
connected to earth potential V.sub.SS instead of node .phi..sub.SA. The 
gate potential .circle.2 ' of transistor 22, which, before sensing, was 
at level V.sub.SS as shown in FIG. 5(e), rises during sensing operation to 
level V.sub.DD, and after sensing is completed falls again to level 
V.sub.SS. 
As can be seen by inspection of the waveforms of the conventional system of 
FIG. 3 and the embodiment of this invention shown in FIG. 5. Whereas, with 
the conventional system, the potential of signal .phi..sub.T on data 
transfer to the input/output lines is V.sub.DD, with this embodiment of 
the invention, it is at least at level "V.sub.DD +V.sub.TH ". Thus the 
conductance of the barrier transistors is large and voltage drop of the 
lower I/O line occurs quickly. That is, the rise in .phi..sub.I of FIG. 
5(a) and the fall of nodes FF, I/O, and BL of FIG. 5(c) and (d) occurs 
quickly. Consequently, by using the circuit of this invention, the 
necessary increase in speed of data transfer can be attained thanks to a 
speeding up of the operation of pre-sensing the I/O lines in the sensing 
circuit. In contrast, with the conventional system, speeding up of the 
operation of pre-sensing the I/O lines in the sensing circuit was 
sacrificed. 
As described above, according to this invention, in a dynamic memory 
wherein barrier transistors are provided between the sensing amplifier and 
bit lines used in order to purpose at increased sensitivity of the sensing 
operation, increased speed of data transfer (which was sacrificed in the 
prior art) can be obtained.