Power-on reset pulse generator

A circuit for generating a pulse is disclosed for resetting certain multi-state elements of an electronic system after the power supply of the system has been activated and said elements have settled. The circuit is composed of an R-C network and a latch. The latch is activated by the power supply and it sets its output to a preselected state. The latch switches to a second state after a capacitor of the RC network is charged to a preselected level. The output of the latch is used to derive the reset signal. The reset signal may be delayed by a delay circuit and amplified and buffered or conditioned by an amplifying stage. The circuit is comprised of elements which may be produced by IC techniques such as CMOS so that it may be implemented on a single IC chip.

BACKGROUND OF THE INVENTION 
1. Field of Invention 
This invention pertains to a circuit for generating a reset pulse after a 
power supply for an electronic system has been energized, and more 
particularly to a miniaturized circuit which could be incorporated into a 
large-scale integration (LSI)-type chip. 
2. Description of the Prior Art 
In many electronic circuits, certain components are used which can have two 
or more stable states. For example, digital circuits often comprise 
flip-flops, latches and counters. These types of components must be set to 
an initial or reset state prior to their normal operation every time the 
circuit is energized. Typically one or more circuits are energized from a 
single power supply. However as a power supply is activated, its output 
rises in an unpredictable manner with frequent fluctuations prior to 
reaching a final nominal steady state value. This is especially the case 
with switched power supplies in which oscillators and SCR's are used to 
convert a (usually high) D.C. or A.C. voltage and a (usually low) D.C. 
voltage. Because of this initial variation in the power supply output it 
is very difficult to insure that the above-mentioned multistate components 
are in a particular state after the power supply output has stabilized. 
Therefore an initializing, or a reset pulse is needed to set said 
components to the desired states. Normally the circuit used to generate 
this reset pulse is activated only once, for each power-up operation, and 
is left inactivated at all other times. It has been found that the reset 
pulse must have a duration, which depending on different power supplies 
ranges from microseconds to seconds. 
In order to conserve space, and power and increase the operational speed of 
the electronic circuits, these circuits have been miniaturized by using 
well-known I.C. techniques such as CMOS. However reset pulse-generating 
circuits traditionally comprised passive elements such as resistors and 
capacitors which cannot be implemented on CMOS IC and therefore must be 
mounted externally. 
OBJECTIVES AND SUMMARY OF THE INVENTION 
In view of the above, an objective of this invention is to provide a reset 
pulse generating circuit which can be produced by usual techniques as part 
of a CMOS IC. 
A further objective is to provide a circuit which can be incorporated in an 
IC chip together with other elements of an electronic system. 
A further objective is to provide a circuit which can be modified to 
produce a pulse ranging from microseconds to seconds in duration. Other 
objectives and advantages of the invention shall become apparent in the 
following description. 
As previously mentioned, the purpose of the reset pulse is to set certain 
circuit elements to predetermined states after the output of the power 
supply has settled. The duration of the pulse depends on the rise time of 
the power supply output. If this rise is very slow or it fluctuates so 
that it reaches the activating level of some circuit elements, such as a 
differential flip-flop, after a relatively long rise time, the reset pulse 
must also be long in order to insure that it has been applied to the 
circuit elements after their activation. In some cases the reset pulses 
must have a duration of a second or more. However, traditionally reset 
pulses have been derived from RC networks having appropriate time 
constants. In order to achieve the time constants necessary for the 
present application, the resistance and capacitance of the network must be 
in the order of megaohms and microfarads respectively. It is very 
difficult to obtain such elements on an integrated circuit (IC) chip. 
Therefore in this invention voltage-dependent elements such as FET's are 
used instead of the resistor. These elements have a high enough resistance 
so that the capacitor C may be reduced to the picofarad range. For very 
long time constants another non-linear element such as a diode is used to 
increase the resistance of the RC network. 
The circuit also includes a latching means which is activated at an early 
stage of the power supply output rise and reset by the RC network. 
The latching means is designed so that its output is either at first or at 
second value, thus eliminating the possibility of indeterminate states. It 
also provides amplification of the RC network output. Finally the latching 
means is also used as a memory means to insure that only one reset pulse 
is produced, every time the power supply is turned on and that 
fluctuations in the power supply output do not result in further reset 
pulses. 
The output of the latching means is fed to delay circuit. This circuit is 
provided to allow time for the preselected components to be activated and 
stabilized before the reset pulse is applied. 
The output of the delay circuit is amplified and buffered or conditioned by 
an amplifying circuit to produce a reset pulse with sharp, well-defined 
leading and trailing edges.

DETAILED DESCRIPTION OF THE INVENTION 
As shown in FIG. 1, the reset pulse generating circuit comprises four 
stages: an RC network 10, a latching stage 12, a delay stage 14 and an 
amplifier stage 16. Advantageously, the circuit comprises only MOSFET's 
and capacitors so that it can be formed on a single IC chip by using CMOS 
or other similar techniques. It is well known the MOSFET's can be made 
either as a P-MOS or as an N-MOS transistor. For the sake of clarity all 
the P and N-MOS FET's are identified in the figures by the letters P or N 
followed by a numeral. Furthermore certain FET's are preferably formed on 
the chip as complementary pairs and coupled to create an inverters. The 
respective P- and N-MOS FET's of each complementary pair have been 
assigned the same numeral. 
In the embodiment of FIG. 1, the RC network 10 comprises a capacitor 
C.sub.1 and two P-MOS transistors P.sub.1 and P.sub.2. The capacitor has a 
value of 4pF. The equivalent resistance of P.sub.1 and P.sub.2 is 
dependent on the voltage between the respective drains and sources of the 
transistors P.sub.1 and P.sub.2. Capacitor C.sub.1 and transistor P.sub.1 
and P.sub.2 are in series between positive bus 20, and ground bus 18 as 
shown. 
The two buses are connected to the output of a power supply (not shown) so 
that when the power supply is activated at time t=0 the voltage across 
them, V.sub.p rises from 0 to a final, nominal value V.sub.DD as shown on 
FIG. 2. 
As V.sub.p rises, transistors P.sub.1 and P.sub.2 start conducting and the 
voltage across the capacitor, and node A starts rising also. The voltage 
profiles at different nodes of the pulse generating circuit are also shown 
on FIG. 2. The voltage drops across P.sub.1 and P.sub.2 depend on the 
current and back bias of the transistors. If the transistors P.sub.1 and 
P.sub.2 are provided with a channel width-per-length of 6/20 and 6/70 
respectively then the voltage drops across them ranges from 1 to 3 volts. 
Therefore Va does not have any appreciable value until V.sub.p reaches at 
least 4 volts, independently of the rate of rise of V.sub.p. 
The latching stage 12 comprises three inverters, and an input transistor 
N.sub.3 used to couple this stage to the RC network 10. The inverters 
consists of two complementary transistors connected in series as shown. 
The inverters consisting of P.sub.4, N.sub.4 and P.sub.5, N.sub.5 
respectively are hooked up back-to-back to form a latch 22 with an input 
node B, and output node C. The transistors are formed with the following 
channel width-to-length ratios: P.sub.4 - 6/11, N.sub.4 - 12/5, P.sub.5 - 
6/11, and N.sub.5 - 6/20. This unsymmetrical arrangement is provided to 
insure that when the power supply is activated the latch output is 
initially low. Therefore, as shown in FIG. 2, at t=T.sub.2 the power 
supply output reaches a threshold value V.sub.p =V.sub.t which activates 
the latching stage, at which point V.sub.b goes high and V.sub.c is low. 
In order to make sure that the latch 22 powers-up to the above-defined 
state the input and output nodes B and C are also coupled respectively to 
the positive and ground buses 18 and 20 through capacitors C.sub.2 and 
C.sub.3 as shown. Preferably C.sub.2 has a value of 0.5 pF while C.sub.3 
=1pF. 
The latching stage also comprises a third inverter consisting of 
complementary transistors P.sub.6 and N.sub.6. This third inverter is used 
to invert the output of the latch. Preferably P.sub.6 and N.sub.6 should 
have a width-to-length ratio of 6/5. 
The delay stage is coupled to output node D of the third inverter, and it 
comprises a second RC network. The resistance of the network is provided 
by a transistor N.sub.7 with its source connected in series with a 
capacitor C.sub.4. The capacitor preferably has a value of 2pF while the 
transistor has a width-to-length channel ratio of 6/30. 
The voltage across the capacitor C.sub.4, i.e. the voltage V.sub.e at node 
E, is coupled to the amplifier stage 16. As shown in FIG. 1, the amplifier 
stage comprises two inverters having two complementary transistors, namely 
P.sub.8, N.sub.8 and P.sub.9, N.sub.9. The two inverters are connected in 
series, so that the output of the delay stage comprises the input of the 
first inverter (P.sub.8 /N.sub.8) and the output the first inverter (node 
F) comprises the input of the second inverter (P.sub.9 /N.sub.9). The 
output of the second inverter comprises the output of the whole pulse 
generating circuit. The width-to-length channel ratio of P.sub.8 and 
N.sub.8 is 6/5 and for P.sub.9 and N.sub.9, 24/5. 
The operation of the circuit is obvious from the above description. As 
shown in FIG. 2, the output of a power supply activated at t=0 stabilizes 
at t=T.sub.1. Sometimes before T.sub.1, at T.sub.2 said output reaches a 
value V.sub.t at which point the latching stage 12 is energized, node B 
goes high and node C stays low. The logic level of node C is inverted by 
inverter P.sub.6 /N.sub.6 so that node D also goes high. As soon as 
V.sub.d goes high, capacitor C.sub.4 starts charging through transistor 
N.sub.7. 
Initially inverter P.sub.8 /N.sub.8 has a high output at node F (V.sub.f) 
due to the low voltage across C.sub.4. When the voltage across C.sub.4 
(V.sub.e) reaches a threshold level V.sub.s (at t=T.sub.4) the output of 
inverter P.sub.8 /N.sub.8 (node F) goes low. This output is inverted by 
inverter P.sub.9 /N.sub.9 so that at t=T.sub.4 the output of the whole 
circuit goes high initializing the reset pulse. 
Meanwhile the capacitor C.sub.1 of RC network 10 has been charging up 
toward V.sub.DD. When its voltage V.sub.a reaches a level V.sub.t (at 
t=T.sub.3) transistor N.sub.3 turns ON pulling node B to ground. The latch 
22 immediately flips over so that its output V.sub.c goes high. 
Consequently the output V.sub.d of inverter P.sub.6 /N.sub.6 goes low and 
stays low for as long as the power supply is ON. 
When node D goes low transistor N.sub.7 is turned off and capacitor C.sub.4 
starts discharging through N.sub.8 as shown. When its voltage V.sub.e 
reaches V.sub.s (at t=T.sub.5) transistor N.sub.8 also turns off and the 
output of inverter P.sub.8 /N.sub.8 (node F) goes high. This change causes 
the output of inverter P.sub.9 /N.sub.9 to go low, terminating the reset 
pulse. 
As shown in FIG. 2, the reset pulse goes on after a period T.sub.D to allow 
all preselected circuit elements to settle. T.sub.D is determined by the 
rate of rise of V.sub.p and the time constant of the delay stage 14. The 
period T.sub.p of the reset pulse is determined essentially by the time 
constant of the RC network 10. 
The circuit shown in FIG. 1 is suitable for reset pulses in the range of 
1-10 microseconds. In order to increase the period of the pulse to 
miliseconds, another element with a much higher resistance can be used. 
One such element, as shown in FIG. 3, could be a zener diode Z which is 
connected in series with C.sub.1 in a reverse-biased position. In this 
embodiment the transistors P.sub.1 and P.sub.2 are used to provide a 
voltage drop as described above. The capacitor is charged up by the 
leakage current passing through the zener diode. Due to the non-linear 
characteristics of this device its effective resistance is much larger 
than the resistance of the two transistors. The effective time constant of 
the capacitor and zener diode is in the milisecond range. 
If a very long pulse of one second or more is required a reverse biased 
diode D may be used to charge the capacitor as shown in FIG. 4. The 
leakage current through this diode D is low enough to extend the reset 
period into minutes. Preferably diode D is made by forming a P-well and 
N-diffusion junction through readily available CMOS techniques. 
In certain applications a very precise control over the time constant of 
the RC network may be necessary. This may be accomplished, as shown in 
FIG. 5 by providing two transistor P.sub.1 and P.sub.2 in series, each 
transistor having its gate connected to clock siqnals C1.sub.1 and 
C1.sub.2 respectively, and its source to two switched capacitors C.sub.1 
and C.sub.1 '. 
The clock signals are enabled as soon as power reaches the threshold value 
V.sub.p =V.sub.T at t=T.sub.2 and will be reset by the reset pulse. 
C1.sub.1 and C1.sub.2 are non-overlapping and 180.degree. out of phase 
clocks. When C1.sub.1 is high, transistor P.sub.1 conducts and C.sub.1 is 
charged up to V.sub.p, This charge is then redistributed between C.sub.1 
and C.sub.1 ' during the cycle when C1.sub.2 is high. During a complete 
clock period, an amount of charge 
##EQU1## 
is deposited on the C.sub.1 ' capacitor. As more is accumulated on the 
capacitor, the voltage increases until it is high enough to flip the latch 
12. The time constant of this embodiment depends on the frequency of 
clocks C1.sub.1 and C1.sub.2 and the ratio of C.sub.1 and C.sub.1 ' and is 
essentially independent of V.sub.p. 
As mentioned above, in order to insure that the latch 22 initially has a 
high output, its component transistors are unsymmetrical, and additional 
capacitors C.sub.2 and C.sub.3 have been added to corresponding nodes B 
and C. 
A further degree of security is provided by the embodiment of FIG. 6 in 
which latch 22 comprises two NAND gates G.sub.1 and G.sub.2. The input of 
NAND gate G.sub.1 comprises V.sub.p and the output of gate G.sub.2, and 
the input of NAND gate G.sub.2 consists of the output of G.sub.1 and node 
B. Thus in effect gates G.sub.1 and G.sub.2 from a flip-flop. The output 
of the flip-flop (node C) is initially coupled to ground by capacitor 
C.sub.3 thus insuring that initially node C is at it low state. Of course 
this embodiment requires more transistors (for implementing gates G.sub.1 
and G.sub.2) than the embodiment of FIG. 1. 
Obviously numerous additions and modifications could be made to the 
invention without departing from its scope as defined in the appended 
claims.