Method and apparatus for abutting p-cell layout based on position and orientation

An electronic design automation (EDA) tool generates first and second instances, which are different in at least one aspect, of a cell representing a device, allowing a user to initiate an abutment of the first and second instances in a layout canvas, reads a position and orientation of each of the first and second instances to be abutted from the layout canvas, evaluates the respective positions and orientations of the first and second instances, altering a component of one of the first and second instances based on the evaluation, and then automatically abuts the first and second instances following the alteration of the component of the one of the first and second instances.

BACKGROUND OF THE INVENTION

The present invention is directed to computer aided circuit design and, more particularly, to a method and system for automatically abutting p-cell layouts based on position and orientation of abutting instances.

In circuit design, a parameterized cell (p-cell) is a cell that is automatically generated by an electronic design automation (EDA) tool based on a value or values of governing parameters. That is, a p-cell represents a part or a component of a circuit that is dependent on one or more parameters, such as transistors or the like.

Analog and memory circuit designs typically require abutting p-cell instances having different dimensions. These designs cause design rule check (DRC) errors due to the limitations of the abutment functionality in current EDA tools, and there currently is no control at the p-cell code level to resolve such issues. The solution offered by current EDA tools for auto-abutment is placement of a stopping gate at 40 nm and lower technologies. In one conventional automatic abutment procedure, the EDA tool considers the overlap of pins in the first and second instances, and automatically adjusts the pin arrangement in the abutted configuration to remove redundant pins. However, this tool does not take into account the position and orientations of the respective instances, and therefore does not alter other necessary parameters to avoid the types of DRC errors described above.

It is therefore desirable to provide a method for an EDA tool to make alterations to components of abutting p-cells that avoid the types of DRC errors caused by the automatic abutment of two differing p-cells.

DETAILED DESCRIPTION

In one embodiment, the present invention provides a method of computer-aided design of an integrated circuit that includes generating, using an EDA tool, a first instance and a second instance of a cell representing a device, where the first and second instances are different in at least one aspect. The method further includes allowing a user, using the EDA tool, to initiate an abutment of the first and second instances in a layout canvas, reading a position and orientation of each of the first and second instances to be abutted from the layout canvas, evaluating the respective positions and orientations of the first and second instances, altering at least one component of at least one of the first and second instances based on the evaluation, and automatically abutting the first and second instances following the alteration of the at least one component of the at least one of the first and second instances.

In another embodiment, the present invention comprises an EDA tool for computer-aided design of an integrated circuit (IC) and includes a memory, a display, an input, and a processor coupled to the memory, the display, and the input. The processor is configured to generate a first instance and a second instance of a cell representing a device, the first and second instances being different in at least one aspect, allow a user, via the input, to initiate an abutment of the first and second instances in a layout canvas shown on the display, read a position and orientation of each of the first and second instances to be abutted from the layout canvas, evaluate the respective positions and orientations of the first and second instances, alter at least one component of at least one of the first and second instances based on the evaluation, and automatically abut the first and second instances following the alteration of the at least one component of the at least one of the first and second instances.

In another embodiment, the present invention comprises a non-transitory computer readable storage medium comprising computer readable instructions for designing an integrated circuit by executing, by an EDA tool, the steps of generating a first instance and a second instance of a parameterized cell representing a device, the first and second instances being different in at least one aspect, allowing a user to initiate an abutment of the first and second instances in a layout canvas, reading a position and orientation of each of the first and second instances to be abutted from the layout canvas, evaluating the respective positions and orientations of the first and second instances, altering at least one component of at least one of the first and second instances based on the evaluation, and automatically abutting the first and second instances following the alteration of the at least one component of the at least one of the first and second instances.

Referring now to the drawings, wherein the same reference numerals are used to designate the same components throughout the several figures, there are shown inFIG. 1relevant components of an electronic design automation (EDA) tool10for use in designing an integrated circuit (IC) in accordance with a first embodiment of the present invention. The EDA tool10is configured to execute the necessary software operations for circuit design. The EDA tool10can be, for example, one or more dedicated workstations, a desktop computer, laptop computer, tablet computer, or the like.

The EDA tool10includes one or more processors12(which may be collectively referred to as a processor). The processor12may be a central microprocessor, microcontroller, or the like. The processor12is coupled to a memory14, which may be in the form of a volatile memory (e.g., random access memory (RAM) or the like) or non-volatile memory (e.g., flash, read-only memory (ROM), or the like), or combinations thereof. In one embodiment, the memory14may be a mass storage non-volatile memory and the processor12may include an internal RAM (not shown). The memory14preferably stores an operating system16, as well as application programs, such as various forms of design software18that can be executed by the processor12.

The EDA tool10further includes a display20and an input22. The display20may be a screen, monitor, or the like using liquid crystal display (LCD), light emitting diode (LED), cathode ray tube (CRT), digital light processing (DLP) technology or the like. The input22may be one or more of a touchscreen, mouse, keyboard, or the like.

FIG. 2is a flow chart illustrating a method or program100for designing an integrated circuit, which may be executed by the EDA tool10inFIG. 1. Referring toFIGS. 2 and 3A, at the start102of the program100, the EDA tool10will have generated, typically at the behest of a user, a first instance30and a second instance40of a cell representing a device. The cell is preferably a parameterized cell (p-cell), although other forms may be used as well. The first and second instances30,40may be shown on the display20to the user in the layout canvas in different locations. It should be noted that more than two instances30,40may be generated and displayed to the user, depending on the requirements of the circuit being designed. The first and second instances30,40preferably also are different in at least one aspect, such as length, width, number of pins, orientation in the layout canvas, or the like.

In the example ofFIG. 3A, the first and second instances30,40each represent a field effect transistor (FET) with a single gate finger32,42. However, the second instance40is much shorter in the Y-direction than the first instance30. In a conventional EDA tool, abutment of the first and second instances30,40would result in a gate polysilicon end cap44of the second instance40that is much shorter in the Y-direction than the first instance30. This would result in a DRC error, which can be avoided using embodiments of the present invention, as set forth more fully below.

It should be noted that more than two instances30,40may be generated and displayed to the user, depending on the requirements of the circuit being designed. Such additional instances (not shown) may be identical to or different from one or more of the first and second instances30,40.

At step104, the user is permitted, via the input22, to initiate an abutment of the first and second instances30,40of the cell. The initiation may be made by dragging one of the instances30,40on the display20to a position adjacent the other of the instances30,40, typing or selecting a command using the input22, or the like. This action triggers the automatic abutment procedure106of the program. However, rather than proceeding to immediately abut the first and second instances30,40in the conventional fashion, additional processing is performed.

Specifically, at step108, the EDA tool10reads the position and orientation of each of the first and second instances30,40to be abutted from the layout canvas. For example, the EDA tool10may read dimensions of components of the first and second instances30,40in the X- and Y-directions, rotation of the first and second instances30,40, and the like.

With this position, dimension, and orientation information, the EDA tool10at step110evaluates the respective positions and orientations of the first and second instances30,40to determine whether any alterations are necessary to maintain the integrity of the circuit. Such alterations may be determined based on known circuit design dimensions applicable to adjacent components, on known potential DRC errors, or the like. At step112, any necessary component alterations are returned to the automatic abutment program, which at step114performs the necessary alterations and automatically abuts the altered first and second instances30,40. It should be noted that if no alterations are necessary, the first and second instances30,40may be abutted in the conventional manner.

In the example ofFIG. 3A, the EDA tool10will determine, based on the positions and orientations of the first and second instances30,40, that the gate polysilicon end cap44must be extended in the positive Y-direction in order to properly abut the first and second instances30,40. The elongated gate polysilicon end cap44is then located with respect to the first instance30at a location based on a position of the remainder of the second instance40. Thus, what is shown inFIG. 3Ais the result of the method ofFIG. 2altering the length in the Y-direction of the gate polysilicon end cap44for the second instance40to abut the first instance30at a lower portion thereof.

FIG. 3Bshows a similar result where the second instance40is moved to abut the first instance30at a middle portion thereof. In that case, the EDA tool10may determine and execute an alteration of the gate polysilicon end cap44to extend in the positive and negative Y-direction.FIG. 3Cshows another similar result where the second instance40is moved to abut the first instance30at a top portion thereof, requiring extension of the gate polysilicon end cap44in the negative Y-direction.

While not shown, similar results would apply if the first and second instances30,40were both rotated by about 90° such that the gate polysilicon end cap44extended in the X-direction. Alterations in the X-direction would be performed as a result of the evaluation of the respective positions and orientations of the first and second instances30,40.

FIG. 4is a slight variation on the configuration shown inFIG. 3Bin that the first and second instances30,40represent FETs each having multiple gate fingers32,42. However, the result is similar to that ofFIG. 3Bin that the second instance40abuts the first instance30at a middle portion thereof, and the gate polysilicon end cap44is altered to extend in the positive and negative Y-directions to compensate for the abutment of the dissimilar first and second instances30,40.

FIG. 5shows a different exemplary arrangement of first and second instances30,40that are automatically abutted. Like the arrangements inFIGS. 3A-3Cand4, the second instance40differs from the first instance30by length in the Y-direction. Each of the first and second instances30,40represents a FET having single gate fingers32,42arranged on top and bottom sides thereof. A drain metal strip36/46is positioned between the first and second instances30,40, while source metal strips38,48are arranged on sides of the first and second instances30,40opposite to the drain metal strip36/46.

In traditional automatic abutment, the material of the gate finger42atop the second instance40would be extended to contact the drain metal strip36/46, resulting in a deficient circuit and a DRC error. Using the method described herein, the EDA tool10uses the position and orientation of the first and second instances30,40to determine that the gate finger42atop the second instance40should be reduced in the X-direction to avoid contact with the drain metal strip36/46.