Imaging device and electronic device

An imaging device capable of obtaining high-quality imaging data is provided. The imaging device includes a first circuit, a second circuit and a third circuit. The first circuit includes a photoelectric conversion element, a plurality of transistors including an amplifier transistor, and a plurality of capacitors. The second circuit includes a transistor. The third circuit includes a resistor and a transistor for controlling a current flowing in the resistor. The output signal of the imaging device is determined in accordance with the current flowing in the resistor. Variations in electrical characteristics of the amplifier transistor included in the first circuit can be compensated.

TECHNICAL FIELD

One embodiment of the present invention relates to an imaging device.

In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are embodiments of semiconductor devices. In some cases, a storage device, a display device, an imaging device, or an electronic device includes a semiconductor device.

BACKGROUND ART

As a semiconductor device in which pixels each provided with a photosensor are arranged in a matrix, a complementary metal oxide semiconductor (CMOS) image sensor is known. CMOS image sensors are provided in many portable devices such as digital cameras or cellular phones as imaging elements.

Silicon is widely known as a semiconductor material applicable to a transistor generally included in a CMOS image sensor or the like. As another material, an oxide semiconductor has attracted attention.

For example, Patent Document 1 discloses that a transistor including an oxide semiconductor and having extremely low off-state current is used in part of a pixel circuit and a transistor including a silicon semiconductor with which a CMOS circuit can be formed is used in a peripheral circuit, so that an imaging device with high speed operation and low power consumption can be manufactured.

REFERENCE

Patent Document

Patent Document 1: Japanese Published Patent Application No. 2011-119711

DISCLOSURE OF INVENTION

A CMOS image sensor includes an amplifier transistor for outputting data in each pixel. In order to obtain high-quality imaging data, electrical characteristics of the transistors in all the pixels are preferably uninform. However, as miniaturization progresses, the degree of difficulty of a transistor manufacturing process increases, and it is difficult to reduce variation in electrical characteristics.

Output data can be compensated by retaining data for compensating variation in electrical characteristics in a capacitor or the like. However, total imaging time becomes long if data is written to a capacitor by each imaging. In addition, the increase in power consumption becomes a problem.

Thus, an object of one embodiment of the present invention is to provide an imaging device capable of obtaining high-quality imaging data. Another object of one embodiment of the present invention is to provide an imaging device capable of compensating variation in electrical characteristics of an amplifier transistor included in a pixel circuit. Another object of one embodiment of the present invention is to provide a low-power imaging device. Another object of one embodiment of the present invention is to provide an imaging device that is suitable for high-speed operation. Another object of one embodiment of the present invention is to provide an imaging device with high sensitivity. Another object of one embodiment of the present invention is to provide an imaging device with a wide dynamic range. Another object of one embodiment of the present invention is to provide an imaging device with high resolution. Another object of one embodiment of the present invention is to provide an imaging device formed at low cost. Another object of one embodiment of the present invention is to provide an imaging device with high reliability. Another object of one embodiment of the present invention is to provide a novel imaging device or the like. Another object of one embodiment of the present invention is to provide a novel semiconductor device or the like.

The description of these objects does not disturb the existence of other objects. In one embodiment of the present invention, there is no need to achieve all the objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

One embodiment of the present invention relates to an imaging device capable of compensating variation in electrical characteristics of an amplifier transistor included in a pixel circuit.

One embodiment of the present invention is an imaging device that includes a first circuit and a second circuit. The first circuit includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and a third capacitor. The second circuit includes a seventh transistor. One terminal of the photoelectric conversion element is electrically connected to one of a source and a drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. The other of the source and the drain of the first transistor is electrically connected to one terminal of the first capacitor. One of a source and a drain of the third transistor is electrically connected to the other terminal of the first capacitor. The other terminal of the first capacitor is electrically connected to one terminal of the second capacitor. One of a source and a drain of the fourth transistor is electrically connected to the other terminal of the second capacitor. The other of the source and the drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor. One terminal of the third capacitor is electrically connected to the other terminal of the second capacitor. The other terminal of the third capacitor is electrically connected to the other of the source and the drain of the fifth transistor. A gate of the fifth transistor is electrically connected to one terminal of the third capacitor. One of a source and a drain of the sixth transistor is electrically connected to the other of the source and the drain of the fifth transistor. The other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor.

The above imaging device may include a third circuit. The third circuit may include an eighth transistor and a resistor. One of a source and a drain of the eighth transistor may be electrically connected to the other of the source and the drain of the sixth transistor. The other of the source and the drain of the eighth transistor may be electrically connected to one terminal of the resistor.

The second circuit may further include a ninth transistor. One of a source and a drain of the ninth transistor may be electrically connected to the other of the source and the drain of the seventh transistor. A gate of the ninth transistor may be electrically connected to a gate of the seventh transistor. The gate of the ninth transistor may be electrically connected to the other of the source and the drain of the ninth transistor.

The other of the source and the drain of the third transistor may be electrically connected to the other terminal of the photoelectric conversion element.

The first circuit may further include a fourth capacitor. One terminal of the fourth capacitor may be electrically connected to one of the source and the drain of the third transistor. The other terminal of the fourth capacitor may be electrically connected to the other of the source and the drain of the fourth transistor.

Each of the first to ninth transistors preferably includes an oxide semiconductor in an active layer, and the oxide semiconductor preferably includes In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

According to one embodiment of the present invention, an imaging device capable of obtaining high-quality imaging data can be provided. An imaging device capable of compensating variation in electrical characteristics of an amplifier transistor included in a pixel circuit can be provided. A low-power imaging device can be provided. An imaging device that is suitable for high-speed operation can be provided. An imaging device with high sensitivity can be provided. An imaging device with a wide dynamic range can be provided. An imaging device with high resolution can be provided. An imaging device formed at low cost can be provided. An imaging device with high reliability can be provided. A novel imaging device or the like can be provided. A novel semiconductor device or the like can be provided.

The description of these effects does not disturb the existence of other effects. In one embodiment of the present invention, there is no need to obtain all the effects. Other effects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments will be described in detail with reference to the drawings. Note that the present invention is not limited to the following description. It will be readily appreciated by those skilled in the art that modes and details of the present invention can be modified in various ways without departing from the spirit and scope of the present invention. The present invention therefore should not be construed as being limited to the following description of the embodiments. In structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and the description thereof is not repeated in some cases. The same components are denoted by different hatching patterns in different drawings, or the hatching patterns are omitted in some cases.

For example, in this specification and the like, an explicit description “X and Y are connected” means that X and Y are electrically connected, X and Y are functionally connected, and X and Y are directly connected. Accordingly, without being limited to a predetermined connection relationship, for example, a connection relationship shown in drawings or texts, another connection relationship is included in the drawings or the texts.

Here, each of X and Y denotes an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

Examples of the case where X and Y are directly connected include the case where an element that enables electrical connection between X and Y (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display element, a light-emitting element, or a load) is not connected between X and Y, and the case where X and Y are connected without the element that enables electrical connection between X and Y provided therebetween.

Note that in this specification and the like, an explicit description “X and Y are electrically connected” means that X and Y are electrically connected (i.e., the case where X and Y are connected with another element or another circuit provided therebetween), X and Y are functionally connected (i.e., the case where X and Y are functionally connected with another circuit provided therebetween), and X and Y are directly connected (i.e., the case where X and Y are connected without another element or another circuit provided therebetween). That is, in this specification and the like, the explicit description “X and Y are electrically connected” is the same as the explicit description “X and Y are connected.”

For example, the case where a source (or a first terminal or the like) of a transistor is electrically connected to X through (or not through) Z1and a drain (or a second terminal or the like) of the transistor is electrically connected to Y through (or not through) Z2, or the case where a source (or a first terminal or the like) of a transistor is directly connected to part of Z1and another part of Z1is directly connected to X while a drain (or a second terminal or the like) of the transistor is directly connected to part of Z2and another part of Z2is directly connected to Y, can be expressed by using any of the following expressions.

Other examples of the expressions include “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least a first connection path, the first connection path does not include a second connection path, the second connection path is a path between the source (or the first terminal or the like) of the transistor and a drain (or a second terminal or the like) of the transistor, Z1is on the first connection path, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through at least a third connection path, the third connection path does not include the second connection path, and Z2is on the third connection path.” It is also possible to use the expression “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least Z1on a first connection path, the first connection path does not include a second connection path, the second connection path includes a connection path through the transistor, a drain (or a second terminal or the like) of the transistor is electrically connected to Y through at least Z2on a third connection path, and the third connection path does not include the second connection path.” Still another example of the expressions is “a source (or a first terminal or the like) of a transistor is electrically connected to X through at least Z1on a first electrical path, the first electrical path does not include a second electrical path, the second electrical path is an electrical path from the source (or the first terminal or the like) of the transistor to a drain (or a second terminal or the like) of the transistor, the drain (or the second terminal or the like) of the transistor is electrically connected to Y through at least Z2on a third electrical path, the third electrical path does not include a fourth electrical path, and the fourth electrical path is an electrical path from the drain (or the second terminal or the like) of the transistor to the source (or the first terminal or the like) of the transistor.” When the connection path in a circuit structure is defined by an expression similar to the above examples, a source (or a first terminal or the like) and a drain (or a second terminal or the like) of a transistor can be distinguished from each other to specify the technical scope.

Note that these expressions are examples and there is no limitation on the expressions. Here, X, Y, Z1, and Z2each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

Even when independent components are electrically connected to each other in a circuit diagram, one component has functions of a plurality of components in some cases. For example, when part of a wiring also functions as an electrode, one conductive film functions as the wiring and the electrode. Thus, the term “electrical connection” in this specification also means such a case where one conductive film has functions of a plurality of components.

Note that the terms “film” and “layer” can be interchanged with each other depending on circumstances or conditions. For example, the term “conductive layer” can be changed into the term “conductive film” in some cases. In addition, the term “insulating film” can be changed into the term “insulating layer” in some cases.

In this embodiment, an imaging device that is one embodiment of the present invention is described with reference to drawings.

An imaging device in one embodiment of the present invention includes a pixel circuit that can compensate variation in electrical characteristics of a source follower amplifier transistor in a pixel of an imaging device that outputs signal charge (data) by a source follower. The pixel circuit can compensate not only variations in the threshold voltage and the mobility of the transistor but also variation in the current due to variation in the size (L, W) of the channel formation region of the transistor or in the thickness (capacitance) of the gate insulating film thereof

FIG. 1is a circuit diagram of a circuit11that can function as a pixel circuit, a circuit12that can function as a reference current source circuit, and a circuit13that can function as an output circuit, included in an imaging device in one embodiment of the present invention. InFIG. 1and the like, transistors are n-ch transistors; however, one embodiment of the present invention is not limited thereto. The transistors may be p-ch transistors by reversing the magnitude relationship of a potential as illustrated inFIG. 42. Alternatively, some of the n-ch transistors may be replaced with p-ch transistors.

The circuit11is broadly divided into a photoelectric conversion portion and a signal generation portion. The photoelectric conversion portion includes a photodiode60, a transistor51, and a transistor52. The signal generation portion includes a transistor53, a transistor54, a transistor55, a transistor56, a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor C4. Note that the capacitor C4can be omitted.

The circuit12includes a transistor57and a transistor59.

The circuit13includes a transistor58, a resistor R, and an output terminal (OUT).

The circuit12and the circuit13that are connected to a wiring30can have structures illustrated inFIGS. 2A to 2C.FIG. 2Aillustrates a structure in which a transistor59is omitted from the circuit12.FIG. 2Billustrates a structure in which the circuit13is omitted and the wiring30is provided with an output terminal (OUT).FIG. 2Cillustrates a structure in which the circuit13, and the transistor59of the circuit12are omitted and the wiring30is provided with the output terminal (OUT).

In the circuit11inFIG. 1, one terminal of the photodiode60is electrically connected to one of a source and a drain of the transistor51. The other of the source and the drain of the transistor51is electrically connected to one of a source and a drain of the transistor52. The other of the source and the drain of the transistor51is electrically connected to one terminal of the capacitor C1. One of a source and a drain of the transistor53is electrically connected to the other terminal of the capacitor C1. The other terminal of the capacitor C1is electrically connected to one terminal of the capacitor C2. One of a source and a drain of the transistor54is electrically connected to the other terminal of the capacitor C2. The other of the source and the drain of the transistor54is electrically connected to one of a source and a drain of the transistor55. One terminal of the capacitor C3is electrically connected to the other terminal of the capacitor C2. The other terminal of the capacitor C3is electrically connected to the other of the source and the drain of the transistor55. A gate of the transistor55is electrically connected to one terminal of the capacitor C3. One terminal of the capacitor C4is electrically connected to one terminal of the capacitor C2. The other terminal of the capacitor C4is electrically connected to one of the source and the drain of the transistor55. The other of the source and the drain of the transistor55is electrically connected to one of a source and a drain of the transistor56.

The other terminal of the photodiode60is electrically connected to a wiring21(VPD). The other of the source and the drain of the transistor52is electrically connected to a wiring22(VPR). One of the source and the drain of the transistor55is electrically connected to a wiring23(VPI). A gate of the transistor51is electrically connected to a wiring25(TX). A gate of the transistor52is electrically connected to a wiring26(PR). A gate of the transistor53is electrically connected to a wiring27(W). A gate of the transistor54is electrically connected to a wiring28(AZ). A gate of the transistor56is electrically connected to a wiring29(SE). The other of the source and the drain of the transistor56is electrically connected to the wiring30.

In the circuit12, one of the source and the drain of the transistor57is electrically connected to the wiring30, and the other of the source and the drain of the transistor57is electrically connected to a wiring24(VPO). One of a source and a drain of the transistor59is electrically connected to a wiring31(BR). One of the source and the drain of the transistor59is electrically connected to a gate of the transistor59and to the gate of the transistor57. The other of the source and the drain of the transistor59is electrically connected to the wiring24(VPO).

In the circuit13, one of a source and a drain of the transistor58is electrically connected to the wiring30. One of the source and the drain of the transistor58is provided with the output terminal (OUT). The other of the source and the drain of the transistor58is electrically connected to one terminal of the resistor R. A gate of the transistor58is electrically connected to the wiring32(OE). The other terminal of the resistor R is electrically connected to the wiring24(VPO).

Here, the wiring21(VPD), the wiring22(VPR), the wiring23(VPI), and the wiring24(VPO) can function as power supply lines. The wiring25(TX), the wiring26(PR), the wiring27(W), the wiring28(AZ), the wiring29(SE), the wiring30, the wiring31(BR), and the wiring32(OE) can function as signal lines.

InFIG. 1, the other of the source and the drain of the transistor53is connected to the wiring21(VPD); however, the other of the source and the drain of the transistor53may be connected to a wiring capable of supplying another fixed potential.

In addition, inFIG. 1, the other terminal of the capacitor C4is connected to the wiring23(VPI); however, the other terminal of the capacitor C4may be connected to a wiring capable of supplying another fixed potential.

In the above structure, a node to which the other of the source and the drain of the transistor51, one of the source and the drain of the transistor52, and one terminal of the capacitor C1are connected is denoted by FD1.

A node to which one of the source and the drain of the transistor53, the other terminal of the capacitor C1, one terminal of the capacitor C2, and one terminal of the capacitor C4are connected is denoted by FD2.

A node to which one of the source and the drain of the transistor54, the other terminal of the capacitor C2, one terminal of the capacitor C3, and the gate of the transistor55are connected is denoted by AG.

A node to which the other of the source and the drain of the transistor55, the other terminal of the capacitor C3, and one of the source and the drain of the transistor56are connected is denoted by AS.

A diode element formed using a silicon substrate with a pn junction or a pin junction can be used as the photodiode60. Alternatively, a pin diode element formed using an amorphous silicon film, a microcrystalline silicon film, or the like may be used. Note that although the circuit11includes the photodiode, the circuit11may include another photoelectric conversion element. For example, a diode-connected transistor may be used. Alternatively, a variable resistor or the like utilizing a photoelectric effect may be formed using silicon, germanium, selenium, or the like.

Alternatively, a photoelectric conversion element that includes selenium utilizing a phenomenon called avalanche multiplication may be used. In the photoelectric conversion element, a highly sensitive sensor in which the amount of amplification of electrons with respect to the amount of incident light is large can be obtained.

Amorphous selenium or crystalline selenium can be used as a selenium-based material. Crystalline selenium can be obtained by, for example, depositing amorphous selenium and then performing heat treatment. When the crystal grain size of crystalline selenium is smaller than a pixel pitch, variation in characteristics between pixels can be reduced.

In the circuit11, the photodiode60is a light-receiving element and can have a function of generating current based on the amount of light incident on the circuit11. The transistor51can have a function of controlling charge accumulation in the node FD1performed by the photodiode60. The transistor52can have a function of executing operation of resetting the potential of the node FD1. The transistor53can have a function of executing operation of resetting the potential of the node FD2. The transistor54can have a function of supplying current to the transistor55. The transistor55can have a function of executing operation of outputting a signal based on the potential of the node AG. The transistor56can have a function of executing operation of controlling selection of the circuit11(pixel circuit) at the time of reading.

In the circuit12, the transistors57and59form a current mirror circuit and have a function of supplying current that is equal to the current flowing to the transistor59to the transistor57.

The circuit13can have a function of outputting a voltage signal based on current supplied to the transistor58and the resistor R from the output terminal (OUT).

In the imaging device in one embodiment of the present invention with the above structure, an output signal can be compensated when the circuit11stores Vgsdetermining reference output in a saturation region (Vds>Vgs−Vth, Vds: drain-source voltage, Vgs: gate-source voltage, Vth: threshold voltage) of the transistor55included in the circuit11.

Details of the compensation operation and output operation after compensation are described with reference to a timing chart inFIG. 3. The timing chart inFIG. 3shows the potentials of the wiring25(TX), the wiring26(PR), the wiring27(W), the wiring28(AZ), the wiring29(SE), the wiring31(BR), the wiring32(OE), the node FD1, the node FD2, the node AG, the node AS, and the output terminal (OUT). Note that each transistor is turned on or off in accordance with a potential supplied to a wiring connected to the gate of each transistor.

In the circuit diagram used for the description, transistors other than the transistor55are described as switches in order to clarify conduction state of the transistors. In addition, some reference numerals are omitted. The switching of the transistor59is performed in conjunction with the switching of the transistor57. Here, the wiring21(VPD) has a low potential (“GND”), the wiring22(VPR) has a high potential (“VPR”), the wiring23(VPI) has a high potential (“VPI”), and the wiring24(VPO) has a low potential (“GND”).

At time T1, the transistors52,53,54,56,57, and59are turned on and the transistors51and58are turned off. When a reference signal current is supplied to the wiring31(BR), a reference current (Iref) flows to the transistor59, and a bias current (Ibias) flows between the wiring23(VPI) and the wiring24(VPO) through the transistor57(see a current path indicated by a broken line inFIG. 4). Note that the reference signal voltage may be supplied to the wiring31(BR).

At this time, the potential of the node FD1is set to the potential (“VPR”) of the wiring22(VPR). The potential of the node FD2is set to the potential (“GND,” for example, 0 V) of the wiring21(VPD). The potential of the node AG is set to the potential (“VPI”) of the wiring23(VPI). Here, when a potential difference between the gate and the source of the transistor55is denoted by “Vgs,” the potential of the node AS is set to “VPI−Vgs” because the potential of the gate (the potential of the node AG) is “VPI.” The potential of the node AG is “VPI” and the potential of the node AS is “VPI−Vgs;” thus, “Vgs” is applied to both ends of the capacitor C3. Note that “Vgs” equals “Vth(the threshold voltage of the transistor55)” plus “Vov(an overdrive voltage).” Accordingly, “Vgs” for supplying the bias current (Ibias) is set.

Next, at time T2, the transistor54is turned off, which makes the node AG floating, so that “Vgs” is held in the capacitor C3(seeFIG. 5).

Next, at time T3, all transistors are turned off, which makes the bias current (Ibias) shut off, so that the potential of the node AS increases from “VPI−Vgs” to “VPI.” In addition, the potential of the node AG increases from “VPI” to “VPI+Vgs.” The potential of the node FD2increases from “GND” to “Vgs” (seeFIG. 6) when “GND” is equal to 0 V. Accordingly, holding of “Vgs” for supplying the bias current (Ibias) is completed. That is, storing, in the circuit11, of “Vgs” determining the reference output of the transistor55is completed.

Next, output operation after the compensation is described. At time T4, the transistors56and58are turned on and the transistors51,52,53,54,57, and59are turned off. At this time, in the capacitor C3, “Vgs” for supplying the bias current (Ibias) is held, so that the bias current (Ibias) flows between the wiring23(VPI) and the wiring24(VPO) through the circuit13(the transistor58and the resistor R). Therefore, “R·Ibias” that is a reference output voltage is output from the output terminal of the circuit13(seeFIG. 7). The potential of the other terminal of the capacitor C3is “R·Ibias” at this time; therefore, the potential of the node AG is “R·Ibias+Vgs”.

Next, on the assumption of actual imaging operation, operation when the potential of the node FD2is changed by −Vαis described. First, in order to change the potential of the node FD2by −Vα, the transistor52is turned off, the transistor51is turned on while the potential “VPR” of the wiring22(VPR) is held in the node FD1, and charge corresponding to −Vαis discharged to the wiring21(VPD) through the photodiode60irradiated with light. Then, the transistor51is turned off to hold the potential of the node FD1. Through the above operation, the potential of the node FD1can be changed from “VPR” to “VPR−Vα.”

When the potential of the node FD1is changed from “VPR” to “VPR−Vα,” the potential of the node FD2is changed from “Vgs” to “Vgs−Vα.” In addition, the potential of the node AG is changed from “R·Ibias+Vgs” to “R·Ibias+Vgs−Vα.” Accordingly, a bias current (Ibias′) based on the potential of the node AG “R·Ibias+Vgs−Vα” is supplied between the wiring23(VPI) and the wiring24(VPO). At this time, “R·Ibias+Vgs−Vα,” that is, “R·Ibias′” (Ibias′<Ibias) is output from the output terminal of the circuit13(seeFIG. 8).

In this manner, the lower output signal than the reference output voltage by the voltage corresponding to −Vαcan be obtained. That is, in the circuit structure ofFIG. 1, as the intensity of light delivered to the photodiode60becomes higher, a signal output from the output terminal (OUT) becomes smaller.

It is not necessary to perform the compensation operation by each imaging and imaging can be successively performed only by one compensation operation. Needless to say, the compensation operation may be performed before imaging, after imaging, at the time of power-on, at the time of power-off, or at given timing using a timer or the like.

An imaging device in one embodiment of the present invention may have a structure inFIG. 9A or 9B. The connection direction of the photodiode60of the photoelectric conversion portion in the circuit11inFIG. 9Ais opposite to that inFIG. 1. In that case, the wiring21(VPD) has a high potential and the wiring22(VPR) has a low potential. The circuit description inFIG. 1can be referred to for compensation operation and output operation. In that case, as the intensity of light delivered to the photodiode60becomes higher, the potential of the node FD1becomes higher. Thus, in the circuit structure ofFIG. 9A, as the intensity of light delivered to the photodiode60becomes higher, a signal output from the output terminal (OUT) becomes larger.

InFIG. 9B, the transistor52is omitted from the circuit11inFIG. 1. In that case, the wiring21(VPD) can be changed to either a low potential or a high potential. FD1reset operation can be performed when the wiring21(VPD) has a high potential. In a predetermined period, when the wiring21(VPD) has a high potential, forward bias is applied to the photodiode60. Thus, the potential of the node FD1can be set to the potential of the wiring21(VPD).

In the case where light detection operation (accumulation operation) is performed, the potential of the wiring21(VPD) is set to a low potential. When the wiring21(VPD) has a low potential, reverse bias is applied to the photodiode60; thus, charge can be released from the node FD1to the wiring21(VPD) in accordance with light intensity. In that case, as the intensity of light delivered to the photodiode60becomes higher, the potential of the node FD1becomes lower. Thus, in the circuit structure ofFIG. 9B, as the intensity of light delivered to the photodiode60becomes higher, a signal output from the output terminal (OUT) becomes smaller.

In the imaging device in one embodiment of the present invention, a transistor including an oxide semiconductor is preferably used. The use of the transistor including an oxide semiconductor in the circuit11can broaden the dynamic range of imaging. In the circuit structure inFIG. 1, when the intensity of light entering the photodiode60is high, the potential of the node AG becomes lower. Since the transistor including an oxide semiconductor has extremely low off-state current, current based on the potential of the node AG (the gate potential of the transistor55) can be accurately output even when the gate potential is extremely low. Thus, it is possible to broaden the detectable range of illuminance, i.e., the dynamic range.

A period during which charge can be held in the node FD1, the node FD2, the node AG, and the node AS can be extremely long owing to the low off-state current of the transistor including an oxide semiconductor. Thus, a global shutter system, in which charge accumulation operation is performed in all the pixels substantially at the same time, can be used without a complicated circuit structure and operation method. Therefore, an image with little distortion can be easily obtained even in the case of a moving object. Furthermore, exposure time (a period of performing charge accumulation operation) can be long; thus, the imaging device is suitable for imaging even in a low illuminance environment.

A transistor connected to any of the node FD1, the node FD2, the node AG, and the node AS needs to be a transistor with low noise. The channel of a transistor including two or three oxide semiconductor layers to be described later is a buried channel, which has significantly high resistance to noise. Thus, the use of the transistor leads to an image with low noise.

In the one embodiment of the present invention, an output signal that does not depend on variations in parameters (the threshold voltage, mobility, size of the channel formation region (L, W), thickness (capacitance) of the gate insulating film, and the like) of the amplifier transistor (the transistor55) included in the pixel circuit can be obtained.

FIG. 10Ais an example of a cross-sectional view of an imaging device including a circuit portion. A circuit portion90is a combination of a transistor70that includes an active region in a silicon substrate40and a transistor71that includes an oxide semiconductor as an active layer, and can form, for example, an inverter circuit or a memory circuit. In addition, a circuit portion92is a combination of the photodiode60formed using the silicon substrate40and the transistor51that includes an oxide semiconductor as an active layer, and corresponds to part of the photoelectric conversion portion of the circuit11inFIG. 1. Note that wirings and contact plugs indicated by broken lines show that placement is different from that of other wirings and contact plugs in a depth direction.

InFIG. 10A, the photodiode60and the transistor51can be formed to overlap with each other; thus, the integration degree of pixels can be increased. In other words, the resolution of the imaging device can be increased. Furthermore, since the silicon substrate40is not provided with a transistor formed in the occupation area of the circuit portion92, the area of the photodiode can be large. Thus, an image with low noise can be obtained even in a low illuminance environment.

AlthoughFIGS. 10A and 10Billustrate a structure in which the photodiode60and the transistor70are formed using the silicon substrate40, one embodiment of the present invention is not limited thereto. For example, the transistor70may be formed using the silicon substrate40and a photodiode formed using another substrate may be attached. Alternatively, the transistor70may be formed without the use of the silicon substrate40, and a transistor that includes an oxide semiconductor as an active layer may be provided as in the transistors71and51. Alternatively, as illustrated inFIG. 10B, the transistors70and51may be provided using the silicon substrate40. An element other than the transistor70may be formed using the silicon substrate40. For example, a capacitor, a diode, or a resistor may be formed using the silicon substrate40.

In the structure inFIG. 10A, an insulating layer80is provided between a region including the transistor70and the photodiode60and a region including the transistors71and51.

Dangling bonds of silicon are terminated with hydrogen in insulating layers provided in the vicinity of the active region of the transistor70. Therefore, hydrogen has an effect of improving the reliability of the transistor70. Meanwhile, hydrogen in insulating layers provided in the vicinities of oxide semiconductor layers that are the active layers of the transistors51and71and the like causes generation of carriers in the oxide semiconductors. Therefore, hydrogen might reduce the reliability of the transistors51and71and the like. Consequently, in the case where one layer that includes a transistor including a silicon-based semiconductor material and the other layer that includes the transistor including an oxide semiconductor are stacked, it is preferable that the insulating layer80having a function of preventing diffusion of hydrogen be provided between these layers. Hydrogen is confined in the one layer by the insulating layer80, so that the reliability of the transistor51can be improved. Furthermore, diffusion of hydrogen from the one layer to the other layer is inhibited, so that the reliability of the transistors51and71and the like can be improved.

The silicon substrate40is not limited to a bulk silicon substrate and may be an SOI substrate. Furthermore, the silicon substrate40can be replaced with a substrate made of germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor, or a substrate over which a thin film of the material is formed.

The transistor70can be a transistor of various types without being limited to a planar type transistor. For example, the transistor70can be a fin-type transistor or a tri-gate transistor.

The transistor51can include various types of semiconductors as well as an oxide semiconductor depending on conditions. For example, the transistor51can include silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor.

As illustrated in FIGS.11A1and11B1, the imaging device may be bent. FIG.11A1illustrates a state in which the imaging device is bent in the direction of dashed-two dotted line X1-X2. FIG.11A2is a cross-sectional view illustrating a portion indicated by dashed-two dotted line X1-X2in FIG.11A1. FIG.11A3is a cross-sectional view illustrating a portion indicated by dashed-two dotted line Y1-Y2in FIG.11A1.

FIG.11B1illustrates a state where the imaging device is bent in the direction of dashed-two dotted line X3-X4and the direction of dashed-two dotted line Y3-Y4. FIG.11B2is a cross-sectional view illustrating a portion indicated by dashed-two dotted line X3-X4in FIG.11B1. FIG.11B3is a cross-sectional view illustrating a portion indicated by dashed-two dotted line Y3-Y4in FIG.11B1.

Bending the imaging device can reduce field curvature and astigmatism. Thus, the optical design of lens and the like, which are used in combination of the imaging device, can be facilitated. For example, the number of lenses used for aberration correction can be reduced; accordingly, the size or weight of semiconductor devices including the imaging device can be easily reduced. In addition, the quality of a captured image can be improved.

In this embodiment, one embodiment of the present invention has been described. Other embodiments of the present invention are described in the other embodiments. Note that one embodiment of the present invention is not limited thereto. Although an example in which one embodiment of the present invention is applied to an imaging device is described, one embodiment of the present invention is not limited thereto. Depending on circumstances or conditions, one embodiment of the present invention is not necessarily applied to an imaging device. One embodiment of the present invention may be applied to a semiconductor device with an another function, for example. Although examples in which, in one embodiment of the present invention, a function of compensating variation or degradation in electrical characteristics of a transistor is provided or compensation operation is performed, one embodiment of the present invention is not limited thereto. Depending on circumstances or conditions, one embodiment of the present invention does not necessarily compensate variation or degradation in electrical characteristics of a transistor.

This embodiment can be combined with any of the structures described in the other embodiments as appropriate.

In this embodiment, an example of a method for driving a pixel circuit is described.

The pixel circuit described in Embodiment 1 can perform first operation in which normal imaging is performed and second operation in which differential data of imaging data of an initial frame and imaging data of a current frame can be retained and a signal based on the differential data can be output. In the second operation, differential data can be output without a comparison process or the like in an external circuit; thus, the pixel circuit can be applied to a low-power security camera or the like.

As illustrated inFIG. 12, an imaging device in one embodiment of the present invention includes a pixel portion400that includes the circuits11arranged in a matrix, a row driver410connected to the circuits11, the circuits12and the circuits13connected to the circuits11, an A/D converter420connected to the circuits12, and a column driver430connected to the A/D converter420.

Imaging data obtained in the circuit11selected by the row driver410is input to the A/D converter420through the circuit12. The A/D converter420converts input imaging data into digital data by A/D conversion. The A/D converted digital data are sequentially extracted to the outside by the column driver430. As the row driver410and the column driver430, for example, a variety of circuits such as a decoder and a shift register can be used.

Next, first operation of the circuit inFIG. 1is described with reference to a timing chart inFIG. 40.

From the time T1to the time T2, the wiring25(TX) is set to a potential higher than VPR+Vth, the wiring26(PR) is set to a potential higher than VPR+Vth, and the wiring27(W) is set to a potential higher than Vth. At this time, the potential of the node FD1is set to the potential of the wiring22(VPR), i.e., “VPR,” and the potential of the node FD2is set to the potential of the wiring21(VPD), i.e., “GND” (reset operation).

From the time T2to the time T3, the wiring25(TX) is set to a potential higher than VPR+Vth, the wiring26(PR) is set to “GND,” and the wiring27(W) is set to a potential lower than −VPR. Here, the potentials of the node FD1and the node FD2are decreased in response to light with which the photodiode60is irradiated. When the amount of decrease in the potential of the node FD1at the time T3is denoted by V1, the potential of the node FD1is VPR−V1. In addition, the potential of the node FD2is decreased by V2due to capacitive coupling and becomes GND−V2(accumulation operation). Note that in the circuit structure inFIG. 1, as the intensity of light delivered to the photodiode60becomes higher, the potentials of the node FD1and the node FD2become lower.

In the case where the wiring25(TX) is set to “GND,” the wiring26(PR) is set to “GND,” and the wiring27(W) is set to a potential lower than −VPR from the time T3to the time T4, the potentials of the node FD1and the node FD2are held.

In the case where the wiring30(SE) is set to a potential higher than VPI+Vth, from the time T4to time T5, a signal based on imaging data is output to the output terminal (OUT) in accordance with the potential of the node FD2(selection operation). Through the operation from the time T1to the time T5, the first operation can be performed.

Next, second operation of the circuit inFIG. 1is described with reference to a timing chart inFIG. 41.

From the time T1to the time T2, the wiring25(TX) is set to a potential higher than VPR+Vth, the wiring26(PR) is set to a potential higher than VPR+Vth, and the wiring27(W) is set to a potential higher than Vth. At this time, the potential of the node FD1is set to the potential of the wiring22(VPR), i.e., “VPR,” and the potential of the node FD2is set to the potential of the wiring21(VPD), i.e., “GND.”

From the time T2to the time T3, the wiring25(TX) is set to a potential higher than VPR+Vth, the wiring26(PR) is set to “GND,” and the wiring27(W) is set to a potential higher than Vth. Here, the potential of the node FD1is decreased in response to light with which the photodiode60is irradiated. When the amount of decrease in the potential of the node FD1at the time T3is denoted by V1, the potential of the node FD1is VPR−V1. Note that in the circuit structure inFIG. 1, as the intensity of light delivered to the photodiode60becomes higher, the potential of the node FD1becomes lower.

In the case where the wiring25(TX) is set to “GND,” the wiring26(PR) is set to “GND,” and the wiring27(W) is set to a potential higher than Vthfrom the time T3to the time T4, the potential of the node FD1is held.

In the case where the wiring25(TX) is set to “GND,” the wiring26(PR) is set to “GND,” and the wiring27(W) is set to a potential lower than −VPR from the time T4to the time T5, the potentials of the node FD1and the node FD2are held.

In the case where the wiring25(TX) is set to a potential higher than VPR+Vth, the wiring26(PR) is set to a potential higher than VPR+Vth, and the wiring27(W) is set to a potential lower than −VPR from the time T5to time T6, the potential of the node FD1is increased by V1and the potential of the node FD2is increased by V2due to capacitive coupling. Here, V1and V2are potentials that reflect illuminance of an initial frame.

In the case where the wiring25(TX) is set to a potential higher than VPR+Vth, the wiring26(PR) is set to “GND,” and the wiring27(W) is set to a potential lower than −VPR from the time T6to time T7, the potentials of the node FD1and the node FD2are decreased in response to light with which the photodiode60is irradiated. When the amount of decrease in the potential of the node FD1at the time T6is denoted by V1′, the potential of the node FD1is VPR−V1′. In addition, the potential of the node FD2is decreased by V2′ due to capacitive coupling and becomes GND+V2−V2′.

In the case where the wiring25(TX) is set to “GND,” the wiring26(PR) is set to “GND,” and the wiring27(W) is set to a potential lower than −VPR from the time T7to time T8, the potentials of the node FD1and the node FD2are held.

In the case where the wiring30(SE) is set to a potential higher than VPI+Vth, from the time T8to time T9, a signal based on imaging data is output from the output terminal (OUT) in accordance with the potential of the node FD2. In the above case, the potential of the node FD2at the time of signal output is GND+V2−V2′; thus, the potential is V2−V2′ when GND is 0 V, for example. Here, V2is a potential that reflects the illuminance of the initial frame, and V2′ is a potential that reflects illuminance of a later frame (current frame). In other words, the second operation in which a difference between the initial frame and the current frame is output can be performed.

This embodiment can be combined with any of the structures described in the other embodiments as appropriate.

In this embodiment, an example of a method for driving a pixel circuit is described.

As described in Embodiment 2, the operation of the pixel circuit is repetition of the reset operation, the accumulation operation, and the selection operation. As imaging modes in which the whole pixel matrix is controlled, a global shutter system and a rolling shutter system are known.

FIG. 13Ais a timing chart of a global shutter system. The timing chart illustrates operation of an imaging device in which a plurality of pixel circuits inFIG. 1are arranged in a matrix. Specifically, the timing chart illustrates operation of the pixel circuits from a first row to an n-th row (n is a natural number of 3 or more). The operation is described giving the first operation described in Embodiment 2 as an example.

InFIG. 13A, a signal501, a signal502, and a signal503are input to the wirings26(PR) connected to the pixel circuits in the first row, the second row, and the n-th row, respectively. A signal504, a signal506, and a signal508are input to the wirings25(TX) connected to the pixel circuits in the first row, the second row, and the n-th row, respectively. A signal505, a signal507, and a signal509are input to the wirings29(SE) connected to the pixel circuits in the first row, the second row, and the n-th row, respectively.

A period510is a period required for one imaging. A period511and a period520are periods in which reset operation and accumulation operation are performed at the same time in the pixel circuits in each row, respectively. Note that the selection operation is sequentially performed in the pixel circuits in each row. For example, in a period531, the selection operation is performed in the pixel circuits in the first row. As described above, in the global shutter system, the reset operation and the accumulation operation are performed in all the pixel circuits substantially at the same time, and then read operation is sequentially performed in each row.

That is, in the global shutter system, since the accumulation operation is performed in all the pixel circuits substantially at the same time, imaging is simultaneously performed in the pixel circuits in all the rows. Therefore, an image with little distortion can be obtained even in the case of a moving object.

FIG. 13Bis a timing chart of the case using a rolling shutter system. The description ofFIG. 13Acan be referred to for the signals501to509. A period610is a period required for one imaging. A period611is a period in which the pixels in the first row perform reset operation. A period612is a period in which the pixels in the second row perform reset operation. A period613is a period in which the pixels in the n-th row perform reset operation. A period621is a period in which the pixels in the first row perform accumulation operation. A period622is a period in which the pixels in the second row perform accumulation operation. A period623is a period in which the pixels in the n-th row perform accumulation operation. A period631is a period in which the pixels in the first row perform selection operation. As described above, in the rolling shutter system, the accumulation operation is not performed at the same time in all the pixel circuits but is sequentially performed in each row; thus, imaging is not simultaneously performed in the pixel circuits in all the rows. Therefore, the timing of imaging in the first row is different from that of imaging in the last row, and thus an image with large distortion is obtained in the case of a moving object.

To achieve the global shutter system, the potential of a charge accumulation portion (the node FD2) needs to be held for a long time until sequential reading of signals from the pixels is terminated. When a transistor including a channel formation region formed using an oxide semiconductor and having extremely low off-state current is used as the transistor55or the like, the potential of charge accumulation portion (the node FD2) can be held for a long time. In the case where a transistor including a channel formation region formed using silicon or the like is used as the transistor55or the like, the potential of the charge accumulation portion (the node FD2) cannot be held for a long time because of high off-state current, which makes it difficult to use the global shutter system.

As described above, the use of the transistor in which a channel formation region is formed using an oxide semiconductor for the pixel circuits makes it easy to achieve the global shutter system.

This embodiment can be combined with any of the structures described in the other embodiments as appropriate.

In this embodiment, a transistor including an oxide semiconductor that can be used in one embodiment of the present invention is described with reference to drawings. In the drawings in this embodiment, some components are enlarged, reduced in size, or omitted for easy understanding.

FIGS. 14A and 14Bare a top view and a cross-sectional view illustrating a transistor101in one embodiment of the present invention. A cross section in the direction of dashed-dotted line B1-B2inFIG. 14Ais illustrated inFIG. 14B. A cross section in the direction of dashed-dotted line B3-B4inFIG. 14Ais illustrated inFIG. 20A. In some cases, the direction of dashed-dotted line B1-B2is referred to as a channel length direction, and the direction of dashed-dotted line B3-B4is referred to as a channel width direction.

The transistor101includes an insulating layer120in contact with a substrate115; an oxide semiconductor layer130in contact with the insulating layer120; conductive layers140and150electrically connected to the oxide semiconductor layer130; an insulating layer160in contact with the oxide semiconductor layer130and the conductive layers140and150; a conductive layer170in contact with the insulating layer160; an insulating layer175in contact with the conductive layers140and150, the insulating layer160, and the conductive layer170; and an insulating layer180in contact with the insulating layer175. The insulating layer180may function as a planarization film as necessary.

Here, the conductive layer140, the conductive layer150, the insulating layer160, and the conductive layer170can function as a source electrode layer, a drain electrode layer, a gate insulating film, and a gate electrode layer, respectively.

A region231, a region232, and a region233inFIG. 14Bcan function as a source region, a drain region, and a channel formation region, respectively. The region231and the region232are in contact with the conductive layer140and the conductive layer150, respectively. When a conductive material that is easily bonded to oxygen is used for the conductive layers140and150, for example, the resistance of the regions231and232can be reduced.

Specifically, since the oxide semiconductor layer130is in contact with the conductive layers140and150, an oxygen vacancy is generated in the oxide semiconductor layer130, and interaction between the oxygen vacancy and hydrogen that remains in the oxide semiconductor layer130or diffuses into the oxide semiconductor layer130from the outside changes the regions231and232to n-type regions with low resistance.

Note that functions of a “source” and a “drain” of a transistor are sometimes interchanged with each other when a transistor of an opposite conductivity type is used or when the direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be interchanged with each other in this specification. In addition, the term “electrode layer” can be changed into the term “wiring.”

The conductive layer170includes two layers, conductive layers171and172, but also may be a single layer or a stack of three or more layers. The same applies to other transistors described in this embodiment.

Each of the conductive layers140and150is a single layer, but also may be a stack of two or more layers. The same applies to other transistors described in this embodiment.

The transistor in one embodiment of the present invention may have a structure illustrated inFIGS. 15A and 15B.FIG. 15Ais a top view of a transistor102. A cross section in the direction of dashed-dotted line C1-C2inFIG. 15Ais illustrated inFIG. 15B. A cross section in the direction of dashed-dotted line C3-C4inFIG. 15Ais illustrated inFIG. 20B. In some cases, the direction of dashed-dotted line C1-C2is referred to as a channel length direction, and the direction of dashed-dotted line C3-C4is referred to as a channel width direction.

The transistor102has the same structure as the transistor101except that an end portion of the insulating layer160functioning as a gate insulating film is not aligned with an end portion of the conductive layer170functioning as a gate electrode layer. In the transistor102, wide areas of the conductive layers140and150are covered with the insulating layer160and accordingly the resistance between the conductive layer170and the conductive layers140and150is high; therefore, the transistor102has low gate leakage current.

The transistors101and102each have a top-gate structure including a region where the conductive layer170overlaps with the conductive layers140and150. To reduce parasitic capacitance, the width of the region in the channel length direction is preferably greater than or equal to 3 nm and less than 300 nm. Since an offset region is not formed in the oxide semiconductor layer130in this structure, a transistor with high on-state current can be easily formed.

The transistor in one embodiment of the present invention may have a structure illustrated inFIGS. 16A and 16B.FIG. 16Ais a top view of a transistor103. A cross section in the direction of dashed-dotted line D1-D2inFIG. 16Ais illustrated inFIG. 16B. A cross section in the direction of dashed-dotted line D3-D4inFIG. 16Ais illustrated inFIG. 20A. In some cases, the direction of dashed-dotted line D1-D2is referred to as a channel length direction, and the direction of dashed-dotted line D3-D4is referred to as a channel width direction.

The transistor103includes the insulating layer120in contact with the substrate115; the oxide semiconductor layer130in contact with the insulating layer120; the insulating layer160in contact with the oxide semiconductor layer130; the conductive layer170in contact with the insulating layer160; the insulating layer175covering the oxide semiconductor layer130, the insulating layer160, and the conductive layer170; the insulating layer180in contact with the insulating layer175; and the conductive layers140and150electrically connected to the oxide semiconductor layer130through openings provided in the insulating layers175and180. The transistor103may further include, for example, an insulating layer (planarization film) in contact with the insulating layer180and the conductive layers140and150as necessary.

Here, the conductive layer140, the conductive layer150, the insulating layer160, and the conductive layer170can function as a source electrode layer, a drain electrode layer, a gate insulating film, and a gate electrode layer, respectively.

The region231, the region232, and the region233inFIG. 16Bcan function as a source region, a drain region, and a channel formation region, respectively. The regions231and232are in contact with the insulating layer175. When an insulating material containing hydrogen is used for the insulating layer175, for example, the resistance of the regions231and232can be reduced.

Specifically, interaction between an oxygen vacancy generated in the regions231and232by the steps up to formation of the insulating layer175and hydrogen that diffuses into the regions231and232from the insulating layer175changes the regions231and232to n-type regions with low resistance. As the insulating material containing hydrogen, for example, silicon nitride, aluminum nitride, or the like can be used.

The transistor in one embodiment of the present invention may have a structure illustrated inFIGS. 17A and 17B.FIG. 17Ais a top view of a transistor104. A cross section in the direction of dashed-dotted line E1-E2inFIG. 17Ais illustrated inFIG. 17B. A cross section in the direction of dashed-dotted line E3-E4inFIG. 17Ais illustrated inFIG. 20A. In some cases, the direction of dashed-dotted line E1-E2is referred to as a channel length direction, and the direction of dashed-dotted line E3-E4is referred to as a channel width direction.

The transistor104has the same structure as the transistor103except that the conductive layers140and150in contact with the oxide semiconductor layer130cover end portions of the oxide semiconductor layer130.

InFIG. 17B, regions331and334can function as a source region, regions332and335can function as a drain region, and a region333can function as a channel formation region.

The resistance of the regions331and332can be reduced in a manner similar to that of the regions231and232in the transistor101.

The resistance of the regions334and335can be reduced in a manner similar to that of the regions231and232in the transistor103. In the case where the length of the regions334and335in the channel length direction is less than or equal to 100 nm, preferably less than or equal to 50 nm, a gate electric field prevents a significant decrease in on-state current. Therefore, a reduction in resistance of the regions334and335is not performed in some cases.

The transistors103and104each have a self-aligned structure that does not include a region where the conductive layer170overlaps with the conductive layers140and150. A transistor with a self-aligned structure, which has extremely low parasitic capacitance between a gate electrode layer and source and drain electrode layers, is suitable for applications that require high-speed operation.

The transistor in one embodiment of the present invention may have a structure illustrated inFIGS. 18A and 18B.FIG. 18Ais a top view of a transistor105. A cross section in the direction of dashed-dotted line F1-F2inFIG. 18Ais illustrated inFIG. 18B. A cross section in the direction of dashed-dotted line F3-F4inFIG. 18Ais illustrated inFIG. 20A. In some cases, the direction of dashed-dotted line F1-F2is referred to as a channel length direction, and the direction of dashed-dotted line F3-F4is referred to as a channel width direction.

The transistor105includes the insulating layer120in contact with the substrate115; the oxide semiconductor layer130in contact with the insulating layer120; conductive layers141and151electrically connected to the oxide semiconductor layer130; the insulating layer160in contact with the oxide semiconductor layer130and the conductive layers141and151; the conductive layer170in contact with the insulating layer160; the insulating layer175in contact with the oxide semiconductor layer130, the conductive layers141and151, the insulating layer160, and the conductive layer170; the insulating layer180in contact with the insulating layer175; and conductive layers142and152electrically connected to the conductive layers141and151, respectively, through openings provided in the insulating layers175and180. The transistor105may further include, for example, an insulating layer in contact with the insulating layer180and the conductive layers142and152as necessary.

Here, the conductive layers141and151are in contact with the top surface of the oxide semiconductor layer130and are not in contact with side surfaces of the oxide semiconductor layer130.

The transistor105has the same structure as the transistor101except that the conductive layers141and151are provided, that openings are provided in the insulating layers175and180, and that the conductive layers142and152electrically connected to the conductive layers141and151, respectively, through the openings are provided. The conductive layer140(the conductive layers141and142) can function as a source electrode layer, and the conductive layer150(the conductive layers151and152) can function as a drain electrode layer.

The transistor in one embodiment of the present invention may have a structure illustrated inFIGS. 19A and 19B.FIG. 19Ais a top view of a transistor106. A cross section in the direction of dashed-dotted line G1-G2inFIG. 19Ais illustrated inFIG. 19B. A cross section in the direction of dashed-dotted line G3-G4inFIG. 19Ais illustrated inFIG. 20A. In some cases, the direction of dashed-dotted line G1-G2is referred to as a channel length direction, and the direction of dashed-dotted line G3-G4is referred to as a channel width direction.

The transistor106includes the insulating layer120in contact with the substrate115; the oxide semiconductor layer130in contact with the insulating layer120; the conductive layers141and151electrically connected to the oxide semiconductor layer130; the insulating layer160in contact with the oxide semiconductor layer130; the conductive layer170in contact with the insulating layer160; the insulating layer175in contact with the insulating layer120, the oxide semiconductor layer130, the conductive layers141and151, the insulating layer160, and the conductive layer170; the insulating layer180in contact with the insulating layer175; and the conductive layers142and152electrically connected to the conductive layers141and151, respectively, through openings provided in the insulating layers175and180. The transistor106may further include, for example, an insulating layer (planarization film) in contact with the insulating layer180and the conductive layers142and152as necessary.

Here, the conductive layers141and151are in contact with the top surface of the oxide semiconductor layer130and are not in contact with side surfaces of the oxide semiconductor layer130.

The transistor106has the same structure as the transistor103except that the conductive layers141and151are provided. The conductive layer140(the conductive layers141and142) can function as a source electrode layer, and the conductive layer150(the conductive layers151and152) can function as a drain electrode layer.

In the structures of the transistors105and106, the conductive layers140and150are not in contact with the insulating layer120. These structures make the insulating layer120less likely to be deprived of oxygen by the conductive layers140and150and facilitate oxygen supply from the insulating layer120to the oxide semiconductor layer130.

An impurity for forming an oxygen vacancy to increase conductivity may be added to the regions231and232in the transistor103and the regions334and335in the transistors104and106. As an impurity for forming an oxygen vacancy in an oxide semiconductor layer, for example, one or more of the following can be used: phosphorus, arsenic, antimony, boron, aluminum, silicon, nitrogen, helium, neon, argon, krypton, xenon, indium, fluorine, chlorine, titanium, zinc, and carbon. As a method for adding the impurity, plasma treatment, ion implantation, ion doping, plasma immersion ion implantation, or the like can be used.

When the above element is added as an impurity element to the oxide semiconductor layer, a bond between a metal element and oxygen in the oxide semiconductor layer is cut, so that an oxygen vacancy is formed. Interaction between an oxygen vacancy in the oxide semiconductor layer and hydrogen that remains in the oxide semiconductor layer or is added to the oxide semiconductor layer later can increase the conductivity of the oxide semiconductor layer.

When hydrogen is added to an oxide semiconductor in which an oxygen vacancy is formed by addition of an impurity element, hydrogen enters an oxygen vacant site and forms a donor level in the vicinity of the conduction band. Consequently, an oxide conductor can be formed. Here, an oxide conductor refers to an oxide semiconductor having become a conductor. Note that the oxide conductor has a light-transmitting property in a manner similar to the oxide semiconductor.

The oxide conductor is a degenerated semiconductor and it is suggested that the conduction band edge equals or substantially equals the Fermi level. For that reason, an ohmic contact is made between an oxide conductor layer and conductive layers functioning as a source electrode layer and a drain electrode layer; thus, contact resistance between the oxide conductor layer and the conductive layers functioning as a source electrode layer and a drain electrode layer can be reduced.

The transistor in one embodiment of the present invention may include a conductive layer173between the oxide semiconductor layer130and the substrate115as illustrated in cross-sectional views in the channel length direction inFIGS. 21A to 21Fand cross-sectional views in the channel width direction inFIGS. 20C and 20D. When the conductive layer173is used as a second gate electrode layer (back gate), the on-state current can be increased or the threshold voltage can be controlled. In the cross-sectional views inFIGS. 21A to 21F, the width of the conductive layer173may be shorter than that of the oxide semiconductor layer130. Moreover, the width of the conductive layer173may be shorter than that of the conductive layer170.

In order to increase the on-state current, for example, the conductive layers170and173are made to have the same potential, and the transistor is driven as a double-gate transistor. Furthermore, in order to control the threshold voltage, a fixed potential that is different from the potential of the conductive layer170is applied to the conductive layer173. To set the conductive layers170and173at the same potential, for example, as illustrated inFIG. 20D, the conductive layers170and173may be electrically connected to each other through a contact hole.

Although the transistors101to106inFIGS. 14A and 14B,FIGS. 15A and 15B,FIGS. 16A and 16B,FIGS. 17A and 17B,FIGS. 18A and 18B, andFIGS. 19A and 19Bare examples in which the oxide semiconductor layer130is a single layer, the oxide semiconductor layer130may be a stacked layer. The oxide semiconductor layer130in the transistors101to106can be replaced with the oxide semiconductor layer130inFIGS. 22A to 22CorFIGS. 23A to 23C.

FIGS. 22A to 22Care a top view and cross-sectional views of the oxide semiconductor layer130with a two-layer structure.FIG. 22Billustrates a cross section in the direction of dashed-dotted line A1-A2inFIG. 22A.FIG. 22Cillustrates a cross section in the direction of dashed-dotted line A3-A4inFIG. 22A.

FIGS. 23A to 23Care a top view and cross-sectional views of the oxide semiconductor layer130with a three-layer structure.FIG. 23Billustrates a cross section in the direction of dashed-dotted line A1-A2inFIG. 23A.FIG. 23Cillustrates a cross section in the direction of dashed-dotted line A3-A4inFIG. 23A.

Oxide semiconductor layers with different compositions, for example, can be used as an oxide semiconductor layer130a, an oxide semiconductor layer130b, and an oxide semiconductor layer130c.

The transistor in one embodiment of the present invention may have a structure illustrated inFIGS. 24A and 24B.FIG. 24Ais a top view of a transistor107. A cross section in the direction of dashed-dotted line H1-H2inFIG. 24Ais illustrated inFIG. 24B. A cross section in the direction of dashed-dotted line H3-H4inFIG. 24Ais illustrated inFIG. 30A. In some cases, the direction of dashed-dotted line H1-H2is referred to as a channel length direction, and the direction of dashed-dotted line H3-H4is referred to as a channel width direction.

The transistor107includes the insulating layer120in contact with the substrate115; a stack of the oxide semiconductor layers130aand130bin contact with the insulating layer120; the conductive layers140and150electrically connected to the stack; the oxide semiconductor layer130cin contact with the stack and the conductive layers140and150; the insulating layer160in contact with the oxide semiconductor layer130c; the conductive layer170in contact with the insulating layer160; the insulating layer175in contact with the conductive layers140and150, the oxide semiconductor layer130c, the insulating layer160, and the conductive layer170; and the insulating layer180in contact with the insulating layer175. The insulating layer180may function as a planarization film as necessary.

The transistor107has the same structure as the transistor101except that the oxide semiconductor layer130includes two layers (the oxide semiconductor layers130aand130b) in the regions231and232, that the oxide semiconductor layer130includes three layers (the oxide semiconductor layers130ato130c) in the region233, and that part of the oxide semiconductor layer (the oxide semiconductor layer130c) exists between the insulating layer160and the conductive layers140and150.

The transistor in one embodiment of the present invention may have a structure illustrated inFIGS. 25A and 25B.FIG. 25Ais a top view of a transistor108. A cross section in the direction of dashed-dotted line I1-I2inFIG. 25Ais illustrated inFIG. 25B. A cross section in the direction of dashed-dotted line I3-I4inFIG. 25Ais illustrated inFIG. 30B. In some cases, the direction of dashed-dotted line I1-I2is referred to as a channel length direction, and the direction of dashed-dotted line I3-I4is referred to as a channel width direction.

The transistor108differs from the transistor107in that end portions of the insulating layer160and the oxide semiconductor layer130care not aligned with the end portion of the conductive layer170.

The transistor in one embodiment of the present invention may have a structure illustrated inFIGS. 26A and 26B.FIG. 26Ais a top view of a transistor109. A cross section in the direction of dashed-dotted line J1-J2inFIG. 26Ais illustrated inFIG. 26B. A cross section in the direction of dashed-dotted line J3-J4inFIG. 26Ais illustrated inFIG. 30A. In some cases, the direction of dashed-dotted line J1-J2is referred to as a channel length direction, and the direction of dashed-dotted line J3-J4is referred to as a channel width direction.

The transistor109includes the insulating layer120in contact with the substrate115; a stack of the oxide semiconductor layers130aand130bin contact with the insulating layer120; the oxide semiconductor layer130cin contact with the stack; the insulating layer160in contact with the oxide semiconductor layer130c; the conductive layer170in contact with the insulating layer160; the insulating layer175covering the stack, the oxide semiconductor layer130c, the insulating layer160, and the conductive layer170; the insulating layer180in contact with the insulating layer175; and the conductive layers140and150electrically connected to the stack through openings provided in the insulating layers175and180. The transistor109may further include, for example, an insulating layer (planarization film) in contact with the insulating layer180and the conductive layers140and150as necessary.

The transistor109has the same structure as the transistor103except that the oxide semiconductor layer130includes two layers (the oxide semiconductor layers130aand130b) in the regions231and232and that the oxide semiconductor layer130includes three layers (the oxide semiconductor layers130ato130c) in the region233.

The transistor in one embodiment of the present invention may have a structure illustrated inFIGS. 27A and 27B.FIG. 27Ais a top view of a transistor110. A cross section in the direction of dashed-dotted line K1-K2inFIG. 27Ais illustrated inFIG. 27B. A cross section in the direction of dashed-dotted line K3-K4inFIG. 27Ais illustrated inFIG. 30A. In some cases, the direction of dashed-dotted line K1-K2is referred to as a channel length direction, and the direction of dashed-dotted line K3-K4is referred to as a channel width direction.

The transistor110has the same structure as the transistor104except that the oxide semiconductor layer130includes two layers (the oxide semiconductor layers130aand130b) in the regions231and232and that the oxide semiconductor layer130includes three layers (the oxide semiconductor layers130ato130c) in the region233.

The transistor in one embodiment of the present invention may have a structure illustrated inFIGS. 28A and 28B.FIG. 28Ais a top view of a transistor111. A cross section in the direction of dashed-dotted line L1-L2inFIG. 28Ais illustrated inFIG. 28B. A cross section in the direction of dashed-dotted line L3-L4inFIG. 28Ais illustrated inFIG. 30A. In some cases, the direction of dashed-dotted line L1-L2is referred to as a channel length direction, and the direction of dashed-dotted line L3-L4is referred to as a channel width direction.

The transistor111includes the insulating layer120in contact with the substrate115; a stack of the oxide semiconductor layers130aand130bin contact with the insulating layer120; the conductive layers141and151electrically connected to the stack; the oxide semiconductor layer130cin contact with the stack and the conductive layers141and151; the insulating layer160in contact with the oxide semiconductor layer130c; the conductive layer170in contact with the insulating layer160; the insulating layer175in contact with the stack, the conductive layers141and151, the oxide semiconductor layer130c, the insulating layer160, and the conductive layer170; the insulating layer180in contact with the insulating layer175; and the conductive layers142and152electrically connected to the conductive layers141and151, respectively, through openings provided in the insulating layers175and180. The transistor111may further include, for example, an insulating layer (planarization film) in contact with the insulating layer180and the conductive layers142and152as necessary.

The transistor111has the same structure as the transistor105except that the oxide semiconductor layer130includes two layers (the oxide semiconductor layers130aand130b) in the regions231and232, that the oxide semiconductor layer130includes three layers (the oxide semiconductor layers130ato130c) in the region233, and that part of the oxide semiconductor layer (the oxide semiconductor layer130c) exists between the insulating layer160and the conductive layers141and151.

The transistor in one embodiment of the present invention may have a structure illustrated inFIGS. 29A and 29B.FIG. 29Ais a top view of a transistor112. A cross section in the direction of dashed-dotted line M1-M2inFIG. 29Ais illustrated inFIG. 29B. A cross section in the direction of dashed-dotted line M3-M4inFIG. 29Ais illustrated inFIG. 30A. In some cases, the direction of dashed-dotted line M1-M2is referred to as a channel length direction, and the direction of dashed-dotted line M3-M4is referred to as a channel width direction.

The transistor112has the same structure as the transistor106except that the oxide semiconductor layer130includes two layers (the oxide semiconductor layers130aand130b) in the regions331,332,334, and335and that the oxide semiconductor layer130includes three layers (the oxide semiconductor layers130ato130c) in the region333.

The transistor in one embodiment of the present invention may include the conductive layer173between the oxide semiconductor layer130and the substrate115as illustrated in cross-sectional views in the channel length direction inFIGS. 31A to 31Fand cross-sectional views in the channel width direction inFIGS. 30C and 30D. When the conductive layer is used as a second gate electrode layer (back gate), the on-state current can be increased or the threshold voltage can be controlled. In the cross-sectional views inFIGS. 31A to 31F, the width of the conductive layer173may be shorter than that of the oxide semiconductor layer130. Moreover, the width of the conductive layer173may be shorter than that of the conductive layer170.

As illustrated inFIG. 32A, the width (WSD) of the conductive layer140(source electrode layer) and the conductive layer150(drain electrode layer) in the transistor in one embodiment of the present invention may be longer than the width (WOS) of the oxide semiconductor layer. Furthermore, as illustrated inFIG. 32B, WSDmay be shorter than WOS. When WOS≧WSD(WSDis less than or equal to WOS) is satisfied, a gate electric field is easily applied to the entire oxide semiconductor layer130, so that electrical characteristics of the transistor can be improved.

In the transistor in one embodiment of the present invention (any of the transistors101to112), the conductive layer170functioning as a gate electrode layer electrically surrounds the oxide semiconductor layer130in the channel width direction with the insulating layer160functioning as a gate insulating film positioned therebetween. This structure increases the on-state current. Such a transistor structure is referred to as a surrounded channel (s-channel) structure.

In the transistor including the oxide semiconductor layers130aand130band the transistor including the oxide semiconductor layers130ato130c, selecting appropriate materials for the two or three layers forming the oxide semiconductor layer130makes current flow to the oxide semiconductor layer130b. Since current flows to the oxide semiconductor layer130b, the current is hardly influenced by interface scattering, leading to high on-state current. Note that increasing the thickness of the oxide semiconductor layer130bcan increase the on-state current. The thickness of the oxide semiconductor layer130bmay be, for example, 100 to 200 nm.

A semiconductor device including a transistor with any of the above structures can have favorable electrical characteristics.

Note that in this specification, the channel length refers to, for example, a distance between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where a semiconductor (or a portion where current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or in a region where a channel is formed in a top view of the transistor. In one transistor, channel lengths in all regions are not necessarily the same. In other words, the channel length of one transistor is not fixed to one value in some cases. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed. In one transistor, channel widths in all regions do not necessarily have the same value. In other words, the channel width of one transistor is not fixed to one value in some cases. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on transistor structures, a channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) is sometimes different from a channel width shown in a top view of a transistor (hereinafter referred to as an apparent channel width). For example, in a transistor having a gate electrode covering a side surface of a semiconductor, an effective channel width is greater than an apparent channel width, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor having a gate electrode covering a side surface of a semiconductor, the proportion of a channel region formed in a side surface of a semiconductor is increased. In that case, an effective channel width is greater than an apparent channel width.

In such a case, measuring an effective channel width is difficult in some cases. For example, to estimate an effective channel width from a design value, it is necessary to assume that the shape of a semiconductor is known. Therefore, in the case where the shape of a semiconductor is not known accurately, measuring an effective channel width accurately is difficult.

Accordingly, in this specification, an apparent channel width is referred to as a surrounded channel width (SCW) in some cases. Furthermore, in this specification, the term “channel width” may denote a surrounded channel width, i.e., an apparent channel width or an effective channel width. Note that the values of a channel length, a channel width, an effective channel width, an apparent channel width, a surrounded channel width, and the like can be determined by obtaining and analyzing a cross-sectional TEM image and the like.

A surrounded channel width may be used to calculate field-effect mobility, a current value per channel width, and the like of a transistor. In this case, the obtained value is sometimes different from the value obtained by using an effective channel width for the calculation.

The structure described above in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

In this embodiment, components of the transistors described in Embodiment 4 are described in detail.

The substrate115includes a silicon substrate provided with a transistor and/or a photodiode; and an insulating layer, a wiring, a conductor functioning as a contact plug, and the like that are provided over the silicon substrate. Note that when p-ch transistors are formed using the silicon substrate, a silicon substrate with n−-type conductivity is preferably used. Alternatively, an SOI substrate including an n−-type or i-type silicon layer may be used. A surface of the silicon substrate where the transistor is formed preferably has a (110) plane orientation. Forming a p-ch transistor with the (110) plane can increase mobility.

The insulating layer120can have a function of supplying oxygen to the oxide semiconductor layer130as well as a function of preventing diffusion of impurities from a component included in the substrate115. For this reason, the insulating layer120is preferably an insulating film containing oxygen and more preferably, the insulating layer120is an insulating film containing oxygen in which the oxygen content is higher than that in the stoichiometric composition. The insulating layer120is a film in which the amount of released oxygen when converted into oxygen atoms is preferably greater than or equal to 1.0×1019atoms/cm3in TDS analysis. In the TDS analysis, the film surface temperature is higher than or equal to 100° C. and lower than or equal to 700° C., or higher than or equal to 100° C. and lower than or equal to 500° C. The insulating layer120also functions as an interlayer insulating film and may be subjected to planarization treatment such as chemical mechanical polishing (CMP) so as to have a flat surface.

For example, the insulating layer120can be formed using an oxide insulating film including aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, or the like; a nitride insulating film including silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like; or a mixed material of any of these. The insulating layer120may be a stack of any of the above materials.

In this embodiment, detailed description is given mainly on the case where the oxide semiconductor layer130of the transistor has a three-layer structure in which the oxide semiconductor layers130ato130care sequentially stacked from the insulating layer120side.

Note that in the case where the oxide semiconductor layer130is a single layer, a layer corresponding to the oxide semiconductor layer130bdescribed in this embodiment is used.

In the case where the oxide semiconductor layer130has a two-layer structure, a stack in which a layer corresponding to the oxide semiconductor layer130aand a layer corresponding to the oxide semiconductor layer130bare sequentially stacked from the insulating layer120side described in this embodiment is used. In such a case, the oxide semiconductor layers130aand130bcan be replaced with each other.

In the case where the oxide semiconductor layer130has a layered structure of four or more layers, for example, a structure in which another oxide semiconductor layer is added to the three-layer stack of the oxide semiconductor layer130described in this embodiment can be employed.

For the oxide semiconductor layer130b, for example, an oxide semiconductor whose electron affinity (an energy difference between a vacuum level and the conduction band minimum) is higher than those of the oxide semiconductor layers130aand130cis used. The electron affinity can be obtained by subtracting an energy difference between the conduction band minimum and the valence band maximum (what is called an energy gap) from an energy difference between the vacuum level and the valence band maximum (what is called an ionization potential).

The oxide semiconductor layers130aand130ceach contain one or more kinds of metal elements contained in the oxide semiconductor layer130b. For example, the oxide semiconductor layers130aand130care preferably formed using an oxide semiconductor whose conduction band minimum is closer to a vacuum level than that of the oxide semiconductor layer130bby 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less.

In such a structure, when an electric field is applied to the conductive layer170, a channel is formed in the oxide semiconductor layer130bwhose conduction band minimum is the lowest in the oxide semiconductor layer130.

Furthermore, since the oxide semiconductor layer130acontains one or more kinds of metal elements contained in the oxide semiconductor layer130b, an interface state is unlikely to be formed at the interface between the oxide semiconductor layers130aand130b, compared with the interface between the oxide semiconductor layer130band the insulating layer120on the assumption that the oxide semiconductor layer130bis in contact with the insulating layer120. The interface state sometimes forms a channel; therefore, the threshold voltage of the transistor is changed in some cases. Thus, with the oxide semiconductor layer130a, variations in electrical characteristics of the transistor, such as a threshold voltage, can be reduced. Moreover, the reliability of the transistor can be improved.

Furthermore, since the oxide semiconductor layer130ccontains one or more kinds of metal elements contained in the oxide semiconductor layer130b, scattering of carriers is unlikely to occur at the interface between the oxide semiconductor layers130band130c, compared with the interface between the oxide semiconductor layer130band the gate insulating film (the insulating layer160) on the assumption that the oxide semiconductor layer130bis in contact with the gate insulating film. Thus, with the oxide semiconductor layer130c, the field-effect mobility of the transistor can be increased.

For the oxide semiconductor layers130aand130c, for example, a material containing Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf with a higher atomic ratio than that used for the oxide semiconductor layer130bcan be used. Specifically, the atomic ratio of any of the above metal elements in the oxide semiconductor layers130aand130cis 1.5 times or more, preferably 2 times or more, more preferably 3 times or more as large as that in the oxide semiconductor layer130b. Any of the above metal elements is strongly bonded to oxygen and thus has a function of suppressing generation of an oxygen vacancy in the oxide semiconductor layers130aand130c. That is, an oxygen vacancy is less likely to be generated in the oxide semiconductor layers130aand130cthan in the oxide semiconductor layer130b.

An oxide semiconductor that can be used for each of the oxide semiconductor layers130ato130cpreferably contains at least In or Zn. Both In and Zn are preferably contained. In order to reduce variations in electrical characteristics of the transistor including the oxide semiconductor, the oxide semiconductor preferably contains a stabilizer in addition to In and Zn.

For example, an In—Ga—Zn oxide means an oxide containing In, Ga, and Zn as its main components. The In—Ga—Zn oxide may contain another metal element in addition to In, Ga, and Zn. In this specification, a film containing the In—Ga—Zn oxide is also referred to as an IGZO film.

A material represented by InMO3(ZnO)m(m>0, where m is not an integer) may be used. Note that M represents one or more metal elements selected from Ga, Y, Zr, La, Ce, and Nd. Alternatively, a material represented by In2SnO5(ZnO)n(n>0, where n is an integer) may be used.

Note that when each of the oxide semiconductor layers130ato130cis an In-M-Zn oxide containing at least indium, zinc, and M (M is a metal such as Al, Ti, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf), in the case where the oxide semiconductor layer130ahas an atomic ratio of In to M and Zn which is x1:y1:z1, the oxide semiconductor layer130bhas an atomic ratio of In to M and Zn which is x2:y2:z2, and the oxide semiconductor layer130chas an atomic ratio of In to M and Zn which is x1:y3:z3, each of y1/x1and y3/x3is preferably larger than y2/x2. Each of y1/x1and Y3/x3is 1.5 times or more, preferably 2 times or more, more preferably 3 times or more as large as y2/x2. At this time, when y2is greater than or equal to x2in the oxide semiconductor layer130b, the transistor can have stable electrical characteristics. However, when y2is 3 times or more as large as x2, the field-effect mobility of the transistor is reduced; accordingly, y2is preferably smaller than 3 times x2.

In the case where Zn and O are not taken into consideration, the proportion of In and the proportion of M in each of the oxide semiconductor layers130aand130care preferably less than 50 atomic % and greater than or equal to 50 atomic %, respectively, more preferably less than 25 atomic % and greater than or equal to 75 atomic %, respectively. Furthermore, in the case where Zn and O are not taken into consideration, the proportion of In and the proportion of M in the oxide semiconductor layer130bare preferably greater than or equal to 25 atomic % and less than 75 atomic %, respectively, more preferably greater than or equal to 34 atomic % and less than 66 atomic %, respectively.

The indium content in the oxide semiconductor layer130bis preferably higher than those in the oxide semiconductor layers130aand130c. In an oxide semiconductor, the s orbital of heavy metal mainly contributes to carrier transfer, and when the proportion of In in the oxide semiconductor is increased, overlap of the s orbitals is likely to be increased. Therefore, an oxide in which the proportion of In is higher than that of M has higher mobility than an oxide in which the proportion of In is equal to or lower than that of M. Thus, with the use of an oxide having a high content of indium for the oxide semiconductor layer130b, a transistor having high field-effect mobility can be obtained.

The thickness of the oxide semiconductor layer130ais greater than or equal to 3 nm and less than or equal to 100 nm, preferably greater than or equal to 5 nm and less than or equal to 50 nm, more preferably greater than or equal to 5 nm and less than or equal to 25 nm. The thickness of the oxide semiconductor layer130bis greater than or equal to 3 nm and less than or equal to 200 nm, preferably greater than or equal to 10 nm and less than or equal to 150 nm, more preferably greater than or equal to 15 nm and less than or equal to 100 nm. The thickness of the oxide semiconductor layer130cis greater than or equal to 1 nm and less than or equal to 50 nm, preferably greater than or equal to 2 nm and less than or equal to 30 nm, more preferably greater than or equal to 3 nm and less than or equal to 15 nm. In addition, the oxide semiconductor layer130bis preferably thicker than the oxide semiconductor layers130aand130c.

Note that in order that a transistor in which a channel is formed in an oxide semiconductor layer have stable electrical characteristics, it is effective to make the oxide semiconductor layer intrinsic or substantially intrinsic by reducing the concentration of impurities in the oxide semiconductor layer. The term “substantially intrinsic” refers to a state where an oxide semiconductor layer has a carrier density lower than 1×1017/cm3, lower than 1×1015/cm3, or lower than 1×1013/cm3.

In the oxide semiconductor layer, hydrogen, nitrogen, carbon, silicon, and a metal element other than main components of the oxide semiconductor layer are impurities. For example, hydrogen and nitrogen form donor levels to increase the carrier density, and silicon forms impurity levels in the oxide semiconductor layer. The impurity levels serve as traps and might cause deterioration of electrical characteristics of the transistor. Therefore, it is preferable to reduce the concentration of the impurities in the oxide semiconductor layers130ato130cand at interfaces between the oxide semiconductor layers.

In order to make the oxide semiconductor layer intrinsic or substantially intrinsic, the oxide semiconductor layer is controlled to have a region in which the concentration of silicon estimated by secondary ion mass spectrometry (SIMS) is lower than 1×1019atoms/cm3, preferably lower than 5×1018atoms/cm3, more preferably lower than 1×1018atoms/cm3. In addition, the oxide semiconductor layer is controlled to have a region in which the concentration of hydrogen is lower than or equal to 2×1020atoms/cm3, preferably lower than or equal to 5×1019atoms/cm3, more preferably lower than or equal to 1×1019atoms/cm3, still more preferably lower than or equal to 5×1018atoms/cm3. Furthermore, the concentration of nitrogen at a certain depth of the oxide semiconductor layer or in a region of the oxide semiconductor layer is lower than 5×1019atoms/cm3, preferably lower than or equal to 5×1018atoms/cm3, more preferably lower than or equal to 1×1018atoms/cm3, still more preferably lower than or equal to 5×1017atoms/cm3.

The high concentration of silicon or carbon might reduce the crystallinity of the oxide semiconductor layer. In order not to lower the crystallinity of the oxide semiconductor layer, for example, the oxide semiconductor layer is controlled to have a region in which the concentration of silicon is lower than 1×1019atoms/cm3, preferably lower than 5×1018atoms/cm3, more preferably lower than 1×1018atoms/cm3. Furthermore, the oxide semiconductor layer is controlled to have a region in which the concentration of carbon is lower than 1×1019atoms/cm3, preferably lower than 5×1018atoms/cm3, more preferably lower than b 1×1018atoms/cm3.

A transistor in which a highly purified oxide semiconductor film is used for a channel formation region exhibits extremely low off-state current. When voltage between a source and a drain is set at about 0.1 V, 5 V, or 10 V, for example, the off-state current per channel width of the transistor can be as low as several yoctoamperes per micrometer to several zeptoamperes per micrometer.

As the gate insulating film of the transistor, an insulating film containing silicon is used in many cases; thus, it is preferable that, as in the transistor in one embodiment of the present invention, a region of the oxide semiconductor layer that serves as a channel not be in contact with the gate insulating film for the above reason. In the case where a channel is formed at the interface between the gate insulating film and the oxide semiconductor layer, scattering of carriers occurs at the interface, so that the field-effect mobility of the transistor is reduced. Also from the view of the above, it is preferable that the region of the oxide semiconductor layer that serves as a channel be separated from the gate insulating film.

Accordingly, with the oxide semiconductor layer130having a layered structure including the oxide semiconductor layers130ato130c, a channel can be formed in the oxide semiconductor layer130b; thus, the transistor can have high field-effect mobility and stable electrical characteristics.

In a band structure, the conduction band minimums of the oxide semiconductor layers130ato130care continuous. This can be understood also from the fact that the compositions of the oxide semiconductor layers130ato130care close to one another and oxygen is easily diffused among the oxide semiconductor layers130ato130c. Thus, the oxide semiconductor layers130ato130chave a continuous physical property though they have different compositions and form a stack. In the drawings, interfaces between the oxide semiconductor layers of the stack are indicated by dotted lines.

The oxide semiconductor layer130in which layers containing the same main components are stacked is formed to have not only a simple layered structure of the layers but also a continuous energy band (here, in particular, a well structure having a U shape in which the conduction band minimums are continuous (U-shape well)). In other words, the layered structure is formed such that there exists no impurity that forms a defect level such as a trap center or a recombination center at each interface. If impurities exist between the stacked oxide semiconductor layers, the continuity of the energy band is lost and carriers disappear by a trap or recombination at the interface.

For example, an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:3:2, 1:3:3, 1:3:4, 1:3:6, 1:4:5, 1:6:4, or 1:9:6 can be used for the oxide semiconductor layers130aand130c, and an In—Ga—Zn oxide whose atomic ratio of In to Ga and Zn is 1:1:1, 2:1:3, 5:5:6, or 3:1:2 can be used for the oxide semiconductor layer130b. In each of the oxide semiconductor layers130ato130c, the proportion of each atom in the atomic ratio varies within a range of ±20% as a margin.

The oxide semiconductor layer130bof the oxide semiconductor layer130serves as a well, so that a channel is formed in the oxide semiconductor layer130b. Note that since the conduction band minimums are continuous, the oxide semiconductor layer130can also be referred to as a U-shaped well. Furthermore, a channel formed to have such a structure can also be referred to as a buried channel.

Note that trap levels due to impurities or defects might be formed in the vicinity of the interface between an insulating layer such as a silicon oxide film and each of the oxide semiconductor layers130aand130c. The oxide semiconductor layer130bcan be distanced away from the trap levels owing to existence of the oxide semiconductor layers130aand130c.

However, when the energy differences between the conduction band minimum of the oxide semiconductor layer130band the conduction band minimum of each of the oxide semiconductor layers130aand130care small, an electron in the oxide semiconductor layer130bmight reach the trap level by passing over the energy differences. When the electron is trapped in the trap level, negative charge is generated at the interface with the insulating layer, so that the threshold voltage of the transistor is shifted in a positive direction.

The oxide semiconductor layers130ato130cpreferably include crystal parts. In particular, when crystals with c-axis alignment are used, the transistor can have stable electrical characteristics. Moreover, crystals with c-axis alignment are resistant to bending; therefore, using such crystals can improve the reliability of a semiconductor device using a flexible substrate.

As the conductive layer140functioning as a source electrode layer and the conductive layer150functioning as a drain electrode layer, for example, a single layer or a stacked layer formed using a material selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, and Sc and alloys of any of these metal materials can be used. Typically, it is preferable to use Ti, which is particularly easily bonded to oxygen, or W, which has a high melting point and thus makes subsequent process temperatures comparatively high. It is also possible to use a stack of any of the above materials and Cu or an alloy such as Cu—Mn, which has low resistance. In the transistors105,106,111, and112, for example, it is possible to use W for the conductive layers141and151and use a stack of Ti and Al for the conductive layers142and152.

The above materials are capable of extracting oxygen from an oxide semiconductor layer. Therefore, in a region of the oxide semiconductor layer that is in contact with any of the above materials, oxygen is released from the oxide semiconductor layer and an oxygen vacancy is formed. Hydrogen slightly contained in the layer and the oxygen vacancy are bonded to each other, so that the region is changed to an n-type region. Accordingly, the n-type region can serve as a source or a drain of the transistor.

In the case where W is used for the conductive layers140and150, the conductive layers140and150may be doped with nitrogen. Doping with nitrogen can appropriately lower the capability of extracting oxygen and prevent the n-type region from spreading to a channel region. It is possible to prevent the n-type region from spreading to a channel region also by using a stack of W and an n-type semiconductor layer as the conductive layers140and150and putting the n-type semiconductor layer in contact with the oxide semiconductor layer. As the n-type semiconductor layer, an In—Ga—Zn oxide, zinc oxide, indium oxide, tin oxide, indium tin oxide, or the like to which nitrogen is added can be used.

The insulating layer160functioning as a gate insulating film can be formed using an insulating film containing one or more of aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer160may be a stack including any of the above materials. The insulating layer160may contain La, nitrogen, Zr, or the like as an impurity.

An example of a layered structure of the insulating layer160is described. The insulating layer160includes, for example, oxygen, nitrogen, silicon, or hafnium. Specifically, the insulating layer160preferably includes hafnium oxide and silicon oxide or silicon oxynitride.

Hafnium oxide and aluminum oxide have higher dielectric constants than silicon oxide and silicon oxynitride. Therefore, the insulating layer160using hafnium oxide or aluminum oxide can have larger thickness than the insulating layer160using silicon oxide, so that leakage current due to tunnel current can be reduced. That is, a transistor with low off-state current can be provided. Moreover, hafnium oxide with a crystalline structure has a higher dielectric constant than hafnium oxide with an amorphous structure. Therefore, it is preferable to use hafnium oxide with a crystalline structure in order to provide a transistor with low off-state current. Examples of the crystal structure include a monoclinic crystal structure and a cubic crystal structure. Note that one embodiment of the present invention is not limited to the above examples.

For the insulating layers120and160in contact with the oxide semiconductor layer130, a film that releases less nitrogen oxide is preferably used. For the insulating layers120and160, for example, a silicon oxynitride film or an aluminum oxynitride film that releases less nitrogen oxide can be used.

A silicon oxynitride film that releases less nitrogen oxide is a film of which the amount of released ammonia is larger than the amount of released nitrogen oxide in TDS; the amount of released ammonia is typically greater than or equal to 1×1018molecules/cm3and less than or equal to 5×1019molecules/cm3. Note that the amount of released ammonia is the amount of ammonia released by heat treatment with which the surface temperature of the film becomes higher than or equal to 50° C. and lower than or equal to 650° C., preferably higher than or equal to 50° C. and lower than or equal to 550° C.

By using the above oxide insulating layer for the insulating layers120and160, a shift in the threshold voltage of the transistor can be reduced, which leads to reduced fluctuations in the electrical characteristics of the transistor.

For the conductive layer170functioning as a gate electrode layer, for example, a conductive film formed using Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ru, Ag, Mn, Nd, Sc, Ta, W, or the like can be used. Alternatively, an alloy or a conductive nitride of any of these materials may be used. Alternatively, a stack of a plurality of materials selected from these materials, alloys of these materials, and conductive nitrides of these materials may be used. Typically, tungsten, a stack of tungsten and titanium nitride, a stack of tungsten and tantalum nitride, or the like can be used. Alternatively, Cu or an alloy such as Cu—Mn, which has low resistance, or a stack of any of the above materials and Cu or an alloy such as Cu—Mn may be used. In this embodiment, tantalum nitride is used for the conductive layer171and tungsten is used for the conductive layer172to form the conductive layer170.

As the insulating layer175, a silicon nitride film, an aluminum nitride film, or the like containing hydrogen can be used. In the transistors103,104,106,109,110, and112described in Embodiment 4, when an insulating film containing hydrogen is used as the insulating layer175, part of the oxide semiconductor layer can have n-type conductivity. In addition, a nitride insulating film functions as a blocking film against moisture and the like and can improve the reliability of the transistor.

An aluminum oxide film can also be used as the insulating layer175. It is particularly preferable to use an aluminum oxide film as the insulating layer175in the transistors101,102,105,107,108, and111described in Embodiment 4. The aluminum oxide film has a high blocking effect of preventing penetration of both oxygen and impurities such as hydrogen and moisture. Accordingly, during and after the manufacturing process of the transistor, the aluminum oxide film can suitably function as a protective film that has effects of preventing entry of impurities such as hydrogen and moisture into the oxide semiconductor layer130, preventing release of oxygen from the oxide semiconductor layer, and preventing unnecessary release of oxygen from the insulating layer120. Furthermore, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor layer.

Furthermore, the insulating layer180is preferably formed over the insulating layer175. The insulating layer180can be formed using an insulating film containing one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. The insulating layer180may be a stack of any of the above materials.

Here, like the insulating layer120, the insulating layer180preferably contains oxygen more than that in the stoichiometric composition. Oxygen released from the insulating layer180can be diffused into the channel formation region in the oxide semiconductor layer130through the insulating layer160, so that oxygen vacancies formed in the channel formation region can be filled with oxygen. In this manner, stable electrical characteristics of the transistor can be achieved.

High integration of a semiconductor device requires miniaturization of a transistor. However, it is known that miniaturization of a transistor causes deterioration of electrical characteristics of the transistor. In particular, a decrease in channel width causes a reduction in on-state current.

In the transistors107to112in one embodiment of the present invention, the oxide semiconductor layer130cis formed to cover the oxide semiconductor layer130bwhere a channel is formed; thus, a channel formation layer is not in contact with the gate insulating film. Accordingly, scattering of carriers at the interface between the channel formation layer and the gate insulating film can be reduced and the on-state current of the transistor can be increased.

In the transistor in one embodiment of the present invention, as described above, the gate electrode layer (the conductive layer170) is formed to electrically surround the oxide semiconductor layer130in the channel width direction; accordingly, a gate electric field is applied to the oxide semiconductor layer130in a direction perpendicular to its side surface in addition to a direction perpendicular to its top surface. In other words, a gate electric field is applied to the entire channel formation layer and effective channel width is increased, leading to a further increase in the on-state current.

Furthermore, in the transistor in one embodiment of the present invention in which the oxide semiconductor layer130has a two-layer structure or a three-layer structure, since the oxide semiconductor layer130bwhere a channel is formed is provided over the oxide semiconductor layer130a, an effect of making an interface state less likely to be formed is obtained. In the transistor in one embodiment of the present invention in which the oxide semiconductor layer130has a three-layer structure, since the oxide semiconductor layer130bis positioned at the middle of the three-layer structure, an effect of eliminating the influence of an impurity that enters from upper and lower layers on the oxide semiconductor layer130bis obtained as well. Therefore, the transistor can achieve not only the increase in the on-state current of the transistor but also stabilization of the threshold voltage and a reduction in the S value (subthreshold value). Thus, current when gate voltage VG is 0 V can be reduced and power consumption can be reduced. In addition, since the threshold voltage of the transistor becomes stable, long-term reliability of the semiconductor device can be improved. Furthermore, the transistor in one embodiment of the present invention is suitable for a highly integrated semiconductor device because deterioration of electrical characteristics due to miniaturization is reduced.

The structure described above in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

In this embodiment, methods for manufacturing the transistors101,107, and111described in Embodiment 4 are described.

First, a method for manufacturing a silicon transistor included in the substrate115is described. Here, an example of a method for manufacturing a p-ch transistor is described. An n−-type single crystal silicon substrate is used as a silicon substrate, and an element formation region isolated with an insulating layer (also referred to as a field oxide film) is formed in the surface. The element formation region can be formed by local oxidation of silicon (LOCOS), shallow trench isolation (STI), or the like.

Here, the substrate is not limited to the single crystal silicon substrate. A silicon on insulator (SOI) substrate or the like can also be used.

Next, a gate insulating film is formed to cover the element formation region. For example, a silicon oxide film is formed by oxidation of a surface of the element formation region by heat treatment. Furthermore, after the silicon oxide film is formed, a surface of the silicon oxide film may be nitrided by nitriding treatment.

Next, a conductive film is formed to cover the gate insulating film. The conductive film can be formed using an element selected from Ta, W, Ti, Mo, Al, Cu, Cr, Nb, and the like, or an alloy material or a compound material containing such an element as a main component. Alternatively, a metal nitride film obtained by nitriding of any of these elements can be used. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used.

Then, the conductive film is selectively etched, so that a gate electrode layer is formed over the gate insulating film.

Next, an insulating film such as a silicon oxide film or a silicon nitride film is formed to cover the gate electrode layer and etch back is performed, so that sidewalls are formed on side surfaces of the gate electrode layer.

Next, a resist mask is selectively formed to cover regions except the element formation region, and an impurity element is added using the resist mask and the gate electrode layer as masks, so that p+-type impurity regions are formed. Here, in order to form a p-ch transistor, an impurity element imparting p-type conductivity such as B or Ga can be used as the impurity element.

Through the above steps, a p-ch transistor including an active region in the silicon substrate is completed. Note that a passivation film such as a silicon nitride film or an aluminum oxide film is preferably formed over the transistor.

Next, an interlayer insulating film is formed over the silicon substrate where the transistor is formed, and contact plugs and wirings are formed.

A method for manufacturing the transistor101is described with reference toFIGS. 33A to 33CandFIGS. 34A to 34C. A cross section of the transistor in the channel length direction is shown on the left side, and a cross section of the transistor in the channel width direction is shown on the right side. The cross-sectional views in the channel width direction are enlarged views; therefore, components on the left side and those on the right side differ in apparent thickness.

The case where the oxide semiconductor layer130has a three-layer structure of the oxide semiconductor layers130ato130cis described as an example. In the case where the oxide semiconductor layer130has a two-layer structure, the oxide semiconductor layers130aand130bare used. In the case where the oxide semiconductor layer130has a single-layer structure, the oxide semiconductor layer130bis used.

First, the insulating layer120is formed over the substrate115. Embodiment 5 can be referred to for the kind of the substrate115and the material of the insulating layer120. The insulating layer120can be formed by sputtering, CVD, molecular beam epitaxy (MBE), or the like.

Oxygen may be added to the insulating layer120by ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, or the like. Adding oxygen enables the insulating layer120to supply oxygen much easily to the oxide semiconductor layer130.

In the case where a surface of the substrate115is made of an insulator and there is no influence of impurity diffusion on the oxide semiconductor layer130to be formed later, the insulating layer120is not necessarily provided.

Next, an oxide semiconductor film130A to be the oxide semiconductor layer130a, an oxide semiconductor film130B to be the oxide semiconductor layer130b, and an oxide semiconductor film130C to be the oxide semiconductor layer130care formed over the insulating layer120by sputtering, CVD, MBE, or the like (seeFIG. 33A).

In the case where the oxide semiconductor layer130has a layered structure, oxide semiconductor films are preferably formed successively without exposure to the air with the use of a multi-chamber deposition apparatus (e.g., a sputtering apparatus) including a load lock chamber. It is preferable that each chamber of the sputtering apparatus be able to be evacuated to a high vacuum (approximately 5×10−7to 1×10−4Pa) by an adsorption vacuum evacuation pump such as a cryopump and that the chamber be able to heat the substrate to higher than or equal to 100° C., preferably higher than or equal to 500° C., so that water and the like serving as impurities of an oxide semiconductor are removed as much as possible. Alternatively, the combination of a turbo molecular pump and a cold trap is preferably used to prevent back-flow of a gas containing a carbon component, moisture, or the like from an exhaust system into the chamber. Alternatively, the combination of a turbo molecular pump and a cryopump may be used as an exhaust system.

Not only high vacuum evacuation of the chamber but also high purity of a sputtering gas is preferred to obtain a highly purified intrinsic oxide semiconductor. As an oxygen gas or an argon gas used for a sputtering gas, a gas which is highly purified to have a dew point of −40° C. or lower, preferably −80° C. or lower, more preferably −100° C. or lower is used, so that entry of moisture or the like into the oxide semiconductor film can be prevented as much as possible.

For the oxide semiconductor films130A to130C, any of the materials described in Embodiment 5 can be used. In the case where sputtering is used for deposition, any of the materials described in Embodiment 5 can be used as a target.

Note that as described in detail in Embodiment 5, a material that has a higher electron affinity than the oxide semiconductor films130A and130C is used for the oxide semiconductor film130B.

The oxide semiconductor films are preferably formed by sputtering. As sputtering, RF sputtering, DC sputtering, AC sputtering, or the like can be used.

After the oxide semiconductor film130C is formed, first heat treatment may be performed. The first heat treatment may be performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas at 10 ppm or more, or a reduced pressure state. Alternatively, the first heat treatment may be performed in such a manner that heat treatment is performed in an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, in order to compensate released oxygen. The first heat treatment can increase the crystallinity of the oxide semiconductor films130A to130C and remove impurities such as water and hydrogen from the insulating layer120and the oxide semiconductor films130A to130C. Note that the first heat treatment may be performed after etching for forming the oxide semiconductor layers130ato130cdescribed later.

Next, a conductive layer is formed over the oxide semiconductor film130C. The conductive layer can be, for example, formed by the following method.

First, a first conductive film is formed over the oxide semiconductor film130C. As the first conductive film, a single layer or a stacked layer can be formed using a material selected from Al, Cr, Cu, Ta, Ti, Mo, W, Ni, Mn, Nd, and Sc and an alloy of any of these metal materials.

Next, a resist film is formed over the first conductive film and the resist film is exposed to light by electron beam exposure, liquid immersion exposure, or EUV exposure and developed, so that a first resist mask is formed. An organic coating film is preferably formed as an adherence agent between the first conductive film and the resist film. Alternatively, the first resist mask may be formed by nanoimprint lithography.

Then, the first conductive film is selectively etched using the first resist mask and the first resist mask is subjected to ashing; thus, the conductive layer is formed.

Next, the oxide semiconductor films130A to130C are selectively etched using the conductive layer as a hard mask and the conductive layer is removed; thus, the oxide semiconductor layer130including a stack of the oxide semiconductor layers130ato130cis formed (seeFIG. 33B). It is also possible to form the oxide semiconductor layer130using the first resist mask, without forming the conductive layer. Here, oxygen ions may be implanted into the oxide semiconductor layer130.

Next, a second conductive film is formed to cover the oxide semiconductor layer130. The second conductive film can be formed using a material that can be used for the conductive layers140and150described in Embodiment 5. Sputtering, CVD, MBE, or the like can be used for the formation of the second conductive film.

Then, a second resist mask is formed over portions to be a source region and a drain region. Then, part of the second conductive film is etched, so that the conductive layers140and150are formed (seeFIG. 33C).

Next, an insulating film160A is formed over the oxide semiconductor layer130and the conductive layers140and150. The insulating film160A can be formed using a material that can be used for the insulating layer160described in Embodiment 5. Sputtering, CVD, MBE, or the like can be used for the formation of the insulating film160A.

After that, second heat treatment may be performed. The second heat treatment can be performed in a condition similar to that of the first heat treatment. The second heat treatment can make oxygen diffuse from the insulating layer120into the entire oxide semiconductor layer130. Note that it is possible to obtain this effect by third heat treatment, without performing the second heat treatment.

Then, a third conductive film171A and a fourth conductive film172A to be the conductive layer170are formed over the insulating film160A. The third conductive film171A and the fourth conductive film172A can be formed using materials that can be used for the conductive layers171and172described in Embodiment 5. Sputtering, CVD, MBE, or the like can be used for the formation of the third conductive film171A and the fourth conductive film172A.

Next, a third resist mask156is formed over the fourth conductive film172A (seeFIG. 34A). The third conductive film171A, the fourth conductive film172A, and the insulating film160A are selectively etched using the third resist mask156, so that the conductive layer170including the conductive layers171and172and the insulating layer160are formed (seeFIG. 34B). Note that if the insulating film160A is not etched, the transistor102can be manufactured.

After that, the insulating layer175is formed over the oxide semiconductor layer130, the conductive layers140and150, the insulating layer160, and the conductive layer170. Embodiment 5 can be referred to for the material of the insulating layer175. In the transistor101, an aluminum oxide film is preferably used. The insulating layer175can be formed by sputtering, CVD, MBE, or the like.

Next, the insulating layer180is formed over the insulating layer175(seeFIG. 34C). Embodiment 5 can be referred to for the material of the insulating layer180. The insulating layer180can be formed by sputtering, CVD, MBE, or the like.

Oxygen may be added to the insulating layer175and/or the insulating layer180by ion implantation, ion doping, plasma immersion ion implantation, plasma treatment, or the like. Adding oxygen enables the insulating layer175and/or the insulating layer180to supply oxygen much easily to the oxide semiconductor layer130.

Next, the third heat treatment may be performed. The third heat treatment can be performed in a condition similar to that of the first heat treatment. By the third heat treatment, excess oxygen is easily released from the insulating layers120,175, and180, so that oxygen vacancies in the oxide semiconductor layer130can be reduced.

Next, a method for manufacturing the transistor107is described. Note that detailed description of steps similar to those for manufacturing the transistor102described above is omitted.

The insulating layer120is formed over the substrate115, and the oxide semiconductor film130A to be the oxide semiconductor layer130aand the oxide semiconductor film130B to be the oxide semiconductor layer130bare formed over the insulating layer120by sputtering, CVD, MBE, or the like (seeFIG. 35A).

After that, a first conductive film is formed over the oxide semiconductor film130B, and a conductive layer is formed using a first resist mask by a method similar to the above method. Then, the oxide semiconductor films130A and130B are selectively etched using the conductive layer as a hard mask and the conductive layer is removed; thus, a stack of the oxide semiconductor layers130aand130bis formed (seeFIG. 35B). It is also possible to form the stack using the first resist mask, without forming the hard mask. Here, oxygen ions may be implanted into the oxide semiconductor layers130aand130b.

Next, a second conductive film is formed to cover the stack. Then, a second resist mask is formed over portions to be a source region and a drain region, and part of the second conductive film is etched using the second resist mask, so that the conductive layers140and150are formed (seeFIG. 35C).

After that, the oxide semiconductor film130C to be the oxide semiconductor layer130cis formed over the stack of the oxide semiconductor layers130aand130band the conductive layers140and150. Furthermore, the insulating film160A, the third conductive film171A, and the fourth conductive film172A are formed over the oxide semiconductor film130C.

Then, the third resist mask156is formed over the fourth conductive film172A (seeFIG. 36A). The third conductive film171A, the fourth conductive film172A, the insulating film160A, and the oxide semiconductor film130C are selectively etched using the resist mask, so that the conductive layer170including the conductive layers171and172, the insulating layer160, and the oxide semiconductor layer130care formed (seeFIG. 36B). Note that when the insulating film160A and the oxide semiconductor film130C are etched using a fourth resist mask, the transistor108can be manufactured.

Next, the insulating layers175and180are formed over the insulating layer120, the oxide semiconductor layer130(the oxide semiconductor layers130ato130c), the conductive layers140and150, the insulating layer160, and the conductive layer170(seeFIG. 36C).

Through the above steps, the transistor107can be manufactured.

Next, a method for manufacturing the transistor111is described. Note that detailed description of steps similar to those for manufacturing the transistor102described above is omitted.

The insulating layer120is formed over the substrate115, and the oxide semiconductor film130A to be the oxide semiconductor layer130aand the oxide semiconductor film130B to be the oxide semiconductor layer130bare formed over the insulating layer120by sputtering, CVD, MBE, or the like. Then, a first conductive film is formed over the oxide semiconductor film130B, and a conductive layer141ais formed using a first resist mask (seeFIG. 37A).

Then, the oxide semiconductor films130A and130B are selectively etched using the conductive layer141aas a hard mask, so that a stack of the oxide semiconductor layers130aand130band the conductive layer141ais formed (seeFIG. 37B). Here, oxygen ions may be implanted into the oxide semiconductor layers130aand130b.

Then, a second resist mask is formed over portions to be a source region and a drain region, and part of the conductive layer141ais etched using the second resist mask, so that the conductive layers141and151are formed (seeFIG. 37C).

After that, the oxide semiconductor film130C to be the oxide semiconductor layer130cis formed over the stack of the oxide semiconductor layers130aand130band the conductive layers141and151. Furthermore, the insulating film160A, the third conductive film171A, and the fourth conductive film172A are formed over the oxide semiconductor film130C.

Then, the third resist mask156is formed over the fourth conductive film172A (seeFIG. 38A). The third conductive film171A, the fourth conductive film172A, the insulating film160A, and the oxide semiconductor film130C are selectively etched using the third resist mask156, so that the conductive layer170including the conductive layers171and172, the insulating layer160, and the oxide semiconductor layer130care formed (seeFIG. 38B).

Next, the insulating layers175and180are formed over the insulating layer120, the oxide semiconductor layer130(the oxide semiconductor layers130ato130c), the conductive layers140and150, the insulating layer160, and the conductive layer170.

Next, openings reaching the conductive layers141and151are provided in the insulating layers175and180, and a fifth conductive film is formed to cover the openings. Then, a fourth resist mask is provided over the fifth conductive film and the fifth conductive film is selectively etched using the resist mask, so that the conductive layers142and152are formed (seeFIG. 38C).

Through the above steps, the transistor111can be manufactured.

Although the variety of films such as the metal films, the semiconductor films, and the inorganic insulating films that are described in this embodiment typically can be formed by sputtering or plasma-enhanced CVD, such films may be formed by another method such as thermal CVD. Examples of thermal CVD include metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD).

Since plasma is not used for deposition, thermal CVD has an advantage that no defect due to plasma damage is generated.

Deposition by thermal CVD may be performed in such a manner that a source gas and an oxidizer are supplied to the chamber at the same time, the pressure in the chamber is set to an atmospheric pressure or a reduced pressure, and reaction is caused in the vicinity of the substrate or over the substrate.

Deposition by ALD is performed in such a manner that the pressure in a chamber is set to an atmospheric pressure or a reduced pressure, source gases for reaction are introduced into the chamber and reacted, and then the sequence of gas introduction is repeated. An inert gas (e.g., argon or nitrogen) may be introduced as a carrier gas with the source gases. For example, two or more kinds of source gases may be sequentially supplied to the chamber. In that case, after reaction of a first source gas, an inert gas is introduced, and then a second source gas is introduced so that the source gases are not mixed. Alternatively, the first source gas may be exhausted by vacuum evacuation instead of introduction of the inert gas, and then the second source gas may be introduced. The first source gas is adsorbed on the surface of the substrate and reacted to form a first layer, and then, the second source gas introduced is absorbed and reacted. As a result, a second layer is stacked over the first layer, so that a thin film is formed. The sequence of gas introduction is controlled and repeated more than once until desired thickness is obtained, so that a thin film with excellent step coverage can be formed. The thickness of the thin film can be adjusted by the number of repetition times of the sequence of gas introduction; therefore, ALD makes it possible to accurately adjust thickness and thus is suitable for manufacturing a minute FET.

The variety of films such as the metal film, the semiconductor film, and the inorganic insulating film that have been disclosed in the embodiments can be formed by thermal CVD such as MOCVD or ALD. For example, in the case where an In—Ga—Zn—O film is formed, trimethylindium (In(CH3)3), trimethylgallium (Ga(CH3)3), and dimethylzinc (Zn(CH3)2) can be used. The chemical formula of trimethylgallium is Ga(CH3)3. Without limitation to the above combination, triethylgallium (Ga(C2H5)3) can be used instead of trimethylgallium and diethylzinc (Zn(C2H5)2) can be used instead of dimethylzinc.

For example, in the case where a hafnium oxide film is formed by a deposition apparatus using ALD, two kinds of gases, i.e., ozone (O3) as an oxidizer and a source material gas which is obtained by vaporizing liquid containing a solvent and a hafnium precursor (hafnium alkoxide and a hafnium amide such as hafnium tetrakis(dimethylamide)hafnium (TDMAH, Hf[N(CH3)2]4) and tetrakis(ethylmethylamide)hafnium) are used. Note that the chemical formula of tetrakis(dimethylamide)hafnium is Hf[N(CH3)2]4. Examples of another material liquid include tetrakis(ethylmethylamide)hafnium.

For example, in the case where an aluminum oxide film is formed by a deposition apparatus using ALD, two kinds of gases, i.e., H2O as an oxidizer and a source gas which is obtained by vaporizing liquid containing a solvent and an aluminum precursor (e.g., trimethylaluminum (TMA, Al(CH3)3)) are used. Examples of another material include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate).

For example, in the case where a silicon oxide film is formed by a deposition apparatus using ALD, hexachlorodisilane is adsorbed on a surface where a film is to be formed, and radicals of an oxidizing gas (e.g., O2or dinitrogen monoxide) are supplied to react with an adsorbate.

For example, in the case where a tungsten film is formed by a deposition apparatus using ALD, a WF6gas and a B2H6gas are sequentially introduced to form an initial tungsten film, and then a WF6gas and an H2gas are sequentially introduced to form a tungsten film. Note that an SiH4gas may be used instead of a B2H6gas.

For example, in the case where an oxide semiconductor film, e.g., an In—Ga—Zn—O film is formed by a deposition apparatus using ALD, an In(CH3)3gas and an O3gas are sequentially introduced to form an In—O layer, a Ga(CH3)3gas and an O3gas are sequentially introduced to form a Ga—O layer, and then a Zn(CH3)2gas and an O3gas are sequentially introduced to form a Zn—O layer. Note that the order of these layers is not limited to this example. A mixed compound layer such as an In—Ga—O layer, an In—Zn—O layer, or a Ga—Zn—O layer may be formed by using these gases. Although an H2O gas which is obtained by bubbling with an inert gas such as Ar may be used instead of an O3gas, it is preferable to use an O3gas, which does not contain H.

The structure described above in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

The structure of an oxide semiconductor film that can be used for one embodiment of the present invention is described below.

In this specification, the trigonal and rhombohedral crystal systems are included in the hexagonal crystal system.

An oxide semiconductor film is roughly classified into a non-single-crystal oxide semiconductor film and a single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film means any of a c-axis aligned crystalline oxide semiconductor (CAAC-OS) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, and the like.

First, a CAAC-OS film is described.

The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis aligned crystal parts.

With a transmission electron microscope (TEM), a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of the CAAC-OS film is observed. Consequently, a plurality of crystal parts are observed clearly. However, in the high-resolution TEM image, a boundary between crystal parts, i.e., a grain boundary is not observed clearly. Thus, in the CAAC-OS film, a reduction in electron mobility due to the grain boundary is less likely to occur.

According to the high-resolution cross-sectional TEM image of the CAAC-OS film observed in a direction substantially parallel to a sample surface (cross-sectional TEM image), metal atoms are arranged in a layered manner in the crystal parts. Each metal atom layer has a morphology that reflects a surface over which the CAAC-OS film is formed (also referred to as a formation surface) or a top surface of the CAAC-OS film, and is provided parallel to the formation surface or the top surface of the CAAC-OS film.

On the other hand, according to the high-resolution planar TEM image of the CAAC-OS film observed in a direction substantially perpendicular to the sample surface (planar TEM image), metal atoms are arranged in a triangular or hexagonal configuration in the crystal parts. However, there is no regularity of arrangement of metal atoms between different crystal parts.

The CAAC-OS film is an oxide semiconductor film having low impurity concentration. The impurity is an element other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element that has higher bonding strength to oxygen than a metal element included in the oxide semiconductor film, such as silicon, disturbs the atomic order of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen and causes a decrease in crystallinity. Furthermore, a heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (molecular radius), and thus disturbs the atomic order of the oxide semiconductor film and causes a decrease in crystallinity when it is contained in the oxide semiconductor film. Note that the impurity contained in the oxide semiconductor film might serve as a carrier trap or a carrier generation source.

The CAAC-OS film is an oxide semiconductor film having low density of defect states. In some cases, oxygen vacancies in the oxide semiconductor film serve as carrier traps or serve as carrier generation sources when hydrogen is captured therein.

The state in which impurity concentration is low and density of defect states is low (the number of oxygen vacancies is small) is referred to as “highly purified intrinsic” or “substantially highly purified intrinsic.” A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have low carrier density. Thus, a transistor including the oxide semiconductor film rarely has negative threshold voltage (is rarely normally on). The highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Accordingly, the transistor including the oxide semiconductor film has few variations in electrical characteristics and high reliability. Charge trapped by the carrier traps in the oxide semiconductor film takes a long time to be released and may behave like fixed charge. Thus, the transistor that includes the oxide semiconductor film having high impurity concentration and high density of defect states has unstable electrical characteristics in some cases.

In a transistor including the CAAC-OS film, changes in electrical characteristics of the transistor due to irradiation with visible light or ultraviolet light are small.

Next, a microcrystalline oxide semiconductor film is described.

A microcrystalline oxide semiconductor film has a region where a crystal part is observed in a high-resolution TEM image and a region where a crystal part is not clearly observed in a high-resolution TEM image. In most cases, a crystal part in the microcrystalline oxide semiconductor film is greater than or equal to 1 nm and less than or equal to 100 nm, or greater than or equal to 1 nm and less than or equal to 10 nm. A microcrystal with a size greater than or equal to 1 nm and less than or equal to 10 nm, or a size greater than or equal to 1 nm and less than or equal to 3 nm is specifically referred to as nanocrystal (nc). An oxide semiconductor film including nanocrystal is referred to as a nanocrystalline oxide semiconductor (nc-OS) film. In a high-resolution TEM image, a crystal grain boundary cannot be found clearly in the nc-OS film in some cases.

In the nc-OS film, a microscopic region (e.g., a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has periodic atomic order. There is no regularity of crystal orientation between different crystal parts in the nc-OS film. Thus, the orientation of the whole film is not observed. Accordingly, in some cases, the nc-OS film cannot be distinguished from an amorphous oxide semiconductor film depending on an analysis method. For example, when the nc-OS film is subjected to structural analysis by an out-of-plane method with an XRD apparatus using an X-ray having a diameter larger than that of a crystal part, a peak that shows a crystal plane does not appear. Furthermore, a halo pattern is shown in a selected-area electron diffraction pattern of the nc-OS film obtained by using an electron beam having a probe diameter larger than the diameter of a crystal part (e.g., larger than or equal to 50 nm). Meanwhile, spots are shown in a nanobeam electron diffraction pattern of the nc-OS film obtained by using an electron beam having a probe diameter close to or smaller than the diameter of a crystal part. Furthermore, in a nanobeam electron diffraction pattern of the nc-OS film, circumferentially distributed spots are observed in some cases. Also in a nanobeam electron diffraction pattern of the nc-OS film, a plurality of spots are shown in a ring-like region in some cases.

The nc-OS film is an oxide semiconductor film that has high regularity than an amorphous oxide semiconductor film. Thus, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. Note that there is no regularity of crystal orientation between different crystal parts in the nc-OS film; thus, the nc-OS film has a higher density of defect states than the CAAC-OS film.

Next, an amorphous oxide semiconductor film is described.

The amorphous oxide semiconductor film has disordered atomic arrangement and no crystal part. For example, the amorphous oxide semiconductor film does not have a specific state as in quartz.

In a high-resolution TEM image of the amorphous oxide semiconductor film, crystal parts cannot be found.

When the amorphous oxide semiconductor film is subjected to structural analysis by an out-of-plane method with an XRD apparatus, a peak which shows a crystal plane does not appear. A halo pattern is shown in an electron diffraction pattern of the amorphous oxide semiconductor film. Furthermore, a halo pattern is shown but a spot is not shown in a nanobeam electron diffraction pattern of the amorphous oxide semiconductor film.

Note that an oxide semiconductor film may have a structure having physical properties between the nc-OS film and the amorphous oxide semiconductor film. The oxide semiconductor film having such a structure is specifically referred to as an amorphous-like oxide semiconductor (a-like OS) film.

In a high-resolution TEM image of the a-like OS film, a void may be seen. Furthermore, in the high-resolution TEM image, there are a region where a crystal part is clearly observed and a region where a crystal part is not observed. In the a-like OS film, crystallization by a slight amount of electron beam used for TEM observation occurs and growth of the crystal part is found sometimes. In contrast, crystallization by a slight amount of electron beam used for TEM observation is less observed in the nc-OS film having good quality.

Note that the crystal part size in the a-like OS film and the nc-OS film can be measured using high-resolution TEM images. For example, an InGaZnO4crystal has a layered structure in which two Ga—Zn—O layers are included between In—O layers. A unit cell of the InGaZnO4crystal has a structure in which nine layers of three In—O layers and six Ga—Zn—O layers are layered in the c-axis direction. Accordingly, the spacing between these adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as a d value). The value is calculated to be 0.29 nm from crystal structure analysis. Thus, each of the lattice fringes in which the spacing therebetween is from 0.28 nm to 0.30 nm corresponds to the a-b plane of the InGaZnO4crystal, focusing on the lattice fringes in the high-resolution TEM image.

Note that an oxide semiconductor film may be a stacked film including two or more films of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

The structure described above in this embodiment can be combined with any of the structures described in the other embodiments as appropriate.

An imaging device in one embodiment of the present invention and a semiconductor device including the imaging device can be used for display devices, personal computers, or image reproducing devices provided with recording media (typically, devices that reproduce the content of recording media such as digital versatile discs (DVD) and have displays for displaying the reproduced images). Furthermore, as electronic devices that can include the imaging device in one embodiment of the present invention and the semiconductor device including the imaging device, cellular phones, game machines (including portable game machines), portable information terminals, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head mounted displays), navigation systems, audio reproducing devices (e.g., car audio systems and digital audio players), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATM), vending machines, and the like can be given.FIGS. 39A to 39Fillustrate specific examples of these electronic devices.

FIG. 39Aillustrates a portable game machine, which includes housings901and902, display portions903and904, a microphone905, speakers906, an operation key907, a stylus908, a camera909, and the like. Although the portable game machine inFIG. 39Ahas the two display portions903and904, the number of display portions included in the portable game machine is not limited to this. The imaging device in one embodiment of the present invention can be used for the camera909.

FIG. 39Billustrates a portable data terminal, which includes a first housing911, a display portion912, a camera919, and the like. The touch panel function of the display portion912enables input and output of information. The imaging device in one embodiment of the present invention can be used for the camera919.

FIG. 39Cillustrates a digital camera, which includes a housing921, a shutter button922, a microphone923, a light-emitting portion927, a lens925, and the like. The imaging device in one embodiment of the present invention can be provided in a focus position of the lens925.

FIG. 39Dillustrates a wrist-watch-type information terminal, which includes a housing931, a display portion932, a wristband933, a camera939, and the like. The display portion932may be a touch panel. The imaging device in one embodiment of the present invention can be used for the camera939.

FIG. 39Eillustrates a video camera, which includes a first housing941, a second housing942, a display portion943, operation keys944, a lens945, a joint946, and the like. The operation keys944and the lens945are provided for the first housing941, and the display portion943is provided for the second housing942. The first housing941and the second housing942are connected to each other with the joint946, and an angle between the first housing941and the second housing942can be changed with the joint946. An image displayed on the display portion943may be switched in accordance with the angle between the first housing941and the second housing942at the joint946. The imaging device in one embodiment of the present invention can be provided in a focus position of the lens945.

FIG. 39Fillustrates a cellular phone, which includes a display portion952, a microphone957, a speaker954, a camera959, an input/output terminal956, an operation button955, and the like in a housing951. The imaging device in one embodiment of the present invention can be used for the camera959.

Note that this embodiment can be combined with any of the other embodiments described in this specification as appropriate.

REFERENCE NUMERALS

This application is based on Japanese Patent Application serial no. 2014-178212 filed with Japan Patent Office on Sep. 2, 2014, the entire contents of which are hereby incorporated by reference.