Motor driving device

A motor driving device includes a microcomputer, a command voltage adjusting circuit, and a driving IC. The command voltage adjusting circuit converts a first command voltage signal from the microcomputer to a second command voltage signal. The driving IC generates a drive pulse based on the second command voltage signal. An upper and a lower limit of an input voltage range of the driving IC are larger than an upper and a lower limit of a voltage range of the first command voltage signal, respectively.

CROSS REFERENCE TO RELATED APPLICATION

The present invention claims priority under 35 U.S.C. §119 to Japanese Application No. 2013-176216 filed Aug. 28, 2013, the entire content of which is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to a motor driving device.

BACKGROUND

Conventionally, there is known a motor driving device that includes a microcomputer having a CPU, a driving IC for generating drive pulses in response to a signal transmitted from the CPU, and an inverter for supplying a driving current to a motor in response to the drive pulses transmitted from the driving IC.

A motor control system employed in the conventional motor driving device is disclosed in, e.g., Japanese Patent Application Publication No. 2010-22150. In the motor control system of Japanese Patent Application Publication No. 2010-22150, a PWM signal output unit corresponding to the driving IC is mounted together with a microcomputer having a CPU on the same chip (see paragraphs 0009 and 0014).

If the driving IC is mounted together with the microcomputer on the same chip as in the motor control system disclosed in Japanese Patent Application Publication No. 2010-22150, the chip including the microcomputer and the driving IC needs to be replaced as a whole in order to implement different variations depending on the kind and purpose of a motor. Meanwhile, if the driving IC and the microcomputer are installed independently of each other, the variations of a motor driving device can be broadened by combining different kinds of driving ICs and different kinds of microcomputers. Therefore, in order to implement different variations, it is preferable to install the driving IC and the microcomputer independently of each other.

However, when the driving IC and the microcomputer are installed independently of each other, it is sometimes the case that the output voltage range of the microcomputer and the input voltage range of the driving IC differ from each other. In that case, if the voltage signal outputted from the microcomputer is directly inputted to the driving IC, the input voltage range of the driving IC cannot be used in its entirety. Thus, the operation of the motor is limited. In particular, if the upper limit and the lower limit of the output voltage range of the microcomputer are respectively different from the upper limit and the lower limit of the input voltage, a reduction in the resolution of a voltage signal cannot be avoided by merely adjusting the magnification of the output voltage of the microcomputer.

At least an embodiment of the present invention provides a motor driving device capable of suppressing a reduction in the resolution of a voltage signal supplied from a microcomputer to a driving IC.

SUMMARY

At least an embodiment of the present invention a motor driving device for driving a motor, which includes a microcomputer, a command voltage adjusting circuit, a driving IC and an inverter. The microcomputer is configured to, based on a rotation command signal inputted from the outside, output a first command voltage signal which falls within a predetermined voltage range. The command voltage adjusting circuit is configured to convert the first command voltage signal to a second command voltage signal which falls within a voltage range differing from the predetermined voltage range. The driving IC is configured to, based on the second command voltage signal, generate a drive pulse. The inverter is configured to, based on the drive pulse, supply a drive current to the motor. An upper limit of an input voltage range of the driving IC is larger than an upper limit of the predetermined voltage range of the first command voltage signal, and a lower limit of the input voltage range of the driving IC is larger than a lower limit of the predetermined voltage range of the first command voltage signal. Further, the command voltage adjusting circuit is configured to set an upper limit of the second command voltage signal to become larger than the upper limit of the first command voltage signal and equal to or larger than the upper limit of the input voltage range of the driving IC and is configured to set a lower limit of the second command voltage signal to become larger than the lower limit of the first command voltage signal and equal to or smaller than the lower limit of the input voltage range of the driving IC.

In accordance with the illustrative embodiment, the command voltage adjusting circuit shifts the upper and the lower limit of the first command voltage signal outputted from the microcomputer. This makes it possible to narrow the voltage range falling outside the input voltage range of the driving IC among the voltage range of the second command voltage signal inputted to the driving IC. As a result, it is possible to suppress a reduction in the resolution of the signal inputted to the driving IC.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Embodiments of the present invention will now be described with reference to the drawings which form a part hereof.

First, description will be made on the overall configuration of a motor driving device1.FIG. 1is a block diagram conceptually illustrating the configuration of the motor driving device1.FIG. 2is a circuit diagram of a command voltage adjusting circuit4. The motor driving device1is a device that drives a motor9by supplying a drive current to the motor9.

In one embodiment of the present invention, the motor9to be driven by the motor driving device1is a three-phase brushless DC motor. The motor9preferably includes stator coils of individual phases, namely a U-phase, a V-phase and a W-phase. If a drive current is supplied to the stator coils of individual phases, torque is generated between a stator and a rotor. Thus, the rotor is rotationally driven. Alternatively, the motor to be driven by the motor driving device according to one embodiment of the present invention may be a single-phase motor or a brush motor.

The motor9preferably includes a position detector91. The position detector91detects the position of the rotor of the motor9and delivers the detection result as a position information signal S91to the motor driving device1. The position detector91detects the position of the rotor by, e.g., combining the signals outputted from three magnetic sensors arranged at an interval of 120 degrees in electric angle.

As shown inFIG. 1, the motor driving device1preferably includes a converter unit2, a microcomputer3, a command voltage adjusting circuit4, a driving IC5, an inverter6and an abnormality detecting unit7.

The converter unit2preferably includes an AC/DC converter circuit21. The converter unit2converts an AC voltage S11inputted from an external AC voltage source11to a DC voltage. The converter unit2generates a control voltage S2from the DC voltage and outputs the control voltage S2to the microcomputer3. In the present preferred embodiment, the motor driving device1includes the converter unit2, so that the motor9, which is a brushless DC motor, can be driven with an AC power source.

As shown inFIG. 2, the microcomputer3preferably includes a command voltage determining unit30, a command voltage generating unit31, an offset instructing unit32and an offset voltage source33. The microcomputer3outputs a first command voltage signal S31and an ON/OFF signal S32based on a rotation command signal S10inputted from the outside of the motor driving device1and a position information signal S91for the rotor of the motor9, which will be described later.

The command voltage determining unit30determines a count number S30, which corresponds to a voltage of the first command voltage signal S31based on the rotation command signal S10and the position information signal S91. Then, the command voltage determining unit30outputs the count number S30to the command voltage generating unit31, the offset instructing unit32and a stop signal generating unit73to be described later.

Based on the count number S30, the command voltage generating unit31generates the first command voltage signal S31. The command voltage generating unit31of the present preferred embodiment is a D/A converter that generates the first command voltage signal S31by digital-to-analog (D/A) converting the count number S30.FIG. 3is a graph representing the relationship between the count number S30and the first command voltage signal S31. In the present preferred embodiment, the count number S30is indicated by 8 bits and 256 counts. Therefore, the count number S30takes a value of 0 to 255 cnt.

While the command voltage generating unit31of the present preferred embodiment is a D/A converter that directly outputs an analog voltage, the present invention is not limited thereto. For example, the command voltage generating unit31may be configured to, based on the count number S30, generate a PWM signal as the first command voltage signal S31. In this case, there is provided a configuration in which the PWM signal is converted to an analog voltage by integrating the PWM signal with a CR integration circuit (not shown) inserted between the command voltage determining unit31and the input end of a third resistor R3of an adder circuit42to be described later.

The first command voltage signal S31is a voltage signal which falls within a predetermined voltage range. In the present preferred embodiment, the voltage range of the first command voltage signal S31is from 0 V to 5V. As shown inFIG. 3, the command voltage generating unit31generates the first command voltage signal S31proportional to the count number S30such that the first command voltage signal S31becomes 0 V when the count number S30is 0 cnt and such that the first command voltage signal S31becomes 5 V when the count number S30is 255 cnt.

The offset instructing unit32outputs an ON/OFF signal S32to an offset circuit41based on the count number S30inputted from the command voltage deciding unit30. Thus, the offset instructing unit32instructs the offset circuit41whether to generate an offset voltage S41or not. When the count number S30is not inputted, the ON/OFF signal S32becomes an OFF signal which is a voltage signal of a voltage higher than 0 V. When the count number S30is inputted, the ON/OFF signal S32becomes an ON signal which is a voltage signal of 0 V.

The offset voltage source33supplies a normal voltage S33normally outputted during the operation of the microcomputer3to a first voltage-dividing circuit411to be described later. In the present preferred embodiment, the normal voltage S33is 5 V.

The command voltage adjusting circuit4is a circuit that converts the first command voltage signal S31outputted from the microcomputer3to a second command voltage signal S43depending on the input voltage range of the driving IC5. As shown inFIG. 1, the command voltage adjusting circuit4preferably includes the offset circuit41, the adder circuit42and a magnification converting circuit43.

FIG. 4is a graph representing the relationship between the second command voltage signal S43inputted to the driving IC5and an output duty of a drive pulse S5outputted from the driving IC5. In the present preferred embodiment, as shown inFIG. 4, the input voltage range of the driving IC5is from 2.1 V to 5.4 V. That is, the upper limit, 5.4 V, of the input voltage range of the driving IC5is larger than the upper limit, 5 V, of the voltage range of the first command voltage signal S31. Moreover, the lower limit, 2.1 V, of the input voltage range of the driving IC5is larger than the lower limit, 0 V, of the voltage range of the first command voltage signal S31.

The command voltage adjusting circuit4is a voltage adjusting circuit that converts a first command voltage signal S31having a voltage range of 0 to 5 V to a second command voltage signal S43having a voltage range of 1.9 to 5.6 V. In the present preferred embodiment, taking the manufacturing error of the driving IC into account, the upper and the lower limit of the voltage range of the second command voltage signal S43are set at the values more affordable than the upper and the lower limit of the input voltage range as the rated values of the driving IC5.

In this way, the command voltage adjusting circuit4sets the upper limit of the second command voltage signal S43to become 5.6 V which is higher than the upper limit, 5 V, of the first command voltage signal S31and which is higher than the upper limit, 5.4 V, of the input voltage range of the driving IC5. Moreover, the command voltage adjusting circuit4sets the lower limit of the second command voltage signal S43to become 1.9 V which is higher than the lower limit, 0 V, of the first command voltage signal S31and which is lower than the lower limit, 2.1 V, of the input voltage range of the driving IC5.

The upper limit and the lower limit of the second command voltage signal S43may be respectively set at the voltage values equal to the upper limit, 5.4 V, and the lower limit, 2.1 V, of the input voltage range of the driving IC5. Moreover, the upper limit of the second command voltage signal S43may be set a little smaller than the upper limit of the input voltage range of the driving IC5within permissible limits of error.

In the present preferred embodiment, the command voltage adjusting circuit4sets the upper limit of the second command voltage signal S43to become larger than the upper limit of the input voltage range of the driving IC5. Moreover, the command voltage adjusting circuit4sets the lower limit of the second command voltage signal S43to become smaller than the lower limit of the input voltage range of the driving IC5. When the voltage range of the second command voltage signal S43is broader than the input voltage range of the driving IC5as set forth above, the input voltage range of the driving IC5can be used without waste even when there exists the manufacturing error in the input voltage range of the driving IC5.

The offset circuit41is a circuit that generates the offset voltage S41based on the ON/OFF signal S32and supplies the generated offset voltage S41to the adder circuit42. The offset circuit41preferably includes the first voltage-dividing circuit411and a buffer circuit412.

When the ON/OFF signal S32is an ON signal, the first voltage-dividing circuit411divides the normal voltage S33to thereby generate a pre-adjustment offset voltage S411. The pre-adjustment offset voltage S411thus generated is outputted to the buffer circuit412. When the ON/OFF signal S32is an OFF signal, the first voltage-dividing circuit411does not output the pre-adjustment offset voltage S411.

The buffer circuit412is a circuit that converts the pre-adjustment offset voltage S411supplied from the first voltage-dividing circuit411to an offset voltage S41having a stable voltage value. Since the buffer circuit412is interposed between the first voltage-dividing circuit411and the adder circuit42, the first voltage-dividing circuit411is not affected by a current change at the side of the adder circuit42. Thus, the voltage value of the offset voltage S41outputted from the offset circuit41becomes stable.

The adder circuit42is a circuit that generates an adder voltage S42by adding the first command voltage signal S31and the offset voltage S41at a predetermined ratio. The adder circuit42outputs the generated adder voltage S42to the magnification converting circuit43.

The magnification converting circuit43generates a second command voltage signal S43by converting the magnification of the adder voltage S42. The second command voltage signal S43thus generated is outputted to the driving IC5. By virtue of the adder circuit42and the magnification converting circuit43, the second command voltage signal S43can be outputted as a voltage, which is obtained by converting the first command voltage signal S31and the offset voltage S41at an arbitrary magnification and then adding the first command voltage signal S31and the offset voltage S41.

With the configuration described above, the command voltage adjusting circuit4converts the first command voltage signal S31having a voltage range of 0 to 5 V to the second command voltage signal S43having a voltage range of 1.9 to 5.6 V.FIG. 5is a graph representing the relationship between the count number S30outputted from the command voltage determining unit30of the microcomputer3and the second command voltage signal S43. As shown inFIG. 5, when the count number S30is 0 cnt, the second command voltage signal S43is 1.9 V. When the count number S30is the maximum of 255 cnt, the second command voltage signal S43is 5.6 V.

By shifting the lower and the upper limit of the first command voltage signal S31to adjust the second command voltage signal S43in the aforementioned manner, the range of 229 counts in which the count number S30is from 13 to 241 cnt can be used as an input signal inputted to the driving IC5.

In this regard,FIG. 6is a graph representing the relationship between the count number and the second command voltage signal in a comparative example where the command voltage adjusting circuit merely amplifies the first command voltage signal having a voltage range of 0 to 5 V by 1.12 times to output the second command voltage signal having a voltage range of 0 to 5.6 V. When the second command voltage signal is adjusted in such a manner that the upper limit of the first command voltage signal is merely shifted, the count number, which corresponds to the second command voltage signal of 2.1 to 5.6 V, namely which can be used as an input signal inputted to the driving IC5, is 151 counts from 96 to 246 cnt.

In contrast, when the second command voltage signal S43is adjusted by shifting both the upper and the lower limit of the first command voltage signal S31as in the present preferred embodiment, the section of the voltage range of the second command voltage signal S43, which falls outside the input voltage range of the driving IC5, is narrowed. Therefore, as compared with a case where the second command voltage signal is adjusted by shifting only the upper limit of the first command voltage signal, a resolution of the second command voltage signal per one count is enhanced.

The driving IC5generates the drive pulse S5as a PWM signal based on the second command voltage signal S43. The drive pulse S5thus generated is outputted to the inverter6. As shown inFIG. 4, the output duty of the drive pulse S5outputted from the driving IC5grows larger in proportion to the second command voltage signal S43within the input voltage range of 2.1 to 5.4 V.

The inverter6supplies a drive current S6to the motor9based on the drive pulse S5inputted from the driving IC5. The inverter6is configured by six switching elements. With respect to the individual phases, namely a U-phase, a V-phase and a W-phase, a pair of drive pulses S5is inputted to the inverter6. The inverter6generates a drive current S6by switching the drive timings of the respective switching elements. Thus, the rotation of the motor9is controlled.

In a case when the second command voltage signal S43has an abnormal voltage value, the abnormality detecting unit7outputs a stop signal S73to stop the driving IC5. As shown inFIG. 2, the abnormality detecting unit7preferably includes a detection signal adjusting circuit71, an A/D (analog/digital) converter72and a stop signal generating unit73.

The detection signal adjusting circuit71adjusts the second command voltage signal S43to fall within a voltage range, which can be inputted to the A/D converter72, and outputs a first detection signal S71. In the present preferred embodiment, the voltage range of the second command voltage signal S43is from 1.9 V to 5.6 V. In contrast, the range of the voltage which can be inputted to the A/D converter72included in the microcomputer3is from 0 V to 5 V. For that reason, a voltage-dividing circuit having two resistors as shown inFIG. 2is used as the detection signal adjusting circuit71of the present preferred embodiment. Depending on the resistance ratio of the two resistors, the detection signal adjusting circuit71divides the voltage of the second command voltage signal S43of 1.9 to 5.6 V to convert the second command voltage signal S43to, e.g., a first detection signal S71of 0.95 to 2.8 V. The A/D converter72performs analog-to-digital convert in which the first detection signal S71is converted to a second detection signal S72as a digital signal.

By comparing the count number S30inputted from the command voltage determining unit30with the second detection signal S72inputted from the A/D converter72, the stop signal generating unit73determines whether the second command voltage signal S43is a value corresponding to the count number S30. If the second detection signal S72and the count number S30are in a predetermined corresponding relationship, the stop signal generating unit73determines that there is no abnormality. Thus, the stop signal generating unit73does not output a stop signal S73to the driving IC5. If the second detection signal S72and the count number S30are not in the predetermined corresponding relationship, the stop signal generating unit73determines that there is an abnormality. Thus, the stop signal generating unit73outputs a stop signal S73to the driving IC5. When the stop signal S73is inputted, the driving IC5stops its operation regardless of the voltage of the second command voltage signal S43. When the motor driving device1includes the abnormality detecting unit7, it becomes possible to avoid a situation that the motor9is continuously driven and cannot be stopped when a malfunction is generated in the command voltage adjusting circuit4.

In the present preferred embodiment, the A/D converter72and the stop signal generating unit73are a part of the microcomputer3. However, the present invention is not limited thereto. The A/D converter72and the stop signal generating unit73may be realized by a microcontroller differing from the microcomputer3or by other configurations.

As indicated by a broken line inFIG. 1, the microcomputer3, the command voltage adjusting circuit4, the driving IC5, the inverter6and the abnormality detecting unit7are arranged on one substrate80. This makes it possible to reduce the number of assembling steps when assembling the motor driving device1and the motor9.

Next, a specific circuit configuration example for realizing the command voltage adjusting circuit4will be described with reference toFIG. 2.

The first voltage-dividing circuit411of the offset circuit41preferably includes a first resistor R1, a second resistor R2and a switching element SW1. One end of the first resistor R1is connected to the offset voltage source33. That is, the normal voltage S33is inputted to one end of the first resistor R1. One end of the second resistor R2is connected to the other end of the first resistor R1. The other end of the second resistor R2is grounded to an earth E1. The switching element SW1is connected in parallel with the second resistor R2. The ON/OFF signal S32transmitted from the offset instructing unit32is inputted to the switching element SW1. The voltage between the first resistor R1and the second resistor R2is outputted to the buffer circuit412as the pre-adjustment offset voltage S411.

As described above, the ON/OFF signal S32inputted to the switching element SW1has a voltage higher than 0 V when the ON/OFF signal S32is an OFF signal, and has a voltage equal to 0 V when the ON/OFF signal S32is an ON signal. For that reason, when the ON/OFF signal S32is the OFF signal, a current flows through the switching element SW1. Accordingly, in between the offset voltage source33and the earth E1, a current flows through the first resistor R1and the switching element SW1without flowing through the second resistor R2. Thus, the pre-adjustment offset voltage S411becomes 0 V.

When the ON/OFF signal S32inputted to the switching element SW1is the ON signal, a current does not flow through the switching element SW1. Thus, in between the offset voltage source33and the earth E1, a current flows through the first resistor R1and the second resistor R2. Accordingly, the normal voltage S33is divided depending on the resistance ratio of the first resistor R1and the second resistor R2and is outputted as the pre-adjustment offset voltage S411. In the present preferred embodiment, the normal voltage S33is 5 V and the pre-adjustment offset voltage S411is about 2.6 V.

The buffer circuit412preferably includes a first operational amplifier OP1. The pre-adjustment offset voltage S411is inputted to the non-inverting input terminal of the first operational amplifier OP1. An output terminal and the inverting input terminal of the first operational amplifier OP1are directly connected to each other. That is, the buffer circuit412is a so-called voltage follower circuit. Thus, the buffer circuit412stably outputs an offset voltage S41having the same voltage value as that of the pre-adjustment offset voltage S411. That is, in the present preferred embodiment, the offset voltage S41is about 2.6 V.

The adder circuit42preferably includes the third resistor R3and a fourth resistor R4. The input end of the third resistor R3is connected to the command voltage generating unit31and the output end thereof is connected to the magnification converting circuit43. The input end of the fourth resistor R4is connected to the buffer circuit412and the output end thereof is connected to the magnification converting circuit43. The output end of the third resistor R3and the output end of the fourth resistor R4are connected to each other.

Accordingly, in the adder circuit42, the first command voltage signal S31is inputted from the input end of the third resistor R3and the offset voltage S41is inputted from the input end of the fourth resistor R4. The adder circuit42adds the first command voltage signal S31and the offset voltage S41depending on the resistance ratio of the third resistor R3and the fourth resistor R4to output the adder voltage S42to the magnification converting circuit43. In the present preferred embodiment, the resistance value of the third resistor R3is equal to the resistance value of the fourth resistor R4. Thus, the adder circuit42adds the first command voltage signal S31and the offset voltage S41respectively multiplied by 0.5 and outputs the adder voltage S42thus obtained. That is, the adder voltage S42outputted by the adder circuit42is equal to the value obtained by adding about 1.3 V to the first command voltage signal S31multiplied by 0.5.

The magnification converting circuit43preferably includes a second operational amplifier OP2and a second voltage-dividing circuit431having a fifth resistor R5and a sixth resistor R6. The adder voltage S42as the output voltage of the adder circuit42is inputted to the non-inverting input terminal of the second operational amplifier OP2. An output terminal of the second operational amplifier OP2is connected to the driving IC5, whereby the second command voltage signal S43outputted from the second operational amplifier OP2is inputted to the driving IC5. The output terminal of the second operational amplifier OP2is also connected to the second voltage-dividing circuit431.

The second voltage-dividing circuit431preferably includes the fifth resistor R5and the sixth resistor R6. One end of the fifth resistor R5is connected to the output terminal of the second operational amplifier OP2. That is, the second command voltage signal S43is inputted to one end of the fifth resistor R5. One end of the sixth resistor R6is connected to the other end of the fifth resistor R5. The other end of the sixth resistor R6is grounded to an earth E2. The midpoint between the fifth resistor R5and the sixth resistor R6is connected to the inverting input terminal of the second operational amplifier OP2. That is, the voltage between the fifth resistor R5and the sixth resistor R6, i.e., a divided voltage S431outputted from the second voltage-dividing circuit431, is inputted to the second operational amplifier OP2as a negative feedback voltage. In other words, the magnification converting circuit43is a so-called non-inverting amplifier circuit. The non-inverting amplifier circuit not only converts the magnification of the input voltage but also serves as a buffer circuit. For that reason, the magnification converting circuit43can maintain a stable output voltage without being affected by the circuit at the output side.

While the magnification converting circuit43of the present preferred embodiment is a non-inverting amplifier circuit, the present invention is not limited thereto. The magnification converting circuit may be formed through the use of an inverting amplifier circuit or other amplifier circuits. The amplification factor of the magnification converting circuit43of the present preferred embodiment is equal to or larger than 1. However, depending on the kind of the adder circuit42combined, it may be possible to use the magnification converting circuit43having an amplification factor of less than 1.

In the present preferred embodiment, the magnification converting circuit43amplifies, by 1.48 times, the voltage inputted to the non-inverting input terminal of the second operational amplifier OP2. Thus, the second command voltage signal S43outputted from the magnification converting circuit43has a voltage obtained by adding 1.9 V to the first command voltage signal S31multiplied by 0.74. That is, when the voltage range of the first command voltage signal S31is from 0 V to 5 V, the voltage range of the second command voltage signal S43is from 1.9 V to 5.6 V.

In the present preferred embodiment, there is provided a dual amplifier in which the first operational amplifier OP1of the offset circuit41and the second operational amplifier OP2of the magnification converting circuit43are formed into a single package. Since the first operational amplifier OP1and the second operational amplifier OP2are formed into a single package, the physical configuration on the substrate80becomes simple.

While one illustrative preferred embodiment of the present invention has been described above, the present invention is not limited to the aforementioned embodiment.

FIG. 7is a block diagram showing the configuration of a motor driving device1A according to one modified example. In the example shown inFIG. 7, as indicated by a broken line, a microcomputer3A, a command voltage adjusting circuit4A and an abnormality detecting unit7A are arranged on one substrate81A. A driving IC5A and an inverter6A are arranged on another substrate82A. The substrate82A is mounted to a motor9A. In case where a control operation is performed with respect to the motor9A including the driving IC5A and the inverter6A, a motor driving device1A according to the present modified example can be implemented by preparing the substrate81A including the microcomputer3A and the command voltage adjusting circuit4A of the present modified example.

FIG. 8is a block diagram showing the configuration of a motor driving device1B according to another modified example. In the example shown inFIG. 8, as indicated by a broken line, a converter unit2B, a microcomputer3B, a command voltage adjusting circuit4B, a driving IC5B, an inverter6B and an abnormality detecting unit7B are arranged on one substrate80B. The substrate80B is mounted to a motor9B. In this way, all elements other than a power source may be mounted to the motor9B.

FIG. 9is a circuit diagram of a command voltage adjusting circuit4C according to a further modified example. In the example shown inFIG. 9, a microcomputer3C includes an offset instructing voltage source32C. The offset instructing voltage source32C serves as the offset instructing unit and the offset voltage source. A first voltage-dividing circuit411C of an offset circuit41C does not include the switching element. It is therefore possible to simplify the configuration of a microcomputer3C and the circuit configuration of the command voltage adjusting circuit4C.

The offset instructing voltage source32C outputs an offset command voltage S32C to the offset circuit41C based on a count number S30C inputted from a command voltage determining unit30C. Thus, the offset instructing voltage source32C instructs the offset circuit41C whether to generate an offset voltage S41C or not and supplies a voltage for generating the offset voltage S41C. In the present modified example, when the count number S30C is not inputted, the offset command voltage S32C is 0 V. When the count number S30C is inputted, the offset command voltage S32C becomes 5 V.

The first voltage-dividing circuit411C preferably includes a first resistor R1C and a second resistor R2C. One end of the first resistor R1C is connected to the offset instructing voltage source32C. That is, the offset command voltage S32C is inputted to one end of the first resistor R1C. One end of the second resistor R2C is connected to the other end of the first resistor R1C. The other end of the second resistor R2C is grounded to an earth E1C. Thus, the offset command voltage S32C is divided depending on the resistance ratio of the first resistor R1C and the second resistor R2C and is outputted as a pre-adjustment offset voltage S411C.

In the example shown inFIG. 9, when the offset command voltage S32C is 5 V, the pre-adjustment offset voltage S411C is about 2.6 V. When the offset command voltage S32C is 0 V, the pre-adjustment offset voltage S411C is 0 V. With this configuration, as in the aforementioned embodiment, the pre-adjustment offset voltage S411C becomes 0 V when the count number S30C is not inputted and the pre-adjustment offset voltage S411C becomes a voltage having a predetermined voltage when the count number S30C is inputted.

Further, in the aforementioned embodiment, the first operational amplifier of the offset circuit and the second operational amplifier of the magnification converting circuit are included in one dual amplifier. However, the present invention is not limited thereto. It may be possible to use two single amplifiers in which case the first operational amplifier and the second operational amplifier are installed independently of each other.

The number of the operational amplifiers included in the motor driving device is not limited to two. For example, the first command voltage signal outputted from the command voltage generating unit may be inputted to the adder circuit through the buffer circuit having an operation amplifier. In this way, the motor driving device may include three or more operation amplifiers. In case where the motor driving device includes three or more operation amplifiers, the motor driving device may include a quadruple amplifier in which four operation amplifiers are formed into one package.

Moreover, the specific circuit configuration for realizing the respective parts of the motor driving device may differ from the circuit configuration shown inFIG. 2. The respective elements employed in the preferred embodiment and the modified examples described above may be appropriately combined as long as no conflict arises.

Industrial Applicability

At least an embodiment of present invention can be used in a motor driving device.