Accurate zero current detector circuit in switching regulators

A switching regulator circuit includes a gate driver circuit driving a first switch and a second switch to generate a first voltage at a first node. Further, the switching regulator includes an LC filter circuit responsive to the first voltage to generate a desired output voltage. Moreover, the switching regulator includes a regulator circuit coupled to the LC filter circuit to control the gate driver circuit. The regulator circuit accurately controls variations in trip point. The trip point is a voltage at which the second switch is switched OFF by the gate control circuit. The regulator circuit includes one of a Delay Locked Loop (DLL) and a Pulse width modulator (PWM) controller.

PRIORITY

This application claims the priority of Indian Provisional Patent Application No. 2397/CHE/2014 filed on 14 May 2014, the disclosure of which is incorporated herein in its entirety.

FIELD OF THE INVENTION

The present invention generally relates to switching regulator circuit and more specifically to a regulator circuit controlling the variations of a trip point for switching OFF a power switch in the switching regulator circuit. The trip point is an instance when value of an inductor current is at an optimal proximity to zero.

BACKGROUND

DC-DC converters or regulators are implemented in circuits to achieve a desired source voltage. A buck switching regulator is a non-linear DC to DC voltage converter. The buck switching regulator has a pair of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) having a common switch node. A gate control circuit in the buck switching regulator controls the pair of MOSFETs connected to an LC filter circuit. The gate control circuit controls timing of the pair of MOSFETs to convert an input voltage Vin to an output voltage Vout. A first switch among the pair of MOSFETs generates a pulsated voltage signal. The pulsated voltage signal is filtered by the LC filter circuit to generate the output voltage Vout. A second switch among the pair of MOSFETs is switched ON to provide a conduction path necessary to de-energize an inductor in the LC filter during each switching cycle. Switching OFF the second switch before the inductor is completely de-energized results in energy loss in the buck switching regulator. As a result, a circuit for identifying an instance when the inductor current is zero is necessary. An instance when the inductor current becomes zero is referred to as “trip point”. A zero current detector is used to identify the instance at which the inductor current is zero.

Referring toFIG. 1now,FIG. 1illustrates an example of an existing buck switching regulator circuit100implementing a zero current detect (ZCD) comparator110. The buck switching regulator100includes a controller105, the ZCD comparator110, a gate control circuit115, a first switch120, a second switch125, an inductor130, a capacitor135, and a load terminal140. The first switch120and the second switch125have a common switch node. A first reference voltage VREF1and a switch node voltage SW_OUT is fed to the ZCD comparator110. The first reference voltage VREF1represents estimated magnitude of the switch node voltage SW_OUT when current through the inductor130is zero. A second reference voltage VREFand an output voltage Vout is fed to the controller105. The controller105controls duty cycle of the buck switching regulator100. The output voltage Vout is proportional to the duty cycle of the buck switching regulator100.

The working of the buck switching regulator100inFIG. 1is explained with reference to voltage signal graphs depicted inFIG. 2.FIG. 2depicts variation in the output of the ZCD comparator110based on the switch node voltage SW_OUT. The gate control circuit115supplies a PON signal to a gate terminal of the first switch120. The gate control circuit115supplies an NON signal to a gate terminal of the second switch125. The variations of the PON signal and the NON signal with time is depicted inFIG. 2. The PON signal goes to the HIGH state at a first instance t1. The PON signal switches on the first switch120at the first instance t1. The first switch120provides a low resistance conduction path from supply voltage Vdd to the inductor130. The switch node voltage SW_OUT signal rises to the supply voltage Vdd at the first instance t1. The gate control circuit115lowers the PON signal to a LOW state at a second instance t2. The PON signal hence switches OFF the first switch120. The first switch120breaks the low resistance conduction path from the supply voltage Vdd to the inductor130. The inductor130resists the abrupt change in current and forward biases a parasitic diode in the second switch125and hence the switch node voltage SW_OUT signal drops to negative value of forward bias voltage of the parasitic diode.

The gate control circuit115shifts the NON signal to HIGH state at a third instance t3. Time elapsed between the second instance t2and the third instance t3is called non-overlap period. The non-overlap period prevents the formation of a short circuit through the first switch120and the second switch125. The second switch125provides a conduction path from the inductor130to ground. At the third instance t3, the inductor current flows through the second switch125to ground de-energizing the inductor130. Therefore the switch node voltage SW_OUT increases to a value almost equal to zero. After the third instance t3the switch node voltage SW_OUT starts gradually increasing at the third instance t3due to linear de-energization of the inductor130. At a fourth instance t4, the switch node voltage SW_OUT equals the first reference voltage VREF1. The ZCD comparator110changes a ZCD Output signal to HIGH state after a comparator delay time td1. At a fifth instance t5, the gate control circuit115changes the NON signal to LOW state. Thus the ZCD comparator110identifies a trip point when the inductor current is zero and switches OFF the second switch125at the instance.

However, accuracy of the trip point of the ZCD comparator110depends on variables such as input supply, output voltage, comparator delay, mismatch in internal reference values, path delays, output inductance of the buck switching regulator100and, routing resistance of the buck switching regulator100. If the trip point occurs before inductor current falls to zero, a positive non-zero current remains in the inductor130when the second switch125is turned OFF. The remaining inductor current passes through a parasitic diode in the second switch125and cause conduction losses. If the trip point occurs after the inductor current cross a zero value, a negative non-zero current remains in the inductor130when the second switch125is turned OFF. Negative non-zero inductor current during the conduction time of the second switch125causes energy loss. The variation of the trip point affects energy efficiency of the buck switching regulator100.

In light of the foregoing discussion, there is a need for a regulator circuit to control the variations in trip point for switching OFF a power switch in the switching regulator circuit.

SUMMARY

The above mentioned need of an energy efficient switching regulator circuit to control the variations in trip point is met by employing a regulator circuit in the switching regulator.

An example of a switching regulator circuit includes a gate control circuit driving a first switch and a second switch to generate a first voltage at a first node. Moreover, the switching regulator includes an LC filter circuit responsive to the first voltage to generate a desired output voltage. Further, the switching regulator includes a regulator circuit coupled to the LC filter circuit to control the gate control circuit. The regulator circuit accurately controls variations in trip point.

Another example of a regulator circuit for controlling variations in trip point of a switching regulator circuit includes a first comparator operable to receive a first reference signal and a feedback signal to generate a first voltage signal. The first reference signal is a predetermined voltage at a first instance. Further, the regulator circuit includes a second comparator operable to receive a second reference signal and the feedback signal to generate a second voltage signal. The second reference signal is a predetermined voltage at a second instance. Further, the regulator circuit includes a reference delay circuit to delay the first voltage signal by a predetermined time period. Furthermore, the regulator circuit includes a Delay Locked Loop (DLL) to modify a zero current detector output. The DLL includes a Phase Frequency Detector (PFD) operable to receive the delayed first voltage signal and the second voltage signal to output a phase difference signal. The DLL includes a charge pump to generate a control voltage signal based on the phase difference signal. Further, the DLL includes a voltage controlled delay line (VCDL) to generate a delayed zero current detector output based on the control voltage signal, wherein the delayed zero current detector output control the variations in trip point of the switching regulator circuit.

Another example of a regulator circuit for controlling variations in trip point of a switching regulator circuit includes a sample and hold circuit to sample a feedback voltage at a first instance to generate a first voltage signal. Moreover, the regulator circuit includes a Pulse Width Modulation (PWM) controller to control the conduction time of a switch. The PWM controller includes an error amplifier operable to receive the first voltage signal and a first reference signal to generate an error signal. Further, the PWM controller includes a ramp circuit to generate a ramp signal. Moreover, a comparator operable to receive the error signal and the ramp signal to generate a control voltage signal. The control voltage signal controls the variations in trip point of the switching regulator circuit.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In non-linear DC to DC voltage converters such as buck switching regulators, energy efficiency at light loads depends on timing accuracy of switching off a power switch when inductor current is zero. As a result, the non-linear DC to DC voltage converters require a circuit to ensure accurate timing for the power switch. A zero cross detector comparator is employed in circuits described in prior arts, to ensure timing accuracy of the power switch. However, accuracy of the zero cross detector comparator is dependent on variables such as switch resistance, routing resistance, input supply, output voltage, output inductance, output capacitance and mismatch in internal reference value of the DC to DC voltage converter. Variations in the variables thus affect the timing accuracy of the power switch. A regulator circuit providing a highly accurate timing for the first switch in a DC to DC voltage converter is explained in the following description. In the disclosure the load current of the switching regulator is assumed to be low.

In the present disclosure, relational terms such as first and second, and the like, may be used to distinguish one entity from the other, without necessarily implying any actual relationship or order between such entities. The following detailed description is intended to provide example implementations to one of ordinary skill in the art, and is not intended to limit the invention to the explicit disclosure, as one or ordinary skill in the art will understand that variations can be substituted that are within the scope of the invention as described.

FIG. 3illustrates a schematic diagram of a buck switching regulator300in accordance with one embodiment of the present invention. The buck switching regulator300comprises a regulator circuit305, a gate control circuit310, a first switch315, a second switch320, an LC filter circuit325, and a load330. Examples of the first switch315include, but are not limited to p-type metal oxide semiconductor field effect transistor (MOSFETs) and n-type MOSFETs. Examples of the second switch320include, but are not limited to p-type MOSFETs and n-type MOSFETs. The first switch315connects the input supply voltage Vin with the LC filter circuit325and the second switch320. The first switch315and the second switch320are arranged in push-pull configuration connected at a first node. The gate control circuit310controls the first switch315and the second switch320by supplying control signals to gate inputs of the first switch315and the second switch320.

The gate control circuit310is operable to receive a controller input and an input signal from the regulator circuit. The controller input controls the gate control circuit310based on duty cycle of the buck switching regulator300. The duty cycle of the first switch315determines magnitude of the output voltage Vout. By switching ON and switching OFF the first switch315at a periodic rate, a rectangular waveform is generated at the input of the LC filter circuit325. An inductor in the LC filter circuit325energizes during the conduction time of the first switch315. The LC filter circuit325filters the rectangular waveform to generate the output voltage Vout across the load330. The gate control circuit310switches OFF the first switch315after a time period determined by the duty cycle. The inductor de-energizes during the non-conduction time of the first switch315.

The second switch320provides a conduction path for inductor current to flow to ground when switched ON. The inductor current decreases linearly during the conduction time of the second switch320. The gate control circuit310further receives an input signal derived from the feedback signal fed to the regulator circuit305. The feedback signal is the voltage signal VSW_OUTat the switch node. The gate control circuit310switches OFF the second switch320at a trip point. The trip point is the voltage at which the inductor current is equal to zero. The variation in the trip point of the buck switching regulator300is regulated by the regulator circuit305.

The regulator circuit305is coupled to the LC filter circuit325to control the gate control circuit310. The regulator circuit305controls the gate control circuit310to switch OFF the second switch320at the trip point. If the trip point occurs before inductor current falls to zero, a positive non-zero inductor current remain in the inductor when the second switch320is turned OFF. The remaining inductor current passes through a parasitic diode in the second switch320and cause conduction losses. If the trip point occurs after the inductor current cross a zero value, a negative non-zero inductor current remains in the inductor when the second switch320is turned OFF. Negative non-zero inductor current during the conduction time of the second switch320causes energy loss. Hence, energy efficiency of the buck switching regulator300depends on switching OFF the second switch320at an accurate trip point.

The regulator circuit305accurately controls variations in trip point. The regulator circuit305regulates the trip point to align the trip point with the instance when the inductor current is zero. The regulator circuit305regulates the trip point with a method comprising sensing an appropriate variable in the buck switching regulator300at a first instance. The method includes calculating magnitude of the inductor current at the first instance from the appropriate variable. Further, the method includes calculating difference in the magnitude of the inductor current at the first instance with an internal reference signal. Furthermore the method includes minimizing the difference in the magnitude of the inductor current at the first instance with an internal reference signal. A control loop minimizes the difference with a predetermined loop gain.

FIG. 4illustrates a buck switching regulator with a delay locked loop, in accordance with one embodiment of the present invention. The buck switching regulator consists of a first comparator405, a zero current detector output generator410, a reference delay420, a second comparator430, a gate control circuit435, a first switch440, a second switch445, a first node450, an inductor455, a capacitor460, and a delay locked loop465. The inductor455and the capacitor460together act as an LC filter circuit.

Examples of the first switch440include, but are not limited to p-type MOSFETs and n-type MOSFETs. Examples of the second switch445include, but are not limited to p-type MOSFETs and n-type MOSFETs. The first switch440connects the input voltage Vin with the LC filter circuit and the second switch445. The second switch445connects the first switch440to the ground. The first switch440and the second switch445are connected at the first node450. The gate control circuit435supplies a first input signal, hereinafter referred to as PON signal to gate input of the first switch440. Further, the gate control circuit435supplies a second input signal, hereinafter referred to as NON signal to the second switch445. Hence, the gate control circuit435controls the switching ON and the switching OFF of the first switch440and the second switch445. By switching ON and switching OFF the first switch440at a periodic rate, a rectangular waveform is generated at the input of the LC filter circuit. The rectangular waveform is filtered by the LC filter circuit to generate an output voltage Vout. The inductor455in the LC filter circuit energizes during the conduction time of the first switch440.

After a time interval, the PON signal falls to a LOW state and the gate control circuit435switches OFF the first switch440. The first switch440blocks the inductor current flow from the input voltage Vin to the LC filter. The inductor455de-energizes during non-conduction time of the first switch440. Hence, polarity of the voltage across the inductor455is reversed. The gate control circuit435switches ON the second switch445. The second switch445provides a conduction path for the inductor current to flow to the ground. The inductor current decreases linearly during the conduction time of the second switch445. Next, the gate control circuit435switches OFF the second switch445at a trip point.

A regulator circuit regulates the trip point to align the trip point with the instance when the inductor current is zero. The regulator circuit is formed by the first comparator405, the zero current detector output generator410, the second comparator430, the reference delay420, and the delay locked loop465.

The first comparator405is operable to receive a first reference signal and a feedback signal. The first reference signal is a first predetermined voltage at a first instance. The magnitude of the first reference signal is equal to the voltage when a parasitic diode in the second switch445of the switching regulator circuit starts to carry the inductor current. The first reference signal is hereinafter referred to as first reference voltage VREF1.

The feedback signal is the voltage signal VSW_OUTat the first node450. The feedback signal reaches the first reference voltage VREF1at the first instance. Output of the first comparator405shifts to HIGH state at the first instance. The second comparator430is operable to receive a second reference signal VREF2and the feedback signal. The second reference voltage VREF2is magnitude of the feedback voltage when damped oscillation commences in the inductor455and a parasitic capacitance. The second reference voltage VREF2is positive in polarity. The feedback signal reaches the second reference voltage VREF2at the second instance Output of the second comparator430shifts to HIGH state at the second instance. The time difference between the first instance and the second instance capture value of the inductor current in the switching regulator circuit.

The reference delay420delays the output of the first comparator405by a predetermined time period. The delayed output of the first comparator405and output of the second comparator430is fed to the delay locked loop465. The delay locked loop465modifies the output of the zero crossing detector depending on the phase difference between the inputs. The delay locked loop465includes a phase detector (PD)415and a voltage controlled delay line (VCDL)425. The PD415includes a phase frequency detector (PFD) and charge pump circuit (CP). The PD415is operable to receive a delayed output of the first comparator405and the output of the second comparator430. The PFD detects phase difference between the outputs of the first comparator405and the second comparator430. The CP generates a control voltage signal proportional to the phase difference between the outputs of the first comparator405and the second comparator430. The zero current detector output generator410generates an output pulse to indicate an estimated time when the inductor current through the inductor455reaches zero.

However, timing accuracy of the generated output pulse is dependent on variables such as switch resistance, internal routing resistance, input supply, output voltage, output inductance, output capacitance and mismatching in internal reference value of the DC to DC voltage converter. The dependent variables vary with external supply and environmental conditions. As a result, the timing of the output pulse is inaccurate and the output pulse is generated prematurely. The VCDL425is operable to receive the output pulse and the control voltage signal as inputs. The VCDL425delays the output pulse by a delay amount proportional to the control voltage signal. The output from the VCDL425is fed to the gate control circuit435to switch OFF the second switch445at a trip point. The trip point is an instance when the inductor current flowing through the inductor455in the LC filter circuit is equal to zero. The delayed output pulse control the variations in the trip point of the switching regulator circuit.

The working of the buck switching regulator inFIG. 4is explained by referring to voltage signal graphs depicted inFIG. 5. Voltage time graphs of the PON signal, the NON signal, and the voltage signal VSW_OUTis explained inFIG. 5. X axis of the graph indicates time and Y axis of graph indicates voltage. At a first instance t1, the gate control circuit435shifts the PON signal to HIGH state, thereby switching ON the first switch440. The first switch440provides a conduction path from input voltage source Vin to ground via the inductor455and the capacitor460. The inductor455energizes during the conduction time of the first switch440. At a second instance t2, the gate control circuit435changes the state of PON signal to LOW state. Hence, the first switch440switches OFF at the second instance t2. The polarity of the voltage across the inductor455reverses and forward biases a parasitic diode in the second switch445. Thus, the voltage signal VSW_OUTdrops to a negative voltage, the magnitude of the negative voltage being the magnitude of the forward biased voltage of the parasitic diode.

The gate control circuit435keeps the PON signal and the NON signal at LOW state during time period between the second instance t2and a third instance t3. The time between the second instance t2and the third instance t3is non-overlap period. The non-overlap period prevents concurrent conduction of the first switch440and the second switch445. As a result, the non-overlap period prevents a short circuit between the input voltage Vin supply and the ground. The gate control circuit435switches the NON signal to HIGH state. The second switch445starts conducting at the third instance t3. The second switch445provides a low resistance conduction path for the inductor current.

The low resistance conduction path generates voltage approximately equal to zero across the second switch445. Thus the voltage signal VSW_OUTabruptly increases to a magnitude approximately equal to zero at the third instance t3. However, the polarity of the voltage signal VSW_OUTis negative. The inductor455de-energizes during conduction time of the second switch445. At a fourth instance t4, the zero current detector output generator410sends the output pulse to gate control circuit435. In response to the output pulse, the gate control circuit435switches the state of the NON signal to LOW state. The second switch445stops conducting at the fourth instance t4. The parasitic diode in the second switch445becomes forward biased at the fourth instance t4. Hence, the voltage signal VSW_OUTdrops to the negative voltage, the magnitude of the negative voltage being the magnitude of the forward biased voltage of the parasitic diode. At a fifth instance t5, the voltage signal VSW_OUTbecomes equal to the first reference voltage VREF1. The first comparator405generates a first comparator output signal. The reference delay420delays the output of the first comparator405by a predetermined delay amount. At a sixth instance t6, the voltage signal VSW_OUTbecomes equal to the second reference voltage VREF2.

At the sixth instance t6, the second comparator430generates a second comparator output signal. In ideal conditions, the gate control circuit435switches OFF the second switch445at an instance when the inductor current is zero. However, the inaccuracy of zero current detector output generator410causes a premature switching OFF of the second switch445. As a result, the inductor current remains non-zero during the switch OFF of the second switch445, thereby causing variation in the trip point.

The inductor current forward biases the parasitic diode in the second switch445. Hence, the voltage signal VSW_OUTdrops to the negative voltage, the magnitude of the negative voltage being the magnitude of the forward biased voltage of the parasitic diode. The voltage signal VSW_OUTreaches the first reference voltage VREF1and output of the first comparator405shifts to HIGH state. The inductor current reduces linearly with the de-energization of the inductor455. The inductor current reaches a value insufficient to maintain the forward biased condition in the parasitic diode, thereby switching OFF the parasitic diode. The energy stored in a parasitic capacitor and output capacitor460causes damped oscillations in the LC filter. In the process, the voltage signal VSW_OUTrises to a value equal to the second reference voltage VREF2and output of the second comparator430shifts to HIGH state. Phase difference between the first comparator output signal and the second comparator output signal indicates the timing error in switching OFF the second switch445. The PD415generates the control voltage signal proportional to the phase difference between the outputs of the second comparator430and output of the reference delay420. The timing error in switching OFF the second switch445is minimized by adding correctional delays to the output pulse generated by the zero current detector output generator410, thereby preventing the premature switching OFF of the second switch445.

The VCDL425is operable to receive the output pulse and the control voltage signal as inputs. The VCDL425delays the output pulse by a correctional delay amount proportional to the control voltage signal to generate a delayed output pulse. Hence, timing accuracy of the second switch445is improved in the next switching cycle. The timing accuracy reaches a highly accurate value over a period of multiple switching cycles. The gate control circuit435shifts the state of PON signal to HIGH state at a seventh instance t7.

FIG. 6illustrates a buck switching regulator with a pulse width modulation (PWM) controller, in accordance with another embodiment of the present invention. The buck switching regulator consists of a zero current PWM controller605, a sample and hold circuit625, a gate control circuit630, a first switch635, a second switch640, an inductor645, a capacitor650and a first node655.

Examples of the first switch635include, but are not limited to p-type MOSFETs and n-type MOSFETs. Examples of the second switch640include, but are not limited to p-type MOSFETs and n-type MOSFETs. The first switch635connects the input voltage Vdd with an LC filter circuit and the second switch640. The LC filter circuit is formed by the inductor645and the capacitor650. The second switch640connects the first switch635to the ground. The first switch635and the second switch640are connected at the first node655. The gate control circuit630supplies a first input signal, hereinafter referred to as PON signal to gate input of the first switch635. Further, the gate control circuit630supplies a second input signal, hereinafter referred to as NON signal to the second switch640. Hence, the gate control circuit630controls the switching ON and the switching OFF of the first switch635and the second switch640. By switching ON and switching OFF the first switch635at a periodic rate, a rectangular waveform is generated at the input of the LC filter circuit. The rectangular waveform is filtered by the LC filter circuit to generate an output voltage Vout. The inductor645in the LC filter circuit energizes during the conduction time of the first switch635.

After a time interval, the PON signal falls to a LOW state and the gate control circuit630switches OFF the first switch635. The first switch635blocks the inductor current flow from the input voltage Vdd to the LC filter. The inductor645de-energizes during non-conduction time of the first switch635. The gate control circuit630switches ON the second switch640. The second switch640provides a conduction path for the inductor current to flow to the ground. The inductor current decreases linearly during the conduction time of the second switch640.

Next, the gate control circuit630switches OFF the second switch640after a regulated time period at a trip point. If the trip point occurs before inductor current falls to zero, a positive non-zero current remain in the inductor645when the second switch640is turned OFF. The remaining inductor current passes through a parasitic diode in the second switch640and cause conduction losses. If the trip point occurs after the inductor current cross a zero value, a negative non-zero current remains in the inductor645when the second switch640is turned OFF. Negative non-zero inductor current during the conduction time of the second switch640causes energy loss. Hence, energy efficiency of the buck switching regulator depends on alignment of the trip point to an instance when the inductor current is zero.

A regulator circuit regulates the trip point to align the trip point with the instance when the inductor current is zero. The regulator circuit is formed by the zero current PWM controller605, and the sample and hold circuit625. The regulator circuit regulates the trip point with a method comprising sensing a voltage signal VSW_OUT. The method includes calculating magnitude of the inductor current at the first instance from the voltage signal VSW_OUT. Further, the method includes calculating difference in the magnitude of the inductor current from zero current. Furthermore, the method includes minimizing the difference in the magnitude of the inductor current at the first instance from zero current with a control loop with a predetermined loop gain.

The zero current PWM controller605is operable to receive an internal reference voltage Vref and the output of the sample and hold circuit625. The internal reference voltage Vref is the voltage across the second switch640when inductor current through the inductor645is zero. The zero current PWM controller605comprises an error amplifier610, a ramp circuit620, and a comparator615.

The error amplifier610is operable to receive the internal reference voltage signal Vref and the output of the sample and hold circuit625. The error amplifier610generates an error signal equal to the difference between the output of the sample and hold circuit625and the internal reference Vref. The ramp circuit620generates a ramp signal changing linearly at a constant rate. The comparator615is operable to receive the output of the error amplifier610and the ramp circuit620.

The comparator615generates a comparator output signal, when the ramp signal of the ramp circuit620equals the output of the error amplifier610. Hence, time taken by the comparator615to generate the comparator output signal depends on the output of the error amplifier610. The gate control circuit630is operable to receive a controller input voltage signal and a regulation voltage signal. The gate control circuit630supplies gating signals to the first switch635and a second switch640.

The gate control circuit630supplies a first input signal PON to gate input of the first switch635and a second input signal NON to the second switch640. As a result, the gate control circuit630controls the switching ON and the switching OFF of the first switch635and the second switch640. The inductor645and the capacitor650forms a LC filter circuit. The first node655connects the inductor645, the first switch635and the second switch640. The sample and hold circuit625is operable to receive the voltage signal VSW_OUTfrom the first node655.

The working of the buck switching regulator inFIG. 6is explained by referring to voltage signal graphs depicted inFIG. 7. Voltage time graphs of the PON signal, the NON signal, and the voltage signal VSW_OUTis explained with reference toFIG. 7. X axis of the graph indicates time and Y axis of graph indicates voltage. At a first instance t1, the gate control circuit630changes the PON signal to HIGH state. The PON signal switches ON the first switch635, and the first switch635provides a conduction path from input voltage Vdd to ground via the inductor645and the capacitor650. The inductor645energizes during the conduction time of the first switch635.

At a second instance t2, the gate control circuit630changes the state of PON signal to LOW state. Hence, the first switch635switches OFF at the second instance t2. As a result, the inductor645starts de-energizing and the polarity of voltage across the inductor645is reversed. A parasitic diode in the second switch640gets forward biased and conducts inductor current to the ground. Thus, the voltage signal VSW_OUTdrops to a negative voltage, the magnitude of the negative voltage being the magnitude of the forward biased voltage of the parasitic diode. The gate control circuit630keeps the PON signal and the NON signal at LOW state during time period between the second instance t2and a third instance t3. The time between the second instance t2and the third instance t3is non-overlap period. The non-overlap period prevents concurrent conduction of the first switch635and the second switch640. As a result, the non-overlap period prevents a short between the input voltage Vdd supply and the ground.

At the third instance t3, the gate control circuit630changes the NON signal to HIGH state. The second switch640starts conducting at the third instance t3. The second switch640provides a LOW resistance conduction path for the inductor current. The low resistance conduction path generates voltage approximately equal to zero across the second switch640. Hence, the voltage signal VSW_OUTabruptly increases to a magnitude approximately equal to zero at the third instance t3. However, the polarity of the voltage signal VSW_OUTis negative. The inductor current decreases linearly during conduction time of the second switch640. Hence, the voltage signal VSW_OUTincreases linearly during conduction time of the second switch640. At a fourth instance t4, the voltage signal VSW_OUTbecomes equal to the internal reference Vref. At this point, the zero current PWM controller605provides a signal to the gate control circuit630to turn off the second switch640. The internal reference voltage Vref corresponds to the value of the voltage signal VSW_OUTwhen the inductor current is zero. However, the timing accuracy of switching OFF the switch640is dependent on variables such as delay in the gate control circuit630and comparator delay. Variations in the variables affect the time accuracy of the trip point.

Conduction time of the second switch640is adjusted to be equal to the time taken for the inductor current to reach zero. The internal reference voltage Vref is the voltage across the second switch640, when inductor current through the inductor645is zero. If the magnitude of the voltage signal VSW_OUTat the fourth instance t4is greater than the internal reference voltage Vref, the conduction time of the second switch640was shorter than desired time. If the magnitude of the voltage signal VSW_OUTat the fourth instance t4is greater than the internal reference voltage Vref, the inductor645rate of de-energization of the inductor645is greater than the ideal rate. If the magnitude of the voltage signal VSW_OUTat the fourth instance t4is greater than the internal reference voltage Vref, the conduction time of the second switch640was longer than desired time. The conduction time of the second switch640is controlled by the zero current PWM controller605.

The sample and hold circuit625samples the voltage signal VSW_OUTwhen the second switch640is switched OFF. The error amplifier610generates an error signal equal to the difference between the output of the sample and hold circuit625and the internal reference voltage Vref. The ramp circuit620generates a ramp signal. The comparator615is operable to receive the error signal from the error amplifier610and the ramp signal from the ramp circuit620. The comparator615generates a comparator output signal when magnitude of the ramp signal reaches magnitude of the error signal. Hence, time taken by the comparator615to generate the comparator output signal depends on the error signal from the error amplifier610. The comparator output signal is supplied to the gate control circuit630to control the conduction time of the second switch640. As a result, the conduction time of the second switch640is regulated. Hence, the present invention improves the timing accuracy of conduction time of the second switch640.

Advantageously the embodiments specified in the present invention improve the timing accuracy of the conduction times of a second switch in a switching regulator. Unlike the existing prior arts, the present invention takes into account the variables such as output inductance, switch resistance, internal routing resistance, input supply, output voltage, mismatching in internal reference values of the DC to DC voltage converter, path delays affecting timing accuracy of the conduction times of a second switch in a switching regulator. As a result, the present invention enhances the energy efficiency of the switching regulator. The circuit configuration allows a fairly accurate timing for conduction times of the second switch, over process, voltage and temperature variation.

In the preceding specification, the present disclosure and its advantages have been described with reference to specific embodiments. However, it will be apparent to a person of ordinary skill in the art that various modifications and changes can be made, without departing from the scope of the present disclosure, as set forth in the claims below. Accordingly, the specification and figures are to be regarded as illustrative examples of the present disclosure, rather than in restrictive sense. All such possible modifications are intended to be included within the scope of present disclosure.