UART aggregation and JTAG selection circuitry for a multi-solid state drive environment

An adaptor device includes a first interface for coupling to a first processor, a second interface for coupling to a second processor, the second interface being different than the first interface, and a plurality of third interfaces, which are different than either the first interface or the second interface. The plurality of third interfaces are configured for coupling to a corresponding plurality of external devices. The adaptor device is configured to receive, at the first interface, a first signal from the first processor. In response to the first signal, the adaptor device couples through the plurality of third interfaces to the plurality of external devices to enable the first processor substantially concurrent access to the plurality of external devices. The adaptor device is also configured to receive, at the first interface, a second signal from the first processor. In response to the second signal, the adaptor device couples the second processor with a selected one of the plurality of external devices.

BACKGROUND OF THE INVENTION

The present disclosure relates generally to systems and methods for communication between electronic devices, and, more specifically, to improving performance monitoring of non-volatile storage devices.

Electronic systems and devices have wide-ranging applications. For example, a solid-state drive (SSD) is a solid-state storage device that uses integrated circuit assemblies to store data persistently, typically using flash memory, and functioning as secondary storage in the hierarchy of computer storage. It is also sometimes referred to as a solid-state device or a solid-state disk. Compared with electromechanical drives, SSDs are typically more resistant to physical shock, run silently, and have quicker access time and lower latency. SSDs store data in semiconductor cells, and can vary in their properties according to the number of bits stored in each cell, for example, single-bit cells (“SLC”), 2-bit cells (“MLC”), 3-bit cells (“TLC”), and quad-bit cells (“QLC”).

SSDs can use traditional hard disk drive (HDD) interfaces and form factors for example, Serial Advanced Technology Attachment (Serial ATA or SATA) and Serial Attached Small Computer System Interface (Serial Attached SCSI or SAS), and standard HDD form factors that allow such SSDs to be used as drop-in replacements for HDDs in computers and other devices. Alternatively, SSDs can use newer interfaces, such as Universal Serial Bus (USB), and form factors that exploit specific advantages of the flash memory in SSDs.

These electronic systems and devices are subject to extensive testing to ensure proper operation. While testing of the systems and devices has made significant advances, traditional approaches to debugging problems or issues that are discovered during the testing are less than satisfactory.

SUMMARY OF THE INVENTION

Solid-state drives can use sideband communication channels like Universal Asynchronous Receiver Transmitter (UART) and Joint Test Action Group (JTAG) for logging telemetry data and configuring device behavior for testing and debug purposes. A typical issue with conventional monitoring of traffic and transactions taking place inside the devices under test (DUT) for debug analysis is that they typically require the DUT to be connected to a discrete external instrument (e.g., external monitor). This usually means that the DUT has to be disconnected and removed from the testing environment and connected to an external wiring harness that communicates the information to the external instrument. Furthermore, during device bring-up in typical traditional approaches, only a single DUT can be debugged at a time. The user often has to disrupt or interrupt other testing activities to hook up an external monitor to the DUT to be able to debug the DUT. Hence, there is a need for a solution which can aggregate multiple UART and JTAG channels, and provide a more efficient mechanism for connection, such as a serial bus, e.g., a Universal Serial Bus (USB), to a host personal computer (PC).

In some embodiments of the present disclosure, an adaptor device can convert UART and JTAG channels into a serial bus output so that standard computer systems can be used for interfacing, logging, and debugging. Existing solutions only support a single UART or JTAG channel, creating setup and stability challenges when multiple solid-state drives (SSDs) are enumerated in a system. The device according to this embodiment allows a user to use a single computer to program any of the drives with UART and JTAG signals connected and allows the user to monitor all connected drives' activities substantially simultaneously or concurrently. As an example, in the application of SSD product design validation, the testing and debug time can be reduced due to enhanced logging and controlling capabilities. It will also mean a single hardware adapter can be used for multiple drives, reducing the need for additional test hardware.

In some embodiments of the present disclosure, an adapter device uses integrated circuits (IC's) capable of interfacing multiple UART channels into a single serial/USB output. The outputs of multiple ICs' serial outputs are then aggregated using a USB hub IC. This way, every UART channel can be individually accessed substantially simultaneously/concurrently. Multiple JTAG connections can be consolidated and selectable using a multiplexer logic. Any individual JTAG channel can be selected using jumpers onboard the adapter, or using a serial channel, which controls a Decoder IC for multiplexer selection logic. Buck convertors can be used to convert USB power into Vcc power for the IC's on the adapter.

According to an exemplary embodiment of the present disclosure, an adaptor device includes a USB connector for coupling to USB signals, a JTAG connector for coupling to JTAG signals, and a plurality of dual-purpose connectors configured for coupling to a corresponding plurality of external devices. Each of the plurality of dual-purpose connectors is configured for coupling to both UART signals and JTAG signals. The adaptor device also includes a USB-to-UART interface circuit coupled to the USB connector and the plurality of dual-purpose connectors. The USB-to-UART interface circuit includes a USB hub and a plurality of USB-UART converters. The adaptor device also includes a multiplexer circuit coupled to the JTAG connector and the plurality of dual-purpose connectors. The multiplexer circuit is configured to couple the JTAG connector to one of the plurality of dual-purpose connectors in response to a selection signal.

In some embodiments of the above adaptor device, each of the plurality of dual-purpose connectors includes a first subset of pins configured for coupling to UART signals and a second subset of pins operable for coupling JTAG signals.

In some embodiments, each of the plurality of dual-purpose connector comprises two UART pins and five JTAG pins.

In some embodiments, each of the plurality of external devices is solid-state drives (SSDs).

In some embodiments, each SSD device comprises a dual-purpose connector having both UART pins and JTAG pins for coupling to a corresponding plurality of external devices.

In some embodiments, each SSD is coupled to a dual-purpose connector through an adaptor for coupling to both UART signals and JTAG signals.

In some embodiments, the USB-to-UART interface circuit comprises a USB hub and a plurality of USB-UART converter circuits, and the USB-to-UART interface circuit is configured to enable the USB connector concurrent access to the plurality of dual-purpose connectors.

In some embodiments, the multiplexer circuit receives the selection signal derived from a signal received from the USB connector and configured to couple the JTAG connector to one of the plurality of dual-purpose connectors in response to a selection signal.

In some embodiments, the multiplexer circuit receives the selection signal from a jumper.

In some embodiments, the adaptor device also includes level shifter circuits coupled between the USB-to-UART converters and the dual-purpose connectors.

In some embodiments, the adaptor device also includes a power converter circuit to convert power received from the USB connector to voltages suitable for circuit components in the adaptor device.

In some embodiments, the adaptor device also includes a Printed Circuit Board (PCB) upon which the USB connector, the JTAG connector, the plurality of dual-purpose connectors, and the USB-to-UART switching circuit are disposed.

According to an exemplary embodiment of the present disclosure, an adaptor device includes a first interface for coupling to a first processor, a second interface for coupling to a second processor, the second interface being different than the first interface, and a plurality of third interfaces, which are different than the first interface and the second interface. The plurality of third interfaces are configured for coupling to a corresponding plurality of external devices. The adaptor device is configured to receive, at the first interface, a first signal from the first processor. In response to the first signal, the adaptor device couples through the plurality of third interfaces to the plurality of external devices to enable the first processor substantially concurrent access to the plurality of external devices. The adaptor device is also configured to receive, at the first interface, a second signal from the first processor. In response to the second signal, the adaptor device couples the second processor with a selected one of the plurality of external devices.

In some embodiments of the above adaptor device, the first interface is configured to couple to USB signals, and the second interface is configured to couple to JTAG signals.

In some embodiments, each of the plurality third interfaces is configured to couple to UART signals and JTAG signals, and each of the plurality of external devices is configured to couple to UART signals and JTAG signals.

In some embodiments, the adaptor device also includes an adaptor circuit that includes a USB hub, a plurality of USB-UART converters, and a multiplexer circuit.

According to another exemplary embodiment of the present invention, a method for accessing a plurality of external devices includes coupling a first processor through a first interface and coupling a second processor through a second interface, the second interface being different than the first interface. The method also includes receiving, at the first interface, a first signal from the first processor; and, in response to the first signal, coupling through a plurality of third interfaces to a corresponding plurality of external devices to enable the first processor substantially concurrent access to the plurality of external devices. The method also includes receiving, at the first interface, a second signal from the first processor, and, in response to the second signal, coupling the second processor with a selected one of the plurality of external devices.

In some embodiments of the above method, the first interface is configured to couple to Universal Serial Bus (USB) signals, and the second interface is configured to couple to Joint Test Action Group (JTAG) signals.

In some embodiments, each of the plurality of external devices is configured to couple to both Universal Asynchronous Receiver Transmitter (UART) signals and JTAG signals.

In some embodiments, the method also includes coupling the first interface to the plurality of third interfaces using a USB-to-UART interface circuit that includes a USB hub and a plurality of USB-UART converters.

DETAILED DESCRIPTION OF THE INVENTION

FIG.1is a simplified block diagram illustrating an electronic device test system, according to an exemplary embodiment of the present disclosure. As shown inFIG.1, test system100includes one or more devices under test (DUT)101, a test system110, and a host120. Host120can include, among other components, a processor for providing user interface. The DUTs101are coupled to test system110, which is coupled to host120. In some embodiments, test system110can provide a primary test channel112and a sideband channel114. The primary test channel112can be configured to perform preliminary analysis and reconfiguration of persistent test information, and also perform preliminary analysis reconfiguration of debug information for communication to an external device. The sideband channel114can be used to provide a monitoring interface. The monitoring interface can communicate information associated with monitoring activities and traffic inside the device under test.

Solid-state drives under test can use sideband communication channels under protocols like Universal Asynchronous Receiver Transmitter (UART) and Joint Test Action Group (JTAG), etc. In some embodiments, a hardware adapter can convert UART and JTAG channels into a serial bus output, so that standard computer systems can be used for interfacing, logging, and debugging. Existing solutions only support a single UART/JTAG channel, creating setup and stability challenges when multiple solid-state drives are enumerated in a system. Hence, there is a need for a solution which can aggregate multiple UART and JTAG channels, and provide a single serial bus (USB) to a host PC for a cleaner and simpler connection. The various connectors and protocols are briefly described below.

JTAG (Joint Test Action Group, which codified it) is an industry standard for verifying designs and testing printed circuit boards after manufacture. A JTAG interface is a special interface added to a chip. Depending on the version of JTAG, two, four, or five pins are added. In the five-pin version, the connector pins are: Test Data In (TDI), Test Data Out (TDO), Test Clock (TCK), Test Mode Select (TMS), and Test Reset (TRST).

A universal asynchronous receiver-transmitter (UART) is a computer hardware device for asynchronous serial communication, in which the data format and transmission speeds are configurable. The electric signaling levels and methods are handled by a driver circuit external to the UART. A UART is usually an individual (or part of an) integrated circuit (IC) used for serial communications over a computer or peripheral device serial port. UART transmitted data is organized into packets. Each packet contains 1 start bit, 5 to 9 data bits (depending on the UART), an optional parity bit, and 1 or 2 stop bits. A UART device usually has two pins, a transmit pin Tx and a receive pin Rx. Data is transferred from the data bus to the transmitting UART in parallel form. Next, the data packet is output serially, bit by bit, at the Tx pin. The receiving UART reads the data packet bit by bit at its Rx pin. The receiving UART then converts the data back into parallel form and transfers the data packet in parallel to the data bus on the receiving end.

Universal Serial Bus (USB) is an industry standard that establishes specifications for cables and connectors and protocols for connection, communication, and power supply (interfacing) between computers, peripherals, and other computers. Examples of peripherals that are connected via USB include computer keyboards and mice, video cameras, printers, portable media players, disk drives, and network adapters. There are various USB standards and connectors, such as USB Type A, Type B, Type C, USB 1.0, 2.0, 3.0, and 4.0. The basic USB-A and USB-B plugs have four pins: VBUS (+5V), Data−, Data+, and Ground.

FIG.2is a simplified block diagram for an adaptor device, according to an exemplary embodiment of the present disclosure. As shown inFIG.2, an adaptor device200includes a first interface210for coupling to a first processor201and a second interface220for coupling to a second processor202, the second interface being different from the first interface. Adaptor device200also includes a plurality of third interfaces230for coupling to a corresponding plurality of external devices203. The plurality of third interfaces230are different from the first and the second interfaces. Adaptor device200is configured to receive, at the first interface210, a first signal from the first processor201. In response to the first signal, adaptor device200couples to the plurality of third interfaces230to the plurality of external devices203to enable the first processor201concurrent access to the plurality of external devices203. Adaptor device200is also configured to receive, at the first interface210, a second signal from the first processor201. In response to the second signal, adaptor device200couples the second processor202with a selected one of the plurality of external devices203.

The adaptor device200also includes an adaptor circuit260that includes a USB-to-UART interface circuit and a multiplexer circuit. The USB-to-UART interface circuit can include a USB hub and a plurality of USB-UART converters. These components are described in more detail below with reference toFIG.5.

In some embodiments of adaptor device200, the first interface210is configured to couple to USB signals, and the second interface220is configured to couple to JTAG signals.

In some embodiments of adaptor device200, each of the plurality third interfaces is configured to couple to UART signals and JTAG signals, and each of the plurality of external devices is configured to couple to both UART signals and JTAG signals.

FIG.3is a simplified schematic diagram illustrating dual-purpose connectors, according to an exemplary embodiment of the present disclosure. As shown inFIG.3, each of dual-purpose connectors310and320includes pins UART-Tx and UART-Rx configured to couple to UART signals Tx and Rx, respectively. Further, each of dual-purpose connectors310and320includes pins TDI, TDO, TCK, TMS, and TRST configured to couple to JTAG signals TDI, TDO, TCK, TMS, and TRST, respectively. Dual-purpose connectors310and320can also include other pins, such as pins for power and ground. In application, dual-purpose connector310can be used as third interface230in adaptor device200inFIG.2. Further, dual-purpose connector320can be used as a dual-purpose connector in external devices203inFIG.2that can be used for communication with dual-purpose connector230in adaptor device200inFIG.2.

FIGS.4A and4Bare perspective views of an adaptor device, according to an exemplary embodiment of the present disclosure.FIG.4Ais a bottom perspective view of adaptor device400, which is an example of adaptor device200described above in connection withFIG.2. As shown inFIG.4A, adaptor device400includes a printed circuit board (PCB)401and multiple components disposed on PCB401. These components include a USB connector410and a JTAG connector420disposed on PCB401. USB connector410is an example of the first interface210in adaptor device200ofFIG.2, and JTAG connector420is an example of the second interface210in adaptor device200ofFIG.2. Adaptor device400also has an adaptor circuit460, which is an example of adaptor circuit260in adaptor device200ofFIG.2.FIG.4Aalso shows switches452and jumpers454, whose functions will be described below with reference toFIG.5.

FIG.4Bis a top perspective view of adaptor device400. As shown inFIG.4B, adaptor device400includes a plurality of dual-purpose connectors430on PCB401. The plurality of dual-purpose connectors430are examples of the third interface230in adaptor device200described above in connection withFIG.2. In one example, each dual-purpose connector can be used to be connected to a solid-state drive (SSD), which also has an appropriate dual-purpose connector.

FIG.5is a simplified schematic diagram for an adaptor device, according to an exemplary embodiment of the present disclosure. As shown inFIG.5, adaptor device500includes a USB (Universal Serial Bus) connector510for coupling to USB signals, a JTAG (Joint Test Action Group) connector520for coupling to JTAG signals, and a plurality of dual-purpose connectors530configured for coupling to a corresponding plurality of external devices. Each of the plurality of dual-purpose connectors530is configured for coupling to both UART (Universal Asynchronous Receiver-Transmitter) signals and JTAG signals. In the example ofFIG.5, USB connector510is shown coupled to a processor501, which can be a person computer (PC), a laptop computer, or other types of processor. The JTAG connector is shown coupled to a JTAG equipment502, such as a JTAG compatible test equipment.

InFIG.5, adaptor device500also includes a USB-to-UART interface circuit540coupled to the USB connector510and the plurality of dual-purpose connectors530. USB-to-UART interface circuit540includes a USB hub542and a plurality of USB-UART converters544. Adaptor device500also includes a multiplexer circuit550coupled to the JTAG connector520and the plurality of dual-purpose connectors530. Multiplexer circuit550is configured to couple the JTAG connector520to one of the plurality of dual-purpose connectors530in response to a selection signal546from the USB-to-UART interface circuit540. In some embodiments, multiplexer circuit550can also select one of the plurality of dual-purpose connectors530in response to a switch552or jumpers554.

As shown inFIG.5, USB-to-UART interface circuit540includes a USB hub542and a plurality of USB-UART converter circuits544. USB-to-UART interface circuit540is configured to enable the USB connector510concurrent access to the plurality of dual-purpose connectors530.

In some embodiments, USB hub542can be a conventional USB hub that expands a USB port into several ports. In the example ofFIG.5, USB hub542expands one port couple to USB connector510into multiple ports, so that there are more ports available to connect devices to a host system, including eight ports for coupling to eight dual-purpose connectors and one port for coupling a selection signal to the multiplexer circuit550. All devices connected through a USB hub share the bandwidth available to that hub.

USB-to-UART converter circuits544can be a conventional USB to serial adapter having a USB processor chip which processes the USB signals. The USB processor sends the processed USB signals to a serial driver chip, which applies the correct voltages and sends the processed data signals to the serial output, in this case, the UART port. In some embodiments, a commercially available adaptor can be used, such as the FTDI USB-to-UART chip from Future Technology Devices International Limited, in the United Kingdom.

In some embodiments, multiplexer circuit550can include a multiplexer556and a plurality of switches557. Multiplexer circuit550is configured to receive the selection signal546derived from a signal received from the USB connector510, and, in response to a selection signal, couple the JTAG connector520to one of the plurality of dual-purpose connectors530. In alternative embodiments, multiplexer circuit550can also receive the selection signal from manual switches552or jumpers554.

InFIG.5, the plurality of dual-purpose connectors530are configured for coupling to a corresponding plurality of external devices503. In some embodiments, each of the plurality of external devices503is a solid-state drive (SSD). In this example,FIG.5shows eight dual-purpose connectors530and eight external devices503. However, the number of connectors and external devices can be varied according to the application.

InFIG.5, adaptor device500also includes level shifter circuits546coupled between the USB-to-UART converters544and the plurality of dual-purpose connectors530. The UART signals from external devices are at a 1.8V level. The 3.3V is used to support devices in the adaptor device. The level shifter circuits546are used to convert the 1.8V UART signal level to 3.3V, and vice versa. As shown inFIG.5, USB-to-UART interface circuit540, level shifter circuits546, and multiplexer circuit550are collectively referred to as adaptor circuit560. Adaptor circuit560is an example of circuit block that can be used as adaptor circuit260in adaptor device200inFIG.2.

As described above in connection toFIGS.4A and4B, the adaptor device can also include a Printed Circuit Board (PCB), upon which the USB connector510, the JTAG connector520, the plurality of dual-purpose connectors530, and adaptor circuit560are disposed.

FIG.6is a simplified block diagram illustrating a power supply circuit for an adaptor device, according to an exemplary embodiment of the present disclosure. In some embodiments, the adaptor components and the PCB receive operating power from a host device from a USB port. As shown inFIG.6, power supply circuit600can be part of adaptor device200ofFIG.2or adaptor device500ofFIG.5. Power supply circuit600includes a USB connector610for coupling to a host device, for example a processor, which provides power to the adaptor device. USB connector610can be the USB connector210ofFIG.2or USB connector510ofFIG.5. In some embodiments, USB connector610receives a 5V power supply from the host device. Power supply circuit600includes a first power converter620, a buck converter in this example, coupled to the USB connector610and converts the 5V voltage to a 3.3V power supply to the adaptor PCB. Power supply circuit600can also include a second power converter630, also a buck converter, coupled to the first power converter620and converts the 3.3V voltage to a 1.5V power supply to the adaptor PCB.FIG.6also shows serial buses640for coupling to the rest of the components in the adaptor circuit.

FIG.7is a simplified flowchart illustrating a method for accessing a plurality of external devices, according to an exemplary embodiment of the present disclosure. An example of an adaptor device implementing method700inFIG.7is described above in connection withFIG.2. As shown inFIG.7, the method700includes, at710, coupling a first processor through a first interface. The method includes, at720, coupling a second processor through a second interface, the second interface being different than the first interface. As shown inFIG.2, an adaptor device200includes a first interface210for coupling to a first processor201and a second interface220for coupling to a second processor202, the second interface being different than the first interface. Adaptor device200also includes a plurality of third interfaces230for coupling to a corresponding plurality of external devices203. The plurality of third interfaces230are different from the first and the second interfaces.

At730, the method includes receiving, at the first interface, a first signal from the first processor. At740, the method includes, in response to the first signal, coupling through a third interface to a plurality of external devices to enable the first processor concurrent access to the plurality of external devices. As shown inFIG.2, adaptor device200is configured to receive, at the first interface210, a first signal from the first processor201. In response to the first signal, adaptor device200couples to the plurality of third interfaces230to the plurality of external devices203to enable the first processor201concurrent access to the plurality of external devices203.

At750, the method includes receiving, at the first interface, a second signal from the first processor. At760, the method includes, in response to the second signal, coupling the second processor with a selected one of the plurality of external devices. As shown inFIG.2, adaptor device200is also configured to receive, at the first interface210, a second signal221from the first processor201. In response to the second signal221, adaptor device200couples the second processor202with a selected one of the plurality of external devices203.

In some embodiments, the first interface is configured to couple to USB signals, and the second interface is configured to couple to JTAG signals. In these embodiments, each of the plurality of external devices is configured to couple to both UART signals and JTAG signals. In some embodiments, the method also includes coupling the first interface to the plurality of external devices using a USB-to-UART interface circuit that includes a USB hub and a plurality of USB-to-UART converters.FIG.5illustrates a schematic diagram for an adaptor device500, which can be used to implement the features described above.

FIG.8is a simplified block diagram illustrating a solid-state storage system, in accordance with certain embodiments of the present disclosure. As shown, solid-state storage system800can include a solid-state storage device850and a storage controller860. Storage controller860, also referred to as a memory controller, is one example of a system that performs the techniques described herein. In some embodiments, storage controller860can be implemented on a semiconductor device, such as an application-specific integrated circuit (ASIC) or field programmable gate array (FPGA). Some of the functions can also be implemented in firmware or software. Solid-state storage system800is an example of a solid-state drive (SSD), which can be coupled to an adaptor device described above in connection toFIGS.2-7.

Controller804can include one or more processors806and memories808for performing the control functions described above. Storage controller860can also include lookup tables810, which can include a table for degraded blocks and a table for bad blocks, etc. Registers814can be used to store data for control functions, such as threshold values for degraded block counts.

Controller804can be coupled to solid-state storage850through a storage interface802. Error-correction decoder812(e.g., an LDPC decoder or a BCH decoder) can perform error-correction decoding on the read data and send the corrected data to controller804. Controller804can identify the pages with read failures to garbage collector816, which performs corrective processing on those pages (e.g., by copying the data, with or without error correction decoding, to a new location).

FIG.9is a simplified block diagram illustrating an apparatus that may be used to implement various embodiments, according the present disclosure.FIG.9is merely illustrative of an embodiment incorporating the present disclosure and does not limit the scope of the invention as recited in the claims. One of ordinary skill in the art would recognize other variations, modifications, and alternatives. In one embodiment, computer system900typically includes a monitor910, a computer920, user output devices930, user input devices940, communications interface950, and the like.

As shown inFIG.9, computer920may include a processor(s)960that communicates with a number of peripheral devices via a bus subsystem990. These peripheral devices may include user output devices930, user input devices940, communications interface950, and a storage subsystem, such as random-access memory (RAM)970and disk drive980. As an example, a disk drive980can include SSD implemented with non-volatile memory devices, such as SSD203depicted inFIG.2, SSD503inFIG.5, or solid-state storage system800inFIG.8. Further, computer system900is an example of a device that can be used as first processor201or second processor202inFIG.2, or as processor501inFIG.5.

User input devices940include all possible types of devices and mechanisms for inputting information to computer system920. These may include a keyboard, a keypad, a touch screen incorporated into the display, audio input devices such as voice recognition systems, microphones, and other types of input devices. In various embodiments, user input devices940are typically embodied as a computer mouse, a trackball, a trackpad, a joystick, a wireless remote, a drawing tablet, a voice command system, an eye-tracking system, and the like. User input devices940typically allow a user to select objects, icons, text, and the like that appear on the monitor910via a command, such as a click of a button or the like.

User output devices930include all possible types of devices and mechanisms for outputting information from computer920. These may include a display (e.g., monitor910), non-visual displays, such as audio output devices.

Communications interface950provides an interface to other communication networks and devices. Communications interface950may serve as an interface for receiving data from and transmitting data to other systems. Embodiments of communications interface950typically include an Ethernet card, a modem (telephone, satellite, cable, integrated services digital network (ISDN)), (asynchronous) digital subscriber line (DSL) unit, FireWire interface, USB interface, and the like. For example, communications interface950may be coupled to a computer network, to a FireWire bus, or the like. In other embodiments, communications interfaces950may be physically integrated on the motherboard of computer920and may be a software program, such as soft DSL or the like.

In various embodiments, computer system900may also include software that enables communications over a network such as the Hypertext Transfer Protocol (HTTP), the Transmission Control Protocol and the Internet Protocol (TCP/IP), the Real Time Streaming Protocol and Real-time Transport Protocol (RTSP/RTP), and the like. In alternative embodiments of the present disclosure, other communications software and transfer protocols may also be used, for example Internetwork Packet Exchange (IPX), User Datagram Protocol (UDP), or the like. In some embodiments, computer920includes one or more Xeon microprocessors from Intel as processor(s)960. Further, in one embodiment, computer920includes a UNIX-based operating system.

RAM970and disk drive980are examples of tangible media configured to store data, such as embodiments of the present disclosure, including executable computer code, human-readable code, or the like. Other types of tangible media include floppy disks, removable hard disks, optical storage media, such as CD-ROMS, DVDs and bar codes, semiconductor memories, such as flash memories, non-transitory read-only memories (ROMs), battery-backed volatile memories, networked storage devices, and the like. RAM970and disk drive980may be configured to store the basic programming and data constructs that provide the functionality of the present disclosure.

Software code modules and instructions that provide the functionality of the present invention may be stored in RAM970and disk drive980. These software modules may be executed by processor(s)960. RAM970and disk drive980may also provide a repository for storing data used in accordance with the present disclosure.

RAM970and disk drive980may include a number of memories, including a main RAM for storage of instructions and data during program execution and a ROM in which fixed non-transitory instructions are stored. RAM970and disk drive980may include a file storage subsystem providing persistent (non-volatile) storage for program and data files. RAM970and disk drive980may also include removable storage systems, such as removable flash memory.

Bus subsystem990provides a mechanism for letting the various components and subsystems of computer920communicate with each other as intended. Although bus subsystem990is shown schematically as a single bus, alternative embodiments of the bus subsystem may utilize multiple busses. Bus system990may be a Peripheral Component Interconnect (PCI) Express bus that may be implemented using Peripheral Component Interconnect Express (PCIe) physical layer (PHY) embodiments of the present disclosure.

FIG.9is representative of a computer system capable of embodying the present disclosure. It will be readily apparent to one of ordinary skill in the art that many other hardware and software configurations are suitable for use with the present disclosure. For example, the computer may be a desktop, portable, rack-mounted, or tablet configuration. Additionally, the computer may be a series of networked computers. Further, the use of other microprocessors are contemplated, such as Pentium™ or Itanium™ microprocessors; Opteron™ or AthlonXP™ microprocessors from Advanced Micro Devices, Inc.; and the like. Further, other types of operating systems are contemplated, such as Windows®, WindowsXP®, WindowsNT®, or the like from Microsoft Corporation; Solaris from Sun Microsystems; LINUX; UNIX; and the like. In still other embodiments, the techniques described above may be implemented upon a chip or an auxiliary processing board.

Various embodiments of the present disclosure can be implemented in the form of logic in software or hardware or a combination of both. The logic may be stored in a computer-readable or machine-readable non-transitory storage medium as a set of instructions adapted to direct a processor of a computer system to perform a set of steps disclosed in embodiments of the present disclosure. The logic may form part of a computer program product adapted to direct an information-processing device to perform a set of steps disclosed in embodiments of the present disclosure. Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will appreciate other ways and/or methods to implement the present disclosure.

The data structures and code described herein may be partially or fully stored on a computer-readable storage medium and/or a hardware module and/or hardware apparatus. A computer-readable storage medium includes, but is not limited to, volatile memory, non-volatile memory, and magnetic and optical storage devices, such as disk drives, magnetic tape, CDs, DVDs, or other media, now known or later developed, that are capable of storing code and/or data. Hardware modules or apparatuses described herein include, but are not limited to, ASICs, FPGAs, dedicated or shared processors, and/or other hardware modules or apparatuses now known or later developed.

The methods and processes described herein may be partially or fully embodied as code and/or data stored in a computer-readable storage medium or device, so that when a computer system reads and executes the code and/or data, the computer system performs the associated methods and processes. The methods and processes may also be partially or fully embodied in hardware modules or apparatuses, so that when the hardware modules or apparatuses are activated, they perform the associated methods and processes. The methods and processes disclosed herein may be embodied using a combination of code, data, and hardware modules or apparatuses.

The embodiments disclosed herein are not to be limited in scope by the specific embodiments described herein. Various modifications of the embodiments of the present disclosure, in addition to those described herein, will be apparent to those of ordinary skill in the art from the foregoing description and accompanying drawings. Further, although some of the embodiments of the present disclosure have been described in the context of a particular implementation in a particular environment for a particular purpose, those of ordinary skill in the art will recognize that the disclosure's usefulness is not limited thereto and that the embodiments of the present disclosure can be beneficially implemented in any number of environments for any number of purposes.