Voltage buffer and source driver thereof

A voltage buffer and the source driver thereof are disclosed. The above-mentioned voltage buffer includes an operational amplifier and an overdriving unit, wherein the operational amplifier outputs an output voltage. The overdriving unit is coupled between an input voltage and the operational amplifier for comparing the input voltage with the output voltage and outputting an overdriving voltage to the positive input terminal of the operational amplifier. Herein if the input voltage is greater than the output voltage, the overdriving voltage is greater than the input voltage; if the input voltage is less than the output voltage, the overdriving voltage is less than the input voltage; if the input voltage is equal to the output voltage, the overdriving voltage is equal to the input voltage.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 95129854, filed Aug. 15, 2006. All disclosure of the Taiwan application is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a voltage buffer. More particular, the present invention relates to a voltage buffer and the source driver thereof which are capable of enhancing the slew rate.

2. Description of Related Art

A conventional voltage buffer is usually used to deliver a voltage signal, enhance the driving capability and avoid the output voltage from being affected by a load. The voltage buffer applied in the source driver of an LCD usually comprises an operational amplifier.

FIG. 1is a schematic circuit drawing of a conventional voltage buffer, wherein the voltage buffer100has a negative feedback structure implemented by coupling the output terminal of the operational amplifier110to the negative input terminal thereof, while the positive input terminal of the operational amplifier110is coupled to an input voltage VINT. In consideration of a virtual short circuit, the output voltage VOUT generated at the output terminal of the operational amplifier110is theoretically equal to the input voltage VINT and varies therewith.

The voltage buffer shown inFIG. 1is applied in the source driver of an LCD. Since the load capacitance of the panel end to be driven by the source driver is quite large, the voltage buffer100may fail to quickly regulate the output voltage VOUT to the same level as the input voltage VINT in response to a change of the input voltage VINT. That is to say, the slew rate of the voltage buffer100gets lower due to a load.

Along with the increase of the dimension of an LCD, the load capacitance thereof would get larger. If the slew rate of the voltage buffer of a source driver is not effectively improved to adapt the large LCD trend, it is for sure that the LCD display quality will be degraded.

SUMMARY OF THE INVENTION

Accordingly, an objective of the present invention is to provide a voltage buffer for converting an input voltage into an overdriving voltage. The overdriving voltage varies with the input voltage, and the variation of the overdriving voltage is greater than the variation of the input voltage, so as to speed up the change of the output voltage and further to enhance the slew rate of the voltage buffer.

Another objective of the present invention is to provide a source driver having a higher slew rate by using the overdriving scheme, so that the source driver is suitable for driving a larger load capacitor and improving the LCD display quality.

To achieve the above-mentioned or other objectives, the present invention provides a voltage buffer, which includes an operational amplifier and an overdriving unit. The operational amplifier has a positive input terminal, a negative input terminal and an output terminal, wherein the output terminal of the operational amplifier is coupled to the negative input terminal, while the output terminal thereof outputs an output voltage. The overdriving unit is coupled between the input voltage and the operational amplifier for comparing the input voltage with the output voltage and outputting the overdriving voltage to the positive input terminal of the operational amplifier. Herein if the input voltage is greater than the output voltage, the overdriving voltage is greater than the input voltage; if the input voltage is less than the output voltage, the overdriving voltage is less than the input voltage; if the input voltage is equal to the output voltage, the overdriving voltage is equal to the input voltage.

In an embodiment of the present invention, the above-mentioned overdriving unit includes a voltage detector, a control unit and a voltage-regulating circuit. The voltage detector is for comparing the input voltage with the output voltage and outputting a voltage-increasing signal and a voltage-decreasing signal. The control unit is coupled to the voltage detector and regulates the output of the voltage-regulating circuit according to the voltage-increasing signal and the voltage-decreasing signal. The voltage-regulating circuit is coupled to the control unit and regulates the overdriving voltage level according to the output of the control unit.

In another embodiment of the present invention, the above-mentioned voltage-regulating circuit includes a capacitor having a first terminal and a second terminal, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch and a seventh switch. The first switch is coupled between a charging voltage and the first terminal of the capacitor. The second switch is coupled between the second terminal of the capacitor and a ground terminal. The third switch is coupled between the second terminal of the capacitor and the input voltage, and the fourth switch is coupled between the first terminal of the capacitor and the positive input terminal of the operational amplifier. The fifth switch is coupled between the input voltage and the first terminal of the capacitor, and the sixth switch is coupled between the second terminal of the capacitor and the positive input terminal of the operational amplifier. And, the seventh switch is coupled between the positive input terminal of the operational amplifier and the input voltage.

In an embodiment of the present invention, the above-mentioned control unit outputs a charging signal, a first path signal, a second path signal and a restoration signal according to the voltage-increasing signal and the voltage-decreasing signal. If the charging signal is enabled, the first switch and the second switch are on; if the first path signal is enabled, the third switch and the fourth switch are on; if the second path signal is enabled, the fifth switch and the sixth switch are on; if the restoration signal is enabled, the seventh switch is on.

In another embodiment of the present invention, the above-mentioned voltage-regulating circuit includes a first resistor, a second resistor, a first current source, a second current source, a first switch, a second switch and a third switch. The first resistor is coupled between the first current source and the input voltage, while another terminal of the first current source is coupled to a first operation voltage. The second resistor is coupled between the input voltage and the second current source, while another terminal of the second current source is coupled to a second operation voltage. A terminal of the first switch is coupled to the common node of the first resistor and the first current source, while another terminal of the first switch is coupled to the positive input terminal of the operational amplifier. A terminal of the second switch is coupled to the common node of the second resistor and the second current source, while another terminal of the second switch is coupled to the positive input terminal of the operational amplifier. The third switch is coupled between the positive input terminal of the operational amplifier and the input voltage.

In another embodiment of the present invention, the control unit outputs the first path signal, the second path signal and the restoration signal according to the voltage-increasing signal and the voltage-decreasing signal. If the first path signal is enabled, the first switch is on; if the second path signal is enabled, the second switch is on; if the restoration signal is enabled, the third switch is on.

To achieve the above-mentioned and other objectives, the present invention provides a source driver suitable for driving an LCD panel. The source driver includes a driving unit and a plurality of the above-mentioned voltage buffers. The driving unit generates a plurality of first driving voltages according to the input display signals. The voltage buffers are coupled to the driving unit, wherein the voltage buffers are corresponding to the first driving voltages in one-to-one manner, and each voltage buffer outputs a second driving voltage according to the corresponding first driving voltage.

Each of the voltage buffers has an operational amplifier and an overdriving unit, the overdriving unit outputs an overdriving voltage to the operational amplifier according to the corresponding first driving voltage. Each of the voltage buffers shortens the time for stabilizing the corresponding second driving voltage according to the corresponding overdriving voltage, so as to make the LCD panel have a better display quality. Herein the first driving voltage refers to the input voltage of the above-mentioned voltage buffer, while the second driving voltage refers to the output voltage of the above-mentioned voltage buffer.

In response to a variation of the input voltage, the present invention uses the overdriving unit to enlarge the voltage difference between the input terminal and the output terminal of the voltage buffer. In other words, the overdriving voltage varies with the variation of the input voltage, and the variation amplitude of the overdriving voltage is greater than the variation amplitude of the input voltage. Consequently, driven by the larger voltage, the voltage level at the output terminal of the voltage buffer is altered more quickly, which contributes to enhance the slew rate thereof. For a source driver application using the voltage buffer thereof, the display quality would be effectively improved since the source driver is capable of driving the LCD panel with larger load capacitance.

DESCRIPTION OF THE EMBODIMENTS

FIG. 2is a circuit block diagram of a voltage buffer according to an embodiment of the present invention. A voltage buffer200includes an operational amplifier210and an overdriving unit220. The operational amplifier210has a positive input terminal, a negative input terminal and an output terminal, wherein the output terminal is coupled to the negative input terminal to form a negative feedback loop. The output terminal of the operational amplifier210outputs an output voltage VOUT. The overdriving unit220is coupled between an input voltage VINT and the operational amplifier210for comparing the input voltage VINT with the output voltage VOUT and outputting an overdriving voltage ODV to the positive input terminal of the operational amplifier210.

According to the comparison result of the overdriving unit220, if the input voltage VINT is greater than the output voltage VOUT, the overdriving voltage ODV is greater than the input voltage VINT; if the input voltage VINT is less than the output voltage VOUT, the overdriving voltage ODV is less than the input voltage VINT; if the input voltage VINT is equal to the output voltage VOUT, the overdriving voltage ODV is equal to the input voltage VINT.

In other words, the overdriving unit220would convert the input voltage VINT into the overdriving voltage ODV according to the variation of the input voltage VINT and enlarge the voltage difference between the overdriving voltage ODV and the output voltage VOUT, so as to more quickly alter the voltage level of the output voltage VOUT of the operational amplifier210to fit the voltage level of the input voltage VINT and enhance the slew rate of the voltage buffer200.

The overdriving unit220includes a voltage detector222, a control unit224and a voltage-regulating circuit226. The voltage detector222is for comparing the input voltage VINT with the output voltage VOUT and outputting a voltage-increasing signal UP and a voltage-decreasing signal DN to the control unit224according to the comparison result. The control unit224is coupled to the voltage detector222and regulates the output of the voltage-regulating circuit226according to the voltage-increasing signal UP and the voltage-decreasing signal DN. The voltage-regulating circuit226regulates the voltage level of the overdriving voltage ODV according to the output of the control unit224(in the present embodiment, the output from the control unit224is generally termed as a control signal CS).

When the input voltage VINT is changed, the overdriving voltage ODV varies therewith in a grater amplitude too. For example, if the input voltage VINT is increased by X volt where X is a positive number, the overdriving voltage ODV would be increased by (X+dV) where dV is a positive number. On the contrary, if the input voltage VINT is decreased by X volt, the overdriving voltage ODV would be decreased by (X+dV) too. Due to an enlarged voltage difference between the overdriving voltage ODV and the output voltage VOUT, the driving capability of the operational amplifier210is enhanced, which speeds up the altering course of the output voltage VOUT and increases the slew rate of the voltage buffer200.

Since the voltage level of the overdriving voltage ODV is altered and the slew rate of the voltage buffer200gets advanced mainly through detecting the variation of the input voltage VINT in the present invention, hence, the implementation of the voltage detector222, the control unit224and the voltage-regulating circuit226is not limited to one mode. In fact, the overdriving voltage ODV can be regulated by using a voltage-regulating circuit226in different structures in association with a control unit224in different structures. In the following, several circuit architectures are introduced to describe the different implementations of the voltage detector222, the control unit224and the voltage-regulating circuit226in the present embodiment.

The implementation of the voltage-regulating circuit226is explained as follows.FIG. 3Ais a schematic circuit drawing of a voltage-regulating circuit according to an embodiment of the present invention. In the embodiment ofFIG. 3A, the control signal CS output from the control unit224includes a charging signal PH1, a first path signal PH2P, a second path signal PH2N and a restoration signal PH2. The circuit architecture of the control unit224in the embodiment ofFIG. 3Ais illustrated byFIGS. 7A and 7B.

In the embodiment ofFIG. 3A, a voltage-regulating circuit226is coupled to the control unit224, regulates the voltage level of the overdriving voltage ODV according to the first path signal PH2P and the second path signal PH2N and makes the overdriving voltage ODV equal to the input voltage VINT according to the restoration signal PH2.

When the input voltage VINT is changed, the charging signal PH1generates an enabling duration to make the voltage-regulating circuit226store a predetermined voltage in advance, for example, a capacitor is used to store the predetermined voltage. After that, the control unit224makes the first path signal PH2P or the second path signal PH2N enabled during an overdriving duration according to the comparison result between the input voltage VINT and the output voltage VOUT, i.e. the voltage levels of the voltage-increasing signal UP and the voltage-decreasing signal DN. During an overdriving duration, however, only one of the first path signal PH2P and the second path signal PH2N is enabled.

If the input voltage VINT is greater than the output voltage VOUT, the first path signal PH2P is enabled in an overdriving duration; if the input voltage VINT is less than the output voltage VOUT, the second path signal PH2N is enabled in the above-mentioned overdriving duration. After the above-mentioned overdriving duration, the restoration signal PH2is enabled, which makes the overdriving voltage ODV equal to the input voltage VINT and avoids the voltage level of the output voltage VOUT from being altered excessively. The period of a clock signal CLK varies with the input voltage VINT; therefore, once the next input voltage VINT is input into the overdriving unit220, an overdriving control flow is repeated again.

The voltage-regulating circuit226outputs the overdriving voltage ODV to the operational amplifier210. As shown byFIG. 3A, the voltage-regulating circuit226includes seven switches S1-S7and a capacitor C. The capacitor C has a first terminal CP1and a second terminal CP2, the switch S1is coupled between the charging voltage dV and the first terminal CP1of the capacitor C. The switch S2is coupled between the second terminal CP2of the capacitor C and a ground terminal GND. The switch S3is coupled between the second terminal CP2of the capacitor C and the input voltage VINT and the switch S4is coupled between the first terminal CP1of the capacitor C and the positive input terminal of the operational amplifier210. The switch S5is coupled between the input voltage VINT and the first terminal CP1of the capacitor C and the switch S6is coupled between the second terminal CP2of the capacitor C and the positive input terminal of the operational amplifier210. The switch S7is coupled between the positive input terminal of the operational amplifier210and the input voltage VINT. In the embodiment, the charging voltage dV is a positive voltage.

If the charging signal PH1is enabled, the switch S1and the switch S2are on, which makes the charging voltage dV charge to the capacitor C, and a positive voltage difference is generated between the first terminal CP1and the second terminal CP2of the capacitor C. Then, if the input voltage VINT is greater than the output voltage VOUT, the first path signal PH2P is enabled in an overdriving duration and the switches S3and S4are on, which further makes the overdriving voltage ODV greater than the input voltage VINT. Theoretically, the overdriving voltage ODV should be greater than the input voltage VINT due to the voltage stored in the capacitor C. The voltage difference between the overdriving voltage ODV and the input voltage VINT depends on the amount of the charging voltage dV which is preset to a different value according to the different demand of an application.

If the input voltage VINT is less than the output voltage VOUT, the second path signal PH2N is enabled during the above-mentioned overdriving duration, and the switches S5and S6are on. The voltage difference between both terminals of the capacitor C would result in a negative voltage difference affecting the input voltage VINT, so as to make the overdriving voltage ODV less than the input voltage VINT. In this way, the operational amplifier210is able to speed up the course for the output voltage VOUT to be declined to the level of the input voltage VINT. After the above-mentioned overdriving duration, the restoration signal PH2is enabled to turn on the seventh switch, meanwhile the overdriving voltage ODV would be equal to the input voltage VINT due to the turning on of the switch S7.

In summary of the above described embodiment ofFIG. 3A, when the input voltage VINT is changed, the voltage-regulating circuit226would store charges first, followed by regulating the overdriving voltage ODV through controlling the signal-delivering path. When the input voltage VINT gets higher, the overdriving voltage ODV gets higher therewith too; when the input voltage VINT gets lower, the overdriving voltage ODV gets lower therewith and the variation amplitude of the overdriving voltage ODV is greater than the variation amplitude of the input voltage VINT. Finally, the level of the overdriving voltage ODV is regulated to the input voltage VINT. Herein during the charging duration, since the positive input terminal of the operational amplifier210has an equivalent parasitic capacitance relative to the ground, the overdriving voltage ODV will not suddenly drop during the enabling duration of the charging signal PH1. As long as the enabling duration of the charging signal PH1is adjusted, the problem of the voltage drop of the overdriving voltage ODV can be alleviated.

In another embodiment of the present invention, when the charging signal PH1or the restoration signal PH2is enabled, or both the first path signal PH2P and the second path signal PH2N are disabled (when the input voltage VINT is equal to the output voltage VOUT), the switches S1, S2and S7are on at the same time. Referring toFIGS. 8A and 8B, the circuit architecture of the control unit associated with the embodiment ofFIG. 3Ais illustrated in the figures. When the voltage detector detects the variation of the input voltage VINT (getting higher or lower), one of the first path signal PH2P and the second path signal PH2N is enabled, so as to regulate the overdriving voltage ODV. When the input voltage VINT gets higher, the first path signal PH2P is enabled and the overdriving voltage ODV is greater than the input voltage VINT; when the input voltage VINT gets lower, the second path signal PH2N is enabled and the overdriving voltage ODV is less than the input voltage VINT; when the input voltage VINT is equal to the output voltage VOUT, the restoration signal PH2is enabled and the overdriving voltage ODV would be equal to the input voltage VINT due to the turning on of the switch S7.

While the restoration signal PH2is enabled, the charging signal PH1is enabled too (note that in another embodiment of the present invention, instead of the charging signal PH1, the restoration signal PH2is used to control the switches S1and S2), thus, the switches S1and S2are on, which enables the charging voltage dV to charge the capacitor C and generates a positive voltage difference between the first terminal CP1and the second terminal CP2of the capacitor C. When the input voltage VINT is changed again, one of the first path signal PH2P and the second path signal PH2N would be immediately enabled to regulate the overdriving voltage ODV without charging the capacitor C in advance. In this way, not only the level of the overdriving voltage ODV is retained, but also the problem of the voltage drop of the overdriving voltage ODV as described in the previous embodiment can be avoided; moreover, the speed of the course of altering the overdriving voltage ODV and the slew rate of the voltage buffer200are increased. In addition, there is another advantage herein that the clock signal CLK and the nonoverlapping clock-generating circuit (710as shown inFIG. 7A) are exempted from being employed. Therefore, the implementation of the control unit800inFIG. 8Ais much simpler than the control unit700inFIG. 700.

The present embodiment mainly uses the capacitor C to store a voltage difference and converts the input voltage VINT into the overdriving voltage ODV through controlling the signal-delivering path. Due to a larger voltage difference between the overdriving voltage ODV and the output voltage VOUT, the operational amplifier210is capable of regulating the voltage level of the output voltage VOUT thereof more quickly, which accordingly increases the slew rate of the voltage buffer.

In another embodiment of the present invention, the voltage-regulating circuit226is implemented by another circuit.FIG. 3Bis a schematic circuit drawing of a voltage-regulating circuit according to another embodiment of the present invention. In the embodiment ofFIG. 3B, the control signal CS output from the control unit224includes a first path signal PH2P, a second path signal PH2N and a restoration signal PH2. The circuit architecture of the control unit224associated with the embodiment ofFIG. 3Bcan refer toFIGS. 8A and 8B. In the embodiment ofFIG. 3B, if the input voltage VINT is greater than the output voltage VOUT, the first path signal PH2P is enabled, and both the second path signal PH2N and the restoration signal PH2are disabled; if the input voltage VINT is less than the output voltage VOUT, both the first path signal PH2P and the restoration signal PH2are disabled and the second path signal PH2N is enabled; if the input voltage VINT is equal to the output voltage VOUT, the restoration signal PH2is enabled, and both the first path signal PH2P and the second path signal PH2N are disabled.

The voltage-regulating circuit300is coupled to the positive input terminal of the operational amplifier210for regulating the overdriving voltage ODV. The voltage-regulating circuit300includes current sources I31and I32, resistors R31and R32and switches S8, S9and S10. The resistor R31is coupled between the current source I31and the input voltage VINT, while another terminal of the current source I31is coupled to a first operation voltage V1. The resistor R32is coupled between the current source I32and the input voltage VINT, while another terminal of the current source I32is coupled to a second operation voltage V2. A terminal of the switch S8is coupled to the common node of the resistor R31and the current source I31, while another terminal thereof is coupled to the positive input terminal of the operational amplifier210.

A terminal of the switch S9is coupled to common node of the resistor R32and the current source I32, while another terminal thereof is coupled to the positive input terminal of the operational amplifier210. The switch S10is coupled between the positive input terminal of the operational amplifier210and the input voltage VINT. Herein, if the first path signal PH2P is enabled, the switch S8is on; if the second path signal PH2N is enabled, the switch S9is on; if the restoration signal PH2is enabled, the switch S10is on.

In other words, when the input voltage VINT is greater than the output voltage VOUT, the switch S8is on and the overdriving voltage ODV is equal to the sum of the input voltage VINT and the voltage difference across the resistor R31where the current of the current source I31passes through; when the input voltage VINT is less than the output voltage VOUT, the switch S9is on and the overdriving voltage ODV is equal to the input voltage VINT less the voltage difference across the resistor R32where the current of the current source I32passes through; when the input voltage VINT is equal to the output voltage VOUT, the switch S10is on and the overdriving voltage ODV is equal to the input voltage VINT. Therefore, in response to a variation of the input voltage VINT, one of the switches S8and S9is on according to the relative magnitude between the input voltage VINT and the output voltage VOUT, so that the overdriving voltage ODV is regulated to VINT+I31×R31or VINT−I32×R32. Once the output voltage VOUT gets the same as the input voltage VINT, the switch S10is on and the overdriving voltage ODV is equal to the input voltage VINT. The present embodiment mainly uses a current of a current source passing through a resistor to generate a voltage difference between both ends of the resistor, and then converts the input voltage VINT into the overdriving voltage ODV through controlling the signal-delivering path. Herein, due to a larger level difference between the overdriving voltage ODV and the output voltage VOUT, the operational amplifier210is able to regulate the level of the output voltage VOUT more quickly, which further enhances the slew rate of the voltage buffer.

In the following, the voltage detector in the embodiment is explained in more detail. The voltage detector222is mainly for comparing the input voltage VINT with the output voltage VOUT and accordingly outputting a voltage-increasing signal UP and a voltage-decreasing signal DN. The control unit224generates an appropriate control signal to control the voltage-regulating circuit and regulate the level of the overdriving voltage ODV according to the comparison result.

FIG. 4is a schematic circuit drawing of a voltage detector according to an embodiment of the present invention. A voltage detector400includes PMOS transistors P41-P43, NMOS transistors N41-N43and current sources I1, I2and I3. The PMOS transistor P41and the NMOS transistor N41are in series connection to each other and together coupled between the operation voltage VDD and the current source I1, while the gate of the NMOS transistor N41is coupled to the input voltage VINT.

The PMOS transistor P42and the NMOS transistor N42are in series connection to each other and together coupled between the operation voltage VDD and the current source I1. The gate of the NMOS transistor N42is coupled to the output voltage VOUT, the gate of the PMOS transistor P42is coupled to the gate of the PMOS transistor P41and the gate of the PMOS transistor P42is coupled to the common node of the PMOS transistor P42and the NMOS transistor N42. The current source I2and the NMOS transistor N43are in series connection to each other and together coupled between the operation voltage VDD and the ground terminal GND, while the gate of the NMOS transistor N43is coupled to the common node of the PMOS transistor P41and the NMOS transistor N41. The common node of the current source I2and the NMOS transistor N43outputs the voltage-decreasing signal DN.

The PMOS transistor P43and the current source I3are in series connection to each other and together coupled between the operation voltage VDD and the ground terminal GND, the gate of the PMOS transistor P43is coupled to the common node of the PMOS transistor P41and the NMOS transistor N41and the common node of the PMOS transistor P43and the current source I3outputs the voltage-increasing signal UP.

Since both gate voltages of the PMOS transistor P41and the PMOS transistor P42are equal to each other, and the sources thereof are coupled to the operation voltage VDD, therefore, the drain voltages of the PMOS transistors P41and P42are regulated mainly through changing the currents passing through the PMOS transistors P41and P42. When the input voltage VINT is greater than the output voltage VOUT, the current passing through the PMOS transistor P41gets larger (must be equal to the current passing through the NMOS transistor N41). Thus, the drain voltage level of the PMOS transistor P41would be dropped to keep the circuit in balance. In the embodiment, the voltage output from the drain of the PMOS transistor P41is termed as sensing voltage VSE.

To keep the current of the PMOS transistor P43unchanged (must be the same as the current source I3), the drain voltage level of the PMOS transistor P43would ascend therewith when the sensing voltage VSE drops, that is to say the voltage level of the voltage-increasing signal UP would ascend. In the embodiment, the voltage level of the ascended voltage-increasing signal UP is considered as a logic high-level. On the other hand, in response to the dropping sensing voltage VSE, in order to make the same current pass through the NMOS transistor N43(must be the same as the current source I2), the drain voltage level of the NMOS transistor N43would ascend therewith; that is to say, the voltage level of the voltage-decreasing signal DN would ascend. In the embodiment, the voltage level of the ascended voltage-decreasing signal DN is considered as a logic high-level as well.

On the contrary, when the input voltage VINT is less than the output voltage VOUT, the sensing voltage VSE would ascend. Thus, the voltage-increasing signal UP and the voltage-decreasing signal DN would retain a lower voltage level. In the embodiment, the above-mentioned voltage-increasing signal UP and the voltage-decreasing signal DN with a lower voltage level are considered as a logic low-level.

Under another status that the input voltage VINT is equal to the output voltage VOUT, all of the PMOS transistors P41and P42and the NMOS transistors N41and N42are on, while the gate voltages of the PMOS transistor P43and the NMOS transistor N43are sensing voltages VSE. Therefore, the logic levels of the voltage-increasing signal UP and the voltage-decreasing signal DN are determined by the current amounts of the current sources I3and I2. In the embodiment, when the input voltage VINT is equal to the output voltage VOUT, the voltage-increasing signal UP becomes a logic low-level, while the voltage-decreasing signal DN becomes a logic high-level.

As described inFIG. 4, the relative magnitude between the input voltage VINT and the output voltage VOUT can be decided by using the voltage level variations of the voltage-increasing signal UP and the voltage-decreasing signal DN.

FIG. 5is a schematic circuit drawing of a voltage detector according to another embodiment of the present invention. The major difference ofFIG. 5fromFIG. 4lies in the circuit for generating the sensing voltage VSE. A voltage detector500includes PMOS transistors P51-P53, NMOS transistors N51-N53and current sources I1, I2and I3. The PMOS transistor P51and the NMOS transistor N51are in series connection to each other and together coupled between the current source I1and the ground terminal GND, while the gate of the PMOS transistor P51is coupled to the input voltage VINT. The PMOS transistor P52and the NMOS transistor N52are in series connection to each other and together coupled between the current source I1and the ground terminal GND, while the gate of the PMOS transistor P52is coupled to the output voltage VOUT. The gates of the NMOS transistors N52and N51are coupled to the drain of the NMOS transistor N52. The common node of the PMOS transistor P51and the NMOS transistor N51outputs the sensing voltage VSE.

The sensing voltage VSE is coupled to the gates of the NMOS transistor N53and the PMOS transistor P53, respectively. The common node of the current source I2and the NMOS transistor N53outputs the voltage-decreasing signal DN, while the common node of the current source I3and the PMOS transistor P53outputs the voltage-increasing signal UP.

When the input voltage VINT is equal to the output voltage VOUT, the voltage level of the sensing voltage VSE can be regulated by the current passing through the current source I1, while the voltage-increasing signal UP and the voltage-decreasing signal DN are affected by the sensing voltage VSE to vary therewith. In the embodiment, when the input voltage VINT is equal to the output voltage VOUT, the voltage-increasing signal UP is logic low, while the voltage-decreasing signal DN is logic high, which are the same as the above-mentioned embodiment inFIG. 4.

When the input voltage VINT is greater than the output voltage VOUT, the sensing voltage VSE drops, which further makes both the voltage-increasing signal UP and the voltage-decreasing signal DN are logic high. When the input voltage VINT is less than the output voltage VOUT, the sensing voltage VSE ascends, which makes both the voltage-increasing signal UP and the voltage-decreasing signal DN are logic low.

FIG. 6Ais a schematic circuit drawing of a voltage detector according to another embodiment of the present invention. A voltage detector600includes NMOS transistors N61-N67, PMOS transistors P61-P67and current sources I61-I62and I2-I3.

Both the gate of the NMOS transistor N61and the gate of the PMOS transistor P61are coupled to the output voltage VOUT, while both the gate of the NMOS transistor N62and the gate of the PMOS transistor P62are coupled to the input voltage VINT. The current source I61is coupled to the source of the PMOS transistor P61and the source of the PMOS transistor P62, respectively. The current source I62is coupled to the source of the NMOS transistor N61and the source of the NMOS transistor N62, respectively.

The PMOS transistor P63is coupled between the operation voltage VDD and the drain of the NMOS transistor N61, the PMOS transistor P64is coupled between the operation voltage VDD and the drain of the NMOS transistor N62, and both the gate of the PMOS transistor P64and the gate of the PMOS transistor P63are coupled to a bias voltage Vb0. The source of the PMOS transistor P65is coupled to the drain of the PMOS transistor P63, the source of the PMOS transistor P66is coupled to the drain of the PMOS transistor P64, and both the gate of the PMOS transistor P66and the gate of the PMOS transistor P65are coupled to a bias voltage Vb1.

The drain of the NMOS transistor N63is coupled to the drain of the PMOS transistor P65, while the source of the NMOS transistor N63is coupled to the drain of the PMOS transistor P61. The drain of the NMOS transistor N64is coupled to the drain of the PMOS transistor P66, the source of the NMOS transistor N64is coupled to the drain of the PMOS transistor P62, and both the gate of the NMOS transistor N64and the gate of the NMOS transistor N63are coupled to a bias voltage Vb2.

The NMOS transistor N65is coupled between the source of the NMOS transistor N63and the ground terminal GND, while the gate of the NMOS transistor N65is coupled to the drain of the NMOS transistor N63. The NMOS transistor N66is coupled between the source of the NMOS transistor N64and the ground terminal GND, while the gate of the NMOS transistor N66is coupled to the gate of the NMOS transistor N65. The NMOS transistor N67is coupled between the current source I2and the ground terminal GND, while the gate of the NMOS transistor N67is coupled to the common node of the PMOS transistor P66and the NMOS transistor N64.

The PMOS transistor P67is coupled between the operation voltage VDD and the current source I3, while the gate of the PMOS transistor P67is coupled to the common node of the PMOS transistor P66and the NMOS transistor N64. Herein the common node of the NMOS transistor N67and the current source I2outputs the voltage-decreasing signal DN, while the common node of the PMOS transistor P67and the current source I3outputs the voltage-increasing signal UP.

The common node of the PMOS transistor P66and the NMOS transistor N64outputs the sensing voltage VSE and the voltage level of the sensing voltage VSE is determined by the variations of the input voltage VINT and the output voltage VOUT. The voltage levels of the voltage-increasing signal UP and the voltage-decreasing signal DN are determined by the variation of the sensing voltage VSE.

In the embodiment, when the input voltage VINT is equal to the output voltage VOUT, the voltage-increasing signal UP is logic low, while the voltage-decreasing signal DN is logic high. When the input voltage VINT is greater than the output voltage VOUT, the sensing voltage VSE drops, which further makes both the voltage-increasing signal UP and the voltage-decreasing signal DN to been logic high. When the input voltage VINT is less than the output voltage VOUT, the sensing voltage VSE ascends, which makes both the voltage-increasing signal UP and the voltage-decreasing signal DN to been logic low. All these are the same as the embodiments ofFIGS. 4 and 5.

Anyone skilled in the art should be able to derive the circuit operation details of the above-described embodiments inFIGS. 4-6Afrom the given disclosure of the present invention without any difficulty, therefore the circuit operation details are omitted to describe for simplicity. Moreover, the schemes for generating the voltage-increasing signal UP and the voltage-decreasing signal DN are not limited by the above-described circuits ofFIGS. 4-6Aas well, wherein the crucial point is the comparison result between the input voltage VINT and the output voltage VOUT must be obtained.

FIG. 6Bis a schematic circuit drawing of a voltage detector according to another embodiment of the present invention. A voltage detector610detects the variation of the input voltage VINT mainly by using a differential amplified signal DAS in the operational amplifier210and outputs the voltage-increasing signal UP and the voltage-decreasing signal DN. In the embodiment, the operational amplifier210includes a differential amplifier212and an output-stage circuit214. The differential amplifier212outputs the differential amplified signal DAS to the output-stage circuit214according to the signals received at the positive input terminal and the negative input terminal thereof. In the prior art, the operational amplifier usually has a differential circuit architecture for receiving an differential input signal, amplifying the received signal, amplifying the signal again through an output-stage circuit in a second time and then generating an output signal. Anyone skilled in the art should be able to derive the internal architecture of the above-described operational amplifier from the given disclosure of the present invention without any difficulty, therefore the internal architecture is omitted to describe for simplicity.

As shown byFIG. 6B, the voltage detector610detects the variation of the input voltage VINT by using a differential amplified signal DAS generated inside the operational amplifier210. Since the overdriving voltage ODV would be firstly regulated with the variation of the input voltage VINT (referring to the descriptions ofFIGS. 3A and 3B), therefore, when the input voltage VINT varies, the overdriving voltage ODV would be regulated to the input voltage VINT. At the same time, the differential amplified signal DAS accordingly varies therewith and the manner of altering the voltage level thereof is similar to the above described sensing voltage VSE. In addition, the voltage detectors400and500also use a circuit structure similar to the differential amplifier as the input stage of the comparator for comparing the input voltage VINT with the output voltage VOUT, therefore, in the embodiment, the voltage detector610directly uses the differential amplified signal DAS generated inside the operational amplifier210to generate the corresponding voltage-increasing signal UP and voltage-decreasing signal DN, which further simplifies the circuit architecture of the voltage detector610and saves the circuit design cost.

The voltage detector610includes an NMOS transistor N68, a PMOS transistor P68and current sources I2and I3. The current source I2and the NMOS transistor N68are coupled between the operation voltage VDD and the ground terminal GND. The PMOS transistor P68and the current source I3are coupled between the operation voltage VDD and the ground terminal GND. Both the gates of the NMOS transistor N68and the PMOS transistor P68are coupled to the differential amplified signal DAS. Herein the common node of the PMOS transistor P68and the current source I3outputs the voltage-increasing signal UP, while the common node of the current source I2and the NMOS transistor N68outputs the voltage-decreasing signal DN.

Referring toFIG. 2, in the following, the control unit224is further described. The control unit224outputs a charging signal PH1, a first path signal PH2P, a second path signal PH2N and a restoration signal PH2for controlling the voltage-regulating circuit226to generate the overdriving voltage ODV according to the voltage-increasing signal UP and the voltage-decreasing signal DN output from the voltage detector222.

FIG. 7Ais a schematic circuit drawing of a control unit according to an embodiment of the present invention. A control unit700includes a clock-regulating circuit710, a first control circuit720, a second control circuit730and a restoration circuit740. The clock-regulating circuit710outputs the charging signal PH1and a reference signal PH20according to a clock signal CLK, while the first control circuit720outputs the first path signal PH2P according to the voltage-increasing signal UP and the reference signal PH20. The second control circuit730outputs the second path signal PH2N according to the voltage-decreasing signal DN and the reference signal PH20. The restoration circuit740outputs the restoration signal PH2according to the voltage-increasing signal UP, the voltage-decreasing signal DN and the reference signal PH20.

The clock-regulating circuit710includes a delay circuit712, an NOT-OR (NOR) gate714, an NOT-AND (NAND) gate716and an inverter718. The delay unit712receives a clock signal CLK and after delaying the received signal outputs a delayed clock signal DCLK. The delay unit712comprises a plurality of delay components, for example, inverters. In the embodiment, the delay unit712comprises four inverters.

The input terminal of the NOR gate714is respectively coupled to the output terminal of the delay unit712and the clock signal CLK and outputs the reference signal PH20according to the delayed clock signal DCLK and the clock signal CLK. The NAND gate716performs an NAND logic operation on the delayed clock signal DCLK and the clock signal CLK, and then outputs the charging signal PH1via the inverter718.

The first control circuit720includes an NAND gate722and an inverter724. After performing a NAND logic operation on the voltage-increasing signal UP and the reference signal PH20, the NAND gate722outputs the first path signal PH2P via the inverter724.

The second control circuit730includes an inverter732, an NAND gate734and an inverter736. The voltage-decreasing signal DN is coupled to the NAND gate734via the inverter732, the NAND gate734performs a NAND logic operation on the inverted voltage-decreasing signal DN and the reference signal PH20and then outputs the second path signal PH2N via the inverter736.

The restoration circuit740includes an inverter742, an NAND gate744and an inverter746. Herein the NAND gate has three input terminals. The voltage-increasing signal UP is coupled to the NAND gate744via the inverter742, the NAND gate744performs a NAND logic operation on the inverted voltage-increasing signal UP, the voltage-decreasing signal DN and the reference signal PH20and then outputs the restoration signal PH2via the inverter746.

Herein the charging signal PH1, the first path signal PH2P and the second path signal PH2N are not overlapped by each other during the enabling duration; and during every period, only one of the first path signal PH2P and the second path signal PH2N is enabled.

The waveforms of the associated signals in an embodiment of the present invention in connection withFIG. 2are explained hereinafter.FIG. 7Bis a diagram of the signals according to the embodiment ofFIG. 7A. In the embodiment ofFIG. 7B, in terms of the signal relationship, the logic high indicates, for example, an enabling duration. However, in another embodiment of the present invention, the logic low can also indicate an enabling duration, wherein an appropriate modification ofFIG. 7Ais made, for example, by adding an inverter at the output terminal. Anyone skilled in the art should be able to derive the appropriate modification from the given disclosure of the present invention without any difficulty, therefore they are omitted to describe for simplicity.

As shown inFIG. 7B, after the clock signal CLK is enabled and thereafter with a delay of time (caused by the delay unit712), the charging signal PH1starts to be enabled and the enabling duration of the charging signal PH1is called as a charging duration T1. The enabling durations of the reference signal PH20and the charging signal PH1are not overlapped by each other (which can be derived from the clock-regulating circuit710).

During the charging duration T1, the switches S1and S2are on and the charging voltage dV starts to charge the capacitor C. Then, during an overdriving duration T2, one of the first path signal PH2P and the second path signal PH2N would be decided to be enabled according to the comparison result between the input voltage VINT and the output voltage VOUT. If the input voltage VINT is greater than the output voltage VOUT, the first path signal PH2P is enabled during the duration T2, wherein the switches S3and S4are on and the overdriving voltage ODV is greater than the input voltage VINT (that is, the overdriving voltage ODV is equal to the sum of the input voltage VINT and the voltage difference at the two terminals of the capacitor C); if the input voltage VINT is less than the output voltage VOUT, the second path signal PH2N is enabled during the duration T2, wherein the switches S5and S6are on and the overdriving voltage ODV is less than the input voltage VINT (that is, the overdriving voltage ODV is equal to the input voltage VINT less the voltage difference at the two terminals of the capacitor C).

After the overdriving duration, the restoration signal PH2is enabled. The enabling duration of the restoration signal PH2is called as the restoration duration T3. During the restoration duration T3, the switch S7is on and the overdriving voltage ODV is equal to the input voltage VINT. During the enabling duration of the restoration signal PH2, the switch S1and the switch S2can be on or kept off depending on the design requirement, while the voltage buffer continues to be operated normally.

On the other hand, if the input voltage VINT is equal to the output voltage VOUT, both the first path signal PH2P and the second path signal PH2N are disabled (which means both the first path signal PH2P and the second path signal PH2N are logic low in the embodiment).

In summary, since the voltage buffer of the present invention uses the overdriving scheme to convert the input voltage into an enlarged overdriving voltage, thus, the driving capability is enhanced and the slew rate of the voltage buffer is furthermore increased.

The above-described voltage buffer can be applied in a source driver of an LCD because the voltage buffer possesses the stronger driving capability and the higher slew rate. Hence, the source driver is suitable for driving a LCD panel with a larger dimension or a larger capacitance load to further improve the display quality thereof.

FIG. 8Ais a schematic circuit drawing of a control unit according to another embodiment of the present invention. A control unit800outputs a first path signal PH2P, a second path signal PH2N and a restoration signal PH2according to the voltage-increasing signal UP and the voltage-decreasing signal DN output from the voltage detector222. Referring toFIGS. 3A and 3B, the control unit800in association with the voltage-regulating circuit226of the embodiment inFIG. 3Aor the voltage-regulating circuit300of the embodiment inFIG. 3Bregulates the level of the overdriving voltage ODV. The control unit800includes inverters810and820and an AND gate830. As shown byFIG. 8A, the inverter810receives the voltage-increasing signal UP, inverts the received signal and outputs an inverted voltage-increasing signal UPB to the AND gate830. The AND gate830outputs a restoration signal PH2according to the inverted voltage-increasing signal UPB and the voltage-decreasing signal DN. The inverter820receives the voltage-decreasing signal DN, inverts the received signal and outputs the inverted signal as the second path signal PH2N, while the voltage-increasing signal UP herein can be directly served as the first path signal PH2P. In the embodiment, the logic high (logic ‘1’) indicates the enabling state and the relationships between the above-mentioned signals are listed in table 1 (in the table, ‘1’ and ‘0’ respectively indicate the logic high state and the logic low state, and all the signal marks are the same as the above described):

Please refer toFIGS. 3A and 3Bfor the following description. As indicated by Table 1, in the state of VINT=VOUT (inFIG. 3A), the restoration signal PH2is enabled, the switches S1, S2and S7are on (herein the restoration signal PH2, instead of the charging signal PH1, is used to control the switches S1and S2), the charging voltage dV charges the capacitor C, a positive voltage difference is generated between the first terminal CP1and the second terminal CP2of the capacitor C, and the overdriving voltage ODV is equal to the input voltage VINT at the point. In the state of VINT>VOUT, the first path signal PH2P is enabled and the switches S3and S4are on, so as to make the overdriving voltage ODV greater than the input voltage VINT. In the state of VINT<VOUT, the second path signal PH2N is enabled and the switches S5and S6are on so as to make the overdriving voltage ODV less than the input voltage VINT. It can be seen from the above that for each of the above-mentioned states, only one signal among the first path signal PH2P, the second path signal PH2N and the restoration signal PH2can take the enabling state at a time.

FIG. 8Bis a diagram of the signals according to the embodiment ofFIG. 8A. As shown inFIG. 8B, during the overdriving duration T81, when VINT≠VOUT, one of the first path signal PH2P and the second path signal PH2N is logic high which indicates the enabling state. Referring toFIG. 8B, if VINT>VOUT, the first path signal PH2P is enabled; if VINT<VOUT, the second path signal PH2N is enabled. During the restoration duration T82, VINT=VOUT and the restoration signal PH2is the logic high which indicates the enabling state. In addition, inFIG. 3B, if VINT=VOUT, the restoration signal PH2is enabled and the switch S10is on, which makes the overdriving voltage ODV equal to the input voltage VINT; if VINT>VOUT, the first path signal PH2P is enabled and the switch S8is on, which makes the overdriving voltage ODV greater than the input voltage VINT; if VINT>VOUT, the second path signal PH2N is enabled and the switch S9is on, which makes the overdriving voltage ODV less than the input voltage VINT.

FIG. 9is a block diagram of a source driver according to another embodiment of the present invention. A source driver900includes a buffer unit910and a driving unit920. The driving unit920generates a plurality of first driving signals FV1-FVNaccording to the display signals. The buffer unit910is coupled to the driving unit920and includes a plurality of voltage buffers BUF1-BUFN. The voltage buffers BUF1-BUFNare corresponding to the first driving signals FV1-FVNin one-to-one manner and respectively output corresponding second driving signals SV1-SVNfor driving an LCD panel according to the first driving signals.

In the embodiment, each of the voltage buffers BUF1-BUFNhas a same architecture as shown byFIG. 2. Therefore, the above-mentioned first driving signals FV1-FVNare respectively corresponding to the input voltage VINT of the voltage buffer200inFIG. 2, and the above-mentioned second driving signals SV1-SVNare respectively corresponding to the output voltage VOUT of the voltage buffer200. The operation details of the voltage buffers BUF1-BUFNcan refer to the depictions of the embodiments inFIGS. 2-8Band are omitted to describe for simplicity.

The driving unit920includes a shift register925, a first latch935, a second latch945, a level shifter955and a digital-to-analog converter (DAC)965. In the embodiment, all of the shift register925, the first latch935and the second latch945are together termed as a shift latch unit mainly for latching display signals (for example, an RGB display signal) and for latching and outputting the display signals according to a clock signal CK, a first control signal CT1and a second control signal CT2. Herein the shift register925outputs a shift signal according to the clock signal CK and the first control signal CT1. The first latch935of the latch unit is coupled to the shift register925and sequentially latches the display signals according to a shift signal. The second latch945of the shift latch unit is coupled to the first latch935and latches and outputs the latch result of the first latch935according to the second control signal CT2.

After the voltage levels of the outputs from the above-mentioned second latch945are regulated by the level shifter955, the DAC965would further convert the regulated signal into analog signals (for example, voltage signals), that is the first driving signals FV1-FVN. The first driving signals FV1-FVNpass the corresponding voltage buffers BUF1-BUFNand then the second driving signals SV1-SVNare output.

Taking the voltage buffer BUF1as an example, herein the received input voltage is the first driving signal FV1and the output voltage is the second driving signal SV1. When the first driving signal FV1is changed, the voltage detector inside the voltage buffer BUF1would compare the first driving signal FV1with the corresponding second driving signal SV1. If the first driving signal FV1is greater than the second driving signal SV1, the voltage buffer BUF1would generate an overdriving voltage greater than the first driving signal FV1. On the contrary, if the first driving signal FV1is less than the second driving signal SV1, the voltage buffer BUF1would generate an overdriving voltage less than the first driving signal FV1.

By using the overdriving voltage, the voltage buffer BUF1will have a more powerful driving capability, which further advances the slew rate of the voltage buffer BUF1. In other words, the speed to alter the second driving signal SV1is enhanced, which makes the second driving signal SV1equal to the first driving signal FV1more quickly. The operation details of the voltage buffers BUF1-BUFNcan refer to the depictions of the embodiments inFIGS. 2-8Band are omitted to describe for simplicity.

In the following, the timing signals to coordinate the source driver and the voltage buffer are described to further explain the technical means of the embodiment. Herein,FIGS. 3A,8A and8B are referred.FIG. 10is a diagram of the signals according to the embodiment ofFIG. 9. The first/second path signal PH2P/PH2N and the restoration signal PH2can refer to the depiction ofFIG. 8B. In the embodiment, the charging signal PH1ofFIG. 3Ais controlled by the timing of the restoration signal PH2.

The clock signal CK is the periodic impulse wave which is served as the reference for the operation of the shift register925. The period of the horizontal synchronization signal HSC can represent the period for the source driver900for driving a gate line. When the first control signal CT1is triggered, the shift latch unit starts to perform a shifting and latching operation on the display signals; when the second control signal CT2is triggered, the second latch945in the shift latch unit latches and outputs the latch result of the first latch935, which further generates a digital driving signal.

It can be seen from the above that the period of the second control signal CT2is corresponding to the period for altering the first driving signals FV1-FVN. That is to say, when the digital driving signal is changed, the first driving signals FV1-FVNvary therewith. Thus, during each period of the second control signal CT2, the voltage buffers BUF1-BUFNrespectively regulate the corresponding second driving signals SV1-SVNaccording to the first/second path signal PH2P/PH2N and the restoration signal PH2.

The above-mentioned signal waveforms inFIG. 10are corresponding to the situation where the voltage-regulating circuit in the voltage buffers BUF1-BUFNadopts the circuit architecture ofFIG. 3A. However, the circuit architecture ofFIG. 3Bis suitable for the voltage-regulating circuit in the voltage buffers BUF1-BUFNas well. Anyone skilled in the art should be able to derive the coordinating manner thereof from the given disclosure of the present invention without any difficulty, therefore it is omitted to describe for simplicity.

Since the voltage buffers BUF1-BUFNpossess a better slew rate, thus, the source driver900is suitable for an LCD panel with a larger dimension or a larger capacitance load. When the load capacitance is increased with a larger panel dimension, or a same voltage buffer200needs to drive more than one data line load, or a same voltage buffer200needs to time after time drive different data line loads during a same time of the horizontal synchronization signal HSC (for example, for the source driving mode of low temperature poly silicon), the source driver900is still competent to enhance the driving capability thereof and to retain a better slew rate by using the overdriving scheme.