Method and apparatus of frequency synthesis

An apparatus having a digitally controlled timing adjustment circuit configured to receive a first clock and a second clock and output a third clock and a fourth clock in accordance with a noise cancellation signal and a gain control signal, an analog phase detector configured to receive the third clock and the fourth clock and output an analog timing error signal, a filtering circuit configure to receive the analog timing error signal and output an oscillator control signal, a controllable oscillator configured to receive the oscillator control signal and output a fifth clock, a clock divider configured to receive the fifth clock and output the second clock in accordance with a division factor, a modulator configured to receive a clock multiplication factor and output the division factor and the noise cancellation signal, wherein a mean value of the division factor is equal to the clock multiplication factor, a digital phase detector configured to receive the third clock and the fourth clock and output a digital timing error signal, wherein the digital phase detector is self-calibrated so that a mean value of the digital timing error signal is zero, and a correlation circuit configured to receive the timing error signal and the noise cancellation signal and output the gain control signal.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention generally relates to phase lock loops.

Description of Related Art

Persons of ordinary skills in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “voltage,” “current,” “signal,” “logical signal,” “clock,” “rising edge,” “phase,” “capacitor,” “charge,” “charge pump,” “transistor,” “MOS (metal-oxide semiconductor),” “PMOS (p-channel metal oxide semiconductor),” “NMOS (n-channel metal oxide semiconductor),” “source,” “gate,” “drain,” “circuit node,” “ground node,” “switch,” “inverter,” “time-to-digital converter,” “digital-to-analog converter,” and “digital-to-time converter.” Terms and basic concepts like these are apparent to those of ordinary skills in the art and thus will not be explained in detail here.

Through this disclosure, a logical signal is a signal of two states: “high” and “low,” which can also be re-phrased as “1” and “0.” For brevity, a logical signal in the “high” (“low”) state is simply stated as the logical signal is “high” (“low”), or alternatively, the logical signal is “1” (“0”). Also, for brevity, quotation marks may be omitted and the immediately above is simply stated as the logical signal is high (low), or alternatively, the logical signal is 1 (0), with the understanding that the statement is made in the context of describing a state of the logical signal.

A logical signal is said to be asserted when it is high. A logical signal is said to be de-asserted when it is low.

A clock signal is a cyclic logical signal. For brevity, hereafter, “clock signal” may be simply referred to as “clock.”

A timing of a clock signal refers to a time instant where the clock signal undergoes a transition of state, either a low-to-high transition or a high-to-low transition. When a clock signal undergoes a low-to-high (high-to-low) transition, a rising (falling) edge is observed in a timing diagram.

As is known, a phase lock loop (PLL) receives a first clock and outputs a second clock such that a phase of the second clock tracks a phase of the first clock. As a result, a frequency of the second clock is determined by a frequency of the first clock. A prior art phase lock loop comprises a phase/frequency detector (hereafter PFD), a charge pump (hereafter CP) circuit, a loop filter (hereafter LF), a voltage-controlled oscillator (hereafter VCO), and a clock divider circuit, wherein: the VCO outputs the second clock in accordance with a control voltage such that the frequency of the second clock is determined by the control voltage, the clock divider circuit receives the second clock and outputs a third clock in accordance with a division ratio, the PFD receives the first clock and the third clock and outputs a timing signal representing a difference in timing between the first clock and the third clock, the CP circuit converts the timing signal into a current signal, the LF filters the current signal to establish the control voltage to control the frequency of the second clock. The frequency of the second clock is thus adjusted in a closed loop manner to track a frequency of the first clock. “Phase/frequency detector,” “charge pump circuit,” “loop filter,” “voltage-controlled oscillator,” and “clock divider circuit” are all well known in the prior art and thus not described in detail here. In a steady state, the frequency of the second clock is equal to the frequency of the first clock multiplied by a multiplication factor N that can be expressed as
N=Nint+α

where Nintis a positive integer and α is a rational number smaller than 1 (one) but not smaller than 0 (zero). If α is zero, the clock divider circuit has a fixed division factor Nint, i.e. it performs a “divide by Nint” function wherein one cycle of the third clock is output for every Nintcycles of the second clock. If α is nonzero, it must be a fractional number; in this case, the phase lock loop is referred to as “fractional-N PLL,” and the clock divider circuit cannot have a fixed division factor. In an embodiment, the division factor of the clock divider circuit is modulated by a delta-sigma modulator and dynamically toggle between Nintand Nint+1 such that a mean value of the division factor is equal to Nint+α. Since the value of the division factor is modulated, an instantaneous value differs from a mean value of the division factor (e.g., Nintand Nint+1 are different from Nint+α), resulting in an instantaneous noise additive to the PLL. In U.S. Pat. No. 7,999,622, Galton et al disclosed a method to cancel the additive noise resulting from the modulation of the division factor. The method is based on using a digital-to-analog converter to output a current that offsets an additive noise in the output of the charge pump circuit (resulting from the modulation of the division factor). The digital-to-analog converter (DAC), however, contributes thermal noise. To reduce the thermal noise contribution, a large current can be used at the cost of high power consumption. Besides, in practice the DAC is not perfectly linear, and its nonlinearity can contribute additional noise to PLL. To reduce the adverse effect of the nonlinearity of the DAC, a dynamic element matching can be used at the cost of high circuit complexity.

BRIEF SUMMARY OF THIS INVENTION

What is desired and disclosed herein is a method for cancelling a noise in a fractional-N PLL resulting from a modulation of a division factor without consuming high power or demanding high circuit complexity.

An aspect of the present invention is to use a digitally controlled timing adjustment circuit to correct a pre-known timing error in a fractional-N phase lock loop due to a modulation of a division factor of a clock divider, wherein a gain of the digitally controlled timing adjustment circuit is calibrated in a closed-loop manner based upon a correlation between the pre-known timing error and a residual timing error of an output of the digitally controlled timing adjustment circuit.

In an embodiment, an apparatus comprises: a digitally controlled timing adjustment circuit configured to receive a first clock and a second clock and output a third clock and a fourth clock in accordance with a noise cancellation signal and a gain control signal; an analog phase detector configured to receive the third clock and the fourth clock and output an analog timing error signal; a filtering circuit configure to receive the analog timing error signal and output an oscillator control signal; a controllable oscillator configured to receive the oscillator control signal and output a fifth clock; a clock divider configured to receive the fifth clock and output the second clock in accordance with a division factor; a modulator configured to receive a clock multiplication factor and output the division factor and the noise cancellation signal; a digital phase detector configured to receive the third clock and the fourth clock and output a digital timing error signal, wherein the digital phase detector is self-calibrated so that a mean value of the digital timing error signal is zero; and a correlation circuit configured to receive the digital timing error signal and the noise cancellation signal and output the gain control signal. In an embodiment, a timing difference between the fourth clock and the third clock is equal to a sum of: a timing difference between the second clock and the first clock, the noise cancellation signal scaled by the gain control signal, and a timing offset. In an embodiment, the digitally controlled timing adjustment circuit comprises: a fixed-delay circuit configured to receive the second clock and output the fourth clock, and a digitally controlled variable-delay circuit configured to receive the first clock and output the third clock in accordance with the noise cancellation signal and the gain control signal. In an embodiment, a delay of the digitally controlled variable delay circuit is linearly dependent on the noise cancellation signal and also linearly dependent on the gain control signal. In an embodiment, the digitally controlled variable delay circuit comprises: a tunable inverter comprising an inverter supplied by a rail voltage controlled by the gain control signal, and a variable capacitor controlled by the noise cancellation signal.

In an embodiment, the digital phase detector comprises: a skew adjustment circuit configured to receive the third clock and the fourth clock and output a first delayed clock and a second delayed clock in accordance with a delay control signal, a time-to-digital converter configured to receive the first delayed clock and the second delay clock and output the digital timing error signal, and an integrator configured to receive the digital timing error signal and output the delay control signal. In an embodiment, the correlation circuit comprises a digital signal processing unit configured to decrement the gain control signal by a value determined by the digital timing error signal if the noise cancellation signal is positive, increment the gain control signal by the value determined by the digital timing error signal if the noise cancellation signal is negative, or make no changes to the gain control signal if the noise cancellation signal is zero. In an embodiment, the modulator comprises a delta-sigma modulator. In an embodiment, the modulator comprises a first order delta-sigma modulator. In an embodiment, the analog phase detector comprises a phase/frequency detector. In an embodiment, the filtering circuit comprises a charge pump and a load circuit comprising a serial connection of a capacitor and a resistor. In an embodiment, the controllable oscillator is a voltage-controlled oscillator. In an embodiment, the clock divider is a counter.

In an embodiment, a method comprises: receiving a first clock and a clock multiplication factor; modulating the clock multiplication factor into a division factor, wherein a mean value of the division factor is equal to the clock multiplication factor; establishing a noise cancellation signal in accordance with a difference between the clock multiplication factor and the division factor; deriving a third clock and a fourth clock from the first clock and a second clock using a digitally controlled timing adjustment circuit in accordance with a noise cancellation signal and a gain control signal; establishing an analog timing error signal by detecting a timing difference between the fourth clock and the third clock using an analog phase detector; filtering the analog timing error signal into an oscillator control signal using a filtering circuit; outputting a fifth clock in accordance with the oscillator control signal using a controllable oscillator; outputting the second clock by dividing down the fifth clock in accordance with the division factor; establishing a digital timing error signal by detecting the timing difference between the fourth clock and the third clock using a digital phase detector that is self-calibrating so that a mean value of the digital timing error signal is zero; and adjusting the gain control signal in accordance with a correlation between the digital timing error signal and the noise cancellation signal. In an embodiment, a timing difference between the fourth clock and the third clock is equal to a sum of: a timing difference between the second clock and the first clock, the noise cancellation signal scaled by the gain control signal, and a timing offset. In an embodiment, the digitally controlled timing adjustment circuit comprises: a fixed-delay circuit configured to receive the second clock and output the fourth clock, and a digitally controlled variable-delay circuit configured to receive the first clock and output the third clock in accordance with the noise cancellation signal and the gain control signal. In an embodiment, a delay of the digitally controlled variable delay circuit is linearly dependent on the noise cancellation signal and also linearly dependent on the gain control signal. In an embodiment, the digitally controlled variable delay circuit comprises: a tunable inverter comprising an inverter supplied by a rail voltage controlled by the gain control signal, and a variable capacitor controlled by the noise cancellation signal. In an embodiment, the digital phase detector comprises: a skew adjustment circuit configured to receive the third clock and the fourth clock and output a first delayed clock and a second delayed clock in accordance with a delay control signal, a time-to-digital converter configured to receive the first delayed clock and the second delay clock and output the digital timing error signal, and an integrator configured to receive the digital timing error signal and output the delay control signal. In an embodiment, the correlation circuit comprises a digital signal processing unit configured to decrement the gain control signal by a value determined by the digital timing error signal if the noise cancellation signal is positive, increment the gain control signal by the value determined by the digital timing error signal if the noise cancellation signal is negative, or make no change to the gain control signal if the noise cancellation signal is zero. In an embodiment, modulating the clock multiplication factor comprises using a delta-sigma modulator. In an embodiment, modulating the clock multiplication factor comprises using a first order delta-sigma modulator. In an embodiment, the analog phase detector comprises a phase/frequency detector. In an embodiment, the filtering circuit comprises a charge pump and a load circuit comprising a serial connection of a capacitor and a resistor. In an embodiment, the controllable oscillator is a voltage-controlled oscillator. In an embodiment, the dividing down the fifth clock comprises using a counter.

DETAILED DESCRIPTION OF THIS INVENTION

The present invention relates to phase lock loops. While the specification describes several example embodiments of the invention considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention.

FIG. 1Ashows a functional block diagram of a PLL100in accordance with an embodiment of the present invention. PLL100comprises: a digitally controlled timing adjustment circuit160configured to receive a first clock CK1and a second clock CK2and output a third clock CK3and a fourth clock CK4in accordance with a noise cancellation signal NCand a gain control signal GC; a phase/frequency detector (PFD)110configured to receive the third clock CK3and the fourth clock CK4and output an analog timing error signal STErepresenting a timing difference between the third clock CK3and the fourth clock CK4; a charge pump (CP)120configured to convert the analog timing error signal STEinto a correction current IC; a loop filter (LF)130configured to receive the correction current ICand output a control voltage VCTL; a voltage-controlled oscillator (VCO)140configured to output a fifth clock CK5in accordance with the control voltage VCTL; a clock divider150configured to receive the fifth clock CK5and output the second clock CK2in accordance with a division factor NDIV; a modulator (MOD)170configured to output the division factor NDIVand the noise cancellation signal NCin accordance with a clock multiplication factor NMUL; a self-calibrating TDC (time-to-digital converter)190configured to receive the third clock CK3and the fourth clock CK4and output a digital timing error signal DTE, and a correlation circuit180configured to output the gain control signal GCin accordance with a correlation between the digital timing error signal DTEand the noise cancellation signal NC. For brevity, hereafter the first (second, third, fourth, fifth) clock CK1(CK2, CK3, CK4, CK5) is simply referred to as CK1(CK2, CK3, CK4, CK5), the analog timing error signal STEis simply referred to as STE, the digital timing error signal DTEis simply referred to as DTE, the correction current ICis simply referred to as IC, the control voltage VCTLis simply referred to as VCTL, the noise cancellation signal NCis simply referred to as NC, the gain control signal GCis simply referred to as GC, the clock multiplication factor NMULis simply referred to as NMUL, and the division factor NDIVis simply referred to as NDIV.

PLL100will be the same as the aforementioned prior art PLL if: the digitally controlled timing adjustment circuit160, the self-calibration TDC190, and the correlation circuit180are removed, and PFD110receives CK1and CK2, instead of CK3and CK4. Similar to the prior art PLL, PLL100receives CK1and outputs CK5using VCO140, which is adjusted in a closed loop manner via a feedback path comprising the clock divider150, PFD110, CP120, and LF130, such that a frequency of CK5is equal to a frequency of CK1times NMUL, which is not a pure integer. Since NMULis not a pure integer but NDIV(which is the clock division factor of the clock divider150) needs to be an integer, NDIVmust be modulated in a way such that a mean value of NDIVequals NMUL. Modulator170receives NMULand outputs NDIV, effectively modulating NDIVsuch that the mean value of NDIVequals NMUL. In doing so, the average frequency of CK5is equal to the frequency of CK1times NMUL, but an instantaneous timing of CK2might deviate from an ideal timing of a fictitious clock divider that allows a non-integer division factor of NMUL. The deviation of the instantaneous timing of CK2from the ideal timing due to the modulation of NDIVleads to an instantaneous noise in the timing difference between CK2and CK1. However, the instantaneous noise of the timing difference between CK2and CK1due to the modulation of NDIVis pre-known. The instantaneous noise is calculated by the modulator170and represented by NC. The digitally controlled timing adjustment circuit160is configured to correct the instantaneous noise in the timing difference between CK2and CK1due to the modulation of NDIV, such the timing difference between CK4and CK3is free of the instantaneous noise. However, NCis numeric and digital in nature, while the timing difference between CK2and CK1is temporal and analog in nature. A function of digital-to-analog conversion is performed by the digitally controlled timing adjustment circuit160to convert NCinto the amount of timing difference that needs to be cancelled. GCdetermines a gain factor of the digital-to-analog conversion.

The self-calibrating TDC190detects a timing difference between CK3and CK4and output DTEto represent the timing difference. The self-calibrating TDC190calibrates itself so that a mean value of DTEis zero.

Note that PFD (such as PFD110ofFIG. 1A) is an example of analog phase detector, while TDC (such as the self-calibrating TDC190ofFIG. 1A) is an example of digital phase detector.

In an embodiment, a function of the digitally controlled timing adjustment circuit160can be described by the following mathematical expression:
t4−t3=t2−t1+NC·GC+tOS(1)

Here, t1is a timing of a rising edge of CK1, t2is a timing of a rising edge of CK2, t3is a timing of a rising edge of CK3, t4is a timing of a rising edge of CK4, and tOSis a timing offset. Here, t2−t1is a timing difference between CK2and CK1, while t4−t3is a timing difference between CK4and CK3. Both STEand DTErepresent a relative timing between CK4and CK3and is mathematically equal to t4−t3. A major difference between STEand DTEis that STEis analog but DTEis digital. NCpresents the instantaneous noise in t2−t1due to the modulation of NDIV. If GC, which is the conversion gain for converting NCinto the timing difference to be cancelled, is set properly, the noise in t2−t1due to the modulation of NDIVwill be corrected and absent in t4−t3. On the other hand, if GCis not set properly, the noise will be either over-corrected or under-corrected, resulting in a residual noise in t4−t3that will become a part of DTE. When GCis set too large (small), the noise will be over-corrected (under-corrected); as a result, t4−t3will contain a residual noise that is positively (negatively) correlated with NC, and therefore DTEwill tend to be positive (negative) when NCis positive and negative (positive) when NCis negative. Correlation circuit180thus adjusts GCin accordance with a correlation between NCand DTE: when DTEis positively (negatively) correlated with NC, it indicates GCis too large (small) and needs to be decreased (increased).

In an embodiment depicted inFIG. 1B, PFD110comprises two data flip-flops (DFF)111and112and an AND gate113. Each DFF comprises an input terminal labeled “D,” an output terminal labeled “Q,” a reset terminal labeled “R,” and a clock terminal denoted by a wedge symbol; such notations are widely used in the prior art. DFF111outputs a first logical signal UP while DFF112outputs a second logical signal DN. The NAND gate113receives the two logical signals UP and DN and outputs a reset signal RST. The first (second) logical signal UP (DN) is asserted upon a rising edge of CK3(CK4) and is de-asserted when the reset signal RST is asserted. The two logical signals UP and DN jointly embody the timing error signal STErepresenting a timing difference between CK3and CK4; such embodiment is widely used and well known in the prior art and thus not explained in detail here.

In an embodiment depicted inFIG. 1C, CP120comprises a current source121configured to source a charge-up current IUP, a current sink122configured to sink a charge-down current IDN, a first switch123configured to couple the charge-up current IUPto an output node125when the logical signal UP is asserted, and a second switch124configured to couple the charge-down current IDNto the output node125when the logical signal DN is asserted. The output node125interfaces with and provides the correction current ICto LF130ofFIG. 1A. Throughout this disclosure, “VDD” denotes a power supply node.FIG. 1Cis well known in the prior art and self-explanatory to those of ordinary skills in the art and thus not described in detail here.

In an embodiment depicted inFIG. 1D, LF130comprises a resistor131, a first capacitor132, and a second capacitor133, configured to receive the correction current ICfrom CP120ofFIG. 1Aand output the control voltage VCTLto VCO140ofFIG. 1A.FIG. 1Dis well known in the prior art and self-explanatory to those of ordinary skills in the art and thus not described in detail here.

In an embodiment depicted inFIG. 1E, VCO140comprises a voltage-to-current converter141configured to convert the control voltage VCTLinto a control current ICTL, a current mirror143configured to mirror the control current ICTLinto a mirrored current IM, and a ring oscillator146configured to output CK5in accordance with the mirrored current IM. The voltage-to-current converter142comprises a NMOS transistor142. The current mirror143comprises two PMOS transistors144and145. The ring oscillator comprises three inverters147,148, and149configured in a ring topology, jointly receiving the mirror current IM. When the control voltage VCTLrises, the control current ICTLrises, and so does the mirrored current IM. As a result, the three inverters147,148, and149receive more power and become faster, resulting in a higher oscillation frequency for CK5.

Clock divider150can be embodied by a counter that increments a count upon a rising edge of CK5. The count starts with 0, increments to 1 upon a rising edge of CK5, then increments to 2 upon a next rising edge of CK5, and so on. When the count reaches NDIV−1, it wraps around to 0 upon a next rising edge of CK5. In this manner, the counter cyclically counts from 0 to NDIV−1. CK2is asserted whenever the count equals 0, and de-asserted otherwise.

Digitally controlled timing adjustment circuit160receives CK1and CK2and outputs CK3and CK4, so that a timing difference between CK4and CK3is related to a timing difference between CK2and CK1in accordance with a relation described by equation (1). In an embodiment depicted inFIG. 1F, digitally controlled timing adjustment circuit160comprises: a fixed-delay circuit160_1configured to receive CK2and output CK4, and a digitally controlled variable-delay circuit160_2configured to receive CK1and output CK3in accordance with GCand NC. The fixed-delay circuit160_1provides a fixed timing difference between CK4and CK2; that is, t4−t2is fixed. On the other hand, the digitally controlled variable-delay circuit160_2provides a variable timing difference between CK3and CK1and the variable timing difference is controlled by GCand NC; that is, t3−t1is variable and controlled by GCand NC. As a result, t4−t3is different from t2−t1by a variable amount controlled by GCand NC. In particular, the variable timing difference is linearly dependent on NC, and also linearly dependent on GC. In an embodiment, the fixed-delay circuit160_1is simply a short circuit; in this case, the fixed delay is zero and CK3is the same as CK1. In an alternative embodiment, the fixed-delay circuit is an inverter chain that includes an even number of inverters configured in a cascade topology.

By way of example but not limitation, NCis a four-bit word comprising four bits NC[0], NC[1], NC[2], and NC[3]. In an embodiment depicted inFIG. 1G, the digitally controlled variable-delay circuit160_2comprises: a tunable inverter161configured to receive CK1and output an intermediate clock CKI at a circuit node165in accordance with GC; an output inverter162configured to receive the intermediate clock CKI and output CK3; and a variable capacitor166configured to provide a capacitive load at the circuit node165. The tunable inverter161comprises: a DAC (digital-to-analog converter)169configured to receive GCand output a rail voltage VR; an inverter168comprising a PMOS transistor MP and a NMOS transistor MN configured to receive CK1and output CKI in accordance with the rail voltage VR. The variable capacitor166comprises four capacitors163_0,163_1,163_2, and163_3configured to conditionally shunt the circuit node165to ground via four switches164_0,164_1,164_2, and164_3in accordance with NC[0], NC[1], NC[2], and NC[3], respectively. The output inverter162serves as an inverting buffer, and together with the tunable inverter161causes CK3to be the same as CK1except for a delay. In an embodiment, a capacitance of the variable capacitor166increases linearly with a value of NC. When CK1is low, CKI is high and equal to the rail voltage VR, and CK3is low. Note that the rail voltage VR is linearly dependent on GC, thanks to the digital-to-analog conversion function of the DAC169. A low-to-high transition of CK1will cause the tunable inverter167to discharge the variable capacitor166via the NMOS transistor MN, resulting in a high-to-low transition of CKI, and consequently a low-to-high transition of CK3. The time that CKI takes to finish the high-to-low transition in response to the low-to-high transition of CK1is linearly dependent on a total capacitance at the circuit node175, and also linearly dependent on the rail voltage VR. The capacitance of the variable capacitor is linearly dependent on the value of NCand the rail voltage VR is also linearly dependent on GC, the time that the intermediate clock CKI takes to finish the transition is approximately linearly dependent on NCand also linearly dependent on GC. Therefore, digitally controlled timing adjustment circuit160can effectively embody equation (1).

The correlation circuit180outputs GCbased on a correlation between DTEand NC. In an embodiment, GCis established in accordance with an algorithm of adaptation described by the following equation

Here, μ is an adaptation constant, GC(old)is a value before adaptation, and GC(new)is a value after adaptation. Since DTEand NCare purely digital, and equation (2) can be implemented by using a digital signal processing engine. In an embodiment, GCis a digital signal, and the correlation circuit180comprises a digital signal processing unit that adapts GCin accordance with DTEand NCusing equation (2).

A functional block diagram of a self-calibrating TDC200suitable for embodying the self-calibrating TDC190ofFIG. 1Ais depicted inFIG. 2. Self-calibrating TDC200comprises: a skew adjustment circuit210configured to receive CK3and CK4and output a first delayed clock CK3D and a second delayed clock CK4D in accordance with a delay control signal DCTL; a TDC (time-to-digital converter)220configured to receive the first delay clock CK3D and the second delayed clock CK4D and output DTE; and an integrator230configured to receive DTEand output the delay control signal DCTL. For brevity, hereafter the first delayed clock CK3D is simply referred to as CK3D, the second delayed clock CK4D is simply referred to as CK4D, and the digital control signal DCTLis simply referred to as DCTL. The skew adjustment circuit210comprises: a variable delay circuit211configured to receive CK3and output CK3D in accordance with DCTL, and a fixed delay circuit212configured to receive CK4and output CK4D. TDC220comprises a data flip-flop (DFF)221configured to output DTEby sampling CK3D in accordance with CK4D. In this particular embodiment, TDC220is a single-bit TDC, wherein DTEis a logical signal that is high (low) when a rising edge of CK3D arrives earlier (later) than a rising edge of CK4D. In the context of digital signal processing, however, DTEis interpreted as a binary signal that is either “1” or “−1,” indicating a relative timing (early or late) of CK3D with respect to CK4D. DCTLis an integral of DTE. In an embodiment, the fixed delay circuit212comprises a cascade of an even number of inverters. In an embodiment, the variable delay circuit211is a digital-to-time converter, wherein CK3D is derived from CK3by delaying CK3with a delay that is linearly dependent on a value of DCTL. Digital-to-time converters are well known in the prior art and thus not described in detailed here. Of the two possible values of DTE, if “1” (“−1”) occurs more often than “−1” (“1”), the value of DCTLwill increase (decrease), and consequently the delay of CK3D will increase (decrease); as a result, the likelihood of CK3D being earlier than CK4D in timing is decreased (increased), so is the likelihood of DTEbeing “1” (“−1”). DCTLis thus adjusted in a closed loop manner. In a steady state, a mean value of DTEis zero and therefore there is no substantial change to DCTL.

In an embodiment, MOD170ofFIG. 1Ais embodied by a modulator300depicted inFIG. 3. Modulator300comprises a rounding operator (denoted by round(•))302, two unit delays (denoted by z−1)304and306, and three summing operators301,303, and305. Unit delay304receives a rounding error e1and outputs a delayed rounding error e1d. Summing operator301sums NMULand e1dinto a modified multiplication factor N′MUL. Rounding operator302rounds N′MULinto NDIV. Summing operator303subtracts NDIVfrom N′MULto generate e1. Summing operator305sums NCwith NDIVand deducts NMULto output an intermediate signal GCNEXT. Unit delay306receives NCNEXTand outputs NC. Rounding operator302, summing operator301and303, and unit delay304form a 1st order delta-sigma modulator, so that a mean value of NDIVequals NMUL. Summing operator305and unit delay306form an error accumulator, so that NCis equal to an accumulative sum of a difference between NDIVand NMUL. The difference between NDIVand NMULis an instantaneous error of the 1st order delta-sigma modulator, and thus an error of the clock dividing operation of the clock divider150. NCis the accumulative sum of a difference between NDIVand NMUL, represents an accumulative error of the clock dividing operation of the clock divider150and thus a timing error of CK2. Digitally controlled timing adjustment circuit160corrects the timing error by adjusting the timing difference between CK2and CK1with an amount determined by NC.

Now refer toFIG. 1F. In an alternative embodiment not shown in the figure, the fixed-delay circuit160_1and the digitally controlled variable-delay circuit160_2are swapped, and the digitally controlled variable-delay circuit160_2is controlled by GCand −NCinstead, where −NCis an inversion of NC. In this alternative embodiment, the timing difference between CK3and CK1is fixed and the timing difference between CK4and CK2is variable and controlled by GCand −NC, but the function remains the same and equation (1) is fulfilled.

Still refer toFIG. 1F. The digitally controlled variable-delay circuit160_2belongs to a category of circuits known as digital-to-time converters, wherein a timing of an output clock is controlled by a digital signal. The digitally controlled variable-delay circuit160_2can be embodied by other digital-to-time converters, as long as the time difference between CK3and CK1is linearly dependent on both NCand GC.

Now refer toFIG. 1A. PFD110is merely an exemplary analog phase detector but not a limitation. An alternative phase detector can be used instead, as long as the timing difference between CK4and CK3can be detected and properly represented by an associated timing error signal (such as STE). Also, VCO140is merely an exemplary controllable oscillator circuit but not a limitation. An alternative controllable oscillator circuit can be used instead, as long as an output clock (such as CK5) can be generated and a frequency of the output clock can be controlled by a control signal (such as VCTL). Likewise, CP120and the subsequent LF130are an exemplary embodiment, but not a limitation, configured to filter an analog timing error signal (such as STE) generated by a preceding analog phase detector (such as PFD110) into a control signal (such as VCTL). An alternative embodiment can be used instead, as long as the analog timing error signal can be filtered into a controllable signal for controlling a subsequent controllable oscillator circuit (such as VCO140).

In accordance with an embodiment of the present invention, a flow chart400of a method comprises: receiving a first clock and a clock multiplication factor (step401); modulating the clock multiplication factor into a division factor, wherein a mean value of the division factor is equal to the clock multiplication factor (step402); establishing a noise cancellation signal in accordance with a difference between the clock multiplication factor and the division factor (step403); deriving a third clock and a fourth clock from the first clock and a second clock using a digitally controlled timing adjustment circuit in accordance with the noise cancellation signal and a gain control signal (step404); establishing an analog timing error signal by detecting a timing difference between the fourth clock and the third clock using an analog phase detector (step405); filtering the analog timing error signal into an oscillator control signal using a filtering circuit (step406); outputting a fifth clock in accordance with the oscillator control signal using a controllable oscillator (step407); outputting the second clock by dividing down the fifth clock in accordance with the division factor (step408); establishing a digital timing error signal by detecting the timing difference between the fourth clock and the third clock using a digital phase detector that is self-calibrating so that a mean value of the digital timing error signal is zero (step409); and adjusting the gain control signal in accordance with a correlation between the digital timing error signal and the noise cancellation signal (step410).