Semiconductor device having buried channel array

A semiconductor device includes a field regions in a substrate to define active regions, gate trenches including active trenches disposed across the active region and field trenches in the field regions, and word lines that fill the gate trenches and extend in a first direction. The word lines include active gate electrodes occupying the active trenches, and field gate electrodes occupying the field trenches. The bottom surface of each field gate electrode, which is disposed between active regions that are adjacent to each other and have one word line therebetween, is disposed at a higher level than the bottom surfaces of the active gate electrodes.

PRIORITY STATEMENT

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2012-0118562 filed on Oct. 24, 2012, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The inventive concept relates to a semiconductor device having a buried channel array, a method of manufacturing the device, and an electronic device and electronic system adopting the device.

2. Description of Related Art

One technique aimed at increasing the integration density of semiconductor devices is to form the word lines of the device in a substrate, i.e., to form buried word lines.

SUMMARY

According to one aspect of the inventive concept, there is provided a semiconductor device comprising a substrate and a field region disposed in the substrate and defining active regions of the substrate, and in which the substrate has active trenches therein extending in and across the active regions, and the field region has field trenches therein, and word lines respectively occupying gate trenches each constituted by respective ones of the active and field trenches together, and in which each of the word lines extends longitudinally in a first direction across a plurality of the active regions, the word lines include active gate electrodes disposed within the active trenches, and field gate electrodes disposed within the field trenches, and each of the field gate electrodes is disposed between respective ones of the active regions that are adjacent to each other with one word line therebetween, and has a bottommost surface disposed at a level than higher than bottommost surfaces of the active gate electrodes.

According to another aspect of the inventive concept, there is provided a semiconductor device comprising a substrate, and a field region disposed in the substrate and defining active regions of the substrate, and in which the substrate has active trenches therein extending in and across the active regions, and the field region has field trenches therein, word lines respectively occupying gate trenches each constituted by respective ones of the active and field trenches together; and in which each of the word lines extends longitudinally in a first direction across a plurality of the active regions, the word lines include active gate electrodes disposed within the active trenches, field gate electrodes disposed within the field trenches, and fin gate electrodes each interposed between a portion of the field region and an active region in the first direction, and each of the field gate electrodes has a bottommost surface disposed at a level higher than that of the bottommost surfaces of the fin gate electrodes.

According to still another aspect of the inventive concept, there is provided a semiconductor device comprising a substrate and a field region disposed in the substrate and defining active regions of the substrate, and in which the substrate has active trenches therein extending in and across the active regions, the field region has field trenches therein, gate trenches are each constituted by respective ones of the active and field trenches together that are contiguous in first direction, and the field trenches have a depth that is different from that of the active trenches, and word lines respectively occupying the gate trenches, respectively, including at the bottommost portion thereof such that each of the word lines has a first section occupying the bottommost portion of at least one of the active trenches and a second section occupying the bottommost portion of at least one of the field trenches, and each of the word lines extending longitudinally in the first direction across a plurality of the active regions, and in which opposite surfaces of the first section of one of the word lines face side surfaces of the second sections of neighboring ones of the word lines, respectively.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Various embodiments and examples of embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. In the drawings, the sizes and relative sizes and shapes of elements, layers and regions, such as implanted regions, shown in section may be exaggerated for clarity. In particular, the cross-sectional illustrations of the semiconductor devices and intermediate structures fabricated during the course of their manufacture are schematic. Also, like numerals are used to designate like elements throughout the drawings.

Furthermore, spatially relative terms, such as “upper,” and “lower” are used to describe an element's and/or feature's relationship to another element(s) and/or feature(s) as illustrated in the figures. Thus, the spatially relative terms may apply to orientations in use which differ from the orientation depicted in the figures. Obviously, though, all such spatially relative terms refer to the orientation shown in the drawings for ease of description and are not necessarily limiting as embodiments according to the inventive concept can assume orientations different than those illustrated in the drawings when in use. In addition, the terms “upper” or “bottom” as used to describe a surface generally refer not only to the orientation depicted in the drawings but to the fact that the surface is the uppermost or bottommost surface in the orientation depicted, as would be clear from the drawings and context of the written description.

Other terminology used herein for the purpose of describing particular examples or embodiments of the inventive concept is to be taken in context. For example, the terms “comprises” or “comprising” when used in this specification specifies the presence of stated features or processes but does not preclude the presence or additional features or processes.

An example of a first embodiment of semiconductor device according to the inventive concept will now be described with reference toFIGS. 1,3A, and3B.

In this example, the semiconductor device includes a substrate100having active regions101and field regions104, gate structures115in the substrate100, and bit line structures125and capacitor structures135on the substrate100.

The substrate100is a semiconductor substrate. For example, the substrate100is a silicon (Si) substrate, a germanium (Ge) substrate, or a silicon-germanium (SiGe) substrate. The substrate100may include a memory cell array region in which memory cells are formed, and a peripheral circuit region in which peripheral circuits configured to operate the memory cells are formed.

The field regions104define the active regions101. The field regions104may be shallow trench isolation (STI) regions. For example, each of the field regions104may be an insulating layer filling a trench102formed in the substrate100. The insulating layer may include silicon oxide.

Each of the active regions101may be elongated island-shaped regions, i.e., may have a major axis and a minor axis. The active regions101may also be arrayed 2-dimensionally in the directions of the major and minor axes.

The gate structures115include word lines114(WL1, WL2, WL3, WL4, and WL5), respectively. The word lines114each extend longitudinally in a first direction across a plurality of the active regions101. The bit line structures125include bit lines126(BL1, BL2, and BL3) each of which may extend longitudinally in a second direction orthogonal to the first direction.

The active regions101may be oriented such that their major axes are oblique with respect to the word lines114and the bit lines126and may be sized such that one active region101intersects two word lines114and one bit line126(as viewed in plan). Accordingly, one active region101may have two unit cell structures. Each such unit cell may have a length of 2F in the first direction and a length of 4F in the second direction, and have an area of 6F2. Here, F refers to a minimum feature size. In this example, a cell area of the 6F2 cell structure is minimal.

However, a semiconductor device according to the inventive concept is not limited to having an 6F2 cell structure layout as described above and as illustrated inFIG. 1, and instead may have an 8F2 cell structure layout in which active regions101intersect word lines114at right angles (as viewed in plan as shown inFIG. 2). Also, semiconductor devices according to the inventive concept may employ other cell structure layouts as desired.

The gate structures115occupy gate trenches106in the substrate100and in addition to the world lines114, may include gate insulating layers108conformally formed on inner surfaces of the substrate100delimiting the gate trenches106.

The word lines114in this embodiment are buried gate lines and constitute buried channel transistors. Buried channel transistors have a smaller unit cell area and greater effective channel length as compared with planar transistors. Also, with buried channel transistors the capacitance between the word line114and the bit line126is minimal as is the total capacitance associated with the bit line126, i.e., parasitic capacitance is minimized.

Each of the gate trenches106may include an active trench106aformed across the corresponding active region101, and a field trench106fformed in the corresponding field region104. The active trench106aand the field trench106fmay be contiguous.

Each of the word lines114may include an active gate electrode114aoccupying the active trench106a, and a field gate electrode114foccupying the field trench106f. Each of the word lines114has a first section occupying the bottommost portion of at least one of the active trenches106aand a second section occupying the bottommost portion of at least one of the field trenches106f. The opposite surfaces of the first section of one of the word lines114face side surfaces of the second section of neighboring ones of the word lines114. Top surfaces of the active gate electrode114aand the field gate electrode114fmay be at substantially the same level or at similar levels within the active region101and the field region104.

Each of the active regions101has first impurity region117sand a second impurity region117don opposite sides of the active gate electrode114aand which serve as a source and a drain of a transistor. The first impurity region117smay be electrically connected to the corresponding capacitor structure135, while the second impurity region117dmay be electrically connected to the corresponding bit line structure125.

Also, in this example, the active trench106aand the field trench106fhave bottoms disposed at different levels. For example, the field trench106fmay have a depth d1 less than the depth d2 of the active trench106aso that the bottom of the field trench106fis disposed at a higher level than the bottom of the active trench106a.

Thus, in this example, a bottom surface b1 of the field gate electrode114fdisposed in and across the field region104is disposed at a higher level than a bottom surface b2 of the active gate electrode114adisposed in and across the active region101. In particular, the bottom surface b1 of the field gate electrode114fdisposed in the field region104between the first impurity regions117sof the active regions101disposed adjacent to each other with one word line114therebetween (e.g., first impurity regions117sin section A inFIG. 1adjacent one another along line II-II′), is disposed at a higher level than the bottom surface b2 of the active gate electrode114a. As a result, the area (of the side surface) of the field gate electrode114fof a word line that faces (is projected onto the side surface of) the active gate electrode114aof a neighboring word line is relatively small, such that word line disturbance between adjacent cells is suppressed.

For instance, inFIG. 1, assuming the case in which the second word line WL2 is turned off and the third word line WL3 is turned on. In this case, parasitic capacitance between the active gate electrode114aof the second word line WL2 and the field gate electrode114fof the third word line WL3 is minimized because the area of the field gate electrode114fof the third word line WL3 that faces the active gate electrode114aof the second word line WL2 is comparatively small (compared to the case in which that active and field gate electrodes are formed together in trenches of the same depths). Thus, a phenomenon in which the electric potential of a channel region disposed under the active gate electrode114aof the turned-off second word line WL2 rises due to a voltage applied to the field gate electrode114fof the third word line WL3 (i.e., word line disturbance) can be prevented.

Referring still toFIGS. 1 and 3A, the field region104includes first and second regions s1 and s2 along the lengthwise direction of each of the word lines WL. Each first region s1 of the field region104spaces respective ones of the active regions101apart from one another by a first distance in the first direction, and each second region s2 of the field region104spaces respective ones of the active regions101apart from one another by a second distance greater than the first distance in the first direction.

The bottom surface b1 of the field gate electrode114fat the top of the second region s2 is disposed at a higher level than the bottom surface b2 of the active gate electrode114a.

Furthermore, in this embodiment, fin recesses110are defined between the field regions104and the active regions101in the direction of the word lines114, that is, in the first direction. In particular, fin recesses110may be located on the sides of the active regions101in the first and second regions s1 and s2. Each gate structure115in this embodiment also includes fin gate electrodes114noccupying the fin recesses110. Furthermore, fin insulating layers112may extend between the active regions101and the fin gate electrodes114nand serve the same function as the gate insulating layers108.

Top surfaces of the active gate electrodes114a, the field gate electrodes114f, and the fin gate electrodes114nmay be disposed at substantially similar levels in the active region101and the field region104.

The bottom surfaces b3 of the fin gate electrodes114nare disposed at a lower level than the bottom surfaces b1 of the field gate electrodes114f. The bottom surfaces b3 of the fin gate electrodes114nare also disposed at a lower level than the bottom surfaces b2 of the active gate electrodes114a.

More specifically, respective ones of the fin gate electrodes114n(whose bottom surfaces b3 are disposed at a lower level than the bottom surfaces b2 of the active gate electrodes114a) are provided in the first region s1 in which word line disturbance is suppressed between adjacent cells. Accordingly, the fin gate electrodes114nensure that a sufficient channel length is provided so that the driving current of a transistor constituting the gate structure115provided with the fin gate electrodes can be increased and operating characteristics of the transistor can be improved.

The gate structures115may further include a gate capping layer116disposed on the gate electrodes114and filling upper regions of the gate trenches106.

In addition to an aforementioned bit line126, each of the bit line structures125may also include a bit line contact pad118bon the second impurity region117d, abit line contact hole122leading to (and into, as shown) the bit line contact pad118b, and a bit line contact plug124filling the bit line contact hole122. The bit line126is disposed directly on the bit line contact plug124in the illustrated example.

Each of the capacitor structures135may include a storage contact pad118son the first impurity region117s, astorage contact hole130leading to (and into, as shown) the storage contact pad118s, astorage contact plug132filling the storage contact hole130, and a capacitor electrode134disposed directly on the storage contact plug132.

In this example, the storage contact pad118sand the bit line contact pad118bmay be contact hole type of contact pads118and may have different sectional areas.

Furthermore, a first interlayer insulating layer120is disposed on the substrate100including over the gate structures115, storage contact pads118s, and bit line contact pads118b. The bit line contact hole122extends through the first interlayer insulating layer120and exposes the bit line contact pad118b.

A second interlayer insulating layer128may be disposed on the bit line structures125and the first interlayer insulating layer120. In this case, the storage contact hole130extends through the first and second interlayer insulating layers120and128and exposes the storage contact pad118s.

A second embodiment of a semiconductor device according to the inventive concept will now be described with reference toFIGS. 1 and 4. Here, features similar to those of the first embodiment will not be described again in detail, though. That is, mainly only those features which differentiate this embodiment from the first embodiment will be described in detail.

In this embodiment of a semiconductor device according to the inventive concept, the bottom surfaces b1 of the field gate electrodes114fare disposed at the same level as the bottom surfaces of the active gate electrodes114a. Also, the bottom surfaces b1 of the field gate electrodes114fare disposed at a higher level than the bottom surfaces b3 of the fin gate electrodes114n.

A third embodiment of a semiconductor device according to the inventive concept will now be described with reference toFIGS. 1 and 5. Here, again, features similar to those of the first embodiment will not be described in detail, though.

In this embodiment of a semiconductor device according to the inventive concept, recess fins110are provided in the first regions s1 of the field regions104but not in the second regions s2.

Furthermore, the bottom surfaces b1 of the field gate electrodes114fare disposed at a lower level than bottom surfaces b2 of the active gate electrodes114a. The bottom surfaces b1 of the field gate electrodes114fare disposed at a higher level than bottom surfaces b3 of the fin gate electrodes114n. On the other hand, the bottom surfaces b3 of the fin gate electrodes114nare disposed at a lower level than the bottom surfaces b2 of the active gate electrodes114a.

A fourth embodiment of the inventive concept will now be described with reference toFIGS. 1 and 6. Here, again, features similar to those of the first embodiment will not be described in detail, though.

In this embodiment of a semiconductor device according to the inventive concept, the word lines114do not include fin gate electrodes. Also, the bottom surfaces b1 of the field gate electrodes114fare disposed at a higher level than bottom surfaces b2 of the active gate electrodes114a.

Also, a field gate electrode114fdisposed in the first region s1, and a field gate electrode114fdisposed in the second region s2 may have bottom surfaces disposed at the same level or have bottom surfaces disposed at different levels. For example, the field gate electrode114fdisposed in the first region s1 of the field region104, where word line disturbance does not occur between adjacent cells, may have a bottom surface disposed at a lower level than a bottom surface of the active gate electrode114a.

A first embodiment of a method of manufacturing a semiconductor device according to the inventive concept will now be described with reference toFIGS. 7A through 7GandFIGS. 8A through 8D. This embodiment may form a device of the type shown in and described with reference toFIGS. 1,3A and3B and so reference will be made to the features of this device in describing the method.

Referring first toFIGS. 1,7A, and8A, substrate100is prepared (provided). For example, the substrate100may be a semiconductor wafer, such as a silicon wafer. The substrate100may include a memory cell array region in which memory cells are to be formed, and a peripheral circuit region in which peripheral circuits configured to operate the memory cells are to be formed.

The substrate100is etched to a predetermined depth to form isolation trenches102in the substrate100defining the active regions101.

Referring toFIGS. 1,7B, and8B, an insulating layer of, silicon oxide, for example, is deposited on the substrate100including the trenches102. Subsequently, the insulating layer is planarized, e.g., etched back, to expose the surface of the substrate100so that trench isolation regions, that is, the field regions104, are formed within the trenches102.

Referring toFIGS. 1,7C,7D, and8C,8D, the first and second impurity regions117sand117dare formed in upper portions of the active regions101and serve as source and drain regions of transistors. The forming of the first and second impurity regions117sand117dmay comprise implanting impurities into the active regions101using an ion implantation process.

Next, a mask (not shown) is formed on the substrate100. The mask has openings which run across the active regions101and extend onto the field regions104. The mask may be formed by photolithography. Then the substrate100is etched using the mask as an etch mask to form the gate trenches106in the substrate100. As was described above, each of the gate trenches106includes an active trench106aextending across an active region101, and a field trench106fin a corresponding field region104.

Also, the field trench106fis formed to a depth d1 smaller than the depth d2 of the active trench106a. In this respect, the field trench106fand the active trench106acan be formed to different depths simultaneously, i.e., by a single etch process, by using a difference in etch selectivity between silicon and silicon oxide when, for example, the substrate100is formed of silicon and the field region104is formed of silicon oxide.

Note, too, that the first and second impurity regions117sand117dmay be formed after the gate trenches106are formed.

After forming the gate trenches106, the gate insulating layers108are formed in the gate trenches106. For instance, the gate insulating layers108may be formed by performing an oxidation process on the substrate100to form silicon oxide layers on the surfaces of the active regions101delimiting the gate trenches106. The gate insulating layers108may be formed of silicon oxide or nitrogen (N)-doped silicon oxide.

Referring toFIGS. 1 and 7D, a mask109is then formed on the field region (refer to A inFIG. 1) between the first impurity regions117sof the active regions101disposed adjacent to each other. For example, the mask109may cover a central portion of each second region s2 of the field region104.

Referring toFIGS. 1 and 7E, the portions of the field region104exposed by the mask109are etched using the mask109as an etch mask. As a result, the fin recesses110are formed to a predetermined depth, namely, a depth d3 greater than the depth d2 to which the active trenches106aare formed. In this example, the fin recesses110are simultaneously formed in the first region s1 of each of the field regions104and in the second region s2 of each of the field regions104between adjacent ones of the active regions101in the word line direction. The mask109may then be removed.

Referring toFIGS. 1 and 7F, the gate insulating layers108exposed by the mask109may be etched, in addition to the field region104, during the etching process for forming the fin recesses110. Accordingly, fin insulating layers112may be formed on those regions of the substrate100exposed by the fin recesses110to compensate for etching damage to the gate insulating layers108. For example, the fin insulating layer112is formed by performing an oxidation process on the substrate100to form silicon oxide layers on the active regions101exposed by the fin recesses110.

Referring toFIGS. 1,7G, and8D, a conductive layer formed of, for example, a metal, is deposited on the substrate100and patterned, thereby forming word lines114each including an active gate electrode114adisposed within the active trench106a, afield gate electrode114fdisposed within the field trench106f, and a fin gate electrode114ndisposed within the fin recess110.

Subsequently, and referring toFIG. 3B, gate capping layers116may be formed on the substrate100having the word lines114, thereby completing the formation of the gate structures115. For example, the gate capping layer116may be formed by depositing capping insulating layer on the substrate100having the word lines114, and planarizing the capping insulating layer.

The gate capping layer116may then be etched to form contact holes exposing the first and second impurity regions117sand117dof the transistors. Then, conductive material may be formed in the contact holes, i.e., may be buried in the gate capping layer116, thereby forming the storage contact pads118sand bit line contact pads118belectrically connected to the first and second impurity regions117sand117d.

First interlayer insulating layer120is then formed on the substrate100. The first interlayer insulating layer120may be formed of silicon oxide or silicon nitride.

The first interlayer insulating layer120is then etched to form bit line contact holes122exposing the second impurity regions117d. The bit line contact holes122are filled with a conductive material, thereby forming bit line contact plugs124electrically connected to the bit line contact pads118b. Next, a conductive layer is deposited on the bit line contact plugs124and the first interlayer insulating layer120and is patterned to thereby form bit lines126electrically connected to the second impurity regions117d.

A second interlayer insulating layer128is then formed on the substrate100over the bit lines126. The second interlayer insulating layer128may be formed of silicon oxide or silicon nitride.

The second interlayer insulating layer128and the first interlayer insulating layer120are etched to form storage contact holes130exposing the storage contact pads118s. The storage contact holes130are then filled with a conductive material, thereby forming storage contact plugs132electrically connected to the storage contact pads118s. Next, a conductive layer is deposited on the storage contact plugs132and the second interlayer insulating layer128and patterned, thereby forming capacitor electrodes134electrically connected to the first impurity regions117s.

A second embodiment of a method of manufacturing a semiconductor device according to the inventive concept will now be described with reference toFIGS. 9A through 9E. This embodiment may form a device of the type shown in and described with reference toFIGS. 1 and 4and so reference will be made to the features of this device in describing the method.

Referring first toFIG. 9A, a substrate100having gate trenches106and gate insulating layers108is formed similarly to the way in which the structure ofFIG. 7Cis formed. However, in this case, each of the gate trenches106is formed to a uniform depth such that the field trench106fis formed to a depth d1 equal to the depth d2 of the active trench106a.

Referring toFIG. 9B, a mask109is formed on the field region (refer to A inFIG. 1) between the first impurity regions117sof adjacent ones of the active regions101in the a first direction, namely, the word line direction. For example, the mask109is formed to cover central portions of the second regions s2 of the field regions104in the first line direction.

Referring toFIG. 9C, the exposed region of the field region104is etched using the mask109as an etch mask to form the fin recesses110to a depth d3 greater than the depth d1 to which the field trenches106fand the depth d2 to which the active trenches106aare formed. The fin recesses110are formed adjacent the sides of the active regions110in the first direction. In this example, the fin recesses110are simultaneously formed in the first region s1 of each of the field regions104and in the second region s2 of each of the field regions104between adjacent ones of the active regions101in the word line direction. The mask109may then be removed.

Referring toFIG. 9D, the gate insulating layers108exposed by the mask109may be etched, in addition to the field region104, during the etching process for forming the fin recesses110. Accordingly, fin insulating layers112may be formed on those regions of the substrate100exposed by the fin recesses110to compensate for etching damage to the gate insulating layers108. For example, the fin insulating layer112is formed by performing an oxidation process on the substrate100to form silicon oxide layers on the active regions101exposed by the fin recesses110.

Referring toFIG. 9E, a conductive layer is deposited on the substrate100and patterned, thereby forming word lines114each including an active gate electrode114aoccupying an active trench106a, afield gate electrode114foccupying a corresponding field trench106f, and a fin gate electrode114ndisposed in a corresponding fin recess110. And accordingly, the bottom surface b1 of the field gate electrode114fformed on the second region s2 of the field region104is disposed at a higher level than the bottom surface b3 of the fin gate electrode114n.

Subsequently, the processes described above with reference toFIG. 3Bare performed. As a result, a semiconductor device of the type described with reference toFIG. 4is formed.

A third embodiment of a method of manufacturing a semiconductor device according to the inventive concept will be described with reference toFIGS. 10A through 10D. This embodiment may form a device of the type shown in and described with reference toFIGS. 1 and 5and so reference will be made to the features of this device in describing the method.

Referring first toFIG. 10A, a structure is formed using processes similar to those described with reference toFIGS. 7A through 7C. Thus, a substrate100having gate trenches106and gate insulating layers108is formed. However, in this case, each gate trenches106includes an active trench106adisposed across an active region101, and a field trench106fformed in a field region104, and the field trench106fis formed to a depth d1 greater than the depth d2 to which the active trench106ais formed.

Referring toFIG. 10B, a mask109is formed on the substrate100. The mask109has openings109aexposing the first regions s1 of the field region104.

Referring toFIG. 10C, the field oxide104is etched using the mask pattern109as an etch mask. As a result, fin recesses110are formed in the first regions s1 of the field region104. The fin recesses110are formed to a depth d3 greater than the depth d1 of the field trenches106f. The mask109may then be removed.

The gate insulating layers108exposed by the mask109may be etched, in addition to field region104, during the etching process for forming the fin recesses110. Accordingly, fin insulating layers112may be formed on those regions of the substrate100exposed by the fin recesses110to compensate for etching damage to the gate insulating layers108. For example, the fin insulating layer112is formed by performing an oxidation process on the substrate100to form silicon oxide layers on the active regions101exposed by the fin recesses110.

Referring toFIG. 10D, a conductive layer is deposited on the substrate100having the fin insulating layers112and patterned, thereby forming word lines114each including an active gate electrode114aoccupying an active trench106a, afield gate electrode114foccupying the corresponding field trench106f, and a fin gate electrode114ndisposed in a corresponding fin recess110. And accordingly, the bottom surface b1 of field gate electrode114fformed on the second region s2 of the field region104is disposed at a higher level than the bottom surface b3 of the fin gate electrode110. Also, the bottom surface b3 of the fin gate electrode110is disposed at a lower level than the bottom surface b2 of the active gate electrode114a.

Subsequently, the processes described with reference toFIG. 3Bare performed. As a result, a semiconductor device of the type described with reference toFIG. 5is formed.

A fourth embodiment of a method of manufacturing a semiconductor device according to the inventive concept will now be described with reference toFIGS. 11A and 11B. This embodiment may form a device of the type shown in and described with reference toFIGS. 1 and 6and so reference will be made to the features of this device in describing the method.

Referring toFIG. 11A, a substrate100having gate trenches106and gate insulating layers108is formed. In this case, each gate trenches106includes an active trench106adisposed across an active region101, and a field trench106fformed in a field region104, and the field trench106fis formed to a depth d1 less than the depth d2 to which the active trench106ais formed.

Referring toFIG. 11B, a conductive layer is then deposited on the substrate100, thereby forming word lines114each including active gate electrodes114adisposed in the active trenches106a, and field gate electrodes114fdisposed in the corresponding field trenches106f.

Subsequently, the processes described with reference toFIG. 3Bare performed. As a result, a semiconductor device of the type described with reference toFIG. 6is formed.

FIG. 12illustrates a semiconductor module2000having a semiconductor device according to the inventive concept.

Referring toFIG. 12, the semiconductor module2000includes a control unit2020, a storage unit2030, and input/output (I/O) units2040disposed on a module substrate2010.

The module substrate2010may comprise a printed circuit board (PCB).

The control unit2020comprises a logic device, such as a controller.

The storage unit2030may include a memory device, such as a dynamic random access memory (DRAM), a magnetic RAM (MRAM), or a NAND flash memory.

The control unit2020and/or the storage unit2030may include a semiconductor device according to any of the embodiments of the inventive concept or a semiconductor device manufactured using any of the embodiments of a method according to the inventive concept.

The semiconductor module2000may be a memory card and hence, may comprise a solid-state drive (SSD).

FIG. 13illustrates an electronic system2100including a semiconductor device according to the inventive concept.

The electronic system2100includes a microprocessor (MP) unit2120, a power unit2130, a functional unit2140, and a display controller unit2150integrated by a body2110of the system. The body2110may be a system board or motherboard constituted by a PCB. In this case, the MP unit2120, the power unit2130, the functional unit2140, and the display controller unit2150are mounted on the body2110.

The system2100also includes a display unit2160. The display unit2160may be disposed on a top surface of the body2110or outside the body2110. For example, the display unit2160may be disposed on a surface of the body2110and display an image processed by the display controller unit2150.

The power unit2130may receive a predetermined voltage from an external power source, divide the predetermined voltage into various voltage levels, and transmit the divided voltages to the MP unit2120, the functional unit2140, and the display controller unit2150.

The MP unit2120may receive a voltage from the power unit2130and control the functional unit2140and the display unit2160.

The functional unit2140may implement various functions of the electronic system2100. For instance, when the electronic system2100is a mobile electronic product, such as a portable phone, the functional unit2140may include several elements capable of performing wireless communication functions, such as outputting an image to the display unit2160or outputting sound (voice) to a speaker, and dialing or facilitating communication with an external unit2170. When the functional unit2140includes a camera, the functional unit2140may serve as an image processor.

In another application, the electronic system2100may be connected to a memory card to increase the capacity of the electronic system2100. In this case, the functional unit2140may be a memory card controller.

In any case, the functional unit2140may exchange signals with the external apparatus2170through a wired or wireless communication unit2180.

In addition, in an application in which the electronic system2100employs a universal serial bus (USB), the functional unit2140may serve as an interface controller.

At least one of the MP unit2120and the functional unit2140includes an embodiment of a semiconductor device according to the inventive concept, or a semiconductor device manufactured using an embodiment of a method according to the inventive concept.

According to an aspect of the inventive concept as described above, the bottom surface of a field gate electrode disposed across a field region (i.e., a pass gate electrode) is disposed at a higher level than the bottom surface of an active gate electrode (i.e., a cell electrode) disposed across an active region and/or the bottom surface of a fin gate electrode interposed between active regions and the field region so that word line disturbance between adjacent active regions can be reduced.

Finally, embodiments of the inventive concept and examples thereof have been described above in detail. The inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments described above. Rather, these embodiments were described so that this disclosure is thorough and complete, and fully conveys the inventive concept to those skilled in the art. Thus, the true spirit and scope of the inventive concept is not limited by the embodiment and examples described above but by the following claims.