SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor device includes a base layer including a silicon material. A field effect transistor is disposed on a first surface of the base layer. A first insulating interlayer covers the field effect transistor, A buried vertical rail passes through the first insulating interlayer and the base layer. The buried vertical rail includes a first metal pattern and a first barrier pattern surrounding a sidewall of the first metal pattern. A first lower insulating interlayer is on the second surface of the base layer. A lower contact plug passes through the first lower insulating interlayer and directly contacts a lower surface of the buried vertical rail. The lower contact plug includes a second metal pattern and a second barrier pattern surrounding a sidewall of the second metal pattern. A bottom surface of the first metal pattern and a top surface of the second metal pattern directly contact each other.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2022-0095806, filed on Aug. 2, 2022 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein.

TECHNICAL FIELD

Embodiments of the present disclosure relate to a semiconductor device and method for manufacturing the same. In particular, embodiments relate to a semiconductor device including power delivery network wirings on a back side of a base layer and method for manufacturing the same.

DISCUSSION OF RELATED ART

In a highly integrated semiconductor device, circuit elements and wirings for transmitting signals to the circuit elements may be formed on a front side of a base layer, and wirings for a power delivery may be formed on a back side of the base layer. A process for forming the wiring on the back side of the base layer may include a depositing and etching process of a metal material. Defects may occur during the processes of the depositing and etching of the metal material for forming the wiring on the back side of the base layer.

SUMMARY

An example embodiment provides a semiconductor device having excellent electrical characteristics.

An example embodiment provides a method for manufacturing a semiconductor device having excellent electrical characteristics.

According to an embodiment, a semiconductor device includes a base layer including a silicon material. The base layer includes a first surface and a second surface opposite to the first surface in a vertical direction. A field effect transistor is disposed on the first surface of the base layer. A first insulating interlayer covers the field effect transistor. A buried vertical rail passes through the first insulating interlayer and the base layer. The buried vertical rail includes a first metal pattern having a sidewall and a first barrier pattern surrounding the sidewall of the first metal pattern, A first lower insulating interlayer is on the second surface of the base layer. A lower contact plug passes through the first lower insulating interlayer and directly contacts a lower surface of the buried vertical rail. The lower contact plug includes a second metal pattern having a sidewall and a second barrier pattern surrounding the sidewall of the second metal pattern. A bottom surface of the first metal pattern and a top surface of the second metal pattern directly contact each other.

According to an embodiment, a semiconductor device includes a base layer including a silicon material. The base layer includes a first surface and a second surface opposite to the first surface in a vertical direction. Active fins protrude from the first surface of the base layer in the vertical direction. The active fins extend in a first direction. A gate structure is on the first surface of the base layer. The gate structure extends in a second direction perpendicular to the first direction and crosses the active fins. Semiconductor patterns are on active fins adjacent to both sides of the gate structure. The semiconductor patterns include impurity regions. A first insulating interlayer is on the first surface of the base layer. The first insulating interlayer covers the gate structure and the semiconductor patterns. A buried vertical rail passes through the first insulating interlayer and the base layer in the vertical direction. The buried vertical mil includes a first metal pattern having a sidewall and a first barrier pattern surrounding the sidewall of the first metal pattern. A first lower insulating interlayer is on the second surface of the base layer. A lower contact plug passes through the first lower insulating interlayer in the vertical direction and directly contacts a lower surface of the buried vertical rail. The lower contact plug includes a second metal pattern having a sidewall and a second barrier pattern surrounding the sidewall of the second metal pattern. A bottom surface of the first metal pattern and a top surface of the second metal pattern directly contact each other.

According to an embodiment, a method for manufacturing a semiconductor device includes forming a field effect transistor on a first surface of a substrate. A first insulating interlayer is formed that covers the field effect transistor. A preliminary buried vertical rail is formed that extends through the first insulating interlayer to an upper portion of the substrate. The preliminary buried vertical rail includes a first metal pattern having a sidewall and a bottom and a first preliminary barrier pattern surrounding the sidewall and the bottom of the first metal pattern. A second surface of the substrate that is opposite to the first surface is removed to expose a lower surface of the first preliminary barrier pattern to form a base layer. A first lower insulating interlayer is formed on a lower surface of the base laver. A first hole is formed that passes through the first lower insulating interlayer and exposes the first preliminary barrier pattern of the preliminary buried vertical rail. A buried vertical rail is formed that includes a first barrier pattern and the first metal pattern by etching the first preliminary barrier pattern exposed by the first hole to form the first barrier pattern. A second barrier layer is formed on a sidewall of the first hole and a bottom of the buried vertical rail. The second barrier layer is etched on a lower surface of the buried vertical rail to form a second barrier pattern on the sidewall of the first hole. A second metal pattern is formed that fills the first hole and directly contacts the first metal pattern on the second barrier pattern to form a lower contact plug including the second metal pattern having a sidewall and the second barrier pattern surrounding the sidewall of the second metal pattern

In an example embodiment, the semiconductor device may not include a barrier pattern at a contact portion between the first metal pattern passing through the base layer and the second metal pattern formed on the second surface of the base layer. Thus, contact resistance between the first metal pattern and the second metal pattern may be decreased. In addition, etching processes for forming the barrier pattern surrounding of a sidewall of each of the first and second metal patterns may be controlled so as to decrease a residue due to re-sputtering of a metal during the etching process.

DETAILED DESCRIPTION OF EMBODIMENTS

Hereinafter, a direction parallel to an upper surface of a substrate is referred to as a first direction, and a direction parallel to the upper surface of the substrate and perpendicular to the first direction is referred to as a second direction. In addition, a direction perpendicular to the surface of the substrate is referred to as a vertical direction.

FIG.1is a cross-sectional view illustrating a semiconductor device in accordance with an example embodiment.FIGS.2A and2Bare enlarged cross-sectional views illustrating a portion of a semiconductor device in accordance with some example embodiments, respectively.FIG.3is a plan view of a transistor portion in a semiconductor device in accordance with an example embodiment.FIG.4is a cross-sectional view of a gate structure of a fin field effect transistor (fin FET) in accordance with an example embodiment.FIG.5is a cross-sectional view of a gate structure of a multi-bridge channel-field effect transistor (MBC FET) in accordance with an example embodiment.

FIG.1is a cross-sectional view taken along line I-I′ ofFIG.3. Each ofFIGS.2A and2Binclude a contact portion between a buried vertical rail and a first lower contact plug.FIG.4is a cross-sectional view taken along line II-II′ ofFIG.3serving as the fin FET.FIG.5is a cross-sectional view taken along line II-II′ ofFIG.3serving as the MBC FET.

Referring toFIGS.1to3, the semiconductor device may include a field effect transistor, such as a fin FET or an MBC FET. Hereinafter, the semiconductor device including the fin FET may be mainly described for convenience of explanation. However, embodiments of the present disclosure are not necessarily limited thereto.

The fin FET may constitute a logic cell. In an embodiment, the logic cell may be configured in various different forms, such as AND, NAND, OR, NOR, exclusive OR (XOR), exclusive NOR (XNOR), inverter (INV), adder (ADD), buffer (BUF), delay (DLY), filter (FIL), multiplexer (MXT/MXIT), OAI (OR/AND/INVERTER), AO (AND/OR), AOI (AND/OR/INVERTER), D flip-flop, reset flip-flop, master-slaver flip-flop and latch, etc. The logic cells may constitute standard cells that perform desired logical functions such as counters and butlers.

A base layer100amay include a semiconductor material, such as a silicon material. The base layer100amay be formed so as to have a relatively thin thickness by removing one surface of a substrate including a semiconductor material. For example, in an embodiment the base layer100amay include single crystal silicon.

A first surface of the base layer100ais defined as a front side of the base layer100a,and a second surface opposite to the first surface of the base layer100ais defined as a back side of the base layer100a.In an embodiment as shown inFIGS.1to5, the first surface of the base layer100amay be an upper side and the second surface of the base layer100amay be a lower side.

A plurality of active fins102may protrude in the vertical direction from the first surface of the base layer100a.The active fins102may extend in the second direction. The active fins102may be spaced apart from each other in the first direction.

In an embodiment, active fins102that are spaced apart from each other in the first direction by a predetermined first interval may form an active fin group. A plurality of active fin groups may be spaced apart by a second interval greater than the first interval.

An isolation pattern104may fill a lower portion of a trench between the active fins102. In an embodiment, upper sidewalls and upper surfaces of the active fins102may be exposed by the isolation pattern104. Upper portions of the active fins102may protrude from an upper surface of the isolation pattern104. In an embodiment, the isolation pattern104may include, for example, silicon oxide.

As shown inFIG.4, the gate structure112may extend in the first direction to cross the active fins102. The plurality of gate structures112may have the same width in the second direction to each other, and may be arranged to have regular intervals in the second direction.

The gate structure112may have a structure in which a gate insulation layer112a,a gate electrode112b,and a capping pattern112care stacked. In an embodiment, the gate insulation layer112amay include a silicon oxide layer, a high dielectric layer, or a combination thereof. The high dielectric layer may include a material having a dielectric constant higher than a dielectric constant of the silicon oxide layer. For example, the high dielectric layer may include metal oxide or metal oxynitride. The gate electrode112bmay include a metal material. In an embodiment, the capping pattern112cmay include silicon nitride or silicon oxynitride.

In an embodiment, as shown inFIG.4, the gate structure112may be formed on sidewalls and upper surfaces of the active fins102. For example, the gate structure may cover an upper portion of the sidewalls of the active fins102and a top surface of the active fins102. In this embodiment, fin FETs may be formed on the active fins102.

In an embodiment, as shown inFIG.5, the active fin101amay include gaps spaced apart from each other in the vertical direction. The gap may pass through the active fin in a horizontal direction. The gate structure112may be formed on sidewalk and top surfaces of the active fins101aand inside the gaps. In this embodiment, MBC FETs may be formed on the active fins101a.

Referring toFIGS.1to3, a recess may be formed in the active fin102adjacent to both sides of the gate structure112, and a semiconductor pattern108may be formed in the recess. For example, in an embodiment the semiconductor pattern108may include silicon or silicon germanium. However, embodiments of the present disclosure are not necessarily limited thereto.

The semiconductor pattern108may be doped with impurities. The semiconductor pattern108may serve as a source/drain region of the field effect transistor. A sidewall of the semiconductor pattern108may protrude further in the first direction than the sidewall of the active fin102. In a cross-sectional view taken in the first direction, the semiconductor pattern108may have a polygonal shape having a protruding central portion, such as a pentagonal shape, a hexagonal shape, or a partial quadrangle shape. However, embodiments of the present disclosure are not necessarily limited thereto.

In an embodiment, portions of sidewalk of adjacent semiconductor patterns108may directly contact each other. In this embodiment, each of the semiconductor patterns108may be connected to each other in the first direction. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in some embodiments, sidewalls of the semiconductor patterns108may not directly contact each other and an entirety of the sidewalk of adjacent semiconductor patterns108may be spaced apart from each other.

A first insulating interlayer110and a second insulating interlayer114may cover the gate structure112and the semiconductor pattern108. The first insulating interlayer110may be disposed on (e.g., directly thereon) upper surfaces of the isolation pattern104. The second insulating interlayer114may be disposed directly on an upper surface of the first insulating interlayer110. The first and second insulating interlayers110and114may include substantially the same material. In an embodiment, the first and second insulating interlayers110and114may include silicon oxide.

A buried vertical rail hole120may pass through the first and second insulating interlayers110and114, the isolation pattern104and the base layer100a(e.g., in the vertical direction). In an embodiment, the buried vertical rail hole120may pass through the isolation pattern104at a portion of the trench having the second interval between the active fins102. In an embodiment, the buried vertical rail hole120may have a sidewall slope such that an inner width gradually decreases from a top portion to a bottom portion. For example, the buried vertical rail hole120may have the sidewall slope such that an inner width gradually decreases from an upper surface of the buried vertical rail hole120of the second insulating interlayer114towards a lower surface of the base layer100a.

An insulation liner122may be formed on a sidewall of the buried vertical rail hole120, In an embodiment, the insulation liner122may include silicon oxide (SiOx), silicon nitride (SiN), or silicon oxycarbonitride (SiOCN). However, embodiments of the present disclosure are not necessarily limited thereto.

A first barrier pattern124bmay be formed on the insulation liner122. The first barrier pattern124bmay be formed on the sidewall of the buried vertical rail hole120.

A first metal pattern126amay be formed on the first barrier pattern124b(e.g., an inner surface of the first barrier pattern124b) to fill the buried vertical rail hole120. The first barrier pattern124bmay be formed only on a sidewall of the first metal pattern126a,and may surround the sidewall of the first metal pattern126a.The first barrier pattern124bmay not be formed on a bottom surface of the first metal pattern126a.

A buried vertical rail130aincluding the first barrier pattern124band the first metal pattern126amay be formed in the buried vertical rail hole120. The buried vertical rail130amay extend in the vertical direction to pass through the first and second insulating interlayers110and114, the isolation pattern104and the base layer100a.The insulation liner122may surround an outer wall of the buried vertical rail130aand may be disposed between the buried vertical rail130aand the base layer100a.The base layer100aand the buried vertical rail130amay be insulated from each other by the insulation liner122.

In an embodiment, the first barrier pattern124hmay include, for example, Ti, Ta TiN, TaN, or a combination thereof. The first metal pattern126amay include, for example, Cu, W, Mo, Ru, or Nb.

A third insulating interlayer134may cover the second insulating interlayer114and the buried vertical rail130a.For example, the third insulating interlayer134may directly contact an upper surface of the second insulating interlayer114, A first contact plug140may be formed in the first to third insulating interlayers110,114, and134to be electrically connected with an upper portion of the semiconductor pattern108and an upper portion of the buried vertical rail130a.The first contact plug140may directly contact at least a portion of the upper portion of the semiconductor pattern108serving as the impurity region and at least a portion of the upper portion of the buried vertical rail130ato electrically connect the buried vertical rail130aand the impurity regions. The first contact plug140may include the second barrier pattern140aand the second metal pattern140b.A lower portion of the sidewall of the second barrier pattern140amay directly contact the first insulating interlayer110, a central portion of the sidewall of the second barrier pattern140amay directly contact the second insulating interlayer114and an upper portion of the sidewall of the second barrier pattern140amay directly contact the third insulating interlayer134.

In some embodiments, a second contact plug may be further formed on the gate electrode112bin the gate structure112. The second contact plug may be electrically connected to the gate electrode112bin the gate structure112. However, embodiments of the present disclosure are not necessarily limited thereto and three or more contact plugs may be further formed on the gate electrode112bin some embodiments.

An etch stop layer200and a first lower insulating interlayer202may be formed on the second surface of the base layer100a.A first lower contact plug230may pass through the first lower insulating interlayer202and the etch stop layer200, and thus the first lower contact plug230may directly contact the buried vertical rail130a,such as a lower portion of the buried vertical rail130a.The first lower contact plug230may till a first hole210apassing through the first lower insulating interlayer202and the etch stop layer200. However, embodiments of the present disclosure are not necessarily limited thereto. For example, in some example embodiments, the etch stop layer200may not be formed.

The first lower contact plug230may include a third barrier pattern212aand a third metal pattern220. The third barrier pattern212amay be formed on a sidewall of the first hole210a,and the third metal pattern220may be formed on the third barrier pattern212ato fill the first hole210a.The third barrier pattern212amay surround a sidewall of the third metal pattern220.

As shown inFIGS.2A and2B, a top surface of the third metal pattern22.0may directly contact a bottom surface of the first metal pattern126a.Therefore, a barrier pattern ay not be formed between the top surface of the third metal pattern220and the bottom surface of the first metal pattern126a.Accordingly, a contact resistance between the buried vertical rail130aand the first lower contact plug230may be decreased.

A contact surface between the buried vertical rail130aand the lower contact plug230amay not be coplanar with the lower surface (e.g., the second surface) of the base layer100a.For example, the contact surface between the buried vertical rail130aand the lower contact plug230amay be located on a plane that is different from the bottom surface of the base layer100a.In an embodiment, the contact surface between the buried vertical mil130aand the lower contact plug230amay be higher than the lower surface of the base layer100a.A portion (e.g., interface) between the third metal pattern220and the first metal pattern126ain which the third metal pattern220and the first metal pattern126adirectly contact each other may be higher than the lower surface of the base layer100a.

In an embodiment, the first lower contact plug230may be vertically aligned with the buried vertical rail130a.

As shown inFIG.2A, an upper surface of the first lower contact plug230and a lower surface of the buried vertical rail130amay have the same or similar areas as each other. For example, in an embodiment the upper surface of the first lower contact plug230and the lower surface of the buried vertical rail130amay completely overlap (e.g., in the vertical direction), and may directly contact each other.

As shown inFIG.2B, an area of an upper portion of the first lower contact plug230may be greater than an area of a lower portion of the buried vertical rail130a.In this embodiment, a barrier layer may not be formed at a contacting portion in which a top surface of the third metal pattern220and a bottom surface of the first metal pattern126adirectly contact each other. However, the third barrier pattern212amay remain on a portion below the contacting portion in which the upper surface of the third metal pattern220is not in direct contact with the first metal pattern126a.The first barrier pattern124bmay extend below the contacting portion and the first metal pattern and may directly contact an upper surface of the third barrier pattern212a.In an embodiment, an additional insulation liner122amay be further formed to surround an outer surface of the first lower contact plug230.

A fourth insulating interlayer150may be formed on (e.g., disposed directly thereon) the third insulating interlayer134, the first contact plug140and the second contact plug. A first upper wiring152for transmitting signals may be formed inside and on the fourth insulating interlayer150to be electrically connected to the field effect transistor. In an embodiment, the first upper wiring152may be electrically connected to the first and second contact plugs.

A first upper insulating interlayer160may cover the first upper wirings152, The first upper wirings152may be multilayer wirings. While an embodiment ofFIG.1shows two layers of wirings for the first upper wirings152, embodiments of the present disclosure are not necessarily limited thereto and the number of layers may vary. The first upper wirings152may include contact plugs and conductive lines. The first upper wirings152may include a metal material. In an embodiment, the first upper wirings152may include, for example, Cu, W, Mo, Ru, or Nb.

The first upper wirings152may be positioned on the first surface (e.g., the front side) of the base layer100a.The first upper wirings152may apply signals to circuit elements formed on the base layer100a.

A second lower insulating interlayer240and a first lower wiring242are formed on (e.g., disposed directly thereon) a lower surfaces of the first lower insulating interlayer202and the first lower contact plug230. The first lower wiring242may be disposed in the second lower insulating interlayer240.

The first lower wirings242may be multi-layer wirings. While an embodiment ofFIG.1shows three layers of wirings for the first lower wirings242, embodiments of the present disclosure are not necessarily limited thereto and the number of layers may vary. The first lower wirings242may include contact plugs and conductive lines, The first lower wirings242may include a metal material. In an embodiment, the first lower wirings242may include, for example, Cu, W, Mo, Ru, or Nb. The first lower wirings242may be electrically connected to the first lower contact plug230.

The first lower wirings242may be formed on the second surface (e.g., the back side) of the base layer100a.The first lower wirings242may apply power to the circuit elements formed on the base layer100a,In an embodiment, the first lower wiring242may include a barrier pattern and a metal pattern.

In an embodiment embodiments, a protective layer may be formed on an uppermost insulating interlayer.

FIGS.6to24are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with some example embodiments.

Hereinafter, a method of manufacturing a semiconductor device including a fin FET is described.

Referring toFIG.6, a portion of a substrate100may be etched to form a plurality of active fins102that protrude from an upper surface of the substrate100in the vertical direction and extend in the second direction, In an embodiment, the substrate100may include a semiconductor material. For example, the substrate100may include single crystal silicon. The active fins102that are spaced apart from each other in the first direction by the first interval may form an active fin group. A plurality of active fins group may be spaced apart to each other by a second interval that is greater than the first interval.

An isolation layer covering the active fins102may be formed to completely fill a space between the active fins102. In an embodiment, the isolation layer may include, for example, silicon oxide.

An upper portion of the isolation layer may be partially etched to expose upper sidewalk and upper surfaces of the active fins102to form isolation patterns104. Accordingly, upper portions of the active fins102may protrude from the surface of the isolation pattern104.

Referring toFIGS.7and8, dummy gate structures106may be formed on the active fins102and the isolation pattern104so as to cross the active fins102. The dummy gate structures106may extend in the first direction. In an embodiment, the dummy gate structures106may include a dummy gate insulation layer106a,a dummy gate pattern106b,and a dummy capping pattern106csequentially stacked. In an embodiment, spacers may be formed on both sides of the dummy gate structure106.

Referring toFIG.9, upper portions of the active fins102adjacent to both sides of the dummy gate structure106may be etched to form recesses. A selective epitaxial growth process may be performed to grow a semiconductor material from the active fins102of a bottom surface of the recess. Thus, a semiconductor pattern108may be formed in the recess. For example, in an embodiment the semiconductor pattern108may include silicon or silicon germanium.

The semiconductor pattern108may be doped with impurities. The semiconductor pattern108may serve as a source/drain region of a fin FET. A sidewall of the semiconductor pattern108may protrude more in the first direction than a sidewall of the active fins102. In an embodiment, in a cross-sectional view taken in the first direction, the semiconductor pattern108may have a polygonal shape having a protruding central portion, such as a pentagonal shape, a hexagonal shape, or a partial quadrangle shape.

Referring toFIGS.10and11, a first insulating interlayer110may be formed to cover the dummy gate structure106and the semiconductor pattern108. The first insulating interlayer110may be planarized until an upper portion of the dummy gate structure106may be exposed. In an embodiment, the first insulating interlayer110may include silicon oxide.

The dummy gate structure106may be removed to form a first trench. A gate structure112may be formed in the first trench. As shown in MG.10, in an embodiment the gate structure112may include a gate insulation layer112a,a gate electrode112band a capping pattern112c.

A second insulating interlayer114may be formed on the first insulating interlayer110. In an embodiment, the first and second insulating interlayers110and114may include substantially the same material.

Referring toFIG.12, a buried vertical rail hole120may be formed through the first and second insulating interlayers110and114and the isolation pattern104, and may extend to an inner portion of the substrate100. In some example embodiments, the buried vertical rail hole120may be formed to pass through a portion of the isolation pattern104having the second interval between the active fins.

In an embodiment, the buried vertical rail hole120may be formed by a dry etching process. Due to a nature of the dry etching process, the buried vertical rail hole120may have a sidewall slope such that an inner width gradually decreases from a top portion of the buried vertical rail hole120towards a bottom portion of the buried vertical rail hole120.

An insulation liner122may be formed along a sidewall and bottom surface of the buried vertical rail hole120and an upper surface of the second insulating interlayer114. In an embodiment, the insulation liner122may include, for example, silicon oxide (SiOx), silicon nitride (SiN), or silicon oxycarbonitride (SiOCN).

A first preliminary barrier layer124may be formed on the second insulating interlayer114along a surface profile of the buried vertical rail hole120. A first metal layer126may be formed on the first preliminary barrier layer12.4to fill the buried vertical rail hole120.

In an embodiment, the first preliminary barrier layer124may be formed of, for example, Ti, Ta, TiN, TaN, or a combination thereof, The first metal layer126may be formed of, for example, Chu, W, Mo, Ru, or Nb.

Referring to HQ13, the first preliminary barrier layer124, the first metal layer126, and the insulation liner122may be planarized until an upper surface of the second insulating interlayer114may be exposed to form a preliminary buried vertical rail130in the buried vertical rail hole120. In an embodiment, the preliminary buried vertical rail130may include a first preliminary barrier pattern124aand a first metal pattern126a.

Referring toFIGS.14and15, a third insulating interlayer134may be formed to cover the second insulating interlayer114and the preliminary buried vertical rail130.

Portions of the first to third insulating interlayers110,114and134may be etched to form a first contact hole136exposing at least portion of an upper surface of the semiconductor pattern108and at least portion of an upper portion of the preliminary buried vertical rail130. In the process of forming the first contact hole136, an upper portion of the preliminary buried vertical rail130may be partially removed.

In some example embodiments, a portion of the capping pattern112cof the gate structure112may be further etched to form a second contact hole exposing the upper surface of the gate electrode112b.

A first contact plug140may be formed in the first contact hole136. In addition, a second contact plug may be formed in the second contact hole. The first contact plug140may directly contact the semiconductor pattern108and the preliminary buried vertical rail130, respectively. Accordingly, the first contact plug140may be electrically connected with the semiconductor pattern108and the preliminary buried vertical rail130. In an embodiment, the first contact plug140may include a metal material.

In some example embodiments, a second barrier layer may be formed along surfaces of the first contact hole136and the second contact hole and an upper surface of the third insulating interlayer134. A second metal layer may be formed on the second barrier layer to fill the first contact hole136and the second contact hole. Thereafter, the second barrier layer and the second metal layer may be planarized until the upper surface of the third insulating interlayer134may be exposed to form the first contact plug140filling the first contact hole136and the second contact plug filling the second contact hole. In an embodiment, each of the first contact plug140and the second contact plug may include a second barrier pattern140aand a second metal pattern140b.

Referring toFIG.16, a fourth insulating interlayer150may be formed on the third insulating interlayer134, the first contact plug140and the second contact plug. First upper wirings152electrically connected to the first and second contact plugs may be formed on the first contact plug140and the second contact plug and inside of the fourth insulating interlayer150. A first upper insulating interlayer160may be formed on the fourth insulating interlayer150and may cover the first upper wirings152.

In an embodiment, the first upper wirings152may be formed as multilayer wirings. The first upper wirings152may include contact plugs and conductive lines. The first upper wirings152may include a metal material. The first upper wirings152may include, for example, Cu, W, Mo, Ru, or Nb.

The first upper wirings152may be positioned on the front side of the substrate100(e.g., a base layer). The first upper wirings152may apply signals to the circuit elements (e.g., field effect transistors) formed on the substrate100.

Referring toFIG.17, an insulation bonding layer may be formed on the first upper insulating interlayer160.

A carrier substrate170may be attached on the insulation bonding layer. In an embodiment, the carrier substrate170may be, for example, a semiconductor wafer, a ceramic substrate, or a glass substrate.

Referring toFIG.18, the substrate100may be rotated180degrees so that the carrier substrate170may be positioned below. Accordingly, a back side surface of the substrate100may be positioned on an uppermost portion from the carrier substrate170. Hereinafter, a portion close to the carrier substrate170is referred to as a lower portion, and a portion close to the back side surface of the substrate100is referred to as an upper portion.

The back side surface of the substrate100may be removed until the first preliminary barrier pattern124aof the preliminary buried vertical rail130may be exposed to form a base layer100ahaving thin thickness. In the removing process of the back side surface of the substrate100, the insulation liner122positioned on an upper portion of the preliminary buried vertical rail130may be removed.

In an embodiment, the substrate100may be removed by a predetermined thickness through a back grinding process or a backlap process. Thereafter, the back side surface of the substrate may be further removed to expose the preliminary buried vertical rail130by a chemical mechanical polishing (CHIP) process, an etch-back process, or a combination thereof to form the base layer100a.

Thereafter, an etch stop layer200and a first lower insulating interlayer202may be formed on the base layer100a.

In some example embodiments, the etch stop layer200may include AIN. The first lower insulating interlayer202may include silicon oxide. A first photoresist pattern204including an opening206opposite to the upper surface of

the preliminary buried vertical rail130may be formed on the first lower insulating interlayer202. The opening206may be vertically aligned with the preliminary buried vertical rail130. For example, the opening206may overlap the preliminary buried vertical rail130in the vertical direction.

In the process of forming the first photoresist pattern204, the preliminary buried vertical rail130may be used as an align key. For example, the first lower insulating interlayer202may have relatively excellent light transmission properties, so that the preliminary buried vertical rail130extending through the base layer100amay serve as an align key.

Referring toFIG.19, the first lower insulating interlayer202and the etch stop layer200may be etched using the first photoresist pattern204as an etching mask to form a first preliminary hole210. A first preliminary barrier pattern124aof the preliminary buried vertical rail130may be exposed by a bottom of the first preliminary hole210.

Referring toFIG.20, the first preliminary barrier pattern124aexposed by the bottom of the first preliminary hole210may be removed to form a first hole210aand the first barrier pattern124b.Accordingly, a buried vertical rail130aincluding a first barrier pattern124band a first metal pattern126amay be formed in the buried vertical rail hole120. The first metal pattern126amay be exposed by a bottom of the first hole210a.

As the first preliminary barrier pattern124aexposed by the bottom of the first preliminary hole210is removed, the bottom of the first hole210amay be positioned lower than an upper surface of the base layer100a.

In some example embodiments, the process of removing the first preliminary barrier pattern124amay include an inductively coupled plasma (ICP) etching process. In an embodiment in which the inductively coupled plasma etching process is performed, an etching rate and an etching direction may be easily controlled. Thus, the first preliminary barrier pattern124aof a desired portion may be removed.

For example, the first preliminary barrier pattern124amay be etched by argon plasma. By applying RF power to the ICP coil, the argon plasma may be generated. Argon ions may be accelerated by an electric field toward the first preliminary barrier pattern124a.The accelerated argon ions may be bombarded to the first preliminary barrier pattern124a,so that the first preliminary barrier pattern124amay be removed. In this embodiment, since the argon ions may be attracted in the vertical direction, the sidewall of the first hole210amay be hardly etched due to a bombardment of the argon ions. Accordingly, the first preliminary barrier pattern124aexposed by the bottom of the first preliminary hole210may be selectively etched.

Referring toFIG.21, a third barrier layer212may be formed along the sidewall and bottom of the first hole210aand an upper surface of the first lower insulating interlayer202,

In an embodiment, the third barrier layer212may be formed of, for example, Ti, Ta, TiN, TaN, or a combination thereof. In some example embodiments, the third barrier layer212. may include the same material as the first barrier pattern124b.In some example embodiments, the third barrier layer212may include a material different from that of the first barrier pattern124b.

Referring toFIG.22, the third barrier layer212formed on the bottom of the first hole210aand the upper surface of the first lower insulating interlayer202may be selectively removed to form the third barrier pattern212a,Accordingly, the first metal pattern126amay be exposed by the bottom of the first hole210a.The third barrier pattern212amay be formed only on the sidewall of the first hole210a.

In an embodiment, the selective removing process may include an inductively coupled plasma etching process. In an embodiment in which the inductively coupled plasma etching process is performed, the etching rate and the etching direction may be easily controlled. Thus, the third barrier layer212of a desired portion may be removed.

In an embodiment in which the inductively coupled plasma etching process is performed, the third barrier layer212formed on the first metal pattern126aon the bottom of the first hole210aand the third barrier layer212formed on the upper surface of the first lower insulating interlayer202may be selectively removed to form the third barrier pattern212a,without forming an etching mask. In addition, in an embodiment in which the inductively coupled plasma etching process is performed, re-sputtering in which an etched third barrier layer212may be re-deposited may hardly occur.

For example, the third barrier layer212may be etched by argon plasma. By applying RF power to the ICP coil, an argon plasma may be generated. Argon ions may be accelerated by the electric field toward the third barrier layer212. The accelerated argon ions may be bombarded to the third barrier layer212, so that the third barrier layer212may be removed. In this embodiment, since the argon ions may be attracted in the vertical direction, the sidewall of the first hole210amay be hardly etched due to a bombardment of the argon ions. Accordingly, the third barrier layer212exposed by the bottom of the first preliminary hole210may be selectively etched to form the third barrier pattern212a.

In some example embodiments, the bottom of the first hole210amay have an area. substantially the same as an area of an exposed surface of the buried vertical rail130a.

In some example embodiments, an area of the bottom of the first hole210amay be greater than an area of the exposed surface of the buried vertical rail130a.In this embodiment, a third barrier layer212contacting the upper surface of the first metal pattern126amay be selectively etched. For example, a portion of the third barrier layer212that is not in direct contact with the first metal pattern126amay remain to form the third barrier pattern212a.

Referring toFIG.23, a third metal layer may be formed on the third barrier pattern212aand the first lower insulating interlayer202to fill the first hole210a.In an embodiment. the third metal layer may include, for example, Cu, W, Mo, Ru, or Nb.

An embodiment in which the third metal layer is formed of copper may be described in more detail for convenience of explanation.

First, a seed layer may be formed on the sidewall and bottom of the first hole210aand the first lower insulating interlayer202. The seed layer may include, for example, copper. copper layer may be formed on the seed layer by an electroplating process. The copper layer may completely fill the first hole210a.

In a comparative embodiment in which a residue generated by the re-sputtering of the third barrier layer may be included in the first hole210abefore forming the third metal layer, the third metal layer may not be normally deposited due to the residue. Therefore, the third metal layer filling the first hole210amay include void.

However, as described above, when the third barrier layer is selectively etched through the inductively coupled plasma etching process, a residue due to re-sputtering of the third barrier layer may hardly be generated in the first hole210a.Therefore, the void in the third metal layer may be decreased.

The third metal layer may be planarized until an upper surface of the first lower insulating interlayer202may be exposed to form a third metal pattern220filling the first hole210a.Accordingly, a first lower contact plug230including the third barrier pattern12aand the third metal pattern220may be formed in the first hole210a.

A bottom surface of the third metal pattern220may directly contact a top surface of the first metal pattern126a.A barrier layer may not be formed between the bottom surface of the third metal pattern220and the top surface of the first metal pattern126a.In some example embodiments, a portion (e.g., interface) between the third metal pattern220and the first metal pattern126ain which the third metal pattern220and the first metal pattern126adirectly contact each other may not be coplanar with the lower surface (e.g., second surface) of the base layer100a.In some example embodiments, the portion (e.g., interface) between the third metal pattern220and the first metal pattern126ain which the third metal pattern220and the first metal pattern126adirectly contact each other may be positioned at an inner portion of the base layer100a.

As such, a barrier layer may not be formed at an interface between the buried vertical rail130aand the first lower contact plug230, and thus the first metal pattern126aand the third metal pattern220may directly contact each other. Accordingly, contact resistance between the buried vertical rail130aand the first lower contact plug230may be decreased.

Referring toFIG.24, a second lower insulating interlayer240and a first lower wiring242may be formed on the first lower insulating interlayer202and the first lower contact plug230. The second lower insulating interlayer240may cover the first lower wiring242.

The first lower wirings242may be formed as multi-layer wirings. The first lower wirings242may include contact plugs and conductive lines. The first lower wirings242may include a metal material. In an embodiment, the first lower wirings242may include, for example, Cu, W, Mo, Ru, or Nb.

The first lower wirings242may be positioned on a back side (e.g., the first surface) of the base layer100a.The first lower wirings242may be applied power to circuit elements formed on the base layer100a.In some example embodiments, the first lower wiring242may include a barrier pattern and a metal pattern.

In example embodiments, a protective layer may be formed on an uppermost insulating interlayer.

The carrier substrate170may be removed.

As described above, the semiconductor device may be manufactured by performing the steps shown inFIGS.6-24.

FIGS.25and26are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with some example embodiments.

Hereinafter, a method of manufacturing a semiconductor device including an MBC field effect transistor is described. Accordingly, a method of manufacturing the semiconductor device is the same as embodiments described with reference toFIGS.6to24, except for some processes for forming a transistor,

Referring toFIG.25, a silicon germanium layer and a silicon layer may be alternately and repeatedly stacked on a substrate100. A mask pattern may be formed on the uppermost silicon layer. The silicon germanium layer, the silicon layer, and the upper portion of the substrate may be etched using the mask pattern as an etch mask to form preliminary active fins101. A first structure in which a silicon germanium pattern90and a silicon pattern92are stacked may be disposed at an upper portion of the preliminary active fin101.

An isolation layer may be formed to cover the preliminary active fins101of the substrate100, and the isolation layer may completely fill a space between the preliminary active fins101. An upper portion of the isolation layer may be partially etched until an upper surface of the first structure in the preliminary active fins101may be exposed to form an isolation pattern104.

Thereafter, the process described with reference toFIGS.7to9may be performed in the same manner. Accordingly, the dummy gate structures may be formed on the preliminary active fins101and the isolation pattern104. Upper portions of the preliminary active fins101adjacent to both sides of the dummy gate structure may be etched to form the recesses. The semiconductor pattern may be formed in the recess.

Referring toFIG.26, a first insulating interlayer may be formed to cover the dummy gate structure and the semiconductor pattern. In an embodiment, the first insulating interlayer may be planarized until an upper portion of the dummy gate structure may be exposed. In an embodiment, the dummy gate structure may be removed to form a first trench.

The silicon germanium patterns exposed by the first trench may be removed to form an active fin101aincluding gaps.

Thereafter, a gate structure112may be formed in the first trench and the gaps. In an embodiment, the gate structure112may include a gate insulation layer112a,a gate electrode112band a capping pattern112c.

A second insulating interlayer114may be formed on the first insulating interlayer110.

An MBC field effect transistor may be formed by the above process.

Thereafter, a semiconductor device may be manufactured by performing the same process as described with reference toFIGS.12to24.