Memory control device and memory control method

A memory device is operative to reset write-in status or read-out status information data in accordance with a reset signal. In response to the reset signal, a memory control device refers to a power-on reset check region in a RAM and determines whether or not the received reset signal is a power-on reset signal that is the reset signal generated firstly after power on. If the reset signal is determined to be the power-on reset signal, a memory check process is executed on respective target pages in each block in the memory. A refresh process is also performed on a block in which the number of error bits detected in the memory check process is more than a threshold value. The memory check process is performed on a different page whenever power is supplied.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a memory control device and a memory control method for performing data access to a memory.

2. Description of the Related Art

In recent years, with an increase in memory capacity, NAND flash memories excellent in a bit unit price are widely used. In the NAND flash memories with increased memory capacity and high integration, problems such as aging degradation of written data and incorrect data read due to concentrated reading operation have become obvious. These problems occur when electric charges that hold data are reduced with a lapse of years and/or when saved data are destroyed by a small amount of charges accumulated in adjacent memory cells through read operation.

To avoid such failures, a process of correcting an error portion of data is performed by adding an error correcting code (ECC), which corrects a data error, to the data, and writing and reading the data together with the ECC. However, the number of bits correctable by using the correcting code is limited. When the number of error bits is more than the correctable limit, error correction is no longer effective. This makes it necessary to detect and correct an error before the number of error bits exceeds the correctable limit. Accordingly, an apparatus has been devised to implement a method for detecting an error before the number of error bits exceeds the correctable limit (for example, Japanese Patent Application Laid-Open No. 2011-128751). In this apparatus, memory check is performed when normal data read is not performed so as to determine whether or not a refresh process is necessary.

In this apparatus, memory check is performed at the time of standby of a memory (at the time of idling) to determine a region that needs a refresh process. However, even if the memory is in a standby state at the time of starting memory check, data read may be requested in the midst of the memory check process thereafter. In such a case, a data read process needs to be performed after the memory check process is completed, which disturbs memory operation, causing such a problem as delayed data read process.

SUMMARY OF THE INVENTION

The present invention has been devised to solve the above problems, and an object of the present invention is to provide a memory control device and a memory control method capable of performing an error check process and a refresh process of a memory without disturbing memory operation.

A memory control device according to the present invention is a memory control device that controls either write-in or read-out operation for a memory, including: an interface unit connected to the memory for performing either write-in or read-out operation for the memory; a power-on reset signal generation unit for generating a power-on reset signal in response to power on; an internal reset signal generation unit for generating an internal reset signal in response to a reset request; an initializing signal supply unit for delivering the power-on reset signal or the internal reset signal as an initializing signal that initializes write-in status or read-out status information data held by the interface unit to the interface unit; and a control unit for determining whether or not the initializing signal is based on the power-on reset signal after the write-in status or read-out status information data in the interface unit is initialized in response to the initializing signal, and for performing a check process on the memory if the initializing signal is determined to be based on the power-on reset signal.

A memory control method according to the present invention is a memory control method for controlling either write-in or read-out operation for a memory, including the steps of: generating a power-on reset signal in response to power on; generating an internal reset signal in response to a reset request; delivering the power-on reset signal or the internal reset signal as an initializing signal; and determining whether or not the initializing signal is based on the power-on reset signal and performing a check process on the memory only when the initializing signal is determined to be based on the power-on reset signal.

In the present invention, when a reset signal is received, it is determined whether or not the reset signal is a power-on reset signal. Only when the power-on reset signal is received, the memory check process and the refresh process are performed.

As a consequence, when a flash memory is accessed after power is supplied, the apparatus is free from a standby state for the memory check process and the refresh process, so that a rapid access to the flash memory can be performed constantly. Therefore, according to the present invention, the error check process and the refresh process of the memory can be performed without disturbing memory operation.

DETAILED DESCRIPTION OF THE INVENTION

Hereinbelow, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First Embodiment

FIG. 1is a block diagram illustrating the configuration of an information processing apparatus10including a memory control device according to the present invention. As illustrated inFIG. 1, the information processing apparatus10includes a central processing unit (CPU)11, an interface unit12, a random access memory (RAM)13, a flash memory14, a CPU bus15, a power-on reset generation unit16, an OR gate17, and an internal reset generation unit18.

The CPU11is connected to the interface unit12, the RAM13, and the internal reset generation unit18through the CPU bus15. The CPU11performs data read and write access to the flash memory14through the CPU bus15and the interface unit12.

The CPU11is a control unit for reading program data stored in the flash memory14, which is a main program for implementing a main function of the information processing apparatus10, through the interface unit12, and for executing main control in accordance with the main program. The CPU11further reads memory check program data stored in the flash memory14through the interface unit12, and executes memory check process in accordance with the memory check program data. The memory check process is to check whether or not the data stored in the flash memory14can correctly be read. The details of the memory check process will be described later.

The interface unit12includes an error detection/correction unit20, a status register21, and a memory check region specification register22. The error detection/correction unit20detects an error included in a page to be checked (hereinafter referred to as an offset page) in a later-described memory check process target block. The error detection/correction unit20corrects an error in a specified block. The status register21holds information, including the number of error bits detected by the error detection/correction unit20. The memory check region specification register22holds information indicative of a memory region specified as a target of the memory check process. The interface unit12has control information such as write-in status or read-out status information data to the flash memory14. Such control information held by the interface unit12is reset (initialized) in response to a reset signal R.

The RAM13includes a power-on reset check region30as a storage unit. For example, a one-byte value “Ox5A” (power-on-reset code) is written to the power-on reset check region30by the CPU11as information indicative of the reception of a power-on reset signal PR that is the power-on reset signal after power is supplied to the information processing apparatus10. Once the value “Ox5A” is written, the power-on reset check region30holds the value “Ox5A” until the information processing apparatus10is turned off. The page/block information31is stored in the RAM13. As illustrated inFIG. 2A, the page/block information31includes memory check target offset page information301, priority memory check target block information302, refresh target block information303, memory check target block information304, and priority memory check target offset page information305.

As illustrated inFIG. 3A, the flash memory14is divided into access regions of L blocks1to L (L is a natural number), with one block including K pages1to K (K is a natural number). The flash memory14has a region for storing management information40. As illustrated inFIG. 2B, the management information40includes check target offset page information401, priority memory check target block information402, and refresh target block information403.

The power-on reset generation unit16generates a one-pulse reset signal PR (power-on reset signal) when power is supplied to the information processing apparatus10, and supplies the signal to the OR gate17. The internal reset generation unit18generates a one-pulse reset signal (internal reset signal) in response to a reset request command issued at the time of execution of main control or a timeout error by a program timer (not illustrated), and supplies the signal to the OR gate17. When the reset signal PR is supplied from the power-on reset generation unit16, the OR gate17supplies the signal as a reset signal R (initializing signal) to the CPU11and the interface unit12. When the reset signal IR is supplied from the internal reset generation unit18, the OR gate17supplies the signal as a reset signal R to the CPU11and the interface unit12.

The CPU11executes the above-stated memory check process in accordance with the memory check routine illustrated inFIG. 4in response to the reset signal R.

First, the CPU11determines whether or not a value held in the power-on reset check region30of the RAM13is “Ox5A” (step S1). If it is determined in step S1that the value held in the power-on reset check region30is “Ox5A,” the CPU11determines that the received reset signal R is not based on the power-on reset signal PR, and ends the memory check routine. If it is determined that the value “Ox5A” is not held in the power-on reset check region30in step S1, the CPU11determines that the received reset signal R is based on the power-on reset signal PR, and writes “Ox5A” to the power-on reset check region30in the RAM13(step S2).

Next, the CPU11reads the management information40illustrated inFIG. 2Bfrom the flash memory14through the interface unit12, and writes the information to the RAM13as the page/block information31(step S3). As a consequence, the check target offset page information401in the management information40is stored in the RAM13as the memory check target offset page information301. The priority memory check target block information402in the management information40is also stored in the RAM13as the priority memory check target block information302. Furthermore, the refresh target block information403is stored in the RAM13as the refresh target block information303.

The CPU11determines whether or not a target block (for example, a block1) in the flash memory14is a priority memory check target block, on the basis of the priority memory check target block information302stored in the RAM13(step S4). The determination in step S4is performed on all the blocks from the block1to block L through a later-described update process of memory check target block and offset page information.

If the target block is the priority memory check target block as a result of determination in step S4, the CPU11sets the block in the memory check region specification register22of the interface unit12as a priority memory check target region (step S5). After execution of step S5, the CPU11shifts to execution of an update process of a priority memory check target offset page (step S6).

FIG. 5is a flow illustrating a routine of the update process of the priority memory check target offset page. InFIG. 5, the CPU11first increments the number indicated in the priority memory check target offset page information305stored in the RAM13by 1, and overwrites the incremented number in the priority memory check target offset page information305in the RAM13as a number representative of new priority memory check target offset page information (step S21). For example, when a page number “N” is stored, a page number “N+1” that is an increment of N by 1 is overwritten as a new page number. An initial value of the priority memory check target offset page is 1, which represents a first page. Next, the CPU11determines whether or not the incremented page number exceeds a last page number K (step S22). If it is determined that the page number exceeds the last page number K in step S22, i.e., when all the priority memory check processes within the priority memory check target block are finished, the priority memory check target offset page information305in the RAM13is cleared and initialized (step S23). After execution of step S23, the CPU11shifts to execution of the memory check target block and offset page update process (step S24).

FIG. 6is a flow chart illustrating a routine of the memory check target block and offset page update process. The CPU11increments the number indicated by the memory check target block information304stored in the RAM13by 1, and overwrites the incremented number in the RAM13as a number representative of a new memory check target block (step S31). Next, the CPU11determines whether or not the incremented block number exceeds a final block number L (step S32). If it is determined in step32that the block number exceeds the final block number L, i.e., if a series of normal memory check processes are completed in the memory check target blocks, the CPU11rewrites the block number of the memory check target block information304stored in the RAM13to an initial number 0 (step S33). Next, the CPU11increments the number indicated by the memory check target offset page information301by 1 and overwrites the incremented number as a number representative of a new memory check target offset page in the RAM13(step S34). Then, the CPU11determines whether or not the incremented page number exceeds a last page number K (step S35). If it is determined that the page number exceeds the last page number K in step S35, i.e., if the normal memory check process is completed in all the pages in the memory check target block, the CPU11rewrites the page number of the memory check target offset page information301stored in the RAM13to an initial number 0 (step S36).

If it is determined that the block number does not exceeds the final block number L after execution of step S36or in step S32, or if it is determined that the page number does not exceed the last page number K in step S35, the CPU11gets out of the memory check target block and offset page update routine illustrated inFIG. 6and shifts to execution of step S9.

If it is determined that the target block is not a priority memory check target block in step S4illustrated inFIG. 4, the CPU11sets the block in the memory check region specification register22of the interface unit12as a normal memory check target region (step S7). After execution of step S7, the CPU11shifts to execution of the update process of memory check target block and offset page information (step S8).

After execution of the update process of priority memory check target offset page information (step S6) illustrated inFIG. 4, or the update process of memory check target block and offset page information (step S8), the CPU11executes a process of checking memory read from a specified memory region (step S9).

In the memory read checking process, the CPU11specifies an address in the flash memory14, and supplies a read command signal to the interface unit12. In response to the read command signal, the interface unit12reads an encoded data piece stored in the page corresponding to the specified address from the flash memory14. The error detection/correction unit20in the interface unit12executes an error detection process on the encoded data piece, and generates error information indicative of the number of error bits. The CPU11stores in the status register21of the interface unit12the error information in association with the number of the block in the flash memory14, in which the error-detected encoded data piece is held.

In the normal memory check process, error detection is performed while the block number is incremented. Accordingly, as illustrated inFIG. 3B, memory check is performed on the same pages of all the blocks in the order of, for example, a page N in the block1, a page N in the block2, and a page N in the block3. . . . When memory check is performed up to the final block, the offset page is incremented. Therefore, whenever power is supplied, the memory check process is performed on a different page.

Contrary to this, in the priority memory check process, a priority memory check target block is checked while the number of pages in that block is incremented. Hence, as illustrated inFIG. 3C, memory check is performed on all the pages in a block M, for example.

The CPU11executes an error occurrence confirmation process as illustrated inFIG. 7during the process of checking memory read from the specified memory region in step S9.

As illustrated inFIG. 7, the CPU11determines whether or not an error is present, i.e., whether or not the number of error bits is one or more, on the basis of the error information stored in the status register21(step S41). If it is determined that the error is not present, the CPU11ends the error occurrence confirmation process.

If it is determined that the error is present in step S41, the CPU11determines whether or not the number of error bits is larger than a first threshold value TE1, on the basis of the error information stored in the status register21(step S42). If it is determined that the number of error bits is larger than the first threshold value TE1, the CPU11adds the number of the pertinent block to the priority memory check target block information302in the RAM13(step S43). Then, the CPU11determines whether or not the number of error bits is larger than a second threshold value TE2(TE2>TE1) (step S44). If it is determined that the number of error bits is larger than the second threshold value TE2, the CPU11adds the number of the pertinent block to the refresh target block information303in the RAM13(step S45).

After execution of step S45, or if it is determined that the number of error bits is less than the second threshold value TE2in step S44, the CPU11ends the error occurrence confirmation routine.

After execution of the process of checking memory read from the specified memory region (step S9) including the error occurrence confirmation routine, the CPU11determines whether or not the memory read check is completed in all the blocks (step10). If it is determined that the check is completed, the CPU11shifts to execution of the refresh process (step S11). If it is determined that the check is not completed, the CPU11returns to step S4and re-executes the process of steps S4to S9.

FIG. 8is a flow chart illustrating the refresh process routine.

The CPU11determines whether or not a refresh target block is present, on the basis of the refresh target block information303in the RAM13(step S51). When it is determined that the refresh target block is not present, the CPU11ends the refresh process.

If it is determined that the refresh target block is present, the CPU11sends out an execution command of the refresh process to the interface unit12(step S52).

In the refresh process, the interface unit12first reads an encoded data piece from the refresh process target block. The error detection/correction unit20of the interface unit12performs an error correction process on the encoded data piece. The interface unit12writes the encoded data piece of one block, on which the error correction process has been performed, to a block different from the block where the original encoded data piece was held.

The CPU11deletes the number of the block, on which the refresh process has been performed, from the refresh target block information303in the RAM13(step S53). The CPU11also deletes the number of the same block from the priority memory check target block information302in the RAM13(step S54).

As described in the foregoing, when a reset signal R is received in the above-stated memory check process, it is first determined whether or not the reset signal R is based on the power-on reset signal PR, on the basis of the value held in the power-on reset check region30of the RAM13. In this case, only when the reset signal R based on the power-on reset signal is received, the memory check process and the refresh process are performed. That is, if the reset signal R based on an internal reset signal IR is received, the memory check process and the refresh process are not performed. As a result, a standby state for execution of the memory check process and the refresh process during access to the flash memory14is no longer present except in the case of immediately after power is supplied to the information processing apparatus10. Therefore, a rapid access to the flash memory14can be performed constantly. Furthermore, since the memory check process and the refresh process are performed only immediately after power is supplied to the information processing apparatus10, it becomes possible to prevent the memory from being deteriorated by frequent execution of these processes.

In the above-stated memory check process, memory check is performed only on one page in each of the blocks whenever power is supplied as illustrated inFIG. 3Bfor example. That is, when each block is constituted of K pages as illustrated inFIG. 3A, a series of memory check processes of all the pages of each block is completed when power is supplied K times. This makes it possible to reduce the starting time needed to enable normal access to the flash memory14after power is supplied, as compared with the case of performing memory check on all the pages in all the blocks after power on.

Second Embodiment

The configuration of respective units of an information processing apparatus according to a second embodiment is similar to that of the information processing apparatus10of the first embodiment. The information stored as page/block information31and the information stored as management information40are different from those in the information processing apparatus10of the first embodiment. Hereinafter, a description will mainly be given of the components and operations different from those in the first embodiment.

As illustrated inFIG. 9A, the page/block information31stored in the RAM13includes the information301to305, as well as information on the number of memory check performing pages306, information on the number of priority memory check processing blocks307, and information on the number of refresh processing blocks308.

As illustrated inFIG. 9B, the management information40stored in the flash memory14includes the information401to403, as well as information on the number of memory check performing pages404, information on the number of priority memory check processing blocks405, and information on the number of refresh processing blocks406.

In step S3of the memory check routine illustrated inFIG. 4, the CPU11reads the management information40from the flash memory14, and writes the information to the RAM13as the page/block information31. As a consequence, the information on the number of memory check performing pages404is stored in the RAM13as the information on the number of memory check performing pages306. The information on the number of priority memory check processing blocks405is also stored in the RAM13as the information on the number of priority memory check processing blocks307. Furthermore, the information on the number of refresh processing blocks406is stored in the RAM13as the information on the number of refresh processing blocks308.

The information on the number of memory check performing pages306and404is information indicative of the number of pages in each block on which memory check is performed in one power on operation. On the basis of on the information on the number of memory check performing pages306in the RAM13, the CPU11specifies addresses corresponding to the number of pages in each block in the flash memory14, on which memory check is performed, and supplies a read command signal to the interface unit12. In response to the read command signal, the interface unit12executes error detection process on encoded data pieces stored in the pages corresponding to the specified addresses.

The information on the number of priority memory check processing blocks307and405indicates a maximum number of blocks on which a priority memory check process is performed in one power on operation, when a plurality of blocks are stored as a priority memory check target block in the priority memory check target block information302and402. On the basis of the information on the number of priority memory check processing blocks307in the RAM13, the CPU11specifies addresses corresponding to the number of blocks within the range of the number of priority memory check target blocks, and supplies a read command signal to the interface unit12. In response to the read command signal, the interface unit12executes an error detection process on the encoded data pieces stored in the blocks corresponding to the specified addresses.

The information on the number of refresh processing blocks308and406indicates a maximum number of blocks on which an error correction process is performed in one power on operation, if a plurality of blocks are stored as a refresh target block in the refresh target block information303and403. On the basis of the information on the number of refresh processing blocks308in the RAM13, the CPU11specifies addresses corresponding to the number of blocks within the range of the number of refresh processing blocks in the flash memory14, and supplies a read command signal to the interface unit12. In response to the read command signal, the interface unit12executes a refresh process on the encoded data pieces stored in the blocks corresponding to the specified addresses.

In the memory check process according to the above-stated second embodiment, the memory check is performed on the number of pages in each block, the number of pages being stored as the information on the number of memory check performing pages. Accordingly, when a value “2” is stored as the number of memory check performing pages, the memory check process is performed on two pages in each block whenever power is supplied to the information processing apparatus10.

In the priority memory check process according to the second embodiment, the priority memory check is performed on the priority memory check target blocks, with the number of blocks stored as the information on the number of priority memory check processing blocks as a maximum block number. Accordingly, in the case where, for example, a value “5” is stored as the number of priority memory check processing blocks and seven blocks are stored as the priority memory check target blocks, the priority memory check is performed on five blocks in one power on operation, and the priority memory check for the remaining two blocks is performed in the next power on operation of the information processing apparatus10.

In the refresh process according to the second embodiment, the refresh process is performed on refresh target blocks, with the number of blocks stored as the information on the number of refresh processing blocks as a maximum block number. Accordingly, in the case where, for example, a value “3” is stored as the number of refresh processing blocks and four blocks are stored as the refresh target blocks, the refresh process is performed on three blocks in one power on operation, and the refresh process for remaining one block is performed in the next power on operation of the information processing apparatus10.

According to the information processing apparatus in the second embodiment, the number of memory check performing pages, the number of priority memory check processing blocks, and the number of refresh processing blocks are stored in advance in the flash memory. This makes it possible to control the range of the memory region targeted to the memory check process and the refresh process and to thereby facilitate adjustment of the time taken for the process in one power on operation.

As described in the foregoing, according to the present invention, the memory check process and the refresh process are performed only when a power-on reset signal is received. Accordingly, except for immediately after power is supplied to the information processing apparatus10, the apparatus is free from the standby state for the memory check process and the refresh process. Therefore, a rapid access to the flash memory can be performed constantly.

According to the present invention, memory check is performed on a specified number of pages of each block whenever power is supplied to the information processing apparatus10. This makes it possible to reduce the time needed to enable access to the flash memory after power is supplied, as compared with the case of performing memory check on all the pages in all the blocks after power on.

In the above embodiment, a one-byte value “Ox5A” is written to the power-on reset check region30upon reception of the reset signal R that is based on the power-on reset signal PR. Whether the received reset signal R is based on the power-on reset signal PR or not is determined on the basis of whether or not the power-on reset check region30holds the value “Ox5A.” However, whether the received reset signal R is based on the power-on reset signal PR or not may be determined on the basis of whether or not a specified value is written to the power-on reset check region30, and the specified value is not limited to the value “Ox5A.” To prevent erroneous recognition, whether the received reset signal R is based on the power-on reset signal PR or not may be determined by writing not a one-byte value but a value of several bytes, for example.

In the above embodiment, the flash memory14stores the management information40. However, a nonvolatile memory or the like, which is connected with the interface unit12, may be provided separately from the flash memory, and the nonvolatile memory or the like may store the management information40.

In the above embodiment, the memory check process has been described as a process for checking whether or not the data stored in the flash memory14is correctly read. In addition to this process, a process for checking whether or not the data can be written correctly may also be performed.

In the above embodiment, the memory check process is performed on one page or a specified number of memory check performing pages in all the blocks, whenever power is supplied to the information processing apparatus10. However, it is also possible to store information, such as information on the number of memory check performing blocks that indicates the number of blocks on which the memory check is performed in one power on operation, and memory check progress information that indicates to which block the memory check has progressed, as the management information40. With such information, the memory check process for all the blocks may be divided and performed in plural times. Such a configuration makes it possible to further reduce the time needed to enable access to the flash memory after power is supplied, as compared with the case where the memory check is performed on all the blocks.