Semiconductor package

A semiconductor package includes: an interposer substrate including a core substrate and a connection structure, the core substrate having a cavity and having through-vias connecting upper and lower surfaces thereof, and the connection structure including an insulating member on the upper surface and a redistribution layer on the insulating member; a semiconductor chip on an upper surface of the connection structure and including connection pads connected to the redistribution layer; a passive component accommodated in the cavity; a first insulating layer disposed between the core substrate and the connection structure; a first wiring layer on the first insulating layer and connecting the through-vias and the passive component to the redistribution layer; a second insulating layer on the lower surface of the core substrate; and a second wiring layer on a lower surface of the second insulating layer and connected to the through-vias.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims benefit of priority to Korean Patent Application No. 10-2019-0024733 filed on Mar. 4, 2019 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to a hybrid interposer and a semiconductor package including the same.

BACKGROUND

In accordance with improvement of specifications of a set and use of a high bandwidth memory (HBM), an interposer market has grown. Currently, silicon has been mainly used as a material of the interposer, but development of a glass or organic formation process has been conducted in order to increase an area and reduce a cost.

In a high performance semiconductor package, a passive component such as a capacitor needs to be disposed in a region adjacent to a semiconductor chip in order to improve power noise and a power integrity due to generation of a parasitic inductance.

SUMMARY

An aspect of the present disclosure may provide a hybrid interposer in which a passive component may be embedded, and a semiconductor package including the same.

According to an aspect of the present disclosure, a semiconductor package may include: an interposer substrate including a core substrate and a connection structure, the core substrate having at least one cavity and having through-vias connecting upper and lower surfaces thereof to each other, and the connection structure including an insulating member disposed on the upper surface of the core substrate and a redistribution layer disposed on the insulating member; at least one semiconductor chip disposed on an upper surface of the connection structure of the interposer substrate and including connection pads connected to the redistribution layer; a passive component accommodated in the at least one cavity; a first insulating layer disposed between the core substrate and the connection structure and encapsulating the passive component in the at least one cavity; a first wiring layer disposed on the first insulating layer and connecting the through-vias and the passive component to the redistribution layer; a second insulating layer disposed on the lower surface of the core substrate; and a second wiring layer disposed on a lower surface of the second insulating layer and connected to the through-vias.

According to another aspect of the present disclosure, a hybrid interposer may include: a core substrate having at least one cavity and having through-vias connecting upper and lower surfaces thereof to each other; a passive component accommodated in the at least one cavity; a first insulating layer disposed on the upper surface of the core substrate and encapsulating the passive component in the at least one cavity; a first wiring layer disposed on the first insulating layer and connected to the through-vias and the passive component; a second insulating layer disposed on the lower surface of the core substrate; a second wiring layer disposed on a lower surface of the second insulating layer and connected to the through-vias; and a connection structure including an insulating member disposed on the upper surface of the core substrate and a redistribution layer disposed on the insulating member and connected to the first wiring layer.

According to another aspect of the present disclosure, a semiconductor package may include: an interposer substrate including a core substrate and a connection structure, the core substrate having cavities in which passive components are embedded and having through-vias connecting upper and lower surfaces of the core substrate to each other, and the connection structure including an insulating member disposed on the upper surface of the core substrate and a redistribution layer disposed on the insulating member; semiconductor chips disposed on an upper surface of the connection structure and including connection pads connected to the redistribution layer; a first insulating layer disposed between the core substrate and the connection structure and encapsulating the passive component in the at least one cavity; a first wiring layer disposed on the first insulating layer and connecting the through-vias and the passive component to the redistribution layer; a second insulating layer disposed on the lower surface of the core substrate; and a second wiring layer disposed on a lower surface of the second insulating layer and connected to the through-vias. One of the cavities may overlap with two or more of the semiconductor chips adjacent to each other, in a plan view.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, shapes, sizes, and the like, of components may be exaggerated or shortened for clarity.

Herein, a lower side, a lower portion, a lower surface, and the like, are used to refer to a downward direction in relation to cross sections of the drawings for convenience, while an upper side, an upper portion, an upper surface, and the like, are used to refer to an opposite direction to the downward direction. However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the directions defined as described above, and concepts of upper and lower portions may be exchanged with each other.

The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with one another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure. In this case, singular forms include plural forms unless interpreted otherwise in context.

Electronic Device

Referring toFIG. 1, an electronic device1000may accommodate a mainboard1010therein. The mainboard1010may include chip related components1020, network related components1030, other components1040, and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal lines1090.

FIG. 2is a schematic perspective view illustrating an example of an electronic device.

Referring toFIG. 2, a semiconductor device may be used for various purposes in the various electronic devices1000as described above. For example, a motherboard1110may be accommodated in a body1101of a smartphone1100, and various electronic components1120may be physically or electrically connected to the motherboard1110. In addition, other components that may or may not be physically or electrically connected to the motherboard1110, such as a camera module1130, may be accommodated in the body1101. Some of the electronic components1120may be chip related components, and some of the chip related components may be a semiconductor device1121. Meanwhile, the electronic device is not necessarily limited to the smartphone1100, but may be other electronic devices.

Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a semiconductor finished product in oneself, and may be damaged due to external physical or chemical impact. Therefore, the semiconductor chip is not used in oneself, and is packaged and is used in an electronic device, or the like, in a package state.

The reason why semiconductor packaging is required is that there is a difference in a circuit width between the semiconductor chip and a mainboard of the electronic device in terms of electrical connection. In detail, a size of connection pads of the semiconductor chip and an interval between the connection pads of the semiconductor chip are very fine, but a size of component mounting pads of the mainboard used in the electronic device and an interval between the component mounting pads of the mainboard are significantly larger than those of the semiconductor chip.

Therefore, it may be difficult to directly mount the semiconductor chip on the mainboard, and packaging technology for buffering a difference in a circuit width between the semiconductor and the mainboard is required.

A semiconductor device manufactured by the packaging technology described above will hereinafter be described in more detail with reference to the drawings.

FIG. 3is a schematic cross-sectional view illustrating a case in which a three-dimensional (3D) ball grid array (BGA) package is mounted on a main board of an electronic device.

An application specific integrated circuit (ASIC) such as a graphics processing unit (GPU) among semiconductor chips is very expensive, and it is thus very important to perform packaging on the ASIC at a high yield. For this purpose, a ball grid array (BGA) substrate2210, or the like, that may redistribute several thousands to several hundreds of thousands of connection pads is prepared before a semiconductor chip is mounted, and the semiconductor chip that is expensive, such as a GPU2220, or the like, is mounted and packaged on the BGA substrate2210by surface mounting technology (SMT), or the like, and is then mounted ultimately on a main board2110.

Meanwhile, in a case of the GPU2220, it is required to significantly reduce a signal path between the GPU2220and a memory such as a high bandwidth memory (HBM). To this end, a product in which a semiconductor chip such as the HBM2240is mounted and then packaged on an interposer2230, and is then stacked on a package in which the GPU2220is mounted, in a package-on-package (POP) form is used. However, in this case, a thickness of a device is excessive increased, and there is a limitation in significantly reducing the signal path.

FIG. 4is a schematic cross-sectional view illustrating a case in which a 2.5D silicon interposer package is mounted on a main board.

As a method for solving the problem described above, it may be considered to manufacture a semiconductor device2310by 2.5 D interposer technology of surface-mounting and then packaging a first semiconductor chip such as a GPU2220and a second semiconductor chip such as an HBM2240side-by-side with each other on a silicon interposer2250. In this case, the GPU2220and the HBM2240having several thousands to several hundreds of thousands of connection pads may be redistributed by the silicon interposer2250, and may be electrically connected to each other at the shortest path. In addition, when the semiconductor device2310is again mounted and redistributed on a BGA substrate2210, or the like, the semiconductor device2310may be ultimately mounted on a main board2110. However, it is very difficult to form through-silicon vias (TSVs) in the silicon interposer2250, and a cost required for manufacturing the silicon interposer2250is significantly high, and the silicon interposer2250is thus disadvantageous in increasing an area and reducing a cost.

FIG. 5is a schematic cross-sectional view illustrating a case in which a 2.5D organic interposer package is mounted on a main board.

As a method for solving the problem described above, it may be considered to use an organic interposer2260instead of the silicon interposer2250. For example, it may be considered to manufacture a semiconductor device2320by 2.5D interposer technology of surface-mounting and then packaging a first semiconductor chip such as a GPU2220and a second semiconductor chip such as an HBM2240side-by-side with each other on the organic interposer2260. In this case, the GPU2220and the HBM2240having several thousands to several hundreds of thousands of connection pads may be redistributed by the organic interposer2260, and may be electrically connected to each other at the shortest path. In addition, when the semiconductor device2320is again mounted and redistributed on a BGA substrate2210, or the like, the semiconductor device2320may be ultimately mounted on a main board2110. In addition, the organic interposer may be advantageous in increasing an area and reducing a cost.

Meanwhile, such a semiconductor device2320is manufactured by performing a package process of mounting chips2220and2240on the organic interposer2260and then molding the chips. The reason is that when a molding process is not performed, the semiconductor device is not handled, such that the semiconductor device may not be connected to the BGA substrate2210, or the like. Therefore, rigidity of the semiconductor device is maintained by the molding. However, when the molding process is performed, warpage of the semiconductor device may occur, fillability of an underfill resin may be deteriorated, and a crack between a die and a molding material of the chips2220and2240may occur, due to mismatch between coefficients of thermal expansion (CTEs) of the interposer2260and the molding material of the chips2220and2240, as described above.

Various exemplary embodiments in the present disclosure will hereinafter be described in detail with reference to the accompanying drawings.

FIG. 6is a schematic cross-sectional view illustrating a semiconductor package according to an exemplary embodiment in the present disclosure, andFIG. 7is a plan view illustrating the semiconductor package illustrated inFIG. 6.

Referring toFIGS. 6 and 7, a semiconductor package300according to the present exemplary embodiment may include an interposer substrate100and a plurality of semiconductor chips310A,310B, and310C disposed on the interposer substrate100. The interposer substrate100used in the present exemplary embodiment may be a hybrid interposer in which a core substrate110and a connection structure130are coupled to each other.

The core substrate110may have first and second cavities110Ha and110Hb and include through-vias123connecting upper and lower surfaces of the core substrate110to each other, and a plurality of passive components125may be accommodated in the first and second cavities110Ha and110Hb. First and second insulating layers121and122may be disposed on the upper and lower surfaces of the core substrate110, respectively.

The core substrate110may provide a space for accommodating the plurality of passive components125, and serve to increase rigidity of the interposer substrate100. The core substrate110may include an organic insulating material, for example, a thermosetting resin such as an epoxy resin or a thermoplastic resin such as polyimide. In some exemplary embodiments, the core substrate110may be formed of a mixture of the insulating material, which is a main material, and other inorganic components. For example, the core substrate110may include a resin mixed with an inorganic filler or a resin in which a glass fiber is impregnated together with an inorganic filler. In a specific example, the core substrate may be formed of Ajinomoto Build-up Film (ABF) or prepreg.

The first insulating layer121may be disposed between the core substrate110and the connection structure130, and may be filled in at least portions of the first and second cavities110Ha and110Hb to encapsulate the plurality of passive components125. The through-vias123and a first wiring layer115aconnected to each of the plurality of passive components125may be disposed in and on the first insulating layer121. In detail, the first wiring layer115amay include a first wiring pattern112adisposed on an upper surface of the first insulating layer121and connected to the through-vias123and connection vias113apenetrating through the first insulating layer121and connected to electrodes of the plurality of passive components125.

The second insulating layer122may be disposed on the lower surface of the core substrate110, and a second wiring layer115bconnected to the through-vias123may be disposed on a lower surface of the second insulating layer122. The electrodes of the plurality of passive components125may be connected to the connection vias113aof the first wiring layer115a. The plurality of passive components125may include, for example, a high frequency inductor, a ferrite inductor, a power inductor, ferrite beads, a low temperature co-firing ceramic (LTCC), an electromagnetic interference (EMI) filter, a multilayer ceramic capacitor (MLCC), or the like. However, the plurality of passive components125are not limited thereto, but may also include passive components used for various other purposes, or the like.

The plurality of passive components125may have different sizes and thicknesses. The first and second cavities110Ha and110Hb may have the size that is the same as or greater than that of a passive component having the greatest thickness. The first cavity110Ha may overlap with two or more of semiconductor chips including the first semiconductor chips310A and the second semiconductor chip310B adjacent to each other, in a plan view. The second cavity110Hb may overlap with two or more of semiconductor chips including the second semiconductor chip310B and the third semiconductor chips310C adjacent to each other, in the plan view. As such, electrical paths from respective semiconductor chips passing through respective passive components in a respective cavity to respective second electrical connection metals may be shortened. The plurality of passive components125may be disposed on the same level on one reference surface. In the present exemplary embodiment, one surfaces of the plurality of passive components125may be arranged in parallel with one another on an upper surface of the second insulating layer122, which is the reference surface. For example, lower surfaces of the plurality of passive components125, a lower surface of the core substrate110, and the upper surface of the second insulating layer122may be coplanar with or substantially coplanar with each other.

The connection structure130may include an insulating member131disposed on the upper surface of the core substrate110and redistribution layers135formed on the insulating member131.

A case in which the redistribution layers135used in the present exemplary embodiment have a three-level structure is exemplified. In detail, the insulating member131may include three insulating layers, and may include, for example, a photoimagable dielectric (PID). The redistribution layer135may be formed in a fine pattern by a photolithography process by using the PID.

The redistribution layers135may include three-level redistribution patterns132disposed on the three insulating layers131and redistribution vias133penetrating through the insulating layers131and connected to the redistribution pattern132. The lowermost redistribution layer135may be connected to the first wiring layer115adisposed on the core substrate110, and the uppermost redistribution layer135, particularly, the redistribution pattern132may be provided as connection lands132P. The connection lands132P may be connected to connection pads310P of the first to third semiconductor chips310A,310B, and310C by first electrical connection metals360. The connection lands132P may include a surface treatment layer. The surface treatment layer may be formed by, for example, electrolytic gold plating, electroless gold plating, organic solderability preservative (OSP) or electroless tin plating, electroless silver plating, electroless nickel plating/substituted gold plating, direct immersion gold (DIG) plating, hot air solder leveling (HASL), or the like, but is not limited thereto.

As described above, the interposer100according to the present exemplary embodiment may be configured by coupling the core substrate110for mounting the passive components125and the connection structure130implemented in a fine pattern on the core substrate110to each other. Therefore, an entire thickness of the interposer100may be relatively small, the passive components125may be disposed adjacent to the first to third semiconductor chips310A,310B, and310C, and the core substrate110may be used as a carrier in a process of manufacturing the interposer100.

The respective components included in the semiconductor package300according to the present exemplary embodiment will hereinafter be described in more detail.

Each of the first to third semiconductor chips310A,310B, and310C may be an integrated circuit (IC) provided in an amount of several hundreds to several millions of elements or more integrated in a single chip. In this case, a base material of a body of each of the semiconductor chips may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on each of the bodies.

The respective connection pads310P of the first to third semiconductor chips310A,310B, and310C may electrically connect the first to third semiconductor chips310A,310B, and310C to another component (for example, the interposer100), and a material of each of the connection pads310P may be any conductive material such as aluminum (Al), or the like. Passivation layers exposing the connection pads310P may be formed on the respective bodies, and may be oxide layers, nitride layers, or the like, or double layers of an oxide layer and a nitride layer. Insulating layers, and the like, may further be disposed in required positions. In some exemplary embodiment, separate redistribution layers may further be formed on active surfaces of the first to third semiconductor chips310A,310B, and310C, and the first electrical connection metals360may connect the connection pads310P to the connection lands132P and include a low melting point metal such as a solder. The first to third semiconductor chips310A,310B, and310C may be fixed onto the interposer100by an underfill resin330.

For example, a second semiconductor chip310B may be an ASIC such as a GPU. First and third semiconductor chips310A and310C may be memories such as HBMs. That is, each of the first to third semiconductor chips310A,310B, and310C may be an expensive chip having several hundreds of thousands or more of inputs/outputs (I/Os), but is not limited thereto. For example, the first and third semiconductor chips310A and310C, which are the HBMs, or the like, may be disposed side-by-side with the second semiconductor chip310B, which is the ASIC such as the GPU, or the like, at both sides of the second semiconductor chip310B, respectively.

The connection structure130of the interposer100may redistribute the respective connection pads310P of the first to third semiconductor chips310A,310B, and310C. Several tens to several hundreds of connection pads310P of each of the semiconductor chips310A,310B, and310C having various functions may be redistributed by the interposer100, and may be physically and/or electrically externally connected through second electrical connection metals260depending on functions. The connection structure130may include a plurality of insulating layers131and redistribution layers135disposed on the plurality of insulating layers131, as described above. A case in which the number of levels of the connection structure130is three is exemplified, but the number of levels of the connection structure130may be one or plural.

The redistribution layers135may serve to substantially redistribute the connection pads310P. A material of each of the redistribution layers135may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers135may perform various functions depending on designs of corresponding layers. For example, the redistribution layers135may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals except for the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the redistribution layers135may include via pads and connection lands.

A material of each of the first and second insulating layers121and122may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin and the thermoplastic resin are mixed with an inorganic filler, for example, ABF, or the like. The first and second wiring layers115aand115band the through-vias123may provide a wiring structure connecting the redistribution layer135of the connection structure130and the second electrical connection metals260to each other. In addition, the first wiring layer115amay be connected to the plurality of passive components125to electrically connect the first to third semiconductor chips310A,310B, and310C to other circuit layers. For example, a material of each of the first and second wiring layers115aand115band the through-vias123may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.

First and second passivation layers210and220may protect the interposer100from external physical or chemical damage. In detail, the first passivation layer210may be disposed on an upper surface of the connection structure130to protect the connection structure130and the redistribution layer135, and the second passivation layer220may be disposed on the lower surface of the core substrate110. The first and second passivation layers210and220may include, respectively, the connection lands132P and openings opening portions of the second wiring layer115b. For example, the first and second passivation layers210and220may be formed of the same material as the insulating material of the first and second insulating layers121and122described above, for example, ABF.

The underbump metal layers250may improve connection reliability of the electronic connection metals260, resulting in improvement of board level reliability of the semiconductor package300. The underbump metal layers250may be formed in the openings of the second passivation layer220and may be electrically connected to the second wiring layer115b. The underbump metal layers250may be formed by any known metallization method. That is, the underbump metal layers250may include any known metal such as copper (Cu).

The second electrical connection metals260may physically or electrically externally connect the semiconductor package300including an organic interposer. For example, the semiconductor package300may be mounted on the mainboard of the electronic device through the electrical connection metals260. Each of the electrical connection metals260may be formed of a conductive material, for example, a solder, or the like. However, this is only an example, and a material of each of the electrical connection metals260is not particularly limited thereto. Each of the electrical connection metals260may be a land, a ball, a pin, or the like. The electrical connection metals260may be formed as a multilayer or single layer structure. When the electrical connection metals260are formed as a multilayer structure, the electrical connection metals260may include a copper (Cu) pillar and a solder. When the electrical connection metals260are formed as a single layer structure, the electrical connection metals260may include a tin-silver solder or copper (Cu). However, this is only an example, and the electrical connection metals260are not limited thereto.

The number, an interval, a disposition form, and the like, of electrical connection metals260are not particularly limited, but may be sufficiently modified depending on design particulars by those skilled in the art. For example, the electrical connection metals260may be provided in an amount of several tens to several thousands according to the number of connection pads310P of the first to third semiconductor chips310A,310B, and310C may be provided in an amount of several tens to several thousands or more or several tens to several thousands or less. Some of the electrical connection metals260may be disposed in a fan-out region. The fan-out region refers to a region except for a region in which the first to third semiconductor chips310A,310B, and310C are disposed. That is, the semiconductor package300including a hybrid interposer according to the exemplary embodiment may be a fan-out semiconductor device. The fan-out package may have excellent reliability as compared to a fan-in package, may implement a plurality of input/output (I/O) terminals, and may facilitate a 3D interconnection. In addition, as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package may be manufactured to have a small thickness, and may have price competitiveness.

The underfill resin330may fix the first to third semiconductor chips310A,310B, and310C onto the hybrid interposer100. Any known material including epoxy, or the like, may be used as a material of the underfill resin330. In some exemplary embodiments, the underfill resin330may be omitted. Meanwhile, although not illustrated in the drawings, additional passive components may be disposed side-by-side with the first to third semiconductor chips310A,310B, and310C on the interposer100and be then packaged, if necessary.

A method of manufacturing the semiconductor package illustrated inFIG. 6will hereinafter be described with reference toFIGS. 8A through 8FandFIGS. 9A through 9D. Various advantageous and effects will be described in detail in a method of manufacturing the semiconductor package, particularly, the hybrid interposer.

FIGS. 8A through 8Fare cross-sectional views illustrating main processes of manufacturing a core substrate.

Referring toFIG. 8A, the first and second cavities110Ha and110Hb may be formed in the core substrate110having the first and second surfaces110A and110B opposing each other.

The core substrate110may be a copper clad laminate (CCL) having metal layers disposed on the first and second surfaces110A and110B. The core substrate110illustrated inFIG. 8A, which is a portion corresponding to a single semiconductor package, may be understood to be a portion of a large panel. An actual process may be performed in a panel unit, and a panel may be cut ultimately (after a process ofFIG. 9D) to obtain individual packages. A process of forming the first and second cavities110Ha and110Hb may be performed using a laser drill, a mechanical drill, a sandblast, or the like.

Referring toFIG. 8B, an adhesive film410may be attached to the second surface110B of the core substrate110, and the plurality of passive components125may be disposed in the first and second cavities110Ha and110Hb.

The adhesive film410may be an adhesive tape including an epoxy resin. The plurality of passive components125may include a high frequency inductor, a ferrite inductor, a power inductor, ferrite beads, an LTCC, an EMI filter, as well as a capacitor such as an MLCC. A form in which the plurality of passive components125have the same thickness is exemplified, but the plurality of passive components125may have different sizes and thicknesses. The first and second cavities110Ha and110Hb may have the size that is the same as or greater than that of a passive component having the greatest thickness. The plurality of passive components125may be arranged side-by-side with one another on a carrier film410.

Referring toFIG. 8C, the first insulating layer121may be formed on the first surface110A of the core substrate110having the first and second cavities110Ha and110Hb in which the plurality of passive components125are disposed.

In the present process, the first insulating layer121may be formed to cover the first surface110A of the core substrate110while filling at least portions of the first and second cavities110Ha and110Hb using an insulating material such as ABF. The first insulating layer121may include an encapsulating region121aencapsulating the plurality of passive components125and a flat region121bfor the first wiring layer in a subsequent process.

Referring toFIG. 8D, the adhesive film410may be removed, and the second insulating layer122may be formed on the second surface110B of the core substrate110.

On a surface from which the adhesive film is removed, the encapsulating region of the first insulating layer121and one surfaces of the plurality of passive components125may be exposed together with the second surface of the core substrate110. The second insulating layer122may be formed on the surface from which the adhesive film410is removed. The second insulating layer122may be formed by a laminating or applying method using an insulating material such as ABF, similar to the process of forming the first insulating layer.

Referring toFIG. 8E, through-holes and via holes may be formed in the core substrate110and the first insulating layer121.

The through-holes TH may be formed by drilling the core substrate110having the first and second insulating layers121and122disposed on opposite surfaces thereof, and the via holes V′ partially penetrating through the first insulating layer121and connected to electrodes of the plurality of passive components125may be formed. Such a drilling process may be performed using a laser drill. In some exemplary embodiments, additional via holes (not illustrated) connected to the passive components125may also be formed in the second insulating layer122(seeFIG. 11).

Referring toFIG. 8F, the through-vias123and the first and second wiring layers115aand115bmay be formed to provide the wiring structure of the core substrate110.

The present process may be performed by a single plating process. The through-vias123may be formed in the through-holes TH of the core substrate110to form an electrical connection path connecting the opposite surfaces of the core substrate110to each other. The first wiring layer115aconnected to the plurality of passive components125may be formed on the first insulating layer121, and the second wiring layer115bconnected to the through-vias123may be formed on the second insulating layer122. The first wiring layer115amay include the first wiring pattern112adisposed on the first insulating layer121and the connection vias113apenetrating through the first insulating layer121and connected to the plurality of passive components125.

The core substrate110in which the plurality of passive components125are embedded may be prepared by the processes described above. The core substrate110illustrated inFIG. 8Fmay substitute for a function of a carrier for forming the connection structure130in a subsequent process of manufacturing a hybrid interposer. Therefore, the carrier may not be separately used in a process of forming the connection structure.

FIGS. 9A through 9Dare cross-sectional views for describing main processes of methods of manufacturing a hybrid interposer and a semiconductor package.

Referring toFIG. 9A, an insulating layer131afor the connection structure may be formed on the core substrate110.

The insulating layer131amay be formed on the first insulating layer131so as to cover the first wiring layer by a laminating or applying method. The insulating layer131afor the connection structure may be formed of a PID, as described above. Therefore, a redistribution layer may be formed in a fine pattern by a photolithography method.

Referring toFIG. 9B, the connection structure130having the redistribution layer135may be formed.

The redistribution layer135may be formed by forming holes in the first insulating layer131aby a photolithography process, forming a seed layer, and forming a pattern using a dry film, or the like, and filling the pattern by a plating process. The plating process may be a subtractive process, an additive process, a semi-additive process (SAP), a modified semi-additive process (MSAP), or the like, but is not limited thereto. The connection structure130may be formed by repeatedly performing processes of forming the insulating layer131and the redistribution layer135by the desired number of times.

Referring toFIG. 9C, the second passivation layer220may be formed on a lower surface of the second insulating layer122, and openings may be formed in the second passivation layer220so that partial regions of the second wiring layer115bare exposed. Then, the underbump metal layers250may be formed on the second passivation layer220so as to be connected to the second wiring layer115bthrough the openings.

In addition, the connection lands132P may be provided by forming a surface treatment layer on the uppermost redistribution pattern132. After the present process is completed, a quad route test, an electrical test of the redistribution layer135and the wiring structure, or the like, may be performed, if necessary.

Referring toFIG. 9D, the first to third semiconductor chips310A,310B, and310C may be mounted on the hybrid interposer100.

Before such a process of mounting the first to third semiconductor chips310A,310B, and310C, the first passivation layer210may be formed on the upper surface of the connection structure130, and openings may be formed in the first passivation layer210so that partial regions of the connection lands132P are exposed. The respective connection pads of the first to third semiconductor chips310A,310B, and310C may be connected to the connection lands132P using the first electrical connection metals360such as the solder, and the first to third semiconductor chips310A,310B, and310C may be firmly fixed to the hybrid interposer100by the underfill resin330.

The processes described above are only an example, and some processes may be added, changed, or deleted, if necessary, or the processes may be performed in a sequence different from the sequence described above. In some exemplary embodiments, after the process of mounting the first to third semiconductor chips310A,310B, and310C, an encapsulant surrounding the first to third semiconductor chips310A,310B, and310C may be additionally formed on the hybrid interposer100(seeFIG. 10). In some exemplary embodiments, the processes of forming the second passivation layer220and the underbump metal layers250may also be performed after the first passivation layer210is formed.

The semiconductor package described above may be variously modified. For example, the passive components embedded in the core substrate may be replaced by other components such as semiconductor chips (seeFIG. 10). In addition, the passive components embedded in the core substrate may be connected to the second wiring layer as well as to the first wiring layer (seeFIGS. 11 and 12).

Semiconductor packages according to various exemplary embodiments in the present disclosure will hereinafter be described in detail with reference to the accompanying drawings.

FIG. 10is a schematic cross-sectional view illustrating a semiconductor package according to another exemplary embodiment in the present disclosure.

Referring toFIG. 10, it may be understood that a semiconductor package300A according to the present exemplary embodiment has a structure similar to that illustrated inFIGS. 6 and 7except that additional semiconductor chips320are used instead of the passive components in a first cavity110Ha and an encapsulant340is formed. Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor package300illustrated inFIGS. 6 and 7unless explicitly described to the contrary.

In the present exemplary embodiment, the passive components125may be accommodated in a second cavity110Hb, and the additional semiconductor chips320may be accommodated in the first cavity110Ha. When the core substrate includes the plurality of cavities as described above, another type of components such as semiconductor chips rather than the passive components may be accommodated in some of the cavities or the remaining spaces of the cavities in which the passive components are mounted.

In addition, the encapsulant340may be disposed on the interposer100so as to surround the first to third semiconductor chips310A,310B, and310C. In the present exemplary embodiment, an upper surface of the encapsulant340may be substantially coplanar with upper surfaces of the first to third semiconductor chips310A,310B, and310C so that the upper surfaces of the first to third semiconductor chips310A,310B, and310C are exposed.

FIG. 11is a schematic cross-sectional view illustrating a semiconductor package according to another exemplary embodiment in the present disclosure.

Referring toFIG. 11, it may be understood that a semiconductor package300B according to the present exemplary embodiment has a structure similar to that illustrated inFIGS. 6 and 7except that a plurality of passive components125are connected to a second wiring layer115bas well as to a first wiring layer115a. Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor package300illustrated inFIGS. 6 and 7unless explicitly described to the contrary.

In the present exemplary embodiment, the plurality of passive components125may be connected to the second wiring layer115bas well as to the first wiring layer115a. The second wiring layer115bmay include a second wiring pattern112bdisposed on a lower surface of a second insulating layer122and connected to through-vias123and second connection vias113bpenetrating through the second insulating layer122and connected to the passive components125. In the present exemplary embodiment, a form in which the first and second wiring layers115aand115bare connected to both of opposite surfaces of the passive components125is exemplified, but in another exemplary embodiment, only the second wiring layer115brather than the first wiring layer115amay be connected to one surfaces of the passive components125.

FIG. 12is a schematic cross-sectional view illustrating a semiconductor package according to another exemplary embodiment in the present disclosure.

Referring toFIG. 12, it may be understood that a semiconductor package300C according to the present exemplary embodiment has a structure similar to that illustrated inFIGS. 6 and 7except that additional semiconductor chips320are used instead of the passive components in a first cavity110Ha and the additional semiconductor chips320as well as the plurality of passive components125are connected to both of a first wiring layer115aand a second wiring layer115b. Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor package300illustrated inFIGS. 6 and 7unless explicitly described to the contrary.

The second wiring layer115bmay include a second wiring pattern112bdisposed on a lower surface of a second insulating layer122and connected to through-vias123and second connection vias113bpenetrating through the second insulating layer122and connected to the passive components125, similar to another exemplary embodiment illustrated inFIG. 11.

In the present exemplary embodiment, the additional semiconductor chips320as well as the passive components125may be connected to the first wiring layer115aand the second wiring layer115b. The additional semiconductor chips320may be semiconductor chips having connection pads320P disposed on upper and lower surfaces thereof. The additional semiconductor chips320may be, for example, power device chips such as insulated gate bipolar transistors (IGBTs) and field effect transistors (FETs).

FIG. 13is a schematic cross-sectional view illustrating a semiconductor package according to another exemplary embodiment in the present disclosure.

Referring toFIG. 13, it may be understood that a semiconductor package300D according to the present exemplary embodiment has a structure similar to that illustrated inFIGS. 6 and 7except that a core substrate100′ includes a plurality of core layers110A and110B. Components according to the present exemplary embodiments may be understood with reference to the description for the same or similar components of the semiconductor package300illustrated inFIGS. 6 and 7unless explicitly described to the contrary.

The core substrate100′ used in the present exemplary embodiment may include first and second core layers110A and110B. The first and second core layers110A and110B may be coupled to an intermediate insulating layer124disposed therebetween. The core substrate100′ may include through-vias123penetrating through the first and second core layers110A and110B and the intermediate insulating layer124. The first core layer110A may include first and second cavities110Ha and110Hb, similar to the core substrate110illustrated inFIG. 6, and a plurality of passive components125may be mounted in the respective cavities110Ha and110Hb and may be electrically connected to a first wiring layer115a.

In the exemplary embodiments described above, a form in which the core substrate includes the plurality of cavities is exemplified, but the core substrate may include a single cavity. In addition, the number of passive components mounted in the cavity is not limited to being plural, and may be one. The passive components and the semiconductor chips may also be mounted together in the same cavity.

As set forth above, according to an exemplary embodiment in the present disclosure, a portion of the interposer may be used as the core substrate and the passive component may be embedded in the core substrate, such that the passive component may be disposed in a region adjacent to the semiconductor chip. The core substrate may be used as the carrier in a process of manufacturing the interposer, such that the connection structure (that is, the redistribution layer) of the interposer may be formed without using a separate carrier.