SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

A semiconductor device and a forming method thereof are provided. The semiconductor device includes a device layer including a front side and a back side opposite to each other, a bonding layer disposed on the back side of the device layer, and a carrier substrate underlying the bonding layer. The device layer includes source/drain (S/D) structures, semiconductor channel layers connecting the S/D structures, and a gate structure disposed between the S/D structures and around each of the semiconductor channel layers, where the back side is planar and includes the S/D structures and the gate structure.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced a fast-paced growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. However, such scaling has also introduced increased complexity to the semiconductor manufacturing process. Thus, the realization of continued advances in ICs and devices calls for similar advances in semiconductor manufacturing processes and technology.

DETAILED DESCRIPTION

The embodiments of the disclosure describe a manufacturing process of a semiconductor device (or a portion of a nanostructure transistor device). The nanostructure transistor device (also referred to as a gate-all-around (GAA) transistor device) may include a gate structure wrapping around the perimeter of one or more nanostructures (i.e. channel regions) for improved control of channel current flow. The embodiments are not limited in this context. The semiconductor device may be included in microprocessors, memories, and/or other integrated circuits (IC). Accordingly, it is understood that additional processes may be provided before, during, and after the illustrated method, and that some other processes may only be briefly described herein. Also, the structures illustrated in the drawings are simplified for a better understanding of the concepts of the present disclosure. For example, although the figures illustrate the structure of the semiconductor device, it is understood the semiconductor device may be part of an IC that further includes a number of other devices such as resistors, capacitors, inductors, fuses, etc.

FIGS.1through17illustrate schematic perspective views and cross-sectional views of intermediate steps during a process for forming a semiconductor device, in accordance with some embodiments. For clarity of illustrations, in the drawings are illustrated the orthogonal axes (X, Y and Z) of the Cartesian coordinate system according to which the views are oriented. It should be understood thatFIG.5is a cross-sectional view of the structure illustrated inFIG.4along the Y-direction (e.g., taken along the line A-A ofFIG.4), andFIGS.6through17are cross-sectional views illustrating the following steps of the process for forming a semiconductor device. In addition,FIGS.10B and14Bare schematic cross-sectional views of optional steps during a process for forming a semiconductor device, as will be discussed in greater detail below.

Referring toFIG.1, a stack of first semiconductor layers104and second semiconductor layers106may be formed on a semiconductor substrate102′. In some embodiments, the semiconductor substrate102′ includes a crystalline silicon substrate or a bulk silicon substrate (e.g., wafer). In some embodiments, the semiconductor substrate102′ is made of a suitable elemental semiconductor (e.g., germanium), a suitable compound semiconductor (e.g., gallium arsenide, silicon carbide, indium arsenide, or indium phosphide), a suitable alloy semiconductor (e.g., silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide), and/or the like. In some embodiments, the semiconductor substrate102′ includes a SOI substrate. The semiconductor substrate102′ may include various doped regions (not individually shown) doped with p-type or n-type dopants, where the doped regions may be configured for an n-type FET, or alternatively, configured for a p-type FET.

The first semiconductor layers104and the second semiconductor layers106may be alternately stacked upon one another (e.g., along the Z direction) to form a stack. The first semiconductor layers104may be considered sacrificial layers in the sense that they are removed in the subsequent process (seeFIG.13). In some embodiments, the bottommost one of the first semiconductor layers104is formed on the semiconductor substrate102′, with the remaining second and first semiconductor layers (106and104) alternately stacked on top. However, either the first semiconductor layer104or the second semiconductor layer106may be the bottommost layer (or the layer most proximate from the semiconductor substrate102′), and either the first semiconductor layer104or the second semiconductor layer106may be the topmost layer (or the layer most distanced to the semiconductor substrate102′). The disclosure is not limited by the number of stacked semiconductor layers.

The first semiconductor layers104and the second semiconductor layers106may have different materials (or compositions) that may provide for different oxidation rates and/or different etch selectivity between the layers. For example, the second semiconductor layers106are formed of the same material as the semiconductor substrate102′, while the first semiconductor layers104may be formed of a different material which may be selectively removed with respect to the material of the semiconductor substrate102′ and the second semiconductor layers106. In some embodiments, the material of the first semiconductor layers104includes silicon germanium. In some embodiments, the second semiconductor layers106include silicon, where each of the second semiconductor layers106may be undoped or substantially dopant-free. However, the disclosure is not limited thereto, and other suitable material, or other combinations of materials for which selective etching is possible are contemplated within the scope of the disclosure. The second semiconductor layers106may be semiconductor nanosheets and may be considered as channel regions in the subsequent processes. The terms “semiconductor nanosheets” and “channel regions” may be used interchangeably herein.

With continued reference toFIG.1, a mask layer202may be formed over the topmost one of the stack, for example, on the topmost one of the first semiconductor layers104. The mask layer may be a single layer or include more than one sublayer (e.g., a first mask sublayer2021overlying the topmost first semiconductor layer104, a second mask sublayer2022overlying the first mask sublayer2021, and a third mask sublayer2023overlying the second mask sublayer2022). In some embodiments, each of the sublayers is formed of a semiconductor material similar to the material of first and second semiconductor layer104or106or is formed of different dielectric materials.

Referring toFIG.2and with reference toFIG.1, a portion of the stack of first semiconductor layers104and second semiconductor layers106and the underlying portion of the semiconductor substrate102′ may be removed to form trenches100T, thereby defining a fin structure100between adjacent trenches100T. Each trench100T may be disposed between adjacent two of the fin structures100and may continuously extend along the Y-direction. The fin structure100may be formed by patterning the stack of first semiconductor layers104and second semiconductor layers106and the semiconductor substrate102′ by using, e.g., lithography and etching, or other suitable techniques. The patterning process may use the mask layer202as a hard mask. For example, the mask layer202is initially patterned to have an elongated size along the X-direction with respect to the Y-direction, and then the mask layer is used to pattern exposed portions of the stack of first semiconductor layers104and second semiconductor layers106and the underlying semiconductor substrate102′. For example, the fin structure100is formed by etching trenches100T at exposed portions of the stack of first semiconductor layers104and second semiconductor layers106and the semiconductor substrate102′. In some embodiments, the trenches100T may be parallel strips (when viewed from the top) elongated along the Y-direction and distributed along the X-direction. The third mask sublayer2023of the mask layer202may be removed during or after the etching process. As shown inFIG.2, the first mask sublayer2021and the second mask sublayer2022are patterned and left on the fin structures100.

Referring toFIG.3and with reference toFIG.2, a plurality of isolation structures302(also referred to as shallow trench isolation (STI) structures) may be formed in lower portions of the trenches100T. For example, the isolation structures302extend at opposing sides of a lower portion of the semiconductor substrate102′. In some embodiments, each of the isolation structures302is disposed between adjacent two of the fin structures100and covers a sidewall of a lower portion of the respective fin structure100. The isolation structures302may be formed of an insulation material (e.g., an oxide, a Si-based oxide (e.g., SiOC, SiOCN, or the like), a nitride, the like, any other suitable material, or combinations thereof) which may electrically isolate neighboring fin structures100from each other.

In some embodiments, the isolation structures302are formed by initially depositing a layer of insulation material in the respective trench100T and recessing the layer of insulation material using an acceptable etching process, such as one that is selective to the material of the isolation structures302. During the recessing, the first mask sublayer2021and the second mask sublayer2022left on the fin structures100may serve as the etch masks. The isolation structures302may be recessed, and thus the fin structure100is protruded from the neighboring isolation structures302. The top surfaces302tof the isolation structures302may be a flat surface, a curved (e.g., convex or concave) surface, or combinations thereof, depending on the etching process. After (or during) the formation of the isolation structures302, the first mask sublayer2021and the second mask sublayer2022may be removed from the fin structures100, and the topmost first semiconductor layer104is then accessibly exposed.

Referring toFIGS.4-5, a dummy gate structure203and a mask layer204overlying the dummy gate structure203may be formed on the fin structures100. For example, the dummy gate structure203includes a dummy dielectric layer2031formed on the fin structures100and a dummy gate layer2032formed on the dummy dielectric layer2031. In some embodiments, the dummy dielectric layer2031covers the top surfaces302tof the isolation regions302and may extend between the dummy gate layer2032and the isolation regions302. The dummy dielectric layer2031may be or include silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The dummy gate layer2032may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polysilicon, poly-crystalline silicon-germanium, metallic oxides, and metals, and may be formed by using physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, or other techniques.

The mask layer204may be formed on the dummy gate layer2032. The mask layer204may be a single mask layer or include multiple sublayers formed of different materials including silicon nitride, silicon oxynitride, or the like. In the illustrated embodiment, the mask layer204includes a first mask sublayer2041overlying the dummy gate layer2032and a second mask sublayer2042overlying the first mask sublayer2031. For example, a layer of mask material is initially formed and then patterned using acceptable photolithography and etching techniques to form the mask layer204. Next, the pattern of the mask layer204may be transferred to the underlying dummy gate and dielectric materials to form the dummy gate layer2032and the dummy dielectric layer2031, respectively. For example, the dummy gate structure203has a lengthwise direction along the X direction which is perpendicular to the lengthwise direction (e.g., the Y direction) of the respective fin structure100.

Referring toFIG.6and with reference toFIG.5, a dummy gate spacer layer205′ may be formed over the structure illustrated inFIG.5. In the Y-Z cross section, the dummy gate spacer layer205′ may be formed on a top surface204tand sidewalls204sof the mask layer204and also formed on sidewalls203sof the dummy gate structure203. In some embodiments, the dummy gate spacer layer205′ may extend across a portion of a top surface100tsof the respective fin structure100which is not masked by the dummy gate structure203. In the X-Z cross section (not shown), the dummy gate spacer layer205′ may further extend to cover sidewalls of the respective fin structure100. The dummy gate spacer layer205′ may be a single layer or may include multiple sublayers formed of different materials including silicon oxide, silicon nitride, silicon oxynitride, or the like. The dummy gate spacer layer205′ may be deposited by thermal oxidation or deposited by CVD, ALD, or the like.

Referring toFIG.7and with reference toFIG.6, a portion of the dummy gate spacer layer205′ covering an upper portion of the mask layer204and top surface100tsof the respective fin structure100may be removed to form a dummy gate spacer205. The dummy gate spacer205may act to self-align subsequently formed source/drain (S/D) regions, as well as to protect sidewalls of the respective fin structure100during subsequent processing. For example, the dummy gate spacer layer205′ is partially removed using an etching process, such as an isotropic etching process, an anisotropic etching process, or the like. After the etching, remaining portions of the dummy gate spacer layer205′ forms the dummy gate spacer205, where the dummy gate spacer205may be disposed on the sidewalls203sof the dummy gate structure203and may extend to partially or fully cover sidewalls204sof the mask layer204. In some embodiments, the top surface204tand the upper sidewalls of the second mask sublayer2042are exposed by the dummy gate spacer205.

In some embodiments, a portion of the respective fin structure100directly underlying the dummy gate spacer layer205′ and a portion of the semiconductor substrate102′ underlying the portion of the respective fin structure100are removed to form recesses100R and a respective etched fin structure100_1between two adjacent recesses100R. S/D regions will be subsequently formed in the recesses100R, and the recesses100R may be referred to as S/D recesses. The recesses100R may be formed by etching the dummy gate spacer layer205′ overlying the top surface100ts, the underlying fin structures100, and the underlying semiconductor substrate102′ using etching processes, such as anisotropic etching, or the like. A single etching process or multiple etching processes may be employed. The respective recess100R may extend through the respective fin structure100to form the etched fin structure100_1. In some embodiments, outer sidewalls of the dummy gate spacer205are substantially aligned with sidewalls of the etched fin structure100_1. The respective recess100R may further extend into the underlying semiconductor substrate102′ to form a semiconductor substrate102having exposed top surfaces102t. The top surfaces102tof the semiconductor substrate102may be a flat surface, a curved (e.g., concave) surface, or combinations thereof, depending on the etching process.

Referring toFIG.8and with reference toFIG.7, portions of the first semiconductor layers104exposed by the recesses100R are removed in the lateral direction (e.g., the Y direction) to form a respective etched fin structure100_2having etched first semiconductor layers104′. The removal may be performed by using, e.g., isotropic etching processes or the like. For example, the etchant of the selective etching process is chosen so that the portions of the first semiconductor layers104are removed to form lateral recesses104R, while the second semiconductor layers106remain substantially intact during the etching. The respective etched first semiconductor layer104′ may be laterally recessed from the sidewalls of the underlying (or overlying) second semiconductor layer106. Although sidewalls of the etched first semiconductor layers104′ adjacent the lateral recesses104R are illustrated as being straight inFIG.8, the sidewalls of the etched first semiconductor layers104′ may be concave or convex.

Referring toFIG.9and with reference toFIG.8, inner spacers212may be formed in the lateral recesses104R. For example, the inner spacers212are formed along the etched ends of each of the etched first semiconductor layers104′ and along respective ends (along the Y-direction) of each of the etched first semiconductor layers104′ and the second semiconductor layers106. The inner spacers212may be formed of silicon nitride, silicon carbon-nitride, silicon-carbon-oxynitride, or any other type of dielectric material, and may be deposited using, e.g., a conformal deposition process and subsequent etching back to remove excess spacer material on the sidewalls of the etched fin structure100_2and on a surface of the semiconductor substrate102. In some embodiments, the inner spacers212are formed of a material different from the dummy gate spacer205. The dummy gate spacer205may serve as an etch mask when removing excess spacer material, and thus the outer sidewall of the dummy gate spacer205may be substantially aligned with outer sidewalls of the underlying second semiconductor layers106and outer sidewalls of the inner spacers212.

Referring toFIG.10Aand with reference toFIG.9, epitaxial structures220′ may be formed in the recesses100R using a process such as CVD, ALD, or the like. Each epitaxial structure220′ may include silicon germanium, indium arsenide, indium gallium arsenide, indium antimonide, germanium arsenide, germanium antimonide, indium aluminum phosphide, indium phosphide, any other suitable material, or combinations thereof. The epitaxial structures220′ may be doped with a conductive dopant to form S/D regions. It should be noted that S/D region(s) may refer to a source or a drain, individually or collectively dependent upon the context. In addition, the terms “epitaxial structures” and “S/D regions” may be used interchangeably herein. In some embodiments, the epitaxial structures220′ are formed on the exposed top surfaces102tof the semiconductor substrate102, and the epitaxial structures220′ are coupled to the outer sidewalls of the second semiconductor layers106and the inner spacers212along the Y-direction.

The epitaxial structures220′ grown on the semiconductor substrate102may have a bottom surface conformally coupled to the exposed top surfaces102tof the semiconductor substrate102. In some embodiments where the semiconductor substrate102has a concave top surface, the bottom surface of the respective epitaxial structure220′ may be a convex surface corresponding to the exposed top surfaces102t. Although the upper surfaces of the epitaxial structures220′ are illustrated as planar surfaces in the Y-Z cross section, it should be understood that in the perspective view, the upper surfaces of the epitaxial structures220′ have facets which expand laterally outward along the Y direction beyond the sidewalls of the dummy gate structures203. Each dummy gate structure203may be disposed between respective neighboring pairs of the epitaxial structures220′. The dummy gate spacer205may be used to separate the epitaxial structures220′ from the dummy gate structure203by a lateral distance so that the epitaxial structures220′ do not short out with subsequently formed gate structures.

The epitaxial structures220′ epitaxially grown on the exposed top surface102tof the semiconductor substrate102without any dielectric/isolation layer blocking the top surface102tmay provide substantially defect-free epitaxial features. In a case where an isolation layer is formed on the top surface of the semiconductor substrate in the S/D recess for prevention of leakage, the epitaxial structures will grow on sidewalls of the channel regions and such sidewall growing results in defects (e.g., void formation and/or stacking fault) in the epitaxial structures. Such defects severely affect the device performance. In the depicted embodiment, the epitaxial structures220′ grown on both of the exposed top surface102tof the semiconductor substrate102and the sidewalls of the second semiconductor layers106may advantageously reduce or prevent the defects formed in the epitaxial structures220′, thereby improving the resulting device performance and yield.

Referring toFIG.10Band with reference toFIG.10A, a planarization process51is optionally performed on the semiconductor substrate102after the formation of the epitaxial structures220′. The planarization process51may include chemical mechanical polishing (CMP), grinding, etching back, combinations thereof, or the like. After the planarization process51, the semiconductor substrate102may be fully removed, and the bottom surfaces220bof the epitaxial structures220may be substantially leveled (e.g., coplanar) with the bottom surface212bof the bottommost inner spacer212, within process variations. It should be understood that the planarization process51is not limiting in this order and can be altered in alternative embodiments.

Referring toFIG.11and with reference toFIG.10AorFIG.10B, a first interlayer dielectric (ILD) material layer306′ may be formed over the structure illustrated inFIG.10AorFIG.10B. The first ILD material layer306′ may be formed of a dielectric material including phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or the like. In some embodiments, an etch stop material layer304′ is disposed between the first ILD material layer306′ and the epitaxial structures220′, the mask layer204, and the dummy gate spacer205. The etch stop material layer304′ may include a dielectric material (e.g., silicon nitride, silicon oxide, silicon oxynitride, or the like), and may have a different etch rate than the material of the overlying first ILD material layer306′. In some embodiments, the etch stop material layer304′ and the dummy gate spacer205are of the same material, and thus no visible interface therebetween. In some other embodiments, the planarization process51described inFIG.10Bis performed after the formation of the first ILD material layer306′, and thus for purposes of illustration, the dashed box B indicates that the bottom portion of the structure inFIG.11may be removed at this stage.

Referring toFIG.12and with reference toFIG.11, a planarization process52may be performed on the first ILD material layer306′, and then a removal process may be performed to remove the dummy gate structure203so as to form a recess306R accessibly revealing the topmost etched first semiconductor layer104′. The planarization process52may include CMP, grinding, etching back, combinations thereof, or the like. In some embodiments, the planarization process52removes upper portions of the first ILD material layer306′ and the etch stop material layer304′ and also removes the mask layer204and an upper portion of the dummy gate spacer205lining the sidewalls of the mask layer204. The removal process may include one or more etching steps. For example, the etching step(s) using reaction gas(es) that selectively etch the dummy structure203at a faster rate than the first ILD material layer306′, the etch stop material layer304′, or the dummy gate spacer205.

After the planarization process52and the removal process, the first ILD layer306and the etch stop layer304are formed. In some embodiments where the etch stop material layer304′ and the dummy gate spacer205are of the same material, no visible interface is formed between the etch stop layer304and the dummy gate spacer205, and thus in the following drawings the etch stop layer304and the dummy gate spacer205are illustrated as a single layer. In some other embodiments, the planarization process51described inFIG.10Bis performed after the formation of the first ILD layer306and the recess306R, and thus for purposes of illustration, the dashed box B indicates that the bottom portion of the structure inFIG.12may be removed at this stage.

Referring toFIG.13and with reference toFIG.12, the etched first semiconductor layers104′ may be removed by etching (e.g., isotropic etching or the like). For example, using etchants which are selective to the materials of the etched first semiconductor layers104′, while the second semiconductor layers106, the first ILD layer306, the etch stop layer304, and the inner spacers212remain relatively un-etched as compared to the etched first semiconductor layers104′. During the removal process, the first ILD layer306and the etch stop layer304may protect the epitaxial structures220′. After the removal of the etched first semiconductor layers104′, respective bottom and top surfaces of each second semiconductor layers106and the top surface of the semiconductor substrate102may be exposed by recesses104S. In some other embodiments, the planarization process51described inFIG.10Bis performed after the removal of the etched first semiconductor layers104′, and thus for purposes of illustration, the dashed box B indicates that the bottom portion of the structure inFIG.13may be removed at this stage.

Referring toFIG.14Aand with reference toFIG.13, a respective gate structure240may be formed around the second semiconductor layers106and fills the recesses306R and104S. The respective gate structure240may include a gate dielectric layer244and a gate metal layer246wrapping around each second semiconductor layer106with the gate dielectric layer244disposed therebetween, where the second semiconductor layers106(also referred to as semiconductor nanosheets or semiconductor channel layers) function as channel regions. The gate dielectric layer244may be a single high-k dielectric material or may include a stack of multiple high-k dielectric materials. Other suitable dielectric material(s) may be used to form the gate dielectric layer244.

The gate metal layer246may include a number of sections abutted to each other along the Z-direction, each of the gate metal sections may extend not only along a horizontal plane (e.g., the X-Y plane), but also along a vertical direction (e.g., the Z-direction), and thus two adjacent ones of the gate metal sections may adjoin together to wrap around a corresponding one of the second semiconductor layers106, with the gate dielectric layer244disposed therebetween. The gate metal layer246may include a stack of multiple metal materials. For example, one or more work function sublayers are interposed between the gate dielectric layer244and the gate metal layer246, wherein the work function sublayers may be formed separately for the n-type FET and the p-type FET which may use different metal layers.

In some embodiments, the respective gate structure240may include an interfacial layer242formed between each second semiconductor layer106and the gate dielectric layer244and between the semiconductor substrate102and the bottommost gate dielectric layer244. In the Y-Z cross section, the interfacial layer242may be formed on the top and bottom surfaces of each second semiconductor layer106and on the top surface of the semiconductor substrate102, and then the gate dielectric layer244is formed on the interfacial layer242and also formed on the sidewalls of the inner spacers212. Subsequently, the gate metal layer246including the word function sublayer(s) and the filled metallic sublayer may be formed in the rest space of the recesses306R and104S. In some embodiments, after sequentially depositing the materials of the gate structures240, excess materials of the gate structure240may be removed by a planarizing process, so that the top surface of the topmost gate structure240is substantially leveled (e.g., coplanar) with top surfaces of the first ILD layer306and the etch stop layer304, within process variations.

Referring toFIG.14Band with reference toFIG.14A, in some embodiments, the planarization process51, as described inFIG.10B, is performed after the formation of the gate structure240. For example, the structure in the dashed box B outlined inFIG.14Ais removed to form the epitaxial structures220having planarized bottom surfaces220b, and the bottommost gate structure240and the inner spacers212around the bottommost gate structure240may be accessibly revealed after the planarization process51. In some embodiments, the bottom surfaces220bof the epitaxial structures220are substantially leveled (e.g., coplanar) with the bottom surface240bof the bottommost gate structure240and the bottom surfaces212bof the inner spacers212, within process variations. There may be planarized marks (not shown; e.g., polishing marks) left on at least one of the bottom surfaces220bof the epitaxial structures220, the bottom surface240bof the bottommost gate structure240, and the bottom surfaces212bof the inner spacers212, as a result of the planarization process51.

In some embodiments, the structure shown inFIG.14Bmay be referred to as a device layer101which includes a plurality of active devices. The device layer101may include the epitaxial structure220(e.g., S/D regions), the second semiconductor layers106(e.g., the channel regions), and the gate structures240. A back side101bof the device layer101including the bottom surfaces (e.g.,220b,240b,212b) of the epitaxial structures220, the bottommost gate structure240, and the bottommost inner spacers212may be planarized. Although the device layer101inFIG.14Bis described as including nano-FETs, other embodiments may include device layers including different types of transistors, such as planar FETs, FinFETs, thin film transistors (TFTs), or the like.

Referring toFIG.15and with reference toFIG.14B, a first bonding sublayer252may be formed on the back side101bof the device layer101. The first bonding sublayer252may be formed of a Si-based material, such as Si, SiOx, SixNy, SiOC:H, SiCO:H, SiONC:H, SiOCN:H, SINC:H, SiCN:H, SINCO:H, a combination thereof, or the like, and may be formed using suitable technique, including PVD, CVD, variants thereof, the like, or combinations thereof. For example, the first bonding sublayer252is in physical contact with the bottom surfaces220bof the epitaxial structures220. In some embodiments, the first bonding sublayer252is also in physical contact with the bottom surface240bof the bottommost gate structure240and the bottom surfaces212bof the inner spacers212.

Referring toFIG.16and with reference toFIG.15, a carrier substrate251may be provided with a second bonding sublayer254, where the second bonding sublayer254may be formed of a material the same as (or similar to) the material of the first bonding sublayer252. In some embodiments, the carrier substrate251is bonded to the structure shown inFIG.15through the second bonding sublayer254. The carrier substrate251may be a wafer (e.g., a silicon wafer), a glass carrier substrate, a ceramic carrier substrate, or the like. In some embodiments, the carrier substrate251includes a substrate having STI regions (not shown) formed in/on the substrate, and the second bonding sublayer254disposed over the STI regions and the substrate. The carrier substrate251may have more elements disposed underlying the second bonding sublayer254and may provide structural support during the bonding and in the completed device. In some embodiments, the process previously described inFIGS.1through16are performed at wafer level, the carrier substrate251with the second bonding sublayer254formed thereon may be provided in a wafer form, and thus wafer-level bonding is performed at this stage.

In some embodiments, a bonding process is performed to form bonds between the bonding surfaces of the first bonding sublayer252and the second bonding sublayer254. For example, the bonding process includes applying a surface treatment to one or more of the first bonding sublayer252and the second bonding sublayer254. The surface treatment may include a plasma treatment. After the plasma treatment, the surface treatment may further include a cleaning process that may be applied to one or more of the first bonding sublayer252and the second bonding sublayer254. Next, the carrier substrate251may be aligned with the structure inFIG.15and the two are pressed against each other to initiate a pre-bonding of the carrier substrate251to the structure inFIG.15. After the pre-bonding, an annealing process is optionally performed. Once the bonding process is complete, dielectric-to-dielectric bonds, such as oxide-to-oxide bonds, may be formed at the interface IF1between the first bonding sublayer252and the second bonding sublayer254.

The first bonding sublayer252and the second bonding sublayer254may be collectively viewed as a bonding layer250. In an embodiment where the first and second bonding sublayers are of the same material, no visible interface is formed in the bonding layer250after the bonding. In an embodiment where the first and second bonding sublayers are of the different materials, bonds (e.g., Si-to-SiOx, Si-to-SixNy, etc.) are formed at the interface IF1. The bonding layer250may act as a bottom isolation layer underlying the epitaxial structures220, the bottom gate structure240, and the bottom inner spacers212. The bonding layer250may have a planar bottom surface facing the carrier substrate251and a planar top surface facing the epitaxial structures220, the bottom gate structure240, and the bottom inner spacers212. Separately providing the device layer101and the carrier substrate251and bonding the device layer101to the carrier substrate251through the bonding layer250may be able to enlarge the process window (e.g., the thermal budget) of the device fabrication.

Referring toFIG.17and with reference toFIG.16, a second ILD layer307may be formed on the first ILD layer306. In some embodiments, S/D contacts312are formed to extend through the second ILD layer307and the underlying first ILD layer306so as to be electrically coupled to the epitaxial structures220. A gate contact314may be formed to extend through the second ILD layer307so as to be electrically coupled to the topmost gate structure240. The second ILD layer may be formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like. In some embodiments, a layer of second ILD material may be initially formed on the first ILD layer306and then patterned to form first recesses revealing the epitaxial structures220and a second recess revealing the topmost gate structure240. Next, one or more layers (e.g., barrier layers, diffusion layers, and conductive fill materials) may be formed in the first and second recesses of the second ILD layer307to form the S/D contacts312and the gate contact314, respectively. In some embodiments, a planarization process may be performed to remove excess portions of the S/D contacts312and the gate contact314, which excess portions are over top surfaces of the second ILD layer307.

With continued reference toFIG.17, a front-side interconnect structure320including interconnect wirings322formed in an interconnect dielectric layer321may be formed over a front side101aof the device layer101. The front-side interconnect structure320may be referred to as a back end of line (BEOL) interconnect structure. The interconnect dielectric layer321formed on the second ILD layer307may be a single material layer or include multiple sublayers having different materials. The material of the interconnect dielectric layer321may include a low-k dielectric material, an extra low-k (ELK) dielectric material, or the like, and the interconnect dielectric layer321may be formed using an appropriate process, such as, CVD, ALD, PVD, PECVD, or the like. The interconnect wirings322may include conductive lines and conductive vias interconnecting the layers of conductive lines, and may be formed through any acceptable process, such as, a damascene process, a dual damascene process, or the like. For example, the conductive vias may extend through the interconnect dielectric layer321to provide vertical connections between layers of the conductive lines, and the bottommost conductive vias of the interconnect wirings322may be in physical and electrical contact with the S/D contacts312and the gate contact314. The front-side interconnect structure320may be electrically coupled to the epitaxial structures220and the gate structures240through the S/D contacts312and the gate contact314, respectively, to form functional circuits.

The semiconductor device10shown inFIG.17may be a portion of a device wafer having a plurality of device die regions. The device wafer may be singulated to separate a device die from one another. The device die may be packaged in subsequent processing to form an integrated circuit package. The device die may be a logic die (e.g., central processing unit (CPU), graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical-system (MEMS) die, a MEMS controller (e.g., application specific integrated circuit (ASIC)), a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) dies), the like, or combinations thereof. It should be noted that althoughFIGS.1through17are described as a series of acts, these acts are not limiting in that the order of the acts can be altered in other embodiments, and the methods disclosed are also applicable to other structures. In alternative embodiments, some acts that are illustrated and/or described may be omitted in whole or in part.

FIG.18illustrates a schematic cross-sectional view of a semiconductor device, in accordance with some embodiments. Unless specified otherwise, like reference numerals in this embodiment (and subsequently discussed embodiments) represent like components in the embodiment shown inFIGS.1through17formed by like processes. Accordingly, the process steps and applicable materials may not be repeated herein. The difference between the semiconductor device20shown inFIG.18and the semiconductor device10shown inFIG.17includes the bonding layer350formed between the carrier substrate251and the device layer101.

In some embodiments, the bonding layer350at the back side101bof the device layer101includes first segments352and a second segment354spatially separating the first segments352from one another. For example, the first segments352bond the epitaxial structures220to the carrier substrate251, and the second segment354separates the bottommost gate structure240and the bottommost inner spacer212from the carrier substrate251. Although a single second segment354is illustrated herein, more than one second segments354may be provided on the carrier substrate251. The materials of the first segments352may be the same as (or similar to) the materials of the first and the second bonding sublayers described inFIG.17. The second segment354may be formed of a material different from the first segments352. The second segment354may be a dielectric bonding material. Alternatively, the second segment354is formed of a material same as the underlying carrier substrate251. The first segments352may be viewed as partial isolation interposed between the epitaxial structures220and the carrier substrate251.

According to some embodiments, a semiconductor device includes a device layer including a front side and a back side opposite to each other, a bonding layer disposed on the back side of the device layer, and a carrier substrate underlying the bonding layer. The device layer includes source/drain (S/D) structures, semiconductor channel layers connecting the S/D structures, and a gate structure disposed between the S/D structures and around each of the semiconductor channel layers, where the back side is planar and includes the S/D structures and the gate structure.

According to some alternative embodiments, a semiconductor device includes a bonding layer overlying a carrier substrate and a device layer overlying the bonding layer. The device layer includes semiconductor channel layers vertically separating apart from one another, a gate structure between adjacent two of the semiconductor channel layers, inner spacers disposed on opposite sidewalls of the gate structure, and source/drain (S/D) structures laterally abutting the semiconductor channel layers and the inner spacers, where an interface of bonding surfaces of the S/D structures and a bonding surface of the bonding layer is planar.

According to some alternative embodiments, a method of forming a semiconductor device includes forming a fin structure extending from a semiconductor substrate, wherein the fin structure comprises semiconductor channel layers alternatively spaced apart from one another with semiconductor sacrificial layers; growing epitaxial structures on exposed surfaces of the semiconductor substrate and the semiconductor channel layers, wherein the fin structure is interposed between the epitaxial structures; replacing the semiconductor sacrificial layers with a gate structure; planarizing the epitaxial structures to form source/drain (S/D) structures with planarized surfaces, wherein the semiconductor substrate is removed during the planarizing; and bonding the planarized surfaces of the S/D structures to a carrier substrate through a bonding layer.