Reducing spacing between conductive features through implantation

A method includes forming a first dielectric layer over a source/drain region, and forming a source/drain contact plug over and electrically connecting to the source/drain region. A top portion of the source/drain contact plug has a first lateral dimension. An implantation process is performed to implant a dopant into the first dielectric layer. The implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension. The method further includes forming a second dielectric layer over the etch stop layer, and forming a gate contact plug adjacent to the source/drain contact plug.

BACKGROUND

In the manufacturing of integrated circuits, contact plugs are used for electrically coupling to the source and drain regions and the gates of transistors. The source/drain contact plugs were typically connected to source/drain silicide regions, whose formation processes include forming contact openings to expose source/drain regions, depositing a metal layer, depositing a barrier layer over the metal layer, performing an anneal process to react the metal layer with the source/drain regions, filling a metal such as tungsten or cobalt into the remaining contact opening, and performing a Chemical Mechanical Polish (CMP) process to remove excess metal. There may be more than one level of contact plugs formed.

DETAILED DESCRIPTION

A contact plug and the method of forming the same are provided in accordance with some embodiments. The contact plug has greater lateral dimensions in its top portion than the bottom portion. An implantation process is performed to dope a dopant into a top portion of a dielectric layer, in which the contact plug is located, so that the lateral size of the top portion of the contact plug is reduced. Accordingly, the spacing between the contact plug and its neighboring conductive features is increased, and the leakage current between the contact plug and its neighboring conductive features is reduced. It is appreciated that although a Fin Field-Effect Transistor (FinFET) is used as an example, other types of transistors such as planar transistors, Gate-All-Around (GAA) transistors, or the like, may also adopt the embodiments of the present disclosure. Furthermore, although source/drain contact plugs are used as examples, other conductive features including, and not limited to, conductive lines, conductive plugs, conductive vias, and the like may also adopt the embodiments of the present disclosure to increase their spacing from their neighboring conductive features. Embodiments discussed herein are to provide examples to enable making or using the subject matter of this disclosure, and a person having ordinary skill in the art will readily understand modifications that can be made while remaining within contemplated scopes of different embodiments. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

FIGS.1-7,8A,8B,9A,9B,10A,10B,11,12A,12B,12C,12D, and13-15illustrate the perspective views and cross-sectional views of intermediate stages in the formation of a Fin Field-Effect Transistor (FinFET) and the corresponding contact plugs in accordance with some embodiments of the present disclosure. The corresponding processes are also reflected schematically in the process flow200as shown inFIG.19.

FIG.1illustrates a perspective view of an initial structure formed on wafer10. Wafer10includes substrate20. Substrate20may be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed of other semiconductor materials. Substrate20may be doped with a p-type or an n-type impurity. Isolation regions22such as Shallow Trench Isolation (STI) regions may be formed to extend from a top surface of substrate20into substrate20. The respective process is illustrated as process202in the process flow200shown inFIG.19. The portions of substrate20between neighboring STI regions22are referred to as semiconductor strips24. The top surfaces of semiconductor strips24and the top surfaces of STI regions22may be substantially level with each other. In accordance with some embodiments of the present disclosure, semiconductor strips24are parts of the original substrate20, and hence the material of semiconductor strips24is the same as that of substrate20. In accordance with alternative embodiments of the present disclosure, semiconductor strips24are replacement strips formed by etching the portions of substrate20between STI regions22to form recesses, and performing an epitaxy process to grow another semiconductor material in the recesses. Accordingly, semiconductor strips24are formed of a semiconductor material different from that of substrate20. In accordance with some embodiments, semiconductor strips24are formed of silicon germanium, silicon carbon, or a III-V compound semiconductor material.

STI regions22may include a liner oxide (not shown), which may be a thermal oxide layer formed through the thermal oxidation of a surface layer of substrate20. The liner oxide may also be a deposited silicon oxide layer formed using, for example, Atomic Layer Deposition (ALD), High-Density Plasma Chemical Vapor Deposition (HDPCVD), Chemical Vapor Deposition (CVD), or the like. STI regions22may also include a dielectric material over the liner oxide, wherein the dielectric material may be formed using Flowable Chemical Vapor Deposition (FCVD), spin-on coating, or the like.

Referring toFIG.2, STI regions22are recessed, so that the top portions of semiconductor strips24protrude higher than the top surfaces22A of the remaining portions of STI regions22to form protruding fins24′. The respective process is illustrated as process204in the process flow200shown inFIG.19. The etching may be performed using a dry etching process, for example, using NF3and NH3as the etching gases. In accordance with alternative embodiments of the present disclosure, the recessing of STI regions22is performed using a wet etching process. The etching chemical may include diluted HF solution, for example.

Referring toFIG.3, dummy gate stacks30are formed to extend on the top surfaces and the sidewalls of (protruding) fins24′. The respective process is illustrated as process206in the process flow200shown inFIG.19. Dummy gate stacks30may include dummy gate dielectrics32and dummy gate electrodes34over the respective dummy gate dielectrics32. Dummy gate electrodes34may be formed, for example, using polysilicon, and other materials may also be used. Each of dummy gate stacks30may also include one (or a plurality of) hard mask layer36over dummy gate electrodes34. Hard mask layers36may be formed of silicon nitride, silicon oxide, silicon oxy-nitride, or multi-layers thereof. Dummy gate stacks30may cross over a single one or a plurality of protruding fins24′ and/or STI regions22. Dummy gate stacks30also have lengthwise directions perpendicular to the lengthwise directions of protruding fins24′.

Next, gate spacers38are formed on the sidewalls of dummy gate stacks30. The respective process is also illustrated as process206in the process flow200shown inFIG.19. In accordance with some embodiments of the present disclosure, gate spacers38are formed of a dielectric material(s) such as silicon nitride, silicon carbo-nitride, or the like, and may have a single-layer structure or a multi-layer structure including a plurality of dielectric layers.

An etching process is then performed to etch the portions of protruding fins24′ that are not covered by dummy gate stack30and gate spacers38, resulting in the structure shown inFIG.4. The respective process is illustrated as process208in the process flow200shown inFIG.19. The recessing may be anisotropic, and hence the portions of fins24′ directly underlying dummy gate stacks30and gate spacers38are protected, and are not etched. The top surfaces of the recessed semiconductor strips24may be lower than the top surfaces22A of STI regions22in accordance with some embodiments. The spaces left by the etched protruding fins24′ and semiconductor strips24are referred to as recesses40. Recesses40are located on the opposite sides of dummy gate stacks30.

Next, as shown inFIG.5, epitaxy regions (source/drain regions)42are formed by selectively growing (through epitaxy) a semiconductor material in recesses40. The respective process is illustrated as process210in the process flow200shown inFIG.19. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, a p-type or an n-type impurity may be in-situ doped with the proceeding of the epitaxy. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), or the like may be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphorous (SiP), silicon carbon phosphorous (SiCP), or the like may be grown. In accordance with alternative embodiments of the present disclosure, epitaxy regions42comprise III-V compound semiconductors such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multi-layers thereof. After recesses40are filled with epitaxy regions42, the further epitaxial growth of epitaxy regions42causes epitaxy regions42to expand horizontally, and facets may be formed. The further growth of epitaxy regions42may also cause neighboring epitaxy regions42to merge with each other. Voids (air gaps)44may be generated. In accordance with some embodiments of the present disclosure, the formation of epitaxy regions42may be finished when the top surface of epitaxy regions42is still wavy, or when the top surface of the merged epitaxy regions42has become planar, which is achieved by further growing on the epitaxy regions42as shown inFIG.6.

After the epitaxy process, epitaxy regions42may be further implanted with a p-type or an n-type impurity to form source and drain regions, which are also denoted using reference numeral42. In accordance with alternative embodiments of the present disclosure, the implantation process is skipped when epitaxy regions42are in-situ doped with the p-type or n-type impurity during the epitaxy.

FIG.7illustrates a perspective view of the structure after the formation of Contact Etch Stop Layer (CESL)46and Inter-Layer Dielectric (ILD)48. The respective process is illustrated as process212in the process flow200shown inFIG.19. CESL46may be formed of silicon oxide, silicon nitride, silicon carbo-nitride, or the like, and may be formed using CVD, ALD, or the like. ILD48may include a dielectric material formed using, for example, FCVD, spin-on coating, CVD, or another deposition process. ILD48may be formed of an oxygen-containing dielectric material, which may be a silicon-oxide based dielectric material such as silicon oxide (formed using Tetra Ethyl Ortho Silicate (TEOS) as a process gas, for example), Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), or the like. In accordance with some embodiments, ILD48comprises hydrogen with an atomic percentage greater than about 3 percent. The hydrogen percentage may also be in the range between about 1 percent and about 10 percent. In accordance with some embodiments, the increase in the hydrogen atomic percentage may be achieved by optimizing precursor concentration, flow rate, and/or partial pressure. A planarization process such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process may be performed to level the top surfaces of ILD48, dummy gate stacks30, and gate spacers38with each other.

Next, dummy gate stacks30, which include hard mask layers36, dummy gate electrodes34, and dummy gate dielectrics32are replaced with replacement gate stacks56, which include metal gate electrodes54and gate dielectrics52as shown inFIGS.8A and8B. The respective process is illustrated as process214in the process flow200shown inFIG.19. When forming replacement gate stacks56, hard mask layers36, dummy gate electrodes34, and dummy gate dielectrics32as shown inFIG.7are first removed in one or a plurality of etching processes, resulting in trenches/openings to be formed between gate spacers38. The top surfaces and the sidewalls of protruding semiconductor fins24′ are exposed to the resulting trenches.

Next, as shown inFIGS.8A and8B, which illustrate a perspective view and a cross-sectional view, respectively, replacement gate dielectric layers52are formed, which extend into the trenches between gate spacers38.FIG.8Billustrates the reference cross-section8B-8B inFIG.8A. In accordance with some embodiments of the present disclosure, each of gate dielectric layers52includes an Interfacial Layer (IL) as its lower part, which contacts the exposed surfaces of the corresponding protruding fins24′. The IL may include an oxide layer such as a silicon oxide layer, which is formed through the thermal oxidation of protruding fins24′, a chemical oxidation process, or a deposition process. Gate dielectric layer52may also include a high-k dielectric layer formed over the IL. The high-k dielectric layer may include a high-k dielectric material such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, or the like. The dielectric constant (k-value) of the high-k dielectric material is higher than 3.9, and may be higher than about 7.0. The high-k dielectric layer is formed as a conformal layer, and extends on the sidewalls of protruding fins24′ and the sidewalls of gate spacers38. In accordance with some embodiments of the present disclosure, the high-k dielectric layer is formed using ALD or CVD.

Referring further toFIGS.8A and8B, gate electrodes54are formed over gate dielectrics52. Gate electrodes54include stacked conductive layers. The stacked conductive layers are not shown separately, while the stacked conductive layers may be distinguishable from each other. The deposition of the stacked conductive layers may be performed using a conformal deposition method(s) such as ALD or CVD. The stacked conductive layers may include a diffusion barrier layer (also sometimes referred to as a glue layer) and one (or more) work-function layer over the diffusion barrier layer. The diffusion barrier layer may be formed of titanium nitride (TiN), which may (or may not) be doped with silicon. The work-function layer determines the work function of the gate, and includes at least one layer, or a plurality of layers formed of different materials. The material of the work-function layer is selected according to whether the respective FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work-function layer may include a TaN layer and a titanium aluminum (TiAl) layer over the TaN layer. When the FinFET is a p-type FinFET, the work-function layer may include a TaN layer and a TiN layer over the TaN layer. After the deposition of the work-function layer(s), a glue layer, which may be another TiN layer, is formed. The glue layer may or may not fully fill the trenches left by the removed dummy gate stacks.

The deposited gate dielectric layers and conductive layers are formed as conformal layers extending into the trenches, and include some portions over ILD48. Next, if the glue layer does not fully fill the trenches, a metallic material is deposited to fill the remaining trenches. The metallic material may be formed of tungsten or cobalt, for example. Subsequently, a planarization process such as a CMP process or a mechanical grinding process is performed, so that the portions of the gate dielectric layers, stacked conductive layers, and the metallic material over ILD48are removed. As a result, gate electrodes54and gate dielectrics52are formed. Gate electrodes54and gate dielectrics52are collectively referred to as replacement gate stacks56. The top surfaces of replacement gate stacks56, gate spacers38, CESL46, and ILD48may be substantially coplanar at this time.

FIGS.8A and8Balso illustrate the formation of (self-aligned) hard masks58in accordance with some embodiments. The respective process is illustrated as process216in the process flow200shown inFIG.19. The formation of hard masks58may include performing an etching process to recess gate stacks56, so that recesses are formed between gate spacers38, filling the recesses with a dielectric material, and then performing a planarization process such as a CMP process or a mechanical grinding process to remove excess portions of the dielectric material. Hard masks58may be formed of silicon nitride, silicon oxy-nitride, silicon oxy-carbo-nitride, or the like.

FIGS.9A and9Billustrate a perspective view and a cross-sectional view, respectively, in the formation of source/drain contact openings60. The respective process is illustrated as process218in the process flow200shown inFIG.19. The formation of contact openings60includes etching ILD48to expose the underlying portions of CESL46, and then etching the exposed portions of CESL46to reveal epitaxy regions42. In accordance with some embodiments of the present disclosure, as illustrated inFIG.9A, gate spacers38are spaced apart from the nearest contact openings60by some remaining portions of ILD48and CESL46. In accordance with other embodiments, the sidewalls of gate spacers38or CESL46are exposed to contact openings60.

In accordance with some embodiments, as shown inFIG.9B, contact openings60have top lateral dimensions (widths) Wt1 greater than the respective bottom dimensions Wb1. The differences (Wt1−Wb1) may be greater than about 3 nm, and may be in the range between about 1 nm and about 5 nm. The sidewalls60S of ILD48, which sidewalls face contact openings60, may be substantially straight.

Referring toFIGS.10A and10B, silicide regions66and source/drain contact plugs70are formed. In accordance with some embodiments, metal layer62(such as a titanium layer or a cobalt layer,FIG.10B) is deposited, for example, using Physical Vapor Deposition (PVD) or a like method. Metal layer62is a conformal layer, and extends onto the top surface of source/drain regions42and the sidewalls of ILD48. A metal nitride layer (such as a titanium nitride layer)64is then deposited as a capping layer. An annealing process is then performed to form source/drain silicide regions66, as shown inFIGS.10A and10B. The respective process is illustrated as process220in the process flow200shown inFIG.19. Next, a metallic material68such as cobalt, tungsten, or the like, is filled into the remaining portions of the contact openings. A planarization process such as a CMP process or a mechanical grinding process is then performed to remove excess portions of metal layer62and the metallic material68, leaving contact plugs70. The respective process is also illustrated as process220in the process flow200shown inFIG.19. FinFET100is thus formed. Contact plugs70have sidewalls70S, which may be straight and slanted, for example, with tilt angle α1 smaller than 90 degrees.

Referring toFIG.11, etch stop layer72is deposited. The respective process is illustrated as process222in the process flow200shown inFIG.19. Etch stop layer72may be formed of a silicon-containing material such as SiN, SiCN, SiC, SiOCN, or the like, or may be formed of other non-silicon-containing dielectric materials. The formation method may include PECVD, ALD, CVD, or the like.

Referring toFIG.12A,12B, or12C, an implantation process74is performed. The respective process is illustrated as process224in the process flow200shown inFIG.19. In implantation process74, a dopant is implanted to cause the volume of ILD48, CESL46, and gate spacers38to expand, so that contact plugs70are squeezed, and their lateral dimensions are reduced, as will be discussed in detail subsequently. In accordance with some embodiments, the dopant comprises Ge, Xe, Ar, Si, or combinations thereof.

FIG.12Dillustrates a cross-sectional view of contact plug70after the implantation process74. To show the results of the implantation process, the sidewalls70S of the top portion of contact plug70before the implantation process74is shown using dashed lines, and the sidewalls70S′ of the top portion of contact plug70after the implantation process74is shown using solid lines. In accordance with some embodiments, the top portion of contact plug70is shrunk in the widthwise direction due to the implantation process. The shrunk of the top portion of contact plug70may be caused by the implantation of the dopant into dielectric layers such as ILD48, CESL46, and gate spacers38, so that these dielectric layers expand in volume, and squeeze contact plug70, so that the top lateral dimension of contact plug70is reduced from Wt1 to Wt1′. In accordance with some embodiments, the difference (Wt1−Wt1′) is greater than about 1 nm, and may be in the range between about 1 nm and about 5 nm. On the other hand, the dopant reaching to the lower portion of ILD48(if any) has a very small amount, and does not change the bottom lateral dimension Wb1.

Furthermore, referring toFIG.10A, contact plug70may have top length Lt1 greater than top width Wt1. Contact plug70is more difficult to shrink, when squeezed, in the lengthwise direction than in the widthwise direction. The greater the top length Lt1, the smaller the shrink value (Lt1−Lt1′) will be, wherein Lt1′ is the top length after the implantation process74. Accordingly, shrink value (Lt1−Lt1′) is smaller than (Wt1−Wt1′). In accordance with some embodiments, the shrink value (Lt1−Lt1′) is smaller than about 0.5 nm, smaller than about 0.2 nm, or smaller than about 0.1 nm.

Referring back toFIG.12D, as a result of the implantation process, contact plug70may become taller since the total volume of contact plug70is essentially unchanged. The increase ΔH in height may be greater than about 3 nm, and may be in the range between about 1 nm and about 10 nm. The top surface70T of contact plug70may become rounded, and the rounded portion may protrude higher than the top surface of ILD48. Dashed line70T shows a possible profile of the rounded top surface of contact plug70.

Furthermore, due to the implantation process74, the sidewalls of the top portions of contact plug70is changed in position, with the top sidewall portions before the implantation process being illustrated as70S, and the top sidewall portions after the implantation process illustrated as being70S′. In accordance some embodiments, the straight sidewalls70S (before the implantation process74) may have a tilt angle α1 smaller than 90 degrees. Tilt angle α1 may also be smaller than about 70 degrees, and may be in the range between about 60 degrees and about 85 degrees. The straight sidewall portions70S′ (after the implantation process74) of the top portion of contact plug70may have a tilt angle α2 greater than tilt angle α1. Tilt angle α2 may be greater than about 85 degrees, and may be in the range between about 70 degrees and about 100 degrees. The difference (α2−α1) may be in the range between about 1 degree and about 15 degrees.

In accordance with some embodiments, the top portion of contact plug, which top portion is shrunk laterally by the implantation process, has a height H1, which may be in the range between about 3 nm and about 10 nm. Furthermore, the ratio H1/H2 (with H2 being the total height of contact plug70) may be greater than about 0.15, and may be in the range between about 0.15 and about 0.5.

To achieve the lateral shrinking of the top portion of contact plugs70, the energy of the implantation is selected to be in a range, which is not too high and not too low. If the implantation energy is too high, the dopant may penetrate through etch stop layer72, ILD48and CESL46and reach source/drain regions42. This may adversely change the property of the resulting FinFET in an un-controllable way. If the implantation energy is too low, the dopant cannot extend into ILD48deep enough, and hence height H1 (FIG.12D) of the shrunk portion is too small. In accordance with some embodiments, the implantation process74may be performed with an energy in the range between about 2 keV and about 50 keV. The dosage of the dopant is also selected so that it is not too high to change the characteristic of the etch stop layer72, implanted ILD48, and CESL46too much, and not too low so that the top portions of contact plugs is adequately shrunk in width. In accordance with some embodiments, the dosage is in the range between about 1E14/cm2and 1E16/cm2. The energy and the dosage may be selected in combination so that the top ⅓ part of each of contact plug70is reduced in dimension by 1 nm or more.

Furthermore, to increase the magnitude of shrinking, the implanted dielectric layers such as ILD48may have increased atomic percentage of hydrogen. Experiment results revealed that with more hydrogen in the implanted dielectric materials adjacent to contact plugs70, the shrinking of contact plugs70is more significant. This may be caused by the effect of breaking the bonds in the dielectric materials. For example, the Si—O bonds in the dielectric materials may be broken by the implantation process. The increased amount of hydrogen (as aforementioned in ILD48) results in more hydrogen atoms to be available and connected to the broken bonds, and hence the volume of the implanted dielectric materials is increased compared to the volume before the implantation process.

The implantation process74may be performed vertically, or tilted with a tilt angle smaller than about 60 degrees. During implantation process74, wafer10may be cooled or heated, or may be at the room temperature. For example, the temperature of wafer10may be in the range between about −100° C. and about 500° C. during the implantation.

Referring toFIGS.12A,12B, and12C, as a result of implantation process74, doped regions76A are formed in contact plugs70and the corresponding overlying portions of etch stop layer72, and doped regions76B are formed in dielectric layers such as ILD48, gate spacers38, hard masks58, and the corresponding overlying portions of etch stop layer72. Since contact plugs70(particularly metal region68) are formed of metal and hence are dense, the dopant is more likely to pile up at the top surfaces of metal regions68. Doped region76A thus extends into only a shallow surface portion of contact plugs70, with the dopant concentrations significantly reduce in lower portions than the respective upper portions. The illustrated doped regions76A and76B may represent the regions with relatively high concentrations, for example, with concentrations smaller than the respective peak concentration values by differences that are smaller than two orders (or may be three orders). The doped regions doped with lower concentrations are not shown as parts of doped regions76A and76B. Since the metal region68is denser, and the dielectric layers are relatively loose, the depth D1 of the doped regions76A is smaller than the depth D2 of the doped regions76B in the dielectric layers. In accordance with some embodiments, the depth D1 is smaller than height H1. Also, the depth D2 is smaller than the total thickness T1 of CESL46and ILD48, so that the bottom portions of contact plugs70are not laterally shrunk. Otherwise, the resistance of contact plugs70will be adversely increased. For example, ratio D2/T1 may be in the range between about 0.3 and about 1. Also, ratio D1/D2 may be in the range between about 0.05 and about 0.5. In accordance with some embodiments, depth D1 is in the range between about 1 nm and about 5 nm, and depth D2 is in the range between about 5 nm and about 20 nm.

In accordance with some embodiments, as shown inFIG.12A, implantation process74is performed on wafer10without any implantation mask, and is performed through etch stop layer72. Since there is no implantation mask, an entirety of wafer10is subject to the implantation, and all surface features of the wafer10receive the dopant. In accordance with alternative embodiments, as shown inFIG.12B, the implantation is performed without etch stop layer72being formed. It is appreciated that implanting with or without etch stop layer72may have different effects. For example, the implanted dopant may have a distribution (sometimes Gaussian distribution), with the peak concentration of the dopant being either at the surface of the implanted features, or at a certain depth below the top surface of the implanted features, depending on the type of dopant, the implantation energy, etc. The implantation with or without the etch stop layer provides a mean to adjust the peak concentration position/level in order to achieve maximum result. For example, without the etch stop layer, the peak concentration may be at a deeper level, while with the etch stop layer, the peak concentration may be a shallower level.

In accordance with yet alternative embodiments, as shown inFIG.12C, the implantation is performed with implantation mask75being formed to mask the regions not to be implanted. For example, implantation mask75may be formed in the regions far away from contact plugs70, because the expansion of the far-away regions will not cause the squeezing of contact plugs70. Implanting with implantation mask may limit the implanted region in desirable regions without affecting other regions. For example, when Si or Ge is implanted, and when the dopant concentration is high, the leakage current between neighboring conductive features such as neighboring contact plugs70may increase due to the high-concentration of Si or Ge in dielectric layers. The implantation mask may prevent such increase in leakage current since the Si/Ge will not be doped into a continuous region connecting two neighboring conductive features. On the other hand, in some situations such as when there is no leakage concern (when Xe and/or Ar are implanted or when the dopant concentration is low), the cost of the implantation mask may be saved by not forming the implantation mask. It is appreciated that inFIG.12C, etch stop layer72is illustrated as being dashed to indicate that at the time implantation process74is performed, etch stop layer72may or may not be formed.

Since metal region68is dense, the dopant is piled up around (both higher than and lower than) the top surface of metal region68. Also, the dopant may have some portions directly over metal region68and extend into at least the lower portions of etch stop layer72. This causes doped regions76A to extend into at least the lower portion, and possibly extend into the entirety, of etch stop layer72.FIG.16illustrates a vertical distribution profile of the dopant in metal region68and etch stop layer72in accordance with some embodiments. The distribution profile is measured on a sample wafer using Secondary-Ion Mass Spectrometry (SIMS). The X-axis shows the depth measured from the top surface of etch stop layer72and in the direction marked by arrow77A inFIG.12A. The Y-axis shows the normalized dopant concentration. It is observed that the peak dopant concentration of doped region is at the interface between etch stop layer72and metal region68, indicating the pile-up of the dopant at the interface. Also, there is a high concentration of the dopant in etch stop layer72, which may be caused by the back-scattering from metal region68. Accordingly, as shown inFIG.12A, doped region76A is illustrated as extending into etch stop layer72. In accordance with some embodiments, the dopant concentration in metal region68and etch stop layer72is in the range between about 1E17/cm3and about 1E22/cm3. The peak dopant concentration PC1 in metal region68and etch stop layer72may be in the range between about 1E20/cm3and about 1E22/cm3.

FIG.17illustrates a distribution profile of the dopant in ILD48and etch stop layer72in accordance with some embodiments. The distribution profile is also measured from the sample wafer using SIMS. The X-axis shows the depth measured from the top surface of etch stop layer72and in the direction marked by arrow77B inFIG.12A. The Y-axis shows the normalized dopant concentration. Since dielectric layers have smaller density values, the peak concentration of the doped regions76B is inside ILD48, rather than at the interface between etch stop layer72and ILD48. The dopant in ILD48extends deeper than doped region76A, but has less steep change than shown inFIG.16. In accordance with some embodiments, the dopant concentration in etch stop layer72and ILD48is in the range between about 1E17/cm3and about 1E22/cm3. The peak dopant concentration PC2 in etch stop layer72and ILD48may be in the range between about 1E17/cm3and about 1E22/cm3. Peak dopant concentration PC2 may be lower than the peak dopant concentration PC1 (FIG.16).

Referring toFIG.12A,12B, or12C again, in accordance with some embodiments, the bottom parts of metal regions68have a dopant concentration (of the implanted dopant) that is at least three orders (1,000 times) lower than the peak dopant concentration at the interface between metal region68and etch stop layer72. The bottom parts of metal regions68may be free from the implanted dopant in accordance with some embodiments. In accordance with some embodiments, the bottom parts of metal ILD48and the underlying part of CESL46have a dopant concentration (of the implanted dopant) that is at least three orders (1,000 times) or four orders lower than the peak dopant concentration in ILD48. The bottom parts of ILD48may be free from the implanted dopant in accordance with some embodiments.

Referring toFIG.13, ILD78is formed over etch stop layer72. The respective process is illustrated as process226in the process flow200shown inFIG.19. The material and the formation method of ILD78may be selected from the same candidate materials and formation methods, respectively, for forming ILD48. For example, ILD78may include silicon oxide, PSG, BSG, BPSG, or the like, which includes silicon therein. In accordance with some embodiments, ILD78is formed using PECVD, FCVD, spin-on coating, or the like.

FIG.14illustrates the etching of ILD78to form source/drain contact openings80. The respective process is illustrated as process228in the process flow200shown inFIG.19. In accordance with some embodiments, ILD78is etched using a process gas including C2F6, CF4, SO2, the mixture of HBr, Cl2, and O2, or the mixture of HBr, Cl2, O2, and CF2etc. The etching processes are anisotropic.

Next, as also shown inFIG.14, etch stop layer72is etched in an anisotropic process. The respective process is also illustrated as process228in the process flow200shown inFIG.19. Source/drain contact plugs70are thus exposed to source/drain contact openings80. Etch stop layer72may be etched using a fluorine-containing gas such as the mixture of CF4, O2, and N2, the mixture of NF3and O2, SF6, or, the mixture of SF6and O2. The etching may be anisotropic or isotropic.

FIG.14further illustrates the formation of gate contact opening84in accordance with some embodiments, which is formed by etching ILD78, etch stop layer72, and hard mask58. The respective process is illustrated as process230in the process flow200shown inFIG.19. In the following discussed example embodiments as shown inFIGS.16and17, gate contact plug88and source/drain contact plugs86are formed sharing a common metal-filling process. It is appreciated that gate contact plug88may also be formed before or after the formation of source/drain contact plugs86.

FIG.15illustrates the formation of source/drain contact plugs86and gate contact plug88in openings80and84, respectively. The respective process is illustrated as process232in the process flow200shown inFIG.19. In accordance with some embodiments, the formation process includes the deposition of a metallic material(s), which may be deposited using PVD, CVD, plating, combinations thereof, or the like, followed by a planarization process to remove excess portions of the metallic material(s). The deposited metallic material(s) may include tungsten, cobalt, molybdenum, copper, or alloys thereof. The metallic material may be the same as or different from the material of metal region68. For example, when metal region68is formed of or comprises cobalt, metallic material may be formed of or comprises tungsten or cobalt. In accordance with some embodiments, source/drain contact plugs86and gate contact plug88are glue-less, wherein the entirety of each of source/drain contact plugs86and gate contact plug88is formed of a homogenous material, with no glue layer formed. In accordance with alternative embodiments, each of source/drain contact plugs86and gate contact plug88includes a glue layer, which may be formed of titanium, titanium nitride, tantalum, tantalum nitride, or the like. The deposited metallic material such as tungsten, cobalt, or the like is thus deposited over the glue layer. Accordingly, dashed lines are illustrated to show the possible boundaries between the glue layers and the overlying metallic material.

As shown inFIG.15, the spacing Si between contact plug70and its neighboring conductive feature such as gate contact plug88may be very small. The leakage current between contact plug70and its neighboring conductive features is related to spacing S1, and the greater the spacing S1, the smaller the leakage current is. In order to reduce the leakage current, either the pitches between contact plug70and its neighboring conductive features are increased, or the pitches are not increased, while contact plugs70are formed narrower. Both approaches have drawbacks. Increasing the pitches has the adverse effect of increasing the size of FinFET100, while making contact plugs70narrower results in higher resistance. In accordance with the embodiments of the present disclosure, the contact plugs such as contact plug70may have wider upper portions than the respective lower portions, and the upper portion is the major source of leakage. Therefore, by shrinking the upper portions so that the upper portions (not the lower portions) are made smaller, the major part of the leakage current is reduced. This does not significantly increase the resistance of contact plugs70since the wider upper parts of the contact plugs70are not the major contributor of the resistance.

In accordance with some embodiments, an additional implantation process90is performed to laterally shrink the top portions86T and88T of source/drain contact plugs86and gate contact plug88, respectively. The respective process is illustrated as process234in the process flow200shown inFIG.19. Implantation process90may be essentially the same as implantation process74(FIG.12A,12B, or12C), and hence the details of implantation process90are not repeated. In accordance with other embodiments, the additional implantation process90is not performed. Whether to perform the additional implantation process90or not may be related to the main material of contact plugs86and88. For example, cobalt shrinks more than tungsten when subjecting to implantation process90. Accordingly, when cobalt is used to form source/drain contact plugs86and gate contact plug88, implantation process90may be performed, while if tungsten is used to form source/drain contact plugs86and gate contact plug88, the magnitude of the shrinking is less significant compared to cobalt, and implantation process90may be, or may not be, performed, depending on the performance requirement.

FIG.18illustrates leakage currents as a function of overlay shift. Line102illustrates a result obtained from a sample formed adopting an embodiment of the present disclosure. Line104illustrates a result obtained from a sample, whose formation of contact plugs does not include implantations for shrinking contact plugs. Overlay position106indicates that contact plug70is in the middle of two neighboring gate contact plugs, so that regardless of whether contact plug70is formed shifting to the left or shifting to the right, the leakage current will increase. Assuming 108 is the upper limit of the leakage current allowed by specification. Window (process margin) M1is the process window of the conventional formation method, and window W2is the process window of the embodiments of the present disclosure.FIG.18illustrates that the process window is increased from M1to M2by adopting the embodiments of the present disclosure.

The embodiments of the present disclosure have some advantageous features. By implanting the top portion of ILD, in which contact plugs are formed, the spacing between the contact plugs and their neighboring conductive features is increased, leading to the reduction of leakage currents. On the other hand, the sizes of the transistors are not increased, and the resistance values of the contact plugs are also not increased significantly.

In accordance with some embodiments of the present disclosure, a method includes forming a first dielectric layer over a source/drain region; forming a source/drain contact plug over and electrically connecting to the source/drain region, wherein a top portion of the source/drain contact plug has a first lateral dimension; performing an implantation process to implant a dopant into the first dielectric layer, wherein the implantation process results in the source/drain contact plug to have a second lateral dimension smaller than the first lateral dimension; forming a second dielectric layer over the first dielectric layer; and forming a gate contact plug adjacent to the source/drain contact plug. In accordance with an embodiment, in the implantation process, an element selected from the group consisting of Ge, Xe, Ar, Si, and combinations thereof is implanted. In accordance with an embodiment, in the implantation process, germanium is implanted. In accordance with an embodiment, in the implantation process, an additional top portion of the first dielectric layer is implanted, and an additional bottom portion of the first dielectric layer is not implanted. In accordance with an embodiment, the second lateral dimension is smaller than the first lateral dimension by a difference greater than about 1 nm. In accordance with an embodiment, the implantation process results in the source/drain contact plug to have an increased height. In accordance with an embodiment, the implanting process is performed before the etch stop layer is formed and when the first dielectric layer is exposed. In accordance with an embodiment, in the implanting process, etch stop layer is implanted. In accordance with an embodiment, the implantation process is performed without adopting a patterned implantation mask.

In accordance with some embodiments of the present disclosure, a structure includes an inter-layer dielectric; a source/drain contact plug in the inter-layer dielectric, wherein an upper portion of the inter-layer dielectric comprises a dopant having a first dopant concentration, and a lower portion of the inter-layer dielectric has a second dopant concentration of the dopant, wherein the second dopant concentration is smaller than the first dopant concentration; a gate stack on a side of the source/drain contact plug; and a gate contact plug over and electrically coupling to the gate stack. In accordance with an embodiment, the dopant comprises germanium. In accordance with an embodiment, the lower portion of the inter-layer dielectric is substantially free from the dopant. In accordance with an embodiment, the structure further includes an etch stop layer over the source/drain contact plug and the inter-layer dielectric, wherein the etch stop layer comprises the dopant. In accordance with an embodiment, the source/drain contact plug comprises a sidewall comprising an additional lower portion, wherein the additional lower portion is straight; and an additional upper portion higher than the additional lower portion, wherein the additional upper portion has a first height greater than about 15 percent of a second height of the source/drain contact plug, and an entirety of the additional upper portion is more vertical than the additional lower portion.

In accordance with some embodiments of the present disclosure, a structure includes a source/drain region; a silicide region over and contacting the source/drain region; a first inter-layer dielectric; a first contact plug over and contacting the silicide region, with the first contact plug being extending into the first inter-layer dielectric; an etch stop layer over and contacting the first contact plug; a second inter-layer dielectric over and contacting the etch stop layer; a second contact plug extending into the second inter-layer dielectric; and a dopant having a first dopant concentration in a top portion of the first inter-layer dielectric, and a second dopant concentration in a bottom portion of the first inter-layer dielectric, wherein the first dopant concentration is at least two orders higher than the second dopant concentration. In accordance with an embodiment, the first dopant concentration is at least three orders higher than the second dopant concentration. In accordance with an embodiment, the first dopant concentration is greater than about 1E20/cm3. In accordance with an embodiment, the bottom portion of the first inter-layer dielectric is free from the dopant. In accordance with an embodiment, the dopant is selected from the group consisting of Ge, Xe, Ar, Si, and combinations thereof. In accordance with an embodiment, the dopant comprises germanium.