Switching power converter circuit

One example includes a switching power converter circuit. The circuit includes a gate driver configured to generate at least one switching signal in response to a feedback signal. The circuit also includes a feedback stage configured to generate the feedback signal based on an amplitude of an output voltage at an output. The circuit further includes a power stage including at least one switch and a transformer. The at least one switch can be controlled via the respective at least one switching signal to provide a primary current through a primary winding of the transformer to induce a secondary current through a secondary winding of the transformer to generate the output voltage. The power stage further includes a self-driven synchronous rectifier stage coupled to the secondary winding to conduct the secondary current from a low voltage rail through the secondary winding.

TECHNICAL FIELD

The present disclosure relates generally to electronics, and specifically to a switching power converter circuit.

BACKGROUND

DC-DC power converters are used to convert an unregulated source of DC power into a source of constant voltage for use in various applications. Some DC power converters include a transformer having primary and secondary windings. A switch can be coupled to the primary winding in order to control energy transfer from the primary to secondary winding. In PWM-controlled converters, the switch can be under the control of a pulse width modulator (PWM) circuit which varies the duty cycle over a switching period. Increasing switching frequency to reduce size and weight, such as required in certain applications, can rapidly increase switching losses. To offset the switching losses, various techniques of soft switching can be employed, such as those which have zero-current or zero voltage switching at turn-on and turn-off transitions, while keeping voltage and current stresses similar those in a PWM (hard-switched) converter. This is so because stress levels for switch voltage and current similar to those in a PWM (hard-switched) converters can provide the best possible efficiency in power transfer.

SUMMARY

One example includes a switching power converter circuit. The circuit includes a gate driver configured to generate at least one switching signal in response to a feedback signal. The circuit also includes a feedback stage configured to generate the feedback signal based on an amplitude of an output voltage at an output. The circuit further includes a power stage including at least one switch and a transformer. The at least one switch can be controlled via the respective at least one switching signal to provide a primary current through a primary winding of the transformer to induce a secondary current through a secondary winding of the transformer to generate the output voltage. The power stage further includes a self-driven synchronous rectifier stage coupled to the secondary winding to conduct the secondary current from a low voltage rail through the secondary winding.

Another example includes a switching power converter circuit. The circuit includes a gate driver configured to generate at least one switching signal in response to a feedback signal. The circuit also includes a feedback stage configured to generate the feedback signal based on an amplitude of an output voltage at an output. The circuit further includes a power stage comprising a pair of switches and a transformer. The pair of switches can be alternately activated via the respective pair of switching signals in a first switching phase and a second switching phase to provide a primary current through a primary winding of the transformer to induce a secondary current through a secondary winding of the transformer to generate the output voltage. The power stage further includes a pair of transistors arranged as a self-driven synchronous rectifier stage coupled to the secondary winding to conduct the secondary current from a low voltage rail through the secondary winding. The pair of transistors can be configured to alternately activate in the first and second switching phases in response to respectively conducting the secondary current in each of the first and second switching phases.

Another example includes a switching power converter circuit. The circuit includes a gate driver configured to generate at least one switching signal in response to a feedback signal. The circuit also includes a power stage including at least one switch and a transformer. The at least one switch can be controlled via the respective at least one switching signal to provide a primary current through a primary winding of the transformer to induce a secondary current through a secondary winding of the transformer to generate an output voltage. The power stage further includes a self-driven synchronous rectifier stage coupled to the secondary winding to conduct the secondary current from a low voltage rail through the secondary winding. The circuit further includes a feedback stage. The feedback stage includes an isolation transformer comprising a primary winding configured to conduct a feedback current associated with the output voltage and a secondary winding configured to generate a secondary feedback current based on the feedback current. The feedback stage further includes a rectifier configured to rectify the secondary feedback current, the feedback stage being configured to generate the feedback signal based on the rectified secondary feedback current in a temperature-compensated manner.

DETAILED DESCRIPTION

The present disclosure relates generally to electronics, and specifically to a switching power converter circuit. The switching power converter circuit can be implemented as a soft-switching power converter that includes a gate driver configured to generate at least one switching signal in response to a feedback signal that is based on an output voltage of the switching power converter. The switching power converter circuit can also include a power stage that includes at least one switch that is controlled by the respective switching signal(s) to generate a primary current flow through a primary winding of a transformer. A secondary current is thus induced in the secondary winding of the transformer, and the secondary current flows from ground to an output on which the output voltage is generated (e.g., via an output filter).

The power stage can include a self-driven synchronous rectifier stage that is configured to alternately activate to provide the secondary current from ground to flow through respective portions of the secondary winding at each of different switching phases, and thus different directions of current flow of the primary current through the primary winding. As an example, the self-driven synchronous rectifier stage can include a pair of transistors that each have a gate that is coupled to a drain of the other of the pair of transistors, such that the flow of the secondary current from ground through the activated one of the pair of transistors slowly activates the other of the pair of transistors synchronously with the activation of the switch(es) in the power stage. Accordingly, the self-driven synchronous rectifier stage provides self-activating very low resistance current paths for the secondary current in providing the output voltage at the output of the switching power converter circuit.

The switching power converter also includes a feedback stage that is configured to generate the feedback signal based on an amplitude of the output voltage. As an example, the feedback stage includes an isolation transformer that is configured to isolate a feedback current that is provided from the output with respect to the feedback stage, and thus the gate driver. The feedback current can be an AC current that induces an AC secondary feedback current that is rectified by a rectifier in the feedback stage (e.g., via a diode and an RC filter). As an example, the rectifier can also include a second diode, a second resistor, and a second capacitor that are arranged as fabrication matched components with respect to the diode and RC filter. As a result, the rectified feedback voltage that is provided by the rectifier can be temperature compensated.

FIG. 1illustrates an example block diagram10of a switching power converter system. As an example, the switching power converter system can be configured as a double-forward power converter circuit. The switching power converter system can be implemented in any of a variety of applications that require generating a regulated output voltage VOUTbased on an input voltage VIN. For example, the switching power converter system can be implemented in aerospace or military applications that may require very low switching losses.

The switching power converter system includes a gate driver12that is configured to generate at least one switching signal SW in response to a feedback signal FB. As an example, the feedback signal FB can be generated based on the output voltage VOUT, such that the switching signal(s) SW can be provided to regulate a substantially constant amplitude of the output voltage VOUT. The gate driver12can thus be configured to generate the switching signal(s) SW in a pulse-width modulation (PWM) manner. The switching signal(s) SW are provided to a power stage14that includes a respective at least one switch that is controlled by the switching signal(s) SW. As an example, the power stage14can include a transformer, such that the switch(es) can be activated by the switching signal(s) SW to generate a primary current flow through a primary winding of the transformer. In response, a secondary current is induced in the secondary winding of the transformer, and the secondary current flows from a low voltage rail (e.g., ground) to an output16on which the output voltage VOUTis generated (e.g., via an output filter). The switching power converter system further includes a feedback stage18that is configured to generate the feedback signal FB based on the output voltage VOUT, as described in greater detail below. As described in greater detail herein, the feedback stage18can generate the feedback signal FB in a manner that is temperature compensated, such that the feedback signal FB can be substantially unaffected by variations in temperature.

In the example ofFIG. 1, the power stage14includes a self-driven synchronous rectifier stage20that is configured to alternately activate to provide the secondary current from ground to flow through respective portions of the secondary winding at each of different switching phases, and thus different directions of current flow of the primary current through the primary winding. As an example, the self-driven synchronous rectifier stage20can include a pair of transistors that each have a gate that is coupled to a drain of the other of the pair of transistors, such that the flow of the secondary current from ground through the activated one of the pair of transistors slowly activates the other of the pair of transistors synchronously with the activation of the switch(es) in the power stage. Accordingly, the self-driven synchronous rectifier stage20provides self-activating very low resistance current paths for the secondary current in providing the output voltage at the output of the switching power converter system.

FIG. 2illustrates an example of a switching power converter circuit50. The switching power converter system50can be implemented in any of a variety of applications that require generating a regulated output voltage VOUTbased on an input voltage VIN. As an example, the switching power converter circuit50can correspond to the switching power converter system in the diagram10of the example ofFIG. 1.

In the example ofFIG. 2, the switching power converter circuit50is demonstrated as a double-forward power converter, similar to as demonstrated in U.S. Pat. No. 5,973,939, which is incorporated herein in its entirety by reference. The switching power converter circuit50includes a gate driver52and a power stage54. The power stage54includes a transformer56having a single primary winding and dual secondary windings. As an example, the transformer56can have each equal turns with respect to the dual secondary windings. The polarities of the primary and secondary windings are as indicated by the dots inFIG. 2. The power stage54also includes a switch stage57that includes an N-channel field effect transistor (N-FET) N1that acts as a switch to control the energy flow in the primary winding of the transformer56. In particular, the source of the N-FET N1is coupled to a current source58coupled to the primary winding and a drain coupled to a low voltage rail (e.g., ground). In the example ofFIG. 2, the current I1is also provided to a feedback stage, such as the feedback stage18in the example ofFIG. 1, such as demonstrated in greater detail in the example ofFIG. 5. The input voltage VINis likewise coupled to the primary winding of the transformer56over a capacitor C1. The current source58is therefore configured to provide a primary current I1from the input voltage VINthrough the primary winding of the transformer56and through the N-FET N1in response to the N-FET N1being activated by a first switching signal SW1provided at the gate of the N-FET N1by the gate driver52.

A P-channel FET (P-FET) P1is coupled to a reset capacitor CRat a source, and has a drain coupled to the source of the N-FET N1and the low-voltage rail. The P-FET P1in combination with the reset capacitor CRis used for resetting the core of the transformer56and for enabling zero-voltage switching for both the N-FET N1and the P-FET P1. The gate driver52provides a second switching signal SW2to the gate of the P-FET P1to control the P-FET P1as a switch. Thus, the N-FET N1and the P-FET P1are operated in a complementary manner wherein both switches are not on at the same time. In addition, the gate driver52is configured to provide a predetermined dead time after the N-FET N1is turned off and before the P-FET P1is turned on, and vice versa.

Lossless snubber capacitors C2and C3are connected in parallel across the drain and source terminals of the N-FET N1and P-FET P1, respectively. These lossless snubber capacitors C2and C3reduce the turn-off losses of the N-FET N1and the P-FET P1by limiting the voltage across the N-FET N1and the P-FET P1to a voltage VCRacross the reset capacitor CR. The snubber capacitors C2and C3may be implemented as discrete capacitors, the stray capacitances associated with the N-FET N1and the P-FET P1, or a combination of both. Additionally, diodes D1and D2are demonstrated as connected across the drain and source terminals of the N-FET N1and the P-FET P1, respectively. The diodes D1and D2are used, together with the reset capacitor CRand the magnetizing inductance of transformer56, to minimize turn-on losses of the N-FET N1and the P-FET P1. As an example, the N-FET N1and the P-FET P1can be implemented as MOSFETS, such that the body diodes of MOSFETS may be used for the diodes D1and D2. Alternatively, the diodes D1and D2can be implemented as discrete diodes.

The reset capacitor CR, in combination with the magnetizing inductance and the N-FET N1and the P-FET P1, automatically transfer the energy stored in the core of the transformer56back to the input voltage VINwhen the N-FET N1is turned off, as well as enable zero-voltage turn-on of the N-FET N1and the P-FET P1. In particular, once the N-FET N1is turned off, the energy stored in the core of the transformer56charges the reset capacitor CR, forward biasing the diode D2across the P-FET P1to enable the P-FET P1to turn on while the diode D2is conducting, which, in turn, enables the P-FET P1to be turned on at zero voltage. Once the P-FET P1is turned on, the energy stored in the core of the transformer56is automatically returned to the input voltage VIN. The reset capacitor CRalso forward biases the diode D1to enable turn on of the N-FET N1while the diode D1is conducting, thereby allowing the N-FET N1to be turned on at zero volts. As will be discussed in more detail below, the turn-off voltage stress across the N-FET N1and the P-FET P1is limited to the voltage VCRacross the reset capacitor CR.

As mentioned above, the transformer56includes dual secondary windings that can, for example, have an equal number of turns. The power stage54includes an N-FET N2and an N-FET N3that are coupled to the secondary winding of the transformer56and which are arranged as a self-driven synchronous rectifier stage. Particularly, the N-FET N2includes a drain that is coupled to a first end of the secondary winding of the transformer56and a source that is coupled to the low-voltage rail, and the N-FET N3includes a drain that is coupled to a second end of the secondary winding of the transformer56and a source that is coupled to the low-voltage rail. The N-FET N2includes a gate that is coupled to the second end of the secondary winding of the transformer56and a drain of the N-FET N3, and the N-FET N3includes a gate that is coupled to the first end of the secondary winding of the transformer56and a drain of the N-FET N2.

As described in greater detail herein, the N-FET N2and the N-FET N3are alternately activated and deactivated in response to respectively conducting a secondary current through the respective portions of the secondary winding of the transformer56. The secondary current is induced in response to the primary current I1flowing through the primary winding of the transformer56, and is provided through an LC low-pass filter formed by an output inductor LOUTand an output capacitor COUTto generate the output voltage VOUTat an output60. In the example ofFIG. 2, a feedback current IFBis provided from the output60to the feedback stage, such as the feedback stage18in the example ofFIG. 1, such as demonstrated in greater detail in the example ofFIG. 5. A freewheeling diode D3is connected across the input of the LC low-pass filter. The freewheeling diode D3in combination with the N-FET N2and the N-FET N3keeps the load current flowing through the secondary winding during the transition time of the N-FET N1and P-FET P1.

During a first switching phase, the N-FET N1is activated by the gate driver52, while the diode D1is conducting, as will be discussed in more detail below. Once the N-FET N1is turned on, the current I1flows from the input voltage VINthrough the primary winding of the transformer56, the drain and source terminals of the N-FET N1and back to the low-voltage rail. As will be discussed in more detail below, the N-FET N1is turned on while the diode D1is conducting, resulting in essentially a zero-voltage turn-on for the N-FET N1, thus mitigating switching losses associated with the turning-on of the N-FET N1. After the N-FET N1is turned on, the electrical current through the primary winding of the transformer56linearly ramps up as a function of the magnetizing inductance of the primary winding of the transformer56.

During the first switching phase, energy is transferred from the primary winding of the transformer56to the secondary winding of the transformer56and, in turn, to the load connected across the capacitor COUT. Also during the first switching phase, the N-FET N3is activated to conduct the secondary current from ground through the N-FET N3and through the second portion of the secondary winding of the transformer56, to the output inductor LOUT, and to the load. As the secondary current flows through the N-FET N3, the voltage at the drain of the N-FET N3, and thus the gate of the N-FET N2, increases.

Immediately after the N-FET N1is turned off, the switching power converter circuit50enters a soft transition mode. In this mode, the freewheeling diode D3allows for soft switching of the N-FETs N2and N3. In particular, immediately after the N-FET N1is turned off (during the dead time before the P-FET P1is turned on) the voltage across the primary winding of the transformer56transitions from positive to negative. During this period, the primary current I1through the primary winding of the transformer56is positive. The primary current I1through the primary winding charges the reset capacitor CR, which, in turn, forward biases the diode D2connected across the P-FET P1, which allows the primary current I1to flow through the diode D2. During this mode, the snubber capacitor C2, connected across the drain and source terminals of the N-FET N1, is slowly charged to a value VCR, equal to the voltage across the reset capacitor CR, thus limiting the voltage stress associated with the turn off of the N-FET N1.

While the voltage across the primary winding of the transformer56is greater than zero, the secondary current flows from the low-voltage rail, through the N-FET N3, through the second portion of the secondary winding of the transformer56, and through the output inductor LOUTto the load. Once the voltage across the primary winding drops below zero, the freewheeling diode D3causes electrical current to circulate through the freewheeling diode D3, through the output inductor LOUTand to the load. The increase in the gate voltage of the N-FET N2begins to activate the N-FET N2, which thus likewise begins to deactivate the N-FET N3. As a result, the secondary current begins to be diverted from the N-FET N3to the freewheeling diode D3. As the amplitude of the secondary current in the N-FET N3approaches zero, the N-FET N2becomes fully activated (e.g., saturation mode) and the N-FET N3becomes fully deactivated (e.g., cutoff mode). Therefore, the N-FET N3experiences substantially zero switching losses, and is thus soft-switched.

Once the P-FET P1turns on in a second switching phase, the primary current I1through the primary winding of the transformer56switches polarity. While the primary current I1is positive, the switching power converter circuit50operates in an auxiliary forward (“flyback”) mode corresponding to the second switching phase. In the second switching phase, the P-FET P1is turned on while the diode D2is conducting, realizing zero-voltage switching of the P-FET P1. Since the voltage across the primary winding is negative during this period, the N-FET N2conducts the secondary current from the low-voltage rail through the N-FET N2, through the first portion of the secondary winding of the transformer56, and through the output inductor LOUTto the load. As the secondary current flows through the N-FET N2, the voltage at the drain of the N-FET N2, and thus the gate of the N-FET N3, increases.

After the P-FET P1is turned off, the switching power converter circuit50again transitions to the first switching phase. As discussed above, a dead-time exists between the turn-off of the P-FET P1and the turn-on of the N-FET N1. During this deadtime, the voltage on the primary winding of the transformer56ramps up linearly to a positive value. Immediately after the P-FET P1is turned off, the primary current I1continues to flow from the low-voltage rail through the P-FET P1, the reset capacitor CR, through the primary winding, and back to the input voltage VIN. The primary current I1also flows from the low-voltage rail through the snubber capacitor C2, thereby discharging the snubber capacitor C2to allow the diode D1to turn on, which, in turn, enables the N-FET N1to be turned on at zero voltage during the first switching phase. Once the P-FET P1is turned off, the snubber C3limits the voltage across the P-FET P1to a voltage VCRcorresponding to the voltage across the reset capacitor CR.

Similar to as described previously, once the reverse polarity voltage across the primary winding drops below zero, the freewheeling diode D3causes electrical current to circulate through the freewheeling diode D3, through the output inductor LOUTand to the load. The increase in the gate voltage of the N-FET N3begins to activate the N-FET N3, which thus likewise begins to deactivate the N-FET N2. As a result, the secondary current begins to be diverted from the N-FET N2to the freewheeling diode D3. As the amplitude of the secondary current in the N-FET N2approaches zero, the N-FET N3becomes fully activated (e.g., saturation mode) and the N-FET N2becomes fully deactivated (e.g., cutoff mode). Therefore, the N-FET N3experiences substantially zero switching losses, and is thus soft-switched. Accordingly, the switching power converter circuit50can transition between the first and second switching phases with soft-switching of the N-FETs N2and N3, and thus providing self-driven rectification of the secondary current that is synchronous with the first and second switching phases.

The self-driven synchronous rectifier stage formed by the N-FETs N2and N3provides better efficiency of the switching power converter system50relative to typical switching power converters that implement diode rectification at the secondary winding of the transformer, such as described in U.S. Pat. No. 5,973,939. As an example, diode rectification may not be efficient enough for power processing and management at sub-volts, such as required by next-generation radio frequency (RF) and digital payloads for aerospace applications based on the diode forward-bias voltage drop forming a significant portion of the output voltage. However, the N-FETs N2and N3can have a very low channel resistance when fully activated (e.g., saturation mode), such as in the range of approximately less than ten milliohms. Accordingly, the N-FETs N2and N3can provide a significantly reduced voltage drop when activated, relative to the 0.7 volt drop of diodes or the 0.4 volt drop of Schottky diodes. Additionally, because the N-FETs N2and N3are activated by the secondary current flowing through each other and through the respective portions of the secondary winding of the transformer56based on the mutual gate coupling to the respective ends of the secondary winding, the N-FETs N2and N3are self-driven. As a result, the activation of the N-FETs N2and N3are synchronous with respect to the switching phases based on the activation of the N-FET N1and the P-FET P1to provide simplicity, efficiency, and automatic dead-time control over load and line changes.

FIG. 3illustrates an example of a power stage100. The power stage100can be implemented in any of a variety of applications that require generating a regulated output voltage VOUTbased on an input voltage VIN. As an example, the power stage100can correspond to a portion of the switching power converter system in the diagram10of the example ofFIG. 1.

The power stage100includes a switch stage102, which can be arranged substantially the same as the switch stage57in the example ofFIG. 2to conduct the current I1. In addition, the power stage100includes a transformer104having a single primary winding106and dual secondary windings108each with equal turns. The transformer104further includes a tertiary winding110that is magnetically coupled with the primary winding106. The polarities of the primary and secondary windings are as indicated by the dots inFIG. 3. The input voltage VINis likewise coupled to the primary winding of the transformer104over a capacitor C1.

As mentioned above, the transformer104includes dual secondary windings108each having an equal number of turns. The power stage100includes an N-FET N2and an N-FET N3that each interconnect a respective end of the secondary winding108of the transformer104(at a drain) and the low-voltage rail (e.g., ground, at a source). In the example ofFIG. 3, the N-FET N2has a gate that is coupled to a first end of the tertiary winding110via a resistor R1, and the N-FET N3has a gate that is coupled to a second end of the tertiary winding110via a resistor R2and a capacitor C4. Additionally, a zener diode DZ1and a damping resistor RD1interconnect the gate of the N-FET N2and the low-voltage rail, and a zener diode DZ2and a damping resistor RD2interconnect the gate of the N-FET N3and the low-voltage rail.

The arrangement of the tertiary winding110of the transformer104with respect to the gates of the N-FETs N2and N3provides that the N-FETs N2and N3are arranged as a self-driven synchronous rectifier stage. Particularly, the N-FET N2and the N-FET N3are alternately activated and deactivated in response to the tertiary winding110conducting a tertiary current I3. The tertiary current is induced in response to the primary current I1flowing through the primary winding106of the transformer104, such that the alternating direction of the primary current I1dictates the alternating direction of the tertiary current I3, with the alternating direction of the tertiary current providing for the alternating activation of the N-FETs N2and N3. Additionally, the damping resistors RD1and RD2provide for substantial mitigation of ringing that can occur in the switching of the N-FETs N2and N3.

As a result of the alternating activation of the N-FETs N2and N3, the secondary current is provided through an LC low-pass filter formed by an output inductor LOUTand an output capacitor COUTto generate the output voltage VOUTat an output112, similar to as described previously in the example ofFIG. 2. In the example ofFIG. 3, a feedback current IFBis provided from the output112to the feedback stage, such as the feedback stage18in the example ofFIG. 1, such as demonstrated in greater detail in the example ofFIG. 5. A freewheeling diode D3is connected across the input of the LC low-pass filter. The freewheeling diode D3in combination with the N-FET N2and the N-FET N3keeps the load current flowing through the secondary winding during the transition time of the N-FET N1and P-FET P1. The self-driven synchronous rectifier stage formed by the N-FETs N2and N3and the tertiary winding110of the transformer104therefore provides for another example of a more efficient switching power converter circuit relative to typical switching power converters that implement diode rectification at the secondary winding of the transformer.

FIG. 4illustrates an example of a power stage150. The power stage150can be implemented in any of a variety of applications that require generating a regulated output voltage VOUTbased on an input voltage VIN. As an example, the power stage150can correspond to a portion of the switching power converter system in the diagram10of the example ofFIG. 1.

The power stage150includes a switch stage152, which can be arranged substantially the same as the switch stage57in the example ofFIG. 2to conduct the current I1. In addition, the power stage150includes a transformer154having a single primary winding156and dual secondary windings158each with equal turns. The transformer154further includes a tertiary winding160that is magnetically coupled with the primary winding156. The polarities of the primary and secondary windings are as indicated by the dots inFIG. 4. The input voltage VINis likewise coupled to the primary winding of the transformer154over a capacitor C1.

As mentioned above, the transformer154includes dual secondary windings158each having an equal number of turns. The power stage150includes an N-FET N2and an N-FET N3that each interconnect a respective end of the secondary winding158of the transformer154(at a drain) and the low-voltage rail (e.g., ground, at a source). In the example ofFIG. 4, the N-FET N2has a gate that is coupled to a first end of the tertiary winding160via a resistor R1, and the N-FET N3has a gate that is coupled to a second end of the tertiary winding160via a resistor R2and a capacitor C4. Additionally, a zener diode DZ1and a damping resistor RD1interconnect the gate of the N-FET N2and the low-voltage rail, and a zener diode DZ2and a damping resistor RD2interconnect the gate of the N-FET N3and the low-voltage rail. Therefore, the arrangement of the tertiary winding160of the transformer154with respect to the gates of the N-FETs N2and N3provides that the N-FETs N2and N3are arranged as a self-driven synchronous rectifier stage based on activation via the tertiary current I3, similar to as described previously in the example ofFIG. 3. Accordingly, the alternating activation of the N-FETs N2and N3can provide the secondary current through the LC low-pass filter to generate the output voltage VOUTat an output162, similar to as described previously in the example ofFIG. 3. The self-driven synchronous rectifier stage formed by the N-FETs N2and N3and the tertiary winding160of the transformer154therefore provides for another example of a more efficient switching power converter circuit relative to typical switching power converters that implement diode rectification at the secondary winding of the transformer.

Furthermore, the power stage150includes a first shutoff transistor N4interconnecting the gate of the N-FET N2(at a drain) and the low-voltage rail (at a source), and a second shutoff transistor N5interconnecting the gate of the N-FET N3(at a drain) and the low-voltage rail (at a source). The shutoff transistors N4and N5have gates that are each coupled to a deactivation signal SD. In the example ofFIG. 4, the power stage150further includes a comparator164that is configured to compare a sense voltage VSNSwith a predetermined shutoff reference voltage VREF_SO. As an example, the sense voltage VSNScan be associated with an amplitude of the primary current I1, such as an absolute value amplitude, that is provided from the switch stage152. Therefore, in response to the gate driver (e.g., the gate driver12) ceasing the switching operation, and thus decreasing the amplitude of the primary current I1, the comparator164can assert the deactivation signal SD in response to the sense voltage VSNSdecreasing less than the predetermined shutoff reference voltage VREF_SO. As a result, the shutoff transistors N4and N5can activate to respectively deactivate the N-FETs N2and N3. For example, the comparator164can be a hysteretic comparator, such that the deactivation signal SD can be maintained for sufficient time to maintain activation of the shutoff transistors N4and N5. Additionally, any residual gate voltage amplitude of the N-FETs N2and/or N3can be dissipated via the shutoff transistors N4and/or N5to the low-voltage rail, or through the damping resistors RD1and/or RD2in the event of failure of the shutoff transistors N4and/or N5.

FIG. 5illustrates an example of a feedback stage200. The feedback stage200is configured to generate a feedback signal FB based on the output voltage VOUT. The feedback stage200can correspond to the feedback stage18in the example ofFIG. 1. Therefore, reference is to be made to the examples ofFIGS. 1-4in the following description of the example ofFIG. 5.

The feedback stage200includes an isolation transformer202that is configured to receive the feedback current IFB, such as provided from the output60of the power stage54, the output112in the example ofFIG. 3, or the output162in the example ofFIG. 4. The feedback current IFBis provided through a primary winding and through an N-channel isolation FET N6. The isolation FET N6is controlled by a feedback control signal FBCTLthat can periodically activate the isolation FET N6to provide the feedback current IFBas an AC current through the primary winding of the isolation transformer202. As an example, the feedback control signal FBCTLcan be provided from a controller, such as the gate driver52, or can be coupled to the secondary winding of the transformer56, such that the activation of the isolation FET N6can be substantially synchronous with the switching phases. The feedback stage200also includes a rectifier204formed by a diode D4in combination with an RC filter formed by a resistor R3and a capacitor C5. The isolation transformer202induces an AC secondary feedback current that is rectified by the rectifier204to provide a rectified feedback voltage VFBat an inverting input of an error amplifier206. The error amplifier206is configured to generate an error signal ER based on a difference in amplitude between the rectified feedback voltage VFBand a reference voltage VREFand based on compensation feedback, demonstrated at208.

In the example ofFIG. 5, the rectifier also includes an additional diode D5, an additional resistor R4, and an additional capacitor C6. The diode D5is demonstrated as arranged in parallel with the capacitor C6between the secondary winding of the isolation transformer202and the low-voltage rail (e.g., ground). Thus, the secondary winding of the isolation transformer202interconnects the parallel diode D5(at the anode) and capacitor C6and the anode of the diode D4. Additionally, the resistor R4interconnects the resistor R3and the reference voltage VREF. As an example, the resistors R3and R4can be fabrication-matched, such that the resistors R3and R4can be substantially identical and can exhibit substantially the same characteristics with respect to process and temperature variations. Similarly, the diodes D4and D5can be fabrication-matched, and the capacitors C5and C6can be fabrication-matched, and thus substantially identical with respect to each other, respectively.

Based on the fabrication matching of the resistors R3and R4, the diodes D4and D5, and the capacitors C5and C6, and based on the arrangement thereof, the rectifier204can provide temperature compensation in generating the error signal ER, and thus the feedback signal FB. Particularly, as described herein, the temperature compensation provided by the rectifier is such that any variations of the reference voltage VREFbased on changes in temperature are proportionally the same with respect to the rectified feedback voltage VFB. As a result, the error signal ER is substantially unaffected by variations in temperature, thus resulting in a feedback signal FB that is substantially unaffected by variations in temperature. Accordingly, the switching power converter circuit50can provide accurate regulation of the amplitude of the output voltage VOUTregardless of environmental considerations.

The error signal ER is provided through a diode D6and through a buffer210before being provided to at a node212that is coupled to a non-inverting input of a comparator214. The comparator214is configured to compare a voltage V1at the node212and a voltage V2at a node216that is coupled to the inverting input of the comparator214. The voltage V2is based on the primary current I1provided from the power stage52in the example ofFIGS. 2-4being provided through a resistor R5and a slope compensation voltage VSCprovided via a resistor R6. Therefore, the voltage V2is provided as a ramp voltage. The comparator214thus generates the feedback signal FB based on the comparison of the voltages V1and V2. Accordingly, the feedback signal FB defines the pulse-width modulation of the switching signals SW1and SW2, as generated by the gate driver52, to define the first and second switching phases corresponding to the respective activation of the N-FET N1and the P-FET P1, and thus the amplitude of the output voltage VOUT, as described previously.

The feedback stage200thus provides feedback with respect to the operation of the switching power converter circuit50, where the current and voltage loops are closed in an isolated manner. Particularly, by implementing the isolation transformer202and the isolation FET N6, the feedback stage200is configured as a “chopper” circuit that chops the output voltage VOUTand reconstructs it after crossing the isolation boundary formed by the isolation transformer202. Thus, the feedback stage200exhibits a more efficient and simplistic behavior relative to other isolation circuits, such as opto-isolators that are affected by ambient conditions and are more complex. Additionally, as described previously, the feedback stage200provides the feedback signal FB in a temperature-compensated manner to provide better regulation of the output voltage VOUT.

What have been described above are example embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the example embodiments, but one of ordinary skill in the art will recognize that many further combinations and permutations of the example embodiments are possible. Accordingly, the example embodiments are intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims.