HETEROJUNCTION CELL AND PROCESSING METHOD THEREFOR, AND BATTERY ASSEMBLY

A heterojunction cell and a processing method thereof, and a battery assembly are provided. The heterojunction cell includes a substrate, a TCO film layer is provided on both a front surface and a back surface of the substrate, and at least two columns of short main gates with the same number are disposed at intervals on the TCO film layer of both the front surface and the back surface of the substrate, the short main gates located on the front surface of the substrate are defined as first main gates; the short main gates located on the back surface of the substrate are defined as second main gates; and the substrate is capable of being cut to form battery slices, each of the battery slices is provided with one column of the first main gates and one column of the second main gates.

TECHNICAL FIELD

The present disclosure relates to a field of a photovoltaic, and in particular, to a heterojunction cell and a processing method of the heterojunction cell, and a battery assembly.

BACKGROUND

Policies have been issued to vigorously promote the development of photovoltaic industry to ease the energy crisis. In the last decade or so, with a rapid increase of a module power, various high-efficiency battery and module technologies have been applied rapidly.

At present, a highest industrialization efficiency of Passivated Emitter and Rear cell (PERC) is about 24.6%, while a highest industrialization efficiency of heterojunction solar cell and Tunnel Oxide Passivating Contacts solar cell (TOPCON) is 26.1% and 25.7% respectively. Coupled with advantages of heterojunction battery, such as high double-sided rate, low temperature coefficient, less production steps and high production yield, high-efficiency heterojunction battery module is undoubtedly important for the development of photovoltaic industry.

Currently, most solar cells on a market have main grids and fine grids on a front side and a back side, which are arranged in a grid-like way, and the main grids and the fine grids use silver paste as raw materials, which leads to a high consumption of the silver paste, thus increasing a battery cost.

SUMMARY

According to various embodiments of the present disclosure, a heterojunction cell and a processing method therefor, and a battery assembly are provided.

The present disclosure provides a heterojunction cell. The heterojunction cell includes a substrate, the substrate is provided with a front surface and a back surface, a TCO film layer is provided on both the front surface and the back surface of the substrate (TCO: Transparent Conductive Oxide), and at least two columns of short main gates with the same number are disposed at intervals on the TCO film layer of both the front surface and the back surface of the substrate. The at least two columns of short main gates located on a side of the substrate adjacent to the front surface of the substrate are defined as first main gates, the at least two columns of short main gates located on a side of the substrate adjacent to the back surface of the substrate are defined as second main gates.

The substrate is capable of being cut to form at least two battery slices, each of the at least two battery slices includes two long edges opposite to each other and two short edges opposite to each other.

Each of the at least two battery slices is provided with one column of the first main gates and one column of the second main gates, wherein the one column of the first main gates is arranged adjacent to one of the two long edges of each of the at least two battery slices, and the one column of the second main gates is arranged adjacent to the other of the two long edges of each of the at least two battery slices.

In some embodiments, each of the at least two columns of short main gates is perpendicular to the two long edges of each of the at least two battery slices.

In some embodiments, a size of each of the at least two columns of short main gates along a direction of the two short edges of each of the at least two battery slices is in a range of 0.3 mm to 1.5 mm.

In some embodiments, the number of the second main gates is the same as the number of the first main gates, the second main gates correspond to the first main gates respectively one by one, and a projection of each of the second main gates on the front surface of the substrate and a projection of corresponding one of the first main gates on the front surface of the substrate is in the same line, which is perpendicular to the long edges of each of the at least two battery slices.

In some embodiments, the number of short main gates in each column of the at least two columns of short main gates is in a range 4 to 25.

In some embodiments, the substrate is in a square shape or a square shape with chamfers on four edges.

The present disclosure further provides a processing method of a heterojunction cell including following steps:providing a substrate, the substrate is provided with a front surface and a back surface, and a TCO film layer is provided on both the front surface and the back surface of the substrate;,disposing at least two columns of short main gates with the same number at intervals on the TCO film layer of both the front surface and the back surface of the substrate by printing, wherein the at least two columns of short main gates located on a side of the substrate adjacent to the front surface of the substrate are defined as first main gates, the at least two columns of short main gates located on a side of the substrate adjacent to the back surface of the substrate are defined as second main gates;cutting the substrate into at least two battery slices, each of the at least two battery slices comprises two long edges opposite to each other and two short edges opposite to each other,wherein each of the at least two battery slices is provided with one column of the first main gates and one column of the second main gates, wherein the one column of the first main gates is arranged adjacent to one of the two long edges of each of the at least two battery slices, and the one column of the second main gates is arranged adjacent to the other of the two long edges of each of the at least two battery slices.

The present disclosure further provides a battery assembly including a plurality of cells and a plurality of welding tapes. The plurality of cells are battery slices formed by cutting a heterojunction cell. Two ends of each of the plurality of welding tapes are respectively connected with the one column of the first main gates of one of adjacent two of the at least two battery slices and the one column of the second main gates of the other one of adjacent two of the at least two battery slices to connect the plurality of cells in series.

Details of one or more embodiments of this application are presented in the attached drawings and descriptions below. And other features, purposes and advantages of this application will become apparent from the description, drawings and claims.

In the figures,1represents a heterojunction cell;10represents a substrate;101represents a front surface;102represents a back surface;10′ represents a battery slice;103represents a long edge;104represents a short edge;20represents a TCO film layer;11represents a N-type monocrystalline silicon layer;12represents an intrinsic amorphous silicon layer;13represents a P-type amorphous silicon layer;30represents a short main gate;31represents a first main gate;32represents a second main gate;40represents a welding tape;50represents a cell;60represents a conductive adhesive;90represents a center line;91represents a first trisecting line; and92represents a second trisecting line.

DETAILED DESCRIPTION

Referring toFIG.1toFIG.3, the present disclosure provides a heterojunction cell. The heterojunction cell includes a substrate10, the substrate10with a front surface101and a back surface102. A TCO film layer20is provided on both the front surface101and the back surface102of the substrate, and at least two columns of short main gates30with same number are disposed at intervals on the TCO film layer20of both the front surface101and the back surface102of the substrate10. The at least two columns of short main gates30located on a side of the substrate10adjacent to the front surface101of the substrate10are defined as first main gates31, the at least two columns of short main gates30located on a side of the substrate10adjacent to the back surface102of the substrate10is defined as second main gates32. In other words, the short main gates30includes a plurality of first main gates31located on the front surface101of the substrate10and a plurality of second main gates32located on the back surface102of the substrate10.

Referring toFIG.4toFIG.5, the substrate10is capable of being cut to form at least two battery slices10′, each of the at least two battery slices10′ includes two long edges103opposite to each other and two short edges104opposite to each other.

Each of the at least two battery slices10′ is provided with one column of the first main gates31and one column of the second main gates32. The one column of the first main gates31is arranged adjacent to one of the two long edges103of each of the at least two battery slices10′, and the one column of the second main gates104is arranged adjacent to the other of the two long edges103of each of the at least two battery slices10′. In this way, it is convenient to connect the first main gates31of one battery slice10′ with the second main gates32of adjacent battery slice10′ by a welding tape, thus facilitating a confluence transmission of charge carriers.

In the heterojunction cell provided by the present disclosure, since the front surface101and the back surface102of the substrate10are both provided with the TCO film layer20and the TCO film layer20has greater conductivity, the charge carriers can be collected through the TCO film layer20. Thereby, the charge carriers can be collected in the short main gate30and then transmitted by the welding tape40.

In the related art, main grids and fine grids are arranged on a front surface and a back surface of a battery slice, a projection of each of the main grids of the front surface on the battery slice and projections of corresponding one of the main grids of the back surface on the battery slice overlap, and the fine grids are vertically connected with the main grids and form a grid-like structure, which leads to more consumption of silver paste. However, the heterojunction cell in the present disclosure is only provided with the short main gates30, omitting the fine grids, the short main gates30includes the first main gates31and the second main gates32, a projection of each of the second main gates32on the front surface101of the substrate10does not overlap with a projection of corresponding one of the first main gates31on the front surface101of the substrate10, and the first main gates31and the second main gates32are respectively arranged adjacent to the long edges103of the battery slice10′, which greatly reduces a consumption of the silver paste, thus reducing a cost.

The substrate10is a basic element of the heterojunction cell, which realizes unidirectional conduction by forming a p-n junction. Referring toFIG.1, in an embodiment, the substrate10includes a n-type monocrystal silicon layer11, an intrinsic amorphous silicon layer12arranged on both sides of the n-type monocrystal silicon layer11, and a p-type amorphous silicon layer13arranged on a surface of each of the intrinsic amorphous silicon layers12. The TCO film layer20is disposed on a surface of each of the p-type amorphous silicon layers13.

The TCO film layer20is a conductive film layer, which can collect the charge carriers and assemble them into the short main gate30. Moreover, the TCO film layer20is made of a transparent material which will not affect an irradiation of light on the substrate10. It can be seen that, by replacing the fine grid with the TCO film layer20and the short main gates30and reducing a length of the main grids, it can not only ensure a normal electrical performance of the cell50, but also reduce an amount of silver pastes.

In this embodiment, the short main gates30are perpendicular to the long edge103of the battery slice10′, that is, the first main gates31and the second main gates32are perpendicular to the long edges103of the battery slice10′. “The short main gates30are perpendicular to the long edges103of the battery slice10′” means that the short main gates30are perpendicular to the long edges103of the battery slice10′, but it does not mean that the short main gates30is connected to the long edges103of the battery slice10′. The short main gates30May be connected to one of the long edges103of the battery slice10′, or it may not be connected to the two long edges103of the battery slice10′. As mentioned above, the first main gates31are located adjacent to one of the two long edges103of the battery slice10′, and the second main gates32are located adjacent to the other one of the two long edges103of the battery slice10′. In this embodiment, the first main gates31are arranged adjacent to one of the two long edges103of the battery slice10′ and extend toward the other one of the two long edges103of the battery slice10′, that is, the first main gates31are parallel to the short edge104of the battery slice10′. Similarly, the second main gates32are arranged adjacent to the other of the two long edges103of the battery slice10′ and extend towards the long edge103of the battery slice10′ where the first main gates31is arranged, that is, the second main gates32are parallel to the short edge104of the battery slice10′.

Referring toFIG.4, a length of the short main gate30along a direction of the short edge104is defined as L, and the length L of the short main gate30is in a range of 0.3 mm to 1.5 mm, so that the short main gates30have enough length to connect with the welding tape40, ensuring both a reliability of the connection between the cell50and the welding tape40and a collection and a transmission of the charge carriers, and decreasing a consumption of the silver paste and greatly reducing the cost. Specifically, the length L of the short main gates30can be 0.3 mm, 0.4 mm, 0.5 mm, 0.6 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1.0 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.4 mm, 1.5 mm, and so on, which are not listed here.

Referring toFIG.2andFIG.3, in an embodiment, the number of the second main gates32is the same as the number of the first main gates31, and the second main gates32correspond to the first main gates31respectively one by one. A projection of each of the second main gates32on the front surface101of the substrate10and a projection of corresponding one of the first main gates31on the front surface101of the substrate10is in the same line, which is perpendicular to the long edges103of each of the at least two battery slices10′. In this way, the first main gates31and the second main gates32can be conveniently connected through the welding tape40, so that a plurality of the battery slices10′ can be connected in series to form a battery assembly, and the connection of the welding tape40facilitates a transmission of the charge carriers. A projection of each of the second main gates32on the front surface101of the substrate10and a projection of corresponding one of the first main gates31on the front surface101of the substrate10is in the same line, which is perpendicular to the long edges103of each of the at least two battery slices10′, thus the short edges104of the battery slices10′ after series connection is in the same straight line.

The number of the short main gates30in each column is in a range of4to25, in this way, efficient collection of the charge carriers on the TCO film layer20can be ensured. Referring toFIG.2, the number of the short main gates30in each column is9. Of course, in other embodiments, the number of the short main gates30in each column can also be 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, and 25.

The substrate10is in a square shape or a square shape with chamfers on four edges. The substrate10is capable of being cut to form a battery slice10′ with a rectangular shape, and the battery slice10′ can be connected in series through the welding tape40.

The substrate10is provided with two opposite first edges and two opposite second edges, the first edge corresponds to the long edge103of the battery slice10′ and the second edge corresponds to the short edge104of the battery slice10′.

Referring toFIG.2andFIG.3, in this embodiment, the heterojunction cell can be cut to form two pieces of the battery slices10′ (i.e., two slices). Specifically, the first main gates31are arranged in two columns, the two columns of the first main gates31are arranged adjacent to a center line90of the second edge of the substrate10, and the two columns of the first main gate31are respectively located on both sides of the center line90of the second side of the substrate10. The second main gates32is also arranged in two columns, and the two columns of the second main gates32are respectively arranged adjacent to the two first edges of the substrate10. In this way, when the substrate10is cut along the center line90of the second side of the substrate10, the heterojunction cell is cut into two pieces of the battery slices10′. Referring toFIG.4toFIG.5, each of the two pieces of the battery slices10′ is provided with one column of the first main gates31and one column of the second main gates32. The one column of the first main gates31is located adjacent to a long edge103of one of two pieces of the battery slices10′, and the one column of the second main gates32is located adjacent to a long edge103of the other of two pieces of the battery slices10′. By connecting the first main gates31of one battery slice10′ and the second main gate32of adjacent battery slice10′ through the welding tape40, a plurality of the battery slices10′ can be connected in series to form the battery assembly. In this way, the battery assembly can collect more of the charge carriers and generate more electricity.

Referring toFIG.6toFIG.7, in this embodiment, the heterojunction cell can be cut to form three pieces of the battery slices10′ (i.e., three slices). Specifically, two trisecting line of the second edge of the substrate10are a first trisecting line91and a second trisecting line92, respectively. The first main gates31is arranged in three columns, wherein two columns of the first main gates31are arranged adjacent to the first trisecting line91, and the two columns of the first main gates31are located on both sides of the first trisecting line91. The other column of the first main gates31is located adjacent to the second trisecting line92and on a side of the second trisecting line92away from the first trisecting line91. The second main gates32are arranged in three columns, wherein two columns of the second main gates32are arranged adjacent to two first sides of the substrate10, the other column of the second main gates32is located adjacent to the second trisecting line92and on a side of the second trisecting line92adjacent to the first trisecting line91. In this way, by cutting the substrate10along the two trisecting line on the second side of the substrate10, the heterojunction cell can be cut into three battery slices. Each of the battery slices10′ is provided with one column of the first main gates31and one column of the second main gates32. The first main gate31is located adjacent to a long edge103of one battery slice10′, and the second main gate32is located adjacent to the long edges103of adjacent battery slice10′. By connecting the first main gate31of one battery slice10′ and the second main gate32of adjacent battery slice10′ through the welding tape40, a plurality of the battery slices10′ can be connected in series to form the battery assembly. In this way, the battery assembly can collect more of the charge carriers and generate more electricity.

The example of cutting the heterojunction cell in two cuts or three cuts is listed above. Similarly, the heterojunction cell can also be cut in four slices, five slices, six slices, seven slices, eight slices, nine slices, ten slices and so on. As long as each of the battery slices10′ obtained after cutting is provided with one column of the first main gates31and one column of the second main gates32. The situations of four slices, five slices, six slices, seven slices, eight slices, nine slices and ten slices will not be described in detail.

The present disclosure further provides a processing method of a heterojunction cell including following steps:providing a substrate10, the substrate10is provided with a front surface101and a back surface102, and a TCO film layer20is provided on both the front surface101and the back surface102of the substrate10;disposing at least two columns of short main gates30with the same number at intervals on the TCO film layers20of both the front surface101and the back surface102of the substrate10by printing, wherein the at least two columns of short main gates30located on a side of the substrate10adjacent to the front surface101of the substrate10are defined as first main gates31, the at least two columns of short main gates30located on a side of the substrate10adjacent to the back surface102of the substrate10are defined as second main gates32; andcutting the substrate10into at least two battery slices10′, each of the at least two battery slices10′ includes two long edges103opposite to each other and two short edges104opposite to each other;wherein each of the at least two battery slice10′ is provided with one column of the first main gates31and one column of the second main gates32, wherein the one column of the first main gates31is arranged adjacent to one of the two long edges103of each of the at least two battery slices10′, and the one column of the second main gates32is arranged adjacent to the other of the two long edge103of each of the at least two battery slices10′.

Referring toFIG.8toFIG.10, the present disclosure further provides a battery assembly including a plurality of cells50and a plurality of welding tapes40, the plurality of cells50are battery slices10′ formed by cutting a heterojunction cell described in the above embodiments. Two ends of each of the plurality of welding tapes40are respectively connected with the one column of the first main gates31of one of adjacent two cells50and the one column of the second main gates32of the other one of adjacent two cells50to connect the plurality of cells50in series. The battery assembly realizes the series connection of the plurality of cells50through the plurality of welding tapes40, so that the charge carriers are collected through the TCO film layer20and assembled into the first main gate31and the second main gate32, and transmitted through the plurality of welding tapes40.

In an embodiment, the welding tape40and the short main gate30are connected by a conductive adhesive60, that is, the welding tape40and the first main gate31are connected by the conductive adhesive60, and the welding tape40and the second main gate32are also connected by the conductive adhesive60. The conductive adhesive60has certain elasticity, the welding tape40is connected to the short main gate30through the conductive adhesive60, which can reduce a stress on the cell50caused by the connection of the welding tape40and reduce a fragment rate of the cell50, thereby ensuring a connection firmness between the welding tape40and the cell50, and ensuring a reliability of the battery assembly. Of course, in other embodiment, the welding tape40and the short main gate30can also be directly and fixedly connected, for example, by welding, which is not specifically described in the present disclosure.

Furthermore, the present disclosure further provides a packaging method of a battery assembly including following steps: S1, coating a conductive adhesive60on both ends of a welding tape40, wherein the conductive adhesive60is respectively located on both sides of the welding tape40, parts of the welding tape40coated with the conductive adhesive60are respectively connected to and in contact with the first main gate31of a cell50and the second main gate32of adjacent cell50; and, S2, heating and pressurizing a contact part of the welding tape40and the cell50to cure the conductive adhesive60. The battery assembly has a simple structure and a simple packaging method. The welding tape40and the cell50are connected by the conductive adhesive60, which has greater connection strength and will not cause concentrated stress, greatly reducing a fragment rate and ensuring a reliability and a quality of the battery assembly.

The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features are described in the embodiments. However, as long as there is no contradiction in the combination of these technical features, the combinations should be considered as in the scope of the present disclosure.

One of ordinary skill in the art should recognize that the above embodiments are used only to illustrate the present disclosure and are not used to limit the present disclosure, and that appropriate variations and improvements to the above embodiments fall within the protection scope of the present disclosure so long as they are made without departing from the substantial spirit of the present disclosure.