Operational context subspaces

A computer-implemented method for implementing a full space dynamic address translation (“DAT”) structure and a subspace DAT structure is provided. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space DAT structure and the subspace DAT structure is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled, and switches, by the processor, the context of the DAT structures based on determining that the new context is different from the existing context.

BACKGROUND

The present invention generally relates to memory access and more specifically, to operational context subspaces.

Dynamic address translation (DAT) tables are used to map virtual addresses to real addresses in a memory structure. Each address space has unique DAT tables and real page frames to back the virtual pages. DAT is the process of translating a virtual address during a storage reference into the corresponding real address. If the virtual address is already backed in central storage, the DAT process may be accelerated through the use of a translation lookaside buffer (TLB). If the virtual address is not backed in central storage, it is brought in from auxiliary storage. DAT is implemented by both hardware and software through the use of page tables, segment tables, region tables, and TLBs.

SUMMARY

Embodiments of the present invention are directed to a computer-implemented method for implementing a full space dynamic address translation (“DAT”) structure and a subspace DAT structure. A non-limiting example of the computer-implemented method includes determining, by a processor, that switching between the full space DAT structure and the subspace DAT structure is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on the bit in the control register indicating that switching is enabled, and switches, by the processor, the context of the DAT structures based on determining that the new context is different from the existing context.

Embodiments of the present invention are directed to a system for implementing a full space dynamic address translation (“DAT”) structure and a subspace DAT structure. A non-limiting example of the system includes a processor and a memory communicatively coupled to the processor. The memory has stored therein instructions that when executed cause the processor to determine that switching between the full space DAT structure and the subspace DAT structure is enabled by examining a bit in a control register. The instructions cause the processor to determine that there is a new context different from an existing context based on an instruction changing a program status word supervisor state bit or program key mask indicating that switching is enabled. The context of the DAT structures is switched based on determining that the new context is different from the existing context.

Embodiments of the invention are directed to a computer program product for implementing a full space dynamic address translation (“DAT”) structure and a subspace DAT structure. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a processor to cause the processor to perform a method. A non-limiting example of the method includes determining, by a processor, that switching between the full space DAT structure and the subspace DAT structure is enabled by examining a bit in a control register. The method determines, by the processor, that there is a new context different from an existing context based on an instruction changing a program status word supervisor state bit or program key mask indicating that switching is enabled, and switches, by the processor, the context of the DAT structures based on determining that the new context is different from the existing context.

DETAILED DESCRIPTION

In accordance with one or more embodiments of the present invention, an address space can be mapped to a subset of a common area used by other address spaces. One or more embodiments of the present invention are compared to contemporary systems where all address spaces sharing a common area must map the entire common area of the address space in the same way. This ability to map to a subset of the common area can result in improved system performance. One or more embodiments of the present invention can be used to allow more virtual memory to be used for private space or to limit access to some virtual memory locations.

Turning now to an overview of technologies that are more specifically relevant to aspects of the invention, an address space is the range of virtual addresses that an operating system (OS) assigns to a user or separately running program. The address space is typically an area of contiguous virtual addresses available for executing instructions and storing data. A virtual storage layout of an address space includes, among other things, a private area and a common area. The common area contains system control programs and control blocks including, for example, a prefixed storage area (PSA), a common service area (CSA), a pageable link pack area (PLPA), a fixed link pack area (FLPA), a modified link pack area (MLPA), a system queue area (SQA), and nucleus. Multiple address spaces can use the same common area. The private area contains, for example, a local system queue area (LSQA), a scheduler work area (SWA), and a private region for running programs and storing data. An address space is referenced by an address control element (ASCE) which is made up of the address of the highest level translation table for that address space.

Certain operating systems can activate fetch-protection-override, which causes fetch protection to be ignored for the first 2K virtual addresses (e.g., VSAs 0-2047). This allows execution in any key to read the first 2K of the PSA even though the frame is “fetch” protected. Key protection includes a two level protection structure, comprised of a supervisory level (key 0) and a non-supervisory level (keys 1-15). Supervisory programs can access non-supervisory assigned storage blocks, but the non-supervisory programs cannot access the supervisory assigned storage blocks. The second 2K (e.g., VSAs 2048-4095) of the first page of the PSA is protected from read access by non-key 0 programs.

An address space that is mapped to a subset of a common area used by other address spaces is referred to herein as a “partial address space” and an address space that maps to the entire common area is referred to herein as a “full address space. These address spaces can be used to control access to some storage such as those in an operational context subspace (OCS). Because all spaces do not fully map the common area, the common segment bit in the segment table entries must remain off. Otherwise, the hardware would detect an inconsistency and issue an error.

Prior addressing schemes would require that full address spaces and partial address spaces be built well in advance of their use, wasting precious computer resource time and energy. In addition, when address subspaces exist, complex methodologies needed to be used that would also take up critical computer resources.

One or more embodiments of the present invention address shortcomings of the prior art by providing a full address space and a subspace that is easily accessed through the use of a single bit in a control register. In this manner, one or more embodiments of the present invention provide easy, fast creation of address subspaces and allow for their quick access through the examination of a single control bit. Furthermore, faults are readily handled by one or more embodiments of the present invention. Thus, the invention dramatically improves computer functionality by more efficiently using computer resources. Additionally, no DAT path to memory is inaccessible, there are limited invocations of costly invalidate instructions, and it is transparent to applications.

Turning now to a more detailed description of aspects of the present invention,FIG. 1depicts a high-level block diagram computer system100, which can be used to implement one or more aspects of the present invention. More specifically, computer system100can be used to implement some hardware components of embodiments of the present invention. Although one exemplary computer system100is shown, computer system100includes a communication path155, which connects computer system100to additional systems (not depicted) and can include one or more wide area networks (WANs) and/or local area networks (LANs) such as the Internet, intranet(s), and/or wireless communication network(s). Computer system100and additional system are in communication via communication path155, e.g., to communicate data between them.

Computer system100includes one or more processors, such as processor105. Processor105is connected to a communication infrastructure160(e.g., a communications bus, cross-over bar, or network). Computer system100can include a display interface115that forwards graphics, text, and other data from communication infrastructure160(or from a frame buffer not shown) for display on a display unit125. Computer system100also includes a main memory110, preferably random access memory (RAM), and can also include a secondary memory165. Secondary memory165can include, for example, a hard disk drive120and/or a removable storage drive130, representing, for example, a floppy disk drive, a magnetic tape drive, or an optical disk drive. Removable storage drive130reads from and/or writes to a removable storage unit140in a manner well known to those having ordinary skill in the art. Removable storage unit140represents, for example, a floppy disk, a compact disc, a magnetic tape, or an optical disk, etc. which is read by and written to by removable storage drive130. As will be appreciated, removable storage unit140includes a computer readable medium having stored therein computer software and/or data.

In alternative embodiments, secondary memory165can include other similar means for allowing computer programs or other instructions to be loaded into the computer system. Such means can include, for example, a removable storage unit145and an interface135. Examples of such means can include a program package and package interface (such as that found in video game devices), a removable memory chip (such as an EPROM, or PROM) and associated socket, and other removable storage units145and interfaces135which allow software and data to be transferred from the removable storage unit145to computer system100.

Computer system100can also include a communications interface150. Communications interface150allows software and data to be transferred between the computer system and external devices. Examples of communications interface150can include a modem, a network interface (such as an Ethernet card), a communications port, or a PCM-CIA slot and card, etcetera. Software and data transferred via communications interface150are in the form of signals which can be, for example, electronic, electromagnetic, optical, or other signals capable of being received by communications interface150. These signals are provided to communications interface150via communication path (i.e., channel)155. Communication path155carries signals and can be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, an RF link, and/or other communications channels.

In the present description, the terms “computer program medium,” “computer usable medium,” and “computer readable medium” are used to generally refer to media such as main memory110and secondary memory165, removable storage drive130, and a hard disk installed in hard disk drive120. Computer programs (also called computer control logic) are stored in main memory110and/or secondary memory165. Computer programs can also be received via communications interface150. Such computer programs, when run, enable the computer system to perform the features of the present invention as discussed herein. In particular, the computer programs, when run, enable processor105to perform the features of the computer system. Accordingly, such computer programs represent controllers of the computer system.

FIG. 2depicts an updated dynamic address translation (“DAT”) structure200according to embodiments of the present invention. The updated DAT structure200includes a full space (or full DAT)205and a subspace245. The subspace245is also known as the alternate table. The full space205includes a region third table R3210, a segment table SGT220, and a page table PGT230. Entries in the region third table R3210each may point to a segment table SGT220whose entries may each point to a page table PGT230whose entries may each point to a page frame240. The subspace245includes a region third table R3250, a segment table SGT260, and a page table PGT270. Entries in the region third table R3250point to entries in the segment table SGT260that points to entries in the page table PGT270that point to page frames240. A control register CR1202points to the region third table210or in some cases may point to higher level tables, such as region first (not shown) or region second (not shown). Millicode switches the control register CR1202between the full space205(as illustrated) and the subspace245(not illustrated). In certain embodiments, the size of the full space205is equal to the size of the subspace245. The subspace245is switched to when a level of authorization is lower than that required for access to the full space205. Certain pages, such as the illustrated page240b, are not accessible from the subspace245in this particular example.

FIG. 3depicts a flowchart of the hardware or firmware switching methodology according to embodiments of the present invention. For any instructions that can switch context (block310), a check is made, by processor105, to see if switching is enabled (block320). This may be enabled, for example, by having a bit in the control register CR0being turned on. If switching is not enabled, instruction flow continues referencing the full space205(block350). If switching is enabled, a check is made, by processor105, to determine if the new context is different from the current context (block330). If not, instruction flow continues referencing the currently accessed space (block350). If the new context is different than the current context, processor105switches to the updated DAT structure200for context (block340) and instruction flow continues (block350). In the context of this description, “switching” means changing the ASCE in CR1to point to the subspace top DAT table245or the converse (going back to the full space top DAT table).

FIG. 4depicts a flowchart of the software or operating system address space creation according to embodiments of the present invention. Upon creation of a new address space (block410), a check is made, by processor105, to determine if a subspace will be used in this new address space (block420). If so, the highest level DAT table is created, by processor105, for all contexts (block430). Entries in the top DAT table for all contexts are invalidated by processor105(block440). Processor105creates a lower full DAT table (block460), and the process of address space creation ends (block470).

If a subspace will not be used in this space (block420), the processor105creates a highest DAT table210only for full context (block450). The lower full DAT tables220and230are created by processor105(block460), and the process ends (block470).

FIG. 5depicts a flowchart of the software or operating system work unit dispatch according to embodiments of the present invention. Work units are threads or tasks, for example. When the work unit is dispatched by processor105at block510, a check is made, by processor105, to determine if a subspace will be used in this space (block520). If so, processor105enables a subspace bit in the control register CR0202(block530) and flow continues to block540. If not, processor105performs the rest of the dispatch normally (block540) and the process ends (block550).

FIG. 6depicts a flowchart of the software or operating system fault methodology according to embodiments of the present invention. When a DAT fault occurs (block610), processor105checks to determine if the faulter was using a subspace (block620). If not, fault processing is performed normally on the full DAT (block650). If the faulter was using the subspace245(block620), processor105checks to see if the DAT entry is valid in the full space DAT205(block630). When reaching block650from630, fault processing will validate normally in full and redrive the faulting instruction which will likely fault again in the subspace and next time move on to block640.

When faulter is using subspace and the DAT entry is valid in the full DAT, processor105makes a check to determine if the subspace245should have access to the data being accessed (block640). In an exemplary embodiment, the check is checking the authority, e.g., Program Status Word (“PSW”) supervisor state bit and program key mask, or it may be other things. For example, the check may be testing other bits in the control register to check for access or a bit in the DUCT. These could be set only when running certain types of transactions or while running in a Java Virtual Machine that should not have access to all data. If not, the fault ends in an error (block680). If so, the subspace245is built by processor105and pointed to the proper data page frame (block650). The faulting instruction is then redriven by processor105(block670).