Semiconductor integrated circuit and transmission device

A semiconductor integrated circuit includes a first signal transmission path and a second signal transmission path in parallel with each other, a first variable delay circuit provided on the first signal transmission path and configured to cause a first signal to be delayed by a first delay amount, a duty adjustment circuit provided on the first signal transmission path in series with the first variable delay circuit, and a second variable delay circuit provided on the second signal transmission path and configured to cause a second signal to be delayed by a second delay amount. The first delay amount is smaller than the second delay amount by a third delay amount corresponding to an amount of delay applied to the first signal by the duty adjustment circuit.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-050386, filed Mar. 18, 2019, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a semiconductor integrated circuit and a transmission device.

BACKGROUND

In a semiconductor integrated circuit in which a plurality of parallel delay paths are provided, different types of signals may be transferred along the plurality of delay paths. It is desirable that the delay amounts of the plurality of parallel delay paths be adjusted appropriately according to different signal types.

DETAILED DESCRIPTION

In general, according to an embodiment, a semiconductor integrated circuit includes a first signal transmission path and a second signal transmission path in parallel with each other, a first variable delay circuit provided on the first signal transmission path and configured to cause a first signal to be delayed by a first delay amount, a duty adjustment circuit provided on the first signal transmission path in series with the first variable delay circuit, and a second variable delay circuit provided on the second signal transmission path and configured to cause a second signal to be delayed by a second delay amount. The first delay amount is smaller than the second delay amount by a third delay amount corresponding to an amount of delay applied to the first signal by the duty adjustment circuit.

Hereinafter, a semiconductor integrated circuit according to an example embodiment will be described with reference to the accompanying drawings. Furthermore, this example embodiment is not intended to limit the present disclosure.

Embodiment

A semiconductor integrated circuit according to one embodiment may be used as a parallel interface for a semiconductor memory. For example, a semiconductor integrated circuit100is provided in the semiconductor device1illustrated inFIG. 1.FIG. 1is a diagram illustrating a configuration of the semiconductor device1including the semiconductor integrated circuit100. For example, the semiconductor device1includes a controller2and a semiconductor memory3. The controller2includes a control circuit4and a transmission device5. The transmission device5is electrically connected to the semiconductor memory3via terminals TMDQS, TMDQ1, TMDQ2, . . . , and TMDQ(N-1), and is able to transmit a plurality of signals to the semiconductor memory3via these terminals TMDQS, TMDQ1, TMDQ2, . . . , and TMDQ(N-1). The transmission device5includes a clock generation circuit6, an interface circuit7, and the semiconductor integrated circuit100, which serves as a parallel interface between the clock generation circuit6and the interface circuit7. Upon receiving a plurality of signals from the semiconductor integrated circuit100, the interface circuit7is able to transmit the plurality of signals to the semiconductor memory3via the terminals TMDQS, TMDQ1, TMDQ2. . . and TMDQ(N-1).

When used as a parallel interface, the semiconductor integrated circuit100has a configuration in which a plurality of delay paths PA-S, PA-1, PA-2, . . . , and PA-(N−1) between the clock generation circuit6and the interface circuit7are provided. These delay paths are provided in parallel to one another. In this context, N is any integer of 3 or more. Different types of signals may be transferred through the plurality of delay paths PA-S to PA-(N−1).

In the semiconductor memory3, such as a NAND-type flash memory, which performs an operation synchronized to a clock signal (also referred to as strobe signal), a clock signal phase-controlled with respect to data is needed. Therefore, the control circuit4previously adjusts a phase relationship between a strobe signal DQS and (N−1) bits of data DQ[1) to DQ[N−1], and then supplies the strobe signal DQS and pieces of data DQ[1] to DQ[N−1], as adjusted in phase relationship, to the semiconductor integrated circuit100. To transmit the strobe signal DQS and pieces of data DQ[1] to DQ[N−1] while maintaining the phase relationship therebetween, the semiconductor integrated circuit100performs bit slicing with use of reference clock signals CK0to CK(N−1). Bit slicing is processing of converting to binary data for data of respective path of parallel data (such as the strobe signal DQS and pieces of data DQ[1] to DQ[N−1]) on a bit-by-bit basis in synchronization with the reference clock signals CK0to CK(N−1). Therefore, it is desirable that amounts of delay of the plurality of delay paths PA-S to PA-(N−1) would be adjusted appropriately with respect to each other (for example, in such a way as to be approximately equal or within sufficient margins) and the parallel data would be transmitted to the interface circuit7while the appropriate phase relationship thereof is maintained.

However, among the plurality of delay paths PA-S to PA-(N−1), the delay path PA-S, which is a delay path for the strobe signal DQS, has a possibility of having a larger amount of delay than those of the delay paths PA-1to PA-(N−1) for the pieces of data DQ[1] to DQ[N−1]. For example, the semiconductor integrated circuit100includes a flip-flop circuit group110, a variable delay circuit group120, and a duty adjustment circuit130. The delay path PA-S goes through the flip-flop circuit group110, the variable delay circuit group120, and the duty adjustment circuit130. The delay paths PA-1to PA-(N−1) go through flip-flop circuits111in the flip-flop circuit group110and variable delay circuits121in the variable delay circuit group120, but not through the duty adjustment circuit130(seeFIG. 2). Therefore, the delay path PA-S has the possibility of having a larger amount of delay than those of the other delay paths PA-1to PA-(N−1) due to an amount of delay corresponding to characteristics of the duty adjustment circuit130.

In light of such, it might be considered that a dummy duty adjustment circuit (a duty adjustment circuit serving as a mirror of the duty adjustment circuit130) could be provided between the variable delay circuit group120for the other delay paths PA-1to PA-(N−1) and the interface circuit7. However, in such a case, the circuit size of the semiconductor integrated circuit100increases, so that the cost of the semiconductor integrated circuit100may also increase.

In the semiconductor integrated circuit100, the present embodiment equalizes the amounts of delay of a plurality of delay paths PA-S to PA-(N−1) by adjusting the amount of delay of the variable delay circuit121provided in the delay path PA-S to be smaller than the amounts of delay of the variable delay circuits121provided in the other delay paths PA-1to PA-(N−1).

Specifically, the semiconductor integrated circuit100is configured as illustrated inFIG. 2.FIG. 2is a diagram illustrating a configuration of the semiconductor integrated circuit100.

The semiconductor integrated circuit100includes, in addition to the flip-flop circuit group110, the variable delay circuit group120, and the duty adjustment circuit130, a delay control circuit140, which adjusts the amounts of delay of the variable delay circuit group120.

The flip-flop circuit111-S stores a strobe signal DQS, which is supplied from the control circuit4to a data terminal D, in synchronization with a clock signal CK0, which is supplied to a clock terminal CK, and then outputs the stored strobe signal DQS from an output terminal Q. The flip-flop circuit111-1stores data DQ[1], which is supplied from the control circuit4to a data terminal D, in synchronization with a clock signal CK1, which is supplied to a clock terminal CK, and then outputs the stored data DQ[1] from an output terminal Q. The flip-flop circuit111-2stores data DQ[2], which is supplied from the control circuit4to a data terminal D, in synchronization with a clock signal CK2, which is supplied to a clock terminal CK, and then outputs the stored data DQ[2] from an output terminal Q. Similarly, the flip-flop circuit111-(N−1) stores data DQ[N−1], which is supplied from the control circuit4to a data terminal D, in synchronization with a clock signal CK(N−1), which is supplied to a clock terminal CK, and then outputs the stored data DQ[N−1] from an output terminal Q.

Furthermore, the clock generation circuit6includes a phase-locked loop (PLL) circuit6aand a clock tree circuit6b. The PLL circuit6agenerates a plurality of clock signals CK0, CK1, . . . , and CK (N−1), and supplies the plurality of clock signals CK0, CK1, . . . , and CK(N−1) to the clock tree circuit6b. The clock tree circuit6bdistributes the plurality of clock signals CK0, CK1, . . . , and CK(N−1) to the plurality of flip-flop circuits111-S,111-1,111-2, . . . , and111-(N−1) in a branched manner. This enables the clock generation circuit6to supply the plurality of clock signals CK0, CK1, . . . , and CK(N−1) synchronized with each other to the plurality of flip-flop circuits111-S,111-1,111-2, . . . , and111-(N−1).

The variable delay circuit121-S applies the amount of delay D_S=a predetermined amount of delay D×n[S] (n[S]≤p and n[S] being any integer more than or equal to 1) to the strobe signal DQS supplied from the flip-flop circuit111-S, and then outputs the strobe signal DQS with the amount of delay D_S applied thereto. The variable delay circuit121-1applies the amount of delay D_1=the predetermined amount of delay D×n[1] (n[1]≤p) to the data DQ[1] supplied from the flip-flop circuit111-1, and then outputs the data DQ[1] with the amount of delay D_1applied thereto. The variable delay circuit121-2applies the amount of delay D_2=the predetermined amount of delay D×n[2] (n[2] p) to the data DQ[2] supplied from the flip-flop circuit111-2, and then outputs the data DQ[2] with the amount of delay D_2applied thereto. Similarly, the variable delay circuit121-(N−1) applies the amount of delay D (N−1)=the predetermined amount of delay D×n[N−1] (n[N−1] p) to the data DQ[N−1] supplied from the flip-flop circuit111-(N−1), and then outputs the data DQ[N−1] with the amount of delay D×n[N−1] applied thereto.

In the respective variable delay circuits121-S,121-1,121-2, . . . , and121-(N−1), as illustrated inFIG. 3, the amount of delay D×n[S], D×n[1], D×n[2], . . . , and D×n[N−1], respectively applied, are configured to be varied by control signals output from the delay control circuit140. The variable delay circuits121-S,121-1,121-2, . . . , and121-(N−1) have similar configurations and are, therefore, represented as a variable delay circuit121inFIG. 3.FIG. 3is a diagram illustrating a configuration of the variable delay circuit121.

The variable delay circuit121includes a delay chain60and a selector70. The delay chain60has a configuration in which a plurality of delay elements61-1to61-p(p being any integer more than or equal to 2) is connected in series. The delay elements61-1to61-phave mutually equivalent delay characteristics (for example, equal amounts of delay D).

The delay elements61-1to61-pin the delay chain60output, to the selector70, tap outputs TAP1to TAPp obtained by delaying an input signal ϕIN according to the number of delay elements from an input node from which the input signal ϕIN is input. For example, the delay element61-k, which is the k-th delay element from the input node (k being any integer more than or equal to 1 and less than or equal to p), outputs, to the selector70, a tap output TAPk obtained by delaying the input signal ϕIN with the amount of delay D×k.

The selector70selects one of a plurality of tap outputs TAP1to TAPp output from the plurality of delay elements61-1to61-paccording to a select signal ϕSEL supplied from the delay control circuit140, and then outputs an output signal ϕϕUT having a desired amount of delay Dtotal.

Here, the select signal ϕSEL can be set as a signal indicating the number of taps corresponding to the amount of delay. More specifically, the select signals can be set as ϕSEL=n[S], n[1], n[2], . . . , and n[N−1] with respect to the amounts of delay D×n[S], D×n[1], D×n[2], . . . , and D×n[N−1], respectively, which are applied to the respective variable delay circuits121-S,121-1,121-2, and121-(N−1).

Referring back toFIG. 2, the duty adjustment circuit130includes a duty cycle adjuster (DCA)131. The DCA131is provided on the delay path PA-S.

The DCA131makes adjustment of duty ratio to the strobe signal DQS supplied from the variable delay circuit121-S, and then outputs the strobe signal DQS subjected to adjustment. In the DCA131, as illustrated inFIG. 4, the amount of adjustment of duty ratio is configured to be varied by a select signal ϕDUTY output from the delay control circuit140.FIG. 4is a diagram illustrating a configuration of the DCA131in the duty adjustment circuit130.

The DCA131includes a delay chain160, a selector170, a delay element261, a selector1311, an AND gate1312, and an OR gate1313. The delay chain160has a configuration in which a plurality of delay elements161-1to161-pis connected in series. The delay elements161-1to161-phave mutually equivalent delay characteristics (for example, equal amounts of delay D) and have delay characteristics equivalent to those of the respective delay elements61-1to61-p(seeFIG. 3) of each variable delay circuit121(for example, equal amounts of delay D). Thus, a delay block180including the delay chain160and the selector170has a circuit configuration equivalent to the variable delay circuit121(seeFIG. 3).

The delay element261has a delay characteristic equivalent to each of the delay elements161-1to161-p(an equal amount of delay D) and has a delay characteristic equivalent to each of the delay elements61-1to61-p(seeFIG. 3) (an equal amount of delay D). The amount of delay which is applied by the delay element261(for example, the amount of delay D) corresponds to the minimum amount of delay in the DCA131.

The select signal ϕDUTY is supplied to each of the selector170and the selector1311. The AND gate1312calculates a logical product between a signal obtained by the delay element261applying the amount of delay D to the input signal ϕIN and an output of the delay block180, and outputs a result of the calculation to the selector1311. The OR gate1313calculates a logical sum between a signal obtained by the delay element261applying the amount of delay D to the input signal ϕIN and an output of the delay block180, and outputs a result of the calculation to the selector1311.

According to the select signal ϕDUTY supplied from the delay control circuit140, the selector1311selects a result of the calculation performed by the AND gate1312when the rising edge of the input signal ϕIN is to be selectively delayed for duty ratio adjustment, and selects a result of the calculation performed by the OR gate1313when the falling edge of the input signal ϕIN is to be selectively delayed for duty ratio adjustment.

Referring back toFIG. 2, the delay control circuit140adjusts the amount of delay D×n[S] of the variable delay circuit121-S provided in the delay path PA-S to be smaller than the amounts of delay D×n[1], D×n[2], . . . , and D×n[N−1] of the variable delay circuits121-1to121-(N−1) provided in the other delay paths PA-1to PA-(N−1).

The delay control circuit140adjusts the amount of delay D×n [ S] to be smaller than the amounts of delay D×n [1], D×n[2], and D×n[N−1] with the amount of delay corresponding to the characteristic of the DCA131(for example, the minimum amount of delay D of the DCA131). For example, when performing adjustment to D×n[1]=D×n[2]= . . . =D×n[N−1]=D×m (m being any integer more than or equal to 2), the delay control circuit140can perform adjustment to D×n[S]=D×(m−1). This enables making the amounts of delay of a plurality of delay paths PA-S to PA-(N−1) approximately equal.

Furthermore, in a case where there is a variation between predetermined amounts of delay D which are applied by the respective variable delay circuits121-S,121-1,121-2, . . . , and121-(N−1), the delay control circuit140can perform calibration in such a manner that the amounts of delay for the delay paths PA-S to PA-(N−1) become equal. In this case, the delay control circuit140is able to store the numbers of delay stages n[1], n[2], . . . , and n[N−1] set in the respective variable delay circuits121-S,121-1,121-2, . . . , and121-(N−1), as criteria for equalizing delays for the respective delay paths PA-S to PA-(N−1).

The configuration of the delay control circuit140for controlling the variable delay circuits121-S to121-(N−1) may be, for example, a configuration illustrated inFIG. 5.FIG. 5is a diagram illustrating a part of the configuration of the delay control circuit140. Furthermore, a portion of the delay control circuit140for controlling the duty adjustment circuit130is omitted inFIG. 5for illustration purposes.

The delay control circuit140includes a sequencer141, a measuring circuit142, a selector143, a calculation circuit144, a subtractor145, a selector146, selectors147-1to147-N, holding circuits148-1to148-N, selectors149-1to149-N, and application circuits151-1to151-N.

The sequencer141comprehensively controls various units of the delay control circuit140. For example, the sequencer141supplies a control signal ϕMS to the measuring circuit142. In response to the control signal ϕMS becoming at active level, the measuring circuit142determines an instruction for calculating the number of taps per unit amount of angle delay being received and thus starts such a calculation. The measuring circuit142, which includes a ring oscillator, generates a unit number-of-taps signal ϕUT, which indicates the number of taps per unit amount of angle delay, and then supplies the unit number-of-taps signal ϕUT to the calculation circuit144. Furthermore, the measuring circuit142may also be, instead of the ring oscillator, a circuit which obtains the number of taps for 360 degrees with use of a delay element having a length exceeding one period, a phase comparator, and a phase comparison sequencer.

The selector143receives, from the control circuit4(seeFIG. 1), the amounts of angle delay ANG[1] to ANG[N], which are directed to the respective variable delay circuits121-S to121-(N−1). The sequencer141selects a variable delay circuit121targeted for calculation of the amount of delay to be set, and supplies a select signal ϕDLY indicating the selected variable delay circuit121to a control terminal of the selector143. The selector143selects the amount of angle delay ANG corresponding to the variable delay circuit121indicated by the select signal ϕDLY, and then outputs the selected amount of angle delay ANG to the calculation circuit144.

For example, in the case of the select signal ϕDLY=1, the selector143determines the variable delay circuit121-S being selected, and thus selects the amount of angle delay ANG[1] and then outputs the selected amount of angle delay ANG[1] to the calculation circuit144. For example, in the case of the select signal ϕDLY=2, the selector143determines the variable delay circuit121-1being selected, and thus selects the amount of angle delay ANG[2] and then outputs the selected amount of angle delay ANG[2] to the calculation circuit144.

The sequencer141supplies a control signal ϕCALC to the calculation circuit144. In response to the control signal ϕCALC becoming at active level, the calculation circuit144determines an instruction for calculating the number of taps equivalent to the amount of angle delay supplied from the selector143and thus starts such a calculation. More specifically, the calculation circuit144obtains the number of taps corresponding to the amount of angle delay ANG by multiplying the amount of angle delay ANG supplied from the selector143by the unit number of taps indicated by the unit number-of-taps signal ϕUT supplied from the measuring circuit142. The calculation circuit144supplies the calculated number of taps to the subtractor145and the selector146.

The subtractor145receives the number of taps corresponding to the amount of angle delay ANG from the calculation circuit144, and receives the number of taps ϕDT corresponding to the characteristic of the DCA131from the control circuit4(seeFIG. 1). The subtractor145subtracts the number of taps ϕDT corresponding to the characteristic of the DCA131from the number of taps corresponding to the amount of angle delay ANG, and supplies a result of the subtraction to the selector146.

For example, in a case where the number of taps corresponding to the amount of angle delay ANG is “3” and the number of taps ϕDT corresponding to the characteristic of the DCA131is “1”, which corresponds to the minimum amount of delay of the DCA131(seeFIG. 4), the subtractor145supplies “3−1=2” as a result of the subtraction to the selector146. At this time, the number of taps “3” is supplied from the calculation circuit144to the selector146. Furthermore, a circuit for clipping the number of taps output from the selector146may be provided between the selector146and the selectors147-1to147-N. The clipping circuit clips the number of taps output from the selector146in such a manner that the number of taps becomes within a range between the minimum number of taps and the maximum number of taps which are physically included in the variable delay circuit121.

The sequencer141generates a control signal ϕDCA indicating whether the selected variable delay circuit121corresponds to the delay path which goes through the DCA131, and then supplies the control signal ϕDCA to the selector146. For example, in a case where the variable delay circuit121-S is selected as a target for calculation, the sequencer141sets ϕDCA=1, and, in a case where any one of the variable delay circuits121-1to121-(N−1) is selected as a target for calculation, the sequencer141sets ϕDCA=0.

If ϕDCA=1, the selector146selects the number of taps indicating the result of the subtraction supplied from the subtractor145, and supplies the selected number of taps to the selectors147-1to147-N. If ϕDCA=0, the selector146selects the number of taps supplied from the calculation circuit144, and supplies the selected number of taps to the selectors147-1to147-N.

Until calculations by the calculation circuit144and the subtractor145are completed (for example, until the calculation for the number of taps is completed with respect to all or respective of the variable delay circuits121), the sequencer141supplies a control signal ϕCOMP=0 to control terminals of the respective selectors147-1to147-N. If the control signal ϕCOMP=0, the respective selectors147-1to147-N select outputs of the holding circuits148-1to148-N, and supply the selected outputs to input terminals of the respective holding circuits148-1to148-N. The sequencer141is able to recognize a calculation progress status which is supplied from the calculation circuit144to the selector146, and upon recognizing a result of calculation performed with respect to the last amount of angle delay ANG[N] being supplied from the calculation circuit144to the selector146, the sequencer141determines the calculations by the calculation circuit144and the subtractor145being completed. In response to the calculations by the calculation circuit144and the subtractor145being completed (for example, in response to the calculation of the number of taps of all of the variable delay circuits121being completed), the sequencer141sets a control signal ϕCOMP=1 and supplies the control signal ϕCOMP=1 to the control terminals of the respective selectors147-1to147-N. The respective selectors147-1to147-N supply the numbers of taps supplied from the selector146to the holding circuits148. This causes the latest results of calculation of the number of taps to be sequentially stored in the holding circuits148-1to148-N.

The numbers of taps stored in the holding circuits148-1to148-N are supplied to the respective selectors149-1to149-N. The selectors149-1to149-N receive, at respective control terminals thereof from the interface circuit7(seeFIG. 1), a select signal ϕIDLE indicating whether the interface circuit7is in an idle state (the semiconductor memory3is in a ready state). Each of the holding circuits148-1to148-N may be configured with, for example, a flip-flop.

If the select signal ϕIDLE=0, which indicates that the interface circuit7is not in an idle state (the semiconductor memory3is in a busy state), the respective selectors149-1to149-N select outputs of the application circuits151-1to151-N and then supply the selected outputs to input terminals of the application circuits151-1to151-N. Thus, the results of calculation of the numbers of taps are not applied to the variable delay circuits121-S to121-(N−1). Each of the application circuits151-1to151-N may be configured with, for example, a flip-flop.

If the select signal ϕIDLE=1, which indicates that the interface circuit7is in an idle state (the semiconductor memory3is in a ready state), the respective selectors149-1to149-N select the results of calculation of the numbers of taps supplied from the holding circuits148-1to148-N, and supply the selected results of calculation to the application circuits151-1to151-N. This causes the results of calculation of the numbers of taps to be applied to the variable delay circuits121-S to121-(N−1).

For example, in the above-mentioned example in which the number of taps corresponding to the amount of angle delay ANG is “3” and the number of taps ϕDT corresponding to the characteristic of the DCA131is “1”, which corresponds to the minimum amount of delay of the DCA131, the result of subtraction indicating the number of taps “2” is set to the variable delay circuit121-S, and the number of taps “3” is set to each of the other variable delay circuits121-1to121-(N−1).

As described above, in the semiconductor integrated circuit100, the present embodiment adjusts the amount of delay of a variable delay circuit provided in the delay path PA-S to be smaller than the amounts of delay of variable delay circuits provided in the other delay paths PA-1to PA-(N−1). This enables preventing or reducing an increase of the circuit size as compared with a case where dummy duty adjustment circuits are provided in the other delay paths PA-1to PA-(N−1), and also enables equalizing delays of a plurality of delay paths PA-S to PA-(N−1).