One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a low-clock-energy latch circuit that is fully static. The clock is only coupled to a first clock-activated pull-up or pull-down transistor and a second clock-activated pull-down or pull-up transistor. The level of the input signal is captured by a storage sub-circuit on one of the rising or the falling clock edge and stored to generate an output signal until the clock transitions. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled and disabled by the first clock-activated transistor and a propagation sub-circuit is activated and deactivated by the second clock-activated transistor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to digital latch circuits and more specifically to a low-clock-energy latch circuit that is fully-static.

2. Description of the Related Art

Power dissipation is a significant problem in conventional integrated circuits. In many applications, the performance of integrated circuit devices is limited by the amount of energy consumed by the circuitry implementing a function rather than by the die area of the circuitry. A large fraction of the power dissipated in conventional digital integrated circuits is consumed in the clock network. The amount of energy that is consumed by flip-flops due to data transitions is small because the activity factor, the fraction of time the data input of the flip-flop toggles, is quite low, typically about 5-10%. In contrast, the clock input load and clock energy is a particularly important metric for determining the energy that is consumed by the latches and flip-flops. Hence reducing the clock-switched capacitance by a given amount produces 10-20× the power savings compared with reducing the data-switched capacitance by the same amount.

Conventional latches are often built as a pass-gate latch with tri-state feedback to produce a static circuit. Such a design requires a local clocked inverter (or two) to produce both polarities of the clock and has two clock loads on each of the pass gate and the feedback gate giving a total clock load of six or eight transistor devices.

FIG. 1illustrates a conventional NOR latch100implemented with AND-OR-Invert (AOI) gates. The latch100is transparent when the clk (clock) input is high, so that the d input passes through to the q output. When the clk input is low the level of the d input is stored and q maintains the stored level of the d input at the q output. Each of the AND gates presents a clock load of two transistor gates, for a total clock load of four transistor devices.

FIG. 2illustrates a latch circuit200corresponding to the conventional latch100shown inFIG. 1. The total clock load presented to Clk220is four transistor devices. The total number of transistors is sixteen, where each of inverters222and224include two transistors.

Accordingly, what is needed in the art is a latch circuit that reduces the clock energy by reducing the capacitance of clock loads. Additionally, the latch circuit should function independent of fabrication process variations.

SUMMARY OF THE INVENTION

One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a low-clock-energy latch circuit that is fully static. The clock is only coupled to a first clock-activated pull-up or pull-down transistor and a second clock-activated pull-down or pull-up transistor. The level of the input signal is captured by a storage sub-circuit on one of the rising or the falling clock edge and stored to generate an output signal until the clock transitions. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled and disabled by the first clock-activated transistor and a propagation sub-circuit is activated and deactivated by the second clock-activated transistor.

Various embodiments of the invention comprise a low-clock-energy and fully-static latch circuit that includes a storage sub-circuit and a propagation sub-circuit. A clock signal is coupled only to a first clock-activated pull-up transistor and a second clock-activated pull-down transistor included in the low-clock-energy and fully-static latch circuit. The storage sub-circuit is configured to capture a level of an input signal when the clock signal transitions from high to low and hold the level to generate an output signal while the clock signal is low, where the first clock-activated pull-up transistor enables the storage sub-circuit when the clock signal is low and disables the storage sub-circuit when the clock signal is high. The propagation sub-circuit is configured to receive the input signal and propagate the level of the input signal to generate the output signal while the clock signal is high, where the second clock-activated pull-down transistor activates the propagation sub-circuit when the clock signal is high and deactivates the propagation sub-circuit when the clock signal is low.

One advantage of the disclosed latch circuit is that the transistor device load is reduced to only two transistor gates. Therefore the clock energy is reduced significantly compared with latch circuit having greater loads on the clock signal. The latch circuit is also completely static and does not rely on sizing relationships between the different transistors. Therefore, the latch circuit operation is robust, even when the characteristics of the transistors vary due to the fabrication process.

DETAILED DESCRIPTION

FIG. 3Aillustrates a low-clock-energy latch circuit300that is transparent when the clock signal, Clk320is high, according to one embodiment of the invention. The latch circuit300is a fully-static, clock-energy-efficient latch that presents only two loads to the clock and which does not depend on transistor device size ratios. With only two minimum sized clock loads, the latch circuit300should consume only a third or a quarter of the clock energy that is consumed by a conventional pass-gate latch. The total number of transistors included in the latch circuit300is sixteen, where each of inverters322and324include two transistors. Compared with the latch circuit200, having the same number of transistors, the loads on the clock are halved.

As shown inFIG. 3Atransistors301,302,303,304, and305are NMOS devices and transistors306,307,308,309,310,311, and312are PMOS devices. Transistors304,305,311, and312are configured as cross-coupled inverters that form a storage sub-circuit. A first inverter includes transistors311and304and a second inverter includes transistors312and305. The transistor306is a clock-enabled pull-up transistor that is configured to enable the storage sub-circuit by allowing current to flow from the supply voltage through either transistor311or312when the clock is low. The transistor306is shared between both inverters of the storage sub-circuit. Transistors302,303,307,308,309,310, and inverter322form propagation circuitry that passes the input signal d321to the output signal Q325. The inverter324isolates Q325from the storage feedback loop of the storage sub-circuit. When setup timing is not critical, synchronization performance is not important, and the load on the output Q325is low and static, inverter324may be omitted.

The transistor301is a clock-enabled pull-down transistor that is configured to activate the propagation circuitry to pass the input signal d321through to the output signal Q325when the clk320is high. Transistor301and transistor306are opposite polarities so that either the storage sub-circuit is enabled or the propagation circuitry is active in order to produce a fully-static circuit. Transistors311and312are isolation transistors327. The gate and drain of transistor311are tied in parallel with the gate and drain of transistor309. This duplication provides two source terminals, one on transistor311and one on transistor309that pull up sN315when s318is low. Splitting these source terminals isolates the drain of transistor307from the drain of the clock-enabled pull-up transistor306. Similarly, the gate and drain of transistor312are tied in parallel with the gate and drain of transistor310and transistor312is configured to isolate the drain of transistor308from the shared clock-enabled pull-up transistor306. Nodes x319and xN316are isolated from the shared clock-enabled pull-up transistor306by isolation transistors311and312. Including transistors309and310enables the isolation transistors311and312to share the clock-enabled pull-up transistor306. Without the isolation transistors311and312, and additional clock-enabled pull-up transistor would be required, increasing the clock load of the latch circuit300by 50%.

When the clk320is high transistors307and302act as an input inverter to drive the complement of input signal d321onto storage node sN315. Transistors303and308act as an inverter to drive the complement of dN323onto the storage node s318. Transistor309disables the pull-up of storage node sN315until the storage node s318has fallen in order to avoid a fight between transistors304and307. Similarly, the transistor310disables the pull-up of storage node s318until the storage node sN315has fallen in order to avoid a fight between transistors308and305.

While the clk320is high, the output signal Q325will follow the level of input signal d321as the input inverter formed by transistors307and302drives the complement of the level of input signal d321onto the storage node sN315and the input inverter formed by transistors308and303drives the level of input signal d321onto the storage node s318. When the clk320falls, the storage sub-circuit captures the level of input signal d321and holds the level to generate the output signal Q325while the clk320is low. While the clk320is low, the input inverters within the propagation sub-circuit (transistors307and302and transistors308and303) have no effect on the output signal Q325. The clock-activated pull-down transistor301is deactivated when the clk320is low, preventing the d input signal321from pulling down the storage node sN315. Pull-up of the low storage node sN315or s318is prevented by either transistor309or310, respectively.

FIG. 3Billustrates a low-clock-energy latch circuit350that is transparent when the clock signal, clk370is low, in accordance with one or more aspects of the present invention. Like the latch circuit300, the latch circuit350is also a fully-static, clock-energy-efficient latch that presents only two loads to the clock and which does not depend on transistor device size ratios. With only two minimum sized cloak loads, the latch circuit350should consume only a third or a quarter of the clock energy that is consumed by a conventional pass-gate latch. The total number of transistors included in the latch circuit350is sixteen, where each of inverters372and374include two transistors. Compared with the latch circuit200having the same number of transistors, the loads on the clock signal, Clk370are halved.

As shown inFIG. 3Btransistors351,352,353,354,355,359, and360are NMOS devices and transistors356,357,358,361, and362are PMOS devices. Transistors354,355,361, and362are configured as cross-coupled invertors that form a storage sub-circuit. A first inverter includes transistors361and354and a second inverter includes transistors362and355. The transistor351is a clock-enabled pull-down transistor, that is configured to enable the storage sub-circuit by allowing current to flow to ground through either transistor354or355when the clock is high. The transistor351is shared between both inverters of the storage sub-circuit. Transistors352,353,357,358,359,360, and inverter372form propagation circuitry that passes the input signal d371to the output signal Q375. The inverter374isolates Q375from the storage feedback loop of storage sub-circuit377. When setup timing is not critical, synchronization performance is not important, and the load on the output Q375is low and static, inverter374may be omitted.

The transistor356is a clock-enabled pull-up transistor that is configured to activate the propagation circuitry to pass the input signal d371through to the output signal Q375when the clk370is low. Transistor351and transistor356are opposite polarities so that either the storage sub-circuit is enabled or the propagation circuitry is active in order to produce a fully-static circuit. The gates of transistor360and transistor355are coupled to each other and to node sN365. Transistors354and355are isolation transistors377. The gate and drain of transistor354are tied in parallel with the gate and drain of transistor359and transistor354is configured to isolate the drain of transistor352from the shared clock-enabled pull-down transistor351. Similarly, the gate and drain of transistor355are tied in parallel with the gate and drain of transistor360and transistor355is configured to isolate the drain of transistor353from the shared clock-enabled pull-down transistor351. Nodes x369and xN366are isolated from the shared clock-enabled pull-down transistor351by the isolation transistors354and355. Including transistors359and360enables the isolation transistors354and355to share the clock-enabled pull-down transistor351.

When the clk370is low, transistors357and352act as an input inverter to drive the complement of input signal d371onto storage node sN365. Transistors353and358act as an inverter to drive the complement of dN373onto the storage node s368. Transistor359disables the pull-down of storage node sN365until the storage node s368has risen in order to avoid a fight between transistors361and352. Similarly, the transistor360disables the pull-down of storage node s368until the storage node sN365has risen in order to avoid a fight between transistors353and362.

While the clk370is low, the output signal Q375will follow the level of input signal d371as the input inverter formed by transistors357and352drives the complement of d371onto the storage node sN365and the input inverter formed by transistors358and353drives the level of input signal d371onto the storage node s368. When the clk370rises, the storage sub-circuit377captures the level of input signal d371and holds the level to generate the output signal Q375while the clk370is high. While the clk370is high, the input inverters within the propagation sub-circuit (transistors357and352and transistors358and353) have no effect on the output signal Q355. The clock-activated pull-up transistor356is deactivated when the clk370is high, preventing the d input signal371from pulling up the storage node sN365. Pull-down of the high storage node sN365or s368is prevented by either transistor359or360, respectively.

FIG. 4is a block diagram illustrating a flip-flop circuit500constructed using the low-clock-energy latch circuits300and350shown inFIGS. 3A and 3B, in accordance with one or more aspects of the present invention. A clock signal is input to the clk320input of the latch circuit300and clk370of the latch circuit350. Because latch350is transparent on clock low and latch300is transparent on clock high, a flip-flop can be realized without the need to invert the clock. The storage node s368from the latch circuit350is coupled to the input signal d321of the latch circuit300and the storage node sN365from the latch circuit350is coupled to the gate of transistor303of the latch circuit300(the inverter322may be omitted from the latch circuit300). The inverter374may be omitted from the latch circuit350.

FIG. 5is a block diagram illustrating a processor/chip540including the flip-flop circuit500fromFIG. 4, in accordance with one or more aspects of the present invention. I/O circuits565may include pads and other I/O specific circuits to send and receive signals from other devices in a system. Output signal555is produced by I/O circuits565based on signals received by the I/O circuits565. The input signal551is received by the I/O circuits565and is input to the first flip-flop circuit500for storage. The I/O circuits565also provide clock signals to the flip-flop circuits500. The combinational circuits570receive the output generated by the first flip flop circuit500and generate a combinational output that is received by the second flip-flop circuit500. The second flip-flop circuit500stores the combinational output and generates an output that is input to the combinational circuits572. The output of the combinational circuits572is received and stored by the third flip-flop circuit500. The third flip-flop circuit500generates an output that is provided to the I/O circuits565. The flip-flop circuits500may be used to store signals for multiple clock cycles or to pipeline signals that change as frequently as each clock cycle.

System Overview

FIG. 6is a block diagram illustrating a computer system100configured to implement one or more aspects of the present invention. Computer system600includes a central processing unit (CPU)602and a system memory604communicating via a bus path through a memory bridge605. Memory bridge605may be integrated into CPU602as shown inFIG. 6. Alternatively, memory bridge605, may be a conventional device, e.g., a Northbridge chip, that is connected via a bus to CPU602. Memory bridge605is connected via communication path606(e.g., a HyperTransport link) to an I/O (input/output) bridge607. I/O bridge607, which may be, e.g., a Southbridge chip, receives user input from one or more user input devices608(e.g., keyboard, mouse) and forwards the input to CPU602via path606and memory bridge605. A parallel processing subsystem612is coupled to memory bridge605via a bus or other communication path613(e.g., a PCI Express, Accelerated Graphics Port, or HyperTransport link); in one embodiment parallel processing subsystem612is a graphics subsystem that delivers pixels to a display device610(e.g., a conventional CRT or LCD based monitor). A system disk614is also connected to I/O bridge607. A switch616provides connections between I/O bridge607and other components such as a network adapter618and various add-in cards620and621. Other components (not explicitly shown), including USB or other port connections, CD drives, DVD drives, film recording devices, and the like, may also be connected to I/O bridge607. Communication paths interconnecting the various components inFIG. 6may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect), PCI-Express (PCI-E), AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol(s), and connections between different devices may use different protocols as is known in the art.

In one embodiment, the parallel processing subsystem612incorporates circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In another embodiment, the parallel processing subsystem612incorporates circuitry optimized for general purpose processing, while preserving the underlying computational architecture, described in greater detail herein. In yet another embodiment, the parallel processing subsystem612may be integrated with one or more other system elements, such as the memory bridge605, CPU602, and I/O bridge607to from a system on chip (SoC). One or more of CPU602, parallel processing sub-system612, I/O bridge607, and switch616may include a low-clock-energy latch circuit300or350or a low-clock-energy flip-flop circuit500.

It will be appreciated that the system shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, may be modified as desired. For instance, in some embodiments, system memory604is connected to CPU602directly rather than through a bridge, and other devices communicate with system memory604via memory bridge605and CPU602. In other alternative topologies, parallel processing subsystem612is connected to I/O bridge607or directly to CPU602, rather than to memory bridge605. In still other embodiments, one or more of CPU602, I/O bridge607, parallel processing subsystem612, and memory bridge605may be integrated into one or more chips. The particular components shown herein are optional; for instance, any number of add-in cards or peripheral devices might be supported. In some embodiments, switch616is eliminated, and network adapter618and add-in cards620,621connect directly to I/O bridge607.

In sum, the low-clock-energy latch circuit300or350reduces the transistor device load to only two transistor gates and is fully static. The clock energy is reduced significantly compared with latch circuit having greater loads on the clock signal. The latch circuit is completely static and does not rely on sizing relationships between the different transistors. Therefore, the latch circuit operation is robust, even when the characteristics of the transistors vary due to the fabrication process.