Semiconductor structure and method for manufacturing the same

The present disclosure provides a method for manufacturing a semiconductor structure. The method includes following operations. A plurality of fin structures and a plurality of trenches are formed over a semiconductor substrate, wherein the fin structures are spaced apart by the trenches, and the fin structures are covered by a mask layer. A dielectric layer is formed over the substrate, wherein the dielectric layer is in the plurality of trenches. The dielectric layer is annealed. A plurality of dopants in the dielectric layer are formed when the fin structures are covered by the mask layer.

BACKGROUND

As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance and lower costs, challenges from both fabrication and design issues have resulted in the development of three-dimensional designs, such as the fin field effect transistor (FinFET). FinFETs are fabricated with a thin “fin” or “fin structure” vertically extending from a substrate, and a gate electrode is formed over the fin. Thus, the channel of the FinFET is formed. However, following a series of manufacturing operations, the fin structure may have some structure losses and thus impacts the electron mobility in the channel.

DETAILED DESCRIPTION

Embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative and do not limit the scope of the disclosure.

In one or more embodiments, a plurality of dopants may be formed in the dielectric layer/isolation structure to alleviate the oxidation of the fin structures and improve the width of the fin structures to be wider. Consequently, the cross section of the fin structures may become larger. Since the electron mobility (unit: cm2/(V·s)) is proportion to the area of the cross section, the electron mobility may be enhanced. Further, the drain current of n-type/p-type MOS FinFET may be improved with the enhanced electron mobility.

Examples of devices that can benefit from one or more embodiments of the present disclosure are semiconductor devices such as, for example but not limited, a fin field effect transistor (FinFET) device. The FinFET device, for example, may be a complementary metal-oxide-semiconductor (CMOS) device including a p-type MOS FinFET device and an n-type MOS FinFET device. It is understood that the application should be not limited to a particular type of device, except as specifically claimed.

In some embodiments, to form a variety of planar and non-planar devices, the semiconductor substrate may include various doped regions depending on design requirements as known in the art (e.g., p-type wells or n-type wells). The doped regions are doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; or combinations thereof. The doped regions may be formed directly on the semiconductor substrate, in a P-well structure, in an N-well structure, in a dual-well structure, or on or within a raised structure. The semiconductor substrate may further include various active regions, such as regions configured for an N-type metal-oxide-semiconductor transistor device (NMOS) and regions configured for a P-type metal-oxide-semiconductor transistor device (PMOS).

Referring toFIG. 1,FIG. 1is a flowchart illustrating a method of manufacturing a semiconductor structure, in accordance with some embodiments of the present disclosure. In some embodiments, the method110includes operations111˜114. In an operation111, a plurality of fin structures and a plurality of trenches are formed over a semiconductor substrate. The fin structures are spaced apart by the trenches, and the fin structures are covered by a mask layer. In an operation112, a dielectric layer is formed over the semiconductor substrate. In an operation113, the dielectric layer is annealed. In an operation114, a plurality of dopants are formed in the dielectric layer when the fin structures are covered by the mask layer.

The method110is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, and after the method110, and some operations described can be replaced, eliminated, or moved around for additional embodiments of the method.

FIG. 2,FIG. 3,FIG. 4,FIG. 5,FIG. 6,FIG. 7,FIG. 8,FIG. 9, andFIG. 10, are cross sectional views of a semiconductor structure fabricated at various stages, in accordance with some embodiments of the present disclosure. Referring toFIG. 2and operation111inFIG. 1, the semiconductor substrate100is illustrated and the semiconductor substrate100is used to form a plurality of fin structures and a plurality of trenches. In some embodiments, the semiconductor substrate100may include an elementary semiconductor, such as silicon or germanium in a crystalline structure; a compound semiconductor, such as silicon germanium, silicon carbide (SiC), gallium arsenic (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide; or combinations thereof. In some embodiments, the substrate100is made of an alloy semiconductor such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), gallium arsenic phosphide (GaAsP), gallium indium phosphide (GaInP), or the like. In some embodiments, the semiconductor substrate100includes an epitaxial layer. For example, the semiconductor substrate100includes an epitaxial layer overlying a bulk semiconductor. In some embodiments, the semiconductor substrate100can include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

Referring toFIG. 2, the operation of forming the fin structures and the trenches is illustrated, but is not limited thereto. In some embodiments, a pad layer103, a mask layer104, and a photoresist layer105are formed over the semiconductor substrate100. The photoresist layer105may be patterned e.g., by photolithography to partially expose the mask layer104and the pad layer103. In some embodiments, the photoresist layer105may be removed after patterning of the mask layer104and the pad layer103and before the trench etching. In some embodiments, the photoresist layer105includes a photosensitive material that causes the photoresist layer105to undergo a property change when exposed to light. Alternatively, a photolithographic operation may be implemented, supplemented, or replaced by other methods such as maskless photolithography, electron-beam writing, and ion-beam writing.

Referring toFIG. 3, the pad layer103and the mask layer104may be recessed to expose the portions of the semiconductor substrate100. In some embodiments, the pad layer103may be a thin film formed of silicon oxide, for example, by using a thermal oxidation operation. The pad layer103may act as an adhesion layer between the semiconductor substrate100and the mask layer104. The pad layer103may also act as an etch stop layer for etching the mask layer104. In some embodiments, the mask layer104is formed of silicon nitride for example, using low-pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). The mask layer104is used as a hard mask during subsequent patterning operations.

Referring toFIG. 4, in some embodiments, in the etching operation of the trenches102, the semiconductor substrate100may be etched by various methods, including a dry etch, a wet etch, or a combination of dry etch and wet etch. In some embodiments, a wet cleaning operation may be performed to remove a native oxide of the semiconductor substrate100. The portions of the semiconductor substrate100between trenches102form the fin structures101.

Referring toFIG. 11,FIG. 11is a top view of the semiconductor substrate100fabricated at one stage, in accordance with some embodiments of the present disclosure. In some embodiments, the fin structures101may be arranged in strips parallel to each other, and closely spaced by the trenches102with respect to each other. In some embodiments, the width of the trenches102,102amay be different at various portion. For examples, the trench102amay be wider than the trench102. The different width of the trenches102,102amay cause the fin structures101asuffered different strain from two sides in the subsequent operations. Therefore, in some embodiments, the fin structure101aadjacent to the wider trench102amay have bending issue in the subsequent operations.

ReferringFIG. 5and the operation112inFIG. 1, the dielectric layer106is formed over the semiconductor substrate100. In some embodiments, the dielectric layer106is formed in the plurality of trenches102and over the fin structures101. In some embodiments, the dielectric layer106may be one or more isolation structures formed on the semiconductor substrate100to electrically isolate circuit devices such as the FinFET. In some embodiments, the dielectric layer106includes a shallow trench isolation (STI) structure.

In other embodiments, the dielectric layer106is a component of a silicon-on-insulator substrate. In some embodiments, the dielectric layer106takes the form of a buried oxide layer (BOX). In some embodiments, the dielectric layer106may include silicon oxide. In some embodiments, the dielectric layer106is made of, for example, silicon dioxide formed by LPCVD (low pressure chemical vapor deposition), plasma-CVD or flowable CVD. In the flowable CVD, flowable dielectric materials are deposited. Flowable dielectric materials, as their name suggests, can “flow” during deposition to fill gaps or spaces with a high aspect ratio. In some embodiments, various chemistries are added to silicon-containing precursors to allow the deposited film to flow. In some embodiments, nitrogen hydride bonds are added. Examples of flowable dielectric precursors, particularly flowable silicon oxide precursors, include a silicate, a siloxane, a methyl silsesquioxane (MSQ), a hydrogen silsesquioxane (HSQ), an MSQ/HSQ, a perhydrosilazane (TCPS), a perhydro-polysilazane (PSZ), a tetraethyl orthosilicate (TEOS), or a silyl-amine, such as trisilylamine (TSA). These flowable silicon oxide materials are formed in a multiple-operation. After the flowable film is deposited, it is cured and then annealed to remove un-desired element(s) to form silicon oxide. When the un-desired element(s) is removed, the flowable film densifies and shrinks. In some embodiments, multiple anneal operations are conducted. The flowable film is then cured and annealed. In some embodiments, the trenches102may have a multi-layer structure.

Referring toFIG. 6, in some embodiments, after the forming of the dielectric layer106, a global planarization operation such as a chemical mechanical polishing (CMP) operation is performed to remove excessive portions of the dielectric layer106outside the trenches102. As shown inFIG. 6, using the mask layer104as a polishing stop layer, after the excessive portions of the dielectric layer106are removed by the CMP operation, the remaining dielectric layer106is converted to temporary isolation structure filling the trenches102.

ReferringFIG. 6and the operation113inFIG. 1, in some embodiments, the dielectric layer106is annealed. The annealing operation includes rapid thermal annealing (RTA), laser annealing operations, or other suitable annealing operations. In some embodiments, the annealing of the dielectric layer106includes recrystallizing the dielectric layer106and grain growth occurred in the dielectric layer106. The annealing operation may densify and harden the isolation structure of the dielectric layer106, and improve the quality of the dielectric layer106. In some embodiments, the annealing operation is performed by using RTA at a temperature in a range of about 900° C. to about 1045° C., but not limited thereto.

ReferringFIG. 7and the operation114inFIG. 1, in some embodiments, the plurality of dopants107are formed in the dielectric layer106when the fin structures102are covered by the mask layer104. In some embodiments, the dopants107are mainly formed in the dielectric layer106, and the mask layer104may block most of the dopants107from entering the fin structures101. In some embodiments, forming the dopants107in the dielectric layer106includes performing an ion implantation. In some embodiments, the dopants107includes group III A elements, group IV A elements, group V A elements, or a combination thereof. In some embodiments, the dopants107includes nitrogen dopants, carbon dopants, germanium dopants, silicon dopants, or a combination thereof. In some embodiments, the a material of the dopants107may be the same or different from a material of the dielectric layer106. In some embodiments, the dopants107formed in the dielectric layer106may provide tensile or compressive strength to the fin structures101.

In some embodiments, during the implantation of the dopants107, the dopants107may break the chemical bonds between the elements of the dielectric layer106. Alternatively, the dopants107may form different chemical bonds with the elements of the dielectric layer106. The broken chemical bonds or the formation of different chemical bonds may change the volume of the dielectric layer106. In some embodiments, as some chemical bonds being broken or different chemical bonds being formed in the dielectric layer106, the crystal structures in some portions of the dielectric layer106are altered. Consequently, the volume of the dielectric layer106may be expanded or deflated depending on the material of the dopants107.

In some embodiments, the volume of the dielectric layer106is expanded, and the dielectric layer106may provide a compressive strain to the fin structures101to mitigate the bending issue of the fin structures101. For examples, referring toFIG. 11, as described above, the fin structures101aon the outer region of the semiconductor substrate100adjacent to the wider trench102amay have bending issue. Consequently, the dielectric layer in the trenches102amay provide a compressive strain to the fin structures101ato mitigate the bending issue.

Further, referring toFIG. 7, in some embodiments, the dielectric layer106is made of, for example, silicon dioxide (SiO2), and the material of the dopants is, for example, nitrogen dopant. The nitrogen dopant may incorporate into silicon dioxide to turn the dielectric layer106to a nitrogen-containing silicon oxide dielectric layer. With the nitrogen-containing silicon oxide dielectric layer, the oxidation of the fin structures101may be alleviated in the post anneal operation. Consequently, the loss of the fin structures may be alleviated and the width W of the fin structures may be wider than the condition without the implantation. This is merely examples and are not intended to be limiting.

In some embodiments, different materials of the dopants107may be used to alleviate the oxidation of the fin structures101and improve the width W of the fin structures101. Consequently, the cross section of the fin structures101may become larger. Since the electron mobility (unit: cm2/(V·s)) is proportion to the area of the cross section, the electron mobility may be enhanced. Further, the drain current of n-type/p-type MOS FinFET may be improved with the enhanced electron mobility.

In some embodiments, the operation113of annealing the dielectric layer may be performed after the operation114of forming the plurality of dopants in the dielectric layer. In other words, the dielectric layer is not annealed before the forming of the dopants. In some embodiments, the annealing of the dielectric layer after the implantation includes recrystallizing the dielectric layer and the dopants. As described above, the annealing operation may densify and harden the structure of the dielectric layer and improve the quality of the dielectric layer. The orders of the annealing of the dielectric layer and the forming of the dopants are merely examples and are not intended to be limiting.

Referring toFIG. 7andFIG. 12,FIG. 12is the doping profile of the dopants in the dielectric layer by different implantation energy, in accordance with some embodiments of the present disclosure. The dopants107may be implanted deeper with higher implantation energy. In some embodiments, the depth D (as shown inFIG. 7) corresponding to the fin structures101is, but not limited to, at a range about 200 A to about 780 A from the top surface106A to the bottom surface106B of the dielectric layer106. In some embodiments, the highest density of the dopants107in the dielectric layer106may be around middle portion of the dielectric layer106(e.g. L1inFIG. 12) and this may provide better effects to the fin structures101, e.g. alleviating the bending of the fin structures101. In some embodiments, a highest density of the dopants107in the dielectric layer106may be equal or lower than 2×1015/cm3. These are merely examples and are not intended to be limiting. For example, in some embodiments, the fin structure may have different height and thus the implantation energy may be variant, and the highest density of the dopants in the dielectric layer may also be different depending on the needs.

Referring toFIG. 7andFIG. 13,FIG. 13is the wafer bow test data of the semiconductor structure, in accordance with some embodiments of the present disclosure. In some embodiments, after the implantation of the dopants107, the semiconductor substrate100may bend in a direction D1the same with the bending direction after the forming of the dielectric layer106(the dotted line area shown inFIG. 13). In other words, the implantation of the dopants107may compensate the semiconductor substrate100's bow caused by the subsequent operations that may bend the substrate in a direction opposite to the direction D1.

Referring toFIG. 8, in some embodiments, a portion of the dielectric layer106in the trenches102is removed. In some embodiments, an etching operation is performed to etch the dielectric layer106to expose upper portions of the fin structures101. In some embodiments, the etched dielectric layer106forms the isolation structures. In some embodiments, the etched dielectric layer106may form as a shallow trench isolation (STI) structure. In some embodiments, the etching operation may include a dry etching operation, wet etching operation, or combination dry and wet etching operations to remove portions of the dielectric layer106. It is understood that the etching operation may be performed as one etching operation or multiple etching operations. In some embodiments, the mask layer (104, shown inFIG. 7) and the pad layer (103, shown inFIG. 7) may be removed after the recessing of the dielectric layer106.

In some embodiments, with the etching of the dielectric layer106, the doping concentration of the dopants107in the dielectric layer106becomes to gradually decreased from a top surface106A of the dielectric layer106to a bottom surface106B of the dielectric layer106. In some embodiments, depending on the etching depth of the dielectric layer106and the doping profile of the dopants, the doping concentration of the dopants107in the dielectric layer106may have different distribution.

In some embodiments, the upper portions of the fin structures101protruding over the top surfaces106A of the dielectric layer106are used to form an active area, such as a channel region, of the semiconductor device (e.g. FinFET device). The upper portions of the fin structures101may include top surfaces101A and sidewalls101B.

Referring toFIG. 8andFIG. 14,FIG. 14is the wet etching rate (WER) of the dielectric layer with/without the implantation, in accordance with some embodiments of the present disclosure. In some embodiments, the WER of the dielectric layer106with the implantation (e.g.11inFIG. 14) is lower than the dielectric layer without the implantation (e.g.12inFIG. 14). In some embodiments, the WER of the dielectric layer106with the implantation may have 40% reduction comparing to the dielectric layer without the implantation. In other words, the dielectric layer106with the implantation may have more densified structure and the implantation may improve the quality of the dielectric layer106.

In some embodiments, when the dielectric layer106is annealed before the forming of the dopants, a supplementary annealing operation may be performed after the forming of the dopants107. The supplementary annealing operation includes RTA, laser annealing operations, or other suitable annealing operations. In some embodiments, the supplementary annealing operation is performed by using RTA at a temperature in a range of about 900° C. to about 1045° C., but not limited thereto. In some embodiments, the annealing operation is performed by using RTA at a temperature about 950° C. to further improve the WER. The supplementary annealing operation may further densify and harden the structure of the dielectric layer106and improve the quality of the dielectric layer106after the implantation.

Referring toFIG. 9, in some embodiments, the gate dielectric layer108is formed over the fin structure101and the dielectric layer106. In some embodiments, the gate dielectric layer108is formed to cover the top surface101A and sidewalls101B of at least a portion of the channel region of the fin structures101. In some embodiments, the gate dielectric layer108includes one or more layers of silicon oxide, silicon nitride, silicon oxy-nitride, or high-k dielectrics. The gate dielectric layer108may be formed using a suitable operation such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), thermal oxidation, UV-ozone oxidation, or combinations thereof. The gate dielectric layer108may further include an interfacial layer (not shown) to reduce damage between the gate dielectric layer108and the fin structures101.

In some embodiments, an additional annealing operation may be performed after the gate dielectric layer108is formed. The additional annealing operation includes RTA, laser annealing operations, or other suitable annealing operations. In some embodiments, the additional anneal operation may further densify both the structure of the dielectric layer106with dopants107and the gate dielectric layer108, and also improve the quality of the dielectric layer106with dopants107and the gate dielectric layer108. In some embodiments, the additional annealing operation is performed by using RTA at a temperature in a range of about 900° C. to about 1045° C.

Referring toFIG. 10, in some embodiments, the gate electrode layer109is then formed on the gate dielectric layer108. In some embodiments, the gate electrode layer109covers the upper portion of more than one fin structures101. The gate electrode layer109may include a single layer or a multilayer structure. The gate electrode layer109may be formed using a suitable operation such as ALD, CVD, PVD, plating, or combinations thereof.

Referring toFIG. 10, the semiconductor structure1includes the semiconductor substrate100, the fin structure101disposed over the semiconductor substrate100, the isolation structure106disposed over the semiconductor substrate100at opposing sides of the fin structure101, and the plurality of dopants107in the isolation structure106. The semiconductor structure1serves only as one example. The semiconductor structure1and the method for manufacturing a semiconductor structure1may be used in various applications such as digital circuit, imaging sensor devices, a hetero-semiconductor device, dynamic random access memory (DRAM) cell, a single electron transistor (SET), and/or other microelectronic devices (collectively referred to herein as microelectronic devices). Aspects of the present disclosure are also applicable and/or readily adaptable to other type of transistor, including single-gate transistors, double-gate transistors, and other multiple-gate transistors, and may be employed in many different applications, including sensor cells, memory cells, logic cells, and others.

In one or more embodiments, the dopants formed in the dielectric layer/isolation structure may be alleviate the oxidation of the fin structures and improve the width of the fin structures to be wider. Consequently, the cross section of the fin structures may become larger. Since the electron mobility (unit: cm2/(V·s)) is proportion to the area of the cross section, the electron mobility may be enhanced. Further, the drain current of n-type/p-type MOS FinFET may be improved with the enhanced electron mobility.

Further, in one or more embodiments, the dopants formed in the dielectric layer/isolation structure may compensate the semiconductor substrate's bow caused by the subsequent operations. In one or more embodiments, the dopants formed in the dielectric layer/isolation structure may densify and harden the dielectric layer/isolation structure, and may improve the quality of the dielectric layer/isolation structure. Consequently, the WER of the dielectric layer/isolation structure with the implantation may be reduced comparing to the dielectric layer/isolation structure without the implantation.

According to one embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided. The method includes following operations. A plurality of fin structures and a plurality of trenches are formed over a semiconductor substrate, wherein the fin structures are spaced apart by the trenches, and the fin structures are covered by a mask layer. A dielectric layer is formed over the substrate, wherein the dielectric layer is in the plurality of trenches. The dielectric layer is annealed. A plurality of dopants in the dielectric layer are formed when the fin structures are covered by the mask layer.

According to another embodiment, a method for manufacturing a semiconductor structure is provided. The method includes following operations. A semiconductor substrate including a fin structure and a plurality of trenches at opposing sides of the fin structure is provided. A dielectric layer is formed in the plurality of trenches. A volume of the dielectric layer is expanded to compress the fin structure.

According to another embodiment, a semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, a fin structure disposed over the semiconductor substrate, an isolation structure disposed over the substrate at opposing sides of the fin structure, and a plurality of dopants in the isolation structure.