Programmable logic device for wireless local area network

Method and apparatus for a wireless local area network programmable logic device is described. More particularly, a field programmable gate array (FPGA) is coupled to memory having programming instructions for configuring the FPGA with a medium access layer selected from more than one type of medium access layers. A physical layer is hardwired or embedded on the FPGA, or a separate integrated circuit for the physical layer is used. Additionally, the memory comprises programming instructions for a baseband controller, and may include programming instructions for a baseband processor, for configuring the FPGA in accordance therewith. In this manner, a single physical layer may be used with an FPGA to provide a multi-platform application specific standard product (ASSP). This is especially advantageous for providing multi-platform devices for use in countries or applications where one or more standards may be employed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to programmable logic devices, and more particularly to programmable logic devices configured for wireless communication.

2. Description of the Related Art

Programmable logic devices exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic devices, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility and cost. An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.

Even though FPGAs are very flexible and can be used to implement many circuits, they have some performance limitations, such as longer signal delays and lower gate counts. These limitations hinder use of FPGAs on high-speed communication applications, namely, those communication applications with real-time processing of information. For these applications, application specific integrated circuits (ASICs) are generally used.

Unfortunately, communication circuits implemented as ASICs have several disadvantages. One such disadvantage is the time-to-market risks associated with the relatively long cycle time necessary for the implementation of a new ASIC design. An additional disadvantage of using ASICs for communication circuits is that ASICs are “hardwired” and thus conventionally are not reconfigurable for a new application or application upgrade.

Wireless Local Area Network (WLAN) radio technology comprising IEEE 802.11a and HiperLAN2 are two forms of next generation communication. The physical layer of both IEEE 802.11a and HiperLAN2 technologies is the same, namely, Orthogonal Frequency Division Multiplex (OFDM). However, the data link layer of each of these technologies is different. The data link layer comprises the medium access control (MAC) and logical link control layers. The physical layer defines electrical, mechanical and procedural specifications, which provide transmission of bits over a communication medium or channel. WLAN physical layer technologies include narrowband radio, spread spectrum and, with reference to the above-identified LAN technologies, OFDM. The logical link layer ensures error control and synchronization between physically connected devices communicating over a channel, and ensures priority determinations and allocations for access to such channel.

Both IEEE 802.11a and HiperLAN2 use a 5 GHz ISM (Industrial, Scientific, Medical) band. However, unknown future unification to a single standard, namely, either IEEE 802.11a or HiperLAN2, is causing concern among those deciding on which version of OFDM to implement in their products. In addition, nonconformance to a single standard is hampering benefits associated with economies of scale.

Accordingly, it would be desirable and advantageous to have available a programmable logic device which is capable of implementing either IEEE 802.11a or HiperLAN2.

SUMMARY OF THE INVENTION

Programmability facilitates interfacing to other interfaces, while a having a common interface hardwired or embedded facilitates communication between systems. Examples of hardwired interfaces include USB 1.1, USB 2.0, IEEE 1394, Ethernet, IEEE 802.11a and HiperLAN2, among others. A hardwired interface may exist outside of and/or internal to an FPGA, where such an FPGA may be programmed as a medium access control layer. Moreover, such an FPGA may be programmed as an interface layer between such a medium access control layer and a physical layer. For example, between Ethernet physical and medium access control layers conventionally there is a MII (Media Independent Interface). This facilitates user access to such an interface through programming an FPGA.

The present invention provides method and apparatus for a programmable integrated circuit that can be used to handle different communication specifications. More particularly, an aspect of the present invention is a subsystem for use in a wireless local area-networking device. The subsystem comprises of transceiver coupled to programmable gates. Memory is coupled to the programmable dates for storing instructions for programming a first portion of the programmable gates with a selected one of a first type of a medium access layer and a second type of a medium access layer. The first type of the medium access layer is different from the second type of medium access layer, though both the first type of the medium access layer and the second type of the medium access layer are compatible with the transceiver. The memory is configured for storing instructions for programming a second portion of the programmable gates as a baseband controller. Another aspect of the present invention is the aforementioned subsystem wherein the second portion of the programmable gates is further programmed as a baseband processor.

Another aspect of the present invention is a circuit board comprising a field programmable gate array. The field programmable gate array comprises configuration logic blocks and programmable input/output blocks. A radio is coupled to the programmable configuration logic blocks through the programmable input/output blocks. Program memory is coupled to the programmable configuration logic blocks through the programmable input/output blocks. Data memory is coupled to the programmable configuration logic blocks through the programmable input/output blocks. An interface transceiver is coupled to the programmable configuration logic blocks through the programmable input/output blocks. The program memory comprises programming instructions for the programmable configuration logic blocks to be configured as a radio interface and controller, a medium access control protocol engine and configuration controller, and a baseband processor interface.

Another aspect of the present invention is a method for providing a multi-platform wireless local area network. More particularly, a radio is provided along with programmable input/output blocks coupled thereto. Configuration logic blocks coupled to the programmable input/output blocks are provided. A plurality of medium access control layers compatible with the radio and configured to program the configuration logic blocks are stored. A first portion of the configuration logic blocks is selectively programmed with a medium access control layer from the plurality of medium access control layers. Another aspect of the present invention is the above method further comprising storing a plurality of encryption algorithms configured to program the configuration logic blocks, and selectively programming a second portion of a configuration logic blocks with an encryption algorithm selected from the plurality of encryption algorithms.

Another aspect of the present invention is a circuit board comprising transceiver means for receiving and transmitting information, and comprising configurable logic means coupled to the transceiver means for communication therewith. The configurable logic means are for programming as a medium access control layer selected from a plurality of medium access control layers.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention relates generally to programmable logic devices, and more particularly to programmable logic devices configured for wireless communication. In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one skilled in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail in order to avoid obscuring the present invention.

FIG. 1is a block diagram of a communication integrated circuit100of the present invention. Integrated circuit100contains two physical layer (PHY) components (102and104) that are connected to a signal line106. Signal line106provides a communication link between integrated circuit100and external data of a physical medium. Each PHY communicates with a media independent interface (MII) component108through a control and a data line. MII108is connected to a media access control (MAC) component110. MAC110is connected to processing component112, which is in turn connected to an interface component114. Interface component114is connected to a signal line118. Signal line118is connected to an external device (not shown), such as a universal serial bus (USB) compatible device.

In integrated circuit100, signal lines106and118are bi-directional lines receiving data from and delivering data to external sources. In the present invention, the data on signal line106conforms to a predetermined specification. One example is the HomePNA 2.0 specification, which is supported by the Home Phoneline Networking Alliance. This specification provides for data communication using regular telephone lines. Another example is the 10 Mbps Ethernet (IEEE 802.3) specification, which is supported by International Electrical and Electronic Engineers (IEEE). This specification provides for data communication between a plurality of devices on shared wires. A PHY interacts with a physical medium that conforms to one of these specifications. MII component108provides a common interface specification so that different PHYs can easily communicate with other components in integrated circuit100. MAC component110is concerned with media access issues, such as whether token passing or contention will be used. It typically includes authentication and encryption functionalities. The MAC is a sub-layer of the “data link control,” which is defined by the IEEE as the lower portion of the OSI reference model data link layer. The data to and from the MAC is processed by processing component112. For example, processing component112is used to implement higher layers of the reference model. Interface component114provides the physical signal and software drivers for integrated circuit100to interact with an external device in accordance with a predetermined protocol (such as USB and IEEE 1394).

In one embodiment of integrated circuit100, PHY102and104are fixed logic components embedded into a programmable logic fabric120. Fixed logic components allow high speed processing of data. This is useful for implementing the physical layers because they need to process tremendous amount of raw data in and out of the physical medium. The rest of the components (i.e., MII108, MAC110, processing component112, and interface component114) are preferably implemented using a programmable logic fabric120. One advantage is that any change in specifications of these components can be implemented easily in the environment of a programmable logic fabric.

In this embodiment, two PHY components and one MAC components are present in integrated circuit100(but note that more than two PHY components may be present if there is a need to do so). Each of the PHY components is able to process data in accordance with a predetermined protocol. For example, PHY102may conform to the HomePNA 2.0 specification while PHY104may confirm to the 10 Mbps Ethernet (IEEE 802.3) specification. It is observed that these two specifications define a MAC that is substantially the same. This observation is especially important in an implementation using field programmable gate array (FPGA). This is because FPGA allows a small portion of its programmable fabric to be changed without affecting the rest of the programmable fabric. This process is called “partial reconfiguration.” An example of partial reconfiguration is disclosed in an application note published in June, 2000, by Xilinx, Inc., the assignee of the present invention, as “Correcting Single-Event Upsets Through Virtex Partial Configuration.” As a result, the portion of MAC that is common to both specifications does not need to be changed after configuration. Only a small portion specific to each specification needs to be changed when integrated circuit100is switched from HomePNA to Ethernet. Alternatively, the specific portions of both specifications are placed in integrated circuit100. The appropriate portion is used after a specification is selected (e.g., by setting a switch). Because the size of each specific portion is small, this method will not use too much resource of the integrated circuit.

Implementation details of integrated circuit100using an FPGA130are shown inFIG. 2. Common elements inFIGS. 1 and 2have common reference numerals. In this exemplary implementation, PHYs102and104are spaced apart so that a common programmable logic fabric can be used to implement MII108and MAC110. As mentioned before, PHYs102and104are fixed logic components (i.e., not implemented using programmable logic fabric elements). A connection logic layer (such as first connection logic layer132and second connection logic layer134) is used to provide transition from a fixed logic component to the programmable logic fabric. FPGA130also has a plurality of programmable IOBs136. Some of these IOBs can be used to carry signals106and118ofFIG. 1.

A detailed description of one of the connection logic layers is now provided.FIG. 3shows one section30of integrated circuit100. As shown inFIG. 3, a programmable logic fabric12includes a plurality of CLBs80, a plurality of memory blocks (block RAM)90, and a plurality of multipliers92. Programmable I/O block section14includes a plurality of individual IOBs86and a plurality of digital clock managers (DCM)84. The operations of CLBs80, DCMs84, IOBs86, block RAM90, and multipliers92function in a similar manner as corresponding components found in the X4000E family of field programmable gate arrays and/or the Virtex-II field programmable gate arrays designed and manufactured by Xilinx, Inc.

As shown, CLBs80, block RAM90and multipliers92are arranged in a series of rows and columns. To embed a fixed logic circuit32, programmable logic fabric12of CLBs80, block RAM90, and multipliers is essentially by way of analogy to “cut to make a hole” for the insertion of the fixed logic circuit and its corresponding interconnecting logic34. As such, fixed logic circuit32and interconnecting logic34replace a set of configurable logic blocks80, a set of memory blocks90, and/or a set of multipliers92.

With “a hole cut” in the programmable logic fabric, typical operation of the FPGA would be interrupted. This interruption occurs as a result of a programming interdependency between the plurality of configurable logic blocks80, block RAMs90, and multipliers92.

The interconnecting logic34includes a plurality of interconnecting tiles96and may further include interfacing logic94. The interconnecting tiles96provide connectivity between the interfacing logic94, when included, and fixed logic circuit32with the plurality of CLBs80, block RAM's90and/or multipliers92of the programmable logic fabric12.

Interfacing logic94conditions data transfers between fixed logic32and CLBs80, block RAM90and/or multipliers92of the programmable logic fabric. Such conditioning is dependent upon the functionality of fixed logic circuit32. For example, if fixed logic circuit32processes video and/or audio signals in the analog domain, interfacing logic94would include analog to digital converters and digital to analog converters. If fixed logic circuit32is a microprocessor, the interfacing logic conditions the data to access control buses, address buses, and/or data buses of the microprocessor. In addition, interfacing logic94may include test circuitry for testing the embedded fixed logic circuit and the surrounding programmable logic fabric.

A different architecture of a communication integrated circuit200is now described. Integrated circuit200contains one PHY component202connected to a signal line206. Signal line206provides a communication link between integrated circuit200and external data of a physical medium. PHY component202is connected to two MAC components204and206. When integrated circuit is in operation, only one MAC is used. MAC204and206are connected to a processing component212, which is in turn connected to an interface component214. Interface component214is connected to signal line218, which is connected to an external device (not shown).

In this architecture, MAC components204and206have very little in common. Thus, the above-mentioned partial reconfiguration may not present many advantages in this case. Consequently, both MAC components are pre-installed in integrated circuit200.

In this embodiment, a PHY component202is preferably a fixed logic component embedded into a programmable logic fabric. The other components, such as the MAC components204and206, processing component212, and interface component214, can be implemented using programmable logic fabric220. It should be noted that any number of MACs might be installed in integrated circuit200, depending on its size.

FIG. 5shows an FPGA230that can be used to implement integrated circuit200ofFIG. 4. Common elements ofFIGS. 4 and 5share common reference numerals. PHY202is placed inside programmable logic fabric220. A connection logic layer226is used to provide transition from a fixed logic component to the programmable logic fabric. FPGA230also has a plurality of programmable IOBs224. Some of the IOBs are used to carry signals206and218ofFIG. 4.

Examples of specifications that can advantageously use the architecture shown inFIG. 4are HiperLAN2, supported by HiperLAN2 Global Forum and IEEE 802.11a, supported by IEEE. These are wireless local area network specifications.

Referring toFIG. 6, there is shown an exemplary embodiment of an FPGA300in accordance with one or more aspects of the present invention. FPGA300comprises programmable gates307, programmable input/output (I/O) blocks306and transceiver (physical layer)301. Transceiver301may be a 5 GHz radio for purposes of implementing IEEE 802.11a technology or HiperLAN2 technology. It should be understood that both IEEE 802.11a and HiperLAN2 use the same physical layer, and thus transceiver301may be used for both technologies. Transceiver301physical layer is therefore for Orthogonal Frequency Division Multiplex (OFDM) in accordance with the mentioned technologies. In order to achieve throughput necessary for operating a 5 GHz radio, transceiver301is hardwired or embedded, as opposed to having substantial functionality provided by programmable gates307. Transceiver301is programmably coupled to programmable gates307through programmable I/O blocks306. Programmable gates may be programmed to comprise several modules, namely medium access control and baseband controller module302, encryption algorithms module305, baseband processor module324, and host interface(s) module304, as well as glue and other logic module303. Notably, a data link layer typically comprises a logical link control (LLC) sub-layer and a medium access control (MAC) sub-layer. However, for purposes of clarity, medium access control, as referred to with respect to module302is intended to cover MAC sub-layer, and may further comprise a portion of LLC sub-layer. More particularly, a framing portion conventionally done in an LLC sub-layer is done in a MAC sub-layer. Glue and other logic module303represent that programmable gates307may be used to provide glue logic or other desired logic functions, assuming sufficient gates307are available for programming. It further should be appreciated that MAC layers for IEEE 802.11a and HiperLAN2 technologies are significantly different. The MAC layer used for IEEE 802.11a is a Carrier Sense Multiple Access protocol, more particularly a Carrier Sense Multiple Access/Collision Avoidance (CSMA/CA), where the MAC layer for HiperLAN2 is Time Division Multiple Access (TDMA) protocol in conjunction with time division duplexing (TDD). Accordingly, MAC and baseband controller module302is programmed according to which technology platform is being employed.

Referring toFIG. 7, there is shown an exemplary embodiment of FPGA300program in accordance with one or more aspects of the present invention. In this embodiment, a separate transceiver301integrated circuit, namely not embedded in FPGA300, is coupled to FPGA300, as is program memory312. In this embodiment, a direct interface between separate transceiver301and FPGA300may be employed for direct interaction between transceiver301and FPGA300. Program memory312stores programming instructions for configuring programmable gates307, or more particularly configuration logic blocks307. Program memory312and transceiver301, whether embedded or separate from FPGA300, are coupled to programmable gates307via programmable I/O blocks306B, which are configurably coupled to I/O routing ring306A. FPGA300comprises memory311, which may be random access memory, for storing configuration information or configuring programmable gates307. FPGA further comprises delay lock loops (DLLs)309and multiply/divide/de-skew clock circuits310.

Programming instructions are used to configure memory311in order to provide one or more desired logical functions, namely, MAC302, hosts interface330, encryption engine321, or baseband processor324. It should be noted that HiperLAN2 and IEEE 802.11a technologies use different baseband controllers, and this particular baseband controller will need to be programmed into FPGA300depending on the technology platform employed. Thus, to this point, it should be appreciated that FPGA300provides a multi-platform Application Specific Standard Product (ASSP).

Referring toFIG. 8, there is shown an exemplary embodiment of a circuit board330comprising an FPGA300in accordance with one or more aspects of the present invention. Circuit board330comprises FPGA300, program memory312, and data memory313. Additionally, circuit board330may comprise an interconnect for connecting to a host bus, for example, a host bus of computers333or access points334. Alternatively, or in addition to, such a connector, circuit board330may comprise a host device interface transceiver322. Moreover, circuit board330may comprise antenna336or may be coupled to antenna336.

Wireless local area network transceiver301receives information from or provides information to antenna336. The receive signal will be in an OFDM form, as mentioned above, however the MAC layer will be CSMA or TDMA. Accordingly, a CSMA/TDMA detector318may be coupled to wireless LAN transceiver301to provide an indicator signal to memory312, indicative of whether a received signal is a CSMA or TDMA signal. FPGA300may have embedded wireless transceiver301and optionally embedded CSMA/TDMA detector318. Because of the time necessary to program FPGA300, using an auto detect signal from detector318to program memory312would be for an initialization or setup operation. Alternatively, CSMA/TDMA detector318may be omitted and FPGA300may be programmed via a host bus or host device for selecting program instructions398stored in program memory312to program FPGA300for CSMA or TDMA MAC layers and appropriate baseband controllers.

FPGA300is programmed by program instructions398contained in program memory312. Thus, once FPGA300is configured, it may communicate with transceiver301.

Configured FPGA300comprises radio interface and controller315, MAC protocol engine/configuration controller320, baseband processor interface323, and optionally encryption engine321. Radio interface and controller315may comprise analog-to-digital converter (ADC)316, digital-to-analog converter (DAC)317and baseband filters318. Alternatively, as circuit board330is directed at providing a 5 GHz WLAN radio implementation, ADC318, DAC317and filters318may be embedded or otherwise hardwired for processing signals from WLAN transceiver301, as opposed to being programmed as part of radio interfacing controller315using programmable gates of FPGA300.

Radio interface controller315is in communication with MAC protocol engine/configured controller320. MAC protocol engine/configuration320is in communication with baseband processor interface323, encryption engine321and memory controller314. Memory controller314is in communication encryption engine321, baseband processor interface323, program memory312and host interface329. Memory controller314may be programmed using a portion of program instruction398for programming programmable gates of FPGA300or may be hardwired or embedded with FPGA300, or may be a separate integrated circuit from FPGA300. Advantageously, using programmable gates of FPGA300a memory controller314facilitates support of various types of memory. For example, static random access memory (SRAM) may be configured for ZBT, DDR, and QDR, among other formats, dynamic random access memory may be configured for page mode, synchronous, and synchronous DDR, among other formats. Memory controller314may be coupled to separate data memory313for use by FPGA300in processing information received from or provided to WLAN transceiver301, computer333, access point334or host device interface receiver322. MAC protocol engine/configuration controller320is in communication baseband processor interface323. Baseband processor interface323is in communication with memory controller314and baseband processor324. Baseband processor324may be programmed with programmable gates of FPGA300, or be provided in an embedded or otherwise hardwired form with FPGA300or provided as a separate integrated circuit from FPGA300.

Encryption engine321may be an implementation of any of a variety of encryption algorithms. Conventionally, in the wireless space, a Wired Equivalent Privacy (WEP) encryption is used. Notably, WEP is only for wireless communication and not necessarily for end-to-end communication. An algorithm for plain text data (RC4) encryption is used, and to protect against unauthorized data modification a redundancy code, namely CRC-32, is used. However, 40 bit RC4 encryption is used for IEEE 802.11a, it is not used for HiperLAN2. Accordingly, program memory312comprises programming instructions398for FPGA300to configure encryption engine321for either of at least these two types of encryptions being employed, namely, RC4 and DES or triple DES with respect to HiperLAN2. Moreover, there is no particular reason that only these encryption algorithms may be a programmed in FPGA300, and thus program memory312may comprise program instructions398for FPGA300for other encryption algorithms including but not limited to Advanced Encryption Standard (AES), Rivest-Shamir-Adleman (RSA), Diffie-Hellman, RC4/RC5, Secure Hashing Algorithm (SHA), Blowfish, Elliptic Curve Encryption, El Gamal, and Lucas Sequence (LUC), among others.

Memory controller314is communication with host interface329. Host interface329may comprise host bus interface325, host device interface326, and host device controller327. Additionally, host interface329may comprise an embedded or hardwired host device interface transceiver322, which is embedded or hardwired with FPGA300. Host bus interface325is in communication with memory controller314and may be put in communication with a bus of computer333or access point334. Host device interface326is in communication with memory controller314and host device controller327. Host device controller327is in communication with host device interface transceiver322. Host interface329is described in more detail herein below for providing a plurality interface platforms with FPGA300.

Referring toFIG. 9, there is shown a network diagram of an exemplary embodiment of a WLAN in accordance with one or more aspects of the present invention. Local area network335comprises server331coupled to hub or switch332coupled to access points (AP)334A and334B, as well as personal computer333A and333B. Access points334and personal computers333are equipped with respective circuit boards330. Notably, computer333A and access point334A may be configured for IEEE 802.11a technology, and computer333B and access point334B may be configured for HiperLAN2 technology, even though computers333and access points334use the same interface card namely circuit board330. Notably, circuit board330may be implemented in a wireless printer337, a wireless fax338, among other well-known peripheral devices for inclusion in local area network335. However, rather than installing a WLAN interface card in accordance with circuit board330in printer337or fax338a separate WLAN interface may be used, such as an universal serial bus (USB) interface between circuit board330, or more particularly, host device interface transceivers332, and a peripheral device or computer.

Referring toFIG. 10, there is shown a block diagram of an exemplary embodiment of an FPGA400coupled to processor410and memory411which may be assembled to a circuit board499in accordance with one or more aspects of the present invention. As will become apparent, FPGA300ofFIG. 8may be configured to incorporate interface functionality described with respect to FPGA400. Memory411stores programming instructions498for configuring FPGA400. FPGA400comprises interface transceiver415, interface communication link413, application interface logic406and glue logic and other logic functions407. I/O data stream414is a USB compliant data stream. More particularly, I/O data stream414may be a USB 2.0 compliant data stream. Data stream414is provided to line driver412. Line driver412is in communication with serial interface engine (SIE)401. Notably, transceiver415comprises line driver412, SIE401, one or more delay lock loops309, and one or more clock generators310. Transceiver415is part of the physical layer, and accordingly may be hardwired or otherwise embedded with respect to formation of FPGA400. Alternatively, transceiver415may be made separate from FPGA400, namely, two separate integrated circuits.

SIE401is in communication with SIE control logic402. SIE control logic402is in communication with delay lock loops309, clock generators310, suspend mode controller405and processor interface404. Processor interface404may be a parallel interface module (PIM), as is known for a USB interface core. Processor interface404is in communication with direct memory address (DMA)408and controller403. Accordingly, controller403may be a USB controller, and more particularly a USB2.0compatible controller. Interface communication link413comprises SIE control logic402, suspend mode controller405, USB controller403, processor interface404and DMA408. Interface communication link413is configured using FPGA400programmable gates. In this manner, FPGA400may be programmed, and therefore reprogrammed. Interface communication link413is programmed with a portion of instructions498stored in memory411. Stored in memory411is a plurality of interface communication link instructions498for selection of a configuration for programming FPGA400.

USB controller403is in communication with application interface logic406and memory411. Application interface logic406is configured using programmable logic gates of FPGA400. Accordingly, application interface logic406may be programmed with one of multiple interfaces stored in memory411as a portion of programming instructions498. Examples of such interfaces include Ethernet, Peripheral Component Interconnect (PCI), Controller Area Network (CAN), WLAN, HomeRF, PCI-X, Video Electronics Standards Association (VESA), Infiniband, RapidIO and Universal Asynchronous Receiver Transmitter (UART), among others. With respect to additional available gates for programming in FPGA400, glue and other logic407is available. Processor410is in communication with processor interface404and application interface logic406. Memory411is in communication with processor interface404and USB controller403. Processor interface404is a selected one of a plurality of processor interface configurations stored in memory411as a portion of programming instructions498. Thus, processor410may be any of a variety of known processor architectures, such as a Complex Instruction-Set Computer (CISC) processor architecture and a Reduced Instruction-Set Computer (RISC) processor architecture. Notably, USB controller403alternatively may be part of the physical layer and thus formed integral with FPGA400through a hardwired or embedded configuration, or formed as a separate integrated circuit. Accordingly, memory411comprises programming instructions498for configuring programmable gates of FPGA400as described above.

I/O data stream414is a USB data stream. However, application interface logic406may be other than USB. Accordingly, application interface logic406is configured to take input from processor410and convert it into a USB format, and application interface logic406is configured to receive USB formatted information from USB controller403and convert it into an application interface format used by processor410. Thus, FPGA400may be configured to provide an interface that is a multi-platform ASSP.

USB is a growing trend with respect to high-speed communication technology. USB is incorporated into printers, scanners, monitors, digital speakers, digital cameras, digital modems, stand alone hubs, external storage drives, digital TV, monitors, and gaming consoles, computers, set-top boxes, SOHO routers, home gateway, home servers, among other consumer electronic devices.

It can be seen from the above description that a novel communication system architecture has been disclosed. Those having skill in the relevant arts of the invention will now perceive various modifications and additions, which may be made as a result of the disclosure herein. Accordingly, all such modifications and additions are deemed to be within the scope of the invention, which is to be limited only by the appended claims and their equivalents.