Display device having display area with luminous pixels over curved surface of semiconductor substrate for use in near-eye display

A near-eye display includes a semiconductor substrate that has a first curved surface and a second curved surface opposite to each other, and a plurality of luminous pixels formed over the first curved surface of the semiconductor substrate. The luminous pixels cooperatively form a display area of the near-eye display. The second curved surface of the semiconductor substrate is formed with a plurality of indentations at a portion that corresponds in position to the display area.

BACKGROUND

With the development of virtual reality (VR) and augmented reality (AR), demands for near-eye displays rise. Manufacturing near-eye displays with semiconductor technologies may fulfill requirements of high resolution and low power consumption.

DETAILED DESCRIPTION

Near-eye displays, also known as head-mounted displays (HMDs) or wearable displays, are commonly used in virtual reality (VR) and/or augmented reality (AR) applications, and are configured to display images in front of one or both of the eyeballs of a user by a small distance, which may range from about 10 mm to about 100 mm. Distances between near-eye displays and eyeballs are so close that the near-eye displays usually have a small size, such as having a width and a length each in a range from about 5 mm to about 150 mm.

FIG.1exemplarily illustrates a top view of a display device1for use in a near-eye display. The display device1includes a display area10(also referred to as luminous area or pixel area), and a peripheral circuit area20(also referred to as dark area) that surrounds the display area10. In accordance with some embodiments, a plurality of luminous pixels12may be arranged in an array in the display area10to display images. The luminous pixels12may refer to self-luminous pixels or back-illuminated pixels or any other types of pixels that are configured to display images, and may be fabricated using, for example, a liquid crystal display (LCD) technology, a light-emitting diode (LED) technology, a mini LED technology, a micro LED technology, a quantum dot technology, an organic light-emitting diode (OLED) technology, other suitable display technologies, or any combination thereof. In accordance with some embodiments, the peripheral circuit area20may include, for example, gate driver circuits, source driver circuits, wire routing, other circuits that are configured to enable the luminous pixels12in the display area10to display images, or any combination thereof. In accordance with some embodiments, it may be that the peripheral circuit area20does not include circuits at every side of the display area10, and the peripheral circuit area20may be configured to be circuit-less at one or more sides of the display area10. In accordance with some embodiments, the display device1may be fabricated on a semiconductor wafer, so as to obtain better circuit performance and less power consumption in comparison to those fabricated on other types of substrates, such as glass substrates, plastic substrates, etc. In accordance with some embodiments, the peripheral circuit area20is minimized for reducing an overall area of the display device1, so a number of the display devices1that can be fabricated on a single wafer can be maximized. In accordance with some embodiments, the peripheral circuit area20may occupy about 5% to about 50% of the area of the display device1, which means that the display area10may occupy about 50% to about 95% of the area of the display device1.

FIG.2exemplarily illustrates a scenario where the display device1is a flat display device1A and is configured to display images for an eyeball9in accordance with some embodiments.FIG.3exemplarily illustrates a simplified sectional structure of the display area10of the display device1A. The display device1A includes a substrate100, a driving element section110formed over a frontside surface101of the substrate100, an interconnection section120formed over the driving element section110, and a luminous device section130formed over the interconnection section120, where the luminous pixels12are formed in the luminous device section130.

In the illustrative embodiment, the substrate100is a semiconductor substrate that may be a bulk semiconductor substrate or a semiconductor-on-insulator (SOI) substrate, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. In some embodiments, an SOI substrate includes a layer of a semiconductor material formed on an insulator layer. The insulator layer may be a buried oxide (BOX) layer, a silicon oxide layer or any other suitable layer. The insulator layer may be provided on a suitable substrate, such as silicon, glass or the like. The substrate100may be made of a suitable semiconductor material, such as silicon or the like. In some embodiments, the substrate100is a silicon substrate; and in other embodiments, the substrate100is made of a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, indium phosphide or other suitable materials. In still other embodiments, the substrate100is made of an alloy semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP or other suitable materials.

In some embodiments, the substrate100includes various p-type doped regions and/or n-type doped regions, such as p-type wells, n-type wells, p-type source/drain features and/or n-type source/drain features (source/drain feature(s) may refer to a source or a drain, individually or collectively depending upon the context), formed by a suitable process such as ion implantation, thermal diffusion, a combination thereof, or the like. In some embodiments, the substrate100may include other functional elements such as resistors, capacitors, diodes, transistors, and/or the like. The transistors are, for example, field effect transistors (FETs), such as planar FETs and/or 3D FETs (e.g., FinFETs, GAAFETs). The substrate100may include lateral isolation features (e.g., shallow trench isolation (STI)) configured to separate various functional elements formed on the substrate100and/or various functional elements formed in the substrate100.

In the illustrative embodiment, the substrate100is opaque and is configured to allow images to travel directly toward the eyeball9(rather than projecting images onto a transparent object, such as a lens), so the display device1A is suitable for VR applications. The driving element section110includes a plurality of pixel-driving components112that are electrically connected to the luminous pixels12, and are configured to drive light emission of the luminous pixels12. In accordance with some embodiments, each of the pixel-driving components112is electrically connected to a respective one of the luminous pixels12, and may be a circuit that includes one or more transistors (not shown). In accordance with some embodiments, the transistors may be realized as planar transistors, FinFETs, GAAFETs, other suitable types of transistors, or any combination thereof. In accordance with some embodiments, each of the pixel-driving components112may include one or more passive components, such as capacitors, resistors, inductors, other suitable passive components, or any combination thereof. In accordance with some embodiments, the driving element section110may also include some circuits (e.g., the gate driver circuits, the source driver circuits, the wire routing, etc.) that are formed in the peripheral circuit area20(seeFIG.1).

The interconnection section120is configured to connect the pixel-driving components112of the driving element section110to the luminous pixels12of the luminous device section130. In accordance with some embodiments, the interconnection section120may include one or more interconnection layers120_1to120_n, each of which may include metal wires and metal vias that are formed in interlayer dielectrics. In accordance with some embodiments, the metal wires and the metal vias may include, for example, Ti, Ta, Cu, W, AlCu, AlSiCu, other suitable materials, or any combination thereof. In different interconnection layers, the metal wires and the metal vias may have different element compositions. For example, the metal wires and the metal vias may be AlSiCu with different compositions (e.g., different atomic ratios among Al, Si and Cu) in different interconnection layers. In accordance with some embodiments, the interlayer dielectrics may include, for example, silicon oxide, silicon oxynitride, fluorosilicate glass (FSG), phosphosilicate glass (PSG), silicon carbide, silicon nitride, low-k materials, or any combination thereof. The pixel-driving components112of the driving element section110are electrically connected to the luminous pixels12in the luminous device section130through the metal wires and the metal vias.

The luminous device section130includes the luminous pixels12formed therein, and the luminous pixels12cooperatively form the display area10(seeFIG.1). In accordance with some embodiments, the luminous device section130may further include an encapsulation layer131that is formed over and covers the luminous pixels12. In a case that the luminous pixels12are fabricated using the OLED technology, each of the luminous pixels12may include an anode layer, a hole injection layer, a hole transporting layer, an emission material layer, an electron transporting layer, an electron injection layer, and a cathode layer that are stacked in the given order, where the anode layer is in contact with the top interconnection layer120_n(when viewed from the perspective ofFIG.3). In accordance with some embodiments, the cathode layers of the luminous pixels12may be electrically connected to a common electrode (not shown) that is formed in the peripheral circuit area20(seeFIG.1).

FIG.4exemplarily illustrates a variation of the display device1in accordance with some embodiments, where the display device1is a curved display device1B that has a curved frontside surface100A and a curved backside surface100B opposite to each other. To be specific, from the perspective of the eyeball9of the user, the frontside surface100A is a concave surface that faces the eyeball9, and the backside surface100B is a convex surface. Referring toFIG.2, when the user views an image displayed by the flat display device1A, since the eyeball9has a curved surface, the user may detect some distortions at an edge portion (represented by stripes inFIG.2) of the image. On the other hand, the curved display device1B as illustrated inFIG.4fits the shape of the eyeball9better, so the user may detect less distortions at the edge portion of the image when the image is displayed by the curved display device1B, and the user may feel that the image presented by the curved display device1B has better quality than the image presented by the flat display device1A.

Referring toFIGS.4and5, the backside surface100B of the curved display device1B is formed with a plurality of indentations150to create a desired curvature of the curved display device1B. In accordance with some embodiments, the backside surface100B of the curved display device1B is a backside surface102of the substrate100that is opposite to the frontside surface101of the substrate100. The indentations150may be formed in various shapes. Since the presence of excessive indentations150may unnecessarily reduce a mechanical strength of the substrate100, in the illustrated embodiment, the indentations150are formed only in a portion of the backside surface102of the substrate100that corresponds in position to the display area10(or to a portion of the luminous device section130where the luminous pixels12are formed), so as to maximize the mechanical strength of the substrate100while the substrate100has the desired curvature, but this disclosure is not limited to such, and in some embodiments, the indentations150may also be formed in a portion of the backside surface102of the substrate100that corresponds in position to the peripheral circuit area20. In accordance with some embodiments, the indentations150may be distributed in 10% to 80% of the overall area of the backside surface102of the substrate100to ensure a sufficient mechanical strength of the substrate100while achieving the desired curvature of the curved display device1B. In the illustrative embodiment, a distribution density of those of the indentations150that correspond in position to an edge portion of the display area10is greater than a distribution density of those of the indentations150that correspond in position to a central portion of the display area10because the edge portion of the display area10may need a greater curvature to alleviate the image distortion that may occur at the edge portion, but this disclosure is not limited to such, and the distribution density of the indentations150may be designed based on specific product specifications in other embodiments.

Referring toFIG.6, part (a) provides some examples for the shapes of the indentations150in a top view. The examples include a square, a triangle, a hexagram, a stripe (or rectangle), a cross, a circle and an oval, but this disclosure is not limited to such. The indentations150may be formed in any shapes as desired by a designer. However, the most commonly-used shapes may be stripes and crosses. A stripe-shaped indentation may have a pair of short edges and a pair of long edges to form a narrow rectangle, and make the display device1B bend toward a frontside direction (i.e., a direction that the frontside surface100A of the display device1B faces) from two sides separated by a longitudinal axis of the stripe-shaped indentation. Therefore, the stripe-shaped indentations can be used to adjust a curvature of the display device1with respect to a target direction, and to adjust uniformity in terms of distribution of stress applied to the substrate100. In accordance with some embodiments, a stripe-shaped indentation may have a width in a range from about 3 μm to about 60 μm and a length in a range from about 3 μm to about 60 μm. An excessively large width/length of the stripe-shaped indentation (e.g., greater than 60 μm) may result in excessive bending toward a single direction, which may lead to poor uniformity in terms of stress distribution. Further, the excessively long or wide stripe-shaped indentation may also cause an insufficient structural strength of the substrate100. An excessively small width/length of the stripe-shaped indentation (e.g., smaller than 3 μm) may lead to insufficient bending of the substrate100, so the curved display device1B may not have the desired curvature. A cross-shaped indentation may have a first stripe pattern and a second stripe pattern that intersect each other. Each of the first stripe pattern and the second stripe pattern is a stripe-shaped indentation that has a width in a range from about 3 μm to about 60 μm and a length in a range from about 3 μm to about 60 μm. Since the cross-shaped indentation have two stripe patterns that extend in different directions, the cross-shaped indentation may have better uniformity in terms of the stress distribution. In accordance with some embodiments, the first stripe pattern and the second stripe pattern of the cross-shaped indentation are perpendicular to each other, thereby achieving even better uniformity in terms of the stress distribution. In accordance with some embodiments, the first stripe pattern and the second stripe pattern of the cross-shaped indentation may have different lengths and/or widths, so as to adjust uniformity in terms of the stress distribution. In accordance with some embodiments, the first stripe pattern and the second stripe pattern of the cross-shaped indentation form a plus sign, where the intersection of the first stripe pattern and the second stripe pattern is located at both of the centers of the first stripe pattern and the second stripe pattern, thereby achieving even better uniformity in terms of the stress distribution.

In accordance with some embodiments, the indentations150can be arranged regularly in terms of shapes of the indentations150and/or distances among the indentations150. That is, the arrangement of the shapes of the indentations150can be periodic, and the distances among the indentations150may be formulated (e.g., the indentations150may be arranged equidistantly or based on a predetermined rule). InFIG.6, parts (b) and (c) illustrate that the arrangement of the indentations150can be irregular in terms of shapes of the indentations150and/or distances among the indentations150. In other words, the arrangement of the shapes of the indentations150can be non-periodic, and the distances among the indentations150may vary and be non-formulated (not following any particular rule) in accordance with some embodiments. In accordance with some embodiments, the indentations150may be arranged in rows and columns. In accordance with some embodiments, the indentations150may be arranged in multiple concentric circles. In accordance with some embodiments, the indentations150may be randomly distributed on the backside surface102of the substrate100.

FIG.7is a flow chart that cooperates withFIGS.8through16to illustrate a process for fabricating the curved display device1B as exemplified inFIG.4in accordance with some embodiments.

Referring toFIG.8, the substrate100is provided. In the illustrative embodiment, the substrate100is a semiconductor wafer (e.g., a silicon wafer) that may be formed with functional elements (e.g., resistors, capacitors, diodes, transistors, and/or the like) therein.

Referring toFIGS.7and9, in step S1, the driving element section110is formed over the frontside surface101of the substrate100. The driving element section110may include a plurality of pixel-driving components112(seeFIG.3) to drive light emission of the luminous pixels12(seeFIG.3), and peripheral circuits (e.g., the gate driver circuits, the source driver circuits, the wire routing, etc.) that are formed in the peripheral circuit area20(seeFIG.1) to drive operation of the pixel-driving components112. For example, the wire routing may include routing of gate lines that extend in a row direction and routing of data lines that extend in a column direction; the gate driver circuits may turn on the pixel-driving components112row by row through the gate lines; and the source driver circuits send image data through the data lines to a row of the pixel-driving components112that is turned on by the gate driver circuits. The operations of the peripheral circuits should be familiar to one having ordinary skill in the art, so details thereof are omitted herein for the sake of brevity.

Referring toFIGS.7and10, in step S2, the interconnection section120is formed over the driving element section110. The interconnection section120may include multiple layers of interconnection structures (e.g., metal wires, metal vias, and the like) to electrically connect some circuit elements (e.g., the pixel-driving components112) that are formed in lower sections (when viewed from the perspective ofFIG.10; e.g., the driving element section110) to circuit elements (e.g., the luminous pixels12inFIG.3) that are to be subsequently formed over the interconnection section120.

Referring toFIGS.3,7and11, in step S3, the luminous device section130is formed over the interconnection section120. The luminous pixels12formed in the luminous device section130are electrically connected to the pixel-driving components112through the interconnection structures of the interconnection section120. At this stage, the substrate100has been formed with a plurality of the display devices1, as exemplified inFIG.12, where the display devices1are flat display devices1A as exemplified inFIG.3. In practice, a number of the display devices1may be either less or more than what is depicted inFIG.12, and may be determined based on the demand and/or design layout, and the disclosure is not limited thereto.

Referring toFIGS.7and13, in step S4, a protective layer140is formed over the luminous device section130to cover the luminous pixels12(seeFIGS.1and3). In accordance with some embodiments, the protective layer140may include, for example, a polymer, silicon nitride, other suitable materials, or any combination thereof. In accordance with some embodiments, a protective polymer layer may be formed using, for example, spin coating, followed by a baking process that has a baking temperature in a range from about 85° C. to about 500° C. An excessively low baking temperature (e.g., lower than 85° C.) may not achieve effective drying of the polymer, while an excessively high baking temperature (e.g., higher than 500° C.) may affect distribution of implants that have been implanted in the front-end-of-line (FEOL) process, resulting in shifting of device characteristics (e.g., threshold voltage of transistors). Using the polymer as the protective layer140is advantageous in that the spin coating process is a process of low cost, high stability, low process temperature (can be performed under room temperature), and low pollution risk and does not require a vacuum environment. In accordance with some embodiments, a protective silicon nitride layer may be formed using, for example, chemical vapor deposition (CVD), other suitable deposition techniques, or any combination thereof. In accordance with some embodiments, a CVD process to form the protective silicon nitride layer may have a process temperature in a range from about 200° C. to about 500° C. An excessively low CVD process temperature (e.g., lower than 200° C.) maybe insufficient to form the silicon nitride layer with desired properties, while an excessively high CVD process temperature (e.g., higher than 500° C.) may affect distribution of implants that have been implanted in the FEOL process, resulting in shifting of device characteristics. In accordance with some embodiments, the protective layer140may have a thickness in a range from about 50 nm to about 100 μm. An excessively small thickness of the protective layer140(e.g., smaller than 50 nm) may be insufficient to protect the luminous device section130from damages in subsequent processes, while an excessively large thickness of the protective layer140(e.g., greater than 100 μm) may result in a longer process time (e.g., time for baking the polymer, time for removing the protective layer140in a later process, etc.), which is less economic. In accordance with some embodiments, during a coating process or a deposition process for forming the protective layer140, the protective layer140may also be formed on a lateral side of the substrate100, but this disclosure is not limited in this respect.

Referring toFIGS.7and14, in step S5, the substrate100is flipped, and the backside surface102of the substrate100is ground to reduce a thickness of the substrate100, so the substrate100may bend more easily or have a greater curvature after the indentations150(seeFIG.5) are formed in a subsequent process. In accordance with some embodiments, the grinding of the substrate100may be performed using a chemical mechanical planarization (CMP) process, other suitable processes, or any combination thereof. The grinding process may generate some particles or pollutions that may cause damages to structures formed at the frontside of the substrate100. However, the protective layer140can protect the luminous device section130from being damaged in the grinding process. In accordance with some embodiments, the substrate100is ground to a thickness in a range from about 10 μm to about 300 μm. An excessively small thickness of the substrate100(e.g., smaller than 10 μm) may result in an insufficient mechanical strength of the substrate100, and thus the substrate100may be easily damaged or may crack. An excessively large thickness of the substrate100(e.g., greater than 300 μm) may make the substrate100unable to achieve a desired curvature.

Referring toFIGS.7and15, in step S6, the backside surface102of the substrate100is etched to formed the indentations150therein. In accordance with some embodiments, the indentations150may be formed using a photolithography process. In detail, a photoresist layer may be formed over the backside surface102of the substrate100using, for example, spin coating, followed by a baking process. Then, an exposure process is performed using a reticle/photomask that is formed with a plurality of indentation patterns (e.g., stripe patterns, cross patterns, square patterns, triangle patterns, hexagram patterns, circle patterns, and/or oval patterns, etc.), followed by a developing process. After the developing process, an etching process is performed using, for example, dry etching, wet etching, other suitable etching techniques, or any combination thereof, to form the indentations150in the backside surface102of the substrate100. In accordance with some embodiments, each of the indentations150is formed to have a depth in a range from about 3 μm to about 60 μm. The depths of the indentations150may be used to adjust the curvature of the resultant display device1, where a deeper indentation may lead to a greater curvature. Excessively small depths of the indentations150(e.g., smaller than 3 μm) may be insufficient to achieve the desired curvature of the substrate100, while excessively large depths of the indentations150(e.g., greater than 60 μm) may reduce the mechanical strength of the substrate100excessively, and thus the substrate100may easily crack. The indentations150may have either the same or different depths. In accordance with some embodiments, an annealing process may be performed after the indentations150are formed, so as to enhance the curvature of the resultant display device1(seeFIG.4). The annealing process may have an annealing temperature in a range from about 300° C. to about 500° C. An excessively low annealing temperature (e.g., lower than 300° C.) may be insufficient to enhance the curvature of the resultant display device1. An excessively high annealing temperature (e.g., greater than 500° C.) may affect distribution of implants that have been implanted in the front-end-of-line (FEOL) process, resulting in shifting of device characteristics. After the etching process, the photoresist layer is removed using, for example, 02 plasma ashing and wet strip, so as to reveal the patterned backside surface102of the substrate100(i.e., the backside surface102that is formed with the indentations150).

Referring toFIGS.7,16and17, in step S7, the protective layer140is removed from the substrate100. As a result, the substrate100is formed with a plurality of display devices that have structures of the curved display devices1B (i.e., the display devices1inFIG.12have the structures of the curved display device1B at the current stage). In accordance with some embodiments, the protective layer140may be removed using, for example, dry etching, other suitable etching techniques, or any combination thereof. In accordance with some embodiments where the protective layer140is transparent, step S7may be omitted. However, the curved display device1B may have a better image quality with the protective layer140removed. Then, the substrate100is cut to separate the display devices1formed on the substrate100, and the display devices1will naturally bend toward the frontside direction by virtue of the indentations150that are formed in the backside surface102of the substrate100, thereby obtaining multiple pieces of the curved display devices1B.

FIG.17exemplarily illustrates a simplified sectional structure of the display area10of the curved display device1B. Similar to the flat display device as exemplified inFIG.3, the curved display device1B includes the substrate100, the driving element section110formed over the frontside surface101of the substrate100, the interconnection section120formed over the driving element section110, and the luminous device section130formed over the interconnection section120, where the luminous pixels12are formed in the luminous device section120. Specifically, the substrate100of the curved display device1B is curved, and the frontside surface101and the backside surface102thereof are curved surfaces, or particularly, a concave surface and a convex surface, respectively. In addition, the curved display device1B has a plurality of indentations150formed in the backside surface102of the substrate100. InFIG.17, the indentations150are stripe-shaped indentations that extend in a direction entering the drawing, thereby making the substrate100bend in directions represented by curved arrows inFIG.17toward the frontside direction (an upper direction inFIG.17) from two sides separated by the direction in which the stripe-shaped indentations extend.

Referring toFIG.18, a curvature of the curved display device1B is defined by an angle θ between a tangent line that passes a center of the backside surface100B and a straight line that interconnects the center of the backside surface100B and an end of the backside surface100B. In accordance with some embodiments, the angle θ of the curved display device1B may range from about 0.9 degrees to about 15 degrees. An excessively small angle θ (e.g., smaller than 0.9 degrees) may be insufficient to effectively alleviate the distortion that may occur at the edge portion of the image displayed by the display device1. An excessively large angle θ (e.g., greater than 15 degrees) may make the substrate100easily crackable, resulting in low yield in mass production.

In accordance with some embodiments, a display device is provided for use in a near-eye display. The display device includes a semiconductor substrate and a plurality of luminous pixels. The semiconductor substrate has a first curved surface and a second curved surface opposite to each other. The luminous pixels are formed over the first curved surface of the semiconductor substrate, and cooperatively form a display area of the display device. The second curved surface of the semiconductor substrate is formed with a plurality of indentations at a portion that corresponds in position to the display area.

In accordance with some embodiments, some of the indentations are stripe-shaped indentations that have a length in a range from 3 μm to 60 μm.

In accordance with some embodiments, the stripe-shaped indentations have a width in a range from 3 μm to 60 μm.

In accordance with some embodiments, some of the indentations are cross-shaped indentations each having a first stripe pattern and a second stripe pattern that intersect each other. For each of the cross-shaped indentations, each of the first stripe pattern and the second stripe pattern has a length in a range from 3 μm to 60 μm.

In accordance with some embodiments, the semiconductor substrate has a thickness in a range from 10 μm to 300 μm.

In accordance with some embodiments, a distribution density of those of the indentations that correspond in position to an edge portion of the display area is greater than a distribution density of those of the indentations that correspond in position to a central portion of the display area.

In accordance with some embodiments, each of the indentations has a depth in a range from 3 μm to 60 μm.

In accordance with some embodiments, a method is provided for fabricating a display device for use in a near-eye display. In one step, a plurality of luminous pixels are formed over a first surface of a semiconductor substrate. The luminous pixels cooperatively form a display area of the display device. In one step, a plurality of indentations are formed in a second surface of the semiconductor substrate that is opposite to the first surface of the semiconductor substrate at a portion that corresponds in position to the display area.

In accordance with some embodiments, between the step of forming the luminous pixels and the step of forming the indentations, the second surface of the semiconductor substrate is ground to reduce a thickness of the semiconductor substrate.

In accordance with some embodiments, between the step of forming the luminous pixels and the step of grinding the second surface of the semiconductor substrate, a protective layer is formed over the luminous pixels.

In accordance with some embodiments, the step of forming the protective layer over the luminous pixels includes coating a polymer layer over the luminous pixels.

In accordance with some embodiments, after the step of forming the indentations, the protective layer is removed.

In accordance with some embodiments, in the step of grinding the second surface of the semiconductor substrate, the thickness of the semiconductor substrate is reduced to fall within a range from 10 μm to 300 μm.

In accordance with some embodiments, some of the indentations are stripe-shaped indentations each having a length in a range from 3 μm to 60 μm.

In accordance with some embodiments, some of the indentations are cross-shaped indentations each having a first stripe pattern and a second stripe pattern that intersect each other. For each of the cross-shaped indentations, each of the first stripe pattern and the second stripe pattern has a length in a range from 3 μm to 60 μm.

In accordance with some embodiments, each of the indentations has a depth in a range from 3 μm to 60 μm.

In accordance with some embodiments, in the step of forming the indentations, a distribution density of those of the indentations that correspond in position to an edge portion of the display area is greater than a distribution density of those of the indentations that correspond in position to a central portion of the display area.

In accordance with some embodiments, a display device is provided for use in a near-eye display. The display device includes a curved semiconductor substrate, a driving element section and a luminous device section. The curved semiconductor substrate has a concave first surface and a convex second surface opposite to each other. The driving element section includes a plurality of pixel-driving components formed therein and is disposed over the concave first surface of the semiconductor substrate. The luminous device section includes a plurality of luminous pixels formed therein. The luminous pixels are electrically connected to and driven by the pixel-driving components to emit light. The convex second surface of the semiconductor substrate has a plurality of indentations formed therein at a portion that corresponds in position to a portion of the luminous device section where the luminous pixels are formed.

In accordance with some embodiments, the semiconductor substrate has a thickness in a range from 10 μm to 300 μm.

In accordance with some embodiments, each of the indentations has a depth in a range from 3 μm to 60 μm.