Thin film transistor structure and method for manufacturing the same

A thin film transistor (TFT) structure includes a metal oxide semiconductor layer, a gate, a source, a drain, a gate insulation layer, and a passivation layer. The metal oxide semiconductor layer has a crystalline surface which is constituted by a plurality of grains separated from one another. An indium content of the grains accounts for at least 50% of all metal elements of the metal oxide semiconductor layer. The gate is disposed on one side of the metal oxide semiconductor layer. The source and the drain are disposed on the other side of the metal oxide semiconductor layer. The gate insulation layer is disposed between the gate and the metal oxide semiconductor layer. The passivation layer is disposed on the gate insulation layer, and the crystalline surface of the metal oxide semiconductor layer is in direct contact with the gate insulation layer or the passivation layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 101138720, filed on Oct. 19, 2012. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a semiconductor structure and a method for manufacturing the same. More particularly, the invention relates to a thin film transistor (TFT) structure and a method for manufacturing the same.

2. Description of Related Art

The most common liquid crystal display (LCD) is mainly composed of a thin film transistor (TFT) array substrate, a color filter substrate, and a liquid crystal layer sandwiched between the two substrates. In a conventional TFT array substrate, amorphous silicon (α-Si) TFT or low temperature polysilicon TFT often serves as a switch device of each sub-pixel. Generally, the TFT at least has a gate, a source, a drain, a channel layer, and so on; and conductivity of the channel layer may be changed by controlling a voltage on the gate, such that the source and the drain are electrically conducted (ON) or electrically insulated (OFF). In addition, an n-doped or p-doped ohmic contact layer is often formed on the channel layer, so as to reduce the contact resistance between the channel layer and the source or between the channel layer and the drain. The channel layer of the conventional TFT is mostly made of α-Si or polysilicon.

The resultant TFT however requires high manufacturing temperature regardless of the material (α-Si or polysilicon) of the channel layer; therefore, the existing manufacturing process of low-temperature polysilicon and α-Si may cause damages to a flexible substrate, an adhesion layer, or other components. The damages to these components may further pose a negative impact on device characteristics of a display. In addition, both the carrier mobility and the reliability of the α-Si TFT are not sufficiently satisfactory, which considerably restricts the application range of the α-Si TFT.

SUMMARY OF THE INVENTION

The invention is directed to a thin film transistor (TFT) structure which contains grains with high indium content, thus improving the carrier mobility and the reliability of devices.

The invention is also directed to a method for manufacturing the aforesaid TFT structure.

In an embodiment of the invention, a TFT structure that is disposed on a substrate is provided. The TFT structure includes a metal oxide semiconductor layer, a gate, a source, a drain, a gate insulation layer, and a passivation layer. The metal oxide semiconductor layer has a crystalline surface that is constituted by a plurality of grains. The grains are separated from one another, and an indium content of the grains accounts for at least 50% of all metal elements of the metal oxide semiconductor layer. The gate is disposed on one side of the metal oxide semiconductor layer. The source and the drain are disposed on the other side of the metal oxide semiconductor layer. The gate insulation layer is disposed between the gate and the metal oxide semiconductor layer. The passivation layer is disposed on the gate insulation layer, and the crystalline surface of the metal oxide semiconductor layer is in direct contact with the gate insulation layer or the passivation layer.

In an embodiment of the invention, a method for manufacturing a TFT structure includes following steps. A gate is formed on a substrate. A gate insulation layer is formed on the substrate, and the gate insulation layer covers the gate and a portion of the substrate. A metal oxide semiconductor layer is formed on the gate insulation layer, and the metal oxide semiconductor layer exposes a portion of the gate insulation layer. A source and a drain are formed on the metal oxide semiconductor layer. Here, the source and the drain expose a portion of a surface of the metal oxide semiconductor layer. A passivation layer is formed on the source and the drain. Here, the passivation layer covers the source, the drain, and the gate insulation layer and is in direct contact with the portion of the surface of the metal oxide semiconductor layer exposed by the source and the drain, so as to form a crystalline surface. The crystalline surface is constituted by a plurality of grains separated from one another, and an indium content of the grains accounts for at least 50% of all metal elements of the metal oxide semiconductor layer.

In an embodiment of the invention, a method for manufacturing a TFT structure includes following steps. A source and a drain are formed on a substrate. Here, the source and the drain expose a portion of the substrate. A metal oxide semiconductor layer is formed on the substrate, and the metal oxide semiconductor layer covers the source, the drain, and the portion of the substrate exposed by the source and the drain. A gate insulation layer is formed on the substrate. Here, the gate insulation layer covers the metal oxide semiconductor layer, the source, and the drain, and the gate insulation layer is in direct contact with the metal oxide semiconductor layer, so as to form a crystalline surface. The crystalline surface is constituted by a plurality of grains separated from one another, and an indium content of the grains accounts for at least 50% of all metal elements of the metal oxide semiconductor layer. A gate is formed on the gate insulation layer. A passivation layer is formed on the gate and covers the gate and the gate insulation layer.

In light of the foregoing, the interface between the metal oxide semiconductor layer and the passivation layer/the gate insulation layer has the grains that are separated from one another, and the indium content of the grains account for at least 50% of all of the metal elements of the metal oxide semiconductor layer. Since indium is characterized by favorable conductivity, the TFT structure described herein may have high carrier mobility and great reliability.

DETAILED DESCRIPTION OF DISCLOSED EMBODIMENTS

FIG. 1Ais a schematic cross-sectional diagram illustrating a thin film transistor (TFT) structure according to an embodiment of the invention.FIG. 1Bis a schematic top diagram illustrating the TFT structure depicted inFIG. 1A. To better describe the invention, certain components shown inFIG. 1Aare omitted inFIG. 1B. With reference toFIG. 1A, in a method for manufacturing a TFT structure, a gate110ais formed on a substrate10. A material of the substrate10is, for instance, glass, plastic, or any other suitable materials; a material of the gate110ais metal, for instance.

With reference toFIG. 1AandFIG. 1B, a gate insulation layer120ais formed on the substrate10, and the gate insulation layer120acovers the gate110aand a portion of the substrate10. Here, the gate insulation layer120ais made of silicon oxide, silicon nitride or silicon oxynitride, for instance.

With reference toFIG. 1AandFIG. 1B, a metal oxide semiconductor layer130ais formed on the gate insulation layer120a, and the metal oxide semiconductor layer130aexposes a portion of the gate insulation layer120a. A material of the metal oxide semiconductor layer130ais indium-gallium-zinc oxide (IGZO), for instance.

As shown inFIG. 1AandFIG. 1B, a source140aand a drain150aare formed on the metal oxide semiconductor layer130a. Here, the source140aand the drain150aexpose a portion of a surface S of the metal oxide semiconductor layer130a. The source140aand the drain150aare made of metal, for instance, and the metal herein may be the same as or different from the metal employed for making the gate110a. This should not be construed as a limitation to the invention.

As shown inFIG. 1A, a passivation layer160ais formed on the source140aand the drain150a, and the passivation layer160acovers the source140a, the drain150a, and the gate insulation layer120a. Particularly, the passivation layer160ais in direct contact with the portion of the surface S of the metal oxide semiconductor layer130aexposed by the source140aand the drain150a, so as to form a crystalline surface131a. Here, the crystalline surface131ais constituted by a plurality of grains132aseparated from one another, and an indium content of the grains132aaccounts for at least 50% of all metal elements of the metal oxide semiconductor layer130a. Preferably, the indium content of the grains132aaccounts for 53% of all of the metal elements of the metal oxide semiconductor layer130a, a gallium content of the grains132aaccounts for 32% of all of the metal elements of the metal oxide semiconductor layer130a, and a zinc content of the grains132aaccounts for 15% of all of the metal elements of the metal oxide semiconductor layer130a. Said percentages of metal content refer to atomic percentages.

To be specific, the passivation layer160ais formed at a temperature that exemplarily ranges from about 100° C. to about 300° C. in the present embodiment. In this manufacturing process, the grains132a(i.e., the precipitates) containing rich indium content are gradually separated from the interface where the metal oxide semiconductor layer130ais in contact with the passivation layer160a, i.e., the portion of the surface S of the metal oxide semiconductor layer130a. A material of the passivation layer160ais, for instance, silicon oxide, silicon nitride, or silicon oxynitride, and a diameter of each of the grains132aranges from about 1 nm to about 100 nm, for instance. So far, the TFT structure100ais substantially formed. In another embodiment of the invention, an annealing process may be performed after the passivation layer160ais formed, and the temperature at which the annealing process is performed exemplarily ranges from about 200° C. to about 400° C. Thereby, the grains132awith the rich indium content may be further separated from the portion of the surface S.

According to the present embodiment shown inFIG. 1A, the TFT structure100ais disposed on the substrate10and includes the metal oxide semiconductor layer130a, the gate110a, the source140a, the drain150a, the gate insulation layer120a, and the passivation layer160a. The metal oxide semiconductor layer130ahas a crystalline surface131athat is constituted by a plurality of grains132a. The grains132aare separated from one another, and an indium content of the grains132aaccounts for at least 50% of all metal elements of the metal oxide semiconductor layer130a. The gate110ais disposed on one side of the metal oxide semiconductor layer130a. The source140aand the drain150aare disposed on the other side of the metal oxide semiconductor layer130a. The gate insulation layer120ais disposed between the gate110aand the metal oxide semiconductor layer130a. The passivation layer160ais disposed on the gate insulation layer120a, and the crystalline surface131aof the metal oxide semiconductor layer130ais in direct contact with the passivation layer160a.

In details, according to the present embodiment, the gate110ais disposed on the substrate10, and the gate insulation layer120acovers the gate110aand a portion of the substrate10. The metal oxide semiconductor layer130ais disposed on the gate insulation layer120a. The source140aand the drain150aexpose the crystalline surface131aof the metal oxide semiconductor layer130a. The passivation layer160acovers the source140a, the drain150a, the gate insulation layer120a, and the crystalline surface131aof the metal oxide semiconductor layer130a. In brief, the TFT structure100adescribed in the present embodiment is a bottom gate TFT structure. In addition, according to the present embodiment, a material of the metal oxide semiconductor layer130ais IGZO, for instance; the gate insulation layer120aand the passivation layer160aare made of silicon oxide, silicon nitride or silicon oxynitride, for instance. A diameter of each of the grains132aranges from about 1 nm to about 100 nm, for instance.

The metal oxide semiconductor layer130adescribed in the present embodiment has the interface (i.e., a portion of the surface S) that is in contact with the passivation layer160aand is constituted by the grains132awhich are separated from one another, and the indium content of the grains132aaccounts for at least 50% of all metal elements of the metal oxide semiconductor layer130a. Besides, conductivity of indium is rather favorable. Hence, the contact resistance between the source140aand the metal oxide semiconductor layer130aor between the drain150aand the metal oxide semiconductor layer130amay be reduced, such that the TFT structure100adescribed herein may have high carrier mobility, high reliability, and high aperture ratio. Moreover, the interface where the metal oxide semiconductor layer130ais in contact with the passivation layer160ahas the grains132a. Accordingly, compared to the conventional oxide semiconductor layer that does not contain the grains, the metal oxide semiconductor layer130adescribed in the present embodiment has a width W that may be reduced without affecting the aperture ratio, so as to save layout space and lower down manufacturing costs.

FIG. 2is a schematic cross-sectional diagram illustrating a TFT structure according to another embodiment of the invention. With reference toFIG. 2, in a method for manufacturing a TFT structure, a source140band a drain150bare formed on a substrate10, and the source140band the drain150bexpose a portion12of the substrate10. A material of the substrate10is, for instance, glass, plastic, or any other suitable materials; a material of the source140aand a material of the drain150bare metal, for instance.

As shown inFIG. 2, a metal oxide semiconductor layer130bis formed on the substrate10, and the metal oxide semiconductor layer130bcovers the source140b, the drain150b, and the portion12of the substrate10exposed by the source140band the drain150b. A material of the metal oxide semiconductor layer130bis IGZO, for instance.

As shown inFIG. 2, a gate insulation layer120bis formed on the substrate10, and the gate insulation layer120bcovers the metal oxide semiconductor layer130b, the source140b, and the drain150b. In particular, the gate insulation layer120bis in direct contact with the metal oxide semiconductor layer130b, so as to form a crystalline surface131bconstituted by a plurality of grains132bseparated from one another, and an indium content of the grains132baccounts for at least 50% of all metal elements of the metal oxide semiconductor layer130b. Preferably, the indium content of the grains132baccounts for 53% of all of the metal elements of the metal oxide semiconductor layer130b, a gallium content of the grains132baccounts for 32% of all of the metal elements of the metal oxide semiconductor layer130b, and a zinc content of the grains132baccounts for 15% of all of the metal elements of the metal oxide semiconductor layer130b. Said percentages of metal content refer to atomic percentages.

To be specific, the gate insulation layer120bis formed at a temperature that exemplarily ranges from about 100° C. to about 400° C. in the present embodiment. In this manufacturing process, the grains132b(i.e., the precipitates) containing rich indium content are gradually separated from the interface where the metal oxide semiconductor layer130bis in contact with the gate insulation layer120b, i.e., the portion of the surface S of the metal oxide semiconductor layer130b. A material of the gate insulation layer120bis, for instance, silicon oxide, silicon nitride, or silicon oxynitride, and a diameter of each of the grains132branges from about 1 nm to about 100 nm, for instance.

With reference toFIG. 2again, a gate110bis formed on the gate insulation layer120b. A material of the gate110bincludes metal, for instance, and the metal herein may be the same as or different from the metal employed for making the source140band the drain150b. This should not be construed as a limitation to the invention.

As shown inFIG. 2, a passivation layer160bis formed on the gate110b, and the passivation layer160bcovers the gate110band the gate insulation layer120b. Here, the passivation layer160bis made of silicon oxide, silicon nitride or silicon oxynitride, for instance. So far, the TFT structure100bis substantially formed. In another embodiment of the invention, an annealing process may be performed after the passivation layer160bis formed, and the temperature at which the annealing process is performed exemplarily ranges from about 200° C. to about 400° C. Thereby, the grains132bwith the rich indium content may be further separated from the portion of the surface S.

According to the present embodiment shown inFIG. 2, the TFT structure100bis disposed on the substrate10and includes the metal oxide semiconductor layer130b, the gate110b, the source140b, the drain150b, the gate insulation layer120b, and the passivation layer160b. The metal oxide semiconductor layer130bhas a crystalline surface131bthat is constituted by a plurality of grains132b. The grains132bare separated from one another, and an indium content of the grains132baccounts for at least 50% of all metal elements of the metal oxide semiconductor layer130b. The gate110bis disposed on one side of the metal oxide semiconductor layer130b. The source140band the drain150bare disposed on the other side of the metal oxide semiconductor layer130b. The gate insulation layer120bis disposed between the gate110band the metal oxide semiconductor layer130b. The passivation layer160bis disposed on the gate insulation layer120b, and the crystalline surface131bof the metal oxide semiconductor layer130bis in direct contact with the gate insulation layer120b.

To be specific, the source140band the drain150bare disposed on the substrate10and expose a portion12of the substrate10. The metal oxide semiconductor layer130bis disposed on the source140band the drain150band covers the portion12of the substrate10. The gate insulation layer120bis disposed on the metal oxide semiconductor layer130band covers the metal oxide semiconductor layer130b, the source140b, and the drain150b. The gate110bis disposed on the gate insulation layer120b, and the passivation layer160bcovers the gate110band the gate insulation layer120b. In addition, according to the present embodiment, a material of the metal oxide semiconductor layer130bis IGZO, for instance; the gate insulation layer120band the passivation layer160bare made of silicon oxide, silicon nitride or silicon oxynitride, for instance. A diameter of each of the grains132branges from about 1 nm to about 100 nm, for instance.

The metal oxide semiconductor layer130bdescribed in the present embodiment has the interface that is in contact with the gate insulation layer120band is constituted by the grains132bwhich are separated from one another, and the indium content of the grains132baccounts for at least 50% of all metal elements of the metal oxide semiconductor layer130b. Besides, conductivity of indium is rather favorable. Hence, the contact resistance between the source140band the metal oxide semiconductor layer130bor between the drain150band the metal oxide semiconductor layer130bmay be reduced, such that the TFT structure100bdescribed herein may have high carrier mobility, high reliability, and high aperture ratio. Moreover, the interface where the metal oxide semiconductor layer130bis in contact with the gate insulation layer120bhas the grains132b. Accordingly, compared to the conventional oxide semiconductor layer that does not contain the grains, the metal oxide semiconductor layer130bdescribed in the present embodiment has a width that may be reduced without affecting the aperture ratio, so as to save layout space and lower down manufacturing costs.

To sum up, the metal oxide semiconductor layer described herein has the interface that is in contact with the gate insulation layer or the passivation layer and is constituted by the grains which are separated from one another, and the indium content of the grains accounts for at least 50% of all metal elements of the metal oxide semiconductor layer. Besides, conductivity of indium is rather favorable. Therefore, the contact resistance between the source and the metal oxide semiconductor layer or between the drain and the metal oxide semiconductor layer may be reduced. As such, the TFT structure described herein may have high carrier mobility, high reliability, and high aperture ratio. Moreover, the interface where the metal oxide semiconductor layer is in contact with the passivation layer or the gate insulation layer has the grains. Accordingly, compared to the conventional oxide semiconductor layer that does not contain the grains, the metal oxide semiconductor layer described herein has the width that may be reduced without affecting the aperture ratio, so as to save layout space and lower down manufacturing costs.