Non-volatile memory device

A non-volatile memory device is provided. The non-volatile memory device includes a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated. An insulating layer that contacts with a top surface of the conductive pattern is formed along side surfaces of the electrode structure. The top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

This application claims priority from Korean Patent Application No. 10-2015-0136347 filed on Sep. 25, 2015 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The herein disclosed subject matter relates to a non-volatile memory device.

BACKGROUND

A semiconductor memory device is a storage device that is achieved using a semiconductor material typically from the Group IV elements or compounds such as, silicon (Si), germanium (Ge), gallium arsenide (GaAs) or indium phosphide (InP) and the like. Semiconductor memory devices are largely classified into volatile memory devices and non-volatile memory devices.

In a volatile memory device saved data disappears when the supply of a power source cuts off. Types of volatile memory devices include a static RAM (SRAM), a dynamic RAM (DRAM), synchronous DRAM (SDRAM) and the like. In a non-volatile memory device the saved data is maintained even when the supply of a power source cuts off. Types of non-volatile memory devices include a flash memory device, a read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), electrically erasable and programmable ROM (EEPROM), a resistive memory device (e.g., a phase-change RAM (PRAM), a ferroelectric RAM (FRAM), a resistive RAM (RRAM) and the like.

To satisfy the consuming public's demand for high performance and low priced semiconductor memory devices has led to increasing degrees of the integration of non-volatile memory devices. However, in the case of a two-dimensional or planar memory device, the degree of integration is limited by an area occupied by a unit memory cell. Thus, three-dimensional memory devices with vertically disposed unit memory cells have been recently developed.

Prior art memory cells are formed with common source line structures which extend perpendicularly from the substrate to a height of equal to or beyond that of adjacent channel structures. During the formation of these prior art devices a slit can be formed within the common source line structure. Moreover, during the memory cell formation processes, a concentration of F-gas can be generated which fills the slit. The filled slit can thereafter cause stress within the formed memory cell which increases the failure rate.

SUMMARY

Aspects of the present exemplary implementations of the herein described subject matter provide a non-volatile memory device with improved reliability by removing a slit generated in a common source line and by reducing stress.

According to exemplary implementations of the herein described subject matter, there is provided a non-volatile memory device comprising a channel structure that is located on a substrate and extends perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, an electrode structure that is located between the channel structure and the conductive pattern, and comprises a plurality of gate patterns and a plurality of insulation patterns that are alternately laminated; and an insulating layer that is in contact with a top surface of the conductive pattern and is formed along side surfaces of the electrode structure, wherein the top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

In some exemplary implementations, the top surface of the conductive pattern is formed to be higher than the top surface of the substrate.

In some exemplary implementations, the non-volatile memory device further comprises a spacer that is disposed between the conductive pattern and the electrode structure and is formed along side surfaces of the conductive pattern and side surfaces of the insulating layer, and a bottom surface of the conductive pattern is formed to be lower than a bottom surface of the spacer.

In some exemplary implementations, the plurality of gate patterns comprises first to n-th gate patterns (n is a natural number) that are sequentially laminated in a direction away from the substrate, and a top surface of the conductive pattern is disposed between the k-th gate pattern (k is a natural number smaller than n) and the k+1st gate pattern.

In some exemplary implementations, the non-volatile memory device further comprises a first interlayer insulating film that covers the channel structure and the electrode structure; and a metal contact structure that is in contact with the top surface of the conductive pattern through the first interlayer insulating film.

In some exemplary implementations, the non-volatile memory device further comprises a second interlayer insulating film that covers the first insulating interlayer film a first conductive stud that is disposed on the metal contact structure through the second interlayer insulating film and a second conductive stud that is disposed on the channel structure through the first and second interlayer insulating films.

In some exemplary implementations, the first conductive stud and the metal contact of the metal contact structure are integrally formed.

According to an exemplary implementation, there is provided a non-volatile memory device comprising a plurality of channel structures that are located on a substrate and extend perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structure, a first interlayer insulating film that covers the plurality of channel structures and the conductive pattern. A metal contact, disposed on the conductive pattern, is electrically connected to the conductive pattern, passes through the first interlayer insulating film, and has a bottom surface formed to be lower than top surfaces of the plurality of channel structures.

In some exemplary implementations, a top surface of the conductive pattern is formed to be higher than a top surface of the substrate and to be lower than the top surfaces of the plurality of channel structures.

In some exemplary implementations, the plurality of channel structures is disposed in a honeycomb shape.

In some exemplary implementations, the plurality of channel structures comprises a dummy channel structure and an active channel structure, and the dummy channel structure closest to the metal contact is disposed to be closer to the metal contact than the active channel structure.

In some exemplary implementations, the conductive pattern comprises a first portion including the metal contact, and a second portion adjacent to the first portion, and a width of the first portion measured in a first direction parallel to the top surface of the substrate is larger than a width of the second portion measured in the first direction.

According to an exemplary implementation, there is provided a non-volatile memory device comprising first and second channel structures that are located on a substrate and extend perpendicularly to the substrate, a conductive pattern that extends perpendicularly to the substrate and is spaced apart from the channel structures, a first interlayer insulating film that covers the plurality of channel structures and the conductive pattern, a second interlayer insulating film that covers the first interlayer insulating film, a metal contact that is disposed on the conductive pattern and penetrates through the first interlayer insulating film, a first conductive stud that is disposed on the metal contact, penetrates through the second interlayer insulating film and is electrically connected to the conductive pattern and a second conductive stud that is disposed only on the first channel structure, is not disposed on the second channel structure and penetrates through the first and second interlayer insulating films.

In some exemplary implementations, a distance between the first channel structure and the metal contact is larger than a distance between the first channel structure and the metal contact.

In some exemplary implementations, wherein the top surface of the conductive pattern is formed to be lower than the top surface of the channel structure.

However, exemplary implementations are not restricted to the ones set forth herein. The above and other exemplary implementations will become more apparent to those of ordinary skill in the art to which the herein described subject matter pertains by referencing the detailed description of the exemplary implementations given below.

Other specific matters of the exemplary implementations are included in the detailed description and the drawings.

The above and other aspects and features of the exemplary implementations will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Advantages and features of the exemplary implementations and methods of accomplishing the same may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings. The exemplary implementations may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the disclosure to those skilled in the art, and the present inventive concepts will only be defined by the appended claims.

In some exemplary implementations a three-dimensional (3D) memory array is provided. The three-dimensional memory array may be monolithically formed in one or more physical layers of a memory cell array that has an electrical circuitry associated with the operation of the memory cell, and an active area formed on a silicon substrate. The associated electrical circuitry may be formed inside or on the substrate. The term ‘monolithic’ may mean that layers of each level of the array are directly placed on the layers of each lower levels of the array.

In some exemplary implementations, the three-dimensional memory array may include a ‘vertical NAND string’ in which at least one memory cell is disposed on the other memory cell and vertically extends. At least one memory cell may include a charge storage film. The three-dimensional memory array may include bit lines and/or word lines shared between the levels, and a plurality of levels.

Hereinafter, a non-volatile memory device according to some exemplary implementations will be described with reference toFIGS. 1 to 25.

FIG. 1is a conceptual diagram for explaining a non-volatile memory device according to some embodiments of the present inventive concept.FIG. 2is a layout diagram for explaining a non-volatile memory device according to an embodiment of the present inventive concept.FIG. 3is a cross-sectional view taken along the line A-A ofFIG. 2.FIG. 4is a cross-sectional view taken along the line B-B ofFIG. 2.FIG. 5is a cross-sectional view taken along the line C-C ofFIG. 2.FIG. 6is an enlarged view of an area TS1ofFIG. 2.

As shown inFIG. 1, a memory cell array of a non-volatile memory device according to some embodiments of the present inventive concept may include a plurality of memory blocks (BLK1to BLKn; where n is a natural number).

Each of the memory blocks BLK1to BLKn may extend in first to third directions (x, y and z). The memory blocks BLK1to BLKn may be three-dimensionally arranged. As illustrated, the first to third directions (x, y and z) may be directions intersecting with each other or may be directions different from each other. For example, the first to the third directions (x, y and z) may be, but not limited to, directions intersecting with each other at right angles.

As shown inFIGS. 2 to 6, each of the memory blocks (BLKi, where 1≦I≦n, i is a natural number) may include channel structures120and130, an electrode structure110, a conductive pattern220, an insulating layer230, metal contact structures310and315, a first interlayer insulating film170, a second interlayer insulating film180, a first conductive stud325and a second conductive stud425that are formed on a substrate100.

The substrate100may include a semiconductor substrate such as a silicon substrate, a germanium substrate or a silicon-germanium substrate, silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

The electrode structure110may include a plurality of gate patterns (GSL, WL0to WLn and SSL) and a plurality of insulation patterns112that are located between the channel structures120and130and the conductive pattern220and are alternately laminated. Specifically, the electrode structure110may include a plurality of insulation patterns112, a plurality of gate patterns (GSL, WL0to WLn and SSL) (where, n is a natural number) and a block layer114. The gate insulating layer120may include a tunnel layer121and a trap layer122.

The plurality of insulation patterns112may be sequentially laminated on the substrate100to be spaced apart from each other in a direction away from the substrate100. As illustrated inFIG. 3, each of the plurality of insulation patterns112may be formed so as to extend long in a direction parallel to a top surface of the substrate100. The insulation pattern112may be, but not limited to, oxide.

A plurality of gate patterns (GSL, WL0to WLn and SSL) may be disposed between the plurality of insulation patterns112. The plurality of gate patterns (GSL, WL0to WLn and SSL) is formed long in a direction parallel to the top surface of the substrate100, and may be laminated in a direction away from the substrate100.

In some exemplary implementations of the herein described subject matter the lowest gate pattern GSL may be provided as a ground selection line (hereinafter, referred to as GSL), and the highest gate pattern SSL may be provided as a string selection line (hereinafter, referred to as SSL). The gate patterns (WL0to WLn) between the GSL and the SSL may be provided as word lines.

A plurality of gate patterns (GSL, WL0to WL and SSL) may be formed of a conductive material, for example, a conductive material such as tungsten (W), cobalt (Co) and nickel (Ni) or a semiconductor material such as silicon, but are not limited thereto.

The block layer114may be disposed between the channel structures120and130and the plurality of gate patterns (GSL, WL0to WLn and SSL). The block layer114may be formed to extend long in the direction away from the substrate100. The block layer114may be formed in a direction parallel to the substrate100in a zigzag form.

At this time, a non-volatile memory cell TS1may be defined in a region in which the channel structures120and130intersect with the plurality of gate patterns (GSL, WL0to WLn and SSL). Details of the non-volatile memory cell TS1will be described below referring toFIGS. 6 to 8.

The channel structures120and130are formed to extend long in the direction away from the substrate100. Specifically, the channel structures120and130are disposed on the substrate100in the form of a pillar and are formed to penetrate through the plurality of laminated insulation patterns112. Each of the plurality of gate patterns (GSL, WL0to WLn and SSL) may be formed between the plurality of laminated insulation patterns112. The plurality of gate patterns (GSL, WL0to WLn and SSL) may be formed to intersect with the channel structures120and130. Although the plurality of gate patterns (GSL, WL0to WLn and SSL) has been described to have the same thickness, the present inventive concept is not limited thereto, and the plurality of gate patterns may also have thicknesses different from each other.

The channel structures120and130may include a channel pattern130and a gate insulating layer120.

The channel pattern130may be formed to extend perpendicularly to the substrate100. The channel pattern130, for example, may be a semiconductor material such as single crystal silicon, but it is not limited thereto. Although it is not clearly illustrated in the drawings, the channel pattern130may have a hollow cylindrical shape, a cup shape, a hollow rectangular parallelepiped shape, a solid pillar shape or the like.

The gate insulating layer120may be formed to wrap the side surfaces of the channel pattern130. The gate insulating layer120may be conformally formed in a lengthwise direction of the channel pattern130. The top surface of the channel pattern130and the top surface of the gate insulating layer120may be located on the same plane.

The gate insulating layer120may include a tunnel layer121and a trap layer122. That is, the tunnel layer121and the trap layer122may be disposed along the lengthwise direction of the channel patterns130. The tunnel layer121and the trap layer122may be disposed between the plurality of gate patterns (GSL, WL0to WLn and SSL) and the channel pattern130. Specifically, for example, the tunnel layer121and the trap layer122may be formed along the channel pattern130to penetrate through the plurality of insulation patterns112.

The tunnel layer121is a portion through which electric charge passes, and for example, may be formed by a silicon oxide film or a double layer of the silicon oxide film and a silicon nitride film.

The trap layer122is a portion in which the electric charge after passing through the tunnel layer121is stored. For example, the trap layer122may be formed of a nitride film or a high dielectric constant (high-k) film. The nitride film, for example, may contain one or more of silicon nitride, silicon oxynitride, hafnium oxynitride, zirconium oxynitride, hafnium silicon oxynitride or hafnium aluminum oxynitride. The high dielectric constant film, for example, may contain one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide or lead zinc niobate.

As shown inFIG. 6, the block layer114may be disposed between an insulation pattern (112ainFIG. 6) disposed on the upper side and the gate pattern (WL1inFIG. 6), between an insulation pattern (112binFIG. 6) disposed on the lower side and the gate pattern WL1, and between the channel pattern130(or the trap layer122) and the electrode WL1. The block layer114may be conformally formed depending on the shapes of the insulation patterns112aand112band the channel pattern130.

The block layer114may be a single layer or multiple layers. The block layer114may include silicon oxide or insulating metal oxide having a dielectric constant greater than silicon oxide. For example, the block layer may be formed of a composite layer that is laminated by a high-dielectric constant material such as aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide, lanthanum aluminum oxide or dysprosium scandium oxide, or combinations thereof. A case where there is a single block layer114is illustrated in the drawings, but it is not limited thereto. For example, the block layer114, for example, may be a laminate of silicon oxide and aluminum oxide.

Meanwhile, the configurations of the tunnel layer121, the trap layer122and the block layer114illustrated inFIG. 6are merely an example. For example, the tunnel layer121, the trap layer122and the block layer114may be disposed along the lengthwise direction of the channel pattern130. This will be described below in detail with reference toFIGS. 7 and 8.

A channel pad135may be formed on the channel structures120and130. A bottom surface of the channel pad135may be in contact with the top surfaces of the channel structures120and130. The channel pad135, for example, may contain polysilicon doped with impurities.

The top surface of the channel pad135may be disposed on the same plane as the top surface of the electrode structure110. At this time, a highest surface of the gate insulating layer120and a highest surface of the block layer114may be disposed on the same plane as the top surface of the channel pad135. However, the present inventive concept is not limited thereto.

The conductive pattern220may be disposed on the substrate100to extend perpendicularly to the substrate100and to be spaced apart from the channel structures120and130. In this example, the conductive pattern220is in contact with the substrate100and is embedded in a trench formed in the substrate100. The conductive pattern220may operate as a common source line (CSL).

The conductive pattern220may be located within the first trench201which penetrates through the electrode structure110. The conductive pattern220may be disposed between different electrode structures110. The top surface of the conductive pattern220may be formed to be higher than the top surface of the substrate100and to be lower than the top surfaces of the channel structures120and130.

The top surface of the conductive pattern220may be formed to be lower than one surface of the plurality of gate patterns. Specifically, when the electrode structure110includes first to n-th gate patterns (WL0to WLn) that are sequentially laminated in a direction away from the substrate100, the top surface of the conductive pattern220may be disposed between the k-th gate pattern and the k+1st gate pattern (k is a natural number smaller than n).

For example, as shown inFIG. 3, the top surface of the conductive pattern220may be higher than the top surface of the first gate pattern WL0and may be lower than the top surface of the second gate pattern WL1. However, the present inventive concept is not limited thereto, and the top surface of the conductive pattern220may be freely adjusted within a range between the top surface of the substrate100and the top surfaces of the channel structure120and130. For example, the top surface of the conductive pattern220may be higher than the top surface of the ground selection line GSL but lower than the top surface of the first gate pattern WL0.

The conductive pattern220may include a metallic material or a metallic compound. For example, the conductive pattern220may contain tungsten (W). However, the present inventive concept is not limited thereto, and for example, may contain at least one of polysilicon, a metal silicide compound, a conductive metal nitride and metals.

The insulating layer230may be formed on the conductive pattern220within the first trench201. The insulating layer230is in contact with the top surface of the conductive pattern220and may be formed along the side surfaces of the electrode structure110. The top surface of the insulating layer230may be located on the same plane as the top surface of the channel pad135or the top surface of the electrode structure110. The insulating layer230may be formed of a material having a dielectric constant. In some embodiments of the present inventive concept, the insulating layer230, for example, may be made of a material such as HfO2, Al2O3, ZrO2 and TaO2, but the present inventive concept is not limited thereto.

The spacer210is disposed between the conductive pattern220and the electrode structure110and between the insulating layer230and the electrode structure110. A spacer210may be formed along the side surfaces of the conductive pattern220and the side surfaces of the insulating layer230. The spacer210may be formed to wrap the conductive pattern220and the insulating layer230. The spacer210may be conformally formed along the side surfaces of the electrode structure110. The top surface of the spacer210may be located on the same plane as the top surface of the channel pad135, the top surface of the electrode structure110or the top surface of the insulating layer230. The spacer210includes at least one insulating material, e.g., silicon oxide.

The spacer210may be formed along the side walls of the first trench201. The bottom surface of the spacer210may be formed to be lower than the top surface of the substrate100. However, the bottom surface of the spacer210may be formed to be higher than the bottom surface of the conductive pattern220.

A first interlayer insulating film170may be formed to cover the channel structures120and130, the channel pad135, the electrode structure110and the insulating layer230. The first interlayer insulating film170may take charge of the electrical insulation between semiconductor devices located below the first interlayer insulating film170and semiconductor elements located above the first interlayer insulating film170.

The metal contact structures310and315may be formed to come into contact with the top surface of the conductive pattern220through the first interlayer insulating film170and the insulating layer230. The metal contact structures310and315may include a metal contact315and a first barrier metal310.

The first barrier metal310may be formed along the side surface of the insulating layer230and the top surface of the conductive pattern220. The first barrier metal310may be conformally formed on the inner surface of the second trench203. That is, the first barrier metal310may be formed on both side surfaces and the bottom surface of the second trench203with a constant thickness. Otherwise, although it is not clearly illustrated in the drawings, the first barrier metal310may also be formed only on the bottom surface of the second trench203with a constant thickness. The first barrier metal310may contain titanium (Ti), titanium nitride (TiN) or tungsten nitride (WN). The first barrier metal310may be formed using PVD, CVD or ILD methods. However, the present inventive concept is not limited thereto.

The metal contact315may be formed on the first barrier metal310. The metal contact315may be formed to embed the second trench203. The metal contact315may be electrically connected to the conductive pattern220. The metal contact315may include a metallic material or a metallic compound. For example, the metal contact315may contain tungsten (W). However, the present inventive concept is not limited thereto, and for example, may contain at least one of polysilicon, a metal silicide compound, a conductive metal nitride and metals.

The bottom surfaces of the metal contact structures310and315may be formed to be lower than the top surfaces of the channel structures120and130. The reason is that the top surface of the conductive pattern220and the bottom surfaces of the metal contact structure310and315are disposed on the same plane. The metal contact315may be formed together in a process of forming the metal contact315included in a PERI region around the memory block. However, the present inventive concept is not limited thereto.

The second interlayer insulating film180may be formed to cover the first interlayer insulating film170. The second interlayer insulating film180may take charge of the electrical insulation between the semiconductor elements located below the second interlayer insulating film180and the semiconductor elements located above the second interlayer insulating film180. The second interlayer insulating film180may include the same material as the first interlayer insulating film170, but the present inventive concept is not limited thereto.

A first conductive stud325may be formed on the metal contact structures310and315. The first conductive stud325may be formed in a third trench205. At this time, the third trench205may be formed to partially expose the metal contact structures310and315. Thus, the first conductive stud325may be formed to penetrate through the second interlayer insulating film180. The first conductive stud325may contain tungsten (W). However, the present inventive concept is not limited thereto, and may contain, for example, at least one of polysilicon, a metal silicide compound, a conductive metal nitride and metals.

A second barrier metal320may be formed between the first conductive stud325and the third trench205. The second barrier metal320may be conformally formed on the inner surface of the third trench. That is, the second barrier metal320may be formed on both side surfaces and the bottom surface of the third trench205with a constant thickness. Otherwise, although it is not clearly illustrated in the drawings, the second barrier metal320may be formed only on the bottom surface of the third trench at a certain thickness. The second barrier metal320may contain titanium (Ti), titanium nitride (TiN) or tungsten nitride (WN). The second barrier metal320may be formed using PVD, CVD or ILD methods. However, the present inventive concept is not limited thereto.

The channel structures120and130illustrated inFIG. 3may be dummy channel structures DM1and DM2. The conductive stud is not disposed on the top surfaces of the dummy channel structures DM1, DM2. Thus, the dummy channel structures DM1and DM2do not operate as a channel.

Meanwhile, the channel structures120and130illustrated inFIG. 4may be active channel structures C1and C2. A second conductive stud425and a third barrier metal420may be formed on the active channel structures C1and C2. Although it is not clearly illustrated in the drawings, the second conductive stud425may electrically connect the active-channel structures C1and C2and the other node through the wirings.

The second conductive stud425may be formed on the active channel structures C1and C2. However, the second conductive stud425may not be formed on the dummy channel structures DM1and DM2.

The second conductive stud425may be formed in the fourth trench207. At this time, a fourth trench207may be formed to expose a part of the active channel structures C1and C2. Thus, the second conductive stud425may be formed to penetrate through the first interlayer insulating film170and the second interlayer insulating film180. The second conductive stud425may be made of the same material as the first conductive stud325. That is, the first conductive stud325and the second conductive stud425may be formed through the same process. However, the present inventive concept is not limited thereto.

A third barrier metal420may be formed between the second conductive stud425and the fourth trench207. The third barrier metal420may be conformally formed on the inner surface of the fourth trench. That is, the third barrier metal420may be formed on both side surfaces and the bottom surface of the fourth trench207with a constant thickness. Otherwise, although it is not clearly illustrated in the drawings, the third barrier metal420may be formed only on the bottom surface of the fourth trench with a constant thickness. The third barrier metal420may be made of the same material as the second barrier metal320. That is, the second barrier metal320and the third barrier metal420may be formed through the same process. However, the present inventive concept is not limited thereto.

As shown inFIGS. 2, 4 and 5, the metal contact structures310and315may be located closest to dummy channel structures DM1and DM2of the plurality of channel structuress120and130. That is, a distance between the metal contact structures310and315and the dummy channel structures DM1and DM2(e.g., DM1) may be smaller than a distance between the metal contact structures310and315and the active channel structures C1and C2(e.g., C3). In other words, the channel structures120and130close to the metal contact structures310and315may be used as dummy channel structures DM1and DM2. However, the present inventive concept is not limited thereto.

A plurality of channel structures120and130may be disposed in a honeycomb shape. That is, a plurality of adjacent channel structures120and130may be continuously arranged in a hexagonal shape.

When the plurality of channel structures120and130includes first to fourth channel structures (C3, C1, C4and DM1), the first channel structure C3may be disposed to be located at the same distance L1as the second to fourth channel structures (C1, C4and DM1).

The conductive pattern220may extend long in a direction parallel to the substrate100on the X-Y plane, and the plurality of channel structures120and130may be symmetrically disposed about the conductive pattern220.

In the case of the related art, the top surface of the conductive pattern is formed to be the same as or higher than the top surface of the channel structure. Accordingly, the conductive pattern is formed vertically long and is also formed long on the left and right sides in a line pattern. A phenomenon in which an F-gas is concentrated in one place through the slit area within the conductive pattern frequently occurs in this process, and a case where HF generated in this process etches tungsten (W) or ONO occurs. This acts as a factor of increasing a failure rate of the non-volatile memory device. Further, the line type conductive pattern also acts as a factor of increasing the stress.

Thus, according to the present exemplary implementations of the disclosed subject matter, the slit area and the F-gas are removed by partially removing the top of the conductive pattern after generating the conductive pattern. That is, the top of the conductive pattern is etched so that the height of the conductive pattern is lower than the top surface of the channel structure. Also, a metal contact structure that takes charge of the electrical connection between the conductive stud and the conductive pattern is added.

Some exemplary implementations can remove the slit area of the conductive pattern formed by the F-gas and reduce the stress applied by the conductive pattern. Thus, the exemplary implementations have the effect of reducing the failure rate of the non-volatile memory device and improving the performance.

FIGS. 7 and 8are cross-sectional views for explaining some application examples of the non-volatile memory device according to exemplary implementations.FIGS. 7 and 8may provide other examples to be used in place of the non-volatile memory cell TS1illustrated inFIG. 6. For convenience of description, differences from the description ofFIG. 6will be mainly described.

As shown inFIG. 7, in the application example of the non-volatile memory device according to some exemplary implementations, a tunnel layer121, a trap layer122and a block layer114may be formed on the side walls of the channel pattern130. The tunnel layer121, the trap layer122and the block layer114may be disposed along the lengthwise direction of the channel pattern130. More specifically, the tunnel layer121, the trap layer122and the block layer114may be formed along the channel pattern130to penetrate through the plurality of insulation patterns112.

Further, as shown inFIG. 8, in some application examples of the non-volatile memory device according to some exemplary implementations, the tunnel layer121, the trap layer122and the block layer114may be disposed between the insulation pattern (112ainFIG. 8) disposed on the upper side and and the gate pattern (WL1inFIG. 8), between the insulation pattern (112binFIG. 8) disposed on the lower side and the gate pattern WL1, and between the channel pattern130and the the pattern WL1. That is, the tunnel layer121, the trap layer122and the block layer114may be conformally formed depending on the shapes of the insulation patterns112aand112band the channel pattern130. However, the present inventive concept is not limited thereto.

FIG. 9is a cross-sectional view for illustrating a non-volatile memory device according to some exemplary implementations.FIG. 10is a cross-sectional view for illustrating a non-volatile memory device according to some exemplary implementations. For convenience of description, hereinafter, the repeated description of the same matters as in the above-described example will be omitted, and the differences will be mainly described.

As shown inFIGS. 9 and 10, non-volatile memory devices2aand2baccording to some exemplary implementations may be configured and operated substantially in the same manner as the non-volatile memory device1described with reference toFIGS. 1 to 8.

However, the height of the top surface of the conductive pattern220and the height of the bottom surface of the metal contact structures310and315may vary. Since the top surface of the conductive pattern220and the bottom surfaces of the metal contact structures310and315are disposed on the same plane, the description will be provided based on the top surface of the conductive pattern220.

The top surface of the conductive pattern220is higher than the top surface of the substrate100, and may vary within a range lower than the top surface of the channel structures120and130.

For example, as shown inFIG. 9, the top surface of the conductive pattern220is higher than the top surface of the substrate100, and may be located below the gate pattern included in the electrode structure110. That is, a height D41of the conductive pattern220may be larger than a height D32between the top surface of the substrate100and the bottom surface of the conductive pattern220.

As still another example, as shown inFIG. 10, when the electrode structure110includes first to n-th gate patterns (WL0to WLn) that are sequentially laminated in a direction away from the substrate100, the top surface of the conductive pattern220may be disposed between the k-th gate pattern and k+1st gate pattern (k is a natural number smaller than n). For example, the top surface of the conductive pattern220may be higher than the top surface of the second gate pattern WL1and may be lower than the top surface of the third gate pattern WL2. As a result, the height D42of the conductive pattern220may be larger than the height D32between the top surface of the substrate100and the bottom surface of the conductive pattern220.

Further, the top surface of the conductive pattern220may be formed to overlap the second gate pattern WL1to be lower than the top surface of the second gate pattern WL1and higher than the bottom surface of the second gate pattern WL1. However, the present inventive concept is not limited thereto.

The bottom surface of the spacer210may be formed to be higher than the bottom surface of the conductive pattern220. That is, a spacer may be present between the bottom surface of the spacer210and the bottom surface of the conductive pattern220. For example, on the basis of the top surface of the substrate100, a depth D31to the bottom surface of the spacer210may be smaller than a depth D32to the bottom surface of the conductive pattern220.

FIG. 11is a cross-sectional view for illustrating the non-volatile memory device according to some exemplary implementations. For convenience of description, hereinafter, the repeated description of the same matters as in the above-described example will be omitted, and the differences will be mainly described.

As shown inFIG. 11, a non-volatile memory device3according to some embodiments of the present inventive concept may be configured and operated substantially in the same manner as the non-volatile memory device1described with reference toFIGS. 1 to 8.

However, the first conductive stud325and the metal contact315of the metal contact structures310and315may be integrally formed. Accordingly, the third conductive stud435may be electrically connected to the conductive pattern220through the first interlayer insulating film170and the second interlayer insulating film180.

Specifically, a fifth trench209may be formed through the first interlayer insulating film170and the second interlayer insulating film180so as to expose a part of the top surface of the conductive pattern220.

The fourth barrier metal430may be conformally formed on the inner surface of the fourth trench. That is, the fourth barrier metal430may be formed along the side surfaces of the insulating layer230, the top surface of the conductive pattern220, the side surfaces of the first interlayer insulating film170and the side surfaces of the second interlayer insulating film180. The fourth barrier metal430may be formed on both side surfaces and the bottom surface of the fifth trench209with a constant thickness. The fourth barrier metal430includes the same material as the third barrier metal420and may be formed in the same process.

The third conductive stud435may be formed on the fourth barrier metal430. The third conductive stud435may be formed to embed the fifth trench209. The third conductive stud435may be electrically connected to the conductive pattern220. The third conductive stud435includes the same material as the second conductive studs425and may be formed in the same process. However, the present inventive concept is not limited thereto.

FIG. 12is a layout diagram for explaining a non-volatile memory device according to some exemplary implementations.FIG. 13is a cross-sectional view taken along the line A-A inFIG. 12. For convenience of description, hereinafter, the repeated description of the same matters as in the above-described example will be omitted, and the differences will be mainly described.

As shown inFIG. 12, a non-volatile memory device4according to some exemplary implementations may be configured and operated substantially in the same manner as the non-volatile memory device1described with reference toFIGS. 1 to 8. Thus, each of the cross-sections taken along the line B-B and the line C-C may be the same as those ofFIGS. 4 and 5.

However, the conductive pattern220may include a first portion221including the metal contact315, and a second portion222adjacent to the first portion221. The second portion222may correspond to both side surfaces of the first portion221. At this time, a width W3of the first portion221measured in a first direction parallel to the top surface of the substrate100may be formed to be larger than a width W4of the second portion222measured in the first direction. That is, the first portion221may be convexly formed in the X-Y plane and may be formed to have a thickness different from the second portion222adjacent to the first portion221.

Thus, a distance L2between the channel structure (e.g., DM1) closest to the first portion221and the first portion221may be smaller than a distance L3between the channel structure (e.g., C4) closest to the second portion222and the second portion222. However, the present inventive concept is not limited thereto.

Thus, as shown inFIG. 13, the width W2of the bottom surface of the conductive pattern220may be formed to be larger than the width W1of the bottom surface of the conductive pattern220illustrated inFIG. 3. Further, the width of the insulating layer230between the spacer210and the metal contact structures310and315and the widths of the metal contact structures310and315may also be formed to be larger than those of the non-volatile memory device illustrated inFIG. 3. However, the present inventive concept is not limited thereto.

FIG. 14is a block diagram for illustrating a memory system according to some embodiments of the present inventive concept.

As shown inFIG. 14, a memory system1000includes a non-volatile memory device1100and a controller1200.

The non-volatile memory device1100may be at least one of the non-volatile memory device according to some exemplary implementations described with reference toFIGS. 1 to 13.

The controller1200is connected to a host and a non-volatile memory device1100. The controller1200is configured to access the non-volatile memory device1100in response to a request from a host. For example, the controller1200is configured to control the operations of read, write, erase and background of the non-volatile memory device1100. The controller1200is configured to provide an interface between the non-volatile memory device1100and the host. The controller1200is configured to drive a firmware for controlling the non-volatile memory device1100.

As an example, the controller1200further includes well-known constituent elements such as a random access memory (RAM), a processing unit, a host interface and a memory interface. The RAM is used as at least as one of an operating memory of the processing unit, a cache memory between the non-volatile memory device1100and the host, and a buffer memory between the non-volatile memory device1100and the host. The processing unit controls various operations of the controller1200.

The host interface includes a protocol for performing a data exchange between the host and the controller1200. As an example, the controller1200is configured to communicate with outside (host) through at least one of various interface protocols, such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol and an integrated drive electronic (IDE) protocol. The memory interface interfaces with the non-volatile memory device1100. For example, the memory interface includes a NAND interface or a NOR interface.

The memory system1000may be configured to further include an error correction block. The error correction block is configured to detect and correct an error of data that is read from the non-volatile memory device1100, using an error correction code ECC. As an example, the error correction block is provided as a constituent element of the controller1200. The error correction block may be provided as a component of the non-volatile memory device1100.

The controller1200and the non-volatile memory device1100may be integrated as a single semiconductor device. As an example, the controller1200and the non-volatile memory device1100may be integrated as a single semiconductor device to constitute a memory card. For example, the controller1200and the non-volatile memory device1100is integrated as a single semiconductor device to constitute a memory card, such as a PC card (personal computer memory card international association: PCMCIA), a compact flash card (CF), a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC and MMCmicro), a SD card (SD, mini SD, microSD and SDHC) and a universal flash storage device (UFS).

The controller1200and the non-volatile memory device1100may be integrated as a single semiconductor device to constitute a semiconductor drive (solid state drive: SSD). The semiconductor drive SSD includes a storage device configured to store data in the semiconductor memory. When the memory system10is utilized as the semiconductor drive SSD, the operating speed of the host connected to the memory system1000is greatly improved.

As another example, the memory system1000is provided as one of various constituent elements of an electronic device, such as a computer, an Ultra Mobile PC (UMPC), a work station, a net-book computer, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3-dimensional television set, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, devices capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, electronic devices, an RFID device or one of various components constituting a computing system.

As an example, the non-volatile memory device1100or the memory system1000may be mounted as various forms of packages. For example, the non-volatile memory device1100or the memory system1000may be packaged and mounted, by methods such as Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline (TSOP), Thin Quad Flatpack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-Level Fabricated Package (WFP) and Wafer-Level Processed Stack Package (WSP).

FIGS. 15 through 25are intermediate step diagrams for illustrating a method of manufacturing a non-volatile memory device according to some exemplary implementations. Hereinafter, a method of manufacturing the non-volatile memory device according to some exemplary implementations will be described with reference toFIGS. 15 through 25.

First, as shown inFIG. 15, the channel structures120and130and the electrode structure110are formed on the substrate100. As a method for forming the channel structures120and130and the electrode structure110, it is possible to use a method of manufacturing a three-dimensional non-volatile memory device disclosed in the related art.

Next, the first trench201that partially exposes the substrate100through the electrode structure110is formed. The bottom surface of the first trench201may be formed to be lower than the top surface of the substrate100. The first trench201may be disposed between the plurality of channel structures120and130, and may partially expose the gate pattern and the block layer114included in the electrode structure110. The first trench201may have a tapered shape in which its width becomes wider as it goes from the top to the bottom.

Next, as shown inFIG. 16, a spacer layer210L is conformally formed along the side surfaces and bottom surface of the first trench201. The spacer layer210L may contain at least one insulating material, e.g., silicon oxide.

Next, as shown inFIG. 17, through the etching process, the spacer layer210L disposed on the bottom surface of the first trench201and the top surfaces of the channel structures120and130and the electrode structure110is removed. The bottom surface of the first trench201may be formed to be deeper than the bottom surface of the spacer210in the etching process. Therefore, a further step may occur on the bottom surface of the first trench201. Both the anisotropic etching and the isotropic etching may be used in the etching process, but the present inventive concept is not limited thereto. Thus, the spacer210may be left only on the side walls of the electrode structure110.

Next, referring toFIG. 18, the conductive layer220L is formed in the first trench201. The conductive layer220L is located on the spacer210and may extend long along the top surface of the spacer210, and may fill up the bottom of the first trench201. The conductive layer220L fills up only the bottom of the first trench201and may not completely fill up the top of the first trench201.

The conductive layer220L may contain a metallic material or a metallic compound. For example, the conductive pattern220may contain tungsten (W). However, the present inventive concept is not limited thereto, and for example, the conductive pattern may contain at least one of polysilicon, a metal silicide compound, a conductive metal nitride and metal.

Next, as shown inFIG. 19, a conductive pattern220is formed by partially etching the conductive layer220L through the etching process. The conductive pattern220may be located only in the lower part of the first trench201. In the etching process, both the anisotropic etching and the isotropic etching may be used, and both the dry etching and the wet etching may be used.

Thus, the top surface of the conductive pattern220is formed to be higher than the top surface of the substrate100and may be formed to be lower than the top surfaces of the channel structures120and130.

Next, as shown inFIG. 20, the insulating layer230that fills up the first trench201is formed. The insulating layer230may be formed on the conductive pattern220within the first trench201. The insulating layer230is in contact with the top surface of the conductive pattern220and may be formed along the side surfaces of the electrode structure110. Next, a planarization process (e.g., a CMP process) is performed so that the top surface of the insulating layer230and the top surface of the electrode structure110are parallel to each other. Thus, the top surface of the insulating layer230may be located on the same plane as the top surface of the channel pad135or the top surface of the electrode structure110. The insulating layer230may be made of a material having a dielectric constant. In some embodiments of the present inventive concept, the insulating layer230, for example, may be made of a material, such as HfO2, Al2O3, ZrO2 and TaO2, but the present inventive concept is not limited thereto.

Next, a first interlayer insulating film170that covers the channel structures120and130, the channel pad135, the electrode structure110and the insulating layer230is formed. The first interlayer insulating film170may take charge of the electrical insulation between the semiconductor elements located below the first interlayer insulating film170and the semiconductor elements located above the first interlayer insulating film170.

Next, as shown inFIG. 21, a second trench203that partially exposes of the top surface of the conductive pattern220is formed through the first interlayer insulating film170and the insulating layer230.

Next, as shown inFIG. 22, the first barrier metal layer310L conformally formed along the inner surface of the second trench is formed. The first barrier metal layer310L may contain titanium (Ti), titanium nitride (TiN) or tungsten nitride (WN). The first barrier metal layer310L may be formed using PVD, CVD or ILD methods. However, the present inventive concept is not limited thereto.

Next, the metal contact layer315L is formed on the first barrier metal layer310L. The metal contact layer315L may be formed to embed the second trench203. The metal contact layer315L may be electrically connected to the conductive pattern220. The metal contact layer315L may contain a metallic material or a metallic compound. For example, the metal contact layer315L may contain tungsten (W). However, the present inventive concept is not limited thereto, and for example, may contain at least one of polysilicon, a metal silicide compound, a conductive metal nitride and metals.

Next, as shown inFIG. 23, a planarization process (e.g., a CMP process) is performed so that the top surface of the first interlayer insulating film170and the top surface of the metal contact315are parallel to each other. Thus, the top surface of the metal contact315layer and the top surface of the first interlayer insulating film170are located on the same plane.

Next, a second interlayer insulating film180that covers the first interlayer insulating film170is formed. The second interlayer insulating film180may take charge of the electrical insulation between the semiconductor elements located below the second interlayer insulating film180and the semiconductor elements located above the second interlayer insulating film180. The second interlayer insulating film180may contain the same material as the first interlayer insulating film170, but the present inventive concept is not limited thereto.

Next, as shown inFIG. 24, a third trench205that partially exposes the metal contact315is formed.

Next, as shown inFIG. 25, a second barrier metal layer320L conformally formed along the inner surface of the third trench is formed. The second barrier metal layer320L may contain titanium (Ti), titanium nitride (TiN) or tungsten nitride (WN). The second barrier metal layer320L may be formed using PVD, CVD or ILD methods. However, the present inventive concept is not limited thereto.

Next, the first conductive stud layer325L is formed on the second barrier metal layer320L. The first conductive stud layer325L may be formed to embed the third trench205. The first conductive stud layer325L may be electrically connected to the conductive pattern220. The first conductive stud layer325L may contain a metallic material or a metallic compound. For example, the first conductive stud layer325L may contain tungsten (W). However, the present inventive concept is not limited thereto, and for example, the first conductive stud layer may contain at least one of polysilicon, a metal silicide compound, a conductive metal nitride and metals.

Next, as shown inFIG. 3, a planarization process (e.g., a CMP process) is performed so that the top surface of the second interlayer insulating film180and the top surface of the first conductive stud325are parallel to each other. Thus, the top surface of the first conductive stud325and the top surface of the second interlayer insulating film180are also located on the same plane.

Consequently, the height of the conductive pattern220is formed to be lower than the top surfaces of the channel structures120and130, and the metal contact315may be disposed between the first conductive stud325and the conductive pattern220. Thus, the non-volatile memory device according to some embodiments of the present inventive concept may remove the slit area in the conductive pattern formed by the F-gas to reduce the stress applied by the conductive pattern. Moreover, it is possible to have an effect of reducing the failure rate of the non-volatile memory device and improving performance.

While the present inventive concept has been particularly illustrated and described with reference to exemplary implementations thereof, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims. The exemplary implementations should be considered in a descriptive sense only and not for purposes of limitation.