Semiconductor device having a porous nickel plating part

A semiconductor device which can reduce a heat stress to a solder layer while suppressing an increase of thermal resistance is provided. A semiconductor device includes a semiconductor element, a solder layer which is arranged on at least one surface of the semiconductor element and a lead frame which is arranged on the solder layer so that a porous nickel plating part is sandwiched between the lead frame and the solder layer. Compared with a case that the semiconductor element and the lead frame are jointed by a solder directly, an increased part of a thermal resistance of the solder junction is held down only to a part of the porous nickel plating part and a thermal resistance applied to the solder layer can be reduced.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a U.S. National Phase Application of PCT International Patent Application No. PCT/JP2012/006277, filed Oct. 1, 2012, claiming the benefit of priority of Japanese Patent Application No. 2011-241873, filed Nov. 4, 2011 and Japanese Patent Application No. 2012-002067, filed Jan. 10, 2012, all of which are incorporated by reference herein in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.

2. Related Art of the Invention

A semiconductor device in which a power semiconductor element is jointed to a lead frame on an insulator directly is known.

FIG. 11(A)shows a schematic sectional view showing a structure of a junction part between a power semiconductor element and a lead frame in such a conventional power semiconductor device.

A surface of one side of the lead frame304is fixed on an insulator305an undersurface of which is arranged with contact on a heat radiation plate306. Another surface of the lead frame304is jointed to a power semiconductor element301through a solder layer302.

Thus, the solder302has been conventionally used for junction of the power semiconductor element301and the lead frame304. However, since a coefficient of linear expansion of the lead frame304and a coefficient of linear expansion of the power semiconductor element301are greatly different, large heat stress is repeatedly impressed to the solder layer302of the solder junction by a power cycle at the time of making the power semiconductor device drive, finally, a solder crack occurs and there is a problem of becoming poor junction.

On the other hand, in order to reduce a heat stress and a heat warp which occur by the difference of the coefficients of linear expansion between the members, a structure where a heat-conducting porous metal plate is arranged between the members with a large difference of the coefficients of linear expansion, and the heat-conducting porous metal plate and each of the members are jointed by the solder, is proposed (see for example Japanese Laid Open Patent Publication No. 2002-237556).

The inventor of the invention considers that the structure proposed in Japanese Laid Open Patent Publication No. 2002-237556 is applied to the solder junction of the conventional power semiconductor device of the structure shown inFIG. 11(A)in order to reduce the heat stress applied to the solder layer302.

FIG. 11(B)shows a schematic sectional view showing a junction part between the power semiconductor element and the lead frame when the heat-conducting porous metal plate is arranged on the conventional power semiconductor device shown inFIG. 11(A).

The power semiconductor element301and the lead frame304which have a large difference of the coefficients of linear expansion are jointed to a heat-conducting porous metal plate303which is held between two solder layers302aand302b.

The porous metal plate303comprises a heat-conducting metal such as copper or aluminum with a large thermal conductivity and a large coefficient of linear expansion.

The porous metal plate303reduces the heat stresses which are applied to the solder layers302aand302bas a stress buffering plate, and an occurrence of the solder crack can be suppressed.

DISCLOSURE OF THE INVENTION

Problems to be Solved by the Invention

However, when the heat-conducting porous metal plate is arranged between the power semiconductor element and the lead frame which have the large difference of the coefficients of linear expansion, a thermal resistance of the junction between the power semiconductor element and the lead frame increases greatly although the heat stress can be reduced.

That is, with the composition which arranges the porous metal plate303shown inFIG. 11(B)compared with the conventional composition as shown inFIG. 11(A)in which the power semiconductor element301and the lead frame304are simply jointed by the solder layer302of one layer, since it becomes a structure in which the porous metal plate303and the solder layer302bare added, the thermal resistance of the junction increases greatly.

In view of the above-mentioned problem, an aspect of the present invention is to provide a semiconductor device and a method of manufacturing the semiconductor device, which can reduce a heat stress to the solder layers and can suppress an occurrence of a solder crack, with suppressing an increase of thermal resistance of a junction.

SUMMARY OF THE INVENTION

In order to solve the problems described above, the 1staspect of the present invention is

a semiconductor device comprising:

a semiconductor element;

a solder layer which is arranged on at least one surface of the semiconductor element; and

a lead frame which is arranged on the solder layer so that a porous nickel plating part is sandwiched between the lead frame and the solder layer.

Moreover, the 2ndaspect of the present invention is

the semiconductor device according to the 1staspect of the present invention, wherein

a thickness of the porous nickel plating part is 10 μm or more and 100 μm or less and a porosity of the porous nickel plating part is 20% or more and 60% or less.

Moreover, the 3rdaspect of the present invention is

the semiconductor device according to the 1staspect of the present invention, wherein

the porous nickel plating part is applied to the lead frame.

Moreover, the 4thaspect of the present invention is

the semiconductor device according to the 1staspect of the present invention, wherein

a coefficient of linear expansion of the porous nickel plating part is larger than a coefficient of linear expansion of the semiconductor element, and smaller than a coefficient of linear expansion of the lead frame.

Moreover, the 5thaspect of the present invention is

the semiconductor device according to the 1staspect of the present invention, comprising:

another solder layer which is arranged on such opposite surface of the semiconductor element, the opposite surface being opposite to the one surface of the semiconductor element on which the solder layer is arranged; and

another lead frame which is arranged on the another solder layer so that another porous nickel plating part is sandwiched between the another lead frame and the another solder layer.

Moreover, the 6thaspect of the present invention is

the semiconductor device according to the 1staspect of the present invention, wherein

the porous nickel plating part has many pores, and

particles having a thermal conductivity which is higher than that of nickel, are embedded in the pores which are located at a junction part of the porous nickel plating part to the solder layer.

Moreover, the 7thaspect of the present invention is

the semiconductor device according to the 6thaspect of the present invention, wherein

a coefficient of linear expansion of the porous nickel plating part in which the particles are embedded, is larger than a coefficient of linear expansion of the semiconductor element, and smaller than a coefficient of linear expansion of the lead frame.

Moreover, the 8thaspect of the present invention is

the semiconductor device according to the 6thaspect of the present invention, wherein

the particles embedded in the pores are particles of a carbon material.

Moreover, the 9thaspect of the present invention is

the semiconductor device according to the 6thaspect of the present invention, wherein

a thickness of the porous nickel plating part is 10 μm or more and 200 μm or less and a porosity of the porous nickel plating part is 20% or more and 60% or less.

Moreover, the 10thaspect of the present invention is

the semiconductor device according to the 6thaspect of the present invention, wherein

a diameter of the particle embedded in the pore is 4 nm or more and 50 nm or less.

Moreover, the 11thaspect of the present invention is

the semiconductor device according to the 6thaspect of the present invention, further comprising:

another solder layer which is arranged on such opposite surface of the semiconductor element, the opposite surface being opposite to the one surface of the semiconductor element on which the solder layer is arranged; and

another lead frame which is arranged on the another solder layer so that another porous nickel plating part having many pores is sandwiched between the another lead frame and the another solder layer, wherein

particles having a thermal conductivity which is higher than that of nickel, are embedded in the pores which are located at a junction part of the another porous nickel plating part to the another solder layer.

Moreover, the 12thaspect of the present invention is

a method of manufacturing a semiconductor device comprising:

a porous nickel plating step of applying a porous nickel plating to a lead frame; and

a solder junction step of joining a side of the lead frame to which the porous nickel plating is applied, to a semiconductor element, by using a solder.

Moreover, the 13thaspect of the present invention is

the method of manufacturing the semiconductor device according to the 12thaspect of the present invention, further comprising:

a particle embedding step of embedding particles having a thermal conductivity which is higher than that of nickel, into pores which are located at a part of the porous nickel plating that is applied to the lead frame in the porous nickel plating step.

Moreover, the 14thaspect of the present invention is

the method of manufacturing the semiconductor device according to the 12thaspect of the present invention, wherein

in the porous nickel plating step, the porous nickel plating is selectively applied to a surface of a side to be joined to the semiconductor element, of the lead frame.

Moreover, the 15thaspect of the present invention is

a semiconductor device which is manufactured by the method of manufacturing the semiconductor device according to the 12thaspect of the present invention, wherein

a coefficient of linear expansion of the porous nickel plating part is larger than a coefficient of linear expansion of the semiconductor element, and smaller than a coefficient of linear expansion of the lead frame.

Moreover, the 16thaspect of the present invention is

a semiconductor device which is manufactured by the method of manufacturing the semiconductor device according to the 13thaspect of the present invention, wherein

a coefficient of linear expansion of the porous nickel plating part in which the particles are embedded, is larger than a coefficient of linear expansion of the semiconductor element, and smaller than a coefficient of linear expansion of the lead frame.

Moreover, the 17thaspect of the present invention is the semiconductor device according to the 2ndaspect of the present invention wherein the porous nickel plating part is applied to the lead frame.

Moreover, the 18thaspect of the present invention is the semiconductor device according to the 7thaspect of the present invention, wherein the particles embedded in the pores are particles of a carbon material.

Moreover, the 19thaspect of the present invention is the method of manufacturing the semiconductor device according to the 13thaspect of the present invention wherein in the porous nickel plating step, the porous nickel plating is selectively applied to a surface of a side to be joined to the semiconductor element, of the lead frame.

By applying the porous nickel plating, a layer with a low coefficient of linear expansion and a low modulus of elasticity lies between the semiconductor element and the lead frame. Thereby, even when the semiconductor element heats, the lead frame expands greatly and a distortion occurs in the plating layer, the heat stress induced on the solder layer is eased since the modulus of elasticity of the plating layer is low.

A heat warp is induced on the solder layer by the difference of the coefficients of linear expansion of the plating layer and the semiconductor element, but the difference is small, and the heat stress to the solder layer becomes small.

In the semiconductor device in the present invention, the heat stress to the junction can be reduced by only applying the porous nickel plating to the lead frame and only jointing it to the semiconductor element by solder, that is, only one solder layer is required for junction. Thereby, compared with a simple solder junction, an increased part of the thermal resistance of the present invention is held down only to that of the part of the porous nickel plating layer.

Advantageous Effects of Invention

The present invention can provide a semiconductor device and a method of manufacturing the semiconductor device which can reduce a heat stress to the solder layers and can suppress an occurrence of a solder crack, with suppressing an increase of thermal resistance of a junction.

PREFERRED EMBODIMENTS OF THE INVENTION

First Embodiment

FIG. 1is a schematic sectional view showing an arrangement of a power semiconductor device according to a first embodiment of the present invention.

A surface of one side of a lead frame2is fixed on an insulator3an undersurface of which is arranged with contact on a heat radiation plate8. Another surface of the lead frame2, to which a porous nickel plating1is applied, is jointed to a power semiconductor element5through a solder layer4.

The power semiconductor element5corresponds to an example of a semiconductor element according to the present invention.

For example, the arrangement of the power semiconductor device is manufactured by steps ofFIG. 2(A)toFIG. 2(C).

FIG. 2(A)toFIG. 2(C)are process drawings of examples of a manufacturing process of the power semiconductor device of the first embodiment.FIG. 2(A)shows a plating step,FIG. 2(B)shows a lead frame fixing step andFIG. 2(C)shows a solder junction step.

First, as shown inFIG. 2(A), the porous nickel plating1is applied on the lead frame2.

For example, the porous nickel plating1is obtained by soaking the lead frame2in a nickel plating tank6in which the foaming agent is put, and applying electroplating to it. InFIG. 2(A), a mask13is attached to the lead frame2, and the porous plating1is applied selectively to only the side surface which is jointed to the power semiconductor element5by solder. At this time, a thickness and a porosity of the porous nickel plating1are controllable by adjusting an electric current density passed to the lead frame2, and a plating time.

FIG. 3shows a schematic sectional view of the porous nickel plating1which is applied on the surface of the lead frame2.

The porous nickel plating1which is applied on the lead frame2corresponds to an example of a porous nickel plating part according to the present invention.

A pore7of the porous nickel plating is 10 μm or more and 15 μm or less in height and needlelike. As the porosity becomes large, a diameter of the pore7becomes larger.

The porous nickel plating1is not limited to be applied selectively to only the part which is jointed to the power semiconductor element5by solder as shown inFIG. 2(A)but can be applied on the whole surface of the lead frame2. However, it is more desirable to apply the porous nickel plating1only to the part which is jointed by the solder selectively, in order to suppress the increase in thermal resistance of the part which is not jointed to the power semiconductor element5.

When a coefficient of linear expansion of the porous nickel plating1is smaller than a coefficient of linear expansion of the lead frame2, and larger than a coefficient of linear expansion of the semiconductor element5, the heat stress applied to the solder layer4can be reduced effectively. It is thought that the coefficient of linear expansion of the porous nickel plating1is equivalent to the value obtained by multiplying a coefficient (12.8 ppm) of linear expansion of nickel by (100−porosity) %. Since the coefficient of linear expansion of the power semiconductor element5is about 4 ppm or more and 5 ppm or less, the porosity of the porous nickel plating1needs to be 60% or less.

When the porosity of the porous nickel plating1is smaller than 20%, a deviation occurs in the number of pores per unit volume, and the porous nickel plating layer of uniform porosity cannot be obtained.

As mentioned above, it is desirable that the porosity of the porous nickel plating1is 20% or more and 60% or less.

Further, the pore7of the porous nickel plating1is 10 μm or more and 15 μm or less in height and needlelike. Therefore when the thickness of the porous nickel plating1is smaller than 10 μm, plating thickness varies and a uniform porous nickel plating layer cannot be obtained. And, in the first embodiment, when the thickness is larger than 100 μm, the thermal resistance of the porous nickel plating layer increases, and a productivity worsens because the plating time becomes long.

Thereby, in the first embodiment, it is desirable that the thickness of the porous nickel plating1is 10 μm or more and 100 μm or less. When the porous nickel plating1has a certain amount of thickness, a distortion induced on the solder layer4decreases and the heat stress is eased. It is more desirable that the thickness of the porous nickel plating1is 20 μm or more and 100 μm or less, so that the stress reduction to the solder layer4is more effective.

Though copper or aluminum is desirable as a material of the lead frame2, the copper which has large electric conductivity and large thermal conductivity is more desirable.

The porous nickel plating1is applied to the lead frame2directly in the above, but the porous nickel plating1can be applied to the lead frame2to which another surface treatment has been applied in advance.

Next, as shown inFIG. 2(B), the lead frame2to which the porous nickel plating1has been applied is fixed on an insulating resin9. Here, the insulating resin9is used as the insulator3.

The lead frame2to which the porous nickel plating1has been applied is placed on the insulating resin9expanded on the heat radiation plate8so that the lead frame2does not come into contact with the heat radiation plate8and one surface of the lead frame2is exposed on the insulating resin9, and the lead frame2is fixed on the insulating resin9by curing the insulating resin9.

Next, as shown inFIG. 2(C), a cream solder10is screen-printed to the exposed surface of the lead frame2, the power semiconductor element5is placed on that, and the arrangement of the present invention is constructed. A suitable cream solder is selected as the cream solder10, according to the environment in which the semiconductor device having the arrangement of the present invention is used.

When the cream solder10is printed to the power semiconductor element5, in order to suppress the increase in the thermal resistance, the cream solder10is supplied so that a thickness of the cream solder10becomes 50 μm or more and 100 μm or less.

Next, when this structure is passed through a reflowing furnace (not shown), the wiring structure as shown inFIG. 1between the lead frame2and the power semiconductor element5can be obtained.

By the construction of the power semiconductor device of the first embodiment, a layer with a low coefficient of linear expansion and a low modulus of elasticity lies between the power semiconductor element5and the lead frame2. Therefore, even when the power semiconductor element5heats, the lead frame2expands greatly and a distortion occurs in the porous nickel plating1, the heat stress induced on the solder layer4is eased since the modulus of elasticity of the porous nickel plating1is low.

A heat warp is induced on the solder layer4by the difference of the coefficients of linear expansion of the porous nickel plating1and the power semiconductor element5, but the difference is small, and the heat stress to the solder layer4is reduced compared with the case where the porous nickel plating1does not intervene.

Since the heat stress to the junction can be reduced by only jointing the lead frame2, to which the porous nickel plating1is applied, to the power semiconductor element5by solder, the solder layer4required for junction can be only one layer. Thereby, compared with a simple solder junction, an increased part of the thermal resistance of the solder junction of the first embodiment can be held down only to that of the part of the porous nickel plating1.

FIG. 4shows a schematic sectional view showing an arrangement of a power semiconductor device of another composition according to the first embodiment. InFIG. 4, the components that are the same as those inFIG. 1are denoted by the same reference numerals.

In the power semiconductor device shown inFIG. 4, lead frames are jointed to both sides of the power semiconductor element5by solder, respectively. One surface of the power semiconductor element5is jointed to a lead frame2, to which a porous nickel plating1is applied, through a solder layer4. The opposite surface of the power semiconductor element5is jointed to a second lead frame11, to which a second porous nickel plating12is applied, through a second solder layer14.

One end of the second lead frame11, to which the second porous nickel plating12is applied, is jointed to the power semiconductor element5by solder, and another end of the second lead frame11is connected to a second power semiconductor element or a third lead frame (not shown).

Even in the arrangement in which two or more lead frames2and11are jointed to the power semiconductor element5by solder as shown inFIG. 4, the same effect as an effect of reducing heat stress of the arrangement shown inFIG. 1can be obtained at the solder layer4and the second solder layer14.

The second solder layer14inFIG. 4corresponds to an example of another solder layer according to the present invention. The second porous nickel plating12corresponds to an example of another porous nickel plating part according to the present invention. The second lead frame11corresponds to an example of another lead frame according to the present invention.

As mentioned above, by using the arrangement of the power semiconductor device of the first embodiment, a heat stress to the solder layer4can be reduced and an occurrence of the solder crack can be suppressed, with suppressing an increase of thermal resistance of the junction.

In the above, the power semiconductor device having the power semiconductor element is described as an example, but the composition of the first embodiment can be applied in a semiconductor device in which a semiconductor element other than a power semiconductor element is jointed to a lead frame directly, and the same effect can be obtained.

Next, the effect of the present invention is described by comparing examples of the first embodiment with comparative examples.

The examples of the first embodiment are described below by using a simulation, but the present invention is not limited to the examples.

When the simulation is performed, the same values common to the examples 1 to 7, comparative example 1 and the comparative example 2 are used for all of a size, material physical property value and the like of a constructional element other than a porous nickel plating layer.

FIG. 5shows a schematic sectional view showing an arrangement of power semiconductor devices in the examples 1 to 7 of the first embodiment and the compatible examples 1 and 2.

In the examples 1 to 6 and the compatible examples 1 and 2, when the plating is applied to the lead frame2, the plating is applied to only one surface which is on a side to be jointed to the power semiconductor element5by using the mask13shown inFIG. 2(A). In the example 7, the plating is applied to the whole surface of the lead frame2by not using the mask13.

In the power semiconductor device in the example 1, as shown inFIG. 5, the power semiconductor element5having a length of 4 mm, a width of 6 mm and a thickness of 0.4 mm (a modulus of elasticity of 450 GPa and a coefficient of linear expansion of 4.2 ppm), and the lead frame2having a length of 10 mm, a width of 10 mm and a thickness of 1.5 mm (Cu, a modulus of elasticity of 120 GPa and a coefficient of linear expansion of 16.6 ppm) to which the porous nickel plating1having a thickness of 10 μm and a porosity of 20% (a modulus of elasticity of 168 GPa, a coefficient of linear expansion of 10.2 ppm and a thermal conductivity of 72.8 W/(m·K)) has been applied are jointed by the solder layer4having a length of 4 mm, a width of 6 mm and a thickness of 100 μm (Sn—Ag—Cu, a modulus of elasticity of 41.6 GPa, a coefficient of linear expansion of 21.7 ppm and a thermal conductivity of 55 W/(m·K)).

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C.

The modulus of elasticity, the coefficient of linear expansion, and the thermal conductivity of the porous nickel plating1are calculated by multiplying the modulus of elasticity (210 GPa), the coefficient of linear expansion (12.8 ppm), and the thermal conductivity (91 W/(m·K)) of nickel, respectively, by (100−porosity) %. The moduli of elasticity and the coefficients of linear expansion of the porous nickel plating in the examples 2 to 7 are defined similarly.

The total of the thermal resistance of the porous nickel plating1and the thermal resistance of the solder layer4is calculated as a value of a thermal resistance of the junction. The values of the thermal resistance of the junction in the examples 2 to 6 are calculated similarly.

In the power semiconductor device in the example 2, the thickness and the porosity of the porous nickel plating1are 10 μm and 60% (a modulus of elasticity of 84 GPa, a coefficient of linear expansion of 5.1 ppm and a thermal conductivity of 36.4 W/(m·K)), respectively, in the composition of the example 1.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C. The other compositions are the same as those of the example 1.

In the power semiconductor device in the example 3, the thickness and the porosity of the porous nickel plating1are 20 μm and 20% (a modulus of elasticity of 168 GPa, a coefficient of linear expansion of 10.2 ppm and a thermal conductivity of 72.8 W/(m·K)), respectively, in the composition of the example 1.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C. The other compositions are the same as those of the example 1.

In the power semiconductor device in the example 4, the thickness and the porosity of the porous nickel plating1are 20 μm and 60% (a modulus of elasticity of 84 GPa, a coefficient of linear expansion of 5.1 ppm and a thermal conductivity of 36.4 W/(m·K)), respectively, in the composition of the example 1.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C. The other compositions are the same as those of the example 1.

In the power semiconductor device in the example 5, the thickness and the porosity of the porous nickel plating1are 100 μm and 20% (a modulus of elasticity of 168 GPa, a coefficient of linear expansion of 10.2 ppm and a thermal conductivity of 72.8 W/(m·K)), respectively, in the composition of the example 1.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C. The other compositions are the same as those of the example 1.

In the power semiconductor device in the example 6, the thickness and the porosity of the porous nickel plating1are 100 μm and 60% (a modulus of elasticity of 84 GPa, a coefficient of linear expansion of 5.1 ppm and a thermal conductivity of 36.4 W/(m·K)), respectively, in the composition of the example 1.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C. The other compositions are the same as those of the example 1.

In the power semiconductor device in the example 7, the porous nickel plating1having a thickness of 10 μm and a porosity of 20% is applied to not only the side surface which is jointed to the power semiconductor element5but also the whole surface of the lead frame2, in the composition of the example 1. Therefore, inFIG. 5, the porous nickel plating1has been applied to not only the upper surface but also the undersurface of the lead frame2.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C. The other compositions are the same as those of the example 1.

Since the undersurface of the lead frame2is not fixed, the thermal resistance is the same value as that of the example 1 in which the porous nickel plating1is applied to only the upper surface.

About thermal resistance, a value of a thermal resistance (the total value of the thermal resistance of the porous nickel plating1and the thermal resistance of the solder layer4) on the side of the upper surface of the lead frame2and a value of a thermal resistance (the thermal resistance of the porous nickel plating1on the side of the undersurface) on the side of the undersurface are calculated individually, and the value of the thermal resistance on the side of the upper surface is calculated as a value of a thermal resistance of the junction.

Comparative Example 1

In the power semiconductor device in the comparative example 1, the power semiconductor element5and the lead frame2are jointed by solder by applying a nickel plating of 4 μm instead of the porous nickel plating to the lead frame2, in the composition of the example 1.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C. The other compositions are the same as those of the example 1.

The thermal resistance of the solder layer4is calculated as a value of a thermal resistance of the junction.

Comparative Example 2

In the power semiconductor device in the comparative example 2, the thickness and the porosity of the porous nickel plating1are 200 μm and 60% (a modulus of elasticity of 84 GPa, a coefficient of linear expansion of 5.1 ppm and a thermal conductivity of 36.4 W/(m·K)), respectively, in the composition of the example 1.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C. The other compositions are the same as those of the example 1.

The total of the thermal resistance of the porous nickel plating1and the thermal resistance of the solder layer4is calculated as a value of a thermal resistance of the junction.

TABLE 1 shows maximum heat stresses and values of the thermal resistance of the junction, which are applied to respective solder layers4in the examples 1 to 7 and the compatible examples 1 and 2.

As shown in TABLE 1, the heat stress applied to the solder layer4is reduced about 4% or more and 50% or less in the examples 1 to 7, compared with the comparative example 1. The value of the thermal resistance is held down so as to be 1.1 to 2.5 times as large as that of the comparative example 1.

An extent of a value of the thermal resistance suitable for a junction of a power semiconductor changes with the area size of the joint surface of the power semiconductor element5. As the value of the thermal resistance of the junction of the power semiconductor in the case of the power semiconductor element5(having a length of 4 mm and a width of 6 mm) and the lead frame2which are used in this simulation, 0.2K/W or less per joint surface is desirable, and 0.15K/W or less per joint surface is more desirable.

In the comparative example 2, although the thermal stress is 420 Mpa and small enough, the value of the thermal resistance is 0.306K/W and a large value, it is not suitable for the junction of the power semiconductor.

As shown in the example 7, the value of the thermal resistance in the joint surface of the power semiconductor element5is the same as that in the case where the porous nickel plating1is applied only to the upper surface of the lead frame2(the example 1). Therefore, when the porous nickel plating1of the same thickness in the examples 2 to 6 is applied on the whole surface of the lead frame2, the values of the thermal resistance to be obtained are the same values in the examples 2 to 6, respectively.

In the examples 1 and 2 in which the thickness of the porous nickel plating1is 10 μm, the reduction of the heat stress is 5% or less compared with the comparative example 1. On the other hand, in the examples 3 to 6 in which the thickness of the porous nickel plating1is 20 μm or more, the reduction of the heat stress is 10% or more compared with the comparative example 1, and more effective stress reduction has been confirmed.

Second Embodiment

FIG. 6(A)is a schematic sectional view showing an arrangement of a power semiconductor device according to a second embodiment of the present invention.

InFIGS. 6 to 10used with the second embodiment, the components that are the same as those inFIGS. 1 to 5used with the first embodiment are denoted by the same reference numerals.

A surface of one side of a lead frame2is fixed on an insulator3an undersurface of which is arranged with contact on a heat radiation plate8. Another surface of the lead frame2, to which a porous nickel plating20is applied, is jointed to a power semiconductor element5through a solder layer4.

FIG. 6(B)shows an expanded sectional view of a part of the porous nickel plating20which is surrounded by the circle-shaped dashed line inFIG. 6(A).

As shown inFIG. 6(B), nanoparticles17with high thermal conductivity are embedded into pores7which are located at a surface of junction side of the porous nickel plating20to the solder layer4.

In the second embodiment, the nanoparticles17are embedded into the pores7of the porous nickel plating20, and it differs in this respect from the first embodiment in which the nanoparticle17is not embedded into the pore7for the porous nickel plating1.

The nanoparticles17correspond to an example of particles having a thermal conductivity, which is higher than that of nickel, are embedded into the pores which are located at a junction part to the solder layer according to the present invention.

For example, the arrangement of the power semiconductor is manufactured by the processes ofFIGS. 7(A) to 7(D).

FIGS. 7(A) to 7(D)are process drawings of examples of a manufacturing process of the power semiconductor device of the second embodiment.FIG. 7(A)shows a plating step,FIG. 7(B)shows a particle embedding step in which the nanoparticles17are embedded into the pores7located in the surface of the porous nickel plating20,FIG. 7(C)shows a lead frame fixing step andFIG. 7(D)shows a solder junction step.

First, as shown inFIG. 7(A), the porous nickel plating20is applied on the lead frame2.

For example, the porous nickel plating20is obtained by soaking the lead frame2in a nickel plating tank6in which the foaming agent is put, and applying electroplating to it. InFIG. 7(A), a mask13is attached to the lead frame2, and the porous plating20is applied selectively to only the side surface which is jointed to the power semiconductor element5by solder. At this time, a thickness and a porosity of the porous nickel plating20are controllable by adjusting an electric current density passed to the lead frame2, and a plating time.

FIG. 8(A)shows a schematic sectional view of the porous nickel plating20which is applied on the surface of the lead frame2after the plating step inFIG. 7(A)is performed.

The pore7of the porous nickel plating is 10 μm or more and 15 μm or less in height and needlelike. As the porosity becomes large, a diameter of the pore7becomes larger.

The porous nickel plating20is not limited to be applied selectively to only the part which is jointed to the power semiconductor element5by solder as shown inFIG. 7(A)but can be applied on the whole of the surface of the lead frame2. However, it is more desirable to apply the porous nickel plating20only to the part which is jointed by the solder selectively, in order to suppress the increase in thermal resistance of the part which is not jointed to the power semiconductor element5.

When a coefficient of linear expansion of the porous nickel plating20is smaller than the coefficient of linear expansion of the lead frame2, and larger than the coefficient of linear expansion of the semiconductor element5, the heat stress applied to the solder layer4can be reduced effectively. It is thought that the coefficient of linear expansion of the porous nickel plating20is equivalent to the value obtained by multiplying a coefficient (12.8 ppm) of linear expansion of nickel by (100−porosity) %. Since the coefficient of linear expansion of the power semiconductor element5is about 4 ppm or more and 5 ppm or less, the porosity of the porous nickel plating20needs to be 60% or less.

When the porosity of the porous nickel plating20is smaller than 20%, a deviation occurs in the number of pores per unit volume, and the porous nickel plating layer of uniform porosity cannot be obtained.

As mentioned above, it is desirable that the porosity of the porous nickel plating20is 20% or more and 60% or less.

Further, the pore7of the porous nickel plating20is 10 μm or more and 15 μm or less in height and needlelike. Therefore when the thickness of the porous nickel plating20is smaller than 10 μm, plating thickness varies and a uniform porous nickel plating layer cannot be obtained. And, in the second embodiment, when the thickness is larger than 200 μm, the thermal resistance of the porous nickel plating layer increases, and a productivity worsens because the plating time becomes still longer.

Thereby, in the second embodiment, it is desirable that the thickness of the porous nickel plating20is 10 μm or more and 200 μm or less. When the porous nickel plating20has a certain amount of thickness, a distortion induced on the solder layer4decreases and a heat stress is eased. It is more desirable that the thickness of the porous nickel plating20is 20 μm or more and 200 μm or less, so that the stress reduction to the solder layer4is more effective.

Though copper or aluminum is desirable as a material of the lead frame2, the copper which has large electric conductivity and large thermal conductivity is more desirable.

The porous nickel plating20is applied to the lead frame2directly in the above, but the porous nickel plating20can be applied to the lead frame2to which another surface treatment has been applied in advance.

Next, as shown inFIG. 7(B), the nanoparticles17are embedded into the pores7located in the surface of the porous nickel plating20applied to the lead frame2.

As a method of embedding the nanoparticles17into the surface of the porous nickel plating20, for example, there is a method of soaking the lead frame2in an ultrasonic cleaning tank15in which the solution16, in which the nanoparticles17are distributed uniformly, is put, and applying an ultrasonic vibration. As the solution16in which the nanoparticles17are distributed uniformly, for example, aqueous solution of ethanol or the like with small surface tension can be used. The nanoparticles17can be led into the pores7of the surface of the porous nickel plating20with uniform density, by adjusting a concentration of the mixed solution16in which the nanoparticles17are dispersed and a time for applying the ultrasonic vibration.

In the lead frame2in which the nanoparticles17are inserted into the surface of the porous nickel plating20, for example, a solvent is evaporated by decompression or slight heating.

FIG. 8(B)shows a schematic sectional view of the porous nickel plating20which is applied on the surface of the lead frame2after the particle embedding step inFIG. 7(B)is performed.

The porous nickel plating20which is applied on the surface of the lead frame2corresponds to an example of a porous nickel plating part according to the present invention.

When the thermal conductivity of the nanoparticle17is not higher than the thermal conductivity (about 90.5 W/(m·K)) of nickel, it cannot reduce the thermal resistance of the junction effectively. Thereby, a material of the nanoparticle17is desirable such that a thermal conductivity is more than 91 W/(m·K). Although carbon materials (e.g. diamond, carbon nanotube and graphite) are desirable as the material of the nanoparticle17, diamond (about 2000 W/(m·K)) is more desirable among the carbon materials.

When the nanoparticles17of small size are embedded into the pore7of the surface of the porous nickel plating20, a contact area between particles, and a contact area between a particle and the porous nickel plating20become large, and the thermal resistance can be reduced more. Thereby, it is desirable that a size of the nanoparticle17is 50 nm or less. When the size is larger than 50 nm, the contact area with the porous nickel plating20becomes small, and it becomes impossible to conduct heat efficiently.

However, when the nanoparticle17is smaller than 4 nm, a control by ultrasonic vibration is difficult since the diffused nanoparticle is very light, and the nanoparticles17cannot go into the pores7of the porous nickel plating20easily. Therefore, it is desirable that the nanoparticle17is larger than 4 nm.

Since the nanoparticles17are contained in the pores7of the surface of the porous nickel plating20with fixed density in the state of particle, they do not influence the stress relaxation effect of the porous nickel plating20. Therefore, the modulus of elasticity and the coefficient of linear expansion of the porous nickel plating20in which the nanoparticles17are embedded into the pores7of the surface are equivalent to those of a porous nickel plating in which the nanoparticle17is not added, respectively.

Since the nanoparticles17with high thermal conductivity are compacted and contained with fixed density in the pores7of the surface of the porous nickel plating20, the heat from the porous nickel plating20can escape quickly with a sufficient contact area to the porous nickel plating20.

Next, as shown inFIG. 7(C), the porous nickel plating20is applied to the lead frame2, and the lead frame2in which the nanoparticles17are embedded into the surface of the porous nickel plating20is fixed on an insulating resin9. Here, the insulating resin9is used as the insulator3.

The lead frame2, to which the porous nickel plating20is applied in which the nanoparticles17are embedded into the surface, is placed on the insulating resin9expanded on the heat radiation plate8so that the lead frame2does not come into contact with the heat radiation plate8and one surface of the lead frame2is exposed on the insulating resin9, and the lead frame2is fixed on the insulating resin9by curing the insulating resin9.

Next, as shown inFIG. 7(D), a cream solder10is screen-printed to the exposed surface of the lead frame2, the power semiconductor element5is placed on that, and the arrangement of the present invention is constructed. A suitable cream solder is selected as the cream solder10, according to the environment in which the power semiconductor device having the arrangement of the present invention is used.

When the cream solder10is printed to the power semiconductor element5, the cream solder10is supplied so that a thickness of the cream solder10becomes 50 μm or more and 100 μm or less. When the thickness of the solder layer is 50 μm or less, the junction intensity between the power semiconductor element5and the porous nickel plating20declines. And when the thickness is 100 μm or more, the thermal resistance increases. Therefore, the cream solder10is supplied so that the thickness of the solder layer becomes 50 μm or more and 100 μm or less.

Next, when this structure is passed through a reflowing furnace (not shown), the wiring structure as shown inFIG. 6(A)between the lead frame2and the power semiconductor element5can be obtained.

By the construction of the power semiconductor device of the second embodiment, a layer with a low coefficient of linear expansion and a low modulus of elasticity lies between the power semiconductor element5and the lead frame2. Therefore, even when the power semiconductor element5heats, the lead frame2expands greatly and a distortion occurs in the porous nickel plating20in which the nanoparticles17are embedded, the heat stress induced on the solder layer4is eased since the modulus of elasticity is low.

A heat warp is induced on the solder layer4by the difference of the coefficients of linear expansion of the porous nickel plating20in which the nanoparticles17are embedded and the power semiconductor element5, but the difference is small, and the heat stress to the solder layer4is reduced compared with the case where the porous nickel plating20in which the nanoparticle17are embedded does not intervene.

Since the heat stress to the junction can be reduced by only jointing the lead frame2, to which the porous nickel plating20is applied in which the nanoparticles17are embedded into the pores7of the surface, to the power semiconductor element5by solder, the solder layer4required for junction can be only one layer. Thereby, compared with a simple solder junction, an increased part of the thermal resistance of the solder junction of the second embodiment can be held down only to that of the part of the porous nickel plating20. Furthermore, since the nanoparticles17with high thermal conductivity are embedded into the pores7of the surface of the porous nickel plating20, the increased part of the thermal resistance by the porous nickel plating20can be suppressed to be still smaller.

FIG. 9shows a schematic sectional view showing an arrangement of a power semiconductor device of another composition according to the second embodiment. InFIG. 9, the components that are the same as those inFIG. 6are denoted by the same reference numerals.

In the power semiconductor device shown inFIG. 9, lead frames are jointed to both sides of the power semiconductor element5by solder, respectively. One surface of the power semiconductor element5is jointed to a lead frame2, to which a porous nickel plating20is applied, through a solder layer4. The opposite surface of the power semiconductor element5is jointed to a second lead frame11, to which a second porous nickel plating21is applied, through a second solder layer14.

As shown inFIG. 6(B), the nanoparticles17are embedded into the pores7which are located at the surface of junction side of the porous nickel plating20to the solder layer4. Similarly, the nanoparticles17are embedded also into the pores which are located at the surface of junction side of the second porous nickel plating21to the second solder layer14.

One end of the second lead frame11, to which the second porous nickel plating21is applied in which the nanoparticles are embedded into the surface, is jointed to the power semiconductor element5by solder, and another end of the second lead frame11is connected to a second power semiconductor element or a third lead frame (not shown).

Even in the arrangement in which two or more lead frames2and11are jointed to the power semiconductor element5by solder as shown inFIG. 9, the same effect as an effect of reducing heat stress of the arrangement shown inFIG. 6(A)can be obtained at the solder layer4and the second solder layer14.

The second solder layer14inFIG. 9corresponds to an example of another solder layer according to the present invention. The second porous nickel plating in which the nanoparticles are embedded into the pores at the surface corresponds to an example of another porous nickel plating part having many pores according to the present invention. The second lead frame11corresponds to an example of another lead frame according to the present invention.

As mentioned above, by using the arrangement of the power semiconductor device of the second embodiment, a heat stress to the solder layer4can be reduced and an occurrence of the solder crack can be suppressed, with suppressing an increase of thermal resistance of the junction.

In the above, the power semiconductor device having the power semiconductor element is described as an example, but the composition of the second embodiment can be applied in a semiconductor device in which a semiconductor element other than a power semiconductor element is jointed to a lead frame directly, and the same effect can be obtained.

Next, the effect of the present invention is described by comparing examples of the second embodiment with comparative examples.

The examples of the second embodiment are described below by using a simulation, but the present invention is not limited to the examples.

When the simulation is performed, the same values common to the examples 8 to 13, comparative example 1 and the comparative example 3 are used for all of a size, material physical property value and the like of a constructional element other than a porous nickel plating layer.

FIG. 10shows a schematic sectional view showing an arrangement of power semiconductor devices in the examples 8 to 13 of the second embodiment and the compatible examples 1 and 3.

In the examples 8 to 13 and the compatible examples 1 and 3, when the plating is applied to the lead frame2, the plating is applied to only one surface which is on a side to be jointed to the power semiconductor element5by using the mask13shown inFIG. 7(A).

In the power semiconductor device in the example 8, as shown inFIG. 10, the power semiconductor element5having a length of 4 mm, a width of 6 mm and a thickness of 0.4 mm (a modulus of elasticity of 450 GPa and a coefficient of linear expansion of 4.2 ppm), and the lead frame2having a length of 10 mm, a width of 10 mm and a thickness of 1.5 mm (Cu, a modulus of elasticity of 120 GPa and a coefficient of linear expansion of 16.6 ppm) to which the porous nickel plating20having a thickness of 20 μm and a porosity of 20% (a modulus of elasticity of 168 GPa, a coefficient of linear expansion of 10.2 ppm and a thermal conductivity of 172.8 W/(m·K)) has been applied are jointed by the solder layer4having a length of 4 mm, a width of 6 mm and a thickness of 100 μm (Sn—Ag—Cu a modulus of elasticity of 41.6 GPa, a coefficient of linear expansion of 21.7 ppm and a thermal conductivity of 55 W/(m·K)). The nanoparticles17(nanodiamonds having a thermal conductivity of 2000 W/(m·K)) are embedded into the pores7of the surface of the porous nickel plating20, and a thickness of the porous nickel plating20is 5 μm.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C.

The modulus of elasticity, and the coefficient of linear expansion of the porous nickel plating20in which the nanoparticles17are embedded into the surface are calculated by multiplying the modulus of elasticity (210 GPa), and the coefficient of linear expansion (12.8 ppm) of nickel, respectively, by (100−porosity) %. The moduli of elasticity and the coefficients of linear expansion of the porous nickel plating in the examples 9 to 13 are defined similarly.

The thermal conductivity of the porous nickel plating20in which the nanoparticles17are embedded into the pores7of the surface is calculated by adding the value calculated by multiplying the thermal conductivity (91 W/(m·K)) of nickel by (100−porosity) % and the value calculated by multiplying the thermal conductivity (2000 W/(m·K)) of the nanodiamonds by ((thickness of nanoparticle/thickness of porous nickel plating)×porosity) %. The thermal conductivity of the porous nickel plating in the examples 9 to 13 are defined similarly.

The total of the thermal resistance of the porous nickel plating20, in which the nanodiamonds are embedded into the pores of the surface, and the thermal resistance of the solder layer4is calculated as a value of a thermal resistance of the junction. The values of the thermal resistance of the junction in the examples 9 to 13 are calculated similarly.

In the power semiconductor device in the example 9, the thickness and the porosity of the porous nickel plating20are 20 μm and 60% (a modulus of elasticity of 84 GPa, a coefficient of linear expansion of 5.1 ppm and a thermal conductivity of 336.4 W/(m·K)), respectively, in the composition of the example 8. The nanoparticles17(nanodiamonds having a thermal conductivity of 2000 W/(m·K)) are embedded into the pores7of the surface of the porous nickel plating20, and a thickness of the porous nickel plating20is 5 μm.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C. The other compositions are the same as those of the example 8.

In the power semiconductor device in the example 10, the thickness and the porosity of the porous nickel plating20are 100 μm and 20% (a modulus of elasticity of 168 GPa, a coefficient of linear expansion of 10.2 ppm and a thermal conductivity of 92.8 W/(m·K)), respectively, in the composition of the example 8. The nanoparticles17(nanodiamonds having a thermal conductivity of 2000 W/(m·K)) are embedded into the pores7of the surface of the porous nickel plating20, and a thickness of the porous nickel plating20is 5 μm.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C. The other compositions are the same as those of the example 8.

In the power semiconductor device in the example 11, the thickness and the porosity of the porous nickel plating20are 100 μm and 60% (a modulus of elasticity of 84 GPa, a coefficient of linear expansion of 5.1 ppm and a thermal conductivity of 96.4 W/(m·K)), respectively, in the composition of the example 8. The nanoparticles17(nanodiamonds having a thermal conductivity of 2000 W/(m·K)) are embedded into the pores7of the surface of the porous nickel plating20, and a thickness of the porous nickel plating20is 5 μm.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C. The other compositions are the same as those of the example 8.

In the power semiconductor device in the example 12, the thickness and the porosity of the porous nickel plating20are 200 μm and 20% (a modulus of elasticity of 168 GPa, a coefficient of linear expansion of 10.2 ppm and a thermal conductivity of 82.8 W/(m·K)), respectively, in the composition of the example 8. The nanoparticles17(nanodiamonds having a thermal conductivity of 2000 W/(m·K)) are embedded into the pores7of the surface of the porous nickel plating20, and a thickness of the porous nickel plating20is 5 μm.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C. The other compositions are the same as those of the example 8.

In the power semiconductor device in the example 13, the thickness and the porosity of the porous nickel plating20are 200 μm and 60% (a modulus of elasticity of 84 GPa, a coefficient of linear expansion of 5.1 ppm and a thermal conductivity of 66.4 W/(m·K)), respectively, in the composition of the example 8. The nanoparticles17(nanodiamonds having a thermal conductivity of 2000 W/(m·K)) are embedded into the pores7of the surface of the porous nickel plating20, and a thickness of the porous nickel plating20is 5 μm.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C. The other compositions are the same as those of the example 8.

Comparative Example 1

In the power semiconductor device in the comparative example 1, the power semiconductor element5and the lead frame2are jointed by solder by applying a nickel plating of 4 μm instead of the porous nickel plating20, in which the nanodiamonds are embedded into the pores of the surface, to the lead frame2, in the composition of the example 8. The composition of this comparative example 1 is the same composition of the comparative example 1 used as a comparative example in the first embodiment.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C. The other compositions are the same as those of the example 8.

The thermal resistance of the solder layer4is calculated as a value of a thermal resistance of the junction.

Comparative Example 3

In the power semiconductor device in the comparative example 3, the thickness and the porosity of the porous nickel plating20are 300 μm and 60% (a modulus of elasticity of 84 GPa, a coefficient of linear expansion of 5.1 ppm and a thermal conductivity of 56.4 W/(m·K)), respectively, in the composition of the example 8. The nanoparticles17(nanodiamonds having a thermal conductivity of 2000 W/(m·K)) are embedded into the pores7of the surface of the porous nickel plating20, and a thickness of the porous nickel plating20is 5 μm.

In the wiring structure between the power semiconductor element5of the power semiconductor device and the lead frame2, the heat stress applied to the solder layer4is calculated by using the linear structural analysis (FEM) when a temperature of constructional elements is changed from 200° C. to −40° C. The other compositions are the same as those of the example 8.

The total of the thermal resistance of the porous nickel plating20, in which the nanodiamonds are embedded into the pores of the surface, and the thermal resistance of the solder layer4is calculated as a value of a thermal resistance of the junction.

TABLE 2 shows maximum heat stresses and values of the thermal resistance of the junction, which are applied to respective solder layers4in the examples 8 to 13 and the compatible examples 1 and 3.

For reference, the values of the thermal resistance of the porous nickel plating20in which the nanodiamonds are not embedded are also indicated in TABLE 2 for the examples 8 to 11 and 13.

As shown in TABLE 2, the heat stress applied to the solder layer4is reduced about 9% or more and 60% or less in the examples 8 to 13, compared with the comparative example 1. The value of the thermal resistance is held down so as to be 1.0 to 2.6 times as large as that of the comparative example 1.

An extent of a value of the thermal resistance suitable for a junction of a power semiconductor changes with the area size of the joint surface of the power semiconductor element5. As the value of the thermal resistance of the junction of the power semiconductor in the case of the power semiconductor element5(having a length of 4 mm and a width of 6 mm) and the lead frame2which are used in this simulation, 0.2K/W or less per joint surface is desirable, and 0.15K/W or less per joint surface is more desirable.

In the comparative example 3, although the thermal stress is 403 Mpa and small enough, the value of the thermal resistance is 0.298K/W and a large value, it is not suitable for the junction of the power semiconductor.

In the examples 8 and 9 in which the thickness of the porous nickel plating20in which the nanodiamonds are embedded into the pores of the surface is 20 μm, the reduction of the heat stress is 10% or less compared with the comparative example 1. On the other hand, in the examples 10 to 13 in which the thickness of the porous nickel plating20in which the nanodiamonds are embedded into the pores of the surface is 100 μm or more, the reduction of the heat stress is 45% or more compared with the comparative example 1, and more effective stress reduction has been confirmed.

As shown in the examples 8 to 13 in TABLE 2, by embedding nanodiamonds into the surface of the porous nickel plating20, the value of the thermal resistance of the junction can be reduced more compared with a porous nickel plating in which the nanodiamonds are not embedded.

Therefore, by embedding the nanodiamonds into the porous nickel plating, a suitable value of the thermal resistance can be obtained by the porous nickel plating with smaller thickness. The heat stress can be reduced more by enlarging the thickness of porous nickel plating with the low value of the thermal resistance maintained.

As described above, in the power semiconductor device in the second embodiment, the porous nickel plating20is applied to the lead frame20, the nanoparticles17with high thermal conductivity are embedded into the pores7of the surface of the porous nickel plating20to the solder layer4, and a layer with a low coefficient of linear expansion, a low modulus of elasticity, and a locally small thermal resistance lies between the semiconductor element5and the lead frame2. Thereby, even when the power semiconductor element5heats, the lead frame expands greatly and a distortion occurs in the layer of porous nickel plating20, the heat stress induced on the solder layer4is eased since the modulus of elasticity of the porous nickel plating20is low.

A heat warp is induced on the solder layer4by the difference of the coefficients of linear expansion of the porous nickel plating20and the power semiconductor element5, but the difference is small, and the heat stress to the solder layer4is reduced. Furthermore, since the thermal resistance of the joint surface of the porous nickel plating20and the solder layer4is small, the thermal diffusion performance in the joint surface is improved, and the heat stress concentration of the junction boundary surface of the layer of the porous nickel plating20and the solder layer4in a thermal cycle is eased.

INDUSTRIAL APPLICABILITY

The semiconductor device and the method of manufacturing the semiconductor device according to the present invention have an effect of reducing a heat stress to the solder layers and can suppress an occurrence of a solder crack, with suppressing an increase of thermal resistance of a junction, and can be used in the field of a car, environment, a residence, and an infrastructure, for example, such as an inverter substrate of a motor of an electric vehicle or a power conditioner of a power generation system used indoors or outdoors.