Distortion reducing semiconductor switch

A semiconductor switch includes a first semiconductor circuit having a nonlinear characteristic, and a second semiconductor circuit having a nonlinear characteristic. Each of the first semiconductor circuit and the second semiconductor circuit is configured to at least one of allow and interrupt transmission of a signal. The first semiconductor circuit reduces the nonlinear characteristic of the second semiconductor circuit and the second semiconductor circuit reduces the nonlinear characteristic of the first semiconductor circuit.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates to a semiconductor switch for use with a mobile communication device, and particularly to a high-frequency semiconductor switch that is used for switching between signal transmission and reception in an antenna of a mobile phone or the like.

(2) Description of the Related Art

With the recent developments in the field of mobile communications, a small, low-power high-frequency semiconductor switch has been desired as a semiconductor switch dedicated to switching between signal transmission and reception in an antenna of a mobile phone or the like. In these days, a semiconductor switch that utilizes a gallium arsenide field-effect transistor that is superior in terms of power consumption is used instead of the mainstream semiconductor switch that utilizes a silicon PIN diode.

The following describes a high-frequency semiconductor switch that utilizes such a field-effect transistor (FET).FIG. 1is a circuit diagram showing a conventional semiconductor switch.

This semiconductor switch is made up of an input terminal501, an output terminal502, a through FET505that allows or interrupts the transmission of a high-frequency signal between the input terminal501and the output terminal502, and a shunt FET506that connects and disconnects the output terminal502and the ground. In this case, the gate electrode of the through FET505is connected to a control terminal503via a resistance507, and the gate electrode of the shunt FET506is connected to a control terminal504via a resistance508. These resistances507and508are inserted for the protection of the gate electrodes. In general, resistances whose resistance values are several times as great as those of the characteristic impedance of a line are selected as the resistances507and508.

In the semiconductor switch with the above structure, the input terminal501and the output terminal502become connected when the through FET505is turned to the ON-state and the shunt FET506is turned to the OFF-state by applying, to the control terminal503, a voltage higher than the pinch-off voltage of the through FET505and by applying, to the control terminal504, a voltage lower than the pinch-off voltage of the shunt FET506, respectively. Meanwhile, when the through FET505is turned to the OFF-state and the shunt FET506is turned to the ON-state, the connection of the input terminal501and the output terminal502are broken, and the output terminal502becomes connected to the ground.

Technologies for improving the linearity in the transmission property of such a semiconductor switch described above include, for example, a method that uses FETs with different pinch-off voltages as a through FET and a shunt FET. Japanese Laid-Open Patent application No. 07-106937 discloses a semiconductor switch using this method. This technology reduces a distortion in a semiconductor switch by controlling power leakage that occurs when the shunt FET is in the OFF-state by using, for example, a FET with a pinch-off voltage of −1.0V as the through FET and a FET with a pinch-off voltage lower than 0.5V as the shunt FET. However, such a semiconductor switch has a problem of poor controllability of pinch-off voltage and an increase in the manufacturing costs since FETs with different pinch-off voltages are formed in the same substrate.

SUMMARY OF THE INVENTION

The conventional semiconductor switch has a problem as described below.

The current-voltage characteristics between the source and the drain of a FET in the ON-state are not completely linear. Thus, while the conventional semiconductor switch is capable of reducing a distortion attributable to the shunt FET, it cannot reduce a distortion attributable to the through FET because a harmonic distortion is generated without fail at a point in time when a high-frequency signal passes through the through FET that is connected serially to the signal path. The value of such a harmonic distortion is greater as the voltage amplitude of a high-frequency signal is larger. In the case where a semiconductor switch with such harmonic distortion is used for a mobile phone or the like, power leakage into another frequency band occurs. Thus, a semiconductor switch for use with a mobile phone or the like is particularly required to be capable of reducing harmonic distortion of a signal passing through such semiconductor switch.

The present invention has been conceived in view of the above problem, and it is an object of the present invention to provide a semiconductor switch that is capable of reducing harmonic distortion of a signal passing through such semiconductor switch.

In order to achieve the above object, the semiconductor switch according to the present invention is a semiconductor switch including a first semiconductor circuit having a nonlinear characteristic and a second semiconductor circuit having a nonlinear characteristic, each allowing or interrupting transmission of a signal, wherein the first semiconductor circuit and the second semiconductor circuit reduce each other's nonlinear characteristic. Here, a current-voltage characteristic of the first semiconductor circuit may satisfy I1=Σai*(V1)i, where V1is a voltage applied to the first semiconductor circuit, I1is an electric current that passes through the first semiconductor circuit when the V1is applied, and aiis a constant, and a current-voltage characteristic of the second semiconductor circuit may satisfy I2=Σbi*(V2)i, where V2is a voltage applied to the second semiconductor circuit, I2is an electric current that passes through the second semiconductor circuit when the V2is applied, and biis a constant, wherein the signs of ajand bjof at least one pair of aiand biare different, where j is 2 or a larger integer.

Accordingly, harmonic distortion of a signal passing through the semiconductor switch is reduced since it is possible to reduce the ith-order harmonic distortion by causing the first semiconductor circuit and the second semiconductor circuit to reduce each other's absolute value of the ith order coefficient included in the power series obtained by expanding the current-voltage characteristics.

Furthermore, the first semiconductor circuit and the second semiconductor circuit may be connected in parallel with each other, the first semiconductor circuit may include a field-effect transistor, and the second semiconductor circuit may include a diode. The diode of the second semiconductor circuit may include a first diode and a second diode that are placed in parallel with each other, wherein a forward current of the first diode may be in a direction from a signal output side to a signal input side of the second semiconductor circuit, and a forward current of the second diode may be in a direction from the signal input side to the signal output side of the second semiconductor circuit. The second semiconductor circuit may include: a first voltage generating circuit that is connected to the first diode and that shifts an ON-voltage of the first diode; and a second voltage generating circuit that is connected to the second diode and that shifts an ON-voltage of the second diode.

Accordingly, it is possible to reduce the third-order harmonic distortion of a signal passing through the semiconductor switch.

Moreover, the first semiconductor circuit and the second semiconductor circuit may be connected in parallel with each other, the first semiconductor circuit may include a field-effect transistor, and the second semiconductor circuit may include a field-effect transistor in which a gate and one of a source and a drain are short-circuited. Here, each of the first field-effect transistor and the second field-effect transistor may be a multi-gate field-effect transistor.

Accordingly, it becomes possible to provide a semiconductor switch that is easier to manufacture since the distortion reducing circuit is formed only by a FET.

Furthermore, the second semiconductor circuit may include a first field-effect transistor and a second field-effect transistor that are placed in parallel with each other, wherein a gate and one of a source and a drain of the first field-effect transistor may be short-circuited at a signal input side of the second semiconductor circuit, and a gate and one of a source and a drain of the second field-effect transistor may be short-circuited at a signal output side of the second semiconductor circuit. Here, the field-effect transistor of the second semiconductor circuit may be a multi-gate field-effect transistor.

Accordingly, it becomes possible to provide a small semiconductor switch since there is no need to be equipped with a FET dedicated to turning the distortion reducing circuit to the OFF-state. In other words, it becomes possible to provide a semiconductor switch whose chip area can be reduced.

As is obvious from the above description, the semiconductor switch according to the present invention is capable of improving the linearity of the current-voltage characteristics of the semiconductor switch since the second semiconductor circuit reduces the current-voltage characteristics of the first semiconductor circuit so as to approximate such current-voltage characteristics to be linear. In other words, it is possible for the semiconductor switch of the present invention to reduce a harmonic distortion that is generated by a high-frequency signal passing through the semiconductor switch.

The disclosure of Japanese Patent Application No. 2004-161036 filed on May 31, 2004 including specification, drawings and claims is incorporated herein by reference in its entirety.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following describes a semiconductor switch according to the preferred embodiments of the present invention with reference to the drawings.

First Embodiment

FIG. 2is a circuit diagram showing a semiconductor switch according the first embodiment of the present invention.

Such semiconductor switch is made up of: an input terminal101; an output terminal102; a through FET106that is connected serially to the signal path between the input terminal101and the output terminal102; a shunt FET107that is connected in between the output terminal102and the ground; and a distortion reducing circuit120that is connected in parallel with the through FET106. Note that the through FET106forms a first semiconductor circuit and the distortion reducing circuit120forms a second semiconductor circuit.

The distortion reducing circuit120, which is a circuit for approximating the current-voltage characteristics of the semiconductor switch to be linear, is made up of: a first diode109and a second diode110that are placed in parallel with each other; a first constant voltage source111and a second constant voltage source112that are placed in parallel with each other and that have a voltage of 0.64V, for example; and a FET108. In this structure, the first diode109has reverse characteristics in the direction from the input terminal101to the output terminal102, i.e., a forward current of the first diode109is in the direction from the output terminal102to the input terminal101, whereas the second diode110has forward characteristics in the direction from the input terminal101to the output terminal102, i.e., a forward current of the second diode110is in the direction from the input terminal101to the output terminal102. The FET108serves as a switch that prevents an electric current from flowing through the distortion reducing circuit120when the through FET106turns to the OFF-state. The first constant voltage source111is connected to the first diode109so as to shift the ON voltage of the first diode109, whereas the second constant voltage source112is connected to the second diode110so as to shift the ON voltage of the second diode110. Note that the first constant voltage source111and the second constant voltage source112form a first voltage generating circuit and a second voltage generating circuit, respectively.

Here, the gate electrode of the through FET106is connected to the control terminal103via a resistance113, the gate electrode of the shunt FET107is connected to a control terminal105via a resistance114, and the gate electrode of the FET108is connected to a control terminal104via a resistance115. As the through FET106, the shunt FET107, and the FET108, FETs with a gate width of 0.5 mm, a gate length of 0.2 μm, and a pinch-off voltage of −0.7V are used, for example. As the resistances113,114, and115, resistances of 50 kΩ are used.

FIG. 3is a diagram showing the current-voltage characteristics of the through FET106and the distortion reducing circuit120.

FIG. 3shows that current-voltage characteristics21of the through FET106when it is in the ON-state exhibit an upward convex shape in the positive domains of electric current and voltage. This is attributable to the current-voltage characteristics peculiar to a FET. Thus, the following is derived by expanding the current-voltage characteristics21of the through FET106into power series:

I⁢⁢1=Σ⁢⁢ai*(V⁢⁢1)i=a0+a1*V⁢⁢1+a2*(V⁢⁢1)2+a3*(V⁢⁢1)3+…
This equation shows that the third-order coefficient a3is a negative value. In the above equation, V1denotes a voltage to be applied to the through FET106, I1denotes an electric current that flows through the through FET106when V1is applied, and ai(i is an integer) denotes a constant.

Meanwhile,FIG. 3also shows that current-voltage characteristics22of the distortion reducing circuit120that is connected in parallel with the through FET106exhibit a downward convex shape in the positive domains of electric current and voltage. This is attributable to the current-voltage characteristics peculiar to a diode. Thus, the following is derived by expanding the current-voltage characteristics22of the distortion reducing circuit120into power series:

I⁢⁢2=Σ⁢⁢bi*(V⁢⁢2)i=b0+b1*V⁢⁢2+b2*(V⁢⁢2)2+b3*(V⁢⁢2)3+…
This equation shows that the third-order coefficient b3is a positive value. In the above equation, V2denotes a voltage to be applied to the distortion reducing circuit120, I2denotes an electric current that flows through the distortion reducing circuit120when V2is applied, and bi(i is an integer) denotes a constant.

Consequently, in the semiconductor switch in which the through FET106and the distortion reducing circuit120are connected in parallel with each other, the through FET106and the distortion reducing circuit120reduce each other's nonlinear characteristics, resulting in a very small absolute value of a nonlinear component of the semiconductor switch that corresponds to the third-order coefficient included in the power series obtained by performing power series expansion. As a result, the current-voltage characteristics23of the semiconductor switch becomes closer to linear. In general, there is a correlation between (1) the absolute value of the n-th order coefficient that is derived by expanding, into power series, the current-voltage characteristics of the signal path between the input terminal and the output terminal and (2) the size of the n-th order harmonic distortion that is generated when a high-frequency power inputted from the input terminal reaches the output terminal. In other words, the greater the absolute value of the n-th order coefficient, the bigger the n-th order harmonic distortion generated at the through FET. It should be noted, however, that a range of voltages obtained by a power series expansion is equal to or lower than the range of the voltage amplitude of a maximum signal that passes through the through FET.

As described above, it is possible to provide a semiconductor switch that is capable of reducing harmonic distortion, since the semiconductor switch according to the present embodiment reduces, through the use of the distortion reducing circuit120, the absolute value of the third-order coefficient that is derived by expanding the current-voltage characteristics of the through FET into power series, thereby reducing the third-order harmonic distortion generated at the through FET.

For example, the following result was obtained by a simulation: in the semiconductor switch shown inFIG. 2, when the through FET106and the FET108are turned to the ON-state and the shunt FET107is turned to the OFF-state respectively by the control terminals103,104, and105, and then a high-frequency signal of 1 GHz and 30 dBm is inputted to the input terminal101, the output value representing the third-order harmonic detected at the output terminal102is −49 dBm; and in the conventional semiconductor switch shown inFIG. 1having no distortion reducing circuit, the output value representing the third-order harmonic detected at the output terminal102is −37 dBm. In other words, the distortion reducing circuit improves the value of the third-order harmonic distortion. Note that in the above simulation, the gate width of the through FET shown inFIG. 1is 1 mm.

Second Embodiment

FIG. 4is a circuit diagram showing a semiconductor switch according to the second embodiment of the present invention.

Such semiconductor switch is different from the semiconductor switch of the first embodiment in the structure of its distortion reducing circuit320that is connected in parallel with the through FET106. The semiconductor switch of the second embodiment is made up of an input terminal101, an output terminal102, a through FET106, a shunt FET107, and a distortion reducing circuit320that is connected in parallel with the through FET106. Note that the distortion reducing circuit320forms the second semiconductor circuit.

The distortion reducing circuit320, which is a circuit for approximating the current-voltage characteristics of the semiconductor switch to be linear, is made up of: a first FET309and a second FET310that are connected in parallel with each other; and a FET308that is connected serially to the first FET309and the second FET310. In this structure, the gate and one of the source and the drain of the first FET309are short-circuited at the input terminal101side, whereas the gate and one of the source and the drain of the second FET310are short-circuited at the output terminal102side. The FET308serves as a switch that prevents an electric current from flowing through the distortion reducing circuit320when the through FET106turns to the OFF-state.

Here, the gate electrode of the FET308is connected to a control terminal304via a resistance313.

As described above, according to the semiconductor switch of the second embodiment, it is possible to provide a semiconductor switch that is capable of reducing harmonic distortion, as in the case of the semiconductor switch of the first embodiment.

Moreover, since the distortion reducing circuit320of the semiconductor switch of the second embodiment does not have a voltage generating circuit, it is possible to provide a semiconductor switch that is easier to manufacture than the semiconductor switch of the first embodiment.

Third Embodiment

FIG. 5is a circuit diagram showing a semiconductor switch according to the third embodiment of the present invention.

Such semiconductor switch is different from the semiconductor switch of the second embodiment in the structure of its distortion reducing circuit420that is connected in parallel with a through FET106. The semiconductor switch of the third embodiment is made up of an input terminal101, an output terminal102, a through FET106, a shunt FET107, and a distortion reducing circuit420that is connected in parallel with the through FET106. Note that the distortion reducing circuit420forms the second semiconductor circuit.

The distortion reducing circuit420, which is a circuit for approximating the current-voltage characteristics of the semiconductor switch to be linear, is made up of a first dual gate FET409and a second dual gate FET410that are connected in parallel with each other. In this structure, one of the gates and the source or the drain of the first dual gate FET409are short-circuited at the input terminal101side, whereas one of the gates and the source or the drain of the second dual gate FET410are short-circuited at the output terminal102side. The other gate of the first dual gate FET409is connected to a control terminal404via a resistance413, whereas the other gate of the second dual gate FET410is connected to a control terminal405via a resistance414. The first dual gate409and the second dual gate410serve as switches that prevent an electric current from flowing through the distortion reducing circuit420when the through FET106turns to the OFF-state.

As described above, according to the semiconductor switch of the third embodiment, it is possible to provide a semiconductor switch that is capable of reducing harmonic distortion, as in the case of the semiconductor switch of the first embodiment.

Moreover, it is possible to provide a small semiconductor switch since the multi-gate FETs are used in the distortion reducing circuit420of the semiconductor switch of the third embodiment, and thus there is no need to be equipped with a FET dedicated to preventing an electric current from flowing through the distortion reducing circuit420. In other words, it is possible to provide a semiconductor switch whose chip area can be reduced.

For example, the semiconductor switch according to the present invention has a distortion reducing circuit in which the sign of the third-order coefficient that is derived by expanding the current-voltage characteristics into power series, is different from that of the through FET. However, the distortion reducing circuit is not limited to this so long as the current-voltage characteristics of a distortion reducing circuit have a linear shape representing desired current-voltage characteristics, e.g., a shape that is axisymmetric to the current-voltage characteristics of the through FET with respect to the straight line going through the point of origin. Thus, the semiconductor switch may include a distortion reducing circuit in which the sign of the second or greater-order coefficient that is derived by expanding the current-voltage characteristics into power series is different from that of the through FET.

INDUSTRIAL APPLICABILITY

The present invention is suited for use as a semiconductor switch and particularly as a high-frequency semiconductor switch or the like that is used for switching between signal transmission and reception in an antenna of a mobile communication device such as a mobile phone and the like.