VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

A vertical memory device includes a memory channel structure disposed on a substrate, a plurality of division layers disposed on the substrate and a gate electrode structure. The memory channel structure extends in a vertical direction substantially perpendicular to an upper surface of the substrate. The division layers contact the memory channel structure, respectively. The gate electrode structure contacts a sidewall of the memory channel structure, which may include a filling pattern, a channel disposed on a sidewall of the filling pattern and a charge storage structure disposed on an outer sidewall of the channel and sidewalls of the division layers, each of which extends through a portion of the charge storage structure and a portion of the channel. Each of the charge storage structure and the channel is divided into two parts by the division layers.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0019716, filed on Feb. 15, 2023 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

Embodiments of the inventive concept relate to a semiconductor device, and more particularly, a vertical memory device.

DISCUSSION OF RELATED ART

In an electronic system that utilizes data storage, a high-capacity semiconductor device may be implemented to store large amounts of data. Various methods have been studied to increase the data storage capacity of such a semiconductor device. For example, a semiconductor device including memory cells that are three-dimensionally stacked may be utilized.

SUMMARY

Example embodiments provide a vertical memory device having improved electrical characteristics.

According to example embodiments, there is provided a vertical memory device. The vertical memory device may include a memory channel structure disposed on a substrate, a plurality of division layers disposed on the substrate and a gate electrode structure. The memory channel structure may extend in a vertical direction substantially perpendicular to an upper surface of the substrate. The division layers may contact the memory channel structure, respectively. The gate electrode structure may contact a sidewall of the memory channel structure, which may include a filling pattern, a channel disposed on a sidewall of the filling pattern and a charge storage structure disposed on an outer sidewall of the channel and sidewalls of the division layers, each of which may extend through a portion of the charge storage structure and a portion of the channel. Each of the charge storage structure and the channel is divided into two parts by the division layers.

According to example embodiments, there is provided a vertical memory device. The vertical memory device may include a memory channel structure disposed on a substrate, a division layer disposed on the substrate, and a gate electrode structure contacting a sidewall of the memory channel structure and a sidewall of the division layer. The memory channel structure, which may extend in a vertical direction substantially perpendicular to an upper surface of the substrate, may be disposed on the substrate and may include a filling pattern, a channel disposed on a sidewall of the filling pattern and a charge storage structure disposed on an outer sidewall of the channel. The charge storage structure may include a tunnel insulation pattern, a charge storage pattern and a blocking pattern sequentially stacked from the outer sidewall of the channel in a horizontal direction substantially parallel to the upper surface of the substrate. The division layer may extend through a portion of the blocking pattern and contact the charge storage pattern, which may include an air gap including air at a portion of the charge storage pattern contacting the division layer.

According to example embodiments, there is provided a semiconductor device. The vertical memory device may include a memory channel structure disposed on a substrate, a plurality of division layers disposed on the substrate and a gate electrode structure contacting a sidewall of the memory channel structure and sidewalls of the division layers. The memory channel structure may extend in a vertical direction substantially perpendicular to an upper surface of the substrate. The charge storage structure may include a tunnel insulation pattern, a charge storage pattern and a blocking pattern sequentially stacked from an outer sidewall of the channel in a horizontal direction substantially parallel to the upper surface of the substrate. Each of the division layers may extend through a portion of the blocking pattern, which may be divided into two parts by the division layers, and may contact the memory channel structure, which may include a filling pattern, a channel on a sidewall of the filling pattern and a charge storage structure on an outer sidewall of the channel, and may have a shape of a circle or an ellipse in a plan view.

In a vertical memory device in accordance with example embodiments, a gate electrode surrounding a single memory channel structure may be divided, or a charge storage structure or a channel included in the memory channel structure may be divided, so that the vertical memory device may have a multi-bit level cell (MLC) structure.

DETAILED DESCRIPTION

The above and other features of the inventive concept will become more apparent by describing in detail embodiments thereof with reference to the accompanying drawings.

It should be understood that descriptions of features or aspects within each example embodiment should typically be considered as available for other similar features or aspects in other example embodiments, unless the context clearly indicates otherwise.

It will be understood that when a component such as a film, a region, a layer, etc., is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another component, it can be directly on, connected, coupled, or adjacent to the other component, or intervening components may be present. It will also be understood that when a component is referred to as being “between” two components, it can be the only component between the two components, or one or more intervening components may also be present. It will also be understood that when a component is referred to as “covering” another component, it can be the only component covering the other component, or one or more intervening components may also be covering the other component. Other words used to describe the relationships between components should be interpreted in a like fashion.

Herein, when two or more elements or values are described as being substantially the same as or about equal to each other, it is to be understood that the elements or values are identical to each other, the elements or values are equal to each other within a measurement error, or if measurably unequal, are close enough in value to be functionally equal to each other as would be understood by a person having ordinary skill in the art. For example, the term “about” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (e.g., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations as understood by one of the ordinary skill in the art. Further, it is to be understood that while parameters may be described herein as having “about” a certain value, according to exemplary embodiments, the parameter may be exactly the certain value or approximately the certain value within a measurement error as would be understood by a person having ordinary skill in the art.

It will be further understood that when two components or directions are described as extending substantially parallel or perpendicular to each other, the two components or directions extend exactly parallel or perpendicular to each other, or extend approximately parallel or perpendicular to each other within a measurement error as would be understood by a person having ordinary skill in the art.

It will be understood that, although the terms “first,” “second,” “third”, etc. may be used herein to describe various materials, layers, regions, pads, electrodes, patterns, structure and/or processes, these various materials, layers, regions, pads, electrodes, patterns, structure and/or processes should not be limited by these terms. These terms are only used to distinguish one material, layer, region, pad, electrode, pattern, structure or process from another material, layer, region, pad, electrode, pattern, structure or process. Thus, “first”, “second”, “third”, etc. may be used selectively or interchangeably for each material, layer, region, electrode, pad, pattern, structure or process respectively.

Hereinafter, a vertical direction substantially perpendicular to an upper surface of a substrate may be referred to as a first direction D1, and two directions crossing each other among horizontal directions substantially parallel to the upper surface of the substrate may be referred to as second and third directions D2and D3, respectively. Additionally, two directions among the horizontal directions, which may have an acute angle with respect to each of the first and second directions D2and D3and may be substantially perpendicular to each other, may be referred to as fourth and fifth directions D4and D5, respectively.

FIG.1is a plan view illustrating a vertical memory device in accordance with example embodiments, and each ofFIGS.2A and2Bis a cross-sectional view taken along line A-A′ ofFIG.1.

Referring toFIGS.1and2A, the vertical memory device may include a first memory channel structure285, a first division layer302and a first gate electrode330disposed on a first substrate100.

The vertical memory device may further include a first insulation layer170, a second blocking pattern320, a first contact plug350, a bit line370, and first to fourth insulating interlayers190,310,340and360.

The first substrate100may include a semiconductor material, e.g., silicon, germanium and silicon-germanium, or a III-V compound, e.g., GaP, GaAs, GaSb, etc. In example embodiments, the first substrate100may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

The first memory channel structure285may extend in the first direction D1on the first substrate100. In an example embodiment, the first memory channel structure285may extend through an upper portion of the first substrate100.

The first memory channel structure285may have various shapes, e.g., a shape of a circle, an ellipse, a polygon, a polygon with rounded vertices, etc., in a plan view. In example embodiments, a plurality of first memory channel structures285may be spaced apart from each other in the second and third directions D2and D3to define a first memory channel structure array.

In example embodiments, the first memory channel structure array may include a plurality of first memory channel structure rows, each of which may include a plurality of first memory channel structures285spaced apart from each other in the second direction D2, spaced apart from each other in the third direction D3. The first memory channel structure array may include a plurality of first memory channel structure columns, each of which may include a plurality of first memory channel structures285spaced apart from each other in the fourth direction D4, spaced apart from each other in the second direction D2.

The first memory channel structure285may have a first filling pattern265having a pillar shape extending in the first direction D1, a first channel255having a cup shape covering a sidewall and a lower surface of the first filling pattern265and contacting the upper surface of the first substrate100, a first capping pattern275disposed on the first filling pattern265and the first channel255, and a first charge storage structure245having a cylindrical shape covering an outer sidewall of the first channel255and a sidewall of the first capping pattern275. The first charge storage structure245may include a first tunnel insulation pattern235, a first charge storage pattern225and a first blocking pattern215sequentially stacked in the horizontal direction from the outer sidewall of the first channel255and the sidewall of the first capping pattern275.

The first filling pattern265may include an oxide, e.g., silicon oxide, the first channel255may include, e.g., polysilicon, and the first capping pattern275may include, e.g., polysilicon doped with impurities, a metal, a metal nitride, etc.

The first tunnel insulation pattern235may include an oxide, e.g., silicon oxide or an oxynitride, e.g., silicon oxynitride. In an example embodiment, the first tunnel insulation pattern235may include a first layer including silicon oxide and a second layer including silicon oxynitride.

The first blocking pattern215may include an oxide, e.g., silicon oxide, and the first charge storage pattern225may include a nitride, e.g., silicon nitride.

The first division layer302may have a shape of a pillar extending in the first direction D1on the first substrate100. In an example embodiment, the first division layer302may extend through the upper portion of the first substrate100, and thus, a lower surface of the first division layer302may be disposed lower than the upper surface of the first substrate100. Alternatively, the lower surface of the first division layer302may be disposed higher than the upper surface of the first substrate100, however, the lower surface of the first division layer302may be disposed lower than an upper surface of a lowermost one of the first insulation layers170.

In example embodiments, the first division layer302may partially contact an outer sidewall of each of ones of the first charge storage structures245neighboring in the fourth direction D4in each of the first memory channel structure columns, for example, an outer sidewall of each of ones of the first blocking patterns215neighboring in the fourth direction D4.

In example embodiments, the first division layer302may have various shapes of, e.g., a circle, an ellipse, a polygon, a polygon with rounded vertices, etc., in a plan view, and may include an oxide, e.g., silicon oxide.

In example embodiments, a plurality of first division layers302may be spaced apart from each other in the second and third directions D2and D3to define a first division layer array.

In example embodiments, the first division layer array may include a plurality of first division layer rows, each of which may include a plurality of first division layers302spaced apart from each other in the second direction D2, spaced apart from each other in the third direction D3. In addition, the first division layer array may include a plurality of first division layer columns, each of which may include a plurality of first division layers302spaced apart from each other in the fourth direction D4, spaced apart from each other in the second direction D2.

A plurality of first gate electrodes330may be spaced apart from each other in the first direction D1on the substrate100to form a first gate electrode structure. The first insulation layer170may be disposed between ones of the first gate electrodes330disposed adjacent to each other in the first direction D1. The first insulation layer170may include an oxide, e.g., silicon oxide.

In example embodiments, the first gate electrode structure may extend in the fourth direction D4, and a plurality of first gate electrode structures may be spaced apart from each other in the second direction D2. In example embodiments, the first memory channel structures285included in the first memory channel structure column and the first division layers302included in the first division layer columns may be disposed between ones of the first gate electrode structures disposed adjacent to each other in the second direction D2.

In example embodiments, the first gate electrodes330included in each of the first gate electrode structures and sequentially stacked in the first direction D1may serve as a ground select line (GSL), a word line and a string select line (SSL), respectively, depending on positions thereof. In an example embodiment, one of the first gate electrodes330disposed at a lowermost level in the first gate electrode structure may serve as the GSL, one of the first gate electrodes330disposed at an uppermost level and one of the first gate electrodes330disposed at a second level from above in the first gate electrode structure may serve as the SSL, and ones of the first gate electrodes330disposed at a plurality of levels between the GSL and the SSL may serve as the word line.

Each of the first gate electrodes330may include a first gate conductive pattern and a first gate barrier pattern covering upper and lower surfaces and a portion of a sidewall of the first gate conductive pattern. The first gate conductive pattern may include a metal having a low electrical resistance, e.g., tungsten, titanium, tantalum, platinum, etc., and the first gate barrier pattern may include a metal nitride, e.g., titanium nitride, tantalum nitride, etc.

Upper and lower surfaces and a sidewall facing the first memory channel structure285of each of the first gate electrodes330may be covered by the second blocking pattern320. The second blocking pattern320may include a metal oxide, e.g., aluminum oxide or hafnium oxide.

The first insulating interlayer190may be disposed on an uppermost one of the first insulation layers170, the second insulating interlayer310may be disposed on the first insulating interlayer190, the first memory channel structure285and the first division layer302, and the third and fourth insulating interlayers340and360may be sequentially stacked on the second insulating interlayer310. Each of the first to fourth insulating interlayers190,310,340and360may include an oxide, e.g., silicon oxide or a low-k dielectric material.

The first contact plug350may extend through the second and third insulating interlayers310and340, and contact an upper surface of the first capping pattern275. The bit line370may extend in the second direction D2, and may contact the first contact plugs350under the bit line370. In example embodiments, a plurality of bit lines370may be spaced apart from each other in the third direction D3.

Referring toFIG.2B, a first sacrificial layer180may be disposed instead of each of the first gate electrodes330and the second blocking pattern320. The first sacrificial layer180may include, as described below with reference toFIGS.3to8, for example, polysilicon doped with impurities instead of an insulating material such as silicon nitride. Thus, the first sacrificial layer180may serve as a gate electrode, instead of being replaced by the first gate electrode330.

As described above, in the vertical memory device, the first gate electrode structure may extend in the fourth direction D4, and a plurality of the first gate electrode structures may be spaced apart from each other in the second direction D2by the first memory channel structures285included in the first memory channel structure column and the first division layers302included in the first division layer column corresponding to the first memory channel structures.

Accordingly, when compared to a vertical memory device including, for example, a single gate electrode structure surrounding a single first memory channel structure285, the vertical memory device in accordance with example embodiments may include two first memory electrode structures respectively disposed at opposite sides in the fifth direction D5of a single first memory channel structure285, so that the vertical memory device may have a multi-bit level cell (MLC) structure.

FIGS.3to8are plan views and cross-sectional views illustrating a method of manufacturing a vertical memory device in accordance with example embodiments. For example,FIGS.4and6are plan views, andFIGS.3,5and7-8are cross-sectional views taken along lines A-A′ of corresponding plan views, respectively.

Referring toFIG.3, a first insulation layer170and a first sacrificial layer180may be alternately and repeatedly stacked on a first substrate100in a first direction D1, and thus, a first mold layer may be formed on the substrate100.

The first insulation layer170may include, for example, an oxide such as silicon oxide, and the first sacrificial layer180may include a material having a high etching selectivity with respect to the first insulation layer170, for example, a nitride such as silicon nitride.

Referring toFIGS.4and5, after a first insulating interlayer190is formed on the first mold layer, a first hole200may be formed through the first insulating interlayer190and the first mold layer to expose an upper surface of the first substrate100by, for example, a dry etching process.

In example embodiments, the dry etching process may be performed until the first hole200exposes the upper surface of the first substrate100, and further, the first hole200may extend through an upper portion of the first substrate100. A plurality of first holes200may be spaced apart from each other in the second and third directions D2and D3to define a first hole array. The first hole array may include a plurality of first hole rows spaced apart from each other in the third direction D3, and each of the first hole rows may include a plurality of first holes200spaced apart from each other in the second direction D2.

In example embodiments, ones of the first holes200respectively included in the first hole rows disposed adjacent to each other in the third direction D3may be arranged in the fourth direction D4. Thus, ones of the first holes200spaced apart from each other in the fourth direction D4may define a first hole column, and the first hole array may include a plurality of first hole columns spaced apart from each other in the second direction D2.

In an example embodiment, ones of the first holes200respectively included in the first hole rows disposed adjacent to each other in the third direction D3do not overlap each other in the third direction D3, however embodiments of the inventive concept are not limited thereto.

In example embodiments, the first hole200may have a shape of, e.g., a circle, an ellipse, a polygon, a polygon with rounded vertices, etc., in a plan view, however, embodiments of the inventive concept are not limited thereto.

A first charge storage layer structure may be formed on a sidewall of the first hole200, the exposed upper surface of the substrate100and an upper surface of the first insulating interlayer190, and an anisotropic etching process may be performed on the first charge storage layer structure to form a first charge storage structure245on the sidewall of the first hole200.

A first channel layer may be formed on the upper surface of the first substrate100, an inner sidewall and an upper surface of the first charge storage structure245, and the upper surface of the first insulating interlayer190, and a first filling layer may be formed to fill the first hole200.

The first filling layer and the first channel layer may be planarized until the upper surface of the first insulating interlayer190is exposed to form a first filling pattern265and a first channel255, respectively. Accordingly, the first filling pattern265, the first channel255covering a sidewall and a lower surface of the first filling pattern265, and the first charge storage structure245covering an outer sidewall of the first channel255may be formed in the first hole200. The first charge storage structure245may include a first blocking pattern215, a first charge storage pattern225and a first tunnel insulation pattern235sequentially stacked from the sidewall of the first hole200.

Upper portions of the first filling pattern265and the first channel255may be removed to form a first recess, a first capping layer may be formed on the first filling pattern265, the first channel255, the first charge storage structure245and the first insulating interlayer190to fill the first recess, and the first capping layer may be planarized until the upper surface of the first insulating interlayer190is exposed to form a first capping pattern275contacting an inner upper sidewall of the first charge storage structure245on the first filling pattern265and the first channel255.

The first charge storage structure245, the first channel255, the first filling pattern265and the first capping pattern275in each of the first holes200may collectively form a first memory channel structure285. As the first holes200, in which the first memory channel structures285are respectively formed, define the first hole array, the first memory channel structures285disposed in the first holes200, respectively, may correspondingly define a first memory channel structure array.

The first memory channel structure array may include a plurality of first memory channel structure rows spaced apart from each other in the third direction D3, and each of the first memory channel structure rows may include a plurality of first memory channel structures285spaced apart from each other in the second direction D2. Additionally, the first memory channel structure array may include a plurality of first memory channel structure columns spaced apart from each other in the second direction D2, and each of the first memory channel structure columns may include a plurality of first memory channel structures285spaced apart from each other in the fourth direction D4.

Referring toFIGS.6and7, a second hole292may be formed through the first insulating interlayer190and the first mold layer by, e.g., a dry etching process, to expose the upper surface of the first substrate100.

In example embodiments, the dry etching process may be performed until the second hole292exposes the upper surface of the first substrate100, and further, the second hole292may be formed to extend through the upper portion of the first substrate100. However, embodiments of the inventive concept are not limited thereto. For example, in an example embodiment, the second hole292does not expose the upper surface of the first substrate100. In this case, the second hole292may extend through at least a lowermost one of the first sacrificial layers180, and thus, a bottom of the second hole292may be disposed lower than a lower surface of the lowermost one of the first sacrificial layers180.

In example embodiments, the second hole292may extend through a portion of the first mold layer between ones of the first memory channels structures285neighboring in the fourth direction D4in each of the first memory channel structure columns to partially expose a sidewall of the first charge storage structure245included in each of the ones of the first memory channel structures285. The second hole292may partially extend through an outer lateral portion of the first charge storage structure245, for example, an outer lateral portion of the first blocking pattern215.

In example embodiments, a plurality of second holes292may be spaced apart from each other in the fourth direction D4to form a second hole column, and a plurality of second hole columns may be spaced apart from each other in the second direction D2to define a second hole array.

Accordingly, the first mold layer may be divided in the fifth direction D5by ones of the first memory channel structures285spaced apart from each other in the fourth direction D4in the first memory channel structure column and ones of the second holes292spaced apart from each other in the fourth direction D4in the second hole column corresponding to the first memory channel structure285. Additionally, a plurality of first memory channel structure columns may be spaced apart from each other in the second direction D2and a plurality of second hole columns may be spaced apart from each other in the second direction D2. Accordingly, the first mold layer may be divided into a plurality of parts in the second direction D2.

In example embodiments, the second hole292may have a shape of, e.g., a circle, an ellipse, a polygon, a polygon with rounded vertices, etc., in a plan view.

Referring toFIG.8, after the first division layer302is formed on the first substrate100to fill the second hole292, a second insulating interlayer310may be formed on the first insulating interlayer190, the first memory channel structure285and the first division layer302.

As the second holes292, in which the first division layers302are respectively formed, define the second hole array, the first division layers302respectively formed in the second holes292may define a first division layer array.

The first division layer array may include a plurality of first division layer rows spaced apart from each other in the third direction D3, and each of the first division layer rows may include a plurality of first division layers302spaced apart from each other in the second direction D2. Additionally, the first division layer array may include a plurality of first division layer columns spaced apart from each other in the second direction D2, and each of the first division layer columns may include a plurality of first division layers302spaced apart from each other in the fourth direction D4.

Referring back toFIGS.1and2A, a first opening may be formed through the first and second insulating interlayers190and310and the first mold layer to expose the upper surface of the first substrate100, and the first sacrificial layers180exposed by the first opening may be removed to form first gaps, respectively, exposing a sidewall of the first memory channel structure285.

A second blocking layer may be formed on the sidewall of the first memory channel structure285exposed by the first gaps, inner walls of the first gaps, sidewalls of the first insulation layers170and the upper surface of the first substrate100exposed by the first openings and an upper surface of the second insulating interlayer310. A first gate electrode layer may be formed on the second blocking layer to fill the first gaps and the first opening. The first gate electrode layer may include a first gate barrier layer and a first gate conductive layer sequentially stacked.

The first gate electrode layer may be partially removed to form a first gate electrode330inside each of the first gaps. The first gate electrode330may include a first gate conductive pattern and a first gate barrier pattern covering upper and lower surfaces and a portion of a sidewall of the first gate conductive pattern. In example embodiments, the first gate electrode layer may be partially removed by a wet etching process.

In example embodiments, the first gate electrode330may extend in the fourth direction D4, and a plurality of first gate electrodes330may be stacked in a plurality of levels, respectively, spaced apart from each other in the first direction D1to form a first gate electrode structure. In example embodiments, a plurality of first gate electrode structures may be spaced apart from each other in the second direction D2by the first memory channel structure column, which may include ones of the first memory channel structures285disposed in the fourth direction D4, and the first division layer column, which may include ones of the first division layers302disposed in the fourth direction D4.

When the first gate electrode layer is partially removed, a portion of the second blocking layer disposed on the upper surface of the second insulating interlayer310may also be removed, and a remaining portion of the second blocking layer may form a second blocking pattern320.

A second division layer may be formed in the first opening.

However, referring toFIG.2B, in an example embodiment, the first sacrificial layer180is not replaced with the first gate electrode330and the second blocking pattern320. In this case, the first sacrificial layer180may include a conductive material, e.g., polysilicon doped with impurities instead of an insulating material, e.g., silicon nitride.

After forming a third insulating interlayer340on the second insulating interlayer310, the second division layer and the second blocking pattern320, a first contact plug350may be formed through the second and third insulating interlayers310and340to contact an upper surface of the first capping pattern275.

A fourth insulating interlayer360may be formed on the third insulating interlayer340and the first contact plug350, and a bit line370may be further formed through the fourth insulating interlayer360to contact an upper surface of the first contact plug350. In example embodiments, the bit line370may extend in the second direction D2, and a plurality of bit lines370may be spaced apart from each other in the third direction D3.

Upper contact plugs contacting upper surfaces of the first gate electrodes330and upper wirings that apply electrical signals to the upper contact plugs may additionally be formed to complete the fabrication of the vertical memory device.

As described above, the second holes292may be formed to extend through respective portions of the first mold layer between neighboring ones of the first memory channel structures285, and the first division layers302may be formed in the second holes292, respectively. Thus, the first gate electrode330, which may be formed by replacing the first sacrificial layer180included in the first mold layer, may extend in the fourth direction D4, and may be divided in the second direction D2by the first memory channel structures285and the first division layers302.

FIGS.9and10are a plan view and a cross-sectional view illustrating a vertical memory device in accordance with example embodiments, which may correspond toFIGS.6and8, respectively. The vertical memory device ofFIGS.9and10may be substantially the same as or similar to that ofFIGS.1and2A, except that the vertical memory device ofFIGS.9and10may include a third hole294and a third division layer304instead of the second hole292and the first division layer302, respectively. For convenience of explanation, a further description of components and technical aspects previously described may be omitted.

Referring toFIGS.9and10, the third hole294may extend through the first charge storage structure245included in each of the first memory channel structures285disposed adjacent to each other in the fourth direction D4, for example, the first blocking pattern215and the first charge storage pattern225, and may also extend through an outer lateral portion of the first tunnel insulation pattern235. Thus, the third division layer304in the third hole294may contact an outer sidewall of the first tunnel insulation pattern235.

Accordingly, a single first memory channel structure285included in the vertical memory device may include two first charge storage patterns225separated from each other in the fifth direction D5.

As a result, the vertical memory device may include not only two first gate electrodes330respectively formed at opposite sides of the single first memory channel structure285in the fifth direction D5, but also two first charge storage patterns225separated from each other in the fifth direction D5, so as to have an MLC structure.

FIGS.11and12are a plan view and a cross-sectional view illustrating a vertical memory device in accordance with example embodiments, which may correspond toFIGS.6and8, respectively. The vertical memory device ofFIGS.11and12may be substantially the same as or similar to that ofFIGS.1and2A, except that the vertical memory device ofFIGS.11and12may include a fourth hole296and a fourth division layer306instead of the second hole292and the first division layer302, respectively. For convenience of explanation, a further description of components and technical aspects previously described may be omitted.

Referring toFIGS.11and12, the fourth hole296may extend through the first charge storage structure245and the first channel included in each of the first memory channel structures285disposed adjacent to each other in the fourth direction D4, and the fourth division layer306in the fourth hole296may contact sidewalls of the first filling pattern265and the first capping pattern275.

Accordingly, a single first memory channel structure285in the vertical memory device may include two first charge storage structures245separated from each other in the fifth direction D5and two first channels255separated from each other in the fifth direction D5.

As a result, the vertical memory device may include not only two first gate electrodes330respectively formed at opposite sides of the single first memory channel structure285in the fifth direction D5, but also two first charge storage patterns225and two first channels255separated from each other in the fifth direction D5, so as to have an MLC structure.

FIG.13is a plan view illustrating a vertical memory device in accordance with example embodiments, which may correspond toFIG.11. The vertical memory device ofFIG.13may be substantially the same as or similar to that ofFIGS.11and12, except that the vertical memory device ofFIG.13may include a fifth hole297instead of the fourth hole296. For convenience of explanation, a further description of components and technical aspects previously described may be omitted.

Referring toFIG.13, the fifth hole297may be formed by forming the second hole292, and forming a hole extending through the first charge storage structure245and the first channel255by an additional etching process.

The fifth division layer that may be formed in the fifth hole297may contact sidewalls of the first filling pattern265and the first capping pattern275.

In example embodiments, the second hole292may have a shape of a first circle having a first radius in a plan view, and the additional hole may have a shape of a portion of a second circle, which may protrude outwardly from the first circle and have a second radius smaller than the first radius in a plan view.

Accordingly, the fifth division layer that may be formed in the fifth hole297may have a shape of the first circle having the first radius and the portion of the second circle having the second radius smaller than the first radius and protruding outwardly from the first circle in a plan view, which may correspond to the shape of the fifth hole297.

As a result, a single first memory channel structure285in the vertical memory device may include two first charge storage structures245separated from each other in the fifth direction D5and two first channels255separated from each other in the fifth direction D5.

FIGS.14A,14B, and15are plan views and a cross-sectional view illustrating a vertical memory device in accordance with example embodiments.FIGS.14A and15may correspond toFIGS.6and8, respectively, andFIG.14Bmay correspond toFIG.15.

The vertical memory device ofFIGS.14A,14B and15may be substantially the same as or similar to that ofFIGS.1and2A, except that the vertical memory device ofFIGS.14A,14B and15may further include a first air gap380. For convenience of explanation, a further description of components and technical aspects previously described may be omitted.

Referring toFIGS.14A,14B and15, the second hole292may extend through the first blocking pattern215in each of the first memory channel structures285disposed adjacent to each other in the fourth direction D4to expose a sidewall of the first charge storage pattern225, and the exposed first charge storage pattern225may be partially removed to form the first air gap380.

In example embodiments, the exposed first charge storage pattern225may be partially removed by a wet etching process, and the first air gap380may extend in the first direction D1.

Thus, a single first memory channel structure285in the vertical memory device may include two first blocking patterns215separated from each other in the fifth direction D5, and a portion of the first charge storage pattern225disposed adjacent to the first division layer302may be the first air gap380containing air, instead of a nitride, e.g., silicon nitride.

As the first air gap380may be formed, the first charge storage pattern225may have increased trap sites.

The second hole292may be filled with the first division layer302.

FIGS.16to21are plan views and cross-sectional views illustrating a vertical memory device in accordance with example embodiments.

For example,FIGS.16to18are plan views,FIG.19is a cross-sectional view taken along line B-B′ ofFIG.17,FIG.20is a cross-sectional view taken along line C-C′ ofFIG.17, andFIG.21is a cross-sectional view taken along line E-E′ ofFIG.17.FIG.18is an enlarged plan view of region Z ofFIG.17, andFIGS.17to21correspond to region Y ofFIG.16.

The vertical memory device ofFIGS.16to21may be substantially the same as or similar to that ofFIGS.11and12except for some components. For convenience of explanation, a further description of components and technical aspects previously described may be omitted.

Referring toFIGS.16to21, the vertical memory device may include a second gate electrode structure, a second memory channel structure600and sixth to eighth division layers910,620and710disposed on a second substrate400.

The vertical memory device may further include a support layer450, a sacrificial layer structure440, a channel connection pattern670, a fourth blocking pattern695, a second insulation pattern465, second to fourth contact plugs732,734and736, first to third wirings752,754and756, and fifth to eighth insulating interlayers610,630,720and740.

The second substrate400may include a first region I and a second region II surrounding the first region I.

In example embodiments, the first region I of the second substrate400may be a cell array region, and the second region II of the second substrate400may be a pad region or an extension region. The first and second regions I and II of the second substrate400may collectively form a cell region. That is, memory cells may be disposed in the first region I of the second substrate100, and contact plugs that transfer signals to the memory cells and pads of gate electrodes contacting the contact plugs may be disposed in the second region II of the second substrate400. Although it is illustrated that the second region II may completely surround the first region I, embodiments of the inventive concept are not limited thereto. For example, according to example embodiments, the second region II may be disposed only at opposite sides of the first region I in the second direction D2.

A third region surrounding the second region II of the second substrate400may be further disposed, and a circuit pattern that transfers electrical signals to the memory cells through the contact plugs may be disposed in the third region of the second substrate400.

The sacrificial layer structure440, the channel connection pattern670and the support layer450may be disposed on the second substrate400.

The channel connection pattern670may be disposed in the first region I of the second substrate400, and the sacrificial layer structure440may be disposed in the second region II of the second substrate400. In some embodiments, the channel connection pattern670may include a second air gap680disposed therein.

The support layer450may be disposed on the channel connection pattern670and the sacrificial layer structure440, and may also be disposed in the second opening445extending through the channel connection pattern670and the sacrificial layer structure440to expose an upper surface of the second substrate400. A portion of the support layer450in the second opening445may be referred to as a support pattern.

The support pattern may be disposed in various layouts in a plan view. For example, a plurality of support patterns may be spaced apart from each other in the second and third directions D2and D3in the first region I of the second substrate400, and the support pattern may extend in the second direction D2or the third direction D3on a boundary between the first and second regions I and II of the second substrate400. Additionally, a plurality of support patterns, each of which may extend in the third direction D3, may be spaced apart from each other in the second direction D2in the second region II of the second substrate400.FIG.20shows one of the support patterns extending in the second direction D2on the boundary between the first and second regions I and II of the second substrate400.

The channel connection pattern670may include, for example, polysilicon doped with n-type impurities or undoped polysilicon.

The sacrificial layer structure440may include second to fourth sacrificial layers410,420and430sequentially stacked in the first direction D1. The second and fourth sacrificial layers410and430may each include an oxide, e.g., silicon oxide, and the third sacrificial layer420may include a nitride, e.g., silicon nitride. The support layer450and the support pattern may include a material having an etching selectivity with respect to the second to fourth sacrificial layers410,420and430, for example, polysilicon doped with n-type impurities.

The second gate electrode structure may include second gate electrodes, each of which may extend in the third direction D3, respectively disposed at a plurality of levels spaced apart from each other in the first direction D1on the support layer450and the support pattern. The second insulation pattern465may be disposed between the second gate electrodes and between the second gate electrode and the support layer450and the support pattern. The second insulation pattern465may include an oxide, e.g., silicon oxide.

In example embodiments, the second gate electrode structure may include third to fifth gate electrodes702,704and706sequentially stacked in the first direction D1. In some embodiments, a sixth gate electrode, which may perform a body erase operation using a gate induced drain leakage (GIDL) phenomenon, may be additionally disposed below the third gate electrode702or above the fifth gate electrode706.

In example embodiments, the third gate electrode702may serve as a ground selection line (GSL) and the fifth gate electrode706may serve as a string selection line (SSL).FIGS.19to21show that the third gate electrode702is disposed at a lowermost level and the fifth gate electrodes706are disposed at an uppermost level and a level directly below the uppermost level, respectively. However, embodiments of the inventive concept are not limited thereto, and each of the third and fifth gate electrodes702and706may be disposed at a single level or a plurality of levels according to example embodiments. The fourth gate electrodes704may be disposed at a plurality of levels, respectively, between the third and fifth gate electrodes702and706, and serve as word lines.

In example embodiments, the second gate electrode structure may have a staircase shape in which a length in the third direction D3decreases in a stepwise manner in the first direction D1from a lowermost level toward an uppermost level, and thus, the second gate electrode structure may include steps arranged in the third direction D3in the second region II of the substrate400. In some embodiments, the second gate electrode structure may further include steps arranged in the second direction D2in the second region II of the second substrate400.

Hereinafter, a portion of each of the gate electrodes corresponding to the step of the second gate electrode structure, that is, an end portion of each of the second gate electrodes that is not overlapped by upper ones of the second gate electrodes, may be referred to as a pad. Thus, the pads of the second gate electrodes may be disposed in the second region II of the substrate400.

Each of the third to fifth gate electrodes702,704and706may include a second gate conductive pattern and a second gate barrier pattern covering a surface of the second gate conductive pattern. The second gate conductive pattern may include a metal having a low electrical resistance, e.g., tungsten, titanium, tantalum, platinum, etc., and the second gate barrier pattern may include a metal nitride, e.g., titanium nitride, tantalum nitride, etc.

In example embodiments, a plurality of second gate electrode structures may be spaced apart from each other in the second direction D2. The eighth division layer710extending in the third direction D3may be disposed between ones of the second gate electrode structures disposed adjacent to each other in the second direction D2in the first and second regions I and II of the second substrate400.

The eighth division layer710may include an oxide, e.g., silicon oxide.

In example embodiments, a plurality of memory blocks, each of which may include the second gate electrode structure in an area defined by ones of the eighth division layers710disposed adjacent to each other in the second direction D2and a plurality of the second memory channel structures in the area, may be spaced apart from each other in the second direction D2to form a memory block array.

The second memory channel structure600may include a second charge storage structure560, a second channel570, a second filling pattern580and a second capping pattern590disposed on the second substrate400. In example embodiments, a plurality of second memory channel structures600may be spaced apart from each other in the second and third directions D2and D3in the first region I of the second substrate400to define a second memory channel structure array.

The second memory channel structure array may include a plurality of second memory channel structure rows spaced apart from each other in the third direction D3, and each of the second memory channel structure rows may include a plurality of second memory channel structures600spaced apart from each other in the second direction D2. In addition, the second memory channel structure array may include a plurality of first memory channel structure columns spaced apart from each other in the second direction D2, and each of the first memory channel structure columns may include a plurality of second memory channel structures600spaced apart from each other in the fourth direction D4.

In an example embodiment, each of the second memory channel structures600may have a width that may gradually decrease from an upper portion toward a lower portion thereof.

The sixth division layer910may be disposed between ones of the second memory channel structures600neighboring in the fourth direction D4in each of the second memory channel structure columns in the first region I of the second substrate400, and may extend through the second charge storage structure560and the second channel570in each of the second memory channel structures600. The sixth division layer910may contact sidewalls of the second filling pattern580and the second capping pattern590.

In example embodiments, a plurality of sixth division layers910may be spaced apart from each other in the second and third directions D2and D3to define a sixth division layer array.

The sixth division layer array may include a plurality of sixth division layer rows spaced apart from each other in the third direction D3, and each of the sixth division layer rows may include a plurality of sixth division layers910spaced apart from each other in the second direction D2. Additionally, the sixth division layer array may include a plurality of sixth division layer columns spaced apart from each other in the second direction D2, and each of the sixth division layer columns may include a plurality of sixth division layers910spaced apart from each other in the fourth direction D4.

The seventh division layer620may extend through the fifth insulation interlayer610, and some of the second insulation patterns465and the second gate electrodes.

The seventh division layer620may extend in the third direction D3in the first and second regions I and II of the second substrate400, and for example, may extend through ones of the second gate electrodes at two upper levels, respectively. Thus, each of the ones of the second gate electrodes at the two upper levels may be divided in the second direction D2by the seventh division layer620. In an example embodiment, the seventh division layer620may extend through an upper portion of some of the second memory channel structures600.

The fourth blocking pattern695may cover upper and lower surfaces and a portion of a sidewall facing the second memory channel structure600of each of the third to fifth gate electrodes702,704and706. The fourth blocking pattern695may include a metal oxide, e.g., aluminum oxide or hafnium oxide.

The fifth insulation interlayer610may be disposed on the second substrate400, and may cover sidewalls of the second gate electrode structure and the second insulating pattern465. The sixth insulation interlayer630may be disposed on the fifth insulation interlayer610, an uppermost one of the second insulating patterns465and the second memory channel structure600. In addition, the seventh and eighth insulation interlayers720and740may be sequentially stacked on the sixth insulation interlayer630. Each of the fifth to eighth insulation interlayers610,630,720and740may include an oxide, e.g., silicon oxide.

The second and third contact plugs732and734may extend through the fifth to seventh insulating interlayers610,630and720, and may contact upper surfaces of the pads of the third to fifth gate electrodes702,704and706and the upper surface of the second substrate400in the second region II of the second substrate400. The fourth contact plug736may extend through the sixth and seventh insulation interlayers630and720, and may contact an upper surface of the second capping pattern590in the first region I of the substrate400.

FIG.17shows exemplary layouts of the second to fourth upper contact plugs732,734and736. However, embodiments of the inventive concept are not limited thereto.

The first to third wirings752,754and756may extend through the eighth insulation interlayer740, and may contact upper surfaces of the second to fourth contact plugs732,734and736, respectively. The layouts of the second to fourth contact plugs732,734and736and the first to third wirings752,754and756shown inFIG.17are an example, and embodiments of the inventive concept are not limited thereto.

In example embodiments, the third wiring756may extend in the second direction D2in the first region I of the second substrate400, and a plurality of third wirings756may be spaced apart from each other in the third direction D3. Each of the third wirings756may serve as a bit line of the vertical memory device.

The second to fourth contact plugs732,734and736and the first to third wirings752,754and756may include a conductive material, e.g., a metal, a metal nitride, a metal silicide, etc.

As described above, the sixth division layer910may extend through a portion of the second charge storage structure560and a portion of the second channel570included in the second memory channel structure600, and the second charge storage structure560and the second channel570may be divided in the fifth direction D5by the sixth division layers910at opposite sides of the memory channel structure600in the fourth direction D4.

Thus, when compared to a vertical memory device in which, for example, a single second memory channel structure600includes a single second channel570, this vertical memory device may include two second channels570at respective opposite sides of a single second memory channel structure600in the fifth direction D5, so as to have an MLC structure.

FIGS.22to35are plan views and cross-sectional views illustrating a method of manufacturing a vertical memory device in accordance with example embodiments.

For example,FIGS.22,25,28-29, and31are plan views,FIGS.23,26, and32-35are cross-sectional views taken along lines B-B′ of corresponding plan views, respectively, andFIGS.24and27are cross-sectional views taken along lines C-C′ of corresponding plan views, respectively.FIG.30is a cross-sectional view taken along line E-E′ of a corresponding plan view.FIG.29is an enlarged plan view of region Y ofFIG.28.

Referring toFIGS.22to24, a sacrificial layer structure440may be formed on a second substrate400, a second opening445may be formed by partially removing the sacrificial layer structure440to expose an upper surface of the second substrate400, and a support layer450may be formed on an upper surface of the sacrificial layer structure440and the exposed upper surface of the second substrate400.

The sacrificial layer structure440may include second to fourth sacrificial layers410,420and430sequentially stacked in the first direction D1. The second and fourth sacrificial layers410and430may each include, for example, an oxide such as silicon oxide, and the third sacrificial layer420may include, for example, a nitride such as silicon nitride.

The second opening445may be formed in various layouts in a plan view. For example, a plurality of second openings445may be spaced apart from each other in second and third directions D2and D3in the first region I of the second substrate400. Additionally, the second opening445may extend in the second direction D2or the third direction D3on a boundary between first and second regions I and II of the second substrate400. Furthermore, a plurality of second openings445, each of which may extend in the third direction D3, may be spaced apart from each other in the second direction D2in the second region II of the second substrate400.FIG.24exemplarily shows the second opening445extending in the second direction D2on the boundary between the first and second regions I and II of the second substrate400.

The support layer450may include a material having an etching selectivity with respect to the second to fourth sacrificial layers410,420and430, for example, polysilicon doped with n-type impurities. The support layer450may be conformally formed, and thus, a second recess may be formed on a portion of the support layer450in the second opening445. The portion of the support layer450in the second opening445may be referred to as a support pattern.

A second insulation layer460and a fifth sacrificial layer470may be alternately and repeatedly stacked on the support layer450in the first direction D1, and thus, a second mold layer including the second insulation layers460and the fifth sacrificial layers470may be formed. The second insulation layer460may include an oxide, e.g., silicon oxide, and the fifth sacrificial layer470may include a material having an etching selectivity with respect to the second insulation layer460, for example, a nitride such as nitride silicon.

FIGS.23and24show that the second mold layer includes the second insulation layers460and the fifth sacrificial layers470stacked at 14 levels and 13 levels, respectively. However, embodiments of the inventive concept are not limited thereto, and the second insulation layers460and the fifth sacrificial layers470may be respectively formed at more levels according to embodiments.

A photoresist layer may be formed on an uppermost one of the second insulation layers460, a photo process may be performed on the photoresist layer to form a photoresist pattern, and the uppermost one of the second insulation layers460and an uppermost one of the fifth sacrificial layers470may be etched using the photoresist pattern as an etching mask. Accordingly, a portion of one of the second insulation layers460disposed directly under the uppermost one of the fifth sacrificial layers470may be exposed. After performing a trimming process for reducing an area of the photoresist pattern, the uppermost one of the second insulation layers460, the uppermost one of the fifth sacrificial layers470, the exposed one of second insulation layers460and one of the fifth sacrificial layer470directly disposed under the exposed one of the second insulation layers460may be etched by an etching process using the reduced photoresist pattern as an etching mask.

The trimming process and the etching process may be repeatedly performed to form a second mold having a staircase shape and including a plurality of step layers each of which may include a single fifth sacrificial layer470and a single second insulation layer460sequentially stacked in the first and second regions I and II of the second substrate400. An end portion of each of the step layers in the third direction D3may be exposed without being overlapped in the first direction D1by upper step layers, which may be referred to as a “step”. In example embodiments, the steps of the second mold may be formed in the second region II of the second substrate400, and may be arranged in the third direction D3and/or the second direction D2.

In an example embodiment, an upper surface of an edge portion of the support layer450is not covered by the second mold, but rather, may be exposed.

Referring toFIGS.25to27, after forming a fifth insulating interlayer610covering the second mold, the support layer450and the sacrificial layer structure440on the second substrate400, the fifth insulating interlayer610may be planarized until an upper surface of the uppermost one of second insulation layers460included in the second mold is exposed, and thus, a sidewall of the second mold, the exposed upper surface and a sidewall of the support layer450, and a sidewall of the sacrificial layer structure440may be covered by the fifth insulating interlayer610.

A sixth hole480may be formed through the second mold, the support layer450and the sacrificial layer structure440to expose the upper surface of the second substrate400, a second charge storage layer structure may be formed on a sidewall of the sixth hole480, the upper surface of the second substrate400exposed by the sixth hole480, the uppermost one of the second insulation layers460in the second mold and the fifth insulating interlayer610, a second channel layer may be formed on the second charge storage layer structure, and a second filling layer may be formed on the second channel layer to fill the sixth hole480.

The second charge layer, the second channel layer and the second charge storage layer structure may be planarized until the upper surface of the uppermost one of the second insulation layers460in the second mold is exposed, and thus, a second filling pattern580, a second channel570and a second charge storage structure560may be formed in the sixth hole480. The second charge storage structure560may include a third blocking pattern530, a second charge storage pattern540and a second tunnel insulation pattern550sequentially stacked from the sidewall of the sixth hole480and the upper surface of the second substrate400.

Upper portions of the second channel570and the second filling pattern580may be removed to form a third recess, and a second capping pattern590may be formed to fill the third recess. The second charge storage structure560, the second channel570, the second filling pattern580and the second capping pattern590may collectively form a second memory channel structure600. In example embodiments, a plurality of second memory channel structures600may be spaced apart from each other in the second and third directions D2and D3in the first region I of the second substrate400to define a second memory channel structure array.

The second memory channel structure array may include a plurality of second memory channel structure rows spaced apart from each other in the third direction D3, and each of the second memory channel structure rows may include a plurality of second memory channel structures600spaced apart from each other in the second direction D2. Additionally, the second memory channel structure array may include a plurality of second memory channel structure columns spaced apart from each other in the second direction D2, and each of the second memory channel structure columns may include a plurality of second memory channel structures600spaced apart from each other in the fourth direction D4.

In an example embodiment, each of the second memory channel structures600may have a width gradually decreasing from an upper portion toward a lower portion thereof.

Referring toFIGS.28to30, processes substantially the same as or similar to those ofFIG.11may be performed, so that a seventh hole900may be formed to extend through a portion of the second mold between neighboring ones of the second memory channel structures600in the fourth direction D4in each of the second memory channel structure columns, and the second charge storage structure560and the second channel570in each of the second memory channel structures600in the first region I of the second substrate400.

Accordingly, a single second memory channel structure600in the vertical memory device may include two second charge storage structures560divided in the fifth direction D5and two second channels570divided in the fifth direction D5.

In example embodiments, a plurality of seventh holes900may be spaced apart from each other in the fourth direction D4to form a seventh hole column, and a plurality of seventh hole columns may be spaced apart from each other in two directions D2to define a seventh hole array.

In example embodiments, the seventh hole900may have a shape of, e.g., a circle, an ellipse, a polygon, a polygon with rounded vertices, etc., in a plan view.

A sixth division layer910may be formed to fill the seventh hole900on the second substrate400. The sixth division layer910may contact sidewalls of the second filling pattern580and the second capping pattern590.

As the seventh holes900, in which the sixth division layers910are respectively formed, define the seventh hole array, the sixth division layers910may also define a sixth division layer array.

The sixth division array may include a plurality of sixth division layer rows spaced apart from each other in the third direction D3, and each of the sixth division layer rows may include a plurality of sixth division layers910spaced apart from each other in the third direction D3. Additionally, the sixth division layer array may include a plurality of sixth division layer columns spaced apart from each other in the second direction D2, and each of the sixth division layer columns may include a plurality of sixth division layers910spaced apart from each other in the fourth direction D4.

Referring toFIG.31, portions of the fifth insulating interlayer610, the second insulation layers460and the fifth sacrificial layers470may be etched to form a third opening extending therethrough in the third direction D3, and a seventh division layer620may be formed to fill the third opening.

The seventh division layer620may extend in the third direction D3in the first and second regions I and II of the second substrate400, and may extend through, for example, upper two step layers included in the second mold. Thus, the fifth sacrificial layers470at the upper two step layers included in the second mold may be divided from each other in the second direction D2by the seventh division layer620. In an example embodiment, the seventh division layer620may extend through a portion of some of the second memory channel structures600.

Referring toFIG.32, after forming a sixth insulating interlayer630on the fifth insulating interlayer610and the seventh division layer620, a fourth opening640may be formed through the fifth and sixth insulating interlayers610and630and the second mold on the second substrate400by, for example, a dry etching process.

The dry etching process may be performed until the fourth opening640exposes an upper surface of the support layer450or the support pattern, and further, may extend through an upper portion of the support layer450or the support pattern. In example embodiments, the fourth opening640may extend in the third direction D3in the first and second regions I and II of the second substrate400, and a plurality of fourth openings640may be spaced apart from each other in the second direction D2. As the fourth opening640is formed, the second insulation layer460in the second mold may be divided into a plurality of second insulation patterns465, each of which may extend in the third direction D3, and the fifth sacrificial layer470may be divided into a plurality of fifth sacrificial patterns475, each of which may extend in the third direction D3.

After forming a spacer layer on a sidewall of the fourth opening640and an upper surface of the sixth insulating interlayer630, a portion of the spacer layer on a bottom of the fourth opening640may be removed by an anisotropic etching process to form a spacer650. Thus, upper surfaces of the support layer450and the support pattern may be partially exposed.

Portions of the exposed support layer450and the support pattern and a portion of the sacrificial layer structure440thereunder may be removed to enlarge the fourth opening640downwardly. Accordingly, the fourth opening640may expose the upper surface of the second substrate400, and further, may extend through an upper portion of the second substrate400.

In example embodiments, the spacer650may include, e.g., an undoped amorphous silicon or undoped polysilicon.

In an example embodiment, when the sacrificial layer structure440is partially removed, a sidewall of the fourth opening640may be covered by the spacer650, so that the second insulation pattern465and the fifth sacrificial pattern475in the second mold are not removed.

Referring toFIG.33, the sacrificial layer structure440may be removed through the fourth opening640by, for example, a wet etching process, and thus, a second gap660may be formed.

In example embodiments, the wet etching process may be performed using, for example, hydrofluoric acid (HF) and/or phosphoric acid (H3PO4).

As the second gap660is formed, a lower portion of the support layer450disposed adjacent to the fourth opening640and the upper portion of the second substrate400may be exposed. In addition, a portion of a sidewall of the second charge storage structure560may be exposed by the second gap660, and the exposed lateral portion of the second charge storage structure560may also be removed by the wet etching process to expose an outer sidewall of the channel570. Thus, the second charge storage structure560may be separated into an upper portion, which may extend through the second mold to cover most of the outer sidewall of the second channel570, and a lower portion, which may be formed on the upper surface of the second substrate400and cover a bottom surface of the second channel570.

In an example embodiment, during the formation of the second gap660by the wet etching process, the support layer450and the support pattern are not removed, and thus, the second mold does not collapse.

Referring toFIG.34, the spacer650may be removed, a channel connection layer may be formed on the sidewall of the fourth opening640and in the second gap660, and a portion of the channel connection layer in the fourth opening640may be removed by, e.g., an etch-back process to form a channel connection pattern670in the second gap660.

As the channel connection pattern670is formed, ones of the second channels570between ones of the fourth openings640disposed adjacent to each other in the second direction D2in the first region I of the second substrate400may be connected to each other.

In some embodiments, a second air gap680may be formed in the channel connection pattern670.

Referring toFIG.35, the fifth sacrificial patterns475exposed by the fourth opening640may be removed to form third gaps between the second insulation patterns465at respective levels, and a portion of an outer sidewall of the third blocking pattern530may be exposed by each of the third gaps.

In example embodiments, the fifth sacrificial patterns475may be removed by a wet etching process using phosphoric acid (H3PO4) or sulfuric acid (H2SO4).

A fourth blocking layer690may be formed on the exposed outer sidewall of the third blocking pattern530, inner walls of the third gaps, surfaces of the second insulation patterns465, a sidewall and a portion of a bottom surface of the support layer450, a sidewall of the support pattern, a sidewall of the channel connection pattern670, the upper surface of the second substrate400and the upper surface of the sixth insulating interlayer630, and a second gate electrode layer may be formed on the fourth blocking layer690.

The second gate electrode layer may include a second gate conductive layer and a second gate barrier layer covering upper and lower surfaces and a portion of sidewall of the second gate conductive layer.

The second gate electrode layer may be partially removed to form a second gate electrode in each of the third gaps. In example embodiments, the second gate electrode may extend in the third direction D3, and a plurality of second gate electrodes may be stacked in a plurality of levels, respectively, spaced apart from each other in the first direction D1to form a second gate electrode structure. The second gate electrodes may be stacked in a staircase shape in which an extension length in the second direction D2decreases from a lowermost level to an uppermost level in a stepwise manner. Additionally, a plurality of second gate electrode structures may be spaced apart from each other in the second direction D2by the fourth opening640.

The second gate electrode structure may include third to fifth gate electrodes702,704and706sequentially stacked in the first direction D1.

Referring back toFIGS.17to21, after forming an eighth division layer710to sufficiently fill a remaining portion of the fourth opening640on the fourth blocking layer690, the eighth division layer710may be planarized until the upper surface of the sixth insulating interlayer630is exposed. During the planarization process, a portion of the fourth blocking layer690disposed on the upper surface of the sixth insulating interlayer630may be removed, and a remaining portion of the fourth blocking layer690may form a fourth blocking pattern695.

The eighth division layer710may extend in the third direction D3in the first and second regions I and II of the second substrate400, and a plurality of eight division layers may be spaced apart from each other in the second direction D2.

A seventh insulating interlayer720may be formed on the sixth insulating interlayer630, the eighth division layer710and the fourth blocking pattern695. Second contact plugs732extending through the fifth to seventh insulating interlayers610,630and720, the second insulation pattern465and the fourth blocking pattern695to contact a corresponding one of the third to fifth gate electrodes702,704and706, a third contact plug734extending through the fifth to seventh insulating interlayers610,630and720to contact the upper surface of the second substrate400, and fourth contact plugs736extending through the sixth and seventh insulating interlayers630and720to contact a corresponding one of the second capping patterns590may be formed. In example embodiments, each of the second to fourth contact plugs732,734and736may have a width that gradually decreases from a top to a bottom thereof.

After forming an eighth insulating interlayer740on the seventh insulating interlayer720, first to third wirings752,754and756may be formed through the eighth insulating interlayer740to contact the second to fourth contact plugs732,734and736, respectively. The layouts of the second to fourth contact plugs732,734and736and the first to third wirings752,754and756shown inFIG.17are an example, and example embodiments of the inventive concept are not limited thereto.

In example embodiments, the third wiring756may extend in the second direction D2in the first region I of the second substrate400, and a plurality of third wirings756may be spaced apart from each other in the third direction D3. Each of the third wirings756may serve as a bit line of the vertical memory device.

The vertical memory device may be manufactured by performing the above processes.