Dynamic logic circuit with device to prevent contention between pull-up and pull-down device

A circuit including is disclosed. The circuit includes a precharge circuit configured to pull a dynamic node toward a voltage present on the voltage supply node during a precharge phase, and an evaluation circuit configured to, during an evaluation phase, pull the dynamic node toward a ground voltage responsive to a first input condition and configured to inhibit pulling of the dynamic node down responsive to a second input condition. A pull-up circuit coupled between the first dynamic node and the voltage supply node includes first and second pull-up transistors. The first pull-up transistor is configured to activate responsive to the precharge phase. The second pull-up transistor is configured to activate at a delay time subsequent to entry of the evaluation phase. When the first and second pull-up transistors are active, a pull-up path is provided between the dynamic node and the voltage supply node.

BACKGROUND

1. Field of the Invention

This invention relates to electronic circuits, and more particularly, to dynamic logic circuits.

2. Description of the Related Art

Dynamic logic circuits are well known in the electronic arts. Operation of a dynamic circuit may be divided into a precharge phase and an evaluate phase. During the precharge phase, a dynamic node may be precharged to a logic high voltage. The precharge may be accomplished by a PMOS (p-channel metal oxide semiconductor) transistor coupled between the dynamic node and a voltage supply node. During the evaluation phase, the dynamic node may either be discharged low or may be held high, depending on the input to the dynamic circuit. For example, if an NMOS (n-channel metal oxide semiconductor) transistor is coupled between the dynamic node and a ground node, the dynamic node may be pulled low during the evaluation phase if the input (i.e. the gate terminal of the NMOS transistor) is high, thus activating the NMOS device. Otherwise, if the NMOS device remains inactive during the evaluation phase (i.e. the gate terminal is low), the dynamic node may be held high. A keeper or half-keeper device may be included in the dynamic logic circuit to hold the dynamic node high if it evaluates high during the evaluation phase.

The precharge and evaluation phases in many dynamic logic circuits may be controlled by a clock signal. The precharge phase may occur during the low phase of the clock cycle, while the evaluation phase may occur during the high phase of the clock cycle. The clock signal may be provided to the gate terminal of a PMOS transistor coupled between the dynamic node and the voltage supply node. Thus, when the gate terminal is low (due to the clock low), the PMOS transistor will turn on and precharge the dynamic node. When the clock transitions high, the PMOS transistor will turn off, thus enabling the evaluation phase to begin.

SUMMARY OF THE DISCLOSURE

A circuit including a dynamic logic circuit is disclosed. In one embodiment, the circuit includes a precharge circuit configured to, during a precharge phase, pull a dynamic node toward a voltage present on the voltage supply node. The circuit further includes an evaluation circuit configured to, during an evaluation phase, pull the dynamic node toward a ground voltage responsive to a first input condition, and further configured to inhibit pulling of the dynamic node toward the ground voltage responsive to a second input condition. A pull-up circuit is coupled between the first dynamic node and the voltage supply node, and includes first and second pull-up transistors. The first pull-up transistor is configured to activate responsive to the precharge phase. The second pull-up transistor is configured to activate at a delay time subsequent to entry of the evaluation phase. When the first and second pull-up transistors are active, a pull-up path is provided between the dynamic node and the voltage supply node.

In one embodiment, a method for operating a dynamic logic circuit includes precharging a dynamic node of a dynamic circuit to a first logic value during a first phase of a clock signal, and activating, responsive to said precharging, a first device of a pull-up circuit coupled between the dynamic node and a voltage supply node. The method further includes ending the precharge phase and beginning an evaluation phase responsive to the clock signal transitioning from the first phase to a second phase and providing an input signal to an evaluation circuit coupled to the dynamic node. A logic value on the dynamic node is evaluated responsive to providing the input signal. A second device of the pull-up circuit is activated at a predetermined delay time subsequent to beginning the evaluation phase.

DETAILED DESCRIPTION

Dynamic Logic Circuit

Turning now toFIG. 1, a schematic diagram illustrating one embodiment of a dynamic logic circuit is shown. In the embodiment shown, dynamic logic circuit10is coupled to input circuit11and a programmable delay unit15. Input circuit11in this embodiment is an NMOS (n-channel metal oxide semiconductor) transistor, N1, although numerous other embodiments of an input circuit are possible and contemplated. Transistor N1is coupled between the dynamic node and a ground terminal (at a ground voltage) in this example. When active, transistor N1may provide a pull-down path between the dynamic node and the ground terminal.

A precharge circuit in the embodiment shown is implemented by transistor P1, which is coupled between the dynamic node and a voltage supply node (Vdd). A gate terminal of transistor P1is coupled to receive a clock signal (‘clk’). When the clock signal is low, transistor P1may activate, thereby pulling the dynamic node up towards the supply voltage. When the clock signal transitions high, transistor P1may deactivate, thus ending the precharge. The transitioning of the clock signal from low to high in this embodiment also indicates the beginning of the evaluation phase of dynamic logic circuit10.

A pull-up circuit in this embodiment is implemented with transistors P2and P3. Transistor P2may be activated when the dynamic node is pulled high during the precharge operation. A gate terminal of transistor P2is coupled to the output of inverter I1, which has an input coupled to the dynamic node. Accordingly, when the dynamic node is precharged high, inverter I1outputs a low, thereby causing activation of transistor P2.

Transistor P3in the embodiment shown may be activated responsive to a signal received from programmable delay unit15. More particularly, transistor P3is configured to be activated when programmable delay unit15asserts a logic low on its gate terminal. In this embodiment, programmable delay unit15is coupled to receive the clock signal, and is configured to assert the signal on the gate terminal of transistor P3at a predetermined delay time following the beginning of the evaluation phase. Since P3is a PMOS (p-channel metal oxide semiconductor) transistor in the embodiment shown, the signal asserted by programmable delay unit15is active low.

The use of transistor P3in the embodiment shown may eliminate contention issues between the pull-up circuit and the pull-down circuit of evaluation circuit11. In this embodiment, transistor N1is activated responsive to a logic high received on its gate terminal (‘In’). When transistor N1is active, the dynamic node may be pulled low. The pulling low of the dynamic node may in turn cause the deactivation of transistor P2, since inverter I1may respond to the low on the dynamic node by outputting a logic high. The high output from inverter I1may be slightly delayed relative to when the dynamic node is pulled low, and thus for at least a brief period, both N1and P2may be active. However, if transistor P3is off for a sufficient time while transistor N1is pulling the dynamic node low, contention between transistors N1and P2may be prevented.

In contrast, an embodiment wherein transistor P2was directly coupled to the dynamic node (i.e. where P3is not present), contention may arise between N1and P2during the evaluation phase when transistor N1is active. Furthermore, if the drive strengths of N1and P2were not balanced correctly, a situation could arise where N1lacks sufficient strength to overdrive P2and pull the dynamic node low. This in turn could cause erroneous operation of the circuit, as it would be unable to evaluate the dynamic node to a logic low. However, these contention issues may be prevented in the embodiment shown inFIG. 1by providing transistor P3and holding it inactive for the delay time subsequent to entering the evaluation phase. If the input signal is such that the dynamic node should evaluate low, transistor N1may be allowed sufficient time to pull the dynamic node low and cause transistor P2to deactivate before transistor P3is turned on.

If, during the evaluation phase, the input signal to evaluation circuit11(i.e., ‘In’ coupled to the gate of transistor N1) is low, the dynamic node may evaluate high. A low input to the gate of N1may cause this device to be inactive. Since the dynamic node is precharged during the precharge phase, the node may remain high during the evaluation phase when transistor N1remains inactive. However, even when inactive, transistor N1may be subject to leakage currents that could cause the voltage level on the dynamic node to degrade if the node is not otherwise pulled high. Such leakage problems may be exacerbated in embodiments in which a number of evaluation circuits share a common dynamic node, as will be discussed in further detail below. However, activation of transistor P3after the delay time has elapsed may provide a pull-up path between the dynamic node and Vdd, which may in turn guarantee the high on the dynamic node. As previously noted, transistor P2may activate during the precharge phase responsive to inverter I1driving a low on its gate (which may occur in turn due to the high on the input of I1). If transistor P3is turned on before leakage as pulled the voltage on the dynamic node sufficiently low, the pull-up path from the dynamic node and Vdd may be restored.

Setting the delay provided by programmable delay unit15may thus be a balancing act between providing a sufficient amount of time to enable transistor N1to pull the dynamic node low without contention while also activating transistor P3in time to prevent leakage currents from causing a logic high to degrade into a logic low. This delay may be tuned during a final testing phase of an integrated circuit (IC) or other device in which the circuit is implemented, before shipping to a customer, or may be determined at other times during operation of the IC (e.g., during a boot-up phase). Testing may be conducted to find a range of values which satisfies the requirements of enabling contention free operation while also activating transistor P3fast enough to prevent leakage from causing an erroneous value to appear on the dynamic node. After determining such a range of values, programmable delay unit15may receive information through a delay control input which sets the delay. In some embodiments, the delay time may be set once and may remain as the permanent delay for the life of the circuit. In other embodiments, the delay time may be adjustable at times subsequent to its initial setting to allow for changing operating conditions or degradation that may occur over the lifetime of the circuit. For example, embodiments are possible and contemplated wherein programmable delay unit15provides a first delay time when operating in a high performance mode (e.g., with a high clock frequency) and a second delay time when operating in a low power mode (e.g., with a clock frequency lower than that uses in the high performance mode).

FIG. 2is a timing diagram illustrating the operation of one embodiment of a dynamic logic circuit. More particularly,FIG. 2illustrates the operation of the embodiment of dynamic logic circuit10shown inFIG. 1, although this timing diagram is exemplary and may apply to other embodiments as well. In the example shown, the clock signal is provided to the gate of transistor P1. Since P1is a PMOS transistor, the low on its gate may cause it to activate. The dynamic node may be pulled high when transistor P1is active. The precharge phase ends when the clock signal transitions high (thereby deactivating P1), however, the dynamic node may remain high since N1remains off at the rising clock edge in this example.

Subsequent to the rising edge of the clock signal, an input signal ‘In’ is received on the gate terminal of N1. When transistor N1becomes active, a pull-down path is provided between the dynamic node and the ground node. At the point where N1becomes active in this example, transistor P3is off since its gate terminal is high. Accordingly, the pull-up path through transistor P2and P3is blocked while the pull-down path is active at this point in the operation, thereby causing the dynamic node to be pulled low. The pulling of the dynamic node low may be accomplished without contention between transistor N2and transistor P2, since the pull-up path is blocked when P3is turned off. Furthermore, as the dynamic node falls low, the gate terminal of transistor P2will be driven high (from the output of inverter I1), and thus transistor P2is turned off.

At a predetermined delay time after the clock transitions from low to high, the programmable delay unit15may assert an active low signal to the gate of transistor P3. However, since transistor P2has already been turned off in this example, no pull-up path is provided between the dynamic node and the voltage supply node. Accordingly, the dynamic node remains low at this point in the example, since transistor N1is active and thus provides the pull-down path. The programmable delay unit15may be configured to de-assert the active low signal to the gate of transistor P3responsive to the clock signal transitioning low again, and before or concurrent with the activation of transistor P2that results from the precharge operation.

The cycle described above repeats itself in a second cycle in the example presented inFIG. 2. However, in a third cycle of this example, the input to the gate terminal of transistor N1remains low during the evaluation phase. Accordingly, transistor N1remains turned off, and the dynamic node should evaluate to a logic high during the evaluation phase. Transistor P2may also remain active as a result of inverter I1continuing to drive a low on its gate terminal. However, even though transistor N1is off, the it may still be subject to leakage currents, which can, without the presence of a pull-up path, degrade the voltage on the dynamic node that originally resulted from the precharge. This is shown by the droop in the dynamic node voltage shown in this example. Since transistors N1and P3are both off at this point in the example, the dynamic node may float, and the voltage thereon may degrade due to leakage as described above. Once the delay time has elapsed and the programmable delay unit15asserts the active low signal on the gate terminal of transistor P3, the pull-up path may be provided through transistors P2and P3. Thus, the dynamic node may be pulled high and thus counteract the leakage that may occur through transistor N1and reinforce the evaluated logic high.

Memory Cell and Memory Array with Dynamic Logic Circuits:

FIG. 3is a schematic diagram illustrating one embodiment of a memory cell coupled to a dynamic logic circuit. In the embodiment shown, memory cell20is coupled to dynamic logic circuit10. Thus, in this example, memory cell20plays the role of an evaluation circuit from which a logic input is provided to dynamic circuit10, with the read bit line (‘rbl’) coupled to memory cell20serving as the dynamic node of dynamic circuit10. The dynamic logic circuit10in the embodiment shown may function in a similar manner as described above for the embodiment shown inFIG. 1. More particularly, dynamic logic circuit10may precharge the read bit line when the clock signal is low. If a read operation is conducted when the clock is high, the dynamic node may be evaluated according to a logic value provided from memory cell20. If no read operation is performed when the clock signal is high, the read bit line may remain high. Furthermore, the programmable delay unit15may assert an active low signal to the gate of transistor P3during the high portion of the clock signal, which may provide a pull-up path between the dynamic node and Vdd if transistor P2is also active.

Memory cell20in this embodiment includes a keeper having two cross-coupled inverters, I2and I3. Inverter I2includes transistors P4and N3, while inverter I3includes transistors P5and N2. Transistors N4and N5are gating transistors in this embodiment and thus are activated during a write to enable true and complementary values to be written into memory cell29from true (‘wbl’) and complementary (‘wbl_x’) write bit lines, respectively. Transistors N4and N5are NMOS transistors in this embodiment, and may be activated responsive to a logic high on the write word line (‘ww1’) coupled to each of their respective gate terminals. When transistors N4and N5are turned on, a logic value present on the true write bit line may be conveyed to a true storage node (‘st’), while the complementary logic value may be conveyed from the complementary write bit line may be conveyed to a complementary storage node (‘st_x’). When transistors N4and N5are turned off (i.e., when the write word line is low in this embodiment), the true and complementary storage nodes are isolated from the true and complementary write word lines.

Read operations in the embodiment shown may be performed responsive to assertion of a logic high on a read word line (‘rwl’). Transistor N7may activate responsive to a logic high asserted on the read word line. The logic value to which the dynamic node evaluates to during a read operation that occurs within the evaluation phase may then depend on the state of the complementary storage node, st_x. If a logic high is stored on the complementary storage node, transistor N6may be active, and thus the read bit line may be pulled low (through transistors N6and N7) during the read operation. If a logic high is stored on the complementary node, transistor N6may be inactive, and thus the read bit line may remain high during the read operation.

The embodiment of memory cell20shown inFIG. 3may be one of a number of different types of memory cells that may be coupled to an embodiment of a dynamic logic circuit such as dynamic circuit10. Such memory cells may include a greater or lesser number of transistors, and may be arranged in a number of different ways.

Memory cell20may be one of a number of memory cells coupled to a single read bit line.FIG. 4is a block diagram illustration a portion of one embodiment of a memory100having dynamic circuits10coupled to respective bit lines. Each of the dynamic circuit10in the embodiment shown is coupled to a programmable delay unit15, and may thus may activate a transistor corresponding to P3as discussed above at a delay time subsequent to commencing an evaluation phase. The delay provided by programmable delay unit may be common to all of the dynamic logic circuits10in one embodiment, but may be individually set for different ones of the dynamic logic circuits10in other embodiments.

For the sake of simplicity, the write bit lines and write word lines are not shown inFIG. 4, although these elements may be present for each memory cell in an arrangement according to that shown inFIG. 3, or in any other suitable arrangement. Furthermore,FIG. 4shows only a portion of the total number of memory cells present in memory100. It is also noted that memory100shown inFIG. 4is exemplary, and that numerous other embodiments are possible and contemplated. Such embodiments may have a greater or lesser number of cells, larger or smaller word widths, and a greater or lesser number of words. The embodiment shown may also represent one bank of an embodiment including multiple memory banks.

In the embodiment shown, memory100includes a number of memory cells coupled to each coupled to a corresponding one of a number of read bit lines (rbl0, rbl1, etc.). Each read bit line may serve as the dynamic node for the respective dynamic logic circuit10coupled thereto. Each of the memory cells20is also coupled to a corresponding one of a number of read word lines (rwl0, rwl1, etc.). A group of memory cells20comprising a word may be selected for a read by the assertion a corresponding read word line. For example, if a logic high is asserted on rwl0, each memory cell20coupled thereto may be selected for a read, and may cause its corresponding read bit line to evaluate to a certain logic value based on a logic value stored therein. Each dynamic logic circuit10in the embodiment shown also includes a respective output node (DN0, DN1, etc) upon which the data read from the memory may be conveyed. This node may be the same node as the dynamic node in some embodiments, or may be a different node in other embodiments, particularly those where the portion of memory100shown is one of a bank of memory from which a read may be conducted.

Since the read bit lines in the embodiment shown serve as dynamic nodes for the dynamic logic circuits10, having a number of memory cells20coupled thereto may provide a greater number of paths for potential leakage. Accordingly, the setting of the timing for the assertion of the delay signal by programmable delay unit15may take into account the amount of leakage that may result from the multiple cells coupled to each read bit line, while also taking into account the contention issues discussed above.

Dynamic Logic Circuit Having Multiple Dynamic Nodes:

FIG. 5is a block diagram illustrating an embodiment of a circuit including a dynamic circuit having multiple dynamic nodes and multiple evaluation circuits coupled to each dynamic node. In this particular embodiment, dynamic logic circuit30includes a first dynamic node (Dynamic Node L, on the left portion of the drawing) and a second dynamic node (Dynamic Node R, right portion of the drawing). Each of a first plurality of N evaluate circuits11are coupled to the first dynamic node, while each of a plurality of a second plurality of N evaluate circuits11are coupled to the second dynamic node. The number of evaluate circuits N coupled to each dynamic node is an integer value and may vary from one embodiment to the next. The evaluate circuits11may be memory cells or other types of circuits. The input signals to the (InL0, InR0, etc.) may select a particular one of the evaluate circuits11to provide an output signal, while the other evaluate circuits may be inhibited (e.g., tri-stated) from providing a signal onto their respective dynamic node. Thus, the circuit shown inFIG. 5may be arranged as a one-hot multiplexer structure, wherein only one evaluation circuit11may provide a signal to a dynamic node at a given time.

Dynamic logic circuit30in this embodiment is configured to precharge the first and second dynamic nodes when the clock is low. Transistor P6and P7in this embodiment are configured to activate when the clock is low in order to precharge the first and second dynamic nodes, respectively. When both the first and second dynamic nodes are precharged, gate G1(a NAND gate in this embodiment) provides a logic low to the gate terminals of transistors P8and P10. When the clock transitions high, one of the evaluation circuits11may be selected and may cause its respective dynamic node to be evaluated to either a logic high or a logic low. In the case where an evaluation circuit11causes its respective dynamic node to evaluate to a logic low, that dynamic node may be pulled low. When either of the dynamic nodes is pulled low in this embodiment, gate G1outputs a logic high, and thus both transistors P8and P10may be deactivated. Furthermore, when gate G1outputs a logic high, transistor N8may be activated, thus causing the global bit line (‘GBL0’) to be pulled low.

If a selected one of the evaluate circuits11causes its respective dynamic node to evaluate to a logic high, gate G1may continue to output a logic low. Both transistors P8and P10may thus remain activated, while transistor N8is inactive. Accordingly, a logic high may be output on the global bit line. Additional circuitry to pull up and enforce a logic high on the global bit line may be included in some embodiments, such as the optional transistor P12(shown in dashed lines) that may become active responsive to a low output by gate G1. In other embodiments, other types of circuitry (e.g., a pull-up resistor) may cause a logic high to be present on the global bit line when transistors N1is inactive. Furthermore, the global bit line may also be subject to a precharge in the same manner as the dynamic nodes in some embodiments, and may be coupled to other circuitry (e.g., a flip-flop) in order to synchronize its output.

Programmable delay unit15may drive an active low signal to each of transistors P7and P9at a delay time subsequent to beginning the evaluation phase. The delay time may be set to allow a sufficient amount of time for either of the dynamic nodes to be pulled low by an evaluation circuit11according to a corresponding condition while also ensuring that transistors P8and P10are de-activated. Thus, if a selected one of the evaluate circuits11causes its respective dynamic node to evaluate to a logic low, that dynamic node may be pulled low, causing gate G1to output a high (responsive to the low input) and therefore deactivate transistors P8and P10. Programmable delay unit15may assert the active low signal at a delay time concurrent with or subsequent to the deactivation of transistors P8and P10.

The delay time may also be set to reinforce a logic high evaluated on a dynamic node associated with a selected one of the evaluate circuits11, by providing a pull-up path. As previously noted, when both dynamic nodes are high, gate G1may output a low and thus cause transistors P8and P10to be active. However, leakage currents in the evaluate circuits11may also cause a logic high voltage to degrade toward a logic low without any intervention. If transistors P7and P9are activated when transistors P8and P10are active, pull-up paths to Vdd are provided for both dynamic nodes. Accordingly, the delay time set by programmable delay unit15may be such that transistors P7and P9are activated before an active dynamic node can, due to leakage, degrade to a logic low despite being evaluated to a logic high.

In this particular embodiment, the delay provided by programmable delay unit15is adjustable. Various inputs are provided to a multiplexer31in this embodiment to provide various delays. The range may at its low point provide no delay (‘Hold On’), to which programmable delay unit15may respond by holding the active low signals to the gate terminals of P7and P9in an asserted condition. This setting may be used if the pull-down devices in the evaluate circuits11are strong, or may be used to enhance writeability in embodiments where the evaluate circuits11are memory cells. At the high point, programmable delay unit15may keep the active low signals de-asserted, causing transistors P7and P9to remain off. This setting may be used to track leakage currents of the dynamic nodes. Delay values X and Y may represent two different time delay values in which the active low signals are asserted by programmable delay unit15subsequent to entering the evaluation phase.

The example of the programmability shown in this embodiment is but one example of various methods that may be used to program the delay time at which programmable delay unit15asserts the active low signals after the evaluation phase begins. In another embodiment, the programming may be done a single time (e.g., at final manufacturing test) by blowing corresponding programming fuses. Embodiments are also possible and contemplated wherein the delay time is set during a boot-up procedure that includes a power-on self test for determining the most appropriate setting. In general, any method appropriate to a given embodiment may be used to set the delay time.

FIG. 6is a block diagram of one embodiment of an IC. IC150may be a processor for a computer system, an ASIC (application specific integrated circuit), or virtually any other type of IC in which clocked logic circuits may be implemented. In the embodiment shown, IC150includes a core logic unit155having a register file160implemented therein, an L1 (level one) cache165, and L2 (level two) cache166, a bus interface unit170, a clock generator175, and a programming unit180. One or more of the units of IC150may include an embodiment of a dynamic logic circuit10or30discussed above or variations thereof. For example, register file160may include a number of memory cells20as discussed above inFIG. 2, with each being coupled to a read bit line that serves as a dynamic node in an arrangement such as that shown inFIG. 5. L1 cache165and L2 cache166may also be similarly arranged. Bus interface unit170may also include dynamic logic circuits in various embodiments that may include those described herein.

Clock generator175in the embodiment shown may be a phase locked loop (PLL) or other type of clock generating circuitry. One or more clock signals may be provided by clock generator175to each of the various units of IC150. These clock signals may be provided to the dynamic logic circuits within IC150, and may control the precharge and evaluation phases of these circuits.

Programming unit180may provide programming information to one or more programmable delay units15that are associated with various ones of the dynamic logic circuits of IC150. In one embodiment, programming unit180may be implemented using fuses that are blown to program the delay times to provide an implementation that is one-time programmable. In another embodiment, programming unit180may be a type of non-volatile memory (e.g., a flash memory, a read-only memory, or other type) which stores the information for programming the delays, and may be updatable to respond to new operating conditions. In addition, programming unit180may store different programming information for different programmable delay units within IC150so that the delay time for each dynamic circuit is set in a manner appropriate for local conditions.

Turning now toFIG. 7, a flow diagram of one embodiment of a method for operating a dynamic logic circuit is shown. In the embodiment shown, method200begins with the precharging of a dynamic node of the dynamic logic circuit (block205). The precharge may be accomplished during a first phase of a clock signal (e.g., when the clock is low) by pulling the dynamic node high through a pull-up path activated responsive to the first clock phase (e.g., through a PMOS transistor coupled between the dynamic node and a supply voltage node).

After the precharge phase ends, and evaluation phase may begin (block210). The precharge phase may end in one embodiment when the clock signal transitions from its first phase (e.g., clock low) to its second phase (e.g., clock high). A transition of the clock from a low to a high may turn off a PMOS transistor or other type of circuit providing a pull-up path between the dynamic node and the supply voltage node for the purposes of conducting the precharge.

Subsequent to the entering of the evaluation phase, an input signal may be provided to an evaluation circuit (block215). Responsive to the input, the evaluation circuit may evaluate the dynamic node to either a logic high or a logic low (block220). The evaluation circuit may be a simple NMOS transistor (such as that shown inFIG. 1), a memory cell (such as that shown inFIG. 2), or other type of circuit capable of changing the state of the dynamic node responsive to a given input.

At a predetermined delay time subsequent to entering the evaluation phase, a second of two devices in a pull-up circuit be activated (block225). For example, transistors P2and P3shown inFIG. 1may form a pull-up circuit, with P3being the second of these two devices. The first of these two devices may be active if the dynamic node is evaluated to a logic high, and thus the activation of the second provides a pull-up path between the dynamic node and the voltage supply node. If the first of these two devices is inactive, the activation of the second device does not provide a pull-up path. However, the delayed activation of the second device may prevent contention between the first device and a pull-down circuit (e.g. an NMOS transistor) when the dynamic node is evaluated low.

Concurrent with the ending of the evaluation phase, the second device may be deactivated (block230). After the evaluation phase ends (e.g., when the clock falls low again), the precharge phase may commence for the next cycle, and the method may repeat.

While the present invention has been described with reference to particular embodiments, it will be understood that the embodiments are illustrative and that the invention scope is not so limited. Any variations, modifications, additions, and improvements to the embodiments described are possible. These variations, modifications, additions, and improvements may fall within the scope of the inventions as detailed within the following claims.