Double metal patterning

A technique relates to a semiconductor device. Mandrels are formed on a substrate, the mandrels including a first metal layer. A second metal layer is formed on the substrate adjacent to the first metal layer, the first and second metal layers being separated by spacer material.

BACKGROUND

The present invention generally relates to fabrication methods and resulting structures for semiconductor devices, and more specifically, to methods and structures using double metal double patterning for interconnects or wires.

Back-end-of-line (BEOL) is the second portion of integrated circuit (IC) fabrication where individual circuit devices such as transistors, capacitors, resistors, etc., are interconnected with wiring on the wafer. Common metals for the wiring include copper and aluminum. BEOL generally begins when the first layer of metal is deposited on the wafer. BEOL includes contacts, insulating layers (dielectrics), metal levels, and bonding sites for chip-to-package connections. Multiple patterning has been practiced for complementary metal-oxide-semiconductor (CMOS) manufacturing. Among the practical schemes for patterning wires, self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) are used to form wires.

SUMMARY

Embodiments of the invention are directed to a method for forming a semiconductor device. A non-limiting example of the method includes forming mandrels on a substrate, the mandrels including a first metal layer, and forming a second metal layer on the substrate adjacent to the first metal layer, the first and second metal layers being separated by spacer material.

Embodiments of the invention are directed to a semiconductor device. A non-limiting example of the semiconductor device includes mandrels formed on a substrate, the mandrels including a first metal layer, and a second metal layer formed on the substrate adjacent to the first metal layer, the first and second metal layers being separated by spacer material.

In the accompanying figures and following detailed description of the embodiments of the invention, the various elements illustrated in the figures are provided with two or three digit reference numbers. With minor exceptions, the leftmost digit(s) of each reference number correspond to the figure in which its element is first illustrated.

DETAILED DESCRIPTION

Turning now to an overview of technologies that are more specifically relevant to aspects of the invention, as the size of devices such as transistor, capacitors, etc., on integrated circuits become smaller, the scaling of interconnect pitch is becoming more difficult. The SADP process can be used to form interconnects but it requires many complicated steps.

Turning now to an overview of the aspects of the invention, one or more embodiments of the invention provide semiconductor devices and methods which use double metal double patterning (DMDP). According to embodiments of the invention, DMDP provides metal resistance control by allowing use of alternative metals, such as cobalt, ruthenium, nickel, etc., and employs an integration scheme that utilizes 50% fewer process operations than the state-of-the-art the self-aligned double patterning (SADP) scheme. For example, DMDP can pattern two different metals with less process steps and less etching steps than the state-of-the-art SADP because one of the metals serves the function of a mandrel and remains on the semiconductor device according to embodiments of the invention. Therefore, the fabrication processes of forming sacrificial mandrels and later removing the sacrificial mandrels are not required for embodiments of the invention.

Turning now to a more detailed description of aspects of the present invention,FIG. 1depicts an isometric view of a semiconductor device100according to embodiments of the invention. After initial fabrication operations, the semiconductor device100includes a layer104formed on a substrate102. The substrate102is formed of semiconductor material. The substrate102can be a silicon (Si), silicon germanium, III-V materials, etc., although other materials can be used. The layer104can include dielectric materials such as oxide materials, nitride materials, etc. A first metal layer106is formed on the prior level/layer104. In one or more embodiments of the invention, the prior level/layer104might be omitted and the first metal layer106can be formed on the substrate102. Example materials of the first metal layer106can include alternative metals such as cobalt, ruthenium, nickel, tungsten, platinum, etc. Other example materials of the first metal layer106can include tungsten, copper, aluminum, gold, silver, etc. A hard mask layer108is formed on the first metal layer106. The hard mask layer108can include oxide materials and nitride materials. Standard lithography techniques can be implemented in the fabrication process of the semiconductor device100.

FIG. 2depicts an isometric view of the semiconductor device100according to embodiments of the invention. Mandrel patterning is performed. Etching can be performed to pattern the hard mask layer108, and the pattern of the hard mask layer108is etched into the first metal layer106, thereby forming mandrels202. Reactive ion etching (ME) or other etching can be used to form the mandrels202. The first metal layer106itself becomes the mandrels202without having to separately form mandrels from non-metal materials. Additionally, the mandrels202which are the patterned material of the first metal layer106remain (i.e., are not etched away) and become metal wires that are used as interconnects. Main etch chemistries are Cl2/BCl2for aluminum, ruthenium, titanium and SF6for tungsten, for example.

FIG. 3depicts an isometric view of the semiconductor device100according to embodiments of the invention. A spacer material302is formed on the semiconductor device100. The spacer material302can be deposited using various deposition techniques including atomic layer deposition, spin-on dielectrics, etc. The spacer material302can include dielectric materials such as oxide materials and nitride materials. Also, example materials of the spacer material302can include carbon-based materials such as graphene, carbon nanotubes, and fullerenes which can be referred to as nanocarbons. Other carbon-based materials can include silicon boron carbide nitride (SiBCN), silicon oxycarbide (SiOC), silicon carbon nitride (SiCN), silicon oxygen carbon nitride (SiOCN), etc. Carbon material is chosen to provide enough etch selectivity for the downstream process when it will be etched over layer104inFIGS. 6A, 6B, and 6C. Further, the spacer material302has sufficient thickness such that the spacer material302provides physical and electrical separation between adjacent metal wires, as discussed further below.

FIG. 4depicts an isometric view of the semiconductor device100according to embodiments of the invention. Backfill deposition and etch back are performed. For example, a fill material402is deposited and etch back is performed stopping on the spacer material302. The fill material402can be formed as spin-on-glass (SOG), which is an interlayer dielectric material applied in liquid form to fill narrow gaps and thus conducive to planarization.

FIG. 5Adepicts an isometric view of the semiconductor device100according to embodiments of the invention.FIG. 5Bdepicts a side view of the semiconductor device100inFIG. 5Aaccording to embodiments of the invention.FIG. 5Cdepicts a top view of the semiconductor device100inFIG. 5Aaccording to embodiments of the invention. Non-mandrel lithography is performed. In the state-of-the-art, sacrificial mandrels are used as placeholders to form subsequent features having a desired shape, and the sacrificial mandrels are then removed. Embodiments of the invention do not require removal of the mandrels202in which the patterned first metal layer106is and/or functions as the mandrel. Accordingly, embodiments of the invention employ a non-mandrel process because the mandrels202are not the sacrificial mandrels used in the state-of-the-art. A block mask502is deposited and patterned using standard lithography. The block mask502can include an organic planarization layer (OPL). Optionally, the block mask502can include an anti-reflective coating (ARC) layer formed on the OPL layer. A trench504is formed in the block mask502. The trench504exposes a portion of the fill material402and spacer material302. In some examples, the top surfaces of the spacer material302might not be exposed in the trench504. The trench504is formed in preparation to deposit metal for metal wires. It is noted that in the conventional SADP integration, non-mandrel area is always a dependent upon having the conventional sacrificial mandrel present. There is no need and no way to perform the non-mandrel lithography discussed in embodiments of the invention, because there is nothing in the non-mandrel area in the state-of-the-art. However, in this DMDP integration according to embodiments of the invention, non-mandrel lithography is possible because of the back fill material402in the non-mandrel area. This enables the ability to define the shape of non-mandrel features, which include the features other than the patterned material of the first metal layer106, because the patterned first metal layer106is or acts as the mandrel.

FIG. 6Adepicts an isometric view of the semiconductor device100according to embodiments of the invention.FIG. 6Bdepicts a side view of the semiconductor device100inFIG. 6Aaccording to embodiments of the invention.FIG. 6Cdepicts a top view of the semiconductor device100inFIG. 6Aaccording to embodiments of the invention. Spacer etch is performed to etch the exposed fill material402and the spacer material302immediately under the removed backfill material402. Reactive ion etching (ME) can be performed. As mentioned above, the spacer material302is a carbon-based material which gives it an etch selective to the back fill material304, an SOG material. In addition, the non-mandrel feature size (CD) (i.e., the location where a second metal layer802will be formed inFIGS. 8A and 8Bafter removing the exposed backfill material402) is expected to be defined by the spacer material302, particularly the previous location of the removed backfill material402exposing the layer104between the spacer material302. As a result, the back fill material402is designated to be etched away in preparation for deposition of the second metal layer802.

FIG. 7depicts an isometric view of the semiconductor device100according to embodiments of the invention. The block mask502is removed. For example, the OPL layer can be stripped using a plasma stripping process. Removing the OPL concurrently removes the ARC layer on top.

FIG. 8Adepicts an isometric view of the semiconductor device100according to embodiments of the invention.FIG. 8Bdepicts a side views of the semiconductor device100inFIG. 8Aaccording to embodiments of the invention. Second metal deposition is performed. A second metal layer802is deposited on the semiconductor device100using standard lithography techniques. More particularly, the second metal layer802is formed in the previous location of the removed backfill material402. As previously seen inFIGS. 6A and 6B, the trench504has an extended depth after removal of the backfill material402.

Example materials of the second metal layer802can include alternative metals such as cobalt, ruthenium, nickel, tungsten, platinum, etc. Other example materials of the second metal layer802can include copper, aluminum, gold, silver, etc. It is noted that the first metal layer106and the second metal layer802can be different materials, which correspondingly forms double metal wire lines with different materials. In this way, one wire can have different properties from another metal wire because the metal wires can be formed of different materials. In some examples, it is contemplated that the first metal layer106and the second metal layer802can be the same materials. It is noted that the first metal layer106having been patterned into mandrels remains to become one of the double metal wires, and therefore, the fabrication processes of forming and subsequently removing sacrificial mandrels are omitted.

FIG. 9Adepicts an isometric view of the semiconductor device100according to embodiments of the invention.FIG. 9Bdepicts a side view of the semiconductor device100inFIG. 9Aaccording to embodiments of the invention.FIG. 9Cdepicts a top view of the semiconductor device100inFIG. 9Aaccording to embodiments of the invention. Chemical mechanical planarization/polishing (CMP) is performed on the second metal layer802to remove excess portions of the second metal layer802, portions of space material302, and hard mask layer108. The CMP stops on the first metal layer106. As noted above, the CMP also removes the hard mask layer108on top of the first metal layer106, and therefore, the tops of the first metal layer106and second metal layer802are exposed. The first metal layer106and second metal layer802are metal wires, which are also referred to as interconnects.

The width of each of the metal wires, for first metal layer106and second metal layer802in the side view, is less than about 40 nanometers (nm). By having line widths less than 40 nm, the first metal wire layer106and the second metal wire layer802can have different wire resistances when the first metal wire layer106and second metal wire layer802are two different metals. The line widths of first metal wires/first metal wire layers106and second metal wire/second metal wire layer802are best seen in the side view. It should be appreciated that although 3 metal wires are illustrated, the semiconductor device100is not limited to 3 metal wires and can have numerous metal wires to make connections to individual circuit devices such as transistors, capacitors, resistors, etc., as understood by one skilled in the art

As an option of depositing a liner,FIG. 10depicts an isometric view of the semiconductor device100according to embodiments of the invention.FIG. 10continues from the fabrication operations inFIG. 7. A liner1002can be deposited on the top surface of the semiconductor device100. A conformal deposition technique can be used. The second metal layer802is now deposited on top of the liner1002using standard lithography techniques. Examples materials of the second metal layer802are noted above. The liner1002could be or acts as an adhesion layer, a diffusion layer, etc. The material of the optional liner1002can be different according to the material of the second metal layer802. For example, in a case where the second metal layer802is copper, the liner1002can be TiN, TaN, etc. In a case where the second metal layer802is aluminum, the liner1002can be TiN, Ta, etc. In a case where the second metal layer802is cobalt, the liner1002can be TiN. In a case where the second metal layer802is ruthenium, no liner1002is utilized.

FIG. 11Adepicts an isometric view of the semiconductor device100according to embodiments of the invention.FIG. 11Bdepicts a side view of the semiconductor device100inFIG. 11Aaccording to embodiments of the invention.FIG. 11Cdepicts a top view of the semiconductor device100inFIG. 11Aaccording to embodiments of the invention. As noted inFIGS. 9A, 9B, and 9C, CMP is performed on the second metal layer802. CMP stops on the first metal layer106. CMP also removes the hard mask layer108on top of the first metal layer106and removes portions of liner1002. Accordingly, the tops of the first metal layer106and second metal layer802are exposed. The first metal layer106and second metal layer802are metal wires, which are also referred to as interconnects.

A method of forming a semiconductor device100is provided according to embodiments of the invention. Mandrels202are formed on a substrate102, the mandrels202including a first metal layer106. A second metal layer802is formed on the substrate102adjacent to the first metal layer106, the first and second metal layers being separated by spacer material302.

A dielectric layer (e.g., layer104) is formed as an intervening layer between the substrate102and the mandrels202. A dielectric layer (e.g., layer104) is an intervening layer formed between the substrate102and the second metal layer802. The spacer material302is formed on sides of the mandrels202.

Forming the second metal layer802on the substrate102adjacent to the first metal layer106includes: forming the spacer material302on the mandrels, forming fill material402on the spacer material302, forming a trench504or pattern through the fill material402and the spacer material302, and forming the second metal layer802in the trench504or pattern.

The first metal layer106includes different material from the second metal layer802. The first metal layer106and the second metal layer802include the same material. The first metal layer is a metal wire, and the second metal layer is a metal wire. A liner layer/liner1002is an intervening layer formed between the second metal layer802and the spacer material302. A liner layer/liner1002is an intervening layer formed between the second metal layer802and the substrate102.