Method to improve source/drain parasitics in vertical devices

A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).

FIELD OF THE DISCLOSURE

The present disclosure relates generally to semiconductor fabrication processes, and more particularly to methods for making FinFET devices with improved source/drain parasitics.

BACKGROUND OF THE DISCLOSURE

As the physical dimensions of semiconductor devices continue to decrease, these ever smaller dimensions pose new challenges which must be overcome in order to make the devices functional. In the field of MOSFETs (metallic oxide semiconductor field effect transistors), the decrease in size, and the commensurate decrease in operating current, have resulted in current leakage when the transistor is in its off state. This leakage is often attributed to the formation of parasitic features which are formed in the substrate beneath the gate of the FET. Generally, such parasitic features create alternate and undesirable pathways for current flow. These parasitic features may be caused by imperfections or physical limitations inherent in the fabrication process. In conventional planar CMOS technology wherein FETs are formed on a bulk substrate, parasitic features often form in the channel between the source and drain and beneath the gate at certain depths where the gate field is no longer effective.

One approach known to the art for compensating for the current leakage problem in planar FETs is through the provision of a second gate disposed beneath the channel region. In such dual gate FETs, the second gate provides a lower boundary for the channel, and also provides a second field for regulating the current flow through the channel region.

While dual gate MOSFETs have certain advantages over single gate MOSFETs, they also have some notable drawbacks. In particular, the formation of a lower gate is challenging from a fabrication standpoint, and it is also difficult to properly align the two gates with each other.

The aforementioned difficulties have led to the development of FinFETs, an example of which is depicted inFIGS. 1-2. As seen therein, a FinFET10is essentially a dual gate MOSFET in which the gates46of the device are formed vertically rather than horizontally, and in which the channel regions42are disposed within a series of vertical fins12which contain source14and drain18regions on opposing sides thereof. The FinFET10is fabricated from an SOI (semiconductor-on-oxide) wafer22which contains an SOI layer34disposed on a BOX (buried oxide) layer26which, in turn, is disposed on a semiconductor substrate30. The gate46, source14and drain18regions are formed in the SOI layer34.

After fins12have been formed, subsequent processing steps include forming a gate oxide (not shown) on fins12, and forming the gate46which is common to both fins12. After formation of the gate46, the source14and drain18regions are doped, as illustrated by arrows50, to achieve a doping profile58. Doping is typically accomplished using ion implantation from the front side of the wafer22, and typically at an angle of about 30 degrees relative to a normal from the wafer22so that ions can enter each fin12along its entire height without interference from any adjacent fin12.

As seen inFIG. 1, FinFET10avoids the problem encountered with planar CMOS devices of having to form a second gate beneath the channel of the FET. FinFET10also overcomes the problem in planar CMOS technology of having to align gates above and below the channel region. Since the fins12in a FinFET device are free-standing structures prior to the formation of the gate46, the portions of the gate46on either side of each channel42(seeFIG. 2) are largely self-aligned as a result of forming the gate46perpendicular to the fins12.

DETAILED DESCRIPTION

In one aspect, a method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate overlying a semiconductor layer, and having at least one spacer structure disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant.

In another aspect, a method for making a transistor is provided which comprises (a) providing a semiconductor substrate having a gate defined thereon, and having first and second spacer structures disposed adjacent to said gate; (b) removing a portion of the semiconductor substrate adjacent to each of the first and second spacer structures, thereby creating a mesa in the semiconductor substrate upon which the gate and the first and second spacer structures are disposed; and (c) subjecting a vertical wall of the mesa to an angled implant.

In still another aspect, a method for making a semiconductor device is provided which comprises (a) providing a FinFET structure comprising (a) raised source and drain regions, a fin-shaped channel region extending between the source and drain regions, and (c) a gate extending over the channel region; (b) etching the FinFET structure such that the height of the channel region and the source and drain regions is reduced; and (c) implanting at the source and drain regions at an angle.

Despite the aforementioned advantages of FinFETs, these devices also present certain challenges. In particular, FinFET devices often suffer from significant parasitic series resistance, of which source/drain extension resistance is frequently a significant component. The cross-sectional area of the source/drain extensions is determined by the thickness of the fins. Source/drain series resistance may be reduced by raising the source/drain, ex-situ doping of the fin area (excluding the area under the gate) and, in particular, by implanting the entire source and drain regions thereof. However, in order to implant to the deeper depths of the source and drain regions, relatively high implant energies are required. The use of such high implant energies may heavily damage the semiconductor structure of the FinFET, and hence is undesirable. Moreover, the use of higher implant energies requires heavy masking of the channel regions to avoid unwanted implantation into these areas of the device.

Source/drain series resistance may also be reduced through salicidation of source/drain contacts. However, this approach is limited by the surface area available for salicidation, which may be further limited by the presence of spacer structures.

It has now been found that the aforementioned problems may be addressed by reducing the height of the source/drain regions in a semiconductor device. This may be accomplished, for example, through the partial removal of the source/drain regions through etching. Preferably, an anisotropic dry etch is used for this purpose, although an isotropic etch may be used in embodiments where etching into the channel region (and under the spacer structures) is desired, as where it is desirable to increase the penetration of the implant dopant beneath the spacer structures.

Since this methodology results in source/drain regions having reduced heights, these regions may be implanted all the way to the bottom of these regions, and at lower implant energies than would otherwise be the case. After implantation, the vertical and horizontal surfaces of the fins may be salicided. Here, the method is further advantageous in that it increases the surface area available for salicidation, since it exposes additional surface area beneath the spacer for salicidation. Absent this approach, salicidation would only occur on previously exposed surfaces of the gate, and hence in many applications would be limited to the top surface of the gate. This additional salicidation can help to compensate for source/drain series resistance, as well as for the adverse effect on drive current of lower levels of implantation when such lower levels are required due to other considerations.

The methodologies described herein are also advantageous in that they allow the polysilicon gate height to be kept sufficiently high to compensate for spacer overetching. The additional height of the polysilicon is useful during such overetching because it gets etched during the etching of the source/drain regions. Hence, the additional height of polysilicon ensures that a suitable amount of polysilicon remains which extends over the fin. Preferably, the additional height of the polysilicon is equal to the amount that will be removed during source/drain etching.

The devices and methodologies disclosed herein may be further understood with reference toFIGS. 3-8, which depict a particular, non-limiting embodiment of a fabrication process for a FinFET device in accordance with the teachings herein. As shown therein, a semiconductor structure201is provided which comprises a dielectric substrate203having a fin205disposed thereon. The fin205extends between source207and drain209regions (which may be further defined in subsequent process steps) and, upon completion of the FinFET, will contain the channel region of the transistor.

The semiconductor structure201ofFIG. 3may be formed from a semiconductor-on-insulator (SOI) wafer or other suitable substrate. Processes for forming such structures are well known in the art and typically include use of suitable masking and etching processes.

With reference toFIG. 4, following formation of the fin205, a gate structure211is formed which extends over the fin205. The gate structure may be formed, for example, by depositing a layer of polysilicon, and exposing the layer of polysilicon to suitable masking and etching processes. Though not shown, a layer of a suitable dielectric material is typically deposited over the fin205prior to formation of the gate structure211, and the exposed portions of the layer of dielectric material are stripped after formation of the gate structure211. As a result, an insulating layer of dielectric material remains between the gate structure211and the fin205to provide suitable electrical isolation between them.

As shown inFIG. 5, a conformal layer, which preferably comprises silicon nitride, is deposited over the structure. The conformal layer is then subjected to a suitable etch back, preferably with a dry, anisotropic etch, to produce first and second spacer structures213on the primary faces of the fin205.

Referring now toFIG. 6, the structure is then subjected to a suitable etch to reduce the height of the source207and drain209regions. This etch also has the effect of reducing the height of the fin205, thus opening up an additional vertical region215on each major face of the fin205where the material of the gate211is exposed.

As shown inFIG. 7, the structure is then subjected to an implantation251to define the source207and drain209regions of the device, and is subjected to first253and second254angular implantations (at first and second angles φ1and φ2, respectively, which may be the same or different) into the additional regions215on the first and second respective major surfaces of the fin205. Typically, |φ1| and |φ2| are within the range of about 20° to about 70° as measured with respect to an axis which is perpendicular to the substrate203. Preferably, |φ1| and |φ2| are within the range of about 30° to about 60°, more preferably, |φ1| and |φ2| are within the range of about 40° to about 50°, and most preferably, |φ1| and |φ2| are about 45°.

The presence of additional exposed regions215allows the angled implant to implant into the extension regions of the device irrespective of fin pitch, and hence reduce source/drain extension resistance and, therefore, parasitic series resistance. Various dopants may be used for the angled implants including, but not limited to, such dopants as Si, Ge, Sb, In, As, P, BF2, Xe or Ar. The dopants used for the angled implant may be the same or different.

With reference toFIG. 8, the structure is then subjected to salicidation. This results in the formation of a layer of metal silicide over the exposed surfaces of the source207, drain209and gate structure211, and also results in salicidation of the additional region215on one or both major surfaces of the fin205.

The foregoing process has some notable advantages. First of all, the etch depicted inFIG. 4has the effect of reducing the height of the fin205and the source207and drain209regions. Consequently, the source205and drain207regions may be implanted to a greater depth, and with a greater dopant concentration, than would be the case if the source207and drain209regions were taller. Also, lower implant energies may be utilized during the implant process, which results in less damage to the structure.

The advantage of greater dopant concentration in the source207and drain209regions of the device afforded by the methodology ofFIGS. 3-8may be appreciated with respect toFIG. 9, which is a graph of the percent change in drive current (IdSat) as a function of the concentration of dopant (in 1020cm−3) in the source/drain regions. As seen therein, drive current drops significantly with an increase in dopant concentration.

A further advantage of the process depicted inFIGS. 3-8is that the opening of additional regions215as a result of fin205etching increases the total surface area available for salicidation. The additional salicidation available by the opening of such regions may be used to compensate for adverse effects on drive current and for parasitic series resistance. For example, in some applications, lower than optimal levels of doping may be utilized in the source207and drain209regions during the fabrication of the FinFET device. This may be due to the need to minimize structure damage by avoiding the use of higher implant energies, which results in lower dopant levels at greater depths. Lower doping levels may also be required to minimize adverse consequences which can result from doping the adjacent portions of the fin205. Such adverse consequences may also include parasitic capacitances attendant to the uneven doping of the fin which may accompany doping of the adjacent source207and drain209regions.

The process depicted inFIGS. 3-8is further advantageous in that it provides a means by which a suitable height of the gate211above the fin205may be maintained in applications in which overetching of the first and second spacer structures213is desirable. In such applications, the additional height of the gate structure211is useful during the overetching because it gets etched during the etching of the source/drain regions. Hence, the additional height of polysilicon ensures that a suitable amount of polysilicon remains which extends over the fin. Preferably, the additional height of the polysilicon is equal to the amount that will be removed during etching of the source207and drain209regions.

FIGS. 10-12illustrate a particular, non-limiting embodiment of an application of the methodologies taught herein to the fabrication of bulk semiconductor devices. With reference toFIG. 10, a structure is depicted which comprises a bulk semiconductor substrate305upon which is defined a gate311. The gate311has first and second spacer structures313defined adjacent thereto.

With reference toFIG. 11, the structure is subjected to a suitable etch to remove a portion of the substrate305adjacent to the first and second spacer structures313. This etch exposes a portion of the substrate305which underlies the spacer structure, and hence creates a mesa structure314which has vertical surfaces315and which contains the channel region of the device.

As shown inFIG. 12, the substrate305is then subjected to an implant to define the source and drain regions of the device (or portions thereof). In addition, the mesa structure314(and in particular, the portion of the substrate305beneath the spacer structures which is contained therein and which has been exposed by the etch) is further subjected to first353and second354tilted implants at first and second angles φ1and φ2, respectively. The angles and dopants used in these implants may be the same or different, and may include any of those mentioned in reference to the previously described embodiments. As with the previously described embodiments, this embodiment is advantageous in that it permits a greater dopant concentration to be achieved in the channel region of the device than would be the case without formation of the mesa structure314. In addition, this approach also permits the use of lower implant energies during the implant process, which results in less damage to the structure.

The above description of the present invention is illustrative, and is not intended to be limiting. It will thus be appreciated that various additions, substitutions and modifications may be made to the above described embodiments without departing from the scope of the present invention. Accordingly, the scope of the present invention should be construed in reference to the appended claims.