Semiconductor structure with protection layer

The method for forming a semiconductor structure includes forming a protection layer having a first portion and a second portion over a substrate and forming a dummy gate layer over the first portion and the second portion of the protection layer. The method for forming a semiconductor structure further includes patterning the dummy gate layer to form a dummy gate structure over the first portion of the protection layer and forming a spacer on a sidewall of the dummy gate structure over a second portion of the protection layer. The method for forming a semiconductor structure further includes replacing the first portion of the protection layer and the dummy gate structure by a gate dielectric layer and a gate electrode layer. In addition, a thickness of the protection layer is greater than a thickness of the gate dielectric layer.

BACKGROUND

Semiconductor devices may include core devices and input/output devices. The core devices may be used to perform the functions of a chip, and the input/output devices may be used to communicate with external circuits in other chips. Although existing manufacturing processes for these semiconductor devices have generally been adequate for their intended purposes, as device scaling-down continues, they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION

Embodiments of semiconductor structures and methods for forming the same are provided. The method for forming the semiconductor structure may include forming a protection layer over a substrate before a dummy gate layer is formed, so that the protection layer may protect the substrate during the process of patterning the dummy gate layer. In addition, the protection layer may be relatively thick to provide better protection for the substrate and may be removed afterwards, so that the performance of the resulting semiconductor structure may be improved.

FIGS. 1A to 1Jare perspective representations of various stages of forming a semiconductor structure100in accordance with some embodiments. As shown inFIG. 1A, a substrate102is provided in accordance with some embodiments. The substrate102may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, the substrate102may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of the elementary semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and diamond. Examples of the compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide. Examples of the alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP.

A fin structure104is formed from the substrate102, and an isolation structure106is formed around the fin structure104, as shown inFIG. 1Ain accordance with some embodiments. The fin structure104may be formed by patterning the substrate102. The isolation structure106may be formed by forming an insulating material over the substrate102and the fin structure104and recessing the insulating material to expose the top portion of the fin structure104. In some embodiments, the insulating material is made of silicon oxide, silicon nitride, silicon oxynitride, fluoride-doped silicate glass (FSG), or other low-K dielectric materials. The insulating material may be formed by using a high-density-plasma (HDP) CVD process, although other deposition processes may be used in other embodiments.

Next, a protection layer108is formed over the fin structure104and the isolation structure106, as shown inFIG. 1Bin accordance with some embodiments. As shown inFIG. 1B, the protection layer108is formed over the top surface of the sidewalls of the fin structure104and extends over the top surface of the isolation structure106. The protection layer108may be configured to prevent the substrate102and the elements formed over the substrate (e.g. the fin structure104and the isolation structure106) from being damaged in subsequent manufacturing processes, and therefore the protection layer108may be relatively thick to protect the elements below it.

In some embodiments, the protection layer108has a thickness in a range from about 20 Å to about 100 Å. The protection layer108should be thick enough to protect the structure formed below it, while not being too thick or it may be too difficult to be completely removed and therefore undermine the performance of the resulting semiconductor structure.

In some embodiments, the protection layer108is an oxide layer. In some embodiments, the protection layer108is a silicon oxide layer. In some embodiments, the protection layer108is made of metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, or oxynitrides of metals. Examples of materials used to form the protection layer108include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), silicon nitride, silicon oxynitride, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, or other applicable dielectric materials.

After the protection layer108is formed, a dummy gate layer110is formed over the protection layer108, as shown inFIG. 1Cin accordance with some embodiments. In some embodiments, the dummy gate layer110is a polysilicon layer.

Next, the dummy gate layer110is patterned to form a dummy gate structure112, as shown inFIG. 1Din accordance with some embodiments. The dummy gate layer110may be patterned by forming a mask over a portion of the dummy gate layer110and etching the portions of the dummy gate layer110not covered by the mask. The dummy gate layer110may be etched by performing a dry etching process. The dry etching process may be designed to be stopped when the protection layer108is exposed. In addition, as described previously, the protection layer108is relatively thick, so that even if some top portions of the protection layer108are removed during the etching process, the structure formed underneath (e.g. the fin structure104and/or the isolation structure106) can still be well protected and therefore will not be damaged.

After the dummy gate layer110is patterned to form the dummy gate structure112over the protection layer108, spacers114are formed on the sidewalls of the dummy gate structure112, as shown inFIG. 1Ein accordance with some embodiments. In addition, the spacers114also cover portions of the protection layer108.

As shown inFIG. 1E, the protection layer108includes a first portion108i, second portions108ii, and third portions108iii, and the dummy gate structure112is located over a first portion108iof the protection layer108and the spacers114are formed over the second portions108iiof the protection layer108. In addition, the second portions108iiof the protection layer108are located at the opposite sides of the first portion108iof the protection layer108, and the third portions108iiiare further apart from the first portion108iof the protection layer108.

In some embodiments, the spacers114are made of silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, or other applicable dielectric materials. In some embodiments, the spacers114and the protection layer108are made of different materials so that they may have relatively good etching selectivity in subsequent etching processes.

After the spacers114are formed, the exposed portions of the protection layer108are removed, as shown inFIG. 1Fin accordance with some embodiments. That is, the third portions108iiiof the protection layer108not covered by the dummy gate structure112and the spacers114are removed. In some embodiments, the third portions108iiiof the protection layer108are removed by performing an etching process.

Afterwards, source/drain structures116are formed in the fin structure104adjacent to the dummy gate structure112, as shown inFIG. 1Fin accordance with some embodiments. In addition, the source/drain structures116are formed at opposite sides of the dummy gate structure112in accordance with some embodiments. The source/drain structures116may be formed by recessing the fin structure104and growing semiconductor materials in the recesses by performing epitaxial (epi) processes. In some embodiments, the source/drain structures116include Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, or a combination thereof.

After the source/drain structures116are formed, a contact etch stop layer (CESL)118is formed over substrate102, and an interlayer dielectric layer120is formed over the contact etch stop layer118, as shown inFIG. 1Hin accordance with some embodiments. In some embodiments, the contact etch stop layer118is made of silicon nitride, silicon oxynitride, and/or other applicable materials. The contact etch stop layer118may be formed by performing plasma enhanced CVD, low pressure CVD, ALD, or other applicable processes.

The interlayer dielectric layer120may include multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and/or other applicable low-k dielectric materials. The interlayer dielectric layer236may be formed by performing chemical vapor deposition (CVD), physical vapor deposition, (PVD), atomic layer deposition (ALD), spin-on coating, or other applicable processes.

Next, the dummy gate structure112is removed to form a trench122between the spacers114, as shown inFIG. 1Hin accordance with some embodiments. In some embodiments, the dummy gate structure112is removed by performing a dry etching process. As shown inFIG. 1H, after the dummy gate structure112is removed, the first portion108iof the protection layer108is exposed by the trench122while the second portions108iiof the protection layer108are covered by the spacers114.

Next, the first portion108iof the protection layer108exposed by the trench122is removed, as shown inFIG. 1Iin accordance with some embodiments. In some embodiments, the first portion108iof the protection layer108is removed by performing a dry etching process. As shown inFIG. 1I, some portions of the fin structure104and the isolation structure106are exposed by the trench122after the first portion108iof the protection layer108is removed.

Afterwards, a metal gate structure124is formed in the trench122, as shown inFIG. 1Jin accordance with some embodiments. In some embodiments, the metal gate structure124in the semiconductor structure100includes a gate dielectric layer126, a work function metal layer128, and a gate electrode layer130. Since the first portion108iof the protection layer108is removed before the metal gate structure124is formed, the metal gate structure124is formed directly on the fin structure104and the isolation structure106.

In some embodiments, the gate dielectric layer126and the protection layer108are made of the same material, but the protection layer108is thicker than the gate dielectric layer126. As described previously, the protection layer108is formed to protect the structures under it (e.g. the fin structure104and the isolation structure106) during subsequent etching processes. Therefore, the protection layer108is designed to be relatively thick. On the other hand, the thickness of the gate dielectric layer126is designed to be relatively thin, so that the resulting semiconductor structure100may have a lower resistance.

In some embodiments, the difference between the thickness of the protection layer108and the thickness of the gate dielectric layer126is in a range from about 5 Å to about 80 Å. As described above, the difference of the thicknesses between the protection layer108and the gate dielectric layer126is adjusted, so that the structure under the protection layer108can be well protected in previous manufacturing processes (e.g. the etching process shown inFIG. 1D) while the resulting semiconductor structure100can still have a relatively low resistance.

In some embodiments, the gate dielectric layer126is an oxide layer. In some embodiments, the gate dielectric layer126is a silicon oxide layer. In some embodiments, the gate dielectric layer126is made of metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, or oxynitrides of metals. Examples of materials used to form the gate dielectric layer240include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), silicon nitride, silicon oxynitride, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, or other applicable dielectric materials.

In some embodiments, the work function metal layer128is formed over the gate dielectric layer126. The work function metal layer128may be tuned to have the proper work function. For example, if a P-type work function metal (P-metal) for a PMOS device is desired, P-type work function materials may be used. Examples of P-type work function materials include, but are not limited to, titanium nitride (TiN), tungsten nitride (WN), tungsten (W), ruthenium (Ru), palladium (Pd), platinum (Pt), cobalt (Co), nickel (Ni), conductive metal oxides, and/or other applicable materials.

On the other hand, if an N-type work function metal (N-metal) for NMOS devices is desired, N-type metal materials may be used. Examples of N-type work function materials include, but are not limited to, titanium aluminide (TiAl), titanium aluminium nitride (TiAlN), carbo-nitride tantalum (TaCN), hafnium (Hf), zirconium (Zr), titanium (Ti), tantalum (Ta), aluminum (Al), metal carbides (e.g., hafnium carbide (HfC), zirconium carbide (ZrC), titanium carbide (TiC), aluminum carbide (AlC), aluminides, and/or other applicable materials.

In some embodiments, the gate electrode layer130is formed over the work function metal layer128. In some embodiments, the gate electrode layer130is made of a conductive material, such as aluminum, copper, tungsten, titanium, tantalum, titanium nitride, tantalum nitride, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other applicable materials.

As described previously, the protection layer108is formed over the fin structure104and the isolation structure106before the dummy gate layer110is formed. Therefore, the protection layer108can protect the structure below it from being damaged during the etching process for patterning the dummy gate layer110. In addition, the first portion108iof the protection layer108located under the dummy gate structure112is replaced by a relatively thin gate dielectric layer126, and therefore the resulting semiconductor structure100can still have a relatively low resistance. Since damage to the fin structure104and the isolation structure106can be prevented while the semiconductor structure100can still have a relatively thin gate dielectric layer126, the performance of the semiconductor structure100can be improved.

It should be noted that, although the first portion108i, the second portions108iiand the third portions108iiiof the protection layer108are shown in the figures described above, there are no real boundaries (e.g. interfaces) between each portion. That is, these portions are merely shown to provide a better understanding of the concept of the disclosure, but the scope of the disclosure is not intended to be limiting.

FIG. 2is a cross-sectional representation of the semiconductor structure100shown alone line A-A′ inFIG. 1Jin accordance with some embodiments. As shown inFIG. 2, the semiconductor structure100includes the metal gate structure124, and the metal gate structure124includes the gate dielectric layer126, which is thinner than the second portion108iiof the protection layer. In addition, the gate dielectric layer126is in direct contact with both the spacer114and the second portion108iiof the protection layer, and the spacer114is located at the upper portion of the gate dielectric layer126and the second portion108iiof the protection layer is located at the bottom portion of the gate dielectric layer126. In some embodiments, the interface between the spacer114and the second portion108iiof the protection layer is at a higher position than the bottom surface of the work function metal layer128, which means that the protection layer is thick enough to protect the fin structure104underneath.

As described previously, the gate dielectric layer126and the protection layer108(i.e. the second portion108iiof the protection layer108) may be made of the same material. In some embodiments, the gate dielectric layer126and the second portion108iiof the protection layer are made of a same oxide, such that an oxide layer is position between the work function metal layer128of the gate structure124and the spacer114and further extends under the work function metal layer128and the spacer114. In addition, the extending portion of the oxide layer located under the spacer114(i.e. the second portion108iiof the protection layer108) is thicker than the extending portion of the oxide layer located under the work function metal layer128(i.e. the gate dielectric layer126).

FIGS. 3A to 3Iare cross-sectional representations of various stages of forming a semiconductor structure200in accordance with some embodiments. Some materials and processes used to form the semiconductor structure200may be similar to, or the same as, those used to form the semiconductor structure100and are not repeated herein.

As shown inFIG. 3A, a substrate202includes a first region201aand a second region201bin accordance with some embodiments. In some embodiments, the first region201ais a core region, and the second region201bis an input/output region. Core devices may be formed in the core region to perform the designed functions of the semiconductor structure, and input/output devices may be formed in the input/output region to communicate with external circuits.

Similar to the processes described previously related toFIG. 1A, a first fin structure204aand a second fin structure204bmay be formed from the substrate202in accordance with some embodiments. In addition, the first fin structure204ais formed over the first region201a, and the second fin structure204bis formed in the second region201bin accordance with some embodiments.

Next, a first protection layer208ais formed over the first region201aof the substrate102, and a second protection layer208bis formed over the second region201bof the substrate102, as shown inFIG. 3Ain accordance with some embodiments. The first protection layer208aand the second protection layer208bmay be similar to the protection layer108described previously and are configured to prevent the substrate202and the elements formed over the substrate (e.g. the first fin structure204aand the second fin structure204b) from being damaged in subsequent manufacturing processes. That is, the first protection layer208aand the second protection layer208bmay be relatively thick.

In addition, although the first protection layer208aand the second protection layer208bare formed over different regions of the substrate202, they may be formed by performing a single depositing process in accordance with some embodiments. Since the first protection layer208aand the second protection layer208bmay be formed by the same process, the thickness of the first protection layer208amay be substantially equal. In some embodiments, both the thickness of the first protection layer208aand the thickness of the second protection layer208bare in a range from about 20 Å to about 100 Å. As described previously, the first protection layer208aand the second protection layer208bshould be thick enough to protect the substrate202underneath in subsequent manufacturing processes. The materials used to form the first protection layer208aand the second protection layer208bmay be similar to those used to form the protection layer108and are not repeated herein.

After the first protection layer208aand the second protection layer208bare formed, a first dummy gate structure212aand a second dummy gate structure212bare formed over the first protection layer208aand the second protection layer208brespectively, as shown inFIG. 3Ain accordance with some embodiments. As described previously, the first protection layer208aand the second protection layer208bmay be configured to protect the first fin structure204aand the second fin structure204bduring the etching process for forming the first dummy gate structure212aand the second dummy gate structure212b.

Next, first spacers214aand second spacers214bare formed on the sidewalls of the first dummy gate structure212aand the second dummy gate structure212brespectively, as shown inFIG. 3Bin accordance with some embodiments. Afterwards, the portions of the first protection layer208aand the second protection layer208bnot covered by the first dummy gate structure212a, the first spacers214a, the second dummy gate structure212b, or the second spacers214bare removed, as shown inFIG. 3Bin accordance with some embodiments. In some embodiments, the first dummy gate structure212ais formed over a first portion208aiof the first protection layer208a, and the first spacers214aare formed over second portions208aiiof the first protection layer208a. Similarly, the second dummy gate structure212bis formed over a second portion208biof the second protection layer208b, and the second spacers214bare formed over second portions208biiof the second protection layer208bin accordance with some embodiments.

Afterwards, first source/drain regions216aare formed in the first region201aof the substrate102and at opposite sides of the first dummy gate structure212a, and second source/drain regions216bare formed in the second region201bof the substrate102and at opposite sides of the second dummy gate structure212b, as shown inFIG. 3Bin accordance with some embodiments. After the first source/drain regions216aand the second source/drain regions216bare formed, a contact etch stop layer (CESL)218is conformally formed over the substrate202, and an interlayer dielectric layer220is formed over the contact etch stop layer218and the top portion of the contact etch stop layer218and the interlayer dielectric layer220are polished until the top surfaces of the first dummy gate structure212aand the second dummy gate structure212bare exposed, as shown inFIG. 3Cin accordance with some embodiments.

Next, the first dummy gate structure212aand the second dummy gate structure212bare removed to form a first trench222aand a second trench222b, as shown inFIG. 3Din accordance with some embodiments. As shown inFIG. 3D, after the first dummy gate structure212aand the second dummy gate structure212bare removed, the first portion208aiof the first protection layer208ais exposed by the first trench222a, and the first portion208biof the second protection layer208bis exposed by the second trench222b.

After the first dummy gate structure212aand the second dummy gate structure212bare removed, the first portion208aiof the first protection layer208aand the first portion208biof the second protection layer208bare removed, as shown inFIG. 3Ein accordance with some embodiments. As shown inFIG. 3E, a top surface205aof the first fin structure204ais exposed by the first trench222a, and a top surface205bof the second fin structure204bis exposed by the second trench222bin accordance with some embodiments.

Afterwards, a first gate dielectric layer226ais conformally formed over the first region201aof the substrate102, and a second gate dielectric layer226bis conformally formed over the second region201bof the substrate102, as shown inFIG. 3Fin accordance with some embodiments. The processes and materials used to form the first gate dielectric layer226aand the second gate dielectric layer226bmay be similar to, or the same as, those of the gate dielectric layer126described previously and may not repeated herein.

In some embodiments, the first gate dielectric layer226aand the second gate dielectric layer226bare formed by performing a single deposition process. Since the first gate dielectric layer226aand the second gate dielectric layer226bmay be formed by performing the same process, the first gate dielectric layer226aand the second gate dielectric layer226bmay be made of the same material and may have a substantially equal thickness. In addition, the first gate dielectric layer226ais thinner than the second portion208aiiof the first protection layer, and the second gate dielectric layer226bis thinner than the second portion208biiof the second protection layer in accordance with some embodiments.

Next, a resist layer223is formed over the second region201bof the substrate102to cover the second gate dielectric layer226b, as shown inFIG. 3Gin accordance with some embodiments. The resist layer223may be a photoresist layer formed over the second gate dielectric layer226band filled in the second trench222bto protect the structure formed in the second region201bof the substrate102during subsequent manufacturing processes. After the resist layer223is formed, the first gate dielectric layer226ais removed, as shown inFIG. 3Gin accordance with some embodiments.

After the first gate dielectric layer226ais removed, a first metal gate structure224ais formed in the first trench222a, as shown inFIG. 3Hin accordance with some embodiments. In some embodiments, the first metal gate structure224aincludes an interfacial layer225, a first work function metal layer228a, and a first gate electrode layer230a.

In some embodiments, the interfacial layer225is an oxide layer formed by reacting the top surface205aof the first fin structure204awith an acidic solution. In some embodiments, the interfacial layer225is thinner than the first gate dielectric layer226a(i.e. thinner than the second gate dielectric layer226b), so that the resulting first gate structure224acan have a lower resistance. Therefore, the operation speed of the first gate structure224acan be improved further. The processes and materials used to form the first work function metal layer228aand the first gate electrode layer230amay be similar to, or the same as, those used to form the work function metal layer128and the gate electrode layer130and are not repeated herein.

After the first metal gate structure224ais formed, the resist layer223is removed, and a second metal gate structure224bis formed in the second trench222b, as shown inFIG. 3Iin accordance with some embodiments. In some embodiments, the second metal gate structure224bincludes the second gate dielectric layer226bformed previously, a second work function metal layer228b, and a second gate electrode layer230b. The processes and materials used to form the second work function metal layer228band the second gate electrode layer230bmay be similar to, or the same as, those used to form the work function metal layer128and the gate electrode layer130and are not repeated herein.

As described previously, the first protection layer208aand the second protection layer208bare formed over the first region201aand the second region201bof the substrate102to prevent the structures underneath from being damaged during subsequent manufacturing processes (e.g. the etching process which is used to form the first dummy gate structure212aand the second dummy gate structure212b). Accordingly, the second portion208aiiof the first protection layer208aand the second portion208biiof the second protection layer208bremaining under the first spacers214aand the second spacers214bare relatively thick so that they can provide sufficient protection during the manufacturing processes.

However, since the first protection layer208aand the second protection layer208bare relatively thick, they may result in high resistance when used in a gate structure. Therefore, in the first metal gate structure224aand the second gate structure224b, the interfacial layer225and the second gate dielectric layer226bare formed to replace the first portion208aiof the first protection layer208aand the second portion208biof the second protection layer208brespectively.

In some embodiments, the second portion208aiiof the first protection layer is thicker than the interfacial layer225, such that the interface between the second portion208aiiof the first protection layer is at a higher position than the top surface of the interfacial layer225(e.g. the bottom surface of the work function metal layer228a). As described previously, the semiconductor structure200can have less substrate damage due to the formation of the first protection layer208awhile having a relatively low resistance due to the formation of the interfacial layer225. As shown inFIG. 3I, the interfacial layer225is in direct contact with the second portion208aiiof the first protection layer but is not in direct contact with the first spacers214asince the interfacial layer225is thinner than the second portion208aiiof the first protection layer in accordance with some embodiments. On the other hand, the sidewall of the first work function metal layer228ais in direct contact with both the second portion208aiiof the first protection layer and the first spacers214ain accordance with some embodiments.

In some embodiments, the second portion208biiof the second protection layer is thicker than the second gate dielectric layer226b, such that the interface between the second portion208biiof the second protection layer is at a higher position than the bottom surface of the second work function metal layer228b. Similarly, the semiconductor structure200can have less substrate damage due to the formation of the second protection layer208bwhile having a relatively low resistance due to the formation of the second gate dielectric layer226b. As shown inFIG. 3I, the second gate dielectric layer226bis in direct contact with both the second portion208biiof the second protection layer and the second spacers214bin accordance with some embodiments. On the other hand, the sidewall of the second work function metal layer228bis not in direct contact with neither the second portion208biiof the second protection layer nor the second spacers214bin accordance with some embodiments.

Furthermore, in some embodiments, the first region201ais a core region and the second region201bis an input/output region in the semiconductor structure200. That is, the first gate structure224aformed in the first region201amay be used in a core device with a relatively high operating speed and greater current control. As described previously, the first protection layer208ais formed over the first region201abefore the first dummy gate structure212ais formed, so that damage to the structure underneath can be prevented and therefore the performance of the resulting semiconductor structure200can be improved. In addition, the first portion208aiof the first protection layer208ais replaced by the thin interfacial layer225in the first gate structure224a, and therefore resistance can be decreased and the operation speed can be improved.

On the other hand, the second gate structure224bformed in the second region201bmay be used in an input/output device to communicate with external circuits. Therefore, the first portion208biof the second protection layer208bis replaced by the second gate dielectric layer226bin the second gate structure224b, so that the second gate dielectric layer226bcan be thin enough to have a relatively low resistance but still be thick enough to sustain the high voltage applied to the peripheral circuit. In addition, damage to the structure underneath the second protection layer208bcan also be prevented, and therefore the performance of the semiconductor structure200may be improved further.

In some embodiments, the difference between the thickness of the first protection layer208aand that of the interfacial layer225is in a range from about 5 Å to about 80 Å. In some embodiments, the difference between the thickness of the second protection layer208band that of the second gate dielectric layer226bis in a range from about 5 Å to about 70 Å. In some embodiments, the difference between the thickness of the first protection layer208aand that of the interfacial layer225is greater than the difference between the thickness of the second protection layer208band that of the second gate dielectric layer226b. Accordingly, the performance of the first gate structure224aused in a core device and that of the second gate structure224bused in an input/output device may both be improved.

Embodiments of methods for forming a semiconductor structure are provided. The method may include forming a relatively thick protection layer over a substrate, and a dummy gate structure is formed over the protection layer. Since the protection layer is formed before the dummy gate structure is formed, the substrate can be protected during the processes for forming the dummy gate structure. In addition, the portion of the protection layer located under the dummy gate structure may be replaced by a gate dielectric layer when the dummy gate structure is replaced by a metal gate structure. The gate dielectric layer may be thinner than the protection layer, so the resulting gate structure may have a lower resistance. Accordingly, the resulting semiconductor structure can have a relatively thin gate structure while the damage to the substrate in the semiconductor structure can be prevented by forming the protection layer.

In some embodiments, a method for forming a semiconductor structure is provided. The method for forming a semiconductor structure includes forming a protection layer having a first portion and a second portion over a substrate and forming a dummy gate structure over the first portion of the protection layer and forming a spacer on a sidewall of the dummy gate structure over a second portion of the protection layer. The method for forming a semiconductor structure further includes replacing the first portion of the protection layer and the dummy gate structure by a gate dielectric layer and a gate electrode layer. In addition, a thickness of the protection layer is greater than a thickness of the gate dielectric layer.

In some embodiments, a method for forming a semiconductor structure is provided. The method for forming a semiconductor structure includes forming a first protection layer over a first region of a substrate and a second protection layer over a second region of the substrate and forming a first dummy gate structure over the first protection layer and a second dummy gate structure over the second protection layer. The method for forming a semiconductor structure further includes forming first spacers over sidewalls of the first dummy gate structure and second spacers over sidewalls of the second dummy gate structure and removing the first dummy gate structure to form a first trench and removing the second dummy gate structure to form a second trench. The method for forming a semiconductor structure further includes removing the first protection layer exposed by the first trench and the second protection layer exposed by the second trench and forming a first gate dielectric layer in the first trench and a second gate dielectric layer in the second trench. The method for forming a semiconductor structure further includes removing the first gate dielectric layer to expose a portion of a top surface of the substrate and forming an interfacial layer over the portion of the top surface of the substrate exposed by the first trench. The method for forming a semiconductor structure further includes forming a first gate structure over the interfacial layer and forming a second gate structure over the second gate dielectric layer.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a first gate structure formed over a first region of a substrate. In addition, the first gate structure includes an interfacial layer and a first gate electrode layer. The semiconductor structure further includes a first protection layer formed adjacent to the first gate structure and a first spacer formed over the first protection layer, such that a sidewall of the first gate structure is covered by the first protection layer and the first spacer. In addition, an interface between the first protection layer and the first spacer is at a higher position than a top surface of the interfacial layer.