Gettering contaminants for integrated circuits formed on a silicon-on-insulator structure

Gettering contaminants for formation of integrated circuits on a semiconductor-on-insulator structure is described. A semiconductor-on-insulator structure is configured to attract contaminants. Contaminant attractor regions are formed using ion implantation into a semiconductor layer of the semiconductor-on-insulator structure. The semiconductor layer is located above a buried insulator layer of the semiconductor-on-insulator structure. The contaminant attractor regions are spaced away from active regions. Tiles are located on an upper surface of the buried insulator layer. The contaminant attractor regions are formed adjacent to, in close proximity to, or in the tiles. At least one dielectric layer laterally adjacent to the tiles and is disposed on the upper surface of the buried insulator layer. The at least one dielectric layer at least inhibits lateral migration of contaminants to the active regions.

FIELD

One or more aspects of the invention generally relate to integrated circuits and, more particularly, to gettering contaminants for formation of integrated circuits on a semiconductor-on-insulator structure, for example a silicon-on-insulator structure.

BACKGROUND

Conventionally, semiconductor memories, such as static random access memory (“SRAM”) and dynamic random access memory (“DRAM”), are in widespread use. DRAM is very common due to its high density with a cell size typically between 6F2and 8F2, where F is a minimum feature size. However, DRAM conventionally has relatively slow access time. SRAM access time is conventionally an order of magnitude faster than DRAM. Though, an SRAM cell is commonly made of four transistors and two resistors or of six transistors, thus leading to a density of approximately 60F2to 100F2.

Memory designs based on a negative differential resistance (“NDR”) cell, such as a thyristor cell, have been introduced as a replacement for conventional DRAM and SRAM. A thyristor-based random access memory (“RAM”) may be effective in either or both SRAM and DRAM applications.

Contaminants remain a problem in forming integrated circuits. This problem is exacerbated in silicon-on-insulator (“SOI”) wafers, as some contaminants do not diffuse through the buried oxide layer, and thus remain in the silicon layer used for formation of integrated circuit components.

Accordingly, it would be desirable and useful to provide means to mitigate against harmful effects of contaminants.

BRIEF SUMMARY

One or more aspects of the invention generally relate to integrated circuits and, more particularly, to gettering contaminants for formation of integrated circuits on a semiconductor-on-insulator structure.

An aspect is a semiconductor-on-insulator structure configured to attract contaminants. Contaminant attractor regions are formed using ion implantation into a semiconductor layer of the semiconductor-on-insulator structure. The semiconductor layer is located above a buried insulator layer of the semiconductor-on-insulator structure. The contaminant attractor regions are spaced away from active regions of the semiconductor-on-insulator structure. Tiles are located on an upper surface of the buried insulator layer. The contaminant attractor regions are formed adjacent to, in close proximity to, or in the tiles. The contaminant attractor regions are for gettering at least a portion of the contaminants located in the active regions to the contaminant attractor regions. At least one dielectric layer laterally adjacent to the tiles and is disposed on the upper surface of the buried insulator layer. The at least one dielectric layer at least inhibits lateral migration of contaminants to the active regions.

Another aspect is a method for forming an array of thyristor-based memory cells. A semiconductor-on-insulator structure is obtained. Shallow trench isolation regions are formed in a semiconductor layer of the semiconductor-on-insulator structure. A patterned mask defining openings is formed, and the openings are associated with at least one type of contact of the thyristor-based memory cells. An implanting is done into contact regions associated with the openings, the implanting forming defect regions within the contact regions. A thermal cycling of the semiconductor-on-insulator structure is done to getter contaminants toward the defect regions.

Yet another aspect is an integrated circuit formed on a semiconductor-on-insulator structure configured to attract contaminants. Contaminant attractor regions are formed using ion implantation into a semiconductor layer of the semiconductor-on-insulator structure. The semiconductor layer is located above a buried oxide layer of the semiconductor-on-insulator structure. An active region of the semiconductor layer of the semiconductor-on-insulator structure includes a dummy stripe and an active stripe. The dummy stripe is disposed at or proximate to an outer border of the active region. The ion implantation is into the dummy stripe for formation of the contaminant attractor regions therein. The contaminant attractor regions are for gettering at least a portion of the contaminants in the active region to the first contaminant attractor regions. At least one dielectric layer is disposed on the upper surface of the buried oxide layer including extending laterally along sides of the dummy stripe. The at least one dielectric layer at least inhibits lateral migration of the contaminants from the contaminant attractor regions of the dummy stripe to the active stripe when the semiconductor-on-insulator structure is exposed to a thermal cycle sufficient to mobilize the contaminants.

Still yet another aspect is a method of forming a semiconductor-on-insulator structure configured to attract contaminants away from active regions. Contaminant attractor regions are formed using ion implantation into a semiconductor layer of the semiconductor-on-insulator structure. The semiconductor layer is located above a buried insulator layer of the semiconductor-on-insulator structure. The contaminant attractor regions are spaced away from the active regions of the semiconductor-on-insulator structure. The contaminant attractor regions are formed adjacent to, in close proximity to, or in tiles. The tiles are located on an upper surface of the buried insulator layer of the semiconductor-on-insulator structure. The contaminants are mobilized by bringing the semiconductor layer up to an elevated temperature at least above 250 degrees Celsius. A sufficient duration of time at the elevated temperature is provided for the contaminants to diffuse to the contaminant attractor regions. The contaminants are trapped in the contaminant attractor regions. A patterned mask is formed above the semiconductor layer, and the semiconductor layer is etched to remove at least a portion thereof to expose sidewalls of the tiles. At least one dielectric layer laterally surrounding the tiles is formed such that it is disposed on the upper surface of the buried insulator layer. The at least one dielectric layer at least inhibits lateral migration of the contaminants trapped in the tiles to the active regions.

DETAILED DESCRIPTION OF THE DRAWINGS

In the following description, numerous specific details are set forth to provide a more thorough description of the specific embodiments of the invention. It should be apparent, however, to one skilled in the art, that the invention may be practiced without all the specific details given below. In other instances, well-known features have not been described in detail so as not to obscure the invention. For ease of illustration, the same number labels are used in different diagrams to refer to the same items, however, in alternative embodiments the items may be different.

FIG. 1Ais a schematic diagram depicting an exemplary embodiment of a memory array100. Memory array100includes thyristor-based memory devices101. Pairs of memory devices101may be commonly coupled at a bitline contact106for connection to a bitline110and may be commonly coupled at a supply voltage contact107for connection to a supply voltage line113. Voltage on supply voltage line113is above both a logic low voltage reference level (“Vss”) and a logic high voltage reference level (“Vdd”), and this supply voltage may be used as an anodic voltage for memory device101. Accordingly, reference to this supply voltage includes its anodic use, and as such it is referred to herein as “VDDA” to clearly distinguish it from Vdd. Thus, supply voltage line113is subsequently referred to herein as anode voltage line113, and supply voltage contact107is subsequent referred to herein as anode contact107.

Each memory device101includes an access device (“transistor”)108, which may be a field effect transistor (“FET”), and a thyristor-based storage element102. In this embodiment, memory device101is for SRAM or SRAM-like applications. However, access device108may be removed for forming a memory device101with an array of thyristor-based storage elements (“array of memory cells”)200, as described below in additional detail with reference toFIG. 1C.

Access device108need not be a transistor; however, for purposes of clarity by way of example, access device108shall be referred to herein as transistor108. Storage element102and transistor108may be commonly coupled at a node109. Node109may be a cathodic node of storage element102and a source/drain node of transistor108, and thus may be referred to hereafter as cathode node109.

In an alternatively embodiment, anode and cathode may be reversed, namely anode node109and cathode node107. This may be thought of as a reversed voltage level difference embodiment. However, for purposes of clarity by way of example and not limitation, it shall be assumed that node109is a cathode node and node107is an anode node, even though in other embodiments these nodes may have reverse functions.

InFIG. 1A, an equivalent circuit model of storage element102having cross coupled bi-polar junction transistors (“BJTs”)103and104, as well as capacitor105. Storage element102may be a type of a device known as Thin Capacity Coupled Thyristor (“TCCT”) device. Again, in this example, storage element102is coupled in series with an NMOS transistor108to provide memory device101. However, a PMOS architecture may be used, namely a reverse polarity from the one described herein may be used. For purposes of clarity by way of example and not limitation, it shall be assumed than transistor108is an NMOS device.

For each memory device101, a gate of access transistor108is formed from a wordline (“WL1”)111in relation to an active area, as generally indicated inFIG. 1Aby small dots coupling gates of access transistors108to WL1s111. A control gate of storage element102, generally indicated as a plate of capacitor105, is formed with another wordline (“WL2”)112, as generally indicated by small dots coupling plates of capacitor105to WL2s112. Though only a few rows of memory cells101are illustratively shown inFIG. 1A, it should be appreciated that many more rows may be used. The exact number of memory cells or bits associated with a WL1111or a WL2112may vary from application to application.

An emitter node of BJT103is coupled to anode voltage line113by anode contact107. A base of BJT103is coupled a collector of BJT104. An emitter of BJT104is coupled to cathode node109. A base of BJT104and a collector of BJT103are commonly coupled to a bottom plate of capacitor105, and this common coupling location may be generally referred to as storage node150.

FIG. 1Bis a cross-sectional view depicting an exemplary embodiment of a device structure for a memory device101ofFIG. 1A. In this embodiment, memory device101is formed using a silicon-on-insulator (“SOI”) structure, such as an SOI wafer, having a substrate layer120on which a buried oxide (“BOx”) layer130is formed. Formed on BOx layer130is an active silicon layer140. Alternatively, an SOI structure may be formed on a bulk silicon wafer.

In an alternative embodiment, for SRAM or SRAM-like applications, NMOS transistor108is replaced with a PMOS transistor108, and doping types of regions are swapped, namely n-type for p-type and vice versa, without having to have any structural changes for the embodiment illustratively depicted inFIG. 1B. Thus regions121,122,141,109,142, and123respectively are cathode, p-base, n-base, anode, n-well, and p-type (e.g., p+) source/drain regions.

Above regions142and141may respectively be formed one or more dielectric layers124and129. Above one or more dielectric layers124and129may respectively be formed wordlines111and112ofFIG. 1A, which in association with regions142and141are defined gates126and125, respectively. One or more dielectric layers124and129may be the same or different sets of layers, and such gate dielectric as associated with gate126and one or more dielectric layers124may be thinner than such gate dielectric associated with gate125and dielectric layers129. Gate126is a gate of transistor108and an access gate of memory device101, and gate125is a control gate of storage element102and a write gate of memory device101. An anode contact107is coupled to anode region121, and a bitline contact106is coupled to access region123. Access region123and cathode node109also serve as source/drain regions of transistor108. Other details regarding memory device101, including silicides, extension regions, and spacers, among other known details, may be found in U.S. Pat. Nos. 6,767,770 B1 and 6,690,039 B1.

FIG. 1Cis a circuit diagram depicting an exemplary embodiment of a thyristor-based array of cells (“array”)200for a DRAM or DRAM-like application. Array200includes TCCT storage elements or thyristor-based memory cells (“memory cells”)102.

WL2s112in this exemplary embodiment are wordlines, as previously described. Row lines221are commonly coupled to rows of memory cells102at respective nodes109thereof, which may be cathodes. For purposes of clarity, the term “node,” as used herein, is to refer to either or both a contact and a semiconductor region. Bitlines or column lines110are commonly coupled to columns of memory cells102at nodes107thereof, which may be anodes.

In an alternative embodiment, wordline and bitline functions may be swapped to form an “inverse” cell. In such an “inverse cell,” p- and n-type dopings are reversed from the embodiment described herein for purposes of clarity and not limitation. In the inverse cell, anode and cathode positions are swapped from the embodiment described herein for purposes of clarity and not limitation. Thus, inFIG. 1B, access device108would be removed for the embodiment ofFIG. 1C, and in an inverse cell embodiment for the embodiment ofFIG. 1C, base region122would be next to a cathode, namely a cathode region121, and would be a p-base. However, for purposes of clarity by way of example and not limitation, it shall be assumed that base region122is next to an anode region121and is an n-base. In other words, for purposes of clarity by way of example and not limitation, it shall be assumed that node109is a cathode and node107is an anode, even though in other embodiments these nodes may have reverse functions.

Such an array of memory cells200may be used in DRAM or DRAM-like applications, where access devices are generally for multiple memory cells, such as a row or column of memory cells, of the array. However, for purposes of clarity by way of example and not limitation, it shall be assumed that a memory device includes an access device108even though in other embodiments such a memory device may not include an access device108.

FIG. 2Ais a top elevation view depicting a portion of a SOI wafer (“SOI portion”)170. Even though the example of an SOI wafer is used, it should be appreciated that other types of semiconductors, other than silicon, and other types of dielectrics, other than oxide, may be used provided contaminants may be mobilized in such other types of semiconductors and generally do not diffuse in such other types of dielectrics. Furthermore, while an entire SOI wafer may be used in the formation of semiconductor integrated circuit die as described herein, only a portion of such wafer is described herein for purposes of clarity and not limitation. SOI portion170may be used for forming an array of thyristor-based memory cells, whether as a stand-alone integrated circuit or as an embedded array in a host integrated circuit. While an exemplary embodiment of an array of thyristor-based memory cells is used, it should be understood that the scope of application for the description herein is for any SOI integrated circuit having leakage and/or yield sensitivity issues due to “contaminants.” For purposes of clarity and unless otherwise contextually or expressly indicated otherwise, the term “contaminants” as used herein singly and collectively refers to contaminants and/or crystalline defects. SOI portion170has a top surface on which a mask160is formed. Mask160may be formed using known lithography technology to define regions for dummy structures, described below in additional detail.

Tiles may be formed to facilitate planar polishing when using a type of technology known as chemical-mechanical polishing (“CMP”). CMP of a semiconductor wafer may be purely a chemical, purely a mechanical, or a combination of a chemical and a mechanical polishing. Such polishing generally substantially planarizes a wafer surface, subject to tile deflection. To mitigate against what is known as “CMP dishing,” dummy structures (“tiles”) are formed using SOI portion170.

Implant209is used to create damage regions in what will be defined as tiles201as indicated by dashed lines, as described below in additional detail. Examples of the type of defects of damage regions include point/crystalline defects, and an agglomeration of one or more of these types of defects. Such defect sites facilitate trapping of contaminants. By silicon point defects, it is generally meant vacancies and interstitials in lattice structure of silicon crystalline. Such point defects may adversely affect device characteristics.

Point defects may be mid-gap states and may increase junction leakage in a manner which is generally electrically equivalent to junction leakage increased due to metallic contamination. It should be understood that defects created by a damage implant include silicon point defects. Furthermore, it should be understood that damage regions may getter silicon point defects, including silicon point defects previously located in the device active regions. While not wishing to be bound by theory, it is believed that the reason implant damaged regions replete with point defects can getter other point defects with a high temp anneal is that the implant-created point defects will first quickly agglomerate into larger line defects, which are more stable and much less able to diffuse away. These line defects continue to agglomerate by acting as a diffusive sinks for other point defects from adjacent active device regions.

In order for the damage regions to sink point defects, however, relatively high diffusion temperatures may be used, such as in the range of approximately 800 to 1100° C., to first form defect clusters and then allow diffusion of point defects to the defect clusters. The exact temperature used depends on the proximity of a damaged region to a point defect site and the time allowed for defect diffusion. Diffusion length is generally proportional to the square root of a “diffusion constant,” D, multiplied by time allowed for such diffusion. The diffusion constant, D, is a function of temperature.

While damage regions may be used to getter mobile contaminants (e.g., metallic contaminants) with some thermal energy, if such damage regions receive enough thermal energy to form defect clusters, then such damage regions may act as sinks for silicon point defects. Accordingly, damage regions may be used to getter mobile contaminants and silicon point defects.

Implant209may be a heavy ion implant. Examples of ions that may be used to create defect sites include silicon, germanium, carbon, and xenon, among other types of ions that may be used to create damage regions in tiles201. It should be appreciated that tiles201are implanted in this embodiment with implant209prior to formation of any active regions of one or more integrated circuits formed using SOI portion170and prior to etching a silicon layer to define tiles201.

Referring toFIG. 2B, there is shown the top elevation view ofFIG. 2A, indicating with dashed lines where active regions (“active stripes”)161are to be formed by etching responsive to a patterned masking layer (not shown). Accordingly, it should be appreciated that tiles201are separated from active regions161, as generally indicated by expanses163. Contaminants202may already exist in a silicon layer, such as silicon layer140ofFIG. 1B, of an SOI portion170, or may result from subsequent handling or semiconductor processing of SOI portion170. Thus, prior to etching, such as shallow-trench isolation (“STI”) etching, of SOI portion170to define stripes161, and possibly tiles201at the same time, in order to mitigate any negative effects from such contaminants, contaminants202may be gettered, namely attracted to gettering regions formed in SOI portion170, as described in additional detail with reference toFIG. 2Cbelow.

InFIG. 6, there is shown a top elevation of an SOI portion170for implantation209ofFIG. 2A.FIG. 6depicts an alternative embodiment to the embodiment illustratively shown inFIG. 2A. In this embodiment, locations for tiles201and dummy stripes161D are implanted at the same time by damage implant209. A patterned masking layer198having openings for tiles201and dummy stripes161D may be used to for implant209. Thus, it should be understood that masking layer198covers active stripes161for protection from implant209, and exposes dummy stripes161D and tiles201for implantation via implant209. Optionally regions between stripes161D and161, as well as regions between stripes161, may be uncovered by masking layer198, namely exposed to implantation via implant209. Outer located stripes161D of an array of stripes161are used as dummy stripes. Formation of such dummy stripes161D may be either or both dummy rows or columns even though only one orientation is illustratively depicted for purposes of clarity. Dummy stripes161D may be added, such as at the outer edges of an array of memory cells or memory devices, to promote uniformity of array patterning, to provide a fixed electrical boundary for memory cells or devices at the outer regions of an array, and to provide an additional location for attracting contaminants; the last of these is described below in additional. Again, contaminants is as defined above.

Mask198may be any masking material sufficient to protect active stripes161thereunder from damage by implant209. However, locations for dummy stripes161D and tiles201are exposed to damage implant209, and thus damage implant209creates damage regions in dummy stripes161D and tiles201at the same time. Contaminants202are illustratively shown for purposes of clarity; however, it should be understood that such contaminants202are covered by mask198. Again, contaminants is as defined above. Subsequently, in this embodiment, tiles201and stripes161and161D may be formed at the same time with a masking layer, other than masking layer198, and an STI etch.

FIG. 2Cis the top elevation view ofFIG. 2Bafter gettering of contaminants202and depositing and patterning a mask166. Again, contaminants is as defined above. Mask166is for covering tiles201, and stripes161and161D for subsequent etching to provide a profile as illustratively depicted inFIG. 2Dafter removal of mask166. Some contaminants202are gettered to tiles201, while other contaminants202, though not reaching tiles201, are drawn away from locations for active stripes161. Some contaminants202may be drawn or trapped in dummy stripes161D ofFIG. 6; however, for purposes of clarity and not limitation, the embodiment ofFIG. 2Cis further described without reference to one or more dummy stripes. However, it should be understood that the following description is applicable to embodiments with or without one or more dummy stripes161D.

Referring back toFIG. 2A, an implant209is used to create damage regions in tiles201. While not wishing to be bound by theory, it is believed that contaminants, as well as defects as described above, are trapped by defects created with implant209. As gettering of point defects was described above, the following description is for trapping of contaminants; however, it should be understood that gettering of point defects may occur along with trapping of contaminants. Trapping of contaminants causes a localized depletion of contaminants, which is believed to drive a contaminant diffusion process toward defects. Such a contaminant diffusion process may continually trap incoming mobile contaminants in or by such defects. Generally, contaminants are mobile at elevated temperatures. The rate of diffusion of contaminants may generally be said to depend on the type of contaminants and exponentially depend on temperature.

Those contaminants202not reaching tiles201may be drawn far enough away from locations for active stripes161so as to be removed when silicon layer140ofFIG. 1Bis etched, as described below in additional detail. A mask, such as mask166, may be used to mask off top surface areas of tiles201and stripes161/161D for subsequent etching.

It should be appreciated that in an SOI wafer, some contaminants do not diffuse through or diffuse so slowly through the BOx layer, such as BOx layer130ofFIG. 1Bfor example, so as to be effectively confined to silicon layer140. Gettering such contaminants away from active regions, such as active stripes161, may improve yield.

FIG. 2Dis a cross-section of SOI portion170after STI etching of an SOI wafer, including SOI portion170, responsive to mask166. The cross-section ofFIG. 2Dis along line A1-A2as illustratively shown inFIG. 2C. Tiles201are formed of silicon layer140, and as such may extend from an upper surface of such silicon layer140down to an upper surface of BOx layer130. Contaminants202trapped in defect sites, such as defect site212for example, of tiles201remain with SOI portion170, while contaminants drawn away from active stripes161into etch-exposed regions of silicon layer140are removed as part of etching to form trench isolation regions, including STI regions between active stripes161.

Referring toFIG. 2E, there is shown the cross-sectional view ofFIG. 2Dafter an STI fill of an SOI wafer, including SOI portion170. STI trenches may be filled with one or more dielectric layers. A liner layer may be deposited followed by one or more other dielectric layers for such STI trench filling. However, at least one dielectric layer211may be used to laterally electrically isolate active stripes161from one another, and may be used to laterally. Formation of at least one dielectric layer211further creates a physical barrier to prevent or at least inhibit contaminants202in tiles201from laterally migrating or diffusing back to active stripes161. Again, BOx layer130prevents such contaminants202from diffusing to a substrate or handle layer120. Thus, at least one dielectric layer211may be used to prevent or at least inhibit lateral diffusion of such contaminants202from tiles201to active stripes161.

FIG. 2Fis the cross-sectional view ofFIG. 2Eafter CMP of an SOI wafer, including SOI portion170. Contaminants202remain trapped in tiles201and are isolated from diffusion to active stripes161by dielectric layer211and BOx layer130. Thus, it should be appreciated that by gettering contaminants202away from active stripes161, yield may be enhanced, as contaminants diffuse from active regions and may be trapped in tiles201.

FIG. 3Ais a top elevation view depicting an alternative exemplary embodiment of SOI portion370A. In contrast toFIG. 2A, tile extension regions are formed around the perimeter of each of tiles201, namely perimeter damage regions301. In this embodiment, implant309may used to create perimeter damage regions301around what will later be defined as tiles201. Mask360has openings defining upper surface areas of damage regions301. Mask360in this embodiment covers locations of tiles201; however, mask360may alternatively leave locations of tiles201exposed. Thus, contaminants202which may be gettered toward tiles201may be first trapped in defect sites of perimeter damage regions301. Implant309may use the same heavy ions as described previously with reference to implant209ofFIG. 2A. Active stripes161may be subsequently formed, as described above.

FIG. 3Bis a top elevation view of yet another exemplary embodiment of SOI portion370B. In this embodiment, defect sites have been formed in damage regions302by a heavy ion implant, such as implant309. Location of tiles201is shown with dashed lines, to reference position of damage regions relative to where tiles201will be formed. However, in this embodiment, a patterned masking layer361is used to define damage regions302. Masking layer361is to define damage regions302between tiles201and where active stripes161will be formed. Active stripes161may be subsequently formed, as described above.

Whether the embodiment ofFIG. 3Aor3B, or a combination thereof, is used, it should be appreciated that damage regions301and302may be removed, as they need not be used to avoid dishing during CMP. Accordingly, after trench etching, SOI portion170ofFIG. 3Aor3B may result in the cross-section as illustratively shown with reference toFIG. 2D. Damage regions301and302are removed with STI etching, unlike damage regions212ofFIG. 2D, for example, which stay put in tiles201during and after STI etching. Contaminants202, which may be trapped in damage regions301or302, may be removed using such STI etching, and thus the likelihood of such contaminants202contaminating active regions of SOI portion170is substantially reduced, as any contaminants201trapped in such regions would be removed and thus would not be available to diffuse out of defect sites in such damage regions301and302. Moreover, with reference to the embodiments ofFIGS. 2A,3A,3B,6, or any combination thereof, it should be appreciated that although a single layer of tiles or damage regions is illustratively shown, subsequent tiles or damage regions may be generally stacked upon previously formed tiles or damage regions, or locations associated therewith.

For contaminants to have diffusive mobility, thermal energy is used. This thermal energy may result from one or more semiconductor processing steps to form one or more portions of an integrated circuit, including thyristor-based memory cells, using an SOI wafer. Thermal cycling of sufficient temperature and time for gettering contaminants may result from an additional anneal or subsequent processing, as described below in additional detail.

FIG. 4, collectivelyFIGS. 4-1through4-3, is a flow diagram depicting an exemplary embodiment of a process flow for forming an array of thyristor-based memory cells.FIG. 4is described in part with reference toFIG. 5, where there is shown a cross-sectional diagram depicting an exemplary embodiment of a portion of a thyristor-based memory cell500having contaminant gettering regions501and502. InFIG. 5, gate dielectrics, spacers, gate electrodes, and gate contacts are not illustratively indicated for purposes of clarity and not limitation.

Regions formed in silicon layer140that are illustratively shown with dotted lines, including extension regions131and132for example, are to indicate that these regions are not necessarily formed prior to forming contaminant gettering regions501and502. Furthermore, contacts106and107are shown with dashed lines to indicate the general proximity of contacts106and107to contaminant gettering regions501and502, respectively, but such contacts106and107are formed after formation of gettering regions501and502.

In the following description, for purposes of clarity by way of example and not limitation, particular numerical examples are used. However, it shall be appreciated by those of ordinary skill in the art that other numerical examples may be used, as may vary from application to application. Moreover, although the example of a thyristor-based memory cell process flow portion is used, it will be appreciated by those of ordinary skill in the art that any integrated circuit formed using an SOI wafer may be used.

At401, an SOI wafer is obtained. At402, a pad oxide is formed on an upper surface of the SOI wafer obtained. This pad oxide may be thermally grown or deposited.

At403, a mask layer, such as resist mask160ofFIG. 2A, is formed over the pad oxide to define locations for a damage implant associated with locations for tiles. For purposes of clarity, it shall be assumed that dummy stripes are not used. However, it should be understood from the description herein that dummy stripes may be used with modification to flow400in accordance with the above description ofFIG. 6.

At404, a heavy ion implant is used to generate defect sites (“defects”) responsive to the mask layer formed at403. The type of ion that may be used includes xenon, germanium, and carbon ions, among other heavy ions.

At405, such mask layer formed at403is removed, and a high temperature anneal is performed, not necessarily in this order. The anneal is of a sufficiently high temperature to mobilize contaminants. Conventionally, mobility of metal ions, namely metal contaminants, involves temperatures equal to or greater than approximately 450 degrees Celsius. More thorough gettering owing to greater mobility of metal ions may occur due to thermal cycling at approximately 600 degrees Celsius or more, or for longer durations of time, or a combination thereof. Such mobile contaminants generally laterally diffuse and are attracted to defects caused by the implant at404. Once the temperature of silicon layer140is generally sufficiently low, such as below the approximately 250 degrees Celsius value, contaminants, which are no longer mobile, are located in or at least proximate to defects. For example, silicon layer140may be allowed to cool to an ambient temperature, such as room temperature.

At406, a mask layer, such as a hardmask layer, is deposited and patterned over the pad oxide to define active regions and thereby define STI trenches. At407, STI trenches and other areas are etched down to an upper surface of a BOx layer. Operations at406and407may involve some thermal cycling; however, even if contaminants are mobilized by these operations, such contaminants generally will remain trapped in or nearby defects and those contaminants not already trapped may become trapped due to such additional mobilization. At407, tiles, such as tiles201and stripes161ofFIG. 2D, may be formed. At408, such STI trenches are filled using one or more dielectric layers, which may include a liner layer as well as other types of STI fills.

At409, the SOI wafer is polished along an upper surface using CMP. The hardmask may be left in place for a stop-on nitride CMP. At410, top and bottom (“front and back”) surfaces of the SOI wafer may be cleaned. At411, the hardmask formed at406may be removed. For a nitride hardmask, a hot phosphoric acid dip may be used to remove the nitride hardmask without removing a significant amount of the pad oxide.

At412, a sacrificial oxide is formed. This sacrificial oxide may be used to remove dislocations in the active silicon layer caused by stress induced by the nitride hardmask and may be used as a buffer for a well implant.

Optionally, at413, additional gettering regions may be formed.FIG. 7is a more detailed flow diagram of operations for forming additional gettering regions at413.

At413A, a masking layer may be formed using a contact vias mask. The contact vias for contacts106and107are proximate to the locations for gettering regions501and502within an array of thyristor-based memory cells. Thus, masking layer510may be formed using the same mask used to form contact vias for contacts106and107for forming gettering regions501and502. For example, gettering region502may be associated with a common anode/cathode contact, and gettering region501may be associated with a common bitline/wordline contact. Accordingly, although part of only one memory cell is illustratively shown inFIG. 5, it should be appreciated from the prior description that an entire array of memory cells may be formed.

In an embodiment, every possible contact for an array of thyristor-based memory cells has a gettering region. In another embodiment, not every possible contact for an array of thyristor-based memory cells has a gettering region. Thus, only a portion of the contacts, whether common bitline/wordline contacts or common anode/cathode contacts, or a combination thereof, may be have associated therewith contaminant gettering regions501and502. More particularly, if there were sensitive areas in an array of memory cells, where such memory cells were more sensitive to contaminants than in other regions of an array, contaminant gettering regions501or502or a combination thereof, may be targeted for formation only in such sensitive areas, and not elsewhere within an array of thyristor-based memory cells. Thus, even though the same contact mask used to form contact vias may be used to define contaminant gettering regions501and502, masking layer510may alternatively be formed using a mask that is a variation of the via contact mask, namely a mask that defines a subset of contact vias for forming either or both types of contaminant gettering regions501and502.

Although formation of contaminant gettering regions501and502responsive to a mask used to form contact vias is described in terms of an array of thyristor-based memory cells, it should be appreciated that contact vias exist in other types of memory arrays, as well as outside of memory arrays. More generally, contact vias exist throughout integrated circuits. Accordingly, gettering regions501and502are merely examples of gettering regions that may be formed anywhere in an integrated circuit of any type of integrated circuit having contact vias that extend to a contact region in an active silicon layer of an SOI wafer.

At413B, a heavy ion implant may used to generate defect sites responsive to mask layer510. Accordingly, contaminant gettering regions501and502are formed. Ions that may be used for such heavy ion implant include xenon, germanium, or carbon ions, among other heavy ions. The implant energy may be targeted to the middle of active silicon layer140. It should be appreciated that the single crystalline silicon of silicon layer140may be implanted to form defect regions in gettering regions501and502by the implant at413B. At413C, the masking layer formed may be removed.

At413D, an optional anneal may be performed to enhance gettering of defects and contaminants. However, the heat induced by anneal413D may be sufficiently high to cause causes mobility of contaminants in an SOI wafer. Accordingly, the defect sites in gettering regions501and502attract such mobile contaminants and defects, as described above. The thermal cycling may cause defect regions of gettering regions501and502to trap contaminants and defects gettered to those regions501and502. Boundaries between gettering regions501and502and their respective contact regions, such as for example bitline access region123and anode region121respectively, generally prevent reunification of silicon layer140into a unitary single crystalline layer. In other words, there may be dislocations along boundaries503. However, other thermal cycling by other processing subsequent to the damage implant at413B may have an effect on mobilizing contaminants and some defects. Such other processing, for example, may include a well anneal after well implants at414, or deposition of a gate dielectric at418, or a source/drain anneal at429. Thus, thermal cycling may mobilize contaminants and some defects, while generally allowing at least the more stable defects in gettering regions to remain.

Forming a sacrificial oxide protects channel regions of silicon layer140from a subsequent well implant. In other words, a subsequent well implant may cause unwanted damage to the crystalline structure of the silicon layer140in proximity to where a gate oxide may be formed. To avoid or minimize this damage, the optional enhanced sacrificial oxide formed at413D may be used. For purposes of clarity by way of example and not limitation, it shall be assumed that optional operation413is employed, even though such optional operation may be omitted in other embodiments.

Returning toFIG. 4, at414, one or more implants are used to form wells, such as base region141and access device body region142. Well implants may be prone to generate metal contaminants. Accordingly, at415the same contact via mask used at413A, or a variation of the contact mask, may be used. However, for purposes of clarity by way of example and not limitation, it shall be assumed that the same contact via mask is used. For example, for an array of thyristor-based memory cells having approximately 8 megabits with common anode and bitline contacts, there may be approximately 8 million gettering regions formed in the array. At416, the implant used at413B may be repeated to generate or regenerate defects in gettering regions501and502. At417, the masking layer formed at415and the sacrificial oxide may be removed. A buffered oxide etch (“BOE”) may be used to remove the sacrificial oxide.

At418, a gate oxide may be formed. The gate oxide may be thermally formed from exposed portions of an upper surface, and to a limited extent below such surface of such exposed portions, of silicon layer140. The thermal cycling involved in forming a gate oxide may cause metal contaminants to be mobile for diffusing to gettering regions501and502, as previously described. The metal contaminants attracted to defect regions are trapped.

For a dual gate thickness for forming thyristor-based memory cells, a dual gate oxide mask is formed at419. After formation of such mask, an exposed portion of the gate oxide formed at418is removed using an oxide dip at420. Basically, the gate oxide is removed from FET areas where access transistors of memory devices are located. Again, it has been assumed that an access device is present for memory devices; however, it should be understood as indicated above that a memory cell need not include an access device as part of such cell. BOE or oxide dip may be used for removing gate oxide in those FET areas.

At421, a thermal oxide is grown for the FET gates. The mask formed at419may be used to mask this thermal oxidation.

At422, polysilicon is deposited, doped, and patterned and a sealing oxidation is applied. At423, extension implants, such as a lightly doped drain (“LDD”) and a halo implant, may be used to form extension regions131and132. At424, spacer deposition is applied to form spacers alongside walls of the polysilicon gates. Additionally, at424a mask to form spacer149ofFIG. 1Bmay be used, namely a spacer that extends in part above a portion of the polysilicon gate of the storage element of the thyristor-based memory cells. Alternatively, deposition for formation of a salicide block149may be performed at a later time in flow400. As such formation of salicide block149is well-known, it is not described in unnecessary detail herein.

At425, a spacer etch is used to remove unwanted spacer material deposited at423. At426, source/drain implants may be used to form regions109,121,122, and123. There may be masking involved for these implants, which is not described herein for purposes of clarity.

At427, the mask used at413A, as well as at415, may be reapplied for forming openings for implantation to generate or regenerate defects in contaminant gettering regions501and502. At428, the implant previously used at413B, as well as at416, may be used to generate or regenerate defects in contaminant gettering regions501and502.

At429, a source/drain anneal may be done. The source/drain anneal thermally cycles the SOI wafer, including memory cell500, making the metal contaminants mobile. The mobile metal contaminants are attracted to the defect sites in gettering regions501or502. Once thermal cycling is complete, gettering regions501and502trap metal contaminants attracted thereto. Thereafter, the array of thyristor-based memory cells may be formed as is known, and such details are omitted for purposes of clarity.

Thus, it should be appreciated that within the process flow for forming an array of thyristor-based memory cells, there may be depositing a masking layer, patterning the masking layer, and performing a heavy ion implant to generate or regenerate defect sites in contaminant gettering regions501and502, or at least one type thereof, whether at the bitline contact, wordline contact, cathode contact, or anode contact, or a combination thereof of a memory cell. Although multiple separate maskings and implantings were described, any one or any combination of two or more of these implantings may be used. For example, only one or two of such maskings and implantings may be implemented. Additionally, as well implants tend to be metal contaminant-prone, one or more maskings and implantings after414may be used to capture contaminants associated with well implants.

FIG. 8is a top elevation view depicting an alternative exemplary embodiment of SOI portion870A. In contrast toFIG. 3A, damage regions are formed within the perimeter of each of tiles201, namely interior damage regions802. In this embodiment, implant309may used to create damage regions802completely within an interior region what will later be defined as tiles201. Some possible reasons for not having damage regions802extend to the edges of tiles201are for example to reduce the potential for contaminating an etcher or subsequent cleaning baths.

Mask360has openings defining upper surface areas of damage regions802. Mask360in this embodiment covers perimeter and partially inward locations of tiles201. Thus, contaminants202may be gettered toward damage regions802and may be trapped in defect sites thereof. Implant309may use the same heavy ions as described previously with reference to implant209ofFIG. 2A.

If both etcher and cleaning bath contamination is not a problem, then arbitrary placement of damaged regions in the field may be used. This means that damage implant309may or may not coincide with tiles201or dummy stripes161D; rather, damage regions from implant309may be located anywhere there is not an active device, such as anywhere in an STI region or STI regions. In an embodiment, damaged regions may be spaced away from active regions for when diffusion of contaminants, or point defects, is not complete, namely such contaminants do not all diffuse all the way to the damage regions.

As previously indicated, diffusion involves use of thermal energy. While not wishing to be bound by theory, it is believed that defects, such as those in damage regions, may atomically bind metallic contaminants, and the force driving contaminant movement to such defects is diffusion, with or without any ionic attraction of such metallic contaminants to such defects.