BACK END OF LINE RESISTOR STRUCTURE

The present disclosure describes a resistor structure with a dielectric layer, trenches, a metal layer, a semiconductor layer, and an insulating layer. The dielectric layer is disposed above electrical components formed on a substrate. The trenches are disposed in the dielectric layer and separated from each other by a dielectric region of the dielectric layer. The metal layer is disposed on a bottom surface and side surfaces of each of the trenches and on a top surface of the dielectric region. The semiconductor layer is disposed on a bottom surface, side surfaces, and a top surface of the metal layer. The insulating layer is disposed in the trenches and in contact with side surfaces of the semiconductor layer and on a top surface of the semiconductor layer.

BACKGROUND

With advances in semiconductor technology, there have been increasing demands for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the dimensions of circuit elements, such as active devices (e.g., planar metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors (finFETs), and gate-all-around field-effect transistors (GAAFETs)) and passive devices (e.g., capacitors, inductors, and resistors). As the number of circuit elements increases, implementation of these circuit elements becomes increasingly more complex.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are merely examples and are not intended to be limiting. In addition, the present disclosure repeats reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and, unless indicated otherwise, does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

With advances in semiconductor technology, there have been increasing demands for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the dimensions of circuit elements, such as active devices (e.g., MOSFETs, finFETs, and GAAFETs) and passive devices (e.g., capacitors, inductors, and resistors). As the number of circuit elements increases, implementation of these circuit elements becomes increasingly more complex.

The present disclosure describes semiconductor structures and methods to form resistor structures in a back end of line region of a semiconductor device (e.g., interconnect structures disposed above a substrate of the semiconductor device). The resistor structure can include a dielectric layer, trenches, a metal layer, a semiconductor layer, and an insulating layer. The dielectric layer is disposed above electrical components formed on a substrate. The trenches are disposed in the dielectric layer and separated from each other by a dielectric region of the dielectric layer. The metal layer is disposed on a bottom surface and side surfaces of each of the trenches and on a top surface of the dielectric region. The semiconductor layer is disposed on a bottom surface, side surfaces, and a top surface of the metal layer. The insulating layer disposed in the plurality of trenches and in contact with side surfaces of the semiconductor layer and on a top surface of the semiconductor layer. A benefit, among others, of implementing the resistor structure in the back end of line region of the semiconductor device is that that the back end of line region can be utilized for the fabrication of passive devices—e.g., resistor structures-thus increasing available area on the substrate for the implementation of additional active devices and/or passive devices to enhance the functionality and performance of the semiconductor device.

FIG.1is an illustration of a cross-sectional view of a semiconductor device100, according to some embodiments of the present disclosure. Semiconductor device100can be a central processing unit, a graphics processing unit, an application-specific integrated circuit, or any other suitable electronic device. In some embodiments of the present disclosure, semiconductor device100can include a substrate110, a device region120, and a back end of line region130.

Substrate110can include a semiconductor material, such as crystalline silicon (Si). In some embodiments of the present disclosure, substrate110can include (i) an elementary semiconductor, such as germanium (Ge); (ii) a compound semiconductor, such as silicon carbide (SiC), silicon arsenide (SiAs), gallium arsenide (GaAs), gallium phosphide (GaP), and/or a III-V semiconductor material; (iii) an alloy semiconductor, such as silicon germanium (SiGe), silicon germanium carbide (SiGeC), germanium tin (GeSn), and/or aluminum gallium arsenide (AlGaAs); (iv) a silicon-on-insulator (SOI) structure; (v) a silicon germanium (SiGe)-on insulator structure (SiGeOI); (vi) a germanium-on-insulator (GeOI) structure; or (vii) a combination thereof. Alternatively, substrate110can be made from an electrically non-conductive material, such as glass and a sapphire wafer. Further, substrate110can be doped depending on design requirements (e.g., p-type substrate or n-type substrate). In some embodiments of the present disclosure, substrate110can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic).

Device region120can be disposed on substrate110. In some embodiments of the present disclosure, device region120can include electrical components, such as active devices, passive devices, or a combination thereof. Examples of the active devices can include planar MOSFETs, finFETs, GAAFETs, and nanostructure transistors (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, and nano-ribbon transistors). Device region120can include one or more of these different types of active devices, which can be separated from one another using shallow trench isolation, deep trench isolation, local oxidation of silicon, any other suitable isolation technique, or a combination thereof. Examples of the passive devices can include resistors, capacitors, and inductors. Device region120can also include one or more of these different types of passive devices. In some embodiments of the present disclosure, a combination of the active devices and the passive devices in device region120can form one or more electronic circuits, such as a central processing unit, a graphics processing unit, an application-specific integrated circuit, any other suitable electronic circuit, and portions thereof.

Referring toFIG.1, back end of line region130is disposed above device region120(e.g., in a y direction) and can include a first interconnect region131, a second interconnect region132, and a third interconnect region136, according to some embodiments of the present disclosure. First interconnect region131can include one or more interconnect structures—e.g., metal line structures and metal via structures—disposed in an interlayer dielectric structure (not shown inFIG.1). The metal line structures and metal via structures can include copper (Cu), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or any other suitable conductive material. The interlayer dielectric structure can include a dielectric material, such as silicon oxide (SiOx), silicon hydroxide (SiOH), silicon oxynitride (SiON), silicon nitride (SiNx), silicon oxycarbide (SiOC), silicon oxynitricarbide (SiOCN), and a combination thereof. The interlayer dielectric structure can include a stack of dielectric layers to implement multiple layers of interconnect structures. The one or more interconnect structures in first interconnect region131can electrically connect to the electrical components in device region120(e.g., active devices, passive devices, or a combination thereof).

Referring toFIG.1, second interconnect region132is above first interconnect region131(e.g., in a y direction) and can include a passive device region133and a metal via structure134—both disposed in an interlayer dielectric structure135—according to some embodiments of the present disclosure. Metal via structure134can electrically connect interconnect structures in first interconnect region131to interconnect structures in third interconnect region136. Although not shown inFIG.1, second interconnect region132can also include metal line structures and other metal via structures. The metal line structures and metal via structures (including metal via structure134) can include Cu, Al, TiN, TaN, W, or any other suitable conductive material. Interlayer dielectric structure135can include a dielectric material, such as SiOx, SiOH, SiON, SiNx, SiOC, SiOCN, and a combination thereof. Interlayer dielectric structure135can include a stack of dielectric layers to implement multiple layers of interconnect structures.

In some embodiments of the present disclosure, passive device region133can include one or more resistor structures. The one or more resistor structures can each be a deep trench resistor, according to some embodiments of the present disclosure. A benefit, among others, of implementing resistor structures in passive device region133is that back end of line region130can be utilized for the fabrication of passive devices—e.g., resistor structures—thus increasing available area in device region120for the implementation of additional active devices and/or passive devices to enhance the functionality and performance of semiconductor device100. Though the description below is in the context of resistor structures (e.g., deep trench resistors), other types of passive devices (e.g., capacitor structures and inductor structures) can be implemented in passive device region133.

Referring toFIG.1, third interconnect region136is above second interconnect region132(e.g., in a y direction) and can include one or more interconnect structures disposed in an interlayer dielectric structure138. The interconnect structures can include metal line structures137and metal via structures (not shown inFIG.1). The metal line structures and metal via structures can include Cu, Al, TiN, TaN, W, or any other suitable conductive material. The interconnect structures in third interconnect region136can electrically connect to the electrical components in device region120through metal via structure134(and other metal via structures not shown inFIG.1) and interconnect structures in first interconnect region131. Interlayer dielectric structure138can include a dielectric material, such as SiOx, SiOH, SiON, SiNx, SiOC, SiOCN, and a combination thereof. Interlayer dielectric structure138can include a stack of dielectric layers to implement multiple layers of interconnect structures. Although three layers of metal line structures137are shown in third interconnect region136, third interconnect region136can have more or less than three layers of metal line structures, depending on the design of semiconductor device100.

FIG.2is an illustration of a cross-sectional view of a portion200of semiconductor device100, according to some embodiments of the present disclosure. Portion200includes substrate110, device region120, and first interconnect region131. Although not shown inFIG.2, second interconnect region132and third interconnect region136are disposed above first interconnect region131as shown inFIG.1.

Device region120can include active devices210implemented within and/or on substrate110. Active devices210can include one or more of MOSFETs, finFETs, GAAFETs, and nanostructure transistors (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, and nano-ribbon transistors), according to some embodiments of the present disclosure. Active devices210can be separated from one another using shallow trench isolation, deep trench isolation, local oxidation of silicon, other suitable isolation techniques, or a combination thereof. In some embodiments of the present disclosure, active devices210can represent portions of a central processing unit, a graphics processing unit, an application-specific integrated circuit, or any other suitable electronic device. Further, although not shown in FIG.2, device region120can also include passive devices (e.g., resistors, capacitors, and inductors) implemented within and/or on substrate110.

In some embodiments of the present disclosure, first interconnect region131can include interconnect structures—e.g., metal line structures220and metal via structure134—disposed in interlayer dielectric structure221. Metal line structures220and metal via structure134can electrically connect to the active devices and/or the passive devices in device region120(e.g., active devices210) such that these electrical components can electrically connect to one another and/or to upper interconnect structures (e.g., interconnect structures in second interconnect region132and in third interconnect region136—not shown inFIG.2). Although not shown inFIG.2, first interconnect region131can also include other metal via structures. The metal line structures and metal via structures (including metal via structure134) can include Cu, Al, TiN, TaN, W, or any other suitable conductive material. Interlayer dielectric structure221can include a dielectric material, such as SiOx, SiOH, SiON, SiNx, SiOC, SiOCN, and a combination thereof. Interlayer dielectric structure221can include a stack of dielectric layers to implement multiple layers of interconnect structures.

FIG.3is an illustration of another cross-sectional view of a portion300of semiconductor device100, according to some embodiments of the present disclosure. Although not shown inFIG.3, second interconnect region132and third interconnect region136are disposed above first interconnect region131as shown inFIG.1, according to some embodiments of the present disclosure.

Portion300includes substrate110, device region120, and first interconnect region131. Device region120can include a backside interconnect region310and device region320, according to some embodiments of the present disclosure. In some embodiments of the present disclosure, backside interconnect region310is below device region120(e.g., in a y direction). Backside interconnect region310can include interconnect structures (e.g., as part of a redistribution layer network of interconnect routings) disposed in an interlayer dielectric structure317and arranged to provide a power supply voltage to electrical components in device region320. Interlayer dielectric structure317can include a dielectric material, such as SiOx, SiOH, SiON, SiNx, SiOC, SiOCN, and a combination thereof. Interlayer dielectric structure317can include a stack of dielectric layers to implement multiple layers of interconnect structures. Further, the interconnect structures can include metal line structures311,313,315, and316and metal via structures312and314electrically connected to one another and to a power supply source to provide a power supply voltage to device region320. Metal line structures311,313,315, and316and metal via structures312and314can include Cu, Al, TiN, TaN, W, or any other suitable conductive material.

Device region120can include active devices322disposed above substrate110(e.g., in a y direction), according to some embodiments of the present disclosure. In some embodiments of the present disclosure, as shown inFIG.3, active devices322can be GAAFETs electrically connected to backside interconnect region310and to first interconnect region131through metal contact structures321and metal contact structure323, respectively. In some embodiments of the present disclosure, active devices322can receive-through metal contact structures321—a power supply voltage from the interconnect structures in backside interconnect region310. Further, in some embodiments of the present disclosure, active devices322can receive—through metal contact structure323—a gate control voltage from interconnect structures in first interconnect region131. Metal contact structures321and323can include Cu, Al, TiN, TaN, W, or any other suitable conductive material.

In some embodiments of the present disclosure, the power supply voltage provided to device region120through backside interconnect structure310is different from a power supply voltage provided to other portions of semiconductor device100. For example, the power supply voltage provided to active devices322in device region120can require a higher power supply voltage than that provided to other portions of device region120. In some embodiments of the present disclosure, referring toFIGS.1and3, the power supply voltage to device region120can be provided by backside interconnect region310and the power supply voltage to the other portions of device region120can be provided by a power supply source electrically connected to second interconnect region132—which includes interconnect structures electrically connected to passive device region133.

Referring toFIG.3, active devices322can be other types of devices, such as MOSFETs, finFETs, nanostructure transistors (e.g., nanosheet transistors, nanowire transistors, multi-bridge channel transistors, and nano-ribbon transistors), and a combination thereof, according to some embodiments of the present disclosure. Active devices322be separated from one another using shallow trench isolation, deep trench isolation, local oxidation of silicon, other suitable isolation techniques, and a combination thereof. Further, although not shown inFIG.3, device region120can also include passive devices (e.g., resistors, capacitors, and inductors).

In some embodiments of the present disclosure, first interconnect region131can include interconnect structures—e.g., metal line structures331and332and metal via structures134and333—disposed in interlayer dielectric structure334. Metal line structures331and332and metal via structures134and333can electrically connect to the active devices and/or the passive devices in device region120(e.g., active devices322) such that these electrical components can electrically connect to one another and/or to upper interconnect structures (e.g., interconnect structures in second interconnect region132and in third interconnect region136—not shown inFIG.3). The metal line structures and metal via structures can include Cu, Al, TiN, TaN, W, or any other suitable conductive material. Interlayer dielectric structure334can include a dielectric material, such as SiOx, SiOH, SiON, SiNx, SiOC, SiOCN, and a combination thereof. Interlayer dielectric structure334can include a stack of dielectric layers to implement multiple layers of interconnect structures.

FIG.4is an illustration of a cross-sectional view of a resistor structure400formed in passive device region133(ofFIG.1), according to some embodiments of the present disclosure. The cross-sectional view ofFIG.4shows second interconnect region132disposed on first interconnect region131. Although not shown inFIG.4, device region120and substrate110are disposed below first interconnect region131(e.g., in a y direction), as shown inFIG.1. Elements inFIG.4with the same annotations as elements inFIGS.1-3are described above.

Referring toFIG.4, first interconnect region131includes an etch stop layer432and a metal line structure434disposed in an interlayer dielectric structure436. Etch stop layer432can include a dielectric material, such as aluminum oxide (AlxOy), nitrogen doped silicon carbide (SiCN), oxygen doped silicon carbide (SiCO), and silicon nitride (SiN). Though not shown inFIG.4, in addition to metal line structure434, first interconnect region131can include other metal line structures and metal via structures—which can include can include Cu, Al, TiN, TaN, W, or any other suitable conductive material. Metal line structure434is electrically connected to one or more interconnect structures in second interconnect region132and to one or more active devices (e.g., planar MOSFETs, finFETs, GAAFETs, and nanostructure transistors) and/or passive devices (e.g., resistors, capacitors, and inductors) in device region120(ofFIG.1), according to some embodiments of the present disclosure.

Referring toFIG.4, second interconnect region132includes metal line structures446,447, and448, metal via structure449, and resistor structure400(in passive device region133) disposed in interlayer dielectric structure135, according to some embodiments of the present disclosure. Interlayer dielectric structure135is disposed above electrical components—e.g., active devices (e.g., planar MOSFETs, finFETs, GAAFETs, and nanostructure transistors), passive devices (e.g., resistors, capacitors, and inductors), or a combination thereof—in device region120(ofFIG.1), according to some embodiments of the present disclosure.

Metal line structure448and metal via structure449electrically connect other interconnect structures in second interconnect region132(and other interconnect structures above interconnect region132—not shown inFIG.4) to metal line structure434and other interconnect structures (not shown inFIG.4) in first interconnect region131. Metal line structures446and447are electrically connected to resistor structure400and electrically connect resistor structure400to one or more active devices (e.g., planar MOSFETs, finFETs, GAAFETs, and nanostructure transistors) and/or passive devices (e.g., resistors, capacitors, and inductors) in device region120(ofFIG.1) through interconnect structures disposed in first interconnect region131(not shown inFIG.4), according to some embodiments of the present disclosure. Though not shown inFIG.4, in addition to metal line structures446,447, and448and metal via structure449, second interconnect region132can include other metal line structures and metal via structures—which can include Cu, Al, TiN, TaN, W, or any other suitable conductive material.

In some embodiments of the present disclosure, resistor structure400in passive device region133is a deep trench resistor disposed in interlayer dielectric structure135. Resistor structure400includes trenches410, a metal layer441, a semiconductor layer442, an insulating layer443, a first contact structure444, and a second contact structure445. Trenches410are disposed in interlayer dielectric structure135and separated from each other by a dielectric region415of interlayer dielectric structure135. For example, resistor structure400includes three trenches410separated from each other by two dielectric regions415. Though three trenches410are shown inFIG.4, based on the description herein, more than or less than three trenches410can be implemented depending on a desired resistance value for resistor structure400.

Metal layer441is disposed on a bottom surface and side surfaces of each of trenches410and on a top surface of dielectric region415, according to some embodiments of the present disclosure. Metal layer441can include gold, platinum, chromium, titanium, tantalum, copper, silver, cobalt, nickel, iron, lead, aluminum, ruthenium, iridium, molybdenum, tungsten, or any other suitable material, according to some embodiments of the present disclosure. In some embodiments of the present disclosure, metal layer441can include ruthenium oxide, iridium oxide, titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum aluminum carbide, titanium aluminum nitride, tantalum aluminum nitride, or any other suitable material.

Semiconductor layer442is disposed on a bottom surface, side surfaces, and a top surface of metal layer441, according to some embodiments of the present disclosure. Semiconductor layer442can include silicon, germanium, silicon germanium, gallium nitride, indium nitride, indium gallium nitride, gallium arsenide, indium arsenide, indium gallium arsenide, indium gallium zinc oxide, copper oxide, indium zinc oxide, gallium zinc oxide, or any other suitable material. In some embodiments of the present disclosure, semiconductor layer442can include silicon germanium doped with boron or phosphorous or other doped materials.

In some embodiments of the present disclosure, metal layer441can be a substantially conformal layer disposed on the bottom surface and side surfaces of each of trenches410. Semiconductor layer442can be a substantially conformal layer-separate from the substantially conformal metal layer441—disposed on the bottom surface, side surfaces, and the top surface of metal layer441. A ratio of a thickness of semiconductor layer442to a thickness of metal layer441can be between about 0.1 and about 0.5, according to some embodiments of the present disclosure. In maintaining the ratio between about 0.1 and about 0.5, a temperature coefficient of resistance for resistor structure400approaches zero, according to some embodiments of the present disclosure. The temperature coefficient of resistance is a calculation of relative change in resistance per degree of temperature change, where a temperature coefficient of resistance of about zero indicates a small change in resistance (if any) over a temperature range. Though resistor structure400has a single layer of semiconductor layer442disposed on a single layer of metal layer441to form a single metal/semiconductor bi-layer, resistor structure400can have multiple metal/semiconductor bi-layers to adjust the temperature coefficient of resistance to a desired value (e.g., a value that approaches zero).

Insulating layer443is disposed in trenches410and is in contact with side surfaces of semiconductor layer442and a top surface of semiconductor layer442, according to some embodiments of the present disclosure. In some embodiments of the present disclosure, insulating layer443can include a dielectric material, such as AlxOy, SiCN, SiCO, and SiN.

First contact structure444is in contact with a portion of semiconductor layer442disposed over a first portion of interlayer dielectric layer structure135opposite to dielectric region415that separates adjacent trenches. Similarly, second contact structure445is in contact with another portion of semiconductor layer442disposed over a second portion of interlayer dielectric structure135opposite to another dielectric region415that separates adjacent trenches. In some embodiments of the present disclosure, first contact structure444and second contact structure445are in contact with terminals of resistor structure400—e.g., a current flowing through resistor structure400can flow from first contact structure444to second contact structure445—or vice versa.

Again, referring toFIGS.1and4, a benefit of implementing resistor structure400in passive device region133is that back end of line region130can be utilized for the fabrication of passive devices—e.g., resistor structure400—thus increasing available area in device region120for the implementation of additional active devices and/or passive devices to enhance the functionality and performance of semiconductor device100.

FIG.5is an illustration of a method500to form resistor structure400in a back end of line region130of semiconductor device100, according to some embodiments of the present disclosure. For illustrative purposes, the operations of method500will be described with reference toFIGS.6A-14A and6B-14B.FIGS.6A-14Aare top-level views andFIGS.6B-14Bare cross-sectional views of resistor structure400at various stages of fabrication, according to some embodiments of the present disclosure. The operations of method500can be performed in a different order or not performed depending on specific applications. It should be noted that method500may not produce a complete semiconductor device. Accordingly, it is understood that additional operations can be provided before, during, and after method500, and that some other processes may only be briefly described herein. Elements inFIGS.6A-14A and6B-14Bwith the same annotations as elements inFIGS.1-4are described above.

Referring toFIG.5, at operation510, an interlayer dielectric structure is formed above electrical components on a substrate. Referring toFIGS.6A and6B, interlayer dielectric structure135is formed above electrical components on the substrate. For example, referring toFIGS.1and4, etch stop layer432is a portion of first interconnect region131, which is disposed above device region120. Device region120can include electrical components, such as active devices (e.g., planar MOSFETs, finFETs, GAAFETs, and nanostructure transistors), passive devices (e.g., resistors, capacitors, and inductors), or a combination thereof. In some embodiments of the present disclosure, a combination of the active devices and the passive devices can form one or more electronic circuits, such as a central processing unit, a graphics processing unit, an application-specific integrated circuit, any other suitable electronic circuit, and portions thereof. Device region120is disposed on substrate110. Further, prior to the formation of interlayer dielectric structure135inFIGS.6A and6B, the active devices and/or passive devices in device region120and interconnect structures in first interconnect region131are formed, according to some embodiments of the present disclosure.

Referring toFIG.5, at operation520, trenches are formed in the interlayer dielectric structure, where the trenches are separated from each other by a dielectric region on the interlayer dielectric structure. Referring toFIGS.7A and7B, trenches410are formed in interlayer dielectric structure135by, for example, a photo pattern and etch process. In some embodiments of the present disclosure, height H410of each trench410(e.g., in a y direction) can be substantially equal to or less than a height of interlayer dielectric structure135. For example, height H410(or depth) can be between about 0.25 μm and about 3 μm—where the height of interlayer dielectric structure can be about 3 μm. In some embodiments of the present disclosure, a width W410of each trench (e.g., in a x direction) can be between about 50 nm and about 250 nm. Further, though three trenches410are shown inFIGS.7A and7B, based on the description herein, more than or less than three trenches410can be implemented depending on a desired resistance value for resistor structure400.

Referring toFIG.5, at operation530, a metal layer is formed on a bottom surface and side surfaces of each of the trenches and on a top surface of the dielectric region. Referring toFIGS.8A and8B, metal layer441is formed on a bottom surface and side surfaces of each of trenches410by, for example, a chemical vapor deposition process, an atomic layer deposition process, or any other suitable deposition process. In some embodiments of the present disclosure, metal layer441can be a substantially conformal layer with a thickness between about 5 nm and about 50 nm. Metal layer441can include gold, platinum, chromium, titanium, tantalum, copper, silver, cobalt, nickel, iron, lead, aluminum, ruthenium, iridium, molybdenum, tungsten, or any other suitable material, according to some embodiments of the present disclosure. In some embodiments of the present disclosure, metal layer441can include ruthenium oxide, iridium oxide, titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum aluminum carbide, titanium aluminum nitride, tantalum aluminum nitride, or any other suitable material.

Referring toFIG.5, at operation540, a semiconductor layer is formed on a bottom surface, side surfaces, and a top surface of the metal layer. Referring toFIGS.8A and8B, semiconductor layer442is formed on a bottom surface, side surfaces, and a top surface of metal layer441by, for example, a chemical vapor deposition process, an atomic layer deposition process, or any other suitable deposition process. In some embodiments of the present disclosure, semiconductor layer442can be a substantially conformal layer with a thickness between about 2 nm and about 10 nm. Semiconductor layer442can include silicon, germanium, silicon germanium, gallium nitride, indium nitride, indium gallium nitride, gallium arsenide, indium arsenide, indium gallium arsenide, indium gallium zinc oxide, copper oxide, indium zinc oxide, gallium zinc oxide, or any other suitable material. In some embodiments of the present disclosure, semiconductor layer442can include silicon germanium doped with boron or phosphorous or other doped materials.

Semiconductor layer442and metal layer441can both be substantially conformal layers with different thicknesses, where a ratio of a thickness of semiconductor layer442to a thickness of metal layer441can be between about 0.1 and about 0.5, according to some embodiments of the present disclosure. In maintaining the ratio between about 0.1 and about 0.5, a temperature coefficient of resistance for resistor structure400approaches zero, according to some embodiments of the present disclosure. Though resistor structure400has a single layer of semiconductor layer442disposed on a single layer of metal layer441to form a single metal/semiconductor bi-layer, resistor structure400can have multiple metal/semiconductor bi-layers-formed by multiple iterations of operations530and540—to adjust the temperature coefficient of resistance to a desired value (e.g., a value that approaches zero).

Referring toFIG.5, at operation550, an insulating layer is formed in the trenches and is in contact with side surfaces of the semiconductor layer and a top surface of the semiconductor layer. Referring toFIGS.9A and9B, insulating layer443is formed in trenches410and is in contact with side surfaces of semiconductor layer442and a top surface of semiconductor layer442by, for example, a chemical vapor deposition process, an atomic layer deposition process, or any other suitable deposition process. In some embodiments of the present disclosure, insulating layer443can include a dielectric material, such as AlxOy, SiCN, SiCO, and SiN.

Insulating layer443can be photo patterned and etched, according to some embodiments of the present disclosure. Referring toFIGS.10A and10B, insulating layer443can be undergo a photo patterning and etching process1010to expose interlayer dielectric structure135along a periphery of insulating layer443. In some embodiments of the present disclosure, insulating layer443can be further photo patterned and etched to form trench end cuts (e.g., to prevent electrical shorts within resistor structure400). Referring toFIGS.11A and11B, insulating layer443can undergo another photo patterning and etching process to remove additional portions of insulating layer443(e.g., in a z direction).

Referring toFIG.5, at operation560, interconnect structures are formed in the interlayer dielectric structure. Referring toFIGS.12A and12B, the formation of the interconnect structures can include depositing a dielectric material (e.g., SiNx, SiOC, and SiOCN) onto the semiconductor structure ofFIGS.11A and11Band performing a polishing operation (e.g., a chemical mechanical polishing operation). The dielectric material can be the same material as interlayer dielectric structure135. Referring toFIGS.13A and13B, the formation of the interconnect structures can also include performing a photo patterning and etching process1310to form contact openings1320. Contact openings1320are formed through interlayer dielectric structure135and insulating layer443so that portions of semiconductor layer442are exposed. Further, referring toFIGS.14A and14B, a conductive material (e.g., Cu, Al, TiN, TaN, and W) is deposited into contact openings1320and polished (e.g., chemical mechanical polishing) to form first contact structure444and second contact structure445.

First contact structure444is in contact with a portion of semiconductor layer442disposed over a portion of interlayer dielectric structure135at an end of resistor structure400. Second contact structure445is in contact with another portion of semiconductor layer442disposed over another portion of interlayer dielectric structure at an opposite end of resistor structure400. First contact structure444and second contact structure445can electrically connect to other interconnect structures, such as metal line structures446and447inFIG.4. Although four contact structures are shown inFIGS.14A and14B, resistor structure400can have more or less than four contact structures depending on the design on resistor structure400.

With advances in semiconductor technology, there have been increasing demands for higher storage capacity, faster processing systems, higher performance, and lower costs. To meet these demands, the semiconductor industry continues to scale down the dimensions of circuit elements, such as active devices (e.g., MOSFETs, finFETs, and GAAFETs) and passive devices (e.g., capacitors, inductors, and resistors). As the number of circuit elements increases, implementation of these circuit elements becomes increasingly more complex.

The present disclosure describes semiconductor structures and methods to form resistor structures (e.g., resistor structure400ofFIG.4) in a back end of line region of a semiconductor device (e.g., back end of line region130of semiconductor device100inFIG.1). The resistor structure can include a dielectric layer, trenches, a metal layer, a semiconductor layer, and an insulating layer. The dielectric layer is disposed above electrical components formed on a substrate. The trenches are disposed in the dielectric layer and separated from each other by a dielectric region of the dielectric layer. The metal layer is disposed on a bottom surface and side surfaces of each of the trenches and on a top surface of the dielectric region. The semiconductor layer is disposed on a bottom surface, side surfaces, and a top surface of the metal layer. The insulating layer disposed in the plurality of trenches and in contact with side surfaces of the semiconductor layer and on a top surface of the semiconductor layer. A benefit, among others, of implementing the resistor structure in the back end of line region of the semiconductor device is that that the back end of line region can be utilized for the fabrication of passive devices—e.g., resistor structures—thus increasing available area on the substrate for the implementation of additional active devices and/or passive devices to enhance the functionality and performance of the semiconductor device.

Embodiments of the present disclosure include a resistor structure with a dielectric layer, trenches, a metal layer, a semiconductor layer, and an insulating layer. The dielectric layer is disposed above electrical components formed on a substrate. The trenches are disposed in the dielectric layer and separated from each other by a dielectric region of the dielectric layer. The metal layer is disposed on a bottom surface and side surfaces of each of the trenches and on a top surface of the dielectric region. The semiconductor layer is disposed on a bottom surface, side surfaces, and a top surface of the metal layer. The insulating layer disposed in the trenches and in contact with side surfaces of the semiconductor layer and a top surface of the semiconductor layer.

Embodiments of the present disclosure include a semiconductor structure with a substrate and a metal region. The substrate includes electrical components formed thereon. The metal region is disposed over the electrical components and includes a dielectric layer, interconnect structures disposed in the dielectric layer, and a resistor structure disposed in the dielectric layer and in contact with the interconnect structures. The resistor structure includes trenches, a metal layer, a semiconductor layer, and an insulating layer. The trenches are separated from each other by a dielectric region of the dielectric layer. The metal layer is disposed on a bottom surface and side surfaces of each of the trenches and on a top surface of the dielectric region. The semiconductor layer is disposed on a bottom surface, side surfaces, and a top surface of the metal layer. The insulating layer disposed in the trenches and in contact with side surfaces of the semiconductor layer and a top surface of the semiconductor layer.

Embodiments of the present disclosure include a method to form a resistor structure in a back end of line region of a semiconductor device. The method includes forming a dielectric layer above electrical components disposed on a substrate; forming, in the dielectric layer, trenches separated from each other by a dielectric region of the dielectric layer; forming a metal layer on a bottom surface and side surfaces of each of the trenches and on a top surface of the dielectric region; forming a semiconductor layer on a bottom surface, side surfaces, and a top surface of the metal layer; and forming an insulating layer in the trenches and in contact with side surfaces of the semiconductor layer and a top surface of the semiconductor layer.