Leadframe package with adjustable clip

An integrated circuit package includes a leadframe with a die pad and a lead. A semiconductor die is attached to a top surface of the die pad. A clip has a lead contact area with a surface pattern on a bottom surface of the clip that is proximate to a first end of the clip. A portion of the surface pattern is attached to a top surface of a terminal pad of the lead. The clip includes a die contact area on the bottom surface of the clip that is proximate to a second end of the clip. The die contact area of the clip is attached to a top contact on the semiconductor die. The surface pattern has a length in a longitudinal direction of the clip in a direction parallel with a plane of the bottom surface of the die pad that is greater than a length of the top surface of the terminal pad of the lead.

FIELD OF TECHNOLOGY

The present application relates to a leadframe package with a semiconductor die and a clip that electrically connects a top contact of the semiconductor die with a lead of the leadframe. More specifically, the present disclosure relates to a clip which can accommodate semiconductor dies having different sizes.

BACKGROUND

An important objective with the design of power devices for high power and high current applications is minimizing the on-resistance of the power device in order to improve overall power efficiency. The total on-resistance when a power device is conducting current is a sum of the resistance of the semiconductor die mounted within a package and the resistance of the package which electrically connects the semiconductor die to external leads of the package. Conductive clips have been used to replace traditional bond wire connections due to the significant reductions in package resistance that can be achieved when compared to packages that use bond wires. Conventional clips that are designed for leadframe packages have a length that accommodates a connection to a top contact of the semiconductor device which is mounted in the center of the die pad of the leadframe. Smaller die however still have to be mounted in the center of the die pad due to the length of the conventional clip which results in a higher than necessary on-resistance contribution from the package.

SUMMARY

According to an embodiment of an integrated circuit package, the integrated circuit package includes a leadframe that includes a die pad and a lead. A semiconductor die is attached to a top surface of the die pad. The integrated circuit package includes a clip having a lead contact area with a surface pattern on a bottom surface of the clip that is proximate to a first end of the clip. A portion of the surface pattern is attached to a top surface of a terminal pad of the lead. The clip includes a die contact area on the bottom surface of the clip that is proximate to a second end of the clip. The die contact area of the clip is attached to a top contact on the semiconductor die. The surface pattern has a length in a longitudinal direction of the clip in a direction parallel with a plane of the bottom surface of the die pad that is greater than a length of the top surface of the terminal pad of the lead.

According to an embodiment of an integrated circuit package, the integrated circuit package includes a leadframe that includes a die pad and a lead. A semiconductor die is attached to a top surface of the die pad. The die pad has a right side, a left side and a center equidistant from the right side and the left side in a direction parallel with a plane of the top surface of the die pad. The integrated circuit package includes a clip that includes a surface pattern on a bottom surface of the clip that is proximate to a first end of the clip. A portion of the surface pattern is attached to a top surface of a terminal pad of the lead. The clip includes a die contact area on the bottom surface of the clip that is proximate to a second end of the clip. The die contact area is attached to a top contact on the semiconductor die. The surface pattern includes features that extend downward from the bottom surface of the clip. The surface pattern has a length in a longitudinal direction of the clip in the direction parallel with a plane of the bottom surface of the die pad that is greater than a length of the top surface of the terminal pad of the lead.

According to an embodiment of a method of forming an integrated circuit package, the method includes providing a leadframe that includes a die pad and a lead having a terminal pad, where the die pad has a right side, a left side and a center equidistant from the right side and the left side in a direction parallel with a plane of the top surface of the die pad. The method includes providing a clip that includes a surface pattern on a bottom surface of the clip that is proximate to a first end of the clip. The clip includes a die contact area on the bottom surface of the clip that is proximate to a second end of the clip. The surface pattern includes features that extend downward from the bottom surface of the clip. The surface pattern has a length in a longitudinal direction of the clip in a direction parallel with a plane of the bottom surface of the die pad that is greater than a length of the top surface of the terminal pad of the lead. The method includes attaching a semiconductor die to the top surface of the die pad. The method includes attaching the die contact area of the clip to a top contact on the semiconductor die. The die contact area of the clip is attached to the top contact on the semiconductor die above the top surface of the die pad and between the center and the right side of the top surface of the die pad in a direction perpendicular to a plane of the top surface of the die pad. The method includes attaching a portion of the surface pattern on the bottom surface of the clip to a top surface of the terminal pad of the lead such that other portions of the surface pattern on the bottom surface of the clip that are not attached to the top surface of the terminal pad are on a right side of the top surface of the terminal pad.

According to an embodiment of a method of forming an integrated circuit package, the method includes providing a leadframe that includes a die pad and a lead having a terminal pad. The die pad has a right side, a left side and a center equidistant from the right side and the left side in a direction parallel with a plane of the top surface of the die pad. The method includes providing a clip that includes a surface pattern on a bottom surface of the clip that is proximate to a first end of the clip. The clip includes a die contact area on the bottom surface of the clip that is proximate to a second end of the clip. The surface pattern includes features that extend downward from the bottom surface of the clip. The surface pattern has a length in a longitudinal direction of the clip in a direction parallel with a plane of the bottom surface of the die pad that is greater than a length of the top surface of the terminal pad of the lead. The method includes attaching a semiconductor die to the top surface of the die pad. The method includes attaching the die contact area of the clip to a top contact on the semiconductor die. The die contact area of the clip is attached to the top contact on the semiconductor die above the top surface of the die pad at approximately the center of the top surface of the die pad in a direction perpendicular to a plane of the top surface of the die pad. The method includes attaching a portion of the surface pattern on the bottom surface of the clip to a top surface of the terminal pad of the lead such that other portions of the surface pattern on the bottom surface of the clip that are not attached to the top surface of the terminal pad are on a left side of the top surface of the terminal pad.

According to an embodiment of an apparatus, the apparatus includes a leadframe that includes a die pad and a lead, where the lead has a terminal pad. A clip includes a lead contact area with a surface pattern on a bottom surface of the clip that is proximate to a first end of the clip, where the surface pattern is configured to be attached to a top surface of the terminal pad. The clip includes a die contact area on the bottom surface of the clip that is proximate to a second end of the clip. The surface pattern has a length in a longitudinal direction of the clip in a direction parallel with a plane of the bottom surface of the die pad that is greater than a length of the top surface of the terminal pad so that a die selected from a plurality of dies each having a different size in the longitudinal direction of the clip in the direction parallel with the plane of the bottom surface of the die pad can be attached to the die pad with the die contact area of the clip attached to a top contact on the semiconductor die such that a different portion of the surface pattern of the clip is attached to the top surface of the terminal pad of the lead depending on the size of the selected die.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing”, “upper,” “lower,” “right”, “left”, “vertical,” “horizontal” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting.

As employed in this specification, the terms “bonded”, “attached”, “connected”, “coupled” and/or “electrically connected/electrically coupled” are not meant to mean that the elements or layers must directly be contacted together; intervening elements or layers may be provided between the “bonded”, “attached”, “connected”, “coupled” and/or “electrically connected/electrically coupled” elements, respectively. However, in accordance with the disclosure, the above-mentioned terms may, optionally, also have the specific meaning that the elements or layers are directly contacted together, i.e. that no intervening elements or layers are provided between the “bonded”, “attached”, “connected”, “coupled” and/or “electrically connected/electrically coupled” elements, respectively.

Furthermore, the word “over” used with regard to a part, element or material layer formed or located “over” a surface may be used herein to mean that the part, element or material layer be located (e.g. placed, formed, deposited, etc.) indirectly on the implied surface with the part, element or material layer or layers being arranged between the implied surface and the part, element or material layer. However, the word “over” used with regard to a part, element or material layer formed or located “over” a surface may optionally also have the specific meaning that the part, element or material layer be located (e.g. placed, formed, deposited, etc.) directly on, e.g. in direct contact with, the implied surface.

The semiconductor die may be of different types, may be manufactured by different technologies and may include, for example, integrated electrical, electro-optical or electro-mechanical circuits and/or passive devices. The semiconductor die may, for example, be logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, power integrated circuits, memory circuits or passive devices. They may include control circuits, microprocessors or microelectromechanical components. The semiconductor die may be power semiconductor die that include, but are not limited to, Metal Oxide Semiconductor Field-effect Transistors (MOSFETs), Insulated Gate Bipolar Transistors (IGBTs), Gallium Nitride (GaN) devices, Silicon Carbide (SiC) devices, Junction Gate Field Effect Transistors (JFETs), as well as power bipolar transistors or power diodes.

The integrated circuit packages, lead frames and leadframe modules described herein include packages such as a Transistor Outline Leadless (TOLL) package, a Quad Flat No Leads Package (QFN) package, a Small Outline (SO) package, a SS08 package, a Small Outline Transistor (SOT) package, a Thin Small Outline Package (TSOP) package, a Dual Small Outline Package (DSO) and a Double Sided Cooling (DSC) package. The leadframe modules can include multiple semiconductor die on a same die pad or on different die pads of the leadframe module.

It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

FIG.1illustrates an embodiment of a cross-sectional view of an integrated circuit package at100. Integrated circuit package100can be any suitable type of package that includes, but is not limited to, a TOLL package, a SS08 package, S308 package, a QFN package, an SO package, a SOT package, a TSOP package, a DSO package, a DSC package and a leadframe module. In the illustrated embodiment, a lead frame102includes a die pad106and a lead108. A semiconductor die110is attached to a top surface112of the die pad106. A clip114includes a lead contact area116with a surface pattern118on a bottom surface120of the clip114that is proximate to a first end122of the clip114(See also,FIGS.2-3B). In the illustrated embodiment, the clip114comprises copper (Cu). In the illustrated embodiment, the leadframe102comprises copper (Cu). In other embodiments, leadframe102can be formed from other suitable materials that include, but are not limited to, aluminum (Al), nickel (Ni), iron (Fe) and steel. In the illustrated embodiment, semiconductor die110is a Metal Oxide Semiconductor Field-effect Transistor (MOSFET) and includes a top contact136which is a source contact and includes a bottom drain contact which is electrically coupled to the top surface112of die pad106. In other embodiments, semiconductor die110can be other suitable types of devices such as an Insulated Gate Bipolar Transistor (IGBT), a Gallium Nitride (GaN) device or a Silicon Carbide (SiC) device.

In the illustrated embodiment, a portion illustrated at124of the surface pattern118is attached to a top surface126of terminal pad128of the lead108. The clip114includes a die contact area130on the bottom surface120of the clip114that is proximate to a second end132of the clip114. The die contact area130is attached to a top contact136on the top side of semiconductor die110. The surface pattern118has a length illustrated at138in a longitudinal direction140of the clip114in a direction parallel with a plane of the bottom surface142of the die pad106that is greater than a length124of the top surface126of the terminal pad128of the lead108(See also,FIG.2). A mold compound104encapsulates the semiconductor die110, the clip114and a portion of the leadframe102.

FIG.2illustrates an embodiment of a bottom view at200of the clip114illustrated inFIG.1. The clip114includes a step portion between202and204between the first end122of clip114and the second end132of clip114. The surface pattern118is between the first end122of clip114and the step portion edge at202. The die contact area130is between the second end132of clip114and the step portion edge at204. The bottom surface120of the clip114between the step portion202/204and the surface pattern118is illustrated at208. The die contact area130has a length illustrated at206that is between the second end132and the step portion edge at204. The length138of the surface pattern118is slightly less than the length of the lead contact area illustrated at116. In other embodiments, the length138of the surface pattern118is equal to the length illustrated at116for the lead contact area116.

FIGS.3A and3Billustrates embodiments of a side view at300A and300B of the clip114illustrated inFIG.1andFIG.2. Referring toFIGS.3A and3B, the top surface312of clip114between the first end122of clip114and the step portion at202is a planar top surface312. The surface pattern118has a length illustrated at138in a longitudinal direction140of the clip114. In one embodiment, the bottom surface120of clip114between the step portion at202and the surface pattern118is parallel with at least a portion of the top surface126of the terminal pad128(See also,FIG.1). In one embodiment, the bottom surface120of clip114between the step portion at202and the surface pattern118is parallel with the bottom surface120of clip114between the second end132and the step portion at204. In one embodiment, the clip114between the first end122and the step portion edge at202has a height in a direction perpendicular with a plane of the bottom surface142of the die pad106that is greater than a height of the clip114between the second end132and the step portion at204(See also,FIGS.1and2).

Referring toFIG.3A, the features302of the surface pattern118have a hemispherical shape. The features302extend downward from the bottom surface120of the clip114by a distance between dash lines304and306as illustrated by arrows308and310. In the illustrated embodiment, the distance between dash lines304and306is equal to or greater than 30 microns. In other embodiments, the distance between dash lines304and306can be less than 30 microns. The features302are spaced apart by a distance between dash lines314and316as illustrated by arrows318and320by a distance that is equal to or greater than 30 microns. In other embodiments, the distance between dash lines314and316can be less than 30 microns.

Referring toFIG.3B, the features322of the surface pattern118are parallel rectangular bar features. The features322extend downward from the bottom surface120of the clip114by a distance between dash lines324and326as illustrated by arrows328and330. In the illustrated embodiment, the distance between dash lines324and326is equal to or greater than 30 microns. In other embodiments, the distance between dash lines324and326can be less than 30 microns. The features322are spaced apart by a distance between dash lines332and334as illustrated by arrows336and338by a distance that is equal to or greater than 30 microns. In other embodiments, the distance between dash lines332and334can be less than 30 microns.

FIGS.4A-4Cillustrate embodiments at400A,400B and400C of a bottom view of surface patterns118for a clip114.FIG.4Aillustrates an embodiment at400A of parallel rectangular bar features at402. Each rectangular bar feature402has a long dimension404in the longitudinal direction140of the clip114. In the illustrated embodiment, each rectangular bar feature402is spaced apart from an adjacent rectangular bar feature402by a distance410between dash lines406and408that is equal to or greater than 30 microns. In other embodiments, each rectangular bar feature402is spaced apart from an adjacent rectangular bar feature402by a distance410that is less than 30 microns.

FIG.4Billustrates an embodiment at400B of parallel rectangular bar features at412. Each rectangular bar feature412has a long dimension414in a direction transverse to the longitudinal direction140of the clip114. In the illustrated embodiment, each rectangular bar feature412is spaced apart from an adjacent rectangular bar feature412by a distance420between dash lines416and418that is equal to or greater than 30 microns. In other embodiments, each rectangular bar feature412is spaced apart from an adjacent rectangular bar feature412by a distance420that is less than 30 microns.

FIG.4Cillustrates an embodiment at400C of a three by three or greater array of spaced-apart features422each having a hemispherical shape. In the illustrated embodiment, the array of spaced-apart features422is a four by four array of spaced-apart features422. In other embodiments, the array of spaced-apart features422can be a two by two array of spaced-apart features422or a five by five or greater array of spaced-apart features422. In other embodiments, the array of spaced-apart features422can be a two by three or greater array of spaced-apart features422or can be a three by two or greater array of spaced-apart features422. In other embodiments, the spaced apart features can be any suitable combination or derivative of the features402,412and422. In the illustrated embodiment, each one of the spaced apart features422is spaced apart from an adjacent one of the spaced apart features422by a distance between arrows428and430between the dash lines424and426that is equal to or greater than 30 microns. In other embodiments, each one of the spaced apart features422is spaced apart from an adjacent one of the spaced apart features422by a distance between arrows428and430between the dash lines424and426that is less than 30 microns.

FIG.5illustrates an embodiment at500of sectional view of the clip114and lead108illustrated inFIG.1. The sectional view at500is in the longitudinal direction140in a direction from the first end122to the second end132of clip114. The features422extend downward from the bottom surface120of clip114and contact the top surface126of terminal pad128of the lead108. In the embodiment illustrated inFIG.5, the features422are an array of spaced-apart features422each having a hemispherical shape (See also,FIGS.3A and4C). In other embodiments, the features422can be any suitable combination or derivative of the features402,412and422illustrated inFIGS.4A-4C. In the illustrated embodiment, the portion124of the surface pattern118is attached to the terminal pad128of lead108via solder as illustrated at502(See also,FIG.1). Solder502at least partially fills portion124of the surface pattern118to attach portion124of the surface pattern118to the top surface126of the terminal pad128(See also,FIG.1).

FIG.6illustrates an embodiment of an integrated circuit package at600.FIG.7illustrates an embodiment of an integrated circuit package at700. In the embodiments illustrated inFIGS.6and7, integrated circuit packages600and700utilize the same leadframe102and clip114, but integrated circuit die110within integrated circuit package600is larger in size than integrated circuit die710within integrated circuit package700. In the embodiments illustrated inFIGS.6and7, the leadframe102and clip114together can make up an apparatus that can be used to manufacture integrated circuit packages with integrated circuit dies110having different sizes.

Referring toFIG.6, leadframe102includes a die pad106and a lead108. A semiconductor die110is attached to a top surface112of the die pad106. A clip114includes a lead contact area116with a surface pattern118on a bottom surface120of the clip114that is proximate to a first end122of the clip114(See also,FIG.2). The clip114includes a surface pattern118on a bottom surface120of clip114that includes features (e.g.,402,412and/or422) that extend downward from the bottom surface120of the clip114(See also,FIGS.3A-4C). In the illustrated embodiment, the clip114comprises copper (Cu) and the leadframe102comprises copper (Cu). In other embodiments, leadframe102can be formed from other suitable materials that include, but are not limited to, aluminum (Al), nickel (Ni), iron (Fe) and steel. In the illustrated embodiment, semiconductor die110is a Metal Oxide Semiconductor Field-effect Transistor (MOSFET) and includes a top contact136which is a source contact and includes a bottom drain contact which is electrically coupled to the top surface112of die pad106. In other embodiments, semiconductor die110can be other suitable types of devices such as an Insulated Gate Bipolar Transistor (IGBT), a Gallium Nitride (GaN) device or a Silicon Carbide (SiC) device.

In the illustrated embodiment, semiconductor die110has a right side602, a left side604and a center606equidistant from the right side602and the left side604in a direction parallel with the plane of the top surface112of the die pad106. The top surface112of the die pad106has a center608, a right side610and a left side612. Semiconductor die110is attached to the top surface112of the die pad106such that a center606of the semiconductor die110is approximately at the center608of the top surface112of the die pad106.

In the illustrated embodiment, the surface pattern118for clip114has a length illustrated as a sum of length124and length614in a longitudinal direction140of the clip114in a direction parallel with a plane of the bottom surface142of the die pad106. Length124represents a length of the top surface126of the terminal pad128which is less than the sum of lengths124and614that represent the length of surface pattern118. The die contact area130of the clip114is attached to the top contact136on the semiconductor die110above the top surface112of the die pad106at approximately the center608of the top surface112of the die pad106. A portion illustrated at124of the surface pattern118is attached to the top surface126of terminal pad128. In the longitudinal direction140of the clip114, other portions of surface pattern118not attached to top surface126of terminal pad128are illustrated at614and are on a left side618of the top surface126of the terminal pad128. In other embodiments, other portions of surface pattern118not attached to top surface126of terminal pad128can be on a right side616of the top surface126of the terminal pad128, or on both the right side616and the left side618of the top surface126of the terminal pad128.

In the illustrated embodiment, clip114has a length between first end122and second end132illustrated at620that is the same as for the embodiment illustrated inFIG.7. The total on-resistance of semiconductor die110and integrated circuit package600when semiconductor die110is conducting current is a sum of the resistance of semiconductor die110which is mounted on die pad106and the resistance of the package which includes clip114. Because semiconductor die110is mounted at approximately at the center608of die pad106such that the top contact136on semiconductor die110is approximately above the center608of the die pad106, the full length620of clip114is utilized to connect top contact136of semiconductor die110to the top surface126of terminal pad128.

Referring toFIG.7, a lead frame102includes a die pad106and a lead108. A semiconductor die710is attached to a top surface112of the die pad106. A clip114includes a lead contact area116with a surface pattern118on a bottom surface120of the clip114that is proximate to a first end122of the clip114(See also,FIG.2). The clip114includes a surface pattern118on a bottom surface120of clip114that includes features (e.g.,402,412and/or422) that extend downward from the bottom surface120of the clip114(See also,FIGS.3A-4C). In the illustrated embodiment, the clip114comprises copper (Cu) and the leadframe102comprises copper (Cu). In other embodiments, leadframe102can be formed from other suitable materials that include, but are not limited to, aluminum (Al), nickel (Ni), iron (Fe) and steel. In the illustrated embodiment, semiconductor die710is a Metal Oxide Semiconductor Field-effect Transistor (MOSFET) and includes a top contact708which is a source contact and includes a bottom drain contact which is electrically coupled to the top surface112of die pad106. In other embodiments, semiconductor die710can be other suitable types of devices such as an Insulated Gate Bipolar Transistor (IGBT), a Gallium Nitride (GaN) device or a Silicon Carbide (SiC) device.

In the illustrated embodiment, semiconductor die710has a right side702, a left side704and a center706equidistant from the right side702and the left side704in a direction parallel with the plane of the top surface112of the die pad106. The top surface112of the die pad106has a center608, a right side610and a left side612. Semiconductor die710is attached to the top surface112of the die pad106such that a center706of the semiconductor die710is between the center608and the right side610of the top surface112of the die pad106. In the illustrated embodiment, the surface pattern118for clip114has a length illustrated as a sum of length124and length712in a longitudinal direction140of the clip114in a direction parallel with a plane of the bottom surface142of the die pad106. Length124represents a length of the top surface126of the terminal pad128which is less than the sum of lengths124and712that represent the length of surface pattern118. The die contact area130of the clip114is attached to the top contact708on the semiconductor die710above the top surface112of the die pad106and between the center608and the right side610of the top surface112of the die pad106. A portion illustrated at124of the surface pattern118is attached to the top surface126of terminal pad128. In the longitudinal direction140of the clip114, other portions of surface pattern118not attached to top surface126of terminal pad128are illustrated at712and are on a right side616of the top surface126of the terminal pad128. In other embodiments, other portions of surface pattern118not attached to top surface126of terminal pad128can be on the left side618of the top surface126of the terminal pad128, or on both the right side616and the left side618of the top surface126of the terminal pad128.

In the illustrated embodiment, clip114has a length between first end122and second end132illustrated at620that is the same as for the embodiment illustrated inFIG.6. The total on-resistance of semiconductor die710and integrated circuit package700when semiconductor die710is conducting current is a sum of the resistance of semiconductor die710which is mounted on die pad106and the resistance of the package which includes clip114. Because semiconductor die710is mounted such that a center706of semiconductor die710is between the center608and the right side610of the die pad106such that the top contact708on semiconductor die710is above top surface112of die pad106between the center608and the right side610of the die pad106, only a portion of the full length620of clip114is utilized to connect top contact708of semiconductor die710to the top surface126of terminal pad128. As a result, the effective length of clip114is reduced by the portion712of the surface pattern118that is to the right side616of terminal pad128which provides a corresponding reduction in the resistance of clip114.

FIG.8illustrates an embodiment at800of a method of forming an integrated circuit package with a clip. Method800illustrates an embodiment of forming integrated circuit package700illustrated inFIG.7. At802, the method includes providing a leadframe102that includes a die pad106and a lead108having a terminal pad128. The die pad106has a right side610, a left side612, and a center608equidistant from the right side610and the left side612in a direction parallel with a plane of the top surface112of die pad106. At804, the method includes providing a clip114that includes a surface pattern118on a bottom surface120of the clip114that is proximate to a first end122of the clip114(See also,FIGS.2-3B). The clip114includes a die contact area130on the bottom surface120of the clip114that is proximate to a second end132of the clip114(See also,FIGS.2-3B). The surface pattern118includes features (e.g.,402,412and/or422) that extend downward from the bottom surface120of the clip114(See also,FIGS.3A-4C). The surface pattern has a length138in a longitudinal direction140of the clip114in a direction parallel with a plane of the bottom surface142of the die pad106that is greater than a length124of the top surface126of the terminal pad128of the lead108(See also,FIG.1). In the embodiment illustrated inFIG.7, the surface pattern118for clip114has a length illustrated as a sum of length124and length712in a longitudinal direction140of the clip114in a direction parallel with a plane of the bottom surface142of the die pad106.

At806, the method includes attaching a semiconductor die710to the top surface112of the die pad106. The semiconductor die710is attached to the top surface112of the die pad106such that a center706of the semiconductor die710is between the center608and the right side610of the top surface112of the die pad106.

At808, the method includes attaching the die contact area130of the clip114to a top contact708on the semiconductor die710. The die contact area130of the clip114is attached to the top contact708on the semiconductor die710above the top surface112of the die pad106at a position that is between the center608and the right side610of the top surface112of the die pad106in a direction perpendicular to a plane of the top surface112of the die pad106.

At810, the method includes attaching a portion of the surface pattern118on the bottom surface120of the clip114to a top surface126of the terminal pad128of the lead108. Other portions of surface pattern118on the bottom surface120of the clip114that are not attached to the top surface126of terminal pad128as illustrated at712are on a right side616of the top surface126of the terminal pad128(See also,FIG.7). In the illustrated embodiment, attaching the portion of the surface pattern118on the bottom surface120of the clip114to the top surface126of the terminal pad128of the lead108includes using solder which at least partially fills the portion of the surface pattern118(See also,FIG.5).

FIG.9illustrates an embodiment at900of a method of forming an integrated circuit package with a clip. Method900illustrates an embodiment of forming integrated circuit package600illustrated inFIG.6. At902, the method includes providing a leadframe102that includes a die pad106and a lead108having a terminal pad128. The die pad106has a right side610, a left side612, and a center608equidistant from the right side610and the left side612in a direction parallel with a plane of the top surface112of die pad106. At904, the method includes providing a clip114that includes a surface pattern118on a bottom surface120of the clip114that is proximate to a first end122of the clip114(See also,FIGS.2-3B). The clip114includes a die contact area130on the bottom surface120of the clip114that is proximate to a second end132of the clip114(See also,FIGS.2-3B). The surface pattern118includes features (e.g.,402,412and/or422) that extend downward from the bottom surface120of the clip114(See also,FIGS.3A-4C). The surface pattern118has a length138in a longitudinal direction140of the clip114in a direction parallel with a plane of the bottom surface142of the die pad106that is greater than a length124of the top surface126of the terminal pad128of the lead108(See also,FIG.1). In the embodiment illustrated inFIG.6, the surface pattern118for clip114has a length illustrated as a sum of length124and length614in a longitudinal direction140of the clip114in a direction parallel with a plane of the bottom surface142of the die pad106.

At906, the method includes attaching a semiconductor die110to the top surface112of the die pad106. In one embodiment, the semiconductor die110is attached to the top surface112of the die pad106such that a center606of the semiconductor die110is approximately aligned with the center608of the top surface112of the die pad106.

At908, the method includes attaching the die contact area130of the clip114to a top contact136on the semiconductor die110. The die contact area130of the clip114is attached to the top contact136on the semiconductor die110above the top surface112of the die pad106at approximately the center606of the top surface112of the die pad106in a direction perpendicular to a plane of the top surface112of the die pad106.

At910, the method includes attaching a portion of the surface pattern118on the bottom surface120of the clip114to a top surface126of the terminal pad128of the lead108. Other portions of surface pattern118on the bottom surface120of the clip114that are not attached to the top surface126of terminal pad128as illustrated at614are on a left side618of the top surface126of the terminal pad128(See also,FIG.6). In the illustrated embodiment, attaching the portion of the surface pattern118on the bottom surface120of the clip114to the top surface126of the terminal pad128of the lead108includes using solder which at least partially fills the portion of the surface pattern118(See also,FIG.5).

FIG.10illustrates an embodiment of a cross-sectional view of an integrated circuit package at1000. A flat leadframe1002includes a die pad1006and a lead1008. A semiconductor die1010is attached to a top surface1012of the die pad1006. A clip1014includes a lead contact area illustrated at1016with a surface pattern1018on a bottom surface of the clip1014that is proximate to a first end1020of the clip1014. The surface pattern1018includes features illustrated at422but can also include features such as those illustrated at402or412, as well as other suitable features that extend downward from the bottom surface of the clip1014(See also,FIGS.4A-4C). Clip1014has a center step portion illustrated at1024that is between the first end1020of clip1014and the second end1030of clip1014. Clip1014has a height between a bottom surface1026of the step portion1024and a reference at1028which is sufficient to facilitate use of the clip1014with flat leadframe1002. In one embodiment, the height between the bottom surface1026of the step portion1024and the reference at1028represents a height between the bottom surface1026of the step portion1024and a bottom surface of clip1014that contacts a top contact1022of semiconductor die1010.

In the illustrated embodiment, the clip1014comprises copper (Cu) and the leadframe1002comprises copper (Cu). In other embodiments, the leadframe1002can be formed from other suitable materials that include, but are not limited to, aluminum (Al), nickel (Ni), iron (Fe) and steel. In the illustrated embodiment, semiconductor die1010is a Metal Oxide Semiconductor Field-effect Transistor (MOSFET) and includes the top contact1022which is a source contact and includes a bottom drain contact which is electrically coupled to the top surface1012of die pad1006. In other embodiments, semiconductor die1010can be other suitable types of devices such as an Insulated Gate Bipolar Transistor (IGBT), a Gallium Nitride (GaN) device or a Silicon Carbide (SiC) device.