Variable gain amplifier with direct current offset correction

Techniques to provide DC-offset correction in a variable gain amplifier are described.

BACKGROUND

In wireless communication applications, it may be desirable to use variable gain amplifiers to amplify received information signals. These amplifiers provide a higher gain when an input signal has a lower level, and a lower gain when an input signal is at a higher level. Variable gain amplifiers, however, may generate direct current (DC) offsets due to component mismatches within each stage of the amplifiers. In wireless applications which require high gain amplifiers, this DC-offset may need to be removed or corrected without compromising data signal integrity.

The DC-offset of a variable gain amplifier may be removed by using certain DC blocking capacitors or feedback loops having various architectures. These techniques may require, however, the use of very high resistance values and capacitors that are too large for integration within microcircuits where space restraints on a die are at a premium. Consequently, there may be a need for improvements in DC-offset correction in variable gain amplifiers that utilize high value resistors with associated low signal distortion.

DETAILED DESCRIPTION

FIG. 1illustrates a schematic diagram of a variable gain amplifier (VGA)100in accordance with one embodiment. VGA100includes multiple gain stages110,120,130and140. Typically, the voltage levels supplied to VGA100are either insufficient to drive one or more corresponding circuit elements, such as an analog-to-digital (A/D) converter connected to the outputs of VGA100, or are too large if supplied to the corresponding circuit element. Therefore, VGA100may be used to vary the supplied voltage levels and provide a sufficient voltage gain for further signal processing without compromising data signal integrity. Since VGA100is capable of providing such high gain, in one embodiment VGA100may be implemented in multiple stages in order to avoid producing too much gain in any one stage, thereby potentially resulting in amplifier instability.

As shown inFIG. 1, VGA100may have two input voltage terminals Vin+ and Vin− and two outputs Vout+ and Vout−. VGA100may amplify the input signal in accordance with the gain of the amplifier. In one embodiment, VGA100may comprise a differential amplifier, such that the gain of the amplifier is based on the difference between the input voltage levels Vin+ and Vin−. The outputs115and116of first gain stage110are supplied to the inputs of second amplifier stage120. The outputs125and126of second amplifier stage120are supplied to the inputs of third amplifier stage130. The outputs135and136of third amplifier stage130are supplied to the inputs of fourth amplifier stage140. Fourth amplifier stage140may produce voltage outputs Vout+ and Vout−. Although four amplifier stages are illustrated inFIG. 1, it may be appreciated that any number of gain stages may be used in accordance with a given implementation to provide an almost constant signal to a corresponding circuit device. An example of a corresponding circuit device may include an A/D converter in a wireless receiver. The gain of each stage110,120,130and140of VGA100may vary, for example, from 12 decibels (dB) to 18 dB in such wireless applications.

A byproduct of the gain provided by VGA100may comprise DC offset. DC offset is the random offset voltage which may cause the outputs of VGA100to deviate from the common mode reference. DC offset may occur for a number of reasons, such as manufacturing process parameters, layout mismatches and variations in threshold voltage levels in the various gain stages110,120,130and140of VGA100. Further, the DC offset may propagate and be further amplified by each of the stages110,120,130and140. Consequently, VGA100may implement a DC-offset correction technique to prevent VGA100from saturating.

VGA100may attempt to correct for DC offset by feeding the output voltage signals from VGA100back to first gain stage110, thereby defining a closed-loop DC-offset correction circuit. This may allow VGA100to adjust the output DC operating parameters and potentially avoid the effects of large settling times on the operation of the amplifier.

In one embodiment, the closed-loop DC-offset correction circuit of VGA110may include a low pass filter (LPF)150and a LPF160. Output terminal Vout− may be connected to LPF150, and output terminal Vout+ may be connected to LPF160. Low pass filters150and160may be arranged to pass frequencies from 0 or DC to a cut-off frequency f1, wherein some attenuation exists for signals that fall off from the cut-off frequency f1.

In one embodiment, the closed-loop DC-offset correction circuit of VGA110may include a voltage to current (V/I) converter circuit170. Voltage to current converter circuit170may receive output signals from LPF150and LPF160via outputs155and156, respectively, and may detect the difference between these two signals. Voltage to current circuit170may supply outputs175and176to first gain stage110of VGA100. In this manner, the DC-offset correction may comprise the supply of the DC signal output by voltage to current circuit170which is added to the input signal of VGA100via first gain stage110.

In one embodiment, resistors and capacitors may be implemented in both LPF150and LPF160to assist in offsetting the undesirable DC component of VGA100. Leakage current may make the use of holding capacitors impractical in storing correction signals for the DC-offset correction unless thick gate devices are employed. In order to reduce component sizes or die areas in manufacturing VGA100, however, it may be useful to employ a very high resistance value and a small capacitance value. One reason for this is that the capacitors desired for this type of application may consume a relatively large area or “footprint” in the microcircuit.

Some embodiments may solve these and other problems by implementing techniques to provide a large resistive value and a smaller capacitance for VGA100while preserving area of the microcircuit. VGA100may be implemented with open loop and closed loop configurations using sub-threshold transistors to emulate resistor values for low voltage circuits used in wireless communication devices and systems. VGA100may be described in more detail with reference toFIGS. 2–6.

FIG. 2illustrates a schematic diagram of voltage to current circuit170for VGA100in accordance with one embodiment. Output voltage signals Vout+ and Vout− from gain stage140may be supplied to corresponding inputs Vout− and Vout+ of LPF150and LPF160. LPF150may comprise RLPF1and CLPF1, and LPF160may comprise RLPF2and CLPF2. Voltage to current circuit170may include a differential amplifier comprised of transistors M6and M7, a first current mirror comprised of transistors M8and M10, and a second current mirror comprised of transistors M9and M11. The current mirrors may provide a high effective output resistance, thereby increasing the gain of the differential amplifier comprised of transistors M6and M7.

Current mirror formed by transistors M8and M10may generate correction current Ic+ which is supplied to first gain stage110of VGA100. Similarly, current mirror formed by transistors M9and M11may generate correction current Ic− which may be supplied to first gain stage110of VGA100. In this manner, the DC-offset correction may utilize the supply of the direct current signals Ic+ and Ic− from voltage to current circuit170, which is added to the input signal of the first gain stage110of VGA100.

FIG. 3is a schematic illustration of a gain stage300. Gain stage300may be representative of a gain stage for a variable gain amplifier, such as one or more gain stages110,120,130or140of VGA100as described with reference toFIG. 1. In one embodiment, for example, gain stage300may be representative of differential gain stage110, andFIG. 3may illustrate the input of correction current supply Ic+ and Ic− to differential gain stage110. It should be understood, however, that gain stage300may also be applicable to each of the differential gains stages120,130and/or140. The embodiments are not limited in this context.

The differential gain stage provides an amplified gain to a received voltage signal. For example, voltage signal Vin+ may be received at the gate terminal of transistor M14, and may be amplified using transistors M13, M14and M15. Output signal Vout+ may be supplied by the outputs of transistors M12and M13. A common mode feedback circuit (not shown) may supply a common mode feedback (cmfb) signal Vcmfb to transistor M12and M12′. Voltage signal Vin− may be received at the gate terminal of transistor M14, and may be amplified using transistors M12, M13, M14and M15. Output Vout− may be supplied by the outputs of transistors M12and M13′. Outputs Vout+ and Vout− may be supplied to a subsequent gain stage of VGA100, such as gain stage120, for example. Since the circuit ofFIG. 3is used to depict gain stage110, the correction current signal Ic+ is provided to transistor M14and correction current signal Ic− is provided to transistor M14of gain stage110. In this manner, the differential voltage input signals are amplified by way of gain stage110, which also receives correction current signals Ic+ and Ic− from voltage to current circuit170.

FIG. 4is a block diagram of a variable gain amplifier with a high-pass filter (HPF) in accordance with one embodiment.FIG. 4may illustrate a VGA400. VGA400may include an open-loop DC-offset correction circuit to correct for DC-offset generated by the amplifier. VGA400may include a HPF410, differential gain stage110, a HPF420, and differential gain stage120. Although only two gain stages are shown with reference toFIG. 4, it may be appreciated that additional gain stages may be employed. In addition, although VGA400is shown in an open-loop DC-offset arrangement, it may be appreciated that VGA400may be modified to operate in a closed-loop DC-offset arrangement similar to VGA100described with reference toFIG. 1. The embodiments are not limited in this context.

In one embodiment, HPF410and HPF420may be configured to pass signals having frequencies above a predetermined threshold frequency ƒh. The output of HPF410may be supplied to gain stage110. The open loop configuration may utilize HPF410before first gain110to reduce or remove any unwanted DC signals before the first gain stage. The output voltage signals generated by gain stage110may be supplied to HPF420. HPF410and HPF420may be used to block the DC-offset error from propagating between stages by filtering out the undesirable low frequency DC signals. HPF410and HPF420may comprise, for example, a resistor and capacitor combination with a small corner frequency to block the DC offset signal without compromising information signal integrity. Similar to the RC combination of LPF150and LPF160, HPF410and HPF420may be arranged to use large resistor values so that relatively small capacitance values may be employed to reduce consumed area for the microcircuit.

As previously described, large RC values may be needed for HPF410and HPF420used in the open loop DC-offset correction circuit as shown inFIG. 4, as well as for LPF150and LPF160used in the closed-loop DC-offset correction circuit as shown inFIG. 1. In one embodiment, for example, the larger resistance values may be emulated by use of one or more sub-threshold transistors. The sub-threshold current is extremely small and a non-linear resistance may be provided. In this manner, the large die area needed for large resistance values will be relatively small as compared to conventional passive resistors. A resistor circuit arranged to provide the appropriate resistance for VGA100and VGA400may be described in more detail with reference toFIG. 5.

FIG. 5illustrates a resistor circuit500. Resistor circuit500may include transistor T1and transistor T2in cascaded connection with transistor T3and transistor T4to emulate a very large resistor with low distortion. This emulated or equivalent resistance may be utilized in combination with a capacitance value in HPF410and HPF420, and the RC combination of LPF150and LPF160, for example. Transistors T1and T2have their respective gate and source terminals connected such that the transistors are operating in the sub-threshold region. Similarly, transistors T3and T4have their respective gate and source terminals connected such that the transistors are operating in the sub-threshold region as well.

A modeling technique for the current equation in the sub-threshold transistor region may be given by Equation (1) as follows:

I=μ⁢⁢Cd⁢WL⁢VT2⁢exp⁡(VGS-VTHζ⁢⁢VT)⁢(1-exp⁡(-VDSVT))(1)
where Cdis the capacitance of the depletion region under the gate,

When the gate terminal is connected to the source terminal, the transistor is operating in the sub-threshold region. Consequently, Equation (1) may be simplified as shown in Equation (2) as follows:

I=μ⁢⁢Cd⁢WL⁢VT2⁢exp⁡(-VTHζ⁢⁢VT)⁢(1-exp⁡(-VDSVT))(2)
The equivalent resistance between the drain and source can be obtained by differentiating Equation (2) with respect to VDSas shown in Equation (3) as follows:

R=VTI0⁢exp⁡(VDSVT)(3)
where I0may be represented as shown in Equation (4) as follows:

I0=μ⁢⁢Cd⁢WL⁢VT2⁢exp⁡(-VTHζ⁢⁢VT)(4)
The non-linearity of the equivalent resistance in equation (3) can be reduced by forcing the drain to source voltage difference to smaller values. This may be accomplished by cascading the sub-threshold transistors as illustrated inFIG. 5.

FIG. 6illustrates equivalent resistance values as a function of voltage variation around a DC operating point of Vin=600 mV for the cascaded sub-threshold transistor configuration as shown inFIG. 5. Marker A having a value of 900 mV may correspond to an equivalent resistance of approximately 52.33 M for a four cascaded transistor configuration. In addition, marker B having a value of 900 mV may correspond to an equivalent resistance of approximately 304.5 K for a single sub-threshold transistor configuration. The graph ofFIG. 6may further illustrate, for example, that an equivalent resistance of approximately 120 M may be achieved utilizing the four cascaded transistor configuration when Vin=500 mV. As another example, an equivalent resistance of approximately 130M may be achieved utilizing the four cascaded configuration when Vin=700 mV. These exemplary resistance values and associated transistor configurations may be used in the RC combination of either LPF150and LPF160, or HPF410and HPF420. In this manner, very high resistance values may be achieved using sub-threshold transistor configurations, which may be implemented in filters used to correct for DC-offset in a variable gain amplifier while avoiding large die area requirements associated with passive resistors or n-well implementations.

Some embodiments may be implemented in a wired system, a wireless system, or a combination of both. When implemented as part of wireless system, VGA100and VGA400may comprise part of a wireless device. A wireless device may be arranged to communicate information over a wireless communication medium, such as radio-frequency (RF) spectrum, for example. The wireless device may include components and interfaces suitable for communicating information signals over the designated RF spectrum. For example, the wireless device may include one or more antennas, wireless RF transmitter/receivers (“transceivers”), amplifiers, filters, control logic, and so forth. Examples of a wireless device may include a mobile or cellular telephone, a computer equipped with a wireless access card or modem, a handheld client device such as a wireless personal digital assistant (PDA), a wireless access point (WAP), a base station (e.g., Node B), a mobile subscriber center (MSC), a radio network controller (RNC), and so forth. The embodiments are not limited in this context.