Semiconductor chip package having contact pins at short side edges

A semiconductor chip package includes a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, a chip pad, and electrical contact elements connected with the semiconductor chip and extending outwardly. The encapsulation body has six side faces and the electrical contact elements extend exclusively through two opposing side faces which have the smallest surface areas from all the side faces. The semiconductor chip is disposed on the chip pad, and a main face of the chip pad remote from the semiconductor chip is at least partially exposed to the outside.

PRIORITY CLAIM

This application claims priority to German Patent Application No. 10 2015 101 674.5 filed on 5 Feb. 2015, the content of said application incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to the field of semiconductor chip packages.

BACKGROUND

A semiconductor package may comprise a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, and electrical contact elements connected with the semiconductor chip and extending through the encapsulation body in an outward direction. The electrical contact elements can be formed in a different way for serving different desires or requirements on the customer's side. According to one variant the semiconductor package is formed as a through-hole device in which the electrical contact elements are formed as contact pins to be inserted in through-hole sockets on the customer's side. According to another variant the semiconductor package is formed as a surface mount device in which the electrical contact elements are formed with flat coplanar lower surfaces to be attached on a suitable contact surface on the customer's side. For the fabrication of semiconductor chip packages and their electrical contact elements other aspects have to be taken also into consideration. One aspect may be that the semiconductor chip may produce heat during operation and the complete design of the semiconductor chip package may have to be optimized to facilitate most efficient heat dissipation. Another aspect concerns the fabrication process of the semiconductor chip package, in particular the problem of how to increase the leadframe density in the fabrication process and thereby to decrease the fabrication costs per each semiconductor chip package.

SUMMARY

According to an embodiment of a semiconductor chip package, the semiconductor chip package comprises a semiconductor chip, an encapsulation body encapsulating the semiconductor chip, electrical contact elements connected with the semiconductor chip and extending outwardly, and a chip pad on which the semiconductor chip is disposed. The encapsulation body has six side faces and the electrical contact elements extending exclusively through two opposing side faces which have the smallest surface areas from all the side faces. The chip pad has a main face remote from the semiconductor chip and at least partially exposed to the outside.

According to another embodiment of a semiconductor chip package, the semiconductor chip package comprises a chip pad, a semiconductor chip disposed on the chip pad, an encapsulation body encapsulating the semiconductor chip, and electrical contact elements connected with the semiconductor chip and extending outwardly. The encapsulation body has a rectangular shape and the electrical contact elements extend exclusively through two opposing short sides of the rectangle and a main face of the chip pad remote from the semiconductor chip is at least partially exposed to the outside.

According to yet another embodiment of a semiconductor chip package, the semiconductor chip package comprises a leadframe comprising a chip pad and electrical contact elements, a semiconductor chip disposed on the chip pad, and an encapsulation body encapsulating the semiconductor chip and a portion of the leadframe in such a way that a main face of the chip pad remote from the semiconductor chip is exposed to the outside. The electrical contact elements are connected with the semiconductor chip and extend outwardly.

DETAILED DESCRIPTION

As employed in this specification, the terms “bonded”, “attached”, “connected”, “coupled” and/or “electrically connected/electrically coupled” are not meant to mean that the elements or layers must directly be contacted together; intervening elements or layers may be provided between the “bonded”, “attached”, “connected”, “coupled” and/or “electrically connected/electrically coupled” elements, respectively. However, in accordance with the disclosure, the above-mentioned terms may, optionally, also have the specific meaning that the elements or layers are directly contacted together, i.e. that no intervening elements or layers are provided between the “bonded”, “attached”, “connected”, “coupled” and/or “electrically connected/electrically coupled” elements, respectively.

Further, the word “over” used with regard to a part, element or material layer formed or located “over” a surface may be used herein to mean that the part, element or material layer be located (e.g. placed, formed, deposited, etc.) “indirectly on” the implied surface with one or more additional parts, elements or layers being arranged between the implied surface and the part, element or material layer. However, the word “over” used with regard to a part, element or material layer formed or located “over” a surface may, optionally, also have the specific meaning that the part, element or material layer be located (e.g. placed, formed, deposited, etc.) “directly on”, e.g. in direct contact with, the implied surface.

Devices or semiconductor packages containing semiconductor chips are described below. The semiconductor chips may be of different types, may be manufactured by different technologies and may include for example integrated electrical, electro-optical or electro-mechanical circuits and/or passives. The semiconductor chips may, for example, be designed as logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, power integrated circuits, memory circuits or integrated passives. They may include control circuits, microprocessors or micro-electromechanical components. Further, they may be configured as power semiconductor chips, such as power MOSFETs (Metal-oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), JFETs (Junction Gate Field Effect Transistors), power bipolar transistors or power diodes. In particular, semiconductor chips having a vertical structure may be involved, that is to say that the semiconductor chips may be fabricated in such a way that electric currents can flow in a direction perpendicular to the main faces of the semiconductor chips. A semiconductor chip having a vertical structure may have contact elements in particular on its two main faces, that is to say on its top side and bottom side. In particular, power semiconductor chips may have a vertical structure. By way of example, the source electrode and gate electrode of a power MOSFET may be situated on one main face, while the drain electrode of the power MOSFET is arranged on the other main face. Furthermore, the electronic modules described below may include integrated circuits to control the integrated circuits of other semiconductor chips, for example the integrated circuits of power semiconductor chips. The semiconductor chips can be manufactured on the basis of a specific semiconductor material, for example Si, SiC, SiGe, GaAs, GaN, AlGaAs, but can also manufactured on the basis of any other semiconductor material and, furthermore, may contain inorganic and/or organic materials that are not semiconductors, such as for example insulators, plastics or metals.

The semiconductor chips or at least parts of the semiconductor chips are covered with an encapsulating material to form an encapsulation (e.g. a molded body), which may be electrically insulating. The encapsulation may be a dielectric material and may be made of any appropriate duroplastic, thermoplastic or thermosetting material or laminate (prepreg). The encapsulant may contain filler materials. After its deposition, the encapsulant may be only partially hardened and may be completely hardened after application of energy (e.g. heat, UV light, etc.) to form an encapsulant. Various techniques may be employed to cover the semiconductor chips with the encapsulant, for example compression molding, injection molding, powder molding, liquid molding, dispensing or laminating.

FIG. 1shows an example of a semiconductor chip package10according to an example in a schematic cross-sectional side view representation (A) and in a top view representation (B). The cross-sectional representation (A) has been taken in a plane as indicated by line A-A in the top view representation (B). The semiconductor chip package10comprises a semiconductor chip11, an encapsulation body12encapsulating the semiconductor chip11, a chip pad13.2having the semiconductor chip11disposed thereon, and electrical contact elements13.1connected with the semiconductor chip11and extending through the encapsulation body12in an outward direction. The encapsulation body12comprises six side faces12A to12F. The electrical contact elements13.1extend exclusively through two opposing side faces12C and12D which have the smallest surface areas from all the side faces12A to12F. A main face of the chip pad13.2remote from the semiconductor chip11is at least partially exposed to the outside.

According to an example of the semiconductor chip package10ofFIG. 1, the six side faces12A to12F comprise two opposing main faces12E and12F which have the largest surface areas from all the side faces12A to12F. The semiconductor chip11can be disposed within the encapsulation body12in such a way that the main plane of the chip is arranged in parallel to the two main faces12E and12F.

According to an example of the semiconductor chip package10ofFIG. 1, the semiconductor chip package10comprises a leadframe13comprising the electrical contact elements13.1and the chip pad13.2. In the example shown inFIG. 1, the complete upper main face of the chip pad13.2is exposed to the outside. It can, however, also be the case that only a portion of the upper main face of the chip pad13.2is exposed to the outside. Anyway, such a configuration allows the user to attach a heat sink onto the semiconductor chip package10so that excessive heat produced by the semiconductor chip11can be effectively dissipated. In this way it is possible to effectively spatially separate the electrical and thermal pathways from each other as a major amount of the heat will be dissipated through the chip pad13.2and the heat sink.

According to an example of the semiconductor chip package10ofFIG. 1, the chip pad13.2is connected with one or more of the electrical contact elements13.1. It can, for example, be contiguous with one or more of the electrical contact elements13.1, in particular be formed out of a portion of a leadframe. According to another example the chip pad is not connected to anyone of the electrical contact elements.

According to an example of the semiconductor chip package10ofFIG. 1, the electrical contact elements13.1are configured as contact pins as shown in the schematic cross-sectional side view representation (A) so that the package is construed as a through-hole device. According to another example, the semiconductor chip package can also be construed as a surface mount device. An embodiment thereof will be shown later.

According to an example of the semiconductor chip package10ofFIG. 1, the electrical contact elements13.1comprise first electrical contact elements arranged at the side face12D and being contiguous with the chip pad13.2, and second electrical contact elements13.1arranged at the side face12C not being contiguous with the chip pad13.2. More specifically, it can be the case that the semiconductor chip11is comprised of an insulated gate bipolar transistor (IGBT) having a drain contact pad at an upper surface thereof and a gate contact pad arranged on a lower surface, a source contact pad arranged on the lower surface, and a source sense contact pad arranged on the lower surface. In this case the first electrical contact elements13.1, arranged at the side face12D, are all electrically connected with the chip pad13.2and thus with the drain contact element and are therefore designated with “D” in the top view representation (B). The second electrical contact elements13.1are designated with “S” and “G” in the top view representation (B) which means that they are connected by wire bonds14to either one of the gate, source or source sense contact pads on the lower surface of the semiconductor chip11. A specific embodiment thereof will be shown and explained in greater detail in connection withFIG. 3.

According to an example of the semiconductor chip package10ofFIG. 1, the semiconductor chip package10comprises one and only one semiconductor chip11as shown inFIG. 1or it may also contain more than one semiconductor chip. It may also contain one or more semiconductor chips and, in addition thereto, one or more passive devices like e.g. resistors, inductors or capacitors which may also be arranged on portions of the leadframe. According to an example, the semiconductor chip11comprises one or more of a transistor, a metal-oxide semiconductor transistor, a vertical transistor, an insulated gate bipolar transistor, and a power transistor.

According to an example of the semiconductor chip package10ofFIG. 1, the encapsulation body12comprises a rectangular cross-section as shown in the schematic cross-sectional side view representation (A) and the electrical contact elements13.1extend exclusively through two opposing short sides of the rectangle which correspond to the side faces designated with the reference numbers12C and12D in the schematic cross-sectional side view representation (A). According to an example thereof, a ratio between a length of the long side of the rectangle, i.e. a length of one of the side faces12E and12F, and a length of the short side of the rectangle, i.e. a length of one of the side faces12C and12D, is between 2 and 3 or greater than 3.

According to an example of the semiconductor chip package10ofFIG. 1, the semiconductor chip package10comprises the form of a cuboid. A length of the semiconductor chip package10may be defined as a distance between the side faces12C and12D, a width of the semiconductor chip package10may be defined as a distance between the side faces12A and12B, and a height of the semiconductor chip package10may be defined as a distance between the side faces12E and12F. According to an example, the length of the semiconductor chip package10may be in a range from 10 mm to 25 mm, the width of the semiconductor chip package10may be in a range from 4 mm to 10 mm, and the height of the semiconductor chip package10may be in a range from 1 mm to 4 mm.

FIG. 2shows an example of a semiconductor chip package20being construed as a surface mount device in a cross-sectional representation (A) and in a perspective top view representation (B). The semiconductor chip package20ofFIG. 2comprises a semiconductor chip (not shown), an encapsulation body22, and electrical contact elements23.1connected with the semiconductor chip and extending through the encapsulation body22in an outward direction. The electrical contact elements23.1first extend in a lateral direction such as the electrical contact elements13.1of the example ofFIG. 1, but are then bent in such a way that their lower surfaces are coplanar so that the semiconductor chip package20can be used as a surface mount device on the customer's side.

The other details of the semiconductor chip package20ofFIG. 2may be similar to those of the example as shown inFIG. 1. In particular, the electrical contact elements23.1may be part of a leadframe23, wherein the leadframe23further comprises a chip pad23.2to which the semiconductor chip is attached.

FIG. 3shows an assembly comprising a leadframe33and a semiconductor chip31connected to the leadframe33. The assembly, as shown inFIG. 3, shows how the semiconductor chip package20ofFIG. 2may have looked like in a perspective down view representation before applying the encapsulation body22to it. The semiconductor chip31may be comprised of an insulated gate bipolar (IGB) transistor being attached with its drain pad surface to the chip pad33.2. The upper right electrical contact elements33.1are contiguous with the chip pad33.2and thus on the same electrical potential as the drain contact. The upper surface of the semiconductor chips31comprise a large source pad area and small gate pad and source sense areas. The large source pad area is connected to three ones of the lower left electrical contact elements33.1by means of two wire bonds34which are both connected to two different contact areas of the large source contact pad. The other two lower left electrical contact elements33.1are connected with wire bonds to the gate and source sense pads.