Embedded MRAM structure and method of fabricating the same

An embedded MRAM structure includes a substrate divided into a memory cell region and a logic device region. An active area is disposed in the memory cell region. A word line is disposed on the substrate and crosses the active area. A source plug is disposed in the active area and at one side of the word line. A drain plug is disposed in the in the active area and at another side of the word line. When viewing from a direction perpendicular to the top surface of the substrate and taking the word line as a symmetric axis, the source plug is a mirror image of the drain plug.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an embedded MRAM (magnetoresistive random access memory) structure and a method of fabricating the same, and more particularly to a method of forming an MRAM structure with a top surface of a source line aligned with a top surface of a second metal layer.

2. Description of the Prior Art

Many modern day electronic devices contain electronic memory configured to store data. Electronic memory may be volatile memory or non-volatile memory. Volatile memory stores data only while it is powered, while non-volatile memory is able to store data when power is removed. MRAM is one promising candidate for next generation non-volatile memory technology. An MRAM cell includes a magnetic tunnel junction (MTJ) unit having a variable resistance, located between two electrodes disposed within back-end-of-the-line (BEOL) metallization layers.

An MTJ unit generally includes a layered structure comprising a reference layer, a free layer and a dielectric barrier in between. The reference layer of magnetic material has a magnetic vector that always points in the same direction. The magnetic vector of the free layer is free, but is determined by the physical dimensions of the element. The magnetic vector of the free layer points in either of two directions: parallel or anti-parallel with the magnetization direction of the pinned layer.

However, conventional fabricating processes of MRAMs still have drawbacks. For example, integrity the standard type MRAMs needs to be improved. Therefore, a new fabricating method of the standard type MRAMs is therefore required in the field.

SUMMARY OF THE INVENTION

In light of the above, the present invention provides a method of fabricating an embedded MRAM structure with a source line and a second metal layer in the logic device region at the same height.

According to a preferred embodiment of the present invention, an embedded MRAM structure includes a substrate divided into a memory cell region and a logic device region. An active area is disposed in the memory cell region. A first word line is disposed on the substrate and crosses the active area. A source plug is disposed in the active area and at one side of the first word line. A drain plug is disposed in the active area and at another side of the first word line, wherein when viewing from a direction perpendicular to a top surface of the substrate and taking the first word line as a symmetric axis, the source plug is a mirror image of the drain plug. A first source metal layer contacts the source plug and a first drain metal layer contacts the drain plug. A first source via plug contacts the first source metal layer and a first drain via plug contacts the first drain metal layer. A source line contacts the first source via plug and a second drain metal layer contacts the first drain via plug, wherein a top surface of the source line is aligned with a top surface of the second drain metal layer. A tungsten plug contacts the second drain metal layer. An MTJ unit contacts the tungsten plug. A third drain via plug contacts the MTJ unit. A bit line contacts the third drain via plug.

According to another preferred embodiment of the present invention, a method of fabricating an embedded MRAM includes providing a substrate divided into a memory cell region and a logic device region. An active area is disposed in the memory cell region and a first word line is disposed on the substrate and crosses the active area. Next, a source plug is formed to contact the active area and is disposed at one side of the first word line. A drain plug is formed to contact the active area and at another side of the first word line, wherein when viewing from a direction perpendicular to a top surface of the substrate and taking the first word line as a symmetric axis, the source plug is a mirror image of the drain plug. Later, the first source metal layer contacting the source plug and a first drain metal layer contacting the drain plug are simultaneously formed. After that, a first source via plug contacting the first source metal layer and a first drain via plug contacting the first drain metal layer are simultaneously formed. Subsequently, a source line contacting the first source via plug and a second drain metal layer contacting the first drain via plug are simultaneously formed, wherein a top surface of the source line is aligned with a top surface of the second drain metal layer. Next, a tungsten plug is formed to contact the second drain metal layer. Later, an MTJ unit is formed to contact the tungsten plug. After that, a third drain via plug is formed to contacting the MTJ unit. Finally, a bit line is formed to contact the third drain via plug.

DETAILED DESCRIPTION

FIG. 1toFIG. 8depict a fabricating method of an embedded MRAM structure according to a preferred embodiment of the present invention.FIG. 2depicts a sectional view respectively taken along a line A-A′ and a line B-B′ shown inFIG. 1.

As shown inFIG. 1, a substrate10is provided. The substrate10is divided into a memory cell region M and a logic device region L. Numerous active areas12are disposed on the substrate10. Several insulating layers14respectively disposed between active areas12to insulate adjacent active areas12. Moreover, numerous word lines WL1/WL2are disposed on the substrate10. Each of the word lines WL1/WL2crosses the active areas12. A dummy gate line WL3can be disposed between the word lines WL1/WL2based on the circuit layout. Later, P-type or N-type dopants are implanted into two sides of each of the word lines WL1/WL2and the dummy word line WL3to form numerous doping regions16/18. Each of the doping regions16/18are within the active areas12. Several embedded MRAM structures and logic devices will be formed by using numerous word lines WL1/WL2, numerous active areas12, and numerous doping regions16/18mentioned above. The following fabricating process will be described by illustrating a single embedded MRAM structure and a single logic device as an example.

The region X inFIG. 1indicates a range where a single embedded MRAM structure will be formed later. The region Y indicates a range where a single logic device will be formed later. Please refer toFIG. 1andFIG. 2. Two source plugs20and two drain plugs22are formed in the region X simultaneously. Meanwhile, two plugs24are formed in the region Y. The source plugs20are disposed in the active area12within the memory cell region M. The source plugs20contact the doping region16and are disposed at one side of the word line WL1. The drain plugs are disposed in the active area12within the memory cell region M. The drain plugs22contact doping region16and are disposed at another side of the word line WL1. The plugs24are disposed within the logic device region L, contact the doping region18and at two sides of the word line WL2. The number of the source plugs20can be more than two, and the number of the drain plugs20can also be more than two. As shown inFIG. 1andFIG. 2, when viewing from a direction perpendicular to a top surface11of the substrate10and taking the word line WL as a symmetric axis, the source plugs20are a mirror image of the drain plugs22. That is, when viewing from the direction perpendicular to the top surface11of the substrate10, the position of the source plugs20and the drain plugs22are in a symmetric layout by taking the word line WL1as the symmetric axis.

FIG. 9depicts a layout of source plugs and drain plugs according to another preferred embodiment of the present invention.FIG. 10depicts a layout of source plugs and drain plugs according to yet another preferred embodiment of the present invention. Elements inFIG. 9andFIG. 10which are substantially the same as those inFIG. 1are denoted by the same reference numerals; an accompanying explanation is therefore omitted. The modification ofFIG. 9andFIG. 10with respective toFIG. 1is the shape and number of the drain plugs and source plugs.

The difference betweenFIG. 9andFIG. 1is that the source plug20and the drain plug22inFIG. 9are respectively in a shape of a strip. The occupied area of the single strip-shaped source plug20inFIG. 9is greater than that of the single source plug20inFIG. 1. The occupied area of the single strip-shaped drain plug22inFIG. 9is greater than that of the single drain plug22inFIG. 1. The difference betweenFIG. 10andFIG. 1is that the numbers of the source plug20and the drain plug22. InFIG. 10, the number of the source plug20and the drain plug22are both one. However, the size of the source plug20inFIG. 10is the same as the size of source plug20inFIG. 1. The size of the drain plug22inFIG. 10is the same as the size of the drain plug22inFIG. 1. As shown inFIG. 9andFIG. 10, when viewing from the direction perpendicular to the top surface11(please refer toFIG. 2for the position of the top surface11) of the substrate10and taking the word line WL1as a symmetric axis, the source plug20is a mirror image of the drain plug22.

FIG. 3depicts a fabricating stage followingFIG. 1.FIG. 4depicts a sectional view respectively taken along a line C-C′ and a line D-D′ inFIG. 3. As shown inFIG. 3andFIG. 4, a first source metal layer M1S contacting the source plugs20and a first drain metal layer M1dcontacting drain plugs22are simultaneously formed within the memory cell region M. Meanwhile, a first metal layer M1contacting plug24is formed in the logic device region L. In other words, the first source metal layer MIS, the first drain metal layer M1d, and the first metal layer M1are formed by the same metal deposition process such as a copper damascene process. The top surface of the first source metal layer MIS, the top surface of the first drain metal layer M1dand the top surface of the first metal layer M1are aligned. Later, a first drain via plug V1S contacting the first source metal layer M1S and a drain via plug V1dcontacting the first drain metal layer M1dare simultaneously formed in the memory cell region M. Meanwhile, a first via plug V1contacting the plug24is formed in the logic device region L. The first drain via plug V1S, the drain via plug V1d, and the first via plug V1are formed by the same metal deposition process such as a copper damascene process. Moreover, as shown inFIG. 3, when viewing from a direction perpendicular to the top surface11(please refer toFIG. 2for the position of the top surface11) of the substrate10and taking the word line WL1as a symmetric axis, the first source via plug V1S and the first drain via plug V1dare in an asymmetric layout.

FIG. 5depicts a fabricating stage followingFIG. 3.FIG. 6depicts a sectional view respectively taken along a line E-E′ and a line F-F′ inFIG. 5. As shown inFIG. 5andFIG. 6, a source line SL and a second drain metal layer M2dare simultaneously formed in the memory cell region M. Meanwhile, a second metal layer M2is formed to contact the first via plug V1within the logic device region L. The source line SL contacts the first source via plug V1S. The second drain metal layer M2dcontacts the first drain via plug V1d. The top surface of the source line SL, the top surface of the second drain metal layer M2dand the top surface of the second metal layer M2are aligned. The source line SL, the second drain metal layer M2d, and the second metal layer M2are formed by the same metal deposition process such as a copper damascene process. Please refer toFIG. 5, the source line SL electrically connects to numerous embedded MRAMs. For example, the source line SL electrically connects to the MRAM disposed in the region X and the MRAM disposed in the region Z. In details, each of the MRAMs has the same structure as that of the MRAM in the region X, therefore the source line SL directly contacts the first via plugs V1S respectively in different MRAMs but in the same row.

FIG. 7depicts a fabricating stage followingFIG. 5.FIG. 8depicts a sectional view respectively taken a line G-G′ and a line H-H′ inFIG. 7. As shown inFIG. 7andFIG. 8, a tungsten plug W contacting the second drain metal layer M2dis formed in the memory cell region M. A second via plug V2contacting the second metal layer M2is formed within the logic device region L. A top surface of the tungsten plug W is aligned with a top surface of the second via plug V2. Later, a MTJ unit is formed contacting the tungsten plug W is formed in the memory cell region M. A third metal layer M3contacting the second via plug V2is formed in the logic device region L. Next, a third drain via plug V3dand a third via plug V3are simultaneously formed. The third drain via plug V3dcontacts the MTJ unit MTJ. The third via plug V3contacts the third metal layer M3. The drain via plug V3dand the third via plug V3are formed by the same metal deposition process such as a copper damascene process. A top surface of the third drain via plug V3dand a top surface of the third via plug V3are aligned.

Later, a bit line BL is formed in the memory cell region M and a fourth metal layer M4is formed in the logic device region L. The bit line BL and the fourth metal layer M4are formed simultaneously. The bit line BL contacts the third drain via plug V3d, and the fourth metal layer M4contacts the third via plug V3. A top surface of the fourth metal layer M4and a top surface of the bit line BL are aligned. Now, an MRAM structure100of the present invention is completed.

FIG. 7depicts an embedded MRAM structure according to a preferred embodiment of the present invention.FIG. 8depicts a sectional view respectively taken along a line G-G′ and a line H-H′ inFIG. 7.FIG. 1depicts a top view of an active area, a word line, a source plug and a drain plug of an embedded MRAM structure of the present invention.

As shown inFIG. 7, an embedded MRAM structure100includes a substrate10. The substrate10is divided into a memory cell region M and a logic device region L. Numerous active areas12are disposed in the memory cell region M and the logic device region L (please refer toFIG. 1for the positions of the active areas12). Numerous word lines WL1/WL2are disposed on the substrate10and cross the active areas12. As shown inFIG. 7, numerous embedded MRAM structures which having the structure as that of the embedded MRAM structure50inFIG. 8, and numerous logic devices60which having the structure as that of the logic device60inFIG. 8are disposed on the substrate10. The embedded MRAM structure50inFIG. 8is disposed in the region X inFIG. 7, and the logic device60inFIG. 8is disposed in the region Y inFIG. 7. In the following description, a single embedded MRAM structure50and a single logic device60are illustrated as example. Please refer to the region X inFIG. 1andFIG. 8. At least one source plug20contacts the active area12and is disposed at one side of the word line WL1. At least one drain plug22contacts the active area12and is disposed at another side of the word line WL1. When viewing from a direction perpendicular to a top surface11of the substrate10and taking the word line WL1as a symmetric axis, the source plug20are mirror images of the drain plug22. The numbers of the source plug20and the drain plug22are exemplified as two inFIG. 1. Moreover, as shown inFIG. 10, the number of the source plug20and the drain plug22can be changed to one respectively. Based on different requirements, as shown inFIG. 9, the shapes of the source plug20and the drain plug22can be respectively changed into a strip.

As shown inFIG. 8, the embedded MRAM structure50further includes a first source metal layer M1S contacting the source plug20and a first drain metal layer M1dcontacting the drain plug22. A first drain via plug V1S contacts the first source metal layer M1S and a drain via plug V1dcontacts the first drain metal layer M1d. The source line SL contacts the first source via plug V1S. The second drain metal layer M2dcontacts the first drain via plug V1d. The top surface of the source line SL and the top surface of the second drain metal layer M2dare aligned. A tungsten plug W contacts the second drain metal layer M2d. A MTJ unit MTJ contacts the tungsten plug W. A third drain via plug V3dcontacts the MTJ unit MTJ. A bit line BL contacts the third drain via plug V3d. In detail, the drain plug22, the first drain metal layer M1d, the first drain via plug V1d, the second drain metal layer M2d, the tungsten plug W, the MTJ unit MTJ, the third drain via plug V3dand the bit line BL are stacked from bottom to top. The source plug20, the first source metal layer M1S, the first source via plug V1S and the source line SL are stacked from bottom to top. The first drain metal layer M1d, the first drain via plug V1d, the second drain metal layer M2d, the third drain via plug V3d, the bit line BL, the first source metal layer M1S, the first source via plug V1S and the source line SL includes copper. The drain plug22and the source plug20include aluminum.

As shown inFIG. 7andFIG. 8, the embedded MRAM structure100further includes numerous logic devices and numerous metal interconnections disposed within the logic device region L. In the following description, a logic device60within the region Y and a metal interconnection70are illustrated as example. The logic device60includes a word line WL2disposed on the substrate10. A doping region18is disposed in the substrate10at one side of the second word line WL2. A plug24contacts the doping region18. The metal interconnection70includes a first metal layer M1contacting the plug24, a first via plug V1contacting the first metal layer M1, a second metal layer M2contacting the first via plug V1, a second via plug V2contacting the second metal layer M2, a third metal layer M3contacting the second via plug V2, a third via plug V3contacting the third metal layer M3, a fourth metal layer M4contacting the third via plug V3. A top surface of the second metal layer M2is aligned with the top surface of the source line S. A top surface of the second via plug V2is aligned with a top surface of the tungsten plug W. A top surface of the third metal layer M3is aligned with a top surface of the MTJ unit MTJ. A top surface of the fourth metal layer M4is aligned with a top surface of the bit line BL. The first metal layer M1, the first via plug V1, the second metal layer M2, the second via plug V2, the third metal layer M3, the third via plug V3, the fourth metal layer M4includes copper. The plug24includes aluminum.

The source line in the present invention is disposed at the same height as that of the second metal layer in the logic device region. In this way, the source plug and the drain plug of the embedded MRAM structure can be arranged in a symmetric layout. On the other hand, regarding the MRAM structure with the source line disposed at the same height as that of the first metal layer, the source plug and the drain plug need to be arranged in an asymmetric layout. As a result, the symmetric layout in the present invention can increase the integrity of the embedded MRAM structure.