METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING SEMICONDUCTOR DEVICE

A semiconductor chip is arranged on a region of laser direct structuring (LDS) material of a laminar substrate. The semiconductor chip has a front active area facing towards, and a metallized back surface facing away from, the laminar substrate. An encapsulation of LDS material on the laminar substrate encapsulates the semiconductor chip with the metallized back surface of the semiconductor chip exposed at an outer surface of the encapsulation of LDS material. Electrically conductive lines and first vias are structured in the region of LDS material to electrically connect to the front active area of the semiconductor chip. A thermally conductive layer is plated over the outer surface of the encapsulation of LDS material in contact with the metallized back surface of the semiconductor chip. A heat extractor body of thermally conductive material is coupled in heat transfer relationship with the thermally conductive layer.

PRIORITY CLAIM

This application claims the priority benefit of Italian Application for Patent No. 102021000014906, filed on Jun. 8, 2021, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.

TECHNICAL FIELD

The description relates to manufacturing semiconductor devices.

One or more embodiments may be applied to semiconductor devices where high thermal draining (dissipation) is a desired feature.

BACKGROUND

In those semiconductor devices where high thermal draining (dissipation) is a desired feature, so-called “slug-up” configurations such as slug-up Quad-Flat No-leads or QFN packages are currently used having a heat extractor (heat dissipater or heat sink) mounted on top of an exposed heat slug at the top of the package.

A problem oftentimes encountered with such configurations lies in the die attach material between the back side metallization (BSM) of the semiconductor chip or die in the device and the heat slug.

Such interface material may represent a bottleneck in terms of heat dissipation.

An approach proposed for addressing that issue involves grinding the insulating encapsulation (molding) to expose the semiconductor chip or die at its backside. Such an approach was, however, found to induce undesired cracking, primarily when the semiconductor chip or die is made markedly thinner as a result of grinding.

There is a need in the art to contribute in addressing these issues.

SUMMARY

One or more embodiments relate to a method.

One or more embodiments relate to corresponding semiconductor device.

One or more embodiments provide a semiconductor chip package design that resorts to laser direct structuring (LDS) technology with the capability of achieving high thermal dissipation on top of the package as a result of directly exposing the die surface.

In one or more embodiments, the most critical thermal interface (to die attach material) is virtually eliminated.

One or more embodiments may provide a small, compact package outline that lends itself to being “tuned” starting from a simple leadframe design.

One or more embodiments may exhibit a full plated package top surface where the presence of an exposed die backside can be identified.

DETAILED DESCRIPTION

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale. The edges of features drawn in the figures do not necessarily indicate the termination of the extent of the feature.

In the ensuing description, various specific details are illustrated in order to provide an in-depth understanding of various examples of embodiments according to the description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that various aspects of the embodiments will not be obscured.

Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment”, “in one embodiment”, or the like, that may be present in various points of the present description do not necessarily refer exactly to one and the same embodiment. Furthermore, particular configurations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

The headings/references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments.

Throughout the instant description, the designation laser direct structuring (LDS) will be use to refer to a laser-based technology now currently used in manufacturing semiconductor devices wherein electrically conductive formations such as lines and vias can be formed in an otherwise insulating molding compound via laser beam activation or “structuring”, possibly followed by plating.

Laser direct structuring (LDS) technology (oftentimes referred to also as direct copper interconnection (DCI) technology) is discussed, for instance, in documents such as United States Patent Application Publication Nos. 2018/0342453, 2020/0203264, 2020/0321274, 2021/0050226 or 2021/0050299, all incorporated herein by reference and assigned to the same assignee of the instant application.

Understanding and predicting thermal dissipation performance prior to integrating a semiconductor device on a substrate such as a printed circuit board (PCB) is useful in order to facilitate device operation within defined temperature limits.

When a semiconductor device is running (operated), electrical energy absorbed thereby is transformed into heat.

Efficient and reliable operation of a semiconductor device is facilitated by adequate heat dissipation from the surface of a semiconductor chip or die to its immediate surrounding environment.

This is particularly the case with power packages integrated on substrates such a printed circuit boards (PCBs) where high currents are developed that generate heat during device operation.

Device performance and reliability improves as a result of the thermal dissipation capability of the package being increased with thermal failures avoided.

In conventional devices including a semiconductor chip or die attached on a die pad, the thermal resistance at the interface between the die and the die attach material plays a significant role in determining the thermal performance of the device. To some extent, thermal conductivity of the die attach material is crucial in facilitating adequate device performance.

An approach proposed in the past in order to improve thermal performance involves using so-called “slug-up” packages having an exposed pad at the front (top) side that facilitates extraction of heat from the front or top surface of a semiconductor die using an external heat dissipator.

A somewhat similar approach involves package grinding to expose the die backside to facilitate heat transfer to a heat sink.

Even leaving other points aside, it is noted that common slug-up packages are not able to adequately exploit the top side surface for heat extraction, with the die attach material still found to represent a bottleneck in determining device thermal performance.

Also, a package grinding process as proposed was found to create die strength issues that may result in undesired die cracks.

One or more embodiments may involve starting from a (planar) substrate10that can be essentially likened to a so-called “pre-molded” leadframe.

The designation “leadframe” (or “lead frame”) is currently used (see, for instance the USPC Consolidated Glossary of the United States Patent and Trademark Office) to indicate a metal frame that provides support for an integrated circuit chip or die as well as electrical leads to interconnect the integrated circuit in the die or chip to other electrical components or contacts.

Leadframes are conventionally created using technologies such as a photo-etching technology. With this technology, metal (e.g., copper) material in the form of a foil or tape is etched on the top and bottom sides to create various pads and leads.

Pre-molded leadframes are currently used that include electrically insulating resin such as epoxy resin, for instance, molded onto a sculptured (e.g., photo-etched) leadframe using a flat molding tool, for instance. Spaces left in the etched metal material are filled by pre-molding resin and the resulting leadframe has a total thickness that is the same thickness of the original etched leadframe.

Essentially, the substrate10illustrate in the figures can be considered as a pre-molded leadframe wherein (only) electrically conductive connecting bars12providing a sculptured (e.g., etched) electrically conductive structure onto which an insulating material such as LDS material14is molded.

Providing such a substrate10involves otherwise conventional processes (e.g., using a flat molding tool), which makes it unnecessary to provide a more detailed description herein.

The insulating material14between the connecting bars12being an LDS material is beneficial in so far as a plating process can be applied thereto as discussed in the following.

FIG.2is exemplary of an insulating film16being laminated onto one (here front or top) surface of the structure ofFIG.1.

An Ajinomoto Build-up Film (ABF) from Ajinomoto, for instance, is exemplary of an insulating film that can be advantageously used in arrangements as discussed herein.

FIG.3is exemplary of semiconductor chips or dice18being placed onto the insulating film16at the molding compound portions14between the connecting bars12of the structure illustrated in the previous figures.

As illustrated in the right-hand side ofFIG.2(where one die18is reproduced in an enlarged scale) the dice12are placed onto the film16turned upside-down, namely with their active area18A provided at the front or top surface of the die12placed facing downwards adjacent the insulating film16and the back side metallization BSN layer18B of the die18facing upwards, away from the insulating film16.

It is noted thatFIGS.1to7herein refer to plural semiconductor devices being produced simultaneously to be finally separated in a “singulation” step (seeFIG.7) as otherwise conventional in the art.

FIG.4is exemplary of an encapsulation (cap) of LDS molding compound20being formed (in a manner known per se to those of skill in the art) onto the structure ofFIG.3so that the devices18are embedded in the encapsulation20.

FIG.5is exemplary of laser beam processing (generally indicated LB) applied to both sides of the structure ofFIG.4.

Such laser beam processing can be performed using a laser beam sources as currently used in LDS technology with a two-fold purpose.

In the first place, laser beam processing LB is applied to the LDS encapsulation or cap20to ablate the encapsulation or cap down to the level of the backside metallization layers18B of the semiconductor dice18so that the metallization layers18B are exposed at the (ablated) surface of the LDS encapsulation or cap20.

In the second place, laser beam processing LB results in vias being drilled through the LDS material both in the portions14of the substrate10and in the LDS encapsulation or cup20.

Specifically: first vias140are structured (drilled) extending from the outer (here lower) surface of the portions14of the substrate10up to the active areas18A of the dice18together with a pattern of lines142at the outer (here lower) surface of the substrate10; and second vias200are structured (drilled) extending from the outer (here upper) surface of the encapsulation or cap20down to the connecting bars12in the substrate10.

As illustrated, both vias140and200extend through the insulating layer16.

FIG.6is exemplary of plating processing applied (as otherwise conventional in the art) to the vias140and200structured via laser beam energy LB applied as discussed previously in connection withFIG.5.

In the first place, such plating has the purpose of facilitating making the vias140and200electrically conductive.

In the second place: with respect to the vias140provided through the substrate10, the plating has the purpose of creating a pattern of electrically-conductive lines142at the outer (here lower) surface of the substrate10that cooperate with the vias140in providing electrical connection for the active areas18A of the dice18; and with respect to the LDS molding compound encapsulation or cap20, the plating is performed in such a way to form a backside metallization layer220that extends over the (entire) outer—here upper—surface of encapsulation or cap20.

Plating the metallization layer220is facilitated by the electrically conductive path(s) provided by the vias200and the connecting bars12in the substrate10.

In one or more embodiments, plating the metallization layer220is further facilitated by the provision of a pre-molded leadframe substrate10wherein the connecting bars12form a mesh pattern, for example a rectangular mesh pattern, of electrically connected conductive material regions12.

A structure as illustrated inFIG.6can then be singulated via sawing blades B, as exemplified inFIG.7, thereby providing individual semiconductor devices100.

Devices such as100can then be arranged (in manner known per se to those of skill in the art) on a support substrate S such as a printed circuit board or PCB as represented inFIGS.8and9with the electrical-conductive lines142facing the substrate S and providing a desired routing pattern of electrical connections for the semiconductor die or dice18.

An external heat extractor (heat sink) HE can be coupled (for instance soldered at a solder layer222) in heat transfer relationship to the (metal) plated layer220formed on the exposed backside metallization18B of the die or dice18is exposed.

FIG.8refers by way of example to an arrangement where a respective individual heat extractor HE is coupled to a single device100.

FIG.9refers, again by way of example, to an arrangement where a heat extractor HE is coupled to plural (e.g., two) devices100.

FIG.7is exemplary of blades B used for cutting at the regions12of electrically conductive material the laminar substrate10having a plurality of semiconductor chips18arranged thereon, with the encapsulation20of LDS material formed thereon and processed with laser direct structuring processing LB applied thereto.

Cutting (singulation) at the regions12as exemplified inFIG.7removes the regions12as well the (second) vias200that extend through the encapsulation20of LDS material and produces a plurality of singulated semiconductor devices100each comprising a respective portion of the thermally conductive layer220.

FIG.8is thus exemplary of coupling a heat extractor body HE of thermally conductive material in heat transfer relationship with (such a respective portion of) the thermally conductive layer220.

Conversely,FIG.9is exemplary of coupling a single (common) heat extractor body HE of thermally conductive material in heat transfer relationship with respective portions of the thermally conductive layer220in two (or more) semiconductor devices100.

Using a heat extractor HE common to plural devices100as exemplified inFIG.9may turn out to be beneficial in order to improve heat dissipation by facilitating convection flows, for instance.

A backside metallization layer such as the layer220, plated on the exposed backside metallization18B of the die or dice18, facilitates heat dissipation towards the heat extractor104by avoiding conventional die attach material and provide effective heat dissipation over the whole surface of the package.

The resulting outline is small and compact in so far as a conventional leadframe is no longer employed.

Simulation experiments have shown that an arrangement as disclosed herein may provide a noteworthy reduction (−27%, for instance) in the temperature reached during operation in a power semiconductor device.

Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described herein merely by way of example without departing from the extent of protection.

The claims are an integral part of the technical teaching provided herein respect of the embodiments.

The extent of protection is determined by the annexed claims.