Techniques to dynamically enable memory channels on a compute platform

Various embodiments are generally directed to an apparatus, method and other techniques to determine one or more memory channels of a plurality of memory channels to be enabled based on an indication received from a basic input/output system (BIOS), determine whether a number of the one or more memory channels to be enabled is greater than a maximum number of memory channels permitted, cause a platform reset if the number of the one or more memory channels is greater than the maximum number of memory channels, and permit enablement of the one or more memory channels if the number of the one or more memory channels is not greater than the maximum number of memory channels.

TECHNICAL FIELD

Embodiments described herein generally include determining memory channels to enable in a compute platform and enabling the memory channels.

BACKGROUND

To meet increasing performance demands in a compute environment there is a trend to increase the number of processing cores and memory bandwidth for processor components. Typically, as the number of processing cores and memory bandwidth increase so does the number of memory channels. However, different users may require different performance demands. Thus, a one size fits all approach is cost prohibitive and does not work. Current solutions statically configure memory channels and core counts based on price and performance. However, statically configuring limits original equipment manufacturers flexibility and can lead to divergent designs. Thus, embodiments discussed herein solve these and other problems to provide a more flexible approach for compute systems.

DETAILED DESCRIPTION

Various embodiments may be generally directed to custom configuring and dynamically enabling memory channels in a compute environment. How many memory channels and which memory channels are to be enabled may be determined by a user, a customer, a board manufacturer, etc. and set via one or more configurable settings in a basic input/output system (BIOS). Embodiments also include enforcing memory channel count compliance, such that the number of memory channels to be enabled does not exceed the number of permitted memory channels to be enabled for a processor device, e.g. computer process unit (CPU) or system on chip (SoC).

More specifically, embodiments include determining one or more memory channels of a plurality of memory channels to be enabled based on an indication received from a basic input/output system (BIOS). For example, a power control unit (PCU) may receive a mailbox command from the BIOS, which includes one or more bits set in a PCU register. The one or more bits set may indicate the number of and which memory channels are to be enabled (or disabled) for a system. Moreover, each memory channel may have a corresponding bit in the PCU register, that when set, indicates that the corresponding memory channel is to be enabled. In some embodiments, the opposite logic may be utilized such that a bit set may indicate that the corresponding memory channel is to be disabled. Embodiments are not limited in this manner.

Embodiments also include determining whether a number of the one or more memory channels to be enabled is greater than a maximum number of memory channels permitted at block410. More specifically, the PCU may determine the maximum number of memory channels permitted based on an indication in a capability identification (CapID) register. The PCU may perform a comparison to determine whether the number of memory channels to be enabled is greater than the maximum number of memory channels permitted. In some embodiments, the PCU may perform the determination with opposite logic, e.g. the PCU may determine whether the number of memory channels to be enabled is less than (or equal) to the maximum number of memory channels permitted.

Based on the determination, embodiments include causing a platform reset if the number of the one or more memory channels is greater than the maximum number of memory channels. For example, the PCU may issue a machine-check exception (MCE) to cause a compute system to reset. In some embodiments, the PCU may cause an indication to be presented on a display indicating that the number of memory channels attempting to be enabled is greater than the maximum number of memory channels permitted to be enabled for a processor device. Further, embodiments also include permitting enablement of the one or more memory channels if the number of the one or more memory channels is not greater than the maximum number of memory channels. For example, the PCU may provide an indication to the BIOS that it may complete the boot process. These and other details will become more apparent in the following description.

FIG. 1illustrates an example embodiment of a compute system100. In various embodiments, system100may be representative of a system or architecture suitable for use with one or more embodiments described herein. However, the embodiments are not limited in this respect.

As shown inFIG. 1, system100may include multiple elements connected via one or more interconnects130. One or more elements may be implemented using circuits, components, registers, processors, software subroutines, modules, or any combination thereof, as desired for a given set of design or performance constraints. Further, the one or more interconnects130may be any type of interconnect including, but not limited to, one or more buses, control lines, data lines, and traces. Example of the interconnects130may operate in accordance with one or more standards, such as the Quick Path Interconnect Ver. 1.1 standard or any predecessors, revisions, or variants thereof, Peripheral Component Interconnect (PCI) Ver. 2.2 standard or any predecessors, revisions, or variants thereof, PCI Express (PCIe) interconnect standard revision 3.1a or any predecessors, revisions, or variants thereof, HyperTransport standard version 3.1 or any predecessors, revisions, or variants thereof, System Management Bus (SMBus) standard version 3 or any predecessors, revisions, or variants thereof, Direct Media Interface (DMI) standard version 3.0 or any predecessors, revisions, or variants thereof. Embodiments are not limited to these examples.

AlthoughFIG. 1shows a limited number of elements in a certain topology by way of example, it can be appreciated that more or fewer elements in any suitable topology may be used in system100as desired for a given implementation. The embodiments are not limited in this context. Moreover, compute system100may be any type of computer or processing device including a personal computer, desktop computer, tablet computer, netbook computer, notebook computer, laptop computer, server, server farm, blade server, or any other type of server, and so forth.

In various embodiments, compute system100may include a processor device120. The processor device120may be one or more of any type of computational element, such as but not limited to, a computer processor unit (CPU), a microprocessor, a processor, central processing unit, digital signal processing unit, dual core processor, multi-core processor, mobile device processor, desktop processor, single core processor, a system-on-chip (SoC) device, complex instruction set computing (CISC) microprocessor, a reduced instruction set (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or any other type of processor or processing circuit on a single chip or integrated circuit. As will be discussed in more detail below, the processor device120may include a number of elements on-die such as one or more cores, a power control unit (PCU), one or more registers, cache, one or more integrated memory controllers, a graphics processor, display controller, one or more input/output (I/O) controllers, and other elements such as a clock, execution unit, and so forth. The processor device120may be connected to and communicate with the other elements of the computing system100via one or more interconnects130.

In embodiments, the processor device120may be coupled with one or more I/O adapters105. Examples of I/O adapters105may include Universal Serial Bus (USB) ports/adapters, IEEE 1394 Firewire ports/adapters, and so forth. The embodiments are not limited in this context. The I/O adapters105may couple with one or more other devices.

In embodiments, the processor device120may be coupled with storage115. Storage115may be implemented as a non-volatile storage device such as, but not limited to, a magnetic disk drive, optical disk drive, tape drive, an internal storage device, an attached storage device, flash memory, and/or a network accessible storage device. In embodiments, storage115may include technology to increase the storage performance enhanced protection for valuable digital media when multiple hard drives are included, for example. Further examples of storage115may include a hard disk, magnetic media, magneto-optical media, removable memory cards or disks, or the like. The embodiments are not limited in this context.

In embodiments, the compute system100may include memory110coupled with the processor device120. Memory110may be coupled with the processor device120via the one or more interconnects130, or by a dedicated memory bus between processor device120and the memory110, as desired for a given implementation.

The memory110may be implemented using any machine-readable or computer-readable media capable of storing data, including both volatile and non-volatile memory. In some embodiments, the machine-readable or computer-readable medium may include a non-transitory medium. The embodiments are not limited in this context. In some embodiments, storage115may be volatile memory, e.g. dynamic random access memory (DRAM), double data rate (DDR) DRAM, synchronous dynamic random-access memory (SDRAM), DDR SDRAM, and so forth. Moreover, the memory110may be 3D XPoint memory, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory such as ferroelectric polymer memory, ferroelectric transistor random access memory (FeTRAM or FeRAM), nanowire, phase change memory, magnetoresistive random access memory (MRAM), spin transfer torque MRAM (STT-MRAM) memory, or the like.

In embodiments, processor device120may communicate with the memory110via one or more memory channels, which may include a multi-channel memory architecture. The one or more memory channels effectively increase the data rate between the processor device120, and in particular, a memory controller and the memory110by approximately the number of channels. For example, in a dual-channel memory architecture, the data rate approximately doubles. In another example, in a quad-channel memory architecture the data rate approximately quadruples. In embodiments, each of the memory channels may be coupled with a corresponding dual in-line memory module (DIMM) slot capable of coupling with a memory module for the memory110. As will be discussed in more detail, the memory channels may be enabled and disabled by a user configuration in a basic input/output system (BIOS)125.

In embodiments, the BIOS125may be a system BIOS, a ROM BIOS, a PC BIOS, unified extensible firmware interface (UEFI), and so forth. The BIOS125may be firmware used to perform hardware initialization during a boot process for the compute system100and provide run-time services for operating systems and programs. The BIOS125may initialize hardware components including initialization of the memory110. For example, as part of the memory initialization, the BIOS125may determine a number of memory channels to enable for the compute system100, determine whether any memory modules/DIMMs have failed a memory test, and map the memory channels to memory. In previous systems, the number of memory channels to be enabled on a system was fixed and fused based on a stock keeping unit (SKU) for a processor device (CPU/SoC). However, in embodiments discussed herein, the number of memory channels enabled may be dynamically adjusted (between boot cycles) via a BIOS interface as long as the number does not exceed a maximum number of permitted memory channels for a processor device. The maximum number of memory channels may be indicated in a capability identification register, which can be read by the BIOS125and provided to a power control unit (PCU) to perform a verification. Embodiments include ensuring that the maximum number of memory channels permitted is not exceeded via a power control unit (PCU), for example.

FIG. 2Aillustrates an example embodiment of processor device220A, which may be the same as or similar to processor device120ofFIG. 1. The processor device220A may include a number of elements, including one or more cores202-1through202-x, where x may be any positive integer greater than zero, a power control unit (PCU)204, and a number of registers, including a capability identification register206, a PCU register208, and a memory channel register210. In embodiments, the processor device220A is not limited to these elements, as they are illustrated based on their relevancy to the details discussed herein.

In embodiments, a core202may be an independent processing unit including circuitry capable of reading, decoding, and executing program instructions. The programming instructions are typical computing processing unit (CPU) instructions. Each of the cores202may be capable of operating and processing the program instructions in parallel, increasing the overall speed at which programming instructions are processed.

The processor device220A also includes a power control unit (PCU), which may be a controller capable of executing instructions, which may be firmware stored in a memory. The PCU204may perform power management operations for the processing device220A and a compute system, for example.

The PCU204may also perform verification and run-time monitoring of memory channels. For example, the PCU204may verify that a number of memory channels to be enabled is less than or equal to a maximum number of memory channels permitted for the processor device220A. The PCU204may determine one or more memory channels of a plurality of memory channels to be enabled based on an indication received from a BIOS. The indication may result from a user setting or selection in the BIOS to enable particular memory channels for a compute system. The PCU204may receive the indication via a mailbox command set by the BIOS. More specifically, the BIOS may set one or more bits in a register, such as power control unit (PCU) register208. The one or more bits may be a bit map such that each bit corresponds to a particular memory channel. Thus, setting a particular bit in the bit map indicates that the corresponding memory channel is to be enabled. The bit map indicates the number of memory channels to be enabled and which memory channels are to be enabled based on the correspondence with the memory channel. In some instances, the bit map of the PCU register208may indicate the opposite logic. In other words, setting a bit in the bit map may indicate that a corresponding memory channel is to be disabled. Embodiments are not limited in this manner.

The PCU204will utilize the number of channels enabled by BIOS to verify that the number of the one or more memory channels to be enabled is less than or equal to (not greater than) a maximum number of memory channels permitted. The PCU204may receive an indication that the BIOS has brought the memory subsystem out of reset via a mailbox command, e.g. setting one or more bits in the PCU register208which may be different bits than the bit map. The PCU204may compare the number of memory channels enabled by the BIOS with the maximum number of permitted memory channels for a processor device. The maximum number of permitted memory channels may be based on an SKU for a processor device, for example. Further, an indication of the maximum number of permitted memory channels may be stored in a capability identification (CapID) register206, which may be a “DDR MC Channel Allowed” register. The PCU204may access the CapID register206to determine the maximum number of permitted memory channels. This CapID register206may be set at the time of manufacture and fused per SKU for a processor device.

Further, the PCU204may take one or more actions if the number of memory channels to be enabled is greater than (or less than/equal) to the number of permitted memory channels. For example, the PCU204may cause a platform reset if the number of memory channels is greater than the maximum number of memory channels permitted. The reset may be a machine check error or exception (MCE) and cause a compute system to perform a soft reset or reboot and require a different number of memory channels to be enabled via the BIOS, for example. Alternatively, the PCU204may permit the enablement of memory channels if the number to be enabled is not greater than the maximum number of memory channels permitted. Thus, a compute system may be permitted to complete the boot process and enter a normal operating state.

The PCU204may also perform real-time monitoring after the initial verification of the memory channels is complete and the memory is initialized. The real-time monitoring may detect a change or attempt to change a number of enabled memory channels after the memory channels were first initialized. For example, the PCU204may prevent changes to the number of memory channels enabled while a compute system is operating in a system management mode (SMM) of operation. The PCU204may utilize one or more hardware mechanisms to detect and prevent changes to a number of memory channels enabled during run-time.

In the embodiment illustrated inFIG. 2A, the PCU204may utilize the memory channel register210, such as the memory controller channel enablement (MCMTR) register. More specifically, during the boot process, channel disable bits in the memory channel register210, e.g. MCMTR.chn_disable, are set based on the memory channels enabled (disabled). These bits indicate the memory channels disabled (and enabled) during run-time operations of a compute system. The PCU204may lock the memory channel register210after the boot phase, e.g. upon completion of memory training boot phase and initialization, such that bits are read-only. In one example, the PCU204may set a policy option in an Intel© On-Chip System Fabric (IOSF) sideband interface to make the MCMTR.chn_disable read-only upon completion of memory training (MRC) boot phase. Thus, the memory channels enabled/disabled are set until a next boot cycle. Moreover, the PCU204may detect and prevent change attempts to enabled/disabled memory channels via the MCMTR register210. In some instances, the PCU204may invoke an MCE if a change attempt is detected.

FIG. 2Billustrates another example of an embodiment of a processor device220B where a different hardware mechanism is utilized to provide run-time enforcement of a memory channel allocation. InFIG. 2B, the PCU204may utilize a shadow register212, such as the MC-uCR register to detect and prevent memory channel enablement changes during run-time. The PCU204may set the shadow register during the boot process and initialization of the memory with memory channels to be disabled (or enabled) using the bit map set in the PCU register208by the BIOS. The shadow register212may be a shadow register in that only the PCU204may access (read/write) to it. The BIOS and other software/hardware is prevented from making changes to the shadow register212. Thus, the PCU204may use the shadow register212to detect any changes made to the memory channel allocation during run-time. More specifically, the PCU204may determine that the memory channels enabled (or disabled) in the memory channel register210matches the original configuration stored in the shadow register212. If they are the same in both the memory channel register210and the shadow register212, then no changes have been made to the memory channel allocation. However, if there are differences, a change attempt is detected and the PCU204may cause a corrective action, such as issuing an MCE to cause a reset. In some instances, the PCU204may permit the change in the memory channel if the number of memory channels does not exceed the maximum permitted number of memory channels.

FIG. 3illustrates an embodiment of logic flow300. The logic flow300may be representative of some or all of the operations executed by one or more embodiments described herein. For example, the logic flow300may illustrate operations performed by a compute system, such as compute system100including the processor device120and the BIOS125.

In embodiments, the logic flow300includes detecting a system initialization at block302. The system initialization may be invoked by a received power signal, which triggers a series of events to boot a compute system into a normal operating state. The series of events may be known as a boot sequence, which includes initialization and testing various hardware components of the compute system. As part of the boot sequence, the BIOS may initialize the memory and processing cores of the compute system, for example.

FIG. 3illustrates one or more operations that may be performed by the BIOS and the PCU as part of a memory initialization. For example, the logic flow300includes determining a number of memory channels to enable for a compute system at block304. In embodiments, the number of memory channels to enable may be based on a user input. For example, a user may be able to make a selection of a number of and which memory channels to enable for a compute system via an interface that may be presented on a display. In some embodiments, a compute system may determine which memory channels to enable or attempt to enable based on a detection of memory modules inserted in DIMM slots of the compute system. Further and at block306, the logic flow300includes determining faulty DIMMs and mapping out memory channel allocations based on the detected faulty DIMMs.

At block308, the logic flow300may include determining the maximum number of memory channels permitted to be enabled for a processor device. More specifically, the BIOS may read a capability identification register, such as a “DDR MC Channel Allowed,” to determine the maximum memory channels that are permitted to be enabled for a particular processor device. If all of the memory channels capable for a compute system are permitted to be enabled for a particular processor device, the logic flow may include permitting the BIOS to enable the memory channels at block314. However, if only a subset of the available memory channels are permitted to be enabled for a particular processor device, a power control unit of the processor device may perform a verification to ensure that the desired number of memory channels to be enabled does not exceed the maximum number of memory channels permitted at blocks310and312.

At block310, the logic flow includes indicating the memory channels to be enabled by setting one or more bits in a PCU register, e.g. communicating a mailbox command. More specifically, the BIOS may set the one or more bits, which may be a bit map indicating a number of memory channels to be enabled and which memory channels. In some embodiments, the logic of PCU register may indicate which memory channels are to be disabled. In other words, a bit set as a logical “1” may indicate that an associated memory channel is to be disabled, while a bit set as a logical “0” may indicate that an associated memory channel is to be enabled. In other embodiments, the opposite logic may be used. For example, a logical “1” may indicate an associated memory channel is to be enabled, and a logical “0” may indicate an associated memory channel is to be disabled. Embodiments are not limited in this manner.

The PCU may determine which memory channels are to be enabled via the PCU register, and at block312, determine whether the number of memory channels to be enabled exceeds the number of permitted memory channels for a processor device. Note that the logic flow may include opposite, such that the PCU may determine whether the number of memory channels to be enabled is less than (or equal) to the number of permitted memory channels. Moreover, the PCU may determine the number of permitted memory channels for the processor device based on information in a capability identification register, such as the “DDR MC Channel Allowed” register. If the determination indicates that the number to be enabled exceeds the number of permitted memory channels for a particular processor device, the PCU may cause a reset by issuing an MCE. However, if the PCU determines the number of memory channels to be enabled does not exceed the permitted number of memory channels, the PCU may permit the BIOS to complete the enablement of the memory channels and finish the boot sequence.

During run-time of a compute system, e.g. when the compute system is operating in a typical fashion via an operating system, the PCU may perform real-time monitoring to detect any attempts to change the number of enabled memory channels at316and318. If no attempts are detected, the PCU may continue to monitor a compute system and operations until the compute system is shut down or a reset occurs (reboot) at block320. At block318, if the PCU detects an attempt to change a number of memory channels enabled, the PCU may cause a reset by issuing an MCE, for example. Embodiments are not limited in this manner.

FIG. 4illustrates an example of a second processing flow400to verify that the number of memory channels to be enabled does not exceed the maximum number of memory channels permitted for a processor device. The processing flow400may be representative of some or all of the operations executed by one or more embodiments described herein. For example, the processing flow400may illustrate operations performed in a compute system, and in particular, a PCU.

At block405, the logic flow400may include determining one or more memory channels of a plurality of memory channels to be enabled based on an indication received from a basic input/output system (BIOS). More specifically, the PCU may receive a mailbox command from the BIOS, which includes one or more bits set in a PCU register. The one or more bits set may indicate the number of and which memory channels are to be enabled (or disabled). Moreover, each memory channel may have a corresponding bit in the PCU register, that when set, indicates that the memory channel is to be enabled. In some embodiments, the opposite logic may be utilized such that a bit set may indicate that the corresponding memory channel is to be disabled.

The logic flow400includes determining whether a number of the one or more memory channels to be enabled is greater than a maximum number of memory channels permitted at block410. More specifically, the PCU may determine the maximum number of memory channels permitted based on an indication in a CapID register. The PCU may perform a comparison to determine whether the number of memory channels to be enabled is greater than the maximum number of memory channels permitted. In some embodiments, the PCU may perform the determination with opposite logic. The PCU may determine whether the number of memory channels to be enabled is less than (or equal to) the maximum number of memory channels permitted.

At block415, the logic flow400includes causing a platform reset if the number of the one or more memory channels is greater than the maximum number of memory channels. For example, the PCU may issue an MCE to cause a compute system to reset. In some embodiments, the PCU may cause an indication to be presented on a display indicating that the number of memory channels attempting to be enabled is greater than the maximum number of memory channels permitted to be enabled for a processor device. At block420, the logic flow400includes permitting enablement of the one or more memory channels if the number of the one or more memory channels is not greater than the maximum number of memory channels. For example, the PCU may provide an indication to the BIOS that it may complete the boot process.

FIGS. 5A/5B illustrate examples of airflow through a compute system500with different memory channel enablement configurations.FIG. 5Aillustrates a typical memory channel configuration with memory on two separate compute devices505A and505B cooled by a system fan510. In the illustrated example ofFIG. 5A, each compute device505A and505B has three memory channels enabled. More specifically, compute device505A has memory channels 0-2 associated with memory slots515A-1through515A-3enabled. Memory slots515A-4are empty, and memory channel three is disabled. Similarly, compute device505B has memory channels 0-2 associated with memory slots515B-1through515B-3enabled. Memory slots515B-4are empty, and memory channel three is disabled.

FIG. 5Billustrates an alternative example of airflow through the compute system500with different memory channels enabled than the memory channels enabled in the example inFIG. 5A. Embodiments discussed herein permit different memory channels on the compute devices505A and505B to be enabled. Thus, different memory slots may be utilized to optimize the cooling capabilities provided by the system fan510.

InFIG. 5B, the compute device505A has memory in memory slots515A-2through515A-4and memory slots515A-1are empty. The memory channels associated with memory slots515A-2through515A-4are enabled, and the memory channel (Ch0) associated with memory slots515A-1is disabled. Compute device505B has a different configuration and airflow is optimized. Compute device505B has memory in memory slots515B-1through515B-3. Memory slot515B-4is empty, and the associated memory channel (Ch3) is disabled. In the illustrated example ofFIG. 5B, the components (memory) of the downstream compute device505B will receive less heat from the components (memory) of the upstream compute device505A, optimizing the thermal performance. InFIG. 5A, the empty slot of the upstream compute device505A is in front of the empty slot of the down compute device505B. The benefit of having an empty slot in front of a component of the downstream compute device505B is not realized.

FIGS. 6A/6B illustrate example I/O bus traces610in a compute system600.FIG. 6Aillustrates a typical bus trace610for systems that are not capable of dynamically configuring memory channels. InFIG. 6A, Ch3 is the disabled memory channel, and memory slots615-1through615-3are utilized. Thus, memory buses must be implemented in the layers of the circuit board of the compute system600to connect the memory slots615-1through615-3to the processor device620. The I/O bus610is routed around the memory slots615-1and615-2due to the memory buses coupling the memory slots615-1and615-2to the processor device620.

FIG. 6Billustrates an alternative example enabled by embodiments discussed herein where the memory slots615-1(Ch0) are not utilized, but the compute system600still includes three memory channels (Ch1, Ch2, and Ch3). In the illustrated example ofFIG. 6B, the I/O bus trace610may be routed through the memory slots615-1area using the layer that typically would have the memory bus trace for the memory slots615-1. Thus,FIG. 6Bcan have the same number of layers as the compute system600inFIG. 6A, but shorter I/O bus trace lengths.

FIG. 7illustrates an embodiment of an exemplary computing architecture700suitable for implementing various embodiments as previously described. In one embodiment, the computing architecture700may include or be implemented as part of the compute system discussed herein.

As shown inFIG. 7, the computing architecture700includes a processing unit704, a system memory706and a system bus708. The processing unit704can be any of various commercially available processors.

The computer702may include various types of computer-readable storage media in the form of one or more lower speed memory units, including an internal (or external) hard disk drive (HDD)714, a magnetic floppy disk drive (FDD)716to read from or write to a removable magnetic disk718, and an optical disk drive720to read from or write to a removable optical disk722(e.g., a CD-ROM or DVD). The HDD714, FDD716and optical disk drive720can be connected to the system bus708by an HDD interface724, an FDD interface726and an optical drive interface727, respectively. The HDD interface724for external drive implementations can include at least one or both of Universal Serial Bus (USB) and IEEE 1394 interface technologies.

The drives and associated computer-readable media provide volatile and/or nonvolatile storage of data, data structures, computer-executable instructions, and so forth. For example, a number of program modules can be stored in the drives and memory units710,712, including an operating system730, one or more application programs732, other program modules734, and program data736. In one embodiment, the one or more application programs732, other program modules734, and program data736can include, for example, the various applications and/or components of the system700.

A monitor744or other type of display device is also connected to the system bus708via an interface, such as a video adaptor746. The monitor744may be internal or external to the computer702. In addition to the monitor744, a computer typically includes other peripheral output devices, such as speakers, printers, and so forth.

When used in a LAN networking environment, the computer702is connected to the LAN752through a wire and/or wireless communication network interface or adaptor756. The adaptor756can facilitate wire and/or wireless communications to the LAN752, which may also include a wireless access point disposed thereon for communicating with the wireless functionality of the adaptor756.

When used in a WAN networking environment, the computer702can include a modem758, or is connected to a communications server on the WAN754, or has other means for establishing communications over the WAN754, such as by way of the Internet. The modem758, which can be internal or external and a wire and/or wireless device, connects to the system bus708via the input device interface742. In a networked environment, program modules depicted relative to the computer702, or portions thereof, can be stored in the remote memory/storage device750. It will be appreciated that the network connections shown are exemplary and other means of establishing a communications link between the computers can be used.

The computer702is operable to communicate with wire and wireless devices or entities using the IEEE 702 family of standards, such as wireless devices operatively disposed in wireless communication (e.g., IEEE 702.11 over-the-air modulation techniques). This includes at least Wi-Fi (or Wireless Fidelity), WiMax, and Bluetooth™ wireless technologies, among others. Thus, the communication can be a predefined structure as with a conventional network or simply an ad hoc communication between at least two devices. Wi-Fi networks use radio technologies called IEEE 702.11x (a, b, g, n, etc.) to provide secure, reliable, fast wireless connectivity. A Wi-Fi network can be used to connect computers to each other, to the Internet, and to wire networks (which use IEEE 702.3-related media and functions).

The detailed disclosure now turns to providing examples that pertain to further embodiments. Examples one through thirty-six (1-36) provided below are intended to be exemplary and non-limiting.

In a first example, a system, device, or apparatus may include a controller and memory storing instructions operable on the controller, the instructions, when executed, causing the controller to determine one or more memory channels of a plurality of memory channels to be enabled based on an indication received from a basic input/output system (BIOS). The controller also may determine whether a number of the one or more memory channels to be enabled is greater than a maximum number of memory channels permitted, cause a platform reset if the number of the one or more memory channels is greater than the maximum number of memory channels, and permit enablement of the one or more memory channels if the number of the one or more memory channels is not greater than the maximum number of memory channels.

In a second example and in furtherance of the first example, a system, device, or apparatus may include the controller to determine the maximum number of memory channels permitted based on information in a capability identification register.

In a third example and in furtherance of any previous example, a system, device, or apparatus may include the controller to process the indication comprising one or more bits, each of the one or more bits to indicate whether a corresponding memory channel of the plurality of memory channels is to be enabled or disabled.

In a fourth example and in furtherance of any previous example, a system, device, or apparatus may include the controller to set one or more bits in a shadow register based on the indication, the shadow register to prevent enablement changes to the plurality of memory channels during run-time of the system.

In a fifth example and in furtherance of any previous example, a system, device, or apparatus may include the controller to lock a memory channel register as read-only based on subsequent completion of a memory training boot phase to prevent enablement changes to the plurality of memory channels during run-time of the system.

In a sixth example and in furtherance of any previous example, a system, device, or apparatus may include the controller to enable the one or more channels during a boot process for the system.

In a seventh example and in furtherance of any previous example, a system, device, or apparatus may include the controller to prevent enablement changes to the plurality of memory channels during run-time of the system subsequent to a boot process.

In an eighth example and in furtherance of any previous example, a system, device, or apparatus may include the controller and the memory, the BIOS, and one or more memory modules including memory.

In a ninth example and in furtherance of any previous example, a computer-implemented method may include determining one or more memory channels of a plurality of memory channels to be enabled based on an indication received from a basic input/output system (BIOS), determining whether a number of the one or more memory channels to be enabled is less than or equal to a maximum number of memory channels permitted, causing a platform reset if the number of the one or more memory channels is greater than the maximum number of memory channels, and permitting enablement of the one or more memory channels if the number of the one or more memory channels is less than or equal to the maximum number of memory channels.

In a tenth example and in furtherance of any previous example, a computer-implemented method may include determining the maximum number of memory channels permitted based on information in a capability identification register.

In an eleventh example and in furtherance of any previous example, a computer-implemented method may include processing the indication comprising one or more bits, each of the one or more bits to indicate whether a corresponding memory channel of the plurality of memory channels is to be enabled or disabled.

In a twelfth example and in furtherance of any previous example, a computer-implemented method may include setting one or more bits in a shadow register based on the indication, the shadow register to prevent enablement changes to the plurality of memory channels during run-time of the system.

In a thirteenth example and in furtherance of any previous example, a computer-implemented method may include locking a memory channel register as read-only based on subsequent completion of a memory training boot phase to prevent enablement changes to the plurality of memory channels during run-time of the system.

In a fourteenth example and in furtherance of any previous example, a computer-implemented method may include enabling the one or more channels during a boot process for the system.

In a fifteenth example and in furtherance of any previous example, a computer-implemented method may include preventing enablement changes to the plurality of memory channels during run-time of the system subsequent to a boot process.

In a sixteenth example and in furtherance of any previous example, embodiments may include a non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, enable processing circuitry to determine one or more memory channels of a plurality of memory channels to be enabled based on an indication received from a basic input/output system (BIOS) to determine whether a number of the one or more memory channels to be enabled is greater than a maximum number of memory channels permitted, cause a platform reset if the number of the one or more memory channels is greater than the maximum number of memory channels, and permit enablement of the one or more memory channels if the number of the one or more memory channels is not greater than the maximum number of memory channels.

In a seventeenth example and in furtherance of any previous example, embodiments may include a non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, enable processing circuitry to determine the maximum number of memory channels permitted based on information in a capability identification register.

In an eighteenth example and in furtherance of any previous example, embodiments may include a non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, enable processing circuitry to process the indication comprising one or more bits, each of the one or more bits to indicate whether a corresponding memory channel of the plurality of memory channels is to be enabled or disabled.

In a nineteenth example and in furtherance of any previous example, embodiments may include a non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, enable processing circuitry to set one or more bits in a shadow register based on the indication, the shadow register to prevent enablement changes to the plurality of memory channels during run-time of the system.

In a twentieth example and in furtherance of any previous example, embodiments may include a non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, enable processing circuitry to lock a memory channel register as read-only based on subsequent completion of a memory training boot phase to prevent enablement changes to the plurality of memory channels during run-time of the system.

In a twenty-first example and in furtherance of any previous example, embodiments may include a non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, enable processing circuitry to enable the one or more channels during a boot process for the system.

In a twenty-second example and in furtherance of any previous example, embodiments may include a non-transitory computer-readable storage medium, comprising a plurality of instructions, that when executed, enable processing circuitry to the plurality of memory channels during run-time of the system subsequent to a boot process.