Circuitry for reducing the skew between two signals

An electronic integrated circuit includes a first signal (A1) generated by a first source block (10) and a second signal (B1) generated by a second source block (12). A variable delay circuit (18) detects a delay between said first and second signals in calibration mode and applies the delay to the first signal during normal operation of the circuit. A fixed delay buffer (32) may be used to apply a delay to the second signal to compensate for known delays associated with the variable delay circuit (18).

This application claims priority under 35 USC § 119(e)(1) of European Patent Application Number 03290003.7 filed Jan. 2, 2003.

CROSS REFERENCE TO RELATED APPLICATIONS

Not Applicable

STATEMENT OF FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not Applicable

BACKGROUND OF THE INVENTION

1. Technical Field

This invention relates in general to electronic circuits and, more particularly, to circuitry for reducing the skew between two signals.

2. Description of the Related Art

In the design of electronic circuits, it is often necessary to compensate for skew between two signals arriving at a common block. Traditionally, the skew between the two signals is reduced with the addition of buffers to equalize the difference between the paths of the two signals. Often, the appropriate buffers can be determined automatically using computer aided design tools.

An example of the problem is set forth in connection withFIGS. 1aand1b.FIG. 1aillustrates an example a portion of an integrated circuit where signals from two different circuitry blocks (source blocks) are received at a third block (user block). First source block10is clocked using clock Ca and a second circuitry block12is clocked using clock Cb. First and second source blocks10and12could implement any type of analog or digital circuitry, or a mix thereof. As shown inFIG. 1b, Clocks Ca and Cb are skewed by an amount Skew(Ca−Cb). The output A of source block10is delayed by a time Da due to propagation through the logic of source block10and routing delays between the output of source block10and the input to user block14. Similarly, the output B of source block12is delayed by a time Db due to propagation through the logic of source block12and routing delays between the output of source block12and the input to user block14. For reference,FIG. 1bis a timing diagram which shows the skew between clocks Ca and Cb at the inputs to source blocks10and12, respectively, and shows the delay between the resulting signals at the input to user block14. This delay is a factor of the skew between clocks Ca and Cb and the delays Da and Db. The delay between signals A and B at the input to user block14could be defined as:
Delay(A−B)=Skew(Ca−Cb)+Db−Da

In mixed signal design, there will be digital spread delays and analog spread delays. The spread of each cannot be easily compensated with a unique addition of digital delay.

Therefore a need has arisen for a method and circuit for reducing skew between two signals.

BRIEF SUMMARY OF THE INVENTION

In the present invention an electronic circuit includes a first source circuit for generating a first signal and for generating a first calibration signal responsive to a calibration mode and a second source circuit of generating a second signal and for generating a second calibration signal responsive to the calibration mode. A variable delay circuit detects a delay between the first and second calibration signals and applies a delay to the first signal responsive to the detected delay.

The present invention provides significant advantages over the prior art. The variable delay circuit can provide high precision compensation for delays between two signals as determined at the input to a circuit that uses the two signals. Therefore, the variable delay circuit takes into account all sources of delay, without needing any knowledge of the sources of delay or their possible variations. Since calibration can occur as often as desired, the variable delay circuit can compensate for dynamically varying delays. The variable delay circuit is particularly well suited for use with analog RF designs which need frequent high precision calibration between signals.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is best understood in relation toFIGS. 1-4of the drawings, like numerals being used for like elements of the various drawings.

FIGS. 2aand2billustrate a prior art solution to the problem of signal skew.FIG. 2ais the same as the example circuit ofFIG. 1a, with the addition of a delay buffer16between the output (A1) of source circuitry10and the input (A) to user circuitry14. The delay Dc is calculated to compensate for the delays caused by clock skew and logic and routing delays. With the addition of delay buffer16, the delay between signals A and B could be estimated as:
Delay(A−B)=Skew(Ca−Cb)+Db−(Da+Dc)

However, it should be noted that clock and signal delays are not exact, since each has a spread which may very based on processing variations and environmental factors. Some environmental factors, such as temperature, may vary during operation of a device. Hence Ca=Canom±ΔCa, Cb=Cbnom±ΔCb, Da=Danom±ΔDa, Db=Dbnom±ΔDb, and Dc=Dcnom±ΔDc, where “nom” indicates and expected nominal value and Δ indicates an expected variation.

In many cases, the possible variations in the delays and clock skew, along with the variation on the compensation delay, Dc, make it impossible to guarantee that the delay between the A and B signals will be within maximum design specifications.

FIGS. 3aand3billustrate a circuit using dynamic best fit delay compensation. InFIG. 3a, the delay buffer16, with fixed delay Dc, has been replaced with a variable delay buffer18, with a dynamically variable delay component Dcv.

During operation of the device, a Start signal is used to calibrate the variable delay circuit18, such that Dcv is set to an appropriate value that will compensate for the clock skew and delays Da and Db. Dcv is set until a reset signal initiates another calibration. Depending upon the design, the circuit could be calibrated upon start-up, periodically, upon an event, or upon each use of the user circuitry block14.

FIG. 4illustrates a preferred embodiment of a variable delay buffer18. The variable delay buffer18comprises a plurality of delay stages20. A delay stage includes a fixed delay buffer22, a flip-flop24, an exclusive-or gate26and an AND gate28. Each fixed delay buffer22receives the output of the fixed delay buffer of the preceding stage20. The first stage receives the output (A1) of the first source block10and can optionally have a delay buffer22or have no delay (as shown). The output of the fixed delay buffer22is coupled to the input of a flip-flop24. Flip-flop24is clocked by the output (B1) of the second source block12while the Start signal is active (in the illustrated embodiment, the Start signal is active high). The flip-flops24are reset by signal RESETZ (active low). The output of flip-flop24is coupled to the input of exclusive-or gate26. The other input of exclusive-or gate26is coupled to the output of the flip-flop of the subsequent stage20. For the last stage20, the second input to the exclusive-or gate is tied to a logical “1”. The output of exclusive-or gate26is coupled to one input of an AND gate28. The other input to the AND gate is the output of the fixed buffer22of the same stage20. The outputs of the AND gates of all stages are coupled to the inputs of OR gate30. The output of the OR gate30is the input (A) to the user block14.

The output (B1) of the second source block12is coupled to fixed delay buffer32, with a delay D0. The output of fixed delay buffer32is the input to the user block14.

In operation, the Start signal begins a calibration cycle. It is assumed that the B1signal is known to (or is designed to) transition to an active state after the A1signal. Prior to calibration, all flip-flops24are reset to output logical “0”s by the RESETZ signal. When the B1signal transitions high (active), the A1signal will have begun propagation through the fixed delay buffers22. When the flip-flops are set, there will be a single occurrence where flip-flops from two consecutive stages have outputs of different logical values—the earlier stage will output a logical “1” and the later stage will output a logical “0”. This is the point where the active edge has propagated through the delay buffers22.

The AND gate28of the stage20having the exclusive-or gate26with a “1” output will pass the output of that stage's fixed delay buffer22. Hence, the exclusive-gates26and the AND gates28form a multiplexer which selects the output of a fixed delay buffer22whose cumulative delay (i.e., the delay of all buffers in the chain) most closely matches the delay between the A1and B1outputs. In the illustrated embodiment, the exclusive-or gates26are configured to choose the output of the fixed delay buffer22in the earlier of the two stages at which the transition occurs as the best fit delay; alternatively, the output of the fixed delay buffer22in the later of the two stages could be chosen as the best fit delay by coupling each exclusive-or gate to the output of the flip-flop24of its own stage and the output of the flip-flop24of the preceding stage (rather than the output of the flip-flop24of the subsequent stage, as shown).

Table 1 illustrates the propagation of the A1signal through the variable delay buffer18during a calibration cycle. When B1transitions to an active state, A1has passed through the delay buffers22of stages 1-4, but has not yet passed through the delay buffer22of stage5. If the delay of each delay buffer22is D, it can be said that 4*D<=Delay(A1−B1)<5*D.

The exclusive-or gate26for stage “4” will be the only exclusive-or gate that outputs a “1”; the remainder of the exclusive-or gates26will output “0”s. Accordingly, only the AND gate28of stage “4” will pass the output of the stage's fixed delay buffer22. The outputs of all other AND gates28will be logical “0”s.

The maximum delay is provided at the output of the fixed delay buffer22of the last stage. If the active edge of A1precedes the active edge of B1by more the sum of all the fixed delay buffers22, then the maximum delay will be used (since the input of the exclusive-or gate26in the last stage is set to a “1”).

The implementation of the variable delay circuit18shown inFIG. 4is designed to minimize the delay between the A1and B1signals without exceeding the actual delay between the signals. Alternatively, by coupling one input of the exclusive-or gates26to the output of the preceding flip-flop24, rather than the subsequent flip-flop24, the delay provided by the variable delay circuit18would be the minimum delay needed to close or exceed the actual delay between the A1and B1signals.

For a given maximum delay, the resolution of the variable delay circuit18can be increased by providing more delay elements22, each with a smaller delay D.

After the appropriate delay buffer22is selected for output, the Start signal transitions to an inactive state. At this point, the appropriate delay is memorized in the variable delay circuit18. The A1signal will continue to pass through the chain of delay buffers22up to the selected delay buffer, at which point it will pass through the AND gate28of the associated stage and the OR gate30to the user block14. This will continue until another calibration is initiated using the Start signal.

The delay buffer32compensates for the delays associated with the AND gate28and OR gate30through which the A1signal must pass. However, since these delay buffer32is fabricated in close proximity to the AND gates28and OR gates30, any variation due to processing or temperature will be closely matched.

The present invention provides significant advantages over the prior art. The variable delay circuit18provides high precision compensation for delays between two signals. The compensation is determined at the input to the user circuit14and therefore takes into account all sources of delay, without needing any knowledge of the sources of delay or their possible variations. Since calibration can occur as often as desired, the variable delay circuit18can compensate of dynamically varying delays. The variable delay circuit is particularly well suited for use with analog RF designs which need frequent high precision calibration between signals.

As is known to those skilled in the art, the logic used to implement the multiplexer could be varied, without changing the functionality of the variable delay circuit18. The concept is easily extended to cases where the active edges of A1, B1and Start could be logical “0”s or mixed.

Although the Detailed Description of the invention has been directed to certain exemplary embodiments, various modifications of these embodiments, as well as alternative embodiments, will be suggested to those skilled in the art. The invention encompasses any modifications or alternative embodiments that fall within the scope the claims.