Restoring register values from stack memory using instruction with restore indication bit and de-allocation frame size stack pointer offset

Provided is a method and system for encoding an instruction to restore processor core register values. The method includes encoding in a first field of the instruction whether a first value, in a stack memory location having an address value equal to A plus a second value in a second register, is to be restored to a first register. A third value is encoded in a second field of the instruction for adjusting the second value in the second register.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to a data processing system. More particularly, it relates to saving and restoring processor register values and allocating and deallocating stack memory.

2. Background Art

Two well-known operations performed by computer systems are the storing and retrieving of items on a stack. Stackable items include general purpose register contents; e.g., data and addresses. These operations (also referred to as “push” and “pop” operations) are typically used to facilitate the entry to and exit from subroutines. That portion of a stack created for a particular subroutine is referred to as a “stack frame.” In programmable devices (such as microprocessors), dedicated instructions may be used to carry out these operations.

It is desired to enhance the utility of stack storing and/or retrieving operations by providing additional functionality associated therewith. Such functionality, when added to instructions for carrying out stack operations, make it possible to write more compact application programs since such instructions encode multiple functions.

BRIEF SUMMARY OF THE INVENTION

The present invention provides methods and means for saving and restoring processor registers and allocating and deallocating a stack frame. In one embodiment, a first field of a save instruction encodes whether a value in a register of a processor is saved as an argument value or a static value. A second field of the save instruction encodes a size of a stack frame created during execution of the save instruction. An argument value is saved in a calling program's stack frame. A static value is saved in a called program's stack frame. A restore instruction is used to restore a static value and deallocate the stack frame. The save and restore instructions may be executed using any programmable device, including a single instruction set architecture processor or a multi-instruction set architecture processor. The functionality of such instructions may be achieved through software, hardware or a combination of both.

In another embodiment, a 16-bit instruction according to the invention comprises at least five fields. These five fields are an instruction opcode field, a 1-bit return address register field, a 1-bit first static register field, a 1-bit second static register field, and a 4-bit frame-size field. This instruction can be executed as a single 16-bit instruction or executed in combination with a 16-bit instruction extension. An instruction extension comprises at least four fields. These four fields are an extend instruction opcode field, a 3-bit additional static registers field, a second 4-bit frame-size field, and a 4-bit arguments register field. The 3-bit additional static registers field allows the values in up to seven addition registers to be saved and restored as static values.

Features of the invention allow the invention to be implemented, for example, as a method for encoding an instruction, as a processor core, as a mapper, as a decoder, and/or as a computer program.

DETAILED DESCRIPTION OF THE INVENTION

The present invention provides methods and means for saving and restoring a processor register value and allocating and deallocating stack memory. Method embodiments of the invention are encoded in instructions that can be efficiently stored as a part of a computer program. Apparatus embodiments of the invention execute instructions according to the invention.

As described herein, instructions according to the invention can be executed using either a single instruction set architecture processor or a multi-instruction set architecture processor.

In an embodiment of the invention, a first field of a save instruction encodes whether a value in a register of a processor is saved as an argument value or a static value. A second field of the save instruction encodes a size of a stack frame created during execution of the save instruction. An argument value is saved in a calling program's stack frame. A static value is saved in a called program's stack frame. A restore instruction is used to restore a static value and deallocate the stack frame.

The invention is now described with reference toFIGS. 1-18.

EXAMPLE APPARATUS/SYSTEM EMBODIMENTS OF THE INVENTION

FIG. 1depicts an example environment for implementation of the present invention. Specifically,FIG. 1depicts a processor system100for implementing the present invention.

System100comprises a processor101, a cache102, a cache controller110, a memory104, a memory management unit160, and a processor-memory bus105. A bus interface103couples processor-memory bus105to an input/output (I/O) bus106and a plurality of I/O controllers such as, for example, I/O controllers107,108, and109. Cache controller110has a mapper120. Processor101has a decoder152and a register bank156.

FIG. 2illustrates an example register bank156having thirty-two registers labeled R0-R31. In other embodiments, register bank156may have more or less than thirty-two registers. Certain of the registers of register bank156are assigned labels. Registers R4, R5, R6, and R7are shown labeled as argument registers A0, A1, A2, and A3, respectively. Registers R16and R17are labeled as static registers S0and S1, respectively. A static register is a processor register which, by software convention, contains a data value that must be preserved across subroutine calls. A subroutine that respects a static register convention must exit with all static registers in the same state that they were in at subroutine entry. This can be achieved either by never modifying the static registers, or by saving the static value before any modified use of the register and then restoring the value before exit from the subroutine. Register R29is labeled as stack pointer register SP. Register R31is labeled as return address register RA. These labels are illustrative, and not intended to limit the invention. The labels are used below to further describe the invention.

Registers other than the registers labeled inFIG. 2can be used to implement the invention, as will be understood by a person skilled in the relevant art given the description herein.

FIG. 3illustrates a portion of memory104in greater detail. Memory104comprises a user memory302and an operating system memory (not shown). User memory302comprises five regions of interest. These regions are a program code region304, a data region306A, a heap region306B, a stack region308, and an unused or available space region310. As can be seen inFIG. 3, stack region308typically comprise a region312for passing argument values to a subroutine via memory104, and a reserved space for storing values passed to a subroutine in a register. A stack pointer316indicates the address of the next available memory location in region310of memory104.

The program code region304is used to store the instructions of a program being implemented by system100. Program instructions to be executed by the processor of system100must be read into cache memory102from main memory104.

Heap306B is used for globally meaningful or long-lived dynamic data, while stack308is used for locally significant and short-lived dynamic data. Allocation of heap memory306B involves software manipulation of data structures in memory that control its explicit allocation. Allocation of dynamic data on stack308is done simply by updating the stack pointer316and remembering the stack pointer offset of each allocated data item. As shown inFIG. 3, stack308grows from higher memory addresses to lower memory address. In other embodiments of the invention, stack308can grow from lower memory addresses to higher memory addresses. The data region306A is used to store static data.

Further description of the elements of system100can be found in any general computer design book. For example, see “Computer Organization & Design: the Hardware/Software Interface,” by David A. Patterson and John L. Hennessy, 2nd ed., Morgan Kaufmann Publishers Inc., San Francisco, Calif., 1998, which is incorporated herein by reference in its entirety for all purposes.

The present invention is now described with reference to the features of system100which provides an example environment for implementation of the invention. It will be apparent to a person skilled in the art, however, that the invention can be implemented in other processor environments. For example, the invention can be implemented in a dual instruction set processor environment such as that described in commonly owned U.S. patent application Ser. No. 09/836,541, filed Apr. 18, 2001, and titled “Mapping System and Method for Instruction Set Processing,” which is incorporated herein by reference as if reproduced in full below.

EXAMPLE METHOD EMBODIMENTS OF THE INVENTION

As described herein, the steps of method embodiments of the invention can be encoded in instructions that are stored as a part of a computer program. These methods are then implemented using a processor (e.g., processor101). A processor according to the invention can decode the instructions described herein and perform the steps of the method embodiments.

FIG. 4illustrates two exemplary 16-bit instructions402and452that encode method embodiments of the invention for saving registers and allocating stack memory upon entry to a subroutine. Instruction402can be executed as a single, stand-alone 16-bit instruction. In addition, instruction402can be executed in combination with instruction extension452as a 32-bit extended version of the 16-bit instruction (i.e., instruction475).

Instruction402comprises five fields. These five fields are a 9-bit save instruction opcode field404, a 1-bit return address register (RA) field406, a 1-bit first static register (SO) field408, a 1-bit second static register (S1) field410, and a 4-bit frame-size field412. As would be known to a person skilled in the relevant art, a return address register is used to store an address of an instruction that is to be executed upon exit from a subroutine, and a static register is used to store a value of a variable that must be preserved by a program before calling a subroutine. The purpose of each of these fields is described below with regard to the steps of method500and pseudo-code650.

Instruction extension452comprises four fields. These four fields are a 5-bit extend instruction opcode field454, a 3-bit additional static registers field456, a 4-bit frame-size field458, and a 4-bit argument registers field460. As would be known to a person skilled in the relevant art, an argument register is used by a calling program to pass a value to a subroutine. The value in the argument register may or may not need to be preserved by the subroutine, depending on software convention. The purpose of each of these fields is described below with regard to the steps of method500and pseudo-code800.

A method500for saving registers and allocating memory on entry to a subroutine according to the invention will now be described.FIGS. 5A and 5Billustrate a flowchart of the steps of method500. As illustrated in the flowchart, method500comprises a plurality of steps divided up into three stages501,509, and515. Stage501comprises steps502,504,506, and508, and is performed prior to or during development and/or implementation of a processor design. As will be understood by a person skilled in the relevant art(s), once these steps have been performed, they need not be repeated. Steps502-508are an inherent part of a processor, a mapper, a decoder and/or an instruction according to the invention. Stage509comprises steps510,512, and514, and an encoding step implicit in step522. These steps of method500are typically performed using a compiler program. A compiler program takes source code and uses the source code to determine a desired encoding for instructions according to the invention. Lastly, stage515comprises steps516,518,520, and522. These steps are performed by an apparatus or system according to the invention executing an instruction encoded according to the invention. As described herein, it is not necessary to perform each step of method500every time the method is implemented.

The steps of method500can be encoded by instruction402and/or instruction475for implementation by a processor. In the description that follows, method500is described in detail with regard to instruction402, register bank156, stack region308of memory104, and pseudo-code650(shown inFIG. 6). Method500begins at a step502.

In step502, at least one general purpose register of register bank156is specified as an argument register. This is to enable subsequent steps of method500to be encoded using the fields of instructions402and475. The number of argument registers specified will typically depend on the number of general purpose registers available in a processor core and/or the number of registers intended to be visible when using a particular instruction set. In an embodiment of the invention, registers R4, R5, R6, and R7are specified as argument registers A0, A1, A2, and A3, respectively, as shown inFIG. 2. In other embodiments, more or less than four argument registers can be specified in step502.

Specifying a general purpose register of register bank156in step502as an argument register is not intended to alter the nature of the general purpose register with regard to other instructions of an instruction set. In fact, a feature of the invention allows any specified argument register according to the invention to be treated as a general purpose register by instructions other than the instructions described herein, and thus maintain all the functionality of a general purpose register with regard to other instructions. Furthermore, this feature of the invention also applies to general purpose registers specified, for example, as a static register (e.g., S0and S1), a stack pointer register (SP), and/or a return address register (RA) in accordance with method500.

In step504, at least one register of register bank156is specified as a static register. In the embodiment ofFIG. 2, two registers R16and R17are specified as static registers S0and S1, respectively. In other embodiments, more or less than two registers may be specified.

In step506, a register of register bank156is specified as a stack pointer register (SP). The stack pointer register typically holds the address value of the next available memory location in memory104.FIG. 3illustrates a stack pointer316. In the embodiment shown inFIG. 2, register R29of register bank156is specified as the stack pointer register.

In step508, a register of register bank156is specified as a return address register (RA). The return address register typically holds the address value of the next instruction to be executed upon exit from a subroutine. In the embodiment shown inFIG. 2, register R31is specified as the return address register.

As would be understood by a person skilled in the relevant art, the purpose of specifying various registers of register bank156as either an argument register, a static register, a stack pointer register, or a return address register is to enable programs to be developed that can compile and link other program code written in a high level programing language such as, for example, C, C++, Pascal, and/or Fortran to run on a processor according to the invention. The number of registers specified in step502as argument registers and the number of registers specified in step504as static registers, however, may not be optimal for all applications. Thus, as described below, the invention enables a compiler program to encode in an instruction whether any or all of the argument registers specified in step502should be handled as static registers in order to enhance a particular feature of an application program. Method500enables a compiler program to encode in an instruction, for example, whether a value in a specified argument register is to be saved at one of two locations in a stack memory. How this is accomplished is described with regard to the following steps of method500.

In step510, fields408and410of instruction402are encoded to indicate whether static registers R16and R17are to be saved to region310of memory104upon entry to a subroutine. If a called subroutine will use a register that has been specified as a static register in step504, the value of the specified static register is saved on stack308in order to preserve the value for the program that called the subroutine. For example, if a call subroutine will use register R16of register bank156, the value of register R16is saved on stack308upon entry to the subroutine. A compiler program can ensure that the value of register R16is saved on stack308by encoding a value in field408of instruction402(e.g., by setting bit5of instruction402) that instructs a processor to save the value of register R16on stack308. In an embodiment, if the compiler clears bit5of instruction402, the value of register R16will not be saved on stack308when instruction402is executed. Similarly, whether a value in register R17is saved on stack308when instruction402is executed by a processor is determined by the state if bit4of instruction402. In an embodiment, if bit4is set, for example, the value of register R17will be saved on stack308when instruction402is executed. If bit4is cleared, the value of register R17will not be saved on stack308when instruction402is executed.

For the embodiment shown inFIG. 4, two 1-bit fields408and410are used to encode whether the values of two specified static registers are saved on stack308. In other embodiments, a single multi-bit field can be used to encode whether values of specified static registers are saved. How to do this will be understood by a person skilled in the relevant art given the description herein.

Step512of method500is not performed by the method embodiment encoded by instruction402. For the method embodiment encoded by instruction402, it is assumed that each of the registers specified in step502are to be treated as argument registers by a called subroutine. This is not the case, however, for other method embodiments of the invention encoded, for example, using instruction475. Step512is further described below with regard to instruction475.

In step514, field406of instruction402is encoded to indicate whether a value in return address register R31is to be saved to region310of memory104upon entry to a subroutine. In an embodiment, for example, the value of register R31will be saved on stack308when instruction402is executed if bit6of instruction402is set. If bit6is cleared, the value of register R31will not be saved on stack308when instruction402is executed.

Step516of method500is also not performed by the method embodiment encoded by instruction402. As described with regard to step512, for the method encoded by instruction402, it is assumed that each of the registers specified in step502is to be treated as an argument register by a called subroutine. Thus, none of the argument registers R4, R5, R6, or R7is saved as a static upon entry to a subroutine.

In step518, a value in register R16is either saved or not saved on stack308when instruction402is executed. Whether the value in register R16is saved is based on the encoding of field408. If the value in register R16is to be saved on stack308, the address of the memory location where the value is saved may be calculated any number of ways, including for example the way shown in the pseudo-code ofFIGS. 6and/or8A and8B. In an embodiment, the value in register R16is saved on stack308only if bit5of instruction402is set. Otherwise, the value of register R16will not be saved when instruction402is executed. Similarly, in step518, a value in register R17will be saved on stack308when instruction402is executed only if bit4of instruction402is set. Otherwise, the value in register R17will not be saved when instruction402is executed. If the value in register R17is to be saved on stack308, the address of the memory location where the value is saved may be calculated any number of ways, including for example the way shown in the pseudo-code ofFIGS. 6and/or8A and8B.

In step520, a value in register R31is either saved or not saved on stack308when instruction402is executed. Whether the value in register R31is saved is based on the encoding of field406. If the value in register R31is to be saved on stack308, the address of the memory location where the value is saved may be calculated any number of ways, including for example the way shown in the pseudo-code ofFIGS. 6and/or8A and8B. In an embodiment, the value in register R31is saved on stack308only if bit6of instruction402is set. Otherwise, the value of register R31will not be saved when instruction402is executed.

Lastly, in step522, the value in the specified stack pointer register (R29) is adjusted based on a value encoded in field412of instruction402. Adjusting the stack pointer allows a stack frame to be set up and memory to be allocated between the calling program and the called subroutine. In an embodiment, the value in the specified stack pointer register is adjusted by subtracting 8 times the value encoded in field412of instruction402. If the value encoded in field412is zero, the value in the stack pointer register is adjusted by subtracting128. In other embodiments, the value in the stack pointer register is adjusted by different amounts.

FIG. 6illustrates pseudo-code650according to the invention. Pseudo-code650describes to a person skilled in the relevant art how a processor according to the invention operates to implement the steps of method500encoded in an instruction402.

The steps of pseudo-code650will now be described. The steps of pseudo-code650are described with reference to register bank156, stack1300, and the example instruction402A shown below and inFIG. 13. Stack1300is shown having memory locations M0-M14. As can be seen by examining the example instruction, the encodings of the instruction fields are: “1” for return address field406; “1” for static register field408; “1” for static register field410; and “0100” (i.e., 4) for frame-size field412. The encoding for the save instruction opcode field404is shown as “XXXXXXXXX” to indicate that the encoding is a processor specific value that is unimportant for understanding the steps of pseudo-code650.

Implementation of pseudo-code650starts by storing the value of register R29(the specified stack pointer) to a temporary variable. The temporary variables in pseudo-code do not represent program variables in memory or registers, but rather temporary values of internal state within a processor. At the start of pseudo-code650, the stack pointer is assumed to have a value equal to that of stack memory location M12. After storing the stack pointer value, the value of return address field406is examined. In the case of the example instruction above, the encoded value is 1. Thus, the value of the temporary variable is reduced by four and the value in register R31(the return address) is saved at memory location M11. Next, the value of static field410is examined. In the case of the example instruction above, the encoded value is 1. Thus, the value of the temporary variable is again reduced by four and the value in register R17(register S1) is saved at memory location M10. Next, the value of static field408is examined. In the case of the example instruction above, the encoded value is 1. Thus, the value of the temporary variable is again reduced by four and the value in register R16(register SO) is saved at memory location M9. Lastly, the value of frame-size field412is examined. In the case of the example instruction above, the encoded value is 4. As indicated by pseudo-code650, the value in the specified stack pointer register (R29) is adjusted by shifting the value in frame-size field412left three bits, padding the new value with zeros, and then subtracting the new value from the value in register R29. At the end of this operation, the stack pointer points at a memory location M4, thereby defining a stack frame from M11to M4.

As will be understood by a person skilled in the relevant art, the stack pointer is adjusted in the above example to reserve space, for example, for storing values of the specified argument registers (i.e., R4, R5, R6, and R7) in stack1300. As shown inFIG. 13, memory locations M4, M5, M6, and M7can be used to save the values of registers R7, R6, R5, and R4, respectively, if necessary. Additional space, below memory location M4, can be reserved by increasing the value encoded in field412of instruction402A.

Method500will now be described in detail with regard to instruction475, register bank156, stack1400(shown inFIG. 14), and pseudo-code800(shown inFIGS. 8A and 8B) in order to point out differences between instruction475and instruction402.

As will be understood by a person skilled in the relevant art given the description herein, steps502,504,506, and508do not change when instruction475is used to encode method500rather than instruction402. Thus, the description for theses steps in not repeated here.

In step510, fields408and410of instruction475are encoded to indicate whether specified static registers R16and R17are to be saved on stack1400upon entry to a subroutine. If a called subroutine will use a register that has been specified as a static register in step504, the value of the specified static register is save on stack1400in order to preserve the value for the program that called the subroutine. As described below, in an embodiment the value of register R16is saved at memory location M5during execution of instruction475by setting bit5of instruction475to a value of 1. If bit5of instruction475is 0, the value of register R16will not be saved on stack1400when instruction475is executed. Similarly, whether a value in register R17is saved at a memory location on stack1400when instruction475is executed by a processor is determined by the state if bit4of instruction475. If bit4is set, the value of register R17will be saved, for example in memory location M6when instruction402is executed. If bit4is cleared, the value of register R17will not be saved when instruction402is executed.

In step512of method500, a binary value (e.g., 4-bit binary value) is encoded in argument registers field460(aregs) of instruction extension452to indicate which registers specified as argument registers in step502are to be treated and saved during execution of instruction475as static registers.FIG. 7illustrates a 4-bit binary encoding used in an embodiment of the invention. Other encodings, however, can also be used in accordance with method500.

In step514, field406of instruction475is encoded to indicate whether a value in specified return address register R31is to be saved, for example, at a memory location M11upon entry to a subroutine. In an embodiment, for example, the value of register R31will be saved when instruction475is executed in memory location M11if bit6of instruction475is set. If bit6is cleared, the value of register R31will not be saved when instruction475is executed.

In step516, none, one, two, three, or four of the registers R4(A0), R5(A1), R6(A2), or R7(A3) specified as argument registers in step502are saved on stack1400during execution of instruction475. Which, if any, specified argument registers are saved depends on the value encoded in field460of instruction475.FIG. 7shows which specified argument registers are treated as argument registers and which specified argument registers are treated as static registers for the 4-bit binary encoding illustrated inFIG. 7. If one or more values in registers R4, R5, R6, and R7are to be saved on stack1400, the addresses of the memory locations where the values are saved may be calculated any number of ways, including for example the way shown in the pseudo-code ofFIGS. 8A and 8B.

In step518, a value in register R16(S0) is either saved or not saved on stack1400when instruction475is executed. Whether the value in register R16is saved is based on the encoding of field408. If the value in register R16is to be saved on stack1400, the address of the memory location where the value is saved may be calculated any number of ways, including for example the way shown in the pseudo-code ofFIGS. 6and/or8A and8B. In an embodiment, the value in register R16is saved on stack1400only if bit5of instruction475is set. Otherwise, the value of register R16will not be saved when instruction475is executed. Similarly, in step518, a value in register R17(S1) will be saved on stack1400when instruction475is executed only if bit4of instruction475is set. Otherwise, the value in register R17will not be saved when instruction475is executed. If the value in register R17is to be saved on stack1400, the address of the memory location where the value is saved may be calculated any number of ways, including for example the way shown in the pseudo-code ofFIGS. 6and/or8A and8B.

In step520, a value in register R31(RA) is either saved or not saved on stack1400when instruction475is executed. Whether the value in register R31is saved is based on the encoding of field406. If the value in register R31is to be saved on stack1400, the address of the memory location where the value is saved may be calculated any number of ways, including for example the way shown in the pseudo-code ofFIGS. 6and/or8A and8B. In an embodiment, the value in register R31is saved on stack1400only if bit6of instruction475is set. Otherwise, the value of register R31will not be saved when instruction475is executed.

In step522, the value in register R29(SP) is adjusted based on a value encoded in fields458and412of instruction475. Adjusting the stack pointer value in register R29allows a stack frame to be set up. In an embodiment, the value in register R29is adjusted by subtracting 8 times the value encoded in fields412and458of instruction475. The 4-bits of field458and the 4-bits of field412are concatenated to form an 8-bit frame-size value. In other embodiments, the value in register R29is adjusted by different amounts.

Field456of instruction475is used to encode whether additional registers of register bank156are to be treated as static registers. For example, in an embodiment, registers R18, R19, R20, R21, R22, R23, and R30can be treated as additional static registers. This feature of the invention is further described below with reference to pseudo-code800.

FIGS. 8A and 8Billustrate pseudo-code800according to the invention. Pseudo-code800describes to a person skilled in the relevant art how a processor according to the invention implements the steps of method500encoded in an instruction475.

The steps of pseudo-code800will now be described. The steps of pseudo-code800are described with reference to register bank156, stack1400, and example instruction475A shown below and inFIG. 14. As can be seen by examining the example instruction, the encodings of the instruction fields are: “1” for return address field406; “1” for static register field408; “1” for static register field410; “00010100” (i.e., 20) for the concatenated frame-size fields458and412; “100” for the additional static registers field456; and “1010” for the argument registers field460. The encodings for the save instruction opcode field404and the extend instruction opcode field454are shown as “XXXXXXXXX” and “XXXXX,” respectfully, to indicate that these encodings are processor specific values that are unimportant for understanding the steps of pseudo-code800.

Implementation of pseudo-code800starts by storing the value of register R29(the stack pointer) to two temporary variables. At the start of pseudo-code800, the stack pointer is assumed to be pointing at memory location M12.

After saving the value of the stack pointer in two temporary variables, the number of argument registers is determined. In the example instruction above, the number encoded in field460is “1010.” By looking at eitherFIG. 7or pseudo-code800, it can be determined that the values in registers R4and R5are to be treaded and stored as argument values (e.g., they are to be stored as values associated with storage already allocated on the stack). In accordance with the method of the invention described by pseudo-code800, the values of argument registers are stored at a stack memory location set up or reserved by a calling program, and thus these values are not restored when control is returned to the calling program. As can be seen in pseudo-code800, the value of register R4(A0) is stored at memory location M12, and the value of register R5(A1) is stored at memory location M13.

After saving the values of the argument registers, the value of return address field406is examined. In the case of the example instruction475A, the encoded value is 1. Thus, the value of the first temporary variable is reduced by four and the value in register R31(the return address) is saved at memory location M11.

The next action is to save any additional static registers on stack1400as indicated by the encoding in register field456of instruction475A. In an embodiment, the encoding “100” indicates that the values of registers R18, R19, R20, and R21are to be saved on stack1400as static values (e.g., they are to be saved as values associated with storage not yet allocated on the stack). As indicated by pseudo-code800, the value of register R21is stored at memory location M10. The values of registers R20, R19, and R18are stored at memory locations M9, M8, and M7, respectfully.

Next, the value of static field410is examined. In the case of example instruction475A, the encoded value is 1. Thus, the value of the first temporary variable is reduced by four and the value in register R17(register S1) is saved at memory location M6.

The value of static field408is examined next. In the case of example instruction475A, the encoded value is 1. Thus, the value of the first temporary variable is again reduced by four and the value in register R16(register S0) is saved at memory location M5.

The next step of pseudo-code800is to store any argument registers on stack1400that are to be treated as static registers in accordance with the encoding of field460. From looking at eitherFIG. 7or pseudo-code800, it can be determined that the values in register R6(A2) and R7(A3) are to be saved on stack1400as static values. The value of register R7is saved at memory location M4. The value of register R6is saved at memory location M3.

Lastly, the concatenated value of frame-size fields458and412is examined and used to adjust the value in the stack pointer register, R29(SP). In the case of example instruction475A, the encoded value is 20. As indicated by pseudo-code800, the value in the register R29is adjusted by shifting the concatenated frame-size value left three bits, padding the new value with zeros, and then subtracting the new value from the value in register R29. At the end of this operation, the stack pointer points to a memory location on stack1400below memory location M0.

FIGS. 15 and 16illustrate the operation of two additional example save instructions475B and475C encoded according to the embodiment of the invention described above. The instructions are assumed to be implemented using a processor operating in accordance with pseudo-code800. As will be understood by a person skilled in the relevant art given the description herein, the invention allows software tools (e.g., a compiler) to flexibly determine whether values stored in a specified argument register are to be treated as argument values or statics values.

FIG. 9illustrates two exemplary 16-bit instructions902and975that encode method embodiments of the invention for restoring registers and deallocating memory before exit from a subroutine. Instruction902can be executed as a single, stand-alone 16-bit instruction. In addition, instruction902can be executed in combination with instruction extension952as an extended 16-bit instruction or a 32-bit instruction975.

Instruction902comprises five fields. These five fields are a 9-bit restore instruction opcode field904, a 1-bit return address register (RA) field906, a 1-bit first static register (S0) field908, a 1-bit second static register (S1) field910, and a 4-bit frame-size field912. The purpose of each of these fields is described below with regard to the steps of method1000and pseudo-code1100.

Instruction extension952comprises four fields. These four fields are a 5-bit extend instruction opcode field954, a 3-bit additional static registers field956, a 4-bit frame-size field958, and a 4-bit arguments registers field960. The purpose of each of these fields is described below with regard to the steps of method1000and pseudo-code1200.

A method1000for restoring registers and deallocating memory before exit from a subroutine according to the invention will now be describe. The steps of method1000can be encoded by instruction902and/or instruction975for implementation by a processor.

FIGS. 10A and 10Billustrate a flowchart of the steps of method1000. As illustrated in the flowchart, method1000comprises a plurality of steps divided up into three stages1001,1009, and1015. Stage1001comprises steps1002,1004,1006, and1008, and is performed prior to or during development and/or implementation of a processor design. As will be understood by a person skilled in the relevant art(s), once these steps have been performed, they need not be repeated. Steps1002-1008are an inherent part of a processor, a mapper, a decoder and/or an instruction according to the invention. Stage1009comprises steps1010,1012, and1014, and an encoding step implicit in step1022. These steps of method1000are typically performed using a compiler program. Lastly, stage1015comprises steps1016,1018,1020, and1022. These steps are performed by an apparatus or system according to the invention executing an instruction encoded according to the invention. As described herein, it is not necessary to perform each step of method1000every time the method is implemented.

In the description that follows, method1000is described with regard to instruction902, register bank156, stack1700(shown inFIG. 17), and pseudo-code1100(shown inFIG. 11). Because many of the steps of method1000are similar to the steps of method500, some of the steps of method1000are described with less detail than the steps of method500.

Method1000begins at a step1002. In step1002, at least one register of register bank156is specified as an argument register. In an embodiment of the invention, registers R4, R5, R6, and R7are specified as argument registers A0, A1, A2, and A3, respectively. In other embodiments, more or less than four argument registers can be specified in step1002. Because instructions902and975are intended to be used in conjunction with instructions402and475, the same argument registers should be specified in step1002as are specified in step502of method500above.

As already described herein, specifying a general purpose register of register bank156as an argument register is not intended to alter the nature of the general purpose register with regard to other instructions of an instruction set. A feature of the invention allows any specified argument register according to the invention to be treated as a general purpose register by instructions other than the instructions described herein. General purpose registers thus maintain all the functionality of a general purpose register with regard to other instructions. This feature of the invention applies to general purpose registers specified, for example, as a static register (e.g., S0and S1), a stack pointer register (SP), and/or a return address register (RA) in accordance with method1000.

In step1004, at least one register of register bank156is specified as a static register. In the embodiment ofFIG. 2, two registers R16and R17are specified as static registers S0and S1, respectively. In other embodiments, more or less than two registers may be specified. Again, because instructions902and975are intended to be used in conjunction with instructions402and475, the same static registers should be specified in step1004as are specified in step504of method500above.

In step1006, a register of register bank156is specified as a stack pointer register. In the embodiment shown inFIG. 2, register R29of register bank156is specified as the stack pointer register.

In step1008, a register of register bank156is specified as a return address register. In the embodiment shown inFIG. 2, register R31is specified as the return address register.

In step1010, fields908and910of instruction902are encoded to indicate whether static registers R16and R17are to be restored from stack1700before exit from a subroutine. In an embodiment, if bit4is set, the value of register R17will be restored from stack1700when instruction902is executed. If bit4is cleared, the value of register R17will not be restored from stack1700when instruction902is executed. Similarly, in an embodiment, if bit5is set, the value of register R16will be restored from stack1700when instruction902is executed. If bit5is cleared, the value of register R16will not be restored from stack1700when instruction902is executed.

Step1012of method1000is not performed by the method embodiment encoded by instruction902. For the method embodiment encoded by instruction902, it is assumed that each of the registers specified in step1002is to be treated as an argument register. This is not the case, however, for other method embodiments of the invention encoded, for example, using instruction975. Step1012is further described below with regard to instruction975.

In step1014, field906of instruction902is encoded to indicate whether a return address value in stack1700should be restored to address register R31before exit from a subroutine. In an embodiment, for example, a return address value will be loaded into register R31from stack1700when instruction902is executed only if bit6of instruction902is set. If bit6is cleared, the return address value will not be loaded into register R31when instruction902is executed.

Step1016of method1000is also not performed by the method embodiment encoded by instruction902. As described with regard to step1012, it is assumed that each of the registers specified in step1002is to be treated as an argument register. Thus, none of the argument registers R4, R5, R6, or R7is restored before exit from a subroutine.

In step1018, a static value is either loaded or not loaded into register R16from stack1700when instruction902is executed. Whether a static value is loaded into register R16is based on the encoding of field908. In an embodiment, the static value of register R16is restored only if bit5of instruction902is set. Otherwise, the value of register R16will not be restored when instruction902is executed. Similarly, in step1018, a static value of register R17will be restored from stack1700when instruction902is executed only if bit4of instruction902is set. Otherwise, the value of register R17will not be restored when instruction902is executed.

In step1020, a return address value is either loaded or not loaded into register R31from stack1700when instruction902is executed. Whether the return address value is loaded into register R31is based on the encoding of field906. In an embodiment, the return address value is loaded into register R31only if bit6of instruction902is set. Otherwise, the return address value is not loaded into register R31when instruction902is executed.

Lastly, in step1022, the value in the stack pointer register (R29) is adjusted based on a value encoded in field912of instruction902. Adjusting the stack pointer allows a stack frame to be deallocated before exit from a subroutine. In an embodiment, the value in the stack pointer register is adjusted by adding 8 times the value encoded in field912of instruction902to the value of register R29. If the value encoded in field912is zero, the value in the stack pointer register is adjusted by adding 128. In other embodiments, the value in the stack pointer register is adjusted by different amounts.

FIG. 11illustrates pseudo-code1100according to the invention. Pseudo-code1100describes to a person skilled in the relevant art how a processor according to the invention implements the steps of method1100encoded in an instruction902.

The steps of pseudo-code1100will now be described. The steps of pseudo-code1100are described with reference to register bank156, stack1700, and example instruction902A shown below and inFIG. 17. Example instruction902A can be used to restore register values save to the stack by example instruction402A, described above. As can be seen by examining example instruction902A, the encodings of the instruction fields are: “1” for return address field906; “1” for static register field908; “1” for static register field910; and “0100” (i.e., 4) for frame-size field912. The encoding for the restore instruction opcode field904is shown as “XXXXXXXXX” to indicate that the encoding is a processor specific value that is unimportant for understanding the steps of pseudo-code1100.

Implementation of pseudo-code1100starts by adjusting the value of register R29(the stack pointer) and saving the new value to a temporary variable. At the start of pseudo-code1100, the stack pointer is assumed to point to memory location M4. The new value saved in the temporary variable points to memory location M12.

After storing the adjusted stack pointer value to a temporary variable, the value of return address field906is examined. In the case of example instruction902A, the encoded value is 1. Thus, the value of the temporary variable is reduced by four and the value at memory location M11(the return address) is loaded into register R31.

Next, the value of static field910is examined. In the case of example instruction902A above, the encoded value is 1. Thus, the value of the temporary variable is again reduced by four and the value saved at memory location M10is loaded into register R17(register S1). Similarly, the value of static field908is examined. In the case of the example instruction902A, the encoded value is 1. Thus, the value of the temporary variable is again reduced by four and the value saved at memory location M9is loaded into register R16(register S0).

Lastly, as indicated by pseudo-code1100, the value in the stack pointer register (R29) is adjusted to deallocate the stack frame (e.g., the stack frame created using example instruction402A).

Method1100will now be described with regard to instruction975, register bank156, stack1800(shown inFIG. 18), and pseudo-code1200(shown inFIGS. 12A and 12B) in order to point out differences between instruction975and instruction902.

As will be understood by a person skilled in the relevant art given the description herein, steps1002,1004,1006, and1008do not change when instruction975is used to encode method1000rather than instruction902. Thus, the description for theses steps in not repeated here.

In step1010, fields908and910of instruction975are encoded to indicate whether static registers R16and R17are to be restored before exit from a subroutine. In an embodiment, if bits4and5of instruction975are set, the static values on stack1800will be restored to registers R16and R17. For example, if bit4of instruction902is set, a value at memory location M5will be loaded into register R16. Similarly, if bit5of instruction902is set, a value at memory location M6will be loaded into register R17.

In step1012of method1000, a 4-bit binary value is encoded in argument registers field960(aregs) of instruction extension952to indicate which registers specified as argument registers in step902are to be restored as static registers during execution of instruction975.FIG. 7illustrates the 4-bit binary encoding used in an embodiment of the invention. Other encodings, however, can also be used in accordance with method1000.

In step1014, field906of instruction975is encoded to indicate whether a value on stack1800is to be loaded into return address register R31before exit from a subroutine. In an embodiment, for example, a value stored at memory location M11will be loaded into register R31during execution of instruction975if bit6of instruction975is set. If bit6is cleared, no value is loaded into register R31during execution of instruction975.

In step1016, none, one, two, three, or four of the argument registers R4, R5, R6, or R7specified in step1002are restore during execution of instruction975. Which, if any, argument registers are restored depends on the value encoded in field960of instruction975.FIG. 7shows which specified argument registers are restored as static registers for the 4-bit binary encoding illustrated inFIG. 7.

In step1018, register R16is either restored or not restored during execution of instruction975. Whether register R16is restored is based on the encoding of field908. In an embodiment, register R16is restored using a value from stack1800only if bit5of instruction975is set. Otherwise, register R16is not restored when instruction975is executed. Similarly, in step1018, register R17is either restored or not restored during execution of instruction975based on the encoding of field910. In an embodiment, register R17is restored using a value from stack1800only if bit4of instruction975is set. If bit4is zero, register R17is not restored when instruction975is executed.

In step1020, register R31is either restored or not restored during execution of instruction975based on the encoding of field906. In an embodiment, register R31is restored using a value from memory location M11of stack1800only if bit6of instruction975is set. Otherwise, register R31is not restored when instruction975is executed.

In step1022, the value in register R29is adjusted based on a value encoded in fields958and912of instruction975. Adjusting the stack pointer value in register R29allows stack memory to be deallocated before exit from a called subroutine. In an embodiment, the value in register R29is adjusted by adding 8 times the frame-size value encoded in fields958and912of instruction975. The 4-bits of field958and the 4-bits of field912are concatenated to form an 8-bit frame-size value. In other embodiments, the value in register R29is adjusted by different amounts.

Field956of instruction975is used to encode whether additional registers of register bank156are restored as static registers before exit from a subroutine. For example, in an embodiment, registers R18, R19, R20, R21, R22, R23, and R30can be restored as additional static registers. This feature of the invention is further described below with reference to pseudo-code1200.

FIGS. 12A and 12Billustrate pseudo-code1200according to the invention. Pseudo-code1200describes to a person skilled in the relevant art how a processor according to the invention implements the steps of method1000encoded in an instruction975.

The steps of pseudo-code1200will now be described. The steps of pseudo-code1200are described with reference to register bank156, stack1800, and example instruction975A shown below and inFIG. 18. Example instruction975A can be used to restore static values saved to the stack using example instruction475A. As can be seen by examining the example instruction, the encodings of the instruction fields are: “1” for return address field906; “1” for static register field908; “1” for static register field910; “00010100” (i.e., 20) for the concatenated frame-size fields958and912; “100” for the additional static registers field956; and “1010” for the argument registers field960. The encodings for the restore instruction opcode field904and the extend instruction opcode field954are shown as “XXXXXXXXX” and “XXXXX,” respectfully, to indicate that these encodings are processor specific values that are unimportant for understanding the steps of pseudo-code1200.

Implementation of pseudo-code1200starts by adjusting the value of register R29(the stack pointer), based on a frame-size value encoded in fields958and912, and saving the new value to two temporary variables. As indicated by pseudo-code1200, the value in the stack pointer register (R29) is adjusted by shifting the concatenated frame-size value left three bits, padding the new value with zeros, and then adding the new value to the value in register R29. At the start of pseudo-code1200, the stack pointer is assumed to be pointing at a memory location below memory location M0(i.e, 64 bytes below memory location M0). The new value saved in the temporary variables points to memory location M12.

After storing the adjusted stack pointer value to a first and second temporary variable, the value of return address field906is examined. In the case of example instruction975A, the encoded value is 1. Thus, the value of the first temporary variable is reduced by four and the value at memory location M11(the return address) is loaded into register R31.

After restoring the return address, pseudo-code1200restores any extra static registers encoded in field956of instruction975A. As described herein, the encoding “100” indicates that registers R21, R20, R19, and R18are to be restored as extra static register. Thus, in an embodiment, the values stored at memory locations M10, M9, M8, and M7are loaded into registers R21, R20, R19, and R18, respectfully.

Next, the value of static field910is examined. In the case of example instruction975A, the encoded value is 1. Thus, the value of the first temporary variable is again reduced by four and the value saved at memory location M6is loaded into register R17(register S1). Similarly, the value of static field908is examined. In the case of example instruction975A, the encoded value is 1. Thus, the value of the first temporary variable is again reduced by four and the value saved at memory location M5is loaded into register R16(register S0).

The next step of pseudo-code1200is to restore any argument register values saved on stack1800that are to be treated as static values in accordance with the encoding of field960. From looking at eitherFIG. 7or pseudo-code1200, it can be determined that registers R6and R7are to be restored as statics registers. Accordingly, register R7is restored with the value saved at memory location M4. Register R6is restored with the value saved at memory location M3.

Lastly, as indicated by pseudo-code1200, the value in the stack pointer register (R29) is adjusted by loading register R29with the adjusted stack pointer value saved in the second temporary variable. It should be noted that registers R4and R5are not restored using the values stored at memory locations M13and M12.

Based on the description of the invention herein, a person skilled in the relevant art will understand how to implement the invention to flexibly allocate which values contained in the registers of register bank156are saved as static or argument values upon entry to a subroutine, and which registers are restored as static registers before exit from a subroutine. A person skilled in the relevant art will understand based on the description herein how to implement the invention to flexibly allocate and deallocate stack memory according to the invention.

CONCLUSION

While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example, and not limitation. It will be apparent to persons skilled in the relevant art(s) that various changes in form and detail can be made therein without departing from the spirit and scope of the invention.

In addition to implementations using hardware (e.g., within a microprocessor or microcontroller), implementations also may be embodied in software disposed, for example, in a computer usable (e.g., readable) medium configured to store the software (i.e., a computer readable program code). The program code causes the enablement of the functions or fabrication, or both, of the systems, techniques and operations disclosed herein. For example, this can be accomplished through the use of general programming languages (e.g., C or C++), hardware description languages (HDL) including Verilog HDL, VHDL, and so on, or other available programming and/or circuit (i.e., schematic) capture tools. The program code can be disposed in any known computer usable medium including semiconductor, magnetic disk, optical disk (e.g., CD-ROM, DVD-ROM) and as a computer data signal embodied in a computer usable (e.g., readable) transmission medium (e.g., carrier wave or any other medium including digital, optical, or analog-based medium). As such, the code can be transmitted over communication networks including the Internet and intranets.

It is understood that the functions accomplished and/or structure provided by the embodiments and techniques described above can be represented in a core (e.g., a microprocessor core) that is embodied in program code and may be transformed to hardware as part of the production of integrated circuits. Also, the system, techniques, and functionality may be embodied as a combination of hardware and software. Moreover, the save and restore functionality described herein may be carried out using a plurality of instructions that emulate such functionality. Thus, the present invention should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.