PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

The present disclosure discloses a package structure and a manufacturing method thereof. The package structure includes a first substrate, a second substrate, a first chip, a second chip, a heat sink and inter-board connection structures. The second substrate is provided with a first opening penetrating through an upper surface and a lower surface of the second substrate. The first chip is mounted to an upper surface of the first substrate, and the first chip is electrically connected to the first substrate. The second substrate is mounted to the upper surface of the first substrate. The inter-board connection structures are positioned between the lower surface of the second substrate and the upper surface of the first substrate, and the second substrate is electrically connected to the first substrate through the inter-board connection structures.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of China application serial no. 202310670705.3, filed on Jun. 7, 2023. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

TECHNICAL FIELD

The present disclosure relates to the field of semiconductor packaging, and in particular, to a package structure and a manufacturing method thereof.

BACKGROUND

With the increasing application demands for smartphones, smart wearables, smart manufacturing, assisted driving of automobiles and motor vehicles, and AIoT, terminal products require a small size and low power consumption while maintaining higher performance. In addition to system on chip (SoC) where chip manufacturing sites focuses on advanced silicon technology nodes, system in package (SiP) where packaging and testing manufacturing sites focuses on advanced packaging technology, is also very competitive with low cost, flexibility and high yield. With the increased integration density, SiP has also developed towards 2.5 D and 3D from early 2D packaging forms (such as Multi-Chip Module, MCM).

As a type of three-dimensional (3D) packaging, POP (Package on Package) stacked packaging generally includes an upper substrate and a lower substrate stacked up and down, and each substrate mounted with corresponding semiconductor chips. The power consumption of semiconductor chips during operation generates heat, and excessively high temperature may cause damage to devices and even cause safety hazards in severe cases; therefore, how to effectively improve the heat dissipation of the semiconductor chips, especially the heat dissipation management of those on the lower substrate, is a challenge that urgently needs to be settled in the field.

SUMMARY

In view of this, the present disclosure provides a package structure, which includes: a first substrate, a second substrate, a first chip, a second chip, a heat sink and inter-board connection structures, where the second substrate is provided with a first opening penetrating through an upper surface and a lower surface of the second substrate;the first chip is mounted to an upper surface of the first substrate, then the first chip is electrically connected to the first substrate;the second substrate is mounted to the upper surface of the first substrate, the inter-board connection structures are positioned between the lower surface of the second substrate and the upper surface of the first substrate, and the second substrate is electrically connected to the first substrate through the inter-board connection structures, and the first opening in the second substrate at least exposes a part of the back side of the first chip;the second chip is mounted to the upper surface of the second substrate, then the second chip is electrically connected to the second substrate; andthe heat sink is mounted to the back side of the first chip through the first opening.

In some embodiments, the first chip has a size larger than that of the first opening, and the first chip has a thickness thinner than that of the inter-board connection structures.

In some embodiments, the surface of the back side beyond the first opening of the first chip is adhered to the lower surface at edge of the first opening of the second substrate by a sealing material, and the first opening exposes the back side surrounded by the sealing materials of the first chip.

In some embodiments, the sealing material completely seals, partially seals, or does not seal the space between the lower surface at edge of the first opening of the second substrate and the surface of the back side beyond the first opening of the first chip.

In some embodiments, a molding compound is filled between the first substrate and the second substrate.

In some embodiments, the heat sink is further mounted to the back side of the second chip.

In some embodiments, the heat sink includes a horizontal heat dissipation area, and its bottom surface protruded with a first vertical pin and a second vertical pin, the bottom end of the first vertical pin is mounted to the back side of the first chip, a part of the bottom surface of the horizontal heat dissipation area is mounted to the back side of the second chip, and the bottom end of the second vertical pin is mounted to the upper surface of the second substrate.

In some embodiments, the first chip has a size smaller than that of the first opening, the first chip has a thickness thicker than or equal to that of the inter-board connection structures, and the back side of the first chip is positioned in the first opening.

In some embodiments, the back side of the first chip is provided with a backside metallization layer, and the heat sink is mounted to the surface of the backside metallization layer through the first opening.

In some embodiments, the inter-board connection structures include one or more of solder ball, cored metal ball, plastic core ball, metal pillar, metal block and 3D interposer, where the 3D interposer can be substrate, PCB, molding package, through-silicon via or through-glass via.

In some embodiments, a third chip and/or a first passive component electrically connected to the first substrate is further mounted onto the upper surface of the first substrate; a fourth chip and/or a second passive component electrically connected to the second substrate is further mounted onto the upper surface of the second substrate; a third passive component electrically connected to the second substrate is further mounted onto the lower surface of the second substrate; and a fourth passive component electrically connected onto the first substrate is further mounted onto the lower surface of the first substrate.

In some embodiments, gap between the first chip and the upper surface of the first substrate and between the second chip and the upper surface of the second substrate are filled with underfill.

The present disclosure further provides a manufacturing method of a package structure, which includes:providing a first substrate, a second substrate, a first chip and a second chip, where the second substrate is provided with a first opening penetrating through an upper surface and a lower surface of the second substrate;mounting the first chip to an upper surface of the first substrate, where the first chip is electrically connected to the first substrate;forming inter-board connection structures on the lower surface of the second substrate;mounting the second substrate to the upper surface of the first substrate, where the second substrate is electrically connected to the first substrate through the inter-board connection structures, and the first opening in the second substrate at least exposes a part of the back side of the first chip;mounting the second chip to the upper surface of the second substrate, where the second chip is electrically connected to the second substrate; andmounting the heat sink to the back side of the first chip through the first opening.

In some embodiments, the first chip has a size larger than that of the first opening, and the first chip has a thickness thinner than that of the inter-board connection structures.

In some embodiments, the surface of the back side beyond the first opening of the first chip is adhered to the lower surface at an edge of the first opening of the second substrate by a sealing material, and the first opening exposes the back side surrounded the sealing materials of the first chip.

In some embodiments, the sealing material completely seals, partially seals, or does not seal the space between the lower surface at edge of the first opening of the second substrate and the surface of the back side beyond the first opening of the first chip.

In some embodiments, the manufacturing method further includes: filling molding compound between the first substrate and the second substrate; and when the sealing material does not seal or partially seals the space between the lower surface at edge of the first opening of the second substrate and the surface of the back side beyond the first opening of the first chip, removing redundant molding compound on the back side below the first opening of the first chip.

In some embodiments, the back side of the first chip is provided with a backside metallization layer, and the heat sink is mounted to the surface of the backside metallization layer through the first opening.

In some embodiments, the heat sink includes a horizontal heat dissipation area, and its bottom surface protruded with a first vertical pin and a second vertical pin, the bottom end of the first vertical pin is mounted to the back side of the first chip, a part of the bottom surface of the horizontal heat dissipation area is mounted to the back side of the second chip, and the bottom end of the second vertical pin is mounted to the upper surface of the second substrate.

In some embodiments, the first chip has a size smaller than that of the first opening, the first chip has a thickness thicker than or equal to that of the inter-board connection structures, and the back side of the first chip is positioned in the first opening.

In some embodiments, the heat sink is further mounted to the back side of the second chip.

In some embodiments, the inter-board connection structures include one or more of solder ball, cored metal ball, plastic core ball, metal pillar, metal block and 3D interposer, where the 3D interposer can be substrate, PCB, molding package, through-silicon via or through-glass via.

In some embodiments, the manufacturing method further includes: mounting a third chip and/or a first passive component onto the upper surface of the first substrate, then electrically connected to the first substrate; mounting a fourth chip and/or a second passive component onto the upper surface of the second substrate, then electrically connected to the second substrate; mounting a third passive component onto the lower surface of the second substrate, then electrically connected to the second substrate; and further mounting a fourth passive component onto the lower surface of the first substrate, then electrically connected to the first substrate.

In some embodiments, the manufacturing method further includes: filling underfill between gap of the first chip and the upper surface of the first substrate and between the second chip and the upper surface of the second substrate.

Compared with the prior art, the technical solutions of the present disclosure have the following advantages:

According to the package structure and the manufacturing method thereof of the present disclosure, the package structure includes: a first substrate, a second substrate, a first chip, a second chip, a heat sink and inter-board connection structures, where the second substrate is provided with a first opening penetrating through an upper surface and a lower surface of the second substrate; the first chip is mounted to an upper surface of the first substrate, and then electrically connected to the first substrate; the second substrate is mounted to the upper surface of the first substrate, the inter-board connection structures are positioned between the lower surface of the second substrate and the upper surface of the first substrate, the second substrate is electrically connected to the first substrate through the inter-board connection structures, and the first opening in the second substrate at least exposes a part of the back side of the first chip; the second chip is mounted to the upper surface of the second substrate, and then electrically connected to the second substrate; and the heat sink is mounted to the back side of the first chip through the first opening. The second substrate is provided with the first opening penetrating through the upper surface and the lower surface of the second substrate, and the heat sink is mounted to the back side of the first chip through the first opening, so that improved the heat dissipation of the first chip assembled between the first substrate and the second substrate; meanwhile, the second substrate is electrically connected to the first substrate through the inter-board connection structures, and particularly when the inter-board connection structures are 3D interposers, thus capable of increasing an interconnection density per unit area and shortening interconnection distance, thereby providing more flexible and changeable system design for smaller package size, higher heat dissipation capacity and higher system performance.

Further, the heat sink is mounted to the back side of the second chip, that is, heat generated by the first chip and the second chip in the package structure can dissipated simultaneously through only one heat sink.

Further, the first chip has a size larger than that of the first opening, and the first chip has a thickness thinner than that of the inter-board connection structures; or the first chip has a size smaller than that of the first opening, the first chip has a thickness thicker than or equal to that of the inter-board connection structures, and the back side of the first chip is positioned in the first opening, then heat dissipation of the first chips with different thicknesses can be improved.

DETAILED DESCRIPTION OF EMBODIMENTS

The following describes specific embodiments of the present disclosure in detail with reference to accompanying drawings. For ease of description of the embodiments of the present disclosure in detail, schematic diagrams are not partially enlarged according to a general proportion. In addition, the schematic diagrams are merely examples and should not limit the protection scope of the present disclosure. Moreover, the length, width and depth of a three-dimensional space should be included in actual manufacture.

Some embodiments of the present disclosure first provide a package structure, referring toFIG.1(or referring to any one ofFIGS.2to6), which includes:a first substrate101, a second substrate102, a first chip201, a second chip202, a heat sink301and inter-board connection structures (209,215), where the second substrate102is provided with a first opening108penetrating through an upper surface and a lower surface of the second substrate102;the first chip201is mounted to an upper surface of the first substrate101, and the first chip201is electrically connected to the first substrate101;the second substrate102is mounted to the upper surface of the first substrate101, the inter-board connection structures (209,215) are positioned between the lower surface of the second substrate102and the upper surface of the first substrate101, the second substrate102is electrically connected to the first substrate101through the inter-board connection structure (209,215), and the first opening108in the second substrate102at least exposes a part of the back side of the first chip201;the second chip202is mounted to the upper surface of the second substrate102, and the second chip202is electrically connected to the second substrate102; andthe heat sink301is mounted to the back side of the first chip201through the first opening108.

The foregoing package structure includes two substrates stacked up and down, and specifically includes a first substrate101and a second substrate102positioned above the first substrate101.

The first substrate101is provided with a first line (not shown in the figure), the upper surface and the lower surface of the first substrate101are respectively provided with an upper pad103and a lower pad104which are connected to the first line, the first line, the upper pad103and the lower pad104are made of metal, and the metal may be one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold and silver. The first line may be of a single-layer or multi-layer structure, and the first line may include a metal line and a plug or a via interconnection connection (or a through via interconnection structure) electrically connected to the metal line. In an embodiment, the first substrate101may be a resin substrate, a ceramic substrate, a glass substrate, a silicon substrate or a printed circuit board (PCB). In an embodiment, surfaces of the upper pad103and the lower pad104are further provided with solder layers. In an embodiment, a part of the surface of the upper pad103and the lower pad104is further provided with a protruding metal pillar and a solder layer positioned on a top surface of the metal pillar. The solder layer is made of one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium or tin-silver-antimony, and the metal pillar is made of one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold and silver.

The second substrate102is provided with a second line (not shown in the figure), the upper surface and the lower surface of the second substrate102are respectively provided with an upper pad107and a lower pad106which are connected to the second line, the second line, the upper pad107and the lower pad106are made of metal, and the metal may be one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold and silver; the second line may be of a single-layer or multi-layer structure, and the second line may include a metal line and a plug or a via interconnection connection (or a through via interconnection structure) electrically connected to the metal line. In an embodiment, the second substrate102may be a resin substrate, a ceramic substrate, a glass substrate, a silicon substrate or a printed circuit board (PCB). In an embodiment, surfaces of the upper pad107and the lower pad106are further provided with solder layers. In an embodiment, a part of the surface of the upper pad107and the lower pad106is further provided with a protruding metal pillar and a solder layer positioned on a top surface of the metal pillar. The solder layer is made of one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium or tin-silver-antimony, and the metal pillar is made of one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold and silver.

The second substrate102is further provided with a first opening108penetrating through the upper surface and the lower surface of the second substrate102, and the first opening108serves as a channel for mounting the heat sink301to the back side of the first chip201(mounted to the upper surface of the first substrate101), so that the heat dissipation of the first chip201molded between the first substrate101and the second substrate102is improved.

The first chip201generates heat during operation. In order not to affect the performance of the first chip201and the package structure, the heat generated by the first chip201needs to be dissipated. The first chip201may be a logic chip and a memory chip. In an embodiment, the logic chip may include a gate array, a cell substrate array, an embedded array, a structured application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a central processing unit (CPU), a micro processing unit (MPU), a micro controller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power supply chip or a complementary metal-oxide-semiconductor (CMOS) image sensor. In an embodiment, the memory chip may include a volatile memory chip (such as a dynamic random access memory (DRAM) or a static RAM (SRAM)) or a non-volatile memory chip (such as a flash memory (Flash), a phase change RAM (PCRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FeRAM) or a resistive RAM (ReRAM)).

The first chip201is mounted to the upper surface of the first substrate101. In an embodiment, the first chip201includes opposite front and back sides, an integrated circuit (not shown in the figure) is formed in the first chip201, the front side of the first chip201is provided with a pad (not shown in the figure), and the pad is electrically connected to the integrated circuit. In an embodiment, a first solder bump203is further formed on the surface of the pad of the first chip201, and the first solder bump203may be made of one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium or tin-silver-antimony.

In an embodiment, when the first chip201is mounted (flip-chipped) on the upper surface of the first substrate101, a pad on the front surface of the first chip201is soldered to the upper pad103on the upper surface of the first substrate101through the first solder bump203. In other embodiments, the first chip201may be mounted face-up on the upper surface of the first substrate101through an adhesive layer, and the pad on the front surface of the first chip201is electrically connected to the upper pad103on the upper surface of the first substrate101through a lead or other connection manners.

In an embodiment, referring to any one ofFIGS.1to6, the first chip201has a size larger than that of the first opening108, and the first chip201has a thickness thinner than that of the inter-board connection structure (209), or the first chip201has a thickness thinner than a vertical distance between the upper surface of the first substrate101and the lower surface of the second substrate102.

In an embodiment, the surface of the back side of the first chip201outside the first opening is adhered to the lower surface of the second substrate102at an edge of the first opening108by a sealing material205, the first opening108exposes the back side of the first chip201between the sealing materials205, and the sealing material205allows the first substrate101and the second substrate102to provide a sealed vacuum molding channel at the first opening108for forming a molding compound111filling a space between the first substrate101and the second substrate102. In an embodiment, the sealing material205may be at least one of a metal bonding layer or an adhesive, the adhesive may or may not contain a filler, and the sealing material205may completely seal, partially seal, or do not seal a space between the second substrate at the edge of the first opening and the surface of the back side of the first chip outside the first opening. Specifically, in some specific embodiments, when the sealing is complete (referring toFIG.1,2,3,5or6), the sealing material205is in a complete circle at a back edge of the first chip201, which seals the first opening108and the space between the first substrate101and the second substrate102, and provides a sealed vacuum molding channel for the molding compound111filling the space between the first substrate101and the second substrate102, where the molding compound does not overflow into the first opening108. In some other specific embodiments, in a case that the sealing is incomplete (referring toFIG.4, the sealing material205is in a shape of a broken ring or a plurality of dots at the back edge of the first chip201) or is not achieved (referring toFIG.4), when the space between the first substrate101and the second substrate102is filled with the molding compound111, a special-shaped mold matched with the first opening108may be used to form a sealed vacuum molding channel, where the molding compound does not overflow into the first opening108; or a conventional mold may be used to form a sealed vacuum molding channel on the upper surface of the second substrate102, where the molding compound at the bottom of the first opening108on the back side of the first chip201needs to be removed from the molded first opening108later to provide a thermal conductive channel for the first chip201to directly dissipate heat outward.

In an embodiment, the surface of the back side of the first chip201is further provided with a backside metallization layer207, the backside metallization layer207is beneficial to improving the heat dissipation efficiency, and the heat sink301is mounted to the surface of the backside metallization layer207through the first opening108. In an embodiment, the backside metallization layer207is made of thermal conductive metal, and the thermal conductive metal may be one or more of aluminum, nickel, tin, tungsten, platinum, copper, titanium, chromium, tantalum, gold and silver.

The first substrate101is electrically connected to the second substrate102through inter-board connection structures (209,215), and the inter-board connection structures are also used to support the first substrate101and the second substrate102in the packaging process. The inter-board connection structures include one or more of a solder ball, a cored metal ball, a plastic core ball, a metal pillar, a metal block, a substrate, a PCB, a plastic package, a through-silicon via or a through-glass via. Specifically, in some specific embodiments, referring toFIG.1,2or4, the inter-board connection structure (209) is a cored metal ball. The cored metal ball may include a core and a metal outer layer covering the core, the core may be made of plastics or metal, and the metal outer layer is made of one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium or tin-silver-antimony. In some other specific embodiments, referring toFIG.3, the inter-board connection structures (209,215) include a cored metal ball and a 3D interposer, where the inter-board connection structure (209) is a cored metal ball, and the inter-board connection structure (215) is a 3D interposer. In still some other embodiments, referring toFIG.5or6, the inter-board connection structure (215) is a 3D interposer. The 3D interposer is one or more of substrate, PCB, molding package, through-silicon via or through-glass via, the 3D interposer is provided with a third line, and an upper surface and a lower surface of the 3D interposer are respectively provided with an upper pad and a lower pad which are electrically connected to the third line. A vertical distance between the first substrate101and the second substrate201is maintained by a combination of the foregoing various inter-board connection structures. Furthermore, the 3D interposer shortens the interconnection distance while improving the interconnection density of the package body.

In an embodiment, a third chip210and/or a first passive component211electrically connected to the first substrate101are further mounted onto the upper surface of the first substrate101. Specifically, only the third chip210or the first passive component211electrically connected to the first substrate101may be mounted onto the upper surface of the first substrate101, or the third chip210and the first passive component211electrically connected to the first substrate101may be simultaneously mounted onto the upper surface of the first substrate101. The third chip210and the first passive component211have a thickness thinner than the vertical distance between the first substrate101and the second substrate102, and the mounting numbers of the third chips210and the first passive components211are adjusted based on an actual requirement. In an embodiment, the third chip210includes an analog-to-digital conversion chip and/or a digital-to-analog conversion chip, and the first passive component211may be one or more of a resistor, a capacitor and an inductor. It should be noted that, in other embodiments, the third chip and/or first passive component may not be mounted onto the upper surface of the first substrate101.

In an embodiment, an external connection bump105connected to a part of the lower pad104is further formed on the lower surface of the first substrate101, the external connection bump105is used to connect an external device, and the external connection bump105is a solder bump or includes a metal pillar and a solder layer on a top of the metal pillar. In another embodiment, a (fourth) passive component (not shown in the figure) electrically connected to a part of the lower pad104is further mounted onto the lower surface of the first substrate101, and the (fourth) passive component may be one or more of a resistor, a capacitor and an inductor. It should be noted that, in other embodiments, the (fourth) passive component may not be mounted onto the lower surface of the first substrate101.

In an embodiment, referring to any one ofFIGS.1to6, a space between the first chip201and the first substrate101is further filled with an underfill204. The underfill204is made of a silicon-based resin material, a thermoplastic resin material, a thermally cured resin material or an ultraviolet cured resin material. The underfill204may be formed using a dispensing process. It should be noted that, in other embodiments, a space between the first chip201and the first substrate101may be filled with a molding compound instead of an underfill.

In an embodiment, referring to any one ofFIGS.1to5, a space between the first substrate101and the second substrate102may be filled with a molding compound111to protect devices between the first substrate101and the second substrate102. The molding compound111may be made of epoxy resin, polyimide resin, benzocyclobutene resin or polybenzoxazole resin, and the forming process may be an injection molding process or a transfer molding process. In another embodiment, referring toFIG.6, the space between the first substrate101and the second substrate102may not be filled with a mold compound.

The second chip202is mounted to the upper surface of the second substrate102, the second chip202also generates heat during operation, and in order not to affect the performance of the first chip201and the package structure, the heat generated by the second chip202needs to be dissipated, in the present disclosure, the heat sink301is further mounted to the back side of the second chip202, that is, the heat generated by the first chip201and the heat generated by the second chip202in the package structure are dissipated simultaneously through one heat sink301.

The second chip202may be a logic chip and a memory chip. In an embodiment, the logic chip may include a gate array, a cell substrate array, an embedded array, a structured application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), a central processing unit (CPU), a micro processing unit (MPU), a micro controller unit (MCU), a logic integrated circuit (IC), an application processor (AP), a display driver IC (DDI), a radio frequency (RF) chip, a power supply chip or a complementary metal-oxide-semiconductor (CMOS) image sensor. In an embodiment, the memory chip may include a volatile memory chip (such as a dynamic random access memory (DRAM) or a static RAM (SRAM)) or a non-volatile memory chip (such as a flash memory (Flash), a phase change RAM (PCRAM), a magnetoresistive RAM (MRAM), a ferroelectric RAM (FeRAM) or a resistive RAM (ReRAM)).

In an embodiment, the second chip202includes opposite front and back sides, an integrated circuit (not shown in the figure) is formed in the second chip202, the front side of the second chip202is provided with a pad (not shown in the figure), and the pad is electrically connected to the integrated circuit. In an embodiment, a second solder bump208is further formed on the surface of the pad of the second chip202, and the second solder bump208may be made of one or more of tin, tin-silver, tin-lead, tin-silver-copper, tin-silver-zinc, tin-zinc, tin-bismuth-indium, tin-indium, tin-gold, tin-copper, tin-zinc-indium or tin-silver-antimony.

In an embodiment, when the second chip202is mounted (flip-chipped) on the upper surface of the second substrate102, a pad on the front surface of the second chip202is soldered to the upper pad107on the upper surface of the second substrate102through the second solder bump208. In other embodiments, the second chip may be mounted face-up on the upper surface of the second substrate102through an adhesive layer, and the pad on the front surface of the second chip202is electrically connected to the upper pad107on the second substrate102through a lead or other connection structures.

The heat sink301is used to release or dissipate heat generated by the first chip201and the second chip202to control the first chip201and the second chip202in a proper temperature range. The heat sink301is made of a material with high thermal conductivity. In an embodiment, the material with high thermal conductivity includes metal (such as copper, aluminum, gold, nickel, steel or stainless steel) or a carbon-containing material (such as graphite, graphene or carbon nanotubes).

In an embodiment, the heat sink301includes a horizontal heat dissipation area, and a first vertical pin and a second vertical pin protruding from a bottom surface of the horizontal heat dissipation area, the first vertical pin passes through the first opening108in the second substrate102and the bottom end of the first vertical pin is mounted to the back side of the first chip201, a part of the bottom surface of the horizontal heat dissipation area is mounted to the back side of the second chip202, and the bottom end of the second vertical pin is mounted to the upper surface of the second substrate102. The package structure of the present disclosure can simultaneously dissipate the heat of the first chip201mounted onto the first substrate101and the heat of the second chip202mounted onto the second substrate102through one heat sink301.

In an embodiment, the bottom end of the first vertical pin of the heat sink301is mounted to the back side of the first chip201through the thermal interface material layer206, a part of the bottom surface of the horizontal heat dissipation area of the heat sink301is also mounted to the back side of the second chip202through the same or different thermal interface material layer206, and the bottom end of the second vertical pin of the heat sink301is mounted to the upper surface of the second substrate102through the adhesive layer303. The thermal interface material (TIM) layer206can effectively reduce thermal contact resistance between different structures and quickly transfer heat generated by the first chip201and the second chip202to the heat sink301. The thermal interface material layer may be made of one or more of thermal conductive silicone, thermal conductive gel, a thermal interface material layer or a metal-based thermal interface material. The adhesive layer303is made of an adhesive glue, and the adhesive glue may or may not contain a filler.

In some embodiments, a fourth chip212and/or a second passive component213electrically connected to the second substrate102are further mounted onto the upper surface of the second substrate102; and a third passive component214electrically connected to the second substrate102is further mounted to the lower surface of the second substrate102. In a specific embodiment, referring toFIG.1,3or4, a fourth chip212and a second passive component213electrically connected to the second substrate102are further mounted onto the upper surface of the second substrate102, and a third passive component214electrically connected to the second substrate102may also be mounted onto the lower surface of the second substrate102(in an embodiment, referring toFIG.3, a third passive component214may also not be mounted onto the lower surface of the second substrate102). In another specific embodiment, referring toFIG.2,5or6, only a second passive component213electrically connected to the second substrate102is further mounted onto the upper surface of the second substrate102, and a third passive component214electrically connected to the second substrate102is further mounted onto the lower surface of the second substrate102. The mounting numbers of the fourth chips212, the second passive components213and the third passive components214are adjusted based on an actual requirement.

In an embodiment, referring toFIG.1,3or4, when the fourth chip212or the second passive component213mounted onto the upper surface of the second substrate102have a high height, to reduce a thickness of the package structure as much as possible, the heat sink301is further provided with a second opening302penetrating through the upper surface and the lower surface of the heat sink, and the back side of the fourth chip212or the second passive component213may extend into the second opening302.

In another embodiment, a height of the fourth chip212and a height of the second passive component213are both thinner than a vertical distance between the bottom surface of the heat sink and the upper surface of the second substrate102, and the heat sink301does not need to be opened.

In an embodiment, a space between the second chip202and the upper surface of the second substrate102is filled with an underfill204.

Some other embodiments of the present disclosure further provide a package structure (the main differences between this embodiment and the foregoing embodiment are that a thickness of the first chip is different, and a size of the first opening108formed in the second substrate102is different; and the limitations of the same or similar parts in this embodiment and the foregoing embodiment are not described herein again. For detail, referring to the limitations of the corresponding parts in the foregoing embodiment). Referring toFIG.7,8or9, the package structure includes a first substrate101, a second substrate102, a first chip201, a second chip202, a heat sink301and inter-board connection structures (209,215), where the second substrate102is provided with a first opening108penetrating through an upper surface and a lower surface of the second substrate102; the first chip201has a size thinner than that of the first opening108, and the first chip201has a thickness larger than or equal to that of the inter-board connection structures (209,215); the first chip201is mounted to an upper surface of the first substrate101, the first chip201is electrically connected to the first substrate101, and the back side of the first chip201is positioned in the first opening108; the second substrate102is mounted to the upper surface of the first substrate101, the inter-board connection structures (209,215) are positioned between the lower surface of the second substrate102and the upper surface of the first substrate101, the second substrate102is electrically connected to the first substrate101through the inter-board connection structure (209,215); the second chip202is mounted to the upper surface of the second substrate102, and the second chip202is electrically connected to the second substrate102; and the heat sink301is mounted to the back side of the first chip201through the first opening108.

In an embodiment, referring toFIG.7, the heat sink301may also be mounted to the back side of the second chip202. The heat sink301may include a horizontal heat dissipation area, and a first vertical pin and a second vertical pin protruding from a bottom surface of the horizontal heat dissipation area, where the first vertical pin passes through the first opening108in the second substrate102and the bottom end of the first vertical pin is mounted to the back side of the first chip201(through a thermal interface material206), a part of the bottom surface of the horizontal heat dissipation area is mounted to the back side of the second chip202, and the bottom end of the second vertical pin is mounted to a top surface of a pillar306positioned on the upper surface of the first substrate101(through an adhesive layer303). The pillar306may be made of metal.

In another embodiment, referring toFIG.8, the heat sink301may include a horizontal heat dissipation area, and a first vertical pin and a second vertical pin protruding from a bottom surface of the horizontal heat dissipation area, where the first vertical lead is mounted to the back side of the first chip201through a thermal interface material206, the bottom end of the second vertical pin is mounted to the upper surface of the first substrate101(through an adhesive layer303), and the horizontal heat dissipation area is provided with a second opening302exposing the back side of the second chip202.

In another embodiment, referring toFIG.9, the heat sink301is not mounted to the second chip202, and the heat sink301is provided with a second opening302to expose the back side of the second chip202. In addition to a part of the heat sink301mounted to the back side of the first chip201(through a thermal interface material206), other parts of the heat sink301may be mounted to the surface of a molding compound111filled between the first substrate101and the second substrate101(through an adhesive layer303).

In an embodiment, a third chip210and/or a first passive component211electrically connected to the first substrate101is further mounted onto the upper surface of the first substrate101; a fourth chip (not shown in the figure) and/or a second passive component213electrically connected to the second substrate102is further mounted onto the upper surface of the second substrate102; a third passive component (not shown in the figure) electrically connected to the second substrate102is further mounted onto the lower surface of the second substrate102; and a fourth passive component (not shown in the figure) electrically connected to the first substrate101is further mounted onto the lower surface of the first substrate101. It should be noted that, in other embodiments, a third chip and/or a second passive component may not be mounted to the upper surface of the first substrate101; a fourth chip and/or a second passive component may not be mounted to the upper surface of the second substrate102; a third passive component may not be mounted to the lower surface of the second substrate102; and a fourth passive component may not be mounted to the lower surface of the first substrate101.

In an embodiment, an underfill204is filled between the first chip201and the upper surface of the first substrate101and between the second chip202and the upper surface of the second substrate102.

In an embodiment, a second molding compound112molding the second chip202and the second passive component213is formed on the upper surface of the second substrate102.

In an embodiment, the inter-board connection structures (209,215) are one or more of solder ball, cored metal ball, plastic core ball, metal pillar, metal block and 3D interposer. In a specific embodiment, the inter-board connection structure (209) is a solder ball. The inter-board connection structure (215) is a 3D interposer.

An embodiment of the present disclosure further provides a manufacturing method of a package structure (the limitations of the same or similar parts in this manufacturing method embodiment and the foregoing package structure embodiment are not described herein again, and for detail, referring to the limitations of the corresponding parts in the foregoing package structure embodiment), referring toFIG.10A to10E, which includes:providing a first substrate101, a second substrate102, a first chip201and a second chip202, where the second substrate102is provided with a first opening108penetrating through an upper surface and a lower surface of the second substrate102(referring toFIG.10AandFIG.10B);the first chip201is mounted to an upper surface of the first substrate101, and the first chip201is electrically connected to the first substrate101(referring toFIG.10A);forming an inter-board connection structure (209) on the lower surface of the second substrate102(referring toFIG.10B);mounting the second substrate102to the upper surface of the first substrate101, where the second substrate201is electrically connected to the first substrate101through the inter-board connection structure (209), and the first opening108in the second substrate201at least exposes a part of the back side of the first chip201(referring toFIG.10C);mounting the second chip202to the upper surface of the second substrate102(referring toFIG.10D); andmounting the heat sink301to the back side of the first chip201through the first opening108(referring toFIG.10E).

In an embodiment, the first chip201has a size larger than that of the first opening108, and the first chip201has a thickness thinner than that of the inter-board connection structure (209).

In an embodiment, the surface of the back side of the first chip201outside the first opening is adhered to the lower surface of the second substrate102at an edge of the first opening108by a sealing material205, and the first opening108exposes the back side of the first chip201between the sealing materials205.

In an embodiment, the sealing material205completely seals, partially seals, or does not seal the space between the second substrate102at the edge of the first opening108and the surface of the back side of the first chip201outside the first opening108.

In an embodiment, forming the sealing material205and electrically connecting the second substrate201to the first substrate through the inter-board connection structure209further includes: filling a molding compound111between the first substrate101and the second substrate102; and when the sealing material205does not seal or partially seals a space between the second substrate102at the edge of the first opening108and the surface of the back side of the first chip101outside the first opening, removing redundant molding compound on the back side of the first chip201below the first opening108.

In an embodiment, the back side of the first chip201is provided with a backside metallization layer207, and the heat sink301is mounted to the surface of the backside metallization layer207through the first opening108.

In an embodiment, the heat sink301is further mounted to the back side of the second chip202. In an embodiment, the heat sink301includes a horizontal heat dissipation area, and its bottom surface protruded with a first vertical pin and a second vertical pin, the bottom end of the first vertical pin is mounted to the back side of the first chip201, a part of the bottom surface of the horizontal heat dissipation area is mounted to the back side of the second chip202, and the bottom end of the second vertical pin is mounted to the upper surface of the second substrate102.

In an embodiment, the inter-board connection structure is one or more of solder ball, cored metal ball, plastic core ball, metal pillar, metal block and 3D interposer. In a specific embodiment, the inter-board connection structure (209) is a cored metal ball. The inter-board connection structure (215) is a 3D interposer.

In another embodiment, the first chip101has a size thinner than that of the first opening108, the first chip101has a thickness larger than or equal to that of the inter-board connection structures (209,215), and the back side of the first chip is positioned in the first opening108(referring toFIG.7,8or9).

In an embodiment, the manufacturing method further includes: mounting a third chip210and/or a first passive component211electrically connected to the first substrate101on the upper surface of the first substrate101(referring toFIG.10A); mounting a fourth chip212and/or a second passive component213electrically connected to the second substrate102on the upper surface of the second substrate102(referring toFIG.10D); and mounting a third passive component214electrically connected to the second substrate102on the lower surface of the second substrate102(referring toFIG.10B).

In an embodiment, the manufacturing method further includes: filling an underfill204between the first chip201and the upper surface of the first substrate101and between the second chip202and the upper surface of the second substrate102(referring toFIG.10AandFIG.10D).

The present disclosure has been described with reference to the preferred embodiment, which is not intended to be limited thereto. Those skilled in the art can make possible variations and modifications to the present disclosure using the disclosed methods and technical contents without departing from the spirit and scope of the present disclosure; and therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical spirit of the present disclosure without departing from the content of the technical solutions of the present disclosure shall fall within the protection scope of the technical solutions of the present disclosure.