Method and apparatus for buried word line formation

An integrated circuit with a memory cell is disclosed. The integrated circuit with a memory cell includes: a word line disposed in a word line trench of a substrate; a bit line disposed below the word line in a bit line trench and extending orthogonal to the word line; and, a separating layer disposed above the bit line in the bit line trench that separates the word line from the bit line; wherein an etching rate of the separating layer approaches that of the substrate.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to the fabrication of semiconductor integrated circuit structures, and more particularly to the formation of buried word line structures in memory cells.

2. Description of the Related Art

Semiconductor memories store bits of information in arrays of memory cells. For example, a dynamic random access memory (DRAM) cell typically includes an access field effect transistor (FET) and a storage capacitor. Memory cell word and bit lines may be buried by forming trenches in a semiconductor substrate and filling the trench with metal. Storage capacitors can be formed on the substrate surface or in the metal layers disposed above the substrate. For example, some types of DRAM cells have buried split word lines formed above buried bit lines. Some types of memory cells have buried word and bit lines.

FIG. 1Ais a perspective view of a conventional memory cell including buried word and bit lines.FIG. 1Bis a cross-section view taken along the cut line A-A ofFIG. 1Abefore buried word line trenches are formed. Referring toFIG. 1B, a silicon substrate101is initially covered with a nitride layer108, such as silicon nitride (Si3N4) and the substrate101is etched off to a preset depth, which forms the bit line trenches150. An oxide (silicon dioxide, SiO2) liner102is formed on the bottom and a portion of sidewalls of the bit line trenches150and a glue layer103is then formed over the oxide liner102. Next, a metal is deposited over the glue layer103to form the bit lines104and nitride liner108ais formed over the top of the metal104and a portion of sidewalls of the buried bit line trenches150. Finally, the resulting spaces are filled with oxide106.

Referring toFIG. 1A, a memory cell100includes buried bit and word lines104,116coupled to a vertical access transistor130disposed in a semiconductor substrate101. Vertically access transistors130are formed in semiconductor pillars that extend outwardly from an underlying substrate101. Each of the vertically access transistors130include a first source/drain region131, a channel region132and a second source/drain region133. Nitride108is formed on the first source/drain region131. The buried word lines116are arranged above the buried bit line104and extend in a trench110orthogonal to a buried bit line104.

Since the word line trenches110are orthogonal to the bit line trenches150, the silicon substrate101and the oxide layer106are alternatingly disposed along the word line trenches110. Some problems arise during the subsequent etching of the word line trenches110. First, since silicon and oxide have two different etching rates, etching depths of the silicon substrate101and the oxide layer106are entirely different, resulting in a rough sidewall and bottom surface along the word line trench110.FIG. 1Cis a cross-section view taken along the cut line A-A ofFIG. 1Aafter buried word lines are formed. Here, gate oxide and a glue layer are designated by114and115, respectively. As can be observed from the bottom of the word line trench110inFIGS. 1A and 1C, it is obvious that the etching depth of the silicon substrate101is deeper than that of the oxide layer106, leading to a depth difference y at the bottom of the trench110. Then, after a metal (not shown) such as Tungsten is filled and then recessed in the word line trench110, two adjacent word lines116in the word line trench110are formed by etching away a center region of Tungsten (hereinafter referred to as “WL separating process”). During this WL separating process, in order to clean Tungsten from the bottom of the word line trench110, the bottom of the word line trench110is subject to being over-etched, thereby resulting in a thinner or weaker isolation between the word lines116and the bit line104. On the other hand, it is difficult to clean Tungsten from the bottom of the word line trench110and thus residues of Tungsten may cause a short circuit.

Further, the word line trenches110also have rough sidewalls for the same reason of different etching rates. More specifically, the oxide sidewalls are more protruding than the silicon sidewalls when the word line trenches110are initially formed. Accordingly, after the WL separating process is performed, the thickness of Tungsten along the oxide sidewalls is generally thinner than that along the silicon sidewalls. In general, the thinner the word line (or Tungsten), the more the resistance. The rough sidewalls seriously increase gate resistance. Even though there is a single word line disposed in the trench116, its rough sidewalls and bottom also lack uniformity in gate resistance.

SUMMARY OF THE INVENTION

In view of the above-mentioned problems, an object of the invention is to provide an integrated circuit with a memory cell, which offers a word line trench having a generally smooth bottom and sidewalls, by way of disposition of a separating layer having an etching rate close to that of its substrate.

According to an embodiment of the invention, an integrated circuit is provided. The integrated circuit includes a vertical transistor, a word line, a bit line and a separating layer. The vertical transistor formed in a substrate includes a channel region arranged between a lower junction region and a upper junction region. The word line is arranged adjacent the channel region in a word line trench. The bit line is disposed below the word line in a bit line trench arranged below the vertical transistor. The separating layer is disposed above the bit line in the bit line trench that separates the word line from the bit line. Here, an etching rate of the separating layer approaches that of the substrate.

According to another embodiment of the invention, an integrated circuit with a memory cell is provided. The integrated circuit with a memory cell includes a word line, a bit line and a separating layer. The word line is disposed in a word line trench of a substrate. The bit line is disposed below the word line in a bit line trench and extending orthogonal to the word line. The separating layer is disposed above the bit line in the bit line trench that separates the word line from the bit line. Here, an etching rate of the separating layer approaches that of the substrate.

According to another embodiment of the invention, a memory device including a plurality of interconnected memory cells is provided. Each of the memory cells includes a word line, a bit line and a separating layer. The word line is disposed in a word line trench of a substrate. The bit line is disposed below the word line in a bit line trench and extends orthogonal to the word line. The separating layer is disposed above the bit line in the bit line trench that separates the word line from the buried bit line. Here, an etching rate of the separating layer approaches that of the substrate.

According to another embodiment of the invention, a method of manufacturing an integrated circuit with a memory cell is provided. The method comprises the following steps. At first, a bit line in a bit line trench of a substrate is formed. Then, a separating layer above the bit line in the bit line trench is formed. Next, a word line trench above and extending orthogonal to the bit line in the substrate is formed. Finally, a word line in the word line trench is formed. Here, the separating layer separates the word line from the bit line and an etching rate of the separating layer approaches that of the substrate.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2Ais a perspective view of a memory cell having a generally smooth word line trench according to an embodiment of the invention. Referring toFIG. 2A, a memory cell200includes buried bit and word lines104,116coupled to a vertical access transistor130disposed in a semiconductor substrate101. The memory cell200can be any type of memory cell employing buried bit and word lines104,116, such as a DRAM cell, a MRAM cell, a FLASH cell, etc. For ease of description, the memory cell200is described herein as a DRAM cell. However, those skilled in the art will appreciate that the embodiments described herein are readily applicable to other types of memory cells having buried bit and word lines104,116.

In this specification, common reference numerals have been employed where common elements have the same function as in all drawings and embodiments described herein.

FIG. 2Bis a cross-section view taken along the cut line B-B ofFIG. 2A. Two adjacent word lines116are arranged in the same trench110. A space250is not provided when a single word line116is disposed in the trench110(as shown inFIG. 5). As can be seen fromFIGS. 2A and 2B, each word line116is horizontally separated from the channel region132of a vertical access transistor130by gate oxide114and a glue layer115.

The bit line104is arranged below the word line116in a bit line trench150(not shown) formed in the semiconductor substrate101as shown inFIG. 2B. The bit line104is vertically separated from the overlying word lines116by gate oxide114, a glue layer115, a separating layer210and an oxide liner212. The silicon substrate101and the separating layer210are alternatingly disposed along the word line trenches110as shown inFIGS. 2A and 4D. In this embodiment, the substrate101is a silicon substrate. According to the invention, the separating layer210may be any material having an etching rate close to the substrate101, such as doped polysilicon, non-doped polysilicon, doped amorphous silicon, non-doped amorphous silicon, etc. Since the silicon substrate101and the separating layer210have similar etching rates, etching depths of the silicon substrate101and the separating layer210are substantially equal after the word line trenches110are initially formed. As illustrated inFIG. 2B, it is obvious that the sidewalls and the bottom of the word line trench110are quite smooth. It is noted that a recess in the separating layer210between two adjacent word lines116is formed by a subsequent WL separating process. Compared with prior art, the sidewall roughness and bottom roughness along the word line trench110are significantly improved and those conventional problems that arise because of different etching rates can be avoided.

FIG. 3is a flow chart illustrating a method for manufacturing a memory cell ofFIG. 2Aaccording to an embodiment of the invention. The steps ofFIG. 3are illustrated inFIGS. 4A-4G. The embodiment begins with forming the bit line104in the bit line trench150of the semiconductor substrate101(step310). According to one embodiment, the substrate101covered with a nitride layer108is etched off to a preset depth, which forms the bit line trenches150. Referring toFIG. 4A, an oxide liner102is formed on the bottom and a portion of sidewalls of the bit line trenches150and a glue layer103is then formed over the oxide liner102. Next, a conductive material such as Tungsten is deposited over the glue layer103and then recessed back to form the bit line104. An insulating liner212such as oxide liner is deposited on the bit line104and the sidewalls of the bit line trench150. Alternatively, the bit line104is formed by fabricating a polysilicon region in the substrate101.

Referring toFIG. 4B, in step320, the bit line trench150is filled with a separating material. Then, CMP or other suitable planarization technique is used to remove portions of the separating material above the surface of the nitride layer108. The separating material is then etched back to a level that is equal to or below the interface between the nitride layer108and the substrate101, thereby forming the separating layer210. Certainly, the top of the separating layer210needs to be higher than that of the subsequent word line116to ensure generally smooth sidewalls of the word line trench110. The separating material has an etching rate close to the substrate101. According to one embodiment, the substrate101is a silicon substrate and the separating material is non-monolithic silicon, such as doped polysilicon, non-doped polysilicon, doped amorphous silicon, non-doped amorphous silicon, etc. Isolation material214, such as SiO2, is deposited to fill the bit line trench150and the working surface is then planarized, such as by CMP, as shown inFIG. 4C.

FIG. 4Dis a cross-section view taken along the cut line C-C ofFIG. 2Aafter the word line trenches are initially formed.FIG. 4Eis a cross-section view taken along the cut line B-B ofFIG. 2Aafter the word line trenches are initially formed.

Afterward, a word line trench110is formed in the substrate101above and orthogonal to the bit line104(step330). It is obvious that the silicon substrate101and the separating layer210are alternatingly disposed along the word line trenches110as shown inFIG. 4D. Since the substrate101and the separating layer210have similar or close etching rates, their etching depths are also close to each other. As can be observed fromFIGS. 4D and 4E, the sidewalls and the bottom of the word line trench110in of the memory cell200are relatively smooth compared with those of the memory cell100inFIG. 1C. This greatly helps gate resistance uniformity in the subsequent deposition of the word line116.

Next, the word line116is formed in the word line trench110(step340). According to one embodiment, gate oxide114is first formed on the sidewalls and a bottom of the word line trench110and a glue layer115is formed over the gate oxide114as illustrated inFIGS. 4F and 4G. A conductive material such as Tungsten is deposited over the glue layer115and then recessed back to form the word line116. According to the embodiment ofFIG. 2A, a center region of Tungsten in the word line trench110is etched off and particularly into the separating layer210to form a recess in the separating layer210. Then the resulting space is filled with isolation material222such as oxide or nitride to isolate adjacent word lines116. Finally, the top insulating layer220is formed over the word lines116and the working surface is planarized, such as by CMP.

In an alternative embodiment, a single word line116is disposed in the word line trench110and the top insulating layer220is formed over the word lines116of a memory cell300as shown inFIG. 5.

While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention should not be limited to the specific construction and arrangement shown and described, since various other modifications may occur to those ordinarily skilled in the art.