Power amplifier module

Consumption current may be reduced in a power amplifier module in which a power supply voltage supplied to a power amplification transistor is controlled according to the level of output power. The power amplifier module includes an amplification transistor supplied with the power supply voltage according to the level of output power to amplify a radio-frequency signal, a bias control circuit for generating a bias voltage according to the power supply voltage, and a bias circuit for supplying a bias current according to the bias voltage to the amplification transistor, wherein current flowing through the amplification transistor when the radio-frequency signal is not input is varied according to the level of output power.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a power amplifier module.

2. Background Art

In a mobile communication device such as a mobile phone, a power amplifier module is used to amplify the power of a signal to be transmitted to a base station. Patent Document 1 discloses a configuration for variably controlling a power supply voltage supplied to a power amplification transistor in such a power amplifier module according to the level of required output power.

Patent Document 2 discloses a configuration for controlling a bias current in a power amplifier module. Specifically, in the configuration disclosed in Patent Document 2, when the peak value of collector voltage of a power amplification transistor becomes higher than a preset voltage due to a load variation, a bias circuit is controlled to increase the bias current.

CITATION LIST

Patent Documents

SUMMARY OF THE INVENTION

In the configuration disclosed in Patent Document 1, the power supply voltage is controlled according to the level of required output power, but the control of bias current is not considered. In other words, in the configuration disclosed in Patent Document 1, the reduction in current (idle current) flowing through the power amplification transistor during a no-signal condition is not considered. In the configuration disclosed in Patent Document 2, the control of bias current is performed only when the load is changed, and the reduction in idle current is not considered.

The present invention has been made in view of these circumstances, and consumption current may be reduced in a power amplifier module in which a power supply voltage supplied to a power amplification transistor is controlled according to the level of output power.

A power amplifier module according to one aspect of the present invention includes an amplification transistor supplied with a power supply voltage according to the level of output power to amplify a radio-frequency signal, a bias control circuit for generating a bias voltage according to the power supply voltage, and a bias circuit for supplying a bias current according to the bias voltage to the amplification transistor, wherein current flowing through the amplification transistor when the radio-frequency signal is not input is varied according to the level of output power.

According to the present invention, consumption current can be reduced in the power amplifier module in which the power supply voltage supplied to the power amplification transistor is controlled according to the level of output power.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

One embodiment of the present invention will be described below with reference to the accompanying drawings.FIG. 1is a diagram showing a configuration example of a transmitting unit including a power amplifier module as one embodiment of the present invention. A transmitting unit100is used, for example, in a mobile communication device such as a mobile phone, to transmit various signals such as voice and data to a base station. Note that the mobile communication device also has a receiving unit for receiving signals from the base station, but the description thereof will be omitted here.

As shown inFIG. 1, the transmitting unit100is configured to include a modulation section110, a power supply control section120, a power amplifier module130, a front-end section140, and an antenna150.

The modulation section110modulates an input signal based on a modulation scheme such as HSUPA (High Speed Uplink Packet Access) or LTE (Long Term Evolution) to generate a radio frequency (RF) signal for radio transmission. For example, the RF signal is in a range of several hundred MHz to several GHz.

The power supply control section120controls the level of power supply voltage VCCsupplied to the power amplifier module130based on a transmission power control signal. For example, the power supply control section120generates a power supply voltage VCCaccording to a level of output power (power level) of the power amplifier module130. Specifically, the power supply voltage VCCincreases as the level of output power increases. For example, the power supply control section120can include a DC-DC converter for generating a target level of power supply voltage VCCfrom a battery voltage. The transmission power control signal is generated based on, for example, an adaptive power control (APC) signal transmitted from the base station. For example, the base station can measure a signal from the mobile communication device to transmit the APC signal to the mobile communication device as a command for adjusting transmission power in the mobile communication device to an appropriate level.

The power amplifier module130amplifies the power of an RF signal (RFIN) output from the modulation section110to a level required for transmission to the base station, and outputs an amplified signal (RFOUT). The power supply voltage VCCsupplied to the power amplifier module130is controlled by the power supply control section120. The power amplifier module130operates in a power mode according to a power mode control voltage VMODEfor controlling the power mode. For example, the power modes include a low power mode (LPM) and a high power mode (HPM).

The front-end section140performs filtering for amplified signals, switching from/to signals received from the base station, and the like. The amplified signal output from the front-end section140is transmitted to the base station through the antenna150.

FIG. 2is a diagram showing an example of the configuration of the power amplifier module130. The power amplifier module130includes a bias control circuit200, a power amplifier circuit210, inductors220and221, and a matching circuit (MN)230.

The bias control circuit200generates bias voltages (VBIAS1, VBIAS2) according to the level of power supply voltage VCCsupplied to the power amplifier module130. Further, the bias control circuit200controls the output of bias voltage based on the power mode control voltage VMODE. Specifically, for example, the bias control circuit200sets the bias voltage VBIAS2to a zero level in the low power mode. The details of the bias control circuit200will be described later.

The power amplifier circuit210includes power amplification transistors PA1, PA2, and PA3, bias circuits240to242, and matching circuits (MN)250to252. The power amplifier circuit210is, for example, composed of heterojunction bipolar transistors (HBT).

The power amplification transistors PA1to PA3are NPN transistors for amplifying the power of an RF signal. The power amplification transistor PA1constitutes a drive stage, and the power amplification transistors PA2and PA3constitute a power stage. An RF signal output from the power amplification transistors PA2and PA3in the power stage is output as an amplified signal (RFOUT) through the matching circuit230.

The power supply voltage VCCis supplied to the collector of the power amplification transistor PA1through the inductor220. Further, a bias current is supplied from the bias circuit240to the base of the power amplification transistor PA1. Further, the RF signal is input to the base of the power amplification transistor PA1through the matching circuit250. Then, the power amplification transistor PA1outputs a signal, obtained by amplifying the RF signal, from the collector of power amplification transistor PA1.

The power supply voltage VCCis supplied to the collector of the power amplification transistor PA2through the inductor221. Further, the bias current is supplied from the bias circuit241to the base of the power amplification transistor PA2. Further, the RF signal output from the power amplification transistor PA1is input to the base of the power amplification transistor PA2through the matching circuit251. Then, the power amplification transistor PA2outputs a signal, obtained by amplifying the RF signal, from the collector of the power amplification transistor PA2.

The power supply voltage VCCis supplied to the collector of the power amplification transistor PA3through the inductor221. Further, the bias current is supplied from the bias circuit242to the base of the power amplification transistor PA3. Further, the RF signal output from the power amplification transistor PA1is input to the base of the power amplification transistor PA3through the matching circuit252. Then, the power amplification transistor PA3outputs a signal, obtained by amplifying the RF signal, from the collector of the power amplification transistor PA3. Note that, since the bias current is not supplied from the bias circuit242in the low power mode, the power amplification transistor PA3does not operate.

The bias circuit240generates a bias current according to the bias voltage VBAIS1to supply the bias current to the base of the power amplification transistor PA1. The bias circuit241generates a bias current according to the bias voltage VBIAS1to supply the bias current to the base of the power amplification transistor PA2. The bias circuit242generates a bias current according to the bias voltage VBIAS2to supply the bias current to the base of the power amplification transistor PA3. Note that, since the bias voltage VBIAS2is the zero level in the low power mode, the bias circuit242does not operate. For example, the bias circuits240to242can be configured by emitter-follower circuits.

FIG. 3is a diagram showing an example of the configuration of the bias control circuit200A. The bias control circuit200A includes a control current generating circuit300, a control voltage generating circuit310, and a bias voltage generating circuit320.

The control current generating circuit300generates a control current ICONTaccording to the power supply voltage VCC. The control voltage generating circuit310generates a control voltage VCONTaccording to the power supply voltage VCCbased on the control current ICONT. The bias voltage generating circuit320generates bias voltages VBIAS1and VBIAS2according to the power supply voltage VCCbased on the power mode control voltage VMODEand the control voltage VCONT. The details of each circuit will be described below.

FIG. 4is a diagram showing an example of the configuration of the control current generating circuit300A, the control voltage generating circuit310A, and the bias voltage generating circuit320A in the bias control circuit200A.

The control current generating circuit300A includes P-channel FETs (P1to P3), N-channel FETs (N1to N4), a constant current source IA(first constant current source), a constant current source IB(second constant current source), and a resistor RC(first resistor).

The gate of the N-channel FET (N1) (first N-channel FET) is supplied with a reference voltage VREF(first reference voltage), the drain is connected to the drain of the P-channel FET (P1), and the source is connected to the constant current source IA. The reference voltage VREFis, for example, a band-gap voltage generated based on the battery voltage. The gate of the N-channel FET (N2) (second N-channel FET) is supplied with the power supply voltage VCC, the drain is connected to the drain of the P-channel FET (P2), and the source is connected to the constant current source IB. The resistor RCis provided between the source of the N-channel FET (N1) and the source of the N-channel FET (N2). The N-channel FETs (N1, N2) are the same size, for example.

The P-channel FET (P1) is diode-connected. The P-channel FET (P2) is also diode-connected. The P-channel FET (P3) is current-mirror connected to the P-channel FET (P1). The size ratio of the P-channel FETs (P1to P3) is, for example, 1:1:m1.

The N-channel FET (N3) is diode-connected with the drain connected to the drain of the P-channel FET (P3). The N-channel FET (N4) is current-mirror connected to the N-channel FET (N3) to output the control current ICONTfrom the drain of the N-channel FET (N4). The size ratio of the N-channel FETs (N3, N4) is, for example, 1:m2.

Here, the currents of the constant current sources IAand IBare denoted as IAand IB, respectively. Current flowing from the source of the N-channel FET (N2) into the source of the N-channel FET (N1) through the resistor RCis denoted as IC. Currents flowing through the P-channel FETs (P1, P2) are denoted as IDand IE, respectively. The resistance value of the resistor RCis denoted as RC. The source voltages of the N-channel FETs (N1, N2) are denoted as VAand VB, respectively. Under this condition, the current flowing through the N-channel FET (N4), i.e., the control current ICONTwill be described.

First, IA+IB=ID+IEis established in the control current generating circuit300A. Further, IA=ID+ICand IB=IE−ICare established. Then, ICONT=m1×m2×IDis established. Note that the current IDis current (differential current) corresponding to a difference between VREF(first reference voltage) and the power supply voltage VCC.

When VCC>VREF, VB>VA, and k becomes positive. Since IAis a constant current, IDdecreases compared to the case when VCC=VREF. Therefore, ICONTdecreases as VCCrises. Note that the minimum value of IDis zero. In other words, the minimum value of ICONTis zero.

When VCC<VREF, VB<VA, and ICbecomes negative. Since IAis a constant current, IDincreases compared to the case when VCC=VREF. Therefore, ICONTincreases as VCCdrops. Note that maximum value of IDis ID=IA+IB. In other words, the maximum value of ICONTis ICONT=m1×m2×(IA+IB).

Thus, the control current generating circuit300A generates the control current ICONTvarying according to the power supply voltage VCC. Note that ICthat affects the variation of the control current ICONTby IC=(VB−VA)/RC. Therefore, the rate of change of the control current ICONTaccording to the change in the power supply voltage VCCvaries with the value of RC. Thus, the dynamic range (a VCCrange where ICONTvaries) of the control current generating circuit300A can be controlled by the value of RC. Specifically, when the value of RCis relatively small, the rate of change of ICONTaccording to VCCincreases and the dynamic range becomes smaller. On the other hand, when the value of RCis relatively large, the rate of change of ICONTaccording to VCCdecreases and the dynamic range becomes larger.

The control voltage generating circuit310A includes an operational amplifier OP1, P-channel FETs (P4, P5), and resistors RF, RG.

The operational amplifier OP1is such that the reference voltage VREFis applied to a non-inverting input terminal and an inverting input terminal is connected to an output terminal and one end of the resistor RF. The other end of the resistor RFis grounded. The drain of the P-channel FET (P4) is connected to the output terminal of the operational amplifier OP1. The P-channel FET (P5) is current-mirror connected to the P-channel FET (P4), and the drain of the P-channel FET (P5) is connected to one end of the resistor RG(current-voltage conversion circuit). The size ratio of the P-channel FETs (P4, P5) is, for example, 1:m3. The output of the control current generating circuit300A is also connected to one end of the resistor RG.

Here, the resistance values of the resistors RF, RGare denoted as RFand RG, respectively. Currents flowing through the P-channel FETs (P4, P5) are denoted as IFand IG, respectively. Under this condition, the control voltage VCONTsupplied to the bias voltage generating circuit320A will be described.

The voltage applied to one end of the resistor RFthrough a virtual short-circuit of the operational amplifier OP1becomes VREF. Therefore, IFis IF=VREF/RF, and IG=m3×IF. As a result, the voltage at one end of the resistor RG, i.e., VCONTbecomes VCONT=(IG−ICONT)×RG.

Thus, the control voltage generating circuit310A generates the control voltage VCONTbased on the reference current IGaccording to the reference voltage VREFand the control current ICONT. Note that, since the control current ICONTis current according to the power supply voltage VCC, the control voltage VCONTbecomes voltage according to the power supply voltage VCC.

The bias voltage generating circuit320A includes an operational amplifier OP2, resistors RX, RY, and a switch S1.

The control voltage VCONTis applied to a non-inverting input terminal of the operational amplifier OP2. The operational amplifier OP2and the resistors RX, RYconstitute a non-inverting amplifier circuit. In other words, a bias voltage VBIASobtained by amplifying the control voltage VCONTis output from an output terminal of the operational amplifier OP2. An output terminal of the operational amplifier OP2is connected to an output terminal of the bias voltage VBIAS1and one end of the switch S1.

The switch S1outputs the bias voltage VBIASor a zero level of voltage as the bias voltage VBIAS2based on the power mode control voltage VMODE. Specifically, in the low power mode, the switch S1is connected to the ground to output the zero level of voltage as the bias voltage VBIAS2. On the other hand, in the high power mode, the switch S1is connected to the output terminal of the operational amplifier OP2to output the bias voltage VBIASas the bias voltage VBIAS2.

Thus, the bias voltage generating circuit320A generates the bias voltages VBIAS1and VBIAS2based on the power mode control voltage VMODEand the control voltage VCONT. Note that, since the control voltage VCONTis voltage according to the power supply voltage VCC, the bias voltages VBIAS1and VBIAS2are also voltages according to the power supply voltage VCC. As a result, bias currents generated in the bias circuits240to242based on the bias voltages VBIAS1and VBIAS2become currents according to the power supply voltage VCC. Accordingly, the bias current is reduced according to a reduction in output power in the power amplifier module130where the power supply voltage VCCsupplied to the power amplification transistors PA1to PA3is controlled according to the level of output power. Thus, since the idle current (current flowing through the power amplification transistors PA1to PA3when no RF signal is input) is reduced according to the reduction in output power in the power amplifier module130, the consumption current can be reduced.

FIG. 5is a diagram showing another example of the configuration of the control current generating circuit300B, the control voltage generating circuit310A, and the bias voltage generating circuit320A in the bias control circuit200A. Since the configuration of the control voltage generating circuit310A and the bias voltage generating circuit320A shown inFIG. 5is the same as that shown inFIG. 4, the description thereof will be omitted.

The P-channel FET (P6) (first P-channel FET) is diode-connected. The P-channel FET (P7) (second P-channel FET) is current-mirror connected to the P-channel FET (P6). The gate of the P-channel FET (P8) is connected to the drain of the P-channel FET (P7), and the drain of the P-channel FET (P8) is connected to one end of the resistor RH. The P-channel FET (P9) is current-mirror connected to the P-channel FET (P8) to output the control current ICONTfrom the drain of the P-channel FET (P9). The size ratio of the P-channel FETs (P8, P9) is, for example, 1:m4.

The N-channel FET (N5) (third N-channel FET) is such that the gate is connected to one end of the resistor RH, the drain is connected to the drain of the P-channel FET (P6), and the source is connected to the current source I5. The N-channel FET (N6) (fourth N-channel FET) is such that the power supply voltage VCCis applied to the gate, the drain is connected to the drain of the P-channel FET (P7), and the source is connected to the current source I5.

Here, the current flowing through the P-channel FET (P9), i.e., the control current ICONTwill be described, where the resistance value of the resistor RHis denoted as RHand the current flowing through the P-channel FET (P8) is denoted as IH.

The P-channel FETs (P6, P7), the N-channel FETs (N5, N6), and the current source I5form a circuit constituting an operational amplifier. The voltage at one end of the resistor RHbecomes the power supply voltage VCCthrough a virtual short-circuit of this operational amplifier. Therefore, the current IHflowing through the P-channel FET (P8) is IH=VCC/RH. As a result, the control current ICONTis ICONT=m4×VCC/RH.

Thus, the control current generating circuit300B shown inFIG. 5generates the control current ICONTvarying according to the power supply voltage VCC. Note that the rate of change of the control current ICONTvaries with the value of RH.

In the configuration shown inFIG. 4, the control voltage VCONTis controlled by subtracting the control current ICONTfrom the reference current IG, whereas in the configuration shown inFIG. 5, the control voltage VCONTis controlled by adding the control current ICONTto the reference current IG. In other words, VCONT=(IG+ICONT)×RG. In the configuration shown inFIG. 5, ICONT=m4×VCC/RH, resulting in reducing the control current ICONTwith a drop in power supply voltage VCC. Therefore, the control voltage VCONTis reduced according to the drop in the power supply voltage VCC. As a result, since the idle current is reduced according to the reduction in output power in the power amplifier module130, the consumption current can be reduced.

FIG. 6is a diagram showing still another example of the configuration of the control current generating circuit300C, the control voltage generating circuit310A, and the bias voltage generating circuit320A in the bias control circuit200A. Note that, since the configuration of the control voltage generating circuit310A and the bias voltage generating circuit320A shown inFIG. 6is the same as that inFIG. 4, the description thereof will be omitted.

The NPN transistor T1(first NPN transistor) is diode-connected in such a manner that the power supply voltage VCCis applied to the collector and the power supply voltage VCCis applied to the base through the resistor RJB. The NPN transistor T2(second NPN transistor) is current-mirror connected to the NPN transistor T1through the resistor RKB. The NPN transistors T1and T2are, for example, of the same size.

The resistor RJBis provided between the base and the collector of the NPN transistor T1, and the resistor RJE(third resistor) is provided between the emitter of the NPN transistor T1and the ground. The resistor RKBis provided between the base of the NPN transistor T2and the collector of the NPN transistor T1, and the resistor R (fourth resistor) is provided between the emitter of the NPN transistor T2and the ground. For example, the resistors RJBand RKBhave the same resistance value. Further, for example, the resistors RJEand RKEhave the same resistance value.

The P-channel FET (P10) is diode-connected with the drain connected to the collector of the NPN transistor T2. The P-channel FET (P11) is current-mirror connected to the P-channel FET (P10) to output the control current ICONTfrom the drain of the P-channel FET (P11). The size ratio of the P-channel FETs (P10, P11) is, for example, 1:m5.

Here, the current flowing through P-channel FET (P11), i.e., the control current ICONTwill be described, where the resistance value of the resistor RJis denoted as RJE, the base-emitter voltage of the NPN transistor T1is denoted as VBE, and the collector currents of the NPN transistors T1and T2are denoted as IJand IK, respectively.

When the base current of the NPN transistor T1is ignored for ease of description, IJ=(VCC−VBE)/RJE, where IK=IJ. Therefore, ICONT=m5×(VCC−VBE)/RJE.

Thus, the control current generating circuit300C shown inFIG. 6generates the control current ICONTvarying according to the power supply voltage VCC. In the configuration shown inFIG. 6, the control voltage VCONTis controlled by adding the control current ICONTto the reference current IGlike in the configuration shown inFIG. 5. In other words, VCONT=(IG+ICONT)×RG. In the configuration shown inFIG. 6, ICONT=m5×(VCC−VBE)/RJE, resulting in reducing the control current ICONTwith a drop in power supply voltage VCC. Therefore, the control voltage VCONTis reduced according to the drop in the power supply voltage VCC. As a result, since the idle current is reduced according to the reduction in output power in the power amplifier module130, the consumption current can be reduced.

FIG. 7is a diagram showing another example of the configuration of the bias voltage generating circuit320B. The bias voltage generating circuit320B shown inFIG. 7can be used instead of the bias voltage generating circuit320A shown inFIG. 4toFIG. 6. Note that the same reference numerals are used for the same elements as those in the bias voltage generating circuit320A shown inFIG. 4toFIG. 6to omit redundant description.

In addition to the configuration of the bias voltage generating circuit320A shown inFIG. 4toFIG. 6, the bias voltage generating circuit320B shown inFIG. 7includes a resistor RZand a switch S2.

The resistors RYand RZare connected in series and provided between the inverting input terminal and the output terminal of the operational amplifier OP2. The switch S2is provided between both ends of the resistor RZto operate based on the power mode control voltage VMODE. Specifically, the switch S2is on in the low power mode or off in the high power mode. Therefore, the bias voltage VBIASgenerated by the bias voltage generating circuit320B is low in the low power mode. This can further reduce the consumption current at the time of low power.

FIG. 8is a diagram showing another example of the configuration of a bias control circuit200B. The bias control circuit200B shown inFIG. 8includes a temperature compensation circuit800in addition to the configuration of bias control circuit200A shown inFIG. 3. The temperature compensation circuit800generates adjustment currents IADJ1and IADJ2for adjusting the bias current according to the temperature characteristics of the amplification transistors PA1to PA3of the power amplifier circuit210.

FIG. 9is a diagram showing an example of the configuration of the temperature compensation circuit800and the control voltage generating circuit310B in the bias control circuit200B shown inFIG. 8. Note that any of the configurations shown inFIG. 4toFIG. 7can be adopted for the control current generating circuit300and the bias voltage generating circuit320.

The operational amplifier OP3is such that the reference voltage VREFis applied to a non-inverting input terminal and an inverting input terminal is connected to an output terminal and one end of the resistor RL. The other end of the resistor RLis connected to the anode of the diode D1, and the cathode of the diode D1is grounded.

The drain of the P-channel FET (P12) is connected to the output terminal of the operational amplifier OP3. The P-channel FET (P13) is current-mirror connected to the P-channel FET (P12), and the drain of the P-channel FET (P13) is connected to the drain of the N-channel FET (N7). The size ratio of the P-channel FETs (P12, P13) is, for example, 1:m6.

The N-channel FET (N7) is diode-connected, and the drain of the N-channel FET (N7) is connected to the drain of the P-channel FET (P13). The N-channel FET (N8) is current-mirror connected to the N-channel FET (N7) to output the adjustment current IADJ1from the drain of the N-channel FET (N8). The N-channel FET (N9) is current-mirror connected to the N-channel FET (N7), and the drain of the N-channel FET (N9) is connected to the source of the N-channel FET (N10). The gate of the N-channel FET (N10) is connected to the source of the P-channel FET (P19) of the control voltage generating circuit310B to output the adjustment current IADJ2from the drain of the N-channel FET (N10). The size ratio of the N-channel FETs (N7, N8, N9) is, for example, 1:m7:m8.

Here, the resistance value of the resistor RLis denoted as RL, a forward-drop voltage across the diode D1is denoted as VDT, and currents flowing through the P-channel FETs (P12, P13) are denoted as ILand IM, respectively. Under this condition, the adjustment currents IADJ1and IADJ2will be described.

The voltage at one end of the resistor RLbecomes VREFthrough a virtual short-circuit of the operational amplifier OP3. Further, the voltage at the other end of the resistor RLbecomes VDT. Therefore, IL=(VREF−VDT)/RL, and IM=m6×IL. As a result, IADJ1=m6×m7×ILand IADJ2=m6×m8×IL. Note that the forward-drop voltage VDTvaries according to the temperature characteristics of the diode D1. Specifically, for example, VDThas such characteristics that it rises at low temperature and drops at high temperature. Thus, IADJ1and IADJ2vary according to the temperature characteristics of the diode D1.

The control voltage generating circuit310B shown inFIG. 9includes P-channel FETs (P14to P19) and a resistor RPin addition to the configuration shown inFIG. 4. Note that the same reference numerals are used for the same elements as those in the control voltage generating circuit310A shown inFIG. 4to omit redundant description.

The P-channel FETs (P14, P15, P16) are current-mirror connected to the P-channel FET (P4). The P-channel FET (P17) is diode-connected with the source connected to the drain of the P-channel FET (P15) and the drain connected to the drain of the P-channel FET (P16). The P-channel FET (P18) is current-mirror connected to the P-channel FET (P17) with the drain connected to one end of the resistor RG. The P-channel FET (P19) is such that the reference voltage VREFis applied to the gate, the source and the back gate are connected to the other end of the resistor RP, and the drain is grounded. The size ratio of the P-channel FETs (P4, P5, P14) is, for example, 1:m3:m9. Further, the size ratio of the P-channel FETs (P17, P18) is, for example, 1:m10.

Here, the resistance values of the resistors RF, RG, and RPare denoted as RF, RG, and RP, respectively. Currents flowing through the P-channel FETs (P4, P5, P14to P18) are denoted as IF, IG1, IG2, IP1, IQ, IP2, and IR, respectively. Further, current flowing through the resistor RGis denoted as IG. Under this condition, the control voltage VCONTsupplied to the bias voltage generating circuit320will be described.

The voltage applied to one end of the resistor RFthrough a virtual short-circuit of the operational amplifier OP1becomes VREF. Therefore, IFis IF=VREF/RF. Further, IG1=m3×IFand IG2=m9×IF. Further, IP2=IADJ2−IQ. As a result, IR=m10×Ip2=m10×(IADJ2−IQ).

When the control current generating circuit300has the configuration shown inFIG. 4, IG=IG1+IG2+IR−IADJ1−ICONT=IG1−ICONT+(IG2−IADJ1)+m10×(IADJ2−IQ). Then, the control voltage VCONT=IG×RG. When the control current generating circuit300has the configuration shown inFIG. 5orFIG. 6, IG=IG1+IG2+IR−IADJ1+ICONT. The following description will be made assuming that the control current generating circuit300has the configuration shown inFIG. 4.

The temperature compensation circuit800and the control voltage generating circuit310B are designed so that IG2=IADJ1and IQ=IADJ2at a predetermined temperature T. In other words, IG=IG1−ICONTat the temperature T.

When the temperature is lower than T, since IQ>IADJ2, IRbecomes zero. Therefore, IG=IG1−ICONT+(IG2−IADJ1). IADJ1increases as the temperature rises. Thus, in a range where the temperature is lower than T, IGdecreases according to the rate of change of IADJ1as the temperature rises.

When the temperature is higher than T, since IQ<IADJ2, IRbecomes positive. Therefore, IG=IG1−ICONT+(IG2−IADJ1)+m10×(IADJ2−IQ). IADJ2increases as the temperature rises. Thus, in a range where the temperature is higher than T, IGdecreases according to the rates of change of IADJ1and IADJ2as the temperature rises. Note that, since IRis added to IGin the range where the temperature is higher than T, the rate of decrease in IGwith a rise in temperature becomes lower than that in the range where the temperature is lower than T.

Thus, the temperature compensation circuit800generates the adjustment currents IADJ1and IADJ2varying according to the temperature characteristics of the amplification transistors PA1to PA3. This leads to the adjustment of the bias voltages VBIAS1and VBIAS2supplied to the power amplifier circuit210according to the temperature characteristics of the amplification transistors PA1to PA3.

Further, in the configuration shown inFIG. 9, if the source voltage of the P-channel FETs (P17, P18) is denoted as VP1and the gate-source voltage of the P-channel FET (P19) is denoted as VPGS19, VP1=VREF+VPGS19+IP×RP. Note that IP=IP1−(IP2+IR). Further, if the drain voltage of the N-channel FET (N9) is denoted as VN1and the gate-source voltage of the N-channel FET (N10) is denoted as VNGS10, VN1=VREF+VPGS19−VNGS10.

Thus, in the configuration shown inFIG. 9, the source voltage VP1of the P-channel FETs (P17, P18) and the drain voltage VN1of the N-channel FET (N9) are independent of the variation of the battery voltage VBAT. Therefore, the dependence of the control voltage VCONTon the battery voltage VBATcan be reduced.

FIG. 10is a graph showing simulation results in the low power mode in the configuration shown inFIG. 9.FIG. 11is a graph showing simulation results in the high power mode in the configuration shown inFIG. 9. InFIG. 10andFIG. 11, the abscissa indicates power supply voltage VCC[V] and the ordinate indicates bias voltage VBIAS[V].

As shown inFIG. 10, the bias voltage VBIASdecreases with a drop in power supply voltage VCCin a dynamic range of about 1.9 V at any of temperatures 25° C., 85° C., and −20° C. Thus, the consumption current can be reduced during low power. Further, as shown inFIG. 10, the bias voltage VBIASvaries according to the temperature. This can lead to the adjustment of the bias current according to the temperature characteristics of the amplification transistors PA1to PA3. The same holds true for the high power mode shown inFIG. 11.

The embodiment has been described above. According to the embodiment, the bias voltage VBIASdecreases with a drop in power supply voltage VCCto reduce the bias current. Thus, since the idle current is reduced according to a reduction in output power in the power amplifier module130in which the power supply voltage VCCsupplied to the power amplification transistors PA1to PA3is controlled according to the level of output power, the consumption current can be reduced.

Note that the embodiment is to facilitate the understanding of the present invention, and not to limit the present invention. The present invention can be changed/modified without departing from the scope thereof, and equivalents can also be included in the present invention.

DESCRIPTION OF REFERENCE NUMERALS