Semiconductor devices having discretely located passivation material, and associated systems and methods

Semiconductor devices having discretely located passivation material are disclosed herein. In one embodiment, a semiconductor device assembly can include a bond pad having a bonding surface with a process artifact. A passivation material can be positioned to at least partially fill a portion of the process artifact. A conductive structure can be positioned to extend across the bonding surface of the bond pad, and a conductive interconnect can extend from the conductive structure.

TECHNICAL FIELD

The disclosed embodiments relate to semiconductor devices, and in particular to semiconductor devices having discretely located passivation material.

BACKGROUND

Packaged semiconductor dies, including memory chips, microprocessor chips, and imaging chips, typically include one or more semiconductor dies mounted on a substrate and at least partially encased in a protective covering. The dies include functional features, such as memory cells, processor circuits, and imaging devices, as well as bond pads electrically connected to the functional features. The bond pads can, in turn, be electrically connected to terminals outside the protective covering to allow the die to be connected to higher level circuitry. Additionally, in devices having multiple dies (e.g., vertically stacked dies), interconnects or pillars can electrically connect adjacent dies via corresponding bond pads.

To provide a reliable and robust electrical connection, conductive materials that are connected to the bond pads need to be securely and uniformly bonded thereto. However, the fabrication of packaged semiconductors typically includes one or more processes that expose the bond pads and/or the conductive materials to corrosive chemicals that can corrode, degrade, or otherwise interfere with the bond between the bond pad pads and the conductive materials. A variety of techniques are used to minimize the adverse effects of the corrosive chemicals, but existing fabrication processes present opportunities for corrosion at the bond pads that can lead to degradation or failure of the electrical connections.

DETAILED DESCRIPTION

Specific details of several embodiments of semiconductor devices having discretely located passivation material are described below. The term “semiconductor device” generally refers to a solid-state device that includes semiconductor material. A semiconductor device can include, for example, a semiconductor substrate, wafer, or die that is singulated from a wafer or substrate. Throughout the disclosure, semiconductor devices are generally described in the context of semiconductor dies; however, semiconductor devices are not limited to semiconductor dies.

The term “semiconductor device package” can refer to an arrangement with one or more semiconductor devices incorporated into a common package. A semiconductor package can include a housing or casing that partially or completely encapsulates at least one semiconductor device. A semiconductor device package can also include an interposer substrate that carries one or more semiconductor devices and is attached to or otherwise incorporated into the casing. The term “semiconductor device assembly” can refer to an assembly of one or more semiconductor devices, semiconductor device packages, and/or substrates (e.g., interposer, support, or other suitable substrates).

In the following description, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the technology. One skilled in the relevant art, however, will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with semiconductor devices are not shown, or are not described in detail, to avoid obscuring aspects of the technology. For example, several functional components of semiconductor dies, device assemblies, devices and packages that are known in the art are not discussed in detail below (e.g., doped semiconductor materials and active regions).

FIG. 1Ais a partially schematic, overhead view of a portion of a prior art semiconductor device100. In particular, the semiconductor device100is a wafer having a die102. The die102includes a plurality of exposed bond pads104that are electrically connected to functional features of the die102. The wafer100is shown in an intermediate stage of manufacture, before interconnects are added to the bond pads104, but subsequent to testing of the die102. More particularly, the die102includes process artifacts106on surfaces108of the bond pads104. Specifically, the process artifacts106are probe scrub marks formed in the bond pad surface108during testing of the die102. To test the die102, probe tips are brought into contact with the surfaces108of corresponding bond pads104to form electrical connections between the bond pads104and the probe tips. Before testing, however, the surfaces108may oxidize and have an oxidation layer that can prevent electrical contact between the probe tips and the surfaces108. To ensure a proper connection, the probe tips must penetrate any oxidation layer and maintain positive contact with the bond pads104.

Various designs and methods can ensure a proper electrical connection between the probe tips and the bond pads104. In general, these designs and methods produce a disruption of any oxidation layer, as well as a disruption of the surfaces108, resulting in the scrub marks106. In many cases, the probe tips contact the surfaces108at an angle, or otherwise include a horizontal component of motion that is parallel to the surfaces108. Such movement produces a brow of material that is pushed upward in front of the probe tips, as well as furrows that are generated along the sides of the probe tips. Additionally, the motion of the probe tips can create voids, crevices, or other irregular features or process artifacts in the surfaces108.

FIG. 1Bis a partially schematic, cross-sectional view of a portion of the prior art die102after the addition of an interconnect or pillar110. The die102can include a substrate112(e.g., silicon) and a plurality of materials114positioned between the substrate112and the bond pad104. Subsequent to the testing that was described above, the die102undergoes several additional processing steps prior to the addition of the pillar110. First, etching or other removal techniques are used to remove any oxidation on the surface108. Subsequently, a bonding and/or seeding material116is added to the die102via physical vapor deposition or other techniques known in the art. The pillar110is subsequently formed via, e.g., plating above the bond pad104and on the seeding material116. The pillar110is thereby bonded to the bond pad104via a bond118that includes the bonding and/or seeding material116.

Subsequent and/or prior to the formation of the pillar110, the wafer100and die102can be subjected to process chemicals that are corrosive to the bond pad104. Although the bonding and/or seeding material116can act as a barrier to inhibit exposing the bond pad104to the corrosive chemicals, the coverage of the material116may not be continuous. For example, the material116may only provide step coverage due to underlying irregularities (e.g., the scrub mark106). Additionally, the material116may have cracks, crevices, voids, or other discontinuities that allow corrosive process chemicals to contact the bond pad104. In general, these corrosive chemicals are removed during follow on processes, and they are only in contact with the bond pad104for a limited time. Accordingly, for most portions of the surface108, the chemicals generally do not present significant corrosion concerns. At the scrub mark106, however, the process chemicals can be retained within voids or other irregularities in the surface108, and produce relatively significant corrosion.

FIG. 1Cis a partially schematic, cross-sectional view of the prior art die102illustrating a magnified view of a portion of the bond118. As shown, the bond118includes significant corrosion120of the bond pad104and of the bonding and/or seeding material116at the scrub mark106. Specifically, the illustrated portion of the bond118shows the corrosion120formed via action of corrosive process chemicals that become “trapped” or otherwise contained within a void122located under a brow124.

FIGS. 2A and 2Bare partially cross-sectional, and cross-sectional focused ion beam scanning electron microscope (FIB-SEM) images, respectively, of a prior art wafer200illustrating several of the features discussed above with respect toFIGS. 1A to 1C.FIG. 2A, for example, is an SEM at 1200× magnification, showing the wafer200, a die202, a bond pad204, a pillar206, and a bond208between the pillar206and the bond pad204.FIG. 2Bis an SEM at 15000× magnification showing the bond208and corrosion210in the bond pad204and in a bonding material212. As shown inFIG. 2B, corrosive process chemicals have corroded significant portions of the bond pad204and the bonding material212, creating voids214through portions of the bond pad204, the bonding material212, and the pillar206. The voids214and the corrosion210can increase the resistance of the electrical connection between the pillar206and the bond pad204, producing increased heat and decreased performance of an associated finished device. Moreover, the corrosion can result in failure of the bond208and the finished device.

FIGS. 3A to 9illustrate the formation of a semiconductor device assembly configured in accordance with an embodiment of the present technology. First,FIG. 3Ais a partially schematic, cross-sectional view of a die300configured in accordance with an embodiment of the present technology. The die300may be one of a plurality of identical dies that are simultaneously fabricated on an associated wafer to include the same features. In the illustrated embodiment, the die300includes a substrate302, dielectric materials304, conductive features306(e.g., traces, redistribution structures, contact pads, etc.), and a bonding element or bond pad308having a surface310. The cross-sectional view ofFIG. 3Aillustrates a cross-sectional view of a portion of the die300at a particular location (i.e., at the bond pad308). It is to be understood that other portions of the die300can include additional materials, structures, devices and components. For example, the die300can include doped semiconductor materials, active regions, and/or a variety of other materials and structures known in the art.

FIG. 3Bis a partially schematic, enlarged, cross-sectional view of a portion of the bond pad308and the bond pad surface310ofFIG. 3B. The surface310includes a scrub mark312having crevices or depressions314and a brow or furrow316. As used herein, the term brow or furrow can refer to any portion of a surface forming an overhanging feature. The crevices314and the brow or furrow316define openings, recesses or voids318in the bond pad308. In several embodiments, the scrub mark312can extend across a minority of the bonding surface310(i.e., the scrub mark can occupy an area that is less than half of the total area of the bonding surface310).

FIG. 4Ais a partially schematic, cross-sectional view of the die300and a passivation material402configured in accordance with an embodiment of the present technology. As described in more detail below, the passivation material402can be an oxidation material that is formed via immersion of the die300and an associated wafer in a chemical solution.FIG. 4Bis a partially schematic, enlarged cross-sectional view of a portion of the bond pad308and the passivation material402. As shown inFIG. 4B, the passivation material402covers the surface310of the bond pad308and fills the voids318.

FIG. 5Ais a partially schematic, cross-sectional view of the die300after portions of the passivation material402have been removed in accordance with an embodiment of the present technology.FIG. 5Bis a partially schematic, enlarged cross-sectional view of a portion of the bond pad308after the portions of the passivation material402have been removed. The portions of the passivation material402can be removed via various semiconductor fabrication techniques, including etching and/or other suitable removal methods. For example, the portions of the passivation material402can be removed via plasma etching with, e.g., argon. After the removal of the portions of the passivation material402, several other portions of the passivation material402remain. In particular, portions of the passivation material402remain in the voids318defined by the crevices314and the brow316. These features in effect at least partially “protect” portions of the passivation material402within the voids318such that the removal process does not remove all of the passivation material402. The voids318each contain a corresponding discrete portion404of the passivation material402that can at least partially fill their corresponding voids318. For example, as shown inFIG. 5B, one of the discrete portions404at least partially underfills the brow316. In several embodiments, removal of the portions of the passivation material402removes all of the passivation material outside of the portion of the surface310that includes the scrub mark312.

FIG. 6Ais a partially schematic, cross-sectional view of a portion of the die300after the addition of a conductive structure502in accordance with an embodiment of the present technology. In the illustrated embodiment, the conductive structure502includes an adhesive material504and a seed material506that can be added to the die300via physical vapor deposition (PVD). In some embodiments, the adhesive material504is titanium and the seed material506is copper. In other embodiments, the conductive structure502can include more or fewer materials, including materials other than titanium or copper (e.g., titanium nitride, titanium tungsten, tantalum, etc.). The adhesive material504can be added to the die300directly adjacent to the bond pad308, encasing the scrub mark312and forming a secure bond to the bond pad308. The seed material506can be formed on, and bonded to, the adhesive material504. In the illustrated embodiment, the adhesive material504and the seed material506, together, form the conductive structure502, which is securely bonded to the bond pad308.

FIG. 6Bis a partially schematic, enlarged cross-sectional view of a portion of the bond pad308after the addition of the conductive structure502. As shown inFIG. 6B, the adhesive material504is in direct contact with the surface310across a majority of the bond pad308. Specifically, the only portions of the surface310that are not in contact with the adhesive material504are those portions of the surface310at the location of the voids318(which are occupied by the discrete portions404of the passivation material402). Although the portions404of the passivation material402can be dielectric and can potentially increase the resistance between the conductive structure502and the bond pad308, the total amount of contact between the portions404of the passivation material402and the adhesive material504constitutes a relatively minor amount in comparison to the amount of contact between the surface310and the adhesive material504(e.g., less than one percent). Accordingly, the conductive adhesive material504forms a strong electrical connection with the bond pad308.

FIGS. 7A and 7Bare partially schematic, isometric and cross-sectional views, respectively, of the die300after the addition of a conductive interconnect or pillar702configured in accordance with an embodiment of the present technology. The pillar702can be added to the die300via one or more semiconductor fabrication techniques (e.g., plating and reflow). In the illustrated embodiment, the pillar702is attached to the bond pad308via the conductive structure502. Specifically, the pillar702extends from the seed material506at a location that is above and overlies the scrub mark312. More particularly, the pillar702includes a base704, and the pillar702is positioned such that a footprint of the pillar702overlies the scrub mark312. That is, a projection of the base704onto the bond pad308defines an area having a perimeter that surrounds or encircles the scrub mark312. In several embodiments, the pillar702and the seed material506can be copper, and a reflow process can join the pillar702and the seed material506into a continuous material (as illustrated inFIG. 7A).

FIGS. 8A and 8Bare partially cross-sectional, and cross-sectional FIB-SEM images, respectively, of a wafer800configured in accordance with an embodiment of the present technology and illustrating several of the features discussed above with respect toFIGS. 3A to 7B.FIG. 8A, for example, is an SEM at 1000× magnification, showing the wafer800, a die802, a bond pad804, a pillar806, and a bond808between the pillar806and the bond pad804.FIG. 8Bis an SEM at 15000× magnification showing the bond808, a scrub mark810, and an adhesive material812. As shown, the scrub mark810includes several interruptions in a surface814of the bond pad804. For example, the scrub mark810has caused a noncontiguous region816in the adhesive material. Notably, however, the bond808does not exhibit any corrosion, and the bond pad804has no voids. Rather, passivation material (not visible inFIGS. 8A and 8B) has filled any voids in the surface814, and reduced or prevented the opportunity for corrosion to occur at the bond808.

FIG. 9is a partially schematic, cross-sectional view of a portion of a semiconductor device assembly900configured in accordance with an embodiment of the present technology. In the illustrated embodiment, the device assembly900includes the die300and a die902in a vertically stacked configuration. It is to be understood, however, that device assemblies configured in accordance with the present technology can include many more dies (e.g., 4, 8, or more dies in one or more stacks and/or in other configurations). The dies300and902are stacked on a controller904and are electrically connected to one another via a plurality of pillars906. The die902can be substantially similar to the die300described above with reference toFIGS. 3-7, and the pillars906can be bonded to bond pads in the corresponding dies300and902.

In several embodiments, the bond pads308and804discussed above with reference toFIGS. 3A to 8can be aluminum bond pads. To produce the passivation material402, a wafer having exposed aluminum bond pads can be immersed in a chemical solution that includes tetramethylammonium hydroxide (TMAH), silicon, and ammonium persulfate. In particular, the inventors have discovered that solutions having various ratios of these chemicals can create the passivation material402via chemical reactions between these chemicals and the aluminum in the bond pads308and804. Several of the chemical reactions associated with formation of the passivation material402follow:

B. Formation of aluminum oxide via ammonium persulfate and aluminum:1. (NH4)2S2O8→2NH4++S2082−2. 2Al+3S2O82−+3H2O→Al2O3+6SO42−+6H+

As can be seen in reactions A1 to A3, the TMAH produces a basic solution that can react with the silicon to produce silicon dioxide. The silicon dioxide can form a portion of the passivation material402. Additionally, as shown in reactions B1 and B2, the ammonium persulfate can dissolve the aluminum bond pads to produce aluminum oxide. The aluminum oxide also forms a portion of the passivation material.

The inventors conducted extensive experiments that included the preparation and testing of a variety of solutions having differing chemical ratios. These experiments were designed to determine preferred chemical ratios to generate thicker formations of the passivation material402. In one such experiment, the inventors compared two differing chemical solutions configured in accordance with embodiments of the present technology, referred to herein as composition 1 and composition 2. Compositions 1 and 2 included the following mass/volume chemical percentages:

After preparing compositions 1 and 2 in accordance with the table above, the compositions were agitated and a first portion of each composition was subsequently heated to 60 degrees Celsius, and a second portion of each composition was heated to 70 degrees Celsius. Semiconductor wafers having die with exposed aluminum bond pads (e.g., the die300with the bond pads308) were then submerged in the various solutions for either 5 minutes or 10 minutes to form a passivation material (e.g., passivation material402) having aluminum oxide material and silicon oxide material. After removal from the solutions, the wafers were analyzed via X-ray photoelectron spectroscopy (XPS) to determine the thickness of the aluminum oxide (AlOx) material and the thickness of the silicon oxide (SiOx) material.

FIG. 10Ais a graph illustrating a thickness of an aluminum oxide material formed on wafers treated with differing compositions, differing temperatures, and for differing durations. As can be seen inFIG. 10A, composition 2 provides a thicker coverage of aluminum oxide.FIG. 10Bis a graph illustrating a thickness of a silicon oxide material formed on wafers treated with differing compositions, differing temperatures, and for differing durations. As shown inFIG. 10B, composition 2 also provides a thicker coverage of silicon oxide.

In addition to measurements of the thickness of aluminum oxide coverage and silicon oxide coverage for the tested wafers, XPS sputter depth profiling was performed to determine atomic concentrations.FIG. 11is a graph illustrating atomic concentration percentages for various elements as a function of depth. Specifically,FIG. 11illustrates atomic concentrations of elements in a passivation material formed on a wafer treated with composition 2 at 70 degrees Celcius for 8 minutes. As shown, the treatment produced a passivation material having continuous coverage of aluminum, silicon, and oxygen to a depth of approximately 10 nm (100 Å).

FIG. 12is a graph illustrating ratios of silicon to aluminum within passivation materials formed on wafers treated with differing compositions, differing temperatures, and for differing durations. The ratios shown in the graph ofFIG. 12were measured using time of flight secondary ion mass spectrometry (TOF-SIMS). As shown, the oxide passivation material that was analyzed includes silicon and aluminum, and composition 2 produced significantly higher ratios of silicon to aluminum than composition 1.

The formation of passivation materials configured in accordance with embodiments of the present technology can include providing sufficient silicon in a solution to reduce or prevent any significant etching of aluminum (e.g., the aluminum bond pads308and,804). Specifically, absent an adequate concentration of silicon, solutions having TMAH can produce significant etching of exposed aluminum bond pads. In some embodiments, silicon is added to an 8% mass/volume solution of TMAH to produce a mass/volume silicon concentration of at least 3%. In such embodiments, the etching of the aluminum bond pads is significantly reduced.

In several embodiments, a temperature of a solution or composition is maintained at or below 80 degrees Celcius to ensure adequate dissolution of silicon. Specifically, above 80 degrees Celcius, TMAH can rapidly disassociate, preventing the dissolution of silicon. However, as the silicon concentration increases, the dissolution rate of silicon decreases. To continue dissolving silicon to reach the desired concentration (e.g., 3% mass/volume), the temperature can be maintained at or above 60 degrees Celcius.

The formation of aluminum oxides via the processes and methods described herein can include a concurrent decrease in the mass/volume percentage of TMAH in a corresponding composition. Specifically, the TMAH can disassociate as part of the chemical process that forms the aluminum oxides. In several embodiments, the TMAH that is consumed in the chemical reactions can be replaced to maintain a relatively constant mass/volume percentage. Specifically, TMAH can be added to a composition (while wafers are immersed therein) to maintain a mass/volume percentage of TMAH at a desired value (e.g., 8%).

Passivation materials formed in accordance with embodiments of the present technology can exhibit several desirable characteristics. For example, although naturally occurring passivation materials can provide some protection from corrosion, these materials are generally too thin (often less than 1 nm) and are stripped away during various fabrication steps (e.g., etching, process chemicals, etc.). Embodiments configured in accordance with the present technology can include passivation material having thicknesses of 3 to 4 nm, or thicker. The thicker passivation material ensures that at least some will remain, particularly at the jagged and irregular surface features associated with probe scrub marks or other process artifacts. The remaining passivation material can protect against corrosion in the manner discussed above, providing for lower resistance electrical connections and more secure and robust bonds between materials and components.

Additionally, passivation materials configured in accordance with the present technology can include both aluminum oxides and silicon oxides. In several embodiments, a ratio of aluminum to silicon in the passivation material can be approximately 3 to 1. In other embodiments, this ratio can be higher or lower than 3 to 1. The aluminum oxides and silicon oxides can be in separate layers within a passivation material or passivation structure, and/or they can be intermixed within one or more layers (e.g., aluminum oxides and silicon oxides intermixed within a layer that is positioned between a monolayer of aluminum oxides and a monolayer of silicon oxides). Regardless of the distribution of the aluminum oxides and silicon oxides, the inclusion of both of these materials in the embodiments disclosed herein can provide significant advantages over a natural passivation material having only aluminum oxide. Specifically, passivation material having both aluminum oxide and silicon oxide has been shown to be significantly less susceptible to corrosion from process chemicals (e.g., TMAH).

Although in the foregoing embodiments, the use of a passivation material to remediate probe scrub mark process artifacts has been described, the present technology has application to other process artifacts or irregular surface features. For example, any discontinuous barrier film (e.g., at the edge of a bond pad opening) can benefit from the mitigation of corrosion, damage, etc. of underlying films using a passivation material as set forth in greater detail in the examples above. Moreover, other surface features having non-planar or non-continuous shapes can similarly benefit (e.g., where barrier films are difficult to dispose due to step coverage limitations).

From the foregoing, it will be appreciated that specific embodiments of the technology have been described herein for purposes of illustration, but that various modifications may be made without deviating from the disclosure. For example, in addition to or in place of the conductive structure502and the pillar702, other materials and components can be bonded to bond pads having discretely located passivation material. In addition, certain aspects of the new technology described in the context of particular embodiments may also be combined or eliminated in other embodiments. Moreover, although advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments need necessarily exhibit such advantages to fall within the scope of the technology. Accordingly, the disclosure and associated technology can encompass other embodiments not expressly shown or described herein.