Liquid crystal display pixel with a capacitive compensating transistor for driving transistor

An active matrix thin film transistor liquid crystal display having two thin film transistors for use in driving each of the liquid crystal pixels making up the matrix of the display. The first thin film transistor associated with each pixel is used in driving the pixel to capture data off of data lines in response to gate drive signals. The second thin film transistor associated with each pixel is used in compensating for the parasitic capacitances associated with the first thin film transistor and is driven by special compensating pulses.

BACKGROUND OF THE INVENTION 
The present invention relates to liquid crystal displays and more 
particularly to systems for use in correcting for image retention and 
flicker problems exhibited by typical active matrix liquid crystal 
displays. 
In most active matrix liquid crystal displays the data signals applied to 
the individual liquid crystal pixels are subject to distortion resulting 
from the gate-source capacitances which are characteristic of the thin 
filled transistors used in driving such pixels and the capacitances 
exhibited by the pixels themselves. As shown in FIG. 1, gate drive pulses 
10 of amplitude V.sub.G are periodically applied to the scanning or select 
lines of a display matrix in order to enable data signals 12 of either 
positive or negative polarity to be applied to the pixel electrodes of the 
liquid crystal pixels in the matrix. However, the gate-source capacitances 
of the thin film transistors driving the pixels affect the waveform of the 
pixel drive signal 14 as charge is diverted at the falling edges of the 
gate drive pulses to satisfy the capacitance requirements of the 
gate-source junctions of the thin film transistors resulting in a voltage 
distortion .DELTA.V in the voltage level at the pixel electrodes. The 
voltage distortion .DELTA.V constitutes a DC offset having longer term 
effects on the liquid crystal pixels and resulting in significantly 
degraded image quality due to image retention and flicker. 
In accordance with past practices for correcting this problem small DC bias 
voltages have been applied across liquid crystal display matrixes in an 
attempt to compensate for the voltage distortion .DELTA.V. However, this 
technique has not proven entirely satisfactory since the amount of voltage 
distortion exhibited by each pixel is a function of the construction of 
the individual liquid crystal pixels and more importantly is a non-linear 
function of the data signal voltage level. Consequently, in active matrix 
liquid crystal displays in which data voltages are controlled to provide a 
gray scale for use in furnishing enhanced images, the bias voltage to be 
applied across the matrix for compensating for the voltage distortion due 
to the inherent parasitic capacitances can only be approximated to an 
average level resulting in continued image retention and flicker problems. 
It is therefore an object of the present invention to provide a system for 
eliminating image retention and flicker problems in active matrix liquid 
crystal displays. 
It is another object of the present invention to provide a construction for 
a liquid crystal display matrix including devices and methods for 
accurately compensating on a pixel-by-pixel basis for the parasitic 
gate-source capacitances of the thin film transistors used in driving the 
liquid crystal pixels in the matrix. 
It is a further object of the present invention to provide a system for 
suppressing image retention and flicker problems in active matrix liquid 
crystal displays which is simple in operation and can be readily 
implemented into a liquid crystal matrix designs at minimum expense and 
with a minimum of effort. 
SUMMARY OF THE INVENTION 
The present invention constitutes an improvement to the pixel modules used 
in active matrix thin film transistor liquid crystal displays having a 
plurality of pixel modules positioned with reference to (n-1)th and (n)th 
scanning lines which bracket said pixels in a display matrix and wherein 
gate drive signals are sequentially applied to the scanning lines. The 
pixel module of the present invention includes a liquid crystal pixel 
having a pixel electrode, a first thin film transistor for driving said 
pixel and a second thin film transistor for compensating for parasitic 
capacitances. The first thin film transistor is located in proximity to 
said pixel and has its gate connected to (n)th scanning line and its drain 
connected to said pixel electrode. The second thin film transistor is also 
located in proximity to said pixel and has its gate connected to the 
(n-1)th scanning line and its drain and source interconnected with the 
pixel electrode. Gate drive signals are applied to the scanning lines 
which include drive pulses and compensating pulses of opposite polarity 
for operating the first thin film transistor to capture data to the liquid 
crystal pixel and operating the second thin film transistor for 
compensating for the parasitic capacitances inherent in the first thin 
film transistor as well as the liquid crystal pixel. The compensating 
pulses are applied to the (n-1)th scanning line and are timed to overlap 
and follow the drive pulses applied to the (n)th scanning line. 
In operation, the charges accumulated due to the parasitic capacitances of 
the second thin film transistors counteract and offset the charges 
required to satisfy the parasitic capacitances of the first thin film 
transistors at the falling edges of the drive pulses. In the preferred 
embodiment, the second thin film transistors are constructed to have 
parasitic capacitances approximately four times the capacitances 
characteristic of the first thin film transistors and the compensating 
pulses are configured to have amplitudes approximately one quarter the 
amplitudes of the drive pulses.

DESCRIPTION FOR THE PREFERRED EMBODIMENT 
Referring now to FIG. 2, a liquid crystal display matrix 20 includes 
individual pixel modules as represented by the module 22 which are 
positioned in between scanning lines 26 and 28 adapted for carrying gate 
drive signals to the pixel modules and data lines 30 and 32 adapted for 
delivering data signals to the pixel modules. The pixel modules are all 
similarly constructed including a liquid crystal pixel 34, a first thin 
film transistor 36 and a second thin film transistor 38. The liquid 
crystal pixel 34 includes a pixel electrode 40 and a counter electrode 42 
which represents a common terminal between all of the pixel modules in the 
matrix 20. 
The thin film transistor 36 includes a gate 44 connected to the scanning 
line 26 for receiving a gate drive signal S.sub.N, a source 46 connected 
to the data line 30 for receiving a data signal D.sub.N and a drain 48 
connected to the pixel electrode 40. The thin film transistor 36 exhibits 
a characteristic capacitance between its gate and source C.sub.GS (or its 
gate and drain) as indicated by the phantom capacitor 50. 
The thin film transistor 38 includes a gate 52 connected to the scanning 
line 28 for receiving a gate drive signal S.sub.N-1 and has its source 54 
interconnected to its drain 56 which is in turn connected to the pixel 
electrode 40. The thin film transistor 38 is constructed to have a 
characteristic capacitance between its gate and its drain and source of 
approximately 4 C.sub.GS as indicated by the phantom capacitor 60. 
Referring now to FIG. 3, the waveforms 70, 72 and 74 correspond to the data 
signal D.sub.N applied on the line 30 and the gate drive signals S.sub.N-1 
and S.sub.N applied on the lines 28 and 26. The data signal D.sub.N 
includes a typical data pulse 80 which extends from time t.sub.2 to time 
t.sub.3. The gate drive signal S.sub.N includes a drive pulse 82 extending 
between times t.sub.0 to t.sub.2 for capturing whatever data may be 
furnished by the signal D.sub.N and applying the same to the pixel 34. 
However, the gate drive signals also include compensating pulses which 
effect the operation of the pixel modules connected to the next succeeding 
scanning line. For instance, the compensating pulse 84 of the gate drive 
signal S.sub.N-1 which extends between times t.sub.1 and t.sub.3 effects 
the operation of the pixel module 22 which is otherwise controlled by the 
signal S.sub.N on line 26. 
In operation, the drive signal S.sub.N applied to line 26 operates on the 
transistor 36 to "latch" data provided by the data signal D.sub.N off of 
the line 30 between times t.sub.1 and t.sub.2 and apply the same to the 
pixel electrode 40. However, at the falling edge of the drive pulse 82, 
the operation of the pixel module 22 may be affected by parasitic 
capacitances such as and primarily the gate-source capacitance C.sub.GS of 
the thin film transistor 36. The operation of the thin film transistor 38 
compensates for this capacitance in accordance with the effects of the 
compensating pulse 84. Since the compensating pulse 84 is of opposite 
polarity from the drive pulse 82, the charge accumulated by the combined 
gate-source and gate-drain capacitance of the thin film transistor 38 is 
of opposite polarity from the charge required to satisfy the gate-source 
capacitance of the thin film transistor 36 at the falling edge of the 
drive pulse 82. Further, since the combined gate-source and the gate-drain 
capacitance of the thin film transistor 38 is approximately four times the 
gate-source capacitance of the thin film transistor 36 and since the 
compensating pulse 38 is configured to have an amplitude V.sub.X which is 
approximately one-quarter the amplitude of the drive pulse V.sub.G, the 
charge drawn off by the gate source capacitance of the transistor 36 is 
approximately equal to the charge available and supplied by the combined 
gate-source and the gate-drain capacitance of the transistor 38. 
Consequently, the voltage level applied to the pixel electrode 40 in 
accordance with the data signal D.sub.N remains substantially constant 
despite the fall in gate drive voltage supplied by the signal S.sub.N. 
Referring now to FIG. 4, the physical configuration of the liquid crystal 
display matrix 20 and the pixel module 22 in relation to the film 
transistors 36 and 38 is more accurately shown. The thin film transistor 
36 is positioned in one corner of the pixel module 22 in proximity to both 
the scanning line 26 carrying the drive signal S.sub.N and the data line 
30 carrying the data signal D.sub.N. The thin film transistor 38 is 
located in proximity to the scanning line 28 carrying the drive signal 
S.sub.N-1. The source 54 and drain 56 of the transistor 38 and the drain 
48 of the transistor 36 are all interconnected by the transparent 
Indium-Tin-Oxide layer of the pixel 34. 
Referring now to FIGS. 5A and 5B, typical constructions are shown for the 
thin film transistors 36 and 38, respectively. Both of the thin film 
transistors 36 and 38 are formed on a glass substrate 86 and have 
configurations which may be characterized as inverted-staggered 
structures. Both of the transistors 36 and 38 include gates 44 and 52 
constructed of MoTa and sources 46 and 54 and drains 48 and 56 constructed 
of Mo. The gates 44 and 52 are overlaid by a layer 88 of gate insulator 
material such as SiOx. A layer 90 of undoped amorphous silicon a-Si(i) and 
a layer 92 of doped amorphous silicon a-Si(n.sup.+) extend between the 
gates 44 and 52 and the sources and drains 46, 48, 54 and 56. A 
passivation layer 94 of silicon nitride SiNx overlays the structures of 
both of the transistors 36 and 38. In the thin film transistor 36 the 
source 46 is connected directly to the Indium-Tin-Oxide (ITO) layer 96 of 
the pixel 34 while in the thin film transistor 38 both the source 54 and 
the drain 56 are connected directly to the conductive Indium-Tin-Oxide 
layer 96 of the pixel 34.