TWISTED DIFFERENTIAL COMPENSATION FOR ROUTING HIGH-SPEED SIGNALS NEAR POWER DELIVERY INDUCTORS AND SYSTEM MINIATURIZATION

Apparatus and methods employing twisted differential compensation for routing high-speed signals near power delivery inductors. Traces used for a high-speed differential signal including a P trace and an N trace are routed through one or more layers in a multi-layer printed circuit board (PCB) substrate and employ a twisted portion proximate to the centerline of an inductor under which portions of the P and N traces are swapped horizontally in a layer parallel to the top plane and/or are swapped vertically by swapping layers. The signal paths are routed such that a level of noise inductively coupled into the P trace and the N trace from the inductor is approximately equally. Stripline structures may be used for signals that are routed under an inductor, while stripline and microstrip structures may be used for signals routed adjacent to an inductor.

BACKGROUND INFORMATION

Market trends are leading to small sized and thin, high performance computer systems in a variety of form factors. The physical size of these systems requires that high-current power delivery components, such as inductors, be placed near high-speed data buses.

High current flowing through the inductors generates large amounts of magnetic noise that couple onto the high-speed buses and cause functional failures. This magnetic noise cannot be effectively shielded by copper planes. This necessitates a large keep out zone (KOZ) surrounding the inductors (8-13 mm) in X/Y dimensions, which limits routing lanes. This can significantly increase board area and/or increase layer count, leading to larger z-heights and higher costs. The large KOZ is applicable to both single ended (e.g., DDR, GDDR) and differential (PCIe (Peripheral Component Interconnect Express), USB (Universal Serial Bus), display) buses.

An example of the KOZ is depicted inFIG. 1. As show, when current flows through the coils in spiral inductor100, a magnetic field is generated. Under the SI system, the unit of inductance is the henry (H), and thus the magnetic field is labeled ‘H’ field inFIG. 1. The inductance of the magnetic field is stronger closest to the inductor, and also varies with the current flow and direction. For example, for a sinusoidal alternating current (AC) the strength of the magnetic field will likewise be sinusoidal.

Spiral inductor100is mounted to a printed circuit board (PCB)102including a top plane (such as a copper ground plane) and circuit traces104in one or more inner layers below the top plane in the PCB. The magnetic “noise” produced by the inductor is inductively coupled into circuit traces104. The level of inductive coupling may adversely alter signals within the KOZ (less so outside of the KOZ), resulting in signal quality failing to meet requirements defined by applicable standards (such as for communication signals like PCIe).

DETAILED DESCRIPTION

Embodiments of apparatus and methods employing twisted differential compensation for routing high-speed signals near power delivery inductors are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

For clarity, individual components in the Figures herein may also be referred to by their labels in the Figures, rather than by a particular reference number. Additionally, reference numbers referring to a particular type of component (as opposed to a particular component) may be shown with a reference number followed by “(typ)” meaning “typical.” It will be understood that the configuration of these components will be typical of similar components that may exist but are not shown in the drawing Figures for simplicity and clarity or otherwise similar components that are not labeled with separate reference numbers. Conversely, “(typ)” is not to be construed as meaning the component, element, etc. is typically used for its disclosed function, implement, purpose, etc.

In accordance with aspects of the embodiments disclosed herein, apparatus and methods are provided that allow high-speed differential signals to be routed significantly closer to (or under) power delivery inductors. This, in turn, permits the size of small form factor systems to be reduced. In one aspect, the embodiments utilize vias to make the differential signals “twisted” proximate to the midpoint of an inductor footprint. The technique can be extended to multiple differential pair routed in parallel, where the twisting occurs proximate to a centerline of the inductor that is perpendicular to the routing traces.

The embodiments provide several advantages. For example, they allow differential high-speed stripline signals to be routed underneath inductors. They also allow microstrip differential pairs to be routed significantly closer to inductors. This enables small form factor compute devices and systems to be implemented with a smaller motherboard (or other PCB) with a lower layer count that is not possible with current design practices.

As described and illustrated herein, the techniques may be applied to both differential stripline signals and microstrip differential pairs. A stripline is sometimes compared to a flattened coaxial cable in that, like the cable, it consists of an inner conductor surrounded by dielectric material which is further surrounded by a ground braid or foil. However, stripline circuits are planar, so that they appear as a sandwich of conductors in the middle, surrounded by dielectric layers, which in turn have parallel ground planes on the top and bottom. Microstrip is a transmission-line format in which the conductor is fabricated on a dielectric substrate which itself has a bottom ground-plane layer. Conductors are usually formed by etching away unwanted metal from a conductor layer, such as copper. As a variant of a microstrip structure is an embedded microstrip, which has another layer of dielectric above the microstrip traces.

For differential signals, two stripline structures may be used. Under an edge-coupled stripline structure, the traces for a pair of differential signals are in the same layer. Under a broad-side stripline structure, the traces for the pair of signals are stacked on top of each other in respective routing layers separated by a dialect layer.

Differential signaling is very effective for removing common mode noise. For example, assume that noise with a magnitude of vnoiseis coupled equally onto both legs of a differential pair (P and N). The output of a differential amplifier with unity gain is shown by (1), which removes the common mode noise.

Because the magnitude of the magnetic field induced by transient current flowing through an inductor falls off quickly, the half of the differential pair in closer proximity to the inductor will see more inductively coupled noise. For example, as shown under the current approach inFIG. 2a, the P half of the conventional differential pair will see more noise compared to the N side. This results in a differential noise, vdiff_noise, that depends on the proximity of the routing, inductor type and current profile as shown in equation (2), where vdiff_noise=vnoiseP−vnoiseN.

Note that vdiff_noisecan be as high as 10 mV per inductor, which is larger than the minimum eye height requirements of the PCIe 4, 5 and 6 specifications.

Under the novel approach provided by the embodiments disclosed herein, a “twist” is introduced in the differential pair by swapping the P and N traces near the centerline of the inductor so that the total coupled noise on each half of the differential pair is approximately equal. A high-level illustration of this approach is shown inFIG. 2b. In this example, (as withFIG. 2a, the relation of the traces can be considered in two different ways. For example, consider theFIG. 2arepresents a cross-section view of an inductor mounted on a PCB using a broad-side stripline structure, where Trace_p begins (from left-to-right) in a PCB layer above Trace_n and they are swapped near the centerline of the inductor such that Trace_n is now in the upper layer and Trace_p is in the lower layer. Alternatively,FIG. 2bshows a plan (top) view of an inductor with Trace_p and Trace_n in the same layer, where the horizontal distance relative to a horizontal line passing through the center of the inductor is swapped near the centerline.

The result of the differential noise using the approach shown inFIG. 2bis shown in equation (3), where the non-primed and the primed variables denote the coupled noise before and after the twist respectively.

If the twist is introduced near the centerline of the inductor, then vnoiseP≈vnoiseP′ and vnoiseN≈vnoiseN′, reducing (3) to (4), resulting in the elimination of the differential magnetic noise coupled from the inductor to the differential pair:

FIG. 3shows a PCB assembly300illustrating an abstracted view of an example of twisting applied to differential signal traces implemented in the same plane. PCB assembly300includes an inductor302mounted to (or otherwise disposed over) a PCB304shown in plan (top) view, with inductor302outlined in phantom lines and having a vertical (Y-axis) centerline306. The central axis of inductor302would be substantially perpendicular to the top plane of PCB304(and the page) and pass through it. PCB assembly300includes two sets of differential pair signal traces308and310, which may be implemented using microstrips (for differential pair signal traces310) or striplines (for either of differential pair signal traces308and310) in alternative embodiments.

Differential pair signal traces308includes a P trace312and an N trace314. P trace312includes a first leg316coupled to a second leg318using a cross-over segment320and vias322and324. N trace314includes a first leg326coupled to a second leg328using a cross-over segment330and vias332and334. In this illustrative example, the legs of P trace312and N trace314are implemented in layer 3 (L3), and at least a portion of a cross-over segment comprises a trace in layer 5 (L5). The term “cross-over” is used to describe a trace segment that crosses over between P legs or crosses over between N legs. Under a physical system, such as illustrated inFIGS. 4a-4cbelow, one of the two cross-over segments will cross under the other cross-over segment.

In PCB assembly300, differential pair signal traces308pass under inductor302, while differential pair signal traces310are offset horizontally (in L3) from differential pair signal traces308and do not pass under inductor302. The crossover (twisting) of the P and N traces occurs proximate to inductor centerline306. Differential pair signal traces310are adjacent to the footprint of inductor302. Differential pair signal traces310has a similar configuration as differential pair signal traces308, except that the legs in signal traces310may be implemented on either layer 1 (L1) when using microstrips or L3 when using striplines. The spacing between the pairs of P and N traces, width of the traces, and size of the vias is exaggerated for clarity. Three-dimensional (3D) views showing further details of an exemplary trace and via routing structures to effect twisting of the P and N traces are shown inFIGS. 4band4c.

FIG. 4ashows a PCB assembly400illustrating an example of a physical implementation employing twisting applied to differential signal traces deposited in the same plane. PCB assembly400includes an inductor402mounted to (or otherwise disposed over) a PCB404shown in plan (top) view, with inductor402outlined in phantom lines and having a vertical (Y-axis) centerline406. PCB assembly400includes a set of differential pair signal traces408, which may be implemented using striplines. Differential pair signal traces408includes a P trace412and an N trace414. P trace412includes a first leg416coupled to a second leg418using a cross-over segment420and vias422and424. N trace414includes a first leg426coupled to lower layer segment428at a via430. Lower layer segment428is coupled to a cross-over segment432at a via434that is part of a second leg436. In this illustrative example, the legs of P trace412and N trace414are implemented in layer 3 (L3), and cross-over segment comprises a stripline trace in layer 5 (L5). Lower layer segment428is also implemented in L3.

FIG. 4bshows a 3D view of PCB assembly400, with the addition of a second differential pair of P and N signal traces450, which have similar structure to differential pair signal traces408. Inductor402is mounted to PCB404at mounts452and454.FIG. 4cshows a 3D view of the crossover portions of differential pair signal traces408and450(toward the rear with unlabeled structural elements).

As shown inFIG. 4c(and also shown inFIG. 4a), the cross-over segment432of the N signal is implemented in L3, while the cross-over segment420of the P trace is implemented in L5. On initial review, lower leg segment428would appear unnecessary, as cross-over segment432and N trace leg426are both in L3. However, this would result in a shorter path for the N signal than the P signal. It would also expose the N signal path to different inductive coupling than the P signal path and the signal paths might have slightly different impedance. Thus, both the signal paths for the P and N signals include a pair of vias and a trace segment that is implemented in L5, as shown inFIGS. 4aand4c.

It is noted that a microstrip circuit structure similar to that shown inFIGS. 4a-4cmay be implemented in layers L1 and L3 for differential signals that are routed adjacent to an inductor rather than under the inductor. For an embedded microstrip structure, layer L2 and L4 may be used.

In addition to routing differential signals in the same plane (having legs in the same PCB layer), differential signals may be routed using traces in different layers. For example,FIG. 5shows an elevation (side) view of a PCB assembly500illustrating an abstracted view of an example of twisting applied to differential signal traces implemented in different layers. PCB assembly500includes an inductor502mounted to (or otherwise disposed over) a PCB504, with inductor502outlined in phantom lines and having a central axis506. When the view would be rotated to a plan view, centerline of inductor302would be perpendicular to central axis506. The central axis of inductor302would be substantially perpendicular to the top plane of PCB304and pass through it (not shown).

PCB assembly500includes a differential pair or signal traces508, which may be implemented using striplines in the illustrated embodiment. Differential pair signal traces508includes a P trace512and an N trace514. P trace512includes a first leg516coupled to a second leg518using a cross-over segment520and a via522. N trace514includes a first leg524coupled to a second leg526using a cross-over segment528and a vias530. In this illustrative example, the P trace leg516and N trace leg are implemented in layer L3 while N trace leg524and P trace leg518are implemented in Layer L5.526of P trace512and N trace514are implemented in layer 3 (L3). Vias522and530are used to route signal paths between layers L3 and L5.

The signal paths for the differential pair of P and N signals may also be twisted such that their distance from the inductor is swapped in the horizontal plane (not shown). The objective, as before, is for the level of noise inductively coupled into the signal paths for the P and N signals to be the same.

FIG. 6shows an example compute device600in which high-speed differential signals are routed using twisting. Compute device600includes a multilayer PCB602to which hardware components are mounted and having traces and vias for providing power planes and for signal routing. The hardware components include a processor604, memory606, power supply circuitry including an inductor610, a USB-C port612, a network controller614, and a network port616. Processor604includes a USB-C interface (I/F)618that is coupled to USB-C port612via differential signal pair traces620, which are routed adjacent to the footprint of inductor610. Processor604also includes a PCIe root port622that is coupled to network controller614via differential signal pair traces620, which are routed under inductor610. As shown in the blow-up of the portion including inductor610at the top ofFIG. 7, differential signal pair traces620and624employ a twist structure that is similar to that shown inFIGS. 4aand4c.

FIGS. 7aand 7bshows signal noise graphs for P and N signals using a conventional approach and with twisting. As shown under the conventional approach inFIG. 7a, the N signal path is routed closer to the inductor than the P signal path. As a result, the level of inductively coupled noise for the N signal is significantly greater than for the P signal. By comparison, the difference in the level of inductively coupled noise for the P and N signals using the twisting approach is substantially reduced, as shown inFIG. 7b.

While the techniques disclosed and illustrated herein may be applied to various systems and devices, they are particularly well-suited for thin and small form factor compute devices. By enabling high-speed signals to be routed under inductors and/or proximate to inductors, the size of such systems and devices may be reduced.

In the description and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. Additionally, “communicatively coupled” means that two or more elements that may or may not be in direct contact with each other, are enabled to communicate with each other. For example, if component A is connected to component B, which in turn is connected to component C, component A may be communicatively coupled to component C using component B as an intermediary component.

As used herein, a list of items joined by the term “at least one of” can mean any combination of the listed terms. For example, the phrase “at least one of A, B or C” can mean A; B; C; A and B; A and C; B and C; or A, B and C.