STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH EPITAXIAL STRUCTURES

A method for forming a semiconductor device structure includes forming a fin structure, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack wrapped around the fin structure and forming a spacer layer extending along sidewalls of the fin structure and the gate stack. The method further includes partially removing the fin structure and the spacer layer to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers. A remaining portion of the spacer layer forms a gate spacer. In addition, the method includes forming an inner spacer layer along a sidewall and a bottom of the recess and partially removing the inner spacer layer using an isotropic etching process. Remaining portions of the inner spacer layers form multiple inner spacers. The method includes forming an epitaxial structure in the recess.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation.

However, these advances have increased the complexity of processing and manufacturing ICs. Since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes.

DETAILED DESCRIPTION

The term “substantially” in the description, such as in “substantially flat” or in “substantially coplanar”, etc., will be understood by the person skilled in the art. In some embodiments the adjective substantially may be removed. Where applicable, the term “substantially” may also include embodiments with “entirely”, “completely”, “all”, etc. Where applicable, the term “substantially” may also relate to 90% or higher, such as 95% or higher, especially 99% or higher, including 100% of what is specified. Furthermore, terms such as “substantially parallel” or “substantially perpendicular” are to be interpreted as not to exclude insignificant deviation from the specified arrangement and may include for example deviations of up to 10 degrees in some embodiments. The word “substantially” does not exclude “completely” e.g. a composition which is “substantially free” from Y may be completely free from Y in some embodiments.

Terms such as “about” in conjunction with a specific distance or size are to be interpreted so as not to exclude insignificant deviation from the specified distance or size and may include for example deviations of up to 10% of what is specified in some embodiments. The term “about” in relation to a numerical value x may mean x±5 or 10% of what is specified in some embodiments.

Embodiments of the disclosure may relate to the gate all around (GAA) transistor structures. The GAA structure may be patterned using any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. In some embodiments, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in some embodiments, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure.

FIGS.1A-1Bare top views of various stages of a process for forming a portion of a semiconductor device structure, in accordance with some embodiments.FIGS.2A-1to2N-1are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, in accordance with some embodiments.FIGS.2A-2to2N-2are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, in accordance with some embodiments.

As shown inFIG.1A, multiple fin structures106A and106B are formed, in accordance with some embodiments. In some embodiments, the fin structures106A and106B are oriented lengthwise. In some embodiments, the extending directions of the fin structures106A and106B are substantially parallel to each other, as shown inFIG.1A. In some embodiments,FIG.2A-1is a cross-sectional view of the structure taken along the line1-1inFIG.1A. In some embodiments,FIG.2A-2is a cross-sectional view of the structure taken along the line2-2inFIG.1A.

As shown inFIGS.2A-1and2A-2, a semiconductor substrate100is received or provided. In some embodiments, the semiconductor substrate100is a bulk semiconductor substrate, such as a semiconductor wafer. The semiconductor substrate100may include silicon or other elementary semiconductor materials such as germanium. The semiconductor substrate100may be un-doped or doped (e.g., p-type, n-type, or a combination thereof). In some embodiments, the semiconductor substrate100includes an epitaxially grown semiconductor layer on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, another suitable material, or a combination thereof.

In some other embodiments, the semiconductor substrate100includes a compound semiconductor. For example, the compound semiconductor includes one or more III-V compound semiconductors having a composition defined by the formula AlX1GaX2InX3AsY1PY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. Each of them is greater than or equal to zero, and added together they equal 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or a combination thereof. Other suitable substrate including II-VI compound semiconductors may also be used.

In some embodiments, the semiconductor substrate100is an active layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be fabricated using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, another applicable method, or a combination thereof. In some other embodiments, the semiconductor substrate100includes a multi-layered structure. For example, the semiconductor substrate100includes a silicon-germanium layer formed on a bulk silicon layer.

In some embodiments, a semiconductor stack having multiple semiconductor layers is formed over the semiconductor substrate100, in accordance with some embodiments. In some embodiments, the semiconductor stack includes multiple semiconductor layers102aand102b. The semiconductor stack also includes multiple semiconductor layers104aand104b. In some embodiments, the semiconductor layers102aand102band the semiconductor layers104aand104bare laid out alternately, as shown inFIGS.2A-1and2A-2. The semiconductor layers102aand102band the semiconductor layers104aand104bhave an alternating configuration, as shown inFIGS.2A-1and2A-2.

In some embodiments, the semiconductor layers102aand102bfunction as sacrificial layers that will be removed in a subsequent process to release the semiconductor layers104aand104b. The semiconductor layers104aand104bthat are released may function as channel structures of one or more transistors.

In some embodiments, the semiconductor layers104aand104bthat will be used to form channel structures are made of a material that is different than that of the semiconductor layers102aand102b. In some embodiments, the semiconductor layers104aand104bare made of or include silicon, germanium, another suitable material, or a combination thereof. In some embodiments, the semiconductor layers102aand102bare made of or include silicon germanium. In some other embodiments, the semiconductor layers104aand104bare made of silicon germanium, and the semiconductor layers102aand102bare made of silicon germanium with different atomic concentration of germanium than that of the semiconductor layers104aand104b. As a result, different etching selectivity and/or different oxidation rates during subsequent processing may be achieved between the semiconductor layers102a-102band the semiconductor layers104a-104b.

The present disclosure contemplates that the semiconductor layers102aand102band the semiconductor layers104aand104binclude any combination of semiconductor materials that can provide desired etching selectivity, desired oxidation rate differences, and/or desired performance characteristics (e.g., materials that maximize current flow).

In some embodiments, the semiconductor layers102a-102band104a-104bare formed using multiple epitaxial growth operations. Each of the semiconductor layers102a-102band104a-104bmay be formed using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, and/or an ultra-high vacuum CVD (UHV-CVD) process), a molecular beam epitaxy process, another applicable process, or a combination thereof. In some embodiments, the semiconductor layers102a-102band104a-104bare grown in-situ in the same process chamber. In some embodiments, the growth of the semiconductor layers102a-102band104a-104bare alternately and sequentially performed in the same process chamber to complete the formation of the semiconductor stack. In some embodiments, the vacuum of the process chamber is not broken before the epitaxial growth of the semiconductor stack is accomplished.

Afterwards, hard mask elements are formed over the semiconductor stack to assist in a subsequent patterning of the semiconductor stack. Each of the hard mask elements may include a first mask layer and a second mask layer. The first mask layer and the second mask layer may be made of different materials. One or more photolithography processes and one or more etching processes are used to pattern the semiconductor stack into multiple fin structures106A and106B, as shown inFIGS.1A,2A-1, and2A-2.

The fin structures106A and106B may be patterned by any suitable method. For example, the fin structures106A and106B may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Double-patterning or multi-patterning processes may combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.

The semiconductor stack is partially removed to form multiple trenches. Each of the fin structures may include portions of the semiconductor layers102a-102band104a-104band multiple semiconductor fins101A and101B, as shown inFIGS.2A-1and2A-2. The semiconductor substrate100may also be partially removed during the etching process that forms the fin structures106A and106B. Protruding portions of the semiconductor substrate100that remain form the semiconductor fins101A-101B.

Afterwards, as shown inFIG.2A-2, an isolation structure114is formed to surround lower portions of the fin structures106A and106B, in accordance with some embodiments. In some embodiments, one or more dielectric layers are deposited over the fin structures106A and106B and the semiconductor substrate100. The dielectric layers may overfill the trenches between the fin structures106A and106B.

The dielectric layers may be made of or include silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, porous dielectric material, another suitable material, or a combination thereof. The dielectric layers may be deposited using a chemical vapor deposition (CVD) process, a flowable chemical vapor deposition (FCVD) process, an atomic layer deposition (ALD) process, another applicable process, or a combination thereof.

Afterwards, a planarization process is used to partially remove the dielectric layers. The hard mask elements (including the first mask layer and the second mask layer) used for forming the fin structures106A-106B may also function as a stop layer of the planarization process. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, a dry polishing process, an etching process, another applicable process, or a combination thereof.

Afterwards, one or more etching back processes are used to partially remove the dielectric layers. As a result, the remaining portion of the dielectric layers forms the isolation structure114. Upper portions of the fin structures106A and106B protrude from the top surface of the isolation structure114, as shown inFIG.2A-2.

In some embodiments, the etching back process for forming the isolation structure114is carefully controlled to ensure that the topmost surface of the isolation structure114is positioned at a suitable height level, as shown inFIG.2A-2. In some embodiments, the topmost surface of the isolation structure114is below the bottommost surface of the semiconductor layer102athat functions as a sacrificial layer.

Afterwards, the hard mask elements (including the first mask layer and the second mask layer) are removed. Alternatively, in some other embodiments, the hard mask elements are removed or consumed during the planarization process and/or the etching back process that forms the isolation structure114.

Afterwards, dummy gate stacks120A,120B, and120C are formed to extend across the fin structures106A and106B, as shown inFIGS.1B and2B-1in accordance with some embodiments. In some embodiments,FIG.2B-2is a cross-sectional view of the structure taken along the line2-2inFIG.1B. The fin structures106A and106B are exposed without being covered by the dummy gate stacks120A-120C. As shown inFIGS.1B and2B-1, the dummy gate stacks120A-120C are formed to partially cover and to extend across the fin structures106A and106B, in accordance with some embodiments. In some embodiments, the dummy gate stacks120A-120C are wrapped around the fin structures106A and106B.

As shown inFIG.2B-1, each of the dummy gate stacks120A-120C includes a dummy gate dielectric layer116and a dummy gate electrode118. The dummy gate dielectric layers116may be made of or include silicon oxide or another suitable material. The dummy gate electrodes118may be made of or include polysilicon or another suitable material.

In some embodiments, a dummy gate dielectric material layer and a dummy gate electrode layer are sequentially deposited over the isolation structure114and the fin structures106A and106B. The dummy gate dielectric material layer may be deposited using an ALD process, a CVD process, another applicable process, or a combination thereof. The dummy gate electrode layer may be deposited using a CVD process. Afterwards, the dummy gate dielectric material layer and the dummy gate electrode layer are patterned to form the dummy gate stacks120A-120C.

In some embodiments, hard mask elements including mask layers122and124are used to assist in the patterning process for forming the dummy gate stacks120A-120C. With the hard mask elements as an etching mask, one or more etching processes are used to partially remove the dummy gate dielectric material layer and the dummy gate electrode layer. As a result, remaining portions of the dummy gate dielectric material layer and the dummy gate electrode layer form the dummy gate dielectric layers116and the dummy gate electrodes118, respectively. As a result, the dummy gate stacks120A-120C are formed.

As shown inFIGS.2C-1and2C-2, spacer layers126and128are then deposited over the dummy gate stacks120A-120C and the fin structures106A-106B, in accordance with some embodiments. The spacer layers126and128extend along the tops and sidewalls of the dummy gate stacks120A-120C and the fin structures106A-106B, as shown inFIGS.2C-1and2C-2.

In some embodiments, the spacer layers126and128are made of different materials. The spacer layer126may be made of a dielectric material that has a low dielectric constant. The spacer layer126may be made of or include silicon carbide, silicon oxycarbide, carbon-containing silicon oxynitride, silicon oxide, another suitable material, or a combination thereof. In some embodiments, the spacer layer126is a single layer. In some other embodiments, the spacer layer126includes multiple sub-layers. Some of the sub-layers may be made of different materials. Some of the sub-layers may be made of similar materials with different compositions. For example, one of the sub-layers may have a greater atomic concentration of carbon than other sub-layers.

The spacer layer128may be made of a dielectric material that can provide more protection to the gate stacks during subsequent processes. The spacer layer128may have a greater dielectric constant than that of the spacer layer126. The spacer layer128may be made of silicon nitride, silicon oxynitride, carbon-containing silicon nitride, carbon-containing silicon oxynitride, another suitable material, or a combination thereof. The spacer layers126and128may be sequentially deposited using a CVD process, an ALD process, a physical vapor deposition (PVD) process, another applicable process, or a combination thereof.

However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the spacer layers126and128are made of the same material.

As shown inFIGS.2D-1and2D-2, the spacer layers126and128are partially removed, in accordance with some embodiments. One or more anisotropic etching processes may be used to partially remove the spacer layers126and128. As a result, first remaining portions of the spacer layers126and128form gate spacers126′ and128′, respectively. The gate spacers126′ and128′ together form gate spacer structures. The gate spacers126′ and128′ extend along the sidewalls of the dummy gate stacks120A-120C, as shown inFIG.2D-1. In some embodiments, second remaining portions of the spacer layers126and128form spacers126″ and128″, respectively. The spacers126″ and128″ together form spacer structures129, as shown inFIG.2D-2. In some embodiments, the spacer structures129and the gate spacer structures are made of the same material.

In some embodiments, the fin structures106A-106B are partially removed, in accordance with some embodiments. As a result, the recesses130are formed, as shown inFIGS.2D-1and2D-2. The recesses130may be used to contain epitaxial structures (such as source/drain structures) that will be formed later. One or more etching processes may be used to form the recesses130. In some embodiments, a dry etching process is used to form the recesses130. Alternatively, a wet etching process may be used to form the recesses130.

In some embodiments, the recesses130penetrate into the fin structures106A-106B. In some embodiments, the recesses130further extend into the semiconductor fins101A and101B, as shown inFIGS.2D-1and2D-2. In some embodiments, the gate spacers126′ and128′, the spacer structures129, and the recesses130are formed simultaneously using the same etching process.

Afterwards, as shown inFIG.2E-1, the semiconductor layers102aand102bare partially removed, in accordance with some embodiments. The semiconductor layers102aand102bmay be laterally etched from the exposed side surfaces. As a result, edges of the semiconductor layers102aand102bretreat from edges of the semiconductor layers104aand104b.

As shown inFIG.2E-1, recesses132are formed due to the lateral etching of the semiconductor layers102aand102b. The recesses132may be used to contain inner spacers that will be formed later. The semiconductor layers102aand102bmay be laterally etched using a wet etching process, a dry etching process, or a combination thereof. In some other embodiments, the semiconductor layers102aand102bare partially oxidized before being laterally etched.

As shown inFIGS.2E-1and2E-2, an inner spacer layer134is deposited over the dummy gate stacks120A-120C and the fin structures106A-106B, in accordance with some embodiments. The inner spacer layer134covers the dummy gate stacks120A-120C and fills the recesses132. The inner spacer layer134further extends over the spacer structures129and the semiconductor fins101A and101B.

The inner spacer layer134may be made of or include carbon-containing silicon nitride (SiCN), carbon-containing silicon oxynitride (SiOCN), carbon-containing silicon oxide (SiOC), silicon oxide, silicon nitride, another suitable material, or a combination thereof. In some embodiments, the inner spacer layer134is a single layer. The inner spacer layer134may be deposited using a CVD process, an ALD process, another applicable process, or a combination thereof.

As shown inFIGS.2F-1and2F-2, an etching process is used to partially remove the inner spacer layer134, in accordance with some embodiments. The portions of the inner spacer layer134that are outside of the recesses132may be removed, as shown inFIGS.2F-1and2F-2. The remaining portions of the inner spacer layer134form inner spacers136, as shown inFIG.2F-1.

In some embodiments, the etching process is an isotropic etching process. The etching process may include a dry etching process, a wet etching process, or a combination thereof. The etching process may be carefully controlled so that it does not substantially etch the gate spacers126′ and128′ or the spacer structures129. The spacer structures129may thus have sufficient height, which facilitates the subsequent formation of epitaxial structures. The nearby epitaxial structures may be prevented from being merged together due to the spacer structures129.

The inner spacers136cover the edges of the semiconductor layers102aand102b. The inner spacers136may be used to prevent subsequently formed epitaxial structures (that function as, for example, source/drain structures) from being damaged during a subsequent process for removing the semiconductor layers102aand102b. As mentioned above, in some embodiments, the inner spacer layer134is partially removed using an isotropic etching process. The laterally etch of the inner spacer layer134may thus be minimized. The dishing degree of the inner spacers136may thus be minimized, which ensures the quality of the inner spacers136. The risk of short circuiting between the gate electrode and the source/drain structures is substantially reduced.

In some embodiments, the inner spacers136are made of a low-k material that has a lower dielectric constant than that of silicon oxide. In these cases, the inner spacers136may also be used to reduce parasitic capacitance between the subsequently formed source/drain structures and the gate stacks. As a result, the operation speed of the semiconductor device structure may be improved.

In some embodiments, after the etching process for forming the inner spacers136, portions of the semiconductor fin101A and101B that are originally covered by the inner spacer layer134are exposed by the recesses130, as shown inFIGS.2F-1and2F-2. The edges of the semiconductor layers104aand104bare also exposed by the recesses130, as shown inFIG.2F-1.

As shown inFIGS.2G-1and2G-2, semiconductor isolation structures137are formed over the bottoms of the recesses130, in accordance with some embodiments. In some embodiments, the semiconductor isolation structures137are epitaxial structures that are undoped. In some embodiments, the semiconductor isolation structures137are substantially free of n-type dopants or p-type dopants.

The semiconductor isolation structures137may be made of or include silicon, silicon germanium, another suitable material, or a combination thereof. The semiconductor isolation structures137may be formed using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, and/or an ultra-high vacuum CVD (UHV-CVD) process), a molecular beam epitaxy process, another applicable process, or a combination thereof.

In some embodiments, the semiconductor isolation structures137are formed to have substantially planar top surfaces, as shown inFIGS.2G-1and2G-2. In some embodiments, the top surfaces of the semiconductor isolation structures137are positioned at a height level that is lower than the bottom surface of the semiconductor layer104a. In some embodiments, the top surfaces of the semiconductor isolation structures137and the top surface of the semiconductor fin101B are substantially level, as shown inFIG.2G-1. In some embodiments, the semiconductor isolation structures137are in direct contact with the spacer structures129, as shown inFIG.2G-2.

As shown inFIGS.2H-1and2H-2, a second inner spacer layer202is deposited over the dummy gate stacks120A-120C, the inner spacers136, and the spacer structures129, in accordance with some embodiments. The second inner spacer layer202covers the dummy gate stacks120A-120C and fills the recesses of the inner spacers136. The second inner spacer layer202further extends over the semiconductor isolation structures137and the isolation structure114.

The second inner spacer layer202may be made of or include carbon-containing silicon nitride (SiCN), carbon-containing silicon oxynitride (SiOCN), carbon-containing silicon oxide (SiOC), silicon oxide, silicon nitride, another suitable material, or a combination thereof. In some embodiments, the second inner spacer layer202is a single layer. In some embodiments, the second inner spacer layer202includes multiple sub-layers. The second inner spacer layer202may be deposited using a CVD process, an ALD process, another applicable process, or a combination thereof.

As shown inFIGS.2I-1and2I-2, an etching process is used to partially remove the second inner spacer layer202, in accordance with some embodiments. The portions of the second inner spacer layer202that are outside of the recesses of the inner spacers136may be removed, as shown inFIGS.2I-1and2I-2. The remaining portions of the second inner spacer layer202form second inner spacers204, as shown inFIG.2I-1.

In some embodiments, the etching process is an isotropic etching process. The etching process may include a dry etching process, a wet etching process, or a combination thereof. The etching process may be carefully controlled so that it does not substantially etch the gate spacers126′ and128′ or the spacer structures129. As shown inFIG.2I-1, the spacer structures129may thus have sufficient height, which facilitates the subsequent formation of epitaxial structures. The nearby epitaxial structures may be prevented from being merged together due to the spacer structures129.

The second inner spacers204cover the edges of the inner spacers136. The second inner spacers204and136may together be used to prevent subsequently formed epitaxial structures (that function as, for example, source/drain structures) from being damaged during a subsequent process for removing the semiconductor layers102aand102b. As mentioned above, in some embodiments, the second inner spacer layer202is partially removed using an isotropic etching process. The laterally etch of the second inner spacer layer202may thus be minimized. The dishing degree of the second inner spacers204may thus be minimized, which ensures the quality of the second inner spacers204. In some embodiments, the edges of the second inner spacers204are aligned with the edges of the semiconductor layers104aand104b, as shown inFIG.2I-1. The risk of short circuiting between the gate electrode and the source/drain structures is substantially reduced.

In some embodiments, the second inner spacers204are made of a low-k material that has a lower dielectric constant than that of silicon oxide. In these cases, the second inner spacers204may also be used to reduce parasitic capacitance between the subsequently formed source/drain structures and the gate stacks. As a result, the operation speed of the semiconductor device structure may be improved.

In some embodiments, after the etching process for forming the second inner spacers204, the semiconductor isolation structures137that are originally covered by the second inner spacer layer202are exposed by the recesses130, as shown inFIGS.2I-1and2I-2. The edges of the semiconductor layers104aand104bare also exposed by the recesses130, as shown inFIG.2I-1.

As shown inFIGS.2J-1and2J-2, isolation films206are formed over the tops of the semiconductor isolation structures137, the spacer structures129, the isolation structure114, and the dummy gate stacks120A-120C, in accordance with some embodiments. The isolation films206may help to prevent or minimize the bulk substrate leakage and well isolation leakage. In some embodiments, the isolation films206covers the tops of the semiconductor isolation structures137, the spacer structures129, the isolation structure114, and the dummy gate stacks120A-120C. In some embodiments, the isolation films206do not cover the sidewalls of the spacer structures129and the dummy gate stacks120A-120C, as shown inFIGS.2J-1and2J-2. In some embodiments, the isolation films206are in direct contact with the semiconductor isolation structures137and some of the second inner spacers204. In some embodiments, the spacer structures129extend across the bottom surfaces of the isolation films206and the top surfaces of the isolation films206, as shown inFIG.2J-2.

As mentioned above, in some embodiments, the semiconductor isolation structures137have substantially planar top surfaces. The planar top surfaces of the semiconductor isolation structures137may facilitate the formation of the isolation films206. As a result, better uniformity control of the isolation films206is achieved. The semiconductor isolation structures137and the isolation films206may thus together suppress the bottom substrate leakage. The performance and reliability of the semiconductor device structure are greatly improved.

The isolation films206may be made of or include carbon-containing silicon nitride (SiCN), carbon-containing silicon oxynitride (SiOCN), carbon-containing silicon oxide (SiOC), silicon oxide, silicon nitride, another suitable material, or a combination thereof. In some embodiments, each of the isolation films206is a single layer. In some other embodiments, each of the isolation films206includes multiple sub-layers.

The isolation films206may be deposited using a CVD process, a plasma-enhanced chemical vapor deposition (PECVD) process, an ALD process, another applicable process, or a combination thereof. In some embodiments, the formation of the isolation films206involves introducing plasma, which may help to prevent the isolation films206from being formed on the sidewalls of the dummy gate stacks120A-120C, the spacer structures129, the semiconductor layers104a-104b, and the second inner spacers204.

As shown inFIGS.2K-1and2K-2, epitaxial structures138are formed in the recesses130, in accordance with some embodiments. In some embodiments, one or more semiconductor materials are directly grown on the side surfaces of the semiconductor layers104aand104b. As a result, the semiconductor material forms the epitaxial structures138. In some embodiments, the epitaxial structures138are in direct contact with the isolation films206. In some embodiments, the epitaxial structures138overfill the recesses130to ensure fully contact between the epitaxial structures138and the semiconductor layers104a-104b. In some embodiments, the top surfaces of the epitaxial structures138are higher than the top surface of the dummy gate dielectric layer116.

In some embodiments, the epitaxial structures138connect to the semiconductor layers104aand104b. Portions of the semiconductor layers104aand104bthat will be function as channel structures are sandwiched between two respective epitaxial structures138, as shown inFIGS.2K-1and2K-2. In some embodiments, the epitaxial structures138are designed to function as source/drain structures of p-channel field-effect transistors (PFET). The epitaxial structures138may include epitaxially grown silicon germanium (SiGe), epitaxially grown silicon, or another suitable epitaxially grown semiconductor material. In some embodiments, the epitaxial structures138are doped with one or more suitable p-type dopants. For example, the epitaxial structures138are SiGe source/drain features or Si source/drain features that are doped with boron (B), gallium (Ga), indium (In), or another suitable dopant.

In some other embodiments, the epitaxial structures138are designed to function as source/drain structures of n-channel field-effect transistors (NFET). The epitaxial structures138may include epitaxially grown silicon or another suitable epitaxially grown semiconductor material. The epitaxial structures138are n-type doped. In some embodiments, the epitaxial structures138are doped with one or more suitable n-type dopants. For example, the epitaxial structures138are Si source/drain features that are doped with phosphor (P), antimony (Sb), arsenic (As), or another suitable dopant.

The term “source/drain structure” may refer to a source structure or a drain structure, individually or collectively, depending on the context.

In some embodiments, the epitaxial structures138are formed using multiple epitaxial growth operations. In some embodiments, these epitaxial growth operations are performed in-situ in the same process chamber. In some embodiments, the vacuum of the process chamber is not broken before the formation of the epitaxial structures138is accomplished. The reaction gases may be varied in the reaction chamber during the epitaxial growth operations.

These epitaxial growth operations may be achieved using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor-phase epitaxy (VPE) process, a low-pressure chemical vapor deposition (LPCVD) process, and/or an ultra-high vacuum CVD (UHV-CVD) process), a molecular beam epitaxy process, one or more other applicable processes, or a combination thereof. In some embodiments, the formation of the epitaxial structures138involves one or more etching processes that are used to fine-tune the shapes of the epitaxial structures138.

In some embodiments, the epitaxial structures138are doped in-situ during their epitaxial growth. The initial reaction gas mixture for forming the epitaxial structures138contains respective dopants. In some embodiments, the epitaxial structures138are further exposed to one or more annealing processes to activate the dopants. For example, a rapid thermal annealing process is used. During the one or more annealing processes, the sacrificial structure210′ remains stable.

The spacer structures129may confine the growth of the epitaxial structures138, so as to form the epitaxial structures138with desired profiles. As shown inFIG.2K-1, due to the confine of the spacer structures129, the epitaxial structures138that are positioned nearby are prevented from being merged together.

As mentioned above, the etching processes used for forming the inner spacers136and204are isotropic etching processes that substantially do not etch the gate spacers126′ and128′ and the spacer structures129. The spacer structures129may substantially remain after these isotropic etching processes. Therefore, each of the spacer structures129may have a height h that is sufficient to confine the growth of the epitaxial structures138, as shown inFIG.2K-2. The height h of the spacer structures129may be within a range from about 10 nm to about 30 nm. As shown inFIG.2K-2, each of the epitaxial structures138has a height H. The height H of the epitaxial structures138may be within a range from about 20 nm to about 45 nm. In some of the embodiments, more stacked channel structures (such as a three nanosheets structure) are to be formed beside each of the epitaxial structures138. The height H may be within a range from about 35 nm to about 60 nm.

The ratio (h/H) of the height h to the height H may be within a range from about 0.15 to about 0.6. In some cases, if the ratio (h/H) is smaller than about 0.15, the height h may be too small. The spacer structures129may not be able to confine the growth of the epitaxial structures138. The epitaxial structures138that are positioned nearby may be merged together. In some other cases, if the ratio (h/H) is greater than about 0.6, the growth of the epitaxial structures138may be confined too much. The epitaxial structures138may thus have insufficient width, which may also not be desired. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the ratio (h/H) of the height h to the height H is within a range from about 0.2 to about 0.5.

As shown inFIGS.2L-1and2L-2, a contact etch stop layer139and a dielectric layer140are then formed to surround the epitaxial structures138, the dummy gate stacks120A-120C, and the spacer structures129, in accordance with some embodiments. The contact etch stop layer139may be made of or include silicon nitride, silicon oxynitride, silicon carbide, aluminum oxide, another suitable material, or a combination thereof. The dielectric layer140may be made of or include silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, porous dielectric material, another suitable material, or a combination thereof.

In some embodiments, an etch stop material layer and a dielectric material layer are sequentially deposited. The etch stop material layer may be deposited using a CVD process, an ALD process, a PVD process, another applicable process, or a combination thereof. The dielectric material layer may be deposited using an FCVD process, a CVD process, an ALD process, another applicable process, or a combination thereof.

Afterwards, a planarization process is used to partially remove the etch stop material layer and the dielectric material layer. As a result, the remaining portions of the etch stop material layer and the dielectric material layer respectively form the contact etch stop layer139and the dielectric layer140, as shown inFIGS.2L-1and2L-2. The planarization process may include a CMP process, a grinding process, an etching process, a dry polishing process, another applicable process, or a combination thereof. In some embodiments, the mask layers122and124and the isolation films206on the mask layer124are also removed during the planarization process. In some embodiments, after the planarization process, the top surfaces of the contact etch stop layer139, the dielectric layer140, and the dummy gate electrodes118are substantially level.

Afterwards, the dummy gate electrodes118are removed to form trenches142using one or more etching processes, in accordance with some embodiments. The trenches142are surrounded by the dielectric layer140. The trenches142may expose the dummy gate dielectric layer116.

Afterwards, as shown inFIG.2M-1, the dummy gate dielectric layer116and the semiconductor layers102aand102b(that function as sacrificial layers) are removed, in accordance with some embodiments. In some embodiments, one or more etching processes are used to remove the dummy gate dielectric layer116and the semiconductor layers102aand102b. As a result, recesses144are formed, as shown inFIG.2M-1. As shown inFIG.2M-2, the dielectric layer140protects the epitaxial structures138thereunder during the formation of the trenches142and the recesses144.

Due to high etching selectivity, the semiconductor layers104aand104bare slightly (or substantially not) etched. The remaining portions of the semiconductor layers104aand104bform multiple semiconductor nanostructures104a′-104b′. The semiconductor nanostructures104a′-104b′ are constructed by or made up of the remaining portions of the semiconductor layers104aand104b. The semiconductor nanostructures104a′-104b′ may function as channel structures of transistors.

In some embodiments, the etchant used for removing the semiconductor layers102aand102balso slightly removes the semiconductor layers104aand104bthat form the semiconductor nanostructures104a′-104b′. As a result, the obtained semiconductor nanostructures104a′-104b′ may become thinner after the removal of the semiconductor layers102aand102b.

After the removal of the semiconductor layers102aand102b(that function as sacrificial layers), the recesses144are formed. The recesses144connect to the trench142and surround each of the semiconductor nanostructures104a′-104b′. As shown inFIG.2M-1, even if the recesses144between the semiconductor nanostructures104a′-104b′ are formed, the semiconductor nanostructures104a′-104b′ remain being held by the epitaxial structures138. Therefore, after the removal of the semiconductor layers102aand102b(that function as sacrificial layers), the released semiconductor nanostructures104a′-104b′ are prevented from falling down.

During the removal of the semiconductor layers102aand102b(that function as sacrificial layers), the inner spacers136and204protect the epitaxial structures138from being etched or damaged. The quality and reliability of the semiconductor device structure are improved.

As shown inFIGS.2N-1and2N-2, metal gate stacks156A,156B, and156C are formed to fill the trenches142, in accordance with some embodiments. The metal gate stacks156A-156C further extend into the recesses144to wrap around each of the semiconductor nanostructures104a′-104b′, as shown inFIG.2N-1.

Each of the metal gate stacks156A-156C includes multiple metal gate stack layers. Each of the metal gate stacks156A-156C may include a gate dielectric layer150and a metal gate electrode152. The metal gate electrode152may include a work function layer. The metal gate electrode152may further include a conductive filling. In some embodiments, the formation of the metal gate stacks156A-156C involves the deposition of multiple metal gate stack layers over the dielectric layer140to fill the trenches142and the recesses144. The metal gate stack layers extend into the recesses144to wrap around each of the semiconductor nanostructures104a′-104b′.

In some embodiments, the gate dielectric layer150is made of or includes a dielectric material with high dielectric constant (high-K). The gate dielectric layer150may be made of or include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high-K materials, or a combination thereof. The gate dielectric layer150may be deposited using an ALD process, a CVD process, another applicable process, or a combination thereof.

In some embodiments, before the formation of the gate dielectric layer150, interfacial layers151are formed on the surfaces of the semiconductor nanostructures104a′-104b′. The interfacial layers151are very thin and are made of silicon oxide or germanium oxide, for example. In some embodiments, the interfacial layers151are formed by applying an oxidizing agent on the surfaces of the semiconductor nanostructures104a′-104b′. For example, a hydrogen peroxide-containing liquid may be provided or applied on the surfaces of the semiconductor nanostructures104a′-104b′ so as to form the interfacial layers151.

The work function layer of the metal gate electrode152may be used to provide the desired work function for transistors to enhance device performance including improved threshold voltage. In some embodiments, the work function layer is used for forming a PMOS device. The work function layer is a p-type work function layer. The p-type work function layer is capable of providing a work function value suitable for the device, such as equal to or greater than about 4.8 eV.

The p-type work function layer may include metal, metal carbide, metal nitride, another suitable material, or a combination thereof. For example, the p-type metal includes tantalum nitride, tungsten nitride, titanium, titanium nitride, another suitable material, or a combination thereof.

In some embodiments, the work function layer is used for forming an NMOS device. The work function layer is an n-type work function layer. The n-type work function layer is capable of providing a work function value suitable for the device, such as equal to or less than about 4.5 eV.

The n-type work function layer may include metal, metal carbide, metal nitride, or a combination thereof. For example, the n-type work function layer includes titanium nitride, tantalum, tantalum nitride, another suitable material, or a combination thereof. In some embodiments, the n-type work function is an aluminum-containing layer. The aluminum-containing layer may be made of or include TiAlC, TiAlO, TiAlN, another suitable material, or a combination thereof.

The work function layer may also be made of or include hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminides, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or a combinations thereof. The thickness and/or the compositions of the work function layer may be fine-tuned to adjust the work function level.

The work function layer may be deposited over the gate dielectric layer150using an ALD process, a CVD process, a PVD process, an electroplating process, an electroless plating process, another applicable process, or a combination thereof. In some embodiments, the formation of the work function layer involves one or more patterning processes. As a result, the n-type work function layer and the n-type work function layer are selectively formed over respective regions.

In some embodiments, a barrier layer is formed before the work function layer to interface the gate dielectric layer150with the subsequently formed work function layer. The barrier layer may also be used to prevent diffusion between the gate dielectric layer150and the subsequently formed work function layer. The barrier layer may be made of or include a metal-containing material. The metal-containing material may include titanium nitride, tantalum nitride, another suitable material, or a combination thereof. The barrier layer may be deposited using an ALD process, a CVD process, a PVD process, an electroplating process, an electroless plating process, another applicable process, or a combination thereof.

In some embodiments, the conductive fillings of the metal gate electrodes152are made of or include a metal material. The metal material may include tungsten, aluminum, copper, cobalt, another suitable material, or a combination thereof. A conductive layer used for forming the conductive filling may be deposited over the work function layer using a CVD process, an ALD process, a PVD process, an electroplating process, an electroless plating process, a spin coating process, another applicable process, or a combination thereof.

In some embodiments, a blocking layer is formed over the work function layer before the formation of the conductive layer used for forming the conductive filling. The blocking layer may be used to prevent the subsequently formed conductive layer from diffusing or penetrating into the work function layer. The blocking layer may be made of or include tantalum nitride, titanium nitride, another suitable material, or a combination thereof. The blocking layer may be deposited using an ALD process, a PVD process, an electroplating process, an electroless plating process, another applicable process, or a combination thereof.

Afterwards, a planarization process is performed to remove the portions of the metal gate stack layers outside of the trenches142, in accordance with some embodiments. As a result, the remaining portions of the metal gate stack layers form the metal gate stacks156A-156C, as shown inFIGS.2N-1and2N-2.

In some embodiments, the conductive filling does not extend into the recesses144since the recesses144are small and have been filled with other elements such as the gate dielectric layer150and the work function layer.

In some embodiments, each of the epitaxial structures138that are n-type doped or p-type doped is separated from the semiconductor isolation structure137thereunder by the isolation film206therebetween. However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, some of the epitaxial structures138are in direct contact with the semiconductor isolation structures137thereunder.

FIGS.3A-1to3D-1are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, in accordance with some embodiments.FIGS.3A-2to3D-2are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, in accordance with some embodiments. As shown inFIGS.3A-1and3A-2, a structure that is the same as or similar to the structure shown inFIGS.2J-1and2J-2is formed, in accordance with some embodiments.

As shown inFIGS.3B-1and3B-2, some of the isolation films206are removed to expose the semiconductor isolation structures137thereunder, in accordance with some embodiments. In some embodiments, a patterned mask layer is formed to partially cover a first part the isolation films206so that a second part of the isolation films206are exposed. Afterwards, one or more etching processes are used to remove the second part of the isolation films206. As a result, the structure illustrated inFIGS.3B-1and3B-2is formed.

As shown inFIGS.3C-1and3C-2, epitaxial structures138are formed on the semiconductor isolation structures137, in accordance with some embodiments. The material and formation method of the epitaxial structures138may be the same as or similar to those of the epitaxial structures138shown inFIGS.2K-1and2K-2. In some embodiments, the epitaxial structures138shown inFIGS.3C-1and3C-2are p-type doped. In some embodiments, the epitaxial structures138are in direct contact with the semiconductor isolation structures137thereunder. Due to the lattice mismatch between the epitaxial structures138and the semiconductor isolation structures137, higher stain may be applied on the semiconductor nanostructures104a′-104b′. The performance and reliability of the semiconductor device structure may be improved.

Afterwards, similar to the embodiments illustrated inFIGS.2L-1to2N-1andFIGS.2L-2to2N-2, a gate replacement process is performed. As a result, the metal gate stacks156A-156C are formed to wrap around the semiconductor nanostructures104a′-104b′, as shown inFIGS.3D-1and3D-2in accordance with some embodiments.

As illustrated in the embodiments shown inFIGS.3A-1to3D-1and3A-2to3D-2, some parts of the isolation films236are selectively removed.FIG.4is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure, in accordance with some embodiments. In some embodiments, multiple epitaxial structures438N that are n-type doped are formed in a first region of the semiconductor device structure. Multiple epitaxial structures438P that are p-type doped are formed in a second region of the semiconductor device structure. The epitaxial structures438N and438P may be sequentially formed. The material and formation method of the epitaxial structures438N may be the same as or similar to the epitaxial structures138that are n-type doped as illustrated inFIGS.2K-1and2K-2. The material and formation method of the epitaxial structures438P may be the same as or similar to the epitaxial structures138that are p-type doped as illustrated inFIGS.2K-1and2K-2.

In some embodiments, each of the epitaxial structures438N is separated from the semiconductor isolation structure137thereunder by the isolation film236thereunder. The isolation film236therebetween may prevent or reduce leakage current from the epitaxial structure438N.

In some embodiments, the isolation films236are selectively removed. No isolation film is formed in the second region where the epitaxial structures438P are formed. In some embodiments, the epitaxial structures438P are in direct contact with the semiconductor isolation structures236.

FIG.5is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure, in accordance with some embodiments. In some embodiments, similar to the embodiments shown inFIG.4, each of the epitaxial structures438N is separated from the semiconductor isolation structure137thereunder by the isolation film236thereunder, as shown inFIG.5. The isolation film236therebetween may prevent or reduce leakage current from the epitaxial structure438N. Similar to the embodiments shown inFIG.2N-1, some of the isolation film236are between the contact etch stop layer139and the spacer structures129. In some embodiments, the tops of the spacer structures129are separated from the contact etch stop layer139by the isolation films236.

In some embodiments, similar to the embodiments shown inFIG.4, the isolation films236are selectively removed, as shown inFIG.5. No isolation film is formed in the second region where the epitaxial structures438P are formed. In some embodiments, the epitaxial structures438P are in direct contact with the semiconductor isolation structures236. In some embodiments, the tops of the spacer structures129are in direct contact with the contact etch stop layer139.

Many variations and/or modifications can be made to embodiments of the disclosure.FIGS.6A-1to6H-1are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, in accordance with some embodiments.FIGS.6A-2to6H-2are cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, in accordance with some embodiments.

As shown inFIGS.6A-1and6A-2, a structure that is the same as or similar to the structure shown inFIGS.2A-1and2A-2is formed, in accordance with some embodiments. Afterwards, the processes that is the same as or similar to those illustrated inFIGS.2B-1and2B-2are performed. As a result, the structure shown inFIGS.6B-1and6B-2is formed, in accordance with some embodiments.

Afterwards, the processes that is the same as or similar to those illustrated inFIGS.2C-1to2E-1and2B-2to2E-2are performed. As a result, the structure shown inFIGS.6C-1and6C-2is formed, in accordance with some embodiments.

As shown inFIGS.6D-1and6D-2, one or more modifiers are introduced into portions of the inner spacer layer134, so as to form multiple modified regions604of the inner spacer layer134, in accordance with some embodiments. One or more implantation process602may be used to form the modified regions604. The modified regions604may be formed on the tops of the dummy gate stacks120A-120C and the bottoms of the recesses130.

The modifiers may include nitrogen atoms, nitrogen-containing ions, carbon atoms, carbon-containing ions, silicon atoms, silicon-containing ions, nitrogen molecules, nitrogen-containing molecules, another suitable modifier, or a combination thereof. In some embodiments, the implantation angle applied in the implantation process602is substantially equal to zero. Therefore, the portions of the inner spacer layer134that are located on the sidewalls of the dummy gate stacks120A-120C and the spacer structures129are free of the implanted modifiers.

As shown inFIGS.6E-1and6E-2, the modified regions604of the inner spacer layer134are removed, in accordance with some embodiments. As a result, a patterned inner spacer layer134′ is formed. The semiconductor fins101A-101B are thus partially exposed, as shown inFIGS.6E-1and6E-2.

As shown inFIGS.6F-1and6F-2, an etching process is used to partially remove the patterned inner spacer layer134′, in accordance with some embodiments. The portions of the patterned inner spacer layer134′ that are outside of the recesses132may be removed, as shown inFIGS.6F-1and6F-2. The remaining portions of the patterned inner spacer layer134′ form inner spacers636, as shown inFIG.6F-1.

In some embodiments, the etching process is an isotropic etching process. The etching process may include a dry etching process, a wet etching process, or a combination thereof. The etching process may be carefully controlled so that it does not substantially etch the gate spacers126′ and128′ or the spacer structures129. The spacer structures129may thus have sufficient height, which facilitates the subsequent formation of epitaxial structures. The nearby epitaxial structures may be prevented from being merged together due to the spacer structures129.

The inner spacers636cover the edges of the semiconductor layers102aand102b. The inner spacers636may be used to prevent subsequently formed epitaxial structures (that function as, for example, source/drain structures) from being damaged during a subsequent process for removing the semiconductor layers102aand102b.

The patterned inner spacer layer134′ has openings that expose the bottoms of the recesses130. The etching time for the patterned inner spacer layer134′ may be significantly reduced. The laterally etch of the patterned inner spacer layer134′ may thus be minimized since the etching time is reduced. The dishing degree of the inner spacers636may thus be minimized, which ensures the quality of the inner spacers636. The risk of short circuiting between the gate electrode and the source/drain structures is substantially reduced. In some embodiments, the edges of the inner spacers636and the semiconductor layers104a-104bare substantially aligned with each other.

In some embodiments, the inner spacers636are made of a low-k material that has a lower dielectric constant than that of silicon oxide. In these cases, the inner spacers636may also be used to reduce parasitic capacitance between the subsequently formed source/drain structures and the gate stacks. As a result, the operation speed of the semiconductor device structure may be improved.

As shown inFIGS.6G-1and6G-2, similar to the embodiments illustrated inFIGS.2J-1and2J-2, the isolation films206are formed, in accordance with some embodiments.

Afterwards, the processes that is the same as or similar to those illustrated inFIGS.2K-1to2N-1and2K-2to2N-2are performed. As a result, the structure shown inFIGS.6H-1and6H-2is formed, in accordance with some embodiments.

Many variations and/modifications can be made to embodiments of the disclosure. In some embodiments, the isolation films206are selectively removed before the formation of the epitaxial structures.FIG.7is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure, in accordance with some embodiments.

In some embodiments, multiple epitaxial structures738N that are n-type doped are formed in a first region of the semiconductor device structure, as shown in the left portion ofFIG.7. Multiple epitaxial structures738P that are p-type doped are formed in a second region of the semiconductor device structure, as shown in the right portion ofFIG.7. The epitaxial structures738N and738P may be sequentially formed. The material and formation method of the epitaxial structures738N may be the same as or similar to the epitaxial structures138that are n-type doped as illustrated inFIGS.2K-1and2K-2. The material and formation method of the epitaxial structures738P may be the same as or similar to the epitaxial structures138that are p-type doped as illustrated inFIGS.2K-1and2K-2.

In some embodiments, each of the epitaxial structures738N is separated from the semiconductor isolation structure137thereunder by the isolation film236thereunder. The isolation film236therebetween may prevent or reduce leakage current from the epitaxial structure738N.

In some embodiments, the isolation films236are selectively removed. No isolation film is formed in the second region where the epitaxial structures738P are formed. In some embodiments, the epitaxial structures738P are in direct contact with the semiconductor isolation structures236. Due to the lattice mismatch between the epitaxial structures738P and the semiconductor isolation structures137, higher stain may be applied on the semiconductor nanostructures104a′-104b′. The performance and reliability of the semiconductor device structure may be improved.

Embodiments of the disclosure form a semiconductor device structure with inner spacers between the epitaxial structures and the semiconductor nanostructures. The formation of the inner spacers involves one or more isotropic etching process. Since no anisotropic etching process is used during the formation of the inner spacers, the spacer structures designed for confining the growth of the epitaxial structures are substantially not damaged. The spacer structures may thus have sufficient height, which facilitates the formation of epitaxial structures. The nearby epitaxial structures may be prevented from being merged together due to the spacer structures. The performance and reliability of the semiconductor device structure are greatly improved.

In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a substrate, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a dummy gate stack wrapped around the fin structure and partially removing the fin structure to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers. The method further includes forming first inner spacers covering the side surfaces of the sacrificial layers and forming a semiconductor isolation structure over a bottom of the recess. In addition, the method includes forming second inner spacers over the first inner spacers and forming an isolation film over the semiconductor isolation structure. The method includes forming an epitaxial structure on the side surfaces of the semiconductor layers. The method also includes removing the dummy gate stack and the sacrificial layers to release multiple semiconductor nanostructures constructed by remaining portions of the semiconductor layers. The method further includes forming a metal gate stack wrapped around the semiconductor nanostructures.

In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a substrate, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes forming a gate stack wrapped around the fin structure and forming a spacer layer extending along sidewalls and tops of the fin structure and the gate stack. The method further includes partially removing the fin structure and the spacer layer to form a recess exposing side surfaces of the semiconductor layers and the sacrificial layers. A remaining portion of the spacer layer forms a gate spacer along the sidewall of the gate stack. In addition, the method includes forming an inner spacer layer along a sidewall and a bottom of the recess and partially removing the inner spacer layer using an isotropic etching process. Remaining portions of the inner spacer layers form multiple inner spacers, and the isotropic etching process does not substantially etch the gate spacer. The method includes forming an epitaxial structure in the recess.

In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes multiple semiconductor nanostructures over a substrate. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure. Each of the semiconductor nanostructures is between the first epitaxial structure and the second epitaxial structure. The semiconductor device structure further includes a gate stack wrapped around each of the semiconductor nanostructures. In addition, the semiconductor device structure includes multiple inner spacers, and each of the inner spacers electrically isolates the gate stack from the first epitaxial structure and the second epitaxial structure. The semiconductor device structure includes a third epitaxial structure between the first epitaxial structure and the substrate, and the third epitaxial structure is undoped. The semiconductor device structure also includes an isolation film between the first epitaxial structure and the third epitaxial structure.