SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

A method for forming a semiconductor device is provided. The method includes forming a device layer over a device substrate and forming a front-side interconnect structure over the device layer. The method also includes forming a bevel oxide over an edge portion of the device substrate, an edge portion of the device layer, and an edge portion of the front-side interconnect structure. The method further includes forming an oxide layer over the device layer, the front-side interconnect structure, and the bevel oxide, polishing the bevel oxide and the oxide layer until a top surface of the bevel oxide is substantially level with a top surface of the oxide layer, and attaching a carrier substrate to the bevel oxide and the oxide layer.

BACKGROUND

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. The individual dies are typically packaged separately. A package not only provides protection for semiconductor devices from environmental contaminants, but also provides a connection interface for the semiconductor devices packaged therein.

Three dimensional integrated circuits (3DICs) are a recent development in semiconductor packaging in which multiple semiconductor dies are stacked upon one another, such as package-on-package (PoP) and system-in-package (SiP) packaging techniques. Some 3DICs are prepared by placing dies over dies on a semiconductor wafer level. 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked dies, as examples. However, there are many challenges related to 3DICs.

DETAILED DESCRIPTION

Typically, a semiconductor device has a central region and a bevel region close to its edge. Bevel defects such as peeling (also known as delamination) or deformation may occur in the bevel region because of the curved edge. To eliminate the bevel defects, a bevel oxide is deposited in the bevel region. However, in current manufacturing processes, when attaching a carrier substrate to the semiconductor device, direct bonding between the carrier substrate and the bevel oxide is not preferred. In particular, in current manufacturing processes, a bonding layer that can be wrapped around the bevel oxide and that provides bonding with the carrier substrate is needed. What is needed, therefore, is a combination of manufacturing processes for forming the bonding layer (such as a deposition process and a planarization process). The bonding layer that wraps the bevel oxide may increase the overall thickness of the semiconductor device and manufacturing costs. Some embodiments of the present disclosure provide direct bonding between the carrier substrate and the bevel oxide, which may reduce the thickness of the semiconductor device and simplify the manufacturing processes.

FIG.1illustrates a top view of a device substrate102and a device layer104formed thereon in accordance with some embodiments. The device substrate102may be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, the device substrate102may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Elementary semiconductor materials may include, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP. The device substrate102may include a central region and a bevel region that is closer to its edge. The device layer104may include various layers formed by various manufacturing processes, e.g., front end-of-line (FEOL) processes. During these manufacturing processes, a device recessed portion106may be inevitably formed in the bevel region of the device substrate102.

The device layer104may include various device components/features, such as doped wells (e.g., n-wells and/or p-wells), isolation features (e.g., shallow trench isolation (STI) structures and/or other suitable isolation structures), gates (e.g., a gate stack having a gate electrode and a gate dielectric), gate spacers along sidewalls of the gates, source/drains (e.g., epitaxial source/drains), other suitable device components and/or device features, or a combination thereof.

In some embodiments, the device layer104include a planar transistor, where a channel of the planar transistor is formed in the semiconductor substrate between respective source/drains and a respective gate is disposed on the channel (e.g., on a portion of the semiconductor substrate in which the channel is formed). In some embodiments, the device layer104include a non-planar transistor having a channel formed in a semiconductor fin that extends from the semiconductor substrate and between respective source/drains on/in the semiconductor fin, where a respective gate is disposed on and wraps the channel of the semiconductor fin (i.e., the non-planar transistor is a fin-like field effect transistor (FinFET)). In some embodiments, the device layer104include a non-planar transistor having channels formed in semiconductor layers suspended over the device substrate102and extending between respective source/drains, where a respective gate is disposed on and at least partially surrounds the channels (i.e., the non-planar transistor is a gate-all-around (GAA) transistor and/or a fork-sheet transistor). The various transistors can be configured as planar transistors or non-planar transistors depending on design requirements.

The device substrate102and/or the device layer104may include various passive electronic devices and active electronic devices, such as resistors, capacitors, inductors, diodes, p-type FETs (PFETs), n-type FETs (NFETs), metal-oxide semiconductor (MOS) FETs (MOSFETs), complementary MOS (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high voltage transistors, high frequency transistors, other suitable components, or a combination thereof. The various electronic devices can be configured to provide functionally distinct regions of an IC, such as a logic region (i.e., a core region), a memory region, an analog region, a peripheral region (e.g., an input/output (I/O) region), a dummy region, other suitable region, or a combination thereof. The logic region may be configured with standard cells, each of which can provide a logic device and/or a logic function, such as an inverter, an AND gate, an NAND gate, an OR gate, an NOR gate, a NOT gate, an XOR gate, an XNOR gate, other suitable logic device, or a combination thereof. The memory region may be configured with memory cells, each of which can provide a storage device and/or storage function, such as flash memory, non-volatile random-access memory (NVRAM), static random-access memory (SRAM), dynamic random-access memory (DRAM), other volatile memory, other non-volatile memory, other suitable memory, or a combination thereof. In some embodiments, memory cells and/or logic cells include transistors and interconnect structures that combine to provide storage devices/functions and logic devices/functions, respectively, of a chip.

FIG.2AtoFIG.2Jillustrate cross-sectional views of forming a semiconductor device200in accordance with some embodiments. Please refer toFIG.2A. The device substrate102may have a front-side102_FS and a back-side102_BS that is opposite to the front-side102_FS. The device layer104is formed over the front-side102_FS of the device substrate102. The device layer104may include multilayers made of multiple dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or other applicable low-k dielectric materials. The device layer104may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable processes.

The device layer104may include a plurality of electrical devices110formed therein. In other words, the electrical devices110may be formed over the front-side surface102_FS of the device substrate102. Each electrical device110may be a transistor, such as a nanostructure transistor (e.g., a nanosheet transistor, a nanowire transistor, a multi-bridge channel transistor, a nano-ribbon FET, or a gate all around (GAA) transistor). Each electrical device110may include a plurality of source/drain structures112, a plurality of gate structures114, a plurality of channel layers116, a plurality of gate spacers118, and a plurality of inner spacers120.

The source/drain structures112are attached to the opposite sides of the channel layers116in the X-direction. The source/drain structures112may refer to a source or a drain, individually or collectively, depending upon the context. The gate structures114wrap around the channel layers116and extend along the Y-direction. The channel layers116are suspended over the device substrate102in the Z-direction. In some embodiments, the gate spacers118and the inner spacers120are formed from a spacer layer. The spacer layer may include one or more dielectric materials. The dielectric materials may include silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), and/or a combination thereof. The spacer layer may be etched to form the gate spacers118and the inner spacers120.

In some embodiments, a dummy gate structure may be formed across a plurality of fin structure to define the channel regions of the resulting transistors (e.g., the electrical devices110). The gate spacers118may be configured to separate source/drain structures112from the dummy gate structure. The inner spacers120may be configured to separate the source/drain structures112and the gate structures114.

In addition, a plurality of source/drain contacts122may be formed in the device layer104. The source/drain contacts122are connected to the source/drain structures112of the electrical device110. In some embodiments, the source/drain contacts122may be made of a conductive material including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other applicable conductive materials, or a combination thereof.

The source/drain contacts122may further include a liner and/or a barrier layer. For example, a liner (not shown) may be formed on the sidewalls and bottom of the contact trench. The liner may be made of silicon nitride, although any other applicable dielectric may be used as an alternative. The liner may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable processes. The barrier layer (not shown) may be formed over the liner (if present) and may cover the sidewalls and bottom of the opening. The barrier layer may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable processes. The barrier layer may be made of tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, may also be used.

After the electrical devices110are formed, a front-side interconnect structure130is formed over the device layer104, as shown inFIG.2Bin accordance with some embodiments. In particular, the front-side interconnect structure130is formed over the front-side surface of the electrical devices110, and the device substrate102is located on the back-side surface of the electrical devices110. In some embodiments, the width of the top surface of the front-side interconnect structure130is different from the width of the bottom surface of the front-side interconnect structure130because the edges of the front-side interconnect structure130are affected by the bevel region of the device substrate102during the manufacturing processes. The front-side interconnect structure130may be formed by a damascene process, such as a single damascene process, a dual damascene process, combinations thereof, or the like. In some embodiments, the front-side interconnect structure130includes a plurality of conductive structures132(e.g., vias and metal lines) formed in a plurality of dielectric layers134. In some embodiments, the conductive structures132are electrically connected to the source/drain contacts122.

The dielectric layers134may include dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and/or other applicable low-k dielectric materials. The dielectric layer134may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable processes.

In some embodiments, the front-side interconnect structure130further includes a plurality of contact plugs136landing on the gate structures114and electrically connected to the gate structures114. In some embodiments, the conductive structures132and the contact plugs136are made of a conductive material including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other applicable conductive materials, or a combination thereof. In some embodiments, the conductive structures132and the contact plugs136may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable processes.

After the front-side interconnect structure130is formed, a bevel oxide140may be formed over the edge portion of the device substrate102, the edge portion of the device layer104, and the edge portion of the front-side interconnect structure130, as shown inFIG.2Cin accordance with some embodiments. The bevel oxide140is mainly formed in the bevel region. In some embodiments, the bevel oxide140may include dielectric materials. In some embodiments, The bevel oxide140may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable processes.

In some embodiments, the formation of the bevel oxide140includes filling the device recessed portion106of the device substrate102with the bevel oxide140. The formation of the bevel oxide140is affected by the topography of the underlying structures, and thus a bevel oxide recessed portion142is formed in the bevel oxide140. The bevel oxide recessed portion142at least partially overlaps the device recessed portion106vertically. In some embodiments, the thickness of the bevel oxide recessed portion142is different from the thickness of the device recessed portion106.

After the bevel oxide140is formed, an oxide layer150may be formed over the device layer104, the front-side interconnect structure130, and the bevel oxide140, as shown inFIG.2Din accordance with some embodiments. In some embodiments, the oxide layer150includes silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane (TEOS), TEOS formed oxide, or the like. In some embodiments, the oxide layer150and the bevel oxide140are made of different dielectric materials. The oxide layer150may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable processes.

In some embodiments, the formation of the oxide layer150includes depositing the oxide layer150until the thickness150T1of the portion of the oxide layer150that is not over the bevel oxide140is about 1000 nm. In some embodiments, the formation of the oxide layer150includes filling the bevel oxide recessed portion142with the oxide layer150. In other words, the oxide layer150includes an oxide layer extending portion154extending into the bevel oxide recessed portion142. The formation of the oxide layer150is affected by the topography of the underlying structures, and thus an oxide layer recessed portion152in the oxide layer150is formed. The oxide layer recessed portion152at least partially overlaps the bevel oxide recessed portion142and the device recessed portion106vertically, and the bevel oxide recessed portion142is between the device recessed portion106and the oxide layer recessed portion152.

After the oxide layer150is deposited to a predetermined thickness, the bevel oxide140and the oxide layer150may be partially removed until the top surface of the bevel oxide140is substantially level with the top surface of the oxide layer150, as shown inFIG.2Ein accordance with some embodiments. The bevel oxide140and the oxide layer150may be partially removed using a planarization process such as chemical mechanical polishing (CMP) process or any other applicable planarization process. In some embodiments, the polishing rate of the oxide layer150is different from the polishing rate of the bevel oxide140during the CMP process.

The polishing of the bevel oxide140and the oxide layer150reduces the thickness of the bevel oxide140and the thickness of the oxide layer150along the Z-direction. In some embodiments, the polishing of the bevel oxide140includes exposing the oxide layer extending portion154of the oxide layer150. In some embodiments, the polishing of the oxide layer150includes polishing the oxide layer150until the thickness150T2of the portion of the oxide layer150that is not over the bevel oxide140is in a range from about 200 nm to about 300 nm.

After the bevel oxide140and the oxide layer150are polished, the edge portion of the bevel oxide140, the edge portion of the front-side interconnect structure130, and the edge portion of the device substrate102are trimmed off, as shown inFIG.2Fin accordance with some embodiments. In some embodiments, the trim of the edge portion of the bevel oxide140includes removing the portion of the bevel oxide140where the bevel oxide recessed portion142is located. In some embodiments the width of the top surface of the device substrate102is less than the width of the bottom surface of the device substrate102after the trim of the bevel oxide140, the front-side interconnect structure130, and the device substrate102. In some embodiments, the width102D of the portion that is trimmed off (i.e., substantially the same as the difference between the width of the top surface of the device substrate102and the width of the bottom surface of the device substrate102) is in a range from about 0.5 mm to about 5 mm.

Next, a carrier substrate160is attached to the bevel oxide140and the oxide layer150to form an intermediate structure170, as shown inFIG.2Gin accordance with some embodiments. The attachment of the carrier substrate160may form covalent bonds between the carrier substrate160and the bevel oxide140and covalent bonds between the carrier substrate160and the oxide layer150. In some embodiments, the bonding process may further include applying a surface treatment to one or more of the bevel oxide140and the oxide layer150. For example, the surface treatment may include a plasma treatment performed in vacuum environment. After the plasma treatment, the surface treatment may further include a cleaning process (e.g., rinse with deionized water) applied to one or more of the bevel oxide140and the oxide layer150. The carrier substrate160is then aligned with the device substrate102, and the carrier substrate160is pressed to initiate a pre-bonding process. For example, a push pin may extend through a carrier substrate chuck (not specifically illustrated) to bend the central region of the carrier substrate160. By bending the carrier substrate160, physical contact is initially made in the central region of the carrier substrate160. The carrier substrate chuck may then be moved further downward to bond a growing concentric circle until the bevel region of the carrier substrate160is bonded with the bevel oxide140.

As a result, a bonded interface is formed between the carrier substrate160and bevel oxide140and the oxide layer150. Therefore, the carrier substrate160may be bonded with the bevel oxide140and the oxide layer150together in a stable way, and the performance of the resulting semiconductor device200may be improved. Due to the trim off of the bevel oxide140, the front-side interconnect structure130, and the device substrate102before the attachment of the carrier substrate160to the bevel oxide140and the oxide layer150, the possibility of fracture and breakage occurred in the intermediate structure170may be further reduced.

After the intermediate structure170is formed, the intermediate structure170is flipped over, and a thinning process is performed on the intermediate structure170, as shown inFIG.2Hin accordance with some embodiments. In other words, the device substrate102is flipped over and thinned. The thinning process may be a grinding process, a planarization process (e.g., CMP), an etching process, other suitable process, or a combination thereof. The thinning process includes removing at least part of the device substrate102, and the thinning process is applied to the back-side102_BS of the device substrate102. In some embodiments, a grinding process or CMP is performed to remove a majority of the device substrate102and then followed by a suitable etch-back process to remove either a remainder of the device substrate102or to form openings (not specifically illustrated) in the device substrate102to expose certain portions of the electrical devices110in the device layer104.

Then, a back-side interconnect structure180is formed, as shown inFIG.2Iin accordance with some embodiments. The back-side interconnect structure180may be able to decouple I/O and power wiring by power rails on the back-side surface, addressing challenges like elevated via resistances in back-end-of-line (BEOL) processes. This may enhance performance of transistors and reduce power consumption. Also, power wiring on back-side surface eliminates some potential interference between data and power connections. In some embodiments, the back-side interconnect structure180includes a dielectric layer182, a plurality of back-side vias184, a plurality of back-side through vias186.

In some embodiments, before forming the back-side vias184, back-side vias trenches are formed through the dielectric layer182and the device substrate102, so that the bottom portions of the source/drain structures112are exposed. In some embodiments, the bottom portions of the source/drain structures112are also slightly removed. Then, a plurality of back-side silicide layers (not shown) are formed over the exposed source/drain structures112, and the back-side vias184are formed over the back-side silicide layers. In some embodiments, the back-side silicide layers are formed by forming metal layers over the exposed surfaces of the source/drain structures112and annealing the metal layers, so the metal layers react with the source/drain structures112to form the back-side silicide layers. The unreacted metal layers are removed after the back-side silicide layers are formed in accordance with some embodiments. In some embodiments, the back-side silicide layers are N-type epi silicide such as TiSi, CrSi, TaSi, MoSi, ZrSi, HfSi, ScSi, Ysi, HoSi, TbSI, GdSi, LuSi, DySi, ErSi, YbSi, or the like. In some embodiments, the back-side silicide layers are P-type epi silicide such as NiSi, CoSi, MnSi, Wsi, FeSi, RhSi, PdSi, RuSi, PtSi, IrSi, OsSi, or the like. After the back-side silicide layers are formed, a conductive filling layer is formed to fill the back-side via trenches, and a polishing process is performed to form the back-side vias184.

In some embodiments, the back-side through vias186are formed through the dielectric layer182, the device substrate102, and the device layer104. In addition, the back-side through vias186are electrically connected to the conductive structures132in the front-side interconnect structure130. In some embodiments, the back-side vias184and the back-side through vias186are made of a conductive material including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other applicable conductive materials, or a combination thereof. The back-side vias184and the back-side through vias186may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable processes.

A liner layer (not shown) and/or a barrier layer (not shown) may be formed on the sidewalls of the back-side vias184and the back-side through vias186. For example, the liner layer may include silicon nitride, although any other applicable dielectric may be used as an alternative. For example, the barrier layer may include tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, may also be used. The liner layer and the barrier layers may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or another applicable processes. In some embodiments, each of the back-side vias184and the back-side through vias186has a width in a range from about 15 nm to about 30 nm in the X-direction. In some embodiments, each of the back-side vias184and the back-side through vias186has a width in a range from about 15 nm to about 30 nm in the Y-direction. In some other embodiments, the device substrate102is completely removed after the back-side vias184and the back-side through vias186are formed.

The back-side interconnect structure180may further include a dielectric layer188and a plurality of back-side metal pads190. The dielectric layer188is formed over the back-side surface of the electrical devices110, and the back-side metal pads190are formed in the dielectric layer188, as shown inFIG.2Jin accordance with some embodiments. In some embodiments, the back-side metal pads190are metal lines embedded in the dielectric layer188. In some embodiments, the dielectric layer188includes multiple layers made of low k dielectric materials having a k value lower than 7. In some embodiments, the dielectric layer188is made of SiO2, SiN, SiCN, SiOC, SiOCN, or the like. The dielectric layer188may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable processes.

In some embodiments, the back-side metal pads190are made of a conductive material including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other applicable conductive materials, or a combination thereof. The back-side metal pads190may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable processes.

Although not specifically illustrated, conductive connectors may be formed. The conductive connectors may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel/electroless palladium/immersion gold technique (ENEPIG) formed bumps, or the like. The conductive connectors may include a conductive material including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiSi), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other applicable conductive materials, or a combination thereof. In some embodiments, the conductive connectors are formed by initially forming a layer of solder through evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into desired bump shapes. In another embodiments, the conductive connectors include metal pillars (such as copper pillars) formed by sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on the top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process.

To sum up, a semiconductor device200includes a device layer104, a front-side interconnect structure130, a back-side interconnect structure180, a bevel oxide140, and an oxide layer150is provided. The front-side interconnect structure130is formed over the front-side surface of the device layer104. The back-side interconnect structure180is formed over the back-side surface of the device layer104. In other words, the device layer104is located between the front-side interconnect structure130and the back-side interconnect structure180. Accordingly, the electrical signals on the back-side surface of the device layer104may be transferred to the elements formed on the front-side surface of the device layer104via the back-side interconnect structure180and the front-side interconnect structure130.

The bevel oxide140covers the bevel region of the front-side interconnect structure130. The oxide layer150covers the central region of the front-side interconnect structure130. In some embodiments, the width of the bevel oxide140is less than the width of the oxide layer150. In some embodiments, the bevel oxide140has a non-uniform thickness. For example, the bevel oxide140may have a maximum thickness140T1and a minimum thickness140T2different from the maximum thickness140T1. In some embodiments, the oxide layer150may have a uniform thickness. For example, the oxide layer150may have substantially the same maximum thickness and minimum thickness denoted as150T.

In some embodiments, the maximum thickness140T1of the bevel oxide140is greater than the maximum thickness150T of the oxide layer150. In some embodiments, the minimum thickness140T2of the bevel oxide140is substantially the same as the maximum thickness150T of the oxide layer150. In some embodiments, the maximum thickness150T of the oxide layer150is in a range from about 200 nm to about 300 nm. The oxide layer150can improve thermal effects and possess good thermal stability due to its relatively small thickness. This also effectively reduces the overall thickness of the semiconductor device200.

The bevel oxide140may provide protection on the bevel region of the semiconductor device200. The bevel oxide140may also provide sufficient mechanical support for direct bonding with the carrier substrate160. In some embodiments, no bubble is generated in the semiconductor device200. The direct bonding between the carrier substrate160and the bevel oxide140reduces the thickness of the semiconductor device200, saves manufacturing costs, and simplifies manufacturing processes because there is no layer wrapping the bevel oxide140. Furthermore, due to the reduced thickness of the semiconductor device200, thermal effects are improved, yield is increased, and the manufacturing processes are optimized.

FIG.3AtoFIG.3Dillustrate cross-sectional views of forming an intermediate structure170′ in accordance with some embodiments. The method embodiments illustrated inFIG.2AtoFIG.2Jand the method embodiments illustrated inFIG.3AtoFIG.3Dare performed in a different order. In addition, the shape of a device recessed portion106′ illustrated inFIG.3AtoFIG.3Dis different from the shape of the device recessed portion106illustrated inFIG.2AtoFIG.2J. The device recessed portion106is trapezoid-shaped, and the device recessed portion106′ is rectangular, but the actual shape of the device recessed portion is not limited thereto. The actual shape of the device recessed portion may be affected by the manufacturing processes. Furthermore, the shape of a front-side interconnect structure130′ illustrated inFIG.3AtoFIG.3Dis different from the shape of the front-side interconnect structure130′ illustrated inFIG.2AtoFIG.2J. The top surface of the front-side interconnect structure130′ and the bottom surface of the front-side interconnect structure130′ have substantially the same width.

An oxide layer150′ is formed over the device substrate102, the device layer104, and the front-side interconnect structure130, as shown inFIG.3Ain accordance with some embodiments. In some embodiments, the formation of the oxide layer150′ includes filling the device recessed portion106′ with the oxide layer150′. The formation of the oxide layer150′ is affected by the topography of the underlying structures, and thus an oxide layer recessed portion152′ is formed in the oxide layer150′. In some embodiments, the formation of the oxide layer150′ includes depositing the oxide layer150until the thickness150′T1of the portion of the oxide layer150′ that is directly over the front-side interconnect structure130is about 1000 nm.

Then, a bevel oxide140′ is formed over the edge portion of the oxide layer150′, the edge portion of the front-side interconnect structure130′, the edge portion of the device substrate102, as shown inFIG.3Bin accordance with some embodiments. In some embodiments, the formation of the bevel oxide140′ includes filling the oxide layer recessed portion152′ with the bevel oxide140′. In other words, the bevel oxide140′ includes a bevel oxide extending portion144′ extending into the oxide layer recessed portion152′. The formation of the bevel oxide140′ is affected by the topography of the underlying structures, and thus a bevel oxide recessed portion142′ is formed in the bevel oxide140′. The device recessed portion106′ at least partially overlaps the oxide layer recessed portion152′ and the bevel oxide recessed portion142′ vertically, and the oxide layer recessed portion152′ is between the device recessed portion106′ and the bevel oxide recessed portion142′. In some embodiments, the thickness of the bevel oxide recessed portion142′ is different from the thickness of the oxide layer recessed portion152′.

Then, the oxide layer150′ and the bevel oxide140′ are polished until the top surface of the oxide layer150′ is substantially level with the top surface of the bevel oxide140′, as shown inFIG.3Cin accordance with some embodiments. The polishing of the oxide layer150′ and the bevel oxide140′ reduces the thickness of the oxide layer150′ and the thickness of the bevel oxide140′ along the Z-direction. In some embodiments, the polishing of the oxide layer150′ and the bevel oxide140′ includes exposing the bevel oxide extending portion144′. In some embodiments, the polishing of the oxide layer150′ includes polishing the oxide layer150′ until the thickness150′T2of the portion that is directly over the front-side interconnect structure130is in a range from about 200 nm to about 300 nm.

After the oxide layer150′ and the bevel oxide140′ are polished to a desirable thickness, a carrier substrate160is then attached to the oxide layer150′ and the bevel oxide140′ to form the intermediate structure170′, as shown inFIG.3Din accordance with some embodiments. Furthermore, a seal192′ may also be added to the intermediate structure170′. In some embodiments, the seal192′ is formed between the carrier substrate160and the bevel oxide140′ to enhance the bonding therebetween. It should be noted that, the aforementioned processes such as a thinning process, a trimming process, or the like, may be further performed to the intermediate structure170′ to obtain a semiconductor device.

As described above, a semiconductor device and method for forming the same are provided. The semiconductor device may include a device layer, a front-side interconnect structure, a back-side interconnect structure, a bevel oxide, and an oxide layer. The front-side interconnect structure is formed over the front-side surface of the device layer. The back-side interconnect structure is formed over the back-side surface of the device layer. In other words, the device layer is located between the front-side interconnect structure and the back-side interconnect structure. Accordingly, the electrical signals on the back-side surface of the device layer may be transferred to the elements formed on the front-side surface of the device layer via the back-side interconnect structure and the front-side interconnect structure. The bevel oxide covers the bevel region of the front-side interconnect structure. The oxide layer covers the central region of the front-side interconnect structure.

The bevel oxide may provide protection on the bevel region of the semiconductor device. The bevel oxide may also provide sufficient mechanical support for direct bonding with the carrier substrate. The oxide layer can improve thermal effects and possess good thermal stability due to its relatively small thickness. This also effectively reduces the overall thickness of the semiconductor device. In some embodiments, no bubble is generated in the semiconductor device. The direct bonding between the carrier substrate and the bevel oxide reduces the thickness of the semiconductor device, saves manufacturing costs, and simplifies manufacturing processes because there is no layer wrapping the bevel oxide. Furthermore, due to the reduced thickness of the semiconductor device, thermal effects are improved, yield is increased, and the manufacturing processes are optimized.

According to some embodiments, a method for forming a semiconductor device is provided. The method includes forming a device layer over a device substrate and forming a front-side interconnect structure over the device layer. The method also includes forming a bevel oxide over an edge portion of the device substrate, an edge portion of the device layer, and an edge portion of the front-side interconnect structure. The method further includes forming an oxide layer over the device layer, the front-side interconnect structure, and the bevel oxide, polishing the bevel oxide and the oxide layer until a top surface of the bevel oxide is substantially level with a top surface of the oxide layer, and attaching a carrier substrate to the bevel oxide and the oxide layer.

In some embodiments, the method further includes flipping over the device substrate and thinning the device substrate. In some embodiments, the method further includes forming a back-side interconnect structure over the device layer, wherein the back-side interconnect structures includes a plurality of back-side vias, a plurality of back-side through vias, and a plurality of back-side metal pads. In some embodiments, the bevel oxide and the oxide layer are polished by performing a chemical mechanical polishing process, and a polishing rate of the oxide layer is different from a polishing rate of the bevel oxide during the chemical mechanical polishing process.

In some embodiments, the bevel oxide has a bevel oxide recessed portion filled with the oxide layer before the bevel oxide and the oxide layer are polished. In some embodiments, the oxide layer has an oxide layer recessed portion vertically overlapping the bevel oxide recessed portion before the bevel oxide and the oxide layer are polished. In some embodiments, the oxide layer has an oxide layer extending portion extending into the bevel oxide recessed portion, and the extending portion is exposed after the bevel oxide and the oxide layer are polished.

In some embodiments, the method further includes trimming the bevel oxide, the front-side interconnect structure, and the device substrate before the carrier substrate is attached to the bevel oxide and the oxide layer. In some embodiments, a width of a top surface of the device substrate is less than a width of a bottom surface of the device substrate after the bevel oxide, the front-side interconnect structure, and the device substrate are trimmed. In some embodiments, a width of a top surface of the front-side interconnect structure is different from a width of a bottom surface of the front-side interconnect structure.

According to some embodiments, a method for forming a semiconductor device is provided. The method includes forming transistors over a front-side surface of a device substrate and forming a first interconnect structure over the transistors. The method also includes forming an oxide layer and a bevel oxide over the device substrate and partially removing the oxide layer and the bevel oxide until a top surface of the oxide layer is substantially level with a top surface of the bevel oxide. The method further includes attaching a carrier substrate to the oxide layer and the bevel oxide and polishing a back-side surface of the device substrate. The device substrate has a device recessed portion formed on the front-side surface.

In some embodiments, the oxide layer has an oxide layer recessed portion, the bevel oxide has a bevel oxide recessed portion, and the device recessed portion, the oxide layer recessed portion, and the bevel oxide recessed portion at least partially overlap each other vertically. In some embodiments, the bevel oxide recessed portion is between the oxide layer recessed portion and the device recessed portion. In some embodiments, the oxide layer recessed portion is between the bevel oxide recessed portion and the device recessed portion. In some embodiments, the method further includes forming a seal between the carrier substrate and the bevel oxide.

According to some embodiments a semiconductor device is provided. The semiconductor device includes a device layer, a front-side interconnect structure, a back-side interconnect structure, an oxide layer, and a bevel oxide. The front-side interconnect structure is formed over a front-side surface of the device layer. The back-side interconnect structure is formed over a back-side surface of the device layer. The oxide layer covers a central region of the front-side interconnect structure. The bevel oxide covers a bevel region of the front-side interconnect structure. The oxide layer and the bevel oxide are made of different dielectric materials.

In some embodiments, a width of the bevel oxide is less than a width of the oxide layer. In some embodiments, a maximum thickness of the bevel oxide is greater than a maximum thickness of the oxide layer. In some embodiments, a minimum thickness of the bevel oxide is substantially the same as the maximum thickness of the oxide layer. In some embodiments, a maximum thickness of the oxide layer is in a range from about 200 nm to about 300 nm.