Serial communication device, method thereof and communication system using the same

A compact serial communication device is disclosed that is formed from simplified circuits on a master side and a slave side and does not need a synchronous signal and a switching unit for switching transmission and reception operations, and is able to reduce load of the slave side. The master transmission/reception circuit outputs a serial data signal DATA to a transmission path with the serial data signal DATA being generated by superposing a low level superposition pulse on a clock signal, when the clock signal is at the high level, according to an output data signal to be output to the slave transmission/reception circuits; the slave transmission/reception circuits superposes a high level superposition pulse on the serial data signal DATA input from the transmission path according to an output data signal to be output to the master transmission/reception circuit when the clock signal is at the low level.

TECHNICAL FIELD

The present invention relates to a serial communication device, a communication method of the device, and a communication system using the communication device, and particularly, a serial communication device performing serial communication by means of half-duplex communication, a communication method of the serial communication device, and a communication system using the serial communication device.

BACKGROUND ART

It is known that there are various methods of transmitting serial signals in serial communications.FIG. 17throughFIG. 20illustrate typical ones of such methods.

FIG. 17exemplifies a method of the related art for transmitting serial signals in serial communications.

InFIG. 17, a data signal SdA is a common data signal, in which data values are directly represented by signal levels, and data values are extracted from the data signal SdA by using a synchronization signal SaA, which delimits different data. In this method, two signals, such as the data signal SdA and the synchronization signal SaA are used.

FIG. 18exemplifies another method of the related art for transmitting serial signals in serial communications.

InFIG. 18, a data signal SdB is a pulse width modulation signal, in which signal intervals are constant, and pulse widths differ between when the data value is “0” and when the data value is “1”. With this method, although the code interval thereof is a problem, it is possible to perform asynchronous operations.

FIG. 19exemplifies another method of the related art for transmitting serial signals in serial communications.

InFIG. 19, a data signal SdC is a pulse position modulation signal in which pulse positions change along time, and data are sampled with a synchronization signal SaC serving as a time reference.

FIG. 20exemplifies still another method of the related art for transmitting serial signals in serial communications.

InFIG. 20, a data signal SdD is a signal used in an infrared remote controller, and is obtained by combining the pulse width modulation and the pulse position modulation signal. However, because data intervals are not constant in the data signal SdD, the data signal SdD is an asynchronous signal, therefore, a synchronization signal is not needed.

FIG. 21is a block diagram illustrating a serial communication device of the related art for performing half-duplex communications.

InFIG. 21, a serial communication device200includes a master transmission/reception circuit201and a slave transmission/reception circuit205. The master transmission/reception circuit201includes a master transmission circuit202, a master reception circuit203, and a master switching section204for transmission authority control. Similarly, the slave transmission/reception circuit205includes a slave transmission circuit206, a slave reception circuit207, and a slave switching section208for transmission authority control. Basically, the master transmission circuit202is the same as the slave transmission circuit206, and the master reception circuit203is the same as the slave reception circuit207.

Here, when the transmission authority is on the master transmission/reception circuit201, data are transmitted from the master transmission circuit202of the master transmission/reception circuit201to the slave reception circuit207of the slave transmission/reception circuit205. Meanwhile, if the transmission authority is transferred to the slave transmission/reception circuit205, data are transmitted from the slave transmission circuit206of the slave transmission/reception circuit205to the master reception circuit203of the master transmission/reception circuit201.

However, as described above, in the related art, a synchronous signal is required. Even if the synchronous signal is not used, the circuits for generating data signals from data or extracting the data from the data signals are complicated. Further, in order to perform the half-duplex communication, the same circuit as that on the master side is required on the slave side, and switching units for switching between transmission operations and reception operations are needed. For this reason, the scale of the circuit is large, and space and cost of the circuit increase.

DISCLOSURE OF THE INVENTION

It is a general object of the present invention to solve one or more of the problems of the related art.

A specific object of the present invention is to provide a compact and inexpensive serial communication device that is formed from simplified circuits on a master side and a slave side, does not use a synchronous signal and a unit for switching transmission operations and reception operations, and is able to reduce the workload of the slave side; and to provide a communication method of the serial communication device, and a communication system using the serial communication device.

According to a first aspect of the present invention, there is provided a serial communication device that includes a first transmission/reception circuit and at least one second transmission/reception circuit connected with the first transmission/reception circuit in a transmission path, and performs serial communication by half-duplex communication between the first transmission/reception circuit and the second transmission/reception circuit, wherein the first transmission/reception circuit outputs a serial data signal DATA to the transmission path, said serial data signal DATA being generated by superposing a first superposition pulse having a second level to a portion of a clock signal input from outside having a first level according on binary first transmission data to be output to the second transmission/reception circuit, said clock signal being a binary signal, said second level being reciprocal to said first level; and the second transmission/reception circuit superposes a second superposition pulse having the first level to a portion of the serial data signal DATA input from the transmission path according to binary second transmission data to be output to the first transmission/reception circuit, said portion corresponding to a duration of the clock signal having the second level.

As an embodiment, the first transmission/reception circuit comprises a first transmission circuit that superposes the first superposition pulse on the portion of the clock signal having the first level, and outputs the serial data signal DATA to the transmission path; and a first reception circuit that extracts the second superposition pulse from the serial data signal DATA to extract the second transmission data.

As an embodiment, the second transmission/reception circuit comprises a second transmission circuit that superposes the second superposition pulse on the portion of the serial data signal DATA corresponding to the duration of the clock signal having the second level and transmits a resulting signal to the transmission path; and a second reception circuit that extracts the first superposition pulse from the serial data signal DATA input from the first transmission/reception circuit to extract the second transmission data.

Preferably, the first transmission circuit superposes the first superposition pulse having the second level and a pulse width T1on the portion of the clock signal having the first level and a pulse width T3starting from a predetermined starting point after a time period T2elapses from the starting point to indicate one of two levels of one bit data in the serial data signal DATA, or the second transmission circuit indicates another one of the two levels of one bit data in the serial data signal DATA when the first superposition pulse is absent after the time period T2elapses from the starting point; and the first transmission circuit generates and outputs the serial data signal DATA one bit by one bit consecutively to perform serial communication so that the pulse width T1, the pulse width T3, and the time period T2satisfy T1<T2<T3, and (T1+T2)<T3.

Preferably, the second transmission circuit superposes the second superposition pulse having the first level and a pulse width T1on the portion of the serial data signal DATA having the second level corresponding to the duration of the clock signal having the second level and a pulse width T3starting from a predetermined starting point after the time period T2elapses from the starting point to indicate one of two levels of one bit data in the serial data signal DATA, or the second transmission circuit indicates another one of the two levels of one bit data in the serial data signal DATA when the second superposition pulse is absent after the time period T2elapses from the starting point; and the second transmission circuit generates and outputs the serial data signal DATA one bit by one bit-consecutively to perform serial communication so that the pulse width T1, the pulse width T3, and the time period T2satisfy T1<T2<T3, and (T1+T2)<T3.

As an embodiment, the first transmission circuit comprises a first T2delay circuit that delays the clock signal by the time period T2and outputs said delayed signal; a first T1delay circuit that delays the output signal from the first T2delay circuit by a time period T1and outputs said delayed signal; a first superposition pulse generation circuit that generates the first superposition pulse having the pulse width T1from the output signal from the first T2delay circuit and the output signal from the first T1delay circuit; and a first output signal generation circuit that superposes the first superposition pulse from the first superposition pulse generation circuit on the clock signal according to the first transmission data, and generates data equaling to one bit sequentially to generate the serial data signal DATA and to transmit the serial data signal DATA to the transmission path.

As an embodiment, the first reception circuit comprises: a first T4delay circuit that delays the received serial data signal DATA by a time period T4equaling to or greater than (T1+T2), and outputs said delayed signal; a first input signal delay circuit that delays the output signal from the first T4delay circuit by a predetermined time period and outputs said delayed signal; and a first data extraction circuit that extracts the second transmission data from the received serial data signal DATA and the output signal from the first input signal delay circuit, and outputs the extracted signal.

As an embodiment, the second reception circuit comprises: a second T4delay circuit that delays the received serial data signal DATA by the time period T4equaling to or greater than (T1+T2), and outputs said delayed signal; a second input signal delay circuit that delays the output signal from the second T4delay circuit by a predetermined time period and outputs said delayed signal; and a second data extraction circuit that extracts the first transmission data from the received serial data signal DATA and the output signal from the second input signal delay circuit, and outputs the extracted signal.

As an embodiment, the second transmission circuit comprises: a second T2delay circuit that delays the received serial data signal DATA by the time period T2and outputs said delayed signal; a second T1delay circuit that delays the output signal from the second T2delay circuit by a time period T1and outputs said delayed signal; a second superposition pulse generation circuit that generates the second superposition pulse having the pulse width T1from the output signal from the second T2delay circuit and the output signal from the second T1delay circuit; and a second output signal generation circuit that superposes, according to the second transmission data, the second superposition pulse output from the second superposition pulse generation circuit to the portion of the received serial data signal DATA corresponding to the duration of the clock signal having the second level, and generates data equaling to one bit sequentially to generate the serial data signal DATA and to transmit the serial data signal DATA to the transmission path.

As an embodiment, the first output signal generation circuit sets an output terminal to be in a high impedance state when the serial data signal DATA is at the second level.

As an embodiment, when the transmission path is pulled down by a pull-down resistance, the first output signal generation circuit shorts the pull-down resistance for a predetermined time period at falling time of the serial data signal DATA.

As an embodiment, when the transmission path is pulled up by a pull-up resistance, the first output signal generation circuit shorts the pull-up resistance for a predetermined time period at rising time of the serial data signal DATA.

As an embodiment, the second output signal generation circuit sets an output terminal to be in a high impedance state when the serial data signal DATA is at the first level.

As an embodiment, when the transmission path is pulled down by a pull-down resistance, the second output signal generation circuit shorts the pull-down resistance for a predetermined time period at falling time of the serial data signal DATA.

As an embodiment, when the transmission path is pulled up by a pull-up resistance, the second output signal generation circuit shorts the pull-up resistance for a predetermined time period at rising time of the serial data signal DATA.

According to a second aspect of the present invention, there is provided a serial communication method of a serial communication device that includes a first transmission/reception circuit and at least one second transmission/reception circuit connected with the first transmission/reception circuit in a transmission path, and performs serial communication by half-duplex communication between the first transmission/reception circuit and the second transmission/reception circuit, said method comprising the steps of: superposing a first superposition pulse having a second level on a portion of a clock signal input from outside having a first level according to binary first transmission data to be output to the second transmission/reception circuit, outputting a resulting serial data signal DATA to the transmission path, said clock signal being a binary signal, said second level being reciprocal to said first level; and superposing a second superposition pulse having the first level on a portion of the serial data signal DATA input from the transmission path corresponding to a duration of the clock signal having the second level according to binary second transmission data to be output to the first transmission/reception circuit.

As an embodiment, the step of superposing a first superposition pulse includes the steps of: superposing the first superposition pulse having the second level and a pulse width T1on the portion of the clock signal having the first level and a pulse width T3starting from a predetermined starting point after a time period T2elapses from the starting point to indicate one of two levels of one bit data in the serial data signal DATA, or indicating another one of the two levels of one bit data in the serial data signal DATA when the first superposition pulse is absent after the time period T2elapses from the starting point; and generating and outputting the serial data signal DATA one bit by one bit consecutively to perform serial communication so that the pulse width T1, the pulse width T3, and the time period T2satisfy: T1<T2<T3, and (T1+T2)<T3.

As an embodiment, the step of superposing a second superposition pulse includes the steps of: superposing the second superposition pulse having the first level and a pulse width T1on the portion of the serial data signal DATA having the second level corresponding to the duration of the clock signal having the second level and a pulse width T3starting from a predetermined starting point after the time period T2elapses from the starting point to indicate one of two levels of one bit data in the serial data signal DATA, or indicating another one of the two levels of one bit data in the serial data signal DATA when the second superposition pulse is absent after the time period T2elapses from the starting point; and generating and outputting the serial data signal DATA one bit by one bit consecutively to perform serial communication so that the pulse width T1, the pulse width T3, and the time period T2satisfy: T1<T2<T3, and (T1+T2)<T3.

According to a third aspect of the present invention, there is provided a communication system comprising a serial communication device that includes a first transmission/reception circuit connected to a host device and at least one second transmission/reception circuit connected corresponding to slave devices able to communicate with the host device, and performs serial communication by half-duplex communication between the first transmission/reception circuit and the second transmission/reception circuit, said first transmission/reception circuit and said second transmission/reception circuit being connected with each other in a transmission path, wherein the first transmission/reception circuit of the serial communication device outputs a serial data signal DATA to second transmission/reception circuit via the transmission path, said serial data signal DATA being generated by superposing a first superposition pulse having a second level on a portion of a clock signal input from the host device having a first level according to binary first transmission data to be transmitted from the host device to the slave device, said clock signal being a binary signal, said second level being reciprocal to said first level; and the second transmission/reception circuit of the serial communication device superposes a second superposition pulse having the first level on a portion of the serial data signal DATA input from the first transmission/reception circuit transmission path according to binary second transmission data to be output from the corresponding slave device to the host device, said portion corresponding to a duration of the clock signal having the second level.

As an embodiment, the first transmission/reception circuit comprises: a first transmission circuit that superposes the first superposition pulse on the portion of the clock signal having the first level, and outputs the serial data signal DATA to the transmission path; and a first reception circuit that extracts the second superposition pulse from the serial data signal DATA to extract the second transmission data.

As an embodiment, the second transmission/reception circuit comprises: a second transmission circuit that superposes the second superposition pulse on the portion of the serial data signal DATA corresponding to the duration of the clock signal having the second level and transmits a resulting signal to the transmission path; and a second reception circuit that extracts the first superposition pulse from the serial data signal DATA input from the first transmission/reception circuit to extract the second transmission data.

As an embodiment, the first transmission circuit superposes the first superposition pulse having the second level and a pulse width T1on the portion of the clock signal having the first level and a pulse width T3starting from a predetermined starting point after a time period T2elapses from the starting point to indicate one of two levels of one bit data in the serial data signal DATA, or the second transmission circuit indicates another one of the two levels of one bit data in the serial data signal DATA when the first superposition pulse is absent after the time period T2elapses from the starting point; and the first transmission circuit generates and outputs the serial data signal DATA one bit by one bit consecutively to perform serial communication so that the pulse width T1, the pulse width T3, and the time period T2satisfy: T1<T2<T3, and (T1+T2)<T3.

As an embodiment, the second transmission circuit superposes the second superposition pulse having the first level and a pulse width T1on the portion of the serial data signal DATA having the second level corresponding to the duration of the clock signal having the second level and a pulse width T3starting from a predetermined starting point after the time period T2elapses from the starting point to indicate one of two levels of one bit data in the serial data signal DATA, or the second transmission circuit indicates another one of the two levels of one bit data in the serial data signal DATA when the second superposition pulse is absent after the time period T2elapses from the starting point; and the second transmission circuit generates and outputs the serial data signal DATA one bit by one bit consecutively to perform serial communication so that the pulse width T1, the pulse width T3, and the time period T2satisfy: T1<T2<T3, and (T1+T2)<T3.

According to the serial communication device related to the present invention, and a communication method thereof and a communication system using the serial communication device, one-wire communication using one channel can be realized with fewer circuits and without a switching unit for switching transmission operations and reception operations; thereby, it is possible to reduce the size and cost of the device, and further, the communication lines can be constructed to have a bus structure.

In addition, according to the serial communication device related to the present invention and the communication system using the serial communication device, the waveform of the serial data signal DATA can be made sharp; thus it is possible to realize high speed operation, prevent signal conflict in the transmission path, and therefore, excess power consumption is preventable.

These and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of preferred embodiments given with reference to the accompanying drawings.

BEST MODE FOR CARRYING OUT THE INVENTION

Below, preferred embodiments of the present invention are explained with reference to the accompanying drawings.

FIG. 1is a block diagram schematically illustrating a serial communication device according to an embodiment of the present invention.

InFIG. 1, a serial communication device1performs serial communications by half-duplex operations between a host device HC and slave devices SC1through SCn (where n is an integer greater than zero). The serial communication device1includes a master transmission/reception circuit2and slave transmission/reception circuits SL1through SLn.

Here, the master transmission/reception circuit2corresponds to the first transmission/reception circuit in claims, and the slave transmission/reception circuits SL1through SLn correspond to the second transmission/reception circuit in claims.

The master transmission/reception circuit2is connected to the host device HC, and the slave transmission/reception circuits SL1through SLn are connected to the slave devices SC1through Scn, respectively.

The master transmission/reception circuit2and the slave transmission/reception circuits SL1through SLn are connected with a transmission path4, which transmits serial signals. In addition, the transmission path4is connected to ground through a pull-down resistor5.

It should be noted that the transmission path4can be formed from not only signal lines but also light, supersonic waves or other sounds, or radio frequency (RF) waves.

The slave transmission/reception circuits SL1through SLn have the same configuration. Below, any one of the slave transmission/reception circuits SL1through SLn, denoted to be SLk (k=1 to n), is used as an example.

The master transmission/reception circuit2includes a master transmission circuit11and a master reception circuit12. The slave transmission/reception circuit SLk includes a slave transmission circuit13and a slave reception circuit14.

The master transmission circuit11and the master reception circuit12, and the slave transmission circuit13and the slave reception circuit14are connected through the transmission path4.

When transmitting data from the master transmission/reception circuit2to the slave transmission/reception circuit SLk, the master transmission circuit11superposes a superposition pulse on a high-level (High) portion of a clock signal TCLK input from the host device HC to write desired data, thereby generating desired serial data signal DATA. The serial data signal DATA is transmitted from the master transmission circuit11to the slave transmission/reception circuit SLk through the transmission path4.

The slave reception circuit14extracts data from the serial data signal DATA input through the transmission path4.

On the other hand, when transmitting data from the slave transmission/reception circuit SLk to the master transmission/reception circuit2, the slave transmission/reception circuit SLk writes data to the serial data signal DATA input from the master transmission/reception circuit2through the transmission path4. The slave transmission circuit13and the slave reception circuit14are connected with each other, and the slave transmission circuit13superposes a superposition pulse on a low-level (Low) portion of the serial data signal DATA input through the transmission path4to write desired data, then the thus obtained serial data signal DATA is transmitted to the master transmission/reception circuit2through the transmission path4.

The master reception circuit12extracts data from the serial data signal DATA input through the transmission path4.

For example, in a mobile cellular phone, the slave devices SC1through SCn serve as a temperature sensor installed in a battery package, a battery checker for indicating residual electric power of a battery BAT, and a battery identifier for identifying the type of the battery package. The slave devices, such as the temperature sensor and the battery checker, are connected to the battery BAT built in the battery package.

FIG. 2AthroughFIG. 2Eshow a timing chart illustrating a communication protocol used by the serial communication device1shown inFIG. 1.

As illustrated inFIG. 2AthroughFIG. 2E, the host device HC uses the serial communication device1to transmit a high level signal to the slave devices SC1through SCn over a certain period, namely, the host device HC performs preamble communications.

Receiving the high level signal continuously, each of the slave devices SC1through SCn recognizes that a preamble is being transmitted from the host device HC, and starts a preamble preparation period. In this state, after the host device HC transmits one clock pulse at the low level, for example, the host device HC transmits a characteristic ID of the slave devices SC1. After the preamble, each of the slave devices SC1through SCn receives the one clock pulse at the low level first, next receives the ID, and then determines whether the received ID is in agreement with its own ID.

Assume the slave device SC1determines that the received ID is in agreement with its own ID, and the other slave devices determine that the received ID is not in agreement with their own IDs. When the slave device SC1determines that the ID issued by the host device HC is in agreement with its own ID, the slave device SC1transmits an acknowledge signal ACK to notify the host device HC of the determination result. When the host device HC confirms that the acknowledge signal ACK is transmitted on the transmission path4, which is formed from one wire, the host device HC determines that the slave device SC1is on the transmission path4, and the slave device SC1is in a state enabling normal communication. Based on this determination result, the host device HC issues a command to execute operations in the slave device SC1.

When receiving the command, the slave device SC1executes the command. When it is necessary to send back results of the command execution to the host device HC, the slave device SC1sends back the results of the command execution to the host device HC.

For example, when the command is a read command of reading a register at a specified address, as the results of the command execution, the slave device SC1sends back the data in the register to the host device HC.

After the host device HC confirms the received data, one processing cycle is completed.

If the host device HC continues communications with the same slave device or other slave devices, a preamble communication for the next communication operation is started.

The one-wire bus communication is frequently used because it enables reduction of the number of terminals of the device, and in turn reduces the cost. For this reason, if the circuits of the slave devices are constructed with general-purpose elements, the cost can be reduced by mass production.

However, with the circuits of the slave device being constructed with general-purpose elements, for example, when the slave device SC1and the slave device SC2are used in different systems, the preamble periods of the slave device SC1and the slave device SC2required by the systems may be different.

In this way, in order to make the slave devices general-purpose, and use a common method in different systems, in the present embodiment, the preamble period is not fixed, and the same signal is transmitted continuously over a certain period to create a guaranteed preamble state.

In this way, for example, when the slave device SC1is in a preamble state over a 32-clock-pulse period, the slave device SC2requires a preamble state over a 20-clock-pulse period, and other slave devices SC3to SCn require preamble states over a 20-clock-pulse period, if a preamble state over a 36-clock-pulse period is created, all slave devices are in a guaranteed preamble state. Afterward, a low level pulse is transmitted, and all slave devices SC1through SCn can transfer to an ID detection period simultaneously.

In the one-wire bus communication, if the slave device connected to the one-wire bus is known beforehand, the following method can be tried, that is, issue an ID to select a specified slave device after the preamble communication, and issue a command immediately. This method has an advantage in that the communication time can be saved, but it is not applicable to the situation in which the one-wire bus is opened to the outside, and an unspecified number of devices are optionally connected to the bus as system devices. When an unspecified number of devices are connected to the bus, it is necessary for the host device HC to first confirm the slave device to be accessed.

For this reason, after the preamble communication, and after the host device HC issues the ID, the recognized slave device transmits the acknowledge signal ACK to the host device HC; thereby, the host device HC can confirm that the slave device is connected to the one-wire bus. If the slave device is connected to the one-wire bus as a system device, it is possible to use the slave device to perform operations on the system. If there is no acknowledge signal ACK sent back, the host device HC can confirm that the slave device is not connected to the one-wire bus, and the system is operating without the slave device. This scheme is useful when the slave device is used just as an option.

If the slave device malfunctions when a clock signal and a data signal are transmitted with the one-wire bus, it is necessary to reset the slave device. However, even if the slave device is reset with data, when the slave device malfunctions, data communication may be disabled. In order to avoid such a problem, the slave device is configured such that if the same signal is received continuously over a certain period, the slave device compulsorily sets the internal status of the slave device to the initial values, namely, the slave device performs resetting.

In this way, if a slave device recognized in the initial state of the system cannot send back the acknowledge signal ACK any more during operations, probably some malfunction has occurred in the slave device; for example, the host device HC continuously sends a high level signal for 128 times to initialize all the slave devices connected to the one-wire bus to an established preamble reception preparation state. In this way, the one-wire system is capable of stable operations.

Below, explanations are made of the applications executed during the one-wire communications.

FIG. 3is a block diagram schematically illustrating a serial communication device in which the slave device is implemented to be a battery package. InFIG. 3, it is assumed that n equals 3.

InFIG. 3, it is assumed that the slave device SC3has an authentication ID function. The slave device SC1is a battery checker that checks and indicates residual power of a battery BAT, and the slave device SC2is a temperature sensor that detects the temperature of the battery BAT. It is assumed that the host device HC first communicates with a device having the authentication ID function as the slave device SC3. In this case, an ID equaling 3 is input to the slave device SC3after the preamble. When the slave device SC3determines that this ID after the preamble points to the slave device SC3, the slave device SC3sends the acknowledge signal ACK on the one-wire transmission path4. Meanwhile, because the ID after the preamble does not point to the slave device SC1and the slave device SC2, the slave device SC1and the slave device SC2do not send back the acknowledge signal ACK.

When the host device HC confirms that the acknowledge signal ACK is sent back from the slave device SC3, the host device HC can determine that an authentication ID device is in the slave device SC3, and the host device HC starts to communication with the authentication ID device. The host device HC sends specified codes to the authentication ID device of the slave device SC3, through the master transmission/reception circuit2, the transmission path4, and the slave transmission/reception circuit SL3.

Receiving the specified codes from the host device HC, the authentication ID device of the slave device SC3encrypts the codes, and sends back the encrypted codes to the host device HC.

The master transmission/reception circuit2sends the encrypted codes received from the slave device SC3to the host device HC.

The host device HC decrypts the encrypted codes; thereby, the host device HC can authenticate that the authentication ID device in the battery package is a predetermined device.

The same protocol is used to enable communications when the residual power of the battery is reported from the slave device SC1, or the temperature is reported from the slave device SC2.

Authentication of any slave device SCk is performed by using the one-wire transmission path4. When receiving the clock signal TCLK input from the host device HC, the master transmission/reception circuit2detects a start of the clock operations to automatically start the authentication process. The host device HC sends specified signals to the slave device SCk through the serial communication device1, and the slave device SCk creates an encryption key based on the specified signals, then sends back the encryption key to the host device HC through the serial communication device1.

FIG. 4shows waveforms presenting an example of states of a flag F during the authentication process.

As illustrated inFIG. 4, the host device HC decrypts the signals sent from the slave device SCk, and when the authentication result is in agreement, the host device HC sets an internal flag F to a high level, stops supply of the clock signal TCLK, and resets the master transmission/reception circuit2; then the authentication sequence is completed.

When it is desired to perform a next authentication sequence, once the host device HC supplies the clock signal TCLK, the authentication process is started automatically.

On the other hand, the host device HC decrypts the signals sent from the slave device sCk, and when the authentication result is not in agreement, the host device HC does not set the internal flag F to the high level, and after a specified time period elapses, the host device HC stops supply of the clock signal TCLK due to the authentication failure. Even in this case, the host device HC resets the master transmission/reception circuit2, and when a start of authentication operations is detected, the host device HC performs again the authentication operations of the slave device.

FIG. 5exemplifies a circuit diagram of the master transmission/reception circuit2.

InFIG. 5, a data signal DHo and a clock signal TCLK are output from the host device HC and input to the master transmission circuit11. According to the data signal DHo, the master transmission circuit11generates the serial data signal DATA and outputs the serial data signal DATA to the transmission path4. For example, the clock signal TCLK has a frequency twice the output timing of the data signal DHo, and is in synchronization with the data signal DHo.

The master transmission circuit11includes a T2delay circuit21that delays the clock signal TCLK by a time period T2and outputs the delayed signal; a T1delay circuit22that delays the output signal S1from the T2delay circuit21by a time period T1and outputs the delayed signal; a pulse generation circuit23that generates a pulse signal S3from the output signal S1from the T2delay circuit21and the output signal S2from the T1delay circuit22; and an output signal generation circuit24that generates the serial data signal DATA corresponding to the data signal DHo from the data signal DHo, the pulse signal S3from the pulse generation circuit23, and the clock signal TCLK, then transmits the serial data signal DATA to the transmission path4.

Here, the master transmission circuit11, the T2delay circuit21, the T1delay circuit22, the pulse generation circuit23, and the output signal generation circuit24correspond to the first transmission circuit, the first T2delay circuit, the first T1delay circuit, the first superposition pulse generation circuit, and the first output signal generation circuit in claims, respectively.

The T2delay circuit21includes a buffer30. The clock signal TCLK is input to an input terminal of the buffer30, and the buffer30delays the input clock signal TCLK by the time period T2, then outputs the obtained signal S1to the T1delay circuit22and the pulse generation circuit23. The time period T2is decided by a threshold voltage of the buffer30.

The T1delay circuit22includes a buffer31and an inverter32, which are connected in series. The buffer31and the inverter32delay the output signal S1from the T2delay circuit21by the time period T1, invert the signal level, and output the obtained signal S2to the pulse generation circuit23.

The pulse generation circuit23includes an AND circuit33. The output signal S1from the T2delay circuit21is input to one input terminal of the AND circuit33, and the output signal S2from the T1delay circuit22is input to the other input terminal of the AND circuit33. From an output terminal of the AND circuit33, the pulse signal S3is output, which is used to generate a superposition pulse having a low level and a pulse width T1at a position after the time period T2elapses from the rising time of the input clock signal TCLK.

The output signal generation circuit24includes an AND circuit34having three input terminals, an ExNOR (exclusive NOR) circuit35, an OR circuit36, a PMOS transistor37, a NMOS transistor38, an AND circuit39, buffers40,41, and an inverter42.

The data signal DHo from the host device, the pulse signal S3from the AND circuit33, and a signal S4from the master reception circuit12are input to the three input terminals of the AND circuit34, respectively.

The clock signal TCLK is input to one input terminal of the ExNOR circuit35, and an output signal S5from the AND circuit34is input to the other input terminal of the ExNOR circuit35, and the ExNOR circuit35output a signal S6to a gate of the PMOS transistor37.

The clock signal TCLK is inverted by the inverter42and is then input to one input terminal of the AND circuit39, and the clock signal TCLK is delayed by the buffers40,41, and is input to the other input terminal of the AND circuit39.

An output signal S8from the AND circuit39is input to one input terminal of the OR circuit36, and an output signal S5from the AND circuit34is input to the other input terminal of the OR circuit36.

An output signal S7from the OR circuit36is input to a gate of the NMOS transistor38, the PMOS transistor37and the NMOS transistor38are connected in series between a power voltage Vdd and the earth, and the transmission path4is connected to a connecting portion of the PMOS transistor37and the NMOS transistor38.

InFIG. 5, the master reception circuit12extracts an input data signal DHi from the serial data signal DATA input through the transmission path1, and outputs the extracted signal to the host device HC as an input data signal DHi.

The master reception circuit12includes a buffer41that amplifies the serial data signal DATA and outputs the amplified signal; a T4delay circuit42that delays an output signal S11from the buffer41by a time period T4, then inverts the signal level and outputs the resulting signal; an input signal delay circuit43that delays the output signal S4from the T4delay circuit42by a predetermined time period and outputs the obtained signal; a data extraction circuit44that extracts a data signal from the output signal S11of the buffer41and outputs the data signal as the input data signal DHi to the host device HC; and an initialization circuit45that initializes the data extraction circuit44.

Here, the master reception circuit12, the T4delay circuit42, the input signal delay circuit43, and the data extraction circuit44correspond to the first reception circuit, the first T4delay circuit, the first input signal delay circuit, and the first data extraction circuit in claims, respectively.

The T4delay circuit42includes a resistor51, a condenser52, and an inverter53. The condenser52is connected between one end of the resistor51and ground, and the other end of the resistor51is connected to the output terminal of the buffer41from which the output signal S11is issued. An input terminal of the inverter53is connected to a connecting portion of the resistor51and the condenser52. The signal from connecting portion of the resistor51and the condenser52is denoted to be S12.

The input signal delay circuit43includes a buffer54and a buffer55which are connected in series. The output signal S4from the T4delay circuit42is input to an input terminal of the buffer54, and a delayed signal S13is output from an output terminal of the buffer55.

The data extraction circuit44includes an inverter56and D flip-flops57,58. The inverter56inverts the signal S11and inputs the inverted signal S11to a clock signal input terminal CK of the D flip-flop57. In the D flip-flop57, an inverted output terminal QB is connected to a data input terminal D, and this connection terminal is connected to a data input terminal D of the D flip-flop58. In the D flip-flop58, the output signal S13from the input signal delay circuit43is input to the clock signal input terminal CK, and the input data signal DHi is output from an output terminal Q to the host device HC. An output signal S14from the initialization circuit45is input to a reset signal input terminal R of the D flip-flop57, and a power-on reset signal RES1from the host device HC is input to a reset signal input terminal R of the D flip-flop58.

The initialization circuit45includes an inverter59, an OR circuit60, and an AND circuit61.

The output signal S13is inverted by the inverter59and is then input to one input terminal of the OR circuit60, and the output signal S4is input to the other input terminal of the OR circuit60.

An output signal from the OR circuit60is input to one input terminal of the AND circuit61, and the power-on reset signal RES1from the host device HC is input to the other input terminal of the AND circuit61. The output terminal of the AND circuit61is connected to the reset signal input terminal R of the D flip-flop57.

FIG. 6exemplifies a circuit diagram of the slave transmission/reception circuit SLk. Other slave transmission/reception circuits are the same as the slave transmission/reception circuit SLk.

InFIG. 6, an output data signal DSo from the slave device SCk is input to the slave transmission circuit13, and the serial data signal DATA, which corresponds to the output data signal DSo, is generated and output to the transmission path4.

The slave transmission circuit13includes a T2delay circuit71that delays the serial data signal DATA by a time period T2and outputs the obtained signal; a T1delay circuit72that delays the output signal S21from the T2delay circuit71by a time period T1and outputs the obtained signal; a pulse generation circuit73that generates a pulse signal S23from the output signal S21from the T2delay circuit71and the output signal S22from the T1delay circuit72; and an output signal generation circuit74that generates the serial data signal DATA corresponding to the output data signal DSo from the output data signal DSo, the output signal S23from the pulse generation circuit73, and outputs the serial data signal DATA.

Here, the slave transmission circuit13, the T2delay circuit71, the T1delay circuit72, the pulse generation circuit73, and the output signal generation circuit74correspond to the second transmission circuit, the second T2delay circuit, the second T1delay circuit, the second pulse generation circuit, and the second output signal generation circuit in claims, respectively.

The T2delay circuit71includes a buffer81, and a buffer82, which are connected in series. The serial data signal DATA is input to an input terminal of the buffer82. The buffer81delays the input serial data signal DATA by the time period12, and outputs the obtained signal S21.

The T1delay circuit72includes a buffer83and an inverter84, which are connected in series. The buffer83and the inverter84delay the output signal S21from the T2delay circuit71by the time period T1, invert the signal level, and output the obtained signal S22to the pulse generation circuit73.

The pulse generation circuit73includes an NOR circuit85. The output signal S21from the T2delay circuit71is input to one input terminal of the NOR circuit85, and the output signal S22from the T1delay circuit72is input to the other input terminal of the NOR circuit85. From an output terminal of the NOR circuit85, the pulse signal S23is output, which is used to generate a superposition pulse having a high level and a pulse width T1at a position after the time period T2elapses from the falling time of the serial data signal DATA.

The output signal generation circuit74includes an AND circuit86having three input terminals, inverters87,95, buffers88to91,94, a PMOS transistor92, a NMOS transistor93, and a D flip-flop96.

A signal S25corresponding to the output data signal DSo from the slave device SCk, the signal S23from the NOR circuit85, and a signal S32from the slave reception circuit14are input to the three input terminals of the AND circuit86, respectively.

An output signal S24from the AND circuit86is inverted by the inverter87, and the inverted signal S27is input to a gate of the PMOS transistor92. In addition, the output signal S24from the AND circuit86is delayed by the buffers88to91which are connected in series, and the delayed signal S28is input to a gate of the NMOS transistor93.

The PMOS transistor92and the NMOS transistor93are connected in series between the power voltage Vdd and ground, and the transmission path4is connected to a connecting portion of the PMOS transistor92and the NMOS transistor93.

The signal S28is input to a reset signal input terminal R of the D flip-flop96through the buffer95and the inverter95, which are connected in series.

In the D flip-flop96, the output data signal DSo from the slave device SCk is input to a data input terminal D, and the output signal S21from the T2delay circuit71is input to the clock signal input terminal CK. The D flip-flop96outputs a signal S25from an output terminal Q to an input terminal corresponding to the AND circuit86.

Next, inFIG. 6, the slave reception circuit14extracts data from the serial data signal DATA input through the transmission path4, and outputs the extracted signal to the slave device SCk as an input data signal DSi.

InFIG. 6, the slave reception circuit14includes a T4delay circuit101that delays the serial data signal DATA by a time period T4and outputs the resulting signal, an input signal delay circuit102that delays the output signal S32from the T4delay circuit101by a predetermined time period and outputs the obtained signal, a data extraction circuit103that extracts a data signal from the output signal S21of the T2delay circuit71and outputs the data signal as the input data signal DSi to the slave device sCk, and an initialization circuit104that initializes the data extraction circuit103.

Here, the T4delay circuit101, the input signal delay circuit102, and the data extraction circuit103correspond to the second T4delay circuit, the second input signal delay circuit, and the second data extraction circuit in claims, respectively.

The T4delay circuit101includes a resistor111, a condenser112, and an inverter113. The condenser112is connected between one end of the resistor111and ground, and the serial data signal DATA is input to the other end of the resistor111. An input terminal of the buffer113is connected to a connecting portion of the resistor111and the condenser112. The signal from connecting portion of the resistor111and the condenser112is denoted to be S31.

The input signal delay circuit102includes a buffer114and a buffer115which are connected in series. The output signal S32from the T4delay circuit101is input to an input terminal of the buffer114, and a delayed signal S33is output from an output terminal of the buffer115.

The data extraction circuit103includes a D flip-flop116, and a D flip-flop117. In the D flip-flop116, the output signal S21from the T2delay circuit71is input to the clock signal input terminal CK, an inverted output terminal QB is connected to a data input terminal D, and this connection part carrying signal S35is connected to the data input terminal D of the D flip-flop117.

In the D flip-flop117, the output signal S33from the input signal delay circuit102is input to the clock signal input terminal CK, and an output terminal outputs the input data signal DSi to the slave device SCk. An output signal S34from the initialization circuit104is input to a reset signal input terminal R of the D flip-flop116, and a power-on reset signal RES1from a not-illustrated power-on reset circuit is input to a reset signal input terminal R of the D flip-flop117.

The initialization circuit104includes an inverter118, an OR circuit119, and an AND circuit120.

The output signal S33is inverted by the inverter118and is then input to one input terminal of the OR circuit119, and the output signal S32from the T4delay circuit101is input to the other input terminal of the OR circuit119.

An output signal from the OR circuit119is input to one input terminal of the AND circuit120, and the power-on reset signal RES2is input to the other input terminal of the AND circuit120. The output terminal of the AND circuit120is connected to the reset signal input terminal R of the D flip-flop116.

Below, a description is made of a communication method of the serial communication device1having the above configuration.

In the serial communication device1, a superposition pulse signal is superposed on the clock signal TCLK, and the value of signal data is expressed in connection with presence or absence of the superposition pulse signal.

FIG. 7AthroughFIG. 7Eshow examples of waveforms in communications in the serial communication device1.

Signal communication in the one-wire communications includes supplying the clock signal TCLK from the master transmission/reception circuit2, transferring data from the master transmission/reception circuit2to the slave transmission/reception circuit SLk, and transferring data from the slave transmission/reception circuit SLk to the master transmission/reception circuit2.

In the serial communication device1, the master transmission/reception circuit2or the slave transmission/reception circuit SLk inserts data signals into the clock signal TCLK supplied from the host device HC for communication.

When transmitting data from the master transmission/reception circuit2to the slave transmission/reception circuit SLk, the high-level (High) portion of the clock signal TCLK is used. When transmitting data from the slave transmission/reception circuit SLk to the master transmission/reception circuit2, the low-level (Low) portion of the clock signal TCLK is used.

When the master transmission/reception circuit2transmits data “1” to the slave transmission/reception circuit SLk, a low-level superposition pulse having a pulse width T1is inserted into the clock signal TCLK, after the time period T2elapses from the rising time of the clock signal TCLK, when the clock signal TCLK is at the high level.

When the master transmission/reception circuit2transmits data “0” to the slave transmission/reception circuit SLk, the low-level superposition pulse is not inserted into the clock signal TCLK when the clock signal TCLK is at the high level.

Similarly, when the slave transmission/reception circuit SLk transmits data “1” to the master transmission/reception circuit2, a high-level superposition pulse having a pulse width T1is inserted into the clock signal TCLK, after the time period T2elapses from the falling time of the clock signal TCLK, when the clock signal TCLK is at the low level.

When the slave transmission/reception circuit SLk transmits data “0” to the master transmission/reception circuit2, the high-level superposition pulse is not inserted into the clock signal TCLK when the clock signal TCLK is at the low level.

In this way, the serial communication device1is able to transmit data through the transmission path4.

The master transmission/reception circuit2and the slave transmission/reception circuit SLk output signals to the transmission path4, which is formed from one signal line. If the master transmission/reception circuit2and the slave transmission/reception circuit SLk output signals to the transmission path4at the same time, the corresponding current becomes too large, and this may cause malfunction of the device.

In order to avoid such a problem, when the master transmission/reception circuit2outputs signals to the transmission path4, the output terminal of the slave transmission/reception circuit SLk is set to be in a high impedance state constantly so that the slave transmission/reception circuit SLk does not output signals to the transmission path4. Meanwhile, when the slave transmission/reception circuit SLk outputs signals to the transmission path4, the output terminal of the master transmission/reception circuit2is set to be in a high impedance state constantly so that the master transmission/reception circuit2does not output signals to the transmission path4.

Here, the transmission path4is pulled down by a pull-down resistance5. The master transmission/reception circuit2always outputs signals when the clock signal TCLK is at the high level. When the master transmission/reception circuit2transmits data “1” to the slave transmission/reception circuit SLk, that is, when the low-level superposition pulse is inserted when the clock signal TCLK is at the high level, because the master transmission/reception circuit2inserts the low-level superposition pulse into the high level portion of the clock signal TCLK, the master transmission/reception circuit2constantly drives the transmission path4(that is, the master transmission/reception circuit2outputs signals to the transmission path4); hence, the master transmission/reception circuit2and the slave transmission/reception circuit SLk do not drive the transmission path4(that is, output signals to the transmission path4) at the same time.

In addition, when the master transmission/reception circuit2transmits data “1” to the slave transmission/reception circuit SLk, the transmission path4is pulled down by the pull-down resistance5, and the master transmission/reception circuit2does not drive the transmission path4. Due to this, even when the slave transmission/reception circuit SLk inserts a high-level superposition pulse into a low-level portion of the clock signal TCLK, the master transmission/reception circuit2and the slave transmission/reception circuit SLk do not drive the transmission path4at the same time.

When the master transmission/reception circuit2inserts the low-level superposition pulse into the high-level portion of the clock signal TCLK, because the transmission path4is being driven constantly, it is possible to change the state of the transmission path4sharply.

However, when the output terminal of the master transmission/reception circuit2is set to be in a high impedance state constantly, and it is attempted to set the transmission path4to the low level only by the pull-down resistance5, if the pull-down resistance5is not sufficiently small, the rising time becomes smooth. Meanwhile, if the pull-down resistance5is too small, when the master transmission/reception circuit2sets the transmission path4to the high level, current flows through the pull-down resistance5, and power consumption increases.

In order to avoid this problem, when the transmission path4is at the low level, the master transmission/reception circuit2turns on the NMOS transistor38for a short time period, to set the transmission path4to be the low level; as a result, a sharp waveform is obtainable.

Similarly, when the slave transmission/reception circuit SLk inserts the high-level superposition pulse into the low-level portion of the clock signal TCLK, although it is easy to allow the transmission path4to transit to the high level rapidly, by only turning off the PMOS transistor92, as the falling time of the signal levels on the transmission path4is only affected by current leakage due to the pull down resistance5, the falling time becomes smooth.

In order to avoid this problem, when the slave transmission/reception circuit SLk turns off the PMOS transistor92, the NMOS transistor93is turned on for a short time period. Due to this, it is possible to generate a sharp waveform and perform high speed operations. In addition, it is possible to increase the value of the pull down resistance5, and decrease excessive current consumption on the transmission path4.

InFIG. 5, when the master transmission/reception circuit2transmits data “1” to the slave transmission/reception circuit SLk, the data signal DHo is set to a high level. In this state, if the clock signal TCLK is at the low level, accordingly the signal S5is at the low level. Since the clock signal TCLK is input and the input terminals of the ExNOR circuit35become {1, 0} at the rising time of the clock signal TCLK under this state, the signal S6turns to be the low level, the PMOS transistor37is turned on, and the serial data signal DATA turns to be the high level.

After that, the clock signal TCLK is delayed by the buffer30by the time period T2, resulting in the high level signal S1. From the signal S1and the signal S2, which the signal S1delayed by the buffer31and the inverter32by the time period T1, the AND circuit33generates a superposition pulse, which has a pulse width T1. The superposition pulse propagates in the AND circuit34, and within the period of the superposition pulse, the PMOS transistor37is turned off, and the NMOS transistor38is turned on. Due to this, a low-level superposition pulse is inserted into the serial data signal DATA, when the clock signal TCLK is at the high level.

Next, when the master transmission/reception circuit2transmits data “0” to the slave transmission/reception circuit SLk, the data signal DHo is constantly at the low level; hence, the signal S5from the AND circuit34is fixed at the low level, and in the serial data signal DATA, there is no low-level superposition pulse generated when the clock signal TCLK is at the high level.

When the clock signal TCLK turns to the low level, since the PMOS transistor37is turned off, the serial data signal DATA declines slowly due to the pull down resistance5. During signal transmission, the slave transmission/reception circuit SLk is required to generate a pulse with a specified time period from the falling time of the clock signal TCLK. However, if the falling edge of the clock signal TCLK is smoothed, sometimes, the slave transmission/reception circuit SLk may fail to generate pulses; thus, it is required that the falling edge of the clock signal TCLK to be sharp.

The AND circuit39, buffers40,41, and the inverter42constitute the circuit for generating pulses at the falling time of the clock signal TCLK. When the clock signal TCLK goes down, a high-level pulse signal is output to the OR circuit36.

Upon receiving the high-level pulse signal from the AND circuit39, the OR circuit36turns on the NMOS transistor38, and within the high-level period of the pulse. Due to this, the transmission path4quickly drops to the low level, and in the serial data signal DATA output from the master transmission/reception circuit2, both the rising edge and the falling edge are sharp.

Next, a description is made of data transmission from the slave transmission/reception circuit SLk.

The master transmission/reception circuit2supplies the slave transmission/reception circuit SLk shown inFIG. 6with the serial data signal DATA through the transmission path4.

The serial data signal DATA is delayed by the buffers81,82of the T2delay circuit71by the time period T2, and is output as the signal S21.

The signal S21is further delayed and inverted by the buffer83and the inverter84, and then, the NOR circuit85outputs the signal S23after the time period T2elapses from the falling time of the clock signal TCLK as the superposition pulse having a pulse width T1. The signal S23is input to a corresponding input terminal of the AND circuit86.

The output data signal DSo from the slave device SCk is latched for a while at the rising time of the signal S21which is input to the clock signal input terminal CK of the D flip-flop96. The resistor111, the condenser112, and the inverter113of the T4delay circuit101delay the clock signal TCLK input from the transmission path4by a time period T4, and generate the signal S32. The signal S32is also input to a corresponding input terminal of the AND circuit86.

When the superposition pulse having a pulse width T1from the NOR circuit85is input to the AND circuit86after the time period T2elapses from the falling time of the clock signal TCLK, and when the output data signal DSo is at the high level, and within the time period T4from the falling time of the clock signal TCLK, the AND circuit86outputs the signal S23from the NOR circuit85as the signal S24. Once the signal S24is generated, the PMOS transistor92is turned on, and the PMOS transistor92drives the transmission path4to the high level. When the signal S24begins to go down after time T1elapses, the PMOS transistor92is turned off, and the transmission path4is in the high impedance state, hence the level of the signal S24decreases to the low level slowly due to the pull-down resistance5.

However, this mechanism is not suitable for high speed operations. Hence, the signal S24from the AND circuit86is delayed by the buffers88to91, and is input to the gate of the NMOS transistor93. The signal S28delayed by the buffers88to91turns on the NMOS transistor93after the PMOS transistor92is turned off, thereby causing the transmission path4to quickly to drop to the low level. Since the signal S28is a pulse signal, after the transmission path4is at the low level, the NMOS transistor93is turned off and becomes the high impedance state, but the transmission path4is fixed to the low level by the pull-down resistance5.

Next, a description is made of a process in which the slave transmission/reception circuit SLk receives signals transmitted from the master transmission/reception circuit2.

When the master transmission circuit11outputs the serial data signal DATA to the transmission path4, the slave reception circuit14delays the serial data signal DATA transmitted from the transmission path4with the T2delay circuit71, and generates the signal S21. The output signal S21from the T2delay circuit71is input to the clock signal input terminal CK of the D flip-flop96.

When the master transmission circuit11outputs the serial data signal DATA representing “1” to the transmission path4, a narrow low-level superposition pulse is inserted after the rising time of the serial data signal DATA; therefore, both of the rising edge of the serial data signal DATA and the rising edge of the low-level superposition pulse having a pulse width of T1are available.

Since the D flip-flop96is configured to invert the output signal at the rising time of the signal input to the clock signal input terminal CK, if the D flip-flop96receives the rising edge of the signal input to the clock signal input terminal CK twice, the output signal is inverted twice and is returned to the original level state.

The serial data signal DATA coming from the transmission path is delayed by the T4delay circuit101by a time period T4, is further delayed by the input signal delay circuit102, and is input to the clock signal input terminal CK of the D flip-flop117.

The signal input to the data input terminal D of the D flip-flop117is an inverted output signal from the D flip-flop116, and the inverted output signal from the D flip-flop116is at the low level, in other words, when detecting twice the rising edge of the signal S21input to the clock signal input terminal CK of the D flip-flop116, the high level data input signal DSi is output in response to the signal reception.

When the master transmission circuit11does not output the superposition pulse to the transmission path4, that is, when the master transmission circuit11outputs the serial data signal DATA representing “0” to the transmission path4, since a rising edge of a signal level is supplied to the clock signal input terminal CK of the D flip-flop116only once, the inverted output signal from the D flip-flop116is at the low level. Hence, the D flip-flop117outputs the data input signal DSi at the low level. Because the D flip-flop116is a toggle, once the initial state of the signal level of the inverted output signal is inverted, all the subsequent data input signals DSi may be inverted, too. In order to avoid such a danger, the D flip-flop116is constantly reset by the initialization circuit104after supplying data to the D flip-flop117, so as to compensate for the initial state.

The serial data signal DATA is delayed by the T4delay circuit101by the time period T4, and outputs the signal S32. The signal S32is further delayed by the input signal delay circuit102and becomes the signal S33. The signal S33is input to the clock signal input terminal CK of the D flip-flop117, and is used for transferring the output signal from the D flip-flop116.

Further, the initialization circuit104generates a reset pulse signal S34from the signal S33, and input the reset pulse signal S34to the reset signal input terminal R of the D flip-flop116. Due to this, after transferring data to the D flip-flop117, the D flip-flop116is reset by the initialization circuit104, so as to maintain the initial state.

FIG. 8AthroughFIG. 8Jshow a timing chart corresponding to the waveforms inFIG. 5andFIG. 6, illustrating a process in which the master transmission circuit11transmits data “1”.

As illustrated inFIG. 8AthroughFIG. 8J, the inverted output signal S35from the D flip-flop116is at the high level initially because of the reset pulse signal S34from the initialization circuit104.

The signal S21input to the clock signal input terminal CK of the D flip-flop116is generated when the serial data signal DATA passes through the T2delay circuit71. Hence, the inverted output signal S35from the D flip-flop116is inverted at the rising time of the signal level of the serial data signal DATA. When data “1” is included in the serial data signal DATA, the superposition pulse having a pulse width T1is inserted after the time period T2elapses from the rising time of the serial data signal DATA.

For this reason, the inverted output signal S35from the D flip-flop116is inverted again at the rising time of the superposition pulse, thus the inverted output signal S35from the D flip-flop116returns to the high level.

After that, at the rising time of the signal S33, which is delayed at the rising time of the serial data signal DATA, the D flip-flop117latches the inverted output signal S35from the D flip-flop116to propagate the data “1” from the master transmission circuit11.

FIG. 9AthroughFIG. 9Jshow a timing chart illustrating a process in which the master transmission circuit11transmits data “0”.

As illustrated inFIG. 9AthroughFIG. 9J, when the master transmission circuit11transmits data “0”, the low-level superposition pulse is not inserted when the serial data signal DATA is at the high level. Due to this, the inverted output signal S35from the D flip-flop116is inverted at the rising time of the signal level of the serial data signal DATA and turned to the low level. In this state, at the rising time of the signal S33, which is generated after the serial data signal DATA is delayed, the D flip-flop117latches the low level of the signal S35so as to propagate the data “0” from the master transmission circuit11.

Under this state, if the rising edge of the next serial data signal DATA is received with the inverted output signal S35from the D flip-flop116being at the low level, the data from the master transmission circuit11cannot be propagated correctly. Due to this, after the D flip-flop117latches the low level of the signal S35, the reset signal S34is generated, and the inverted output signal S35from the D flip-flop116is reset to the initial high level. In doing so, in each cycle, the serial data signal DATA from the master transmission circuit11can be propagated correctly.

Next, a description is made of a process in which the master transmission/reception circuit2receives signals transmitted from the slave transmission/reception circuit SLk.

When the slave transmission/reception circuit SLk transmits data to the master transmission/reception circuit2, the serial data signal DATA from the master transmission/reception circuit2is used as the clock signal. After the falling edge of the serial data signal DATA corresponding to the falling edge of the clock signal TCLK is detected, a high-level pulse is generated.

FIG. 10AthroughFIG. 10Mshow a timing chart illustrating a process in which the slave transmission/reception circuit SLk transmits data “1”.

As illustrated inFIG. 10AthroughFIG. 10M, when the slave transmission/reception circuit SLk transmits data “1” to the master transmission/reception circuit2, a high-level superposition pulse is inserted when the clock signal TCLK is at the low level.

FIG. 11AthroughFIG. 11Mshow a timing chart illustrating a process in which the slave transmission/reception circuit SLk transmits data “0”.

As illustrated inFIG. 11AthroughFIG. 11M, when the slave transmission/reception circuit SLk transmits data “0” to the master transmission/reception circuit2, the high-level superposition pulse is not inserted when the serial data signal DATA is at the low level, which corresponds to the low level of the clock signal TCLK.

When the slave transmission/reception circuit SLk transmits data to the master transmission/reception circuit2, the high-level superposition pulse is inserted when the transmission path4is at the low level. However, in this state, because the master transmission/reception circuit2does not drive the transmission path4, in other words, the transmission path4is in the high impedance state, in which both the PMOS transistor37and the NMOS transistor38are turned off, data conflict does not occur.

InFIG. 10, the output data signal DSo is latched in the D flip-flop96at the rising time of the serial data signal DATA. This is for the purpose of preventing the slave transmission/reception circuit SLk from starting pulse transmission again erroneously with the falling edge of the superposition pulse as a trigger when the superposition pulse is inserted into the serial data signal DATA in the slave transmission/reception circuit SLk.

When the output data signal DSo is at the high level, a high level signal is latched in the D flip-flop96at the rising time of the serial data signal DATA, and the output signal S25of the D flip-flop96turns to the high level. After the time period T2elapses from the falling time of the serial data signal DATA, the superposition pulse having a pulse width T1is output from the NOR circuit85.

The signal S25corresponding to the output data signal DSo from the slave device SCk, the superposition pulse signal S23output from the NOR circuit85, and the signal S32which is obtained by delaying the serial data signal DATA by the time T4are input to the corresponding input terminals of the AND circuit86.

When the serial data signal DATA goes down to the low level, if the signal S25of the D flip-flop96is at the low level, the PMOS transistor37is turned on, and a high level pulse is output to the transmission path4. This pulse goes to the low level after the time period T1, and although the PMOS transistor37is turned off, the voltage on the transmission path4decreases slowly-due to the pull-down resistance5. However, this condition prevents the transmission speed from being increased, and may cause malfunction of the device.

In order to avoid this problem, when the slave transmission circuit13turns off the PMOS transistor92, the NMOS transistor93is turned on for a short time period. Due to this, it is possible to generate a signal having a sharp falling edge on the transmission path4. The signal, which is obtained by delaying the output signal from the AND circuit86with the buffers88to91, is input to the gate of the NMOS transistor93.

Here, even when the signals on the transmission path4drops to the low level, under such a condition, the slave transmission/reception circuit SLk may detect a falling edge of the superposition pulse, which is inserted when the serial data signal DATA is at the low level, and generate a pulse, causing oscillation in which the above operations are repeatedly performed.

In order to avoid the oscillation, when the NMOS transistor93is turned on to cause signals on the transmission path4to go to the low level, the signal28, which is input to the gate of the NMOS transistor93, is used to reset the D flip-flop96to set the output signal S25to the low level. In doing so, it is possible to prevent the slave transmission/reception circuit SLk from successively outputting signals. As illustrated inFIG. 10AthroughFIG. 10M, the falling edge of the signal on the transmission path4is detected, and two pulses are generated in the signal S23. The first pulse is generated in order to transmit data “1”. When the second pulse is generated, since the D flip-flop96is reset, and the output signal S25is at the low level, there is no output signal from the AND circuit86, and the aforesaid oscillation is preventable.

Next, a description is made of a process in which the master transmission/reception circuit2receives signals transmitted from the slave transmission/reception circuit SLk.

When extracting data from the received signals, the master transmission/reception circuit2uses the signal S4, which is obtained by delaying the signal on the transmission path4by the time period T4, and the signal S13, which is obtained by delaying the signal S4in the input signal delay circuit43. With the T4delay circuit42, the signal S12decreases slowly at the falling time of the signal on the transmission path4.

As shown inFIG. 10AthroughFIG. 10M, after the time period T4elapses, the signal S12exceeds the threshold value of the inverter53, and the output signal S4from the inverter53is inverted.

Similar to the slave transmission/reception circuit SLk, the master transmission/reception circuit2supplies the serial data signal DATA on the transmission path to the D flip-flop57as the clock signal, but in the master reception circuit12, it is the signal inverted by the inverter56that is supplied to the D flip-flop57.

In the D flip-flop57, a signal output from the inverted output terminal QB is input to the data input terminal D to toggle the internal state at the rising time of the signal input to the clock signal input terminal CK. In the initial state of the D flip-flop57, an inverted output signal S15is inverted to a high level by the signal S14, which is input to the reset signal input terminal R of the D flip-flop57. In this state, when the D flip-flop57detects a falling edge of the serial data signal DATA, the inverted output signal S15is inverted. After that, when a high-level superposition pulse from the slave transmission/reception circuit SLk is inserted into the serial data signal DATA, the D flip-flop57inverts the inverted output signal S15again, and the inverted output signal S15turns to the high level. Due to the signal S13, which is the serial data signal DATA delayed in the T4delay circuit42and further delayed in the input signal delay circuit43, the inverted output signal S15of the D flip-flop57is latched in the D flip-flop58.

In this way, from the D flip-flop58, the data “1” from the slave transmission/reception circuit SLk is transmitted to the host device HC. Because the D flip-flop57is a toggle, if the initial state is not stable, the signals cannot be correctly propagated. In order to avoid such a problem, once the D flip-flop57detects a rising edge of the serial data signal DATA, the D flip-flop57is reset by the initialization circuit45. In doing so, the initial state is stable in each cycle. As for the pulse signal for this reset operation, by performing a logical OR operation of a signal obtained by inverting the signal S13with the inverter59, and the signal S4in the OR circuit60, the reset pulse S14is generated after a certain time period elapses from the rising time of the serial data signal DATA. In this way, because the condition of the D flip-flop57is initialized at the rising time of the serial data signal DATA, and the data from the slave transmission/reception circuit SLk is received at the falling time of the serial data signal DATA, the condition of the D flip-flop57can be constantly stabilized.

As shown inFIG. 11AthroughFIG. 11M, when the master transmission/reception circuit2receives data “0” from the slave transmission/reception circuit SLk, in the slave transmission/reception circuit SLk, a low level portion of the output data signal DSo is latched in the D flip-flop96at the rising time of the serial data signal DATA to set the signal S25to the low level. Afterward, when the D flip-flop57detects a falling edge of the serial data signal DATA, the NOR circuit85outputs a pulse having a pulse width T1, and the signal S25is at the low level. Hence, the pulse output from the NOR circuit85is not output from the AND circuit86.

Under this state, in the master reception circuit12, the D flip-flop57toggles to set the inverted output signal S15to the low level at the falling time of the serial data signal DATA. Because there is no pulse indicating the data “1” from the slave transmission/reception circuit SLk in the serial data signal DATA, the inverted output signal S15at the low level is latched in the D flip-flop58at the rising time of the signal S13. In doing so, the data “0” is transmitted from the slave transmission/reception circuit SLk to the master transmission/reception circuit2.

After that, the reset signal is generated in the signal S14at the rising time of the serial data signal DATA, and the D flip-flop57is reset to the initial state, so as to correctly receive data from the slave transmission/reception circuit SLk at the next falling time of the serial data signal DATA.

In the above descriptions, it is exemplified that the transmission path4is pulled down by the pull down resistance5. However, the present invention is also applicable to the case in which the transmission path4is pulled up by a pull-up resistance7.

FIG. 12is a block diagram schematically illustrating another example of the serial communication device according to an embodiment of the present invention.

FIG. 13exemplifies a circuit diagram of the master transmission/reception circuit2inFIG. 12.

InFIG. 13, the same reference numbers are assigned to the same elements as those shown inFIG. 5, and overlapping descriptions are omitted with the difference between them is explained.

FIG. 14exemplifies a circuit diagram of the slave transmission/reception circuit SLk inFIG. 12.

InFIG. 14, the same reference numbers are assigned to the same elements as those shown inFIG. 6, and overlapping descriptions are omitted with the difference between them is explained.

InFIG. 13, being different fromFIG. 5, in the master transmission circuit11, the ExNOR circuit35is replaced by a NOR circuit35a, the OR circuit36is replaced by an ExNOR circuit36a. In the master reception circuit12, the buffer41is replaced by an inverter41a.

With the master transmission/reception circuit2inFIG. 13, signals input to the gates for driving the PMOS transistor37, and the NMOS transistor38are changed, the output signal from the NOR circuit35ais input to the gate of the PMOS transistor37, and the output signal from the ExNOR circuit36ais input to the gate of the NMOS transistor38. The serial data signal DATA is inverted in the inverter41aand is supplied to the master reception circuit12.

Therefore, when the clock signal TCLK is at the high level, the serial data signal DATA is at the low level, and when data “1” is transferred to the slave transmission/reception circuit SL1through SLn in this period, the output signal S5from the AND circuit34is input to the gate of the PMOS transistor37and the gate of the NMOS transistor38, and a high level pulse is superposed on the serial data signal DATA when the serial data signal DATA is at the low level. When the clock signal TCLK goes down to the low level, both the PMOS transistor37and the KMOS transistor38are turned off, and the output terminal of the master transmission circuit11turns to be a high impedance state.

Although the transmission path4increases slowly to the high level due to the pull up resistance7, because of the output signal S8from the AND circuit39, the PMOS transistor37is turned on for a short time period, and is turned off again. Due to this, when the transmission path4is pulled up by the pull up resistance7, the serial data signal DATA stays at the high level for a short time, the transmission path4is fixed to the high level by the pull up resistance7, and the output terminal of the master transmission circuit11is in the high impedance state and is stable.

InFIG. 14, being different fromFIG. 6, in the slave transmission/reception circuit SLk, the inverter87is replaced by a buffer87a, and the buffer91is replaced by an inverter91a.

With the slave transmission/reception circuit SLk inFIG. 14, signals are input to the gates for driving the PMOS transistor92and the NMOS transistor93.

When the serial data signal DATA changes from the low level to the high level, and when data “1” from the slave transmission/reception circuit SLk is transmitted to the master transmission/reception circuit2, the pulse signal from the AND circuit86is output, and this pulse signal turns on the PMOS transistor92for a short time and for the first time.

Hence, when the serial data signal DATA changes to the low level, the PMOS transistor92is turned off, and after that, the signal24is delayed by the buffers88to90, is inverted by the inverter91a, and is input to the gate of the NMOS transistor93, to turn on the NMOS transistor93for a short time. Due to this, when the transmission path4is pulled up by the pull up resistance7, the serial data signal DATA stays at the high level for a short time, the transmission path4is fixed to the high level by the pull up resistance7, and the output terminal of the slave transmission circuit13is in the high impedance state and is stable.

FIG. 16AthroughFIG. 16Mshow a timing chart illustrating operations of the slave transmission/reception circuit SLk shown inFIG. 14.

As described above, even when the transmission path4is pulled up, the master transmission/reception circuit2can communicate with the slave transmission/reception circuits SL1through SLn.

While the present invention is above described with reference to specific embodiments chosen for purpose of illustration, it should be apparent that the invention is not limited to these embodiments, but numerous modifications could be made thereto by those skilled in the art without departing from the basic concept and scope of the invention.

This patent application is based on Japanese Priority Patent Application No. 2004-193040 filed on Jun. 30, 2004.