Transistor and display device

A transistor whose characteristic degradation due to stray light is small is provided. The transistor includes a first insulator, a second insulator over the first insulator, a metal oxide over the second insulator, a first and a second conductor over the metal oxide, a third insulator over the first insulator, the second insulator, the metal oxide, the first conductor, and the second conductor, a fourth insulator over the metal oxide, a fifth insulator over the fourth insulator, and a third conductor over the fifth insulator. The third insulator has an opening to overlap with a region between the first conductor and the second conductor. The fourth insulator, the fifth insulator, and the third conductor are positioned in the opening. The metal oxide has a bandgap greater than or equal to 3.3 eV. The transistor has Vsh higher than or equal to −0.3 V.

BACKGROUND OF THE INVENTION

1. Field of the Invention

One embodiment of the present invention relates to a transistor, a semiconductor device, a display device, and an electronic device. Another embodiment of the present invention relates to manufacturing methods of a transistor, a semiconductor device, and a display device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a memory device are each an embodiment of a semiconductor device. A display device (e.g., a liquid crystal display device and a light-emitting display device), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, and the like are sometimes regarded as including a semiconductor device.

2. Description of the Related Art

In recent years, higher definition display panels have been demanded. Examples of devices that require high-definition display panels include a smartphone, a tablet terminal, and a laptop computer. Furthermore, higher definition has been required for a stationary display device such as a television device or a monitor device along with an increase in resolution. A device absolutely required to have a high-definition display panel is a device for virtual reality (VR) or augmented reality (AR).

Examples of the display device that can be used for a display panel include, typically, a liquid crystal display device, a light-emitting apparatus including a light-emitting element such as an organic electroluminescent (EL) element or a light-emitting diode (LED), and electronic paper performing display by an electrophoretic method or the like.

Although the transistors used in these display devices have mainly used a semiconductor material such as silicon, attention has been drawn to a technique in which a metal oxide exhibiting semiconductor characteristics is used for transistors instead of the semiconductor material such as silicon in recent years. For example, in Patent Documents 1 and 2, a technique is disclosed in which a transistor using zinc oxide or an In—Ga—Zn-based oxide as a semiconductor layer is used in a pixel of a display device.

REFERENCE

Patent Document

SUMMARY OF THE INVENTION

A transistor used in a display device or the like is required to have high reliability. For example, part of light (stray light) emitted by a light-emitting element in the display device enters the transistor in some cases. In such a case, the stray light might cause a degradation of transistor characteristics and adversely affect an image to be displayed.

An object of one embodiment of the present invention is to provide a transistor whose characteristic degradation due to stray light is small. Another object of one embodiment of the present invention is to provide a display device in which a degradation in transistor characteristics due to stray light is small. Another object of one embodiment of the present invention is to provide a display device with stable pixel operation. Another object of one embodiment of the present invention is to provide a semiconductor device with a small variation in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a miniaturized or highly integrated semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present invention does not need to achieve all these objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

One embodiment of the present invention relates to a transistor including a metal oxide in a channel formation region. The transistor includes the following: a first insulator; a second insulator over the first insulator; a metal oxide over the second insulator; a first conductor and a second conductor over the metal oxide; a third insulator over the first insulator, the second insulator, the metal oxide, the first conductor, and the second conductor; a fourth insulator over the metal oxide; a fifth insulator over the fourth insulator; and a third conductor over the fifth insulator. In the third insulator, an opening is formed to overlap with a region between the first conductor and the second conductor. The fourth insulator, the fifth insulator, and the third conductor are positioned in the opening. The metal oxide has a bandgap greater than or equal to 3.3 eV. The transistor has Vshhigher than or equal to −0.3 V.

In the above transistor, the metal oxide preferably contains In, Ga, and Zn, and the atomic ratio of In to Ga and Zn is preferably 2:6:5 or in its vicinity.

In the above transistor, the fifth insulator preferably contains silicon and oxygen and includes a region in which the nitrogen concentration obtained by SIMS is lower than or equal to 5×1019atoms/cm3.

Another embodiment of the present invention relates to a display device including the transistor and a light-emitting element electrically connected to the transistor. The light-emitting element includes a lower electrode, an upper electrode, and a light-emitting layer between the lower electrode and the upper electrode. In a cross-sectional observation of the light-emitting element, the light-emitting element includes a region where a side surface of the lower electrode and a side surface of the light-emitting layer are aligned or substantially aligned with each other.

In the above display device, an insulator is preferably included between the light-emitting element and an adjacent light-emitting element and includes one or both of an inorganic material and an organic material.

Another embodiment of the present invention is a display device including a first to a fourth wiring, a light-emitting element, a first capacitor, a second capacitor, and a first to a fourth transistor. In the first transistor, one of a source and a drain is electrically connected to the first wiring, the other of the source and the drain is electrically connected to one electrode of the first capacitor, and a gate is electrically connected to the second wiring. In the second transistor, one of a source and a drain is electrically connected to an anode of the light-emitting element, the other of the source and the drain is electrically connected to the third wiring, and a gate is electrically connected to the one electrode of the first capacitor. In the third transistor, one of a source and a drain is electrically connected to the fourth wiring, and the other of the source and the drain is electrically connected to the anode of the light-emitting element. In the fourth transistor, one of a source and a drain is electrically connected to the fourth wiring, and the other of the source and the drain is electrically connected to the one electrode of the first capacitor. The other electrode of the first capacitor is electrically connected to the anode of the light-emitting element. One electrode of the second capacitor is electrically connected to the one electrode of the first capacitor, and the other electrode of the second capacitor is electrically connected to the third wiring. The first transistor includes a metal oxide in a channel formation region. The first transistor has Vshhigher than or equal to −0.3 V.

In the above display device, the metal oxide preferably contains In, Ga, and Zn, and the atomic ratio of In to Ga and Zn is preferably 2:6:5 or in its vicinity.

According to one embodiment of the present invention, a transistor whose characteristic degradation due to stray light is small can be provided. According to one embodiment of the present invention, a display device in which a degradation in transistor characteristics due to stray light is small can be provided. According to one embodiment of the present invention, a display device with stable pixel operation can be provided. According to one embodiment of the present invention, a semiconductor device with a small variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. According to one embodiment of the present invention, a miniaturized or highly integrated semiconductor device can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

Note that the description of these effects does not preclude the existence of other effects. In one embodiment of the present invention, there is no need to achieve all the effects. Other effects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

DETAILED DESCRIPTION OF THE INVENTION

In the drawings, sizes, layer thicknesses, or regions are sometimes exaggerated for clarity. Therefore, the scale is not limited to those illustrated in the drawings. Note that the drawings are schematic views showing ideal examples, and embodiments of the present invention are not limited to shapes or values shown in the drawings. For example, in the actual manufacturing process, a layer, a resist mask, or the like might be unintentionally reduced in size by treatment such as etching, which is not illustrated in some cases for easy understanding. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and explanation thereof will not be repeated in some cases. The same hatching pattern is used for portions having similar functions, and the portions are not denoted by specific reference numerals in some cases.

In a top view (also referred to as a plan view), a perspective view, or the like, especially, some components might not be illustrated for easy understanding of the invention. In addition, some hidden lines and the like might not be shown.

The ordinal numbers such as “first” and “second” in this specification and the like are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, description can be made even when “first” is replaced with “second”, “third”, or the like as appropriate. In addition, the ordinal numbers in this specification and the like are not necessarily the same as those used to specify one embodiment of the present invention.

In this specification and the like, the terms for describing arrangement, such as “over”, “above”, “under”, and “below”, are used for convenience to describe a positional relation between components with reference to drawings. The positional relation between components is changed as appropriate in accordance with the direction from which each component is described. Thus, the positional relation is not limited to that described with a term used in this specification and can be explained with other terms as appropriate depending on the situation.

For example, when this specification and the like explicitly state that X and Y are connected, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are regarded as being disclosed in this specification and the like. Accordingly, without limitation to a predetermined connection relation, for example, a connection relation shown in drawings or text, another connection relation is regarded as being disclosed in the drawings or the text. Here, X and Y each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

In this specification and the like, a transistor is an element having at least three terminals of a gate, a drain, and a source. The transistor includes a region where a channel is formed (hereinafter also referred to as a channel formation region) between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, a channel formation region refers to a region through which current mainly flows.

Furthermore, functions of a source and a drain might be switched when transistors of opposite polarity are employed or a direction of current flow is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can be interchanged in some cases in this specification and the like.

Note that a channel length refers to, for example, a distance between a source (source region or source electrode) and a drain (drain region or drain electrode) in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap each other or in a channel formation region in a top view of the transistor. In one transistor, channel lengths in all regions are not necessarily the same. In other words, the channel length of one transistor is not fixed to one value in some cases. Therefore, in this specification, the channel length is any one of values, the maximum values, the minimum value, or the average value in a channel formation region.

A channel width refers to, for example, the length of a channel formation region perpendicular to a channel length direction in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or in the channel formation region in a top view of the transistor. In one transistor, channel widths in all regions are not necessarily the same. In other words, the channel width of one transistor is not fixed to one value in some cases. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a channel formation region.

Note that in this specification and the like, depending on the transistor structure, a channel width in a region where a channel is actually formed (hereinafter also referred to as an effective channel width) is different from a channel width shown in a top view of a transistor (hereinafter also referred to as an apparent channel width) in some cases. For example, in a transistor having a gate electrode covering the side surface of a semiconductor, the effective channel width is larger than the apparent channel width, and its influence cannot be ignored in some cases. As another example, in a miniaturized transistor having a gate electrode covering the side surface of a semiconductor, the proportion of a channel formation region formed on the side surface of the semiconductor is sometimes increased. In that case, the effective channel width is larger than the apparent channel width.

In such cases, an effective channel width is sometimes difficult to estimate by measuring. For example, to estimate an effective channel width from a design value, it is necessary to assume that the shape of a semiconductor is known. Accordingly, in the case where the shape of a semiconductor is not known exactly, it is difficult to measure an effective channel width accurately.

In this specification, the simple term “channel width” denotes an apparent channel width in some cases. In other cases, the simple term “channel width” denotes an effective channel width. Note that the values of a channel length, a channel width, an effective channel width, an apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image and the like.

Note that an impurity in a semiconductor refers to, for example, elements other than the main components of the semiconductor. For example, an element with a concentration lower than 0.1 atomic % is regarded as an impurity. When a semiconductor contains an impurity, an increase in density of defect states or a reduction in crystallinity of the semiconductor may occur, for example. In the case where the semiconductor is an oxide semiconductor, examples of an impurity that changes the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor. Specific examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water also serves as an impurity in some cases. Entry of an impurity may cause oxygen vacancies (VO) in an oxide semiconductor, for example.

In this specification and the like, silicon oxynitride contains more oxygen than nitrogen. Silicon nitride oxide contains more nitrogen than oxygen.

In this specification and the like, the term “insulator” can be replaced with an insulating film or an insulating layer. The term “conductor” can be replaced with a conductive film or a conductive layer. The term “semiconductor” can be replaced with a semiconductor film or a semiconductor layer.

In this specification and the like, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°. Thus, the case where the angle is greater than or equal to −5° and less than or equal to 5° is also included. The term “substantially parallel” indicates that the angle formed between two straight lines is greater than or equal to −30° and less than or equal to 30°. The term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°. Thus, the case where the angle is greater than or equal to 85° and less than or equal to 95° is also included. In addition, the term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°.

In this specification and the like, a metal oxide means an oxide of metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also simply referred to as an OS), and the like. For example, a metal oxide used in a semiconductor layer of a transistor is referred to as an oxide semiconductor in some cases. That is, an OS transistor is a transistor including a metal oxide or an oxide semiconductor.

In this specification and the like, the term “normally off” means that the drain current per micrometer of channel width that flows through a transistor when no potential or a ground potential is supplied to its gate is lower than or equal to 1×10−20A at room temperature, lower than or equal to 1×1018A at 85° C., or lower than or equal to 1×10−16A at 125° C.

In this specification, in the case where the maximum value and the minimum value are specified, a structure in which the maximum value and the minimum value are freely combined is disclosed.

In this specification and the like, a device formed using a metal mask or a fine metal mask (FMM) may be referred to as a device having a metal mask (MM) structure. In this specification and the like, a device formed without using a metal mask or an FMM may be referred to as an element having a metal maskless (MML) structure.

In this specification and the like, a structure in which light-emitting layers are separately formed or patterned to make light-emitting devices for emission colors (e.g., blue (B), green (G), and red (R)) is called a side by side (SBS) structure in some cases. In this specification and the like, a light-emitting device capable of emitting white light is called a white light-emitting device in some cases. Note that a white light-emitting device can be a full-color-display light-emitting device by being combined with a coloring layer (e.g., a color filter).

The light-emitting devices can be roughly classified into a single structure and a tandem structure. It is preferable that a device having a single structure include one light-emitting unit between a pair of electrodes and the light-emitting unit include one or more light-emitting layers. To obtain white light emission, two or more light-emitting layers may be selected such that emission colors of the light-emitting layers are complementary colors. Thus, the emission colors of the first light-emitting layer and the second light-emitting layer are made complementary, so that the whole light-emitting device can emit white light, for example. This can be applied to a light-emitting device including three or more light-emitting layers.

It is preferable that a device having a tandem structure include two or more light-emitting units between a pair of electrodes and each light-emitting unit include one or more light-emitting layers. To obtain white light emission, white light may be obtained by combining light emitted from light-emitting layers of a plurality of light-emitting units. Note that the structure that can provide white light emission is similar to that of the single structure. In the device having a tandem structure, an intermediate layer such as a charge-generation layer is preferably provided between the plurality of light-emitting units.

When the above-described white light-emitting device (including a single structure or a tandem structure) and a light-emitting device having an SBS structure are compared, the light-emitting device having an SBS structure can have lower power consumption than the white light-emitting device. In the case where power consumption is required to be low, the light-emitting device having an SBS structure is preferably used. In contrast, the white light-emitting device is preferable in that the manufacturing cost is low and the manufacturing yield is high because a process for manufacturing the white light-emitting device is easier than that for the light-emitting device having an SBS structure.

In this embodiment, an example of a semiconductor device including a transistor200of one embodiment of the present invention and a manufacturing method thereof will be described with reference toFIG.1AtoFIG.21C.

Structure Example of Semiconductor Device

A structure of a semiconductor device including the transistor200is described with reference toFIGS.1A to1D.FIGS.1A to1Dare a top view and cross-sectional views of the semiconductor device including the transistor200.FIG.1Ais the top view of the semiconductor device.FIGS.1B to1Dare the cross-sectional views of the semiconductor device.FIG.1Bis a cross-sectional view taken along the dashed-dotted line A1-A2inFIG.1A, which corresponds to a cross-sectional view in the channel length direction of the transistor200.FIG.1Cis a cross-sectional view taken along the dashed-dotted line A3-A4inFIG.1A, which is a cross-sectional view of the transistor200in the channel width direction.FIG.1Dis a cross-sectional view taken along the dashed-dotted line A5-A6inFIG.1A. Note that for simplification, some components are not illustrated in the top view inFIG.1A.

The semiconductor device of one embodiment of the present invention includes, an insulator212over a substrate (not illustrated), an insulator214over the insulator212, the transistor200over the insulator214, an insulator280over the transistor200, an insulator282over the insulator280, an insulator283over the insulator282, and an insulator285over the insulator283. The insulators212,214,280,282,283, and285each function as an interlayer film. The semiconductor device also includes a conductor240aand a conductor240bthat are electrically connected to the transistor200and function as a plug. An insulator241ais provided in contact with a side surface of the conductor240a, and an insulator241bis provided in contact with a side surface of the insulator240b. A conductor246athat is electrically connected to the conductor240aand functions as a wiring is provided over the insulator285and the conductor240a, and a conductor246bthat is electrically connected to the conductor240band functions as a wiring is provided over the insulator285and the conductor240b.

Note that the conductor240aand the conductor240bare sometimes collectively referred to as a conductor240in the following description. The insulator241aand the insulator241bare collectively referred to as an insulator241in some cases. The conductor246aand the conductor246bare collectively referred to as a conductor246in some cases.

The insulator241ais provided in contact with an inner wall of an opening formed in the insulators280,282,283, and285, and the conductor240ais provided in contact with the side surface of the insulator241a. The insulator241bis provided in contact with an inner wall of an opening formed in the insulators280,282,283, and285, and the conductor240bis provided in contact with the side surface of the insulator241b. Each of the insulator241aand the insulator241bhas a structure in which a first insulator is provided in contact with the inner wall of the opening and a second insulator is provided on the inner side of the first insulator. The conductor240a(conductor240b) has a structure in which a first conductor is provided in contact with the side surface of the insulator241a(insulator241b) and a second conductor is provided on the inner side of the first conductor. The top surface of the conductor240a(conductor240b) can be substantially level with the top surface of the insulator285in a region overlapping with the conductor246a(conductor246b).

Note that in the semiconductor device of one embodiment of the present invention, the insulator241a(the insulator241b) has the structure in which a first insulator and a second insulator are stacked; however, the present invention is not limited to this structure. For example, the insulator241a(insulator241b) may have a single-layer structure or a stacked-layer structure of three or more layers. In addition, in the transistor200, the conductor240a(conductor240b) has the structure in which a first conductor and a second conductor are stacked; however, the present invention is not limited to this structure. For example, the conductor240a(conductor240b) may have a single-layer structure or a stacked-layer structure of three or more layers. In the case where a component has a stacked-layer structure, layers may be distinguished by ordinal numbers corresponding to the formation order.

As illustrated inFIGS.1A to1D, the transistor200includes an insulator216over the insulator214, a conductor205(a conductor205aand a conductor205b) provided to be embedded in the insulator216, an insulator222over the insulator216and the conductor205, an insulator224over the insulator222, an oxide230over the insulator224, a conductor242aover the oxide230, an insulator271aover the conductor242a, a conductor242bover the oxide230, an insulator271bover the conductor242b, an insulator252over the oxide230, an insulator250over the insulator252, an insulator254over the insulator250, a conductor260(a conductor260aand a conductor260b) over the insulator254and overlapping with part of the oxide230, and an insulator275over the insulator222, the insulator224, the oxide230, the conductor242a, the conductor242b, the insulator271a, and insulator271b. Here, as illustrated inFIGS.1B and1C, the insulator252is in contact with the top surface of the insulator222, the side surface of the insulator224, the top surface and the side surface of the oxide230, the side surfaces of the conductors242aand242b, the side surfaces of the insulator271aand the insulator271b, the side surfaces of the insulators275and280, and the bottom surface of the insulator250. The top surface of the conductor260is positioned so as to be substantially aligned with the uppermost portions of the insulators254,250, and252and the top surface of the insulator280. In addition, the insulator282is in contact with at least parts of the top surfaces of the conductor260, the insulators252,250,254, and280.

Note that in this specification and the like, the expression “substantially level with” indicates a structure having the same level from a reference surface (e.g., a flat surface such as a substrate surface) in a cross-sectional view. For example, in a manufacturing process of the semiconductor device, planarization treatment (typically, CMP treatment) is performed, whereby the surface(s) of a single layer or a plurality of layers are exposed in some cases. In this case, the surfaces on which the CMP treatment is performed is at the same level as a reference surface. In addition, the expression “substantially level with” includes the case of leveling with each other. However, a plurality of layers may be on the different levels, in some cases, depending on a treatment apparatus, a treatment method, or a material of the treated surfaces, used for CMP treatment. This case is also included in the scope of “substantially level with” in this specification and the like. For example, in a structure where two layers (here, given as a first layer and a second layer) have different two levels with respect to the reference surface, the difference in the top-surface level between the first and second layers is less than or equal to 20 nm, in which case the structure is regarded to have the surfaces substantially leveling with each other.

Hereinafter, the conductor242aand the conductor242bare collectively referred to as a conductor242in some cases. The insulator271aand the insulator271bare collectively referred to as an insulator271in some cases.

An opening reaching the oxide230is provided in the insulators280and275. The insulators252,250, and254and the conductor260are positioned in the opening. The conductor260and the insulators252,250,254are provided between the conductor242aand the conductor242band between the insulator271aand the insulator271bin the channel length direction of the transistor200. The insulator254includes a region in contact with the side surface of the conductor260and a region in contact with the bottom surface of the conductor260.

Note that the transistor200includes a single-layer oxide230; however, one embodiment of the present invention is not limited to this structure. For example, the oxide230may have a stacked-layer structure of two or more layers.

The conductor260functions as a first gate (also referred to as a top gate) electrode and the conductor205functions as a second gate (also referred to as a back gate) electrode. The insulators252,250and254function as a first gate insulator, and the insulators222and224function as a second gate insulator. Note that the gate insulator is also referred to as a gate insulating layer or a gate insulating film in some cases. The conductor242afunctions as one of a source electrode and a drain electrode, and the conductor242bfunctions as the other of the source electrode and the drain electrode. A region of the oxide230that overlaps with the conductor260at least partly functions as a channel formation region.

In the transistor200, a metal oxide functioning as a semiconductor (hereinafter such a metal oxide is also referred to as an oxide semiconductor) is preferably used for the oxide230including a channel formation region.

In the case where the transistor200is used in a pixel circuit of a display device, part of light (stray light) emitted by a light-emitting element in the display device might enter the transistor200. In that case, the stray light sometimes causes a degradation in transistor characteristics and adversely affects pixel operation.

The degradation of the transistor characteristics due to light is estimated as follows. First, when a metal oxide functioning as a semiconductor of a transistor is irradiated with light, electrons (carriers) in the valence band or a deep level of the metal oxide is excited into the conduction band of the metal oxide. Here, the deep level of the metal oxide is presumed to be attributed to oxygen vacancies in the metal oxide. Next, holes are generated in the valence band or the deep level of the metal oxide by electron excitation into the conduction band of the metal oxide. When a negative bias is applied between the gate and the source, holes are accumulated at the interface between the metal oxide and the gate insulator and in the vicinity thereof. At this time, when a defect state exists at the interface and in the vicinity thereof, holes are trapped by the defect state. Thus, the threshold voltage or the shift voltage (Vsh) is shifted in the negative direction. Consequently, the transistor has normally-on characteristics and adversely affects the pixel operation.

The stray-light-induced degradation amount of transistor characteristics can be evaluated using the amount of change in the threshold voltage or the shift voltage (Vsh) measured in a negative bias temperature illumination stress (NBTIS) test of the transistor. The shift voltage (Vsh) is defined as Vgat which, in a drain current (Id)-gate voltage (Vg) curve of a transistor, the tangent at a point where the slope of the curve is the steepest intersects the straight line of Id=1 pA. The degradation that the threshold voltage or Vas of the transistor varies in the NBTIS test is referred to as negative-bias stress temperature photodegradation.

Accordingly, it is preferable to reduce the influence of stray light on the transistor200used in the pixel circuit of the display device. For example, it is preferable to reduce the stray-light-induced degradation of transistor characteristics for the transistor200used in the pixel circuit of the display device. Specifically, the transistor200used in the pixel circuit of the display device preferably has high resistance to the NBTIS test (reduces negative-bias stress temperature photodegradation).

The metal oxide functioning as a semiconductor of the transistor200preferably has a bandgap greater than or equal to 3.1 eV, further preferably greater than or equal to 3.3 eV. The energy of light having a wavelength greater than or equal to 400 nm is less than or equal to 3.1 eV. In other words, even when light having a wavelength greater than or equal to 400 nm enters the metal oxide, electrons in the valence band are less likely to be excited into the conduction band. Thus, when a metal oxide having a wider bandgap is used in a channel formation region of the transistor, the resistance to the NBTIS test can be increased. That is, with use of a metal oxide having a wider bandgap in a channel formation region of the transistor, influence of stray light can be reduced even when a light-blocking layer or the like is not provided, so that degradation of the transistor characteristics can be suppressed.

The bandgap of the metal oxide can be evaluated optically using one or a plurality of a spectrophotometer, spectroscopic ellipsometry, a photoluminescence method, X-ray photoelectron spectroscopy (XPS), electron spectroscopy for chemical analysis (ESCA), an X-ray absorption fine structure (XAFS), and the like.

For example, as the oxide230, a metal oxide such as an In-M-Zn oxide containing indium, an element M, and zinc is used; the element M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like. Specifically, the element M is preferably one or more kinds selected from gallium, aluminum, gallium, yttrium, and tin. Gallium is further preferable.

Specifically, it is preferable for the oxide230to use a metal oxide film with an atomic ratio where In:M:Zn=2:6:5 or a composition in the neighborhood thereof, an atomic ratio where In:M:Zn=1:3:4 or a composition in the neighborhood thereof, an atomic ratio where In:M:Zn=1:1:1 or a composition in the neighborhood thereof, an atomic ratio where In:M:Zn=1:4:5 or a composition in the neighborhood thereof. Note that the neighborhood of the atomic ratio includes ±30% of an intended atomic ratio. When the metal oxide is deposited by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide and may be the atomic ratio of a sputtering target used for depositing the metal oxide.

For example, in the case of describing an atomic ratio of In to M and Zn that is 2:6:5 or a composition in the neighborhood thereof, the case is included in which with the atomic proportion of In being 2, the atomic proportion of M is greater than or equal to 4 and less than or equal to 8 and the atomic proportion of Zn is greater than or equal to 3 and less than or equal to 7.5. In the case of describing an atomic ratio of In and M to Zn that is 1:1:1 or a composition in the neighborhood thereof, the case is included in which with the atomic proportion of In being 1, the atomic proportion of M is greater than 0.1 and less than or equal to 2 and the atomic proportion of Zn is greater than 0.1 and less than or equal to 2.

Note that the composition of the metal oxide can be evaluated by an inductively coupled plasma-mass spectrometry (ICP-MS), XPS, scanning electron microscopy (SEM)-energy dispersive X-ray spectroscopy (EDX), secondary ion mass spectrometry (SIMS), or the like.

In particular, a metal oxide deposited by sputtering using an oxide target whose atomic ratio (In:M:Zn) is 1:3:4 has a bandgap that is approximately 3.4 eV, which can be favorably used as the oxide230. Note that the metal oxide deposited by sputtering using an oxide target whose atomic ratio (In:M:Zn) is 1:3:4 has an atomic ratio where In:M:Zn=2:6:5 or a composition in the neighborhood thereof. That is, the metal oxide with an atomic ratio where In:M:Zn=2:6:5 or a composition in the neighborhood thereof has a bandgap that is approximately 3.4 eV.

A gallium atom has a stronger strength of bonding with an oxygen atom than an indium atom has. Thus, the metal oxide in which an atomic ratio of gallium to main metal elements is higher than or equal to an atomic ratio of indium to the main metal elements is used as the oxide230, whereby oxygen vacancies in the oxide230can be reduced in some cases.

Furthermore, there is a case where due to the negative bias, holes generated in the metal oxide by light irradiation are trapped by defect states existing at an interface between the metal oxide and a gate insulator or in the gate insulator, so that the threshold voltage or Vshvaries. Thus, it is preferable to reduce the density of defect states in the gate insulator to prevent the negative-bias stress temperature photodegradation.

When silicon oxide or silicon oxynitride is used as the gate insulator, the defect states (levels) relating to the negative-bias stress temperature photodegradation include a defect state attributed to oxygen, a defect state attributed to nitrogen, and the like. As nitrogen to which the defect state is attributed, a nitrogen atom bonded to two silicon atoms can be given, for example. The nitrogen atom has a dangling bond. As oxygen to which the defect state is attributed, an oxygen atom bonded to one silicon atom can be given, for example. The oxygen atom has a dangling bond. Due to these dangling bonds, holes might be trapped, and the threshold voltage or Vshvaries in some cases. In the following description, a nitrogen atom bonded to two silicon atoms is denoted by No in some cases. In addition, an oxygen atom bonded to one silicon atom is denoted by a non-bridging oxygen hole center (NBOHC) in some cases.

In order to reduce the defect state attributed to nitrogen, the amount of nitrogen atoms having dangling bonds in the gate insulator is preferably reduced. The quantification of nitrogen atoms having dangling bonds in the gate insulator is difficult in some cases. Therefore, the amount of nitrogen atoms having dangling bonds in the gate insulator is preferably evaluated with the nitrogen concentration in the gate insulator, for example. In a gate insulator with a small amount of nitrogen atoms, the amount of nitrogen atoms having dangling bonds is presumed to be small. Specifically, the nitrogen concentration in the gate insulator, which is measured by SIMS, is preferably lower than 2×1020atoms/cm3, further preferably lower than or equal to 1×1020atoms/cm3, still further preferably lower than or equal to 5×1019atoms/cm3.

Note that it is difficult to detect a nitrogen atom as a single ion (N+or N−) in SIMS. Therefore, a nitrogen atom in the gate insulator is preferably detected as a cluster ion of SiN.

In the case where the gate insulator has a stacked-layer structure of two or more layers, the nitrogen concentration of the layer containing silicon oxide or silicon oxynitride is preferably reduced. In the transistor200included in the semiconductor device inFIGS.1A to1D, part of each of the insulators222,224,252,250, and254functions as a gate insulator. Thus, silicon oxide or silicon oxynitride with a low nitrogen concentration is preferably used in one or more of the insulators222,224,252,250, and254. In particular, a silicon oxide or silicon oxynitride with a low nitrogen concentration is preferably used as the insulator250.

Silicon oxide or silicon oxynitride with a low nitrogen concentration can be deposited by a sputtering method, a chemical vapor deposition (CVD) method, an atomic layer deposition (ALD) method, or the like. For example, an insulating film to be the insulator250is deposited on bottom and side surfaces of an opening formed in the insulator280and the like to have favorable coverage. Therefore, in the case where silicon oxide or silicon oxynitride is used as the insulator250, an insulating film to be the insulator250is preferably deposited by a CVD method or an ALD method. In particular, an ALD method enables film formation to have excellent step coverage and excellent thickness uniformity and thus is suitable for depositing an insulating film to be the insulator250.

As the defect level relating to the negative-bias stress temperature photodegradation, a level attributed to a defect formed by diffusion of atoms in the gate insulator into the metal oxide, a level attributed to a defect formed by diffusion of atoms in the metal oxide into the gate insulator, or the like can be given. For example, as the defect generated by diffusion of atoms in the metal oxide into the gate insulator, a defect in which silicon atoms in the silicon oxide or silicon oxynitride are replaced with metal atoms in the metal oxide can be given. When the metal oxide is an In—Ga—Zn oxide, a defect in which a silicon atom is replaced with an indium atom, a gallium atom, or a zinc atom can be given as the defect. In this specification, a defect in which a silicon atom is replaced with an indium atom is referred to as InSi, a defect in which a silicon atom is replaced with a gallium atom is referred to as GaSi, and a defect in which a silicon atom is replaced with a zin atom is referred to as ZnSi.

The crystallinity of the metal oxide is preferably high in order to prevent formation of defects such as InSi, GaSi, and ZnSi. When the crystallinity of the metal oxide is high, a metal element contained in the metal oxide can be prevented from diffusing into the gate insulator. Furthermore, diffusion of an atom (e.g., silicon atom) contained in the gate insulator to the metal oxide can be suppressed.

In the above manner, the influence of stray light on the transistor200can be reduced even when a light-blocking layer or the like is not provided, and accordingly the degradation of transistor characteristics can be inhibited. As a result, a transistor whose characteristic degradation due to stray light is small can be provided. Furthermore, with use of such a transistor, a display device in which deterioration in transistor characteristics due to stray light is small can be provided. Furthermore, a display device with stable pixel operation can be provided.

Here, a defect in agate insulator is described using calculation. In this section, the gate insulator is silicon oxide, and the metal oxide is an In—Ga—Zn oxide. As a defect that may be a cause of negative-bias stress temperature photodegradation in this case, a defect such as NBOHC, InSi, GaSi, or ZnSican be given.

First, a silicon oxide model in an amorphous state (denoted by a-SiO2model) as a reference is prepared. The a-SiO2model consists of 20 silicon atoms and 40 oxygen atoms.

A calculation model including one NBOHC is made in the following manner: one silicon atom in the a-SiO2model is removed to form four NBOHCs and then one hydrogen atom is bonded to each of three out of the four NBOHCs. A calculation model including one InSiis made by replacing one silicon atom in the a-SiO2model with an In atom. A calculation model including one GaSiis made similarly by replacing one silicon atom in the a-SiO2model with a Ga atom. A calculation model including one ZnSiis made similarly by replacing one silicon atom in the a-SiO2model with a Zn atom.

The feasibility of formation of defects in the gate insulator is described below with use of results of first-principles calculation. Specifically, each of formation energies of InSi, GaSi, ZnSi, and NBOHC is calculated by the first-principles calculation, and the feasibility of defect formation in the gate insulator is evaluated.

Here, formation energy of each defect (InSi, GaSi, ZnSi, and NBOHC) is described. In this specification, formation energy of a defect is calculated using the following formulae. A defect whose formation energy is lower can be regarded as being formed more easily.
ΔE(XSi)=E(XSi)−{E(no defect)−μSi+μX}
ΔE(NBOHC)=E(NBOHC)−{E(no defect)−μSi+3μH}  [Formula 1]

In the above formulae, ΔE(XSi) represents a formation energy of XSi, and an atom X is an In atom, a Ga atom, or a Zn atom. ΔE(NBOHC) represents a formation energy of NBOHC. E(XSi) represents a total energy of the calculation model including one XSi, and E(NBOHC) represents a total energy of the calculation model including one NBOHC. E(no defect) represents a total energy of the calculation model (a-SiO2model) without a defect. μSirepresents a chemical potential of a silicon atom, μXrepresents a chemical potential of an atom X, and μHrepresents a chemical potential of a hydrogen potential.

The chemical potential of a silicon atom (μSi), the chemical potential of an atom X (μX), and the chemical potential of a hydrogen atom (μH) are calculated using the following formulae.

In the above formulae, μOrepresents a chemical potential of an oxygen atom. E(O2) represents a total energy of an oxygen molecule (O2), E(SiO2) represents a total energy of silicon oxide, E(XaOb) represents a total energy of a metal oxide (XaOb), and E(H2O) represents a total energy of a water molecule (H2O). In the case where the atom X is an In atom or a Ga atom, a is 2, and b is 3. In the case where the atom X is a Zn atom, a is 1, and b is 2.

The above is the description of the formation energy of a defect.

First, the atom relaxation calculation is performed on the calculation model with one defect (any one of InSi, GaSi, ZnSi, and NBOHC). Calculation conditions are as follows.

In the first-principles calculation, software VASP (Vienna Ab-initio Simulation Package) was used. For the exchange-correlation potential, Perdew-Burke-Ernzerhof (PBE) type generalized gradient approximation (GGA) was used, and for the ion potential, a projector augmented wave (PAW) method was used. The cut-off energy was 800 eV, and the grid of only r-point was used for the k-point. Note that the charge state of the whole model was neutral.

With the above formulae, the formation energy of each defect was calculated. Table 1 shows the formation energies of the defects.

Table 1 shows that the formation energy of NBOHC is the lowest and suggests that NBOHC is easily formed. Among InSi, GaSi, and ZnSi, the formation energy of ZnSiis higher than the formation energies of InSiand GaSi. Thus, ZnSiis estimated to be less likely to be formed than InSiand GaSi.

<<Graph of Density of States>>

FIG.2Ashows the density of states of the calculation model including one InSion which the atom relaxation calculation was performed. InFIG.2A, the horizontal axis represents energy [eV], and the vertical axis represents the density of states (DOS) [arbitrary unit (arb. unit)]. Note that inFIG.2A, the valence band maximum was adjusted to be at 0 eV on the horizontal axis.

According toFIG.2A, a deep defect level (a level1inFIG.2A) exists above the valence band maximum. This suggests that the defect level is to be a level trapping holes. Furthermore, a level (a level2inFIG.2A) exists in the vicinity of the conduction band minimum. The level corresponds to an s-orbital of an In atom, which suggests that the level is to be a level trapping electrons.

FIG.2Bshows a density of states of the calculation model including one GaSion which the atom relaxation calculation was performed. InFIG.2B, the horizontal axis represents energy [eV], and the vertical axis represents the density of states (DOS) [arbitrary unit (arb. unit)]. Note that inFIG.2B, the valence band maximum was adjusted to be at 0 eV on the horizontal axis.

According toFIG.2B, a defect level (a level inFIG.2B) exists in the upper portion of the valence band maximum. This suggests that the defect level is to be a level trapping holes.

<<Transition Level of Defect>>

A level involving transition to a different charge state, which is also called a transition level, exists in an energy gap, depending on the kind of defect. This causes capture or release of carriers depending on the depth of the level and the position of the Fermi level. Thus, this section describes calculation of the transition level of a defect with first-principles calculation.

The transition levels of defects that can be formed in the gate insulator were calculated. Such defects are specifically NBOHC, InSi, GaSi, and ZnSi. Thus, in the calculation of the transition level, a calculation model including one NBOHC, a calculation model including one InSi, a calculation model including one GaSi, and a calculation model including one ZnSiare used.FIGS.3A to3Dshow the calculation models used for the transition level calculation.FIG.3Ais the calculation model including one NBOHC,FIG.3Bis the calculation model including one InSi,FIG.3Cis the calculation model including one GaSi, andFIG.3Dis the calculation model including one ZnSi. Note that InSi, GaSi, and ZnSiare the defects formed by replacing one Si atom in the gate insulator with an In atom, a Ga atom, and a Zn atom, respectively, that is, with atoms different from the Si. That is, InSi, GaSi, and ZnSican be referred to as substitutional defects.

The transition level of the defect is calculated from the formation energy of the defect having charges. The formation energy Eform(defect, q) of a defect having a charge q is calculated with the following formula.

Here, E(defect, q) is an energy of a calculation model including a defect having a charge q, and E(no defect) is an energy of a calculation model (a-SiO2model) without a defect. X1 represents an atom having a change in the number of atoms due to defect generation, and nX1represents the number of atoms X1 increased or decreased. In the case where the number of atoms X1 is increased, the value of nX1is positive; in the case where the number of atoms X1 is decreased, the value of nX1 is negative. μX1represents a chemical potential of the atom X1. εVBMrepresents an energy of the valence band maximum, and EFrepresents an energy of a Fermi level when the energy at the valence band maximum is regarded as a reference. In other words, the Fermi level, EF=0 V, is located on the valence band maximum. Note that the energy at the Fermi level is denoted by a Fermi energy in some cases below.

In addition, ΔV represents an electrostatic energy correction, which is represented by the following formula. A finite-sized calculation model is used in calculation of the transition level of the defect; the electrostatic potential due to charge does not converge even at a portion far from the defect. Thus, the electrostatic potential V(q, r) at the atomic position r in the calculation model including the defect of the charge q and the electrostatic potential V(0, r) at the atomic position r in the calculation model without a neutrally charged defect are calculated, and an average value of the difference between V(q, r) and V(0, r) at the position far from the defect (r=far) is regarded as ΔV.
ΔV=[V(q,r)−V(0,r)]r=far[Formula 4]

The transition level ε(q/q′) of the defect is calculated with the following formula.

The value of ε(q/q′) obtained from the above formula represents the transition level of the defect when the valence band maximum is set to 0.0 eV. In other words, the value obtained by subtracting the transition level of the defect from the energy gap represents a transition level of the defect when the conduction band minimum is regarded as a reference. In the case where the Fermi level is located on the valence band side beyond ε(q/q′), the defect is in the charge state q, which means stable. In the case where the Fermi level is located on the conduction band side beyond ε(q/q′), the defect is in the charge state q′, which means stable.

In the first-principles calculation, VASP was used. The Heyd-Scuseria-Ernzerhof (HSE) hybrid functional (HSE06) was used as a hybrid functional, the Perdew-Burke-Ernzerhof (PBE) generalized gradient approximation (GGA) was used for an exchange-correlation potential, and a projector augmented-wave (PAW) method was used for the ion potential. The cut-off energy was 800 eV, and the k-point grid points was 3×3×3. In addition, the screening parameter of the HSE functional was 2 nm−1, and the fraction of the Hartree-Fock exchange term was 0.25.

FIG.4shows the transition levels of defects calculated. InFIG.4, the vertical axis represents the Fermi energy [eV].FIG.4shows the transition levels of NBOHC, InSi, GaSi, and ZnSiin this order from left to right. InFIG.4, the position where the Fermi energy is 0 eV represents the valence band maximum (VBM), and the position where the Fermi energy is 6.89 eV represents the conduction band minimum (CBM). The transition level ε(2/0) is denoted by a solid line, the transition level ε(1/0) is denoted by a dashed line, the transition level ε(0/−1) is denoted by a dashed-dotted line, and the transition level ε(−1/−2) is denoted by a dotted line. Note thatFIG.4shows values of the transition levels of the defects.

According toFIG.4, the transition level ε(2/0) of NBOHC exists at a position of 0.51 eV from the valence band maximum; the transition level ε(2/0) of InSiexists at a position of 0.12 eV from the valence band maximum; and the transition level ε(2/0) of GaSiexists at a position of 0.32 eV from the valence band maximum. Being located around the valence band maximum, the transition levels ε(2/0) of NBOHC, InSi, and GaSiare each presumed as a hole trap level. In other words, the hole trap levels derived from InSiand GaSiare located on the valence band side more than the hole trap level derived from NBOHC. Therefore, InSiand GaSigenerated in the gate insulator are estimated to have hole trap properties.

In contrast, the transition level ε(1/0) of ZnSiexists at a position of 1.04 eV from the valence band maximum. Being located around the valence band maximum, the transition level ε(1/0) of ZnSiis presumed as a hole trap level. In other words, since the hole trap level derived from ZnSiis located closer to the conduction band than the hole trap levels derived from NBOHC, InSi, and GaSi, ZnSiis presumed to have lower hole trap properties than NBOHC, InSi, and GaSi.

From the above, it is presumed that, in the case of using an In—Ga—Zn oxide as an oxide semiconductor, the defects (InSiand GaSi) which could be generated by diffusion of In and Ga into the gate insulator induce the formation of hole trap levels, which could be a cause of the negative-bias stress temperature photodegradation.

<<Diffusion of Metal Atom in Metal Oxide into Gate Insulator>>

In this section, diffusion of metal atoms in a metal oxide into a gate insulator is described using calculation. Note that diffusion of metal atoms in a metal oxide into a gate insulator can also be referred to as a release of metal atoms from the metal oxide. In this section, the gate insulator is silicon oxide, the metal oxide is an In—Ga—Zn oxide.

As a defect in the In—Ga—Zn oxide, oxygen vacancy (VO) can be given. In addition, the metal atoms around the oxygen vacancy are presumed to be released more easily, from the metal oxide, than metal atoms located far away from the oxygen vacancy. In other words, it is assumed that the metal atom diffused from the metal oxide into the gate insulator is a metal atom in the vicinity of the oxygen vacancy. Thus, the energy of releasing the metal atom around VOis calculated by first-principles calculation.

Here, a calculation model used for first-principles calculation is described. First, a model of an In—Ga—Zn oxide having a single crystal structure is prepared. Hereinafter, the In—Ga—Zn oxide model having a single crystal structure is denoted by a sc-IGZO model. The compositions of the sc-IGZO model is In:Ga:Zn:O=1:1:1:4 [atomic ratio]. The sc-IGZO model is composed of 112 atoms.

Next, one oxygen atom is removed from the sc-IGZO model. The removed oxygen atom is an oxygen atom bonded to indium and zinc. The sc-IGZO model from which the oxygen atom has been removed has oxygen vacancy. In the following description, the model is referred to as a sc-IGZO model having oxygen vacancy in some cases.FIG.5shows the sc-IGZO model having oxygen vacancy. InFIG.5, VOrepresents oxygen vacancy, In-1 represents one of indium atoms adjacent to VOshown inFIG.5, In-2 represents another of the indium atoms adjacent to VOshown inFIG.5, Zn represents a zinc atom adjacent to VOshown inFIG.5, Ga-1 represents one of gallium atoms adjacent to Zn shown inFIG.5, and Ga-2 represents another of the gallium atoms adjacent to Zn shown inFIG.5.

Next, from the sc-IGZO model having oxygen vacancy, the In-1, the In-2, the Ga-1, the Ga-2, or the Zn shown inFIG.5is separately removed. Specifically, a sc-IGZO model having oxygen vacancy, from which the In-1 is removed, is prepared; a sc-IGZO model having oxygen vacancy, from which the In-2 is removed, is prepared; a sc-IGZO model having oxygen vacancy, from which the Ga-1 is removed, is prepared; a sc-IGZO model having oxygen vacancy, from which the Ga-2 is removed, is prepared; and a sc-IGZO model having oxygen vacancy, from which the Zn is removed, is prepared.

With the above five calculation models, an energy of releasing a metal atom X2 (the In-1, the In-2, the Ga-1, the Ga-2, or the Zn) was calculated. The energy of releasing the metal atom X2, ΔE(VO, X2), was calculated with the following formula. As the value of the energy of releasing the metal atom X2, ΔE(VO, X2), is smaller, the metal atom X2 is more easily released.
ΔE(VO,X2)=E(VO,X2)−{E(VO)−μX2}  [Formula 6]

In the above formula, ΔE(VO, X2) represents an energy of releasing the metal atom X2, E(VO, X2) represents a total energy of the sc-IGZO model having oxygen vacancy, from which the metal atom X2 is removed, E(VO) represents a total energy of the sc-IGZO model having oxygen vacancy, and μX2represents a chemical potential of the metal atom X2.

Table 2 shows calculation results of the energy of releasing the metal atom X2.

According to Table 2, the zinc atom adjacent to VO(the Zn shown inFIG.5) is presumed to be released easily. The energy of releasing the In-1 is a negative value, and the energy of releasing the In-2 is low. On the basis of the results, the indium atoms adjacent to VOare also presumed to be released easily. In contrast, the energy of releasing the Ga-1 is 1.29 eV and lower than that of releasing the Ga-2. From these results, in the metal atoms around VO, the zinc atom and the indium atom are presumed to be released more easily than the gallium atom. In other words, the results suggest that, in the case of using an In—Ga—Zn oxide as a metal oxide, metal atoms easily diffusing into a gate insulator are zinc and indium atoms.

As described above, in an In—Ga—Zn oxide, zinc and indium atoms are implied as metal atoms easily diffusing into a gate insulator. ZnSiand InSiare examples of substitutional defects that could be generated when zinc and indium atoms diffuse into the gate insulator. Thus, the formation energies of ZnSiand InSiare calculated. For the calculation method of the ZnSiand InSiformation energies, the description in <<Defect formation energy>> can be referred to. In addition, for the conditions of calculating the formation energies of ZnSiand InSi, the description in <<Transition level of defect>> can be referred to.

Table 3 shows the formation energies of ZnSiand InSi. Here, metal atoms contained in the metal oxide, which diffuse into the gate insulator, are called diffusing atomic species. When the diffusing atomic species is an In atom, the defect formed by diffusion of the In atom is InSi. When the diffusing atomic species is a Zn atom, the defect formed by diffusion of the Zn atom is ZnSi.

According to Tables 2 and 3, it is conceivable that although the zinc atom is easily released from the metal oxide, the substitutional defect ZnSiis less likely to be formed. On the other hand, in the case of the indium atom, although a release from the metal oxide is not easily caused as compared to that of the zinc atom, the substitutional defect InSiis easily formed as compared to the case of the zinc atom. On the basis of the results, it is conceivable that the indium atom easily diffuses in to the gate insulator.

The above is the description of the defects in the gate insulator.

Details of a structure of the semiconductor device illustrated inFIGS.1A to1Dare described below.

The oxide230preferably exhibits crystallinity. In particular, as the oxide230, a c-axis-aligned crystalline oxide semiconductor (CAAC-OS) is preferably used.

The CAAC-OS is a metal oxide having a dense structure with high crystallinity and a low amount of impurities and defects (e.g., oxygen vacancies). In particular, after the formation of a metal oxide, heat treatment is performed at a temperature at which the metal oxide does not become a polycrystal (e.g., higher than or equal to 400° C. and lower than or equal to 600° C.), whereby a CAAC-OS having a dense structure with higher crystallinity can be obtained. As the density of the CAAC-OS is increased in such a manner, diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

When an oxide having crystallinity, such as CAAC-OS, is used as the oxide230, oxygen extraction from the oxide230by source or drain electrodes can be inhibited. In this case, extraction of oxygen from the oxide230can be inhibited even when heat treatment is performed; hence, the transistor200is stable against high temperatures in the manufacturing process (i.e., thermal budget).

By contrast, in the CAAC-OS, a reduction in electron mobility due to a crystal grain boundary is less likely to occur because it is difficult to observe a clear crystal grain boundary. Thus, a metal oxide including the CAAC-OS is physically stable. Accordingly, the metal oxide including the CAAC-OS is resistant to heat and has high reliability.

FIG.6Ais an enlarged view of the vicinity of the channel formation region inFIG.1B. As illustrated inFIG.6A, the oxide230includes a region230bcfunctioning as the channel formation region of the transistor200and a region230baand a region230bbthat are provided to sandwich the region230bcand function as a source region and a drain region. At least part of the region230bcoverlaps with the conductor260. In other words, the region230bcis provided between the conductor242aand the conductor242b. The region230bais provided to overlap with the conductor242a, and the region230bbis provided to overlap with the conductor242b.

The region230bcfunctioning as the channel formation region has a smaller amount of oxygen vacancies or a lower impurity concentration than the regions230baand230bb, i.e., is a high-resistance region with a low carrier concentration. Thus, the region230bccan be regarded as being i-type (intrinsic) or substantially i-type.

The regions230baand230bbfunctioning as the source and the drain regions have a large amount of oxygen vacancies or a high concentration of impurities such as hydrogen, nitrogen, and a metal element, i.e., are low-resistance regions with a high carrier concentration. In other words, the region230baand the region230bbare each a n-type region having a higher carrier concentration and a lower resistance than the region230bc.

The carrier concentration in the region230bcfunctioning as the channel formation region is preferably lower than or equal to 1×1018cm−3, further preferably lower than 1×107cm−3, still further preferably lower than 1×1016cm−3, yet further preferably lower than 1×103cm−3, and yet still further preferably lower than 1×1012cm−3. Note that the lower limit of the carrier concentration in the region230bcfunctioning as the channel formation region is not particularly limited and can be, for example, 1×10−9cm−3.

A region having a carrier concentration lower than or equal to that of the region230ba(230bb) and higher than or equal to that of the region230bcmay be formed between the region230bcand the region230ba(230bb). That is, the region functions as a junction region between the region230bcand the region230ba(230bb). The hydrogen concentration in the junction region is sometimes lower than or equal to that in the region230ba(230bb) and higher than or equal to that in the region230bc. The amount of oxygen vacancies in the junction region is sometimes smaller than or equal to that in the region230ba(230bb) and larger than or equal to that in the region230bc.

In the oxide230, the boundaries between the regions are difficult to clearly observe in some cases. The concentration of a metal element and an impurity element such as hydrogen or nitrogen, which is detected in each region, may be gradually changed not only between the regions but also in each region. That is, the region closer to the channel formation region preferably has a lower concentration of a metal element and an impurity element such as hydrogen or nitrogen.

If impurities and oxygen vacancies exist in a channel formation region of an oxide semiconductor, a transistor including the oxide semiconductor might have variable electrical characteristics and poor reliability. In some cases, a defect that is an oxygen vacancy into which hydrogen enters (hereinafter also referred to as VOH in some cases) generates an electron serving as a carrier. Therefore, when the channel formation region in the oxide semiconductor includes oxygen vacancies, the transistor tends to have normally-on characteristics (the channel is generated even when no voltage is applied to the gate electrode and current flows through the transistor). Thus, impurities, oxygen vacancies, and VOH are preferably reduced as much as possible in the channel formation region in the oxide semiconductor. In other words, the channel formation region in the oxide semiconductor is an i-type (intrinsic) or substantially i-type region with a low carrier concentration.

In contrast, when an insulator containing oxygen that is released by heating (hereinafter, also referred to as excess oxygen) is provided in the vicinity of the oxide semiconductor and heat treatment is performed, oxygen can be supplied from the insulator to the oxide semiconductor so as to reduce oxygen vacancies and VOH. Note that too much oxygen supplied to the source region or the drain region might cause a decrease in the on-state current or the field-effect mobility of the transistor200. Furthermore, a variation in the amount of oxygen supplied to the source region or the drain region on the substrate plane leads to variable characteristics of the semiconductor device including the transistor.

Hence, the region230bcfunctioning as the channel formation region in the oxide semiconductor is preferably an i-type or substantially i-type region with a low carrier concentration, whereas the regions230baand230bbfunctioning as the source and drain regions are preferably n-type regions with a high carrier concentration. That is, it is preferable that in the oxide semiconductor, oxygen vacancies and VOH in the region230bcbe reduced and supply of too much oxygen to the regions230baand230bbbe prevented.

Thus, in this embodiment, microwave treatment is performed in an atmosphere containing oxygen in a state where the conductor242aand the conductor242bare provided over the oxide230so that oxygen vacancies and VOH in the region230bcare reduced. Here, the microwave treatment refers to, for example, treatment using an apparatus including a power source that generates high-density plasma with use of a microwave. Note that in this specification and the like, a microwave refers to an electromagnetic wave having a frequency from 300 MHz to 300 GHz, inclusive in some cases.

The microwave treatment in an oxygen-containing atmosphere converts an oxygen gas into plasma using a microwave or a high-frequency wave such as RF and activates the oxygen plasma. At this time, the region230bccan be irradiated with the microwave or the high-frequency wave such as RF. By the effect of the plasma, the microwave, or the like, VOH in the region230bccan be divided into oxygen vacancy (VO) and hydrogen (H); the hydrogen can be removed from the region230bcand the oxygen vacancy VOcan be filled with oxygen. That is, the reaction “VOH→H+VO” occurs in the region230bc, so that the hydrogen concentration in the region230bccan be reduced. As a result, oxygen vacancies and VOH in the region230bccan be reduced to lower the carrier concentration.

In the microwave treatment in an oxygen-containing atmosphere, the effect of the microwave, the high-frequency wave such as RF, the oxygen plasma, and the like is blocked by the conductor242aand the conductor242band does not reach the regions230baand230bb. In addition, the effect of the oxygen plasma can be reduced by the insulator271, the insulator275, and the insulator280that are provided to cover the oxide230and the conductor242. Hence, a reduction in VOH and supply of too much oxygen due to the microwave treatment do not occur in the regions230baand230bb, preventing a decrease in carrier concentration therein.

Oxygen supplied into the region230bchas a variety of forms such as an oxygen atom, an oxygen molecule, an oxygen ion, and an oxygen radical (also referred to as O radical which is an atom, a molecule or an ion having an unpaired electron). The oxygen supplied to the region230bcpreferably has one or more of the above forms. An oxygen radical is particularly preferable.

The microwave treatment is preferably performed in an oxygen-containing atmosphere after the formation of an insulating film to be the insulator252and/or after the formation of an insulating film to be the insulator250. The microwave treatment is performed in an oxygen-containing atmosphere through the insulator252and/or the insulator250, whereby oxygen can be supplied efficiently into the region230bc. In addition, the insulator252is provided to be in contact with the side surface of the conductor242and the surface of the region230bc, whereby an excess amount of oxygen is prevented from being supplied to the region230bc, and the side surface of the conductor242can be prevented from being oxidized. Furthermore, the side surface of the conductor242can be prevented from being oxidized when an insulating film to be the insulator250is formed.

In the above manner, the amount of oxygen vacancies and VOH can be selectively removed from the region230bcin the oxide semiconductor, whereby the region230bccan be an i-type or substantially i-type region. Furthermore, supply of an excess amount of oxygen to the region230baand the region230bbfunctioning as the source and drain regions can be inhibited and the n-type regions on which the microwave treatment is performed can be maintained. As a result, a variation in the electrical characteristics of the transistor200can be inhibited, and thus variation in the electrical characteristics of the transistors200in the substrate plane can be inhibited.

As illustrated inFIG.1C, a curved surface may be provided between the side and top surfaces of the oxide230in a cross-sectional view in the channel width direction of the transistor200. In other words, the end portion of the side surface and the end portion of the top surface may be curved (rounded).

The radius of curvature of the curved surface is preferably greater than 0 nm and less than the thickness of the oxide230in a region overlapping with the conductor242, or less than half of the length of a region of the top surface of the oxide230that does not have the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than or equal to 20 nm, preferably greater than or equal to 1 nm and less than or equal to 15 nm, and further preferably greater than or equal to 2 nm and less than or equal to 10 nm. Such a shape can improve the coverage of the oxide230with the insulator252, the insulator250, the insulator254, and the conductor260.

As illustrated inFIG.1Cor the like, the insulator252formed using aluminum oxide or the like is provided in contact with the top and side surfaces of the oxide230, whereby indium contained in the oxide230is unevenly distributed, in some cases, at the interface between the oxide230and the insulator252and in its vicinity. Accordingly, the vicinity of the surface of the oxide230comes to have an atomic ratio close to that of an indium oxide or that of an In—Zn oxide. When the proportion of indium atoms in the vicinity of the surface of the oxide230is increased in the above manner, the field-effect mobility of the transistor200can be improved.

At least one of the insulators212,214,271,275,282,283, and285preferably functions as a barrier insulating film that inhibits diffusion of impurities such as water or hydrogen from the substrate side or from above the transistor200into the transistor200. Thus, at least one of the insulators212,214,271,275,282,283, and285is preferably formed using an insulating material having a function of inhibiting diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, and NO2), and copper atoms, that is, an insulating material through which the impurities are less likely to pass. Alternatively, it is preferable to use an insulating material having a function of inhibiting diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like), that is, an insulating material through which the oxygen is less likely to pass.

Note that in this specification, a barrier insulating film refers to an insulating film having a barrier property. A barrier property in this specification means a function of inhibiting diffusion of a particular substance (also referred to as a function of less easily transmitting the substance). Alternatively, a barrier property in this specification means a function of capturing or fixing (also referred to as gettering) a particular substance.

An insulator having a function of inhibiting diffusion of oxygen and impurities such as hydrogen and water is preferably used for the insulators212,214,271,275,282,283, and285, and examples of the insulator includes aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. For example, silicon nitride, which has a high hydrogen barrier property, is preferably used for the insulators212,275, and283. For example, aluminum oxide or magnesium oxide, which has a function of capturing or fixing more hydrogen, is preferably used for the insulators214,271,282, and285. Accordingly, impurities such as water and hydrogen can be inhibited from diffusing from the substrate side to the transistor200side through the insulators212and214. Furthermore, impurities such as water or hydrogen can be inhibited from diffusing to the transistor200side from an interlayer insulating film and the like positioned outside the insulator285. In addition, oxygen contained in the insulator224and the like can be inhibited from diffusing to the substrate side through the insulators212and214. Oxygen contained in the insulator280and the like can be inhibited from diffusing to the components over the transistor200through the insulator282and the like. In this manner, the transistor200is preferably surrounded by the insulators212,214,271,275,282,283, and285, which have a function of inhibiting diffusion of oxygen and impurities such as water or hydrogen.

Here, an oxide having an amorphous structure is preferably used as the insulators212,214,271,275,282,283, and285. For example, a metal oxide such as AlOx (x is a given number greater than 0) or MgOy (y is a given number greater than 0) is preferably used. In such a metal oxide having an amorphous structure, an oxygen atom has a dangling bond and a property of capturing or fixing hydrogen by the dangling bond. When such a metal oxide having an amorphous structure is used as the component of the transistor200or provided in the vicinity of the transistor200, hydrogen contained in the transistor200or hydrogen in the vicinity of the transistor200can be captured or fixed. In particular, hydrogen contained in the channel formation region of the transistor200is preferably captured or fixed. The metal oxide having an amorphous structure is used as the component of the transistor200or provided in the vicinity of the transistor200, whereby the transistor200and the semiconductor device with favorable characteristics and high reliability can be manufactured.

Although the insulators212,214,271,275,282,283, and285preferably have an amorphous structure, they may include a region having a polycrystalline structure. Alternatively, the insulators212,214,271,275,282,283, and285may have a multilayer structure in which a layer having an amorphous structure and a layer having a polycrystalline structure are stacked. For example, a stacked-layer structure in which a layer with a polycrystalline structure is formed over a layer with an amorphous structure may be employed.

The insulators212,214,271,275,282,283, and285can be formed by a sputtering method, for example. Since a sputtering method does not need to use a molecule including hydrogen in a deposition gas, the hydrogen concentrations of the insulators212,214,271,275,282,283, and285can be reduced. Note that the deposition method is not limited to a sputtering method, and a CVD method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an ALD method, or the like may be used as appropriate.

The resistivity of the insulators212,275, and283is preferably low in some cases. For example, the insulators212,275, and283with a resistivity approximately 1×1013Ωcm can sometimes relieve charge buildup of the conductor205,242,260, or246in the treatment using plasma or the like in the manufacturing process of a semiconductor device. The resistivity of the insulators212,275, and283is preferably higher than or equal to 1×1010Ωcm and lower than or equal to 1×1015Ωcm.

The dielectric constants of the insulators216,280, and285are preferably lower than that of the insulator214. When a material with a low dielectric constant is used for an interlayer film, the parasitic capacitance generated between wirings can be reduced. For example, for the insulators216,280, and285, silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like is used as appropriate.

The conductor205is provided to overlap with the oxide230and the conductor260. Here, the conductor205is preferably provided to fill an opening formed in the insulator216. Part of the conductor205is embedded in the insulator214in some cases.

The conductor205includes a conductor205aand a conductor205b. The conductor205ais provided in contact with a bottom surface and a side wall of the opening. The conductor205bis provided so as to be embedded in a recessed portion formed in the conductor205a. Here, the top surface of the conductor205bis substantially level with the top surfaces of the conductor205aand the insulator216.

Here, the conductor205ais preferably formed using a conductive material which has a function of inhibiting diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O, NO, and NO2), and copper atoms. Alternatively, the conductor205ais preferably formed using a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

When the conductor205ais formed using a conductive material having a function of inhibiting diffusion of hydrogen, impurities such as hydrogen contained in the conductor205bcan be prevented from diffusing into the oxide230through the insulator224and the like. When a conductive material having a function of inhibiting oxygen diffusion is used for the conductor205a, a reduction in conductivity of the conductor205bdue to oxidation of the conductor205bcan be inhibited. As the conductive material having a function of inhibiting diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. Thus, the conductor205amay be a single layer or a stacked layer of the above conductive materials. For example, titanium nitride may be used for the conductor205a.

A conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor205b. For example, tungsten may be used for the conductor205b.

The conductor205functions as a second gate electrode in some cases. In that case, by changing a potential applied to the conductor205independently of a potential applied to the conductor260, the threshold voltage (Vth) of the transistor200can be controlled. In particular, by applying a negative potential to the conductor205, Vthof the transistor200can be higher, and its off-state current can be reduced. Thus, a drain current at the time when a potential applied to the conductor260is 0 V can be lower in the case where a negative potential is applied to the conductor205than in the case where the negative potential is not applied to the conductor205.

The electric resistivity of the conductor205is designed in consideration of the potential applied to the conductor205, and the thickness of the conductor205is determined in accordance with the electric resistivity. The thickness of the insulator216is substantially equal to that of the conductor205. The conductor205and the insulator216are preferably as thin as possible in the allowable range of the design of the conductor205. The insulator216with a reduced thickness contains a smaller absolute amount of impurities such as hydrogen, inhibiting the diffusion of the impurity into the oxide230.

As illustrated inFIG.1A, the size of the conductor205is preferably larger than the size of a region of the oxide230that does not overlap with the conductors242aand242b. As illustrated inFIG.1C, it is particularly preferable that the conductor205extend beyond the end portion of the oxide230in the channel width direction. That is, the conductor205and the conductor260preferably overlap with each other with the insulator positioned therebetween, in a region beyond the side surface of the oxide230in the channel width direction. With this structure, the channel formation region in the oxide230can be electrically surrounded by electric fields of the conductor260functioning as a first gate electrode and electric fields of the conductor205functioning as a second gate electrode. In this specification, such a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode is referred to as a surrounded channel (S-channel) structure.

In this specification and the like, the S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like is different from a Fin-type structure and a planar structure. With the S-channel structure, resistance to a short-channel effect can be enhanced, that is, a transistor in which a short-channel effect is less likely to occur can be provided.

When the transistor200has normally-off characteristics and the above S-channel structure, the channel formation region can be electrically surrounded. Thus, the transistor200can be regarded as having a gate all around (GAA) structure or a lateral gate all around (LGAA) structure. When the transistor200has any of an S-channel structure, a GAA structure, and an LGAA structure, the channel formation region formed at the interface between the oxide230and the gate insulator or in the vicinity thereof can correspond to the whole of bulk in the oxide230. Consequently, the density of current flowing in the transistor can be improved, so that the on-state current or the field-effect mobility of the transistor can be increased.

As illustrated inFIG.1C, the conductor205is extended to have a function of a wiring. However, without limitation to this structure, a structure in which a conductor functioning as a wiring is provided below the conductor205may be employed. In addition, the conductor205is not necessarily provided in each transistor. For example, the conductor205may be shared by a plurality of transistors.

Although the conductors205aand205bare stacked as the conductor205in the transistor200, the present invention is not limited thereto. For example, the conductor205may have a single-layer structure or a stacked-layer structure of three or more layers.

The insulators222and224function as a gate insulator.

The insulator222preferably has a function of inhibiting diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, and the like). Moreover, the insulator222preferably has a function of inhibiting diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like). For example, the insulator222preferably has a function of inhibiting diffusion of much hydrogen and/or oxygen compared to the insulator224.

As the insulator222, an insulator containing an oxide of aluminum and/or an oxide of hafnium, which are insulating materials, is preferably used. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. The insulator222formed of such a material functions as a layer that inhibits release of oxygen from the oxide230to the substrate side or diffusion of impurities such as hydrogen from the periphery of the transistor200into the oxide230. Thus, providing the insulator222can inhibit diffusion of impurities such as hydrogen into the transistor200and inhibit generation of oxygen vacancies in the oxide230. Moreover, the conductor205can be inhibited from reacting with oxygen contained in the insulator224or the metal oxide230.

Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above insulator, for example. Alternatively, the insulator may be subjected to nitriding treatment. The insulator222may have a stacked-layer structure including silicon oxide, silicon oxynitride, or silicon nitride over any of these insulators.

The insulator222may be formed to have a single-layer structure or a stacked-layer structure using an insulator containing what is called a high-k material such as aluminum oxide, hafnium oxide, hafnium aluminate, tantalum oxide, or zirconium oxide. As miniaturization and high integration of transistors progress, a problem such as leakage current may arise because of a thinner gate insulator. When a high-k material is used for the insulator functioning as a gate insulator, a gate potential at the time of operation of the transistor can be reduced while the physical thickness is maintained. Alternatively, the insulator222can be formed using a substance with high dielectric constant, in some cases, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3(BST).

Silicon oxide, silicon oxynitride, or the like can be used as appropriate for the insulator224in contact with the oxide230.

In a manufacturing process of the transistor200, the heat treatment is preferably performed with the surface of the oxide230exposed. The heat treatment may be performed at a temperature higher than or equal to 100° C. and lower than or equal to 600° C., preferably higher than or equal to 350° C. and lower than or equal to 550° C., for example. The heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxide230to reduce oxygen vacancies. The heat treatment may be performed under a reduced pressure. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in a nitrogen gas atmosphere or an inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for released oxygen. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more, and then another heat treatment is successively performed in a nitrogen gas atmosphere or an inert gas atmosphere.

Note that the oxygen adding treatment performed on the oxide230can promote a reaction in which oxygen vacancies in the oxide230are filled with supplied oxygen, i.e., a reaction of VO+O→null. Furthermore, the supplied oxygen reacts with hydrogen remaining in the oxide230, so that the hydrogen can be removed as H2O (dehydration). This can inhibit recombination of hydrogen remaining in the oxide230with oxygen vacancies and formation of VOH.

Note that the insulators222and224may each have a stacked-layer structure of two or more layers. In those cases, without limitation to a stacked-layer structure formed of the same material, a stacked-layer structure formed of different materials may be employed. The insulator224may be formed into an island shape overlapping with the oxide230. In that case, the insulator275is in contact with the side surface of the insulator224and the top surface of the insulator222.

The conductor242aand the conductor242bare provided in contact with the top surface of the oxide230. The conductor242aand the conductor242bfunction as the source electrode and the drain electrode of the transistor200.

For the conductor242, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum is preferably used, for example. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. As another example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are not easily oxidized or a material that maintains the conductivity even when absorbing oxygen.

Note that hydrogen contained in the oxide230or the like diffuses into the conductor242aor242bin some cases. In particular, when a nitride containing tantalum is used for the conductors242aand242b, hydrogen contained in the oxide230or the like is likely to diffuse into the conductor242aor242b, and the diffused hydrogen is bonded to nitrogen contained in the conductor242aor242bin some cases. That is, hydrogen contained in the oxide230or the like is sometimes absorbed by the conductor242aor242b.

No curved surface is preferably formed between the side surface and the top surface of the conductor242. Without the curved surface, the conductor242can have a large cross-sectional area in the channel width direction as illustrated inFIG.1D. Accordingly, the conductivity of the conductor242is increased, so that the on-state current of the transistor200can be increased.

The insulator271ais provided in contact with the top surface of the conductor242a, and the insulator271bis provided in contact with the top surface of the conductor242b. The insulator271preferably functions as at least an insulating film functioning as a barrier against oxygen. Thus, the insulator271preferably has a function of inhibiting oxygen diffusion. For example, the insulator271preferably has a function of inhibiting oxygen diffusion more than the insulator280. For example, a nitride containing silicon such as silicon nitride may be used for the insulator271. The insulator271preferably has a function of capturing impurities such as hydrogen. In that case, for the insulator271, a metal oxide with an amorphous structure, for example, an insulator such as aluminum oxide or magnesium oxide may be used. It is particularly preferable to use aluminum oxide having an amorphous structure or amorphous aluminum oxide as the insulator271because hydrogen can be sufficiently trapped or fixed in some cases. Accordingly, the transistor200and the semiconductor device with favorable characteristics and high reliability can be fabricated.

The insulator275is provided to cover the insulator224, the oxide230, the conductor242, and the insulator271. The insulator275preferably has a function of capturing and fixing hydrogen. In that case, the insulator275preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure (e.g., aluminum oxide or magnesium oxide). Alternatively, for example, a stacked-layer film of aluminum oxide and silicon nitride over the aluminum oxide may be used as the insulator275.

When the above insulators271and275are provided, the conductor242can be surrounded by the insulators having a barrier property against oxygen. That is, oxygen contained in the insulators224and280can be prevented from diffusing into the conductor242. As a result, the conductor242can be inhibited from being directly oxidized by oxygen contained in the insulators224and280, so that an increase in resistivity and a reduction in on-state current can be inhibited.

The insulator252functions as part of a gate insulator. As the insulator252, an insulating film functioning as a barrier against oxygen is preferably used. Any of the above-described insulators that can be used for the insulator282may be used as the insulator252. As the insulator252, an insulator containing an oxide of one or both of aluminum and hafnium is preferably used. For the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing a hafnium and silicon (hafnium silicate), or the like can be used. In this embodiment, aluminum oxide is used as the insulator252. In this case, the insulator252serves as an insulator containing at least oxygen and aluminum.

As illustrated inFIG.1C, the insulator252is provided in contact with the top and side surfaces of the oxide230, the side surface of the insulator224, and the top surface of the insulator222. In other words, a region where the oxide230and the insulator224overlap with the conductor260is covered with the insulator252in a cross section in the channel width direction. With this structure, a release of oxygen in the oxide230by the heat treatment or the like can be blocked by the insulator252having a barrier property against oxygen. Thus, formation of oxygen vacancies in the oxide230can be inhibited. Thus, the amount of oxygen vacancies and VOH formed in the region230bccan be reduced. Accordingly, electrical characteristics and reliability of the transistor200can be improved.

By contrast, even when the excess amount of oxygen is included in the insulator280, the insulator250, or the like, supply of the oxygen to the oxide230can be inhibited. Thus, the regions230baand230bbare prevented from being excessively oxidized by supply of the oxygen through the region230bc; a reduction in on-state current or field-effect mobility of the transistor200can be inhibited.

As illustrated inFIG.1B, the insulator252is provided in contact with the side surfaces of the conductor242and the insulators271,275, and280. This inhibits formation of an oxide film on the side surface of the conductor242by oxidization of the side surface. Accordingly, a reduction in on-state current or field-effect mobility of the transistor200can be inhibited.

Furthermore, the insulator252needs to be provided in an opening formed in the insulator280, and the like, together with the insulators254and250and the conductor260. The thickness of the insulator252is preferably thin for miniaturization of the transistor200. The thickness of the insulator252is greater than or equal to 0.1 nm and less than or equal to 5.0 nm, preferably greater than or equal to 0.5 nm and less than or equal to 3.0 nm, further preferably greater than or equal to 1.0 nm and less than or equal to 3.0 nm. In that case, at least part of the insulator252preferably includes a region having the above-described thickness. The thickness of the insulator252is preferably smaller than that of the insulator250. In that case, at least part of the insulator252preferably includes a region having a thickness smaller than that of the insulator250.

To form the insulator252having a small thickness as the above, an ALD method is preferably used for deposition. As the ALD method, a thermal ALD method, in which a precursor and a reactant react with each other only by a thermal energy, a plasma-enhanced ALD (PEALD) method, in which a reactant excited by plasma is used, and the like can be used. The use of plasma is sometimes preferable because deposition at a lower temperature is possible in a PEALD method.

In the ALD method, one atomic layer can be deposited at a time by using self-controllability of atoms. Hence, the ALD method has various advantages such as deposition of an extremely thin film, deposition on a component with a high aspect ratio, deposition of a film with a small number of defects such as pinholes, deposition with excellent coverage, and low-temperature deposition. Therefore, the insulator252can be formed on the side surface of the opening formed in the insulator280and the like to have a small thickness as the above and to have favorable coverage.

Note that a precursor used in the ALD method sometimes contains impurities such as carbon. Thus, a film formed by the ALD method may contain impurities such as carbon in a larger amount than a film formed by another deposition method. Note that impurities can be quantified by SIMS or XPS.

Note that in the case where the insulator252includes a region having the above-described thickness, the defect level relating to the negative-bias stress temperature photodegradation is not limited to the defect level at the interface between the oxide230and the insulator252but presumably includes the defect level at the interface between the insulator252and the insulator250or the defect level in the insulator250.

The insulator250functions as part of a gate insulator. The insulator250is preferably located in contact with at least part of the insulator252. The insulator250can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like. In particular, silicon oxide and silicon oxynitride, which have thermal stability, are preferable. In this case, the insulator250includes at least oxygen and silicon.

As in the insulator224, the concentration of impurities such as water or hydrogen in the insulator250is preferably reduced.

The thickness of the insulator250is preferably greater than or equal to 0.5 nm and less than or equal to 20 nm, further preferably greater than or equal to 1.0 nm and less than or equal to 15.0 nm. In that case, at least part of the insulator250preferably has the thickness described above.

AlthoughFIG.1Bor the like shows a single-layer structure of the insulator250, the present invention is not limited to this structure, and a stacked-layer structure of two or more layers may be employed. For example, as illustrated inFIG.6B, the insulator250may have a stacked-layer structure including two layers of an insulator250aand an insulator250bover the insulator250a.

When the insulator250has a stacked-layer structure including two layers as illustrated inFIG.6B, the insulator250athat is a lower layer is preferably formed using an insulator through which oxygen is easily transmitted, and the insulator250bthat is an upper layer is preferably formed using an insulator having a function of inhibiting diffusion of oxygen. Owing to this structure, diffusion of oxygen contained in the insulator250ainto the conductor260can be inhibited. That is, a reduction in the amount of oxygen supplied to the oxide230can be inhibited. Moreover, oxidation of the conductor260due to oxygen contained in the insulator250acan be inhibited. For example, the insulator250ais preferably formed using the above-described material that can be used for the insulator250, and the insulator250bis preferably formed using an insulator containing one or both of aluminum oxide and hafnium oxide. For the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and silicon (hafnium silicate), or the like can be used. In this embodiment, hafnium oxide is used as the insulator250b. In this case, the insulator250bserves as an insulator containing at least oxygen and hafnium. The thickness of the insulator250bis greater than or equal to 0.5 nm and less than or equal to 5.0 nm, preferably greater than or equal to 1.0 nm and less than or equal to 5.0 nm, further preferably greater than or equal to 1.0 nm and less than or equal to 3.0 nm. In that case, at least part of the insulator250bpreferably includes a region having the above-described thickness.

In the case where silicon oxide, silicon oxynitride, or the like is used for the insulator250a, the insulator250bmay be formed using an insulating material that is a high-k material having a high relative dielectric constant. The gate insulator having a stacked-layer structure of the insulator250aand the insulator250bcan be thermally stable and can have a high dielectric constant. Accordingly, a gate potential applied during operation of the transistor can be lowered while the physical thickness of the gate insulator is maintained. In addition, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. Therefore, the breakdown voltage of the insulator250can be increased.

The insulator254functions as part of a gate insulator. As the insulator254, an insulating film having a barrier property against hydrogen is preferably used. This can prevent diffusion of impurities such as hydrogen contained in the conductor260into the insulator250and the oxide230. Any of the above-described insulators that can be used as the insulator283is used as the insulator254. For example, silicon nitride deposited by a PEALD method may be used as the insulator254. In this case, the insulator254serves as an insulator containing at least nitrogen and silicon.

Furthermore, the insulator254may have a barrier property against oxygen. In this case, oxygen contained in the insulator250can be inhibited from diffusing into the conductor260.

Furthermore, the insulator254needs to be provided in an opening formed in the insulators252and250, the conductor260, the insulator280, and the like. The thickness of the insulator254is preferably thin for miniaturization of the transistor200. The thickness of the insulator254is greater than or equal to 0.1 nm and less than or equal to 5.0 nm, preferably greater than or equal to 0.5 nm and less than or equal to 3.0 nm, further preferably greater than or equal to 1.0 nm and less than or equal to 3.0 nm. In that case, at least part of the insulator254preferably includes a region having the above-described thickness. The thickness of the insulator254is preferably smaller than that of the insulator250. In that case, at least part of the insulator254preferably includes a region having the above-described thickness.

The conductor260functions as a first gate electrode of the transistor200. The conductor260preferably includes a conductor260aand a conductor260bover the conductor260a. For example, the conductor260ais preferably positioned so as to cover the bottom and side surfaces of the conductor260b. Moreover, as illustrated inFIG.1BandFIG.1C, the top surface of the conductor260is substantially level with the uppermost portions of the insulators252,250, and254. AlthoughFIGS.1B and1Cshow that the conductor260has a two-layer structure of the conductor260aand the conductor260b, the conductor260may have a single-layer structure or a stacked-layer structure of three or more layers.

The conductor260ais preferably formed using a conductive material having a function of inhibiting diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Alternatively, the conductor260ais preferably formed using a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

When the conductor260ahas a function of inhibiting diffusion of oxygen, the conductivity of the conductor260bcan be prevented from being lowered because of oxidization of the conductor260bdue to oxygen in the insulator250. As the conductive material having a function of inhibiting diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

The conductor260also functions as a wiring and thus is preferably formed using a conductor having high conductivity. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used for the conductor260b. The conductor260bmay have a stacked-layer structure, for example, a stacked-layer structure of titanium or titanium nitride and the above conductive material.

In the transistor200, the conductor260is formed in a self-aligned manner so as to fill an opening formed in the insulator280and the like. In this manner, the conductor260can surely be provided in a region between the conductor242aand the conductor242bwithout alignment.

In the channel width direction of the transistor200as illustrated inFIG.1C, with the level of the bottom surface of the insulator222as a reference, the level of a region of the bottom surface of the conductor260that does not overlap with the oxide230is preferably substantially same level or lower than the level of the bottom surface of the oxide230. When the conductor260functioning as the gate electrode covers the side and top surfaces of the channel formation region of the oxide230with the insulator250and the like therebetween, the electric field of the conductor260is likely to affect the entire channel formation region of the oxide230. Hence, the transistor200can have a higher on-state current and higher frequency characteristics. With the level of the bottom surface of the insulator222as a reference, a distance between the bottom surface of the conductor260and the bottom surfaces of the oxide230in a region where the conductor260does not overlap with the oxide230is greater than or equal to 0 nm and less than or equal to 100 nm, preferably greater than or equal to 3 nm and less than or equal to 50 nm, and further preferably greater than or equal to 5 nm and less than or equal 30 to 20 nm.

The insulator280is provided over the insulator275, and the opening is formed in the region where the insulators252,250, and254and the conductor260are provided. In addition, the top surface of the insulator280may be planarized.

The insulator280functioning as the interlayer film preferably has a low dielectric constant. When a material with a low dielectric constant is used for an interlayer film, the parasitic capacitance generated between wirings can be reduced. The insulator280is preferably formed using a material similar to that used for the insulator216, for example. Silicon oxide and silicon oxynitride are particularly preferable because of their thermal stability. Silicon oxide, silicon oxynitride, and porous silicon oxide are particularly preferable because a region containing oxygen that is released by heating can be easily formed in these materials.

The concentration of impurities such as water or hydrogen in the insulator280is preferably reduced. For example, an oxide containing silicon such as silicon oxide or silicon oxynitride can be used for the insulator280as appropriate.

The insulator282preferably functions as a barrier insulating film that inhibits impurities such as water or hydrogen from diffusing into the insulator280from the above and also has a function of capturing impurities such as hydrogen. The insulator282also preferably functions as a barrier insulating film that inhibits oxygen transmission. As the insulator282, for example, an insulator such as a metal oxide having an amorphous structure or aluminum oxide can be used. In this case, the insulator282serves as an insulator containing at least oxygen and aluminum. The insulator282, which has a function of capturing impurities such as hydrogen, is provided in contact with the insulator280in a region sandwiched between the insulator212and the insulator283, whereby impurities such as hydrogen contained in the insulator280and the like can be captured and the amount of hydrogen in the region can be kept constant. It is particularly preferable to use aluminum oxide having an amorphous structure as the insulator282because hydrogen can be captured or fixed more effectively in some cases. Accordingly, the transistor200and the semiconductor device with favorable characteristics and high reliability can be fabricated.

The insulator283functions as a barrier insulating film that inhibits impurities such as water or hydrogen from diffusing into the insulator280from the above. The insulator283is provided over the insulator282. The insulator283is preferably formed using a nitride containing silicon such as silicon nitride or silicon nitride oxide. For example, silicon nitride deposited by a sputtering method may be used for the insulator283. When the insulator283is formed by a sputtering method, a high-density silicon nitride film can be obtained. To obtain the insulator283, silicon nitride deposited by a PEALD method or a CVD method may be stacked over silicon nitride deposited by a sputtering method.

The conductor240is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. The conductors240aand240bmay have a stacked-layer structure.

In the case where the conductor240has a stacked-layer structure, a conductive material having a function of inhibiting transmission of impurities such as water or hydrogen is preferably used as a first conductor located in the vicinity of the insulators285,283,282,280,275, and271. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. The conductive material having a function of inhibiting transmission of impurities such as water or hydrogen can be used as a single layer or stacked layers. Furthermore, impurities such as water and hydrogen contained in the components above the insulator283can be prevented from entering the oxide230through the conductor240.

The insulator241can be formed using the insulator that can be used as the insulator275or the like. For the insulator241, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide can be used. Since the insulator241a(241b) is provided in contact with the insulators283,282, and271, impurities such as water or hydrogen contained in the insulator280and the like can be prevented from entering the oxide230through the conductor240a(240b). Silicon nitride is particularly preferable because of its high blocking property against hydrogen. Moreover, oxygen contained in the insulator280can be inhibited from being absorbed into the conductor240.

When the insulator241aand the insulator241beach have a stacked-layer structure illustrated inFIG.1B, a first insulator in contact with an inner wall of the opening formed in the insulator280and the like and a second insulator on the inner side of the first insulator are preferably formed using a combination of an insulating film functioning as a barrier against oxygen and an insulating film functioning as a barrier against hydrogen.

For example, aluminum oxide deposited by an ALD method and silicon nitride deposited by a PEALD method may be used respectively as the first insulator and the second insulator. With this structure, oxidation of the conductor240can be inhibited, and hydrogen can be prevented from entering the conductor240.

The conductors246aand246bfunctioning as a wiring may be provided in contact with the top surfaces of the conductors240aand240b. The conductor246is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. The conductors246aand246bmay have a stacked-layer structure, for example, a stacked-layer structure of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed to be embedded in an opening in an insulator.

With the above structure, a semiconductor device with a small variation in transistor characteristics can be provided. A highly reliable semiconductor device can be provided. In addition, a semiconductor device having favorable electrical characteristics can be provided.

Materials that can be used for the semiconductor device are described below.

As a substrate where the transistor200is formed, an insulator substrate, a semiconductor substrate, or a conductor substrate can be used, for example. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate of silicon or germanium and a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Another example includes a semiconductor substrate in which an insulator region is provided in the above semiconductor substrate, such as a silicon on insulator (SOI) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Other examples include a substrate containing a nitride of a metal, a substrate containing an oxide of a metal, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator. Alternatively, these substrates provided with elements may be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light-emitting element, and a memory element.

Examples of an insulator include an insulating oxide, an insulating nitride, an insulating oxynitride, an insulating nitride oxide, an insulating metal oxide, an insulating metal oxynitride, and an insulating metal nitride oxide.

With miniaturization and high integration of a transistor, for example, a problem such as generation of leakage current may arise because of a thin gate insulator. When a high-k material is used for the insulator functioning as a gate insulator, the voltage at the time of operation of the transistor can be reduced while the physical thickness is maintained. By contrast, when a material with a low dielectric constant is used for the insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Thus, a material is preferably selected depending on the function of an insulator.

Examples of the insulator having a high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

Examples of the insulator having a low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, and a resin.

A transistor including a metal oxide can have stable electrical characteristics when surrounded by an insulator having a function of inhibiting transmission of oxygen and impurities such as hydrogen. The insulator having a function of inhibiting transmission of oxygen and impurities such as hydrogen can have, for example, a single-layer structure or a stacked-layer structure of an insulator including boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, as the insulator having a function of inhibiting transmission of oxygen and impurities such as hydrogen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide or a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride can be used.

The insulator functioning as a gate insulator preferably includes a region containing oxygen that is released by heating. For example, silicon oxide or silicon oxynitride that includes a region containing oxygen that is released by heating is provided in contact with the oxide230to compensate for the oxygen vacancies in the oxide230.

Conductive layers formed using any of the above materials may be stacked. For example, a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen may be employed. Alternatively, a stacked-layer structure combining a material containing the above metal element and a conductive material containing nitrogen may be employed. Further alternatively, a stacked-layer structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.

When an oxide is used for the channel formation region of the transistor, the conductor functioning as the gate electrode preferably has a stacked-layer structure combining a material containing any of the above metal elements and a conductive material containing oxygen. In that case, the conductive material containing oxygen is preferably provided on the channel formation region side. When the conductive material containing oxygen is provided on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

It is particularly preferable to use, for the conductor functioning as the gate electrode, a conductive material containing oxygen and a metal element contained in a metal oxide in which the channel is formed. A conductive material containing any of the above metal elements and nitrogen may also be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Indium gallium zinc oxide containing nitrogen may be used. With use of such a material, hydrogen contained in the metal oxide where the channel is formed can be captured in some cases. Hydrogen entered from a surrounding insulator or the like can also be captured in some cases.

As the oxide230, a metal oxide functioning as a semiconductor (oxide semiconductor) is preferably used. A metal oxide that can be used for the oxide230according to the present invention is described below.

The metal oxide functioning as a semiconductor preferably has a bandgap of 2 eV or more, further preferably 2.5 eV or more. The use of such a metal oxide having a wide bandgap can reduce the off-state current of the transistor.

Note that in this specification and the like, a metal oxide containing nitrogen is also referred to as a metal oxide in some cases. In addition, a metal oxide containing nitrogen may be referred to as a metal oxynitride.

<Classification of Crystal Structure>

Amorphous (including a completely amorphous structure), c-axis-aligned crystalline (CAAC), nanocrystalline (nc), cloud-aligned composite (CAC), single-crystal, polycrystalline structures, and the like can be given as examples of a crystal structure of an oxide semiconductor.

A crystal structure of a film or a substrate can be analyzed with an X-ray diffraction (XRD) spectrum. For example, evaluation is possible using an XRD spectrum which is obtained by grazing-incidence XRD (GIXD) measurement. Note that a GIXD method is also referred to as a thin film method or a Seemann-Bohlin method. Hereinafter, an XRD spectrum obtained from GIXD measurement is simply referred to as an XRD spectrum in some cases.

For example, the peak of the XRD spectrum of the quartz glass substrate has a bilaterally symmetrical shape. On the other hand, the peak of the XRD spectrum of the In—Ga—Zn oxide film having a crystal structure has a bilaterally asymmetrical shape. The bilaterally asymmetrical peak shows the existence of crystal in the film or the substrate. In other words, the crystal structure of the film or the substrate cannot be regarded as “amorphous” unless it has a bilaterally symmetrical peak in the XRD spectrum.

A crystal structure of a film or a substrate can also be evaluated with a diffraction pattern obtained by a nanobeam electron diffraction (NBED) method (such a pattern is also referred to as a nanobeam electron diffraction pattern). For example, a halo pattern is observed in the diffraction pattern of the quartz glass substrate, which indicates that the quartz glass substrate is in an amorphous state. Furthermore, not a halo pattern but a spot-like pattern is observed in the diffraction pattern of the In—Ga—Zn oxide film formed at room temperature. Thus, it is presumed that the In—Ga—Zn oxide film formed at room temperature is in an intermediate state, which is neither a crystal nor polycrystal state nor an amorphous state, and it cannot be concluded that the In—Ga—Zn oxide film is in an amorphous state.

Next, the CAAC-OS, nc-OS, and a-like OS will be described in detail.

Note that each of the plurality of crystal regions is formed of one or more fine crystals (crystals each of which has a maximum diameter of less than 10 nm). In the case where the crystal region is formed of one fine crystal, the maximum diameter of the crystal region is less than 10 nm. In the case where the crystal region is formed of a large number of fine crystals, the maximum diameter of the crystal region may be approximately several tens of nanometers.

In the case of an In—Ga—Zn oxide, the CAAC-OS tends to have a layered crystal structure (also referred to as a stacked-layer structure) in which a layer containing indium (In) and oxygen (hereinafter, an In layer) and a layer containing gallium (Ga), zinc (Zn), and oxygen (hereinafter, an (Ga,Zn) layer) are stacked. Indium and gallium can be replaced with each other. Therefore, indium may be contained in the (Ga,Zn) layer. In addition, the gallium may be contained in the In layer. Note that zinc may be contained in the In layer. Such a layered structure is observed as a lattice image in a high-resolution transmission electron microscope (TEM) image, for example.

When the CAAC-OS film is subjected to structural analysis by out-of-plane XRD measurement with an XRD apparatus using θ/2θ scanning, for example, a peak indicating c-axis alignment is detected at or around 2θ=31°. Note that the position of the peak indicating c-axis alignment (the value of 2θ) may change depending on the kind, composition, or the like of the metal element contained in the CAAC-OS.

The CAAC-OS is an oxide semiconductor with high crystallinity in which no clear grain boundary is observed. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS can be referred to as an oxide semiconductor having small amounts of impurities and defects (e.g., oxygen vacancies). Therefore, an oxide semiconductor including the CAAC-OS is physically stable. Accordingly, the oxide semiconductor including the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable with respect to high temperatures in the manufacturing process (i.e., thermal budget). Accordingly, the use of the CAAC-OS for the OS transistor can extend a degree of freedom of the manufacturing process.

The a-like OS is an oxide semiconductor having a structure between those of the nc-OS and the amorphous oxide semiconductor. The a-like OS has a void or a low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS. Moreover, the a-like OS has higher hydrogen concentration than the nc-OS and the CAAC-OS.

Next, the CAC-OS is described in detail. Note that the CAC-OS relates to the material composition.

The CAC-OS refers to one composition of a material in which elements constituting a metal oxide are unevenly distributed with a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size, for example. Note that in the following description of a metal oxide, a state in which one or more types of metal elements are unevenly distributed and regions including the metal element(s) are mixed is referred to as a mosaic pattern or a patch-like pattern. The regions each have a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size.

Here, the atomic ratios of In, Ga, and Zn to the metal elements contained in the CAC-OS in an In—Ga—Zn oxide are denoted by [In], [Ga], and [Zn], respectively. For example, the first region in the CAC-OS in the In—Ga—Zn oxide has [In] higher than that in the composition of the CAC-OS film. Moreover, the second region of the CAC-OS in the In—Ga—Zn oxide has [Ga] higher than that in the composition of the CAC-OS film. Alternatively, for example, the first region has higher [In] and lower [Ga] than the second region. Moreover, the second region has higher [Ga] and lower [In] than the first region.

Specifically, the first region includes indium oxide, indium zinc oxide, or the like as its main component. The second region includes gallium oxide, gallium zinc oxide, or the like as its main component. That is, the first region can be referred to as a region containing In as its main component. The second region can be referred to as a region containing Ga as its main component.

In a material composition of a CAC-OS in an In—Ga—Zn oxide that contains In, Ga, Zn, and O, regions containing Ga as a main component are observed in part of the CAC-OS and regions containing In as a main component are observed in part thereof. These regions are randomly dispersed to form a mosaic pattern. Thus, it is suggested that the CAC-OS has a structure in which metal elements are unevenly distributed.

The CAC-OS can be formed by a sputtering method under a condition where a substrate is intentionally not heated, for example. In the case of forming the CAC-OS by a sputtering method, one or more selected from an inert gas (typically, argon), an oxygen gas, and a nitrogen gas may be used as a deposition gas. The ratio of the flow rate of an oxygen gas to the total flow rate of the deposition gas during deposition is preferably as low as possible. For example, the flow-rate proportion of an oxygen gas in the total deposition gas is preferably higher than or equal to 0% and lower than 30%, further preferably higher than or equal to 0% and lower than or equal to 10%.

For example, energy dispersive X-ray spectroscopy (EDX) is used to obtain EDX mapping, and according to the EDX mapping, the CAC-OS in the In—Ga—Zn oxide has a composition in which the regions containing In as a main component (the first regions) and the regions containing Ga as a main component (the second regions) are unevenly distributed and mixed.

Here, the first region has a higher conductivity than the second region. In other words, when carriers flow through the first region, the conductivity of a metal oxide is exhibited. Accordingly, when the first regions are distributed in a metal oxide as a cloud, high field-effect mobility (s) can be achieved.

The second region has a higher insulating property than the first region. In other words, when the second regions are distributed in a metal oxide, leakage current can be inhibited.

Thus, in the case where a CAC-OS is used for a transistor, by the complementary function of the conducting function due to the first region and the insulating function due to the second region, the CAC-OS can have a switching function (on/off function). That is, the CAC-OS has a conducting function in part of the material and has an insulating function in another part of the material; as a whole, the CAC-OS has a function of a semiconductor. Separation of the conducting function and the insulating function can maximize each function. Thus, when the CAC-OS is used for a transistor, high on-state current (Ion), high field-effect mobility (p), and excellent switching operation can be achieved.

A transistor including a CAC-OS is highly reliable. Thus, the CAC-OS is suitably used in a variety of semiconductor devices typified by a display device.

An oxide semiconductor can have any of various structures that show various different properties. Two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, the CAC-OS, an nc-OS, and the CAAC-OS may be included in an oxide semiconductor of one embodiment of the present invention.

Note that a plurality of crystal structures are included in an oxide semiconductor in some cases. For example, in the case where the oxide semiconductor contains a larger amount of gallium than that of indium, a layered crystal structure and a spinel crystal structure are included in the oxide semiconductor in some cases. The oxide semiconductor in this case includes a CAAC-OS, an nc-OS, a CAAC-OS including a crystal region with a spinel crystal structure, an nc-OS including a crystal region with a layered crystal structure and a crystal region with a spinel crystal structure, and the like.

Next, a transistor including the above oxide semiconductor is described.

When the oxide semiconductor is used for a transistor, the transistor can have high field-effect mobility. In addition, the transistor can have high reliability.

A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and accordingly has a low density of trap states in some cases.

Charges trapped by the trap states in an oxide semiconductor take a long time to be released and may behave like fixed charges. A transistor whose channel formation region is formed in an oxide semiconductor having a high density of trap states has unstable electrical characteristics in some cases.

In order to obtain stable electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, the impurity concentration in a film that is adjacent to the oxide semiconductor is preferably reduced. Examples of impurities include hydrogen, nitrogen, alkali metal, alkaline earth metal, iron, nickel, and silicon. Note that an impurity in an oxide semiconductor refers to, for example, elements other than the main components of the oxide semiconductor. For example, an element with a concentration lower than 0.1 atomic % is regarded as an impurity.

The influence of impurities in the oxide semiconductor is described.

When silicon or carbon, which is a Group 14 element, is contained in an oxide semiconductor, defect states are formed in the oxide semiconductor. Thus, the concentration of silicon or carbon in the oxide semiconductor, which is measured by SIMS, is lower than or equal to 2×1018atoms/cm3, preferably lower than or equal to 2×1017atoms/cm3.

When the oxide semiconductor contains alkali metal or alkaline earth metal, defect states are formed and carriers are generated in some cases. Accordingly, a transistor including an oxide semiconductor that contains alkali metal or alkaline earth metal tends to have normally-on characteristics. Thus, the concentration of alkali metal or alkaline earth metal in the oxide semiconductor, which is measured by SIMS, is lower than or equal to 1×1018atoms/cm3, preferably lower than or equal to 2×1016atoms/cm3.

An oxide semiconductor containing nitrogen easily becomes n-type by generation of electrons serving as carriers and an increase in carrier concentration. A transistor including an oxide semiconductor that contains nitrogen tends to have normally-on characteristics. When nitrogen is contained in the oxide semiconductor, a trap state is sometimes formed. This might make the electrical characteristics of the transistor unstable. Thus, the concentration of nitrogen in the oxide semiconductor, which is measured by SIMS, is lower than 5×1019atoms/cm3, preferably lower than or equal to 5×1018atoms/cm3, further preferably lower than or equal to 1×1018atoms/cm3, still further preferably lower than or equal to 5×1017atoms/cm3.

When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region in a transistor, the transistor can have stable electrical characteristics.

<Method for Manufacturing Semiconductor Device>

Next, a method for manufacturing a semiconductor device of one embodiment of the present invention, which is illustrated inFIGS.1A to1D, will be described with reference toFIGS.7A to15D.

Note thatFIG.7A,FIG.8A,FIG.9A,FIG.10A,FIG.11A,FIG.12A,FIG.13A,FIG.14A,FIG.15Aare each a top view.FIG.7B,FIG.8B,FIG.9B,FIG.10B,FIG.11B,FIG.12B,FIG.13B,FIG.14B, andFIG.15Bare cross-sectional views taken along the dashed-dotted lines A1-A2inFIG.7A,FIG.8A,FIG.9A,FIG.10A,FIG.11A,FIG.12A,FIG.13A,FIG.14A, andFIG.15A, which correspond to cross-sectional views in the channel length direction of the transistor200.FIG.7C,FIG.8C,FIG.9C,FIG.10C,FIG.11C,FIG.12C,FIG.13C,FIG.14C, andFIG.15Care cross-sectional views taken along dashed-dotted lines A3-A4inFIG.7A,FIG.8A,FIG.9A,FIG.10A,FIG.11A,FIG.12A,FIG.13A,FIG.14A, andFIG.15, which correspond to cross-sectional views in the channel width direction of the transistor200.FIG.7D,FIG.8D,FIG.9D,FIG.10D,FIG.11D,FIG.12D,FIG.13D,FIG.14D, andFIG.15Dare cross-sectional views taken along dashed-dotted lines A5-A6inFIG.7A,FIG.8A,FIG.9A,FIG.10A,FIG.11A,FIG.12A,FIG.13A,FIG.14A, andFIG.15, which correspond to cross-sectional views in the channel width direction of the transistor200. For simplification, some components are not illustrated in the top views inFIG.7A,FIG.8A,FIG.9A,FIG.10A,FIG.11A,FIG.12A,FIG.13A,FIG.14A, andFIG.15A.

In the following steps, an insulating material for forming an insulator, a conductive material for forming a conductor, and a semiconductor material for forming a semiconductor can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Examples of the sputtering method include an RF sputtering method in which a high-frequency power source is used for a sputtering power supply, a DC sputtering method in which a DC power source is used, and a pulsed DC sputtering method in which a voltage is applied while being changed in a pulsed manner. The RF sputtering method is mainly used in the case where an insulating film is formed, and the DC sputtering method is mainly used in the case where a metal conductive film is formed. The pulsed DC sputtering method is mainly used in the case where a compound such as an oxide, a nitride, or a carbide is deposited by a reactive sputtering method.

Note that CVD methods can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Moreover, CVD methods can be classified into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method according to a source gas.

A high-quality film can be obtained at a relatively low temperature through a PECVD method. A thermal CVD method does not use plasma and thus causes less plasma damage to an object. For example, a wiring, an electrode, an element (e.g., a transistor or a capacitor), or the like included in a semiconductor device may be charged up by receiving charge from plasma. In that case, accumulated charge may break the wiring, electrode, element, or the like included in the semiconductor device. A thermal CVD method, which does not use plasma, does not cause such plasma damage, and thus can increase the yield of the semiconductor device. A thermal CVD method yields a film with few defects because of no plasma damage during film formation.

As the ALD method, a thermal ALD method, in which a precursor and a reactant react with each other only by a thermal energy, a plasma-enhanced ALD (PEALD) method, in which a reactant excited by plasma is used, and the like can be used.

Methods of CVD and ALD differ from a sputtering method by which particles ejected from a target or the like are deposited. Thus, a CVD method and an ALD method can provide good step coverage, almost regardless of the shape of an object. In particular, an ALD method allows excellent step coverage and excellent thickness uniformity and can be suitably used to cover a surface of an opening portion with a high aspect ratio, for example. Note that an ALD method has a relatively low deposition rate; hence, in some cases, an ALD method is preferably combined with another film formation method with a high deposition rate, such as a CVD method.

By a CVD method, a film with a certain composition can be formed by adjusting the flow rate ratio of the source gases. For example, a CVD method enables a film with a gradually-changed composition to be formed by changing the flow rate ratio of the source gases during film formation. In the case where a film is formed while the flow rate ratio of the source gases is changed, as compared to the case where a film is formed using a plurality of deposition chambers, the time taken for the deposition can be shortened because the time taken for transfer and pressure adjustment is omitted. Hence, the productivity of the semiconductor device can be improved in some cases.

An ALD method, with which a plurality of different kinds of precursors are introduced at a time, enables formation of a film with desired composition. In the case where a plurality of different kinds of precursors are introduced, the cycle number of precursor deposition is controlled, whereby a film with desired composition can be formed.

First, a substrate (not illustrated) is prepared, and the insulator212is formed over the substrate (seeFIGS.7A to7D). The insulator212is preferably formed by a sputtering method. Since a molecule containing hydrogen is not used as a deposition gas in the sputtering method, the concentration of hydrogen in the insulator212can be reduced. Note that the insulator212can be formed by a CVD method, an MBE method, a PLD method, an ALD method, or the like as well as the sputtering method.

In this embodiment, as the insulator212, silicon nitride is deposited by a pulsed DC sputtering method using a silicon target in an atmosphere containing a nitrogen gas. The use of the pulsed DC sputtering can inhibit generation of particles due to arcing on the target surface, achieving more uniform film thickness. In addition, by using the pulsed voltage, rising and falling in discharge can be made steep as compared with the case where a high-frequency voltage is used. As a result, power can be supplied to an electrode more efficiently to improve the sputtering rate and film quality.

The use of an insulator through which impurities such as water or hydrogen are less likely to pass, such as silicon nitride, can inhibit diffusion of impurities such as water or hydrogen contained in a layer under the insulator212. Even when a metal that is easily diffused, such as copper, is used for a conductor (not illustrated) under the insulator212, the metal can be inhibited from diffusing into a layer over the insulator212through the insulator212when an insulator through which copper is less likely to pass, such as silicon nitride, is used as the insulator212.

Next, the insulator214is formed over the insulator212(seeFIG.7AtoFIG.7D). The insulator214is preferably formed by a sputtering method. Since a molecule containing hydrogen is not used as a deposition gas in the sputtering method, the concentration of hydrogen in the insulator214can be reduced. Note that the insulator214can be formed by a CVD method, an MBE method, a PLD method, an ALD method, or the like as well as the sputtering method.

In this embodiment, as the insulator214, aluminum oxide is deposited by a pulsed DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas. The use of the pulsed DC sputtering can achieve more uniform film thickness and improve the sputtering rate and film quality. A radio frequency (RF) power may be applied to the substrate. The amount of oxygen implanted into layers under the insulator214can be controlled depending on the amount of the RF power applied to the substrate. The RF power is higher than or equal to 0 W/cm2and lower than or equal to 1.86 W/cm2. In other words, an appropriate amount of oxygen for the transistor characteristics can be implanted by changing the amount of RF power used for the formation of the insulator214. Accordingly, an appropriate amount of oxygen for improving the reliability of the transistor can be implanted. The RF frequency is preferably 10 MHz or higher. The typical frequency is 13.56 MHz. The higher the RF frequency is, the less damage to the substrate can be.

A metal oxide having an amorphous structure and an excellent function of capturing or fixing hydrogen, such as aluminum oxide, is preferably used for the insulator214. Thus, the insulator214captures or fixes hydrogen contained in the insulator216and the like and prevents the hydrogen from diffusing to the oxide230. It is particularly preferable to use aluminum oxide having an amorphous structure or amorphous aluminum oxide as the insulator214because hydrogen can be effectively trapped or fixed in some cases. Accordingly, the transistor200and the semiconductor device with favorable characteristics and high reliability can be fabricated.

Next, the insulator216is formed over the insulator214. The insulator216is preferably formed by a sputtering method. Since a molecule containing hydrogen is not used as a deposition gas in the sputtering method, the concentration of hydrogen in the insulator216can be reduced. Note that the insulator216can be formed by a CVD method, an MBE method, a PLD method, an ALD method, or the like as well as the sputtering method.

In this embodiment, as the insulator216, silicon oxide is deposited by a pulsed DC sputtering method using a silicon target in an atmosphere containing an oxygen gas. The use of the pulsed DC sputtering can achieve more uniform film thickness and improve the sputtering rate and film quality.

The insulators212,214, and216are preferably formed successively without exposure to the air. For example, a multi-chamber film formation apparatus is used. As a result, the amount of hydrogen in the formed insulators212,214, and216can be reduced, and furthermore, entry of hydrogen in the films between film formation steps can be inhibited.

Then, an opening reaching the insulator214is formed in the insulator216. Examples of the opening include a groove and a slit. A region where the opening is formed may be referred to as an opening portion. Wet etching can be used for the formation of the opening; however, dry etching is preferable for microfabrication. The insulator214is preferably an insulator that functions as an etching stopper film when a groove is formed by etching of the insulator216. For example, in the case where silicon oxide or silicon oxynitride is used as the insulator216in which the groove is to be formed, the insulator214is preferably silicon nitride, aluminum oxide, or hafnium oxide.

As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus including parallel plate electrodes may have a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, different high-frequency voltages may be applied to one of the parallel plate electrodes. Further alternatively, high-frequency voltages with the same frequency may be applied to the parallel plate electrodes. Still further alternatively, high-frequency voltages with different frequencies may be applied to the parallel plate electrodes. A dry etching apparatus including a high-density plasma source can be used. As the dry etching apparatus including a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus can be used, for example.

After the formation of the opening, a conductive film to be the conductor205ais formed. The conductive film preferably contains a conductor that has a function of inhibiting transmission of oxygen. For example, tantalum nitride, tungsten nitride, or titanium nitride can be used. Alternatively, a stacked-layer film of the conductor that has a function of inhibiting transmission of oxygen and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, a titanium nitride film is deposited as the conductive film to be the conductor205a. When such a metal nitride is used for the layer under the conductor205bdescribed later, oxidation of the conductor205bby the insulator216or the like can be inhibited. Furthermore, even when a metal that is easily diffused, such as copper, is used as the conductor205b, the metal can be prevented from diffusing from the conductor205a.

Next, a conductive film to be the conductor205bis formed. The conductive film can be formed using tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a tungsten film is deposited as the conductive film.

Next, the conductive film to be the conductor205aand the conductive film to be the conductor205bare partly removed by CMP treatment to expose the insulator216(seeFIGS.7A to7D). As a result, the conductors205aand205bremain only in the opening portion. Note that the insulator216is partly removed by the CMP treatment in some cases.

Next, the insulator222is formed over the insulator216and the conductor205(seeFIG.8AtoFIG.8D). The insulator222is preferably formed using an insulator containing an oxide of one or both of aluminum and hafnium. As the insulator containing an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator222has a barrier property against hydrogen and water, diffusion of hydrogen and water contained in a structure body provided around the transistor200into the transistor200through the insulator222is inhibited, and accordingly oxygen vacancies are less likely to be generated in the oxide230.

The insulator222can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, hafnium oxide is formed as the insulator222by an ALD method.

Subsequently, heat treatment is preferably performed. The heat treatment is performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C., further preferably higher than or equal to 320° C. and lower than or equal to 450° C. The heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, in the case where the heat treatment is performed in an atmosphere of mixing a nitrogen gas and an oxygen gas, the proportion of the oxygen gas may be approximately 20%. The heat treatment may be performed under a reduced pressure. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in an atmosphere of a nitrogen gas or an inert gas, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for released oxygen.

The gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and further preferably 0.05 ppb or less. The heat treatment using a highly purified gas can prevent the entry of moisture or the like into the insulator222and the like as much as possible.

In this embodiment, as the heat treatment, after the formation of the insulator222, heat treatment at 400° C. for one hour is performed with a flow rate ratio of a nitrogen gas to an oxygen gas that is 4:1. By the heat treatment, impurities such as water or hydrogen included in the insulator222can be removed, for example. In the case where an oxide containing hafnium is used as the insulator222, the heat treatment makes part of the insulator222have crystallinity in some cases. The heat treatment can also be performed after the formation of the insulator224, or the like.

Next, an insulating film224A is formed over the insulator222(FIGS.8A to8D). The insulating film224A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulating film224A by a sputtering method. Since a molecule containing hydrogen is not used as a deposition gas in the sputtering method, the concentration of hydrogen in the insulating film224A can be reduced. The hydrogen concentration in the insulating film224A is preferably reduced because the insulating film224A is in contact with the oxide230in a later step.

Next, an oxide film230A is formed over the insulating film224A (seeFIG.8AtoFIG.8D). The oxide film230A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, in the case where the oxide film230A is formed by a sputtering method, oxygen or a mixed gas of oxygen and a noble gas is used as a sputtering gas. An increase in the proportion of oxygen in the sputtering gas can increase the amount of excess oxygen contained in the oxide film to be formed. Moreover, when the oxide films are formed by a sputtering method, a target of the In-M-Zn oxide can be used, for example.

When the oxide film230A is formed by a sputtering method and the proportion of oxygen in the sputtering gas is higher than 30% and lower than or equal to 100%, preferably higher than or equal to 70% and lower than or equal to 100%, an oxygen-excess oxide semiconductor is formed. A transistor including an oxygen-excess oxide semiconductor in a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. When the oxide film230A is formed by a sputtering method and the proportion of oxygen in the sputtering gas is higher than or equal to 1% and lower than or equal to 30%, preferably higher than or equal to 5% and lower than or equal to 20%, an oxygen-deficient oxide semiconductor is formed. A transistor including an oxygen-deficient oxide semiconductor in a channel formation region can have relatively high field-effect mobility. In addition, when the oxide film is formed while the substrate is being heated, the crystallinity of the oxide film can be improved.

In particular, in the formation of the oxide film230A, part of oxygen contained in the sputtering gas is supplied to the insulator224in some cases. Therefore, the proportion of oxygen in the sputtering gas may be preferably 70% or higher, further preferably 80% or higher, and still further preferably 100%.

Alternatively, it is preferable to employ an ALD method, for example, for formation of the oxide film230A, in which case a film with a uniform thickness can be formed in a groove or an opening having a large aspect ratio. Employing a PEALD method is preferable because the oxide film230A can be formed at a lower temperature than the case of employing a thermal ALD method.

In this embodiment, the oxide film230A is formed by a sputtering method using an oxide target with an atomic ratio of In:Ga:Zn=1:3:4. Note that the oxide film230A is formed by appropriate conditions of the film formation and the atomic ratio to have characteristics required for the oxide230.

Note that the insulating film224A and the oxide film230A are preferably deposited by a sputtering method without exposure to the air. For example, a multi-chamber film formation apparatus is used. In this manner, hydrogen can be prevented from entering the insulating film224A and the oxide film230A during each of film formation steps.

Next, heat treatment is preferably performed. The heat treatment is performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 400° C. and lower than or equal to 600° C. so that the oxide film230A does not become polycrystal. The heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, in the case where the heat treatment is performed in an atmosphere of mixing a nitrogen gas and an oxygen gas, the proportion of the oxygen gas may be approximately 20%. The heat treatment may be performed under a reduced pressure. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in an atmosphere of a nitrogen gas or an inert gas, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for released oxygen.

The gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and further preferably 0.05 ppb or less. The heat treatment using a highly purified gas can prevent the entry of moisture or the like into the oxide film230A and the like as much as possible.

In this embodiment, heat treatment at 400° C. for two hours is performed with a flow rate ratio of a nitrogen gas to an oxygen gas that is 4:1. With the heat treatment using the above-described oxygen gas, impurities such as carbon, hydrogen, and water in the oxide film230A can be reduced. Impurities in the film are reduced in the above manner, whereby the crystallinity of the oxide film230A can be improved and a dense structure can be obtained. Accordingly, the crystal region in the oxide film230A can be increased, and in-plane variation in the oxide film230A can be reduced. Thus, in-plane variation in electrical characteristics of the transistor200can be reduced.

Furthermore, the heat treatment using the above-described oxygen gas enables reductions in the density of tail states around the valence band or the density of deep-level states in the oxide film230A. As a result, the bandgap of the oxide film230A can be made wider than that before the heat treatment is performed. Alternatively, the number of electrons excited into the conduction band of the oxide film230A can be reduced. Consequently, degradation in transistor characteristics due to stray light can be reduced.

Next, a conductive film242A is formed over the oxide film230A (seeFIG.8AtoFIG.8D). The conductive film242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a tantalum nitride film may be deposited as the conductive film242A by a sputtering method. Note that heat treatment may be performed before the formation of the conductive film242A. The heat treatment may be performed under a reduced pressure, and the conductive film242A may be successively formed without exposure to the air. By such treatment, moisture and hydrogen adsorbed on the surface of the oxide film230A can be removed, and the moisture concentration and the hydrogen concentration in the oxide film230A can be reduced. The temperature of the heat treatment is preferably higher than or equal to 100° C. and lower than or equal to 400° C. In this embodiment, the temperature of the heat treatment is 200° C.

Next, an insulating film271A is formed over the conductive film242A (seeFIG.8AtoFIG.8D). The insulating film271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film271A is preferably an insulating film having a function of inhibiting the passage of oxygen. For example, an aluminum oxide film or a silicon nitride film is deposited as the insulating film271A by a sputtering method.

Note that the conductive film242A and the insulating film271A are preferably deposited by a sputtering method without exposure to the air. For example, a multi-chamber film formation apparatus is used. As a result, the amount of hydrogen in the formed conductive film242A and insulating film271A can be reduced, and furthermore, entry of hydrogen in the films between film formation steps can be inhibited. In the case where a hard mask is provided over the insulating film271A, a film to be the hard mask is preferably successively deposited without exposure to the air.

Next, the insulating film224A, the oxide film230A, the conductive film242A, and the insulating film271A are processed into island shapes by a lithography method, so that the insulator224, the oxide230, a conductive layer242B, and an insulating layer271B are formed (seeFIGS.9A to9D). The insulator224, the oxide230, the conductive layer242B, and the insulating layer271B are formed to overlap with the conductor205at least partly. The processing can be performed by a dry etching method or a wet etching method. A dry etching method is suitable for microfabrication. The insulating film224A, the oxide film230A, the conductive film242A, and the insulating film271A may be processed under different conditions.

In the lithography method, first, a resist is exposed to light through a mask. Next, a region exposed to light is removed or left using a developing solution, so that a resist mask is formed. Then, etching is conducted with the resist mask, whereby a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape. The resist mask is formed, for example, by exposing the resist to KrF excimer laser light, ArF excimer laser light, or extreme ultraviolet (EUV) light. A liquid immersion technique may be employed in which a portion between a substrate and a projection lens is filled with a liquid (e.g., water) to perform light exposure. An electron beam or an ion beam may be used instead of the above-mentioned light. Note that a photomask is not necessary in the case of using an electron beam or an ion beam. To remove the resist mask, dry etching treatment such as ashing or wet etching treatment can be used. Alternatively, wet etching treatment can be performed after dry etching treatment, or dry etching treatment can be performed after wet etching treatment.

A hard mask formed of an insulator or a conductor may be used under the resist mask. In the case of using a hard mask, a hard mask with a desired shape can be formed in the following manner: an insulating film or a conductive film that is the material of the hard mask is formed over the conductive film242A, a resist mask is formed thereover, and then the hard mask material is etched. The etching of the conductive film242A and the like may be performed after or without removal of the resist mask. In the latter case, the resist mask sometimes disappears during the etching. The hard mask may be removed by etching after the etching of the conductive film242A and the like. The hard mask does not need to be removed when the hard mask material does not affect the following process or can be utilized in the following process. In this embodiment, the insulating layer271B is used as a hard mask.

Here, the insulating layer271B functions as a mask for the conductive layer242B; thus, as illustrated inFIGS.9B to9D, the conductive layer242B does not have a curved surface between the side surface and the top surface. Thus, end portions at the intersection of the side surface and the top surface of the conductor242shown inFIGS.1B to1Dis angular. The cross-sectional area of the conductor242is larger in the case where an end portion at the intersection of the side surface and the top surface of the conductor242is angular than in the case where the end portion is rounded. Accordingly, the resistance of the conductor242is reduced, so that the on-state current of the transistor200can be increased.

Furthermore, as illustrated inFIGS.9B to9D, the side surfaces of the insulator224, the oxide230, the conductive layer242B, and the insulating layer271B may be formed to have tapered shapes. In this specification and the like, a tapered shape indicates a shape in which at least part of a side surface of a structure is inclined to a substrate surface. For example, the angle formed between the inclined side surface and the substrate surface (the angle is also referred to as a taper angle) is preferably less than 90°. Each of the insulator224, the oxide230, the conductive layer242B, and the insulating layer271B may be processed to have a taper angle greater than or equal to 60° and less than 90°. With such tapered shapes on the side surfaces, the coverage with the insulator275and the like can be improved in a later step, so that defects such as a void can be reduced.

Not being limited to the above, the insulator224, the oxide230, the conductive layer242B, and the insulating layer271B may be processed to have side surfaces that are substantially perpendicular to the top surface of the insulator222. When the side surfaces are substantially perpendicular to the top surface of the insulator222, a plurality of the transistors200can be provided with high density in a small area.

A by-product generated in the etching step is sometimes formed in a layered manner on the side surfaces of the insulator224, the oxide230, the conductive layer242B, and the insulating layer271B. In this case, the layered by-product is formed between the insulator275and the insulator224, the oxide230, the conductive layer242B, and the insulating layer271B. Hence, the layered by-product formed in contact with the top surface of the insulator222is preferably removed.

Next, the insulator275is formed to cover the insulator224, the oxide230, the conductive layer242B, and the insulating layer271B (seeFIGS.10A to10D). Here, it is preferable that the insulator275be in close contact with the top surface of the insulator222and the side surface of the insulator224. The insulator275can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator275is preferably formed using an insulating film having a function of inhibiting transmission of oxygen. For example, as the insulator275, aluminum oxide may be deposited by a sputtering method, and silicon nitride may be deposited thereover by a PEALD method. When the insulator275has such a stacked-layer structure, the function of inhibiting diffusion of impurities such as water or hydrogen and oxygen is improved in some cases.

In this manner, the oxide230and the conductive layer242B can be covered with the insulator275and the insulating layer271B, which have a function of inhibiting diffusion of oxygen. This structure enables inhabitation of diffusion of oxygen directly from the insulator280or the like into the insulator224, the oxide230, and the conductive layer242B in a later step.

Next, an insulating film to be the insulator280is formed over the insulator275. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, a silicon oxide film may be deposited as the insulating film by a sputtering method. When the insulating film is deposited by a sputtering method in an oxygen-containing atmosphere, the insulator280containing excess oxygen can be formed. Since a molecule containing hydrogen is not used as a deposition gas in the sputtering method, the concentration of hydrogen in the insulator280can be reduced. Note that heat treatment may be performed before the formation of the insulating film. The heat treatment may be performed under a reduced pressure, and the insulating film may be successively formed without exposure to the air. By such treatment, moisture and hydrogen adsorbed on the surface of the insulator275and the like can be removed, and the moisture concentration and the hydrogen concentration in the oxide230and the insulator224can be reduced. The heat treatment can be performed with the above-described heat treatment conditions.

Next, an insulating film to be the insulator280is subjected to CMP treatment, so that the insulator280having a flat top surface is formed (seeFIGS.10A to10D). Note that silicon nitride may be deposited over the insulator280by a sputtering method, for example, and then subjected to CMP treatment until the insulator280is exposed.

Subsequently, the insulator280, the insulator275, the insulating layer271B, and the conductive layer242B are partly processed to form an opening reaching the oxide230. The opening is preferably formed to overlap with the conductor205. The formation of the opening leads to formation of the insulator271a, the insulator271b, the conductor242a, and the conductor242b(seeFIG.11AtoFIG.11D).

As illustrated inFIGS.11B and11C, the side surfaces of the insulators280,275, and271and the conductor242may be tapered. The taper angle of the insulator280is larger than that of the conductor242in some cases. Although not illustrated in FIGS.11A to11C, the upper portion of the oxide230is removed in some cases when the opening is formed.

The insulator280, the insulator275, the insulating layer271B, and the conductive layer242B can be partly processed by a dry etching method or a wet etching method. A dry etching method is suitable for microfabrication. The processing may be performed under different conditions. For example, part of the insulator280may be processed by a dry etching method, parts of the insulator275and the insulating layer271B may be processed by a wet etching method, and part of the conductive layer242B may be processed by a dry etching method.

By the processing, in some cases, impurities are attached to the top and side surfaces of the oxide230, the side surface of the conductor242, and the side surface of the insulator280and diffuse therein. A step of removing the impurities may be performed. A damaged region is formed on the surface of the oxide230by the dry etching in some cases. Such a damaged region may be removed. The impurities result from components contained in the insulator280, the insulator275, the insulating layer271B, and the conductive layer242B; components contained in a member of an apparatus used to form the opening; and components contained in a gas or a liquid used for etching, for example. Examples of the impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

In particular, impurities such as aluminum and silicon hinder the oxide230from becoming a CAAC-OS. It is thus preferable to reduce or eliminate impurity elements such as aluminum and silicon, which hinder the oxide from becoming a CAAC-OS. For example, the concentration of aluminum atoms in the oxide230and in the vicinity thereof is lower than or equal to 5.0 atomic %, preferably lower than or equal to 2.0 atomic %, further preferably lower than or equal to 1.5 atomic %, still further preferably lower than or equal to 1.0 atomic %, and yet further preferably lower than 0.3 atomic %. A region of the metal oxide that is hindered from becoming CAAC-OS by the impurity such as aluminum or silicon and results in becoming a-like OS is sometimes referred to as a non-CAAC region. In the non-CAAC region, the density of the crystal structure is reduced to increase VOH; thus, the transistor is likely to be normally on. Hence, the non-CAAC region in the oxide230is preferably scaled down or removed.

In contrast, the oxide230preferably has a layered CAAC structure. In particular, the CAAC structure preferably reaches a lower edge of a drain in the oxide230. In the transistor200, the conductor242aor the conductor242b, and the vicinity thereof function as the drain. That is, the oxide230in the vicinity of the lower edge of the conductor242a(the conductor242b) preferably has the CAAC structure. In this manner, the damaged region is removed and the CAAC structure is formed in the oxide230also in the edge portion of the drain, which significantly affects the drain breakdown voltage, so that variations in the electrical characteristics of the transistor200can be further inhibited. Moreover, the reliability of the transistor200can be improved.

In order to remove the impurities attached to the surface of the oxide230in the etching step, cleaning treatment is performed. As the cleaning, any of wet cleaning using a cleaning solution or the like (also referred to as wet etching treatment), plasma treatment using plasma, cleaning by heat treatment, and the like can be performed by itself or in appropriate combination. The cleaning treatment sometimes makes the groove deeper.

The wet cleaning may be performed using an aqueous solution in which ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like is diluted with carbonated water or pure water; pure water; or carbonated water, for example. Alternatively, ultrasonic cleaning using such an aqueous solution, pure water, or carbonated water may be performed. Further alternatively, such cleaning methods may be performed in combination as appropriate.

Note that in this specification and the like, in some cases, an aqueous solution in which hydrofluoric acid is diluted with pure water is referred to as diluted hydrofluoric acid, and an aqueous solution in which ammonia water is diluted with pure water is referred to as diluted ammonia water. The concentration, temperature, and the like of the aqueous solution may be adjusted as appropriate in accordance with an impurity to be removed, the structure of a semiconductor device to be cleaned, or the like. The concentration of ammonia in the diluted ammonia water may be higher than or equal to 0.01% and lower than or equal to 5%, preferably higher than or equal to 0.1% and lower than or equal to 0.5%. The concentration of hydrogen fluoride in the diluted hydrofluoric acid may be higher than or equal to 0.01 ppm and lower than or equal to 100 ppm, preferably higher than or equal to 0.1 ppm and lower than or equal to 10 ppm.

A frequency greater than or equal to 200 kHz, preferably greater than or equal to 900 kHz is preferably used for the ultrasonic cleaning. Damage to the oxide230and the like can be reduced with this frequency.

The cleaning treatment may be performed plural times, and the cleaning solution may be changed in every cleaning treatment. For example, the first cleaning treatment may use diluted hydrofluoric acid or diluted ammonia water and the second cleaning treatment may use pure water or carbonated water.

In this embodiment, as the cleaning, wet cleaning is performed with use of diluted ammonia water. The cleaning treatment allows removing impurities that are attached onto the surfaces of the oxide230and the like or diffused into the oxide230and the like. Furthermore, the crystallinity of the oxide230can be improved.

After the etching or the cleaning, heat treatment may be performed. The heat treatment may be performed at a temperature higher than or equal to 100° C. and lower than or equal to 450° C., preferably higher than or equal to 350° C. and lower than or equal to 400° C. The heat treatment is performed in a nitrogen gas atmosphere, an inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. Accordingly, oxygen can be supplied to the oxide230to reduce oxygen vacancies. In addition, the crystallinity of the oxide230can be improved by the heat treatment. The heat treatment may be performed under a reduced pressure. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in an oxygen atmosphere, and then another heat treatment is successively performed in a nitrogen atmosphere without exposure to the air.

Next, an insulating film252A is formed (seeFIGS.12A to12D). The insulating film252A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film252A is preferably formed by an ALD method. As described above, it is preferable to form the insulating film252A to have a small thickness, and an unevenness of the thickness needs to be reduced. In the ALD method, a precursor and a reactant (such as oxidizer) are alternately introduced to deposit a film, and the film thickness can be adjusted by the number of repetition times of the sequence of the gas introduction; thus, accurate control of the film thickness is possible. Furthermore, as illustrated inFIG.12BandFIG.12C, the insulating film252A needs to be deposited on the bottom surface and the side surface of the opening formed in the insulator280and the like so as to have good coverage. In particular, it is preferable that the insulating film252A be deposited on the top and side surfaces of the oxide230and the side surface of the conductor242so as to have good coverage. One atomic layer can be deposited at a time on the bottom and side surfaces of the opening, whereby the insulating film252A can be formed in the opening with good coverage.

When the insulating film252A is deposited by an ALD method, ozone (O3), oxygen (O2), water (H2O), or the like is used as the oxidizer. When an oxidizer without hydrogen, such as (O3) or (O2), is used, the amount of hydrogen diffusing into the oxide230can be reduced.

In this embodiment, an aluminum oxide film is formed as the insulating film252A by a thermal ALD method.

Next, an insulating film250A is formed (seeFIGS.12A to12D). Heat treatment may be performed before the insulating film250A is formed; it is preferable that the heat treatment be performed under a reduced pressure and the insulating film250A be successively formed without exposure to the air. The heat treatment is preferably performed in an oxygen-containing atmosphere. By such treatment, moisture and hydrogen adsorbed on the surface of the insulating film252A and the like can be removed, and the moisture concentration and the hydrogen concentration in the oxide230can be reduced. The temperature of the heat treatment is preferably higher than or equal to 100° C. and lower than or equal to 400° C.

The insulating film250A can be formed by a sputtering method, a CVD method, a PECVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film250A is preferably formed by a deposition method using a material in which the number of hydrogen atoms is reduced or hydrogen atoms are removed. This reduces the hydrogen concentration of the insulating film250A. The hydrogen concentration in the insulating film250A is preferably reduced because the insulating film250A becomes the insulator250that faces the oxide230with the thin insulator252sandwiched therebetween.

The insulating film250A is preferably formed by a CVD method or an ALD method, for example. It is particularly preferable to employ an ALD method, in which case a film with an uniform thickness can be formed in a groove or an opening having a large aspect ratio. It is also preferable to employ a PEALD method, in which case the insulating film250A can be formed at a lower temperature than the case of employing a thermal ALD method.

When the insulating film250A is formed by a PEALD method, a gas containing an organic such as bis(diethylamino)silane (BDEAS: SiH2[N(C2H5)2]2) or tris(diethylamino)silane (3DMAS: SiH[N(CH3)2]3) can be used as a precursor. Alternatively, the precursor may be a gas containing silicon and no hydrocarbon (also referred to as an inorganic precursor), such as SiH4, Si2H6, SiF4, SiCl4, SiBr4, SiH2Cl2, or SiH2I2. As an oxidation gas, O2, N2O, CO2, O3, NO2, H2O, or the like can be used. As the oxidation gas, O2or N2O is much preferable when a PEALD method is employed. Alternatively, a noble gas such as helium, neon, argon, krypton, or xenon may be added to the oxidation gas.

For example, the insulating film250A is preferably formed by a PEALD method with use of BDEAS as a precursor and a mixed gas of O2and argon as an oxidizer. Use of an oxidation gas not containing a nitrogen atom enables the nitrogen concentration in the insulating film250A to be reduced in some cases.

In this embodiment, the insulating film250A is formed by a PEALD method.

Next, it is preferable to perform microwave treatment in an atmosphere containing oxygen (seeFIGS.12A to12D).

Here, dotted lines inFIG.12BtoFIG.12Dindicate microwaves, high-frequency waves such as RF, oxygen plasma, oxygen radicals, or the like. The microwave treatment is preferably performed with a microwave treatment apparatus including a power source for generating high-density plasma using microwaves, for example. Here, the frequency of the microwave treatment apparatus is set to greater than or equal to 300 MHz and less than or equal to 300 GHz, preferably greater than or equal to 2.4 GHz and less than or equal to 2.5 GHz, for example, 2.45 GHz. Oxygen radicals at a high density can be generated with high-density plasma. The electric power of the power source that applies microwaves of the microwave treatment apparatus is set to higher than or equal to 1000 W and lower than or equal to 10000 W, preferably higher than or equal to 2000 W and lower than or equal to 5000 W. A power source may be provided to the microwave treatment apparatus to apply RF to the substrate side. Furthermore, application of RF to the substrate side allows oxygen ions generated by the high-density plasma to permeate the oxide230efficiently.

The microwave treatment is preferably performed under reduced pressure, and the pressure may be higher than or equal to 10 Pa and lower than or equal to 1000 Pa, preferably higher than or equal to 300 Pa and lower than or equal to 700 Pa. The treatment temperature is lower than or equal to 750° C., preferably lower than or equal to 500° C., and may be approximately 400° C., for example. The oxygen plasma treatment can be followed successively by heat treatment without exposure to air. For example, the temperature may be higher than or equal to 100° C. and lower than or equal to 750° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C.

Furthermore, the microwave treatment is performed using an oxygen gas and an argon gas, for example. Here, the oxygen flow rate ratio (O2/O2+Ar) is higher than 0% and lower than or equal to 100%. The oxygen flow rate ratio (O2/O2+Ar) is preferably higher than 0% and lower than or equal to 50%. The oxygen flow rate ratio (O2/O2+Ar) is further preferably higher than or equal to 10% and lower than or equal to 40%. The oxygen flow rate ratio (O/O2+Ar) is still further preferably higher than or equal to 10% and lower than or equal to 30%. The carrier concentration in the region230bccan be reduced by thus performing the microwave treatment in an atmosphere containing oxygen. In addition, the carrier concentrations in the region230baand the region230bbcan be prevented from being excessively reduced by preventing an excessive amount of oxygen from being introduced into the chamber in the microwave treatment.

The microwave treatment in an oxygen-containing atmosphere converts oxygen gas into plasma using a microwave or a high-frequency wave such as RF, and applies the oxygen plasma to a region of the oxide230that is between the conductor242aand the conductor242bas illustrated inFIGS.12B to12D. At this time, the region230bccan be irradiated with the microwave or the high-frequency wave such as RF. In other words, the microwave, the high-frequency wave such as RF, the oxygen plasma, and the like can be applied to the region230cillustrated inFIG.6A. The effect of the plasma, the microwave, and the like enables VOH in the region230bcto be cut off, and hydrogen (H) to be removed from the region230bc. That is, the reaction “VOH→H+VO” occurs in the region230bc, so that the VOH in the region230bccan be reduced. As a result, oxygen vacancies and VOH in the region230bccan be reduced to lower the carrier concentration. In addition, oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator250can be supplied to oxygen vacancies formed in the region230bc, thereby further reducing oxygen vacancies and lowering the carrier concentration in the region230bc.

By contrast, the conductor242aand the conductor242bare provided over the region230baand the region230bbillustrated inFIG.6A. The conductor242preferably functions as a blocking film preventing the effect caused by the microwave, the high-frequency wave such as RF, the oxygen plasma, or the like in the microwave treatment in an atmosphere containing oxygen. Therefore, the conductor242preferably has a function of blocking an electromagnetic wave greater than or equal to 300 MHz and less than or equal to 300 GHz, for example, greater than or equal to 2.4 GHz and less than or equal to 2.5 GHz.

As illustrated inFIGS.12B to12D, the effects of the microwave, the high-frequency wave such as RF, the oxygen plasma, and the like are blocked by the conductor242aand the conductor242b, and thus, are not applied to the region230baand the region230bb. Hence, a reduction in VOH and supply of too much oxygen due to the microwave treatment do not occur in the region230baand the region230bb, preventing a decrease in carrier concentration therein.

Furthermore, the insulator252having a barrier property against oxygen is provided in contact with the side surfaces of the conductor242aand the conductor242b. Thus, formation of oxide films on the side surfaces of the conductor242aand the conductor242bby the microwave treatment can be inhibited.

In the above manner, oxygen vacancies and VOH can be selectively removed from the region230bcin the oxide semiconductor, whereby the region230bccan be an i-type or substantially i-type region. Furthermore, supply of an excess amount of oxygen to the region230baand the region230bbfunctioning as the source region and the drain region can be inhibited and the n-type regions before the microwave treatment can be maintained. As a result, a change in the electrical characteristics of the transistor200can be inhibited, and thus variation in the electrical characteristics of the transistors200in the substrate plane can be inhibited.

In the microwave treatment, thermal energy is directly transmitted to the oxide230in some cases owing to an electromagnetic interaction between the microwave and a molecule in the oxide230. The oxide230might be heated by this thermal energy. Such heat treatment is sometimes referred to as microwave annealing. When microwave treatment is performed in an atmosphere containing oxygen, an effect equivalent to that of oxygen annealing might be obtained. In the case where hydrogen is contained in the oxide230, it is probable that the thermal energy is transmitted to the hydrogen in the oxide230and the hydrogen activated by the energy is released from the oxide230.

In the case where the insulator250has a two-layer structure as illustrated inFIG.6B, an insulating film to be the insulator250bis formed after the formation of the insulating film250A. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film preferably has a function of inhibiting the diffusion of oxygen. Owing to this structure, the diffusion of oxygen contained in the insulator250ainto the conductor260can be inhibited. That is, a reduction in the amount of oxygen supplied to the oxide230can be inhibited. Moreover, oxidation of the conductor260due to oxygen contained in the insulator250acan be inhibited. For example, the insulating film can be formed using a material similar to that used for the insulator222. For example, the hafnium oxide film may be formed by a thermal ALD method as the insulating film.

The microwave treatment may be performed after the insulating film252A is formed (before the insulating film250A is formed) under the conditions for microwave treatment performed after the formation of the insulating film250A. Furthermore, the microwave treatment performed after the formation of the insulating film250A may be omitted and the microwave treatment may be performed after the formation of the insulating film252A. In the case where the insulating film to be the insulator250bis provided as described above, microwave treatment may be performed after the formation of the insulating film. In this case, the microwave treatment may be performed under the conditions for microwave treatment performed after the formation of the insulating film250A. Furthermore, the microwave treatment performed after the formation of the insulating film252A and/or the insulating film250A may be omitted, and the microwave treatment may be performed after the formation of the insulating film to be the insulator250b.

Heat treatment with the reduced pressure being maintained may be performed at one or a plurality of timings after the formation of the insulating film252A, after the formation of the insulating film250A, and after the formation of the insulating film to be the insulator250b. Such treatment enables hydrogen in the insulating film252A, the insulating film250A, the insulating film to be the insulator250b, and the oxide230to be removed efficiently. Some hydrogen may be gettered by the conductor242. It is possible to repeat the step of performing heat treatment with the reduced pressure being maintained after the microwave treatment. The repetition of the heat treatment enables hydrogen in the insulating film252A, the insulating film250A, the insulating film to be the insulator250b, and the oxide230to be removed more efficiently. Note that the temperature of the heat treatment is preferably higher than or equal to 300° C. and lower than or equal to 500° C. The microwave treatment, i.e., the microwave annealing may also serve as the heat treatment. The heat treatment is not necessarily performed in the case where the oxide230and the like are sufficiently heated by the microwave annealing.

The microwave treatment improves the film quality of the insulating film252A, the insulating film250A, and the insulating film to be the insulator250b, which can lead to inhibition of diffusion of hydrogen, water, impurities, and the like. Accordingly, hydrogen, water, impurities, and the like can be inhibited from diffusing into the oxide230and the like through the insulator252in the following step such as formation of a conductive film to be the conductor260or the following treatment such as heat treatment.

Next, an insulating film254A is formed (seeFIGS.13A to13D). The insulating film254A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film254A is preferably formed by an ALD method, like the insulating film252A. By an ALD method, the insulating film254A can be formed to have small thickness and good coverage. In this embodiment, a silicon nitride film is formed as the insulating film254A by a PEALD method.

Next, a conductive film to be the conductor260aand a conductive film to be the conductor260bare deposited in this order. The conductive film to be the conductor260aand the conductive film to be the conductor260bcan be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a titanium nitride film is deposited as the conductive film to be the conductor260aby an ALD method, and a tungsten film is deposited as the conductive film to be the conductor260bby a CVD method.

Next, the insulating film252A, the insulating film250A, the insulating film254A, the conductive film to be the conductor260a, and the conductive film to be the conductor260bare polished by CMP treatment until the insulator280is exposed, whereby the insulator252, the insulator250, the insulator254, and the conductor260(the conductor260aand the conductor260b) are formed (seeFIG.14AtoFIG.14D). Thus, the insulator252is positioned to cover the opening reaching the oxide230. The conductor260is positioned to fill the opening with the insulator252, the insulator250, and the insulator254placed therebetween.

Then, heat treatment may be performed under conditions similar to those of the above heat treatment. In this embodiment, the heat treatment is performed at 400° C. in a nitrogen atmosphere for one hour. The heat treatment can reduce the moisture concentration and the hydrogen concentration in the insulators250and280. The insulator282can be formed successively after the heat treatment without exposure to the air.

Next, the insulator282is formed over the insulator252, the insulator250, the insulator254, the conductor260, and the insulator280(seeFIG.14AtoFIG.14D). The insulator282can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator282is preferably formed by a sputtering method. Since a molecule containing hydrogen is not used as a deposition gas in the sputtering method, the concentration of hydrogen in the insulator282can be reduced.

In this embodiment, as the insulator282, aluminum oxide is deposited by a pulsed DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas. The use of the pulsed DC sputtering can achieve more uniform film thickness and improve the sputtering rate and film quality.

Forming the insulator282in an atmosphere containing oxygen by a sputtering method can provide oxygen to the insulator280during the formation. Thus, excess oxygen can be contained in the insulator280. The formation of the insulator282is preferably performed while the substrate is heated.

Next, the insulator283is formed over the insulator282. The insulator283can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator283is preferably formed by a sputtering method. Since a molecule containing hydrogen is not used as a deposition gas in the sputtering method, the concentration of hydrogen in the insulator283can be reduced. The insulator283may have a multilayer structure. For example, silicon nitride may be deposited by a sputtering method and another silicon nitride may be deposited by an ALD method over the silicon nitride. Forming the insulator283having a high barrier property over the transistor200can prevent entry of moisture and hydrogen from the outside.

Next, the insulator285is formed over the insulator283(seeFIGS.15A to15D). The insulator285can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator285is preferably formed by a sputtering method. Since a molecule containing hydrogen is not used as a deposition gas in the sputtering method, the concentration of hydrogen in the insulator285can be reduced.

In this embodiment, silicon oxide is deposited as the insulator285by a sputtering method.

Subsequently, openings reaching the conductor242are formed in the insulators271,275,280,282,283, and285(seeFIGS.15A and15B). The opening are formed by a lithography method. Note that the openings in the top view inFIG.15Aeach have a circular shape; however, the shapes of the openings are not limited thereto. For example, the openings in the top view may each have an almost circular shape such as an elliptical shape, a polygonal shape such as a quadrangular shape, or a polygonal shape such as a quadrangular shape with rounded corners.

Then, an insulating film to be the insulator241aand the insulator241bis formed and subjected to anisotropic etching, so that the insulator241is formed (seeFIG.15B). The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film preferably has a function of inhibiting the passage of oxygen. For example, it is preferable that an aluminum oxide film be deposited by an ALD method and a silicon nitride film be deposited thereover by a PEALD method. Silicon nitride is particularly preferable because of its high hydrogen blocking property.

As an anisotropic etching for the insulating film to be the insulator241aand the insulator241b, a dry etching method may be performed, for example. The insulator241is provided on the sidewall of the opening. This inhibits transmission of oxygen from the outside to inhibit oxidation of the conductor240. Furthermore, diffusion of impurities such as water or hydrogen contained in the insulator280or the like into the conductor240can be prevented.

Next, a conductive film to be the conductor240aand the conductor240bis formed. The conductive film preferably has a stacked-layer structure including a conductor with a function of inhibiting passage of impurities such as water or hydrogen. For example, a stacked-layer structure of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be employed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the conductive film to be the conductors240aand240bis partly removed by CMP treatment to expose the top surface of the insulator285. As a result, the conductive film remains only in the openings, whereby the conductors240aand240bhaving flat top surfaces can be formed (seeFIGS.15A to15D). The CMP treatment may remove part of the top surface of the insulator285.

Next, a conductive film to be the conductor246aand the conductor246bis formed. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Next, the conductive film to be the conductor246aand the conductor246bis processed by a lithography method to form the conductor246ain contact with the top surface of the conductor240aand the conductor246bin contact with the top surface of the conductor240b. At this time, part of the insulator285in a region not overlapping with the conductors246aand246bis sometimes removed.

Through the above process, the semiconductor device including the transistor200illustrated inFIGS.1A to1Dcan be manufactured. By the manufacturing method of a semiconductor device which is described in this embodiment and illustrated inFIGS.7A to15D, the transistor200can be formed.

A microwave treatment apparatus that can be used for the above method for manufacturing the semiconductor device is described below.

First, a structure of a manufacturing apparatus which allows the entry of few impurities into a film at the time of fabrication of a semiconductor device or the like is described with reference toFIG.16,FIG.17,FIG.18, andFIG.19.

FIG.16is a top view schematically illustrating a single wafer multi-chamber manufacturing apparatus2700. The manufacturing apparatus2700includes an atmosphere-side substrate supply chamber2701including a cassette port2761for holding a substrate and an alignment port2762for performing alignment of a substrate, an atmosphere-side substrate transfer chamber2702through which a substrate is transferred from the atmosphere-side substrate supply chamber2701, a load lock chamber2703awhere a substrate is carried and the pressure inside the chamber is switched from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure, an unload lock chamber2703bwhere a substrate is carried out and the pressure inside the chamber is switched from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure, a transfer chamber2704through which a substrate is transferred in a vacuum, and chambers2706a,2706b,2706c, and2706d.

The atmosphere-side substrate transfer chamber2702is connected to the load lock chamber2703aand the unload lock chamber2703b, the load lock chamber2703aand the unload lock chamber2703bare connected to the transfer chamber2704, and the transfer chamber2704is connected to the chambers2706a,2706b,2706c, and2706d.

Note that gate valves GV are provided in connecting portions between the chambers so that each chamber excluding the atmosphere-side substrate supply chamber2701and the atmosphere-side substrate transfer chamber2702can be independently kept in a vacuum state. In addition, the atmosphere-side substrate transfer chamber2702is provided with a transfer robot2763a, and the transfer chamber2704is provided with a transfer robot2763b. With the transfer robot2763aand the transfer robot2763b, a substrate can be transferred inside the manufacturing apparatus2700.

In the transfer chamber2704and each of the chambers, the back pressure (total pressure) is, for example, lower than or equal to 1×10−4Pa, preferably lower than or equal to 3×10−5Pa, further preferably lower than or equal to 1×10−5Pa. In the transfer chamber2704and each of the chambers, the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 18 is, for example, lower than or equal to 3×10−5Pa, preferably lower than or equal to 1×10−5Pa, further preferably lower than or equal to 3×10−5Pa. Moreover, in the transfer chamber2704and each of the chambers, the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 28 is, for example, lower than or equal to 3×10−5Pa, preferably lower than or equal to 1×10−5Pa, further preferably lower than or equal to 3×10−5Pa. Furthermore, in the transfer chamber2704and each of the chambers, the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 44 is, for example, lower than or equal to 3×10−5Pa, preferably lower than or equal to 1×10−5Pa, further preferably lower than or equal to 3×10−6Pa.

Note that the total pressure and the partial pressure in the transfer chamber2704and each of the chambers can be measured using an ionization vacuum gauge, a mass analyzer, or the like.

Moreover, the transfer chamber2704and each of the chambers preferably have a small amount of external leakage or internal leakage. For example, the leakage rate of the transfer chamber2704is less than or equal to 1×100Pa/min., preferably less than or equal to 5×10−1Pa/min. In addition, the leakage rate of each chamber is less than or equal to 1×10−1Pa/min., preferably lower than or equal to 5×10−2Pa/min.

Note that a leakage rate can be derived from the total pressure and partial pressure measured using the ionization vacuum gauge, the mass analyzer, or the like. For example, the leakage rate is preferably derived from the total pressure at the time when 10 minutes have passed from the start of evacuation to a vacuum using a vacuum pump such as a turbo molecular pump and the total pressure at the time when 10 minutes have passed from the operation of closing the valve. Note that the total pressure at the time of 10 minutes passing from the start of evacuation to a vacuum is preferably an average value of total pressures measured a plurality of times.

The leakage rate depends on external leakage and internal leakage. The external leakage refers to inflow of gas from the outside of a vacuum system through a minute hole, a sealing defect, or the like. The internal leakage is due to leakage through a partition, such as a valve, in a vacuum system or due to released gas from an internal member. Measures need to be taken from both aspects of external leakage and internal leakage so that the leakage rate can be set to be less than or equal to the above-mentioned value.

For example, open/close portions of the transfer chamber2704and the chambers can be sealed with a metal gasket. For the metal gasket, metal covered with iron fluoride, aluminum oxide, or chromium oxide is preferably used. The metal gasket realizes higher adhesion than an O-ring, and can reduce the external leakage. Furthermore, with use of the metal covered with iron fluoride, aluminum oxide, chromium oxide, or the like, which is in the passive state, the release of gas containing impurities released from the metal gasket is suppressed, so that the internal leakage can be reduced.

For a member of the manufacturing apparatus2700, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which releases a small amount of gas containing impurities, is used. Alternatively, an alloy containing iron, chromium, nickel, or the like covered with the above material from which releases a small amount of gas containing the impurities may be used. The alloy containing iron, chromium, nickel, or the like is rigid, resistant to heat, and suitable for processing. Here, when surface unevenness of the member is decreased by polishing or the like to reduce the surface area, the release of gas can be reduced.

Alternatively, the above member of the manufacturing apparatus2700may be covered with iron fluoride, aluminum oxide, chromium oxide, or the like.

The member of the manufacturing apparatus2700is preferably formed using only metal when possible. For example, in the case where a viewing window formed of quartz or the like is provided, it is preferable that the surface of the viewing window be thinly covered with iron fluoride, aluminum oxide, chromium oxide, or the like so as to suppress release of gas.

When an adsorbed substance is present in the transfer chamber2704and each of the chambers, although the adsorbed substance does not affect the pressure in the transfer chamber2704and each of the chambers because it is adsorbed onto an inner wall or the like, the adsorbed substance causes a release of gas when the insides of the transfer chamber2704and each of the chambers is evacuated. Therefore, although there is no correlation between the leakage rate and the exhaust rate, it is important that the adsorbed substance present in the transfer chamber2704and each of the chambers be desorbed as much as possible and exhaust be performed in advance with use of a pump with high exhaust capability. Note that the transfer chamber2704and each of the chambers may be subjected to baking to promote desorption of the adsorbed substance. By the baking, the desorption rate of the adsorbed substance can be increased about tenfold. The baking can be performed at a temperature higher than or equal to 100° C. and lower than or equal to 450° C. At this time, when the adsorbed substance is removed while an inert gas is introduced into the transfer chamber2704and each of the chambers, the desorption rate of water or the like, which is difficult to desorb simply by exhaust, can be further increased. Note that when the inert gas that is introduced is heated to substantially the same temperature as the baking temperature, the desorption rate of the adsorbed substance can be further increased. Here, a noble gas is preferably used as the inert gas.

Alternatively, treatment for evacuating the insides of the transfer chamber2704and each of the chambers is preferably performed a certain period of time after heated oxygen, a heated inert gas such as a heated noble gas, or the like is introduced to increase the pressures in the transfer chamber2704and each of the chambers. The introduction of the heated gas can desorb the adsorbed substance in the transfer chamber2704and each of the chambers, and the impurities present in the transfer chamber2704and each of the chambers can be reduced. Note that an advantageous effect can be achieved when this treatment is repeated more than or equal to 2 times and less than or equal to 30 times, preferably more than or equal to 5 times and less than or equal to 15 times. Specifically, an inert gas, oxygen, or the like with a temperature higher than or equal to 40° C. and lower than or equal to 400° C., preferably higher than or equal to 50° C. and lower than or equal to 200° C. is introduced to the transfer chamber2704and each of the chambers, so that the pressure therein can be kept to be higher than or equal to 0.1 Pa and lower than or equal to 10 kPa, preferably higher than or equal to 1 Pa and lower than or equal to 1 kPa, further preferably higher than or equal to 5 Pa and lower than or equal to 100 Pa in the time range of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. After that, the inside of the transfer chamber2704and each of the chambers is evacuated in the time range of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

Next, the chambers2706band2706care described with reference to a schematic cross-sectional view ofFIG.17.

The chambers2706band2706care chambers capable of performing microwave treatment on an object, for example. Note that the chamber2706bis different from the chamber2706conly in the atmosphere in which microwave treatment is performed. The other structures are common and thus collectively described below.

The chambers2706band2706ceach include a slot antenna plate2808, a dielectric plate2809, a substrate holder2812, and an exhaust port2819. A gas supply source2801, a valve2802, a high-frequency generator2803, a waveguide2804, a mode converter2805, a gas pipe2806, a waveguide2807, a matching box2815, a high-frequency power source2816, a vacuum pump2817, and a valve2818are provided outside the chambers2706band2706c.

The high-frequency generator2803is connected to the mode converter2805through the waveguide2804. The mode converter2805is connected to the slot antenna plate2808through the waveguide2807. The slot antenna plate2808is positioned in contact with the dielectric plate2809. Furthermore, the gas supply source2801is connected to the mode converter2805through the valve2802. Gas is transferred to the chambers2706band2706cthrough the gas pipe2806which runs through the mode converter2805, the waveguide2807, and the dielectric plate2809. The vacuum pump2817has a function of exhausting gas or the like from the chambers2706band2706cthrough the valve2818and the exhaust port2819. The high-frequency power source2816is connected to the substrate holder2812through the matching box2815.

As the vacuum pump2817, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, a turbomolecular pump, or the like can be used, for example. In addition to the vacuum pump2817, a cryotrap may be used as well. The combinational use of the cryopump and the cryotrap allows water to be efficiently exhausted and is particularly preferable.

For example, the heating mechanism2813may be a heating mechanism which uses a resistance heater or the like for heating. Alternatively, heat conduction or heat radiation from a medium such as a heated gas may be used as the heating mechanism. For example, rapid thermal annealing (RTA) such as gas rapid thermal annealing (GRTA) or lamp rapid thermal annealing (LRTA) can be used. In the GRTA apparatus, heat treatment is performed using a high-temperature gas. An inert gas is used as a gas.

The gas supply source2801may be connected to a purifier through a mass flow controller. As the gas, a gas whose dew point is −80° C. or lower, preferably −100° C. or lower is preferably used. For example, an oxygen gas, a nitrogen gas, or a noble gas (e.g., an argon gas) may be used.

As the dielectric plate2809, silicon oxide (quartz), aluminum oxide (alumina), yttrium oxide (yttria), or the like may be used, for example. A protective layer may be further formed on a surface of the dielectric plate2809. As the protective layer, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, yttrium oxide, or the like may be used. The dielectric plate2809is exposed to an especially high density region of high-density plasma2810that is to be described later. Therefore, the protective layer can reduce the damage and consequently prevent an increase of particles or the like during the treatment.

The high-frequency generator2803has a function of generating a microwave with a frequency of, for example, greater than or equal to 0.3 GHz and less than or equal to 3.0 GHz, greater than or equal to 0.7 GHz and less than or equal to 1.1 GHz, or greater than or equal to 2.2 GHz and less than or equal to 2.8 GHz. The microwave generated by the high-frequency generator2803is propagated to the mode converter2805through the waveguide2804. The mode converter2805converts the microwave propagated in the TE mode into a microwave in the TEM mode. Then, the microwave is propagated to the slot antenna plate2808through the waveguide2807. The slot antenna plate2808is provided with a plurality of slot holes, and the microwave propagates through the slot holes and the dielectric plate2809. Then, an electric field is generated below the dielectric plate2809, and the high-density plasma2810can be generated. The high-density plasma2810includes ions and radicals depending on the gas species supplied from the gas supply source2801. For example, oxygen radicals or the like are included.

At this time, the quality of a film or the like over the substrate2811can be modified by the ions and radicals generated in the high-density plasma2810. Note that it is preferable in some cases to apply a bias to the substrate2811using the high-frequency power source2816. As the high-frequency power source2816, a radio frequency (RF) power source with a frequency of 13.56 MHz, 27.12 MHz, or the like may be used, for example. The application of a bias to the substrate allows ions in the high-density plasma2810to efficiently reach a deep portion of an opening of the film or the like over the substrate2811.

For example, in the chamber2706bor the chamber2706c, oxygen radical treatment using the high-density plasma2810can be performed by introducing oxygen from the gas supply source2801.

Next, the chambers2706aand2706dare described with reference to a schematic cross-sectional view ofFIG.18.

The chambers2706aand2706dare chambers capable of irradiating an object with an electromagnetic wave, for example. Note that the chamber2706ais different from the chamber2706donly in the kind of the electromagnetic wave. The other structures have many common portions and thus are collectively described below.

The chambers2706aand2706deach include one or more lamps2820, a substrate holder2825, a gas inlet2823, and an exhaust port2830. A gas supply source2821, a valve2822, a vacuum pump2828, and a valve2829are provided outside the chambers2706aand2706d.

The gas supply source2821is connected to the gas inlet2823through the valve2822. The vacuum pump2828is connected to the exhaust port2830through the valve2829. The lamp2820is provided to face the substrate holder2825. The substrate holder2825has a function of holding a substrate2824. The substrate holder2825includes a heating mechanism2826therein and thus has a function of heating the substrate2824.

As the lamp2820, a light source having a function of emitting an electromagnetic wave such as visible light or ultraviolet light may be used, for example. For example, a light source having a function of emitting an electromagnetic wave which has a peak in a wavelength region longer than or equal to 10 nm and shorter than or equal to 2500 nm, longer than or equal to 500 nm and shorter than or equal to 2000 nm, or longer than or equal to 40 nm and shorter than or equal to 340 nm may be used.

As the lamp2820, a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp may be used, for example.

For example, part of or the whole electromagnetic wave emitted from the lamp2820is absorbed by the substrate2824, so that the quality of a film or the like over the substrate2824can be modified. For example, defects can be generated or reduced or impurities can be removed. When the substrate2824absorbs the electromagnetic wave while being heated, generation or reduction of defects or removal of impurities can be efficiently performed.

Alternatively, for example, the electromagnetic wave emitted from the lamp2820may cause heat generation in the substrate holder2825, by which the substrate2824may be heated. In this case, the heating mechanism2826inside the substrate holder2825may be omitted.

For the vacuum pump2828, the description of the vacuum pump2817is referred to. For the heating mechanism2826, the description of the heating mechanism2813is referred to. For the gas supply source2821, the description of the gas supply source2801is referred to.

A microwave treatment apparatus that can be used in this embodiment is not limited to the above. It is possible to use a microwave treatment apparatus2900shown inFIG.19. The microwave treatment apparatus2900includes a quartz tube2901, the exhaust port2819, the gas supply source2801, the valve2802, the high-frequency generator2803, the waveguide2804, the gas pipe2806, the vacuum pump2817, and the valve2818. Furthermore, the microwave treatment apparatus2900includes a substrate holder2902that holds a plurality of substrates2811(2811_1to2811_n, n is an integer greater than or equal to 2) in the quartz tube2901. The microwave treatment apparatus2900may further include a heating means2903outside the quartz tube2901.

The substrate placed in the quartz tube2901is irradiated with the microwave generated by the high-frequency generator2803and passing through the waveguide2804. The vacuum pump2817is connected to the exhaust port2819through the valve2818and can adjust the pressure inside the quartz tube2901. The gas supply source2801is connected to the gas pipe2806through the valve2802and can introduce a desired gas into the quartz tube2901. The heating means2903can heat the substrate2811in the quartz tube2901to a desired temperature. Alternatively, the heating means2903may heat the gas which is supplied from the gas supply source2801. With use of the microwave treatment apparatus2900, the substrate2811can be subjected to heat treatment and microwave treatment at the same time. Alternatively, the substrate2811can be heated and then subjected to microwave treatment. Alternatively, the substrate2811can be subjected to microwave treatment and then heat treatment.

All of the substrate2811_1to the substrate2811_nmay be substrates to be treated where a semiconductor device or a memory device is to be formed, or some of the substrates may be dummy substrates. For example, the substrate2811_1and the substrate2811_nmay be dummy substrates and the substrate2811_2to the substrate2811_n−1 may be substrates to be treated. Alternatively, the substrate2811_1, the substrate2811_2, the substrate2811_n−1, and the substrate2811_nmay be dummy substrates and the substrate2811_3to the substrate2811_n−2 may be substrates to be treated. A dummy substrate is preferably used, in which case a plurality of substrates to be treated can be uniformly treated at the time of microwave treatment or heat treatment and a variation between the substrates to be treated can be reduced. For example, a dummy substrate is preferably placed over the substrate to be treated which is the closest to the high-frequency generator2803and the waveguide2804, in which case the substrate to be treated is inhibited from being directly exposed to a microwave.

With the above-described manufacturing apparatus, the quality of a film can be modified while the entry of impurities into an object suppressed.

An example of the semiconductor device that is one embodiment of the present invention will be described below with reference toFIG.20AtoFIG.20D.

FIG.20Ais a top view of the semiconductor device.FIG.20Bis a cross-sectional view corresponding to a portion taken along dashed-dotted line A1-A2inFIG.20A.FIG.20Cis a cross-sectional view corresponding to a portion taken along dashed-dotted line A3-A4inFIG.20A.FIG.20Dis a cross-sectional view corresponding to a portion taken along the dashed-dotted line A5-A6inFIG.20A. Note that for simplification, some components are not illustrated in the top view inFIG.20A.

Note that in the semiconductor device illustrated inFIGS.20A to20C, components having the same functions as the components in the semiconductor device described in <Structure example of semiconductor device> are denoted by the same reference numerals. Note that also in this section, the materials described in detail in <Structure example of semiconductor device> can be used as materials of the semiconductor device.

The semiconductor device illustrated inFIG.20AtoFIG.20Dis a variation example of the semiconductor device illustrated inFIG.1AtoFIG.1D. The semiconductor device inFIG.20AtoFIG.20Dis different from the semiconductor device inFIG.1AtoFIG.1Din that the insulator282is not included. Thus, in the semiconductor device illustrated inFIGS.20A to20D, the insulator283is in contact with the top surface of the conductor260, the top surface of the insulator280, the uppermost portions of the insulators254,250, and252.

For example, in the case where oxygen can be supplied sufficiently to the oxide230by the microwave treatment or the like as illustrated inFIGS.12A to12D, the region230bccan be substantially i-type without the insulator282for adding oxygen to the insulator280. In such a case, the structure without the insulator282as illustrated inFIGS.20A to20Denables the simplification of the manufacturing process and productivity of the semiconductor device.

The semiconductor device illustrated inFIGS.20A to20Dis different from the semiconductor device illustrated inFIGS.1A to1Din that the oxide230has a stacked structure of an oxide230aand an oxide230b. The oxide230includes the oxide230aprovided over the insulator224and the oxide230bprovided over the oxide230a.

Here, the conduction band minimum is gradually varied at a junction portion of the oxide230aand the oxide230b. In other words, the conduction band minimum at the junction portion of the oxide230aand the oxide230bis continuously varied or continuously connected. To vary the conduction band minimum gradually, the density of defect states in a mixed layer formed at the interface between the oxides230aand230bis decreased. By a reduction in the density of defect states in the mixed layer, the influence of interface scattering on carrier conduction is reduced, and the transistor200can have a high on-state current and high frequency characteristics.

For example, when the oxide230aand the oxide230bcontain the same element as a main component in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide230bis an In-M-Zn oxide, an In-M-Zn oxide, a M-Zn oxide, an oxide of the element M, an In—Zn oxide, or indium oxide may be used as the oxide230a.

The atomic ratio of In to the element M in the metal oxide used as the oxide230bis preferably higher than that in the metal oxide used as the oxide230a, for example. The oxide230aunder the oxide230binhibits diffusion of impurities into the oxide230bfrom the components formed below the oxide230a.

The oxide230apreferably has crystallinity, for example. In particular, the CAAC-OS is preferably used as the oxide230a. For example, it is preferable to use a metal oxide in which the atomic ratio of zinc to a metal element that is a main component is high. With this structure, the crystallinity of the oxide230bover the oxide230acan be further enhanced. Thus, as described above, the transistor200can exhibit stability with respect to thermal budget.

Specifically, as the oxide230a, it is preferable to use a metal oxide with an atomic ratio where Ga:Zn=2:1 or a composition in the neighborhood thereof, a metal oxide with an atomic ratio where Ga:Zn=2:5 or a composition in the neighborhood thereof, a metal oxide with an atomic ratio where In:M:Zn=1:1:2 or a composition in the neighborhood thereof, or a metal oxide with an atomic ratio where In:M:Zn=4:2:3 or a composition in the neighborhood thereof. As the oxide230b, it is preferable to use a metal oxide with an atomic ratio where In:M:Zn=2:6:5 or a composition in the neighborhood thereof, a metal oxide with an atomic ratio where In:M:Zn=1:3:4 or a composition in the neighborhood thereof, a metal oxide with an atomic ratio where In:M:Zn=1:1:1 or a composition in the neighborhood thereof, or a metal oxide with an atomic ratio where In:M:Zn=1:4:5 or a composition in the neighborhood thereof. Note that the neighborhood of the atomic ratio includes ±30% of an intended atomic ratio. Gallium is preferably used as the element M.

Note thatFIGS.20B and20Cillustrate an example in which the region230ba, the region230bb, and the region230bcare formed in the oxide230b; however, the present invention is not limited to this. For example, the above regions may be formed not only in the oxide230bbut also in the oxide230a.

In the semiconductor devices illustrated inFIGS.1A to1Dand inFIGS.20A to20D, the oxide230in the transistor200has a single-layer structure or a stacked-layer structure of two layers; however, one embodiment of the present invention is not limited to this. For example, the oxide230may have a stacked-layer structure of three or more layers, or the oxide230bmay have a stacked-layer structure.

The semiconductor device illustrated inFIGS.20A to20Dis different from that inFIGS.1A to1Din that an oxide243aand an oxide243bare included. The oxide243ais provided between the oxide230band the conductor242a, and the oxide243bis provided between the oxide230band the conductor242b. The oxide243ais preferably in contact with the top surface of the oxide230band the bottom surface of the conductor242a. The oxide243bis preferably in contact with the top surface of the oxide230band the bottom surface of the conductor242b.

The oxide243aand the oxide243bpreferably have a function of inhibiting oxygen transmission. It is preferable that the oxide243a(oxide243b) having a function of inhibiting oxygen transmission be provided between the oxide230and the conductor242a(conductor242b) functioning as the source electrode or the drain electrode, in which case the electrical resistance between the oxide230and the conductor242a(conductor242b) is reduced. Such a structure improves the electrical characteristics, field-effect mobility, and reliability of the transistor200.

A metal oxide containing the element M may be used as the oxide243aand the oxide243b. In particular, aluminum, gallium, yttrium, or tin is preferably used as the element M. The concentration of the element M in the oxides243aand243bis preferably higher than that in the oxide230b. Alternatively, gallium oxide may be used as the oxides243aand243b. A metal oxide such as an In-M-Zn oxide may be used as the oxides243aand243b. Specifically, the atomic ratio of the element M to In in the metal oxide used as the oxides243aand243bis preferably higher than that in the metal oxide used as the oxide230b. The thickness of each of the oxides243aand243bpreferably ranges from 0.5 nm to 5 nm, further preferably from 1 nm to 3 nm, and still further preferably from 1 nm to 2 nm. The oxides243aand243bpreferably have crystallinity. The oxides243aand243bwith crystallinity efficiently inhibits release of oxygen from the oxide230. When the oxides243aand243bhave a hexagonal crystal structure, for example, release of oxygen from the oxide230can sometimes be inhibited.

Application Example of Semiconductor Device

An example of the semiconductor device that is one embodiment of the present invention will be described below with reference toFIG.21AtoFIG.21C.

FIG.21Ais a top view of a semiconductor device500. InFIG.21A, the x-axis is parallel to the channel length direction of the transistor200, and the y-axis is perpendicular to the x-axis.FIG.21Bis a cross-sectional view taken along the dashed-dotted line A1-A2inFIG.21A, which corresponds to a cross-sectional view in the channel length direction of the transistor200.FIG.21Cis a cross-sectional view taken along the dashed-dotted line A3-A4inFIG.21A, which corresponds to a cross-sectional view of an opening region295and its vicinity thereof. Note that for simplification, some components are not illustrated in the top view inFIG.21A.

Note that in the semiconductor device illustrated inFIGS.21A to21C, components having the same functions as the components in the semiconductor device described in <Structure example of semiconductor device> are denoted by the same reference numerals. Note that also in this section, the materials described in detail in <Structure example of semiconductor device> can be used as materials of the semiconductor device.

The semiconductor device500illustrated inFIG.21AtoFIG.21Cis a variation example of the semiconductor device illustrated inFIG.1AtoFIG.1D. The semiconductor device500illustrated inFIGS.21A to21Cis different from the semiconductor device inFIGS.1A to1Din that a sealing portion265is formed. In addition, the opening region295is formed in the insulators282and280, which is a different point from the semiconductor device illustrated inFIGS.1A to1D. Moreover, the sealing portion265is formed to surround a plurality of transistors200, which is a different point from the semiconductor device illustrated inFIGS.1A to1D.

The semiconductor device500includes a plurality of transistors200and a plurality of opening regions295arranged in a matrix. In addition, the plurality of conductors260functioning as gate electrode of the transistors200are provided to extend in the y-axis direction. The opening regions295are provided in regions not overlapping with the oxide230or the conductor260. The sealing portion265is formed so as to surround the plurality of transistors200, the plurality of conductors260, and the plurality of opening regions295. Note that the number, the position, and the size of the transistors200, the conductors260, and the opening regions295are not limited to those illustrated inFIG.21Aand may be set as appropriate in accordance with the design of the semiconductor device500.

As illustrated inFIGS.21B and21C, the sealing portion265is provided to surround the plurality of transistors200and the insulators216,222,275,280, and282. In other words, the insulator283is provided to cover the insulators216,222,275,280, and282. In the sealing portion265, the insulator283is in contact with a top surface of the insulator214. In the sealing portion265, an insulator274is provided between the insulator283and the insulator285. The top surface of the insulator274is substantially level with the uppermost surface of the insulator283. The insulator274can be formed using the same material as that used for the insulator280.

Such a structure enables the plurality of transistors200to be surrounded by the insulators283,214, and212. One or more of the insulators283,214, and212preferably function as an insulating film having a barrier property against hydrogen. Accordingly, entry of hydrogen contained in the region outside the sealing portion265into a region in the sealing portion265can be inhibited.

As illustrated inFIG.21C, the insulator282in the opening region295has an opening. In the opening region295, the insulator280may have a groove to overlap with the opening in the insulator282. The depth of the groove of the insulator280is preferably adjusted so that the top surface of the insulator275is exposed at the deepest portion. For example, the depth of the groove may be approximately greater than or equal to ¼ and less than or equal to ½ of the maximum thickness of the insulator280.

As illustrated inFIG.21C, the insulator283in the opening region295is in contact with the side surface of the insulator282and the side and top surfaces of the insulator280. Part of the insulator274is formed in the opening region295to fill the depression portion formed in the insulator283, in some cases. At this time, the top surface of the insulator274formed in the opening region295is substantially aligned with the uppermost surface of the insulator283, in some cases.

When heat treatment is performed in such a state that the opening region295is formed and the insulator280is exposed in the opening of the insulator282, part of oxygen contained in the insulator280can be made to diffuse outwardly from the opening region295while oxygen is supplied to the oxide230. This heat treatment enables oxygen released from the insulator280to be sufficiently supplied into a region serving as a channel formation region in the oxide semiconductor layer and its vicinity and also prevents an excess amount of oxygen from being supplied thereto.

At this time, hydrogen in the insulator280can be bonded to oxygen and released to the outside through the opening region295. The hydrogen bonded to oxygen is released as water. Through the treatment, the amount of hydrogen in the insulator280can be reduced, and the hydrogen in the insulator280can be prevented from entering the oxide230.

InFIG.21A, the shape of the opening region295in the top view is substantially rectangular; however, the present invention is not limited to this structure. For example, the shape of the opening region295in the top view can be a rectangular shape, an elliptical shape, a circular shape, a rhombus shape, or a shape obtained by combining any of the above shapes. The area and arrangement interval of the opening regions295can be set as appropriate in accordance with the design of the semiconductor device including the transistor200. For example, in the region where the density of the transistors200is low, the area of the opening region295may be increased or the arrangement interval of the opening regions295may be narrowed. For example, in the region where the density of the transistors200is high, the area of the opening region295may be decreased, or the arrangement interval of the opening regions295may be increased.

Note that the insulator283may be partly in contact with the top surface of the insulator212. In this structure, the transistor200is located in a region sealed with the insulators283and212. Thus, entry of hydrogen contained in the outside of the sealed region into the sealed region can be inhibited.

Although the transistor200having a structure in which the insulators212and283each have a single-layer structure is illustrated inFIG.21AtoFIG.21C, the present invention is not limited thereto. For example, each of the insulators212and283may have a stacked-layer structure of two or more layers.

According to one embodiment of the present invention, a novel transistor can be provided. According to one embodiment of the present invention, a transistor whose characteristic degradation due to stray light is small and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a display device in which degradation in transistor characteristics due to stray light is small and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a display device with stable pixel operation can be provided.

According to one embodiment of the present invention, a semiconductor device in which a variation in transistor characteristics is small and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device with favorable electrical characteristics and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a highly reliable semiconductor device and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a miniaturized or highly integrated semiconductor device and a manufacturing method thereof can be provided. According to one embodiment of the present invention, a semiconductor device with low power consumption and a manufacturing method thereof can be provided.

At least part of the structure, method, and the like described in this embodiment can be implemented in appropriate combination with any of those in the other embodiments described in this specification.

In this embodiment, a structure example of a display device of one embodiment of the present invention will be described.

The display device in this embodiment can be a high-resolution display device. Thus, the display device in this embodiment can be used for display portions of information terminals (wearable devices) such as watch-type or bracelet-type information terminals and display portions of wearable devices capable of being worn on a head, such as a VR device such as a head mounted display and a glasses-type AR device.

FIG.22Ais a perspective view of a display module400. The display module400includes a display device410A and an FPC420. Note that the display device included in the display module400is not limited to the display device410A and may be a display device410B described later.

FIG.22Bis a perspective view schematically illustrating a structure on the substrate421side. Over the substrate421, a circuit portion432, a pixel circuit portion433over the circuit portion432, and the pixel portion434over the pixel circuit portion433are stacked. In addition, a terminal portion435for connection to the FPC420is included in a portion not overlapping with the pixel portion434over the substrate421. The terminal portion435and the circuit portion432are electrically connected to each other through a wiring portion436formed of a plurality of wirings.

The pixel portion434includes a plurality of pixels434aarranged periodically. An enlarged view of one pixel434ais illustrated on the right side inFIG.22B. The pixel434aincludes light-emitting elements440a,440b, and440cwhose emission colors are different from each other. The plurality of light-emitting elements are preferably arranged in a stripe pattern as illustrated inFIG.22B. With the stripe pattern that enables high-density arrangement of pixel circuits, a high-resolution display device can be provided. Alternatively, a variety of kinds of patterns such as a delta pattern or a pentile pattern can be employed.

The pixel circuit portion433includes a plurality of pixel circuits433aarranged periodically.

One pixel circuit433ais a circuit that controls light emission from three light-emitting elements included in one pixel434a. One pixel circuit433amay be provided with three circuits each of which controls light emission of one light-emitting element. For example, the pixel circuit433acan include at least one selection transistor, one current control transistor (driving transistor), and a capacitor for one light-emitting element. A gate signal is input to a gate of the selection transistor, and a source signal is input to one of a source and a drain of the selection transistor. With such a structure, an active-matrix display device is achieved.

The circuit portion432includes a circuit for driving the pixel circuits433ain the pixel circuit portion433. For example, one or both of a gate line driver circuit and a source line driver circuit are preferably included. In addition, at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like may be included.

The FPC420serves as a wiring for supplying a video signal or a power supply potential to the circuit portion432from the outside. An IC may be mounted on the FPC420.

The display module400can have a structure in which one or both of the pixel circuit portion433and the circuit portion432are stacked below the pixel portion434; thus, the aperture ratio (the effective display area ratio) of the display portion431can be significantly high. For example, the aperture ratio of the display portion431can be greater than or equal to 40% and less than 100%, preferably greater than or equal to 50% and less than or equal to 95%, and further preferably greater than or equal to 60% and less than or equal to 95%. Furthermore, the pixels434acan be arranged extremely densely and thus the display portion431can have greatly high resolution. For example, the pixels434aare preferably arranged in the display portion431with a resolution greater than or equal to 2000 ppi, preferably greater than or equal to 3000 ppi, further preferably greater than or equal to 5000 ppi, still further preferably greater than or equal to 6000 ppi, and less than or equal to 20000 ppi or less than or equal to 30000 ppi.

Such a display module400has extremely high resolution, and thus can be suitably used for a device for VR such as a head-mounted display or a glasses-type device for AR. For example, even in the case of a structure in which the display portion of the display module400is seen through a lens, pixels of the extremely-high-resolution display portion431included in the display module400are prevented from being seen when the display portion is enlarged by the lens, so that display providing a high sense of immersion can be performed. Without being limited thereto, the display module400can be suitably used for electronic devices including a relatively small display portion. For example, the display module400can be favorably used in a display portion of a wearable electronic device, such as a wrist watch.

A display device410A illustrated inFIG.23includes a substrate341, the light-emitting elements440a,440b, and440c, a capacitor330, and a transistor320.

The transistor320contains a metal oxide (also referred to as an oxide semiconductor) in a semiconductor layer where a channel is formed. The transistor200described in Embodiment 1 can be used as the transistor320. For the structures and the effect of the transistor320, the structure example of the transistor200illustrated inFIGS.1A to1Dand the like can be referred to.

The substrate341corresponds to the substrate421inFIGS.22A and22B. As the substrate341, an insulating substrate or a semiconductor substrate can be used.

An insulating layer361is provided over a substrate341. The insulating layer361functions as a barrier layer that prevents diffusion of impurities such as water or hydrogen from the substrate341side into the transistor320and release of oxygen from the metal oxide in the transistor320to the insulating layer361side. As the insulating layer361, for example, a film in which hydrogen or oxygen is less likely to diffuse than in a silicon oxide film can be used. Examples of such a film include an aluminum oxide film, a hafnium oxide film, and a silicon nitride film.

An insulating layer365and an insulating layer367are provided to cover the transistor320and an insulating layer363. The insulating layer363corresponds to the insulator280described in Embodiment 1.

The insulating layers363and367each function as an interlayer insulating layer. The insulating layer365functions as a barrier layer that prevents diffusion of impurities such as water or hydrogen from the insulating layer367or the like to the transistor320. As the insulating layer365, an insulating film similar to the insulating layer361can be used.

A plug362electrically connected to one of a source and a drain of the transistor320is provided to be embedded in the insulating layer367, the insulating layer365, and the insulating layer363. The plug362is formed using a single conductive layer or a stacked structure of two or more conductive layers. In the case where the plug362is formed using two conductive layers that are stacked, a conductive material through which hydrogen and oxygen are less likely to diffuse is preferably used as a conductive layer that covers a side surface of an opening in the insulating layers367,365, and363, and the like, and part of the top surface of the source or the drain of the transistor320. Such a structure can inhibit entry of impurities such as water or hydrogen from insulating layer363and the like into the metal oxide in the transistor320through the plug362. Furthermore, the structure inhibits oxygen contained in the insulating layer363from being absorbed by the plug362.

An insulating layer369is provided in contact with the side surface of the plug362. That is, the insulating layer369may be provided in contact with the inner wall of the opening in the insulating layers367,365,363, and the like, and the plug362may be provided in contact with the side surface of the insulating layer369and part of the top surface of the source or the drain of the transistor320. Note that the insulating layer369is not necessarily provided.

The transistor320can be used as a transistor included in the pixel circuit. The transistor320can also be used as transistors included in a variety of circuits such as an arithmetic circuit and a memory circuit.

The insulating layer367is provided to cover the transistor320, and the capacitor330is provided over the insulating layer367. The capacitor330and the transistor320are electrically connected to each other through the plug362.

The capacitor330includes a conductive layer331, a conductive layer335, and an insulating layer333therebetween. The conductive layer331functions as one electrode of the capacitor330, the conductive layer335functions as the other electrode of the capacitor330, and the insulating layer333functions as a dielectric of the capacitor330.

The conductive layer331is provided over the insulating layer367and is embedded in an insulating layer371. The conductive layer331is electrically connected to one of the source and the drain of the transistor320through a plug362embedded in the insulating layer367and the like. The insulating layer333is provided to cover the conductive layer331. The conductive layer335is provided in a region overlapping with the conductive layer331with the insulating layer333therebetween.

An insulating layer373is provided to cover the capacitor330, and the light-emitting elements440a,440b, and440care provided over the insulating layer373. A protective layer456is provided over the light-emitting elements440a,440b, and440c, and a substrate460is bonded to a top surface of the protective layer456with a resin layer459. An insulator is provided in a region between adjacent light-emitting elements. InFIG.23, an insulating layer125and an insulating layer127over the insulating layer125are provided in the region. The substrate460corresponds to the substrate422inFIGS.22A and22B.

The embodiment shows an example of a top-emission display device in which light is emitted to the side opposite to the substrate where the light-emitting device is formed. Note that the display device may have a bottom-emission structure in which light is emitted to the substrate side where the light-emitting device is formed or a dual-emission structure in which light is emitted to the both sides.

The light-emitting elements440a,440b, and440care preferably organic electroluminescence elements (organic EL elements). For example, the light-emitting element440aemits red light (R), the light-emitting element440bemits green light (G), and the light-emitting element440cemits blue light (B). The display device410A includes three kinds of light-emitting elements emitting red (R), green (G), and blue (B) colors, thereby achieving full-color display. Note thatFIG.23illustrates an example in which the display device410A includes light-emitting elements of three colors; however, the present invention is not limited thereto, and the display device may include light-emitting element(s) of a single color, two colors or four or more colors.

The light-emitting element includes an EL layer between a pair of electrodes. In this specification and the like, one of the pair of electrodes is referred to as a pixel electrode, and the other electrode is referred to as a common electrode in some cases. One of the pair of electrodes in the light-emitting device serves as an anode, and the other electrode serves as a cathode. Hereinafter, the case where the pixel electrode serves as an anode and the common electrode serves as a cathode is described as an example.

The light-emitting element440aincludes a pixel electrode111aover the insulating layer373, a first layer113ain an island shape over the pixel electrode111a, a fourth layer114over the first layer113ain an island shape, and a common electrode115over the fourth layer114. In the light-emitting element440a, the first layer113aand the fourth layer114can be collectively referred to as an EL layer.

The light-emitting element440bincludes a pixel electrode111b, a second layer113b, a fourth layer114, and the common electrode115. The light-emitting element440cincludes the pixel electrode111c, a third layer113c, the fourth layer114, and the common electrode115.

In the cross-sectional observation, a region where the side surface of the lower electrode (pixel electrode) and the side surface of the light-emitting layer are aligned or substantially aligned is included. In the top view, the top-surface shape of the lower electrode can be regarded as being aligned or substantially aligned with the top-surface shape of the light-emitting layer.

Note that in this specification and the like, the expression “side surfaces are substantially aligned with each other” or “the top-surface shapes are substantially aligned with each other” means that at least part of outlines overlap with each other between the upper layer and the lower layer in the top view. For example, the case of patterning or partly patterning the upper layer and the lower layer with use of the same mask pattern is included in the expression. The expression “the side surfaces are substantially aligned with each other” or “the top-surface shapes are substantially aligned with each other” also includes the case where the outlines do not completely overlap with each other; for instance, the edge of the upper layer may be positioned on the inner side or the outer side of the edge of the lower layer.

The same film is shared by the light-emitting elements of three colors as the common electrode. The common electrode115shared by the light-emitting elements is electrically connected to a wiring provided below the plug372through the plug372(not illustrated). Thus, the same potential is supplied to the common electrodes of the light-emitting elements of three colors.

The pixel electrode of the light-emitting element is electrically connected to one of the source and the drain of the transistor320through the plug372embedded in the insulating layer373, the conductive layer331embedded in the insulating layer371, and the plug362embedded in the insulating layer367, and the like. The tops surface of the insulating layer373and the top surface of the plug372are level or substantially level with each other. Any of a variety of conductive materials can be used for the plug.

Note that the details the light-emitting element will be described in Embodiment 3.

As a way of forming EL layers separately between light-emitting elements of different colors, an evaporation method using a shadow mask such as a metal mask is known. However, this method causes a deviation from the designed shape and position of an island-shaped organic film due to various influences such as the low accuracy of the metal mask position, the positional deviation between the metal mask and a substrate, a warp of the metal mask, and the vapor-scattering-induced expansion of outline of the deposited film, accordingly, it is difficult to achieve high resolution and high aperture ratio of the display device. Thus, a measure has been taken for pseudo improvement in resolution (also referred to pixel density). As a specific measure, a unique pixel arrangement such as a PenTile pattern has been employed.

For example, fine patterning of an EL layer is performed without a shadow mask such as a metal mask. With the patterning, a high-resolution display device with a high aperture ratio, which had been difficult to achieve, can be fabricated. Moreover, EL layers can be formed separately, which enables extremely clear images; thus, a display device with a high contrast and high display quality can be fabricated.

Here, a description is made on a case where EL layers in light-emitting elements of two colors are separately formed, for simplicity. First, a stack of a first EL film and a first sacrificial film is formed to cover two pixel electrodes. Next, a resist mask is formed over the first sacrifice film and in a position overlapping with the one pixel electrode (a first pixel electrode). Then, the resist mask, the part of the first sacrificial film, and part of the first EL film are etched. At this time, the etching is stopped when the other pixel electrodes (a second pixel electrode) are exposed. Thus, part of the first EL film processed into a belt-like or island shape (also referred to as a first EL layer) can be formed over the first pixel electrode, and part of the sacrificial film (also referred to as a first sacrificial layer) can be formed thereover. Note that the sacrificial film may be called a mask film.

Next, a stack of a second EL film and a second sacrificial film is formed. Then, resist masks are formed in a position overlapping with the first pixel electrode and in a position overlapping with the second pixel electrode. Then, the resist masks, part of the second sacrificial film, and part of the second EL film are partly etched in a manner similar to the above. As a result, the first EL layer and the first sacrificial layer are provided over the first pixel electrode, and a second EL layer and a second sacrificial layer are provided over the second pixel electrode. In this manner, the first EL layer and the second EL layer can be formed separately. Finally, the first and second sacrificial layers are removed to expose the first and second EL layers, and then the common electrode is formed, so that the light-emitting elements of two colors can be formed separately. Note that the sacrificial layer may be called a mask layer.

Furthermore, by repeating the above-described steps, EL layers in light-emitting elements of three or more colors can be separately formed. Accordingly, a display device including light-emitting elements of three or more colors can be achieved.

Note that an electrode (also referred to as a first electrode, a connection electrode, or the like), which is to supply a potential to the common electrode, can be formed on the same plane as the pixel electrode to be electrically connected to the common electrode. The connection electrode is located outside the display portion including the pixels. In order to prevent a top surface of the connection electrode from being exposed in etching of the first EL film, it is preferable that the first sacrificial layer be also provided over the connection electrode. Also in etching of the second EL film, the second sacrificial layer is preferably provided over the connection electrode. The first and sacrificial layers provided over the connection electrode can be removed by etching concurrently with the first and second sacrificial layers over the first and second EL layers.

In the case where EL layers for different colors are adjacent to each other, it is difficult to set the distance between the EL layers adjacent to each other to be less than 10 μm with a formation method using a metal mask, for example. In contrast, with use of the above method, the distance can be decreased to be less than or equal to 3 μm, less than or equal to 2 μm, or less than or equal to 1 μm. For example, with use of an exposure tool for LSI, the distance can be decreased to be less than or equal to 500 nm, less than or equal to 200 nm, less than or equal to 100 nm, or less than or equal to 50 nm. Accordingly, the area of a non-light-emitting region exiting between two light-emitting elements can be significantly reduced, and the aperture ratio can be close to 100%. For example, the aperture ratio may be higher than or equal to 50%, higher than or equal to 60%, higher than or equal to 70%, higher than or equal to 80%, or higher than or equal to 90%; that is, the aperture ratio lower than 100% can be achieved.

Furthermore, a pattern of the EL layer itself can be made extremely smaller than that in the case of using a metal mask. For example, in the case of using a metal mask for forming EL layers separately, a variation in the thickness of the pattern occurs between the center and the edge of the pattern. This causes a reduction in an effective area that can be used as a light-emitting region with respect to the whole pattern area. In contrast, in the manufacturing method, a pattern is formed by processing a film deposited to have a uniform thickness, which enables a uniform thickness in the pattern. Thus, even in the fine pattern, almost the whole area can be used as a light-emitting region. Therefore, the above method makes it possible to obtain a high resolution display device with a high aperture ratio.

As described above, with the above manufacturing method, a display device in which minute light-emitting elements are integrated can be achieved, and it is not necessary to conduct a pseudo improvement in resolution with a unique pixel arrangement such as a PenTile pattern. Thus, with what is called a stripe pattern where R, G, and B are arranged in one direction, a high-resolution display device, greater than or equal to 500 ppi, greater than or equal to 1000 ppi, greater than or equal to 2000 ppi, greater than or equal to 3000 ppi, or greater than or equal to 5000 ppi, can be achieved.

Side surfaces of the pixel electrodes111a,111b, and111c, the first layer113a, the second layer113b, and the third layer113care covered with the insulating layer125and the insulating layer127. A fourth layer114is provided over the first layer113a, the second layer113b, the third layer113c, the insulating layer125, and the insulating layer127, and the common electrode115is provided over the fourth layer114.

With the above structure, the fourth layer114(or the common electrode115) can be prevented from being in contact with any of the side surfaces of the pixel electrodes111a,111b, and111c, the first layer113a, the second layer113b, and the third layer113c, so that the light-emitting elements can be prevented from being short-circuited.

The insulating layer125preferably covers at least the side surfaces of the pixel electrodes111a,111b, and111c. Furthermore, the insulating layer125preferably covers the side surfaces of the first layer113a, the second layer113b, and the third layer113c. The insulating layer125can be in contact with side surfaces of the pixel electrodes111a,111b, and111c, the first layer113a, the second layer113b, and the third layer113c.

The insulating layer127is provided over the insulating layer125to fill a depressed portion formed in the insulating layer125. The insulating layer127can overlap with the side surfaces of the pixel electrodes111a,111b, and111c, the first layer113a, the second layer113b, and the third layer113cwith the insulating layer125provided therebetween.

Note that either the insulating layer125or the insulating layer127is not necessarily provided. In the case where the insulating layer125is not provided, the insulating layer127can be in contact with side surfaces of the first layer113a, the second layer113b, and the third layer113c. In addition, the display device may include an insulating layer covering an end portion of the pixel electrode. In this case, one or both of the insulating layer125and the insulating layer127may be provided over the insulating layer.

The fourth layer114and the common electrode115are provided over the first layer113a, the second layer113b, the third layer113c, the insulating layer125, and the insulating layer127. Before the insulating layer125and the insulating layer127are provided, a step is generated due to a difference between a region where the pixel electrode and the EL layer are provided and a region where neither the pixel electrode nor the EL layer is provided (region between the light-emitting elements). In the display device of one embodiment of the present invention, the step can be planarized with the insulating layer125and the insulating layer127, and the coverage with the fourth layer114and the common electrode115can be improved. Thus, connection defects caused by disconnection can be inhibited. Alternatively, an increase in electrical resistance, which is caused by a reduction in thickness locally of the common electrode115due to the step, can be prevented.

To improve the planarity of a surface over which the fourth layer114and the common electrode115are formed, the levels of the top surfaces of the insulating layers125and127are preferably aligned or substantially aligned with at least one of levels of the top surfaces of the first layer113a, the second layer113b, and the third layer113c. Although the top surface of the insulating layer127preferably has a flat surface, a projection or depression portion may be provided.

The insulating layer125includes regions in contact with the side surfaces of the first layer113a, the second layer113b, and the third layer113c, and functions as a protective insulating layer of the first layer113a, the second layer113b, and the third layer113c. With the insulating layer125, entry of impurities such as oxygen or moisture from the side surfaces of the first, second, and third layers113a,113b, and113cinto their insides can be prevented, and thus a highly reliable display device can be obtained.

When the widths (thicknesses) of the insulating layer125in the regions in contact with the side surfaces of the first, second, and third layers113a,113b, and113care large in the cross-sectional view, the distance between the first, second, and third layers113a,113b, and113cis large, which results in a reduction in aperture ratio in some cases. When the widths (thicknesses) of the insulating layer125in the regions in contact with the side surfaces of the first, second, and third layers113a,113b, and113care small in the cross-sectional view, the effect of preventing the entry of the impurities from the side surfaces of the first, second, and third layers113a,113b, and113cinto their insides is lowered in some cases. In the cross-sectional view, the widths (thicknesses) of the insulating layer125in the regions in contact with the side surfaces of the first, second, and third layers113a,113b, and113care preferably greater than or equal to 3 nm and less than or equal to 200 nm, further preferably greater than or equal to 3 nm and less than or equal to 150 nm, still further preferably greater than or equal to 5 nm and less than or equal to 150 nm, still further preferably greater than or equal to 5 nm and less than or equal to 100 nm, still further preferably greater than or equal to 10 nm and less than or equal to 100 nm, yet still further preferably greater than or equal to 10 nm and less than or equal to 50 nm. When the width (thickness) of the insulating layer125is within the above range, a highly reliable display device with high aperture ratio can be obtained.

The insulating layer125can be formed using an inorganic material. For the insulating layer125, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used, for example. The insulating layer125may have a single-layer structure or a stacked-layer structure. Examples of the oxide insulating film include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium-gallium-zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of the nitride insulating film include a silicon nitride film and an aluminum nitride film. Examples of the nitride insulating film include a silicon oxynitride film and an aluminum oxynitride film. Examples of the nitride oxide insulating film include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, aluminum oxide is preferably used because it has high selectivity with respect to the EL layer in etching and has a function of protecting the EL layer when the insulating layer127is formed in a later step. An inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film is formed by an ALD method as the insulating layer125, whereby the insulating layer125can have few pinholes and an excellent function of protecting the EL layer.

Note that in this specification and the like, oxynitride refers to a material that contains more oxygen than nitrogen, and nitride oxide refers to a material that contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material which contains oxygen at a higher proportion than nitrogen, and silicon nitride oxide refers to a material which contains nitrogen at a higher proportion than oxygen.

The insulating layer125can be deposited by a sputtering method, a CVD method, a PLD method, an ALD method, or the like. The insulating layer125is preferably formed by an ALD method achieving good coverage.

The insulating layer127over the insulating layer125has a function of reducing the depression portion in the insulating layer125formed between adjacent light-emitting devices. In other words, the insulating layer127brings an effect of improving the planarity of a surface where the common electrode115is formed. As the insulating layer127, an insulating layer containing an organic material can be favorably used. Examples of materials used for the insulating layer127include an acrylic resin, a polyimide resin, an epoxy resin, an imide resin, a polyamide resin, a polyimide-amide resin, a silicone resin, a siloxane resin, a benzocyclobutene-based resin, a phenol resin, and precursors of these resins. Examples of an organic materials used for the insulating layer127include polyvinyl alcohol (PVA), polyvinylbutyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, and an alcohol-soluble polyamide resin. Alternatively, a photosensitive resin (also referred to as an organic resin) can be used as the insulating layer127. A photoresist may be used for the photosensitive resin. As the photosensitive resin, a positive photosensitive material or a negative photosensitive material can be used.

The level difference between the top surface of the insulating layer127and the top surface of any of the first, second, or third layer113a,113b, or113cis, preferably, for example, less than or equal to 0.5 times the thickness of the insulating layer127, further preferably less than or equal to 0.3 times the thickness of the insulating layer127. The insulating layer127may be provided so that the level of the top surface of any of the first, second, or third layer113a,113b, or113cis higher than the level of the top surface of the insulating layer127, for example. Further alternatively, the insulating layer127may be provided so that the level of the top surface of insulating layer127is higher than the level of the top surface of the light-emitting layer included in the first, second, or third layer113a,113b, or113c.

A display device410B illustrated inFIG.24is different from the display device410A mainly in a structure of the transistor. Note that portions similar to those in the display device410A are not be described in some cases.

A substrate301corresponds to the substrate421illustrated inFIGS.22A and22B.

The transistor310includes a channel formation region in the substrate301. As the substrate301, a semiconductor substrate such as a single crystal silicon substrate can be used, for example. The transistor310includes part of the substrate301, a conductive layer311, a pair of low-resistance regions312, an insulating layer313, and an insulating layer314. The conductive layer311functions as a gate electrode. The insulating layer313is positioned between the substrate301and the conductive layer311and functions as a gate insulating layer. The pair of low-resistance regions312are regions where the substrate301is doped with an impurity, and function as a source and a drain. The insulating layer314is provided so as to cover a side surface of the conductive layer311and functions as an insulating layer.

An element isolation layer315is provided between two adjacent transistors310to be embedded in the substrate301.

An insulating layer351is provided to cover the transistor310, and a conductive layer354is provided over the insulating layer351. The conductive layer354is electrically connected to one of the source and the drain of the transistor310through a plug352embedded in the insulating layer351. An insulating layer353is provided to cover the conductive layer354, and a conductive layer356is provided over the insulating layer353. The conductive layer354and the conductive layer356each function as a wiring. An insulating layer355and the insulating layer361are provided to cover the conductive layer356, and the transistor320is provided over the insulating layer361.

The transistor310can be used as a transistor included in the pixel circuit or a transistor included in a driver circuit (one or both of a gate driver and a source driver) for driving the pixel circuit. The transistor310can also be used as transistors included in a variety of circuits such as an arithmetic circuit and a memory circuit.

With such a structure, not only the pixel circuit but also the driver circuit or the like can be formed directly under the light-emitting element; thus, the display device can be downsized as compared with the case where the driver circuit is provided around a display portion.

Example of Structure of Pixel Circuit

A structural example of a pixel circuit applicable to the display device of one embodiment of the present invention is described below.

A pixel circuit PIX1illustrated inFIG.25Aincludes a transistor M1, a transistor M2, a capacitor C1, and a light-emitting element EL. Wirings SL, GL, AL, and CL are electrically connected to the pixel circuit PIX1.

A gate of the transistor M1is electrically connected to the wiring GL, one of a source and a drain of the transistor M1is electrically connected to the wiring SL, and the other of the source and the drain of the transistor M1is electrically connected to a gate of the transistor M2and one electrode of the capacitor C1. One of a source and a drain of the transistor M2is electrically connected to the wiring AL and the other of the source and the drain of the transistor M2is electrically connected to an anode of the light-emitting element EL. The other electrode of the capacitor C1is electrically connected to the anode of the light-emitting element EL. A cathode of the light-emitting element EL is electrically connected to the wiring CL.

The transistor M1can be referred to as a selection transistor and functions as a switch for controlling selection/non-selection of the pixel. The transistor M2can be referred to as a driver transistor and has a function of controlling a current flowing to the light-emitting element EL. The capacitor C1functions as a storage capacitor and has a function of retaining a gate potential of the transistor M2. A capacitor such as a MIM capacitor may be used as the capacitor C1; alternatively, capacitance between wirings, a gate capacitance of the transistor, or the like may be used as the capacitor C1.

The wiring SL is supplied with a source signal. The wiring GL is supplied with a gate signal. The wirings AL and CL are each supplied with a constant potential. In the light-emitting element EL, the anode side can have a high potential and the cathode side can have a lower potential than the anode side.

A pixel circuit PIX2illustrated inFIG.25Bhas a structure in which a transistor M3is added to the pixel circuit PIX1. In addition, a wiring V0is electrically connected to the pixel circuit PIX2.

A gate of the transistor M3is electrically connected to the wiring GL, one of a source and a drain of the transistor M3is electrically connected to the anode of the light-emitting element EL, and the other of the source and the drain of the transistor M3is electrically connected to the wiring V0.

The wiring V0is supplied with a constant potential when data is written to the pixel circuit PIX2. Thus, a variation in the gate-source voltage of the transistor M2can be inhibited.

A pixel circuit PIX3illustrated inFIG.25Cis an example in the case where a transistor in which a pair of gates are electrically connected to each other is used as each of the transistors M1and M2of the pixel circuit PIX1. A pixel circuit PIX4illustrated inFIG.25Dis an example in the case where such transistors are used in the pixel circuit PIX2. With these structures, a current that can flow through the transistors can be increased. Although the transistor in which the pair of gates are connected to each other is used as every transistor here, one embodiment of the present invention is not limited thereto. A transistor that includes a pair of gates electrically connected to different wirings may be used. When, for example, a transistor in which one of the gates is electrically connected to the source is used, the reliability can be increased.

A pixel circuit PIX5illustrated inFIG.26Ahas a structure in which a transistor M4is added to the pixel circuit PIX2. Three wirings (wirings GL1, GL2, and GL3) functioning as gate lines are electrically connected to the pixel circuit PIX5.

A gate of the transistor M4is electrically connected to the wiring GL3, one of a source and a drain of the transistor M4is electrically connected to the gate of the transistor M2, and the other of the source and the drain of the transistor M4is electrically connected to the wiring V0. The gate of the transistor M1is electrically connected to the wiring GL1, and the gate of the transistor M3is electrically connected to the wiring GL2.

When the transistors M3and M4are turned on at the same time, the source and the gate of the transistor M2have the same potential, so that the transistor M2can be turned off. Thus, a current flowing to the light-emitting element EL can be blocked forcibly. Such a pixel circuit is suitable for the case of using a display method in which a display period and an off period are alternately provided.

A pixel circuit PIX6illustrated inFIG.26Bis an example in the case where a capacitor C2is added to the pixel circuit PIX5. One electrode of the capacitor C2is electrically connected to the gate of the transistor M2, and the other electrode is electrically connected to the wiring AL. The capacitor C2functions as a storage capacitor.

A pixel circuit PIX7illustrated inFIG.26Cis an example in the case where transistors including a pair of gates are employed in the pixel circuit PIX5. A pixel circuit PIX8illustrated inFIG.26Dis an example in the case where transistors including a pair of gates are employed in the pixel circuit PIX6. A transistor in which a pair of gates are electrically connected to each other is used as each of the transistors M1, M3, and M4, and a transistor in which one of gates is electrically connected to a source is used as the transistor M2.

Each transistor M1illustrated inFIGS.25A to25DandFIGS.26A to26Dneed to maintain charges accumulated in the capacitor C1and/or the capacitor C2for a long time. In other words, the transistor M1is required to have normally-off characteristics. Vshdegradation tolerance amount of the transistor M1, with which the pixel operation is normally performed, is described below.

Here, the Vshdegradation tolerance amount of the transistor M1in of the pixel circuit PIX8illustrated inFIG.26Dis calculated.

First, a calculation method of Ioffof the transistor M1, which is crucial to maintain charges accumulated in the capacitors C1and C2, is described.

The basic formula of a capacitor is shown below as Formula (1)
[Formula 7]
Q=CV=Ioff×t(1)

In Formula (1), Q represents charges retained in the capacitors C1and C2, C represents combined capacitance of the capacitors C1and C2, V represents a variation in voltage, and t represents a retention time. Here, assuming that Ioffhas no time dependence, Formula (1) can be regarded as Formula (2).

Note that assuming that the variation V in voltage is equivalent to the full grayscale range GR of the source line, V is calculated from Formula (3).

In Formula (3), Vgs1represents a gate-source voltage under the condition of full-white display, and Vgs2represents a gate-source voltage under the condition of full-black display. Using Formula (2) and the variation V calculated from Formula (3), Ioffof the transistor M1, which is crucial to maintain charges accumulated in the capacitor C1, can be calculated.

Next, a calculation method of Vshcrucial to the transistor M1under the full-black display condition is described. Hereinafter, Vshcrucial to the transistor M1under the full-black display condition is denoted by Vsh1.

The transistor M1under the full-black display condition is regarded as in the subthreshold region. At this time, the subthreshold leakage is presumably a domination term of Ioff. The subthreshold leakage is calculated by Formula (4).

In Formula (4), Vsh1represents a gate-source voltage Vgswhen the drain current Idis 1 pA, Vddrepresents a gate-source voltage Vgs2under the full-black display condition, and SS represents a subthreshold slope. Note that Formula (4) can be replaced with Formula (5).
[Formula 11]
Vsh1=Vdd−SS×{log10(Ioff)+12}  (5)

Table 4 shows an example of specifications of the pixel circuit PIX8.

By the calculation using the specifications of the pixel circuit PIX8shown in Table 4 and Formula (3), the variation in voltage V is found to be 0.0127 V. In addition, off of the transistor M1, which is crucial to maintain charges accumulated in the capacitors C1and C2, is found to be 1.17×10−13A from the calculation with use of the calculated variation in V and Formula (2). On the basis of the calculated Ioffof the transistor M1, which is crucial to maintain charges accumulated in the capacitors C1and C2, and Formula (5), Vsh1is estimated to be −0.407 V.

The full-black display condition is the minimum requirements to maintain charges accumulated in the capacitors C1and C2. When Vshof the transistor M1is higher than or equal to Vsh1, normal pixel operation is presumably performed in the pixel circuit PIX8. Thus, Vshof the transistor M1is preferably higher than or equal to −0.4 V.

Note that Vsh1depends on the subthreshold slope SS. The subthreshold slope SS increases, in some cases, depending on the temperature condition in the NBTIS test, the thickness of the gate insulator, or the like. When the subthreshold slope SS is 200 mV/dec., Vsh1is estimated to be −0.313 V. Therefore, Vshof the transistor M1is further preferably higher than or equal to −0.3 V.

As described above, a transistor whose Vshis higher than or equal to −0.4 V, preferably higher than or equal to −0.3 V is used as the transistor M1, whereby the pixel operation in the pixel circuit can be normally performed. Thus, a display device in which degradation in transistor characteristics due to stray is small can be provided. Furthermore, a display device with stable pixel operation can be provided.

Note that the transistor200described in Embodiment 1 can be used as the transistor M1included in the pixel circuit PIX8illustrated inFIG.26D. In other words, it can be said that the pixel operation in the pixel circuit is normally performed when Vshof the transistor200described in Embodiment 1 is higher than or equal to −0.4 V, preferably higher than or equal to −0.3 V. Thus, Vshof the transistor200described in Embodiment 1 is preferably higher than or equal to −0.4 V, further preferably higher than or equal to −0.3 V, in some cases.

At least part of any of the structure examples, the drawings corresponding thereto, and the like described in this embodiment can be implemented in combination with any of the other structure examples, the other drawings corresponding thereto, and the like as appropriate.

In this embodiment, a light-emitting element (also referred to as light-emitting device) that can be used in the display device of one embodiment of the present invention will be described.

Structure Example of Light-Emitting Element

As illustrated inFIG.27A, the light-emitting element includes an EL layer23between a pair of electrodes (a lower electrode21and an upper electrode25). The EL layer23can be formed of a plurality of layers such as a layer4420, a light-emitting layer4411, and a layer4430. The layer4420can include, for example, a layer containing a substance with a high electron-injection property (an electron-injection layer) and a layer containing a substance with a high electron-transport property (an electron-transport layer). The light-emitting layer4411contains a light-emitting compound, for example. The layer4430can include, for example, a layer containing a substance with a high hole-injection property (a hole-injection layer) and a layer containing a substance with a high hole-transport property (a hole-transport layer).

The structure including the layer4420, the light-emitting layer4411, and the layer4430, which is provided between a pair of electrodes, can function as a single light-emitting unit, and the structure inFIG.27Ais referred to as a single structure in this specification.

FIG.27Bis a modification example of the EL layer23included in the light-emitting element20illustrated inFIG.27A. Specifically, the light-emitting element20illustrated inFIG.27Bincludes a layer4430-1over the lower electrode21, a layer4430-2over the layer4430-1, the light-emitting layer4411over the layer4430-2, a layer4420-1over the light-emitting layer4411, a layer4420-2over the layer4420-1, and the upper electrode25over the layer4420-2. For example, when the lower electrode21functions as an anode and the upper electrode25functions as a cathode, the layer4430-1functions as a hole-injection layer, the layer4430-2functions as a hole-transport layer, the layer4420-1functions as an electron-transport layer, and the layer4420-2functions as an electron-injection layer. Alternatively, when the lower electrode21functions as a cathode and the upper electrode25functions as an anode, the layer4430-1functions as an electron-injection layer, the layer4430-2functions as an electron-transport layer, the layer4420-1functions as a hole-transport layer, and the layer4420-2functions as the hole-injection layer. With such a layered structure, carriers can be efficiently injected to the light-emitting layer4411, and the efficiency of the recombination of carriers in the light-emitting layer4411can be enhanced.

The structure in which a plurality of light-emitting layers (light-emitting layers4411,4412, and4413) is provided between the layer4420and the layer4430as illustrated inFIG.27Cis another variation of the single structure.

The structure in which a plurality of light-emitting units (EL layers23aand23b) is connected in series with an intermediate layer4440therebetween as illustrated inFIG.27Dis referred to as a tandem structure in this specification. The intermediate layer4440is sometimes referred to as a charge-generation layer. In this specification and the like, the structure illustrated inFIG.27Dis referred to as a tandem structure; however, without being limited to this, a tandem structure may be referred to as a stack structure, for example. The tandem structure enables a light-emitting device capable of high luminance light emission.

Also in the structures illustrated inFIGS.27C and27D, the layers4420and4430may each have a stacked-layer structure of two or more layers as illustrated inFIG.27B.

The emission color of the light-emitting element can be changed to red, green, blue, cyan, magenta, yellow, white, or the like depending on the material of the EL layer23. When the light-emitting elements have a microcavity structure, the color purity can be further increased.

A light-emitting layer preferably contains two or more selected from light-emitting substances that emit light of red (R), green (G), blue (B), yellow (Y), orange (O), and the like. Alternatively, the light-emitting layer preferably contains two or more light-emitting substances that emit light containing two or more of spectral components of R, G, and B.

Here, a specific structure example of a light-emitting element will be described.

The light-emitting element includes at least a light-emitting layer. In addition to the light-emitting layer, the light-emitting element may further include a layer containing any of a substance with a high hole-injection property, a substance with a high hole-transport property, a hole-blocking material, a substance with a high electron-transport property, an electron-blocking material, a substance with a high electron-injection property, a substance with a bipolar property (a substance with a high electron- and hole-transport property), and the like.

For the light-emitting element, either a low-molecular compound or a high-molecular compound can be used, and an inorganic compound may also be used. Each of the layers included in the light-emitting element can be formed by any of the following methods: an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, a coating method, and the like.

For example, the light-emitting element can include one or more of the hole-injection layer, the hole-transport layer, the hole-blocking layer, an electron-blocking layer, an electron-transport layer, and an electron-injection layer.

The hole-injection layer injects holes from an anode to the hole-transport layer and contains a material with a high hole-injection property. As the material with a high hole-injection property, an aromatic amine compound, a composite material containing a hole-transport material and an acceptor material (electron-accepting material), or the like can be used.

The hole-transport layer transports holes injected from the anode by the hole-injection layer, to the light-emitting layer. The hole-transport layer contains a hole-transport material. The hole-transport material preferably has a hole mobility of 1×10−6cm2/Vs or higher. Note that other substances can also be used as long as the substances have a hole-transport property higher than an electron-transport property. As the hole-transport material, materials having a high hole-transport property, such as a π-electron rich heteroaromatic compound (e.g., a carbazole derivative, a thiophene derivative, and a furan derivative) and an aromatic amine (a compound having an aromatic amine skeleton), are preferred.

The electron-transport layer transports electrons injected from the cathode by the electron-injection layer, to the light-emitting layer. The electron-transport layer contains an electron-transport material. The electron-transport material preferably has an electron mobility of 1×10−6cm2/Vs or higher. Note that other substances can also be used as long as the substances have an electron-transport property higher than a hole-transport property. As the electron-transport material, any of the following materials having a high electron-transport property can be used, for example: a metal complex having a quinoline skeleton, a metal complex having a benzoquinoline skeleton, a metal complex having an oxazole skeleton, a metal complex having a thiazole skeleton, an oxadiazole derivative, a triazole derivative, an imidazole derivative, an oxazole derivative, a thiazole derivative, a phenanthroline derivative, a quinoline derivative having a quinoline ligand, a benzoquinoline derivative, a quinoxaline derivative, a dibenzoquinoxaline derivative, a pyridine derivative, a bipyridine derivative, a pyrimidine derivative, and a n-electron deficient heteroaromatic compound such as a nitrogen-containing heteroaromatic compound.

The electron-injection layer injects electrons from the cathode to the electron-transport layer and contains a material with a high electron-injection property. As the material with a high electron-injection property, an alkali metal, an alkaline earth metal, or a compound thereof can be used. As the material with a high electron-injection property, a composite material containing an electron-transport material and a donor material (electron-donating material) can also be used.

Alternatively, an electron-transport material may be used for the electron-injection layer. For example, a compound having an unshared electron pair and an electron deficient heteroaromatic ring can be used as the electron-transport material. Specifically, a compound with at least one of a pyridine ring, a diazine ring (a pyrimidine ring, a pyrazine ring, and a pyridazine ring), and a triazine ring can be used.

Note that the lowest unoccupied molecular orbital (LUMO) of the organic compound including an unshared electron pair is preferably greater than or equal to −3.6 eV and less than or equal to −2.3 eV. In general, the highest occupied molecular orbital (HOMO) level and the LUMO level of the organic compound can be estimated by cyclic voltammetry (CV), photoelectron spectroscopy, optical absorption spectroscopy, inverse photoelectron spectroscopy, or the like.

The light-emitting layer contains a light-emitting substance. The light-emitting layer can contain one or more kinds of light-emitting substances. As the light-emitting substance, a substance whose emission color is blue, violet, bluish violet, green, yellowish green, yellow, orange, red, or the like is appropriately used. Alternatively, as the light-emitting substance, a substance that emits near-infrared light can be used.

Examples of the light-emitting substance include a fluorescent material, a phosphorescent material, a TADF material, and a quantum dot material.

Examples of the fluorescent material include a pyrene derivative, an anthracene derivative, a triphenylene derivative, a fluorene derivative, a carbazole derivative, a dibenzothiophene derivative, a dibenzofuran derivative, a dibenzoquinoxaline derivative, a quinoxaline derivative, a pyridine derivative, a pyrimidine derivative, a phenanthrene derivative, and a naphthalene derivative.

Examples of the phosphorescent material include an organometallic complex (particularly an iridium complex) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton, or a pyridine skeleton; an organometallic complex (particularly an iridium complex) having a phenylpyridine derivative including an electron-withdrawing group as a ligand; a platinum complex; and a rare earth metal complex.

The light-emitting layer may contain one or more kinds of organic compounds (e.g., a host material or an assist material) in addition to the light-emitting substance (guest material). As one kind or two or more kinds of organic compounds, one or both of the hole-transport material and the electron-transport material can be used. Alternatively, as one kind or two or kinds of organic compounds, a bipolar material or a TADF material may be used.

The light-emitting layer preferably includes a combination of a hole-transport material and an electron-transport material that easily forms an exciplex and a phosphorescent material, for example. With such a structure, light emission can be efficiently obtained by exciplex-triplet energy transfer (ExTET), which is energy transfer from an exciplex to a light-emitting substance (phosphorescent material). When a combination of materials is selected so as to form an exciplex that exhibits light emission whose wavelength overlaps with the wavelength of a lowest-energy-side absorption band of the light-emitting substance, energy can be transferred smoothly and light emission can be obtained efficiently. With the above structure, high efficiency, low-voltage driving, and a long lifetime of a light-emitting device can be achieved at the same time.

A conductive film that can be used for the anode and the cathode and transmits visible light can be formed using, for example, indium oxide, indium tin oxide, indium tin oxide containing silicon oxide (ITSO), indium zinc oxide, zinc oxide, or zinc oxide to which gallium is added. Alternatively, a film of a metal material such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, or titanium; an alloy containing any of these metal materials; or a nitride of any of these metal materials (e.g., titanium nitride) can be formed thin so as to have a light-transmitting property. Alternatively, a stacked film of any of the above materials can be used for the conductive layers. For example, a stacked film of an alloy of silver and magnesium and indium tin oxide or indium tin oxide containing silicon is preferably used because the conductivity can be increased. Still alternatively, graphene or the like may be used.

The cathode or the anode is preferably formed using a conductive film that reflects visible light. For the conductive film, for example, a metal material such as aluminum, gold, platinum, silver, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, or palladium, or an alloy containing any of these metal materials can be used. Silver is preferably used because of high resistivity of visible light. In addition, aluminum is preferably used because an electrode using aluminum is easily etched, processing of the electrode is easy, and the aluminum electrode has high resistivity of visible light and near-infrared light. Furthermore, lanthanum, neodymium, germanium, or the like may be added to the metal material or the alloy. Alternatively, an alloy containing aluminum (an aluminum alloy) such as an alloy of aluminum and titanium, an alloy of aluminum and nickel, or an alloy of aluminum and neodymium may be used. Alternatively, an alloy containing silver such as an alloy of silver and copper, an alloy of silver and palladium, or an alloy of silver and magnesium may be used. An alloy containing silver and copper is preferable because of its high heat resistance.

The cathode or the anode may have a structure in which a conductive metal film or a metal oxide film is stacked over the conductive film reflecting visible light. Such a structure can avoid the conductive film reflecting visible light from being oxidized or corroded. For example, when a metal film or a metal oxide film is stacked in contact with an aluminum film or an aluminum alloy film, oxidation can be suppressed. Examples of a material for the metal film or the metal oxide film include titanium or titanium oxide. Alternatively, the above conductive film that transmits visible light and a film containing a metal material may be stacked. For example, a stack of silver and indium tin oxide, a stack of an alloy of silver and magnesium and indium tin oxide, or the like can be used. Furthermore, the above metal film or the above metal oxide film may be provided under the conductive film that reflects visible light.

When aluminum is used as the anode or the anode, the thickness of aluminum is preferably greater than or equal to 40 nm, further preferably greater than or equal to 70 nm, in which case the reflectivity of visible light or the like can be sufficiently increased. When silver is used as the cathode or the anode, the thickness of silver is preferably greater than or equal to 70 nm, further preferably greater than or equal to 100 nm, in which case the reflectivity of visible light or the like can be sufficiently increased.

As the conductive film having light transmitting and reflecting properties that can be used for the cathode or the anode, the conductive film reflecting visible light formed to be thin enough to transmit visible light can be used. In addition, with the stacked-layer structure of the conductive film and the conductive film transmitting visible light, the conductivity or the mechanical strength can be increased.

The conductive film having light transmitting and reflecting properties has a reflectance with respect to visible light (e.g., the reflectance with respect to light having a specific wavelength within the range of 400 nm to 700 nm) of higher than or equal to 20% and lower than or equal to 80%, preferably higher than or equal to 40% and lower than or equal to 70%. The conductive film having reflectivity preferably has a reflectance with respect to visible light higher than or equal to 40% and lower than or equal to 100%, further preferably higher than or equal to 70% and lower than or equal to 100%. The conductive film having light-transmitting property preferably has a reflectance with respect to visible light higher than or equal to 0% and lower than or equal to 40%, further preferably higher than or equal to 0% and lower than or equal to 30%.

Each of the electrodes included in the light-emitting element can be formed by an evaporation method, a sputtering method or the like. Alternatively, a discharging method such as an inkjet method, a printing method such as a screen printing method, or a plating method may be used.

At least part of any of the structure examples, the drawings corresponding thereto, and the like described in this embodiment can be implemented in combination with any of the other structure examples, the other drawings corresponding thereto, and the like as appropriate.

In this embodiment, electronic devices of one embodiment of the present invention will be described with reference toFIGS.28A and28B,FIGS.29A to29D,FIGS.30A to30F, andFIGS.31A to31F.

An electronic device in this embodiment includes the display device of one embodiment of the present invention. For the display device of one embodiment of the present invention, increases in resolution, definition, and sizes are easily achieved. Thus, the display device of one embodiment of the present invention can be used for display portions of a variety of electronic devices.

The display device of one embodiment of the present invention can be manufactured at low cost, which leads to a reduction in manufacturing cost of an electronic device.

Examples of electronic devices include electronic devices with a relatively large screen, such as a television device, a desktop or laptop personal computer, a monitor of a computer or the like, digital signage, and a large game machine (e.g., a pachinko machine); a camera such as a digital camera or a digital video camera; a digital photo frame; a mobile phone; a portable game console; a portable information terminal; and an audio reproducing device.

In particular, a display device of one embodiment of the present invention can have a high resolution, and thus can be favorably used for an electronic device having a relatively small display portion. As such an electronic device, a watch-type or bracelet-type information terminal device (wearable device); and a wearable device worn on a head, such as a device for VR such as a head mounted display and a glasses-type device for AR can be given, for example. Examples of wearable devices include a device for substitution reality (SR) and a device for mixed reality (MR).

The resolution of the display device of one embodiment of the present invention is preferably as high as HD (number of pixels: 1280×720), FHD (number of pixels: 1920×1080), WQHD (number of pixels: 2560×1440), WQXGA (number of pixels: 2560×1600), 4K2K (number of pixels: 3840×2160), or 8K4K (number of pixels: 7680×4320). In particular, resolution of 4K2K, 8K4K, or higher is preferable. Furthermore, the pixel density (definition) of the display device of one embodiment of the present invention is preferably higher than or equal to 300 ppi, further preferably higher than or equal to 500 ppi, still further preferably higher than or equal to 1000 ppi, still further preferably higher than or equal to 2000 ppi, still further preferably higher than or equal to 3000 ppi, still further preferably higher than or equal to 5000 ppi, and yet further preferably higher than or equal to 7000 ppi. With such a display device with high resolution and high definition, the electronic device can have higher realistic sensation, sense of depth, and the like in personal use such as portable use and home use.

The electronic device in this embodiment can be incorporated along a curved surface of an inside wall or an outside wall of a house or a building or the interior or the exterior of a car.

The electronic device in this embodiment may include an antenna. With the antenna receiving a signal, the electronic device can display an image, information, and the like on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

An electronic device6500inFIG.28Ais a portable information terminal that can be used as a smartphone.

FIG.28Bis a schematic cross-sectional view including an end portion of the housing6501on the microphone6506side.

The display panel6511, the optical member6512, and the touch sensor panel6513are fixed to the protection member6510with an adhesive layer (not illustrated).

Part of the display panel6511is folded back in a region outside the display portion6502, and an FPC6515is connected to the part that is folded back. An IC6516is mounted on the FPC6515. The FPC6515is connected to a terminal provided on the printed circuit board6517.

A flexible display of one embodiment of the present invention can be used as the display panel6511. Thus, an extremely lightweight electronic device can be achieved. Since the display panel6511is extremely thin, the battery6518with high capacity can be mounted while the thickness of the electronic device is controlled. Moreover, a part of the display panel6511is folded back so that a connection portion with the FPC6515is provided on the back side of the pixel portion, whereby an electronic device with a narrow bezel can be achieved.

FIG.29Aillustrates an example of a television device. In a television device7100, a display portion7000is incorporated in a housing7101. Here, the housing7101is supported by a stand7103.

The display device of one embodiment of the present invention can be used for the display portion7000.

Operation of the television device7100illustrated inFIG.29Acan be performed with an operation switch provided in the housing7101and a separate remote controller7111. Alternatively, the display portion7000may include a touch sensor, and the television device7100may be operated by touch on the display portion7000with a finger or the like. The remote controller7111may be provided with a display portion for displaying information output from the remote controller7111. With operation keys or a touch panel provided in the remote controller7111, channels and volume can be operated and videos displayed on the display portion7000can be operated.

Note that the television device7100has a structure in which a receiver, a modem, and the like are provided. A general television broadcast can be received with the receiver. When the television device is connected to a communication network with or without wires via the modem, one-way (from a transmitter to a receiver) or two-way (between a transmitter and a receiver or between receivers, for example) data communication can be performed.

FIG.29Billustrates an example of a laptop personal computer. The laptop personal computer7200includes a housing7211, a keyboard7212, a pointing device7213, an external connection port7214, and the like. In the housing7211, the display portion7000is incorporated.

The display device of one embodiment of the present invention can be used for the display portion7000.

A digital signage7300illustrated inFIG.29Cincludes a housing7301, the display portion7000, a speaker7303, and the like. The digital signage7300can also include an LED lamp, an operation key (including a power switch or an operation switch), a connection terminal, a variety of sensors, a microphone, and the like.

FIG.29Dillustrates a digital signage7400mounted on a cylindrical pillar7401. The digital signage7400includes the display portion7000provided along a curved surface of the pillar7401.

The display device of one embodiment of the present invention can be used in the display portion7000illustrated in each ofFIGS.29C and29D.

A larger area of the display portion7000can increase the amount of data that can be provided at a time. The larger display portion7000attracts more attention, so that the effectiveness of the advertisement can be increased, for example.

The use of a touch panel in the display portion7000is preferable because in addition to display of a still image or a moving image on the display portion7000, intuitive operation by a user is possible. Moreover, for an application for providing information such as route information or traffic information, usability can be enhanced by intuitive operation.

As illustrated inFIGS.29C and29D, it is preferable that the digital signage7300or the digital signage7400can work with an information terminal7311or an information terminal7411such as a smartphone a user has through wireless communication. For example, information of an advertisement displayed on the display portion7000can be displayed on a screen of the information terminal7311or the information terminal7411. By operation of the information terminal7311or the information terminal7411, display on the display portion7000can be switched.

It is possible to make the digital signage7300or the digital signage7400execute a game with use of the screen of the information terminal7311or the information terminal7411as an operation means (controller). Thus, an unspecified number of users can join in and enjoy the game concurrently.

FIG.30Ais an external view of a camera8000to which a finder8100is attached.

The camera8000includes a housing8001, a display portion8002, operation buttons8003, a shutter button8004, and the like. Furthermore, a detachable lens8006is attached to the camera8000. Note that the lens8006and the housing may be integrated with each other in the camera8000.

Images can be taken with the camera8000at the press of the shutter button8004or the touch of the display portion8002serving as a touch panel.

The housing8001includes a mount including an electrode, so that the finder8100, a stroboscope, or the like can be connected to the housing.

The finder8100includes a housing8101, a display portion8102, a button8103, and the like.

The housing8101is attached to the camera8000by a mount for engagement with the mount of the camera8000. The finder8100can display a video received from the camera8000and the like on the display portion8102.

The button8103functions as a power supply button or the like.

A display device of one embodiment of the present invention can be used in the display portion8002of the camera8000and the display portion8102of the finder8100. Note that a finder may be incorporated in the camera8000.

FIG.30Bis an external view of a head-mounted display8200.

The head-mounted display8200includes a mounting portion8201, a lens8202, a main body8203, a display portion8204, a cable8205, and the like. A battery8206is incorporated in the mounting portion8201.

The cable8205supplies electric power from the battery8206to the main body8203. The main body8203includes a wireless receiver or the like to receive image data and display it on the display portion8204. The main body8203includes a camera, and data on the movement of the eyeballs or the eyelids of the user can be used as an input means.

The mounting portion8201may include a plurality of electrodes capable of sensing current flowing accompanying with the movement of the user's eyeball at a position in contact with the user to recognize the user's sight line. The mounting portion8201may also have a function of monitoring the user's pulse with use of current flowing in the electrodes. The mounting portion8201may include sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor so that the user's biological information can be displayed on the display portion8204and an image displayed on the display portion8204can be changed in accordance with the movement of the user's head.

A display device of one embodiment of the present invention can be used in the display portion8204.

FIGS.30C to30Eare external views of a head-mounted display8300. The head-mounted display8300includes the housing8301, the display portion8302, the band-like fixing member8304, and a pair of lenses8305.

A user can see display on the display portion8302through the lenses8305. The display portion8302is preferably curved because the user can feel high realistic sensation. Another image displayed in another region of the display portion8302is viewed through the lenses8305, so that three-dimensional display using parallax or the like can be performed. Note that the number of the display portions8302is not limited to one; two display portions8302may be provided for user's respective eyes.

The display device of one embodiment of the present invention can be used for the display portion8302. The display device of one embodiment of the present invention achieves extremely high resolution. For example, a pixel is not easily seen by the user even when the user sees display that is magnified by the use of the lenses8305as illustrated inFIG.30E. In other words, a video with a strong sense of reality can be seen by the user with use of the display portion8302.

FIG.30Fis an external view of a google-type head-mounted display8400. The head-mounted display8400includes a pair of housings8401, a mounting portion8402, and a cushion8403. A display portion8404and a lens8405are provided in each of the pair of housings8401. Furthermore, when the pair of display portions8404display different images, three-dimensional display using parallax can be performed.

A user can see display on the display portion8404through the lens8405. The lens8405has a focus adjustment mechanism and can adjust the position according to the user's eyesight. The display portion8404is preferably a square or a horizontal rectangle. This can improve a realistic sensation.

The mounting portion8402preferably has flexibility and elasticity so as to be adjusted to fit the size of the user's face and not to slide down. In addition, part of the mounting portion8402preferably has a vibration mechanism functioning as a bone conduction earphone. Thus, audio devices such as an earphone and a speaker are not necessarily provided separately, and the user can enjoy images and sounds only when wearing the head-mounted display8400. Note that the housing8401may have a function of outputting sound data by wireless communication.

The mounting portion8402and the cushion8403are portions in contact with the user's face (forehead, cheek, or the like). The cushion8403is in close contact with the user's face, so that light leakage can be prevented, which increases the sense of immersion. The cushion8403is preferably formed using a soft material so that the head-mounted display8400is in close contact with the user's face when being worn by the user. For example, a material such as rubber, silicone rubber, urethane, or sponge can be used. Furthermore, when a sponge or the like whose surface is covered with cloth, leather (natural leather or synthetic leather), or the like is used, a gap is unlikely to be generated between the user's face and the cushion8403, whereby light leakage can be suitably prevented. Furthermore, using such a material is preferable because it has a soft texture and the user does not feel cold when wearing the device in a cold season, for example. The member in contact with user's skin, such as the cushion8403or the mounting portion8402, is preferably detachable because cleaning or replacement can be easily performed.

The electronic devices illustrated inFIGS.31A to31Fhave a variety of functions. For example, the electronic device can have a function of displaying a variety of information (a still image, a moving image, a text image, and the like) on the display portion, a touch panel function, a function of displaying a calendar, date, time, and the like, a function of executing a variety of software (programs), a wireless communication function, and a function of reading out a program or data stored in a recording medium. Note that the functions of the electronic devices are not limited thereto, and the electronic devices can have a variety of functions. The electronic devices may include a plurality of display portions. The electronic devices may each be provided with a camera or the like and have a function of taking a still image or a moving image, a function of storing the taken image in a storage medium (an external storage medium or a storage medium incorporated in the camera), a function of displaying the taken image on the display portion, or the like.

The display device of one embodiment of the present invention can be used for the display portion9001.

The electronic devices illustrated inFIGS.31A to31Fwill be described in detail below.

FIG.31Ais a perspective view showing a portable information terminal9101. For example, the portable information terminal9101can be used as a smartphone. Note that the portable information terminal9101may include the speaker9003, the connection terminal9006, the sensor9007, or the like. The portable information terminal9101can display characters and image information on its plurality of surfaces.FIG.31Aillustrates an example in which three icons9050are displayed. Furthermore, information9051indicated by dashed rectangles can be displayed on another surface of the display portion9001. Examples of the information9051include notification of reception of an e-mail, an SNS message, or an incoming call, the title and sender of an e-mail, an SNS message, or the like, the date, the time, remaining battery, and the reception strength of an antenna. Alternatively, the icon9050or the like may be displayed at the position where the information9051is displayed.

FIG.31Bis a perspective view showing a portable information terminal9102. The portable information terminal9102has a function of displaying information on three or more surfaces of the display portion9001. Here, information9052, information9053, and information9054are displayed on different surfaces. For example, a user of the portable information terminal9102can check the information9053displayed such that it can be seen from above the portable information terminal9102, with the portable information terminal9102put in a breast pocket of his/her clothes. Thus, the user can see the display without taking out the portable information terminal9102from the pocket and decide whether to answer the call, for example.

FIG.31Cis a perspective view illustrating a watch-type portable information terminal9200. For example, the portable information terminal9200can be used as a Smartwatch (registered trademark). The display surface of the display portion9001is curved, and an image can be displayed on the curved display surface. Mutual communication between the portable information terminal9200and, for example, a headset capable of wireless communication enables hands-free calling. With the connection terminal9006, the portable information terminal9200can perform mutual data transmission with another information terminal and charging. Note that the charging operation may be performed by wireless power feeding.

FIGS.31D to31Fare perspective views illustrating a foldable portable information terminal9201.FIG.31Dis a perspective view of an opened state of the portable information terminal9201,FIG.31Fis a perspective view of a folded state thereof, andFIG.31Eis a perspective view of a state in the middle of change from one ofFIG.31DandFIG.31Fto the other. The portable information terminal9201is highly portable when folded. When the portable information terminal9201is opened, a seamless large display region is highly browsable. The display portion9001of the portable information terminal9201is supported by three housings9000joined together by hinges9055. For example, the display portion9001can be folded with a radius of curvature greater than or equal to 0.1 mm and less than or equal to 150 mm.

At least part of any of the structure examples, the drawings corresponding thereto, and the like described in this embodiment can be implemented in combination with any of the other structure examples, the other drawings corresponding thereto, and the like as appropriate.

The application of the transistor200described in Embodiment 1 is not limited to display devices, electronic devices including the display device, and the like. In this embodiment, a memory device including a transistor in which an oxide is used for a semiconductor (hereinafter sometimes referred to as an OS transistor) of one embodiment of the present invention will be described with reference toFIGS.32A and32BandFIGS.33A to33H. The OS memory device includes at least a capacitor and an OS transistor that controls the charging and discharging of the capacitor. Since the OS transistor has an extremely low off-state current, the OS memory device has excellent retention characteristics and can function as a nonvolatile memory.

Structure Example of Memory Device

FIG.32Ashows a structure example of an OS memory device. A memory device1400includes a peripheral circuit1411and a memory cell array1470. The peripheral circuit1411includes a row circuit1420, a column circuit1430, an output circuit1440, and a control logic circuit1460.

The column circuit1430includes a column decoder, a precharge circuit, a sense amplifier, and a write circuit, for example. The precharge circuit has a function of precharging wirings. The sense amplifier has a function of amplifying a data signal read from a memory cell. The wirings mentioned above are connected to memory cells included in the memory cell array1470, which will be described later in detail. The amplified data signal is output as a data signal RDATA to the outside of the memory device1400through the output circuit1440. The row circuit1420includes a row decoder and a word line driver circuit, for example, and can select a row to be accessed.

As power supply voltages from the outside, a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit1411, and a high power supply voltage (VIL) for the memory cell array1470are supplied to the memory device1400. Control signals (CE, WE, and RE), an address signal ADDR, and a data signal WDATA are also input to the memory device1400from the outside. The address signal ADDR is input to the row decoder and the column decoder, and the data signal WDATA is input to the write circuit.

The control logic circuit1460processes the control signals (CE, WE, and RE) input from the outside, and generates control signals for the row decoder and the column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. Signals processed by the control logic circuit1460are not limited thereto and other control signals may be input as necessary.

The memory cell array1470includes a plurality of memory cells MC arranged in a matrix and a plurality of wirings. The number of wirings that connect the memory cell array1470and the row circuit1420depends on the configuration of the memory cell MC, the number of memory cells MC in one column, and the like. The number of wirings that connect the memory cell array1470and the column circuit1430depends on the configuration of the memory cell MC, the number of memory cells MC in one row, and the like.

FIG.32Ashows an example in which the peripheral circuit1411and the memory cell array1470are formed on the same plane; however, this embodiment is not limited thereto. For example, as illustrated inFIG.32B, the memory cell array1470may be provided to partly overlap the peripheral circuit1411. For example, the sense amplifier may be provided below the memory cell array1470so that they overlap each other.

FIGS.33A to33Hillustrate configuration examples of memory cells that can be used as the memory cell MC.

FIGS.33A to33Cillustrate a circuit configuration example of a memory cell of a DRAM. In this specification and the like, a DRAM using a memory cell including one OS transistor and one capacitor is sometimes referred to as a dynamic oxide semiconductor random access memory (DOSRAM). A memory cell1471shown inFIG.33Aincludes a transistor M1and a capacitor CA. The transistor M1includes a gate (also sometimes referred to as a top gate) and a back gate.

A first terminal of the transistor M1is connected to a first terminal of the capacitor CA. A second terminal of the transistor M1is connected to a wiring BIL. The gate of the transistor M1is connected to a wiring WOL. The back gate of the transistor M1is connected to a wiring BGL. A second terminal of the capacitor CA is connected to a wiring LL.

The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring LL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. In data writing and data reading, the wiring LL may be set to a ground potential or a low-level potential. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. The threshold voltage of the transistor M1can be increased or decreased by supplying a given potential to the wiring BGL.

The memory cell MC is not limited to the memory cell1471and can have a different circuit configuration. For example, in the memory cell MC, the back gate of the transistor M1may be connected to the wiring WOL instead of the wiring BGL as in a memory cell1472illustrated inFIG.33B. As another example of the memory cell MC, the transistor M1may be a single-gate transistor, that is, a transistor without a back gate as in a memory cell1473illustrated inFIG.33C.

When the semiconductor device shown in the above embodiment is used in the memory cell1471and the like, the transistor200can be used as the transistor M1. When an OS transistor is used as the transistor M1, the leakage current of the transistor M1can be extremely low. That is, with use of the transistor M1, written data can be retained for a long time, and thus the frequency of refresh operation for the memory cell can be decreased. Alternatively, refresh operation for the memory cell can be omitted. In addition, since the transistor M1has an extremely low leakage current, multi-level data or analog data can be retained in the memory cells1471,1472, and1473.

In the DOSRAM, when the sense amplifier is provided below the memory cell array1470so that they overlap each other as described above, the bit line can be shortened. This reduces bit line capacity, which reduces the storage capacity of the memory cell.

FIGS.33D to33Geach illustrate a circuit configuration example of a gain-cell memory cell including two transistors and one capacitor. A memory cell1474illustrated inFIG.33Dincludes a transistor M2, a transistor M3, and a capacitor CB. The transistor M2includes a top gate (simply referred to as a gate in some cases) and a back gate. In this specification and the like, a memory device including a gain-cell memory cell using an OS transistor as the transistor M2is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM) in some cases.

A first terminal of the transistor M2is connected to a first terminal of the capacitor CB. A second terminal of the transistor M2is connected to a wiring WBL. The gate of the transistor M2is connected to the wiring WOL. The back gate of the transistor M2is connected to the wiring BGL. A second terminal of the capacitor CB is connected to the wiring CAL. A first terminal of the transistor M3is connected to a wiring RBL. A second terminal of the transistor M3is connected to a wiring SL. A gate of the transistor M3is connected to the first terminal of the capacitor CB.

The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. A high-level potential is preferably applied to the wiring CAL at the time of data writing and data reading. In the data retention, the low-level potential is preferably applied to the wiring CAL. The wiring BGL functions as a wiring for applying a predetermined potential to the back gate of the transistor M2. The threshold voltage of the transistor M2can be increased or decreased by supplying a given potential to the wiring BGL.

The circuit configuration of the memory cell MC is not limited to that of the memory cell1474, and the circuit configuration can be changed as appropriate. For example, as in a memory cell1475illustrated inFIG.33E, the back gate of the transistor M2may be connected not to the wiring BGL but to the wiring WOL in the memory cell MC. Alternatively, for example, the transistor M2may be a single-gate transistor, that is, a transistor without a back gate in the memory cell MC as in a memory cell1476illustrated inFIG.33F. For example, the memory cell MC may have a structure in which the wirings WBL and RBL are combined into one wiring BIL as in a memory cell1477illustrated inFIG.33G.

When the semiconductor device shown in the above embodiment is used in the memory cell1474and the like, the transistor200can be used as the transistor M2. When an OS transistor is used as the transistor M2, the leakage current of the transistor M2can be extremely low. That is, with use of the transistor M2, written data can be retained for a long time, and thus the frequency of the refresh operation for the memory cell can be decreased. Alternatively, refresh operation for the memory cell can be omitted. In addition, since the transistor M2has an extremely low leakage current, multi-level data and analog data can be retained in the memory cell1474. The same applies to the memory cells1475to1477.

Note that the transistor M3may be a transistor containing silicon in a channel formation region (hereinafter, also referred to as a Si transistor in some cases). The Si transistor may be either an n-channel transistor or a p-channel transistor. The Si transistor has higher field-effect mobility than the OS transistor in some cases. Therefore, a Si transistor may be used as the transistor M3functioning as a reading transistor. Furthermore, the transistor M2can be formed over the transistor M3when a Si transistor is used as the transistor M3, in which case the area of the memory cell can be reduced, leading to high integration of the memory device.

Alternatively, the transistor M3may be an OS transistor. When an OS transistor is used as each of the transistors M2and M3, the memory cell array1470can be formed using only n-channel transistors.

FIG.33Hillustrates an example of a gain-cell memory cell including three transistors and one capacitor. A memory cell1478illustrated inFIG.33Hincludes transistors M4to M6and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell1478is electrically connected to the wiring BIL, a wiring RWL, a wiring WWL, the wiring BGL, and a wiring GNDL. The wiring GNDL is a wiring for supplying a low-level potential. Note that the memory cell1478may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.

The transistor M4is an OS transistor with a back gate that is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4may be electrically connected to each other. Alternatively, the transistor M4may not include the back gate.

Note that each of the transistors M5and M6may be an n-channel Si transistor or a p-channel Si transistor. Alternatively, the transistor M4to the transistor M6may be OS transistors. In that case, the circuit of the memory cell array1470can be formed using only n-channel transistors.

When the semiconductor device shown in the above embodiment is used in the memory cell1478and the like, the transistor200can be used as the transistor M4. When an OS transistor is used as the transistor M4, the leakage current of the transistor M4can be extremely low.

Note that the configurations of the peripheral circuit1411, the memory cell array1470, and the like shown in this embodiment are not limited to those described above. The arrangement and functions of these circuits and the wirings, circuit components, and the like connected to the circuits can be changed, removed, or added as needed.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the other structures, methods, and the like described in this embodiment or any of the structures, methods, and the like described in the other embodiments.

In this embodiment, a memory device, a chip, and an electronic device in which a semiconductor device of the present invention is mounted will be described.

In this embodiment, application examples of a memory device using the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment can be applied to, for example, memory devices of a variety of electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), video recording/reproducing devices, and navigation systems). Here, computers refer not only to tablet computers, laptop computers, and desktop computers, but also to large computers such as server systems. The semiconductor device described in the above embodiment is applied to removable memory devices such as memory cards (e.g., SD cards), USB memories, and solid state drives (SSD).

A plurality of circuits (systems) are mounted on the chip. The technique for integrating a plurality of circuits (systems) on one chip is referred to as system on chip (SoC) in some cases.

The chip includes a CPU, a GPU, at least one analog arithmetic unit, at least one memory controller, at least one interface, at least one network circuit, and the like.

A bump (not illustrated) is provided on the chip, and the chip is connected to a first surface of a printed circuit board (PCB). A plurality of bumps are provided on the rear side of the first surface of the PCB, and the PCB is connected to a motherboard.

A memory device such as a DRAM or a flash memory may be provided over the motherboard. For example, the DOSRAM described in the above embodiment can be used as the DRAM. For example, the NOSRAM described in the above embodiment can be used as the flash memory.

The CPU preferably includes a plurality of CPU cores. The GPU preferably includes a plurality of GPU cores. The CPU and the GPU may each include a memory for storing data temporarily. Alternatively, a common memory for the CPU and the GPU may be provided in the chip. The NOSRAM or the DOSRAM described above can be used as the common memory. The GPU is suitable for parallel computation of a number of data and thus can be used for image processing and product-sum operation. When an image processing circuit and a product-sum operation circuit including an oxide semiconductor of the present invention is provided in the GPU, image processing and product-sum operation can be performed with low power consumption.

The analog arithmetic unit includes one or both of an analog/digital (A/D) converter circuit and a digital/analog (D/A) converter circuit. Furthermore, the analog arithmetic unit may include the above-described product-sum operation circuit.

The memory controller includes a circuit functioning as a controller of the DRAM and a circuit functioning as the interface of the flash memory.

The interface includes an interface circuit for connection with an external connection device such as a display device, a speaker, a microphone, a camera, or a controller.

The network circuit includes a circuit for a network such as a local-area network (LAN). Furthermore, the network circuit may include a circuit for network security.

The motherboard provided with the PCB on which the chip including the GPU is mounted, the DRAM, and the flash memory can be referred to as a GPU module.

The GPU module includes the chip formed using the SoC technology, and thus can have a small size. Furthermore, the GPU module is excellent in image processing, and thus is suitably used in a portable electronic device such as a smartphone, a tablet terminal, a laptop PC, or a portable (mobile) game console. Furthermore, the product-sum operation circuit using the GPU can implement techniques such as a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), or a deep belief network (DBN); hence, the chip can be used as an AI chip or the GPU module can be used as an AI system module.

The above-described chip can be mounted on a variety of electronic devices. Examples of electronic devices include electronic devices with relatively large screens (e.g., television devices, monitors for desktop or laptop information terminals and the like, digital signage, and large game machines such as pachinko machines), cameras such as digital cameras and digital video cameras, digital photo frames, e-book readers, mobile phones (smartphones), portable game machines, portable information terminals, and audio reproducing devices. Other examples of moving vehicles include an automobile, a train, a monorail train, a ship, and a flying object (a helicopter, an unmanned aircraft (a drone), an airplane, and a rocket). Examples of household appliances include an electric refrigerator-freezer, a vacuum, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, a heating-cooling combination appliance such as an air conditioner, a washing machine, a drying machine, and an audio visual appliance. When the chip of one embodiment of the present invention is provided in an electronic device, the electronic device can include artificial intelligence.

The electronic device of one embodiment of the present invention may include an antenna. When a signal is received by the antenna, the electronic device can display a video, data, or the like on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

The electronic device and its functions, an application example of the artificial intelligence and its effects, and the like described in this embodiment can be combined as appropriate with the description of another electronic device.

Example

In this example, results relating to negative-bias stress temperature photodegradation will be described. Specifically, this example shows results of negative-bias stress temperature photodegradation measurement, evaluation of density of deep defect states, and SIMS measurement, which were performed on transistors. In this example, the deep defect states of an oxide semiconductor film were evaluated by a constant photocurrent method (CPM).

In this section, samples fabricated in this example are described. In this example, three samples (Samples800A,800B, and800C) were fabricated. A transistor included in each sample has a dual gate structure including a top gate and a bottom gate (also referred to as a back gate). The transistor includes an oxide semiconductor film in a channel formation region.

FIG.34is a schematic cross-sectional view of the transistor included in each sample. The transistor illustrated inFIG.34includes, over a substrate851, a conductive layer821, an insulating layer811over the conductive layer821, a semiconductor layer831over the insulating layer811, an insulating layer825over the semiconductor layer831and the insulating layer811, a conductive layer823over the insulating layer825, an insulating layer815over the conductive layer823and the insulating layer825, and a conductive layer822aand a conductive layer822bover the insulating layer815. The semiconductor layer831includes a channel formation region831iand a pair of low-resistance regions831n.

The conductive layer823functions as a top gate, the insulating layer825functions as a top gate insulating layer, the conductive layer821functions as a bottom gate, and the insulating layer811functions as a bottom gate insulating layer. The conductive layer822aand the conductive layer822bare connected to the corresponding low-resistance regions831nthrough openings provided in the insulating layer825and the insulating layer815. One of the conductive layer822aand the conductive layer822bserves as a source, and the other serves as a drain.

In the transistor, the channel length L was 3 μm and the channel width W was 50 μm.

In addition to the transistor, a TEG for CPM evaluation and a TEG for SIMS measurement were included in each of fabricated Samples800A to800C.

As the semiconductor layer831, a 25-nm-thick oxide semiconductor film deposited by a sputtering method was used. Deposition of the oxide semiconductor film was performed under the following conditions. An oxide target with an atomic ratio where In:Ga:Zn=1:1:1 was used; the substrate temperature during the deposition was set to room temperature; the deposition gas contained an oxygen gas (10% as the flow rate) and an argon gas (90% as the flow rate); the pressure was 0.6 PA; and the alternating-current (AC) power source was set to 2.5 kW.

As the insulating layer825, a 100-nm-thick silicon oxynitride film deposited by a PECVD method was used. The deposition condition (the substrate temperature) of the silicon oxynitride film used as the insulating layer825differs between Samples800A to800C. Specifically, the substrate temperatures during the deposition were 300° C. in Sample800A, 350° C. in Sample800B, and 400° C. in Sample800C. The other deposition conditions (such as the deposition gas species, the pressure, and the power) of the silicon oxynitride film used as the insulating layer825were common between Samples800A to800C.

The TEG for CPM evaluation includes the semiconductor layer831, the insulating layer825, and a pair of electrodes electrically connected to the semiconductor layer831. The TEG for SIMS measurement includes the semiconductor layer831and the insulating layer825.

In this section, the measurement results of negative-bias stress temperature photodegradation are described. Specifically, obtained results through the following process are described. Stress was applied to the samples including the transistors in such a manner that a negative voltage was applied to the top gates and the bottom gates while the samples were irradiated with light, and threshold voltages Vthof the transistors, which changed depending on the time period of applying the stress, were evaluated.

Stress was applied to fabricated Samples800A to800C by application of a negative voltage to the gates under light irradiation. Then, Id-Vgcharacteristics of the transistors in the samples were measured, whereby the amount of change in threshold voltages before and after the stress application was evaluated.

In applying the stress, the temperature was set to 105° C., the gate voltage was −20V, the drain voltage was 0 V, the source voltage was 0 V, the illuminance of irradiation light was 10000 lx, and the time for stress application was an hour. The Id-Vgcharacteristics of the transistors to which the above stress had been applied were measured. In measuring the Id-Vgcharacteristics, the drain voltage was set to +10 V, the gate voltage was swept in the range of from −15 V to +2 V in 0.1 V steps, and the other conditions were similar to those in applying stress.

FIG.35shows measurement results of the negative-bias stress temperature photodegradation in the transistors in the samples. Specifically,FIG.35is a graph showing the amount of change in threshold voltages ΔVthof the transistors in the samples. InFIG.35, the vertical axis represents the amount of change in threshold voltages ΔVth[V], and the horizontal axis represents the substrate temperature [° C.] during the formation of the insulating layer825.

As shown inFIG.35, the absolute value of the amount of change in the threshold voltage ΔVthof the transistor included in Sample800A is almost the same that of the transistor included in Sample800B. The absolute value of the amount of change in the threshold voltage ΔVthof the transistor included in Sample800C is larger than that of the transistor included in Sample800B. In other words, the above results indicate that, even when the substrate temperature during the formation of the insulating layer825is increased from 300° C. to 350° C., there is almost no difference in the amount of changes in threshold voltages. However, when the substrate temperature during the formation of the insulating layer825is increased from 350° C. to 400° C., the amount of change in threshold voltages is increased.

<Evaluation of Density of Deep Defect States>

With use of the TEGs for CPM evaluation included in fabricated Samples800A to800C, deep defects states (levels) of oxide semiconductor films were evaluated.

In CPM measurement, the amount of light with which a surface of a sample between terminals is irradiated is adjusted in the state where voltage is applied between two electrodes included in the sample so that a photocurrent value is kept constant, and then an absorption coefficient is derived from the amount of the irradiation light with each wavelength. In the CPM measurement, when the sample has a defect, the absorption coefficient of energy which corresponds to a level attributed to the defect (calculated from a wavelength) is increased. The increase in the absorption coefficient is multiplied by a constant, whereby the density of deep defect states (also referred to as dDOS) of the sample can be obtained.

A part of the absorption coefficient which is referred to as an urbach tail due to the band tail is removed from a curve of the absorption coefficient obtained by the CPM measurement, whereby the absorption α due to the defect levels can be calculated from the following formula. Here, E represents energy, αCPMrepresents an absorption coefficient obtained through CPM measurement, and au represents an absorption coefficient in the urbach tail.

FIG.36shows CPM measurement results of Samples800A to800C. InFIG.36, the vertical axis represents absorption α [cm−1] due to the deep defect level, and the horizontal axis represents the substrate temperature [° C.] during the formation of the insulating layer825.

As shown in the results inFIG.36, the absorption α due to the deep defect level changes depending on the substrate temperature during the formation of the insulating layer825. Specifically, the absorption α due to the deep defect level in the oxide semiconductor film included in Sample800B is higher than that in the oxide semiconductor film in Sample800A. The absorption α due to the deep defect level in the oxide semiconductor film included in Sample800C is lower than that in the oxide semiconductor film in Sample800B. In other words, the results indicate that the density of deep defect states is decreased when the substrate temperature during the formation of the insulating layer825is increased from 350° C. to 400° C.

SIMS analysis was performed on the TEGs for SIMS evaluation included in fabricated Samples800A to800C. The direction in which the SIMS analysis proceeded was a direction from the insulating layer825toward the semiconductor layer831. In this SIMS analysis, a PHI ADEPT-1010 quadrupole SIMS instrument manufactured by ULVAC-PHI, Inc was used. From the SIMS analysis, profiles of indium, gallium, and zinc concentrations in the TEGs for SIMS evaluation in the samples were obtained.

FIGS.37A to37Cshow results of SIMS analysis on the TEGs for SIMS evaluation. Specifically,FIGS.37A to37Cshow profile results of indium, gallium, and zinc concentrations, respectively, at the interface between the insulating layer825and the semiconductor layer831and in its vicinity in the TEGs for SIMS evaluation. In each ofFIGS.37A to37C, the horizontal axis represents the depth in the film thickness direction (Depth) [nm]. Note that the position at a depth of 0 nm in the film thickness direction corresponds to the top surface (the surface on the side not in contact with the semiconductor layer831) of the insulating layer825, and the position at a depth approximately 100 nm in the film thickness direction corresponds to the interface between the insulating layer825and the semiconductor layer831.

InFIGS.37A to37C, areas corresponding to the insulating layer825and the semiconductor layer831are denoted by arrows. Note thatFIGS.37A to37Ceach seem to provide a space between two adjacent arrows. This is because it is difficult to strictly specify the interface between two films in SIMS analysis. For example, when the position where the depth in the film thickness direction is 0 nm is set to the top surface (the surface on the side not in contact with the semiconductor layer831) of the insulating layer825, the position where the depth in the film thickness direction is equal to the thickness of the insulating layer825is defined as the interface between the insulating layer825and the semiconductor layer831. In this example, since the thickness of the insulating layer825is 100 nm, the interface between the insulating layer825and the semiconductor layer831is positioned at a depth of 100 nm in the film thickness direction.

The vertical axis inFIG.37Arepresents the indium concentration (In concentration) per unit volume [atoms/cm3]; that inFIG.37B, the gallium concentration (Ga concentration) per unit volume [atoms/cm3]; and that inFIG.37C, the zinc concentration (Zn concentration) per unit volume [atoms/cm3].

In each ofFIGS.37A to37C, the dotted line indicates a profile of a metal (In, Ga, or Zn) contained in the TEG for SIMS evaluation in Sample800A, the dashed-dotted line indicates a profile of a metal contained in the TEG for SIMS evaluation in Sample800B, and the solid line indicates a profile of a metal contained in the TEG for SIMS evaluation in Sample800C.

According toFIG.37A, Sample800C exhibits the largest amount of indium diffusing from the semiconductor layer831into the insulating layer825, Sample800B exhibits the second largest amount, and Sample800A exhibits the smallest amount. The results indicate that indium diffuses into the insulating layer825as the temperature during the formation of the insulating layer825rises. In addition, according toFIG.37A, the insulating layer825in Sample800A has a region where the indium concentration is lower than or equal to 1×1019atoms/cm3, within 5 nm from the interface between the insulating layer825and the semiconductor layer831. Moreover, the insulating layer825in Sample800A has a region where the indium concentration is lower than or equal to 5×1018atoms/cm3, within 10 nm from the interface between the insulating layer825and the semiconductor layer831.

According toFIG.37B, all Samples800A to800C exhibit almost the same amount of gallium diffusing from the semiconductor layer831into the insulating layer825. According toFIG.37C, all Samples800A to800C exhibit almost the same amount of zinc diffusing from the semiconductor layer831into the insulating layer825. In other words, dependence on the temperature during the formation of the insulating layer825was not observed in diffusion of gallium and zinc into the insulating layer825.

The results described in this example and the calculation results described in the aforementioned embodiments suggest the following possibility. In a transistor using an oxide containing indium (typically IGZO) for a channel formation region, the negative-bias stress temperature photodegradation is accelerated when indium diffuses into a gate insulator to form InSiin the gate insulator.

The structure described above in this example can be combined with any of the structures described in the other embodiments as appropriate.

This application is based on Japanese Patent Application Serial No. 2021-035525 filed with Japan Patent Office on Mar. 5, 2021, Japanese Patent Application Serial No. 2021-080946 filed with Japan Patent Office on May 12, 2021, and Japanese Patent Application Serial No. 2021-161151 filed with Japan Patent Office on Sep. 30, 2021, the entire contents of which are hereby incorporated by reference.