Control methods and power controllers with load compensation adapted for a power supply

Disclosure includes control methods and power controllers with load compensation adapted for a power supply powering a load. A disclosed power controller comprises a converter and a control circuit. The converter converts the load signal at a first node to output a load-compensation signal at a second node. The load signal corresponds to an output power provided from the power supply to the load, and the converter includes a low-pass filter coupled between the first and second nodes. The control circuit is coupled to an inductive device via a feedback node, for controlling the output power to make a cross voltage of the inductive device approach a target voltage, based on a feedback voltage at the feedback node. The higher the load-compensation signal the higher the target voltage.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Taiwan Application Serial Number 100132159, filed on Sep. 7, 2011, which is incorporated by reference in its entirety.

BACKGROUND

The present disclosure relates generally to switching-mode power supplies and control methods with regard to primary side control and load compensation.

A power supply need provide a steady output voltage at an output power node to power a load. The regulation of the output voltage is commonly achieved by using detection devices, such as resistors and LT431, at a secondary side to detect the output voltage and then passing the detection result to the power controller at a primary side with the help of a photo coupler. This kind of control means is generally referred to as secondary side control.

To eliminate the need of the detection devices at the secondary side and save the electric power there consumed, primary side control (PSC) is developed. PSC achieves the detection of the output voltage at the primary side, employing the theory of inductance coupling.

FIG. 1demonstrates switching-mode power supply8using PSC. Power supply8includes a flyback topology10, which uses a transformer with primary winding PRM, secondary winding SEC, and auxiliary winding AUX to isolate the primary side from the secondary side. As shown inFIG. 1, the primary and secondary sides have different grounds, isolated by the transformer. By switching power switch15, power controller18controls the energizing and de-energizing of the transformer. During a discharge time TDISwhen the transformer is de-energizing, secondary and auxiliary windings, SEC and AUX, discharge to charge output power node OUT and operation power node VCC, respectively. Because of inductance coupling, during discharge time TDIS, the cross voltage VSECacross secondary winding SEC should be in certain proportion to the cross voltage VAUXacross auxiliary winding AUX. Power controller18detects cross voltage VAUXvia feedback node FB, and voltage-dividing resistors13and14, equivalently detecting cross voltage VSEC, which in a way is substantially equivalent to output voltage VOUTat output power node OUT. Based on feedback voltage VFBat feedback node FB, power controller18modifies compensation voltage VCOMat compensation node COM and accordingly controls the ON time, the OFF time, or the duty cycle of power switch15. Simply put, PSC monitors cross voltage VAUXacross auxiliary winding AUX to regulate output voltage VOUT.

PSC might induce a phenomenon that the regulated output voltage VOUTvaries while load20is changed. It is because that parasitic resistance exists inevitably between output power node OUT and secondary winding SEC, such that output voltage VOUTis somehow smaller than cross voltage VSECand the voltage difference there between increases along with the increase of output current IOUT. In other words, to make output voltage VOUTsubstantially independent from output current IOUT, the target voltages that cross voltages VSECand VAUXare controlled to approach shall increase as load20or output current IOUTincreases, such that the voltage difference between output power node OUT and secondary winding SEC is compensated. This kind of control concept for voltage regulation is generally referred to as load compensation.

Load compensation introduces a positive feedback loop, which, if not well designed, might cause oscillation easily. According to load compensation, for a certain load20, the higher output current IOUT, the higher target voltages that cross voltages VSECand VAUXare controlled to approach. Nevertheless, the higher target voltages also need further higher output current IOUTto support, such that a positive feedback loop is formed. The oscillation that would company with a positive feedback loop should be avoided or damped, however, for good output voltage regulation.

DETAILED DESCRIPTION

The following embodiments of the invention are used in but not limited to power supply8ofFIG. 1. The invention is not limited to isolation structures, for example, the flyback topology exemplified inFIG. 1, and could be used in non-isolation structures, such as boosters. For instance, the invention might be embodied in a power controller, which detects cross voltage VAUXof an auxiliary winding that inductively coupled to a primary winding coupled between an input voltage node and an output voltage node in a booster topology.

FIG. 2demonstrates power controller30adapted for being used in power controller18of power supply8ofFIG. 1according to one embodiment of the invention.

In one embodiment, circuit34determines the beginning of an ON time TON, a period of time when power switch15is turned ON and performs a short circuit. For example, circuit34could detect the complete of de-energizing of the transformer and accordingly set SR register32, to turn on power switch15.

Circuit38substantially determines the beginning of an OFF time TOFF, a period time when power switch15is turned OFF and performs an open circuit. For example, voltage divider36generates limiting voltage VCOMIat node COMI based on compensation voltage VCOMat compensation node COM. When current-sensing signal VCSexceeds limiting voltage VCOMI, circuit38resets SR register32, turning OFF power switch15and making it an open circuit. Accordingly, limiting voltage VCOMIsubstantially determines the peak voltage of current-sensing signal VCS.

Peak detection circuit42provides peak signal VCS-Prepresenting the peak voltage of current-sensing signal VCS. As peak signal VCS-Pcorresponds to the peak current flowing through primary winding PRM, it also corresponds to the output power currently output to load20from power supply8.

At a moment within discharge time TDIS, a short-pulse of signal SSHmakes sample/hold circuit40sample feedback voltage VFBat feedback node FB to hold and provide held voltage VFBINat node FBIN. The comparison result between held voltage VFBINand predetermined voltage VTAR0determines the increase or decrease of compensation voltage VCOM. When power supply8makes output voltage VOUTa substantially constant, compensation voltage VCOMshall remain substantially unchanged over time, and held voltage VFBINshall be very close to, if not the same with, predetermined voltage VTAR0.

Please refer to bothFIGS. 1 and 2, where load-compensation current IOffSetseems to be an offset current draining from feedback node FB to primary ground. As aforementioned, power controller30makes cross voltages VSECand VAUXduring discharge time TDISapproach target voltages, respectively referred to as VSEC-TARand VAUX-TAR, where the ratio of target voltage VSEC-TARto target voltage VAUX-TARshould equal to the turn ratio of secondary winding SEC to auxiliary winding AUX. During discharge time TDISand when output voltage VOUTis substantially stabilized, the following equations should be complied.
VFB=VFBIN=VTAR0;
VFB=VAUX-TAR*R13/(R13+R14)−IOffSet*R13*R14/(R13+R14);
and
VAUX-TAR=IOffSet*R14+VTAR0*(R13+R14)/R13;
where R13and R14represent resistances of resistors13and14, respectively. It can be derived from the last equation above that the higher load-compensation current IOffSetthe higher target voltage VAUX-TARand as a result, the higher target voltage VSEC-TAR.

When output voltage VOUTis substantially stabilized, power supply8provides a steady output power to load20and peak signal VCS-Pis about a constant. The higher peak signal VCS-Pmeans the higher output power. In the meantime, peak signal VCS-Pcorresponds to both current IOSand load-compensation current IOffSet, and the higher load-compensation current IOffSetthe higher target voltage VSEC-TAR. Accordingly, during the steady state when output voltage VOUTis substantially stabilized, the higher output power the higher target voltage VSEC-TAR, achieving load compensation.

Nevertheless, during a load transient when output voltage VOUThas not been stabilized, peak signal VCS-Pmight change dramatically, and low-pass filter60limits the variation rate of load-compensation current IOffSet. Once a signal that exists in a positive feedback loop is limited in view of it variation rate, the possibility of oscillation caused by the positive feedback loop is decreased or eliminated. Accordingly, with undue diligence in circuit design, low-pass filter60might depress or eliminate the oscillation caused by load compensation.

FIG. 3demonstrates peak detection circuit42and voltage-to-current converter64shown inFIG. 2. At the moment when power switch15is turned OFF, the switch in peak detection circuit42is turned OFF, such that peak signal VCS-Pstored on the capacitor substantially equals to the peak voltage of current-sensing signal VCS. Voltage-to-current converter64has an operational amplifier, a NMOS transistor, and a current mirror63, the operation of which can be well derived by persons skilled in the art and is not detailed herein for brevity. Voltage-to-current converter64provides current IOSin proportion to peak signal VCS-P.

FIG. 4demonstrates low-pass filter60shown inFIG. 2. By periodically toggling signal VGATEat gate node GATE, switched-capacitor low-pass filter61low passes the gate voltage at the control gate of NMOS68to provide another gate voltage at the control gate of NMOS66. In the long run when output voltage VOUTis stabilized, the gate voltage of NMOS66should be equal to that of NMOS68, forming a current mirror.

In the embodiment ofFIG. 2, peak signal VCS-Pis used as an output power indicator corresponding to the output power that power supply8provides to load20, and load-compensation current IOffSetis generated according to peak signal VCS-P. In other embodiments, compensation voltage VCOMor limiting voltage VCOMIcould be an output power indicator to generate current IOSand load-compensation current IOffSet.

In an embodiment, converter44that converts peak signal VCS-Pto load-compensation current IOffSetmight have a LPF to first low pass peak signal VCS-P, outputting a filtered result VCS-LP, and a voltage-to-current converter to second convert the filtered result VCS-LPinto load-compensation current IOffSet.

At the beginning of a startup period when, for example, a power supply is just connected to a grid outlet, the power controller of the power supply will deem the load as being heavy no matter what the load actually is, because the output voltage to the load starts from a value much lower than the required one. If load compensation starts at the startup period, load compensation will make target voltages VSEC-TARand VAUX-TARmuch higher during the startup period. The output voltage, as pulled by the much higher target voltage VSEC-TAR, might easily overshoots if the load is light or zero in real, and the stabilization of the output voltage might be adversely delayed.

Comparator70and load-compensation controller62both inFIG. 2could solve the output voltage overshooting caused by load compensation. Basically speaking, during the startup period, comparator70and load-compensation controller62prohibit the execution of load compensation. Only if output voltage VOUTis almost well built, or exceeds a certain level, then load compensation is executed softly, or little by little.

FIG. 5shows waveforms of signals inFIG. 2, corresponding, from top to bottom, held voltage VFBIN, signal SEN, ramp signal SSC, peak signal VCS-P, and load-compensation current IOffSet. Held voltage VFBINis the sampled result from feedback voltage VFBduring discharge time TDIS, substantially in proportion to output voltage VOUTif load compensation is not introduced. Before time point tS, peak signal VCS-Pstays at its maximum because output voltage VOUTis very low, held voltage VFBINgoes up as output power node OUT is steadily charged. In the meantime, held voltage VFBINis lower than predetermined reference voltage VREF, such that signal SENoutput by comparator70is 0 in logic, ramp signal SSCis 0V, load-compensation current IOffSetis forced by load-compensation controller62to be 0A, and, as a result, no load compensation is introduced.

At time point tSwhen held voltage VFBINexceeds predetermined reference voltage VREF, comparator70turns its output to 1 in logic and ramp signal SSCstarts to rise, causing load-compensation current IOffSetto increase slowly. In other words, load compensation is softly introduced and load-compensation current IOffSetis softly or little by little built. At time point tEwhen ramp signal SSCreaches its highest value, load compensation is completely introduced and load-compensation current IOffSetis controlled by peak signal VCS-P. The time period from time point tSto time point tEwhen load compensation is softly introduced is referred to as soft-compensation time TSC.

As shown inFIG. 5, predetermined reference voltage VREFcould be very close to, but smaller than predetermined voltage VTAR0, which as shown inFIG. 2is used to compare with held voltage VFBIN. In another embodiment, predetermined reference voltage VREFis equal to predetermined voltage VTAR0.