Pad input signal processing circuit

A pad input signal processing circuit includes a control unit for setting a level of a pad output terminal to which a first control signal is input in response to a power up signal, and a signal output unit for outputting a command signal in response to a signal of the pad output terminal and a second control signal.

TECHNICAL FIELD

The present disclosure relates to a semiconductor memory and, more particularly, to a pad input signal processing circuit for processing a deep power down mode signal received through a pad in a mobile DRAM.

BACKGROUND

Generally, a semiconductor memory stores data or outputs stored data to an exterior by operating periphery circuits in an active state, and minimizes power consumption by disabling unnecessary periphery circuits in a stand-by state.

In particular, in order to minimize unnecessary power consumption in a stand-by mode, a mobile semiconductor memory enters a deep power down (DPD) mode to stop operations of periphery circuits. There are two ways of entering the deep power down mode, one is by a pad and the other is by a command. A user can select one of these two ways and generally the memory is configured to allow the user to make such selection by fuse cutting.

FIG. 1is a circuit diagram illustrating a conventional pad input signal processing circuit.

Referring toFIG. 1, the conventional pad input signal processing circuit shown therein is configured to enter the DPD mode by a command or a pad, as selected using fuse option.

Referring to the DPD mode entry by a command, a pad input terminal becomes a logic low level through NMOS transistors which are turned on in response to a power supply voltage VDD. Therefore, a signal DPD_PAD which went through an input buffer always becomes a logic low level. A signal CMD_DPD is a signal that becomes a logic high level in the case of entering the DPD mode by a command and a deep power down mode signal is controlled only by the signal CMD_DPD.

Referring to the DPD mode entry by a pad, a fuse connected to the pad input terminal is cut and at the DPD mode entry, a logic high level is applied from an external pin connected to the pad. Since the signal CMD_DPD by a command always maintains a logic low level, the deep power down mode signal is controlled by an external pin.

However, such a conventional technique requires the cutting of a fuse when entering the DPD mode by a pad. If a memory enters the DPD mode by a pad without cutting a fuse, it does not have any operational problem. However, when entering the DPD mode by a pad, there is a problem of current consumption through a fuse and NMOS transistors under the condition that the pad input terminal is in a logic high level. Such unnecessary current consumption is critical in the DPD mode in which current specification is several μA. In addition, since the fuse cutting is post-processed upon the request from an orderer, it is difficult to keep stocks, resulting in late customer response.

SUMMARY

In an aspect of the present disclosure, a pad input signal processing circuit is provided that avoids unnecessary current consumption, such as is present in conventional pad input signal processing circuits, regardless of the way of entering a deep power down mode, while not cutting a fuse.

In an exemplary embodiment, a pad input signal processing circuit includes a control unit for setting a level of a pad output terminal to which a first control signal is input in response to a power up signal, and a signal output unit for outputting a command signal in response to a signal of the pad output terminal and a second control signal.

The first control signal is a deep power down mode entry signal activated by a pad.

The second control signal is a deep power down mode entry signal activated by a command.

The command signal is a deep power down mode signal.

The control unit drives the pad output terminal to a certain logic level when the power up signal is activated.

In another exemplary embodiment, a pad input signal processing circuit includes a pad, an control signal generating unit configured to generate a control signal to control the pad output terminal to which a first control signal is input in response to a power up signal, a current sink unit for driving the pad output terminal in response to an output signal of the control signal generating unit, and a signal output unit for outputting a command signal in response to a signal of the pad output terminal and a second control signal.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Hereinafter, examples and exemplary embodiments of the present disclosure will be described with reference to accompanying drawings. However, the examples and embodiments are for illustrative purposes only and are not intended to limit the scope of the invention.

FIG. 2is a block diagram illustrating a pad input signal processing circuit (2), in an embodiment of this disclosure, andFIG. 3is a circuit diagram illustrating a pad input signal processing circuit (3), similar to the pad input signal processing circuit2ofFIG. 2except that a buffer (30) is provided additionally in the pad input signal processing circuit3.

Referring toFIGS. 2 and 3, each of the pad input signal processing circuits (2,3) includes a pad10, a control unit20for controlling a pad output terminal A to which a first control signal PAD_DPD is input in response to a power up signal PowerUp, and a signal output unit40for outputting a deep power down signal DPD in response to a signal of the pad output terminal A and a second control signal CMD_DPD.

Here, the first control signal PAD_DPD is a signal which is activated at the time of entering the deep power down mode by a pad, the second control signal CMD_DPD is a signal which is activated at the time of entering the deep power down mode by a command, and the power up signal PowerUp is a signal which is transited to a logic low level when a power supply voltage VDD increases to a high enough level at the power up.

The control unit20includes the control signal generating unit22for performing a logic operation in response to the first control signal PAD_DPD and the power up signal PowerUp, and a current sink unit21which is driven in response to an output signal of the control signal generating unit22. When the power up signal PowerUp is activated, the current sink unit21is turned on, and when the first control signal PAD_DPD is activated, the current sink unit21is turned off.

The control signal generating unit22includes a first logic element ND1for performing a NAND operation on the first control signal PAD_DPD and an inverted signal of the power up signal, and a second logic element IV1for inverting and outputting an output signal NCTRL of the first logic element ND1.

The current sink unit21includes a plurality of first NMOS transistors N2, N5, N6, N7and N8which are connected in series with one another and performs pull-down driving in response to the output signal NCTRL of the first logic element ND1, and a first PMOS transistor P1which is connected in series with the first NMOS transistors and pull-down drives the pad output terminal A in response to an output signal of the second logic element IV1.

A buffer30is provided in the pad input signal processing circuit3ofFIG. 3to buffer the control signal PAD_DPD between the control unit20and the signal output unit40. More specifically, the buffer30buffers an output signal of the pad output terminal A and outputs the output signal to the signal output unit40.

The signal output unit40includes a for performing an OR operation in response to the output signal of the input buffer30and the second control signal CMD_DPD and outputting a deep power down mode signal DPD. That is, the signal output unit40activates and outputs the deep power down mode signal DPD when the first control signal PAD_DPD or the second control signal CMD_DPD is activated.

FIG. 4is a circuit diagram illustrating a pad input signal processing circuit according to another exemplary embodiment of this disclosure. The current sink unit21ofFIG. 3is driven in response to the output signal NCTRL of the first logic element ND1, but the current sink unit may also be configured to constantly perform a pull-down driving in response to the power supply voltage VDD as shown inFIG. 4.

Operation of a pad input signal processing circuit according to the embodiments of this disclosure configured as described above will be discussed in detail with reference to the accompanying drawings.

First, operation when the deep power down mode is entered through a command is as follows.

Since the pad10is not connected to anything, at the time of the power up, the first PMOS transistor P1connected to the pad output terminal A is turned on in response to an inverted signal of the output signal NCTRL of the first logic element ND1, and the first NMOS transistors are turned on in response to the output signal NCTRL of the first logic element ND1. Then the pad output terminal A is set to a logic low level.

Accordingly, this disclosure is controlled to enter or exit from the deep power down mode by the command signal CMD_DPD.

Next, operation when the deep power down mode is entered through a pad is as follows.

In the beginning, the pad output terminal A is set to a logic low level by the power up signal. Thereafter, the power up is completed, and if a logic high level is applied to the pad, the first logic element ND1outputs a logic low level signal.

Then the first NMOS transistors N2, N5, N6, N7and N8are turned off in response to the output signal NCTRL of the first logic element ND1, and the first PMOS transistor P1is turned off in response to an inverted signal of the output signal NCTRL of the first logic element ND1.

Therefore, the first NMOS transistors N2, N5, N6, N7and N8and the first PMOS transistor P1are controlled to be turned off at the time of entering the deep power down mode by a pad, thus preventing unnecessary current consumption which occurs in the prior art circuit.

As described above, the pad input signal processing circuit of this disclosure can avoid unnecessary current consumption, regardless of the way of entering the deep power down mode. In addition, by removing a fuse, the pad input signal processing circuit of this disclosure does not follow the pre-order and post-process method and can provide an identical wafer in the pre-process regardless of the required deep power down mode entry option, thereby making it easy to manage stocks and reducing considerable time in responding to customers' order.

The present disclosure claims priority to Korean application 10-2008-0052693, filed on Jun. 4, 2008, the entire contents of which are incorporated herein by reference.