Vertical memory device and method of fabricating the same

A vertical memory device includes a substrate with a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes parallel to the substrate in the cell array and word line contact regions, the gate electrodes being stacked and spaced apart in a direction perpendicular to the substrate, a channel structure through the gate electrodes in the cell array region, the channel structure being electrically connected to the substrate, a dummy channel structure through the gate electrodes in the word line contact region, the dummy channel structure being spaced apart from the substrate, and a conductive line parallel to the substrate and electrically connected to a first gate electrode, the conductive line crossing at least a portion of an extension of the dummy channel structure in the perpendicular direction.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2016-0104982, filed on Aug. 18, 2016, in the Korean Intellectual Property Office, and entitled: “Vertical Memory Device and Method of Fabricating the Same,” is incorporated by reference herein in its entirety.

BACKGROUND

Embodiments relate to a memory device and a method of fabricating the same, and more particularly, to a vertical memory device and a method of fabricating the same.

2. Description of the Related Art

Consumers demand memory devices having excellent performance and low prices. To this end, there is a need to increase the integration degree of memory devices. Recently, vertical memory devices, in which memory cells are vertically stacked on a substrate, are being developed to produce highly integrated memory devices.

SUMMARY

According to embodiments, there is provided a vertical memory device including a substrate including a cell array region, a word line contact region, and a peripheral circuit region, gate electrodes configured to extend substantially parallel to a top surface of the substrate in the cell array region and the word line contact region and to be stacked while being spaced apart from one another in a first direction, wherein the first direction is a direction that is substantially perpendicular to the top surface of the substrate, a channel structure configured to pass through the gate electrodes in the first direction in the cell array region and to be electrically connected to the substrate, a dummy channel structure configured to pass through the gate electrodes in the word line contact region in the first direction and to be spaced apart from the substrate in the first direction, and a conductive line configured to be substantially parallel to the top surface of the substrate in the peripheral circuit region and the word line contact region and to be electrically connected to a first gate electrode, which is any one of the gate electrodes, wherein the conductive line crosses at least a portion of an extension of the dummy channel structure in the first direction.

According to other embodiments, there is provided a vertical memory device including a substrate with a cell array region and a word line contact region defined thereon, gate electrodes configured to extend substantially parallel to a top surface of the substrate in the cell array region and the word line contact region and to be stacked while being spaced apart from one another in a first direction, wherein the first direction is a direction that is substantially perpendicular to the top surface of the substrate, a channel structure configured to pass through the gate electrodes in the first direction in the cell array region and to be electrically connected to the substrate, a dummy channel structure configured to pass through the gate electrodes in the word line contact region in the first direction and to be spaced apart from the substrate in the first direction, and an insulating structure between the dummy channel structure and the substrate, and a conductive line configured to be substantially parallel to the top surface of the substrate in the word line contact region and to be electrically connected to a first gate electrode, which is any one of the gate electrodes, wherein the conductive line is electrically connected to the dummy channel structure.

According to other embodiments, there is provided a vertical memory device including gate electrodes extending substantially parallel to a top surface of a substrate, the gate electrodes being stacked on the substrate while being spaced apart from one another in a direction normal to the top surface of the substrate, a channel structure through the gate electrodes and normal to the top surface of the substrate, the channel structure being electrically connected to the substrate, a dummy channel structure through the gate electrodes and normal to the top surface of the substrate, an insulating structure between the dummy channel structure and the substrate, and a conductive line extending parallel to the top surface of the substrate and overlapping at least a portion of a top of the dummy channel structure, the channel structure electrically connecting the conductive line to the substrate.

DETAILED DESCRIPTION

Hereinafter, example embodiments will be described in detail with reference to the attached drawings. In the drawings, like elements are denoted by like reference numerals, and the repeated explanations thereabout will be skipped.

FIG. 1shows a schematic block diagram of a vertical memory device according to an example embodiment.

Referring toFIG. 1, a vertical memory device according to the present embodiment may include a cell array region CAR, a word line contact region WCTR, and a peripheral circuit region PERI. In the cell array region CAR, memory cells, which are three-dimensionally arranged, and bit lines and word lines, which are electrically connected to the memory cells, may be formed. The word line contact region WCTR may be disposed between the cell array region CAR and the peripheral circuit region PERI, and, in the word line contact region WCTR, wiring plugs and conductive lines, which connect memory cells with peripheral circuits, may be formed. In the peripheral circuit region PERI, peripheral circuits, which drive memory cells and read data stored in memory cells, may be formed. In one embodiment, the peripheral circuit region PERI may include a word line driver, a sense amplifier, a row decoder, a column decoder, and a control circuit.

FIG. 2shows a portion of a circuit diagram of the cell array region CAR according to an example embodiment.

Referring toFIG. 2, the cell array region CAR of the vertical memory device according to the present embodiment may include a common source line CSL, bit lines BL, and a plurality of cell strings CSTR between the common source line CSL and the bit lines BL.

The bit lines BL are two-dimensionally arranged, and a plurality of cell strings CSTR are connected to each bit line BL in parallel. The cell strings CSTR may be commonly connected to a common source line CSL. That is, a plurality of cell strings CSTR may be disposed between a plurality of bit lines BL and a common source line CSL. In one example embodiment, a plurality of common source lines CSL may be two-dimensionally arranged. In this regard, the same voltage amplitude may be applied to the common source lines CSL, or different voltage amplitudes may be applied to the common source lines CSL.

Each of the cell strings CSTR may include a ground selection transistor GST connected to a common source line CSL, a string selection transistor SST connected to a bit line BL, and a plurality of memory cell transistors MCT between the ground selection transistor GST and the string selection transistor SST. The string selection transistor SST, the memory cell transistors MCT, and the ground selection transistor GST may be connected in series.

Referring toFIG. 2, one ground selection transistor GST and one string selection transistor SST are connected to n memory cell transistors MCT connected in series. However, in one embodiment, a plurality of ground cell transistors GST or a plurality of string selection transistors SST may be connected to n memory cell transistors MCT connected in series.

The common source line CSL may be commonly connected to sources of ground cell transistors GST. A ground selection line GSL, a plurality of word lines WL0through WL3, and a string selection line SSL, which are between the common source line CSL and the bit lines BL, may be respectively used as a gate electrode of the ground selection transistor GST, gate electrodes of memory cell transistors MCT, and a gate electrode of the string selection transistor SST. Each of the memory cell transistors MCT may include a data storage element.

A drain terminal of the string selection transistor SST may be connected to the bit line BL. When a signal is applied to a gate electrode of the string selection transistor SST through the string selection line SSL, the signal applied through a bit line BL is transmitted in series to the memory cell transistors MCT, thereby enabling reading or writing data. When a signal is applied to a gate terminal of the ground selection transistor GST through a ground selection line GSL, an erase operation may be performed in which charges stored in the memory cell transistors MCT may be completely removed.

FIG. 3Ashows a plan view of a vertical memory device10aaccording to an example embodiment.FIG. 3Bshows a cross-sectional view taken along lines I-I′, II-II′, and III-III′ inFIG. 3A.

Referring toFIGS. 3A and 3B, a first direction (z direction) is substantially perpendicular, e.g., normal, to a top surface of a substrate100, and a second direction (x direction) and a third direction (y direction) are parallel to the top surface of the substrate100, wherein the second direction crosses the third direction. In one embodiment, the second direction may be substantially perpendicular to the third direction, and the second direction may cross the third direction. The second direction and the third direction may substantially be perpendicular to the first direction. In the drawings herein, an arrow direction and a direction opposite thereto are considered as being the same direction. The descriptions about directions are commonly applied to drawings used in the present specification.

Referring toFIGS. 3A and 3B, the vertical memory device10aaccording to an example embodiment may include the cell array region CAR, the word line contact region WCTR, and the peripheral circuit region PERI described previously with reference toFIGS. 1-2, all constituting the substrate100. In the cell array region CAR, gate electrodes220, channel structures200a, common source lines CSL, and bit lines BL may be disposed. In the word line contact region WCTR, dummy channel structures200b, first wiring plugs245a, and conductive lines260may be disposed. In the peripheral circuit region PERI, peripheral transistors110, second wiring plugs245b, and the conductive lines260may be disposed.

The substrate100may include a device isolation film102defining an active region. The substrate100may include a material having semiconductor characteristics, e.g., a silicon wafer. The gate electrodes220and interlayer insulating films140may surround side walls of the channel structures200a, and may extend from the cell array region CAR to the word line contact region WCTR. In the word line contact region WCTR, the gate electrodes220may be arranged to form a continuous stair structure. Accordingly, horizontal lengths of the gate electrodes220may vary. The gate electrodes220may have shorter horizontal lengths away, i.e., as a distance increases, from the substrate100. In one embodiment, from among the gate electrodes220, the lowermost gate electrode220may have the longest horizontal length, and the uppermost gate electrode220may have the shortest horizontal length. The gate electrodes220may be insulated from one another by the interlayer insulating films140.

The gate electrodes220may include at least one ground selection gate electrode, a plurality of memory cell gate electrodes, and a string selection gate electrode. A ground selection gate electrode may be the lowermost gate electrode220, and the string selection gate electrode may be the uppermost gate electrode. The memory cell gate electrodes may be stacked between the ground selection gate electrode and the string selection gate electrode. Referring toFIG. 3B, there are four (4) memory cell gate electrodes illustrated therein. However, embodiments are not limited thereto, e.g., eight (8), sixteen (16), thirty-two (32), or sixty-four (64) memory cell gate electrodes may be formed between the ground selection gate electrode and the string selection gate electrode.

Thickness of the memory cell gate electrodes may be substantially identical. Thicknesses of the ground selection gate electrode and the string selection gate electrode may be different from those of the memory cell gate electrodes. In one embodiment, the thicknesses of the ground selection gate electrode and the string selection gate electrode may be greater than those of the memory cell gate electrodes. In example embodiments, the memory cell gate electrodes may be word lines. The ground selection gate electrode may be a ground selection line, and the string selection gate electrode may be a string selection line. The gate electrodes220may include, e.g., tungsten, copper, or metal silicide.

Thicknesses of the interlayer insulating films140may not be identical to one another, e.g., the lowermost interlayer insulating film140may be thicker than other interlayer insulating films140. The interlayer insulating films140may include an insulating material, e.g., silicon oxide, silicon nitride, silicon oxynitride, or the like.

In the cell array region CAR, the gate electrodes220and the interlayer insulating films140may be alternately stacked. The channel structures200amay pass through the stacked gate electrodes220and the interlayer insulating films140in the first direction (z direction) and contact semiconductor patterns190. The memory cell transistors MCT and the string selection transistor SST may be disposed where the channel structures200across the gate electrodes220. The ground selection transistor GST may be disposed where the semiconductor patterns190cross the gate electrodes220.

Each of the channel structures200amay include a first dielectric film pattern201a, a first vertical channel pattern203a, and a first filling insulating film pattern205a. The first vertical channel pattern203amay be electrically connected to the substrate100via the semiconductor pattern190. In one or more embodiments, the semiconductor patterns190may be disposed between the channel structures200aand the substrate100, and may be configured to electrically connect the channel structures200awith the substrate100. Each of the channel structures200amay have a bottom surface that lies at a higher level than a top surface of the lowermost gate electrode220. Contact pads207amay be formed on top surfaces of the channel structures200a. The contact pads207amay each include, e.g., impurity-doped poly silicon.

Referring toFIG. 3A, in a top view of the channel structures200a, the channel structures200amay form rows and columns, thereby forming a two-dimensional arrangement. The channel structures200amay be arranged in a zig-zag shape. In one or more embodiments, the rows or columns of the channel structures200amay be alternately arranged and be spaced apart from one another. The common source line CSL may pass through the gate electrodes220and the interlayer insulating films140in the first direction (z direction). The common source line CSL may include, for example, a conductive material, e.g., tungsten (W). An impurity region211may be where the substrate100contacts the common source line CSL, and an insulating spacer225may be disposed on side walls of the common source line CSL. The impurity region211may include an impurity, e.g., P or As, implanted into the substrate100.

The common source line CSL may extend vertically through the gate electrodes220and the interlayer insulating films140, and contact the impurity region211. The common source line CSL may have a dam-like shape. In one embodiment, in a top view of the common source line CSL, the common source line CSL may have a line or bar-shape. The insulating spacer225may be formed between the common source line CSL and the gate electrodes220. The insulating spacer225may be disposed on side walls of the common source line CSL. The insulating spacer225may insulate the common source line CSL from the gate electrodes220. The insulating spacer225may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or other insulating materials.

The first wiring plugs245amay extend in the first direction (z direction) through a top insulating film175or through both the top insulating film175and a bottom insulating pattern165, and may electrically connect any one of the gate electrodes220with the conductive line260. The second wiring plugs245bmay extend in the first direction (z direction) through the top insulating film175and a peripheral insulating film120, and may electrically connect the conductive lines260with the peripheral transistors110formed in the peripheral circuit region PERI.

The first wiring plugs245amay be connected to the string selection gate electrode, the memory cell gate electrodes, and the ground selection gate electrode. Referring toFIG. 3A, the first wiring plugs245amay be arranged in a row on the gate electrodes220in the word line contact region WCTR. The second wiring plugs245bmay be connected to a peripheral gate electrode112and a source/drain region113of each of the peripheral transistors110in the peripheral circuit region PERI.

In this regard, the first wiring plugs245aand the second wiring plugs245bmay include, for example, a conductive material, e.g., tungsten. Top surfaces of the first wiring plugs245a, the second wiring plugs245b, and the common source line CSL may lie at the same level. This is because, as to be described later, the first wiring plugs245a, the second wiring plugs245b, and the common source line CSL may be formed by an etch-back process or a chemical mechanical polishing (CMP) process.

The dummy channel structures200bmay have a shape and structure that are similar to those of the channel structures200a. In one embodiment, each of the dummy channel structures200bmay include a second dielectric pattern201b, a second vertical channel pattern203b, and a second filling insulating film pattern205b. Top surfaces of the dummy channel structures200bmay lie at the same level as top surfaces of the channel structures200a. The dummy channel structures200bmay contact the device isolation film102of the word line contact region WCTR through the gate electrodes220and the interlayer insulating films140. Bottom surfaces of the channel structures200amay be farther away from the top surface of the substrate100than bottom surfaces of the dummy channel structures200b. In one embodiment, a length of each of the channel structures200ain the first direction may be less than that of each of the dummy channel structures200bin the first direction. The bottom surfaces of the dummy channel structures200bmay lie at a lower level than the bottom surfaces of the channel structures200a.

Referring toFIG. 3A, in a top view of the dummy channel structures200b, the dummy channel structures200bpassing through the gate electrodes220are arranged in rows and columns in such a manner that four dummy channel structures200bsurround each of the first wiring plugs245aconnected to the gate electrodes220. However, embodiments are not limited thereto.

Dummy contact pads207bmay be formed on the top surfaces of the dummy channel structures200b. The composition of the dummy contact pads207bmay be substantially the same as the composition of the contact pads207a. The top surfaces of the dummy contact pads207bmay lie at the same level as the top surfaces of the contact pads207a. In this regard, the top surfaces of the dummy contact pads207bmay lie at the same level as top surfaces of the first wiring plugs245a, the second wiring plugs245b, and the common source line CSL.

The semiconductor patterns190may protrude from the substrate100and may be disposed between the channel structures200aand the substrate100, in the cell array region CAR. Top surfaces of the semiconductor patterns190may lie at a higher level than the top surface of the lowermost gate electrode220. The semiconductor patterns190may contact the first vertical channel pattern203aof each of the channel structures200a. The first vertical channel pattern203amay be electrically connected to the substrate100through the semiconductor pattern190. The semiconductor patterns190may be formed by a selective epitaxial growth (SEG) process that uses the top surface of the substrate100as a seed. Accordingly, the semiconductor patterns190may be formed only within channel holes180aexposing the top surface of the substrate100, not within dummy holes180bformed on the device isolation film102.

A bottom gate insulating film101may be disposed between the lowermost gate electrode220and the substrate100, in the cell array region CAR. The bottom gate insulating film101may include an insulating material, e.g., silicon oxide, silicon nitride, silicon oxynitride, or the like. A thickness of the bottom gate insulating film101in the first direction (z direction) may be less than that of each of the interlayer insulating films140in the first direction.

The bottom insulating pattern165may be disposed in the word line contact region WCTR. In some cases, a portion of the bottom insulating pattern165may extend to the peripheral circuit region PERI. In the word line contact region WCTR, the bottom insulating pattern165may be disposed on top or side surfaces of the interlayer insulating films140and the gate electrodes220and a side surface of the peripheral insulating film120, and on the device isolation film102. A top surface of the bottom insulating pattern165and a top surface of the peripheral insulating film120may form a single plane. The bottom insulating pattern165may include an insulating material, such as silicon oxide.

The peripheral transistors110may form a peripheral circuit on the substrate100in the peripheral circuit region PERI. Each of the peripheral transistors110may include a peripheral gate insulating pattern111, a peripheral gate electrode112, a source/drain region113, and gate spacers115. The peripheral transistors110may be covered by the peripheral insulating film120. The top insulating film175may be formed on top and side surfaces of the interlayer insulating films140and the gate electrodes220in the word line contact region WCTR, and on the bottom insulating pattern165and the peripheral insulating film120. In one embodiment, the top insulating film175may surround side surfaces of the dummy channel structures200band the first and second wiring plugs245aand245b. In one embodiment, the first and second wiring plugs245aand245band the dummy channel structures200bmay vertically pass through the top insulating film175. The top insulating film175and the uppermost interlayer insulating film140may form a single plane. That is, the top surface of the top insulating film175may lie at the same level as the top surface of the interlayer insulating film140, thereby forming a continuous plane.

The conductive lines260may be disposed in the word line contact region WCTR and the peripheral circuit region PERI. The conductive lines260may extend on the first wiring plugs245a, the second wiring plugs245b, the uppermost interlayer insulating film140, and the top insulating film175, in a direction parallel to the top surface of the substrate100. The conductive lines260may each have, e.g., a curved structure or a bent structure. In one embodiment, the conductive lines260may each have a portion extending in the second direction (x direction) or a portion extending in the third direction (y direction), as illustrated inFIG. 3A. That is, the conductive lines260may each have a two-directional structure.

The conductive lines260may be electrically connected to the gate electrodes220through the first wiring plugs245aand to the peripheral transistors110through the second wiring plugs245b. In this regard, the conductive lines260may cross at least a portion of each of the dummy channel structures200bextending in the first direction (z direction). In one embodiment, the conductive lines260may cross at least a portion of each of the dummy contact pads207bextending in the first direction (z direction). Top surfaces of the dummy contact pads207band bottom surfaces of the conductive lines260may lie at the substantially same level. In one or more embodiments, the conductive lines260may contact the dummy contact pads207b. In one or more embodiments, the conductive lines260may be directly connected to the dummy contact pads207b. As described above, the top surfaces of the first wiring plugs245a, second wiring plugs245b, common source line CSL, dummy contact pads207b, uppermost interlayer insulating film, and top insulating film175may lie at the same level as bottom surfaces of the conductive lines260.

As to be described in connection withFIG. 5Q, since the common source line CSL and the first and second wiring plugs245aand245bare formed at the same time, e.g., simultaneously, a top surface of the common source line CSL and the top surfaces of the first and second wiring plugs245aand245blie at the same level. Compared to a related method, e.g., when a common source line is formed before formation of the first and second wiring plugs, the distance between the top surfaces of the dummy contact pads207band the bottom surfaces of the conductive lines260in the first direction (z direction) may be reduced. Accordingly, when the conductive lines260cross a portion of the dummy channel structures200b, the conductive lines260may be potentially short-circuited with the substrate100through the dummy contact pads207band the dummy channel structures200b.

Furthermore, when each of the conductive lines260has a curved structure or a bent structure, or when the conductive lines260have a two-directional structure extending in the second direction (x direction) and the third direction (y direction), a bent portion of each of the conductive lines260may undergo corner-rounding. Accordingly, for the conductive lines260not to cross a portion of each of the dummy channel structures200bextending in the first direction (z direction), there is a limitation on designing of a conductive line having a two-directional structure.

Therefore, according to one or more embodiments, the dummy channel structures200bare formed on the device isolation film102, e.g., the device isolation film102completely separates bottoms of the dummy channel structures200bfrom the substrate100. Accordingly, the semiconductor patterns190, which are formed by SEG, may be formed only in the channel holes180aof the cell array region CAR, not in the dummy holes180bof the word line contact region WCTR. Further, the dummy channel structures200bare spaced apart from the substrate100with the device isolation film102therebetween. Thus, even when the conductive lines260cross a portion of each of the dummy channel structures200bthat extends in the first direction (z direction), the conductive lines260may not be short-circuited with respect to the substrate100. In other words, even when the conductive lines260are configured to be electrically connected to the dummy channel structures200bthrough the dummy contact pads207b, the conductive lines260may not be short-circuited with respect to the substrate100, e.g., due to the separation therefrom via the device isolation film102. Accordingly, the conductive lines260may cross a portion of each of the dummy contact pads207bextending in the first direction (z direction). Therefore, the conductive lines260, i.e., the conductive lines260in the word line contact region WCTR, may have a higher degree of freedom

The interlayer insulating film235may be formed on the uppermost interlayer insulating film140and the top insulating film175, the interlayer insulating film235covering the channel structures200a, the common source line CSL, and the dummy channel structures200b. The top interlayer insulating film235may surround side surfaces of bit line plugs240. In one embodiment, the bit line plugs240may vertically pass through the top interlayer insulating film235. The top interlayer insulating film235may surround side surfaces and top surfaces of the conductive lines260.

The bit lines BL may be formed on the top interlayer insulating film235. The bit line plugs240may be disposed between the bit lines BL and the channel structures200a. The bit line plugs240may electrically connect the bit lines BL with the channel structures200a. The bit lines BL and the bit line plugs240may each include a conductive material, e.g., doped silicon, metal silicide, or metal.

FIG. 4Ashows a plan view of a vertical memory device10baccording to an example embodiment.FIG. 4Bshows a cross-sectional view taken along lines I-I′ and II-II′ illustrated inFIG. 4A.

Referring toFIGS. 4A and 4B, the vertical memory device10baccording to the present embodiment may include the cell array region CAR, the word line contact region WCTR, and the peripheral circuit region PERI on the substrate100. The substrate100may include a first substrate100aand a second substrate100b. The first substrate100amay be disposed under the second substrate100b. The peripheral circuit region PERI may be disposed on the first substrate100a, and the cell array region CAR and the word line contact region WCTR may be disposed on the second substrate100b. The peripheral transistors110for forming a peripheral circuit may be disposed on the first substrate100a. In this case, each of the peripheral transistors110may include the peripheral gate insulating pattern111, the peripheral gate electrodes112, the source/drain region113, and the gate spacer115. A first peripheral insulating film120bmay be disposed on the first substrate100ahaving the peripheral transistors110. Peripheral conductive lines116and a second peripheral insulating film120amay be disposed on the first peripheral insulating film120bto electrically connect the peripheral transistors110each other.

The peripheral transistors110for forming a peripheral circuit may be formed on the first substrate100a, and the resultant structure is covered by the peripheral insulating film120, and then, the second substrate100bmay be formed on the peripheral insulating film120. The second substrate100bmay include the device isolation film102for defining an active region. Elements formed on the second substrate100bin the cell array region CAR and the word line contact region WCTR are the same as elements that have been described in connection withFIG. 3A, and accordingly, descriptions thereof will be skipped herein.

Referring toFIG. 4B, only one of the peripheral conductive lines116is connected to any one of the second wiring plugs245b. However, in one or more embodiments, the peripheral conductive lines116may be connected to the second wiring plugs245b, respectively.

FIGS. 5A to 5Sshow cross-sectional views taken along lines I-I′, and illustrated inFIG. 3Ato explain stages in a method of fabricating a vertical memory device according to an example embodiment.

Referring toFIG. 5A, the device isolation film102may be formed in the substrate100to define an active region. The device isolation film102may be formed by performing a shallow trench isolation (STI) process. The STI process may include forming isolation trenches in the substrate100and filling the isolation trenches with an insulating material, e.g., silicon oxide. The substrate100may include a material having semiconductor characteristics, e.g., a silicon wafer. The substrate100may include the cell array region CAR, the peripheral circuit region PERI, and the word line contact region WCTR.

Referring toFIG. 5B, the peripheral transistors110may be formed in the peripheral circuit region PERI. Each of the peripheral transistors110may include the peripheral gate electrode112, the peripheral gate insulating pattern111, the source/drain region113, and the gate spacers115. The peripheral insulating film120and a peripheral sacrificial film125may be formed to cover the substrate100in the peripheral circuit region PERI.

In one example embodiment, forming of peripheral circuits may include forming a word line driver, which has been described in connection withFIG. 1, a sense amplifier, a low decoder, a column decoder, and a control circuit. In one embodiment, as illustrated inFIG. 5B, the peripheral transistors110constituting peripheral circuits may be formed on the substrate100in the peripheral circuit region PERI in the following manner. A peripheral gate insulating film and a peripheral gate film are sequentially stacked on the substrate100. The stack structure of the peripheral gate insulating film and the peripheral gate film are patterned to form the peripheral gate electrodes112and the peripheral gate insulating patterns111. The peripheral gate electrodes112may be formed by using, e.g., impurity-doped poly silicon or a metal material. The peripheral gate insulating pattern111may include, e.g., silicon oxide that is formed by a thermal oxidation process. Then, the source/drain region113and the gate spacer115may be formed on or in a portion of the substrate100exposed by the peripheral gate electrodes112.

The peripheral insulating film120may be formed by providing an insulating material on the surface of the substrate100and planarizing the resultant structure. In one embodiment, the peripheral insulating film120may include, e.g., silicon oxide. The peripheral sacrificial film125may be provided on the peripheral insulating film120. The peripheral sacrificial film125may include a material having etch selectivity with respect to the peripheral insulating film120. In one embodiment, the peripheral sacrificial film125may include, e.g., silicon nitride, silicon oxynitride, silicon carbide, and silicon oxy carbide.

The peripheral insulating film120and the peripheral sacrificial film125may be patterned to remain only within the peripheral circuit region PERI. Accordingly, the peripheral insulating film120and the peripheral sacrificial film125may expose the substrate100corresponding to the cell array region CAR and the device isolation film102corresponding to the word line contact region WCTR.

Referring toFIG. 5C, a bottom stack structure150may be formed on the surface of the substrate100with the peripheral transistors110formed thereon. In example embodiments, the bottom stack structure150may be formed in the cell array region CAR, the word line contact region WCTR, and the peripheral circuit region PERI. The bottom stack structure150may be conformal to the surface of the substrate100with the peripheral insulating film120and the peripheral sacrificial film125thereon. The bottom stack structure150may cover a side wall of the peripheral insulating film120and a top surface of the peripheral sacrificial film125.

The bottom stack structure150may include the interlayer insulating films140and a plurality of sacrificial films130. The interlayer insulating films140and the sacrificial films130may be alternately, repeatedly stacked by a deposition process.

The interlayer insulating films140may each include a material that shows high etch selectivity with respect to a material in the sacrificial films130during wet etch. In one embodiment, the interlayer insulating films140may include at least one of, e.g., silicon oxide and silicon nitride, and the sacrificial films130may be selected from, e.g., a silicon film, a silicon oxide film, a silicon carbide, and a silicon nitride film, each having etch selectivity with respect to the interlayer insulating films140.

A cell sacrificial film145may be formed on a top portion of the bottom stack structure150. The cell sacrificial film145may include the same material as that in the peripheral sacrificial film125. The cell sacrificial film145may include an insulating material that has etch selectivity with respect to the interlayer insulating films140or sacrificial films130. In one embodiment, the cell sacrificial film145may include at least one of, e.g., silicon, silicon oxide, silicon oxynitride, silicon carbide, and silicon oxy carbide. In example embodiments, when the cell sacrificial film145is formed on the interlayer insulating films140each including a silicon oxide film, the sacrificial films130may be formed by using a silicon nitride film.

Before forming the bottom stack structure150, the bottom gate insulating film101including a thermal oxidation film may be formed on the substrate100. Since the bottom gate insulating film101is formed by a thermal oxidation process, the bottom gate insulating film101may be formed in the cell array region CAR exposing the surface of the substrate100, and a thickness of the bottom gate insulating film101in the first direction (z direction) may be less than that of each of the interlayer insulating films140.

Referring toFIG. 5D, the bottom stack structure150is patterned to form a bottom cell structure152on the substrate100in the cell array region CAR. The bottom cell structure152may have a stair-like structure obtained by patterning the bottom stack structure150a plurality of times. The bottom cell structure152may extend from the cell array region CAR to the word line contact region WCTR and may have a stair-shaped contact portion. As described above, since the bottom cell structure152has a stair-like structure, ends of the interlayer insulating films140and sacrificial films130may be located in the word line contact region WCTR. The interlayer insulating films140and the sacrificial films130may have a smaller area in a direction being away from the substrate100. In other words, away from the substrate100, side surfaces of the sacrificial films130and interlayer insulating films140may be farther away from the peripheral circuit region PERI.

In one example embodiment, due to the patterning process of the bottom stack structure150, a portion of the device isolation film102in the word line contact region WCTR being adjacent to the peripheral circuit region PERI may be exposed. In one embodiment, due to the patterning of the bottom stack structure150, the peripheral sacrificial film125and the peripheral insulating film120in the peripheral circuit region PERI may be exposed.

Referring toFIG. 5E, a bottom insulating film160covering the bottom cell structure152, the device isolation film102, the peripheral sacrificial film125, and the peripheral insulating film120may be formed.

The bottom insulating film160may be formed by chemical mechanical deposition (CVD), having a conformal structure to the resultant structure on the substrate100in the cell array region CAR, the word line contact region WCTR, and the peripheral circuit region PERI. The bottom insulating film160may be formed by using a material that has etch selectivity with respect to the sacrificial films130and cell sacrificial film145of the bottom cell structure152, and the peripheral sacrificial film125.

In one embodiment, the bottom insulating film160may be the top insulating film175and the top interlayer insulating film235. The bottom insulating film160may include, e.g., silicon nitride, silicon oxynitride, or a material having low permittivity.

Referring toFIG. 5F, the bottom insulating film160may be planarized by a planarizing process using the cell sacrificial film145and the peripheral sacrificial film125as a planarization stopper. Due to the planarizing process, local steps of the bottom insulating film160may be removed, thereby forming a planarized bottom insulating pattern165between the bottom cell structure152and the peripheral insulating film120.

The bottom insulating film160may be planarized by, e.g., CMP. When the CMP process is performed on the bottom insulating film160, the cell sacrificial film145may prevent etching of the interlayer insulating film140disposed thereunder, and the peripheral sacrificial film125may prevent etching of the peripheral insulating film120.

Referring toFIG. 5G, the cell sacrificial film145and the peripheral sacrificial film125may be removed. Accordingly, the bottom cell structure152, the bottom insulating pattern165, and the peripheral insulating film120may have a common top surface.

In one embodiment, the cell sacrificial film145and the peripheral sacrificial film125may be removed by an anisotropic or isotropic etch process using an etch recipe that has etch selectivity with respect to the interlayer insulating films140of the bottom cell structure152, the bottom insulating pattern165, and the peripheral insulating film120. In example embodiments, when the cell sacrificial film145and the peripheral sacrificial film125each includes a silicon nitride film, an etchant including a phosphoric acid may be used for an isotropic etch process.

Referring toFIG. 5H, a top stack structure170may be formed on the bottom cell structure152, the bottom insulating pattern165, and the peripheral insulating film120. Like the bottom stack structure150(seeFIG. 5C), the top stack structure170may include a plurality of interlayer insulating films140and a plurality of sacrificial films130, and may be formed over the surface of the substrate100. The interlayer insulating films140and the sacrificial films130may be alternately, repeatedly stacked by a deposition process.

Referring toFIG. 5I, the top stack structure170may be patterned to form a top cell structure172on the bottom cell structure152. The top cell structure172may be formed by patterning the top stack structure170a plurality of times. Due to the patterning of the top stack structure170, the top stack structure170is removed from the peripheral circuit region PERI and the word line contact region WCTR, thereby exposing the bottom insulating pattern165and the peripheral insulating film120.

The top cell structure172may extend from the cell array region CAR to the word line contact region WCTR, and may have a stair-shaped contact portion. In the word line contact region WCTR, a contact portion of the top cell structure172and a contact portion of the bottom cell structure152may each have a stair-like shape. The contact portion of the top cell structure172contacts the first wiring plug245a(seeFIG. 5Q) that is to be formed in the subsequent process, and is electrically connected to the conductive lines260. In an example embodiment, in the cell array region CAR, the number of sacrificial films130constituting the bottom cell structure152and the top cell structure172may be the same as the number of gate electrodes220vertically stacked in the cell array region CAR.

In one example embodiment, the thickness of each of the sacrificial films130of the bottom and top cell structures152and172may be identical, except that, from among the sacrificial films130, the uppermost sacrificial film and the lowermost sacrificial film may have greater thicknesses than the other sacrificial films.

However, the number of films constituting the bottom and top cell structures152and172, the thickness of each of the films, and a material that forms each of the films are not limited to the description above and related drawings. That is, the numbers, the thicknesses, and the materials may vary according to the kind of applied products, electrical characteristics of a memory cell transistor, and efficiency or technical difficulties in patterning the bottom cell structures152and the top cell structures172.

Referring toFIG. 5J, the top insulating film175may be formed on the substrate100in the peripheral circuit region PERI and the word line contact region WCTR. The top insulating film175may be formed by using a material that has etch selectivity with respect to the sacrificial films130when the sacrificial films130of the bottom and top cell structures152and172are removed. The top insulating film175may be formed by, e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), sub-atmospheric CVD (SACVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), or high density plasma CVD (HDP CVD). By these deposition processes, the top insulating film175may be provided to cover the structure on the substrate100, that is, the structure that has been explained in connection withFIG. 5I, in the cell array region CAR, the word line contact region WCTR, and the peripheral circuit region PERI.

Thereafter, a planarization process may be performed on the top insulating film175. As a result, the planarized top insulating film175may expose the top surface of the uppermost interlayer insulating film140. The top insulating film175may include a material that is substantially the same as the bottom insulating film160.

Referring toFIG. 5K, the channel holes180amay be formed in the cell array region CAR and the dummy holes180bmay be formed in the word line contact region WCTR, and the semiconductor pattern190may be formed to fill a bottom portion of each of channel holes180a. In one example embodiment, forming the channel holes180amay include forming a mask pattern on the top cell structure172, and anisotropically, continuously etching the top and bottom cell structures172and152and the bottom gate insulating film101by using a mask pattern as an etch mask until the top surface of the substrate100is exposed. The channel holes180amay expose side surfaces of the sacrificial films130and the interlayer insulating films140, and may pass through the bottom gate insulating film101to expose the top surface of the substrate100. In one example embodiment, when the channel holes180aare formed, the top surface of the substrate100exposed by the channel holes180ais over-etched to form a recess having a predetermined depth. The top surface of the substrate100corresponds to an active region of the cell array region CAR.

In one example embodiment, forming the dummy holes180bmay include anisotropic, continuous etching of the top insulating film175and the top and bottom cell structures172and152by using a mask pattern as an etch mask until the device isolation film102of the substrate100is exposed. The dummy holes180bmay pass through the top insulating film175, the sacrificial films130, and the interlayer insulating films140to expose the device isolation film102of the substrate100. In one example embodiment, when the dummy holes180bare formed, a portion of the device isolation film102exposed by the dummy holes180bmay be over-etched to form a recess having a predetermined depth. The channel holes180aand the dummy holes180bmay be formed at the same time by anisotropic etching.

In one example embodiment, the semiconductor patterns190filling the bottom portion of each of the channel holes180amay be formed by a SEG process using the top surface of the substrate100exposed by the channel holes180aas a seed. However, the semiconductor patterns190are not formed on the device isolation film102exposed by the dummy holes180b. This is because the device isolation film102includes an insulating film, e.g., silicon oxide film, and cannot be used as a seed for a SEG process. Accordingly, the semiconductor patterns190may be formed only within the channel holes180ain the cell array region CAR. The semiconductor patterns190may include a monocrystalline silicon or monocrystalline silicon-germanium. In one or more embodiments, the semiconductor patterns190may include a doped impurity ion. Top surfaces of the semiconductor patterns190may lie at a higher level than the lowermost sacrificial film130.

Referring toFIG. 5L, the channel structures200aand the contact pads207amay be formed in the channel holes180aon the semiconductor patterns190. Simultaneously, the dummy channel structures200band the dummy contact pads207bmay be formed on the device isolation film102exposed by the dummy holes180b.

Each of the channel structures200amay include the first dielectric film pattern201a, the first vertical channel pattern203a, and the first filling insulating film pattern205a, which are sequentially stacked. The channel structures200amay contact the semiconductor patterns190and may be electrically connected to the substrate100. Bottom surfaces of the channel structures200amay lie at a higher level than the top surface of the lowermost sacrificial film, but embodiments are not limited thereto.

Each of the dummy channel structures200bmay include the second dielectric pattern201b, the second vertical channel pattern203b, and the second filling insulating film pattern205b, which are sequentially stacked. The dummy channel structures200bmay contact the device isolation film102through the lowermost sacrificial film130. Accordingly, the dummy channel structures200bmay be vertically spaced apart from the substrate100with the device isolation film102therebetween. That is, the dummy channel structures200bmay be electrically insulated from the substrate100by the device isolation film102. Bottom surfaces of the dummy channel structures200bmay lie at a lower level than the bottom surface of the sacrificial film130. In one or more embodiments, bottom surfaces of the dummy channel structures200bmay lie at a lower level than bottom surfaces of the channel structures200a.

The first and second dielectric patterns201aand201bmay each have a pipe shape, and may be respectively formed in the channel holes180aand the dummy holes180b. The first and second dielectric patterns201aand201bmay each include a plurality of insulating films. In one embodiment, each of the first and second dielectric patterns201aand201bmay include a plurality of films including, e.g., a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and a high-dielectric film.

The first and second vertical channel patterns203aand203bmay be formed to have a hollow cylindrical shape or a cup shape. Empty regions defined by the first and second vertical channel patterns203aand203bmay be respectively filled with first and second filling insulating film patterns205aand205b. Each of the first and second vertical channel patterns203aand203bmay include an impurity-doped semiconductor, or impurity-undoped intrinsic semiconductor. In one embodiment, a semiconductor material may include, e.g., silicon (Si), germanium (Ge), or a mixture thereof. The first and second filling insulating film patterns205aand205bmay each be formed by using an insulating material having gap-fill characteristics. In one embodiment, each of the first and second filling insulating film patterns205aand205bmay include, e.g., a high-density plasma oxide film, a spin-on-glass (SOG) film, or a CVD oxide film.

The contact pads207aand the dummy contact pads207bmay be formed on the channel structures200aand the dummy channel structures200b, respectively. Each of the contact pads207aand the dummy contact pads207bmay be formed by using impurity-doped poly silicon or a metal material.

Referring toFIG. 5M, a trench210vertically passing through the sacrificial films130and the interlayer insulating films140may be formed between adjacent channel structures200a. The trench210may extend between the dummy channel structures200b.

Forming of the trench210may include forming of a mask pattern defining where the trench210is to be formed on the top cell structure172and the top insulating film175, and anisotropic-etching of the top and bottom cell structures172and152and the top insulating film175by using the mask pattern as an etch mask. The trench210may expose a portion of the top surface of the substrate100vertically through the interlayer insulating films140, the sacrificial films130, the top insulating film175, and the bottom gate insulating film101. The trench210may extend in parallel to the top surface of the substrate100in the cell array region CAR and the word line contact region WCTR. The trench210may be spaced from the channel structures200aand the dummy channel structures200band may expose side walls of the top insulating film175, the sacrificial films130, the interlayer insulating films140, and the bottom gate insulating film101. In the plan view of the trench210, the trench210may have a line shape, a bar shape, or a rectangular shape. The trench210may, by a vertical depth, expose the top surfaces of the substrate100and the device isolation film102. In one example embodiment, when the trench210is formed, the top surfaces of the substrate100and the device isolation film102exposed by the trench210may be over-etched and recessed.

In one example embodiment, once the trench210is formed, the impurity region211may be locally formed on the substrate100exposed by the trench210. During an ion implantation process for forming the impurity region211, the bottom and top cell structures152and172having the trench210may be used as a mask. The impurity region211may have, like the horizontal shape of the trench210, a line shape that extends in one direction. The impurity region211may overlap with a portion of a bottom portion of each of the bottom and top cell structures152and172due to diffusion of an impurity. The impurity region211may have a conductive type that is opposite to that of the substrate100. For example, when the substrate100has an n-type conductivity, the impurity region may have a p-type conductivity, and when the substrate100has p-type conductivity, the impurity region may have an n-type conductivity.

Referring toFIG. 5N, the sacrificial films130exposed by a side wall of the trench210are removed by performing an etch process, thereby forming side gap regions213.

The etch process may include isotropic etching the sacrificial films130through the trench210by using an etchant that has etch selectivity with respect to the interlayer insulating films140, the bottom gate insulating film101, and the top insulating film175. In one embodiment, when the sacrificial films130are each a silicon nitride film, and the interlayer insulating films140, the bottom gate insulating film101, and the top insulating film175are silicon oxide films, an etch process may be performed by using an etchant including a phosphoric acid. The side gap regions213may horizontally extend from the trench210in between the interlayer insulating films140to expose portions of the channel structures200aand the dummy channel structures200b.

Referring toFIG. 5O, the side gap regions213are filled with the gate electrodes220.

Forming of the gate electrodes220may include forming of a conductive film in the side gap regions213and the trench210, and removing the conductive film in the trench210. The gate electrodes220may vertically be spaced from each other.

A conductive film may be formed by a deposition technique that provides excellent step coverage properties. Such a deposition technique may be, e.g., a chemical vapor deposition technique or an atomic layer deposition technique. Accordingly, the conductive film may fill the side gap regions213. The conductive film may be formed conformally within the trench210. The conductive film may include at least one of, e.g., doped polysilicon, tungsten, metal nitride films, and metal silicide. In one example embodiment, forming of the conductive film may include forming a metal film, e.g., metal nitride, and a metal film, e.g., tungsten, in a sequential manner. However, embodiments are not limited to a flash memory device, and accordingly, the conductive film may have other materials and structures than those described herein. Thereafter, the conductive film is removed from the trench210, thereby allowing the gate electrodes220to be vertically spaced apart from each other.

In one embodiment, the gate electrodes220may be used as the string selection line SSL, the ground selection line GSL, and the word lines WL, which have been explained in connection withFIG. 2. In one embodiment, the uppermost layer and the lowermost layer of the gate electrodes220are respectively used as the string selection line SSL and the ground selection line GSL, and the remaining layers of the gate electrodes220between the uppermost layer and the lowermost layer may be used as the word lines WL. The string selection transistor SST may be formed where the string selection line SSL crosses the channel structures200a, the ground selection transistor GST may be formed where the ground selection line GSL crosses the semiconductor pattern190, and the memory cell transistors MCT may be formed where the word line WL crosses the channel structures220a.

The insulating spacer225may be formed on the side wall of the trench210. The insulating spacer225may be formed in such a manner that an insulating film for a spacer is provided on the surface of the substrate100, and then, an anisotropic etch is performed on the gate electrodes220and the interlayer insulating films140in a direction vertical to the top surface of the substrate100until the impurity region211is exposed. The insulating spacer225may include, e.g., silicon oxide, silicon nitride, silicon oxy nitride, or other insulating materials.

Referring toFIG. 5P, a first contact hole215aand a second contact hole215bare respectively formed in the word line contact region WCTR and the peripheral circuit region PERI. The first contact hole215amay expose a portion of a first gate electrode which is any one of the gate electrodes220. The second contact hole215bmay expose a portion of top surfaces of the peripheral gate electrodes112of the peripheral transistors110and a portion of the top surface of the source/drain region113.

Referring toFIG. 5Q, the common source line CSL, and the first and second wiring plugs245aand245bmay be formed by filling the trench210and the first and second contact holes215aand215bwith a, e.g., same, conductive material, e.g., tungsten, and performing an etch-back process or CMP thereon. As a result, the common source line CSL and the first and second wiring plugs245aand245bmay have an identical composition, and top surfaces of the common source line CSL, and first and second wiring plugs245aand245bmay lie at the same level, e.g., be substantially level and coplanar with each other. By forming the common source line CSL simultaneously with the first and second wiring plugs245aand245b, e.g., as opposed to sequentially, the amount of the conductive material consumed by, e.g., CMP, may be reduced.

In one example embodiment, forming each of the common source line CSL and the first and second wiring plugs245aand245bmay include forming of a barrier metal film, e.g., a metal nitride film, and a metal film, e.g., a tungsten film, in a sequential manner. The common source line CSL may contact and be electrically connected to the impurity region211. The common source line CSL may have a line shape that extends in one direction.

Referring toFIG. 5R, the conductive lines260may be formed on the dummy contact pads207band the first and second wiring plugs245aand245bin the word line contact region WCTR and the peripheral circuit region PERI, and may extend in parallel to the top surface of the substrate100. Forming of a conductive line may include forming of a barrier metal film, e.g., a metal nitride film, and a metal film, e.g., a tungsten film, in a sequential manner. The conductive lines260may cross, e.g., overlap, at least a portion of a vertical extension of the dummy channel structures200band the dummy contact pads207b.

Referring toFIG. 5S, the top interlayer insulating film235may be formed over the surface of the substrate100, and the bit line plugs240and bit lines BL may be formed in the cell array region CAR. The bit line plugs240may be configured to contact the contact pads207aformed on the channel structures200ato be electrically connected to the channel structures200a. The bit lines BL may be formed on the bit line plugs240and may cross the gate electrodes220. Forming the bit line plugs240may include forming contact holes passing through the top interlayer insulating film235on the contact pad in the cell array region CAR and filling the contact holes with a conductive material. The bit line plugs240may include a metallic material, and the metallic material may include a barrier metal film, e.g., a metal nitride film, and a metal film, e.g., a tungsten film.

In one example embodiment, forming of the bit lines BL may include forming of a barrier metal film, e.g., a metal nitride film, and a metal film, e.g., a tungsten film, in a sequential manner.

FIGS. 6A to 6Eshow cross-sectional views taken along lines I-I′ and II-II′ illustrated inFIG. 4Ato explain stages in a method of fabricating a vertical memory device according to another example embodiment

Referring toFIG. 6A, the peripheral transistors110and the peripheral conductive lines116connecting the peripheral transistors110to each other may be formed on the first substrate100a. The first substrate100amay include a material having semiconductor characteristics, e.g., a silicon wafer. The first substrate100amay include the peripheral circuit region PERI.

Each of the peripheral transistors110may include the peripheral gate insulating pattern111, the peripheral gate electrodes112, the source/drain region113, and the gate spacer115. The peripheral transistors110and the conductive lines116may be covered by the peripheral insulating film120. The peripheral insulating film120may include the first peripheral insulating film120band the second peripheral insulating film120a. The first peripheral insulating film120band the second peripheral insulating film120amay each include a silicon oxide film.

Referring toFIG. 6B, the second substrate100bmay be formed on the second peripheral insulating film120b. The second substrate100bmay be formed by providing and monocrystallizing a material having semiconductor characteristics, for example, poly silicon or amorphous silicon. The second substrate100bmay include the cell array region CAR and the word line contact region WCTR. The device isolation film102may be formed in the second substrate100b. The device isolation film102may be formed by a STI process. The STI process may include forming isolation trenches in the substrate100b, and filling the isolation trenches with, for example, silicon oxide.

Referring toFIG. 6C, a stack structure270may be formed on the second substrate100b. The stack structure270may include the interlayer insulating films140and the sacrificial films130, which are sequentially, repeatedly stacked. Before the stack structure270is formed, the bottom gate insulating film101including a thermal oxidation film may be formed on a top surface of the second substrate100b.

Referring toFIG. 6D, the stack structure270is patterned to form a cell structure272on a substrate100bin the cell array region CAR. The cell structure272may be formed by patterning the stack structure270a plurality of times to form a stair-like structure. The cell structure272may extend from the cell array region CAR to the word line contact region WCTR, thereby forming a contact portion having a stair-like shape. Due to the forming of the cell structure272having a stair-like structure, ends of the interlayer insulating films140and the sacrificial films130may be located in the word line contact region WCTR.

Referring toFIG. 6E, the top insulating film175may be formed on the second substrate100bin the word line contact region WCTR.

The subsequent processes for forming a vertical memory are similar to those explained in connection withFIGS. 5K to 5S, and accordingly, will not be described in detail herein.

In the method of fabricating a vertical memory device as described above, the first and second wiring plugs245aand245band the common source line CSL are simultaneously provided. Due to the simultaneous formation, an amount of conductive material used is minimized, and the vertical distance between the conductive lines260and the top surface of the substrate100is decreased, thereby providing a space for forming wiring in a subsequent process, and reducing the size of a vertical memory device, enabling miniaturization and integration.

In this regard, if the vertical distance between the bottom surfaces of the conductive lines260and the top surfaces of the dummy contact pads207bformed on the dummy channel structures200bwere to be reduced, without the device isolation film102between the substrates100and the dummy channel structures200b, the conductive lines260would be short-circuited with the substrates1001and100bthrough the dummy contact pads207band the dummy channel structures200b. However, in example embodiments, since the dummy holes180bare formed on the device isolation film102, the semiconductor patterns190formed by SEG may not be formed in the dummy holes180b. Accordingly, the dummy channel structures200bmay be insulated from the substrates100aand100b, and the conductive lines260may be insulated from the substrates100aand100b. By doing so, the conductive lines260cross the vertical extension of the dummy channel structures200b, and thus, a degree of freedom in designing a wiring may be increased.

By way of summation and review, embodiments provide a vertical memory device with a high degree of freedom in terms of wiring. Embodiments also provide a method of fabricating the vertical memory device. That is, a dummy channel is formed on a device isolation region, so the dummy channel is insulated from a substrate via the insulating material of the device isolation region. Accordingly, a metal line crossing the dummy channel may not be short-circuited with the substrate.