Selective margin testing to determine whether to signal train a memory system

Method, systems and apparatuses may provide for technology that executes a margin test of a first memory storage based on a subset of first signals associated with the first memory storage. The technology determines, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints. The technology determines, based on the first margin data, whether to execute a signal training process.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application is a U.S. National Phase Patent Application, which claims the benefit of priority to International Patent Application No. PCT/CN2019/074738 filed on Feb. 8, 2019.

TECHNICAL FIELD

Embodiments generally relate to memory management. More particularly, embodiments relate to accurate memory control and design.

BACKGROUND

to Computing systems (e.g., servers, cellular devices, etc.) may be trained to effectively utilize memory modules (e.g., Dual-Inline-Memory-Modules which may be referred to as DIMMs). For example, the computing systems may undergo signal training to deliver a stable memory environment. Signal training may include identifying appropriate voltages, timings and/or electrical characteristics of control, command and data signals of a memory module to avoid memory losses and/or failures. The total latency of signal training is dependent on the number of memory modules (e.g., DIMMs) populated on system. That is, as the number of DIMMs increase, the time needed to perform signal training increases. Further, a computing system may perform the signal training during a boot process of the computing system to provide a stable operating system environment after the boot process. Thus, signal training is necessary under some circumstances for stability, but increases latency during the boot process.

DESCRIPTION OF EMBODIMENTS

FIG.1illustrates a process100to enhance memory reliability and usage in a power efficient and low latency manner. The process100may occur during a current boot process that includes a low latency “fast boot” mode. For example, a boot process firmware (e.g., Basic Input-Output System or Unified Extensible Firmware Interface) may cache previously identified signal values (e.g., timings and/or voltages) that were identified during a full signal training mode of a previous boot process. In the fast boot mode, boot process firmware may apply the identified signal values directly to a system without any signal training. For example, the memory controller102may control first memory block110, second memory block112and third memory block114based on the identified signal values. The memory controller102may interact with the first, second and third memory blocks110,112,114using the first, second and third signals104,106,108. The memory controller102may program data into (e.g., write) and/or retrieve data (e.g., read) from the first, second and third memory blocks110,112,114using the first, second and third signals104,106,108. For example, the memory controller102may transmit the first, second and third signals104,106,108to program and send instructions to the first, second and third memory blocks110,112,114. For example, the third signals108may include control, command and data signals. The memory controller102may be a processor, and the first, second and third memory blocks110,112,114may be memory storages for example.

An external environment may be changed between the previous and current boot processes. Such external environmental changes may result in changes to temperature, humidity or electronic noises, etc. For example, the memory controller102, the first memory block110, the second memory block112and the third memory block114may be part of a same computing system. The computing system may be shipped from a low latitudes area (e.g., warm area) to a high latitudes area (e.g., cold area). The change in the external environment may result in a shift of signal characteristics. In some cases, the computing system is unable to compensate for the shift through signal-compensation circuits, and the previously identified signal values may not be trustable (e.g., cause system instability).

Some embodiments may provide for a low latency boot process while enhancing system stability and safety. In detail, the boot process firmware may employ a memory tester116to test the third memory block114based on the third signals108(that are output and received during the testing) to diagnose memory signal margins and identify whether a signal retraining process is to be executed. The testing process latency is reduced by testing only a subset of the first, second and third memory blocks110,112,114based on a subset of the first, second and third signals104,106,108. Reliability increases as well since the process100may accurately determine when to retain based on the results of the memory tester116. Thus, due to the reduced latency of testing, the process100may execute during each boot process of the computing system that includes the first, second and third memory blocks110,112,114to enhance system reliability and performance.

For example, the memory tester116may execute margin testing to intentionally vary system parameters (e.g., modify voltage levels higher or lower to test for failures and/or misreads, modify temperatures, etc.) to expose the memory controller102and the third memory block114to conditions that reveal failure and pass conditions. In some embodiments, the results of the testing may include pass/fail levels, voltage level output (e.g., high or low) by the memory controller102, voltage level read (e.g., high or low) by the third memory block104, whether the third memory block114received the third signals108during an intended clock cycle and an intended voltage value, etc. The results of the margin testing may be stored as margin data indicating margin quality.

For example, the memory tester116may determine that the third memory block114is not receiving commands from the memory controller102through the third signals108, and/or reading improper voltage levels to result in a potentially unsafe computing environment. For example, the memory controller102may output one signal of the third signals108to be at a high voltage, but the third memory block114may improperly read the one signal as a low. The memory tester116may identify that the third memory block114is reading a low voltage when the memory controller102actually outputs a high voltage, and thus the memory tester116determines that a test failure has occurred.

As another example, the memory tester116may identify the commands and data that the memory controller102transmits to the third memory block, and the memory tester116may read the third memory block114to determine whether the third memory block114receives the correct commands and data. For example, the memory tester116may read the third memory block114to determine whether the correct data is being stored and retrieved based on the third signals108. In some embodiments, the memory tester116may compare the current boot process testing data to testing data generated during a last full signal training process. The last full signal training process may have occurred during the previous boot process. If the difference in the testing data of the current boot process and the testing data of the previous boot process is higher than a specific threshold, the first-third signals104,106,108may undergo a full signal training process.

Thus, the memory tester116may check margin quality of the third signals108at the timings identified by the previously identified signal values. If the memory tester116determines that the margin quality is unacceptable, another signal training process may be executed to modify the electrical and/or timing characteristics of the first, second and third signals104,106,108. In some embodiments, the memory tester116may be part of the boot process firmware and include a Rank Margin Tool (RMT) to execute a margin test of third memory block114based on the third signals108.

As illustrated, in some embodiments the memory tester116may only test the third memory block114based on a subset of the third signals108. A change in margin quality based on the subset of third signals108may correlate to an overall change in margin quality of the first, second and third memory blocks110,112,114. As such, it may be unnecessary to test each the first, second and third memory blocks110,112,114based on all of the first, second and third signals104,106,108. By omitting some testing, latency is reduced since the memory tester116only tests the third memory block114based on a subset of the third signals108. Further, only some, but not all, of the third signals108may be tested.

While the present example describes that the third memory block114is tested, it will be understood that various combinations of first, second and third signals,104,106,108and the first, second and third memory blocks110,112,114may be tested. For example, the memory tester116may test the first memory block110based on a subset of the first signals104in addition to or rather than testing the third memory block114based on the third signals108.

Process100may retrain the first, second and third signals104,106,108based on the third memory block114testing118described above. That is, in the present example, the memory tester116determines that the testing of the third memory block114has failed so that the first, second and third signals104,106,108should be modified118. The memory trainers120a,120b,120cmay execute a full training process, that may include rebooting the computing system. The memory trainers120a,120b,120cmay execute an iterative process with the memory controller102to modify electrical and/or timing characteristics of the first, second and third signals104,106,108.

For example, the memory trainers120a,120b,120cmay test the first, second and third memory blocks110,112,114based on the first, second and third signals104,106,108to identify whether the first, second and third memory blocks110,112,114operate correctly based on commands and data communicated by the first, second and third signals104,106,108. The memory trainers120a,120b,120cmay determine adjustments to electrical and/or timing characteristics of the first, second and third signals104,106,108so that the first, second and third memory blocks110,112,114accurately receive commands and data from the memory controller102. The memory trainers120a,120b,120cmay provide the adjustments to the memory controller102that outputs modified first, second and third signals104,106,108. The memory trainers120a,120b,120cmay then execute another testing process based on the adjusted first, second and third signals104,106,108and adjust the first, second and third signals104,106,108accordingly. For example, the memory trainers120a,120b,120cmay adjust a guard band, timing and/or values of the first, second and third signals104,106,108.

Thus, some embodiments may leverage rank margin functionality in boot process firmware, and trigger a test (e.g., margin test) on a limited number of memory blocks110,112,114and signals104,106,108for reduced boot times and enhanced memory reliability. Thus, it may be possible to deliver trustable memory system, such as first-third memory blocks110,112,114in a fast boot mode (i.e., without signal training in every boot process) no matter what environmental changes the computing system undergoes. Further, some embodiments may implement a software-based solution without custom hardware designs to facilitate a lower cost.

In some embodiments, the first, second and third memory blocks110,112,114may be volatile memory, such as Dynamic Random-Access Memory (DRAM), Synchronous DRAM (SDRAM), Dual-Inline-Memory-Modules (DIMM), etc. In some embodiments the first, second and third memory blocks110,112,114may be non-volatile. Further, in some embodiments the first, second and third memory blocks110,112,114may be of different types from each other.

FIG.2shows a method300for signal training that may provide a low latency boot process, stable memory usage and stable operating environment. In an embodiment, the method300is implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc., in configurable logic such as, for example, programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), in fixed-functionality logic hardware using circuit technology such as, for example, application specific integrated circuit (ASIC), complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technology, or any combination thereof.

Illustrated processing block302executes a margin test of the first memory storage based on a subset of first signals associated with the first memory storage. For example, the first signals are associated with a read of the first memory storage and a write to the first memory storage.

Illustrated processing block304determines, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints. The one or more electrical constraints may be a proper voltage read by the first memory storage. For example, the one or more electrical constraints may be that the first memory storage should read a high voltage level when a memory controller outputs a corresponding a high voltage signal (i.e., the one or more subset signals). The one or more electrical constraints may not be met if the first memory storage reads a low voltage level when the memory controller outputs a high voltage signal.

Illustrated processing block306determines, based on the first margin data, whether to execute a signal training process. The signal training process includes adjusting one or more of an electrical characteristic or a timing characteristic (e.g., a timing, a voltage and/or a guard band) associated with at least one second signal that is different from the one or more subset signals. The at least one second signal is associated with a second memory storage that is different from the first memory storage.

In some embodiments, illustrated processing blocks302,304,306occur during a current boot process of a computing architecture. In some embodiments, the computing architecture includes the first and second memory storages. In some embodiments, illustrated processing block306includes determining whether to execute the signal training process based on a comparison of the first margin data to second margin data. If the first margin data is substantially different from the second margin data, processing block306determines that the signal training process is to be executed. The second margin data is determined during a previous boot sequence and based on another margin test. The second margin data indicates whether the first memory storage complies with the one or more electrical constraints during the previous boot sequence.

FIG.3shows a method350illustrates a boot process flow to provide stable memory usage with enhanced signal training and memory management at low latency boot process speeds. More particularly, the method350may be implemented in one or more modules as a set of logic instructions stored in a machine- or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc., in configurable logic such as, for example, PLAs, FPGAs, CPLDs, in fixed-functionality logic hardware using circuit technology such as, for example, ASIC, CMOS or TTL technology, or any combination thereof.

Illustrated processing block352includes boot process initialization of a computing system that includes memory storages and a memory controller. The memory controller may interact with the memory storages using memory signals. In some embodiments, a power button actuation or a software reboot command may trigger illustrated processing block352.

Illustrated processing block354determines whether a “Fast Boot Mode” is enabled. A user may enable or disable the fast boot mode. When enabled, the fast boot mode may omit full memory signal training in some circumstances (explained below further). If the fast boot mode is disabled, illustrated processing block356executes a full signal training on the memory structure (e.g., memory storages and the memory signals) to determine setting data (e.g., timing and/or electrical values of the memory signals). For example, block356trains all control, command and data signals associated with the memory storages. Illustrated processing block358executes a full margin test on the entire memory structure to determine second margin data. Illustrated processing block executes the margin test over all ranks and signals (e.g., data, control, etc.). Illustrated processing block360stores the setting and second margin data in a non-volatile memory to be accessed after the boot process completes (e.g., future boot processes and/or while the operating system is executing). Illustrated processing block360then proceeds to illustrated processing block372to continue the boot process. Illustrated processing block374may initialize the operating system and utilize the setting data during execution of an operating system.

If illustrated processing block354determines that the fast boot mode is enabled, illustrated processing block362determines whether a fail flag is set. The fail flag indicates whether a previous margin test failed (explained below). If the fail flag is set, the method350proceeds to illustrated processing block356to execute full signal training, and then to processing block358to reset the fail flag. The fail flag indicates whether the computing system is undergoing a reboot due to a margin shift detected during a previous boot process (e.g., during a fast boot mode of a directly preceding boot process). Thus, method350delivers a trustable memory storage system architecture.

If the fail flag is not set, the method350proceeds to illustrated processing block364. Illustrated processing block364applies stored setting data. The stored setting data was determined during a previous boot process of the computing system, for example at block356of the previous boot process. In particular, the setting data may include saved timings for the memory signals (e.g., when to send the memory signals relative to rising and falling edges of a clock of the computing architecture) and voltages.

Illustrated processing block366executes a partial margin test on the memory structure (e.g., a subset of the memory storages and a subset of the memory signals) to determine first margin data. In contrast, some RMT applications may test all memory storages and memory signals. Thus, illustrated processing block366executes with enhanced time and power efficiency. For example, processing block366may run the RMT on one or two ranks of a DIMM of the computing system, and on limited signals of the one or two ranks. For example, processing block366may only execute a command signals margin test on the one or two ranks, and not a data signal margin test or control signal margin test.

That is, the method350is to detect an impact of significant signal shift and correct the signal shift by re-training the memory signals, and as such there is no need to run a test on all signals of the memory storages or even all the signals of one memory storage. Rather, the identification of significant signal shift is identified from a subset of the memory signals (i.e., less than all memory signals) and a subset of the memory storages (i.e., less than all memory storages). A rank of a DIMM may include a set of dynamic random-access memory (DRAM) chips including a DRAM and one or more optional error correction code (ECC) modules. The number of DRAM chips and ECC modules may vary according to the different ranks.

Illustrated processing block368compares the first margin data to the second margin data. Processing block368checks for significant signal shifts, and so processing block368identifies a margin delta (i.e., differences) between a last cold boot with full memory training applied by block356and margin testing executed by block358, and the current fast boot. Processing block368therefore determines differences between the first and second margin data.

As an example, processing block368determines from the second margin data, a second value for control signal(s) of one or two ranks. As described above, the second margin data was determined during a margin testing of a previous boot process. Processing block368determines from the first margin data, a first value for the control signal(s) of the one or two ranks. As described, the first margin data is determined during the margin test of a current boot process. Processing block368determines a difference between the first value and the second value. Likewise, other results of the margin tests stored in the first and second margin data are compared. As noted, the same setting data (e.g., timing data of signals) may be used when executing the margin tests to generate the first and second margin data.

Processing block370may determine whether a threshold is met by the differences. The threshold may be set by a user or be a predetermined value. In some embodiments, processing block370may determine if there is any significant change on a specific signal's margin, irrespective of whether a current signal margin is higher or lower than a previous signal margin. In some embodiments, if a pass/fail margin test methodology is employed, processing block370may compare the first and second margin data to determine whether enough of the passes and fails are changed between the second margin data and the first margin data, or between previous boot and current boot. If so, then processing block376may set the fail flag so that on during a reboot process, the full signal training of processing block356executes. Processing block378may initialize the reboot (i.e., reboot process) along with the memory re-training request (i.e., the fail flag is set).

If processing block370determines that the threshold is not met, the signals' quality may be deemed sufficient and illustrated processing block372performs a continuous boot process. Processing block374may initialize the operating system with the trustable memory storages.

FIG.4illustrates a process500to enhance memory usage while also maintaining low latency boot processes. The process500may include similar elements to process100, and the corresponding description is omitted for brevity. In process500, the memory tester516may test the first memory block510based on a first subset of the first signals502. That is, not all of the first signals504are tested. The memory tester516may further test the second memory block512based on a second subset of the second signals506. That is, not all of the second signals506are tested. The memory tester516may further test the third memory block514based on a third subset of the third signals508. That is, not all of the third signals508are tested. In further detail, the memory tester516may not test all of the first, second and third signals504,506,506, but may test each of the first, second and third memory blocks510,512,514.

The process500may retrain the second and third signals506,508based on the testing518, and specifically the testing of the second and third memory blocks510,512based on the second and third subsets. That is, process500may identify that the second and third signals506,508may need to be retrained based on the second and third subsets and the second and third memory blocks510,512failing to conform to electrical constraints. Therefore, the memory trainers520a,520bmay be employed to retrain the second and third signals506,508.

As illustrated, the memory tester516may identify that the first memory block510and first signals504conform to the electrical constraints. Therefore, the first memory block510and first signals504are not retrained. As such, the process500may limit the testing to first, second and third subsets, and limit retraining to the second and third memory blocks512,514. Doing so may reduce the retraining time while also ensuring a stable memory environment, particularly if the first, second and third memory blocks510,512,514are of different types from each other. For example, different types of memory may respond differently to environmental changes. In the present example, the first memory block510may be of a first type of memory (e.g., static random-access memory or SRAM) and the second memory block514may be a different type of memory (e.g., erasable programmable read-only memory or EPROM), and thus have different testing outcomes. In another example, the first memory block510may be relatively younger than the second memory block512, and hence have enhanced hardware to exhibit greater resilience to environmental changes.

Turning now toFIG.5, a stability enhanced computing system158(e.g., server, desktop, laptop, mobile device, etc.) is shown. The computing system158may generally be part of an electronic device/platform having computing functionality (e.g., personal digital assistant/PDA, notebook computer, tablet computer, convertible tablet, server), communications functionality (e.g., smart phone), imaging functionality (e.g., camera, camcorder), media playing functionality (e.g., smart television/TV), wearable functionality (e.g., watch, eyewear, headwear, footwear, jewelry), vehicular functionality (e.g., car, truck, motorcycle), etc., or any combination thereof. In the illustrated example, the system158includes a host processor160(e.g., CPU with one or more processor cores) having an integrated memory controller (IMC)162that is coupled to a system memory164, and particularly to first-third storages140a-140c. The IMC162may communicate with the first-third storage140a-140cto store and retrieve data. The first-third storages140a-140cmay be DRAM. The memory tester178may test, during a boot process of the system158, one or more of the first-third storages140a-140cbased on a subset of signals used by the IMC162to communicate with the first-third storages140a-140c. The test may determine whether the first-third storages140a-140bare accurately receiving and interpreting signals from the IMC162. If the test indicates not, the system158may reboot and the memory trainer180may retrain the signals to ensure a safe and reliable memory usage. Thus, the memory tester178, the memory trainer180and the first-third storages140a-140cmay implement one or more aspects of the process100(FIG.1), the method300(FIG.2), method350(FIG.3), and/or process500(FIG.4) already discussed.

The illustrated system158also includes a graphics processor168(e.g., graphics processing unit/GPU) and an input output (IO) module166implemented together with the processor160(e.g., as microcontrollers) on a semiconductor die170as a System on Chip (SOC), where the IO module166may communicate with, for example, a display172(e.g., touch screen, liquid crystal display/LCD, light emitting diode/LED display), an input peripheral156(e.g., mouse, keyboard, microphone), a network controller174(e.g., wired and/or wireless), and mass storage176(e.g., hard disk drive/HDD, optical disc, solid-state drive/SSD, flash memory or other non-volatile memory/NVM).

FIG.6shows a semiconductor package apparatus180. The illustrated apparatus180includes one or more substrates184(e.g., silicon, sapphire, gallium arsenide) and logic182(e.g., transistor array and other integrated circuit/IC components) coupled to the substrate(s)184. In one example, the logic182is implemented at least partly in configurable logic or fixed-functionality logic hardware. The logic182may implement one or more aspects of the process100(FIG.1), the method300(FIG.2), method350(FIG.3), and/or process500(FIG.4) already discussed. In some embodiments, the logic182may execute a margin test of a first memory storage based on one or more subset signals of first signals that are to be received by the first memory storage during the margin test. The logic182may determine, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints. The logic182may determine, based on the first margin data, whether to execute a signal training process. In one example, the logic182includes transistor channel regions that are positioned (e.g., embedded) within the substrate(s)184. Thus, the interface between the logic182and the substrate(s)184may not be an abrupt junction. The logic182may also be considered to include an epitaxial layer that is grown on an initial wafer of the substrate(s)184.

FIG.7also illustrates a memory270coupled to the processor core200. The memory270may be any of a wide variety of memories (including various layers of memory hierarchy) as are known or otherwise available to those of skill in the art. The memory270may include one or more code213instruction(s) to be executed by the processor core200, wherein the code213may implement one or more aspects of the process100(FIG.1), the method300(FIG.2), method350(FIG.3), and/or process500(FIG.4) already discussed. The processor core200follows a program sequence of instructions indicated by the code213. Each instruction may enter a front end portion210and be processed by one or more decoders220. The decoder220may generate as its output a micro operation such as a fixed width micro operation in a predefined format, or may generate other instructions, microinstructions, or control signals which reflect the original code instruction. The illustrated front end portion210also includes register renaming logic225and scheduling logic230, which generally allocate resources and queue the operation corresponding to the convert instruction for execution.

Although not illustrated inFIG.7, a processing element may include other elements on chip with the processor core200. For example, a processing element may include memory control logic along with the processor core200. The processing element may include input/output (I/O) control logic and/or may include I/O control logic integrated with memory control logic. The processing element may also include one or more caches.

Referring now toFIG.8, shown is a block diagram of a computing system1000embodiment in accordance with an embodiment. Shown inFIG.8is a multiprocessor system1000that includes a first processing element1070and a second processing element1080. While two processing elements1070and1080are shown, it is to be understood that an embodiment of the system1000may also include only one such processing element.

Each processing element1070,1080may include at least one shared cache1896a,1896b. The shared cache1896a,1896bmay store data (e.g., instructions) that are utilized by one or more components of the processor, such as the cores1074a,1074band1084a,1084b, respectively. For example, the shared cache1896a,1896bmay locally cache data stored in a memory1032,1034for faster access by components of the processor. In one or more embodiments, the shared cache1896a,1896bmay include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof.

As shown inFIG.8, various I/O devices1014(e.g., biometric scanners, speakers, cameras, sensors) may be coupled to the first bus1016, along with a bus bridge1018which may couple the first bus1016to a second bus1020. In one embodiment, the second bus1020may be a low pin count (LPC) bus. Various devices may be coupled to the second bus1020including, for example, a keyboard/mouse1012, communication device(s)1026, and a data storage unit1019such as a disk drive or other mass storage device which may include code1030, in one embodiment. The illustrated code1030may implement one or more aspects of the process100(FIG.1), the method300(FIG.2), method350(FIG.3), and/or process500(FIG.4) already discussed. Further, an audio I/O1024may be coupled to second bus1020and a battery1010may supply power to the computing system1000.

Note that other embodiments are contemplated. For example, instead of the point-to-point architecture ofFIG.8a system may implement a multi-drop bus or another such communication topology. Also, the elements ofFIG.8may alternatively be partitioned using more or fewer integrated chips than shown inFIG.8.

ADDITIONAL NOTES AND EXAMPLES

Example 1 includes a computing device including a host processor, and a plurality of memory storages coupled to the host processor and including a first memory storage, the plurality of memory storages including executable program instructions, which when executed by the host processor, cause the host processor to execute a margin test of the first memory storage based on a subset of first signals associated with the first memory storage, determine, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints, and determine, based on the first margin data, whether to execute a signal training process.

Example 2 includes the computing device of example 1, wherein the executable program instructions, which when executed by the host processor, is to cause the host processor to execute the margin test, determine the first margin data and whether to execute the signal training process during a current boot process of the computing device.

Example 3 includes the computing device of example 2, wherein the executable program instructions, which when executed by the host processor, cause the host processor to during a previous boot sequence of the computing device, execute another margin test on the first memory storage, during the previous boot sequence and based on the another margin test, determine second margin data to indicate whether the first memory storage complies with the one or more electrical constraints, and determine whether to execute the signal training process based on a comparison of the first margin data to the second margin data

Example 4 includes the computing device of example 1, wherein the first signals are associated with a read of the first memory storage and a write to the first memory storage.

Example 5 includes the computing device of example 4, wherein the executable program instructions, which when executed by the host processor, cause the host processor to determine, based on the first margin data, that the signal training process is to be executed, execute a reboot process of the computing device, and execute, during the reboot process, the signal training process to adjust one or more of an electrical characteristic or a timing characteristic associated with at least one second signal that is different from the subset of the first signals.

Example 6 includes the computing device of example 5, wherein the at least one second signal is associated with a second memory storage of the plurality of memory storages.

Example 7 includes a semiconductor apparatus including one or more substrates, and logic coupled to the one or more substrates, wherein the logic is implemented in one or more of configurable logic or fixed-functionality logic hardware, the logic coupled to the one or more substrates to execute a margin test of a first memory storage based on a subset of first signals associated with the first memory storage, determine, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints, and determine, based on the first margin data, whether to execute a signal training process.

Example 8 includes the semiconductor apparatus of example 7, wherein the logic is to execute the margin test, determine the first margin data and determine whether to execute the signal training process during a current boot process of a computing device, and the computing device includes the first memory storage.

Example 9 includes the semiconductor apparatus of example 8, wherein the logic coupled to the one or more substrates is to during a previous boot sequence, execute another margin test on the first memory storage, during the previous boot sequence and based on the another margin test, determine second margin data to indicate whether the first memory storage complies with the one or more electrical constraints, and determine whether to execute the signal training process based on a comparison of the first margin data to the second margin data.

Example 10 includes the semiconductor apparatus of example 7, the first signals are associated with a read of the first memory storage and a write to the first memory storage.

Example 11 includes the semiconductor apparatus of example 7, wherein the logic coupled to the one or more substrates is to determine, based on the first margin data, that the signal training process is to be executed, execute a reboot process of a computing device that includes the first memory storage, and execute, during the reboot process, the signal training process to adjust one or more of an electrical characteristic or a timing characteristic associated with at least one second signal that is different from the subset of the first signals.

Example 12 includes the semiconductor apparatus of example 11, wherein the at least one second signal is associated with a second memory storage different from the first memory storage.

Example 13 includes the semiconductor apparatus of example 7, wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

Example 14 includes at least one computer readable storage medium including a set of executable program instructions, which when executed by a computing system, cause the computing system to execute a margin test of a first memory storage based on a subset of first signals associated with the first memory storage, determine, based on the margin test, first margin data to indicate whether the first memory storage complies with one or more electrical constraints, and determine, based on the first margin data, whether to execute a signal training process.

Example 15 includes the at least one computer readable storage medium of example 14, wherein the executable program instructions, when executed by the computing system, cause the computing system to execute the margin test, determine the first margin data and determine whether to execute the signal training process during a current boot process of the computing system, and the computing system includes the first memory storage.

Example 16 includes the at least one computer readable storage medium of example 15, wherein the executable program instructions, when executed by the computing system, cause the computing system to during a previous boot sequence of the computing system, execute another margin test on the first memory storage, during the previous boot sequence and based on the another margin test, determine second margin data to indicate whether the first memory storage complies with the one or more electrical constraints, and determine whether to execute the signal training process based on a comparison of the first margin data to the second margin data.

Example 17 includes the at least one computer readable storage medium of example 14, wherein the first signals are associated with a read of the first memory storage and a write to the first memory storage.

Example 18 includes the at least one computer readable storage medium of example 14, wherein the executable program instructions, when executed by the computing system, cause the computing system to determine, based on the first margin data, that the signal training process is to be executed, execute a reboot process of the computing system, wherein the computing system includes the first memory storage, and execute, during the reboot process, the signal training process to adjust one or more of an electrical characteristic or a timing characteristic associated with at least one second signal that is different from the subset of the first signals.

Example 19 includes the at least one computer readable storage medium of example 18, wherein the at least one second signal is associated with a second memory storage different from the first memory storage.

Example 20 includes a method including executing a margin test of a first memory storage based on a subset of first signals associated with the first memory storage, determining, based on the margin test, first margin data indicating whether the first memory storage complies with one or more electrical constraints, and determining whether to execute a signal training process based on the first margin data.

Example 21 includes the method of example 20, wherein the executing, the determining the first margin data, and the determining whether to execute the signal training process occurs during a current boot process of a computing device, and the computing device includes the first memory storage.

Example 22 includes the method of example 21, further including during a previous boot sequence, executing another margin testing of the first memory storage, during the previous boot sequence and based on the another margin testing, determining second margin data indicating whether the first memory storage complies with the one or more electrical constraints, and determining whether to execute the signal training process based on a comparison of the first margin data to the second margin data.

Example 23 includes the method of example 20, wherein the first signals are associated with a read of the first memory storage and a write to the first memory storage.

Example 24 includes the method of example 20, further including determining, based on the first margin data, that the signal training process is to be executed, rebooting a computing device that includes the first memory storage, and executing, during the rebooting, the signal training process to adjust one or more of an electrical characteristic or a timing characteristic associated with at least one second signal that is different from the subset of the first signals.

Example 25 includes the method of example 24, further wherein the at least one second signal is associated with a second memory storage different from the first memory storage.

Example 26 includes a semiconductor apparatus including a means for executing a margin test of a first memory storage based on a subset of first signals associated with the first memory storage, means for determining, based on the margin test, first margin data indicating whether the first memory storage complies with one or more electrical constraints, and means for determining whether to execute a signal training process based on the first margin data.

Example 27 includes the semiconductor apparatus of example 26, wherein the means for executing, the means for determining the first margin data, and the means for determining whether to execute the signal training process execute during a current boot process of a computing device, and the computing device includes the first memory storage.

Example 28 includes the semiconductor apparatus of example 27, further including means for during a previous boot sequence, executing another margin testing of the first memory storage, means for during the previous boot sequence and based on the another margin testing, determining second margin data indicating whether the first memory storage complies with the one or more electrical constraints, and means for determining whether to execute the signal training process based on a comparison of the first margin data to the second margin data.

Example 29 includes the semiconductor apparatus of example 26, wherein the first signals are associated with a read of the first memory storage and a write to the first memory storage.

Example 30 includes the semiconductor apparatus of example 26, further including means for determining, based on the first margin data, that the signal training process is to be executed, means for rebooting a computing device that includes the first memory storage and means for executing, during the rebooting, the signal training process to adjust one or more of an electrical characteristic or a timing characteristic associated with at least one second signal that is different from the subset of the first signals.

Example 31 includes the semiconductor apparatus of example 30, further wherein the at least one second signal is associated with a second memory storage different from the first memory storage.

As used in this application and in the claims, a list of items joined by the term “one or more of” may mean any combination of the listed terms. For example, the phrase “one or more of A, B, or C” both may mean A; B; C; A and B; A and C; B and C; or A, B and C.