SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME

A semiconductor package according to at least one embodiment may include: a first chiplet and a second chiplet disposed side by side with each other, wherein each of the first chiplet and the second comprises a substrate including an active side and a back side opposite to the active side; a back side power distribution network (BSPDN) in the back side of the substrate; and a third chiplet electrically coupling the first chiplet and the second chiplet to each other above the first chiplet and the second chiplet; and a fourth chiplet and a fifth chiplet disposed side by side with the third chiplet.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2022-0189163 filed in the Korean Intellectual Property Office on Dec. 29, 2022, the entire contents of which are incorporated herein by reference.

BACKGROUND

(a) Field of the Invention

The present disclosure relates to a semiconductor package and a method for manufacturing the same.

(b) Description of the Related Art

A semiconductor manufacturing technology to overcome a performance limitation of a conventional single chip is being developed.

If the plurality of chiplets are made smaller and an interconnect that transmits a signal and power is formed more concisely when the chiplets is packaged, more passive or active devices may be integrated within a given area. This leads to improved performance of a semiconductor package. Therefore, it is necessary to develop a new semiconductor package technology capable of miniaturizing the plurality of chiplets and simply forming the interconnect that transmits the signal and the power.

SUMMARY

In at least one embodiment, a back side power delivery network (BSPDN) structure may be formed at a back side of each of heterogeneous chiplets, and a chiplet for a silicon bridge overlapping a portion of a front side of the heterogeneous chiplets may be mounted at a front side of each of the heterogeneous chiplets so that the heterogeneous chiplets are electrically coupled. In at least one embodiment, in order to enhance a heat dissipation characteristic of a semiconductor package, chiplets formed in a dummy may be mounted at the front side of each of the heterogeneous chiplets. A semiconductor package according to at least one embodiment may include: a first chiplet and a second chiplet side by side with each other; a third chiplet above the first chiplet and the second chiplet and electrically coupling the first chiplet and the second chiplet to each other; and a fourth chiplet and a fifth chiplet side by side with the third chiplet. Each of the first chiplet and the second chiplet may include: a substrate including an active side and a back side opposite to the active side; and the back side of the substrate includes a back side power distribution network (BSPDN).

Each of the first chiplet and the second chiplet may further include a through silicon via (TSV) in the back side of the substrate.

The active side of each of the first chiplet and the second chiplet may further include: a back end of the line (BEOL) structure, and a front end of the line (FEOL) structure under the BEOL structure.

The FEOL structure may include a buried power rail (BPR).

One end of the through silicon via (TSV) may be bonded to the buried power rail (BPR), and the other end of the through silicon via (TSV) may be bonded to the back side power distribution network (BSPDN).

The FEOL structure may include a transistor.

One end of the TSV may be bonded to the transistor, and another end of the TSV may be bonded to the BSPDN.

The BEOL structure may include a plurality of signal wiring layers.

At least one of: the fourth chiplet and the fifth chiplet may be a dummy die.

The dummy die may include at least one of copper, aluminum, gold, silver, iron, or stainless steel.

The third chiplet may include a silicon (Si) bridge layer.

A semiconductor package according to another embodiment may include: a redistribution layer substrate; a first chiplet and a second chiplet above the redistribution layer substrate and side by side with each other, wherein each of the first chiplet and the second chiplet includes a back side power distribution network (BSPDN); a first redistribution layer structure on the first chiplet; a second redistribution layer structure on the second chiplet; a third chiplet above the first chiplet and the second chiplet, and overlapping with a partial region of the first redistribution layer structure and a partial region of the second redistribution layer structure, the third chiplet configured to electrically couple the first redistribution layer structure and the second redistribution layer structure; and a fourth chiplet and a fifth chiplet side by side with the third chiplet.

The semiconductor package may further include an encapsulant molding the first chiplet, the second chiplet, the third chiplet, the fourth chiplet, and the fifth chiplet on the redistribution layer substrate.

The encapsulant may further include an epoxy molding compound (EMC).

A method for manufacturing a semiconductor package according to at least one embodiment may include: forming a first chiplet and a second chiplet, wherein the first chiplet and the second chiplet include a back side power distribution network (BSPDN); forming a first redistribution layer structure on the first chiplet; forming a second redistribution layer structure on the second chiplet; mounting the first chiplet and the second chiplet on a third redistribution layer substrate; mounting a third chiplet above the first redistribution layer structure and the second redistribution layer structure such that the third chiplet overlaps on a partial region of the first redistribution layer structure and a partial region of the second redistribution layer structure and electrically couples the first redistribution layer structure and the second redistribution layer structure; mounting a fourth chiplet on the first redistribution layer structure and a fifth chiplet on the second redistribution layer structure such that the fourth chiplet and the fifth chiplet are side by side with the third chiplet; and molding the first redistribution layer structure, the second redistribution layer structure, the first chiplet, the second chiplet, the third chiplet, the fourth chiplet, and the fifth chiplet on the redistribution layer substrate.

The forming the first chiplet and the second chiplet may each include: forming a front end of the line (FEOL) structure on an active side of a first wafer; forming a first back end of the line (BEOL) structure on the FEOL structure; bonding a second wafer to the first BEOL structure; forming a through silicon via (TSV) at a back side of the first wafer and forming a second BEOL structure at the back side of the first wafer; and de-bonding the second wafer. The forming the first redistribution layer structure and the forming the second redistribution layer structure may include forming the first redistribution layer structure and the second redistribution layer structure on the first BEOL structure of first chiplet and the second chiplet, respectively.

The bonding the second wafer to the first BEOL structure may include bonding an oxide layer of the second wafer to the first BEOL structure.

The forming the FEOL structure on the active side of the first wafer may include forming a transistor and a buried power rail (BPR).

The forming the first BEOL structure on the FEOL structure may include forming a plurality of signal wiring layers.

The forming the through silicon via (TSV) at the back side of the first wafer and forming the second BEOL structure at the back side of the first wafer may include forming a back side power distribution network (BSPDN).

According to at least one embodiment, when the embodiment is compared with a back end of the line (BEOL) structure that serves to transmit a signal and power at a front side of a substrate of conventional chiplets, if chiplets including a BEOL structure for a signal at a front side of a substrate and a BEOL structure of a back side power delivery network (BSPDN) structure at a back side of the substrate are used, an area and resistance of the BEOL structure at the front side of the substrate may be reduced so that signal and power characteristics of a semiconductor package are improved.

According to at least one embodiment, the heat dissipation characteristic of the semiconductor package may be enhanced by mounting the chiplets formed in the dummy at the front surface of each of the heterogeneous chiplets.

According to at least one embodiment, the chiplet for the silicon bridge overlapping the portion of the front side of the heterogeneous chiplets may be mounted at the front side of each of the heterogeneous chiplets so that a signal characteristic of the heterogeneous chiplets within the semiconductor package is improved and the semiconductor package in which various elements are mounted at high density is provided.

DETAILED DESCRIPTION

In order to clearly describe the present disclosure, parts or portions that are irrelevant to the description are omitted, and identical or similar constituent elements throughout the specification are denoted by the same reference numerals.

Further, in the drawings, the size and thickness of each element are illustrated for ease of description, and the present disclosure is not necessarily limited to those illustrated in the drawings. For example, the size of each component in the drawings may be exaggerated for clarity and convenience of description.

Throughout the specification, when a part is “connected” to another part, it includes not only a case where the part is “directly connected” but also a case where the part is “indirectly connected” with another part in between. In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

It will be understood that when an element such as a layer, film, region, area, or substrate is referred to as being “on” or “above” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. Further, in the specification, the word “on” or “above” means positioned on or below the object portion, and does not necessarily mean positioned on the upper side of the object portion based on a gravitational direction. Therefore, it will also be understood that spatially relative terms, such as “above”, “top”, etc., are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures, and that the device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein interpreted accordingly.

Further, throughout the specification, the phrase “in a plan view” or “on a plane” means viewing a target portion from the top, and the phrase “in a cross-sectional view” or “on a cross-section” means viewing a cross-section formed by vertically cutting a target portion from the side.

Hereinafter, a semiconductor package and a method for manufacturing the semiconductor package according to at least one embodiment will be described with reference to the drawings.

FIG.1is a cross-sectional view illustrating a step of providing a first substrate210as one of a plurality of steps of a method for manufacturing a chiplet according to at least one embodiment.

Referring toFIG.1, the first substrate210is provided. In at least one embodiment, the first substrate210may be a semiconductor substrate doped with a p-type or n-type dopant. In another embodiment, the first substrate210may be undoped. In at least one embodiment, the first substrate210may comprise an elemental and/or a compound semiconductor. For example, in at least one embodiment, the first substrate210is bulk silicon, a silicon-on-insulator (SOI), a silicon substrate, a silicon germanium substrate, a silicon germanium-on-insulator (SGOI) substrate, a silicon carbide substrate, a indium antimonide substrate, a lead tellurium compound substrate, an indium arsenide substrate, an indium phosphide substrate, a gallium arsenide substrate, and/or a gallium antimonide substrate, but the present disclosure is not limited thereto.

FIG.2is a cross-sectional view illustrating a step of forming a front end of the line (FEOL) structure220on the first substrate210as one of the steps of the method for manufacturing the chiplet according to the at least one embodiment.

Referring toFIG.2, the FEOL structure220of a chiplet may include epitaxial layers221, an epitaxial contact222, a buried power rail (BPR)224, fins225, a shallow trench isolation (STI)226, and an insulating layer227.

Describing a formation process of the FEOL structure, first, the first substrate210is patterned to form the fins225. The fins225may be channel structures of each of fin field effect transistors (FinFETs).

Next, the shallow trench isolation (STI)226is formed. In at least one embodiment, the shallow trench isolation region (STI)226may include an insulator, such as a silicon oxide, a silicon oxynitride, a silicon nitride, a combination, and/or the like, and may be formed by low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), flowable CVD, and/or the like. In at least one embodiment, the STI226may include spin-on-glass (SOG), SiO, SiON, SiOCN, fluoride-doped silicate glass (FSG), a combination thereof, and/or the like.

Next, a trench is formed at a level below the fins225, and the trench is filled with a conductive material, and then the conductive material is etched to form the buried power rail (BPR)224. The buried power rail (BPR)224serves to deliver electric power to the epitaxial layers221that are active regions. The buried power rail (BPR)224may include, for example at least one of: cobalt (Co), tungsten (W), ruthenium (Ru), an alloy thereof, and/or the like.

Next, the epitaxial layers221are formed on the fins225. The epitaxial layers221may include active regions of transistors (e.g., source regions and/or drain regions).

Next, the insulating layer227burying the epitaxial layers221is formed. In at least one embodiment, the insulating layer227may include a silicon oxide, a silicon nitride, a silicon oxynitride, a tetraethyl orthosilicate (TEOS) forming oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), a low-k dielectric material, another suitable dielectric material, a combination thereof, and/or the like. In at least one embodiment, the insulating layer227may be formed by a CVD, physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal organic CVD (MOCVD), remote plasma CVD (RPCVD), PECVD, LPCVD, atmospheric pressure CVD (APCVD), (and/or the like) process.

Next, the epitaxial contact222(bonded to the epitaxial layers221and extending in a horizontal direction), first vias223(bonded to the epitaxial contact222and the buried power rail (BPR)224), and second vias228(to bond the epitaxial contact222and a first metal pad232of a first back end of the line (BEOL) structure230) are formed. For example, at least one of the epitaxial contact222, the first vias223, and/or the second vias228may be formed by etching the insulating layer227to form a trench and filling the trench with a conductive material, such as a metal. For example, the epitaxial contact222, the first vias223, and the second vias228may include at least one of: copper, aluminum, tungsten, nickel, gold, tin, titanium, an alloy thereof, and/or the like. In at least one embodiment, the epitaxial contact222, the first vias223, and the second vias228may be formed by performing a PVD process.

FIG.3is a cross-sectional view illustrating a step of forming the first BEOL structure230on the FEOL structure220as one of the steps of the method for manufacturing the chiplet according to the at least one embodiment.

Referring toFIG.3, the first BEOL structure230is formed on the FEOL structure220. The first BEOL structure230may include a first metal wiring structure connecting each element and a first intermetal dielectric (IMD)238.

The first metal wiring structure may be a structure including at least one wiring layer that is configured to transmit a signal between elements. The first metal wiring structure may include the first metal pad232, first contact plugs233,235, and237, and first metal wiring layers234and236. The first metal pad232and the first metal wiring layers234and236are patterned in a horizontal direction to transmit a signal at the same level layer. The first contact plugs233,235, and237are patterned in a vertical direction to interconnect the first metal pad232and the first metal wiring layers234and236so that a signal between different level layers is transferred. In at least one embodiment, the first metal pad232, the first contact plugs233,235, and237, and the first metal wiring layers234and236may include a conductive material, such as at least one of: copper, aluminum, tungsten, nickel, gold, tin, titanium, an alloy thereof, and/or the like. Though an example has been illustrated, the examples are not limited to the illustrated example; for example, the first metal wiring structure may include fewer or more first metal pads232, fewer or more first contact plugs233,235, and237, and/or fewer or more first metal wiring layers234and236and still be included within the scope of the present disclosure.

The first intermetal dielectric (IMD)238buries and insulates the first metal pad232, the first contact plugs233,235, and237, and the first metal wiring layers234and236. In at least one embodiment, the first intermetal dielectric238may include an insulator, such as a silicon oxide, a silicon nitride, a silicon oxynitride, a TEOS forming oxide, PSG, BPSG, a low-k dielectric material, another suitable dielectric material, a combination thereof, and/or the like.

In at least one embodiment, a process of the first BEOL structure includes, first, forming the first intermetal dielectric (IMD)238. In at least one embodiment, the first intermetal dielectric (IMD)238may be formed by a CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, or APCVD process.

Next, the first metal pad232may be formed by etching the first intermetal dielectric238to form a trench and filling the trench with a metal. In at least one embodiment, the first metal pad232may be formed by performing a PVD process.

Next, a chemical mechanical polishing (CMP) process is performed at an upper surface of the first metal pad232and an upper surface of the first intermetal dielectric238so that the upper surfaces of the first metal pad232and the first intermetal dielectric238are planarized.

Thereafter, the first contact plug233and the first intermetal dielectric (IMD)238, the first metal wiring layer234and the first intermetal dielectric (IMD)238, the first contact plug235and the first intermetal dielectric (IMD)238, the first metal wiring layer236and the first intermetal dielectric (IMD)238, and the first contact plug237and the first intermetal dielectric (IMD)238may be formed by applying the same characteristic as a characteristic of a formation process of the first metal pad232and the first intermetal dielectric238described above.

FIG.4is a cross-sectional view illustrating a step of bonding a second substrate300to the first BEOL structure230as one of the steps of the method for manufacturing the chiplet according to the embodiment.

Referring toFIG.4, the second substrate300is bonded to the first BEOL structure230. The second substrate300includes an oxide layer310for bonding. In at least one embodiment, the second substrate300may comprise an elemental and/or a compound semiconductor, and may include, for example, a silicon wafer.

FIG.5is a cross-sectional view illustrating a step of forming a through silicon via (TSV)211on a back side of the first substrate210as one of the steps of the method for manufacturing the chiplet according to the at least one embodiment.

Referring toFIG.5, the through silicon via (TSV)211electrically couples the buried power rail (BPR)224of the first FEOL structure220and a second metal pad247of a second BEOL structure240. The through silicon via (TSV)211is formed by forming holes penetrating an insulating material from the back side of the first substrate210and filling the holes with a conductive material. In at least one embodiment, the hole of the through silicon via (TSV)211may be formed by deep etching and/or by a laser. In at least one embodiment, the hole of the through silicon via (TSV)211may be filled with a conductive material by electroplating. In at least one embodiment, the through silicon via (TSV)211may include at least one of: tungsten (W), aluminum (Al), copper (Cu), an alloy thereof, and/or the like.

A barrier layer (not shown) may be formed between the through silicon via (TSV)211and an insulating material of the first substrate210. In at least one embodiment, the barrier layer (not shown) may include at least one of: titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), an alloy thereof, and/or the like.

FIG.6is a cross-sectional view illustrating a step of forming the second BEOL structure240at the back side of the first substrate210as one of the steps of the method for manufacturing the chiplet according to the at least one embodiment.

Referring toFIG.6, the second BEOL structure240is formed at the back side of the first substrate210. The second BEOL structure240is a back side power distribution network (BSPDN). In these cases, the second BEOL structure240is configured to deliver electric power to each element. For example, the second BEOL structure240may include a second metal wiring structure connecting each element and a second inter metal dielectric (IMD)248.

The second metal wiring structure may include the second metal pad247, second contact plugs242,244, and246, and second metal wiring layers241,243, and245. The second metal pad247and the second metal wiring layers241,243, and245are patterned in a horizontal direction to transmit electric power at the same level layer. The second contact plugs242,244, and246are patterned in a vertical direction to interconnect the second metal pad247and the second metal wiring layers241,243, and245so that electric power between different level layers is transferred. In at least one embodiment, the second metal pad247, the second contact plugs242,244, and246, and the second metal wiring layers241,243, and245may include a conductive material, such as at least one of: copper, aluminum, tungsten, nickel, gold, tin, titanium, an alloy thereof, and/or the like. Though an example has been illustrated, the examples are not limited to the illustrated example; for example, the second metal wiring structure may include fewer or more second metal pads247, fewer or more second contact plugs242,244, and246, and/or fewer or more second metal wiring layers241,243, and245and still be included within the scope of the present disclosure.

The second inter metal dielectric (IMD)248buries and insulates the second metal pad247, the second contact plugs242,244, and246, and the second metal wiring layers241,243, and245. In at least one embodiment, the second inter metal dielectric (IMD)248may include an insulator, such as a silicon oxide, a silicon nitride, a silicon oxynitride, a TEOS forming oxide, PSG, BPSG, a low-k dielectric material, another suitable dielectric material, a combination thereof, and/or the like.

A formation process of the second BEOL structure240may be formed by applying the same characteristic as characteristic of a formation process of the first BEOL structure230described above.

FIG.7is a cross-sectional view illustrating a step of de-bonding the second substrate300as one of the steps of the method for manufacturing the chiplet according to the embodiment.

Referring toFIG.7, the second substrate300is de-bonded except for the oxide layer310. After de-bonding the second substrate300, a third via311is formed at the oxide layer310. The third via311is formed by forming a hole at the oxide layer310and filling the hole with a conductive material. In at least one embodiment, the third via311may include at least one of: copper, aluminum, tungsten, nickel, gold, tin, titanium, an alloy thereof, and/or the like.

FIG.8is a cross-sectional view illustrating a step of forming a redistribution layer structure150on the first BEOL structure230as one of the steps of the method for manufacturing the chiplet according to the at least one embodiment.

Referring toFIG.8, the redistribution layer structure150is formed on the first BEOL structure230. The redistribution layer structure150may include a dielectric layer157, and redistribution lines151,153, and156and redistribution vias152,154, and155within the dielectric layer157. Though an example has been illustrated, the examples are not limited to the illustrated example; for example, a redistribution layer substrate may include a fewer or more redistribution lines and/or a fewer or more redistribution vias and still be included within the scope of the present disclosure.

In a process of forming the redistribution layer structure150, the dielectric layer157is formed on the first BEOL structure230. In at least one embodiment, the dielectric layer157is formed of a polymer (such as polybenzoxazoles (PBO), polyimide, and/or the like) and/or an inorganic dielectric material (such as a silicon nitride, a silicon oxide, and/or the like). In at least one embodiment, the dielectric layer157may be formed by a CVD, ALD, or PECVD process.

After forming the dielectric layer157, a via hole is formed by selectively etching the dielectric layer157, and redistribution lines151are formed by filling the via hole with a conductive material. In at least one embodiment, the redistribution lines151may include a conductive material such as at least one of: copper, aluminum, tungsten, nickel, gold, tin, titanium, an alloy thereof, and/or the like. In at least one embodiment, the redistribution lines151may be formed by performing a sputtering process and/or by an electroplating process after forming a seed metal layer.

Next, the dielectric layer157is additionally deposited on the redistribution lines151and the dielectric layer157, and the additionally deposited dielectric layer157is selectively etched to form redistribution vias152. Thereafter, the redistribution lines153and the dielectric layer157, the redistribution vias154and the dielectric layer157, the redistribution lines156and the dielectric layer157, and the redistribution vias155and the dielectric layer157may be repeatedly formed in the same way as forming the redistribution lines151and the dielectric layer157, and the redistribution vias152and the additional dielectric layer157.

Next, an insulating layer146and a bonding pad141may be formed on the dielectric layer157of the redistribution layer structure150. In at least one embodiment, the insulating layer146may be a solder resist. The insulating layer146may include a plurality of openings for soldering. In at least one embodiment, the bonding pad141may include a conductive material, such as at least one of: copper, nickel, zinc, gold, silver, platinum, palladium, chromium, titanium, an alloy thereof, and/or the like.

FIG.9is a cross-sectional view illustrating a step of forming a connection member250below the second BEOL structure240as one of the steps of the method for manufacturing the chiplet according to the at least one embodiment.

Referring toFIG.9, an insulating layer251and the connection member250are formed below the second BEOL structure240. In at least one embodiment, the insulating layer251may be a solder resist. The insulating layer251may include a plurality of openings for soldering. In at least one embodiment, the connection member250may include a conductive material such as a solder. The solder may include, for example, at least one of: tin, silver, lead, nickel, copper, a eutectic alloy thereof, and/or the like.

FIG.10is a cross-sectional view illustrating a chiplet of at least one embodiment different from that ofFIG.9, in which the through silicon via (TSV)211is directly bonded to the epitaxial contact222.

Referring toFIG.10, one end of the through silicon via (TSV)211is bonded to the second metal pad247of the second BEOL structure240, and the other end of the through silicon via (TSV)211is directly bonded to the epitaxial contact222. WhenFIG.10is compared withFIG.9in which one end of the through silicon via (TSV)211is bonded to the second metal pad247of the second BEOL structure240and the other end of the through silicon via (TSV)211is directly bonded to the buried power rail (BPR)224, the through silicon via (TSV)211in the embodiment ofFIG.10may be directly bonded to the epitaxial contact222without forming the buried power rail (BPR)224to transfer electric power.

For reference, inFIGS.1to10, a feature of the chiplet is described based on the chiplet including the FinFET transistor according to the embodiment, but in another embodiment, the structure ofFIGS.1to10may be applied to a chiplet including a gate-all-around transistor.

FIG.11is a cross-sectional view illustrating a step of forming a redistribution layer substrate110on a carrier125as one of a plurality of steps of a method for manufacturing a semiconductor package100according to at least one embodiment.

Referring toFIG.11, a front redistribution layer substrate110is formed on the carrier125.

For example, the carrier125may include a silicon-based material (such as glass or a silicon oxide), an organic material, an aluminum-based material (such as aluminum oxide), a combination thereof, and/or the like.

The front redistribution layer substrate110may include a dielectric layer114, and redistribution lines113and117and redistribution vias112,116, and118within the dielectric layer114. Though an example has been illustrated, the examples are not limited to the illustrated example; for example, a redistribution layer substrate may include fewer or more redistribution lines and/or fewer or more redistribution vias and still be included within the scope of the present disclosure.

A formation process of the front redistribution layer substrate110may be formed by applying the same characteristic as a characteristic of a formation process of the redistribution layer structure150described above.

FIG.12is a cross-sectional view illustrating a step of mounting a first chiplet200and a second chiplet200-1on the redistribution layer substrate110as one of the steps of the method for manufacturing the semiconductor package100according to the embodiment.

Referring toFIG.12, the first chiplet200and the second chiplet200-1are mounted on the redistribution layer substrate110. The first chiplet200and the second chiplet200-1may be disposed side by side. The first chiplet200and the redistribution layer structure150may be formed, e.g., by the method referenced inFIGS.1to10; and the second chiplet200-1may be the same type or different type of chiplet as the first chiplet200. Therefore, the structure of the first chiplet ofFIGS.1to10may be equally applied to a structure of the first chiplet200and the second chiplet200-1.

Each of the first chiplet200and the second chiplet200-1may be bonded to a bonding pad121disposed at an upper surface of the redistribution layer substrate110by a connection member250formed at lower surfaces of the first chiplet200and the second chiplet200-1.

Each of the first chiplet200and the second chiplet200-1includes a substrate including an active side and a back side opposite to the active side. Each of the first chiplet200and the second chiplet200-1includes the FEOL structure on the active side of the first substrate210and the first BEOL structure on the FEOL structure, and includes the second BEOL structure below the back side of the first substrate210. The second BEOL structure includes a back side power distribution network (BSPDN). For example, the first chiplet200and the second chiplet200-1may be bonded to the redistribution layer substrate110through the back side.

In the first chiplet200and the second chiplet200-1, the first BEOL structure at a front side of the first substrate210transmits a signal between elements, and the second BEOL structure at a back side of the first substrate210is electrically coupled to a reference voltage (VSS) and a supply voltage (VDD) to deliver electric power. As a result, an interconnection density of the first BEOL structure230may be increased by disposing a power rail above or on the back side of the first substrate210instead of the front side of the first substrate210. In addition, the second BEOL structure240may accommodate a wider power rail, may reduce resistance, and may increase efficiency of power delivery to a transistor.

FIG.13is a cross-sectional view illustrating a step of connecting the first chiplet200and the second chiplet200-1with a third chiplet130as one of the steps of the method for manufacturing the semiconductor package100according to the at least one embodiment.

Referring toFIG.13, the third chiplet130is disposed on a portion of the redistribution layer structure150on the first chiplet200and a portion of the redistribution layer structure150on the second chiplet200-1. The third chiplet130is electrically coupled to the redistribution layer structure150on the first chiplet200and the redistribution layer structure150on the second chiplet200-1by a connection member135. The third chiplet130includes a BEOL structure (not shown). The third chiplet130connects the first chiplet200, the second chiplet200-1, a fourth chiplet140, and a fifth chiplet170, and transfers a signal between the first chiplet200, the second chiplet200-1, the fourth chiplet140, and the fifth chiplet170through the BEOL structure. In at least one embodiment, the third chiplet130may include a silicon (Si) bridge layer.

FIG.14is a cross-sectional view illustrating a step of mounting the fourth chiplet140and the fifth chiplet170on the first chiplet200and the second chiplet200-1as one of the steps of the method for manufacturing the semiconductor package according to the at least one embodiment.

Referring toFIG.14, the fourth chiplet140or the fifth chiplet170may be mounted on the redistribution layer structure150of the first chiplet200or the redistribution layer structure150of the second chiplet200-1. The fourth chiplet140and the fifth chiplet170may be disposed side by side with the third chiplet130. In at least one embodiment, at least one of: the fourth chiplet140and the fifth chiplet170may be a dummy die or a dummy stack. In at least one embodiment, the dummy die or the dummy stack may include a conductor, such as at least one of: copper, aluminum, gold, silver, iron, stainless steel (SUS), an alloy thereof, and/or the like. At least one of the fourth chiplet140and/or the fifth chiplet170may be formed as the dummy die and/or the dummy stack to enhance a heat dissipation characteristic of the semiconductor package. For example, the at least one of the fourth chiplet140and/or the fifth chiplet170may be configured to draw heat from a corresponding one of the first or second chiplets200and200-1, and/or to redistribute the heat from one section of the corresponding one of the first or second chiplets200and200-1to another section of the corresponding one of the first or second chiplets200and200-1. In at least one embodiment, functional elements (such as active elements (e.g., transistors) and/or passive elements (e.g., capacitors)) may be omitted from the dummy die and/or dummy stack and/or the paths for heat dissipation may circumnavigate functional elements such that the paths for heat dissipation are electrically isolated from the functional elements but convey heat away from the active elements through, e.g., thermal conduction.

FIG.15is a cross-sectional view illustrating a step of molding the first chiplet200, the second chiplet200-1, the third chiplet130, the fourth chiplet140, and the fifth chiplet170on the redistribution layer substrate110as one of the steps of the method for manufacturing the semiconductor package100according to the at least one embodiment.

Referring toFIG.15, the first chiplet200, the second chiplet200-1, the third chiplet130, the fourth chiplet140, and the fifth chiplet170are molded on the redistribution layer substrate110with an encapsulant160. In at least one embodiment, the encapsulant160may comprise an epoxy, such as an epoxy molding compound (EMC). In at least one example, a process of molding with the encapsulant160may include a compression molding and/or transfer molding process. After the molding is performed with the encapsulant, a CMP process may be performed at an upper surface of the encapsulant to level the upper surface.

FIG.16is a cross-sectional view illustrating a step of de-bonding the carrier125from the redistribution layer substrate110as one of the steps of the method for manufacturing the semiconductor package100according to the embodiment.

Referring toFIG.16, the carrier125is de-bonded from the redistribution layer substrate110.

FIG.17is a cross-sectional view illustrating a step of forming an external connection terminal115below the redistribution layer substrate110as one of the steps of the method for manufacturing the semiconductor package100according to the at least one embodiment.

Referring toFIG.17, a bonding pad111, an insulating layer119, and the external connection terminal115are formed below a lower surface of the redistribution layer substrate110. In at least one embodiment, the external connection terminal115may include a solder including, e.g., at least one of: tin, silver, lead, nickel, copper, an alloy thereof, and/or the like.