Test system for semiconductor array

In accordance with an embodiment, an integrated circuit includes a plurality of devices on the integrated circuit. Each device includes a driving circuit, an individual contact pad coupled to a first terminal of the driving circuit, and a switch having a first terminal coupled to the first terminal of the driving circuit. Also, the integrated circuit includes a shared contact pad coupled to a second terminal of each switch of the plurality of devices. The integrated circuit also includes a controller coupled to each switch of the plurality of devices, where the controller is configured to selectively control each switch to couple each driving circuit to the shared contact pad.

TECHNICAL FIELD

The present invention relates generally to the field of semiconductor devices, and in particular for the testing of a semiconductor device array.

BACKGROUND

In the field of semiconductor devices, large arrays of many semiconductor devices are increasingly used. For example, large arrays of LED pixels are used for lighting or display purposes. LED arrays are useful because of low energy consumption, high reliability, long lifetime, small size, and fast switching speeds. A large array of LED pixels may be controlled by a large array of semiconductor devices, such as driving circuits implemented using current sources and/or power switches.

Testing semiconductor devices is important to ensure their reliability. However, large arrays of semiconductor devices pose some testing issues. Some industries, such as the automotive industry and aerospace industry, have significant testing requirements to ensure reliability and safety. In order to obtain good test coverage, automated test equipment (ATE) systems have become widespread for testing semiconductor devices. Such ATE systems allow testing to be performed quickly and reduce human involvement in the testing, thereby reducing test cost and human error. An ATE system often involves software that controls hardware to perform tests, collect data, and create reports on the operation of the semiconductor devices.

Front end testing for a large array of semiconductor devices can be problematic because of the high number of contacts corresponding to a large number of devices. Back end testing can be problematic because of the high production costs from failed devices that are not discovered until late in production.

SUMMARY OF THE INVENTION

In accordance with an embodiment, an integrated circuit includes a plurality of devices. Each device includes a driving circuit, an individual contact pad coupled to a first terminal of the driving circuit, and a switch having a first terminal coupled to the first terminal of the driving circuit. Also, the integrated circuit includes a shared contact pad coupled to a second terminal of each switch of the plurality of devices. The integrated circuit also includes a controller coupled to each switch of the plurality of devices, where the controller is configured to selectively control each switch to couple each driving circuit to the shared contact pad.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present invention will be described with respect to preferred embodiments in a specific context, namely the testing of a semiconductor device array. The invention may also be applied, however, to other types of circuits, systems, and methods, such as other testing circuits, systems, and methods.

Large arrays of semiconductor devices have a variety of applications. For example, a large array of LED pixels might be used for displays and lighting.FIG. 1illustrates embodiment chip assembly100for a lighting circuit. LED array106is mounted on semiconductor device array104. Many pixels may be disposed on LED array106. For example, LED array106may contain from about 500 LED pixels to about 10,000 LED pixels. However, LED array106may contain fewer than 500 LED pixels or more than 10,000 LED pixels. The LED pixels of semiconductor device array104may be independently controlled, for example, by coupling a separate semiconductor device to the LED pixels. The semiconductor devices may be driving circuits. In one example, semiconductor device array104is an array of current sources. In another example, semiconductor device array104is an array of switches, for example an array of power switches. The driving circuits on semiconductor device array104have pads that correspond to contact pads of LED pixels on LED array106. Semiconductor device array104may be mounted on PCB102so that the contact pad corresponding to the driving circuits are coupled to the contact pads for the corresponding LED pixels. Hence, the driving circuits are coupled to the corresponding LED pixels. Bond wire108couples semiconductor device array104and PCB102.

FIG. 2illustrates embodiment integrated driver circuit having on-chip test circuitry200for testing driving circuits. In an embodiment, the functionality of the current sources may be verified by connecting the outputs of some or all of the current sources together during a test mode. During this test mode, the total current may be measured using internal or external measurement circuitry. The sum of the current from the connected current sources may then be measured to determine if the current sources are defective. Integrated driver circuit having on-chip test circuitry200includes semiconductor device array104.FIG. 2illustrates three current sources: current source230, current source240, and current source250for clarity of illustration. However, semiconductor device array104may contain a large number of current sources. For example, in some embodiments, semiconductor device array104may contain between about 500 and about 10,000 current sources. Other embodiments may have greater or fewer current sources. In one embodiment, current source230, current source24, and current source250are adjustable current sources. In another embodiment, current source230, current source240, and current source250are controlled remotely using a communication interface.

Current sources230,240, and250are coupled to corresponding individual contact pads234,244, and254respectively. Individual contact pads234,244, and254are configured to be coupled to separate loads202,204, and206in a normal operation mode. Loads202,204, and206may be LED pixels. In addition, loads202,204, and206may be coupled to ground in a normal operation mode. Current sources230,240, and250are coupled to supply voltage contact pad226, which is coupled to supply voltage210in both normal operation mode and test mode. Current sources230,240, and250are coupled to respective test switches232,242, and252. Test switches232,242, and252are each coupled to ground contact pad224. Ground contact pad224may be coupled to ground208in both a normal operation mode and in a test mode.

On-chip controller222on semiconductor device array104, coupled to current sources230,240, and250, and to test switches232,242, and252, controls the output current of current sources230,240, and250in both a normal operation mode and a test mode. Also, on-chip controller222controls current sources230,240, and250by activating and deactivating them. Further, on-chip controller222may also control test switches232,242, and252in a test mode. Communications interface272is coupled to on-chip controller222. External controller274may be coupled to communications interface272. During testing, and during normal operation, external controller274may send commands to on-chip controller222via communications interface272. Communications interface272may be a serial digital interface such as an IIC or SPI interface. Alternately, the communications interface may be a parallel interface or it may be a CAN, LIN, UART, or μs-bus interface.

In a normal operation mode, current sources230,240, and250are configured to output, for example, from about 1 mA to about 10 mA each to loads202,204, and206. Alternatively, other current levels may be used. On-chip controller222turns current sources230,240, and250on and off during normal operation and in test mode. In both modes, on-chip controller222may receive commands from external controller274through a communications interface272. Current sources230,240, and250produce less current in the test mode than they do in the normal operation mode. For example, these current sources may produce from about 100 μA to about 600 μA or from about 10 μA to about 60 μA in test mode. Consequently, in some embodiments, test switches232,242, and252may be implemented using small switches requiring only a fraction of size compared to current sources230,240, and250, which do not have to be able to withstand the high current that the current sources230,240, and250produce in normal operation mode. On-chip controller222controls test switches232,242, and252that remain open in normal operation mode.

To measure the current of a single current source, on-chip controller222turns current source230on to produce current236. Next, on-chip controller222closes test switch232to connect current source230to ground contact pad224. On-chip controller222then turns all other current sources off, and disconnects them from ground contact pad224by closing their corresponding test switches. Thus, current262at ground contact pad224is about the same as current236produced by current source230. Current262can then be measured from ground contact pad224using a contact pin.

To measure the sum of the current in multiple current sources, on-chip controller222turns on all of the current sources to be simultaneously measured and closes the test switches corresponding to the current sources to be measured. In some embodiments, the current sources may be grouped together. With three current sources to be measured, current sources230,240, and250produce respective currents236,246, and256. When test switches232,242, and252are closed, current262is the sum of the current produced by individual current sources230,240, and250(currents236,246, and256). A plurality of current sources may be connected to ground contact pad224through many test switches, and the sum of their currents can be measured. Any number of current sources may be coupled to ground contact pad224by corresponding test switches. In some embodiments, all current sources are coupled and tested at the same time. In other embodiments, for example, embodiments having very large arrays, current sources are tested in groups. During testing, an array may having a total of about 1000 current sources may be tested, for example, in groups of 100 at a time. Alternately, an array may have different numbers of test sources that are tested in groups of other sizes.

Next,FIG. 3illustrates embodiment integrated driver circuit having on-chip test circuitry280for testing driving circuits.FIG. 3is similar to the embodiment ofFIG. 2, except that current sources230,240, and250are directly connected to ground contact pad224instead of to supply voltage contact pad226, as shown inFIG. 2. Loads202,204, and206are coupled to supply voltage210inFIG. 3instead of to ground208inFIG. 2. Also, test switches232,242, and252are coupled to supply voltage contact pad226inFIG. 3instead of to ground contact pad224inFIG. 2.

FIG. 4illustrates embodiment integrated driver circuit having on-chip test circuitry270for testing driving circuits in which the driver is implemented using a switch instead of a current source. Except for the following differences,FIG. 4is similar toFIG. 2except that power switches238,248, and258inFIG. 4replace current sources230,240, and250inFIG. 2. Resistor260inFIG. 4is coupled between ground contact pad224and test switches232,242, and252to limit the current of power switches238,248, and258in test mode when they are coupled to ground contact pad224. On-chip controller222activates and deactivates power switches238,248, and258, by closing and opening them via control signals. In an embodiment, power switches238,248, and258are implemented using switching transistors, such as a MOSFET transistor. Alternatively, other transistor types, such as bipolar transistors may be used. Resistor260may be implemented using an on-chip resistance, using, for example, a resistor or a MOS device biased in the linear region, or it may be a partial power DMOS switch off. By testing the current of power switches238,248, and258, the internal resistance of the power switches may be tested.

FIG. 5illustrates embodiment integrated driver circuit having on-chip test circuitry290for testing driving circuits. Integrated driver circuit having on-chip test circuitry290inFIG. 5is similar to integrated driver circuit having on-chip test circuitry270inFIG. 4except that power switches238,248, and258are directly connected to ground contact pad224inFIG. 5instead of to supply voltage contact pad226inFIG. 4. Also, loads202,204, and206are coupled to supply voltage210inFIG. 5instead of to ground208inFIG. 4. InFIG. 5, resistor260is coupled to supply voltage contact pad226instead of to ground contact pad224inFIG. 4.

FIG. 6illustrates embodiment semiconductor device array104for testing driving circuits. Semiconductor device array104contains supply voltage contact pad226, ground contact pad224, communications interface272, and integrated driver circuit having on-chip test circuitry600. The squares on integrated driver circuit having on-chip test circuitry600represent driving circuits. For testing, integrated driver circuit having on-chip test circuitry600is placed on automatic test equipment (ATE). The driving circuits are divided into virtual groups, for example groups604,606,608,610,612,614,616, and618, as illustrated. An array of driving circuits containing 5000 driving circuits may, for example, be divided into 264 groups with 19 driving circuits in each group. Ground contact pad224, supply voltage contact pad226, communications interface272, and at least one output pin per group is contacted by a probe of a probe card coupled to the ATE. For example, the output pin may be contacted to individual contact pad234inFIG. 2.

Initially, in an embodiment, a single driving circuit in group604is activated. The single driving circuit is activated to a current for normal operation mode, because the current does not pass through the corresponding test switch, which remains open. The other driving circuits in group604are deactivated. Next, the current is measured at the individual output pin for the activated driving circuit, and if the current is not within an acceptable range, the driving circuit fails. If the current is within an acceptable range, the driving circuit passes. If the single driving circuit passes, all the driving circuits in group604are activated and connected to a shared contact pad, for example, to ground contact pad224. The driving circuits are activated at a reduced current in test mode, because the current passes through the test switches. The current for all of the driving circuits in group604is measured at the shared contact pad. When this measurement is within an acceptable range the group passes.

If the measurement is not within an acceptable range, group604fails, and may be split into subgroups to localize the failing driving circuit(s). For example, if group604contains 19 driving circuits, ten of the driving circuits may be activated and connected to the shared contact pad, while the other nine driving circuits are deactivated and disconnected. If a measurement of the ten driving circuits is within an acceptable range, the ten driving circuits are deactivated and disconnected, and the other nine driving circuits are activated and connected. However, if the measurement is not within the acceptable range, five of the ten driving circuits are activated and connected, and the other five are deactivated and disconnected. This may continue until the failing driving circuit is located. Testing is repeated for group606, followed by groups608,610,612,614,616, and618, until all driving circuits are tested.

FIG. 7illustrates flowchart for an embodiment method700for testing driving circuits. Method700may be implemented using integrated driver circuits having on-chip test circuitry200,270,280, or290. Step702involves an operator or an automatic test handler placing a device under test, or a wafer containing multiple devices under test on a test fixture of an ATE. The devices under test may contain arrays of driving circuits. In step704, the array is contacted using, for example, a probe card or other test fixture. For example, the probe card may contact the wafer with a ground probe, a supply voltage probe, one or more communications probe, and one probe per group of driving circuits.

In an embodiment, steps706,708,710,712, and714involve testing a single driving circuit in each group using a probe connected to an individual contact pad of the driving circuit to be tested to test the single driving circuit in normal operation mode. Counter n, used as a loop counter representing the group number may be implemented in the test software of the ATE or using dedicated hardware. Initially, step706sets counter n to zero. Next, in step708, counter n is incremented to n+1. Then, in step710, the current of a single driving circuit is measured. This may be accomplished by activating a single driving circuit in a group while deactivating all the other driving circuits in that group. Activating a driving circuit may involve turning a current source on or closing a power switch, while deactivating a driving circuit may involve turning a current source off or opening a power switch. The driving circuit being tested is activated to a normal operating current, which may be, for example, from about 1 mA to about 10 mA. The current does not pass through the test switches, so a normal current may be used, and the test switches are open. Then, the current at the individual contact pad is evaluated in step712. If the current is not within an acceptable range, the driving circuit fails.

In some embodiments, a required device yield defines the proportion of devices that must operate within tolerance. A required device yield may allow for a certain number of failing devices to occur before the entire array is rejected. The distribution of the failures may affect the required device yield. For example, a cluster of failed devices in one region may make it more likely that the entire array will be failed. If it is not acceptable to have any failed driving circuits, the array of driving circuits fails if any device fails, for example in step710, and testing is complete. However, if it is acceptable to have some failed driving circuits, testing may continue after step710. For example, the process may, for example, return to step710to test another single driving circuit, which may involve contacting another probe to the corresponding individual contact pad for the new driving circuit to test. If the current of the single driving circuit is within an acceptable range, the test proceeds to step714, where it is determined if n is greater than or equal to the number of groups. Then, if n is less than the total number of groups, the test goes back to step708to repeat steps708,710,712, and714.

However, if n is greater than or equal to the total number of groups, testing proceeds to step718, where counter n is set to zero. Steps718,720,722,724, and726test the devices in a group together for multiple groups. Next, in step720, n is set to n+1. In step722, the current for the entire group of driving circuits is measured by activating them and connecting the driving circuits in the group to a shared contact pad, such as a ground contact pad. Connecting the driving circuits may be performed by closing the test switches corresponding to the driving circuits. The driving circuits and test switches may be controlled by an on-chip controller, which in turn may be controlled by an external controller. In step722, the driving circuits are activated to a current lower than that in the normal operation mode. For example, the current may be 1/100 of that in normal operation mode, or from about 10 μA to about 60 μA, to protect the test switches. The current is measured through the output probe at the shared contact pad. The current measured is equal to the sum of the currents in all the driving circuits.

Next, in step724, the current at the shared contact pad is evaluated to determine if it is within an acceptable range. If the current is not within an acceptable range, the test goes to step716. If it is not acceptable to have any failed driving circuits, testing ends. However, if it is acceptable to have some failed driving circuits, for example, the tester may pinpoint which driving circuit(s) failed by dividing the group into subgroups and repeating steps718,720,722, and724for the subgroups.

On the other hand, if the current is within an acceptable range, the test goes to step726to determine if n is less than the total number of groups. If n is less than the total number of groups, the test repeats steps720,722,724, and726for the next group. If n is greater than or equal to the total number of groups, in step728, the entire array passes.

In one example, 19 driving circuits may be measured in a group to maintain a desired testing accuracy. 264 groups of 19 driving circuits each may be created in an array containing 5000 driving circuits. If the test time is 2 ms per group, the total test time will be about 530 ms for testing all the groups (not including testing individual driving circuits.) Testing a single driving circuit per group takes 50 μs per driving circuit. Thus, testing 16 driving circuits will take an additional 0.8 ms. Pinpointing a failed driving circuit would increase the test time.

FIG. 8illustrates embodiment integrated driver circuit having on-chip test circuitry300for testing driving circuits. Integrated driver circuit having on-chip test circuitry300is capable of testing the current sources simultaneously. In test mode, the current sources being simultaneously tested are coupled to ground by corresponding test switches, and the current sources are evaluated using corresponding comparators. Integrated driver circuit having on-chip test circuitry300includes semiconductor device array104.FIG. 8illustrates three current sources: current source230, current source240, and current source250, for clarity of illustration. However, semiconductor device array104may contain a large number of current sources. For example, in some embodiments, semiconductor device array104may contain from about 500 to about 10,000 current sources.

Current sources230,240, and250are coupled to corresponding individual contact pads234,244, and254. Individual contact pads234,244, and254are configured to be coupled to separate loads202,204, and206in normal operation mode. Loads202,204, and206may be LED pixels, which may be coupled to ground in a normal operation mode. Current sources230,240, and250are coupled to supply voltage contact pad226, which is coupled to supply voltage210. Also, current sources230,240, and250are coupled to corresponding test switches232,242, and252. Test switches232,242, and252are coupled to ground contact pad224, which may be coupled to ground208. A first input of comparators302,306, and310is coupled to the corresponding current sources230,240, and250, and to the corresponding test switches232,242, and252. A second input of comparators302,306, and310is coupled to corresponding voltage references304,308, and312.

On-chip controller222on semiconductor device array104is coupled to current sources230,240, and250, to test switches232,242, and252, and to voltage references304,308, and312. On-chip controller controls the current sources230,240, and250by activating and deactivating them. Also, on-chip controller222controls test switches232,242, and252in a test mode. The output of comparators302,306, and310feeds back to on-chip controller222. Communications interface272is coupled to on-chip controller222. External controller274may be coupled to on-chip controller222via communications interface272. External controller274may send commands to on-chip controller222via communications interface272. Also, during testing, on-chip controller222may send data to external controller274using communications interface272. Communications interface272may be a serial digital interface such as an IIC or SPI interface. Alternately, the communications interface may be a parallel interface or a CAN, LIN, UART, μs-bus interface.

On-chip controller222activates current sources230,240, and250and closes test switches232,242, and252to connect the driving circuits to ground contact pad224. External controller274may control on-chip controller222via communications interface272. The voltage under test is developed by the current from the current sources flowing through the parasitic resistance of the system. Then, on-chip controller222causes voltage references304,308, and312to output a minimum voltage references. Next, on-chip controller222evaluates the results of the outputs of comparators302,306, and310, setting a test bit to pass for each driving circuit that has an output voltage that is greater than the minimum reference voltage, and setting a test bit to fail for each driving circuit that has an output voltage that is less than the minimum reference voltage. Then, on-chip controller222causes voltage references304,308, and312to output a maximum voltage reference. On-chip controller222evaluates the results of the outputs of comparators302,306, and310, setting a test bit to pass for each current source that has an output voltage that is less than the maximum reference voltage and setting a test bit to fail for each current source that has an output voltage that is more than the maximum reference voltage. Finally, on-chip controller222transmits the test bits to external controller274via communications interface272.

FIG. 10illustrates embodiment method750of testing driving circuits. Method750may be implemented using integrated driver circuits having on-chip test circuitry300and320. First, step702involves an operator or an automatic test handler placing a device under test or a wafer containing multiple devices under test on a test fixture of an ATE. Each device under test may contain an array of driving circuits. In step704, the array is contacted using, for example, a probe card. For example, the probe card may contact the wafer with a ground probe, a supply voltage probe, one or more communications probe, and one probe per group of driving circuits.

In an embodiment, steps706,708,710,712,713, and714involve testing a single driving circuit in each group using a probe connected to the driving circuit to be tested using an individual contact pad. Counter n, used as a loop counter for the group may be implemented in the test software of the ATE or using dedicated hardware. Initially, step706sets counter n to zero. Next, in step708, counter n is incremented to n+1. In step710, the current of a single driving circuit is measured. This may be performed by activating a single driving circuit in a group while deactivating all the other driving circuits in that group. Activating a driving circuit may involve turning a current source on or closing a power switch, while deactivating a driving circuit may involve turning a current source off or opening a power switch. The driving circuit is activated to a normal operating current in step710, which may be from about 1 mA to about 10 mA. In step710, the current does not pass through the test switches, so a normal current may be used, and the test switches are open. The current at the individual contact pad is then evaluated in step712. In some embodiments, a required device yield defines the proportion of the devices that must be effective.

A device yield may allow for a certain number of failing devices to occur before the entire array is rejected. The distribution of the failed devices may affect the acceptable device yield. For example, a cluster of failed devices in one region may make it more likely that the entire array will be failed. If it is not acceptable to have any failed driving circuits, the array of driving circuits fails if a single driving circuit fails, and testing is complete. If it is acceptable to have some failed driving circuits, testing may continue. For example, the test may return to step710to test another single driving circuit in the region, which may involve contacting another probe to the corresponding individual contact pad for the new driving circuit to test. If the current of the single driving circuit is within an acceptable range, the test proceeds to step714, where the test determines if n is equal to the number of groups in the array of driving circuits. If n is less than the total number of groups, the test goes back to step708to repeat steps708,710,712, and714, for a device in the next group.

After step712, if the driving circuit fails, step748sets a prediagnosis bit to fail. Each individual driving circuit tested corresponds to a prediagnosis bit, which verifies the fault location, which could be used to verify a systematic problem during production. If it is not acceptable to have any failing driving circuits, testing ends. However, if it is acceptable to have some failed driving circuits, testing proceeds, for example to step714. If the driving circuit passes, step713sets the prediagnosis bit to pass, and then proceeds to step714. If n is greater than or equal to the number of groups in step714, testing proceeds to step732.

In steps732,734,736,738,740,742, and744, driving circuits are simultaneously tested in test mode by connecting each tested driving circuit to a corresponding comparator using a corresponding test switch. First, in step732, all driving circuits to be simultaneously tested are activated and the corresponding test switches are closed, connecting each tested driving circuit to the respective comparator. In step732, the driving circuits are activated to a current that is lower than that in a normal operation mode, for example a test mode current from about 10 μA to about 60 μA when the current in normal operation mode is from about 1 mA to about 10 mA. This may be done by signaling an on-chip controller through a communications interface from an external controller to control the driving circuits and test switches. Next, in step734, the voltage references corresponding to the driving circuits are set to the minimum value, for example 500 mV. This step may be performed by a signal through a communications interface from an external controller signaling an on-chip controller to set the voltage references to the minimum value. Alternately, a signal from the on-chip controller may independently set the voltage reference. Next, in step736, the voltage of the driving circuits is compared to the voltage of the reference signals. Step736may be performed by a comparator comparing the voltage of the driving circuit to the voltage of the comparator and sending the comparator output to the on-chip controller. In step738, the voltage difference is evaluated by the on-chip controller of the external controller. If a driving circuit fails, a corresponding diagnosis bit is set to fail in step730. If it is not acceptable to have any failing driving circuits, testing stops. Alternately, if it is acceptable to have some failed driving circuits, testing proceeds in step738. If the voltages of all the driving circuits pass, testing proceeds to step738.

In step738, the voltage references are set to a maximum value, for example 550 mV. This may be performed by a signal from a control interface signaling the on-chip controller, or the on-chip controller may signal independently. Next, in step740, the driving circuit voltage is evaluated. If a driving circuit fails, a diagnosis bit is set to fail in step730. The diagnosis bit represents whether or not each of the tested driving circuits failed. For the driving circuits that pass, diagnosis bits are set to pass. The driving circuits are deactivated and the test switches opened in step744. Then, in step746, the diagnosis bit stream is transmitted to an external controller by a communications interface.

In some embodiments, method750has a short test time when all driving circuits are being tested simultaneously. In some embodiments, a complete measurement may take, for example, about 50 ms using a simultaneous measurement. Measuring the nominal current of physical devices in a normal operating mode might take about an additional 0.8 ms.

FIG. 11illustrates embodiment integrated driver circuit400having on-chip test circuitry400, which includes semiconductor device array104. Integrated driver circuit having on-chip test circuitry400can test multiple current sources by connecting in sequence each current source in a group to be tested to a shared comparator, while optionally testing multiple groups simultaneously using separate comparator circuits.FIG. 11illustrates three current sources: current source230, current source240, and current source250for clarity of illustration. However, semiconductor device array104may contain a large number of current sources. For example, in some embodiments, semiconductor device array104may contain between about 500 and about 10,000 current sources. Alternatively, other numbers of current sources may be used.

Current sources230,240, and250are coupled to corresponding individual contact pads234,244, and254. Individual contact pads234,244, and254are configured to be coupled to separate loads202,204, and206in normal operation mode. Loads202,204, and206may be LED pixels. Additionally, loads202,204, and206may be coupled to ground in normal operation mode. Current sources230,240, and250are coupled to supply voltage contact pad226, which is coupled to supply voltage210. Also, current sources230,240, and250are coupled to respective test switches402,404, and406. Test switches232,242, and252are coupled to comparator408.

A second input of comparator408is coupled to a constant voltage, which may be equal to about half of supply voltage210, while a first output of comparator408is coupled to switch264. Switch264couples the first input of comparator408to either minimum test current source266or to maximum test current source268. Minimum test current source266and maximum test current source268are coupled to ground contact pad224, which may be connected to ground208. Ground contact pad may be coupled to ground208.

On-chip controller222on semiconductor device array104is coupled to current sources230,240, and250, to test switches402,404, and406. Additionally, on-chip controller222is coupled to switch264. On-chip controller222controls the output current of current sources230,240, and250in both a normal operation mode and a test mode. Current sources230,240, and250are controlled by activating and deactivating them. Also, on-chip controller222also controls test switches402,404, and406and switch264in a test mode. External controller274is coupled to on-chip controller222via communications interface272. The output of comparator408is fed back to chip controller222, which may relay this to external controller274by way of communications interface272. During testing, and during normal operation, external controller274may send commands to on-chip controller222via communications interface272. Communications interface272may be a serial digital interface such as an IIC or SPI interface. Alternately, the communications interface may be a parallel interface or it may be a CAN, LIN, UART, or μs-bus interface.

Integrated driver circuit having on-chip test circuitry450illustrated inFIG. 12is similar to integrated driver circuit having on-chip test circuitry400inFIG. 11, with the exception that the driving circuits are implemented using power switches238,248, and258instead of current sources.

FIG. 13illustrates embodiment method760of testing driving circuits. Method760may be implemented using integrated driver circuits having on-chip test circuitry400and450. Initially, step702involves an operator or an automatic test handler placing a device under test, or a wafer containing multiple devices under test on a test fixture of an ATE. Each device under test may contain an array of driving circuits. Next, in step704, the array is contacted using, for example, a probe card. For example, the probe card may contact the wafer with a ground probe, a supply voltage probe, a communications probe, and one probe per group of driving circuits.

In an embodiment, steps706,708,710,712,713,714, and748involve testing a single driving circuit in each group using a probe connected to the driving circuit to be tested. Counter n, used as a loop counter for the group may be implemented in the test software of the ATE or using dedicated hardware. Initially, step706sets counter n to zero. Next, in step708, counter n is incremented to n+1. In step710, the current of a single driving circuit is measured. This may be performed by activating a single driving circuit in a group while deactivating all the other driving circuits in that group. Activating a driving circuit may involve turning a current source on or closing a power switch, while deactivating a driving circuit may involve turning a current source off or opening a power switch. In step710, the driving circuit is activated to a normal operating current, which may be from about 1 mA to about 10 mA. The current does not pass through the test switches in step710, so a normal current may be used, while the test switches are open. The current at the individual contact pad is then evaluated in step712. If the current is not within an acceptable range, the driving circuit fails.

If the current of the single driving circuit is not within an acceptable range, the test continues to step748, where it sets a prediagnosis bit to fail. In some embodiments, a required device yield defines the proportion of the devices that must be effective. A required device yield may allow for a certain number of failing devices to occur before the entire array is rejected. The distribution of the failures may affect the acceptable device yield. For example, a cluster of failed devices in one area may make it more likely that the entire array will be failed. If it is not acceptable to have any failed driving circuits, the array of driving circuits fails if a single driving circuit fails, and testing is complete. If it is acceptable to have some failed driving circuits, testing may continue. For example, the process may return to step710to test another single driving circuit in the region. This may involve contacting another probe to the corresponding individual contact pad for the new driving circuit to test. If the current of the single driving circuit is within an acceptable range, the test sets a prediagnosis bit to pass in step713, and proceeds to step714, where the test determines if n is greater than or equal to the number of groups in the array of driving circuits. If n is less than the total number of groups, the test goes back to step708to repeat steps708,710,712,713, and714for the next group. On the other hand, if n is greater than or equal to the total number of groups, the test goes to step718.

Steps718,720,772,762,764,730,766,768,742,744,770, and746test multiple driving circuits in a group by sequentially connecting them to a comparator, and optionally testing multiple groups in parallel. First, step718sets counter n to zero and step720sets n to n plus one. In step772, one driving circuit per group is activated by closing a corresponding test switch. An on-chip controller may activate the driving circuit and close the test switch, which may be externally controlled via a communications interface by an external controller. Then, in step762, the minimum test current is connected to the input of the comparator. This step may be achieved by an on-chip controller connecting a switch to the minimum test current source. In step764, the output of the comparator is evaluated, for example by an on-chip controller. If the driving circuit fails, step730sets a diagnostic bit to fail. If it is not acceptable to have any failed driving circuits, testing ends. If it is acceptable to have failed driving circuits, testing continues, for example in step744.

If the driving circuit passes, testing continues in step766, where the maximum test current is selected. This may be achieved by switching the comparator input from the minimum current current source to the maximum current current source. Next, in step768, the test voltage is evaluated, possibly by the on-chip controller. If the test voltage is not within an acceptable range, the test goes to step730. If the test voltage is within an acceptable range, a diagnostic bit is set to pass in step742. Then, in step744, the driving circuit is deactivated and disconnected from the comparator by opening the corresponding test switch. In step770, if n is less than the number of driving circuits per comparator, the test proceeds to step720to test the next driving circuit in the group. If n is greater than or equal to the number of driving circuits, the diagnosis bit stream and prediagnosis bit stream are sent by a communications interface from the on-chip controller in step746.

In method760, one comparator and two current sources may be used for all driving circuits on a chip. Alternately, a separate comparator and two current sources can be used for each driving circuit, leading to a higher device count but a lower testing time, because all devices can be tested in parallel. In some embodiments, the driving circuits can be divided into groups of any size where all driving circuits in a group are connected to the same comparator with a separate comparator for each group, with an intermediate device count and intermediate test time. Hence, a tradeoff may be made between test time and device count.

In accordance with an embodiment, an integrated circuit includes a plurality of devices on the integrated circuit. Each device includes a driving circuit, an individual contact pad coupled to a first terminal of the driving circuit, and a switch having a first terminal coupled to the first terminal of the driving circuit. Also, the integrated circuit includes a shared contact pad coupled to a second terminal of each switch of the plurality of devices. The integrated circuit also includes a controller coupled to each switch of the plurality of devices, where the controller is configured to selectively control each switch to couple each driving circuit to the shared contact pad. In some embodiments, the controller is further configured to selectively activate the driving circuit in a normal operation mode and in a test mode, such that an output current of the driving circuit is lower in the test mode than in the normal operation mode. The output current in the test mode may be less than one-tenth the output current in the normal operation mode.

In an embodiment, the controller is further configured to operate in a normal operation mode and in a test mode, the driving circuit is configured to output a current to the individual contact pad in the normal operation mode, and the driving circuit is configured to open circuit the individual contact pad in the test mode. The driving circuit may include a current source in some examples.

In an embodiment, the driving circuit includes a power switch, and the integrated circuit further includes a resistor coupled between the shared contact pad and the switch. The individual contact pad may be configured to be coupled to a corresponding LED during a normal operation mode. In some embodiments, the plurality of devices further includes a comparator having a first terminal coupled to the first terminal of the driving circuit and a voltage reference coupled to a second input terminal of the comparator. The controller may be further configured to control the reference voltage.

In an embodiment, the integrated circuit further includes a common terminal of a current switch coupled to the second terminal of the switch, a first reference current source coupled to a first terminal of the current switch, and a second reference current source coupled to a second terminal of the current switch. The controller may be further configured to connect the common terminal of the current switch to at least one of the first reference current source and the second reference current source.

In accordance with a further embodiment, a method of testing a first plurality of driving circuits that are coupled to a plurality of individual contact pads includes coupling the plurality of driving circuits to a shared contact pad by closing a first plurality of test switches, wherein the plurality of test switches is coupled to the first plurality of driving circuits. The method further includes activating the first plurality of driving circuits to produce a test current, and measuring a current of the first plurality of driving circuits. Measuring the current of the first plurality of driving circuits may include measuring the current of the first plurality of driving circuits at the shared contact pad.

In an embodiment, the method may further include contacting the shared contact pad to a test fixture and/or contacting a ground pad, a supply voltage pad, and a communications interface to the test fixture. The test current of the first plurality of driving circuits may be lower than a current of the first plurality of driving circuits operating in a normal operation mode.

In an embodiment, the method may further include coupling a second plurality of driving circuits to the shared contact pad by closing a second plurality of test switches, activating the second plurality of driving circuits, and measuring a current of the second plurality of driving circuits. Activating the first plurality of driving circuits may include activating a plurality of current sources and/or a plurality of power switches.

In some embodiments, the method further includes activating a first driving circuit to produce a test current and measuring the test current of the first driving circuit at an individual contact pad. The method may also include determining if the measured current is within a predefined current range. In some examples, the method includes placing a wafer on an automated test equipment system.

In an embodiment, the method further includes activating a plurality of reference voltages, and comparing a signal of the plurality of driving circuits to the plurality of reference voltages. The method may also include connecting a first terminal of the first plurality of driving circuits to a first terminal of a comparator, connecting a reference current source to the first terminal of the comparator, and comparing a voltage of the first terminal of the comparator to a fixed voltage.

In accordance with a further embodiment, an integrated circuit includes a plurality of devices on the integrated circuit. Each device includes a driving circuit and a contact pad coupled to a first terminal of the driving circuit, and a switch having a first terminal coupled to the first terminal of the driving circuit. The integrated circuit further includes a current switch having a common terminal coupled to a second terminal of the switch, a first reference current source coupled to a first terminal of the current switch, a second reference current source coupled to a second terminal of the current switch, a comparator having a first input coupled to the common terminal of the current switch, and a controller coupled to the current switch. The controller may be configured to connect the common of the current switch to at least one of the first reference current source and the second reference current source. The driving circuit may include a current source and/or a power switch.

Advantages of embodiments include the ability to accurately test a large array of driving circuits. Some embodiments include the ability to test every driving circuit in a large array. Embodiments allow testing driving circuits before a load array (e.g. an LED array) is connected to the semiconductor device array, which can allow for the detection of defective driving circuits earlier in the production process, saving costs. Some embodiments allow for testing multiple driving circuits at once, leading to a short test time. Various embodiments allow for a tradeoff between the test time and the total number of added test components. Embodiments allow the driving circuits to operate at a reduced current in a test mode, minimizing the size of the added components.

A further advantage of some embodiments allow for the testing of a semiconductor array containing thousands of driving circuits with thousands of associated contact pads without requiring a probe card pads to be coupled to the corresponding contact pad of each driver to be tested.