Display panel, manufacturing method thereof, driving method and display device

A display panel includes a first display sub-panel and a second display sub-panel disposed opposite to each other, the first display sub-panel including a plurality of first gate lines and the second display sub-panel including a plurality of second gate lines. The display panel further includes a plurality of single-way conducting switches, the first gate lines, the second gate lines and the single-way conducting switches being disposed in one-to-one correspondence, each of the single-way conducting switches having an input end which is electrically connected to the corresponding first gate line and an output end which is electrically connected to the corresponding second gate line, and each of the single-way conducting switches being unidirectionaly conducted from the corresponding first gate line to the corresponding second gate line.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of and priority to Chinese Patent Application No. 201810997011.X filed Aug. 29, 2018, the entire contents of which being incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to the field of display technologies, and more particularly, to a display panel, a manufacturing method thereof, a driving method, and a display device.

BACKGROUND

A double-sided display device is a display device that includes a double-sided display. Presently, double-sided display devices have a very vast market foreground and these devices are mainly applied to road sign boards, communication tools (such as mobile phones), and window interaction tools (such as government windows, financial enterprise windows). A common double-sided display device is formed by bonding two display panels arranged opposite to one another, which has a relatively complicated driving process. When the synchronous display of the two display panels is performed, the asynchronous display of two screens commonly occurs and, as such, there is a problem of poor display synchronization.

SUMMARY

An embodiment of the present disclosure provides a display panel, comprising: a first display sub-panel and a second display sub-panel disposed opposite to each other, the first display sub-panel comprising a plurality of first gate lines and the second display sub-panel comprising a plurality of second gate lines, wherein the display panel further comprises a plurality of single-way conducting switches, the first gate lines, the second gate lines and the single-way conducting switches being disposed in one-to-one correspondence, each of the single-way conducting switches having an input end which is electrically connected to the corresponding first gate line and an output end which is electrically connected to the corresponding second gate line, and each of the single-way conducting switches being unidirectionaly conducted from the corresponding first gate line to the corresponding second gate line.

The display panel provided by the present disclosure disposes the single-way conducting switch which is connected between each of the first gate lines and the second gate line corresponding thereto. When the double-sided synchronous display of the display panel is required, a gate scan signal is sent to the first gate line of the display sub-panel, but no signal or a cutoff signal is inputted to the second gate line of the second display sub-panel. The single-way conducting switch, at this time, is turned on and the second gate line corresponding to the first gate line is also synchronously inputted with the gate scan signal by the connection to the single-way conducting switch.

An embodiment of the present disclosure further provides a method for manufacturing a display panel, comprising: providing a base substrate having a first surface and a second surface, which is opposite to the first surface; forming a first stacked structure on the first surface; forming a second stacked structure on the second surface; wherein a structure consisted of the first stacked structure, the base substrate and the second stacked structure comprises a first display sub-panel and a second display sub-panel disposed opposite to each other and a plurality of single-way conducting switches; wherein, the first display sub-panel comprises a plurality of first gate lines and the second display sub-panel comprises a plurality of second gate lines, the first gate lines, the second gate lines and the single-way conducting switches are provided in one-to-one correspondence, each of the single-way conducting switches comprises an input end which is electrically connected to the corresponding first gate line and an output end which is electrically connected to the corresponding second gate line; each of the single-way conducting switches is unidirectionally conducted from the first gate line to the second gate line corresponding thereto.

An embodiment of the present disclosure further provides a driving method for a display panel being used for driving the display panel provided in the first aspect, comprising: when the simultaneous display of the first display sub-panel and the second display sub-panel is performed, inputting a first gate scan signal to the first gate line of the first display sub-panel and enabling the display of the first display sub-panel; and the gate scan signal driving the corresponding single-way conducting switch to be unidirectionally turned on from the first gate line to the second gate line of the second display sub-panel, and allowing the simultaneous display of the second display sub-panel and the first display sub-panel.

An embodiment of the present disclosure further provides a display device comprising the above described display panel.

DETAILED DESCRIPTION

A clear and through description will be given to the technical solution of the present disclosure with reference to the accompanying drawings of the present disclosure. Understandably, the illustrated embodiments are not all of the embodiments of the present disclosure, but only a part of them. According to the embodiments of the present disclosure, all of the other embodiments obtained by those skilled in the art without consuming any creative work fall within the protection scope of the present disclosure.

Referring toFIG. 1, a display panel in an embodiment of the present disclosure includes a first display sub-panel1and a second display sub-panel2which are disposed opposite to each other. The first display sub-panel1includes a plurality of first gate lines101and the second display sub-panel2includes a plurality of second gate lines201. The display panel further includes a plurality of single-way conducting switches3, each of which is connected to one of the first gate lines101and one of the second gate lines201, respectively. Each of the single-way conducting switches3has an input end which is electrically connected to the corresponding first gate line101and an output end which is electrically connected to the corresponding second gate line201. Further, each single-way conducting switch3is unidirectionally conducted from the corresponding first gate line101to the corresponding second gate line201.

The display panel provided by the embodiment of the present disclosure disposes the single-way conducting switch3which is connected between each of the first gate lines101and the second gate line201corresponding thereto. When the double-sided synchronous display of the display panel is required, a gate scan signal is sent to the first gate line101of the display sub-panel1, but no signal or a cutoff signal is inputted to the second gate line201of the second display sub-panel2. The single-way conducting switch3, at this time, is turned on and the second gate line201corresponding to the first gate line101is also synchronously inputted with the gate scan signal by the connection to the single-way conducting switch3, which allows the synchronous display of the first display sub-panel1and the second display sub-panel2and improves the synchronization and consistency of screen when the display sub-panel1and the second display sub-panel2are simultaneously displayed. It should be noted that the cutoff signal or a cutoff voltage described in the embodiment of the present disclosure is a low level signal such as a grounding signal. The single-way conducting switch3is unidirectionally conducted from the input end to the output end thereof in the embodiment of the present disclosure. For example, when the single-way conducting switch3is a P-N junction, it is unidirectionally conducted from a P-region301(input end) to an N-region302(output end) of the P-N junction.

Referring toFIG. 2, the foregoing single-way conducting switch3may be a P-N junction in some embodiments, the P-region301of which is connected to the first gate line101corresponding thereto and the N-region302of which is connected to the second gate line201corresponding thereto.

Referring toFIG. 2, the display panel further includes a spacer layer4interposed between the first display sub-panel1and the second display sub-panel2in some embodiments. The spacer layer4is provided with a plurality of through-holes5, which correspond to the single-way conducting switches3one by one and also correspond to wiring areas of the first display sub-panel1and the second display sub-panel2. It should be noted that the display panel includes a display area and a frame area. The gate lines and data lines in the display area are provided in the frame area through wire bonding, that is to say, the frame area outside the display area is the wiring area in the embodiment of the present disclosure. In addition, it should be noted thatFIG. 2only shows one through-hole5in the wiring area and the first gate line101as well as the second gate line201with which the through-hole5is communicating, but it does not show any other structures as provided in the first display sub-panel1and the second display sub-panel2.

Each of the single-way conducting switches3can be provided in the through-hole5corresponding thereto or in the wiring area of the first display sub-panel1. By passing through the through-hole5corresponding thereto, the output end of each single-way conducting switch3is electrically connected to the second gate line201corresponding thereto. In this case, a line for the connection of the single-way conducting switch3and the second gate line201is disposed in the corresponding through-hole5. When located in the wiring area of the first display sub-panel1, each of the single-way conducting switches3may also be integrated into a gate drive circuit to which each of the first gate lines101is connected. In addition, each of the single-way conducting switches3can also be located in the wiring area of the second display sub-panel2. Through the through-hole5corresponding thereto, the input end of each of the single-way conducting switches3is electrically connected to the first gate line101corresponding thereto. In this case, a line for the connection of the single-way conducting switch3and the first gate line101is disposed in the through-hole5corresponding thereto.

The gate drive circuit may be a shift register unit, for example, a GOA unit. Gate Driver on Array (GOA) is a technology for the integration of a gate drive circuit on an array substrate. Pixel units are periodically arranged in the array substrate. Each of the pixel units may include a switch tube and a pixel electrode and each of the pixel electrodes or a light emitting device8is driven by connecting a data line and a gate line to the switch tube. The switch tube may be a thin film transistor and have a source electrode to which the data line is connected, as well as a gate electrode to which the gate line is connected and a drain electrode to which the pixel electrode is connected. The GOA unit is used as a shift register unit to drive the switch tube in this embodiment.

When the gate drive circuit is the GOA unit, as shown inFIG. 1, the first display sub-panel1further includes a plurality of first GOA units (GOA11˜GOA14inFIG. 1) which are disposed in the wiring areas of the first display sub-panel1and the first GOA units are electrically connected to the first gate lines101in one-to-one correspondence in some embodiments. In order to more clearly indicate correspondence between the GOA unit and the gate lines, referring toFIG. 1, the first gate line numbered Gate11corresponds to GOA11, while the first gate line numbered Gate12corresponds to GOA12, the first gate line numbered Gate13corresponds to GOA13, and the gate line numbered Gate14corresponds to GOA14. The second display sub-panel2further includes a plurality of second GOA units (GOA21˜GOA24inFIG. 1) which are disposed in the wiring areas of the second display sub-panel2and the second GOA units are electrically connected to the second gate lines201in one-to-one correspondence. In order to clearly denote correspondence between the GOA unit and the second gate lines, referring toFIG. 1, the second gate line numbered Gate21corresponds to GOA21, while the second gate line numbered Gate22corresponds to GOA22, the second gate line numbered Gate23corresponds to GOA23, and the gate line numbered Gate24corresponds to GOA24. The input end of each of the single-way conducting switches3is electrically connected to the first GOA unit and the first gate line101corresponding thereto and the output end thereof is electrically connected to the second gate line201corresponding thereto.

Each of the first gate lines101is connected to a plurality of first switch tubes in a row where the first gate line101is arranged, specifically, to a first gate electrode of the first switch tubes. Each of the second gate lines201is connected to a second gate electrode of a plurality of second switch tubes in a row where the second gate line201is arranged.

The gate drive circuit may also be a gate driver chip, which may be bound to the array substrate and connected to a gate electrode through a gate line. As shown inFIG. 3, a first gate driver chip115is used as a driving circuit of a first gate electrode and has a plurality of output ends, each of which is connected to one of the first gate lines101, respectively. Similarly, a second gate driver chip215is used as a driving circuit of a second gate electrode and has a plurality of output ends, each of which is connected to one of the second gate lines201, respectively. When the gate driver chip is used as the gate drive circuit, as shown inFIG. 3, the single-way conducting switch3may be disposed between the first display sub-panel1and the second display sub-panel2and located in the through-hole5. Alternatively, the single-way conducting switch3may be disposed in the wiring area of the first display sub-panel1to be integrated with or separate from the first gate driver chip115.

It should be noted that only four groups of the first and second gate lines are exemplarily illustrated inFIGS. 1 and 3, however, there are a plurality of groups of the first and gate lines disposed on the wiring area of the display panel in one-to-one correspondence.

The display panel in the embodiment of the present disclosure also has the advantage of reducing power consumption during synchronous display. The synchronous display of the first display sub-panel1and the second display sub-panel2may be implemented by sending a gate scan signal to the first gate line101of the first display sub-panel1without any signal input to the second gate line201of the second display sub-panel2. In this case, the first gate driver chip115(or each of the first GOA unit) has a signal output but the second gate driver chip215(or each of the second GOA units) is in a sleep state, and only the gate drive circuit of the first display sub-panel1is operating, thereby reducing the power consumption of the display panel.

As shown inFIGS. 1 and 3, in some embodiments, the second display sub-panel2further includes a plurality of voltage stabilizing resistors R which are disposed in the wiring area of the second display sub-panel2and a plurality of short-circuit branches217. The voltage stabilizing resistors R and the single-way conducting switches3are in one-to-one correspondence and each of the voltage stabilizing resistors R has one end which is electrically connected to the second GOA unit corresponding thereto and the other end which is electrically connected to the output end of the single-way conducting switch3corresponding thereto. The short-circuit branches217are disposed in the wiring area of the second display sub-panel2and are in one-to-one correspondence to the voltage stabilizing resistors R and each of the short-circuit branches217is connected in parallel to both ends of the voltage stabilizing resistor R corresponding thereto. In a specific implementation, two output ends may be provided in the GOA unit, wherein the first output end is connected to the voltage stabilizing resistor R and the second output end is connected to the short-circuit branch217. Whether or not to output a signal from the first output end is controlled by a circuit and a clock signal within the GOA unit, so as to control the turn-on or turn-off of the voltage stabilizing resistor R, and whether or not to output a signal from the second output end is controlled by a circuit and a clock signal within the GOA unit, so as to control the turn-on or turn-off of the short-circuit branch217.

For an instance, the GOA units may be a gate drive circuit. When the first display sub-panel1and the second display sub-panel2are simultaneously displayed, a first gate scan signal is outputted from the first GOA units but no signal or only a cutoff signal is outputted from the second GOA units. The single-way conducting switch3corresponding to them, at this time, has a voltage difference between its input end and output end, so the single-way conducting switch3is turned on. When there is no voltage stabilizing resistor R provided, since no signal or only a cutoff signal is outputted from the second GOA units, voltage at the output end of the single-way conducting switch3is pulled down and voltage of a data signal of each of the second gate electrodes to which the second gate line201is connected is pulled down to be lower than a turn-on voltage of the second gate electrode, so that the second gate electrode cannot be turned on. When a voltage stabilizing resistor R is provided, the short-circuit branch217is disconnected when the synchronous display is performed so as to keep the conducting of the voltage stabilizing resistor R. A appropriate type of resistor may be selected to maintain voltage inputted to each of the second gate electrodes at an appropriate value, which is neither higher than voltage of the first gate scan signal to unable to conduct the single-way conducting switch nor lower than the turn-on voltage of each of the second gate electrodes, so as to ensure the normal turn-on of each of the second gate electrodes and smoothly realize the double-sided synchronous display.

In some embodiments, the above voltage stabilizing resistors may be directly connected to a grounding signal other than the gate drive circuit. That is to say, one end of each of the voltage stabilizing resistors R is electrically connected to the grounding signal and a switch which controls on and off of the voltage stabilizing resistor R is interposed between the voltage stabilizing resistor R and the grounding signal. The other end of each of the voltage stabilizing resistors R is electrically connected to the output end of the single-way conducting switch3corresponding thereto. A plurality of short-circuit branches217are disposed in the wiring area of the second display sub-panel2and are in one-to-one correspondence to the voltage stabilizing resistors R. Each short-circuit branch217has one end which is connected to a second gate drive circuit and the other end which is connected to the second gate line. The on and off of the voltage stabilizing resistor R are controlled by the switch between the voltage stabilizing resistor R and the grounding signal and the on and off of the short-circuit branch is controlled by the second gate drive circuit (the second GOA unit or a second gate starting chip215). The operation principle of the circuit refers to the operation principle of the circuit shown inFIGS. 1 and 3, and repetitive descriptions will not be elaborated herein.

The above-described voltage stabilizing resistors R may be fixed resistors or variable resistors. In practical applications, a resistance value of the voltage-stabilizing resistors R may be determined by reasonable test and calculation and may be ranged from several ohms to several megaohms. For example, a display panel of a device such as a mobile phone has a resistance of less than 10Ω and a 60-inch TV may have a resistance in the order of magnitude of kiloohm (kΩ), megaohm (MΩ).

The first display sub-panel1further includes a plurality of first data lines116and the second display sub-panel2further includes a plurality of second data lines216in some embodiments. It should be noted thatFIGS. 4-5only show a schematic circuit diagram of a display panel having a source driver chip7by taking an example of a group of the first GOA unit and first gate line in the first display sub-panel1as well as a group of the second GOA unit and second gate line in the second display sub-panel2corresponding thereto. Furthermore,FIGS. 4 and 5only exemplarily show a first data line116and a second data line216. As shown inFIG. 4, the display panel includes two source driver chips, which are a first source driver chip701and a second source driver chip702in some embodiments. The first source driver chip701is electrically connected to a plurality of first data lines116and the second source driver chip702is electrically connected to a plurality of second data lines216. The above-described two source driver chips may input different data signals to the first data lines116and the second data lines216, respectively, so as to realize the simultaneous display of a first display sub-substrate and a second display sub substrate and the displayed images are distinct. The above scheme in which the two source driver chips are disposed may also realize the separate display of a corresponding display sub-panel or the double-sided simultaneous display by cooperation with a gate drive circuit and by one of the source driver chips outputting a cutoff signal to a data line connected thereto.

As shown inFIG. 5, the first source driver chip701includes a plurality of first output ends (only one of which is shown inFIG. 5) and a plurality of second output ends (only one of which is shown inFIG. 5) in some embodiments. The first output ends of the first source driver chip701are electrically connected to the first data lines116in a one-to-one correspondence way and the second output ends of thereof are electrically connected to the second data lines216in a one-to-one correspondence way. The second source driver chip702is electrically connected to the second data lines216. When the same contents are synchronously displayed by the first display sub-substrate and the second display sub-substrate, the second source driver chip702connected to the second data lines216has no signal output, but the first source driver chip701simultaneously outputs source drive signals to the first data lines116and the second data lines216, respectively, through the first output ends and the second output ends, which improve the consistency of the signals of the first display sub-panel1and the second display sub-panel2, and further increases the consistency of the simultaneous display of the first display sub-panel1and the second display sub-panel2. In addition, only the first source driver chip701is required to be turned on upon the synchronous display, which may save energy consumption.

As shown in the figures, the light emitting device8of the display panel may be an OLED (Organic Light Emitting Diode) in some embodiments. As shown inFIGS. 6-8, the first display sub-panel1includes a first gate layer102which includes a plurality of first gate lines101, a first active layer103, a first source and drain layer104, a first anode layer105, a first luminescent layer106, and a first cathode layer107, in a direction perpendicular to the spacer layer4and pointed to the first display sub-panel1from the spacer layer4. The second display sub-panel2includes a second gate layer202which includes a plurality of second gate lines201, a second active layer203, a second source and drain layer204, a second anode layer205, a second luminescent layer206, and a second cathode layer207, in a direction perpendicular to the spacer layer4and directed from the spacer layer4to the second display sub-panel2. The display panel further includes a base substrate6, as shown inFIG. 6. The base substrate6may be located between the second cathode layer207and the second anode layer205. As shown inFIG. 7, the base substrate6may be located between the second gate layer202and the second active layer203. As shown inFIG. 8, the base substrate6may be located between the first gate layer102and the second gate layer202and the base substrate6serves as the spacer layer4. The base substrate6may also be located between the first cathode layer107and the first anode layer105or the substrate6is located between the first gate layer102and the first active layer103. The above base substrate6is used to form various functional layers on both sides thereof, respectively. In this embodiment, only one base substrate6needs to be disposed, which contributes to the reducing of a thickness of the whole display panel compared with a conventional double-sided display panel on which two base substrates6are disposed.

The above base substrate6may be a rigid base substrate6made of glass, for example, or a flexible base substrate6made of polyethylene naphthalate or polyethylene terephthalate, for example.

In some embodiments, the display panel further includes a first support member108disposed on a side of the first cathode layer107facing away from the base substrate6, and a second support member208disposed on a side of the second cathode layer207facing away from the base substrate6. The first and second support members108and208provide support between the display panel and other components (such as a polarizer) disposed on the outerside of the display panel.

In some embodiments, the first display sub-panel1includes a first liquid crystal cell and the second display sub-panel2includes a second liquid crystal cell, as shown inFIG. 9. The display panel further includes a backlight9disposed between the first display sub-panel1and the second display sub-panels2and the backlight9can emit light on both sides thereof and can be used as the spacer layer4. In a direction perpendicular to the backlight9and directed from the backlight9to the first display sub-panel1, the first display sub-panel1includes a first gate layer102which includes a plurality of first gate lines101, a first source layer103, a first source and drain layer104, a layer of a first pixel electrode113which is electrically connected to a first drain electrode, a first liquid crystal layer114, and a layer of a first common electrode112. In a direction perpendicular to the backlight9and directed from the backlight9to the second display sub-panel2, the second display sub-panel2includes a second gate layer202which includes a plurality of second gate lines201, a second source layer203, a second source and drain layer204, a layer of a second pixel electrode213which is electrically connected to a second drain electrode, a second liquid crystal layer214, and a layer of a second common electrode212.

An embodiment of the present disclosure further provides a method for manufacturing a display panel which includes the following steps:

In step S1, a base substrate6having a first surface and a second surface, which is opposite to the first surface, is provided.

In step S2, a first stacked structure is formed on the first surface.

In step S3, a second stacked structure is formed on the second surface.

The structure consisted of the first stacked structure, the base substrate6and the second stacked structure include a first display sub-panel1and a second display sub-panel2disposed opposite to each other and a plurality of single-way conducting switches3. The first display sub-panel1includes a plurality of first gate lines101and the second display sub-panel2includes a plurality of second gate lines201. The first gate lines101, the second gate lines201and the single-way conducting switches3are provided in one-to-one correspondence. Each of the single-way conducting switches3includes an input end which is electrically connected to the first gate line101corresponding thereto and an output end which is electrically connected to the second gate line201corresponding thereto. Each of the single-way conducting switches3is unidirectionally conducted from the first gate line101to the second gate line201corresponding thereto.

The method for manufacturing a display panel provided by this embodiment can achieve a beneficial effect the same as that achieved by the above-mentioned display panel, which will not be elaborated herein.

In some embodiments, the step in which the first stacked structure is formed on the first surface includes the following steps.

In step S111, a second anode layer205, a second source and drain layer204, a second active layer203, a second gate layer202, and a spacer layer4are sequentially formed on the first surface in this order.

In step S112, a plurality of through-holes5are formed in the spacer layer4and the single-way conducting switches3are formed in the through-holes5, and are electrically connected to the second gate layer202.

In step S113, a first gate layer102which is electrically connected to the second gate layer202via the single-way conducting switch3, a first active layer103, a first source and drain layer104, a first anode layer105, a first luminescent layer106, and a first cathode layer107are sequentially formed on a side of the through-hole5facing away from the base substrate6.

The step in which the second stacked structure is formed on the second surface includes:

In step S211, a plurality of openings, in which a second luminescent layer206is formed, are formed on the base substrate6.

In step S212, a second cathode layer207is formed on a surface of the second luminescent layer206facing away from the base substrate6.

During the forming of the above functional layers, an insulating layer or a passivation layer is also formed between them to perform the insulation and protection of the functional layers. In specific implementation, referring toFIG. 6, during the forming of the first stacked structure on the first surface of the base substrate6, first, the second anode layer205is formed on the first surface. Subsequet to the forming of a desired pattern of the second anode layer205by an etching process or the like. A second passivation layer210is formed on the second anode layer205and a via-hole is formed at a position corresponding to the second anode layer205in the second passivation layer210. The second source and drain layer204is further formed on the second passivation layer210and the second drain electrode is connected to the second anode layer205through the via-hole. Subsequent to the obtaining of the desired pattern of the second source and drain layer204by etching or the like, an insulating layer is formed on the second source and drain layer204, and a via-hole is formed at a position corresponding to the pattern of the second source and drain layer204in the insulating layer. The second active layer203is formed on the insulating layer and the second active layer203is connected to a second source electrode and the second drain electrode through the via-hole in the insulating layer. A second insulating layer211is formed on the second active layer204and the second gate layer202is then formed on the second insulating layer211. The spacer layer is formed on the second gate layer202subsequent to the forming of the desired pattern of the second gate layer202. The through-holes5are formed in the spacer layer4and the single-way conducting switches3are formed in the through-holes5and are electrically connected to the second gate layer202. The first gate layer102is formed on a side of the through-hole5facing away from the base substrate6and a first insulating layer111is then formed on the first gate layer102. Thereafter, the first active layer103and an insulating layer are sequentially formed on the first insulating layer111and a via-hole is formed in the insulating layer. The first source and drain layer104is formed on the insulating layer and a first source electrode is connected to the first active layer103through the via-hole while a first drain electrode is connected to the first active layer103through another via-hole. A first passivation layer110is formed on the first source and drain layer104and a via-hole is formed at a location corresponding to the first drain electrode in the first passivation layer110. The first anode layer105is formed on the first passivation layer110and is connected to the first drain electrode through the via-hole. After a desired pattern for the first anode layer105is formed by processes such as exposure and etching, an insulating layer is formed on the first anode layer105and an opening is formed at a location corresponding to a first anode in the insulating layer. Thereafter, a first pixel defining layer109is formed over the insulating layer and an opening, in which the first luminescent layer106is formed, is formed at a position corresponding to the first anode in the first pixel defining layer109. Finally, the first cathode layer107is formed on the first luminescent layer106.

The fabricated first surface of the base substrate6is flipped down to allow the second surface of the base substrate6to face upward. During the forming of the second stacked structure on the second surface of the base substrate6, a plurality of openings are first formed on the base substrate6and a second pixel defining layer209is formed on the second surface of the base substrate6and openings are also formed at positions corresponding to the openings of the base substrate6in the second pixel defining layer209and a second luminescent layer206is formed in the openings of the base substrate6and the second pixel defining layer209. Finally, the second cathode layer207is formed on a surface of the second luminescent layer206facing away from the base substrate6.

Referring toFIG. 7, in some embodiments, the step in which the first stacked structure is formed on the first surface includes the following steps.

In step S121, a second gate layer202and a spacer layer4are sequentially formed on the first surface.

In step S122, a plurality of through-holes5are formed in the spacer layer4and a plurality of single-way conducting switches3are formed in the through-holes5and are electrically connected to the second gate layer202.

In step S123, a first gate layer102, a first active layer103, a first source and drain layer104, a first anode layer105, a first luminescent layer106, and a first cathode layer107are sequentially formed on a side of the through-holes5facing away from the base substrate6, wherein the first gate layer102is electrically connected to the second gate layer202through the single-way conducting switch3.

The step in which the second stacked structure is formed on the second surface includes the following steps.

In step S221, a second active layer203, a second source and drain layer204, a second anode layer205, a second luminescent layer206, and a second cathode layer207are sequentially formed on the second surface.

In the steps above, a plurality of insulating layers or passivation layers are also formed during the forming of the functional layers and a principle for the forming of the layers refers to the description of the forming of the layers in the embodiment shown inFIG. 6.

Referring toFIG. 8, in some embodiments, the step of forming the first stacked structure on the first surface includes the following steps.

In step S131, a plurality of through-holes5are formed in the base substrate6and a plurality of single-way conducting switches3are formed in the through-holes5.

In step S132, a first gate layer102, a first active layer103, a first source and drain layer104, a first anode layer105, a first luminescent layer106, and a first cathode layer107are sequentially formed on the first surface, wherein the first gate layer102is electrically connected to the single-way conducting switches3.

The step of forming the second stacked structure on the second surface includes the following steps.

In step S231, a second gate layer202, a second active layer203, a second source and drain layer204, a second anode layer205, a second luminescent layer206and a second cathode layer207are sequentially formed on the second surface, wherein the second gate layer202is electrically connected to the single-way conducting switches3.

An embodiment of the present disclosure further provides a method for driving a display panel, which is used for driving the display panel as described above. The driving method includes: when a first display sub-panel1and a second display sub-panel2are simultaneously displayed, inputting a first gate scan signal to a first gate line101of the first display sub-panel1and enabling the display of the first display sub-panel1; and the first gate scan signal driving a corresponding single-way conducting switch3to be unidirectionally turned on from the first gate line101to a second gate line201of the second display sub-panel2, and allowing the simultaneous display of the second display sub-panel2and the first display sub-panel1. The method for driving a display panel provided by this embodiment can achieve a beneficial effect the same as that achieved by the above-mentioned display panel, which will not be elaborated herein.

Hereinafter, the driving method for the display panel will be described in detail by taking an example in which the gate drive circuit is a GOA unit. The technical solution of the gate drive circuit serving as a gate driver chip is also included in the protection scope of the present disclosure.

In specific implementation, a first GOA unit provides a first gate scan signal to a first gate line101while a second GOA unit outputs no signal or a cutoff signal to a second gate line201, so that a single-way conducting switch3has a voltage difference between both ends thereof and the single-way conducting switch3is unidirectionally conducted from the first gate line101to the second gate line201of the second display sub-panel2, so as to synchronize the input of the first gate scan signal to the second gate line201with that to the first gate line101and achieve the simultaneous display of the first display sub-panel1and the second display sub-panel2.

In order to better ensure the stabilization of a signal pressure of second gate electrodes connected to the second gate lines201during the synchronous display, in some embodiments, the second display sub-panel2further includes a plurality of voltage stabilizing resistors R which are disposed in a wiring area of the second display sub-panel2, as shown inFIG. 1. The voltage stabilizing resistors R and the single-way conducting switches3are disposed in one-to-one correspondence and each of the voltage stabilizing resistors R has one end which is electrically connected to the second GOA unit corresponding thereto and the other end which is electrically connected to the output end of the single-way conducting switch3corresponding thereto. When the simultaneous display of the first display sub-panel1and the second display sub-panel2is performed, a first gate scan signal is input to the first gate lines101of the first display sub-panel1, to enable the display of the first display sub-panel1. The voltage stabilizing resistors R are conducted and the first gate scan signal drives the single-way conducting switch3corresponding thereto to be unidirectionally conducted from the first gate line101to the second gate line201of the second display sub-panel2, so as to achieve the synchronous display of the second display sub-panel and the first display sub-panel. That is to say, a first gate scan signal is outputted from the first GOA units, but no signal or only a cutoff signal is outputted from the second GOA units. The single-way conducting switch3corresponding to them, at this time, has a voltage difference between its input end and output end, so the single-way conducting switch3is turned on. When there is no voltage stabilizing resistor R provided, since no signal or only a cutoff signal is outputted from the second GOA units, voltage at the output end of the single-way conducting switch3is pulled down and voltage of each of the second gate electrodes to which the second gate line201is connected is pulled down to be lower than a turn-on voltage of the second gate electrode, so that the second gate electrode cannot be turned on. When a voltage stabilizing resistor R is provided, the voltage stabilizing resistor R remains conducted when the synchronous display is performed. A appropriate type of resistor may be selected to maintain voltage inputted to each of the second gate electrodes at an appropriate value, which is neither higher than voltage of the first gate scan signal to unable to conduct the single-way conducting switch nor lower than the turn-on voltage of each of the second gate electrodes, so as to ensure the normal turn-on of each of the second gate electrodes and smoothly realize the double-sided synchronous display.

In some embodiments, the driving method further includes: when the first display sub-panel1and the second display sub-panel2display different screens, inputting a first gate scan signal V1to the first gate line101of the first display sub-panel1to realize the display of a first screen of the first display sub-panel1; inputting a second gate scan signal V2to the second gate line201of the second display sub-panel2and V1−V2<Von, wherein Vonis a forward turn-on voltage of the single-way conducting switch3and the second display sub-panel2displays a second screen. In specific implementation, the first gate scan signal V1may be input to the first gate lines101by the first GOA units in a one-to-one correspondence way while the second gate scan signal V2may be input to the second gate lines201by the second GOA units in a one-to-one correspondence way. When V1−V2<Von, the single-way conducting switch3cannot be reversely conducted, the first gate electrodes connected to the first gate lines101are turned on and the second gate electrodes connected to the second gate lines201are turned on. A first data signal is input to first data lines116through a first source starting chip in the first display sub-panel1and a second data signal is input to second data lines216through a second source starting chip in the second display sub-panel2, so as to realize the simultaneous display of the two display sub-panels to display different screens.

In some embodiments, the driving method for the display panel further includes: when the first display sub-panel1displays a screen but the second display sub-panel2displays no screen, inputting a first gate scan signal to the first gate line101of the first display sub-panel1to allow the first display sub-panel1to display a first screen; and inputting a cutoff signal to the second gate line201of the second display sub-panel2to pull down a signal on the second gate line201and, thus, the second display sub-panel2does not display any screen. In a specific implementation, the display panel further includes a plurality of short-circuit branches217disposed in the wiring area of the second display sub-panel2. The short-circuit branches217are disposed in one-to-one correspondence to the voltage stabilizing resistors R and each of the short-circuit branches217is connected in parallel to both ends of the voltage stabilizing resistor R corresponding thereto. The second display sub-panel2further includes a plurality of second data lines216. Two output ends are disposed in the second GOA unit, wherein the first output end is connected to the voltage stabilizing resistor R and the second output end is connected to the short-circuit branch217. On or off of the first output end and the second output end is controlled by a circuit and a clock signal within the second GOA unit, so as to control turn-on or turn-off of the voltage stabilizing resistor R and the short-circuit branch217. When the short-circuit branch217is conducted, the voltage stabilizing resistor R is short-circuited and since the second GOA unit has no signal output or only outputs a cutoff signal, voltage at the output end of the single-way conducting switch3is pulled down, so that voltage of the second gate electrodes connected to the second gate lines201is pulled down. When the voltage is lower than the turn-on voltage of the second gate electrodes, the second gate electrodes cannot be turned on, so that the second display sub-panel2fails to display a screen, but the first GOA unit normally inputs a first gate drive signal to the first gate lines101, to allow the normal display of a screen of the first display sub-panel1.

It should be noted that in an embodiment in which a short-circuit branch217are provided, upon the simultaneous display of the first display sub-panel1and the second display sub-panel2, the voltage stabilizing resistor R is conducted but the short-circuit branch217is disconnected so as to ensure the normal operation of the voltage stabilizing resistor R.

When the first display sub-panel1displays a screen but the second display sub-panel2does not display any screen, a first gate scan signal may be input to the first gate line101of the first display sub-panel1to enable the display of a first screen of the first display sub-panel1, however, the second data line216of the second display sub-panel2has no signal input thus the second display sub-panel2fails to display any screen. That is to say, the first GOA unit supplies a first gate scan signal to the first gate line101and the first source driver chip701supplies a first data signal to the first source electrode connected to the first data line116, to realize the display of the first display sub-panel1. The second GOA unit supplies a second gate scan signal to the second gate line201and the second source driver chip702does not supply any data signal to the second source electrode connected to the second data line216, so the display of the second display sub-panel2is not performed.

In some embodiments, the driving method further includes: when the first display sub-panel1does not display any screen, but the second display sub-panel2displays a screen, inputting no signal or a cutoff signal V3to the first gate line101of the first display sub-panel1; inputting a second gate scan signal V2to the second gate line201of the second display sub-panel2, wherein a difference of V2−V3is less than a reverse breakdown voltage of the single-way conducting switch3, so the display of the second display sub-panel2is performed. That is to say, the first GOA unit outputs no signal or a cutoff signal V3to the first gate line101corresponding thereto, but the second GOA unit outputs a second gate scan signal V2to the second gate line201corresponding thereto. The single-way conducting switch3corresponding to the second gate line201, at this time, is not conducted, and the difference of V2−V3is smaller than the reverse breakdown voltage of the single-way conducting switch3, so the display of a screen of the second display sub-panel2is performed, but the display of a screen of the first display sub-panel1is not performed.

An embodiment of the present disclosure also provides a display device including the display panel as described above. The display device may be an OLED display device, a liquid crystal display device, a PM-OLED (Passive Matrix Organic Light Emitting Diode) display device, an AM-OLED (Active Matrix Organic Light Emitting Diode) display device, a Micro-OLED (Organic Light Emitting Diode Microdisplay Technology) display device, a QLED (Quantum Dot Light Emitting Diodes) display device, and the like. During specific implementation, the display device may be products or components having a display function such as mobile phones, tablets, televisions, monitors, notebook computers, digital photo frames, and navigators which perform a double-sided display.

The display device provided by the embodiment of the present disclosure can achieve a beneficial effect the same as that achieved by the above-mentioned display panel, which will not be elaborated herein.

The above-described contents are only specific embodiments of the present disclosure and the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or substitutions that fall into the protection scope of the present disclosure within the technical scope of the disclosure of the present disclosure. Therefore, the protection scope of the present disclosure should be determined by the protection scope of the claims.