Reducing parasitic mutual capacitances

A method to reduce parasitic mutual capacitances in embedded passives. A first capacitor is formed by first and second electrodes embedding a dielectric layer. A second capacitor is formed by third and fourth electrodes embedding the dielectric layer. The third and first electrodes are etched from a first metal layer. The fourth and second electrodes are etched from a second metal layer. The first and the fourth electrodes are connected by a connection through the dielectric layer to shield a mutual capacitance between the first and second capacitors.

BACKGROUND

1. Field of the Invention

Embodiments of the invention relate to the field of electronic fabrication, and more specifically, to capacitor fabrication.

2. Description of Related Art

Embedded Passives (EP) technology has been increasingly popular in manufacturing radio frequency (RF) communication devices. Passive components such as resistors, capacitors, and inductors, typically contribute a significant portion of the number of components used in wireless and mobile miniature modules. System on chip (SOC), system in package (SIP), or system on package (SOP) utilizing EP technology provides a high degree of integration of passive components.

Capacitors used in RF devices have a significant impact on device performance. When RF functional blocks with lumped elements are built on package, the parasitic mutual capacitances among the capacitors are inevitable. Such parasitic mutual capacitances may cause unwanted component coupling and degrade the electrical performance. Existing techniques to reduce these unwanted mutual capacitances have a number of disadvantages. One technique is to increase the distances of the capacitors. This technique is not effective in reducing mutual capacitances. In addition, it results in increased package form factor.

DESCRIPTION

An embodiment of the present invention is a technique to reduce parasitic mutual capacitances in embedded passives. A first capacitor is formed by first and second electrodes embedding a dielectric layer. A second capacitor is formed by third and fourth electrodes embedding the dielectric layer. The third and first electrodes are etched from a first metal layer. The fourth and second electrodes are etched from a second metal layer. The first and the fourth electrodes are connected by a connection through the dielectric layer to shield a mutual capacitance between the first and second capacitors.

In the following description, numerous specific details are set forth. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown to avoid obscuring the understanding of this description.

One embodiment of the invention may be described as a process which is usually depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. Although a flowchart may describe the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed. A process may correspond to a method, a program, a procedure, a method of manufacturing or fabrication, etc.

Embodiments of the invention include adjacent capacitors having a connection to reduce the unwanted parasitic mutual capacitance caused by the coupling between the capacitors. The technique is simple to implement, reduces package form factor, and enhances electrical performance.

FIG. 1is a diagram illustrating a system100in which one embodiment of the invention can be practiced. The system100represents a mobile communication module. It includes a system on package (SOP)110, an intermediate frequency processing unit160, and a base-band processing unit165.

The SOP110represents the front end processing unit for the mobile communication module. It is a transceiver incorporating on-package integrated lumped passive components as well as RF components. It includes an antenna115, a duplexer120, a filter125, a system-on-chip (SOC)150, a power amplifier (PA)180, and a filter185.

The antenna115receives and transmits RF signals. It is designed in compact micro-strip and strip-line for L and C-band wireless applications. The duplexer120acts as a switch to couple to the antenna115to the receiver and the transmitter to the antenna115. The filters125and185are C-band LTCC-strip-line filter at 5.8 GHz and narrowband performance of 200 MHz suitable for the Institute of Electrical and Electronic Engineers (IEEE) 802.11 wireless local area network (WLAN). The SOC150includes a low noise amplifier (LNA)130, a down converter135, a local voltage controlled oscillator (VCO)140, an up converter170, and a driver amplifier175. The LNA130amplifies the received signal. The down converter135is a mixer to convert the RF signal to the IF band to be processed by the IF processing unit160. The up converter170is a mixer to convert the IF signal to the proper RF signal for transmission. The VCO140generates modulation signal at appropriate frequencies for down conversion and up conversion. The driver amplifier175drives the PA180. The PA180amplifies the transmit signal for transmission.

The IF processing unit160includes analog components to process IF signals for receiving and transmission. It may include a band-pass filter and a low pass filter at suitable frequency bands. The base-band processing unit165may include analog-to-digital converter (ADC) and digital-to-analog converter (DAC) to convert analog signal to digital data and vice versa. It may include a digital processor with memory and peripheral components to process digital data.

The SOP110may be a multi-layer three-dimensional (3D) architecture for a monolithic microwave integrated circuit (MMIC) with EP technology. It may be implemented using Low Temperature Co-fired Ceramics (LTCC) and organic-based technologies. The 3D architecture may include multiple layers include a layer10to implement the planar antenna115, layers20,22, and24for the filters125and185, and layer30for the SOC150, monolithic microwave integrate circuits (MMICs), and the passive components using EP technology. In particular, the EP includes lumped capacitors35with shielding technique to reduce unwanted mutual capacitances.

Parasitic mutual capacitances are caused by the coupling of adjacent capacitors. These capacitances may degrade electrical performance. Other mutual coupling between inductors and capacitors may also exist. The techniques in embodiments of the invention reduce the undesired effects caused by these mutual capacitances.

FIG. 2Ais a diagram illustrating a design of capacitors sharing a common ground according to one embodiment of the invention. The design shows a traditional layout200and an improved layout220.

The traditional layout200illustrates a top view and a cross sectional view of capacitors that share a common ground. It includes an electrode210and three electrodes212,214, and216. The electrodes212,214, and216and the electrode210embed a dielectric layer218to form three capacitors201,202, and203sharing a common terminal. These capacitors are adjacent to each other causing unwanted parasitic mutual capacitances204and205. The mutual capacitance204is caused by the coupling between capacitors201and202. The mutual capacitance205is caused by the coupling between capacitors202and203.

The improved layout220illustrates a top view and a cross sectional view of a new improved design of capacitors. The design uses shielding to block the coupling between adjacent capacitors, resulting in reduced parasitic mutual capacitance. It includes an electrode230and three electrodes232,234, and236, and via connections242and244. The electrode230has a center portion raised above the electrode234. The electrodes232and236are similar to the electrodes212and216in the traditional layout200. The electrode234is below the center portion of the electrode230. These electrodes embed a dielectric layer238to form three capacitors221,222, and223. The mutual capacitance224is caused by the coupling between capacitors221and222. The mutual capacitance225is caused by the coupling between capacitors222and223.

The via connections242and244provide connections between the center portion of the electrode230and its two side portions using vias formed through the dielectric layer238. In effect, the via connection242acts as a shield to block the coupling between the capacitors221and222. Due to this shielding, the mutual capacitance224is significantly reduced. Similarly, the via connection244blocks the coupling between the capacitors222and223, leading to a reduction of the mutual capacitance225.

FIG. 2Bis a diagram illustrating a design of series capacitors according to one embodiment of the invention. The design shows a traditional layout250and an improved layout270.

The traditional layout250illustrates a top view and a cross sectional view of series capacitors. It includes electrodes260,262,264, and266. The electrodes260,262,264, and266embed a dielectric layer268to form three capacitors251,252, and253in series. These capacitors are adjacent to each other causing unwanted parasitic mutual capacitances254and255. The mutual capacitance254is caused by the coupling between electrodes264and266. The mutual capacitance255is caused by the coupling between the electrodes260and262.

The improved layout270illustrates a top view and a cross sectional view of a new improved design of capacitors. The design uses shielding to block the coupling between adjacent capacitors, resulting in reduced parasitic mutual capacitance. It includes electrodes272,274,276,282,284, and286and via connections292and294. These electrodes embed a dielectric layer288to form three capacitors271,272, and273in series. The mutual capacitance274is caused by the coupling between the electrodes282and286. The mutual capacitance275is caused by the coupling between the electrodes272and276.

The via connections292and294provide connections between the electrodes272and284and between the electrodes274and286, respectively, using vias formed through the dielectric layer238. In effect, the via connections292and294act as a shield to block the coupling between the capacitors271and272. Due to this shielding, the mutual capacitances274and275are significantly reduced.

FIG. 3Ais a diagram illustrating a layout300of capacitors with via connection according to one embodiment of the invention. The layout300includes metal layers310and320, and a dielectric layer330.

The metal layer310has a first electrode312and a third electrode314. The metal layer has a second electrode322and a fourth electrode324. These electrodes embed the dielectric layer330to form a first capacitor301and a second capacitor302. The first capacitor301includes the first and second electrodes312and322. The second capacitor302includes the third and fourth electrodes314and324. The first and second capacitors301and301may be formed in the build-up layer on a core layer. A via connection335is formed between the first and fourth electrode312and324. The via connection335acts as a shield to block the coupling between the first and second capacitors301and302. This blocking results in reduced parasitic mutual capacitance between the two capacitors.

Typically, the use of via connection to reduce mutual capacitance is more suitable for capacitors with small capacitances. Therefore, the dielectric layer330is made of a dielectric material of low dielectric constant k (e.g., k<3). However, depending on the process, the dielectric layer330may also have a high dielectric constant (e.g., k>10).

FIG. 3Bis a diagram illustrating a layout350of capacitors with ribbon connection according to one embodiment of the invention. The layout350includes metal layers360and a dielectric layer375.

The metal layer360includes a first electrode362and a third electrode366. Within the dielectric layer375are a second electrode364and a fourth electrode368. These electrodes are etched from a metal layer (not shown). The first and second electrodes362and364embed a dielectric layer382having a high dielectric constant k to form a first capacitor351. The third and fourth electrodes366and368embed a dielectric layer384having a high dielectric constant k to form a second capacitor352. A ribbon386is formed between the first and fourth electrodes362and368. Vias372,374, and376are formed to provide connections between the first and second capacitors351and352to the metal layer370.

The ribbon386acts like a shield to block the coupling between the first and second capacitors351and352, leading to a reduction in parasitic mutual capacitance between the two capacitors. Typically, the use of ribbon connection to reduce mutual capacitance is more suitable for capacitors with large capacitances. Therefore, the dielectric layers382and384are made of a dielectric material of high dielectric constant k, e.g., k>10. However, depending on the process the dielectric material may also have low dielectric constant k, e.g., k<3.

Simulation data show that the reduction of mutual capacitance may be around 20 dB over a frequency range of 1 GHz to 10 GHz. In addition, the ratio between the mutual capacitance and the self capacitance is reduced to approximately 1.6% for capacitors with shielding from 3.7%-13% for capacitors without shielding.

FIG. 4is a diagram illustrating a process500of fabrication of capacitors according to one embodiment of the invention.

Upon START, the process400prepares a core layer having metal (e.g., copper) front layer and bottom layer embedding the core layer (Block410). Then, the process400coats a dielectric layer on the metal front layer and bottom layer (Block420). The dielectric layer may be made of a dielectric material having a low or high dielectric constant. Next, the process400deposits a metal (e.g., copper) layer on the dielectric layer (Block430).

Then, the process400patterns and etches the metal layers to expose the dielectric layer to form at least two adjacent capacitors, each having two electrodes embedding the dielectric layer (Block440). The capacitors are formed in the build-up layer on the core layer. Next, the process400develops the dielectric layer and cures the two capacitors (Block450). Then, the process400forms a via or a ribbon connection to connect the bottom electrode of the first capacitor to the top electrode of the second capacitor (Block460). The connection serves as a shield to reduce the parasitic mutual capacitance between the two capacitors. The process400is then terminated.