Methods and systems for transposition channel routing

Systems and assemblies are provided for transposition channel routing where the characteristics of an escape route can be modified on a printed circuit board (PCB) in a manner that reduces crosstalk and realizes significant signal quality improvement. The techniques involve “transposition” of a signal line pair on the PCB, reduces effect coupling coefficients for individual aggressor signals, thereby reducing the crosstalk. Transposition channel routing techniques can also be applied to other areas on a PCB (e.g., other than escape routes) where space is constrained and other mitigation techniques are not possible. The PCB can include an array of contact pads, a plurality of signal line pairs that include an escape route. One or more transposition junctions disposed within the escape route can route a signal line pair from a first routing channel in the escape route into a second routing channel in the escape route.

DESCRIPTION OF RELATED ART

Escape routing generally refers to a pattern and method used to route the I/O pads or solder bumps on a die (or package) to the lines that can escape to the area surrounding the die to be routed out of the package or its immediate surroundings. Particularly with circuits that implement memory circuits that use double data rate (DDR) and quadruple data rate (QDR) standards, the integrated circuits (IC) chips often require high frequency data transmission links that provide low bit error rate (BER), high bandwidth and low on-chip latency.

Accordingly, escape routing techniques for printed circuit boards (PCBs) that implement memory circuits, must take into account such factors as: increased package size, increased channel bandwidth, smaller signal levels, and decreased via and pad spacing. This is in addition to factors that are frequently design considerations in conventional escape routing techniques, such as: ball pitch; land diameter; number of I/O pins; via type; pad size; trace width/spacing; and the number of layers required to escape the PCB.

DETAILED DESCRIPTION

Various embodiments described herein are directed to improved escape routing techniques for printed circuit boards (PCBs) implementing electronics that require high data rate channel buses, such as double data rate 5 (DDR5) memory modules. According to the embodiments, multiple physical characteristics of the escape route can be modified on the PCB in a manner that reduces crosstalk and realizes significant signal quality improvement. The improved escape routing techniques can involve adding interconnects, such as micro-vias, to the electrical trace layout that can be used for the “transposition” of the signal routing channels on the PCB. Transposing channels, as disclosed herein, effectuates a transposition of the relationship between two aggressor signals in a manner that reduces the effect coupling coefficients for individual aggressors. Accordingly, the disclosed transposition channel routing techniques can achieve reduced crosstalk by partially cancelling coupled signal lines in a channel, which otherwise may cause an unwanted transfer of signals between the channels on the PCB.

The various mechanisms and techniques of the disclosed embodiments may be referred to herein as transposition channel routing. As a general description of the techniques, one or more signal lines can be transposed, or repositioned, from a routing layer to another routing layer using micro-vias at designated transposition junctions along an escape route. The transposition of signal lines can add a second period to the via crosstalk term, reducing the peak accumulated via crosstalk by changing the phase relationship of the accumulated coupled signal. Additionally, a peak accumulated signal may be reduced by implementing the disclosed transposition channel routing techniques.

Furthermore, although the transposition channel routing techniques are described with respect to escape routing for purposes of discussion, it should be appreciated that the disclosed techniques can also be applied to areas on a PCB where space is constrained and other mitigation techniques are not possible. In other words, escape routing is one example of a practical application of the transposition channel routing techniques, as disclosed herein.

FIG.1Ashows an example configuration for a PCB104where the disclosed transposition channel routing can be employed. As referred to herein, a PCB is a structure that mechanically supports and electrically connects electrical (or electronic) components using conductive tracks, pads and other features etched from sheet layers of conductive material (e.g., copper) laminated onto and/or between sheet layers of a non-conductive substrate. Although PCBs are discussed herein for purposes of illustration, it should be appreciated that the disclosed techniques can be applied to other types of electrical circuitry elements, such as printed circuit assemblies (PCAs), printed circuit board assemblies (PCBA5), circuit card assemblies (CCAs), and the like. In the example, the PCB104has circuitry to implement an electronic device100including a DDR5 memory modules102. As background, electronic devices typically contain memory for storing data and software instructions. Such memory is typically provided between secondary storage (usually implemented with a disk-based storage device) and a central processing unit (CPU) of the electronic device. The memory can be implemented with dynamic random access memories (DRAMs). There are various different types of DRAMs, including synchronous DRAMs (SDRAMs) and double data rate (DDR) DRAMs (defined by standards set by JEDEC). The original DDR SDRAM standard has been superseded by later established standards, such as DDR5.

In the illustrated example, the PCB104can be configured to include high data rate channels, which are typically required for memory modules, such as a DDR5, to function optimally. For example, as a DDR5 memory, the memory module120can support data rates of approximately mega-transfers-per second (MT/s) with a fundamental frequency content of 2400-3200 mhz, thereby having increased performance and bandwidth. In order to accommodate such high data rate channels on the PCB104, the disclosed transposition channel routing techniques can be used as a form of improved escape routing. Channels on the PCB104may be especially impacted by the particular escape routing that is employed, since as opposed to other signals, DDR5 channel buses are often required to be routed with minimal skew. For instance, escape routing on a PCB with high data rate channels, such as a PCB104, may be impacted by multiple factors in the chips' design, including but not limited to:1) increased package size, lengthening the channel escape routes from under the package;2) increased channel bandwidth, lowering signal to noise ratio, increasing channel losses, and increasing lane to lane coupling; and3) decreased via and pad spacing, moving traces closer together.

Also,FIG.1Adepicts that the PCB104can include multiple components112a,112b, also referred to herein as devices (e.g., processors, input/output controllers, memory controllers, bridge devices, etc.), that are mounted on a surface of the PCB104. The PCB104can also include a connector114of the memory module102. As shown, the memory module102is implemented as a dual in-line memory module (DIMM), which may be designed for use by PCs and servers. A DIMM is made up of a series of dynamic, random-access memory integrated circuits (ICs). These modules are mounted on the PCB104via the connector114, which is illustrated as a DIMM connector (having an vertical orientation). One function of DIMM connector114is to stably hold the DIMMs once mounted, and route signals vertically between ICs (on the DIMM) and PCB104. In some cases, the connector114may be connected to the PCB104via an interposer or packaged using a ball grid array (BGA).

As shown, the memory module102may be mounted in the connector114, which includes a mechanical system such as a cavity in which an IC fits and a retention chip or a lever system for holding IC in place. Although the memory module102is described as a DDR5 memory module for purposes of illustration, it should be appreciated that the memory module102can be another type of memory module, such as a DDR SDRAM, DDR2, DDR3, DDR4, or a memory module having multiple DRAMs. Accordingly, transposition channel routing is applicable to various types of technologies having high data rate channels on circuit boards, such as a PCB. Memory channels, as disclose above, serve as an example of a specific technology which benefits from the disclosed techniques.

The memory module102can include memory devices106that are mounted to a first surface105of the memory module102. The memory module102further has an opposite surface (on the other side of the memory module102that is not visible in the view ofFIG.1A) on which additional memory devices can be mounted. The memory devices106can include packaging, e.g., flip-chip packaging, that provides an array of pins (or terminals) for electrical connections. Data input into a memory device106is stored in memory cells of that memory device106. In one example, the memory devices106can have a ×4 data pin configuration (in which four data pins are used). The data pins of the memory devices106are interconnected by conductive lines108on the memory module102. The conductive lines108can be implemented as conductive traces on the memory module102.

As alluded to above, the DDR5 may require the PCB104to have high density electrical traces around the connector114for the IC implementing the memory module102. As an example, some of the traces in the PCB104may need to route signals that exit on one side of the component112b(shown as an IC chip) to connect to the connector114(shown on the opposite side of the PCB104). Thus, the PCB104may need many layers to route traces that cross under the IC of the component112band the connector114. As an example, the component112bcan be implemented as an IC chip device (e.g., CPU) having an ASIC with an associated chip substrate. Under the ASIC for the component112bmay be a socket. The combination of the packaged chip and potential socket for the device112b, can then be assembled to the PCB104. A close-up (indicated by dashed circle) illustrating a mounting side of the ASIC (or IC chip) implementing the component112bis shown.

As seen in the close-up section ofFIG.1A, the component112bcan be a surface-mount package with one side (e.g., mounting side) of the package having an array of pads131(I/O contacts) on its bottom surface, where each pad has a solder ball attached thereto. Bottom pads131(e.g., on the BGA) can be arranged in a pattern matching the pattern of pads132on the PCB104. The pattern of bottom pads131may match the pattern of top pads132on the PCB104, such that the bottom pads131of the packaging are directly connected to corresponding top pads132of the PCB104by vertical conductive vias. In some cases, the pattern of bottom pads131may include a scaling to a larger pitch or contact size than used for pads132on the PCB104, or may be different from the pattern of pads132. In particular, top pads132of the PCB104that are adjacent to each other may respectively be connected to bottom pads131on the that are adjacent, thereby causing their respective connecting vias to also be adjacent. The array of pads131(or contacts) make electrical connections to respective pads in an array on PCB104, and a conductive network of vias, traces, or other electrical routings that connect top contacts to bottom contacts. In this example, transposition channel routing can be implemented using a pattern of signal lines beneath the component112brouted out of its immediate surroundings, in adjacent layers between the connector114and the component112bon the PCB104.

The routes on the PCB104can start under component112bfor the disclosed techniques. The routes may propagate to the connector114connecting the memory module102(i.e., DIMM). That is, the transposition channel routing techniques disclosed herein can be applied to routes that flow from device112bto the connector114of the memory module102(i.e., DIMM), and it is in that region of the PCB104where the transposition channel routing occurs.

As alluded to above, routing of signals from beneath the device112bcan provide routings to the ICs of the memory module102, and to devices112aon the other side of the PCB104. For example, signal lines133routed in between an IC package (or socket) layer and a PCB104can escape outside the footprint of the IC chip packaging (or outside the main chip cavity) for the component112b. As will be described in further detail, the signal lines133on the PCB104may be arranged as multiple pairs of signal lines (e.g., two signal lines running parallel to each other) that are particularly routed to travel the same channel (either above or below) around adjacent pads132in a layer, as an escape route. The transposition routing techniques can involve physically transposing the signal lines133, namely repositioning the signal lines133from a routing channel (e.g., running in a layer below a pad) to a transposition channel (e.g., interconnected to the routing channel using micro-vias) for, at least, a partial length of the escape route. Details of transposition signal routing are shown and described in reference toFIG.3. As referred to herein, a transposition channel can be a routing channel that is particularly used for directing the electrical traces that have been “transposed” to a different routing channel from their initial routing channel in the escape route.

Furthermore, the component112b, being an IC that is socket-mounted on the PCB104, can communicate to other devices (e.g., component112a) through electrically conductive traces formed in and on the PCB104. With respect to routing, the area of the PCB104under the component112band the connector114for memory module102may provide space for traces or routings that may extend beyond the boundaries of their respective ICs. Accordingly, the transposition channel routing techniques can be implemented in spaces of the PCB104having electrical traces connecting the component112bto other devices.

FIG.1Bdepicts an example of another circuitry configuration150, shown as ASIC151to ASIC157, in which the disclosed transposition routing techniques can be implemented. Particularly,FIG.1Bshows that the transposition signal routing techniques can be implemented in a constrained open field section of the PCB (as opposed to an escape route from beneath a socket, IC chip, and the like as shown inFIG.1A). In the illustrated example ofFIG.1B, a first ASIC151and a second ASIC157are shown to be disposed on distal ends of a circuit substrate, shown as PCB160. Further, close-up views illustrate the multiple electrical traces, or signal lines153, that can be routed from the areas on the PCB160where the ASICs151,157are mounted. Specifically, the signal lines153are routed as traces that connect ASIC151on one side of the PCB160to ASIC157on the opposing end of the PCB160. Also, shown is a constrained open field155section of the PCB160. As shown, the constrained open field155is a section of open space on the PCB160in between the ASICs151,157. The signal lines153are routed through the constrained open field155such that that form traces which connect the ASICs151,157on the board. For example, the signal lines153can be described as running from the ASIC151(on the left) through the constrained open field155and terminating at the ASIC157(on the right), or vice versa.

In this configuration, the disclosed transposition channel routing techniques can be implemented within the constrained open field155. As will be described in further detail, the signal lines153on the PCB160may be arranged as multiple pairs of signal lines (e.g., two signal lines running parallel to each other) as they traverse the constrained open field155. Consequently, applying transposition channel routing to the signal lines153approximately for the length of the traces through the constrained open field155can transpose the pairs of signal lines153from a routing channel126to a transposition channel127. As shown, multiple micro-vias125can be used as interconnections for “transposing” the signal lines153from their respective routing channel126to a transposition channel127(which may be on a different layer of the PCB160than the routing channel126). This transposition of the signal lines153also transposes the relationship between the two aggressor signals to partially cancel the coupled signals of the signal line pair, and reduces crosstalk. Additionally, transposition routing of signal lines153in the constrain open field155area can change the phase relationship of the accumulated coupled signal (from interaction of the signal line pairs) on the signal lines153up to that point (e.g., start of transposition at the transposition junction).

FIG.2depicts a portion of a typical escape routing pattern200that can be arranged on a substrate, such as a PCB (shown inFIG.1A). The vertical columns of the pattern200can represent “layers” of semi-conductive components mounted on the PCB (e.g., BGA, sockets, ICs, etc.), and the horizontal can represent “rows” that run along the horizontal plane of the PCB, which is also referred to herein as the “length” of the escape routing pattern200. Also shown, is an array of various contact points2201a-2205f, which represent a pattern of solder balls, vias, or conductive pads, on the corresponding IC packaging or substrate. In some cases, the array of contact points2201a-2205fis configured to match (in number and shape) the corresponding pattern of pads (or balls) on the IC package to which it will be mounted.

As can be seen, signal lines210a-213b(also referred to as “metal traces” or “trace”) exit from the periphery contacts2201a,2202a,2203a,2204a, and2205a(on the right side) and contacts2201f,2202f,2203f,2204f, and2205f(on the left side) that are adjacent the outer edges of the escape routing pattern200. More particular, the signal lines210a-213bare arranged into pairs at each layer of the pattern200. Further, these pairs of signal lines run parallel to each other, traversing the same route across the full length of the escape routing pattern200. For instance, in the illustrated example, signal lines210a,210bare positioned parallel to each other (with signal line210adirectly above signal line210b), being routed horizontally along the first row (or layer) of the pattern200, between contacts2201a,2201b,2201c,2201d,2201e, and2201fand2202a,2202b,2202c,2202d,2202e, and2202f. Restated, signal lines210a,210btraverse the same path for the entire length of the escape route routing pattern200, running in parallel with each other in a routing channel beneath contacts2201a,2201b,2201c,2201d,2201e, and2201fand above the contacts2202a,2202b,2202c,2202d,2202e, and2202f. Also, a pitch (i.e., distance between centers of pads) is the same in both the horizontal and vertical directions, though this need not be the case. In some cases, the number of traces that can exit through a layer depth (n=1) is limited by the pitch, the pad dimension, and the trace width. Thus, in some embodiments, there may be more than two signal lines that are run in parallel through each layer (or row) in the pattern200.

With the pairs of signal lines210a,210b;211a,211b;212a,212b; and213a,213bbeing routed together (in parallel) through a routing channel (or row), there is some coupling between the signal lines in each of the pairs. Generally, as the length (e.g., distance and/or time) of coupling between the signal line pairs210a,210b;211a,211b;212a,212b; and213a,213bincreases, the amount of interference between the signals similarly increases. Consequently, a substantially large amount of interference, or crosstalk, may be accumulated on the signal lines, due to the signal line pairs210a,210b;211a,211b;212a,212b; and213a,213bbeing coupled together for the full length of the escape route in this pattern200. Also, this pattern200for escape routing can cause a large coupled signal amplitude to be accumulated on the routing channels, which can degrade quality of the signal (e.g., low signal to noise ratio, increased channel losses). Accordingly, conventional escape routing techniques, as shown inFIG.2, are particularly non-optimal for circuitry requiring high data rate channels to be implemented on the PCBs, such as the DDR5 memory circuitry (shown inFIG.1A).

To achieve escape routing, it is common for the outer rows (for example, two to four of the outer rows) within the array to contain all pins that require escape routing. The number of metal traces on the PCB that can be routed between adjacent contacts is limited, however, by the width of the traces, the size (e.g., diameter) of the contacts, and the design rules associated therewith. Thus, as the interconnect complexity of modern PCBs (and IC packages) increases, it has become increasingly difficult to route traces from the internal contacts of the array while still achieving suitable design tolerances for number of traces that can reasonably fit between adjacent contacts. As the number of pins in ICs increases, the number of rows and layers required for escape routing increases non-linearly. Even further, complex IC designs can cause many IC package sizes to increase, lengthening the channel escape routes from under the package. These aforementioned challenges can be intensified by the implementation of high data rate channels on PCBs, particularly in DDR technology. Accordingly, the disclosed transposition channel routing techniques can realize an improvement over conventional escape routing techniques, such as pattern200, by transposing (or repositioning) signal lines from one routing channel to another routing channel, for example a transposition channel. Therefore, the disclosed transposition can cancel out the accumulation of the couple signal line pairs along some portion(s) of the escape route length (e.g., reducing the length of coupling of signal lines along any given routing channel).

FIG.3depicts a portion of an escape routing pattern300that can be arranged on a substrate, such as a PCB (shown inFIG.1A), implementing the disclosed transposition channel routing techniques. As an example, the PCB can include a plurality of component interface fields, which comprises the plurality of component contact pads3201a-3205f. For purposes of discussion, the contacts3201a-3205fare described as contact pads, but it should be appreciated that contacts can also be vias, or other interconnections that may correspond to the contacts pads3201a-3205f. For example, a corresponding via may be placed at the same positions of each of the contact pads3201a-3205f.

The plurality of signal lines that includes310a,310b;311a,311b;312a,312b; and313a,313bcan be disposed on the PCB, having a first end that is connected to one of the contact pads3201a-3205fand a second end connected to a system interface bus of the PCB. In designing an electrical trace layout for the PCB including the escape routing pattern300comprising the plurality of signal lines and the one or more transposition junctions for each of the signal line pairs.

Similar toFIG.2, contacts3201a-3205f(also referred to as contact pads) represent a pattern of solder balls, or conductive pads, on the corresponding IC packaging or substrate. Also, signal lines310a-313bexit from the periphery contacts3201a,3202a,3203a,3204a, and3205a(on the right side) and contacts3201l,3202k,3203l,3204k, and3205l(on the left side) that are adjacent the outer edges of the escape routing pattern300. Also, the pairs of signal lines310a,310b;311a,311b;312a,312b; and313a,313bare routed together (in parallel) through a specific routing channel (or row). For instance, signal line pair310a,310brun in parallel in a routing channel around contacts3201a,320m,3201cfor a portion of the escape route. Thus, there is some coupling between the signal lines in each of the pairs for this duration. However, in contrast to the escape route inFIG.2, transposition channel routing is applied to the signal line pairs, thereby rerouting the signal lines pairs to continue to run in parallel (e.g., coupled) with each other in another channel, shown as transposition channel, of the escape routing pattern300. That is, in the illustrated example, both signal lines of the pair can be “transposed” from their initial routing channel and ran though a different routing channel. As shown, the “transposed” signal lines310c,310d;311c,311d;312c,312d; and313c,313d(represented by dashed lines) are on the left of the transposition junction340. The “transposed” signal lines310c,310d;311c,311d;312c,312d; and313c,313dare signal lines that have been re-directed through micro-vias3251a,3251b;3252a,3252b;3253a,3253b; and3254a,3254bfrom an initial routing channel to a transposition channel, adding a second period to the via crosstalk term that may cancel any accumulation on coupled signal line pairs. It should be understood that the transposition channel can be considered as being in a separate and adjacent layer of the PCB with respect to the initial routing channel. For example, the micro-vias3251a,3251b;3252a,3252b;3253a,3253b; and3254a,3254bcan be blind and/or buried vias on the PCB that consists of pads in an additional routing layer in the electrical trace layout, namely the transposition channel. The micro-vias3251a,3251b;3252a,3252b;3253a,3253b; and3254a,3254bcan correspond to positions (in the layer for the transposition channel of the PCB), that are electrically connected by a hole through the board to a corresponding contact pad (in the layer for the initial routing channel). As referred to herein, micro-vias can be vias having a small diameter (approximately equal to or less than 150 microns) in comparison to mechanically drilled vias.

InFIG.3, pairs of micro-vias3251a,3251b;3252a,3252b;3253a,3253b; and3254a,3254bare placed at a transposition junction340(point along the length of the escape route300), such that each pair of micro-vias3251a,3251b;3252a,3252b;3253a,3253b; and3254a,3254bcorresponds to a respect signal line pair310a,310b;311a,311b;312a,312b; and313a,313b. In the illustrated example: signal line pair310a,310bis re-routed through micro-via pair3251a,3251bin order to directed the “transposed” signal lines310c,310dthrough the transposition channel adjacent to contact pads2301d,3201e;3201f; signal line pair311a,311bis re-routed through micro-via pair3251a,3251bin order to directed the “transposed” signal lines311c,311dthrough the transposition channel adjacent to contact pads2302d,3202e;3202f; signal line pair312a,312bis re-routed through micro-via pair3253a,3253bin order to directed the “transposed” signal lines312c,312dthrough the transposition channel adjacent to contact pads2303d,3203e;3203f; and signal line pair313a,313bis re-routed through micro-via pair3254a,3254bin order to directed the “transposed” signal lines313c,313dthrough the transposition channel adjacent to contact pads2304d,3204e;3204f.

By implementing this transposition channel (adding micro-vias3251a,3251b;3252a,3252b;3253a,3253b; and3254a,3254b), the transposition of the signal lines changes the relationship position as the lines are routed parallel to each other. For a period of time when the relationship between two aggressor signals are transposed, it can induce additional noise in the opposite phase (e.g., in the opposite direction), which results in a cancelling out of any interference that may be accumulated as the coupled signal pairs traverse the initial routing channels. Restated, transposing the relationship of the signals from one layer to another, can add a cancelation factor to the interference of the two signals. This also reduces the coupling length for individual aggressors, which reduces the crosstalk and limits the frequency content of the coupled signals. As alluded to above, position340in the escape route length can represent a “transposition junction” in the escape routing pattern300, which can be described as a point of offset (or transposition) of the “transposed” signal lines to a different routing channel, namely the transposition channel.

Although not shown inFIG.3, various combinations of signal lines can be “transposed” in the same manner described above, as deemed necessary or appropriate. For example, only one signal line of the signal line pair may be transposed. As another example, one or more signal line pairs (lesser than all of the signal lines pairs in the electrical trace layout) may be transposed. In yet another example, there escape route pattern may include more than one transposition junction. In yet another example, signal line pairs may be “transposed” for a smaller portion of the escape route length (e.g., shorter distance between transposition junctions), thereby allowing the frequency of the transposition to be increased. In other words, the same signal lines pair may be transposed two or more times along the length of the escape route pattern300. Accordingly, in some embodiments of the transposition channel routing techniques the placement of the transposition junctions in the escape route, which sets the spacing between offsets (or transitions) of the transposed signal lines can be varied based on the specific application or a desired amount of crosstalk reduction. As a general concept, it should be understood that shortening the spacing between “transposed” positions of the signal lines, in turn increases the coupling reduction. For example, a total number of transposed junctions to be used within an electrical trace layout can be determined, and variably adjusted as a design choice prior to fabricating the PCB. The total number of transposition junctions in the electrical trace layout (e.g., escape route portion of the PCB) can govern a length of coupling between the signal lines within a respective signal line pair. That is, at each transposition junction, the signal line pair is transposed by to an adjacent channel. Generally, the total number of transposition junctions has an inversely proportional relationship to a length of coupling of a signal line pair in a respective routing channel. For instance, increasing the total number of transposition junctions in an escape route, adding multiple periods to the via crosstalk term, which may increase the reduction of the peak accumulated via crosstalk.

Implementing the disclosed transposition channel routing techniques, shown in the escape routing pattern300, can result in an estimated reduction coupling by 50% for the same Nyqyist frequency. It should be understood that due to the use of re-routed, or “transposed” routing channels, the disclosed techniques may require an occasional added routing channel (e.g., 1 added routing channel per 16 lanes on a given layer). Nonetheless, the resulting improved signal to noise ratio, increases the reliability and information carrying capacity of the channel, which are both important characteristics in platforms developed to high performance/high data rate applications, such as a Service (AaS) applications and DDR5.