Maskless exposure device

In an aspect, a grating light valve module including: a substrate; and a plurality of ribbons disposed on the substrate, wherein each of the ribbons includes an insulating layer, a conductive layer disposed on the insulating layer, and an anti-oxidation layer disposed on the conductive layer is provided.

INCORPORATION BY REFERENCE TO ANY PRIORITY APPLICATIONS

Any and all priority claims identified in the Application Data Sheet, or any correction thereto, are hereby incorporated by reference under 37 CFR 1.57. For example, this application claims priority to and the benefit of Korean Patent Application No. 10-2013-0056645 filed in the Korean Intellectual Property Office on May 20, 2013, disclosure of which is herein incorporated by reference in its entirety.

BACKGROUND

This disclosure relates to a light exposure device. For example, this disclosure relates to a maskless exposure device.

2. Description of the Related Technology

Photoresists and exposure masks are usually used in patterning thin films on a semiconductor device or a flat panel display. For example, a thin film is deposited on a substrate and a photoresist film is coated thereon. The photoresist film is exposed to light through an exposure mask and developed to form a photoresist pattern. The thin film is then etched by using the photoresist pattern to form a thin film pattern.

Since the cost for manufacturing a panel for a semiconductor device or a flat panel display is lowered as the size of the panel increase, it is a recent trend to enlarge the panel. However, the increase of the panel size may cause the increase of the size of the exposure mask, thereby increasing the cost for the exposure mask.

In addition, it may be difficult to form minute thin film patterns, for example, having a width equal to or smaller than about 1.5 μm by using the exposure mask.

Alternatively, a maskless light exposure may be used for patterning thin films on a semiconductor device or a flat panel display. A maskless exposure device illuminates an exposure beam directly on a photoresist film without a mask to form a photoresist pattern. Examples of maskless exposure technologies may include a digital micro-mirror device (“DMD”) and a grating light valve (“GLV”).

DMD may have a slow exposure speed and may not be adapted to a minute pattern with a width equal to or smaller than about 2 μm.

GLV may have a relatively large deviation in a direction perpendicular to a scanning direction of an exposure beam compared with a deviation in the scanning direction when forming a pattern with a width equal to or smaller than about 1.5 μm. Furthermore, a ribbon used in GLV may easily deteriorate.

SUMMARY

Some embodiments provide a grating light valve module including: a substrate; and a plurality of ribbons disposed on the substrate, wherein each of the ribbons includes an insulating layer, a conductive layer disposed on the insulating layer, and an anti-oxidation layer disposed on the conductive layer.

In some embodiments, the anti-oxidation layer may include a nitride.

In some embodiments, the anti-oxidation layer may include AlN3.

In some embodiments, the anti-oxidation layer may include: an AlN3sublayer; and a TiO2sublayer disposed on the AlN3sublayer.

In some embodiments, a sum of a retardation of the AlN3sublayer and a retardation of the TiO2sublayer may range from about 550 nm to about 950 nm.

Some embodiments provide a light exposure device including: a light source; a lighting unit configured to receive a beam from the light source and to change a shape of the beam; a grating light valve module configured to switch the beam from the lighting unit; and a projection unit configured to receive the beam from the grating light valve module and to illuminate the received beam onto a substrate coated with a photoresist. In some embodiments, the grating light valve module includes: a substrate; and a plurality of ribbons disposed on the substrate, wherein each of the ribbons includes an insulating layer, a conductive layer disposed on the insulating layer; and an anti-oxidation layer disposed on the conductive layer.

In some embodiments, the anti-oxidation layer may include a nitride.

In some embodiments, the anti-oxidation layer may include AlN3.

In some embodiments, the anti-oxidation layer may include: an AlN3sublayer; and a TiO2sublayer disposed on the AlN3sublayer.

In some embodiments, a sum of a retardation of the AlN3sublayer and a retardation of the TiO2sublayer may range from about 550 nm to about 950 nm.

DETAILED DESCRIPTION

Aspects of the embodiments will be described more fully hereinafter with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the embodiments. In the drawing, the same or similar reference numerals designate the same or similar elements throughout the specification.

A maskless exposure device according to an embodiment of the present disclosure is described in detail with reference toFIG. 1toFIG. 5.

FIG. 1is a schematic block diagram of a maskless exposure device according to an embodiment,FIG. 2is a schematic diagram of an optical unit of the maskless exposure device according to an embodiment,FIG. 3is a schematic plan view of a grating light valve according to an embodiment,FIG. 4a schematic perspective view of a ribbon for a grating light valve according to an embodiment, andFIG. 5is a schematic sectional view of the ribbon for a grating light valve shown inFIG. 4taken along line V-V.

Referring toFIG. 1, a maskless exposure device1according to an embodiment includes an optical unit10and a control unit20.

The optical unit10includes a light source12, a lighting unit14, a grating light valve module (“GLV”) module16, and a projection unit18, and the control unit20an auto focusing (“AF”) controller22and a GLV controller24. In some embodiments, the AF controller22is connected to the lighting unit14and the projection unit18and controls the lighting unit14and the projection unit18, and the GLV controller24controls the GLV module16.

Referring toFIG. 2, the light source12may include a laser generating a laser beam, for example. In some embodiments, the wavelength of the laser beam may be about 405 nm or about 355 nm.

In some embodiments, the lighting unit14may spread, collimate, and attenuate the light from the light source12to form a beam having a proper shape and a proper intensity, and the light unit includes a plurality of lenses142,144,146and148an attenuator149that are arranged in series. In some embodiments, the plurality of lenses142,144,146and148may be a Powell lens142, an x focusing lens144, a y collimating lens146, and a condensing lens148.

In some embodiments, the Powell lens142spreads the incident laser beam.

In some embodiments, the x focusing lens144and the y collimating lens146may correct the shape of the laser beam. In some embodiments, the x focusing lens144may correct an x position of the laser beam, and the y collimating lens146may correct a y position or a width of the laser beam. In some embodiments, the positions of the x focusing lens144and the y collimating lens146may be exchanged.

In some embodiments, the condensing lens148may control a slope of x directional main light beam, and the attenuator149may control the transmittance of the laser beam.

In some embodiments, the lighting unit14may further include a lens (not shown) that converts the shape of the laser beam from a Gaussian intensity distribution to a constant intensity distribution.

In some embodiments, the lighting unit14may further include a mirror that changes a proceeding direction of the laser beam. In some embodiments, the lenses142,144,146and148and the attenuator149may not be aligned on a straight line but on a curved line.

In some embodiments, the lighting unit14may further include a beam shifter (not shown) or a beam sampler (not shown). In some embodiments, the beam sampler may reflect only a little of the laser beam outputted from the attenuator149to measure the light amount.

The projection unit18may include an x shifter182, an objective lens186, and a plurality of lenses184. In some embodiments, the x shifter182may receive the light from the GLV module16and includes a wedge-shaped prism. In some embodiments, the objective lens186may illuminate a leaser beam on a substrate2coated with a photoresist. In some embodiments, the lenses184are disposed between the x shifter182and the objective lens186, and may correct multiplication.

In the above description, y axis is substantially parallel to a proceeding direction of the laser beam from the light source, and x axis is substantially perpendicular to y axis.

Referring toFIG. 2andFIG. 3, the GLV module16includes a substrate160and a plurality of ribbons170disposed thereon. Referring toFIG. 4, both ends of each of the ribbons170are disposed on the substrate160, and the rest portion of the ribbon170is spaced apart from the substrate160by a support162. In some embodiments, the support162is disposed on the substrate160and under the ribbon170, and spaced apart from the ends of the ribbon170to make a gap between a center portion of the ribbon170and the substrate160.

Referring toFIG. 5, each of the ribbons170includes an insulating layer172, a conductive layer174, and an anti-oxidation layer176that are deposited in sequence.

In some embodiments, the insulating layer172may include Si3N4and the conductive layer174may include aluminum (Al).

In some embodiments, the anti-oxidation layer176may reduce or prevent the conductive layer174from being oxidized, and may include a nitride layer, for example. In some embodiments, the anti-oxidation layer176may include a highly refractive material that may enhance the efficiency of the reflection of a laser beam. In some embodiments, the anti-oxidation layer176may have a multi-layered structure including an AlN3sublayer177and a TiO2sublayer178. In some embodiments, the thickness of the AlN3sublayer177and the TiO2sublayer178may be determined so that the total optical retardation of the sublayers177and178may be integer times half of the wavelength of the laser beam, for example, from about 550 nm to about 950 nm, thereby increasing the reflective efficiency.

In some embodiments, the anti-oxidation layer176may have a single layered structure.

In some embodiments, the anti-oxidation layer176on the conductive layer174of the ribbon170in the GLV module16may reduce oxidation of GLV and may increase the lifetime of GLV.

GLV according to experimental examples and a comparative example is described in detail.

FIG. 6is a table illustrating measured reflectance of GLV according to experimental examples and a comparative example, andFIG. 7is a graph illustrating measured reflectance of GLV according to experimental examples and a comparative example.

GLVs according to Experimental Example 1, Experimental Example 2, and a Comparative Example were manufactured, and were tested at a high temperature of about 60° C. and high humidity of about 95%. The Comparative Example omitted the AlN3sublayer177and the TiO2sublayer178in the structure shown inFIG. 5. Experimental Example 1 omitted the TiO2sublayer178in the structure shown inFIG. 5, and Experimental Example 2 has the same structure shown inFIG. 5.

Referring toFIG. 6andFIG. 7, Experimental Example 2 having both the AlN3sublayer177and the TiO2sublayer178shows the best reflective property. Experimental Example 1 having only the AlN3sublayer177shows excellent reflective property compared with the Comparative Example without the AlN3sublayer177and the TiO2sublayer178.

Next, a maskless exposure device including GLVs and a GLV controller according to an embodiment is described in detail with reference toFIG. 8toFIG. 11.

FIG. 8is a schematic block diagram of a maskless exposure device including GLVs and a GLV controller according to an embodiment,FIG. 9is a schematic block diagram of a GLV cell block according to an embodiment,FIG. 10a schematic block diagram of the GLV controller according to an embodiment, andFIG. 11is a graph illustrating an amplitude signal outputted from a maskless exposure device as function of pixels according to an experimental example and a comparative example.

Referring toFIG. 8, a maskless exposure device200according to an embodiment includes a GLV unit210, a GLV control unit220, and a data conversion unit230.

In some embodiments, the GLV unit210includes a plurality of GLV cell blocks212and214, and the GLV cell blocks212and214may include a plurality of even GLV cell blocks212and a plurality of odd GLV cell blocks214, respectively. In some embodiments, each of the even GLV cell blocks212includes a plurality of even GLV cells, for example, about 256 even GLV cells. In some embodiments, each of the odd GLV cell blocks214includes a plurality of odd GLV cells, for example, about 256 odd GLV cells. In some embodiments, the number of the GLV cell blocks212and214included in the GLV unit210may be about 32, for example.

In some embodiments, the data conversion unit230includes a plurality of digital-to-analog converters232, and is connected between the GLV control unit220and the cell blocks212and214.

In some embodiments, the GLV control unit220is connected to the data conversion unit230and the GLV unit210, and may include a field-programmable gate array (“FPGA”), for example.

Referring toFIG. 9, each of the GLV blocks300include a GLV cell310, a data interface320, and a global block logic330.

In some embodiments, the GLV cell310may include a pixel311, first to third sample-hold unit (SH)312a,312band312c, an amplifier313, first and second registers (RG)314aand314b, and a comparator315.

In some embodiments, the data interface320includes a first shift register (SR)322, a second shift register324, and a double data rate (“DDR”) interface326.

In some embodiments, the global block logic330includes a register332and a ramp counter334.

In some embodiments, the DDR interface326in the data interface320has an input terminal connected to the GLV control unit220, an output terminal connected to an input terminal of the first register314aand the second shift register324, and a clock terminal connected to the GLV control unit220and receiving a clock signal Sck. In some embodiments, the DDR interface326may convert four-bit delay data from the GLV control unit220into eight-bit data based on a clock signal Sck from the GLV control unit220.

In some embodiments, the first shift register322has an input terminal connected to the GLV control unit220and receiving a signal Psrdi from the GLV control unit220, an output terminal connected to an input terminal of the first sample-hold unit312a, and a clock terminal connected to the GLV control unit220and receiving the clock signal Pck from the GLV control unit220. In some embodiments, the first shift register322may shift and output the signal Psrdi from the GLV control unit220based on the clock signal Pck from the GLV control unit220.

In some embodiments, the second shift register324has an input terminal connected to an output terminal of the DDR interface326, an output terminal connected to a clock terminal of the first register314a, and a clock terminal connected to the GLV control unit220and receiving the clock signal Sck. The second shift register324may shift and output a signal from the DDR interface326based on the clock signal Sck from the GLV control unit220.

In some embodiments, the ramp counter334included in the global block logic330has an input terminal connected to the GLV control unit220and receiving a signal Pcs from the GLV control unit220, an output terminal connected to an input terminal of the comparator315, and a clock terminal connected to the GLV control unit220and receiving a clock signal Wck. In some embodiments, the ramp counter334may count the signal Pcs from the GLV control unit220to generate an eight-bit signal based on the clock signal Wck from the GLV control unit220.

In some embodiments, the register332included in the global block logic330has an input terminal connected to the GLV control unit220and receiving the signal Pcs from the GLV control unit220, and an output terminal connected to a clock terminal of the second register314bin the GLV cell310.

In some embodiments, the first and second registers314aand314bincluded in the GLV cell310are connected in series. In some embodiments, the first register314ahas an input terminal connected to the DDR interface326of the data interface320, an output terminal connected to the second register314b, and a clock terminal connected to the second shift register324. In some embodiments, the second register314bhas an input terminal connected to the output terminal of the first register314a, an output terminal connected to the comparator315, a clock terminal connected to the register332of the global block logic330. In some embodiments, the first register314aand the second register314bmay delay an eight-bit signal from the DDR interface326.

In some embodiments, the comparator315has a first input terminal connected to the output terminal of the second register314band a second input terminal connected to the ramp counter334of the global block logic330, and the output terminal connected to an input terminal of the third sample-hold unit312c. In some embodiments, the comparator315may compare a signal from the second register314band a signal from the ramp counter334and output a result of the comparison.

In some embodiments, the first to third sample-hold units312a,312band312care connected in series. In some embodiments, the first sample-hold unit312ahas an input terminal connected to the digital-to-analog converter232and an input terminal connected to the first shift register322of the data interface320, and the output terminal connected to the second sample-hold unit312b. In some embodiments, the second sample-hold unit312bhas an input terminal connected to the output terminal of the first sample-hold unit312aand an input terminal connected to the second register314b. In some embodiments, the third sample-hold unit312chas an input terminal connected to the output terminal of the second sample-hold unit312band an input terminal connected to the comparator315, and an output terminal connected to the amplifier313.

In some embodiments, the first sample-hold unit312amay sample and hold an amplitude of a signal or analog data from the digital-to-analog converter232based on a signal from the first shift register322of the data interface320. In some embodiments, the second sample-hold unit312bmay sample and hold an amplitude of a signal from the first sample-hold unit312abased on a signal from the second register314b. In some embodiments, the third sample-hold unit312cmay sample and hold a signal from the second sample-hold unit312bbased on a signal from the comparator315.

In some embodiments, the amplifier313has an input terminal connected to the third sample-hold unit312c, and the output terminal connected to a pixel311. The amplifier313may receive and amplify a signal from the third sample-hold unit312cand transmit the amplified signal to the pixel311.

Referring toFIG. 10, the GLV control unit400, for example, FPGA includes a plurality of channels460and a plurality of portions connected to the channels460. For example, the GLV control unit400includes a first data distributor410, a pair of pixel data registers422and424, a second data distributor430, and a DDR converter440.

In some embodiments, the pixel data register422includes an even-column pixel data register422. In some embodiments, the pixel data register424includes an odd-column pixel data register424.

In some embodiments, the first data distributor410may receive pixel data by six bits per channel from an external device, and may divide the pixel data into even-column pixel data and odd-column pixel data to be outputted. In some embodiments, the even-column pixel data register422may receive and store the even-column pixel data from the first data distributor410and may transmit the even-column pixel data to the channel460. In some embodiments, the odd-column pixel data register424may receive and store the odd-column pixel data from the first data distributor410and may transmit the odd-column pixel data to the channel460.

In some embodiments, the channel460includes a third data distributor461, an amplitude table462, a previous amplitude data register463, an edge detection table464, an edge delay offset table465, a logical/physical delay convert table466, an add-and-limiter467, a gray code conversion table468, a header register469, a reset command register470, a redundancy and testability driver471, and a multiplexer472.

In some embodiments, the third data distributor461may receive pixel data from the pixel data registers422and424, and may divide the pixel data into two 3-bit amplitude data Amp and a 3-bit position or phase data V-pos to be outputted.

In some embodiments, the amplitude table462may convert the 3-bit amplitude data from the third data distributor461into 7-level 10-bit amplitude data, for example.

In some embodiments, the 10-bit amplitude data from the amplitude table462along with 10-bit amplitude data from an adjacent channel may be inputted into the second data distributor430, and may be then inputted into the digital-to-analog converters232.

In some embodiments, the previous amplitude data register463may store and delay the amplitude data from the third data distributor461, and may output the delayed amplitude data. In some embodiments, the edge detection table464may detect edge based on current amplitude data from the third data distributor461and the previous amplitude data from the previous amplitude data register463. In some embodiments, the edge delay offset table465may calculate edge delay offset based on the data from the edge detection table464.

In some embodiments, the phase data V-pos from the third data distributor461may be converted by the logical/physical delay convert table466, and then the converted data along with the delay offset from the edge delay offset table465may be added and limited by the add-and-limiter467and may inputted to the gray code conversion table468. In some embodiments, the add-and-limiter467may limit 8-bit delay sum into a predetermined range, for example, between a minimum value and a maximum value.

In some embodiments, the delay value converted by the gray code conversion table468along with signals from the header register469, the reset command register470, and the redundancy and testability driver471may be inputted into the multiplexer472to be outputted selectively.

In some embodiments, the DDR converter440may divide 8-bit data from the multiplexer472into two 4-bit delay data and may output the 4-bit delay data to the GLV cell blocks212and214.

As described above, the data interface320including the DDR interface326and the first and second shift registers322and324is added to the GLV cell block300, and the first and second registers314aand314bare placed in the GLV cell310. Therefore, the device may process digital data instead of analog data and a conventional analog delay circuit may be removed.

For example, referring toFIG. 11, a conventional maskless exposure device that has no DDR interface, and includes a pair of sample-hold units that processes analog data instead of the first and second registers314aand314bmay cause a delay of about 100 ns in switching time due to the analog delay and thus the amplitude may abruptly increase in a period of about 4 pixels. However, the maskless exposure device according to the present embodiments may show a substantially uniform amplitude.

Thin film patterns formed using a maskless exposure device according to an experimental example and a comparative example are described in detail with reference toFIG. 12andFIG. 13.

FIG. 12is a photograph of a thin film pattern formed using a maskless exposure device according to a comparative example, andFIG. 13is a photograph of a thin film pattern formed using a maskless exposure device according to an experimental example.

Referring toFIG. 12, a thin film pattern formed using a maskless exposure device according to a comparative example has non-uniform widths and hardly obtains an inter-line distance of about 1.5 μm. However, referring toFIG. 13, a thin film pattern formed using a maskless exposure device according to an experimental example has a uniform line width and shows an inter-line distance of about 1.5 μm and a line edge roughness (LER) of about 0.2 μm.