Voltage control circuit having a power switch

A voltage control circuit includes a first transistor coupled to a first voltage supply terminal having a first voltage, a second transistor coupled to the first transistor and a node, a third transistor coupled to a second voltage supply terminal and the node, wherein the second voltage supply terminal has a second voltage and the node is at a voltage selected from the group consisting of the first voltage and the second voltage, and a fourth transistor coupled to the node.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates in general to circuits and more specifically to a voltage control circuit having a power switch.

2. Description of the Related Art

In certain applications a node of an integrated circuit may need different voltage supply depending upon the mode of operation. Traditional circuits for coupling different supply voltages to the node of the integrated circuit suffer from problems, such as leakage current. The presence of leakage current in turn increases the power consumption by the integrated circuit.

Thus, there is a need for a voltage control circuit having a power switch.

DETAILED DESCRIPTION

In one aspect, a voltage control circuit is provided. The voltage control circuit may include a first transistor coupled to a first voltage supply terminal having a first voltage, a second transistor coupled to the first transistor and a node, a third transistor coupled to a second voltage supply terminal and the node, wherein the second voltage supply terminal has a second voltage and the node is at a voltage selected from the group consisting of the first voltage and the second voltage, and a fourth transistor coupled to the node.

In another aspect, a voltage control circuit is provided. The voltage control circuit may include a first transistor and a second transistor coupled in series, wherein the second transistor has a first conducting terminal and a second conducting terminal and the first conducting terminal is coupled to the first transistor. The voltage control circuit may further include a third transistor and a fourth transistor coupled in series, wherein the third transistor has a first bulk region, the fourth transistor has a second bulk region and the first bulk region, the second bulk region, and the second conducting terminal of the second transistor are coupled to a node.

In yet another aspect, a voltage control circuit is provided. The voltage control circuit may include a first driver coupled to a first voltage supply terminal, a power switch coupled to the first voltage supply terminal, a second voltage supply terminal, and an enable terminal. The power switch may include a first transistor having a first conducting terminal, a second conducting terminal, and a first bulk region, wherein the first conducting terminal is coupled to the first voltage supply terminal and the first conducting terminal is coupled to the first bulk region. The power switch may further include a second transistor having a third conducting terminal, a fourth conducting terminal and a second bulk region, wherein the third conducting terminal is coupled to the second conducting terminal of the first transistor, the fourth conducting terminal is coupled to the second bulk region and the fourth conducting terminal is coupled to a node. The power switch may further include a third transistor having a fifth conducting terminal, a sixth conducting terminal and a third bulk region, wherein the fifth conducting terminal is coupled to the second voltage supply terminal, the sixth conducting terminal is coupled to the third bulk region and the sixth conducting terminal is coupled to the node. The power switch may further include a fourth transistor having a seventh conducting terminal, an eighth conducting terminal and a fourth bulk region, wherein the seventh conducting terminal is coupled to the node and the seventh conducting terminal is coupled to the fourth bulk region. The voltage circuit may further include a second driver coupled to the enable terminal and the eighth conducting terminal of the fourth transistor of the power switch.

FIG. 1shows a diagram of an exemplary integrated circuit10, consistent with one embodiment of the invention. Although not shown, integrated circuit10may include components, such as a processor, memory, or any other devices. Integrated circuit10may have one or more nodes, which may need to be coupled to at least one driver. Each driver, in turn, may be coupled to a voltage supply terminal or rail (not shown). For example,FIG. 1shows internal nodes12(e.g., bonding pads) as part of integrated circuit10.

FIG. 2shows a block diagram of an exemplary implementation of a voltage control circuit14, consistent with one embodiment of the invention. Voltage control circuit14may receive at least three inputs and provide an output voltage supply that may be coupled to an external node12, for example. By way of example, voltage control circuit14may include a power switch20, a first driver22(labeled as DRIVER1), and a second driver24(labeled as DRIVER2) . First driver22and second driver24may be implemented using conventional techniques. In addition, by way of example, first driver22may receive a first voltage via a first voltage supply terminal26(labeled as VST1) . Second driver24may receive (by way of power switch20) a second voltage via a second voltage supply terminal28(labeled as VST2) . Power switch20may receive the first voltage via first voltage supply terminal26. Power switch20may also receive the second voltage via second voltage supply terminal28. By way of example, first voltage may correspond to a voltage between 1.8 volts to 3.3 volts and second voltage may correspond to 1.2 volts. Further, by way of example, first driver22may correspond to a general purpose input output GPIO driver and second driver24may correspond to a mobile industry processor interface (MIPI) driver. Further, power switch20may receive an enable signal via an enable terminal30(labeled as ENABLE) and second driver24may also receive enable signal30. In one embodiment, the enable signal may be generated by a source of the first voltage supply and the second voltage supply. By way of example, the enable signal may be generated by another integrated circuit or device.

In operation, power switch20may couple either the first voltage (coupled via first voltage terminal26) or the second voltage (coupled via second voltage terminal28) to internal node12based on the state of a signal coupled to enable terminal30. The signal coupled to enable terminal30may also be used to enable or disable power switch20and/or second driver24. By way of example, the enable signal may be sent by another integrated circuit that supplies the first voltage and the second voltage to voltage control circuit14. That integrated circuit may turn-off the first voltage or the second voltage in combination with an appropriate value of the enable signal. By way of example, an unused voltage supply may always be turned off, thus saving power.

FIG. 3shows an exemplary circuit diagram of a power switch20, consistent with one embodiment of the invention. Power switch20may include gate control logic32(labeled as GATE CONTROL LOGIC), a first transistor34, a second transistor36, a third transistor38, and a fourth transistor40. A first conducting terminal (source or drain, for example) of first transistor34may be coupled to first voltage terminal26. A control terminal (gate, for example) may be coupled to gate control logic32. A second conducting terminal of first transistor34may be coupled to a first conducting terminal of a second transistor36. A control terminal of second transistor36may be coupled to gate control logic32. A first conducting terminal of a third transistor38may be coupled to second voltage terminal28. A control terminal of third transistor38may be coupled to gate control logic32. A second conducting terminal of third transistor38may be coupled to node42(labeled as VBULK). The second conducting terminal of second transistor36may also be coupled to node42. A first conducting terminal of a fourth transistor40may be coupled to node42. A control terminal of fourth transistor40may be coupled to gate control logic32. A second conducting terminal of fourth transistor40may provide an output, which may be coupled to second driver24. Further, the enable signal may be coupled vial enable terminal30to gate control logic32. As shown inFIG. 3, the bulk region of first transistor34may be coupled to first voltage terminal26. Additionally, the bulk regions of each of second transistor36, third transistor38, and fourth transistor40may be coupled to node42(labeled as VBULK).

In operation, when the enable signal is high and the first voltage (for example, 1.8 volts) is coupled to first voltage terminal26and the second voltage (for example, 1.2 volts) is coupled to second voltage terminal28, power switch20couples the second voltage to second driver24. This can be accomplished, for example, by gate control logic32, which turns off first transistor34and second transistor36and turns on third transistor38and fourth transistor40. This in turn causes the voltage at node42to be equal to the second voltage (for example, 1.2 volts), which is in turn, coupled to second driver24. When the second voltage is coupled to second driver24, the first voltage is turned off by an integrated circuit supplying the first and second voltages. Alternatively, when the enable signal is low and the first voltage (for example, 1.8 volts) is coupled to first voltage terminal26and the second voltage (for example, 1.2 volts) is coupled to second voltage terminal28or is coupled to no voltage, power switch20couples the first voltage to second driver24. This can be accomplished, for example, by gate control logic32, which turns on first transistor34, second transistor36, and fourth transistor40, and turns off third transistor38. This in turn causes the voltage at node42to be equal to the first voltage (for example, 1.8 volts), which is in turn, coupled to second driver24. When the first voltage is coupled to second driver24, the second voltage is turned off by the integrated circuit supplying the first and second voltages. Referring back toFIG. 2, when enable signal is high, second driver24is used to drive node12, however, when enable signal is low, first driver22is used to drive node12.

Further, referring toFIG. 3, when enable signal is low and no voltage is coupled to first voltage terminal26and the second voltage (for example, 1.2 volts) is coupled to second voltage terminal28, power switch20de-couples first driver22and second driver24from node12. Alternatively, when enable signal is high and no voltage is coupled to second voltage terminal28and the first voltage (for example, 1.8 volts) is coupled to first voltage terminal26, power switch20de-couples first driver22and second driver24from node12. Although details of gate control logic32are not shown, it may be implemented using various logic gates or other components.

In the foregoing specification, the invention has been described with reference to specific embodiments. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. It should be understood that circuitry described herein may be implemented either in silicon or another semiconductor material or alternatively by software code representation of silicon or another semiconductor material.