Static magnetic field assisted resistive sense element

Apparatus and associated method for writing data to a non-volatile memory cell, such as spin-torque transfer random access memory (STRAM). In accordance with some embodiments, a resistive sense element (RSE) has a heat assist region, magnetic tunneling junction (MTJ), and pinned region. When a first logical state is written to the MTJ with a spin polarized current, the pinned and heat assist regions each have a substantially zero net magnetic moment. When a second logical state is written to the MTJ with a static magnetic field, the pinned region has a substantially zero net magnetic moment and the heat assist region has a non-zero net magnetic moment.

BACKGROUND

Data storage devices generally operate to store and retrieve data in a fast and efficient manner. Some storage devices utilize a semiconductor array of solid-state memory cells to store individual bits of data. Such memory cells can be volatile or non-volatile. Volatile memory cells generally retain data stored in memory only so long as operational power continues to be supplied to the device. Non-volatile memory cells generally retain data stored in memory even in the absence of the application of operational power.

Resistive sense memory (RSM) cells can be configured to have different electrical resistances to store different logical states. The resistance of the cells can be subsequently detected during a read operation by applying a read current and sensing a signal in relation to a voltage drop across the cell. Exemplary types of RSM cells include resistive random access memory (RRAM), magnetic random access memory (MRAM), and spin-torque transfer random access memory (STTRAM or STRAM).

In these and other types of devices, it is often desirable to increase performance while decreasing power consumption, lowering switching currents and decreasing design complexity.

SUMMARY

Various embodiments of the present invention are generally directed to an apparatus and associated method for writing data to a non-volatile memory cell, such as spin-torque transfer random access memory (STRAM).

In accordance with some embodiments, a resistive sense element (RSE) has a heat assist region, magnetic tunneling junction (MTJ), and pinned region. When a first logical state is written to the MTJ with a spin polarized current, the pinned and heat assist regions each have a substantially zero net magnetic moment. When a second logical state is written to the MTJ with a static magnetic field, the pinned region has a substantially zero net magnetic moment and the heat assist region has a non-zero net magnetic moment.

In accordance with other embodiments, a resistive sense element (RSE) having a heat assist region, magnetic tunneling junction (MTJ), and pinned region is provided. A first logical state is then written to the MTJ with a spin polarized current while the pinned and heat assist regions each have a zero net magnetic moment. A second logical state is then written to the MTJ with a static magnetic field while the pinned region has a zero net magnetic moment and the heat assist region is activated to produce a non-zero net magnetic moment.

These and various other features and advantages which characterize the various embodiments of the present invention can be understood in view of the following detailed discussion in view of the accompanying drawings.

DETAILED DESCRIPTION

FIG. 1provides a functional block representation of a data storage device100constructed and operated in accordance with various embodiments of the present invention. The device100includes a top level controller (CPU)102, an interface (I/F) circuit104and a non-volatile data storage array106. The I/F circuit104operates under the direction of the controller102to transfer data between the array106and a host device.

FIG. 2displays functional block representations of a unit cell110construction that can be used in the array106ofFIG. 1. The unit cell110has a resistive sense element (RSE)112connected in series with a switching device114. The switching device114functions to increase the resistance of the unit cell110when in an open position, as shown, so as to effectively prevent current from passing through the cell. A closed position allows read and write currents through the unit cell110.

FIG. 3shows an exemplary RSE construction at120. The RSE120is configured as a spin torque-transfer random access memory (STRAM) cell that includes a magnetic tunneling junction (MTJ)122formed from two ferromagnetic layers124,126separated by a barrier layer128(such as magnesium oxide, MgO). The resistance of the MTJ122is determined in relation to the relative magnetization directions of the ferromagnetic layers124,126: when the magnetization is in the same direction (parallel), the MTJ is in the low resistance state (RL); when the magnetization is in opposite directions (anti-parallel), the MTJ is in the high resistance state (RH).

The magnetization direction of the reference layer126is fixed by coupling the reference layer to a pinned magnetization layer (e.g., a permanent magnet, etc.). The magnetization direction of the free layer124can be changed by passing a driving current polarized by magnetization in the reference layer126.

To read the logic state stored by the MTJ122, a relatively small current is passed through the MTJ between a source line (SL) and a bit line (BL). Because of the difference between the low and high resistances of the MTJ in the respective logical 0 and 1 states, the voltage at the bit line will be different, which can be sensed using a suitable sense amplifier. A switching device130allows selective access to the MTJ122during read and write operations. The switching device130can be characterized as a metal oxide semiconductor field effect transistor (MOSFET). A word line (WL) is connected to a gate terminal of the transistor130, as shown.

While operable, unit cells such as represented inFIGS. 2-3can have disadvantages, such as asymmetric write current characteristics. For example, a greater write driver effort may be required to set the RSE120inFIG. 3to the anti-parallel high resistance state (hard programming direction) than to set the RSE to the parallel low resistance state (easy programming direction). The relative ordering of the RSE and the switching device within the unit cell with respect to the direction of write current flow can also contribute to such asymmetric write characteristics.

Accordingly, various embodiments of the present invention are generally directed to a novel memory cell structure with improved write characteristics. As explained below, the memory cell structure includes a resistive sense element (RSE) having a heat assist region, a magnetic tunneling junction (MTJ), and a pinned region. The pinned and heat assist regions each have a substantially zero net magnetic moment while a first logical state is written to the MTJ with a spin polarized current.

Further, the pinned region has a substantially zero net magnetic moment and the heat assist region has a non-zero net magnetic moment when a second logical state is written to the MTJ with a static magnetic field. Both logical states are written with unipolar write currents that pass in the same direction through the memory cell.

FIG. 4provides an exemplary construction for an RSE140capable of being used in the unit cell110ofFIG. 2in accordance with various embodiments. The RSE140is characterized by a magnetic tunneling junction142that comprises a free layer144as well as a first and second barrier layer146and148. In some embodiments, the free layer144is a ferromagnetic material capable of maintaining a magnetic polarity, and the first and second barrier layers146,148are oxide barrier layers. The first and second oxide layers146and148can be constructed of various materials and are not limited to oxides. That is, a barrier material other than an oxide can be utilized in the magnetic tunneling junction142to shield the free layer144from unwanted magnetic pulses.

Further, the magnetic tunneling junction142of the RSE140is disposed between a heat assist layer150and a pinned layer152. The heat assist layer150has the capability of storing a magnetic polarity with a moment in either of two opposing directions. Meanwhile, the pinned layer152has a magnetic polarity with a moment in a single direction. In some embodiments, the magnetic moment of the pinned layer152opposes the magnetic moment of the heat assist layer150in order to provide a net zero magnetic moment on the magnetic tunneling junction142.

In addition, a switching device154is also connected to the RSE140to allow selection of the RSE140, as desired. It can be appreciated that the position of the switching device in relation to the RSE140is not limiting and can vary without deterring from the spirit of the present invention.

It should be noted that the heat assist layer150has a zero net magnetic moment, in some embodiments, at a first temperature while having a non-zero net magnetic moment at an elevated second temperature. As shown inFIG. 4, the heat assist layer150can be a single ferromagnetic material such as, but not limited to, rare earth-transition metals and their alloys such as TbCoFe. However, multiple heat assist layers150can be used in combination to form a heat assist region, illustrated inFIG. 5.

FIG. 5shows an exemplary construction for an RSE160in accordance with the various embodiments of the present invention. A magnetic tunneling junction162with a free layer164as well as a first and second oxide layer166and168is shown disposed between a pinned region170and a heat assist region172. The pinned region170comprises a first and second pinned layer174and176connected by an oxide layer178. The pinned layers176and178are configured to have opposing magnetic moments in order to provide a zero net magnetic moment to the magnetic tunneling junction162.

However, the use of an oxide material to separate the pinned layers176and178is not required as any desired spacing material can be used without deterring from the spirit of the present invention. Likewise, the specific magnetic orientation of the first and second pinned layers176and178is not limited and can be any variety of configurations that produce a zero net magnetic moment. One skilled in the art can appreciate that the position of a switching device184is adjacent to the heat assist region172, but can be located adjacent the pinned region170without detrimental effect to the spirit of the present invention.

As discussed above, the heat assist region172comprises multiple heat assist layers180and182configured to provide a zero net magnetic moment to the magnetic tunneling junction162at a first temperature. Much like the pinned region170, the heat assist layers180and182have magnetic orientations that produce opposing magnetic moments. A barrier, oxide, or similar layer184is disposed between the heat assist layers180and182to separate the magnetic moments.

As such, the RSE160has a zero net magnetic moment due to the balancing magnetic moments of both the pinned layers176and174as well as the heat assist layers180and182. Once the free layer164holds a magnetic polarity, a resistance state of the RSE160will be present and allow a logical state to be read. It should be noted that the multiple heat assist layers can be constructed with synthetic ferri-magnetic material to which one layer has a Curie temperature that is higher than the other heat assist layer. Hence, at a predetermined temperature, the magnetic moments of the heat assist layers180and182as well as the heat assist region172can be manipulated with temperature, as desired.

InFIGS. 6 and 7, the RSE160ofFIG. 5is generally illustrated in alternative constructions that conform to various embodiments of the present invention. As shown inFIG. 6, the magnetic moment of each of the heat assist layers180and182as well as the heat assist region172is perpendicular with the magnetic moment of the magnetic tunneling junction162and pinned region170. This configuration still provides a zero net magnetic moment to the magnetic tunneling junction at a first temperature while greatly reducing the amount of current required to write a logical state to the free layer164at a second temperature.

In contrast, the magnetic tunneling junction162and pinned region170can be configured to have perpendicular anisotropy in relation to the heat assist region172, as illustrated inFIG. 7. Despite a perpendicular anisotropy, the net magnetic moment experienced by the magnetic tunneling junction162remains zero until a second temperature activates the heat assist region172to produce a non-zero net magnetic moment.

It should be noted that the magnetic orientations of each of the regions of the RSE160depicted inFIGS. 6 and 7are not limiting. For example, the magnetic tunneling junction162can be configured to have perpendicular anisotropy while the pinned region170has a magnetic moment perpendicular to the heat assist region172that has in-plane magnetization.

One issue that has been found with STRAM cells (as well as with other types of RSE cells) relates to the minimal achievable sizing of the cell transistor. Generally, it is desirable to ensure that the cell transistor is configured to be large enough to be able to accommodate the requisite write current densities and gate control voltages necessary to carry out write operations without incurring damage to the cell transistor. At the same time, since the transistor can often be the limiting factor in cell scalability, reducing the size of the transistor can promote increases in the overall density of the memory array.

A related matter is write current asymmetry. STRAM cells are often configured such that write currents are passed in different directions through the cell in order to write the different logical states. This can also be true for other types of RSE cells. For example, application of a write current in a first direction may set the resistance of the cell low, thereby signifying a first logical state (e.g., logical 0). Application of a write current in the opposite second direction may set the resistance of the cell high, thereby signifying the opposite logical state (e.g., logical 1).

Depending on the configuration of the cell, it may be harder to write the cell in one direction as compared to the other. A number of factors can contribute to such asymmetry. One factor relates to the relative ordering of the magnetic tunneling junction and switching device elements with respect to the direction of the applied write current; that is, whether the write current passes through the magnetic tunneling junction first, or passes through the switching device first. Other factors can relate to the configuration and ordering of layers within the magnetic tunneling junction (or other variable resistive element).

For the exemplary RSE160ofFIG. 5, it is contemplated that it will be relatively easy to write the state of the magnetic tunneling junction162when the current is passed in a direction such that the write current encounters the magnetic tunneling junction162prior to the switching device184(this direction is referred to as the “easy” direction). Contrawise, it is contemplated that it will be more difficult to write in the opposite direction when the write current passes through the transistor (drain-source juncture) prior to encountering the magnetic tunneling junction (this direction is referred to as the “hard” direction).

Accordingly, as explained below, various embodiments of the present invention utilize a novel structure and technique to facilitate the writing of various logical states to an RSE with a uni-directional and uni-polar current and a static magnetic field. The use of a single current, polarity, and direction for a RSE allows for complete avoidance of both RSE and unit cell write current asymmetry. Meanwhile, the use of a static magnetic field to write a logical state to the RSE provides advantageous power consumption in combination with improved reliability of data storage due to increased unit cell degradation.

Reference is now made toFIGS. 8 and 9, which provide an exemplary operation of the RSE160ofFIG. 5. InFIG. 8, the RSE160is depicted as a variable resistor in series with the switching element (transistor)184. The bit line is positioned adjacent the pinned region170while the switching device184and source line are adjacent the heat assist region172. It should be noted that the heat assist region172is shown at a first temperature to which a zero net magnetic moment is produced.

As a write current190flows from the bit lined to the pinned region170, the RSE160has a zero net magnetic moment due the balanced magnetic moments of both the pinned and heat assist regions170and172. In some embodiments, the write current190is spin polarized as it passes through the RSE160to set the magnetic orientation of the free layer164of the magnetic tunneling junction162to a first polarity. The set plurality has an associated resistance for the RSE160that corresponds to a predetermined logical state. After the write current190has passed through the RSE160, switching device184, and source line the RSE160experiences a general magnetic moment from the free layer164because the magnetic moments of the heat assist region172and pinned region170remain balanced with respect to magnetic moment.

In order to write a second logical state to the RSE160,FIG. 9depicts a static magnetic field192generation and function. When it is desired to write a second logical state to the RSE160, the heat assist region172is heated to a second temperature in which one of the heat assist layers180or182has a modified magnetic moment. The lack of balancing magnetic moments in the heat assist region172produces a non-zero net magnetic moment and a static magnetic field strong enough to switch the polarity of the free layer164of the magnetic tunneling junction162to the second logical state.

It should be noted that the pinned region170remains balanced with a zero net magnetic moment during the generation and utilization of the static magnetic field192. The zero net magnetic moment of the pinned region170allows the static field to change the magnetic polarity of the free layer164with less intensity than would be required if a magnetic moment of the pinned region170would need to be compensated.

Consequently, the net zero magnetic moment of the various regions of the RSE160allows improved reliability, performance, and power consumption. The use of a single uni-polar and uni-directional write current greatly reduces the complexity often required to compensate for write current asymmetry. Meanwhile, the use of a static magnetic field provides precision and low power consumption that cannot be realized with bi-directional write currents.

It should further be noted that the manner in which the heat assist region172reaches a second temperature is not limited. That is, various components or procedures can be utilized to elevate the temperature of the heat assist region172and generate a static magnetic field. Furthermore, the elevation of temperature of the heat assist region172does not require the passing of a current through the entire RSE160. For example, the heat assist region172can be heated independent of the magnetic tunneling junction162and pinned region170. Thus, control and manipulation of the heat assist region172can be facilitated in various manners that generate a non-zero net magnetic moment and an associated static magnetic field.

It can be appreciated that using a bi-directional write current to write a logical state to a resistive sense element has numerous disadvantages such as high power consumption, reduced reliability, and complex write current asymmetry compensation circuitry. Indeed, the use of bi-directional write current provides more disadvantages than advantages considering the imprecision and inconsistency of passing write current through a resistive sense element in opposing directions.

Accordingly, various embodiments of the present invention generally operate to provide a precise and reliable resistive sense element that has specific regions that have a substantially zero net magnetic moment during a uni-polar and uni-directional write current, but have a non-zero net magnetic moment when a static magnetic field is used to write a logical state to the resistive sense element. The use of a static magnetic field instead of a write current passing through the resistive sense element in the opposing direction provides greater performance while reducing power consumption.

An exemplary embodiment is set forth byFIG. 10to explain the foregoing features and advantages.FIG. 10illustrates an array200of resistive sense elements as set forth byFIGS. 5-9arranged into a semiconductor array. More specifically,FIG. 10illustrates three STRAM cells denoted202A-202C, each having an associated switching device (transistor)204A-C. The switching devices are each connected and controlled by word lines206that are capable of selecting a particular one, or many, resistive sense elements, as desired.

It will be appreciated that the array can be extended to have any numbers of columns and rows of such cells, so the simplified 2×2 array inFIG. 7is merely for purposes of illustration and is not limiting. The various directions of the word, bit and source lines across the array are also merely exemplary and can be oriented as desired. Each of the resistive sense elements202A-C also is connected to a heat assist line208that is coupled to a multiplexer210. The heat assist lines208allow the heat assist region of the resistive sense element to be heated from a first temperature to a second temperature without having to pass a current through the entire resistive sense element.

However, the configuration of the heat assist lines208is not limiting as one heat assist line208could be connected to any number of resistive sense elements. Likewise, the number and orientation of the multiplexer210is not limited to the configuration shown inFIG. 10. For example, a multiplexer210could be implemented for each row or column of resistive sense elements.

During operation, the array200can provide voltages to each, or all, of the resistive sense elements202A-C from a driver212. The driver212produces voltages that travel, in some embodiments, through the bit line214to a predetermined number of resistive sense elements202A-C that have been selected by having the word line206operate a gate on each desired switching device204A-C. After passing through the resistive sense element, voltage can pass through a source line216to a ground218.

It should be noted that due to the static magnetic field writing capability of the resistive sense elements202A-C, a second voltage driver capable of passing current through the resistive sense elements in the opposing direction (from source line to bit line) is not needed. However, the configuration of the driver212being positioned on the bit line214is not limiting as the position of the driver212and ground218can be inverted without deterring from the spirit of the present invention.

FIG. 11provides a flow chart for an uni-directional write operation230, generally illustrative of steps carried out in accordance with various embodiments of the present invention. At step232, a resistive sense element (RSE) is provided that has at least a heat assist region, pinned region, and magnetic tunneling junction. A first logical state is written to the RSE at step234with a spin polarized current. In some embodiments, the heat assist region is at a first temperature to which a substantially zero net magnetic moment is produced. Likewise, the pinned region is characterized during step234as having a zero net magnetic moment.

Subsequently, the heat assist region of the RSE is activated at step236to provide a non-zero net magnetic moment and generate a static magnetic field. In step238, the static magnetic field migrates to the magnetic tunneling junction of the RSE to write a second logical state to the RSE. The routine then ends at step240.

The various steps of the uni-directional write operation230are not limiting as steps can be omitted or repeated any number of times. That is, a first logical state could be written to an RSE repeatedly without ever writing a second logical state, or vice versa.

Although various embodiments set forth above generally identify the hard and easy directions based on the relative sequential ordering of a resistive sense element and a switching device of a cell, such is not necessarily limiting. Rather, it is contemplated that various memory cell constructions may alternatively have an “easy” and a “hard” direction based on some other feature of the cell. It will be understood that the various embodiments disclosed herein are equally suitable for these other types of memory cells in obtaining read current symmetry without compromising cell reliability.

As can be appreciated by one skilled in the art, the various embodiments illustrated herein provide advantageous writing of data to a resistive sense element in a fast and reliable manner. The ability to write various resistance states with a single uni-directional write current allows for consistent data writing without elevated power consumption. The use of a static magnetic field to write a logical state to a resistive sense element vastly improves the efficiency and complexity of any electronic data storage device. Moreover, the dynamic nature of the static magnetic field write provides increased performance with respect to write current driving ability. However, it will be appreciated that the various embodiments discussed herein have numerous potential applications and are not limited to a certain field of electronic media or type of data storage devices.