Diagnostic protocol and display system

A diagnostic protocol and display system wherein the cable bus output of a computer to a printer is sensed to select coded error data out of the output stream in order to activate a visual display of coded error data for benefit of the human operator.

FIELD OF THE INVENTION 
This disclosure relates to systems for diagnosing and displaying status and 
error conditions in a personal computer environment. 
BACKGROUND OF THE INVENTION 
As seen in FIG. 4A, a personal computer will generally have a line printer 
connector and a cable which is connected to a printer such as printer 40 
in order to print out required data which has been processed in the 
computer. Thus the line printer connector uses a cable A in order to make 
the connection to the printer 40 from the personal computer (PC) 
motherboard 10.sub.m. 
At the same time it has been found desirable to also display, using a 
display means, the status of the personal computer and any error 
indications which may result from diagnostic operations. Thus the problem 
arises as to how to provide some means for displaying error or status 
conditions in the personal computer (PC) with a minimal interference to 
and a minimal amount of extra hardware changes to the personal computer 
platform. 
As seen in FIG. 4B, the present disclosure arranges for the interconnection 
of a newly modified cable AA such that while the same output connection is 
made to the printer 40, there is a corresponding extension cable 10.sub.c 
which is connected to a power control card 20 which enables signals to be 
provided to a display panel 30. The display panel 30 has three digital 
displays demarked as display position 0, display position 1 and display 
position 2. Additionally, the display panel 30 provides a series of light 
emitting diode signals and a set/reset button. 
While the prior art and otherwise normal handling of adding a display 
system to a PC motherboard would normally require the use of another card 
slot with the insertion of a printed circuit board for the card slot, the 
present disclosure enables the elimination of any need for a printed 
circuit slot on another printed circuit board. No changes are required to 
the hardware of the personal computer motherboard except for a new 
internal Y-ribbon cable, designated cable AA (FIG. 4B), which shares the 
common line printer interface but still does not disrupt the normal 
printer operations that are concurrently ongoing. 
SUMMARY OF THE INVENTION 
The line printer output connector of a personal computer motherboard is 
modified to also feed a power control card which regulates a display panel 
permitting code numbered displays which will indicate the status condition 
of the personal computer and also any error conditions as a result of 
diagnostic operations. 
The personal computer includes a disk unit with software which provides 
diagnostic routines through which the results can be output onto the 
display panel for operator view and analysis. 
A single output cable from the personal computer has buses which feed data 
to a printer and buses which feed a power control card having a state 
machine with a protocol that implements a special display. The state 
machine recognizes error code data destined for diagnostic display via a 
"Sequence 1" and "Sequence 2" signal from the personal computer. The state 
machine conveys error code data, when necessary, for display on windows in 
a display panel unit visible to an operator.

DESCRIPTION OF PREFERRED EMBODIMENT 
A general overview of the presently described diagnostic protocol and 
display system is seen in FIG. 1 in block diagram form. A personal 
computer 10 includes a motherboard 10.sub.m which holds a buffer 10.sub.b 
whereby coded data is sent to a printer 40 for printout. Additionally, the 
buffer 10.sub.b also connects to a power control card 20 having a buffer 
20.sub.b which provides data to a State Machine Unit 22 which functions to 
interpret status data of the computer and error data in the computer into 
signals which can be displayed on display unit 30. 
FIG. 2 shows a more detailed diagram of the diagnostic protocol and display 
system of FIG. 1. As seen in FIG. 2, the motherboard 10.sub.m provides a 
parallel printer interface 16 which holds a data register 16.sub.r which 
then terminates in a port LPT1 (line printer terminal port) on which an 8 
bit bus 16.sub.b feeds the buffer 10.sub.b. Additionally, the personal 
computer motherboard 10.sub.m also holds a control register 10.sub.c. 
The PC buffer 10.sub.b has a cable or bus 16.sub.p which feeds the printer 
40. Additionally, a cable AA (as also seen in FIG. 4B) encompasses a 
series of busses (16.sub.p, 16.sub.t, 16.sub.a, 16.sub.s) some of which 
feed the power control card (PCC) 20 and the display panel 30. 
The bus 16.sub.t feeds 4 bits of data from the buffer 10.sub.b to the 
display panel 30. The other parts of cable AA involve the busses 16.sub.a 
and 16.sub.s. The bus 16.sub.a is designated as the auto FEED-B (CLK) 
clock signal to the State Machine Unit 22. The bus 16.sub.s carries 4 bits 
of data "commands" from the parallel printer interface 16 over to the 
State Machine Unit 22. The State Machine Unit 22 provides the protocol 
logic for the display panel unit 30, that is to say, a set of signals are 
sent to the display panel 30 in order to activate three display windows 
designated as digit position 0, digit position 1, and digit position 2, 
the entire 3-position window being designated as item 32. The State 
Machine Unit 22 is seen to have a fault register 22.sub.f and a no-blank 
register 22.sub.n. The state machine has an input on line 19 from the hard 
reset button 33 of display panel unit 30 and also has another input (power 
up override) on line 18 from the power supply 12. 
The State Machine Unit 22 functions as protocol logic unit. This unit 22 
has a series of output lines which are fed to the display panel unit 30. 
The line 22.sub.e is used to activate a light emitting device (LED) on the 
display panel unit 30. The line 22.sub.s is the line for setting or 
resetting the fault register 22.sub.f and provides an output from State 
Machine Unit 22 based on a command sent to the state machine. When the 
command (data bits [7:4]) equals 4, the fault register 22f is set and when 
the command (data bits [7:4]) equals 5, the fault register 22f is reset. 
The fault register operates to indicate that the system has detected an 
error condition and that the error code (describing that condition) is 
being displayed on the digital windows 32. 
The lines 22.sub.0, 22.sub.1 and 22.sub.2 are the latching lines for the 
display windows for digit position 0, digit position 1, and digit position 
2 respectively. The line 22.sub.3 is the "no-blank" line to the display 
panel unit 30 which "enables" the digit windows 32 for display of codes. 
The display panel unit 30 is seen having a digit display panel with windows 
32. These windows indicate the available digit windows for coded 
information as is shown in FIG. 1 as 2-1-0, i.e. digital window location 
2, digital window location 1, and digital window location 0. 
The power control card display panel unit 30 has the display windows 32 
showing three hexadecimal LED digit positions 0, 1, 2, which can be used 
to display information related to the status of the system. A special 
"display panel protocol" is used to write to the display panel unit 30 
through the 8-bit parallel printer port LPT1, seen in FIG. 2. This is done 
via bus 16.sub.t, FIG. 2. 
The display logic in the protocol logic card of State Machine Unit 22 also 
contains the "fault register" 22.sub.f and also a "no-blank register", 
22.sub.n. If the fault register 22.sub.f is "set", the fault-light 
emitting diode 33.sub.f (LED) on the display panel unit 30 will be turned 
"on". If the no-blank register 22.sub.n is "set", the display panel digits 
in windows 32 will be lit. 
Once set, both the fault register 22.sub.f and the no-blank register 
22.sub.n will remain "set" and can only be reset with subsequent commands 
or by depressing the "hard reset button" 33 on the display panel unit 30. 
Two of the three registers, namely the "Data Register 16.sub.r and the 
Control Register 10.sub.c associated with the parallel port printer 
interface 16 are used to send the commands and data to the display panel 
30. 
The logic in State Machine Unit 22, FIG. 2 used to implement the protocol, 
is implemented via a Programmable Array Logic Unit such as a 22V10- as 
manufactured by the Motorola Corp. or National Semiconductor Corp. 
INITIALIZATION: Upon powering up of the system in FIG. 2, all states in the 
programmable array logic of State Machine Unit 22 will be initialized to 
"0" such that the fault register 22.sub.f and the no-blank register 
22.sub.n are reset. During the period of time that the "power up" override 
signal on line 18 is asserted (generally about 7 seconds in the worst 
case), the display digits on window 32 will be lit. 
During this period of time, the display logic in the State Machine Unit 22 
will be fully functional and will accept commands from the line printer 
port LPT1, from interface 16. 
Default, (after the Power-up Override Signal on line 18, FIG. 2) will be 
de-asserted to provide for the display digits on windows 32 to be "blank" 
unless the "no-blank register 22.sub.n " has been "set" through a command 
during that time. The system software (in the disk unit of PC10) sends a 
command (CMD-7) to the display logic in State Machine Unit 22 in order to 
"un-blank" the display (via line 22.sub.3) prior to writing to it. 
The system software sends a display command by writing to the line printer 
port (LPT1). it is now up to the State Machine Unit 22 to sense that this 
data is "not" for the printer 40, but rather for the display unit 30. This 
"sensing" is arranged by use of the "Sequence 1" and "Sequence 2" signals. 
Thus a valid command for display operation in State Machine Unit 22 must 
be preceded by the SEQ1 and SEQ2 signals which activate the State Machine 
22 and indicate that the data is for the display windows 32 on display 
unit 30. 
The "hard reset" button 33 on the display panel 30 (FIG. 2) operates such 
that when depressed, it will send a "reset" to the motherboard 10.sub.m as 
well as to the display logic in the programmable array logic protocol 
state machine 22. This hard reset signal will clear all states to "0" 
and also reset the "fault register" 22.sub.f and also the "no-blank" 
register 22.sub.n. However, the current contents of the display digits, in 
window 32, will be unchanged at this time. 
POWER CONTROL CARD DISPLAY COMMAND DEFINITIONS 
The bits (7:4) of the port LPT1 data register 16.sub.r, (FIG. 2) are used 
to define the power control card 20 (PCC) display commands and the bits 
(3:0) are used to hold the display values to be written to any one of the 
three display digit positional windows 32. The cable AA data bits (7:0) 
are defined as follows, and shown in the attached Table I. 
TABLE I 
______________________________________ 
bit bit 
7 6 5 4 CMD FUNCTION 3 2 1 0 
______________________________________ 
1 0 1 0 A Sequence 1 x x x x 
1 1 0 0 C Sequence 2 x x x x 
0 0 0 0 0 no operation x x x x 
0 0 0 1 1 Write to digit 0 
(display value) 
0 0 1 0 2 Write to digit 1 
(display value) 
0 0 1 1 3 Write to digit 2 
(display value) 
0 1 0 0 4 Reset Fault Register 
x x x x 
0 1 0 1 5 Set Fault Register 
x x x x 
0 1 1 0 6 Blank display 
x x x x 
0 1 1 1 7 Do not blank display 
x x x x 
______________________________________ 
Note: x = don't care; undefined states will be ignored. 
Table I shows the 8-bits of bus 16.sub.b (FIG. 2) which are encompassed in 
FIG. 2 by the data bus 16.sub.t and the command bus 16.sub.s. Table I 
shows how bit locations 4, 5, 6 and 7 are organized to provide the various 
commands A, C, 0 thru 7 in addition to the individual functions provided 
by each of these commands. The bit locations 0, 1, 2, 3, are undefined 
states which can be ignored, except for the commands 1, 2, and 3, which 
write respectively to the digit location 0, the digit location 1, and the 
digit location 2 of windows 32 for displaying a value which represents 
useful information to the operator. 
POWER CONTROL CARD SIGNALS FOR DISPLAY INPUT CONTROL 
The line printer terminal port LPT1 has a parallel printer interface unit 
16, FIG. 2, which provides control signals to the PCC card 20 which are 
sourced by the LPT1 control register 10.sub.c on the motherboard, 
10.sub.m. The LPT1 control register 10.sub.c is shown on the PC 
motherboard 10.sub.m of FIG. 2. On the control signals (listed below), and 
transmitted to the power control card 20, it should be indicated that the 
signal names which end in ".sub.-- B" are "low" active signals. The 
following control signals are sourced by the control register 10.sub.c : 
Bit 0: STROBE.sub.-- B: This signal is low active on the LPT1 bus 
(16.sub.t) and a "1" must be written to the LPT1 data register 16.sub.r to 
cause it to be asserted. This signal is not used in the PCC display logic 
State Machine Unit 22. 
Bit 1: AUTOFEED.sub.-- B: This signal on bus 16.sub.a is used to simulate a 
clock to the power control card logic protocol State Machine Unit 22. Bit 
1 of the control register 10.sub.c must be initialized to a "1". To send a 
clock, this bit must be toggled from "1" to "0" and then back to "1". This 
signal is inverted twice to delay it to a minimum of 20 nanoseconds before 
entering the programmable array logic of the State Machine Unit 22. This 
is discussed further in the programming example provided hereinafter in 
FIG. 6. 
Bit 2: INIT: This signal is not used in the display logic of State Machine 
Unit 22. During the PCC display accesses, the original state of this bit 
is left unchanged in order to avoid erroneously initializing the printer. 
This signal is used on bus 16.sub.p of FIG. 2 for initializing the printer 
40. 
Bit 3: SELECT.sub.-- B: This signal is not used in the PCC State Machine 
Unit logic 22.sub.p. During the PCC display accesses, the original state 
of this bit is left unchanged. 
Bit 4: ENABLE INTERRUPT: This bit must be reset in order to inhibit 
interrupts from being generated to the motherboard 10.sub.m while the PCC 
display 30 is being accessed. This bit is reset within the motherboard 
10.sub.m and is not transmitted to the display logic in the protocol State 
Machine 22. 
Signals that are used for transmission from PCC 20 (Power Control Card) to 
the display unit 30 include: 
(a) PWRUP-OVRD: (Power-Up Override) This signal on line 18 is "high" upon 
power-up of the operating system and remains high for about 6 to 7 
seconds. During this period of time, the logic that monitors cooling fan 
failures is disabled. This signal is used to force the "no-blank" signal 
on line 22.sub.3 to be "low" such that the contents of the three panel 
display digits 32 are "lit". 
(b) H.sub.-- RST: (Hard Reset Bar) This signal on line 19 is asserted when 
the "reset" switch 33 on the display panel unit 30 is depressed. While the 
switch is depressed, the display logic State Machine Unit 22 will be 
cleared to state "0", and the fault register 22.sub.f and the no-blank 
register 22.sub.n will be reset. The display logic state machine is shown 
at block 22 of the power control card 20 of FIG. 2. 
FIG. 3 is a flow chart showing the operation of the diagnostic protocol and 
display system. At step A it is seen that the personal computer 10 is 
operating in conjunction with the running of diagnostic software. No 
action occurs until such time (B) as the diagnostic software detects an 
error. 
Upon detection of an error at step B, the personal computer 10 will send an 
error command to the operating program in the personal computer (PC 10), 
to initiate diagnostic display code information. 
Thus at step C, the commands from the personal computer will activate the 
power control card 20 and initiate action whereby various status commands 
and digital value data will be sent to the display panel 30. This is shown 
at step D and step E. 
As seen in FIG. 5 the State Machine Unit 22 controls and operates through 
some eight different state conditions. These are designated as ST=0, ST=1, 
. . . ST=6, ST=7, as seen in FIG. 5. 
The attached Table II shows the definition of various symbols used in the 
functional equations as shown in Table IV. 
TABLE II 
______________________________________ 
! LOGICAL NOT 
If before an output term, it means output is active 
LOW when equation is TRUE. If before an input term, 
it means input is active LOW for that term to be TRUE. 
& LOGICAL AND 
# LOGICAL OR 
:= Clocked output. Output given value of equation 
following rising edge of clock. 
= Combinatorial output. Output will be determined by 
logic equation and combinatorial enabling term. 
.ar Asynchronous rest. 
.oe Output enable. 
______________________________________ 
As illustrated in FIG. 5, the State Machine Unit 22 in the PCC 20 is 
normally at ST=0 looking for a valid command. Any valid command to the PCC 
must be preceded by a command of "SEQ1" and a command of "SEQ2". This 
scheme ensures that the State Machine Unit 22 will only respond to 
"genuine" Panel Display commands. When a "SEQ1" command is received at 
ST=0, the state machine changes its state to ST=1, expecting to receive 
"SEQ2" command next. If a "SEQ2" command is "not" received with the next 
clock, the state machine changes its state back to ST=0 and starts looking 
for a command of "SEQ1" again. If, while at ST=1, it receives a command of 
"SEQ2" with the next clock, the state machine changes its state from ST=1 
to ST=2. 
At ST=2, the State Machine Unit 22 is enabled, and with the next clock, 
will look for the particular command. If the command is "1" (See Table I, 
Command List) then the state machine changes its state to ST=3. If the 
command is "2" then the state machine changes its state to ST=4. If the 
command is "3" then the state machine changes it state to ST=5. If the 
command is "4 or 5" then the state machine changes its state to ST=6. If 
the command is "6 or 7" then the state machine changes its state to ST=7. 
The next clock will see the state machine going back to ST=0. 
At ST=3, "Latch 0" will be asserted and set in order to write to digit 
position 0 of the display. At ST=4, "Latch 1" will be asserted and set in 
order to write to digit position 1 of the display. At ST=5, "Latch 2" will 
be asserted and set to write to digit position 2 of the display. At ST=6, 
if the command received had been "4", (Table I) then "fault reg set/reset" 
line (22.sub.s) will be "low" to reset the fault register. At ST=6, if the 
command received had been "5", (Table I) then "fault reg set/reset" line 
(22.sub.s) will be "high" to set the fault register. At ST=7, if the 
command received had been "6", (Table I) then the "no blank" signal 
(22.sub.3) will be "low" to blank the display. At ST=7, if the command 
received had been "7", (Table I) then the "no blank" signal (22.sub.3) 
will be "high" to "not blank" the display. 
Table III shows the input pins to the programmable address logic of the 
display unit 30, FIG. 2. 
TABLE III 
______________________________________ 
Input Pin Definitions For Disiplay (State Machine 22) 
______________________________________ 
h.sub.-- rst 
pin 2; "hard push button rest" 
spare pin 3; "not used" 
init.sub.-- b 
pin 4; 
strobe pin 5; "s/b low all the time" 
select pin 10; "s/b low to enable pcc display" 
clockin pin 1; "clock derived from autofeed.sub.-- b" 
data 4 pin 6; 
data 5 pin 7; 
data 6 pin 8; 
data 7 pin 9; 
cmd = [data7,data6,data5,data4]; 
seq1 = [1, 0, 1, 0]; "first qualifying pattern." 
______________________________________ 
The logic operation of the various state conditions shown in FIG. 5 can be 
described by a series of logic equations which are attached here below as 
Table IV (using the notations of Table II). 
TABLE IV 
______________________________________ 
[st,latch.sub.-- dig0,latch.sub.-- dig1,latch.sub.-- disg2, 
sys.sub.-- fault].oe = pal.sub.-- test1; 
[noblank.sub.-- reg,no.sub.-- blank.sub.-- b].oe = ap1.sub.-- test1; 
[sys.sub.-- fault,noblank.sub.-- reg,st].clk = clockin; 
[sys.sub.-- fault,noblank.sub.-- reg,st].ar = h.sub.-- rst*!pwrup.sub.-- 
ovrd 
no.sub.-- blank.sub.-- b = !noblank.sub.-- reg; 
state.sub.-- diagram st 
state st0: 
noblank.sub.-- reg := noblank.sub.-- reg; 
sys.sub.-- fault := sys.sub.-- fault; 
if (cmd == seq1) then st1 else st0; 
state st1: 
noblank.sub.-- reg := noblank.sub.-- reg; 
sys.sub.-- fault := sys.sub.-- fault; 
if (cmd == seq2) then st2 else 
if (cmd == seq1) then st1 else st0; 
state st2: 
noblank.sub.-- reg := noblank.sub.-- reg; 
sys.sub.-- fault := sys.sub.-- fault; 
if (cmd == latch0) then st3 else 
if (cmd == latch1) then st4 else 
if (cmd == latch2) then st5 else 
if (cmd == cmd.sub.-- fault) then st6 else 
if (cmd == cmd.sub.-- blank) then st7 else st0; 
state st3: 
sys.sub.-- fault := sys.sub.-- fault; 
noblank.sub.-- reg := noblank.sub.-- reg; 
latch.sub.-- dig0 = 1; 
goto st0; 
state st4: 
sys.sub.-- fault := sys.sub.-- fault; 
noblank.sub.-- reg := noblank.sub.-- reg; 
latch.sub.-- dig1 = 1; 
goto st0; 
state st5: 
sys.sub.-- fault := sys.sub.-- fault; 
noblank.sub.-- reg := noblank.sub.-- reg; 
latch.sub.-- dig2 = 1; 
goto st0; 
state st6: 
"set or reset fault register" 
sys.sub.-- fault := data 4; 
noblank.sub.-- reg := noblank.sub.-- reg; 
state st7: 
"set or reset noblank register" 
noblank.sub.-- reg := data 4; 
sys.sub.-- fault := sys.sub.-- fault; 
goto st0; 
______________________________________ 
The attached Table V provides a definition of the data bits involved for 
the functions of the various eight bits of data presented to the display 
unit 30. 
TABLE V 
______________________________________ 
Definition Of Data Bits 
bit (line 16.sub.s FIG. 2) bit (Data Line 16.sub.t, FIG. 2) 
7 6 4 5 FUNCTION 3 2 1 0 
______________________________________ 
1 0 1 0 Qualifying seq 1 
x x x x 
1 1 0 0 Qualifying seq 2 
x x x x 
0 0 0 1 Write to digit 0 
[display value 0-F] 
0 0 1 0 Write to digit 1 
[display value O-F] 
0 0 1 1 Write to digit 2 
[display value O-F] 
0 1 0 0 Reset Fault Register 
x x x x 
0 1 0 1 Set Fault Register 
x x x x 
0 1 1 0 Blank display 
x x x x 
0 1 1 1 Do not blank display 
x x x x 
______________________________________ 
FIG. 6 is a display timing diagram which is used in conjunction with an 
example of writing "A" to the digit position "0". 
At line 1 of FIG. 6, the data commands are provided for "A" (hexadecimal) 
and subsequently "C" (hexadecimal) with the subsequent period for writing 
to digit position 1. 
On line 2 of FIG. 6, the initial period for the four data bits is 
irrelevant until the later portion where the value of "A" in hexadecimal 
is digitally presented. 
In line 3 of FIG. 6, the autofeed clocking signal is initiated at state=0 
and operates through state 1, state 2, state 3, and back to state 0 on the 
fourth clock (clock 4). 
Seen below is a programming example of the assembly program which 
illustrates the coding in order to implement a command such as "Write to 
digit position 1" with the value of "A" (hexadecimal). 
PROGRAMMING EXAMPLE 
The following assembly program illustrates the code to implement a "Write 
to digit 1" command with a value of "A" (hexadecimal). Note the section 
below, labelled "INITIALIZE", which starts off the current values of the 
LPT1 data register 16r as well as the LPT1 Control Register 16.sub.c. For 
this example, the LPT1 port address for the Data Register is at "3BC" and 
the corresponding Control Register is at "3BE". This program example is 
based on assembly code instructions used in Intel processors as referenced 
in the Intel iAPX 86/88, i86/i88, 186/188 User's Manual (Programmer's 
Reference) May 1983 at pages 3-39 through 3-170, published by Intel 
Corporation, 3065 Bowers Ave., Santa Clara, Calif. 95051. 
__________________________________________________________________________ 
INITIALIZE: 
MOV DX, 3BC 
IN AL, DX 
MOV[SAVE], al 
;SAVE OFF CURRENT VALUES OF 
MOV DX, 3BE 
;DATA AND CONTROL REGISTERS IN MEMORY 
IN AL, DX 
MOV[SAVE2], AL 
OUT DX, AL 
START: 
MOV DX, 3BC 
MOV AL, A0 
;SEQ1 
OUT DX, AL 
MOV DX, 3BE 
MOV AL, [SAVE2] 
AND AL, FC 
;"0" TO AUTOFEED BIT TO SEND CLOCK. 
OUT DX, AL 
;CLOCK #1 
OR AL, 2 ;"1" TO AUTOFEED BIT FOR NEG.CLOCK EDGE 
OUT DX, AL 
MOV DX, 3BC 
MOV AL, C0 
SEQ 2 
OUT DX, AL 
MOV DX, 3BE 
MOV AL, [SAVE2] 
AND AL, FC 
;"0" TO AUTOFEED BIT TO SEND CLOCK. 
OUT DX, AL 
;CLOCK #2 
OR AL, 2 ;"1" TO AUTOFEED BIT FOR NEG. CLOCK EDGE 
OUT DX, AL 
MOV DX, 3BC 
MOV AL, 2A 
;COMMAND TO WRITE DIGIT 1 WITH "A" 
OUT DX, AL 
MOV AL, [SAVE2] 
AND AL, FC 
;"0" TO AUTOFEED BIT TO SEND CLOCK. 
OUT DX, AL 
;CLOCK #3 
OR AL, 2 ;"1" TO AUTOFEED BIT FOR NEG. CLOCK EDGE 
OUT DX, AL 
MOV DX, 3BE 
MOV AL, [SAVE2] 
AND AL, FC 
;"0" TO AUTOFEED BIT TO SEND CLOCK. 
OUT DX, AL 
;CLOCK #4 
OR AL, 2 ;"1" TO AUTOFEED BIT FOR NEG. CLOCK EDGE 
OUT DX, AL 
(GO TO "START" IF MORE COMMANDS ELSE GO TO FINISH) 
FINISH: 
MOV DX, 3BC 
MOV AL, [SAVE1] 
OUT DX, AL 
;REPLACE PRIOR VALUE TO DATA REG. 
MOV AL, [SAV2] 
MOV DX, 3BE 
OUT DX, AL 
;REPLACE PRIOR VALUE TO CONTROL REG. 
END OF EXAMPLE-- 
__________________________________________________________________________ 
Described herein is a system where the output bus cable of a personal 
computer is used in a dual function, that is (i) to convey data to a 
printer and (ii) to convey codes representing error conditions to a power 
control card holding a state machine which recognizes error codes as 
different from printer data, and selects the error codes for display on a 
display panel unit thus informing the operator of various error conditions 
occurring. 
While the preferred embodiment illustrates one example of effectuating both 
printer operations and diagnostic error readout from the same output 
cable, it should be understood that other implementations may still be 
encompassed by the following claims.