Chip package structure and fabricating method thereof

A chip package structure including a chip, a lead frame, first bonding wires and second bonding wires is provided. The chip has an active surface and chip bonding pads disposed thereon. The lead frame is fixed on the chip and the lead frame includes inner leads, at least one bus bar, an insulating layer and transfer bonding pads. The bus bar is located between the chip bonding pads and the inner leads. The insulating layer is disposed on the bus bar and the transfer bonding pads are disposed thereon. The inner leads and the bus bar are located above the active surface. The chip and the insulating layer are located respectively on two opposite surfaces of the bus bar. The first bonding wires respectively connect the chip bonding pads and the transfer bonding pads. The second bonding wires respectively connect the transfer bonding pads and the inner leads.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention relates to a semiconductor device and a fabricating method thereof. More particularly, the present invention relates to a chip package structure and a fabricating method thereof.

2. Description of Related Art

In the semiconductor industry, the fabrication of an integrated circuit (IC) is mainly divided into three stages: IC design, IC process and IC package.

During the fabrication of ICs, a chip is made by the steps of wafer fabricating, IC forming, wafer sawing and so on. The wafer has an active surface, which generally refers to a surface having active devices of the wafer. When the IC on the wafer is finished, a plurality of bonding pads is further disposed on the active surface of the wafer, such that the chip formed by wafer sawing is electrically connected to a carrier outward via the bonding pads. The carrier is, for example, a lead frame or a package substrate. The chip can be connected to the carrier by means of wire bonding or flip-chip bonding, such that the bonding pads of the chip are electrically connected to the contacts of the carrier, thus forming a chip package structure.

FIG. 1Ais a schematic sectional side view of a conventional chip package structure.FIG. 1Bis a schematic top view of a portion of the members of the chip package structure inFIG. 1A. Referring toFIGS. 1A and 1B, a conventional chip package structure100comprises a chip110, a lead frame120, a plurality of first bonding wires130, a plurality of second bonding wires140, a plurality of third bonding wires150and an encapsulant160. The chip110has an active surface112and a plurality of first bonding pads114and second bonding pads116disposed on the active surface112. The chip110is fixed below the lead frame120, and the lead frame120includes a plurality of inner leads122and a bus bar124. The inner leads122and the bus bar124are located above or below the active surface112of the chip110, and the bus bar124is in an annular shape.

Referring toFIG. 1B, as the first bonding pads114of the chip110have the same electric potential, and the first bonding pads114are, for example, ground bonding pads or power supply bonding pads, thus the first bonding pads114of the same electric potential are respectively connected to the bus bar124via the first bonding wires130, and the bus bar124is further connected to the corresponding portion of the inner leads122via the second bonding wires140. However, the second bonding pads116of the chip110for transmitting signals (for example, signal bonding pads with ever-changing electric potentials) must be connected to other corresponding inner leads122via the third bonding wires150, and the third bonding wires150usually have to cross a portion of the first bonding wires130, a portion of the second bonding wires140and the bus bar124. Therefore, the third bonding wires150are quite long, which is likely to make the third bonding wires150collapsed, thereby causing electric shorts. Or, the third bonding wires150may be collapsed during molding or being pulled apart by the injected encapsulant, thus causing electric broken circuits.

SUMMARY OF THE INVENTION

An objective of the present invention is to provide a chip package structure, so as to reduce the possibility of the collapse of the bonding wires.

Another objective of the present invention is to provide a method of fabricating the chip package structure, so as to improve the product yield of the chip package structure.

To achieve the above or other objectives, the present invention provides a chip package structure, which comprises a chip, a lead frame, a plurality of first bonding wires and a plurality of second bonding wires. The chip has an active surface and a plurality of chip bonding pads disposed on the active surface. The lead frame fixed on the chip and the lead frame comprises a plurality of inner leads, at least one bus bar, an insulating layer and a plurality of transfer bonding pads. The bus bar is located between the chip bonding pads and the inner leads. The insulating layer is disposed on the bus bar. The transfer bonding pads are disposed on the insulating layer. The inner leads and the bus bar are located above the active surface of the chip. The chip and the insulating layer are located respectively on two opposite surfaces of the bus bar. The first bonding wires respectively connect the chip bonding pads and the transfer bonding pads. The second bonding wires respectively connect the transfer bonding pads and the inner leads.

In an embodiment of the present invention, the bus bar can be in an annular shape.

In an embodiment of the present invention, the bus bar can be in a strip shape.

In an embodiment of the present invention, the chip package structure further comprises an encapsulant, so as to cover the active surface, the inner leads, the bus bar, the first bonding wires and the second bonding wires.

To achieve the above or other objectives, the present invention provides a chip package structure, which comprises a chip, a lead frame, a plurality of first bonding wires and a plurality of second bonding wires. The chip has an active surface and a plurality of chip bonding pads disposed on the active surface. The lead frame comprises a die pad, a plurality of inner leads, at least one bus bar, an insulating layer and a plurality of transfer bonding pads. The chip is disposed on the die pad and the active surface is away from the die pad. The bus bar is located between the die pad and the inner leads. The insulating layer is disposed on the bus bar. The transfer bonding pads are disposed on the insulating layer. The first bonding wires respectively connect the chip bonding pads and the transfer bonding pads. The second bonding wires respectively connect the transfer bonding pads and the inner leads.

In an embodiment of the present invention, the bus bar can be in an annular shape.

In an embodiment of the present invention, the bus bar can be in a strip-shape.

In an embodiment of the present invention, the chip package structure further comprises an encapsulant, so as to cover the active surface, the die pad, the inner leads, the bus bar, the first bonding wires and the second bonding wires.

To achieve the above or other objectives, the present invention provides a method of fabricating the chip package structure, which comprises the following steps. First, a lead frame comprising a plurality of inner leads and at least one bus bar is provided. Then, an insulating layer is formed on the bus bar. Next, a plurality of transfer bonding pads is formed on the insulating layer. Afterward, a chip having an active surface and a plurality of chip bonding pads disposed on the active surface is provided. Thereafter, the chip is fixed below the lead frame, such that the inner leads and the bus bar are located above the active surface of the chip, and the chip and the insulating layer are located on two opposite surfaces of the bus bar. Next, a plurality of first bonding wires is formed to respectively connect the chip bonding pads and the transfer bonding pads. A plurality of second bonding wires is then formed to respectively connect the transfer bonding pads and the inner leads.

In an embodiment of the present invention, the above method of fabricating the chip package structure further comprises forming an encapsulant for covering the active surface, the inner leads, the bus bar, the first bonding wires and the second bonding wires.

To achieve the above or other objectives, the present invention provides a method of fabricating the chip package structure, which comprises the following steps. First, a lead frame comprising a die pad, a plurality of inner leads and at least one bus bar is provided, wherein the bus bar is located between the die pad and the inner leads. Then, an insulating layer is formed on the bus bar. Next, a plurality of transfer bonding pads is formed on the insulating layer. Afterward, a chip having an active surface and a plurality of chip bonding pads disposed on the active surface is provided. Thereafter, the chip is fixed on the die pad, wherein the active surface is away from the die pad. Next, a plurality of first bonding wires is formed to respectively connect the chip bonding pads and the transfer bonding pads. A plurality of second bonding wires is then formed to respectively connect the transfer bonding pads and the inner leads.

In an embodiment of the present invention, the above method of fabricating the chip package structure further comprises forming an encapsulant for covering the active surface, the die pad, the inner leads, the bus bar, the first bonding wires and the second bonding wires.

In view of the above, in the present invention, the transfer bonding pads are formed on the bus bar and are used as transfer points for the chip bonding pads being electrically connected to the inner leads respectively, so the desired first bonding wires and second bonding wires are very short, thus reducing the possibility of the collapse of the first bonding wires and the second bonding wires. In addition, as the first bonding wires and the second bonding wires are very short, the possibility of the first bonding wires and the second bonding wires being collapsed during molding or being pulled apart by the injected encapsulant may be reduced.

In order to make the aforementioned and other objectives, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

DESCRIPTION OF EMBODIMENTS

The First Embodiment

FIG. 2Ais a schematic sectional side view of a chip package structure according to the first embodiment of the present invention.FIG. 2Bis a schematic top view of the lead frame of the chip package structure inFIG. 2A. Referring toFIGS. 2A and 2B, a chip package structure200of the first embodiment comprises a chip210, a lead frame220, a plurality of first bonding wires230and a plurality of second bonding wires240. The chip210has an active surface212and a plurality of chip bonding pads214disposed on the active surface212. In addition, the chip bonding pads214may be ground bonding pads, power supply bonding pads or signal bonding pads.

The lead frame220fixed on the chip210comprises a plurality of inner leads222, at least one bus bar224, an insulating layer226and a plurality of transfer bonding pads228. The bus bar224is located between the chip bonding pads214and the inner leads222. The insulating layer226is disposed on the bus bar224. The transfer bonding pads228are disposed on the insulating layer226. The inner leads222and the bus bar224are located above the active surface212of the chip210. The chip210and the insulating layer226are respectively located on two opposite surfaces224a,224bof the bus bar224.

The first bonding wires230are used to respectively connect the chip bonding pads214to the transfer bonding pads228. The second bonding wires240are used to respectively connect the transfer bonding pads228to the inner leads222. In the first embodiment, the chip package structure200further comprises an encapsulant250, so as to cover the active surface212, the inner leads222, the bus bar224, the first bonding wires230and the second bonding wires240.

It should be illustrated that, comparing the chip package structure200in the first embodiment with the conventional chip package structure100(referring toFIGS. 1A and 1B), the chip bonding pads214are respectively connected to the transfer bonding pads228by the first bonding wires230, and the transfer bonding pads228are respectively connected to the inner leads222by the second bonding wires240. In other words, the transfer bonding pads228function as the transfer points for the chip bonding pads214being electrically connected to the inner leads222correspondingly. Therefore, the first bonding wires230and the second bonding wires240are very short, thus eliminating the disadvantage of the conventional package structure100, and thereby raising the product yield of the chip package structure200of the first embodiment.

In the first embodiment, the shape of the bus bar224is annular and the quantity thereof is one. However, the appearance and quantity of the bus bar224may be varied according to the design requirement, i.e., the first embodiment is used to illustrate instead of to limit the present invention. For example, referring toFIG. 2C, it is a schematic top view of the lead frame of the chip package structure according to another embodiment of the present invention. In another embodiment, the bus bar224′ of the lead frame220′ may be strip-shaped and the quantity of the bus bar224′ may be several. Moreover, in the present embodiment, all the chip bonding pads214have the corresponding transfer bonding pads228for wire jumping. However, the present invention does not limit that every chip bonding pad must have a jumper wire.

The method of fabricating the chip package structure200in the first embodiment is illustrated below.FIGS. 3A to 3Fare schematic views of the method of fabricating the chip package structure according to the first embodiment of the present invention. The method comprises the following steps. First, referring toFIG. 3A, a lead frame220including a plurality of inner leads222and at least one bus bar224is provided.

Then, referring toFIG. 3B, an insulating layer226is formed on the bus bar224. In the first embodiment, the insulating layer226is formed by chemical vapor deposition (CVD) process. Then, a plurality of transfer bonding pads228is formed on the insulating layer226. In the first embodiment, a conductive material layer (not shown) can be formed on the insulating layer226by sputtering process, physical vapor deposition or other film deposition processes. After that, a patterning process (e.g., lithography process and etching process) is performed for the conductive material layer, so as to form a plurality of transfer bonding pads228on the insulating layer226.

Next, referring toFIG. 3C, a chip210is provided. The chip210has an active surface212and a plurality of chip bonding pads214, wherein the chip bonding pads214are disposed on the active surface212. Afterward, referring toFIG. 3D, the chip210is fixed below the lead frame220, such that the inner leads222and the bus bar224are located above the active surface212of the chip210, and the chip210and the insulating layer226are respectively located on two opposite surfaces224a,224bof the bus bar224.

Afterward, referring toFIG. 3E, a wiring process is performed to form a plurality of first bonding wires230, so as to respectively connect the chip bonding pads214and the transfer bonding pads228. Next, a plurality of second bonding wires240is formed sequentially to connect the transfer bonding pads228and the inner leads222respectively. Referring toFIG. 3F, in the first embodiment, the method of fabricating the chip package structure200further comprises forming an encapsulant250to cover the active surface212, the inner leads222, the bus bar224, the first bonding wires230and the second bonding wires240. The chip package structure200of the first embodiment is achieved through the above steps.

It should be stressed that, in the present embodiment, the transfer bonding pads228are formed on the bus bar224for facilitating wire jumping. More particularly, as the first bonding wires230and the second bonding wires240are very short, the possibility of electric shorts caused by the collapse of the first bonding wires230and the second bonding wires240is reduced. Or, the possibility of electric broken circuits caused by the collapse of the first bonding wires230and the second bonding wires240during the molding process or being pulled apart by the injected encapsulant260is reduced, thereby improving the product yield of the chip package structure200of the first embodiment.

The Second Embodiment

FIG. 4Ais a schematic sectional side view of a chip package structure according to the second embodiment of the present invention.FIG. 4Bis a schematic top view of the lead frame of the chip package structure inFIG. 4A. Referring toFIGS. 4A and 4B, the main difference between a chip package structure300in the second embodiment and the chip package structure200in the first embodiment is that: a lead frame320of the chip package structure300comprises a die pad P, a plurality of inner leads322, at least one bus bar324, an insulating layer326and a plurality of transfer bonding pads328. The chip310is disposed on the die pad P, and the active surface312is away from the die pad P. In other words, as for the relative position inFIG. 4A, the active surface312of the chip310faces upward. In addition, the bus bar324is located between the die pad P and the inner leads322.

The method of fabricating the chip package structure300according to the second embodiment is illustrated below.FIGS. 5A to 5Fare schematic views of the method of fabricating the chip package structure according to the second embodiment of the present invention. The method of the second embodiment comprises the following steps. First, referring toFIG. 5A, a lead frame320is provided. The lead frame320has a die pad P, a plurality of inner leads322and at least one bus bar324, wherein the bus bar324is located between the die pad P and the inner leads322.

Then, referring toFIG. 5B, an insulating layer326is formed on the bus bar324in the same manner as illustrated in the first embodiment. Thereafter, a plurality of transfer bonding pads328is formed on the insulating layer326in the same manner as illustrated in the first embodiment.

After that, referring toFIG. 5C, a chip310is provided. The chip has an active surface312and a plurality of chip bonding pads314, wherein the chip bonding pads314are disposed on the active surface312. Then, referring toFIG. 5D, the chip310is fixed on the die pad P, wherein the active surface312is away from the die pad P.

Next, referring toFIG. 5E, a wiring process is performed to form a plurality of first bonding wires330, so as to respectively connect the chip bonding pads314and the transfer bonding pads328. Then, a plurality of second bonding wires340is formed to respectively connect the transfer bonding pads328and the inner leads322. Referring toFIG. 5F, in the second embodiment, the method of fabricating the chip package structure300further comprises forming an encapsulant350to cover the active surface312, the die pad P, the inner leads322, the bus bar324, the first bonding wires330and the second bonding wires340.

In view of the above, the chip package structure and the fabricating method thereof in the present invention at least have the following advantages.

1. In the present invention, the transfer bonding pads are formed on the bus bar for carrying out wire jumping, so compared with the conventional art, the bonding wires formed in the present invention are shorter and lower, thereby enhancing the reliability of the chip package structure.

2. The chip bonding pads are connected to the transfer bonding pads via the first bonding wires, and the transfer bonding pads are connected to the inner leads via the second bonding wires. In other words, the transfer bonding pads function as transfer points for the chip bonding pads being electrically connected to the inner leads correspondingly. Therefore, the first bonding wires and the second bonding wires are very short, such that the possibility of electric short circuits caused by the collapse of the first bonding wires and the second bonding wires is reduced, thereby improving the product yield of the chip package structure of the present invention.

3. As the first bonding wires and the second bonding wires are very short, the possibility of electric broken circuits caused by the collapse of the first bonding wires and the second bonding wires during the molding process or being pulled apart by the injected encapsulant is reduced, thereby improving the product yield of the chip package structure of the present invention.

Though the present invention has been disclosed above by the preferred embodiments, they are not intended to limit the present invention. Anybody skilled in the art can make some modifications and variations without departing from the spirit and scope of the present invention. Therefore, the protecting range of the present invention falls in the appended claims.