Semiconductor component and method of manufacture

A semiconductor component having a memory cell coupled to a trench line and a method for manufacturing the semiconductor component. Trenches having sidewalls are formed in a semiconductor substrate and a trench line is formed in each trench. A polysilicon insert is formed between the trench line and each sidewall of the trench. A column of memory cells is formed between the trenches where each memory cell of the column of memory cells has a gate structure, a source region, and a drain region. The source regions of the column of memory cells are electrically coupled to the trench line on one side of the column of memory cells via one of the polysilicon inserts. The drain regions of the column of memory cells are electrically coupled to the trench line adjacent the opposite side of the column of memory cells via another of the polysilicon inserts.

FIELD OF THE INVENTION

This invention relates, in general, to memory devices and, more particularly, to memory devices having a flash architecture.

BACKGROUND OF THE INVENTION

Memory devices are used in a variety of electronic systems including computers, cellular phones, pagers, personal digital assistants, avionic systems, automotive systems, industrial control systems, appliances, etc. Depending on the particular system configuration, the memory devices may be either non-volatile or volatile. A non-volatile memory device retains the data or instructions stored therein when the device is turned off or power is removed. A volatile memory device, on the other hand, does not retain the stored data or instructions when the device is turned off. Flash memory has become an important type of non-volatile memory because it is less expensive to manufacture and denser than most other types of memory devices. In addition, Flash memory is electrically erasable and has a life span of up to one million write cycles.

Memory systems such as flash memory are typically configured on a semiconductor chip such that high density memory arrays occupy a central portion of the chip and lower density control and logic circuitry are placed along peripheral portions of the chip. The high-density memory arrays are typically comprised of memory cells arranged in columns and rows.FIG. 1is a schematic diagram illustrating a prior art memory array10in a NOR type circuit architecture. Memory array10comprises an array of memory cells12arranged in columns and rows, where each memory cell has a control gate terminal, a drain terminal, and a source terminal. Memory cells20,22,24, and26form a column. Their drain terminals connect to a bit line BL1and their source terminals connect to a source line SL. Likewise, memory cells30,32,34, and36form a column wherein their drain terminals connect to bit line BL2and their source terminals connect to source line SL. Memory cells40,42,44, and46form a column in which their drain terminals connect to bit line BL3and their source terminals connect to source line SL. Memory cells50,52,54, and56form a column in which their drain terminals connect to bit line BL4and their source terminals connect to source line SL.

The gate terminals of memory cells20,30,40, and50connect to a word line WL1. Likewise, the gate terminals of memory cells22,32,42, and52connect to a word line WL2; the gate terminals of memory cells24,34,44, and54connect to a word line WL3; and the gate terminals of memory cells26,36,46, and56connect to a word line WL4.

A drawback with this type of memory array configuration is the amount of silicon area it consumes. One reason this type of memory array configuration consumes a large silicon area is that one drain contact is required for every two memory cells.

Accordingly, what is needed is a memory device and a cost-effective method for manufacturing a memory device that increases the density of the memory cells of the memory array.

SUMMARY OF THE INVENTION

The present invention satisfies the foregoing need by providing a memory device and a method for manufacturing the memory device that increases the density of the memory cells. In accordance with one aspect, the present invention is a memory device comprising a substrate in which a trench is formed. The trench has first and second sidewalls and a floor. A first column of memory cells is adjacent the first sidewall of the trench. A trench line is disposed in the trench and is electrically coupled to the first column of memory cells.

In accordance with another aspect, the present invention comprises a memory device comprising first and second memory cells that cooperate to form a column of memory cells. Each of the first and second memory cells has a gate structure, a drain region, and a source region. The source region of the second memory cell is coupled to the source region of the first memory cell. A trench line is adjacent to the first column of memory cells. The source regions of the first and second memory cells are coupled to the trench line.

In accordance with yet another aspect, the present invention comprises a method for manufacturing a semiconductor component. A semiconductor substrate having a major surface is provided. A trench is formed in the semiconductor substrate, extends from the major surface into the semiconductor substrate, and has first and second sidewalls and a floor. A trench line is formed in the trench and inserts are formed between the trench line and the first and second sidewalls of the trench. A first doped region is formed in a portion of the semiconductor substrate adjacent the first sidewall of the first trench. A second doped region is formed in another portion of the semiconductor substrate adjacent the first sidewall of the trench, electrically connecting the trench to either the source or drain regions of the cell.

DETAILED DESCRIPTION

FIG. 2is a schematic diagram illustrating a sub-array100of a memory array in a NOR type circuit architecture in accordance with an embodiment of the present invention. Sub-array100is a 4×4 sub-array of memory cells102arranged in columns and rows, where each memory cell of sub-array100has a drain terminal, a source terminal, and a gate terminal. It should be understood that the size of sub-array100or the size of the array of memory cells is not a limitation of the present invention. For example, sub-array100can be a portion of an 8×8 array of memory cells, a 16×16 array of memory cells, 32×32 array of memory cells, a 64×64 array of memory cells, a 128×128 array of memory cells, a 256×256 array of memory cells, a 512×512 array of memory cells, a 1024×1024 array of memory cells, etc.

The columns of memory cells102are arranged along respective bit/trench lines BLTL1, BLTL2, BLTL3, BLTL4, etc. Memory cells110,112,114, and116of memory cell array100form a column118of memory cells along bit line BLTL1. Memory cells120,122,124, and126of memory cell array100form a column128of memory cells along bit line BLTL2. Memory cells130,132,134, and136of memory cell array100form a column138of memory cells along bit line BLTL3. Memory cells140,142,144, and146of memory cell array100form a column148of memory cells along bit line BLTL4.

The drain terminals of memory cells110,112,114, and116are connected to bit line BLTL1and the source terminals of memory cells110,112,114, and116are connected to a source line SL. The drain terminals of memory cells120,122,124, and126are connected to bit line BLTL2and the source terminals of memory cells120,122,124, and126are connected to bit line BLTL1. The drain terminals of memory cells130,132,134, and136are connected to bit line BLTL3and the source terminals of memory cells130,132,134, and136are connected to bit line BLTL2. The drain terminals of memory cells140,142,144, and146are connected to bit line BLTL4and the source terminals of memory cells140,142,144, and146are connected to bit line BLTL3.

The gate terminals of memory cells110,120,130, and140are connected to word line WL1. The gate terminals of memory cells112,122,132, and142are connected to word line WL2. The gate terminals of memory cells114,124,134, and144are connected to word line WL3. The gate terminals of memory cells116,126,136, and146are connected to word line WL4.

In operation, a memory cell is selected and programmed, read, or erased by applying the appropriate voltages to the gate, drain, and source terminals of the desired memory cell. The desired memory cell is selected or accessed by applying high voltages to the word line and to the bit line to which the respective gate and drain terminals of the desired memory cell are connected. And, applying a low voltage to the remaining word lines and bit lines. For example, if it is desired to select or access memory cell122shown inFIG. 2, a high voltage is applied to word line WL2and a high voltage is applied to bit line BLTL2, and a low voltage is applied to word lines WL1, WL3, and WL4and to bit lines BLTL1, BLTL3, and BLTL4, and to source line SL. In addition to selecting the desired memory cell, the voltages applied to the word lines, bit lines, and source line either program, read, or erase the selected memory cell. For example, memory cell122is programmed by applying a voltage ranging from about 5 volts to about 15 volts to word line WL2, connecting bit line BLTL1to ground, and applying a voltage to bit line BLTL2that is sufficiently higher than the voltage applied to bit line BLTL1(i.e., the voltage applied to the source terminal of memory cell122) to cause electrons to become trapped in the floating gate of memory cell122.

Memory cell122is read by applying a control voltage to word line WL2that is greater than the threshold voltage of an unprogrammed or erased memory cell, but less than the threshold voltage of a programmed memory cell. In addition, a ground potential is connected to bit line BLTL1and a voltage ranging from about one volt to about two volts is applied to bit line BLTL2. Because word line WL2is connected to the control gate of memory cell122, the voltage applied to word line WL2is also applied to the gate terminal of memory cell122. Likewise, the ground potential applied to bit line BLTL1is also applied to the source terminal of memory cell122and the voltage applied to bit line BLTL2is also applied to the drain terminal of memory cell122.

Memory cell122can be erased by applying a relatively high voltage to bit line BLTL1, i.e., the source terminal of memory cell122, while grounding word line WL2, i.e., the gate terminal of memory cell122, and allowing the bit line BLTL2, i.e., the drain terminal of memory cell122, to float. The method for erasing memory cell122is not a limitation of the present invention.

FIG. 3is a schematic diagram illustrating a sub-array200of a memory array in a NOR type circuit architecture in accordance with another embodiment of the present invention. Sub-array200is a 4×4 sub-array of memory cells202arranged in columns and rows, where each memory cell of sub-array200has a drain terminal, a source terminal, and a gate terminal. It should be understood that the size of sub-array200or the size of the array of memory cells is not a limitation of the present invention. For example, sub-array200can be a portion of an 8×8 array of memory cells, a 16×16 array of memory cells, 32×32 array of memory cells, a 64×64 array of memory cells, a 128×128 array of memory cells, a 256×256 array of memory cells, a 512×512 array of memory cells, a 1024×1024array of memory cells, etc.

The columns of memory cells202are arranged along respective bit lines BL1, BL2, BL3, BL4, etc. More particularly, memory cells210,212,214, and216of memory cell array202form a column218of memory cells along bit line BL1. Memory cells220,222,224, and226of memory cell array202form a column228of memory cells along bit line BL2. Memory cells230,232,234, and236of memory cell array202form a column238of memory cells along bit line BL3. Memory cells240,242,244, and246of memory cell array202form a column248of memory cells along bit line BL4. Accordingly, memory cells210and212form a set213in which the source terminals of memory cells210and212are commonly connected to each other and memory cells214and216form a set217having their source terminals commonly connected to each other. Likewise memory cells220and222form a set223, memory cells224and226form a set227, memory cells230and232form a set233, memory cells234and236form a set237, etc.

The drain terminals of memory cells210,212,214, and216are connected to bit line BL1, the source terminals of memory cells210and212are connected to a source line SL1, and the source terminals of memory cells214and216are connected to a source line SL2. The drain terminals of memory cells220,222,224, and226are connected to bit line BL2, the source terminals of memory cells220and222are connected to source line SL1, and the source terminals of memory cells224and226are connected to source line SL2. The drain terminals of memory cells230,232,234, and236are connected to bit line BL3, the source terminals of memory cells230and232are connected to source line SL1, and the source terminals of memory cells234and236are connected to source line SL2. The drain terminals of memory cells240,242,244, and246are connected to bit line BL4, the source terminals of memory cells240and242are connected to source line SL1, and the source terminals of memory cells244and246are connected to source line SL2. In addition, source lines SL1and SL2are connected to trench lines TL1, TL2, and TL3. Thus, source lines SL1and SL2and trench lines TL1, TL2, and TL3are electrically connected to each other.

The gate terminals of memory cells210,220,230, and240are connected to word line WL1. The gate terminals of memory cells212,222,232, and242are connected to word line WL2. The gate terminals of memory cells214,224,234, and244are connected to word line WL3. The gate terminals of memory cells216,226,236, and246are connected to word line WL4.

Similar to sub-array100, a memory cell of sub-array200is selected and either programmed, read, or erased by applying the appropriate voltages to the gate, drain, and source terminals of the desired memory cell. The desired memory cell is selected or accessed by applying high voltages to the word line and to the bit line to which the respective gate and drain terminals of the desired memory cell are connected and by applying a low voltage to the remaining word lines and bit lines. For example, if it is desired to select or access memory cell234shown inFIG. 3, a high voltage is applied to word line WL3, a low voltage is applied to word lines WL1, WL2, and WL4, a low voltage is applied to bit lines BL1, BL2, and BL4, and a ground potential is applied to source lines SL1and SL2and to trench lines TL1, TL2, and TL3. In addition to selecting the desired memory cell, the voltages applied to the word lines, bit lines, and source lines either programs, reads, or erases the selected memory cell. For example, memory cell234is programmed by applying a voltage ranging from about 5 volts to about 15 volts to word line WL3, connecting source lines SL1and SL2and trench lines TL1, TL2, and TL3to ground, and applying a voltage to bit line BL3that is sufficiently higher than the voltage applied to source line SL1(i.e., the voltage applied to the source terminal of memory cell234) to cause electrons to become trapped in the floating gate of memory cell234.

Memory cell234is read by applying a control voltage to word line WL3that is greater than the threshold voltage of an unprogrammed or erased memory cell, but less than the threshold voltage of a programmed memory cell. In addition, a ground potential is connected to source line SL2and a voltage ranging from about one volt to about two volts is applied to bit line BL3. Because word line WL3is connected to the control gate of memory cell234, the voltage applied to word line WL3is also applied to the gate terminal of memory cell234. Likewise, the ground potential applied to source line SL2is also applied to the source terminal of memory cell234and the voltage applied to bit line BL3is also applied to the drain terminal of memory cell234.

Memory cell234can be erased by applying a relatively high voltage to source line SL2, i.e., the source terminal of memory cell234, while applying a voltage of ground potential to word line WL3, i.e., the gate terminal of memory cell234, and allowing the bit line BL3, i.e., the drain terminal of memory cell234, to float. The method for erasing memory cell234is not a limitation of the present invention.

FIG. 4is an isometric view of memory cells110,112,120,122,130, and132of sub-array100ofFIG. 2. What is shown inFIG. 4is a semiconductor substrate300having a surface302and a plurality of trenches314extending from surface302into substrate300. A dielectric material321is formed in trench314and a trench line324is formed on dielectric material321. Polysilicon liners or inserts336and338are formed between each trench line324and its corresponding trench sidewall318. Gate structures370comprising gate dielectric material and a conductive material are formed on surface302. Source regions348and drain regions352are formed in semiconductor material300. Doped regions342and344are formed adjacent corresponding sidewalls318. Straps or connectors354connect doped regions342to drain regions352. The manufacture of memory cells110,112,120,122,130, and132shown inFIG. 4are further shown and described with reference toFIGS. 5–13.

Referring now toFIG. 5, a cross-sectional view of either memory cells110,120, and130ofFIG. 2taken along section line12—12ofFIG. 4or of memory cells112,122, and132ofFIG. 2taken along section line13—13ofFIG. 4is shown. It should be understood that the processing steps at the early stages of manufacture of memory cells102are the same for the source and drain regions. Thus, the cross-sectional view ofFIG. 5can represent a cross section taken along section line12—12or the cross section taken along section line13—13. What is shown inFIG. 5is semiconductor material300of P-type conductivity having a major surface302. By way of example, semiconductor material300has a concentration ranging from about 1×1014atoms per centimeter cubed (atoms/cm3) to about 2×1014atoms/cm3. Although semiconductor material300is described as being silicon, it should be understood this is not a limitation of the present invention. Other suitable materials for substrate300include, but are not limited to, silicon germanium, germanium, Silicon-On-Insulator (SOI), and the like. The semiconductor material may also be a compound semiconductor material such as, for example, gallium arsenide, indium phosphide, and the like. The conductivity type of semiconductor material300is not a limitation of the present invention. In accordance with the present embodiment, the conductivity type is chosen to form an n-channel insulated gate semiconductor device. However, the conductivity type can be selected to form a p-channel insulated gate semiconductor device or a complementary insulated gate semiconductor device.

A layer of dielectric material304is formed on major surface302. Preferably, dielectric layer304is oxide having a thickness ranging from about 50 Angstroms (Å) to about 250 Å. Oxide layer304can be either grown or deposited on semiconductor material300. By way of example, oxide layer304is grown using a furnace process. Layer304is also referred to as a pad oxide layer or a pad layer.

Still referring toFIG. 5, a hardmask306having a thickness ranging from about 100 Å to about 5,000 Å is formed on dielectric layer304. Preferably, hardmask306has a thickness ranging between about 500 Å and about 1,000 Å and comprises a single layer of a dielectric material such as, for example, silicon oxynitride (SiON), silicon nitride (SiN), silicon rich nitride (SiRN), silicon carbide (SiC), and hydrogenated oxidized silicon carbon material (SiCOH). It should be noted that hard mask306is not limited to being a single layer system, but can also be a multi-layer system. Hardmask306should comprise a material having a different etch rate or selectivity and a different thickness than oxide layer304.

A layer of photoresist308is formed on hardmask306. Photoresist layer308is patterned to form openings310using techniques known to those skilled in the art. The portions of hardmask306and dielectric layer304that are not protected by patterned photoresist layer308, i.e., the portions exposed by openings310, are etched using an anisotropic reactive ion etch to extend openings310and expose portions of surface302. Photoresist layer308is removed using techniques known to those skilled in the art.

Referring now toFIG. 6, the exposed portions of semiconductor material300are anisotropically etched to form trenches314having floors316and sidewalls318. The etch chemistry is selected so that sidewalls318form an angle α with surface302ranging from about 45 degrees to about 90 degrees. Preferably, the width (W) of trenches314ranges from about 500 Å to about 2,000 Å, the depth (D) of trenches314ranges from about 1,000 Å to about 5,000 Å, and the center-to-center distance (CD) between adjacent trenches ranges from about 500 Å to about 2,000 Å. Suitable techniques for forming trenches are known to those skilled in the art and may include, for example, Shallow Trench Isolation (STI) techniques.

Referring now toFIG. 7, a dielectric liner320is formed on floors316and sidewalls318of trenches314. By way of example, dielectric liner320is oxide having a thickness ranging from about 50 Å to about 300 Å. A polysilicon layer322of N-type conductivity is formed on dielectric liner320and hardmask306using, for example, a chemical vapor deposition technique. Preferably, polysilicon layer322has a concentration of N-type dopants of greater than about 1×1019atoms/cm3. Alternatively, polysilicon layer322may be doped with a dopant of P-type conductivity.

Referring now toFIG. 8, polysilicon layer322is planarized using, for example, a Chemical Mechanical Planarization (CMP) technique having a high selectivity to hardmask306. Hence, the planarization stops on hardmask306. Other suitable planarization techniques include electropolishing, electrochemical polishing, chemical polishing, and chemically enhanced polishing. After planarization, a layer of photoresist (not shown) is patterned on hardmask306to expose the portions of polysilicon layer322disposed in trenches314. The portions of polysilicon layer322disposed in trenches314are etched using, for example, a wet etchant to form trench lines324. By way of example, the wet etchant is dilute hydrofluoric acid (HF). Preferably, the thickness of trench lines324, indicated by arrows326, ranges from about 200 Å to about 2,500 Å.

A layer of dielectric material330is formed on trench lines324, oxide liner320, and hardmask306, and fills partially re-opened trenches314. By way of example, dielectric layer330is oxide formed by the decomposition of tetraethylorthosilicate (TEOS). Dielectric material330is planarized using, for example, a CMP technique having a high selectivity to hardmask306. Thus, the planarization stops on hardmask306.

Referring now toFIG. 9, hardmask306and the remaining portions of dielectric layer304are removed from major surface302using for example, a CMP technique. In addition, portions of dielectric material330are removed along with hardmask306, thereby forming a planarized structure. Then, after the word lines have been patterned (perpendicular to the trench lines), the remaining portions of dielectric layer330and the portions of dielectric liner320along sidewalls218are removed using, for example, an anisotropic reactive ion etch that preferentially etches oxide. Preferably, only the portion321of dielectric liner320between each floor316and each trench line324remains after the anisotropic reactive ion etch.

Referring now toFIG. 10, an undoped polysilicon layer334is formed on trench lines324, sidewalls318, and major surface302. By way of example, undoped polysilicon layer334is formed using a chemical vapor deposition technique and has a thickness ranging from about 75 Å to about 150 Å. It should be noted that undoped polysilicon layer334is also formed between each sidewall318and its associated trench line324.

Referring now toFIG. 11, undoped polysilicon layer334is anisotropically etched, leaving side regions or inserts336and338between sidewalls318and trench lines324. Alternatively, polysilicon layer334is oxidized leaving inserts336and338between sidewalls318and trench lines324. Because of the concentration gradient between trench lines324and side regions336and338and between side regions336and338and semiconductor substrate300, the dopant in trench lines324diffuses through side regions336and338and into semiconductor material300, thereby forming doped regions342and344, respectively. A layer of dielectric material346is formed on semiconductor substrate300, trench lines324, the exposed portions of sidewalls318, and on the exposed portions of side regions336and338. Preferably, the formation of doped regions342and344is facilitated by forming dielectric layer346at temperatures sufficiently high to cause the dopant in trench lines324to laterally diffuse through side regions336and338and into substrate300.

Referring now toFIG. 12, a layer of photoresist (not shown) is patterned on dielectric layer346to have openings overlying trench lines324and the portions of semiconductor substrate300in which source regions will be formed. It should be understood that beginning at the step indicated inFIG. 12, the regions of semiconductor substrate300indicated by section lines12—12and13—13inFIG. 4undergo different masking and doping steps from each other. In particular, the regions of semiconductor substrate300indicated by section line12—12become the source regions and the regions of semiconductor substrate300indicated by section line13—13become the drain regions. It should be further understood that the cross-sectional side view shown inFIG. 12represents the source regions of memory cells110,120, and130shown inFIG. 2. Accordingly,FIG. 12is a cross-sectional side view taken along the region indicated by section line12—12. A dopant of N-type conductivity is implanted into semiconductor substrate300and trench lines324to form source regions348and to further dope source lines324. The layer of photoresist is removed and another layer of photoresist (not shown) is patterned on dielectric layer346to have openings that expose the portions of dielectric layer346overlying and adjacent doped regions344. A dopant of N-type conductivity is implanted through the openings to form doped regions350, which serve as straps or connectors that connect doped regions344to corresponding source regions348. Preferably, straps350are formed using an angled or tilt angle implant. The layer of photoresist is removed.

Referring now toFIG. 13, a layer of photoresist (not shown) is patterned on dielectric layer346to have openings overlying trench lines324and the portions of semiconductor substrate300in which drain regions will be formed. It should be understood thatFIG. 13is a cross-sectional side view of the region of semiconductor substrate300taken along section line13—13ofFIG. 4. A dopant of N-type conductivity is implanted into semiconductor substrate300and trench lines324to form drain regions352and to further dope source lines324. The layer of photoresist is removed and another layer of photoresist (not shown) is patterned on dielectric layer346to have openings that expose the portions of dielectric layer346overlying and adjacent doped regions342. A dopant of N-type conductivity is implanted through the openings to form doped regions354, which serve as straps or connectors that connect doped regions342to corresponding drain regions352. Preferably, straps354are formed using an angled or tilt angle implant. The layer of photoresist is removed.

Referring now toFIG. 14, an alternative embodiment showing a cross-sectional side view of a portion of the source regions of memory cells202ofFIG. 3is illustrated. In memory cells202ofFIG. 3, straps350A are formed on each side of trench lines324. In other words, a strap350A connects doped regions342and source regions348and a strap350connects doped regions344and source regions348. It should be noted straps350A may be formed contemporaneously with straps350, hence the letter “A” has been appended to reference number350to distinguish the two straps.