Digital frequency detector and digital phase locked loop using the digital frequency detector

A digital frequency detector and a digital phase locked loop (PLL) are provided. The digital frequency detector includes a first conversion unit which outputs a first frequency as first frequency information of a digital type using a first ring oscillator that operates in a high-level period of the first frequency, a second conversion unit which outputs a second frequency as second frequency information of a digital type using a second ring oscillator that operates in a high-level period of the second frequency, and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority from Korean Patent Application No. 10-2007-0062354, filed on Jun. 25, 2007 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Apparatuses consistent with the present invention relate to a digital frequency detector and a digital phase locked loop (PLL) using the digital frequency detector. More particularly, apparatuses consistent with the present invention relate to a digital frequency detector for use in a digital PLL or a frequency synthesizer, and a digital PLL using the digital frequency detector.

2. Description of the Related Art

Generally, a PLL is used to obtain an output signal having a fixed phase and frequency by sensing and controlling the change of the phase and frequency that may occur in peripheral environments.

FIG. 1is a block diagram schematically illustrating the construction of a related PLL.

Referring toFIG. 1, a PLL comprises a phase frequency detector (PFD)10, a charge pump30, a loop filter50, a voltage controlled oscillator (VCO)70, and a divider90.

The PFD10compares an input frequency Fccwith a frequency output from the divider90to be described later, and outputs a pulse string corresponding to a difference between the two frequencies.

The charge pump30pushes or pulls current that is in proportion to a width of the pulse output from the PFD10in accordance with a pulse code. In the process of converting the pulse into the current as described above, a current gain is produced to exert a great influence upon the performance of the PLL including a lock time for which the output of the PLL is stabilized.

The loop filter50has a structure of a low pass filter, and filters noise generated during the operation of the loop. The loop filter50varies the voltage of a control terminal of the VCO70by changing the amount of charge accumulated using capacitors.

The VCO70outputs a specified frequency Fvco, which is a high frequency, in accordance with the voltage output from the loop filter50.

The divider90divides the output frequency Fvcoof the VCO70to output a frequency that comparable with the input frequency Fccprovided to the PFD10.

As described above, the PLL is a circuit that processes the frequency in an analog form, and an analog type circuit has a high sensitivity to external noise if the supply voltage is reduced. According to recent semiconductor processes, there is a growing tendency that a speed of a transistor is increased while a supply voltage is reduced, and due to this, circuits, which had been designed in an analog domain, are now being designed in a digital domain.

The tendency also appears in the field of PLLs. In implementing a digital PLL, the biggest problem is that the accuracy of the digital PLL is lowered in the case of converting the high frequency signal output from the VCO into a digital signal. The problem occurs not only in the digital PLL but also in a frequency synthesizer and the like, designed in the digital domain.

SUMMARY OF THE INVENTION

The present invention provides a digital frequency detector that can detect the frequency of a high frequency signal as a digital signal having a high precision to improve the performance of a digital circuit in designing a circuit, which had been designed in an analog domain, in a digital domain, and a digital PLL using the digital frequency detector.

According to an aspect of the present invention, there is provided a digital frequency detector, which comprises a first conversion unit which outputs a first frequency as first frequency information of a digital type using a first ring oscillator that operates in a high-level period of the first frequency; a second conversion unit which outputs a second frequency as second frequency information of a digital type using a second ring oscillator that operates in a high-level period of the second frequency; and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information.

The first frequency information and the second frequency information of the digital type may be information in which fractional frequency information and integer frequency information are added together.

The second frequency may be generated through a crystal, and may be a frequency the size of which can be known.

The first ring oscillator and the second ring oscillator may operate at the same frequency.

The first ring oscillator may either comprise a NAND gate and an even number of inverters as delay elements, or be implemented as a differential type oscillator.

The first conversion unit may comprise a first latch unit which temporarily stores states of signals passing through the respective delay elements at a falling edge of the first frequency, and outputs the state signal as delay information of the first ring oscillator, the first latch unit comprising latches the number of which corresponds to the number of delay elements provided in the first ring oscillator; a first edge detection unit which detects the delay element that makes the state of the delay information be changed from “1” to “0”; a first encoder unit which encodes the position of the delay element detected by the first edge detection unit to binary information, and outputs the encoded signal as fractional frequency information of the first ring oscillator; a first counter unit which counts a period of the first ring oscillator, and outputs counted value as integer frequency information; and a first addition unit which outputs the first frequency information obtained by adding the fractional frequency information to the integer frequency information.

The first counter unit may count a clock signal output from the first ring oscillator from a rising edge to the falling edge of the first frequency, and output the counted value as the integer frequency information.

The second conversion unit may comprise a second latch unit which temporarily stores states of signals passing through the respective delay elements at a falling edge of the second frequency, and outputs the state signal as delay information of the second ring oscillator, the second latch unit comprising latches the number of which corresponds to the number of delay elements provided in the second ring oscillator; a second edge detection unit which detects the delay element that makes the state of the delay information be changed from “1” to “0”; a second encoder unit which encodes the position of the delay element detected by the second edge detection unit to binary information, and outputs the encoded signal as fractional frequency information of the second ring oscillator; a second counter unit which counts a period of the second ring oscillator, and outputs the counted value as integer frequency information; and a second addition unit which outputs the second frequency information obtained by adding the fractional frequency information to the integer frequency information.

The second counter unit may count a clock signal output from the second ring oscillator from a rising edge to the falling edge of the second frequency, and output the counted value as the integer frequency information.

According to another aspect of the present invention, there is provided a digital frequency detector, which comprises a quantization unit which quantizes a first frequency and a second frequency using a ring oscillator; a first conversion unit which outputs the first frequency as first frequency information of a digital type using quantized information of the first frequency; a second conversion unit which outputs the second frequency as second frequency information of a digital type using quantized information of the second frequency; and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information.

The first frequency information and the second frequency information of the digital type may be information in which fractional frequency information and integer frequency information are added together.

The second frequency may be generated through a crystal, and may be a frequency the size of which can be known.

The ring oscillator may either comprise an odd number of inverters provided in a feedback loop as delay elements, or be implemented as a differential type oscillator.

The quantization unit may comprise a first latch unit which temporarily stores states of signals passing through the respective delay elements at a falling edge of the first frequency, and outputs the state signal as first delay information of the ring oscillator, the first latch unit comprising latches the number of which corresponds to the number of delay elements provided in the ring oscillator; a second latch unit which temporarily stores states of signals passing through respective delay elements at a falling edge of the second frequency, and outputs the state signal as second delay information of the ring oscillator, the second latch unit comprising latches the number of which corresponds to the number of delay elements provided in the ring oscillator; and a counter unit which outputs first integer phase information by counting a period of the ring oscillator for a period of the first frequency, and outputs second integer phase information by counting the period of the ring oscillator for a period of the second frequency.

The first conversion unit may comprise a first edge detection unit which detects the delay element that makes the state of the first delay information be changed from “1” to “0”; a first encoder unit which encodes the position of the delay element detected by the first edge detection unit to binary information, and outputs the encoded signal as first fractional phase information of the ring oscillator; a first addition unit which outputs first phase information obtained by adding the first fractional phase information to the first integer phase information; and a first differentiator which differentiates the first phase information and outputs the differentiated first phase information as the first frequency information.

The second conversion unit may comprise a second edge detection unit which detects the delay element that makes the state of the second delay information be changed from “1” to “0”; a second encoder unit which encodes the position of the delay element detected by the second edge detection unit to binary information, and outputs the encoded signal as second fractional phase information of the ring oscillator; a second addition unit which outputs second phase information obtained by adding the second fractional phase information to the second integer phase information; and a second differentiator which differentiates the second phase information and outputs the differentiated second phase information as the second frequency information.

The digital frequency detector according to embodiments of the present invention may further comprise a re-timer which rearranges the first frequency and the second frequency using a clock signal generated from the ring oscillator and provides the rearranged frequencies as clock signals of the first conversion unit and the second conversion unit, respectively.

The re-timer may comprise a first latch which latches the first frequency according to the clock signal generated from the ring oscillator; and a second latch which latches the second frequency according to the clock signal generated from the ring oscillator.

According to another aspect of the present invention, there is provided a digital phase locked loop (PLL), which comprises a detection unit which compares a first digital frequency with a second digital frequency and outputs an error value corresponding to a difference between the first and second digital frequencies; a filter unit which adjusts and outputs a control value for controlling an output frequency according to the error value output from the detection unit so that the error value is included within a predetermined permitted limit; an oscillator which outputs a high-frequency oscillation frequency by controlling a fixed frequency input from a fixed frequency oscillator according to the control value output from the filter unit; and a digital frequency detector which outputs a second digital frequency using a ratio of digital-type frequency information of the oscillation frequency to digital-type frequency information of a reference frequency the size of which is known.

The digital PLL according to embodiments of the present invention may further comprise a divider which divides the high-frequency oscillation frequency output from the oscillator by a specified integer and outputting the divided frequency as a low-frequency oscillation frequency; and a multiplier which multiplies the second digital frequency output from the digital frequency detector by the integer and outputs the multiplied frequency as the second high-frequency digital frequency.

The digital frequency detector may comprise a first conversion unit which outputs a first frequency as first frequency information of a digital type using a first ring oscillator that operates in a high-level period of the first frequency; a second conversion unit which outputs a second frequency as second frequency information of a digital type using a second ring oscillator that operates in a high-level period of the second frequency; and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information.

Alternatively, the digital frequency detector may comprise a quantization unit which quantizes a first frequency and a second frequency using a ring oscillator; a first conversion unit which outputs the first frequency as first frequency information of a digital type using quantized information of the first frequency; a second conversion unit which outputs the second frequency as second frequency information of a digital type using quantized information of the second frequency; and an operation unit which outputs a digital frequency for the first frequency by calculating a ratio of the first frequency information to the second frequency information.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 2is a block diagram schematically illustrating the construction of a digital frequency detector according to an exemplary embodiment of the present invention.

Referring toFIG. 2, the digital frequency detector100according to an exemplary embodiment of the present invention comprises a first conversion unit120, a second conversion unit140, and an operation unit160.

The first conversion unit120converts an oscillation frequency Fvcointo a digital signal, and comprises a first latch unit121, a first ring oscillator122, a first edge detection unit123, a first counter unit124, a first encoder unit125, and a first addition unit126.

The first ring oscillator122comprises a plurality of delay elements connected to a feedback loop, and generates a clock signal of a predetermined frequency. The first ring oscillator122operates when the oscillation frequency Fvcois at a high level and does not operate when the oscillation frequency Fvcois at a low level.

The first latch unit121comprises a plurality of latches, the number of which corresponds to the number of delay elements provided in the first ring oscillator122. The first latch unit214temporarily stores states of signals passing through the respective delay elements at a falling edge of the oscillation frequency Fvco, and outputs the state signal as first delay information of the first ring oscillator122.

The first edge detection unit123detects the delay element that makes a state of the first delay information output from the first latch unit121be changed from “1” to “0”.

The first encoder unit125encodes a position of the delay element detected by the first edge detection unit132into binary information, and outputs the encoded signal as first fractional frequency information of the first ring oscillator122.

The first counter unit124counts a period of the first ring oscillator122, and outputs counter information. That is, the counter unit124counts the clock signal output from the first ring oscillator122from a rising edge to a falling edge of the oscillation frequency Fvco, and outputs first integer frequency information.

The first addition unit126outputs the first frequency information obtained by adding the first fractional frequency information output from the first encoder unit125to the first integer frequency information output from the first counter unit124.

The second conversion unit140converts a reference frequency Frefinto a digital signal, and comprises a second latch unit141, a second ring oscillator142, a second edge detection unit143, a second counter unit144, a second encoder unit145, and a second addition unit146. Here, the reference frequency Frefis generated through a crystal, and is a frequency the size of which can be known.

The second ring oscillator142comprises a plurality of delay elements connected to a feedback loop, and generates a clock signal having the same frequency as the first ring oscillator122. The second ring oscillator142operates when the reference frequency Frefis at a high level and does not operate when the reference frequency Frefis at a low level.

The second latch unit141comprises a plurality of latches, the number of which corresponds to the number of delay elements provided in the second ring oscillator142. The second latch unit141temporarily stores states of signals passing through the respective delay elements at a falling edge of the reference frequency Fref, and outputs the state signal as second delay information of the second ring oscillator124.

The second edge detection unit143detects the delay element that makes a state of the second delay information output from the second latch unit141be changed from “1” to “0”.

The second encoder unit145encodes a position of the delay element detected by the second edge detection unit143into binary information, and outputs the encoded signal as second fractional frequency information of the second ring oscillator142.

The second counter unit144counts a period of the second ring oscillator142, and outputs counter information. That is, the counter unit144counts a clock signal output from the second ring oscillator142from a rising edge to a falling edge of the reference frequency Fref, and outputs the counted signal as the second integer frequency information.

The second addition unit146outputs the second frequency information obtained by adding the second fractional frequency information output from the second encoder unit145to the second integer frequency information output from the second counter unit144.

The operation unit160outputs a digital frequency Fdigby calculating a ratio of the frequencies output from the first conversion unit120and the second conversion unit140. That is, if it is assumed that the first frequency information output from the first conversion unit120is “a” and the second frequency information output from the second conversion unit140is “b”, the operation unit160outputs b/a=Fvco/fref=Fdig. Here, since the reference signal Frefis generated through crystal and is a frequency the size of which can be known, the digital frequency Fdigcorresponds to the value obtained by converting the input oscillation frequency Fvcointo a digital signal.

FIG. 3is a block diagram illustrating in detail the construction of the first conversion unit120of the digital frequency detector according to an exemplary embodiment of the present invention, andFIG. 4is a timing diagram explaining the operation of the first conversion unit120illustrated inFIG. 3.

InFIG. 3, the first ring oscillator122comprises a NAND gate (“0”) and 10 inverters (“1” to “10”) as delay elements. The first ring oscillator122connects the 10 inverters to an output terminal of the NAND gate, and an output signal of the first ring oscillator122is fed back to an input terminal of the NAND gate. Through this construction, the first ring oscillator122operates if the oscillation frequency Fvcois at a high level and does not operate if the oscillation frequency Fvcois at a low level.

Alternatively, the first ring oscillator122may be of a differential type in which a NAND gate and inverters are combined.

Also, the reference numerals “0” to “10” given to the respective delay elements of the first ring oscillator122are used to obtain fractional phase information by encoding the delay information to binary information. In this case, the first latch unit121comprises 11 latches, the number of which corresponds to the number of delay elements of the first ring oscillator122.

The first counter unit124comprises a counter CNT for counting the clock signal output from the first ring oscillator122from the rising edge to the falling edge of the oscillation frequency Fvco, and a latch for temporarily storing a counted value.

Referring toFIG. 4, the first counter unit124counts the clock signal output from the first ring oscillator122from the rising edge Tsrtto the falling edge Tedgof the oscillation frequency Fvco, and outputs a counted value “6”. Then, the first latch unit121temporarily stores states of respective nodes a, b, c, . . . , and k, and outputs “00001111100” that is the first delay information.

The first edge detection unit123detects the delay element number9, which makes the state of the signal output from the first latch unit121be changed from “1” to “0”, from “00001111100”. Here, the first encoder unit divides the total number of inverters provided in the first ring oscillator122“11” by a numeral “9”, and outputs the result, i.e., 9/11=0.8181, as the first fractional frequency information.

The first addition unit126adds “6”, that is the first integer frequency information output from the first counter unit124, to “0.8181”, that is the first fractional frequency information output from the first encoder unit125, and outputs “6.8181” that is the first frequency information.

Since the detailed construction and operation of the second conversion unit140are the same as those of the first conversion unit120as described above with reference toFIGS. 3 and 4, the detailed description thereof will be omitted.

As described above, the digital frequency detector100can detect the oscillation frequency Fvcoin the rate of the reference frequency Fref, the size of which is known, using the ring oscillators122and142that operate at the same frequency.

FIG. 5is a block diagram schematically illustrating the construction of the digital frequency detector according to another exemplary embodiment of the present invention.

The digital frequency detector according to another exemplary embodiment of the present invention comprises a quantization unit210, a first conversion unit230, a second conversion unit250, an operation unit270, and a re-timer290.

The quantization unit210quantizes an oscillation frequency Fvcoand a reference frequency Fref, and outputs quantized frequencies. The quantization unit210comprises a ring oscillator212, a first latch unit214, a second latch unit216, and a counter unit218. Here, the reference frequency Fref is generated through crystal, and is a frequency the size of which can be known.

The ring oscillator212comprises an odd number of delay elements connected to a feedback loop, and generates a clock signal of a predetermined frequency.

The first latch unit214comprises a plurality of latches, the number of which corresponds to the number of delay elements provided in the ring oscillator212. The first latch unit214temporarily stores states of signals passing through the respective delay elements at a rising edge of the oscillation frequency Fvco, and outputs the state signal as first delay information of the ring oscillator212.

The second latch unit216also comprises latches the number of which corresponds to the number of delay elements provided in the ring oscillator212. The second latch unit216temporarily stores states of signals passing through the respective delay elements at a rising edge of the reference frequency Fref, and outputs the state signal as second delay information of the ring oscillator212.

The counter unit218counts a period of the ring oscillator212, and outputs counter information. That is, the counter unit218counts the clock signal output from the ring oscillator212for a period of the oscillation frequency Fvco, and outputs first integer phase information. Also, the counter unit218counts the clock signal output from the ring oscillator212for a period of the reference frequency Fref, and outputs second integer phase information.

The first conversion unit230converts the first delay information output from the first latch unit214and the first integer phase information output from the counter unit218into a first digital frequency, and outputs the first digital frequency. The first conversion unit230comprises a first edge detection unit232, a first encoder unit234, a first addition unit236, and a first differentiator238.

The first edge detection unit232detects the delay element that makes a state of the first delay information output from the first latch unit214be changed from “1” to “0”.

The first encoder unit234encodes a position of the delay element detected by the first edge detection unit232into binary information, and outputs the encoded signal as first fractional phase information of the ring oscillator212.

The first addition unit226outputs the first phase information obtained by adding the first fractional phase information output from the first encoder unit234to the first integer phase information output from the counter unit218.

The first differentiator238differentiates the first phase information in accordance with a first re-timing clock signal rFvcoprovided from the re-timer290to be described later, and outputs the first digital frequency.

The second conversion unit250converts the second delay information output from the second latch unit216and the second integer phase information output from the counter unit218into a second digital frequency, and outputs the second digital frequency. The second conversion unit250comprises a second edge detection unit252, a second encoder unit254, a second addition unit256, and a second differentiator258.

The second edge detection unit252detects the delay element that makes the state of the second delay information output from the second latch unit216be changed from “1” to “0”.

The second encoder unit254encodes a position of the delay element detected by the second edge detection unit252into binary information, and outputs the encoded signal as second fractional phase information of the ring oscillator212.

The second addition unit256outputs the second phase information obtained by adding the second fractional phase information output from the second encoder unit254to the second integer phase information output from the counter unit218.

The second differentiator258differentiates the second phase information in accordance with a second re-timing clock signal rFrefprovided from the re-timer290to be described later, and outputs the second digital frequency.

The operation unit270outputs a digital frequency Fdigby calculating a ratio of the first digital frequency output from the first conversion unit230to the second digital frequency output from the second conversion unit250.

The re-timer290rearranges the oscillation frequency Fvcoand the reference frequency Frefusing the clock signal generated from the ring oscillator212, and outputs the rearrange frequencies to the first differentiator238and the second differentiator258as the first re-timing clock rFvcoand the second re-timing clock rFref.

FIGS. 6 to 9are views explaining in detail the operation of the digital frequency detector200according to another exemplary embodiment of the present invention.

FIG. 6is an exemplary view illustrating in detail the construction of a quantization unit210of the digital frequency detector200according to another exemplary embodiment of the present invention, andFIG. 7is a view illustrating the construction of a ring oscillator212used in the quantization unit210illustrated inFIG. 6.FIG. 8is a timing diagram explaining the operation of the digital frequency detector200according to another exemplary embodiment of the present invention, andFIG. 9is a view explaining the operation of conversion units230and250of the digital frequency detector200according to another exemplary embodiment of the present invention.

Referring toFIG. 6, the quantization unit210comprises the ring oscillator212provided with nine delay elements connected to the feedback loop, the first latch unit214having nine latches, and the second latch unit216having nine latches.

Here, nine delay elements may comprise inverters, and the respective inverters invert their input signals, respectively. That is, inverter1inverts a signal at node a, and outputs an inverted signal to node b. Inverter2inverts the signal at node b, and outputs an inverted signal to node c. Inverters0and3to8operate in the same manner as inverters1and2, and thus the ring oscillator212generates a clock signal of a predetermined frequency.

Although not illustrated in the drawing, the ring oscillator212may be of a differential type in which a NAND gate and inverters are combined.

The number of the latches of the first latch unit214and the second latch unit216is the same as the number of inverters of the ring oscillator212. As illustrated inFIG. 6, the first and second latch units temporarily store states of signals detected at nodes a to i, and output the state signals to the first conversion unit230and the second conversion unit250.

As illustrated inFIG. 7, the delay information output from the first latch unit214and the second latch unit216may be the phase information of the ring oscillator212, and the numerals “0” to “8” given to the respective delay elements are used to obtain fractional phase information by encoding the delay information to binary information. A method of obtaining the fractional phase information will be described with reference toFIG. 8.

As illustrated inFIG. 8, nine latches that constitute the first latch unit214temporarily store states of signals detected at nodes a to i at the first rising edge TV1of the oscillation frequency Fvcoand output “011110000”. Here, the first edge detection unit232detects inverter4that makes the signal state at the first rising edge TV1be changed from “1” to “0”. Also, the first encoder unit234divides the numeral “4” by “9” that is the total number of inverters provided in the ring oscillator212, and outputs “4/9=0.444” as the first fractional phase information.

The nine latches that constitute the second latch unit216temporarily store states of signals detected at nodes a to i at the first rising edge TR1of the reference frequency Fref, and output “100001111”. Here, the second edge detection unit252detects inverter0that makes the signal state at the first rising edge TRI be changed from “1” to “0”. Also, the second encoder unit254outputs “0/9=0” as the second fractional phase information.

The counter CNT counts the number of clocks output from the ring oscillator212, and an oscillation latch Dvconnected to the counter CNT temporarily stores the number of clocks output from the ring oscillator212at the first rising edge TV1to output the number of clocks temporarily stored as the first integer phase information. A reference latch Drconnected to the counter CNT temporarily stores the number of clocks output from the ring oscillator212at the first rising edge TR1to output the number of clocks temporarily stored as the second integer phase information.

Referring toFIGS. 8 and 9, the digital frequency of the oscillation frequency Fvcois the value obtained by dividing the frequency of the ring oscillator212by the oscillation frequency Fvcoas in Equation (1).
freq(n)=F(RingOSC)/Fvco=CNT(n)−CNT(n−1)−1+fr(n)+1−fr(n−1)  (1)

In Equation (1), freq(n) denotes a digital frequency detected at the n-th rising edge TVn, CNT(n) the first integer phase information output at the n-th rising edge TVn, CNT(n−1) the first integer phase information output at the (n−1)-th rising edge TVn−1, fr(n) the first fractional phase information output at the n-th rising edge TVn, and fr(n−1) the first fractional phase information output at the (n−1)-th rising edge TVn−1, respectively.

Consequently, it can be known that the digital frequency becomes freq(n)={CNT(n)−CNT(n−1)}+(fr(n)−fr(n−1)}. The digital frequency of the reference frequency Frefcan be obtained in the same manner as the obtaining of the oscillation frequency Fvco.

Accordingly, with reference to the timing diagram ofFIG. 8, the fractional phase information fr output from the first encoder unit234at the first to third rising edges TV1to TV3is given in Equation (2)
fr(TV1)=4/9=0.444;fr(TV2)=0/9=0;fr(TV3)=4/9=0.444;fr(TV4)=0/9=0  (2)

With reference to Equation (1) and Equation (2), as a result of calculating the digital frequency, the first digital frequencydFVCOas given in Equation (3) is output from the first conversion unit230.
dFVCO(TV2−TV1)=CNT(TV2)−CNT(TV1)+fr(TV2)−fr(TV1)=5−0.444=4.555
dFVCO(TV3−TV2)=CNT(TV3)−CNT(TV2)+fr(TV3)−fr(TV2)=4+0.444=4.444  (3)
dFVCO(TV4−TV3)=CNT(TV4)−CNT(TV3)+fr(TV4)=fr(TV3)=5−0.444=4.555

In the same manner, the fractional phase information fr output from the second encoder unit254at the first to third rising edges TR1to TR3is given in Equation (4).
fr(TR1)=0/9=0;fr(TR2)=1/9=0.111;fr(TR3)=2/9=0.222  (4)

With reference to Equation (1) and Equation (4), as a result of calculating the digital frequency, the second digital frequency dFrefas given in Equation (5) is output from the first conversion unit230.
dFref(TR2−TR1)=CNT(TR2)−CNT(TR1)+fr(TR2)−fr(TR1)=6+0.111=6.111
dFref(TV3−TV2)=CNT(TV3)−CNT(TV2)+fr(TV3)−fr(TV2)=6+0.111=6.111

Lastly, the operation unit270operates the ratio of the first digital frequency Fvcooutput from the first conversion unit230to the second digital frequency Frefoutput from the second conversion unit250, and outputs the digital frequency Fdigobtained as a result of operation. The digital frequency Fdigfinally output is operated in Equation (6).
Fdig=dFref/dFVCO=6.111/4.555=1.3416 or 6.111/4.111=1.3751  (6)

FIG. 10is a view illustrating the construction of a re-timer290of the digital frequency detector according to another exemplary embodiment of the present invention.

Referring toFIG. 10, the re-timer290comprises two latches. Each latch rearranges the oscillation frequency FVCOand the second frequency Frefusing the clock signal Ring OSC generated from the ring oscillator212, and provides the rearranged frequencies as the first re-timing clock signal rFVCOand the second re-timing clock signal rFref.

FIG. 11is a block diagram schematically illustrating the construction of a digital PLL to which the digital frequency detector according to embodiments of the present invention is applied.

Referring toFIG. 11, the digital PLL comprises a detector310, a digital loop filter (DLF)320, a digital controlled oscillator (DCO)330, a divider (1/N)340, a digital frequency detector (DFD)350, and a multiplier (N)360.

The detector310compares an input frequency Fccwith the frequency Fdigoutput from the multiplier360to be described later, and outputs an error value corresponding to a difference between the two frequencies.

The DLF320adjusts a control value for controlling the oscillation frequency FVCOthat is output when the error value output from the detector310exceeds the permitted limit of the digital PLL according to the error value.

The DCO330outputs the high-frequency oscillation frequency FVCOby controlling the fixed frequency input from a fixed frequency oscillator (not illustrated) according to the control value output from the DLF320.

The divider340divides the high-frequency oscillation frequency FVCOoutput from the VCO330by a specified integer value N, and outputs the divided frequency as the low-frequency oscillation frequency FVCO.

The DFD350converts the ratio of the low-frequency oscillation frequency FVCOto the reference frequency Frefinto a digital value, and outputs the digital value as the digital frequency Fdig. The digital frequency detectors100and200according to embodiments of the present invention may be applied as the DFD350.

The multiplier360multiplies the digital frequency Fdigoutput from the DFD350by the integer value N, and outputs the multiplied frequency as the high-frequency digital frequency Fdig.

In the exemplary embodiments of the present invention as described above, the digital PLL can be implemented by employing the digital frequency detectors100and200that convert the ratio of two frequencies into a digital value. The digital frequency detector according to the present invention can also be applied to a frequency synthesizer designed in a digital domain.

As described above, according to the exemplary embodiments of the present invention, the frequency of a high-frequency signal is detected as a digital signal having a high precision using a ring oscillator, and thus a high-performance digital frequency detector can be provided in designing a circuit, which had been designed in an analog domain, in a digital domain.