SUBSTRATE(S) FOR AN INTEGRATED CIRCUIT (IC) PACKAGE EMPLOYING A CORE LAYER AND AN ADJACENT INSULATION LAYER(S) WITH AN EMBEDDED METAL STRUCTURE(S) POSITIONED FROM THE CORE LAYER

A substrate includes a core layer and one or more metallization layers. The core layer provides stabilization to the substrate to reduce or avoid warpage. The core layer may include a glass material weaved throughout the core to provide stabilization and avoid warpage. A metallization layer adjacent to the core layer in the substate includes an insulation layer and the embedded metal structure(s) that is positioned from the core layer. The thickness of the insulation layer is greater than the embedded metal structure so that a surface of the embedded metal structure is positioned at least at a length from the surface of the glass material. This can avoid or reduce the risk of the embedded metal structure electrically shorting to another metal structure in the substrate through the core layer.

BACKGROUND

I. Field of the Disclosure

The field of the disclosure relates to integrated circuit (IC) packages, and more particularly to design and manufacture of a substrate within an IC package to improve circuit reliability due to substrate thinning requirements.

Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in an IC package, also called a “semiconductor package” or “chip package.” The IC package includes one or more semiconductor dice (“dies” or “dice”) as an IC(s) that are mounted on and electrically coupled to a package substrate to provide physical support and an electrical interface to the die(s). The package substrate includes one or more metallization layers that include respective metal layers with metal interconnects (e.g., metal traces, metal lines) with vias coupling the metal interconnects together between adjacent metallization layers to provide electrical interfaces between the die(s). The die(s) is electrically interfaced to metal interconnects exposed in a top or outer metallization layer of the package substrate to electrically couple the die(s) to the metal interconnects of the package substrate. For example, the package substrate may include a laminate substrate or an embedded trace substrate (ETS) layer adjacent to and electrically coupled to a die to provide signal routing paths to the die. Metal interconnects in the outer metallization layer of the package substrate are coupled to other metal interconnects in other, lower metallization layers in the package substrate to provide signal routing paths to a coupled die. The term “adjacent” as used herein means spatially next to but not necessarily adjoining something as shown in the Figures unless specifically stated otherwise.

Some IC packages are known as “hybrid” IC packages, which include multiple die packages with respective dies for different purposes or applications. For example, a hybrid IC package may be an application die, such as a communications modem or processor (including a system). The hybrid IC package could also include, for example, one or more memory dies to provide memory to support data storage and access by the application die. Multiple dies could be disposed in a single die layer and disposed adjacent to each other in a horizontal direction on a package substrate in the IC package. The multiple dies could also be provided in their own respective die packages that are stacked on top of each other in a three-dimensional (3D) arrangement as an overall 3DIC package. A die in a die layer is typically encased in an epoxy molding compound (EMC) to protect the die. 3DIC packages may be desired to reduce the cross-sectional area of the package.

In a 3DIC package, a first, bottom die directly supported on a package substrate is electrically coupled through die interconnects to metallization layers of the package substrate. Metal interconnects (e.g., metal traces, metal lines) in the metallization layers of the package substrate provide signal routing paths to the bottom die. Other stacked dies that are not directly adjacent to the package substrate in the 3DIC package can be electrically coupled to the package substrate by wire bonds and/or an interposer substrate to provide die-to-die (D2D) connections between the multiple stacked dies. An interposer substrate is adjacent to and electrically coupled to a second, top die to provide signal routing paths between the top die and the package substrate for external and/or D2D connections. Similar to a package substrate, an interposer substrate includes one or more metallization layers each with a respective metal layer that includes metal interconnects (e.g., metal traces, metal lines) with vias coupling the metal interconnects together between adjacent metallization layers to provide signal routing paths between the multiple stacked dies through the package substrate. The top die routes electrical signals to metal interconnects exposed in a top, outer metallization layer of the interposer substrate to electrically couple the bottom die through the metal interconnects of the bottom, lower metallization layer of the interposer substrate, and vertical die interconnects and metal interconnects in the package substrate to provide signal routing paths to the bottom die.

SUMMARY

Aspects disclosed in the detailed description include a substrate for an integrated circuit (IC) package employing a core layer and an adjacent insulation layer with an embedded metal structure(s) positioned from the core layer to avoid electron migration. The substrate includes a core layer and one or more metallization layers. The core layer provides stabilization to the substrate to reduce or avoid warpage. For example, the core layer may include a glass material weaved throughout the core to provide stabilization to the core layer and avoid warpage. In exemplary aspects disclosed herein, a metallization layer adjacent to the core layer in the substate includes an insulation layer and the embedded metal structure(s) that is positioned from the core layer. The thickness of the insulation layer is greater than the embedded metal structure so that a surface of the embedded metal structure is positioned at least at a length (l) from the surface of the glass material. This can avoid or reduce the risk of the embedded metal structure electrically shorting to another metal structure in the substrate through the core layer.

Additionally, in other exemplary aspects, in reducing the thickness of the core layer to meet today's overall package height requirements, shorter vias are formed through the core layer of the substrate to couple the embedded metal structure. The vias provide a pass through electrical connection through the core layer to adjacent metallization layers. To advantageously achieve a reliable via connection of the resulting shorter via, the embedded metal structure in the metallization layer can include two stacked metal structures forming a post. The post enables a drilled via (which may be formed by a drilling and metal fill process) to terminate within the two stacked metal structures and provide greater surface area connecting the inside of the two stacked metal structures and the via.

In this regard, in one exemplary aspect, a substrate is disclosed. The substrate comprises a first core layer extending in a first direction. The first core layer comprises a glass material, a first surface, and a second surface opposite the first surface in a second direction orthogonal to the first direction. The substrate also comprises a first metallization layer adjacent to the first surface. The first metallization layer comprises a first insulation layer and a first metal structure embedded in the first insulation layer, the first metal structure having a third surface, the third surface positioned at least a length (l) in the second direction from the first surface of the first core layer to prevent electron migration through the glass material.

In another exemplary aspect, a method for fabricating a substrate is disclosed. The method comprises forming a first core layer extending in a first direction. The first core layer comprises a glass material, a first surface, and a second surface opposite the first surface in a second direction orthogonal to the first direction. The method further comprises forming a first metallization layer adjacent to the first surface. The first metallization layer comprises a first insulation layer and a first metal structure embedded in the first insulation layer. The method further comprises coupling the first metallization layer to the first core layer wherein the first metal structure has a third surface, the third surface positioned at least a length (l) in the second direction from the first surface of the first core layer to prevent electron migration through the glass material.

DETAILED DESCRIPTION

Aspects disclosed in the detailed description include a substrate for an integrated circuit (IC) package employing a core layer and an adjacent insulation layer with an embedded metal structure(s) positioned from the core layer to avoid electron migration. The substrate includes a core layer and one or more metallization layers. The core layer provides stabilization to the substrate to reduce or avoid warpage. For example, the core layer may include a glass material weaved throughout the core to provide stabilization to the core layer and avoid warpage. In exemplary aspects disclosed herein, a metallization layer adjacent to the core layer in the substate includes an insulation layer and the embedded metal structure(s) that is positioned from the core layer. The thickness of the insulation layer is greater than the embedded metal structure so that a surface of the embedded metal structure is positioned at least at a length (l) from the surface of the glass material. This can avoid or reduce the risk of the embedded metal structure electrically shorting to another metal structure in the substrate through the core layer.

Additionally, in other exemplary aspects, in reducing the thickness of the core layer to meet today's overall package height requirements, shorter vias are formed through the core layer of the substrate to couple the embedded metal structure. The vias provide a pass through electrical connection through the core layer to adjacent metallization layers. To advantageously achieve a reliable via connection of the resulting shorter via, the embedded metal structure in the metallization layer can include two stacked metal structures forming a post. The post enables a drilled via (which may be formed by a drilling and metal fill process) to terminate within the two stacked metal structures and provide greater surface area connecting the inside of the two stacked metal structures and the via.

In this regard,FIG.1is a side view of an exemplary IC package100, which in this example is a three-dimensional (3D) IC (3DIC) package100. The IC package100includes a package substrate102and an interposer substrate104. The package substrate102and the interposer substrate104commonly route signals and power and, for convenience, may both be referred to simply as a substrate106. The substrate106employs a core layer and an adjacent insulation layer with an embedded metal structure(s) positioned from the core layer to avoid electron migration. Exemplary embodiments of the substrate106will be discussed in more detail in connection with the description ofFIGS.2-5below.

In this example, the IC package100includes first and second dies110(1),110(2) that are included in respective first and second die packages112(1),112(2) that are stacked on top of each other in the vertical direction (Z-axis direction). The first die package112(1) of the IC package100includes the first die110(1) coupled to the package substrate102. In this example, the package substrate102includes a first, upper metallization layer114disposed on a core layer108. The core layer108is a central layer of a substrate that provides mechanical strength to the IC package100. The core layer108is typically made of a strong dielectric material such as glass. The core layer108is disposed on a second, bottom metallization layer116. The first, upper metallization layer114provides an electrical interface for signal routing to the first die110(1). The first die110(1) is coupled to die interconnects118(e.g., raised metal bumps) that are electrically coupled to metal interconnects120in the first, upper metallization layer114. The metal interconnects120in the first, upper metallization layer114are coupled to metal vias122(not visible) in the core layer108, which are coupled to metal interconnects124in the second, bottom metallization layer116. In this manner, the package substrate102provides interconnections between its first and second metallization layers114,116, and core layer108to provide signal routing to the first die110(1). External interconnects126(e.g., ball grid array (BGA) interconnects) are coupled to the metal interconnects124in the second, bottom metallization layer116to provide interconnections through the package substrate102to the first die110(1) through the die interconnects118. In this example, a first, active side128(1) of the first die110(1) is adjacent to and coupled to the package substrate102, and more specifically the first, upper metallization layer114of the package substrate102.

In the exemplary IC package100inFIG.1, an additional optional second die package112(2) is provided and coupled to the first die package112(1) to support multiple dies. For example, the first die110(1) in the first die package112(1) may include an application processor, and the second die110(2) may be a memory die, such as a dynamic random access memory (DRAM) die that provides memory support for the application processor. In this regard, in this example, the first die package112(1) also includes the interposer substrate104that is disposed on a package mold130encasing the first die110(1), adjacent to a second, inactive side128(2) of the first die110(1). The interposer substrate104also includes a core layer108and one or more metallization layers132that each include metal interconnects134to provide interconnections to the second die110(2) in the second die package112(2). The second die package112(2) is physically and electrically coupled to the first die package112(1) by being coupled through external interconnects136(e.g., solder bumps, BGA interconnects) to the interposer substrate104. The external interconnects136are coupled to the metal interconnects134in the interposer substrate104through metal vias138(not visible). The first die package112(1) includes vertical interconnects140to couple the second die110(2) to the external interconnects126and to first die110(1) through the package substrate102.

FIG.2is a side view of a first exemplary embodiment of a substrate106,200employing a core layer108and an adjacent insulation layer202with embedded metal structures204A,204B positioned from the core layer108to avoid electron migration wherein the embedded metal structures204A,204B are composed of a single metal layer206. The embedded metal structures204A,204B are positioned at least a length, l, from the core layer108. The length, l, is at least two micrometers (2 μm). The core layer108extends in a first, horizontal direction (X-axis direction) and comprises a glass material208weaved in the core layer108. The core layer108includes a first surface210and a second surface212opposite the first surface210in a second, vertical direction (Z-axis) orthogonal to the first direction (X-axis). The first, upper metallization layer114is adjacent to the first surface210and comprises the insulation layer202and the metal structures204A,204B embedded in the insulation layer202. Insulation layer213is above metallization layer114in the Z-direction. The metal structures204A,204B have a third surface214positioned at least the length (l) in the second, vertical direction (Z-axis) from the first surface210of the core layer108. A lower insulation layer216is adjacent to the second surface212of the core layer108in the second, vertical direction (Z-axis). The insulation layer202and the lower insulation layer216have a coefficient of thermal expansion (CTE) that substantially matches the CTE of the core layer108. The insulation layer202and the lower insulation layer216have a dielectric constant (κil) that substantially matches the dielectric constant (κcl) of the core layer108. Alternative examples of the insulation layer202and/or the lower insulation layer216may include a resin material including, but not limited to, resin coated Cu foil (RCC), a photo imageable dielectric (PID), and an Ajinomoto Build-up Film® (ABF). For example, the core layer108may include a resin material with a glass material weaved in the resin material such as Samsung® GHPL-830NS prepreg material which has a dielectric constant (κcl) of 3.9 and a CTE of 14 and can be matched with RCC, such as Sumitomo® LaZ 7752 which has a dielectric constant (κil) of 4 and a CTE of 14. During the fabrication processes which will be described in connection withFIGS.7A-7C and9A-9D, the core layer108may be referred to as prepreg material (PPG).

A metallization layer218is adjacent to the lower insulation layer216in the second, vertical direction (Z-axis). The metallization layer218includes metal structures220A and220B and an insulation material222. Metal vias224A,224B connect the metal structures220A,220B to the metal structures204A,204B, respectively. The thickness (t) of the lower insulation layer216prevents electron migration from the metal structures220A.220B through the core layer108. The thickness (t) of the insulation layer216is preferably at least 20 μm and the thickness of metal structures220A,220B are generally 14 μm. As mentioned above, the length (l) from the first surface210of the core layer108and the third surface214of the metal structures204A,204B prevents electron migration between metal structures in the metallization layer114through the core layer108. In other words, metal structures in the metallization layer114will not be electrically shorted through the core layer108.

FIG.3is a side view of another exemplary embodiment of a substrate106,300employing a core layer108and an adjacent insulation layer302with embedded metal structures304A,304B positioned from the core layer108to avoid electron migration wherein the embedded metal structures304A,304B are composed of at least two metal layers, metal layer306and metal layer308, forming a post310. Common elements between the substrate300inFIG.3and elements of the substrate200inFIG.2are shown with common element numbers. The upper metallization layer114is adjacent to the first surface210and comprises the insulation layer302and the metal structures304A,304B embedded in the insulation layer302. The metal structures304A,304B have a third surface214positioned at least a length (l) in the second, vertical direction (Z-axis) from the first surface210of the core layer108. The insulation layer302and the lower insulation layer216have a CTE that substantially matches the CTE of the core layer108. The insulation layer302and the lower insulation layer216have a dielectric constant (κil) that substantially matches the dielectric constant (κcl) of the core layer108. Alternative examples of the insulation layer302may include a resin material including, but not limited to, resin coated Cu foil (RCC), a photo imageable dielectric (PID), and an Ajinomoto Build-up Film® (ABF). Metal vias312A,312B connect the metal structures220A.220B to the metal structures304A,304B, respectively.

Utilizing the post310in this embodiment facilitates the vias312A,312B to be shorter than the vias224A,224B inFIG.2. However, without a separation of at least the length (l) as described herein between the third surface214of the post310and the first surface210of the core layer108, electron migration between metal structure304A and other metal structures through the core layer108would occur with higher probability than a single metal layer structure.

FIG.4is a side view of another exemplary embodiment of a substrate106, substrate400employing two core layers, core layer402A and core layer402B, wherein each core layer includes an adjacent insulation layer and an embedded metal structure positioned from its respective core layer to avoid electron migration wherein the embedded metal structures are composed of a single metal layer. The core layers402A,402B, like the core layer108, are adjacent to metallization layers404A,404B, respectively.

The core layers402A,402B extend in a first, horizontal direction (X-axis direction) and comprise a glass material208in the core layers402A and402B. The core layer402A includes a first surface406and a second surface408opposite the first surface406in a second, vertical direction (Z-axis) orthogonal to the first direction (X-axis). The metallization layer404A is adjacent to the first surface406and comprises an insulation layer410A and metal structures412A,414A embedded in the insulation layer410A. The metal structures412A,414A are composed of a single metal layer416and have a third surface418positioned at least a length (l) in the second, vertical direction (Z-axis) from the first surface406of the core layer402A. An insulation layer420is adjacent to the second surface408of the core layer402A in the second, vertical direction (Z-axis).

The core layer402B includes a fourth surface422and a fifth surface424opposite the fourth surface422in the second, vertical direction (Z-axis) orthogonal to the first direction (X-axis). The metallization layer404B is adjacent to the fourth surface422and comprises an insulation layer410B and metal structures412B,414B embedded in the insulation layer410B. The metal structures412B,414B are composed of a single metal layer426and have a sixth surface428and a seventh surface429. The sixth surface428is positioned at least a length (l) in the second, vertical direction (Z-axis) from the fourth surface422of the core layer402B. The seventh surface429is positioned at least the thickness (t) of the insulation layer420in the second, vertical direction (Z-axis) from the second surface408of the core layer402A. The thickness (t) is greater than the length (l). The minimum thickness (t) is 15 μm. An insulation layer430is adjacent to the fifth surface424of the core layer402B in the second, vertical direction (Z-axis). A metal via432connects metal structure412A with metal structure412B through the core layer402A. A metal via434connects metal structure414A with metal structure414B through the core layer402A. A metal via436connects a metal structure440with metal structure412B through the core layer402B. A metal via438connects metal structure442with metal structure414B through the core layer402B.

The insulation layers410A,410B,420, and430have a CTE that substantially matches the CTE of the core layers402A and402B. The insulation layers410A,410B.420, and430have a dielectric constant (κil) that substantially matches the dielectric constant (κcl) of the core layers402A and402B.

FIG.5is a side view of another exemplary embodiment of substrate106, substrate500employing two core layers wherein each core layer includes an adjacent insulation layer with an embedded metal structure positioned from its respective core layer to avoid electron migration wherein the embedded metal structures are composed of at least two metal layers. Common elements between the substrate500inFIG.5and elements of the substrate400inFIG.4are shown with common element numbers. Core layers402A,402B, similar to the core layer108, are adjacent to metallization layers404A,404B, respectively.

The core layers402A,402B extend in a first, horizontal direction (X-axis direction) and comprise a glass material208in the core layers402A and402B. The core layer402A includes a first surface406and a second surface408opposite the first surface406in a second, vertical direction (Z-axis) orthogonal to the first direction (X-axis). The metallization layer404A is adjacent to the first surface406and comprises an insulation layer410A and metal structures502A,504A embedded in the insulation layer410A. The metal structures502A,504A are composed of two metal layers, metal layer506and metal layer508. The metal structures502A,504A, also known as posts, have a third surface418positioned at least a length (l) in the second, vertical direction (Z-axis) from the first surface406of the core layer402A. An insulation layer420is adjacent to the second surface408of the core layer402A in the second, vertical direction (Z-axis).

The core layer402B includes a fourth surface422and a fifth surface424opposite the fourth surface422in the second, vertical direction (Z-axis) orthogonal to the first direction (X-axis). The metallization layer404B is adjacent to the fourth surface422and comprises an insulation layer410B and metal structures502B,504B embedded in the insulation layer410B. The metal structures502B,504B, also known as posts, are composed of two metal layers, metal layer510and512. Metal structure502B has a sixth surface428and a seventh surface513. The sixth surface428is positioned at least a length (l) in the second, vertical direction (Z-axis) from the fourth surface422of the core layer402B. The seventh surface513is positioned at least the thickness (t) of the insulation layer420in the second, vertical direction (Z-axis) from the second surface408of the core layer402A. The thickness (t) is greater than the length (l). The minimum thickness (t) is 15 μm. An insulation layer430is adjacent to the fifth surface424of the core layer402B in the second, vertical direction (Z-axis). A metal via514connects metal structure502A with metal structure502B through the core layer402A. A metal via516connects metal structure504A with metal structure504B through the core layer402A. A metal via518connects a metal structure520with metal structure502B through the core layer402B. A metal via522connects a metal structure524with metal structure504B through the core layer402B.

The insulation layers410A,410B,420, and430have a CTE that substantially matches the CTE of the core layers402A and402B. The insulation layers410A,410B,420, and430have a dielectric constant (κil) that substantially matches the dielectric constant (κcl) of the core layers402A and402B.

A substrate employing a core layer and an adjacent insulation layer with an embedded metal structure positioned from the core layer to avoid electron migration, including, but not limited to, the substrates200,300,400, and500inFIGS.2-5in the related IC package100inFIG.1can be fabricated by different fabrication processes.FIG.6is a flowchart illustrating an exemplary fabrication process600of fabricating a substrate such the substrates200,300,400, and500in the related IC package100inFIG.1, wherein the substrate employs a core layer and an adjacent insulation layer with an embedded metal structure positioned from the core layer to avoid electron migration, including, but not limited to, the substrates inFIGS.2-5.

In this regard, a first exemplary step in the fabrication process600ofFIG.6can include forming a first core layer108,402A. The first core layer108,402A comprises a glass material208, a first surface210,406, and a second surface212,408opposite the first surface in a second direction orthogonal to the first direction (block602inFIG.6). A next step in the fabrication process600can include forming a first metallization layer114,404A adjacent to the first surface210,406. The first metallization layer114,404A comprises a first insulation layer202,302,410A and a first metal structure204A,204B.304A,304B,310,412A,414A,502A,504A embedded in the first insulation layer202,302,410A (block604inFIG.6). A next step in the fabrication process600can include coupling the first metallization layer114,404A to the first core layer108,402A, the first metal structure204A,204B,304A,304B,310,412A,414A,502A,504A having a third surface214,418, the third surface214,418positioned at least a length (l) in the second direction from the first surface210,406of the first core layer108,402A (block606inFIG.6).

Other fabrication processes can also be employed to fabricate a substrate employing a core layer and an adjacent insulation layer with an embedded metal structure positioned from the core layer to avoid electron migration, including, but not limited to, the substrates200,300,400, and500inFIGS.2-5in the related IC package100inFIG.1. In this regard,FIGS.7A-7Care a flowchart illustrating another exemplary fabrication process700of fabricating a substrate which employs a core layer and an adjacent insulation layer with an embedded metal structure positioned from the core layer to avoid electron migration, including, but not limited to, the substrates200,400inFIGS.2and4.FIGS.8A-8Hare exemplary fabrication stages during fabrication of the substrate according to the fabrication process inFIGS.7A-7C. The fabrication process700as shown in the fabrication stages800A-800H inFIGS.8A-8Hare in reference to the substrate200inFIG.2and the related IC package100inFIG.1, and thus will be discussed with reference to the substrate200and related IC package100inFIGS.1and2. For economies of scale, the fabrication process700will be described when fabricating two individual substrates200.

In this regard, as shown in fabrication stage800A inFIG.8A, an exemplary step in the fabrication process700is to provide two core layers108(e.g., PPG material) with a first surface210and a second surface212(block702inFIG.7A). As shown at fabrication stage800B inFIG.8B, a next step in the fabrication process700can include laminating insulation layers202and216to each core layer108. Additionally, the fabrication process700can include applying a metal (Cu) seed layer802on the insulating layer216through an electroless Cu plating process (block704inFIG.7A). The insulation layers202and216will have a width (w). In parallel, the fabrication process700includes patterning a metal layer206on a carrier804. As shown at fabrication stage800C inFIG.8C, an exemplary step in the fabrication process700is to pattern metal layers206on both a top surface806and a bottom surface808of the carrier804(block706inFIG.7B). The patterned metal layers206have a height (h). The one metal layer206has a surface810and the other metal layer206has a surface812. As shown at fabrication stage800D inFIG.8D, a next step in the fabrication process700can include laminating one intermediate substrate from fabrication stage800B to the top surface806of the carrier804and the other intermediate substrate from fabrication stage800B to the bottom surface808of the carrier804(block708inFIG.7B). Regarding the metal seed layers802, another alternative to applying the metal seed layers802at fabrication stage800B is to apply the metal seed layers802after laminating the two intermediate substrates in fabrication stage800D by dipping the laminated intermediate substrates in a water solution containing copper salts and a reducing agent such as formaldehyde. As shown at fabrication stage800D, there is a distance, t, between the surface810of the one metal layer206and the surface210of the one core layer108. Also, there is a distance, t, between the surface812of the other metal layer206and the surface210of the other core layer108. As shown at fabrication stage800E inFIG.8E, a next step in the fabrication process700can include laser drilling holes814through the one core layer108to the surface810of the one metal layer206and laser drilling holes816through the other core layer108to the other surface812of the other metal layer206(block710inFIG.7B).

As shown at fabrication stage800F inFIG.8F, a next step in the fabrication process700can include patterning metal to fill the holes814and816and form metal vias818and820(block712inFIG.7C). Please note that seed layer802is removed during the patterning process. As shown at fabrication stage800G inFIG.8G, a next step in the fabrication process700can include detaching each of the two intermediate substrates822from the carrier804(block714inFIG.7C). As shown at fabrication stage800H inFIG.8H, a next step in the fabrication process700can include laminating insulation material222on both sides of the intermediate substrate822to form substrate200(block716inFIG.7C). Additionally, the two detached intermediate substrate822can be laminated together to form substrate400.

Other fabrication processes can also be employed to fabricate a substrate employing a core layer and an adjacent insulation layer with an embedded metal structure positioned from the core layer to avoid electron migration, including, but not limited to, the substrates200,300,400, and500inFIGS.2-5in the related IC package100inFIG.1. In this regard,FIGS.9A-9Dare a flowchart illustrating another exemplary fabrication process900of fabricating a substrate which employs a core layer and an adjacent insulation layer with an embedded metal structure positioned from the core layer to avoid electron migration, including, but not limited to, the substrates300,500inFIGS.3and5.FIGS.10A-10Iare exemplary fabrication stages during fabrication of the substrate according to the fabrication process inFIGS.9A-9D. The fabrication process900as shown in the fabrication stages1000A-1000I inFIGS.10A-10Iare in reference to the substrate300inFIG.3and the related IC package100inFIG.1, and thus will be discussed with reference to the substrate300and related IC package100inFIGS.1and3. For economies of scale, the fabrication process900will be described when fabricating two individual substrates300.

In this regard, as shown in fabrication stage1000A inFIG.10A, an exemplary step in the fabrication process900is to provide two core layers108(e.g., PPG material) with a first surface210and a second surface212(block902inFIG.9A). As shown at fabrication stage1000B inFIG.10B, a next step in the fabrication process900can include laminating insulation layers302and216to each core layer108. Additionally, the fabrication process900can include applying a metal (Cu) seed layer1002on the insulating layer216through an electroless Cu plating process (block904inFIG.9A). For simplicity, fabrication stage1000B shows one core layer108. The insulation layers302and216will have a width (w).

In parallel, the fabrication process900includes patterning a metal layer306on a carrier1004. As shown at fabrication stage1000C inFIG.10C, an exemplary step in the fabrication process900can include patterning metal layers306on both a top surface1006and bottom surface1008of the carrier1004(block906inFIG.9B). The patterned metal layers306have a height, h1. The one metal layer306has a surface1010and the other metal layer306has a surface1012. As shown at fabrication stage1000D inFIG.10D, a next step in the fabrication process900can include plating a second metal layer308on the surface1010of the one metal layer306and a second metal layer308on the surface1012of the other metal layer306(block908inFIG.9B). The second metal layer308has a surface214.

As shown at fabrication stage1000E inFIG.10E, a next step in the fabrication process900can include laminating one intermediate substrate from fabrication stage1000B to the top surface1006of the carrier1004and the other intermediate substrate from fabrication stage1000B to the bottom surface1008of the carrier1004(block910inFIG.9B). Regarding the metal seed layers1002, another alternative is applying the metal seed layer1002at fabrication stage1000B is to apply the metal seed layers1002after laminating the two intermediate substrates in fabrication stage1000D by dipping the laminated two intermediate substrates in a water solution containing copper salts and a reducing agent such as formaldehyde. As shown at fabrication stage1000E, there is a distance, t, between the surface214of the one metal layer308and the surface210of the one core layer108. Also, there is a distance, t, between the surface214of the other metal layer306and the surface210of the other core layer108. As shown at fabrication stage1000F inFIG.10F, a next step in the fabrication process900can include laser drilling holes1014through the one core layer108to the one surface214of the metal layer308and laser drilling holes1016through the other core layer108to the other surface214of the other metal layer308(block914inFIG.9C).

As shown at fabrication stage1000G inFIG.10G, a next step in the fabrication process900can include patterning metal to fill the holes1014,1016and form metal vias1018and1020(block916inFIG.9C). As shown at fabrication stage1000H inFIG.10H, a next step in the fabrication process900can include detaching each of the two intermediate substrates1022from the carrier1004(block918inFIG.9C). As shown at fabrication stage1000I inFIG.10I, a next step in the fabrication process900can include laminating insulation material222on both sides of the intermediate substrate1022to form substrate300(block920inFIG.9D). Additionally, the two detached intermediate substrates1022can be laminated together to form substrate500.

The substrate for an IC package wherein such substrate employs a core layer and an adjacent insulation layer with an embedded metal structure positioned from the core layer to avoid electron migration in the substrate(s), including, but not limited to, substrates200,300,400, and500inFIGS.2-5, may be provided in or integrated into any processor-based device. Examples, without limitation, include a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics systems, a drone, and a multicopter.

In this regard,FIG.11is a block diagram of an exemplary processor-based system1100that can include components deployed in an IC package, wherein the IC package includes a substrate(s)1102(1)-1100(7) employing a core layer and an adjacent insulation layer with an embedded metal structure positioned from the core layer to avoid electron migration in the substrate(s), including, but not limited to, the substrate(s)106,200,300,400, and500inFIGS.1-5and according to the exemplary fabrication processes inFIGS.6-10I. In this example, the processor-based system1100includes one or more central processing units (CPUs)1108, each including one or more processors1110. The CPU(s)1108may be a master device. The CPU(s)1108may have cache memory1112coupled to the processor(s)1110for rapid access to temporarily stored data. The CPU(s)1108is coupled to a system bus1114and can intercouple master and slave devices included in the processor-based system1100. As is well known, the CPU(s)1108communicates with these other devices by exchanging address, control, and data information over the system bus1114. For example, the CPU(s)1108can communicate bus transaction requests to a memory controller1116as an example of a slave device. Although not illustrated inFIG.11, multiple system buses could be provided, wherein each system bus1114constitutes a different fabric.

Other master and slave devices can be connected to the system bus1114. As illustrated inFIG.11, these devices can include a memory system1120, one or more input devices1122, one or more output devices1124, one or more network interface devices1126, and one or more display controllers1128, as examples. The input device(s)1122can include any type of input device, including, but not limited to, input keys, switches, voice processors, etc. The output device(s)1124can include any type of output device, including, but not limited to, audio, video, other visual indicators, etc. The network interface device(s)1126can be any devices configured to allow exchange of data to and from a network1130. The network1130can be any type of network, including, but not limited to, a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH™ network, and the Internet. The network interface device(s)1126can be configured to support any type of communications protocol desired. The memory system1120can include one or more memory arrays1118.

The CPU(s)1108may also be configured to access the display controller(s)1128over the system bus1114to control information sent to one or more displays1132. The display controller(s)1128sends information to the display(s)1132to be displayed via one or more video processors1134, which process the information to be displayed into a format suitable for the display(s)1132. The display(s)1132can include any type of display, including, but not limited to, a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, a light emitting diode (LED) display, etc.

FIG.12is a block diagram of an exemplary wireless communications device1200that includes radio-frequency (RF) components formed from one or more ICs1202, wherein any of the ICs1202include a substrate(s) employing a core layer and an adjacent insulation layer with an embedded metal structure positioned from the core layer to avoid electron migration in the substrate(s), including, but not limited to, the substrate(s)106,200,300,400, and500inFIGS.1-5, and according to the exemplary fabrication processes inFIGS.6-10I, and according to any exemplary aspects disclosed herein.

The wireless communications device1200may include or be provided in any of the above-referenced devices, as examples. As shown inFIG.12, the wireless communications device1200includes a transceiver1204and a data processor1206. The data processor1206may include a memory to store data and program codes. The transceiver1204includes a transmitter1208and a receiver1210that support bi-directional communications. In general, the wireless communications device1200may include any number of transmitters1208and/or receivers1210for any number of communication systems and frequency bands. All or a portion of the transceiver1204may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

The transmitter1208or the receiver1210may be implemented with a super-heterodyne architecture or a direct-conversion architecture. In the super-heterodyne architecture, a signal is frequency-converted between RF and baseband in multiple stages, for example, from RF to an intermediate frequency (IF) in one stage, and then from IF to baseband in another stage for the receiver1210. In the direct-conversion architecture, a signal is frequency-converted between RF and baseband in one stage. The super-heterodyne and direct-conversion architectures may use different circuit blocks and/or have different requirements. In the wireless communications device1200in Figure Y, the transmitter1208and the receiver1210are implemented with the direct-conversion architecture.

In the transmit path, the data processor1206processes data to be transmitted and provides I and Q analog output signals to the transmitter1208. In the exemplary wireless communications device1200, the data processor1206includes digital-to-analog converters (DACs)1212(1),1212(2) for converting digital signals generated by the data processor1206into the I and Q analog output signals (e.g., I and Q output currents) for further processing.

Within the transmitter1208, lowpass filters1214(1),1214(2) filter the I and Q analog output signals, respectively, to remove undesired signals caused by the prior digital-to-analog conversion. Amplifiers (AMPs)1216(1),1216(2) amplify the signals from the lowpass filters1214(1),1214(2), respectively, and provide I and Q baseband signals. An upconverter1218upconverts the I and Q baseband signals with I and Q transmit (TX) local oscillator (LO) signals through mixers1220(1),1220(2) from a TX LO signal generator1222to provide an upconverted signal1224. A filter1226filters the upconverted signal1224to remove undesired signals caused by the frequency up-conversion as well as noise in a receive frequency band. A power amplifier (PA)1228amplifies the upconverted signal1224from the filter1226to obtain the desired output power level and provides a transmit RF signal. The transmit RF signal is routed through a duplexer or switch1230and transmitted via an antenna1232.

In the receive path, the antenna1232receives signals transmitted by base stations and provides a received RF signal, which is routed through the duplexer or switch1230and provided to a low noise amplifier (LNA)1234. The duplexer or switch1230is designed to operate with a specific receive (RX)-to-TX duplexer frequency separation, such that RX signals are isolated from TX signals. The received RF signal is amplified by the LNA1234and filtered by a filter1236to obtain a desired RF input signal. Down-conversion mixers1238(1),1238(2) mix the output of the filter1236with I and Q RX LO signals (i.e., LO_I and LO_Q) from an RX LO signal generator1240to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs1242(1),1242(2) and further filtered by lowpass filters1244(1),1244(2) to obtain I and Q analog input signals, which are provided to the data processor1206. In this example, the data processor1206includes analog-to-digital converters (ADCs)1246(1),1246(2) for converting the analog input signals into digital signals to be further processed by the data processor1206.

In the wireless communications device1200ofFIG.12, the TX LO signal generator1222generates the I and Q TX LO signals used for frequency up-conversion, while the RX LO signal generator1240generates the I and Q RX LO signals used for frequency down-conversion. Each LO signal is a periodic signal with a particular fundamental frequency. A TX phase-locked loop (PLL) circuit1248receives timing information from the data processor1206and generates a control signal used to adjust the frequency and/or phase of the TX LO signals from the TX LO signal generator1222. Similarly, an RX PLL circuit1250receives timing information from the data processor1206and generates a control signal used to adjust the frequency and/or phase of the RX LO signals from the RX LO signal generator1240.

Implementation examples are described in the following numbered clauses:1. A substrate, comprising:a first core layer extending in a first direction comprising:a glass material;a first surface; anda second surface opposite the first surface in a second direction orthogonal to the first direction; anda first metallization layer adjacent to the first surface, the first metallization layer comprising:a first insulation layer; anda first metal structure embedded in the first insulation layer, the first metal structure having a third surface, the third surface positioned at least a length (l) in the second direction from the first surface of the first core layer.2. The substrate of clause 1, wherein the first insulation layer has a coefficient of thermal expansion (CTE) that substantially matches a CTE of the first core layer.3. The substrate of clause 1 or 2, wherein the first insulation layer has a first dielectric constant (κil) that substantially matches a second dielectric constant (κcl) of the first core layer.4. The substrate of any of clauses 1-3, wherein the first metal structure comprises:a first metal layer; anda second metal layer adjacent to the first metal layer forming a post.5. The substrate of any of clauses 1-4, wherein the first core layer further comprises a resin material.6. The substrate of any of clauses 1-5, wherein the first insulation layer comprises a resin material.7. The substrate of clause 6, wherein the resin material is selected from a group consisting of a resin coated Cu foil (RCC), a photo imageable dielectric (PID), and an Ajinomoto Build-up Film® (ABF).8. The substrate of any of clauses 1-7, further comprising:a second insulation layer adjacent to the second surface;a second metallization layer adjacent to the second insulation layer; anda metal via connecting the second metallization layer to the first metal structure through the second insulation layer and the first core layer.9. The substrate of clause 8, further comprising:a second core layer extending in the first direction, the second core layer comprising:a fourth surface; anda fifth surface, wherein the second metallization layer is adjacent to the fourth surface, the second metallization layer comprising:a third insulation layer; anda second metal structure embedded in the third insulation layer, the second metal structure having a sixth surface and a seventh surface, the sixth surface positioned at least a length (l) in the second direction from the fourth surface of the second core layer, the seventh surface positioned at least a thickness (t) in the second direction from the second surface of the first core layer.10. The substrate of any of clauses 1-9 integrated into an integrated circuit (IC).11. The substrate of any of clauses 1-10 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics systems; a drone; and a multicopter.12. A method for fabricating a substrate, comprising:forming a first core layer extending in a first direction, the first core layer comprising:a glass material;a first surface; anda second surface opposite the first surface in a second direction orthogonal to the first direction;forming a first metallization layer adjacent to the first surface, the first metallization layer comprising:a first insulation layer; anda first metal structure embedded in the first insulation layer; andcoupling the first metallization layer to the first core layer, the first metal structure having a third surface, the third surface positioned at least a length (l) in the second direction from the first surface of the first core layer.13. The method of clause 12, wherein the first insulation layer has a coefficient of thermal expansion (CTE) that substantially matches a CTE of the first core layer.14. The method of clause 12 or 13, wherein the first insulation layer has a first dielectric constant (κil) that substantially matches a second dielectric constant (κcl) of the first core layer.15. The method of any of clauses 12-14, wherein the first metal structure comprises:a first metal layer; anda second metal layer adjacent to the first metal layer forming a post.16. The method of any of clauses 12-15, wherein the first core layer further comprises a resin material.17. The method of any of clauses 12-16, wherein the first insulation layer comprises a resin material.18. The method of clause 17, wherein the resin material is selected from a group consisting of a resin coated Cu foil (RCC), a photo imageable dielectric (PID), and an Ajinomoto Build-up Film® (ABF).19. The method of any of clauses 12-18, further comprising:forming a second insulation layer adjacent to the second surface of the first core layer;forming a second metallization layer adjacent to the second insulation layer; andcoupling a metal via between the second metallization layer to the first metal structure through the second insulation layer and the first core layer.20. The method of clause 19, further comprising:forming a second core layer extending in the first direction, the second core layer comprising:a fourth surface; anda fifth surface, wherein the second metallization layer is adjacent to the fourth surface, the second metallization layer comprising:a third insulation layer; anda second metal structure embedded in the third insulation layer, the second metal structure having a sixth surface and a seventh surface, the sixth surface positioned at least a length (l) in the second direction from the fourth surface of the second core layer, the seventh surface positioned at least a thickness (t) in the second direction from the second surface of the first core layer.