Using thresholds to gate timing packet generation in a tracing system

In accordance with embodiments disclosed herein, there is provided systems and methods for using thresholds to gate timing packet generation in a tracing system (TS). For example, the method may include generating and outputting a trace data (TD) packet into a packet log. The method also includes generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

TECHNICAL FIELD

The embodiments of the disclosure relate generally to processing devices and, more specifically, relate to utilization of a threshold mechanism to limit output of timing packets in a tracing system.

BACKGROUND

A tracing system (TS) is a tracing capability, which provides a trace of software execution in a processor. This may include indication of changes in control flow, addresses accessed by load or store instructions, or other dynamic indication of software behavior. The trace output is in the form of packets of variable sizes. Such packets may include trace data (TD) packets and timing packets (TM).

DETAILED DESCRIPTION

Disclosed herein are embodiments for outputting a timing packet (TM) in a tracing system (TS). In one embodiment, the TM packet may be outputted when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value. The clock threshold value may be pre-defined as a specific number of clock cycles. The TM packet may be outputted corresponding to a trace data (TD) packet in the TS.

The output packet stream of the TS may typically consist of TD packets and a TM packet issued together with each of the TD packets. The TM packet provides a number of clock cycle counts that have passed between consecutive TD packets. As such, the TM packet provides an ability to analyze processor performance over the course of the trace, as well as an ability to align the trace with other logs or events that have related timing information. In many cases, timing granularity at the level of each packet is unnecessary, and undesirable given the correspondingly higher trace data rate associated with generating a TM packet with each TD packet. Elevated trace data rates can require larger trace output buffers, longer trace decode times, increased interference with the software being traced, and increased likelihood of trace data loss due to internal buffer overflow.

Embodiments of the disclosure introduce an ability to trade off precision in timing information, in exchange for reduced trace size and bandwidth. In one embodiment, a TS prevents generating and outputting the TM packet with every TD packet in the output packet stream. In one embodiment, the TM packet is generated and outputted with the TD packet when a clock threshold value is fulfilled. The clock threshold value may be pre-defined based on a specific task to be performed in the TD.

In some embodiments, the clock threshold is pre-defined with a specific number of clock cycles. A user may set the clock threshold to define its required timestamp resolution. In one embodiment, a TM packet may be generated and outputted with the TD packet when a total number of clock cycles that have elapsed since the last TM packet exceeds the predefined clock threshold. In one embodiment, the TM packet is generated and outputted only when the total number of clock cycles that have elapsed since the last TM packet exceeds the predefined clock threshold. In some embodiments, the TM packet is outputted adjacent to the TD packet. The TM packet may be appended to the TD packet, or it may precede the TD packet.

The above technique of reducing frequency of issuance of the TM packet in the TS has many advantages. One such advantage is the ability to obtain information associated with performance of the TD at a higher level. More specifically, the information is provided in a resolution provided by the user for that specific task, which helps a user to concentrate on information according to a nature of the specific task. Also, by reducing the number of TM packets issued into the TS output packet stream, the total number of data binary bytes may be reduced, thus reducing the memory bandwidth and output buffer size required for TS use. In some tracing systems, where enabling trace has a performance impact, this may also reduce the performance impact of generating trace data.

In the following description, numerous specific details are set forth (for example, specific TD logic implementations, TD packet formats, hardware/firmware partitioning details, logic partitioning/integration details, processor configurations, micro-architectural details, sequences of operations, types and interrelationships of system components, and the like). However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

FIG. 1Aillustrates an exemplary architecture100of a processor (also referred to herein as “processing device”) in accordance with which embodiments may operate. Architecture100includes TS architecture that generates real time TD packets115and TM packets117. In one embodiment, the processing device is a central processing unit (CPU).

In one embodiment, processing device120includes a retirement unit101. Retirement unit101can include a TS module103, which receives information from the retirement unit101and packetizes the information to output the TD packets115and the TM packets117in a TS output packet stream.

The TS module103includes a trace data packet generation component (TDPGC)105, which in turn generates and writes the TD packets115to the TS output packet stream. Trace Event1(TE1) and Trace Event2(TE2) are generic examples of TD packets that could be generated by a TS to indicate some specific events in the trace. Examples of such events could include, but are not limited to, taken branch completion, external interrupt receipt, processor frequency change, or memory store completion.

The TS module103may also include a timing packet generation component (TMPGC)107, which in turn generates and writes the TM packets117to the TS output packet stream. The TM packets117are outputted adjacent to the TD packets115.

The processor120also includes a clock frequency element129. The clock frequency element129may receive a reference clock signal that is used to generate clock cycle information as the timing information. Frequency may refer to the number of occurrences of a repeating event per unit time. The cycle information may be appended to other packets and may indicate the number of clock cycles elapsed between consecutive packets. The cycle packets may be issued with core clock resolution. In one embodiment, the clock frequency element129outputs the current clock cycles of the processor to the TS module103.

The TS module103may also include a clock counter component111. The clock counter component111counts number of clock cycles generated by the clock frequency element129as described above.

The TS module103includes a threshold comparison (TC) logic113, which compares the number of clock cycles counted by the clock counter component111to a clock threshold value. As discussed above, the clock threshold value may be pre-defined based on a specific task to be performed in the TD. Also, as discussed above, in some embodiments, the clock threshold value is pre-defined with a specific number of clock cycles. The clock threshold value may be assigned by a user, such as an administrator of the system containing the processor120. The clock threshold value options may include, but are not limited to, 16 clock cycles, 32 clock cycles or 64 clock cycles. In one embodiment, when the number of clock cycles exceeds the clock threshold value, the TC logic113will allow a TM packet to be generated with the next TD packet. When the TD packet is generated by the TDPGC105, the TC logic113sends a command signal to the TMGC107to generate and output the TM packet117into the TS output packet stream. The TMGC107outputs the TM packet117along with the generated TD packet115, to the TS output packet stream. In one embodiment, the TM packet117is appended to the TD packet115in the TS output packet stream. The clock counter component111is reset after outputting of the TM packet117into the TS output packet stream. In one embodiment, the clock counter component111is reset to zero. As such, the clock counter component111re-starts counting the cycle counts generated by the clock frequency element129.

In one implementation, the TM packet117is generated and outputted into the TS output packet stream without the TD packet115. Such implementation may occur when there is an overflow in the clock counter component111. The overflow in the clock counter component111may occur when a number of clock cycles have been counted without generating and outputting a TD packet115. For example, if the clock counter component111is a 12 bit counter, when 4,095 clock cycles have been counted and not a single TD packet has been issued, then at the next clock cycle a TM packet117with value 4096 is outputted into the TS output packet stream.

The TS module103may also include a configuration component109, which may allow software or firmware to configure the inclusion of the TM packets117in the TS packets115. In addition, the configuration component109may establish and manage the clock threshold value.

FIG. 1Billustrates an example of TD packets115and TM packets117generated and outputted into a TS output packet stream by the TS module103when a clock threshold is set to 32 clock cycles, for example. As shown, the TD packets115may include, but are not limited to, trace event1(TE1) packets120a-120n, trace event2(TE2) packets122a-122nand trace event3(TE3) packets124a-124n. The TM packets117may include clock cycle (CYC) packets130a-130n.

As shown inFIG. 1B, initially a CYC packet130ais generated and outputted into the TS output packet stream upon the generation and output of a TD packet, which in this example is TE1packet120a. As shown, the CYC packet130ais appended to the TE1packet120ain the TS output packet stream. After outputting the CYC packet130ainto the TS output packet stream, the clock counter component111is reset to zero, and continues counting the clock cycles.

Another CYC packet130bis then generated and outputted into the TS output packet stream when the number of counted clock cycles exceeds the clock threshold of 32 (in this example, counted clock cycles reaches 34) and the next TD packet (i.e., TE1packet120b) is generated and outputted into the TS output packet stream. As shown inFIG. 1B, one or more other TD packets such as the TE3packet124aand the TE2packet122aare generated and outputted into TS output packet stream without corresponding CYC packets. This occurs because the clock threshold of 32 had not been exceeded by the clock counter component111.

After outputting CYC packet130binto the TS output packet stream, the clock counter component111resets to zero and continues to count the clock cycles. When the number of clock cycles exceeds the clock threshold of 32, a CYC packet130ccan be generated and appended to the next TD packet occurring in the TS output packet stream. In this example, the next TD packet after the clock threshold of 32 is exceeded is TE3packet124b, which occurs 48 clock cycles after the issuance of the previous CYC packet130binto the TS output packet stream. Immediately after the TE3packet124bis generated, a third CYC packet130cis generated and appended to the TE3packet124bto be outputted into the TS output packet stream.

FIG. 2Ais a block diagram illustrating an in-order pipeline and a register re-naming stage, out-of-order issue/execution pipeline of a processor outputting timing packets (TM) in TS according to at least one embodiment of the invention.FIG. 2Bis a block diagram illustrating an in-order architecture core and a register renaming logic, out-of-order issue/execution logic to be included in a processor according to at least one embodiment of the invention. The solid lined boxes inFIG. 2Aillustrate the in-order pipeline, while the dashed lined boxes illustrates the register renaming, out-of-order issue/execution pipeline. Similarly, the solid lined boxes inFIG. 2Billustrate the in-order architecture logic, while the dashed lined boxes illustrates the register renaming logic and out-of-order issue/execution logic.

InFIG. 2A, a processor pipeline200includes a fetch stage202, a length decode stage204, a decode stage206, an allocation stage208, a renaming stage210, a scheduling (also known as a dispatch or issue) stage212, a register read/memory read stage214, an execute stage216, a write back/memory write stage218, an exception handling stage222, and a commit stage224. In some embodiments, the stages are provided in a different order and different stages may be considered in-order and out-of-order.

InFIG. 2B, arrows denote a coupling between two or more units and the direction of the arrow indicates a direction of data flow between those units.FIG. 2Bshows processor core290including a front end unit230coupled to an execution engine unit250, and both are coupled to a memory unit70.

The core290may be a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As yet another option, the core290may be a special-purpose core, such as, for example, a network or communication core, compression engine, graphics core, or the like.

The front end unit230includes a branch prediction unit232coupled to an instruction cache unit234, which is coupled to an instruction translation lookaside buffer (TLB)236, which is coupled to an instruction fetch unit238, which is coupled to a decode unit240. The decode unit or decoder may decode instructions, and generate as an output one or more micro-operations, micro-code entry points, microinstructions, other instructions, or other control signals, which are decoded from, or which otherwise reflect, or are derived from, the original instructions. The decoder may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc. The instruction cache unit234is further coupled to a level 2 (L2) cache unit276in the memory unit270. The decode unit240is coupled to a rename/allocator unit252in the execution engine unit250.

The execution engine unit250includes the rename/allocator unit252coupled to a retirement unit254and a set of one or more scheduler unit(s)256. The retirement unit254may include a TS component203to generate TD packets. The scheduler unit(s)256represents any number of different schedulers, including reservations stations, central instruction window, etc. The scheduler unit(s)256is coupled to the physical register file(s) unit(s)258. Each of the physical register file(s) units258represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, etc., status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc. The physical register file(s) unit(s)258is overlapped by the retirement unit254to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s), using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of registers; etc.).

Generally, the architectural registers are visible from the outside of the processor or from a programmer's perspective. The registers are not limited to any known particular type of circuit. Various different types of registers are suitable as long as they are capable of storing and providing data as described herein. Examples of suitable registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. The retirement unit254and the physical register file(s) unit(s)258are coupled to the execution cluster(s)460. The execution cluster(s)260includes a set of one or more execution units262and a set of one or more memory access units264. The execution units262may perform various operations (e.g., shifts, addition, subtraction, multiplication) and on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point).

While some embodiments may include a number of execution units dedicated to specific functions or sets of functions, other embodiments may include one execution unit or multiple execution units that all perform all functions. The scheduler unit(s)256, physical register file(s) unit(s)258, and execution cluster(s)260are shown as being possibly plural because certain embodiments create separate pipelines for certain types of data/operations (e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster—and in the case of a separate memory access pipeline, certain embodiments are implemented in which the execution cluster of this pipeline has the memory access unit(s)264). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.

The set of memory access units264is coupled to the memory unit270, which includes a data TLB unit272coupled to a data cache unit274coupled to a level 2 (L2) cache unit276. In one exemplary embodiment, the memory access units264may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit272in the memory unit270. The L2 cache unit276is coupled to one or more other levels of cache and eventually to a main memory.

By way of example, the exemplary register renaming, out-of-order issue/execution core architecture may implement the pipeline200as follows: 1) the instruction fetch38performs the fetch and length decoding stages202and204; 2) the decode unit240performs the decode stage206; 3) the rename/allocator unit252performs the allocation stage208and renaming stage210; 4) the scheduler unit(s)256performs the schedule stage212; 5) the physical register file(s) unit(s)258and the memory unit270perform the register read/memory read stage214; the execution cluster260perform the execute stage216; 6) the memory unit270and the physical register file(s) unit(s)258perform the write back/memory write stage218; 7) various units may be involved in the exception handling stage222; and 8) the retirement unit254and the physical register file(s) unit(s)258perform the commit stage224.

The core290may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, Calif.; the ARM instruction set (with additional extensions such as NEON) of ARM Holdings of Sunnyvale, Calif.).

While register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in-order architecture. While the illustrated embodiment of the processor also includes a separate instruction and data cache units234/274and a shared L2 cache unit276, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (L1) internal cache, or multiple levels of internal cache. In some embodiments, the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor. Alternatively, all of the cache may be external to the core and/or the processor.

FIG. 3is a flow diagram illustrating an example of a method300for outputting a TM packet into the TS. Method300may be performed by processing logic that may include hardware (e.g. circuitry, dedicated logic, programmable logic, microcode, etc.). The numbering of the blocks presented is for the sake of clarity and is not intended to prescribe an order of operations in which the various blocks may occur. In one embodiment, method300is performed by TS module103described with respect toFIG. 1.

Beginning with block301, a clock counter is reset to zero. The clock threshold value options may include, but are not limited to, 16 clock cycles, 32 clock cycles or 64 clock cycles. At block303, a number of clock cycles since the last TM packet in the TS output packet stream is counted. For example, the clock counter component111ofFIG. 1counts the number clock cycles generated by the clock frequency element129ofFIG. 1. At block305, it is determined that the TD packet is generated. At block307, the number of clock cycles is compared with the clock threshold. At block309, it is determined whether the number of clock cycles exceeds the clock threshold. If it is determined at block309that the number of clock cycles did not exceed the clock threshold, then at block311, the generated TD packet is outputted into the TS output packet stream, which is followed by repeat from block303. If it determined at block309that the number of clock cycles exceeds the clock threshold, then at block313, a TM packet is generated and outputted along with the generated TD packet into the TS output packet stream. In one embodiment, the TM packet is appended to the generated TD packet. Method300then returns to block303.

FIG. 4is a block diagram illustrating a micro-architecture for a processor400that includes logic circuits to perform instructions in accordance with one embodiment of the invention. In one embodiment, processor400outputs timing packets (TM) in a TS. In some embodiments, an instruction in accordance with one embodiment can be implemented to operate on data elements having sizes of byte, word, doubleword, quadword, etc., as well as datatypes, such as single and double precision integer and floating point datatypes. In one embodiment the in-order front end401is the part of the processor400that fetches instructions to be executed and prepares them to be used later in the processor pipeline. The front end401may include several units. In one embodiment, the instruction prefetcher426fetches instructions from memory and feeds them to an instruction decoder428, which in turn decodes or interprets them. For example, in one embodiment, the decoder decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called micro op or uops) that the machine can execute.

In other embodiments, the decoder parses the instruction into an opcode and corresponding data and control fields that are used by the micro-architecture to perform operations in accordance with one embodiment. In one embodiment, the trace cache430takes decoded uops and assembles them into program ordered sequences or traces in the uop queue434for execution. When the trace cache430encounters a complex instruction, the microcode ROM432provides the uops needed to complete the operation.

Some instructions are converted into a single micro-op, whereas others use several micro-ops to complete the full operation. In one embodiment, if more than four micro-ops are needed to complete an instruction, the decoder428accesses the microcode ROM432to do the instruction. For one embodiment, an instruction can be decoded into a small number of micro ops for processing at the instruction decoder428. In another embodiment, an instruction can be stored within the microcode ROM432should a number of micro-ops be needed to accomplish the operation. The trace cache430refers to an entry point programmable logic array (PLA) to determine a correct micro-instruction pointer for reading the micro-code sequences to complete one or more instructions in accordance with one embodiment from the micro-code ROM432. After the microcode ROM432finishes sequencing micro-ops for an instruction, the front end401of the machine resumes fetching micro-ops from the trace cache430.

The out-of-order execution engine403is where the instructions are prepared for execution. The out-of-order execution logic has a number of buffers to smooth out and re-order the flow of instructions to optimize performance as they go down the pipeline and get scheduled for execution. The allocator logic allocates the machine buffers and resources that each uop needs in order to execute. The register renaming logic renames logic registers onto entries in a register file. The allocator also allocates an entry for each uop in one of the two uop queues, one for memory operations and one for non-memory operations, in front of the instruction schedulers: memory scheduler, fast scheduler402, slow/general floating point scheduler404, and simple floating point scheduler406. The uop schedulers402,404,406determine when a uop is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources the uops use to complete their operation. The fast scheduler402of one embodiment can schedule on each half of the main clock cycle while the other schedulers can schedule once per main processor clock cycle. The schedulers arbitrate for the dispatch ports to schedule uops for execution.

Register files408,410sit between the schedulers402,404,406, and the execution units412,414,416,418,420,422,424in the execution block411. There is a separate register file208,410for integer and floating point operations, respectively. Each register file408,410, of one embodiment also includes a bypass network that can bypass or forward just completed results that have not yet been written into the register file to new dependent uops. The integer register file408and the floating point register file410are also capable of communicating data with the other. For one embodiment, the integer register file408is split into two separate register files, one register file for the low order 32 bits of data and a second register file for the high order 32 bits of data. The floating point register file410of one embodiment has 128 bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width.

The execution block411contains the execution units412,414,416,418,420,422,424, where the instructions are actually executed. This section includes the register files408,410, that store the integer and floating point data operand values that the micro-instructions use to execute. The execution block411may include a TS component to generate TD packets. The processor400of one embodiment is comprised of a number of execution units: address generation unit (AGU)412, AGU414, fast ALU416, fast ALU418, slow ALU420, floating point ALU422, floating point move unit424. For one embodiment, the floating point execution blocks422,424, execute floating point, MMX, SIMD, and SSE, or other operations. The floating point ALU422of one embodiment includes a 64 bit by 64 bit floating point divider to execute divide, square root, and remainder micro-ops. For embodiments of the invention, instructions involving a floating point value may be handled with the floating point hardware.

In one embodiment, the ALU operations go to the high-speed ALU execution units416,418. The fast ALUs416,418, of one embodiment can execute fast operations with an effective latency of half a clock cycle. For one embodiment, most complex integer operations go to the slow ALU420as the slow ALU420includes integer execution hardware for long latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. Memory load/store operations are executed by the AGUs412,414. For one embodiment, the integer ALUs416,418,420are described in the context of performing integer operations on 64 bit data operands. In alternative embodiments, the ALUs416,418,420can be implemented to support a variety of data bits including 16, 32, 128, 256, etc. Similarly, the floating point units422,424can be implemented to support a range of operands having bits of various widths. For one embodiment, the floating point units422,424can operate on 128 bits wide packed data operands in conjunction with SIMD and multimedia instructions.

In one embodiment, the uops schedulers402,404,406dispatch dependent operations before the parent load has finished executing. As uops are speculatively scheduled and executed in processor400, the processor400also includes logic to handle memory misses. If a data load misses in the data cache, there can be dependent operations in flight in the pipeline that have left the scheduler with temporarily incorrect data. A replay mechanism tracks and re-executes instructions that use incorrect data. The dependent operations should be replayed and the independent ones are allowed to complete. The schedulers and replay mechanism of one embodiment of a processor are also designed to catch instruction sequences for text string comparison operations.

The term “registers” may refer to the on-board processor storage locations that are used as part of instructions to identify operands. In other words, registers may be those that are usable from the outside of the processor (from a programmer's perspective). However, the registers of an embodiment should not be limited in meaning to a particular type of circuit. Rather, a register of an embodiment is capable of storing and providing data, and performing the functions described herein. The registers described herein can be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In one embodiment, integer registers store thirty-two bit integer data.

A register file of one embodiment also contains eight multimedia SIMD registers for packed data. For the discussions below, the registers are understood to be data registers designed to hold packed data, such as 64 bits wide MMX registers (also referred to as ‘mm’ registers in some instances) in microprocessors enabled with the MMX™ technology from Intel Corporation of Santa Clara, Calif. These MMX registers, available in both integer and floating point forms, can operate with packed data elements that accompany SIMD and SSE instructions. Similarly, 128 bits wide XMM registers relating to SSE2, SSE3, SSE4, or beyond (referred to generically as “SSEx”) technology can also be used to hold such packed data operands. In one embodiment, in storing packed data and integer data, the registers do not differentiate between the two data types. In one embodiment, integer and floating point are either contained in the same register file or different register files. Furthermore, in one embodiment, floating point and integer data may be stored in different registers or the same registers.

FIG. 5Aillustrates an alternative exemplary architecture in accordance with which embodiments may operate. In one embodiment, the integrated circuit501includes TS module503to trace behavior of a traced application, mode, or code region, as the instructions are executed by the integrated circuit501; a retirement unit506to output TM packets in a TS. The retirement unit506may include a TD packet generation component505to generate a plurality of TD packets. The retirement unit506may also include a TM packet generation component507to generate a plurality of TM packets adjacent to the TD packets. The retirement unit506may also include a clock counter component511, which counts a number of clock cycles elapsed between consecutive TM packets. The retirement unit506may further include a threshold comparison logic513to compare the number of counted clock cycles to a clock threshold value, and to send a command signal to the TM packet generation component507to generate and output the TM packet with the next TD packet based on the comparison. In one embodiment, the retirement unit506implements the tracing logic503.

In one embodiment, the retirement unit506includes TS logic to implement the tracing module503. In one embodiment, the TD logic implementing the tracing component503includes a state packet generation component505, periodic sync point counter component507configuration component509and event packet generation component511. In one embodiment, the state packet generation component505outputs packets, such as the TD packets502depicted on the data bus504. In one embodiment, the event packet generation component511also outputs packets such as the TD packets502depicted on the data bus504. In one embodiment, logic implementing the tracing component503may be implemented in hardware. In one embodiment, logic implementing the tracing component503may be implemented in microcode. In one embodiment, logic implementing the tracing component503may be implemented in a combination hardware and microcode.

In one embodiment, the integrated circuit is a Central Processing Unit (CPU). In one embodiment, the central processing unit is utilized for one of a tablet computing device or a smartphone.

In accordance with one embodiment, such an integrated circuit501thus initiates tracing (e.g., via tracing system module503) for instructions of a traced application, mode, or code region, as the instructions are executed by the integrated circuit501; generates a plurality of TD packets (e.g., via TD generation component505); generate a plurality of TM packets adjacent to the TD packets (e.g. via TM generation component507); count a number of clock cycles elapsed between consecutive TM packets (e.g. via clock counter component511) and compare the number of counted clock cycles to a clock threshold value and to send a command signal to the TM packet generation component507to generate and output the TM packet with the next TD packet based on the comparison (e.g. via threshold comparison logic513). In one embodiment, the integrated circuit501generates and outputs the TM packet with the next TD packet when the number of clock cycles exceeds the clock threshold value.

FIG. 5Bshows a diagrammatic representation of a system599in accordance with which embodiments may operate, be installed, integrated, or configured.

In one embodiment, system599includes a memory595and a processor or processors596. For example, memory595may store instructions to be executed and processor(s)596may execute such instructions. System599includes communication bus(es)565to transfer transactions, instructions, requests, and data within system599among a plurality of peripheral device(s)570communicably interfaced with one or more communication buses565and/or interface(s)575. Display unit580is additionally depicted within system599.

Distinct within system599is integrated circuit501which may be installed and configured in a compatible system599, or manufactured and provided separately so as to operate in conjunction with appropriate components of system599.

In accordance with one embodiment, system599includes at least a display unit580and an integrated circuit501. The integrated circuit501may operate as, for example, a processor or as another computing component of system599. In such an embodiment, the integrated circuit501of system599includes at least: a data bus504, and tracing system module503including a state packet generation component (not shown) and event packet generation component (not shown) to generate a plurality of TD packets describing the traced instructions. In one embodiment, the TD packets include information describing a status of the processor and a synchronization point in the traced instructions.

In accordance with one embodiment, such a system599embodies a tablet or a smartphone, in which the display unit580is a touchscreen interface of the tablet or the smartphone; and further in which the integrated circuit501is incorporated into the tablet or smartphone.

Referring now toFIG. 6, shown is a block diagram of a system600in accordance with one embodiment of the invention. The system600may include one or more processors610,615, which are coupled to graphics memory controller hub (GMCH)620. The optional nature of additional processors615is denoted inFIG. 6with broken lines. In one embodiment, processors610,615outputs timing packets (TM) in TS.

Each processor610,615may be some version of the circuit, integrated circuit, processor, and/or silicon integrated circuit as described above. However, it should be noted that it is unlikely that integrated graphics logic and integrated memory control units would exist in the processors610,615.FIG. 6illustrates that the GMCH620may be coupled to a memory640that may be, for example, a dynamic random access memory (DRAM). The DRAM may, for at least one embodiment, be associated with a non-volatile cache.

The GMCH620may be a chipset, or a portion of a chipset. The GMCH620may communicate with the processor(s)610,615and control interaction between the processor(s)610,615and memory640. The GMCH620may also act as an accelerated bus interface between the processor(s)610,615and other elements of the system600. For at least one embodiment, the GMCH620communicates with the processor(s)610,615via a multi-drop bus, such as a frontside bus (FSB)695.

Furthermore, GMCH620is coupled to a display645(such as a flat panel or touchscreen display). GMCH620may include an integrated graphics accelerator. GMCH620is further coupled to an input/output (I/O) controller hub (ICH)650, which may be used to couple various peripheral devices to system600. Shown for example in the embodiment ofFIG. 6is an external graphics device660, which may be a discrete graphics device coupled to ICH650, along with another peripheral device670.

Alternatively, additional or different processors may also be present in the system600. For example, additional processor(s)615may include additional processors(s) that are the same as processor610, additional processor(s) that are heterogeneous or asymmetric to processor610, accelerators (such as, e.g., graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays, or any other processor. There can be a variety of differences between the processor(s)610,615in terms of a spectrum of metrics of merit including architectural, micro-architectural thermal, power consumption characteristics, and the like. These differences may effectively manifest themselves as asymmetry and heterogeneity amongst the processors610,615. For at least one embodiment, the various processors610,615may reside in the same die package.

Embodiments may be implemented in many different system types.FIG. 7is a block diagram of a SoC700in accordance with an embodiment of the present disclosure. Dashed lined boxes are optional features on more advanced SoCs. InFIG. 7, an interconnect unit(s)712is coupled to: an application processor720which includes a set of one or more cores702A-N and shared cache unit(s)706; a system agent unit710; a bus controller unit(s)716; an integrated memory controller unit(s)714; a set or one or more media processors718which may include integrated graphics logic708, an image processor724for providing still and/or video camera functionality, an audio processor726for providing hardware audio acceleration, and a video processor728for providing video encode/decode acceleration; an static random access memory (SRAM) unit730; a direct memory access (DMA) unit732; and a display unit740for coupling to one or more external displays. In one embodiment, a memory module may be included in the integrated memory controller unit(s)714. In another embodiment, the memory module may be included in one or more other components of the SoC700that may be used to access and/or control a memory. The application processor720may include an conditional branch, indirect branch and event execution logics as described in embodiments herein.

The memory hierarchy includes one or more levels of cache within the cores, a set or one or more shared cache units706, and external memory (not shown) coupled to the set of integrated memory controller units714. The set of shared cache units706may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, a last level cache (LLC), and/or combinations thereof.

In some embodiments, one or more of the cores702A-N are capable of multi-threading.

The system agent710includes those components coordinating and operating cores702A-N. The system agent unit710may include for example a power control unit (PCU) and a display unit. The PCU may be or include logic and components needed for regulating the power state of the cores702A-N and the integrated graphics logic708. The display unit is for driving one or more externally connected displays.

The cores702A-N may be homogenous or heterogeneous in terms of architecture and/or instruction set. For example, some of the cores702A-N may be in order while others are out-of-order. As another example, two or more of the cores702A-N may be capable of execution the same instruction set, while others may be capable of executing only a subset of that instruction set or a different instruction set.

The application processor720may be a general-purpose processor, such as a Core™ i3, i5, i7, 2 Duo and Quad, Xeon™, Itanium™, XScale™ or StrongARM™ processor, which are available from Intel™ Corporation, of Santa Clara, Calif. Alternatively, the application processor720may be from another company, such as ARM Holdings™, Ltd, MIPS™, etc. The application processor720may be a special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, co-processor, embedded processor, or the like. The application processor720may be implemented on one or more chips. The application processor720may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, BiCMOS, CMOS, or NMOS.

FIG. 8is a block diagram of an embodiment of a system on-chip (SoC) design in accordance with the present disclosure. As a specific illustrative example, SoC800is included in user equipment (UE). In one embodiment, UE refers to any device to be used by an end-user to communicate, such as a hand-held phone, smartphone, tablet, ultra-thin notebook, notebook with broadband adapter, or any other similar communication device. Often a UE connects to a base station or node, which potentially corresponds in nature to a mobile station (MS) in a GSM network.

Here, SOC1300includes 2 core—806and807. Cores806and807may conform to an Instruction Set Architecture, such as an Intel® Architecture Core™-based processor, an Advanced Micro Devices, Inc. (AMD) processor, a MIPS-based processor, an ARM-based processor design, or a customer thereof, as well as their licensees or adopters. Cores806and807are coupled to cache control808that is associated with bus interface unit808and L2 cache810to communicate with other parts of system800. Interconnect810includes an on-chip interconnect, such as an IOSF, AMBA, or other interconnect discussed above, which potentially implements one or more aspects of the described disclosure. In one embodiment, a conditional branch, indirect branch and event execution logics may be included in cores806,807.

Interconnect810provides communication channels to the other components, such as a Subscriber Identity Module (SIM)830to interface with a SIM card, a boot ROM835to hold boot code for execution by cores806and807to initialize and boot SoC800, a SDRAM controller840to interface with external memory (e.g. DRAM860), a flash controller845to interface with non-volatile memory (e.g. Flash865), a peripheral control850(e.g. Serial Peripheral Interface) to interface with peripherals, video codecs820and Video interface825to display and receive input (e.g. touch enabled input), GPU815to perform graphics related computations, etc. Any of these interfaces may incorporate aspects of the disclosure described herein. In addition, the system800illustrates peripherals for communication, such as a Bluetooth module870, 3G modem875, GPS880, and Wi-Fi885.

Referring now toFIG. 9, shown is a block diagram of a system900in accordance with an embodiment of the invention. As shown inFIG. 9, multiprocessor system900is a point-to-point interconnect system, and includes a first processor970and a second processor980coupled via a point-to-point interconnect950. Each of processors970and980may be some version of the processors of the computing systems as described herein. In one embodiment, processors970,980outputs timing packets (TM) in TS.

While shown with two processors970,980, it is to be understood that the scope of the disclosure is not so limited. In other embodiments, one or more additional processors may be present in a given processor.

Processors970and980are shown including integrated memory controller units972and982, respectively. Processor970also includes as part of its bus controller units point-to-point (P-P) interfaces976and978; similarly, second processor980includes P-P interfaces986and988. Processors970,980may exchange information via a point-to-point (P-P) interface950using P-P interface circuits978,988. As shown inFIG. 9, IMCs972and982couple the processors to respective memories, namely a memory932and a memory934, which may be portions of main memory locally attached to the respective processors.

Processors970and980may each exchange information with a chipset990via individual P-P interfaces952,954using point to point interface circuits976,994,986,998. Chipset990may also exchange information with a high-performance graphics circuit938via a high-performance graphics interface939.

Chipset990may be coupled to a first bus916via an interface996. In one embodiment, first bus916may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation I/O interconnect bus, although the scope of the disclosure is not so limited.

As shown inFIG. 9, various I/O devices914may be coupled to first bus916, along with a bus bridge918which couples first bus916to a second bus920. In one embodiment, second bus920may be a low pin count (LPC) bus. Various devices may be coupled to second bus920including, for example, a keyboard and/or mouse922, communication devices927and a storage unit928such as a disk drive or other mass storage device which may include instructions/code and data930, in one embodiment. Further, an audio I/O924may be coupled to second bus920. Note that other architectures are possible. For example, instead of the point-to-point architecture ofFIG. 9, a system may implement a multi-drop bus or other such architecture.

Referring now toFIG. 10, shown is a block diagram of a system1000in accordance with an embodiment of the invention.FIG. 10illustrates processors1070,1080. In one embodiment, processors1070,1080outputs timing packets (TM) in TS. Furthermore, processors1070,1080may include integrated memory and I/O control logic (“CL”)1072and1082, respectively and intercommunicate with each other via point-to-point interconnect1050between point-to-point (P-P) interfaces1078and1088respectively. Processors1070,1080each communicate with chipset1090via point-to-point interconnect1052and1054through the respective P-P interfaces1076to1094and1086to1098as shown. For at least one embodiment, the CL1072,1082may include integrated memory controller units. CLs1072,1082may include I/O control logic. As depicted, memories1032,1034coupled to CLs1072,1082and I/O devices1014are also coupled to the control logic1072,1082. Legacy I/O devices1015are coupled to the chipset1090via interface1096.

FIG. 11illustrates a block diagram1100of an embodiment of tablet computing device, a smartphone, or other mobile device in which touchscreen interface connectors may be used. Processor1110may output timing packets (TM) in TS. In addition, processor1110performs the primary processing operations. Audio subsystem1120represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. In one embodiment, a user interacts with the tablet computing device or smartphone by providing audio commands that are received and processed by processor1110.

Display subsystem1130represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the tablet computing device or smartphone. Display subsystem1130includes display interface1132, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display subsystem1130includes a touchscreen device that provides both output and input to a user.

I/O controller1140represents hardware devices and software components related to interaction with a user. I/O controller1140can operate to manage hardware that is part of audio subsystem1120and/or display subsystem1130. Additionally, I/O controller1140illustrates a connection point for additional devices that connect to the tablet computing device or smartphone through which a user might interact. In one embodiment, I/O controller1140manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the tablet computing device or smartphone. The input can be part of direct user interaction, as well as providing environmental input to the tablet computing device or smartphone.

In one embodiment, the tablet computing device or smartphone includes power management1150that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem1160includes memory devices for storing information in the tablet computing device or smartphone. Connectivity1170includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to the tablet computing device or smartphone to communicate with external devices. Cellular connectivity1172may include, for example, wireless carriers such as GSM (global system for mobile communications), CDMA (code division multiple access), TDM (time division multiplexing), or other cellular service standards). Wireless connectivity1174may include, for example, activity that is not cellular, such as personal area networks (e.g., Bluetooth), local area networks (e.g., WiFi), and/or wide area networks (e.g., WiMax), or other wireless communication.

Peripheral connections1180include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections as a peripheral device (“to”1182) to other computing devices, as well as have peripheral devices (“from”1184) connected to the tablet computing device or smartphone, including, for example, a “docking” connector to connect with other computing devices. Peripheral connections1180include common or standards-based connectors, such as a Universal Serial Bus (USB) connector, DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, etc.

The computing system1200includes a processing device1202, a main memory1204(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or DRAM (RDRAM), etc.), a static memory1206(e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device1218, which communicate with each other via a bus1230.

Processing device1202represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computer (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device1202may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. In one embodiment, processing device1202may include one or processing cores. The processing device1202is configured to execute the processing logic1226for performing the operations discussed herein. In one embodiment, processing device1202is the same as processing device120described with respect toFIG. 1Athat implements the trace module103and scheduler and execution unit102. Alternatively, the computing system1200can include other components as described herein.

The computing system1200may further include a network interface device1208communicably coupled to a network1220. The computing system1200also may include a video display unit1210(e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device1212(e.g., a keyboard), a cursor control device1214(e.g., a mouse), a signal generation device1216(e.g., a speaker), or other peripheral devices. Furthermore, computing system1200may include a graphics processing unit1222, a video processing unit1228and an audio processing unit1232. In another embodiment, the computing system1200may include a chipset (not illustrated), which refers to a group of integrated circuits, or chips, that are designed to work with the processing device1202and controls communications between the processing device1202and external devices. For example, the chipset may be a set of chips on a motherboard that links the processing device1202to very high-speed devices, such as main memory1204and graphic controllers, as well as linking the processing device1202to lower-speed peripheral buses of peripherals, such as USB, PCI or ISA buses.

The data storage device1218may include a computer-readable storage medium1224on which is stored software1226embodying any one or more of the methodologies of functions described herein. The software1226may also reside, completely or at least partially, within the main memory1204as instructions1226and/or within the processing device1202as processing logic1226during execution thereof by the computing system1200; the main memory1204and the processing device1202also constituting computer-readable storage media.

The computer-readable storage medium1224may also be used to store instructions1226utilizing the trace component103and the scheduler and execution unit102, such as described with respect toFIG. 1, and/or a software library containing methods that call the above applications. While the computer-readable storage medium1224is shown in an example embodiment to be a single medium, the term “computer-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “computer-readable storage medium” shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instruction for execution by the machine and that cause the machine to perform any one or more of the methodologies of the embodiments. The term “computer-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media. While the invention has been described with respect to a limited number of embodiments, those skilled in the art will appreciate numerous modifications and variations therefrom. It is intended that the appended claims cover all such modifications and variations as fall within the true spirit and scope of this invention.

The following examples pertain to further embodiments.

Example 1 is a processing device using thresholds to gate timing packet generation in a tracing system (TS) comprising a tracing (TD) module to generate and output a trace data (TD) packet into a packet log and generate and output a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

In Example 2, the subject matter of Example 1 can optionally include wherein the TM packet precedes the TD packet in the packet log.

In Example 3, the subject matter of any one of Examples 1-2 can optionally include wherein the TM packet is appended to the TD packet in the packet log.

In Example 4, the subject matter of any one of Examples 1-3 can optionally include wherein the clock threshold value comprises a pre-determined number of clock cycles.

In Example 5, the subject matter of any one of Examples 1-4 can optionally include wherein the TS module comprises a clock counter component to count the number of clock cycles and a threshold comparison component to compare the clock threshold value with the counted number of clock cycles.

In Example 6, the subject matter of any one of Examples 1-5 can optionally include wherein the TS module comprises a TD packet generation component to generate and output the TD packet into the packet log.

In Example 7, the subject matter of any one of Examples 1-6 can optionally include wherein the TS module comprise a TM packet generation component to generate and output the TM packet adjacent to the TD packet in the packet log when the number of clock cycles exceeds the clock threshold value, wherein the TM packet generation component is coupled to the TD packet generation component and the threshold comparison component.

In Example 8, the subject matter of any one of Examples 1-7 can optionally include wherein the clock counter component is reset to zero after the TM packet is outputted into the packet log.

Example 9 is a system using thresholds to gate timing packet generation in a tracing system (TS). and includes a memory and a processing device communicably coupled to the memory, the processing device includes a data bus and a tracing module (TD) communicably coupled to the data bus, the TS module to generate and output a trace data (TD) packet into a packet log and generate and output a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

In Example 10, the subject matter of Example 9 can optionally include wherein the TM packet is outputted together with the TD packet into the packet log.

Example 11 is a method using thresholds to gate timing packet generation in a tracing system (TS) comprising generating and outputting a trace data (TD) packet into a packet log and generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

In Example 12, the subject matter of Example 11 can optionally include wherein the TM packet precedes the TD packet into the packet log.

In Example 13, the subject matter of any one of Examples 11-12 can optionally include wherein the TM packet is appended to the TD packet in the packet log.

In Example 14, the subject matter of any one of Examples 11-13 can optionally include wherein the clock threshold value comprises a pre-determined number of clock cycles

In Example 15, the subject matter of any one of Examples 11-14 can optionally include counting the number of clock cycles and comparing the clock threshold value to the counted number of clock cycles

Example 16 is a non-transitory machine-readable storage medium for using thresholds to gate timing packet generation in a tracing system (TS).

In Example 16, the non-transitory machine-readable medium includes data that, when accessed by a processing device, cause the processing device to perform operations comprising generating and outputting a trace data (TD) packet into a packet log and generating and outputting a timing packet (TM) corresponding to the TD packet into the packet log when a number of clock cycles elapsed since an output of a previous TM packet exceeds a clock threshold value.

In Example 17, the subject matter of Example 16 can optionally include wherein the TM packet precedes the TD packet into the packet log.

In Example 18, the subject matter of any one of Examples 16-17 can optionally include wherein the TM packet is appended to the TD packet in the packet log.

In Example 19, the subject matter of any one of Examples 16-18 can optionally include wherein the clock threshold value comprises a pre-determined number of clock cycles.

In Example 20, the subject matter of any one of Examples 16-19 can optionally include wherein the operations further comprising counting the number of clock cycles and comparing the clock threshold value to the counted number of clock cycles.

Various embodiments may have different combinations of the structural features described above. For instance, all optional features of the SOC described above may also be implemented with respect to a processor described herein and specifics in the examples may be used anywhere in one or more embodiments.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics maybe combined in any suitable manner in one or more embodiments.