SEMICONDUCTOR DEVICE WITH BACKSIDE U-SHAPED SILICIDE

A semiconductor device is provided. The semiconductor device includes a field effect transistor (FET) structure having a source/drain (S/D) region between channel regions, primary epitaxy disposed in the S/D region and a backside contact disposed in contact with and gouging into the primary epitaxy.

BACKGROUND

The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to a semiconductor device fabrication method to form a semiconductor device with backside U-shaped silicide.

SUMMARY

Embodiments of the invention are directed to a semiconductor device. A non-limiting example of the semiconductor device includes a field effect transistor (FET) structure having a source/drain (S/D) region between channel regions, primary epitaxy disposed in the S/D region and a backside contact disposed in contact with and gouging into the primary epitaxy.

Embodiments of the present invention are directed to a semiconductor device. A non-limiting example of the semiconductor device includes a backside power rail, a field effect transistor (FET) structure having source/drain (S/D) regions between channel regions, primary epitaxy disposed in each of the S/D regions and a backside contact disposed in contact with the backside power rail and the primary epitaxy in a first one of the S/D regions and gouging into the primary epitaxy in the first one of the S/D regions.

Embodiments of the present invention are directed to a semiconductor device fabrication method. A non-limiting example of the semiconductor device fabrication method includes forming bottom dielectric isolation (BDI) under a gate structure with a source/drain (S/D) region and replacing a portion of the BDI in the S/D region with a sacrificial placeholder. In addition, the semiconductor device fabrication method further includes growing primary epitaxy over the sacrificial placeholder, using the sacrificial placeholder to create an opening, removing the sacrificial placeholder, enlarging the opening, growing backside trench epitaxy in contact with the primary epitaxy and within the opening, forming sacrificial spacers in a periphery of a remaining portion of the opening to define an aperture, gouging into the backside trench epitaxy and the primary epitaxy via the aperture to form a contact opening and forming a backside contact by metallization of the contact opening.

In the accompanying figures and following detailed description of the described embodiments, the various elements illustrated in the figures are provided with two or three digit reference numbers. With minor exceptions, the leftmost digit(s) of each reference number correspond to the figure in which its element is first illustrated.

DETAILED DESCRIPTION

Turning now to an overview of technologies that are more specifically relevant to aspects of the invention, a field effect transistor (FET) typically has a source, a channel and a drain where current flows from the source to the drain as well as a gate that controls the flow of current through the device channel. FETs can have a variety of different structures. For example, FETs have been fabricated with the source, channel and drain formed in a substrate material itself, where the current flows horizontally (i.e., in the plane of the substrate). As another example, FinFETs have been formed with the channel extending outwardly from the substrate, but where the current also flows horizontally from the source to the drain. The channel for the FinFET can be an upright slab of thin rectangular silicon (Si), commonly referred to as the fin with a gate on the fin, as compared to a metal-oxide-semiconductor FET (MOSFET) with a single gate parallel with the plane of the substrate. Depending on doping of the source and drain, an n-doped FET (nFET) or a p-doped FET (pFET) can be formed. Two FETs also can be coupled to form a complementary metal-oxide-semiconductor (CMOS) device, where a p-channel MOSFET and n-channel MOSFET are coupled together.

In certain logic circuits in which FETs are employed, contacts are provided to allow for electrical communication between source/drain (S/D) epitaxy of FET devices and external features. Frontside contacts allow for electrical communication between FET devices and middle-of-line (MOL) or back-end-of-line (BEOL) layers whereas backside contacts allow for electrical communication between S/D epitaxy of FET devices and backside power rails or backside power delivery networks (BSPDN). The total resistance of these connections, i.e., the connection of a metal backside contact to S/D epitaxy of an FET, is dominated by the metal-to-epitaxy contact resistivity. In fact, it has been observed that this “contact resistance” effectively forms a bottleneck for next generation logic circuits.

A need therefore remains for a semiconductor device exhibiting reduced contact resistance, such as metal-to-epitaxy contact resistivity, between a metal contact and S/D epitaxy of an FET device.

Turning now to an overview of the aspects of the invention, one or more embodiments of the invention address the above-described shortcomings of the prior art by providing a method of semiconductor device fabrication. The method includes forming bottom dielectric isolation (BDI) under a gate structure and forming a sacrificial placeholder under original S/D epitaxy of the gate structure followed by wafer flipping and substrate removal. The method further includes removing the sacrificial placeholder, enlarging a contact size, forming backside trench epitaxy in contact with the original S/D epitaxy, forming sacrificial spacers and contact gouging into the backside trench epitaxy and the original S/D epitaxy. In addition, the method includes removing the sacrificial spacers and forming a backside contact by metallization.

The above-described aspects of the invention address the shortcomings of the prior art by providing for a semiconductor device that includes a backside power rail and a backside contact by which the backside power rail is electrically connected to S/D epitaxy.

Turning now to a more detailed description of aspects of the present invention,FIG.1depicts a method of semiconductor device fabrication100according to one or more embodiments of the present invention.

As shown inFIG.1, the method of semiconductor device fabrication100includes forming bottom dielectric isolation (BDI) under a gate structure with a source/drain (S/D) region (block101) and replacing a portion of the BDI in the S/D region with a sacrificial placeholder (block102). The method of semiconductor device fabrication100further includes growing primary epitaxy over the sacrificial placeholder (block103), using the sacrificial placeholder to create an opening (block104), removing the sacrificial placeholder (block105) and enlarging the opening (block106) by widening the opening. In addition, the method of semiconductor device fabrication100also includes growing backside trench epitaxy in contact with the primary epitaxy and within the opening (block107), forming sacrificial spacers in a periphery of a remaining portion of the opening to define an aperture (block108), gouging into the backside trench epitaxy and the primary epitaxy via the aperture to form a contact opening (block109) and forming a backside contact by metallization of the contact opening (block110). The contact opening can be formed with a diameter (i.e., a maximum diameter) that is smaller than that of the backside trench epitaxy and the primary epitaxy. The contact opening can have a V-shape or a U-shape, for example, although other shapes for the contact opening are possible.

With reference toFIGS.2-8B, the method of semiconductor device fabrication100ofFIG.1will now be described in greater detail.

FIG.2depicts a top-down view of semiconductor device201being fabricated and illustrates that the semiconductor device201will eventually include active nFET regions210,211, active nFET regions212,213, active pFET regions214,215and active pFET regions216,217as well as non-active regions220,221and non-active regions222,223and gates230,231,232. The gates230,231,232span the active nFET regions210,211, the active nFET regions212,213, the active pFET regions214,215and the active pFET regions216,217as well as the non-active regions220,221and the non-active regions222,223.FIGS.3-9are cross-sectional views of varying stages of semiconductor device fabrication which correspond to line2-2ofFIG.2.

As shown inFIG.3, an initial structure301of a semiconductor device is provided in accordance with one or more embodiments of the present invention. The initial structure301includes a semiconductor substrate310, which is bisected by a semiconductor layer311. In an exemplary case, the semiconductor substrate310can include silicon and the semiconductor layer311can include silicon germanium. The semiconductor substrate310has an uppermost surface312. The initial structure301further includes nanosheet layers314, which are made up of interleaved layers of differing semiconductor materials (i.e., silicon and silicon germanium), dummy gate structures315disposed on an uppermost layer of the nanosheet layers314and bottom dielectric isolation (BDI)316. The BDI316is interposed between the uppermost surface312and a lowermost layer of the nanosheet layers314so that the BDI underlies the dummy gate structures315.

Each dummy gate structure315is formed at a distance from a neighboring dummy gate structure315to define S/D regions317between channel regions318.

As shown inFIG.4, a first intermediate structure401of a semiconductor device is provided. The first intermediate structure401results from nanosheet recession, indentation of certain ones of the nanosheet layers314(i.e., the silicon germanium layers), formation of inner spacers410and subsequent formation of a sacrificial placeholder420applied to the initial structure301ofFIG.3. The nanosheet recession, the indentation of the certain ones of the nanosheet layers314(i.e., the silicon germanium layers) and the formation of the inner spacers410give each of the dummy gate structures315a gate-all-around (GAA) nanosheet (NS) FET configuration. It is to be understood, however, that this is not required and that other configurations are possible. For purposes of clarity and brevity, the following description will relate to the case of the dummy gate structures315as being configured as GAA NS FETs. The nanosheet recession exposes the BDI316in a first one3171of the S/D regions317. This allows for the formation of the sacrificial placeholder420in the first one3171of the S/D regions3171by depositional processing for example.

As shown inFIG.5, a second intermediate structure501of a semiconductor device is provided following several processing operations applied to the first intermediate structure401ofFIG.4. The several processing operations can include, but are not limited to, growth of primary source/drain (S/D) epitaxy510in a second one3172of the S/D regions and over the sacrificial placeholder420in the first one3171of the S/D regions317, deposition of interlayer dielectric (ILD)520and chemical mechanical polishing (CMP) of the ILD520. The several processing operations can further include dummy gate replacement with high-k metal gate material530, middle-of-line (MOL) formation to form a frontside contact540disposed in contact with the primary S/D epitaxy510in the second one3172of the S/D regions317, back-end-of-line (BEOL) formation to form a BEOL layer550disposed in contact with the frontside contact540and bonding of a carrier wafer560to the BEOL layer550.

The dummy gate structures315(seeFIG.3) are thus reconfigured as FET (nFET or pFET) structures570.

As shown inFIG.6, a third intermediate structure601of a semiconductor device is provided following removal of the substrate310(seeFIG.3), deposition of backside ILD610, CMP of the backside ILD610and removal of the sacrificial placeholder420(seeFIG.4) applied to the second intermediate structure501ofFIG.5. The removal of the sacrificial placeholder420leaves an opening620in the backside ILD610, which exposes a lowermost surface of the primary S/D epitaxy510in the first one3171of the S/D regions317. The opening620has an initial width of W1.

As shown inFIG.7, a fourth intermediate structure701of a semiconductor device is provided following enlargement or widening of the opening620to have an enlarged width W2, growth of backside trench S/D epitaxy710and deposition of sacrificial spacers720applied to the third intermediate structure601ofFIG.6. The backside trench S/D epitaxy710is disposed in contact with the primary S/D epitaxy510in the first one3171of the S/D regions317and extends from a plane P of the BDI316and below the plane P of the BDI316and into the opening620. The deposition of the sacrificial spacers720forms the sacrificial spacers720in a periphery of the opening620such that the sacrificial spacers720define an aperture730which exposes a central portion of the backside trench S/D epitaxy710.

As shown inFIG.8, a fifth intermediate structure801of a semiconductor device is provided following epitaxial gouging into the backside trench S/D epitaxy710and the primary S/D epitaxy510via the aperture730(seeFIG.7) in the first one3171of the S/D regions317to form a contact opening810and removal of the sacrificial spacers720(seeFIG.7) applied to the fourth intermediate structure701ofFIG.7. The gouging into the backside trench S/D epitaxy710and the primary S/D epitaxy510in the first one3171of the S/D regions317can be executed to form the contact opening810with a maximum diameter D1that is smaller than a corresponding diameter D2of the backside trench S/D epitaxy710and the primary S/D epitaxy510. In addition, the gouging into the backside trench S/D epitaxy710and the primary S/D epitaxy510can be executed to form the contact opening810to have a V-shape811or a U-shape812or another similar shape.

As shown inFIG.9, a final structure901of a semiconductor device is provided following formation of a backside contact910in the first one3171of the S/D regions317by metallization and formation of a backside power rail920, which is disposed in contact with the backside contact910, and a backside power distribution network (BSPDN)930applied to the fifth intermediate801structure ofFIG.8. The backside power rail920is thus communicative with the backside trench S/D epitaxy710and the primary S/D epitaxy510via the backside contact910in the first one3171of the S/D regions317.

The final structure901therefore includes the BSPDN930, the backside power rail920, the FET structures570having S/D regions317(i.e., the first one3171of the S/D regions317and the second one3172of the S/D regions317) between channel regions318(seeFIG.3), the primary S/D epitaxy510disposed in each of the first one3171of the S/D regions317and the second one3172of the S/D regions317and the backside contact910as well as the BDI316underlying the channel regions318and the backside trench S/D epitaxy710. The backside trench S/D epitaxy710is interposed between the primary S/D epitaxy510and the backside contact910and extends from the plane P of the BDI316and below the plane P of the BDI316. The backside contact910is disposed in contact with the backside power rail920and the BSPDN930at a lower end thereof and in contact with the backside trench S/D epitaxy710and the primary S/D epitaxy510at an upper end thereof in the first one3171of the S/D regions317. The final structure901further includes the carrier wafer560, the BEOL layer550underlying the carrier wafer560and the frontside contact540, which is disposed in contact with the primary S/D epitaxy510in the second one3172of the S/D regions317(seeFIG.3) and the BEOL layer550.

In greater detail, the backside contact910includes a base portion911and a gouging portion912extending from the base portion911and into and through the backside trench S/D epitaxy712and into the primary S/D epitaxy510in the first one3171of the S/D regions317. The gouging portion912has the maximum diameter D1that is smaller than the corresponding diameter D2of the backside trench S/D epitaxy710and the primary S/D epitaxy510. In accordance with one or more embodiments of the present invention, the gouging portion912of the backside contact910gouging into and through the backside trench S/D epitaxy710and into the primary S/D epitaxy510can have a V-shape911or a U-shape912or another similar shape.

The term “conformal” (e.g., a conformal layer) means that the thickness of the layer is substantially the same on all surfaces, or that the thickness variation is less than 15% of the nominal thickness of the layer.