Detecting special handling metadata using address verification

Exemplary methods, apparatuses, and systems include receiving a read request directed to an addressable unit of memory. The read request includes an address for the addressable unit and the addressable unit includes a metadata portion. A mismatch between one or more bits of the address in the read request and a corresponding one or more bits of an address verification value in the metadata portion of the addressable unit is detected. A position of each of the one or more bits that did not match is determined to be an indication of special handling for the addressable unit of memory. In response to the indication of special handling, special handling metadata for the addressable unit of memory is read and the read request is processed according to the special handling metadata.

TECHNICAL FIELD

The present disclosure generally relates to managing metadata in a memory subsystem, and more specifically, relates to detecting special handling metadata using address verification.

BACKGROUND ART

DETAILED DESCRIPTION

A memory device can be a non-volatile memory device. A non-volatile memory device is a package of one or more dice. One example of non-volatile memory devices is a negative-and (NAND) memory device. Other examples of non-volatile memory devices are described below in conjunction withFIG. 1. The dice in the packages can be assigned to one or more channels for communicating with a memory subsystem controller. Each die can consist of one or more planes. Planes can be grouped into logic units (LUN). For some types of non-volatile memory devices (e.g., NAND memory devices), each plane consists of a set of physical blocks, which are groups of memory cells to store data. A cell is an electronic circuit that stores information.

Depending on the cell type, a cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1”, or combinations of such values. There are various types of cells, such as single-level cells (SLCs), multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs). For example, a SLC can store one bit of information and has two logic states.

Typical memory subsystems can contain host data that are subject to special handling. Often this occurs when the data size as managed by a host system does not match the data size as managed by the media of the memory subsystem. For example, a memory subsystem with a 4-kilobyte media data size will mismatch with a host having a data size of 512 bytes. The memory subsystem resolves this mismatch by storing eight host data structures (e.g., 512-byte sectors) within one media data structure (e.g., a 4-kilobyte translation unit or transfer unit (TU)). A typical memory subsystem media data structure stores metadata along with each media data structure. This metadata includes a copy of the logical block address (LBA) mapped to the media data structure as an address verification value as well as special handling indicators for the host data structures stored therein.

A host data structure can be subject to special handling, for example, when the host data structure has been deallocated, been subject to a prior ECC error, or remains unwritten. In such scenarios, while the host data structure is stored in a media data structure that can otherwise contain host data structures that do not require special handling, the presence of a single host data structure subject to special handling means the memory subsystem cannot simply read and return the contents of the entire media data structure to the host (or another operation that would return at least that host data structure). Managing each host data structure separately for the possibility of special handling increases the amount of metadata that the memory subsystem tracks and processes.

Conventional memory subsystems verify the LBA (e.g., a 4-byte address value) as a data integrity check. Because the memory system performs this comparison for every media data structure read, the comparison of the LBA in the read request with the address verification value stored in metadata is typically preformed using an address verifier in the hardware data path. In contrast, conventional memory subsystems check other metadata (e.g., 12 bytes of special handling indicators) with firmware. As a result, special handling metadata consumes space within the memory subsystem that cannot be used for storing other metadata or host data. Additionally, processing each read request for special handling includes examining the metadata (e.g., with firmware), which can significantly contribute to read latency.

Aspects of the present disclosure address the above and other deficiencies by detecting special handling metadata using the existing address verification process. When creating the metadata for a host data structure, embodiments flip one or more bits of the LBA to create a masked LBA (i.e., the address verification value) as an indication of special handling for the host data structure. When the memory subsystem reads the host data structure, the address verifier will indicate there is an error in the metadata associated with the host data structure when the LBA and masked LBA do not match. In response to the mismatch, the memory subsystem can determine if a bitmap for special handling metadata indicators matches the bit flip pattern of the LBA-masked LBA mismatch (i.e., the positions of bits that do not match). If the one or more positions within the bitmap match the bit flip pattern of the LBA-masked LBA mismatch, the memory subsystem has determined that a host data structure is subject to special handling. As a result of using an existing hardware check of the LBA, embodiments reduce instances of the firmware processing metadata associated with a host data structure to look for special handling indicators and, in turn, decrease read operation latency for media data structures that do not include host data structures that are subject to special handling.

Additionally, embodiments can map bit flip patterns in the LBA-masked LBA mismatches to locations of special handling metadata or instructions. For example, different patterns of flipped bits can be associated with different host data structures. The location of flipped bits in the masked LBA can, therefore, be mapped to a location of the one or more host data structures (e.g. sectors) within the media data structure that are subject to special handling. Because host data structures that are subject to special handling do not store data that is simply read and returned, special handling metadata (e.g., confirming special handling or identifying a special handling type) and any special handling details can be stored in the mapped host data structures that are subject to special handling. As a result of storing special handling metadata in the unused host data structures, the corresponding space in the metadata portion of each media data structure can be freed for other uses (e.g., up to 12 bytes per media data structure following the example above), such as an increase in error-correcting code metadata, an increase in addressable space (e.g., giving an additional byte to the LBA), and/or a reduction in page size.

A memory subsystem controller115(or controller115for simplicity) can communicate with the memory devices130to perform operations such as reading data, writing data, or erasing data at the memory devices130and other such operations (e.g., in response to commands scheduled on a command bus by controller115). The memory subsystem controller115can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller115can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

The memory subsystem110includes an operation manager113that can detect special handling metadata using address verification. In some embodiments, the controller115includes at least a portion of the operation manager113. For example, the controller115can include a processor117(processing device) configured to execute instructions stored in local memory119for performing the operations described herein. In some embodiments, the operation manager113is part of the host system110, an application, or an operating system.

The memory subsystem110further includes an address verifier114to compare an address included in a read operation/request with an address verification value stored in metadata associated with the corresponding memory location in a memory device130. In some embodiments, the address verifier114is implemented as a portion of the hardware data path used in reading data from a memory device130. For example, the memory subsystem110can include a digital comparator to serve as the address verifier114. The comparison of the read operation address with the address verification value is performed faster by hardware than by firmware/software.

The operation manager113can flip one or more bits of the LBA to create a masked LBA (i.e., the address verification value) as an indication of special handling for the host data structure. When the address verifier114flags an LBA mismatch error, the operation manager113can determine if the mismatch is the result of a bit flip pattern that indicates special handling. In some embodiments, the operation manager113uses the bit flip pattern to locate special handling metadata, instructions, or other information related to the special handling. Further details with regards to the operations of the operation manager113are described below.

FIG. 2illustrates an example of the organization of data and metadata in accordance with some embodiments of the present disclosure. The memory subsystem110stores data, e.g., within memory devices130, in a hierarchical organization structure. A page200can refer to physical unit of data written to memory. In some embodiments, a page200represents the smallest writeable unit of memory within a memory device130.

The illustrated page200is divided into multiple individually addressable units, TU's205. Each TU205represents an addressable media data structure. As one example, a TU205can store approximately 4 kilobytes of data and corresponding metadata.

When a host data structure is smaller than a media data structure, the memory subsystem110can store multiple host media structures within a single media data structure. For example, each TU205is divided into multiple sectors210. Continuing the example above, a TU205can include eight 512-byte sectors210. Sectors210store host data, e.g., when not subject to special handling.

Each TU205further includes a metadata portion215. The metadata215can include error-correcting code (ECC) data220and a masked LBA225. The masked LBA225serves as an address verification value. For example, when one or more sectors210within a TU205are subject to special handling, the operation manager113can flip one or more bits of the address corresponding to the TU205. The resulting masked LBA225is stored within the metadata215as an indication of special handling for the corresponding one or more sectors210. The creation and utilization of masked LBA's225is described in additional detail with reference toFIG. 3-D.

In one embodiment, the metadata215further includes special handling metadata. For example, special handling metadata can identify whether a sector210has been deallocated, been subject to a prior ECC error, remains unwritten, or is otherwise subject to special handling. Each scenario can trigger, e.g., in response to a read request, a different type of special handling procedure for the memory subsystem110. In another embodiment, the memory subsystem110stores the special handling metadata within the corresponding sector210that is subject to special handling. As described further with reference toFIG. 3-D, the pattern of flipped bits in the masked LBA225can indicate which sector(s)210are subject to special handling and, accordingly, where to find the special handling metadata.

At operation305, the processing device identifies an addressable unit of memory to be subject to special handling. For example, the processing device identifies sectors210that have been deallocated, been subject to a prior ECC error, or remain unwritten as being subject to special handling. In one embodiment, the processing device identifies unwritten sectors210subject to special handling in response to an initial power-on, creation of an address translation table, or similar event. In one embodiment, the processing device identifies addressable units subject to special handling in response to a trigger event, e.g., when a sector210triggers an ECC error or is deallocated.

At operation310, the processing device applies a special handling bitmap mask to flip one or more bits of an address verification value for the addressable unit of memory that is subject to special handling. For example, the processing device can use a mask or other bitmap pattern to selectively flip the value of one or more bits within the copy of the LBA used as an address verification value to create a masked address verification value (e.g., masked LBA225). In one embodiment, the mask is a sequence of binary values in which 0's represent bits that will remain and l's represent bits to be flipped. The processing device can exclusive-OR (XOR) this mask with the LBA to flip the corresponding bits and create the masked LBA value.

In one embodiment, there are multiple masks and the processing device selects a mask based upon the type of special handling and/or location of the sector subject to special handling within the TU. In an embodiment including N sectors within a TU, the processing device can use a mask to flip one or more bits in any of N bit positions to indicate which of the N sectors (alone or in combination) are subject to special handling. Similarly, the processing device can use a mask to flip one or more bits in any of log2N bit positions to indicate which single sector within the N sectors is subject to special handling. The special handling information for that sector (e.g., as stored within the data portion of that sector) can include an indication of any other sectors within the TU that are also subject to special handling. Other embodiments use different numbers of flipped bits. For example, the processing device can flip multiple bits per sector subject to special handling to avoid false indications of special handling due to bit errors.

At operation315, the processing device stores the masked address verification value in the metadata for the addressable unit of memory. For example, when writing a TU205as a part of a page200to a memory device130, the processing device writes the masked address verification value within metadata215. In one embodiment, the processing device also stores special handling metadata along with the masked address verification value in the metadata portion of the addressable unit of memory. For example, when the masked address verification value only indicates the presence of a sector subject to special handling (e.g., but not the location of that sector or the type of special handling), the processing device can include an indicator of the location of the sector in question and/or the type of special handling in the metadata215portion of the TU205.

At operation320, the processing device optionally writes special handling metadata and/or information to the data portion of the addressable unit that is subject to special handling. For example, in addition to or instead of writing special handling metadata to the metadata215portion of the TU205, the processing device stores special handling metadata and/or other information in the sector210subject to special handling. The processing device can write an indicator of special handling to the sector210(e.g., to confirm that the sector210is subject to special handling), an indicator of the type of special handling, instructions or information used in processing the special handling, etc. In one embodiment, the processing device writes an error message or code to deliver to a host device as special handling information.

FIG. 4is a flow diagram of an example method400to detect special handling metadata using address verification in accordance with some embodiments of the present disclosure. The method400can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method400is performed by the operation manager113ofFIG. 1. Although shown in a particular sequence or order, unless otherwise specified, the order of the processes can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

At operation405, the processing device receives a read request including an address for the addressable unit of memory. For example, the processing device can receive a read request from a host system120, the read request including an LBA that maps to a TU205within a memory device130.

At operation410, the processing device determines whether the LBA and address verification value match or not. As described above, the processing device can take advantage of a hardware address verifier114in the read path to obtain a result of this comparison. In one embodiment, the processing device receives a simple indication of match or mismatch, such as a single bit, from the address verifier114. In another embodiment, the processing device receives an output from the address verifier114that indicates each bit position in the address verification value that does not match with the LBA. For example, the address verifier114can output the result of an XOR operation performed on both the address verification value and the LBA, the result including bits set to zero for bit positions that match and set to one for bit positions that do not match.

If the LBA and address verification value match, at operation415, the processing device fulfills the read request without any special handling. For example, the processing device can read the TU205and return the data of one or more of the sectors210within that TU205to the host system120. In one embodiment, the processing device triggers a direct memory access (DMA) operation to fulfill the read request.

If the LBA and address verification value do not match, at operation420, the processing device determines if the bits that resulted in the mismatch are in bit positions that correspond to a special handling bitmap mask. If the address verifier114provides an indication of mismatch that includes bit positions that do not match, the processing device can compare the mismatched bit positions to one or more bitmap masks. If the address verifier114does not provide an indication that includes mismatching bit positions, the processing device can compare the LBA and address verification, e.g., using an XOR operation as described above. In one embodiment, the processing device compares the mismatching bit positions with one or more bitmap masks using an XOR operation for each comparison. A match between flipped bits in the address verification value and a bitmap mask indicates that the TU205includes one or more sectors210that are subject to special handling.

If the mismatching bit positions do not match a special handling bitmap mask, at operation425, the processing device performs a read error process. The lack of a matching mask indicates that, instead of special handling, the mismatch has resulted from a corruption of the metadata for the TU205, an error in an address translation table, or another error.

If the mismatching bit positions match a special handling bitmap mask, at operation430, the processing device flips the mismatching bits to restore the address to an unmasked state. For example, the processing device can perform an XOR operation between the address verification value and the matching special handling bitmap mask to return the address to an original state. The processing device can then request that the address verifier114retry the comparison between the address of the received read request and the restored address verification value to, e.g., enable a read of the memory device130.

At operation435, the processing device determines if the address of the received read request and the restored address verification value now result in a match. If the address verifier114indicates another mismatch, the processing device performs the read error process at operation425.

If the address verifier114indicates a match between the address of the received read request and the restored address verification value (or if the processing device bypasses operations430-435), at operation440, the processing device reads the special handling metadata for the corresponding one or more sectors210. As described above, the special handling metadata can confirm which sector(s) are subject to special handling, indicate what type of special handling to apply, or other information about the special handling. In one embodiment, the special handling metadata is stored in the metadata portion215of the TU205. In such an embodiment, the processing device parses the metadata215and reads the special handling metadata stored therein. In another embodiment, the special handling metadata is stored within one or more sectors210and the matching special handling bitmap mask maps to or otherwise indicates which sectors210are subject to special handling and, accordingly, store special handling metadata. Additionally, sectors210subject to special handling do not store host data and can instead store special handling instructions or other information to enable the processing device to fulfill the read request according to the corresponding special handling.

In one embodiment, the special handling metadata is encrypted or otherwise protected to ensure the integrity of the special handling process. In such an embodiment, the processing device decrypts the special handling metadata as a part of the process of reading the special handling metadata.

At operation445, the processing device fulfills the read request with the corresponding special handling process. For example, the processing device can deliver an error message to the host system120, such as an error message stored in the corresponding sector210, or trigger another response to the read request directed to a sector that is subject to special handling.

At operation505, the processing device receives a read request including an address for the addressable unit of memory. As described with reference to operation405above, the processing device can receive a read request from a host system120and the read request includes an LBA that maps to a TU205within a memory device130.

At operation510, the processing device detects a mismatch between the address in the read request and the corresponding address verification value stored in the metadata portion of the addressable unit of memory. As described above with reference to operation410, the processing device can utilize the address verifier114to detect the mismatch.

At operation515, the processing device determines the bit positions of flipped/mismatching bits between the address and the address verification value indicate the addressable unit of memory is subject to special handling. As described above with reference to operation420, the processing device can use an XOR or similar comparison operation to determine that a special handling bitmap mask matches the pattern of mismatching bits in the address verification value.

At operation520, the processing device reads the special handling metadata in response to detecting the indication of special handling. As described above with reference to operation440, the processing device can read special handling metadata from the metadata portion215of the TU205or from the sector210subject to special handling.

At operation525, the processing device processes the read request according to the special handling metadata. As described above with reference to operation445, the processing device can deliver an error message to the host system120, such as an error message stored in the corresponding sector210, or trigger another response to the read request directed to a sector that is subject to special handling.