Charge pump for intermediate voltage

A charge pump generates a voltage higher than an intermediate voltage and a regulator circuit provides a first regulated voltage higher than the intermediate voltage. A second stage includes a regulator stage using the first voltage to provide the intermediate voltage from the first voltage. A charge pump provides a pump output voltage. The pump output voltage is divided and the divided voltage is presented to a first comparator that compares it with a reference voltage. The first comparator drives the gate of a first MOS transistor to regulate the pump output voltage to a regulated voltage related to the reference voltage. The regulated voltage is presented to a second comparator that compares it with the reference voltage. The second comparator drives the gate of a second MOS transistor to downconvert the regulated output voltage to an intermediate voltage related to the reference voltage.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to integrated circuit technology and to charge pump circuits for use in integrated circuits. More particularly, the present invention relates to charge pump circuits for providing intermediate voltage potentials in integrated circuits.

2. The Prior Art

Charge pump circuits are known for providing both positive and negative voltage potentials in integrated circuits. It is, however, difficult to generate charge pump voltages that are slightly above the supply voltage because of the nature of charge pump circuits.FIG. 1shows a typical prior-art Dickson charge pump circuit in which three diodes10,12, and14are connected in series between an input node16and an output node18. A clock signal drives a first node20common to the cathode of diode10and the anode of diode12through a capacitor22. The clock signal is inverted through inverter24and the inverted clock signal drives a second node26common to the cathode of diode12and the anode of diode14through a capacitor28.

As will be appreciated by persons of ordinary skill in the art, each clock pulse will drive the output node18up by an amount of voltage roughly equal to VDD−Vt, where VDDis the supply voltage and Vtis the threshold voltage of the diodes. If VDDis 3V, Vtis 1V, every clock cycle will drive the output node18up by 3V−1V=2V. If it is desired to regulate the output voltage to 4.5V, there will be a temporary overshoot to 5V, resulting in a very noisy output voltage. This can be avoided by providing fast regulation at the expense of drawing a lot of power or by providing a large capacitor on the output of the regulator. Both of these solutions are less than desirable.

BRIEF DESCRIPTION OF THE INVENTION

According to the present invention, a charge pump circuit for providing an intermediate voltage has two stages. A first stage includes a charge pump that generates a voltage higher than the intermediate voltage and a regulator circuit that provides a first regulated voltage higher than the intermediate voltage. A second stage includes a downconverter circuit that provides the intermediate voltage from the first voltage.

In one exemplary embodiment of the present invention, a charge pump provides a pump output voltage. The pump output voltage is divided and the divide voltage is presented to a first comparator that compares it with a reference voltage. The first comparator drives the gate of a first MOS transistor to regulate the pump output voltage to a regulated voltage related to the reference voltage. The regulated voltage is presented to a second comparator that compares it with the reference voltage. The second comparator drives the gate of a second MOS transistor to downconvert the regulated output voltage to an intermediate voltage related to the reference voltage.

DETAILED DESCRIPTION OF THE INVENTION

Persons of ordinary skill in the art will realize that the following description of the present invention is illustrative only and not in any way limiting. Other embodiments of the present invention will readily suggest themselves to such skilled persons.

Referring now toFIG. 2, a schematic diagram shows an illustrative circuit30for providing an intermediate voltage according to the present invention. A charge pump circuit32generates a first voltage higher than the intermediate voltage. As a non-limiting example, in an integrated circuit having a VDDsupply voltage of 3V, it is desired to generate a voltage of 4.5V. In such a case, the charge pump circuit32may be configured to output a voltage of 7V.

A regulator circuit includes comparator34, having the output of charge pump32on line36coupled to its inverting input through a voltage divider including resistors38and40and having a reference voltage coupled to its non-inverting input. Comparator34may be powered from the VDDsupply. The output of comparator34is coupled to the gate of n-channel MOS transistor42.

For example, if the reference voltage is chosen to be 1V and the ratio of the values of resistors38and40is 6:1, the comparator34will change state when the output voltage of the charge pump32on line36exceeds 7V, thus turning on n-channel MOS transistor42as will be appreciated by persons of ordinary skill in the art. Thus, the voltage on line36is regulated at 7V.

The regulated voltage at line36is used to provide the power to second comparator44. The second comparator44is powered from the regulated voltage on line36. The non-inverting input of second comparator44is coupled to the reference voltage. The inverting input of second comparator44is coupled to a voltage divider including resistors46and48, connected in series between the source of n-channel MOS transistor50and ground. N-channel MOS transistor50is configured as a source follower. The gate of n-channel MOS transistor50is driven by the output of second comparator44and its drain is coupled to the regulated voltage line36. The output of the circuit is line52at the source of n-channel MOS transistor50.

The ratio of the values of resistors46and48is chosen to produce the desired output at output node52. As an example, if an output voltage of 4.5V is desired, the ratio of resistors46and48should be chosen to be 3.5:1. By powering the comparator44from the regulated voltage on line36, the downconverter circuit has power supply noise rejection.

By employing the circuit of the present invention the presence of charge pump overshoot noise on the output is prevented. The present invention allows generation of intermediate voltage levels, which are sufficiently close to the VDDsupply voltage that would otherwise introduce unacceptable noise into the power supply potential.