Dual-gate CMOS semiconductor device and dual-gate CMOS semiconductor device manufacturing method

A manufacturing method for a dual-gate CMOS semiconductor device that suppresses mutual diffusion of P type impurities and N type impurities in a gate electrode. An NMOS part and a PMOS part are formed on a semiconductor substrate. A polycrystalline silicon layer is formed on the NMOS part and the PMOS part, and consists of an N type impurity containing polycrystalline silicon layer and a P type impurity containing polycrystalline silicon layer. A first conductive layer is formed on the polycrystalline silicon layer so as to include a groove region, in which the first conductive layer is not formed, on a predetermined region including a boundary between the N type impurity containing polycrystalline silicon layer and the P type impurity containing polycrystalline silicon layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a dual-gate CMOS semiconductor device and a dual-gate CMOS semiconductor device manufacturing method. More specifically, the present invention relates to a dual-gate CMOS semiconductor device and a dual-gate CMOS semiconductor device manufacturing method capable of reducing the mutual diffusion of impurities in a gate electrode.

2. Description of Related Art

In recent years, CMOS semiconductor devices of a dual-gate structure have been adopted with a view of improving performance and reducing power consumption. As the gate electrodes of this dual-gate structure, a polycrystalline silicon layer containing N type impurities such as arsenic is used on an NMOS part and a polycrystalline silicon layer containing P type impurities such as boron is used on a PMOS part.

The semiconductor device of such a dual-gate structure is disclosed by, for example, “M. Togo, et al., Thermal Robust Dual-Gate CMOS Integration Technologies for High-Performance DRAM-Embedded ASCIs', IEDM Technical Digest, p. 49 (1999)”.

According to the above-cited document, a so-called W polyside structure in which a WSi2 layer is built up on a polycrystalline silicon layer, is used as a gate electrode. This gate electrode is normally employed in a device having a mixture of a DRAM and Logic. In addition, for the purpose of realizing higher integration, a so-called SAC structure for providing contacts on a source/drain layer in a self-aligned manner to a gate electrode by forming a nitride film on the WSi2 layer and also forming a nitride film on a sidewall.

The conventional dual-gate CMOS semiconductor device, however, has the following disadvantages. A heat treatment is conducted to form elements after the formation of a gate electrode. Due to this, impurities contained in a polycrystalline silicon layer on an NMOS part and those contained in a polycrystalline silicon layer on a PMOS part are mutually diffused through the WSi2 layer. In other words, N type impurities are introduced into the polycrystalline silicon layer on the PMOS part and P type impurities are introduced into the polycrystalline silicon layer on the NMOS part, with the result that the performance of the semiconductor device disadvantageously deteriorates.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide a novel, improved dual-gate CMOS semiconductor device and a manufacturing method therefor capable of suppressing the mutual diffusion of P type impurities and N type impurities in polycrystalline silicon layers on a gate electrode.

To obtain the above object, a typical invention of the present invention provides a dual-gate CMOS semiconductor device characterized by comprising: an NMOS part and a PMOS part formed on a semiconductor substrate; and a gate electrode formed on the NMOS part and the PMOS part, and constituted out of a polycrystalline silicon layer and a first conductive layer, and characterized in that the polycrystalline silicon layer is constituted out of a polycrystalline silicon layer containing N type impurities and a polycrystalline silicon layer containing P type impurities; and the first conductive layer has a groove region on a predetermined region including a boundary between the polycrystalline silicon layer containing the N type impurities and the polycrystalline silicon layer containing the P type impurities, the first conductive layer not being formed in the groove region.

According to the above-stated invention, the first conductive layer on the PMOS part and the first conductive layer on the NMOS part are isolated from each other by the formation of the groove region. It is, therefore, possible to reduce the mutual diffusion of the P type impurities and the N type impurities in the polycrystalline silicon layers.

Furthermore, to obtain the above object, another typical invention of the present application provides a dual-gate CMOS semiconductor device manufacturing method characterized by: forming a P well and an N well on a semiconductor substrate using a first masking pattern; forming a gate insulating film on the P well and the N well formed on the semiconductor substrate; forming a polycrystalline silicon layer constituted out of a polycrystalline silicon layer containing N type impurities and a polycrystalline silicon layer containing P type impurities, on the gate insulating film; forming a first conductive layer on an entire surface on the polycrystalline silicon layer; removing the first conductive layer on a predetermined region including a boundary between the polycrystalline silicon layer containing the N type impurities and the polycrystalline silicon layer containing the P type impurities while using a second masking pattern, and thereby forming a groove region; forming a gate electrode by a photolithographic method and an etching method; and forming a source/drain layer on each of the P well and the N well by the photolithographic method and an ion implantation method, after forming the gate electrode.”

The above-stated invention can provide a semiconductor device wherein the first conductive layer on the PMOS part is isolated from the first conductive layer on the NMOS part by a boundary portion. As a result, it is possible to reduce the mutual diffusion of the P type impurities and the N type impurities in the polycrystalline silicon layers through the first conductive layers.

DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION

The prefer embodiments of the present invention will be described hereinafter in detail with reference to the accompanying drawing. It is noted that constituent elements having the same functions and constitutions are denoted by the same reference symbols in the description given hereinafter and the drawings and repetitive description will not be given.

In the first embodiment, differently from the conventional semiconductor device, a groove region is formed in a WSi2 layer (or tungsten silicide layer) on a boundary region between an NMOS part and a PMOS part to thereby isolate the WSi2 layer on the NMOS part from the WSi2 layer on the PMOS part.

The constitution of a semiconductor device in the first embodiment will be described with reference to FIG.1.FIG. 1Ais a top view showing the constitution of the semiconductor device in the first embodiment.FIG. 1Bis a cross-sectional view taken along line a-a′ ofFIG. 1A, showing the constitution of the semiconductor device in this embodiment.FIG. 1Cis a cross-sectional view taken along line b-b′ ofFIG. 1A, showing the constitution of the semiconductor device in this embodiment.

First, as shown inFIG. 1, an element isolation insulating film102is formed on a silicon substrate101by, for example, an STI method. Impurities are injected into an NMOS part and a PMOS part by a photolithographic method and an implantation method so as to form a P well103and an N well104, respectively. Also, source/drain layers110are formed on the P well103and N well104, respectively by the photolithographic method and the implantation method.

A gate oxide film105is formed on the P well103and the N well104by, for example, a thermal oxidization method and polycrystalline silicon layers106and107are deposited on the gate oxide film105. N type impurities such as arsenic are injected into the polycrystalline silicon layer on the NMOS part and P type impurities such as boron are injected into the polycrystalline silicon layer on the PMOS part by, for example, the photolithographic method and the implantation method, thereby forming an N+polycrystalline layer106and a P+polycrystalline layer107, respectively.

The first conductive layer108such as a WSi2 layer is formed on the polycrystalline silicon layers106and107by, for example, a sputtering method or a CVD method. In this embodiment, differently from the conventional semiconductor device, a groove region120is formed in the WSi2 layer108on the boundary region between the NMOS part and the PMOS part, thereby isolating the WSi2 layer108on the NMOS part from the WSi2 layer108on the PMOS part.

In addition, a gate electrode109is formed by the photolithographic method and the etching method and an oxide film111is formed on the gate electrode109by, for example, the CVD method. Further, a contact112is formed on the source/drain layer110and a contact113is formed on the gate electrode109.

In this embodiment, the WSi2 layer108on the NMOS part is isolated from the WSi2 layer108on the PMOS part by forming the groove region120, it is possible to reduce the mutual diffusion of the P type impurities and the N type impurities in the polycrystalline silicon layers through the WSi2 layers.

Next, referring toFIG. 2, a method of manufacturing the semiconductor device in the first embodiment will be described.FIG. 2is a cross-sectional view for manufacturing steps showing the semiconductor method manufacturing method in this embodiment.

First, as shown inFIG. 2A, an element isolation insulating film102is formed on a silicon substrate101by, for example, the STI method so as to isolate elements. Then, impurities are injected into an NMOS part and a PMOS part, respectively, by the photolithographic method and the implantation method to thereby form a P well103and an N well104, respectively.

Next, after forming a gate oxide film105on the entire surface by, for example, the thermal oxidization method, polycrystalline silicon layers106and107are deposited on the gate oxide film105. Further, arsenic and boron are injected into the polycrystalline silicon layers106and107on the NMOS part and the PMOS part, respectively, by the photolithographic method and the implantation method and activated by a heat treatment, thereby forming a polycrystalline silicon layer consisting of an N+polycrystalline silicon layer106and a P+polycrystalline silicon layer107. Further, a WSi2 layer108is deposited on the entire surface by, for example, the sputtering method or CVD method.

Thereafter, as shown inFIG. 2B, the WSi2 layer108on the boundary portion between the NMOS part and the PMOS part is removed by, for example, the photolithographic method or etching method to form a groove region120. It is noted that mask data used by this photolithographic method or the like can be created by synthesizing mask data used in the well formation step.

Next, as shown inFIG. 2C, a gate electrode109is formed by, for example, the photolithographic method and the etching method and source/drain layers110are formed on the P well103and the N well104, respectively by, for example, the photolithographic method and the implantation method. Then, an oxide film111is deposited on the entire surface by, for example, the CVD method and contacts112and113are formed on the source/drain layer110and the gate electrode109, respectively by, for example, the photolithographic method and the etching method.

In this embodiment, the groove region is formed in the WSi2 layer on the boundary region between the NMOS part and the PMOS part, and the WSi2 layer on the NMOS part is isolated from the WSi2 layer on the PMOS part. This can reduce the mutual diffusion of the N type impurities and the P type impurities in the polycrystalline silicon layer through the WSi2 layers.

In the first embodiment stated above, description has been given to a case where the groove region is formed in the WSi2 layer on the boundary region between the NMOS part and the PMOS part and where the WSi2 layer on the NMOS part and the WSi2 layer on the PMOS part are isolated from each other. In the second embodiment, a CoSi2 layer (or cobalt silicide layer) having a low impurity diffusion coefficient and high conductivity is formed on a polycrystalline silicon layer on the bottom of a groove region on the first conductive layer.

Now, the constitution of a semiconductor device in the second embodiment will be described with reference to FIG.3.FIG. 3Ais a top view showing the constitution of the semiconductor device in the second embodiment.FIG. 3Bis a cross-sectional view taken along line a-a′ ofFIG. 3A, showing the constitution of the semiconductor device in this embodiment.FIG. 3Cis a cross-sectional view taken along line b-b′ ofFIG. 3A, showing the constitution of the semiconductor device in this embodiment.

First, as shown inFIG. 3, an element isolation insulating film202is formed on a silicon substrate201by, for example, the STI method. Impurities are injected into an NMOS part and a PMOS part, respectively by, for example, the photolithographic method and the implantation method, thereby forming a P well203and an N well204, respectively. Also, a source/drain layer210is formed on each of the P well203and the N well204by, for example, the photolithographic method and the implantation method.

A gate oxide film205is formed on the entire surface on the P well203and the N well204by, for example, the thermal oxidization method. Polycrystalline silicon layers206and207are deposited on the gate oxide film205. N type impurities such as arsenic are injected into the polycrystalline silicon layer206on the NMOS part and P type impurities such as boron are injected into the polycrystalline silicon layer207on the PMOS part by, for example, the photolithographic method and the implantation method, thereby forming an N+polycrystalline silicon layer206and a P+polycrystalline silicon layer207, respectively.

The first conductive layer208such as a WSi2 layer is formed on the polycrystalline silicon layers206and207by, for example, the sputtering method or the CVD method. Also, a groove region220is formed on the boundary portion between the NMOS part and the PMOS part to thereby isolate the WSi2 layer208on the NMOS part from the WSi2 layer208on the PMOS part as in the case of the first embodiment. Further, a gate electrode209is formed by the photolithographic method and the etching method and an oxide film211is formed on the gate electrode209by, for example, the CVD method. Sidewalls221made of nitride films are formed on the side surface of the gate electrode209and the side surface of the groove region220, respectively.

Further, in the second embodiment, differently from the first embodiment, a CoSi2 layer222having a low impurity diffusion coefficient and high conductivity is formed on the polycrystalline silicon layers206and207exposed to the bottom of the groove region. As shown inFIG. 3C, this CoSi2 layer222is also formed on the source/drain layer210.

Contacts212and213are formed on the source/drain layer210and the gate electrode209, respectively.

In this embodiment, differently from the first embodiment, the CoSi2 layer having a low impurity diffusion coefficient and high conductivity is formed on the bottom of the groove region. As a result, it is possible to reduce the mutual diffusion of the P type impurities and the N type impurities in the polycrystalline silicon layers and to prevent more effectively the resistance of the gate electrode from increasing due to the formation of the groove region.

Next, referring toFIG. 4, a method for manufacturing the semiconductor device in the second embodiment will be described.FIG. 4is a cross-sectional view for manufacturing steps showing the semiconductor device manufacturing method in this embodiment. Since the steps (FIGS. 4A and 4B) of the semiconductor device manufacturing method in this embodiment until a groove region is formed are the same as those in the first embodiment (FIGS.2A and2B), no description will be given to these steps herein.

As shown inFIG. 4C, after a WSi2 layer208on the boundary portion between an NMOS part and a PMOS part is removed by the photolithographic method and the etching method to thereby form a groove region220, a gate electrode209is formed by, for example, the photolithographic method and the etching method. A source/drain layer210is then formed on each of a P well203and an N well204by the photolithographic method and the implantation method.

Next, a nitride film is deposited on the entire surface by, for example, the CVD method and then a sidewall221made of a nitride film is formed by the etching method.

After forming a Co (cobalt) layer on the entire surface, a CoSi2 layer222is formed on the source/drain layer through the first heat treatment step for forming silicide, a removal step for removing unreacted Co and the second heat treatment step for forming silicide. At this moment, since the WSi2 layer208is removed on the boundary portion between the NMOS part and the PMOS part, the CoSi2 layer222is formed on the surfaces of the polycrystalline silicon layers206and207on the bottom of the groove region220, as well. In this way, the CoSi2 layer222can be formed in a self-aligned manner by reacting Co to the polycrystalline silicon layers206and207exposed on the bottom of the groove region220and to the source/drain layer210.

Thereafter, an oxide film211is formed on the entire surface by, for example, the CVD method and then contacts212and213are formed on the source/drain layer210and the gate electrode209, respectively by, for example, the photolithographic method and the etching method.

As can be seen from the above, in the second embodiment, it is possible to provide a semiconductor device capable of reducing the mutual diffusion of the P type impurities and the N type impurities in the polycrystalline silicon layers and preventing the resistance of the gate electrode from increasing due to the formation of the groove region.

In the first embodiment stated above, description has been given to a case where the groove region is formed in the WSi2 layer on the boundary region between the NMOS part and the PMOS part and where the WSi2 layer on the NMOS part and the WSi2 layer on the PMOS part are isolated from each other. In the third embodiment, an oxide film almost equal in height to a WSi2 layer is formed in a groove region.

Now, referring toFIG. 5, the constitution of a semiconductor device in the third embodiment will be described.FIG. 5Ais a top view showing the constitution of the semiconductor device in the third embodiment.FIG. 5Bis a cross-sectional view taken along line a-a′ of FIG.5A.FIG. 5Cis a cross-sectional view taken along line b-b′ of FIG.5A.

First, as shown inFIG. 5, an element isolation insulating film302is formed on a silicon substrate301by, for example, the STI method. Impurities are injected into an NMOS part and a PMOS part by the photolithographic method and the implantation method, thereby forming a P well303and an N well304, respectively. Also, a source/drain layer310is formed on each of the P well303and the N well304by the photolithographic method and the implantation method.

A gate oxide film305is formed on the entire surface on the P well303and the N well304by, for example, the thermal oxidization method. Polycrystalline silicon layers306and307are deposited on the gate oxide film305. N type impurities such as arsenic are injected into the polycrystalline silicon layer306on the NMOS part and P type impurities such as boron are injected into the polycrystalline silicon layer307on the PMOS part by, for example, the photolithographic method and the implantation method, thereby forming an N+polycrystalline silicon layer306and a P+polycrystalline silicon layer307, respectively.

The first conductive layer308such as a WSi2 layer is formed on the polycrystalline silicon layers306and307by, for example, the sputtering method or the CVD method. Also, a groove region320is formed in the boundary portion between the NMOS part and the PMOS part to thereby isolate the WSi2 layer308on the NMOS part from the WSi2 layer308on the PMOS part as in the case of the first embodiment.

In the third embodiment, differently from the first embodiment, an oxide film331almost equal in height as the first conductive layer (or WSi2 layer) is formed in the groove region. As a result, no stepped portion is formed on the boundary between the NMOS part and the PMOS part, thus facilitating a fine processing for forming a gate electrode.

In addition, a gate electrode309is formed by the photolithographic method and the etching method and an oxide film311is formed on the gate electrode309by, for example, the CVD method. Further, contacts312and313are formed on the source/drain layer310and the gate electrode309, respectively.

In this embodiment, differently from the first embodiment, the oxide film almost equal in height to the first conductive layer (or WSi2 layer) is formed in the groove region and no stepped portion is formed on the boundary between the NMOS part and the PMOS part. This can reduce the mutual diffusion of the P type impurities and the N type impurities in the polycrystalline silicon layers and facilitate a fine processing for forming the gate electrode.

Next, referring toFIG. 6, a method for manufacturing the semiconductor device in the third embodiment will be described.FIG. 6is a cross-sectional view for manufacturing steps showing the semiconductor device manufacturing method in this embodiment. Since the steps (FIGS. 6A and 6B) of the semiconductor device manufacturing method in this embodiment until a groove region is formed are the same as those in the first embodiment (FIGS.2A and2B), no description will be given to these steps herein.

As shown inFIG. 6C, after a WSi2 layer308on the boundary portion between an NMOS part and a PMOS part is removed by the photolithographic method and the etching method to form a groove region320, an oxide film331is formed on the entire surface by, for example, the CVD method and an oxide film331is formed only in the groove region320by the etching method. Then, a gate electrode309is then formed by the photolithographic method and the etching method and a source/drain layer310is formed on the P well303and the N well304by the photolithographic method and the implantation method.

Thereafter, after an oxide film311is formed on the entire surface by, for example, the CVD method, contacts312and313are formed on the source/drain layer310and the gate electrode309, respectively by the photolithographic method and the etching method.

As can be seen, in this embodiment, differently from the first embodiment, the oxide film almost equal in height to the first conductive layer (or WSi2 layer) is formed in the groove region and no stepped portion is formed on the boundary between the NMOS part and the PMOS part. As a result, it is possible to reduce the mutual diffusion of the P type impurities and the N type impurities in the polycrystalline silicon layers and to facilitate a fine processing for forming the gate electrode because no stepped portion is formed on the boundary between the NMOS part and the PMOS part.

In the first embodiment stated above, description has been given to a case where the groove region is formed in the WSi2 layer in the boundary region between the NMOS part and the PMOS part and where the WSi2 layer on the NMOS part and the WSi2 layer on the PMOS part are isolated from each other. In the fourth embodiment, a nitride film is formed on the entire surface on a WSi2 layer including the interior of a groove region.

Now, referring toFIG. 7, the constitution of a semiconductor device in the fourth embodiment will be described.FIG. 7Ais a top view showing the constitution of the semiconductor device in the third embodiment.FIG. 7Bis a cross-sectional view taken along line a-a′ of FIG.7A.FIG. 7Cis a cross-sectional view taken along line b-b′ of FIG.7A.

First, as shown inFIG. 7, an element isolation insulating film402is formed on a silicon substrate401by, for example, the STI method. Impurities are injected into an NMOS part and a PMOS part by the photolithographic method and the implantation method, thereby forming a P well403and an N well404, respectively. Also, a source/drain layer410is formed on each of the P well403and the N well404by the photolithographic method and the implantation method.

A gate oxide film405is formed on the entire surface on the P well403and the N well404by, for example, the thermal oxidization method. Polycrystalline silicon layers406and407are deposited on the gate oxide film405. N type impurities such as arsenic are injected into the polycrystalline silicon layer406on the NMOS part and P type impurities such as boron are injected into the polycrystalline silicon layer407on the PMOS part by, for example, the photolithographic method and the implantation method, thereby forming an N+polycrystalline silicon layer406and a P+polycrystalline silicon layer407, respectively.

The first conductive layer408such as a WSi2 layer is formed on the polycrystalline silicon layers406and407by, for example, the sputtering method or the CVD method. Also, a groove region420is formed in the WSi2 layer408on the boundary portion between the NMOS part and the PMOS part to thereby isolate the WSi2 layer408on the NMOS part from the WSi2 layer408on the PMOS part as in the case of the first embodiment. Further, a gate electrode409is formed by the photolithographic method and the etching method and an oxide film411is formed on the gate electrode409by, for example, the CVD method.

In the fourth embodiment, differently from the first embodiment, a nitride film441is formed in the groove region420and on the entire surface on the WSi2 layer408as shown inFIGS. 7B and 7C. As shown inFIG. 7C, a sidewall442made of a nitride film is formed on the gate electrode409.

Further, contacts412and413are formed on the source/drain layer410and the gate electrode409, respectively. As shown inFIG. 7A, while no nitride film is formed in a region on the source/drain layer410in which region the contact412is formed, a nitride film is formed in a region on the gate electrode409in which region the contact413is formed. Due to this, the contact412on the source/drain layer410and the contact413on the gate electrode409cannot be formed in the same step but formed in different steps.

In the fourth embodiment, differently from the first embodiment, the nitride film is formed in the groove region and on the entire surface on the WSi2 layer and the sidewall made of the nitride film is formed on the gate electrode portion. As can be seen, since the sidewall made of the nitride film is formed on the gate electrode portion, it is possible to form the contact on the source/drain layer in a self-aligned manner to the gate electrode.

Next, referring toFIG. 8, a method for manufacturing the semiconductor device in the fourth embodiment will be described.FIG. 8is a cross-sectional view for manufacturing steps showing the semiconductor device manufacturing method in this embodiment. Since the steps (FIGS. 8A and 8B) of the semiconductor device manufacturing method in this embodiment until a groove region is formed are the same as those in the first embodiment (FIGS.2A and2B), no description will be given to these steps herein.

As shown inFIG. 8C, after a WSi2 layer408on the boundary portion between an NMOS part and a PMOS part is removed by the photolithographic method and the etching method to thereby form a groove region420, a nitride film441is deposited on the entire surface by, for example, the CVD method and the surface of the nitride film441is flattened by a CMP method.

Next, a gate electrode409is formed by the photolithographic method and the etching method. A source/drain layer410is then formed on each of the P well403and the N well404by the photolithographic method and the implantation method.

Further, a nitride film is deposited on the entire surface by, for example, the CVD method and then a sidewall442made of a nitride film is formed by an etch-back method.

Thereafter, after an oxide film411is deposited on the entire surface by, for example, the CVD method, contacts412and413are formed on the source/drain layer410and the gate electrode409, respectively by the photolithographic method and the etching method in different steps.

In the fourth embodiment, no nitride film is formed in a region on the source/drain layer410in which region the contact412is formed and the nitride film and the WSi2 layer is formed in a region on the gate electrode409in which region the contact413is formed. Due to this, the contact412on the source/drain layer410and the contact413on the gate electrode409cannot be simultaneously formed in the same step.

As can be seen, in this embodiment, since the nitride film is formed in the groove region and on the entire surface on the WSi2 layer and the sidewall made of the nitride film is formed on the side surface of the gate electrode portion, it is possible to form the contact on the source/drain layer in a self-aligned manner to the gate electrode. As a result, it is possible to reduce the mutual diffusion of the P type impurities and the N type impurities in the polycrystalline silicon layers and to facilitate forming the contact on the source/drain layer. Besides, since the contact can be formed on the source/drain layer in a self-aligned manner, this structure is advantageous to provide a semiconductor device having a finer structure.

In the fourth embodiment stated above, description has been given to a case where the nitride film is formed in the groove region and on the entire surface on the WSi2 layer. In the fifth embodiment, no nitride film is formed in a groove region and a nitride film is formed only on a WSi2 layer.

Now, referring toFIG. 9, the constitution of a semiconductor device in the fifth embodiment will be described.FIG. 9Ais a top view showing the constitution of the semiconductor device in the third embodiment.FIG. 9Bis a cross-sectional view taken along line a-a′ of FIG.9A.FIG. 9Cis a cross-sectional view taken along line b-b′ of FIG.9A.

First, as shown inFIG. 9, an element isolation insulating film502is formed on a silicon substrate501by, for example, the STI method. Impurities are injected into an NMOS part and a PMOS part by the photolithographic method and the implantation method, thereby forming a P well503and an N well504, respectively. Also, a source/drain layer510is formed on each of the P well503and the N well504by the photolithographic method and the implantation method.

A gate oxide film505is formed on the entire surface on the P well503and the N well504by, for example, the thermal oxidization method. Polycrystalline silicon layers506and507are deposited on the gate oxide film505. N type impurities such as arsenic are injected into the polycrystalline silicon layer506on the NMOS part and P type impurities such as boron are injected into the polycrystalline silicon layer507on the PMOS part by, for example, the photolithographic method and the implantation method, thereby forming an N+polycrystalline silicon layer506and a P+polycrystalline silicon layer507, respectively.

The first conductive layer508such as a WSi2 layer is formed on the polycrystalline silicon layers506and507by, for example, the sputtering method or the CVD method. Also, a groove region520is formed in the WSi2 layer508on the boundary portion between the NMOS part and the PMOS part to thereby isolate the WSi2 layer508on the NMOS part from the WSi2 layer508on the PMOS part as in the case of the first embodiment.

In addition, a gate electrode509is formed by the photolithographic method and the etching method and an oxide film511is formed by, for example, the CVD method.

In the fifth embodiment, differently from the fourth embodiment, no nitride film is formed in the groove region. On the other hand, similarly to the fourth embodiment, a sidewall made of a nitride film is formed on the gate electrode portion. Due to this, it is possible to form a contact on the source/drain layer in a self-aligned manner to the gate electrode.

Further, contacts512and513are formed on the source/drain layer510and the gate electrode509, respectively. In this embodiment, differently from the fourth embodiment, no nitride film is formed in a region on the gate electrode in which region the contact is formed as shown in FIG.9A. Due to this, the contact on the source/drain layer and the contact on the gate electrode can be formed in the same step using the same mask.

Next, referring toFIG. 10, a method for manufacturing the semiconductor device in the fifth embodiment will be described.FIG. 10is a cross-sectional view for manufacturing steps showing the semiconductor device manufacturing method in this embodiment. Since the steps (FIG. 10A) of the semiconductor device manufacturing method in this embodiment until a WSi2 layer is deposited on an N+polycrystalline silicon layer and a P+polycrystalline silicon layer are the same as those in the first embodiment (FIG.2A), no description will be given to the steps herein.

As shown inFIG. 10B, after a WSi2 layer508is deposited on the entire surface on a polycrystalline silicon layer consisting of an N+polycrystalline silicon layer506and a P+polycrystalline silicon layer507, a nitride film551is deposited on the entire surface by, for example, the CVD method.

Thereafter, the nitride film551and the WSi2 layer508on the boundary portion between an NMOS part and a PMOS part are removed to by the photolithographic method and the etching method thereby form a groove region520. At the same time, the nitride film551and the WSi2 layer508in a region on the gate electrode509in which region a contact513is formed, are removed.

Mask data used by this photolithographic method can be created by synthesizing mask data used to form wells with mask data on the contact formed on a gate electrode. Using the mask thus synthesized, it is possible to form the groove region520and, at the same time, to remove the nitride film551and the WSi2 layer508in the region on the gate electrode509in which region the contact513is formed.

Next, a gate electrode509is formed by the photolithographic method and the etching method. A source/drain layer510is then formed on each of the P well503and the N well504by the photolithographic method and the implantation method.

Next, a nitride film is deposited on the entire surface by, for example, the CVD method and then a sidewall552made of a nitride film is formed by the etching method as shown in FIG.10C. Further, after depositing an oxide film511on the entire surface by, for example, the CVD method, contacts512and513are formed simultaneously on the source/drain layer510and the gate electrode509, respectively by the photolithographic method and the etching method.

In the fifth embodiment, since the nitride film and the WSi2 layer in the region on the gate electrode in which region the contact is formed, are removed when the groove region is formed, it is possible to form the contact on the source/drain layer and the contact on the gate electrode simultaneously in the same step using the same mask.

As can be seen, in this embodiment, since the nitride film and the first conductive layer in the contact formation region on the gate electrode, the contact on the source/drain layer and the contact on the gate electrode can be formed simultaneously in the same step using the same mask. As a result, it is possible to reduce the mutual diffusion of the N type impurities and the P type impurities in the polycrystalline silicon layers and to simplify a manufacturing process to thereby reduce manufacturing cost. Besides, since the contact can be formed on the source/drain layer in a self-aligned manner, this structure is advantageous to provide a semiconductor device having a finer structure.

While the preferred embodiments according to the present invention have been described so far, the present invention should not be limited to these constitutions. Those skilled in the art could contrive various changes and modifications within the scope of the technical concept of the present invention as defined in claims which follows. It is appreciated that such changes and modifications fall within the technical scope of the present invention.

The embodiments have been described above while taking the constitution in which the tungsten silicide layer is adopted as the first conductive layer an example. The present invention should not be limited to this constitution. For example, the other material such as metallic tungsten can be employed to work the present invention.

Furthermore, the embodiments have been described above while taking the constitution in which the cobalt silicide layer is adopted as the first conductive layer as an example. The present invention should not be limited to this constitution. For example, a layer formed out of the other material such as titanium silicide can be adopted to work the present invention. In that case, it is preferable that a material having a low impurity diffusion coefficient and high conductivity is used.

Moreover, the embodiments have been described above while taking a case where the second conductive layer (or cobalt suicide layer) is formed in a self-aligned manner as an example. Alternatively, the second conductive layer can be formed using conventional thin film formation means.

As stated so far, according to the present invention, the groove region is formed in the WSi2 layer on the boundary region between the PMOS part and the NMOS part and the WSi2 layer on the PMOS part is isolated from the WSi2 layer on the NMOS part. Hence, it is possible to reduce the mutual diffusion of impurities through the WSi2 layers.