A self-gating flip-flop circuit includes a flip-flop circuit and a clock circuit. The flip-flop circuit includes a clock input. The clock circuit is coupled to the clock input. The clock circuit includes a latch circuit, a reset circuit, and a gate circuit. The reset circuit is coupled to the latch circuit. The gate circuit is coupled to the latch circuit and the clock input.

BACKGROUND

Many digital systems use flip-flops as storage and/or synchronization elements. In some circuits, the flip-flops consume a substantial portion of the circuit's power. The transistors receiving the clock input are responsible for most of the flip-flop's power consumption. The transistors receiving the clock input switch at every clock cycle, irrespective of whether the data input changes.

SUMMARY

A self-gating flip-flop circuit includes a flip-flop circuit and a clock circuit. The flip-flop circuit includes a clock input. The clock circuit is coupled to the clock input. The clock circuit includes a latch circuit, a reset circuit, and a gate circuit. The reset circuit is coupled to the latch circuit. The gate circuit is coupled to the latch circuit and the clock input.

A self-gating flip-flop circuit includes a data input terminal, a clock input terminal, a flip-flop circuit, and a clock circuit. The flip-flop circuit is coupled to the data input terminal. The clock circuit coupled to the flip-flop circuit and the data input terminal. The clock circuit configured to activate an internal clock signal to the flip-flop circuit responsive to a data signal at the data input terminal and a value stored in the flip-flop circuit being different logical values. The clock circuit is also configured to apply the internal clock signal to latch a signal that indicates the data signal at the data input terminal and the value stored in the flip-flop circuit are different logical values.

A self-gating flip-flop circuit includes a data input terminal, a clock input terminal, a flip-flop circuit, an exclusive-OR circuit, a latch circuit, a reset circuit, and a gate circuit. The flip-flop circuit is coupled to the data input terminal. The exclusive-OR circuit is coupled to the data input terminal and the flip-flop circuit. The latch circuit is coupled to the exclusive-OR circuit. The reset circuit is coupled to the latch circuit and the clock input terminal. The gate circuit is coupled to the latch circuit, the clock input terminal, and the flip-flop circuit. The latch circuit is transparent responsive to an output clock signal of the gate circuit being inactive and is latched responsive to the output of the gate circuit being active.

DETAILED DESCRIPTION

In this description, the term “couple” or “couples” means either an indirect or direct connection. Thus, if a first device couples to a second device, that connection may be through a direct connection or through an indirect connection via other devices and connections. Also, in this description, the recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, then X may be a function of Y and any number of other factors.

Flip-flop power consumption can be reduced be reducing the switching frequency of the transistors that receive the clock signal. For example, by reducing the switching frequency of the clock signal provided to the flip-flop, the power consumed by the flip-flop can be reduced. Some flip-flop circuits include an enable input that gates the clock signal provided to the circuit, such that the clock signal is provided to the flip-flop only while an enable signal is active. In such implementations, circuitry external to the flip-flop circuit must generate an enable signal that is suitable to control clocking of the flip-flop in a given application. Some flip-flop circuits include clock gating circuitry that controls the clock signal to a flip-flop, based on a comparison of the data stored in the flip-flop to a flip-flop data input value. For example, if the data input value is different from the value of the data stored in the flip-flop, then the clock gating circuitry passes a clock edge to the flip-flop, allowing the flip-flop to store the data input value. Conversely, if the data input value is the same as the value of the data stored in the flip-flop, then the clock gating circuitry does not pass a clock edge to the flip-flop, and the data stored in the flip-flop remains unchanged. Such self-gating flip-circuits can be more power efficient than flip-flops that lack clock gating. However, the clock input to such a circuit can still be connected to a substantial number of transistors, and each transistor connected to the clock input is a source of power consumption.

The self-gating flip-flops described herein reduce power consumption by reducing the number of transistors connected to the clock input. For example, some implementations of the self-gating flip-flops described herein connect as few as four transistors to the clock input.

FIG. 1is a high-level schematic diagram of an example self-gating flip-flop circuit100in accordance with the described examples. The self-gating flip-flop circuit100includes a flip-flop circuit102and a flip-flop clock circuit104. The flip-flop clock circuit104is coupled to the flip-flop circuit102and provides an internal clock signal134to the flip-flop circuit102if the logical value of the data stored in the flip-flop circuit102is different from the logical value of the signal (DIN) at the data input terminal122. For example, if the value stored in the flip-flop circuit102(i.e., DOUT at the output120of the flip-flop circuit102) is a logic “0”, and if the signal at the data input terminal122is a logic “1”, then: the flip-flop clock circuit104will pass a clock to the flip-flop circuit102; and the flip-flop circuit102will store the value of the signal that exists at the data input terminal122. The flip-flop circuit102may be a master-slave flip-flop.

The flip-flop clock circuit104includes a latch circuit106, a clock gate circuit108, a latch reset circuit110, and an exclusive-OR circuit112. The exclusive-OR circuit112compares the value of the data stored in the flip-flop circuit102to the value of the signal at the data input terminal122, and provides the result of the comparison to the latch circuit latch circuit106. Accordingly, the exclusive-OR circuit112is connected to the data input terminal122, the flip-flop circuit102, and the latch circuit106. The exclusive-OR circuit112may be implemented as an exclusive-OR (XOR) gate.

The latch circuit106receives the output of the exclusive-OR circuit112. The latch circuit106is coupled to the exclusive-OR circuit112, the clock gate circuit108, and the latch reset circuit110. The latch circuit106includes a data input terminal124that is coupled to the exclusive-OR circuit112. The latch circuit106is configured to pass or store the output of the exclusive-OR circuit112for use by the clock gate circuit108. The latch circuit106includes a latch control input126for receiving a signal that controls whether the latch circuit106passes or stores the output of the exclusive-OR circuit112. The latch control input126is coupled to the clock gate circuit108to allow the clock signal generated by the clock gate circuit108to control whether the latch circuit106passes or stores the output of the exclusive-OR circuit112. For example, if a clock signal generated by the clock gate circuit108is active, then the latch circuit106latches the output of the exclusive-OR circuit112. Conversely, if the clock signal generated by the clock gate circuit108is inactive, then the latch circuit106passes the output of the exclusive-OR circuit112. The signal output of the latch circuit106, irrespective of whether passed or latched, is provided on a latch data output terminal128. The latch circuit106also includes a reset terminal130for receiving a signal that controls resetting of the latch circuit106.

The latch data output terminal128is coupled to the clock gate circuit108and the latch reset circuit110. The clock gate circuit108generates the clock signal, which is provided to the clock input132of the flip-flop circuit102and to the latch control input126of the latch circuit106. The clock gate circuit108is coupled to the latch data output terminal128and the clock input terminal118, and receives (as its inputs) the output of the latch circuit106and the clock signal (CLK) at the clock input terminal118. If the output of the latch circuit106is active (indicating that the logical value of the data stored in the flip-flop circuit102is different from the logical value of the signal at the data input terminal122), and if the clock signal at the clock input terminal118is active, then the clock gate circuit108generates an output clock by passing a clock received via the clock input terminal118. The clock gate circuit108may be implemented as an “AND” gate114.

The latch reset circuit110generates the reset signal, which is provided to the reset terminal130to control resetting of the latch circuit106. The latch reset circuit110is coupled to the latch data output terminal128and the clock input terminal118, and receives (as inputs) the output of the latch circuit106and the clock signal at the clock input terminal118. If the output of the latch circuit106is inactive (indicating that the logical value of the data stored in the flip-flop circuit102is the same as the logical value of the signal at the data input terminal122), and if the clock signal at the clock input terminal118is active, then the latch reset circuit110generates an a signal to reset the latch circuit106. The latch reset circuit110may be implemented as a “NAND” gate116. Thus, the latch reset circuit110holds the latch circuit106reset while: the clock signal at the clock input terminal118is “high”; and the logical value of the data stored in the flip-flop circuit102is the same as the logical value of the signal at the data input terminal122.

In the self-gating flip-flop circuit100, the clock input terminal118is connected to only the clock gate circuit108and the latch reset circuit110. In the clock gate circuit108and the latch reset circuit110, the clock input terminal118may be connected to only two logic gates114and116, which may connect the clock input terminal118to only four transistors of the two logic gates114and116. Because the clock signal (received via the clock input terminal118) switches only four transistors in the self-gating flip-flop circuit100, the power consumption of the self-gating flip-flop circuit100is reduced relative to flip-flop circuits that connect the clock signal to more than four transistors.

FIG. 2is a low-level schematic diagram of an example self-gating flip-flop circuit200in accordance with the described examples. The self-gating flip-flop circuit200is an implementation of the self-gating flip-flop circuit100. The self-gating flip-flop circuit200includes a flip-flop circuit202and a flip-flop clock circuit204. The flip-flop clock circuit204is coupled to the flip-flop circuit202and provides an internal clock signal234to the flip-flop circuit202if the logical value of the data stored in the flip-flop circuit202is different from the logical value of the signal at the data input terminal222. For example, if the value stored in the flip-flop circuit flip-flop circuit202(i.e., at the output220of the flip-flop circuit102) is a logic “0”, and if the signal at the data input terminal222is a logic “1”, then the flip-flop clock circuit204will pass a clock to the flip-flop circuit202, and the flip-flop circuit202will store the value of the signal that exists at the data input terminal222. The flip-flop circuit202may be a master-slave flip-flop.

The flip-flop clock circuit204includes a latch circuit206, a clock gate circuit208, a latch reset circuit210, and an exclusive-OR circuit212. The exclusive-OR circuit212compares the value of the data stored in the flip-flop circuit202to the value of the signal at the data input terminal222, and provides the result of the comparison to the latch circuit latch circuit206. The exclusive-OR circuit212is connected to the data input terminal222, the flip-flop circuit202, and the latch circuit206. The exclusive-OR circuit212may be implemented as an exclusive-OR (XOR) gate.

The latch circuit206receives the output of the exclusive-OR circuit212. The latch circuit206is coupled to the exclusive-OR circuit212, the clock gate circuit208, and the latch reset circuit210. The latch circuit206includes a data input terminal224that is coupled to the exclusive-OR circuit212. The latch circuit206is configured to pass or store the output of the exclusive-OR circuit212for use by the clock gate circuit208. The latch circuit206includes a latch control input226for receiving a signal that controls whether the latch circuit206passes or stores the output of the exclusive-OR circuit212. The latch control input226is coupled to the clock gate circuit208to allow the clock signal generated by the clock gate circuit208to control whether the latch circuit206passes or stores the output of the exclusive-OR circuit212. For example, if an internal clock signal234generated by the clock gate circuit208is active, then the latch circuit206latches the output of the exclusive-OR circuit212. Conversely, if the internal clock signal234generated by the clock gate circuit208is inactive, then the latch circuit206passes the output of the exclusive-OR circuit212. The signal output of the latch circuit206, irrespective of whether passed or latched, is provided on a latch data output terminal228. The latch circuit206also includes a reset terminal230for receiving a signal that controls resetting of the latch circuit206.

The latch data output terminal228is coupled to the clock gate circuit208and the latch reset circuit210. The clock gate circuit208generates the internal clock signal234, which is provided to the clock input232of the flip-flop circuit202and to the latch control input226of the latch circuit206. The clock gate circuit208is coupled to the latch data output terminal228and the clock input terminal218, and receives (as its inputs) the output of the latch circuit206and the clock signal at the clock input terminal218. If the output of the latch circuit206is active (indicating that the logical value of the data stored in the flip-flop circuit202is different from the logical value of the signal at the data input terminal222), and if the clock signal at the clock input terminal218is active, then the clock gate circuit208generates the internal clock signal234by passing a clock received via the clock input terminal218. In some implementations of the self-gating flip-flop circuit200, the clock gate circuit208is implemented as a NAND gate236coupled to an inverter238to provide two phases of the internal clock signal234.

The latch reset circuit210generates the reset signal, which is provided to the reset terminal230to control resetting of the latch circuit106. The latch reset circuit210is coupled to the latch data output terminal228and the clock input terminal218, and receives (as its inputs) the output of the latch circuit206and the clock signal at the clock input terminal218. If the output of the latch circuit206is inactive (indicating that the logical value of the data stored in the flip-flop circuit202is the same as the logical value of the signal at the data input terminal222), and if the clock signal at the clock input terminal218is active, then the clock gate circuit208generates a signal to reset the latch circuit206. The clock gate circuit208may be implemented as a “NAND” gate216. Thus, the latch reset circuit210holds the latch circuit206reset while: the clock signal at the clock input terminal218is “high”; and the logical value of the data stored in the flip-flop circuit202is the same as the logical value of the signal at the data input terminal222.

In the self-gating flip-flop circuit200, the clock input terminal218is connected to only the NAND gate216and the NAND gate236. Within the NAND gate216, the clock input terminal218may be connected to only two transistors. Within the NAND gate236, the clock input terminal218may be connected to only two transistors. Because the clock signal (received via the clock input terminal218) switches only four transistors in the self-gating flip-flop circuit200, the power consumption of the self-gating flip-flop circuit200is reduced relative to flip-flop circuits that connect the clock signal to more than four transistors.

FIG. 3is a low-level schematic diagram of an example self-gating flip-flop circuit300in accordance with the described examples. The self-gating flip-flop circuit300is an implementation of the self-gating flip-flop circuit100. The self-gating flip-flop circuit300is similar to the self-gating flip-flop circuit200, and includes features that allow the self-gating flip-flop circuit300to be used in a scan chain, such as a joint test action group (JTAG) scan chain. The self-gating flip-flop circuit300includes a scan enable terminal302. The scan enable terminal302is connected to the latch circuit306. The latch circuit306is similar to the latch circuit206, and includes a NAND gate304in place of the inverter240of the latch circuit206. If a scan enable signal (received at the scan enable terminal302) is active, then the signal output of the latch circuit306enables the clock gate circuit308to pass the clock signal (received at the clock input terminal318) to the flip-flop circuit302.

FIG. 4is an example timing diagram for operation of the self-gating flip-flop circuit100. At time402, the output of the flip-flop circuit102is “low,” and the signal DIN at the data input terminal122transitions from “low” to “high.” The signal output by the exclusive-OR circuit112indicates the difference in the output (DOUT) of the flip-flop circuit102and the signal DIN at the data input terminal122. Responsive to the output of the exclusive-OR circuit112, the latch circuit106output signal is active in interval406, and the clock gate circuit108activates the internal clock signal134(clock pulse408) to latch the latch circuit106and clock the signal DIN into the flip-flop circuit102, thereby changing the output (DOUT) of the flip-flop circuit102at410.