High bandwidth memory having plural channels

An apparatus that includes: a control chip; a plurality of memory chips stacked on the control chip, the plurality of memory chips including first and second memory chips; and a plurality of via conductors connected between the plurality of memory chips and the control chip. Each of the first and second memory chips is divided into a plurality of channels including a first channel. The plurality of via conductors include a first via conductor electrically connected between the first channel in the first memory chip and the control chip, and a second via conductor electrically connected between the first channel in the second memory chip and the control chip. The first and second memory chips substantially simultaneously output read data read from the first channel to the first and second via conductors, respectively.

BACKGROUND

A memory device called HBM (High Bandwidth Memory) has a structure in which memory chips each having a plurality of channels are stacked. The channels can operate asynchronously and non-exclusively from each other. Because distinct data paths are assigned to the channels, respectively, the HBM can input or output a large amount of data at a high speed.

When an access is requested from a controller to a certain channel in a general HBM, a memory cell array included in any of the stacked memory chips is selected. Accordingly, when accesses are concentrated in the same channel, current consumption concentrates in the same region in the same memory chip, which may result in change of the power potential.

DETAILED DESCRIPTION

Various embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structural, logical and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessarily mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

A semiconductor device1shown inFIG. 1has a control chip20, and four memory chips10to13stacked on the control chip20. The memory chips10to13are, for example, DRAMs (Dynamic Random Access Memories). Each of the memory chips10to13is divided into four channels and the channels can operate independently of each other. Therefore, terminals such as a data input/output terminal, an address terminal, a command terminal, and a clock terminal are assigned to each of the channels. The memory chips10and11are divided into channels Ch0, Ch2, Ch4, and Ch6and the memory chips12and13are divided into channels Ch1, Ch3, Ch5, and Ch7. Therefore, the semiconductor device1has a configuration including a total of eight channels. The terminals such as the data input/output terminals, the address terminals, the command terminals, and the clock terminals respectively assigned to the channels Ch0to Ch7are connected to the control chip20through via conductors provided to penetrate through the memory chips10to13.

As shown inFIG. 1, the channel Ch0included in the memory chips10and11and the channel Ch1included in the memory chips12and13are located at the same position in a planar view, the channel Ch2included in the memory chips10and11and the channel Ch3included in the memory chips12and13are located at the same position in a planar view, the channel Ch4included in the memory chips10and11and the channel Ch5included in the memory chips12and13are located at the same position in a planar view, and channel Ch6included in the memory chips10and11and the channel Ch7included in the memory chips12and13are located at the same position in a planar view. Each of the channels Ch0to Ch7is divided into pseudo channels PC0and PC1. When one of the channels Ch0to Ch7is to be accessed, the access is performed by designating either the pseudo channel PC0or PC1. The two pseudo channels PC0and PC1in the same channel cannot be accessed simultaneously. Meanwhile, the different channels Ch0to Ch7can be accessed asynchronously and non-exclusively.

In the present embodiment, the number of I/O bits per channel is 144 bits, where 128 bits are actual data and 16 bits are ECC (Error Correction Code) data. A half of the 128-bit actual data, that is, 64 bits are assigned to one of the pseudo channels, i.e., the pseudo channel PC0and the remaining 64 bits are assigned to the other pseudo channel PC1. Eight-bit ECC data is assigned to each of the pseudo channels PC0and PC1. The 64-bit data assigned to the pseudo channel PC0is constituted by a group DW0(DWord0) including 32 bits and a group DW1(DWord1) including 32 bits. Similarly, the 64-bit data assigned to the pseudo channel PC1is constituted by a group DW2including 32 bits and a group DW3including 32 bits. Four-bit ECC data is assigned to each of the groups.

Two groups constituting the same pseudo channel in the same channel are assigned to different memory chips, respectively. For example, in the pseudo channel PC0of the channel Ch0, the group DW0is assigned to the memory chip10and the group DW1is assigned to the memory chip11. Accordingly, for example, when a read request for the pseudo channel PC0of the channel Ch0is issued, 32-bit data are output in parallel from the memory chips10and11, respectively. As shown inFIG. 2, via conductors31assigned to the group DW0of the pseudo channel PC0in the channel Ch0and via conductors32assigned to the group DW1of the pseudo channel PC0in the channel Ch0are provided independently. That is, the control chip20and the memory chips10to13are connected in a one-to-one relation and one via conductor is not assigned to a plurality of memory chips. As a result, even when there are differences in the operation speed among the memory chips10to13due to process variation, data do not collide in the via conductors. Furthermore, memory cell arrays activated with one access are distributed to two memory chips and therefore change of the power potential due to concentration of current consumption can also be suppressed.

FIG. 3Ais a plan view showing a floor plan of the memory chips10and12, andFIG. 3Bis a plan view showing a floor plan of the memory chips11and13. As shown inFIGS. 3A and 3B, each of the pseudo channels in each channel is divided into 16 memory banks including memory banks B0to B15. Positions of the memory banks B0to B15on a memory chip differ between the memory chips10and12, and the memory chips11and13. The positions of the memory banks B0to B15on the memory chips10and12are different from the positions of the memory banks B0to B15on the memory chips11and13by 180 degrees. Therefore, planar positions of the memory banks B0to B15constituting the same pseudo cannel in the same channel differ between two memory chips. For example, the planar position of the memory bank B0included in the pseudo channel PC0of the channel Ch0differs between the memory chip10and the memory chip11.

FIG. 4is a diagram showing an example in which an access to the pseudo channel PC0in the channel Ch0and an access to the pseudo channel PC0in the channel Ch4are performed in parallel. In the example shown inFIG. 4, a seamless read access using eight memory banks is performed in each of the channels Ch0and Ch4. In the present embodiment, even in a case where such a seamless read access is performed, the positions of accessed memory banks are distributed and therefore change of the power potential due to concentration of the current consumption can be suppressed.

A plurality of via conductors penetrating through the memory chips are arranged in a via formation region30shown inFIGS. 3A and 3B. A layout of the via conductors arranged in the via formation region30is as shown inFIG. 5. Signs SID0to SID3shown inFIG. 5are slice IDs corresponding to the memory chips10to13, respectively. For example, via conductors corresponding to the group DW0of the pseudo channel PC0in the channel Ch0of the memory chip10are arranged in an area31. Similarly, via conductors corresponding to the group DW1of the pseudo channel PC0in the channel Ch0of the memory chip11are arranged in an area32. The via conductors included in the areas31and32shown inFIG. 5correspond to the via conductors31and32shown inFIG. 2, respectively.

When a read access is performed to the pseudo channel PC0in the channel Ch0, 32-bit read data read from the memory chip10is supplied to the control chip20through the via conductors arranged in the area31, and 32-bit read data read from the memory chip11is supplied to the control chip20through the via conductors arranged in the area32. The 32-bit read data read from the memory chip10and the 32-bit read data read from the memory chip11are transferred substantially simultaneously. When a write access is performed to the pseudo channel PC0in the channel Ch0, 32-bit write data to be written in the memory chip10is supplied from the control chip20to the memory chip10through the via conductors arranged in the area31, and 32-bit write data to be written in the memory chip11is supplied from the control chip20to the memory chip11through the via conductors arranged in the area32. The 32-bit write data to be written in the memory chip10and the 32-bit write data to be written in the memory chip11are transferred substantially simultaneously. A plurality of via conductors for supplying address signals to the memory chips10to13are arranged in an area33.

FIG. 6is a table showing a layout of the via conductors arranged in the area31. As shown inFIG. 6, the via conductors arranged in the area31include 32 via conductors corresponding to data DQ0R to DQ31R, respectively and 32 via conductors corresponding to data DQ0F to DQ31F, respectively. The data DQ0R to DQ31R are data of 32 bits simultaneously input/output in synchronization with a rising edge of a clock signal, and the data DQ0F to DQ31F are data of 32 bits simultaneously input/output in synchronization with a falling edge of a clock signal. Other via conductors such as via conductors corresponding to data mask signals DM0R to DM3R and DM0F to DM3F and via conductors corresponding to a read clock signal and a write clock signal are also included in the area31. In the example shown inFIG. 6, paired data, for example, the data DQ0R and the data DQ0F are arranged adjacent to each other.

FIG. 7is a circuit diagram showing an example of a connection relation between via conductors and memory cell arrays. In the example shown inFIG. 7, a read path including an internal buffer43, a read FIFO circuit44, a parallel-serial conversion circuit45, and an output buffer46, and a write path including an input receiver47, a serial-parallel conversion circuit48, and an internal buffer49are connected in parallel between a via conductor41and a memory cell array42corresponding to the data DQ0R. Similarly, a read path including an internal buffer53, a read FIFO circuit54, a parallel-serial conversion circuit55, and an output buffer56, and a write path including an input receiver57, a serial-parallel conversion circuit58, and an internal buffer59are connected in parallel between a via conductor51and a memory cell array52corresponding to the data DQ0F. In this way the read path and the write path are assigned individually to each of the via conductors in the example shown inFIG. 7.

FIG. 8shows another layout of the via conductors arranged in the via formation region30. In the example shown inFIG. 8, a plurality of via conductors corresponding to the same pseudo channel in the same channel are not arranged collectively for each of the memory chips, that is, for each of the groups DW and a plurality of via conductors corresponding to the two groups DW are mixed in one area. For example, via conductors corresponding to the group DW0and the group DW1of the pseudo channel PC0in the channel Ch0are arranged in a mixed manner in areas34and35.

FIGS. 9A and 9Bshow layouts of via conductors arranged in the areas34and35, respectively. As shown inFIGS. 9A and 9B, while the layouts of the via conductors arranged in the areas34and35are the same as the layout of the via conductors arranged in the area31shown inFIG. 6, via conductors adjacent in the row direction are assigned to different memory chips. That is, via conductors arranged in columns A, C, E, and G are assigned to the memory chip10(SID0/DW0) and via conductors arranged in columns B, D, F, and H are assigned to the memory chip11(SID1/DW1) in the area34. Meanwhile, via conductors arranged in the columns A, C, E, and G are assigned to the memory chip11(SID1/DW1) and via conductors arranged in the columns B, D, F, and H are assigned to the memory chip10(SID0/DW0) in the area35.

FIG. 10is a circuit diagram showing another example of a connection relation between via conductors and a memory cell array and shows an example suitable for a case where the layout of via conductors is the layout shown inFIGS. 8, 9A, and 9B. In the example shown inFIG. 10, an output buffer62, an input receiver63, a parallel-serial conversion circuit64, and a serial-parallel conversion circuit65are assigned to a via conductor61corresponding to the data DQ0R, and an output buffer72, an input receiver73, a parallel-serial conversion circuit74, and a serial-parallel conversion circuit75are assigned to a via conductor71corresponding to the data DQ0F. A memory cell array81is assigned in common to the parallel-serial conversion circuits64and74via an internal buffer82and a read FIFO circuit83, and is assigned in common to the serial-parallel conversion circuits65and75via an internal buffer84. However, one of the paths is deactivated and is not operatively connected to the memory cell array81. For example, when the output buffer62, the input receiver63, the parallel-serial conversion circuit64, and the serial-parallel conversion circuit65corresponding to the via conductor61are activated, the output buffer72, the input receiver73, the parallel-serial conversion circuit74, and the serial-parallel conversion circuit75corresponding to the via conductor71are deactivated. As a result, the via conductor71and the memory cell array81are not operatively connected to each other. In this case, the via conductor61and the memory cell array81are operatively connected to each other.

In this way, when the via conductors are arranged in the layout shown inFIGS. 8, 9A, and 9B, adjacent via conductors are assigned to different memory chips and therefore the internal buffers82and84and the read FIFO circuit83can be assigned in common to two via conductors. This halves the numbers of the internal buffers82and84and the read FIFO circuits83and accordingly the chip area can be reduced.

A semiconductor device2shown inFIG. 11has the control chip20, and eight memory chips10to17stacked on the control chip20. That is, the semiconductor device2has a configuration in which the four memory chips14to17are added to the semiconductor device1shown inFIG. 1. The memory chips14to17have the same address configurations as those of the memory chips10to13, respectively except for the chip addresses (SIDs). Selection of the memory chips10to13and the memory chips14to17can be performed, for example, using a least significant bit of the chip address.

Accordingly, for example, when a read request is issued to the pseud channel PC0in the channel Ch4and when the least significant bit of the chip address is 0 (zero), the memory chips10and11are selected, so that 32-bit read data is output from the memory chip10through via a conductor91assigned to the group DW0of the pseudo channel PC0in the channel Ch4and 32-bit read data is output from the memory chip11through a via conductor92assigned to the group DW1of the pseudo channel PC0in the channel Ch4. In this case the pseudo channels PC0of the channel Ch4included in the memory chips14and15are not accessed. On the other hand, when a read request is issued to the pseudo channel PC0in the channel Ch4and the least significant bit of the chip address is 1, the memory chips14and15are selected, so that the 32-bit read data is output from the memory chip14through the via conductor91and 32-bit read data is output from the memory chip15through the via conductor92. In this case, the pseudo channels PC0of the channel Ch4included in the memory chips10and11are not accessed. As described above, the number of memory chips in the semiconductor device2shown inFIG. 11is doubled as compared to the semiconductor device1shown inFIG. 1and therefore the connection between the control chip20and the memory chips10to17has a one-to-two relation.

The number of the memory chips is not specifically limited. For example, it is also possible that twelve memory chips are stacked on the control chip. In this case, the connection between the control chip and the memory chips has a one-to-three relation. Further, it is also possible that the number of the memory chips is two.

Although this invention has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the inventions extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the inventions and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this invention will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the inventions. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying mode of the disclosed invention. Thus, it is intended that the scope of at least some of the present invention herein disclosed should not be limited by the particular disclosed embodiments described above.