Semiconductor device having field insulation layer between two fins

Semiconductor devices are provided. The semiconductor device includes a first fin and a second fin on a substrate and a field insulation layer between the first fin and the second fin. The field insulation layer include a first insulation layer and a second insulation layer on the first insulation layer and connected to the first insulation layer. The second insulation layer is wider than the first insulation layer. A ratio of a top width to a bottom width of each of the first fin and the second fin exceeds 0.5.

CROSS-REFERENCE TO RELATED APPLICATION

Korean Patent Application No. 10-2016-0001535, filed on Jan. 6, 2016, in the Korean Intellectual Property Office, and entitled: “Semiconductor Device,” is incorporated by reference herein in its entirety.

BACKGROUND

Embodiments relate to a semiconductor device, and more particularly, to a semiconductor device using a three-dimensional channel.

2. Description of the Related Art

One scaling technique for increasing the integration density of a semiconductor device includes using a multi-gate transistor having a fin- or nanowire-shaped silicon body on a substrate and a gate on the surface of the silicon body.

Such a multi-gate transistor uses a three-dimensional channel, thus allowing for ease of scaling thereof. Furthermore, the multi-gate transistor may have improved current control capability without increasing the length of the gate thereof. In addition, a short channel effect (SCE) in which electric potential in a channel region is influenced by a drain voltage can be effectively suppressed.

SUMMARY

One or more embodiments provide a semiconductor device, including a first fin and a second fin protruding from a substrate and including respective longer sides and shorter sides, the shorter side of the first fin and the shorter side of the second fin being spaced apart from each other to face each other, a field insulation layer between the shorter side of the first fin and the shorter side of the second fin, the field insulation layer including a first insulation layer and a second insulation layer on the first insulation layer, a gate on the first fin to intersect the first fin, a dummy gate on the field insulation layer, and a source/drain in the first fin between the gate and the dummy gate, wherein the second insulation layer is wider than the first insulation layer and a portion of the source/drain is below the second insulation layer.

One or more embodiments provide a semiconductor device, the semiconductor device comprises a first fin and a second fin formed on a substrate and a field insulation layer formed between the first fin and the second fin, and including a first insulation layer and a second insulation layer formed on the first insulation layer and connected to the first insulation layer, the second insulation layer having a width wider than a width of the first insulation layer, wherein a ratio of a top width to a bottom width of each of the first fin and the second fin exceeds 0.5.

One or more embodiments provide a semiconductor device, the semiconductor device including a first fin and a second fin protruding on a substrate and including respective longer sides and shorter sides, the shorter side of the first fin and the shorter side of the second fin being spaced apart from each other to face each other, a field insulation layer extending between the shorter side of the first fin and the shorter side of the second fin, a gate extending on the first fin to intersect the first fin, a dummy gate formed on the field insulation layer and a source/drain formed in the first fin between the gate and the dummy gate, wherein each of the first fin and the second fin has a ratio of a top width to a bottom width measured along the shorter side of each of the first fin and the second fin exceeds 0.5.

DETAILED DESCRIPTION

Semiconductor devices according to some embodiments will be explained with reference toFIG. 1toFIG. 4.FIG. 1is a plan view illustrating semiconductor devices according to some embodiments.FIG. 2is a perspective view illustrating semiconductor devices according to some embodiments.FIG. 3is a cross-sectional view taken along line A-A ofFIG. 2.FIG. 4is a cross-sectional view taken along line B-B ofFIG. 2.

Referring toFIG. 1toFIG. 4, the semiconductor device according to some embodiments may include a plurality of fins F1and F2, a plurality of gates147_1,147_2,147_5and147_6, a field insulation layer110, a plurality of dummy gates247_1, a plurality of sources/drains161and162and the like.

The plurality of fins F1and F2may extend along a second direction Y1. The fins F1and F2may be a part of a substrate101, or may include an epitaxial layer grown from the substrate101. Although the drawings herein depict two fins F1and F2that extend along a same center in a lengthwise direction, i.e., a second direction Y1, the present disclosure is not limited thereto.

Although the drawings herein depict the fins F1and F2formed in an overall rectangular parallelepiped shape, the present disclosure is not limited thereto. That is, the fins F1and F2may have a chamfered shape or have rounded edges. Since the fins F1and F2extend in the second direction Y1, the fins F1and F2may have longer sides in the second direction Y1and shorter sides in a first direction X1. As shown in the drawings, the shorter sides of the fins F1and F2may face each other. Even when the fins F1and F2have chamfered or rounded edges, it would be obvious to a person skilled in the art to distinguish between longer sides and shorter sides.

The fins F1and F2may serve as an active pattern used in a multi-gate transistor. That is, channels may be interconnected along three sides of the fins F1and F2, or formed at two sides of the fins F1and F2facing each other.

As shown inFIG. 2, the field insulation layer110may be formed on the substrate101and surround a part of the plurality of fins F1and F2. The field insulation layer110may be formed of a high density plasma (HDP) oxide layer, tetraethylorthosilicate (TEOS), plasma enhanced tetraethylorthosilicate (PE-TEOS), O3-tetra ethyl ortho silicate (O3-TEOS), undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluoride silicate glass (FSG), spin on glass (SOG), or a combination thereof.

The field insulation layer110may include a first portion111and a second portion112having different heights. The first portion111may extend in the second direction Y1, and the second portion112may extend in the first direction X1. The field insulation layer110may be an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof. The first portion111may contact, e.g., directly contact, the longer sides of the fins F1and F2, and the second portion112may to contact the shorter sides of the fins F1and F2, e.g. directly contact sidewalls of the fins F1and F2. The first portion111may have a height H0, and the second portion112may have a height H0+H1, as shown inFIG. 2. The second portion112may perform a function of an insulator for electrically isolating the fins F1and F2.

In particular, as shown inFIG. 4, a trench502may be formed between the fins F1and F2. That is, the trench502may be interposed between the shorter sides of the fins F1and F2facing each other. The second portion112may be interposed between the fins F1and F2, e.g., may be disposed in the trench502to completely fill the trench502.

The trench502may include an upper region UTR and a lower region LTR having different widths. The width of the upper region UTR may be wider than that of the lower region LTR, e.g., a smallest width in the upper region UTR may be wider than a largest width of the lower region LTR. In the present embodiment, the feature of the upper region and the lower region of the trench502having different widths may mean that the profile of the upper region and the profile of the lower region may not be continuously connected to each other, as shown in the drawings. In other words, a width of a bottom surface of the upper region UTR may be greater than a width of an upper surface of the lower region LTR that is adjacent to the bottom surface of the upper region UTR. That is, the upper region UTR and the lower region LTR of the trench502may be form a multi-step structure.

Furthermore, the sidewall of the lower region LTR of the trench502may have a slope, and the width of the lower region LTR may be continuously decrease approaching the substrate101. However, the trench502may have perpendicular sidewalls such that the lower region LTR may have the same width throughout.

As described above, the second portion112may extend in the first direction X1. In this case, as shown inFIG. 1, the second portion112may include, in the first direction X1, a region that overlaps the fins F1and F2and a region that does not overlap the fins F1and F2. In other words, the second portion may extend beyond the fins F1and F2in the first direction X1. A first insulation layer112_1and a second insulation layer112_2may be disposed in the region that overlaps the fins F1and F2.

That is, the trench502between the fins F1and F2may include the lower region LTR and the upper region UTR having different widths as described above, such that the first insulation layer112_1in the lower region LTR may also have a width different from that of the second insulation layer112_2in the upper region UTR. Specifically, the width of the second insulation layer112_2may be wider than that of the first insulation layer112_1. In the present embodiment, the feature of the first insulation layer112_1and the second insulation layer112_2having different widths may mean that the profile of the first insulation layer112_1and the profile of the second insulation layer112_2may not be continuously connected to each other, as shown in the drawings. That is, the first insulation layer112_1and the second insulation layer112_2may have a multi-step structure.

The second insulation layer1122may have a top surface with a first width TW and a bottom surface with a second width BW. The first width TW and the second width BW may be different from each other. That is, the first width TW may be wider or narrower than the second width BW. In this case, the ratio of the first width TW to the second width BW may be 0.9 or higher. Furthermore, the ratio of the first width TW to the second width BW may be 1 or higher than 1. That is, when the ratio of the first width TW to the second width BW is 1, the second insulation layer1122may have a rectangular cross-sectional surface, and when the ratio of the first width TW to the second width BW is higher than 1, the second insulation layer112_2may have an inverse trapezoidal cross-sectional surface. The ratio of the first width TW to the second width BW is 1 can be controlled through a method for manufacturing the semiconductor device according to embodiments. This will be described in detail below.

The second portion112may be formed beneath the dummy gate247_1, and the first portion111may be formed beneath the gates147_1,147_2,147_5and147_6. In the particular example shown, gates147_1and147_2may be formed on the second fin F2and gates147_5and147_6may be formed on the first fin such that the gates147_1,147_2,147_5and147_6intersect the corresponding fins F2and F1. The gates147_1,147_2,147_5and147_6may extend in the first direction X1.

The dummy gate247_1may be formed on the second portion112. Specifically, only one dummy gate247_1may be formed on the corresponding second portion112. Since only one dummy gate247_1rather than two or more dummy gates247_1is formed, a layout size can be reduced. Furthermore, the width W2of the dummy gate247_1may be narrower than the width W1of the second portion112. Thus, the dummy gate247_1may be stably disposed on the second portion112. Thus, since the width of the dummy gate is the same as that of other gates, at least the second insulation layer1122may be wider in the first direction X1than the fins F1and F2,

Referring back toFIG. 3andFIG. 4, each gate (for example, gate147_1) may include metal layers MG1and MG2. As shown in the drawings, the gate147_1may be formed by stacking two or more metal layers MG1and MG2. The first metal layer MG1may serve to regulate a work function, and the second metal layer MG2may serve to fill a space in the first metal layer MG1. For example, the first metal layer MG1may include at least one of titanium nitride (TiN), tantalum nitride (TaN), titanium carbide (TiC), and tantalum carbide (TaC). The second metal layer MG2may include tungsten (W) or aluminum (Al). The gate147_1may be formed through, e.g., a replacement process (or a gate last process), but the present disclosure is not limited thereto.

Each dummy gate (for example, dummy gate247_1) may have a structure similar to the structure of the gate147_1. As shown in the drawings, the dummy gate247_1may be formed by stacking two or more metal layers MG1and MG2. For example, the first metal layer MG1may serve to regulate a work function, and the second metal layer MG2may serve to fill the space formed by the first metal layer MG1.

A gate insulation layer145may be interposed between the first fin F1and the gate147_1. As shown inFIG. 3, the gate insulation layer145may be formed on a top surface and sidewalls of the first fin F1extending above the first portion111. Furthermore, the gate insulation layer145may be interposed between the gate147_1and the first portion111. The gate insulation layer145may include a high dielectric constant material having a dielectric constant higher than that of a silicon oxide layer. For example, the gate insulation layer145may include hafnium dioxide (HfO2), zirconium dioxide (ZrO2), or tantalum pentoxide (Ta2Os).

The plurality of sources/drains161and162may be disposed among the plurality of gates147_1,1472,147_5and147_6, and between the gate (for example, gate147_1) and the dummy gate (for example, dummy gate247_1). The sources/drains161and162may be elevated sources/drains protruding further than the fins F1and F2.

Furthermore, a part of the sources/drains161and162may overlap a spacer151. A part of the sources/drains161and162may overlap the second insulation layer112_2. That is, a part of the sources/drains161and162may have a tuck shape tucked under the spacer151and the second insulation layer112_2, e.g., an interface between the isolation region and the active region is not linear, but includes an indentation.

The height of the source/drain161and162disposed among the plurality of gates147_1,147_2,147_5and147_6and the height of the source/drain162aand161ainterposed between the gates147_1and147_5and the dummy gate247_1may be the same. That is, the source/drain161aand162ainterposed between the gates147_1and147_5and the dummy gate247_1may be full sized.

When a semiconductor device1according to a first embodiment is a PMOS transistor, the sources/drains161and162may include a compressive stress material. For example, the compressive stress material may have a lattice constant larger than that of Si, and may be, for example, silicon germanium (SiGe). The compressive stress material may apply compressive stress to the first fin F1so as to improve carrier mobility in a channel region.

When the semiconductor device1according to the first embodiment is an NMOS transistor, the sources/drains161and162may include a material same as that of the substrate101, or a tensile stress material. For example, when the substrate101is Si, the sources/drains161and162may be Si or a material having a lattice constant smaller than that of Si (for example, SiC).

Alternatively, the sources/drains161and162may be formed by doping the fins F1and F2with impurities.

The spacers151and251may include at least either a nitride layer or an oxynitride layer. The spacers151and251may be formed on sidewalls of the plurality of fins F1and F2, sidewalls of the plurality of gates1471,147_2,147_5and147_6, and sidewalls of the plurality of dummy gates247_1.

The substrate101may be made of one or more semiconductor materials selected from a group consisting of Si, Ge, SiGe, GaP, GaAs, SiC, SiGeC, InAs and InP. The substrate101may be a silicon-on-insulator substrate.

The top surface of the second portion112, i.e., the top surface of the second insulation layer112_2, may be formed on the same plane with the top surface of the fins F1and F2i.e., may have a same height along a third direction Z1, but the present disclosure is not limited thereto. Thus, the top surface of the second portion112may be disposed closer to the substrate101as compared with the top surface of the fins F1and F2, i.e., may be shorter than the fins F1and F2.

The width BW of the top surface of the second insulation layer112_2may be wider than the width of the first insulation layer112_1. The width BW of the top surface of the second insulation layer112_2may be wider than a width W3of the dummy gate247_1. Thus, the dummy gate247_1can be stably disposed on the second insulation layer112_2. Furthermore, a thickness L1of the second insulation layer112_2may range from 0.01 Å to 300 Å. A thickness L1may change depending on processes.

Referring back toFIG. 4, since the second insulation layer112_2is wider than the first insulation layer112_1as shown, the first insulation layer112_1and the elevated source/drain162do not contact each other, and a part166of the fins F1and F2may be interposed between the first insulation layer112_1and the elevated source/drain162, but the present disclosure is not limited thereto.

Referring back toFIG. 2andFIG. 3, the fins F1and F2according to the embodiments may have a top width TCD and a bottom width BCD. The top width TCD may be a length of the top surface of the fins F1and F2in the first direction X1. However, the top surface of the fins F1and F2is depicted as flat in the present embodiment, but the present disclosure is not limited thereto. Thus, when the top surface of the fins F1and F2are protruded, that is, shaped as a hemisphere, the top width TCD may mean the width of the fins F1and F2at the point of 5 nm below from the highest point of the protruded hemisphere shape. The bottom width BCD may be a length measured along the first direction X1from the point where the fins F1and F2and the substrate101are connected.

Referring toFIG. 3, the ratio of the top width TCD to the bottom width BCD of the fins F1and F2may be 0.5 or higher. That is, the ratio of the top width TCD to the bottom width BCD can be controlled through a method for manufacturing the semiconductor device according to embodiments. Therefore, the ratio of the top width TCD to the bottom width BCD can be made as large as possible, up to 1. When the ratio is almost 1, sidewalls of the fins F1and F2have a slope close to perpendicular. The method for manufacturing the semiconductor device according to embodiments will be described later.

The semiconductor device according to embodiments may include fins of which ratio of the top width TCD to the bottom width BCD is 0.5 or higher, e.g., up to 1. Thus, the semiconductor device may have improved performance, and the plurality of fins of the semiconductor device may have a uniform width. Furthermore, the semiconductor device according to embodiments may include the second insulation layer112_2having a controllable shape.

A method for manufacturing a semiconductor device according to some embodiments will now be described with reference toFIG. 5toFIG. 18.FIG. 5toFIG. 18illustrate stages in a method for manufacturing the semiconductor device according to some embodiments.

Referring toFIG. 5andFIG. 6, the first fin F1and the second fin F2may be formed on the substrate101such that the fins F1and F2are adjacent to each other in a lengthwise direction. Subsequently, an insulation layer3120may be formed between the first fin F1and the second fin F2. In this case, the insulation layer3120may be an oxide layer, a nitride layer, an oxynitride layer or a combination thereof.

The height of the first fin F1and the second fin F2, that is, the length protruding in the third direction Z1may range from approximately 10 nm to 50 nm. The distance along the second direction Y1between the shorter sides of the first fin F1and the second fin F2facing each other can be determined depending on the type and shape of the device to be formed by using the first fin F1and the second fin F2.

Forming the first fin F1and the second fin F2may include forming a fin mask pattern210on a substrate on which the first fin F1and the second fin F2will be formed, and then anisotropically etching the substrate by using the fin mask pattern210as an etching mask. The fin mask pattern210may include a plurality of layers which have etch selectivity relative to each other and are sequentially stacked. A buffer layer205may be provided on the substrate prior to the formation of the fin mask pattern210. The buffer layer205may include a silicon oxide layer or a silicon oxynitride layer. The fin mask pattern210may be removed after formation of the first fin F1and the second fin F2. Therefore, although the fin mask pattern210is depicted as remaining on the first fin F1and the second fin F2inFIG. 7, the present disclosure is not limited thereto.

Referring toFIG. 7andFIG. 8, a mask pattern990including an opening991may be formed on the first fin F1, the second fin F2and the insulation layer3120.

In this case, the mask pattern990may have a height determined in consideration of a subsequent planarizing process, a field recess process and the like. The mask pattern990may be a material having an etch ratio with respect to the insulation layer3120, e.g., the mask pattern990may be a nitride layer when the insulation layer3120is an oxide layer. The opening991may have a linear shape.

Subsequently, a part of the first fin F1, a part of the second fin F2, and a part of the insulation layer3120may be removed by using the mask pattern990so as to form a trench993having an opening991and the insulation layer3120a. For example, the trench993may be formed through a drying etching process.

Referring toFIG. 9andFIG. 10, an insulation layer3121may be formed to fill the trench993and the opening991.

Specifically, the insulation layer3121may be formed on the mask pattern990so as to fully fill the trench993and the opening991. Subsequently, the top surface of the insulation layer3121and the top surface of the mask pattern990may be planarized. The insulation layer3121may be made of a material same as that of the insulation layer3120, but the present disclosure is not limited thereto. Therefore, the insulation layer3121and the insulation layer3120may be made of materials having different etch ratios.

Referring toFIG. 11andFIG. 12, the mask pattern990may be removed. For example, the mask pattern990may be removed through a wet etching process. The fin mask pattern210may also be removed during the removal of the mask pattern990. An insulation layer3120amay be formed to have a top surface thereof higher than a top surface of the buffer layer205, but the present disclosure is not limited thereto. Forming the insulation layer3120amay include a planarizing process.

Referring toFIG. 13toFIG. 15, a field recess process may be performed. That is, at least a part of the insulation layers3120aand3121, a part of the first fin F1and a part of the second fin F2can be simultaneously removed. Resultantly, the height of the insulation layer3120acontacting longer sides of the fins F1and F2may be lowered so as to form the first portion111of the field insulation layer990. Furthermore, the height of the insulation layer3121may be lowered to form the second portion112of the field insulation layer990.

Removing a part of the insulation layers3120aand3121may include a dry etching process. The dry etching process may have etch selectivity with respect to the insulation layers3120aand3121.

FIG. 14andFIG. 15conceptually illustrate the removal of a part of the fins F1and F2performed and the formation of the first insulation layer112_1and the second insulation layer112_2during the removal of the insulation layers3120aand3121. These can be performed through the same process of etching the insulation layers.

The exposed top portion of the fins F1and F2can also be affected by the removal of the top portions of the insulation layers3120aand3121. Thus, the width of the top portion of the initially formed fins F1and F2may be reduced. As shown inFIG. 16, the fins F1and F2may be gradually exposed to an etch source from the top portion thereof while the insulation layer3120ais removed as much as the first thickness t1so as to be formed into the first portion111of the field insulation layer110. Thus, the top portion of the fins F1and F2can be removed as much as a second thickness t2, and sidewalls of the fins F1and F2can be removed as much as a third thickness t3.

As shown inFIG. 15, the insulation layer3121may be removed as much as a fourth thickness t4so as to be formed into the first insulation layer112_1and the second insulation layer112_2included in the first portion112of the field insulation layer110. The first thickness t1and the fourth thickness t4may be the same, but the present disclosure is not limited thereto. As described above, the insulation layer3121may be made of a material having etch selectivity different from that of the insulation layer3120a. Thus, the width of the first insulation layer112_1and the width of the second insulation layer112_2may be different from each other.

Furthermore, the second insulation layer112_2may have the first width TW and the second width BW, and the ratio of the first width TW to the second width BW may be 0.5 or higher. In the present embodiment, the ratio of the first width TW to the second width BW may vary depending on the condition and number of repetition of the etching process of the insulation layers3120aand3121.

Thus,FIG. 16toFIG. 18illustrate the second insulation layer1122having various shapes. Referring toFIG. 16, the ratio of the first width TW to the second width BW may be 1, and in this case, the second insulation layer1122may have a rectangular cross-sectional area. Referring toFIG. 17, the ratio of the first width TW to the second width BW may exceed 1, and in this case, the second insulation layer112_2may have an inverse trapezoidal cross-sectional area.

Referring toFIG. 18, the second insulation layer112_2may have a curved sidewall112_F. The curved sidewall112_F shown inFIG. 18may be applied to other embodiments.

Meanwhile, the ratio of the second thickness t2and/or the third thickness t3to the first thickness t1may be determined depending on the etch selectivity of an etch source. As the second thickness t2and the third thickness t3increase, i.e., as the fins F1and F2are removed as much as possible together with the top portions of the insulation layers3120aand3121, the top width of the final fins F1and F2may be much reduced after the removal as compared with the initial fins F1and F2. A channel region of a transistor may be formed in the top portion of the final fins F1and F2, and when the width of the top portion of the final fins F1and F2is reduced, the channel width may also be reduced, thereby causing degradation of a device such as a reduction in charge carrier mobility or an undesired high threshold voltage of the transistor.

A process of etching the insulation layers3120aand3121will now be described in more detail with reference toFIG. 19toFIG. 24.

Etching equipment for performing the insulation layer etching process according to embodiments will be described with reference toFIG. 19.FIG. 19is a conceptual view of etching equipment for performing the insulation layer etching process according to embodiments. The insulation layer etching process according to embodiments may be performed in an etching device including a process chamber10. The etching device may be etching equipment using a high density plasma source. More specifically, the etching device according to embodiments may be surface wave plasma (SWP) equipment including a radial line slot antenna31.

The etching device may include a susceptor11beneath which a wafer W may be arranged. The susceptor11may be connected to radio frequency (RF) bias12. The RF bias as used hereinafter may mean the RF bias12connected to the susceptor11. As an exemplary embodiment, high frequency of 13.56 MHz can be applied to the susceptor11by the RF bias12. The wafer W can be electrostatically adsorbed to the susceptor11by direct current power. The susceptor11may be connected to a heater.

The chamber10may be connected to a gas supply source25so as to receive treatment gas. As an exemplary embodiment, the treatment gas may include gas for plasma excitation and etching gas. The gas for plasma excitation may include at least one of argon (Ar), helium (He), neon (Ne), krypton (Kr), and xenon (Xe). The etching gas may include a carbon fluorine (CF)-based etching source. As an exemplary embodiment, the CF-based etching source may include C4F6 or C4F8. The etching gas may include oxidizing gas. The oxidizing gas may include oxygen (O2), carbon dioxide (CO2), or carbon monoxide (CO).

The gas supply source25may include a first gas supply unit23disposed in an upper portion of the chamber10, and a second gas supply unit22shaped as a ring extending along an inner sidewall of the chamber10. The gas supply unit22may include a plurality of openings or nozzles to supply treatment gas from the sidewall to the center of the chamber10.

The etching device may include a radial line slot antenna (RLSA)30disposed on the chamber10so as to generate microwave plasma. The RLSA30may be connected to a microwave generator40through a waveguide39. That is, microwave generated from the microwave generator40may be supplied to the RLSA30through the waveguide39. As an exemplary embodiment, the microwave generator40may generate microwave of 2.45 GHz. As an exemplary embodiment, high frequency power for generating the microwave may be regulated in a range from 100 W to 3000 W. The RLSA30may include a slot plate33made of a conductive material such as copper or aluminum, and a dielectric plate34disposed on the slot plate33. The slot plate33may have T-shaped slits formed at a lower surface thereof. As an exemplary embodiment, the slits may be arranged in a shape of a concentric circle. The microwave which has reached the RLSA30may be diffused in a radial direction of the RLSA30, and radiated into the chamber10through the slits of the slot plate33. Thus, the treatment gas beneath the RLSA30may be ionized to generate plasma in the chamber10.

The dielectric plate34may enable the microwave propagating toward the RLSA30along the waveguide39to propagate in a radial direction of the dielectric plate34, and may compress the wavelength of the microwave. As an exemplary embodiment, the dielectric plate34may include quartz, ceramic, or alumina. The dielectric plate34may have an upper surface and a lower surface covered with a conductor. A cooling plate37may be provided on the dielectric plate34. The cooling plate37may discharge heat generated from the RLSA30to outside. As an exemplary embodiment, the cooling plate37may include a thermally conductive material such as copper or aluminum.

A dielectric window31may be provided beneath the RLSA30. The dielectric window31may seal the inside of the chamber10. The dielectric window31may have microwave transmittance. As an exemplary embodiment, the dielectric window31may include quartz, ceramic, or alumina.

The etching device may use microwave as a plasma source, and generate high density plasma having a low electron temperature in a region where etching is performed. Thus, damages caused in the wafer W by ion bombardment during an etching process may be reduced. Furthermore, since the treatment gas is supplied through the ring-shaped second gas supply unit22beneath the dielectric window31, dissociation of the treatment gas can be controlled.

FIG. 20is a flowchart illustrating an insulation layer etching process according to embodiments. The insulation layer etching process according to embodiments may be performed in the etching device shown inFIG. 19.

Referring toFIG. 20, the insulation layer etching process according to embodiments may include a first step (S11) in which etch selectivity of the insulation layers3120aand3121relative to the fins F1and F2is higher, and a second step (S12) in which the etch selectively is relatively lower than that of the first step (S11). The first step (S11) and the second step (S12) can be performed in the same process chamber. The first step (S11) and the second step (S12) can be repeated at least twice in a cyclic manner. When the number of repetition of the first step (S11) and the second step (S12) has reached a preset value N (S13), the etching process may end.

The first step (S11) may be a more polymeric condition than the second step (S12). The second step (S12) may be a less polymeric condition than the first step (S11). The term “more polymeric condition” is used herein to describe a condition in which a polymer formed on a surface of an object to be bonded through a combination between the object to be etched and an etch source in an etching step (hereinafter, referred to as “surface polymer”) is relatively thick, and the term “less polymeric condition” may be used herein to describe a condition in which the surface polymer is relatively thin. As an exemplary embodiment, when CF-based gas is used as an etch source, the surface polymer may be a CF-based polymer obtained by combining the fins F1and F2and/or the insulation layers3120aand3121and the etch source. The first step (S11) may be referred to as an absorption step in which the formation of the surface polymer is relatively easy, and the second step (S12) may be referred to as a desorption step in which the formation of the surface polymer is relatively difficult.

The etching process may be performed by forming and removing the surface polymer. The surface polymer may be continuously formed and removed during the etching process. Thus, the thickness of the surface polymer may be determined by the ratio of the quantity of the formed surface polymer to the quantity of the removed surface polymer during the etching process. The surface polymer formed on the surface of the object to be etched in the more polymeric condition may be relatively thicker. That is, the object to be etched may be passivated by the thick surface polymer and etched at a relatively slower etching speed.

The surface polymer formed on the surface of the object to be etched in the less polymeric condition may be relatively thinner. That is, the object to be etched can be relatively rapidly etched since the thin surface polymer can be quickly removed from the object.

The first step (S11) and the second step (S12) according to embodiments can be implemented in various ways. As an exemplary embodiment, the first step (S11) and the second step (S12) can be determined by a difference in the duty ratio of RF bias. Hereinafter, a difference between the first step (S11) and the second step (S12) depending on the duty ratio of RF bias will be described in detail.

FIG. 21is a conceptual view of the first step (S11) according to embodiments andFIG. 22is a conceptual view of the second step (S12) according to embodiments. The top portion of the fin F and the top portion of the insulation layer111may be exposed to active ions R in the chamber10shown inFIG. 18. In this case, the fin F may be the above-mentioned fins F1and F2. Furthermore, the insulation layer111may be the above-mentioned first portion111of the field insulation layer110, and in the present embodiment, the etching process applied to the insulation layer111can also be applied in the same way to the above-mentioned second portion112of the field insulation layer110.

A method for controlling the ratio between the top width TCD and the bottom width BCD of the fins F1and F2according to embodiments will be described in more detail. Although the method for controlling the ratio between the top width TCD and the bottom width BCD of the fins F1and F2according to the present embodiment will be illustrated by way of example. Further, the method can be applied in the substantially same way to the method for controlling the ratio of the first width TW to the second width BW of the second insulation layer112_2.

A part of the active ions R may be bonded to the top portion of the fin F and the top portion of the insulation layer111so as to form a surface polymer PL on the fin F and the insulation layer111. When the fin F includes silicon and the insulation layer111includes an oxide layer, the insulation layer111containing oxygen and a part of the active ions R can be bonded into a CO and/or CO2form. Thus, in case of the exposed surface of the insulation layer111, the bonded active ions can be relatively easily separated from the surface of the object to be etched than the active ions bonded onto the top surface of the fin F. Resultantly, the etching speed of the insulation layer111may be higher than the etching speed of the fin F.

Referring toFIG. 21, in the first step (S11) in which the duty ratio of RF bias is relatively lower than that in the second step (S12), which will be described hereinafter, the active ions R may have relatively low linearity toward the wafer including the fin F and the insulation layer111because of the low duty ratio. As an exemplary embodiment, the duty ratio in the first step (S11) may range from approximately 60% to approximately 80%. That is, the active ions R may include a large amount of cations of low energy having a large angular distribution. As described above, the insulation layer111containing oxygen may be bonded to the active ions R, and easily separated from the surface of the object to be etched, and thus the surface polymer PL may be formed into the first thickness d1which is relatively thin on the surface of the insulation layer111during the etching process. However, the surface polymer PL may be formed into the second thickness d2which is relatively thick on the surface of the fin F because of the relatively low duty ratio of RF bias. Accordingly, the fin F having the relatively thick surface polymer PL may have a lower etching speed, and the insulation layer111may have a relatively higher etching speed. That is, the etch selectivity of the insulation layer111may be higher relatively to the fin F in the first step (S11).

Referring toFIG. 22, the duty ratio of RF bias in the second step (S12) may be relatively higher than that in the first step (S11). As an exemplary embodiment, the duty ratio in the second step (S12) may be 1.1 to 1.7 times higher than the duty ratio in the first step (S11). As an exemplary embodiment, the duty ratio in the second step (S12) may be approximately 80% to approximately 100%. In the second step (S12), the active ions R may have relatively high linearity toward the wafer including the fin F and the insulation layer111due to the high duty ratio. That is, the active ions R may include a large amount of cations of high energy having a small angular distribution. Thus, the surface polymer PL having a fourth thickness d4thinner than the second thickness d2of the first step (S11) due to the high duty ratio of RF bias may be formed on the fin F. In the second step (S12), the surface polymer PL formed on the insulation layer111may have a third thickness d3thinner than the fourth thickness d4. As an exemplary embodiment, the third thickness d3may be approximately 10% to 30% thinner than the fourth thickness d4. The third thickness d3may be thinner than the first thickness d1.

The fourth thickness d4may be thicker than the third thickness d3, but a difference between the third thickness d3and the fourth thickness d4may be smaller than a difference between the first thickness d1and the second thickness d2, and the thickness d3and d4of the surface polymer PL formed in the second step (S12) may not be sufficient to suppress the insulation layer111and the fin F from etching. Resultantly, the etch selectivity of the insulation layer111to the fin F may be lower in the second step (S12) than in the first step (S11). The etching speed of the first insulation layer111may be relatively higher in the second step (S12) than in the first step (S11) due to the duty ratio of RF bias.

In the embodiments, the first step (S11) and the second step (S12) may be repeated a plurality of times. The first step (S11) may have high etch selectivity but relatively lower etching speed for the first insulation layer111, and the second step (S12) may have low etch selectivity but relatively higher etching speed for the first insulation layer111. According to embodiments, since two steps having different etching process conditions may be repeated, large process windows can be built as compared with a non-cyclic etching process. Furthermore, etch selectivity can be improved without sacrificing the etching speed for the insulation layer111, thus preventing excessive loss of the fin F to be used as a channel region of a transistor later. That is, the ratio of top width (TCD) to bottom width (BCD) (top/bottom CD ratio) of the fin F can be improved.

That is, as the first step (S11) and the second step (S12) are repeated a plurality of times, the ratio of top width (TCD) to bottom width (BCD) of the fin F can be improved, and the ratio of top width (TCD) to bottom width (BCD) of the fin F may exceed at least 0.5. When the first step (S11) and the second step (S12) is repeated three or more times, the ratio of top width (TCD) to bottom width (BCD) of the fin F may reach approximately 0.6 or higher.

Furthermore, the respective numbers of repetitions of the first step (S11) and the second step (S12) can be controlled so as to control the ratio of the first width TW of the second insulation layer112_2to the second width BW thereof, and the ratio of the first width TW to the second width BW may be 0.9 or higher. For example, when the first step (S11) and the second step (S12) are repeated one time, the ratio of the first width TW to the second width BW may be 0.9 or higher, and the ratio of the first width TW to the second width BW may be closer to 1 as shown inFIG. 16. When the first step (S11) and the second step (S12) are repeated two or more times, the ratio of the first width TW to the second width BW may exceed 1 as shown inFIG. 17.

In the embodiments, the first step (S11) and the second step (S12) may be performed under other different process conditions as well as under the condition of different duty ratios. As an exemplary embodiment, the first step (S11) may be performed under a relatively higher chamber pressure, and the second step (S12) may be performed under a relatively lower chamber pressure. The chamber pressure in the first step (S11) may range from 14 to 21 mTorr, and the chamber pressure in the second step (S12) may range from 7 to 14 mTorr.

The first step (S11) may be an etching step using a first etch source having a high carbon to fluorine (C/F) ratio, and the second step (S12) may be an etching step using a second etch source having a low C/F ratio. As an exemplary embodiment, the first etch source may have a C/F ratio of ½ or higher, and the second etch source may have a C/F ratio lower than ½. As an exemplary embodiment, the first etch source may have C4F6(C/F ratio=:1:1.5), the second etch source may have C4F8(C/F ratio=1:2.0), C2F6(C/F ratio=1:3.0), and CF4(C/F ratio=1:4.0). The second step (S12) may have RF bias and/or RF power relatively lower than those of the first step (S11). As an exemplary embodiment, the first step (S11) may have source RF power of 1000 to 2000 W, and the second step (S12) may have source RF power of 2000 to 3000 W. The first step (S11) may have bias RF power of 0 to 500 W, and the second step (S12) may have bias RF power of 500 to 1000 W.

FIG. 23andFIG. 24are graphical representations illustrating the RF bias and duty ratio of the first step (S11) and the second step (S12) according to embodiments.

Referring toFIG. 23, the first step (S11) may have a relatively lower duty ratio of RF bias, and the second step (S12) may have a relatively higher duty ratio of RF bias. X axis may correspond to time, and Y axis may correspond to RF bias and/or RF power. The first step (S11) and the second step (S12) may be repeated a plurality of times. Thus, the first step (S11) may be performed under the more polymeric condition, and the second step (S11) may be performed under the less polymeric condition. In the present embodiment, the RF bias and/or RF power of the first step (S11) and the second step (S12) may be substantially the same.

Referring toFIG. 24, the second step (S12) may have RF bias and/or RF power larger than those in the first step (S11). The duty ratio in the second step (S12) may be larger than that in the first step (S11), or the duty ratio in the second step (S12) may be substantially the same as that in the first step (S11).

FIG. 25is a block diagram of an electronic system including semiconductor devices according to some embodiments. Referring toFIG. 26, an electronic system1100according to embodiments may include a controller1110, an input/output (I/O) device1120, a memory device1130, an interface1140, and a bus1150. The controller1110, the input/output device1120, the memory device1130and/or the interface1140may be coupled with each other through the bus1150. The bus1150may serve as a path for data movement.

The controller1110may include at least one of a microprocessor, a digital signal processor, a microcontroller, and logic elements capable of performing functions similar to those of the microprocessor, the digital signal processor, and the microcontroller. The input/output device1120may include a keypad, a keyboard, a touch screen, a mouse, and the like. The memory device1130may store therein data and/or instructions, and the like. The interface1140may perform the function of transmitting data to a communication network or receiving data from the communication network. The interface1140may be of a wired or wireless type. For example, the interface1140may include an antenna, a wired/wireless transceiver or the like. Although not shown in the drawings, the electronic system1100may further include high speed DRAM and/or SRAM as an operation memory for improving an operation of the controller1110. The semiconductor device according to some embodiments may be provided within the memory device1130, or provided as a part of the controller1110, the input/output device1120, and the like.

The electronic system1100can be applied to a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a smart phone, a mobile phone, a digital music player, a memory card, or all electronic products that can transmit and/or receive information in a wireless environment.

FIG. 26illustrates an example of a semiconductor system to which semiconductor devices according to some embodiments can be applied.FIG. 25illustrates a tablet PC. The semiconductor devices manufactured according to some embodiments of can be employed in a tablet personal computer, a notebook computer and the like. It may be readily apparent to those skilled in the art that the semiconductor devices manufactured according to some embodiments can also be applied to other integrated circuit devices which are not illustrated herein.

By way of summation and review, embodiments may provide fins having a ratio of the top width to the bottom width of greater than 0.5, e.g., up to 1. Embodiments may also provide an isolation region between fins having an upper portion on a lower portion, with the upper portion forming a tuck shape with the source/drain regions adjacent thereto. Embodiments may also provide isolation regions between fins that are wider than a dummy gate thereon.