Multi-cluster dynamic reconfigurable circuit for context valid processing of data by clearing received data with added context change indicative signal

A dynamic reconfigurable circuit includes multiple clusters each including a group of reconfigurable processing elements. The dynamic reconfigurable circuit is capable of dynamically changing a configuration of the clusters according to a context including a description of processing of the processing elements and of connection between the processing elements. A first cluster among the clusters includes a signal generating circuit that when an instruction to change the context is received, generates a report signal indicative of the instruction to change the context; a signal adding circuit that adds the report signal generated by the signal generating circuit to output data that is to be transmitted from the first cluster to a second cluster; and a data clearing circuit that, when output data to which a report signal generated by the second cluster is added is received, performs a clearing process of clearing the output data received.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2008-160430, filed on Jun. 19, 2008, the entire contents of which are incorporated herein by reference.

FIELD

The embodiment discussed herein is related to a dynamic reconfigurable circuit and to a data transmission control method of a dynamic reconfigurable circuit.

BACKGROUND

Conventionally, dynamic reconfigurable circuits (hereinafter, reconfigurable circuits) have a function of changing the contents of a command to a processing element (PE) in the reconfigurable circuit and connection between PEs during operation. Generally, information indicative of the contents of a command to a PE in the reconfigurable circuit and of connection between PEs is referred to as a context. Reading in a new context to change configuration is referred to as context switch.

The reconfigurable circuit changes a context to enable common use of PEs divided along a temporal axis, thereby enabling reduction of the hardware size of the reconfigurable circuit as a whole. The reconfigurable circuit may include plural clusters (see, e.g., Japanese Laid-Open Patent Application Publication No. 2006-18514). Such a cluster-type reconfigurable circuit can control context switch according to cluster.

FIG. 17is a circuit diagram of an internal configuration of a conventional cluster. A cluster110includes a sequencer310, a configuration memory320, a PE array330, and a crossbar switch111. The sequencer310, a state machine, controls the switching of context stored on the configuration memory320. The PE array330changes the arithmetic processing contents or connections of PEs according to configuration data read out from the configuration memory320under the control of the sequencer310.

Typically, in the installation of an application program to a reconfigurable circuit, a source code written in C language and compiled by a compiler for the reconfigurable circuit is used for the application program. Here, among processes written in C language, a loop control process is particularly time consuming. The reconfigurable circuit, however, has a configuration that reduces the processing time for the loop control through pipeline arithmetic processing of the loop control. Specifically, the reconfigurable circuit includes a counter and output from the counter serves as a starting point from which the arithmetic processing including loop control can be controlled.

The clusters110, as depictedFIG. 17, are interconnected via respective crossbar switches111in a matrix arrangement.FIG. 18is a schematic of an example of data transfer between conventional clusters. Connections between the clusters110will be described with reference toFIG. 18. In a reconfigurable circuit100, the clusters110are interconnected via the crossbar switches111in a matrix arrangement. In this manner, by using the crossbar switches111, the number of clusters is adjusted to determine the number of arithmetic processors (PE) incorporated in the reconfigurable circuit100enabling customization. The clusters110can transfer data to each other via the crossbar switches111. In this configuration, a D flip-flop (DFF), which is not depicted, is disposed on a line interconnecting clusters. Disposing the DFF prevents such a situation where a timing restriction on data transfer between clusters110cannot be satisfied due to LSI operation speed.

In the cluster-type reconfigurable circuit100, therefore, the number of clusters110and the number and bit width of ports on a line between clusters110can be changed freely, depending on the application program installed in the reconfigurable circuit100and the circuit area of the LSI. In the example depicted inFIG. 18, the number of clusters is four (clusters0,1,2, and3). When the number of PEs is to be increased, additional clusters, such as clusters ex0, ex1, ex2, and ex3, are arranged horizontally and vertically with respect to the orientation ofFIG. 18.

The number and bit width of ports on a line between clusters110depend on the architecture of arithmetic processors in the clusters110. Generally, any one of an 8-bit processor, 16-bit processor, and 32-bit processor is adopted. By increasing the number of ports, the types of data that can be transferred between clusters110can be increased.

The conventional cluster-type reconfigurable circuit100, however, may have trouble in data transmission between the clusters110when carrying out processing across context switching (e.g., a series of processes including a change in context from a context A to a context B).

A context can be changed without a standby-cycle when the sequencer310in the cluster110is able to read a context transition destination in advance. When data transmission is performed between different clusters110, however, a cluster110as a data transmission origin cannot grasp the state of another cluster110as a data transmission destination. As a result, the data transmission origin cluster110sends unnecessary data to the data transmission destination cluster110because of the context switch, which may lead to the occurrence of a malfunction.

In an example in which a group of clusters110are interconnected in matrix arrangement as depicted inFIG. 18, two types of data A and B are transferred from a cluster0to clusters2and3.FIG. 19is a schematic of a context switch sequence at each cluster.

At each cluster110(cluster0,1,2, and3) depicted inFIG. 18, context switch from a context0to a context1is performed at a given time (time n) (seeFIG. 19) under the control of the internal sequencer310(seeFIG. 17). “context numeral-numeral” written in each cluster depicted inFIG. 19means “context [context number]-[cluster number]”. In context switching, transition to the next context can be made without a stand-by cycle.

As depicted inFIG. 19, when data transfer is performed between clusters110across context switching, the reconfigurable circuit110may malfunction because of the DFF disposed on the line between the clusters110.FIG. 20is a timing chart of inter-cluster data transfer operation. As depicted in the timing chart ofFIG. 20, while executing contexts1-2and1-3, clusters2and3receive data that the cluster0outputs according to a context0-0(portion marked with *). The data received is data that has been held in the DFF between the clusters110during cluster switch.

As depicted inFIG. 20, among data output from the cluster0, data A-0to A-5and B-0to B-5are generated by a process based on the context0, while data A-6to A-10and B-6to B-10are generated by a process based on the context1. Here, if the clusters2and3continue to use output data that is generated based on the context0preceding the current context by one context as input data (i.e., group of data marked with * inFIG. 20), the clusters2and3receiving the data having been held in the DFF causes no problem.

However, when the output data based on the context0is not used as input data that is to be used based on the currently set context1, using the data based on the context0preceding the current context by one context and having been held in the DFF between the clusters110, may result in output of different calculation values or the occurrence of malfunction. To remedy such a situation, a cycle of intentional flow of invalid data must be added during context switch, resulting in the occurrence of unnecessary waiting during context switch, thus leading to a problem of the deterioration of performance of the reconfigurable circuit.

SUMMARY

According to an aspect of an embodiment, a dynamic reconfigurable circuit includes multiple clusters each including a group of reconfigurable processing elements. The dynamic reconfigurable circuit is capable of dynamically changing a configuration of the clusters according to a context including a description of processing of the processing elements and of connection between the processing elements. A first cluster among the clusters includes a signal generating circuit that when an instruction to change the context is received, generates a report signal indicative of the instruction to change the context; a signal adding circuit that adds the report signal generated by the signal generating circuit to output data that is to be transmitted from the first cluster to a second cluster; and a data clearing circuit that, when output data to which a report signal generated by the second cluster is added is received, performs a clearing process of clearing the output data received.

DESCRIPTION OF EMBODIMENT(S)

Preferred embodiments of the present invention will be explained with reference to the accompanying drawings. According to the embodiments, optimum data flow is achieved between clusters by adding a report signal (i.e., inhibit signal to be described later) indicative of data during context switch to data transmitted between clusters.

FIG. 1is a schematic of connections of clusters in a reconfigurable circuit according to an embodiment. As depicted inFIG. 1, a reconfigurable circuit100includes plural clusters110connected via crossbar switches111in a matrix arrangement.

A line interconnecting clusters110is provided with ports (e.g., port0to port (x)) for transmitting data generated by the clusters110as output data to a specific cluster. In the embodiment, the line also includes a dedicated port (inhibit) for transmitting an inhibit signal, in addition to the ordinary ports. InFIG. 1, the dedicated port (inhibit) for one line is exemplarily depicted for simplification, though the number of dedicated ports provided is equivalent to the number of data output ports (the ports1to (x)).

In the embodiment, when output data is transmitted from a cluster110(e.g., cluster0) to another cluster110(e.g., clusters2and3), an inhibit signal is output from the dedicated port concurrently. When output data of a cluster110is addressed to another cluster110, the crossbar switch111of the other cluster110receives the output data and when the output data transmitted is not addressed the other cluster110, the other cluster110forwards the output data to a cluster110adjacent to the cluster110having transmitted the output data. In other words, when determined to be the cluster to receive output data, the cluster receives the output data and when not determined to be an address cluster, the cluster causes the output data to travel through to a transmission destination cluster. When receiving output data, therefore, each cluster is able to make a determination on the context switch status of a transmission destination cluster110according to whether an inhibit signal is added to the output data.

A general configuration of the reconfigurable circuit100of the embodiment is described with reference toFIG. 1. The reconfigurable circuit (a dynamic reconfigurable circuit)100includes plural clusters110each including a group of PEs for which a PE command and inter-PE connection can be changed dynamically according to a context. The reconfigurable circuit100works together with a high-order program to execute a PE command and inter-PE connection set in a specified context to realize operation desired by a user.

When the reconfigurable circuit100executes a program prepared by a user, the program is compiled according to the configuration of the reconfigurable circuit100. A practical application procedure of the reconfigurable circuit100is described. An example is assumed where a user prepares a program written in C language to cause the reconfigurable circuit100to execute the program. A program written in a higher language other than C language may also be used. In such a case, a compiler corresponding to the higher language is prepared.

FIG. 2is a schematic of an application procedure of the reconfigurable circuit. As depicted inFIG. 2, a C source code201for a reconfigurable circuit is prepared. The C source code201for the reconfigurable circuit is a source code that is written in C language prepared by the user of the reconfigurable circuit100.

In use of the reconfigurable circuit100, the C source code201for the reconfigurable circuit is translated first by a compiler for a reconfigurable circuit (step S210) to generate configuration data202. The compiler is a compiler for the reconfigurable circuit100to be used, and generates the configuration data202corresponding to the hardware configuration of the reconfigurable circuit100.

Following the end of compiling by the compiler for the reconfigurable circuit, a startup request for starting up the reconfigurable circuit100is made (step S220). After the startup request is made, the configuration data202generated at step S210is loaded (step S230), and the reconfigurable circuit100starts operating (step S240).

The contents of the process at step S240is described in detail. When the clusters110start up as a result of the startup of the reconfigurable circuit100, the configuration data202is written to a configuration memory in each cluster110. A sequencer in each cluster110then performs a context switch process (203) according to the configuration data202written to the configuration memory. When the context switch according to the configuration data202is finished, a series of operations by the reconfigurable circuit ends (step S250).

In this manner, according to the reconfigurable circuit100of the embodiment, different contexts are set for different programs to be executed, and the contexts are changed dynamically according to the processing flow.

FIG. 3is a circuit diagram of a configuration of the cluster according to this embodiment. As depicted inFIG. 3, the cluster110includes arithmetic processing functional units including a sequencer310, a configuration memory320and a PE array330, and data transferring functional units including a crossbar switch111, an inhibit-signal generating circuit340, an inhibit-signal adding circuit350and an input-data clearing circuit360.

The operation of the cluster100related to arithmetic processing is started by a trigger that is a context start instruction (signal) from a high-order program. The cluster110has the crossbar switch111, as depicted inFIG. 1, and transmits output data to and receives input data from another cluster110via the crossbar switch111.

When the sequencer310receives a start instruction (signal) from a high-order program, the sequencer310outputs a program counter (PC) value to the configuration memory320and further outputs a context start signal to the PE array330to perform a context switch instruction and change the connection and command setting of PEs in the cluster. The PE array330having received the context start signal transmits a predicate signal to the sequencer310when processing based on a set context is finished. The predicate signal is a signal for executing control in the PE array330and giving a context switch instruction to the sequencer310. Upon receiving the predicate signal, the sequencer310outputs the PC value and the context start signal to the configuration memory320and the PE array330, respectively, to change the next context.

The configuration memory320stores therein the configuration data202generated at step S210depicted inFIG. 2. The configuration data202is made up of contexts to be executed by the reconfigurable circuit. When input of a PC value from the sequencer310is received, the configuration memory320outputs the configuration data202of a context corresponding to the PC value as a configuration signal to each functional unit in the PE array330. The configuration data202includes a signal for controlling the operation of the inhibit-signal generating circuit340, the inhibit-signal adding circuit350, and the input-data clearing circuit360, which are data transferring functional units of the cluster. Therefore, the configuration memory320further outputs the configuration data as a configuration signal to each of the functional units340to360.

Because a context is generated by compiling a program written by the user in C language, the number of contexts varies depending on the written contents of a program. During the compiling, a context based on the hardware configuration of the reconfigurable circuit is generated. Thus, in the embodiment, a context based on the configuration of the cluster110of the reconfigurable circuit is generated.

The PE array330is a functional unit that performs arithmetic processing according to the setting of a context. The PE array330includes a signal converter331, a PE332, a network circuit333, and a counter334. The signal converter331is a functional unit that converts a received context start signal into a predicate signal.

The PE332works as an operator, and performs arithmetic processing specified by an input configuration signal from the configuration memory320. The network circuit333interconnects the signal converter331, the PE332, and the counter334in the PE array330according to an input configuration signal from the configuration memory320. The counter334counts operations specified by an input configuration signal from the configuration memory320.

Among the components of the PE array330, the PE332and the counter334are arranged in plural. Within the PE array330, a data signal is transmitted and received via the network circuit333to report a result of arithmetic processing by the PE332and a count value that is circuit output from the counter334. Connection for the transmission and reception of data signals can be changed dynamically by the network circuit333.

A predicate signal for executing control in the PE array330and giving a context switch instruction to the sequencer310is described. The predicate signal is a 2-bit control signal in the cluster that indicates a comparison result in the PE332and gives an instruction for the start and the end of a context. A connection destination for the predicate signal can also be changed dynamically by the network circuit333.

The predicate signal is generated as a result of conversion of a context start instruction (signal) from the sequencer310into a 2-bit signal by the signal converter331. The predicate signal generated by conversion is output to the PE332and to the counter334via the network circuit333. Here, specifically, the predicate signal signifies the following:2′ b=“11”: true2′ b=“10”: false2′ b=“01”, “00”: invalid, i.e., indicative of nothing

Among the components of the cluster110depicted inFIG. 3, the crossbar switch111, the inhibit-signal generating circuit340, the inhibit-signal adding circuit350, and the input-data clearing circuit360are functional units that appropriately perform data transfer between clusters110. The crossbar switch111of the embodiment is configured to have a function of controlling data transfer.

FIG. 4is a circuit diagram of a configuration of the inhibit-signal generating circuit. The inhibit-signal generating circuit340receives input of a predicate signal from the PE array330and input of configuration data (configuration) from the configuration memory320. The inhibit-signal generating circuit340has a function of generating an inhibit signal for a given period set in the configuration data using the predicate signal as a trigger for signal generation.

Specifically, the inhibit-signal generating circuit340includes a start-signal generating circuit341, a 3-bit counter circuit342, and an output circuit343, as depicted inFIG. 4. InFIG. 4, a numeral on the input line of the predicate signal and a numeral on the input line of the configuration data represent the number of bits of the predicate signal and the number of bits of the configuration data, respectively.

The start-signal generating circuit341generates a start signal that causes the 3-bit counter circuit342to start counting at the input of the predicate signal having a value of “11” indicative of a true signal. The start signal generated by the start-signal generating circuit341is input to the 3-bit counter circuit342.

Subsequently, the 3-bit counter circuit342counts the number of times the start signal is input from the start-signal generating circuit341for a given period set in the input configuration data. Having a 3-bit memory capacity as the name indicates, the 3-bit counter circuit342can be set to count for 1 to 8 cycles in counting for a period of a preset value+1. The 3-bit counter circuit342outputs a flag indicative of counting in progress to the output circuit343.

While receiving input of the flag from the 3-bit counter circuit342, the output circuit343continuously outputs an inhibit signal, which is output to the inhibit-signal adding circuit350. Thus, a period during which the inhibit signal is continuously output from the output circuit343is equivalent to an assert period of the inhibit signal.

FIG. 5is a timing chart of the operation of the inhibit-signal generating circuit. A common clock signal (not depicted) is input to each cluster of the reconfigurable circuit100. Processing by each functional unit, therefore, is performed based on a clock signal (clock) as depicted inFIG. 5.

InFIG. 5, “predicate” represents the value (2-bit value) of a predicate signal input to the start-signal generating circuit341, “configuration” represents the value (3-bit value) of configuration data input to the 3-bit counter circuit342, and “inhibit” represents a generation state of an inhibit signal. During a period in which “inhibit” remains high, the inhibit signal is continuously generated.

A period during which the inhibit signal is continuously generated thus represents an assert period of the inhibit signal. In the embodiment, a preset value (representing the configuration data value) plus one cycle is equivalent to an assert period of the inhibit signal. For example, in the timing chart depicted inFIG. 5, generation of the inhibit signal starts at a time t1marked by the clock immediately after the predicate signal value changes to “11”. At the time t1, the configuration data value is “001”, which means the preset value is “1”. Hence, the inhibit signal is continuously generated for two cycles that is the sum of the preset value “1” and one additional cycle.

When the predicate signal value subsequently changes to “11”, the configuration data value changes to “011”, which means the preset value is “3”. As a result, the inhibit signal is continuously generated for four cycles from a time t2immediately after the point at which the predicate signal value changes to “11”.

In this manner, an assert period of an inhibit signal can be changed according to the setting of configuration data. An inhibit signal assert period that can be changed according to the setting of configuration data enables use of the inhibit-signal generating circuit340without altering the configuration thereof even when the number of stages of DFFs disposed on a connection line between clusters110is changed because of a timing restriction.

When unnecessary data other than data stored in the DFFs between clusters is present in output data, the output data can be cleared at an arbitrary cycle. As described with respect toFIG. 4, the 3-bit counter circuit342can count up to eight counts. If counting more than eight counts is desired according to the number of stages of DFFs, the 3-bit counter circuit342is expanded in counting capacity into a counter circuit capable of handling data greater than 3 bits.

FIG. 6is a block diagram of connections with the inhibit-signal adding circuit. When receiving input of an inhibit signal (inhibit) from the inhibit-signal generating circuit340, the inhibit-signal adding circuit350performs a process of adding the input inhibit signal to a specified data port for output data. Here, whether to add the inhibit signal depends on the setting of configuration data. Thus, addition of the inhibit signal can be adjusted according to port. For this reason, the number of bits of the configuration data is equivalent to the number of ports for output from the cluster. In the embodiment, the cluster has (x) ports as depicted inFIG. 1; hence, the configuration data is assumed to be x-bit data.

FIG. 7is a timing chart of the operation of the inhibit-signal adding circuit.FIG. 7depicts an excerpt of the operation through peripheral connections of the inhibit-signal adding circuit350among the functional units described with respect toFIG. 3.

Configuration data (configuration) of (x)-bit data from the configuration memory320is input to the inhibit-signal adding circuit350. When receiving input of an inhibit signal from the inhibit-signal generating circuit340, the inhibit-signal adding circuit350determines whether to add the inhibit signal for each of the following ports, according to the setting of the configuration data input from the configuration memory320. In this example, the inhibit signal is added when the setting of the configuration data is “1′ b1”; the bit position corresponding to port number.

As a result, output of the inhibit signal occurs according to port. Output data output from a port for which the inhibit signal is added is transmitted to another cluster110via the crossbar switch111.

For example, in the timing chart depicted inFIG. 7, an inhibit signal is input from the inhibit-signal generating circuit340initially at a time t3. At this time, bits of configurations [0] and [(x)] are effective, which means addition of the inhibit signal. The inhibit signal is, therefore, added to data output from ports0and (x) among output data output from the crossbar switch111, and is output together with the output data. An inhibit signal is input further at a time t4, at which bits of configurations [1] and [(x)] are effective; hence, the inhibit signal is added to data output from ports1and (x).

As described, the cluster110can add to output data, information indicative of context switch through the operation of the inhibit-signal generating circuit340and the inhibit-signal adding circuit350. Based on the information, i.e., an inhibit signal, a cluster110to which output data is transmitted can determine whether context switch occurs at a cluster110transmitting the output data.

As described, the cluster110can add to output data, information indicative of context switch. The input-data clearing circuit360is a circuit that when output data with an inhibit signal added thereto is transmitted from another cluster110, processes the output data properly.

FIG. 8is a block diagram of connections with the input-data clearing circuit. The input-data clearing circuit360, when the inhibit-signal adding circuit350adds, port by port, an inhibit signal to output data transmitted from another cluster110, performs a clearing process (ALL-0) of clearing output data to be cleared. The clearing process is not performed indiscriminately on data with an inhibit signal added thereto. Based on the setting of configuration data, it can be determined port by port whether the clearing process is to be performed. The number of bits of the configuration data, therefore, is equivalent to the number of ports of the cluster110. In the embodiment, the cluster has (x) ports as depicted inFIG. 1; hence, the configuration data is assumed to be x-bit data.

FIG. 9is a timing chart of the operation of the input-data clearing circuit.FIG. 9depicts an excerpt of the operation through peripheral connections of the input-data clearing circuit360among the functional units of the cluster110described with respect toFIG. 3.

Output data transmitted from another cluster110is input via the crossbar switch111to the input-data clearing circuit360. Here, from a data port corresponding to the output data, an inhibit signal added at the cluster110generating the inhibit signal is output and is also input to the input-data clearing circuit360. When the output data with the inhibit signal added thereto is input through each of the following ports based on (x)-bit configuration data, whether the corresponding output data is to be cleared is determined for each port. In this example, incoming output data (i.e., data input to this cluster110) is cleared when the inhibit signal is added to the incoming output data and the setting of configuration data is “1′ b1”. When the inhibit signal is not added to incoming output data or when, although the inhibit signal is added, the setting of configuration data is “0”, the incoming output data is directly output to the PE array330. Here, the bit position in the configuration data corresponds to port number.

For example, in the timing chart depicted inFIG. 9, an inhibit signal is added to input data from ports0,1, and (x) at a time t5. At this time, bits of configurations [0] and [(x)] are effective, which indicates an instruction for execution of the clearing process. The data from the ports0and (x) corresponding to the configurations [0] and [(x)] are, therefore, cleared (clear (ALL 0)). Subsequently, at time t6, the configurations [1] and [(x)] are effective. However, with respect to the port1, as the input inhibit data is 0, the data clearing process is not executed. Meanwhile, with respect to the port (x), as the input inhibit data is 1, the data clearing process is executed.

In this manner, an inhibit signal is added to data to indicate that the data with the inhibit signal is data at the verge of context switch. Thus, when data is specified by configuration data as data to be cleared, using the period during which an inhibit signal is added to the data as a guide, the data is cleared, thereby preventing unintentional deletion of data.

Therefore, as depicted inFIG. 8, output data from the input-data clearing circuit360that is controlled by an inhibit signal passes directly through the network circuit333of the PE array330to be input to each PE332. In this manner, the cluster110causes the input-data clearing circuit360to perform a determining process before input of output data transmitted from another cluster110to the PE array330. Thus, the cluster110can select input data according to context switch.

In the embodiment, because data passes through one additional DFF stage when transferred to another cluster110, the crossbar switch111has a function such that when input data is transferred to another cluster110, if an inhibit signal has been added to the data, an inhibit signal is added to data at the subsequent cycle.

FIG. 10is a schematic of an example of the operation of the crossbar switch. As depicted inFIG. 10, data generated by the cluster0is transmitted as output data through the cluster2to the cluster3, using the port1. An inhibit signal is added to the output data from the cluster0.

The output data from the cluster0passes through the cluster2to be transferred to the cluster3. Here, the crossbar switch111in the cluster2newly adds a one-cycle inhibit signal to output data from the port1.FIG. 11is a timing chart of the operation of the crossbar switch of the cluster2. As depicted inFIG. 11, at a time t7immediately after the end of an inhibit signal adding period in the output data from the cluster0, the crossbar switch111extends the inhibit signal adding period by one cycle before outputting the output data.

FIG. 12is a schematic of connections between clusters concerning an inhibit signal. Among connection lines between clusters110,FIG. 12depicts only the connection lines for the inhibit signal. Because the inhibit signal is paired with output data, the connection line for the inhibit signal passes through the crossbar switch111similar to a data transmission connection line as depicted inFIG. 10. Different from the connection line for transmitting output data, however, the connection line for transmitting the inhibit signal has no DFF thereon, as depicted inFIG. 1. Through application of the functions described with reference toFIGS. 10 and 11, the inhibit signal can be controlled so as not be added out of step with output data.

As described, in the reconfigurable circuit100of the embodiment, an inhibit signal is added to output data stored in a DFF between clusters110during context switch. This process enables a cluster110to determine whether incoming data is data output during context switch, i.e., hazard data.

A cluster110to which output data having an inhibit signal added thereto is transmitted, determines whether the inhibit signal is valid based on configuration data. When the inhibit signal is determined to be valid, data to be cleared is cleared. Setting concerning the determination of the validity/invalidity of the inhibit signal can be made port by port based on configuration data. In other words, the clearing operation can also be invalidated. Therefore, data having an inhibit signal added thereto is not cleared indiscriminately and may be used continuously as it is in a context after data switch.

Application of the clearing operation based on an inhibit signal enables the start of operation after the initialization of input to a cluster at the start of the second context and thereby eliminates a need of soft resetting at each cluster110and waiting time during context switch. Application of the process above enables the sharing of ports during context switch and thus suppresses an increase in wiring resources between clusters110.

FIG. 13is a schematic of an example of an application program installed in the reconfigurable circuit. Operations performed when an application program written by a source code1300depicted inFIG. 13is executed are described.

Two contexts are written in the source code1300. Specifically, a description1301is equivalent to a process of a context0, and a description1302is equivalent to a process of a context1. Array parameters A[ ], B[ ], and C[ ] written in the source code1300are expanded in a RAM, which is a PE in the cluster110. func-0, func-1, and func-2written in the source code1300represent arithmetic processing flows realized by combining plural PEs in the cluster110.

Two for-statements written in the context-0are not dependent on each other, and are, therefore, executed in parallel. The end of the final for-loop is waited for, and then the context0is switched to the context-1. The func-0is executed in the context0and in the context1in succession.

The physically arranged wiring of the reconfigurable circuit100is described in an example of an operation that is performed when the application program above is installed.FIG. 14is a schematic of an application installation example of the reconfigurable circuit in the context0, andFIG. 15is a schematic of an application installation example of the reconfigurable circuit in the context1.

As depicted in the application installation examples ofFIGS. 14 and 15, three clusters110(the cluster0, the cluster2, and the cluster3) are used when the application program written by the source code1300is executed. The three clusters110each change a context at the same timing. The array parameters A[ ], B[ ], and C[ ] are all expanded in the RAM in the cluster0, and a counter in the cluster0reads out a parameter. An array parameter read out by the counter is transferred to the cluster2and to the cluster3via the crossbar switch111. At this time, in the course of transfer between clusters110, an output signal (output data) other than an inhibit signal passes through one stage of a DFF (seeFIG. 1).

In context change from the context0to the context1in the configuration above, the following process is applied in each context to minimize waiting time (to zero).FIG. 16is a timing chart of the operation of the application program depictedFIG. 13. Process contents in the contexts0and1are reflected in the timing chart ofFIG. 16.

Immediately before the end of the context0, an inhibit signal is generated in the cluster0, and is added to the array parameters A[ ] and B[ ]. At this time, an inhibit signal generation period is set to “2”, which is equivalent to clock cycles until the input of the inhibit signal to a PE in an adjacent cluster110. In signal transfer from the cluster0to the cluster3, to transfer the inhibit signal from the cluster0to a PE of the cluster3via the cluster2consumes3clock cycles. However, through the function of the crossbar switch111described with reference toFIGS. 10 and 11, an additional inhibit signal period is extended by one cycle. Therefore, the set inhibit generation period “2”, is applied as it is.

In the context1, setting is made in the cluster2for continuous use of input data of the context0. Specifically, the input-data clearing circuit360in the cluster2makes setting so as not to clear input data from the port0and to which the inhibit signal is added. As a result, context switch can be executed without waiting time at the cluster2(seeFIG. 16).

In the context1, setting is made in the cluster3such that input data of the context0is not continuously used. Specifically, the input-data clearing circuit360in the cluster3makes setting so as to clear input data from the port0and the port1and to which the inhibit signal is added. As a result, the port1that has been used in the context0can be used as a port for transferring other data in the context1. Although the port0is not used for input data in the context0, the port0is reset at the start of the context1because the type of data to come is not known at that point. The resetting is achieved by the clearing operation based on the inhibit signal, thereby enabling operation to immediately proceed to a process in the next context without a soft resetting operation.

As described above, according to the reconfigurable circuit of the embodiment, waiting does not occur during context switch. Hence a decline in the performance of the reconfigurable circuit is prevented to realize optimum inter-cluster data transmission.

According to the embodiment, a report signal can be added to output data that is output during a process across context switch, thereby enabling a cluster to determine, based on the presence/absence of the report signal, whether received data is data output before context switch. Thus, the cluster can proceed to a process based on the next context without waiting for context switch.

Further, according to the embodiment, optimal inter-cluster data transmission corresponding to the contents of context switch is achieved.