SEMICONDUCTOR DEVICE

A semiconductor device includes a semiconductor control element, a first drive element, a second drive element, a first insulating element and a second insulating element. In plan view, the first drive element and the second drive element are located on the opposite sides with respect to the semiconductor control element. The first insulating element is located between the semiconductor control element and the first drive element, relays a signal transmitted from the semiconductor control element to the first drive element, and provides electrical insulation between the semiconductor control element and the first drive element. The second insulating element is located between the semiconductor control element and the second drive element, relays a signal transmitted from the semiconductor control element to the second drive element, and provides electrical insulation between the semiconductor control element and the second drive element.

TECHNICAL FIELD

The present disclosure relates to semiconductor devices.

BACKGROUND ART

Inverter devices have been used in electronic vehicles and consumer electronics. An inverter device includes a plurality of power semiconductors, such as insulated gate bipolar transistors (IGBTs) and metal-oxide-semiconductor field-effect transistors (MOSFETs), and a plurality of semiconductor devices incorporating insulating elements and serving as insulated gate drivers for generating drive signals for the power semiconductors. Each semiconductor device includes a semiconductor control element, an insulating element and a drive element. A control signal issued from an engine control unit (ECU) to the inverter device is inputted to the semiconductor control element of a semiconductor device. The semiconductor control element converts the control signal to a pulse width modulation (PWM) control signal, which is then transmitted to the drive element via the insulating element. The drive element generates a drive signal based on the PWM control signal and inputs the resulting signal to a power semiconductor to switch the power semiconductor on and off with desired timing. By switching six power semiconductors on and off at desired times, an inverter device can generate AC power for driving the motor from the DC power fed from a vehicle-mounted battery. An example of a semiconductor device that includes an insulating element is disclosed, for example, in JP-A-2016-207714.

A typical inverter device includes a plurality of half-bridge circuits each composed of two power semiconductors. The power semiconductors of each half-bridge circuit receive a drive signal from a semiconductor device. As the semiconductor device disclosed in JP-A-2016-207714 is for generating a drive signal for one power semiconductor, two such semiconductor devices are mounted on the wiring board of the inverter device per half-bridge circuit. In view of a demand for downsizing inverter devices, the wiring board is desired to be as small as possible.

DETAILED DESCRIPTION OF EMBODIMENTS

Unless otherwise noted, the phrases such as “an object A is formed in an object B” and “an object A is formed on an object B” used in the present disclosure include “the object A is formed in direct contact with the object B” and “the object A is formed on the object B with another object interposed between the object A and the object B”. Similarly, unless otherwise noted, the phrases such as “an object A is arranged in an object B” and “an object A is arranged on an object B” include “the object A is arranged with direct contact with the object B” and “the object A is arranged on the object B with another object interposed between the object A and the object B”. Similarly, unless otherwise noted, the phrase such as “an object A is located on an object B” include “the object A is located on the object B with direct contact between the object A and the object B” and “the object A is located on the object B with another object interposed between the object A and the object B”. Additionally, unless otherwise noted, the phrase such as “an object A overlaps with an object B as viewed in a certain direction” includes “the object A overlaps with the entire object B as viewed in the direction” and “the object A overlaps with a portion of the object B as viewed in the direction”.

FIGS.1to12show an example of a semiconductor device according to a first embodiment of the present disclosure. A semiconductor device A10according to the present embodiment includes a semiconductor control element11, a first drive element12, a first insulating element13, a second drive element14, a second insulating element15, an electroconductive support member2, a plurality of wires61to67and a sealing resin7. The electroconductive support member2includes a first die pad31, a second die pad32, a third die pad33, a plurality of input-side terminals51, a plurality of first output-side terminals52, a plurality of second output-side terminals53and a plurality of pad portions54to56. The semiconductor device A10may be, but not limited to, for surface mounting on a wiring board of an inverter device of, for example, an electric vehicle (e.g., a hybrid vehicle). The semiconductor device A10is not limited to specific applications and/or functions. The semiconductor device A10may be, but not limited to, a small outline package (SOP) device.

FIG.1is a plan view of the semiconductor device A10.FIG.2is a plan view of the semiconductor device A10. For convenience,FIG.2shows the sealing resin7as transparent and shows the outline of the sealing resin7in phantom (two-dot-dash lines).FIG.3is a front view of the semiconductor device A10.FIG.4is a rear view of the semiconductor device A10.FIG.5is a left-side view of the semiconductor device A10.FIG.6is a right-side view of the semiconductor device A10.FIG.7is a sectional view taken along line VII-VII ofFIG.2.FIG.8is a sectional view taken along line VIII-VIII ofFIG.2.FIG.9is a sectional view taken along line IX-IX ofFIG.2.FIG.10is a sectional view taken along line X-X ofFIG.2.FIG.11is a sectional view taken along line XI-XI ofFIG.1.FIG.12is a sectional view taken along line XII-XII ofFIG.1.

The semiconductor device A10has the shape of an oblong rectangle as viewed in the thickness direction (in plan view). For convenience, the thickness direction of the semiconductor device A10is designated as the z direction. A direction perpendicular to the z direction and parallel to one side of the semiconductor device A10(the vertical direction as seen in theFIGS.1and2) is designated as the x direction. The direction perpendicular to the z and x directions (the lateral direction as seen in theFIGS.1and2) is designated as the y direction. The x direction is an example of the “first direction”, and the y direction as the “second direction”. The shapes and dimensions of the semiconductor device A10are not specifically limited.

In one example, the semiconductor control element11, the first drive element12, the first insulating element13, the second drive element14and the second insulating element15are integral elements to the functionality of the semiconductor device A10.

As shown inFIG.2, the semiconductor control element11, which is mounted on a portion of the electroconductive support member2(the first die pad31as described later), is located at the center of the semiconductor device A10in the x direction and offset to the y1 side in the y direction. The semiconductor control element11has a rectangular shape elongated in the y direction as viewed in the z direction. The semiconductor control element11includes a circuit for converting a control signal inputted from, for example, an ECU into a PWM control signal and also includes a transmitting circuit for transmitting a PWM control signal to the first drive element12and the second drive element14. In this embodiment, the semiconductor control element11receives a control signal for the high side and a control signal for the low side and transmits a PWM control signal for the high side to the first drive element12and a PWM control signal for the low side to the second drive element14.

As shown inFIG.2, the first drive element12, which is mounted on a portion of the electroconductive support member2(the second die pad32as described later), is located at the end of the semiconductor device A10on the x1 side in the x direction. In the y direction, the first drive element12is offset to the y2 side. The first drive element12has a rectangular shape elongated in the y direction as viewed in the z direction. The first drive element12includes a receiving circuit for receiving a PWM control signal transmitted from the semiconductor control element11and a circuit for issuing a drive signal (a gate driver) for driving a switching element (e.g., IGBT or MOSFET) based on the received PWM control signal. The first drive element12drives a high-side switching element.

As shown inFIG.2, the second drive element14, which is mounted on a portion of the electroconductive support member2(the third die pad33as described later), is located at the end of the semiconductor device A10on the x2 side in the x direction. In the y direction, the second drive element14is offset to the y2 side. The second drive element14has a rectangular shape elongated in the y direction as viewed in the z direction. The second drive element14includes a receiving circuit for receiving a PWM control signal transmitted from the semiconductor control element11and a circuit for issuing a drive signal (a gate driver) for driving a switching element based on the received PWM control signal. The second drive element14drives a low-side switching element.

In this embodiment, the first drive element12drives a high-side switching element based on a high-side PWM control signal, and the second drive element14drives a low-side switching element based on a low-side PWM control signal. In an alternative example, the first drive element12may drive a low-side switching element based on a low-side PWM control signal, and the second drive element14may drive a high-side switching element based on a high-side PWM control signal.

As shown inFIG.2, the first insulating element13, which is mounted on a portion of the electroconductive support member2(the first die pad31), is located at the center of the semiconductor device A10in the y direction. In the x direction, the first insulating element13is located on the x2 side with respect to the first drive element12and on the x1 side with respect to the semiconductor control element11. That is, the first insulating element13is located between the first drive element12and the semiconductor control element11in the x direction. The first insulating element13has a rectangular shape elongated in the y direction as viewed in the z direction. The first insulating element13is provided for transmitting a PWM control signal in an insulated condition. The first insulating element13receives a PWM control signal from the semiconductor control element11via the wires64and transmits the received PWM control signal to the first drive element12via the wires65in an insulated condition. That is, the first insulating element13provides a signal transmission between the first drive element12and the semiconductor control element11, while also providing electrical insulation between the first drive element12and the semiconductor control element11.

In this embodiment, the first insulating element13is of an inductive-coupling type. An inductive-coupling type insulating element implements insulated transmission of signals by inductively coupling two inductors (coils). The first insulating element13includes a substrate made of Si and inductors made of Cu on the substrate. The inductors include a transmitting-side inductor and a receiving-side inductor that are stacked with each other in the thickness direction (the z direction) of the first insulating element13. A dielectric layer made of e.g. SiO2is interposed between the transmitting-side inductor and the receiving-side inductor. The dielectric layer electrically insulates the transmitting-side inductor and the receiving-side inductor. Although the first insulating element13of this embodiment is of an inductive type, the first insulating element13may be of a capacitive type. A capacitor is an example of a capacitive type insulating element.

As shown inFIG.2, the second insulating element15, which is mounted on a portion of the electroconductive support member2(the first die pad31), is located at the center of the semiconductor device A10in the y direction. In the x direction, the second insulating element15is located on the x1 side with respect to the second drive element14and on the x2 side with respect to the semiconductor control element11. That is, the second insulating element15is located between the second drive element14and the semiconductor control element11in the x direction. The second insulating element15has a rectangular shape elongated in the y direction as viewed in the z direction. The second insulating element15is provided for transmitting a PWM control signal in an insulated condition. The second insulating element15receives a PWM control signal from the semiconductor control element11via the wires66and transmits the received PWM control signal to the second drive element14via the wires67in an insulated condition. That is, the second insulating element15provides a signal transmission between the second drive element14and the semiconductor control element11, while also providing electrical insulation between the second drive element14and the semiconductor control element11. In this embodiment, the second insulating element15is an inductive-coupling type insulating element as with the first insulating element13. Alternatively, the second insulating element15may be of a capacitive type.

The semiconductor control element11transmits a high-side PWM control signal to the first drive element12via the first insulating element13and a low-side PWM control signal to the second drive element14via the second insulating element15. Signals other than the PWM control signals may also be transmitted from the semiconductor control element11to the first drive element12via the first insulating element13and to the second drive element14via the second insulating element15. Signals may also be transmitted from the first drive element12to the semiconductor control element11via the first insulating element13. Signals may also be transmitted from the second drive element14to the semiconductor control element11via the second insulating element15. Note that the signals transmitted from the first drive element12and the second drive element14to the semiconductor control element11may indicate any appropriate information and not specifically limited.

Generally, the motor driver circuit used in an inverter device of a hybrid vehicle, for example, is a half-bridge circuit composed of a low-side switching element and a high-side switching element connected by totem-pole configuration. An insulated gate driver turns on only one of the low-side switching element and the high-side switching element at an any given time. In the high-voltage region, the source of the low-side switching element and the reference voltage of the insulated gate driver for driving the low-side switching element are connected to ground, so that the setting of the gate-to-source voltage is relative to the ground. In contrast, the source of the high-side switching element and the reference voltage of the insulated gate driver for driving the high-side switching element are connected to the output node of the half-bridge circuit. The potential at the output node of the half-bridge circuit changes depending on which of the low-side switching element and the high-side switching element is on, so that the reference potential of the high-side insulated gate driver changes as well. When the high-side switching element is on, the reference potential is equal to the voltage applied to the drain of the high-side switching element (for example, 600 V or higher). In the semiconductor device A10, the first drive element12is used as an insulated gate driver for driving a high-side switching element. As the first drive element12and the semiconductor control element11are connected to different grounds for ensuring insulation, the first drive element12may be subjected to a transient voltage of 600 V or higher relative to the ground of the semiconductor control element11. In light of such a large potential difference occurring between the first drive element12and the semiconductor control element11, the semiconductor device A10includes the first insulating element13that electrically isolates the input-side circuit including the semiconductor control element11and the first output-side circuit including the first drive element12from each other. That is, the first insulating element13provides electrical insulation between the input-side circuit held at lower potential and the first output-side circuit held at higher potential. Also, the semiconductor device A10additionally includes the second insulating element15that electrically isolates the input-side circuit including the semiconductor control element11and the second output-side circuit including the second drive element14from each other. That is, the second insulating element15provides electrical insulation between the input-side circuit held at lower potential and the second output-side circuit held at higher potential.

A plurality of non-illustrated electrodes are provided on the upper surfaces (the surfaces on the z1 side) of the semiconductor control element11, the first drive element12, the first insulating element13, the second drive element14and the second insulating element15. In the x direction, the first drive element12, the first insulating element13, the semiconductor control element11, the second insulating element15and the second drive element14are arranged in the stated order from the x1 side to the x2 side. As viewed in the y direction, the first drive element12, the first insulating element13, the semiconductor control element11, the second insulating element15and the second drive element14do not overlap with each other, and an appropriate spacing is provided between them. The first insulating element13has a center13abetween the center11aof the semiconductor control element11and the center12aof the first drive element12in the y direction. The second insulating element15has a center15abetween the center11aof the semiconductor control element11and the center14aof the second drive element14in the y direction. That is, as viewed in the z direction, the semiconductor control element11, the first drive element12, the first insulating element13, the second drive element14and the second insulating element15are arranged in the shape of a letter V that is open toward the y2 side in the y direction.

The electroconductive support member2forms conduction paths connecting the semiconductor control element11, the first drive element12and the second drive element14of the semiconductor device A10to the wiring board of an inverter device. The electroconductive support member2may be made of an alloy containing Cu, for example. The electroconductive support member2is formed from a leadframe80, which will be described later. The electroconductive support member2supports the semiconductor control element11, the first drive element12, the first insulating element13, the second drive element14and the second insulating element15mounted thereon. As shown inFIG.2, the electroconductive support member2includes the first die pad31, the second die pad32, the third die pad33, the input-side terminals51, the first output-side terminals52, the second output-side terminals53and the pad portions54to56.

The first die pad31is located at the center of the semiconductor device A10in the x direction and offset to the y1 side in the y direction. The second die pad32is located on the x1 side in the x direction with respect to the first die pad31and spaced apart from the first die pad31. The third die pad33is located on the x2 side in the x direction with respect to the first die pad31and spaced apart from the first die pad31.

As shown inFIGS.2,7,9and10, the first die pad31has the semiconductor control element11, the first insulating element13and the second insulating element15mounted thereon. The first die pad31is electrically connected to the semiconductor control element11and is one element of the input-side circuit described above. The first die pad31may have a rectangular (or substantially rectangular) shape elongated in the x direction as viewed in the z direction. The first die pad31has an obverse surface311and a reverse surface312. The obverse surface311and the reverse surface312are spaced apart in the z direction as shown inFIGS.7,9and10. The obverse surface311is on the z1 side and the reverse surface312is on the z2 side. Each of the obverse surface311and the reverse surface312is flat (or substantially flat). As shown inFIGS.2,7,9and10, the semiconductor control element11, the first insulating element13and the second insulating element15are each bonded to the obverse surface311of the first die pad31by a bonding layer69. The bonding layer69is made by solidifying a paste of metal, such as Ag. The bonding layer69is not limited to this example and may be made from a paste of solder or sintered metal or even from an insulating paste.

In this embodiment, the first die pad31includes a plurality of protrusions313and a plurality of grooves314. As shown inFIGS.2, the protrusions313protrude to the y2 side in the y direction from the side surface of the first die pad31on the y2 side in the y direction. In this embodiment, three protrusions313are provided at equal intervals in the x direction. The protrusions313are not exposed from the sealing resin7. The protrusions313are the portions where the first die pad31is clamped and held firmly during the wire bonding in a manufacturing process. A wire61c, which will be described later, is bonded to the middle one of the protrusions313in the x direction. The first die pad31may be provided with a plating layer covering the region of the obverse surface311corresponding to the middle protrusion313. The plating layer may be made of metal containing Ag, for example. The plating layer serves to increase the strength of bonding to the wire61cand protect the leadframe80(described later) from impact or shock at the time of bonding the wire61c.

As shown inFIGS.2and10, each groove314is recessed from the obverse surface311in the z direction and extends in the y direction. In this embodiment, the plurality of grooves314include three grooves aligned in the y direction at a location between the semiconductor control element11and the first insulating element13in the x direction and another three aligned at a location between the semiconductor control element11and the second insulating element15. In this embodiment, the grooves314are formed by half-etching. The method of forming the grooves314is not limited to half-etching. For example, the grooves314may be formed by a stamping process of depressing appropriate portions of the obverse surface311. The grooves314are provided to improve the adhesion of the sealing resin7to the first die pad31. The shapes, locations and number of the grooves314to be provided are not specifically limited. In one example, the grooves314may penetrate the first die pad31in the z direction. In another example, the first die pad31may be without the grooves314.

As shown inFIGS.2,8and10, the second die pad32has the first drive element12mounted thereon. The second die pad32is electrically connected to the first drive element12and is one element of the first output-side circuit described above. The second die pad32may have a rectangular (or substantially rectangular) shape as viewed in the z direction. The second die pad32has an obverse surface321and a reverse surface322. The obverse surface321and the reverse surface322are spaced apart in the z direction as shown inFIGS.8and10. The obverse surface321is on the z1 side and the reverse surface322is on the z2 side. Each of the obverse surface321and the reverse surface322is flat (or substantially flat). As shown inFIGS.8and10, the first drive element12is bonded to the obverse surface321of the second die pad32by a bonding layer69. As shown inFIG.2, a wire62a, which will be described later, is bonded to the obverse surface321at a location away from the first drive element12to the y2 side in the y direction. The second die pad32may be provided with a plating layer covering a region of the obverse surface321to which the wire62ais bonded. The plating layer may be made of metal containing Ag, for example. The plating layer serves to increase the strength of bonding to the wire62aand protect the leadframe80(described later) from impact or shock at the time of bonding the wire62a.

In this embodiment, the second die pad32includes a protrusion323. As shown inFIG.2, the protrusion323protrudes to the x1 side in the x direction from the side surface of the second die pad32on the x1 side in the x direction. On the side surface, the protrusion323is offset to the y1 side in the y direction. The protrusion323is not exposed from the sealing resin7. The protrusion323is a portion where the second die pad32is clamped and held firmly during the wire bonding in a manufacturing process.

As shown inFIGS.2and10, the third die pad33has the second drive element14mounted thereon. The third die pad33is electrically connected to the second drive element14and is one element of the second output-side circuit described above. The third die pad33may have a rectangular (or substantially rectangular) shape as viewed in the z direction. The third die pad33has an obverse surface331and a reverse surface332. The obverse surface331and the reverse surface332are spaced apart in the z direction as shown inFIG.10. The obverse surface331is on the z1 side and the reverse surface332is on the z2 side. Each of the obverse surface331and the reverse surface332is flat (or substantially flat). As shown inFIG.10, the second drive element14is bonded to the obverse surface331of the third die pad33by a bonding layer69. As shown inFIG.2, a wire63a, which will be described later, is bonded to the obverse surface331at a location away from the second drive element14to the y2 side in the y direction. The third die pad33may be provided with a plating layer covering a region of the obverse surface321to which the wire63ais bonded. The plating layer may be made of metal containing Ag, for example. The plating layer serves to increase the strength of bonding to the wire63aand protect the leadframe80(described later) from impact or shock at the time of bonding the wire63a.

In this embodiment, the third die pad33includes a protrusion333. As shown inFIG.2, the protrusion333protrudes to the x2 side in the x direction from the side surface of the third die pad33on the x2 side in the x direction. On the side surface, the protrusion333is offset to the y1 side in the y direction. The protrusion333is not exposed from the sealing resin7. The protrusion333is a portion where the third die pad33is clamped and held firmly during the wire bonding in a manufacturing process.

The input-side terminals51form conduction paths connecting the semiconductor device A10to the wiring board of an inverter device when bonded to the wiring board. The input-side terminals51, which are electrically connected to the semiconductor control element11as necessary, are components of the input-side circuit described above. As shown inFIGS.1,2and5, the input-side terminals51are spaced apart from each other in the x direction at equal intervals. The input-side terminals51are located on the y1 side in the y direction with respect to the first die pad31and protrude to the y1 side in the y direction from the sealing resin7(the side surface73as described later). The input-side terminals51include a power supply terminal for receiving supply voltage, a ground terminal, and an input terminal for receiving a control signal. In this embodiment, the semiconductor device A10includes, but not limited to, eight input-side terminals51. Also, the signals inputted to and outputted from the input-side terminals51are not specifically limited.

Each input-side terminal51has a rectangular shape elongated in the y direction and includes a portion exposed from the sealing resin7and a portion covered with the sealing resin7. As shown inFIGS.7to9, the portion of each input-side terminal51exposed from the sealing resin7is bent into a gull-wing profile. Each input-side terminal51may be provided with a plating layer covering a portion exposed from the sealing resin7. The plating layer may be made of an Sn-containing alloy, such as solder, and covers the portion exposed from the sealing resin7. The plating layer improves the adhesion of solder to the exposed portion when the semiconductor device A10is soldered to the wiring board of an inverter device and prevents erosion of the exposed portion which may be caused by the solder. The plurality of input-side terminals51include input-side terminals51a,51b,51cand51d. The input-side terminal51ais the one of the input-side terminals51located farthest on the x1 side in the x direction. The input-side terminal51bis the one of the input-side terminals51located farthest on the x2 side in the x direction. The input-side terminal51cis the fourth one of the input-side terminals51counted from the farthest one on the x1 side in the x direction. The input-side terminal51dis the fifth one of the input-side terminals51counted from the farthest one on the x1 side in the x direction. That is, the input-side terminals51cand51dare the pair of terminals located in the middle in the x direction among the plurality of input-side terminals51. The input-side terminals51cand51dare connected to the first die pad31and support the first die pad31.

Each input-side terminals51other than the input-side terminals51cand51dis connected to a pad portion54at the end on the y2 side in the y direction. Although the shapes of the pad portions54as viewed in the z direction are not specifically limited, each pad portion54in this embodiment has an elongated shape extending toward the first die pad31. Each pad portion54has a flat (or substantially flat) upper surface (the surface on the z1 side), and a wire61is bonded thereto. The upper surface of each pad portion54may be plated. The plating layer may be made of metal containing Ag, for example, and covers the upper surface of the pad portion54. The plating layer serves to increase the strength of bonding to the wire61and to protect the leadframe80from impact or shock expected at the time of bonding the wire61. The pad portions54are entirely covered with the sealing resin7. The plurality of pad portions54include a pad portion54aand a pad portion54b. The pad portion54ais connected to the input-side terminal51a. The pad portion54bis connected to the input-side terminal51b.

Similarly to the input-side terminals51, the first output-side terminals52form conduction paths connecting the semiconductor device A10to the wiring board of an inverter device when bonded to the wiring board. The first output-side terminals52, which are electrically connected to the first drive element12as necessary, are components of the first output-side circuit described above. As shown inFIGS.1,2and6, the first output-side terminals52are spaced apart from each other in the x direction at equal intervals. The first output-side terminals52are located on the y2 side in the y direction with respect to the second die pad32and protrude to the y2 side in the y direction from the sealing resin7(the side surface74as described later). The first output-side terminals52include a power supply terminal for receiving supply voltage, a ground terminal, and an output terminal for outputting a drive signal. In this embodiment, the semiconductor device A10includes, but not limited to, three first output-side terminals52. Also, the signals inputted to and outputted from the first output-side terminals52are not specifically limited.

Each first output-side terminal52has a rectangular shape elongated in the y direction and includes a portion exposed from the sealing resin7and a portion covered with the sealing resin7. As shown inFIGS.7to9, the portion of each first output-side terminal52exposed from the sealing resin7is bent into a gull-wing profile. As with the input-side terminals51, each first output-side terminal52may be provided with a plating layer (of an Sn-containing alloy, such as solder) covering the portion exposed from the sealing resin7. The plurality of first output-side terminals52include a first output-side terminal52aand a first output-side terminal52b. The first output-side terminal52ais the one of the first output-side terminals52located farthest on the x1 side in the x direction. The first output-side terminal52ais connected to the second die pad32and supports the second die pad32. The first output-side terminal52bis the one of the first output-side terminals52located farthest on the x2 side in the x direction.

Each first output-side terminal52other than the first output-side terminal52ais connected to a pad portion55at the end on the y1 side in the y direction. Although the shapes of the pad portions55as viewed in the z direction are not specifically limited, each pad portion55in this embodiment has an elongated shape extending in the x direction. Each pad portion55has a flat (or substantially flat) upper surface (the surface on the z1 side), and a wire62is bonded thereto. As with the upper surfaces of the pad portions54, the upper surfaces of the pad portions55may be plated (with metal containing Ag, for example). The pad portions55are entirely covered with the sealing resin7.

Similarly to the input-side terminals51, the second output-side terminals53form conduction paths connecting the semiconductor device A10to the wiring board of an inverter device when bonded to the wiring board. The second output-side terminals53, which are electrically connected to the second drive element14as necessary, are components of the second output-side circuit described above. As shown inFIGS.1,2and6, the second output-side terminals53are located on the x2 side in the x direction with respect to the first output-side terminals52and are spaced apart from each other in the x direction at equal intervals. The second output-side terminals53are located on the y2 side in the y direction with respect to the third die pad33and protrude to the y2 side in the y direction from the sealing resin7(the side surface74as described later). The second output-side terminals53include a power supply terminal for receiving supply voltage, a ground terminal, au output terminal for outputting a drive signal. In this embodiment, the semiconductor device A10includes, but not limited to, three second output-side terminals53. Also, the signals inputted to and outputted from the second output-side terminals53are not specifically limited.

Each second output-side terminal53has a rectangular shape elongated in the y direction and includes a portion exposed from the sealing resin7and a portion covered with the sealing resin7. As shown inFIG.3, the portion of each second output-side terminal53exposed from the sealing resin7is bent into a gull-wing profile. As with the input-side terminals51, each second output-side terminal53may be provided with a plating layer (of an Sn-containing alloy, such as solder) covering the portion exposed from the sealing resin7. The plurality of second output-side terminals53include a second output-side terminal53aand a second output-side terminal53b. The second output-side terminal53ais the one of the second output-side terminals53located farthest on the x2 side in the x direction. The second output-side terminal53ais connected to the third die pad33and supports the third die pad33. The second output-side terminal53bis the one of the second output-side terminals53located farthest on the x1 side in the x direction.

Each second output-side terminal53other than the second output-side terminal53ais connected to a pad portion56at the end on the y1 side in the y direction. Although the shapes of the pad portions56as viewed in the z direction are not specifically limited, each pad portion56in this embodiment has an elongated shape extending in the x direction. Each pad portion56has a flat (or substantially flat) upper surface (the surface on the z1 side), and a wire63is bonded to the upper surface. As with the upper surfaces of the pad portions56, the upper surfaces of the pad portions54may be plated (with metal containing Ag, for example). The pad portions56are entirely covered with the sealing resin7.

In the semiconductor device A10, the first drive element12may receive a transient voltage of 600 V or higher relative to the ground of the semiconductor control element11. As a result, a significant potential difference may be caused between the first output-side terminals52electrically connected to the first drive element12and the input-side terminals51electrically connected to the semiconductor control element11. In addition, as the potential difference between the second drive element14and the semiconductor control element11is relatively small, a significant potential difference may also be caused between the first output-side terminals52electrically connected to the first drive element12and the second output-side terminals53electrically connected to the second drive element14.

In this embodiment, as shown inFIG.1, a large separation distance is provided in the x direction between the portions of the first output-side terminals52exposed from the sealing resin7and the portions of the second output-side terminals53exposed from the sealing resin7. Specifically, let a first inter-terminal distance L1denote the separation distance between the exposed portion of the first output-side terminal52band the exposed portion of the second output-side terminal53b, and a second inter-terminal distance L2denote the separation distance between the exposed portions of a pair of two adjacent first output-side terminals52. Then, the first inter-terminal distance L1is about 3.5 times greater than the second inter-terminal distance L2. The first inter-terminal distance L1is preferably, but not limited to, at least three times greater than the second inter-terminal distance L2. In the illustrated example, the first output-side terminals52are arranged at equal intervals in the x direction, so that the separation distance between each pair of two adjacent first output-side terminals52is the same. In an alternative example, the intervals between the first output-side terminals52may be not be uniform, in which case, the greatest one of the separation distances may be designated as the second inter-terminal distance L2.

As shown inFIG.2, the wires61to67together with the electroconductive support member2form conduction paths for the semiconductor control element11, the first drive element12and the second drive element14to perform their functions. The wires61to64may each be made of metal, such as Au, Cu or Al.

The wires61form conduction paths connecting the semiconductor control element11and the input-side terminals51. With the wires61, the semiconductor control element11is electrically connected to at least one of the input-side terminals51. The wires61are components of the input-side circuit described above. Each wire61is bonded to an electrode of the semiconductor control element11. The plurality of wires61include wires61a,61band61c. The wire61aextends from the semiconductor control element11to the x1 side in the x direction and bonded to the pad portion54aconnected to the input-side terminal51a. As such, the wire61ais relatively long and passes through a region near the first insulating element13as viewed in the z direction. Yet, the wire61adoes not overlap with the first insulating element13as viewed in the z direction. The wire61aforms a relatively small angle of 20° or less with the x direction. The wire61ais an example of a “first wire”. The wire61bextends from the semiconductor control element11to the x2 side in the x direction and bonded to the pad portion54bconnected to the input-side terminal51b. As such, the wire61bis relatively long and passes through a region near the second insulating element15as viewed in the z direction. Yet, the wire61bdoes not overlap with the second insulating element15as viewed in the z direction. The wire61bforms a relatively small angle of 20° or less with the x direction. The wire61bis an example of a “second wire”. The wire61cextends from the semiconductor control element11to the y2 side in the y direction and bonded to the protrusion313of the first die pad31. In this way, the semiconductor control element11is electrically connected via the wire61cand the first die pad31to the input-side terminals51cand51d. The numbers of the wires61a,61band61cto be provided are not specifically limited. Each wire61other than the wires61a,61band61cextends from the semiconductor control element11to the y1 side in the y direction and bonded to a pad portion54. The number of the wires61bonded to each pad portion54is not specifically limited.

The wires62form conduction paths connecting the first drive element12and the first output-side terminals52. With the wires62, the first drive element12is electrically connected to at least one of the first output-side terminals52. The wires62are components of the first output-side circuit described above. Each wire62is bonded to an electrode of the first drive element12. The plurality of wires62include a wire62a. The wire62aextends from the first drive element12to the y2 side in the y direction and bonded to the second die pad32. In this way, the first drive element12is electrically connected via the wire62aand the second die pad32to the first output-side terminal52a. The number of the wires62ato be provided is not specifically limited. Each wire62other than the wire62aextends from the first drive element12to the y2 side in the y direction and bonded to a pad portion55. The number of the wires62to be bonded to each pad portion55is not specifically limited.

The wires63form conduction paths connecting the second drive element14and the second output-side terminals53. With the wires63, the second drive element14is electrically connected to at least one of the second output-side terminals53. The wires63are components of the second output-side circuit described above. Each wire63is bonded to an electrode of the second drive element14. The plurality of wires63include a wire63a. The wire63aextends from the second drive element14to the y2 side in the y direction and bonded to the third die pad33. In this way, the second drive element14is electrically connected via the wire63aand the third die pad33to the second output-side terminal53a. The number of the wires63ato be provided is not specifically limited. Each wire63other than the wire63aextends from the second drive element14to the y2 side in the y direction and bonded to a pad portion56. The number of the wires63to be bonded to each pad portion56is not specifically limited.

As shown inFIGS.2and10, the wires64form conduction paths connecting the semiconductor control element11and the first insulating element13. With the wires64, the semiconductor control element11and the first insulating element13are electrically connected to each other. The wires64are components of the input-side circuit described above. Each wire64extends in the x direction (or substantially in the x direction) to be bonded to an electrode of the semiconductor control element11and to an electrode of the first insulating element13. The number of the wires64to be provided is not specifically limited.

As shown inFIGS.2and10, the wires65form conduction paths connecting the first drive element12and the first insulating element13. With the wires65, the first drive element12and the first insulating element13are electrically connected to each other. The wires65are components of the first output-side circuit described above. Each wire65extends in the x direction (or substantially in the x direction) to be bonded to an electrode of the first drive element12and to an electrode of the first insulating element13. The number of the wires65to be provided is not specifically limited.

As shown inFIGS.2and10, the wires66form conduction paths connecting the semiconductor control element11and the second insulating element15. With the wires66, the semiconductor control element11and the second insulating element15are electrically connected to each other. The wires66are components of the input-side circuit described above. Each wire66extends in the x direction (or substantially in the x direction) to be bonded to an electrode of the semiconductor control element11and to an electrode of the second insulating element15. The number of the wires66to be provided is not specifically limited.

As shown inFIGS.2and10, the wires67form conduction paths connecting the second drive element14and the second insulating element15. With the wires67, the second drive element14and the second insulating element15are electrically connected to each other. The wires67are components of the second output-side circuit described above. Each wire67extends in the x direction (or substantially in the x direction) to be bonded to an electrode of the second drive element14and to an electrode of the second insulating element15. The number of the wires67to be provided is not specifically limited.

As shown inFIG.1, the sealing resin7covers the semiconductor control element11, the first drive element12, the first insulating element13, the second drive element14, the second insulating element15, the first die pad31, the second die pad32, the third die pad33, the pad portions54to56, the wires61to67, a portion of each input-side terminal51, a portion of each first output-side terminal52, and a portion of each second output-side terminal53. The sealing resin7is electrically insulating. The sealing resin7is made of a material containing black epoxy resin, for example. The sealing resin7has a rectangular shape elongated in the y direction as viewed in the z direction. In this embodiment, the sealing resin7may have an x-direction dimension of about 9.0 to 11 mm, a y-direction dimension of about 3.5 to 4.5 mm and a z-direction dimension of about 1.3 to 1.5 mm, but the respective dimensions are not limited to these.

As shown inFIGS.3to6, the sealing resin7includes a top surface71, a bottom surface72and side surfaces73to76.

The top surface71and the bottom surface72are spaced apart from each other in the z direction. The top surface71and the bottom surface72face away from each other in the z direction. The top surface71is on the z1 side in the z direction, facing the same side as the obverse surface311(the z1 side) of the first die pad31. In other words, the top surface71is located on the side opposite the first die pad31with respect to the semiconductor control element11. The bottom surface72is located on the z2 side in the z direction and faces the same z2 side as the reverse surface312of the first die pad31. Each of the top surface71and the bottom surface72is flat (or substantially flat).

Each of the side surfaces73to76is connected to the top surface71and the bottom surface72and located between the top surface71and the bottom surface72in the z direction. The side surfaces73and74are spaced apart from each other in the y direction. The side surfaces73and74face away from each other in the y direction. The side surface73is located on the y1 side in the y direction, and the side surface74is located on the y2 side in the y direction. The side surfaces75and76are spaced apart from each other in the x direction and connected to the side surfaces73and74. The side surfaces75and76face away from each other in the x direction. The side surface75is located on the x1 side in the x direction, and the side surface76is located on the x2 side in the x direction. As shown inFIG.1, portions of the input-side terminals51protrude from the side surface73. In addition, portions of the first output-side terminals52and of the second output-side terminals53protrude from the side surface74. Yet, in the region of the side surface74between the first output-side terminal52band the second output-side terminal53b, the electroconductive support member2is not exposed. In addition, the electroconductive support member2is not exposed on the side surfaces75and76either. The side surface74is an example of a “first side surface”, the side surface75is an example of a “second side surface” and the side surface76is an example of a “third side surface”.

As shown inFIG.5, the side surface73includes an upper region731, a lower region732and a middle region733. The upper region731is connected to the top surface71at one end in the z direction and to the middle region733at the other end in the z direction. The upper region731is inclined relative to the top surface71. The lower region732is connected to the bottom surface72at one end in the z direction and to the middle region733at the other end in the z direction. The lower region732is inclined relative to the bottom surface72. The middle region733is connected to the upper region731at one end in the z direction and to the lower region732at the other end in the z direction. The middle region733is parallel to both the z direction and the x direction. As viewed in the z direction, the middle region733is located outside the top surface71and the bottom surface72. The middle region733is where the portions of the input-side terminals51are exposed.

As shown inFIG.6, the side surface74includes an upper region741, a lower region742and a middle region743. The upper region741is connected to the top surface71at one end in the z direction and to the middle region743at the other end in the z direction. The upper region741is inclined relative to the top surface71. The lower region742is connected to the bottom surface72at one end in the z direction and to the middle region743at the other end in the z direction. The lower region742is inclined relative to the bottom surface72. The middle region743is connected to the upper region741at one end in the z direction and to the lower region742at the other end in the z direction. The middle region743is parallel to both the z direction and the x direction. As viewed in the z direction, the middle region743is located outside the top surface71and the bottom surface72. The middle region743is where the portions of the first output-side terminals52and of the second output-side terminals53are exposed.

As shown inFIG.4, the side surface75includes an upper region751, a lower region752and a middle region753. The upper region751is connected to the top surface71at one end in the z direction and to the middle region753at the other end in the z direction. The upper region751is inclined relative to the top surface71. The lower region752is connected to the bottom surface72at one end in the z direction and to the middle region753at the other end in the z direction. The lower region752is inclined relative to the bottom surface72. The middle region753is connected to the upper region751at one end in the z direction and to the lower region752at the other end in the z direction. The middle region753is parallel to both the z direction and the y direction. As viewed in the z direction, the middle region753is located outside the top surface71and the bottom surface72.

As shown inFIG.4, the side surface75has a first gate mark75a. The first gate mark75ahas a rougher surface than the other region of the side surface75. The first gate mark75ais formed during the manufacture of the semiconductor device A10in the later-described process of forming the sealing resin7. The first gate mark75ais formed by removing resin burrs left at the site of the inlet gate of a melted resin. As shown inFIG.1, the first gate mark75ais offset in the y direction to the y1 side. Specifically, the first gate mark75ais located on the y1 side in the y direction with respect to the center12aof the first drive element12(closer to the center11aof the semiconductor control element11).

As shown inFIG.3, the side surface76includes an upper region761, a lower region762and a middle region763. The upper region761is connected to the top surface71at one end in the z direction and to the middle region763at the other end in the z direction. The upper region761is inclined relative to the top surface71. The lower region762is connected to the bottom surface72at one end in the z direction and to the middle region763at the other end in the z direction. The lower region762is inclined relative to the bottom surface72. The middle region763is connected to the upper region761at one end in the z direction and to the lower region762at the other end in the z direction. The middle region763is parallel to both the z direction and the y direction. As viewed in the z direction, the middle region763is located outside the top surface71and the bottom surface72.

As shown inFIG.3, the side surface76has a second gate mark76a. The second gate mark76ahas a rougher surface than the other region of the side surface76. The second gate mark76ais formed during the manufacture of the semiconductor device A10in the later-described process of forming the sealing resin7. The second gate mark76ais formed by removing resin burrs left at the site of the outlet gate of a melted resin. As shown inFIG.1, the second gate mark76ais offset in the y direction to the y2 side. Specifically, the second gate mark76ais located on the y2 side in the y direction (opposite the center11aof the semiconductor control element11) with respect to the center14aof the second drive element14.

In this embodiment, as shown inFIGS.11and12, the sealing resin7has a greater surface roughness on the top surface71, the bottom surface72, and each of the upper region731and the lower region732of the side surface73than on the middle region733of the side surface73. Also, the sealing resin7has a greater surface roughness on the top surface71, the bottom surface72, and each of the upper region741and the lower region742of the side surface74than on the middle region743of the side surface74. The surface roughness of each of the top surface71and the bottom surface72is preferably between 5 and 20 μm Rz. The upper region741is an example of a “first region”, the lower region742is an example of a “second region”, and the middle region743is an example of a “third region”.

Next, a method of manufacturing the semiconductor device A10is described below with reference toFIGS.13to15.FIGS.13to15are plan views illustrating processes of manufacturing the semiconductor device A10. The x, y and z directions shown in the figures correspond to those shown inFIGS.1to12.

First, a leadframe80is prepared as shown inFIG.13. The leadframe80is a plate-like material. In this embodiment, the base material of the leadframe80is Cu. The leadframe80may be made from a metal plate by etching and, if necessary, other processing. The leadframe80is a flat frame without depressions. The leadframe80has an obverse surface80A and a reverse surface80B spaced apart from each other in the z direction. The grooves314are formed by half-etching the obverse surface80A. The leadframe80may be formed by punching of a metal plate. In this case, the grooves314are formed by stamping on the obverse surface80A.

The leadframe80includes the electroconductive support member2(the first die pad31, the second die pad32, the third die pad33, the input-side terminals51, the first output-side terminals52, the second output-side terminals53and the pad portions54to56) and additionally includes a frame81, a plurality of first tie bars821, a plurality of second tie bars822and a pair of dam bars83. The frame81, the first tie bars821, the second tie bars822and the dam bars83do not form parts of the semiconductor device A10.

As viewed in the z direction, the frame81is a closed rectangular structure. The frame81surrounds the electroconductive support member2, the first tie bars821, the second tie bars822and the dam bars83. The input-side terminals51are tied to the frame81at their ends on the y1 side in the y direction. The first output-side terminals52and the second output-side terminals53are tied to the frame81at their ends on the y2 side in the y direction.

The first tie bars821extend in the x direction. Each first tie bar821is tied to a pair of second tie bars822at their opposite ends in the x direction. The plurality of first tie bars821include a pair of first tie bars821located on the y1 side in the y direction and a pair of first tie bars821located on the y2 side in the y direction. The input-side terminals51are tied to the pair of first tie bars821located on the y1 side in the y direction. The first output-side terminals52and the second output-side terminals53are tied to the pair of first tie bars821located on the y2 side in the y direction.

The second tie bars822extend in the y direction. Each second tie bar822is tied to a dam bar83at an end in the y direction. The plurality of second tie bars822include a pair of second tie bars822located on the y1 side in the y direction and a pair of second tie bars822located on the y2 side in the y direction. On each of the y1 side and the y2 side, the pair of second tie bars822and the pair of first tie bars821form closed rectangular structure as viewed in the z direction.

The pair of dam bars83are provided at the ends of the leadframe80in the x direction. Each dam bar83extends in the y direction and protrudes toward the electroconductive support member2. Each dam bar83has a cutout portion831. The cutout portions831serve as a gate through which melted resin enters and exits out at the time of molding the sealing resin7.

Next, as shown inFIG.14, the semiconductor control element11, the first insulating element13, and the second insulating element15are bonded to the first die pad31each by a bonding layer69, the first drive element12is bonded to the second die pad32by a bonding layer69, and the second drive element14is bonded to the third die pad33by a bonding layer69. InFIG.14, the bonding layers69are shaded with dots for the purpose of illustration. In the bonding process, a paste of a bonding material, which will be later hardened to form the bonding layers69, is applied to the regions of the first die pad31where the semiconductor control element11, the first insulating element13and the second insulating element15will be placed, the region of the second die pad32where the first drive element12will be placed and the region of the third die pad33where the second drive element14will be placed. Then, the semiconductor control element11, the first drive element12, the first insulating element13, the second drive element14and the second insulating element15are placed on the layers of the applied bonding material. Next, reflowing is performed to melt and then harden the bonding material. Each of the second die pad32and the third die pad33is supported by a single lead like a cantilever. Despite this structure, the leadframe80, being a flat frame, is less likely to be deformed by the mounting of the first drive element12and the second drive element14.

Next, as shown inFIG.14, the wires61to67are formed by wire bonding. The process of forming the wires involves heating the leadframe80while the leadframe80is held by a mold.

The process of forming the wire61begins with lowering a capillary toward the semiconductor control element11and presses the tip of a wire against a target electrode. In this state, by the action of the weight of the capillary, ultrasonic vibrations generated by the capillary, and so on, the wire tip is pressed against the electrode to form a bond. This completes first bonding. Then, the capillary is raised while the wire is continually fed. As a result, a ball bond is formed on the electrode. Next, the capillary is moved to a position directly above a target pad portion54(the middle protrusion313of the first die pad31in the case of forming the wire61c) and then lowered to press the tip of the capillary against the pad portion54. This causes the wire to be sandwiched between the capillary tip and the pad portion54to form a bond. This completes second bonding. Then, the capillary is raised to break the wire.

The process of forming a wire62includes first bonding of a wire to an electrode of the first drive element12, forming a ball bond on the electrode, and second bonding of the wire on a target pad portion55(the second die pad32in the case of forming the wire62a). The process of forming a wire63includes first bonding of a wire to an electrode of the second drive element14, forming a ball bond on the electrode, and second bonding of the wire on a target pad portion56(the third die pad33in the case of forming the wire63a).

The process of forming a wire64includes first bonding of a wire to an electrode of the first insulating element13, forming a ball bond on the electrode, and second bonding of the wire on an electrode of the semiconductor control element11. The process of forming a wire65includes first bonding of a wire to an electrode of the first insulating element13, forming a ball bond on the electrode, and second bonding of the wire on an electrode of the first drive element12. The process of forming a wire66includes first bonding of a wire to an electrode of the second insulating element15, forming a ball bond on the electrode, and second bonding of the wire on an electrode of the semiconductor control element11. The process of forming a wire67includes first bonding of a wire to an electrode of the second insulating element15, forming a ball bond on the electrode, and second bonding of the wire on an electrode of the second drive element14.

Next, a sealing resin7is formed. The sealing resin7is formed by transfer molding. This process includes placing the leadframe80into a mold defining a plurality of cavities88. The leadframe80is placed as shown inFIG.15, such that each portion of the electroconductive support member2to be covered later by the sealing resin7of a produced semiconductor device A10is located within one of the cavities88. Then, melted resin is introduced into the cavities88. The melted resin flows into each cavity88through the inlet gate, which may be the cutout portion831on the x1 side in the x direction, flows along the dashed arrow shown inFIG.15, and out from the cavity88through the outlet gate, which may be the cutout portion831on the x2 side in the x direction.

The melted resin injected into each cavity88is solidified to form the sealing resin7, and resin burrs remaining outside the cavity88are removed by, for example, applying high-pressure water jet. Removing resin burrs from the site of the inlet gate leaves the first gate mark75aon the sealing resin7. Similarly, removing resin burrs from the site of the outlet gate leaves the second gate mark76aon the sealing resin7. This complete the formation of the sealing resin7. Note that the gates used as the inlet and the outlet may be opposite.

Next, dicing is performed to isolate individual pieces, by separating the input-side terminals51, the first output-side terminals52and the second output-side terminals53from the frame81, the first tie bars821, the second tie bars822and the dam bars83. Through the processes described above, the semiconductor device A10is manufactured.

The following describes advantages of the semiconductor device A10.

According to this embodiment, the semiconductor device A10includes the first drive element12that generates a drive signal for a high-side switching element and the second drive element14that generates a drive signal for a low-side switching element. In other words, two switching elements of a half-bridge circuit can be driven by one semiconductor device A10. That is, the semiconductor device A10includes one common semiconductor control element11for driving two switching elements and is more compact than two conventional semiconductor devices each of which includes a semiconductor control element for driving one switching element. The semiconductor device A10can therefore reduce the footprint on the wiring board of an inverter device than the footprint of two conventional semiconductor devices. In addition, the semiconductor device A10does not require spacing that needs to be provided between two conventional semiconductor devices mounted on a wiring board. The footprint of the semiconductor device A10can be further reduced by the area of the spacing.

According to this embodiment, in addition, the semiconductor control element11is offset in the semiconductor device A10to the y1 side in the y direction. Due to this arrangement, the wires61connecting the semiconductor control element11to the pad portions54extend at relatively small angles with the x direction. For example, the wires61aand61bform an angle of 20° or less with the x direction. In addition, the first insulating element13is located between the semiconductor control element11and the first drive element12in the x direction, and the second insulating element15is located between the semiconductor control element11and the second drive element14in the x direction. Due to this arrangement, the wires64to67extend at relatively small angles with the x direction. In the process of forming the sealing resin7(seeFIG.15), melted resin injected into each cavity88flows in the x direction. The wires61and64to67extending in the direction in which the melted resin flows are less likely to be displaced by the flow of melted resin. The wires61and64to67are therefore prevented from contacting or being too close to another wire or an element. In addition, the first drive element12and the second drive element14are offset in the semiconductor device A10to the y2 side in the y direction. The center13aof the first insulating element13is located between the center11aof the semiconductor control element11and the center12aof the first drive element12in the y direction. The center15aof the second insulating element15is located between the center11aof the semiconductor control element11and the center14aof the second drive element14in the y direction. This arrangement can ensure the angles formed by the wires64to67with the x direction are not unduly large. In addition, the wires64and65can be shorter than with the arrangement where the center13aof the first insulating element13is not located between the center11aof the semiconductor control element11and the center12aof the first drive element12. Similarly, the wires66and67can be shorter than with the arrangement in which the center15aof the second insulating element15is not located between the center11aof the semiconductor control element11and the center14aof the second drive element14.

According to this embodiment, in addition, the semiconductor device A10includes the first insulating element13that transmits a signal between the first drive element12and the semiconductor control element11, while providing electrical insulation between the first drive element12and the semiconductor control element11. This configuration can improve the voltage insulation between the input-side circuit, which includes the semiconductor control element11, and the first output-side circuit, which includes the first drive element12, in light of a significant potential difference possibly caused between the first drive element12and the semiconductor control element11. According to this embodiment, in addition, the semiconductor device A10includes the second insulating element15that transmits a signal between the second drive element14and the semiconductor control element11, while providing electrical insulation between the second drive element14and the semiconductor control element11. This configuration can improve the voltage insulation between the input-side circuit, which includes the semiconductor control element11, and the second output-side circuit, which includes the second drive element14, in light of a significant potential difference possibly caused between the second drive element14and the semiconductor control element11. Thus, the semiconductor device A10is operable with the high side and the low side being interchangeable.

According to this embodiment, in addition, the electroconductive support member2includes the first die pad31, the second die pad32, the third die pad33, the input-side terminals51, the first output-side terminals52, the second output-side terminals53and the pad portions54to56. The input-side terminals51are exposed on the side surface73of the sealing resin7, and the first output-side terminals52and the second output-side terminals53are exposed on the side surface74of the sealing resin7. In contrast, no portion of the electroconductive support member2is exposed on the side surfaces75and76of the sealing resin7. For example, the protrusion323of the second die pad32is not exposed on the side surface75of the sealing resin7. That is, the electroconductive support member2can increase the insulation distance between the portions exposed from the sealing resin7and electrically connected to the semiconductor control element11(the exposed portions of the input-side terminals51) and the portions exposed from the sealing resin7and electrically connected to the second die pad32(the creepage distance along the surface of the sealing resin7), as compared with when the protrusion323is provided as a support lead and exposed on the side surface75of the sealing resin7. Also, the protrusion333of the third die pad33is not exposed on the side surface76of the sealing resin7. The electroconductive support member2can increase the insulation distance between the input-side terminals51and the portion of the third die pad33exposed from the sealing resin7as compared with when the protrusion333is provided as a support lead and exposed on the side surface76of the sealing resin7. The semiconductor device A10can therefore improve the voltage insulation as compared with a configuration in which a portion of the electroconductive support member2, such as a support lead, is exposed on the side surface75or76. In addition, without a support lead exposed on the side surface75, design flexibility is allowed in setting the location of the inlet gate (the cutout portion831on the x1 side) through which melted resin enters in the process of forming the sealing resin7(seeFIG.15). Similarly, without a support lead exposed on the side surface76, design flexibility is allowed in setting the location of the outlet gate (the cutout portion831on the x2 side) through which melted resin exits in the process of forming the sealing resin7.

According to this embodiment, in addition, the sealing resin7has a greater surface roughness on the top surface71, the bottom surface72and the upper region731and the lower region732of the side surface73than on the middle region733of the side surface73. Similarly, the sealing resin7has a greater surface roughness on the top surface71, the bottom surface72and the upper region741and the lower region742of the side surface74than on the middle region743of the side surface74. This can increase the creepage distance from the input-side terminal51ato the first output-side terminal52aalong the upper region731of the side surface73, the top surface71and the upper region741of the side surface74, as well as the creepage distance from the input-side terminal51ato the first output-side terminal52aalong the surfaces of the lower region732of the side surface73, the bottom surface72and the lower region742of the side surface74. Consequently, the semiconductor device A10can further improve the voltage insulation.

According to this embodiment, in addition, the first inter-terminal distance L1(the distance between the portion of the first output-side terminal52bexposed from the sealing resin7and the portion of the second output-side terminal53bexposed from the sealing resin7) is at least three times greater than the second inter-terminal distance L2(the distance between the portions of two adjacent first output-side terminals52exposed from the sealing resin7). That is, a sufficient separation distance is provided between the exposed portions of the first output-side terminals52and the exposed portions of the second output-side terminals53in the x direction. Although a significant potential difference may occur between the first output-side terminals52and the second output-side terminals53, the semiconductor device A10provided with the sufficient separation distance can ensure high voltage insulation. In addition, the electroconductive support member2does not have any portion exposed in the region of the side surface74of the sealing resin7between the first output-side terminal52band the second output-side terminal53b, and thus no metal part is present in that region. This means that a relatively long insulation distance is provided between the first output-side terminals52and the second output-side terminals53. The semiconductor device A10can therefore ensure high voltage insulation as compared with a configuration in which a portion of the electroconductive support member2, such as a support lead, is exposed on the side surface74.

According to this embodiment, in addition, the side surface75of the sealing resin7includes the first gate mark75ahaving a rougher surface than the other region of the side surface75. The first gate mark75ais formed as a result of the process of forming the sealing resin7(seeFIG.15) during the manufacture of the semiconductor device A10, at the site of the inlet gate (the cutout portion831on the x1 side) through which melted resin enters. As shown inFIG.1, the first gate mark75ais offset to the y1 side in the y direction. Similarly, the side surface76of the sealing resin7includes the second gate mark76ahaving a rougher surface than the other region of the side surface76. The second gate mark76ais formed as a result of the process of forming the sealing resin7during the manufacture of the semiconductor device A10, at the site of the outlet gate (the cutout portion831on the x2 side) through which melted resin exits. As shown inFIG.1, the second gate mark76ais offset to the y2 side in the y direction. This means that the melted resin injected in the process of forming the sealing resin7flows along a diagonal line across the cavity88. This is effective for preventing formation of voids in the sealing resin7.

According to this embodiment, the wire61adoes not overlap with the first insulating element13as viewed in the z direction. That is, the wire61ais prevented from contacting or being too close to the first insulating element13. Similarly, the wire61bdoes not overlap with the second insulating element15as viewed in the z direction. That is, the wire61cis prevented from contacting or being too close to the second insulating element15. The wires61aand61bare connected to the semiconductor control element11and are components of the input-side circuit, which is held at a relatively low potential. The first insulating elements13and the second insulating element15include portions of the first and second output-side circuits, which are held at a relatively high potential. Preventing the wire61afrom being too close to the first insulating element13and the wire61bfrom being too close to the second insulating element15serves to improve the voltage insulation of the semiconductor device A10. According to this embodiment, in addition, although the wire61amay be pushed by the melted resin that flows through the inlet gate (the cutout portion831on the x1 side) in the process of forming the sealing resin7(seeFIG.15), the wire61ais pushed in a direction away from the first insulating element13. That is, the wire61ais prevented from being too close to the first insulating element13.

Although this embodiment describes the first gate mark75aas being offset to the y1 side in the y direction and the second gate mark76ato the y2 side, the present disclosure is not limited to this. The locations of the first gate mark75aand the second gate mark76aare not specifically limited. In other words, in the manufacture of the semiconductor device A10, the locations of the inlet gate and the outlet gate used in the process of forming the sealing resin7are not specifically limited. For example, the first gate mark75amay be located offset to the y2 side in the y direction and the second gate mark76ato the y1 side. This arrangement can still ensure that the melted resin injected in the process of forming the sealing resin7flows along a diagonal line across the cavity88. This is effective for preventing formation of voids in the sealing resin7. In another example, the first gate mark75aand the second gate mark76amay be both located offset to the y1 side in the y direction, both located offset to the y2 side in the y direction or both located offset to the center in the y direction. Since the semiconductor device A10of this embodiment has no support lead exposed on the side surfaces75and76, the locations of the inlet gate and the outlet gate can be flexibly determined.

Although this embodiment describes the electroconductive support member2not exposed on the side surfaces75and76, the present disclosure is not limited to this. The electroconductive support member2may include a support lead exposed on the side surface75or76.

In addition, although this embodiment describes the sealing resin7having a greater surface roughness on the top surface71, the bottom surface72, the upper region731and the lower region732of the side surface73and the upper region741and the lower region742of the side surface74than on the middle region733of the side surface73and the middle region743of the side surface74, the present disclosure is not limited to this. For example, the sealing resin7may have about the same level of surface roughness on each of the surfaces71to76. In such a case, the surface roughness of each of the surfaces71to76of the sealing resin7may be relatively small or relatively great (e.g., between 5 and 20 μm Rz).

FIGS.16to20show other embodiments of the present disclosure. In these figures, the elements identical or similar to those of the embodiment described above are denoted by the same reference signs.

FIG.16is a view illustrating a semiconductor device A20according to a second embodiment of the present disclosure.FIG.16is a plan view of the semiconductor device A20and corresponds toFIG.2. For convenience,FIG.16shows the sealing resin7as transparent and shows the outline of the sealing resin7in phantom (two-dot-dash lines). The semiconductor device A20of this embodiment is different from the first embodiment in that the first insulating element13is mounted on the second die pad32and the second insulating element15is mounted on the third die pad33.

The first die pad31of this embodiment has a smaller x-direction dimension than in the first embodiment. The second die pad32and the third die pad33have greater x-direction dimensions than in the first embodiment. In this embodiment, the first insulating element13is mounted on the second die pad32, whereas the second insulating element15is mounted on the third die pad33.

Also in this embodiment, the semiconductor device A20includes the semiconductor control element11, the first drive element12and the second drive element14and thus is capable of driving two switching elements of a half-bridge circuit. The semiconductor device A20can be more compact than two conventional semiconductor devices together and can therefore reduce the footprint on the wiring board of an inverter device. In addition, the footprint of the semiconductor device A20can be further reduced as the spacing required between two conventional semiconductor devices is not necessary. In addition, the semiconductor device A20includes the same configuration as that of the semiconductor device A10and can therefore achieve the same advantages as the semiconductor device A10.

FIG.17is a view illustrating a semiconductor device A30according to a third embodiment of the present disclosure.FIG.17is a plan view of the semiconductor device A30and corresponds toFIG.1. The semiconductor device A30of this embodiment differs from the first embodiment in that the sealing resin7is formed with grooves.

In this embodiment, the sealing resin7additionally includes a first groove74band a second groove75b. The first groove74bis recessed from the side surface74in the y direction and extends in z direction from the top surface71to the bottom surface72. The sealing resin7of this embodiment includes, but not limited to, three first grooves74bat equal intervals in the x direction. The first grooves74bare rectangular as viewed in the z direction. The shape of each first groove74bas viewed in the z direction is not limited to this and may be semi-circular, for example. The first grooves74bare located in a region of the side surface74between the first output-side terminal52band the second output-side terminal53b. The second groove75bis recessed from the side surface75in the x direction and extends in z direction from the top surface71to the bottom surface72. The sealing resin7of this embodiment includes three second grooves75bat equal intervals in the y direction. The number and the location of the second grooves75bto be provided are not limited. The second grooves75bare rectangular as viewed in the z direction. The shape of each second groove75bas viewed in the z direction is not limited to this and may be semi-circular, for example. The second grooves75bare formed in a region of the side surface75other than the first gate mark75a. The sealing resin7may additionally include one or more third grooves recessed from the side surface76in the x direction and extending in the z direction from the top surface71to the bottom surface72.

Also in this embodiment, the semiconductor device A30includes the semiconductor control element11, the first drive element12and the second drive element14and thus is capable of driving two switching elements of a half-bridge circuit. The semiconductor device A30can be more compact than two conventional semiconductor devices together and can therefore reduce the footprint on the wiring board of an inverter device. In addition, the footprint of the semiconductor device A30can be further reduced as the spacing required between two conventional semiconductor devices is not necessary. In addition, the semiconductor device A30includes the same configuration as that of the semiconductor device A10and can therefore achieve the same advantages as the semiconductor device A10.

According to this embodiment, in addition, the sealing resin7has the first grooves74bin a region of the side surface74between the first output-side terminal52band the second output-side terminal53b. The creepage distance from the first output-side terminal52bto the second output-side terminal53balong the side surface74is greater with the first grooves74bthan without. Consequently, the semiconductor device A30can further improve the voltage insulation. In addition, the sealing resin7has the second grooves75bon the side surface75. The creepage distance from the input-side terminal51ato the first output-side terminal52aalong the side surfaces73,75and74of the sealing resin7is greater with the second grooves75bthan without. Consequently, the semiconductor device A30can further improve the voltage insulation.

FIG.18is a view illustrating a semiconductor device A40according to a fourth embodiment of the present disclosure.FIG.18is a plan view of the semiconductor device A40and corresponds toFIG.1. The semiconductor device A40of this embodiment differs from the first embodiment in that the sealing resin7is formed with protrusions.

The sealing resin7of this embodiment includes a first protrusion74cand a second protrusion75c. The first protrusion74cprotrudes from the side surface74in the y direction and extends in z direction from the top surface71to the bottom surface72. The sealing resin7of this embodiment includes, but not limited to, three first protrusions74cat equal intervals in the x direction. The first protrusions74care rectangular as viewed in the z direction. The shape of each first protrusion74cas viewed in the z direction is not limited to this and may be semi-circular, for example. The first protrusions74care located in a region of the side surface74between the first output-side terminal52band the second output-side terminal53b.The second protrusion75cprotrudes from the side surface75in the x direction and extends in z direction from the top surface71to the bottom surface72. The sealing resin7of this embodiment includes three second protrusions75cat equal intervals in the y direction. The number and the location of the second protrusions75cto be provided are not limited. The second protrusions75care rectangular as viewed in the z direction. The shape of each second protrusion75cas viewed in the z direction is not limited to this and may be semi-circular, for example. The second protrusions75care formed in a region of the side surface75other than the first gate mark75a. The sealing resin7may additionally include one or more third protrusions protruding from the side surface76in the x direction and extending in the z direction from the top surface71to the bottom surface72.

Also in this embodiment, the semiconductor device A40includes the semiconductor control element11, the first drive element12and the second drive element14and thus is capable of driving two switching elements of a half-bridge circuit. The semiconductor device A40can be more compact than two conventional semiconductor devices together and can therefore reduce the footprint on the wiring board of an inverter device. In addition, the footprint of the semiconductor device A40can be further reduced as the spacing required between two conventional semiconductor devices is not necessary. In addition, the semiconductor device A40includes the same configuration as that of the semiconductor device A10and can therefore achieve the same advantages as the semiconductor device A10.

According to this embodiment, in addition, the sealing resin7has the first protrusions74cin a region of the side surface74between the first output-side terminal52band the second output-side terminal53b. The creepage distance from the first output-side terminal52bto the second output-side terminal53balong the side surface74is greater with the first protrusions74cthan without. Consequently, the semiconductor device A40can further improve the voltage insulation. In addition, the sealing resin7has the second protrusions75con the side surface75. The creepage distance from the input-side terminal51ato the first output-side terminal52aalong the side surfaces73,75and74of the sealing resin7is greater with the second protrusions75cthan without. Consequently, the semiconductor device A40can further improve the voltage insulation.

FIG.19is a view illustrating a semiconductor device A50according to a fifth embodiment of the present disclosure.FIG.19is a plan view of the semiconductor device A50and corresponds toFIG.2. For convenience,FIG.19shows the sealing resin7as transparent and shows the outline of the sealing resin7in phantom (two-dot-dash lines). The semiconductor device A50of this embodiment differs from the first embodiment in that the first die pad31, the second die pad32and the third die pad33are each additionally supported by a support lead.

The first die pad31of this embodiment includes a support lead315instead of the middle one of the three protrusions313. The support lead315protrudes outward from the side surface of the first die pad31on the y2 side in the y direction and supports the first die pad31. The end surface of the support lead315on the y2 side in the y direction is exposed on the side surface74of the sealing resin7. The support lead315is a portion that is tied to the first die pad31and a first tie bar821in the leadframe80and cut off from the first tie bar821in the dicing process. The cut surface formed by this cutting is the end surface on the y2 side in the y direction and exposed on the side surface74of the sealing resin7.

In addition, the second die pad32of this embodiment includes a support lead324instead of the protrusion323. The support lead324protrudes outward from the side surface of the second die pad32on the x1 side in the x direction and supports the second die pad32. The end surface of the support lead324on the x1 side in the x direction is exposed on the side surface75of the sealing resin7. The support lead324is a portion that is tied to the second die pad32and a dam bar83in the leadframe80and cut off from the dam bar83in the dicing process. The cut surface formed by this cutting is the end surface on the x1 side in the x direction and exposed on the side surface75of the sealing resin7.

In addition, the third die pad33of this embodiment includes a support lead334instead of the protrusion333. The support lead334protrudes outward from the side surface of the third die pad33on the x2 side in the x direction and supports the third die pad33. The end surface of the support lead334on the x2 side in the x direction is exposed on the side surface76of the sealing resin7. The support lead334is a portion that is tied to the third die pad33and a dam bar83in the leadframe80and cut off from the dam bar83in the dicing process. The cut surface formed by this cutting is the end surface on the x2 side in the x direction and exposed on the side surface76of the sealing resin7.

Also in this embodiment, the semiconductor device A50includes the semiconductor control element11, the first drive element12and the second drive element14and thus is capable of driving two switching elements of a half-bridge circuit. The semiconductor device A50can be more compact than two conventional semiconductor devices together and can therefore reduce the footprint on the wiring board of an inverter device. In addition, the footprint of the semiconductor device A50can be further reduced as the spacing required between two conventional semiconductor devices is not necessary. In addition, the semiconductor device A50includes the same configuration as that of the semiconductor device A10and can therefore achieve the same advantages as the semiconductor device A10.

According to this embodiment, the support lead315provides additional support to the first die pad31. The first die pad31can therefore be held more stable during the process of bonding the semiconductor control element11, the first insulating element13and the second insulating element15to the first die pad31and also during the process of forming the wires61. In addition, the support lead324provides additional support to the second die pad32. The second die pad32can therefore be held more stable during the process of bonding the first drive element12to the second die pad32and also during the process of forming the wires62. In addition, the support lead334provides additional support to the third die pad33. The third die pad33can therefore be held more stable during the process of bonding the second drive element14to the third die pad33and also during the process of forming the wires63.

FIG.20is a view illustrating a semiconductor device A60according to a sixth embodiment of the present disclosure.FIG.20is a plan view of the semiconductor device A60and corresponds toFIG.2. For convenience,FIG.20shows the sealing resin7as transparent and shows the outline of the sealing resin7in phantom (two-dot-dash lines). The semiconductor device A60of this embodiment differs from the first embodiment in that the semiconductor control element11, the first drive element12, the first insulating element13, the second drive element14and the second insulating element15are aligned in the x direction.

According to this embodiment, the center11aof the semiconductor control element11, the center12aof the first drive element12, the center13aof the first insulating element13, the center14aof the second drive element14, and the center15aof the second insulating element15are aligned in the x direction.

Also in this embodiment, the semiconductor device A60includes the semiconductor control element11, the first drive element12and the second drive element14and thus is capable of driving two switching elements of a half-bridge circuit. The semiconductor device A60can be more compact than two conventional semiconductor devices together and can therefore reduce the footprint on the wiring board of an inverter device. In addition, the footprint of the semiconductor device A60can be further reduced as the spacing required between two conventional semiconductor devices is not necessary. In addition, the semiconductor device A60includes the same configuration as that of the semiconductor device A10and can therefore achieve the same advantages as the semiconductor device A10.

The semiconductor device according to the present disclosure is not limited to the foregoing embodiments. Various design changes can be made to the specific configuration of each part of the semiconductor device according to present disclosure. The present disclosure covers the embodiments described in the following clauses.

A semiconductor device comprising:a semiconductor control element;a first drive element spaced apart from the semiconductor control element to a first side in a first direction perpendicular to a thickness direction of the semiconductor control element, the first drive element receiving a signal transmitted from the semiconductor control element;a second drive element spaced apart from the semiconductor control element to a second side opposite the first side in the first direction, the second drive element receiving a signal transmitted from the semiconductor control element;a first insulating element located between the semiconductor control element and the first drive element in the first direction, the first insulating element relaying a signal transmitted from the semiconductor control element to the first drive element and providing electrical insulation between the semiconductor control element and the first drive element;a second insulating element located between the semiconductor control element and the second drive element in the first direction, the second insulating element relaying a signal transmitted from the semiconductor control element to the second drive element and providing electrical insulation between the semiconductor control element and the second drive element; anda sealing resin covering the semiconductor control element.

The semiconductor device according to Clause 1, further comprising an electroconductive support member including a first die pad on which the semiconductor control element is mounted, a second die pad on which the first drive element is mounted and a third die pad on which the second drive element is mounted.

The semiconductor device according to Clause 2, wherein the first insulating element and the second insulating element are mounted on the first die pad.

The semiconductor device according to Clause 2, wherein the first insulating element is mounted on the second die pad, andthe second insulating element is mounted on the third die pad.

The semiconductor device according to any one of Clauses 2 to 4, wherein the electroconductive support member includes a plurality of input-side terminals arranged side by side in the first direction, and at least one of the plurality of input-side terminals is electrically connected to the semiconductor control element.

The semiconductor device according to Clause 5, further comprising a first wire and a second wire,wherein the plurality of input-side terminals include an input-side first terminal that is located farthest on the first side and an input-side second terminal that is located farthest on the second side,the first wire electrically connects the semiconductor control element and the input-side first terminal and does not overlap with the first insulating element as viewed in the thickness direction, andthe second wire electrically connects the semiconductor control element and the input-side second terminal and does not overlap with the second insulating element as viewed in the thickness direction.

The semiconductor device according to Clause 6, wherein each of the first wire and the second wire forms an angle of 20° or less with the first direction.

The semiconductor device according to any one of Clauses 5 to 7, wherein the plurality of input-side terminals includes an input-side support terminal connected to the first die pad.

The semiconductor device according to any one of Clauses 2 to 8, wherein the electroconductive support member includes:a plurality of first output-side terminals arranged side by side in the first direction, at least one of the plurality of first output-side terminals being electrically connected to the first drive element; anda plurality of second output-side terminals arranged side by side in the first direction on the second side with respect to the plurality of first output-side terminal, at least one of the plurality of second output-side terminals being electrically connected to the second drive element.

The semiconductor device according to Clause 9, wherein the plurality of first output-side terminals include a single first output-side support terminal connected to the second die pad, andthe plurality of second output-side terminals include a single second output-side support terminal connected to the third die pad.

The semiconductor device according to Clause 9 or 10, wherein each of the plurality of first output-side terminals includes a first exposed portion that is exposed from the sealing resin, and each of the plurality of second output-side terminals includes a second exposed portion that is exposed from the sealing resin, andthe plurality of first output-side terminals include a first output-side innermost terminal that is located farthest on the second side, and the plurality of second output-side terminals include a second output-side innermost terminal that is located farthest on the first side,the first exposed portion of the first output-side innermost terminal and the second exposed portion of the second output-side innermost terminal are spaced apart from each other by a first inter-terminal distance,the plurality of first exposed portions are spaced apart from each other to define one or more separation distances between each pair of two adjacent first exposed portions of the plurality first exposed portions, and a greatest one of the separation distances is defined as a second inter-terminal distance, andthe first inter-terminal distance is at least three times greater than the second inter-terminal distance.

The semiconductor device according to Clause 11, wherein the sealing resin includes a first side surface from which the plurality of first output-side terminals and the plurality of second output-side terminals protrude, andthe electroconductive support member is not exposed in a region of the first side surface between the first output-side innermost terminal and the second output-side innermost terminal.

The semiconductor device according to Clause 12, wherein the sealing resin includes a first groove recessed from the first side surface and extending in the thickness direction, andthe first groove is located between the first output-side innermost terminal and the second output-side innermost terminal in the first direction.

The semiconductor device according to Clause 12 or 13, wherein the sealing resin includes a top surface located on a side opposite the first die pad with respect to the semiconductor control element in the thickness direction and a bottom surface opposite the top surface in the thickness direction,the first side surface includes a first region connected to the top surface, a second region connected to the bottom surface, and a third region connected to the first region and the second region and from which the plurality of first output-side terminals and the plurality of second output-side terminals protrude, andthe top surface, the bottom surface, the first region and the second region each have a greater surface roughness than the third region.

The semiconductor device according to any one of Clauses 2 to 14, wherein in a second direction perpendicular to the thickness direction and the first direction, the first insulating element has a center between a center of the semiconductor control element and a center of the first drive element and the second insulating element has a center between the center of the semiconductor control element and a center of the second drive element, andthe center of the first drive element and the center of the second drive element are located on a same side in the second direction with respect to the center of the semiconductor control element.

The semiconductor device according to Clause 15, wherein the sealing resin includes a second side surface located on the first side in the first direction, andthe electroconductive support member is not exposed on the second side surface.

The semiconductor device according to Clause 16, wherein the sealing resin includes a second groove recessed from the second side surface in the first direction and extending in the thickness direction.

The semiconductor device according to Clause 16 or 17, wherein the second side surface includes a first gate mark having a greater surface roughness than another region of the second side surface, andthe first gate mark is offset in the second direction to a side closer to the center of the semiconductor control element with respect to the center of the first drive element.

The semiconductor device according to Clause 18, wherein the sealing resin includes a third side surface located on the second side in the first direction,the third side surface includes a second gate mark having a greater surface roughness than another region of the third side surface, andthe second gate mark is offset in the second direction to a side opposite the center of the semiconductor control element with respect to the center of the second drive element.

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