Illuminated socket

In one embodiment an electronic device comprises a housing, a socket in the housing to receive a connector, and an illumination source proximate the socket to illuminate the socket. Other embodiments may be described.

RELATED APPLICATIONS

BACKGROUND

The subject matter described herein relates generally to the field of electronic devices and more particularly to illuminated sockets in electronic devices.

Electronic devices such as laptops, desktops, tablet devices, mobile phones, electronic readers, and the like commonly include multiple sockets to receive connectors for charging or to couple with other devices. Electronic devices are frequently used in poor lighting conditions which can make it difficult to locate the appropriate socket on the device. Accordingly, techniques to illuminate a socket may find utility.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth to provide a thorough understanding of various embodiments. However, it will be understood by those skilled in the art that the various embodiments may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been illustrated or described in detail so as not to obscure the particular embodiments.

Described herein are exemplary electronic devices adapted to include an illuminated socket. Various embodiments described herein adapt enable electronic devices, e.g., smart phones, laptop computers, tablet computers, electronic readers, and desktop computers and the like to include one or more illuminated sockets. By way of example, sockets for power cords, universal serial bus (USB) connectors, high-definition multimedia interface (HDMI) connectors, audio/visual (A/V) connectors, or the like. Further, in some examples the electronic device may be provided with one or more sensors to monitor conditions in the environment surrounding the socket and logic to manage conditions under which the socket(s) may be illuminated.

FIG. 1is a schematic illustration of an electronic device100which may be adapted to include an illuminated socket in accordance with some examples. In one example, electronic device100includes one or more accompanying input/output devices including a display102having a screen104, one or more speakers106, a keyboard110, one or more other I/O device(s)112, and a mouse114. The other I/O device(s)112may include a touch screen, a voice-activated input device, a track ball, a geolocation device, an accelerometer/gyrometer and any other device that allows the electronic device100to receive input from a user.

In various embodiments, the electronic device100may be embodied as a personal computer, a laptop computer, a personal digital assistant, a mobile telephone, an entertainment device, or another computing device. The electronic device100includes system hardware120and memory130, which may be implemented as random access memory and/or read-only memory. A file store180may be communicatively coupled to electronic device100. File store180may be internal to computing device108such as, e.g., one or more hard drives, CD-ROM drives, DVD-ROM drives, or other types of storage devices. File store180may also be external electronic device100such as, e.g., one or more external hard drives, network attached storage, or a separate storage network.

System hardware120may include one or more processors122, graphics processors124, network interfaces126, and bus structures128. In one embodiment, processor122may be embodied as an Intel® Core2 Duo® processor available from Intel Corporation, Santa Clara, Calif., USA. As used herein, the term “processor” means any type of computational element, such as but not limited to, a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or any other type of processor or processing circuit.

Graphics processor(s)124may function as adjunct processor that manages graphics and/or video operations. Graphics processor(s)124may be integrated into the packaging of processor(s)122, onto the motherboard of computing system100or may be coupled via an expansion slot on the motherboard.

In one embodiment, network interface126could be a wired interface such as an Ethernet interface (see, e.g., Institute of Electrical and Electronics Engineers/IEEE 802.3-2002) or a wireless interface such as an IEEE 802.11a, b or g-compliant interface (see, e.g., IEEE Standard for IT-Telecommunications and information exchange between systems LAN/MAN—Part II: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications Amendment 4: Further Higher Data Rate Extension in the 2.4 GHz Band, 802.11G-2003). Another example of a wireless interface would be a general packet radio service (GPRS) interface (see, e.g., Guidelines on GPRS Handset Requirements, Global System for Mobile Communications/GSM Association, Ver. 3.0.1, December 2002).

Memory130may include an operating system140for managing operations of computing device108. In one embodiment, operating system140includes a hardware interface module154that provides an interface to system hardware120. In addition, operating system140may include a file system150that manages files used in the operation of computing device108and a process control subsystem152that manages processes executing on electronic device100.

Operating system140may include (or manage) one or more communication interfaces that may operate in conjunction with system hardware120to transceive data packets and/or data streams from a remote source. Operating system140may further include a system call interface module142that provides an interface between the operating system140and one or more application modules resident in memory130. Operating system140may be embodied as a UNIX operating system or any derivative thereof (e.g., Linux, Solaris, etc.) or as a Windows® brand operating system, or other operating systems.

Memory130may comprise one or more applications which execute on the processor(s)122. The applications may be stored in permanent memory such as file store180when not in use by the electronic device100. In use, the applications may be copied into memory130for execution. In the embodiment depicted inFIG. 1the applications comprise an illumination manager160.

In some embodiments electronic device100may comprise a low-power embedded processor, referred to herein as a controller170. The controller170may be implemented as an independent integrated circuit located on the motherboard of the system100. In the embodiment depicted inFIG. 1the controller170comprises a processor172, a memory module174, and an I/O module176. In some embodiments the memory module174may comprise a persistent flash memory module and the authentication module174may be implemented as logic instructions encoded in the persistent memory module, e.g., firmware or software. The I/O module178may comprise a serial I/O module or a parallel I/O module. Because the adjunct controller170is physically separate from the main processor(s)122and operating system140, the adjunct controller170may be made secure, i.e., inaccessible to hackers such that it cannot be tampered with. In some embodiments the illumination manager160may be implemented in the controller170such that the illumination manager160operates in a low power consumption environment.

FIG. 2is a schematic illustration of another embodiment of an electronic device210which may be adapted to include an illuminated socket, according to embodiments. In some embodiments electronic device210may be embodied as a mobile telephone, a personal digital assistant (PDA), a tablet computer, or the like. Electronic device210may include an RF transceiver220to transceive RF signals and a signal processing module222to process signals received by RF transceiver220.

RF transceiver220may implement a local wireless connection via a protocol such as, e.g., Bluetooth or 802.11X. IEEE 802.11a, b or g-compliant interface (see, e.g., IEEE Standard for IT-Telecommunications and information exchange between systems LAN/MAN—Part II: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications Amendment 4: Further Higher Data Rate Extension in the 2.4 GHz Band, 802.11G-2003). Another example of a wireless interface would be a general packet radio service (GPRS) interface (see, e.g., Guidelines on GPRS Handset Requirements, Global System for Mobile Communications/GSM Association, Ver. 3.0.1, December 2002).

Electronic device210may further include one or more processors224and a memory module240. As used herein, the term “processor” means any type of computational element, such as but not limited to, a microprocessor, a microcontroller, a complex instruction set computing (CISC) microprocessor, a reduced instruction set (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or any other type of processor or processing circuit. In some embodiments, processor224may be one or more processors in the family of Intel® PXA27x processors available from Intel® Corporation of Santa Clara, Calif. Alternatively, other CPUs may be used, such as Intel's Itanium®, XEON™, ATOM™, and Celeron® processors. Also, one or more processors from other manufactures may be utilized. Moreover, the processors may have a single or multi core design.

In some embodiments, memory module240includes random access memory (RAM); however, memory module240may be implemented using other memory types such as dynamic RAM (DRAM), synchronous DRAM (SDRAM), and the like. Memory240may comprise one or more applications which execute on the processor(s)222. In the embodiment depicted inFIG. 2the applications comprise an illumination manager260.

Electronic device210may further include one or more input/output interfaces such as, e.g., a keypad226and one or more displays228. In some embodiments electronic device210comprises one or more camera modules230and an image signal processor232, and speakers234.

In some embodiments electronic device210may include a controller270which may be implemented in a manner analogous to that of controller170, described above. In the embodiment depicted inFIG. 2the adjunct controller270comprises one or more processor(s)272, a memory module274, and an I/O module276. In some embodiments the memory module274may comprise a persistent flash memory module and the authentication module276may be implemented as logic instructions encoded in the persistent memory module, e.g., firmware or software. The I/O module276may comprise a serial I/O module or a parallel I/O module. Again, because the adjunct controller270is physically separate from the main processor(s)224, the adjunct controller270may be made secure, i.e., inaccessible to hackers such that it cannot be tampered with. In some embodiments the illumination manager260may be implemented in the controller270such that the illumination manager260operates in a low power consumption environment.

FIG. 3is a high-level schematic illustration of an exemplary architecture for an electronic device adapted to include an illuminated socket in accordance with some embodiments. Referring toFIG. 3, an electronic device300may comprise a housing310which includes one or more sockets320to receive a connector to couple the electronic device300with an external device. The specific type of socket320is not critical. Many electronic devices are equipped with one or more universal serial bus (USB) sockets, high-definition multimedia interface (HDMI) sockets, audio/visual (A/V) sockets, power sockets or the like.

As described herein, an illumination source such as one or more light emitting diodes (LEDs)330may be positioned proximate the socket(s)320to illuminate the environment proximate the socket(s)320. The light emitting diode(s)330may be pointed directed into the ambient environment. Alternatively, or in addition, the light emitting diode(s)330may be coupled to a light pipe panel332which surrounds at least a portion of the sockets320. Light pipe panel332may be implemented as a panel formed from a light-transmissive material, e.g., a polymer or glass. Light from LED330may be injected at a first end of light pipe pane.332and propagates along the length of panel332, typically via total internal reflection (TIR). Light pipe panel332may include diffusers which may be implemented as impurities that cause light incident on the impurity to reflect at an angle outside the TIR angle such that it is emitted from the front surface of the panel332. Alternatively, the panel332may include a structured surface that allows light to be emitted or may be made from a material that has a graded index of refraction along its length such that light exits the panel332.

Electronic device300may comprise one or more sensors such as an accelerometer340, an orientation sensor342, a gyrometer344, a proximity detector346, or a photodetector348and a near field communication (NFC) device352. An illumination manager360in an electronic device300may be implemented as logic instructions executable on one or more processors350, i.e., as software, firmware or the like. Alternatively, illumination manager may be reduced to hardwired circuitry, e.g., as an application specific integrated circuit (ASIC) or as a portion of an integrated circuit in electronic device300.

As described above, in some embodiments the illumination manager360implements logic which enables a user of electronic device300to configure the illumination source(s)330to illuminate the environment surrounding the socket(s)320in response to environmental conditions. In some embodiments the illumination manager360monitors conditions proximate the one or more socket(s)320via the sensors and activates the illumination source330in response to a determination that at least one of the conditions are satisfied. Operations implemented by illumination manager360will be described with reference toFIG. 4andFIG. 5.

FIG. 4is a flowchart illustrating operations implemented by illumination manager360in an electronic device300. Referring toFIG. 4, at operation410the illumination manager receives one or more illumination configuration parameters. In some examples the illumination manager may present an interactive user interface, such as the user interface500depicted inFIG. 5, through which a user may enter one or more illumination configuration parameters.

For example, the configuration parameters may include a clock parameter510which allows a user to enter a start time at which the illumination source330may be activated and a stop time after which the illumination source330may not be activated. If the clock parameter is set to ON then the illumination source330may be illuminated only between the start time and the stop time. By contrast, if the clock parameter is set to OFF then there are no time limitations are enforced.

The configuration parameters may further include a photodetector parameter which allows a user to enter a brightness level above which the illumination source will not be operable. If the photodetector parameter is set to ON then the illumination source330may be illuminated only when the photodetector output is below the selected brightness. By contrast, if the photodetector parameter is set to OFF then there are no brightness limitations are enforced.

The configuration parameters may further include a proximity sensor parameter540which allows a user to enter a proximity level. If the proximity sensor is set to ON then when the proximity sensor detects an object that is closer than the proximity sensor parameter the illumination source330may be illuminated. By contrast, if the photodetector parameter is set to OFF then there are no proximity limitations are enforced.

The configuration parameters may further include a motion sensor parameter550which allows a user to enter a motion detector sensitivity level. If the motion sensor is set to ON then when the motion sensor detects an object moving the illumination source330may be illuminated. By contrast, if the motion sensor parameter is set to OFF then there are no brightness limitations enforced.

The configuration parameters may further include a duration timer parameter560which allows a user to enter a time duration for which the illumination sources are to remain activated. If the time duration parameter is set to ON then the illumination source330may be illuminated for a time duration indicated by the time duration parameter. By contrast, if the motion sensor parameter is set to OFF then there are no time duration limitations enforced.

The configuration parameters may further include off on connection parameter570which allows a user to select whether the illumination source330should be turned off when a connection to an external device is detected on one of the sockets. If the time duration parameter is set to ON then the illumination source330may be turned off when a connection is detected. By contrast, if the motion sensor parameter is set to OFF then there are no connection limitations enforced.

In various examples the illumination manager may allow a user to enter more or fewer configuration parameters via the user interface500. Once entered, the parameters are used to configure (operation415) the illumination manager.

At operation420the illumination manager360monitors the sensor conditions by monitoring the outputs of the various sensors on the electronic device300. If, at operation425none of the sensors produce an output which indicates that one or more of the illumination configuration parameters are satisfied then control passes back to operation420and the illumination manager360continues to monitor the sensor conditions.

By contrast, if at operation425one or more of sensors produce an output which indicates that the illumination conditions are satisfied then control passes to operation430and the illumination source(s)330are activated to illuminate the environment proximate the socket(s)320.

For example, a user may configure the illumination manager360to activate the illumination source(s)330only when an output from the photodetector348indicates that the environment proximate the at least one socket is dark, and/or only when an output from the proximity detector346indicates that an object is proximate the at least one socket320, and/or in response to a motion imparted to the electronic device.

For example, the near field communication (NFC) device352may be configured to detect when a near field communication (NFC) device on a male plug adapted to mate with one or more of the socket(s)320is in communication with the NFC device352.

If, at operation435a termination condition is not satisfied then control passes back to operation420and the illumination manager360continues to monitor the sensor conditions. By contrast, if at operation435a termination condition is satisfied then control passes to operation440and the illumination manager360terminates the illumination source.

For example, the configuration manager360may deactivate the illumination source330after a predetermined period of time, and or in response to detecting a connection with a remote device on the socket.

Thus, the illumination manager360enables a user of the electronic device300to set configuration parameters which are then used to manage the illumination of illumination source(s)330. It will be recognized that additional configuration parameters may be incorporated into the configuration manager360.

As described above, in some embodiments the electronic device may be embodied as a computer system.FIG. 6illustrates a block diagram of a computing system600in accordance with an embodiment of the invention. The computing system600may include one or more central processing unit(s) (CPUs)602or processors that communicate via an interconnection network (or bus)604. The processors602may include a general purpose processor, a network processor (that processes data communicated over a computer network603), or other types of a processor (including a reduced instruction set computer (RISC) processor or a complex instruction set computer (CISC)). Moreover, the processors602may have a single or multiple core design. The processors602with a multiple core design may integrate different types of processor cores on the same integrated circuit (IC) die. Also, the processors602with a multiple core design may be implemented as symmetrical or asymmetrical multiprocessors. In an embodiment, one or more of the processors602may be the same or similar to the processors102ofFIG. 1. For example, one or more of the processors602may include the control unit120discussed with reference toFIGS. 1-3. Also, the operations discussed with reference toFIGS. 3-5may be performed by one or more components of the system600.

A chipset606may also communicate with the interconnection network604. The chipset606may include a memory control hub (MCH)608. The MCH608may include a memory controller610that communicates with a memory612(which may be the same or similar to the memory130ofFIG. 1). The memory412may store data, including sequences of instructions, that may be executed by the CPU602, or any other device included in the computing system600. In one embodiment of the invention, the memory612may include one or more volatile storage (or memory) devices such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or other types of storage devices. Nonvolatile memory may also be utilized such as a hard disk. Additional devices may communicate via the interconnection network604, such as multiple CPUs and/or multiple system memories.

The MCH608may also include a graphics interface614that communicates with a display device616. In one embodiment of the invention, the graphics interface614may communicate with the display device616via an accelerated graphics port (AGP). In an embodiment of the invention, the display616(such as a flat panel display) may communicate with the graphics interface614through, for example, a signal converter that translates a digital representation of an image stored in a storage device such as video memory or system memory into display signals that are interpreted and displayed by the display616. The display signals produced by the display device may pass through various control devices before being interpreted by and subsequently displayed on the display616.

A hub interface618may allow the MCH608and an input/output control hub (ICH)620to communicate. The ICH620may provide an interface to I/O device(s) that communicate with the computing system600. The ICH620may communicate with a bus622through a peripheral bridge (or controller)624, such as a peripheral component interconnect (PCI) bridge, a universal serial bus (USB) controller, or other types of peripheral bridges or controllers. The bridge624may provide a data path between the CPU602and peripheral devices. Other types of topologies may be utilized. Also, multiple buses may communicate with the ICH620, e.g., through multiple bridges or controllers. Moreover, other peripherals in communication with the ICH620may include, in various embodiments of the invention, integrated drive electronics (IDE) or small computer system interface (SCSI) hard drive(s), USB port(s), a keyboard, a mouse, parallel port(s), serial port(s), floppy disk drive(s), digital output support (e.g., digital video interface (DVI)), or other devices.

The bus622may communicate with an audio device626, one or more disk drive(s)628, and a network interface device630(which is in communication with the computer network603). Other devices may communicate via the bus622. Also, various components (such as the network interface device630) may communicate with the MCH608in some embodiments of the invention. In addition, the processor602and one or more other components discussed herein may be combined to form a single chip (e.g., to provide a System on Chip (SOC)). Furthermore, the graphics accelerator616may be included within the MCH608in other embodiments of the invention.

Furthermore, the computing system600may include volatile and/or nonvolatile memory (or storage). For example, nonvolatile memory may include one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), a disk drive (e.g.,628), a floppy disk, a compact disk ROM (CD-ROM), a digital versatile disk (DVD), flash memory, a magneto-optical disk, or other types of nonvolatile machine-readable media that are capable of storing electronic data (e.g., including instructions).

FIG. 7illustrates a block diagram of a computing system700, according to an embodiment of the invention. The system700may include one or more processors702-1through702-N (generally referred to herein as “processors702” or “processor702”). The processors702may communicate via an interconnection network or bus704. Each processor may include various components some of which are only discussed with reference to processor702-1for clarity. Accordingly, each of the remaining processors702-2through702-N may include the same or similar components discussed with reference to the processor702-1.

In an embodiment, the processor702-1may include one or more processor cores706-1through706-M (referred to herein as “cores706” or more generally as “core706”), a shared cache708, a router710, and/or a processor control logic or unit720. The processor cores706may be implemented on a single integrated circuit (IC) chip. Moreover, the chip may include one or more shared and/or private caches (such as cache708), buses or interconnections (such as a bus or interconnection network712), memory controllers, or other components.

In one embodiment, the router710may be used to communicate between various components of the processor702-1and/or system700. Moreover, the processor702-1may include more than one router710. Furthermore, the multitude of routers710may be in communication to enable data routing between various components inside or outside of the processor702-1.

The shared cache708may store data (e.g., including instructions) that are utilized by one or more components of the processor702-1, such as the cores706. For example, the shared cache708may locally cache data stored in a memory714for faster access by components of the processor702. In an embodiment, the cache708may include a mid-level cache (such as a level 2 (L2), a level 3 (L3), a level 4 (L4), or other levels of cache), a last level cache (LLC), and/or combinations thereof. Moreover, various components of the processor702-1may communicate with the shared cache708directly, through a bus (e.g., the bus712), and/or a memory controller or hub. As shown inFIG. 7, in some embodiments, one or more of the cores706may include a level 1 (L1) cache716-1(generally referred to herein as “L1 cache716”). In one embodiment, the control unit720may include logic to implement the operations described above with reference to the memory controller122inFIG. 2.

FIG. 8illustrates a block diagram of portions of a processor core706and other components of a computing system, according to an embodiment of the invention. In one embodiment, the arrows shown inFIG. 8illustrate the flow direction of instructions through the core706. One or more processor cores (such as the processor core706) may be implemented on a single integrated circuit chip (or die) such as discussed with reference toFIG. 7. Moreover, the chip may include one or more shared and/or private caches (e.g., cache708ofFIG. 7), interconnections (e.g., interconnections704and/or112ofFIG. 7), control units, memory controllers, or other components.

As illustrated inFIG. 8, the processor core706may include a fetch unit802to fetch instructions (including instructions with conditional branches) for execution by the core706. The instructions may be fetched from any storage devices such as the memory714. The core706may also include a decode unit804to decode the fetched instruction. For instance, the decode unit804may decode the fetched instruction into a plurality of uops (micro-operations).

Additionally, the core706may include a schedule unit806. The schedule unit806may perform various operations associated with storing decoded instructions (e.g., received from the decode unit804) until the instructions are ready for dispatch, e.g., until all source values of a decoded instruction become available. In one embodiment, the schedule unit806may schedule and/or issue (or dispatch) decoded instructions to an execution unit808for execution. The execution unit808may execute the dispatched instructions after they are decoded (e.g., by the decode unit804) and dispatched (e.g., by the schedule unit806). In an embodiment, the execution unit808may include more than one execution unit. The execution unit808may also perform various arithmetic operations such as addition, subtraction, multiplication, and/or division, and may include one or more an arithmetic logic units (ALUs). In an embodiment, a co-processor (not shown) may perform various arithmetic operations in conjunction with the execution unit808.

Further, the execution unit808may execute instructions out-of-order. Hence, the processor core706may be an out-of-order processor core in one embodiment. The core706may also include a retirement unit810. The retirement unit810may retire executed instructions after they are committed. In an embodiment, retirement of the executed instructions may result in processor state being committed from the execution of the instructions, physical registers used by the instructions being de-allocated, etc.

The core706may also include a bus unit714to enable communication between components of the processor core706and other components (such as the components discussed with reference toFIG. 8) via one or more buses (e.g., buses804and/or812). The core706may also include one or more registers816to store data accessed by various components of the core706(such as values related to power consumption state settings).

Furthermore, even thoughFIG. 7illustrates the control unit720to be coupled to the core706via interconnect812, in various embodiments the control unit720may be located elsewhere such as inside the core706, coupled to the core via bus704, etc.

In some embodiments, one or more of the components discussed herein can be embodied as a System On Chip (SOC) device.FIG. 9illustrates a block diagram of an SOC package in accordance with an embodiment. As illustrated inFIG. 9, SOC902includes one or more Central Processing Unit (CPU) cores920, one or more Graphics Processor Unit (GPU) cores930, an Input/Output (I/O) interface940, and a memory controller942. Various components of the SOC package902may be coupled to an interconnect or bus such as discussed herein with reference to the other figures. Also, the SOC package902may include more or less components, such as those discussed herein with reference to the other figures. Further, each component of the SOC package902may include one or more other components, e.g., as discussed with reference to the other figures herein. In one embodiment, SOC package902(and its components) is provided on one or more Integrated Circuit (IC) die, e.g., which are packaged into a single semiconductor device.

As illustrated inFIG. 9, SOC package902is coupled to a memory960(which may be similar to or the same as memory discussed herein with reference to the other figures) via the memory controller942. In an embodiment, the memory960(or a portion of it) can be integrated on the SOC package902.

The I/O interface940may be coupled to one or more I/O devices970, e.g., via an interconnect and/or bus such as discussed herein with reference to other figures. I/O device(s)970may include one or more of a keyboard, a mouse, a touchpad, a display, an image/video capture device (such as a camera or camcorder/video recorder), a touch screen, a speaker, or the like.

FIG. 10illustrates a computing system1000that is arranged in a point-to-point (PtP) configuration, according to an embodiment of the invention. In particular,FIG. 10shows a system where processors, memory, and input/output devices are interconnected by a number of point-to-point interfaces. The operations discussed with reference toFIG. 2may be performed by one or more components of the system1000.

As illustrated inFIG. 10, the system1000may include several processors, of which only two, processors1002and1004are shown for clarity. The processors1002and1004may each include a local memory controller hub (MCH)1006and1008to enable communication with memories1010and1012. MCH1006and1008may include the memory controller120and/or logic125ofFIG. 1in some embodiments.

In an embodiment, the processors1002and1004may be one of the processors702discussed with reference toFIG. 7. The processors1002and1004may exchange data via a point-to-point (PtP) interface1014using PtP interface circuits1016and1018, respectively. Also, the processors1002and1004may each exchange data with a chipset1020via individual PtP interfaces1022and1024using point-to-point interface circuits1026,1028,1030, and1032. The chipset1020may further exchange data with a high-performance graphics circuit1034via a high-performance graphics interface1036, e.g., using a PtP interface circuit1037.

As shown inFIG. 10, one or more of the cores106and/or cache108ofFIG. 1may be located within the processors1004. Other embodiments of the invention, however, may exist in other circuits, logic units, or devices within the system1000ofFIG. 10. Furthermore, other embodiments of the invention may be distributed throughout several circuits, logic units, or devices illustrated inFIG. 10.

The chipset1020may communicate with a bus1040using a PtP interface circuit1041. The bus1040may have one or more devices that communicate with it, such as a bus bridge1042and I/O devices1043. Via a bus1044, the bus bridge1043may communicate with other devices such as a keyboard/mouse1045, communication devices1046(such as modems, network interface devices, or other communication devices that may communicate with the computer network1003), audio I/O device, and/or a data storage device1048. The data storage device1048(which may be a hard disk drive or a NAND flash based solid state drive) may store code1049that may be executed by the processors1004.

The following examples pertain to further embodiments.

Example 1 is an apparatus electronic device, comprising a housing, a socket in the housing to receive a connector, and an illumination source proximate the socket to illuminate the socket.

In Example 2, the subject matter of Example 1 can optionally include an arrangement in which the socket comprises at least one of a power socket, a universal serial bus (USB) socket, an audio/visual (AV) socket, or an Ethernet socket.

In Example 3, the subject matter of any one of Examples 1-2 can optionally include an arrangement in which the illumination source comprises a light emitting diode.

In Example 4, the subject matter of any one of Examples 1-3 can optionally include an arrangement in which the light emitting diode is coupled to a light pipe panel surrounding the socket.

In Example 5, the subject matter of any one of Examples 1-4 can optionally include logic, at least partially including hardware logic, configured to receive at least one illumination configuration parameter, monitor sensor conditions in at least one sensor proximate the socket, and activate the illumination source in response to a determination that at least one of the illumination configuration parameters are satisfied.

In Example 6, the subject matter of any one of Examples 1-5 can optionally include an arrangement in which the at least one sensor comprises a photodetector and the logic is further configured to activate the illumination source only when an output from the photodetector indicates that the environment proximate the at least one socket is dark.

In Example 7, the subject matter of any one of Examples 1-6 can optionally include an arrangement in which the at least one sensor comprises a proximity detector and the logic is further configured to activate the illumination source only when an output from the proximity detector indicates that an object is proximate the at least one socket.

In Example 8, the subject matter of any one of Examples 1-7 can optionally include an arrangement in which the electronic device comprises a first near field communication (NFC) device and the logic is further configured to activate the illumination source only when the first NFC device detects a second NFC proximate the first electronic device.

In Example 9, the subject matter of any one of Examples 1-8 can optionally include an arrangement in which the logic is further configured to deactivate the illumination source after a predetermined period of time.

In Example 10, the subject matter of any one of Examples 1-9 can optionally include logic an arrangement in which the logic is further configured to deactivate the illumination source in response to detecting a connection with a remote device on the socket.

Example 11 is an apparatus comprising logic, at least partially including hardware logic, configured to receive at least one illumination configuration parameter, monitor sensor conditions in at least one sensor proximate the socket, and activate the illumination source in response to a determination that at least one of the illumination configuration parameters are satisfied.

In Example 12, the subject matter of Example 11 can optionally include an arrangement in which the at least one sensor comprises a photodetector and the logic is further configured to activate the illumination source only when an output from the photodetector indicates that the environment proximate the at least one socket is dark.

In Example 13, the subject matter of any one of Examples 11-12 can optionally include an arrangement in which the at least one sensor comprises a proximity detector and the logic is further configured to activate the illumination source only when an output from the proximity detector indicates that an object is proximate the at least one socket.

In Example 14, the subject matter of any one of Examples 11-13 can optionally include an arrangement in which the electronic device comprises a first near field communication (NFC) device and the logic is further configured to activate the illumination source only when the first NFC device detects a second NFC proximate the first electronic device.

In Example 15, the subject matter of any one of Examples 11-14 can optionally include an arrangement in which the logic is further configured to deactivate the illumination source after a predetermined period of time.

In Example 16, the subject matter of any one of Examples 11-15 can optionally include logic an arrangement in which the logic is further configured to deactivate the illumination source in response to detecting a connection with a remote device on the socket.

Example 17 is a computer program product comprising logic instructions stored in a non-transitory computer readable medium which, when executed by a processor, configure the processor to receive at least one illumination configuration parameter, monitor sensor conditions in at least one sensor proximate the socket, and activate the illumination source in response to a determination that at least one of the illumination configuration parameters are satisfied.

In Example 18, the subject matter of Example 17 can optionally include an arrangement in which the at least one sensor comprises a photodetector and the logic is further configured to activate the illumination source only when an output from the photodetector indicates that the environment proximate the at least one socket is dark.

In Example 19, the subject matter of any one of Examples 17-18 can optionally include an arrangement in which the at least one sensor comprises a proximity detector and the logic is further configured to activate the illumination source only when an output from the proximity detector indicates that an object is proximate the at least one socket.

In Example 20, the subject matter of any one of Examples 17-19 can optionally include an arrangement in which the electronic device comprises a first near field communication (NFC) device and the logic is further configured to activate the illumination source only when the first NFC device detects a second NFC proximate the first electronic device.

In Example 21, the subject matter of any one of Examples 17-20 can optionally include an arrangement in which the logic is further configured to deactivate the illumination source after a predetermined period of time.

In Example 22, the subject matter of any one of Examples 17-21 can optionally include logic an arrangement in which the logic is further configured to deactivate the illumination source in response to detecting a connection with a remote device on the socket.

Example 23 is an apparatus comprising means to receive at least one illumination configuration parameter, monitor sensor conditions in at least one sensor proximate the socket, and activate the illumination source in response to a determination that at least one of the illumination configuration parameters are satisfied.

In Example 24, the subject matter of Example 23 can optionally include an arrangement which further comprises means to activate the illumination source only when an output from the photodetector indicates that the environment proximate the at least one socket is dark.

In Example 25, the subject matter of any one of Examples 23-24 can optionally include an arrangement which further comprising means to activate the illumination source only when an output from the proximity detector indicates that an object is proximate the at least one socket

In Example 26, the subject matter of any one of Examples 23-25 can optionally include an arrangement in which the electronic device comprises a first near field communication (NFC) device and further comprising means to activate the illumination source only when the first NFC device detects a second NFC proximate the first electronic device.

In Example 27, the subject matter of any one of Examples 23-26 can optionally means to deactivate the illumination source after a predetermined period of time.

In Example 28, the subject matter of any one of Examples 23-27 can optionally means to deactivate the illumination source in response to detecting a connection with a remote device on the socket.

The terms “logic instructions” as referred to herein relates to expressions which may be understood by one or more machines for performing one or more logical operations. For example, logic instructions may comprise instructions which are interpretable by a processor compiler for executing one or more operations on one or more data objects. However, this is merely an example of machine-readable instructions and embodiments are not limited in this respect.

The terms “computer readable medium” as referred to herein relates to media capable of maintaining expressions which are perceivable by one or more machines. For example, a computer readable medium may comprise one or more storage devices for storing computer readable instructions or data. Such storage devices may comprise storage media such as, for example, optical, magnetic or semiconductor storage media. However, this is merely an example of a computer readable medium and embodiments are not limited in this respect.

The term “logic” as referred to herein relates to structure for performing one or more logical operations. For example, logic may comprise circuitry which provides one or more output signals based upon one or more input signals. Such circuitry may comprise a finite state machine which receives a digital input and provides a digital output, or circuitry which provides one or more analog output signals in response to one or more analog input signals. Such circuitry may be provided in an application specific integrated circuit (ASIC) or field programmable gate array (FPGA). Also, logic may comprise machine-readable instructions stored in a memory in combination with processing circuitry to execute such machine-readable instructions. However, these are merely examples of structures which may provide logic and embodiments are not limited in this respect.

Some of the methods described herein may be embodied as logic instructions on a computer-readable medium. When executed on a processor, the logic instructions cause a processor to be programmed as a special-purpose machine that implements the described methods. The processor, when configured by the logic instructions to execute the methods described herein, constitutes structure for performing the described methods. Alternatively, the methods described herein may be reduced to logic on, e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC) or the like.

In the description and claims, the terms coupled and connected, along with their derivatives, may be used. In particular embodiments, connected may be used to indicate that two or more elements are in direct physical or electrical contact with each other. Coupled may mean that two or more elements are in direct physical or electrical contact. However, coupled may also mean that two or more elements may not be in direct contact with each other, but yet may still cooperate or interact with each other.

Reference in the specification to “one embodiment” or “some embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment.