Operating method of memory device for extending synchronization of data clock signal, and operating method of electronic device including the same

Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.

CROSS-REFERENCE TO RELATED APPLICATIONS

This non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0030656 filed on Mar. 9, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference in its entirety herein.

Technical Field

Embodiments of the present disclosure described herein relate to an operating method of a memory device, and more particularly, relate to an operating method of a memory device for extending synchronization of a data clock signal, and an operating method of an electronic device including the memory device.

Discussion of Related Art

A memory device may include various circuits for generating, processing, or storing data. For example, the memory device may include various circuits for storing or outputting data based on electrical signals such as a command, an address, a clock signal, a data clock signal, and data. The data clock signal may be directly involved in storing or outputting data, and a frequency of the data clock signal may be higher than a frequency of a clock signal.

As the amount of data to be processed in the memory device increases, the frequency of the data clock signal may increase, thereby causing an increase in power consumption of the memory device. To reduce power consumption, the memory device may selectively enable synchronization of the data clock signal. When data processing has completed, the synchronization of the data clock signal is disabled, and the memory device again enables the synchronization of the data clock signal for the purpose of processing next data. However, since it takes time to again enable synchronization of the data clock signal, a next data processing is delayed.

SUMMARY

At least one embodiment of the present disclosure provides an operating method of a memory device for extending synchronization of a data clock signal, and an operating method of an electronic device including the memory device.

According to an embodiment, an operating method of a memory device which communicates with a memory controller includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock signal toggling at the reference frequency and extended for a period of the defined clock section.

According to an embodiment, an operating method of a memory device which communicates with a memory controller includes receiving a first command and a second command from the memory controller, the first command including mode register setting information and the second command indicating initiation of synchronization of a data clock signal, changing settings of a mode register based on the mode register setting information, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock signal toggling at the reference frequency and extended according to a reference cycle count of the changed settings.

According to an embodiment, an operating method of an electronic device which includes a memory device and a memory controller controlling the memory device includes providing, by the memory controller, a command for extending a synchronization of a data clock signal, preparing, by the memory device, a toggling of the data clock signal during a preparation time period, processing, by the memory device, a first data stream based on the data clock signal toggling at a reference frequency, and processing, by the memory device, a second data stream based on the data clock signal toggling at the reference frequency, and the synchronization of the data clock signal is extended based on the command.

According to an embodiment, an operating method of an electronic device which includes a memory device and a memory controller controlling the memory device includes determining, by the memory controller, whether a processing interval between a first processing command and a second processing command is shorter than a reference interval, when it is determined that the processing interval is shorter than the reference interval, generating, by the memory controller, an extension command for extending a synchronization of a data clock signal, preparing, by the memory device, a toggling of the data clock signal during a preparation time period based on the extension command, processing, by the memory device, a first data stream corresponding to the first processing command based on the data clock signal toggling at a reference frequency, and processing, by the memory device, a second data stream corresponding to the second processing command based on the data clock signal toggling at the reference frequency, and the synchronization of the data clock signal is extended based on the extension command.

DETAILED DESCRIPTION

Below, embodiments of the present disclosure will be described in detail and clearly to such an extent that one skilled in the art may implement the present disclosure. Below, for convenience of description, like components are expressed by using the same or like reference numerals.

FIG.1is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Referring toFIG.1, an electronic device10includes a memory controller100(e.g., a control circuit) and a memory device200. The electronic device10may be a device that stores data or outputs the stored data. For example, the electronic device10may be used to store data in the following devices: a computer, a tablet, a laptop, a notebook computer, a personal digital assistant (PDA), a mobile computing device, a smartphone, and an Internet home appliance.

The memory controller100may communicate with the memory device200. The memory controller100may control the memory device200. The memory controller100may store data in the memory device200or may read data stored in the memory device200. The memory controller100may include a command generator110(e.g., a circuit). The command generator110may generate a command CMD.

The memory controller100may generate the command CMD, an address ADD, a clock signal CK, and a data clock signal WCK. The memory controller100may output the command CMD, the address ADD, the clock signal CK, and the data clock signal WCK to the memory device200. The memory controller100may output data to the memory device200or may receive the data from the memory device200.

The memory device200may receive the command CMD, the address ADD, the clock signal CK, and the data clock signal WCK from the memory controller100. The memory device200may output the data to the memory controller100or may receive the data from the memory controller100. That is, the memory device200may be a device that stores data. For example, the memory device200may be volatile memory such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), or a static random access memory (SRAM), but the present disclosure is not limited thereto.

The memory device200may include a synchronization circuit220. The synchronization circuit220may control synchronization of the data clock signal WCK. The synchronization of the data clock signal WCK may mean that the data clock signal WCK toggles at a timing synchronized with the clock signal CK for the purpose of reading or writing data. The toggling may mean that a logical state transitions from low (L) to high (H) or transitions from H to L.

The command CMD may be a signal indicating an operation to be performed by the memory device200. For example, the command CMD may include read, write, refresh, precharge, mode register, column address strobe CAS, deselect DES, etc., but the present disclosure is not limited thereto. For example, the command CMD may vary depending on the specification that is applied to the memory device200.

In an embodiment, the CAS that is a command accompanied before the read command or the write command may be a command for initiating the synchronization of the data clock signal WCK in the LPDDR5 (Low Power Double Data Rate 5). In an embodiment, the DES may be a command indicating that the memory device200is to perform no operation.

In an embodiment, the memory controller100may be connected with the memory device200through a command/address bus (i.e., a CA bus) including a plurality of command pins. The memory controller100may output command/address signals (hereinafter referred to as “CAs”) to the plurality of command pins of the CA bus, and a combination of the CAs may correspond to the command CMD or the address ADD. The memory device200may determine the command CMD based on the CAs received through the plurality of command pins and a command truth table.

In an embodiment, the command generator110generates a command defined by a user. In an embodiment, the command generator110generates a command for changing settings (e.g., mode register settings) of the memory device200. This will be described in more detail with reference toFIG.2.

The address ADD may be a signal indicating a location of a memory rank, a memory bank, a memory cell, etc. of the memory device200, at which an operation is to be performed. For example, the address ADD may include a row address and a column address of a memory cell of a memory bank in a selected memory rank.

The clock signal CK may be a signal that toggles periodically. For example, the clock signal CK may be an electrical signal having a logical high level and a logical low level that are periodically repeated. The clock signal CK may be used to determine a timing being a reference of communication with the memory device200or an internal operation of the memory device200. In an embodiment, the clock signal CK includes complementary clock signals CK_t and CK_c.

The data clock signal WCK may be a signal that is used in reading or writing data. A frequency of the data clock signal WCK may be higher than a frequency of the clock signal CK. For example, the data clock signal WCK may be a signal that toggles at a high frequency for data processing. In an embodiment, the data clock signal WCK includes complementary clock signals WCK_t and WCK_c.

In an embodiment, to reduce power consumption of the memory device200, the synchronization circuit220temporarily performs synchronization of the data clock signal WCK only when a request is received from the memory controller100. After a given time period passes, the synchronization of the data clock signal WCK may be disabled. In the case where there is a need to process next data, the synchronization circuit220may again perform synchronization of the data clock signal WCK depending on the request of the memory controller100. This will be described in more detail with reference toFIG.3.

In an embodiment, the memory controller100and the memory device200exchange data with each other. For example, when the command CMD is the write command, the memory controller100may output data to the memory device200. For example, when the command CMD is the read command, the memory controller100may receive data from the memory device200. The data may be at least a portion of a computer program or application, or may be at least a portion of user data such as an image, a video, a voice, or a text.

In an embodiment, the communication between the memory controller100and the memory device200may comply with the specification defined in the LPDDR5.

FIG.2is a block diagram illustrating a memory controller ofFIG.1, according to an embodiment of the present disclosure. Referring toFIGS.1and2, the memory controller100may communicate with a host and the memory device200. For example, the memory controller100may output the command CMD, the address ADD, the clock signal CK, and the data clock signal WCK to the memory device200and may communicate with the memory device200.

The memory controller100may include the command generator110, a mode register setting module111(e.g., a circuit), an address generator112(e.g., a circuit), a CMD/ADD transmitter113, a clock generator120(e.g., a signal generator), a CK transmitter121, a WCK transmitter122, a write data queue130, a write data transmitter131, a read data receiver132, a read data queue133, a host interface140(e.g., an interface circuit), and a bus150.

The command generator110may generate the command CMD. The command generator110may output the command CMD to the CMD/ADD transmitter113.

In an embodiments, the command generator110generates a column address strobe lengthened CASL, which is defined by the user, based on communication with the host and outputs the command CMD including the CASL. The CASL may be a command that is similar to the CAS in terms of initiating the synchronization of the data clock signal WCK but is defined independently of the CAS to extend the synchronization of the data clock signal WCK. The CASL will be described in more detail with reference toFIGS.5and6together.

In an embodiment, the command generator110receives mode register setting information MRS from the mode register setting module111. The command generator110may output a command CMD including the mode register setting information MRS. The mode register setting information MRS may be information for changing mode register settings of the memory device200. The mode register setting information MRS will be described in more detail with reference toFIGS.7and8together.

The mode register setting module111may generate the mode register setting information MRS defined by the user, based on communication with the host. The mode register setting module111may output the mode register setting information MRS to the command generator110.

The address generator112may generate the address ADD. The address generator112may output the address ADD to the CMD/ADD transmitter113. The CMD/ADD transmitter113may receive the command CMD from the command generator110. The CMD/ADD transmitter113may receive the address ADD from the address generator112. The CMD/ADD transmitter113may output the command CMD and the address ADD to the memory device200.

The clock generator120may generate the clock signal CK and the data clock signal WCK. The clock generator120may output the clock signal CK to the CK transmitter121. The clock generator120may output the data clock signal WCK to the WCK transmitter122. The CK transmitter121may output the clock signal CK to the memory device200. The WCK transmitter122may output the data clock signal WCK to the memory device200.

The write data queue130may store data to be written in the memory device200. For example, data stored in the write data queue130may be data provided from the host. The write data queue130may output the data to the write data transmitter131. The write data transmitter131may output the data to the memory device200. For example, the write data transmitter131may output, to the memory device200, a data signal DQ and a data mask inversion signal DMI for a write operation. The data signal DQ may be a signal indicating actual information of data. The data mask inversion signal DMI may be a signal for data mask and data bus inversion.

The read data receiver132may receive data from the memory device200. For example, the read data receiver132may receive the data signal DQ and the data mask inversion signal DMI for a read operation from the memory device200. The read data receiver132may output the data to the read data queue133. The read data queue133may store the data read from the memory device200. The read data queue133may provide the host with the data corresponding to a request (e.g., a read request) of the host.

The host interface140may communicate with the host. The host interface140may receive the mode register setting information MRS and the CASL from the host and may output the mode register setting information MRS and the CASL to the command generator110. The host interface140may receive data for the write operation from the host and may output the data to the write data queue130. The host interface140may receive data associated with the read operation from the read data queue133and may output the data to the host.

The bus150may electrically connect the command generator110, the mode register setting module111, the address generator112, the CMD/ADD transmitter113, the clock generator120, the CK transmitter121, the WCK transmitter122, the write data queue130, the write data transmitter131, the read data receiver132, the read data queue133, and the host interface140.

FIG.3is a block diagram illustrating a memory device ofFIG.1, according to an embodiment of the present disclosure. Referring toFIGS.1and3, the memory device200may communicate with the memory controller100. For example, the memory device200may receive the command CMD, the address ADD, the clock signal CK, and the data clock signal WCK from the memory controller100and may communicate with the memory controller100.

The memory device200includes a CMD/ADD receiver210, a CMD/ADD circuit211, a mode register212, a row decoder213(e.g., a decoder circuit), a column decoder214(e.g., a decoder circuit), the synchronization circuit220, a CK receiver221, a WCK receiver222, an internal clock circuit223, an input/output (I/O) control circuit230, a write data receiver231, a read data transmitter232, and a plurality of memory ranks240.

The CMD/ADD receiver210may receive the command CMD and the address ADD from the memory controller100through the CA bus. The CMD/ADD receiver210may receive the clock signal CK from the CK receiver221. The CMD/ADD receiver210may output the command CMD and the address ADD to the CMD/ADD circuit211.

The CMD/ADD circuit211may include a CMD decoder (e.g., a decoder circuit) and an ADD demultiplexer. The CMD decoder may decode the command CMD. The ADD demultiplexer may demultiplex the address ADD. The CMD/ADD circuit211may control the mode register212based on a decoding result of the CMD decoder.

In an embodiment, when the command CMD is determined as the CAS by the CMD decoder, the CMD/ADD circuit211controls the mode register212or the synchronization circuit220to initiate synchronization. In an embodiment, when the decoding result of the CMD decoder indicates that the command CMD includes the mode register setting information MRS, the CMD/ADD circuit211changes settings of the mode register212.

The CMD/ADD circuit211may control the row decoder213and the column decoder214based on a demultiplexing result of the ADD demultiplexer. For example, the ADD demultiplexer may demultiplex the address ADD to obtain a row address and a column address. The CMD/ADD circuit211may output the row address to the row decoder213. The CMD/ADD circuit211may output the column address to the column decoder214.

The mode register212may be connected with the CMD/ADD circuit211. In an embodiment, settings of the mode register212may be changed based on the mode register setting information MRS decoded by the CMD/ADD circuit211. In an embodiment, the mode register212outputs a synchronization initiation signal SYI to the synchronization circuit220under control of the CMD/ADD circuit211. The synchronization initiation signal SYI may be a signal that triggers the synchronization of the data clock signal WCK.

The row decoder213may be connected to the plurality of memory ranks240. The column decoder214may be connected to the plurality of memory ranks240. A location of a memory cell in the plurality of memory ranks240may be specified by the row decoder213and the column decoder214. For example, the row decoder213may specify a row of a memory rank based on the row address and the column decoder214may specify a column of the memory rank based on the column address.

The CK receiver221may receive the clock signal CK from the memory controller100. The CK receiver221may output the clock signal CK to the CMD/ADD receiver210and the synchronization circuit220. The clock signal CK may provide a timing being a reference in overall operations of the memory device200.

The WCK receiver222may receive the data clock signal WCK from the memory controller100. The WCK receiver222may output the data clock signal WCK to the synchronization circuit220.

The synchronization circuit220may receive the synchronization initiation signal SYI from the mode register212. The synchronization circuit220may receive the clock signal CK from the CK receiver221. The synchronization circuit220may receive the data clock signal WCK from the WCK receiver222. The synchronization circuit220may perform synchronization of the data clock signal WCK based on the clock signal CK, in response to the synchronization initiation signal SYI. The synchronization circuit220may output a synchronized data clock signal SWCK to the internal clock circuit223.

The synchronization of the data clock signal WCK may mean matching a timing with the clock signal CK and allowing the data clock signal WCK to toggle at a reference frequency, such that data are processed within the memory device200. The reference frequency may be a frequency of the data clock signal WCK in a normal state, which is determined to read or write data in units of a bit. The reference frequency may be higher than a frequency of the clock signal CK. The synchronization of the data clock signal WCK will be described in more detail with reference toFIGS.4A to4Ctogether.

The internal clock circuit223may receive the synchronized data clock signal SWCK from the synchronization circuit220. The internal clock circuit223may output an internal clock signal to the I/O control circuit230based on the synchronized data clock signal SWCK. The internal clock signal may be used for the read operation and the write operation in the I/O control circuit230. In an embodiment, the internal clock circuit223includes a four-phase converter. The four-phase converter will be described in more detail with reference toFIGS.12A and12Btogether.

The I/O control circuit230may be connected with the write data receiver231, the read data transmitter232, the internal clock circuit223, and the plurality of memory ranks240. The I/O control circuit230may be a circuit that controls the read operation and the write operation with the plurality of memory ranks240. For example, the I/O control circuit230may receive data from the write data receiver231. The I/O control circuit230may output data to the memory rank240through a write driver. For example, the I/O control circuit230may receive data from the memory rank240through a sense amplifier. The I/O control circuit230may output the data to the read data transmitter232.

Each of the plurality of memory ranks240may be connected with the row decoder213, the corresponding column decoder214, and the corresponding write driver, and the corresponding sense amplifier. Each of the plurality of memory ranks240may include a plurality of memory banks. Each of the plurality of memory banks may include a plurality of memory cells. Each of the plurality of memory cells may have a row address and a column address and may store data in the form of logical high or logical low. How data are processed in the plurality of memory ranks240will be described in more detail with reference toFIGS.10,11A, and11Btogether.

FIGS.4A to4Care timing diagrams illustrating synchronization of a data clock signal ofFIG.3, according to an embodiment of the present disclosure. For better understanding of the present invention, a case where the synchronization of a data clock signal is not extended will be described with reference toFIGS.4A to4C, and a case where the synchronization of the data clock signal is extended will be described with reference toFIGS.5to16.

FIG.4Adescribes a method for processing a data stream depending on the CAS and the write command. Referring toFIG.4A, waveforms of CK_t, CK_c, CS, CA, CMD, WCK_t, WCK_c, DQ, and DMI are illustrated by way of example. InFIG.4A, a horizontal axis represents a time. CK_t and CK_c may correspond to the clock CK ofFIG.3. A command/address signal CA may correspond to the command CMD and the address ADD ofFIG.3. A chip select signal CS may be a signal for activating the CA. The CMD may be determined based on a command truth table of the CA. WCK_t and WCK_c may correspond to the data clock signal WCK ofFIG.3. DQ and DMI may correspond to data ofFIG.3(e.g., DQ and DMI for a write operation). To provide a better understanding of the present disclosure, the timing diagram ofFIG.4Awill be described with reference toFIGS.3and4A.

At time tp1, the memory device200detects toggling of the clock signal CK. For example, the memory device200may detect a transition of CK_t from logical low to logical high and/or a transition of CK_c from logical high to logical low. The memory device200may determine the CA in response to the toggling of the clock signal CK. The command CMD corresponding to the determined CA may be the CAS. At time tp1, WCK_t, WCK_c, DQ, and DMI may be in a don't care state.

The memory device200initiates the synchronization of the data clock signal WCK in response to the command CMD being determined as the CAS. For example, time tp1may be a start point of a time period tWCK_SYNC indicating a period associated with the synchronization of the data clock signal WCK. For example, time tp1may be a start point of a preparation time period tSYNC_Prepare indicating a period of preparing the synchronization of the data clock signal WCK.

In an embodiment, immediately after receiving the CAS, the memory device200may receive the command CMD corresponding to a write. For example, the memory device200may sequentially receive the CAS and the command CMD corresponding to the write. In an embodiment, a time period from when a command corresponding to the write is applied to when the data DQ and DMI are processed may be determined in advance depending on the specification applied to the memory device200.

At time tp2, the memory device200determines that a time period tENL passes from time tp1when the CAS is determined. The time period tENL may indicate a period where the data clock signal WCK is in the don't care state. The memory device200may maintain the data clock signal WCK in a given logical state from time tp2. For example, the memory device200may maintain WCK_t at logical low and may maintain WCK_c at logical high.

At time tp3, the memory device200determines that a time period tPRE_Static passes from time tp2when the data clock signal WCK is maintained in the given logical state. The time period tPRE_Static may indicate a period where the data clock signal WCK is maintained in the given logical state. The memory device200may perform pre-toggling of the data clock signal WCK after time tp3. The pre-toggling may mean that the data clock signal WCK toggles at a frequency lower than the reference frequency. For example, the memory device200may allow the data clock signal WCK to toggle at a frequency, which is lower than the reference frequency as much as two times, during a time period tPRE_Toggle from time tp3. However, the present disclosure is not limited thereto. For example, according to an embodiment, the memory device200allows the data clock signal WCK to toggle at the reference frequency in the time period tPRE_Toggle.

At time tp4, the memory device200determines that the time period tPRE_Toggle passes from time tp3when the data clock signal WCK pre-toggles at a frequency lower than the reference frequency. The time period tPRE_Toggle may indicate a period where the data clock signal WCK pre-toggles at the frequency lower than the reference frequency. In an embodiment, the memory device200allows the data clock signal WCK to toggle at the reference frequency after time tp4. The reference frequency that is a frequency used to read or write data in units of a bit may be a frequency of the data clock signal WCK in a normal state. For example, the reference frequency may correspond to a frequency of the DQ.

At time tpd1, the memory device200may initiate processing of a data stream. The data stream may indicate a set of DQs corresponding to valid data. For example, the memory device200may store the DQ based on the data clock signal WCK from time tpd1.

In an embodiment, the memory device200processes a data stream from time tpd1when a time period tDQI passes from time tp4. The time period tDQI may be a margin that is set to cope with an abnormal operation (e.g., the situation where a frequency of the data clock signal WCK does not yet converge to the reference frequency). In an embodiment, the time period tDQI is omitted or may be decreased or increased.

At time tpd2, the memory device200completes the processing of the data stream. The data clock signal WCK that toggles after time tpd2may be irrelevant to the processing of the data stream. In the case where processing of another data stream is not required, the toggling of the data clock signal WCK after time tpd2may cause unnecessary power consumption.

At time tp5, the memory device200may disable the synchronization of the data clock signal WCK. To disable the synchronization may mean that the data clock signal WCK does not toggle or that the data clock signal WCK is in the don't care state without solving a skew with the clock signal CK. After time tp5, since the synchronization of the data clock signal WCK is disabled, power consumption of the memory device200may be reduced. In the case of a mobile device in which a power supply is limited, disabling the synchronization of the data clock signal WCK when data processing is not required may be useful for power management.

In an embodiments, time tp5when the synchronization of the data clock signal WCK is disabled may be determined as a time when a time period tWCK_Toggle passes from time tp4when the data clock signal WCK toggles. The time period tWCK_Toggle may comply with settings in the mode register212of the memory device200. Time tp5may be an end point of the time period tWCK_SYNC.

As described above, the synchronization of the data clock signal WCK corresponding to the CAS and the write command is described with reference toFIG.4A. The time period tWCK_SYNC associated with the synchronization of the data clock signal WCK may be a time period from tp1to tp5. The time period tWCK_SYNC may include the preparation time period tSYNC_Prepare and the time period tWCK_Toggle. The preparation time period tSYNC_Prepare may include the time period tENL, the time period tPRE_Static, and the time period tPRE_Toggle. The time period tWCK_Toggle may indicate a period where the data clock signal WCK toggles at the reference frequency. After the time period tDQI passes from time tp4being a start point of the time period tWCK_Toggle, a data stream may be processed.

FIG.4Bdescribes a method for processing a data stream depending the CAS and the read command. Referring toFIG.4B, waveforms of CK_t, CK_c, CS, CA, CMD, WCK_t, WCK_c, DQ, and DMI are illustrated by way of example. InFIG.4B, a horizontal axis represents a time. In each waveform, the meaning and a correspondence relationship of the memory device200are similar to those described with reference toFIG.4A, and thus, additional description will be omitted to avoid redundancy. The timing diagram ofFIG.4Bwill be described with reference toFIGS.3and4B.

Even in the case of processing the read command as well as the write command, the memory device200may process data based on the synchronization of the data clock signal WCK. For example, the memory device200may prepare the toggling of the data clock signal WCK during the preparation time period tSYNC_Prepare and may then process a data stream within the time period tWCK_Toggle.

In more detail, based on the CAS and the read command sequentially received, the memory device200may maintain the data clock signal WCK in the don't care state during the time period tENL, may maintain the data clock signal WCK in the given logical state during the time period tPRE_Static, and may perform pre-toggling of the data clock signal WCK at a frequency lower than the reference frequency during the time period tPRE_Toggle. After the time period tDQI for margin passes from time tp4being a start point of the time period tWCK_Toggle, the memory device200may output the data stream depending on the read command.

As described above, the method for processing the data stream in the write operation is described with reference toFIG.4A, and the method for processing the data stream in the read operation is described with reference toFIG.4B. After the data stream is processed, the synchronization of the data clock signal WCK may be disabled, and thus, power consumption of the memory device200may be reduced. However, after the synchronization of the data clock WCK signal is disabled, when another read command or a write command is received, the memory device200may again perform the synchronization of the data clock signal WCK. This will be more fully described with reference toFIG.4Ctogether.

FIG.4Cdescribes a method for processing a plurality of data streams. Referring toFIG.4C, waveforms of CK_t, CK_c, CMD, WCK_t, WCK_c, DQ, and DMI are illustrated by way of example. InFIG.4C, a horizontal axis represents a time. In each waveform, the meaning and a correspondence relationship of the memory device200are similar to those described with reference toFIG.4A, and thus, additional description will be omitted to avoid redundancy. The timing diagram ofFIG.4Cwill be described with reference toFIGS.3and4C.

The memory device200may process a plurality of data streams. For example, the memory device200may process a first data stream during a time period 1st tWCK_SYNC. Afterwards, the memory device200may process a second data stream during a time period 2nd tWCK_SYNC.

The time period 1st tWCK_SYNC may be a time period from tp1to tp5. Time tp1may be a time at which the CAS corresponding to a first write command is determined. Time tp5may be a time at which the toggling of the data clock signal WCK for a first write operation ends. The time period 1st tWCK_SYNC may include a time period 1st tValid_Data. The time period 1st tValid_Data may be a time period from time tp1when a command associated with the first data stream is determined to time tpd2when processing of the first data stream is completed.

The time period 1st tWCK_SYNC may include a preparation time period 1st tSYNC_Prepare and a time period 1st tWCK_Toggle. The preparation time period 1st tSYNC_Prepare may be a time period from time tp1when the command associated with the first data stream is determined to time tp4when the data clock signal WCK toggles at the reference frequency. The preparation time period 1st tSYNC_Prepare may include a time period in which the data clock signal WCK is in the don't care state, a time period in which the data clock signal WCK is maintained in the given logical state, and a time period in which the data clock signal WCK pre-toggles at a frequency lower than the reference frequency.

The time period 1st tWCK_Toggle may be a time period from time tp4when the data clock signal WCK toggles at the reference frequency to time tp5when the synchronization of the data clock signal WCK is disabled. In the time period 1st tWCK_Toggle, the memory device200may start to process the first data stream from time tpd1when the time period tDQI passes from time tp4. At time tpd2, the memory device200may complete the processing of the first data stream.

The time period 2nd tWCK_SYNC may be a time period from tp6to tp10. Time tp6may be a time at which the CAS corresponding to a second write command is determined. Time tp10may be a time at which the toggling of the data clock signal WCK for a second write operation ends. The time period 2nd tWCK_SYNC may include a time period 2nd tValid_Data. The time period 2nd tValid_Data may be a time period from time tp6when a command associated with the second data stream is determined to time tpd4when processing of the second data stream is completed.

The time period 2nd tWCK_SYNC may include a preparation time period 2nd tSYNC_Prepare and a time period 2nd tWCK_Toggle. The preparation time period 2nd tSYNC_Prepare may be a time period from time tp6when the command associated with the second data stream is determined to time tp9when the data clock signal WCK toggles at the reference frequency. The preparation time period 2nd tSYNC_Prepare may include a time period in which the data clock signal WCK is in the don't care state, a time period in which the data clock signal WCK is maintained in the given logical state, and a time period in which the data clock signal WCK pre-toggles at a frequency lower than the reference frequency.

The time period 2nd tWCK_Toggle may be a time period from time tp9when the data clock signal WCK toggles at the reference frequency to time tp10when the synchronization of the data clock signal WCK is disabled. In the time period 2nd tWCK_Toggle, the memory device200may start to process the second data stream from time tpd3when the time period tDQI passes from time tp9. At time tpd4, the memory device200may complete the processing of the second data stream.

As described above, in the memory device200, the synchronization of the data clock signal WCK may be disabled to reduce power consumption after data processing is completed. However, in the case where a new write command or a new read command is received later, the memory device200again performs the synchronization of the data clock signal WCK, thereby causing a delay of data processing. Accordingly, there is required a method for extending the synchronization of the data clock signal WCK in the memory device200. This will be more fully described with reference toFIGS.5to9together.

FIG.5is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Referring toFIG.5, an electronic device20includes a memory controller100aand a memory device200a. The memory controller100aincludes the command generator110, the address generator112, the CMD/ADD transmitter113, the CK transmitter121, the WCK transmitter122, the write data transmitter131, and the read data receiver132. The memory device200aincludes the CMD/ADD receiver210, the CMD/ADD circuit211, the mode register212, the synchronization circuit220, the CK receiver221, the WCK receiver222, the I/O control circuit230, the write data receiver231, the read data transmitter232, and the memory rank240. Lower level components of the electronic device20are similar to those described with reference toFIGS.1to3, and thus, additional description will be omitted to avoid redundancy.

According to an embodiment of the present disclosure, the electronic device20extends the synchronization of the data clock signal WCK based on the CASL defined by the user. The CASL may be a command defined by the user. The CASL may define a clock section that indicates initiation of the synchronization of the data clock signal WCK and corresponds to the synchronization. In an embodiment, the clock section defined in the CASL is longer than a clock section defined in the CAS of the LPDDR5.

According to an embodiment of the present disclosure, the command generator110may include the CASL being the defined command. The CASL may be provided from the host. To extend the synchronization, the command generator110may output the CASL to the CMD/ADD transmitter113. The CMD/ADD transmitter113may output the CASL to the CMD/ADD receiver210in the form of the command CMD. The CMD/ADD receiver210may output the command CMD including the CAS L to the CMD/ADD circuit211. The CMD/ADD circuit211may decode the command CMD to obtain the CASL. The CMD/ADD circuit211may output the CASL to the mode register212.

The mode register212may receive the CASL from the CMD/ADD circuit211. The mode register212may determine the clock section for the synchronization, based on the CASL. In this case, the determined clock section may be longer than the clock section corresponding to the CAS. The mode register212may output a synchronization initiation signal SYIa to the synchronization circuit220. For example, the mode register212may output the synchronization initiation signal SYIa in response to receiving the CASL. The synchronization initiation signal SYIa may include information about the clock section according to the CASL.

The synchronization circuit220may receive the synchronization initiation signal SYIa from the mode register212. The synchronization circuit220may perform the synchronization of the data clock signal WCK during an extended clock section, based on the synchronization initiation signal SYIa.

FIG.6is a timing diagram illustrating a data clock signal in which the synchronization inFIG.5is extended, according to an embodiment of the present disclosure. A timing diagram indicating synchronization in the case of using the CAS and a timing diagram indicating synchronization in the case of using the CASL are illustrated inFIG.6. For example, the case of using the CAS may correspond to the memory device200ofFIG.1, and the case of using the CASL may correspond to the memory device200aofFIG.5. InFIG.6, a horizontal axis represents a time. In each waveform, the meaning and a correspondence relationship of the memory device are similar to those described with reference toFIG.4A, and thus, additional description will be omitted to avoid redundancy.

Referring toFIG.6associated with the case of using the CAS andFIG.1, in response to that the command CMD is determined as the CAS, the memory device200may prepare the toggling of the data clock signal WCK during the preparation time period tSYNC_Prepare and may allow the data clock signal WCK to toggle during the time period tWCK_Toggle. In this case, the time period tWCK_Toggle may correspond to a clock section.

Referring toFIG.6associated with the case of using the CASL andFIG.5, in response to the command CMD being determined as the CASL, the memory device200aprepares the toggling of the data clock signal WCK during the preparation time period tSYNC_Prepare and allows the data clock signal WCK to toggle during the time period tWCK_Toggle. In this case, the time period tWCK_Toggle corresponds to the clock section defined in the CASL.

That is, in the case of using the CAS, the clock section corresponding to the time period tWCK_Toggle may be from tp4to tp5. In the case of using the CASL, the clock section corresponding to the time period tWCK_Toggle may be from tp4to tpa. As the clock section corresponding to the time period tWCK_Toggle is extended based on the defined CASL, the time period tWCK_Toggle may be extended as much as a time period from tp5to tpa.

FIG.7is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Referring toFIG.7, an electronic device30includes a memory controller100band a memory device200b. The memory controller100bincludes the command generator110, the mode register setting module111, the address generator112, the CMD/ADD transmitter113, the CK transmitter121, the WCK transmitter122, the write data transmitter131, and the read data receiver132. The memory device200bincludes the CMD/ADD receiver210, the CMD/ADD circuit211, the mode register212, the synchronization circuit220, the CK receiver221, the WCK receiver222, the I/O control circuit230, the write data receiver231, the read data transmitter232, and the memory rank240. Lower level components of the electronic device30are similar to those described with reference toFIGS.1to3, and thus, additional description will be omitted to avoid redundancy.

According to an embodiment of the present disclosure, the electronic device30may extend the synchronization of the data clock signal WCK by changing settings of the mode register212, based on a command including the mode register setting information MRS. The mode register setting information MRS may be set by the user. In an embodiment, the mode register setting information MRS include a reference cycle count (or number) of the data clock signal WCK. The reference cycle count (or number) may indicate the number of times that the data clock signal WCK toggles in the synchronization of the data clock signal WCK. For example, the reference cycle count (or number) that is the number of times defined by the user may be greater than the number of times that the data clock signal WCK toggles, which is defined in the mode register212.

According to an embodiment of the present disclosure, the mode register setting module111may determine the mode register setting information MRS. Alternatively, the mode register setting information MRS may be received from the host. The mode register setting module111may output the mode register setting information MRS to the command generator110. The command generator110may output the mode register setting information MRS to the CMD/ADD transmitter113. The CMD/ADD transmitter113may output the command CMD including the mode register setting information MRS to the CMD/ADD receiver210. The CMD/ADD receiver210may output the command CMD including the mode register setting information MRS to the CMD/ADD circuit211. The CMD/ADD circuit211may decode the command CMD to obtain the mode register setting information MRS. The CMD/ADD circuit211may output the mode register setting information MRS to the mode register212.

Settings of the mode register212may be changed based on the mode register setting information MRS. For example, based on the mode register setting information MRS, the mode register212may determine the number of times that the data clock signal WCK toggles in the time period tWCK_Toggle, as the reference cycle count (or number). In an embodiment, the reference cycle count (or number) is greater than the number of times that the data clock signal WCK toggles in the time period tWCK_Toggle. The mode register212may output a synchronization initiation signal SYIb to the synchronization circuit220. For example, the mode register212may output a synchronization initiation signal SYIb in response to receiving the mode register setting information MRS.

The synchronization circuit220may receive the synchronization initiation signal SYIb from the mode register212. The synchronization circuit220may extend the synchronization of the data clock signal WCK, based on the synchronization initiation signal SYIb.

FIG.8is a timing diagram illustrating a data clock signal in which the synchronization inFIG.7is extended, according to an embodiment of the present disclosure. A timing diagram indicating synchronization performed depending on conventional mode register setting and a timing diagram indicating synchronization performed depending on changed mode register setting are illustrated inFIG.8. For example, the case of the conventional mode register setting may correspond to the memory device200ofFIG.1, and the case of the changed mode register setting may correspond to the memory device200bofFIG.7. InFIG.8, a horizontal axis represents a time. In each waveform, the meaning and a correspondence relationship of the memory device are similar to those described with reference toFIG.4A, and thus, additional description will be omitted to avoid redundancy.

Referring toFIG.8associated with the conventional mode register setting andFIG.1, in response to that the command CMD is determined as the CAS, the memory device200may prepare the toggling of the data clock signal WCK during the preparation time period tSYNC_Prepare and may allow the data clock signal WCK to toggle during the time period tWCK_Toggle. The number of times that the data clock signal WCK toggles in the time period tWCK_Toggle may comply with a setting in the mode register212. For example, during the time period tWCK_Toggle, the data clock signal WCK may toggle by as much as a default cycle count (or number).

Referring toFIG.8associated with the changed mode register setting andFIG.7, the memory device200bmay receive the mode register setting information MRS before time tp1. The mode register212of the memory device200bmay change settings based on the mode register setting information MRS. For example, with regard to the synchronization of the data clock signal WCK, the mode register212may determine the number of times that the data clock signal WCK toggles in the time period tWCK_Toggle, as the reference cycle count (or number) instead of the default cycle count (or number). At time tp1, in response to the command CMD being determined as the CASL, the memory device200bmay prepare the toggling of the data clock signal WCK during the preparation time period tSYNC_Prepare and may allow the data clock signal WCK to toggle during the time period tWCK_Toggle. In this case, the number of times that the data clock signal WCK toggles in the time period tWCK_Toggle may comply with the changed setting in the mode register212. For example, during the time period tWCK_Toggle, the data clock signal WCK may toggle by as much as the reference cycle count (or number). In an embodiment, the reference cycle count (or number) is greater than the default cycle count (or number).

That is, a frequency of the data clock signal WCK may be uniform during the time period tWCK_Toggle, and the time period tWCK_Toggle that is based on the data clock signal WCK toggling by as much as the default cycle number may be from tp4to tp5. The time period tWCK_Toggle that is based on the data clock signal WCK toggling by as much as the reference cycle number may be from tp4to tpb. As the number of times that the data clock signal WCK toggles increases during the time period tWCK_Toggle, the time period tWCK_Toggle may be extended by as much as a time period from tp5to tpb.

FIG.9is a timing diagram illustrating data streams that are processed based on a data clock signal in which synchronization is extended, according to an embodiment of the present disclosure. A method for processing a plurality of data streams based on the extended data clock signal WCK will be described with reference toFIG.9. In each waveform, the meaning and a correspondence relationship of the memory device are similar to those described with reference toFIG.4A, and thus, additional description will be omitted to avoid redundancy. The timing diagram ofFIG.9may correspond to the synchronization in the memory device200aofFIG.5or the synchronization in the memory device200bofFIG.7.

In an embodiment, at time tp1, a command may be determined as the CASL. In an embodiment, the command CMD for changing settings of a mode register before time tp1is received, and the number of times that the data clock signal WCK toggles is determined as the reference cycle count (or number). At time tp1, a command may be determined as the CAS.

During the preparation time period tSYNC_Prepare from time tp1, a memory device prepares toggling of the data clock signal WCK. During the time period tWCK_Toggle from time tp4, the memory device allows the data clock signal WCK to toggle. In this case, the time period tWCK_Toggle may be a time period extended based on the CASL or the setting change of the mode register. For example, the time period tWCK_Toggle may be longer than the first time period 1st tWCK_Toggle ofFIG.4C. In an embodiment, the first time period 1st tWCK_Toggle has a first duration and the duration of the time period tWCK_Toggle is a sum of the first duration and a second duration of the clock section indicated by the CASL or the setting change. Thus, the duration of the time period tWCK_Toggle is extended by the second duration.

At time tp5, the data clock signal WCK may continuously toggle. Because the synchronization of the data clock signal WCK is not disabled, a command for initiation of the synchronization may not be required. For example, because the toggling of the data clock signal WCK is maintained at time tp5, the CAS for a second write operation may not be required. Since one cycle where the command CMD for the CAS is received is omitted, the time period 2nd tValid_Data may be shortened. As such, processing of the second data stream may quicken. For example, a time tpd4cwhen the processing of the second data stream is completed may be earlier than a time tpd4ofFIG.4C, at which the processing of the second data stream is completed.

In an embodiment, a command received immediately before the second write command is not the CAS command in the LPDDR5. For example, the CA received at time tp6may be determined as a write command based on the command truth table, and the CA received at time tp5may be determined as the DES (i.e., as not being the CAS) based on the command truth table.

As described above, according to an embodiment of the present disclosure, there is provided a method for improving a speed, at which data are processed in a memory device, by extending the synchronization of the data clock signal WCK.

FIG.10is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Referring toFIG.10, an electronic device40includes a memory controller100cand a memory device200c. The memory device200cincludes the I/O control circuit230, a first memory rank240a, and a second memory rank240b. Each of the first memory rank240aand the second memory rank240bmay include a plurality of memory banks. The memory controller100cmay output the command CMD, the address ADD, the clock signal CK, and the data clock signal WCK to the memory device200c. The memory controller100cmay exchange data with the memory device200c. The clock signal CK, the data clock signal WCK, and data are similar to the clock signal CK, the data clock signal WCK, and the data inFIG.1, and thus, additional description will be omitted to avoid redundancy.

The memory device200cmay receive the command CMD and the address ADD from the memory controller100c. The command CMD includes CMD_R1and CMD_R2. CMD_R1may indicate a command to be performed in the first memory rank240a. CMD_R2may indicate a command to be performed in the second memory rank240b. CS_R1may indicate a signal indicating whether to select the first memory rank240a. CS_R2may indicate a signal indicating whether to select the second memory rank240b.

The I/O control circuit230may control the first memory rank240abased on CS_R1and CMD_R1. For example, the I/O control circuit230may select the first memory rank240abased on CS_R1, and based on CMD_R1, the I/O control circuit230may write data in the first memory rank240aor may read data from the first memory rank240a.

The I/O control circuit230may control the second memory rank240bbased on CS_R2and CMD_R2. For example, the I/O control circuit230may select the second memory rank240bbased on CS_R2, and based on CMD_R2, the I/O control circuit230may write data in the second memory rank240bor may read data from the second memory rank240b.

In an embodiment, the I/O control circuit230independently controls the first memory rank240aand the second memory rank240b. For example, while the I/O control circuit230writes data in the first memory rank240a, the I/O control circuit230may read data from the second memory rank240b. Alternately, while the I/O control circuit230writes data in the second memory rank240b, the I/O control circuit230may read data from the first memory rank240a.

FIG.11Ais a timing diagram illustrating data streams that are processed according to an embodiment of the present disclosure. A method for processing a plurality of data streams in a memory device where the synchronization of the data clock signal WCK is not extended will be described with reference toFIG.11A.

Referring toFIG.11A, waveforms of CK_t, CK_c, CS_R1, CMD_R1, CS_R2, CMD_R2, WCK_t, WCK_c, DQ, and DMI are illustrated by way of example. InFIG.11A, a horizontal axis represents a time. In CK_t, CK_c, WCK_t, WCK_c, DQ, and DMI, meanings and a correspondence relationship with a memory device are similar to those described with reference toFIG.4A, and CS_R1, CMD_R1, CS_R2, and CMD_R2are similar to those described with reference toFIG.10. Thus, additional description will be omitted to avoid redundancy. The timing diagram ofFIG.11Awill be described with reference toFIGS.10and11A.

The memory device200cmay process the first data stream through the first memory rank240aand may process the second data stream through the second memory rank240b. For example, the memory device200cmay process the first data stream during the time period 1st tWCK_SYNC. Afterwards, the memory device200cmay process the second data stream during the time period 2nd tWCK_SYNC.

At time tp4, the memory device200cmay allow the data clock signal WCK to toggle at the reference frequency. After the time period 1st tWCK_Toggle passes from time tp4, the synchronization of the data clock signal WCK may be disabled at time tp5. After the synchronization of the data clock signal WCK is disabled, processing of the second data stream may be requested. To again perform the synchronization of the data clock signal WCK, the memory device200cmay again prepare the toggling of the data clock signal WCK during the preparation time period 2nd tSYNC_Prepare, based on a new CAS (e.g., the CAS determined at time tp6). As such, processing of the second data stream may be delayed.

FIG.11Bis a timing diagram illustrating data streams that are processed based on a data clock signal in which synchronization is extended, according to an embodiment of the present disclosure. A method for processing a plurality of data streams in a memory device where the synchronization of the data clock signal WCK is extended will be described with reference toFIG.11B.

Referring toFIG.11B, waveforms of CK_t, CK_c, CS_R1, CMD_R1, CS_R2, CMD_R2, WCK_t, WCK_c, DQ, and DMI are illustrated by way of example. In each waveform, the meaning and a correspondence relationship of a memory device are similar to those described with reference toFIG.11A, and thus, additional description will be omitted to avoid redundancy. The timing diagram ofFIG.11Bwill be described with reference toFIGS.10and11B.

In an embodiment, at time tp1, a command may be determined as the CASL. In an embodiment, the command CMD for changing settings of a mode register before time tp1may be received, and the number of times that the data clock signal WCK toggles may be determined as the reference cycle count (or number) (e.g., greater than the default cycle count (or number)). At time tp1, a command may be determined as the CAS. As such, the synchronization of the data clock signal WCK of the memory device200cmay be extended. For example, the time period tWCK_Toggle corresponding to the synchronization of the data clock signal WCK may be from tp4to tp10x, and the time period tWCK_Toggle may be longer than the time period 1st tWCK_Toggle inFIG.11A.

In an embodiment, the memory device200cprocesses the first data stream and the second data stream in parallel, based on the extended synchronization of the data clock signal WCK. For example, the memory device200cmay process the first data stream during the time period 1st tValid_Data. Before the processing of the first data stream is completed, at time tp6x, the memory device200cmay determine a write command for the second data stream. In this case, because the toggling of the data clock signal WCK is maintained, the memory device200cmay process the second data stream without the CAS for a write operation of the second data stream. At time tpd4x, the memory device200cmay complete the processing of the second data stream based on the toggling of the data clock signal WCK thus extended.

As described above, the memory device200cmay process the first data stream and the second data stream in parallel based on the extended synchronization of the data clock signal WCK, thus improving a data processing speed. For example, a time tpd4xwhen the processing of the second data stream is completed may be earlier than a time tpd4ofFIG.11A, at which the processing of the second data stream is completed.

FIG.12Ais a block diagram illustrating a memory device according to an embodiment of the present disclosure. Referring toFIG.12A, a memory device200dincludes the CMD/ADD receiver210, the CMD/ADD circuit211, the mode register212, the synchronization circuit220, the CK receiver221, the WCK receiver222, the internal clock circuit223, the I/O control circuit230, the write data receiver231, the read data transmitter232, and the plurality of memory ranks240.

The CMD/ADD receiver210, the CMD/ADD circuit211, the mode register212, the synchronization circuit220, the CK receiver221, the WCK receiver222, the I/O control circuit230, the write data receiver231, the read data transmitter232, and the plurality of memory ranks240are similar to those described with reference toFIG.3, and thus, additional description will be omitted to avoid redundancy.

In an embodiment, the internal clock circuit223may receive the synchronized data clock signal SWCK from the synchronization circuit220. The internal clock circuit223may output an internal clock signal to the I/O control circuit230based on the synchronized data clock signal SWCK.

In an embodiment, the internal clock signal is a four-phase clock signal. For example, the internal clock circuit223may include a four-phase converter. The four-phase converter may generate a four-phase clock signal based on the synchronized data clock signal SWCK. The four-phase clock may include a first phase clock signal WCK0, a second phase clock signal WCK90, a third phase clock signal WCK180, and a fourth phase clock signal WCK270.

Phases of the first to fourth phase clock signals WCK0, WCK90, WCK180, and WCK270may be different from one another. For example, a phase of the first phase clock signal WCK0may be the same as a phase of the synchronized data clock signal SWCK. A phase of the second phase clock signal WCK90may be delayed with respect to the phase of the synchronized data clock signal SWCK by as much as 90 degrees. A phase of the third phase clock signal WCK180may be delayed with respect to the phase of the synchronized data clock signal SWCK by as much as 180 degrees. A phase of the fourth phase clock signal WCK270may be delayed with respect to the phase of the synchronized data clock signal SWCK by as much as 270 degrees.

The first to fourth phase clock signals WCK0, WCK90, WCK180, and WCK270may be used to process different data. For example, when processing of a data stream including first to fourth data is requested, the memory device200dmay process the first data of the data stream based on the first phase clock signal WCK0. The memory device200dmay process the second data of the data stream based on the second phase clock signal WCK90. The memory device200dmay process the third data of the data stream based on the third phase clock signal WCK180. The memory device200dmay process the fourth data of the data stream based on the fourth phase clock signal WCK270.

FIG.12Bis a timing diagram illustrating data clock signals and a data signal ofFIG.12A, according to an embodiment of the present disclosure. Referring toFIG.12B, waveforms of WCK_t, WCK_c, WCK0, WCK90, WCK180, WCK270, and DQ are illustrated by way of example. InFIG.12B, a horizontal axis represents a time. WCK_t and WCK_c may correspond to the data clock signal WCK or the synchronized data clock signal SWCK ofFIG.12A. WCK0, WCK90, WCK180, and WCK270may correspond to the first to fourth phase clock signals WCK0, WCK90, WCK180, and WCK270ofFIG.12A, respectively. DQ may correspond to data DQ for a write operation ofFIG.12Aor data DQ for a read operation ofFIG.12A. DQ may indicate a data stream including a plurality of data D1to D10.

Referring toFIGS.12A and12B, the memory device200dmay generate the first to fourth phase clock signals WCK0, WCK90, WCK180, and WCK270based on the synchronized data clock signal SWCK. The first to fourth phase clock signals WCK0, WCK90, WCK180, and WCK270may have phase differences of 0 degree, 90 degrees, 180 degrees, and 270 degrees with respect to the synchronized data clock signal SWCK. Cycles (or periods) of the first to fourth phase clock signals WCK0, WCK90, WCK180, and WCK270may be the same. For example, a cycle may correspond to a time period from tp1fto tp5f.

At time tp1f, the memory device200dmay process the first data D1of the data stream corresponding to the DQ in response to a rising edge of the first phase clock signal WCK0. The rising edge may mean that a logical state of a clock signal changes from logical low to logical high. At time tp2f, the memory device200dmay process the second data D2of the data stream corresponding to the DQ in response to a rising edge of the second phase clock signal WCK90. At time tp3f, the memory device200dmay process the third data D3of the data stream corresponding to the DQ in response to a rising edge of the third phase clock signal WCK180. At time tp4f, the memory device200dmay process the fourth data D4of the data stream corresponding to the DQ in response to a rising edge of the fourth phase clock signal WCK270.

FIG.13is a timing diagram illustrating data streams that are processed based on a data clock signal selectively extended, according to an embodiment of the present disclosure. A graph of data streams that are processed when a processing interval is longer than or equal to a reference interval is illustrated inFIG.13. Also, a graph of data streams that are processed when the processing interval is shorter than the reference interval is illustrated.

The processing interval may mean a time interval between processing commands (e.g., read commands or write commands). The reference interval may be a time interval being a reference for determining whether to extend synchronization of a data clock signal. In each time and each waveform, the meaning and a correspondence relationship of a memory device are similar to those described with reference toFIGS.4A and9, and thus, additional description will be omitted to avoid redundancy.

According to an embodiment of the present disclosure, an electronic device may include a memory device and a memory controller controlling the memory device. The memory controller may include information about a time interval (i.e., a processing interval) between consecutive processing commands.

In an embodiment, when the processing interval is longer than or equal to the reference interval, the memory controller may determine that it is inefficient to extend the synchronization of the data clock signal. For example, when the processing interval is longer than or equal to the reference interval, the memory controller may determine that the extension of the synchronization of the data clock signal causes an increase in power consumption due to maintaining the synchronization of the data clock signal, rather than improving a data processing speed by omitting the CAS command.

In an embodiment, when the processing interval is shorter than the reference interval, the memory controller may determine that it is efficient to extend the synchronization of the data clock signal. For example, when the processing interval is shorter than the reference interval, the memory controller may determine that the extension of the synchronization of the data clock signal improves a data processing speed, rather than increasing power consumption due to maintaining the synchronization of the data clock signal.

InFIG.13, referring to an embodiment of a first processing interval, the memory device may determine a first write command at time tpra1and may determine a second write command at time tpra2. A time interval from time tpra1when the first write command is determined to time tpra2when the second write command is determined may be referred to as a “first processing interval”. The memory controller may store information about the first processing interval.

In an embodiment, the memory controller determines whether the first processing interval is longer than or equal to the reference interval. When the first processing interval is longer than or equal to the reference interval, it may be inefficient to extend the synchronization of the data clock signal. The memory device does not extend the synchronization of the data clock signal under control of the memory controller. For example, at time tp5, the memory device200terminates the synchronization of the data clock signal WCK. A time interval from tp5to tp6rmay be long. At time tp6r, the memory device may determine the CAS command. At time tp9r, the memory device may again perform the synchronization of the data clock signal WCK.

InFIG.13, referring to an embodiment of a second processing interval, the memory device may determine the first write command at time tprb1and may determine the second write command at time tprb2. A time interval from time tprb1when the first write command is determined to time tprb2when the second write command is determined may be referred to as a “second processing interval”. The memory controller may store information about the second processing interval.

In an embodiment, the memory controller determines whether the second processing interval is shorter than the reference interval. When the second processing interval is shorter than the reference interval, it may be efficient to extend the synchronization of the data clock signal. The memory device may extend the synchronization of the data clock signal under control of the memory controller.

For example, the memory controller may generate a command (e.g., the CASL) that indicates initiation of the synchronization of the data clock signal and defines a clock section corresponding to the synchronization. Alternatively, the memory controller may generate a command including mode register setting information for changing the number of times of toggling of the data clock signal to the reference cycle count (or number). The number of times of toggling of the data clock signal may be changed to the reference cycle count (or number). As such, the data clock signal may continuously toggle from time tp4to time tp5r. For better understanding of the present disclosure, the processing interval may be illustrated as being between the first write command and the second write command, but the present disclosure is not limited thereto. For example, the first write command may be changed to a first read command, and the second write command may be changed to a second read command.

FIG.14is a flowchart illustrating an operating method of a memory device according to an embodiment of the present disclosure. An operating method of a memory device will be described with reference toFIG.14. The memory device may correspond to at least one of the memory device200ofFIG.3, the memory device200aofFIG.5, the memory device200cofFIG.10, and the memory device200dofFIG.12A. The memory device may communicate with a memory controller.

In operation S110, the memory device may receive a command from the memory controller. The command may define a clock section that indicates initiation of synchronization of a data clock signal and corresponds to the synchronization. For example, the command may be the CASL being a defined command.

In an embodiment, the clock section defined by the command in operation S110is longer than a clock section corresponding to the synchronization of the data clock signal, which is performed based on the CAS command in the LPDDR5.

In an embodiment, in operation S110, after receiving the command indicating the initiation of the synchronization of the data clock signal and defining the clock section, the memory device further receives a first processing command for processing a first data stream and a second processing command for processing a second data stream. For example, the first processing command may be a write command or a read command for the first data stream. The second processing command may be a write command or a read command for the second data stream. In an embodiment, a command received immediately before the second processing command is not the CAS and is not the CASL.

In operation S120, the memory device prepares toggling of the data clock signal during a preparation time period. In an embodiment, the preparation time period sequentially includes a first time period in which the data clock signal is in the don't care state, a second time period in which the data clock signal is maintained in a given logical state, and a third time period in which the data clock signal pre-toggles at a frequency lower than a reference frequency. The pre-toggling of the data clock signal may be performed by toggling the data clock signal at the frequency lower than the reference frequency.

In operation S130, the memory device processes the first data stream based on the data clock signal toggling at the reference frequency. In an embodiment, the memory device allows the data clock signal to toggle at the reference frequency during a fourth time period and then processes the first data stream. In an embodiment, the memory device generates a four-phase clock signal based on the data clock signal and processes the first data stream based on the four-phase clock signal.

In operation S140, the memory device processes the second data stream based on the data clock signal toggling at the reference frequency and the defined clock section. For example, unlike operation S130in which the first data stream is processed, the second data stream may be processed within a time period where the synchronization of the data clock signal is extended by the CASL.

In an embodiment, the memory device allows the data clock signal to toggle at the reference frequency during a fifth time period and then processes the second data stream. In an embodiment, the memory device generates the four-phase clock signal based on the data clock signal and then processes the second data stream based on the four-phase clock signal. In this case, the four-phase clock signal may continuously toggle from when the first data stream is processed in operation S130to when the second data stream is processed.

In an embodiment, the memory device processes a plurality of data streams through a plurality of memory ranks. For example, in operation S130, the memory device may process the first data stream through a first memory rank. In operation S140, the memory device may process the second data stream through a second memory rank. In this case, a time at which the processing of the second data stream starts may be earlier than a time at which the processing of the first data stream is completed.

FIG.15is a flowchart illustrating an operating method of a memory device according to some embodiments of the present disclosure. An operating method of a memory device will be described with reference toFIG.15. The memory device may correspond to at least one of the memory device200ofFIG.3, the memory device200bofFIG.7, the memory device200cofFIG.10, and the memory device200dofFIG.12A. The memory device may communicate with a memory controller.

In operation S210, the memory device receives a first command and a second command from the memory controller. The first command includes mode register setting information. The second command indicates initiation of synchronization of a data clock signal. For example, the first command may include the mode register setting information for extending the synchronization of the data clock signal. The second command may be the CAS command in the LPDDR5.

In an embodiment, in operation S210, after receiving the first command and the second command, the memory device may further receive a first processing command for processing a first data stream and a second processing command for processing a second data stream. In an embodiment, a command received immediately before the second processing command is not the CAS and is not the CASL.

In operation S215, the memory device changes settings of a mode register based on the mode register setting information. For example, the memory device may decode the first command received in operation S210to obtain the mode register setting information. Based on the mode register setting information, the memory device may determine the number of times that the data clock signal toggles with regard to the synchronization, as a reference cycle count (or number). In this case, the reference cycle count (or number) may be greater than a default cycle count (or number) by which the data clock toggles, which is defined in the LPDDR5.

In operation S220, the memory device prepares toggling of the data clock signal during a preparation time period. In an embodiment, the preparation time period sequentially includes a first time period in which the data clock signal is in the don't care state, a second time period in which the data clock signal is maintained in a given logical state, and a third time period in which the data clock signal pre-toggles at a frequency lower than a reference frequency.

In operation S230, the memory device processes the first data stream based on the data clock signal toggling at the reference frequency. In an embodiment, the memory device allows the data clock signal to toggle at the reference frequency during a fourth time period and then processes the first data stream. In an embodiment, the memory device generates a four-phase clock signal based on the data clock signal and processes the first data stream based on the four-phase clock signal.

In operation S240, the memory device processes the second data stream based on the data clock signal toggling at the reference frequency and the changed settings of the mode register. For example, unlike operation S230in which the first data stream is processed, the second data stream may be processed within a time period that is extended based on the changed settings of the mode register.

In an embodiment, the memory device allows the data clock signal to toggle at the reference frequency during a fifth time period and then processes the second data stream. In an embodiment, the memory device generates the four-phase clock signal based on the data clock signal and processes the second data stream based on the four-phase clock signal. In an embodiment, the memory device processes a plurality of data streams through a plurality of memory ranks.

FIG.16is a flowchart illustrating an operating method of an electronic device according to an embodiment of the present disclosure. The operating method of the electronic device will be described with reference toFIG.16. The electronic device may include a memory controller and a memory device. The electronic device may correspond to at least one of the electronic device10ofFIG.1, the electronic device20ofFIG.5, the electronic device30ofFIG.7, the electronic device40ofFIG.10, and an electronic device including the memory device200dofFIG.12A.

In operation S310, the memory controller of the electronic device issues a command. The command is for extending synchronization of a data clock signal. For example, the command may be the CASL being a defined command. Alternatively, the command may include mode register setting information for extending the synchronization of the data clock signal.

In operation S320, the memory device of the electronic device prepares a toggling of the data clock signal during a preparation time period. In operation S330, the memory device of the electronic device processes a first data stream based on the data clock signal toggling at the reference frequency. In operation S340, the memory device of the electronic device processes a second data stream based on the data clock signal toggling at the reference frequency. A time at which the second data stream is processed may be included in a synchronization period of the data clock signal that is extended based on the command in operation S310.

FIG.17is a flowchart illustrating an operating method of an electronic device according to an embodiment of the present disclosure. The operating method of the electronic device will be described with reference toFIG.17. The electronic device may include a memory controller and a memory device. The electronic device may correspond to at least one of the electronic device10ofFIG.1, the electronic device20ofFIG.5, the electronic device30ofFIG.7, the electronic device40ofFIG.10, and an electronic device including the memory device200dofFIG.12A. As in the embodiment ofFIG.13, the electronic device may compare a processing interval and a reference interval to determine whether to extend synchronization of a data clock signal.

In operation S410, the electronic device determines whether the processing interval is shorter than the reference interval. For example, a memory controller of the electronic device may determine whether a processing interval between a first processing command and a second processing command is shorter than the reference interval.

The first processing command may be a first read command for a first data stream or a first write command for the first data stream. The second processing command may be a second read command for a second data stream or a second write command for the second data stream. The reference interval may be a time interval being a reference for determining whether to extend the synchronization of the data clock signal.

When it is determined in operation S410that the processing interval is shorter than the reference interval, the electronic device performs operation S415. In operation S415, the memory controller of the electronic device generates an extension command for extending the synchronization of the data clock signal.

In an embodiment, the extension command is a defined command (e.g., the CASL). For example, the defined command may indicate the initiation of the synchronization of the data clock signal and may define a clock section that corresponds to the synchronization.

In an embodiments, the extension command includes a mode register change command including mode register setting information and an initiation command (e.g., the CAS in the LPDDR5) indicating the initiation of the synchronization of the data clock signal.

In operation S420, the memory device of the electronic device prepares toggling of the data clock signal during a preparation time period, based on the extension command. In operation S430, the memory device processes the first data stream corresponding to the first processing command based on the data clock signal toggling at the reference frequency. In operation S440, the memory device of the electronic device processes the second data stream corresponding to the second processing command based on the data clock signal toggling at the reference frequency. In this case, the toggling of the data clock signal may be extended based on the extension command in operation S415, and the toggling of the data clock signal may be continuously maintained while both the first data stream and the second data stream are processed.

When it is determined in operation S410that the processing interval is longer than or equal to the reference interval, the electronic device performs operation S450. In operation S450, the memory controller of the electronic device generates a first initiation command and a second initiation command. For example, the first initiation command may be a command indicating the initiation of the synchronization of the data clock signal for the purpose of processing the first processing command. The second initiation command may be a command indicating the initiation of the synchronization of the data clock signal for the purpose of processing the second processing command. In an embodiment, each of the first initiation command and the second initiation command are the CAS command in the LPDDR5.

In operation S460, the memory device of the electronic device processes the first data stream based on the first initiation command. For example, the memory device of the electronic device may process the first data stream corresponding to the first processing command based on the data clock signal toggling based on the first initiation command.

In an embodiment, operation S460may include preparing, by the memory device, toggling of the data clock signal during a preparation time period based on the first initiation command, processing, by the memory device, the first data stream based on the data clock signal toggling at the reference frequency, and terminating, by the memory device, the toggling of the data clock signal after the processing of the first data stream (i.e., terminating the synchronization of the data clock signal).

In operation S470, the memory device of the electronic device processes the second data stream based on the second initiation command. For example, the memory device of the electronic device may process the second data stream corresponding to the second processing command based on the data clock signal toggling based on the second initiation command. In this case, unlike the case of processing the second data stream in operation S440, after toggling is terminated in operation S460, the data clock signal in operation S470may again toggle based on the second initiation command.

In an embodiment, operation S470include preparing, by the memory device, toggling of the data clock signal during a preparation time period based on the second initiation command, processing, by the memory device, the second data stream based on the data clock signal toggling at the reference frequency, and terminating, by the memory device, the toggling of the data clock signal after the processing of the second data stream (i.e., terminating the synchronization of the data clock signal).

FIG.18is a block diagram illustrating an electronic system according to an embodiment of the present disclosure. Referring toFIG.18, an electronic system1000includes an electronic device1200. The electronic device1200may correspond to at least one of the electronic device10ofFIG.1, the electronic device20ofFIG.5, the electronic device30ofFIG.7, the electronic device40ofFIG.10, and an electronic device including the memory device200dofFIG.12A. An operating method of the electronic device1200may correspond to the flowchart ofFIG.16. The electronic device1200may include the memory device200. An operating method of the memory device200may correspond to at least one of the flowchart ofFIG.14and the flowchart ofFIG.15.

The electronic system1000may be a mobile system such as a mobile phone, a smartphone, a tablet PC, a wearable device, a health care device, or an Internet of things (IoT) device. However, the electronic system1000is not limited to the mobile system. For example, the electronic system1000may be a system such as a personal computer, a laptop, a server, a media player, or an automotive device such as a navigation device.

The electronic system1000may include a main processor1100, the electronic device1200, and storage devices1300aand1300b, and may further include one or more of an optical input device1410, a user input device1420, a sensor1430, a communication device1440, a display1450, a speaker1460, a power supplying device1470, and a connecting interface1480.

The main processor1100may control overall operations of the electronic system1000. For example, the main processor1100may control operations of the remaining components of the electronic system1000implementing the electronic system1000. The main processor1100may be implemented with a general-purpose processor, a special-purpose processor, or an application processor.

The main processor1100may include one or more CPU cores1110, and may further include a controller1120for controlling the electronic device1200and/or the storage devices1300aand1300b. In some embodiments, the main processor1100may further include an accelerator1130being a dedicated circuit for high-speed data computation such as artificial intelligence (AI) data computation. The accelerator1130may include a graphics processing unit (GPU), a neural processing unit (NPU), and/or a data processing unit (DPU) and may be implemented with a separate chip physically independent of any other component of the main processor1100.

The electronic device1200may be a volatile memory such as a DRAM and/or an SRAM. The electronic device1200may be implemented within the same package as the main processor1100.

The storage devices1300aand1300bmay function as a nonvolatile storage device that stores data regardless of whether power is supplied, and may have a relatively high capacity compared to the electronic device1200. The storage device1300amay include a storage controller1310aand a flash memory1320astoring data under control of the storage controller1310a, and the storage device1300bmay include a storage controller1310band a flash memory1320bstoring data under control of the storage controller1310b. Each of the flash memories1320aand1320bbeing non-volatile memories may include a flash memory of a two-dimensional (2D) structure or a V-NAND flash memory of a three-dimensional structure or may include a different kind of nonvolatile memory such as a PRAM and/or a RRAM.

The storage devices1300aand1300bmay be included in the electronic system1000in a state of being physically separated from the main processor1100or may be implemented within the same package as the main processor1100. Also, the storage devices1300aand1300bmay have a shape identical to that of a solid state drive (SSD) or a memory card so as to be removable from any other components of the electronic system1000through an interface such as the connecting interface1480to be described later. The storage devices1300aand1300bmay include a device to which the standard such as universal flash storage (UFS), embedded multi-media card (eMMC), or non-volatile memory express (NVMe) is applied, but is not limited thereto.

The optical input device1410may photograph (or capture) a still image or a moving image and may include a camera, a camcorder, and/or a webcam.

The user input device1420may receive various types of data input by a user of the electronic system1000and may include a touch pad, a keypad, a keyboard, a mouse, and/or a microphone.

The sensor1430may detect various types of physical quantities capable of being obtained from the outside of the electronic system1000and may convert the detected physical quantities to electrical signals. The sensor1430may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and/or a gyroscope sensor.

The communication device1440may communicate with external devices of the electronic system1000in compliance with various communication protocols. The communication device1440may be implemented to include an antenna, a transceiver, and/or a MODEM.

The display1450and the speaker1460may function as an output device that outputs visual information and auditory information to the user of the electronic system1000.

The power supplying device1470may appropriately convert a power supplied from a battery (not illustrated) embedded in the electronic system1000and/or an external power source so as to be supplied to each component of the electronic system1000.

The connecting interface1480may provide a connection between the electronic system1000and an external device. The connecting interface1480may be implemented with various interfaces such as an ATA (Advanced Technology Attachment) interface, an SATA

According to at least one embodiment of the present disclosure, an operating method of a memory device for extending synchronization of a data clock signal, and an operating method of an electronic device including the memory device are provided.

Also, according to at least one embodiment of the present disclosure, since synchronization of a data clock signal is extended based on a defined command or a setting change of a mode register, a memory device is provided that is capable of skipping additional synchronization of the data clock signal and improving a data processing speed.