Circuit apparatus and method for testing integrated circuits using weighted pseudo-random test patterns

A method for testing an electronic circuit includes selecting an input signal using a first multiplexer, selecting a signal to be input to the first multiplexer using at least one other multiplexer, and controlling the at least one other multiplexer using a selection signal output from a control circuit.

FIELD OF THE INVENTION

The present invention relates to testing of integrated electronic circuits, and in particular, to built-in self test circuits and methods for testing the functionality of integrated electronic circuits.

BACKGROUND OF THE INVENTION

A single very large scale integration (VLSI) semiconductor chip may contain thousands of interconnected logic gates which may include, for example, AND, OR, NAND, NOR, and XOR gates. A critical part of the manufacturing process for any such integrated circuit is verifying the functionality of the logic gates included in the integrated circuit. Verifying the functionality of each logic gate can be difficult because of the limited number of input/output (I/O) pins for the integrated circuit and the complex interconnections between the inputs and outputs of the multitude of logic gates. In many cases, multiple channels within the integrated circuit share I/O pins.

During functional tests of an integrated circuit contained within a semiconductor chip, the integrated circuit's inputs receive known digital data patterns, made up of sequences of 0s and 1s, that are input to the logic gates internal to the chip. In response, the logic gates process the input data patterns, and eventually, the integrated circuit generates output data patterns, again made up of sequences of 0s and 1s, that are dependent upon the input data patterns and the functionality of the logic gates. When the output data patterns do not match predicted output data patterns, it is known that a fault has occurred in at least one of the logic gates.

One option for integrated circuit functional testing involves the application of multiple data patterns to the inputs of the chip in hopes of generating every predicted output data pattern. However, such a test process may require extremely long test times due to the need for generating and inputting a large number of different input data patterns.

Another option involves the application of random data patterns to the integrated circuit's inputs in hopes of identifying defective logic gates. Again, the measured data patterns output from the logic circuit are compared to predicted output data patterns. However, one problem associated with applying random data patterns is that only a portion of the logic circuits will be tested, and therefore, there is a likelihood that an integrated circuit having a defect may go undetected. Applying a larger number of random input data patterns to the integrated circuit's inputs will increase the likelihood that more of the logic gates will be tested. However, the increased number of input data patterns lengthens the overall test time, and thus, increases the overall manufacturing cost for the integrated circuit.

Many integrated circuits include logic gate structures that are difficult to test using a purely random input data pattern. An example of such a logic gate structure is an AND gate. The probability of faults being detected in an AND gate decreases as the number of inputs to the AND gate increases. Initially, in order to check the AND gate for faults, all of the AND gate's inputs must receive an input digit of 1 in order for the signal output from the AND gate to be 1. Next, all but one of the AND gate's inputs should be 1 in order to verify the correct functioning of the AND gate. Therefore, the bits that make up the data pattern input to the integrated circuit must be configured so as to facilitate the various bit changes that must be input to each of the AND gate's inputs.

In order to deal with the limitations of the random number generation test, testing methods that alter the probabilities of generating a 0 or a 1 have been developed. These testing methods weight random input data patterns using a weighted random number generator so as to perform specific tests of a desired logic gate. The weighted random number generator outputs weighted random input patterns to the integrated circuit under test. In the weighted random input patterns, the probability that the input digit is 0 is multiplied by a weighting factor times one half, and the probability that the input digit is 1 is one minus the weighting factor time one half, where the weighting factor is a positive number. Thus, the weighting factor is expressed as a probability of occurrence of a 0 or a 1. The weighting factor is selected dependent upon the number of inputs to the integrated circuit and the number and type of logic gates internal to the chip. In addition, the weighting factor is selected in a manner to facilitate time and cost efficient testing with an acceptable level of confidence that no faults exist in the logic circuit.

SUMMARY OF THE INVENTION

An exemplary circuit for testing an electronic circuit, which weights a plurality of pseudo-random data patterns and inputs signals of the weighted pseudo-random data patterns to an electronic circuit to be tested, includes at least one input logic gate, at least one input multiplexer, at least one control circuit, a first multiplexer, an output logic gate, an output multiplexer, and a weight channel circuit. The at least one input logic gate is configured to receive at least one signal of a pseudo-random data pattern. The at least one input multiplexer is configured to receive a signal that is the same as the signal of the pseudo-random data pattern inputted to the input logic gate and a signal outputted from the input logic gate, and to select and output one of the signals. The at least one control circuit is configured to input a selection signal to the input multiplexer, the selection signal being used for selecting the signal outputted from the input multiplexer. The first multiplexer is configured to receive a signal that is the same as the signal of the pseudo-random data pattern inputted to the input logic gate and a signal outputted from the input multiplexer, and to select and output one of the signals. The output logic gate is configured to receive a signal outputted from the first multiplexer to one input of the output logic gate. The output multiplexer is configured to receive the signal outputted from the output logic gate and a signal inputted from an external input, and to select and input one of the signals to the electronic circuit. The weight channel circuit is configured to input a weight selection signal to the first multiplexer from a selection output of the weight channel circuit, the weight selection signal being used for selecting one of the signals outputted from the first multiplexer, to input another weight selection signal to the output multiplexer from an additional output of the weight channel circuit, the weight selection signal being used for selecting one of the signals outputted from the output multiplexer, the weight channel circuit having another output connected to another input of the output logic gate.

An apparatus for testing an electronic circuit includes a pseudo-random binary number generator, a programmable weighted random pattern generator, and a data compressing device. The pseudo-random binary number generator is configured to generate a plurality of pseudo-random data patterns and output the pseudo-random data patterns. The programmable weighted random pattern generator is provided between the pseudo-random binary number generator and an electronic circuit to be tested, and is configured to receive and weight the pseudo-random data patterns, and to input the weighted pseudo-random data patterns to the electronic circuit. The data compressing device is configured to receive a plurality of output data patterns which the electronic circuit generates in accordance with the weighted pseudo-random data patterns inputted to the electronic circuit and an internal error state of the electronic circuit, and to compress the output data patterns into a unique signature. The programmable weighted random generator has a circuit for testing an electronic circuit that includes at least one input logic gate, at least one input multiplexer, at least one control circuit, a first multiplexer, an output logic gate, an output multiplexer, and a weight channel circuit. The at least one input logic gate is configured to receive at least one signal of a pseudo-random data pattern. The at least one input multiplexer is configured to receive a signal that is the same as the signal of the pseudo-random data pattern inputted to the input logic gate and a signal outputted from the input logic gate, and to select and output one of the signals. The at least one control circuit is configured to input a selection signal to the input multiplexer, the selection signal being used for selecting the signal outputted from the input multiplexer. The first multiplexer is configured to receive a signal that is the same as the signal of the pseudo-random data pattern inputted to the input logic gate and a signal outputted from the input multiplexer, and to select and output one of the signals. The output logic gate is configured to receive a signal outputted from the first multiplexer to one input of the output logic gate. The output multiplexer is configured to receive the signal outputted from the output logic gate and a signal inputted from an external input, and to select and input one of the signals to the electronic circuit. The weight channel circuit is configured to input a weight selection signal to the first multiplexer from a selection output of the weight channel circuit, the weight selection signal being used for selecting one of the signals outputted from the first multiplexer, to input another weight selection signal to the output multiplexer from an additional output of the weight channel circuit, the weight selection signal being used for selecting one of the signals outputted from the output multiplexer, the weight channel circuit having another output connected to another input of the output logic gate.

A method for testing an electronic circuit includes generating a plurality of pseudo-random data patterns, causing a circuit for testing an electronic circuit to weight the pseudo-random data patterns, supplying signals of the weighted pseudo-random data patterns to an electronic circuit to be tested, compressing output data patterns into a unique signature, the output data patterns being patterns the electronic circuit generates in accordance with the signals and a fault state of the electronic circuit, and comparing the unique signature with a signature which the electronic circuit is expected to generate in a proper state, so as to detect a defect in the electronic circuit. The circuit for testing the electronic circuit includes at least one input logic gate configured to receive at least one signal of a pseudo-random data pattern, at least one input multiplexer configured to receive a signal that is the same as the signal of the pseudo-random data pattern inputted to the input logic gate and a signal outputted from the input logic gate, and to select and output one of the signals, at least one control circuit configured to input a selection signal to the input multiplexer, the selection signal being used for selecting the signal outputted from the input multiplexer, a first multiplexer configured to receive a signal that is the same as the signal of the pseudo-random data pattern inputted to the input logic gate and a signal outputted from the input multiplexer, and to select and output one of the signals, an output logic gate configured to receive a signal outputted from the first multiplexer to one input of the output logic gate, an output multiplexer configured to receive the signal outputted from the output logic gate and a signal inputted from an external input, and to select and input one of the signals to the electronic circuit, and a weight channel circuit configured to input a weight selection signal to the first multiplexer from a selection output of the weight channel circuit, the weight selection signal being used for selecting one of the signals outputted from the first multiplexer, to input another weight selection signal to the output multiplexer from an additional output of the weight channel circuit, the weight selection signal being used for selecting one of the signals outputted from the output multiplexer, the weight channel circuit having another output connected to another input of the output logic gate.

Other aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, which shows and describes exemplary embodiments of the invention, simply by way of illustration of the best mode contemplated for carrying out the invention. The invention is capable of other and different embodiments, and its several details are capable of modifications in various respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a block diagram of a typical logic built-in self test (“LBIST”) test configuration10which utilizes a psuedo-random pattern generation technique. The LBIST test configuration is also referred to as a scan-path structure called a self test using MSIR and parallel shift register sequence generator (“STUMPS”). The STUMPS structure is a built-in architecture for testing multiple chip systems at high throughput speeds. The LBIST test configuration includes a linear feedback shift register (“LFSR”)12, programmable weighted random pattern generator (“PWR”)14, integrated circuit to be tested16, and multiple input shift register (“MISR”)18. The LFSR as sixteen outputs20, comprised of four groups of four outputs22, that are coupled to sixteen corresponding inputs24of the PWR. The PWR has four outputs26that are coupled to four corresponding inputs28of the integrated circuit. The integrated circuit has four outputs30that are coupled to four corresponding inputs32of the MISR. The MISR has one output34.

While, inFIG. 1, the LFSR12is depicted as having only sixteen outputs20, the PWR14is depicted as having only sixteen inputs24and four outputs26, the integrated circuit under test16is depicted as having four inputs28and four outputs30, and the MISR18is depicted as having only four inputs32and one output34, any of the LFSR, PWR integrated circuit under test, and the MISR may have fewer or more inputs or outputs.

In operation, the LFSR12operates as a psuedo-random binary number generator that generates pseudo random data patterns that are output from the LFSR and are input to the PWR14. The PWR receives the pseudo random data patterns from the LFSR and weights the pseudo random data patterns to increase test efficiency. The resulting weighted pseudo-random data patters are output from the PWR and input to the integrated circuit under test16. The integrated circuit under test generates output data patterns that correspond to the input weighted pseudo random data patterns and the fault state of the logic gates included in the integrated circuit. The resulting output data patterns are output from the integrated circuit under test and input to the MISR18. The MISR compresses the output data patterns from the integrated circuit under test into a unique signature that represents the responses from the logic circuits included in the integrated circuit under test. The MISR-generated signature is output from the MISR and can be analyzed and compared to the predicted signature. Thus, after analyzing the measured and predicted signatures, it can be determine whether the integrated circuit under test is faulty.

As discussed previously, efforts to test for defective logic gates are more difficult for specific types of logic gates, for example, AND gates.FIG. 2depicts a STUMPS test configuration40that includes twelve flip-flops42–64, a first AND gate66, a second AND gate68, and an inverter70. The twelve flip-flops are configured in four columns72–78, wherein each of the columns includes three series-connected flip-flops. The flip-flops, first and second AND gates, and inverter can be selected from a number of commercially available flip-flops, AND gates, and inverters as desired.

The first AND gate66has three inputs80–84and one output86. The output of each of the three series-connected flip-flops42–46in the first column72is coupled to one of the inputs of the first AND gate. In particular, the first flip-flop's output88is coupled to the first AND gate's first input80, the second flip-flop's output90is coupled to the first AND gate's second input82, and the third flip-flop's output92is coupled to the first AND gate's third input84. The first AND gate's output is coupled to an input94of the fourth flip-flop48in the second column74.

The second AND gate68has three inputs96–100and one output102. The third flip-flop's output92is coupled to the second AND gate's first input96. The sixth flip-flop's output104is coupled to the input106of the inverter70. The output108of the inverter is coupled to the second AND gate's second input98. The ninth flip-flop's output110is coupled to the second AND gate's third input100. The second AND gate's output102is coupled to an input112of the twelveth flip-flop64.

As mentioned above, in order to test the function of the first and second AND gates66and68, all of the inputs80–84and96–100to the AND gates must be set to 1 and the outputs86and102of the AND gates is monitored as each input changes value from 1 to 0. Therefore, testing for a defect in either of the first or second AND gates can be difficult depending upon the weighted pseudo-random data patters output from the PWR14and input to the integrated circuit under test16. If the integrated circuit under test includes AND gates having many inputs, it is difficult to supply a “1” to all of the inputs of the AND gate using the pseudo-random pattern. Because of this difficulty brought on by the limited number of I/O channels114–120, fault coverage is limited.FIG. 2shows a test configuration40where defect A can be detected, however, defect B cannot be detected.

FIG. 3is a block diagram of a circuit configuration130that is included in a conventional PWR14that includes a first AND gate132, a second AND gate134, a third AND gate136, a 4-to-1 multiplexer138, an XOR gate140, and a weight channel circuit142. A first output144of the LFSR12is coupled to the 4-to-1 multiplexer's first input146and an input148of the first AND gate132. The LFSR's second output150is coupled to the other input152of the first AND gate132. The first AND gate's output154is coupled to the 4-to-1 multiplexer's second input156and an input158of the second AND gate134. The LFSR's third output160is coupled to the other input162of the second AND gate134. The second AND gate's output164is coupled to the 4-to-1 multiplexer's third input166and to an input168of the third AND gate136. The LFSR's fourth output170is coupled to the other input172of the third AND gate176. The third AND gate's output174is coupled to the 4-to-1 multiplexer's fourth input176.

The 4-to-1 multiplexer's two selection lines (only one shown)178are coupled to the selection outputs (only one shown)180of the weight channel circuit142. The 4-to-1 multiplexer's output182is coupled to one input184of the XOR gate140. The XOR gate's other input186is coupled to another output188of the weight channel circuit. Referring additionally toFIG. 1, the XOR gate's output190is coupled to an input of the circuit under test16.

As mentioned above, the circuit configuration130depicted inFIG. 3represents only a portion of the PWR14. Since the circuit configuration depicted inFIG. 3couples to four output lines22from the LFSR12and one input channel28of the circuit under test16, four of the circuit configurations depicted inFIG. 3would be included in the PWR. Therefore, the number of circuit configurations can vary and is dependent upon the number of outputs20from the LFSR and the number of input channels28for the circuit under test.

The first, second, and third AND gates132–136, the 4-to-1 multiplexer138, and the XOR gate140may be selected from a number of commercially available electronic parts as desired.

In operation, the circuit configuration130depicted inFIG. 3receives pseudo-random four-bit data patterns from the LFSR12. The probability of each of the four bits being a 0 or a 1 is ½. Therefore, the probability that the first bit output from the LFSR and received at the 4-to-1 multiplexer's first input146is 1 is ½. Since the probability of the first bit output from the LFSR and input to one input148of the first AND gate132being 1 is ½, and the probability of the second bit output from the LFSR and input to the other input152of the first AND gate132being 1 is ½, the probability of the signal output from the first AND gate132and input to the 4-to-1 multiplexer's second input156being 1 is ¼. Since the probability of the signal output from the first AND gate and input158to one input of the second AND gate134being 1 is ¼, and the probability of the third bit output from the LFSR and input to the other input162of the second AND gate134being 1 is ½, the probability of the signal output from the second AND gate and input to the 4-to-1 multiplexer's third input166being 1 is ⅛. Also, since the probability of the signal output from the second AND gate134and input to one input168of the third AND gate136being 1 is ⅛, and the probability of the fourth bit output from the LFSR and input to the other input172of the third AND gate136being 1 is ½, the probability of the signal output from the third AND gate136and input to the 4-to-1 multiplexer's fourth input176being 1 is 1/16.

The signal output from the 4-to-1 multiplexer138is controlled by the two weight selection signals output from the weight channel circuit142and input to the selection lines178of the 4-to-1 multiplexer. When the weight selection signals on the two selection lines is (0,0), (0,1), (1,0), or (1,1), the signal output from the 4-to-1 multiplexer is either the signal received by the 4-to-1 multiplexer's first input, second input, third input, or fourth input,146,156,166, and176, respectively. Thus, when the weight selection signals are (0,0), (0,1), (1,0), or (1,1), the probability of the signal at the 4-to-1 multiplexer's output182being 1 is ½, ¼, ⅛, or 1/16, respectively.

The weight channel circuit142depicted inFIG. 3also outputs a single bit control signal that is received by one input186of the XOR140. The other input184of the XOR receives the signal output from the 4-to-1 multiplexer138. The probability of the signal output from the XOR gate is dependent upon the signal output from the 4-to-1 multiplexer in addition to the single bit control signal. When the single bit control signal is 0, and selection line signals are (0,0), (0,1), (1,0), or (1,1), the probability of the signal at the XOR. gate's output190being 1 is ½, ¼, ⅛, or 1/16, respectively. In addition, when the single bit control signal is 1, and selection line signals are (0,0), (0,1), (1,0), or (1,1), the probability of the signal at the XOR gate's output being 1 is ½, ¾, ⅞, or 15/16, respectively.

FIG. 4is a block diagram of a circuit configuration200included in a PWR14that is an embodiment of the present invention. Similar to the circuit configuration ofFIG. 3, the circuit configuration ofFIG. 4includes a first AND gate202, a second AND gate204, a third AND gate206, a 4-to-1 multiplexer208, an XOR gate210, and a weight channel circuit212. In addition, the circuit configuration depicted inFIG. 4includes a first 2-to-1 multiplexer214, a second 2-to-1 multiplexer216, a third 2-to-1 multiplexer218, a fourth 2-to-1 multiplexer220, and a control circuit222.

The 4-to-1 multiplexer208is also referred to as the first multiplexer, and the first, second, and third 2-to-1 multiplexers214,216, and218, respectively, are also cumulatively referred to as at least one other multiplexer. The fourth 2-to-1 multiplexer220is also referred to as the output multiplexer. The XOR gate210is also referred to as the output logic gate, and the first, second, and third AND gates202,204, and206, respectively, are also collectively referred to as the another logic gate.

The first, second, third, and fourth 2-to-1 multiplexers214–220, and the control circuit222may be selected from any of various types of electronic components as desired. In alternative embodiments, the components included in the circuit configuration200ofFIG. 4are housed within a single electronic chip (not shown).

A first output224of the LFSR12is coupled to the 4-to-1 multiplexer's first input226and an input228of the first AND gate202. The LFSR's second output230is coupled to the other input232of the first. AND gate202and the first 2-to-1 multiplexer's second input234. The first AND gate's output236is coupled to the first 2-to-1 multiplexer's first input238. The first 2-to-1 multiplexer's output240is coupled to 4-to-1 multiplexer's second input242and one input244of the second AND gate204. The LFSR's third output246is coupled to the other input248of the second AND gate204and the second 2-to-1 multiplexer's second input250. The second AND gate's output252is coupled to the second 2-to-1 multiplexer's first input254. The output256of the second 2-to-1 multiplexer216is coupled to the 4-to-1 multiplexer's third input258and one input260of the third AND gate206. The LFSR's fourth output262is coupled to the other input264of the third AND gate206and the third 2-to-1 multiplexer's second input266. The third AND gate's output268is coupled to the third 2-to-1 multiplexer's first input270. The third 2-to-1 multiplexer's output272is coupled to the 4-to-1 multiplexer's fourth input274. An output276of the control circuit222is coupled to the first 2-to-1 multiplexer's selection line278, the second 2-to-1 multiplexer's selection line280, and the third 2-to-1 multiplexer's selection line282.

While the embodiment200depicted inFIG. 4illustrates only one control circuit222, there may be additional embodiments (not shown) that include more than one control circuit. In these additional embodiments, the each control circuit may be coupled to the selection line of one or more 2-to-1 multiplexers. Thus, there may be embodiments in which the signal on the selection lines is different for the 2-to-1 multiplexers.

The 4-to-1 multiplexer's two selection lines (only one shown)284are coupled to selection outputs (only one shown)286of the weight channel circuit212. The 4-to-1 multiplexer's output288is coupled to one input290of the XOR gate210. The XOR gate's other input296is coupled to another output294of the weight channel circuit. The XOR gate's output296is coupled to the fourth 2-to-1 multiplexer's first input298. An external input300is coupled to the fourth 2-to-1 multiplexer's second input302. An additional output304of the weight channel circuit is coupled to the fourth 2-to-1 multiplexer's selection line306. Referring additionally toFIG. 1, the fourth 2-to-1 multiplexer's output308is coupled to an input28of the circuit under test16.

In operation, the circuit configuration200depicted inFIG. 4receives pseudo-random four-bit data patterns from the LFSR12. The probability of the signals received at the 4-to-1 multiplexer's inputs226,242,258, and274being 1 is dependent upon the selection signal on the selection lines278,280, and282of the first, second, and third 2-to-1 multiplexers214,216, and218, respectively. In the case where the selection signals on the selection lines of the first, second, and third 2-to-1 multiplexers are 0, the outputs236,252, and268of the first, second, and third AND gates202,204, and206, respectively, are coupled to the second, third, and fourth inputs242,258, and274, respectively, of the 4-to-1 multiplexer208. Thus, the probability of the signal output from the 4-to-1 multiplexer and also the XOR gate296are the same as those of the circuit configuration130depicted inFIG. 3.

The circuit configuration200ofFIG. 4has the added feature that the signal output from the fourth 2-to-1 multiplexer220is dependent upon the output selection signal output from the weight channel circuit212and input to the fourth 2-to-1 multiplexer's selection line306. When the output selection signal input to the fourth 2-to-1 multiplexer's selection line is 0, the signal output from the XOR gate210is coupled through the fourth 2-to-1 multiplexer and output from the fourth 2-to-1 multiplexer. When the output selection signal input to the fourth 2-to-1 multiplexer's selection line is 1, the signal on the external input300is coupled through the fourth 2-to-1 multiplexer and output from the fourth 2-to-1 multiplexer.

In the case where the signals on the selection lines278,280, and282of the first, second, and third 2-to-1 multiplexers214,216, and218, respectively, are 1, the second, third, and fourth bits output from the LFSR12respectively are coupled to the second, third, and fourth inputs242,258, and274, respectively, of the 4-to-1 multiplexer208through the first, second, and third 2-to-1 multiplexers214,216, and281, respectively. As discussed above, the probability of each of the four bits output from the LFSR being a 0 or a 1 is ½. Thus, the probability that the first, second, third, and fourth bits output from the LFSR and received at the 4-to-1 multiplexer's first, second, third, and fourth input226,242,258, and274, respectively, is 1 is ½. Accordingly, regardless of the state of the signal input to the 4-to-1 multiplexer's selection lines (one shown)284, the probability of signal output from the 4-to-1 multiplexer being 1 is ½. Also, the probability of the signal output from the XOR gate210being 1 is ½regardless of the signal output from the weight channel circuit's another output294.

As discussed above, the signal output from the fourth 2-to-1 multiplexer's output308in the circuit configuration200ofFIG. 4is dependent upon the signal output from the weight channel circuit's additional output304and input to the fourth 2-to-1 multiplexer's selection line306. In the case where the signal input to the fourth 2-to-1 multiplexer's selection line is 0, the signal output from the XOR gate210is coupled through the fourth 2-to-1 multiplexer220and output from the fourth 2-to-1 multiplexer's output. Thus, when the signal input to the fourth 2-to-1 multiplexer's selection line is 0, the probability of the signal output from the XOR gate being 1 is ½. In contrast, when the signal input to the fourth 2-to-1 multiplexer's selection line is 1, the signal output from the XOR gate is the signal present on external input300and the probability of the signal output from the fourth 2-to-1 multiplexer being 1 is dependent upon the probability of the signal present on the external input being 1.

Thus, the probability of the signal output from the fourth 2-to-1 multiplexer220being 1 is dependent upon the signals output from the weight channel circuit's additional output304as well as the signals output from the weight channel circuit's selection and another outputs286and294, respectively, and the signal input to the selection lines278,280, and282of the first, second, and third 2-to-1 multiplexer214,216, and218, respectively. Therefore, the circuit configuration200depicted inFIG. 4advantageously offers an output signal that has a selectable probability of being 1. The present invention offers greater flexibility in generating test signals to be transferred across the I/O channels to the electronic circuit under test16, thus, increasing the fault coverage of the electronic circuit under test.

In additional embodiments, the circuit configuration200depicted inFIG. 4can be extended such that the 4-to-1 multiplexer208is an 2n-to-1 multiplexer, where n is an integer greater than one, and the circuit configuration includes 2n-1 AND gates and 2n-1 2-to-1 multiplexers, and similar coupling between the control circuit212, 2n-1 AND gates, 2n-1 2-to-1 multiplexers and the LFSR12. In these additional embodiments, the circuit configuration couples to 2noutputs of the LFSR and one input of the circuit under test16.

Also, the circuit configuration200ofFIG. 4is advantageous in that a computer (not shown) can control the control circuit212, the weight channel circuit212, and the external input300. Because the circuit configuration is computer-controllable, the patterns generated by the circuit configuration and supplied to the electronic circuit under test16can be modified to satisfy test requirements.

Moreover, to those skilled in the various arts, the invention itself herein will suggest solutions to other tasks and adaptations for other applications. The present embodiments must therefore be considered in all respects as illustrative and not restrictive. The scope of the invention is not limited to those embodiments, but must be determined instead by the appended claims, along with the full scope of equivalents to which those claims are legally entitled.