Substrate inspection apparatus

There is provided a substrate inspection apparatus capable of inspecting the electrical characteristics of a packaged semiconductor device in a mounting environment. A prober includes a test box, a probe card and a package inspection card. A packaged device is attached to the package inspection card. A test board of the test box and a card board of the package inspection card reproduce the mounting environment in which a wafer-level system-level test is performed.

TECHNICAL FIELD

The present disclosure relates to a substrate inspection apparatus that inspects a semiconductor device formed on a substrate without detaching the semiconductor device from the substrate.

BACKGROUND

A prober is known as a substrate inspection apparatus for inspecting electrical characteristics of semiconductor devices, such as power devices and memories, formed on a semiconductor wafer (hereinafter simply referred to as a “wafer”) as a substrate.

The prober includes a probe card having a number of pin-like probes, a stage which freely moves a wafer placed on the stage vertically and horizontally, and an IC tester. Each probe of the probe card is brought into contact with an electrode pad or a solder bump formed on the semiconductor device, and a signal obtained from the semiconductor device is transmitted to the IC tester to inspect the electrical characteristics of the semiconductor device (see, e.g., Patent Document 1).

The IC tester determines the acceptability of the electrical characteristics and functions of the semiconductor device based on the transmitted signal. The IC tester has a circuit configuration different from a circuit configuration in which a packaged semiconductor device (hereinafter referred to as a “packaged device”) is mounted, for example, the circuit configuration of a motherboard or a function expansion card. Because of this, the IC tester fails to determine the acceptability of the electrical characteristics in the mounted state. As a result, there is a problem that defects of the semiconductor device which have not been detected by the IC tester are found when the packaged device is mounted on the motherboard or the like. Particularly, in recent years, with the complication and speeding up of semiconductor devices, a test pattern in the IC tester becomes larger in size, and a fine control of the test timing is required. This makes the above-mentioned problem conspicuous.

Therefore, in order to guarantee the quality of a semiconductor device, there has been proposed a technique for installing, in place of the IC tester, an inspection circuit for reproducing a circuit configuration in which a packaged device is mounted on a probe card, for example, a circuit configuration of a motherboard, and using the probe card to measure the electrical characteristics of the semiconductor device without detaching the semiconductor device from a wafer in an environment in which the packaged device is mounted on the mother board (hereinafter referred to as a “mounting environment”) is reproduced (see, e.g., Patent Document 2). The semiconductor device inspection performed in such a mounting environment is referred to as a wafer-level system-level test.

Meanwhile, after packaging and shipping semiconductor devices that passed the wafer-level system-level test, the packaged devices may malfunction on the market. In this case, in order to pursue a cause of the malfunction, it is necessary to inspect the electrical characteristics of the packaged devices in a mounting environment where the wafer-level system-level test is performed.

Patent Documents

The probe card of the prober which performs the wafer-level system-level test is brought into electrical contact with the electrode pad or the solder bump of the semiconductor device by using each probe. However, the packaged device does not include an electrode pad and a solder bump. Therefore, there is a problem that the use of the probe card fails to inspect the electrical characteristics of the packaged device in the mounting environment.

SUMMARY

The present disclosure provides some embodiments of a substrate inspection apparatus capable of inspecting electrical characteristics of a packaged semiconductor device in a mounting environment.

According to one embodiment of the present disclosure, there is provided a substrate inspection apparatus including: a probe card having a plurality of probes configured to make contact with each electrode of a semiconductor device formed on a substrate; a test box electrically connected to the probe card, wherein the test box includes an inspection board on which a circuit is formed, and the probe card and the inspection board are configured to reproduce a mounting environment of the semiconductor device which is cut out from the substrate and is packaged; and a package inspection card to which the packaged semiconductor device is attached, wherein the test box is electrically connected to the package inspection card, wherein the package inspection card includes another inspection board on which a circuit is formed, and wherein the inspection board and the another inspection board reproduce the mounting environment.

According to the present disclosure, an inspection board of a test box and another inspection board of a package inspection card to which a packaged semiconductor device is attached reproduce a mounting environment of the packaged semiconductor device detached from a substrate, namely a mounting environment in which a wafer-level system-level test is performed. Therefore, by attaching the packaged semiconductor device to the package inspection card, it is possible to inspect the electrical characteristics of the packaged semiconductor device in the mounting environment in which the wafer-level system-level test is performed.

DETAILED DESCRIPTION

FIG. 1is a perspective view schematically illustrating the configuration of a prober as a substrate inspection apparatus according to an embodiment, andFIG. 2is a front view thereof.FIG. 2is drawn as a partial cross-sectional view, showing a main body12, a loader13and components included in a test box14, which will be described later.

InFIGS. 1 and 2, a prober10includes the main body12incorporating a stage11on which a wafer W is placed, the loader13disposed adjacent to the main body12, and the test box14disposed so as to cover the main body12, and inspects electrical characteristics of a semiconductor device which is a DUT (Device Under Test) formed on the wafer W. The main body12has a hollowed housing shape. In the interior of the main body12, the stage11and a probe card15arranged to face the stage11are disposed. The probe card15is disposed to face the wafer W. The probe card15includes a plate-shaped card board16and a probe head17disposed below the card board16to face the wafer W. As illustrated inFIG. 3, the probe head17includes a number of needle-like probes18which correspond to electrode pads and solder bumps of a semiconductor device of the wafer W.

The wafer W is fixed to the stage11so as not to shift relative to the stage11. The stage11is movable in the horizontal direction and the vertical direction. The relative position of the probe card15and the wafer W is adjusted to bring the electrode pads and the solder bumps of the semiconductor device into contact with the respective probes18of the probe head17. The loader13takes the wafer W, on which the semiconductor device is formed, out of a FOUP (not shown) which is a transfer container, places the wafer W on the stage11inside the main body12, removes the wafer W subjected to the wafer-level system-level test from the stage11and accommodates the wafer W into the FOUP.

A card-side inspection circuit20for reproducing a portion of a circuit configuration in which a packaged semiconductor device (packaged device) cut out from the wafer W is mounted, for example, a circuit configuration of the mother board, is formed on the card board16of the probe card15(seeFIG. 3). The card-side inspection circuit20is connected to the probe head17. When the respective probes18of the probe head17come into contact with the electrode pads or the solder bumps of the semiconductor device of the wafer W, the respective probes18supply electric power to the power supply of the semiconductor device or deliver a signal from the semiconductor device to the card-side inspection circuit20.

The test box14includes a harness19which is a wiring, a test control unit and a recording unit (both not shown), and a test board22(inspection board) on which a box-side inspection circuit21for reproducing a portion of the circuit configuration of the mother board is formed. The harness19connects the test board22of the test box14and the card board16of the probe card15, and delivers a signal from the card-side inspection circuit20to the box-side inspection circuit21. In the prober10, by replacing the test board22of the test box14, a portion of the circuit configuration of plural types of mother boards may be reproduced.

The loader13incorporates a base unit23including a power supply, a controller and a simple measurement module. The base unit23is connected to the box-side inspection circuit21by a wiring24. The controller instructs the box-side inspection circuit21to start inspection of the electric characteristics of the semiconductor device. In the prober10, as described above, each of the card-side inspection circuit20formed on the card board16and the box-side inspection circuit21formed on the test board22reproduces a portion of the circuit configuration of the mother board. The base unit23reproduces a circuit configuration common to various types of mother boards. Therefore, the entire mother board on which the packaged device is mounted is reproduced in cooperation between the card board16, the test board22and the base unit23. In other words, the card board16, the test board22and the base unit23reproduce a mounting environment which is the environment in which the packaged device is mounted on the mother board.

In the prober10, when the electrical characteristics of the semiconductor device is inspected, for example, the inspection control unit of the box-side inspection circuit21transmits data to the card-side inspection circuit20, and determines whether or not the transmitted data has been correctly processed by the card-side inspection circuit20connected to the semiconductor device, based on an electric signal provided from the card-side inspection circuit20. Further, in the prober10, the test board22of the test box14and the card board16of the probe card15are connected to each other by the harness19. A bottom opening25having a size corresponding to the card board16is formed in the bottom of the test box14, and the test board22and the card board16face each other. Thus, the test board22and the card board16can be disposed close to each other, thereby making the harness19as short as possible. As a result, in the wafer-level system-level test, it is possible to minimize the influence of the length of the harness19, for example, the influence of a change in wiring capacitance. This makes it possible to perform the wafer-level system-level test in a mounting environment extremely similar to the operating environment of a computer as the actual machine having a function expansion card and a mother board.

However, after packaging and shipping semiconductor devices that passed the wafer-level system-level test, the packaged device may malfunction on the market. In this case, in order to verify the reliability of the wafer-level system-level test, it is necessary to determine whether the malfunction can be found in the wafer-level system-level test or whether the malfunction is caused by packaging the semiconductor devices after being subjected to the wafer-level system-level test or by an environmental load or an external force in the market. The determination as to whether the malfunction can be found in the wafer-level system-level test is made based on whether the malfunction is reproduced by inspecting the electrical characteristics of the packaged devices that triggered the malfunction in the mounting environment in which the wafer-level system-level test is performed. Specifically, unless the malfunction of the packaged devices in the mounting environment is reproduced, it is determined that the malfunction cannot be found in the wafer-level system-level test. On the other hand, if the malfunction of the packaged devices in the mounting environment is reproduced, it is determined that the malfunction is caused by packaging the semiconductor devices after being subjected to the wafer-level system-level test or by an environmental load or an external force in the market.

In addition, if it is determined that the malfunction cannot be found in the wafer-level system-level test, it is necessary to change the contents of implementation of the wafer-level system-level test. However, when a specific semiconductor device formed on the wafer is used to verify the wafer-level system-level test after the change of the contents of implementation, many other semiconductor devices formed on the wafer may be damaged. Therefore, it is much cheaper to carry out the verification using a packaged device rather than the semiconductor devices formed on the wafer. Further, since the packaged devices can be more easily handled than the wafer, it is easier to carry out the verification using the packaged device. In the case where the probe card15and the semiconductor device formed on the wafer are used for verification, each probe18comes in contact with the electrode pad or the solder bump of the semiconductor device. However, such contact may cause deterioration of the semiconductor device. Specifically, a needle trace remains on the electrode pad or the solder bump of the semiconductor device. Particularly, when the contact is repeated, the needle trace becomes deeper, which may cause a problem when the packaged device is manufactured from the semiconductor device. Therefore, from the viewpoint of preventing the deterioration of the semiconductor device, it is preferable to carry out the verification using the packaged device rather than the wafer. That is to say, there is a strong need to inspect the electrical characteristics of the packaged device in the mounting environment where the wafer-level system-level test is performed.

On the other hand, the above-described probe card15makes electrical contact with the electrode pad and solder bump of the semiconductor device of the wafer W using each probe18, but the packaged device has no electrode pad and no solder bump. Therefore, the probe card15cannot be used to inspect the electrical characteristics of the packaged device in the mounting environment in which the wafer-level system-level test is performed. In the present embodiment, to cope with this problem, the prober10further includes a card on which a packaged device can be mounted for inspecting the electrical characteristics of the packaged device (hereinafter referred to as a “package inspection card”).

FIG. 4is a front view schematically illustrating the configuration of a package inspection card included in the prober ofFIG. 1.

InFIG. 4, a package inspection card26includes a plate-like card board27(another inspection board) and a socket28disposed on an upper surface of the card board27inFIG. 4. A card-side inspection circuit29for reproducing a portion of the circuit configuration of a mother board is formed on a lower surface of the card board27inFIG. 4. A packaged device30is attached to a leading end of the socket28and is coupled to the card-side inspection circuit29via the socket28. The socket28supplies power to the packaged device30or delivers a signal provided from the packaged device30to the card-side inspection circuit29.

FIG. 5is a front view for explaining a state in which the package inspection card26inFIG. 4is attached to the prober inFIG. 1.FIG. 5is also partially drawn as a sectional view.

InFIG. 5, the test box14includes a ceiling port31formed in a ceiling surface so as to face the bottom port25, and a card holder32installed in the vicinity of the ceiling port31inside the test box14. The ceiling port31has a size corresponding to the card board27and is closed by a ceiling plate33(seeFIG. 2) when performing the wafer-level system-level test.

When inspecting the electrical characteristics of the packaged device30, the package inspection card26is loaded into the test box14via the ceiling port31and is held by the card holder32. At this time, the card holder32holds the package inspection card26so that the socket28is oriented towards the side opposite the probe card15. Further, the card holder32holds the package inspection card26so that the package inspection card26faces the probe card15through the test board22. Here, since one end of the harness19is connected to the test board22, the package inspection card26faces the probe card15through the harness19. When the package inspection card26is held by the card holder32, the harness19connects the test board22of the test box14and the card board27of the package inspection card26, and delivers a signal provided from the card-side inspection circuit29to the box-side inspection circuit21. As will be described later, the card holder32holds the package inspection card26so that the package inspection card26is rotatable around one end thereof.

In the package inspection card26, as described above, the card-side inspection circuit29formed on the card board27reproduces a portion of the circuit configuration of the mother board, while the box-side inspection circuit21formed on the test board22reproduces a portion of the circuit configuration of the mother board and the base unit23reproduces a circuit configuration common to various types of mother boards. Therefore, the entire motherboard on which the packaged device is mounted is reproduced in cooperation between the card board27, the test board22and the base unit23. That is to say, the card board27, the test board22and the base unit23reproduce the mounting environment in which the wafer-level system-level test is performed.

In the prober10, when the electrical characteristics of the packaged device30are inspected, for example, the inspection control unit of the box-side inspection circuit21transmits data to the card-side inspection circuit29, and determines whether or not the transmitted data has been correctly processed by the card-side inspection circuit29connected to the packaged device30based on an electric signal provided from the card-side inspection circuit29.

FIG. 6is a flow chart illustrating a method of attaching a package inspection card to a test box, andFIGS. 7A and 7Bare process diagrams for explaining a connection between a card board of the package inspection card and a test board of the test box with the harness in the attaching method ofFIG. 6. InFIGS. 7A to 7B, each process is drawn with a sectional view looking at the test box14from the right side.

First, the ceiling plate33is removed from the test box14to open the interior of the test box14(step S71). At this time, the harness19connecting the test board22and the card board16of the probe card15is exposed.

Thereafter, the other end of the harness19is detached from the card board16(step S72). Subsequently, the package inspection card26is loaded into the test box14via the ceiling port31and is placed on the card holder32(step S73). The package inspection card26is held by the card holder32(step S74). At this time, the card holder32holds the package inspection card26so that the package inspection card26is rotatable around one end thereof.

Subsequently, as illustrated inFIG. 7A, the package inspection card26is rotated around its one end so that the other end of the package inspection card26is moved upward inFIG. 7A(step S75). Thus, the interior of the test box14is again opened to expose the harness19. Thereafter, the other end of the harness19is connected to the card board27of the package inspection card26(step S76).

Subsequently, as illustrated inFIG. 7B, the package inspection card26is rotated around its one end so that the other end of the package inspection card26is moved downward inFIG. 7B(step S77). The interior of the test box14is closed and the other end of the package inspection card26is held by the card holder32. In this way, the present method is ended.

As described above, according to the prober10, the test board22of the test box14and the card board27of the package inspection card26reproduce the mounting environment in which the wafer-level system-level test is performed. Therefore, by attaching the packaged device30to the package inspection card26via the socket28, it is possible to inspect the electrical characteristics of the packaged device30in the mounting environment in which the wafer-level system-level test is performed. As a result, the reliability of the wafer-level system-level test can be easily verified. Further, by using the packaged device rather than a dummy device or the like when verifying the wafer-level system-level test after changing the contents of implementation in the mounting environment in which the wafer-level system-level test is performed, it is possible to improve the reliability of the verification.

In the prober10described above, when the packaged device30is attached to the package inspection card26, the test board22of the test box14is connected to the card board27of the package inspection card26by the harness19used for connection with the card board16of the probe card15. As a result, a difference between the mounting environment reproduced by the card board16of the probe card15and the test board22and the mounting environment reproduced by the card board27of the package inspection card26and the test board22corresponds to a difference in configuration between the card board16and the test board22. It is therefore possible to make the two mounting environments almost the same.

Further, in the prober10described above, since the package inspection card26faces the probe card15through the harness19, the harness19easily reaches both the card board16of the probe card15and the card board27of the package inspection card26. That is to say, it is possible to easily connect the same harness19to both the card board16and the card board27.

Furthermore, in the prober10described above, the card holder32holds the package inspection card26so that the package inspection card26is rotatable around its one end. Thus, by rotating the package inspection card26, the interior of the test box14is opened to easily expose the harness19. This makes it possible to improve the workability of attachment/detachment of the harness19to/from the card board16of the probe card15and the workability of attachment/detachment of the harness19to/from the card board27of the package inspection card26.

In the prober10described above, since the card holder32holds the package inspection card26so that the socket28is oriented towards the opposite side of the probe card15, the package inspection card26can be attached to the test box14without interference of the socket28with the probe card15and the test board22. In addition, as the socket28is oriented towards the opposite side of the probe card15, the packaged device30attached to the leading end of the socket28is exposed from the test box14. This facilitates handling of the packaged device30by an operator, for example, a fine position adjustment performed to improve the contact of the packaged device30.

Furthermore, in the prober10described above, since the card holder32is installed inside the test box14, the package inspection card26held by the card holder32can be disposed close to the test board22. This eliminates a need to lengthen the harness19. As a result, in the inspection of the electrical characteristics of the packaged device30, it is possible to minimize the influence of the length of the harness19, for example, the influence of a change in wiring capacitance.

Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above embodiments.

This application claims priority based on Japanese Patent Application No. 2016-063373 filed on Mar. 28, 2016, the entire contents of which are incorporated herein by reference.

EXPLANATION OF REFERENCE NUMERALS