Thin film transistor array panel and method for manufacturing the same

A thin film transistor array panel according to the present invention includes: a gate line formed on a substrate and including a gate electrode; a gate insulating layer formed on the gate electrode; a mold layer formed on the gate insulating layer and having an opening overlapping the gate electrode; a semiconductor layer filled in the opening; a data line formed on the mold layer and including a source electrode contacted with the semiconductor layer; a drain electrode contacted with the semiconductor layer on the mold layer and facing the source electrode; a passivation layer formed on the data line and the drain electrode; and a pixel electrode formed on the passivation layer and connected to the drain electrode, wherein the passivation layer, the source electrode, and the drain electrode have at least one through-hole connected to the opening.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to and the benefit of Korean Patent Application No. 10-2008-0092764 filed in the Korean Intellectual Property Office on Sep. 22, 2008, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a thin film transistor array panel and a manufacturing method thereof.

2. Description of the Related Art

Generally, a flat panel display, such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, and an electrophoretic display, includes a plurality of pairs of field generating electrodes and an electro-optical activation layer disposed therebetween. The liquid crystal display includes a liquid crystal layer as the electro-optical activation layer, and the organic light emitting diode display includes an organic emission layer as the electro-optical activation layer.

One of the pair of field generating electrodes is generally connected to a switching element so as to receive an electrical signal, and the electro-optical activation layer converts the electrical signal to an optical signal to thereby display images.

In the flat panel display, a thin film transistor (TFT), which includes a gate electrode, a source electrode, a drain electrode, and a semiconductor, is used as the switching element, and a gate line transmitting a scanning signal for controlling the thin film transistor and a data line transmitting a signal applied to a pixel electrode are provided to the flat panel display.

In the field of thin film transistors, research including a semiconductor formed through a solution process is actively being undertaken.

A semiconductor can be manufactured by a solution process, so it can be easily applied to a large flat panel display limited by a deposition process.

However, unlike a conventional deposition process, the solution process requires an additional process for forming a bank for sealing the solution.

The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that is not prior art known to a person of ordinary skill in the art.

SUMMARY OF THE INVENTION

Accordingly, the present invention provides a thin film transistor array panel and a manufacturing method thereof including an organic semiconductor while using the conventional process.

A thin film transistor array panel according to an exemplary embodiment of the present invention includes: a gate line formed on a substrate including a gate electrode; a gate insulating layer formed on the gate electrode; a mold layer formed on the gate insulating layer and having an opening overlapping the gate electrode; a semiconductor layer filling in the opening; a data line formed on the mold layer including a source electrode which is contact with the semiconductor; a drain electrode contacting the semiconductor layer on the mold layer and facing the source electrode; a passivation layer formed on the data line and the drain electrode; and a pixel electrode formed on the passivation layer and connected to the drain electrode, wherein the passivation layer, the source electrode, and the drain electrode have at least one through-hole connected to the opening.

An overcoat covering the semiconductor may be formed in the through-hole.

The through-hole may include a first through-hole formed in the passivation layer and the source electrode, and a second through-hole formed in the passivation layer and the drain electrode.

The boundaries of the first through-hole and the second through-hole may be disposed at the boundary of the opening.

A first distance as the shortest distance from the boundary of the opening to the first through-hole or a second distance as the shortest distance from the boundary of the opening to the second through-hole may be more than 3 μm.

The distance between the neighboring first through-holes or the distance between the neighboring second through-holes may be more than twice the first distance or the second distance.

The distance between the boundary of the first through-hole nearest to the channel between the source electrode and the drain electrode, and the boundary of the second through-hole nearest to the channel, may be less than twice the first distance or the second distance.

The semiconductor layer comprises an organic semiconductor.

The gate insulating layer and the mold layer may have the same composition but different densities, and the gate insulating layer may be denser and more solid than the mold layer.

The mold layer may be made of a metal having an etch rate that is different from the etch rate of data line and drain electrode.

A manufacturing method of a thin film transistor array panel includes: forming a gate line including a gate electrode on a substrate; forming a gate insulating layer, a buffer layer, and a metal layer on the gate line; patterning the metal layer and the buffer layer by photolithography to form a data line including a source electrode and a drain electrode, and a mold layer pattern; forming a passivation layer having a contact hole exposing the drain electrode on the data line and the drain electrode; forming a transparent conductive layer connected to the drain electrode through the contact hole on the passivation layer; patterning the transparent conductive layer, the passivation layer, the source electrode and the drain electrode by photolithography to form a pixel electrode and a through-hole exposing the mold layer pattern; etching the exposed mold layer pattern through the through-hole to form a mold layer having an opening connected to the through-hole; and filling a semiconductor in the opening through the through-hole.

The gate insulating layer and the buffer layer may be made of materials having different etch rate.

The gate insulating layer and the buffer layer may have the same composition but different densities, and the gate insulating layer may be formed at a higher temperature than the buffer layer.

The gate insulating layer may be formed at a temperature of more than 220° C., and the buffer layer may be formed at a temperature of less than 130° C.

In the forming of the mold layer, the mold layer pattern may be over-etched after exposing the gate insulating layer, and the neighboring first through-hole or the neighboring second through-hole may be connected by the opening through the over-etch.

The through-hole may include a first through-hole passing through the source electrode and a second through-hole passing through the drain electrode.

The patterning of the transparent conductive layer, the passivation layer, the source electrode, and the drain electrode by photolithography to form the pixel electrode and the through-hole exposing the mold layer pattern includes forming a first photosensitive film pattern including a first portion and a second portion thicker the first portion on the transparent conductive layer, etching the transparent conductive layer, the passivation layer, the source electrode, and the drain electrode by using the first photosensitive film pattern as a mask to form the through-hole, developing the first photosensitive film pattern to remove the first portion, and etching the transparent conductive layer to form the pixel electrode.

The first photosensitive film pattern may expose the transparent conductive layer corresponding to the through-hole, and the second portion may be disposed corresponding to the pixel electrode.

A gate contact assistant connected to an end portion of the gate line and a data contact assistant connected to an end portion of the data line may be formed along with the pixel electrode.

The patterning of the metal layer and the buffer layer by photolithography to form a data line including a source electrode and a drain electrode, and a mold layer pattern, includes forming a second photosensitive film pattern including a third portion and a fourth portion thicker than the third portion on the metal layer, etching the metal layer and the buffer layer by using the second photosensitive film pattern as a mask to form an incomplete data pattern and the mold layer pattern, developing the third photosensitive film pattern to remove the third portion, and etching the incomplete data pattern that is exposed by the removal of the third portion to form the source electrode and the drain electrode.

The filling of the organic semiconductor in the opening may be executed by Inkjet printing.

After forming the pixel electrode, the organic semiconductor is finally formed such that the organic semiconductor is prevented from being damaged, thereby increasing the efficiency of the thin film transistor.

DESCRIPTION OF REFERENCE NUMERALS INDICATING PRIMARY ELEMENTS IN THE DRAWINGS

DETAILED DESCRIPTION OF THE EMBODIMENTS

A thin film transistor array panel according to an exemplary embodiment of the present invention will be described with reference toFIG. 1 to 3.

FIG. 1is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention,FIG. 2is a cross-sectional view of the thin film transistor array panel shown inFIG. 1taken along the line II-II, andFIG. 3is an enlarged cross-sectional view of a portion of the thin film transistor array panel shown inFIG. 1.

A gate line121is formed on an insulation substrate110made of transparent glass, silicone, or plastic.

The gate lines121transmit gate signals and substantially extend in a first direction. Each gate line121includes a plurality of gate electrodes124extending from the gate line121, and an end portion129having a large area for contact with another layer or an external driving circuit.

A gate insulating layer140is formed on the gate line121. The gate insulating layer140is made of silicon oxide or silicon nitride.

A mold layer400is formed on the gate insulating layer140, and a data line171and a drain electrode175are formed on the mold layer400. The mold layer and the gate insulating layer may have the same composition but different densities.

The mold layer400has a plurality of openings40extending to the gate insulating layer140. The mold layer400may be made of a photosensitive organic material, or of silicon oxide or silicon nitride.

The data line171transmits data signals and extends in a second direction that is substantially perpendicular to the first direction. Each data line171includes a plurality of source electrodes173extending toward the gate electrodes124, and an end portion179having a large area for contact with another layer or an external driving circuit.

The data line171and the drain electrode175may be made of a metal having low resistance such as chromium (Cr), molybdenum (Mo), tantalum (Ta), and titanium (Ti), and they may prevent a signal delay as low resistance wiring.

The source electrode173and the drain electrode175directly contact an organic semiconductor154that will be described, such that it is preferable that the source electrode173and the drain electrode175are made of a conductive material. The conductive material is selected to reduce the work function difference between the source electrode173and the organic semiconductor, and also between the drain electrode175, and the organic semiconductor. The source electrode173and the drain electrode175may simultaneously have the function of an ohmic contact reducing the Schottky barrier between the organic semiconductor and the electrodes in this case. A passivation layer180is formed on the data line171and the drain electrode175.

The passivation layer180and source electrode173have a plurality of first through-holes183aconnected to the openings40, and the passivation layer180and the drain electrode175have a plurality of second through-holes183bconnected to the openings40. Also, the passivation layer180has contact-holes185and182exposing the drain electrode175and the end portion179, and the passivation layer180and the gate insulating layer140have a contact hole181exposing the end portion129.

The boundaries of the openings40are preferably within the boundaries of the gate electrodes124, the boundaries of the first and second through-holes183aand183bare disposed within the boundary of the opening40.

For convenience of description, the portion between the source electrode173and the drain electrode175is referred to as a channel.

The outer boundaries of the first and second through-holes183aand183bthat are disposed further away from the channel are at a distance Al from the boundary of the opening40. Therefore an undercut is formed on the mold layer400under the source electrode173and the drain electrode175, as shown in the cross-section ofFIG. 2.

The distance between the two neighboring first through-holes183a, or the two neighboring second through-holes183b, is less than twice the distance Al. Also, the distance A2between the channel, and the first and second neighboring through-holes183aand183b, is less than twice the distance A1.

A pixel electrode191and contact assistants81and82are formed on the passivation layer180. The pixel electrode191is connected to the drain electrode175through the contact hole185and receives the data voltages from the drain electrode175. The contact assistants81and82are respectively connected to the exposed end portions129and179of the gate lines121and the data lines171through the contact holes181and182, and protect the exposed end portions129and179of the gate lines121and the data lines171and complement the adhesion between the exposed portions and external devices such as a driving integrated circuit.

The opening40, and the first and second through-holes183aand183b, are filled with the organic semiconductor layer154.

The organic semiconductor layer154may include a high molecular weight compound and a low molecular weight compound that are dissolved in an aqueous solution or an organic solvent and formed by an Inkjet printing method. However, the organic semiconductor154may be formed by another solution process such as spin coating or slit coating, or a deposition process.

The organic semiconductor layer154may include a material selected from the group consisting of polythienylenevinylene, poly3-hexylthiophene, polythiophene, phthalocyanine, metalized phthalocyanine, and halogenation derivatives thereof. The organic semiconductor layer154may include one selected from the group consisting of perylenetetracarboxylic dianhydride (PTCDA), naphthalenetetracarboxylic dianhydride (NTCDA), and imide derivatives thereof. The organic semiconductor layer154may include a derivative including perylene and coronene, and substitution groups thereof.

A gate electrode124, a source electrode173, and a drain electrode175form a thin film transistor (TFT) along with the organic semiconductor layer154, and the channel of the thin film transistor is formed in the organic semiconductor layer154between the source electrode173and the drain electrode175.

The pixel electrode191and the contact assistants81and82may be made of a transparent conductive material or a reflective metal.

Next, a manufacturing method of the thin film transistor shown inFIG. 1andFIG. 2will be described with reference toFIG. 4 to 7as well asFIG. 1 to 3.

FIG. 4toFIG. 7are cross-sectional views sequentially showing steps in the manufacturing method of a thin film transistor array panel according to the present invention.

First, as shown inFIG. 4, a metal layer is deposited on a substrate110, and patterned by photolithography to form a gate line121including gate electrodes124.

Then, a gate insulating layer140made of silicon oxide or silicon nitride is formed on the substrate110and the gate electrodes124.

A buffer layer made of an insulating material such as an organic material or silicon oxide is deposited on the gate insulating layer140. The buffer layer is formed of a material having a different etch rate from the etch rate of the gate insulating layer140. For example, the formation temperature of the silicon nitride layer may be varied to enable the etch selectivity difference. That is, the gate insulating layer is deposited at a temperature higher than 220° C. such that the film becomes dense thereby forming a rigid layer, and the buffer layer is deposited at a temperature of less than 130° C. such that the film is not denser than the gate insulating layer, thereby forming a soft layer.

Next, a conductive metal is deposited on the buffer layer to form a data metal layer.

Next, a photosensitive film pattern, having different thicknesses depending on positions, is formed on the data metal layer, and the data metal layer is etched by using the photosensitive film pattern as a mask to form a data line171, a source electrode173and a drain electrode175, and a mold layer pattern4.

The photosensitive film pattern having the different thicknesses may be formed by using a slit or a half tone mask, wherein a first portion of one thickness is disposed between the source electrode173and the drain electrode175, and a second portion that is thicker than the first portion is disposed on the source data line171and the drain electrode175.

After etching the data metal layer and a buffer layer by using the photosensitive film pattern as a mask, the photosensitive film pattern is ashed to remove the first portion, and then the data metal layer is etched by using the second portion as a mask to separate the source electrode173. and the drain electrode175from each other, thereby completing the source electrode173and the drain electrode175.

The data metal layer and the buffer layer may be formed by using an imprinting process.

Next, as shown inFIG. 5, a passivation layer180of an organic material or inorganic material is formed on the source electrode173and the drain electrode175.

Next, the passivation layer180is etched to form a contact hole185exposing the drain electrode175.

Next, as shown inFIG. 6, a transparent conductive layer900of ITO or IZO is formed on the substrate110including the contact hole185.

Next, a photosensitive film is coated on the transparent conductive layer900, and patterned by using a slit or half tone mask to form the first and second photosensitive film patterns PR1and PR2.

The first photosensitive film pattern PR1that corresponds to a pixel electrode of the pixel area is thicker than the second photosensitive film pattern PR2.

Next, the transparent conductive layer900, the passivation layer180, the source electrode173, and the drain electrode175are etched by using the first and second photosensitive film patterns PR1and PR2as a mask to form the first and second through-holes183aand183bexposing the mold layer pattern. The mold layer pattern exposed through the first and second through-holes183aand183bis etched second time to form a mold layer400having an opening40.

Here, the secondary etching is executed as an over-etch such that the mold layer pattern is etched under the corners of source electrode173and the drain electrode175after the exposure of the gate insulating layer140, thereby forming an undercut around the corners of the source electrode and the drain electrode. Here, the etching is executed laterally as well as vertically in the direction of the curved line tips.

The gate insulating layer140and the mold layer400have similar composition, but may have significant etch rate difference such that the mold layer400is over-etched while the gate insulating layer140is intact.

The mold layer400may be formed of a material having a significant etch rate difference from that of the data metal layer.

Referring toFIG. 3andFIG. 6, the channel of the semiconductor layer must be formed between the source electrode173and the drain electrode175such that the opening40is connected between the source electrode173and the drain electrode175.

According to an exemplary embodiment of the present invention, the length of the channel between the source electrode173and the drain electrode175is in the range of about 3-4 μm such that it is preferable that the undercut A1is in the range more than 3 μm. Here, the distance A2between the first through-hole183aand the second through-hole183bis less than twice the length of the undercut A1.

For example, if the undercut A1is 3 μm, it is respectively under the first and second through-holes183aand183badjacent to the channel such that the distance A2between the first through-hole183aand the second through-hole183bwould be less than 6 μm.

Accordingly, if the channel length 3 μm is excluded, there is 3 μm remaining. Also, the interval A3from the first through-hole183ato a nearest boundary of the source electrode, boundary, and the interval A3from the second through-hole183bto a nearest boundary of the drain electrode may be both 1.5 μm.

In this case, the length A2is twice the length A1. However if the length A2is 7 μm, more than twice the length A1, and an undercut of only 3 μm is formed, the mold layer opening is etched short by 1 μm between two A1s such that the channel is not connected. Accordingly, it is preferable that the length A2be less than twice the length A1.

Next, as shown inFIG. 7, ashing is executed to remove the second photosensitive film pattern PR2, and the exposed transparent conductive layer900is etched by using the first photosensitive film pattern PR1as a mask to form a pixel electrode191. Referring toFIG. 1, a gate contact assistant81and a data contact assistant82may be formed along the pixel electrode191. In this case, the second photosensitive film pattern PR2is formed on the portion where the contact assistants81and82are disposed.

Next, as shown inFIG. 1, the first photosensitive film pattern PR1is removed, and an organic semiconductor layer154is formed in the opening40by using an Inkjet printing method through the first and second through-holes183aand183b.

Before filling the opening40with organic semiconductor layer154, the surfaces of the first and second through-holes183aand183band the opening40are subjected to surface treatment using a gas including fluorine to provide a hydrophobic property. Next, if the organic semiconductor solution is formed of a material having a hydrophilic property, the characteristic of the surfaces of the first and second through-holes183aand183band the opening40is different from the characteristic of the organic semiconductor layer such that the organic semiconductor layer may be easily collected in the opening40.

FIG. 8is a cross-sectional view of a thin film transistor array panel according to another exemplary embodiment of the present invention.

Referring toFIG. 8, as shown inFIG. 7, after forming an organic semiconductor154, an overcoat80of an insulating material of a solution type may be formed on the organic semiconductor154. The overcoat80is formed in the through-holes183aand183b, and protects the exposed semiconductor154. The overcoat80may be formed by the Inkjet printing method like the organic semiconductor154. Here, the organic semiconductor154does not completely fill the first and second through-holes183aand183b.

Accordingly, in an exemplary embodiment of the present invention, the organic semiconductor layer154is formed after forming the pixel electrode191to prevent the surface of the organic semiconductor layer154may be protected from being exposed to and damaged by the chemical solution or plasma in the etch process. Hence, the insertion forms a thin film transistor having stable channel characteristics.