Integrated circuit layout and method of configuring the same

An integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation.

The smaller feature size is the use of multigate devices such as fin field effect transistor (FinFET) devices. FinFETs are so called because a gate is present on and around a “fin” that extends from the substrate. FinFET devices may allow for shrinking the gate width of device while providing a gate on the sides and/or top of the fin including the channel region.

DETAILED DESCRIPTION

Reference is made toFIG. 1, which is a schematic diagram of an inverter100according to some embodiments of the present disclosure. The inverter100includes a PMOS (P-channel metal oxide semiconductor) transistor110and an NMOS (N-channel metal oxide semiconductor) transistor120. An input port130of the inverter100is electrically connected to gate terminals of the PMOS transistor110and the NMOS transistor120. An output port140of the inverter100is electrically connected to drain terminals of the PMOS transistor110and the NMOS transistor120.

When the input port130is set to “0” (for example, ground voltage), the PMOS transistor110is turned on, and the NMOS transistor120is turned off. In such a situation, current flows from VDD (voltage drain drain) through the PMOS transistor110to the output port140. When the input port130is set to “1” (for example, operation voltage), the PMOS transistor110is turned off, and the NMOS transistor120is turned on. In such a situation, current flows from the output port140through the NMOS transistor120to VSS (voltage source source).

Reference is made toFIG. 2A, which is a top view of a cell layout according to some embodiments of the present disclosure. The cell200is present on a semiconductor substrate. The cell200has a cell boundary including a top edge312, a bottom edge314, and opposite side edges316and318. A cell height is defined between the top edge312and the bottom edge314. A cell width is defined between the opposite side edges316and318.

The cell200includes a first transistor region212and a second transistor region214, in which the second transistor region214is arranged vertically next to the first transistor region212. A common boundary line315separates the first transistor region212and the second transistor region214. The first transistor region212of the cell200can be arranged to form PMOS transistors and can be regarded as a PMOS region212. The second transistor region214of the cell200can be arranged to form NMOS transistors and can be regarded as an NMOS region214.

A plurality of P-type active regions220a-220dare present in the PMOS region212, and a plurality of N-type active regions224a-224dare present in the NMOS region214. In some embodiments, an active region, such as the P-type active regions220a-220dand the N-type active regions224a-224d, is also referred to herein as OD (oxide-dimensioned region). The P-type active regions220a-220dare substantially perpendicular to the top edge312. The P-type active regions220a-220dare arranged substantially parallel to each other and are substantially equally spaced apart. The N-type active regions224a-224dare substantially perpendicular to the bottom edge314. The N-type active regions224a-224dare arranged substantially parallel to each other and are substantially equally spaced apart. In some embodiments, the P-type active regions220a-220dand the N-type active regions224a-224dare fin shaped, and the P-type active regions220a-220dand the N-type active regions224a-224dare staggered in a one-by-one configuration, in which each of the active regions, such as the P-type active regions220a-220dand the N-type active regions224a-224d, is staggered with the active region or regions adjacent thereto.

Gate electrodes230a-230dand dummy gate electrodes240a-240care present over the semiconductor substrate. InFIG. 2A, the gate electrodes230a-230dand the dummy gate electrodes240a-240care substantially parallel to each other and are substantially parallel to the top edge312and the bottom edge314. The gate electrodes230a-230dand the dummy gate electrodes240a-240care formed of polysilicon or other conductive materials, such as metals, metal alloys and metal silicides. The dummy gate electrodes240a-240care arranged to not act as a gate to any transistor. In some embodiments, gate electrodes and dummy gate electrodes, such as the gate electrodes230a-230dand the dummy gate electrodes240a-240c, are also referred to herein as PO. In some embodiments, the dummy gate electrodes240a-240care also referred to herein as PODE (poly on OD edge). In some embodiments, the active regions220a-220dand224a-224dare fin type in shape and, together with the corresponding gate electrodes230a-230d, form respective FinFET transistors.

The gate electrodes230aand230bare present in the PMOS region212. The gate electrodes230cand230dare present in the NMOS region214. The cell200further includes a plurality of cutting patterns250a-250d, such as cut polysilicon (CPO) patterns, for respectively separating the gate electrodes230a-230d. The cutting patterns250a-250drespectively represent cut sections or patterning areas where the gate electrodes230a-230dare removed.

The cutting pattern250aseparates the gate electrode230ainto two parts. One part of the gate electrode230acrosses the P-type active regions220aand220cand is partially present on an edge of the P-type active region220b, in which said part of the gate electrode230ais regarded as a dummy gate electrode to the P-type active region220b. The other part of the gate electrode230ais partially present on an edge of the P-type active region220dand is regarded as a dummy gate electrode to the P-type active region220d.

The cutting pattern250bseparates the gate electrode230binto two parts. One part of the gate electrode230bcrosses the P-type active regions220band220dand is partially present on an edge of the P-type active region220c, in which said part of the gate electrode230bis regarded as a dummy gate electrode to the P-type active region220c. The other part of the gate electrode230bis partially present on an edge of the P-type active region220aand is regarded as a dummy gate electrode to the P-type active region220a.

The cutting pattern250cseparates the gate electrode230cinto two parts. One part of the gate electrode230ccrosses the N-type active regions224aand224cand is partially present on an edge of the N-type active region224b, in which said part of the gate electrode230cis regarded as a dummy gate electrode to the N-type active region224b. The other part of the gate electrode230cis partially present on an edge of the N-type active region224dand is regarded as a dummy gate electrode to the N-type active region224d.

The cutting pattern250dseparates the gate electrode230dinto two parts. One part of the gate electrode230dcrosses the N-type active regions224band224dand is partially present on an edge of the N-type active region224c, in which said part of the gate electrode230dis regarded as a dummy gate electrode to the N-type active region224c. The other part of the gate electrode230dis partially present on an edge of the N-type active region224aand is regarded as a dummy gate electrode to the N-type active region224a.

In some embodiments, the dummy gate electrode240ais present on the top edge312, the dummy gate electrode240bis present on the common boundary line315, and the dummy gate electrode240cis present on the bottom edge314. The gate electrodes230aand230bare present between the dummy gate electrodes240aand240b, in which the gate electrode230ais present between the dummy gate electrode240aand the gate electrode230b, and the gate electrode230bis present between the gate electrode230aand the dummy gate electrode240b. The gate electrodes230cand230dare present between the dummy gate electrodes240band240c, in which the gate electrode230cis present between the dummy gate electrode240band the gate electrode230d, and the gate electrode230dis present between the gate electrode230cand the dummy gate electrode240c.

In some embodiments, the P-type active regions220a-220dare staggered in the PMOS region212, and the N-type active regions224a-224dare staggered in the NMOS region214. As shown inFIG. 2A, the P-type active regions220aand220care partially covered by the dummy gate electrode240awhile being spaced from the dummy gate electrode240b. The P-type active regions220band220dare partially covered by the dummy gate electrode240bwhile being spaced from the dummy gate electrode240a. The N-type active regions224aand224care partially covered by the dummy gate electrode240bwhile being spaced from the dummy gate electrode240c. The N-type active regions224band224dare partially covered by the dummy gate electrode240cwhile being spaced from the dummy gate electrode240b.

Reference is made toFIG. 2B, which is a top view of an integrated circuit layout using the cell200ofFIG. 2Aaccording to some embodiments of the present disclosure. In some embodiments, the cell200is arranged to form two inverters. One of the inverters includes the P-type active regions220aand220c, the N-type active regions224aand224c, and the gate electrodes230aand230c, and the other inverter includes the P-type active regions220band220d, the N-type active regions224band224d, and the gate electrodes230band230d.

In some embodiments, the P-type active regions220a-220dand the corresponding N-type active regions224a-224dare respectively interconnected through conductive metal one lines280aand conductive via zeros290a. For example, the P-type active region220dis connected to the N-type active region224dthrough the conductive metal one line280aand the conductive via zeros290a. Output ports of the inverters are respectively on or electrically connected to the conductive metal one lines280a. For simplicity, only one conductive metal one line280aand two conductive via zeros290aare labelled.

A VDD power supply line260and a VSS ground line270are implemented, for example, in metal two lines. In a top-down sequence, the VDD power supply line260is connected through conductive via ones292a, conductive metal one lines280b, and conductive via zeros290bto each of source regions of the P-type active regions220a-220d. For simplicity, only one conductive metal one line280b, one conductive via one292a, and one conductive via zero290bare labelled.

Similarly, the VSS ground line270is connected through conductive via ones292b, conductive metal one lines280c, and conductive via zeros290cto each of source regions of the N-type active regions224a-224d. For simplicity, only one conductive metal one line280c, one conductive via one292b, and one conductive via zero290care labelled.

Furthermore, the gate electrodes230aand230bin the PMOS region212are respectively connected to the gate electrodes230cand230din the NMOS region214through conductive metal one lines280dand conductive via zeros290d. For example, the gate electrode230ais connected to the gate electrode230cthrough the conductive metal one line280dand the conductive via zeros290d. Input ports of the inverters are respectively on or electrically connected to the conductive metal one lines280d. For simplicity, only one conductive metal one line280dand two conductive via zeros290dare labelled.

FIG. 3is a top view of a cell layout according to some embodiments of the present disclosure. The difference betweenFIG. 3andFIG. 2Aincludes the arrangement of the P-type active regions220a-220d, the N-type active regions224a-224d, and the cutting patterns250a-250d. Referring toFIG. 3, the P-type active regions220band220dare partially covered by the dummy gate electrode240awhile being spaced from the dummy gate electrode240b. The P-type active regions220aand220care partially covered by the dummy gate electrode240bwhile being spaced from the dummy gate electrode240a. The N-type active regions224band224dare partially covered by the dummy gate electrode240bwhile being spaced from the dummy gate electrode240c. The N-type active regions224aand224care partially covered by the dummy gate electrode240cwhile being spaced from the dummy gate electrode240b. The positions of the cutting patterns250a-250dmay be adjusted accordingly. For example, the cutting pattern250afor separating the gate electrode230ais present between the P-type active regions220aand220b; the cutting pattern250bfor separating the gate electrode230bis present between the P-type active regions220cand220d; the cutting pattern250cfor separating the gate electrode230cis present between the N-type active regions224aand224b; and the cutting pattern250dfor separating the gate electrode230dis present between the N-type active regions224cand224d.

Similarly, the interconnection among the P-type active regions220a-220d, the N-type active regions224a-224d, and the gate electrodes230a-230dmay be similar to that shown inFIG. 2Band therefore is not repeated here to avoid duplicity.

FIG. 4is a top view of a cell layout according to some embodiments of the present disclosure. The difference betweenFIG. 4andFIG. 2Aincludes the arrangement of the P-type active regions220a-220d, the N-type active regions224a-224d, the gate electrodes230a-230d, and the cutting patterns250a-250d. InFIG. 4, the edge of each of the P-type active regions220aand220cdistal to the dummy gate electrode240ais not covered by the gate electrode230b; the edge of each of the P-type active regions220band220ddistal to the dummy gate electrode240bis not covered by the gate electrode230a; the edge of each of the N-type active regions224aand224cdistal to the dummy gate electrode240bis not covered by the gate electrode230d; and the edge of each of the N-type active regions224band224ddistal to the dummy gate electrode240cis not covered by the gate electrode230c. That is, the cell layout ofFIG. 4represents a non-PODE configuration, in which each of the gate electrodes230a-230dhas no portion arranged to act as a PODE structure. In some embodiments, each or at least one of the cutting patterns250a-250din the non-PODE configuration may be substantially aligned with at least one of the active regions220a-220dand224a-224d. For example, the cutting pattern250amay be substantially aligned with the P-type active region220d; the cutting pattern250bmay be substantially aligned with the P-type active region220a; the cutting pattern250cmay be substantially aligned with the N-type active region224d; and the cutting pattern250dmay be substantially aligned with the N-type active region224a. In some alternative embodiments, the cutting patterns250a-250din the non-PODE configuration may be similar to that shown inFIG. 2Aas well, in which each or at least one of the cutting patterns250a-250dis present between adjacent two of the active regions220a-220dand224a-224d.

The interconnection among the P-type active regions220a-220d, the N-type active regions224a-224d, and the gate electrodes230a-230dmay be similar to that shown inFIG. 2Band therefore is not repeated here to avoid duplicity.

FIG. 5Ais a top view of a cell layout according to some embodiments of the present disclosure. Unlike the cells200having the active regions220a-220dand224a-224dstaggered in the one-by-one configuration shown inFIGS. 2A, 3 and 4, the active regions420a-420dand424a-424dof the cell400are staggered in groups, in which the active regions420a-420dand424a-424dof each group are substantially aligned with each other, and the active regions420a-420dand424a-424dof adjacent groups are not aligned. Referring toFIG. 5A, the P-type active regions420aand420bare partially covered by the dummy gate electrode440awhile being spaced from the dummy gate electrode440b. The P-type active regions420cand420dare partially covered by the dummy gate electrode440bwhile being spaced from the dummy gate electrode440a. The N-type active regions424aand424bare partially covered by the dummy gate electrode440bwhile being spaced from the dummy gate electrode440c. The N-type active regions424cand424dare partially covered by the dummy gate electrode440cwhile being spaced from the dummy gate electrode440b.

The gate electrode430ais separated by the cutting pattern450ainto two parts. One part of the gate electrode430acrosses the P-type active regions420aand420b. The other part of the gate electrode430ais partially present on edges of the P-type active regions420cand420dand is regarded as a dummy gate electrode to the P-type active regions420cand420d. The gate electrode430bis separated by the cutting pattern450binto two parts. One part of the gate electrode430bcrosses the P-type active regions420cand420d. The other part of the gate electrode430bis partially present on edges of the P-type active regions420aand420band is regarded as a dummy gate electrode to the P-type active regions420aand420b. The gate electrode430cis separated by the cutting pattern450cinto two parts. One part of the gate electrode430ccrosses the N-type active regions424aand424b. The other part of the gate electrode430cis partially present on edges of the N-type active regions424cand424dand is regarded as a dummy gate electrode to the N-type active regions424cand424d. The gate electrode430dis separated by the cutting pattern450dinto two parts. One part of the gate electrode430dcrosses the N-type active regions424cand424d. The other part of the gate electrode430dis partially present on edges of the N-type active regions424aand424band is regarded as a dummy gate electrode to the N-type active regions424aand424b.

Reference is made toFIG. 5B, which is a top view of an integrated circuit layout using the cell400ofFIG. 5Aaccording to some embodiments of the present disclosure. In some embodiments, the cell400is arranged to form two inverters. One of the inverters includes the P-type active regions420aand420b, the N-type active regions424aand424b, and the gate electrodes430aand430c, and the other inverter includes the P-type active regions420cand420d, the N-type active regions424cand424d, and the gate electrodes430band430d.

In some embodiments, the P-type active regions420a-420dand the corresponding N-type active regions424a-424dare respectively interconnected through conductive metal one lines480aand conductive via zeros490a. For example, the P-type active region420ais connected to the N-type active region424athrough the conductive metal one line480aand the conductive via zeros490a. Output ports of the inverters are respectively on or electrically connected to the conductive metal one lines480a. For simplicity, only one conductive metal one line480aand two conductive via zeros490aare labelled.

A VDD power supply line460and a VSS ground line470are implemented, for example, in metal two lines. In a top-down sequence, the VDD power supply line460is connected through conductive via ones492a, conductive metal one lines480b, and conductive via zeros490bto each of source regions of the P-type active regions420a-420d. For simplicity, only one conductive metal one line480b, one conductive via one492a, and one conductive via zero490bare labelled.

The VSS ground line470is connected through conductive via ones492b, conductive metal one lines480c, and conductive via zeros490cto each of source regions of the N-type active regions424a-424d. For simplicity, only one conductive metal one line480c, one conductive via one492b, and one conductive via zero490care labelled.

Furthermore, the gate electrodes430aand430bare respectively connected to the gate electrodes430cand430dthrough conductive metal one lines480dand conductive via zeros490d. For example, the gate electrode430ais connected to the gate electrode430cthrough the conductive metal one line480dand the conductive via zeros490d. Input ports of the inverters are respectively on or electrically connected to the conductive metal one lines480d. For simplicity, only one conductive metal one line480dand two conductive via zeros490dare labelled.

FIG. 6is a top view of a cell layout according to some embodiments of the present disclosure. The difference betweenFIG. 6andFIG. 5Aincludes the arrangement of the P-type active regions420a-420dand the N-type active regions424a-424d. The P-type active regions420aand420bare partially covered by the dummy gate electrode440bwhile being spaced from the dummy gate electrode440a. The P-type active regions420cand420dare partially covered by the dummy gate electrode440awhile being spaced from the dummy gate electrode440b. The N-type active regions424aand424bare partially covered by the dummy gate electrode440cwhile being spaced from the dummy gate electrode440b. The N-type active regions424cand424dare partially covered by the dummy gate electrode440bwhile being spaced from the dummy gate electrode440c.

Similarly, the interconnection among the P-type active regions420a-420d, the N-type active regions424a-424d, and the gate electrodes430a-430dmay be similar to that shown inFIG. 5Band therefore is not repeated here to avoid duplicity.

FIG. 7is a top view of a cell layout according to some embodiments of the present disclosure. The difference betweenFIG. 7andFIG. 5Aincludes the arrangement of the P-type active regions420a-420d, the N-type active regions424a-424d, the gate electrodes430a-430d, and the cutting patterns450a-450d. InFIG. 7, the edge of each of the P-type active regions420aand420bdistal to the dummy gate electrode440ais not covered by the gate electrode430b; the edge of each of the P-type active regions420cand420ddistal to the dummy gate electrode440bis not covered by the gate electrode430a; the edge of each of the N-type active regions424aand424bdistal to the dummy gate electrode440bis not covered by the gate electrode430d; and the edge of each of the N-type active regions424cand424ddistal to the dummy gate electrode440cis not covered by the gate electrode430c. That is, the cell layout ofFIG. 7represents a non-PODE configuration, in which each of the gate electrodes430a-430dhas no portion arranged to act as a PODE structure. In some embodiments, each or at least one of the cutting patterns450a-450din the non-PODE configuration may be substantially aligned with at least one of the active regions420a-420dand424a-424d. For example, the cutting pattern450amay be substantially aligned with the P-type active region420c; the cutting pattern450bmay be substantially aligned with the P-type active region420b; the cutting pattern450cmay be substantially aligned with the N-type active region424c; and the cutting pattern450dmay be substantially aligned with the N-type active region424b. In some alternative embodiments, the cutting patterns450a-450din the non-PODE configuration may be similar to that shown inFIG. 5Aas well, in which each or at least one of the cutting patterns450a-450dis present between adjacent two of the active regions420a-420dand424a-424d.

The interconnection among the P-type active regions420a-420d, the N-type active regions424a-424d, and the gate electrodes430a-430dmay be similar to that shown inFIG. 5Band therefore is not repeated here to avoid duplicity.

In some embodiments, as shown inFIG. 8, the cell400has eight P-type active regions420and eight N-type active regions424. The P-type active regions420are divided into two groups420L and420R. The P-type active regions420in the same group420L or420R are substantially aligned with each other, while the groups420L and420R are staggered. The P-type active regions420in the group420L are closer to the top edge312, and the P-type active regions420in the group420R are closer to the common boundary line315. Similarly, the N-type active regions424are divided into two groups424L and424R as well. The N-type active regions424in the same group424L or424R are substantially aligned with each other, while the groups424L and424R are staggered. The N-type active regions424in the group424L are closer to the common boundary line315, and the N-type active regions424in the group420R are closer to the bottom edge314.

In some embodiments, as shown inFIG. 8, each of the cutting patterns450a-450dmay be present between adjacent two of the active regions420and424. On the other hand, in a non-PODE configuration, in which each of the gate electrodes430a-430dhas no portion arranged to act as a PODE structure, as shown inFIG. 9, each of the cutting patterns450a-450dmay be substantially aligned with at least one of the active regions420and424. In some alternative embodiments, the cutting patterns450a-450din the non-PODE configuration may be similar to that shown inFIG. 8as well, in which each or at least one of the cutting patterns450a-450dare present between adjacent two of the active regions420and424.

The interconnection among the P-type active regions420, the N-type active regions424, and the gate electrodes430a-430dmay be similar to that shown inFIG. 5Band therefore is not repeated here to avoid duplicity.

Reference is made toFIG. 10, which is a top view of an integrated circuit layout according to some embodiments of the present disclosure. The layout600includes at least one first cell610and at least one second cell620. The first cell610is a cell having active regions staggered in a one-by-one configuration, such as but not limited to the cells200shown inFIGS. 2A, 3 and 4. The second cell620is a cell having active regions staggered in groups, such as but not limited to the cells400shown inFIGS. 5A, and6-9.

The cell heights of the first cell610and the second cell620are substantially the same, which enables the first cell610and the second cell620to be placed in a row. The first cell610has high device density since the devices of the first cell610can be more staggered, and the first cell610can be small in size. On the other hand, the devices of the second cell620can be used to build a complicated circuit. Furthermore, the devices of the second cell620have less or no PODE structure on their gate electrodes, and thus the devices of the second cell620will have high device performance and low power consumption. For example, as shown inFIG. 6, a part of the gate electrode430athat crosses the P-type active regions420cand420dhas no portion arranged to act as a PODE structure, and thus the device performance and the power consumption of the FinFET formed by the P-type active regions420cand420dand the gate electrode430awill not be affected by the PODE structure. As shown inFIG. 10, by abutting the first cell610and the second cell620in the row, the designer will have the freedom to design the arrangement of devices.

In some embodiments, at least one of gate electrodes616a-616dof the first cell610and at least one of gate electrodes626a-626dof the second cell620are physically connected to each other. As shown inFIG. 10, the gate electrode616aof the first cell610is physically connected to the gate electrode626aof the second cell620; the gate electrode616bof the first cell610is physically connected to the gate electrode626bof the second cell620; the gate electrode616cof the first cell610is physically connected to the gate electrode626cof the second cell620; and the gate electrode616dof the first cell610is physically connected to the gate electrode626dof the second cell620.

Furthermore, dummy gate electrodes614a-614cof the first cell610and dummy gate electrodes624a-624cof the second cell620extend substantially along a longitudinal direction of the row. When the first cell610and the second cell620are abutted in the row, the dummy gate electrodes614a-614cof the first cell610and the dummy gate electrodes624a-624cof the second cell620at the same horizontal level are physically connected to each other. For example, the dummy gate electrode614aof the first cell610and the dummy gate electrode624aof the second cell620are physically connected to each other; the dummy gate electrode614bof the first cell610and the dummy gate electrode624bof the second cell620are physically connected to each other; and the dummy gate electrode614cof the first cell610and the dummy gate electrode624cof the second cell620are physically connected to each other.

Since the dummy gate electrodes614a-614cof the first cell610and the dummy gate electrodes624a-624cof the second cell620are conductive, the continuous dummy gate electrodes614a-614cand624a-624ccan be utilized for interconnecting the first cell610and the second cell620. That is, some signals may travel through the dummy gate electrodes614a-614cand624a-624crather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the first cell610and the second cell620can be reduced.

FIG. 11toFIG. 13are top views of integrated circuit layouts according to some embodiments of the present disclosure. The numbers, arrangement, and types of the first cell610and the second cell620may vary according to circuit design. As shown inFIG. 11, a first cell610is sandwiched between two second cells620, and the second cells620are different from each other. As shown inFIG. 12, the first cells610and the second cells620are alternatingly arranged. As shown inFIG. 13, a second cell620is sandwiched between two first cells610.

In some embodiments, the P-type active regions and the N-type active regions may be horizontally arranged in the cell. Reference is made toFIG. 14A. The cell700includes a plurality of P-type active regions710aand710b, a plurality of N-type active regions720aand720b, a plurality of gate electrodes730aand730b, and a plurality of dummy gate electrodes740aand740b.

The dummy gate electrodes740aand740bare respectively present on the top edge and the bottom edge of the cell700. The gate electrodes730aand730bare present between the dummy gate electrodes740aand740b.

In some embodiments, the P-type active regions710aand710band the N-type active regions720aand720bare staggered in the cell700. For example, the P-type active region710aand the N-type active region720aare partially covered by the dummy gate electrode740awhile being spaced from the dummy gate electrode740b. The P-type active region710band the N-type active region720bare partially covered by the dummy gate electrode740bwhile being spaced from the dummy gate electrode740a. The P-type active region710bis present between the P-type active region710aand the N-type active region720a, and the N-type active region720ais present between the P-type active regions710band the N-type active region720b.

The cell700further includes a plurality of cutting patterns750aand750brespectively for separating the gate electrodes730aand730b. In some embodiments, the gate electrode730ais separated by the cutting pattern750ainto two parts. One part of the gate electrode730acrosses the P-type active region710aand the N-type active region720aand is partially present on an edge of the P-type active region710b, in which said part of the gate electrode730ais regarded as a dummy gate electrode to the P-type active region710b. The other part of the gate electrode730ais partially present on an edge of the N-type active region720band is regarded as a dummy gate electrode to the N-type active region720b. The gate electrode730bis separated by the cutting pattern750binto two parts. One part of the gate electrode730bcrosses the P-type active region710band the N-type active region720band is partially present on an edge of the N-type active region720a, in which said part of the gate electrode730bis regarded as a dummy gate electrode to the N-type active region720a. The other part of the gate electrode730bis partially present on an edge of the P-type active region710aand is regarded as a dummy gate electrode to the P-type active region710a.

Reference is made toFIG. 14B, which is a top view of an integrated circuit layout using the cell700ofFIG. 14Aaccording to some embodiments of the present disclosure. In some embodiments, the cell700is arranged to form two inverters. One of the inverters includes the P-type active region710a, the N-type active region720a, and the gate electrode730a, and the other inverter includes the P-type active region710b, the N-type active region720b, and the gate electrode730b.

A VDD power supply line760and a VSS ground line770are implemented, for example, in metal one lines. The VDD power supply line760is connected through conductive via zeros790ato each of source regions of the P-type active regions710aand710b. Similarly, the VSS ground line770is connected through conductive via zeros790bto each of source regions of the N-type active regions720aand720b.

In some embodiments, drain regions of the P-type active region710aand the N-type active region720aare interconnected through a local conductive metal segment780c. Similarly, drain regions of the P-type active regions710band the N-type active region720bare interconnected through a local conductive metal segment780d. Output ports of the inverters are respectively on or electrically connected to the local conductive metal segments780cand780d. Input ports of the inverters are respectively on or electrically connected to a part of the gate electrode730athat crosses the P-type active region710aand the N-type active region720aand a part of the gate electrode730bthat crosses the P-type active region710band the N-type active region720b.

FIG. 15is a top view of a cell layout according to some embodiments of the present disclosure. The difference betweenFIG. 15andFIG. 14Aincludes the arrangement of the P-type active regions710aand710b, the N-type active regions720aand720b, and the cutting patterns750aand750b. Referring toFIG. 15, the P-type active region710aand the N-type active region720aare partially covered by the dummy gate electrode740bwhile being spaced from the dummy gate electrode740a. The P-type active region710band the N-type active region720bare partially covered by the dummy gate electrode740awhile being spaced from the dummy gate electrode740b. The cutting pattern750afor separating the gate electrode730ais present between the P-type active regions710aand710b. The cutting pattern750bfor separating the gate electrode730bis present between the N-type active regions720aand720b.

The interconnection among the P-type active regions710aand710b, the N-type active regions720aand720b, and the gate electrodes730aand730bmay be similar to that shown inFIG. 14Band therefore is not repeated here to avoid duplicity.

FIG. 16is a top view of a cell layout according to some embodiments of the present disclosure. The difference betweenFIG. 16andFIG. 14Aincludes the arrangement of the P-type active regions710aand710b, the N-type active regions720aand720b, the gate electrodes730a-730band the cutting patterns750aand750d. Referring toFIG. 16, the edge of each of the P-type active region710aand the N-type active region720adistal to the dummy gate electrode740ais not covered by the gate electrode730b, and the edge of each of the P-type active region710band the N-type active region720bdistal to the dummy gate electrode740bis not covered by the gate electrode730a. That is, the cell layout ofFIG. 16represents a non-PODE configuration, in which each of the gate electrodes730aand730bhas no portion arranged to act as a PODE structure. In some embodiments, each or at least one of the cutting patterns750aand750bin the non-PODE configuration may be substantially aligned with at least one of the active regions710a-710band720a-720b. For example, the cutting pattern750amay be substantially aligned with the N-type active region720b, and the cutting pattern750bmay be substantially aligned with the P-type active region710a. In some alternative embodiments, the cutting patterns750aand750bin the non-PODE configuration may be similar to that shown inFIG. 14Aas well, in which each or at least one of the cutting patterns750aand750bis present between adjacent two of the active regions710a-710band720a-720b.

The interconnection among the P-type active regions710aand710b, the N-type active regions720aand720b, and the gate electrodes730aand730bmay be similar to that shown inFIG. 14Band therefore is not repeated here to avoid duplicity.

Reference is made toFIG. 17A. Unlike the cells700having the active regions710a-710band720a-720bstaggered in the one-by-one configuration shown in FIGS.14A,15and16, the active regions810a-810band820a-820bof the cell800are staggered in groups, in which the active regions810a-810band820a-820bof each group are substantially aligned with each other, and the active regions810a-810band820a-820bof adjacent groups are not aligned. Referring toFIG. 17A, the P-type active region810aand the N-type active region820aare partially covered by the dummy gate electrode840awhile being spaced from the dummy gate electrode840b. The P-type active region810band the N-type active region820bare partially covered by the dummy gate electrode840bwhile being spaced from the dummy gate electrode840a.

The gate electrode830ais separated by the cutting pattern850ainto two parts. One part of the gate electrode830acrosses the P-type active region810aand the N-type active region820a. The other part of the gate electrode830ais partially present on edges of the P-type active region810band the N-type active region820band is regarded as a dummy gate electrode to the P-type active region810band the N-type active region820b. The gate electrode830bis separated by the cutting pattern850binto two parts. One part of the gate electrode830bcrosses the P-type active region810band the N-type active region820b. The other part of the gate electrode830bis partially present on edges of the P-type active region810aand the N-type active region820aand is regarded as a dummy gate electrode to the P-type active region810aand the N-type active region820a.

Reference is made toFIG. 17B, which is a top view of an integrated circuit layout using the cell800ofFIG. 17Aaccording to some embodiments of the present disclosure. In some embodiments, the cell800is arranged to form two inverters. One of the inverters includes the P-type active region810a, the N-type active region820a, and the gate electrode830a, and the other inverter includes the P-type active region810b, the N-type active region820b, and the gate electrode830b.

A VDD power supply line860and a VSS ground line870are implemented, for example, in metal one lines. The VDD power supply line860is connected through conductive via zeros890ato each of source regions of the P-type active regions810aand810b. Similarly, the VSS ground line870is connected through conductive via zeros890bto each of source regions of the N-type active regions820aand820b.

In some embodiments, drain regions of the P-type active region810aand the N-type active region820aare interconnected through a local conductive metal segment880c. Similarly, drain regions of the P-type active region810band the N-type active region820bare interconnected through a local conductive metal segment880d. Output ports of the inverters are respectively on or electrically connected to the local conductive metal segments880cand880d. Input ports of the inverters are respectively on or electrically connected to a part of the gate electrode830athat crosses the P-type active region810aand the N-type active region820aand a part of the gate electrode830bthat crosses the P-type active region810band the N-type active region820b.

FIG. 18is a top view of a cell layout according to some embodiments of the present disclosure. The difference betweenFIG. 18andFIG. 17Aincludes the arrangement of the P-type active regions810aand810band the N-type active regions820aand820b. Referring toFIG. 18, the P-type active region810aand the N-type active region820aare partially covered by the dummy gate electrode840bwhile being spaced from the dummy gate electrode840a. The P-type active region810band the N-type active region820bare partially covered by the dummy gate electrode840awhile being spaced from the dummy gate electrode840b.

Similarly, the interconnection among the P-type active regions810aand810b, the N-type active regions820aand820b, and the gate electrodes830aand830bmay be similar to that shown inFIG. 17Band therefore is not repeated here to avoid duplicity.

FIG. 19is a top view of a cell layout according to some embodiments of the present disclosure. The difference betweenFIG. 19andFIG. 17Aincludes the arrangement of the P-type active regions810aand810b, the N-type active regions820aand820b, the gate electrodes830aand830band the cutting patterns850aand850b. Referring toFIG. 19, the edge of each of the P-type active region810aand the N-type active region820adistal to the dummy gate electrode840ais not covered by the gate electrode830b, and the edge of each of the P-type active region810band the N-type active region820bdistal to the dummy gate electrode840bis not covered by the gate electrode830a. That is, the cell layout ofFIG. 19represents a non-PODE configuration, in which each of the gate electrodes830aand830bhas no portion arranged to act as a PODE structure. In some embodiments, each or at least one of the cutting patterns850aand850bin the non-PODE configuration may be substantially aligned with at least one of the active regions810a-810band820a-820b. For example, the cutting pattern850amay be substantially aligned with the P-type active region810b, and the cutting pattern850bmay be substantially aligned with the N-type active region820a. In some alternative embodiments, the cutting patterns850aand850bin the non-PODE configuration may be similar to that shown inFIG. 17Aas well, in which each or at least one of the cutting patterns850aand850bis present between adjacent two of the active regions810a-810band820a-820b.

The interconnection among the P-type active regions810aand810b, the N-type active regions820aand820b, and the gate electrodes830aand830bmay be similar to that shown inFIG. 17Band therefore is not repeated here to avoid duplicity.

Reference is made toFIG. 20. The cell700and the cell800can be abutted in a row, in which the cell700is a cell having active regions staggered in a one-by-one configuration, such as but not limited to the cells700shown inFIGS. 14A, 15 and 16, and the cell800is a cell having active regions staggered in groups, such as but not limited to the cells400shown inFIGS. 17A, 18, and 19.

The cell heights of the cell700and the cell800are substantially the same, which enables the cell700and the cell800to be placed in a row. The cell700has high device density since the devices of the cell700can be more staggered, and the cell700can be small in size. On the other hand, the devices of the cell800can be used to build a complicated circuit and will have high device performance and low power consumption since the devices of the cell800have less or no PODE structure on their gate electrodes. As shown inFIG. 20, by abutting the cell700and the cell800in the row, the designer will have the freedom to design the arrangement of devices. Furthermore, at least one of the dummy gate electrodes of the cell700and at least one of the dummy gate electrodes of the cell800are physically connected, thus the conductive and continuous dummy gate electrodes can be utilized for interconnecting the cell700and the cell800.

Reference is made toFIG. 21, which is a flowchart of a method of configuring an integrated circuit layout according to some embodiments of the present disclosure. In the design of an integrated circuit, various cells having predetermined functions are used, and the layouts of cells are stored in, for example, at least one cell library. The method begins at operation910, in which at least one first cell having active regions staggered in a one-by-one configuration, such as but not limited to the cells shown inFIGS. 2A, 3, 4, 14A, 15 and 16, and at least one second cell having active regions staggered in groups, such as but not limited to the cells shown inFIGS. 5A, 6-9, 17A, 18, and19, are obtained from the cell library. The method goes to operation920, in which the first cell and the second cell are placed into one or more desired locations on an integrated circuit layout and are abutted in at least one row.

FIG. 22illustrates a processing system1000wherein the above described method may be implemented in order to generate one or more of the above described layout embodiments. The processing system1000includes a processor1002, which may include a central processing unit, an input/output circuitry, a signal processing circuitry, and a volatile and/or a non-volatile memory. The processor1002receives input, such as user input, from an input device1004. The input device1004may include one or more of a keyboard, a mouse, a tablet, a contact sensitive surface, a stylus, a microphone, and the like. The processor1002may also receive input, such as standard cell layouts, cell libraries, models, and the like, from a non-transitory machine readable storage medium1008. The non-transitory machine readable storage medium1008may be located locally to the processor1002, or may be remote from the processor1002, in which communications between the processor1002and the non-transitory machine readable storage medium1008occur over a network, such as a telephone network, the Internet, a local area network, a wide area network, or the like. The non-transitory machine readable storage medium1008may include one or more of a hard disk, magnetic storage, optical storage, non-volatile memory storage, and the like. Included in the non-transitory machine readable storage medium1008may be database software for organizing data and instructions stored on the non-transitory machine readable storage medium1008. The processing system1000may include an output device1006, such as one or more of a display device, speaker, and the like, for outputting information to a user. As described above, the processor1002generates a layout for an integrated circuit. The layout may be stored in the non-transitory machine readable storage medium1008. One or more integrated circuit manufacturing machines, such as a photomask generator1010, may communicate with the non-transitory machine readable storage medium1008, either locally or over a network, either directly or via an intermediate processor, such as the processor1002. In some embodiments, the photomask generator1010generates one or more photomasks to be used in the manufacture of an integrated circuit, in conformance with a layout stored in the non-transitory machine readable storage medium1008.

By abutting a first cell having active regions staggered in a one-by-one configuration and a second cell having active regions staggered in groups in a row, the designer will have the freedom to dispose different devices adjacent to each other. Therefore, the devices with various sizes, performances, channel widths, or the like may be put together to build an integrated circuit.

According to some embodiments of the disclosure, an integrated circuit includes at least one first active region, at least one second active region adjacent to the first active region, and a plurality of third active regions. The first active region and the second active region are staggered. The third active regions are present adjacent to the first active region, wherein the third active regions are substantially aligned with each other.

According to some embodiments of the disclosure, an integrated circuit includes a first cell and a second cell. The first cell includes a first active region, a first gate electrode crossing the first active region, a second active region adjacent to the first active region, and a second gate electrode crossing the second active region. The second cell includes a plurality of third active regions adjacent to each other, and a third gate electrode crossing the third active regions, in which the first cell and the second cell abut each other.

According to some embodiments of the disclosure, a method of configuring an integrated circuit layout using a processor includes using the processor to generate a first cell and a second cell, in which the first cell includes at least one first active region and at least one second active region arranged therein, and the second cell includes a plurality of third active regions substantially aligned with each other. The first active region and the second active region are adjacent to each other but are not aligned. The processor abuts the first cell and the second cell on the integrated circuit layout. A set of instructions are generated for manufacturing an integrated circuit based upon the integrated circuit layout, and the set of instructions are stored in an non-transitory machine readable storage medium.