Wafer-level package having multiple dies arranged in side-by-side fashion and associated yield improvement method

A wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die and a second die. The dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths connect input/output (I/O) pads arranged on the first side of the first die to I/O pads arranged on the first side of the second die, wherein adjacent I/O pads on the first side of the first die are connected to adjacent I/O pads on the first side of the second die via connection paths on only a single layer. For example, the first die is identical to the second die. For another example, the wafer-level package is an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. For yet another example, the dies are assembled in the wafer-level package to perform a network switch function.

BACKGROUND

The present invention relates to design and fabrication of a chip, and more particularly, to a wafer-level package having multiple dies arranged in a side-by-side fashion and an associated yield improvement method.

When a chip function of a target chip is achieved using a large-sized die, the fabrication of large-sized dies on a wafer will suffer from low yield and high cost. For example, assuming that distribution of defects on a wafer is the same, a die yield of large-sized dies fabricated on the wafer is lower than a die yield of small-sized dies fabricated on the same wafer. In other words, the die yield loss is positively correlated with the die size. If the network switch chips are fabricated using large-sized dies, the production cost of the network switch chips is high due to the high die yield loss. Thus, there is a need for an innovative integrated circuit design which is capable of reducing the yield loss as well as the production cost.

SUMMARY

One of the objectives of the claimed invention is to provide a wafer-level package having multiple dies arranged in a side-by-side fashion and a related yield improvement method.

According to a first aspect of the present invention, an exemplary wafer-level package is disclosed. The exemplary wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die and a second die, wherein the dies are arranged in a side-by-side fashion, and a first side of the first die is adjacent to a first side of the second die. The connection paths are configured to connect input/output (I/O) pads arranged on the first side of the first die to I/O pads arranged on the first side of the second die, wherein adjacent I/O pads on the first side of the first die are connected to adjacent I/O pads on the first side of the second die via connection paths on only a single layer.

According to a second aspect of the present invention, an exemplary wafer-level package is disclosed. The exemplary wafer-level package includes a plurality of dies and a plurality of connection paths. The dies include at least a first die, a second die, and a third die, wherein the dies are arranged in a side-by-side fashion, the first die is identical to the second die, and the third die is distinct from each of the first die and the second die. The connection paths are configured to connect input/output (I/O) pads arranged on a first side of the first die to I/O pads arranged on a first side of the third die, and configured to connect I/O pads arranged on a first side of the second die to I/O pads arranged on a second side of the third die, wherein each of the first side of the first die and the first side of the second die is a same side of an identical die.

According to a third aspect of the present invention, an exemplary yield improvement method is disclosed. The exemplary yield improvement method includes: providing a plurality of first candidate dies each having a same first circuit module design, wherein a chip function of a target chip is split into at least first circuit designs each having the same first circuit module design; selecting a plurality of first good dies from the first candidate dies; and generating the target chip by assembling at least the selected first good dies in a wafer-level package.

DETAILED DESCRIPTION

FIG. 1is a flowchart illustrating a first yield improvement method according to an embodiment of the present invention. Provided that the result is substantially the same, the steps are not required to be executed in the exact order shown inFIG. 1. In addition, certain steps may be added to or removed from the flow shown inFIG. 1. The exemplary yield improvement method may be briefly summarized as below.

Step102: Provide a plurality of candidate dies each having the same circuit module design. For example, a chip function of a target chip is split into a plurality of circuit designs each having the same circuit module design.

Step104: Select a plurality of good dies from the candidate dies.

Step106: Generate the target chip by assembling the selected good dies in the same wafer-level package.

Byway of example, but not limitation, all of the steps102-106may be performed in the same semiconductor foundry. Given the same die area, the yield of one large die is lower than the yield of multiple small dies. Splitting one large die to multiple smaller dies may bring some overhead. There is a need to minimize the overhead. Hence, the present proposes an innovative manner to split a chip (e.g., a switch chip). For example, assuming that distribution of defects on a wafer is the same, a die yield of one large-sized dies fabricated on the wafer is lower than a die yield of multiple small-sized dies which have the same area fabricated on the same wafer. Since the fabrication of large-sized dies on a wafer suffers from low yield and high cost, the present invention therefore proposes determining a circuit module design such that a chip function of a target chip can be split into a plurality of circuit designs each having the same circuit module design, and fabricating a plurality of smaller-sized dies, each having the same circuit module design, on a wafer.

Please refer toFIG. 2in conjunction withFIG. 3.FIG. 2is a diagram illustrating an example of a target chip fabricated using a large-sized die.FIG. 3is a diagram illustrating an example of splitting a chip function of a target chip into two circuit designs each having the same circuit module design. In this example, one target chip (e.g., a network switch chip)200is designed to support a chip function (e.g., a network switch function) realized using a plurality of functional blocks202and204_1-204_4, where the functional blocks204_1-204_4have the same function F2, and the functional block202has a function F1distinct from the function F2. For example, the functional block202may include a traffic manager (TM) of a multi-plane network switch, and each of the functional blocks204_1-204_4may include ingress packet processing circuits and egress packet processing circuits of one plane.

Wafer-level packaging is the technology of packaging semiconductor dies, which is different from a typical packaging method of slicing a wafer into individual semiconductor dies and then packaging the individual semiconductor dies. The wafer-level package mentioned above is therefore fabricated based on wafer-level process. That is, multiple semiconductor dies (e.g., homogeneous dies or heterogeneous dies) assembled in the same wafer-level package and connection paths/transmission buses/communication channels and so on routed between the semiconductor dies are fabricated with wafer-level process. Hence, connection paths, communication buses, or communication channels could be implemented by metal layer (such as RDL metal layer, Re-Distribution Layer, a metal layer on a die that makes the I/O pads of an integrated circuit available in other locations) rather than bonding wire of typical package.

The wafer-level package may be an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. Take InFO packages as examples for the following wafer-level packages, but not for a limitation. The wafer-level package used for the proposed ideas may be an InFO package or a CoWoS package, “InFO package” and “CoWoS package” may be interchangeable.

As shown inFIG. 3, the chip function of the target chip200is evenly split into two circuit designs206_1and206_2each having the same circuit module design. In this embodiment, a circuit module design is designed to have one functional block with the function F1and two function blocks with the same function F2, and is further designed to have an extra input/output (I/O) function302due to partition overhead needed for reconstructing a target chip with a desired chip function in a wafer-level package. If the circuit design206_2is rotated by 180 degrees, the circuit design206_2exactly matches the circuit design206_1due to that fact both of the circuit designs206_1and206_2have the same circuit module design. Since the chip function of the target chip200is evenly split into two identical dies, none of the function blocks in each identical die is treated as a redundant block after two identical dies are assembled in the same wafer-level package to generate the target chip200.

According to a circuit module design configured by splitting a chip function of a target chip, identical smaller-sized dies, each having the same circuit module design, can be fabricated on a wafer (Step102). Compared to a die yield of larger-sized dies each having the chip function of the chip200and fabricated on a wafer, a die yield of smaller-sized dies each having the circuit module design and fabricated on the same wafer is higher due to reduced yield loss. Moreover, since a single mask of the circuit module design can be used to fabricate a plurality of identical dies, the mask cost can be saved greatly.

Since the desired chip function is split into multiple circuit designs each having the same circuit module design and each identical die is fabricated using the same circuit module design, multiple dies can be assembled to reconstruct the target chip with the desired chip function. In step104, multiple good dies are selected from the candidate dies fabricated on a wafer, where the number of selected good dies depends on the number of identical circuit module designs needed to reconstruct the desired chip function. In step106, the selected good dies are assembled in a wafer-level package to generate a target chip with the desired chip function. For example, the wafer-level package may be an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. With regard to assembling homogeneous dies in one wafer-level package, several exemplary assembly designs are provided as below.

FIG. 4is a section view of a wafer-level package according to an embodiment of the present invention. In this example, two dies402_1and402_2(e.g., identical dies) are assembled in the same wafer-level package400. The dies402_1and402_2are arranged on a wafer-level package in a side-by-side fashion. That is, the dies402_1and402_2are not vertically stacked. The die402_1has a plurality of input/output (I/O) pads403_1, and is mounted on a redistribution layer (RDL) or substrate404via bumps405_1. Similarly, the die402_2has a plurality of I/O pads403_2, and is mounted on the RDL/substrate404via bumps405_2. Further, the dies402_1and402_2can be connected by connection paths routed in the RDL/substrate404. For example, in a case where the InFO packaging technology is employed, the connection paths are implemented using InFO wires (e.g., Cu post passivation interconnections) that may act as the RDL routing. It should be noted that the package structure shown inFIG. 4is for illustrative purposes only, and is not meant to be a limitation of the present invention.

FIG. 5is a diagram illustrating a first assembly design of homogeneous dies according to an embodiment of the present invention. The sub-diagram (A) ofFIG. 5illustrates a single die A1having a plurality of I/O pads P1, P2, P3, P4on the right side RS. The I/O pads P1-P4are unidirectional, where the I/O pads P1and P4are output pads for transmitting output signals generated from output buffers (not shown) in the die A1, and I/O pads P2and P3are input pads for receiving input signals to be processed by input buffers (not shown) in the die A1. The sub-diagram (B) ofFIG. 5illustrates two identical dies502_1and502_2connected using RDL/substrate routing. The dies502_1and502_2may be a master-slave pair or a peer-to-peer pair. The single die A1shown in sub-diagram (A) ofFIG. 5may be fabricated according a circuit module design mentioned above. Hence, each of the dies502_1and502_2is identical to the single die A1. The dies502_1and502_2are arranged on a wafer-level package in a side-by-side fashion. In addition, a first side S1of the die502_1is adjacent to a first side S1of the die502_2, where each of the first side S1of the die502_1and the first side S1of the die502_2is the same side of an identical die (i.e., right side RS of single die A1). Hence, the orientation of the die502_2has a 180-degree rotation with respect to the orientation of the die502_1. As mentioned above, the I/O pads P1and P4are output pads, and the I/O pads P2and P3are input pads. In this example, the I/O pad P1of the die502_1is connected to the I/O pad P3of the die502_2via a connection path L1, the I/O pad P2of the die502_1is connected to the I/O pad P4of the die502_2via a connection path L2, the I/O pad P3of the die502_1is connected to the I/O pad P1of the die502_2via a connection path L3, and the I/O pad P4of the die502_1is connected to the I/O pad P2of the die502_2via a connection path L4. The connection paths between the dies502_1and502_2have crossing connection paths L1-L4routed on different layers, which increases the design complexity of the RDL/substrate routing. The present invention further proposes an innovative I/O design/arrangement for avoiding crossing connection paths between identical dies assembled in a wafer-level package.

FIG. 6is a diagram illustrating a second assembly design of homogeneous dies according to an embodiment of the present invention. The sub-diagram (A) ofFIG. 6illustrates a single die A2having a plurality of I/O pads P1′, P2′, P3′, P4′ on the right side RS. The I/O pads P1′-P4′ are bidirectional. Hence, each of the I/O pads P1′-P4′ can be configured to act as either an input pad (which is used for receiving an input signal to be processed by an input buffer (not shown) in the die A2) or an output pad (which is used for transmitting an output signal generated from an output buffer (not shown) in the die A2). The sub-diagram (B) ofFIG. 6illustrates two identical dies602_1and602_2connected using direct connection paths L1′, L2′, L3′, L4′. The dies602_1and602_2may be a master-slave pair or a peer-to-peer pair. The single die A2shown in sub-diagram (A) ofFIG. 6may be fabricated according a circuit module design mentioned above. Hence, each of the dies602_1and602_2is identical to the single die A2. The dies602_1and602_2are arranged on a wafer-level package in a side-by-side fashion. In addition, a first side S1of the die602_1is adjacent to a first side S1of the die602_2, where each of the first side S1of the die602_1and the first side S1of the die602_2is the same side of an identical die (i.e., right side RS of single die A2). Hence, the orientation of the die602_2has a 180-degree rotation with respect to the orientation of the die602_1. Since the I/O pads P1′-P4′ are bidirectional, the I/O pad P1′ of the die602_1is connected to the I/O pad P4′ of the die602_2via a direct connection path L1′, the I/O pad P2′ of the die602_1is connected to the I/O pad P3′ of the die602_2via a direct connection path L2′, the I/O pad P3′ of the die602_1is connected to the I/O pad P2′ of the die602_2via a direct connection path L3′, and the I/O pad P4′ of the die602_1is connected to the I/O pad P1′ of the die602_2via a direct connection path L4′. With the use of a bidirectional I/O design, adjacent I/O pads on the first side S1of the die602_1are connected to adjacent I/O pads on the first side S1of the die602_2via connection paths on only a single layer. For example, the connection paths between the dies602_1and602_2have no crossing connection paths routed via different layers, which can simplify the RDL/substrate routing greatly. It is noted that the I/O pads or the connection paths operate functionally, which are not dummy ones.

The assembly example shown inFIG. 6has only two identical dies each using a bidirectional I/O design. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Assembling more than two identical dies each using a bidirectional I/O design in a wafer-level package is feasible. Hence, different products (e.g., network switch products with different line rates) can be provided by assembling different numbers of homogeneous dies. In addition, the same objective of connecting adjacent I/O pads on one side of one die to adjacent I/O pads on one side of another die via connection paths on only a single layer is achieved. For example, routing crossing connection paths via different layers can be avoided.

FIG. 7is a diagram illustrating a third assembly design of homogeneous dies according to an embodiment of the present invention. The sub-diagram (A) ofFIG. 7illustrates a single die A3having a plurality of I/O pads P1′, P2′, P3′ on the right side RS and a plurality of I/O pads P4′, P5′, P6′ on the bottom side BS. The I/O pads P1′-P6′ are bidirectional. Hence, each of the I/O pads P1′-P6′ can be configured to act as either an input pad (which is used for receiving an input signal to be processed by an input buffer (not shown) in the die A3) or an output pad (which is used for transmitting an output signal generated from an output buffer (not shown) in the die A3). The sub-diagram (B) ofFIG. 7illustrates four identical dies702_1,702_2,702_3, and702_4connected via direct connection paths L1′-L12′. The single die A3shown in sub-diagram (A) ofFIG. 7may be fabricated according a circuit module design mentioned above. Hence, each of the dies702_1-702_4is identical to the single die A3. The dies702_1-702_4are arranged on a wafer-level package in a side-by-side fashion. By way of example, but not limitation, the dies702_1and702_2are aligned in an X-axis direction on a plane of the wafer-level package, the dies702_3and702_4are aligned in an X-axis direction on the plane of the wafer-level package, the dies702_1and702_4are aligned in a Y-axis direction on the plane of the wafer-level package, and the dies702_2and702_3are aligned in a Y-axis direction on the plane of the wafer-level package. In this way, the symmetric placement of the dies702_1-702_4on the wafer-level package makes the wafer-level package have a compact size.

In addition, a first side S1of the die702_1is adjacent to a first side S1of the die702_2, a first side S1of the die702_3is adjacent to a first side S1of the die702_4, a second side S2of the die702_1is adjacent to a second side S2of the die702_4, and a second side S2of the die702_2is adjacent to a second side S2of the die702_3, where the first side S1of the die702_1and the first side S1of the die702_2are different sides of an identical die (i.e., right side RS and bottom side BS of single die A3), the first side S1of the die702_3and the first side S1of the die702_4are different sides of the identical die (i.e., right side RS and bottom side BS of single die A3), the second side S2of the die702_2and the second side S2of the die702_3are different sides of the identical die (i.e., right side RS and bottom side BS of single die A3), and the second side S2of the die702_1and the second side S2of the die702_4are different sides of the identical die (i.e., bottom side BS and right side RS of the single die A3). Hence, the orientation of the die702_2has a 90-degree clockwise rotation with respect to the orientation of the die702_1, the orientation of the die702_3has a 90-degree rotation with respect to the orientation of the die702_2, the orientation of the die702_4has a 90-degree clockwise rotation with respect to the orientation of the die702_3, and the orientation of the die702_1has a 90-degree clockwise rotation with respect to the orientation of the die702_4. Since the I/O pads P1′-P6′ are bidirectional, direct connection paths L1′-L12′ can be used. With the use of a bidirectional I/O design, adjacent I/O pads on one side of one die are connected to adjacent I/O pads on one side of another die via connection paths on only a single layer. For example, the connection paths between any two of the dies702_1-702_4have no crossing connection paths routed via different layers, which can simplify the RDL/substrate routing greatly.

In above examples shown inFIG. 6andFIG. 7, direct connection paths can be used to connect identical dies due to a bidirectional I/O design employed by a circuit module design. Alternatively, direct connection paths can be used to connect identical dies by properly arranging the unidirectional I/O pads employed by a circuit module design.

FIG. 8is a diagram illustrating a fourth assembly design of homogeneous dies according to an embodiment of the present invention. The sub-diagram (A) ofFIG. 8illustrates a single die A4having a plurality of I/O pads P1, P2, P3, P4on the right side RS. The I/O pads P1-P4are unidirectional. The I/O pads P1and P2are output pads for transmitting output signals generated from output buffers (not shown) in the die A4. The I/O pads P3and P4are input pads for receiving input signals to be processed by input buffers (not shown) in the die A4. In this example, the I/O pads P1-P4on the right side RS of the die A4are rotationally symmetric. “Rotationally symmetric” means that the I/O pads of the non-rotated die A4exactly match the I/O pads of the die A4rotated by a specific rotation angle (e.g., 180 degrees). As shown in the sub-diagram (A) ofFIG. 8, the I/O pad P1matches the I/O pad P4after a 180-degree rotation, and the I/O pad P2matches the I/O pad P3after a 180-degree rotation. When the single die A4has a first orientation (e.g., 0-degree rotation), I/O pads arranged on a same side of the non-rotated die A4have a specific I/O pad definition from a top I/O pad to a bottom I/O pad. When the single die A4has a second orientation (e.g., 180-degree rotation), the I/O pad on a same side of the rotated die A4have the same specific I/O pad definition from a top I/O pad to a bottom I/O pad.

The sub-diagram (B) ofFIG. 8illustrates two identical dies802_1and802_2connected via direct connection paths L2′, L3′, L4′. For example, the dies802_1and802_2may be a master-slave pair or a peer-to-peer pair. The single die A4shown in sub-diagram (A) ofFIG. 8may be fabricated according a circuit module design mentioned above. Hence, each of the dies802_1and802_2is identical to the single die A4. The dies802_1and802_2are arranged on a wafer-level package in a side-by-side fashion. In addition, a first side S1of the die802_1is adjacent to a first side S1of the die802_2, where each of the first side S1of the die802_1and the first side S1of the die802_2is the same side of an identical die (i.e., right side RS of single die A4). Hence, the orientation of the die802_2has a 180-degree rotation with respect to the orientation of the die802_1.

Since the I/O pads P1-P4on the right side RS of the die A4are rotationally symmetric, the I/O pad P1of the die802_1is connected to the I/O pad P4of the die802_2via a direct connection path L1′, the I/O pad P2of the die802_1is connected to the I/O pad P3of the die802_2via a direct connection path L2′, the I/O pad P3of the die802_1is connected to the I/O pad P2of the die802_2via a direct connection path L3′, and the I/O pad P4of the die802_1is connected to the I/O pad P1of the die802_2via a direct connection path L4′. With the use of a rotationally symmetric I/O design, adjacent I/O pads on one side of one die are connected to adjacent I/O pads on one side of another die via connection paths on only a single layer. For example, the connection paths between the dies802_1and802_2have no crossing connection paths routed via different layers, which can simplify the RDL/substrate routing greatly.

The assembly example shown inFIG. 8has only two identical dies each using a rotationally symmetric I/O design. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Assembling more than two identical dies each using a rotationally symmetric I/O design in a wafer-level package is feasible. Hence, different products (e.g., network switch products with different line rates) can be provided by assembling different numbers of homogeneous dies. In addition, connecting adjacent I/O pads on one side of one die to adjacent I/O pads on one side of another die via connection paths on only a single layer can be achieved. For example, routing crossing connection paths via different layers can be avoided.

FIG. 9is a diagram illustrating a fifth assembly design of homogeneous dies according to an embodiment of the present invention. The sub-diagram (A) ofFIG. 9illustrates a single die A5having a plurality of I/O pads P1, P2, P3, P4on the right side RS and a plurality of I/O pads P5, P6, P7, P8on the bottom side BS. The I/O pads P1-P8are unidirectional. The I/O pads P1, P2, P5, P6are output pads for transmitting output signals generated from output buffers (not shown) in the die A5. The I/O pads P3, P4, P7, P8are input pads for receiving input signals to be processed by input buffers (not shown) in the die A5. In this example, the I/O pads P1-P4on the right side RS of the die A5are rotationally symmetric, and the I/O pads P5-P8on the bottom side BS are rotationally symmetric. As shown in the sub-diagram (A) ofFIG. 9, the I/O pad P1matches the I/O pad P4after a 180-degree rotation, the I/O pad P2matches the I/O pad P3after a 180-degree rotation, the I/O pad P5matches the I/O pad P8after a 180-degree rotation, and the I/O pad P6matches the I/O pad P7after a 180-degree rotation. Moreover, the I/O pads P1-P4on the right side RS are rotationally symmetric to the I/O pads P5-P8on the bottom side BS. As shown in the sub-diagram (A) ofFIG. 9, the I/O pad P1matches the I/O pad P5after a 90-degree rotation, the I/O pad P2matches the I/O pad P6after a 90-degree rotation, the I/O pad P3matches the I/O pad P7after a 90-degree rotation, and the I/O pad P4matches the I/O pad P8after a 90-degree rotation.

The sub-diagram (B) ofFIG. 9illustrates four identical dies902_1,902_2,902_3, and902_4connected via direct connection paths L1′-L16′. The single die A5shown in sub-diagram (A) ofFIG. 9may be fabricated according a circuit module design mentioned above. Hence, each of the dies902_1-902_4is identical to the single die A5. The dies902_1-902_4are arranged on a wafer-level package in a side-by-side fashion. Byway of example, but not limitation, the dies902_1and902_2are aligned in an X-axis direction on a plane of the wafer-level package, the dies902_3and902_4are aligned in an X-axis direction on the plane of the wafer-level package, the dies902_1and902_4are aligned in a Y-axis direction on the plane of the wafer-level package, and the dies902_2and902_3are aligned in a Y-axis direction on the plane of the wafer-level package. In this way, the symmetric placement of the dies902_1-902_4on the wafer-level package makes the wafer-level package have a compact size.

In addition, a first side S1of the die902_1is adjacent to a first side S1of the die902_2, a first side S1of the die902_3is adjacent to a first side S1of the die902_4, a second side S2of the die902_1is adjacent to a second side S2of the die902_4, and a second side S2of the die902_2is adjacent to a second side S2of the die902_3, where the first side S1of the die902_1and the first side S1of the die902_2are different sides of an identical die (i.e., right side RS and bottom side BS of single die A5), the first side S1of the die902_3and the first side S1of the die902_4are different sides of the identical die (i.e., right side RS and bottom side BS of single die A5), the second side S2of the die902_2and the second side S2of the die902_3are different sides of the identical die (i.e., right side RS and bottom side BS of single die A5), and the second side S2of the die902_1and the second side S2of the die902_4are different sides of the identical die (i.e., bottom side BS and right side RS of single die A5). Hence, the orientation of the die902_2has a 90-degree clockwise rotation with respect to the orientation of the die902_1, the orientation of the die902_3has a 90-degree rotation with respect to the orientation of the die902_2, the orientation of the die902_4has a 90-degree clockwise rotation with respect to the orientation of the die902_3, and the orientation of the die902_1has a 90-degree clockwise rotation with respect to the orientation of the die902_4. Since I/O pads P1-P4arranged on the right side RS of the die A5are rotationally symmetric, I/O pads P5-P8arranged on the bottom side BS of the die A5are rotationally symmetric and I/O pads P1-P4arranged on the right side RS of the die A5are rotationally symmetric to I/O pads P5-P8arranged on the bottom side BS of the die A5, direct connection paths L1′-L16′ can be used. With the use of a rotationally symmetric I/O design, adjacent I/O pads on one side of one die are connected to adjacent I/O pads on one side of another die via connection paths on only a single layer. For example, the connection paths between any two of the dies902_1-902_4have no crossing connection paths routed via different layers, which can simplify the RDL/substrate routing greatly.

In above examples shown inFIG. 8andFIG. 9, a rotationally symmetric I/O design is employed by a circuit module design, and direct connection paths can be used to connect identical dies each having the circuit module design by arranging the side-by-side identical dies in different orientations. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, direct connection paths can be used to connect the side-by-side identical dies in the same orientation by properly arranging I/O pads on opposite sides of a circuit module design.

FIG. 10is a diagram illustrating a sixth assembly design of homogeneous dies according to an embodiment of the present invention. The sub-diagram (A) ofFIG. 10illustrates a single die A6having a plurality of I/O pads P1, P2, P3, P4on the right side RS and a plurality of I/O pads P5, P6, P7, P8on the left side LS opposite to the right side RS. The I/O pads P1-P8are unidirectional. The I/O pads P1, P2, P3, P8are output pads for transmitting output signals generated from output buffers (not shown) in the die A6. The I/O pads P4, P5, P6, P7are input pads for receiving input signals to be processed by input buffers (not shown) in the die A6. In this example, the I/O pads P1and P5arranged on opposite sides of the die A6form a first side-to-side transmit/receive (Tx/Rx) pair, the I/O pads P2and P6arranged on opposite sides of the die A6form a second side-to-side Tx/Rx pair, the I/O pads P3and P7arranged on opposite sides of the die A6form a third side-to-side Tx/Rx pair, and the I/O pads P8and P4arranged on opposite sides of the die A6form a fourth side-to-side Tx/Rx pair.

The sub-diagram (B) ofFIG. 10illustrates three identical dies1002_1,1002_2, and1002_3connected via direct connection paths L1′-L8′. The single die A6shown in sub-diagram (A) ofFIG. 10may be fabricated according a circuit module design mentioned above. Hence, each of the dies1002_1-1002_3is identical to the single die A6. The dies1002_1-1002_3are arranged on a wafer-level package in a side-by-side fashion. In addition, a first side S1of the die1002_2is adjacent to a first side S1of the die1002_1, and a second side S2of the die1002_2is adjacent to a first side S1of the die1002_3, where the first side S1of the die1002_1and the first side S1of the die1002_2are different sides of an identical die (i.e., right side RS and left side LS of single die A6), and the second side S2of the die1002_2and the first side S1of the die1002_3are different sides of the identical die (i.e., right side RS and left side LS of single die A6). Since I/O pads P1-P4arranged on the right side RS of the die A6and I/O pads P5-P8arranged on the left side LS of the same die A6form a plurality of side-to-side Tx/Rx pairs, direct connection paths L1′-L4′ can be used between two identical dies1002_1and1002_2, and direct connection paths L5′-L8′ can be used between two identical dies1002_2and1002_3. It should be noted that the unused I/O pads can be tied to the ground. With the use of a side-to-side Tx/Rx I/O pair design, adjacent I/O pads on one side of one die are connected to adjacent I/O pads on one side of another die via connection paths on only a single layer. For example, the connection paths between any two of the dies1002_1-1002_3have no crossing connection paths routed via different layers, which can simplify the RDL/substrate routing greatly.

If I/O pads on the same side of an identical die are arranged in multiple rows, the present invention further proposes configuring the connection paths between two identical dies properly to make the difference between connection paths small.FIG. 11is a diagram illustrating a seventh assembly design of homogeneous dies according to an embodiment of the present invention. A wafer-level package has two identical dies1102_1and1102_2arranged in a side-by-side fashion, wherein a first side S1of the die1102_1is adjacent to a first side of the die1102_2, and each of the first side S1of the die1102_1and the first side S1of the die1102_1is the same side of an identical die. As shown inFIG. 11, the die1102_1is a non-rotated version of an identical die, and the die1102_2is a rotated version of the identical die. In this example, a Tx/Rx multi-row I/O design is employed by each identical die. Hence, the I/O pads on the first side S1of the die1102_1are arranged in multiple rows including at least an inner row1104_1and an outer row1106_1, where the outer row1106_1is closer to an edge of the first side S1of the die1102_1than the inner row1104_1. In addition, the I/O pads on the first side S1of the die1102_2are arranged in multiple rows including at least an inner row1104_2and an outer row1106_2, where the outer row1106_2is closer to an edge of the first side S1of the die1102_2than the inner row1104_2. For example, I/O pads of the same inner row1104_1/1104_2are all input pads, and I/O pads of the same outer row1106_1/1106_2are all output pads.

For another example, I/O pads of the same inner row1104_1/1104_2are all output pads, and I/O pads of the same outer row1106_1/1106_2are all input pads. As shown inFIG. 11, first connection paths L11, L12, L13, L14are used to connect I/O pads arranged in the inner row1104_1to I/O pads arranged in the outer row1106_2, respectively; and second connection paths L21, L22, L23, L24are used to connect I/O pads arranged in the outer row1106_1to I/O pads arranged in the inner row1104_2, respectively. In this example, all of first connection paths L11-L14and second connection paths L21-L24are configured to have the same wire length. It should be noted that the Tx/Rx multi-row I/O design is not limited to identical dies assembled in the same wafer-level package to generate a target chip. For example, the dies1102_1and1102_2may be distinct dies in an alternative design.

FIG. 12is a diagram illustrating an eighth assembly design of homogeneous dies according to an embodiment of the present invention. A wafer-level package has two identical dies1202_1and1202_2arranged in a side-by-side fashion, wherein a first side S1of the die1202_1is adjacent to a first side of the die1202_2, and each of the first side S1of the die1202_1and the first side S1of the die1202_1is the same side of an identical die. As shown inFIG. 12, the die1202_1is a non-rotated version of an identical die, and the die1202_2is a rotated version of the identical die. In this example, a Tx/Rx multi-row I/O design is employed by each identical die. Hence, the I/O pads on the first side S1of the die1202_1are arranged in multiple rows including at least an inner row1204_1and an outer row1206_1, where the outer row1206_1is closer to an edge of the first side S1of the die1202_1than the inner row1204_1. The I/O pads on the first side S1of the die1202_2are arranged in multiple rows including at least an inner row1204_2and an outer row1206_2, where the outer row1206_2is closer to an edge of the first side S1of the die1202_2than the inner row1204_2. The I/O pads of the same inner row1204_1/1204_2include input pads and output pads, and the I/O pads of the same outer row1206_1/1206_2include input pads and output pads.

For example, the upper two I/O pads of the same row are input pads, and the lower two I/O pads of the same row are output pads. For another example, the upper two I/O pads of the same row are output pads, and the lower two I/O pads of the same row are input pads. As shown inFIG. 12, first connection paths L11, L12, L13, L14are used to connect I/O pads arranged in the inner row1204_1to I/O pads arranged in the outer row1206_2, respectively; and second connection paths L21, L22, L23, L24are used to connect I/O pads arranged in the outer row1206_1to I/O pads arranged in the inner row1204_2, respectively. In this example, all of first connection paths L11-L14and second connection paths L21-L24are configured to have the same wire length. It should be noted that the Tx/Rx multi-row I/O design is not limited to identical dies assembled in the same wafer-level package to generate a target chip. For example, the dies1202_1and1202_2may be distinct dies in an alternative design.

In above examples, multiple dies assembled in a wafer-level package are homogeneous dies (i.e., identical dies) only. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, multiple dies assembled in a wafer-level package can include heterogeneous dies (i.e., distinct dies). That is, any wafer-level package using the proposed I/O pad design/arrangement (e.g., bidirectional I/O design, rotationally symmetric I/O design, or side-to-side Tx/Rx I/O pair design) to connect adjacent I/O pads on one side of one die to adjacent I/O pads on one side of another die via connection paths on only a single layer falls within the scope of the present invention. For example, any wafer-level package using the proposed I/O pad design/arrangement (e.g., bidirectional I/O design, rotationally symmetric I/O design, or side-to-side Tx/Rx I/O pair design) to avoid using crossing connection paths between side-by-side dies falls within the scope of the present invention.

The yield improvement method shown inFIG. 1is employed to generate a target chip by assembling multiple identical dies in a same wafer-level package. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. Alternatively, a target chip may be generated by assembling multiple dies in a same wafer-level package, where the multiple dies may have identical dies and at least one distinct die.FIG. 13is a flowchart illustrating a second yield improvement method according to an embodiment of the present invention. Provided that the result is substantially the same, the steps are not required to be executed in the exact order shown inFIG. 13. In addition, certain steps may be added to or removed from the flow shown inFIG. 13. The exemplary yield improvement method may be briefly summarized as below.

Step1302: Provide a plurality of first candidate dies each having the same first circuit module design.

Step1304: Provide a plurality of second candidate dies each having the same second circuit module design, where the second circuit module is distinct from the first circuit module design. For example, a chip function of a target chip is split into first circuit designs each having the same first circuit module design and at least one second circuit design each having the same second circuit module design.

Step1306: Select a plurality of first good dies from the first candidate dies.

Step1308: Select at least one second good die from the second candidate dies.

Step1310: Generate the target chip by assembling the selected first good dies and the selected at least one second good die in a wafer-level package.

By way of example, but not limitation, all of the steps1302-1310may be performed in the same semiconductor foundry. Since the fabrication of large-sized dies on a wafer suffers from low yield and high cost, the present invention therefore proposes splitting a chip function of a target chip into a plurality of circuit designs, including first circuit designs each having the same first circuit module design and at least one second circuit design each having the same second circuit module design.

Please refer toFIG. 2in conjunction withFIG. 14.FIG. 14is a diagram illustrating an example of splitting a chip function of a target chip into two identical circuit designs and one distinct circuit design. As shown inFIG. 14, the chip function of the target chip200inFIG. 2is split into three circuit designs1402,1404_1and1404_2, where each of the circuit designs1404_1and1404_2has a first circuit module design, and the circuit design1402has a second circuit module design distinct from the first circuit module design. In this embodiment, the first circuit module design is designed to have two function blocks with the same function F2, and is further designed to have an extra input/output (I/O) function1403due to partition overhead needed for reconstructing a chip with the desired chip function in a wafer-level package; and the second circuit module design is designed to have one functional block with the function F1, and is further designed to have an extra input/output (I/O) function1405due to partition overhead needed for reconstructing a chip with the desired chip function in a wafer-level package. It should be noted that, if the circuit design1404_2is rotated by 180 degrees, the circuit design1404_2exactly matches the circuit design1404_1due to the fact that both of the circuit designs1404_1and1404_2have the same first circuit module design.

According to a circuit module design configured by splitting a chip function of a target chip, identical smaller-sized dies, each having the first circuit module design, can be fabricated on one wafer (Step1302), and identical smaller-sized dies, each having the second circuit module design, can be fabricated on another wafer (Step1304). Compared to a die yield of larger-sized dies each having the chip function of the chip200, a die yield of smaller-sized dies each having the first circuit module design and a die yield of smaller-sized dies each having the second circuit module design are both higher due to reduced yield loss.

Since the desired chip function is split into multiple circuit designs, multiple dies can be combined to reconstruct the target chip with the desired chip function. In step1306, first good dies are selected from the first candidate dies fabricated on a wafer, where the number of selected first good dies depends on the number of first circuit module designs needed to reconstruct the desired chip function. In step1308, at least one second good die is selected from the second candidate dies fabricated on a wafer, where the number of selected second good dies depends on the number of second circuit module designs also needed to reconstruct the desired chip function. In step1310, the selected first good dies and the selected at least one second good die are assembled in a wafer-level package to generate a target chip with the desired chip function. For example, the wafer-level package may be an integrated fan-out (InFO) package or a chip on wafer on substrate (CoWoS) package. With regard to assembling heterogeneous dies in one wafer-level package, several exemplary assembly designs are provided as below.

FIG. 15is a diagram illustrating a first assembly design of heterogeneous dies according to an embodiment of the present invention. In this example, a wafer-layer package has three dies1502,1504_1, and1504_2arranged in a side-by-side fashion, where the die1504_1is identical to the die1504_2, and the die1502is distinct from each of the dies1504_1and1504_2. For example, the die1504_1may be fabricated according to the second circuit module design illustrated inFIG. 14, and each of the dies1504_1and1504_2may be fabricated using the first circuit module design illustrated inFIG. 14. There are connection paths (e.g., direct connection paths) configured to connect I/O pads arranged on a first side S1of the dies1502to I/O pads arranged on a first side S1of the die1504_1. In addition, there are connection paths (e.g., direct connection paths) configured to connect I/O pads arranged on a second side S2of the dies1502to I/O pads arranged on a first side S1of the die1504_2. In this example, each of the first side S1of the die1504_1and the first side S1of the die1504_2is the same side of an identical die. Hence, the I/O pad design on the first side S1of the die1502is rotationally symmetric to the I/O pad design on the second side S2of the die1502.

The assembly example shown inFIG. 15has only two identical dies connected to a distinct die. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. For example, different products (e.g., network switch products with different line rates) can be provided by different combinations of heterogeneous dies. Hence, assembling more than two identical dies and at least one distinct die in a wafer-level package is feasible.

FIG. 16is a diagram illustrating a second assembly design of heterogeneous dies according to an embodiment of the present invention. In this example, a wafer-layer package has five dies1602,1604_1,1604_2,1604_3,1604_4arranged in a side-by-side fashion, where the dies1604_1-1604_4are identical dies, and the die1602is distinct from each of the dies1604_1-1604_4. For example, the die1604_1may be fabricated according to the second circuit module design illustrated inFIG. 14, and each of the dies1604_1-1604_4may be fabricated using the first circuit module design illustrated inFIG. 14. Since more identical dies are used, a target chip generated from assembling these dies1602and1604_1-1604_4can support more processing capabilities. In other words, different products (e.g., network switch products with different line rates) can be provided by assembling different numbers of heterogeneous dies (which include identical dies and at least one distinct die).

As mentioned above, a chip function of a target chip can be split into a plurality of circuit designs. For example, each of the circuit designs may be identical to a same circuit module design. For another example, the circuit designs may include first circuit designs each having a first circuit module design and at least one second circuit design each having a second circuit module design. It is possible that certain logic in a target chip is not evenly separated into multiple identical dies. After the identical dies are assembled to generate a target chip, one of the assembled identical dies may have a logic circuit that will be enabled to achieve the chip function of the target chip, and the rest of the assembled identical dies may have duplicate(s) of the logic circuit that may be treated as redundant circuit(s).

FIG. 17is diagram illustrating a network switch realized using a single die according to an embodiment of the present invention.FIG. 18is a diagram illustrating a network switch realized using two identical dies according to an embodiment of the present invention. As shown inFIG. 17, the network switch has logic circuits1702,1704,1706, and1708that are not evenly distributed. As shown inFIG. 18, a circuit module design of an identical die encompasses these logic circuits1702-1708. When two identical dies Die_0and Die_1, each having the same circuit module design, are assembled in a wafer-level package, a duplicate of the logic circuits1702-1708in one die (e.g., Die_1) is a redundant part that will not be enabled during a normal operation of the network switch. That is, if a chip function of a target chip is not evenly split into two identical dies, at least one of the function blocks in one or more identical die is treated as a redundant block after multiple identical dies are assembled in the same wafer-level package to generate the target chip. However, if a chip function of a target chip is evenly split into two identical dies, none of the function blocks in each identical die is treated as a redundant block after two identical dies are assembled in the same wafer-level package to generate the target chip.

When a network switch chip is realized using multiple dies assembled in a wafer-level package, a larger number of cross-die signals may become a problem.FIG. 19is a diagram illustrating a network switch according to an embodiment of the present invention. The network switch1900includes a packet switching circuit1902arranged to receive a packet received from one of N Ethernet ingress ports and forward the received packet to one of N Ethernet egress ports. As a result, the packet switching circuit1902needs a complicated switch fabric. If the packet switching function of the packet switching circuit1902is split into multiple dies, a large number of connection paths between any two dies assembled in a wafer-level package is needed.

To simply the switch fabric of a packet switching circuit, a time-division multiplexing (TDM) technique may be employed by a network switch to transmit and receive independent signals over a common signal path.FIG. 20is a diagram illustrating another network switch according to an embodiment of the present invention. For clarity and simplicity, it is assumed that the N Ethernet ingress ports are divided into two groups, and the N Ethernet egress ports are also divided into two groups. The network switch2000includes two packet switching circuits2002_1and2002_2, two ingress packet multiplexers2004_1and2004_2, and two egress packet multiplexers2006_1and2006_2. The ingress packet multiplexer2004_1is arranged to receive a packet received from one of Ethernet ingress port 0 to Ethernet ingress port K, and forward the received packet to one of the packet switching circuits2002_1and2002_2. For example, if a packet forwarding decision indicates that the received packet is required to be forwarded to one of Ethernet egress port 0 to Ethernet egress port K, the ingress packet multiplexer2004_1outputs the received packet to the packet switching circuit2002_1. Next, the packet switching circuit2002_1forwards the received packet to one of Ethernet egress port 0 to Ethernet egress port K via the egress packet multiplexer2006_1. For another example, if a packet forwarding decision indicates that the received packet is required to be forwarded to one of Ethernet egress port (K+1) to Ethernet egress port (N−1), the ingress packet multiplexer2004_1outputs the received packet to the packet switching circuit2002_2. Next, the packet switching circuit2002_2forwards the received packet to one of Ethernet egress port (K+1) to Ethernet egress port (N−1) via the egress packet multiplexer2006_2. Since the operation of the ingress packet multiplexer2004_2is similar to that of the ingress packet multiplexer2004_1, further description is omitted here for brevity.

The ingress packet multiplexers2004_1,2004_2and egress packet multiplexers2006_1,2006_2are used to support a TDM feature which transmits and receives independent signals over a common signal path. As shown inFIG. 20, the ingress packet multiplexer2004_1receives ingress packets from Ethernet ingress port 0 to Ethernet ingress port K, and communicates with any of the packet switching circuits2002_1and2002_2via a single signal path; and the ingress packet multiplexer2004_2receives ingress packets from Ethernet ingress port (K+1) to Ethernet ingress port (N−1), and communicates with any of the packet switching circuits2002_1and2002_2via a single signal path. Moreover, the egress packet multiplexer2006_1transmits egress packets to Ethernet egress port 0 to Ethernet egress port K, and communicates with the packet switching circuit2002_1via a single signal path; and the egress packet multiplexer2006_2transmits egress packets to Ethernet ingress port (K+1) to Ethernet ingress port (N−1), and communicates with the packet switching circuit2002_2via a single signal path.

The chip function of the network switch2000can be split into two dies as illustrated by the broken lines shown inFIG. 20. The first die Die_0and the second die Die_1may be arranged in a side-by-side fashion, where a first side S1of the first die Die_0is adjacent to a first side S1of the second die Die_1. Since the TDM technique is implemented in each of the first die Die_0and the second die Die_1, the number of cross-die signals can be significantly reduced. In this example, the I/O pads arranged on the first side S1of the first die Die_0have an output pad2008_1for transmitting an output of the ingress packet multiplexer2004_1, and further have an input pad2009_1for receiving an output of the ingress packet multiplexer2004_2and transmitting the output of the ingress packet multiplexer2004_2to the packet switching circuit2002_1. In addition, the I/O pads arranged on the first side S1of the second die Die_1have an output pad2008_2for transmitting the output of the ingress packet multiplexer2004_2, and further have an input pad2009_2for receiving the output of the ingress packet multiplexer2004_1and transmitting the output of the ingress packet multiplexer2004_1to the packet switching circuit2002_2. As shown inFIG. 20, two connection paths2010_1and2010_2are needed for packet transaction between two dies Die_0and Die_1.

In this example shown inFIG. 20, the chip function of the network switch2000is split into two dies. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. In an alternative design, splitting the chip function of the network switch2000into more than two dies is feasible. For example, N Ethernet ingress ports can be divided into M groups, and N Ethernet egress ports can be divided into M groups, where M is an integer larger than 2. In addition, M ingress packet multiplexers, M packet switching circuits, and M egress packet multiplexers are used. Hence, the chip function of the network switch2000can be split into M dies each having one ingress packet multiplexer, one packet switching circuit and one egress packet multiplexer. It should be noted that the same objective of reducing the number of cross-die signals is achieved due to the M ingress packet multiplexers preceding the M packet switching circuits.

FIG. 21is a diagram illustrating yet another network switch according to an embodiment of the present invention. For clarity and simplicity, it is assumed that the N Ethernet ingress ports are divided into two groups, and the N Ethernet egress ports are divided into two groups. The network switch2100includes two packet switching circuits2102_1and2102_2, two ingress packet multiplexers2104_1and2104_2, and two egress packet multiplexers2106_1and2106_2. The ingress packet multiplexer2104_1is arranged to receive a packet received from one of Ethernet ingress port 0 to Ethernet ingress port K, and outputs the received packet to the packet switching circuit2102_1. If a packet forwarding decision indicates that the received packet is required to be forwarded to one of Ethernet egress port 0 to Ethernet egress port K, the packet switching circuit2102_1outputs the received packet to the egress packet multiplexer2106_1, and the received packet is forwarded to a target Ethernet egress port via the egress packet multiplexer2106_1. If a packet forwarding decision indicates that the received packet is required to be forwarded to one of Ethernet egress port (K+1) to Ethernet egress port (N−1), the packet switching circuit2102_1outputs the received packet to the egress packet multiplexer2106_2, and the received packet is forwarded to a target Ethernet egress port via the egress packet multiplexer2106_2. Since the operation of the packet switching circuit2102_2is similar to that of the packet switching circuit2102_2, further description is omitted for brevity.

The ingress packet multiplexers2004_1,2004_2and egress packet multiplexers2006_1,2006_2are used to support a TDM feature which transmits and receives independent signals over a common signal path. As shown inFIG. 21, the ingress packet multiplexer2104_1receives ingress packets from Ethernet ingress port 0 to Ethernet ingress port K, and communicates with the packet switching circuit2102_1via a single signal path; and the ingress packet multiplexer2104_2receives ingress packets from Ethernet ingress port (K+1) to Ethernet ingress port (N−1), and communicates with the packet switching circuit2102_2via a single signal path. Moreover, the egress packet multiplexer2106_1transmits egress packets to Ethernet egress port 0 to Ethernet egress port K, and communicates with any of the packet switching circuits2102_1and2102_2via a single signal path; and the egress packet multiplexer2106_2transmits egress packets to Ethernet ingress port (K+1) to Ethernet ingress port (N−1), and communicates with any of the packet switching circuits2102_1and2102_2via a single signal path.

The chip function of the network switch2100can be split into two dies as illustrated by the broken lines shown inFIG. 21. The first die Die_0and the second die Die_1may be arranged in a side-by-side fashion, where a first side S1of the first die Die_0is adjacent to a first side S1of the second die Die_1. Since the TDM technique is implemented in each of the first die Die_0and the second die Die_1, the number of cross-die signals can be significantly reduced. In this example, the I/O pads arranged on the first side S1of the first die Die_0have an output pad2108_1for transmitting an output of the packet switching circuit2102_1, and further have an input pad2109_1for receiving an output of the packet switching circuit2102_2and transmitting the output of the packet switching circuit2102_2to the egress packet multiplexer2106_1. In addition, the I/O pads arranged on the first side S1of the second die Die_1have an output pad2108_2for transmitting the output of the packet switching circuit2102_2, and further have an input pad2109_2for receiving the output of the packet switching circuit2102_1and transmitting the output of the packet switching circuit2102_1to the egress packet multiplexer2106_2. As shown inFIG. 21, two connection paths2110_1and2110_2are needed for packet transaction between two dies Die_0and Die_1.

In this example shown inFIG. 21, the chip function of the network switch2100is split into two dies. However, this is for illustrative purposes only, and is not meant to be a limitation of the present invention. In an alternative design, splitting the chip function of the network switch2100into more than two dies is feasible. For example, N Ethernet ingress ports can be divided into M groups, and N Ethernet egress ports can be divided into M groups, where M is an integer larger than 2. In addition, M ingress packet multiplexers, M packet switching circuits, and M egress packet multiplexers are used. Hence, the chip function of the network switch2100can be split into M dies each having one ingress packet multiplexer, one packet switching circuit and one egress packet multiplexer. It should be noted that the same objective of reducing the number of cross-die signals is achieved due to the M egress packet multiplexers following the M packet switching circuits.