Quadrangle MOS transistors

A quadrangle transistor unit includes four transistor units. Each of the four transistor units includes a gate electrode. The gate electrodes of the four transistor units are aligned to four sides of a square. At least two of the four transistor units are connected in parallel.

TECHNICAL FIELD

This disclosure relates generally to transistors, and more particularly to the design of quadrangle metal-oxide-semiconductor (MOS) transistors having symmetric layouts.

BACKGROUND

Parallel implementations are often used in high-current applications and high-frequency applications. To achieve high drive currents, metal-oxide-semiconductor (MOS) transistors are connected in parallel to form a single transistor, with the gates interconnected with each other, sources interconnected with each other, and drains interconnected with each other.

FIGS. 1 through 3illustrate several commonly used parallel implementations, wherein gate electrodes of MOS transistors are parallel to each other. In each ofFIGS. 1 through 3, letters “G” represent gates, letters “S” represent sources, and letters “D” represent drains.FIG. 1illustrates an implementation with the active regions (including respective sources S and drains D) of the individual MOS transistors physically separated from each other.FIG. 2illustrates an implementation wherein each of sources S and drains D may be shared by two neighboring MOS transistors, and the MOS transistors are aligned to a single direction.FIG. 3illustrates an implementation wherein each of sources S and drains D may be shared by two neighboring MOS transistors, and the MOS transistors are arranged into an array. It was observed that these implementations suffer from various drawbacks. For example, the implementation shown inFIG. 1suffers from poly (gate electrode) loading effect, and the critical dimensions of the poly gates are difficult to control. The poly gate electrodes may be wider at the middle and narrower at ends. Further, the IR drop in implementations shown inFIGS. 1 and 2may be high due to long metal lines required to interconnect gates, sources, and drains. The implementations shown inFIGS. 2 and 3may further suffer from length of diffusion (LOD) problems.

In addition to the above-described drawbacks, due to the asymmetric layouts, it is difficult to construct models for the implementations shown inFIGS. 1 through 3. The reason is that the behavior of these MOS transistors not only changes with the number of individual MOS devices connected in parallel, but also changes with the gate widths.

SUMMARY

In accordance with one aspect, a quadrangle transistor unit includes four transistor units. Each of the four transistor units includes a gate electrode. The gate electrodes of the four transistor units are aligned to four sides of a square. At least two of the four transistor units are connected in parallel.

Other embodiments are also disclosed.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

Novel parallel implementations of metal-oxide-semiconductor (MOS) transistors are provided in accordance with various embodiments. The variations of the embodiments are then discussed. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. Throughout the description, when two transistors are referred to as being electrically coupled/connected in parallel, the gates of the transistors are electrically coupled/connected to each other, the sources of the transistors are electrically coupled/connected to each other, and the drains of the transistors are coupled to each other.

FIG. 4A through 4Dillustrate layouts of quadrangle transistor units10in accordance with various embodiments. Throughout the description, the term “quadrangle transistor unit” refers to the combination of four transistor units (for example, transistors T1through T4), each including a gate electrode (for example, G1through G4) over an active region (marked as OD1through OD4). No additional transistors are formed in the region defined by the four transistor units. Gate electrodes G1and G2of transistor units T1and T2are parallel to each other, and perpendicular to gate electrodes G3and G4of transistor units T3and T4. Gate electrodes G1through G4of transistor units T1through T4may be all interconnected physically to form a closed loop, as shown inFIG. 4A. Alternatively, as shown inFIG. 4C, gate electrodes G1and G4may be interconnected, and disconnected from gate electrodes G2and G3, which are also interconnected with each other. However, gate electrodes G1and G4may be electrically coupled to, or electrically decoupled from, gate electrodes G2and G3. Regardless of whether gate electrodes G1through G4are physically and/or electrically connected, they are aligned to a square shaped (or rectangular shaped) ring R (as marked inFIGS. 4C and 4D), which is illustrated using dotted lines. Further, active regions OD1through OD4may be formed in insulation regions12, which may be shallow trench isolation (STI) regions. The electrical connection of gate electrodes, sources, and drains of transistor units T1through T4may be achieved using contact plugs and metal lines, which are not shown inFIGS. 4A through 4D.FIG. 6, however, schematically illustrates the connections using dotted lines ML.

The sources of two or more transistor units in transistor units T1through T4may be interconnected. The drains of two or more transistor units may be interconnected. Accordingly, quadrangle transistor unit10may form a single transistor with all four transistor units T1through T4connected in parallel, as shown inFIGS. 4A and 4B. Alternatively, as shown inFIG. 4C, transistor units T1and T4may be connected in parallel, and transistor units T2and T3may be connected in parallel. However, transistor units T1and T4may be disconnected from transistors T2and T3. Similarly, inFIG. 4D, all four transistor units T1through T4may be electrically connected in parallel, or parallel connected in pairs.

In the embodiments shown inFIGS. 4A through 4C, the portions of active regions inside the squares formed of gate electrodes G1through G4may form a common source or a common drain. Further, width W of gate electrodes may be smaller than the distance between gate electrodes G1and G2(or between G3and G4). Accordingly, the common source or common drain may have a shape of a cross in a top view, with insulation regions12filling rest of the areas that are in the squares and are not occupied by the common source/drain. Width W of the common source/drain may be equal to, but not greater than, the distances between gate electrodes G1and G2(or G3and G4). In other words, the common source/drains may not extend to directly underlying the respective gate electrodes G1through G4, and may not extend to the corners of the square formed of gate electrodes G1through G4.

The embodiments may be low-voltage transistors or high-voltage transistors. For example, referring toFIGS. 5A and 5B, high-voltage quadrangle transistor unit10includes four gate electrodes forming a square, wherein each of the four transistor units T1through T4is a high-voltage transistor. A common source S is formed in the square, while drains D1through D4are formed outside of the square.FIG. 5Billustrates a cross-sectional view obtained from the plan crossing line5B-5B inFIG. 5A. It is observed that due to the formation of insulation region12, the drain-to-gate voltage is increased.FIG. 5Bonly illustrates an exemplary implementation of the high-voltage transistors, and other applicable implementations such as double diffused drain (DDD) are also in the scope of the present disclosure. Further, high-voltage quadrangle transistor unit10may also be implemented using essentially the same schemes as shown in any ofFIGS. 4B through 4D.

Quadrangle transistor units may form a quadrangle transistor array, as shown inFIG. 6. In this embodiment, all transistor units throughout the array may be connected/coupled in parallel to form a single transistor have a high drive current, or may be disconnected from each other. The interconnection may be achieved through metal lines ML in metallization layers (not shown). Depending on the required drive current, the array may be expanded to add more columns and/or rows of quadrangle transistor units. Similarly, the embodiments shown inFIGS. 4B through 4Dmay also be used to form quadrangle transistor unit arrays.

FIGS. 7A and 7Billustrate a circuit diagram and a layout, respectively, of inverter20. Inverter20includes NMOS transistor TN and PMOS transistor TP. Referring toFIG. 7B, quadrangle transistor unit22implements inverter20, with gate electrodes G1and G3being used to form NMOS transistor TN, and gate electrodes G2and G4being used to form PMOS transistor TP. Further, gate electrodes G1through G4form a close-loop ring, although NMOS transistor TN and PMOS transistor TP may also be implemented using the schemes shown inFIGS. 4B through 4D. The input of inverter20is connected to gate electrodes G1through G4, and the output is connected to the common drain formed inside the gate electrode ring. PMOS transistor TP may be formed in an N-well, while NMOS transistor TN may be formed in a P-well or a P-substrate. The active regions of PMOS transistor TP and NMOS transistor TN in the ring are adjacent to, and may contact, each other, and contact plug Cout may be landed on the active regions of both PMOS transistor TP and NMOS transistor TN, which active regions are in the gate electrode ring. Contact plug Cout is the output of inverter20. Again, inFIG. 7B, although gate electrodes G1through G4are shown as forming adopting the scheme as shown inFIG. 4A, the schemes as shown inFIGS. 4B through 4Dmay also be adopted.

FIGS. 8B and 8Cillustrate the layouts of differential transistor pair TA and TB. The circuit diagram is shown inFIG. 8A. Drains DA and DB of Differential transistor pair TA and TB are interconnected. As shown inFIG. 8B, quadrangle transistor unit30implements differential transistor pair TA and TB. Transistor TA is formed of transistor units T1and T3, while transistor TB is formed of transistor units T2and T4. The common source SS is placed in the square formed of gate electrodes, while drains DA and DB are formed outside of the square.FIG. 8Cillustrates an array formed of four quadrangle transistor units30, which are connected in parallel, meaning transistors TA of quadrangle transistor units30are connected in parallel, and transistors TB of quadrangle transistor units30are connected in parallel.

FIGS. 9B and 9Cillustrate layouts of a cross-coupled transistor pair TC and TD. The respective circuit diagram is shown inFIG. 9A.FIG. 9Billustrates quadrangle transistor unit40that implements cross-coupled pair TC and TD. Transistor TC is formed of transistor units T1and T3, while transistor TD is formed of transistor units T2and T4. The common source SS is again placed in the square formed of gate electrodes, while drains DC and DD are formed outside of the square. The cross-connection of gates and drains are illustrated using dotted lines.FIG. 9Cillustrates an array formed of four quadrangle transistor units40, which are connected in parallel to form a single cross-coupled transistor pair.

FIGS. 10B and 10Cillustrate layouts of a cascaded transistor pair TE and TF, with the source of transistor TE connected to the drain of transistor TF. The respective circuit diagram is shown inFIG. 10A. As shown inFIG. 10B, quadrangle transistor unit50implements cascaded transistor pair TE and TF. Transistor TE is formed of transistor units T1and T3, while transistor TF is formed of transistor units T2and T4. Active region CSD in the square represents the source of transistors TE and the drain of transistor TF, while drain D of transistors TE and source S of transistor TF are formed outside of the square.FIG. 10Cillustrates an array formed of four quadrangle transistor units50, which are connected in parallel to form a single cascaded transistor pair.

In the embodiments, although gate electrodes of quadrangle transistor units are referred to as forming squares or aligned to sides of the squares, the gate electrodes of the quadrangle transistor units may also form rectangles with lengths not equal to widths, or aligned to the sides of the rectangles.

In the embodiments, instead of aligning gate electrodes parallel to each other, gate electrodes in quadrangle transistor units form a square. Accordingly, all four gate electrodes may have a same symmetric environment, all four sources may have a same symmetric environment, and all four drains may have a same symmetric environment. This results in the reduction in the adverse effects related to length of diffusion (LOD), mask misalignment, optical proximity, and the like. Further, the modeling becomes simpler and more accurate with the implementation of quadrangle transistor units.