SUBSTRATES WITH DOWNSET

A variety of applications can include systems with packaged electronic devices having multiple dies arranged on a substrate with a downset design. A substrate with a downset design can include an upper portion and a lower portion with a downset portion connecting the upper portion to the lower portion. The downset portion can include through vias to provide conductive paths between the lower portion and the upper portion. Dies can be positioned with a region defined by walls of the downset portion with a non-conductive film covering the dies in the region defined by walls of the downset portion. Additional dies can be positioned on the non-conductive film and the upper portion of the substrate. A packaged electronic device having a substrate with a downset design can be implemented to raise the neutral axis of the packaged electronic device to near the top surface of the dies.

FIELD OF THE DISCLOSURE

Embodiments of the disclosure relate generally to electronic devices and, more specifically, to structures for semiconductor device packages and formation thereof.

BACKGROUND

Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data, and includes random-access memory (RAM), dynamic random-access memory (DRAM), static RAM (SRAM), or synchronous dynamic random-access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory, such as phase-change random-access memory (PCRAM), resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), or three-dimensional (3D) XPoint™ memory, among others. Operation and properties of memory devices and other electronic devices can be improved by enhancements to the design of packaging of electronic devices such as, but not limited to, semiconductor device packages for multiple dies.

DETAILED DESCRIPTION

The following detailed description refers to the accompanying drawings that show, by way of illustration, various embodiments that can be implemented. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice these and other embodiments. Other embodiments can be utilized, and structural, logical, mechanical, and electrical changes can be made to these embodiments. The term “horizontal” as used in this application is defined as a plane parallel to a conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Various features can have a vertical component to the direction of their structure. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. The following detailed description is, therefore, not to be taken in a limiting sense.

FIG.1is a cross-sectional representation of a packaged electronic device100having multiple dies supported by a package substrate105. Dies110-1,110-2,110-3,110-4, and110-5form a first set of dies; dies115-1,115-2,115-3, and115-4form a second set of dies; and dies115-5,115-6,115-7, and115-8form a third set of dies, where the three sets of dies are arranged for support extending from substrate105. The sets of dies can be arranged in a level manner; that is, the dies can be arranged parallel to package substrate105. Die110-1is positioned on substrate105by contacts118, with dies110-2,110-3,110-4, and110-5positioned on dic110-1. Contacts118can be, but are not limited to, a ball grid array. Die110-2can be separated from die110-1by a region111-1. Die110-3can be separated from die110-2by a region111-2. Die110-4can be separated from die110-3by a region111-3. Die110-5can be separated from die110-4by a region111-4. Each of regions111-1,111-2,111-3, and111-4can include a backing of the respective die, an adhesive, a die-attach-film (DAF), or a paste, among other materials.

The second set of dies are positioned on and supported by a spacer103-1, which can be a silicon spacer. Die115-1can be separated from a top surface of spacer103-1by a region116-1. Die115-2can be separated from die115-1by a region116-2. Die115-3can be separated from die115-2by a region116-3. Die115-4can be separated from die115-3by a region116-4. Each of regions116-1,116-2,116-3, and116-4can include a backing of the respective die, an adhesive, a DAF, or a paste, among other materials.

The third set of dies are positioned on and supported by a spacer103-2, which can be a silicon spacer. Die115-5can be separated from a top surface of spacer103-2by a region116-5. Die115-6can be separated from die115-5by a region116-6. Die115-7can be separated from die115-6by a region116-7. Die115-8can be separated from die115-7by a region116-8. Each of regions116-5,116-6,116-7, and116-8can include a backing of the respective die, an adhesive, a DAF, or a paste, among other materials.

In various situations, two or more of dies110-1,110-2,110-3,110-4, and110-5can be the same type of device and can be different from the type of devices implemented in dies115-1,115-2, . . .115-7, and115-18. In a non-limiting example, dies110-2,110-3,110-4, and110-5can be DRAM dies and dies115-1,115-2, . . .115-7, and115-18can be NAND memory dies, where die110-1can be a controller die. Since different die types are implemented in packaged electronic device100, it may not be appropriate to arrange all the dies in a common stack. As shown inFIG.1, spacers103-1and103-2are implemented to arrange the different types of dies within the dimensions of different sections of packaged electronic device100. Typically, spacer103-1and spacer103-2are silicon spacers. However, use of relatively thick silicon spacers can undesirably increase part or production costs.

With spacer103-1and spacer103-2being silicon spacers different from the materials of the dies, wires, and package substrate105, there can be an issue of a mismatch of thermal properties within packaged electronic device100. This thermal issue can be apparent by a mismatch of the coefficient of thermal expansion (CTE) of spacers103-1and103-2with respect to the other components within packaged electronic device100. CTE values of different features in packaged electronic device100can differ and cause mismatches. Active dies and spacers are typically made of silicon, which is a significantly low CTE material, while the CTE value of other materials in package are much higher than silicon. When such a package goes through high temperature operations or temperature cycling, silicon can shrink or expand to levels different from the other non-silicon material, which can cause stress and strain in coupling of these materials in the package such as packaged electronic device100. For example, the CTE of a spacer is typically higher than the CTE of mold compound. In some cases, warpage can become out of specification limits due to high shrinkage of mold compound when there is excessive mold compound volume. The CTE mismatch can result in warpage of the dies within packaged electronic device100, which can reduce the reliability performance of the dies within packaged electronic device100.

The components of packaged electronic device100can be encapsulated with a mold compound125. This encapsulation includes encapsulation of bond wires to the dies within packaged electronic device100. Components can be coupled together by DAFs117. Dies110-2,110-3,110-4, and110-5can also be coupled to package substrate105by sets of wires113-1and113-2. Dies115-1,115-2,115-3, and115-4can be coupled to package substrate105by a set of wires114-1and dies115-5,115-6,115-7, and115-8can be coupled to package substrate105by a set of wires114-2. The sets of wires114-1and114-2can be substantially longer than the sets of wires113-1and113-2. The longer wires can be susceptible to wire sweep, where wire sweep is a deformation that can occur when bonded wires are not correctly aligned in the horizontal plane. Wire sweep is undesirable, as it can affect electrical performance by changing the mutual inductance of adjacent wires. Wire sweep can occur during forming of mold compound125. A mismatch associated with spacers103-1and103-2being relatively large and the dies having varying die size aspect ratios (width to length) within packaged electronic device100can result in a relatively large mold compound volume that can lead to wire sweep risk due to one or more long wires of the sets of wires114-1and114-2extending to the top of dies115-4and115-8, which are at the tops of two die stacks. Such a relatively large mold compound can also lead to excessive mold compound volume, which can be a source of high positive warpage, relative to specifications, of dies such as at 260° C. for current design layouts, for example, as shown inFIG.1.

Package substrate105has contacts112coupled to contact pads122to allow components of packaged electronic device100to communicate, through package substrate105, with electronic devices or systems exterior to packaged electronic device100. Conductive paths123through substrate105are used to facilitate such communication within package substrate105. Contacts112can be implemented by a ball grid array or other arrangements of contacts.

Packaged electronic device100having multiple dies supported by package substrate105is an illustration of an architecture for a conventional multichip package (MCP) memory. Such a MCP memory can include a controller die, DRAM dies, and NAND dies, where all dies fit within the MCP having silicon spacers adopted for support. Die110-1can be a controller die and dies110-2,110-3,110-4, and110-5can be DRAM dies. Dies115-1,115-2. . .115-7, and115-8can be NAND dies. Mold compound125covers and protects the components of packaged electronic device100. Mold compound125can be flowed to positon above substrate105, around, between, and among the components of packaged electronic device100.

The loading of the components within packaged electronic device100can lead to a bending stress in packaged electronic device100when implementing the package in a system. The directional location of a package at which the bending stress is zero is defined as the neutral axis (NA). For a conventional packaged electronic device, such as packaged electronic device100, a NA102can run through spacers103-1and103-2.

FIG.2illustrates a composite beam200having a lower beam201-2and an upper beam201-1, where lower beam201-2and an upper beam201-1have different mechanical properties resulting from different sizes and material compositions. The horizontal interface between lower beam201-2and upper beam201-1is taken along an x-axis for which there can be a moment M of the area of composite beam about the x-axis. The location of the NA for the composite beam200depends on the relative stiffness and size (thickness) of each of the material sections, lower beam201-2and an upper beam201-1. The relative stiffness of a material can be described by Young's modulus, which can also be referred to as the modulus of elasticity, which modulus can be determined as the slope of a stress and strain relationship (ratio of stress to strain corresponding to the strain). In the composite structure, upper beam201-1has a Young's modulus of elasticity E1and lower beam201-2has a Young's modulus of elasticity E2.

FIG.3is a cross-sectional view of the composite beam200ofFIG.2along direction a-a. Upper beam201-1has an area A1with a center204-1and lower beam201-2has an area A2with a center204-2. With NA taken along the y-axis, NA of composite beam200is taken to be at a height h from the bottom surface of A2, at a distance of z1from center204-2, and at a distance of 22 from center204-1. The distances h, z1, and z2and Young's moduli E1and E2are related to NA by the relationship

With A1=A2, NA will be closer to the beam having higher stiffness. A substrate with attached dies can be considered as a simple composite beam having a die beam and a substrate beam. Typically, Young's modulus of a die beam is significantly higher than substrate beam.

In analyzing an electronic device package, a model of a composite beam having a die beam and a substrate beam can be implemented. The die beam can include multiple dies, DAFs, and an epoxy mold compound (EMC) covering the multiple dies. The substrate beam can include the substrate and components on and within the substrate structure to support the die beam. It has been determined that higher package (mold) strain, which provides better package strength, is observed when the NA is nearer to a top die surface, that is, when the difference between the distance from the bottom of the substrate to the top die surface and the distance from the bottom of the substrate to the NA is a relative minimum.

In various embodiments, substrates to support multiple dies are structured to provide a packaged electronic device with limited strain. Such substrates can be structured as an upper substrate connected to a lower substrate by a downset substrate, where the downset substrate includes through-vias between the upper substrate and the lower substrate. A substrate with a downset can be realized by a substrate structured in a U-shape pattern with an upper portion, a lower portion, and a connecting portion. The U-shape can have an approximate ninety degree angle from the lower to the upper portion. Other angles between the upper portion and the lower portion can be implemented.

Dies can be positioned with a region defined by walls of the downset portion with a non-conductive film (NCF) covering the dies in the region defined by walls of the downset portion. The NCF can cover walls of the downset, between which walls the dies are positioned. Additional dies can be positioned on the non-conductive film and the upper portion of the substrate. A substrate with a downset can be realized by an upper substrate, a lower substrate, and a downset substrate connecting the upper substrate to the lower substrate. The substrate with a downset shape can have an appropriate ninety degree angle from a lower substrate to an upper substrate. Other angles between the lower substrate and the upper substrate can be implemented.

Dies can be positioned with a region defined by walls of the downset substrate with a NCF covering the dies in the region defined by walls of the downset substrate. The NCF can cover walls of the downset, between which walls the dies are positioned. Additional dies can be positioned on the non-conductive film and the upper portion of the substrate.

The connecting portion and the downset substrate can include through vias between upper substrate to the lower substrate. The architecture for this substrate with a downset design can eliminate use of silicon spacers to support dies on the substrate, where a NCF can be applied over the downset. The NCF can provide strong support to top dies after a curing procedure performed for the NCF. The substrate with downset allows for the construction of a substrate with die locations within the substrate modeled as part of a substrate beam and die locations on and supported by a NCF modeled as a die beam, such that the NA can be located at a more advantageous position for the packaged electronic device using the substrate. A substrate with a downset design can make the NA shift upward towards the top of the dies, which benefits overall package strength.

FIG.4is a cross-sectional representation of an embodiment of an example packaged electronic device400having multiple dies. Dies410-1,410-2,410-3,410-4, and410-5form a first set of dies; dies415-1,415-2,415-3, and415-4form a second set of dies; and dies415-5,415-6,415-7, and415-8form a third set of dies. The sets of dies can be arranged in a level manner; that is, the dies can be arranged parallel to a substrate for packaged electronic device400. The substrate of packaged electronic device400can include an upper substrate405-3, a lower substrate405-1, and a downset substrate405-2connecting upper substrate405-3to lower substrate405-1. Upper substrate405-3, lower substrate405-1, and downset substrate405-2can be implemented as a single substrate. Downset substrate405-2can include vias407-1and407-2to provide conductive paths between lower substrate405-1and upper substrate405-3. Though five dies are shown in the first set, the first set can have more or fewer than five dies. Though four dies are shown in the second set, the second set can have more or fewer than four dies. Though four dies are shown in the third set, the third set can have more or fewer than four dies. The sets of dies can be supported by a substrate structured having multiple sections. The number of dies in each set can depend on the dimensions and material of the substrate with downset formed by upper substrate405-3, lower substrate405-1, and downset substrate405-2.

The first set of dies410-1,410-2,410-3,410-4, and410-5are supported by lower substrate405-1. Die410-1is positioned on lower substrate405-1by contacts418, with dies410-2,410-3,410-4, and410-5positioned on die410-1. Contacts418can be, but are not limited to, a ball grid array. Die410-2can be separated from die410-1by a region411-1. Die410-3can be separated from die410-2by a region411-2. Die410-4can be separated from die410-3by a region411-3. Die410-5can be separated from die410-4by a region411-4. Each of regions411-1,411-2,411-3, and411-4can include a backing of the respective die, an adhesive, a DAF, or a paste, among other materials.

The second set of dies415-1,415-2,415-3, and415-4are supported by a portion of upper substrate405-3. Die415-1can be separated from a top surface of the portion of upper substrate405-3by a region416-1. Die415-2can be separated from die415-1by a region416-2. Die415-3can be separated from die415-2by a region416-3. Die415-4can be separated from die415-3by a region416-4. Each of regions416-1,416-2,416-3, and416-4can include a backing of the respective die, an adhesive, a DAF, or a paste, among other materials.

The third set of dies415-5,415-6,415-7, and415-8are supported by another portion of upper substrate405-3. Die415-5can be separated from a top surface of the other portion of upper substrate by a region416-5. Die415-6can be separated from die415-5by a region416-6. Die415-7can be separated from die415-6by a region416-7. Die415-8can be separated from die415-7by a region416-8. Each of regions416-5,416-6,416-7, and416-8can include a backing of the respective die, an adhesive, a DAF, or a paste, among other materials.

A NCF420is located above lower substrate405-1and adjacent downset substrate405-2. NCF420be positioned to contact and cover downset substrate405-2while covering dies of the first set. NCF420covers the first set of dies positioned on lower substrate405-1and provides additional support for the second set of dies and the third set of dies that are also supported by upper substrate405-3. Lower substrate405-1, with the first set of dies positioned on lower substrate405-1covered by NCF420and located within the walls of downset substrate405-2, can be viewed as a lower beam of a two-beam composite beam. The first set of dies and a mold compound425covering the first set of dies can form the second beam of the two-beam composite beam. Various materials can be used for the substrates including, but not limited to, a halogen-free bismaleimide triazine resin material or a metal-clad laminate with metal cladding of the metal-clad laminate patterned with conductive routing.

With the substrate with downset design provided by upper substrate405-3, lower substrate405-1, and downset substrate405-2, selecting the number of dies to include along material and sizing of NCF420, lower substrate405-1, upper substrate405-3, and downset substrate405-1can place a NA402near the top surface of die415-4or415-8. With NA402near the top surface of the dies on upper substrate405-3, packaged electronic device400can meet or surpass specifications for package bending performance using a 3-point bending test and a 4-point bending test. In addition to selecting size, positioning, and material of NCF420to adjust the position of NA402, the material of NCF420can be selected according to the material's ability to support dies. A wide range of non-conducting materials can be selected for NCF420. For example, a mold compound material can be used for NCF420, where NCF420is different from mold compound425. NCF420can be formed by a pick and place process, while mold compound425is part of an encapsulating process with mold flow. If a mold compound is used as NCF420, the fabrication would include forming the mold compound in two processes. In various embodiments, material of NCF420is different from material of mold compound425.

In various situations, two or more of dies410-1,410-2,410-3,410-4, and410-5can be the same type of device die and can be different from the type of device dies implemented in dies415-4,415-2, . . .415-17, and415-18. In a non-limiting example, dies410-2,410-3,410-4, and410-5can be DRAM dies and dies415-1,415-2, . . .415-17, and415-18can be NAND memory dies, where die410-1can be a controller die. Since different die types are implemented in packaged electronic device400, it may not be appropriate to arrange all the dies in a common stack. As shown inFIG.4, the substrate with downset design is implemented to arrange the different types of dies within the dimensions of different sections of packaged electronic device400.

The components of packaged electronic device400are encapsulated with a mold compound425. This encapsulation includes encapsulation of bond wires to the dies within packaged electronic device400. Components can be coupled together by die-attach-films (DAFs)417. Dies410-2,410-3,410-4, and410-5can also be coupled to contact pads422on lower substrate405-1by sets of wires413-1and413-2. Dies415-1,415-2,415-3, and415-4can be coupled to contact pads422on upper substrate405-3by a set of wires414-1and dies415-5,415-6,415-7, and415-8can be coupled to contact pads422on upper substrate405-3by a set of wires414-2. The sets of wires414-1and414-2can have a length comparable to the sets of wires413-1and413-2based on the substrate with downset design shown inFIG.4.

Package substrate405-1has contacts412coupled to contact pads422to allow components of packaged electronic device400to communicate, through package substrate including lower substrate405-1, downset substrate405-2, and upper substrate405-3, with electronic devices or systems exterior to packaged electronic device400. Conductive paths423and vias407-1and407-2through lower substrate405-1, upper substrate405-3, and downset substrate405-2can be used to facilitate such communication within packaged electronic device400. Contacts412can be implemented by a ball grid array or other arrangements of contacts.

As can be seen in comparingFIG.4withFIG.1, the package substrate ofFIG.4defined by lower substrate405-1, downset substrate405-2, and upper substrate405-3can provide additional characteristics not provided by package substrate105ofFIG.1. The package substrate with downset design ofFIG.4can eliminate use of a costly and relatively thick silicon spacers (thick relative to the dies housed in packaged electronic devices). Such elimination can reduce the number of components in packaged electronic device400. A package substrate with downset design, such as that ofFIG.4, can enhance reliability performance by reducing CTE mismatch within packaged electronic device400. For example, the package substrate with downset design (upper substrate405-3, downset substrate405-2, and lower substrate405-1) can reduce mold compound volume by removing the use of spacers, which can help reduce shrinkage differences to balance warpage behavior when packaged electronic device400is in a relatively high temperature range. As seen inFIG.4, the package substrate with downset design can allow for a shorter wire length that can save cost as well as provide shorter signal path. The wires can be, but are not limited to, gold wires. The package substrate with downset design can also reduce wire sweep risk due to long wires on the die stack extending to the top region of packaged electronic device400.

WithFIG.4being a cross-sectional view, other vias and landing pads to these vias are coupled to various ones of the contacts412providing communication paths to other sections of packaged electronic device400. These vias, pads, and contacts can be designed in number and location based on electronic dies to be positioned on the substrate with downset design. The contacts to mate with electrical communication paths exterior to packaged electronic device400can be formed to meet designs associated with specifications for application of the electronic dies to be packaged on the substrate with downset design for packaged electronic device400.

FIG.5is a top view of the example packaged electronic device400ofFIG.4along an upper substrate405-3of the packaged electronic device400. Upper substrate405-3is a continuous structure having an opening in which NCF420is disposed.FIG.5shows NCF420around the first set of dies410-1. . .410-5, where a top surface410of the first set is indicated. The continuous structure of upper substrate405-3can include conductive paths coupled to the one or more vias407-1and407-2. About the upper substrate405-3is the mold compound425.

FIG.6is a cross-sectional representation of an embodiment of an example packaged electronic device600having multiple dies. The cross-section ofFIG.6is similar to the cross-section ofFIG.4, where packaged electronic device600can differ from packaged electronic device400by the arrangement in the y-direction of a substrate with downset for the two packaged electronic devices. Dies610-1,610-2,610-3,610-4, and610-5form a first set of dies; dies615-1,615-2,615-3, and615-4form a second set of dies; and dies615-5,615-6,615-7, and615-8form a third set of dies. The sets of dies can be arranged in a level manner; that is, the dies can be arranged parallel to a substrate for packaged electronic device600. The substrate of packaged electronic device600can include an upper substrate605-3, a lower substrate605-1, and a downset substrate605-2connecting upper substrate605-3to lower substrate605-1. Upper substrate605-3, lower substrate605-1, and downset substrate605-2can be implemented as a single substrate. Downset substrate605-2can include vias607-1and607-2to provide conductive paths between lower substrate605-1and upper substrate605-3. Though five dies are shown in the first set, the first set can have more or fewer than five dies. Though four dies are shown in the second set, the second set can have more or fewer than four dies. Though four dies are shown in the third set, the third set can have more or fewer than four dies. The sets of dies can be supported by a substrate structured with multiple sections. The number of dies in each set can depend on the dimensions and material of the substrate with downset formed by upper substrate605-3, lower substrate605-1, and downset substrate605-2.

The first set of dies610-1,610-2,610-3,610-4, and610-5are supported by lower substrate605-1. Die610-1is positioned on lower substrate605-1by contacts618, with dies610-2,610-3,610-4, and610-5positioned on die610-1. Contacts618can be, but are not limited to, a ball grid array. Die610-2can be separated from die610-1by a region611-1. Die610-3can be separated from die610-2by a region611-2. Die610-4can be separated from die610-3by a region611-3. Die610-5can be separated from die610-4by a region611-4. Each of regions611-1,611-2,611-3, and611-4can include a backing of the respective die, an adhesive, or a paste, among other materials.

The second set of dies615-1,615-2,615-3, and615-4are supported by a portion of upper substrate605-3. Die615-1can be separated from a top surface of the portion of upper substrate605-3by a region616-1. Die615-2can be separated from die615-1by a region616-2. Die615-3can be separated from die615-2by a region616-3. Die615-4can be separated from die615-3by a region616-4. Each of regions616-1,616-2,616-3, and616-4can include a backing of the respective die, an adhesive, a DAF, or a paste, among other materials.

The third set of dies615-5,615-6,615-7, and615-8are supported by another portion of upper substrate605-3. Die615-5can be separated from a top surface of the other portion of upper substrate by a region616-5. Die615-6can be separated from die615-5by a region616-6. Die615-7can be separated from die615-6by a region616-7. Die615-8can be separated from die615-7by a region616-8. Each of regions616-5,616-6,616-7, and616-8can include a backing of the respective die, an adhesive, a DAF, or a paste, among other materials.

A NCF620is located above lower substrate605-1and adjacent downset substrate605-2. NCF620covers the first set of dies positioned on lower substrate605-1and provides additional support for the second set of dies and the third set of dies that are also supported by upper substrate605-3. Lower substrate605-1with the first set of dies positioned on lower substrate605-1covered by NCF620and located within the walls of downset substrate605-2, can be viewed as a lower beam of a two-beam composite beam. The first set of dies and a mold compound625covering the first set of dies can form the second beam of the two-beam composite beam. Various materials can be used for the substrates including, but not limited to, a halogen-free bismaleimide triazine resin material or a metal-clad laminate with metal cladding of the metal-clad laminate patterned with conductive routing.

With the substrate with downset design provided by upper substrate605-3, lower substrate605-1, and downset substrate605-2, selecting material for and sizing NCF620, lower substrate605-1, upper substrate605-3, and downset substrate605-1can place a NA602near the top surface of die615-4or615-8. With NA602near the top surface of the dies on upper substrate605-3, packaged electronic device600can meet or surpass specifications for package bending performance using a 3-point bending test and a 4-point bending test. In addition to selecting size, positioning, and material of NCF420to adjust the position of NA602, the material of NCF620can be selected according to the material's ability to support dies. A wide range of non-conducting materials can be selected for NCF620. For example, a mold compound material can be used for NCF620, where NCF620is different from mold compound625. NCF620can be formed by a pick and place process, while mold compound625is part of an encapsulating process with mold flow. If a mold compound is used as NCF620, the fabrication would include forming the mold compound in two processes. In various embodiments, material of NCF620is different from material of mold compound625.

In various situations, two or more of dies610-1,610-2,610-3,610-4, and610-5can be the same type of device die and can be different from the type of device dies implemented in dies615-4,615-2, . . .615-17, and615-18. In a non-limiting example, dies610-2,610-3,610-4, and610-5can be DRAM dies and dies615-1,615-2, . . .615-17, and615-18can be NAND memory dies, where die610-1can be a controller die. Since different die types are implemented in packaged electronic device600, it may not be appropriate to arrange all the dies in a common stack. As shown inFIG.6, the substrate with downset design can be implemented to arrange the different types of dies within the dimensions of different sections of packaged electronic device600.

The components of packaged electronic device600are encapsulated with a mold compound625. This encapsulation includes encapsulation of bond wires to the dies within packaged electronic device600. Components can be coupled together by DAFs617. Dies610-2,610-3,610-4, and610-5can also be coupled to lower substrate605-1by sets of wires613-1and613-2. Dies615-1,615-2,615-3, and615-4can be coupled to upper substrate605-3by a set of wires614-1and dies615-5,615-6,615-7, and615-8can be coupled to upper substrate605-3by a set of wires614-2. The sets of wires614-1and614-2can have a length comparable to the sets of wires613-1and613-2based on the substrate with downset design shown inFIG.6.

Package substrate605-1has contacts612coupled to contact pads622to allow components of packaged electronic device600to communicate, through package substrate including lower substrate605-1, downset substrate605-2, and upper substrate605-3, with electronic devices or systems exterior to packaged electronic device600. Conductive paths623and vias607-1and607-2through lower substrate605-1, upper substrate605-3, and downset substrate605-2can be used to facilitate such communication within packaged electronic device600. Contacts612can be implemented by a ball grid array or other arrangements of contacts.

As can be seen in comparingFIG.6withFIG.1, package substrate ofFIG.6defined by lower substrate605-1, downset substrate605-2, and upper substrate605-3can provide additional characteristics not provided by package substrate105ofFIG.1. The package substrate with downset design ofFIG.6can eliminate use of a costly and relatively thick silicon spacers (thick relative to the dies housed in packaged electronic devices). Such elimination can reduce the number of components in packaged electronic device600. A package substrate with downset design, such as that ofFIG.6, can enhance reliability performance by reducing CTE mismatch within packaged electronic device600. For example, the package substrate with downset design (upper substrate605-3, downset substrate605-2, and lower substrate605-1) can reduce mold compound volume by removing the use of spacers, which can help reduce shrinkage differences to balance warpage behavior when packaged electronic device600is in a relatively high temperature range. As seen inFIG.6, the package substrate with downset design can allow for shorter wire length that can save cost as well as provide shorter signal path. The wires can be, but are not limited to, gold wires. The package substrate with downset design can also reduce wire sweep risk due to long wires on the die stack extending to the top region of packaged electronic device600.

WithFIG.6being a cross-sectional view, other vias and landing pads to these vias are coupled to various ones of the contacts612providing communication paths to other sections of packaged electronic device600. These vias, pads, and contacts can be designed in number and location based on electronic dies to be positioned on the substrate with downset design. The contacts to mate with electrical communication paths exterior to packaged electronic device600can be formed to meet designs associated with specifications for application of the electronic dies to be packaged on the substrate with downset design for packaged electronic device600.

FIG.7is a top view of the example packaged electronic device600ofFIG.6along an upper substrate605-3of the packaged electronic device600. Upper substrate605-3is non-continuous having a first substantially continuous portion and a second substantially continuous portion. The first portion can include a first set of conductive paths coupled to vias607-1ofFIG.6and the second portion can include a second set of conductive paths coupled to vias607-2ofFIG.6. Upper substrate605-3has an opening between the first and the second portion in which NCF620is disposed.FIG.7shows NCF620around the first set of dies610-1. . .610-5, where a top surface610of the first set is indicated. Similar toFIG.5, mold compound625ofFIG.6(not shown inFIG.7) can be disposed about upper substrate605-3.

Packaged electronic devices having a substrate with downset design, as taught herein, can be manufacturable with various processes. The substrate with downset design can be a single substrate formed with an upper portion, a downset portion, and a lower portion. The downset portion can include through vias providing conductive paths between the lower portion and the upper portion. The substrate with downset design can be formed as an upper substrate connected to a lower substrate by a downset substrate. The downset substrate can include through vias providing conductive paths between the lower substrate and the upper substrate. Such substrates with downset design allow for a set of multiple dies within the downset portion or within the region formed by downset substrates. NCF within the downset provides support for additional dies located on the upper portion or upper substrate. Such package substrates with downset design can provide enhanced package bending performance in 3-point bending tests and 4-point bending tests and improve reliability performance. Such package substrates with downset design can eliminate use of costly thick silicon spacers in electronic device packaging. Such package substrates with downset design can provide shorter gold wire length to save cost as well as shorter signal path and reduce wire sweep risk by avoiding long wires extending to the top of a die stack. Packaged electronic devices using such package substrates with a downset design are not limited to memory devices. Such package substrates can be used in other packaged electronic devices having multiple semiconductor dies.

FIG.8is a block diagram of an embodiment of an example system800having one or more packaged electronic devices840-1,840-2. . .840-N. One or more of packaged electronic devices840-1,840-2. . .840-N can include a package substrate having a downset design, as taught herein. Packaged electronic devices840-1,840-2. . .840-N can operate in conjunction with one or more processors835. Such operation can be facilitated using routing circuitry845. One or more of the packaged electronic devices840-1,840-2. . .840-N can be memory devices.

One or more of the packaged electronic devices840-1,840-2. . .840-N can include semiconductor dies different from memory dies or memory controllers that perform functions designed to operate according to system specifications for which packaged electronic devices840-1,840-2. . .840-N are included in the given system. The one or more processors835, packaged electronic devices840-1,840-2. . .840-N, and routing circuitry845can be implemented on a platform830. Platform830can be, but is not limited to, a printed circuit board or a computer motherboard. Though routing circuitry845is shown as individual lines, routing circuitry845can be implemented as sets of patterned electrically conductive traces on platform830. Routing circuitry845can be implemented as sets of bundled routing wires.

FIG.9is a flow diagram of features of an embodiment of an example method900of forming a packaged electronic device. At910, a lower substrate is formed. At920, an upper substrate is formed above the lower substrate with the upper substrate having an opening. At930, a downset substrate is formed connecting the upper substrate to the lower substrate, with the downset substrate having one or more vias between the upper substrate and the lower substrate. The upper substrate, downset substrate, and lower substrate can be formed as a single substrate in which an open region is generated to form the downset substrate in which open region dies can be positioned. At940, one or more electronic devices are positioned on the lower substrate. At950, a non-conductive film is formed, disposed in the opening of the upper substrate, on the one or more electronic dies and on sidewalls of the downset substrate.

Variations of method900or methods similar to method900can include a number of different embodiments that may be combined depending on the application of such methods and/or the architecture of systems including an electronic device for which such methods are implemented. Such methods can include positioning one or more additional electronic dies above and supported by the non-conductive film. A mold compound can be formed covering the one or more additional electronic dies, the upper substrate, the downset substrate, and the lower substrate.

Variations of method900or methods similar to method900can include forming the packaged electronic device having a neutral axis at about a top of electronic dies above a top surface of the upper substrate. Forming the packaged electronic device having the neutral axis positioned at about the top of electronic dies above the top surface of the upper substrate can include, with respect to quantities and sizes of the one or more electronic devices, selecting material of the non-conductive film, the lower substrate, the upper substrate, and the downset substrate and sizing the non-conductive film, the lower substrate, the upper substrate, and the downset substrate with respect to quantities and sizes of the one or more electronic devices.

Variations of method900or methods similar to method900can include curing the non-conductive film after forming the non-conductive film. Variations can include forming the upper substrate as a continuous structure around the opening, with the continuous structure having conductive paths coupled to the one or more vias. Variations can include forming the upper substrate as two separate continuous structures providing the opening, with each of the two continuous structures having conductive paths coupled to the one or more vias.

In various embodiments, an electronic device can comprise one or more electronic dies, a lower substrate, an upper substrate, and a downset substrate. The lower substrate is constructed on which the one or more electronic dies can be positioned. The upper substrate is positioned above the lower substrate, where the upper substrate has an opening above the one or more electronic dies. The downset substrate connects the upper substrate to the lower substrate, where the downset substrate has one or more vias between the upper substrate and the lower substrate. A non-conductive film can be disposed in the opening of the upper substrate, on the one or more electronic dies and on sidewalls of the downset substrate.

Variations of such an electronic device and its features, as taught herein, can include a number of different embodiments and features that can be combined depending on the application of such electronic devices, the format of such electronic devices, and/or the architecture in which such electronic devices are implemented. Variations of such an electronic device can include one or more additional electronic dies being positioned above and supported by the non-conductive film. The electronic device can be a packaged electronic device having a neutral axis positioned at about a top of the electronic dies on the upper substrate. The electronic device can include package electrical contacts coupled to the lower substrate, where one or more of the package electrical contacts can be configured to provide signals, via the one or more vias, between the one or more additional electronic dies and one or more devices external to the electronic device. The electronic device can include package electrical contacts coupled to the lower substrate, where one or more of the package electrical contacts can be configured to provide signals between the one or more electronic dies and one or more devices external to the electronic device.

Variations of such an electronic device and its features can include the upper substrate being a continuous structure around the opening, where the continuous structure can include conductive paths coupled to the one or more vias. Variations of such an electronic device can include the opening of the upper substrate separating a first portion of the upper substrate from a second portion of the upper substrate such that the upper substrate is non-continuous between the first portion and the second portion. The first portion can include a first set of conductive paths coupled to a first via set of the one or more vias and the second portion can include a second set of conductive paths coupled to a second via set of the one or more vias.

Such an electronic device can include one or more additional electronic dies positioned above and supported by the non-conductive film. A mold compound can be structured to provide a cover to the one or more additional electronic dies, the upper substrate, the downset substrate, and the lower substrate.

In various embodiments, a system can comprise at least one packaged electronic device. The at least one packaged electronic device can include a processing device die and memory device dies coupled to the processing device, with the processing device die and the memory device dies positioned on a substrate. The substrate can include a lower substrate, an upper substrate, and a downset substrate. The processing device die and memory device dies can be positioned on the lower substrate. The upper substrate can be structured above the lower substrate, where the upper substrate has an opening above the memory device dies that are positioned on the lower substrate. The downset substrate connects the upper substrate to the lower substrate, where the downset substrate has one or more vias between the upper substrate and the lower substrate. A non-conductive film can be disposed in the opening of the upper substrate, on the memory device dies and on sidewalls of the downset substrate.

Variations of such a system and its features, as taught herein, can include a number of different embodiments and features that can be combined depending on the application of such systems, the format of such systems, and/or the architecture in which such systems are implemented. Variations of such a system can include the at least one packaged electronic device having a neutral axis at about a top surface of a top additional die on the upper substrate of the at least one packaged electronic device.

Variations of such a system can include one or more additional dies positioned above and supported by the non-conductive film in the at least one packaged electronic device. The memory device dies can include volatile memory devices and the one or more additional dies can include one or more non-volatile memory dies. Variations can include packaging of the at least one packaged electronic device having a mold compound structured to provide a cover to the one or more additional dies, the upper substrate, the downset substrate, and the lower substrate.

Electronic devices, such as mobile electronic devices (e.g., smart phones, tablets, etc.), electronic devices for use in automotive applications (e.g., automotive sensors, control units, driver-assistance systems, passenger safety or comfort systems, etc.), and internet-connected appliances or devices (e.g., internet-of-things (IoT) devices, etc.), have varying storage needs depending on, among other things, the type of electronic device, use environment, performance expectations, etc. Such electronic devices can be broken down into several main components: a processor (e.g., a central processing unit (CPU) or other main processor); memory (e.g., one or more volatile or non-volatile RAM memory device, such as DRAM, mobile or low-power double-data-rate synchronous DRAM (DDR SDRAM), etc.); and a storage device (e.g., non-volatile memory (NVM) device, such as flash memory, ROM, a solid-state drive (SSD), a MultiMediaCard (MMC), or other memory card structure or assembly, etc.). In certain examples, electronic devices can include a user interface (e.g., a display, touch-screen, keyboard, one or more buttons, etc.), a graphics processing unit (GPU), a power management circuit, a baseband processor or one or more transceiver circuits, etc. As used herein, “processor device” means any type of computational circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor (DSP), or any other type of processor or processing circuit, including a group of processors or multi-core devices. These electronic devices provide examples of structures that can include a substrate with a downset design similar to substrates with a downset design discussed herein.

The following example embodiments of methods, devices, and systems, in accordance with the teachings herein.

An example electronic device1can comprise: one or more electronic dies; a lower substrate on which the one or more electronic dies are positioned; an upper substrate above the lower substrate, the upper substrate having an opening above the one or more electronic dies; a downset substrate connecting the upper substrate to the lower substrate, the downset substrate having one or more vias between the upper substrate and the lower substrate; and a non-conductive film disposed in the opening of the upper substrate, on the one or more electronic dies and on sidewalls of the downset substrate.

An example electronic device2can include features of example electronic device1and can include one or more additional electronic dies being positioned above and supported by the non-conductive film.

An example electronic device3can include features of example electronic device2and any features of the preceding example electronic devices and can include the electronic device being a packaged electronic device having a neutral axis at a top surface of the one or more additional electronic dies.

An example electronic device4can include features of example electronic device2and any features of the preceding example electronic devices and can include package electrical contacts coupled to the lower substrate, one or more of the package electrical contacts configured to provide signals, via the one or more vias, between the one or more additional electronic dies and one or more devices external to the electronic device.

An example electronic device5can include features of any of the preceding example electronic devices and can include package electrical contacts coupled to the lower substrate, one or more of the package electrical contacts configured to provide signals between the one or more electronic dies and one or more devices external to the electronic device.

An example electronic device6can include features of any of the preceding example electronic devices and can include the upper substrate being a continuous structure around the opening, the continuous structure including conductive paths coupled to the one or more vias.

An example electronic device7can include features of example electronic device6and any of the preceding example electronic devices and can include the opening of the upper substrate separating a first portion of the upper substrate from a second portion of the upper substrate such that the upper substrate is non-continuous between the first portion and the second portion, the first portion including a first set of conductive paths coupled to a first via set of the one or more vias and the second portion including a second set of conductive paths coupled to a second via set of the one or more vias.

An example electronic device8can include features of any of the preceding example electronic devices and can include one or more additional electronic dies being positioned above and supported by the non-conductive film; and a mold compound being structured to provide a cover to the one or more additional electronic dies, the upper substrate, the downset substrate, and the lower substrate.

In an example electronic device9, any of the electronic devices of example electronic devices1to8may include electronic devices incorporated into an electronic apparatus further comprising a host processor and a communication bus extending between the host processor and the electronic device.

In an example electronic device10, any of the electronic devices of example electronic devices1to9may be modified to include any structure presented in another of example electronic device1to9.

In an example electronic device11, any apparatus associated with the electronic devices of example electronic devices1to10may further include a machine-readable storage device configured to store instructions as a physical state, wherein the instructions may be used to perform one or more operations of the apparatus.

In an example electronic device12, any of the electronic devices of example electronic devices1to11may be formed in accordance with any of the below example methods1to11.

An example system1can comprise: at least one packaged electronic device, the at least one packaged electronic device including: a processing device die; memory device dies coupled to the processing device; a lower substrate on which the processing device die and memory device dies are positioned; an upper substrate above the lower substrate, the upper substrate having an opening above the memory device dies; a downset substrate connecting the upper substrate to the lower substrate, the downset substrate having one or more vias between the upper substrate and the lower substrate; and a non-conductive film disposed in the opening of the upper substrate, on the memory device dies and on sidewalls of the downset substrate.

An example system2can include features of preceding example system1and can include the at least one packaged electronic device having a neutral axis at a top surface of the upper substrate of the at least one packaged electronic device.

An example system3can include features of any of the preceding example systems and can include one or more additional dies being positioned above and supported by the non-conductive film in the at least one packaged electronic device.

An example system4can include features of example system3and any of the preceding example packaged electronic devices and can include the one or more memory device dies including volatile memory devices and the one or more additional dies including one or more non-volatile memory dies.

An example system5can include features of example system4and any features of the preceding example packaged electronic devices and can include packaging of the at least one packaged electronic device including a mold compound structured to provide a cover to the one or more additional electronic dies, the upper substrate, the downset substrate, and the lower substrate.

In an example system6, any of the systems of example systems1to5may include systems incorporated into an electronic apparatus further comprising a host processor and a communication bus extending between the host processor and the systems.

In an example system7, any of the systems of example systems1to6may be modified to include any structure presented in another of example system1to6.

In an example system8, any apparatus associated with the systems of example systems1to7may further include a machine-readable storage device configured to store instructions as a physical state, wherein the instructions may be used to perform one or more operations of the apparatus.

In an example system9, any of the systems of example systems1to8may be formed in accordance with any of the methods of the below example methods1to11.

An example method1of forming a packaged electronic device can comprise: forming a lower substrate; forming an upper substrate above the lower substrate with the upper substrate having an opening; forming a downset substrate connecting the upper substrate to the lower substrate, with the downset substrate having one or more vias between the upper substrate and the lower substrate; positioning one or more electronic devices on the lower substrate; and forming a non-conductive film, disposed in the opening of the upper substrate, on the one or more electronic dies and on sidewalls of the downset substrate.

An example method2of forming a packaged electronic device can include features of example method1of forming a packaged electronic device and can include positioning one or more additional electronic dies above and supported by the non-conductive film.

An example method3of forming a packaged electronic device can include features of example method2and any of the preceding example methods of forming a packaged electronic device and can include forming a mold compound covering the one or more additional electronic dies, the upper substrate, the downset substrate, and the lower substrate.

An example method4of forming a packaged electronic device can include features of example method2and any of the preceding example methods of forming a packaged electronic device and can include forming the packaged electronic device having a neutral axis at a top surface of the one or more additional electronic dies.

An example method5of forming a packaged electronic device can include features of example method4of forming a packaged electronic device and any of the preceding example methods of forming a packaged electronic device and can include forming the packaged electronic device having the neutral axis at the top surface of the upper substrate material to include, with respect to quantities and sizes of the one or more electronic devices, selecting material of the non-conductive film, the lower substrate, the upper substrate, and the downset substrate, and sizing the non-conductive film, the lower substrate, the upper substrate, and the downset substrate.

An example method6of forming a packaged electronic device can include features of any of the preceding example methods of forming a packaged electronic device and can include curing the non-conductive film after forming the non-conductive film.

An example method7of forming a packaged electronic device can include features of any of the preceding example methods of forming a packaged electronic device and can include forming the upper substrate as a continuous structure around the opening, with the continuous structure having conductive paths coupled to the one or more vias.

In an example method8of forming a packaged electronic device, any of the example methods1to7of forming a packaged electronic device may be performed in forming a packaged electronic device further comprising a host processor and a communication bus extending between the host processor and the packaged electronic device.

In an example method9of forming a packaged electronic device, any of the example methods1to8of forming a packaged electronic device may be modified to include operations set forth in any other of example methods1to8of forming a packaged electronic device.

In an example method10of forming a packaged electronic device, any of the example methods1to9of forming a packaged electronic device may be implemented at least in part through use of instructions stored as a physical state in one or more machine-readable storage devices.

An example method11of forming a packaged electronic device can include features of any of the preceding example methods1to10and can include performing functions associated with any features of example electronic devices1to12and systems1to9.

An example machine-readable storage device1storing instructions that when executed by one or more processors, cause a machine to perform operations, can comprise instructions to perform functions associated with any features of example electronic device1to12and example systems1to9or perform methods associated with any features of example methods1to11.