Semiconductor device

A semiconductor device that can cope with larger numbers of pins and finer pitches while suppressing lowering of the manufacturing yield and reliability includes: a semiconductor chip having a plurality of electrodes provided on an upper surface thereof; a plurality of lead terminals including inner lead portions disposed toward the semiconductor chip; a sheet-form wiring member having a plurality of conductors insulated from one another on one main surface thereof; and a sealing-resin layer for sealing at least the semiconductor chip, the inner lead portions and the wiring member. The electrodes of the semiconductor device and the inner lead portions of the lead terminals are electrically connected respectively to each other via the conductors of the wiring member.

This nonprovisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 2007-272443 filed on Oct. 19, 2007, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor devices, and in particular to a semiconductor device of the resin-sealed type formed with a lead frame.

2. Description of Related Art

As an example of semiconductor devices of a resin-sealed type that are formed with a lead frame, those of a QFP (Quad Flat Package) type are conventionally known. Generally, in QFP type semiconductor devices, by narrowing the width of the inner lead portions (lead terminals) of the lead frame, larger number of pins and finer pitches are achieved so as to cope with higher degrees of integration in semiconductor elements.

However, since there is a limit to the formation of the width of inner lead portions (lead terminals), in a case where the number of inner lead portions (lead terminals) is increased so as to cope with an increased number of pins, it is necessary to enlarge the size of the lead frame itself. And as the lead frame is enlarged, the distances between electrode pads of a semiconductor chip and the inner lead portions corresponding thereto are lengthened. Accordingly, there arises a disadvantage that the bonding wires that electrically connect the electrode pads and the inner lead portions are lengthened.

Here, if the lengths of the bonding wires exceed a predetermined length, so-called wire sweep takes place in which the bonding wires are deformed in the flow direction of sealing resin during the process of resin-sealing the semiconductor chip with the sealing resin. As a result, there arises a disadvantage that a short-circuit occurs owing to the mutual contact of adjacent bonding wires. Generally, in a semiconductor device of a QFP type, of all the bonding wires, those at the corners of the semiconductor chip are longest, and therefore the occurrence of the aforementioned wire sweep is noticeable at the corners of the semiconductor device.

In this connection, there is conventionally known a QFP type semiconductor device capable of suppressing the wire sweep at the corners thereof. A semiconductor device of this type is described, for example, in Japanese Unexamined Patent Application Publication (JP-A) No. H10-116953. This publication discloses a QFP type semiconductor device in which the inner lead portions connected to the electrode pads at the corners of the semiconductor chip are arranged closer to the semiconductor chip than the adjacent inner lead portions are. In the conventional semiconductor devices structured in this manner, it is possible to prevent the bonding wires at the corners from becoming longer than the rest, and therefore it is possible to suppress the wire sweep at the corners of the semiconductor device.

However, in the conventional semiconductor device disclosed in the aforementioned publication JP-A No. H10-116953, in a case where the number of lead terminals (inner lead portions) is further increased so as to cope with an even larger number of pins, the lead frame becomes even larger, and therefore there arises a disadvantage that the bonding wires except those at the corners of the semiconductor device become longer than a predetermined length. Thus, with the structure described above, the semiconductor device, though capable of suppressing the wire sweep at the corners thereof, yet has a disadvantage that the wire sweep still occurs at any part of the device other than the corners. Accordingly, in a case where even larger numbers of pins and even finer pitches are to be coped with, the semiconductor device in JP-A No. H10-116953 raises a problem of lowering the manufacturing yield and reliability of the semiconductor device due to a short-circuit between bonding wires resulting from the wire sweep. Incidentally, it is difficult to overcome the above-mentioned disadvantages and problems by changing the conditions of the resin-sealing process or changing the material of the bonding wires.

SUMMARY OF THE INVENTION

In light of the foregoing, it is an object of the present invention to provide a semiconductor device that can cope with even larger numbers of pins and even finer pitches while suppressing the lowering of the manufacturing yield and reliability of the semiconductor device.

In order to achieve the above object, according to one aspect of the present invention, a semiconductor device includes: a semiconductor chip having a plurality of electrodes provided on a surface on one side thereof; a plurality of lead terminals having one end portions thereof disposed toward the semiconductor chip; a sheet-form wiring member having a plurality of conductors insulated from one another on one main surface thereof; and a sealing-resin layer for sealing at least the semiconductor chip, the one end portions of the lead terminals and the wiring member, wherein the electrodes of the semiconductor chip and the one end portions of the lead terminals are electrically connected respectively to each other via the conductors of the wiring member.

As described above, the semiconductor device in accordance with this aspect of the present invention is provided with the sheet-form wiring member having the plurality of conductors insulated from one another on the one main surface thereof, and via the conductors of the wiring member, the electrodes and the one end portions of the lead terminals are electrically connected respectively to each other. Thereby, unlike a case where bonding wires are used for electrical connection between the electrodes of the semiconductor chip and the one end portions of the lead terminals, the occurrence of a problem such as wire sweep can be suppressed. That is, during the process of resin-sealing the semiconductor chip with the sealing-resin layer, the conductors provided on the sheet-form wiring member are difficult to deform in the flow direction of the sealing resin as compared with the bonding wires. Accordingly, even in a case where the distances between the electrode pads of the semiconductor chip and the one end portions of the lead terminals corresponding thereto are lengthened and the pitch of the conductors on the wiring member is narrowed so as to cope with larger numbers of pins and finer pitches, a short-circuit between adjacent conductors can be prevented. Consequently, it is possible to suppress the lowering of the manufacturing yield and reliability even in a case where even larger numbers of pins and even finer pitches are to be coped with.

In the semiconductor device in accordance with the above-described aspect of the present invention, a metal bump is preferably formed on the electrodes of the semiconductor chip and on the one end portions of the lead terminals. With this structure, the electrodes of the semiconductor chip and the one end portions of the lead terminals can be electrically connected respectively to each other with ease. Consequently, it is possible to cope with even larger numbers of pins and even finer pitches while suppressing the lowering of the manufacturing yield and reliability with ease.

In this case, the metal bump is preferably a stud bump. With this structure, the electrodes of the semiconductor chip and the one end portions of the lead terminals can be electrically connected respectively to each other with more ease. Consequently, it is possible to cope with even larger numbers of pins and even finer pitches while suppressing the lowering of the manufacturing yield and reliability with more ease.

In the above-described semiconductor device in accordance with the above-described aspect of the present invention, the sheet-form wiring member may include a sheet-form polyimide member.

Preferably, the semiconductor device in accordance with the above-described aspect of the present invention is structured such that the upper surfaces of the one end portions of the lead terminals are at substantially a same height as the surface on the one side of the semiconductor chip. With this structure, the electrodes of the semiconductor chip and the one end portions of the lead terminals can be electrically connected respectively to each other with more ease. Consequently, it is possible to cope with even larger numbers of pins and even finer pitches while suppressing the lowering of the manufacturing yield and reliability with more ease.

Preferably, the semiconductor device in accordance with the above-described aspect of the present invention is formed into the QFP type package by sealing the semiconductor chip in the sealing-resin layer. This structure makes it possible to easily obtain semiconductor devices that can cope with larger numbers of pins and finer pitches while suppressing the lowering of the manufacturing yield and reliability of the semiconductor devices.

As described above, according to the present invention, it is possible to easily obtain semiconductor devices that can cope with even larger numbers of pins and even finer pitches while suppressing the lowering of the manufacturing yield and reliability of the semiconductor devices.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A preferred embodiment of the present invention will be described in detail below with reference to the accompanying drawings. This embodiment deals with a case where the present invention is applied to a QFP type semiconductor device as an example of resin-sealed type semiconductor devices.

First, with reference toFIGS. 1 to 5, a structure of a semiconductor device in accordance with one embodiment of the present invention will be described.

As shown inFIG. 1, the semiconductor device in accordance with the one embodiment of the present invention includes: a semiconductor chip1; a die pad10having the semiconductor chip1mounted thereon; a plurality of lead terminals21; a sheet-form wiring member30for electrically connecting the semiconductor chip1and the plurality of lead terminals21; and a resin-sealing layer40.

The semiconductor chip1includes a silicon substrate having an integrated circuit or the like formed on a main surface on one side (an upper surface) thereof. On a peripheral part of the main surface on one side (the upper surface, the surface on one side) of the semiconductor chip1, a plurality of electrode pads2(seeFIGS. 4 and 5) are arranged at a predetermined interval along the peripheral edges of the semiconductor chip1. The semiconductor chip1is mounted on an upper surface of the die pad10via an adhesive layer made of solder or the like. Note that the electrode pads2are an example of “electrodes” according to the present invention.

As shown inFIGS. 4 and 5, the die pad10is formed in a substantially rectangular shape as seen in a plan view, and includes four suspension leads11integrally connected thereto. These four leads11are disposed at the four corners, respectively, of the die pad10, and are formed so as to extend in a radial pattern as seen in a plan view. The suspension leads11are provided for holding the die pad10on a lead frame described later. Each of these suspension leads11is bent so as to allow the die pad10to be down-set. Thus, as shown inFIG. 1, the die pad10of this embodiment is disposed below inner lead portions21b(the one end portions of the lead terminals21) described later.

The lead terminals21are formed of a copper-based material (copper or copper alloy) such as phosphor bronze or oxygen-free copper. As shown inFIGS. 1 and 4, each of the lead terminals21includes an outer lead portion21a, which is located outside the sealing-resin layer40, and an inner lead portion21b, which together with the semiconductor chip1is covered with the sealing-resin layer40. With the lead terminals21bent into a gull-wing like shape as shown inFIG. 1, the outer lead portions21aare mounted via a solder layer45on a mount target board50.

The plurality of lead terminals21are arranged so as to be separated from one another and to surround the die pad10from four directions as shown inFIG. 4. More specifically, the lead terminals21are divided into four groups each having a predetermined number thereof, and those four groups each including the predetermined number of lead terminals21are arranged so as to surround the die pad10from four directions. Each of the lead terminals21is arranged such that the inner lead portion21b(the one end portion of the lead terminal21) thereof are disposed toward the semiconductor chip1. By arranging the plurality of lead terminals21as described above, a predetermined number out of the plurality of lead terminals21in the gull-wing like shape are pulled out in each of the four directions.

In this embodiment, as shown inFIGS. 1 and 2, with the semiconductor chip1mounted on the upper surface of the die pad10, the upper surface of the semiconductor chip1is at substantially a same height as the upper surfaces of the inner lead portions21bin a Z-axis direction (a thickness direction of the semiconductor chip1). On the upper surfaces of the inner lead portions21band on the upper surfaces of the electrode pads2of the semiconductor chip1, metal stud bumps4and5are formed, respectively, that have a predetermined height and are made of gold (Au). The metal stud bumps4and5are an example of “metal bumps” and “stud bumps” according to the present invention. On the surfaces of the metal stud bumps4and5, a plated-tin (Sn) layer (not shown) is formed.

As shown inFIG. 3, the sheet-form wiring member30has a structure in which plurality of wiring layers32insulatively separated from one another are formed on a main surface on one side of the sheet-form wiring member (the sheet-form polyimide member31). This sheet-form wiring member30(polyimide member31) has a rectangular shape as seen in a plan view. The sheet-form wiring member30(polyimide member31) is formed so as to have an area smaller than that of the sealing-resin layer40described later. On the other hand, the wiring layers32are each composed of a gold (Au) layer having a thickness of about 30 μm and are formed, by a deposition method or the like, into a wiring pattern that allows the inner lead portions21bto be electrically connected to the electrode pads2corresponding thereto, respectively. Note that the wiring layers32are an example of “conductors” according to the present invention.

Moreover, in this embodiment, the lead terminals21and the semiconductor chip1are electrically connected to each other via the wiring layers32of the wiring member30described above. More specifically, as shown inFIG. 2, one and the other end portions of the wiring layers32are fixed to the metal stud bumps4formed on the inner lead portions21band to the metal stud bumps5formed on the electrode pads2, respectively, by heat-press bonding (gold-tin eutectic bonding). Thereby, the inner lead portions21bof the lead terminals21and the electrode pads2of the semiconductor chip1are electrically connected respectively to each other via the wiring layers32.

The sealing-resin layer40is formed of, for example, heat-curing resin such as epoxy resin and has a function of protecting the semiconductor chip1and the wiring member30against gas or moisture by resin-sealing the semiconductor chip1and the wiring member30. Moreover, seen in a plan view as inFIG. 4, the sealing-resin layer40is formed in a rectangular shape. That is, the sealing-resin layer40has four sides as seen in a plan view. At each of the four sides of the rectangular sealing-resin layer40, the predetermined number of lead terminals21(outer lead portions21a) protrude.

In this embodiment, as described above, the semiconductor device includes the sheet-form wiring member30having the plurality of wiring layers32insulated from one another on the main surface on the one side thereof. The electrode pads2and the inner lead portions21bof the lead terminals21are electrically connected respectively to each other via the wiring layers32of that wiring member30. Thereby, unlike a case where the bonding wires are used for the electrical connection between the electrode pads2of the semiconductor chip1and the inner lead portions21bof the lead terminals21, the occurrence of a problem such as wire sweep can be suppressed. That is, during the resin-sealing process of sealing the semiconductor chip1with the sealing-resin layer40, the wiring layers32disposed on the sheet-form wiring member30are difficult to deform in a flow direction of the sealing resin as compared with the bonding wires. Even in a case where the distances between the electrode pads2and the inner lead portions21bcorresponding thereto are lengthened and the pitches of the wiring layers32are narrowed with the increasing numbers of pins and finer pitches, a short-circuit between the adjacent wiring layers32can be prevented. Consequently, even in a case where even larger numbers of pins and even finer pitches are to be coped with, it is possible to suppress the lowering of the manufacturing yield and reliability of the semiconductor device.

Moreover, in this embodiment, the metal stud bumps4and5are formed on the inner lead portions21bof the lead terminals21and the electrode pads2of the semiconductor chip1, respectively. Thereby, the wiring layers32of the wiring member30can be electrically connected to the electrode pads2of the semiconductor chip1and the inner lead portions21bof the lead terminal21with ease, respectively, so that the electrical connections can be made between the electrode pads2of the semiconductor chip1and the inner lead portions21bof the lead terminal21via the wiring layer32with ease. Consequently, it is possible to cope with even larger numbers of pins and finer pitches while suppressing the manufacturing yield and reliability of the semiconductor device with ease.

Furthermore, in this embodiment, the semiconductor device is structured such that the upper surfaces of the inner lead portions21bare at substantially the same height as the upper surface of the semiconductor chip1in the thickness direction (the Z-axis direction) of the semiconductor chip1. Thereby, the electrode pads2of the semiconductor chip1and the inner lead portions21bof the lead terminals21can be electrically connected respectively to each other via the wiring layers32of the wiring members30with more ease. Consequently, it is possible to cope with even larger numbers of pins and finer pitches while suppressing the lowering of the manufacturing yield and reliability of the semiconductor device with more ease.

Furthermore, in this embodiment, the semiconductor device is formed into a QFP type package by sealing the semiconductor chip1in the sealing-resin layer40. Thereby, it is possible to easily obtain semiconductor devices that can cope with even larger numbers of pins and finer pitches while suppressing the lowering of the manufacturing yield and reliability.

Next, a method for manufacturing the semiconductor device in accordance with this embodiment of the present invention will be described with reference toFIG. 1andFIGS. 5 to 10.

First, as shown inFIG. 6, the lead frame20is integrally formed by performing punch-press or etching processing on a thin plate composed of a copper-based material (copper or copper alloy) such as phosphor bronze or oxygen-free copper. In this processing, the lead frame20is formed so as to include the plurality of lead terminals21, dam portions22and positioning holes23. Note that the lead frame20is formed so as not to include the die pad10.

Thereafter, the metal stud bump4composed of gold (Au) is formed on the upper surfaces of the inner lead portions21bof the lead frame20. The die pad10is then formed, as a separate member from the lead frame20, by performing punch-press or etching processing on a thin plate composed of copper-based material (copper or copper alloy) such as phosphor bronze or oxygen-free copper. In this processing, the die pad10is formed in a rectangular shape as seen in a plan view, and as shown inFIGS. 5 and 7, the suspension leads11are formed at the four corners of the die pad10integrally therewith so as to extend in a radial pattern as seen in a plan view.

Subsequently, the metal stud bump5composed of gold (Au) is formed on the upper surfaces of the electrode pads2of the semiconductor chip1, and then the semiconductor chip1is mounted on the upper surface of the die pad10via the adhesive layer3as shown inFIG. 5.

Thereafter, the four suspension leads11are bent and the tip ends thereof are connected to predetermined positions on the lead frame20as shown inFIG. 7. Thereby, the die pad10is connected to the lead frame20, with the former arranged below the inner lead portions21b, so that the upper surface of the semiconductor chip1is at substantially the same height as the upper surfaces of the inner lead portions21bin the Z-axis direction (the thickness direction of the semiconductor chip1) as shown inFIG. 8.

Thereafter, as shown inFIGS. 8 and 9, the electrode pads2of the semiconductor chip1and the inner lead portions21bare electrically connected respectively to each other via the wiring layers32of the wiring member30. More specifically, the sheet-form wiring member30is disposed on the semiconductor chip1such that the wiring layers32face the semiconductor chip1. The wiring member30is then positioned such that the one end portions of the wiring layers32make contact with the metal stud bumps4of the inner lead portions21b, and that the second ends of the layers32make contact with the metal stud bumps5of the electrode pads2. And by using an apparatus such as a heat-press bonding apparatus, the one and the other end portions of the wiring layers32are bonded by heat-press bonding (gold-tin eutectic bonding) to the metal stud bumps4of the inner lead portions21band the metal stud bumps5of the electrode pads2, respectively, so that the wiring layers32and the metal stud bumps4and5are fixed together.

Subsequently, by using an apparatus such as a transfer molding apparatus, the semiconductor chip1, the die pad10, the sheet-form wiring member30and the inner lead portions21bof the lead terminals21are sealed in the sealing-resin layer40as shown inFIG. 10.

Thereafter, parts of the suspension leads11protruding from the sealing-resin layer40, the lead terminals21(outer lead portions21a) and the dam portions22are all cut off. Finally, the outer lead portions21aare bent in a gull-wing like shape outside the resin layer40. In this manner, the semiconductor device in accordance with this embodiment of the present invention shown inFIG. 1is manufactured.

The embodiment disclosed herein is to be considered in all respects as illustrative and not restrictive. The scope of the present invention is set out in the appended claims and not in the description of the embodiment hereinabove, and includes any changes or modifications within the sense and scope equivalent to those of the claims.

For instance, although the above-described embodiment deals with an example in which the invention is applied to a QFP type semiconductor device, this is not intended to limit the application of the invention; the invention may be applied to BGA (Ball Grid Array) type semiconductor devices, QFN (Quad Flat Non-Leaded Package) type semiconductor devices and the like. Also, a semiconductor device of the present invention may be formed into any type of package other than those mentioned above.

Moreover, although the above-described embodiment deals with an example in which the wiring layers and the stud bumps are composed of gold (Au), this is not intended to limit the invention; the wiring layers and the stud bumps may also be composed of any conductive material other than gold (Au). For example, the wiring layers and the stud bumps may be composed of copper (Cu). Note that in this case it is possible to obtain the benefit of effectively reducing the manufacturing costs.

Furthermore, although the above-described embodiment deals with an example in which the metal stud bumps are formed on the upper surfaces of the inner lead portions and on the upper surfaces of the electrode pads, this is not intended to limit the invention; the invention may also be feasible without the metal stud bumps formed on the upper surfaces of the inner lead portions and on the upper surfaces of the electrode pads. Instead of the metal stud bumps, a plated layer with a larger thickness may be formed on predetermined portions on the upper surfaces of the inner lead portions.

Moreover, although the above-described embodiment deals with an example in which the wiring member is formed using a sheet-form polyimide member, this is not intended to limit the invention; the wiring member of the invention may be formed using any insulating member other than a polyimide member.

Moreover, although the above-described embodiment deals with an example in which the semiconductor device is structured such that the main surface of the semiconductor chip are at substantially the same height as the upper surfaces of the inner lead portions in the Z-axis direction (the thickness direction of the semiconductor chip), this is not intended to limit the invention; the semiconductor device of the invention may also be structured such that the upper surface of the semiconductor chip is at a different height from the upper surfaces of the inner lead portions.

Moreover, although the above-described embodiment deals with an example in which the die pad is formed of the same material as the lead frame, this is not intended to limit the invention; the die pad of the invention may also be formed of any material other than that of the lead frame. For example, it may be formed of 42 alloy or Kovar alloy.