Semiconductor device

A semiconductor device may include a cooling unit, the cooling unit including a circuit unit, a first flow path member comprised of an insulating material, and a second flow path member comprised of an insulating material. The circuit unit may include a heat sink layer, a wiring layer, and a semiconductor element that is disposed between the heat sink layer and the wiring layer. The circuit unit is disposed between the first flow path member and the second flow path member. The wiring layer may face the first flow path member or the second flow path member.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a national stage entry according to 35 U.S.C. 371 of PCT Application No. PCT/JP2017/015404 filed on Apr. 14, 2017, which claims priority to Japanese Application No. 2016-082526 filed on Apr. 15, 2016, which are entirely incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device.

BACKGROUND

A semiconductor device for high power is widely used as a power conversion device for railway vehicles, etc. Examples of such a semiconductor device include an inverter using semiconductor elements such as an IGBT (Insulated Gate Bipolar Transistor) and an FWD (Free Wheeling Diode). In the case of a semiconductor device for high power, heating value due to switching loss or conduction loss becomes enormous, and thus it is necessary to take measures for cooling.

For example, in the semiconductor device disclosed in Japanese Unexamined Patent Publication JP-A 2008-103623 (Patent Literature 1), a semiconductor element is sandwiched between two lead frames, and a ceramic tube having a coolant flow path for flowing a coolant is provided on the outside of each lead frame. The semiconductor element and a signal line are connected by wire bonding.

SUMMARY

A semiconductor device may include a cooling unit, the cooling unit including a circuit unit, a first flow path member comprised of an insulating material, and a second flow path member comprised of an insulating material. The circuit unit may include a heat sink layer, a wiring layer, and a semiconductor element that is disposed between the heat sink layer and the wiring layer. The circuit unit is disposed between the first flow path member and the second flow path member. The wiring layer may face the first flow path member or the second flow path member.

DETAILED DESCRIPTION

In a semiconductor device, when heat exchange is performed between a coolant flowing through a ceramic tube and a semiconductor element via a lead frame, it is possible to cool the semiconductor element. However, wire bonding, which is the wiring for exchanging signals, is not in contact with the ceramic tube, and thus the cooling of the wire bonding is insufficient. Since the wire bonding carries heat, there is a possibility of occurrence of a problem that the semiconductor element does not function properly.

A semiconductor device of the present disclosure can efficiently cool the semiconductor element, and can also efficiently remove heat of the wiring layer for exchanging signals.

The semiconductor devices of the present disclosure will be described below with reference to the drawings. However, only constituent members necessary for explaining the features of the semiconductor devices of the present disclosure are shown in each of the following drawings for reference. Therefore, the semiconductor devices of the present disclosure may further include well-known constituent members not shown in each drawing.

FIG. 1is a cross-sectional view schematically showing a first non-limiting embodiment of a semiconductor device of the present disclosure.

In a semiconductor device100shown inFIG. 1, a circuit unit10including a heat sink layer13, wiring layers16ato16d, and a semiconductor element14disposed between the heat sink layer13and the wiring layers16ato16dis sandwiched between a first flow path member11and a second flow path member21.

The first flow path member11and the second flow path member21include coolant flow paths12and22, respectively, for flowing a cooling medium (hereinafter also referred to as “coolant”) inside. Any coolable liquid and gas may be used as the coolant. For example, as a liquid coolant, pure water, Galden™ and the like may be used, and an anti-rust agent may be added. In this way, by flowing a coolant through the coolant flow paths12and22, the circuit unit10can be cooled from both sides thereof. In the circuit unit10, since the wiring layers16ato16dface the second flow path member21, heat generated in the wiring layers16ato16dduring signal exchange can be efficiently removed. Therefore, in the semiconductor device100of the present disclosure, deterioration of the function possessed by the semiconductor element14is little. Moreover, since the heat sink layer13faces the first flow path member11, the semiconductor element14can be efficiently cooled via the wiring layers16ato16dand the heat sink layer13.

In addition, the first flow path member11and the second flow path member21are formed of an insulating material, and thus it is possible to directly form the wiring layers16ato16dand the heat sink layer13, and heat of the wiring layers16ato16dand the heat sink layer13can be delivered to the first flow path member11and the second flow path member21immediately.

For example, insulating material may be ceramics such as alumina ceramics, alumina-zirconia composite ceramics, aluminum nitride ceramics, and silicon nitride ceramics. In particular, since silicon nitride ceramics have both excellent thermal conductivity and mechanical strength, by forming the first flow path member11and the second flow path member21with silicon nitride ceramics, the semiconductor device100of the present disclosure can have both excellent cooling efficiency and mechanical strength.

For example, a silicon nitride ceramic may contain 70% by mass or more of silicon nitride out of 100% by mass of all components constituting the silicon nitride ceramic. The materials of the first flow path member11and the second flow path member21can be confirmed by the following method. First, measurement is performed using an X-ray diffraction apparatus (XRD), and the obtained value of 2θ (2θ is the diffraction angle) is identified with a JCPDS card. Next, quantitative analysis of each component is carried out using an ICP (Inductively Coupled Plasma) emission spectrophotometric analyzer (ICP) or an X-ray fluorescence analyzer (XRF). For example, in the XRD, when the presence of silicon nitride is confirmed and the content of silicon nitride (Si3N4) converted from the content of silicon (Si) measured by ICP or XRF is 70% by mass or more, the material is a silicon nitride ceramic. The same applies to other ceramics.

The first flow path member11and the second flow path member21may be formed with ceramics by various methods, including, for example, an extrusion method of preparing a metallic mold and extruding a green body, a lamination method of laminating and making green sheets, etc. In the lamination method, the structures of the coolant flow paths12and22can be freely designed.

FIG. 2Ais a schematic front view of a circuit unit of the first non-limiting embodiment of a semiconductor device of the present disclosure.FIG. 2Ashows a view as seen towards the wiring layers16ato16dwith the first flow path member11removed. Further,FIG. 2Ashows a state in which the wiring layers16ato16dare connected to the semiconductor element (for example, IGBT)14via brazing materials or solders15ato15din the four wiring layers16ato16dconstituted in the same manner. InFIG. 2A, the brazing materials or solders15ato15d, which are hidden constituents, are indicated by broken lines.

In addition,FIG. 2Bis a schematic rear view of the circuit unit of the first non-limiting embodiment of a semiconductor device of the present disclosure, and is a view corresponding toFIG. 2A. InFIG. 2B, the semiconductor element14and part of the wiring layers16ato16d, which are hidden and partially hidden, are indicated by broken lines.

Further,FIG. 2Cis a schematic view of a modified example of the circuit unit of the first non-limiting embodiment of a semiconductor device of the present disclosure as seen from the side. A modified example10aofFIG. 2Cshows a case where a collector of the semiconductor element14is on the heat sink layer13side, a gate of the semiconductor element14is on the wiring layer16aside, an emitter of the semiconductor element14is on the wiring layer16eside, the collector of the semiconductor element14is connected to the heat sink layer13, the gate of the semiconductor element14is connected to the wiring layer16avia the brazing material or the solder15a, and the emitter of the semiconductor element14is connected to the wiring layer16e. When the semiconductor element14is an IGBT, by providing another wiring layer on the second flow path member21and connecting the another wiring layer to the collector and the emitter of the semiconductor element14, the semiconductor element14can function as an IGBT power module.

The wiring layers16ato16dincluded in the circuit unit10are wirings or terminals for establishing the connection with external devices, signal terminals, etc. The heat sink layer13included in the circuit unit10is a member for delivering heat of the semiconductor element14to the first flow path member11. The heat sink layer13may also function as an electrode. The semiconductor element14is, for example, an IGBT (Insulated Gate Bipolar Transistor) or an FWD (Free Wheeling Diode), and may have another circuit element such as a capacitor and a resistor.

The wiring layers16ato16dand the heat sink layer13included in the circuit unit10may be formed of metal. When the wiring layers16ato16dand the heat sink layer13are formed of copper, copper alloy, aluminum, aluminum alloy or the like among metals, they have excellent thermal conductivity. As shown inFIG. 1, the wiring layers16ato16dmay be connected to the semiconductor element14via brazing materials or solders15ato15d. Similarly, although not shown in the drawing, the heat sink layer13may be connected to the semiconductor element14via a brazing material, a solder, or a nano metal paste containing gold, silver, or copper as a main component. As the brazing materials or the solders15ato15d, a publicly known material may be used. For example, a silver-based brazing material or a tin-based solder may be used.

The wiring layers16ato16dand the heat sink layer13(hereinafter generally referred to as a metal layer in some cases) may be formed by various methods, including for example, a DBC (Direct Bond Copper) method or a DBA (Direct Bond Aluminum) method in which a metal plate such as a copper plate and an aluminum plate is directly adhered to the first flow path member11or the second flow path member21, an AMB (Active Metal Bonding) method in which a metal plate is bonded via a silver and copper brazing material in which an active metal such as titanium, zirconium, hafnium, and niobium is added, a printing method of forming using a paste containing a metal component as a main component, a sputtering method of forming a metal layer by sputtering using titanium or chromium as an underlayer, a plating method of forming a metal layer using titanium or chromium as an underlayer, or after fine unevenness is formed, etc.

For example, in the case of using the plating method, thermal stress is not applied when a metal layer is formed on the first flow path member11and the second flow path member21, and thus it is possible to obtain a semiconductor device100in which cracking is less prone to occur even in a long-term thermal cycle, and it is possible to enhance reliability.

FIG. 3Ais a cross-sectional view schematically showing a second non-limiting embodiment of a semiconductor device of the present disclosure. For example, a circuit unit20of a semiconductor device200may be a circuit unit having the same laminated structure as the circuit unit10, and similarly, wiring layers26ato26dface the first flow path member11and are efficiently cooled.

The circuit units10and20do not necessarily need to have the same laminated structure. For example, even when the elements or members forming each layer may be partially different in the circuit units10and20, for example, the thicknesses of the heat sink layers13and23may be varied, so that the heat sink layers may be configured so as to mitigate the effects of the difference in thicknesses of the other elements or members of the circuit units and the like and the circuit units can be fitted between the first flow path member11and the second flow path member21without causing stress distortion.

For example, as shown inFIG. 3A, the circuit unit10and the circuit unit20are arranged adjacent to each other with the top and bottom of one being opposite to those of the other, that is, the laminating orders are opposite as “heat sink layer→semiconductor element→wiring layer” and “wiring layer→semiconductor element→heat sink layer”. In other words, in the arrangement defined by a direction from the first flow path member11to the second flow path member21inFIG. 3A, the first circuit unit10comprises the heat sink layer13, the semiconductor element14, and the wiring layers16ato16dwhich are arranged in this order, and the second circuit unit20comprises the wiring layers26ato26d, the semiconductor element24, and the heat sink layer23which are arranged in this order. Since the two circuit units10and20are positioned adjacent to each other in the semiconductor device200, the wiring layers16ato16dand the wiring layers26ato26dcan be efficiently cooled because they face the first flow path member11or the second flow path member21. Furthermore, by arranging the adjacent circuit units10and20laminated oppositely, it is possible to balance heat and thermal stress.

Generally, since ceramics and metal have different thermal expansion coefficients, thermal stress is generated due to this difference. However, as shown inFIG. 3A, by laminating the adjacent circuit units10and20with the top and bottom reverse to each other, it is possible to avoid a situation in which the aforementioned thermal stresses are superimposed and to minimize the adverse effect thereof. The adjacent circuit units10and20are not limited to two but also may be three, and they may be arranged in front and rear. Moreover, a plurality of circuit units may be arranged in front, rear, left and right. In fabricating a semiconductor device200as shown inFIG. 3A, first, the heat sink layers13and23and the wiring layers16ato16d,26ato26dare respectively formed on the first flow path member11and the second flow path member21. Then, after the semiconductor elements14and24are respectively bonded to the heat sink layers13and23via a brazing material, a solder, or a nano metal paste and the brazing material or the solders15ato15dand25ato25dare disposed to predetermined positions of the wiring layers16ato16dand26ato26d, the first flow path member11and the second flow path member21are laminated, and by passing through a solder reflow process, the semiconductor device200can be efficiently produced.

FIG. 3Bis a cross-sectional view schematically showing a third non-limiting embodiment of a semiconductor device of the present disclosure. A semiconductor device201ofFIG. 3Bmay be the semiconductor device200ofFIG. 3Athat is additionally provided with connecting pipes51and61. In order to join the connecting pipes51and61to the first flow path member11or the second flow path member21, an adhesive layer15eis provided between the respective opposing surfaces of the connecting pipes51,61and the first flow path member11or the second flow path member21. The adhesive layer15eis formed by passing through a solder reflow process after applying an adhesive (for example, a silicon-based brazing material or a polyimide-based adhesive) between the connecting pipes51,61and the first flow path member11or the second flow path member21. In this way, the joining of the connecting pipes51,61becomes possible simultaneously with soldering (or applying a brazing material) between the semiconductor elements14,24and the wiring layers16ato16d,26ato26d.

For example, a semiconductor device201of the present disclosure may have an adhesive layer15ebetween the respective opposing surfaces of the connecting pipes51,61and the first flow path member11or the second flow path member21. However, a part of the adhesive layer15emay be positioned from the outer peripheral surfaces of the connecting pipes51and61to the first flow path member11or the second flow path member21. The outer peripheral surfaces of the connecting pipes51and61are surfaces adjacent to the opposing surfaces. When such a structure is satisfied, a coolant flowing through the coolant flow paths52and62can be inhibited from leaking from between the connecting pipes51,61and the first flow path member11or the second flow path member21by the adhesive layer15e. In addition, when a part of the adhesive layer15eis positioned from the inner surfaces of the coolant flow paths52and62of the connecting pipes51and61to the first flow path member11or the second flow path member21, the coolant flowing through the coolant flow paths52and62can also be inhibited from leaking from between the connecting pipes51,61and the first flow path member11or the second flow path member21.

FIG. 4is a cross-sectional view schematically showing a fourth non-limiting embodiment of a semiconductor device of the present disclosure. A semiconductor device300as shown inFIG. 4has a structure in which two semiconductor devices201ofFIG. 3Bare stacked vertically and further a pipe91for inflow of the coolant and a pipe101for outflow of the coolant are added, and the coolant circulates inside each coolant flow path. A cooling unit19may include a first flow path member11, circuit units10and20, and a second flow path member21. Similarly, another cooling unit39may include a first flow path member31, circuit units30and40, and a second flow path member41. As shown inFIG. 4, the first flow path member11and the second flow path member41are members shared by the cooling units19and39. As shown inFIG. 4, the circuit units10,20,30and40may have the same laminated structures. However, they do not necessarily need to have the same laminated structures.

As another feature of the semiconductor device300, by connecting the second flow path member21and the first flow path member11(also referred to as the second flow path member41) and the first flow path member31with connecting pipes51,61,71and81, a three-dimensional cooling unit can be formed and it is possible to balance heat and stress even in this case. Further, by disposing a brazing material paste or the like at a predetermined place and performing a heat treatment or the like, it is possible to constitute a stack type power module, and it is possible to realize a semiconductor device300with high cooling efficiency while having a high density circuit.

FIG. 5is a cross-sectional view schematically showing a fifth non-limiting embodiment of a semiconductor device of the present disclosure. A semiconductor device400as shown inFIG. 5may include connecting pipes that are integrated. By preparing in advance a pipe111having a notch112and connecting it with the aforementioned cooling unit, it is possible to easily construct a stack type power module. In fabricating a semiconductor device400as shown inFIG. 5, it is possible to easily insert the pipe111positioned across a plurality of flow path members by preparing a ring-shaped spacer and arranging the spacer at a position corresponding to the notch112between a plurality of flow path members. Such a ring-shaped spacer also has an effect of preventing liquid leakage when the pipe111is broken.

Also in the semiconductor devices300and400, similar to the semiconductor device201, in order to join the connecting pipes51,61,71,81, the pipes91,101,111, and the ring-shaped spacer, an adhesive (for example, a silicon-based brazing material or a polyimide-based adhesive) may be applied in advance, and by passing through a solder reflow process, the joining of the connecting pipes51,61,71,81, the pipes91,101,111, and the ring-shaped spacer becomes possible simultaneously with soldering between the semiconductor elements and the wiring layers. The connecting pipes51,61,71,81, the pipes91,101,111, and the ring-shaped spacer are preferably materials that can withstand the solder reflow process, for example, metal, resin, and ceramics. As the resin, polyimide is preferable. By sealing the circuit units10,20,30and40with a resin mold, the reliability of the semiconductor devices300and400can be enhanced. A silicone gel or an epoxy resin may be used as the resin mold. In the resin mold, by resin-molding not only the circuit units10,20,30and40but also the connecting pipes51,61,71,81, the pipes91,101,111, and the ring-shaped spacer, it is possible to reinforce the joint portions between the connecting pipes51,61,71,81, the pipes91,101,111, the ring-shaped spacer and the first flow path members11,31, the second flow path members21and41.

The present disclosure may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive. Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. One skilled in the art would recognize that various features in the disclosure are not necessarily mutually exclusive, as some aspects of the disclosure may be combined with one or more other embodiments and aspects of the disclosure. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

REFERENCE SIGNS LIST

10,20,30,40: Circuit unit

11,31: First flow path member

21,41: Second flow path member

12,22,32,42: Coolant flow path

13,23: Heat sink layer

15a,15b,15c,15d: Brazing material or solder

19,39: Cooling unit

25a,25b,25c,25d: Brazing material or solder

52,62,72,82: Coolant flow path

92,102: Coolant flow path

100,200,201,300,400: Semiconductor device