Method and circuit for reducing VCO noise

A calibrated VCO for use in a phase-locked loop includes a low frequency calibration block for setting a bias signal for a ring oscillator to a center point to prompt the ring oscillator to generate an oscillation that is in the middle of its output frequency range and a high frequency VCO gm stage for generating an adjustment calibration signal that is added or subtracted to and from the bias signal created by the low frequency calibration block. A low pass filter coupled between the gates of a current mirror of the low frequency calibration block operates to filter noise and interference generated within the low frequency calibration block. Additionally, the magnitude of the bias signal produced by the low frequency calibration block is significantly greater than the adjustment bias signal generated by the high frequency VCO gm stage.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

This invention relates generally to communication systems and more particularly to high speed serial data transmissions.

2. Description of Related Art

Communication systems are known to transport large amounts of data between a plurality of end user devices, which, for example, include telephones, facsimile machines, computers, television sets, cellular telephones, personal digital assistants, etc. As is also known, such communication systems may be local area networks (LANs) and/or wide area networks (WANs) that are stand-alone communication systems or interconnected to other LANs and/or WANs as part of a public switched telephone network (PSTN), packet switched data network (PSDN), integrated service digital network (ISDN), or Internet. As is further known, communication systems include a plurality of system equipment to facilitate the transporting of data. Such system equipment includes, but is not limited to, routers, switches, bridges, gateways, protocol converters, frame relays, private branch exchanges, etc.

The transportation of data within communication systems is governed by one or more standards that ensure the integrity of data conveyances and fairness of access for data conveyances. For example, there are a variety of Ethernet standards that govern serial transmissions within a communication system at data rates of 10 megabits per second, 100 megabits per second, 1 gigabit per second and beyond. Synchronous Optical NETwork (SONET), for example, requires 10 gigabits per second. In accordance with such standards, many system components and end user devices of a communication system transport data via serial transmission paths. Internally, however, the system components and end user devices process data in a parallel manner. As such, each system component and end user device must receive the serial data and convert the serial data into parallel data without loss of information.

Accurate recovery of information from high-speed serial transmissions typically requires transceiver components that operate at clock speeds equal to or higher than the received serial data rate. Higher clock speeds limit the usefulness of prior art clock recovery circuits that require precise alignment of signals to recover clock and/or data. Higher data rates require greater bandwidth for a feedback loop of the recovery circuits to operate correctly. Some prior art designs are bandwidth limited.

As the demand for data throughput increases, so do the demands on a high-speed serial transceiver. The increased throughput demands are pushing some current integrated circuit manufacturing processes to their operating limits, where integrated circuit processing limits (e.g., device parasitics, trace sizes, propagation delays, device sizes, etc.) and integrated circuit (IC) fabrication limits (e.g., IC layout, frequency response of the packaging, frequency response of bonding wires, etc.) limit the speed at which the high-speed serial transceiver may operate without excessive jitter performance and/or noise performance.

A further alternative for high-speed serial transceivers is to use an IC technology that inherently provides for greater speeds. For instance, switching from a Complementary Metal Oxide Semiconductor (CMOS) process to a silicon germanium or gallium arsenide process would allow integrated circuit transceivers to operate at greater speeds, but at substantially increased manufacturing costs. CMOS is more cost effective and provides easier system integration. Currently, for most commercial-grade applications, including communication systems, such alternate integrated circuit fabrication processes are too cost prohibitive for wide spread use.

Modern communication systems, including high data rate, wire lined and wireless communication systems, typically include a phase locked loop for generating an oscillation that is used to drive clock rates, set transmission frequencies, and for down-converting received radio frequency transmissions to baseband frequencies. While there are many different designs for generating a clock or reconstructing a clock from a received data signal, the designs typically involve circuitry that increases or decreases a bias signal to a device that generates the local oscillation. Noise and interference, however, often affect the magnitude of a bias signal thereby resulting in local oscillations whose frequencies are not as accurate as desired. What is needed, therefore, is an apparatus and method that provide accurate or improved local oscillation signals by eliminating or reducing noise that contribute to error.

BRIEF SUMMARY OF THE INVENTION

A voltage controlled oscillator (VCO) of a phase locked loop (PLL) includes a ring oscillator for producing an oscillation and circuitry that calibrates the ring oscillator in a manner that reduces the affects of interference and noise upon a bias signal magnitude and therefore upon an output local oscillation. The preferred embodiment of the VCO includes a low frequency calibration circuit that produces a steady state low frequency bias signal to the ring oscillator and a high frequency VCO transconductance stage that produces a high frequency bias signal to the ring oscillator. The high frequency bias signal is an adjustment bias signal to the low frequency bias signal and is superimposed therewith. Stated differently, the low frequency bias signal compensates for error due to process variations, temperature change and corresponding operational characteristics, and other similar types of error while the high frequency bias signal is added to allow the PLL to adjust the VCO to track the reference clock under ordinary PLL operations.

In the described embodiment of the invention, both the low frequency calibration circuit and the high frequency VCO transconductance stage are coupled to receive a control voltage. The low frequency calibration circuit generates a steady state bias signal for the ring oscillator based upon the magnitude of the control voltage, while the high frequency VCO transconductance stage sinks or sources current from the bias signal according to changes in the control voltage magnitude.

The low frequency calibration circuit is formed to provide high levels of gain and to be significantly larger than the bias signal produced by the high frequency VCO transconductance stage. In one embodiment of the invention, the low frequency calibration circuit generates a bias signal whose magnitude is approximately 10 times greater than a magnitude of the high frequency bias signal. Further, because the low frequency calibration circuit comprises a low pass filter that is coupled as close as possible to the ring oscillator (electrically close), the noise introduced into the bias signal is only introduced in the high frequency VCO transconductance stage. Because, however, the relative magnitude of the high frequency bias signal is so much smaller than the low frequency bias signal, the error introduced therefrom is proportionately very small, thereby minimizing the introduction of error into the local oscillation. Generally, because the low frequency calibration circuit includes a low pass filter, and because of the scaling between the low frequency bias signal and the high frequency bias signal, error due to noise and interference is minimized.

A method of the present invention includes producing an oscillation by receiving a control voltage from a control voltage source and by producing a steady state bias signal and an adjustment bias signal responsive to the control voltage magnitude. The adjustment bias signal and the steady state bias signal are then summed to create a bias signal that results in a corresponding local oscillation. As one aspect of the present invention, the steady state bias signal has a magnitude that is at least a multiple of the adjustment bias signal in terms of magnitude. Further, the steady state bias signal is filtered thereby resulting in the introduction of noise only from the adjustment bias signal. In one embodiment, the multiple is equal to at least five.

With respect to the adjustment bias signal, the invention includes either sinking current from a node carrying the steady state bias signal or sourcing current into the node that carries the steady state bias signal. Accordingly, biased differential current mirror circuitry operates to sink or source the current to adjust the steady state bias signal level to produce a corresponding adjustment in an oscillation of a ring oscillator that is coupled to receive the bias signal.

The preferred embodiment of the VCO, as stated before, may be used for a number of applications. Typically, such VCO is used as a part of a phase-lockedphase locked loop. Accordingly, a preferred embodiment of the phase-locked loop comprises a phase frequency detector that generates an adjustment signal based on the relative difference in phase or frequency of two signals, a charge pump that is coupled to receive the control signals from the phase frequency detector to sink or source current from a loop filter responsive to the control signals received from the phase frequency detector and a voltage controlled oscillator that is coupled to receive a voltage signal from the loop filter wherein the voltage controlled oscillator produces the local oscillation. In the described embodiment of the invention, the voltage controlled oscillator is formed as described herein so as to minimize the adverse affects of noise and interference produced within the VCO.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a schematic block diagram of a programmable logic device10that includes programmable logic fabric12, a plurality of programmable multi-gigabit transceivers (PMGTS)14–28and a control module30. The programmable logic device10may be a programmable logic array device, a programmable array logic device, an erasable programmable logic device, and/or a field programmable gate array (FPGA). When the programmable logic device10is an field programmable gate array (FPGA), the programmable logic fabric12may be implemented as a symmetric array configuration, a row-based configuration, a sea-of-gates configuration, and/or a hierarchical programmable logic device configuration. The programmable logic fabric12may further include at least one dedicated fixed processor, such as a microprocessor core, to further facilitate the programmable flexibility offered by programmable logic device10.

The control module30may be contained within the programmable logic fabric12or it may be a separate module. In either implementation, the control module30generates the control signals to program each of the transmit and receive sections of the programmable multi-gigabit transceivers14–28. In general, each of the programmable multi-gigabit transceivers14–28performs a serial-to-parallel conversion on received data and performs a parallel-to-serial conversion on transmit data. The parallel data may be 8-bits, 16-bits, 32-bits, 64-bits, etc.

Typically, the serial data will be a 1-bit stream of data that may be a binary level signal, multi-level signal, etc. Further, two or more programmable multi-gigabit transceivers may be bonded together to provide greater transmitting speeds. For example, if PMGTs14,16and18are transceiving data at 3.125 gigabits-per-second, the PMGTs14–18may be bonded together such that the effective serial rate is 3 times 3.125 gigabits-per-second.

Each of the programmable multi-gigabit transceivers14–28may be individually programmed to conform to separate standards. In addition, the transmit path and receive path of each programmable multi-gigabit transceiver14–28may be separately programmed such that the transmit path of a transceiver is supporting one standard while the receive path of the same transceiver is supporting a different standard. Further, the serial rates of the transmit path and receive path may be programmed from 1 gigabit-per-second to tens of gigabits-per-second. The size of the parallel data in the transmit and receive sections, or paths, is also programmable and may vary from 8-bits, 16-bits, 32-bits, 64-bits, etc.

FIG. 2is a schematic block diagram of one embodiment representing one of the programmable multi-gigabit transceivers14–28. As shown, the programmable multi-gigabit transceiver includes a programmable physical media attachment (PMA) module32, a programmable physical coding sub-layer (PCS) module34, a programmable interface36, a control module35, a PMA memory mapping register45and a PCS register55. The control module35, based on the desired mode of operation for the individual programmable multi-gigabit transceivers14–28, generates a programmed deserialization setting66, a programmed serialization setting64, a receive PNA_PCS interface setting62, a transmit PMA_PCS interface setting60, and a logic interface setting58. The control module35may be a separate device within each of the programmable multi-gigabit transceivers and/or included within the control module30(ofFIG. 1). In either embodiment of the control module35, the programmable logic device control module30determines the corresponding overall desired operating conditions for the programmable logic device10(ofFIG. 1) and provides the corresponding operating parameters for a given programmable multi-gigabit transceiver to its control module35, which generates the settings58–66.

The programmable physical media attachment (PMA) module32includes a programmable transmit PMA module38and a programmable receive PMA module40. The programmable transmit PMA module38is operably coupled to convert transmit parallel data48into transmit serial data50in accordance with the programmed serialization setting64. The programmed serialization setting64indicates the desired rate of the transmit serial data50, the desired rate of the transmit parallel data48, and the data width of the transmit parallel data48. The programmable receive PMA module40is operably coupled to convert receive serial data52into receive parallel data54based on the programmed deserialization setting66. The programmed deserialization setting66indicates the rate of the receive serial data52, the desired rate of the receive parallel data54, and the data width of the receive parallel data54. The PMA memory mapping register45may store the programmed serialization setting64and the programmed deserialization setting66.

The programmable physical coding sub-layer (PCS) module34includes a programmable transmit PCS module42and a programmable receive PCS module44. The programmable transmit PCS module42receives transmit data words46from the programmable logic fabric12via the programmable interface36and converts them into the transmit parallel data48in accordance with the transmit PMA_PCS interface setting60. The transmit PMA_PCS interface setting60indicates the rate of the transmit data words46, the size of the transmit data words (e.g., 1-byte, 2-bytes, 3-bytes, 4-bytes, etc.) and the corresponding transmission rate of the transmit parallel data48. The programmable receive PCS module44converts the receive parallel data54into received data words56in accordance with the receive PMA_PCS interface setting62. The receive PMA_PCS interface setting62indicates the rate at which the receive parallel data54will be received, the width of the receive parallel data54, the transmit rate of the receive data words56and the word size of the receive data words56.

The control module35also generates the logic interface setting58that provides the rates at which the transmit data words46and receive data words56will be transceived with the programmable logic fabric12. Note that the transmit data words46may be received from the programmable logic fabric12at a different rate than the receive data words56are provided to the programmable logic fabric12.

As one of average skill in the art will appreciate, each of the modules within the programmable PMA module32and the programmable PCS module34may be individually programmed to support a desired data transfer rate. The data transfer rate may be in accordance with a particular standard such that the receive path, i.e., the programmable receive PMA module40and the programmable receive PCS module44may be programmed in accordance with one standard, while the transmit path, i.e., the programmable transmit PCS module42and the programmable transmit PMA module38may be programmed in accordance with another standard.

FIG. 3illustrates an alternate schematic block diagram representing one of the programmable multi-gigabit transceivers14–28. In this embodiment, the programmable multi-gigabit transceivers14–28include a transmit section70, a receive section72, the control module35and the programmable interface36. The transmit section70includes the programmable transmit PMA module38and the programmable transmit PCS module42. The receive section72includes the programmable receive PMA module40and the programmable receive PCS module44.

In this embodiment, the control module35separately programs the transmit section and the receive section via transmit setting74and receive setting76, respectively. The control module35also programs the programmable interface36via the logic interface setting58. Accordingly, the control module35may program the receiver section72to function in accordance with one standard while programming the transmit section70in accordance with another standard. Further, the logic interface setting58may indicate that the transmit data words46are received from the programmable logic fabric12at a different rate than the receive data words56are provided to the programmable logic fabric12. As one of average skill in the art will appreciate, the programmable interface36may include a transmit buffer and a receive buffer, and/or an elastic store buffer to facilitate the providing and receiving of the transmit data words46and the receive data words56to and from the programmable logic fabric12.

FIG. 4Aillustrates a schematic block diagram of the programmable receive PMA module40that includes a programmable front-end100, a data and clock recovery module102, and a serial-to-parallel module104. The programmable front-end100includes a receive termination circuit106and a receive amplifier108. The data and clock recovery module102includes a data detection circuit110and a phase locked loop112. The phase locked loop112includes a phase detection module114, a loop filter116, a voltage controlled oscillator (VCO)118, a 1stdivider module120, and a 2nddivider module122.

The programmable front-end100is operably coupled to receive the receive serial data52and produce amplified and equalized receive serial data124therefrom. To achieve this, the receive termination circuit106is programmed in accordance with a receive termination setting126to provide the appropriate termination for the transmission line between the programmable receive PMA module40and the source that originally transmitted the receive serial data52. The receive termination setting126may indicate whether the receive serial data52is a single-ended signal, a differential signal, may indicate the impedance of the termination line, and may indicate the biasing of the receiver termination circuit106. For a more detailed discussion of the receiver termination circuit106, refer to co-pending patent application entitled RECEIVER TERMINATION NETWORK AND APPLICATION THEREOF, by Charles W. Boecker, et al., and having the same filing date as the present application. This co-pending application is incorporated by reference, herein.

The receive termination circuit106further biases the receive serial data52and provides the bias adjusted signal to the receive amplifier108. The gain and equalization settings of the receive amplifier108may be adjusted in accordance with the equalization setting128and the amplification setting130, respectively. The receive amplifier108may be further described in co-pending patent application entitled ANALOG FRONT-END HAVING BUILT-IN EQUALIZATION AND APPLICATIONS THEREOF, by William C. Black, et al., and having a filing date the same as the present patent application. This co-pending application is incorporated by reference, herein. Note that the receive termination setting126, the equalization setting128, and the amplification setting130are part of the programmed deserialization setting66provided by the control module35.

The data and clock recovery module102receives the amplified and equalized receive serial data124via the phase detection module114of phase locked loop112and via the data detection circuit110. The phase detection module114has been initialized prior to receiving the amplified and equalized receive serial data124by comparing the phase and/or frequency of a reference clock86with a feedback reference clock produced by divider module120. Based on this phase and/or frequency difference, the phase detection module114produces a corresponding current that is provided to loop filter116. The loop filter116converts the current into a control voltage that adjusts the output frequency of the VCO118. The divider module120, based on a serial received clock setting132, divides the output oscillation produced by the VCO118to produce the feedback signal. Once the amplified and equalized receive serial data124is received, the phase detection module114compares the phase of the amplified and equalized receive serial data124with the phase of the feedback signal from divider module120. Based on a phase difference between the amplified and equalized receive serial data124and the feedback signal, a current signal is produced.

The phase detection module114provides the current signal to the loop filter116, which converts it into a control voltage that controls the output frequency of the VCO118. At this point, the output of the VCO118corresponds to a recovered clock138. The recovered clock138, which was referenced as the serial receive clock98inFIG. 4, is provided to the divider module122, the data detection circuit110and to the serial-to-parallel module104. The data detection circuit110utilizes the recovered clock138to produce recovered data136from the amplified and equalized receive serial data124. The divider module122divides the recovered clock138, in accordance with a parallel receive and programmable logic clock setting134, to produce a parallel receive clock94and a programmable logic receive clock96. Note that the serial receive clock setting132and the parallel receive and programmable logic clock setting134are part of the programmed deserialization setting66provided to the programmable receive PMA module40by the control module35.

The serial-to-parallel module104, which may include an elastic store buffer, receives the recovered data136at a serial rate in accordance with the recovered clock138. Based on a serial-to-parallel setting135and the parallel receive clock94, the serial-to-parallel module104outputs the receive parallel data54. The serial-to-parallel setting135, which may be part of the programmed deserialization setting66, indicates the rate and data width of the receive parallel data54.

FIG. 4Billustrates a schematic block diagram of a programmable transmit PMA module38that includes a phase locked loop144, a parallel-to-serial module140, and a line driver142. The phase locked loop144includes a phase detection module146, a charge pump147, a loop filter148, a voltage control oscillator (VCO)150, a divider module154, and a divider module152.

The phase detection module146compares the phase and/or frequency of the reference clock86with the phase and/or frequency of a feedback oscillation produced by divider module154. The phase detection module146generates control signals to charge pump147which, in turn, produces a current signal to represent the phase and/or frequency difference between the reference clock86and the feedback oscillation in one embodiment of the invention. The loop filter148converts the current signal into a control voltage that regulates the output oscillation produced by the VCO150. Divider module154, based on a serial transmit clock setting158, divides the output oscillation of the VCO150, which corresponds to a serial transmit clock92, to produce the feedback oscillation. Note that the serial transmit clock setting158may be part of the programmed serialization setting64provided to the programmable transmit PMA module38by the control module35.

Divider module152receives the serial transmit clock92and, based on a parallel transmit and programmable logic clock setting160, produces the parallel transmit clock88and a transmit programmable logic clock90. The parallel transmit and programmable logic clock setting160may be part of the programmed serialization setting64.

The parallel-to-serial module140receives the transmit parallel data48and produces therefrom a serial data stream156. To facilitate the parallel-to-serial conversion, the parallel-to-serial module140, which may include an elastic stored buffer, receives a parallel-to-serial setting to indicate the width of the transmit parallel data48and the rate of the transmit parallel data, which corresponds to the parallel transmit clock88. Based on the parallel-to-serial setting, the serial transmit clock92and the parallel transmit clock88, the parallel-to-serial module140produces the serial data stream156from the transmit parallel data48.

The line driver142increases the power of the serial data stream156to produce the transmit serial data50. The line driver142, may be programmed to adjust its pre-emphasis settings, slew rate settings, and drive setting via a pre-emphasis control signal161, a pre-emphasis setting signal162, a slew rate setting signal164, an idle state setting165and a drive current setting166. The pre-emphasis control signal161, pre-emphasis setting signal162, the slew rate setting signal164, the idle state setting165and the drive current setting166may be part of the programmed serialization setting64. As one of average skill in the art will appreciate, while the diagram ofFIG. 4Bis shown as a single-ended system, the entire system may be differential signaling and/or a combination of differential and single-ended signaling.

Further details on the line driver142are described in co-pending patent application entitled DAC BASED DRIVER WITH SELECTABLE PRE-EMPHASIS SIGNAL LEVELS, by Eric D. Groen et al., and having a filing date the same as the present patent application and in co-pending patent application entitled TX LINE DRIVER WITH COMMON MODE IDLE STATE AND SELECTABLE SLEW RATES, by Eric D. Groen et al. and having a filing date the same as the present patent application. These co-pending applications are incorporated by reference, herein.

FIG. 5is a functional block diagram of a prior art voltage controlled oscillator comprising a ring oscillator and a single calibration biasing circuit. More specifically, a prior art voltage controlled oscillator (VCO184includes a gm circuit186and is coupled to receive a control voltage VCTRL, produced by a loop filter. Gm circuit186produces a bias current for a ring oscillator188. Because ring oscillator188is required to provide wide frequency ranges for the local oscillation produced therefrom, gm circuit186must be able to significantly adjust or modify the adjustment bias produced to ring oscillator188based upon changes in the control voltage that is received. As such, small incremental steps in the local oscillation are difficult to achieve if the system is designed to provide a wide frequency response.

Generally, a VCO, such as VCO184, adjusts a frequency of the local oscillation in response to small changes in the received VCTRLsignal. VCO184must be designed, however, to respond to large fluctuations in the value of VCTRLaccording to whether the PLL is operating in a calibration mode or is in steady state and is operating in an operational mode. On one hand, if VCO184is designed to have a wide frequency response range in response to VCTRL, the sensitivity is very high thereby resulting in large swings in the local oscillation for small changes in VCTRL. On the other hand, it is desirable, while operating in a steady state condition, to be able to adjust the local oscillation in small or fine amounts responsive to changes in VCTRL. Accordingly, a need exists for a voltage controlled oscillator that may readily be calibrated to a steady state condition but then may be adjusted in small amounts responsive to changes in VCTRLin a manner that reduces error introduced into the VCO due to noise.

FIG. 6is a functional block diagram of a calibrated VCO formed according to one embodiment of the present invention. A calibrated VCO190comprises a low frequency calibration block192and a high frequency VCO gm circuit194that both couple to receive a control voltage “VCTRL”. Low frequency calibration block192produces a low frequency bias signal to a ring oscillator196that produces an oscillation responsive to the low frequency bias signal. High frequency VCO gm circuit194produces a high frequency bias signal to ring oscillator196to adjust the local oscillation. In operation, the high frequency bias signal, which is much smaller in magnitude than the low frequency bias signal, in the described embodiments of the invention, is superimposed or added to the low frequency bias signal to create a net bias signal. Generally, the low frequency bias signal is for compensating for process and temperature variations while the high frequency bias signal is superimposed to set the local oscillation.

Low frequency calibration block192further comprises a low pass filter198that is for filtering noise and interference above a specified frequency. In one described embodiment of the invention, noise and interference having frequency components above one kHz are filtered.

FIG. 7is a frequency response curve for the calibrated VCO ofFIG. 6. As may be seen from the frequency response curve, the curve comprises two primary portions. A first portion is produced by the low frequency calibration and ranges in frequency from DC to a frequency f1. A second portion ranges from frequency f1to a frequency f2and is produced by the high frequency gm calibration stage (and partially by the low frequency bias between f1and f1′. As may be seen in the described embodiment, a magnitude of the low frequency calibration portion is several times higher than a magnitude for the high frequency portion ranging from frequency f1, to frequency f2above a frequency corner of a low pass filter.

Referring back toFIG. 6, and also referring toFIG. 7, therefore, it may be seen that the preferred embodiment of the calibrated VCO operates to reduce interference and noise and therefore error in the local oscillation in two ways. First, a low pass filter within low frequency calibration block192serves to filter out noise components above a specified frequency corner. Additionally, by designing the system such that low frequency calibration block192produces a magnitude signal that is several times greater in magnitude than high frequency VCO gm circuit194, any unfiltered error produced by the high frequency VCO gm circuit194is small in comparison to the total magnitude of a bias signal produced to ring oscillator196.

In operation, low frequency calibration block192produces a low frequency signal with relatively high bias that is intended to bias the ring oscillator at a center frequency of oscillation. The high frequency bias signal that is produced by high frequency VCO gm circuit194, in contrast, provides an adjustment to the center bias of low frequency calibration block192and is a low bias signal. Thus, for small changes in VCTRL, high frequency VCO gm circuit194operates to add or subtract current from the low frequency bias signal produced by low frequency calibration block192to produce corresponding increases or decreases in the local oscillation. Such adjustments, by the nature of the preferred embodiment of the design, are smaller in magnitude than prior art calibration schemes as discussed herein.

FIG. 8is a schematic diagram of a circuit for calibrating a VCO according to one embodiment of the present invention. The circuit ofFIG. 8illustrates with more detail one embodiment of the functional block diagram for the calibrated VCO ofFIG. 6. As may be seen, a low frequency calibration block202is coupled to provide a low frequency bias signal to ring oscillator206. Low frequency calibration block202further is coupled to high frequency VCO gm stage204.

Low frequency calibration block202includes low pass filter208that is formed between the gates of a current mirror210. The frequency response curve ofFIG. 7illustrates operation of the present invention in relation to a frequency corner defined by low pass filter208. Current mirror210includes a reference MOSFET212that is coupled to generate a reference current for a plurality of mirror MOSFETs214. The sources of reference MOSFET212and mirror MOSFETs214are all coupled to a common ground. Low pass filter208, which is coupled between the gates of reference MOSFET212and mirror MOSFETs214is shown as a low pass resistor-capacitor (RC) filter, although other known low pass filters may be used in its place.

A drain of reference MOSFET212is further coupled to low frequency transconductance gm stage216, which sets a bias current for reference MOSFET212responsive to a magnitude of VCTRL. The current that is conducted through the channel of reference MOSFET212is, as is known by those of average skill in the art, reflected in each of the mirror MOSFETs214. By “reflected”, it is understood that the current in mirror MOSFETs214maintain a proportional relationship to the current conducted through reference MOSFET212. Thus, for similar devices, the proportion is 1:1. If, however, the mirror MOSFETs214were formed to have different operating characteristics, the proportion may change.

For example, in the described embodiment of the invention, mirror MOSFETs214each conduct five times more current than reference MOSFET212and therefore each maintain a 5:1 proportional ratio. In general, current mirror210of low frequency calibration block202is designed to create a bias signal for each branch (delay element) of ring oscillator206, as is known to one of average skill in the art, to result in an oscillation that is in the middle of its frequency range. For example, if low frequency transconductance gm stage216produces 1 milliamp of current through reference MOSFET212, mirror MOSFETs214in each stage of the current mirror will each conduct 5 milliamps of bias current for each delay element of the ring oscillator in one embodiment of the invention. This results in ring oscillator206producing a 5 GHz local oscillation.

High frequency VCO gm stage204includes a differential amplifier pair that drive a plurality of current mirrors that, when properly biased, either sink or source current from or to, respectively, the drains of mirror MOSFETs214of current mirror210. To illustrate, a reference MOSFET217conducts a current that is proportionately reflected in mirror MOSFETs218. Similarly reference MOSFET220conducts a current that is reflected in mirror MOSFET222and therefore is conducted through reference MOSFET224.

The reference current in reference MOSFET224is then reflected in mirror MOSFETs226. Because reference MOSFETs217and220define the current levels in mirror MOSFETs218and226, respectively, the current that is sink or sourced from the drains of mirror MOSFETs214is a function of the relative magnitude of the current levels of the mirror MOSFETs218and226. A properly scaled set of current mirrors, therefore, can be made to operate such that current is either sinked or sourced from the drains of mirror MOSFETs214according to a value of VCTRL.

Thus, the differential pair that drives these current mirrors, namely, MOSFETs228and230, are coupled to receive VCTRLat their gates. Additionally, the bias circuitry for the high frequency VCO gm stage is shown generally at232. The bias circuitry232is formed so as to bias differential MOSFETs228and230to set the current levels of reference MOSFETs217and220such that current mirrors may be sinked or sourced from the drains of mirror MOSFETs214responsive to changes in VCTRL.

In general it may be seen that bias circuitry232comprises a current source233coupled in series with a reference MOSFET234and a pair of mirror MOSFETs236that bias differential MOSFETs228and230. Additionally, a 1 kilo-ohm resistor235, in the described embodiment, is coupled between the sources of differential MOSFETs228and230. One of average skill in the art can readily determine according to system requirements, the corresponding current levels for the current source of bias circuitry232, as well as the device characteristics of MOSFETs234,236,228,230, etc., to provide the described operation.

Based upon the bias provided by bias circuitry232, VCTRLmust reach a specified magnitude to bias either differential MOSFET228or230into an operational state. Examining differential MOSFET228, when it is biased into an “off” state, the drain of reference MOSFET217floats to VDDand reference MOSFET217is also “off”. As VCTRLchanges in magnitude to bias MOSFET228into an “on” state, the drain voltage of reference MOSFET217drops, thereby dropping the gate voltage and increasing the source-to-gate voltage of reference MOSFET217.

As reference MOSFET217turns on harder, it conducts more current thereby causing mirror MOSFETs218to conduct more current as well. Because the gates of mirror MOSFETs218are coupled to the gate and drain of reference MOSFET217, the source-to-gate voltage of mirror MOSFETs218will equal that of reference MOSFET217, thereby causing mirror MOSFETs218to conduct a corresponding proportionate current level. As has been described before, factors such as relative channel and dimensions affect the proportional ratios between the mirror MOSFETs218and reference MOSFET217.

Conversely, as differential MOSFET228tends to turn “off”, differential MOSFET230tends to turn “on”. Accordingly, as differential MOSFET230conducts more current, the drain and gate of reference MOSFET220drop in magnitude thereby increasing the source-to-gate voltage of reference MOSFET220. Because the gate of mirror MOSFET222is coupled to the gate and drain of reference MOSFET220, it produces a corresponding source-to-gate voltage and current flow as described before. As mirror MOSFET222turns “on” and conducts current, the gate-to-source voltage of reference MOSFET224is increased thereby increasing the gate-to-source voltages of mirror MOSFETs226to produce a corresponding increase and current flow there through.

In operation, therefore, as differential MOSFET228tends to turn “on”, reference MOSFET217conducts more current, as do mirror MOSFETs218, while at the same time, mirror MOSFETs226conduct less current. Accordingly, the current is forced to flow into the drain of mirror MOSFETs214thereby sourcing current into the drain of mirror MOSFETS214. Because the current level of mirror MOSFETs214is fixed, the bias current for ring oscillator206decreases by a corresponding amount thereby decreasing the frequency of the local oscillation.

Conversely, when differential MOSFET228tends to turn “off” and differential MOSFET230tends to turn “on”, the current through MOSFETs220,222,224and mirror MOSFETs226tend to turn “on”. Thus, as reference MOSFET217conducts less current, while mirror MOSFETs226conduct more current, current is drawn from the drains of mirror MOSFETs214, thereby sinking bias current thereby increasing the total bias current level for ring oscillator206and increasing the frequency of the oscillation.

FIG. 9is a flowchart illustrating a method for calibrating a VCO according to one embodiment of the described invention. More particularly, the method ofFIG. 8may be considered with the embodiment shown inFIG. 6for the calibrated VCO and the frequency response curve ofFIG. 7. Initially, the method includes receiving a control voltage from a control voltage source (step240). For example, the control voltage may be received from a loop filter, such as loop filter116ofFIG. 4A. Responsive to receiving the control voltage, the method includes producing a low frequency calibration signal (step242). In the described embodiment of the invention, the low frequency calibration signal is one that is designed to prompt the ring oscillator to produce an oscillation that is centered in terms of its frequency range.

The invention further includes, based on the control voltage that was received, producing a high frequency VCO transconductance gm signal (step244). The high frequency VCO transconductance gm signal is a bias adjustment signal that is to be superimposed or summed with the low frequency calibration signal. Accordingly, the next step of the invention includes summing the low frequency calibration signal and the high frequency transconductance signal to produce a net bias signal and a corresponding local oscillation (step246). Thus, the final step includes producing a corresponding local oscillation (step248).

In the described embodiment, the low frequency calibration signal is one that prompts the VCO, and more particularly, the ring oscillator of the VCO, to produce an oscillation that is centered within its operational frequency band. Accordingly, the high frequency VCO transconductance gm signal is added to the low frequency calibration signal to either increase or decrease the bias signal, thereby increasing or decreasing the local oscillation. In an alternate embodiment of the invention, however, the low frequency calibration signal is set to a maximum frequency of the local oscillation frequency range and the high frequency VCO transconductance gm signal is used solely to reduce the bias signal and thereby the corresponding local oscillation. While such a design may work, such an approach consumes more power and is therefore less efficient.

The invention disclosed herein is susceptible to various modifications and alternative forms. Specific embodiments therefore have been shown by way of example in the drawings and detailed description. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the invention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the claims.