ERROR CODE CORRECTION COHERENCY CHECKS FOR TERNARY CELL-BASED MEMORY DEVICES

In some implementations, the techniques described herein relate to a method including: receiving a codeword, the codeword having a first portion and a second portion, the first portion including user data and the second portion including synthesized data; detecting, using an ECC engine, at least one error in the codeword at a first position; and signaling an error misdetection when the first position is within the second portion.

TECHNICAL FIELD

At least some embodiments disclosed herein relate to memory systems in general and, more particularly but not limited to, techniques of configuring memory cells to store data.

BACKGROUND

A memory device can include a memory integrated circuit having one or more arrays of memory cells formed on an integrated circuit die of semiconducting material. A memory cell is the smallest unit of memory that can be individually used or operated upon to store data. In general, a memory cell can store one or more bits of data.

Different types of memory cells have been developed for memory integrated circuits, such as random-access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magneto random access memory (MRAM), negative-or (NOR) flash memory, electrically erasable programmable read-only memory (EEPROM), flash memory, etc.

Some integrated circuit memory cells are volatile and require power to maintain data stored in the cells. Examples of volatile memory include Dynamic Random-Access Memory (DRAM) and Static Random-Access Memory (SRAM).

Some integrated circuit memory cells are non-volatile and can retain stored data even when not powered. Examples of non-volatile memory include flash memory, Read-Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM) and Electronically Erasable Programmable Read-Only Memory (EEPROM) memory, etc. Flash memory includes negative-and (NAND) type flash memory or a negative-or (NOR) type flash memory. A NAND memory cell is based on a NAND logic gate; and a NOR memory cell is based on a NOR logic gate.

Cross-point memory (e.g., 3D XPoint memory) uses an array of non-volatile memory cells. The memory cells in cross-point memory are transistor-less. Each of such memory cells can have a selector device and optionally a phase-change memory device that are stacked together as a column in an integrated circuit. Memory cells of such columns are connected in the integrated circuit via two layers of wires running in directions that are perpendicular to each other. One of the two layers is above the memory cells; and the other layer is below the memory cells. Thus, each memory cell can be individually selected at a cross point of two wires running in different directions in two layers. Cross point memory devices are fast and non-volatile and can be used as a unified memory pool for processing and storage.

A non-volatile integrated circuit memory cell can be programmed to store data by applying a voltage or a pattern of voltage to the memory cell during a program/write operation. The program/write operation sets the memory cell in a state that corresponds to the data being programmed/stored into the memory cell. The data stored in the memory cell can be retrieved in a read operation by examining the state of the memory cell. The read operation determines the state of the memory cell by applying a voltage and determining whether the memory cell becomes conductive at a voltage corresponding to a pre-defined state.

DETAILED DESCRIPTION

At least some aspects of the disclosure are directed to a memory sub-system configured to correct errors when reading one or more self-selecting memory cells.

The memory sub-system can be used as a storage device and/or a memory module. Examples of storage devices, memory modules, and memory devices are described below in conjunction with the following figures. A host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

An integrated circuit memory cell, such as a memory cell in a flash memory or a memory cell in a cross-point memory, can be programmed to store data by the way of its state at a voltage applied across the memory cell. For example, if a memory cell is configured or programmed in such a state that allows a substantial current to pass the memory cell at a voltage in a predefined voltage region, the memory cell is considered to have been configured or programmed to store a first bit value (e.g., one or zero); and otherwise, the memory cell is storing a second bit value (e.g., zero or one). Optionally, a memory cell can be configured or programmed to store more than one bit of data by being configured or programmed to have a threshold voltage in one of more than two separate voltage regions.

The threshold voltage of a memory cell is such that when the magnitude of the voltage applied across the memory cell is increased to above the threshold voltage, the memory cell changes rapidly or abruptly, snaps, or jumps from a non-conductive state to a conductive state. The non-conductive state allows a small leak current to go through the memory cell; and in contrast, the conductive state allows more than a threshold amount of current to go through. Thus, a memory device can use a sensor to detect the change or determine the conductive/non-conductive state of the memory device at one or more applied voltages, to evaluate or classify the level of the threshold voltage of the memory cell and thus its stored data.

The threshold voltage of a memory cell being configured or programmed to be in different voltage regions can be used to represent different data values stored in the memory cell. For example, the threshold voltage of the memory cell can be programmed to be in any of three predefined voltage regions; and each of the regions can be used to represent the bit values of a different two-bit data item. Thus, when given a two-bit data item, one of the three voltage regions can be selected based on a mapping between two-bit data items and voltage regions; and the threshold voltage of the memory cell can be adjusted, programmed, or configured to be in the selected voltage region to represent or store the given two-bit data item. To retrieve, determine, or read the data item from the memory cell, one or more read voltages can be applied across the memory cell to determine which of the three voltage regions contain the threshold voltage of the memory cell. The identification of the voltage region that contains the threshold voltage of the memory cell provides the two-bit data item that has been stored, programmed, or written into the memory cell.

For example, a memory cell can be configured or programmed to store a one-bit data item in a Single Level Cell (SLC) mode, or a two-bit data item in a Multi-Level Cell (MLC) mode, or a three-bit data item in a Triple Level Cell (TLC) mode, or a four-bit data item in Quad-Level Cell (QLC) mode, or a five-bit data item in a Penta-Level Cell (PLC) mode.

The threshold voltage of a memory cell can change or drift over a period of time, usage, and/or read operations, and in response to certain environmental factors, such as temperate changes. The rate of change or drift can increase as the memory cell ages. The change or drift can result in errors in determining, retrieving, or reading the data item back from the memory cell.

Random errors in reading memory cells can be detected and corrected using redundant information. Data to be stored into memory cells can be encoded to include redundant information to facilitate error detection and recovery. When data encoded with redundant information is stored in a memory sub-system, the memory sub-system can detect errors in data represented by the voltage regions of the threshold voltages of the memory cells and/or recover the original data that is used to generate the data used to program the threshold voltages of the memory cells. The recovery operation can be successful (or have a high probability of success) when the data represented by the threshold voltages of the memory cells and thus retrieved directly from the memory cells in the memory sub-system contains fewer errors, or the bit error rate in the retrieved data is low and/or when the amount of redundant information is high. For example, error detection and data recovery can be performed using techniques such as Error Correction Code (ECC), Low-Density Parity-Check (LDPC) code, etc., as will be discussed in more detail herein.

It is a challenge to efficiently program a memory cell into an intermediate state representing by its threshold voltage being in a voltage region assigned to represent a value, separate from a high voltage region and a low voltage region. It is relatively easy to program the threshold voltage of a memory cell into the high voltage region and the low voltage region. It is difficult to precisely program the threshold voltage of the memory cell into an intermediate region between, but having no overlapping with, the high voltage region and the low voltage region.

FIG.1shows a memory device130configured with a programming manager113according to one embodiment.

InFIG.1, the memory device130includes an array133of memory cells, such as a memory cell101. An array133can be referred to as a tile; and a memory device (e.g.,130) can have one or more tiles. Different tiles can be operated in parallel in a memory device (e.g.,130).

For example, the memory device130illustrated inFIG.1can have a cross-point memory having at least the array133of memory cells (e.g.,101).

In some implementations, the cross point memory uses a memory cell101that has an element (e.g., a sole element) acting both as a selector device and a memory device. For example, the memory cell101can use a single piece of alloy with variable threshold capability. The read/write operations of such a memory cell101can be based on thresholding the memory cell101while inhibiting other cells in sub-threshold bias, in a way similar to the read/write operations for a memory cell having a first element acting as a selector device and a second element acting as a phase-change memory device that are stacked together as a column. A selector device usable to store information can be referred to as a selector/memory device.

The memory device130ofFIG.1includes a controller131that operates bitline drivers137and wordline drivers135to access the individual memory cells (e.g.,101) in the array133.

For example, each memory cell (e.g.,101) in the array133can be accessed via voltages driven by a pair of a bitline driver147and a wordline driver145, as illustrated inFIG.2.

The controller131includes a programming manager113configured to implement a counter-controlled programming pulse. The programming manager113can be implemented, for example, via logic circuits and/or microcodes/instructions. For example, to program the threshold voltage of the memory cell101into a second voltage region adjacent to a first voltage region, the programming manager113can instruct the bitline drivers137and the wordline drivers135to initially apply a voltage pulse configured to program the threshold voltage of the memory cell101into the first voltage region. After the completion of the initial voltage pulse, the programming manager113further instructs the bitline drivers137and the wordline drivers135to apply a subsequent voltage pulse to move the threshold voltage of the memory cell101from the first voltage region to the adjacent second voltage region that is separate from the first voltage region. The magnitude of the subsequent voltage pulse is dynamically controlled for a set of memory cells that are to be read together for a data item (e.g., a codeword for error detection and data recovery using an Error Correction Code (ECC)). The programming manager113can instruct the bitline drivers137and the wordline drivers135to increase the applied magnitude in increments until each and every of the memory cells to be programmed to the second voltage regions are conductive under the applied magnitude. For example, a counter can be used to count the number of memory cells that are in a conductive state under the current increment of the magnitude. When the magnitude is increased to a level of increment that causes the value in the counter to be equal to the number of memory cells in the codeword to be programmed to the adjacent second voltage region, no further increment is applied to the magnitude of the subsequent voltage pulse applied to the memory cells.

FIG.2shows a memory cell101with a bitline driver147and a wordline driver145configured to apply voltage pulses according to one embodiment. For example, the memory cell101can be a typical memory cell101in the memory cell array133ofFIG.1.

The bitline driver147and the wordline driver145ofFIG.2are controlled by the programming manager113of the controller131to selectively apply one or more voltages pulses to the memory cell101.

The bitline driver147and the wordline driver145can apply voltages of different polarities on the memory cell101.

For example, in applying one polarity of voltage (e.g., positive polarity), the bitline driver147drives a positive voltage relative to the ground on a bitline141connected to a row of memory cells in the array133; and the wordline driver145drives a negative voltage relative to the ground on a wordline143connected to a column of memory cells in the array133.

In applying the opposite polarity of voltage (e.g., negative polarity), the bitline driver147drives a negative voltage on the bitline141; and the wordline driver145drives a positive voltage on the wordline143.

The memory cell101is in both the row connected to the bitline141and the column connected to the wordline143. Thus, the memory cell101is subjected to the voltage difference between the voltage driven by the bitline driver147on the bitline141and the voltage driven by the wordline driver145on the wordline143.

In general, when the voltage driven by the bitline driver147is higher than the voltage driven by the wordline driver145, the memory cell101is subjected to a voltage in one polarity (e.g., positive polarity); and when the voltage driven by the bitline driver147is lower than the voltage driven by the wordline driver145, the memory cell101is subjected to a voltage in the opposite polarity (e.g., negative polarity).

In some implementations, the memory cell101is a self-selecting memory cell implemented using a selector/memory device. The selector/memory device has a chalcogenide (e.g., chalcogenide material and/or chalcogenide alloy). For example, the chalcogenide material can include a chalcogenide glass such as, for example, an alloy of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). A chalcogenide material can primarily have selenium (Se), arsenic (As), and germanium (Ge) and be referred to as SAG-alloy. SAG-alloy can include silicon (Si) and be referred to as SiSAG-alloy. In some embodiments, the chalcogenide glass can include additional elements such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular forms. The selector/memory device has a top side and a bottom side. A top electrode is formed on the top side of the selector/memory device for connecting to a bitline141; and a bottom electrode is formed on the bottom side of the selector/memory device for connecting to a wordline143. For example, the top and bottom electrodes can be formed of a carbon material. For example, a chalcogenide material of the memory cell101can take the form of a crystalline atomic configuration or an amorphous atomic configuration. The threshold voltage of the memory cell101can be dependent on the ratio of the material in the crystalline configuration and the material of the amorphous configuration in the memory cell101. The ratio can change under various conditions (e.g., having currents of different magnitudes and directions going through the memory cell101).

A self-selecting memory cell101, having a selector/memory device, can be programmed to have a threshold voltage window. The threshold voltage window can be created by applying programming pulses with opposite polarity to the selector/memory device. For example, the memory cell101can be biased to have a positive voltage difference between two sides of the selector/memory device and alternatively, or to have a negative voltage difference between the same two sides of the selector/memory device. When the positive voltage difference is considered in positive polarity, the negative voltage difference is considered in negative polarity that is opposite to the positive polarity. Reading can be performed with a given/fixed polarity. When programmed, the memory cell has a low threshold (e.g., lower than the cell that has been reset, or a cell that has been programmed to have a high threshold), such that during a read operation, the read voltage can cause a programmed cell to snap and thus become conductive while a reset cell remains non-conductive.

For example, to program the voltage threshold of the memory cell101, the bitline driver147and the wordline driver145can drive a pulse of voltage onto the memory cell101in one polarity (e.g., positive polarity) to snap the memory cell101such that the memory cell101is in a conductive state. While the memory cell101is conductive, the bitline driver147and the wordline driver145continue driving the programming pulse to change the threshold voltage of the memory cell101towards a voltage region that represents the data or bit value(s) to be stored in the memory cell101.

The controller131can be configured in an integrated circuit having a plurality of decks of memory cells. Each deck can be sandwiched between a layer of bitlines, a layer of wordlines; and the memory cells in the deck can be arranged in an array133. A deck can have one or more arrays or tiles. Adjacent decks of memory cells may share a layer of bitlines (e.g.,141) or a layer of wordlines (e.g.,143). Bitlines are arranged to run in parallel in their layer in one direction; and the wordlines are arranged to run in parallel in their layer in another direction orthogonal to the direction of the bitlines. Each of the bitlines is connected to a row of memory cells in the array; and each of the wordlines is connected to a column of memory cells in the array. Bitline drivers137are connected to bitlines in the decks; and wordline drivers135are connected to wordlines in the decks. Thus, a typical memory cell101is connected to a bitline driver147and a wordline driver145.

The threshold voltage of a typically memory cell101is configured to be sufficiently high such that when only one of its bitline driver147and wordline driver145drives a voltage in either polarity while the other voltage driver holds the respective line to the ground, the magnitude of the voltage applied across the memory cell101is insufficient to cause the memory cell101to become conductive. Thus, addressing the memory cell101can be performed via both of its bitline driver147and wordline driver145driving a voltage in opposite polarity relative to the ground for operating/selecting the memory cell101. Other memory cells connected to the same wordline driver145can be de-selected by their respective bitline drivers holding the respective bitlines to the ground; and other memory cells connected to the same bitline driver can be de-selected by their respective wordline drives holding the respective wordlines to the ground.

A group of memory cells (e.g.,101) connected to a common wordline driver145can be selected for parallel operation by their respective bitline drivers (e.g.,147) driving up the magnitude of voltages in one polarity while the wordline driver145is also driving up the magnitude of a voltage in the opposite polarity. Similarly, a group of memory cells connected to a common bitline driver147can be selected for parallel operation by their respective wordline drivers (e.g.,145) driving voltages in one polarity while the bitline driver147is also driving a voltage in the opposite polarity.

At least some examples are disclosed herein in reference to a cross-point memory having self-selecting memory cells. Other types of memory cells and/or memory having similar threshold voltage characteristics can also be used. For example, memory cells each having a selector device and a phase-change memory device and/or flash memory cells can also be used in at least some embodiments.

FIG.3illustrates distributions of threshold voltages of memory cells each configured to represent one of three predetermined values according to one embodiment. For example, the programming manager113ofFIGS.1and2can be used to program the threshold voltage of a memory cell101such that the probability distribution of its threshold voltage is as illustrated inFIG.3.

The probability distribution of the threshold voltage of a memory cell can be illustrated via a normal quantile (NQ) plot, as inFIG.3. When a probability distribution (e.g.,151) of threshold voltage programmed in a region is a normal distribution (also known as Gaussian distribution), its normal quantile (NQ) plot is seen as aligned on a straight line (e.g., distribution151).

A self-selecting memory cell (e.g.,101) can have a threshold voltage in negative polarity and a threshold voltage in positive polarity. When a voltage applied on the memory cell101in either polarity is increased in magnitude up to its threshold voltage in the corresponding polarity, the memory cell (e.g.,101) snaps from a non-conductive state to a conductive state.

The threshold voltage of a memory cell101in negative polarity and the threshold voltage of the memory cell101in positive polarity can have different magnitudes. Memory cells programmed to have large magnitudes in threshold voltages in positive polarity can have small magnitudes in threshold voltages in negative polarity; and memory cells programmed to have small magnitudes in threshold voltages in positive polarity can have large magnitudes in threshold voltages in negative polarity.

For example, a memory cell101can be programmed to have a small magnitude in threshold voltage according to distribution151in the positive polarity to represent a value (e.g., zero); and as a result, its threshold voltage has a large magnitude according to distribution152in the negative polarity to represent the same value (e.g., zero). The threshold voltages of the memory cell101in the positive and negative polarities can be programmed to the distributions151and152by applying a voltage pulse in the positive polarity (e.g., as illustrated inFIG.4) to place the memory cell101in a conductive state and to cause a predetermined level of current (e.g., 120 μA) to go through the memory cell101.

Alternatively, the memory cell101can be programmed to have a smaller magnitude in threshold voltage according to distribution156in the negative polarity to represent another value (e.g., two); and as a result, its threshold voltage has a large magnitude according to distribution155in the positive polarity to represent the same value (e.g., two). The threshold voltages of the memory cell101in the positive and negative polarities can be programmed to the distributions155and156by applying a voltage pulse in the negative polarity (e.g., as illustrated inFIG.5) to place the memory cell101in a conductive state and to cause a predetermined level of current (e.g., 120 μA) to go through the memory cell101.

The state of having threshold voltages in the distributions151and152and the state of having threshold voltages in the distributions155and156are relatively easy to obtain. The programming of the memory cell101to such two states can be implemented using voltage pulses illustrated inFIGS.4and5. The voltage regions of the distributions151,152,155and156are controlled primarily by the polarity of the programming voltage pulses and the level of current passing through the memory cell101near the end of the programming voltage pulses.

To facilitate the storing of more than one bit of data per memory cell, the memory cell101can be programmed into an intermediate state between the two states.

For example, the memory cell101can be programmed to have a medium magnitude in threshold voltage according to distribution153in the positive polarity to represent a further value (e.g., one); and as a result, its threshold voltage has a magnitude according to distribution154in the negative polarity to represent the same value (e.g., one). The threshold voltages of the memory cell101in the positive and negative polarities can be programmed to the distributions153and154by applying a voltage pulse to move the threshold voltages of the memory from the distributions151and152, or from the distributions155and156.

In some implementations, more than one intermediate state can be programmed in a similar way such that the threshold voltage in the positive polarity is in the voltage region of one of four distributions and the threshold voltage in the negative polarity is in the voltage region of one of four distributions. Such four states can be used to represent a two-bit data item stored in the memory cell101.

InFIG.3, the voltage distributions151,153and155in the positive polarity are separated by read voltage V1161and read voltage V2162. Thus, whether the threshold voltage of the memory cell101in the positive polarity is in the distribution151can be determined by testing whether the memory cell101is conductive at the read voltage V1161in the positive polarity; and whether the threshold voltage of the memory cell101in the positive polarity is in the distribution155can be determined by testing whether the memory cell101is non-conductive at the read voltage V2162in the positive polarity. If the threshold voltage of the memory cell101in the positive polarity is in neither the distribution151nor the distribution155, it is in the distribution153representative of the corresponding value (e.g., one).

Similarly, inFIG.3, the distributions152,154and156in the negative polarity are separated by the read voltage V3163and read voltage V4164. Thus, whether the threshold voltage of the memory cell101in the negative polarity is in the distribution156can be determined by testing whether the memory cell101is conductive at the read voltage V3163in the negative polarity; and whether the threshold voltage of the memory cell101in the negative polarity is in the distribution152can be determined by testing whether the memory cell101is non-conductive at the read voltage V4164in the negative polarity. If the threshold voltage of the memory cell101in the negative polarity is in neither the distribution152nor the distribution156, it is in the distribution154representative of the corresponding value (e.g., one).

Thus, the determination of the state and thus the value represented by the state (e.g., region of threshold voltage) can be performed by reading the memory cell101in the positive polarity using the read voltages V1and V2, or reading the memory cell101in the negative polarity using the read voltages V3and V4, or a combination of reading the memory cell101in the negative polarity using read voltage V3and in the positive polarity using read voltage V1.

In the following embodiments, a codeword can be read from a memory device. This single codeword may be physically stored in the types of ternary cells described above. In general, pairs of ternary cells can be read together to generate a three-digit binary value. In the various implementations, it may be beneficial to segment a codeword based on bit positions of these individual three-digit binary values.

FIG.7Aillustrates the segmentation of a message into two codewords.

In the illustrated embodiment, user data702A comprises a set of k bits. The specific number of k is not limiting and the specifically illustrated size of the user data702A is not limiting. In general, user data702A may comprise any type of binary data.

In a first step, the user data702A is chunked into three-bit chunks to form chunked user data704A. In some implementations, the value of three is determined by the underlying memory cell technology. For example, as used herein, a given memory device may utilize three-state ternary cells and the choice of three for chunking may be based on this underlying physical characteristic of the memory cells. Certainly, other types of memory cells may change the chunking value, however a value of three is used herein and ternary cells are also used herein. Formally, the user data702A may be represented as:

Next, in state706A, the chunked user data704A is split into two separate codewords:

In state708A, parity bits can be computed for each codeword independently. Thus, CWxcan have its own associated parity bits (x5x6) while CWyzcan have its own parity bits (y5z5y6z6). Finally, the codewords and parity bits can be encoded into ternary values710A. As illustrated, each ternary value is formed from a bit of CWxand two bits from CWyz. Notably, as illustrated, there is a correspondence between the values of CWxand CWyzdue to the construction of the codewords. In some implementations, an encoding table can be used to map three-bit strings to ternary cell combinations. Examples of such encoding tables are provided in commonly-owned application bearing attorney docket number 120426-063400, which is incorporated by reference in its entirety.

During reading and decoding from ternary cells, physical errors in a ternary cell can impact the decoding process. One example of this problem is depicted inFIG.7B. As illustrated, pairs of ternary cells702B corresponding to a binary codeword are retrieved. Further, two ternary memory cells (t2,2and t4,1) experienced read errors caused by the underlying physical memory structure (described more fully in commonly-owned application bearing attorney docket number 120426-063400, which is incorporated by reference in its entirety). During decoding, these physical errors may propagate to errors in the binary decoded values704B. Specifically, the error in t2,2causes one error in CWyz(at z2) while the error in t4,1causes three errors, one in CWx(x4) and two in CWyz(y4and z4).

In some memory devices, a single ECC engine may be used. As illustrated, an ECC2 decoder710B is used, such as a BCH-2 engine, however the specific algorithm used is not limiting. As illustrated, both CWx706B and CWyz708B are input into the ECC2 decoder710B. In this specific example, CWx706B is properly decoded since it includes one error and does not overflow the ECC2 decoder710B. However, the ECC2 decoder710B overflows714B when detecting and/or correcting errors in CWyz708B since it includes three errors. Specifically, the resulting syndrome generated by ECC2 decoder710B may result in an arbitrary correction resulting in incorrect data. If the decoded CWx712B were combined with the output of decoding CWyz708B, the resulting data would be incorrect.

However, since the construction of ternary cells from two codewords is used, aspects of CWxcan be used to adjust CWyzprior to decoding. For example, the ECC engine can identify any CWyerror positions that have corresponding CWyzerrors and invert those bits. The result of this is shown in partially-inverted codeword716B. Here, since x4included an error and the corresponding y4and z4bits included errors, the ECC engine can invert y4and z4bits and attempt to decode the partially-inverted codeword716B. Since the partially-inverted codeword716B only includes one error, the ECC2 decoder710B can decode the codeword (result718B). The result718B can then be combined with decoded CWx712B to generate a correctly decoded value. Thus, the foregoing example can leverage information from CWxto correct errors in CWyz. Certainly, the number of errors in both CWxand CWyzmay vary andFIGS.9and10provide a complete process to account for various scenarios of errors.

FIGS.8A and8Billustrate a scenario in which an ECC engine improperly recommends an error correction.

In the illustrated embodiment, a codeword may include a real portion802and a parity portion804. The real portion802generally refers to user data stored in a memory device, while the associated parity portion804comprises redundant parity data generated during write by an ECC engine. The specific sizes of real portion802and parity portion804are not limiting.

A given ECC code (e.g., BCH Code) may have a fixed size. For example, the illustrated BCH code includes a user data portion806and a parity portion808. In some implementations, the size of the ECC code may be selected to be the smallest size capable of storing the real portion802of the codeword described above. For example, the size of the ECC code may be defined as 2m−1, where m is such that the number of user data bits plus the number of parity bits (t*m) is less than or equal to 2m−1, and t represents the error correction capability. As illustrated, the total size of the ECC code is larger than the size of the real portion802and parity portion804. Indeed, while the parity portion804is equal in size to the parity portion808, the user data portion806is larger than real portion802.

In some implementations, it may be desired to reuse an ECC engine, regardless of the user data size (e.g., to reduce the hardware complexity of a memory controller). However, real portion802and parity portion804will generally not be processible by an ECC engine that is not designed to operate on the size of real portion802. To overcome this issue, synthesized data810may be added to real portion802prior to input to an ECC engine. In some implementations, the synthesized data may comprise all zero or all one values. In some implementations, the size of synthesized data810is designed such that the total size of synthesized data810and real portion802is equal to the expected user data size of real portion806. In this manner, the combination of real portion802, synthesized data810and parity portion804meets the requirements of an ECC engine used by a memory device. The combination of real portion802, synthesized data810and parity portion804is referred to a “shortened” codeword.

However, the introduction of synthesized data810may introduce false-positive errors detected by the ECC engine. Specifically, since the parity portion804is generated based on real portion802during encoding and then real portion802and synthesized data810are used for decoding, the parity portion804is no longer synchronized with the codeword.FIG.8Billustrates this decoding problem. As illustrated, the shortened codeword is input into an ECC decoder818. The ECC decoder may comprise, for example, an ECC2 decoder that can detect up to two errors (e.g., a BCH-2 decoder). In some implementations, the shortened codeword can be generated before input into ECC decoder818. In other implementations, the ECC decoder818itself may add the synthesized data810to form the shortened codeword.

As illustrated by the darkened locations, real portion802includes three errors. Synthesized data810necessarily does not include true errors since it is synthesized data. However, when decoding the shortened codeword using ECC decoder818, ECC decoder818detects two errors: one error in real portion802and an error in synthesized data810(also illustrated as a darkened location). Thus, ECC decoder818proposes to correct two errors, however one error is improper. Notably, when the ECC decoder818overflows, the proposed corrections may all be incorrect. Further, in some implementations, the use of synthesized data can overwhelm the ECC and thus the ECC may incorrectly detect errors in real portion802as well. As will be discussed, an error in synthesized data810can be ensured to be a sign of error overflow since no errors can exist in synthesized data810. In general, when the number of errors overpowers the ECC, the resulting syndrome may propose to correct two errors in potentially arbitrary positions which may or may not be coherent with the actual error positions.

If the number of actual errors overpowers the ECC correction power, the probability of having two proposed corrections within the real positions can be defined probabilistically and expressed as follows:

Here, real refers to the length of the real portion802and total refers to the size of the shortened codeword input into the ECC engine (e.g., real plus the size of synthesized data810). For example, if a codeword size is 511 bits but the size of the real portion802is only 274 bits, the probability of the ECC correcting two true errors is as follows:

Thus, in such a scenario, the ECC engine will incorrectly try to correct false errors in 72% of the considered codewords (containing more than two errors). The above probability necessarily increases as the real portion802occupies less of the total size of shortened codeword. In all of these scenarios, the example embodiments provide techniques for resolving the coherency of detected errors given a shortened ECC codeword.

FIG.9is a flow diagram illustrating a method for detecting an incorrect error position in an ECC algorithm executing on an extended ECC codeword.

In step902, the method can include receiving a codeword.

As discussed above, the codeword in step902can include a codeword that includes a first portion and at least one other portion. The following description utilizes a first portion and one other portion (the “second” portion); however the disclosure is not limited to a single other portion. In an implementation, the first portion can include actual data. As used herein, actual data refers to data written to a memory device or otherwise of use by a computing system. By contrast, the second portion may include synthesized data. In the implementations, the codeword also includes a parity portion generated using the first portion as input. In some implementations, the synthesized data may comprise all zeros, all ones, or a random pattern of zeros and ones. In some implementations, step902can be implemented within an ECC circuit or algorithm. In other implementations, step902can be implemented by a microcontroller or via software prior to inputting the extended codeword into an ECC circuit or algorithm.

In step904, the method can include using an ECC engine (e.g., circuit or algorithm) to detect the positions of errors within the entire codeword.

In some implementations, the ECC engine can detect multiple bit errors. In some implementations, the ECC engine can implement an existing ECC algorithm such Single error correction/double error detection (SEC-DED) Hsiao codes, Single error correction/double error detection/single byte error detection (SEC-DED-SBD) Reddy codes, Single byte error correction/double byte error detection (SBC-DBD) finite field-based codes, Double error correction/triple error detection (DEC-TED) Bose-Chaudhuri-Hocquenghem (BCH) codes, or similar types of ECC. In general, any ECC engine that can detect error positions can be used.

In some embodiments, the method can store the positions of any errors detected in step904. For example, the method can store the bit positions of errors relative to the codeword in a volatile storage device (e.g., DRAM) for later use (e.g., in step908and step910, discussed herein).

In step906, the method can include determining if any errors are present within the codeword. If not, the method can terminate as no error correction is needed. As illustrated, in one embodiment, the method can proceed to step908if even a single error is detected and of course if multiple errors are detected. As discussed in connection withFIG.8, since the codeword received in step902includes synthesized data that may be all zeroes or all ones, errors may be detected both within a real portion of the keyword (including user data) or within this synthesized region. Since this synthesized region does not include actual data, errors detected within the region are false positives.

In step908, the method can include comparing the detected error positions to the real portion positions of the codeword.

In some embodiments, the method can be configured with a mapping of real positions and synthesized positions of the codeword received in step902. For example, in some embodiments, the method can store a length (from zero) of the real portion. Alternative, in some embodiments, the method can store a bit mapping that identifies (e.g., non-contiguous) real bits of the codeword.

The method can compare the detected error positions to a list (or range) of real bit positions in the codeword. Then, in step910, the method can determine whether the ECC engine properly detected the errors. Specifically, in step910, the method can determine if the detected error positions correspond to bits of real data in the codeword. For example, if the codeword includes n bits and bits zero through m comprise a real portion of the codeword (where m<n), step910can include determining if error bit positions (b1, b2, . . . bn) are located in bit positions between zero and m.

In some scenarios, all of the detected bit errors may be within the real portion. In this case, the method can proceed to step912and correct the errors. In one embodiment, step912can include running a correction engine of the ECC engine to correct the detected errors. The specific operations of an ECC engine are not limiting and are not discussed in detail herein. After correcting errors, the method can then return the codeword to a calling device in step916.

By contrast, if the method determines (in step910) that at least one error position is not in the real portion of the keyword (i.e., is in the synthesized data), the method can proceed to step914where it handles the ECC misdetection and miscorrection before ending. In some implementations, the method can raise a signal indicating that error correction has failed due to overwhelming of the ECC engine with the synthesized portion. Such an approach can be used in conjunction with any of the foregoing embodiments (e.g., as a flag indicating such a correction was performed). Alternatively, the signal can be raised immediately, and the method can halt, signaling remedial measures are needed. For example, a backup of the codeword can be read from a redundant memory device.

Using the above method ofFIG.9, the form of the codeword can be used to re-utilize an ECC engine for a varying length input codeword. Since an ECC engine will improperly detect errors in such an “extended” codeword (as illustrated inFIGS.8A and8B), the method utilizes the structure of the codeword to ensure that only valid errors are detected. Use of this structure allows for standard ECC engines to be used with variable length codewords and allows re-use of existing ECC engines, despite shortened user data.

FIGS.10and11are flow diagrams illustrating a method for increasing the correction power of an ECC engine using correlations between two codewords.

The illustrated method is described in more detail below. At a high-level, the method can include receiving a codeword having a first portion and a second portion and detecting, using an ECC (e.g., ECC2) engine at least one error or failure in the first portion (step1002). Based on the number of errors or failure of the ECC2, the method can then perform error correction on the second portion and invert zero or more bits of the first or second portions and then proceed to perform error corrections on the first and second portions (step1024). More specifically, if the ECC on the first portion fails the method can invert bits of the first portion based on an extended ECC performed on the second portion (steps1004,1006,1008). If no errors exist on the first portion, the method can perform an extended ECC operation on the second portion and mark the codeword as uncorrectable if three errors occur or correct the errors otherwise (steps1010and1012). If one error in the first portion is detected, the method can employ a combination of extended ECC detection on the second portion as well as a coherency check to determine when to invert bits of the second portion (steps1014,1016,1018,1020,1026,1028). Finally, if two errors are detected in the first portion the method can perform an extended ECC operation on the second portion and perform alternative coherency checks to determine when to invert bits of the second portion. Details of these operations are provided herein. While the foregoing method generally describes a maximum of three errors, the method may be generalized to include more errors than three.

In step1002, the method can begin by receiving a codeword and using an ECC engine (e.g., circuit or algorithm) to detect the positions of errors within a first portion of the codeword.

As discussed above, the codeword in step1002can include a codeword that includes a first portion (referred to as codeword X) and at least one other portion (referred to as codeword YZ). The following description utilizes a first portion and one other portion (the “second” portion), however the disclosure is not limited to a single other portion. In an implementation, the first portion can include actual data. As used herein, actual data refers to data written to a memory device or otherwise of use by a computing system. By contrast, the second portion may include synthesized data. In some implementations, the synthesized data may comprise all zeros, all ones, or a random pattern of zeros and ones. In some implementations, step1002can be implemented within an ECC circuit or algorithm. In other implementations, step1002can be implemented by a microcontroller or via software prior to inputting the extended codeword into an ECC circuit or algorithm.

In some implementations, the ECC engine can detect multiple bit errors. In some implementations, the ECC engine can implement an existing ECC algorithm such as Single Error Correction/Double Error Detection (SEC-DED) Hsiao codes, Single Error Correction/Double Error Detection/Single Byte Error Detection (SEC-DED-SBD) Reddy codes, Single Byte Error Correction/Double Byte Error Detection (SBC-DBD) finite field-based codes, Double Error Correction/Triple Error Detection (DEC-TED) Bose-Chaudhuri-Hocquenghem (BCH) codes, or similar types of ECC. In general, any ECC engine that can detect error positions can be used. In some implementations, step1002may include utilizing an ECC2 engine.

As illustrated, the method in step1002can detect 0, 1, or 2 errors in codeword X or can also fail, as illustrated by the branches of step1002. In general, failing refers to an ECC algorithm detecting too many errors that it may not be capable of correcting. In some implementations, failing may also refer to detecting a correction proposed in a synthesized region of a codeword as described previously with respect toFIG.9. Such a scenario is also referred to as overpowering or overwhelming the error correction capabilities of the ECC. An ECC algorithm or engine may include two stages: a detection stage or engine and a correction stage or engine. In the various detection steps, only the detection engine may be utilized. In some implementations, the detection engine may not be capable of identifying the specific number of errors, but simply that error overflow has occurred.

If the ECC2 engine in step1002fails, the method proceeds to step1004. In step1004, an extended ECC2 engine is applied to the second portion of the codeword (codeword YZ). As illustrated, in some implementations, the extended ECC2 engine can detect zero to three errors or may also fail, similar to the ECC2 engine discussed in step1002. As illustrated, if the extended ECC2 engine detects one or two errors in codeword YZ, the method proceeds to step1006(described next). However, if the extended ECC2 engine detect no errors, three errors, or fails, the method marks the entire codeword (e.g., both codeword X and codeword YZ) as uncorrectable in step1008and fails.

In step1006, the method has determined that one or two errors are present in codeword YZ. In response, the method inverts one or more corresponding bits in codeword X. Specifically, in some implementations, the method identifies which bits in codeword YZ are associated with detected errors and inverts the corresponding codeword X bits. As discussed above, a given bit in codeword YZ may correspond (e.g., based on addressing) to a corresponding bit in codeword X. Thus, the extended ECC2 engine may indicate the address of the errors in codeword YZ and this address can be used to identify the corresponding bits in codeword X that should be inverted.

As illustrated, after the bits of codeword X are inverted in step1006, the method proceeds to step1024where the codeword is corrected using an appropriate ECC engine. Specifically, an ECC2 engine is used to correct codeword X (with bit inversions applied in step1006) while the extended ECC2 engine is used to correct codeword YZ. Notably in step1024the actual error correction is performed.

Returning to step1002, in another scenario, the ECC2 engine of step1002may not detect any errors in codeword X. In this scenario, the method proceeds to step1010. In step1010, the method uses an extended ECC2 engine to detect errors in codeword YZ. As in step1004, the method in step1010include detecting zero to three errors (or in some implementations zero to two errors) or failing. However, in step1010, the method can include determining whether the detected number of errors is equal or not to three. If the extended ECC2 engine detects three errors (and in some implementations if the check fails), the method proceeds to step1012. In step1012, the method (as in step1008) marks the entire codeword as uncorrectable and fails. By contrast, if less than three errors are detected (or the extended ECC2 fails), the method proceeds to step1024where the codeword is corrected using an appropriate ECC engine. Specifically, an ECC2 engine is used to correct codeword X while the extended ECC2 engine is used to correct codeword YZ. Notably in step1024the actual error correction is performed.

Returning to step1002, in another scenario, the ECC2 engine of step1002may detect a single error in codeword X. In response to detecting a single error in codeword X, the method may perform an extended ECC operation on the second portion in step1014. If the extended ECC operation in step1014indicates zero or one error, the method may proceed to1026where the codeword is corrected using an appropriate ECC engine. Specifically, an ECC2 engine is used to correct codeword X while the extended ECC2 engine is used to correct codeword YZ. Notably in step1026the actual error correction is performed.

By contrast, if the extended ECC operation in step1014indicates three errors (and in some implementations if the extended ECC operation fails), the method may proceed to step1020where bits of codeword YZ are inverted based on the detected errors in codeword X. Specifically, in some implementations, the method identifies which bits in codeword X are associated with detected errors and inverts the corresponding codeword YZ bits. As discussed above, a given bit in codeword X may correspond (e.g., based on addressing) to a corresponding bit in codeword YZ. Thus, the ECC2 engine may indicate the address of the errors in codeword X and this address can be used to identify the corresponding bits in codeword YZ that should be inverted. After performing this inversion in step1020, the method proceeds to step1022where a second extended ECC operation is performed on the second portion (codeword YZ). Here, if the second extended ECC operation indicates three errors, the method proceeds to step1018and marks the codeword as uncorrectable (similar to step1008or1012, discussed previously). By contrast, if the second extended ECC operation yields any other result (e.g., zero to two errors or a failure), the method proceeds to step1028where the codeword portions are corrected (similar to step1024and step1026).

Finally, in some scenarios, the extended ECC operation in step1014may either fail or indicate two errors. In this scenario, the method proceeds to step1016where a coherency check is performed. As used herein, a coherency check refers to a logical test that yields an OK or not OK value (e.g., pass or fail). In some implementations, the OK value can be determined by determining if at least one error in the second portion (codeword YZ) matches with at least one error in the first portion (codeword X). By contrast, a not OK value can be returned if the error locations in the second portion (codeword YZ) are different from the error locations in the first portion (codeword X). This coherency check can thus be used to leverage the relation between codeword portions to quickly confirm or reject errors. If the coherency check passes, the method can correct the codewords in step1026as described above. By contrast, if the coherency check fails, the method can mark the codeword as uncorrectable in step1018as described previously.

Returning to step1002, the final scenario, the ECC2 engine of step1002may detect two errors in codeword X. In this scenario, step1030may be performed on codeword YZ, as will be described next herein with respect to the steps ofFIG.11.

Turning toFIG.11, this method may be called when the method ofFIG.10detects two errors in the first portion of the codeword (codeword X). In step1102, the method can include applying an extended ECC error correction operation to the second portion of the codeword (codeword YZ).

In a first scenario, the method may detect no errors in the second portion of the codeword. In this scenario, the method proceeds to step1108where the errors in the codeword are corrected. In some implementations the codeword can be corrected using an appropriate ECC engine. Specifically, an ECC2 engine is used to correct codeword X while the extended ECC2 engine is used to correct codeword YZ. Notably in step1108the actual error correction is performed.

In another scenario, the method may detect a single error in the second portion of the codeword. In this scenario, the method performs a coherency check in step1104. As with step1016, this coherency check may return an OK or not OK value based on comparing the positions of errors in each portion of the codeword. Details of the coherency check are the same as those in step1016and not repeated herein. If the coherency check passes (i.e., yields an OK value), the method proceeds to step1108and corrects the errors in the codeword. Step1108is described above and not repeated herein. By contrast, if the coherency check fails (not OK), the method proceeds to step1106and marks the codeword as uncorrectable.

In a third scenario, the method may detect two errors in the second portion of the codeword or may alternatively fail. In this scenario, the method can proceed to step1110where a second coherency check is performed on the codeword portions (identical to that described in step1104). If the coherency check passes (OK), the method proceeds to step1108and corrects the errors in the codeword. Step1108is described above and not repeated herein. By contrast, if the coherency check fails (not OK), the method proceeds to step1112, described herein.

Finally, if the extended ECC operation in step1102indicates three errors (and in some implementations if the extended ECC operation fails), or if the coherency check in step1110fails, the method may proceed to step1112where bits of codeword YZ are inverted based on the detected errors in codeword X. Specifically, in some implementations, the method identifies which bits in codeword X are associated with detected errors and inverts the corresponding codeword YZ bits. As discussed above, a given bit in codeword X may correspond (e.g., based on addressing) to a corresponding bit in codeword YZ. Thus, the ECC2 engine may indicate the address of the errors in codeword X and this address can be used to identify the corresponding bits in codeword YZ that should be inverted. After performing this inversion in step1112, the method proceeds to step1114where a second extended ECC operation is performed on the second portion (codeword YZ). Here, if the second extended ECC operation indicates three errors, the method proceeds to step1106and marks the codeword as uncorrectable. By contrast, if the second extended ECC operation yields any other result (e.g., zero to two errors or, optionally, a failure), the method proceeds to step1108where the codeword portions are corrected (as discussed previously).

The computing system100can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), an Internet of Things (IoT) enabled device, an embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes memory and a processing device.

The host system122can include a processor chipset (e.g., processing device118) and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., controller116) (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system122uses the memory sub-system110, for example, to write data to the memory sub-system110and read data from the memory sub-system110.

The processing device118of the host system122can be, for example, a microprocessor, a central processing unit (CPU), a processing core of a processor, an execution unit, etc. In some instances, the controller116can be referred to as a memory controller, a memory management unit, and/or an initiator. In one example, the controller116controls the communications over a bus coupled between the host system122and the memory sub-system110. In general, the controller116can send commands or requests to the memory sub-system110for desired access to memory devices130,140. The controller116can further include interface circuitry to communicate with the memory sub-system110. The interface circuitry can convert responses received from memory sub-system110into information for the host system122.

The controller116of the host system122can communicate with controller115of the memory sub-system110to perform operations such as reading data, writing data, or erasing data at the memory devices130,140and other such operations. In some instances, the controller116is integrated within the same package of the processing device118. In other instances, the controller116is separate from the package of the processing device118. The controller116and/or the processing device118can include hardware such as one or more integrated circuits (ICs) and/or discrete components, a buffer memory, a cache memory, or a combination thereof. The controller116and/or the processing device118can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

The memory devices130,140can include any combination of the different types of non-volatile memory components and/or volatile memory components. The volatile memory devices (e.g., memory device140) can be, but are not limited to, random access memory (RAM), such as dynamic random-access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

A memory sub-system controller115(or controller115for simplicity) can communicate with the memory devices130to perform operations such as reading data, writing data, or erasing data at the memory devices130and other such operations (e.g., in response to commands scheduled on a command bus by controller116). The controller115can include hardware such as one or more integrated circuits (ICs) and/or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (e.g., hard-coded) logic to perform the operations described herein. The controller115can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor.

In some embodiments, the memory devices130include local media controllers131that operate in conjunction with memory sub-system controller115to execute operations on one or more memory cells of the memory devices130. An external controller (e.g., memory sub-system controller115) can externally manage the memory device130(e.g., perform media management operations on the memory device130). In some embodiments, a memory device130is a managed memory device, which is a raw memory device combined with a local controller (e.g., local media controller131) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

The controller115and/or a memory device130can include a programming manager113, such as the programming manager113discussed above in connection withFIGS.1to6. In some embodiments, the controller115in the memory sub-system110includes at least a portion of the programming manager113. In other embodiments, or in combination, the controller116and/or the processing device118in the host system122includes at least a portion of the programming manager113. For example, the controller115, the controller116, and/or the processing device118can include logic circuitry implementing the programming manager113. For example, the controller115, or the processing device118(e.g., processor) of the host system122, can be configured to execute instructions stored in memory for performing the operations of the programming manager113described herein. In some embodiments, the programming manager113is implemented in an integrated circuit chip (e.g., memory device130) installed in the memory sub-system110. In other embodiments, the programming manager113can be part of firmware of the memory sub-system110, an operating system of the host system122, a device driver, or an application, or any combination therein.

FIG.13illustrates an example machine of a computer system300within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. In some embodiments, the computer system300can correspond to a host system (e.g., the host system122ofFIG.12) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system110ofFIG.12) or can be used to perform the operations of a programming manager113(e.g., to execute instructions to perform operations corresponding to the programming manager113described with reference toFIGS.12and13). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The example computer system300includes a processing device302, a main memory304(e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), static random access memory (SRAM), etc.), and a data storage system318, which communicate with each other via a bus330(which can include multiple buses).

The data storage system318can include a machine-readable medium324(also known as a computer-readable medium) on which is stored one or more sets of instructions326or software embodying any one or more of the methodologies or functions described herein. The instructions326can also reside, completely or at least partially, within the main memory304and/or within the processing device302during execution thereof by the computer system300, the main memory304and the processing device302also constituting machine-readable storage media. The machine-readable medium324, data storage system318, and/or main memory304can correspond to the memory sub-system110ofFIG.12.