Semiconductor memory devices and methods of manufacturing thereof

A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.

BACKGROUND

DETAILED DESCRIPTION

In general, a 3D memory device (sometimes referred to as a semiconductor device) includes a number of memory blocks. Each memory block includes at least one memory array (or sub-array) of memory cells formed in a stack of insulating layers and conductive layers. The array of memory devices are formed in a stack of insulating layers and gate layers and may include a plurality of gate layers. The memory cells are formed across multiple memory levels (or tiers) over a substrate. For example, each memory cell can be constituted by at least one of: a portion of a semiconductor channel layer that continuously extends along a vertical direction of the array, a portion of a memory film that continuously extends along the vertical direction, a first conductive structure (functioning as a drain electrode) that continuously extends along the vertical direction, a second conductive structure (functioning as a source electrode) that continuously extends along the vertical direction, and one of a plurality of third conductive structures (functioning as gate layers or gate electrodes) that continuously extend along a first lateral direction of the array. The drain electrode, source electrode, and gate layers may sometimes be referred to as “bit line (BL),” “source/select line (SL), and “word line (WL),” respectively.

In some cases, the memory block further includes an interface portion formed on either or both sides of the memory array to allow electrical connection to the memory cells included in the array. For example, the WLs may extend from the array (which is sometimes referred to as a device portion) and further along the interface portion(s). The WLs can have a staircase profile in the interface portion. A number of WL staircase vias, electrically and physically coupled to respective WLs, are generally formed in the interface portions. Further, the WL staircase vias are electrically and physically coupled through metal routings to a number of WL vias. As will be discussed below, a controller (e.g., a memory core control circuit) can provide suitable (e.g., voltage) levels of bias for different WLs, through such interconnect structures in the interface portion.

In some cases, the memory array can include a certain number of memory levels (e.g., about 16 memory levels), which causes the BLs/SLs to have a relatively high aspect ratio or ratio of the height to the weight. With such a high aspect ratio, the BLs and SLs can be formed as having a tapered profile. Generally, the channel length of a memory cell is defined as the length of a portion of a semiconductor channel that is interposed between the BL and SL. Alternatively stated, the channel length may correspond to the distance separating respective (inner) sidewalls of the BL and the SL along a lateral direction. Because of the tapered profile of the BL and SL, the respective channel lengths of memory cells arranged along a vertical direction (which are sometimes referred to as a memory string) can vary. For example, when the BL and SL are formed to have a wider upper portion and a narrower lower portion, the channel length of a memory cell disposed at a lower level may be longer than the channel length of a memory cell disposed at a higher level. Such non-uniform (or otherwise varying) channel lengths can disadvantageously impact overall performance of the memory array. As the current level of each memory cell is generally proportional to its channel length, the varying channel lengths result in varying levels of cell current. For example, a longer (or longer than expected) channel length can lead to an undesired, insufficient cell current level, while a shorter (or shorter than expected) channel length can lead to an undesired, overwhelming cell current level.

Embodiments of the present disclosure are discussed in the context of forming a semiconductor device, and particularly in the context of forming a 3D memory device, that can compensate for varying cell currents. In accordance with various embodiments, even with the tapered profile of the BL and SL being formed which causes a varying channel length, the 3D memory device, as disclosed herein, includes a plurality of WLs that are provided with different levels of bias by a controller to compensate for the varying cell current. For example, the cell current of a longer channel length can be compensated through applying, by the controller, a higher (e.g., voltage) level of bias, which can compensate for the lower cell current. On the other hand, the controller can apply a lower (e.g. voltage) level of bias to word lines with shorter channel lengths, which can compensate for the higher cell current. As such, the current levels of a number of memory cells (e.g., the memory cells of a memory string) can be adjusted to be uniform. Alternatively or additionally, by controlling the level of bias to vary in the direction where memory cells of a memory string are (e.g., vertically) arranged, current levels of those memory cells can be accordingly modulated, as desired, which will be discussed in further detail below.

FIG.1illustrates a perspective view of a semiconductor device100, in accordance to some embodiments. In some embodiments, the semiconductor device100depicts the device portion of a memory block. The semiconductor device100includes an array of memory cells102. The semiconductor device may be disposed on a substrate (e.g., a silicon, or silicon on insulator (SOI) substrate) (not shown). When viewed from the top, such an array may be arranged in a column-row configuration, e.g., having a number of rows extending along a first lateral direction (e.g., the X-direction) and a number of columns extending along a second lateral direction (e.g., the Y-direction). Within each row, a number of memory cells102can be separated and electrically isolated from one another by an isolation structure104. Each memory cell102can include a source line (SL)106and a bit line (BL)108separated and electrically isolated from each other by an inner spacer110.

The semiconductor device100can include one or more semiconductor channels112. The semiconductor channel112, extending along the vertical direction (e.g., the Z-direction), can be disposed along each of the opposite surfaces (or sidewalls) of the SL106and BL108in the Y-direction, which may be better seen in the cut-out portion ofFIG.1. Each semiconductor channel112can extend in the first lateral direction (e.g., the X-direction), with itself physically separated or electrically isolated from another semiconductor channel112within the row (along the X-direction).

The semiconductor device100can include one or more memory films114. The memory film114, extending along the vertical direction (e.g., the Z-direction), can be disposed along a surface (or sidewall) of each semiconductor channel112opposite from the SL106and BL108in the Y-direction. The memory film114can extend in the first lateral direction (e.g., the X-direction).

In some embodiments, a number of memory cells102can be defined in the semiconductor device100. A memory cell102can be constituted by a BL, a SL, a portion of a semiconductor channel, a portion of a memory film, and a word line (WL) (which will be discussed below). In the configuration of exampleFIG.1, within one of the rows of the array, a number of memory cells102can be formed on the opposite sides of each pair of the BL and SL. For example, a first memory cell102can be partially defined by a portion of a memory film114and a portion of a semiconductor channel112disposed on one side of each pair of SL106and BL108, and a second memory cell102can be partially defined by a portion of a memory fill114and a portion of a semiconductor channel112disposed on the other side of that pair of SL106and BL108. Alternatively stated, these two memory cells102may share one pair of BL and SL. Further, each row can extend along the vertical direction (e.g., the Z-direction) to include an additional number of memory cells, thereby forming a number of memory strings. It should be understood that the semiconductor device100shown inFIG.1is merely an illustrative example, and thus, the semiconductor device100can be formed in any of various other 3D configurations, while remaining within the scope of present disclosure.

The semiconductor device100also includes a plurality of WLs120and a plurality of insulating layers118alternatively stacked on top of one another in the vertical direction (e.g., the Z-direction) which form a stack116disposed on outer surfaces of the memory film114(along the Y-direction), such that the stack116can be interposed between adjacent rows of memory cells102. In some embodiments, a topmost layer and a bottommost layer of the stack116may include an insulating layer118of the plurality of insulating layers118. The bottommost insulating layer118may be disposed on the substrate.

Each of the plurality of WLs120extends in semiconductor device100along the respective row of memory cells102along the first lateral direction (e.g. the X-direction). The insulating layers118may also extend along the first lateral direction (e.g., the X-direction). Two parallel WLs120may be located adjacent to each other in a second lateral direction that is perpendicular to the first lateral direction and in the same plane (e.g., the Y-direction), and may be interposed between two vertically separated insulating layers118. In some embodiments, an adhesive layer122may be interposed between the WLs120and the adjacent insulating layers118, and facilitate adhesion of the WL120to the insulating layer118, and may also serve as a spacer between two parallel WLs120that are interposed between the same vertically separated insulating layers118. In some embodiments, the adhesive layer122is optional.

As a representative example inFIG.1, one of a number memory cells102can be defined by the SL106, the BL108, a portion of the semiconductor channel112, a portion of the memory film114, and one of the WLs120. The SL106has an inner sidewall107and the BL108has an inner sidewall109, a distance of which can define the channel length of such a memory cell. When the SL and the BL are formed in a tapered profile, as shown inFIG.1, respective channel lengths of the memory cells arranged in the Z-direction (a vertical direction) may vary. In some embodiments, by controlling (e.g., voltage) levels applied to the WLs120operatively coupled to those vertically arranged memory cells to vary, the varying channel lengths of those memory cells can be compensated for more controllable overall performance of the semiconductor device100.

FIG.2Aillustrates a block diagram including a memory system200and a host202, in accordance with various embodiments. As will be discussed below, the memory system200can include one or more above-discussed semiconductor devices100. The memory system200may include a non-volatile storage system interfacing with the host202(e.g., a mobile computing device). In some embodiments, the memory system200may be embedded within the host202. In some embodiments, the memory system200may include a memory card. As shown, the memory system200includes a memory chip controller204and a memory chip206. Although a single memory chip206is shown, the memory system200may include more than one memory chip (e.g., four, eight or some other number of memory chips). The memory chip controller204can receive data and commands from the host202and provide memory chip data to the host202.

The memory chip controller204may include one or more state machines, page registers, SRAM, and control circuitry for controlling the operation of the memory chip206. The one or more state machines, page registers, static random access memory (SRAM), and control circuitry for controlling the operation of the memory chip206may be referred to as managing or control circuits. The managing or control circuits may facilitate one or more memory array operations, such as forming, erasing, programming, and reading operations.

In some embodiments, the managing or control circuits (or a portion of the managing or control circuits) for facilitating one or more memory array operations may be integrated within the memory chip206. The memory chip controller204and memory chip206may be arranged on a single integrated circuit. In other embodiments, the memory chip controller204and memory chip206may be arranged on different integrated circuits. In some cases, the memory chip controller204and memory chip206may be integrated on a system board, logic board, or a printed circuit board (PCB).

The memory chip206includes memory core control circuit208and a memory core210. In various embodiments, the memory core control circuit208may include logic for controlling the selection of memory blocks (or arrays) within the memory core210such as, for example, controlling the generation of voltage references for biasing a particular memory array into a read or write state, generating row and column addresses, applying respective voltage levels of biases on different memory cells that have different channel lengths, which will be discussed in further detail below.

The memory core210may include one or more two-dimensional arrays of non-volatile memory cells or one or more three-dimensional arrays of non-volatile memory cells. In an embodiment, the memory core control circuit208and memory core210are arranged on a single integrated circuit. In other embodiments, the memory core control circuit208(or a portion of the memory core control circuit208) and memory core210may be arranged on different integrated circuits.

An example memory operation may be initiated when the host202sends instructions to the memory chip controller204indicating that the host202would like to read data from the memory system200or write data to the memory system200. In the event of a write (or programming) operation, the host202will send to the memory chip controller204both a write command and the data to be written. The data to be written may be buffered by the memory chip controller204and error correcting code (ECC) data may be generated corresponding with the data to be written. The ECC data, which allows data errors that occur during transmission or storage to be detected and/or corrected, may be written to the memory core210or stored in non-volatile memory within the memory chip controller204. In an embodiment, the ECC data are generated and data errors are corrected by circuitry within the memory chip controller204.

The memory chip controller204can control operation of the memory chip206. In one example, before issuing a write operation to the memory chip206, the memory chip controller204may check a status register to make sure that the memory chip206is able to accept the data to be written. In another example, before issuing a read operation to the memory chip206, the memory chip controller204may pre-read overhead information associated with the data to be read. The overhead information may include ECC data associated with the data to be read or a redirection pointer to a new memory location within the memory chip206in which to read the data requested. Once a read or write operation is initiated by the memory chip controller204, the memory core control circuit208may, for example, generate the appropriate levels of biases for word lines (WLs) and bit lines (BLs) within the memory core210, and generate the appropriate memory block, row, and column addresses.

FIG.2Billustrates one example block diagram of the memory core control circuit208, in accordance with various embodiments. As shown, the memory core control circuit208includes an address decoder220, a voltage generator for first access lines222, a voltage generator for second access lines224, and a signal generator for reference signals226. In some embodiments, access lines may include word lines (WLs), bit lines (BLs), source/select lines (SLs), or combinations thereof. First access lines may include selected WLs, selected BLs, and/or selected SLs that are used to place non-volatile memory cells into a selected state. Second access lines may include unselected WLs, unselected BLs, and/or unselected SLs that are used to place non-volatile memory cells into an unselected state.

In accordance with various embodiments, the address decoder220can generate memory block addresses, as well as row addresses and column addresses for a particular memory block. The voltage generator (or voltage regulators) for first access lines222can include one or more voltage generators for generating first (e.g., selected) access line voltages. The voltage generator for second access lines224can include one or more voltage generators for generating second (e.g., unselected) access line voltages. The signal generators for reference signals226can include one or more voltage and/or current generators for generating reference voltage and/or current signals.

FIGS.2C-2Eillustrate an example organization of the memory core210, in accordance with various embodiments. The memory core210includes a number of memory banks, and each memory bank includes a number of memory blocks. Although an example memory core organization is disclosed where memory banks each include memory blocks, and memory blocks each include a group of non-volatile memory cells (arranged as a memory array or sub-array), other organizations or groupings also can be used, while remaining within the scope of the present disclosure.

FIG.2Cillustrates an example block diagram of the memory core210, in accordance with various embodiments. As shown, the memory core210includes memory banks230,232, etc. It should be appreciated the memory core200can include any number of memory banks, while remaining within the scope of the present disclosure. For example, a memory core may include only a single memory bank or multiple memory banks (e.g.,16or other number of memory banks).

FIG.2Dillustrates an example block diagram of one of the memory banks (e.g.,230shown inFIG.2C), in accordance with various embodiments. As shown, the memory bank230includes memory blocks240,241,242,243,244,245,246, and247, and a read/write circuit248. It should be appreciated the memory bank230can include any number of memory blocks, while remaining within the scope of the present disclosure. For example, a memory bank may include one or more memory blocks (e.g.,32or other number of memory blocks per memory bank). The read/write circuit248can include circuitry for reading and writing memory cells within the memory blocks240-247.

In some embodiments, the read/write circuit248may be shared across multiple memory blocks within a memory bank. This allows chip area to be reduced because a single group of read/write circuit248may be used to support multiple memory blocks. However, in some embodiments, only a single memory block may be electrically coupled to the read/write circuit248at a particular time to avoid signal conflicts. In some embodiments, the read/write circuit248may be used to write one or more pages of data into the memory blocks240-247(or into a subset of the memory blocks). The non-volatile memory cells within the memory blocks240-247may permit direct over-writing of pages (i.e., data representing a page or a portion of a page may be written into the memory blocks240-247without requiring an erase or reset operation to be performed on the non-volatile memory cells prior to writing the data).

In some cases, the read/write circuit248may be used to program a particular non-volatile memory cell to be in one of multiple (e.g., 2, 3, etc.) data states. For example, the particular non-volatile memory cell may include a single-level or multi-level non-volatile memory cell. In one example, the read/write circuits248may apply a first voltage difference (e.g., 2V) across the particular non-volatile memory cell to program the particular non-volatile memory cell into a first state of the multiple data states or a second voltage difference (e.g., 1V) across the particular non-volatile memory cell that is less than the first voltage difference to program the particular non-volatile memory cell into a second state of the multiple data states.

FIG.2Eillustrates an example block diagram of one of the memory blocks (e.g.,240) of the memory bank230ofFIG.2D, in accordance with various embodiments. As shown, the memory block240includes a memory array (or sometimes referred to as a memory sub-array)250, a row decoder252, and a column decoder254. As disclosed herein, the memory array250may be implemented as the semiconductor device100, as shown inFIG.1. For example, such a memory array250includes a contiguous group of non-volatile memory cells, each of which can be accessed through a respective combination of access lines (e.g., a combination of one of contiguous WLs, one of contiguous BLs, and one of contiguous SLs). Such access lines may sometimes be referred to as an interface portion of the memory block, in some embodiments. The memory array250may include one or more layers of non-volatile memory cells. The memory array250may include a two-dimensional memory array and/or a three-dimensional memory array. The device portion may be formed within the memory array250, which will be shown and discussed in further detail below.

The row decoder252can decode a row address and select a particular WL, when appropriate (e.g., when reading or writing non-volatile memory cells in the memory array250). The column decoder254can decode a column address and select one or more BLs/SLs in the memory array250to be electrically coupled to read/write circuits, such as the read/write circuit248inFIG.2D. As a non-limiting example, the number of WLs is in the range of 4K per memory layer, the number of BLs/SLs is in the range of 1K per memory layer, and the number of memory layers is 4, which renders about 16M non-volatile memory cells contained in the memory array250(of the memory block240).

FIG.3illustrates a perspective view of an example portion of the memory block240, according to various embodiments of the present disclosure. In the following discussions, the memory block240(sometimes referred to as a semiconductor device or a memory device) is selected as a representative example. It should be understood that other memory blocks (of the memory bank230ofFIG.2D) are substantially similar to the memory block240, and thus, the discussions are not repeated. Further, the perspective view ofFIG.3is simplified, and thus, it should be understood that any of various other features/components can also be included inFIG.3, while remaining within the scope of the present disclosure.

As shown, the memory block240includes a device portion302. The device portion302inFIG.3can be a portion of the memory array250(FIG.2E), which may be implemented as the semiconductor device100shown inFIG.1. Hereinafter, the device portion302may sometimes be referred to as “memory array302.” The memory array302includes a number of memory cells formed across a number of memory layers (e.g., 3 memory layers as shown) stacked on top of one another along a vertical direction, e.g., the Z direction. In addition, the memory block240includes a number of interface portions304located next to the device portion302, which allows each memory cell of the memory array302to be accessed (or otherwise controlled). The interface portions304each have a staircase or step profile in the Z-direction, as described later in further detail herein.

To electrically access the memory array302through the interface portion304, the memory block240further includes a number of first interconnect structures306(e.g., via structures or WL staircase vias) extending along the Z-direction that land on respective stairs of a number of word lines308of the interface portion304. In some embodiments, the memory block240also includes a number of second interconnect structures310(sometimes referred to as WL vias) extending along the Z-direction that may be electrically coupled to the memory core control circuit208configured to apply a varying bias to each word line. In some embodiments, each WL via310is electrically coupled to a corresponding WL staircase via306through a metal routing314. For the purposes of clarity, three groups of WL staircase306, WL via310, and metal routing314, coupled to three stairs of WLs308along a certain row of the memory block240, are shown, but it should be understood that the memory block240can include a greater number of such groups that are coupled to the stairs of WLs along other row. According to some embodiments, a controller (e.g., memory core control circuit208) can apply suitable voltage levels of bias to the different WLs308through such interconnect structures.

FIGS.4A-Cillustrate a flowchart of an example method400for forming at least a portion of a semiconductor device500, for example, a 3D memory device (e.g., the semiconductor devices100and300described with respect toFIGS.1and3, respectively), in accordance with some embodiments. It should be noted that the method400is merely an example, and is not intended to limit the present disclosure. Accordingly, it is understood that the order of operation of the method400ofFIGS.4A-Ccan change, that additional operations may be provided before, during, and after the method400ofFIGS.4A-C, and that some other operations may only be described briefly described herein.

In some embodiments, operations of the method400may be associated with perspective views of the example semiconductor device500at various fabrication stages as shown inFIGS.5,6,7,8,9,10,11,12,13,14,15,16,17, and18. In addition, the operations of the method400are equally applicable to any other semiconductor device, for example, a semiconductor device600shown inFIG.21, a semiconductor device700shown inFIG.23, or any other semiconductor device. AlthoughFIGS.5-18illustrate the semiconductor device500including a plurality of memory cells, it should be understood the semiconductor device500,600, or700may include a number of other devices such as inductors, fuses, capacitors, coils, etc., which are not shown inFIGS.5-19B,21, and23, for purposes of clarity of illustration.

In a brief overview, the method400may start with the operation402in which a semiconductor substrate is provided. The method400continues to operation404in which a stack is provided wherein the stack comprises a plurality of insulating layers and a plurality of sacrificial layers alternatively stacked on top of each other. The method400continues to operation406in which the stack is patterned to form a staircase profile. The method400continues to operation408in which an interlayer dielectric (ILD) is deposited. The method400continues to operation410in which a plurality of trenches extending in a first lateral direction (e.g., the X-direction) are formed. The method400continues to operation412in which the plurality of sacrificial layers are partially etched. The method400continues to operation414in which a plurality of word lines are formed. The method400continues to operation416in a memory layer or memory film is formed. The method400continues to operation418in which a semiconductor channel layer is formed. The method400continues to operation420in which the semiconductor channel layer is cut to form a semiconductor channel.

The method400continues to operation422in which an insulation layer is formed. The method400continues to operation424in which a chemical mechanical polish (CMP) process applied which may remove any excess insulation material. The method400continues to operation426in which a plurality of second trenches are formed in the first direction. The method400continues to operation428in which the remaining portions of the sacrificial value are removed. The method400continues to operation430in which a second set of word lines are formed. The method400continues to operation432in which a second memory layer or film is formed. The method400continues to operation434in which a second semiconductor channel layer is formed. The method400continues to operation436in which the second semiconductor channel layer is cut to form a semiconductor channel. The method400continues to operation438in which an insulation layer is formed. The method400continues to operation440in which a CMP process is applied. The method400continues to operation442in which BLs and SLs are formed. The method400continues to operation444in which WL staircase vias are formed in a vertical direction in the interface portions.

Corresponding to operations402-404ofFIG.4,FIG.5is a perspective view of a semiconductor device500including a substrate501and a stack116, in accordance with some embodiments.

The stack116is formed on the substrate501. The stack includes a plurality of insulating layers118and a plurality of sacrificial layers524alternately stacked on top of each other in the vertical direction (e.g., the Z-direction). For example, one of the sacrificial layers524is disposed over one of the insulating layers118, then another one of the insulating layers118is disposed on the sacrificial layer524, so on and so forth. As shown inFIG.5, a topmost layer (e.g., a layer distanced most from the substrate501) and a bottommost layer (e.g., a layer most proximate to the substrate501) of the stack116may include an insulating layer118. WhileFIG.5shows the stack116as including 4 insulating layers118and3sacrificial layers524, the stack116may include any number of insulating layers118and sacrificial layers524(e.g., 4, 5, 6, 7, 8, or even more). In various embodiments, if the number of sacrificial layers524in the stack116is n, a number of insulating layers118in the stack116may be n+1.

Each of the plurality of insulating layers118may have about the same thickness, for example, in a range of about 5 nm to about 100 nm, inclusive. Moreover, the sacrificial layers524may have the same thickness or different thickness from the insulating layers118. The thickness of the sacrificial layers524may range from a few nanometers to few tens of nanometers (e.g., in a range of 5 nm to 100 nm, inclusive). It is understood that the insulating layers118and the sacrificial layers524may have any suitable thickness.

The insulating layers118and the sacrificial layers524have different compositions. In various embodiments, the insulating layers118and the sacrificial layers524have compositions that provide for different oxidation rates and/or different etch selectivity between the respective layers. The insulating materials that can be employed for the insulating layer118include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides that are generally known as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. Other insulating materials are within the scope of the present disclosure. The sacrificial layers524may include an insulating material, a semiconductor material, or a conductive material. Non-limiting examples of the sacrificial layers524include silicon nitride, an amorphous semiconductor material (such as amorphous silicon), and a polycrystalline semiconductor material (such as polysilicon). In some embodiments, the insulating layers118may be formed from SiO, and the sacrificial layers524may be formed from SiN. The sacrificial layers524are merely spacer layers that are eventually removed and do not form an active component of the semiconductor device500.

In various embodiments, the insulating layers118and/or the sacrificial layers524may be grown over the substrate501. For example, each of the insulating layers118and the sacrificial layers524may be grown by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process such as a metal organic CVD (MOCVD) process, a furnace CVD process, an atomic layer deposition (ALD) process, and/or other suitable growth processes.

Corresponding to operation406ofFIG.4,FIG.6is a perspective view of a semiconductor device500in which the stack116is patterned to form a staircase profile at one of the various stages of fabrication, in accordance with various embodiments.

To form the staircase profile, a mask layer (not shown) is deposited on the stack (on the topmost insulating layer118), and is patterned. In some embodiments, the mask layer may include a photoresist (e.g., a positive photoresist or a negative photoresist), for example, a single layer or multiple layers of the same photoresist or different photoresists. In other embodiments, the mask layer may include a hard mask layer, for example, a polysilicon mask layer, a metallic mask layer, or any other suitable mask layer.

Next, the mask layer is patterned to etch portions of the mask layer at axial ends off the mask layer in the X-direction, for example, so as to reduce its axial width. The mask layer may be patterned using photolithography techniques. Generally, photolithography techniques utilize a photoresist material that forms the mask layer and that is deposited, irradiated (exposed), and developed to remove a portion of the photoresist material, in this instance, end portions of the mask layer. The remaining mask layer protects the underlying material, such as a portion of the stack116below the patterned mask layer, from subsequent processing steps, such as etching.

Next, respective portions of the topmost insulating layer118and the topmost sacrificial layer526on both sides of the mask layer in the X-direction, are etched. For example, the patterned mask layer is used to etch the exposed portions of the topmost insulating layer118and the topmost sacrificial layer524so as to form a first step (or stair)602(out of the topmost insulating layer118and sacrificial layer524) over the next lower insulating layer118and sacrificial layer524(i.e., the second topmost insulating layer118and sacrificial layer524). In some embodiments, the etch may be an anisotropic etch (e.g., a reactive ion etch (RIE), neutral beam etch (NBE), deep reactive ion etch (DRIE), any other suitable etch, or combinations thereof,) which selectively etches the exposed portions of the topmost insulating and sacrificial layers.

In some embodiments, the etching may include a first etch that selectively etches the topmost insulating layer118until the underlying (e.g., topmost) sacrificial layer524is exposed, and a second subsequent etch that etches the sacrificial layer524until the underlying (e.g., second topmost) insulating layer118is exposed. Such two-step etching process may allow the underlying sacrificial layer or the insulating layer to serve as a etch stop such that once a portion of the layer immediately above it has been removed, so as to prevent over-etching.

Next, the mask layer is again etched to reduce its axial width in the X-direction, followed by the two-step etching process to form a second step604(out of the second topmost insulating layer118and sacrificial layer524). By iteratively performing the width reduction process on the mask layer and the two-step etching process, the stack116can be patterned to include a number of steps (e.g., steps602,604, and606), which results in the staircase profile as shown inFIG.6.

Corresponding to operation408ofFIG.4,FIG.7is a perspective view of the semiconductor device500in which an ILD702is formed over the stack116(having the staircase profile) at one of the various stages of fabrication, in accordance with various embodiments.

The ILD702can be formed by depositing a dielectric material in bulk over the partially formed semiconductor device500, and polishing the bulk oxide back (e.g., using CMP) to the level off the topmost insulating layer118, such that the ILD702is disposed only over the steps602-606. The dielectric material of the ILD702may include SiO, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate Glass (BPSG), undoped silicate glass (USG), any other suitable material, or combinations thereof. Moreover, a portion of the semiconductor device500comprising the staircase steps602-606and the ILD702can be defined as an interface portion706. A portion of the semiconductor device500comprising the stack116of alternating insulating layers118and sacrificial layers524can be defined as a device portion704.

Corresponding to operation410ofFIG.4,FIG.8is a perspective view of the semiconductor device500with a plurality of first trenches802formed extending in the X-direction, in accordance with some embodiments. Although three first trenches802are shown in the embodiment ofFIG.8, it should be understood that the semiconductor device500can include any numbers of first trenches802, while remaining within the scope of the present disclosure.

The plurality of first trenches802extending in the X-direction, have been formed through the stack116up to the substrate501by etching the stack116in the Z-direction. The etching process for forming the plurality of first trenches802may include a plasma etching process, which can have a certain amount of anisotropic characteristic. For example, the first trenches802may be formed, for example, by depositing a photoresist or other masking layer on a top surface of the semiconductor device500, i.e., the top surface of the topmost insulating layer118of the stack116, and a pattern corresponding to the first trenches802defined in the masking layer (e.g., via photolithography, e-beam lithography, or any other suitable lithographic process).

The first trenches802may be formed using a plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes, ME, DRIE), gas sources such as Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, NF3, and other suitable etch gas sources and combinations thereof can be used with passivation gases such as N2, O2, CO2, SO2, CO, CH4, SiCl4, and other suitable passivation gases and combinations thereof. Moreover, for the plasma etching process, the gas sources and/or the passivation gases can be diluted with gases such as Ar, He, Ne, and other suitable dilutive gases and combinations thereof to form the first trenches802.

As a non-limiting example, a source power of 10 Watts to 3,000 Watts, a bias power of 0 watts to 3,000 watts, a pressure of 1 millitorr to 5 torr, and an etch gas flow of 0 sccm to 5,000 sccm may be used in the etching process. However, it is noted that source powers, bias powers, pressures, and flow rates outside of these ranges are also contemplated. As shown inFIG.8, the etch used to form the plurality of first trenches802etches through each of the sacrificial layers524and insulating layers118of the stack116such that each of the plurality of first trenches802extend form the topmost insulating layer118through the bottommost insulating layer118to the substrate501. In other embodiments, a hard mask may be used. In some embodiments, the first trenches802may be formed with a varying width along, the Y-direction. In some embodiments, the first trenches802may be etched with an increasing width as the height of first trench802increases in the Z-direction, as shown inFIG.8. In some embodiments, the upper portion of the first trench802may be exposed to more etchants in order to create the varying width.

In some embodiments, the first trenches802may have a first portion802A and a second portion802B along the Z-direction. In some embodiments, the width of the first trenches802may decrease along the first portion802A and increase along the second portion802B with an increasing height along the Z-direction. In some embodiments, the width of the first trenches802may increase along the first portion802A and decrease along the second portion802B with an increasing height along the Z-direction.

As a result of forming the first trenches802, fin-like structures804are formed. As shown, the fin-like structures804(sometimes referred to as stripe structures) all extend along a lateral direction (e.g., the X direction), and are in parallel with one another. Each of the fin-like structures804includes a number of layers (or tiers) alternately stacked on top of one another. In particular, each fin-like structure includes an alternate stack of a number of (remaining portions of) the insulating layers118, a number of (remaining portions of) the sacrificial layers524, and a remaining portion of the ILD702.

Corresponding to operations412-414ofFIG.4,FIG.9is a perspective view of the semiconductor device500with a plurality of word lines (WLs)902formed after partially etching the sacrificial layers524within the first trenches802, in accordance with some embodiments.

At operation412, the exposed surfaces of the sacrificial layers524within the trenches in each of the fin-like structures are partially etched so as to reduce a width of the sacrificial layers relative to the insulating layers118in the stack116(not shown). The exposed surfaces extend in the X-direction, and etching the exposed surfaces of the sacrificial layers524reduces a width of the insulating layers118on either side of the sacrificial layers524in the Y-direction. Such an etch-back distance can be controlled to be less than one half the width of the sacrificial layer118along the Y-direction, so as to remain a central portion of the sacrificial layers118intact, as shown inFIG.9. In some embodiments, the sacrificial layers524may be etched using a wet etch process (e.g., hydrofluoric etch, buffered hydrofluoric acid). In other embodiments, the exposed surfaces of the sacrificial layers524may be partially etched using a plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes, RIE, DRIE), gas sources such as Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, NF3, and other suitable etch gas sources and combinations thereof can be used with passivation gases such as N2, O2, CO2, SO2, CO, CH4, SiCl4, and other suitable passivation gases and combinations thereof. Moreover, for the plasma etching process, the gas sources and/or the passivation gases can be diluted with gases such as Ar, He, Ne, and other suitable dilutive gases and combinations thereof. As a non-limiting example, a source power of 10 Watts to 3,000 Watts, a bias power of 0 watts to 3,000 watts, a pressure of 1 millitorr to 5 torr, and an etch gas flow of 0 sccm to 5,000 sccm may be used in the etching process. However, it is noted that source powers, bias powers, pressures, and flow rates outside of these ranges are also contemplated.

Partially etching the sacrificial layers in the Y-direction reduces a width of the sacrificial layers524relative to the insulating layers118disposed in the stack116such that first cavities are formed whose boundaries are formed by top and bottom surfaces of adjacent insulating layers118and a surface of the partially etched sacrificial layers524that face the first trenches802and extend in the X-direction (not shown).

In some embodiments, an adhesive layer is then formed on sidewalls of the cavities (not shown). In some embodiments, the adhesive layer is optional. In various embodiments, the adhesive layers may include a material that has good adhesion with each of the insulating layers118, the sacrificial layers524, and the WLs902, for example, Ti, Cr, etc. In some embodiments, the adhesive layer (e.g., the adhesive layer122) may include e.g., titanium (Ti), chromium (Cr), or any other suitable adhesive material. The adhesive layers may be deposited using any suitable method including, for example, molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like. In some embodiments, the adhesive layer may have a thickness in a range of 0.1 nm to 5 nm, inclusive.

At operation414, a plurality of WLs902are formed in the first cavities located in the trenches. The exposed edges of the word lines may be etched back such that the edges of the WLs902facing the trenches are axially aligned in the Z-direction with corresponding edges of the insulating layers118disposed adjacent thereto, as shown inFIG.9.

In various embodiments, the WLs902are formed by filling a gate metal in the cavities over the optional adhesive layer, such that the WLs902inherit the dimensions and profiles of the cavities. The WLs902can be formed by filling the first cavities with a metal material. The metal material can be selected from the group consisting of aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chrome, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. Other metal materials are within the scope of the present disclosure. The WLs902can be formed by overlaying the workpiece with the above-listed metal material by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating, electroplating, any other suitable method, or combinations thereof.

Although each WL902shown inFIG.9is shown as a single layer, the word line material may include a stack of multiple metal materials. For example, the word line material may be a p-type work function layer, an n-type work function layer, multi-layers thereof, any other suitable material, or combinations thereof. The work function layer may also be referred to as a work function metal. Example p-type work function metals that may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Example n-type work function metals that may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. A work function value is associated with the material composition of the work function layer, and thus, the material of the work function layer is chosen to tune its work function value so that a target threshold voltage Vt (sometimes referred to as Vat) is achieved in the device that is to be formed. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable processes.

Formation of the WLs902in the cavities may cause edges of the WLs902in the Y-direction to protrude outwards of the cavities, i.e., outwards of the corresponding edges of the insulating layers118, and/or the material forming the WLs902may also be deposited on exposed surfaces of the insulating layers118that face the first trenches802and/or the substrate501. The protruding edges of the WLs902are etched, for example, using a selective wet etching or dry etching process (e.g., RIE, DRIE, etc.) until any gate material deposited on the surfaces of the insulating layers118and/or the substrate501, and edges of the WLs902facing the first trenches802are substantially axially aligned with corresponding edges of the insulating layers118.

Corresponding to operations416ofFIG.4,FIG.10is a perspective view of the semiconductor device500in which memory layers1002,1012, and1022are formed in each of plurality of first trenches802on exposed surfaces of the insulating layers118and the WLs902located in the first trenches802, such that the memory layers1002-1012continuously extend along the X-direction, in accordance with some embodiments.

The memory layers1002-1012may include a ferroelectric material, for example, lead zirconate titanate (PZT), PbZr/TiO3, BaTiO3, PbTiO2, any other suitable material, or combinations thereof, etc. However, it should be understood that the memory layers1002-1022can include any of various other materials that are suitable as in memory devices, while remaining within the scope of the present disclosure. For example, the memory layers1002-1022can include a material selected from the group consisting of: HfO2, Hr1-xZrxO2, ZrO2, TiO2, NiO, TaOx, Cu2O, Nb2O5, AlOx, any other suitable material, or combinations thereof. The memory layers1002-1022may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), MBE, any other suitable process or a combination thereof. A conformal coating may be deposited such that the memory layers1002-1022are continuous on the walls of the first trenches426in the Z-direction. In some embodiments, a CMP operation may be performed after forming the memory layers1002-1022so that they will lie in the same X-Y plane or are level with a top surface of the topmost insulating layer118. In various embodiments, each of the memory layers1002-1012includes two portions, each of which is formed to extend along one of the sidewalls of a corresponding trench. As such, each portion of the memory layer is in contact with a corresponding number of WLs (through their respective exposed sidewalls). After formation, the memory layers1002-1022may sometimes be referred to as memory films.

Corresponding to operations418ofFIG.4,FIG.11is a perspective view of the semiconductor device500in which semiconductor channel layers1102,1112, and1122are formed within each of the plurality of first trenches802on exposed surfaces of the memory layers1002,1012, and1022, respectively, such that the semiconductor channel layers1102-1122also continuously extend along the X-direction in accordance with some embodiments.

In some embodiments, the semiconductor channel layers1102-1122may be formed from a semiconductor material, for example, Si (e.g., polysilicon or amorphous silicon), Ge, SiGe, silicon carbide (SiC), indium gallium zinc oxide (IGZO), indium tin oxide (ITO), indium zinc oxide (IZO), indium tungsten oxide (IWO), any other suitable material, or combinations thereof. The semiconductor channel layers1102-1122may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), MBE, any other suitable process, or a combination thereof. A conformal coating may be deposited such that the semiconductor channel layers1102-1122are continuous on the inner surface of the memory layers1002-1022, respectively. In some embodiments, a CMP operation may be performed after forming the semiconductor channel layers1102-1122so that they will lie in the same X-Y plane or are level with a top surface of the topmost insulating layer118. Over the memory layer, each of the channel layers1102-1122also includes two portions that are in contact with the two portions of a corresponding memory layer, respectively.

Corresponding to operations420-424ofFIG.4,FIG.12is a perspective view of the semiconductor device500in which the semiconductor channel layers1102-1122are cut along the X-direction to form semiconductor channels1102A-F,1112A-F, and1122A-F, respectively, and insulation layers are formed within each of the plurality of trenches, in accordance with some embodiments.

Corresponding to operation420, the semiconductor channel layers1102-1122are patterned by, for example, an anisotropic etching process to form a number of portions. Other methods of patterning the semiconductor channel layers1102-1122are within the scope of the present disclosure. The semiconductor channel layer1102is patterned to form a number of channel segments1102A,1102B,1102C,1102D,1102E, and1102F. The semiconductor channel layer1112is patterned to form a number of channel segments1112A,1112B,1112C,1112D,1112E, and1112F. The channel layer1122is patterned to form a number of channel segments1122A,1122B,1122C,1122D,1122E, and1122F. In various embodiments, each of the channel segments1102A-F,1112A-F, and1122A-F may extend along the X-direction with a length (LC), which may be configured to define the physical channel length of a memory cell. Each channel segment defines the initial footprint of a memory string.

Corresponding to operation422, insulation layers are formed within each of the plurality of trenches by filling each of the plurality of trenches with an insulating material such that a plurality of first device segments that include the memory layers1002-1022, the semiconductor channels1102A-1122F, and the insulation layers are formed in the semiconductor device, and extend in the first direction parallel to each other. The insulation layers form isolation structures1204,1214, and1224as well as inner spacers1210,1220, and1230.

Each of the trenches is filled with an insulating material (e.g., SiO2, SiN, SiON, SiCN, SiC, SiOC, SiOCN, any other suitable material, or combinations thereof) so as to form the insulation layer. In some embodiments, the insulation layers may be formed from the same material as the plurality of insulating layers118(e.g., SiO2). The insulation layers may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), MBE, any other suitable process or a combination thereof, a high aspect ratio process (HARP), another applicable process, or combinations thereof. Thus, a plurality of partially-formed memory cells1202that include the memory layers1002-1022, the semiconductor channels1102A-1122F, and the insulation layers are formed in the semiconductor device500, and extend in the X-direction parallel to each other.

The cavities filled with the insulation layer in between the partially-formed memory cells1206form the isolation structures1204,1214, and1224. The isolation structures1204-1224separate the semiconductor channels1102A-1122F into portions such that the semiconductor channels1102A-1122F are included in each memory cells1206.

As shown inFIG.12, each partially-formed memory cell1206includes an inner spacer1210,1220, or1230formed from a portion of the insulation layer extending between adjacent isolation structures1204-1224in the X-direction, in accordance with some embodiments. The semiconductor channels1102A-1122F are disposed on outer surfaces of the inner spacers1210-1230in the X-direction. Corresponding to operation424, a CMP process may then be performed after forming the insulation layer so that it will lie in the same X-Y plane or are level with a top surface of the topmost insulating layer118.

Corresponding to operations426-430ofFIG.4,FIG.13is a perspective view of the semiconductor device500in which a plurality of second trenches1302are formed between each of the first device segments such that the plurality of second trenches1302also continuously extends in the X-direction, and the remaining portions of the sacrificial layers524are etched to form a second set of WLs902, in accordance with some embodiments.

As with the first trenches802, the second trenches1302are formed by etching the stack116in the Z-direction to the substrate501.FIG.13depicts that two second trenches1302are formed, but it is understood that any number of second trenches can be formed (e.g., 2, 3, 4, 5, 6, 7, 8, 9, or 10 trenches). In some embodiments, the number of second trenches formed may be one less than the number of first trenches.

The plurality of second trenches1302may be formed using the same process used to form the first plurality of first trenches802. For example, the second trenches1302may be formed, for example, by depositing a photoresist or other masking layer on a top surface of the semiconductor device500, i.e., the top surface of the topmost insulating layer118of the stack116, and a pattern corresponding to the second trenches1302defined in the masking layer (e.g., via photolithography, e-beam lithography, or any other suitable lithographic process). In other embodiments, a hard mask may be used. Subsequently, semiconductor device500may be etched using a plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes, RIE, DRIE), gas sources such as Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, NF3, and other suitable etch gas sources and combinations thereof can be used with passivation gases such as N2, O2, CO2, SO2, CO, CH4, SiCl4, and other suitable passivation gases and combinations thereof. Moreover, for the plasma etching process, the gas sources and/or the passivation gases can be diluted with gases such as Ar, He, Ne, and other suitable dilutive gases and combinations thereof to form the second trenches1302. As a non-limiting example, a source power of 10 Watts to 3,000 Watts, a bias power of 0 watts to 3,000 watts, a pressure of 1 millitorr to 5 torr, and an etch gas flow of 0 sccm to 5,000 sccm may be used in the etching process. However, it is noted that source powers, bias powers, pressures, and flow rates outside of these ranges are also contemplated.

The etch used to form the plurality of second trenches1302etches through each of the sacrificial layers524and insulating layers118of the stack116such that each of the plurality of second trenches1302extend form the topmost insulating layer118through the bottommost insulating layer118to the substrate301. In some embodiments, the second trenches1302may be etched with an increasing width as the height of second trenches1302increases the Z-direction, as shown inFIG.13. In some embodiments, the upper portion of the second trenches1302may be exposed to more etchants in order to create the varying width.

In some embodiments, the second trenches1302may have a first portion1302A and a second portion1302B along the Z-direction. In some embodiments, the width of the second trenches1302may decrease along the first portion1302A and increase along the second portion1302B with an increasing height along the Z-direction. In some embodiments, the width of the second trenches1302may increase along the first portion1302A and decrease along the second portion1302B with an increasing height along the Z-direction.

Corresponding to operation428, the remaining portions of the sacrificial layers524are removed so as to form cavities between the insulating layers118adjacent to the previously formed WLs902(not shown). A second set of adhesive layers are optionally formed and WLs902are formed adjacent to the previously formed WLs902.FIG.13is a perspective view of the semiconductor device500after forming a second set of WLs902adjacent to the previously formed WLs902. The remaining portions of the sacrificial layers524may be etched using the same process as described by etching exposed portions of the sacrificial layers524in the second trenches1302until the sacrificial layers524are completely removed. This leaves cavities between adjacent layers of insulating layers118and adjacent to the WLs902. Optionally, an adhesive layer is deposited on walls of the newly formed cavities.

Corresponding to operation430, a WL902material is then deposited in the cavities so as to fill the cavities to form a second set of WLs902adjacent to the previously formed WLs902such that the two WLs902are disposed next to each other with the adhesive layer disposed therebetween. The WLs902may inherit the dimensions and profiles of the cavities. The WLs902can be formed by filling the first cavities with a metal material. The metal material can be selected from the group consisting of aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chrome, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. Other metal materials are within the scope of the present disclosure. The WLs902can be formed by overlaying the workpiece with the above-listed metal material by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating, electroplating, any other suitable method, or combinations thereof.

Although each WL902is shown as a single layer, the word line material may include a stack of multiple metal materials. For example, the word line material may be a p-type work function layer, an n-type work function layer, multi-layers thereof, any other suitable material, or combinations thereof. The work function layer may also be referred to as a work function metal. Example p-type work function metals that may include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Example n-type work function metals that may include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. A work function value is associated with the material composition of the work function layer, and thus, the material of the work function layer is chosen to tune its work function value so that a target threshold voltage Vt (sometimes referred to as Vat) is achieved in the device that is to be formed. The work function layer(s) may be deposited by CVD, physical vapor deposition (PVD), ALD, and/or other suitable processes.

Formation of the WLs902in the cavities may cause edges of the WLs902in the Y-direction to protrude outwards of the cavities, i.e., outwards of the corresponding edges of the insulating layers118, and/or the material forming the WLs902may also be deposited on exposed surfaces of the insulating layers118that face the second trenches1302and/or the substrate501. The protruding edges of the WLs902are etched, for example, using a selective wet etching or dry etching process (e.g., RIE, DRIE, etc.) until any gate material deposited on the surfaces of the insulating layers118and/or the substrate501, and edges of the WLs902facing the second trenches1302are substantially axially aligned with corresponding edges of the insulating layers118.

Corresponding to operation432ofFIG.4,FIG.14is a perspective view of the semiconductor device500in which a second set of memory layers1402and1412is formed in each of the second trenches1302on exposed surfaces of the insulating layers118and the WLs902located in the second trenches1302, such that the memory layers1402and1412continuously extend along the X-direction, in accordance with some embodiments.

The second set of memory layers1402and1412are substantially similar to the memory layers1002-1022. The memory layers1402and1412may include a ferroelectric material, for example, lead zirconate titanate (PZT), PbZr/TiO3, BaTiO3, PbTiO2, etc. However, it should be understood that the memory layers1402and1412can include any of various other materials that are suitable as in memory devices, while remaining within the scope of the present disclosure. For example, the memory layers1402and1412can include a material selected from the group consisting of: HfO2, Hr1-xZrxO2, ZrO2, TiO2, NiO, TaOx, Cu2O, Nb2O5, AlOx, and combinations thereof. The memory layers1402and1412may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), MBE, any other suitable process or a combination thereof. A conformal coating may be deposited such that the memory layers1402and1412are continuous on the walls of the second trenches1302in the Z-direction. In some embodiments, a CMP operation may be performed after forming the memory layers1402and1412so that they will lie in the same X-Y plane or are level with a top surface of the topmost insulating layer118. After formation, memory layers1402and1412are sometimes referred to as memory films.

Corresponding to operation434ofFIG.4,FIG.15is a perspective view of the semiconductor device500in which a second set of semiconductor channel layers1502and1512are formed within each of the plurality of second trenches1302on exposed surfaces of the memory layers1402and1412, respectively, such that the semiconductor channel layers1402and1412also continuously extend along the X-direction, in accordance with some embodiments.

The second set of semiconductor channel layers1502and1512are substantially similar to the semiconductor channel layers1102,1112, and1122. In some embodiments, the semiconductor channel layers1502and1512may be formed from a semiconductor material, for example, silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; any other suitable material; or combinations thereof. The semiconductor channel layers1502and1512may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), MBE, any other suitable process, or a combination thereof. A conformal coating may be deposited such that the semiconductor channel layers1502and1512are continuous on the inner surface of the memory layers1402and1412, respectively. In some embodiments, a CMP operation may be performed after forming the semiconductor channel layers1502and1512so that they will lie in the same X-Y plane or are level with a top surface of the topmost insulating layer118.

Corresponding to operation436-440ofFIG.4,FIG.16is a perspective view of the semiconductor device500in which the semiconductor channel layers1502and1512are cut along the X-direction to form a semiconductor channel segments1502A-F and1512A-F, respectively, and insulation layers are formed within each of the plurality of trenches, in accordance with some embodiments.

The semiconductor channel layers1502and1512are patterned by, for example, an anisotropic etching process to form a number of portions. Other methods of patterning the semiconductor channel layers1502and1512are within the scope of the present disclosure. The semiconductor channel layer1502is patterned to form a number of channel segments1502A,1502B,1502C,1502D,1502E, and1502F. The semiconductor channel layer1512is patterned to form a number of channel segments1512A,1512B,1512C,1512D,1512E, and1512F. In various embodiments, each of the channel segments1502A-F and1512A-F may extend along the X-direction with a length (LC), which may be configured to define the physical channel length of a memory cell.

Corresponding to operation438, insulation layers are formed within each of the plurality of trenches by filling each of the plurality of trenches with an insulating material such that a plurality of second device segments that include the memory layers1402and1412, the semiconductor channels1502A-1512F, and the insulation layers are formed in the semiconductor device, and extend in the X-direction parallel to each other. The insulation layers form isolation structures1604and1614as well as inner spacers1610and1620.

Each of the trenches is filled with an insulating material (e.g., SiO2, SiN, SiON, SiCN, SiC, SiOC, SiOCN, any other suitable material, or combinations thereof) so as to form the insulation layer. In some embodiments, the insulation layer may be formed from the same material as the plurality of insulating layers118(e.g., SiO2). The insulation layer may be formed using physical vapor deposition (PVD), chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), MBE, any other suitable process or a combination thereof, a high aspect ratio process (HARP), another applicable process, or combinations thereof. Thus, a plurality of partially-formed memory cells1606that include the memory layers1402and1412, the semiconductor channels1502A-1512F, and the insulation layers are formed in the semiconductor device500and extend in the X-direction parallel to each other.

The cavities filled with the insulation layer in between the partially formed memory cells1606form the isolation structures1604and1614. The isolation structures1604and1614separate the semiconductor channels1502A-1512F into portions such that the semiconductor channels1502A-1512F are included in each partially-formed memory cell1606.

Each partially-formed memory cell1606includes an inner spacer1610or1620formed from a portion of the insulation layer extending between adjacent isolation structures1604or1614in the X-direction. The semiconductor channels1502A-1512F are disposed on outer surfaces of the inner spacers1610or1620in the X-direction. At operation440, a CMP process may then be performed after forming the insulation layer so that it will lie in the same X-Y plane or are level with a top surface of the topmost insulating layer118.

FIG.16also illustrates second device segments1612and1632formed between the first device segments1602,1622, and1642. Each of the second device segments1612and1632is similar in structure to the first device segments1602,1622, and1642and include the memory layers1402and1412, the semiconductor channel layers1502A-1512F, the isolation structures1604and1614, and the inner spacers1610and1620. The second device segments1612and1632extend in the X-direction parallel to each other with the first device segment1622interposed between a pair of second device segments1612and1632. Forming the first and second device segments1602-1642allows adjacent insulating layers118in the stack116to always be supported by either the sacrificial layers524during formation of the WLs902included in the first device segments1602,1622, and1642, or supported by the WLs902of the first device segments1602,1622, and1642during formation of the second device segments1612and1632, while allowing increase in a device packing density of the semiconductor device500.

Corresponding to operation442ofFIG.4,FIG.17is a perspective view of the semiconductor device500in which a number of source lines (SLs)1706,1710,1714,1718,1722,1726,1730,1734,1738,1742,1746,1750,1754,1758, and1762and bit lines (BLs)1708,1712,1716,1720,1724,1728,1732,1736,1740,1744,1748,1752,1756,1760, and1764are formed to form memory cells, in accordance with some embodiments. In some embodiments, a source line or a bit line may sometimes be collectively referred to as a bit/source line. However, it should be understood that, in some embodiments, the source lines and bit lines may be coupled to different levels of (e.g., voltage) signals, when operating the semiconductor device.

The inner spacers1210,1220,1230,1610, and1620may be patterned to define initial footprints of a number of source lines and bit lines. The patterning generates trench portions by first etching through axial ends of the inner spacers1210,1220,1230,1610, and1620to the substrate501. The axial ends of the inner spacers1210,1220,1230,1610, and1620may be etched using a plasma etching process (including radical plasma etching, remote plasma etching, and other suitable plasma etching processes, RIE, DRIE), gas sources such as Cl2, HBr, CF4, CHF3, CH2F2, CH3F, C4F6, BCl3, SF6, H2, NF3, and other suitable etch gas sources and combinations thereof can be used with passivation gases such as N2, O2, CO2, SO2, CO, CH4, SiCl4, and other suitable passivation gases and combinations thereof. Moreover, for the plasma etching process, the gas sources and/or the passivation gases can be diluted with gases such as Ar, He, Ne, and other suitable dilutive gases and combinations thereof. As a non-limiting example, a source power of 10 Watts to 3,000 Watts, a bias power of 0 watts to 3,000 watts, a pressure of 1 millitorr to 5 torr, and an etch gas flow of 0 sccm to 5,000 sccm may be used in the etching process. However, it is noted that source powers, bias powers, pressures, and flow rates outside of these ranges are also contemplated.

Next, the SLs1706-1762and the BLs1708-1764may be formed, for example, using an epitaxial layer growth process to fill the trench portions with a metal material such that the SLs1706-1762and the BLs1708-1764are located on opposite axial ends of the inner spacers1210-1230and1610-1620, each extending from the substrate501to a top surface of the inner spacers1210-1230and1610-1620, as shown inFIG.17. The SLs1706-1762and the BLs1708-1764may be formed in contact with end portions of a sidewall of the semiconductor channels1102A-F,1112A-F,1122A-F,1502A-F, and1512A-F. The metal material can be selected from the group consisting of aluminum, tungsten, tungsten nitride, copper, cobalt, silver, gold, chrome, ruthenium, platinum, titanium, titanium nitride, tantalum, tantalum nitride, nickel, hafnium, and combinations thereof. Other metal materials are within the scope of the present disclosure.

The SLs1706-1762and BLs1708-1764can be formed by overlaying the workpiece (e.g., to fill the recesses) with the above-listed metal material by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), electroless plating, electroplating, or combinations thereof. In some embodiments, a control deposition step may be performed for forming the SLs1706-1762and the BLs1708-1764such that the deposition step is stopped when a height of the SLs1706-1762and the BLs1708-1764in the Z-direction are equal to a height of the stack116. In other embodiments, a CMP operation may be performed after formation of the SLs1706-1762and the BLs1708-1764so as to ensure a top surface of each of the topmost insulating layer118, the memory layers1002,1012,1022,1402, and1412, the semiconductor channels1102A-1122F and1502A-1512F, the inner spacers1210-1230and1610-1620, the SLs1706-1762, and the BLs1708-1764lie in the same X-Y plane or are level with a top surface of the topmost insulating layer118. In other embodiments, a top surface of the SLs1706-1762and the BLs1708-1764may be higher than a top surface of the topmost insulating layer118. In some other embodiments, the top surface of the SLs1706-1762and the BLs1708-1764may be lower than the top surface of the topmost insulating layer118.

Corresponding to operation444ofFIG.4,FIG.18is a perspective view of the semiconductor device500in which a plurality of WL staircase vias1806, a plurality of WL vias1820, and a plurality of metal routings1814are formed, in accordance with some embodiments.

The semiconductor device500is comprised of a device portion704(substantially similar to the device portion302inFIG.3) and one or more interface portion(s)706(substantially similar to the interface portions304inFIG.3). WL staircase vias1806are formed in the interface portions706on exposed portions of the WLs902. The WL staircase vias1806each penetrate through the ILD702with a respective height (or depth) to land on a respective word line. For example inFIG.18, a number of WL staircase vias1806vertically extends with a first height to land on the WLs902at the first step602; a number of WL staircase vias1806vertically extends with a second height to land on the WLs902at the second step604; and a number of WL staircase vias1806vertically extends with a third height to land on the WLs902at the third step606. The WL staircase vias1806are formed by etching the ILD702to form a number of openings that expose various portions of the WLs902at different steps, and then filled out with the openings with a metallic fill material. The metallic fill material includes at least one metal material selected from the group consisting of tungsten, copper, cobalt, ruthenium, titanium, tantalum, any other suitable material, or combinations thereof. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, any other suitable method, or a combination thereof.

Concurrently with or subsequently to forming the WL staircase vias1806, WL vias1820(substantially similar to the WL vias310inFIG.3) are formed in a similar manner to the WL staircase vias. Next, metal routings1814(substantially similar to the metal routings314inFIG.3) are formed to electrically couple the WL staircase vias1806to the WL vias1820. Each of the metal routings1814are formed as a horizontal conductive line, as shown inFIG.18. Similar as the WL staircase vias1806, such metal routings1814and WL vias1820can be formed through a dual-damascene or single-damascene process by forming one or more horizontal and vertical trenches extending through an ILD and filling those trenches with a metallic fill material. The metallic fill material include at least one metal material selected from the group consisting of tungsten, copper, cobalt, ruthenium, titanium, tantalum, any other suitable material, or combinations thereof. The metallic fill material can be deposited by a conformal deposition method, which can be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or a combination thereof.

For the purposes of clarity, only three WL vias1820are depicted, but it should be understood that each WL902can be coupled to a respective group of WL staircase via1806, WL via1820, and metal routing1814, while remaining within the scope of present disclosure.

Upon forming the WL staircase vias1806, metal routings1814, and WL vias1820, each of the WLs902can be electrically coupled to a memory core control circuit1808(substantially similar to the metal core control circuit208ofFIG.2B). As mentioned above, each WL902can function as a gate of each memory cell. Alternatively stated, each WL902can turn on or off a corresponding memory cell. Further, upon being turned on or otherwise accessed (e.g., read), the level of cell current of each memory cell can be modulated based on a voltage level applied to the corresponding WL902. In accordance with various embodiments, the memory core control circuit1808can provide different voltage levels of bias to the WLs902through the respective group of WL staircase via, metal routing, and WL via. For example, the memory core control circuit1808can provide a relatively higher voltage level of (e.g., read) bias to be applied on the WL902that gates a memory cell having a longer channel, and provide a relatively lower voltage level of (e.g., read) bias to be applied on the WL902that gates a memory cell having a shorter channel. Details of different voltage levels applied to memory cells that include respective different channel lengths will be discussed as follows.

FIGS.19A-Bare a top view and a cross-section view of the semiconductor device500cut along a first cross-section (e.g., along X-X inFIG.18), respectively, in accordance with some embodiments.

FIG.19Aillustrates the top view of two memory cells1902and1904, each of which may be comprised of one WL, one SL, one BL, a portion of a semiconductor channel, and a portion of a memory layer.

The memory cell1902is one memory cell from the semiconductor device500and comprises a portion of the WL902A, the SL1706, the bit line1708, a portion of the semiconductor channel1102A, and a portion of the memory layer1002A. The memory cell1904is another memory cell from the semiconductor device500and comprises a portion of the WL902B, the SL1706, the BL1708, a portion of the semiconductor channel1102B, and a portion of the memory layer1002B. A plurality of memory cells arranged along the Z-direction can form a memory string. In some embodiments, the plurality of memory cells in the memory string conduct a current with a constant level. Li is defined as the length of the inner spacer1210in the between the SL1706and the BL1708in the X-direction. It is understood that semiconductor devices are not limited to the number of memory cells shown on semiconductor device500.

FIG.19Bis a cross-section view of the semiconductor device500that illustrates the SL1706and the BL1708and the alternating WLs902and insulating layers118taken across the cross-section X-X along the X-direction inFIG.18. Multiple memory cells such as but not limited to1902and1904can form respective channel lengths of memory cells arranged along a vertical direction (which are sometimes referred to as a memory string).

The dotted lines illustrate that the alternating WLs902and the insulating layers118are in a plane behind the SL1706and the BL1708. For the purposes of clarity, the SL1706, the BL1708, and the WLs902are depicted in the same plane. As shown inFIG.19B, the SL1706and the BL1708extend vertically along the Z-direction. The SL1706and the BL1708are spaced apart from each other along the X-direction. A plurality of WLs902alternating with insulating layers118extend along the X-direction and are disposed across the SL1706and the BL1708. The SL1706and the BL1708may have an increasing varying width along an increasing height in the Z-direction. The varying width of the SL1706and the BL1708result in a varying channel length in the memory string. For example, the topmost channel length is Lx1, and the bottommost channel length is Lx2. In some embodiments, the channel length Lx1may be less than the channel length Lx2. In such embodiments, the channel lengths between the bottommost channel length Lx2and the topmost channel length Lx1decrease in length along an increasing height in the Z-direction.

In such embodiments, the voltage levels of read bias applied to the WLs902, respectively, decrease with an increasing height along the Z-direction, which corresponds to the channel lengths of memory cells gated by those WLs902. For example, a first memory cell, gate by the topmost WL902, has a relatively shorter channel length Lx1. The topmost WL902may be applied with a relatively lower level of bias (hereinafter WL bias “Vtop”) when accessing (e.g., reading) such a first memory cell. A second memory cell, gate by the bottommost WL902, has a relatively longer channel length Lx2. The bottommost WL902may be applied with a relatively higher level of bias (hereinafter WL bias “Vbottom”) when accessing (e.g., reading) such a second memory cell. Further, the voltage levels applied to the WLs902in between the bottommost and topmost WLs902can decrease from Vbottom to Vtop. The varying levels of bias applied on the WLs902are designed to make the cell current increases with an increasing channel length so as to provide a constant cell current throughout the memory cells.

FIGS.20A-Cillustrate plots of WL read bias, cell current, and cell current, respectively, along the vertical axes that correspond to the embodiment of the semiconductor device500shown inFIGS.19A-B. The horizontal axes of19A-B are channel length of the semiconductor device500from the top of the device to the bottom.

In the semiconductor device500, the channel length increases from the top to the bottom.FIG.20Aillustrates that the WL read bias shown on the vertical axis varies in accordance with different channel lengths for this embodiment, in comparison to a constant word line bias applied. From top to bottom, the channel length increases, and the word line bias increases accordingly.FIG.20Bdemonstrates that the varying word line bias results in a constant cell current shown on the vertical axis, in comparison to the degradation of cell current typically observed along longer channel lengths. It is shown inFIG.20Bthat increasing the WL read bias with an increasing channel length results in the desired cell current.FIG.20Cdemonstrates another embodiment in which the varying word line bias can be modified in order to result in an increasing cell current shown on the vertical axis instead of the degradation of cell current typically observed along longer channel lengths.FIG.20Cdemonstrates that modifying the WL read bias of the semiconductor500can result in any desired cell current.

FIG.21is a cross-section view of a semiconductor device600with a SL2106and a BL2108that have varying widths that decrease in a first portion2100A and increase in a second portion2100B with an increasing height along the vertical direction (e.g., the Z-direction), cut along the X-direction, in accordance with some embodiments.

The semiconductor device600is formed from the method400fromFIG.4. The semiconductor device600is substantially similar to the semiconductor device500but with a decreasing varying width of the bit lines and the source lines in a first portion and an increasing varying width of the bit lines and source lines in a second portion along an increasing height of the semiconductor device600along the Z-direction. In contrast, the semiconductor device500has a continuously increasing varying width of the bit lines and the source lines along an increasing height of the semiconductor device500.

The semiconductor device600comprises the SL2106, the BL2108, and a plurality of alternating WLs2102and insulating layers2118which are substantially similar to the SL1706, the BL1708, and the plurality of alternating WLs902and insulating layers118of the semiconductor device500inFIG.19B, respectively. The dotted lines illustrate that the alternating WLs2102and the insulating layers2118are in a plane behind the SL2106and the BL2108. For the purposes of clarity, the SL2106, the BL2108, and the WLs2102are depicted in the same plane. As shown inFIG.21, the width of the SL2106and the BL2108decrease with an increasing height along the first portion2100A. The width of the SL2106and BL2108increase with an increasing height along the second portion2100B. The varying width of the SL2106and the BL2108result in a varying channel length. For example, the topmost channel length is Lx1, the bottommost channel length is Lx2, and the channel length at the point where the first portion2100A meets the second portion2100B is Lx3. In some embodiments, the channel length Lx3is greater than the channel lengths Lx1and Lx2. In some embodiments, the channel length Lx1is equal to the channel length Lx2. In some embodiments, the channel lengths between the bottommost channel length Lx2and the channel length Lx3increase in length in an increasing height along the Z-direction. In some embodiments, the channel length Lx3and the topmost channel length Lx1decrease in length in an increasing height along the Z-direction.

The semiconductor device600further comprises memory layers and semiconductor channels corresponding to SL2106and the BL2108(not shown). The memory layers and the semiconductor channels of the semiconductor device600are substantially similar to the memory layers1002-1022and1402-1412and the semiconductor channels1102A-1122F and1502A-1512F, respectively, in the semiconductor device500.

In some embodiments, the voltage level of bias applied to the WLs2102increases along the first portion2100A and decreases along the second portion2100B with an increasing height in the Z-direction. The voltage level of bias applied to the WLs2102may be positively proportional to the channel length. For example, the topmost WL2102corresponding to the channel length Lx1may have a first level of bias applied. The bottommost WL2102corresponding to the channel length Lx2has may have a second level of bias applied. The WL2102at the point where the first portion2100A meets the second portion2100B (sometimes referred to as a middle one of the plurality of third conductive structures) corresponding to the channel length Lx3may have a third level of bias applied. In some embodiments, the third level of read bias is greater than the first level of bias and second level of bias. In some embodiments, the first level of bias may be equal to the second level of read bias. The varying levels of bias applied to the WLs1502are designed to make cell current increase or remain constant with varying channel lengths. In some embodiments, the plurality of memory cells in a memory string conduct a current with a constant level. It is understood that the semiconductor device600is not limited to the three WLs2102shown inFIG.21, and that the middle one of the plurality of third conductive structures can refer to any WL2102between the topmost WL2102and the bottommost WL2102.

FIGS.22A-Billustrate plots of WL read bias and cell current, respectively, along the vertical axes that correspond to the embodiment of the semiconductor device600shown inFIG.21. The horizontal axes ofFIGS.22A-Bare channel length of the semiconductor device600from the top of the device to the bottom.

In the semiconductor device600, the channel length increases from the bottom along a first portion and decreases along a second portion to the top.FIG.22Aillustrates that the WL read bias shown on the vertical axis directly corresponds to the channel length for this embodiment, in comparison to a constant WL read bias typically applied.FIG.22Bdemonstrates that the varying WL read bias results in a constant cell current shown on the vertical axis, in comparison to the degradation of cell current typically observed along longer channel lengths. It is shown inFIG.22Bthat increasing the WL read bias with an increasing channel length results in the desired cell current.

FIG.23is a cross-section view of a semiconductor device700with a SL2306and a BL2308that have varying widths that increases in a first portion2300A and decreases in a second portion2300B with an increasing height along the vertical direction (e.g., the Z-direction), cut along the X-direction, in accordance with some embodiments.

The semiconductor device700is formed from the method400fromFIG.4. The semiconductor device700is substantially similar to the semiconductor device500but with an increasing varying width of the bit lines and the source lines in a first portion and a decreasing varying width of the bit lines and source lines in a second portion along an increasing height of the semiconductor device700along the Z-direction. In contrast, the semiconductor device500has a continuously increasing varying width of the bit lines and the source lines along an increasing height of the semiconductor device500.

The semiconductor device700comprises the SL2306, the BL2308, and a plurality of alternating WLs2302and insulating layers2318which are substantially similar to the SL1706, the BL1708, and the plurality of alternating WLs902and insulating layers118of the semiconductor device500inFIG.19B, respectively. The dotted lines illustrate that the alternating WLs2302and the insulating layers2318are in a plane behind the SL2306and the BL2308. For the purposes of clarity, the SL2306, the BL2308, and the WLs2302are depicted in the same plane. As shown inFIG.23, the width of the SL2306and the BL2308increase with an increasing height along the first portion2300A. The width of the SL2306and BL2308decrease with an increasing height along the second portion2300B. The varying width of the SL2306and the BL2308result in a varying channel length. For example, the topmost channel length is Lx1, the bottommost channel length is Lx2, and the channel length at the point where the first portion2300A meets the second portion2300B is Lx3. In some embodiments, the channel length Lx3is less than the channel lengths Lx1and Lx2. In some embodiments, the channel length Lx1is equal to the channel length Lx2. In some embodiments, the channel lengths between the bottommost channel length Lx2and the channel length Lx3decrease in length in an increasing height along the Z-direction. In some embodiments, the channel length Lx3and the topmost channel length Lx1increase in length in an increasing height along the Z-direction.

The semiconductor device700further comprises memory layers and semiconductor channels corresponding to SL2306and the BL2308(not shown). The memory layers and the semiconductor channels of the semiconductor device700are substantially similar to the memory layers1002-1022and1402-1412and the semiconductor channels1102A-1122F and1502A-1512F, respectively, in the semiconductor device500.

In some embodiments, the voltage level of read bias applied to the WLs2302decreases along the first portion2300A and decreases along the second portion2300B with an increasing height in the Z-direction. The voltage level of read bias applied to the WLs2302may be proportional to the channel length. For example, the topmost WL2302corresponding to the channel length Lx1may have a first level of read bias applied. The bottommost WL2302corresponding to the channel length Lx2has may have a second level of read bias applied. The WL2302at the point where the first portion2300A meets the second portion2300B (sometimes referred to as a middle one of the plurality of third conductive structures) corresponding to the channel length Lx3may have a third level of read bias applied. In some embodiments, the third level of read bias applied may be less than the first and second level of read biases. In some embodiments, the first level of read bias is equal to the second level of read bias. The varying read biases of the WL2302are designed to make cell current increase or remain constant with varying channel lengths. In some embodiments, the plurality of memory cells in a memory string conduct a current with a constant level. It is understood that the semiconductor device700is not limited to the three WL2302shown inFIG.23, and that the middle one of the plurality of third conductive structures can refer to any WL2302between the topmost WL2302and the bottommost WL2302.

FIGS.24A-Billustrate plots of WL read bias and cell current, respectively, along the vertical axes that correspond to the embodiment of the semiconductor device700shown inFIG.23. The horizontal axes ofFIGS.24A-Bare channel length of the semiconductor device700from the top of the device to the bottom.

In the semiconductor device700, the channel length decreases from the bottom along a first portion and increases along a second portion to the top.FIG.24Aillustrates that the WL read bias shown on the vertical axis directly corresponds to the channel length for this embodiment, in comparison to a constant WL read bias applied.FIG.24Bdemonstrates that the WL read bias results in a constant cell current shown on the vertical axis, in comparison to the degradation of cell current typically observed along longer channel lengths. In is shown inFIG.24Bthat increasing the WL read bias with an increasing channel length results in the desired cell current.

FIGS.25A-27Billustrate various plots of varying the levels of word line bias to correspond to channel length and the effect on cell current. Therefore, the present invention is not limited to the embodiments discussed above.FIGS.25A,26A, and27Aare plots of word line bias as a result of channel length.FIGS.25B,26B, and27Bare plots of the cell current as versus channel length as a result of varying WL read bias that correspond toFIGS.25A,26A, and27A, respectively.

InFIGS.25A-B, the WL read bias is constant along a first portion of a semiconductor device from the topmost word line to a middle word line and increases linearly with two different slopes along a second portion of the semiconductor device from the middle word line to a bottommost word line.FIG.25Bshows the resulting cell current along the vertical axis of the semiconductor device. When the WL read bias is constant along an increasing channel length, the cell current decreases. When an increasing WL read bias is added along increasing channel lengths, the cell current will increase. When a larger amount of WL read bias is added along channel lengths, the cell current is constant.

InFIGS.26A-B, the WL read bias increases along a first portion of a semiconductor device from the topmost word line to a middle word line, decreases, and then remains constant until the bottommost word line as shown inFIG.26A.FIG.26Bshows the resulting cell current along the vertical axis. As WL read bias increases along an increasing channel length, the cell current stays constant. When a constant WL read bias is present, the cell current decreases.

InFIGS.27A-B, the WL read bias stays constant along a first portion of a semiconductor device from the topmost word line to a middle word line, increases, and then decrease until the bottommost word line as shown inFIG.27A.FIG.27Bshows the resulting cell current along the vertical axis. When the WL read bias remains constant along an increasing channel length, the cell current will degrade. An increasing WL read bias results in a constant cell current along the semiconductor device.

FIGS.25A-27Bfurther demonstrate that modifying the word line bias to correspond to the channel length compensates for the loss of cell current typically seen in semiconductor devices. Furthermore, the word line bias does not need to increase or decrease continuously throughout the semiconductor device and can be modified according to the desired outcome. In a semiconductor device that has an increasing channel length from the topmost word line to the bottommost word line, cell current would typically degrade from the topmost word line to the bottommost word line.FIGS.25A-27Bdemonstrate that a constant WL read bias leads to a decreasing cell current, an increasing WL read bias leads to an increasing or constant cell current, and a decreasing WL read bias leads to a decreasing cell current.

In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.

In another aspect of the present disclosure, a memory device is disclosed. The memory device comprises a controller and a memory array operatively coupled to the controller. The memory array comprises a first bit/source line extending along a vertical direction, a second bit/source line extending along the vertical direction, and a plurality of first word lines each extending along a first lateral direction. The memory array further comprises a first memory film extending along the vertical direction. The first memory film is in contact with the plurality of first word lines. The memory array further comprises a first semiconductor channel extending along the vertical direction. The first semiconductor channel is in contact with the first and second bit/source lines and with the first memory film on respective sides. The first and second bit/source lines each have a width extending along the first lateral direction, and the width increases in accordance with an increasing height of the first and second bit/source lines. The controller is configured to provide respective different voltages to the plurality of first word lines. The different voltages decrease from a bottommost one of the plurality of first word lines to a topmost one of the plurality of first word lines.

In yet another aspect of the present disclosure, a method for operating a memory device is disclosed. The method comprises providing a plurality of memory cells vertically arranged on top of one another. The plurality of memory cells share a vertically extending bit line and a vertically extending source line but are gated by a plurality of word lines, respectively. The bit line and the source line are separated from each other along a lateral direction. The plurality of word lines each extend along the lateral direction. The method further comprises adjusting voltages applied to the plurality of word lines in accordance with a varying width of each of the bit line source line. The varying width extends along the lateral direction.