Method and apparatus for power domain isolation during power down

An apparatus and method for isolating circuitry from one power domain from that of another power domain prior to performing a power down operation is disclosed. In one embodiment, circuitry in a first power domain is coupled to receive signals based on outputs from circuitry in a second power domain. The signals may be conveyed to the circuitry in the first power domain via passgate circuits. When powering down the circuitry of the first and second power domains, a control circuit may first deactivate the passgate circuits in order to isolate the circuitry of the first power domain from that of the second power domain. The circuitry in the second power domain may be powered off subsequent to deactivating the passgate circuits. The circuitry in the first power domain may be powered off subsequent to powering off the circuitry in the second power domain.

BACKGROUND

1. Field of the Invention

This invention relates to electronic circuits, and more particularly, to circuitry for isolating power domains from one another during power down operations.

2. Description of the Related Art

In many modern integrated circuits (ICs), the circuitry of different functional units may be implemented within different power domains. The reasons for implementing circuits in different power domains may vary. For example, some functional units may have different operating voltage requirement than others. Accordingly, circuits with different operating voltage requirements with respect to other circuits may be implemented in separate power domains.

Another reason for implementing different circuits in different power domains may be due to power saving requirements. While the circuitry of two different functional units may operate at the same supply voltage, the arrangement of an IC on which they are both implemented may require that one be capable of being powered down while the power is still applied to the other.

Although an IC may implement various functional units in different power domains, many of these functional units may be interfaced with others in other power domains. When functional units of two different power domains are both receiving power, communications between them may occur. Communications between the two functional units may be inhibited when one or both are powered down.

SUMMARY

An apparatus and method for isolating circuitry from one power domain from that of another power domain prior to performing a power down or a power up operation is disclosed. In one embodiment, circuitry in a first power domain is coupled to receive signals based on outputs from circuitry in a second power domain. The signals may be conveyed to the circuitry in the first power domain via passgate circuits. When powering down (i.e. removing power from) or powering up (i.e. applying power to) the circuitry of the first and second power domains, a control circuit may first deactivate the passgate circuits in order to isolate the circuitry of the first power domain from that of the second power domain. During a power down operation, the circuitry in the second power domain may be powered off subsequent to deactivating the passgate circuits. The circuitry in the first power domain may be powered off subsequent to powering off the circuitry in the second power domain. During a power up operation, the circuitry in the first power domain may be powered up prior to powering up the circuitry in the second domain. The control circuitry may deactivate the passgate circuits prior to powering up the circuitry in the first power domain, and may allow the passgates to be activated subsequent to powering up the second power domain,

In one embodiment, a processor core is implemented in first power domain of an integrated circuit (IC) and a memory is implemented in a second power domain of the IC. In one embodiment, the memory may be a static random access memory (SRAM) used as a cache memory. The memory may be coupled to provide signals to respective gate terminals of one or more n-channel metal oxide semiconductor (NMOS) transistors coupled to global bit lines in the first power domain. Passgate circuits may be implemented on the global bit lines, between the NMOS transistors and dynamic-to-static converter circuitry. During normal operations, reads of the SRAM may cause signals to be provided to the respective gate terminals of the NMOS transistors, which may in turn cause corresponding signals to be conveyed on the global bit lines to the dynamic-to-static converter circuitry. Prior to an operation where the second power domain (or both power domains) are to have circuitry therein powered down, a control circuit may deactivate the passgates, thereby isolating the portion of each global bit line coupled between its respective NMOS device and the passgate circuit. This may in turn effectively isolate the SRAM from the dynamic-to-static converter circuitry, and prevent indeterminate or erroneous data from being conveyed to the ends of global bit lines coupled to a functional unit (e.g., a processor core) coupled to the static outputs of the dynamic-to-static converter circuitry. After the deactivation of the passgates, the circuitry of the second power domain, including the SRAM may be powered down. The circuitry of the first power domain may be powered down subsequent to the powering down of the circuitry of the second power domains.

In one embodiment, a method includes determining that the circuitry one or more power domains are to be powered down, including a first power domain coupled to receive signals from circuitry in a second power domain. In an operation in which the circuitry of at least the second power domain is to be powered down, isolation signals may be generated to deactivate one or more gating circuits each implemented as part of a corresponding signal line. The gating circuits, when active, are operable to convey signals corresponding to those provided from the circuitry of the second power domain to circuitry in the first power domain. When the gating circuits are disabled, the circuitry of the first power domain is effectively isolated from receiving signals corresponding to those provided by the circuitry of the first power domain. Subsequent to disabling the gating circuits, the circuitry of the second power domain may be powered down.

Isolating the circuitry of the second power domain from that of the first power domain may prevent indeterminate data from being conveyed on the signal lines. Such isolation may also prevent power contention issues between circuitry configured to drive the signal lines based on signals received from circuitry in the second power domain and dynamic-to-static circuitry in the first power domain.

DETAILED DESCRIPTION OF EMBODIMENTS

Exemplary IC and Exemplary Interface Between Power Domains

Turning now toFIG. 1, a block diagram of one embodiment of an integrated circuit (IC) is illustrated. In the embodiment shown, IC10includes functional unit102in power domain #1and functional unit104in power domain #2. Additional functional units may be present, as well as additional circuitry not explicitly shown here, including within power domains #1and #2. Functional units102and104may be implemented using various types of circuitry that provide certain functionality. For example, in one embodiment, functional unit102may be a processor core, while functional unit104may be a cache memory implemented using static random access memory (SRAM).

In the embodiment shown, functional unit104may communicate with functional unit102via bus107, which may include a number of signal lines configured to convey information from the former to the latter. Gating circuitry105in the embodiment shown may effectively bisect bus107into separate segments. As will be explained below, gating circuitry105may include a number of passgates or similar circuits that, when enabled, may be transparent to signals on the individual signal lines of bus107. During operation of IC10when the circuitry of both power domains #1and #2are receiving power, the passgates of gating circuitry105may be enabled.

IC10includes power management unit108in the illustrated embodiment, which may be implemented in either one of power domains #1or #2, or may be implemented in another power domain altogether. Power management unit108may implement functionality to control whether circuitry of the various power domains is powered up (i.e. receiving power) or powered down (i.e. not receiving power). Such control may be useful to reduce the overall power consumption of IC10by powering down circuitry that is idle. In the embodiment shown, power management unit108is coupled to both functional unit102and functional unit104, and thus may apply or remove power to these units based on a power management scheme. Furthermore, power management unit108may remove or apply power to functional units102and104independently of one another.

IC10also includes an isolation unit110. In the embodiment shown, isolation unit110is coupled to receive a signal ‘PwrDn’ indicating that power management unit108is going to power down one or both of functional units102and104. Responsive to receiving the indication from power management unit108, isolation unit110may assert one or more isolation signals (‘Isolate’) that may be received by gating circuitry105. Responsive to receiving these signals, the individual gating circuits of gating circuitry105may be disabled, effectively creating on open circuit on bus107and thereby preventing communications between functional units102and104. Subsequent to disabling the gating circuits, power management unit108may power down one or both of the functional units102and104. Isolation unit110is also coupled to receive a signal ‘PwrUp’ indicating that power management unit108is to power up at least functional unit102(irrespective of whether functional unit104is powered up at that time). Isolation unit110may assert the isolation signals during the powering up of functional102such that it remains isolated from, and therefore unaffected by, functional unit104at least until the operation is complete and functional unit102is fully initialized and operating. Subsequent thereto, the isolation signals may be de-asserted.

Although not explicitly shown here, some embodiments of isolation unit110may be configured to assert an acknowledgement signal that is returned to power management unit108in order to indicate that the gating circuits have been disabled. In such embodiments, power management unit108may delay the powering down of either of the functional units until the acknowledgement signal has been received. In other embodiments, power management unit108may be configured to allow a certain amount of time to elapse before powering down any functional units, and thus an acknowledgement signal may not be implemented.

The isolation function provided by isolation unit110may be useful in preventing erroneous communications or contention issues in powering down circuitry in the different power domains. In some embodiments of IC10, some functional units may be capable of powering down faster than functional units of an adjacent power domain to which they are coupled to communicate. Using the example noted above, functional unit104, when implemented as an SRAM, may be capable of powering down faster than functional unit102, when implemented as a processor core. If functional unit104is powered down before functional unit102, the respective states of signal lines on bus107may be affected by indeterminate data received from functional unit104, potentially causing the issues noted above if gating circuitry105remains enabled.

Without the isolation function, the functional unit that is first to be powered down may cause indeterminate states and/or signal contention issues on the signal lines of bus107. This in turn may cause erroneous operation of any functional unit that is coupled to receive signals via these signal lines and remains powered on. By disabling the individual gating circuits of gating circuitry105, these issues may be prevented since the functional units connected by the signal lines of bus107may be electrically isolated from each other. Accordingly, if a functional unit of one power domain is quicker to power down than that of another power domain to which it is coupled, the issues noted above may be avoided.

FIG. 2is a schematic diagram of one embodiment of an interface between a memory in one power domain and a dynamic-to-static converter circuit in another power domain. Circuit20in the embodiment shown includes circuitry in a first power domain and a second power domain. The circuit may be divided into a number of bit slices. The dynamic-to-static converter circuit21illustrated in detail in the embodiment shown is applicable to one of a number of the bit slices, and may be coupled to provide an output signal to a processor core that is not shown here for the sake of simplicity. The processor core may correspond to at least a part of functional unit102as shown inFIG. 1.

It is noted that transistors designated with a ‘P’ in the illustrated example are p-channel metal oxide semiconductor (PMOS) devices, while transistors designated with an ‘N’ are n-channel metal oxide semiconductor (NMOS) devices. It is noted that the arrangement of the devices in the illustrated embodiment are exemplarily, and that other arrangements using other types of devices may fall within the scope of this disclosure.

In the embodiment shown, circuit20may be one of a number of possible specific implementations of the generalized embodiment illustrated inFIG. 1. In this particular example, circuitry in a central processing unit (CPU) power domain is coupled to receive signals from SRAM204in an SRAM power domain. Circuitry in the CPU power domain is arranged to receive the supply voltage VddCPU, while SRAM204(as well as other any other circuitry that may be implemented in the SRAM power domain) is coupled to receive the supply voltage VddSRAM. These two supply voltages may be different from one another in the embodiment shown, although embodiments where these voltages are substantially the same are possible and contemplated. Although not explicitly shown in this example, a power management unit108may be coupled to provide or inhibit the supply voltages VddCPU and VddSRAM to the circuitry in their respective power domains.

SRAM204in the embodiment shown may be configured to provide signals to a number of input circuits, the number of input circuits including transistors N9and N10in this particular example. For the sake of simplicity, only these two devices are shown inFIG. 2, although it is understood that a larger number of devices may be present in accordance with the width of the data path of a read port in SRAM204. For example, if the width of the data path is 32 bits, than 32 input circuits may be implemented, along with the same number of instances of the other circuits shown.

Transistors N9and N10in the embodiment shown may serve as inputs to dynamic circuitry of respective dynamic-to-static converter circuits21. One instance of a dynamic-to-static converter circuit21is shown in detail inFIG. 2. Each dynamic-to-static converter circuit21may be coupled to one of two possible global bit lines through passgate circuitry implemented in gating circuitry105. For example, the instance of dynamic-to-static converter circuit21illustrated in detail (i.e. associated with Gbl—0_end may be coupled to transistor N10is passgate transistor N8is active, or to transistor N9if passgate transistor N7is active).

It is noted that additional input circuits (not shown here for the sake of simplicity) may also be coupled to each global bit line. For example, in addition to N10, a number of additional NMOS devices may also be coupled to GBL—0. Each of these additional devices may have a respective gate terminal coupled to a corresponding bit line of SRAM204. Furthermore, the devices may be arranged in a one-hot multiplexer configuration, wherein a maximum of one of the devices coupled to a given global bit line may be active at a given time.

The particular arrangement shown inFIG. 2provides a redundancy multiplexer, and thus SRAM204may be implemented as a redundant memory array that may provide protection against failure of specific memory cells or groups thereof Thus, only one of passgate transistors N7or N8may be active at any given time during normal operation. The determination of which of these devices is active during normal operation may be made according to a binary repair value (determined during a manufacturing test) received by redundancy decoder208. Based on the received binary repair value, redundancy decoder may assert active low signals (i.e. considered asserted when low in this embodiment) such as ‘Redundant—0’, ‘Redundant—1’, and so forth. When one of these signals is active low, a corresponding redundant passgate circuit is enabled, while the normal passgate is disabled. For example, if ‘Redundant—0’ is low, the output of inverter I9is high, thereby causing the activation of redundant passgate N7. The high output of inverter I9is also received by NOR gate G4, causing it to provide a low output to the gate of passgate G8, which in turn causes this device to be inactive. An active low on ‘Redundant—1’ may have a similar effect by causing the enabling of N5via the output of I8and the disabling of N6via the output of G3.

When a given redundancy signal is high, a corresponding normal passgate may be enabled while the respective redundant passgate is disabled. For example, if ‘Redundant—0’ is high, the output of inverter I9is low and thus redundant passgate N7is disabled. If the output of inverter I6is also low (which may occur when the ‘Isolate’ signal is low), NOR gate G4outputs a high and may thus activate passgate N8.

It is noted that the active one of a given pair of passgate devices (e.g., N8and redundant passgate N7) may change during normal operation. For example, responsive to SRAM204receiving a first address, passgate N8may be active while passgate N7is inactive. Responsive to SRAM204receiving a second address, passgate N8may be inactive while passgate N7is active. The active one of these two passgates may be determined by the address received by SRAM204and the binary repair value. However, only one passgate device of a given pair may be active for a particular address.

Operation of the dynamic-to-static converter circuit21in the embodiment shown may be divided into a precharge phase and an evaluation phase. During operation in the precharge phase, the signal ‘Precharge_L’ may be held low. This signal may be propagated through inverters I4and I3, the latter of which may output a low to activate precharge device P2. When P2is active, the global bit line ‘GBL—0_end’ may be pulled high. Global bit line ‘GBL—0’ may also be pulled high through passgate N8to a voltage that is approximately a threshold voltage (i.e. the threshold voltage of N8) below the value to which ‘GBL—0_end’ is pulled (assuming P4is inactive).

Transistor P4in the embodiment shown provides a secondary precharge transistor coupled to precharge ‘GBL—0’. When the output of inverter I7(‘Isolate_L’) is high, and the secondary precharge is enable (when ‘S_pchg_en’ is high), both inputs to NAND gate G1are low. Accordingly, the output of inverter I5is correspondingly high at this time. When the ‘Precharge_L’ is low, the output of inverter I4(‘Precharge_H’) is high, and thus both inputs to NAND gate G2are high. Responsive to the two high inputs, NAND gate G2outputs a low to the gate terminal of P4, thereby activating this device and thus causing a precharge of ‘GBL—0’ independent of the precharge of ‘GBL—0_end’. However, it is noted that the secondary precharge circuitry is not required for all embodiments. Furthermore, the secondary precharge circuitry may be disabled for at least some of the time in some embodiments in which it is included.

The ‘Precharge_L’ signal that initiates the precharge phase may be derived from a clock signal in one embodiment. Thus, when the clock signal is low, the ‘Precharge_L’ may correspondingly be low, causing the precharge operation to take place. When the clock signal is high, the ‘Precharge_L’ signal may correspondingly be high, and thus the precharge devices may be inhibited at this time. In other embodiments, the ‘Precharge_L’ signal may be generated independently of a clock signal.

When the precharge operation is complete, circuit20may operate in an evaluation phase. During the evaluation phase, a precharged global bit line may remain high if none of the input devices to which it is coupled (e.g., N10, coupled to ‘GBL—0’) is activated. If one of the input devices coupled to a given global bit line is activated, the global bit line (e.g., ‘GBL—0’) may be pulled low during the evaluation phase, and this low may be propagated to its corresponding portion of the global bit line (e.g., ‘GBL—0_end’) on the other side of the respective passgate device (e.g., N8).

During the evaluation phase, the precharge signal, ‘Precharge_L’, may be high. Accordingly, the output of inverter I3, which is coupled to respective gate terminals of transistors N1and N3, is also high. Accordingly, transistors N1and N3are active during the evaluation phase. Transistor N3is a component of a gated keeper circuit that also includes inverter I10and transistors P3and N4. When N3is active, the gated keeper circuit may hold ‘GBL—0_end’ low if it evaluates low during the evaluation phase, via the pull-down path through N3and N4. Otherwise, ‘GBL_0_end’ may be held high through transistor P3, which may be activated due to the low output from I10resulting from a high on ‘GBL—0_end’. During the precharge phase, transistor N3may be inactive, thereby blocking the pull-down path between ‘GBL—0_end’ and ground.

Transistor N1in the embodiment shown is one component of a gated inverter circuit that also includes transistors P1and N2. When ‘GBL—0_end’ evaluates low during the evaluation phase, transistor P1may be activated and may thus pull node ‘Keeper—0’ high. When ‘GBL—0_end’ evaluates high during the evaluation phase, transistor N2is activated, and thus ‘Keeper—0’ may be pulled low through N1and N2. During the precharge phase, N1is inactive due to the low output from13, while P1is inactive due to ‘GBL_0_end’ being precharged high. Accordingly, the gated inverter blocks signal propagation during the precharge phase. A static keeper including inverters I1and I2may hold, during the precharge phase, the most recently driven value on ‘Keeper—0’ (i.e. the value driven thereon during the evaluation phase preceding the precharge phase). Since ‘Keeper—0’ is not subject to a precharge in the illustrated embodiment, it is a static node. It is also noted that the logic value driven on ‘Keeper—0’ during the evaluation phase may be the logical equivalent of the value output by SRAM204to the gate terminals of the input devices (e.g., N9, N10) in this embodiment.

As noted above, for each end global bit line (e.g., ‘GBL—0_end’), at least one passgate device coupled thereto may be active during normal operation. However, if the SRAM domain is to be powered down, or both power domains are to be powered down, each active passgate device may be turned off without turning on any of the previously inactive passgates. When each passgate device is inactive, SRAM204is electrically isolated from the corresponding dynamic-to-static converter circuits21in the CPU power domain. This isolation may be performed in order to prevent signals conveyed from SRAM204from affecting other circuitry coupled to the dynamic-to-static converter circuits21, as SRAM204may be capable of powering down quicker than circuitry in the CPU power domain.

In the embodiment shown, circuit20includes isolation unit110, which is coupled to receive the ‘Isolate’ signal from a power management unit (e.g., power management unit108ofFIG. 1). In this particular embodiment, isolation unit110includes inverters I6and I7, as well as various signal connections. The output of inverter I6may be provided to an input of each NOR gate associated with a given bit slice (e.g., to G3, G4, as well as NOR gates associated with other bit slices not explicitly shown). Inverter I6may produce a high on its output responsive to the power management unit asserting the ‘Isolate’ signal high. The high output from inverter I6may be received by NOR gates G3and G4, which may respond by outputting a low to passgate devices N6and N8, respectively. Responsive to the low on their respective gate terminals, N6and N8may be held inactive, thereby isolating ‘GBL—1’ from ‘GBL—1_end’ and ‘GBL—0’ from ‘GBL—0_end’, respectively.

The isolate signal may also be received by redundancy decoder208. As noted above, redundancy decoder208may provide active low signals corresponding to redundancy passgates that are to be activated, based on a received binary repair value. However, responsive to receiving the ‘Isolate’ signal, redundancy decoder may drive or hold each of its respectively provided output signals high. Accordingly, any previously active redundant passgates may be deactivated, while inactive redundant passgates may be held inactive. For example, if passgate N7is active prior to redundancy decoder208receiving the ‘Isolate’ signal, the low-to-high transition of ‘Redundant—0’ may cause inverter I9to output a low. Passgate N7may thus be deactivated responsive to receiving the low. Furthermore, if passgate N5was inactive prior to redundancy decoder208receiving the ‘isolate’ signal, it may remain inactive responsive to the continued high output of ‘Redundant—1’.

As noted above in the discussion related toFIG. 1, the power management unit may assert the ‘Isolate’ signal prior to powering down the SRAM power domain. Once sufficient time has elapsed for the passgates to be deactivated, SRAM204and any other circuitry in the SRAM power domain may be powered down. Powering down of the CPU power domain may subsequent to powering down of SRAM204and other circuitry that may be in the SRAM power domain.

Assertion of the ‘Isolate’ signal may also disable the secondary precharge circuit in embodiments that are so configured. In the embodiment shown, the output of inverter I7may provide an active low ‘Isolate_L’ signal responsive to assertion of the ‘Isolate’ signal. When ‘Isolate_L’ is low, the output of NAND gate G1is high, even if ‘S_pchg_en’ is asserted high. Accordingly, the high output by G1is inverted into a low by inverter I5, which in turn results in NAND gate G2outputting a high to the gate terminal of secondary precharge transistor P4. Accordingly, assertion of the ‘Isolate’ signal may inhibit a precharge operation from occurring to the portions of the global bit lines coupled thereto, regardless of any precharge that may be performed in the dynamic-to-static converter circuits21.

Method Embodiment

FIG. 3is a flow diagram of one embodiment of a method for powering down power domains of an IC. The method may be applied to the embodiments discussed above in reference toFIGS. 1 and 2, as well as to other embodiments not explicitly shown or discussed here.

Method300begins with the determination that various power domains of an IC are to be powered down (block305). In on example, the determination may be made a power management unit in order to conserve power in an IC where circuitry of various power domains is idle. Another example may include powering down circuitry of various power domains due to thermal considerations such as exceeding a specified temperature threshold.

Subsequent to making the power down determination, the power management unit may assert one or more isolation signals (block310). The isolation signals may be provided to a control unit coupled to circuitry used in interfacing circuits of one power domain to those of another power domain. Responsive to receiving an isolation signal, a control circuit may disable one or more gating circuits (block315). The gating circuits may enable communication between circuits in different power domains when active. Disabling the gating circuits may isolate the circuits of the different power domains from one another, thereby ensuring that erroneous or indeterminate data is not inadvertently provided to one of the circuits.

Subsequent to disabling the gating circuits, circuitry from an isolated one of the power domains may be powered down (block320). The power domain for which circuitry is powered down may be one the circuitry may power down quicker than other circuits of another power domain to which it is coupled. Using the example ofFIG. 2, SRAM204may be capable of powering down faster than circuits in the CPU power domain. Thus, when powered down in accordance with method300, the circuitry in the SRAM power domain, including SRAM204, may be powered down prior to circuitry in the CPU power domain.

After powering down the circuitry of one of the power domains as discussed in the previous paragraph, circuitry of another power domain to which it is coupled may be powered down (block325). In some embodiments, circuitry in additional power domains may also be powered down.

It is noted that a similar method may be performed for performing a power up of circuitry in different power domains. For example, power management unit108ofFIG. 1may assert the PwrUp signal to isolation unit110prior to powering up functional unit102(regardless of whether functional unit104is powered up or down at the time). Isolation unit110may then assert the isolation signals in order to isolate functional unit102from functional104at least until the power up operation is complete.

Exemplary System

Turning next toFIG. 4, a block diagram of one embodiment of a system150is shown. In the illustrated embodiment, the system150includes at least one instance of an IC10(e.g., fromFIG. 1) coupled to one or more peripherals154and an external memory158. A power supply156is also provided which supplies the supply voltages to the IC10as well as one or more supply voltages to the memory158and/or the peripherals154. In some embodiments, more than one instance of the IC10may be included (and more than one external memory158may be included as well).

The peripherals154may include any desired circuitry, depending on the type of system150. For example, in one embodiment, the system150may be a mobile device (e.g. personal digital assistant (PDA), smart phone, etc.) and the peripherals154may include devices for various types of wireless communication, such as wifi, Bluetooth, cellular, global positioning system, etc. The peripherals154may also include additional storage, including RAM storage, solid state storage, or disk storage. The peripherals154may include user interface devices such as a display screen, including touch display screens or multitouch display screens, keyboard or other input devices, microphones, speakers, etc. In other embodiments, the system150may be any type of computing system (e.g. desktop personal computer, laptop, workstation, net top etc.).

The external memory158may include any type of memory. For example, the external memory158may be SRAM, dynamic RAM (DRAM) such as synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, RAMBUS DRAM, etc. The external memory158may include one or more memory modules to which the memory devices are mounted, such as single inline memory modules (SIMMs), dual inline memory modules (DIMM5), etc.