Semiconductor device having a first circuit block isolating a plurality of circuit blocks

A semiconductor device, includes: a semiconductor layer, arranged, via an insulation layer, on a region of a part of a semiconductor substrate; a first circuit block formed on the semiconductor layer; and a second and a third circuit blocks formed on the semiconductor substrate, isolated from each other by the first circuit block.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device, particularly to the ones in which bulk structures and silicon-on-insulator (hereafter “SOI”) structures are combined on the same substrate.

2. Related Art

Field-effect transistors formed on SOI substrates have been attracting attention, due to their high level of usability such as easiness in device isolation, latch-up free characteristics, and a small source/drain junction capacitance. Particularly, researches for achieving the operation of the SOI transistors in a fully depleted mode have been very active, since fully depleted SOI transistors allow rapid operations with low-power consumption, and can be driven with low-voltage. A method of forming the SOI transistors at a low cost, by forming SOI layers on bulk substrates, is disclosed as an example of related art. In the method disclosed in the example of related art, Si/SiGe layer is deposited on an Si substrate, and thereafter, a hollow portion is formed between the Si substrate and the Si layer, by selectively removing only the SiGe layer, using the difference in etching rate between Si and SiGe. Subsequently, by performing thermo oxidation of Si that is exposed inside the hollow portion, SiO2layer is buried between the Si substrate and the Si layer, thereby forming a BOX layer between the Si substrate and the Si layer.

T. Sakai et al. “Separation by BondingSi Islans (SBSI) for LSI Application”, Second International SiGe Technology and Device Meeting, Metting Abstract, pp. 230-231, May 2004, is the above-referenced example of related art.

However, in the case of combining the bulk structure and the SOI structure on the same substrate, an interference caused by the substrate noise may occur between the circuit blocks, depending on the arrangement thereof, resulting in a problem that the reliability declines in the semiconductor device. On the other hand, if the sufficient distance is provided between the adjacent circuit blocks, so as to reduce the interference caused by the noise between the circuit blocks, then the chip size increases, resulting in a problem of causing an increase in packaging area and cost.

SUMMARY

An advantage of the invention is to provide a semiconductor device combining a bulk structure with an SOI structure on the same substrate, while suppressing the interference caused by the noise between circuit blocks.

According to a first aspect of the invention, a semiconductor device includes: a semiconductor layer, arranged, via an insulation layer, on a region of a part of a semiconductor substrate; a first circuit block formed on the semiconductor layer; and a second and a third circuit blocks formed on the semiconductor substrate, isolated from each other by the first circuit block.

Consequently, a plurality of circuit blocks having the bulk structures can be combined on the same semiconductor substrate, isolated from each other by the SOI structure that has a high tolerance against crosstalk noises. This allows a decreasing of the distances between the adjacent circuit blocks, while suppressing the crosstalk noise between the circuit blocks, thereby suppressing the increase in the chip size, allowing to mount various functional components onto a single chip, while improving the characteristics and reliability of semiconductor devices.

It is desirable, in the semiconductor device according to the first aspect of the invention, that the first circuit block be arranged between the second circuit block and the third circuit block.

Consequently, a plurality of circuit blocks having the bulk structures can be combined on the same semiconductor substrate, isolated from each other by the SOI structure, thereby allowing a suppressing of the increase in the chip size, while also suppressing the crosstalk noise between the circuit blocks. Moreover, the periphery of the first circuit block can be surrounded by the semiconductor substrate, improving the heat dissipation from the first circuit block, and thereby improving the temperature characteristic of the first circuit block.

It is desirable, in the semiconductor device according to the first aspect of the invention, that either the second or the third circuit block be arranged to contact at least one side of the first circuit block.

Consequently, a plurality of circuit blocks having the bulk structures can be arranged to be isolated from each other by the SOI structure, even in the case of combining the bulk structure and the SOI structure on the same semiconductor substrate, thereby allowing a suppressing of the increase in the chip size, while also suppressing the crosstalk noise between the circuit blocks.

It is desirable, in the semiconductor device according to the first aspect of the invention, that the semiconductor substrate have a resistivity of more than 500 Ωcm.

It is desirable, in the semiconductor device according to the first aspect of the invention, that the first circuit block be a digital circuit, and the second circuit block and the third circuit block be analog circuits.

Consequently, the digital circuit and the analog circuits can be combined on the same substrate, while forming the digital circuit in the SOI structure, and the analog circuits in the bulk structure. At the same time, noises emitted outward from the digital circuit can be blocked by the SOI structure, while enhancing the latch-up resistance. This suppresses the increase in chip sizes, allowing the digital circuit to operate in high speed, as well as with lower power consumption, while being driven with a low voltage. At the same time, the voltage tolerance and the reliability of the analog circuits can be improved.

It is desirable, in the semiconductor device according to the first aspect of the invention, that the first circuit block be a low-voltage driver circuit, and the second circuit block and the third circuit block be high-voltage driver circuits.

Consequently, the low-voltage driver circuit and the high-voltage driver circuits can be combined on the same semiconductor substrate, while forming the low-voltage driver circuit in the SOI structure, and the high-voltage driver circuits in the bulk structure. At the same time, noises emitted outward from the low-voltage driver circuit can be blocked by the SOI structure, while enhancing the latch-up resistance. This suppresses the increase in chip sizes, allowing the low-voltage driver circuit to operate in high speed as well as with lower power consumption, and at the same time, improving the voltage tolerance and reliability of the high-voltage driver circuit.

According to a second aspect of the invention, a semiconductor device includes: a semiconductor layer, arranged, via an insulation layer, on a region of a part of a semiconductor substrate; a microcontroller (MCU) core formed on the semiconductor layer; and two or more circuit blocks formed on the semiconductor substrate, selected from the group including: a DRAM arranged around the MCU core; a nonvolatile memory; a power circuit; a high-voltage driver; a radio frequency circuit; and an oscillation circuit.

Consequently, a plurality of circuit blocks having the bulk structure can be combined on the same semiconductor substrate, isolated from each other by the SOI structure, in the case of forming the system LSI in a single chip. This allows a decrease of the distances between the circuit blocks, while suppressing the crosstalk noise between the circuit blocks, thereby the system LSI is realized, while suppressing the increase in the chip size, while also improving the characteristics and reliability of the system LSI.

According to a third aspect of the invention, a semiconductor device includes: a semiconductor layer, arranged, via an insulation layer, on a region of a part of a semiconductor substrate; an MCU core formed on the semiconductor layer; and two or more circuit blocks formed on the semiconductor substrate, selected from the group including: a sensor interface circuit arranged around the MCU core; a radio frequency circuit; and an oscillation circuit; wherein the circuit block is provided with an SOI structure arranged on at least one side of the periphery of the circuit block, while contacting another circuit block.

This allows a decreasing of the distances between the adjacent circuit blocks, while suppressing the crosstalk noise between those circuit blocks, in the case of forming a system LSI in a single chip. Thereby, the system LSI is realized while suppressing the increase in the chip size, while also improving the characteristics and reliability of the system LSI.

According to a forth aspect of the invention, a semiconductor device includes: a semiconductor layer, arranged, via an insulation layer, on a region of a part of a semiconductor substrate; an SRAM formed on the semiconductor layer; and two or more circuit blocks formed on the semiconductor substrate, selected from the group including: a power circuit arranged around the SRAM; a driver; and a digital-to-analog converter.

This allows a decreasing of the distances between the circuit blocks, while suppressing the crosstalk noise therebetween, in the case of forming, in a single chip, a driver LSI that has the SRAM. Thereby the driver LSI is realized while suppressing the increase in the chip size, while also improving the characteristics and reliability of the driver LSI.

According to a fifth aspect of the invention, a semiconductor device includes: a semiconductor layer, arranged, via an insulation layer, on a region of a part of a semiconductor substrate; and a real-time clock circuit and a circuit operative on stand-by, both of which being formed on the semiconductor layer.

According to a sixth aspect of the invention, a semiconductor device includes: an SOI region in which a semiconductor layer is deposited on an insulation layer; a bulk region having only a substrate as an underlying layer; and a first dopant diffusion layer for potential fixing, deposited on the semiconductor substrate, between a circuit element formed in the silicon-on-insulator region and a circuit element formed in the bulk region; wherein the silicon-on-insulator region and the bulk region are on the same semiconductor substrate.

This allows the first dopant diffusion layer to block the electric flux line generated between the circuit element formed in the SOI region and the circuit element formed in the bulk region, thereby suppressing the crosstalk noise therebetween. Consequently, it is possible to prevent the improper operation of the semiconductor device.

It is desirable that the semiconductor device according to the sixth aspect of the invention further include: the silicon-on-insulator region including a first silicon-on-insulator region and a second silicon-on-insulator region which is thicker than the first silicon-on-insulator region; and a second dopant diffusion layer for potential fixing, formed on the semiconductor layer, between a circuit element formed in the first silicon-on-insulator region and a circuit element formed in the second silicon-on-insulator region. Here, in the first SOI region, a transistor that is, for instance, a partially depleted one is formed, and in the second SOI region, a transistor that is, for instance, a fully depleted one is formed.

This allows the second dopant diffusion layer to block the electric flux line generated between the circuit element formed in the first SOI region and the circuit element formed in the second SOI region, thereby suppressing the crosstalk noise within those SOI regions.

It is desirable that the semiconductor device according to the sixth aspect of the invention further include a third dopant diffusion layer for potential fixing, on the semiconductor substrate under the insulation layer in the SOI region.

In this case, the first dopant diffusion layer and the third dopant diffusion layer may both have a first conductivity type; and the first dopant diffusion layer may have a higher dopant concentration of the first conductivity type than the third dopant diffusion layer.

In this case, the second dopant diffusion layer and the third dopant diffusion layer may both be of a first conductivity type; and the second dopant diffusion layer may have a higher dopant concentration of the first conductivity type than the third dopant diffusion layer.

In the semiconductor device according to the sixth aspect of the invention, it is easy to block the electric flux line curling in from the bulk region to underneath the insulation layer in the SOI region, as well as to prevent the transmission of noise generated in the SOI region toward the semiconductor substrate.

It is desirable that, in the semiconductor device according to the sixth aspect of the invention, the semiconductor substrate have a resistivity of more than 500 Ωcm. This allows the further improvement of the crosstalk-noise resistance of the semiconductor substrate, since the substrate resistance under the insulation layer inside the SOI region can be increased in this structure.

According to a seventh aspect of the invention, a semiconductor device includes: a first silicon-on-insulator region in which a first semiconductor layer is deposited on an insulation layer; a second silicon-on-insulator region in which a second insulation layer and a second semiconductor layer are deposited on the first semiconductor layer; and a dopant diffusion layer for potential fixing, deposited on the first semiconductor substrate, between a circuit element formed in the first silicon-on-insulator region and a circuit element formed in the second silicon-on-insulator region; wherein the first silicon-on-insulator region and the second silicon-on-insulator region are on the same supporting substrate.

This allows the dopant diffusion layer to block the electric flux line generated between the circuit element formed in the first SOI region and the circuit element formed in the second SOI region, thereby suppressing the crosstalk noise between those regions. Consequently, it is possible to prevent the improper operation of the semiconductor device.

According to an eighth aspect of the invention, a semiconductor device includes: a semiconductor layer, arranged, via an insulation layer, on a region of a part of a semiconductor substrate; a first circuit block formed on the semiconductor layer; a second circuit block formed on the semiconductor substrate in the perimeter of the prescribed regions; and a dopant diffusion layer for potential fixing, formed on the semiconductor substrate, between the first circuit block and the second circuit block.

This allows the dopant diffusion layer to block the electric flux line generated between the first circuit block that has the SOI structure and the second circuit block that has the bulk structure, suppressing the crosstalk noise between the first and the second circuit blocks, thereby preventing an improper operation of the semiconductor device.

According to a ninth aspect of the invention, a semiconductor device includes: a semiconductor layer, arranged, via an insulation layer, on a region of a part of a semiconductor substrate; an MCU core formed on the semiconductor layer; a peripheral circuit block which is formed on the semiconductor substrate and arranged in the perimeter of the MCU core, while having at least one of a member of the group including: a memory circuit; a power circuit; an oscillation circuit; and an analog-to-digital converter; and a dopant diffusion layer for potential fixing, formed on the semiconductor substrate, between the MCU core and the peripheral circuit block.

This allows the dopant diffusion layer to block the electric flux line generated between the MCU core that has the SOI structure and the peripheral circuit block that has the bulk structure, suppressing the crosstalk noise therebetween, in the case of forming the system LSI in a single chip. This allows a prevention of the improper operation of the system LSI, thereby improving the operational reliability.

According to a tenth aspect of the invention, a semiconductor device includes: a semiconductor layer, arranged, via an insulation layer, on a region of a part of a semiconductor substrate; an MCU core formed on the semiconductor layer; a first peripheral circuit block which is formed on the semiconductor substrate and arranged in the perimeter of the MCU core, while having at least one of a member of the group including: a sensor interface circuit; a radio frequency circuit; a liquid crystal controller; and a power circuit; and a second peripheral circuit block formed on the semiconductor substrate; an SOI structure arranged on at least one side of the periphery of the first peripheral circuit block, while being adjacent to the second peripheral circuit block; and a dopant diffusion layer for potential fixing, formed on the semiconductor substrate, between the microcontroller core and the first peripheral circuit block.

This allows the dopant diffusion layer to block the electric flux line generated between the MCU core that has the SOI structure and the first peripheral circuit block that has the bulk structure, suppressing the crosstalk noise therebetween, in the case of forming the system LSI in a single chip. Moreover, the crosstalk noise between the first peripheral circuit block and the second peripheral circuit block can also be suppressed by the SOI structure. This allows a prevention of the improper operation of the system LSI, thereby improving the operational reliability.

Here, if the RTC circuit and the circuits to which the voltage is impressed during the stand-by are formed in fully depleted SOI structure, then the power consumption during stand-by can be significantly reduced. Moreover, due to the high crosstalk noise tolerance, the circuits having the bulk structure can be driven in a high voltage during the operation, while the RTC circuit and the stand-by operational circuit being driven in a low voltage.

According to an eleventh aspect of the invention, a semiconductor device includes: a semiconductor layer, arranged, via an insulation layer, on a region of a part of a semiconductor substrate; an SRAM formed on the semiconductor layer; a peripheral circuit block which is formed on the semiconductor substrate and arranged in the perimeter of the SRAM, while having at least one of a member of the group including: a power circuit; a driver; an input-output circuit; and a digital-to-analog converter; and a dopant diffusion layer for potential fixing, formed on the semiconductor substrate, between the SRAM and the peripheral circuit block.

This allows the dopant diffusion layer to block the electric flux line generated between the SRAM that has the SOI structure and the peripheral circuit block that has the bulk structure, suppressing the crosstalk noise therebetween, in the case of forming, in a single chip, a driver LSI that has the SRAM. This enables to prevent the improper operation of the driver LSI, thereby improving the operational reliability.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

A method for manufacturing a semiconductor device in accordance with embodiments of the invention will now be described with references to the accompanying drawings.

First Embodiment

FIG. 1is a sectional drawing illustrating a configuration example of a semiconductor device according to the first embodiment.

InFIG. 1, an SOI forming region R11and a bulk regions R12and R13are provided on a semiconductor substrate1, and wells2and3are formed in the bulk regions R12and R13. Here, the bulk regions R12and R13can be arranged on the semiconductor substrate1so as to be isolated from each other by the SOI forming region R11. For instance, the SOI forming region R11can be formed between the bulk region R12and the bulk region R13. In the case of using a high-resistant substrate with resistivity of more than 500 Ωcm for the semiconductor substrate1, the substrate resistance under an insulation film4in the silicon-on-insulator forming region can be increased.

In the SOI forming region R11and the bulk regions R12and R13, grooves14are formed, isolating devices in the SOI forming region R11as well as in the bulk regions R12and R13. Moreover, at the border between the SOI forming region R11and the bulk region R12, as well as at the border between the SOI forming region R11and the bulk region R13, grooves13are formed, isolating devices in the SOI forming region R11from the bulk regions R12and R13. Buried insulators11and12are buried in the grooves13and14. Examples for buried insulators11and12buried in the grooves13and14include films such as silicon oxide film and silicon nitride film.

In the SOI forming region R11, a buried insulation layer4is formed on the semiconductor substrate1, and on the buried insulation layer4, a semiconductor layer5is deposited, isolated by the groove13and the groove14. Further, gate electrodes7aand7bare formed on the semiconductor layer5via gate insulation films6aand6b, and sidewalls8aand8bare formed on the sides of the gate electrodes7aand7b. Still further, on the semiconductor layer5, a source layer9aand a drain layer10aare formed, arranged so as to sandwich the gate electrode7a, and, a source layer9band a drain layer10bare formed, arranged so as to sandwich the gate electrode7b.

In the bulk region R12, gate electrodes7cand7dare formed on a well2via gate insulation films6cand6d, and sidewalls8cand8dare formed on the sides of the gate electrodes7cand7d. Further, on the well2, a source layer9cand a drain layer10care formed, arranged so as to sandwich the gate electrode7c, and, a source layer9dand a drain layer10dare formed, arranged so as to sandwich the gate electrode7d.

In the bulk region R13, gate electrodes7eand7fare formed on a well3via gate insulation films6eand6f, and sidewalls8eand8fare formed on the sides of the gate electrodes7eand7f. Moreover, on the well3, a source layer9eand a drain layer10eare formed, arranged so as to sandwich the gate electrode7e, and, a source layer9fand a drain layer10fare formed, arranged so as to sandwich the gate electrode7f.

Examples of materials for the semiconductor substrate1and the semiconductor layer5include Si, Ge, SiGe, SiC, SiSn, PbS, GaAs, InP, GaP, GaN, and ZnSe. The semiconductor substrate1on which the SOI forming region R11and the bulk regions R12and R13are provided can be formed, using the SOI substrate, or with separation-by-bonding-Si-islands (SBSI) method. Examples of the SOI substrate include a separation by implanted oxygen (SIMOX) substrate, a bonded substrate, and a laser-annealed substrate. Substrates such as the ones formed with sapphire or glass may also be used, alternatively to the semiconductor substrate1.

Consequently, a plurality of circuit blocks formed on the bulk regions R12and R13can be installed on the same semiconductor substrate1, isolated from each other by the SOI forming region R11that has a tolerance against crosstalk noises. This allows a decreasing of the distances between the adjacent circuit blocks, while suppressing the crosstalk noise between the circuit blocks formed on the semiconductor substrate1, thereby suppressing the increase in a chip size, allowing to mount various functional components onto a single chip, while improving the characteristics and reliability of semiconductor devices. The crosstalk noise tolerance of the substrate further increases, if a high-resistance substrate is used as the semiconductor substrate1. Moreover, the bulk regions R12and R13can surround the perimeter of the SOI forming region R11, improving the heat dissipation from the SOI forming region R11, and thereby improving the temperature characteristic of the circuit blocks formed on the SOI forming region R11.

In the above-referenced embodiment, a method for device isolation of the SOI forming region R11and the bulk regions R12and R13in a shallow trench isolation (STI) structure is described, while device isolation with local oxidation of silicon (LOCOS) structure may also be employed.

Low-voltage, low-current driver devices can be formed on the SOI forming region R11, and high-voltage tolerant, high-voltage driver devices can be formed on the bulk regions R12and R13. Consequently, low-voltage driver circuits and high-voltage driver circuits can be combined on the same semiconductor substrate1, forming the low-voltage driver circuits in the SOI structure, and high-voltage driver circuits in the bulk structure. At the same time, noises emitted outward from the low-voltage driver circuit can be blocked by the SOI structure, while enhancing the latch-up resistance. This suppresses the increase in chip sizes, allowing the low-voltage driver circuit to operate in high speed as well as with lower power consumption, and at the same time, improving the voltage tolerance and reliability of the high-voltage driver circuit. Alternatively, logic circuits or SRAM can be formed on the SOI forming region R11, and electrostatic protection circuits, analog circuits, or bipolar transistors can be formed on the bulk regions R12and R13.

Second Embodiment

FIGS. 2A to 2Eare top view drawings illustrating configuration examples of a semiconductor device according to a second embodiment.

As shown inFIG. 2A, a plurality of circuit blocks is mounted on a semiconductor chip, and a gate driver21, digital-to-analog (hereinafter “D/A”) converter22, an SRAM23, a power circuit24, a gate array logic circuit25, and an input-output (hereinafter “I/O”) circuit26are formed as the circuit blocks. Here, the gate driver21, the D/A converter22, the power circuit24, and the I/O circuit26are arranged in the bulk regions, and the SRAM23and the gate array logic circuit25are arranged in the SOI forming regions. Moreover, the circuit blocks formed in the bulk regions can be arranged to contact at least one side of the circuit blocks formed in the SOI forming regions. Further, the circuit blocks formed in the SOI regions can be arranged between the circuit blocks formed in the bulk forming regions.

This allows a decreasing of the distances between the adjacent circuit blocks, while suppressing the crosstalk noise between the circuit blocks, in the case of forming, in a single chip, a driver LSI that has the SRAM23. Thereby the driver LSI is realized while suppressing the increase in the chip size, while also improving the characteristics and reliability of the driver LSI.

As shown inFIG. 2B, a plurality of circuit blocks is mounted on the semiconductor chip, and a liquid crystal controller31, a sensor interface circuit32, a microcontroller unit (MCU)33, a radio frequency (RF) circuit34, a real time clock circuit35, and a power circuit36are formed as the circuit blocks. Here, the liquid crystal controller31and the power circuit36are arranged in the bulk regions, and the MCU33and the RTC circuit35are arranged in the SOI forming regions. Moreover, the sensor interface circuit32and the RF circuit34are arranged in the bulk region, and at the same time, the SOI structures are installed, arranged to contact other circuit blocks, while arranged on at least one side of the periphery of the sensor interface circuit32and the RF circuit34.

This allows a decreasing of the distances between the adjacent circuit blocks, while suppressing the crosstalk noise between the circuit blocks, in the case of forming a system LSI in a single chip. Thereby, the system LSI is realized while suppressing the increase in the chip size, while also improving the characteristics and reliability of the system LSI. Here, if the RTC circuit and the circuits to which the voltage is impressed during the stand-by are formed in fully depleted SOI structure, the power consumption during stand-by can be significantly reduced. There is no increase in power consumption, if the circuit regions in which the voltage is not impressed during the stand-by are formed in the bulk regions.

As shown inFIG. 2C, a plurality of circuit blocks is mounted on the semiconductor chip, and a power circuit41, an SRAM42, an oscillator43, an MCU44, a DRAM45, a logic circuit46, and an analog-to-digital (hereinafter “A/D”) converter47are formed as the circuit blocks. Here, the power circuit41, the oscillator43, the DRAM45, and the A/D converter47are arranged in the bulk regions, and the SRAM42, the MCU44, and the logic circuit46are arranged in the SOI forming regions. Moreover, the circuit blocks formed in the bulk regions can be arranged to contact at least one side of the circuit blocks formed in the SOI forming regions. Further, the circuit blocks formed in the SOI regions can be arranged between the circuit blocks formed in the bulk forming regions.

Consequently, a plurality of circuit blocks having the bulk structure can be combined on the same semiconductor substrate, isolated from each other by the SOI structure, in the case of forming the system LSI in a single chip. This allows a decrease of the distances between the circuit blocks, while suppressing the crosstalk noise between the circuit blocks, thereby the system LSI is realized while suppressing the increase in the chip size, while also improving the characteristics and reliability of the system LSI.

As shown inFIG. 2D, a plurality of circuit blocks is mounted on the semiconductor chip, and analog circuits51and53, as well as digital circuit52are formed as the circuit blocks. Here, the analog circuits51and53are arranged in the bulk regions, and the digital circuit52is arranged in the SOI forming region. Moreover, the circuit blocks formed in the bulk regions can be arranged to contact at least one side of the circuit blocks formed in the SOI forming regions. Further, the circuit blocks formed in the SOI regions can be arranged between the circuit blocks formed in the bulk forming regions.

Consequently, the digital circuit52and the analog circuits51and53can be combined on the same substrate, while forming the digital circuit52in the SOI structure, and the analog circuits51and53in the bulk structure. At the same time, noises emitted outward from the digital circuit62can be blocked by the SOI structure, while enhancing the latch-up resistance. Moreover, the analog circuits51and53are distant from one another, having the SOI structure in between, resulting in the improvement of the crosstalk tolerance between the analog circuit blocks (i.e., between the analog circuit51and53). This suppresses the increase in chip sizes, allowing the digital circuit52to operate in high speed, as well as with lower power consumption, while being driven in a lower voltage. At the same time, the voltage tolerance and the reliability of the analog circuits51and53can be improved.

As shown inFIG. 2E, a plurality of circuit blocks is mounted on the semiconductor chip. A circuit62that needs to operate during the stand-by, as well as shutdown circuits61and63to which no voltage is impressed during the stand-by, are formed as the circuit blocks. Here, the stand-by operational circuit62can be arranged in the SOI forming region, utilizing a fully depleted SOI device. Consequently, the voltage for the stand-by operational circuit62can be set low, and the current leak during the stand-by can be suppressed. As a result, power consumption of the entire LSI during the stand-by can be significantly reduced. Moreover, the stand-by shutdown circuits61and63may be formed in either of the bulk regions or the SOI region. At this time, the circuit blocks formed in the bulk regions can be arranged to contact at least one side of the circuit blocks formed in the SOI forming region. Consequently, a semiconductor device having an excellent tolerance in substrate crosstalk noise can be provided, while significantly reducing the power consumption during the stand-by.

Third Embodiment

FIG. 3is a sectional drawing illustrating a configuration example of a semiconductor device according to a third embodiment.

As shown inFIG. 3, this semiconductor device has the bulk region and the SOI region formed in a semiconductor substrate101. Here, the bulk region means that the region has only the semiconductor substrate101as an underlying layer. Moreover, the SOI region means that semiconductor layers105are formed on the semiconductor substrate101via insulation layers103. Examples of the semiconductor substrate101include a p-type silicon (Si) substrate, and examples of the insulation layers103include silicon oxide film (SiO2). The semiconductor layers105are formed with, for instance, Si. Such semiconductor substrate (device) having the bulk region and the SOI region in the same substrate is formed, for instance, with the SBSI method.

As shown inFIG. 3, a well107of, for instance, an n-type, is formed in the semiconductor substrate101within the bulk region. Device isolation films109are formed in the perimeter of the well107, and a metal-insulator-semiconductor (MIS) transistor110is formed in the region surrounded by the device isolation films109. That is to say, a gate electrode111is formed on the well107via a gate insulation film, and sidewalls112are formed on both sides of the gate electrode111. A source113and a drain114are formed in the well107at the sides of the gate electrode111.

At the same time, an insulation layers103are formed in the semiconductor substrate101within the SOI regions, and a semiconductor layers105are formed on the insulation layers103. The device isolation films109are formed in the SOI regions, and MIS transistors120and130are formed in the region surrounded by the device isolation films109. That is to say, in one of the SOI regions, a gate electrode121is formed via the gate insulation film, and sidewalls22are formed on both sides of the gate electrode121. A source123and a drain124are formed in the semiconductor layer105at the sides of the gate electrode121. Similarly, in the other SOI region, a gate electrode131is formed via the gate insulation film, and sidewalls32are formed on both sides of the gate electrode131. A source133and a drain134are formed in the semiconductor layer105at the sides of the gate electrode131.

The device isolation film109is formed with, for instance, SiO2, with methods such as STI or LOCOS. The un-illustrated gate insulation film is formed with materials such as SiO2, silicon oxide nitride (SiON) film, silicon nitride (SiN) film, or the combinations thereof. The gate electrodes111,121, and131are composed of materials such as polycrystalline silicon that includes conductive dopants such as phosphorus and boron. The sidewalls112,122, and132are formed with, for instance, SiO2.

Hereafter, for the convenience of description, the MIS transistors formed in the bulk regions are referred to as “bulk transistors”. Moreover, the MIS transistors formed in the SOI regions are referred to as “SOI transistors”.

In this semiconductor device, a dopant diffusion layer191for potential fixing is formed on the semiconductor substrate101, between the bulk transistor110and the SOI transistor120. The conductivity type of this dopant diffusion layer191is, for instance, p-type, and in order to fix the potential in this semiconductor device, a reverse bias (in other words, a negative potential) is impressed to the dopant diffusion layer191during the operation of the semiconductor device. This allows the dopant diffusion layer191to block the electric flux line generated between the bulk transistor110and the SOI transistor120, suppressing the crosstalk noise between those transistors110and120.

In the case where, for instance, the SOI transistor120functions as a circuit element constituting the low-voltage driver digital circuit, and the bulk transistor110functions as a circuit element constituting the high-voltage driver circuit (or an analog circuit), the high-voltage noise of electric flux line (in other words, noise generated by impressing a high voltage to the source or the drain) emitted from the bulk transistor110is terminated at the dopant diffusion layer191, by impressing the reverse bias to the dopant diffusion layer191so as to fix the potential thereof. Moreover, since the depletion layer extends from the dopant diffusion layer191toward the semiconductor substrate101by impressing the reverse bias, the depletion layer blocks the high field from the bulk transistor110. As a result, the inversion is prevented in the vicinity of the insulation layers103that are under the semiconductor layers105directly under the gate electrode121.

A rapid signal switching in the digital circuit generates large amount of noise. However, since the SOI transistors120and130are separated from the semiconductor substrate101by the insulation layers103, the noise transmission to the semiconductor substrate101can be suppressed. Further, there is no DC current path due to the device isolation films109formed between the bulk transistor110and the SOI transistors.

Hence, the crosstalk noise between the bulk transistor110and the SOI transistor120, as well as the SOI transistor130, can be suppressed, preventing an improper operation of the low-voltage driver digital circuit and of the high-voltage driver circuit (or analog circuit). Consequently, it is possible to improve the operation reliability of the semiconductor device.

Here, it is desirable to use a high-resistance substrate with resistivity of more than 500 Ωcm for the semiconductor substrate101. This allows the further improvement of the crosstalk-noise tolerance of the semiconductor substrate, since the substrate tolerance under the insulation layers103inside the SOI region can be increased in this structure.

In this third embodiment, the dopant diffusion layer191corresponds to the “first dopant diffusion layer” referred in claim11through claim16; the bulk transistor110corresponds to the “circuit element formed in the bulk region” referred in claim11through claim16; and the SOI transistors120and130correspond to the “circuit elements formed in the silicon-on-insulator regions” referred in claim11, and claim13through claim16.

Forth Embodiment

FIG. 4is a sectional drawing illustrating a configuration example of a semiconductor device according to the forth embodiment. The same signs and numerals as that ofFIG. 3are used inFIG. 4for the parts having the same structure as indicated inFIG. 3, and the overlapping description thereof is omitted.

As shown inFIG. 4, this semiconductor device has the bulk region, as well as the first and the second SOI regions formed in a semiconductor substrate101. The n-type well107is formed in the semiconductor substrate101within the bulk region. The device isolation films109are formed in the perimeter of the well107, and the bulk transistor110is formed in the region surrounded by the device isolation films109.

Moreover, the insulation layers103are formed in the semiconductor substrate101within the first SOI regions, and the semiconductor layers105are formed on the insulation layers103. The device isolation films109are formed in the first SOI regions, and the SOI transistors120and130that are, for instance, fully depleted, are formed in the region surrounded by the device isolation films109.

Here, in the fully depleted SOI transistors, the semiconductor layer has a thickness of, for instance, 50 nm or less, and the entire body sandwiched by the source/drain is fully depleted. A precipitous sub threshold characteristics is obtained in the fully depleted transistors, allowing to keep the threshold voltage low, while suppressing the off-leak current, thereby enabling rapid operation in a low-voltage. Due to the above characteristics, the fully depleted transistors are often used as a circuit element of the low-voltage driver logic circuit.

Particularly, the power consumption during the stand-by can be significantly reduced, by forming the RTC circuit that operates during the stand-by and the circuit to which the voltage is impressed during the stand-by in the first SOI region.

Moreover, the insulation layer153is formed in the second SOI regions, and the semiconductor layer155is formed thereon. The device isolation films159are formed in the second SOI regions, extending deeper than the device isolation films109in the direction of substrate, and the SOI transistor140that is, for instance, partially depleted, is formed in the region surrounded by the device isolation films159.

Here, in the partially depleted SOI transistor, the semiconductor layer has a thickness of, for instance, 100 nm or more, and the bottom of the body is fully not depleted. The partially depleted SOI transistors have approximately the same level of sub-threshold characteristics as that of the bulk transistors, which means that from the viewpoint of low-power consumption, the effect is not as much as that of the fully depleted ones. On the other hand, the partially depleted ones excel in voltage tolerance, compared to the fully depleted ones. Due to the above characteristics, the partially depleted transistors are often used as a circuit element of the high-voltage driver circuit.

The insulation layer153in the second SOI region is formed with, for instance, SiO2, and the semiconductor layer155is formed with, for instance, Si. The device isolation films159surrounding the second SOI region are formed with, for instance, SiO2, using STI or LOCOS method.

In this semiconductor device, the dopant diffusion layer191of, for instance, p-type, is formed on the semiconductor substrate101, between the bulk transistor110and the SOI transistor120. Moreover, a dopant diffusion layer192of, for instance, n-type, is formed between the fully depleted SOI transistor130and the partially depleted SOI transistor140. Further, in the semiconductor substrate101under the insulation layer103directly under the SOI transistor120, a p-type well126is formed, and in the semiconductor substrate101under the insulation layer directly under the SOI transistor130.

As shown inFIG. 4, the dopant diffusion layer191is in junction with the well126inside the semiconductor substrate101, and the p-type dopant concentration is higher in the dopant diffusion layer191than in the well126. Moreover, the dopant diffusion layer192is in junction with the well136inside the semiconductor substrate101, and the n-type dopant concentration is higher in the dopant diffusion layer192than in the well136. When operating this semiconductor device, a bias (for example, a negative potential) is impressed on the dopant diffusion layer191, in order to fix the potentials of the dopant diffusion layer191and of the well126. At the same time, the same bias or a reverse bias (in other words, a positive potential) is impressed on the dopant diffusion layer192, in order to fix the potentials of the dopant diffusion layer192and the well136.

This allows the dopant diffusion layer191to block the electric flux line generated between the bulk transistor110and the SOI transistor120. This also allows the dopant diffusion layer192to block the electric flux line generated between the SOI transistor130and the SOI transistor140.

Moreover, in this semiconductor device, the well126is formed in the semiconductor substrate101, under the insulation layer103directly under the SOI transistor120. Therefore, it is easy to block the electric flux line curling in from the bulk region to underneath the SOI transistor120, as well as to prevent the transmission of noise generated in the SOI transistor120toward the semiconductor substrate101. Similarly, in this semiconductor device, the well136is formed in the semiconductor substrate101, under the insulation layer103directly under the SOI transistor130. Therefore, it is easy to block the electric flux line curling in from the second SOI region to underneath the SOI transistor130, as well as to prevent the transmission of noise generated in the SOI transistor130, toward the semiconductor substrate101.

In this forth embodiment, the dopant diffusion layer191corresponds to the “first dopant diffusion layer” referred in claim11through claim15; the bulk transistor110corresponds to the “circuit element formed in the bulk region” referred in claim11through claim15; the SOI transistors120and130correspond to the “circuit elements formed in the (first) silicon-on-insulator region” referred in claim11through claim15; and the SOI transistor140corresponds to the “circuit element formed in the second silicon-on-insulator region” referred in claim12through claim15. Further, the dopant diffusion layer192corresponds to the “second dopant diffusion layer” referred in claim12through claim15.

Fifth Embodiment

FIG. 5is a sectional drawing illustrating a configuration example of a semiconductor device according to the fifth embodiment. The same signs and numerals as that ofFIGS. 3 and 4are used inFIG. 5for the parts having the same structure as indicated inFIGS. 3 and 4, and the overlapping description thereof is omitted.

As shown inFIG. 5, this semiconductor device has the first and the second SOI regions in a semiconductor substrate101, and a first insulation layer163and a first semiconductor layer165are deposited on the part of the semiconductor substrate101. In the second SOI region, the partially depleted SOI transistor140is formed on the first semiconductor layer165. Moreover, in the first SOI region, the second insulation layers103and the second semiconductor layers105are deposited on the first semiconductor layer165, and the fully depleted SOI transistors120and130are formed on the second insulation layers105.

In this semiconductor device, a dopant diffusion layer193for potential fixing is formed between SOI transistor120in the first SOI region and the SOI transistor140in the second SOI region. The conductivity type of the semiconductor layer193is, for instance, a p-type. When operating this semiconductor device, a reverse bias (in other words, a negative potential) is impressed on the dopant diffusion layer193, in order to fix the potential thereof. This allows the dopant diffusion layer193to block the electric flux line generated between the fully depleted SOI transistor120and the partially depleted SOI transistor140, suppressing the crosstalk noise between those transistors120and140.

In this fifth embodiment, the semiconductor substrate101corresponds to the “supporting substrate” referred in claim17; the SOI transistors120and130correspond to the “circuit element formed in the first silicon-on-insulator region” referred in claim17; and the SOI transistor140corresponds to the “circuit element formed in the second silicon-on-insulator region” referred in claim17.

As described, in the third to fifth embodiments, the dopant diffusion layers191,192, and193, as well as the wells126and136are formed in the periphery of the SOI structure within the circuit blocks. The high-voltage noises of electric flux line emitted from the peripheral circuit blocks are terminated, by fixing the potentials of those dopant diffusion layers and of the wells, thereby preventing the inversion of the back side of the SOI layer (in other words, a semiconductor layer) on the box (in other words, an insulation layer). A rapid signal switching of the digital circuits generates many noises in the semiconductor substrate101. According to the embodiments of the invention, the boxes or the device isolation films blocks these noises.

Moreover, according to the embodiments of the invention, it is desirable to use a high-resistance substrate with resistivity of more than 500 Ωcm for the semiconductor substrate101. The SOI structures on the high-resistance substrate further strengthen the crosstalk noise tolerance. It is possible to provide an inexpensive semiconductor device that operates in a high precision, and in a high speed with low power consumption, having a high tolerance against the crosstalk noises, where the circuit blocks driven in different voltages, or, the circuit blocks having a hybrid of digital and analog circuits, operate in a stable manner.

Sixth Embodiment

FIG. 6is a top view drawing illustrating a configuration example of a semiconductor device according to a sixth embodiment of the invention. The same signs and numerals as that ofFIG. 3are used inFIG. 6for the parts having the same structure as indicated inFIG. 3, and the overlapping description thereof is omitted.

As shown inFIG. 6, a plurality of circuit blocks are mounted on a semiconductor substrate (semiconductor chip), and a gate driver211, a D/A converter212, an SRAM213, a power circuit214, a gate array logic circuit215, and an I/O circuit216are formed as the circuit blocks. Here, the gate driver211, the D/A converter212, the power circuit214, and the I/O circuit216are arranged in the bulk regions, and the SRAM213and the gate array logic circuit215are arranged in the SOI regions. At this time, the circuit blocks formed in the bulk regions (in other words, the circuit blocks having the bulk structure) are arranged to be adjacent to at least one side of the circuit blocks formed in the SOI region (in other words, the circuit blocks having the SOI structure). Further, the circuit blocks having the SOI structure are arranged between the circuit blocks having the bulk structure.

This allows a decrease of the distances between the adjacent circuit blocks, while suppressing the crosstalk noise between the circuit blocks, even in the case of forming, in a single chip, the driver LSI that has the SRAM213.

Moreover, in this semiconductor device, the dopant diffusion layer191for potential fixing is formed on the semiconductor substrate in the periphery of the SRAM213that has the SOI structure, and the SRAM213is surrounded by the dopant diffusion layer191, when viewed from the top. Similarly, in the semiconductor substrate in the periphery of the gate array logic circuit215that has the SOI structure, the dopant diffusion layer191for potential fixing is formed, and the gate array logic circuit215is surrounded by the dopant diffusion layer191, when viewed from the top. When operating the driver LSI, a reverse bias is impressed on the dopant diffusion layer191in order to fix the potential of the dopant diffusion layer191.

This allows the dopant diffusion layers191to block the electric flux line generated between the SRAM213or the gate array logic circuit215that have the SOI structure and the circuit blocks that have the bulk structure, suppressing the crosstalk noise therebetween. This enables to prevent the improper operation of the driver LSI, thereby improving the operational reliability.

In the sixth embodiment, the SRAM213and the gate array logic circuit215correspond to the “first circuit block” referred in claim18. Moreover, the gate driver211, the D/A converter212, the power circuit214, and the I/O circuit216correspond to the “second circuit block” referred in claim18, and the “peripheral circuit block” referred in claim21.

Seventh Embodiment

FIG. 7is a top view drawing illustrating a configuration example of a semiconductor device according to a seventh embodiment of the invention. The same signs and numerals as that ofFIG. 3are used inFIG. 7for the parts having the same structure as indicated inFIG. 3, and the overlapping description thereof is omitted.

As shown inFIG. 7, a plurality of circuit blocks are mounted on the semiconductor substrate (semiconductor chip), and a liquid crystal controller (LCD)221, a sensor interface circuit222, a microcontroller unit (MCU)223, a radio frequency (RF) circuit224, a real time clock (RTC) circuit225, and a power circuit226are formed as the circuit blocks. Here, the LCD221, the sensor interface circuit222, the RF circuit224, and the power circuit226are arranged in the bulk regions, and the MCU223and the RTC circuit225are arranged in the SOI regions.

Moreover, in the region including at least one side of the periphery of the sensor interface circuit222and the RF circuit224, SOI structures229are arranged adjacently to other circuit blocks. Here, the SOI structures means a structure in which an insulation layer and a semiconductor layers are deposited on a semiconductor substrate. This allows a decreasing of the distances between the adjacent circuit blocks, while suppressing the crosstalk noise between the circuit blocks, in the case of forming a system LSI in a single chip.

Moreover, in this semiconductor device, the dopant diffusion layers191for potential fixing are formed on the semiconductor substrate in the peripheries of the MCU223and the RTC circuit225that are arranged in the SOI regions (in other words, that have SOI structures), and the MCU223and the RTC circuit225are surrounded by this dopant diffusion layer191, when viewed from the top. Further, the dopant diffusion layer191for potential fixing is formed on the substrate in the peripheries of the SOI structures229, so as to surround the SOI structures.

This allows a blocking of the electric flux line generated between the MCU223or RTC circuit225that have the SOI structure, and the circuit blocks that have the bulk structure, suppressing the crosstalk noise therebetween. This allows a prevention of the improper operation of the system LSI, thereby improving the operational reliability.

Moreover, the power consumption during the stand-by can be significantly reduced, by forming, in the first SOI regions, the group of circuits such as RTC circuit to which the voltage is impressed during the stand-by, as well as by applying the fully depleted SOI transistors.

In the seventh embodiment, the MCU223and the RTC circuit225correspond to the “first circuit block” referred in claim18. Further, the LCD221, the sensor interface circuit222, and the power circuit226correspond to the “second circuit block” referred in claim18. Still further, the MCU223corresponds to the “microcontroller core” referred in claim20; the sensor interface circuit222and the RF circuit224correspond to the “first peripheral circuit block” referred in claim20; and the LCD221corresponds to the “second peripheral circuit block” referred in claim20.

Eighth Embodiment

FIG. 8is a top view drawing illustrating a configuration example of a semiconductor device according to a eighth embodiment of the invention. The same signs and numerals as that ofFIG. 3are used inFIG. 8for the parts having the same structure as indicated inFIG. 3, and the overlapping description thereof is omitted.

As shown inFIG. 8, a plurality of circuit blocks are mounted on a semiconductor substrate (semiconductor chip), and a power circuit231, an SRAM232, an oscillator233, an MCU234, a DRAM235, and a logic circuits236and237are formed as the circuit blocks. Here, the power circuit231, the oscillator233, and the DRAMs235and237are arranged in the bulk regions, and the SRAM232, the MCU234and the logic circuit236are arranged in the SOI regions. At this time, the circuit blocks formed in the bulk regions (in other words, the circuit blocks having the bulk structure) are arranged to be adjacent to at least one side of the circuit blocks formed in the SOI region (in other words, the circuit blocks having the SOI structure). Further, the circuit blocks having the SOI structure are arranged between the circuit blocks having the bulk structure.

Consequently, a plurality of circuit blocks having the bulk structure can be combined on the same semiconductor substrate, isolated from each other by the SOI structure, in the case of forming the system LSI in a single chip. This allows a decreasing of the distances between the circuit blocks, while suppressing the crosstalk noise therebetween.

Moreover, in this semiconductor device, the dopant diffusion layer191for potential fixing is formed on the semiconductor substrate in the periphery of the circuit blocks that have the SOI structure, and the SRAM232, the MCU234, and the logic circuit236are surrounded by the dopant diffusion layer191together, when viewed from the top.

This allows the dopant diffusion layer191to block the electric flux line generated between the circuit blocks that have the SOI structure and the circuit blocks that have the bulk structure, suppressing the crosstalk noise therebetween. This enables to prevent the improper operation of the system LSI, thereby improving the operational reliability.

In the eighth embodiment, the SRAM232, the MCU234, and the logic circuit236correspond to the “first circuit block” referred in claim18. Moreover, the power circuit231, the oscillator233, and the DRAMs235and237correspond to the “second circuit block” referred in claim18, as well as to the “peripheral circuit block” referred in claim19. Further, the MCU234corresponds to the “microcontroller core” referred in claim19; the DRAM19corresponds to the “memory circuit” referred in claim19; and the oscillator233corresponds to the “oscillator” referred in claim19.

As described, in the sixth to eighth embodiments, the dopant diffusion layers191for potential fixing are arranged between the block of the MCU or the SRAM that drive in a low voltage, having a thin SOI structure, and the block of the high-voltage driver circuits (or analog circuits) that have the bulk structure (or, a thick SOI structure). The insulation layers103(or boxes103) and the device isolation films109electrically disconnect the low-voltage driver digital circuit blocks from the circuit blocks, such as the driver circuit block, the DRAM, and the flash memory circuit blocks that drive in a high voltage.

As a result, the crosstalk noises generated by the digital circuits do not break-in to the semiconductor substrate101, avoiding the characteristics deterioration of the analog circuits. Particularly, when the high-resistance Si substrate is used, the crosstalk noise tolerance increases. At the same time, by impressing the reverse bias, the depletion layer that extends from the dopant diffusion layers191to the semiconductor substrate101blocks the electric field. Hence, the electric field noise from the high-voltage driver circuit blocks to the low-voltage driver circuit blocks is suppressed, enabling a highly reliable, low-voltage and low-power digital circuit operation with a high precision. As described above, according to the embodiments of the invention, it is possible to provide a highly reliable system LSI semiconductor device that excels in crosstalk noise tolerance, having therein the high-precision low-voltage driver circuit blocks and the high-voltage driver circuit blocks combined.