Semiconductor device package and method of manufacturing the same

A semiconductor device package includes a transparent substrate, a photo detector and a first conductive layer. The transparent substrate has a first surface and a first cavity underneath the first surface. The photo detector is disposed within the first cavity. The photo detector has a sensing area facing toward a bottom surface of the first cavity of the transparent substrate. The first conductive layer is disposed over the transparent substrate and electrically connected to the photo detector.

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor device package and a method of manufacturing the same, and more particularly, to a semiconductor device package including an optical device and a method of manufacturing the same.

2. Description of the Related Art

Optical devices (such as image sensors) are widely used in many applications, such as digital cameras, cellular phones, security cameras, medical, automobile and the like. The technology used to manufacture optical devices has continued to advance at a great pace. For example, the demands of higher resolution and lower power consumption encourage the miniaturization and integration of optical devices and other electronic components to form a system in package (SiP).

In some existing semiconductor device package, to integrate optical devices and other electronic components into a package, the optical device and other electronic components may be arranged in a stacked structure. For example, the optical device may stack on other electronic components. However, the semiconductor device package with the stacked structure has relatively high manufacturing cost. Moreover, some issues (e.g. warpage, delamination or the like) may occur in the stacked structure, which would adversely affect performance or reliability of the semiconductor device package. Further, the semiconductor device package with the stacked structure has a relatively great size (thickness).

SUMMARY

In some embodiments, a semiconductor device package includes a transparent substrate, a photo detector and a first conductive layer. The transparent substrate has a first surface and a first cavity underneath the first surface. The photo detector is disposed within the first cavity. The photo detector has a sensing area facing toward a bottom surface of the first cavity of the transparent substrate. The first conductive layer is disposed over the transparent substrate and electrically connected to the photo detector.

In some embodiments, a method for manufacturing a semiconductor device package includes (a) providing a transparent substrate with a cavity; (b) disposing a photo detector within the cavity of the transparent substrate, the photo detector having a sensing area facing toward a bottom surface of the cavity of the transparent substrate; (c) forming a first passivation layer on the transparent substrate and within the cavity to cover at least a portion of the photo detector; and (d) forming a first conductive layer on the first passivation layer and electrically connected to the photo detector.

In some embodiments, a method for manufacturing a semiconductor device package includes (a) providing a transparent substrate with a cavity; (b) forming a first passivation layer on the transparent substrate and sidewall of the cavity; (c) forming a conductive layer on the first passivation layer and a portion of a bottom surface of the cavity; and (d) disposing a photo detector within the cavity of the transparent substrate and electrically connected to the conductive layer on the bottom surface of the cavity, the photo detector having a sensing area facing toward a bottom surface of the cavity of the transparent substrate

Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar components. The present disclosure can be best understood from the following detailed description taken in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

FIG. 1illustrates a cross-sectional view of a semiconductor device package1in accordance with some embodiments of the present disclosure. The semiconductor device package1includes a substrate10, an optical device11, a bonding layer12, passivation layers13and15, a conductive layer14and an electrical contact16.

The substrate10has a surface101and a surface102opposite to the surface101. In some embodiments, the surface101of the substrate10is referred to as a first surface and the surface102of the substrate10is referred to as a second surface. In some embodiments, the substrate10is light transparent. The material of the substrate10may be selected to allow the transmission of light emitted or received by the optical device11. In some embodiments, the substrate10is a glass substrate.

The substrate10has or defines a cavity10cextending from the surface101of the substrate10into the substrate10. The cavity10cof the substrate10is underneath the surface101of the substrate10. The cavity10chas a surface10c2(e.g., a bottom surface) and a surface10c1(e.g., a lateral surface or sidewall) connecting the surface101of the substrate10to the surface10c2of the cavity10c. As shown inFIG. 1, the surface10c1and an extension surface of the surface10c2define an angle θ. In some embodiments, the angle θ is greater than 0 degree and equal to or less than 90 degrees.

The optical device11is disposed within the cavity10cof the substrate10. The optical device11is disposed on the surface10c2of the cavity10c. In some embodiments, the optical device11is spaced apart from the surface10c1of the cavity10c. The optical device11is or includes an image sensor or a light detector which may be, e.g., a PIN diode, a photodiode, or a phototransistor. The optical device11has a light receiving area (also referred to as an active surface) facing toward the surface10c2of the cavity10c. The light receiving area of the optical device11is covered or encapsulated by the bonding layer12. The material of the bonding layer12is selected to allow the transmission of light received by the optical device11. In some embodiments, the bonding layer12includes an epoxy resin. In some embodiments, the bonding layer12may also include materials with high transmission and low stress to prevent a particle. In some embodiments, the bonding layer12includes microlens to increase optical performance. In other embodiments, the optical device11may be or include a light emitter or a light emitting device, such as a light-emitting diode (LED) or other light emitting die. For example, the optical device11may include, e.g., an LED, a laser diode, another device that may include one or more semiconductor layers, or a combination of two or more thereof.

The passivation layer13is disposed on the surface101of the substrate10and extends within the cavity10cof the substrate10to cover or encapsulate the optical device11. In some embodiments, the passivation layer13includes silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide or hafnium oxide. In other embodiments, the passivation layer13can be replaced by a solder mask or a molding compound including epoxy without fillers.

The conductive layer14(or redistribution layer, RDL) is disposed on the passivation layer13and penetrates a portion of the passivation layer13to define a through via to electrically connect to the optical device11. In some embodiments, the conductive layer14also extends from the backside surface of the optical device11into the optical device11to electrically connect to conductive contacts or terminals of the optical device11. In some embodiments, the conductive layer14defines an aperture14c(a hole or an opening) as shown inFIG. 1. The aperture14cis at least partially surrounded by the passivation layer13and/or the optical device11.

The passivation layer15is disposed on the passivation layer13to cover or encapsulate the passivation layer13, the conductive layer14and the aperture14cof the conductive layer14. In some embodiments, the passivation layer15includes silicon oxide, silicon nitride, gallium oxide, aluminum oxide, scandium oxide, zirconium oxide, lanthanum oxide or hafnium oxide. In other embodiments, the passivation layer15can be replaced by a solder mask. In some embodiments, the passivation layer15and the passivation layer13are formed of the same material. Alternatively, the passivation layer15and the passivation layer13are formed of different same materials. The passivation layer15may include one or more openings to expose a portion of the conductive layer14. The electrical contacts16(e.g., solder balls) are disposed on the exposed portion of the conductive layer14to provide electrical connections between the optical device11and other circuits, circuit boards or components.

In some embodiments, the optical device11illustrated inFIG. 1can be integrated with other non-optical devices. For example, as shown inFIG. 2A, the optical device11and an electronic component21are integrated into a semiconductor device package2. The substrate10includes another cavity20cfor accommodating the electronic component21. The electronic component21is disposed within the cavity20cof the substrate10and covered or encapsulated by the passivation layer13. The electronic component21may be an active element, such as an IC chip or a die. Examples for the electronic component21may include a processor, a memory, a controller, a RF circuit or any other circuits. The electronic component21may be electrically connected to the optical device11, other circuits or circuit boards through the conductive layer14and/or the electrical contacts16. The electronic component21has a backside surface facing toward a surface20c1of the cavity20cand is connected to the surface20c1through an adhesive layer21h(e.g., tape or glue).

In some existing semiconductor device packages, to integrate optical devices and other electronic components into a package, the optical device and other electronic components may be arranged in a stacked structure. However, the semiconductor device package with the stacked structure has relatively high manufacturing costs. In accordance with the embodiments inFIG. 2Aof the present disclosure, the optical device11and the electronic component21are embedded within the substrate10and arranged side-by-side, which would reduce the manufacturing costs and the thickness of the semiconductor device package. In addition, due to the limitations of the process for the stacked package, the number of the stacked layers is limited, which hinders the integration of optical devices and other electronic components. As shown inFIG. 2BandFIG. 2C, which illustrate top views of the semiconductor device package2inFIG. 2Aaccording to different embodiments, since the optical device11and other electronic components21,21aand/or21bare embedded within the substrate10and arranged side-by-side, it would be easier to integrate the optical device11with required electronic components into a single package, leading to increased flexibility for designing the semiconductor device package2.

Moreover, since the optical device11and the electronic components21,21aand/or21bare embedded within the substrate10, a molding compound for protecting the optical device11and the electronic components21,21aand/or21bcan be omitted, which would eliminate the warpage issues, delamination issues or the like due to coefficient of thermal expansion (CTE) mismatch between different materials. Furthermore, disposing the optical device11and the electronic components21,21aand/or21bwithin the glass substrate can improve the heat dissipation compared with the use of the molding compound.

FIG. 3illustrates a cross-sectional view of a semiconductor device package3in accordance with some embodiments of the present disclosure. The semiconductor device package3inFIG. 3is similar to the semiconductor device package1inFIG. 1, and the differences therebetween are described below.

The passivation layer13is disposed on the surface101of the substrate10and extends on the surface10c1of the cavity10c. The passivation layer13does not cover the optical device11. In other words, the optical device11is exposed from the passivation layer13. The conductive layer14is disposed on the passivation layer13and further extends on the surface10c2of the cavity10c. The passivation layer15is disposed on the conductive layer14and exposes a portion of the conductive layer14.

The optical device11disposed within the cavity10cof the substrate10and electrically connected to the exposed portion of the conductive layer14through electrical contacts34. In some embodiments, the electrical contacts34may be or include conductive pillars, solder balls, stub bumps or other suitable electrical contacts. The optical device11has a light receiving area facing toward the surface10c2of the cavity10c. In some embodiments, the microlens11mmay be disposed on the light receiving area of the optical device11.

As shown in the semiconductor device package1ofFIG. 1, the optical device11is connected to the conductive layer14on the substrate10by the through via that penetrates the passivation layer13. Compared with the semiconductor device package1, the optical device11of the semiconductor device package3is connected to the conductive layer14through an electrical contact34, which would further simplify the manufacturing process and cost. In some embodiments, the optical device11inFIG. 3also can be integrated with other electronic components21as shown inFIG. 4. As shown inFIG. 4, the optical device11and the electronic component21are also arranged side-by-side, and thus the effects or advantages of the semiconductor device package2A can be applicable to the semiconductor device package4inFIG. 4.

FIG. 5illustrates a cross-sectional view of a semiconductor device package5in accordance with some embodiments of the present disclosure. The semiconductor device package5inFIG. 5is similar to the semiconductor device package2inFIG. 2A, and the differences therebetween are described below.

The semiconductor device package5further includes a passivation layer55disposed on the backside surface of the optical device11. For example, the backside surface of the optical device11of the semiconductor device package5is covered by the passivation layer55rather than the passivation layer13as shown inFIG. 2A. A conductive layer54is disposed on the backside surface of the optical device11and penetrates the optical device11to be electrically connected to the electrical contacts or terminals of the optical device11. The conductive layer54is electrically connected to the conductive layer14disposed on the passivation layer13and the passivation layer55through a conductive via54v. In some embodiments, the conductive layer54defines an aperture54c(a hole or an opening). The aperture54cis at least partially surrounded by the passivation layer55and/or the optical device11. In some embodiments, the number of layers of the conductive layer and/or the passivation layer can be changed depending on different design specifications. For example, there may be N conductive layers covered by the passivation layer, where N is an integer equal to or greater than 1. As shown inFIG. 5, the optical device11and the electronic component21are also arranged side-by-side, and thus the effects or advantages of the semiconductor device package2A can be applicable to the semiconductor device package5inFIG. 5.

FIG. 6illustrates a cross-sectional view of a semiconductor device package6in accordance with some embodiments of the present disclosure. The semiconductor device package6inFIG. 6is similar to the semiconductor device package5inFIG. 5, and one of the differences therebetween is that the semiconductor device package5provides electrical connections for the optical device11and the electronic component21by solder balls16while the semiconductor device package6provides electrical connections for the optical device11and the electronic component21by bonding wires66. In some embodiments, the number of layers of the conductive layer and/or the passivation layer can be changed depending on different design specifications. For example, there may be N conductive layers covered by the passivation layer, where N is an integer equal to or greater than 1. As shown inFIG. 6, the optical device11and the electronic component21are also arranged side-by-side, and thus the effects or advantages of the semiconductor device package2A can be applicable to the semiconductor device package6inFIG. 6.

FIGS. 7A, 7B, 7C, 7D, 7E, and 7Fillustrate various stages of a semiconductor package manufacturing process, according to some embodiments of the present disclosure. In some embodiments, the operations illustrated inFIGS. 7A, 7B, 7C, 7D, 7E, and 7Fare used to manufacturing the semiconductor device package2inFIG. 2A. Alternatively, the operations illustrated inFIGS. 7A, 7B, 7C, 7D, 7E, and 7Fcan be used to manufacturing other semiconductor device packages.

Referring toFIG. 7A, a substrate strip including the substrate10is provided. In some embodiments, the substrate10is light transparent substrate, such as a glass substrate. Cavities10cand20care then formed from the surface101of the substrate10into the substrate10. The cavities10cand20care separated from each other. In some embodiments, the angle θ defined by the surface10c1and an extension surface of the surface10c2is greater than 0 degree and equal to or less than 90 degrees.

Referring toFIG. 7B, the optical device11is disposed within the cavity10cand the electronic component21is disposed within the cavity20c. In some embodiments, the optical device11and the electronic component21are disposed within the cavities10cand20cby, for example, pick-and-place or other suitable techniques. The optical device11and the electronic component21are respectively bonded to the surfaces10c2and20c1of the cavities10cand20cthrough the bonding layer (or the adhesive layer).

Referring toFIG. 7C, the passivation layer13is formed on the surface101of the substrate10and the cavities10c,20cto cover or encapsulate the optical device11and the electronic component21. In some embodiments, the passivation layer13can be formed by, for example, coating, molding, printing or any other suitable technique(s).

Referring toFIG. 7D, a plurality of openings14care formed to penetrate a portion of the passivation layer13. The openings14care also formed to penetrate a portion of the optical device11and the electronic component21to expose electrical contacts or terminals thereof. In some embodiments, the openings14ccan be formed by, for example, etching, drilling, laser drilling or any other suitable technique(s).

Referring toFIG. 7E, the conductive layer14(e.g., RDL) is formed on the passivation layer13and extends within the openings14cto be electrically connected to the exposed portion of the electrical contacts or terminals of the optical device11and the electronic component21. The passivation layer15is formed on the passivation layer13to cover or encapsulate the passivation layer13, the conductive layer14and the openings14c. One or more openings are then formed to expose a portion of the conductive layer14.

Referring toFIG. 7F, the electrical contacts16(e.g., solder balls) are disposed on the exposed portion of the conductive layer14to provide electrical connections between the optical device11or the electronic component21and other circuits, circuit boards or components. Then, a singulation may be performed to separate out individual semiconductor device packages including the semiconductor device package2. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting technique.

FIGS. 8A, 8B, 8C, 8D and 8Eillustrate various stages of a semiconductor package manufacturing process, according to some embodiments of the present disclosure. In some embodiments, the operations illustrated inFIGS. 8A, 8B, 8C, 8D and 8Eare used to manufacturing the semiconductor device package4inFIG. 4. Alternatively, the operations illustrated inFIGS. 8A, 8B, 8C, 8D and 8Ecan be used to manufacturing other semiconductor device packages.

Referring toFIG. 8A, a substrate strip including the substrate10is provided. In some embodiments, the substrate10is light transparent substrate, such as a glass substrate. Cavities10cand20care then formed from the surface101of the substrate10into the substrate10. The cavities10cand20care separated from each other. In some embodiments, the angle θ defined by the surface10c1and an extension surface of the surface10c2is greater than 0 degree and equal to or less than 90 degrees.

Referring toFIG. 8B, the passivation layer13is formed on the surface101of the substrate10and the surface10c1of the cavities10c,20c. In some embodiments, the passivation layer13can be formed by, for example, coating, molding, printing or any other suitable technique(s).

Referring toFIG. 8C, the conductive layer14(e.g., RDL) is formed on the passivation layer13and further extends on the surfaces10c2,20c1of the cavities10c,20c. The passivation layer15is formed on the conductive layer14. One or more openings are then formed to expose a portion of the conductive layer14.

Referring toFIG. 8D, the optical device11is disposed within the cavity10cand the electronic component21is disposed within the cavity20c. In some embodiments, the optical device11and the electronic component21are disposed within the cavities10cand20cby, for example, pick-and-place or other suitable techniques. The optical device11and the electronic component21are respectively connected to the exposed portions of the conductive layer14through the electrical contacts34(e.g., conductive pillars, solder balls or stub bumps).

Referring toFIG. 8E, the electrical contacts16(e.g., solder balls) are disposed on the exposed portion of the conductive layer14to provide electrical connections between the optical device11or the electronic component21and other circuits, circuit boards or components. Then, a singulation may be performed to separate out individual semiconductor device packages including the semiconductor device package4. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting technique.

FIGS. 9A, 9B, 9C, 9D and 9Eillustrate various stages of a semiconductor package manufacturing process, according to some embodiments of the present disclosure. In some embodiments, the operations illustrated inFIGS. 9A, 9B, 9C, 9D and 9Eare used to manufacturing the semiconductor device package5or6inFIG. 5orFIG. 6. Alternatively, the operations illustrated inFIGS. 9A, 9B, 9C, 9D and 9Ecan be used to manufacturing other semiconductor device packages. In some embodiments, the operation inFIG. 9Ais carried out subsequent to the operation inFIG. 7A(i.e., the formation of the cavities10c,20c).

Referring toFIG. 9A, an optical module90aand an electronic module90bare respectively disposed within the cavities10cand20c. The optical module90ais similar to the optical device11except that the optical module90afurther includes a conductive layer54and a passivation layer55. The conductive layer54is disposed on the backside surface of the optical device and penetrates the optical device to be electrically connected to the electrical contacts or terminals of the optical device. The passivation layer55is disposed on the backside surface of the optical device to cover a portion of the conductive layer54and expose another portion of the conductive layer54. Similarly, the electronic module90bis similar to the electronic component21except that the optical module90afurther includes a conductive layer and a passivation layer. The optical module90aand the electronic module90bare respectively bonded to the surfaces10c2and20c1of the cavities10cand20cthrough the bonding layer (or the adhesive layer).

Referring toFIG. 9B, the passivation layer13is formed on the surface101of the substrate10and the cavities10c,20cto cover or encapsulate the optical module90aand the electronic module90b. The top portion of the optical module90aand the electronic module90bare exposed from the passivation layer13. In some embodiments, the passivation layer13can be formed by, for example, coating, molding, printing or any other suitable technique(s).

Referring toFIG. 9C, the conductive layer14(e.g., RDL) is formed on the passivation layer13, the optical module90aand the electronic module90bto be electrically connected to the exposed portion of the conductive layer54of the optical module90aand the electronic module90b. The passivation layer15is formed on the passivation layer13to cover or encapsulate the passivation layer13and the conductive layer14. One or more openings are then formed to expose a portion of the conductive layer14.

Referring toFIG. 9D, the electrical contacts16(e.g., solder balls) are disposed on the exposed portion of the conductive layer14to provide electrical connections between the optical module90aor the electronic module90band other circuits, circuit boards or components. Then, a singulation may be performed to separate out individual semiconductor device packages including the semiconductor device package5. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting technique.

The operation inFIG. 9Eis carried out subsequent to the operation inFIG. 9C, the bonding wires66are formed on the exposed portion of the conductive layer14to provide electrical connections between the optical module90aor the electronic module90band other circuits, circuit boards or components. Then, a singulation may be performed to separate out individual semiconductor device packages including the semiconductor device package6. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting technique.

FIGS. 10A, 10B, 10C, 10D and 10Eillustrate various stages of a semiconductor package manufacturing process, according to some embodiments of the present disclosure. In some embodiments, the operation inFIG. 10Ais carried out subsequent to the operation inFIG. 7A(i.e., the formation of the cavities10c,20c).

Referring toFIG. 10A, the optical module90aand the electronic component21are respectively disposed within the cavities10cand20c. The optical module90ais similar to the optical device11except that the optical module90afurther includes a conductive layer54and a passivation layer55. The conductive layer54is disposed on the backside surface of the optical device and penetrates the optical device to be electrically connected to the electrical contacts or terminals of the optical device. The passivation layer55is disposed on the backside surface of the optical device to cover a portion of the conductive layer54and expose another portion of the conductive layer54. The optical module90aand the electronic component21are respectively bonded to the surfaces10c2and20c1of the cavities10cand20cthrough the bonding layer (or the adhesive layer).

Referring toFIG. 10B, the passivation layer13is formed on the surface101of the substrate10and the cavities10c,20cto cover or encapsulate the optical module90aand the electronic component21. The top portion of the optical module90aand electrical contacts of the electronic component21are exposed from the passivation layer13. In some embodiments, the passivation layer13can be formed by, for example, coating, molding, printing or any other suitable technique(s).

Referring toFIG. 10C, the conductive layer14(e.g., RDL) is formed on the passivation layer13, the optical module90aand the electronic module90bto be electrically connected to the exposed portion of the conductive layer54of the optical module90aand the electrical contacts of the electronic component21. The passivation layer15is formed on the passivation layer13to cover or encapsulate the passivation layer13and the conductive layer14. One or more openings are then formed to expose a portion of the conductive layer14.

Referring toFIG. 10D, the electrical contacts16(e.g., solder balls) are disposed on the exposed portion of the conductive layer14to provide electrical connections between the optical module90aor the electronic component21and other circuits, circuit boards or components. Then, a singulation may be performed to separate out individual semiconductor device packages including the semiconductor device package10. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting technique.

The operation inFIG. 10Eis carried out subsequent to the operation inFIG. 10C, the bonding wires66are formed on the exposed portion of the conductive layer14to provide electrical connections between the optical module90aor the electronic component21and other circuits, circuit boards or components. Then, a singulation may be performed to separate out individual semiconductor device packages including the semiconductor device package10′. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting technique.

FIG. 11Aillustrates a cross-sectional view of a semiconductor device package11ain accordance with some embodiments of the present disclosure. The semiconductor device package11ais similar to the semiconductor device package2inFIG. 2except that the semiconductor device package11afurther includes a protection layer110.

The protection layer110is disposed on the passivation layer15to cover the passivation layer and a portion of the electrical contact16and to expose the other portion of the electrical contact16. In some embodiments, the exposed portion of the electrical contact16is not coplanar with a surface1101of the protection layer110. For example, the electrical contact16protrudes from the surface1101of the protection layer110. The protection layer110is also disposed on a lateral surface103aof the substrate10that is recessed from a lateral surface103bof the substrate10. A lateral surface1102of the protection layer110is substantially coplanar with the lateral surface103bof the substrate10. In some embodiments, the protection layer110can be a molding compound (e.g., an epoxy molding compound or other molding compound). In some embodiments, the passivation layer15can be formed by light blocking materials or light absorbing material to prevent undesired light transmitting into the light receiving area of the optical device11.

When connecting an optical package on a circuit board or a substrate through electrical contacts (e.g., solder balls), the maximum strain/stress usually occurs at the contour (corners or edges) of the solder balls, which would cause some issues, such as crack, warpage and/or delamination. In some existing approaches, to reduce the strain/stress of the solder balls, an underfill may be used to cover/encapsulate the solder balls after connecting the optical package on the circuit board. However, the use of the underfill will increase the manufacturing time and cost. In accordance with the embodiments as shown inFIG. 11A, the protection layer110is disposed to cover a portion of the semiconductor device package11ato improve the robustness and to reduce the strain/stress, and thus no additional underfill is required when connecting the semiconductor device package11ato a circuit board or a substrate. In addition, the board level reliability (BLR) can be improved as well.

FIG. 11Billustrates a cross-sectional view of a semiconductor device package11bin accordance with some embodiments of the present disclosure. The semiconductor device package11bis similar to the semiconductor device package11ainFIG. 11Aexcept that inFIG. 11B, a surface161of the electrical contact16that is exposed from the protection layer110is substantially coplanar with the surface1101of the protection layer110.

FIG. 11Cillustrates a cross-sectional view of a semiconductor device package11cin accordance with some embodiments of the present disclosure. The semiconductor device package11cis similar to the semiconductor device package11ainFIG. 11Aexcept that inFIG. 11C, the protection layer110fully covers the lateral surface103aof the substrate10.

FIG. 12Aillustrates a cross-sectional view of a semiconductor device package12ain accordance with some embodiments of the present disclosure. The semiconductor device package12ais similar to the semiconductor device package4inFIG. 4except that the semiconductor device package12afurther includes a protection layer110. The protection layer110inFIG. 12Ais similar to the protection layer110inFIG. 11A, and thus the properties, the function and the effect achieved by the protection layer110inFIG. 11Acan be applicable toFIG. 12A.

FIG. 12Billustrates a cross-sectional view of a semiconductor device package12bin accordance with some embodiments of the present disclosure. The semiconductor device package12bis similar to the semiconductor device package12ainFIG. 12Aexcept that inFIG. 12B, a surface161of the electrical contact16that is exposed from the protection layer110is substantially coplanar with the surface1101of the protection layer110.

FIG. 12Cillustrates a cross-sectional view of a semiconductor device package12cin accordance with some embodiments of the present disclosure. The semiconductor device package12cis similar to the semiconductor device package12ainFIG. 12Aexcept that inFIG. 12C, the protection layer110fully covers the lateral surface103aof the substrate10.

FIG. 13Aillustrates a cross-sectional view of a semiconductor device package13ain accordance with some embodiments of the present disclosure. The semiconductor device package13ais similar to the semiconductor device package5inFIG. 5except that the semiconductor device package13afurther includes a protection layer110. The protection layer110inFIG. 13Ais similar to the protection layer110inFIG. 11A, and thus the properties, the function and the effect achieved by the protection layer110inFIG. 11Acan be applicable toFIG. 13A.

FIG. 13Billustrates a cross-sectional view of a semiconductor device package13bin accordance with some embodiments of the present disclosure. The semiconductor device package13bis similar to the semiconductor device package13ainFIG. 13Aexcept that inFIG. 13B, a surface161of the electrical contact16that is exposed from the protection layer110is substantially coplanar with the surface1101of the protection layer110.

FIG. 13Cillustrates a cross-sectional view of a semiconductor device package13cin accordance with some embodiments of the present disclosure. The semiconductor device package13cis similar to the semiconductor device package13ainFIG. 13Aexcept that inFIG. 13C, the protection layer110fully covers the lateral surface103aof the substrate10.

FIGS. 14A, 14B and 14Cillustrate various stages of a semiconductor package manufacturing process, according to some embodiments of the present disclosure. In some embodiments, the operation inFIG. 14Ais carried out after the operation inFIG. 7Fand before the singulation operation.

Referring toFIG. 14A, one or more cavities110care formed between two adjacent semiconductor device packages (one semiconductor device package may include an optical device11and an electronic component21) without cutting through the substrate10. In some embodiments, the cavities110cmay be formed by, dicing saw, laser or other appropriate technique.

Referring toFIG. 14B, the protection layer110is formed on the semiconductor device packages and within the cavities110c. The protection layer110covers a portion of the electrical contact16and exposes the other portion of the electrical contact16. In some embodiments, the protection layer110can be formed by, for example, wafer level molding (such as compression molding) or other appropriate technique.

Referring toFIG. 14C, a singulation is performed to separate out individual semiconductor device packages including the semiconductor device package11a. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting technique.

FIGS. 15A, 15B and 15Cillustrate various stages of a semiconductor package manufacturing process, according to some embodiments of the present disclosure. In some embodiments, the operation inFIG. 15Ais carried out after the operation inFIG. 14A.

Referring toFIG. 15A, the protection layer110is formed on the semiconductor device packages and within the cavities110c. The protection layer110fully covers the electrical contact16. In some embodiments, the protection layer110can be formed by, for example, wafer level molding (such as transfer molding), printing or other appropriate technique.

Referring toFIG. 15B, a grinding or planarization operation is carried out to remove a portion of the protection layer110and the electrical contact16to expose a portion of the electrical contact16.

Referring toFIG. 15C, a singulation is performed to separate out individual semiconductor device packages including the semiconductor device package11b. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting technique.

FIGS. 16A, 16B and 16Cillustrate various stages of a semiconductor package manufacturing process, according to some embodiments of the present disclosure. In some embodiments, the operation inFIG. 16Ais carried out after the operation inFIG. 8Eand before the singulation operation.

Referring toFIG. 16A, one or more cavities110care formed between two adjacent semiconductor device packages (one semiconductor device package may include an optical device11and an electronic component21) without cutting through the substrate10. In some embodiments, the cavities110cmay be formed by, dicing saw, laser or other appropriate technique.

Referring toFIG. 16B, the protection layer110is formed on the semiconductor device packages and within the cavities110c. The protection layer110covers a portion of the electrical contact16and exposes the other portion of the electrical contact16. In some embodiments, the protection layer110can be formed by, for example, wafer level molding (such as compression molding) or other appropriate technique.

Referring toFIG. 16C, a singulation is performed to separate out individual semiconductor device packages including the semiconductor device package12a. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting technique.

FIGS. 17A, 17B and 17Cillustrate various stages of a semiconductor package manufacturing process, according to some embodiments of the present disclosure. In some embodiments, the operation inFIG. 17Ais carried out after the operation inFIG. 16A.

Referring toFIG. 17A, the protection layer110is formed on the semiconductor device packages and within the cavities110c. The protection layer110fully covers the electrical contact16. In some embodiments, the protection layer110can be formed by, for example, wafer level molding (such as transfer molding), printing or other appropriate technique.

Referring toFIG. 17B, a grinding or planarization operation is carried out to remove a portion of the protection layer110and the electrical contact16to expose a portion of the electrical contact16.

Referring toFIG. 17C, a singulation is performed to separate out individual semiconductor device packages including the semiconductor device package12b. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting technique.

FIGS. 18A, 18B and 18Cillustrate various stages of a semiconductor package manufacturing process, according to some embodiments of the present disclosure. In some embodiments, the operation inFIG. 18Ais carried out after the operation inFIG. 9Dand before the singulation operation.

Referring toFIG. 18A, one or more cavities110care formed between two adjacent semiconductor device packages (one semiconductor device package may include an optical device11and an electronic component21) without cutting through the substrate10. In some embodiments, the cavities110cmay be formed by, dicing saw, laser or other appropriate technique.

Referring toFIG. 18B, the protection layer110is formed on the semiconductor device packages and within the cavities110c. The protection layer110covers a portion of the electrical contact16and exposes the other portion of the electrical contact16. In some embodiments, the protection layer110can be formed by, for example, wafer level molding (such as compression molding) or other appropriate technique.

Referring toFIG. 18C, a singulation is performed to separate out individual semiconductor device packages including the semiconductor device package13a. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting technique.

FIGS. 19A, 19B and 19Cillustrate various stages of a semiconductor package manufacturing process, according to some embodiments of the present disclosure. In some embodiments, the operation inFIG. 19Ais carried out after the operation inFIG. 18A.

Referring toFIG. 19A, the protection layer110is formed on the semiconductor device packages and within the cavities110c. The protection layer110fully covers the electrical contact16. In some embodiments, the protection layer110can be formed by, for example, wafer level molding (such as transfer molding), printing or other appropriate technique.

Referring toFIG. 19B, a grinding or planarization operation is carried out to remove a portion of the protection layer110and the electrical contact16to expose a portion of the electrical contact16.

Referring toFIG. 19C, a singulation is performed to separate out individual semiconductor device packages including the semiconductor device package13b. The singulation may be performed, for example, by using a dicing saw, laser or other appropriate cutting technique.

In the description of some embodiments, a component provided “on” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component.

In the description of some embodiments, a component characterized as “light transmitting” or “transparent” can refer to such a component as having a light transmittance of at least 80%, such as at least 85% or at least 90%, over a relevant wavelength or a relevant range of wavelengths, such as a peak infrared wavelength or a range of infrared wavelengths emitted by a light emitter. In the description of some embodiments, a component characterized as “light shielding,” “light blocking,” or “opaque” can refer to such a component as having a light transmittance of no greater than 20%, such as no greater than 15% or no greater than 10%, over a relevant wavelength or a relevant range of wavelengths, such as a peak infrared wavelength or a range of infrared wavelengths emitted by a light emitter.

Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It can be understood that such range formats are used for convenience and brevity, and should be understood flexibly to include not only numerical values explicitly specified as limits of a range, but also all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.