Solid-state imaging apparatus having a sealing portion to reduce water invasion into the plurality of pixels and the peripheral circuit in a first member and a second member and method for manufacturing the solid-state imaging apparatus

A solid-state imaging apparatus includes a first substrate that includes a plurality of photoelectric conversion units, a second substrate that includes at least a part of a readout circuit configured to read signals based on electric charges of the plurality of photoelectric conversion units and a peripheral circuit including a control circuit, and a wiring structure that is disposed between the first substrate and the second substrate and includes a pad portion electrically connected to the peripheral circuit via a draw-out wiring and an insulating layer. The wiring structure has, at least at a part thereof, a seal ring disposed in such a way as to surround the photoelectric conversion units and the peripheral circuit.

TECHNICAL FIELD

The present invention relates to a solid-state imaging apparatus which is formed by laminating a plurality of members.

BACKGROUND ART

As a representative configuration of a solid-state imaging apparatus, it is conventionally known to form photoelectric conversion units on one substrate and form peripheral circuit portions on another substrate, and then electrically connect these members with micro bumps.

A backside illumination type solid-state imaging apparatus discussed in Japanese Patent Application Laid-Open No. 2009-170448 includes a first semiconductor substrate on which a photoelectric conversion unit and a readout circuit for reading a signal are provided to constitute each pixel, and a second semiconductor substrate on which a peripheral circuit that processes a signal read from the pixel is provided. The first semiconductor substrate and the second semiconductor substrate are laminated with each other.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

A general semiconductor substrate, which includes various circuits, is required to have the capability of protecting internal elements against water and ions entering from an external environment surrounding the semiconductor substrate. Hence, in a solid-state imaging apparatus including the first semiconductor substrate and the second semiconductor substrate as discussed in Japanese Patent Application Laid-Open No. 2009-170448, it is necessary to protect the internal components from water and ions entering from the ambient environment.

The present invention relates to a solid-state imaging apparatus having improved moisture resistance.

Solution to Problem

According to an aspect of the present invention, a solid-state imaging apparatus includes a plurality of pixels each of which includes a photoelectric conversion unit and a readout circuit configured to process a signal generated by the photoelectric conversion unit or configured to read the signal, and a peripheral circuit configured to read signals from the plurality of pixels. The plurality of photoelectric conversion units is disposed in a first member, and at least a part of the readout circuit and the peripheral circuit are disposed in a second member. The first member and the second member are bonded in such a way that a signal from the photoelectric conversion unit can be received by the readout circuit disposed in the second member. The solid-state imaging apparatus includes a sealing portion configured to reduce water invasion from an outside region of the solid-state imaging apparatus into the plurality of pixels and the peripheral circuit, wherein the sealing portion includes a first sealing portion disposed in the first member and a second sealing portion disposed in the second member, and a part of the first sealing portion is in contact with a part of the second sealing portion.

Advantageous Effects of Invention

The present invention can provide a solid-state imaging apparatus capable of protecting internal elements, for example, from water that may enter from an external environment.

DESCRIPTION OF EMBODIMENTS

The present invention is described below in detail with reference to attached drawings. In the following description of exemplary embodiments, one principal plane of a first substrate and one principal plane of a second substrate are substrate surfaces on which photoelectric conversion units or transistors are disposed. An opposite side of the principal plane is referred to as a backside of the first substrate and the second substrate respectively. Further, in the following description, a direction from the backside of each substrate to the principal plane thereof is referred to as an upward direction. A direction from the principal plane of the substrate to the backside thereof is referred to as a downward direction or a depth direction.

In the present invention, a seal ring is described as an example of a sealing portion provided to reduce water invasion from the outside. However, the shape of the sealing portion is not limited to the ring shape. Any other sealing members having appropriate moisture resistant property can be used.

A first exemplary embodiment of the present invention is described below with reference toFIGS. 1A and 1BthoughFIGS. 8A to 8C.

FIGS. 1A and 1Billustrate a solid-state imaging apparatus according to the first exemplary embodiment.FIG. 1Ais a perspective view illustrating the solid-state imaging apparatus.FIG. 1Bis a plan view illustrating the solid-state imaging apparatus illustrated inFIG. 1A, which is seen from a light incidence side thereof. As illustrated inFIG. 1A, the solid-state imaging apparatus according to the present exemplary embodiment includes a first member308and a second member309that cooperatively form a laminated structure. The first member308includes a first substrate. The second member309includes a second substrate. A wiring structure is disposed between the first substrate and the second substrate. It is desired that the wiring structure is constituted by a plurality of wiring layers. In the following description, each constituent component located on the first member308is suffixed with “A”, and each constituent component located on the second member309is suffixed with “B.”

The first member308and the second member309are sequentially positioned from the light incidence side of the solid-state imaging apparatus.FIG. 1Billustrates the first member308at the left half thereof and illustrates the second member309(i.e., a state where the first member308is omitted) at the right half thereof. The right half, where the first member308is not illustrated, can be arranged in the same manner as the left half.

The solid-state imaging apparatus illustrated inFIGS. 1A and 1Bincludes pixel portions301A and301B. A plurality of photoelectric conversion units, each corresponding to a pixel, is disposed on the pixel portion301A. A microlens118can condense incidence light to each photoelectric conversion unit. Each peripheral circuit120includes various circuits configured to read signals from the pixel portion301. A main part of the peripheral circuit120is located on the second member309. A part of the peripheral circuit120can be located on the first member308.

A plurality of pads313is disposed on a pad portion312A. The plurality of pads313can include input pads and output pads (hereinafter, simply referred to as “pads”) to input and output signals from and to external circuits. Each pad313can be constituted, for example, by a conductive pattern that forms a part of the wiring structure. In general, the conductive pattern that forms the wiring is surrounded by an insulating member. To provide electrical connection between the pads and the external circuits, openings100are formed on the insulating member on the pads.

A plurality of seal rings150A,151A,152A, and150B is provided to reduce water from entering inside the device. The seal ring150A is disposed along the outermost periphery of the first member308. The seal ring152A is positioned inside the seal ring150A and is disposed between the pad portion312A and the pixel portion301A. The seal ring151A is disposed in such a way as to surround each pad313disposed on the pad portion312A. The seal ring150B is disposed along the outermost periphery of the second member309.

More specifically, the first member308has a first sealing portion that includes the seal rings150A to152A. The second member has a second sealing portion that includes the seal ring150B. Each seal ring can protect the corresponding member from water invasion entering from the outside. As described below, a part of the first sealing portion is in contact with a part of the second sealing portion. More specifically, a surface of the first sealing portion that faces the second member309is in contact with a surface of the second sealing portion that faces the first member308.

The seal rings are described below in more detail. Each seal ring according to the present invention can be classified into one of the following four types depending on its arrangement. In the following exemplary embodiments, sealing portions are an appropriate combination of the following four types of seal rings.

First, the seal rings that belong to a first classification includes a seal ring disposed along the outermost periphery of each member, such as the seal rings150A and150B described in the following exemplary embodiments. The seal rings150A and150B are positioned outside the pixel portion, the peripheral circuit portion, and the pad portion in each member.

The seal rings that belong to a second classification include a seal ring disposed along the periphery of each pad disposed on the pad portion in such a way as to surround the pad, such as the seal rings151A and151B described in the following exemplary embodiments.

The seal rings that belong to a third classification include a seal ring disposed between the pad portion and the pixel portion or between the pad portion and the peripheral circuit portion, such as the seal rings152A and152B described in the following exemplary embodiments.

The seal rings that belong to a fourth classification include a sealing portion constituted by an insulating member disposed on a contact surface where two members are laminated and bonded. A passivation layer is functionally operable as a sealing portion belonging to the fourth classification. More specifically, the passivation layer can be made of a material containing SiN or SiON, each of which has high moisture-absorption characteristics compared to a material containing SiO2 and thus shows excellent sealing property.

In the present invention, the seal rings belonging to the above-described four classifications can be appropriately combined to form sealing portions. More specifically, the first sealing portion disposed in the first member is brought into contact with the second sealing portion disposed in the second member to constitute a sealing portion. To enhance the sealing properties, among the sealing portions disposed on respective members, it is desired to bring seal rings that belong to the same classification into contact with each other.

Next, an equivalent circuit diagram of the solid-state imaging apparatus according to the first exemplary embodiment is described below with reference toFIG. 2. In the present exemplary embodiment, signal charges are electrons. A solid-state imaging apparatus300illustrated inFIG. 2includes a pixel portion301on which a plurality of pixels is arranged. Each pixel includes a photoelectric conversion unit and a readout circuit for processing or reading a signal generated from the photoelectric conversion unit. Further, the solid-state imaging apparatus300includes a peripheral circuit portion302provided to read signals from the plurality of pixels. A plurality of peripheral circuits120(seeFIG. 1B) is disposed on the peripheral circuit portion302.

The pixel portion301is constituted by a plurality of portions, each including a photoelectric conversion unit303, a transfer transistor304, an amplifying transistor306, and a reset transistor307. A structure including one photoelectric conversion unit303is referred to as a pixel. One pixel according to the present exemplary embodiment includes the photoelectric conversion unit303, the transfer transistor304, the amplifying transistor306, and the reset transistor307. A source of the transfer transistor304is connected to the photoelectric conversion unit303. A drain of the transfer transistor304is connected to a gate of the amplifying transistor306. A node305represents the gate of the amplifying transistor306.

A source of the reset transistor307is connected to the node305to set an electric potential of the node305to an arbitrary value (e.g., a reset potential). It is configured that a reset voltage can be applied to a drain of the reset transistor307. In the present exemplary embodiment, the amplifying transistor306is a part of a source follower circuit and is configured to output a signal representing the electric potential of the node305to a signal line RL. The node305can be configured to include a floating diffusion.

A plurality of peripheral circuits is disposed on the peripheral circuit portion302. For example, the peripheral circuit portion302includes a vertical scanning circuit VSR that can supply a control signal to a gate of a transistor provided on the pixel portion301and a readout circuit RC that can perform signal processing, such as amplification, addition, or analog-to-digital (AD) conversion, on a signal output from the pixel portion301. Further, the peripheral circuit portion302includes a horizontal scanning circuit HSR that can supply pulses to the readout circuit RC to output signals successively from the readout circuit RC.

In the solid-state imaging apparatus according to the first exemplary embodiment, the plurality of photoelectric conversion units303is disposed on the first member308. At least a part of the readout circuit of the pixel and the peripheral circuit are disposed on the second member309. More specifically, the photoelectric conversion unit303and the transfer transistor304constitute the pixel portion301A disposed on the first member308. The remaining constituent elements of the pixel constitute the pixel portion disposed on the second member309. The arrangement of the transistors that constitute each pixel portion of the first substrate and the second substrate is not limited to the above-described configuration and can be appropriately modified considering situations.

A connecting portion310is a node for electrically connecting a gate of the transfer transistor304located on the first substrate to the peripheral circuit120disposed on the second member. A practical configuration of the connecting portion310is described below.

The electric charge generated by the photoelectric conversion unit303can be read at the drain of the transfer transistor304, i.e., the node305. The node305can include the configuration provided on the first member308and the configuration provided on the second member309. More specifically, the configuration included in the first member308is a floating diffusion and a part of a first wiring structure electrically connected to the floating diffusion. The configuration included in the second member309is the source of the reset transistor307, the gate of the amplifying transistor306, and a part of the second wiring structure that electrically connects these terminals to a part of the first wiring structure.

When the above-described configuration is employed, the area of each photoelectric conversion unit303can be increased and the sensitivity can be improved, compared to a conventional circuit arrangement in which the pixel portion and the peripheral circuit portion are entirely arranged on one member (i.e., one substrate). Further, compared to the conventional configuration, if the area of the photoelectric conversion unit remains the same, a greater number of photoelectric conversion units303can be provided and it is useful to realize a multiple pixel arrangement. Further, a part of the first wiring structure of the first member308and a part of the second wiring structure of the second member309can cooperatively constitute a sealing portion that can reduce water invasion from the outside of the solid-state imaging apparatus.

A practical plan view layout of the solid-state imaging apparatus is described below with reference to schematic plan views of the solid-state imaging apparatus illustrated inFIGS. 3A and 3B.FIG. 3Ais a top view illustrating a plan view layout of the first member308.FIG. 3Bis a top view illustrating a plan view layout of the second member309. Portions whose functions are similar to those illustrated inFIGS. 1A,1B and2are denoted by the same reference numerals and their descriptions are not repeated.

InFIG. 3A, the first member308includes the pixel portion301A on which a plurality of photoelectric conversion units303is disposed and the pad portion312A on which a plurality of pads313is disposed. More specifically, a plurality of photoelectric conversion units303and a plurality of transfer transistors304are disposed on the pixel portion301A. Further, a plurality of connecting portions314A for being electrically connected to the second member309and the corresponding pads313are disposed at the same positions when seen from the top. The connecting portion can be constituted by a conductive pattern that is formed in the same layer as a wiring layer included in the wiring structure.

If the pad313is used as an input pad, a signal or a power source voltage input via the pad313is supplied to a circuit of the second member309via the corresponding connecting portion314A. If the pad313is used as an output pad, a signal from the second member309is transmitted to the pad313via the corresponding connecting portion314A. The pads include electrode pads which are electrically connected to external circuits and disposed on the wiring layer, and electrode pads which are connected to through electrodes that extend from one surface of a semiconductor substrate to the other surface thereof.

Next, as illustrated inFIG. 3B, the pixel portion301B, a peripheral circuit portion302B, and a pad portion312B are provided on the second member309. The pad portion312B is an area in which pads themselves are not disposed but a conductive pattern to be electrically connected to the pads313on the second member309is disposed. Transistors that constitute the readout circuits of the pixel are disposed on the pixel portion301B. For example, a plurality of amplifying transistors306and a plurality of reset transistors307illustrated inFIG. 2are disposed on the pixel portion301B.

The horizontal scanning circuits HSR, the vertical scanning circuits VSR, and the readout circuits RC are disposed on the peripheral circuit portion302. Connecting portions314B are disposed on the pad portion312B so that the connecting portions314B can be connected to the corresponding connecting portions314A disposed on the first member308. The horizontal scanning circuits HSR, the vertical scanning circuits VSR, and the readout circuits RC are electrically connected to corresponding connecting portions314B via draw-out wirings316.

The first member308and the second member309, whose plan view layouts are illustrated inFIG. 3AandFIG. 3B, are separate examples of the two laminated members that constitute the solid-state imaging apparatus according to the present exemplary embodiment illustrated inFIGS. 1A and 1B. More specifically, the pixel portion301A and the pixel portion301B are disposed so as to overlap with each other. Further, the connecting portions314A are electrically connected to the connecting portions314B.

The peripheral circuit portion302A illustrated inFIG. 3Ais an area of the first member308that corresponds to the peripheral circuit portion302B of the second member309B illustrated inFIG. 3B. A part of the scanning circuit can be disposed on the peripheral circuit portion302A. Alternatively, no circuit element can be disposed on the peripheral circuit portion302A. As roles allocated to the first member308and the second member309, the first member308includes at least the photoelectric conversion units, and the second member309includes at least a part of the pixel readout circuits or the peripheral circuits.

Next, sealing portions of the first member308are described below. The following description is based on an arrangement of the sealing portions vertically projected on a first substrate101from the second member309side. The seal ring150A is disposed along the outermost periphery of the first member308. In the present exemplary embodiment, the outermost periphery is, for example, a boundary indicating an external area where no circuit element is disposed or no conductive pattern is disposed. Further, the seal ring151A is disposed so as to surround each of the plurality of pads313, which are provided around the pixel portion301.

The seal ring151A can be electrically connected to the pad313and to a semiconductor area disposed on the first substrate101. An electrostatic destruction protection circuit can be formed to include the semiconductor area to which the seal ring151A is connected. A protection diode can be used as an example element for the electrostatic destruction protection circuit. The seal ring151A can reduce water invasion through each pad opening100. Further, the seal ring151A can eliminate the influence of external noises.

The seal ring152A is disposed between the pad portion312A and the pixel portion301. When the seal ring151A is employed, it is desired that the seal ring152A is disposed between an edge portion of the seal ring151A positioned on the pixel portion side and the pixel portion301. It is desired that the seal ring152A can surround the pixel portion301.

Next, sealing portions of the second member309are described below. The following description is based on an arrangement of the sealing portions vertically projected on a second substrate121from the first member308.

The seal ring150B of the second member309is disposed along the outermost periphery of the second member309. If a plurality of draw-out wirings316is provided for electrical connection between each peripheral circuit120and a corresponding connecting portion314B, it is desired that the seal ring150B is located outside the plurality of draw-out wirings316. As illustrated, it is desired that the seal ring150B is disposed to surround the plurality of draw-out wirings316. In a case where the pads313are disposed on the pad portions312B of the second member309, a seal ring151B (not illustrated) that is disposed in the same manner as the seal ring151A of the first member308can be provided.

The positional relationship between the seal rings on the first member308and the second member309, in a state where the first member308and the second member309are laminated, can be in an overlapped relationship or in a non-overlapped relationship. In particular, if a passivation layer is provided on the surface side of the wiring structure, it is unnecessary to dispose the seal rings of the first and second members in an overlapped fashion because the passivation layer constitutes a part of the sealing portion. In this case, it is desired that the passivation layer is constituted by a material having excellent moisture-absorption characteristics compared to other insulating film that constitutes the wiring structure. A practical material for the passivation layer is a material containing nitrogen, such as SiN or SiON, components.

Further, if the seal rings, which are constituted by electric conductors, of the first member308and the second member309are arranged to come into contact with each other, moisture resistance can be improved and reliability can be improved. Further, in a case where the seal rings (electric conductors) of the first and second members are brought into contact with each other and continuously integrated as a sealing portion, the seal rings can suppress a chipping range from increasing when a wafer of the first member308and a wafer of the second member309are bonded together and then subjected to dicing. Further, the yield rate and the reliability can be improved.

FIG. 4is a schematic cross-sectional view taken along a line X-X′ illustrated inFIG. 1B. The solid-state imaging apparatus, which has the circuit illustrated inFIG. 2and the plan view layouts illustrated inFIGS. 3A and 3B, is described below with reference toFIG. 4. InFIG. 4, constituent components similar to those illustrated inFIG. 1AtoFIG. 3Bare denoted by the same reference numerals and their descriptions are not repeated.

The solid-state imaging apparatus according to the present exemplary embodiment includes the first substrate, the second substrate, and the wiring structure disposed between the first substrate and the second substrate. It is desired that the first substrate is a semiconductor substrate that is included in the first member308. It is desired that the second substrate is a semiconductor substrate that is included in the second member309.

It is desired that the wiring structure is a multi-layered structure constituted by a plurality of wiring layers with each intervening insulating layer. Further, as an example configuration of the wiring structure, the first member308can include the first wiring structure and the second member309can include the second wiring structure. In this case, each of the first wiring structure and the second wiring structure can be configured to have a multilayered structure constituted by a plurality of wiring layers with each intervening insulating layer. As another example configuration of the wiring structure, only one of the first member and the second member can be configured to have a wiring structure.

The first member308includes the first wiring structure, which includes at least the insulating layer and the wiring layer, and the first substrate101. The first substrate101is, for example, a semiconductor substrate that includes a principal plane102and a backside103. The first substrate101according to the present exemplary embodiment is an n-type silicon semiconductor substrate. The photoelectric conversion unit303is disposed on the principal plane102of the first substrate.

The first wiring structure includes interlayer insulating films104to106and a gate electrode layer107including a gate electrode and a gate wiring. Further, the first wiring structure includes wiring layers109and111including a plurality of wirings and plug layers108and110including a plurality of contact plugs or via plugs. The interlayer insulating film106is a passivation layer that is disposed on the topmost surface of the first wiring structure. In the present exemplary embodiment, the passivation layer (i.e., the interlayer insulating film106) is an insulating film containing SiN components.

An n-type semiconductor area112, which constitutes the photoelectric conversion unit303, and an n-type semiconductor area114, which is a drain of a transfer transistor, in other words, a floating diffusion, are disposed on the first substrate101. Further, an element isolation structure119is disposed on the first substrate101. The element isolation structure119can be constituted by an insulating member. Alternatively, a PN junction isolation structure can be employed instead of the insulating member. Further, it is feasible to employ both the insulating member and the PN junction isolation structure.

The transfer transistor304can be constituted by the n-type semiconductor area112, the n-type semiconductor area114, and a gate electrode113included in the gate electrode layer107. In response to a driving pulse supplied to the gate electrode113, electric charge of the n-type semiconductor area112can be transferred to the n-type semiconductor area114. The electric potential based on the electric charge having been transferred to the n-type semiconductor area114can be transmitted to the second member309via the plug layer108, the wiring layer109, the plug layer110, and the wiring layer111.

A part of the conductive pattern included in the wiring layer111constitutes a connecting portion311A. The photoelectric conversion unit303is appropriately changeable. For example, the photoelectric conversion unit303can be constituted by an embedded photodiode that includes a p-type semiconductor area provided on the light-receiving surface side, or can be constituted by a photogate.

A planarization layer115, a color filter layer116including a plurality of color filters, a planarization layer117, and a microlens layer118including a plurality of microlenses are disposed in this order on the backside103of the first substrate101, at a portion corresponding to the pixel portion301A. Each of the plurality of color filters and each of the plurality of microlenses illustrated inFIG. 4are disposed to correspond to one photoelectric conversion unit, i.e., disposed for each pixel. However, each of the color filters and each of the microlenses can be provided commonly for a plurality of pixels. The solid-state imaging apparatus according to the present exemplary embodiment can be referred to as a backside illumination type solid-state imaging apparatus which is configured to receive incoming light via the microlens layer118by the photoelectric conversion unit.

The pads313and the openings100, via which the pads313are exposed, are disposed on the pad portion312A of the first member308. Further, the connecting portions314A electrically connected to the pads313are disposed on the pad portion312A. The connecting portions314A can be constituted by the conductive pattern included in the wiring layer111.

A part of the first wiring structure of the first member308constitutes seal rings. The seal rings150A,151A, and152A can be formed by a conductive pattern that is manufactured in the same process as that of the wiring layers and plug layers.

An area of the first substrate101where the seal ring150A is vertically projected from the second member309is disposed along the outermost periphery of the first member. Accordingly, an area of the first substrate where the plurality of photoelectric conversion units is disposed, i.e., the pixel portion301A, is positioned inside the area where the seal ring150A is projected. The seal ring150A is positioned outside the pixel portion301A and the pad portion312A and entirely surrounds them.

An area of the first substrate101where the seal ring152A is vertically projected from the second member309is positioned between the pixel portion302and the pad portion312A. Further, it is desired that the seal ring152A can surround the pixel portion301A.

It will be easier to understand the above-described arrangements and positional relationships with reference toFIG. 4andFIG. 3A. The seal rings150A and152A are disposed in such a way as to extend from the principal plane102of the first substrate101to an opposite surface of the interlayer insulating film106that does not face the first substrate101. In other words, the seal rings150A and152A have a structure including an electric conductor continuously extending from the semiconductor substrate to a surface of the interlayer insulating film106that is functionally operable as a passivation film and contacts the second member309.

In the present exemplary embodiment, the seal ring151A is disposed so as to surround each pad313disposed on the pad portion312A.

Providing at least one of the seal rings150A and152A is effective to secure appropriate moisture resistance because a water invasion path extending from an edge portion of the solid-state imaging apparatus or a pad opening to an internal element of the solid-state imaging apparatus becomes narrower.

Further, the electric potential of the substrate can be supplied to each seal ring via, for example, semiconductor areas114′ and112′, which are disposed on the first substrate101and are similar to the first substrate101in conduction type. When the above-described configuration is employed, adverse influences of exogenous noises can be suppressed.

The second member309includes the second wiring structure and the second substrate121. The second substrate121is, for example, a semiconductor substrate that includes a principal plane122and a backside123. Transistors are disposed on the principal plane122of the second substrate. The second wiring structure includes interlayer insulating films124to127, a gate electrode layer128including a gate electrode and a wiring, wiring layers130,132, and134including a plurality of wirings, and plug layers129,131, and133including a plurality of contacts or via plugs.

A conductive pattern included in the wiring layer134, which is an uppermost wiring layer, includes a portion electrically connected to the first member308. The interlayer insulating film127is a passivation layer that is disposed on the topmost surface of the second wiring structure. In the present exemplary embodiment, the passivation layer can be formed by a material containing nitrogen, such as SiN or SiON, components.

Disposed on the pixel portion301B of the second substrate121are a p-type semiconductor area135that provides a channel of the amplifying transistor306, an n-type source area of the amplifying transistor306, a drain area138, and an element isolation structure136. The amplifying transistor306is constituted by a gate electrode137included in the gate electrode layer128, a source area, and the drain area138.

In the present exemplary embodiment, the connecting portion311A of the first member308is electrically connected to the gate electrode137of the amplifying transistor via the wiring layer134, the plug layer133, the wiring layer132, the plug layer131, the wiring layer130, and the plug layer129. In the present exemplary embodiment, the node305illustrated inFIG. 2is configured to include the n-type semiconductor area114, the wirings of the wiring layers109,111,134,132, and130, the contact plugs or via plugs of the plug layers108,110,133,131, and129, and the gate electrode137illustrated inFIG. 4. The remaining circuit (e.g., reset transistors) of the pixel portion301B is not illustrated.

The horizontal scanning circuit HSR and the vertical scanning circuit VSR are disposed on the peripheral circuit portion302of the second member309.FIG. 4illustrates an n-type transistor and a p-type transistor, which constitute an arbitrary circuit included in the peripheral circuit portion302. The n-type transistor is configured to include a gate electrode140included in the gate electrode layer128, an n-type source area disposed in a P-type semiconductor area139, and a drain area141. The p-type transistor is configured to include a gate electrode143included in the gate electrode layer128, a p-type source area disposed in an n-type semiconductor area142, and a drain area144.

The seal ring150B can be constituted by a part of the wiring layers and the plug layers that constitute the second wiring structure. An area of the second substrate121where the seal ring150B is vertically projected from the first member308is positioned along the outermost periphery of the second member309. Alternatively, the above-described area can be positioned outside the peripheral circuit portion302that includes various peripheral circuits. It will be easier to understand the above-described arrangements and positional relationships with reference toFIG. 4andFIG. 3B.

The seal ring150B is disposed in such a way as to extend from the principal plane122of the second substrate121to an opposite surface of the interlayer insulating film127that does not face the second substrate121. The interlayer insulating film127functions as a passivation film. In other words, the seal ring150B has a structure including an electric conductor continuously extending from the semiconductor substrate to a surface of the interlayer insulating film106that contacts the first member308. The interlayer insulating film106functions as a passivation film.

As illustrated inFIG. 4, the seal ring150A is in contact with the seal ring150B. More specifically, a conductive pattern of the wiring layer111that constitutes the topmost surface of the seal ring150A, which is positioned on the second member309side, is in contact with a conductive pattern of the wiring layer134that constitutes the topmost surface of the seal ring150B, which is positioned on the first member308side.

The electric potential of the substrate can be supplied to the seal ring150B via semiconductor areas138′ and139′ which are disposed on the second substrate121and are similar to the second substrate121in conduction type. Thus, when the seal ring150B is employed, adverse influences of exogenous noises can be suppressed.

The first member308and the second member309are assembled in such a manner that the principal plane102of the first substrate101faces to the principal plane122of the second substrate121(face-to-face arrangement), and constitute the solid-state imaging apparatus.

Thus, the above-described configuration can reduce water from invading into the element area including the pixel portion301A of the first member308, and the pixel portion301B and the peripheral circuit portion302B of the second member309.

Further, as exposure surfaces of respective pads313are disposed on the backside of the first member308, it becomes easier to assure electrical connection between external circuits and the pads313. Therefore, the above-described arrangement can reduce contact defectiveness.

Here, a modified example of the solid-state imaging apparatus illustrated inFIG. 4is described below with reference to schematic cross-sectional views ofFIG. 5AandFIG. 5B. A solid-state imaging apparatus illustrated inFIG. 5Ais different from the solid-state imaging apparatus illustrated inFIG. 4in that insulating layers106′ are disposed on the topmost surfaces of the first and second wiring structures. The function of the insulating layer106′ as a passivation layer is lower compared to that of a material containing SiN components. The remaining portions that are functionally similar to the constituent components illustrated inFIG. 4are denoted by the same reference numerals and their descriptions are not repeated.

Further, the configuration illustrated inFIG. 5Adoes not include the seal ring152A. Even in this case, the seal ring151A can secure satisfactory moisture resistance. The solid-state imaging apparatus illustrated inFIG. 5Aincludes the seal rings150A and150B. Thus, the above-described configuration can reduce the possibility of water invasion from the topmost surfaces of the first and second members308and309that may occur in a case where no passivation layer is provided.

Next, a solid-state imaging apparatus illustrated inFIG. 5Bis described below. The solid-state imaging apparatus illustrated inFIG. 5Bis different from the solid-state imaging apparatus illustrated inFIG. 4in that both of the seal rings150A and151A are omitted. Further, interlayer insulating films106′ and127′ which function as passivation layers are disposed in such a way as to constitute the topmost surfaces of the first and second members308and309respectively. The solid-state imaging apparatus illustrated inFIG. 5Bincludes the seal rings152A and150B.

When the above-described structure is employed, the conductive pattern of the first member308and the conductive pattern of the second member309constitute a part of the sealing portion while the conductive patterns provide an electrical connection between the pads313and the second member309. The above-described configuration can reduce water invasion via a cross-sectional area of the first wiring structure at each pad opening100. Each seal ring has a multi-layered structure of conductive patterns which are formed by a material similar to the wiring layers and the plug layers included in the wiring structures.

Next, an example method for manufacturing the solid-state imaging apparatus illustrated inFIG. 4according to the present exemplary embodiment is described below with reference toFIGS. 6A to 8C.FIGS. 6A and 6Bare cross-sectional views schematically illustrating manufacturing processes of the first member308.FIGS. 7A and 7Bare cross-sectional views schematically illustrating manufacturing processes of the second member309.FIGS. 8A to 8Care cross-sectional views schematically illustrating manufacturing processes after the first member308and the second member309are bonded.

The manufacturing processes of the first member308illustrated inFIG. 4are described below with reference toFIGS. 6A and 6B. InFIGS. 6A and 6B, a configuration308′ is an unfinished portion to be later completed as the first member308illustrated inFIG. 4. Circuit element regions301′,302′, and312′ are unfinished portions to be later completed as the pixel portion301, the peripheral circuit portion302, and the pad portion312, as illustrated inFIG. 4. Seal ring regions150A′,151A′, and152A′ are unfinished portions to be later completed as the seal rings150A,151A, and152A.

In the manufacturing processes of the first member308according to the present exemplary embodiment, first a semiconductor substrate401is prepared and elements are formed on the semiconductor substrate401. The semiconductor substrate401includes a principal plane402and a backside403. The semiconductor substrate401has a thickness of D3. The material chiefly constituting the semiconductor substrate401is a silicon material.

The element isolation structure119is formed on the semiconductor substrate401. The element isolation structure119is, for example, a local oxidation of silicon (LOCOS) or shallow trench isolation (STI) structure that includes an insulating member. Alternatively, the element isolation structure119can be a structure that includes a PN junction isolation structure or a combination of an insulating member and the PN junction isolation structure. A semiconductor area (not illustrated) that functions as P-type and N-type wells is formed on the semiconductor substrate401. Then, the n-type semiconductor areas112and114that constitute a photoelectric conversion unit are formed. Further, n-type semiconductor areas112′ and114′ that are electrically connected to electric conductors constituting the seal rings are formed. The n-type semiconductor areas112′ and114′ can be configured to be similar to the substrate in conduction type.

Next, the gate electrode layer107is formed. The gate electrode layer107is, for example, a polysilicon-made member, and can include not only a gate electrode but also a wiring. In the present exemplary embodiment, general semiconductor processes are employable to form the gate electrode and the element isolation and semiconductor areas, although detailed description thereof is omitted. When the above-described manufacturing processes have been thoroughly finished, the configuration illustrated inFIG. 6Acan be obtained.

The manufacturing processes further include forming a first wiring structure321on the principal plane of the semiconductor substrate401. The first wiring structure321includes the interlayer insulating films104,105, and106, the plug layers108and110, and the wiring layers109and111. In the present exemplary embodiment, the interlayer insulating films can be constituted by silicon dioxide films, silicon nitride films, or organic resin films. The wiring layers can be constituted by wirings chiefly containing aluminum components or electric conductors chiefly containing copper components.

The interlayer insulating film106which is the topmost interlayer insulating film functions as a passivation film and can be constituted by a silicon oxynitride film or a silicon nitride film. The contact plugs can be, for example, tungsten members. Further, via plugs can be also tungsten members. If a copper material is used to form the wiring, a material chiefly containing copper components can be selected to constitute via plugs as a so-called damascene structure.

In the present exemplary embodiment, the connecting portions314A can be formed by the conductive pattern that constitutes the wiring layer111. A material chiefly containing copper components can be used to form the conductive pattern. Further, the pads313can be constituted by the conductive pattern included in the wiring layer109. A material chiefly containing aluminum components can be used to form the pads. Further, general semiconductor processes are employable to form the wiring layers, the plug layers, and the interlayer insulating film, although detailed description thereof is omitted. When the above-described manufacturing processes have been thoroughly finished, the configuration illustrated inFIG. 6Bcan be obtained.

Next, manufacturing processes of the second member309illustrated inFIG. 4are described below with reference toFIGS. 7A and 7B. InFIGS. 7A and 7B, a configuration309′ is an unfinished portion to be later completed as the second member309illustrated inFIG. 4. Regions301′,302′, and312′ are unfinished portions to be later completed as the pixel portion301B, the peripheral circuit portion302B, and the pad portion312B, as illustrated inFIG. 4. A region150B′ is an unfinished portion to be later completed as the seal ring150B.

The manufacturing processes of the second member309according to the present exemplary embodiment include preparing a semiconductor substrate404and forming elements on the semiconductor substrate404. The semiconductor substrate404includes a principal plane405and a backside406. The semiconductor substrate404has a thickness of D4. Then, the element isolation structure136is formed on the semiconductor substrate404. The element isolation structure136is, for example, the LOCOS or STI structure. Further, the P-type semiconductor areas135and139that function as p-type wells and the n-type semiconductor area142that functions as an n-type well are formed on the semiconductor substrate404. Then, the n-type semiconductor areas138and141that form a source area and a drain area that constitutes a transistor, the p-type semiconductor area144, and a semiconductor area that constitutes a protection diode are formed.

Further, the manufacturing processes include forming n-type semiconductor areas138′ and139′ that are electrically connected to electric conductors constituting the seal rings. The n-type semiconductor areas138′ and139′ can be configured to be similar to the substrate in conduction type. Then, the gate electrode layer128, which includes the gate electrodes137,140, and143of transistors and wirings (i.e., resistors), is formed by deposition and patterning of a polysilicon layer. In the present exemplary embodiment, general semiconductor processes are employable to form the gate electrode and the element isolation and semiconductor areas, although detailed description thereof is omitted. When the above-described manufacturing processes have been thoroughly finished, the configuration illustrated inFIG. 7Acan be obtained.

The manufacturing processes further include forming a second wiring structure322on the principal plane of the semiconductor substrate404. The second wiring structure322includes the interlayer insulating films124to127, the plug layers129,131, and133, and the wiring layers130,132, and134. In the present exemplary embodiment, the interlayer insulating films can be constituted by silicon dioxide films. The interlayer insulating films may be constituted by silicon nitride films, or organic resin films. The wiring layers can be constituted by wirings chiefly containing aluminum components or wirings chiefly containing copper components.

In the present exemplary embodiment, the connecting portions314B can be formed by the conductive pattern that constitutes the wiring layer134. A material chiefly containing copper components can be used to constitute the conductive pattern. The interlayer insulating film106which is the topmost interlayer insulating film functions as a passivation film and can be constituted by a silicon oxynitride film or a silicon nitride film. Further, general semiconductor processes are employable to form the wiring layers, the plug layers, and the interlayer insulating film, although detailed description thereof is omitted. When the above-described manufacturing processes have been thoroughly finished, the configuration illustrated inFIG. 7Bcan be obtained.

The manufacturing processes further includes laminating the first member308′ and the second member309′ illustrated inFIG. 6BandFIG. 7Bin such a manner that the principal plane402and the principal plane405of these semiconductor substrates are bonded by facing to each other. More specifically, the uppermost surface of the wiring structure of the first member308′ is bonded to the uppermost surface of the wiring structure of the second member309′. In the present exemplary embodiment, the first connecting portions311and314and801are constituted by the conductive pattern that chiefly contains copper components. Therefore, a metal junction of copper can be employed to realize the above-described lamination. The conductive pattern formed on the topmost surface of the seal ring150A, which is brought into direct contact with the seal ring150B, and the conductive pattern formed on the topmost surface of the seal ring151B, which is brought into direct contact with the seal ring150A, constitute the connecting portion152. Further, the first wiring structure321illustrated inFIG. 6Band the second wiring structure322illustrated inFIG. 7Bform a wiring structure320.

After the first member308′ and the second member309′ are bonded, a backside403portion of the semiconductor substrate401constituting the first member308′ can be removed to reduce the entire thickness thereof. In other words, the first member308′ can be formed as a thin-film layer. Further, a backside406portion of the semiconductor substrate404constituting the second member309′ can be removed to reduce the entire thickness thereof. Namely, the second member309′ can be formed as a thin-film layer. Chemical mechanical polishing (CMP) or etching processing is employable to form the above-described thin-film layers according to the present exemplary embodiment. The semiconductor substrate401is finally configured as the semiconductor substrate101having a thickness of D1, which is smaller than D3, (i.e., D1<D3) (seeFIG. 8A).

Reducing the thickness of the semiconductor substrate401to form the semiconductor substrate101as described above is desired because incident light can be effectively guided into the photoelectric conversion unit. The semiconductor substrate404is finally configured as the semiconductor substrate121having a thickness of D2, which is smaller than D4, (i.e., D2<D4) (seeFIG. 8A). Further, in this case, the thickness D1of the semiconductor substrate101is smaller than the thickness D2of the semiconductor substrate121(i.e., D1<D2). In a case where the thickness of the second member309′ is not reduced, the thickness D1of the semiconductor substrate101is smaller than the thickness D4of the semiconductor substrate404(i.e., D1<D4).

The manufacturing processes further includes forming the planarization layer115made of a resin material, the color filter layer116, the planarization layer117made of a resin material, and the microlens layer118, in this order, on a backside408of the semiconductor substrate101. Further, general semiconductor processes are employable to form the planarization layer, the color filter layer, and the microlens layer, although detailed description thereof is omitted. The microlens layer can be formed to cover the region312′ to be finally configured as the pad portion. When the above-described manufacturing processes have been thoroughly finished, the configuration illustrated inFIG. 8Bcan be obtained.

The manufacturing processes further include forming the openings100to uncover the surfaces of the pads313. In the present exemplary embodiment, the photolithography technique is employed to provide a photoresist mask including arbitrary openings on the microlens layer118. Then, the dry etching technique is employed to remove the microlens layer118, the planarization layer117, the color filter layer116, the planarization layer115, the semiconductor substrate101, and an interlayer insulating film104′ and form the openings100to uncover the pads313. Then, the microlens layer118, the planarization layers117and115, the color filter layer116, the semiconductor substrate101and the interlayer insulating film104are formed. When the above-described manufacturing processes have been thoroughly finished, the configuration illustrated inFIG. 8C, i.e., the configuration illustrated inFIG. 4, can be obtained.

As described above, the seal rings150A,151A,152A, and150B can be formed in the same processes together with the wirings of the wiring structures. Further, in the etching processing, the pads313are functionally operable as etching stoppers.

The present invention is not limited to the processes of the manufacturing method according to the present exemplary embodiment. The order of the above-described manufacturing processes can be arbitrarily changed. Further, the first member308and the second member309can be formed sequentially or in parallel. Further, the first member308and the second member309can be purchased beforehand and later laminated to form a finished product. Further, each of the semiconductor substrates401and402can be constituted by a silicon on insulator (SOI) substrate.

A second exemplary embodiment of the present invention is described below with reference toFIGS. 9A to 9C. Each ofFIG. 9A,FIG. 9B, andFIG. 9Cis a cross-sectional view schematically illustrating a solid-state imaging apparatus. More specifically,FIGS. 9A to 9Care cross-sectional views illustrating modified examples of the solid-state imaging apparatus illustrated inFIG. 4. InFIGS. 9A to 9C, constituent components similar to those illustrated inFIG. 4are denoted by the same reference numerals and their descriptions are not repeated.

The present exemplary embodiment is different from the first exemplary embodiment in the electric path extending from the pads313to the second member. In the above-described first exemplary embodiment, the plugs and the wirings are disposed in a projection area of the pads313disposed on the first member, which is vertically projected toward the second member. The electric path is formed to reach the lowermost wiring layer of the second member, and then electrical connection is formed so that signals can be transmitted and received to and from the circuit elements of the second member.

On the other hand, the electric path according to the present exemplary embodiment extends from the pads313to the peripheral circuit portion in the first member and further extends to the circuit elements of the second member via the plugs to form the electrical connection.

As illustrated inFIG. 9A, a first member808includes the draw-out wiring316that extends from the pad313to the peripheral circuit portion in the horizontal direction. Further, a second member809includes a connecting portion at a horizontally extended region, which is formed by the draw-out wiring316of the first member808. The seal rings150A,151A,152A, and150B are similar to those described in the first exemplary embodiment.

The solid-state imaging apparatus illustrated inFIG. 9Aincludes the seal ring151A. Therefore, it is required to provide at least one of the seal rings150A and152A. However, the configuration including continuously disposed seal rings150A and152A is effective to enhance the moisture resistance effects and suppress the chipping, as described in the first exemplary embodiment. Further, the pads313can be disposed at an arbitrary position if the pads313are positioned on the first member808side compared to the principal plane122of the second member809.

Next, the configuration illustrated inFIG. 9Bis described below. The solid-state imaging apparatus illustrated inFIG. 9Bis different from that illustrated inFIG. 9Ain that no passivation layer is provided. The insulating layer106′, whose function as a passivation layer is lower compared to that of a material containing SiN components, is disposed on the topmost surface of the wiring structure. In this case, since the solid-state imaging apparatus includes the seal ring151A, the seal ring152A is not indispensible as illustrated inFIG. 9B. As the seal rings150A and151B are provided, conductive patterns that constitute the topmost surfaces of respective members are in contact with each other.

Thus, the above-described configuration can suppress water invasion from the topmost surfaces of the first and second members that may occur in a case where no passivation layer is provided. Further, the seal ring150B of the second member809is positioned outside the peripheral circuit portion, which is provided inside the pad portion, and is positioned inside the outer peripheral portion, which is provided outside the pad portion. The solid-state imaging apparatus illustrated inFIG. 9Bincludes the seal ring150B disposed along the outermost periphery of the second member and can obtain effects similar to those obtainable from the configuration illustrated inFIG. 9A.

Next, the solid-state imaging apparatus illustrated inFIG. 9Cis described below. The solid-state imaging apparatus illustrated inFIG. 9Cis different from the solid-state imaging apparatus illustrated inFIG. 9Ain that the seal ring151A is not provided and passivation layers are provided to constitute topmost surfaces of the first and second members. In this case, the seal rings150A and150B can be omitted although the seal ring152A is required. Further, the passivation layers of the above-described configuration can constitute a part of the seal ring.

The above-described configuration can reduce water invasion via a cross-sectional area of the wiring structure at each pad opening.

A third exemplary embodiment of the present invention is described below with reference toFIGS. 10A to 10CandFIG. 11. Each ofFIG. 10A,FIG. 10BandFIG. 10Cis a cross-sectional view schematically illustrating a solid-state imaging apparatus. More specifically,FIGS. 10A to 10Care cross-sectional views illustrating modified examples of the solid-state imaging apparatus illustrated inFIG. 4.FIG. 11illustrates another modified example of the solid-state imaging apparatus illustrated inFIGS. 10A to 10C. InFIGS. 10A to 10CandFIG. 11, constituent components similar to those illustrated inFIG. 4are denoted by the same reference numerals and their descriptions are not repeated.

The present exemplary embodiment is different from the first exemplary embodiment in the arrangement of the pads.

The solid-state imaging apparatus illustrated inFIG. 10Ais different from the solid-state imaging apparatus illustrated inFIG. 4in that a conductive pattern that constitutes a pad1013is provided on a second member909. Then, a part of a first member908, which corresponds to the pad portion of the first member908, extends therethrough. Further, the second member909includes the draw-out wiring316that extends from the pad313in the horizontal direction. The seal ring can be formed to have a configuration similar to the seal ring described in the first exemplary embodiment. When the above-described configuration is employed, adverse influences of exogenous noises can be suppressed.

The solid-state imaging apparatus illustrated inFIG. 10Aincludes the seal ring151A. Therefore, it is required to provide at least one of the seal rings150A and152A. The configuration including the seal rings150A and150B connected along the entire periphery thereof is effective to enhance the moisture resistance effects and suppress the chipping, as described in the first exemplary embodiment.

The solid-state imaging apparatus illustrated inFIG. 10Bis different from the solid-state imaging apparatus illustrated inFIG. 10Ain that no passivation layer is provided. The insulating layer106′, whose function as a passivation layer is lower compared to that of a material containing SiN components, is disposed on the topmost surface of the wiring structure. In other words, the solid-state imaging apparatus illustrated inFIG. 10Bis similar to the solid-state imaging apparatus illustrated inFIG. 9B. In this case, as the solid-state imaging apparatus includes the seal rings151A and151B, the seal ring152A as illustrated inFIG. 9Bis not indispensible. However, the seal rings150A and150B are disposed.

Thus, the above-described configuration can reduce the possibility of water invasion from the topmost surfaces of the first and second members that may occur in a case where no passivation layer is provided. Further, the seal ring of the second member809is positioned outside the peripheral circuit portion, which is provided inside the pad portion, and is positioned inside the outer peripheral portion, which is provided outside the pad portion. The solid-state imaging apparatus illustrated inFIG. 10Bincludes the seal ring150A disposed along the outermost periphery and can obtain effects similar to those obtainable from the configuration illustrated inFIG. 10A.

Next, the solid-state imaging apparatus illustrated inFIG. 10Cis described below. The solid-state imaging apparatus illustrated inFIG. 10Cis different from the solid-state imaging apparatus illustrated inFIG. 10Ain that the seal ring151A is not provided and passivation layers are provided to constitute topmost surfaces of the first and second members. In other words, the solid-state imaging apparatus illustrated inFIG. 10Cis similar to the solid-state imaging apparatus illustrated inFIG. 9C. In this case, the seal ring150A can be omitted although the seal rings152A,150B, and151B are required. The above-described configuration can reduce water invasion via a cross-sectional area of the wiring structure at each pad opening. In this case, it is unnecessary to connect the seal rings150A and150B along the entire periphery thereof.

FIG. 11illustrates a modified example of the solid-state imaging apparatus illustrated inFIGS. 10A to 10C, in which the pad313is provided on a second member1009. The solid-state imaging apparatus illustrated inFIG. 11includes a through electrode317that extends across the second substrate from the backside thereof to the pad313. The pad313can be formed by a conductive pattern similar to the wiring layer. Further, the pad313is an electrode pad connected to the through electrode317that extends across the semiconductor substrate from one surface to the other surface positioned on the opposite side. Further, it is unnecessary to form the seal ring151A of the pad portion having been described in other exemplary embodiments if the seal rings150A and150B are provided. When the configuration illustrated inFIG. 11is employed, the solid-state imaging apparatus can be connected to other circuit substrate at the backside thereof. Therefore, downsizing of the solid-state imaging apparatus can be realized.

A fourth exemplary embodiment of the present invention is described below with reference toFIGS. 12A to 12C. Each ofFIG. 12A,FIG. 12B, andFIG. 12Cis a cross-sectional view schematically illustrating a solid-state imaging apparatus. More specifically,FIGS. 12A to 12Care cross-sectional views illustrating modified examples of the solid-state imaging apparatus illustrated inFIG. 4. InFIGS. 12A to 12C, constituent components similar to those illustrated inFIG. 4are denoted by the same reference numerals and their descriptions are not repeated.

The present exemplary embodiment is different from the first exemplary embodiment in the arrangement of the draw-out wiring316and the pad portion. Similar to the solid-state imaging apparatus illustrated inFIGS. 10A to 10C, the solid-state imaging apparatus illustrated inFIGS. 12A to 12Cinclude a first member1108and a second member1109that are partly removed for wire bonding.

The solid-state imaging apparatus illustrated inFIG. 12Ais different from the solid-state imaging apparatus illustrated inFIG. 4in that a portion corresponding to the pad portion of the first member1108is removed and the pad313is included in the second member1109. Further, the solid-state imaging apparatus illustrated inFIG. 12Aincludes the draw-out wiring316located on the first member1108to electrically connect the pad313of the second member1109to the peripheral circuit portion.

The seal rings150A,151A, and152A are provided in the first member1108to constitute the first sealing portion. Further, the seal rings150B,151B, and152B are provided in the second member1109to constitute the second sealing portion. Similar to the above-described exemplary embodiments, it is desired to constitute the first sealing portion and the second sealing portion to have the capability of suppressing adverse influences of exogenous noises. Further, the seal ring152B of the second member1109is disposed between the pad portion and the peripheral circuit.

Further, it is desired that the seal ring152B is disposed in such a way as to surround the peripheral circuit portion, when vertically projected from the first member1108side toward the second substrate of the second member1109. The solid-state imaging apparatus illustrated inFIG. 12Aincludes the seal ring151A. Therefore, it is required to provide at least one of the seal rings150A and152A. Further, the solid-state imaging apparatus illustrated inFIG. 12Aincludes the seal ring151B. Therefore, it is required to provide at least one of the seal rings150B and152B.

Next, the solid-state imaging apparatus illustrated inFIG. 12Bis described below. The configuration illustrated inFIG. 12Bis different from the solid-state imaging apparatus illustrated inFIG. 12Ain that no passivation layer is provided. The insulating layer106′, whose function as a passivation layer is lower compared to that of a material containing SiN components, is disposed on the topmost surface of the wiring structure. In other words, the solid-state imaging apparatus illustrated inFIG. 12Bis similar to the solid-state imaging apparatus illustrated inFIG. 9BandFIG. 10B. In this case, since the solid-state imaging apparatus includes the seal rings151A and151B, the seal ring152A is not indispensible but the seal ring150A is disposed as illustrated inFIG. 12B.

The above-described configuration can reduce water invasion from the topmost surfaces of the first and second members even if no passivation layer is provided. The seal ring152B can be omitted if the seal rings150B and151B are provided. However, providing the seal ring152B is desired to improve the moisture resistance.

Next, the solid-state imaging apparatus illustrated inFIG. 12Cis described below. The configuration illustrated inFIG. 12Cis different from the solid-state imaging apparatus illustrated inFIG. 12Ain that the wiring structure does not include the seal ring151A and passivation layers are provided to constitute topmost surfaces of the first and second members. The solid-state imaging apparatus illustrated inFIG. 12Cincludes the seal ring150A, the seal ring152A, and the seal ring152B. The above-described configuration can reduce water invasion via a cross-sectional area of the wiring structure at each pad opening. If the pads313are provided on the topmost surface of the second member, the seal ring152B can be omitted. However, providing the seal ring152B is desired to improve the moisture resistance.

The above-described solid-state imaging apparatuses include the first member and the second member that are connected in an overlapped fashion. If the seal rings150A and150B of the first and second member are electrically connected to each other and are respectively connected to semiconductor areas disposed on the substrates thereof, it is desired that these semiconductor areas are similar in conduction type.

On the other hand, if the seal rings of the first and second members are not connected to each other and independently arranged, semiconductor substrates that are different in conduction type can be used. The configuration independently arranging the seal rings of the first and second members can bring an effect of protecting the substrate of one member from being adversely influenced by a noise entering the substrate of the other member regardless of the conduction type of each semiconductor substrate provided in the first and second members.

A solid-state imaging apparatus according to a fifth exemplary embodiment is described below with reference toFIG. 13. The solid-state imaging apparatus according to the fifth exemplary embodiment is different from the solid-state imaging apparatus described in the first to fourth exemplary embodiments in that seal rings constituted by electric conductors are not in contact with each other at the sealing portions of the first member and the second member. Instead, passivation layers constituting the topmost surfaces of the first member and the second member are in contact with each other.

In the configuration illustrated inFIG. 13, a first member1308includes a seal ring152A constituted by an electric conductor. A second member1309includes a seal ring150B constituted by an electric conductor. The seal rings152A and150B are mutually offset in the horizontal direction. Conductive patterns that constitute the topmost surfaces of the first member1308and the second member1309are not in contact with each other. However, passivation layers1301A and1301B having excellent moisture-absorption characteristics are provided on the topmost surfaces, so that sealing properties can be maintained adequately.

An example imaging system that includes a solid-state imaging apparatus, as a practical application of the solid-state imaging apparatus according to any one of the above-described exemplary embodiments, is described below. The imaging system is not limited to a photographing device, such as a camera, and can be any other device (e.g., a personal computer or a portable terminal) if it accessorily has the capability of capturing an image. For example, a camera can include a solid-state imaging apparatus according to the present invention and a processing unit configured to process an output signal of the solid-state imaging apparatus. The above-described processing unit can be configured to include, for example, an analog-to-digital (AD) converter and a processor that can process digital data output from the AD converter.

As described above, the solid-state imaging apparatus according to the present invention can reduce water invasion into the photoelectric conversion unit or the peripheral circuit portion. Further, the manufacturing method according to the present invention can accomplish the connection of the seal rings at the same time as the connection of the first member and the second member at their connecting portions. Therefore, it becomes feasible to improve the moisture resistance and suppress the chipping without increasing time required to finish the manufacturing processes.

The present invention is not limited to the configurations having been described in the exemplary embodiments. The conduction type and the circuits can be changed to an opposite conduction type. Further, the present invention is applicable to a case where the connecting portions are provided only in an area not including the pixel portion (e.g., the peripheral circuit portion). Further, the configurations described in respective exemplary embodiments are appropriately combinable.

This application claims the benefit of Japanese Patent Applications No. 2010-149488 filed Jun. 30, 2010, and No. 2011-138657 filed Jun. 22, 2011, which are hereby incorporated by reference herein in their entirety.

REFERENCE SIGNS LIST

302peripheral circuit portion