Method and apparatus for performing dynamic throttling control with aid of configuration setting

A method for performing dynamic throttling control with aid of configuration setting and associated apparatus such as a host device, a data storage device and a controller thereof are provided. The method includes: utilizing the host device to provide a user interface, to allow a user to select any of a plurality of throttling control configurations of the data storage device; and in response to the selection of said any of the plurality of throttling control configurations by the user, utilizing the host device to send throttling control information corresponding to said any of the plurality of throttling control configurations toward the data storage device, to perform the dynamic throttling control on the data storage device during programming the NV memory, for limiting power consumption of the data storage device during programming the NV memory, wherein the throttling control information indicates performing the dynamic throttling control is required.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to flash memory access, and more particularly, to a method and apparatus for performing dynamic throttling control with aid of configuration setting, where examples of the apparatus may include, but are not limited to: a host device, a data storage device and a controller thereof.

2. Description of the Prior Art

Developments in memory technology have enabled the wide application of portable memory devices, such as memory cards conforming to SD/MMC, CF, MS and XD specifications. Improving access control of memories in these portable memory devices remains an issue to be solved in the art.

NAND flash memories may comprise single level cell (SLC) and multiple level cell (MLC) flash memories. In an SLC flash memory, each transistor used as a memory cell may have either of two electrical charge values respectively corresponding to logic values 0 and 1. In comparison, the storage ability of each transistor used as a memory cell in an MLC flash memory may be fully utilized. The transistor in the MLC flash memory can be driven by a voltage higher than that in the SLC flash memory, and different voltage levels can be utilized to record information of at least two bits (e.g. 00, 01, 11, or 10). In theory, the recording density of the MLC flash memory may reach at least twice the recording density of the SLC flash memory, and is therefore preferred by manufacturers of NAND flash memories.

The lower cost and larger capacity of the MLC flash memory means it is more likely to be applied in portable memory devices than an SLC flash memory. The MLC flash memory does have instability issues, however. To ensure that access control of the flash memory in the portable memory device meets required specifications, a controller of the flash memory may be equipped with some management mechanisms for properly managing data access.

Even memory devices with the above management mechanisms may have certain deficiencies, however. For example, the instantaneous power consumption of a memory device in response to some types of write/program operations may be too large, potentially exceeding predetermined product specification limitations. Thus, a novel method and associated architecture are needed for solving the problems without introducing any side effect or in a way that is less likely to introduce a side effect.

SUMMARY OF THE INVENTION

It is therefore an objective of the present invention to provide a method for performing dynamic throttling control with aid of configuration setting, and to provide associated apparatus such as a host device, a data storage device and a controller thereof, in order to solve the above-mentioned problems.

It is another objective of the present invention to provide a method for performing dynamic throttling control with aid of configuration setting, and to provide associated apparatus such as a host device, a data storage device and a controller thereof, in order to achieve an optimal performance without introducing a side effect or in a way that less likely to introduce a side effect.

At least one embodiment of the present invention provides a method for performing dynamic throttling control with aid of configuration setting, where the method may be applied to an electronic device comprising a host device and a data storage device. For example, the data storage device may comprise a non-volatile (NV) memory, and the NV memory may comprise a plurality of NV memory elements. The method may comprise: utilizing the host device to provide a user interface, to allow a user to select any of a plurality of throttling control configurations of the data storage device; and in response to the selection of said any of the plurality of throttling control configurations by the user, utilizing the host device to send throttling control information corresponding to said any of the plurality of throttling control configurations toward the data storage device, to perform the dynamic throttling control on the data storage device during programming the NV memory, for limiting power consumption of the data storage device during programming the NV memory, wherein the throttling control information indicates performing the dynamic throttling control is required.

In addition to the above method, the present invention also provides a host device. The host device may comprise a processing circuit, and the processing circuit may be arranged to control the host device to perform dynamic throttling control of a data storage device with aid of configuration setting, where the data storage device may be arranged to store information for the host device. For example, the data storage device may comprise an NV memory, and the NV memory may comprise a plurality of NV memory elements. In addition, the host device may provide a user interface, to allow a user to select any of a plurality of throttling control configurations of the data storage device. In response to the selection of said any of the plurality of throttling control configurations by the user, the host device may send throttling control information corresponding to said any of the plurality of throttling control configurations toward the data storage device, to perform the dynamic throttling control on the data storage device during programming the NV memory, for limiting power consumption of the data storage device during programming the NV memory, wherein the throttling control information indicates performing the dynamic throttling control is required.

In addition to the above method, the present invention also provides a data storage device, and the data storage device may comprise an NV memory and a memory controller, where the NV memory may comprise a plurality of NV memory elements. The memory controller may be arranged to control accessing of the NV memory, to allow a host device to access the NV memory through the memory controller and perform dynamic throttling control of the data storage device with aid of configuration setting. In addition, the host device may provide a user interface, to allow a user to select any of a plurality of throttling control configurations of the data storage device. In response to the selection of said any of the plurality of throttling control configurations by the user, the host device may send throttling control information corresponding to said any of the plurality of throttling control configurations toward the data storage device, to perform the dynamic throttling control on the data storage device during programming the NV memory, for limiting power consumption of the data storage device during programming the NV memory, wherein the throttling control information indicates performing the dynamic throttling control is required. Based on the dynamic throttling control, the memory controller may dynamically perform a plurality of throttling control operations according to the throttling control information, to limit the power consumption of the data storage device during programming the NV memory.

In addition to the above method, the present invention also provides a controller of a data storage device, where the data storage device may comprise the controller and an NV memory, and the NV memory may comprise a plurality of NV memory elements. For example, the controller may comprise a processing circuit, and the processing circuit may be arranged to control operations of the controller for controlling accessing of the NV memory, to allow a host device to access the NV memory through the controller and perform dynamic throttling control of the data storage device with aid of configuration setting. In addition, the host device may provide a user interface, to allow a user to select any of a plurality of throttling control configurations of the data storage device. In response to the selection of said any of the plurality of throttling control configurations by the user, the host device may send throttling control information corresponding to said any of the plurality of throttling control configurations toward the data storage device, to perform the dynamic throttling control on the data storage device during programming the NV memory, for limiting power consumption of the data storage device during programming the NV memory, wherein the throttling control information indicates performing the dynamic throttling control is required. Based on the dynamic throttling control, the controller may dynamically perform a plurality of throttling control operations according to the throttling control information, to limit the power consumption of the data storage device during programming the NV memory.

According to some embodiments, the dynamic throttling control may comprise: before a target NV memory element of the plurality of NV memory elements is programmed, utilizing the memory controller to check whether at least one other NV memory element of the plurality of NV memory elements is in a busy state or in a non-busy state; and in response to each of the aforementioned at least one other NV memory element enters the non-busy state, utilizing the memory controller to program the target NV memory element.

The present invention method and associated apparatus can guarantee that the electronic device can operate properly, to prevent problems in the related art, such as the instantaneous power consumption exceeding the predetermined product specification limitations. In addition, implementing according to the embodiments of the present invention does not significantly increase additional costs. Therefore, the related art problems can be solved, and the overall cost will not increase too much. In comparison with the related art, the present invention method and associated apparatus can enhance overall performance without introducing any side effect or in a way that is less likely to introduce a side effect.

DETAILED DESCRIPTION

FIG. 1is a diagram of an electronic device10according to an embodiment of the present invention, where the electronic device10may comprise a host device50and a data storage device100, and the data storage device100may be arranged to store information for the host device50. According to this embodiment, the data storage device100may provide storage space to the host device50, and may obtain one or more driving voltages from the host device50as the power of the data storage device100, but the present invention is not limited thereto.

The host device50may comprise: a processing circuit52(e.g. at least one processor such as one or more processors, and associated circuits such as Random Access Memory (RAM), bus, etc.) arranged to control operations of the host device50; a storage interface circuit54arranged to couple one or more data storage devices (e.g. the data storage device100) to the host device50; and a touch-sensitive display panel56(e.g. a liquid crystal display (LCD) touch screen) that is coupled to the processing circuit52, and is arranged to provide a user interface57(labeled “UI” inFIG. 1, for brevity) to a user of the electronic device10. Examples of the host device50may include, but are not limited to: multifunctional mobile phones, tablets, wearable devices, and personal computers (PCs) such as desktop computers or laptop computers.

The data storage device100may comprise a controller such as a memory controller110, and may further comprise a non-volatile (NV) memory120, wherein the controller is arranged to access the NV memory120, and the NV memory120is arranged to store information. The NV memory120may comprise at least one NV memory element (e.g. one or more NV memory elements), such as a plurality of NV memory elements122-1,122-2, . . . , and122-N, where the symbol “N” may represent an integer greater than one. For example, the NV memory120may be a flash memory, and the NV memory elements122-1,122-2, . . . , and122-N may be a plurality of flash memory chips (which may be referred to as flash chips, for brevity) or a plurality of flash memory dies (which may be referred to as flash dies, for brevity), respectively, but the present invention is not limited thereto. Examples of the data storage device100may include, but are not limited to: portable memory devices (such as memory cards conforming to the SD/MMC, CF, MS, XD or UFS specifications), solid state drives (SSDs) and various embedded data storage devices (such as those conforming to the UFS or EMMC specifications).

As shown inFIG. 1, the memory controller110may comprise at least one clock source (e.g. one or more clock sources) which may be collectively referred to as the clock source111(labeled “CS” inFIG. 1, for brevity). The aforementioned at least one clock source such as the clock source111may be arranged to generate at least one clock signal (e.g. one or more clock signals) which may be collectively referred to as the clock signal CLK. For example, based on one or more default settings or one or more user settings, the clock signal CLK may carry any frequency of a plurality of predetermined frequencies of the clock source111, for being utilized as an operating frequency of the memory controller110. In addition, the memory controller110may further comprise a processing circuit such as a microprocessor112, a storage such as a read-only memory (ROM)112M, a control logic circuit114, a buffer memory116and a transmission interface circuit118, where at least one portion (e.g. a portion or all) of these components may be coupled to each other via a bus. The buffer memory116is implemented with a random access memory (RAM), for example, a Static RAM (SRAM), where the RAM may provide internal storage space for the memory controller110, for example, may temporarily store data, but the present invention is not limited thereto. Further, the ROM112M of this embodiment is arranged to store a program code112C, and the microprocessor112is arranged to execute the program code112C to control the access of the NV memory120. Please note that the program code112C may be stored in the buffer memory116or any type of memories. Additionally, the control logic circuit114may be arranged to control the NV memory120. The control logic circuit114may comprise an error correction code (ECC) circuit (not shown), to protect data and/or perform error correction. The transmission interface circuit118may conform to a specific communications specification (such as the Serial Advanced Technology Attachment (SATA) specification, Universal Serial Bus (USB) specification, Peripheral Component Interconnect Express (PCIe) specification, embedded Multi-Media Card (eMMC) specification, or Universal Flash Storage (UFS) specification), and may perform communications according to the specific communications specification.

The host device50may access the NV memory120in the data storage device100by transmitting a plurality of host commands and corresponding logic addresses to the memory controller110. The memory controller110may receive the plurality of host commands and the logic addresses, and translate the plurality of host commands into memory operating commands (which may be referred to as “operating commands” for brevity), respectively, and then use the operating commands to control the NV memory120to read, write or program memory units of certain physical addresses in the NV memory120, where the physical addresses may be associated with the logical addresses. For example, the memory controller110may generate or update at least one logical-to-physical address mapping table (which may be referred to as L2P table, for brevity), to manage relationships between the physical addresses and the logic addresses, but the present invention is not limited thereto.

The aforementioned L2P table preferably uses a logical address as an index, with the corresponding entry thereof recording a physical address (which may consist of a block number, a page number, an offset, a plane number, a logical unit number (LUN), a channel number, etc.), for recording or updating the relationships between the physical addresses and the logic addresses.

For example, in the NV memory120, any NV memory element122-nwithin the NV memory elements122-1,122-2, . . . , and122-N (e.g. the symbol “n” may represent any integer in the interval [1, N]) may comprise multiple blocks, wherein a block within the multiple blocks may comprise and record a specific number of pages. In a situation where a physical address comprises a block address such as a block number and a page address such as a page number, the memory controller110may access a certain page in a certain block within the NV memory120according to the block number and the page number.

In another example, the aforementioned any NV memory element122-nmay comprise multiple planes, where a plane within the multiple planes may comprise a set of blocks such as the aforementioned multiple blocks, and a block within the set of blocks may comprise and record a specific number of pages. In a situation where a physical address comprises a plane number, a block number and a page number, the memory controller110may access a certain page in a certain block in a certain plane within the NV memory120according to the plane number, the block address and the page address, but the present invention is not limited thereto. As the total block count increases, the storage capacity of the NV memory120becomes larger.

Based on the architecture of the NV memory120, the smallest unit that the memory controller110performs operations of erasing data on the NV memory120may be a block, and the smallest unit that the memory controller110performs operations of writing data on the NV memory120may be a page, but the present invention is not limited thereto. As the difference between the smallest units of the above operations exists, the memory controller110may be designed to have various management mechanisms to guarantee that the data storage device100can operate correctly.

Regarding manufacturing the NV memory120, there are a plenty of applicable techniques, such as the2D/planar NAND flash technique that arranges the memory cells into a single layer, and the3D NAND Flash technique that arranges the memory cells into a multi-layer vertical stack. For example, the NV memory120may be implemented as a planar NAND flash architecture having memory cells arranged in a single layer. In another example, the NV memory120may be implemented as a3D NAND flash architecture having multi-layer vertically stacked memory cells. In this situation, the storage capacity of the NV memory120may become very huge.

In comparison with an operation of reading data from the NV memory120, an operation of writing (more particularly, programming) data into the NV memory120may be time-consuming and power consuming. According to some embodiments, the host device50may provide various configuration options on the user interface57for the user, and obtain the latest configurations that the user selects via the user interface57. The host device50may control the memory controller110according to the latest configurations to manage one or more operations of the data storage device100, for limiting the power consumption of the data storage device100during programming the NV memory120. As a result, the architecture of the present invention can solve problems in the related arts without introducing side effects or in a way that is less likely to introduce side effects. For example, based on the latest configurations, the memory controller110may dynamically adjust the scheduling of the programming operations, for achieving optimal performance of the data storage device100while limiting the power consumption. In another example, based on the latest configurations, the memory controller110may dynamically adjust the operating frequency of the memory controller110, for achieving optimal performance of the data storage device100while limiting the power consumption.

FIG. 2is a flowchart of a method200for performing dynamic throttling control with aid of configuration setting according to an embodiment of the present invention. The method200can be applied to the electronic device10, and more particularly, can be applied to the host device50comprising the processing circuit52running the program modules53corresponding to the method, and applied to the one or more data storage devices mentioned above, such as the data storage device100comprising the memory controller110. For example, the processing circuit52running the program module53may control the host device50to operate according to the method. For another example, the memory controller110, and more particularly, the microprocessor112running one or more program codes corresponding to the method, may control the data storage device100to operate according to the method, where the one or more program codes may comprise the program code112C and/or an additional program code such as an in-system program (ISP) code.

In Step202, the host device50may establish a connection between the host device50and the data storage device100, but the present invention is not limited thereto.

In Step204, the host device50may check whether establishing the connection is successful. If establishing the connection is successful, Step206is entered; otherwise, Step202is entered.

In Step206, the host device50may provide the user interface57, to allow the user to select any of a plurality of throttling control configurations of the data storage device100. For example, the host device50may provide the user interface57in a selection procedure, and the user may confirm his/her selection (e.g. touch or press a virtual button labeled “OK” in the user interface57) after the selection of the user is completed.

In Step208, the host device50may check whether the user selection (e.g. the selection of the user in the selection procedure) is completed. If the user selection is completed, Step210is entered; otherwise, Step206is entered.

In Step210, in response to the selection of the aforementioned any of the plurality of throttling control configurations by the user, the host device50may send throttling control information (e.g. the throttling control information corresponding to the aforementioned any of the plurality of throttling control configurations) toward the data storage device100, to perform the dynamic throttling control on the data storage device100during programming the NV memory120, for limiting power consumption of the data storage device100during programming the NV memory120. For example, the throttling control information may indicate performing the dynamic throttling control is required.

In Step212, the host device50may detect any user trigger from a widget. For example, the widget may be implemented as a home screen widget on a home screen displayed by the touch-sensitive display panel56. According to this embodiment, the user may touch or press a virtual button of the widget (e.g. the home screen widget) to trigger the host device50to provide the user interface57. As a result, the host device50may utilize the touch-sensitive display panel56to display the user interface57, and may detect the latest selection of the user via the user interface57.

In Step214, the host device50may check whether an operation of providing the user interface57is triggered. If the operation of providing the user interface57is triggered, Step206is entered; otherwise, Step212is entered.

For better comprehension, the method200may be illustrated with the working flow shown inFIG. 2, but the present invention is not limited thereto. According to some embodiments, one or more steps may be added, deleted, or changed in the working flow shown inFIG. 2.

In the working flow shown inFIG. 2, it may be assumed that the user does not need to cancel his/her selection, and the host device50may provide default settings on the user interface57, for the user to select by default, but the present invention is not limited thereto. According to some embodiments, an additional step may be inserted between Step206and Step208in the working flow shown inFIG. 2, to allow the user to cancel his/her selection, where this additional step may be entered after Step206is performed. In the additional step, the host device50may check whether the user cancels his/her selection. More particularly, in the additional step, if the user cancels his/her selection, Step212is entered; otherwise, Step208is entered.

FIG. 3illustrates a user interface window57W involved with the method200shown inFIG. 2according to an embodiment of the present invention, where the user interface57may comprise the user interface window57W, but the present invention is not limited thereto. The host device50may utilize the user interface window57W to interact with the user, for dynamically performing throttling control of the data storage device100(labeled “Storage Device Throttling Control” inFIG. 3, for brevity). According to this embodiment, there may be multiple categories of configuration setting, such as a first category and a second category respectively shown in the left-hand side and the right-hand side of the user interface window57W.

For example, according to the first category, the host device50may be arranged to obtain the latest configurations regarding controlling the maximum number of concurrently programmed NV memory elements within the NV memory120(labeled “Control maximum number of concurrently programmed NV memory elements” inFIG. 3, for brevity). The host device50may detect whether a checkbox labeled “Enable” in the first category shown in the left-hand side of the user interface window57W is selected by the user, to detect whether the user would like to enable the dynamic throttling control corresponding to the first category during programming the NV memory120. In addition, the host device50may detect whether one of a plurality of checkboxes respectively labeled “1”, “2”, “3”, “4”, “5”, “6”, “7”, and “Other” is selected by the user, to detect whether the user would like to select the corresponding value (e.g. a certain value within the values 1, 2, 3, 4, 5, 6, and 7 or a user defined value in the field next to the checkbox labeled “Other” within the first category) as the maximum number of concurrently programmed NV memory elements within the NV memory12, but the present invention is not limited thereto.

For another example, according to the second category, the host device50may be arranged to obtain the latest configurations regarding controlling the operating frequency of the memory controller110(labeled “Control operating frequency of memory controller” inFIG. 3, for brevity). The host device50may detect whether a checkbox labeled “Enable” in the second category shown in the right-hand side of the user interface window57W is selected by the user, to detect whether the user would like to enable the dynamic throttling control corresponding to the second category during programming the NV memory120. In addition, the host device50may detect whether one of a plurality of checkboxes respectively labeled “100 MHz”, “200 MHz”, “400 MHz”, and “Other” is selected by the user, to detect whether the user would like to select the corresponding value (e.g. a certain value within the frequency values 100 MHz, 200 MHz, and 400 MHz or a user defined value in the field next to the checkbox labeled “Other” within the second category) as the operating frequency of the memory controller110, but the present invention is not limited thereto. According to some embodiments, the frequency values 100 MHz, 200 MHz, and 400 MHz may be determined according to the architecture of the memory controller110, and more particularly, according to the implementation details of the clock source111and/or the microprocessor112.

When the user is going to confirm his/her selection, the user may touch or press the virtual button labeled “OK” at the bottommost of the user interface window57W. As a result, the host device50may determine that the user selection (e.g. the selection of the user in the selection procedure) is completed in Step208, and may close the user interface window57W, but the present invention is not limited thereto. For example, when the user is going to cancel his/her selection, the user may touch or press the virtual button labeled “Cancel” at the bottommost of the user interface window57W. As a result, the host device50may determine that the user cancels his/her selection in the additional step mentioned above, and may close the user interface window57W. For brevity, similar descriptions for this embodiment are not repeated in detail here.

For better comprehension, it may be illustrated in the user interface window57W shown inFIG. 3that the user has selected the checkboxes respectively labeled “Enable” and “3” in the first category and has selected the checkboxes respectively labeled “Enable” and “400 MHz” in the second category, to indicate a possible selection by the user, but the present invention is not limited thereto. According to some embodiments, within all of the checkboxes of the user interface window57W shown inFIG. 3, the user may select one or more of the checkboxes in the first category and/or one or more of the checkboxes in the second category. For example, the user may select one or more of the checkboxes of the first category in one manner to select a throttling control configuration within the plurality of throttling control configurations, and may select one or more of the checkboxes of the first category in another manner to select another throttling control configuration within the plurality of throttling control configurations. For another example, the user may select one or more of the checkboxes of the second category in one manner to select a throttling control configuration within the plurality of throttling control configurations, and may select one or more of the checkboxes of the second category in another manner to select another throttling control configuration within the plurality of throttling control configurations. For yet another example, the user may select one or more of the checkboxes of at least one category (e.g. one or more categories) within the first category and the second category in one manner to select a throttling control configuration within the plurality of throttling control configurations, and may select one or more of the checkboxes of at least one category (e.g. one or more categories) within the first category and the second category in another manner to select another throttling control configuration within the plurality of throttling control configurations.

FIG. 4illustrates a configuration-based throttling control scheme of the method200shown inFIG. 2according to an embodiment of the present invention. The plurality of throttling control configurations may comprise a throttling control configuration CONFIG.1and a throttling control configuration CONFIG.2.

In Step S10, the host device50may provide the user interface57to allow the user to select the throttling control configuration CONFIG.1.

In Step S11, in response to the throttling control configuration CONFIG.1selected by the user, the host device50may send throttling control information TCInfo1corresponding to the throttling control configuration CONFIG.1toward the data storage device100, to perform the dynamic throttling control on the data storage device100during programming the NV memory120, where the throttling control information TCInfo1may indicate a setting value SV11of a control parameter PARA1for controlling the data storage device100.

In Step S13, during programming the NV memory120, the data storage device100(e.g. the memory controller110) may perform a throttling control operation with the control parameter PARA1being equal to the setting value SV11(labeled “PARA1=SV11” inFIG. 4, for brevity).

In Step S20, the host device50may provide the user interface57to allow the user to select the throttling control configuration CONFIG.2.

In Step S21, in response to the throttling control configuration CONFIG.2selected by the user, the host device50may send throttling control information TCInfo2corresponding to the throttling control configuration CONFIG.2toward the data storage device100, to perform the dynamic throttling control on the data storage device100during programming the NV memory120, where the throttling control information TCInfo2may indicate a setting value SV12of the control parameter PARA1for controlling the data storage device100.

In Step S23, during programming the NV memory120, the data storage device100(e.g. the memory controller110) may perform a throttling control operation with the control parameter PARA1being equal to the setting value SV12(labeled “PARA1=SV12” inFIG. 4, for brevity).

According to this embodiment, the setting value SV12is not equal to the setting value SV11. In response to the control parameter PARA1changing from the setting value SV11to the setting value SV12, the power consumption of the data storage device100is changed. As a result, the electronic device10(e.g. the host device50and the data storage device100) can dynamically perform throttling control with aid of configuration setting.

For better comprehension, assume that the control parameter PARA1may indicate an upper limit of the number of concurrently programmed NV memory elements within the plurality of NV memory elements122-1,122-2, . . . , and122-N, such as the maximum number of concurrently programmed NV memory elements within the NV memory120as mentioned in the embodiment shown inFIG. 3. The host device50may control the data storage device100according to the control parameter PARA1, to maintain the number of the concurrently programmed NV memory elements within the plurality of NV memory elements122-1,122-2, . . . , and122-N to be less than or equal to the upper limited indicated by the control parameter PARA1(e.g. a current setting value within the setting values SV11and SV12). For example, the setting values SV11and SV12may represent two different values within the candidate values of the first category, and the user may select the corresponding value within the first category, such as the certain value within the values 1, 2, 3, 4, 5, 6, and 7 or the user defined value in the field next to the checkbox labeled “Other” within the first category. As a result, the data storage device100can prevent the number of the concurrently programmed NV memory elements from exceeding the corresponding value within the first category during programming the NV memory120, but the present invention is not limited thereto.

According to some embodiments, the control parameter PARA1may indicate the operating frequency of the memory controller110within the data storage device100, such as the operating frequency as mentioned in the embodiment shown inFIG. 3. The host device50may control the memory controller110to operate according to the operating frequency indicated by the control parameter PARA1(e.g. a current setting value within the setting values SV11and SV12). For example, the setting values SV11and SV12may represent two different values within the candidate values of the second category, and the user may select the corresponding value within the second category, such as the certain value within the frequency values 100 MHz, 200 MHz, and 400 MHz or the user defined value in the field next to the checkbox labeled “Other” within the second category. As a result, the memory controller110may operate according to the operating frequency as required by the host device50.

FIG. 5is a working flow300of the method200shown inFIG. 2according to an embodiment of the present invention. The working flow300is applicable to the data storage device100, and is applicable to the aforementioned controller such as the memory controller110. Under the control of the aforementioned processing circuit such as the microprocessor112, the memory controller110may perform the working flow300. For brevity, assume that the data storage device100may include a single channel, the total number of NV memory elements in the single channel may equal 4 (N=4), and these NV memory elements such as the NV memory elements122-1,122-2,122-3and122-4can be taken as an example in the embodiment. The present invention is not limited thereto, however. The working flow300is also applicable to the data storage device100with N NV memory elements, wherein N is a positive integer and N=(NPC*NCH), wherein the parameter NCH represents the total channel count, and the parameter NPC represents the NV-memory-element-count per channel.

In Step302, the memory controller110may select one of any un-programmed memory elements. For example, assuming the NV memory elements122-1,122-2and122-3have been selected, and these selections have not been canceled, the NV memory element122-4is the only one left to be selected. Hence, in Step302, the memory controller110may select the NV memory element122-4.

In Step304, the memory controller110may record the selection order of the memory element. Assume that NV memory elements122-1,122-2and122-3have been selected, and the corresponding selection order is 0, 1 and 2, respectively. In this case, the selection order of the NV memory element122-4will be 3.

In Step306, according to the selection order, the memory controller110may determine whether programming of the memory element with a preset selection interval has been completed. If yes, Step310is entered; otherwise, Step308is entered. The preset selection interval is used to determine the relevance between the previously selected NV memory element and the currently selected NV memory element, and the value of the preset selection interval is smaller than the total number of NV memory elements. According to the selection order, the selection intervals of the NV memory elements122-1,122-2and122-3with respect to the NV memory element122-4are 3 (e.g. (3-0)=3), 2 (e.g. (3-1)=2) and 1 (e.g. (3-2)=1), respectively. When the preset selection interval is 3, the memory element of the preset selection interval will correspond to the NV memory element122-1. Then, the memory controller110may check whether the NV memory element122-1is in a busy state or in a non-busy state. According to this embodiment, the non-busy state may be a ready state, but the present invention is not limited thereto.

In Step308, the memory controller110may wait for a preset period. Afterwards, Step306is entered. Since the NV memory elements122-1,122-2and122-3have been selected, programming of the NV memory elements122-1,122-2and122-3still continues. In order to prevent the data storage device100from consuming too much electricity, the memory controller110may wait for a preset period, e.g. 50 nanoseconds (ns). Then, Step306is entered to determine whether programming of the NV memory element122-1has been completed. If yes, programming is performed upon the NV memory element122-4.

In Step310, the memory controller110may initiate (or start) the programming of this memory element. When programming of the NV memory element122-1is completed and the NV memory element122-1enters the non-busy state, the memory controller110may program the selected NV memory element122-4. In this way, the working flow300can prevent the selected NV memory element122-4from being programmed until the NV memory element122-1enters the non-busy state (e.g. programming the selected NV memory element122-4can be performed when the NV memory element122-1enters the non-busy state), thus reaching at least one objective of the present invention. After that, operations of the working flow300end.

Step310may further comprise deleting the selection order of this memory element. When the working flow300is executed again, since the respective selection orders of the memory elements whose programming have been completed are deleted, the NV memory elements corresponding to the remaining selection orders are still being programmed and are in the busy state. Hence, the determination result in Step306conforms to the actual situations of the NV memory elements122-1,122-2,122-3and122-4.

In the above-mentioned embodiment, both the selection order and the programming order of the NV memory elements122-1,122-2,122-3and122-4are shuffled; this explains why Step304might be necessary. In another implementation, the selection order of the NV memory elements122-1,122-2,122-3and122-4is fixed. In this situation, Step304is not necessary and can be skipped.

In the above-mentioned embodiment, the preset programming interval is preferably equal to the total number of NV memory elements minus one, but the present invention is not limited thereto. For example, the preset programming interval may be an integer which is smaller than the total number of NV memory elements.

FIG. 6is a working flow320according to another embodiment of the present invention, where the working flow320may be illustrated through changing the working flow300shown inFIG. 5, for example, Steps322,328and330are the same as Steps302,308and310, respectively, while Steps324and326are different from Steps304and306, respectively.

In Step324, the memory controller110may determine states of other memory elements. For example, when the NV memory elements122-1,122-2and122-3are selected and being programmed, the states of the NV memory elements122-1,122-2and122-3will be busy states.

In Step326, the memory controller110may determine whether the total number of memory elements in the busy state is smaller than a preset value. If yes, Step330is entered; otherwise, Step328is entered. Assuming that the preset value is 3, since the states of the NV memory elements122-1,122-2and122-3are all busy states, the total number of memory elements in the busy state is not smaller than 3, and Step328is therefore entered. When the state of one of the NV memory elements122-1,122-2and122-3changes from the busy state into the non-busy state (e.g. programming of the NV memory element122-1is completed first and the NV memory element122-1enters the non-busy state from the busy state), the total number of memory elements in the busy state will be smaller than the preset value and Step330will be entered, in order to perform programming on the NV memory element122-4.

According to some embodiments, before programming a target NV memory element within the NV memory elements122-1,122-2, . . . and122-N, such as the aforementioned any NV memory element122-n(e.g. the symbol “n” may represent any positive integer within the interval [1, N]), the memory controller110may check whether another NV memory element of the NV memory elements122-1,122-2, . . . and122-N is in the busy state or in the non-busy state. The non-busy state may be the abovementioned ready state, but the present invention is not limited thereto. When the other NV memory element enters the non-busy state, the memory controller110may program the target NV memory element such as the NV memory element122-n. For example, the memory controller110may prevent programming the target NV memory element such as the NV memory element122-nuntil the other NV memory element enters the non-busy state. In a predetermined logic sequence of the NV memory elements122-1,122-2, . . . and122-N, the other NV memory element is a subsequent NV memory element of the target NV memory element such as the NV memory element122-n. For better comprehension, the predetermined logic sequence may be {{122-1,122-2, . . . ,122-N}, {122-1,122-2, . . . ,122-N}, . . . } (which is formed by repeating the sequence {122-1,122-2, . . . ,122-N}), but the present invention is not limited thereto. When the target NV memory element such as the NV memory element122-nrepresents a certain NV memory element of the predetermined logic sequence {{122-1,122-2, . . . ,122-N}, {122-1,122-2, . . . ,122-N}, . . . }, in the predetermined logic sequences {{122-1,122-2, . . . ,122-N}, {122-1,122-2, . . . ,122-N}, . . . }, the other NV memory element is located after this NV memory element. For example, in the predetermined logic sequence, the other NV memory element may be the next NV memory element of the target NV memory element122-n, such as the NV memory element122-(n+1) or NV memory element122-(n+1−N), wherein: if n<N, the next NV memory element represents the NV memory element122-(n+1); otherwise (i.e. n=N), the next NV memory element represents the NV memory element122-(n+1−N) (i.e.122-1, when n=N). In this situation, in the NV memory elements122-1,122-2, . . . and122-N, the maximum of the number of NV memory elements that are simultaneously in the busy state (e.g. the number of concurrently programmed NV memory elements within the plurality of NV memory elements122-1,122-2, . . . , and122-N) may equal the total number of NV memory elements122-1,122-2, . . . and122-N minus one. Further, the predetermined logic sequence may indicate a programming order (e.g. the order of programming operations) applicable to the NV memory elements122-1,122-2, . . . and122-N. In response to at least one request from outside the data storage device100, the memory controller110may program the NV memory elements122-1,122-2, . . . and122-N in turns according to the predetermined logic sequence. The above-mentioned at least one request may represent at least one writing command transmitted from the host device50to the data storage device100. In response to the above-mentioned at least one writing command, the data storage device100may perform a series of programming operations upon the NV memory elements122-1,122-2, . . . and122-N, to store a series of data into the NV memory120as soon as possible without encountering the problems associated with the related arts, e.g. instantaneous power consumption exceeding the predetermined product specification. Based on the method200(e.g. one or more configuration-based throttling control schemes of the method200, such as the configuration-based throttling control scheme shown inFIG. 4), the memory controller110can manage the series of programming operations to achieve optimal performance of the data storage device100without introducing side effects or in a way that is less likely to introduce side effects.

According to some embodiments, the memory controller110may simultaneously program a set of NV memory elements of the NV memory elements122-1,122-2, . . . and122-N, and make the amount of the set of NV memory elements be less than or equal to a predetermined NV memory element count, wherein the predetermined NV memory element count is smaller than the total number of the NV memory elements122-1,122-2, . . . and122-N. For example, during checking whether the other NV memory element is in the busy state or in the non-busy state, the target NV memory element such as the NV memory element122-nhas not yet been selected as an NV memory element of the set of NV memory elements. When the other NV memory element enters the non-busy state, the memory controller110may select the target NV memory element such as the NV memory element122-nas the NV memory element of the set of NV memory elements. In another example, before checking whether the other NV memory element is in the busy state or in the non-busy state, the other NV memory element has been selected as one of the set of NV memory elements. When the other NV memory element enters the non-busy state, the other NV memory element is not one of the set of NV memory elements.

According to some embodiments, the host device50(e.g. the processing circuit52running the program module53) and the data storage device100(e.g. the memory controller110) within the electronic device10may perform associated control of multiple control parameters (such as the control parameter PARA1) according to the configuration-based throttling control scheme shown inFIG. 4, and more particularly, may perform the operations of Steps S10to S23regarding the multiple control parameters, respectively, to perform the configuration adjustment, the parameter setting, the corresponding throttling control operations, etc. regarding the multiple control parameters, respectively. The multiple control parameters may comprise a first control parameter and a second control parameter. The data storage device100(e.g. the memory controller110) may change the first control parameter multiple times to change or update the corresponding throttling control configuration of the data storage device100, and may change the second control parameter multiple times to change or update the corresponding throttling control configuration of the data storage device100. For example, the first control parameter may indicate the upper limit of the number of concurrently programmed NV memory elements within the plurality of NV memory elements122-1,122-2, . . . , and122-N, such as the maximum number of concurrently programmed NV memory elements within the NV memory120as mentioned in the embodiment shown inFIG. 3, and the second control parameter may indicate the operating frequency of the memory controller110within the data storage device100, such as the operating frequency as mentioned in the embodiment shown inFIG. 3. For brevity, similar descriptions for this embodiment are not repeated in detail here.

As mentioned above, when the data storage device100is operating, the throttling control may be set with preset values or set by the user. As a result, the throttling control can meet the needs of the user better or can meet the actual use condition of the host device50or the data storage device100better, and can achieve the object of the present invention.