Signal transmitting apparatus, power supplying system, and serial communication apparatus

A signal transmitting apparatus includes a sending part and a receiving part. The sending part converts each width of a plurality of digital input signals into a voltage in accordance with a predetermined weight, generates a send signal by adding voltages converted from the plurality of digital input signals, and outputs the send signal. The receiving part receives the send signal from the sending part, compares the send signal with a plurality of predetermined voltages, generates each of the digital input signals, and outputs each of the digital input signals.

TECHNICAL FIELD

This disclosure generally relates to a signal transmitting apparatus for multiplexing a plurality of digital signals and sending and receiving the plurality of digital signals through a single signal line, a power supplying system for conducting each of controls of actuating and stopping a plurality of power supplying devices, an output voltage, an output current, and operation modes of the plurality of power supplying devices through a communication part, and a serial communication apparatus for conducting a serial communication, especially by a half-duplex communication.

DESCRIPTION OF RELATED ART

Conventionally, since a signal line is provided per each signal in order to send and receive a plurality of signals, the number of signal lines has been increased proportional to the number of signals and wirings among devices for sending and receive signals become more complicate. As a result, the devices become larger and expenses are increased. Accordingly, a serial communication for sending receiving data by a single signal, in which the plurality of signals are aligned in chronological order, is conducted. The number of signal lines is remarkably reduced by applying the serial communication. On the other hand, since the serial communication sends a signal by, converting into a serial data, a parallel-serial converting circuit is required for a sending part and a serial-parallel converting circuit is required for a receiving part. Accordingly, the circuit size is enlarged, a device size becomes bigger, and expenses are increased.

Moreover, since the plurality of signals are sent by a time-share, a transmission rate becomes lower. Furthermore, in a case of the serial communication, at least three signal lines are required for a data signal, a clock signal used as a shift signal, a load signal for latching to convert the serial signal sent in chronological order into an original parallel signal. Thus, in a case of a few signals for a transmission, the number of signals cannot be reduced and the circuit size is enlarged even if the serial communication is applied. In this case, there is no advantage. Therefore, for example, the Japanese Laid-Open Patent Application No. 11-355255 discloses a multiplexed data transmission device in that the data signal, the clock signal, and the load signal are multiplexed and a wave height of a signal waveform is changed to send a multiplexed signal through a single signal line.

As described above, the number of the signal lines becomes one line. However, since a plurality of data sets are sent to a data line in serial in chronological order, time is required for convert serial data to a parallel signal. Thus, a higher data transmission cannot be achieved. Still, the parallel-serial converting circuit is required for the sending part, and the serial-parallel converting circuit is required for the receiving part.

FIG. 1is a block diagram illustrating a power supply apparatus being used conventionally and generally.

In a power supply apparatus100illustrated inFIG. 1, a power supplying part101is connected loads102through104. Each of the loads102through104receives a power supply from the power supplying part101. A controlling part105conducts various operation controls and condition settings such as an actuating operation and a stopping operation, a setting of an output voltage, a setting of an output current, and a switching operation for switching an operation mode from a regular mode to a low-power-consumption mode, with respect to the power supplying part101. Moreover, the power supplying part101monitors a present electric current consumption value and the output voltage for each of the loads102though104and sends monitoring information to the controlling part105. As a result, the controlling part105sends a new instruction to the power supplying part101. As described above, a large amount of information is sent and received mutually between the controlling part105and the power supplying part101.

FIG. 2is a block diagram illustrating a conventional power supplying apparatus having a configuration in that a controlling part controls a plurality of power supplying parts.

In a power supply apparatus110shown inFIG. 2, a first power supplying part112is connected to loads1athrough1c,a second power supplying part113is connected to loads2athrough2c,and a third power supplying part114is connected to loads3athrough3c,respectively. A controlling part111is connected to the first, second, and third power supplying parts112through114, and directly controls each of the first, second, and third power supplying parts112through114.

Recently, functions of electronic products are remarkably improved. Various circuits and components having various functions are used inside the electronic products. For example a large numbers of circuits and components such as a digital camera, a speaker, a microphone, a liquid crystal display unit, switches, a sending circuit, a receiving circuit, an audio circuit, a motor, an operating unit, a storage unit, and a like are used inside a cellular phone. Moreover, the digital camera itself mounted inside the cellular phone includes a large number of functional components.

In order to supply an electric power to a large number of circuits and components, for example, a voltage and current characteristics suitable for each of circuits and the components is required. Thus, it is difficult to conduct by one electric power circuit. In particular, since a power saving has been demanded, instead of supplying the electric power to all circuits inside the electric products, it becomes common to restrain power supplies to unused circuits and components based on a use condition of the electric product, and to minimize the power consumption of a power supply circuit itself for supplying the electric power to these circuits and components.

Moreover, an overcurrent preventing circuit and a short protecting circuit are provided to each of the power supplying parts112through114, so that an action is informed to each of the controlling parts105and110when the overcurrent preventing circuit and the short protecting circuit are activated and then, an operation is determined as the electric product. Therefore, conventionally, information sent and received between the controlling parts111and the power supplying parts112through114has been simply to control an activation and stop of the power supplying parts112through114. Recently, an amount of the information is significantly increased and as a result, the number of signal lines is increased. In addition, when the number of the power supplying parts112through114is increased, the number of signal lines is increased by the increase of the number of the power supplying parts112through114. This increase of the number of signal lines causes the electric products to be enlarged and an increase of an expense. In order to reduce the number of signal lanes between the controlling part111and the plurality of the power supplying parts112through114, the Japanese Laid-Open Patent Application No. 4-322140 discloses a power supply control system120in that a controlling unit including a CPU (Central Processing Unit) is connected to a plurality of power supplying units, as shown inFIG. 3.

The power supply control system120includes a plurality of power supplying units PS1through PS4, and a plurality of remote controllers RCD1through RCD4for controlling power ON and OFF of each of the plurality of power supplying units PS1through PS4and monitoring the plurality of power supplying units PS1through PS4. The power supply control system120further includes a power controller MCD for outputting serial data configuring instruction data of each of selecting, turning on, shutting down, and monitoring the power supplying units PS1through PS4with respect to each of the remote controllers RCD1through RCD4, and a serial bus SBUS connected between the power controller MCD and each of the remote controllers RCD1through RCD4. The serial bus SBUS transmits each instruction data from the power controller MCD to each of the remote controllers RCD1through RCD4and power monitor data from each of the remote controllers RCD1through RCD4to the power controller MCD.

However, in the convention system described above, since the power controller MCD is separated from the remote controllers RCD1through RCD4, ever if the convention system is realized by a minimum configuration, a serial bus is required. Therefore, it makes it difficult to minimize the system.

Conventionally, various methods for transmitting a digital signal by a serial communication have been known. One of typical methods is shown inFIG. 4throughFIG. 7.

InFIG. 4, a data signal SdA is the most common signal and shows data by a signal level. Data are extracted from the data signal SdA by using a synchronous signal SaA indicating a delimiter of a data block. In this method, two signals, that is, a data signal and a synchronization signal are required.

Next, inFIG. 5, the data signal SdB is a signal of which pulse width is modulated, and an interval of the data signal SdB is constant in that a pulse width when data shows “0” is different from a pulse width, when data shows “1”. In this method, an interval of code may be concerned but it is possible to easily conduct an asynchronous operation. In addition, inFIG. 6, the data signal SdC is a signal in a pulse position modulating method in that a temporal position of the pulse is changed. Data are sampled by the synchronous signal SaC as a time base. InFIG. 7, a data signal SdD is a signal corresponding the pulse width modulation described above to the pulse position modulation. It should be noted that the interval of code is not the same but the data signal SdD is an asynchronous signal and the synchronous signal is not needed.

FIG. 8is a schematic block diagram illustrating a conventional serial communication apparatus for conducing a half-duplex communication. In a serial communication apparatus120shown inFIG. 8, an host sending/receiving circuit121includes a first sending circuit part122, a first receiving circuit part123, and a first switching part124for conducting a sending right control. Similarly, a slave sending/receiving circuit125includes a second sending circuit part126, a second receiving circuit part127, and a second switching part128for conducting the sending right control. Basically, the first sending circuit part122is the same as the second sending circuit part126and the first receiving circuit part123is the same as the second receiving circuit part127.

In a case in that the host sending/receiving circuit121has a sending right, data are transmitted from the first sending circuit part122of the host sending/receiving circuit121to the second receiving circuit part127of the slave sending/receiving circuit125. When the sending right is moved to the slave sending/receiving circuit125, data are transmitted from the second sending circuit127of the slave sending/receiving circuit125to the first receiving circuit part123of the host sending/receiving circuit121.

However, as described above, conventionally, the synchronous signal in addition to the data signal is required. Even if the synchronous signal is not required, circuit configuration to generate a data signal from data and extract data from the data signal are complicated. Moreover, in order to conduct the half-duplex communication, the same as the host side is required for the slave side. Accordingly, a switching part for switching between a sending part and a receiving part is required. As a result, a circuit size and a circuit space become larger, and an expense is increased.

SUMMARY

In an aspect of this disclosure, there is provided a signal transmitting apparatus for multiplexing a plurality of digital signals and sending and receiving the plurality of digital signals through a single signal line, a power supplying system for conducting each of controls of actuating and stopping a plurality of power supplying devices, an output voltage, an output current, and operation modes of the plurality of power supplying devices through a communication part, and a serial communication apparatus for conducting a serial communication, especially by a half-duplex communication, in which the above-mentioned problems are eliminated.

In another aspect of this disclosure, there is provided a signal transmitting apparatus for transmitting a plurality of data sets by a single signal line without a parallel-serial conversion at a sending part and a serial-parallel conversion at a receiving part.

In another aspect of this disclosure, there is provided a power supplying system that can reduce an increase of the number of signal lines connecting a controlling part and a power supplying part even if the number of the power supplying parts is increased and an amount of information to send and receive between the power supplying parts and the controlling part.

In another aspect of this disclosure, there is provided a serial communication apparatus, which is minimized and realized by less expense in that a synchronous signal is not needed, each of a sending circuit and a receiving circuit at a host side and a slave side can be realized by a simple circuit configuration, a circuit load at the slave side can be reduced, and a switching part for switching between the sending circuit and the receiving circuit is not needed.

In another aspect of this disclosure, there is a provided a signal transmitting apparatus for sending and receiving a plurality of digital input signals input to the signal transmitting apparatus through a single signal line, the signal transmitting apparatus including: a sending part for converting each width of the plurality of digital input signals into a voltage in accordance with a predetermined weight, generating a send signal by adding voltages converted from the plurality of digital input signals, and outputting the send signal; and a receiving part for receiving the send signal from the sending part, comparing the send signal with a plurality of predetermined voltages, generating each of the digital input signals, and outputting the each of the digital input signals.

In another aspect of this disclosure, there is provided a power supplying system for supplying a power from a plurality of power supplying devices to each of a plurality of loads, the power supplying system including: a first power supplying device including a first power supplying part for supplying a power to at least one of the plurality of loads, a controlling part for conducting an operation control of the first power supplying part, and a first communicating part for sending and receiving a signal to and from the controlling part; and at least one second power supplying device including a second power supplying part for supplying a power to at least one of the plurality of loads, and a second communicating part for sending and receiving a signal to and from the second power supplying part, wherein the first communicating part and the second communicating part send and receive signals each other, and the controlling part conducts the operation control of the second power supplying part through the first communicating part and the second communicating part.

In another aspect of this disclosure, there is provided a power supplying system for supplying a power from a plurality of power supplying devices to each of a plurality of loads, the power supplying system including: a first power supplying device including a first power supplying part for supplying a power to at least one of the plurality of loads, a controlling part for conducting an operation control of the first power supplying part, and a first communicating part for sending and receiving a signal to and from the controlling part; and at least one second power supplying device including a second power supplying part for supplying a power to at least one of the plurality of loads, and a second communicating part for sending and receiving a signal to and from the second power supplying part, wherein the first communicating part and the second communicating part send and receive signals each other, and the controlling part conducts the operation control of the second power supplying part through the first communicating part and the second communicating part.

In another aspect of this disclosure, there is provided a serial communication apparatus for conducting a serial communication by a half-duplex communication between a first sending/receiving circuit and a second sending/receiving circuit in that at least one first sending/receiving circuit is connected to at least one second sending/receiving circuit through a transmission channel, wherein each of the first sending/receiving circuit and the second sending/receiving circuit includes: a sending circuit part for generating a serial data signal by superimposing a predetermined superimposing pulse over a send data signal having two values during a predetermined signal level, and outputting the serial data signal; and a receiving circuit part for receiving the serial data signal sent from the sending circuit part, and extracting the send data signal by extracting the superimposing pulse from the serial data signal.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, embodiments the present invention will be described with reference to the accompanying drawings.

First Embodiment

FIG. 9is a diagram showing a circuit configuration of a signal transmitting apparatus according to a first embodiment of the present invention. InFIG. 9, for the sake of convenience, a case of multiplexing and transmitting two digital input signals is illustrated.

InFIG. 9, a signal transmitting apparatus1includes a sending part2which converts amplitude of digital input signals Ai and Bi input to the signal transmitting apparatus1into corresponding voltage in accordance with a predetermined weight, and generates and outputs a send signal So1by adding each voltage converted from amplitude, and a receiving part3for receiving the send signal So1from the sending part2through a signal line5, for comparing the send signal So1with each of predetermined reference voltages Vt1through Vt3, and for generating and outputting digital input signals Ai and Bi based on a comparison result.

The sending part2includes an inversion amplifying circuit configured of an operational amplifier AMP1and resistors R1through R5. The digital input signal Ai is input to inverting input terminal of the operational amplifier AMP1through the resistor R1having an input resistance. The digital input signal Bi is input to the inverting input terminal of the operational amplified AMP1through the resistor R2having an input resistance. On the other hand, between a power voltage Vdd and an earth ground, the resistor R4and the resistor R5are connected n series, a connection portion for the resistors R4and R5is connected to a non-inverting input terminal of the operational amplifier AMP1, and a predetermined bias voltage Vs is input to the non-inverting input terminal of the operational amplifier AVP1. Moreover, the resistor R3having a feedback resistance is connected between an output terminal of the operational amplifier AMP1and an inverting input terminal and the output terminal of the operational amplifier AMP1is connected to the send terminal OUT of the sending part2. The send terminal OUT is connected to a receive terminal IN of the receiving part3by the signal line5.

Next, the receiving part3includes voltage comparators CMP1through CMP3, NAND circuits N1through N3, an inverter INV, and resistors R6through R9. The resistors R6through R9configure reference voltage generating circuits, the voltage comparators CMP1through CPM3configure voltage comparing circuits, and the NAND circuits N1through N3and the inverter INV configure logic circuits. A signal input to the receive terminal IN is input to each inverting input terminal of the voltage comparators CMP1through CPM3. The resistors R6through R9are connected in series between the power voltage Vdd and the earth ground. A connection portions of the resistor R6and the resistor R7is connected to the non-inverting input terminal of the voltage comparator CMP1, a connection portion of the resistor R7and resistor R8is connected to the nor-inverting input terminal of the voltage comparator CMP2, and a connection portion of the resistor R8and the resistor R9is connected to the non-inverting input terminal of the voltage comparator CMP3.

The output terminal of the voltage comparator CMP1is connected to the input terminal at one side of the NAND circuit N1, and the output terminal of the voltage comparator CMP2is an output terminal at one side of the receiving part3and is connected to the input terminal at another side of the NAND circuit N1. Moreover, the output terminal of the voltage comparator CMP2is connected to the input terminal at one side of the NAND circuit N2, and the output terminal of the voltage comparator CMP3is connected to the input terminal at another side of the NAND circuit2. The output terminals of the NAND circuits N1and N2are connected to relative input terminals of the NAND circuit N3, and the output terminal of the NAND circuit N3is the output terminal at another side of the receiving part3.

In this configuration, the voltage Vo of the send signal So1output from the send terminal OUT of the sending part2is expressed by the following a formula (1):
Vo=Vs−R3×{(VAi−Vs)/R1}+(VBi−Vs)/R1}}  (1)
In the formula (1), R1represents a resistance value of the resistor R1, R3represents a resistance value of the resistor R3, Vai represents a voltage at a high level or a low level of the digital input signal Ai, and Vbi represents a voltage at a high level or a low level of the digital input signal Bi.

The power voltage Vdd is 6V, the bias voltage Vs is 3V, the resistance value of the resistor R1is 15 kΩ, the resistance value of the resistor R2is 30 kΩ, and the resistance value of the resistor R3is 10 kΩ. In addition, in the digital input signals Ai and Bi, each voltage at the high level is 6V and is 0V at the low level. In this case, the output voltage Vo by each combination of signal levels of the digital input signals Ai and Bi becomes as shown inFIG. 10. In a case in that the bias voltage Vs is set to be half the power voltage Vdd, a resistance ratio of the resistor R1to the resistor R2is set to be 1:2, and the resistance value of the resistor R3is set to be equal to a combined resistance value when the resistor R1is connected to the resistor R2in parallel, as shown inFIG. 10, the output voltage Vo is obtained as an even voltage difference with respect to each combination of voltages of the digital input signal Ai and the digital input signal Bi. This relationship is stable even if the number of the input signals is increased.

That is, inFIG. 10, in a case of a state M1in that both the digital input signals Ai and Bi are the high level, the output voltage Vo becomes 0V of a predetermined value V1. And in a case of a state M2in that the digital input signal Ai is the high level and the digital input signal Bi is the low level, the output voltage Vo is 2V of a predetermined value V2. Moreover, in a case of a state M3in that the digital input signal Ai is the low level and the digital input signal Bi is the high level, the output voltage Vo is 4V of a predetermined value V3. Furthermore, in a case of a state MA in that the digital input signal Ai and Bi are the low level, the output voltage Vo is 6V of a predetermined value V4.

FIG. 11is a timing chart diagram showing a waveform of a signal of each part shown inFIG. 9.

InFIG. 11, in a section (a) of the low level of both the digital input signal Ai and the digital input signal Bi, the output voltage Vo is 6V. When the digital input signal Bi becomes the high level in a section (b), the output voltage Vo becomes 4V. When, the digital input signal Ai becomes the high level in a section (c), the output voltage Vo becomes 0V. Next, when the digital input signal Bi becomes the low level in a section (d), the output voltage Vo is 2V. After a section (d), in sections (e), (f), (g), (h), and (i), the voltage value of the output voltage Vo is changed each time the signal levels of the digital input signal Ai and the digital input signal Bi are changed. In addition, with respect to all combinations of the signal levels in the digital input signal Ai and the digital input signal Bi, the output voltage Vo output a different voltage value.

Next, in the receiving part3, each voltage value of the resistors R6through R9is set so that a reference value Vt1is 1V, a reference voltage Vt2is 3V, and a reference voltage Vt3is 5V. That is, the reference value Vt1is set to be an intermediate value of the output voltages Vo of the state M1and the state M2shown inFIG. 10, the reference value Vt2is set to be an intermediate value of the output voltages Vo of the state M2and the state M3shown inFIG. 10, and the reference value Vt3is set to be an intermediate value of the output voltages Vo of the state M3and the state M4shown inFIG. 10.

As seen fromFIG. 11, the same signal as the digital input signal Ai is output from the output terminal of the voltage comparator CMP2. When the output signal Ao is the high level, the sane signal as the digital input signal Bi is output from the output terminal of the voltage comparator CMP3and is output from the NAND circuit N2. Moreover, when the output signal Ao is the low level, the same signal as the digital input signal Bi is output from the output terminal of the voltage comparator CMP1and is output from the NAND circuit N1. The output signals of the NAND circuits N1and N2are synthesized by the NAND circuit N3, and the same signal as the digital input signal Bi is output as the output signal Bo.

As described above, in the signal transmitting apparatus1, the sending part2converts amplitude of the digital input signals Ai and Bi into a voltage in accordance with a predetermined weight [such as R3/R1in formula (1)], adds all converted voltages, generates different predetermined voltages V1through V4, respectively, and transmits a signal to the receiving part3. The receiving part3conducts a voltage comparison for the signal received from the sending part2by using the predetermined reference voltages Vt1through Vt3, generates the output signal Ao being the same as the digital input signal Ai and the output signal Bo being the same as the digital input signal Bi from the comparison result, and outputs the output signal Ao and the output signal Bo. Accordingly, it is possible to reproduce all digital input signals at the same time. Since the delay by the conventional serial-parallel conversion is eliminated, it is possible to conduct a signal process at higher speed.

In the first embodiment, the case of two digital input signals is illustrated and described. Since this case is just an example, the present invention is not limited to this case but can be applied to a plurality of digital input signals. Moreover, in the first embodiment, the case in that each of the resistance values is weighted by a multiple of two. Since this case is just an example, the present invention is not limited to this case.

Second Embodiment

In a case of sending a signal to a specific circuit and there is an enable signal to enable the specific circuit, if other control signals are multiplexed and transmitted only when the enable signal becomes active, it is possible to multiplex the control signals by a simple circuit. That is, in the first embodiment, the sending part2can multiplex and transmit the digital input signals Ai and Bi to the receiving part3only when the digital input signal Ai is the low level and the high level. This configuration will be described as a second embodiment of the present invention.

FIG. 12is a diagram illustrating a circuit configuration of a signal transmitting apparatus according to the second embodiment of the present invention. InFIG. 12, parts that parts that are the same as those shown inFIG. 9are given the same reference numbers. Also, inFIG. 12, for the sake of convenience, the case of multiplexing and transmitting two digital input signals is illustrated and described.

InFIG. 12, for example, the signal transmitting apparatus1aincludes a sending part2aand a receiving part2b.The sending part2aconverts amplitude of the digital input signal Bi when the digital input signal Ai is the row level, into each voltage in accordance with a predetermined weight, in which the amplitude is converted by a greatest weight n two digital input signals Ai and Bi. Also, the sending part2agenerates a send signal SoA by adding the converted voltages of the digital input signal Bi to the converted voltages of the low level of the digital input signal Ai. The receiving part3areceives a send signal SoA from the sending part2athrough the signal line5, compares the send signal SoA as a receive signal with each of predetermined reference voltages Vt4and Vt5, generates the digital input signals Ai and Bi based on a comparison result, and outputs the digital input signals Ai and Bi.

The sending part2aincludes NMOS (N-channel MOS) transistors M1and M2configuring switching circuits and resistors R11and R22configuring load resistances. The digital input signal Ai is input to a gate of the NTMOS transistor M1, and the digital input signal Bi is input to a gate of the NMOS transistor M2. On the other hand, the resistor R11and the NMOS transistor M1are connected in series between the power voltage Vdd and the earth ground, and a series circuit of the resistor R12and the NMOS transistor M2is connected to the NMOS transistor M1in parallel. A connection portion of the NMOS transistor M1and the resistors R11and R12is connected to a sending terminal OUT of the sending part2a.The sending terminal OUTa is connected to a receiving terminal Ina of the receiving part3aby the signal line5.

Next, the receiving part3aincludes voltage comparators CMP11and CMP12and resistors R13through R15. The resistors R13through R15configure reference voltage generating circuits, the voltage comparators CM11and CMP12configure voltage generating circuits, and the voltage comparators CMP11and CMP12configure voltage comparing circuits. Each wiring line connected to each output terminal of the voltage comparators CMP11and CMP12configures a pseudo logic circuit. A signal input to a receiving terminal INa is input to each inverting input terminal of the voltage comparators CMP11and CMP12. The resistors R13through R15are connected in series between the power voltage Vdd and the earth ground. A connection portion of the resistor R13and the resistor R14is connected to a non-inverting input terminal of the voltage comparator CMP11, and a connection portion of the resistor R14and the resistor R15is connected to a non-inverting input of the voltage comparator CMP12. The output terminal of the voltage comparator CMP11configures one output terminal of the receiving part3aand the output terminal of the voltage comparator CMP12configures another output terminal of the receiving part3a.

In this configuration described above, in a case in that the power voltage Vdd is set to be 4V and a resistance value of the resistor R11is the same as a resistance value of the resistor R12, an output voltage VoA corresponding to each combination of signal levels of the digital input signal Ai and Bi becomes as shown inFIG. 13. As seen fromFIG. 13, by setting the resistance value of the resistor R11to be the same as the resistance value of the resistor R12, amplitudes of the digital input signals Ai and Bi are evenly changed.

That is, inFIG. 13, in a case of a state M4ain that both the digital input signals Ai and Bi are the low level, the output voltage VoA becomes 4V of a predetermined value V3a.And in a case of a state M3ain that the digital input signal Ai is the Low level and the digital input signal Bi is the high level, the output voltage VoA becomes 2V of a predetermined value V2a.Moreover, in a case of a state M2ain that the digital input signal Ai is the high level and the digital input signal Bi is the high level an in a case of a state M1ain that both the digital input signals Ai and Bi are the high level, the output voltage VoA becomes 0V of a predetermined value V1a.

FIG. 14is a timing chart diagram showing2waveform of a signal of each part shown inFIG. 12. Each operation of parts shown inFIG. 12will be described in detail with reference toFIG. 14.

When the digital input signal Ai is the high Level (4V), the NMOS transistor M1as a switching device is turned on and 0V of the send signal SoA is output from the send terminal OUTa. When the digital input signal Ai becomes the low level (0V) 2V or 4V corresponding to the signal level of the digital input signal Bi is output from the send terminal OUTa as the send signal SoA. That is, in a case in that the digital input signal Ai is the low level, the send signal SoA becomes 4V when the digital input signal Bi is the low level (0V), and the send signal SoA becomes 2V when the digital input signal Bi is the high level (4V).

On the other hand, in the receiving part3a,the resistance values of the resistors R13through R15are set so that the reference voltage Vt4becomes 1V and the reference voltage Vt5becomes 3V, that is, the reference voltage Vt4becomes an intermediate value between the predetermined value V1aand the predetermined value V2abecomes an intermediate value between the predetermined V2aand the predetermined value V3a.As seen fromFIG. 14, the voltage comparator CMP11outputs the output signal Bo having a signal level corresponding to the comparison result from comparing the output voltage VoA and the reference voltage Vt5, and the output signal Bo becomes the same signal as the digital input signal Bi. Also, the voltage comparator CMP12outputs the output signal Ao having a signal level corresponding the comparison result from comparing the output voltage VoA and the reference voltage Vt4.

In a case in that the digital input signal Ai is the high level and the digital input signal Bi is multiplexed, inFIG. 12, simply, the signal level of the digital input signal Ai is inverted by and inverter and is input to the gate of the NMOS transistor M1. Alternatively, the NMOS transistors M1and M2may be replaced with a PMOS transistor. As described above, it is possible to transmit a signal by a simple circuit configuration in the case of multiplexing two signals.

The case of multiplexing two input signals is described with reference toFIG. 12throughFIG. 14. InFIG. 12throughFIG. 15, parts that are the same as those shown inFIG. 12are given the same reference numbers and the explanation thereof will be omitted. Differences fromFIG. 12will be described.

Different fromFIG. 12, inFIG. 15, an NMOS transistor M3and a resistor R21are additionally provided to the sending part2ashown inFIG. 12as a switching device. Moreover, instead of the resistors R13through R15in the receiving part3ashown inFIG. 12, resistors R22through R26are additionally provided, and the voltage comparators CMP13and CMP14and a logic circuit11are additionally provided to the receiving part3a.

InFIG. 15, the signal transmitting apparatus1bincludes a sending part2band a receiving part3b. The sending part2bconverts amplitude of each of the digital input signals Bi and Ci when the digital input signal Ai is the low level, into each voltage in accordance with a predetermined weight, in which the amplitude is converted by a greatest weight in three digital input signals Ai, Bi, and Ci. And the sending part2bgenerates a send signal SoB by adding each voltage of the digital input signals Bi and Ci to a voltage at the low level of the converted digital input signal Ai, and outputs the send signal SoB. The receiving part3breceives the send signal SoB from the sending part2bthrough the signal line5, compares the send signal SoB with each of predetermined Vt6through Vt9, generates the digital input signal Ai, Bi, and Ci based on the comparison result, and outputs the digital input signal Ai, Bi, and Ci.

The sending part2bincludes NMOS transistors M1through M3configuring a switching circuit, and resisters R11, R12, and R21each of which configures a load resistance. The digital input signal Ci is input to a gate of the NMOS transistor M3. Moreover, a series circuit of the NMOS transistor M2is connected to a series circuit of the resistor R12in parallel. A connection portion of the NMOS transistor M1and the resistors R11, R12, and R21is connected a sending terminal OUTb of the sending part2b.The sending terminal OUTb is connected to a receiving terminal INb of the receiving part3bby the signal line5.

Next, the receiving part3bincludes voltage comparators CMP11through CMP14, the resistors R22through R26, and a logic circuit11. The resistors R22through R26configure reference voltage generating circuits, and the voltage comparators CMP11through CMP13configure voltage comparing circuits. A signal input into the receiving terminal INb is input to each of the inverting input terminals of the voltage comparator CMP11through CMP14. The resistors R22through R26are connected in series between the power voltage Vdd and the earth ground. A connection portion of the resistor R22and the resistor R23is connected to a non-inverting input terminal of the voltage comparator, and a connection portion of the resistor R23and the resistor R24is connected to a non-inverting input terminal of the voltage comparator CMP12.

Moreover, a connection portion of the resistor R24and the resistor R25is connected to a non-inverting input terminal of the voltage comparator CMP13, a connection portion of the resistor R25and the resistor R26is connected to a non-inverting input terminal of the voltage comparator CMP14. Each output terminal of the voltage comparators CMP11through CMP14is connected to the logic circuit11. The logic circuit11generates each of the digital input signal Ai, Bi, and Ci from each output signal of the four voltage comparators CMP11through CMP14and outputs each of the output signals Ao, Bo, and Co from corresponding output terminals of the receiving part3b.

In this circuit configuration, in a case in that the power voltage Vdd is set to be 4V the resistor R11is set to be 10kΩ, the resistor R11is 15 kΩ, and the resistor R21is set to be 30 kΩ, output voltages VoB corresponding to combinations of the signal levels of the digital input signal Ai, Bi, and Ci. As seen fromFIG. 16, a resistance ratio of the resistance R12and the resistance R21is set to be 1:2, the resistor R12is connected to the resistor R21in parallel, and a combined resistance value is set to be approximately equal to a resistance value of the resistor R11, so that a voltage change of the output voltage VoB output from the sending terminal OUTb is made to be relatively greater.

On the other hand, each of the reference voltages Vt6through Vt9may be set to be an intermediate voltage of the output voltages VoB shown inFIG. 16. For example, in a case shown inFIG. 16, each resistance value of the resistors R22through R26is set so that the reference voltage Vt6becomes 1V, the reference voltage Vt7becomes 2.2V, the reference voltage Vt8becomes 2.7V, and the reference voltage Vt9becomes 3.5V. The logic circuit11generates each of the digital input signals Ai, Bi, and Ci from each output signal of the four voltage comparators CMP11through CMP14, and outputs the digital input signals Ai, Bi, and Ci as output signals Ac, Bo, and Co.

As described above, the signal transmitting apparatus1aaccording to the second embodiment, the sending part2aconverts amplitude of each digital input signal into a voltage in accordance with a predetermined weight only when a predetermined one input signal is the low level or the high level, generates different predetermined voltages by adding converted voltages, and transmits the different voltages to the receiving part3b.The receiving part3bconducts a voltage comparison to compare a signal received from the sending part3bwith each predetermined reference voltage, generates an output signal being the same as each of the digital input signals based on the comparison result, and outputs each output signal. Accordingly, the same effects as the first embodiment can be obtained in the second embodiment. Moreover, in a case in that only when an enable signal for enabling a specific circuit is active, other control signals are multiplexed and transmitted, it is possible to simplify a circuit configuration.

According to the present invention, in the signal transmitting apparatuses1,1a,and1b,since the amplitude of each of the plurality of the digital input signals is converted into a voltage by a predetermined weight, and voltages of converted digital input signals are added and are transmitted, it is possible to transmit information of the plurality of the digital input signals by a single signal line. Therefore, it is possible to reduce a space for wiring lines and an expense. Moreover, it is possible to simultaneously all digital input signals at the receiving parts3,3a,and3b,it is possible to eliminate a time loss for the conventional serial-parallel conversion, and it is possible to conduct a signal process at higher speed.

Moreover, in a case in that other digital input signals are transmitted only when the digital input signal having the greatest weight in the plurality of digital input signals is the signal level, which is either the high level or the low level, it is possible to realize and minimize a sending/receiving circuit by a simple configuration, and to reduce the expense of the sending/receiving circuit.

Third Embodiment

FIG. 17is a block diagram illustrating a power supplying system according to a third embodiment of the present invention.

InFIG. 17, the power supplying system1001includes a first power supplying unit1002for conducting a power supply to loads A1through Am (m is an integer where m>0), and a second power supplying unit1003for conducting a power supply to loads B1through Br (n is an integer where n>0). The first power supplying unit1002and the second power supplying unit1003are mutually connected by a communication line1004.

The power supplying unit1002includes a first power supplying part1011for conducting a power supply to the loads A1through Am, a controlling part1012for conducting an operation control of the first power supplying part1011, and a first complicating part1013for communicating with the second power supplying unit1003. Moreover, the second power supplying unit1003includes a second power supplying part1021for conducting a power supply to the loads B1through Bn, and a second communicating part1022for communicating with the first power supplying unit1002. The first communicating part1013and the second communicating part1022mutually send and receive a signal by using the communication line1004. The controlling part1012conducts the operation control of the first power supplying part1101and also conducts the operation control of the second power supplying part1021through the first communicating part1013and the second communicating part1022.

For example, the controlling part1012conducts various condition settings and operation controls such as a start and stop of the power supply, a voltage setting of a power to supply, a current setting of the power to supply, a switch from a regular operation mode to a low power consumption operation mode, and a like, with respect to the first power supplying part1011and the second power supplying part1021. In addition, the controlling part1012receives information for each of the loads A1through Am sent from the first power supplying part1011and the second power supplying part1021, for example, information such as a present current consumption value, an output voltage value, and a like, and sends a new instruction to the first power supplying part1011and the second power supplying part1021. As described above, the controlling part1012sends and receives information to and from the first power supplying part1011and the second power supplying part1021, mutually.

A signal between the controlling part1012and the first power supplying part1011is directly sent and received. A signal between the controlling part1012and the second power supplying part1021is sent and received through the first communicating part1013and the second communication part1022. The first communication part1013and the second communication part1022are mutually connected by the communication line1004. The first communicating part1013and the second communicating part1022may be connected by any kind of communication part. A well-known technology can be used and may be either wired or wireless The first power supplying unit1002corresponds to a first power supplying device in claims, and the second power supplying unit1003corresponds to a second power supplying device in claims. The first power supplying part1011corresponds to a first power supplying part in claims, and the first communicating part1013corresponds to a first communication part in claims. The second power supplying part1021corresponds to a second supplying part in claims, and the second communicating part1022corresponds to a second communicating part in claims.

By this configuration, in a case in that a small size power supplying system is formed due to a fewer number of loads for conducting the power supply, it is possible to minimize the power supplying system by configuring by the first power supplying unit1002alone. Moreover, in order to correspond to a product size such as the number of loads for conducting the power supply, it is possible to correspond to a case of conducting a complicated power supply by adding the second power supplying unit1003.

In addition, in order to control the second power supplying part1021, simply, only a signal line may be connected between the first communicating part1013and the second communication part1022, so that it is possible to easily wire lines within a product using the power supplying system1001. Moreover, a serial communication can be used for a communication between the first communicating part1013and the second communicating part1022, so that it is possible to reduce the number of signal lines. Therefore, it is possible to minimize the product using the power supplying system1001and reduce the expense. Furthermore, the communication between the first communicating part1013and the second communicating part1022can be realized by a radio transmission. Accordingly, the signal line is not needed, and it is possible to further minimize the power supplying system.

Next, inFIG. 17, a case in that a power supplying unit connected to the first power supplying unit1002is only the second power supplying unit1003is illustrated. Alternatively, a plurality of power supplying units may be connected to the first power supplying unit1002. In this case, the configuration shown inFIG. 17can be modified as shown inFIG. 18. InFIG. 18, a case in that two power supplying units are connected to the first power supplying unit1002is illustrated. InFIG. 18, parts that are the same as those shown inFIG. 17are given the same reference numbers and the explanation thereof will be omitted. Differences fromFIG. 17will be described.

Different from the configuration shown inFIG. 17, inFIG. 18, a third power supplying unit1005is additionally provided.

InFIG. 18, a power supplying system1101includes she first power supplying unit1002, the second power supplying unit1003, and the third power supplying unit1005for conducting the power supply to loads C1through Cp (p is an integer where p>0). The first power supplying unit1002, the second power supplying unit1003, and the third power supplying unit1005are connected to the communication line1004. The third power supplying unit1005includes a third power supplying part1031for conducting the power supply to loads C1through Cp, and a third communicating part1032for communicating with the first power supplying unit1002. The first through the third communicating parts1013,1022, and1032mutually communicate by using the communication line1004. The controlling part1012conducts the operation controls of the first power supplying part1011and the second power supplying part1021, and also conducts the operation control of the third power supplying part1031through the first communicating part1013and the third communicating part1032.

For example, the controlling part1012conducts various condition settings and operation controls such as a start and stop of the power supply, a voltage setting of a power to supply, a current setting of the power to supply, a switch from a regular operation mode to a low power consumption operation mode, and a like, with respect to each of the first, second, and third power supplying parts1011,1021, and1031. Also, the controlling part1012receives information for each of the loads A1through Am, Bi through Bn, and C1through Cp sent from the first power supplying part1011, the second power supplying part1021, and the third power supplying part1031, for example, information such as a present current consumption value, an output voltage value, and a like, and sends a new instruction to the first power supplying part1011, the second power supplying part1021, and the third power supplying part1031. As described above, the controlling part1012sends and receives information to and from the first power supplying part1011, the second power supplying part1021, and the third power supplying part1031, mutually.

A signal between the controlling part1012and the third power supplying part1031is received and sent through the first communicating part1013and the third communicating part1032. The first, second, and third communicating parts1013,1022, and1032are connected by the communication line1004. The first, second, and third communicating parts1013,1022, and1032may be connected by any kind of a communication part. A well-known technology can be used and may be either wired or wireless. The third power supplying unit1005corresponds to the second power supplying device in claims, the third power supplying part1031corresponds to the second power supplying part in claims, and the third communicating part1032corresponds to the second communicating part.

By this configuration, in order to correspond to the product size based on the number of loads for conducting the power supply, in addition to operating the first power supplying unit1002, the first, second, and third power supplying units are combined to use. Accordingly, by combining the first, second, and third power supplying units1002,1003, and1005, it is possible to realize a further complicated power supply.

Moreover, in order to control the third power supplying part1031, only the signal line may be simply connected between the first communicating part1013and the third communicating part1032. Therefore, it is possible to easily wire lines within the product using the power supplying system1101. Furthermore, a serial communication can be used for a communication between the first communicating part1013and each of the second communicating part1022and the third communicating part1032, so that it is possible to reduce the number of signal lines. Therefore, t is possible to minimize the product using the power supplying system and reduce the expense. In addition, a radio transmission can be used for a communication between the first communicating part1013and each of the second communicating part1022and the third communicating part1032, so that the signal line is not needed. Therefore, it is possible to further minimize the product using the power supplying system.

As described above through the communication line1004, an instruction from the controlling part1012provided to the first power supplying unit1002is sent to each of the power supplying units1003and1005. Accordingly, various conditions can be set for each of the power supplying units1003and1005. On the other hand, information from each of the power supplying units1003and1005is sent to the first power supplying unit1002. Then, the controlling part1012receives the information and generates a next Instruction. By this configuration, it is possible to realize the power supplying system1101by a simple configuration for any size of the product. Moreover, by using communication parts for an external communication of the power supply system1101, it is possible to control an option apparatus externally provided to the power supply system1101and a power supplying unit of a parallel operation of the same system.

As described above, the power supply systems1001and1101according to the third embodiment, the first power supplying unit1002is connected to at least one of other power supplying units by the communication line1004, and the operation control of the power supplying part within at least one power supplying unit is conducted. Accordingly, even if the number of the power supplying units is increase and an amount of information to send and receive between the power supplying units and the number of controlling part is increased, it is possible to reduce the number of signal lines to connect the controlling part and the power supplying units.

Fourth Embodiment

in the third embodiment, the controlling part1012controls each power supplying part. Some products using the power supplying system includes a controlling part for controlling various functions being included in the product and controls the mower supplying part by the controlling part. In this case, it is ineffective to provide a special controlling circuit for controlling the power supplying part. Accordingly, the controlling part1012may be configured as one controlling unit separated from the first power supplying unit1002. This configuration will be described as a fourth embodiment.

FIG. 19is a block diagram illustrating a power supplying system according to the fourth embodiment of the present invention. InFIG. 19, parts that are the same as those shown inFIG. 18are given the same reference numbers and the explanation thereof will be omitted. Differences fromFIG. 18will be described.

Different from the configuration shown inFIG. 18, inFIG. 19, the controlling part1012of the first power supplying unit1002is separately configured as a controlling unit1041, an interface part for connecting the power supplying unit1002and the controlling unit1041is provided to each of the first power supplying unit1002and the controlling unit1041. Accordingly, the first power supplying unit1002shown inFIG. 18is configured as a first power supplying unit1002ashown inFIG. 18, and the power supplying system1001shown inFIG. 18is configured as a power supplying system1001a.

InFIG. 19, the power supplying system1001aincludes the first power supplying unit1002a,the second power supplying unit1003, the third power supplying unit1004, and a function unit including the first, second, and third power supplying part1011,1021, and1031and a predetermined function. The power supplying unit1002aincludes a first interface part1015for interfacing between the first power supplying part1011and the controlling unit1041, and a first communicating part1013. In addition, a controlling part1042for conducting operation controls of the first, second, and third power supplying parts1011,1021, and1031, and the function unit1045, and a second interface part1043for interfacing with the first power supplying unit1002a.

The first and second interface parts1015and1043are connected each other and the first interface part1015and the first communicating part1013are connected each other. The controlling part1042and the function unit1045send and receive a signal directly each other. The controlling part1042sends and receives a signal to and from the first power supplying part1011through the second interface part1043and the first interface part1015. Moreover, the controlling part1042sends and receives a signal to and from the second power supplying part1012through the second interface part1043, the first interface part1015, the first communicating part1013, the communication line1004, and the second communicating part1022. Also, the controlling part1042sends and receives a signal to and from the third power supplying part1031through the second interface part1043, the first interface part1015, the first communicating part1013, the communication line1004, and the third communicating part1032.

The controlling part1042conducts various condition settings and operation controls such as a start and stop of the power supply, a voltage setting of a power to supply, a current setting of the power to supply, a switch from a regular operation mode to a low power consumption operation mode, and a like, with respect to each of the first, second, and third power supplying parts1011,1021, and1031. Also, the controlling part1042receives information for each of the loads A1through Am, B1through Bn, and C1through Cp sent from the first power supplying part1011, the second power supplying part1021, and the third power supplying part1031, for example, information such as a present current consumption value, an output voltage value, and a like, and sends a new instruction to the first power supplying part1011, the second power supplying part1021, and the third power supplying part1031. As described above, the controlling part1012sends and receives information to and from the first power supplying part1011, the second power supplying part1021, and the third power supplying part.1031, mutually.

As described above, the power supplying system1001ain the second embodiment conducts the operation control to each of the power supplying parts1011,1021, and1031of the power supplying units1002a,1003, and1005by separately providing the controlling unit1041, and also sends and receives a signal with respect to the function unit1045so as to conduct the operation control. Accordingly, by the configuration in that a controlling part for controlling the entire product or a controlling part for controlling another function other than a power source serves as a controlling part for controlling each power supplying part of each power supplying unit, it is possible to further minimize the configuration of the power supplying system1001aand to further reduce the expense.

In the fourth embodiment, the first interface part1015and the second interface part1043are provided in the power supplying system1001a.Alternatively, if conditions such as input/output voltage levels, current driving abilities, and a like of the controlling part1042corresponds to those of the first power supplying part1011and the first communicating part1013, the first interface1015and the second interface part1043are not needed. Accordingly, the controlling part1042maybe directly connected to the first power supplying part1011and the first communicating part1013.

As seen from the above-explanation, according to the power supplying system according to the third and fourth embodiments of the present invention, the first power supplying part directly controlled from the controlling part is combined with at least one second power supplying part controlled from the controlling part through the first communicating part and the second communicating part. Therefore, it is possible to realize a preferable power supply from a small size of the power supplying system to a large size of the power supplying system. Moreover, since the first communicating part and the second communicating part conduct a communication each other to send and receive a signal, the number of signal lines is not increased even in the large size power supplying system. It is possible to minimize the power supplying system and reduce the expense.

Moreover, the controlling unit is provided to conduct the operation control of the first power supplying part in the first power supplying unit is conducted, and also the operation control of the second power supplying part in the second power supplying unit. Accordingly, the controlling parts being used in the product can be partially used. Therefore, it is possible to further minimize the power supplying system and reduce the expense.

Fifth Embodiment

FIG. 20is a schematic block diagram illustrating a serial communication apparatus according to a fifth embodiment of the present invention.

InFIG. 20, the serial communication apparatus2001conducts a serial communication by a half-duplex communication between the host unit HC and slave unit SC, and includes a host sending/receiving circuit2002, and a slave sending/receiving circuit2003. The host sending/receiving circuit2002is connected to the host unit HC and the slave sending/receiving circuit2003is connected to the slave unit SC. The host sending/receiving circuit2002and the slave sending/receiving circuit2003are connected each other by a transmission channel2004for a transmission of a serial signal. The host sending/receiving circuit2002corresponds to a first sending/receiving circuit in claims, and the slave sending/receiving circuit2003corresponds to a second sending/receiving circuit in claims.

The host sending/receiving circuit2002includes a first sending circuit part2011and a first receiving circuit part2012. The slave sending/receiving circuit2003includes a second sending circuit part2003and a second receiving circuit part2014. The first sending circuit part2011and the first receiving circuit part2012are connected to the second sending circuit part2013and the second receiving circuit part2014by the transmission channel2004. In a case of sending data from the host sending/receiving circuit2002to the slave sending/receiving circuit2003, a serial data signal is sent to the slave sending/receiving circuit2003from the first sending circuit part2011through the transmission channel2004, and the second receiving circuit part2014extracts data from an signal input through the transmission channel2004.

Moreover, when date are sent from the slave sending/receiving circuit2003to the host sending/receiving circuit2002, a no-data signal is sent from the first sending circuit part2011to the slave sending/receiving circuit2003through the transmission channel2004. The second sending circuit part2013is connected to the second receiving circuit part2014. The second sending circuit part2013writes data by superimposing a pulse over the no-data signal input through the transmission channel2004, and sends a serial data signal, in which the data are written, to the host sending/receiving circuit2002through the transmission channel2004. The first receiving circuit part2012extracts the data from a signal input through the transmission channel2004.

FIG. 21is a diagram illustrating a circuit configuration of the first sending circuit part2011shown inFIG. 20according to the fifth embodiment of the present invention.FIG. 22is a timing chart diagram showing a waveform of a signal of each part shown inFIG. 21. The first sending circuit part2011will be described with reference toFIG. 21andFIG. 22.

An output data signal SDo51and a clock signal CLK are input to the first sending circuit part2011shown inFIG. 21from the host unit HC. The first sending circuit part2011generates a serial output signal So51corresponding to the output data signal SDo51and outputs the serial output signal So51to the transmission channel2004. The clock signal CLK has a frequency two times as much as an output timing of the output data signal SDo51, and synchronizes the output data signal SDo51.

The first sending circuit part2011includes a T52delaying circuit2021for delaying the clock signal CLK by a predetermined time T52, a T51delaying circuit2022for further delaying an output signal S51or the T52delaying circuit2021by a predetermined time T51, a superimposing pulse generating circuit2023for generating a superimposing pulse signal S53from the output signal S51of the T52delaying circuit2021and the output signal S52of the T51delaying circuit2022, a T53signal generating circuit2024for generating a pulse signal S55of a predetermined pulse width T53by dividing the clock signal CLK into two frequencies, and an output signal generating circuit2025for generating the serial output signal So51from a superimposing pulse signal S54, in which the superimposing pulse signal S53is superimposed by corresponding to the output data signal So51, and the pulse signal S55. The T51delaying circuit2022corresponds to a first T51delaying circuit in claims, the superimposing pulse generating circuit2023corresponds to a first superimposing pulse generating circuit in claims, and the output signal generating circuit2025corresponds to a first output signal generating circuit in claims.

The T52delaying circuit2021includes a resistor R51, a capacitor C51, and a buffer gate BUF51. The capacitor C51is connected between one end of the resistor R51and the earth ground, and the clock signal CLK is input to another end of the resistor R51. Moreover, a connection portion of the resistor R51and the capacitor C51is connected to an input terminal of the buffer gate BUF51. The output signal S51of the T52delaying circuit2021becomes a signal in which the clock signal CLK is delayed by the time T52as shown inFIG. 22. The time T52to be delayed is determined by a threshold voltage Vt51for the resistor R51, the capacitor C51, and the buffer gate BUF51.

Moreover, the T51delaying circuit2022includes a resistor R52, a capacitor C52, and an inverter INV51. The resistor R52and the capacitor C52are connected in serial at an output terminal of the T52delaying circuit2021, that is, between an output terminal of the buffer gate BUF51and an earth ground. In addition, a connection portion of the resistor R52and the capacitor C52is connected to an input terminal of the inverter INV51. The output signal S52of the T51delaying circuit2022inverts the output signal S51of the T52delaying circuit2021as shown inFIG. 22, and becomes a signal being delayed by the time T51. The time T51to be delayed for the T5delaying circuit2022is determined by a threshold Vt52for the resistor R32, the capacitor C52, and the inverter INV51.

The superimposing pulse generating circuit2023includes an AND circuit AN51. The output signal S51of the T52delaying circuit2021and the output signal S52of the T51delaying circuit2022are input to input terminals of the AND circuit AN51, respectively. As shown by the superimposing pulse signal S53inFIG. 22, from the output terminal of the AND circuit AN51, the superimposing pulse is created at intervals of one period of the clock signal CLK one by one.

The T53signal generating circuit2024includes a ½ dividing circuit configured of a D flip flop DFF51. The clock signal CLK is input to a clock input terminal CK of the D flip flop DFF51. An output terminal Q s inverted when the clock signal CLK is raised from the low level to the high level, and as shown by the signal S55inFIG. 22, the T53signal generating circuit2024generates a signal having the pulse width T53being inverted at intervals of the time T33, and outputs the signal.

The output signal generating2025Includes an AND circuit AN52and ExOR (Exclusive OR) circuit EXC51. The output data signal SDo51and the output signal S53of the superimposing pulse generating circuit2023are input to two input terminals of the AND circuit AN52, respectively. An output terminal of the AND circuit AN52is connected to one input terminal of the ExOR circuit EXC51. The output signal S55of the T53signal generating circuit2024is input to another input terminal of the ExOR circuit EXC51. The output signal generating circuit2025determines a presence or absence of a superimposing pulse of the output signal S53in response to the output data signal SDo51each time the signal level of the out put signal S55is charged, and generates the serial output signal So51as shown inFIG. 22.

Next,FIG. 23is a diagram illustrating a circuit configuration of the first receiving circuit part2012inFIG. 20.FIG. 24is a timing chart diagram showing a waveform of each part inFIG. 23. The first receiving circuit part2012will be described withFIG. 23andFIG. 24.

The first receiving circuit Dart2012inFIG. 24extracts data from a serial input signal Si51input from the transmission channel2004and outputs the data as an input data signal SDi51to the host unit EC.

The first receiving circuit part2012includes a T51eliminating circuit2031for eliminating a superimposing pulse from the serial input signal Si51an input signal delaying circuit2032for delaying by more than a time of the serial input signal Si51(T51+T52) while eliminating the superimposing pulse, a superimposing pulse extracting circuit2033for extracting the superimposing pulse from the serial input signal Si51, an output signal S12of the T51eliminating circuit2031, an output signal S14of the input signal delaying circuit2032, and a data extracting circuit2034for extracting a data signal from an output signal S17of the superimposing pulse extracting circuit2033and outputting the data signal as the input data signal SDi51to the host unit HC. Moreover, the T51eliminating circuit2031corresponds to a first T1eliminating circuit in claims, the input signal delaying circuit32corresponds to an input signal delaying circuit in claims, the superimposing pulse extracting circuit2033corresponds to a first superimposing pulse extracting circuit in claims, and the data extracting circuit2034corresponds to a first data extracting circuit in claims.

The T51eliminating circuit2031includes a resistor R11, a capacitor C11, and a buffer gate BUF11. The capacitor C11is connected between one end of the resistor R11and the earth ground, and the serial input signal Si51is input to another end of the resistor R11. Moreover, a connection portion of the resistor R11and the capacitor C11is connected to an input terminal of the buffer gate BUF11. A signal at a connection portion of the resistor R11and the capacitor C11is a signal S11.

As seen fromFIG. 24, by the T51eliminating circuit2031, the superimposing pulse of the serial input signal Si51is eliminated, and are original signal of the pulse width T53is taken out and output as the output signal S12. The shorter the pulse width T51of the superimposing pulse, the smaller a time constant of the T51eliminating circuit2031becomes. Accordingly, it is possible to easily eliminate the superimposing pulse. Moreover, since a phase difference between the output signal S12of the T51eliminating circuit2031and the serial input signal Si51becomes smaller, it is preferable when the pulse width T51of the imposed pulse is shorter.

The input signal delaying circuit2032includes a resistor R12, a capacitor C12, and a buffer gate BUF12. The capacitor C12is connected to one end of the resistor R12and an earth ground, and the serial input signal Si51is input to the resistor R12. Moreover, a connection portion of the resistor R12and the capacitor C12is connected to an input terminal of the buffer gate BUF12. A signal data connection portion of the resistor R12and the capacitor C12is a signal S13.

As seen fromFIG. 24, since a time constant of the input signal delaying circuit2032is set to be greater then the time constant, the output signal S14of the input signal delaying circuit2032is a signal in that the superimposing pulse is eliminated from the serial input signal Si51and the serial input signal Si51is delayed by more than a time (T51+T52). InFIG. 24, a voltage Vt11shows a threshold voltage of the buffer gate BUF11and the voltage Vt12is a threshold voltage of the buffer gate BUF12.

The superimposing pulse extracting circuit2033includes an ExNOR (Exclusive NOR) circuit EXN11, an ExOR circuit EXC11, and an AND circuit AN11. The serial input signal Si51and the output signal S14of the input signal delaying circuit2032are corresponded and input to two input terminals of the ExNOR circuit EXN11. The output terminal of the T51eliminating circuit2031and the output terminal of the input signal delaying circuit2032are corresponded and connected to two input terminals of the ExOR circuit EXC11.

The output terminal of the ExNOR circuit EXN11and the output terminal of the ExOR circuit EXC11are corresponded and connected to two input terminals of the AND circuit AN11. An output signal S15is the output signal of the ExOR circuit EXC11, an output signal S16is the output signal of the ExNOR circuit EXN11, and an output signal S17is the output signal of the AND circuit AN11. As seen fromFIG. 24, an extracted superimposing pulse is output as the output signal S17from the AND circuit AN11.

The data extracting circuit2034includes three D flip flop DFF11through DFF13, an inverter INV11, and an ExOR circuit EXC12. The output signal S17of the super imposing pulse extracting circuit2033is input to a clock signal input terminal CK of the D flit flop DFF11. An inverting output terminal QB of the D flip flop DFF11is connected to a data input terminal D of the D flip flop DFF11. In addition, an output terminal Q of the D flip flop DFF11is connected to a data input terminal D of the D flip flop DFF12.

Furthermore, the output terminal Q of the D flip flop DFF12is connected to a data input terminal D of the D flip flop DFF13. An output terminal of the ExOR circuit EXC11is connected to the D flip flop DFF12and the clock signal input terminal CK of the D flip flop DFF13. The output terminals Q of the D flip flop DFF12and the D flip flop DFF13are corresponded and connected to two input terminals of the ExOR circuit EXC12.

A output signal S18is the output signal of the inverter INV11and output signals S19through S21are the output signals from the output terminals Q of the D flip flop DFF11through DFF13.

InFIG. 24, the ExOR circuit EXC12outputs a signal having the low level when the signal levels of the output signal S20and the output signal S21are corresponded to each other, and the ExOR circuit EXC12outputs a signal having the high level when the signal levels of the output signal S20and the output signal S21are not corresponded to each other. Accordingly, the input data signal SDi51becomes the high level while the superimposing pulse is superimposed over the serial input signal Si51.

FIG. 25is a diagram illustrating another circuit configuration of the input signal delaying circuit2032shown inFIG. 24. Since the superimposing pulse is eliminated by the T51eliminating circuit2031, it is possible to generate a signal S14shown inFIG. 24by delaying the output signal S12of the T51eliminating circuit2031. InFIG. 25, a circuit example utilizing a signal delay until an input change of Inverters appears is illustrated. Four Inverters INV12through INV15are connected in series. It is possible to obtain a necessary delay time by increasing the number of inverters. InFIG. 25, in the input signal delaying circuit2032, the number of inverters, which are connected in series so as not to invert the signal level of the output signal With respect to the input signal, is even number. Moreover, the input signal delaying circuit2032is not limited to the circuit shown inFIG. 25but can be a monostable multivibrator using a CR or a delaying circuit such a shift transistor or a like.

FIG. 26is a diagram illustrating a circuit configuration of the slave sending/receiving circuit shown inFIG. 20.FIG. 27is a timing chart showing a waveform of each part shown inFIG. 26. The slave sending/receiving circuit2003will be described with reference toFIG. 26andFIG. 27.

InFIG. 26, the second receiving circuit part2014extracts data from the serial input signal Si52input from the transmission channel and outputs as the input data signal SDi52to the slave unit SC.

The second receiving circuit part2014includes a T51eliminating circuit2041for eliminating the superimposing pulse from the serial input signal Si52, a input signal delaying circuit2042for outputting an output signal S31of the T51eliminating circuit2041by delaying by more than a time (T51+T52), a superimposing pulse extracting circuit2043for extracting the superimposing pulse from the serial input signal Si52, the output signal S31of the T51eliminating circuit2041, and the output signal S32of the input signal delaying circuit2042, and a data extracting circuit2044for extracting a data signal from the output signal of the superimposing pulse extracting circuit2042and outputting the data signal as the input data signal SDi52.

The second receiving circuit part2014has a circuit configuration similar to the first receiving circuit part2012shown inFIG. 23, and the explanation thereof will be omitted. The T51eliminating circuit2041corresponds to a second T1eliminating circuit in claims, the input signal delaying circuit2042corresponds to an input signal delaying circuit in claims, the superimposing pulse extracting circuit2043corresponds to a second superimposing pulse extracting circuit in claims; and the data extracting circuit2044corresponds to a second data extracting circuit in claims.

Next, the second sending circuit part2013includes a T51delaying circuit2051for delaying the output signal S32of the input signal delaying circuit2042by a time T51, a superimposing pulse generating circuit2052for generating and outputting a superimposing pulse signal S34from the output signal S32of the input signal delaying circuit2042and the output signal S33of the T51delaying circuit2051, and an output signal generating circuit2053for generating a serial output signal So52and outputting the serial output signal So52to the transmission channel2004. The T51delaying circuit2051corresponds to a second T51delaying circuit in claims, the superimposing pulse generating circuit2052corresponds to a second superimposing pulse generating circuit in claims, and the output signal generating circuit2053corresponds to a second output signal generating circuit in claims.

The T51delaying circuit2051includes a resistor R32, a capacitor C22, and an inverter INV26. The capacitor C22is connected to between one and of the resistor R32and an earth ground, and an output signal S32of the input signal delaying circuit2042is input to another end of the resistor R32. Moreover, a connection part of the resistor R32and the capacitor C22is connected to an input terminal of the inverter INT26. As seen fromFIG. 27, the T51delaying circuit2051delays the output signal S32of the input signal delaying circuit2042by the delay time T51and also inverts the signal level to output the output signal S32as the output signal S33.

The superimposing pulse generating circuit2052includes an ExNOR circuit EXN22. An input terminal and an output terminal of the T51delaying circuit2051correspond and are connected to two input terminals of the ExNOR circuit EXN22. From an output terminal of the ExNOR circuit EXN22, the output signal S34, which is formed by generating the superimposing signal one by one at intervals of half period of the serial input signal Si52, is output.

The output signal generating circuit2053includes an AND circuit AN22having three input terminals, a NAND circuit NA21having three input terminals, a PNP transistor Tr21, and an NPN transistor Tr22. In the AND circuit AN22and the NAND circuit NA21, the output signal S34of the superimposing pulse generating circuit2052is input to each of first input terminals and the output data signal SDo52is input to each of second input terminals. Furthermore, the output signal S31of the T51eliminating circuit2041in the second receiving circuit part2014is input to a third input terminal of the AND circuit AN22, and a signal, in which the signal level of the output signal S31of the T51eliminating circuit2041is inverted, is input to a third input terminal of the NAND circuit NA21.

An output terminal of the AND circuit AN22is connected to a base of the NPN transistor Tr22, and an output terminal of the NAND circuit NA21is connected to a base of the PNP Transistor Tr22. The PNP transistor Tr21and the NPN transistor Tr22are connected in series between the power voltage Vdd and an earth ground, and the serial output signal So52is output from a connection portion of the PNP transistor Tr21and the NPN transistor Tr22to the transmission channel2004. The AND circuit AN22outputs a signal having the high level when both the serial input signal Si52and the output data signal SDo52have the high level, and the NPN transistor Tr22turns ON to lower the signal level of the serial output signal So52.

The NAND circuit NA21outputs a signal having the low level when the serial input signal Si52is the low level and the output data signal SDi52is the high level, and the PNP transistor Tr21turns ON to raise the signal level of the serial input signal Si52. As described above, the second sending circuit part2013generates the serial output signal So52by superimposing the superimposing pulse over the serial input signal So52. In the serial output signal So52output from the second sending circuit part2013inFIG. 26, a location where the superimposing pulse is superimposed is Later than approximate time (T52+T51) from a start point. Since the time T51is sufficiently smaller than the time T52, T52≈T51+T52can be expressed. Accordingly, the serial output signal So52can be sufficiently received by the first receiving circuit party2012described above.

The times T51through T53well be described above.

FIG. 28AthroughFIG. 28Care diagrams illustrating the serial output signal output from the transmission channel.

In the serial output signal shown inFIG. 28A, both a time point of changing from the low level to the high level and a time point of changing from the high level to the low level in a repeating signal repeating a pulse width having the time T53are a start point.

When the output data signal is “1”, at a time point when the time T52passes from the start point, a pulse, which has a pulse width having the time T51and in which the signal level is inverted, is generated. When the output data signal is “0”, the pulse having the time T51is not generated. In addition, the time T53shows a term from the start point to the high level or the low level.

Relationships among the times T51through T53satisfy the following condition 1:
T51<T52<T53 and (T51+T52)<T53   (condition 1).

The smaller the time T51as much as possible, the easier a sending/receiving circuit can be configured. Preferably, the times T51through T53satisfy the following condition 2:
T51<<T52<T53   (condition 2).

Moreover, if the time53is two times shorter than the time T52, the sending/receiving circuit can be easily configured. Preferably, the following condition 3 is satisfied:
(T51+T52)<T53/2   (condition 3),

FIG. 28Billustrates a serial output signal in that a time point of changing from the low level to the high level in the repeating signal is set as the start point. In this case, a pulse width having T53is a term of the high level of the repeating signal. On the other hand, if the start point is a time point of changing from the high level to the low level, the pulse width having the time T53becomes a term of the low level of the repeating signal.

FIG. 28Cillustrates a serial output signal in that a time point of changing from the low level to the high level every two periods of the repeating signal is set as the start point.

Various settings of the start point can be considered other than the start points shown inFIG. 28A,FIG. 28B, andFIG. 28C. Preferably, the start point may be set so as to satisfy the above conditions 1 through 3 based on a transmission system being used.

FIG. 29is a diagram illustrating another circuit configuration of the first receiving circuit.FIG. 30is a timing chart diagram showing a waveform of a signal of each part shown inFIG. 29. InFIG. 29, parts that are the same as those shown inFIG. 23are given the same reference numbers, and an explanation thereof will be omitted. Different points from the circuit configuration of the first receiving circuit2012inFIG. 23will be described.

Differently from the circuit configuration shown inFIG. 23, inFIG. 29, a circuit configuration of the data extracting circuit2034inFIG. 23is changed.

The data extracting circuit2034inFIG. 29includes a D flip flop DFF11through DFF13, and a down counter DC31configured by an inverter INV11and a PLL (Phase-Locked Loop). Connections to the D flip flop DFF11are similar to the connections inFIG. 23, and connections to the D flip flops DFF12, DFF13, and the ExOR circuit EXC12are similar to the connections other than each clock signal input terminal CK of the D flip flops DFF12and DFF13.

An internal clock signal CLKi, in which the clock signal CLK is divided into four, is supplied from an output terminal Q2of the down counter DC31being an output of the PLL to each clock signal input terminal CK of the D flip Flops DFF12and DFF13. Accordingly, as shown inFIG. 30, an output signal S20of the D flip flop DFF12and an output signal S21of the D flip flop DFF13synchronize when the internal clock signal CLKi rises and become a signal in that the output signal of the D flip flop DFF11is shifted.

The output signal S17of the superimposing pulse extracting circuit2033is input to a reset input terminal R of the down counter DC31, and the clock signal CLK is locked so as to generate four clocks during the pulse width having the time T53. Accordingly, the internal clock signal CLKi output from the output terminal Q of the down counter DC31being the output of the PLL becomes a signal having two times frequency as much as a basic frequency of the serial input signal Si51. As seen fromFIG. 30, the ExOR circuit EXC12outputs a signal being the low level when the signal levels of the output signals S20and S21are corresponded to each other, and outputs a signal being the high level when the signal levels of the output signals S20and S21are not corresponded to each other. As seen from the input data signal SDi51shown inFIG. 30, the input data signal SDi51, which becomes the high level in a term in which the serial input signal Si51is superimposed over the serial input signal Si51, can be obtained.

As described above, according to the fifth embodiment of the present invention, in the serial communication apparatus, “1” and “0” of data are represented by a presence and absence of the superimposing pulse having a shorter pulse width than the time T52in the pulse width having the time T53which starts from a predetermined start point, at a time point in which the time T52shorter than the time T53passes from the start point. Accordingly, a synchronization signal is not required, and it is possible to realize sending/receiving circuits at an host side and a slave side by a simple circuit configuration. And it is possible to reduce a circuit size at the slave side, and a switching part for switching to send or receive is not required. It is possible to minimize the serial communication apparatus and reduce the expense. Moreover, it is not required for the slave sending/receiving circuit at the slave side to generate a clock signal. Therefore, it is possible to further simplify the circuit configuration.

Sixth Embodiment

FIG. 31is a diagram illustrating a circuit configuration of the slave sending/receiving circuit of the serial communication apparatus according to a sixth embodiment of the present invention.FIG. 32is a timing chart diagram showing a waveform of a signal of each part shown inFIG. 31. InFIG. 32, reference numbers are changed regarding the slave sending/receiving circuit2003and the second sending circuit part2013inFIG. 20. InFIG. 32, parts other than the slave sending/receiving circuit2003and the second sending circuit part2013inFIG. 20are the same as those shown inFIG. 26and are given the same reference numbers, and an explanation thereof will be omitted. Different points from the circuit configuration inFIG. 26will be described.

Differently from the configuration inFIG. 26, inFIG. 31, the circuit configuration of the superimposing pulse generating circuit2052inFIG. 26is changed to be a superimposing pulse generating circuit2052a,and the circuit configuration of the output signal generating circuit2053is changed to be an output signal generating circuit2053a.Thus, the second sending circuit part2013inFIG. 26is shown as a second sending circuit part2013a,and the slave sending/receiving circuit2003is shown as a slave sending/receiving circuit2003a.

InFIG. 31, the slave sending/receiving circuit2003aIncludes the second sending circuit part2013aand the second receiving circuit part2014. The second receiving circuit part2014is the same as that inFIG. 7and an explanation thereof will be omitted.

The second sending circuit part2013aincludes a T51delaying circuit51, a superimposing pulse generating circuit2052afor generating a superimposing pulse signal S34afrom the output signal S32of the input signal delaying circuit2042and the output signal S33of the T51delaying circuit2051, and an output signal generating circuit2053afor generating the serial output signal So52and outputting the serial output signal So52to the transmission channel2004. The superimposing pulse generating circuit2052acorresponds to a second superimposing pulse generating circuit in claims, and the output signal generating circuit2053acorresponds to a second output signal circuit.

The superimposing pulse generating circuit2052aincludes an AND circuit AN31. An input terminal and an output terminal of the T51delaying circuit2051are corresponded and connected to two input terminals of the AND circuit AN31. An output signal S34a,which is formed by generating every high level term of the serial input signal Si52one by one, is output from the output terminal of the AND circuit AN31.

The output signal generating circuit2053aincludes the AND circuit AN32and the NPN transistor Tr31. The output signal S34aof the superimposing pulse generating circuit2052ais connected to one input terminal of the AND circuit AN32and the output data signal SDo52is connected to another input terminal of the AND circuit AN32. The output terminal of the AND circuit AN32is connected to a base of the NPN transistor Tr31, and the NPN transistor Tr31is connected between the input terminal where the serial input signal Si52and an earth ground. An output signal S36ais the output signal of the ANTD circuit AN32.

In this configuration, when the output signal S36aof the AND circuit AN32becomes the high level, the NPN transistor Tr31turns ON to lower the signal level of the serial input signal Si52. Therefore, as shown inFIG. 32, it is possible to generate the serial output signal So52in which the superimposing pulse is superimposed over the serial input signal. As seen fromFIG. 32, the second sending circuit part2013ainFIG. 31superimposes the superimposing pulse over the serial input signal Si52only when the serial input signal Si52is the high level. In a case of sending the data signal from the second sending circuit part2013ato the host unit HC, a data signal density becomes half a case of sending the data signal from the host sending/receiving circuit2003to the slave sending/receiving circuit2003. In this case, the serial output signal So52is the same as that shown inFIG. 28B.

As described above, according to the sixth embodiment of the present invention, in the serial communication apparatus2003a,the second sending circuit part2013asuperimposes the superimposing pulse over the serial input signal Si32only when the serial Input signal Si52is the high level. Therefore, it is possible to obtain the same effect as the fifth embodiment. In addition, when there is no data from the slave sending/receiving circuit2003, the location of the start point is set every one period of the repeating signal. Thus, it is possible to further simplify the circuit configuration of the sending circuit part2013ain the slave sending/receiving circuit2003.

According to the fifth embodiment and the sixth embodiment, in the serial communication apparatuses2003and2003a,the reference pulse signal having the pulse width having the time T53and starting from a predetermined start point represents “1” and “0” of send data at a time point in which the time52shorter than the time T53passes from the predetermined start point, by corresponding to a presence and absence of the superimposing pulse having a shorter width than the time T52. Accordingly, a synchronization signal, which is a line different from the data signal to send, is not required. Therefore, it is possible to configure the sending circuit parts2013and2013aand the receiving circuit part2014by only a simple circuit such as two sets of a delaying circuit and a simple logic circuit. In addition, the delaying circuit can be significantly a simple circuit applying a time constant of a CR, so that it is possible to save circuit space and to improve cost performance.

Moreover, in the second sending/receiving circuit, the delaying circuit used in the receiving circuit part can be partially shared with the sending circuit part, and the sending circuit part itself can be configured by a simple logic circuit. In addition, the second sending/receiving circuit superimposes the superimposing pulse over the serial data signal having no data input to the second sending/receiving circuit to generate the serial data signal to output to the transmission channel. Therefore, the clock generating circuit and a circuit for controlling a sending right are not required and it is possible for the second sending/receiving circuit to save circuit space more than the first sending/receiving circuit and improve the cost performance.

Furthermore, when there is no send data from the second sending/receiving circuit, the location of the start point is set every one period of the reference pulse signal. Therefore, it is possible to further simplify the circuit configuration of the sending circuit part.

In the power supplying system, the serial communication apparatus can be applied to the first communicating part and the second communicating part. In addition, the serial transmitting apparatus can be applied to the serial communication apparatus.

According to the present invention, the power supplying system for supplying a power from a plurality of power supplying devices to each of a plurality of loads, may include: a first power supplying device including a first power supplying part for supplying a power to at least one of the plurality of loads, a controlling part for conducting an operation control of the first power supplying part, and a first communicating part for sending and receiving a signal to and from the controlling part; and at least one second power supplying device including a second power supplying part for supplying a power to at least one of the plurality of loads, and a second communicating part for sending and receiving a signal to and from the second power supplying part, wherein the first communicating part and the second communicating part send and receive signals each other, and the controlling part conducts the operation control of the second power supplying part through the first communicating part and the second communicating part,

wherein a serial communication by a half-duplex communication is conducted between a first sending/receiving circuit in the first communicating part and a second sending/receiving circuit in the second communicating part in that at least one first sending/receiving circuit is connected to at least one second sending/receiving circuit through a transmission channel, wherein each of the first sending/receiving circuit and the second sending/receiving circuit includes: a sending circuit part for generating a serial data signal by superimposing a predetermined superimposing pulse over a send data signal having two values during a predetermined signal level and outputting the serial data signal; and a receiving circuit part for receiving the serial data signal sent from the sending circuit part, and extracting the send data signal by extracting the superimposing pulse from the serial data signal.

According to the present invention, the power supplying system for supplying a power from a plurality of power supplying devices to each of a plurality of loads may include: a first power supplying device including a first power supplying part for supplying a power to at least one of the plurality of loads, a controlling part for conducting an operation control of the first power supplying part, and a first communicating part for sending and receiving a signal to and from the controlling part; and at least one second power supplying device including a second power supplying part for supplying a power to at least one of the plurality of loads, and a second communicating part for sending and receiving a signal to and from the second power supplying part, wherein the first communicating part and the second communicating part send and receive signals each other, and the controlling part conducts the operation control of the second power supplying part through the first communicating part and the second communicating part,

wherein a serial communication by a half-duplex communication is conducted between a first sending/receiving circuit in the first communicating part and a second sending/receiving circuit in the second communicating part in that at least one first sending/receiving circuit is connected to at least one second sending/receiving circuit through a transmission channel, wherein each of the first sending/receiving circuit and the second sending/receiving circuit includes: a sending circuit part for generating a serial data signal by superimposing a predetermined superimposing pulse over a send data signal having two values during a predetermined signal level, and outputting the serial data signal; and a receiving circuit part for receiving the serial data signal sent from the sending circuit part, and extracting the send data signal by extracting the superimposing pulse from the serial data signal,

wherein, each of the first sending/receiving circuit and the first sending/receiving circuit includes, a sending part for converting each width of the plurality of digital input signals into a voltage in accordance with a predetermined weight, generating a send signal by adding voltages converted from the plurality of digital input signals, and outputting the send signal; and a receiving part for receiving the send signal from the sending part, comparing the send signal with a plurality of predetermined voltages, generating each of the digital input signals, and outputting the each of the digital input signals, so that a plurality of digital input signals are sent and received through a single signal line.

The present application is based on the Japanese Priority Patent Applications No. 2003-112930 filed on Apr. 17, 2003, No. 2003-112916 filed on Apr. 17, 2003, and No. 2003-112922 filed on Apr. 17, 2003 the entire contents of which are hereby incorporated by reference.