Semiconductor package

A semiconductor package includes a first substrate that includes a first trench on a recessed portion of a bottom surface of the first substrate and a first through hole extending through the first substrate to the first trench, a first semiconductor chip on the first substrate, a first capacitor chip in the first trench and on the first substrate, and a first molding layer on the first substrate and covering the first semiconductor chip. The first molding layer includes a first part that extends parallel to a top surface of the first substrate, a second part connected to the first part and extending vertically in the first through hole, and a third part connected to the second part and surrounding the first capacitor chip. A bottom surface of the third part is coplanar with the bottom surface of the first substrate.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2020-0107346, filed on Aug. 25, 2020 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Inventive concepts relate to a semiconductor package, and more particularly, to a semiconductor package including a capacitor chip.

A semiconductor package is provided to implement an integrated circuit chip to qualify for use in electronic products. Typically, a semiconductor package includes a semiconductor chip is mounted on a printed circuit board (PCB) and bonding wires or bumps are to electrically connect the semiconductor chip to the printed circuit board. With the development of electronic industry, various research has been conducted to improve reliability and durability of semiconductor packages.

SUMMARY

Some example embodiments of inventive concepts provide a semiconductor package with improved electrical characteristics and compact size.

Some example embodiments of inventive concepts provide a method of fabricating a semiconductor package in which method cuts down manufacturing cost.

Inventive concepts are not limited to the features mentioned above, and other features and effects, which have not been mentioned above, will be clearly understood to those skilled in the art from the following description.

According to some example embodiments of inventive concepts, a semiconductor package may include a first substrate including a first trench in a recessed portion of a bottom surface of the first substrate and a first through hole extending through the first substrate to the first trench; a first semiconductor chip on the first substrate; a first capacitor chip in the first trench and on the first substrate; and a first molding layer on the first substrate and covering the first semiconductor chip. The first molding layer may include a first part extending parallel to a top surface of the first substrate, a second part connected to the first part and extending vertically in the first through hole, and a third part connected to the second part and surrounding the first capacitor chip. A bottom surface of the third part may be coplanar with the bottom surface of the first substrate.

According to some example embodiments of inventive concepts, a semiconductor package may include a first substrate including a first trench in a recessed portion of a bottom surface of the first substrate and a first through hole extending through the first substrate to the first trench; a first semiconductor chip on the first substrate; a first capacitor chip in the first trench, the first capacitor chip having a first surface facing the first semiconductor chip and a second surface opposite to the first surface; and a first molding layer on the first substrate and covering the first semiconductor chip. The first molding layer may include a first part extending parallel to a top surface of the first substrate and covering the first semiconductor chip, a second part connected to the first part and extending vertically in the first through hole, and a third part connected to the second part and in the first trench. The third part of the first molding layer may cover the second surface of the first capacitor chip.

According to some example embodiments of inventive concepts, a semiconductor package may include a first substrate including a first trench in a recessed portion of a bottom surface of the first substrate and a first through hole extending through the first substrate to the first trench; a plurality of external coupling terminals on the bottom surface of the first substrate; a first semiconductor chip on the first substrate and including a plurality of first chip pads; a first capacitor chip in the first trench and on the first substrate; a first molding layer on the first substrate and covering the first semiconductor chip; a second substrate on a top surface of the first molding layer; a third substrate on the second substrate and including a plurality of conductive pads; a plurality of package connection terminals between the second substrate and the third substrate; a second semiconductor chip on the third substrate and including a plurality of second chip pads; and a plurality of bonding wires on the third substrate and connecting the plurality of conductive pads to the plurality of second chip pads. The first molding layer may include a first part extending parallel to a top surface of the first substrate; a second part connected to the first part and extending vertically in the first through hole; and a third part connected to the second part and surrounding the first capacitor chip. A bottom surface of the third part may be coplanar with the bottom surface of the first substrate.

DETAILED DESCRIPTION

In this description, like reference numerals may indicate like components. The following will now describe a semiconductor package and its fabrication method according to inventive concepts.

FIG.1illustrates a plan view showing a semiconductor package according to some example embodiments of inventive concepts.FIG.2illustrates a cross-sectional view taken along line I-I′ ofFIG.1.FIG.3illustrates an enlarged view of section A ofFIG.2.

Referring toFIGS.1to3, a semiconductor package10according to some example embodiments of inventive concepts may include a lower semiconductor package1and an upper semiconductor package2. The lower semiconductor package1may include a first substrate100, a first semiconductor chip200, a first capacitor chip150, and a first molding layer250, and the upper semiconductor package2may include a third substrate500, a second semiconductor chip600, bonding wires630, and a second molding layer650.

The first substrate100may be provided. The first substrate100may include a first lower passivation layer110, a first upper passivation layer120, a first core layer130, first lower conductive patterns131, first upper conductive patterns132, and interconnection patterns133. The first substrate100may be, for example, a printed circuit board (PCB) or a flexible substrate. However, this is merely an example without limiting inventive concepts, and the first substrate100may be one of a coreless printed circuit board, a coreless multi-layered printed circuit board, and a coreless flexible substrate, each of which does not include the first core layer130. The first substrate100may have a height of about 100 μm to about 200 μm in a third direction D3.

The first core layer130may include, for example, one or both of resin and glass fiber. The first lower passivation layer110and the first upper passivation layer120may be respectively provided on a bottom surface and a top surface of the first core layer130. The first lower passivation layer110may cover the bottom surface of the first core layer130, but may not cover bottom surfaces of the first lower conductive patterns131. For example, the first lower passivation layer110may include openings OP that expose the bottom surfaces of the first lower conductive patterns131. The first upper passivation layer120may cover the top surface of the first core layer130, but may not cover top surfaces of the first upper conductive patterns135. For example, the first upper passivation layer120may include openings that expose the top surfaces of the first upper conductive patterns135.

The first lower passivation layer110and the first upper passivation layer120may include a dielectric material. For example, the first lower passivation layer110and the first upper passivation layer120may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, a photo-curable resin, or a resin impregnated with one or more of glass fiber and inorganic fillers. The first lower passivation layer110may have a bottom surface that corresponds to a bottom surface100bof the first substrate100, and the first upper passivation layer120may have a top surface that corresponds to a top surface100aof the first substrate100.

The first lower conductive patterns131may be provided in the first core layer130. For example, the first lower conductive patterns131may be provided on a lower portion of the first core layer130. The first lower conductive patterns131may each have top and lateral surfaces covered with the first core layer130. The bottom surface of each of the first lower conductive patterns131may not be covered with the first core layer130. Therefore, the bottom surface of each of the first lower conductive patterns131may be exposed to the outside. The first lower conductive patterns131may define positions where external coupling terminals360are disposed. The first lower conductive patterns131may serve as pads for the external coupling terminals360. The first lower conductive patterns131may include a metallic material. For example, the first lower conductive patterns131may include one or more of copper, tungsten, and titanium. The first lower conductive patterns131may be disposed spaced apart from each other in a first direction D1.

In this description, the first direction D1may be parallel to the bottom surface100bof the first substrate100. A second direction D2may be parallel to the bottom surface100bof the first substrate100, while intersecting the first direction D1. The third direction D3may intersect both of the first and second directions D1and D2.

The interconnection patterns133may be provided in the first core layer130. The interconnection patterns133may be correspondingly provided on the first lower conductive patterns131. The interconnection patterns133may be in contact with and electrically connected to the first lower conductive patterns131. The interconnection patterns133may each include a line part and a via part provided on the line part. The via part may be connected to the line part, and may extend from the line part toward the top surface100aof the first substrate100. However, differently from that shown, the line part may be provided on the via part, and the configuration of the line and via parts may be variously changed without being limited thereto. The interconnection patterns133may include a metallic material, such as one or more of copper, tungsten, and titanium.

The first upper conductive patterns135may be provided in the first core layer130. The first upper conductive patterns135may be provided on an upper portion of the first core layer130. The first upper conductive patterns135may each have bottom and lateral surfaces covered with the first core layer130. The top surface of each of the first upper conductive patterns132may not be covered with the first core layer130. Therefore, the top surface of each of the first upper conductive patterns135may be exposed to the outside. The first upper conductive patterns135may define positions where conductive structures240are disposed. The first upper conductive patterns135may serve as pads for the conductive structures240. The first upper conductive patterns135may be in contact with and electrically connected to the interconnection patterns133. The first upper conductive patterns135may include a metallic material. For example, the first upper conductive patterns135may include one or more of copper, tungsten, and titanium. The first upper conductive patterns135may be disposed spaced apart from each other in the first direction D1.

The first lower conductive patterns131may be provided on their bottom surfaces with the external coupling terminals360coupled to the interconnection patterns133. The external coupling terminals360may fill the openings OP of the first lower passivation layer110. External electrical signals may be transferred through the external coupling terminals360to the interconnection patterns133. Solder balls may be used as the external coupling terminals360. The external coupling terminal360may include metal, such as a solder material.

The first substrate100may include a first trench TR on a recessed portion of the bottom surface100bthereof. The first trench TR may have a width W1of about 300 μm to about 400 μm in the first direction D1. The first trench TR may have a height H2of about 10 μm to about 100 μm in the third direction D3. A value of about 0.1 to about 0.5 may be given as a ratio of the height H2of the first trench TR to a height H1in the third direction D3of the first substrate100. The first substrate100may include a first through hole TH that penetrates therethrough. The first through hole TH may have a width W2of about 100 μm to about 300 μm in the first direction D1. When viewed in plan, at least a portion of the first trench TR may overlap the first semiconductor chip200. When viewed in plan, the first through hole TH may not overlap the first semiconductor chip200. For example, when viewed in plan, the first through hole TH may be disposed between the first semiconductor chip200and the conductive structures240. The first through hole TH may be spatially connected to the first trench TR. The first through hole TH may be provided on the first trench TR. The first through hole TH and the first trench TR1may vertically overlap each other. The first through hole TH may have an inner sidewall that is vertically aligned with that of the first trench TR. The first trench TR may expose bottom surfaces of some of the interconnection patterns133. The exposed bottom surfaces of the interconnection patterns133may define positions where capacitor connection terminals153are disposed.

The first semiconductor chip200may be mounted on the first substrate100. The first semiconductor chip200may be disposed on a central region of the first substrate100. When viewed in plan, the first semiconductor chip200may overlap at least a portion of the first trench TR. When viewed in plan, the first semiconductor chip200may not overlap the first through hole TH. The first semiconductor chip200may include first chip pads210. The first chip pads210may include a metallic material, such as copper, tungsten, titanium, or any alloy thereof. The first chip pads210may be exposed on a bottom surface of the first semiconductor chip200. The first chip pads210may connect the first semiconductor chip200to the first substrate100. The first semiconductor chip200may include integrated circuits therein. The integrated circuits may be disposed adjacent to the bottom surface of the first semiconductor chip200. The integrated circuits may include a memory circuit, a logic circuit, or a combination thereof. The first chip pads210may be electrically connected to the integrated circuits. Chip connection terminals230may be correspondingly interposed between the first chip pads210and the first upper conductive patterns135. The chip connection terminals230may include one or more of solders, pillars, and bumps. The chip connection terminals230may include a conductive material, such as a solder material. The solder material may include, for example, tin, bismuth, lead, silver, or any alloy thereof. The first semiconductor chip200may be electrically connected through the chip connection terminals230to the first substrate100. In this description, the language “connected” may include “physically connected”, “directly electrically connected”, or “indirectly electrically connected.”

The first capacitor chip150may be mounted on the first substrate100. The first capacitor chip150may have a first surface150adirected toward the first semiconductor chip200and a second surface150bopposite to the first surface150a. The first capacitor chip150may include capacitor chip pads151. The capacitor chip pads151may be exposed on the first surface150aof the first capacitor chip150. The capacitor chip pads151may include a metallic material, such as copper, tungsten, titanium, or any alloy thereof. According to some example embodiments, the capacitor connection terminals153may be correspondingly interposed between the capacitor chip pads151and the interconnection patterns133. The first capacitor chip150may be electrically connected to the first semiconductor chip200through the capacitor connection terminals153and the first substrate100. The first capacitor chip150will be further discussed below with reference toFIGS.3to5.

The first molding layer250may be provided on the first substrate100. The first molding layer250may include a dielectric material. For example, the first molding layer250may include an epoxy-based polymer. The first molding layer250may cover the top surface100aof the first substrate100and may surround the first semiconductor chip200. The first molding layer250may vertically extend to fill the first through hole TH and the first trench TR. The first molding layer250may include a first part251provided on the top surface100aof the first substrate100, a second part253provided in the first through hole TH, a third part255provided in the first trench TR. The first part251, the second part253, and the third part255may be connected to each other to constitute the first molding layer250. The second part253may be provided between the first part251and the third part255. The first molding layer250will be further discussed in detail below with reference toFIG.3.

The conductive structures240may be provided on the first substrate100. The conductive structures240may be correspondingly provided between the first upper conductive patterns135and second lower conductive patterns331which will be discussed below. When viewed in plan, the conductive structures240may be disposed on an edge region of the first substrate100. The conductive structures240may be disposed spaced apart in the first direction D1from the first semiconductor chip200. The conductive structures240may be disposed spaced apart from each other in the first direction D1or the second direction D2. The conductive structures240may penetrate the first molding layer250and may connect the first substrate100to a second substrate300which will be discussed below. The conductive structures240may include a metallic material, such as one or more of copper, tungsten, and titanium. The conductive structures240may include one or more of solders, pillars, and bumps. The conductive structures may include a conductive material, such as a solder material.

According to some example embodiments of inventive concepts, the semiconductor package10may further include a second substrate300provided on the first molding layer250. The second substrate300may include a second lower passivation layer310, a second upper passivation layer320, a second core layer330, second lower conductive patterns331, and second upper conductive patterns333.

The second substrate300may be, for example, a single-layered or multi-layered printed circuit board (PCB) or a single-layered or multi-layered flexible substrate. However, this is merely an example without limiting inventive concepts, and the second substrate300may be one of a coreless printed circuit board and a coreless flexible substrate, each of which does not include the second core layer330.

The second core layer330may include the same material as the first core layer130. The second lower passivation layer310and the second upper passivation layer320may be respectively provided on a bottom surface and a top surface of the second core layer330. The second lower passivation layer310and the second upper passivation layer320may include the same material as that of the first lower passivation layer110and the first upper passivation layer120. The second lower passivation layer310may include openings that expose bottom surfaces of the second lower conductive patterns331, and the second upper passivation layer320may include openings that expose top surfaces of the second upper conductive patterns333. The exposed bottom surfaces of the second lower conductive patterns331may define positions where the conductive structures240are disposed, and the exposed top surfaces of the second upper conductive patterns333may define positions where package connection terminals400are disposed.

The semiconductor package10according to some example embodiments of inventive concepts may include the upper semiconductor package2provided on the lower semiconductor package1. The upper semiconductor package2may include a third substrate500, a second semiconductor chip600, bonding wires630, and a second molding layer650.

The third substrate500may include one or more of a silicon substrate, a germanium substrate, a silicon-germanium substrate, and a single-layered or multi-layered printed circuit board, but inventive concepts are not limited thereto. The third substrate500may include a third core layer530, third lower conductive patterns510, and third upper conductive patterns520. The third core layer530may include the same material as that of the first and second core layers130and330. The third core layer530may cover top and lateral surfaces of the third lower conductive patterns510, but may not cover bottom surfaces of the third lower conductive patterns510. Therefore, the bottom surfaces of the third lower conductive patterns510may be exposed to the outside. The third lower conductive patterns510may serve as pads for the package connection terminals400. The third lower conductive patterns510may be referred to as conductive pads510. The third core layer530may cover bottom and lateral surfaces of the third upper conductive patterns520, but may not cover top surfaces of the third upper conductive patterns520. Therefore, the top surfaces of the third upper conductive patterns520may be exposed to the outside. The third upper and lower conductive patterns520and510may include a metallic material, such as one or more of copper, tungsten, and titanium. The third core layer530may be provided therein with interconnection lines (not shown) that connect the third upper conductive patterns520to the third lower conductive patterns510. The interconnection lines (not shown) may include a metallic material.

The package connection terminals400may be correspondingly interposed between the third lower conductive patterns510of the third substrate500and the second upper conductive patterns333of the second substrate300. Solder balls may be used as the package connection terminals400. The package connection terminals400may include metal, such as a solder material. The package connection terminals400may electrically connect the second substrate300to the third substrate500.

The second semiconductor chip600may be provided on the third substrate500. The second semiconductor chip600may include second chip pads610. The second chip pads610may include a metallic material, such as copper, tungsten, titanium, or any alloy thereof. The second chip pads610may be exposed on a top surface of the second semiconductor chip600. The second chip pads610may connect the second semiconductor chip600to the third substrate500. The second semiconductor chip600may include integrated circuits therein. The integrated circuits may be disposed adjacent to the top surface of the second semiconductor chip600. The integrated circuits may include a memory circuit, a logic circuit, or a combination thereof. The second chip pads610may be electrically connected to the integrated circuits.

The bonding wires630may be correspondingly provided between the second chip pads610and the third upper conductive patterns520. The bonding wires630may have a curved line shape. The bonding wires630may include a metallic material, such as gold, silver, platinum, lead, copper, tungsten, aluminum, titanium, or any alloy thereof. The bonding wires630may electrically connect the second semiconductor chip600to the third substrate500.

The second molding layer650may be provided on a top surface of the third substrate500. The second molding layer650may include a dielectric material. The second molding layer650may include, for example, an epoxy-based polymer. The second molding layer650may cover lateral and top surfaces of the second semiconductor chip600. The second molding layer650may encapsulate the bonding wires630. The second molding layer650and the third substrate500may have their lateral surfaces that are vertically aligned with each other.

FIG.3illustrates an enlarged view of section A ofFIG.2.FIG.4illustrates an enlarged view of section B ofFIG.3, showing a capacitor chip according to some example embodiments of inventive concepts.FIG.5illustrates a plan view taken along line II-IF ofFIG.4. The following description will refer toFIGS.3to5together withFIG.2.

ReferringFIGS.2and3, the first molding layer250may include the first part251, the second part253, and the third part255.

The first part251of the first molding layer250may be provided on the top surface100aof the first substrate100. The first part251may cover lateral and top surfaces of the first semiconductor chip200and may encapsulate the chip connection terminals230. Of the first molding layer250, the first part251may be a segment located at a higher level than that of the top surface100aof the first substrate100. The first part251may extend in a direction parallel to the top surface100a.

The second part253of the first molding layer250may penetrate an upper portion of the first substrate100. The second part253may be provided in the first through hole TH and may extend vertically. The second part253may fill the first through hole TH and may contact the inner sidewall of the first through hole TH. For example, the second part253may contact the first lower passivation layer110, the first upper passivation layer120, and the first core layer130exposed to the first through hole TH. The second part253may have one end connected to the first part251and other end connected to the third part255. Of the first molding layer250, the second part253may be a segment at a level between that of a top surface TRa of the first trench TR and that of the top surface100aof the first substrate100. The second part253may have a cylindrical shape, but no limitation is imposed on the shape of the second part253.

The third part255of the first molding layer250may be provided in the first trench TR. Of the first molding layer250, the third part255may be a segment at a level between that of the top surface TRa of the first trench TR and that of the bottom surface100bof the first substrate100. The third part255may contact the first lower passivation layer110and the first core layer130exposed to the first trench TR. The third part255may contact a first surface150a, lateral surfaces150c, and a second surface150bof the first capacitor chip150. The third part255may encapsulate the capacitor connection terminals153. The third part255may be connected to the second part253.

When viewed in plan, the second part253of the first molding layer250may be provided between the first semiconductor chip200and the conductive structures240. Therefore, the second part253may not vertically overlap the first semiconductor chip200. At least a portion of the third part255of the first molding layer250may overlap the first semiconductor chip200, when viewed in plan. The second part253may have one lateral surface253cvertically aligned with one lateral surface255cof the third part255. For example, the one lateral surface253cof the second part253may be coplanar with the one lateral surface255cof the third part255.

The third part255may have a bottom surface255bat the same level as that of the bottom surface100bof the first substrate100. For example, the bottom surface255bof the third part255may be coplanar with the bottom surface100bof the first substrate100. For another example, differently from that shown, the bottom surface255bof the third part255may be located at a level between that of the bottom surface100bof the first substrate100and that of the second surface150bof the first capacitor chip150.

Referring toFIG.4, according to some example embodiments of inventive concepts, the first capacitor chip150may include a capacitor substrate171, a common dielectric layer173, a first conductive layer175, a capacitor dielectric layer156, a capacitance structure169, contacts157and158, interconnection lines154, vias152, and capacitor chip pads151.

The capacitor substrate171may be provided. The capacitor substrate171may include, for example, a silicon substrate. The common dielectric layer173may be provided on a top surface of the capacitor substrate171. The common dielectric layer173may include a dielectric material, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride. The common dielectric layer173may include a single layer or a plurality of layers. The first conductive layer175may be provided on the common dielectric layer173. The first conductive layer175may include a metallic material, such as one or more of copper, tungsten, and titanium.

The first conductive layer175may be provided thereon with the capacitor dielectric layer156that has a plurality of through holes TRc on a lower portion of the capacitor dielectric layer156. The capacitor dielectric layer156may include a dielectric material, such as one or more of silicon oxide, silicon nitride, and silicon oxynitride.

The capacitance structure169may be provided in the capacitor dielectric layer156. The capacitance structure169may be provided on the first conductive layer175, and the capacitor dielectric layer156may surround the capacitance structure169. The capacitance structure169may include first, second, third, and fourth layers161,163,165, and167that fill the through holes TRc of the capacitor dielectric layer156. When viewed in plan, as shown inFIG.5, a spacing distance L1between the through holes TRc may range from about 100 nm to about 200 nm. The first, second, and third layers161,163, and165may be sequentially provided on inner sidewalls of the through holes TRc. The first, second, and third layers161,163, and165may conformally cover the inner sidewalls of the through holes TRc. The fourth layer167may be provided on the third layer165. The fourth layer167may fill remaining portions of the through holes TRc. Therefore, when viewed in plan as shown inFIG.5, the first, second, third, and fourth layers161,163,165, and167may each have a circular or annular shape. The fourth layer167may include via parts167V that extend into the through holes TRc and a horizontal part167P that is provided on the via parts167V. The via parts167V may be connected to the horizontal part167P. The first, second, third, and fourth layers161,163,165, and167may include, for example, one or both of titanium nitride and silicon-germanium. The capacitance structure169may be a segment in which charges are substantially accumulated in the first capacitor chip150.

First contacts158may be provided on the capacitance structure169, and second contacts157may be provided on the first conductive layer175. The vias152and the interconnection lines154may be provided on the first contacts158and the second contacts157. The vias152and the interconnection lines154may electrically connect the first and second contacts158and157to the capacitor chip pads151. The first contacts158, the second contacts157, the vias152, and the interconnection lines154may include a metallic material, such as one or more of copper, titanium, and tungsten.

FIG.6illustrates a plan view showing a semiconductor package according to some example embodiments of inventive concepts.

Referring toFIG.6, a semiconductor package20according to some example embodiments of inventive concepts may include a lower semiconductor package1and an upper semiconductor package2. The lower semiconductor package1may include a first substrate100, a first semiconductor chip200, a plurality of first capacitor chips150, and a first molding layer250. The first semiconductor chip200and the first capacitor chips150may be substantially the same as those discussed with reference toFIGS.1to5. The upper semiconductor package2may be substantially the same as that discussed with reference toFIGS.1and2. In that embodiment that follows, a repetitive description will be omitted, and a difference will be discussed in detail.

The first substrate100may include trenches TR on a recessed portion of the bottom surface100bthereof. The trenches TR may include first trenches TR1and second trenches TR2. When viewed in plan, the first trenches TR1and the second trenches TR2may overlap the first semiconductor chip200. The first substrate100may include through holes TH that penetrate therethrough. The through holes TH may include first through holes TH1that are spatially connected to the first trenches TR1, and may also include second through holes TH2that are spatially connected to the second trenches TR2. When viewed in plan, the first trenches TR1and the second trenches TR2may be disposed between the first semiconductor chip200and the conductive structures240. For example, the first through holes TH1and the first trenches TR1may be disposed adjacent to one lateral surface of the first semiconductor chip200, and the second through holes TH2and the second trenches TR2may be disposed adjacent to other lateral surface, opposite to the one lateral surface, of the first semiconductor chip200.

The first molding layer250may include a first part251provided on the top surface100aof the first substrate100, second parts253that fill the first and second through holes TH1and TH2, and third parts255that fill the first and second trenches TR1and TR2. Each of the second parts253may have one end connected to the first part251and other end connected to the third part255. For example, the second parts253may be disposed spaced apart from each other in the first direction D1or the second direction D2. The third parts255may surround the first capacitor chips150. The first capacitor chips150may be provided in the first trenches TR1and the second trenches TR2. At least a portion of the first capacitor chip150may vertically overlap the first semiconductor chip200.

FIGS.7to11illustrate diagrams showing a method of fabricating a semiconductor package according to some example embodiments of inventive concepts.

Referring toFIG.7, a first substrate100may be prepared. The first substrate100may be, for example, a printed circuit board (PCB). The first substrate100may include a first lower passivation layer110having openings OP that expose bottom surfaces131bof first lower conductive patterns131. The first substrate100may include a first upper passivation layer120having openings that expose top surfaces135aof first upper conductive patterns135. Conductive structures240may be formed on corresponding first upper conductive patterns135on an outer region of the first substrate100.

Referring toFIG.8, a first trench TR1may be formed in a recessed portion of a bottom surface100bof the first substrate100, and a first through hole TH may be formed which is spatially connected to the first trench TR. The formation of the first trench TR and the first through hole TH may include removing a lower portion of the first substrate100to thereby form the first trench TR1, and forming the first through hole TH on an outer region of the first trench TR1. The formation of the first trench TR and the first through hole TH may include, for example, irradiating a laser on the bottom surface100bof the first substrate100. Alternatively, the formation of the first trench TR and the first through hole TH may include allowing the first substrate100to undergo one or both of wet and dry etching processes. The formation of the first trench TR and the first through hole TH is not limited to that discussed above, and the first trench TR and the first through holes TH may be formed by partially removing the first substrate100or by various methods. The first trench TR may expose bottom surfaces of ones of interconnection patterns133. The exposed bottom surfaces of the interconnection patterns133may define a position on which a first capacitor chip (see150ofFIG.10) is subsequently mounted.

Referring toFIG.9, a first semiconductor chip200may be mounted on the first substrate100. When the first semiconductor chip200is mounted, first chip pads210may be aligned to face a top surface100aof the first substrate100. Chip connection terminals230may fix the first semiconductor chip200to the first substrate100.

A second substrate300may be prepared. The second substrate300may be, for example, a printed circuit board (PCB). The second substrate300may be provided on the conductive structures240. In this step, second lower conductive patterns331of the second substrate300may be vertically aligned with the conductive structures240. The first substrate100and the second substrate300may undergo a reflow process to allow the conductive structures240to fix the first substrate100and the second substrate300to each other.

Referring toFIGS.10and11, the first substrate100and the second substrate300may be provided therebetween with a first molding resin250pthat is introduced parallel to a first direction D1. The first molding resin250pmay include an epoxy-based polymer. The first molding resin250pmay have fluidity. Therefore, the first molding resin250pmay flow along the top surface100aof the first substrate100and into the first through hole TH. The first molding resin250pmay surround the first semiconductor chip200and the conductive structures240on the top surface100aof the first substrate100. The first molding resin250pmay flow along the first through hole TH and may enter the first trench TR. Thus, the first molding resin250pmay surround a first capacitor chip150provided in the first trench TR, and may fill the first through hole TH. Afterwards, the first molding resin250pmay be cured to form a first molding layer250.

Referring back toFIG.2, an upper semiconductor package2may be prepared. The preparation of the upper semiconductor package2may include preparing a third substrate500, providing a second semiconductor chip600on the third substrate500, allowing bonding wires630to connect second chip pads610of the second semiconductor chip600to third upper conductive patterns520of the third substrate500, forming a second molding layer650on a top surface of the third substrate500, and forming package connection terminals400on bottom surfaces of third lower conductive patterns510of the third substrate500. The upper semiconductor package2may be provided on a top surface of the second substrate300. In this step, the upper semiconductor package2may be disposed to vertically align the package connection terminals400with corresponding second upper conductive patterns333of the second substrate300. The package connection terminals400may undergo a reflow process to fix the lower and upper semiconductor packages1and2to each other. The processes mentioned above may fabricate semiconductor packages according to some example embodiments of inventive concepts.

When a power or input signal is applied through an external coupling terminal to a semiconductor chip mounted in a semiconductor package, the removal of signal noise may increase operating reliability of semiconductor packages. In the semiconductor package10according to some example embodiments of inventive concepts, the first trench TR may be formed in the first substrate100and the first capacitor chip150may be disposed in the first trench TR, with the result that a space may be effectively used. Accordingly, it may be possible to provide semiconductor packages with small thicknesses.

According to the method of fabricating the first molding layer250in accordance with some example embodiments of inventive concepts, the first molding resin250pmay be introduced through the first through hole TH into the first trench TR to thereby form the first molding layer250that protects both of the first semiconductor chip200and the first capacitor chip150. Accordingly, a separate under-fill process may not be required to insulate and protect the first capacitor chip150, which may result in a reduction in process step and a decrease in manufacturing cost.

According to inventive concepts, a first capacitor chip may be disposed in a first trench of a first substrate. It may thus be possible to effectively remove noise of power or input signals and to provide a compact-sized semiconductor package.

While some example embodiments of inventive concepts have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of inventive concepts in the attached claims.