SEMICONDUCTOR DEVICE INCLUDING DIELECTRICS MADE OF POROUS ORGANIC FRAMEWORKS, AND METHOD OF FABRICATING THE SAME

A semiconductor device includes a substrate and an interconnection layer disposed on the substrate. The interconnection layer includes a plurality of etch-stop layers, a plurality of first dielectric layers, and a plurality of conductive layers. The first dielectric layers are disposed on the plurality of etch-stop layers, wherein the plurality of first dielectric layers comprises porous organic framework (POF) dielectrics having a dielectric constant of 2 or less, and a thermal conductivity of 1 W/(m·K) or more. The conductive layers are embedded in the first dielectric layers.

BACKGROUND

DETAILED DESCRIPTION

FIG.1is a schematic cross-sectional view of a semiconductor device in accordance with some embodiments of the disclosure. In some embodiments, the semiconductor device100includes a substrate102, a bottom dielectric layer104A, a bottom conductive layer104B, an interconnection layer106, a passivation layer108, a post-passivation layer112, a plurality of conductive pads110, and a plurality of conductive terminals114. In some embodiments, the substrate102is made of elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide; or alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. The substrate102may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate.

In some embodiments, the substrate102includes various doped regions depending on circuit requirements (e.g., p-type semiconductor substrate or n-type semiconductor substrate). In some embodiments, the doped regions are doped with p-type dopants or n-type dopants. For example, the doped regions may be doped with p-type dopants, such as boron or BF2; n-type dopants, such as phosphorus or arsenic; and/or combinations thereof. In some embodiments, these doped regions serve as source/drain regions of a transistor TX1, which is formed over the substrate102. Depending on the types of the dopants in the doped regions, the transistor TX1may be referred to as n-type transistor or p-type transistor. In some embodiments, the transistor TX1further includes a metal gate and a channel under the metal gate. The channel is located between the source region and the drain region to serve as a path for electron to travel when the transistor TX1is turned on. On the other hand, the metal gate is located above the substrate102and is embedded in the bottom dielectric layer104A.

In some embodiments, the bottom conductive layer104B is electrically connected to the transistor TX1. For example, the bottom conductive layer104B includes a conductive via104B1and a conductive pattern104B2embedded in the bottom dielectric layer104A, whereby the conductive via104B1is connected to the transistor TX1, and the conductive pattern104B2is disposed on the conductive via104B1. In certain embodiments, the conductive via104B1is connected to the metal gate of the transistor TX1. It should be noted that in some alternative cross-sectional views, other conductive vias104B1are also connected to source/drain regions of the transistor TX1. That is, in some embodiments, the conductive vias104B1may be referred to as “contact structures” of the transistor TX1.

In some embodiments, the transistor TX1is formed using suitable Front-end-of-line (FEOL) process. For simplicity, one transistor TX1is shown inFIG.1. However, it should be understood that more than one transistor TX1may be presented depending on the application of the semiconductor device100. When multiple transistors TX1are presented, these transistors TX1may be separated by shallow trench isolation (STI; not shown) located between two adjacent transistors TX1.

As illustrated inFIG.1, the interconnection layer106is formed over the substrate102, and on the bottom dielectric layer104A. In some embodiments, the interconnection layer106includes a plurality of dielectric layers106A and a plurality of conductive layers106B alternately stacked up along a build-up direction. In some embodiments, the conductive layers106B include conductive vias106B1and conductive patterns106B2embedded in the dielectric layers104A. In some embodiments, the conductive patterns106B2located at different level heights are connected to one another through the conductive vias106B1. In other words, the conductive patterns106B2are electrically connected to one another through the conductive vias106B1. In some embodiments, the bottommost conductive vias106B1are connected to the transistor TX1through the conductive via104B1and the conductive pattern104B2.

In some embodiments, the interconnection layer106further includes a plurality of transistors TX2located in between the plurality of dielectric layers106A. The transistors TX2may be similar to the transistor TX1described above, thus its details will not be repeated herein. The transistors TX2may be embedded in the interconnection layer106. For example, each transistor TX2may be embedded in one of the dielectric layers106A. In some embodiments, the transistors TX2are electrically connected to the conductive layers106B. In certain embodiments, the transistors TX2may be arranged in an array (e.g. array of transistors/array of memory cells) in each of the dielectric layers106A.

In some embodiments, the bottom dielectric layer104A and the dielectric layers106A are porous organic framework (POF) dielectrics having a dielectric constant (k value) of 2 or less, and a thermal conductivity of 1 W/(m·K) or more. Furthermore, the dielectric layers106A have a Young's modulus of 55 GPa or more. In certain embodiments, the porous organic framework (POF) dielectrics include covalent organic framework (COF) dielectrics. In some embodiments, the dielectric layers106A in the interconnection layer106are silicon-free. The details of the porous organic framework (POF) dielectrics will be explained in more detail in the later embodiments. The dielectric layers106A may be formed by suitable fabrication techniques such as spin-on coating, chemical vapor deposition (CVD), or the like.

In some embodiments, the bottom conductive layer104B and the conductive layers106B include materials such as aluminum, titanium, copper, nickel, tungsten, or alloys thereof. The conductive layers106B (including conductive patterns106B2and the conductive vias106B1) may be formed by electroplating, deposition, and/or photolithography and etching. In some embodiments, the conductive patterns106B2and the underlying conductive vias106B1are formed simultaneously. It should be noted that the number of the dielectric layers106A, the number of the conductive layers106B illustrated inFIG.1are merely for illustrative purposes, and the disclosure is not limited thereto. In some alternative embodiments, fewer or more layers of the dielectric layers106A and the conductive layers106B may be formed depending on the circuit design.

As illustrated inFIG.1, the passivation layer108, the conductive pads110, the post-passivation layer112, and the conductive terminals114are sequentially formed on the interconnection layer106. In some embodiments, the passivation layer108is disposed on the topmost dielectric layer106A and the topmost conductive layer106B (conductive pattern106B2). In some embodiments, the passivation layer108has a plurality of openings partially exposing the topmost conductive patterns106B2. In some embodiments, the passivation layer108is a silicon oxide layer, a silicon nitride layer, a silicon oxy-nitride layer, or a dielectric layer formed by other suitable dielectric materials. The passivation layer108may be formed by suitable fabrication techniques such as (high-density plasma chemical vapor deposition) HDP-CVD, (plasma-enhanced chemical vapor deposition) PECVD, or the like.

In some embodiments, the conductive pads110are formed over the passivation layer108. In some embodiments, the conductive pads110extend into the openings of the passivation layer108to be in direct contact with the topmost conductive patterns106B2. That is, the conductive pads110are physically and electrically connected to the interconnection layer106. In some embodiments, the conductive pads110include aluminum pads, titanium pads, copper pads, nickel pads, tungsten pads, or other suitable metal pads. The conductive pads110may be formed by, for example, electroplating, deposition, and/or photolithography and etching. It should be noted that the number and the shape of the conductive pads110illustrated inFIG.1are merely for illustrative purposes, and the disclosure is not limited thereto. In some alternative embodiments, the number and the shape of the conductive pads110may be adjusted based on demand.

In some embodiments, the post-passivation layer112is formed over the passivation layer108and the conductive pads110. In some embodiments, the post-passivation layer112is formed on the conductive pads110to protect the conductive pads110. In some embodiments, the post-passivation layer112has a plurality of contact openings partially exposing each of the conductive pads110. The post-passivation layer112may be a polyimide layer, a PBO layer, or a dielectric layer formed by other suitable polymers. In some embodiments, the post-passivation layer112is formed by suitable fabrication techniques such as HDP-CVD, PECVD, or the like.

As further illustrated inFIG.1, the conductive terminals114are formed over the post-passivation layer112and the conductive pads110. In some embodiments, the conductive terminals114extend into the contact openings of the post-passivation layer112to be in direct contact with the corresponding conductive pad110. That is, the conductive terminals114are electrically connected to the interconnection layer106through the conductive pads110. In some embodiments, the conductive terminals114are conductive pillars, conductive posts, conductive balls, conductive bumps, or the like. In some embodiments, a material of the conductive terminals114includes a variety of metals, metal alloys, or metals and mixture of other materials. For example, the conductive terminals114may be made of aluminum, titanium, copper, nickel, tungsten, tin, and/or alloys thereof. The conductive terminals114are formed by, for example, deposition, electroplating, screen printing, or other suitable methods. In some embodiments, the conductive terminals114are used to establish electrical connection with other components (not shown) subsequently formed or provided. Up to here, a semiconductor device100in accordance with some embodiments of the present disclosure is accomplished.

As illustrated inFIG.1, the interconnection layer106is formed with dielectric layers106A that are porous organic framework (POF) dielectrics having a dielectric constant (k value) of 2 or less, and a thermal conductivity of 1 W/(m·K) or more. The formation method and the arrangement of the dielectric layers106A will be described in more detail by referring toFIG.2AtoFIG.2Kshown below.

FIG.2AtoFIG.2Kare schematic cross-sectional views illustrating various stages in a method of fabricating a semiconductor device in accordance with some embodiments of the disclosure.FIG.2AtoFIG.2Jillustrate a portion of the interconnection layer106in a semiconductor device. Referring toFIG.2A, an etch-stop layer105is formed over an underlying dielectric layer202A and over an underlying conductive layer202B. For example, the underlying dielectric layer202A and the underlying conductive layer202B may correspond to the bottom dielectric layer104A and the bottom conductive layer104B of the semiconductor device. Alternatively, the underlying dielectric layer202A and the underlying conductive layer202B may correspond to the dielectric layers106A and the conductive layers106B located at any level of the interconnection layer.

In the exemplary embodiment, the etch-stop layer105includes a first layer105A, a second layer105B disposed on the first layer105A, a third layer105C disposed on the second layer105B, and a fourth layer105D disposed on the third layer105C. For example, in one embodiment, the first layer105A is an aluminum nitride (AlN) layer, the second layer105B is a silicon oxycarbide (SiOC) layer, the third layer105C is an aluminum oxide (AlOx) layer, and the fourth layer105D is a silicon oxycarbide (SiOC) layer. However, the disclosure is not limited thereto. In some other embodiments, the etch-stop layer105may also include one layer, or more than one layer, which may be adjusted based on design requirements. Furthermore, when one or more layers are contained in the etch-stop layer105, these layers may independently include AlN, AlOx, silicon nitride (SiN), silicon carbide (SiC), SiOC, silicon oxynitride (SiON), silicon methylidyne (SiCH), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), or the like, or combinations thereof.

As further illustrated inFIG.2A, a dielectric layer106A is formed over the etch-stop layer105. In some embodiments, the dielectric layer106A is a POF dielectric, whereby the POF dielectric is a first covalent organic framework (COF) material CFL1(or first COF layer CFL1). For example, the first COF material CFL1is a two-dimensional COF layer. In the exemplary embodiment, the two-dimensional COF is formed by a reaction between a first compound having a partial structure represented by formula IA and a second compound having a partial structure represented by formula IB to form a boronic ester shown in formula IC.

For example, referring toFIG.2B, in some embodiments, the first compound is a compound having a structure represented by formula IA-X:

wherein in formula IA-X, Lxis a linker selected from the group consisting of L1 to L5:

Furthermore, the second compound is for example, hexahydroxytriphenylene (HHTP).

In some embodiments, the first compound and the second compound react to form a two-dimensional building block that constitute the first covalent organic framework (COF) material CFL1of the dielectric layer106A. For example, in one embodiment, when the linker Lx in the first compound is L1, then a two-dimensional building block of the first covalent organic framework (COF) material CFL1may be COF-5 having the chemical structure as shown below.

In another embodiment, when the linker Lx in the first compound is L2, then a two-dimensional building block of the first covalent organic framework (COF) material CFL1may be TP-COF having the chemical structure as shown below.

In another embodiment, when the linker Lx in the first compound is L3, then a two-dimensional building block of the first covalent organic framework (COF) material CFL1may be COF-10 having the chemical structure as shown below.

In another embodiment, when the linker Lx in the first compound is L4, then a two-dimensional building block of the first covalent organic framework (COF) material CFL1may be COF-117 having the chemical structure as shown below (not shown inFIG.2B).

In another embodiment, when the linker Lx in the first compound is L5, then a two-dimensional building block of the first covalent organic framework (COF) material CFL1may be DPB-COF having the chemical structure as shown below (not shown inFIG.2B).

In the above embodiments, although certain linkers Lx are used in the first compound to react with the second compound to form a two-dimensional building block of the first covalent organic framework (COF) material CFL1, it is noted that other linkers may also be used. For example, other linkers selected from the group consisting of L6 to L18 may be exemplified.

In the exemplary embodiment, the dielectric layer106A or the first COF material CFL1is formed on the etch-stop layer105by spin-on coating or chemical vapor deposition (CVD). For example, in one embodiment, the precursors (the first compound and the second compound) are mixed and dissolved into an organic solvent (e.g. by dichloromethane, or other suitable solvents) for reaction at room temperature, and then the solution is coated onto the etch-stop layer105by spin-on coating. In another embodiment, the precursors (the first compound and the second compound) are heated, and the vapor of the precursors are reacted on the surface of the etch-stop layer105by CVD at temperatures of 300° C. or less to form the dielectric layer106A (or first COF material CFL1).

By using a two-dimensional building block to form the dielectric layer106A having covalent organic frameworks, the formed dielectric layer106A will have a dielectric constant of 2 or less, and a thermal conductivity in a range of 1 W/(m·K) to 4 W/(m·K). Furthermore, the Young's modulus of the dielectric layer106A (or first COF material CFL1) is in a range of 55 GPa to 220 GPa. As such, when the first COF material CFL1is used in replacement of the conventional low k dielectric materials (typically with dielectric constant of ˜3 and thermal conductivity of <1 W/(m·K)) in forming the interconnection layer106in the back-end-of-line (BEOL) process, the covalent bonds and highly ordered ring structure in the COF layer enables high thermal conductivities and high mechanical strengths. Overall, the heat dissipation efficiency and the parasitic capacitance of the semiconductor device can be improved to fulfill the needs of BEOL performance and reliability requirement in the advanced node.

Referring toFIG.2C, after forming the dielectric layer106A (or first COF material CFL1), a patterning mask layer204is formed over the dielectric layer106A, and a photoresist206is provided on the patterning mask layer204. In some embodiments, the patterning mask layer204includes a first pattern mask204A disposed on the dielectric layer106A, and a second pattern mask204B disposed on the first pattern mask204A. For example, in one embodiment, the first pattern mask204A is a nitrogen free anti-reflection layer made of oxides, while the second pattern mask204B is a titanium nitride (TiN) layer. However, the disclosure is not limited thereto, and the materials of the first pattern mask204A and the second pattern mask204B may be suitably adjusted based on design requirements.

Furthermore, the photoresist206has a tri-layer structure including a bottom layer206A, a middle layer206B and an upper layer206C. The bottom layer206A may include a carbon-rich layer or a carbon-containing polymeric material such as novolac resin, or the like. In some alternative embodiments, the bottom layer206A include other material(s), such as silicon nitride (SiN), silicon oxynitride, other suitable material, or a composition thereof. The middle layer206B is formed on the bottom layer206A and may include an oxide layer such as silicon oxide (SiOx). The middle layer206B is designed to have a composition different from the bottom layer206A in order to have enough etch selectivity between those two layers. The upper layer206C is formed on the middle layer206B and may include a photoresist material.

In some embodiments, the upper layer206C (e.g. photoresist) is patterned by a photolithography process using a photomask to form opening patterns (only one is shown), whereby the opening patterns are transferred to the underlying layers through subsequent etching steps. For example, the middle layer206B is patterned by using the patterned upper layer206C as a pattern mask, such that the opening patterns are transferred into the middle layer206B; and the bottom layer206A is then patterned by using the patterned upper layer206C and/or the patterned middle layer206B as a pattern mask, such that the opening patterns are transferred into the bottom layer206A. Thereafter, by using the photoresist206as a pattern mask, the opening patterns of the photoresist206are transferred into the second pattern mask204B of the patterning mask layer204. In other words, the second pattern mask204B of the patterning mask layer204may be etched to form an opening OP1as shown inFIG.2Dusing the photoresist206. Subsequently, the photoresist206may be removed, whereby the opening OP1reveals the underlying first pattern mask204A.

Referring toFIG.2E, in some embodiments, a second photoresist208is provided over the patterning mask layer204. For example, the second photoresist208has a tri-layer structure including a bottom layer208A, a middle layer208B and an upper layer208C similar in material to the bottom layer206A, the middle layer206B and the upper layer206C of the photoresist206. In some embodiments, the upper layer208C (e.g. photoresist) is patterned by a photolithography process using a photomask to form opening patterns (only one is shown), whereby the opening patterns are transferred to the underlying layers through subsequent etching steps. For example, the middle layer208B is patterned by using the patterned upper layer208C as a pattern mask, such that the opening patterns are transferred into the middle layer208B; and the bottom layer208A is then patterned by using the patterned upper layer208C and/or the patterned middle layer208B as a pattern mask, such that the opening patterns are transferred into the bottom layer208A. Thereafter, by using the second photoresist208as a pattern mask, the opening patterns of the second photoresist208are transferred into the first pattern mask204A of the patterning mask layer204. In other words, the first pattern mask204A of the patterning mask layer204may be etched to form a second opening OP2as shown inFIG.2Fusing the second photoresist208. By using the first pattern mask204A as a masking layer, the dielectric layer106A (or first COF material CFL1) may be patterned (or removed) by an ashing process using N2/H2plasma at a temperature range from 150° C. to 250° C. After the ashing process, the second opening OP2reveals an upper surface of the etch-stop layer105.

Referring toFIG.2G, in a next step, the etch-stop layer105is further removed. For example, the etch-stop layer105is removed so that the second opening OP2reveals an upper surface of the underlying conductive layer202B. As illustrated inFIG.2H, the first pattern mask204A of the patterning mask layer204may be further etched so that the first opening OP1reveals a top surface of the dielectric layer106A (or first COF material CFL1). For example, the first pattern mask204A is etched so that sidewalls of the first pattern mask204A are aligned with sidewalls of the second pattern mask204B.

Referring toFIG.2I, in a subsequent step, the dielectric layer106A (or first COF material CFL1) may be patterned (or removed) by an ashing process using N2/H2plasma at a temperature range from 150° C. to 250° C. After the ashing process, the first opening OP1extends into the dielectric layer106A (or first COF material CFL1), whereby the second opening OP2overlaps with the first opening OP1in the dielectric layer106A (or first COF material CFL1).

Referring toFIG.2J, a conductive layer106B is filled into the first opening OP1and the second opening OP2. For example, forming the conductive layer106B includes conformally forming a barrier layer106B3in the first opening OP1and the second opening OP2, and forming a conductive material including conductive vias106B1and conductive patterns106B2on the barrier layer106B3. In some embodiments, the barrier layer106B3includes tantalum (Ta), tantalum nitride (TaN), a combination thereof, or the like. In certain embodiments, the conductive vias106B1and the conductive patterns106B2include materials such as aluminum, titanium, copper, nickel, tungsten, or alloys thereof. After forming the conductive layer106B, the patterning mask layer204is removed, and a planarization process (e.g., a chemical-mechanical planarization (CMP) process) is performed to remove excessive conductive material of the conductive layer106B. As such, a top surface of the conductive layer106B may be aligned with a top surface of the dielectric layer106A (or first COF material CFL1).

Referring toFIG.2K, the formation of the interconnection layer106may be completed by repeating the steps illustrated inFIG.2AtoFIG.2J. InFIG.2K, the etch-stop layer105is omitted for ease of illustration, and it should be noted that the etch-stop layers105are located below each of the dielectric layers106A in the manner shown inFIG.2J. After forming the interconnection layer106, the passivation layer108, the post-passivation layer112, the conductive pads110, and the conductive terminals114are formed over the interconnection layer106in a similar manner as described inFIG.1. Up to here, a semiconductor device100A in accordance with some embodiments of the present disclosure is accomplished. In the semiconductor device100A, since the first COF material CFL1is used in replacement of the conventional low-k dielectric materials (typically with dielectric constant of ˜3 and thermal conductivity of <1 W/(m·K)) in the interconnection layer106, the covalent bonds and highly ordered ring structure in the COF layer enables high thermal conductivities and high mechanical strengths. Overall, the heat dissipation efficiency and the parasitic capacitance of the semiconductor device100A can be improved to fulfill the needs of BEOL performance and reliability requirement in the advanced node.

FIG.3AtoFIG.3Care schematic cross-sectional views illustrating various stages in a method of fabricating a semiconductor device in accordance with some other embodiments of the disclosure. The method illustrated inFIG.3AtoFIG.3Cis similar to the method illustrated inFIG.2AtoFIG.2K. Therefore, the same reference numerals are used to refer to the same or liked parts, and its detailed description will be omitted herein. As illustrated inFIG.3A, after forming an etch-stop layer105over the underlying dielectric layer202A, a two-dimensional material layer103is formed over the etch-stop layer105. For example, the two-dimensional material layer103is made of two-dimensional materials such as graphene, transition-metal dichalcogenides, or the like. In some embodiments, the two-dimensional material layer103may be two-dimensional materials containing carbon, tungsten, sulfur, oxygen, selenium (Se), tellurium (Te), molybdenum (Mo), nitrogen, tantalum (Ta), titanium, or may include other metals. In certain embodiments, the two-dimensional material layer103is a monolayer that has a thickness in a range of 0.3 nm to 0.5 nm. After forming the two-dimensional material layer103, the dielectric layer106A (or first COF material CFL1) may be formed on the two-dimensional material layer103by a similar method described inFIG.2A. For example, the thickness of the two-dimensional material layer103is smaller than a thickness of the dielectric layer106A (or first COF material CFL1).

Referring toFIG.3B, the method described inFIG.2BtoFIG.2Jmay be performed to pattern the dielectric layer106A (or first COF material CFL1), and to form the conductive layer106B in the dielectric layer106A. For example, after forming the conductive layer106B in the first opening OP1and the second opening OP2(shown inFIG.2I), the conductive layer106B is surrounded by the etch-stop layer105, the two-dimensional material layer103, and further surrounded by the dielectric layer106A (or first COF material CFL1).

Referring toFIG.3C, the formation of the interconnection layer106may be completed by repeating the steps illustrated inFIG.3AtoFIG.3B. Thereafter, the passivation layer108, the post-passivation layer112, the conductive pads110, and the conductive terminals114are formed over the interconnection layer106in a similar manner as described inFIG.1. Up to here, a semiconductor device100B in accordance with some embodiments of the present disclosure is accomplished. Similar to the above embodiments, in the semiconductor device100B, since the first COF material CFL1is used in replacement of the conventional low-k dielectric materials (typically with dielectric constant of ˜3 and thermal conductivity of <1 W/(m·K)) in the interconnection layer106, the covalent bonds and highly ordered ring structure in the COF layer enables high thermal conductivities and high mechanical strengths. In addition, the presence of the two-dimensional material layer103further improves the mechanical strengths and enables high thermal conductivities. Overall, the heat dissipation efficiency and the parasitic capacitance of the semiconductor device100B can be improved to fulfill the needs of BEOL performance and reliability requirement in the advanced node.

FIG.4AtoFIG.4Eare schematic cross-sectional views illustrating various stages in a method of fabricating a semiconductor device in accordance with some other embodiments of the disclosure. The method illustrated inFIG.4AtoFIG.4Eis similar to the method illustrated inFIG.2AtoFIG.2K. Therefore, the same reference numerals are used to refer to the same or liked parts, and its detailed description will be omitted herein. The difference between the embodiments is that a second covalent organic framework (COF) material CFL2(or second COF layer CFL2) is used in replacement of the first COF material CFL1as the dielectric layer106A.

Referring toFIG.4A, an etch-stop layer105is formed over an underlying dielectric layer202A and over an underlying conductive layer202B. Thereafter, a dielectric layer106A is formed over the etch-stop layer105. In the exemplary embodiment, the dielectric layer106A is a second COF material CFL2. For example, the second COF material CFL2is a three-dimensional COF layer. In the exemplary embodiment, the three-dimensional COF is formed by a reaction between a third compound having a partial structure represented by formula IIA and a fourth compound having a partial structure represented by formula IIB to form an imine (>C═N—).

For example, referring toFIG.4B, the third compound is tetrakis(4-aminophenyl)methane (TAM), and the fourth compound is benzene-1,4-dicarbaldehyde (BDA), whereby TAM and BDA may react to form a three-dimensional building block COF-300.

In the above embodiments, although the third compound and the fourth compound have a certain structure as designated above, it is noted that the disclosure is not limited thereto. For example, the partial structure represented by formula IIA and the partial structure represented by formula IIB may be further linked to the linkers Lx (including L1-L18) exemplified above to form third and fourth compounds having different structures. In addition, although the two-dimensional building blocks or the three-dimensional building blocks mentioned above are constructed through boronic ester connections or imine connections, it is noted that other types of connections may be used to form the two-dimensional building blocks or three-dimensional building blocks. For example, one or two types of precursor compounds may be reacted to form covalent organic frameworks that are constructed by boroxine, hydrazone, azine, P-ketoenamine, imide connections, or the like.

In the exemplary embodiment, the dielectric layer106A or the second COF material CFL2is formed on the etch-stop layer105by spin-on coating or chemical vapor deposition (CVD). For example, in one embodiment, the precursors (the third compound and the fourth compound) are mixed and dissolved into an organic solvent (e.g. by dichloromethane, or other suitable solvents) for reaction at room temperature, and then the solution is coated onto the etch-stop layer105by spin-on coating. In another embodiment, the precursors (the third compound and the fourth compound) are heated, and the vapor of the precursors are reacted on the surface of the etch-stop layer105by CVD at temperatures of 300° C. or less to form the dielectric layer106A (or second COF material CFL2).

By using a three-dimensional building block to form the dielectric layer106A having covalent organic frameworks, the formed dielectric layer106A will have a dielectric constant of 2 or less, and a thermal conductivity will be greater than 4 W/(m·K). Furthermore, the Young's modulus of the dielectric layer106A (or second COF material CFL2) is in a range of 220 GPa to 350 GPa. In other words, the second COF material CFL2will have a higher thermal conductivity and higher Young's modulus than the first COF material CFL1. As such, higher thermal conductivities and higher mechanical strengths can be obtained.

Referring toFIG.4C, after forming the dielectric layer106A (or second COF material CFL2), a patterning mask layer204is formed over the dielectric layer106A, and a photoresist206is provided on the patterning mask layer204. The patterning mask layer204and the photoresist206are the same as described inFIG.2C, thus its details will not be repeated herein. Thereafter, referring toFIG.4D, the method described inFIG.2DtoFIG.2Jmay be performed to pattern the dielectric layer106A (or first second material CFL2), and to form the conductive layer106B in the dielectric layer106A. For example, after forming the conductive layer106B in the first opening OP1and the second opening OP2(shown inFIG.2I), the conductive layer106B is surrounded by the etch-stop layer105and the dielectric layer106A (or second COF material CFL2).

Referring toFIG.4E, the formation of the interconnection layer106may be completed by repeating the steps illustrated inFIG.4AtoFIG.4D. Thereafter, the passivation layer108, the post-passivation layer112, the conductive pads110, and the conductive terminals114are formed over the interconnection layer106in a similar manner as described inFIG.1. Up to here, a semiconductor device100C in accordance with some embodiments of the present disclosure is accomplished. Similar to the above embodiments, in the semiconductor device100C, since the second COF material CFL2(with three-dimensional building block) is used in replacement of the conventional low-k dielectric materials (typically with dielectric constant of ˜3 and thermal conductivity of <1 W/(m·K)) in the interconnection layer106, the covalent bonds and highly ordered ring structure in the COF layer enables high thermal conductivities and high mechanical strengths. Furthermore, due to the formation of three-dimensional building blocks in the second COF material CFL2, the thermal conductivities and mechanical strengths can be further improved as compared with the first COF material CFL1with two-dimensional building blocks. Overall, the heat dissipation efficiency and the parasitic capacitance of the semiconductor device100C can be further improved to fulfill the needs of BEOL performance and reliability requirement in the advanced node.

FIG.5AtoFIG.5Bare schematic cross-sectional views illustrating various stages in a method of fabricating a semiconductor device in accordance with some other embodiments of the disclosure. The method illustrated inFIG.5AtoFIG.5Bis similar to the method illustrated inFIG.4AtoFIG.4E. Therefore, the same reference numerals are used to refer to the same or liked parts, and its detailed description will be omitted herein. As illustrated inFIG.5A, after forming an etch-stop layer105over the underlying dielectric layer202A, a two-dimensional material layer103is formed over the etch-stop layer105. For example, the two-dimensional material layer103is made of two-dimensional materials such as graphene, transition-metal dichalcogenides, or the like. In some embodiments, the two-dimensional material layer103may be two-dimensional materials containing carbon, tungsten, sulfur, oxygen, selenium (Se), tellurium (Te), molybdenum (Mo), nitrogen, tantalum (Ta), titanium, or may include other metals. In certain embodiments, the two-dimensional material layer103has a thickness in a range of 0.3 nm to 0.5 nm. After forming the two-dimensional material layer103, the dielectric layer106A (or second COF material CFL2) may be formed on the two-dimensional material layer103by a similar method described inFIG.4A.

As illustrated inFIG.5A, after forming the dielectric layer106A (or second COF material CFL2), the method described inFIG.2BtoFIG.2Jmay be performed to pattern the dielectric layer106A (or first COF material CFL1), and to form the conductive layer106B in the dielectric layer106A. For example, after forming the conductive layer106B in the first opening OP1and the second opening OP2(shown inFIG.2I), the conductive layer106B is surrounded by the etch-stop layer105, the two-dimensional material layer103, and further surrounded by the dielectric layer106A (or second COF material CFL2).

Referring toFIG.5B, the formation of the interconnection layer106may be completed by repeating the formation of the structure illustrated inFIG.5A. Thereafter, the passivation layer108, the post-passivation layer112, the conductive pads110, and the conductive terminals114are formed over the interconnection layer106in a similar manner as described inFIG.1. Up to here, a semiconductor device100D in accordance with some embodiments of the present disclosure is accomplished. Similar to the above embodiments, in the semiconductor device100D, since the second COF material CFL2(with three-dimensional building block) is used in replacement of the conventional low-k dielectric materials (typically with dielectric constant of ˜3 and thermal conductivity of <1 W/(m·K)) in the interconnection layer106, the covalent bonds and highly ordered ring structure in the COF layer enables high thermal conductivities and high mechanical strengths. Furthermore, due to the formation of three-dimensional building blocks in the second COF material CFL2, the thermal conductivities and mechanical strengths can be further improved as compared with the first COF material CFL1with two-dimensional building blocks. In addition, the presence of the two-dimensional material layer103further improves the mechanical strengths and enables high thermal conductivities. Overall, the heat dissipation efficiency and the parasitic capacitance of the semiconductor device100D can be further improved to fulfill the needs of BEOL performance and reliability requirement in the advanced node.

FIG.6is a schematic cross-sectional view of a semiconductor device in accordance with some other embodiments of the disclosure. The semiconductor device100E shown inFIG.6is similar to the semiconductor device100B shown inFIG.3C. Therefore, the same reference numerals are used to refer to the same or liked parts, and its detailed description will be omitted herein. The difference between the embodiments is that both the first COF material CFL1and the second COF material CFL2are used in the formation of the dielectric layer106A in the semiconductor device100E.

As illustrated inFIG.6, the dielectric layers106A includes a first dielectric layer106A1(first COF layer), a second dielectric layer106A2(second COF layer), a third dielectric layer106A3(third COF layer), a fourth dielectric layer106A4(fourth COF layer), a fifth dielectric layer106A5(fifth COF layer), a sixth dielectric layer106A6(sixth COF layer), a seventh dielectric layer106A7(seventh COF layer) and an eighth dielectric layer106A8(eighth COF layer) disposed over the bottom dielectric layer104A and stacked up in sequence. In the exemplary embodiment, the first, third, fifth, and seventh dielectric layer (106A1,106A3,106A5and106A7) are made of the first COF material CFL1, while the second, fourth, sixth and eighth dielectric layer (106A2,106A4,106A6and106A8) are made of the second COF material CFL2. In other words, the dielectric layers106A made of the second COF material CFL2having higher thermal conductivity are interposed between the dielectric layers106A made of the first COF material CFL1. Furthermore, each of the dielectric layers (106A1-106A8) have a two-dimensional material layer103and an etch-stop layer105(not shown) located underneath (corresponding to the structure shown inFIG.3BorFIG.5A).

Similar to the above embodiments, in the semiconductor device100E, since the first COF material CFL1(with two-dimensional building block) and the second COF material CFL2(with three-dimensional building block) are used in replacement of the conventional low-k dielectric materials (typically with dielectric constant of ˜3 and thermal conductivity of <1 W/(m·K)) in the interconnection layer106, the covalent bonds and highly ordered ring structure in the COF layers enables high thermal conductivities and high mechanical strengths. Furthermore, due to the arrangement of the dielectric layers106A made of the second COF material CFL2interposed between the dielectric layers106A made of the first COF material CFL1, the thermal conductivities and mechanical strengths can be further improved as compared with the use of the first COF material CFL1alone. Overall, the heat dissipation efficiency and the parasitic capacitance of the semiconductor device100E can be further improved to fulfill the needs of BEOL performance and reliability requirement in the advanced node.

FIG.7is a schematic cross-sectional view of a semiconductor device in accordance with some other embodiments of the disclosure. The semiconductor device100F shown inFIG.7is similar to the semiconductor device100E shown inFIG.6. Therefore, the same reference numerals are used to refer to the same or liked parts, and its detailed description will be omitted herein. The difference between the embodiments is that an auxiliary metal organic framework (MOF) layer ACF1is further included.

As illustrated inFIG.7, a topmost dielectric layer106A in the interconnection layer106is an auxiliary metal organic framework (MOF) layer ACF1, whereby an auxiliary conductive layer ACL2(including the conductive layer106B) is embedded in the auxiliary MOF layer ACF1. In the exemplary embodiment, the auxiliary MOF layer ACF1is for example, MOF-5, MOF-119, UIO-66, or the like. The auxiliary MOF layer ACF1has a dielectric constant (k value) of 2 or less. However, the auxiliary MOF layer ACF1has lower mechanical strength and lower thermal conductivities than the first COF material CFL1and the second COF material CFL2. In other words, the formation of covalent bond frameworks provides higher mechanical strength and thermal conductivities. As such, if an auxiliary MOF layer ACF1is included, the number of auxiliary MOF layers ACF1should be less than the number of the dielectric layers106A made of the first COF material CFL1or the second COF material CFL2.

Similar to the above embodiments, in the semiconductor device100F, since the first COF material CFL1(with two-dimensional building block) and the second COF material CFL2(with three-dimensional building block) are used in replacement of the conventional low-k dielectric materials (typically with dielectric constant of ˜3 and thermal conductivity of <1 W/(m·K)) in the interconnection layer106, the covalent bonds and highly ordered ring structure in the COF layers enables high thermal conductivities and high mechanical strengths. Furthermore, due to the arrangement of the dielectric layers106A made of the second COF material CFL2interposed between the dielectric layers106A made of the first COF material CFL1, the thermal conductivities and mechanical strengths can be further improved as compared with the use of the first COF material CFL1alone. Overall, the heat dissipation efficiency and the parasitic capacitance of the semiconductor device100F can be further improved to fulfill the needs of BEOL performance and reliability requirement in the advanced node.

In the above-mentioned embodiments, the semiconductor device includes an interconnection layer having dielectric layers that are porous organic framework (POF) dielectrics having a dielectric constant of 2 or less, and a thermal conductivity of 1 W/(m·K) or more. As such, the thermal conductivities and mechanical strengths of the BEOL dielectrics can be further improved as compared with conventional low-k materials, which suffers from low mechanical strength issues and low thermal conductivity issues leading to degradation of device performance. Overall, the heat dissipation efficiency and the parasitic capacitance of the semiconductor device can be further improved to fulfill the needs of BEOL performance and reliability requirement in the advanced node.

In accordance with some embodiments of the present disclosure, a semiconductor device includes a substrate and an interconnection layer disposed on the substrate. The interconnection layer includes a plurality of etch-stop layers, a plurality of first dielectric layers, and a plurality of conductive layers. The first dielectric layers are disposed on the plurality of etch-stop layers, wherein the plurality of first dielectric layers comprises porous organic framework (POF) dielectrics having a dielectric constant of 2 or less, and a thermal conductivity of 1 W/(m·K) or more. The conductive layers are embedded in the first dielectric layers.

In accordance with some other embodiments of the present disclosure, the semiconductor device includes a substrate, an interconnection layer disposed on the substrate, a passivation layer disposed on the interconnection layer, and conductive terminals disposed on the passivation layer and electrically connected to the interconnection layer. The interconnection layer includes a first covalent organic framework (COF) layer, a first conductive layer, a second COF layer and a second conductive layer. The first COF layer is disposed on the substrate. The first conductive layer is surrounded by the first COF layer. The second COF layer is disposed on the first COF layer, wherein a thermal conductivity of the second COF layer is higher than the first COF layer. The second conductive layer is surrounded by the second COF layer.

In accordance with yet another embodiment of the present disclosure, a method of fabricating a semiconductor device is described. The method includes the following steps. A substrate is provided. An interconnection layer is formed on the substrate. The formation of interconnection layer includes: forming a first covalent organic framework (COF) layer on the substrate; patterning the first COF layer to form a first opening, and forming a first conductive layer in the first opening so that it is surrounded by the first COF layer; forming a second COF layer on the first COF layer, wherein a thermal conductivity of the second COF layer is higher than the first COF layer; and patterning the second COF layer to form a second opening, and forming a second conductive layer in the second opening so that it is surrounded by the second COF layer. A passivation layer is formed on the interconnection layer, and conductive terminals are formed on the passivation layer and electrically connected to the interconnection layer.