Fast access with low leakage and low power technique for read only memory devices

A Read Only Memory (ROM) and method for providing a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. The source of the ROM cell (NMOS) is connected to a virtual ground line (VNGD) instead of VSS. Thus, the ROM cell can be operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage. Non-selected columns virtual ground can be maintained at a supply voltage to ensure that unwanted columns will not have any sub-threshold current (as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM achieves a high operational speed with reduced leakage and low power consumption.

FIELD OF THE INVENTION

Embodiments are generally related to memory devices and components. Embodiments also relate to ROM (Read Only Memory) devices and more particularly to ROMS having high operational speeds with reduced leakage and lower power consumption.

BACKGROUND

Semiconductor memory devices have undergone various design changes in terms of package density, operating speed, or power/current dissipation. Many devices, such as microprocessors, or other related devices include onboard memory components, which may contain one or more read only memory (ROM) cells.

ROM circuits are generally composed of memory elements disposed in rows and columns. Energizing the word-line corresponding to the desired word and also energizing the column corresponding to the addressed word generally address a particular word in a memory. There are schemes that can reduce static leakage and dynamic power consumption of the bit-line, for example, selectively pre-charging the bit-lines of a selected column.

FIG. 1, for example, illustrates a schematic diagram of a prior art “classical” NOR memory cell core200. Cell core200demonstrates some of the problems with prior art architectures. Depending on the specifications, such prior art ROM configurations can offer high speed and high areas (e.g., NAND memory cell or special NOR memory cells), and may also offer low leakage, zero leakage, and low speeds. Some prior art configurations may also offer a medium area, a low speed, and low leakage. Such schemes, however, do not offer medium area, high speed, and low leakage (the disclosed embodiments do offer these features). The “classical” NOR memory cell core200configuration shown inFIG. 1includes an arrangement in which WL <0, 1, 2, 3> are the word-lines and BL <0> is the column bit-line selected for the READ operation. A GND line can also be included with respect to the cell core200. In general, no discharge takes place if, for example, WL 1 is selected. An accompanying timing diagram20is also shown inFIG. 1. The dashed area28shown inFIG. 1indicates an overlapping of respective selected bit line pre-charge and word-lines24and22. The scheme of circuit200shown inFIG. 1suffers, however, from the problem of high dynamic power and high penalty on speed as the pre-charge is accomplished in the access time period, which overlaps with the word-line selection.

A need exists for ROMs that improve operational speeds while providing power and leakage benefits. As will be seen shortly, the disclosed embodiments can reduce leakage and power dissipation which offer continued high performance.

SUMMARY

It is, therefore, one aspect of the disclosed embodiments to provide improved memory devices and components.

It is another aspect of the disclosed embodiments to provided improved ROM devices and more particularly to ROM devices having high operational speeds with reduced leakage and lower power consumption.

The aforementioned aspects and other objectives and advantages can now be achieved as described herein. A read only memory (ROM) and method thereof are disclosed having a high operational speed with reduced leakage, no core cell standby leakage and low power consumption. Such a ROM generally includes one or more bit lines, one or more word lines, and one or more virtual grounds. Additionally such a ROM includes one or more ROM cells, wherein each ROM cell includes a source operatively coupled to the bit line(s), the word line(s), and the virtual ground such that the virtual ground(s) is pulled down to a ground voltage and with respect to non-selected columns, and virtual ground(s) is maintained at a supply voltage to ensure that unwanted columns do not offer sub-threshold currents. The virtual ground(s) additionally can function as a column select signal. The ROM cell can be, for example, a NMOS transistor.

Such an improved ROM offers a high operational speed with reduced leakage, no core cell standby leakage, and low power consumption. In the proposed invention, the source of the ROM cell (NMOS) is connected to virtual ground line (VGND) instead of VSS. Thus, the ROM cell is operatively coupled to the bit-line, the word-line, and the virtual ground, which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage GND. The non-selected columns virtual ground can be maintained at a supply voltage VDD to ensure that unwanted columns will not have any sub-threshold current (i.e., as Vds=0). Since no pre-charging of bit-line comes in the access time path, the ROM can achieve a high operational speed with reduced leakage and low power consumption.

DETAILED DESCRIPTION

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Thus, for example, although different embodiments are described with respect to different features and components and varying figures, each figure can relate to the prior figure or next figure as part of an overall description of the present invention. Similarly, similar or identical parts or components may be indicated by the same reference numeral or identifier in different figures.

The embodiments described herein generally relate to a high speed with low power and low leakage scheme that employs a ROM cell that is operatively coupled to the bit-line, the word-line, and the virtual ground instead of GND (ground) which also acts as a column select signal. The arrangement of the ROM is such that the virtual ground of the selected column is pulled down to a ground voltage GND. Non-selected columns virtual ground can be maintained at a supply voltage VDD to ensure that unwanted columns will not include any sub-threshold current (as Vds=0). During a standby period, the VGND (virtual ground) and the BLs are pre-charged to “1” so there is practically no BL leakage at all. Since no pre-charging of bit-line comes in the access time path, the disclosed ROM achieves a high operational speed with reduced leakage and low power consumption.

Such an approach therefore offers a high speed ROM with low leakage and low dynamic power. Additionally, no tracking circuitry is required as opposed to bit-line pre-charge tracking circuitry, thus such a design is area efficient and no performance penalty exists due to extra margins. The disclosed embodiments also offering the possibility of utilizing adjacent bit-line(s) for using an unbalanced sense amplifier.

With the disclosed embodiments, bit-lines can be pre-charged to VDD in the default case. The virtual ground, which runs per column, can be pre-charged until VDD is attained. Thus, when no read operation is being performed, the sub-threshold leakage through the ROM cell is negligible as VDS=0. With the rising edge of clock, the selected virtual ground can be pulled to GND from VDD. Since the virtual ground line is pulled down from VDD to GND using NMOS which does not require a tracking path as such (i.e., gets automatically tracked through a “dummy” bit-line which also has its virtual ground pre-charged to VDD and pulled down same as actual bit-line), such a configuration is much faster than pre-charging bit-lines to VDD using PMOS. With the arrival of word-line, bit-line stays at VDD or discharges as per the data stored in memory cell. For the non-accessed columns, since virtual ground is at VDD, no bit-line discharges. Such an approach provides rapid access with reduced leakage and power consumption.

FIG. 2illustrates a schematic diagram of a circuit60for high performance with low power and low leakage, in accordance with a preferred embodiment. Circuit60provides for a ROM cell configuration that includes a bit-line (e.g., bit-lines83,85,90,91also respectively labeled BL1, BL2, BL3, BL4) and a word-line (e.g., word-lines62,64, also respectively labeled WL2, WL1), and a select-cum-discharge signal VGND (i.e., VGND81,87,89,93, also respectively labeled VGND1, VGND2, VGND3, VGND 4). Thus, circuit60provides for an array of memory with a plurality of word-lines, a plurality of bit-lines, and a plurality of virtual ground VGND connections. VGND lines/connections81,87,89,93can act both as column select lines while providing a discharge path. Since only 1 ROM cell per column discharges, the level of VGND remains at GND

Clock diagram100shown inFIG. 2demonstrates sample operations corresponding to circuit60. Clock signals102,104,106,108, and110shown in the clock diagram100correspond respectively to WL1, VGND1, BL1, VGND <2-4> (Unselected), and BL <2-4> (Unselected BL). The dashed area112shown inFIG. 2indicate no leakage as Vds is zero. The dashed area114shown inFIG. 2indicates no power loss and that the bit-line pre-charge and word-line do not overlap. Thus, the VGND level remains at GND as only one memory cell discharges through it.

Depending on the column that has been selected, the corresponding GND can be pulled down to zero at the arrival of clock. The NMOS device used to bring VGND low can be made sufficiently large so that the VGND acts as virtual ground. There is no requirement of VGND to be brought to “O” before word-line is turned ON. Thus, the word-line need not be delayed as in other low leakage ROM architecture. Thus a much faster low leakage ROM is achieved with the proposal. The remainder of the column selects VGND lines can be connected to VDD, so that the bit-lines in other columns (i.e., not intended to be read) will not discharge. This provides a selective reading of column since memory in those columns have Vds=0.

Adjacent bit-line can be used as inputs to an unbalanced latch type sense amplifier. However, a switch has to be used to route the selected bit-line to the drain of the weaker NMOS. This makes the unbalanced sense amplifier more noise immune as none of the two nodes of sense amplifier are tied to the supply voltage VDD. Use of adjacent bit-line for unbalanced sense amplifier is not possible in the case of the prior configuration shown inFIG. 1.

Note that since in the non-accessed case the Vds across the ROM cell is “0”, no sub-threshold leakage takes place achieving low leakage. Also since the bit-line are not pre-charged in the access cycle, and that no overlapping of pre-charge and word-line selection takes place, low power consumption can be achieved.

FIG. 3illustrates a flow chart of operations illustrating logical operational steps of a prior art method260associated with a medium area, low speed, and low leakage ROM architecture. As shown at block262, an operation can be implemented in which by default BL <0> is at GND (0). There is 0 leakage during this phase or operation. As indicated next at block264, at the start of the cycle BL <0> is pre-charged to VDD. Then, as illustrated at block266, after BL <0> reaches complete VDD, only then is the word-line allowed to go HIGH. Note that with such a prior art configuration, a tracking circuit is likely required to track the pre-charging or circuit failure could occur. A penalty of around 30% (CK to WL timing) therefore is present with respect to the total access time. The “dummy” block for tracking is also a major area of loss. This is a significant problem with such prior art schemes.

Following implementation of the operation depicted at block266, the bit-line discharge/non-discharge can be detected at the output via, for example, a sense amplifier. Finally, as described at block270, whatever the level bit-line is, it is discharged to 0 to bring it to the default state.

FIG. 4illustrates a schematic diagram of a circuit280that includes a NOR memcell core incorporating a virtual GND arrangement, in accordance with an alternative embodiment. In the arrangement of circuit280shown inFIG. 4, WL <0, 1, 2, 3> are the word-lines. BL <0> is the column bit-line selected for a READ operation. A virtual_GND (virtual ground) is also shown in circuit280. By default, the virtual_GND will be at VDD to eradicate any leakage during the default state.

FIG. 5illustrates a high-level flow chart of operations depicting logical operational steps of a method300for a medium area, high-speed, and low leakage ROM configuration with virtual ground, in accordance with the disclosed embodiments. Note that the method300shown inFIG. 5can apply to, for example, the preferred embodiment shown inFIG. 2and the alternative embodiment depicted inFIG. 4. As shown at block302, by default BL <0> and Virtual_GND are at VDD. Thus, zero leakage is present during this step. Thereafter, as illustrated at block304, at the start of the cycle, the virtual GND is discharged to 0. Then, as described at block306, after virtual GND reaches 0, the word-line can be taken to HIGH. Note that even if this criterion is not met, this will only give minimal penalty in timing, and thus no functionality failures will occur. Thereafter, as illustrated at block308, bit-line discharge/non-discharge can be detected at the sense-amplifier. Finally, as shown at block310, whatever level the bit-line is, it is discharged to VDD to bring it to the default state.

Based on the foregoing, it can be appreciated that a number of embodiments, preferred and alternative, are disclosed herein including apparatus and method embodiments thereof. For example, in one embodiment, a read only memory (ROM) having high operational speed with reduced leakage, no core cell standby leakage, and low power consumption can be implemented. Such a ROM may include, for example, one or more bit lines, one or more word lines, one or more virtual grounds, and one or more ROM cells having a source operative coupled to the bit line(s), the word line(s), and the virtual ground(s). The virtual ground can be pulled down to a ground voltage and with respect to non-selected columns, and the virtual ground(s) can be maintained at a supply voltage to ensure that unwanted columns do not offer sub-threshold currents.

In another embodiment the virtual ground(s) can additionally function as a column select signal. In yet another embodiment, the ROM cell(s) can include, for example, a NMOS transistor. In still another embodiment, the virtual ground(s) of a selected column can be pulled to the ground voltage. In yet another embodiment, pre-charging of the bit line(s) does not interfere with an access time path of the ROM, thereby promoting a high operational speed with reduced leakage and low power consumption thereof. In other embodiments, the NOR ROM can be implemented as a NOR memory cell.