Semiconductor device

A semiconductor device including a semiconductor section including a semiconductor element and a recess formed in one of main surfaces and a metallic member at least a part of which is embedded in the recess. A void is formed in a region of the metallic member corresponding to the recess.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device including a metallic member a part of which is embedded in a recess formed in a substrate.

2. Description of the Related Art

A semiconductor device including a substrate in which a semiconductor element and a recess are formed and a metallic member embedded in the recess for release of heat has been hitherto known.

Japanese Patent Publication No. 3791459 (hereinafter, Patent Literature 1) discloses a semiconductor device including a semiconductor layer provided with a semiconductor element formed therein, a support substrate formed a plurality of recesses for supporting the semiconductor layer and a metallic member embedded in the recess of the support substrate. The metallic member is made of a material with high thermal conductivity such as copper, aluminum, silver, gold, copper alloy, aluminum alloy, silver alloy, and gold alloy to quickly release heat generated in upper part of the semiconductor element during operation of the semiconductor element.

However, the linear expansion coefficients of copper and aluminum are 17×10−6/° C. and 23×10−6/° C., respectively while the linear expansion coefficient of the support substrate, for example, a silicon substrate is 3×10−6/° C. In the semiconductor device of the aforementioned Patent Literature 1, the metallic member and support substrate are different in linear expansion coefficient. Accordingly, stress due to the difference in linear expansion coefficient affects the support substrate. Furthermore, part of the support substrate where the recess is formed to embed the metallic member therein is thinner than part of the substrate where the recess is not formed. Accordingly, the support substrate warps and deforms.

SUMMARY OF THE INVENTION

The present invention was invented to solve the aforementioned problem, and an object of the present invention is to provide a semiconductor device capable of preventing itself from changing in electrical characteristics because of deformation of the support substrate due to heat generated during the operation of the semiconductor element and conducted to the support substrate.

A first invention is a semiconductor device including a semiconductor section including a semiconductor element and a recess formed in one of main surfaces and a metallic member at least a part of which is embedded in the recess. A void is formed in a region of the metallic member corresponding to the recess.

According to the first invention, by providing the void in the metallic member, it is possible to prevent deformation of the substrate due to stress caused by a difference in linear expansion coefficient between the substrate and metallic member with the heat release properties thereof maintained or prevented from degrading.

In a second invention, a plurality of the recesses are formed in the one of the main surfaces. Intervals between the recesses in side part of the semiconductor section are narrower than intervals between the recesses in center part of the same.

In a third invention, a plurality of the voids are formed in each of the recess. An electrode section is formed in the other main surface of the semiconductor section. The metallic member is in a low-resistance contact with bottom and side surfaces of the recess, and the metallic member is formed on the other main surface where a recess is not formed.

DETAILED DESCRIPTION OF THE INVENTION

First Embodiment

Hereinafter, with reference to the drawings, a description is given of a semiconductor device according to a first embodiment in which the present invention is applied to a vertical MOSFET.FIG. 1is a partial cross-sectional view of a semiconductor device according to the first embodiment.

As shown inFIG. 1, a semiconductor device1includes a semiconductor section having a substrate2and a semiconductor element region3, electrode sections4, and a drain electrode5(equivalent to metallic members of claims). A region7surrounded by a dotted line inFIG. 1indicates a single unit of the MOSFETs7(equivalent to a semiconductor element of claims).

The substrate2is composed of n+type silicon with a thickness of several hundreds μm and includes a drain region10. In a first main surface2aof the substrate2, the semiconductor element region3is formed. In a second main surface2b(equivalent to one of main surfaces of claims) of the substrate2, a plurality of recesses2care formed so as to extend in a thickness direction and have a width of 1 to 10 μm, for example, about 5 μm, and a depth of 10 to 300 μm, for example, about 100 μm. The recesses2care arranged at intervals of about 5 μm. It is desirable that the aspect ratio (depth/width) of each recess2cfor easy formation of later described voids6in the recesses2is large.

The semiconductor element region3includes a drift region11, base regions12, and source regions13.

The drift regions11are composed of n-type silicon. The drift region11has a concentration of impurities lower than that of the drain region10. The drift region11is formed so as to cover the first main surface2aof the substrate2. The base regions12form channels between the drift region11and the source region13. The base regions12are composed of p-type silicon. The base regions12are formed at predetermined regions in a surface of the drift regions11on the electrode section4side. The base regions12are formed into rectangles larger than the source regions13and surround the respective source region13in a plan view. The source regions13are composed of n+type silicon. The source regions13have a concentration of impurities higher than that of the drift region11. The source region13is formed into a square ring in the base region12.

The electrode sections4includes a gate insulating film15, a gate electrode16, an interlayer insulating film17, and a source electrode18in an upper surface (equivalent to the other main surface of claims) of the semiconductor element region3.

The gate insulating film15is composed of a silicon oxide film and is formed between the semiconductor element region3and gate electrode16. The gate electrode16forms a channel in the base region12sandwiched between the drift region11and source region13. The gate electrode16is composed of polysilicon and is formed on the gate insulating film15. The gate electrode16is formed in a lattice in a plan view and is connected to a metallic gate terminal (not shown). The interlayer insulating film17insulates the gate electrode16from the source electrode18. The interlayer insulating film17is composed of a silicon oxide film. The source electrodes18is electrically connected to the base regions12and source regions13. The source electrode18is composed of an aluminum film.

The drain electrode5is composed of a film stack of titanium and nickel or an aluminum film. The drain electrode5is formed in a low resistance contact to a first part of the second main surface2bof the substrate2where the recesses2care not formed. Desirably, the drain electrode5is formed so as to cover the first part of the second main surface2bof the substrate2in order to reduce contact resistance with the substrate2. Moreover, the drain electrode5is embedded in recesses2cand is formed in a low resistance contact to second parts of the second main surface2bof the substrate2where the recesses2care formed, or side and bottom surfaces of the recesses2c. The drain electrode5does not fill the entire area of each recess2c, and each recess2cincludes a void6formed therein.

Next, a description is given of an operation of the aforementioned semiconductor device1.

When a predetermined voltage is applied to the gate electrode16, channels are formed between the drift region11and source regions13in areas of the base regions12on the gate electrode16side. In this state, when a voltage is applied between the source electrode18and the drain electrode5, current flows from the source electrodes18through the source regions13, the channels of the base regions12, the drift region11, and the drain region10to the drain electrode5.

Next, a description is given of a method of manufacturing the above semiconductor device1with reference to the drawings.FIGS. 2 to 4are partial cross-sectional views of individual manufacturing steps.

First, as shown inFIG. 2, the substrate2composed of n+type silicon is prepared. Next, an n-type silicon layer is epitaxially grown on the first main surface2aof the substrate2. Thereafter, the semiconductor element region3and electrode section4are formed by using a known ion injection method, etching technique, photolithography technique, and the like.

Next, as shown inFIG. 3, a resist film21with a desired pattern is formed on the second main surface2bof the substrate2by a photolithography technique so as to expose part of the substrate2other than regions where the recesses2care formed.

Next, as shown inFIG. 4, the recesses2care formed in the second main surface2bof the substrate2by RIE (reactive ion etching). The resist film21is then removed.

Eventually, as shown inFIG. 1, the drain electrode5including the voids6formed in the individual recesses2care composed of an aluminum film by vacuum deposition. In the step of forming the drain electrode5, the higher the aspect ratio of the recesses2cis, the voids6can be more easily formed when the aluminum film is formed by the vacuum deposition or the like. The semiconductor device1is thus completed.

As described above, in the semiconductor device1according to the first embodiment, the voids6are formed in the drain electrode5. Herein, if the semiconductor device1becomes hot, the difference in linear expansion coefficient between the substrate2which is made of a semiconductor and the drain electrode5which is made of metal, causes a stress. However, the metal of the drain electrode5is more elastic than the substrate2, and deformation of the voids6or the like can relax the stress. Accordingly, the deformation due to warp and the like of the semiconductor device1can be prevented. It is therefore possible to reduce variations in characteristic of the semiconductor device1.

Moreover, the substrate2is thick in the first part of the second main surface2b, and the semiconductor device1is mechanically strong. Furthermore, the drain electrode5and the second part of the main surface2bof the substrate2, where the recesses2care formed, are in low-resistance contact with each other, thus reducing on-resistance thereof. Still furthermore, the drain electrode5has a higher thermal conductivity than that of the substrate2, and accordingly, heat generated by the semiconductor elements can be easily radiated through the drain electrode5.

Second Embodiment

Next, a description is given of a second embodiment obtained by modifying a part of the aforementioned first embodiment with reference to the drawing.FIG. 5is a partial cross-sectional view of a semiconductor device according to the second embodiment. The same components as those of the first embodiment are given same reference numerals, and the description thereof is omitted.

As shown inFIG. 5, in a semiconductor device1A according to the second embodiment, voids6A are formed in a drain electrode5A. An end of each of the voids6A in the thickness direction is opened.

As described above, the semiconductor device1A according to the second embodiment is provided with the voids6A in the drain electrode5A and can therefore provide a similar effect to the first embodiment.

Third Embodiment

Next, with reference to the drawing, a description is given of a third embodiment obtained by modifying a part of the aforementioned first embodiment.FIG. 6is a partial cross-sectional view of a semiconductor device according to the third embodiment. The components same as those of the first embodiment are given same reference numerals, and a description thereof is omitted.

As shown inFIG. 6, in a semiconductor device1B according to the third embodiment, a plurality of voids6B are formed in a region of the drain electrode5B corresponding to each of the recesses2c. The voids6B have the same size and shape. The voids6B are cyclically arranged. The voids6B may have different sizes or shapes. Moreover, the voids6B may be not cyclically arranged.

As described above, the semiconductor device1B according to the third embodiment is provided with the drain electrode5B and the plurality of voids6B formed in each recess2cand can therefore provide a similar effect to that of the first embodiment. Furthermore, a lot of the voids6B are formed in the region corresponding to each recess2C, and the stress can be therefore further reduced.

Fourth Embodiment

Next, a description is given of a fourth embodiment obtained by applying the present invention to a MOSFET having a trench gate structure with reference to the drawing.FIG. 7is a partial cross-sectional view of a semiconductor device according to the fourth embodiment. The components same as those of the first embodiment are given same reference numerals, and a description thereof is omitted.

As shown inFIG. 7, a semiconductor device1C according to the fourth embodiment includes a substrate2C, electrode sections4C, and a drain electrode5C.

In the substrate2C, a drain region10C, a base region12C, and source regions13C are formed. In a first main surface2Ca of the substrate2C, recesses2Cd are formed so as to extend to the center. Each of recesses2Cc is formed corresponding to eight to ten of the recesses2Cd, or eight to ten MOSFETs7C.

The drain region10C is formed in the second main surface2Cb side of the substrate2C and is composed of n+type silicon. The base region12C is formed in the first main surface2Ca side of the substrate2C and is composed of p-type silicon. The source region13C is formed in the first main surface2Ca side of the substrate2C so as to be surrounded by the base region12C. The source region13C is composed of n-type silicon.

Each of the electrode sections4C includes a gate insulating film15C, a gate electrode16C, an interlayer insulating film17C, and a part of a source electrode18C.

The gate insulating film15C is composed of a silicon oxide film and is formed on an inner wall surface of the corresponding recess2C. The gate electrode16C is composed of conductive polysilicon and is embedded within the gate insulating film15C.

The interlayer insulating film17C is composed of a silicon oxide film and is formed so as to cover upper part of the gate insulating film15C and gate electrode16C. The source electrode18C is composed of an aluminum film and is formed so as to cover upper surfaces of the substrate2C and interlayer insulating film17C.

The drain electrode5C is composed of an aluminum film. The drain electrode5C is formed so as to cover the second main surface2Cb of the substrate2. Part of the drain electrode5C is embedded in the recesses2Cc. In a region corresponding to each recess2Cc section of the drain electrode5C, a plurality of voids6C are formed.

As described above, the semiconductor device1C according to the fourth embodiment is provided with the voids6C formed in the drain electrode5C and can therefore provide a similar effect to that of the first embodiment.

Fifth Embodiment

Next, a description is given of a fifth embodiment obtained by modifying a part of the aforementioned first embodiment with reference to the drawing.FIG. 8is a partial cross-sectional view of a semiconductor device according to the fifth embodiment. The components same as those of the first embodiment are given same reference numerals, and a description thereof is omitted.

As shown inFIG. 8, in a semiconductor device1D of the fifth embodiment, intervals between the recesses2care not equal. Herein, intervals of the recess sections2cformed in the center part of the semiconductor device1D are d1, and intervals of the recess sections2cformed in the peripheral part of the semiconductor device1D is d2.

In the semiconductor device1D, the interval d2of the peripheral part, which largely warps and deforms, is set smaller than the interval d1of the center part, which deforms less. Furthermore, in a same region, the number of recesses2cin the peripheral part may be set larger than that in the central part, and the number of voids6formed in the drain electrode5in the peripheral part may be also set larger than that in the central part.

As described above, the semiconductor device1D according to the fifth embodiment, the recesses2care formed more in the peripheral part, which is largely deformed, than in the center part to provide more voids6in the peripheral part. It is therefore possible to prevent deformation of the peripheral part and accordingly further prevent deformation of the entire semiconductor device1D.

Hereinabove, the present invention is described in detail using the embodiments, but the present invention is not limited to the embodiments described in the specification. The scope of the present invention is determined by the description of claims and equivalents thereof. Hereinbelow, a description is given of modifications obtained by partially modifying the above embodiments.

For example, the aforementioned embodiments include the example of the present invention applied to a vertical MOSFET. In addition, the present invention may be also applied to other semiconductor devices such as horizontal MOSFETs and IGBTs.

Moreover, the aforementioned embodiments include the example including the drain electrode with the voids formed therein. The voids may be formed not in the drain electrode but in a heat releasing metallic member formed in the rear surface.

In the aforementioned embodiments, the drain electrode is formed by vacuum deposition but may be formed by spattering, plating, or the like.

In the aforementioned embodiments, the voids are not filled with any material but may be filled with a material softer than the metallic member constituting the drain electrode.

Moreover, the specific numerals in the aforementioned embodiments can be properly changed. For example, the thickness of the substrate, the depth and intervals of the recesses, and the like can be properly changed. Specifically, it may be configured that, in a plan view, only a single large recess is formed in any one of the main surfaces of the substrate and voids are formed in a metallic member provided therein.