Method for forming interconnection in semiconductor pattern device

A method for forming an interconnection pattern in a semiconductor device for reducing metallic reflection, includes the steps of forming a conductive layer on a substrate, polishing the conductive layer to form a rugged surface on the conductive layer, and selectively removing the polished conductive layer to form the interconnection pattern.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a semiconductor device, and more 
particularly to a method for forming an interconnection pattern in a 
semiconductor device which is suitable for reducing metallic reflection. 
2. Discussion of the Related Art 
In Anti-Reflection Coating (ARC) process for reducing reflection, the 
inorganic ARC process and the organic ARC process are widely used. In the 
inorganic ARC process, an appropriate thickness of an ARC film is formed 
on a metal film which causes a strong reflection during exposure and 
induces notching effects. Incident lights are absorbed by the ARC film to 
the maximum, thereby inhibiting notching effects in the exposure. For an 
ARC film, the inorganic ARC process uses TiN, SiN.sub.4 and TiW as 
inorganic film, whereas the organic ARC process uses polymer as organic 
film. 
A conventional method for forming an interconnection pattern using the ARC 
process will be explained with reference to the attached drawings. 
FIGS. 1a-1d illustrate sectional views for explaining the steps of the 
conventional process for forming a conventional interconnection pattern in 
a semiconductor device. 
Referring to FIG. 1a, an insulating film 2 is formed on a silicon substrate 
1 and a metal film 3 is formed on the insulating film 2. In this instant, 
step coverage is formed between a portion of the insulating film 2 where a 
device (not shown) is to be formed and a portion of the insulating film 2 
where no device is formed. To reduce reflections from the metal film 3, an 
ARC film 4 is deposited on the top surface of the metal film 3. 
Then, as shown in FIG. 1b, a photoresist 5 is coated on the ARC film 4, and 
exposed and developed to pattern the photoresist 5. The photoresist 5 is 
used as a mask for selectively etching the ARC film 4 and the metal film 
3. Since the etch selectivity of the ARC film 4 is different from that of 
the metal film 3, some portions of the metal film 3 under the ARC film 4 
are etched excessively, as shown in FIG. 1c. The photoresist pattern 5 is 
completely removed and an interlayer insulating film 6 is formed thereon, 
as shown in FIG. 1d. The conventional process for fabricating an 
interconnection pattern in a semiconductor device is thereby finished. 
The aforementioned conventional method for forming an interconnection 
pattern in a semiconductor device has at least the following problems. 
First, the method is complicated because it requires the ARC film forming 
process. 
Second, there is difficulty in controlling etch selectivity for the ARC 
film and the metal film. Due to the difficult, overetching of the metal 
film occurs. 
Third, overetching of the metal film causes formation of unnecessary gaps 
in a planarizing film formed thereon. 
SUMMARY OF THE INVENTION 
Accordingly, the present invention is directed to a method for forming an 
interconnection pattern in a semiconductor device that substantially 
obviates one or more of the problems arising from limitations and 
disadvantages of the related art. 
An object of the present invention is to provide a method for forming an 
interconnection pattern in a semiconductor device which is suitable for 
reducing metallic reflection. 
Another object of the present invention is to provide a method for forming 
an interconnection pattern in a semiconductor device which can simplify 
the fabrication process and improve reliability of a planarizing 
insulating film formed in the semiconductor device. 
Additional features and advantages of the invention will be set forth in 
the description which follows, and in part will be apparent from the 
description, or may be learned by practice of the invention. The 
objectives and other advantages of the invention will be realized and 
attained by the structure particularly pointed out in the written 
description and claims hereof as well as the appended drawings. 
To achieve these and other advantages and in accordance with the purpose of 
the present invention, as embodied and broadly described, the method for 
forming an interconnection pattern in a semiconductor includes the steps 
of forming a conductive layer on a substrate, polishing the conductive 
layer for forming a rugged surface on the conductive layer, and 
selectively removing the conductive layer for forming an interconnection 
pattern. 
It is to be understood that both the foregoing general description and the 
following detailed description are exemplary and explanatory and are 
intended to provide further explanation of the invention as claimed.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Reference will now be made in detail to the preferred embodiments of the 
present invention, examples of which are illustrated in the accompanying 
drawings. 
FIGS. 2a-2e illustrate sectional views showing steps of a process for 
forming an interconnection pattern in a semiconductor device in accordance 
the embodiments of the present invention. 
Referring to FIG. 2a, an insulating film 12 is formed on a substrate 11. 
The material for the substrate 11 is either a semiconductor material or an 
insulative material, and the material for the insulating film 12 is either 
an oxide or a nitride. A metal film 13 is formed on the insulating film 
12. An alloy film can be formed instead of the metal film 13. The metal 
film 13 is formed of one of Al, W, Cr and Cu, and the alloy film is formed 
of silicon and one selected from Al, W, Cr and Cu. 
Referring to FIG. 2b, the metal film 13 is subjected to CMP (Chemical 
Mechanical Polishing) to make the surface of the metal film 13 rugged and 
to prevent reflections therefrom. 
A method for making the surface of the metal film 13 rugged using CMP will 
be explained. 
In the CMP process, urethane or polyester is used as a pad, and alumina 
(Al.sub.2 O.sub.3) particles as an abrasive and chemicals, such as HF, 
KOH, HCl, H.sub.2 O.sub.2, H.sub.2 O, are used. 
In CMP, a pad is fixed on a plate, and a mixture of abrasive and chemical 
is injected through a polishing liquid feed pipe into the center of the 
plate which is being rotated. A surface of the wafer fixed to a chuck, 
which is rotated in a direction opposite to the rotation direction of the 
plate, is polished on the pad as the wafer reacts with the injected 
mixture. Due to the reaction, the metal film formed on the surface of the 
wafer is polished. 
Polishing may be a chemical mechanical polishing or mechanical polishing, 
depending on the composition of the mixture of a polishing liquid. In case 
of chemical mechanical polishing, the composition of polishing liquid may 
be Al.sub.2 O.sub.3 (alumina) particles+(HF or HCl)+H.sub.2 O.sub.2 
+H.sub.2 O. Therefore, mechanical polishing is carried out by the Al.sub.2 
O.sub.3 particles, and chemical polishing is carried out by HF or HCl. In 
case of mechanical polishing, the composition of a polishing liquid may be 
Al.sub.2 O.sub.3 particles+H.sub.2 O. The mechanical polishing is carried 
out by the Al.sub.2 O.sub.3 particles mechanically only. The ruggedness of 
the top surface of the metal film 13 is dependent on the size of Al.sub.2 
O.sub.3 particles. Here, the size of the Al.sub.2 O.sub.3 particles is 
about 200.about.1000 .ANG., and the thickness of the polished metal film 
13 is about 100.about.500 .ANG.. Different Al.sub.2 O.sub.3 particle sizes 
can be used to obtain a desired polished thickness for the metal film. 
Referring to FIG. 2c, a photoresist is coated on the polished metal film 
13, and exposed and developed using an interconnection pattern mask (not 
shown) to form a photoresist pattern 14. As shown in FIG. 2d, the 
photoresist pattern 14 is used as a mask in subjecting the metal film 13 
to anisotropic etching for forming a metal interconnection pattern 13'. 
Referring to FIG. 2e, the photoresist pattern 14 is completely removed and 
a planarizing insulating film 15 is formed on the metal interconnection 
pattern 13' and the insulating film 12. 
FIGS. 3a-3e show steps for forming a polished metal film on a stepped 
substrate in a semiconductor device according to the embodiments of the 
present invention. To polish the metal film formed on a stepped substrate, 
a flexible pad is used in the CMP process. That is, in order to make a 
simultaneous abrasion of the upper and lower portions of the step in the 
metal film, a flexible pad is used to control abrasive force. 
The steps for forming a polished metal film on a stepped substrate are 
similar to the steps shown in FIGS. 2a-2e, which will be discussed below. 
Referring to FIG. 3a, an insulating film 22 and a metal film 23 are formed 
on a substrate 21, wherein one or more layers 21-23 have a step therein. 
The material for the substrate 21 is either a semiconductor material or an 
insulative material, the material for the insulating film 22 is either an 
oxide or a nitride, and the metal film 23 is formed of one of Al, W, Cr, 
and Cu. An alloy film can be used instead of the metal film 23 and the 
alloy film can be formed of silicon and one selected from Al, W, Cr and 
Cu. 
Referring to FIG. 3b, the metal film 23 is subjected to a CMP (Chemical 
Mechanical Polishing) process to make the surface of the metal film 23 
rugged and to prevent reflections therefrom. In the CMP process, urethane 
or polyester as a pad, alumina (Al.sub.2 O.sub.3) particles as abrasive, 
and chemicals, such as HF, KOH, HCl, H.sub.2 O.sub.2, H.sub.2 O, are used. 
Polishing may be a chemical mechanical polishing or a mechanical chemical 
polishing, depending on the composition of the mixture of polishing 
liquid. 
In case of chemical mechanical polishing, the composition of a polishing 
liquid may be Al.sub.2 O.sub.3 (alumina) particles+(HF or HCl)+H.sub.2 
O.sub.2 +H.sub.2 O. Therefore, mechanical polishing is carried out by the 
Al.sub.2 O.sub.3 particles, and chemical polishing is carried out by HF or 
HCl. In case of mechanical polishing, the composition of a polishing 
liquid may be Al.sub.2 O.sub.3 particles+H.sub.2 O. The mechanical 
polishing is carried out by the Al.sub.2 O.sub.3 particles mechanically 
only. The ruggedness of the top surface of the metal film 23 is dependent 
on the size of Al.sub.2 O.sub.3 particles. Here, the size of the Al.sub.2 
O.sub.3 particles is about 200.about.1000 .ANG., and the thickness of the 
polished metal film 13 is about 100.about.500 .ANG.. Different Al.sub.2 
O.sub.3 particle sizes can be used to obtain a desired polished thickness 
for the metal film. 
Referring to FIG. 3c, a photoresist is coated on the polished metal film 
23, and exposed and developed using an interconnection pattern mask (not 
shown) to form a photoresist pattern 24. As shown in FIG. 3d, the 
photoresist pattern 24 is used as a mask in subjecting the metal film 23 
to anisotropic etching for forming a metal interconnection pattern 23'. 
The photoresist pattern 24 is completely removed and a planarizing 
insulating film 25 is formed on the metal interconnection pattern 23' and 
the insulating film 22 as shown in FIG. 3e. 
The method for forming an interconnection pattern in a semiconductor device 
according to the embodiments of the present invention has the following 
advantages. 
First, the rugged surface of the metal film reduces reflection from the 
metal surface when exposing the metal film to form a metal film pattern. 
It inhibits occurrence of notching (distortion of a photoresist pattern). 
Notching occurs due to lights scattered from the surface of the metal film 
and due to interference of lights arising when a photoresist is deposited 
and exposed to form the photoresist pattern. 
Second, the entire fabrication process is simplified since no ARC process 
is required for reducing reflections from the metal film. 
Third, etch selectivity for metal etching and profile need not be taken 
into account in order to avoid overetching. 
Fourth, since accurate patterning of the metal film allows no gaps to be 
formed in the planarizing insulating film formed on the metal film, 
reliability of the planarizing insulating film is improved. 
It will be apparent to those skilled in the art that various modifications 
and variations can be made in the methods for fabricating the 
semiconductor device according to the present invention without departing 
from the spirit or scope of the invention. Thus, it is intended that the 
present invention covers the modifications and variations of this 
invention provided they come within the scope of the appended claims and 
their equivalents.