Method and apparatus for generating a frequency estimation signal

A frequency estimation signal generator component arranged to receive an input frequency signal and to generate therefrom a frequency estimation signal. The frequency estimation signal generator component comprises a counter component arranged to sequentially output a sequence of control signal patterns over a plurality of digital control signals under the control of an oscillating signal derived from the received input frequency signal terns. The frequency estimation signal generator further comprises a continuous waveform generator component arranged to receive the plurality of digital control signals and a weighted analogue signal for each of the received digital control signals, and to output a continuous waveform signal comprising a sum of the weighted analogue signals for which the corresponding digital control signals comprise an asserted logical state. The frequency conversion component is arranged to derive the frequency estimation signal from the continuous waveform signal output by the continuous waveform generator component.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority under 35 U.S.C. § 119 of European Patent application no. 16203729.5, filed on Dec. 13, 2016, the contents of which are incorporated by reference herein.

FIELD OF THE INVENTION

This invention relates to a method and apparatus for generating frequency estimation signal, and in particular to a frequency estimation signal generator component arranged to receive an input frequency signal and to generate therefrom a frequency estimation signal in digital form.

BACKGROUND OF THE INVENTION

In Frequency-Modulated Continuous Wave (FMCW) automotive radar systems, the frequency of the transmitted signal is controlled by a voltage controlled local oscillator (VCO) and accurate run time monitoring of the VCO frequency is crucial for such systems.

In a FMCW automotive radar system, the transmitted signal (e.g. a 76 to 77 GHz mm-Wave sine wave with linear frequency modulation chirp) is controlled by a voltage controlled oscillator (VCO). In such a system, one of the mandatory functions is the ability for run-time monitoring of the VCO frequency with sufficient accuracy for the purpose of built-in self-test and functional safety requirements of automotive applications. A conventional approach to monitoring VCO frequency is illustrated inFIG. 1. Firstly the frequency of the VCO output signal110(e.g. ˜27 GHz) is scaled down by a clock divider120(e.g. by a factor of 512, to a frequency around 50 MHz). The output signal125of the divider120is filtered130to remove its harmonics from its fundamental signal. After that, the filtered signal135is digitized by an analogue-to-digital converter (ADC)140for further digital signal processing to estimate the frequency of the VCO output signal110.

A problem with this conventional approach for monitoring the frequency of a VCO output signal is that the output waveform125of the divider120is a square wave (or a heavily distorted sine wave), and so it has very strong harmonic tones close to the fundamental tone (especially the third order harmonic tone). In order to estimate the frequency of the VCO output signal110accurately, these harmonics of the divider output signal125need to be sufficiently filtered out in accordance with the system requirements, which can require a very complex high order analogue filter in order to have enough suppression of the harmonics to fulfil stringent accuracy requirements. For example, in a FMCW automotive radar system, the requirements for the analogue filter may be:passband: 45-55 MHz, ripple <2 dB; andstopband: attenuation >70 dB for f>150 MHz.

The 70 dB suppression on the 3rdharmonic is a tough specification and a 9th order Butterworth filter is typically required to achieve such suppression. For such a complex filtering function, it is very difficult and cost ineffective to be implemented in advance CMOS technology due to the noise, bandwidth and linearity performance typically required resulting in large power and area penalties to implement. Consequently, such a complex filtering function is typically implemented on a separate chip with a dedicated technology, often based on Cauer or Sallen-Key topologies and requiring many bulky passive components or multiple high gain and low noise amplifiers as well as calibration or trimming to maintain the desired filter characteristics over PVT (process voltage temperature) variations.

SUMMARY OF THE INVENTION

The present invention provides a frequency estimation signal generator component, a frequency monitor circuit for performing run-time frequency monitoring of an input signal and a method of generating a frequency estimation signal for performing run-time frequency monitoring of an input frequency signal as described in the accompanying claims.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention will now be described with reference to the accompanying drawings. However, it will be appreciated that the present invention is not limited to the specific embodiments herein described and as illustrated in the accompanying drawings, and that various modifications may be made without departing from the inventive concept.

Referring first toFIG. 2there is illustrated a simplified block diagram of an example embodiment of a part of a frequency monitor circuit200for performing run-time frequency monitoring of an input frequency signal205. For example, the frequency monitor circuit200may be arranged to perform run-time frequency monitoring of an oscillator signal for a Frequency-Modulated Continuous Wave (FMCW) automotive radar system. However, it is contemplated that the frequency monitor circuit200may equally be used in other types of systems that require frequency monitoring or measurement.

In the example embodiment illustrated inFIG. 2, the frequency monitor circuit200comprises a frequency estimation signal generator component210arranged to receive the input frequency signal205and to generate therefrom a frequency estimation signal215from which a frequency of the input frequency signal205may be estimated. In the illustrated example, the frequency estimation signal215comprises an analogue signal which is provided to an analogue-to-digital converter220which digitizes the frequency estimation signal215for further digital signal processing to estimate the frequency of the input frequency signal205.

The frequency estimation signal generator component210comprises a counter component240arranged to receive an oscillating signal235derived from the input frequency signal205. In the example embodiment illustrated inFIG. 2, the oscillating signal235is derived by a divider component230arranged to receive the input frequency signal205and to perform frequency division of the input frequency signal205to generate the oscillating signal235received by the counter component240. Accordingly, in the illustrated example the divider component230is arranged to divide the frequency of the input frequency signal205by N, and the oscillating signal235received by the counter component240comprises a fundamental frequency equal to 1/N the frequency of the input frequency signal205.

The counter component240is arranged to output a plurality of digital control signals245. The counter component240is further arranged to output a sequence of k control signal patterns, and is controllable by the received oscillating signal235to sequentially step through the k control signal patterns. For example, and as described in greater detail below, the counter component240may be arranged to sequentially step through the k control signal patterns upon every n cycle(s) of the received oscillating signal235, where n≥1. In the manner, the counter component240may be arranged to cycle through the sequence of k control signal patterns once every n*k cycles of the oscillating signal235.

The frequency estimation signal generator210further comprises a continuous waveform generator component250arranged to receive the M digital control signals245output by the counter component240and a weighted analogue signal260for each of the received digital control signals245(thus M weighted analogue signals260), and to output a continuous waveform signal255comprising a sum of the weighted analogue signals260for which the corresponding digital control signals245comprise an asserted logical state. In this manner, the continuous waveform signal255output by the continuous waveform generator250will have a repetitive profile that repeats each cycle of the sequence of k control signal patterns.

In some example embodiments, the weighted analogue signals260comprise weighted current signals, and the continuous waveform signal255output by the continuous waveform generator250comprises a continuous summed current signal applied to a resistive load275that converts the continuous summed current signal into a continuous waveform voltage signal255at the output of the continuous waveform generator250. For some alternative embodiments, it is contemplated that the weighted analogue signals260may alternatively comprise weighted signals in charge form or weighted voltage signals, and the continuous waveform signal255output by the continuous waveform generator250comprises a summed continuous voltage waveform signal.

The frequency conversion component210is arranged to derive the frequency estimation signal215from the continuous waveform signal255output by the continuous waveform generator component250. As illustrated inFIG. 2, the frequency conversion component210may further comprise a low-order filter270arranged to perform low-order filtering of the continuous waveform signal255output by the continuous waveform generator component250to derive the frequency estimation signal215.

In some example embodiments, such as described in greater detail below, the sequence of control signal patterns generated by the counter component240and the weighted analogue signals260are arranged such that the continuous waveform signal255output by the continuous waveform generator250comprises a substantially sinusoidal profile.

FIG. 3illustrates a simplified block diagram of the frequency conversion component210showing an example implementation of the continuous waveform generator component250in greater detail. The counter component240arranged to receive the oscillating signal235derived by the divider component230from the input frequency signal205, and to sequentially output a sequence of k control signal patterns upon every n cycle(s) of the received oscillating signal235.

FIG. 4illustrates an example of a sequence400of control signal patterns that may be generated by the counter component240. In the examples illustrated inFIGS. 3 and 4, the counter component240is arranged to output a set of M digital control signals245made up of a first subset410of M/2 ‘down’ control signals, labelled D_0to D_7, and a second subset420of M/2 ‘up’ control signals, labelled U_0to U_7. In the illustrated example M=16. Each cycle430of the oscillating signal235output by the divider component230the logical state of one of the control signals245is transitioned, either from an asserted logical state to an un-asserted logical state or from an un-asserted logical state to an asserted logical state. Each control signal245is transitioned from an un-asserted logical state to an asserted logical state and from an asserted logical state to an un-asserted logical state once within the sequence400of control signal patterns. Thus, the sequence400comprises 32 control signal patterns (2*16) and a complete cycle of the sequence400of control signal patterns occurs over 32 cycles430of the oscillating signal235output by the divider component230.

In the example illustrated inFIG. 4, the sequence400of control signal patterns comprises:a down asserting phase412during which the subset410of down control signals are sequentially transitioned from un-asserted states to asserted states;a down de-asserting phase414during which the subset410of down control signals are sequentially transitioned from asserted states to un-asserted states;an up asserting phase422during which the subset420of up control signals are sequentially transitioned from un-asserted states to asserted states; andan up de-asserting phase424during which the subset420of up control signals are sequentially transitioned from asserted states to un-asserted states.

At the start of the down asserting phase412, a first control signal D_7from the subset410of down control signals is transitioned from an un-asserted logical state (which in the illustrated example comprises a ‘high’ state) to an asserted logical state (which in the illustrated example comprises a ‘low’ state) and all other control signals are maintained at an un-asserted logical state. Accordingly for the first control signal pattern in the down asserting phase412of the sequence400of control signal patterns, the first control signal D_7from the subset410of down control signals is asserted whilst all other control signals are un-asserted. For each subsequent control signal pattern in the down asserting phase412of the sequence400of control signal patterns, one more of the control signals from the subset410of down control signals is transitioned from an un-asserted logical state to an asserted logical state until all of the control signals from the subset410of down control signals are asserted, in the eighth control signal pattern of the down asserting phase412of the sequence400of control signal patterns.

During the down de-asserting phase414, the control signals from the subset410of down control signals are sequentially transitioned to the un-asserted logical state in the reverse order in which they were transitioned to the asserted logical state during the down asserting phase412; one control signal being transitioned between each control signal pattern, until all control signals are once again in un-asserted logical states.

At the start of the up asserting phase422, a first control signal U_7from the subset420of up control signals is transitioned from an un-asserted logical state (which in the illustrated example comprises a ‘high’ state) to an asserted logical state (which in the illustrated example comprises a ‘low’ state) and all other control signals are maintained at an un-asserted logical state. Accordingly for the first control signal pattern in the up asserting phase422of the sequence400of control signal patterns, the first control signal U_7from the subset420of up control signals is asserted whilst all other control signals are un-asserted. For each subsequent control signal pattern in the up asserting phase422of the sequence400of control signal patterns, one more of the control signals from the subset420of up control signals is transitioned from an un-asserted logical state to an asserted logical state until all of the control signals from the subset420of up control signals are asserted, in the eighth control signal pattern of the up asserting phase422of the sequence400of control signal patterns.

During the up de-asserting phase424, the control signals from the subset420of up control signals are sequentially transitioned to the un-asserted logical state in the reverse order in which they were transitioned to the asserted logical state during the up asserting phase422; one control signal being transitioned between each control signal pattern, until all control signals are once again in un-asserted logical states.

Referring back toFIG. 3, in this illustrated example the continuous waveform generator component250comprises a set of switch drivers310. For example, inFIG. 3the counter component240is arranged to output M (e.g. sixteen) digital control signals245. Accordingly, the continuous waveform generator component250ofFIG. 3may comprise M (e.g. sixteen) switch drivers310, one for each control signal245.FIG. 5illustrates a simplified block diagram of one example of such a switch driver310. In the example illustrated inFIG. 5, the switch driver310comprises a latch component510arranged to receive at a data input thereof one of the control signals245, and the oscillating signal235output by the divider component230as a clock signal. The output of the latch component510is provided to an input of a buffer520, which outputs a driver signal315for the switch driver310. In this manner, each switch driver310is arranged to generate a driver signal315corresponding to the received control signal245, with the oscillating signal235being used to synchronise the driver signals315output by the switch drivers310.

Referring back toFIG. 3, the driver signals315output by the switch drivers310are provided to a set of switching components320, the switching components230being arranged to receive the driver signals315output by the switch drivers310and the weighted analogue signals260and to collectively generate the continuous waveform signal255comprising a sum of the weighted analogue signals260for which the corresponding driver signals315comprise an asserted logical state.

FIG. 6schematically illustrates a simplified diagram of one example of such a switching component320. In particular,FIG. 6illustrates a switching component320comprises a tri-state operation and is arranged to receive a pair of driver signals315and a pair of weighted current signals260, and to steer the current signals to a first output610, a second output620or to both outputs610,620, depending on the received driver signals315.

For example, each switching component320may be arranged to receive a pair of driver signals315generated from an up control signal U_i from the subset420of up control signals and a corresponding down control signal D_i from the subset410of down control signals. Table 1 below illustrates the tri-state operation for the example switching component320ofFIG. 5.

In some examples, the received weighted current signals260may comprise equally weighted current signals, for example generated by a split current source, such as the split current source700illustrated inFIG. 7. Accordingly, the frequency estimation signal generator component210illustrated inFIG. 3may comprise a weighted current sources330in the form of eight split current sources700, each arranged to output a pair of equally weighted current signals to a corresponding switching component320.

Referring back toFIG. 6, as outlined above the switching component320is arranged to steer the weighted current signals260between a first output610and a second output620, depending on the received driver signals315. In this manner a first output current signal615is generated at the first output610of the switching component320and a second output current signal625is generated at the second output620of the switching component320. In accordance with some example embodiments, the output current signals615,625generated by the switching component320may comprise a pair of complementary up and down current signals615,625.

Referring back toFIG. 3, the output currents615,625generated by the switching components320may then be converted to a voltage signal, for example by a current to voltage converter circuit340.FIG. 8illustrates a simplified diagram of an example implementation of such a current-to-voltage converter circuit340. In the illustrated example, the up current signals615from the switching components320are combined and collectively routed through a first resistance810to generate an ‘up’ voltage signal Voutp815across the first resistance810, whilst the down current signals625from the switching components320are combined and collectively routed through a second resistance820to generate a ‘down’ voltage signal Voutn825across the second resistance820. The difference between the up and down voltage signals815,825may then used to generate to an output voltage waveform VoutFor example, where the first and second resistances810,820are equal, the output voltage Voutmay be expressed as:
Vout=Voutn−Voutp=R*Σi=07((Ioutpi)−(Ioutn,i))  Equation 1

FIG. 9illustrates a plot of an example output voltage from the current-to-voltage converter circuit340in response to the sequence400of control signal patterns illustrated inFIG. 4that may be generated by the counter component240. For the example output voltage illustrated inFIG. 9, the current signals260provided to the switching components320have been progressively weighted by factors W0to W7. For example, to achieve a normalised output voltage ranged from −1 to 1, the current signals260may be progressively weighted by [0.1951 0.1876 0.1729 0.1515 0.1244 0.0924 0.0569 0.0192]. Notably, by multiplying the control signals245output by the counter component240with the progressively weighted current signals260, and summing the resulting currents, a continuous waveform may be generated that resembles a zero-order hold reconstructed sin wave.

Significantly, the mixed-signal approach herein described enables the suppression of undesired harmonics of the divider component230, thereby significantly relaxing any subsequent filtering requirements. The output signal255of the frequency estimation signal generator component210comprises a repeating waveform having a cycle equal to that of the sequence of control signal patterns generated by the counter component240, and thus equal to n*k cycles of the oscillating signal235; i.e. equal to N*n*k cycles of the input frequency signal205. Thus, the fundamental tone of the oscillating signal235output by the divider component230is preserved while its harmonic tones are greatly suppressed (the choice of the pre-defined weights determining how much the harmonic tones can be suppressed). By selecting a proper number of points (with equal spacing in time domain) for reconstructing a sin wave (i.e. the number of control signal patterns within the sequence), the only unwanted tones (image tones due to the zero-order hold function) that need to be suppressed may be located at much higher frequencies and can be filtered using a simple low order analogue filter, such as illustrated at270, (for example just a simple first order RC filter).

For example,FIG. 10illustrates a first plot1010showing an example waveform output by the divider component230, and a second plot1020illustrating the frequency spectrum for the waveform of the first plot1010. The attenuation required to achieve the stringent 70 dB suppression on the 3rdharmonic for FMCW automotive radar systems is illustrated by the broken line at1025.FIG. 11illustrates a first plot1110showing an example 32 points/cycle sinusoidal waveform output by the frequency estimation signal generator component210in response to the example waveform output by the divider component230in the first plot1010ofFIG. 10, and a second plot1120illustrating the frequency spectrum for the waveform of the first plot1110. As shown in this example, the harmonic tones of the waveform output by the divider component230have been greatly suppressed within the sinusoidal waveform output by the frequency estimation signal generator component210. Accordingly, the image tones sinusoidal waveform output by the frequency estimation signal generator component210(illustrated in the second plot1120inFIG. 11) are spaced far away from the fundamental tone (more than 30 times the fundamental frequency in this example) which greatly relaxes the filter requirements for the stringent 70 dB suppression on the 3rdharmonic for FMCW automotive radar systems as illustrated by the broken line at1125.

Advantageously, because of the reduced filtering requirements, and the reduced sensitivity to process variation, a frequency monitor circuit for performing run-time frequency monitoring of an input signal, such as the frequency monitor circuit illustrated inFIG. 2, may be implemented in CMOS (complementary metal oxide semiconductor) technology, and thus integrated with other components of, for example, a radar system. As a result, the proposed solution can help to realize a cost effective single chip solution.

Referring now toFIG. 12, there is illustrated a simplified flowchart1200of an example of a method of generating a frequency estimation signal for performing run-time frequency monitoring of an input signal, for example an oscillator signal for a RMCW automotive radar system, such as may be implemented within the frequency estimation signal generator component210hereinbefore described. The method ofFIG. 12starts at1205and moves on to1210where in input frequency signal is received, such as the input frequency signal205illustrated inFIGS. 2 and 3. In the illustrated example, frequency division is then performed on the received input frequency signal at1220to derive an oscillating signal, such as the oscillating signal235illustrated inFIGS. 2 and 3. Sequentially outputting a sequence of control signal patterns, such as the sequence of control signal patterns400illustrated inFIG. 4, over a plurality of digital control signals at1230under the control of the oscillating signal derived from the received input frequency signal. Weighted analogue signals are received at1240, and a continuous waveform signal is output at1250comprising a sum of the weighted analogue signals for which the corresponding digital control signals comprise an asserted logical state. The frequency estimation signal may then be then derived from the continuous waveform signal at1260, and the method ends at1295.

Furthermore, the terms ‘assert’ or ‘set’ and ‘negate’ (or ‘un-assert’ or ‘clear’) are used herein when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one.

Any arrangement of components to achieve the same functionality is effectively ‘associated’ such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as ‘associated with’ each other such that the desired functionality is achieved, irrespective of architectures or intermediary components. Likewise, any two components so associated can also be viewed as being ‘operably connected,’ or ‘operably coupled,’ to each other to achieve the desired functionality.