MICROELECTRONIC ASSEMBLIES INCLUDING INTERCONNECTS WITH DIFFERENT SOLDER MATERIALS

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

BACKGROUND

Integrated circuit (IC) devices (e.g., dies) are typically coupled together in a multi-die IC package to integrate features or functionality and to facilitate connections to other components, such as package substrates. In a conventional package, dies may be coupled together by solder. Such a package may be limited in the achievable interconnect density by the solder interconnects between the dies.

DETAILED DESCRIPTION

Microelectronic assemblies, related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

Communicating large numbers of signals between two or more dies in a multi-die IC package is challenging due to the increasingly small size of such dies and increased use of stacking dies. Conventional approaches for achieving small form factor, high performance, and high density interconnects in multi-die IC packages includes die partitioning and/or using a small silicon die without through-silicon vias (TSVs) for die-to-die interconnects. Some of these conventional approaches require additional assembly operations and specialized manufacturing equipment, which increases the cost and complexity of manufacturing, and decreases die yields. Another current approach includes embedding a bridge die with TSVs or an active functional die for fine interconnects between multiple dies (e.g., die tiling), however, this approach suffers from a highly cumulative bump thickness variation (BTV), which increases as the number of bridges to be embedded increases, and results in increased cost of manufacturing and reduced yields. The microelectronic structures and assemblies disclosed herein may achieve interconnect densities as high or higher than conventional approaches without the expense of conventional costly manufacturing operations and with increased yields, for example, by reducing the risk of die shifting during reconstitution to prevent a significant true position error, by patterning interconnects directly on a low total thickness variation (TTV) glass carrier and enabling lower BTV, by incorporating a sacrificial film with a low modulus of elasticity to maintain lower BTV, and by eliminating the need for a topside passivation, which requires stringent design rules. Further, the microelectronic structures and assemblies disclosed herein offer new flexibility to electronics designers and manufacturers, allowing them to select an architecture that achieves their device goals without excess cost or manufacturing complexity.

For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The drawings are not necessarily to scale. Although many of the drawings illustrate rectilinear structures with flat walls and right-angle corners, this is simply for ease of illustration, and actual devices made using these techniques will exhibit rounded corners, surface roughness, and other features.

The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. As used herein, a “package” and an “IC package” are synonymous, as are a “die” and an “IC die.” The terms “top” and “bottom” may be used herein to explain various features of the drawings, but these terms are simply for ease of discussion, and do not imply a desired or required orientation. As used herein, the term “insulating” means “electrically insulating,” unless otherwise specified. Throughout the specification, and in the claims, the term “coupled” means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.” Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

When used to describe a range of dimensions, the phrase “between X and V” represents a range that includes X and Y. For convenience, the phrase “FIG.2” may be used to refer to the collection of drawings ofFIGS.2A-2N. Although certain elements may be referred to in the singular herein, such elements may include multiple sub-elements. For example, “an insulating material” may include one or more insulating materials.

FIG.1is a side, cross-sectional view of an example microelectronic assembly, in accordance with various embodiments. The microelectronic assembly100may include a multi-layer die subassembly104having a first layer die114-1coupled by first solder interconnects130having a first solder material132and a second layer die114-2electrically coupled by second solder interconnects140having a second solder material136. As used herein, the term a “multi-layer die subassembly”104may refer to a composite die having two or more stacked dielectric layers with one or more dies in each layer, and conductive interconnects and/or conductive pathways connecting the one or more dies, including dies in non-adjacent layers. As used herein, the terms a “multi-layer die subassembly” and a “composite die” may be used interchangeably. As shown inFIG.1, the multi-layer die subassembly104may include a first redistribution layer (RDL)148-1, a passivation layer149, a first layer104-1having a die114-1with TSVs117and a conductive pillar152, a second layer104-2having a die114-2and a die114-3, and a second RDL148-2between the first and second layers104-1,104-2where the die114-1is electrically coupled to the second RDL148-2by first solder interconnects130and the dies114-2,114-3are electrically coupled to the second RDL148-2by second solder interconnects140. As used herein, the terms “second solder interconnects140” and “first-level interconnects (FLIs)” may be used interchangeably. The multi-layer die subassembly104may include a first surface170-1and an opposing second surface170-2. In particular, the die114-1may include a bottom surface (e.g., the surface facing towards the first surface170-1) with first conductive contacts122, and an opposing top surface (e.g., the surface facing towards the second surface170-2) with second conductive contacts124. In some embodiments, the first conductive contacts122and second conductive contacts124may be surrounded by (e.g., embedded in) a mold material123. The dies114-2,114-3may include conductive contacts122on the bottom surface of the die (e.g., the surface facing towards the first surface170-1). The first and second RDLs148-1,148-2may include conductive pathways (e.g., conductive vias194and conductive lines196) through a dielectric material. The vias194in the first and second RDLs148-1,148-2may have an inverted taper, in the sense that the vias194are formed having a larger width (e.g., y-direction or y-axis) at a bottom surface (e.g., a surface nearer the first surface170-1) and a smaller width at a top surface (e.g., at a surface nearer the second surface170-2). The first and second RDLs148-1,148-2may include first conductive contacts172on a bottom surface and second conductive contacts174on a top surface.

As used herein, a “conductive contact” may refer to a portion of conductive material (e.g., metal) serving as an electrical interface between different components (e.g., part of a conductive interconnect); conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket, or portion of a conductive line or via). In a general sense, an “interconnect” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides electrical connectivity between two electrical components, facilitating communication of electrical signals between them; an optical interconnect provides optical connectivity between two optical components, facilitating communication of optical signals between them. As used herein, both electrical interconnects and optical interconnects are comprised in the term “interconnect.” The nature of the interconnect being described is to be understood herein with reference to the signal medium associated therewith. Thus, when used with reference to an electronic device, such as an IC that operates using electrical signals, the term “interconnect” describes any element formed of an electrically conductive material for providing electrical connectivity to one or more elements associated with the IC or/and between various such elements. In such cases, the term “interconnect” may refer to both conductive traces (also sometimes referred to as “metal traces,” “lines,” “metal lines,” “wires,” “metal wires,” “trenches,” or “metal trenches”) and conductive vias (also sometimes referred to as “vias” or “metal vias”). Sometimes, electrically conductive traces and vias may be referred to as “conductive traces” and “conductive vias”, respectively, to highlight the fact that these elements include electrically conductive materials such as metals. Likewise, when used with reference to a device that operates on optical signals as well, such as a photonic IC (PIC), “interconnect” may also describe any element formed of a material that is optically conductive for providing optical connectivity to one or more elements associated with the PIC. In such cases, the term “interconnect” may refer to optical waveguides (e.g., structures that guide and confine light waves), including optical fiber, optical splitters, optical combiners, optical couplers, and optical vias.

Any of the conductive contacts disclosed herein (e.g., the conductive contacts122,124,146,172, and/or174) may include bond pads, solder bumps, conductive posts, or any other suitable conductive contact, for example. As shown inFIG.1, the die114-1is depicted as having conductive contacts124extending away from a surface of the die, and may be referred to herein as “a bumped die” or “a micro-bumped die.” The dies114-2, and114-3are depicted as having conductive contacts122flush with a surface of the die, and may be referred to herein as “a bumpless die.” The die114-1further includes a mold material123around the first and second conductive contacts122,124. In some embodiments, the die114-1may include a passivation layer (not shown), such as a material including silicon and nitrogen (e.g., in the form of silicon nitride), at the top and/or bottom surface of the die114-1between the die114-1and the mold material123. The die114may include other conductive pathways (e.g., including lines and vias) and/or to other circuitry (not shown) coupled to the respective conductive contacts (e.g., conductive contacts122,124) on the surface of the die114.

The first solder interconnects130may include conductive contacts124on the top surface of the die114-1, solder132, and conductive contacts172on the bottom surface of the second RDL148-1. The first solder interconnects130disclosed herein may take any suitable form. The first solder interconnects130may have a finer pitch than or a same pitch as the second solder interconnects140in a microelectronic assembly. The solder interconnects130may have a finer pitch than the die-to-package substrate (DTPS) interconnects150in a microelectronic assembly. As used herein, pitch is measured center-to-center (e.g., from a center of a conductive contact to a center of an adjacent conductive contact or from a center of a conductive pillar to a center of an adjacent conductive pillar). In some embodiments, the solder interconnects130may include small conductive bumps (e.g., copper bumps) attached to the conductive contacts124by solder132. In some embodiments, the solder interconnects130disclosed herein may have a pitch between 1 microns and-100 microns. In some embodiments, a diameter of the solder132is equal to approximately half a minimum pitch. The solder interconnects130may have too fine a pitch to couple to the package substrate102directly (e.g., too fine to serve as DTPS interconnects150). In some embodiments, the solder interconnects130may be used as data transfer lanes, while the DTPS interconnects150may be used for power and ground lines, among others. In some embodiments, the first solder interconnects130in a microelectronic assembly100may include a solder132that is a no remelt solder, a lower-temperature solder, or a conventional solder. As used herein, a “no remelt solder” includes solder with a melting point above 400 degrees Celsius. For example, a no remelt solder may include a copper and tin alloy paste where, during reflow, the tin alloy particles melt and react with the copper alloy particles to form an intermetallic compound (IMC), such as an IMC in the form of Cu3Sn. The no remelt solder interconnects may be formed at a lower temperature (e.g., a temperature of 241 degrees Celsius for the tin alloy particles to melt) and, once the no remelt solder interconnects are formed with the IMC, the melting point temperature of the no remelt solder increases to above 400 degrees Celsius. As used herein, a “lower-temperature” solder includes a solder with a melting point below 241 degrees Celsius. In some embodiments, a lower-temperature solder may include tin and bismuth (e.g., eutectic tin bismuth) or tin, silver, and bismuth. In some embodiments, a lower-temperature solder may include indium, indium and tin, or gallium. A “conventional solder” includes solder with a melting point equal to 241 degrees Celsius and may include tin.

The second solder interconnects140may include conductive contacts174on the top surface of the second RDL148-2, solder136, and conductive contacts122on the bottom surface of the die114-2or the die114-3. The second solder interconnects140disclosed herein may take any suitable form. The second solder interconnects140may have a coarser pitch than or a same pitch as the first solder interconnects130in a microelectronic assembly. The second solder interconnects140may have a finer pitch than the DTPS interconnects150in a microelectronic assembly. In some embodiments, the second solder interconnects140disclosed herein may have a pitch between 50 microns and 150 microns. In some embodiments, the second solder interconnects140in a microelectronic assembly100may be include a solder136that is a higher-temperature solder. A higher-temperature solder includes solder with a melting point above 241 degrees Celsius). In some embodiments, a higher-temperature solder material may include metal alloys, including tin alloys, for example, tin and copper; tin and gold; tin and silver; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, the second solder interconnects140may include a solder136that is a no remelt solder (e.g., solder with a melting point above 400 degrees Celsius).

The DTPS interconnects150disclosed herein may take any suitable form. In some embodiments, a set of DTPS interconnects150may include solder134(e.g., solder bumps or balls that are subject to a thermal reflow to form the DTPS interconnects150). For example, the DTPS interconnects150may include solder134that is a no remelt solder, a lower-temperature solder, or a conventional solder. In some embodiments, the second solder interconnects140in a microelectronic assembly100may be formed before the DTPS interconnects150are formed, such that the second solder interconnects140may use a higher-temperature solder (e.g., solder with a melting point above 241 degrees Celsius), while the DTPS interconnects150may use a no remelt solder (e.g., solder with a melting point above 400 degrees Celsius). In such cases, the second solder interconnects140may be surrounded by an underfill127-2to contain any remelting of higher-temperature solder when the DTPS interconnects150are formed. In some embodiments, the second solder interconnects140in a microelectronic assembly100may be formed after the DTPS interconnects150are formed, such that the second solder interconnects140may use a higher-temperature solder (e.g., solder with a melting point above 241 degrees Celsius), while the DTPS interconnects150may use a lower-temperature solder (e.g., solder with a melting point below 241 degrees Celsius). In such cases, the DTPS interconnects150may be surrounded by an underfill material127-3to contain any remelting of the low-temperature solder when the second solder interconnects140are formed under higher temperatures. The chemical composition of the solder132,134,136may be determined using any suitable technique, such as energy dispersive x-ray (EDX).

In some embodiments, a set of DTPS interconnects150may include an anisotropic conductive material, such as an anisotropic conductive film or an anisotropic conductive paste. An anisotropic conductive material may include conductive materials dispersed in a non-conductive material. In the microelectronic assemblies100disclosed herein, some or all of the DTPS interconnects150may have a larger pitch than some or all of the first solder interconnects130. First solder interconnects130and second solder interconnects140may have a smaller pitch than DTPS interconnects150due to the greater similarity of materials between the dies114and the first RDL148-1than between the first RDL148-1and the package substrate102on either side of a set of DTPS interconnects150. In particular, the differences in the material composition of the first RDL148-1and a package substrate102may result in differential expansion and contraction of the first RDL148-1and the package substrate102due to heat generated during operation (as well as the heat applied during various manufacturing operations). To mitigate damage caused by this differential expansion and contraction (e.g., cracking, solder bridging, etc.), the DTPS interconnects150may be formed larger and farther apart than the first solder interconnects130and second solder interconnects140, which may experience less thermal stress due to the greater material similarity of the dies114and the RDL148. In some embodiments, the DTPS interconnects150disclosed herein may have a pitch between 100 microns and 350 microns.

The die114-1in the first layer104-1may be coupled to the package substrate102by DTPS interconnects150through conductive pathways in the first RDL148-1and the passivation layer149, and may be coupled to the dies114-2,114-3in the second layer104-2by first solder interconnects130and second solder interconnects140through conductive pathways in the second RDL148-2. The dies114-2,114-3in the second layer104-2may be coupled to the package substrate102by second solder interconnects140and DTPS interconnects150through conductive pathways in the first RDL148-1, the second RDL148-2, and the passivation layer149, and the conductive pillars152to form multi-level (ML) interconnects. The ML interconnects may be power delivery interconnects or high speed signal interconnects. As used herein, the term “ML interconnect” may refer to an interconnect that includes a conductive pillar between a first component and a second component where the first component and the second component are not in adjacent layers, or may refer to an interconnect that spans one or more layers (e.g., an interconnect between a first die in a first layer and a second die in a third layer, or an interconnect between a package substrate and a die in a second layer). In particular, as shown inFIG.1, the DTPS interconnects150may include conductive contacts146on the top surface of the package substrate102, solder134, and conductive contacts172on a bottom surface of the first RDL148-1(e.g., at a bottom surface170-1of the multi-layer die subassembly104).

A microelectronic assembly100may include one or more RDLs148(e.g., a first RDL148-1and a second RDL148-2, as shown inFIG.1). An RDL148may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive pathways through the dielectric material (e.g., including conductive vias194and/or conductive traces196). The conductive pathways may electrically couple the first conductive contacts172and the second conductive contacts174on the RDL148. In some embodiments, the insulating material of the RDL148may be composed of dielectric materials, bismaleimide triazine (BT) resin, polyimide materials, epoxy materials (e.g., glass reinforced epoxy matrix materials, epoxy build-up films, or the like), mold materials, oxide-based materials (e.g., silicon dioxide or spin on oxide), or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics). AlthoughFIG.1shows two RDLs148-1,148-2, the multi-layer die subassembly104may include any suitable number of RDLs148, including one RDL148or more than two RDLs148. The microelectronic assembly100may further include one or more passivation layers149. A material of the passivation layer149may include any suitable material, for example, silicon and nitrogen (e.g., in the form of silicon nitride), silicon, oxygen, and nitrogen (e.g., in the form of silicon oxynitride); silicon and oxygen (e.g., in the form of silicon oxide); tantalum and nitrogen (e.g., in the form of tantalum nitride); aluminum and oxygen (e.g., in the form of aluminum oxide); yttrium and oxygen (e.g., in the form of yttrium oxide); titanium and oxygen (e.g., in the form of titanium oxide); and hafnium and oxygen (e.g., in the form of hafnium oxide). In some embodiments, the passivation layer149may be omitted.

The conductive pillars152may be formed of any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys, for example. The conductive pillars152may be formed using any suitable process, including, for example, a lithographic process or an additive process, such as cold spray or 3-dimensional printing. In some embodiments, the conductive pillars152disclosed herein may have a pitch between 75 microns and 200 microns. As used herein, pitch is measured center-to-center (e.g., from a center of a conductive pillar to a center of an adjacent conductive pillar). The conductive pillars152may have any suitable size and shape. In some embodiments, the conductive pillars152may have a circular, rectangular, or other shaped cross-section. The conductive pillars152may be electrically coupled to the first and/or second RDL148-1,148-2by non-solder interconnects, for example, metal-to-metal interconnects, as shown inFIG.1.

The die114disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and multiple conductive pathways formed through the insulating material. In some embodiments, the insulating material of a die114may include a dielectric material, such as silicon dioxide, silicon nitride, oxynitride, polyimide materials, glass reinforced epoxy matrix materials, or a low-k or ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymeric dielectrics, photo-imageable dielectrics, and/or benzocyclobutene-based polymers). In some embodiments, the insulating material of a die114may include a semiconductor material, such as silicon, germanium, or a III-V material (e.g., gallium nitride), and one or more additional materials. For example, an insulating material may include silicon oxide or silicon nitride. The conductive pathways in a die114may include conductive traces and/or conductive vias, and may connect any of the conductive contacts in the die114in any suitable manner (e.g., connecting multiple conductive contacts on a same surface or on different surfaces of the die114). Example structures that may be included in the dies114disclosed herein are discussed below with reference toFIG.5. The conductive pathways in the dies114may be bordered by liner materials, such as adhesion liners and/or barrier liners, as suitable. In some embodiments, the die114is a wafer. In some embodiments, the die114is a monolithic silicon, a fan-out or fan-in package die, or a die stack (e.g., wafer stacked, die stacked, or multi-layer die stacked).

In some embodiments, the die114may include conductive pathways to route power, ground, and/or signals to/from other dies114included in the microelectronic assembly100. For example, the die114-1may include TSVs (not shown), including a conductive material via, such as a metal via, isolated from the surrounding silicon or other semiconductor material by a barrier oxide), or other conductive pathways through which power, ground, and/or signals may be transmitted between the package substrate102and one or more dies114“on top” of the die114-1(e.g., in the embodiment ofFIG.1, the dies114-2and/or114-3). In some embodiments, the die114-1may not route power and/or ground to the dies114-2and114-3; instead, the dies114-2,114-3may couple directly to power and/or ground lines in the package substrate102by ML interconnects (e.g., via conductive pillars152). In some embodiments, the die114-1in the first layer104-1, also referred to herein as “base die,” “interposer die,” or bridge die,” may be thicker than the dies114-2,114-3in the second layer104-2. In some embodiments, a die114may span multiple layers of the multi-layer die subassembly104. In some embodiments, the die114-1may be a memory device (e.g., as described below with reference to the die1502ofFIG.4), a high frequency serializer and deserializer (SerDes), such as a Peripheral Component Interconnect (PCI) express. In some embodiments, the die114-1may be a processor die, a radio frequency chip, a power converter, a network processor, a workload accelerator, a security encryptor, or a passive/active bridge die to provide high Bandwidth Die-to-Die interconnections between the die114-2and114-3at low power. In some embodiments, the die114-2and/or the die114-3may be a processor die.

The multi-layer die subassembly104may include an insulating material133(e.g., a dielectric material formed in multiple layers, as known in the art) to form the multiple layers and to embed one or more dies in a layer. In particular, the die114-1and conductive pillars152may be embedded in the insulating material133-1in the first layer104-1and the second and third dies114-2,114-3may be embedded in the insulating material133-2in the second layer104-2. In some embodiments, the insulating material133of the multi-layer die subassembly104may be a dielectric material, such as an organic dielectric material, a fire retardant grade4material (FR-4), bismaleimide triazine (BT) resin, polyimide materials, glass reinforced epoxy matrix materials, or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics). In some embodiments, the die114may be embedded in an inhomogeneous dielectric, such as stacked dielectric layers (e.g., alternating layers of different inorganic dielectrics). In some embodiments, the insulating material133of the multi-layer die subassembly104may be a mold material, such as an organic polymer with inorganic silica particles. In some embodiments, the insulating materials133-1and133-2are a same insulating material. In some embodiments, the insulating material133-1is different than the insulating material133-2. The multi-layer die subassembly104may include one or more ML interconnects through the dielectric material (e.g., including conductive vias and/or conductive pillars, as shown). The multi-layer die subassembly104may have any suitable dimensions. For example, in some embodiments, a thickness of the multi-layer die subassembly104may be between 100 um and 2000 um. In some embodiments, the multi-layer die subassembly104may include a composite die, such as stacked dies. The multi-layer die subassembly104may have any suitable number of layers, any suitable number of dies, and any suitable die arrangement. For example, in some embodiments, the multi-layer die subassembly104may have between 3 and 20 layers of dies. In some embodiments, the multi-layer die subassembly104may include a layer having between 2 and 50 dies.

The package substrate102may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive pathways to route power, ground, and signals through the dielectric material (e.g., including conductive traces and/or conductive vias, as shown). In some embodiments, the insulating material of the package substrate102may be a dielectric material, such as an organic dielectric material, a fire retardant grade4material (FR-4), BT resin, polyimide materials, glass reinforced epoxy matrix materials, organic dielectrics with inorganic fillers or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics). In particular, when the package substrate102is formed using standard printed circuit board (PCB) processes, the package substrate102may include FR-4, and the conductive pathways in the package substrate102may be formed by patterned sheets of copper separated by build-up layers of the FR-4. The conductive pathways in the package substrate102may be bordered by liner materials, such as adhesion liners and/or barrier liners, as suitable. In some embodiments, the package substrate102may be formed using a lithographically defined via packaging process. In some embodiments, the package substrate102may be manufactured using standard organic package manufacturing processes, and thus the package substrate102may take the form of an organic package. In some embodiments, the package substrate102may be a set of redistribution layers formed on a panel carrier by laminating or spinning on a dielectric material, and creating conductive vias and lines by laser drilling and plating. In some embodiments, the package substrate102may be formed on a removable carrier using any suitable technique, such as a redistribution layer technique. Any method known in the art for fabrication of the package substrate102may be used, and for the sake of brevity, such methods will not be discussed in further detail herein.

In some embodiments, the package substrate102may be a lower density medium and the die114may be a higher density medium or have an area with a higher density medium. As used herein, the term “lower density” and “higher density” are relative terms indicating that the conductive pathways (e.g., including conductive interconnects, conductive lines, and conductive vias) in a lower density medium are larger and/or have a greater pitch than the conductive pathways in a higher density medium. In some embodiments, a higher density medium may be manufactured using a modified semi-additive process or a semi-additive build-up process with advanced lithography (with small vertical interconnect features formed by advanced laser or lithography processes), while a lower density medium may be a PCB manufactured using a standard PCB process (e.g., a standard subtractive process using etch chemistry to remove areas of unwanted copper, and with coarse vertical interconnect features formed by a standard laser process). In other embodiments, the higher density medium may be manufactured using semiconductor fabrication process, such as a single damascene process or a dual damascene process. In some embodiments, additional dies may be disposed on the top surface of the dies114-2,114-3. In some embodiments, additional components may be disposed on the top surface of the dies114-2,114-3. Additional passive components, such as surface-mount resistors, capacitors, and/or inductors, may be disposed on the top surface or the bottom surface of the package substrate102, or embedded in the package substrate102.

The microelectronic assembly100ofFIG.1may also include an underfill material127. For example, microelectronic assembly100may include the underfill material127-1that extends around the first solder interconnects130, may include the underfill material127-1that extends around the second solder interconnects140, and may include the underfill material127-3that extends between the multi-layer die subassembly104and the package substrate102around the associated DTPS interconnects150. The underfill material127may be an insulating material, such as an appropriate epoxy material. In some embodiments, the underfill material127may include a capillary underfill, non-conductive film (NCF), or molded underfill. In some embodiments, the underfill material127-1may include an epoxy flux that assists with soldering the die114-1to the second RDL148-2when forming the first solder interconnects130, and then polymerizes and encapsulates the first solder interconnects130. In some embodiments, the underfill material127-2may include an epoxy flux that assists with soldering the dies114-2and/or114-3to the second RDL148-2when forming the second solder interconnects140, and then polymerizes and encapsulates the second solder interconnects140. In some embodiments, the underfill material127-3may include an epoxy flux that assists with soldering the multi-layer die subassembly104to the package substrate102when forming the DTPS interconnects150, and then polymerizes and encapsulates the DTPS interconnects150. The underfill material127-1and/or127-2may be selected to have a coefficient of thermal expansion (CTE) that may mitigate or minimize the stress between the dies114and the RDL148arising from uneven thermal expansion in the microelectronic assembly100. The underfill material127-3may be selected to have a coefficient of thermal expansion (CTE) that may mitigate or minimize the stress between the RDL148and the package substrate102arising from uneven thermal expansion in the microelectronic assembly100. In some embodiments, the CTE of the underfill material127may have a value that is intermediate to the CTE of the package substrate102(e.g., the CTE of the dielectric material of the package substrate102) and a CTE of the dies114and/or insulating material133of the multi-layer die subassembly104.

The microelectronic assembly100ofFIG.1may also include a circuit board (not shown). The package substrate102may be coupled to the circuit board by second-level interconnects at the bottom surface of the package substrate102. The second-level interconnects may be any suitable second-level interconnects, including solder balls for a ball grid array arrangement, pins in a pin grid array arrangement or lands in a land grid array arrangement. The circuit board may be a motherboard, for example, and may have other components attached to it. The circuit board may include conductive pathways and other conductive contacts for routing power, ground, and signals through the circuit board, as known in the art. In some embodiments, the second-level interconnects may not couple the package substrate102to a circuit board, but may instead couple the package substrate102to another IC package, an interposer, or any other suitable component. In some embodiments, the multi-layer die subassembly104may not be coupled to a package substrate102, but may instead be coupled to a circuit board, such as a PCB.

AlthoughFIG.1depicts a multi-layer die subassembly104having a particular number of dies114coupled to the package substrate102and to other dies114, this number and arrangement are simply illustrative, and a multi-layer die subassembly104may include any desired number and arrangement of dies114coupled to a package substrate102. AlthoughFIG.1shows the die114-1as a double-sided die and the dies114-2,114-3as single-sided dies, the dies114may be a single-sided or a double-sided die and may be a single-pitch die or a mixed-pitch die. In some embodiments, additional components may be disposed on the top surface of the dies114-2and/or114-3. In this context, a double-sided die refers to a die that has connections on both surfaces. In some embodiments, a double-sided die may include TSVs (e.g., the TSVs117in die114-1) to form connections on both surfaces. The active surface of a double-sided die, which is the surface containing one or more active devices and a majority of interconnects, may face either direction depending on the design and electrical requirements.

Many of the elements of the microelectronic assembly100ofFIG.1are included in other ones of the accompanying drawings; the discussion of these elements is not repeated when discussing these drawings, and any of these elements may take any of the forms disclosed herein. Further, a number of elements are illustrated inFIG.1as included in the microelectronic assembly100, but a number of these elements may not be present in a microelectronic assembly100. For example, in various embodiments, the underfill material127-2and/or127-3, and the package substrate102may not be included. In some embodiments, individual ones of the microelectronic assemblies100disclosed herein may serve as a system-in-package (SiP) in which multiple dies114having different functionality are included. In such embodiments, the microelectronic assembly100may be referred to as an SiP.

Any suitable techniques may be used to manufacture the microelectronic assemblies100disclosed herein. For example,FIGS.2A-2Nare side, cross-sectional views of various stages in an example process for manufacturing the microelectronic assembly100ofFIG.1, in accordance with various embodiments.FIGS.2A-2Ndescribe an example process where the second solder interconnects140and the second RDL148-2are formed first and then the die114-1is coupled to form the first solder interconnects130, which enables more precise solder bump formation. Although the operations discussed below with reference toFIGS.2A-2N(and others of the accompanying drawings representing manufacturing processes) are illustrated in a particular order, these operations may be performed in any suitable order. Further, additional operations which are not illustrated may also be performed without departing from the scope of the present disclosure. Also, various ones of the operations discussed herein with respect toFIGS.2A-2Nmay be modified in accordance with the present disclosure to fabricate others of microelectronic assembly100disclosed herein.

FIG.2Aillustrates an assembly subsequent to patterning solder136and second conductive contact174for second solder interconnects140(e.g., first-level interconnects) on a first carrier105-1. A carrier105may include any suitable material for providing mechanical stability during manufacturing operations to achieve a tight relative solder bump variation (e.g., a small rBTV) required for top die attachment (e.g., dies114-2,114-3). As the bump pitch decreases, the rBTV requirements become more stringent. In an example where the second solder interconnects140have a bump pitch of 18 microns a solder bump coplanarity value may be equal to 1.5 microns. In some embodiments, a carrier105may include glass (e.g., a glass panel) or an other low TTV material. In some embodiments, a carrier105may be sized to form a quarter panel. A solder136may include any suitable higher-temperature solder material, as described above with reference toFIG.1. A second conductive contact174may include any suitable conductive material, such as nickel and/or copper, and may be formed using any suitable technique, including semi-additive plating.

FIG.2Billustrates an assembly subsequent to providing a removable protective material142around the solder136and the second conductive contacts174. A removable protective material142may include any suitable material, for example, a dry film resist, a thermal decomposable polymer, or a dielectric material susceptible to etching. The removable protective material142may be formed using any suitable process including lamination, or spray coating or slit coating and curing. In some embodiments, the removable protective material142may be initially deposited on and over the top surface of the conductive contacts174, then polished back to expose the top surface of the conductive contacts174, and planarize the surface to reduce TTV. The removable protective material142may be removed using any suitable technique, including grinding, or etching, such as a wet etch, a dry etch (e.g., a plasma etch), a wet blast, or a laser ablation (e.g., using excimer laser). In some embodiments, the thickness of the removable protective material142may be minimized to reduce the etching time required. In some embodiments, the top surface of the removable protective material142may be planarized using any suitable process, such as chemical mechanical polishing (CMP).

FIG.2Cillustrates an assembly subsequent to forming a second RDL148-2on a top surface of the assembly ofFIG.2B. The second RDL148-2may be patterned in reverse order as the assembly will be inverted such that the second RDL148-2will be towards a top surface (e.g., nearer to the second surface170-2, as shown inFIG.1). The second RDL148-2may include conductive pathways (e.g., conductive lines196and vias194) between first conductive contacts172and second conductive contacts174. The second RDL148-2may be manufactured using any suitable technique, such as a PCB technique or a redistribution layer technique. The conductive vias194may be formed having a taper, such that the conductive vias194have a smaller width at the bottom (e.g., towards a first surface270-1) and a greater width at the top (e.g., towards a second surface270-2). In some embodiments, the conductive vias194in the second RDL148-2may be formed using a lithographic process (e.g., by patterning vias, laminating a dielectric, and planarizing), a photo-imageable dielectric (PID) process (e.g., by laminating a PID, exposing the PID to form via openings, and providing a conductive material in the openings to form the conductive vias), or a laser drilling process (e.g., by forming via openings in a dielectric material and providing a conductive material in the openings to form the conductive vias).

FIG.2Dillustrates an assembly subsequent to depositing solder132on the first conductive contacts172(e.g., for forming first solder interconnects130). The solder132may include a material that is a no remelt solder, a lower-temperature solder, or a conventional solder, as described above with reference toFIG.1.

FIG.2Eillustrates an assembly subsequent to placing a die114-1on a top surface of the assembly ofFIG.2D, forming first solder interconnects130between the die114-1and the first conductive contacts172on the second RDL148-2, and dispensing an underfill127-1around the first solder interconnects130. Any suitable method may be used to place the die114-1, for example, automated pick-and-place. The die114-1may include first conductive contacts122and second conductive contacts124surrounded by a mold material123which may be formed on the die114-1prior to placing the die114-1on the assembly. The die114-1may further include TSVs117. The assembly ofFIG.2Emay be subjected to a solder reflow process during which solder132of the first solder interconnects130melt and bond to mechanically and electrically couple the die114-1to the second RDL148-2. The underfill material127-1may be formed of any suitable material and may be dispensed using any suitable technique, as described above with reference toFIG.1. As shown inFIG.2E, a die attach film (DAF) between the die114-1and the second RDL148-2is omitted as the die114-1is soldered via solder132to the second RDL148-2.

FIG.2Fillustrates an assembly subsequent to depositing a conductive material, such as copper, on a top surface of the assembly ofFIG.2Eto generate conductive pillars152. The conductive pillars152may be formed on and electrically coupled to the first conductive contacts172on the second RDL148-2. The conductive pillars152may be formed using any suitable technique, for example, a lithographic process or an additive process, such as cold spray or 3-dimensional printing. The conductive pillars152may have any suitable dimensions. In some embodiments, the conductive pillars152may span one or more layers. For example, in some embodiments, an individual conductive pillar152may have an aspect ratio (height:diameter) between 1:1 and 4:1 (e.g., between 1:1 and 3:1). In some embodiments, an individual conductive pillar152may have a diameter (e.g., cross-section) between 10 microns and 150 microns. For example, an individual conductive pillar152may have a diameter between 50 microns and 100 microns. In some embodiments, an individual conductive pillar152may have a height (e.g., z-height or thickness) between 50 and 150 microns. The conductive pillars152may have any suitable cross-sectional shape, for example, square, triangular, and oval, among others.

FIG.2Gillustrates an assembly subsequent to depositing an insulating material133-1on and around the die114-1and the conductive pillars152and planarizing the top surface of the assembly to form the first layer104-1. The insulating material133-1may be a mold material, such as an organic polymer with inorganic silica particles, an epoxy material, or a silicon and nitrogen material (e.g., in the form of silicon nitride). In some embodiments, the insulating material133-1is a dielectric material. In some embodiments, the dielectric material may include an organic dielectric material, a fire retardant grade4material (FR-4), BT resin, polyimide materials, glass reinforced epoxy matrix materials, or low-k and ultra low-k dielectric (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymeric dielectrics). The insulating material133-1may be formed using any suitable process, including lamination, or slit coating and curing. In some embodiments, the insulating material133-1may be dispensed in liquid form to flow around and conform to various shapes of components and metallization, and, subsequently, may be subjected to a process, for example, curing, that solidifies the insulating material133-1. In some embodiments, the insulating material133-1may be initially deposited on and over the top surface of the die114-1, then polished back to expose the top surface of the conductive contacts122on the die114-1. The insulating material133-1may be removed using any suitable technique, including grinding, or etching, such as a wet etch, a dry etch (e.g., a plasma etch), a wet blast, or a laser ablation (e.g., using excimer laser). In some embodiments, the thickness of the insulating material133-1may be minimized to reduce the etching time required. In some embodiments, the top surface of the insulating material133-1may be planarized using any suitable process, such as chemical mechanical polishing (CMP).

FIG.2Hillustrates an assembly subsequent to forming a passivation layer149and an RDL148(e.g., the first RDL148-1, as shown inFIG.1) on a top surface of the assembly ofFIG.2G. The passivation layer149may include conductive pathways (e.g., conductive lines196and conductive vias194). The first RDL148-1may include conductive pathways (e.g., conductive lines196and conductive vias194) between first conductive contacts172and second conductive contacts174on the first RDL148-1. The passivation layer149may be manufactured using any suitable technique, such as plasma chemical vapor deposition (PCVD) or ebeam evaporation, or sputtering. The first RDL148-1may be manufactured using any suitable technique, such as a PCB technique or a redistribution layer technique, as described above with reference toFIG.2C. The conductive vias194may be formed having a taper, such that the conductive vias194have a smaller width at the bottom (e.g., towards a first surface270-1) and a greater width at the top (e.g., towards a second surface270-2). In some embodiments, the passivation layer149and/or the first RDL148-1may be omitted.

FIG.2Iillustrates an assembly subsequent to depositing solder134on the first conductive contacts172of the first RDL148-1(e.g., for forming DTPS solder interconnects150). The solder134may include a solder material that is a no remelt solder, a lower-temperature solder, or a conventional solder, as described above with reference toFIG.1. In embodiments where the first RDL148-1and/or the passivation layer149are omitted, the solder134may be deposited on conductive contacts (not shown) on a top surface (e.g., towards the second surface270-2) of the insulating material133-1of the first layer104-1.

FIG.2J-1illustrates an assembly where the second solder interconnects140are formed prior to the DTPS interconnects150.FIG.2J-1illustrates an assembly subsequent to providing a sacrificial material143around the solder134and the first conductive contacts172on the first RDL148-1, and attaching a second carrier105-2to a top surface270-2of the assembly. A sacrificial material143may include any suitable material, for example, titanium (e.g., as an etch stop layer) and copper, a laser release material, a negative coefficient of thermal expansion (CTE) material, a dry film resist, a thermal decomposable polymer, a dielectric material susceptible to etching, or a combination thereof. The removable protective material142may be formed using any suitable process including lamination, or slit coating and curing. The second carrier105-2may include any suitable carrier105, as described above with reference toFIG.2A, and may include a carrier105having a greater thickness than a first carrier105-1or an other such carrier configured to reduce warpage on the removal of the first carrier105-1.

FIG.2J-2illustrates an alternate assembly toFIG.2J-1, where the DTPS interconnects150are formed prior to the second solder interconnects140.FIG.2J-2illustrates an assembly subsequent to attaching a package substrate102to the top surface270-2of the assembly ofFIG.2I, forming DTPS solder interconnects150, and dispensing an underfill127-3around the DTPS interconnects150. The DTPS interconnects150may include the conductive contacts146on the package substrate102, the solder134, and the the first conductive contacts172on the first RDL148-1. The assembly ofFIG.2J-2may be subjected to a solder reflow process during which solder134of the DTPS interconnects150melt and bond to mechanically and electrically couple the package substrate102to the top surface270-2of the assembly ofFIG.2I. The underfill material127-3may be formed of any suitable material and may be dispensed using any suitable technique, as described above with reference toFIG.1. Further operations may be performed on the assembly ofFIG.2J-2, as described below with reference toFIGS.2K-2M, where the package substrate102may function as the second carrier105-2.

FIG.2Killustrates an assembly subsequent to inverting the assembly ofFIG.2J-1and removing the first carrier105-1. If multiple assemblies are manufactured together, the assemblies may be singulated after removal of the first carrier105-1(e.g., singulated into four quarter panels).

FIG.2Lillustrates an assembly subsequent to removing the removable protective material142. The removable protective material142may be removed using any suitable technique. For example, in some embodiments, the removable protective material142may be removed using dimethyl sulfoxide in a wet strip process, an acidic copper etch process, or an ammoniacal copper etch process.

FIG.2Millustrates an assembly subsequent to placing dies114-2,114-3on a top surface of the assembly ofFIG.2K, forming second solder interconnects140between the dies114-2,114-3and the second conductive contacts174on the second RDL148-2, and depositing an insulating material133-2on and around the dies114-2,114-3to form the second layer104-2. Any suitable method may be used to place the dies114-2,114-3, for example, automated pick-and-place. The dies114-2,114-3may include first conductive contacts122on a bottom surface. The assembly ofFIG.2Mmay be subjected to a solder reflow process during which solder136of the solder interconnects140melt and bond to mechanically and electrically couple the dies114-2,114-3to the second RDL148-2. The solder136may include any suitable material, including a higher-temperature solder, as described above with reference toFIG.1. The insulating material133-2may include any suitable material and may be formed and removed using any suitable process, including as described above with reference toFIG.2G. In some embodiments, the insulating material133-1in the first layer104-1(e.g., deposited inFIG.2G) is different material than the insulating material133-2in the second layer104-2(e.g., deposited inFIG.2M). In some embodiments, the insulating material133-1in the first layer104-1(e.g., deposited inFIG.2G) is a same material as the insulating material133-2in the second layer104-2(e.g., deposited inFIG.2M). In some embodiments, underfill127-2may be dispensed around the second solder interconnects140prior to depositing the insulating material133-2. In some embodiments, underfill127-2around the second solder interconnects140may be omitted. In some embodiments, the insulating material133-2may be initially deposited on and over the top surface of the dies114-2,114-3, then polished back to expose the top surface of the dies114-2,114-3. If the insulating material133-2is formed to completely cover the dies114-2,114-3, the insulating material133-2may be removed using any suitable technique, including grinding, or etching, such as a wet etch, a dry etch (e.g., a plasma etch), a wet blast, or a laser ablation (e.g., using excimer laser). In some embodiments, the thickness of the insulating material133-2may be minimized to reduce the etching time required. In some embodiments, the top surface of the insulating material133-2may be planarized using any suitable process, such as CMP.

FIG.2Nillustrates an assembly subsequent to removing the second carrier105-2and removing the sacrificial material143. The sacrificial material143may be removed using any suitable technique. For example, in some embodiments, the sacrificial material143may be removed using dimethyl sulfoxide in a wet strip process or an alkaline copper etch process. In some embodiments, when an etch stop is used, the sacrificial material143may be removed using a dry etch process. In some embodiments, when a thermal decomposable polymer material is used, the sacrificial material143may be removed using heat. In some embodiments, when a laser release material is used, the sacrificial material143may be removed using light. The assembly ofFIG.2Nmay itself be a microelectronic assembly100, as shown. Further manufacturing operations may be performed on the microelectronic assembly100ofFIG.2Nto form other microelectronic assembly100; for example, the solder134may be used to couple the microelectronic assembly100ofFIG.2Nto a package substrate102by DTPS interconnects150, similar to the microelectronic assembly100ofFIG.1.

FIG.3is a flow diagram of an example method of fabricating an example microelectronic assembly, in accordance with various embodiments. At302, higher-temperature solder136and conductive contacts (e.g., conductive contacts174on a second RDL148-2) for second solder interconnects140are patterned on a first carrier105-1. The higher-temperature solder136and conductive contacts174are encapsulated with a removable protective material142and a top surface of the removable protective material142is planarized.

At304, an RDL148(e.g., the second RDL148-2ofFIG.1) is formed on a top surface of the removable protective material142and electrically coupled to the conductive contacts174and the higher-temperature solder136. The RDL148may be formed in reverse order (e.g., formed upside down) as the assembly may be subsequently inverted (e.g., oriented with the higher-temperature solder136at a top surface of the microelectronic assembly100, as shown inFIG.1).

At306, a solder132is deposited on conductive contacts172at a top surface of the RDL148for forming first solder interconnects130. The solder132may include a no remelt, a lower-temperature solder, or a conventional solder.

At308, a first layer die114-1is attached to a top surface of the RDL148and electrically coupled to the RDL148by first solder interconnects130. An underfill material127-1may be deposited around the first solder interconnects130. The underfill process may include dispensing underfill material in liquid form, allowing the material to flow and fill interstitial gaps around the first solder interconnects130, and subjecting the assembly to a curing process, such as baking, to solidify the material. The first layer die114-1may be placed and electrically coupled to the RDL148by first solder interconnects130without using a DAF or other adhesive material.

At310, conductive pillars152are formed on a top surface of the RDL148and electrically coupled to conductive contacts172on the RDL148. After forming the conductive pillars152, an insulating material133-1is disposed on and around the first layer die114-1and conductive pillars152using any suitable method such that the insulating material133-1encapsulates the first layer die114-1and the conductive pillars152. A top surface of the insulating material133-1may be planarized using CMP or any other suitable process. A grinding (also called grind back) process may substantially planarize and/or smooth a top surface of the assembly.

At312, an other RDL148(e.g., the first RDL148-1ofFIG.1) is formed on a top surface of the insulating material133-1and electrically coupled to the first layer die114-1and conductive pillars152. The other RDL148may be formed in reverse order (e.g., formed upside down) as the assembly may be subsequently inverted (e.g., oriented with the higher-temperature solder136at a top surface of the microelectronic assembly100, as shown inFIG.1).

At314, a solder134is deposited on conductive contacts172at a top surface of the other RDL148for forming DTPS interconnects150. The solder134may include a no remelt, a lower-temperature solder, or a conventional solder. In an embodiment where the second solder interconnects140are formed prior to the DTPS interconnects150, the solder134is encapsulated with a sacrificial material143, a second carrier105-2is attached to a top surface of the sacrificial material143, the assembly is inverted, and the first carrier105-1is removed. In an embodiment where the DTPS interconnects150are formed prior to the second solder interconnects140, a package substrate102may be attached and DTPS interconnects150may be formed. An underfill material127-3may be deposited around the DTPS interconnects150. The underfill process may include dispensing underfill material in liquid form, allowing the material to flow and fill interstitial gaps around the DTPS interconnects150, and subjecting the assembly to a curing process, such as baking, to solidify the material.

At316, the removable protective material142is removed and a second layer die114-2and/or114-3is attached and electrically coupled to the solder136(e.g., at a top surface of the assembly after being inverted) to form second solder interconnects140. An underfill material127-2may be deposited around the second solder interconnects140. The underfill process may include dispensing underfill material in liquid form, allowing the material to flow and fill interstitial gaps around the second solder interconnects140, and subjecting the assembly to a curing process, such as baking, to solidify the material. The second layer dies114-2,114-3may be encapsulated with an insulating material133-2and planarized using CMP or any other suitable process.

At318, if used, the second carrier105-2and the sacrificial material143is removed to expose the solder134. Further operations may be performed, such as attaching and electrically coupling a package substrate102to the solder134to form DTPS interconnects150.

The microelectronic assemblies100disclosed herein may be used for any suitable application. For example, in some embodiments, a microelectronic assembly100may be used to enable very small form factor voltage regulation for field programmable gate array (FPGA) or processing units (e.g., a central processing unit, a graphics processing unit, a FPGA, a modem, an applications processor, etc.) especially in mobile devices and small form factor devices. In another example, the die114in a microelectronic assembly100may be a processing device (e.g., a central processing unit, a graphics processing unit, a FPGA, a modem, an applications processor, a server processor, etc.).

The microelectronic assemblies100disclosed herein may be included in any suitable electronic component.FIGS.4-7illustrate various examples of apparatuses that may include, or be included in, any of the microelectronic assemblies100disclosed herein.

FIG.4is a top view of a wafer1500and dies1502that may be included in any of the microelectronic assemblies100disclosed herein (e.g., as any suitable ones of the dies114). The wafer1500may be composed of semiconductor material and may include one or more dies1502having IC structures formed on a surface of the wafer1500. Each of the dies1502may be a repeating unit of a semiconductor product that includes any suitable IC. After the fabrication of the semiconductor product is complete, the wafer1500may undergo a singulation process in which the dies1502are separated from one another to provide discrete “chips” of the semiconductor product. The die1502may be any of the dies114disclosed herein. The die1502may include one or more transistors (e.g., some of the transistors1640ofFIG.5, discussed below), supporting circuitry to route electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and/or any other IC components. In some embodiments, the wafer1500or the die1502may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die1502. For example, a memory array formed by multiple memory devices may be formed on a same die1502as a processing device (e.g., the processing device1802ofFIG.7) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array. In some embodiments, a die1502(e.g., a die114) may be a central processing unit, a radio frequency chip, a power converter, or a network processor. Various ones of the microelectronic assemblies100disclosed herein may be manufactured using a die-to-wafer assembly technique in which some dies114are attached to a wafer1500that include others of the dies114, and the wafer1500is subsequently singulated.

FIG.5is a cross-sectional side view of an IC device1600that may be included in any of the microelectronic assemblies100disclosed herein (e.g., in any of the dies114). One or more of the IC devices1600may be included in one or more dies1502(FIG.4). The IC device1600may be formed on a die substrate1602(e.g., the wafer1500ofFIG.4) and may be included in a die (e.g., the die1502ofFIG.4). The die substrate1602may be a semiconductor substrate composed of semiconductor material systems including, for example, n-type or p-type materials systems (or a combination of both). The die substrate1602may include, for example, a crystalline substrate formed using a bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate1602may be formed using alternative materials, which may or may not be combined with silicon, that include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Further materials classified as group II-VI, III-V, or IV may also be used to form the die substrate1602. Although a few examples of materials from which the die substrate1602may be formed are described here, any material that may serve as a foundation for an IC device1600may be used. The die substrate1602may be part of a singulated die (e.g., the dies1502ofFIG.4) or a wafer (e.g., the wafer1500ofFIG.4).

The IC device1600may include one or more device layers1604disposed on the die substrate1602. The device layer1604may include features of one or more transistors1640(e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate1602. The device layer1604may include, for example, one or more source and/or drain (S/D) regions1620, a gate1622to control current flow in the transistors1640between the S/D regions1620, and one or more S/D contacts1624to route electrical signals to/from the S/D regions1620. The transistors1640may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors1640are not limited to the type and configuration depicted inFIG.5and may include a wide variety of other types and configurations such as, for example, planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate transistors or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon and nanowire transistors.

The S/D regions1620may be formed within the die substrate1602adjacent to the gate1622of each transistor1640. The S/D regions1620may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate1602to form the S/D regions1620. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate1602may follow the ion-implantation process. In the latter process, the die substrate1602may first be etched to form recesses at the locations of the S/D regions1620. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions1620. In some implementations, the S/D regions1620may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions1620may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions1620.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors1640) of the device layer1604through one or more interconnect layers disposed on the device layer1604(illustrated inFIG.5as interconnect layers1606-1610). For example, electrically conductive features of the device layer1604(e.g., the gate1622and the S/D contacts1624) may be electrically coupled with the interconnect structures1628of the interconnect layers1606-1610. The one or more interconnect layers1606-1610may form a metallization stack (also referred to as an “ILD stack”)1619of the IC device1600.

The interconnect structures1628may be arranged within the interconnect layers1606-1610to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures1628depicted inFIG.5. Although a particular number of interconnect layers1606-1610is depicted inFIG.5, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than depicted.

In some embodiments, the interconnect structures1628may include lines1628aand/or vias1628bfilled with an electrically conductive material such as a metal. The lines1628amay be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate1602upon which the device layer1604is formed. For example, the lines1628amay route electrical signals in a direction in and out of the page from the perspective ofFIG.5. The vias1628bmay be arranged to route electrical signals in a direction of a plane that is substantially perpendicular to the surface of the die substrate1602upon which the device layer1604is formed. In some embodiments, the vias1628bmay electrically couple lines1628aof different interconnect layers1606-1610together.

The interconnect layers1606-1610may include a dielectric material1626disposed between the interconnect structures1628, as shown inFIG.5. In some embodiments, the dielectric material1626disposed between the interconnect structures1628in different ones of the interconnect layers1606-1610may have different compositions; in other embodiments, the composition of the dielectric material1626between different interconnect layers1606-1610may be the same.

A first interconnect layer1606(referred to as Metal 1 or “M1”) may be formed directly on the device layer1604. In some embodiments, the first interconnect layer1606may include lines1628aand/or vias1628b, as shown. The lines1628aof the first interconnect layer1606may be coupled with contacts (e.g., the S/D contacts1624) of the device layer1604.

A second interconnect layer1608(referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer1606. In some embodiments, the second interconnect layer1608may include vias1628bto couple the lines1628aof the second interconnect layer1608with the lines1628aof the first interconnect layer1606. Although the lines1628aand the vias1628bare structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer1608) for the sake of clarity, the lines1628aand the vias1628bmay be structurally and/or materially contiguous (e.g., simultaneously filled during a dual damascene process) in some embodiments.

A third interconnect layer1610(referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer1608according to similar techniques and configurations described in connection with the second interconnect layer1608or the first interconnect layer1606. In some embodiments, the interconnect layers that are “higher up” in the metallization stack1619in the IC device1600(i.e., farther away from the device layer1604) may be thicker.

The IC device1600may include a solder resist material1634(e.g., polyimide or similar material) and one or more conductive contacts1636formed on the interconnect layers1606-1610. InFIG.5, the conductive contacts1636are illustrated as taking the form of bond pads. The conductive contacts1636may be electrically coupled with the interconnect structures1628and configured to route the electrical signals of the transistor(s)1640to other external devices. For example, solder bonds may be formed on the one or more conductive contacts1636to mechanically and/or electrically couple a chip including the IC device1600with another component (e.g., a circuit board). The IC device1600may include additional or alternate structures to route the electrical signals from the interconnect layers1606-1610; for example, the conductive contacts1636may include other analogous features (e.g., posts) that route the electrical signals to external components.

In some embodiments in which the IC device1600is a double-sided die (e.g., like the die114-1), the IC device1600may include another metallization stack (not shown) on the opposite side of the device layer(s)1604. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers1606-1610, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s)1604and additional conductive contacts (not shown) on the opposite side of the IC device1600from the conductive contacts1636.

In other embodiments in which the IC device1600is a double-sided die (e.g., like the die114-1), the IC device1600may include one or more TSVs through the die substrate1602; these TSVs may make contact with the device layer(s)1604, and may provide conductive pathways between the device layer(s)1604and additional conductive contacts (not shown) on the opposite side of the IC device1600from the conductive contacts1636.

FIG.6is a cross-sectional side view of an IC device assembly1700that may include any of the microelectronic assemblies100disclosed herein. In some embodiments, the IC device assembly1700may be a microelectronic assembly100. The IC device assembly1700includes a number of components disposed on a circuit board1702(which may be, e.g., a motherboard). The IC device assembly1700includes components disposed on a first face1740of the circuit board1702and an opposing second face1742of the circuit board1702; generally, components may be disposed on one or both faces1740and1742. Any of the IC packages discussed below with reference to the IC device assembly1700may take the form of any suitable ones of the embodiments of the microelectronic assemblies100disclosed herein.

In some embodiments, the circuit board1702may be a PCB including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board1702. In other embodiments, the circuit board1702may be a non-PCB substrate. In some embodiments the circuit board1702may be, for example, a circuit board.

The IC device assembly1700illustrated inFIG.6includes a package-on-interposer structure1736coupled to the first face1740of the circuit board1702by coupling components1716. The coupling components1716may electrically and mechanically couple the package-on-interposer structure1736to the circuit board1702, and may include solder balls (as shown inFIG.6), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure.

The package-on-interposer structure1736may include an IC package1720coupled to an interposer1704by coupling components1718. The coupling components1718may take any suitable form for the application, such as the forms discussed above with reference to the coupling components1716. Although a single IC package1720is shown inFIG.6, multiple IC packages may be coupled to the interposer1704; indeed, additional interposers may be coupled to the interposer1704. The interposer1704may provide an intervening substrate used to bridge the circuit board1702and the IC package1720. The IC package1720may be or include, for example, a die (the die1502ofFIG.4), an IC device (e.g., the IC device1600ofFIG.5), or any other suitable component. Generally, the interposer1704may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer1704may couple the IC package1720(e.g., a die) to a set of ball grid array (BGA) conductive contacts of the coupling components1716for coupling to the circuit board1702. In the embodiment illustrated inFIG.6, the IC package1720and the circuit board1702are attached to opposing sides of the interposer1704; in other embodiments, the IC package1720and the circuit board1702may be attached to a same side of the interposer1704. In some embodiments, three or more components may be interconnected by way of the interposer1704.

The IC device assembly1700may include an IC package1724coupled to the first face1740of the circuit board1702by coupling components1722. The coupling components1722may take the form of any of the embodiments discussed above with reference to the coupling components1716, and the IC package1724may take the form of any of the embodiments discussed above with reference to the IC package1720.

The IC device assembly1700illustrated inFIG.6includes a package-on-package structure1734coupled to the second face1742of the circuit board1702by coupling components1728. The package-on-package structure1734may include an IC package1726and an IC package1732coupled together by coupling components1730such that the IC package1726is disposed between the circuit board1702and the IC package1732. The coupling components1728and1730may take the form of any of the embodiments of the coupling components1716discussed above, and the IC packages1726and1732may take the form of any of the embodiments of the IC package1720discussed above. The package-on-package structure1734may be configured in accordance with any of the package-on-package structures known in the art.

FIG.7is a block diagram of an example electrical device1800that may include one or more of the microelectronic assemblies100disclosed herein. For example, any suitable ones of the components of the electrical device1800may include one or more of the IC device assemblies1700, IC devices1600, or dies1502disclosed herein, and may be arranged in any of the microelectronic assemblies100disclosed herein. A number of components are illustrated inFIG.7as included in the electrical device1800, but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the electrical device1800may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die.

Additionally, in various embodiments, the electrical device1800may not include one or more of the components illustrated inFIG.7, but the electrical device1800may include interface circuitry for coupling to the one or more components. For example, the electrical device1800may not include a display device1806, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device1806may be coupled. In another set of examples, the electrical device1800may not include an audio input device1824or an audio output device1808, but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device1824or audio output device1808may be coupled.

The electrical device1800may include battery/power circuitry1814. The battery/power circuitry1814may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device1800to an energy source separate from the electrical device1800(e.g., AC line power).

The electrical device1800may include a display device1806(or corresponding interface circuitry, as discussed above). The display device1806may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

The electrical device1800may include an audio output device1808(or corresponding interface circuitry, as discussed above). The audio output device1808may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.

The electrical device1800may include an audio input device1824(or corresponding interface circuitry, as discussed above). The audio input device1824may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).

The electrical device1800may include a GPS device1818(or corresponding interface circuitry, as discussed above). The GPS device1818may be in communication with a satellite-based system and may receive a location of the electrical device1800, as known in the art.

The electrical device1800may include an other output device1810(or corresponding interface circuitry, as discussed above). Examples of the other output device1810may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

Example 1 is a microelectronic assembly, including a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects having a first solder; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects having a second solder, wherein the second solder is different than the first solder.

Example 2 may include the subject matter of Example 1, and may further specify that the second solder includes a higher-temperature solder.

Example 3 may include the subject matter of Examples 1 or 2, and may further specify that the second solder includes tin and copper; tin and gold; tin and silver; or tin, silver, and copper.

Example 4 may include the subject matter of any of Examples 1-3, and may further specify that the first solder includes a no remelt solder, a lower-temperature solder, or a conventional solder.

Example 5 may include the subject matter of Example 4, and may further specify that the first solder interconnects include the lower-temperature solder or the conventional solder, and the microelectronic assembly and may further include an underfill material surrounding the first solder interconnects.

Example 6 may include the subject matter of any of Examples 1-3, and may further specify that the first solder interconnects include tin and bismuth; tin, silver, and bismuth; indium; indium and tin; or gallium.

Example 7 may include the subject matter of any of Examples 1-6, and may further specify that a pitch of the first solder interconnects is between 1 and 100 microns.

Example 8 may include the subject matter of any of Examples 1-7, and may further specify that a pitch of the second solder interconnects is between 50 and 150 microns.

Example 9 may include the subject matter of any of Examples 1-8, and may further specify that the first die is electrically coupled to the second die by the first solder interconnects, conductive pathways in the RDL, and the second solder interconnects.

Example 10 may include the subject matter of any of Examples 1-9, and may further include a package substrate electrically coupled to the first surface of the first die by third solder interconnects having a third solder, wherein the third solder is different than the second solder.

Example 11 may include the subject matter of Example 10, and may further specify that the third solder includes a no remelt solder, a lower-temperature solder, or a conventional solder

Example 12 may include the subject matter of any of Examples 1-11, and may further include a conductive pillar in the first layer, wherein the conductive pillar is coupled to the RDL by non-solder interconnects.

Example 13 may include the subject matter of any of Examples 1-12, and may further specify that the RDL is a first RDL, and may further include a second RDL at the first surface of the first die.

Example 14 may include the subject matter of Example 13, and may further include a passivation layer between the second RDL and the first surface of the first die.

Example 15 may include the subject matter of any of Examples 1-14, and may further specify that the first layer and the second layer include one or more insulating materials.

Example 16 is a microelectronic assembly, including a first die, having a first surface and an opposing second surface, in a first layer; a redistribution layer (RDL) on the first layer, wherein the RDL includes conductive vias having a greater width towards a first surface of the RDL and a smaller width towards an opposing second surface of the RDL; wherein the first surface of the RDL is electrically coupled to the second surface of the first die by first solder interconnects; and a second die in a second layer on the RDL, wherein the second die is electrically coupled to the RDL by second solder interconnects, wherein the second solder interconnects include a higher-temperature solder.

Example 17 may include the subject matter of Example 16, and may further specify that the first solder interconnects include a no remelt solder, a lower-temperature solder, or a conventional solder.

Example 18 may include the subject matter of Example 17, and may further specify that the first solder interconnects include the lower-temperature solder or the conventional solder, and the microelectronic assembly and may further include an underfill material surrounding the first solder interconnects.

Example 19 may include the subject matter of Example 16, and may further specify that the first solder interconnects include tin and bismuth; tin, silver, and bismuth; indium; indium and tin; or gallium.

Example 20 may include the subject matter of Example 16, and may further specify that the second solder interconnects include tin and copper; tin and gold; tin and silver; or tin, silver, and copper.

Example 21 may include the subject matter of any of Examples 16-20, and may further specify that a pitch of the first solder interconnects is between 1 and 100 microns.

Example 22 may include the subject matter of any of Examples 16-21, and may further specify that a pitch of the second solder interconnects is between 50 and 150 microns.

Example 23 may include the subject matter of any of Examples 16-22, and may further specify that the first die is electrically coupled to the second die by the first solder interconnects, conductive pathways in the RDL, and the second solder interconnects.

Example 24 may include the subject matter of any of Examples 16-23, and may further include a package substrate electrically coupled to the first surface of the first die by third solder interconnects, wherein the third solder interconnects include a no remelt solder, a lower-temperature solder, or a conventional solder.

Example 25 may include the subject matter of any of Examples 16-24, and may further include a conductive pillar in the first layer, wherein the conductive pillar is coupled to the RDL by non-solder interconnects.

Example 26 may include the subject matter of any of Examples 16-25, and may further specify that the RDL is a first RDL, and may further include a second RDL at the first surface of the first die.

Example 27 may include the subject matter of Example 26, and may further include a passivation layer between the second RDL and the first surface of the first die.

Example 28 may include the subject matter of any of Examples 16-27, and may further specify that the first layer and the second layer include one or more insulating materials.

Example 29 is a microelectronic assembly, including a first die, having a first surface with first conductive contacts and an opposing second surface with second conductive contacts, in a first layer; a redistribution layer (RDL), having a first surface with third conductive contacts and an opposing second surface with fourth conductive contacts, on the first layer, wherein the third conductive contacts on the RDL are electrically coupled to the second conductive contacts on the first die by first solder interconnects, and wherein the first solder interconnects include a no remelt solder, a lower-temperature solder, or a conventional solder; and a second die, having a surface with fifth conductive contacts, in a second layer on the second surface of the RDL, wherein the fifth conductive contacts on the second die are electrically coupled to the fourth conductive contacts on the RDL by second solder interconnects, wherein the second solder interconnects include a higher-temperature solder.

Example 30 may include the subject matter of Example 29, and may further specify that the first die is electrically coupled to the second die by the first solder interconnects, conductive pathways in the RDL, and the second solder interconnects.

Example 31 may include the subject matter of Examples 29 or 30, and may further specify that the RDL further includes conductive vias having a greater width towards the first surface of the RDL and a smaller width towards the second surface of the RDL.

Example 32 may include the subject matter of any of Examples 29-31, and may further specify that a pitch of the first solder interconnects is between 1 and 100 microns.

Example 33 may include the subject matter of any of Examples 29-32, and may further specify that a pitch of the second solder interconnects is between 50 and 150 microns.

Example 34 may include the subject matter of any of Examples 29-33, and may further specify that the second solder interconnects include tin and copper; tin and gold; tin and silver; or tin, silver, and copper.

Example 35 may include the subject matter of any of Examples 29-34, and may further specify that the first solder interconnects include tin and bismuth; tin, silver, and bismuth; indium; indium and tin; or gallium.

Example 36 may include the subject matter of any of Examples 29-34, and may further specify that the first solder interconnects include the no remelt solder, and wherein the no remelt solder includes copper and tin.

Example 37 may include the subject matter of any of Examples 29-34, and may further specify that the first solder interconnects include the lower-temperature solder or the conventional solder, and the microelectronic assembly and may further include an underfill material surrounding the first solder interconnects.

Example 38 may include the subject matter of any of Examples 29-37, and may further include a package substrate electrically coupled to the first conductive contacts of the first die by third solder interconnects, wherein the third solder interconnects include the no remelt solder, the lower-temperature solder, or the conventional solder.

Example 39 may include the subject matter of Example 38, and may further specify that the third solder interconnects include tin and bismuth; tin, silver, and bismuth; indium; indium and tin; or gallium.

Example 40 may include the subject matter of Example 38, and may further specify that the third solder interconnects include the lower-temperature solder or the conventional solder, and the microelectronic assembly and may further include an underfill material surrounding the third solder interconnects.

Example 41 is a method of manufacturing a microelectronic assembly, including patterning a higher-temperature solder on a first carrier and encapsulating the higher-temperature solder with a removable protective material; forming a redistribution layer (RDL) on the removable protective material and electrically coupling the RDL to the higher-temperature solder; depositing a no remelt solder, a lower-temperature solder, or a conventional solder on conductive contacts on a top surface of the RDL; attaching a first die to the no remelt solder, the lower-temperature solder, or the conventional solder on the conductive contacts on the top surface of the RDL and forming first solder interconnects; forming a conductive pillar on one or more of the conductive contacts on the top surface of the RDL; encapsulating a first die and the conductive pillar with an insulating material and planarizing; depositing die-to-package substrate (DTPS) solder on conductive contacts on a top surface of the insulating material, encapsulating with a sacrificial material, and attaching a second carrier to a top surface of the sacrificial material, wherein the DTPS solder includes the no remelt solder, the lower-temperature solder, or the conventional solder; inverting the assembly, detaching the first carrier, and removing the removable protective material; attaching a second die to the higher-temperature solder and forming second solder interconnects; and detaching the second carrier and removing the sacrificial material.

Example 42 may include the subject matter of Example 41, and may further specify that the first solder interconnects include tin and bismuth; tin, silver, and bismuth; indium; indium and tin; or gallium.

Example 43 may include the subject matter of Examples 41 or 42, and may further specify that the second solder interconnects include tin and copper; tin and gold; or tin, silver, and copper.

Example 44 may include the subject matter of any of Examples 41-43, and may further include depositing an underfill material around the first solder interconnects.

Example 45 may include the subject matter of any of Examples 41-44, and may further specify that the RDL is a first RDL, and the method and may further include forming a second RDL on the insulating material and depositing the DTPS solder on conductive contacts on a top surface of the second RDL.

Example 46 may include the subject matter of any of Examples 41-44, and may further include attaching a package substrate to the DTPS solder and forming third solder interconnects.

Example 47 may include the subject matter of Example 46, and may further specify that the third solder interconnects are formed before the second solder interconnects are formed.

Example 48 may include the subject matter of Example 47, and may further include depositing an underfill material around the third solder interconnects before forming the second solder interconnects.