Structure and formation method of semiconductor device with fin structures

A structure and formation method of a semiconductor device is provided. The semiconductor device structure includes an epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a dielectric fin over the semiconductor substrate. The dielectric fin extends upwards to exceed a bottom surface of the epitaxial structure. The dielectric fin has a dielectric structure and a protective shell, and the protective shell extends along sidewalls and a bottom of the dielectric structure. The protective shell has a first average grain size, and the dielectric structure has a second average grain size. The first average grain size is larger than the second average grain size.

BACKGROUND

The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs. Each generation has smaller and more complex circuits than the previous generation.

However, these advances have increased the complexity of processing and manufacturing ICs. Since feature sizes continue to decrease, fabrication processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices at smaller and smaller sizes.

DETAILED DESCRIPTION

The term “substantially” in the description, such as in “substantially flat” or in “substantially coplanar”, etc., will be understood by the person skilled in the art. In some embodiments the adjective substantially may be removed. Where applicable, the term “substantially” may also include embodiments with “entirely”, “completely”, “all”, etc. Where applicable, the term “substantially” may also relate to 90% or higher, such as 95% or higher, especially 99% or higher, including 100%. Furthermore, terms such as “substantially parallel” or “substantially perpendicular” are to be interpreted as not to exclude insignificant deviation from the specified arrangement and may include for example deviations of up to 10° in some embodiments. The word “substantially” does not exclude “completely” e.g. a composition which is “substantially free” from Y may be completely free from Y in some embodiments.

Terms such as “about” in conjunction with a specific distance or size are to be interpreted so as not to exclude insignificant deviation from the specified distance or size and may include for example deviations of up to 10% in some embodiments. The term “about” in relation to a numerical value x may mean x±5 or 10% in some embodiments.

Terms such as “about” in conjunction with a specific distance or size are to be interpreted so as not to exclude insignificant deviation from the specified distance or size and may include for example deviations of up to 10%. The term “about” in relation to a numerical value x may mean x±5 or 10%.

FIGS.1A-1Hare cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, in accordance with some embodiments. As shown inFIG.1A, a semiconductor substrate100is received or provided. In some embodiments, the semiconductor substrate100is a bulk semiconductor substrate, such as a semiconductor wafer.

The semiconductor substrate100may include silicon or other elementary semiconductor materials such as germanium. The semiconductor substrate100may be un-doped or doped (e.g., p-type, n-type, or a combination thereof). In some embodiments, the semiconductor substrate100includes an epitaxially grown semiconductor layer on a dielectric layer. The epitaxially grown semiconductor layer may be made of silicon germanium, silicon, germanium, one or more other suitable materials, or a combination thereof.

In some other embodiments, the semiconductor substrate100includes a compound semiconductor. For example, the compound semiconductor includes one or more III-V compound semiconductors having a composition defined by the formula Alx1Gax2Inx3AsY1PY2NY2NY3SbY4, where X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions. Each of them is greater than or equal to zero, and added together they equal 1. The compound semiconductor may include silicon carbide, gallium arsenide, indium arsenide, indium phosphide, one or more other suitable compound semiconductors, or a combination thereof. Another suitable substrate including II-VI compound semiconductors may also be used.

In some embodiments, the semiconductor substrate100is an active layer of a semiconductor-on-insulator (SOI) substrate. The SOI substrate may be fabricated using a separation by implantation of oxygen (SIMOX) process, a wafer bonding process, another applicable method, or a combination thereof. In some other embodiments, the semiconductor substrate100includes a multi-layered structure. For example, the semiconductor substrate100includes a silicon-germanium layer formed on a bulk silicon layer.

As shown inFIG.1A, multiple fin structures101A,101B, and101C are formed over the semiconductor substrate100, in accordance with some embodiments. In some embodiments, multiple recesses (or trenches) are formed in the semiconductor substrate100, in accordance with some embodiments. As a result, multiple fin structures that protrude from the surface of the semiconductor substrate100are formed or defined between the recesses. In some embodiments, one or more photolithography and etching processes are used to form the recesses. In some embodiments, the fin structures101A to101C are in direct contact with the semiconductor substrate100.

However, embodiments of the disclosure have many variations and/or modifications. In some other embodiments, the fin structures101A to101C are not in direct contact with the semiconductor substrate100. One or more other material layers may be formed between the semiconductor substrate100and the fin structures101A to101C. For example, a dielectric layer may be formed therebetween.

As shown inFIG.1B, an isolation layer102is deposited over the semiconductor substrate100and the fin structures101A to101C, in accordance with some embodiments. In some embodiments, the isolation layer102extends along sidewalls and tops of the fin structures101A to101C. In some embodiments, the isolation layer102conformally extends along the fin structures101A to101C. In some embodiments, the isolation layer102is in direct contact with the fin structures101A to101C.

In some embodiments, the isolation layer102is made of or includes silicon oxide, silicon oxynitride, carbon-containing silicon oxide, one or more other suitable materials, or a combination thereof. The isolation layer102may be deposited using a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal oxidation process, one or more other applicable processes, or a combination thereof.

As shown inFIG.1C, a protective layer104is deposited over the isolation layer102, in accordance with some embodiments. In some embodiments, the protective layer104extends conformally along the isolation layer102. In some embodiments, the protective layer104extends along sidewalls and tops of the fin structures101A to101C. In some embodiments, the protective layer104conformally extends along the fin structures101A to101C. In some embodiments, the protective layer104is in direct contact with the isolation layer102.

In some embodiments, the protective layer104is made of or includes a high dielectric constant (high-k) material. The high-k material may include hafnium oxide, hafnium zirconium oxide, zirconium oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, lanthanum oxide, hafnium lanthanum oxide, one or more other suitable materials, or a combination thereof. The protective layer104may be deposited using an ALD process, a CVD process, one or more other applicable processes, or a combination thereof.

As shown inFIG.1D, a dielectric layer106is deposited over the protective layer104, in accordance with some embodiments. In some embodiments, the dielectric layer106extends conformally along the protective layer104. In some embodiments, the dielectric layer106extends along sidewalls and tops of the fin structures101A to101C. In some embodiments, the dielectric layer106conformally extends along the fin structures101A to101C. In some embodiments, the dielectric layer106is in direct contact with the protective layer104. In some embodiments, the dielectric layer106surrounds seams S, as shown inFIG.1D.

In some embodiments, the dielectric layer106is made of or includes silicon nitride, silicon oxide, silicon oxynitride, carbon-containing silicon oxide, carbon-containing silicon oxynitride, one or more other suitable materials, or a combination thereof. The dielectric layer106may be deposited using an ALD process, a CVD process, one or more other applicable processes, or a combination thereof. In some embodiments, the deposition of the dielectric layer106involves a thermal operation. For example, the deposition of the dielectric layer106is performed at a high temperature that is in a range from about 450 degrees C. to about 550 degrees C.

In some embodiments, due to the thermal operation, the protective layer104is crystallized during the deposition of the dielectric layer106. As a result, the protective layer104is crystallized to form a crystallized protective layer104′, as shown inFIG.1Din accordance with some embodiments. The crystallized protective layer104′ may have a better etching resistance than the protective layer104that is not or merely slightly crystallized. The crystallized protective layer104′ may thus provide better protection to dielectric fins that will be formed later.

In some embodiments, the dielectric layer106is substantially not crystallized. The dielectric layer106may be amorphous or include a small amount of nanocrystals. The crystallized protective layer104′ may have a first average grain size, and the dielectric layer106may have a second average grain size. In some embodiments, the first average grain size is larger than the second average grain size.

Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, one or more additional thermal operations are used to form the crystallized protective layer104′ and/or to enhance the crystallization of the crystallized protective layer104′. The operation temperature of the thermal operations may be in a range from about 450 degrees C. to about 1000 degrees C. The operation time of the thermal operations may be in a range from about 1 second to about 1 hour.

The crystallized protective layer104′ has a first dielectric constant, and the dielectric layer106has a second dielectric constant. In some embodiments, the first dielectric constant is higher than the second dielectric constant. In some embodiments, the first dielectric constant is higher than about 14. In some embodiments, the first dielectric constant is higher than the dielectric constant of silicon nitride. In some embodiments, the first dielectric constant is higher than the dielectric constant of carbon-containing silicon nitride. In some embodiments, the first dielectric constant is higher than the dielectric constant of carbon-containing silicon oxynitride.

As shown inFIG.1E, the dielectric layer106, the crystallized protective layer104′, and the isolation layer102are partially removed, in accordance with some embodiments. As a result, the tops of the fin structures101A to101C that are originally covered by these layers are exposed, as shown inFIG.1E. In some embodiments, the dielectric layer106, the crystallized protective layer104′, and the isolation layer102are partially removed using a planarization process. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, a dry polishing process, an etching process, one or more other applicable processes, or a combination thereof.

As shown inFIG.1F, the isolation layer102is recessed, in accordance with some embodiments. The isolation layer102may be recessed using an etching back process. As a result, the remaining portion of the isolation layer102forms an isolation structure. The isolation structure (i.e., the isolation layer102) laterally surrounds lower portions of the fin structures101A to101C, as shown inFIG.1F. The reference number “102” may also be used to designate the isolation structure.

As shown inFIG.1F, the remaining portions of the crystallized protective layer104′ and the dielectric layer106together form multiple dielectric fins108. The isolation structure (i.e., the isolation layer102) also laterally surrounds lower portions of the dielectric fins108. Each of the fin structures101A to101C and each of the dielectric fins108protrude from the top surface of the isolation structure (i.e., the isolation layer102). In some embodiments, in each of the dielectric fins108, the seam S extends downwards from the top surface of the inner portion (i.e., the dielectric layer106) to exceed the topmost surface of the isolation structure102, as shown inFIG.1F.

The crystallized protective layer104′ of the dielectric fin108may function as a protective shell that protects the inner portion of the dielectric fin108. The inner portion of the dielectric fin108is a dielectric structure constructed by the dielectric layer106. During a subsequent etching process, the crystallized protective layer104′ that has good etching resistance may protect the dielectric layer106from being damaged. Due to the blocking of the dielectric layer106, voids are prevented from being formed in the crystallized protective layer104′.

In some other cases where the dielectric layer106is not formed, the crystallization of the protective layer104may occur in accompany with grain growth. As a result, the seam S may be randomly merged into voids. These voids may result in the unexpected merging of nearby epitaxial structures. Alternatively, the voids may result in unexpected short circuiting between two portions of a gate stack that are designed to be electrically isolated from each other.

FIGS.2A-2Bare cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, in accordance with some embodiments. As shown inFIG.2A, after the formation of the dielectric fins108, a dummy gate stack is formed over the fin structures101A to101C and the dielectric fins108, in accordance with some embodiments. The dummy gate stack is formed to partially cover and to extend across the fin structures101A to101C.

The dummy gate stack includes a dummy gate dielectric layer116and a dummy gate electrode118. The dummy gate dielectric layer116may be made of or include silicon oxide. The dummy gate electrode118may be made of or include polysilicon. In some embodiments, a dummy gate dielectric material layer and a dummy gate electrode layer are sequentially deposited over the isolation structure102, the fin structures101A to101C, and the dielectric fins108. Afterwards, the dummy gate dielectric material layer and the dummy gate electrode layer are patterned to form the dummy gate stack.

FIG.1Gshows the cross-sectional view of the portion of the semiconductor device structure that is not covered by the dummy gate stack. The cross-sectional view is taken along a line parallel to the longitudinal direction of the dummy gate stack but not overlapping the dummy gate stack.

As shown inFIG.1G, after the formation of the dummy gate stack as illustrated inFIG.2A, the exposed portions of the fin structures101A to101C are partially removed, in accordance with some embodiments. The fin structures101A to101C may be recessed using one or more etching processes. In some embodiments, after the recessing, the top surfaces of the fin structures101A to101C are lower than the top surface of the isolation structure102.

In some embodiments, the dielectric layer106of the dielectric fin108is slightly etched during the recessing of the fin structures101A to101C. In some embodiments, the topmost surface of the inner portion (i.e., the dielectric layer106) of the dielectric fin108is closer to the semiconductor substrate100than the topmost surface of the crystallized protective layer104′ (that functions as a protective shell) of the dielectric fin108. In some embodiments, the topmost surface of the inner portion (i.e., the dielectric layer106) has a curved profile.

As shown inFIG.1G, the crystallized protective layer104′ has a film thickness T1, and the dielectric layer106has a film thickness T2. In some embodiments, the film thickness T1of the crystallized protective layer104′ is in a range from about 2 nm to about 5 nm. In some embodiments, the film thickness T2of the dielectric layer106is in a range from about 2 nm to about 10 nm. The ratio (T1/T2) of the film thickness T1to the film thickness T2may be in a range from about 0.5 to about 1. In some embodiments, the ratio of the film thickness T1to the total width of the dielectric fin108may be in a range from about 0.2 to about 0.4.

In some cases where the film thickness T1of the crystallized protective layer104′ is thinner than about 2 nm, the grain growth of the crystallized protective layer104′ might be suppressed. The crystallized protective layer104′ might not be able to provide sufficient etch resistance to sustain the subsequent etching process. In some other cases where the film thickness T1of the crystallized protective layer104′ is thicker than about 5 nm, voids might be formed in the crystallized protective layer104′ since the seam would be too narrow. As a result, the seam S may be randomly merged into voids. As mentioned above, these voids may results in the unexpected merging of nearby epitaxial structures. Alternatively, the voids may result in unexpected short circuiting between two portions of a gate stack that are designed to be electrically isolated from each other.

As shown inFIG.1H, epitaxial structures110A,110B, and110C are respectively formed on the recessed fin structures101A,110B, and110C, in accordance with some embodiments. Due to the dielectric fins108, each of the epitaxial structures110A,110B, and110C is prevented from being merged with another nearby epitaxial structure. In some embodiments, the dielectric fins108are in direct contact with the nearby epitaxial structures110A,110B, and/or110C.

In some embodiments, the epitaxial structures110A to110C are p-type semiconductor structures. For example, the epitaxial structures110A to110C may include epitaxially grown silicon germanium or silicon germanium doped with boron. It should be appreciated, however, that the epitaxial structures110A to110C are not limited to being p-type semiconductor structures.

In some embodiments, the epitaxial structures110A to110C are n-type semiconductor structures. The epitaxial structures110A to110C may include epitaxially grown silicon, epitaxially grown silicon carbide (SiC), epitaxially grown silicon phosphide (SiP), or another suitable epitaxially grown semiconductor material. Alternatively, one or two of the epitaxial structures110A to110C is a p-type semiconductor structure while another one is an n-type semiconductor structure.

In some embodiments, the epitaxial structures110A to110C are formed by using a selective epitaxial growth (SEG) process, a CVD process (e.g., a vapor-phase epitaxy (VPE) process, a low pressure chemical vapor deposition (LPCVD) process, and/or an ultra-high vacuum CVD (UHV-CVD) process), a molecular beam epitaxy process, one or more other applicable processes, or a combination thereof.

In some embodiments, one or both of the epitaxial structures110A to110C are doped with one or more suitable dopants. For example, the epitaxial structures110A to110C are SiGe source/drain features doped with boron (B), indium (In), or another suitable dopant. Alternatively, in some other embodiments, one or both of the epitaxial structures110A to110C are Si source/drain features doped with phosphor (P), antimony (Sb), or another suitable dopant.

In some embodiments, the epitaxial structures110A to110C are doped in-situ during their epitaxial growth. In some other embodiments, the epitaxial structures110A to110C are not doped during the growth of the epitaxial structures110A to110C. Instead, after the formation of the epitaxial structures110A to110C, the epitaxial structures110A to110C are doped in a subsequent process. In some embodiments, the doping is achieved by using an ion implantation process, a plasma immersion ion implantation process, a gas and/or solid source diffusion process, one or more other applicable processes, or a combination thereof. In some embodiments, the epitaxial structures110A to110C are further exposed to one or more annealing processes to activate the dopants. For example, a rapid thermal annealing process is used.

After the formation of the epitaxial structures110A to110C, a dielectric layer is deposited over the dummy gate stack and the epitaxial structures110A to110C. Afterwards, a planarization process is used to thin down the dielectric layer and to expose the top surface of the dummy gate stack. Then, the dummy gate stack is removed to form a trench that partially exposes the fin structures101A to101C and the dielectric fins108. Afterwards, a metal gate stack is formed in the trench.

As shown inFIG.2B, the metal gate stack includes a gate dielectric layer126and a metal gate electrode128. The metal gate electrode128may include a work function layer and a conducive filling. In some embodiments, the formation of the metal gate stack involves the deposition of multiple metal gate stack layers over the dielectric layer to fill the trench.

In some embodiments, the gate dielectric layer126is made of or includes a dielectric material with high dielectric constant (high-K). The gate dielectric layer126may be made of or include hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, one or more other suitable high-K materials, or a combination thereof. The gate dielectric layer126may be deposited using an ALD process, a CVD process, one or more other applicable processes, or a combination thereof.

In some embodiments, before the formation of the gate dielectric layer126, an interfacial layer is formed on the surfaces of the fin structures101A to101C. The interfacial layer is very thin and is made of, for example, silicon oxide or germanium oxide. In some embodiments, the interfacial layer is formed by applying an oxidizing agent on the surfaces of the fin structures101A to101C. For example, a hydrogen peroxide-containing liquid may be applied or provided on the surfaces of the fin structures101A to101C so as to grow the interfacial layer.

The work function layer may be used to provide the desired work function for transistors to enhance device performance including improved threshold voltage. In some embodiments, the work function layer is used for forming an NMOS device. The work function layer is an n-type work function layer. The n-type work function layer is capable of providing a work function value suitable for the device, such as equal to or less than about 4.5 eV.

The n-type work function layer may include metal, metal carbide, metal nitride, or a combination thereof. For example, the n-type work function layer includes titanium nitride, tantalum, tantalum nitride, one or more other suitable materials, or a combination thereof. In some embodiments, the n-type work function is an aluminum-containing layer. The aluminum-containing layer may be made of or include TiAlC, TiAlO, TiAlN, one or more other suitable materials, or a combination thereof.

The work function layer may also be made of or include hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, aluminum carbide), aluminides, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides, or a combinations thereof. The thickness and/or the compositions of the work function layer may be fine-tuned to adjust the work function level.

The work function layer may be deposited over the gate dielectric layer126using an ALD process, a CVD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

In some embodiments, a barrier layer is formed before the work function layer to interface the gate dielectric layer126with the subsequently formed work function layer. The barrier layer may also be used to prevent diffusion between the gate dielectric layer126and the subsequently formed work function layer. The barrier layer may be made of or include a metal-containing material. The metal-containing material may include titanium nitride, tantalum nitride, one or more other suitable materials, or a combination thereof. The barrier layer may be deposited using an ALD process, a CVD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

In some embodiments, the conductive filling is made of or includes a metal material. The metal material may include tungsten, aluminum, copper, cobalt, one or more other suitable materials, or a combination thereof. A conductive layer used for forming the conductive filling may be deposited over the work function layer using a CVD process, an ALD process, a PVD process, an electroplating process, an electroless plating process, a spin coating process, one or more other applicable processes, or a combination thereof.

In some embodiments, a blocking layer is formed over the work function layer before the formation of the conductive layer used for forming the conductive filling. The blocking layer may be used to prevent the subsequently formed conductive layer from diffusing or penetrating into the work function layer. The blocking layer may be made of or include tantalum nitride, titanium nitride, one or more other suitable materials, or a combination thereof. The blocking layer may be deposited using an ALD process, a PVD process, an electroplating process, an electroless plating process, one or more other applicable processes, or a combination thereof.

Afterwards, a planarization process is performed to remove the portions of the metal gate stack layers that are outside of the trench, in accordance with some embodiments. As a result, the remaining portions of the metal gate stack layers form the metal gate stack, as shown inFIG.2B.

Afterwards, an insulating structure190is formed in the metal gate stack, as shown inFIG.2Bin accordance with some embodiments. In some embodiments, the insulating structure190penetrates through the metal gate electrode128and the gate dielectric layer126to reach one of the dielectric fins108. In some embodiments, the insulating structure190and the dielectric fin108thereunder together separate the metal gate stack into a first portion128aand a second portion128b, as shown inFIG.2B. The first portion128aand the second portion128bare thus electrically isolated from each other. The first portion128aand the second portion128bthat are cut from the same metal gate stack may now function as two metal gate stacks of different devices.

The insulating structure190may be made of or include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, carbon-containing silicon oxide, carbon-containing silicon nitride, carbon-containing silicon oxynitride, one or more other suitable materials, or a combination thereof. In some embodiments, a photolithography process and an etching process is used to partially remove the metal gate stack and to form a trench that exposes one of the dielectric fins108. Afterwards, the insulating material used for forming the insulating structure190is formed to fill the trench. A planarization process may then be used to remove the portion of the insulating material outside of the trench. As a result, the remaining portion of the insulating material in the trench forms the insulating structure190.

Many variations and/or modifications can be made to embodiments of the disclosure.FIGS.3A-3Gare cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, in accordance with some embodiments. As shown inFIG.3A, a structure the same as or similar to the structure shown inFIG.1Eis formed, in accordance with some embodiments.

As shown inFIG.3B, before the recessing of the isolation layer102, the dielectric layer106is partially removed to form recesses202, in accordance with some embodiments. In some embodiments, the recesses202connect the seam S.

As shown inFIG.3C, a protective material layer204is deposited to fill the recesses202, in accordance with some embodiments. In some embodiments, the protective material layer204is made of or includes a high dielectric constant (high-k) material. The high-k material may include hafnium oxide, hafnium zirconium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, one or more other suitable materials, or a combination thereof. The protective material layer204may be deposited using an ALD process, a CVD process, a flowable chemical vapor deposition (FCVD) process, one or more other applicable processes, or a combination thereof. The material and/or formation method of the protective material layer204may be the same as or similar to those of the protective layer104.

As shown inFIG.3D, the portion of the protective material layer204outside of the recesses202is removed, in accordance with some embodiments. As a result, the remaining portions of the protective material layer204form protective caps206over the inner portions of the dielectric fins108. In some embodiments, the seams S are sealed by the protective caps206and become closed holes. In some embodiments, the topmost surfaces of the protective caps206and the protective shells (i.e., the crystallized protective layer104′) are at substantially the same level, as shown inFIG.3D. In some embodiments, the protective shell (i.e., the crystallized protective layer104′) extends along or covers the sidewalls of the protective cap206, as shown inFIG.3D.

As shown inFIG.3E, similar to the process illustrated inFIG.1F, the isolation layer102is partially removed, in accordance with some embodiments. As a result, the fin structures101A to101C and the dielectric fins108protrude from the top surface of the isolation structure (i.e., the remaining portion of the isolation layer102).

Afterwards, similar to the embodiments illustrated inFIG.2A, a dummy gate stack is formed to partially cover the fin structures101A to101B and the dielectric fins108.

As shown inFIG.3F, similar to the process illustrated inFIG.1G, the portions of the fin structures101A to101C that are not covered by the dummy gate stack is then partially removed, in accordance with some embodiments. During the recessing of the fin structures101A to101C, the dielectric structure (i.e., the dielectric layer106) of the dielectric fin108under the protective cap206is protected and prevented from being damaged by the etchant used for recessing the fin structures101A to101C.

In some embodiments, similar to the protective shell of the dielectric fin108, one or more thermal operations is used to crystallize the protective cap206, so as to enhance the etching resistance of the protective cap206. In some embodiments, the thermal operation is performed after the deposition of the protective material layer204. In some other embodiments, the thermal operation is performed after the formation of the protective cap206and before the recessing of the fin structures101A to101C.

As shown inFIG.3G, similar to the embodiments illustrated inFIG.1H, the epitaxial structures110A to110C are formed, in accordance with some embodiments. Due to the dielectric fins108, the epitaxial structures110A to110C are prevented from being merged together. The performance and reliability of the semiconductor device structure are ensured.

Many variations and/or modifications can be made to embodiments of the disclosure.FIGS.4A-4Fare cross-sectional views of various stages of a process for forming a portion of a semiconductor device structure, in accordance with some embodiments. As shown inFIG.4A, a structure the same as or similar to the structure shown inFIG.1Cis formed, in accordance with some embodiments.

As shown inFIG.4B, a thermal operation is used to crystallize the protective layer104, so as to form a crystallized protective layer104′, in accordance with some embodiments.

As shown inFIG.4C, a dielectric layer306is deposited over the crystallized protective layer104′ to overfill the trenches, in accordance with some embodiments. The dielectric layer306may be made of or include silicon nitride, silicon oxide, silicon oxynitride, carbon-containing silicon oxide, carbon-containing silicon oxynitride, one or more other suitable materials, or a combination thereof. The dielectric layer306may be deposited using an FCVD process. In some embodiments, no seam is formed, as shown inFIG.4C.

As shown inFIG.4D, similar to the process illustrated inFIGS.3A-3E, the protective caps206are formed, and the isolation layer102is partially removed, in accordance with some embodiments. As a result, the fin structures101A to101C and the dielectric fins108protrude from the top surface of the isolation structure (i.e., the remaining portion of the isolation layer102).

Afterwards, similar to the embodiments illustrated inFIG.2A, a dummy gate stack is formed to partially cover the fin structures101A to101B and the dielectric fins108.

As shown inFIG.4E, similar to the process illustrated inFIG.1G, the portions of the fin structures101A to101C that are not covered by the dummy gate stack is then partially removed, in accordance with some embodiments. During the recessing of the fin structures101A to101C, the inner portion (i.e., the dielectric layer306) of the dielectric fin108under the protective cap206is protected and prevented from being damaged by the etchant used for recessing the fin structures101A to101C.

As shown inFIG.4F, similar to the embodiments illustrated inFIG.1H, the epitaxial structures110A to110C are formed, in accordance with some embodiments. Due to the dielectric fins108, the epitaxial structures110A to110C are prevented from being merged together. The performance and reliability of the semiconductor device structure are ensured.

Many variations and/or modifications can be made to embodiments of the disclosure.FIG.5is a cross-sectional view of an intermediate stage of a process for forming a portion of a semiconductor device structure, in accordance with some embodiments. In some embodiments, no protective cap is formed over the dielectric layer306.

In some embodiments, similar to the structure shown inFIG.1G, the dielectric layer306of the dielectric fin108is slightly etched during the recessing of the fin structures101A to101C. In some embodiments, the topmost surface of the inner portion (i.e., the dielectric layer306) of the dielectric fin108is closer to the semiconductor substrate100than the topmost surface of the crystallized protective layer104′ (that functions as a protective shell) of the dielectric fin108. In some embodiments, the topmost surface of the inner portion (i.e., the dielectric layer306) has a curved profile. In some embodiments, the topmost surface of the inner portion (i.e., the dielectric layer306) has convex profile facing downwards, as shown inFIG.5.

Embodiments of the disclosure form a semiconductor device structure with dielectric fins. The dielectric fin has a protective shell that extends along sidewalls and a bottom of a dielectric structure. The protective shell may be a crystallized high-k material that has a better etching resistance than the inner portion (i.e., the dielectric structure) of the dielectric fin. The protective shell ensures the structural stability of the dielectric fin. Due to the blocking of the dielectric structure, the seam surrounded by the protective shell is prevented from being merged to form voids through the protective shell. The reliability and performance of the semiconductor device structure are improved.

In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure over a semiconductor substrate. The semiconductor device structure also includes a first epitaxial structure over the first fin structure and a second epitaxial structure over the second fin structure. The semiconductor device structure further includes a dielectric fin over the semiconductor substrate, and the dielectric fin is between the first fin structure and the second fin structure. The dielectric fin has an inner portion and a protective layer, and the protective layer extends along sidewalls and a bottom of the inner portion. The protective layer has a dielectric constant higher than that of silicon nitride.

In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes an epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a dielectric fin over the semiconductor substrate. The dielectric fin extends upwards to exceed a bottom surface of the epitaxial structure. The dielectric fin has a dielectric structure and a protective shell, and the protective shell extends along sidewalls and a bottom of the dielectric structure. The protective shell has a first average grain size, and the dielectric structure has a second average grain size. The first average grain size is larger than the second average grain size.

In accordance with some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming an isolation layer over the fin structure and the semiconductor substrate. The method also includes forming a protective layer over the isolation layer and forming a dielectric layer over the protective layer. The method further includes partially removing the isolation layer, the protective layer, and the dielectric layer. A remaining portion of the isolation layer forms an isolation structure, and remaining portions of the protective layer and the dielectric layer form a dielectric fin. The isolation structure laterally surrounds a lower portion of the fin structure and a lower portion of the dielectric fin. The protective shell has a first average grain size, the dielectric structure has a second average grain size, and the first average grain size is larger than the second average grain size.