Wiring with external terminal

Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes a first group of wiring layers of an internal redistributing layer (iRDL) providing a power supply voltage and a second group of wiring layers of another iRDL providing a ground voltage. The first group of wiring layers providing the power supply voltage from a first side of the semiconductor device to a second side of the semiconductor device opposite to the first side are at least partially separated by at least one cut portion between the first side and the second side.

BACKGROUND

High data reliability, high speed of memory access, reduced chip size and reduced power consumption are features that are demanded from semiconductor memory. To achieve reduced power consumption and higher memory access speed, a redistribution layer (RDL), a metal layer that provides low impedance and high conductivity has been increasingly used in semiconductor memory devices, to couple, for example, pads and data queue circuits (or data input/output circuits) across layers. Thin package products including multiple chips stacked thereon have been increasingly used. In a thin package product, the RDL increases the thickness of a laminated material on a board.

To construct a package or chip stack with a reduced height, the thickness of each chip must be reduced. To reduce the thickness of each chip to achieve a desired chip thickness, a back surface of a wafer that provide chips may be processed by a back grinding process. Because the thickness of the RDL accounts for approximately 10% of the entire chip thickness, distortion of the RDL that affects the warpage of the chip becomes non-negligible as the wafer is thinned by back grinding. Thus, the thickness of a wafer providing chips has been reduced as desired, the warpage of the chip in the product due to the distortion of the RDL has become a major problem.

For example, forming a thin film on a flat wafer creates a mechanical stress applied to the wafer, and to reduce this stress, the wafer warps.FIG. 1is a schematic diagram of warpage of a wafer and a thin film in a conventional semiconductor device while forming the thin film on the wafer. First, the thin film is formed in a high-temperature as shown in the top. After the thin film is formed, an ambient temperature of the wafer with the film is lowered to a room temperature, as shown in the middle. Because there is a difference in coefficient of thermal expansion (CTE) between the wafer and the thin film, the difference in CTE causes the wafer to be distorted in a manner to bend towards the thin film, which causes the stress on the thin film and the thin film also becomes distorted as shown in the bottom.

FIG. 2is a layout diagram of wiring layers of RDLs6in a conventional semiconductor device5. The conventional semiconductor device5is a chip. The wiring layers of RDLs6are connected to major power supply lines, such as a power supply voltage line and a ground voltage line. Some other power supply lines (e.g., a partial power supply voltage VDD2, etc.) are also be connected to the wiring layers of RDLs6, but they are thinner than the major power supply lines. When pads24aare arranged along an upper side2aand pads24bare arranged on a lower side2cof the chip5, the wiring layers of RDLs6coupled to the pads24aand24binevitably have an elongated shape extending in a first direction of7aalong sides2band2d, perpendicular to and longer than the sides2aand2cextending in a second direction7b. Thus, the wiring layers of RDLs6supply the power supply voltages from the pads24aand24bto an array of internal elements. Being thick RDLs in an uppermost layer close to the surface of the chip5, the wiring layers of RDLs have stress greater than stresses of internal metal layers (i.e. lower layers made of aluminum or copper etc.) of the chip5. When the wiring layers of RDLs6are elongated in the first direction7a, therefore, the large stress of the wiring layers of RDLs6pull the upper and lower pads24aand24btoward each other. The wafer warps along the first direction7aof the chip5. Even if the chip5is in a square shaper, stress arises in the direction of the uppermost wiring layers of the RDLs, causing the wafer to warp towards the surface of the chip5.

FIG. 3Ais a layout diagram of wiring layers of RDLs with a dicing diagonally rotated in a wafer plane with respect the wiring layer of RDLs in a conventional semiconductor device.FIG. 3Bis a schematic diagram of warpage in the conventional semiconductor device. Dicing the wafer along 45-degree dicing lines as shown inFIG. 3Aresults in the diagonal warpage of the chip as shown inFIG. 3B. Diagonal corners close to longer wiring layers of the RDLs tend to have greater warpages whereas the other two diagonal corners closet to shorter wiring layers of the RDLs tend to have less warpages. The greater diagonal warpage close to the longer wiring layers of the RDLs is caused by stress along the direction of a pattern of RDLs wiring layers and other patterns in the chip not by the chip shape.

FIG. 4Ais a layout diagram of an uppermost wiring layer in a conventional semiconductor device45.FIG. 4Ais a plan view of the uppermost wiring layer of the conventional semiconductor device45. The semiconductor device45may have sides40ato40d. The sides40band40dopposite to each other with respect to the conventional semiconductor device45, extending in a first direction47a. The sides40aand40copposite to each other with respect to the semiconductor device45, extending in a second direction47b, which is perpendicular to the first direction47a. The semiconductor device45including the uppermost wiring layer is a one-channel mobile dynamic random access memory (DRAM). The uppermost wiring layer of the semiconductor device45includes a plurality of pads44, such as power terminals or data terminals, which are arranged in the second direction87balong the side40aextending in the first direction. The uppermost wiring layer of the semiconductor device includes wiring layers461and462made of redistribution layers (e.g., internal redistribution layers (iRDL)) extending along the first direction47ain parallel to the sides40band40d. The wiring layers461is coupled to a power supply wire for providing a power supply voltage VDD from a power pad that receives the power supply voltage VDD. The wiring layers462is coupled to another power supply wire for providing a power supply voltage VSS (e.g., a ground voltage) that is lower than the power supply voltage VDD from another power pad that receives the power supply voltage VSS. The power supply wiring layers461and462for providing the power supply voltage VDD and VSS may have greater thicknesses than other power supply wires (e.g., power supply wire that provides a partial power supply voltage VDD2) that are coupled to another wiring layers of RDLs. The warpage due to the stress along the wiring layers of RDLs461and462extending from the side40ato the side40calong the sides40band40cin the first direction47aare great and non-negligible as explained earlier.FIG. 4Bis a schematic diagram of the uppermost wiring layer in the conventional semiconductor device45.

As described above, the warpage is affected by physical property of the wafer, the aspect ratio of the chip, and the direction of layout patterns. Because the RDLs and a passivation layer made of polyimid (PI) and covering the RDL, both having greater thicknesses extend in the uppermost layer closer to the surface, stress and distortions of the PI layer and the RDL affect greatly to the warpage of a semiconductor device. Thus, a greater thickness of the RDL distorts the chip that is undesirable to reduce the chip size in thickness.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Various embodiments of the present disclosure will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. Other embodiments may be utilized, and structure, logical and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

FIG. 5is a block diagram of a semiconductor device10in accordance with the present disclosure. The semiconductor device10is an apparatus, that may be a synchronous dynamic random-access memory (SDRAM) integrated into a single semiconductor chip (e.g., a semiconductor die), for example. The semiconductor device10may be mounted on an external substrate that is a memory module substrate, a mother board or the like. As shown inFIG. 3, the semiconductor device10includes a memory cell array11. The memory cell array11includes a plurality of banks, each bank including a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word line WL is performed by a row decoder/driver12and the selection of the bit line BL is performed by a column decoder/driver13. Sense amplifiers18are coupled to corresponding bit lines BL and connected to local I/O line pairs LIOT/B. Local IO line pairs LIOT/B are connected to main IO line pairs MIOT/B via transfer gates TG19which function as switches.

Turning to the explanation of a plurality of external terminals included in the semiconductor device10, the plurality of external terminals includes address terminals21, command terminals22, clock terminals23, a clock enable terminal23′, data terminals24, a data strobe terminal24′, power supply terminals25and26. The data terminals24may be coupled to output buffers for read operations of memories. Alternatively, the data terminals24may be coupled to input buffers for read/write access of the memories responsive to a data strobe signal provided at the data strobe terminal24′.FIG. 3shows an example of dynamic random access memory (DRAM), however, any device having external terminals for signal input/output may be included as the external terminals of embodiments of the present disclosure.

The address terminals21are supplied with an address signal ADD and a bank address signal BADD. The address signal ADD and the bank address signal BADD supplied to the address terminals21are transferred via an address input circuit31to an address decoder32. The address decoder32receives the address signal ADD and supplies a decoded row address signal XADD to the row decoder/driver12, and a decoded column address signal YADD to the column decoder/driver13. The address decoder32also receives the bank address signal BADD and supplies the bank address signal BADD to the row decoder/driver12, the column decoder/driver13. In a self-refresh mode, a self-refresh circuit38may provide a row address signal to the row/decoder driver12for self-refresh operation.

The command terminals22are supplied with a command signal COM. The command signal COM may include one or more separate signals. The command signal COM input to the command terminals22is provided to a command decoder34via a command input circuit33. The command decoder34decodes the command signal COM and provides the decoded command, and an internal control signal generator37may generate various internal command signals responsive to the decoded command from the command decoder34. For example, the internal commands may include a row command signal to select a word line and a column command signal, such as a read command or a write command, to select a bit line.

Accordingly, when a read command is issued and a row address and a column address are timely supplied with the read command, read data is read from a memory cell MC in the memory cell array1designated by these row address and column address. The read data DQ is output externally from the data terminals24via a read/write amplifier15and an input/output circuit17. Similarly, when the write command is issued and a row address and a column address are timely supplied with this command, and then write data DQ is supplied to the data terminals24, the write data DQ is supplied via the input/output circuit17and the read/write amplifier15to the memory cell array11and written in the memory cell MC designated by the row address and the column address.

The clock terminals23are supplied with external clock signals CK and /CK, respectively. These external clock signals CK and /CK are complementary to each other and are supplied to a clock input circuit35with a clock enable signal CKE received at the clock enable terminal23′. The clock input circuit35receives the external clock signals CK and /CK and the clock enable signal CKE and generates an internal clock signal ICLK. The internal clock signal ICLK is supplied to an internal clock and timing generator36and thus a phase controlled internal clock signal LCLK is generated based on the received internal clock signal ICLK. Although not limited thereto, a DLL circuit can be used as the internal clock and timing generator36. The phase controlled internal clock signal LCLK is supplied to the input/output circuit17and is used as a timing signal for determining an output timing of the read data DQ. The internal clock and timing generator36may further generate various internal clock signals.

The power supply terminals25are supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS are supplied to a power circuit39. The power circuit39generates various internal potentials VPP, VOD, VARY, VPERI, and the like. The internal potential VPP is mainly used in the row decoder/driver12, the internal potentials VOD and VARY are mainly used in the sense amplifiers18included in the memory cell array11, and the internal potential VPERI is used in many other circuit blocks. The power supply terminals26are supplied with power supply potentials VDDQ and VSSQ. These power supply potentials VDDQ and VSSQ are supplied to the input/output circuit17. The power supply potentials VDDQ and VSSQ may be the same potentials as the power supply potentials VDD and VSS that are supplied to the power supply terminals25, respectively. However, the power supply potentials VDDQ and VSSQ may be used for the input/output circuit17so that power supply noise generated by the input/output circuit17does not propagate to the other circuit blocks.

FIG. 6is a schematic diagram of circuits in metal layers in the semiconductor device in accordance with the present disclosure. For example,FIG. 6may be a sectional view of the circuits in the metal layers around external terminals in the semiconductor device10inFIG. 5. The semiconductor device10may include a semiconductor substrate69, insulating material67that insulates the semiconductor substrate69and a plurality of wiring layers in a multi-level wiring structure on the semiconductor substrate, including first to fifth level wiring layers61to65and a passivation layer66. Each layer of the first to fourth level wiring layers61to64may include a metal layer to form conductive wirings and an interlayer insulating film as an insulator to isolate the metal layer from metal layers of other wiring layers. A circuit component in the metal layer and another component in the metal layer of another wiring layer may be coupled by a contact plug and/or conductive via. The input/output circuit17inFIG. 5between data terminals24(e.g., DQ and DM pads) and the memory cell array11may be provided through the first to fourth level wiring layers61to64.

Table 1 shows examples of materials and thicknesses of wiring layers.

For example, a gate67a, typically made of a polycrystalline silicon layer of transistors in the input/output circuit17may be disposed in the insulating material67, and source/drain diffusions (a source or drain region)67bof the transistors may be disposed in the semiconductor substrate69. One of the source/drain diffusions67bmay be coupled to a circuit component made of a high conductivity metal layer (Metal1, of a high conductivity material, such as Copper)62ain the second level wiring layer62via a component of a low conductivity metal layer (Metal0, of a low conductivity material, such as Tungsten)61aand a conductive plug (not shown). The circuit component in the metal layer (Metal1)62amay be coupled to a conductor made of the metal layer (Metal0)61a. The metal layer (Metal0)61ais typically very thin with high impedance, such as Tungsten, that is disposed in the first level wiring layer61via another contact plug (not shown). A first interlayer insulating film61bmay be a cap layer (e.g., Cpoly, an upper layer of cylinder cap) that covers a conductor (e.g. a wiring layer or a circuit component) made of the metal layer (Metal0)61a. A second interlayer insulating film62bmay cover a conductor (e.g. a wiring layer or a circuit component) made of the metal layer (Metal1)62a. A third interlayer insulating film63bmay cover a conductor (e.g. a wiring layer or a circuit component) made of the metal layer (Metal2)63a. For example, the metal layer (Metal2)63amay be made of a mid-level conductive material, such as aluminum with a thickness of approximately 0.3 um. A fourth interlayer insulating film64bmay cover a conductor (e.g., a wiring layer or a circuit component) made of the metal layer (Metal3)64a. For example, the metal layer (Metal3)64amay be made of a mid-level conductive material, such as aluminum with a thickness of approximately 0.7 um. The source or drain region67bof the transistor in the input/output circuit17in the semiconductor substrate69may be coupled to the conductor (e.g., the wiring layer or the circuit component)64ain the fourth level wiring layer64through the first to fourth level wiring layers61to64via contact plugs (not shown).

The fourth level wiring layer64may include the fourth interlayer insulating film64b, typically very thick, covering the metal layer (Metal3)64a. The fifth level wiring layer65may be made of a redistribution layer (e.g., an internal redistribution layer (iRDL))65athat is an uppermost wiring layer (e.g., an uppermost metal layer) formed on the interlayer insulating film at the fourth level wiring layer64. For example, the redistribution layer65amay be made of a mid-level conductive material, such as aluminum with a thickness of approximately 4.6 um. For example, a conductor made of the redistribution layer65amay have greater width and thickness than these of the other metal layers61a,62a,63aand64ain order to reduce impedance of the conductor. Thus the redistribution layer65amay reduce the impedance of circuits and wiring layers in the semiconductor device10that are coupled to the external terminals24. For example, a pad (e.g., the data terminal24) may be disposed on the conductor made of the redistribution layer65a, surrounded by a passivation layer66made of polyimide (PI).

FIG. 7Ais a layout diagram of example memory banks and circuit regions of a memory device75in the semiconductor device10in accordance with an embodiment of the present disclosure. The memory device75may be a memory cell array11inFIG. 5, including sides70band70dextending in a first direction77aand70aand70cextending in a second direction77b. Some metal layers (e.g., the metal layers Metal162aand Metal364a) may extend in the second direction77band some metal layers (e.g., the metal layer Metal263a) may extend in the first direction77a. The memory device75may include drivers71, such as wordline drivers, a circuit region BFLAYG79a(e.g., a FLAY region including logic circuits), memory banks (e.g., B0, B1, B2, B3) divided by a data sense amplifier region DSA78ain the first direction77a, a circuit region BFLAYV/GBUSBUF79b(e.g., a FLAY region including logic circuits and global bus buffers GBUSBUF), memory banks (e.g., B4, B5,86, B7), divided by a data sense amplifier region DSA78bin the first direction77a.FIG. 7Bis a schematic diagram of a portion of circuits in the circuit regions in the memory device75in accordance with an embodiment of the present disclosure. For example, the drivers71may provide segment masking information signals of six bits, SegMsk<5:0> to a buffer BUF790ain the FLAYG region79a. The buffer BUF790amay divide the segment masking information signals SegMsk <5:0> into two 3-bits signals SegMsk<2:0> and SegMsk<5:3> and may provide the segment masking information signals SegMsk<2:0> and SegMsk<5:3> to buffers BUF791aand792a, respectively. The buffer BUF790amay provide the segment masking information signals SegMsk <5:0> to a buffer BUF(DSA)780athat is a data sense amplifier (DSA) which provides the received the segment masking information signals SegMsk <5:0> to a buffer BUF790bin the FLAYV region79b. The buffer BUF790bmay divide the segment masking information signals SegMsk <5:0> into two 3-bits signals SegMsk<2:0> and SegMsk<5:3> and may provide the segment masking information signals SegMsk<2:0> and SegMsk<5:3> to buffers BUF791band792b, respectively.

FIG. 8Ais a layout diagram of an uppermost wiring layer85in the semiconductor device10in accordance with an embodiment of the present disclosure. For example,FIG. 8Amay be a plan view of an uppermost wiring layer85(e.g., the fifth level wiring layer65) of the semiconductor device10. The semiconductor device10may have sides80ato80d. The sides80band80dopposite to each other with respect to the uppermost wiring layer85, extending in a first direction87a. The sides80aand80copposite to each other with respect to the uppermost wiring layer85, extending in a second direction87b, which is perpendicular to the first direction87a. The uppermost wiring layer85may include wiring layers made of a redistribution layer (e.g., an internal redistribution layer (iRDL)) extending along a first direction87ain parallel to the sides80band80d. For example, the semiconductor device10including the uppermost wiring layer85may be a one-channel mobile dynamic random access memory (DRAM). Thus the uppermost wiring layer85may include a plurality of pads84(e.g., the external terminals24) that are arranged in the second direction87balong the side80. Alternatively, if the semiconductor device10is a two-channel mobile memory, which may include the plurality of pads84arranged in the second direction87balong the sides80aand80cextending in the second direction87bin parallel.

The wiring layers made of the redistribution layer in the uppermost wiring layer85may include wiring layers861ato861dand wiring layers862ato862d. The wiring layers861ato861dmay provide a power supply voltage VDD from a power pad84that receives the power supply voltage VDD. The wiring layers862ato862dmay provide a power supply voltage VSS (e.g., a ground voltage) that is lower than the power supply voltage VDD from another power pad84that receives the power supply voltage VSS. The wiring layers861ato861dand862ato862dfor providing the power supply voltage VDD and VSS may have greater thicknesses than other power supply wires (e.g., power supply wire that provides a partial power supply voltage VDD2) that may be coupled to another wiring layers of RDLs.

The wiring layer861amay be coupled (e.g., interconnected) to the wiring layer861bvia one of lower metal layers, the metal layer (Metal3)64a, the metal layer (Metal1)63a, the metal layer (Metal1)62a, different from the RDL in the uppermost wiring layer, in a cut portion88aover an amplifier (AMP) region. The wiring layer861bmay be coupled to the wiring layer861cvia one of the lower metal layers in a cut portion89over a FLAY region and the wiring layer861cmay be coupled to the wiring layer861dvia one of the lower metal layers in a cut portion88bover an AMP region. Thus, voltages, such as the power supply voltages VDD and VSS may be provided to amplifiers in the AMP regions88aand88band logic circuits in the FLAY region89via the wiring layers861ato861dand the wiring layers862ato862din the retribution layer. The warpage due to the stress can be reduced and alleviated by dividing the wiring layers. InFIG. 8A, the cut portions where the wiring layers of the RDLs may be coupled via one of the lower metal layers may be included over the AMP region and the FLAY region, however, the cut portions may be included over a region including fuses (FUSE region), a region including decoders (DEC region).

FIG. 8Bis a schematic diagram of the upper most wiring layer85of the semiconductor device in accordance with an embodiment of the present disclosure.FIG. 8Bmay be a side view of the uppermost wiring layer85(e.g., the fifth level wiring layer65) of the semiconductor device10. Because the pad84inFIG. 8Ais coupled to the wiring layers862ato862dto provide the power supply voltage VSS, unlike inFIG. 4Bhaving one wiring layer462to provide the power supply voltage VSS, a total warpage due to distortion of wiring layers862ato862dfrom stress is smaller than a warpage due to distortion of the wiring layer462from stress accumulated through the entire wiring layer462. Thus, by dividing a wiring layer that provides a power supply voltage into a plurality of wiring layers (e.g., the wiring layers862ato862d) by intervening cut portions (e.g., the AMP regions88aand88b, the FLAY region89), the warpage due to the stress can be reduced.

FIG. 9Ais a layout diagram of wiring layers of RDLs in the semiconductor device10in accordance with an embodiment of the present disclosure. For example,FIG. 9Amay be a plan view of an uppermost wiring layer95(e.g., the fifth level wiring layer65) of the semiconductor device10. The semiconductor device10may have sides90ato90d. The sides90band90dopposite to each other with respect to the uppermost wiring layer95, extending in a first direction97abetween the sides90aand90c. The sides90aand90copposite to each other with respect to the uppermost wiring layer95, extending in a second direction97b, which is perpendicular to the first direction97a. The uppermost wiring layer95may include wiring layers made of a redistribution layer (e.g., an internal redistribution layer (iRDL)) extending along a first direction97ain parallel to the sides90band90d. For example, the semiconductor device10including the uppermost wiring layer95may be a one-channel mobile dynamic random access memory (DRAM). Thus the uppermost wiring layer95may include a plurality of pads94(e.g., the external terminals24) that are arranged in the second direction97balong the side90a. Alternatively, if the semiconductor device10is a two-channel mobile memory, which may include the plurality of pads94arranged in the second direction97balong the sides90aand90cextending in the second direction87bin parallel.

The wiring layers of RDLs in the uppermost wiring layer95may include a first group of wiring layers961ato961dand a second group of wiring layers962ato962d. The first group of wiring layers961ato961dmay provide a power supply voltage VDD from a power pad94that receives the power supply voltage VDD. The second group of wiring layers962ato962dmay provide a power supply voltage VSS (e.g., a ground voltage) that is lower than the power supply voltage VDD from another power pad94that receives the power supply voltage VSS. The wiring layers961ato961dand962ato962dfor providing the power supply voltage VDD and VSS may have greater thicknesses than other power supply wiring layers (e.g., power supply wiring layers that provides a partial power supply voltage VDD2) that may be coupled to another wiring layers in the redistribution layer. The first group of wiring layers961ato961dare arranged in line in the first direction97aand the second group of wiring layers962ato962dare arranged in line in the first direction97a.

FIG. 9Bis a layout diagram of a cut portion98coupling the wiring layers of RDLs in the semiconductor device10in accordance with an embodiment of the present disclosure. In an embodiment of the disclosure, the wiring layer961band the wiring layer961care and completely separated. For example, the wiring layer961band the wiring layer961care in the same layer (e.g., the iRDL65a) and the wiring layer961bis apart from the wiring layer961c. The wiring layer961bmay be coupled (e.g., interconnected) to the wiring layer961cthrough one of lower metal layers, the metal layer (Metal3)64a, the metal layer (Metal2)63a, the metal layer (Metal1)62a. A cut portion981is a sub portion of the cut portion98disposed between the wiring layer961band the wiring layer961cviewed from a third direction perpendicular to the first direction97aand the second direction97b. Thus, the wiring layer961band the wiring layer961care separated from each other by the cut portion981. The wiring layer961bmay be coupled to the one lower metal layer through via911bin the cut portion981. The wiring layer961cmay be coupled to the one lower metal layer through via911cin the cut portion981. Similarly, the wiring layer962bmay be coupled (e.g., interconnected) to the wiring layer962cthrough one of lower metal layers, the metal layer (Metal3)64a, the metal layer (Metal2)63a, the metal layer (Metal1)62a. A cut portion982is a sub portion of the cut portion98disposed between the wiring layer962band the wiring layer962cviewed from the third direction. Thus, the wiring layer962band the wiring layer962care separated from each other by the cut portion982. The wiring layer962bmay be coupled to the one lower metal layer through via912bin the cut portion982. The wiring layer962cmay be coupled to the one lower metal layer through via912cin the cut portion982.

Furthermore, a portion of the wiring layer961bmay extend to the cut portion982in the uppermost wiring layer95and coupled to another wiring layer961b, while a portion of the wiring layer962bis coupled to the one lower metal layer through via912b. A portion of the wiring layer962cmay extend to the cut portion981in the uppermost wiring layer95and coupled to another wiring layer962c, while a portion of the wiring layer961cis coupled to the one lower metal layer through via911c.

FIG. 10Ais a layout diagram of wiring layers of RDLs in the semiconductor device10in accordance with an embodiment of the present disclosure. For example,FIG. 10Amay be a plan view of an uppermost wiring layer105(e.g., the fifth level wiring layer65) of the semiconductor device10. The semiconductor device10may have sides100ato100d. The sides100band100dopposite to each other with respect to the uppermost wiring layer105, extending in a first direction107abetween the sides100aand100c. The sides100aand100copposite to each other with respect to the uppermost wiring layer105, extending in a second direction107b, which is perpendicular to the first direction107a. The uppermost wiring layer105may include wiring layers made of a redistribution layer (e.g., an internal redistribution layer (iRDL)) extending along a first direction107ain parallel to the sides100band100d. For example, the semiconductor device10including the uppermost wiring layer105may be a one-channel mobile dynamic random access memory (DRAM). Thus the uppermost wiring layer105may include a plurality of pads104(e.g., the external terminals24) that are arranged in the second direction107balong the side100a. Alternatively, if the semiconductor device10may be a two-channel mobile memory, which may include the plurality of pads104arranged in the second direction107balong the sides100aand100cextending in the second direction107bin parallel.

The wiring layers of RDLs in the uppermost wiring layer105may include a first group of wiring layers1061ato1061dand a second group of wiring layers1062ato1062d. The first group of wiring layers1061ato1061dmay provide a power supply voltage VDD from a power pad104that receives the power supply voltage VDD. The second group of wiring layers1062ato1062dmay provide a power supply voltage VSS (e.g., a ground voltage) that is lower than the power supply voltage VDD from another power pad104that receives the power supply voltage VSS. The wiring layers1061ato1061dand1062ato1062dfor providing the power supply voltage VDD and VSS may have greater thicknesses than other power supply wiring layers (e.g., power supply wiring layers that provides a partial power supply voltage VDD2) that may be coupled to another wiring layers in the redistribution layer. The first group of wiring layers and the second group of wiring layers are arrange alternately in the first direction. For example, the wiring layers1061a,1062b,1061c, and1062dmay be arranged in the first direction107ain this order. The wiring layers1062a,1061b,1062cand1061dmay be arranged in the first direction107ain this order, in parallel to the wiring layers1061a,1062b,1061c, and1062d. Thus, each group of wiring layers provide a pattern of a non-linear shape and each line includes wiring layers of alternating groups having at least partially alternating polarities.

FIG. 10Bis a layout diagram of a cut portion108coupling the wiring layers of RDLs in the semiconductor device10in accordance with an embodiment of the present disclosure. The wiring layer1061bmay be coupled (e.g., interconnected) to the wiring layer1061cthrough one of lower metal layers, the metal layer (Metal3)64a, the metal layer (Metal2)63a, the metal layer (Metal1)62a. The cut portion108is disposed between the wiring layers1061b,1062band the wiring layer1061c,1062cviewed from a third direction perpendicular to the first direction107aand the second direction107b. Thus, the wiring layer1061band the wiring layer1061care separated from each other by the cut portion108. The wiring layer1061bmay be coupled to the one lower metal layer through via1011bin the cut portion108. The wiring layer1061cmay be coupled to the one lower metal layer through via1011cin the cut portion108. Furthermore, the wiring layer1062band the wiring layer1062cmay be coupled to each other via a bridge1062dof the same RDL with the second group of wiring layers1062band1062cacross lines in the cut portion108in the uppermost wiring layer105. Thus, the second group of wiring layers1062band1062cmay be partially separated across lines, however, the wiring layers1062band1062care still commonly connected to one another by the bridge1062d.

FIG. 11Ais a layout diagram of wiring layers of RDLs in the semiconductor device10in accordance with an embodiment of the present disclosure. Components of an uppermost wiring layer1105may include components similar to the uppermost wiring layer95ofFIG. 9A, and elements previously described are referenced using common last two digits of reference numbers. As such, a detailed description of functionality of components in the uppermost wiring layer1105will not be repeated forFIG. 11in the interest of brevity. The uppermost wiring layer95may further include a cut portion118between the wiring layers1161b,1162band the wiring layers1161cand1162c.FIG. 11Bis a layout diagram of the cut portion118coupling the wiring layers of RDLs in the semiconductor device10in accordance with an embodiment of the present disclosure. The cut portion118may include slits11l3carranged in a direction117bin parallel to an extending direction of sides110aand110cof the uppermost layer115, shorter than sides110band110dextending in a direction117a. The slits1113cmay be between thin wires1111b, having a width less than the width of the first group of wiring layer of RDL161band1161c, that couples the first group of wiring layer of RDL1161band1161c. Similarly, the cut portion118may also include a slit1113barranged with the slits1113cin the direction117b. The slit1113bmay be between thin wires1111c, having a width less than the width of the second group of wiring layer of RDL1162band1162c, coupling the second group of wiring layer of RDL1162band1162c. For example, the slits1113band1113cmay be formed by a passivation layer made of polyimide (PI). Thus, the first group of wiring layers of RDL1161band1161cmay be partially separated and the second group of wiring layers of RDL1162band1162maybe also partially separated. Thus, in the cut portion118, coupling wiring layers of the same RDL may be reduced in width. Thus, each group of wiring layers of a pattern in line between two opposite sides may have several portions partially reduced in width.

Although this invention has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the inventions extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the inventions and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this invention will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the inventions. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying mode of the disclosed invention. Thus, it is intended that the scope of at least some of the present disclosure herein should not be limited by the particular disclosed embodiments described above.