A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

TECHNICAL FIELD

The field relates generally to circuits and methods for generating clock signals, and in particular, circuits and methods for generating clocks signals using high-resolution phase interpolator architectures for digital and mixed signal systems.

BACKGROUND

Clock signal generation is a critical function in many digital and mixed-signal circuits as achieving high performance in such systems often requires a clock with precise phase position. Examples of such systems are phase-locked loops and delay-locked loops, clock and data recovery circuits, time-interleaved analog to digital converters (ADCs) etc. Phase interpolators are often used to generate an output clock with an adjustable phase from two input clock signals. Phase interpolators typically use digital control bits to determine the phase of the output clock that is a weighted sum of the phases of the two input clocks.

Traditionally, interpolators with high phase resolution have been implemented using current mode logic (CML) circuits. In particular, with a standard CML-type interpolator, two input clocks are first pre-conditioned using a slew-rate limiting circuit, and then input to an interpolator core that interpolates the phases of the two slew-rate limited input clock signals. The interpolation between the two slew-rate limited input clock phases is determined by the relative magnitudes of tail currents of the CML circuit, which can be set with current-mode digital to analog converters (DACs). High phase resolution in the interpolation can be achieved in a straightforward manner by employing high-resolution DACs.

A CML phase interpolator is a convenient choice when clock signals in the system are distributed with CML levels. In more recent systems, such as high-speed I/O macros, CMOS (rail-to-rail) clock distribution is employed instead of CML clock distribution, to improve power efficiency. In this case, the use of CML phase interpolators necessitates CMOS-to-CML converters in front of the interpolator, and CML-to-CMOS converters in back of the interpolator. Furthermore, pre-conditioning slew-rate-limiters may also be used to maintain good linearity in the interpolation. The complexity of all these additional circuits increases the circuit costs (e.g., chip area, power), reducing the attractiveness of a CML phase interpolator solution.

For these reasons, it is desirable to have a phase interpolator that directly operates on and produces CMOS rail-to-rail clock signals. A simple CMOS phase interpolator can be implemented by dotting together the outputs of a plurality of CMOS inverters driven by different clock phases. In this circuit implementation, two input clock phases are fed to multiple tri-state inverters of varying strengths, which are turned on or off using n-bit control words. The sum of these control words can be held constant, wherein the output clock phase depends on the relative values of these control words.

Typically, the interpolation linearity achieved with a CMOS interpolator is not as good as the interpolation linearity achieved with a CML phase interpolator, especially if the input phases are relatively widely spaced, such as 90 degrees or more. Furthermore, it is difficult to achieve high phase resolution with CMOS interpolators. Indeed, since the area and power considerations usually limit the number of inverters that can be switched in, the quantization of the resulting interpolation is relatively coarse.

SUMMARY

Exemplary embodiments of the invention generally include circuits and methods for generating clock signals, and in particular, circuits and methods for generating clocks signals using high-resolution phase interpolator techniques for digital and mixed signal systems. Exemplary embodiments of the invention provide phase interpolation circuits and methods that can directly operate on and generate CMOS rail-to-rail clock signals.

In one exemplary embodiment of the invention, a phase interpolator circuit includes an interpolator core that generates an output clock signal by interpolating between a phase of a first input clock signal and a phase of a second input clock signal, wherein the phase of the first input clock signal is earlier than the phase of the second input clock signal. The interpolator core performs interpolation by detecting an arrival of an edge of the first input clock signal and in response to the detecting, by switchably connecting a first current source to an output node to apply a first current that charges a capacitance of the output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator circuit. The interpolator core further performs interpolation by detecting an arrival of an edge of the second input clock signal and in response to the detecting, by switchably connecting a second current source to the output node to apply a second current that charges the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator circuit. The phase interpolator circuit further includes a controller that controls the first current source to generate a first current having a variable magnitude that is selected to adjust a timing at which the capacitance at the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator circuit and thereby adjust a phase shift of the output clock signal output from the voltage comparator circuit.

In another exemplary embodiment of the invention, a phase interpolator circuit includes a first power supply node, a second power supply node, a first output node and a second output node, a voltage comparator circuit, a first current source, a second current source, a first switch circuit, a second switch circuit, a third switch circuit, and a controller. The voltage comparator circuit has a first input terminal connected to the first output node and an output terminal connected to the second output node. The first current source and the second current source are both connected to the first power supply node. The first current source generates a first current and the second current source generates a second current. The first switch circuit is connected between the first current source and the first output node, wherein the first switch circuit is controlled to switchably apply the first current to the first output node and charge a capacitance of the first output node during an interpolation period. The second switch circuit is connected between the second current source and the first output node, wherein the second switch circuit is controlled to switchably apply the second current to the first output node and charge the capacitance of the first output node during the interpolation period. The third switch circuit is connected between the first output node and the second power supply node, wherein the third switch circuit is controlled during a reset period to switchably connect the first output node to the second power supply node and reset a voltage level of the first output node to a voltage level of the second power supply node. The controller controls the first current source to generate a first current having a variable magnitude that is selected to adjust a timing at which the capacitance of the first output node is charged to a voltage level that exceeds a switching threshold of the voltage comparator circuit and thereby adjust a phase shift of an output clock signal output from the voltage comparator circuit.

In yet another exemplary embodiment of the invention, a phase interpolator circuit includes a first interpolation stage and a second interpolation stage. The first interpolation stage includes a first interpolator circuit and a second interpolator circuit. The first and second interpolator circuits each receive as input a first input clock signal and a second input clock signal, wherein the first input clock signal has a phase that is earlier than a phase of the second input clock signal. The first interpolator circuit generates a first output clock signal by interpolating between the phases of the first and second input clock signals, and the second interpolator circuit generates a second output clock signal by interpolating between the phases of the first and second input clock signals. The second interpolation stage receives as input the first and second output clock signals output from the first interpolation stage, and generates a third output clock signal by interpolating between phases of the first and second output clock signals.

In another exemplary embodiment of the invention, a method is provided for generating a clock signal by interpolating between a phase of a first input clock signal and a phase of a second input clock signal, wherein the phase of the first input clock signal is earlier than the phase of the second input clock signal. The method includes detecting an arrival of an edge of the first input clock signal; in response to said detecting, switchably connecting a first current source to an output node to apply a first current to the output node and charge a capacitance of the output node, using only the first current, to a voltage level which is less than or equal to a switching threshold of a voltage comparator circuit; detecting an arrival of an edge of the second input clock signal; in response to said detecting, switchably connecting a second current source to the output node to apply a second current to the output node and charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator circuit; and controlling the first current source to generate a first current having a variable magnitude that is selected to adjust a timing at which the capacitance on the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator circuit and thereby adjust a phase shift of the output clock signal output from the voltage comparator circuit.

These and other exemplary embodiments of the invention will become apparent from the following detailed description of exemplary embodiments thereof, which is to be read in connection with the accompanying drawings.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary embodiments will now be discussed in further detail with regard to circuits and methods for generating clock signals, and in particular, circuits and methods for generating clocks signals using high-resolution phase interpolator techniques for digital and mixed signal systems. Phase interpolation circuits and methods according to exemplary embodiments of the invention as described below are configured to directly operate on and generate CMOS rail-to-rail clock signals.

For instance,FIG. 1is a schematic diagram of a phase interpolator circuit according to an embodiment of the invention. In particular, as depicted inFIG. 1, a CMOS phase interpolator circuit100comprises a current mode DAC110, an interpolating core120, and a gating signal generator130. The interpolating core120comprises a variable current source121that generates a variable charging current Ilin, a fixed current source122that generates a fixed charging current Imax, a first switch123, a second switch124, a third switch125, an output capacitor126(with capacitance Cout), and an inverter127. The current sources121and122are connected between a first power supply node128and respective switches123and124. The switches123,124and125are connected to an output node Vout(first output node). The output capacitor126is connected between the output node Voutand a second power supply node129(e.g., ground) and the third switch125is connected between the output node Voutand the second power supply node129. The inverter127has an input connected to the (first) output node Voutand an output connected to a second output node (CLK_OUT) of the phase interpolator100.

It is to be noted that in the exemplary embodiment ofFIG. 1(and other embodiments described below), the output capacitor126represents a discrete capacitance or a parasitic capacitance, or both. In particular, in one embodiment, the output capacitance Coutat the output node Voutcan be implemented by using a discrete capacitor element that is physically connected between the output node and the second power supply node. In other embodiments, the output capacitance Coutat the output node Voutcan be implemented by using a total of the parasitic capacitances present on the output node Voutdue to the various components (e.g., input to inverter127) connected to the output node Vout. In other embodiments, the output capacitance Coutat the output node Voutcan be implemented by relying on both a discrete capacitor and the total parasitic capacitance present on the output node Vout, assuming of course that the value of the total parasitic capacitance is essentially not negligible in view of the capacitance value of the discrete capacitor.

In the exemplary embodiment ofFIG. 1(and other embodiments described below), the DAC110and current sources121and122may be implemented using known techniques and circuit architectures. In general, the DAC110can be any circuit that generates a current IREFthat serves as a reference current that is used by the variable current source121to generate a current Ilinin that is proportional to the reference current IREF. The variable current source121may be a current mirror circuit that mirrors the reference current IREFand generates a current proportional (e.g., 1:1) to the reference current IREF. Although the embodiment ofFIG. 1shows a DAC110to generate the reference current IREF, the DAC110can be replaced with any suitable current control circuit (analog or digital) for generating reference currents and controlling the charging currents of variable current sources, without departing from the scope of the appended claims.

The gating signal generator130receives as input four quadrature clock input signals (CLK0, CLK90, CLK180, and CLK270) and optionally an output clock signal (CLK_OUT) output from the inverter127, to produce three gating signals Slin, Smax, Sdisch. A first gating signal Slincontrols the first switch123, a second gating signal Smaxcontrols the second switch124, and a third gating signal Sdischcontrols the third switch125. The gating signals control the charging and discharging of the output capacitor126in accordance with a sequence shown in the timing diagram ofFIG. 2.

More specifically,FIG. 2shows example waveforms that illustrate an operating mode of the phase interpolator ofFIG. 1. InFIG. 2, waveform (a) illustrates a first clock signal CLK0input to the gating signal generator130, waveform (b) illustrates a second clock signal CLK90input to the gating signal generator130, waveform (c) illustrates a third clock signal CLK180input to the gating signal generator130, waveform (d) illustrates a fourth clock signal CLK270input to the gating signal generator130, waveform (e) illustrates a first gating signal Slinthat switchably controls the first switch123, waveform (f) illustrates a second gating signal Smaxthat switchably controls the second switch124, waveform (g) illustrates a third gating signal Sdischthat switchably controls the third switch125, waveform (h) illustrates different output voltage waveforms generated at the output node Voutfor different values of the variable current Ilingenerated by the variable current source121, and waveform (i) illustrates different output clock CLK_OUT waveforms that are generated in response to the different values of the variable current Ilin.

As shown inFIG. 2, in a first quarter cycle (time period from t0to t1), the first switch123is activated (closed) in response to a logic “high” gating signal Slin, while the second and third switches124and125are deactivated (opened) in response to logic “low” gating signals Smaxand Sdisch, respectively. As such, in the first quarter cycle, a variable charging current Ilingenerated by the first current source121is applied to charge the output capacitor126, thereby creating a linearly varying output voltage on the output node Voutat time t1that varies between 0 and Vmid, where Vmidis a voltage level equal to or less than the switching threshold of the downstream inverter127.

This voltage variation is then converted to a time variation in a next half-cycle when the output capacitor126is charged with a fixed current Imax. In particular, in the next half-cycle (time period from t1to t3), the first switch123is deactivated (opened) in response to a logic “low” gating signal Slin, while the second switch124is activated (closed) in response to logic “high” gating signal Smaxand the third switch125remains deactivated (opened) in response to a logic “low” gating signal Sdisch. As such, in the period from t1to t3, the fixed current Imaxgenerated by the second current source122is applied to charge the output capacitor126, wherein the voltage on the output node Voutcrosses the inverter threshold with constant slope.

Next, in a final quarter cycle (time period from t3to t4), the output capacitor126is discharged by deactivating (opening) the second switch124, and activating (closing) the third switch125. In particular, in the time period from t3to t4, the first switch123remains deactivated (opened) in response to a logic “low” gating signal Slin, while the second switch124is deactivated (opened) in response to logic “low” gating signal Smaxand the third switch125is activated (closed) in response to a logic “high” gating signal Sdisch. As such, in the period from t3to t4, neither the variable current Ilinnor the fixed current Imaxis applied to the output capacitor126. Instead, the node Voutis switchably connected to the second power supply node129(e.g., ground in this exemplary embodiment) to discharge the capacitor126and reset the voltage on the output node Vout.

It is to be appreciated that resetting the voltage on the output node Voutto the level of the second supply voltage (e.g., ground in the exemplary embodiment) in every clock cycle eliminates the need for circuitry to set the common-mode of Vout. Since the voltage swing of Voutis close to rail-to-rail, standard, simple CMOS inverters can be employed to produce interpolated clock signals with sharp rising and falling transitions, wherein the output of the phase interpolator (i.e., output of inverter127) is close to rail-to-rail as well. The switches123,124and125are driven by CMOS rail-to-rail signals.

Moreover, the current mode DAC110is responsive to an n-bit digital control signal to control the variable current source121to generate a variable current Ilin, which varies between 0 and Imax. The waveform (h) inFIG. 2shows the voltage on the output node Voutfor a range of values of Ilinfrom 0 to Imax. As shown in waveform (h) ofFIG. 2, when Ilinis at its maximum value (Imax), Voutcrosses Vmidat the instant (time t1) when Slinis asserted logic “low” to deactivate (open) the first switch123and Smaxis asserted logic “high” to activate (close) the second switch124. Thus, when Ilinis at its maximum value (Imax), at time instant t1, the adjustable current source is switched off, and the fixed current Imaxis applied to charge the output capacitance, which drives the output voltage on node Voutabove the threshold of the CMOS inverter127. This implies that the insertion delay of the interpolator100ofFIG. 1is at least one-quarter of the clock period.

As further shown in waveform (h) ofFIG. 2, when Ilinis zero, Voutcrosses Vmidwhen CLK180goes high (at time t2). In other words, for cases where Ilinis near 0, the variable voltage on the output node Voutis near 0V (at the time t1when the fixed current Imaxis applied and the variable current Ilinis disconnected), and there is a maximum delay in driving the output voltage on Voutabove the threshold of a CMOS inverter. For cases where Ilinis raised above 0, the variable voltage on the output node Vout(at time t1) is above 0V and the time instant when Voutcrosses Vmidis shifted earlier (at some earlier time less than t2). The magnitude of the time-shift is directly proportional to Ilin. Thus, the phase interpolator100has a range equal to one-quarter of the clock period. The resolution of interpolation depends on the current resolution of Ilin. A high resolution phase interpolator can be realized if the DAC110has high resolution. The gating signal generator130may comprise combinational logic gates.

FIG. 3is a schematic diagram of a phase interpolator circuit according to another embodiment of the invention. In general,FIG. 3shows a CMOS phase interpolator circuit200which is similar to that ofFIG. 1, but where CMOS level clock signals directly drive an interpolator core. In particular, as depicted inFIG. 3, the CMOS phase interpolator circuit200comprises a current-mode DAC110and an interpolating core220. The current mode DAC110is similar in function as described with reference toFIGS. 1 and 2. The interpolating core220comprises a variable current source121that generates a variable charging current Ilin, a fixed current source122that generates a fixed charging current Imax, a first switch circuit223, a second switch circuit224, a third switch circuit225, an output capacitor126(with capacitance Cout), and an inverter127. The current sources121and122are connected between a first power supply node128and respective switch circuits223and224. The switch circuits223,224and225are connected to an output node Vout(first output node). The output capacitor126is connected between the output node Voutand a second power supply node129(e.g., ground) and the third switch circuit225is connected between the output node Voutand the second power supply node129. The inverter127has an input connected to the (first) output node Voutand an output connected to a second output node (CLK_OUT) of the phase interpolator200.

The exemplary embodiment ofFIG. 3is similar in function to the exemplary embodiment ofFIG. 1except that in the embodiment ofFIG. 3, gating logic is embedded within the interpolator core220wherein gating clocks (clock_early and clock_late) are directly applied to transistors within the switch circuits223,224and225of the interpolator core220. In particular, as shown inFIG. 3, the first switch circuit223comprises serially connected PMOS transistors MP1and MP2, the second switch circuit224comprises PMOS transistor MP3, and the third switch circuit225comprises serially connected NMOS transistors MN1and MN2. The clock_late signal is applied to gate terminals of transistors MP3and MN1of the switch circuits224and225, respectively. Aclock_late(complement of the clock_late signal) is applied to a gate terminal of transistor MP1of the first switch circuit223. The clock_early signal is applied to gate terminals of transistors MP2and MN2of the switch circuits223and225, respectively.

The clock_early andclock_latesignals applied to transistors MP2and MP1of the first switch circuit223implicitly generate a control signal similar to the gating signal SlinofFIG. 1to switchably apply the linearly controlled current Ilinto charge the output capacitor126. Similarly, the clock_early and clock_late signals applied to transistors MN2and MN1implicitly generate a control signal similar to the gating signal SdischofFIG. 1to switchably connect the output voltage node Voutto the second power supply node (e.g., ground) to discharge the output capacitor126and reset the voltage on the output node Voutto “ground” level. The clock_late signal applied to transistor MP3of the second switch circuit224functions as the gate control signal SmaxofFIG. 1to switchably apply the fixed maximum current Imaxto charge the output capacitor126. The clock_early and clock_late andclock_latesignals control the charging and discharging of the output capacitor126in accordance with a sequence shown in the timing diagram ofFIG. 4.

More specifically,FIG. 4shows example waveforms that illustrate an operating mode of the phase interpolator ofFIG. 3. InFIG. 4, waveform (a) illustrates a clock_early signal, waveform (b) illustrates a clock_late signal, waveform (c) illustrates aclock_latesignal and waveform (d) illustrates different output voltage waveforms generated at the output node Vout for different values of the variable current Ilingenerated by the variable current source121. As shown inFIG. 4, the clock_early signal is 90 degrees ahead of theclock_latesignal.

As shown inFIG. 4, in a first quarter cycle (time period from t0to t1), the transistors MP1and MP2of the first switch circuit223are turned on (activated) in response to respective logic “low”clock_lateand clock_early signals, while transistor MP3of the second switch circuit224is turned off (deactivated) in response to a logic “high” clock_late signal, and the third switch circuit225is effectively turned off since the transistor MN2of the third switch circuit225is turned off (deactivated) in response to respective logic “low” clock_early signal. As such, in the first quarter cycle, a variable charging current Ilingenerated by the first current source121is applied to charge the output capacitor126, thereby creating a linearly varying output voltage on the output node Voutat time t1that varies between 0 and Vmid, where Vmidis a voltage level equal to or less than the switching threshold of the downstream inverter127.

This voltage variation is then converted to a time variation in a next half-cycle (time period from t1to t3) when the output capacitor126is charged with a fixed current Imax. In particular, during the next half-cycle (time period from t1to t3), the first switch circuit223is effectively deactivated (open) since the transistor MP1of the first switch circuit223is turned off (deactivated) in response to a logic “high”clock_latesignal, while transistor MP3of the second switch circuit224is turned on (activated) in response to a logic “low” clock_late signal, and the third switch circuit225is effectively turned off since transistor MN1is turned off (deactivated) in response to the clock_late signal being set at a logic “low” level during the time period from t1to t3. As such, in the period from t1to t3, the fixed current Imaxgenerated by the second current source122is applied to charge the output capacitor126, wherein Voutcrosses the inverter threshold with constant slope.

Next, in a final quarter cycle (time period from t3to t4), the output capacitor126is discharged by maintaining the first switch circuit223deactivated (MP2is turned off), by deactivating (opening) the second switch circuit224(MP3is turned off), and by activating (closing) the third switch circuit225(both MN1and MN2are activated). In particular, in the time period from t3to t4, the first switch circuit223remains deactivated (opened) as transistor MP2of the first switch circuit223is turned off (deactivated) in response to a logic “high” clock_early signal. Moreover, transistor MP3of the second switch circuit224is turned off (deactivated) in response to a logic “high” clock_late signal, and transistors MN1and MN2of the third switch circuit225are turned on (activated) in response to respective clock_late and clock_early signals being maintained/asserted at a logic “high” level. As such, in the period from t3to t4, neither the variable current Ilinnor the fixed current Imaxis applied to the output node Vout. Instead, the output node Voutis switchably connected to the second power supply node129(e.g., ground in this exemplary embodiment) to discharge the output capacitor126(more generally, discharge the output capacitance Couton node Vout) and reset the voltage on the output node Voutto a voltage level of the second power supply node in preparation for the arrival of the next falling edge of the clock_early signal. As with the exemplary embodiment ofFIG. 1, the phase resolution of the interpolator200ofFIG. 3is set by the current resolution of the DAC110.

FIG. 5is a schematic diagram of a phase interpolator circuit according to another embodiment of the invention. In general,FIG. 5shows a CMOS phase interpolator circuit300which is similar to that ofFIG. 1, but where a current steering DAC generates bias currents for each of a plurality of charging branches of the phase interpolator. In particular, as depicted inFIG. 5, the CMOS phase interpolator circuit300comprises a current-steering DAC310, an interpolating core320and a gating signal generator330. The interpolating core320comprises a first variable current source121that generates a first variable charging current Ilin1, a second variable current source322that generates a second variable charging current Ilin2, a first switch123, a second switch124, a third switch125, an output capacitor126(with capacitance Cout), and an inverter127. The current sources121and322are connected between a first power supply node128and respective switches123and124. The switches123,124and125are connected to an output node Vout(first output node). The output capacitor126is connected between the output node Voutand a second power supply node129(e.g., ground) and the third switch125is connected between the output node Voutand the second power supply node129. The inverter127has an input connected to the (first) output node Voutand an output connected to a second output node (CLK_OUT) of the phase interpolator300.

In the exemplary embodiment ofFIG. 5, the interpolator core320is similar to the interpolator core120ofFIG. 1except that the second current source122(inFIG. 1) which generates a fixed current Imaxis replaced by the second variable current source322. In the embodiment ofFIG. 5, the current steering DAC310generates control signals I1and I2(reference currents) to control the variable current sources121and322that generate currents Ilin1and Ilin2for each charging branch of the interpolator core320. Depending on the value of an n-bit digital control word input to the current steering DAC310, the current steering DAC310routes its internal current sources to either of its output current branches, wherein for all codes, the sum of I1+I2is equal to some constant, Isum. In one exemplary embodiment, the variable current sources121and322are current mirror circuits that mirror the reference currents I1and I2, respectively, to generate respective currents Ilin1and Ilin2which are proportional (e.g., 1:1) to the reference currents I1and I2. When the currents Ilin1and Ilin2are 1:1 proportional to the reference currents I1and I2, Isumis chosen to equal Imax.

The gating signal generator330receives as input four quadrature clock input signals (CLK0, CLK90, CLK180and CLK270) to produce three gating signals Slin1, Slin2, Sdisch. A first gating signal Slin1controls the first switch123, a second gating signal Slin2controls the second switch124, and a third gating signal Sdischcontrols the third switch125. The gating signals control the charging and discharging of the output capacitor126in accordance with a sequence shown in the timing diagram ofFIG. 6.

More specifically,FIG. 6shows example waveforms that illustrate an operating mode of the phase interpolator ofFIG. 5. InFIG. 6, waveform (a) illustrates a first clock signal CLK0input to the gating signal generator330, waveform (b) illustrates a second clock signal CLK90input to the gating signal generator330, waveform (c) illustrates a third clock signal CLK180input to the gating signal generator330, waveform (d) illustrates a fourth clock signal CLK270input to the gating signal generator330, waveform (e) illustrates a first gating signal Slin1that switchably controls the first switch123, waveform (f) illustrates a second gating signal Slin2that switchably controls the second switch124, waveform (g) illustrates a third gating signal Sdischthat switchably controls the third switch125, and waveform (h) illustrates different output voltage waveforms generated at the output node Voutfor different values of the variable currents Ilin1and Ilin2generated by the variable current sources121and322, respectively.

As shown inFIG. 6, in a first quarter cycle (time period from t0to t1), the first switch123is activated (closed) in response to a logic “high” gating signal Slin1, while the second and third switches124and125are deactivated (opened) in response to logic “low” gating signals Slin2and Sdisch, respectively. As such, in the first quarter cycle, a variable charging current Ilin1generated by the first current source121is applied to charge the output capacitor126, thereby creating a linearly varying output voltage on the output node Voutat time t1that varies between 0 and Vmid, where Vmidis a voltage level equal to or less than the switching threshold of the downstream inverter127.

During the first quarter cycle (time period from t0to t1) the capacitor126is charged only with Ilin1, while in a next half-cycle (time period from t1to t3), both Ilin1and Ilin2are applied to charge the output capacitance Coutof the output node Vout, effectively charging the capacitor126with a total current of Imax. In particular, in the next half-cycle (time period from t1to t3), the first switch123remains activated (closed) in response to a logic “high” gating signal Slin1, the second switch124is also activated (closed) in response to logic “high” gating signal Slin2, and the third switch125remains deactivated (opened) in response to a logic “low” gating signal Sdisch. As such, in the period from t1to t3, a total current Imax=Ilin1+Ilin2is applied to charge the output capacitor126, such that the output voltage on node Voutincreases past the inverter threshold voltage level with a constant slope.

Next, in a final quarter cycle (time period from t3to t4), the output capacitor is discharged by deactivating (opening) the first and second switches123and124and activating (closing) the third switch125. In particular, in the time period from t3to t4, the first and second switches123and124are deactivated (opened) in response to logic “low” gating signals Slin1and Slin2, while the third switch125is activated (closed) in response to a logic “high” gating signal Sdisch. As such, in the period from t3to t4, neither variable current Ilin1nor Ilin2is applied to the output capacitor126. Instead, the node Voutis switchably connected to the second power supply node129(e.g., ground in this exemplary embodiment) to discharge the output capacitor126and reset the voltage on the output node Voutto a voltage level of the second power supply node129in preparation for the arrival of the next rising edge of the gating signal Slin1.

In other exemplary embodiments of the invention, a phase interpolator may be implemented with additional current steering paths in the interpolator core to improve the linearity of the interpolation. For example,FIG. 7is a schematic diagram of a phase interpolator circuit according to another embodiment of the invention, which implements current steering to improve the linearity of the interpolation. More specifically,FIG. 7schematically depicts a phase interpolator400having an interpolator core420that is similar to the interpolator core320of the phase interpolator300ofFIG. 5, except for the inclusion of additional current steering paths P1and P2comprising fourth and fifth switches421and422. The fourth switch421(in path P1) is responsive to a control signalSlin1, which is the complement (inverse) of the control signal Slin1that controls the first switch123. The fifth switch422(in path P2) is responsive to a control signalSlin2, which is the complement (inverse) of the control signal Slin2that controls the second switch124.

In the exemplary embodiment ofFIG. 7, the additional current steering paths P1and P2allow currents from the variable current sources121and322to be steered to the second power supply node129(ground in the example ofFIG. 7) when the control signals Slin1and Slin2have logic levels that deactivate the first and second switches123and124and, thus, turn off the respective current branches in the interpolator core420for charging the output capacitor126. It is to be appreciated that by providing a conduction path for the current sources121and322at all times irrespective of the phase of operation of the interpolator circuit, the transistors that form the current sources121and322are kept in saturation. This improves the linearity of the output clock phase versus control code transfer function by avoiding unwanted surges in the currents Ilin1and Ilin2that would otherwise introduce errors in the interpolation.

In other embodiments of the invention, a separate reset circuit may be implemented to generate a control signal that is used to reset the output node Voutin response to the output clock signal of a phase interpolator circuit. For instance,FIG. 8is a schematic diagram of a phase interpolator circuit according to another embodiment of the invention, which implements self-resetting logic to reset the output node Vout. More specifically,FIG. 8schematically depicts a phase interpolator circuit500that is similar to the phase interpolator circuit300ofFIG. 5with regard to the interpolator core320(with the current steering DAC310not shown inFIG. 8). The phase interpolator circuit500ofFIG. 8further includes a reset logic circuit530that receives the output clock signal CLK_OUT and a subset m of the input clocks to produce the Sdischsignal for resetting Vout. The reset logic circuit530is one exemplary embodiment of the gating signal generator330shown inFIG. 5(or the gating signal generator130shown inFIG. 1), which receives as input a subset of the four quadrature clock input signals (CLK0, CLK90, CLK180, and CLK270) and the output clock signal to produce the gating signal Sdisch.

The reset logic circuit530generates a trigger after the output clock CLK_OUT transitions, which occurs after Vouthas crossed the inverter threshold. Since the phase of the output clock CLK_OUT is determined by the timing of Voutcrossing the inverter threshold, the control code-to-phase transfer function of the interpolator is similar to that of other embodiments discussed above. By allowing the reset to occur as early as the reset circuit permits, more accurate resetting of the output node Voutis possible.

FIG. 9is a schematic diagram of a phase interpolator circuit according to another embodiment of the invention, which implements self-resetting logic to reset the output node Vout. More specifically,FIG. 9schematically depicts a phase interpolator circuit600that is similar to the phase interpolator circuit500ofFIG. 8, but showing an exemplary implementation of the reset logic circuit. In particular, a reset logic circuit630shown inFIG. 9comprises an inverter631, a first rising-edge detector (RED) circuit632, a second RED circuit633and a set-reset (S-R) latch634. The inverter631is connected between the second output node (CLK_OUT) and the input to the RED circuit632. The inverter631inverts the output clock signal CLK_OUT and the RED circuit632receives as input a complementary output clock signal CLK_OUTB. The second RED circuit633receives as input the CLK0signal. The rising edges of the CLK_OUTB and CLK0signals are detected using the RED circuits632and633, respectively. The outputs of the RED circuits632and633are connected to respective S and R inputs of the S-R latch634whose output is the Sdischcontrol signal that controls the third switch125for the interpolator core320. As further shown inFIG. 9, each RED circuit632and633may be implemented by logic circuit640. The logic circuit640comprises a series of inverters641,642, and643, and an AND gate644, the operation of which is readily understood by one of ordinary skill in the art.

The exemplary embodiments of phase interpolator circuits100,200,300,400,500and600described above have a maximum phase adjustment range of a quarter clock cycle. However, many applications require phase interpolators that cover the entire clock cycle (for example, clock recovery circuits that need to accommodate cycle slipping).FIG. 10is a schematic diagram of a phase interpolator circuit according to another embodiment of the invention providing four quadrant operation. In particular,FIG. 10shows a CMOS phase interpolator circuit700comprising a current-steering DAC310, an interpolating core320and a gating signal generator730, which is similar to the phase interpolator circuit300ofFIG. 5. In addition, the phase interpolator circuit700ofFIG. 10includes a quadrant selection circuit740at the front end of the phase interpolator circuit700.

The quadrant selection circuit740receives as input four quadrature clock signals (CLK0, CLK90, CLK180and CLK270), along with a 2-bit SELECT signal that determines the quadrant of operation for the phase interpolator700. Depending on the SELECT signal, the output clocks of the quadrature selection circuit740(CLK_E and CLK_L) may be CLK0and CLK90, or CLK90and CLK180, or CLK180and CLK270, or CLK270and CLK0. CLK_EB and CLK_LB are the complements of CLK_E and CLK_L, respectively. Thus, the output clock phases of CLK_E and CLK_L are separated by a quarter clock cycle, and the interpolator acts upon these clock signals. In some embodiments, these output clocks are input to the gating signal generator730to provide three gating signals Slin1, Slin2, Sdischas shown inFIG. 10. In other embodiments, the output clock phases of quadrature selection circuit740may be directly applied to an interpolator core designed in accordance with the exemplary embodiment ofFIG. 3. The quadrant selection circuit740may be formed of multiplexer circuits, or other combinatorial logic gates.

In other exemplary embodiments of the invention, phase interpolation may be performed in multiple stages.FIG. 11is a block diagram of a phase interpolator circuit according to another embodiment of the invention wherein interpolation is performed in two stages. In particular,FIG. 11depicts a 2-stage phase interpolator800comprising a first phase interpolator802, a second phase interpolator804, and a third phase interpolator806, wherein the phase interpolators802,804and806may be implemented using any one of the exemplary phase interpolator embodiments described herein. The first and second phase interpolators802and804comprise the first stage of the multi-stage interpolator, and both receive as input two clock signals CLK_E and CLK_L that are phase-separated by a quarter clock cycle.

In the exemplary embodiment ofFIG. 11, the phase interpolator circuit802is configured as a 1:1 mixer, implying that an output clock CLK_1of the phase interpolator802has a phase (ignoring insertion delay) that is an average of the input clock phases. In the phase interpolator circuit802, Ilin1=Imax/2, such that the two input clock phases are equally weighted by the interpolator802. Moreover, the phase interpolator circuit804is configured as a 2:1 MUX, which selects either CLK_E or CLK_L based on a control bit, by setting Ilin1either to Imaxor to zero. When Ilin1=Imax, the output clock CLK_2is governed only by the CLK_E signal, and when Ilin1=0, CLK_2is governed only by the CLK_L signal. Using the interpolator804as a 2:1 MUX ensures that the insertion delays of the two paths are equal. Thus, the output signals CLK_1and CLK_2of the respective interpolator circuits802and804are phase-separated by 45 degrees. The clocks CLK_1and CLK_2are input to the third phase interpolator circuit806(having (n−1) control bits), to produce the final output clock, CLK_OUT, with n-bits of phase resolution. In general, an m-stage n-bit phase interpolator may be implemented with (m−1) stages of mixers and multiplexers and a final stage interpolator with [n−(m−1)] bits of resolution. This allows finer resolution in the phase interpolator.

Although the exemplary embodiments ofFIGS. 1,3,5,7,8,9, and10, for example, illustrate the use of an inverter127in the interpolator core for generating the final output clock signal CLK_OUT, it is to be appreciated that any voltage-sensitive comparator circuit may be used for this purpose. For example,FIG. 12is a schematic diagram of a phase interpolator circuit900according to another exemplary embodiment of the invention, which is similar to the phase interpolator circuit100shown inFIG. 1, for example, but wherein an interpolator core920shown inFIG. 12employs a two-input voltage comparator circuit927(in place of the inverter127in the interpolator core120ofFIG. 1). The voltage comparator circuit927has one input that is connected to the output node Voutand a second input that is connected to a reference voltage Vref. The operation of the phase interpolator circuit900ofFIG. 12is similar to the phase interpolator circuit100ofFIG. 1(as discussed with reference to the timing diagram ofFIG. 2), wherein the reference voltage Vrefsets the switching threshold of the voltage comparator circuit927and thereby plays a role similar to the switching threshold of the inverter127.

While the embodiments of the invention as described herein have been shown to have Voutreset to the low supply voltage or ground voltage, the principles of the invention are equally applicable to embodiments where Voutis reset to the high supply voltage. In this case, however the current sources will be of opposite polarity, sinking current instead of sourcing current. Other straightforward modifications and variations of the disclosed embodiments, such as changing NMOS transistors to PMOS types, and vice versa, will be obvious to those skilled in the art. Such modifications and variations do not depart from the spirit and scope of the invention.

Further aspects of the present invention provide phase interpolator circuits which can be utilized in integrated circuit chips with various analog and digital integrated circuitries. In particular, integrated circuit dies can be fabricated having phase interpolator circuits and other semiconductor devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, resistors, capacitors, inductors, etc., forming analog and/or digital circuits. The phase interpolator circuits can be formed upon or within a semiconductor substrate, the die also comprising the substrate. An integrated circuit in accordance with the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of this invention. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.