Analog-to-digital converter, solid-state imaging device including the same, and method of digitizing analog signal

An analog-to-digital converter receives first and second analog signal voltages, and first and second comparison voltages. The first and second comparison voltages decrease by the same fixed inclination from a first reference voltage to below the first signal voltage and from a second reference voltage to below the second signal voltage, respectively. The converter counts cumulatively over first periods to acquire a first result, counts cumulatively over second periods to acquire a second result, and outputs a difference between the first and second results as a digital quantity. Each first period is time required for the first comparison voltage to change from the first reference voltage to the same voltage as the first signal voltage. Each second period is time required for the second comparison voltage to change from the second reference voltage to the same voltage as the second signal voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2008-275566, filed Oct. 27, 2008, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an analog-to-digital converter, a solid-state imaging device including the same, and a method of digitizing analog signal.

2. Description of the Related Art

A means known so far as a system which digitizes a pixel signal in a CMOS image sensor continues counting until a voltage which is generated by a reference voltage generation circuit and changes in the shape of a slope with time reaches a voltage output from a pixel section to digitize a video signal output from the pixel section. Specifically, a difference between the voltage of the video signal output from the pixel section and the reset voltage which is a reference for this video signal is digitized. However, this technique generates thermal noise upon sampling of the potential difference.

Then, the following technique is known in consideration of the above-mentioned problem. First, after digitization of the reset voltage using the voltage output from the reference voltage generation circuit, the video signal is digitized using the voltage output also from the reference voltage generation circuit. Then, the difference between the two digitization results is adopted as the final digitization quantity, i.e., a digital quantity (see W. Yanget et al. and “An Integrated 800×600 CMOS Imaging System” ISSCC Digest of Technical Papers and February, 1999, pp. 304-305). However, since the difference between the digitization results of two times is adopted as the digital quantity, the above-mentioned technique has a fault that the thermal noise generated in the pixel section, the reference voltage generation circuit, and a comparator which are included in a solid-state imaging device is added twice.

BRIEF SUMMARY OF THE INVENTION

According to an aspect of the present invention, there is provided an analog-to-digital converter which

receives a first analog signal voltage and a second analog signal voltage,

receives a first comparison voltage which decreases by a fixed inclination with time from a first reference voltage larger than the first analog signal voltage to a voltage smaller than the first analog signal voltage,

receives a second comparison voltage which decreases by the same inclination as the first comparison voltage with time from a second reference voltage larger than the second analog signal voltage to a voltage smaller than the second analog signal voltage,

counts cumulatively over first periods to acquire a first result, wherein each of the first periods is time required for the first comparison voltage to change from the first reference voltage to the same voltage as the first analog signal voltage,

counts cumulatively over second periods to acquire a second result, wherein each of the second periods is time required for the second comparison voltage to change from the second reference voltage to the same voltage as the second analog signal voltage, and

outputs a difference between the first result and the second result as a digital quantity.

According to another aspect of the present invention, there is provided a solid-state imaging device comprising:

an analog-to-digital converter of claim1;

a pixel section which generates a reset signal as the first analog signal voltage, and generates a video signal as the second analog signal voltage;

a voltage generation circuit which generates the first comparison voltage and the second comparison voltage; and

a controller which instructs the voltage generation circuit to generate the first comparison voltage and the second comparison voltage for each of the reset signal and the video signal multiple times.

According to an aspect of the present invention, there is provided a method of digitizing an analog signal comprising:

reading out a first analog signal;

comparing the first analog signal with a first comparison voltage which decreases by a fixed inclination with time from a first reference voltage larger than a voltage of the first analog signal to a voltage smaller than the voltage of the first analog signal;

counting cumulatively over first periods to acquire a first result, each of the first periods being time required for the first comparison voltage to change from the first reference voltage to the same voltage as the first analog signal;

reading out a second analog signal;

comparing the second analog signal with a second comparison voltage which decreases by the same inclination as the first comparison voltage with time from a second reference voltage larger than a voltage of the second analog signal to a voltage smaller than the voltage of the second analog signal;

counting cumulatively over second periods to acquire a second result, each of the second periods being time required for the second comparison voltage to change from the second reference voltage to the same voltage as the second analog signal; and

outputting a difference between the first result and the second result as a digital quantity.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will now be described with reference to drawings. In the following description, the same components are indicated with the same reference numbers throughout the figures.

First Embodiment

The analog-to-digital converter and solid-state imaging device including the same according to the first embodiment of the present invention will be described with reference toFIG. 1.

FIG. 1illustrates configuration of the solid-state imaging device according to the first embodiment of the present invention. Description will be given using a CMOS image sensor as an example. As shown inFIG. 1, the solid-state imaging device1includes a clock control circuit10(VCOPLL10), serial command input/output section12, serial interface13, video signal processing circuit14(ISP14), data output interface15(DOUT15), reference timing generation circuit16(TG16), sensor driving timing generation circuit17(ST17), ramp wave generation circuit18, sensor core section19, and lens20. The sensor core section19includes an analog-to-digital conversion circuit31(ADC section31) established in the side part of the pixel section30and the pixel section30. The details of each part will now be described.

The VCOPLL10generates an internal clock (hereinafter referred to as the clock signal CLK) of the solid-state imaging device1based on the master clock MCK. The master clock MCK is, for example, the clock signal CLK acquired with a clock (hereinafter referred to as an external clock) provided outside the solid-state imaging device1and used as a reference. The frequency of the internal clock is controlled by the VCOPLL10.

The serial interface13receives control data DATA for operating the overall system of the solid-state imaging device1including the ISP14from the outside. Control data DATA includes, for example, commands and operation timings for operating the whole system. The serial interface13outputs control data received from the outside to the serial command input/output section12.

The serial command input/output section12outputs control data received from the serial interface13to the VCOPLL10, TG16, ISP14, and DOUT15.

The TG16outputs instructions to the ST17and ISP14, and controls the operation of the sensor core section19and ISP14in accordance with control data DATA from the serial command input/output section12. That is, the TG16outputs operation timing instructions to the ISP14which drives video signal processing, and the ST17which controls operation timing of the sensor core section19. Namely, after accumulation of electric charge received by the sensor core section19, the TG16outputs to the ST17instructions regarding the timings for reading of this electric charge, for digitization of the read video signal, and for transmission of this video signal to the ISP14, etc. Further, the TG16outputs to the ISP14the timings for transmission of the video signal from the sensor core section19, and for outputting the video signal to the DOUT15, etc.

The ST17, based on the operation timings output from the TG16, outputs a detection-section reset pulse (signal RESET), and a signal read pulse (signal READ) to the sensor core section19. RESET and READ are digital signals. The ST17outputs instructions regarding the operation timings and the number of times for generating the ramp wave to the ramp wave generation circuit18.

The ramp wave generation circuit18, in accordance with the operation timing output from the ST17, generates the ramp wave and outputs it to the ADC section31. Specifically, the ramp wave generation circuit18outputs the ramp wave several times for each of the video signal read from the sensor core section19and the reset voltage (described later).

The sensor core section19includes pixels arranged in a matrix. In the pixel section30, reset is performed on pixels and the video signals are read from the pixels in accordance with signals RESET and READ, which are output from the ST17. The reset triggers the pixel section30to output a reset level to the ADC section31. The reset level will be described later.

The ADC section31, in accordance with the level of the ramp wave output from the ramp wave generation circuit18, digitizes each of the analog reset voltage and video signal output from the pixel section30, and then outputs a difference between these digital signals. The ADC section31converts the analog reset voltage and video signal into digital quantities of, for example, 1024 levels. As a result, the ADC section31obtains a 10-bit digital signal of the video signal. Then, the obtained digital signal is read from the ADC section31.

The ISP14performs video signal processing on the digital video signal from the sensor core section19in accordance with the timing output from the TG16. The video signal processing includes white balancing, broad dynamic range processing, noise reduction, defective pixel compensation, etc. The ISP14then outputs the digital signal on which video signal processing has been performed to the DOUT15.

The DOUT15outputs the digital signal on which video signal processing has been carried out to the outside of the solid-state imaging device1.

The lens20collects external light, which passes through a color separation filter that separates the light into red, green and blue components, these being presented to the pixel section30.

<Details of Sensor Core Section19>

The sensor core section19will now be described in detail with reference toFIG. 2.FIG. 2is a circuit diagram of the sensor core section19.

As shown, the pixel section30includes pixels40arranged in a matrix. The pixels40are connected to one of the perpendicular signal lines VLIN. In a perpendicular direction, the (m+1) pixels40are provided. Each perpendicular signal line VLIN is connected to a MOS transistor TL and the ADC section31provided for its own. In the following, the perpendicular signal line VLIN1and the pixels40arranged on the first horizontal line which intersects perpendicularly with the perpendicular signal line VLIN will be described.

Each pixel40includes MOS transistors Tb, Tc, Td, and a photodiode PD. The MOS transistor Tc receives signal RESET1from the ST17at its gate, receives voltage VDD (for example, 2.8 V) at its drain, and is connected to the connection node N1at its source. That is, the MOS transistor Tc functions as a reset transistor which generates the reset voltage used as a reference voltage of the video signal read from the photodiode PD. The MOS transistor Td receives signal READ1from the ST17at its gate, is connected to the connection node N1at its drain and to the cathode of the photodiode PD at its source. That is, the MOS transistor Td functions as a signal-electric-charge read transistor. The anode of the photodiode PD is grounded.

The MOS transistor Tb is connected to the connection node N1at its gate, and receives voltage VDD at its drain, and is connected to the perpendicular signal line VLIN1at its source. As a result, the gate of the MOS transistor Tb, the source of the MOS transistor Tc, and the drain of the MOS transistor Td are connected at the connection node N1. The connection node N1is a node for detecting potential. The MOS transistor Tb serves to amplify the video signal.

A signal line which transmits signals RESET1and READ1is respectively connected to the pixels40arranged on the first horizontal line. That is, a signal line is the first horizontal line, and is connected to the pixels40which are connected to one of the perpendicular signals line VLIN1to VLIN (n+1). The same holds true for the second to (m+1)th horizontal lines which intersect perpendicularly with the perpendicular signal line VLIN.

The pixels40arranged on the same column are connected to one of perpendicular signal lines VLIN1to VLIN(n+1) via the source of the MOS transistor Tb. In the following description, when perpendicular signal lines VLIN1to VLIN(n+1) are not distinguished, each of them is only referred to as a perpendicular signal line VLIN, where n is a natural number.

The pixels40in the same row receive the same one of signals RESET1to RESET(m+1), and the same one of signals READ1to READ(m+1), where m is a natural number. In the following description, when signals RESET1to RESET(m+1) and signals READ1to READ(m+1) are not distinguished, they are referred to simply as signals RESET and READ, respectively.

The MOS transistor TL is connected to one end of the perpendicular signal line VLIN at its drain, receives at its gate voltage VLL generated by the voltage generation circuit41, and is grounded at its source. Voltage VLL output from the voltage generation circuit41is applied to the gate of each of all MOS transistors TL each for the perpendicular signal lines VLIN1to VLIN(n+1). MOS transistors TL and Tb constitute a source follower circuit.

Configuration of the ADC section31will now be described in detail. The ADC section31includes a set of a comparator50, counter51, computing element53, and a register52for each perpendicular signal line VLIN. The inverting input of the comparator50is connected to the drain of the MOS transistor TL, and the non-inverting input thereof is connected to the output of the ramp wave generation circuit18. That is, the drain of each MOS transistor TL in the same column and one end of the perpendicular signal line VLIN are connected to the non-inverting input of the comparator50. The comparator50compares the signals input to the inverting input and the non-inverting input, and outputs the comparison result to the counter51.

The counter51receives the comparison result from the comparator50, and the clock signal CLK. The clock signal CLK may be output from the ST17, or output directly from the VCOPLL10. The counter51counts in accordance with the signal from the comparator50and the clock signal CLK. Specifically, the counter51counts in accordance with the clock signal CLK when the output of the comparator50is high, and stops counting when the output is low. The counter51uses the count to measure the time required for the ramp wave to fall from the initial value to the potential of the perpendicular signal line. Then, the counter51outputs the count to the computing element53, and then resets the count up to that time if needed. In cases where 1-bit analog-to-digital conversion is performed in the ADC section31, the counter51counts up to at least 21 (1 being a natural number). For example, when 1=10 bits, the counter51counts up to at least 1024.

The computing element53outputs the count output from the counter51to the register52. Further, the computing element53subtracts the count held in the register52beforehand from the count output from the counter51.

The register52receives the count output from the computing element53. Then, the register52holds the count, and outputs this count to the computing element53. Then, the register52stores the count with the subtraction performed by the computing element53. Then, the digital quantity stored in the register52passes through the ISP14and is output by the operation of this register52. Note that the digital signal transmitted to the ISP14from the register52includes the video signals from the pixels40arranged on one horizontal line which intersects perpendicularly with perpendicular signal lines VLIN1to VLIN(n+1). That is, the registers52collectively transmit to the ISP14the video signals read from the n+1 pixels40arranged on one horizontal line.

Digitization of the analog reset voltage and video signal in the solid-state imaging device according to the first embodiment will now be described with reference toFIGS. 3A and 3B.FIGS. 3A and 3Bare a flowchart showing the flow of digitization of the analog reset signal and video signal by the solid-state imaging device.

First, the ST17instructs the counter51to reset the count. As a result, the counter51sets the count to zero (FIG. 3A, Step S0). Then, the reset signal is read from the pixel section30, and the read reset signal is input to the inverting input of the comparator50(S1). The ramp wave generation circuit18generates the ramp wave for the reset signal to be output to the comparator50. The comparator50compares the ramp wave for the reset signal and the reset signal (S2). The clock signal CLK is output to the counter51from, for example, the ST17(S3). The counter51counts in synchronization with the clock signal CLK (S4). Specifically, when signal EN output from the comparator50is high (S5, YES), the counter51counts up in synchronization with the clock signal CLK (S4). Conversely, when signal EN is low, the counter51stops digitization (analog-to-digital conversion) (S6). Accordingly, the counter51stops the count-up. The ST17determines whether the reset signal has been digitized N times (S7), where N is a natural number.

If it is determined in step S7that the reset signal has not been digitized N times (S7, NO), the processing returns to step S2and repeats the above-mentioned steps. Conversely, if it is determined in step S7that the reset signal has been digitized N times (S7, YES), the ST17instructs the register52to hold the count up to that time held in the counter51(S8). Then, the ST17instructs the counter51to reset the count held thereby to set the counter51to zero (FIG. 3B, S9).

Then, the video signal is read from the pixel section30. The read video signal is input to the inverting input of the comparator50(S10). The ramp wave generation circuit18generates the ramp wave for the video signal to be output to the comparator50. The comparator50compares the ramp wave for the video signal and the video signal (S11). The clock signal CLK is output to the counter51from, for example, the ST17(S12). The counter51counts in synchronization with the clock signal CLK (S13). Specifically, when signal EN output from the comparator50is high (S14, YES), the counter51counts up in synchronization with the clock signal CLK (S13). Conversely, when signal EN is low, the counter51stops the digitization (S15). Accordingly, the counter51stops the count-up. The ST17determines whether the video signal has been digitized N times (S16). If it is determined in step S16that the reset signal has not been digitized N times (S16, NO), the processing returns to step S11and repeats above-mentioned steps. Conversely, if it is determined in step S16that the video signal has been digitized N times, or the number of times of digitization of the video signal and that of the reset signal is the same (S16, YES), the computing element53subtracts the value up to that time held in the register52from the counter51(S17). The register52temporarily holds this subtraction result, and outputs it (S18).

<Operation of Solid-State Imaging Device According to First Embodiment>

Operation by the solid-state imaging device including the ADC section31will now be described with reference toFIG. 4.FIG. 4is a timing chart showing digitization of the analog reset voltage and the voltage of the video signal (hereinafter referred to as the video signal voltage) which are output to the ADC section31from the pixel section30. The vertical axis represents the output of the ramp wave generation circuit18, reset voltage and video signal voltage (in the figure, indicated as an analog-to-digital conversion input voltage) which are output from the pixel section30, clock signal CLK of the VCOPLL10, output from the counter51, and digitized video signal held in the register52. The horizontal axis represents time. The ADC section31converts the difference between the video signal voltage and reset voltage which are output from the pixel section30into 12-bit digital data. Suppose that 10-bit analog-to-digital conversion is performed on the reset voltage or video signal voltage for every output of the ramp wave, output of four times of the ramp wave to each of the reset voltage and video signal voltage will realize 12-bit analog-to-digital conversion. The ramp wave generation circuit18is controlled by the ST17. The ramp wave varies from and to larger and smaller values than the amplitude of the reset voltage and video signal voltage. Specifically, the ramp wave for reset voltage has an amplitude of −a to a [V] with the reset voltage as the basis, and the ramp wave for the video signal voltage has an amplitude of −b to −a[V] with the reset voltage as the basis, b being larger than a.

The inclination of the RAMP and the frequency of the clock signal CLK are always constant for the reset voltage detection and video signal voltage detection. First, at time t0, the reset voltage is read from the pixel section30, and the ramp wave generation circuit18generates the ramp wave. Then, the ADC section31digitizes the reset voltage. Specifically, processing from steps S0to S8described with reference toFIG. 3Ais performed. Then, with reception of the reset command by the counter51from the ST17at time t0, the counter51is reset to zero. The voltage of the output of the ramp wave generation circuit18has amplitude a[V] larger than the reset voltage. For this reason, the comparator50compares the ramp wave input to the non-inverting input thereof with the reset voltage input to the inverting input thereof to output a high signal EN to the counter51. Therefore, the counter51counts up in synchronization with the clock signal CLK. Then, the potential of the ramp wave decreases in the shape of a slope from time t0, and becomes the same as the reset voltage at time t1. When the ramp wave becomes smaller than reset voltage, the comparator50outputs a low signal EN to the counter51. As a result, the counter51stops the count. It is assumed that the counter51at the time of stopping has a count of 20. At time t2, the ramp wave generation circuit18finishes the first sweep, and the voltage of the ramp wave becomes −a[V]. In addition, the clock signal CLK to the counter51stops at time t2. Here, the digitization of the reset voltage is completed.

Also at time t2, the voltage output from the ramp wave generation circuit18is changed to a[V] from −a[V] under control of the ST17. The ramp wave generation circuit18outputs fixed voltage a[V] from time t2to time t3under control of the ST17.

Then, the operation from time t0to time t3(digitization of the analog reset voltage in the period from time t0to time t1) is repeated several times (for example, 3 times). That is, the ramp wave generation circuit18outputs the ramp wave for the reset voltage three times under control of the ST17from time t3to time t11, as in the operation between times t0and t3. That is, the ramp wave generation circuit18carries out the sweep of the ramp wave three times under control of the ST17. The counter51continues the count in accordance with the clock signal CLK during each period until the ramp wave is the same as the reset voltage. The counter51accumulates the count up to that time without resetting it. Specifically, the counter51counts by 20 during each period of times t0to t1, t3to t4, t6to t7, and t9to t10for which the output of the comparator50remains high. As a result, the counter51has a count of 80 at time t10. Note that the ST17issues a command to reset the counter51on the first digitization of the reset voltage, but does not issue it on the following digitization of the reset voltage.

At time t11, the voltage output from the ramp wave generation circuit18is changed to a[V] from −a[V] under control of the ST17. Then, the ramp wave generation circuit18outputs fixed voltage a[V] from time t11to time t13under control of the ST17.

At time t12, the video signal read from the pixel section30under control of the ST17is output to the inverting input of the comparator50. Then, the ST17instructs the register52to output the count of 80 accumulated by the counter51up to that time. As a result, the ADC section31starts digitization of the video signal. Specifically, processing from steps S9to S16described with reference toFIG. 3Bis performed. In addition, the counter51outputs the count accumulated up to that time to the register52, and then resets the count.

At time t13, the ramp wave generation circuit18outputs the voltage which has amplitude a[V] larger than the video signal. For this reason, the comparator50compares the ramp wave input to the non-inverting input thereof with the video signal input to the inverting input thereof to output a high signal EN to the counter51. Therefore, the counter51counts up from zero again in accordance with the clock signal CLK. Then, the potential of the ramp wave starts decreasing from time t13under control of the ST17, and becomes the same as the potential of the video signal at time t14. When the ramp wave becomes smaller than the reset voltage, the comparator50makes signal EN output to the counter51low. As a result, the counter51stops the count. The counter51has a count of 76 at the time of stopping. At time t15, the ramp wave generation circuit18finishes the sweep, and the voltage of the ramp wave becomes −b[V]. In addition, at time t15, the clock signal CLK to the counter51stops.

Also at time t15, the voltage output from the ramp wave generation circuit18is changed to a from −b[V] under control of the ST17. The ramp wave generation circuit18outputs fixed voltage a[V] from time t16to time t17under control of the ST17.

Then, the operation from time t13to time t16(digitization of the analog video signal voltage in the period from time t13to time t14) is repeated several times (for example, three times). That is, the ramp wave generation circuit18outputs the ramp wave for the video signal three times from time t16to time t24as in the operation from time t13to time t16. The counter51continues the count in accordance with the clock signal CLK during each period in which the ramp wave is larger than the video signal voltage. That is, the counter51accumulates the count up to that time without resetting it. Specifically, the counter51counts by 76 during each period of times t13to t14, t16to t17, t19to t20, and t22to t23for which the output of the comparator50remains high. As a result, the counter51outputs the accumulated count of 304 to the computing element53. Note that ST17issues a command to reset the counter51on the first digitization of the video signal, but does not issue it on the following digitization of the video signal.

At time t25, the computing element53subtracts the digital quantity of 80 of the reset voltage held in the register52from the count of 304 output from the counter51, and stores the subtraction result of 224 in the register52. The register52outputs the subtraction result of 224 as the digital quantity of the video signal. Note that the digitization of the reset voltage and video signal voltage using the ramp wave is referred to as a digital double sampling, and execution of four digitizations as in the first embodiment is referred to as quadruplex digital double sampling.

<Advantage According to First Embodiment>

The analog-to-digital converter and solid-state imaging device including the same according to the first embodiment can realize the following advantages.

(1) Noise Characteristics can be Improved.

The advantage according to the first embodiment will be described with reference to a comparative example. As a comparative example, the case where the ramp wave generation circuit18would output the ramp wave once for each of the reset signal and video signal inFIG. 4will be described. That is, operation of the ADC section31according to the comparative example does not have the operation from time t3to time t11and from time t16to time t24inFIG. 4. Also in this case, the ramp wave generation circuit18is controlled by the ST17. In other words, digital double sampling is used as a comparative example.

When components in a solid-state imaging device operate, various forms of noise are generated. Among such noise, that included in the reset voltage and video signal in the solid-state imaging device, and that generated in the ramp wave generation circuit18and in the comparator50may be particularly pronounced. Standard deviation as a result of the digitization of the signal which includes such thermal noise is assumed to be σ [LSB]. Specifically, the counter51counts in accordance with an output from the comparator50, and even if the count should be 10, the variation represented by σ may change the count from 10.

Since the ADC section31according to the comparative example digitizes the reset voltage and video signal once, respectively (or, a total of two times) to calculate a difference between the two results, a component of thermal noise included in the final digitization result is 21/2×σ. This is proportional to the square root of the number of times of digitization because noise components are not correlated. Then, assume that 10-bit analog-to-digital conversion is performed on the reset voltage and video signal voltage for every output of the ramp wave as described above, the digitized difference between the final video signal voltage and reset voltage is a 10-bit digital quantity, which is a quantity having 1024 levels. The signal has a signal-to-noise ratio of 1024/21/2×σ.

In contrast, the analog-to-digital converter and solid-state imaging device including the same according to the first embodiment can reduce the above-mentioned thermal noise and improve the signal-to-noise ratio. This will be described in detail. As mentioned above, in the first embodiment, the ramp wave generation circuit18outputs the same ramp waves four times for each of the reset voltage and video signal voltage. That is, digitization is performed eight times in total. Therefore, the digitized thermal noise generated is 81/2×σ. Assume that 10-bit analog-to-digital conversion is performed for every output of the ramp wave, the final digitization result is a 12-bit digital quantity, which is a quantity having 4096 levels. The components of the thermal noise included in the final digitization result converted to 10 bits are 1024/4096×81/2×σ=21/2×σ/2. It is appreciated that the thermal noise is half the comparative example. That is, σ can be reduced to a half. In other words, the execution of the quadruplex digital double sampling by the ADC section31can reduce the influence of thermal noise. Accordingly, the variation in the count obtained by the counter51can be suppressed.

In addition, the signal-to-noise ratio is 4096/81/2×σ=2048/21/2×σ, and is twice the comparative example.

<Operation of Modified Solid-State Imaging Device According to First Embodiment>

Operation of solid-state imaging device including a modified ADC section31will now be described with reference toFIG. 5.FIG. 5shows quadruplex digital double sampling as inFIG. 4, and it is a timing chart which shows digitization of the reset voltage and the video signal output to the ADC section31from the pixel section30. The vertical axis represents the output of the ramp wave generation circuit18, reset voltage and video signal (shown in the figure as an analog-to-digital conversion input voltage) which are output from the pixel section30, clock signal CLK of the VCOPLL10, output from the counter51, and digitized video signal held in the register52. The horizontal axis represents time. Only operations different from those of the solid-state imaging device described with reference toFIG. 4will be described.

The ADC section31according to the modified first embodiment repeats digitization k times to the reset voltage and video signal voltage to convert a difference between the two signals into an 1-bit digital quantity. The counter51, for every output of the ramp wave, counts to m (m being a natural number) for the reset voltage, and counts to m+21/k for the video signal voltage (k being a natural number). By outputting the ramp wave for each of the reset voltage and video signal voltage which are output from the pixel section30, for example, four times, for conversion of those to 10-bit digital data, the reset voltage is converted into a digital quantity m for one ramp wave output, and the video signal voltage is converted into a digital quantity m+256.

Specifically, the first digitization of the reset voltage is performed from time t0to time t3. As a result, the counter51counts to 5 until time t1when signal EN output from the comparator50is made low. That is, since the ADC section31according to the modified first embodiment obtains a 256-level digital signal by one digitization, the counter51takes one fourth a level of the ADC section31according to the first embodiment. Here, the digitization of the reset voltage is completed.

Then, the operation from time t0to time t3(digitization of the analog reset voltage in the period from time t0to time t1) is repeated several times (for example, three times). That is, the ramp wave generation circuit18outputs the ramp wave of the shape of a slope for the reset voltage three times and repeats digitization of the reset voltage three times from time t3to time t11as the operation from time t0to time t3. That is, the counter51keeps counting in accordance with the clock signal CLK during each period in which the ramp wave is larger than the reset voltage. Then, the counter51accumulates the count up to that time without resetting it. Specifically, the counter51counts by 5 during each period of times t0to t1, t3to t4, t6to t7, and t9to t10for which the output of the comparator51remains high. Then, when the video signal is read from the pixel section30, the counter51outputs the accumulated count of 20 to the register52. Operation of the solid-state imaging device according to the modified first embodiment other than that described above are the same as that of the solid-state imaging device shown inFIG. 4.

The same holds true for the video signal voltage. That is, the first digitization of the video signal is performed from time t13to time t16. As a result, the counter51counts up to 19 until time t14when signal EN output from the comparator50is made low. That is, since the ADC section31according to the modified first embodiment obtains a 256-level digital signal by one digitization as described above, the counter51takes one fourth a level of the ADC section31according to the first embodiment. Here, the digitization of the video signal voltage is completed. Then, the ramp wave generation circuit18outputs the ramp wave for video signal voltage three times under control of the ST17from time t16to time t24as the operation from time t13to time t16described above. Then, the counter51keeps counting up in accordance with the clock signal CLK during each period in which the ramp wave is larger than the video signal voltage. That is, the counter51accumulates the count up to that time without resetting it. Specifically, the counter51counts by 19 during each period of times t13to t14, t16to t17, t19to t20, and t22to t23for which the output of the comparator51remains high. Then, the counter51outputs the accumulated count of 76 to the register52.

At time t25, the register52uses the subtracter to subtract the held digital quantity of 20 of the reset voltage from the count of 76 output from the counter51to obtain digital quantity of 56 of the video signal.

<Advantage According to Modified First Embodiment>

The analog-to-digital converter and solid-state imaging device including the same according to the modified first embodiment can realize not only advantage1, above, but the following advantage.

(2) Processing Speed can be Improved or Power Consumption can be Reduced.

Also in the analog-to-digital converter and solid-state imaging device including the same according to the modified first embodiment, the ramp wave generation circuit18outputs the same ramp wave four times for each of the reset voltage and video signal voltage. That is, a total of eight digitizations are performed. Further, counts of the clock signal CLK in the ADC section31according to the modified first embodiment are smaller than those of the first embodiment and the comparative example. Specifically, the counts by the counter51in one digitization are 5 and 19. Then, the counts obtained as a result of the four digitizations of each of the reset voltage and video signal are 20 and 76, respectively. Therefore, the magnitude of the thermal noise generated by one digitization is a fourth the first embodiment and the comparative example. That is, it is σ/4. Then, since the ADC section31performs eight digitizations in total, the thermal noise is 81/2×σ/4. That is, it is half the comparative example. The signal-to-noise ratio is 1024/(81/2×σ/4)=2048/21/2×σ, and is twice the comparative example. However, this relation holds only in cases where the thermal noise is fully larger than quantizing noise.

Then, the ADC section31according to the modified first embodiment converts the reset voltage and video signal voltage read from the pixel section30to digital quantities of 256 levels per sampling. That is, the clock signal CLK input to the counter51is counted 256 times for every counting operation. Therefore, if the time required for one clock cycle is the same in the ADC sections31in both the modified and unmodified first embodiments, the ADC section31spends less time to digitize each of the reset signal and video signal voltage four times than the first embodiment. Thereby, advantage of increased processing speed can also be obtained.

Further, lengthening the time required for one clock cycle using the VCOPLL and multiplying this clock with the time required for digitization of the reset voltage and video signal voltage may reduce the power consumption of the solid-state imaging device.

Second Embodiment

The analog-to-digital converter and solid-state imaging device including the same according to the second embodiment of the present invention will now be described. Description will be given using a CMOS image sensor as an example. The second embodiment corresponds to the first embodiment with a modified ADC section31shown inFIG. 2of the first embodiment. Only differences from the solid-state imaging device according to the first embodiment will be described with reference toFIG. 6. The same components are indicated with the same reference numbers.

FIG. 6is a block diagram of the ADC section31according to the second embodiment. As shown, the ADC section31does not include the register52and subtraction section53, but includes an up/down counter54instead of the counter51. The comparison result of the comparator50is output to the up/down counter54as signal EN. Then, the up/down counter54outputs a digital quantity of a difference between the reset voltage and video signal voltage. In other words, the up/down counter54also functions as a computing element and a register.

As a different function from the counter51according to the first embodiment, the up/down counter54adopts either a down-count mode or an up-count mode, and either counts up or counts down when signal EN, representing a comparison result from the comparator50, is high.

When, for example, the output of the comparator50on reading the reset voltage is high, the comparator50counts down. Alternatively, when the output from the comparator50on reading of the video signal voltage is high, the comparator50counts up. Because of this operation, the last value of the up/down counter54is equal to a digitized difference between the reset voltage and video signal voltage.

Digitization of the analog reset voltage and video signal by the solid-state imaging device according to the second embodiment will now be described with reference toFIGS. 7A and 7B.FIGS. 7A and 7Bare a flowchart showing the flow of the digitization of the analog signal by the solid-state imaging device.

First, the ST17instructs the up/down counter54to reset the count. As a result, the up/down counter54sets the count to zero (FIG. 7A, step S20). Then, the reset signal is read from the pixel section30, and the read reset signal is input to the inverting input of the comparator50(S21). The ramp wave generation circuit18generates the ramp wave for the reset signal to be output to the comparator50. The comparator50compares the ramp wave for the reset signal and the reset signal (S22). The clock signal CLK is output to the up/down counter54from, for example, the ST17(S23). The up/down counter54functions as a downcounter, and counts down in synchronization with the clock signal CLK (S24). Specifically, when signal EN output from the comparator50is high (S25, YES), the up/down counter54counts down in synchronization with the clock signal CLK (S24). Conversely, when signal EN is low, the up/down counter54stops the digitization (S26). Accordingly, the up/down counter54stops the countdown. The ST17determines whether the reset signal has been digitized N times (S27). If it is determined that the reset signal has not been digitized N times in step S27(S27, NO), the processing returns to step S22and repeats above-mentioned steps. If it is determined that the reset signal has been digitized N times in step S27(S27, YES), the ST17instructs the up/down counter54to hold the count up to that time without resetting it (S28).

Then, the video signal is read from the pixel section30. The read video signal is input to the inverting input of the comparator50(FIG. 7B, S29). The ramp wave generation circuit18generates the ramp wave for the video signal output to the comparator50. The comparator50compares the ramp wave for the video signal and the video signal (S30). The clock signal CLK is output to the up/down counter54from, for example, the ST17(S31). The up/down counter54functions as an upcounter, and counts up in synchronization with the clock signal CLK (S32). Specifically, when signal EN output from the comparator50is high (S33, YES), the up/down counter54counts up in synchronization with the clock signal CLK (S32). Conversely, when signal EN is low, the up/down counter54stops the digitization (S34). Accordingly, the up/down counter54stops the count-up. The ST17determines whether the video signal has been digitized N times (S35). If it is determined in step S35that the video signal has not been digitized N times (S35, NO), the processing returns to step S30and repeats above-mentioned steps. Conversely, if it is determined in step S35that the video signal has been digitized N times (S35, YES), or the number of times of digitization of the video signal and that of the reset signal is the same, the ST17outputs the count counted by the up/down counter54as a digital signal of the video signal (S36).

Operation by the solid-state imaging device including the ADC section31will now be described with reference toFIG. 8.FIG. 8is a timing chart showing four digitizations of each of the analog reset voltage and video signal voltage which are output to the ADC section31from the pixel section30asFIG. 4for the modified first embodiment. The ADC section31according to the second embodiment outputs the ramp wave four times for each of the video signal voltage and reset voltage to convert each voltage into an 8-bit digital quantity. That is, the ADC section31carries out a quadruplex digital double sampling. The vertical axis represents the output of the ramp wave generation circuit18, reset voltage and video signal (indicated in the figure as an analog-to-digital conversion input voltage) which are output from the pixel section30, clock signal CLK of the VCOPLL10, and output from the up/down counter54. The horizontal axis represents time. Only operation of the solid-state imaging device different from that described with reference toFIG. 4will be described in the following.

The solid-state imaging device according to the second embodiment includes the ADC section31described with reference toFIG. 6. When the up/down counter54receives a high signal from the comparator50, it counts up or counts down as required.

As shown, first, at time to, the reset voltage is read from the pixel section30, and the ramp wave generation circuit18generates the ramp wave. Then, the ADC section31digitizes the reset voltage. Specifically, processing from steps S20to S28described with reference toFIG. 7Ais performed. That is, at time t0, the up/down counter54is functioning as a downcounter. After the counter51is reset to zero by reception of the reset command from the ST17, the first digitization is performed from time t0to time t3. As a result, the up/down counter54counts down to −5 until time t1when signal EN output from the comparator50is made low. Here, the digitization of the reset voltage is completed.

Then, the operation from time t0to time t3(digitization of the analog reset voltage in the period from time t0to time t1) is repeated several times (for example, three times). That is, the ramp wave generation circuit18outputs the ramp wave for the reset voltage three times under control of the ST17from time t3to time t11as the operation to time t0to time t3. That is, the ramp wave generation circuit18carries out the sweep of the ramp wave three times under control of the ST17. Then, the up/down counter54keeps counting in accordance with the clock signal CLK during each period until the ramp wave becomes the same as the reset voltage. The up/down counter54accumulates the count up to that time without resetting it. Specifically, the up/down counter54counts down by −5 during each period of times t0to t1, t3to t4, t6to t7, and t9to t10for which the output of the comparator50remains high. As a result, the up/down counter54has a count of −20 at time t10.

Then, the up/down counter54does not reset the count of −20 up to that time and functions as an upcounter for the video signal. Specifically, the up/down counter54uses −20 as an initial value to count up by 19 for every reception of the high signal from the comparator50. In the following, reading of the video signal voltage from the pixel section30under control of the ST17after time t12will be described.

At time t12, the video signal voltage is read from the pixel section30, and the ramp wave generation circuit18generates the ramp wave. Then, the ADC section31digitizes the video signal voltage. Specifically, processing from steps S29to S36described with reference toFIG. 7Bis performed. Namely, the ramp wave starts decreasing from time t13under control of the ST17, and becomes the same as the potential of the video signal at time t14. When the ramp wave becomes smaller than the reset voltage, the comparator50outputs a low signal EN to the up/down counter54. As a result, the up/down counter54stop the count-up. As mentioned above, since the up/down counter54uses −20 as an initial value to count up by 19, the up/down counter54now has a count of −1. Here, the digitization of the video signal voltage by the ADC section31is completed.

Then, the operation from time t13to time t16(digitization of the analog video signal voltage in the period from time t13to time t14) is repeated several times (for example, three times). That is, the ramp wave generation circuit18outputs the ramp wave for the video signal voltage three times from time t16and t24. Then, the up/down counter54continues the count-up in accordance with the clock signal CLK during each period in which the ramp wave is larger than the video signal voltage. That is, the up/down counter54accumulates the count up to that time without resetting it. Specifically, the up/down counter54counts down by 19 during each period of times t13to t14, t16to t17, t19to t20, and t22to t23for which the output of the comparator50remains high. Then, the up/down counter54outputs an accumulated count of 56 as a digital quantity of the video signal. Note that the ADC section31in the solid-state imaging device according to the second embodiment is also applicable to the count of 76 and −20. Description of this application is omitted.

<Advantage According to the Second Embodiment>

The analog-to-digital converter and solid-state imaging device including the same according to the second embodiment can reduce thermal noise and improve the signal-to-noise ratio as well as offer advantages 1 and 2, above. Furthermore, the ADC section31according to the second embodiment does not include the register52and computing element53in the ADC section31of the first embodiment, and uses the up/down counter54instead of the counter51to realize reduction in circuit structure size and simplification of the circuit control.

Note that although the same number of times of the sampling of the reset voltage and video signal voltage by the ADC section31is described, the ramp wave generation circuit18does not necessarily need to output the ramp wave for the reset signal and video signal voltage the same number of times. For example, one output of the ramp wave to the reset voltage and four outputs to the video signal are possible. In this case, the digital signal obtained by the sampling of the reset signal needs to be quadrupled.

The present invention is not limited to the embodiments described herein and can be variously modified at the practical stages as long as it does not deviate from the essence. Embodiments include inventions at various stages, and various inventions can be extracted from appropriate combinations of the components disclosed herein. For example, even if some components are omitted from all the components shown in the embodiments, if the problem indicated herein can be solved and the advantage presented herein can be obtained, the configuration obtained without these components can be extracted as an invention.