Integrated circuit (IC) having IC floorplan silhouette-like power supply net, and sea of supply (SoS) electronic design automation (EDA) tool for designing same

An integrated circuit (IC) having an IC floorplan silhouette-like power supply net, and a computer executable Sea of Supply (SoS) Electronic Design Automation (EDA) tool for automatically designing same. An IC floorplan silhouette-like power supply net preferably includes both a Sea-of-Supply (SoS) power net and a Sea-of-Supply (SoS) ground net each exclusively occupying different layers of the two lowermost metal layers of an interconnect structure overlying its underlying transistor embedded silicon based structure. The SoS nets are the logical complement of preferably all the exempt areas of an IC floorplan.

FIELD OF THE INVENTION

The invention is in the field of Integrated Circuit (IC) design in general, and IC power supply net design in particular.

BACKGROUND OF THE INVENTION

ICs ranging from ASICs to full custom ICs include a transistor embedded silicon based structure, and an interconnect structure with metal layers for power routing purposes, namely, the provision of an IC power supply net, and transistor interconnection purposes. An IC power supply net includes a power net for connection to the power ports (hereinafter denoted “VDDports”) of an IC's power consuming entities (hereinafter denoted “PCEs”), and a ground net for connection to their ground ports (hereinafter denoted “GND ports”). PCEs include full custom macrocells, and standard cell placement areas and, since an IC can have a hierarchically designed structure, a PCE in a non-leaf layer may include lower layer PCEs. IC power routing starts with the provision of an initial IC floorplan with PCEs, and involves determining an IC power supply net physical layout, calculating the widths of the wires making up its power and ground nets, determining slot spread in the wires to satisfy IC fabrication requirements, passing an IC power supply net verification procedure, and if necessary, modifying the IC floorplan and/or the IC power supply net.

SUMMARY OF THE INVENTION

Generally speaking, a computer executable Sea of Supply (SoS) Electronic Design Automation (EDA) tool in accordance with the present invention is programmed to implement a novel methodology for automating the hitherto manual IC power routing design process to yield a so-called IC floorplan silhouette-like power supply net based on the following two principles: First, each net of an IC floorplan silhouette-like power supply net exclusively occupies a single metal layer (hereinafter denoted “supply layer”). And second, any area of a supply layer unoccupied by PCEs, areas reserved for interconnection purposes, and the like, is assigned to be metal filled hence the term “IC floorplan silhouette-like”. By virtue of this logical complement approach, the supply layers assigned for use as an IC floorplan silhouette-like power supply net are entirely occupied by either exempt areas or metal filled areas whereby the former are conceptually islands floating within a so-called Sea-of-Supply power net (hereinafter denoted “SoS power net”) and a so-called Sea-of-Supply ground net (hereinafter denoted “SoS ground net”). Moreover, an IC floorplan silhouette-like power supply net has identical SoS power and ground nets except possibly for the locations of their slots because of IC fabrication reasons.

An IC floorplan silhouette-like power supply net preferably occupies the two lowermost metal layers of an interconnect structure immediately overlying its underlying silicon based structure to minimize the need for vias for connecting PCEs thereto, however, other metal layers which may not necessarily be neighboring may also be equally employed as supply layers. The appearance of a SoS net depends on the degree to which its originating IC floorplan can be compacted taking into account the dimensions of its typically rectangular PCEs and other exempt areas. Highly compact IC floorplans with, say, a 90% area utilization, defined as the combined area of an IC floorplan's exempt areas divided by its total area, lead to SoS nets similar in appearance to conventional manually designed nets. However, a SoS net of a less compact IC floorplan having, say, a 70% area utilization, in all likelihood includes one or more very wide metal wires or more aptly termed metal tracts to convey the fact that they have smaller aspect ratios than metal wires.

To summarize, the present invention facilitates an efficient IC power routing design process by negating the need to manually design a layout, determine slot spread, and the like. Moreover, since the present invention can be readily applied to different IC floorplans having the same exempt areas with minimal manual design effort, an IC layout designer is empowered to conveniently test different IC floorplans to determine the optimal IC floorplan and its inherently rendered IC floorplan silhouette-like power supply net. The present invention also benefits ICs having an IC floorplan silhouette-like power supply net in accordance with the present invention since PCEs can be readily provided with several VDDports and GND ports along their horizontal and vertical edges for connection to a SoS power net and a SoS ground net, respectively, thereby rendering improved port accessibility. Furthermore, an IC having an IC floorplan silhouette-like power supply net enjoys lower noise levels. In this connection, it should be noted that an IC floorplan silhouette-like power supply net in accordance with the present invention may be designed using conventional EDA tools, for example, commercially available inter alia Synopsys, Inc., and Cadence, Inc.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

FIG. 1shows a general purpose computer system1including a processor2, system memory3, non-volatile storage4, a user console6including a keyboard, a mouse, a display, and the like, and a communication interface7. The constitution of each of these elements is well known and accordingly will not be described earlier, and each performs its conventional function as known in the art. In particular, the system memory3and the non-volatile storage4are employed to store a working copy and a permanent copy of the programming instructions implementing the present invention, and to store IC designs. The permanent copy of the programming instructions to practice the present invention may be loaded into the non-volatile storage4in the factory, or in the field, through communication interface7, or through distribution medium8. Any one of a number of recordable medium such as tapes, CD-ROM, DVD and so forth may be employed to store the programming instructions for distribution purposes.

The computer system1is capable of running an Electronic Design Automation (EDA) tool suite11including a Sea of Supply (SoS) Electronic Design Automation (EDA) tool12for automatically designing IC floorplan silhouette-like power supply nets, an IC Power Supply Net Verification tool13for verifying that an IC floorplan silhouette-plan power supply net satisfies predetermined criteria in terms of voltage drop, and electron migration, and possibly other tools14. The SoS EDA tool12includes the following modules:

First, an Input Module16for receiving the following inputs:

(1) An IC floorplan including a multitude of exempt areas including PCEs, and other areas reserved, for example, for interconnection purposes. An IC floorplan is typically provided in a commercially recognized format, for example, DEF, and the like, in which the bottom left hand corner of its boundary is designated the origin (0,0) of an XY coordinate system for specifying locations.

(2) Technical information, for example, the width of a PCE's internal power supply ring, the width of a PCE's save ring, and the like.

(3) An SoS net boundary preferably congruent with the boundary of an IC floorplan, thereby maximizing the size of its inherently rendered SoS nets and reducing the need for any manual power routing design.

(4) The designations of the one or two metal layers assigned as the supply layers for an IC floorplan silhouette-like power supply net. The supply layers are preferably the two lowermost metal layers of an interconnect structure commonly referred to as Metal1and Metal2. Metal1is preferably employed for the SoS ground net of an IC floorplan silhouette-like power supply net because of noise considerations.

(5) A Boolean flag for selectively invoking (Boolean flag=TRUE) a predetermined slot offset to avoid slot registration of slots on neighboring supply layers.

Second, a Save Ring Module17for provisioning save rings around PCEs, each save ring21being constituted by a pair of opposite horizontal save ring regions22co-extensive with a PCE's horizontal edges23, a pair of opposite vertical save ring regions24co-extensive with its vertical edges26, and four square save ring vertices27each at the juncture of a horizontal save ring region and a vertical save ring region (see FIG.2A). Since the preferred direction of electron flow in horizontal save ring regions22and vertical save ring regions24can be predicted with a high degree of certainty, they are initially intended for provisioning with horizontal slots28and vertical slots29, respectively. However, portions of these regions may be designated as non-slotted regions in accordance with non-slotting rules described hereinbelow with respect toFIGS. 2B-2Dwhen the direction of electron flow cannot be predicted with a reasonable degree of certainty. For this reason, save ring vertices27are always designated non-slotted regions (shown by hatching in FIG.2A).

And lastly, a Slot Spread and Orientation Determination (SSOD) Module18for determining slot spread within a SoS net, and slot orientation, namely, horizontal or vertical, in its different regions. The SSOD Module18operates in conjunction with a Design Rule Check (DRC) file19including slot design rules imposed by IC fabrication requirements. One such design rule is the so-called wide wire design rule which stipulates that slots are required when the shortest dimension of a wire exceeds a predetermined value, say, 35 microns in the case of 0.18 micron IC fab technology. Another such design rule is the introduction of an offset between slots on adjacent supply layers to avoid slot registration. For example, if a Metal1slot is located at (X, Y), it is preferable that a Metal2slot in registration therewith be offset to, say, (X+10,Y+10). The SSOD Module18applies the following non-slotting rules:

Rule (1): The inner ring of a save ring surrounding a PCE up to a maximum predetermined width of, say, 35 microns less the width of its internal power supply ring, if it exists, is classified as a non-slotted region. For example, in the case of a PCE with a 15 micron wide internal power supply ring31, and a 100 micron wide save ring21, a 20 micron wide inner ring32of the save ring21is classified as a non-slotted region (shown by hatching in FIG.2B).

Rule (2): The overlap portion of a horizontal save ring region and either a non-slotted region or a vertical save ring region is classified a non-slotted region.FIG. 2Cshows two non-slotted regions33resulting from the overlap between the bottom left hand corner of a save ring21A and the top right hand corner of a save ring21B.FIG. 2Dshows two non-slotted regions34resulting from the overlap between the bottom left hand corner of a save ring21C and the top right hand corner of a save ring21D. The non-slotted regions34are larger than the non-slotted regions33since save rings21C and21D are more overlapping than the save rings21A and21B causing the overlap of horizontal save ring regions and vertical save ring regions in addition to the overlap of horizontal save ring regions and save ring vertices as occurs in FIG.2C.

Rule (3): The same as Rule (2) except in respect of vertical save ring regions. It should be noted that Rules (2) and (3) only become operative in the case of relatively compact IC floorplans and sufficiently wide save rings.

After applying these non-slotting rules, a SoS net includes a patchwork of non-slotted regions, complete horizontal save ring regions and/or portions thereof, complete vertical save ring regions and/or portions thereof, and remaining blank regions which can be equally provisioned with either horizontal or vertical slots without disrupting expected electron flow.

The SSOD Module18executes a minus union algorithm to minimize the size of an IC power supply net file outputted by the SoS EDA tool12. The minus union algorithm involves four steps as follows: First, placing a grid over a SoS net. The grid includes horizontal and vertical grid lines at all abscissas and ordinates at the transitions between non-slotted regions, horizontal save ring regions, and vertical save ring regions. Second, merging contiguous grid rectangles of a SoS net bounded by a pair of adjacent horizontal grid lines to form landscape SoS rectangles defined as having an aspect ratio >1 where an aspect ratio is defined as the width of a SoS rectangle divided by its height. Third, without violating the landscape SoS rectangles, merging contiguous grid rectangles bounded by a pair of adjacent vertical grid lines to form portrait SoS rectangles defined as having an aspect ratio <1. And finally, taking into account the setting of the user set Boolean flag, provisioning horizontal slots to landscape SoS rectangles and vertical slots to portrait SoS rectangles.

FIGS. 3A-3Cillustrate the application of the minus union algorithm to an SoS net36inherently rendered by a side-by-side pair of exempt areas37A and37B.FIG. 3Ashows the horizontal and vertical grid lines placed on the SoS net36.FIG. 3Bshows the merging of contiguous grid rectangles bounded by pairs of adjacent horizontal grid lines to form four landscape SoS rectangles.FIG. 3Cshows the merging of contiguous grid rectangles bounded by pairs of adjacent vertical grid lines to form two portrait SoS rectangles. As shown, the SoS net36can be uniquely described by seven SoS rectangles, namely, five landscape SoS rectangles38and two portrait SoS rectangles39to be respectively provisioned with horizontal slot and vertical slots.

The SoS EDA tool12outputs an IC power supply net file with the XY coordinates of the SoS rectangles of the SoS nets of an IC floorplan silhouette-like power supply net, and their slots.

The operation of the SoS EDA tool12for designing an IC floorplan silhouette-like power supply net for a highly simplified IC floorplan41is now described with reference toFIGS. 4-6.FIG. 5shows that the IC floorplan41has a 10 mm×10 mm floorplan boundary42including two PCEs43and44. The PCE43has a 20 micron wide internal power supply ring37and is assigned a 80 micron wide save ring. The PCE44does not have an internal power supply ring, and is assigned a 60 micron wide save ring.

The Input Module16receives the following inputs: The IC floorplan and the SoS net boundary which is congruent with the former's boundary. The designations that Metal1and Metal2are the supply layers for the SoS ground and power nets, respectively. Boolean flag=TRUE for imposing a (X+10, Y+10) slot offset. The Save Ring Module17determines the XY coordinates of the four save ring vertices46surrounding each of the PCEs43and44. The Save Ring Module17determines the XY coordinates of the 60 micron wide inner rings47surrounding each of the PCEs43and44. The vertices46and the inner rings47are classified as non-slotted regions. The Save Ring Module17determines the XY coordinates of the remaining portions of the two horizontal save ring regions48and the two vertical save ring regions49surrounding each of the PCEs43and44(see FIG.5). The SSOD Module18places the grid over the IC floorplan41and executes the minus union algorithm to yield eight landscape SoS rectangles51and seven portrait SoS rectangles52(see FIG.6). The SSOD Module18assigns horizontal slots to the eight landscape SoS rectangles51, and vertical slots to the seven portrait SoS rectangles52taking into account the slot offset.

The SoS EDA tool12outputs the IC power supply net file including the XY coordinates of the PCEs43and44, the non-slotted regions46and47, the landscape SoS rectangles51and their horizontal slots, and the portrait SoS rectangles52and their vertical slots of the proposed IC floorplan silhouette-like power supply net for the IC floorplan41to the IC Power Supply Design Verification tool13for verification purposes. If the proposed IC floorplan silhouette-like power supply net fails verification, then the IC floorplan is modified, for example, by increasing its size to increase the separation between PCEs, reorganizing the locations of its PCEs, and the like, whereupon the SoS EDA tool12is run on the modified IC floorplan to yield a modified IC floorplan silhouette-like power supply net. This iterative process is repeated until a proposed IC floorplan silhouette-like power supply net passes verification.

While the invention has been described with respect to a limited number of embodiments, it will be appreciated that many variations, modifications, and other applications of the invention can be made within the scope of the appended claims. For example, the present invention can be applied to a single net of an IC power supply net in which case it would preferably be its ground which is more susceptible to noise than its power net.