Non-volatile memory device and method for fabricating the same

A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over a substrate, forming a channel layer that is coupled with a portion of the substrate by penetrating through the stacked structure, forming a slit that penetrates through the second sacrificial layers by selectively etching the stacked structure, removing the second sacrificial layers that are exposed through the slit, forming an epitaxial layer over the channel layer exposed as a result of the removal of the second sacrificial layers, and forming a gate electrode layer filling a space from which the second sacrificial layers are removed, and a memory layer interposed between the gate electrode layer and the epitaxial layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority of Korean Patent Application No. 10-2012-0024075, filed on Mar. 8, 2012, which is incorporated herein by reference in its entirety.

BACKGROUND

Exemplary embodiments of the present invention relate to a non-volatile memory device and a fabrication method thereof, and more particularly, to a non-volatile memory device including a plurality of memory cells that are stacked perpendicularly to a substrate, and a method for fabricating the non-volatile memory device.

2. Description of the Related Art

Non-volatile memory devices retain data stored therein although power is turned off. Diverse non-volatile memory devices, such as NAND-type flash memory devices, are widely used.

As improvement in the integration degree of two-dimensional non-volatile memory devices where memory cells are formed in a single layer over a silicon substrate has come across technical limitation, a three-dimensional non-volatile memory device where a plurality of memory cells are stacked perpendicularly to a silicon substrate is introduced.

The non-volatile memory device includes a plurality of channels that are stretched in a perpendicular direction to the substrate, a plurality of gate electrode layers that are stacked along the channels and insulated from each other by inter-layer dielectric layers, and a memory layer that is interposed between the gate electrode layers and the channels to insulate the gate electrode layers and the channels from each other and stores charges. The memory layer may have a triple-layer structure which includes a charge blocking layer that is disposed on the side of the gate electrode layers, a tunnel insulation layer that is disposed on the side of the channels, and a charge storage layer that is interposed between the charge blocking layer and the tunnel insulation layer.

In order to form the channels expanded in the perpendicular direction and form the memory layer along the channels in the fabrication process of the three-dimensional non-volatile memory device, a Chemical Vapor Deposition (CVD) process or an Atomic Layer Deposition (ALD) process that has excellent step coverage is used. The CVD process or the ALD process, however, may cause defects on the interface between the channels and the tunnel insulation layer, thus deteriorating the electrical characteristics of the non-volatile memory device.

Also, since the channels have a shape of pillars that are stretched in the perpendicular direction and the gate electrode layers and the inter-layer dielectric layers surround the channels, it is impossible to perform an ion implantation process onto the channels to form source/drain regions, just as the conventional two-dimensional non-volatile memory devices are fabricated, and thus, there are some concerns such as the deteriorated interference between neighboring cells and the decreased cell current.

SUMMARY

An embodiment of the present invention is directed to a non-volatile memory device having a three-dimensional structure and improved electrical characteristics, and a method for fabricating the non-volatile memory device.

A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over a substrate; forming a channel layer that is coupled with a portion of the substrate by penetrating through the stacked structure; removing the second sacrificial layers; forming an epitaxial layer over the channel layer exposed by the removal of the second sacrificial layers; and forming a gate electrode layer filling a space from which the second sacrificial layers are removed, and a memory layer interposed between the gate electrode layer and the epitaxial layer.

In accordance with another embodiment of the present invention, a non-volatile memory device includes a stacked structure formed over a substrate and including a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked; a channel layer coupled with a portion of the substrate by penetrating through the stacked structure; an epitaxial layer interposed between the channel layer and the gate electrode; and a memory layer interposed between the epitaxial layer and the gate electrode.

DETAILED DESCRIPTION

Hereafter, a non-volatile memory device and a fabrication method thereof in accordance with an embodiment of the present invention are described with reference toFIGS. 1 to 10.FIGS. 1 to 9are cross-sectional views illustrating a non-volatile memory device and a fabrication method thereof in accordance with an embodiment of the present invention. Particularly,FIG. 9shows the non-volatile memory device, andFIGS. 1 to 8illustrate procedural steps for fabricating the non-volatile memory device ofFIG. 9.FIG. 10is an enlarged view of a C part ofFIG. 9.

Referring toFIG. 1, a substrate10is provided. The substrate10may be formed of a semiconductor material such as monocrystalline silicon, and an insulation layer, which is not illustrated in the drawing, may be formed in the uppermost portion of the substrate10to insulate the substrate10from a gate electrode of a pipe channel transistor, which is to be described later. The gate electrode of a pipe channel transistor is referred to as a pipe gate electrode, hereafter.

Subsequently, a first conductive layer11A for forming a pipe gate electrode is formed over the substrate10, and then a first sacrificial layer12is formed by selectively etching the first conductive layer11A and filling it with an insulation material. The first conductive layer11A may be a polysilicon layer doped with an impurity. The first sacrificial layer12defines a space where a channel of a pipe channel transistor is to be formed. The first sacrificial layer12has a shape of island having a long axis of the cross-sectional direction shown in the drawing, which is referred to as a first direction hereafter, and a short axis of a cross direction to the first direction, which penetrates through the drawing (not shown in drawing). A plurality of first sacrificial layers12are arrayed in the first and second directions. Although the drawing illustrates a case where two first sacrificial layers12are arrayed in the first direction for the sake of convenience in description, the scope and concept of the present invention is not limited to it and multiple first sacrificial layers12may be arrayed in the first direction and the second direction. The first sacrificial layer12may be a nitride layer.

Referring toFIG. 2, a second conductive layer11B for forming a pipe gate electrode is formed over the first conductive layer11A and the first sacrificial layer12. The second conductive layer11B may be a polysilicon layer doped with an impurity. The first conductive layer11A and the second conductive layer11B are collectively referred to as a pipe gate electrode layer11, hereafter.

Subsequently, a plurality of inter-layer dielectric layers13and a plurality of second sacrificial layers14are alternately stacked in a perpendicular direction over the second conductive layer11B. The second sacrificial layers14provide a space where the gate electrodes of memory cells are to be formed, and the second sacrificial layers14may be formed of a material having an etch selectivity from the inter-layer dielectric layers13, such as a nitride. The inter-layer dielectric layers13insulate the gate electrodes of memory cells from each other, and the inter-layer dielectric layers13may be oxide layers.

Referring toFIG. 3, a pair of first channel holes H1that exposes the first sacrificial layer12is formed by selectively etching the second conductive layer11B and the stacked structure where the inter-layer dielectric layers13and the second sacrificial layers14are alternately stacked. A pair of first channel holes H1is disposed in the first direction for each first sacrificial layer12.

Referring toFIG. 4, a protective layer15is formed on the sidewalls of the first channel holes H1, and then second channel holes H2are formed by removing the exposed first sacrificial layer12.

The protective layer15is formed on the sidewalls of the first channel holes H1by depositing a material layer for forming the protective layer15over the substrate structure including the first channel holes H1and then performing a dry etch process to remove a material layer on the bottom of the first channel holes H1and in the upper portion of the stacked structure where the inter-layer dielectric layers13and the second sacrificial layers14are alternately stacked.

The protective layer15protects the second sacrificial layers14from being damaged in the process of removing the first sacrificial layer12when both of the first sacrificial layer12and the second sacrificial layers14are all nitride layers. The protective layer15may be formed of a material having an etch selectivity from the first sacrificial layer12, for example, the protective layer15may be an oxide layer or an amorphous carbon layer. When the first sacrificial layer12and the second sacrificial layers14are formed of materials having different etch selectivities, the process of forming the protective layer15may be omitted. For example, when any one between the first sacrificial layer12and the second sacrificial layers14is a nitride layer, and the other one is formed of an amorphous carbon layer, it might be not required to perform the process of forming the protective layer15.

The first sacrificial layer12may be removed through a wet etch process. When the first sacrificial layer12is a nitride layer, it may be removed through a wet etch process using phosphoric acid.

As a result, the lower ends of the pair of the first channel holes H1are coupled with each other through a second channel hole H2so as to form a U-shaped channel hole H1and H2.

Referring toFIG. 5, the protective layer15is removed through a method such as a wet etch process, and then a gate insulation layer of the pipe channel transistor, which is referred to as a pipe gate insulation layer16, is formed along the internal walls of the U-shaped channel hole H1and H2. Subsequently, a channel layer17is formed over the pipe gate insulation layer16, and the remaining space of the U-shaped channel hole H1and H2is filled with an insulation layer18.

The pipe gate insulation layer16insulates the pipe gate electrode layer11and the channel layer17from each other. The pipe gate insulation layer16may be an oxide layer. As a result of this process, a pipe channel transistor including the pipe gate electrode layer11, the channel layer17, and the pipe gate insulation layer16interposed between the pipe gate electrode layer11and the channel layer17is formed.

The channel layer17is used to form the channels of the pipe channel transistor and the channels of the memory cells. In particular, the channel layer17may be formed of a polycrystalline semiconductor material doped with a high-concentration impurity. Also, the channel layer17may be formed through an Atomic Layer Deposition (ALD) process or a Chemical Vapor Deposition (CVD) process which has excellent step coverage characteristics.

The insulation layer18may be an oxide layer or a nitride layer. In accordance with an embodiment of the present invention, the insulation layer18is formed because the channel layer17is not thick enough to fill all of the U-shaped channel hole H1and H2. Therefore, when the channel layer17fills the U-shaped channel hole H1and H2according to another embodiment of the present invention, the insulation layer18may be not required.

Referring toFIG. 6, a first slit S1and a second slit S2are formed. The first slit S1is disposed between a pair of first channel holes H1that are coupled with each other through one second channel hole H2and penetrates through the stacked structure of the inter-layer dielectric layers13and the second sacrificial layers14. The second slit S2is disposed between neighboring first channel holes H1while not sharing a second channel hole H2and penetrates through the stacked structure of the inter-layer dielectric layers13and the second sacrificial layers14.

The first slit S1separates the gate electrodes of the memory cells in one string in one side and another side of the pair of first channel holes H1. The first slit S1may be stretched in the second direction. Furthermore, the first slit S1provides a space into which a wet etch solution may permeate to remove the second sacrificial layers14. The first slit S1has a thickness penetrate through the stacked structure according to the embodiment of the present invention, but the scope of the present invention is not limited to it and the first slit S1has a thickness that penetrates the lowermost second sacrificial layers14.

The second slit S2separates plural strings from each other. The second slit S2has a similar shape to that of the first slit S1in the embodiment of the present invention, but the scope of the present invention is not limited to it.

Referring toFIG. 7, after the second sacrificial layers14exposed through the first slit S1and the second slit S2is removed, a groove G1is formed to expose the channel layer17by removing a portion of the exposed pipe gate insulation layer16. The second sacrificial layers14and the pipe gate insulation layer16may be removed through a wet etch process.

Referring toFIG. 8, an epitaxial layer19filling a portion of the groove G1is formed over the exposed channel layer17by performing a selective epitaxial growth process. The epitaxial layer19forms a channel along with the channel layer17.

When the epitaxial layer19is formed, a tunnel insulation layer, which is to be formed later, comes to contact the epitaxial layer19instead of the channel layer17, which is formed through the ALD process or the CVD process. As a result, the defect on the interface between the channel and the tunnel insulation layer may be decreased.

Meanwhile, as described above, the channel layer17may be formed of a polycrystalline semiconductor material doped with a high-concentration impurity. In this case, as the selective epitaxial growth process is performed, the impurity of the channel layer17may move to the epitaxial layer19. As a result, the portion of the channel layer17that substantially corresponds to the epitaxial layer19becomes a low-concentration polycrystalline semiconductor (refer to ‘L’ ofFIG. 10), and the other portion of the channel layer17maintains to be a high-concentration polycrystalline semiconductor (refer to ‘H’ ofFIG. 10). Consequently, as the epitaxial layer19is formed, the portion of the channel layer17that corresponds to the gate electrodes of the memory cells, which are to be described later, becomes a low-concentration polycrystalline semiconductor and used as a typical channel region, and the other region of the channel layer17, which is a part between the gate electrodes of the memory cells, remains as a high-concentration polycrystalline semiconductor and used as a source/drain region. In short, a source/drain region may be formed without performing an ion implantation process in accordance with the embodiment of the present invention.

Referring toFIG. 9, a tunnel insulation layer20having a thickness filling a portion of the groove G1is formed over the epitaxial layer19. The tunnel insulation layer20is a layer for the tunneling of charges, and the tunnel insulation layer20may be an oxide layer.

In particular, the tunnel insulation layer20may be formed through a thermal oxidation process. When the tunnel insulation layer20is formed through a thermal oxidation process, the defect on the interface between the epitaxial layer19and the tunnel insulation layer20may be reduced. Furthermore, more impurity of the channel layer17moves to the epitaxial layer19due to the high-temperature process, it is favorable for forming the low-concentration polycrystalline semiconductor (refer to ‘L’ ofFIG. 10) and the high-concentration polycrystalline semiconductor (refer to ‘H’ ofFIG. 10).

Subsequently, a charge storage layer21and a charge blocking layer22are sequentially formed in a thickness that fills a portion of the groove G1over the profile of the substrate structure. The charge storage layer21is a layer for storing charges, and the charge storage layer21may be an insulation layer such as a nitride layer having a charge trapping function. The charge blocking layer22prevents charges from transferring between the charge storage layer21and a third conductive layer, which is to be formed later. The charge blocking layer22may be an oxide layer. The charge storage layer21and the charge blocking layer22may be formed through an ALD process or a CVD process.

Subsequently, a third conductive layer23filling the space inside the groove G1is formed to form the gate electrodes of the memory cells. The third conductive layer23may be formed by forming a conductive material covering the substrate structure including the charge blocking layer22and then performing a blanket etch process until the charge blocking layer22is exposed. The third conductive layer23may be formed of polysilicon doped with an impurity or metal.

As a result of the process, memory cells include the third conductive layer23, the channel layer17and the epitaxial layer19, and the memory layer which includes the tunnel insulation layer20, the charge storage layer21and the charge blocking layer22, interposed between the channels are formed.

Since subsequent processes, which include a process of forming bit lines coupled with the upper end of one side of the channel layer17, and another process for forming source lines coupled with upper end of the other side of the channel layer17, are widely known to those skilled in the art, further description on the subsequent processes is omitted herein.

The non-volatile memory device ofFIGS. 9 and 10is fabricated through the fabrication process described above.

Referring back toFIGS. 9 and 10, the non-volatile memory device in accordance with the embodiment of the present invention includes a plurality of memory cells and a pipe channel transistor. The memory cells include the inter-layer dielectric layers13and the third conductive layers23that are alternately stacked along the channel layers17stretched perpendicularly to the substrate10, and the memory layer interposed between the channel layer17and the third conductive layer23. The memory layer includes the tunnel insulation layer20, the charge storage layer21, and the charge blocking layer22. The pipe channel transistor is disposed under the multiple memory cells and includes the pipe gate electrode layer11, the pipe gate insulation layer16, and the channel layer17interposed between the pipe gate electrode layer11and the pipe gate insulation layer16. The pipe channel transistor may selectively couple a first sub-string with a second sub-string. The first sub-string is formed of memory cells formed along the channel layer17that is formed in one of a pair of first channel holes H1. The second sub-string is formed of memory cells formed along the channel layer17that is formed in the other of the pair of first channel holes H1. The sub-strings of the pair are coupled with each other so as to form one U-shaped string.

The epitaxial layer19is further formed on the sidewall of the channel layer17facing the third conductive layer23. The memory layer is interposed between the epitaxial layer19and the third conductive layer23. Therefore, the interface characteristics between the epitaxial layer19and the tunnel insulation layer20may be improved. Furthermore, since the concentration of the impurity in the portion of the channel layer17corresponding to the epitaxial layer19is lower than the concentration of the impurity in the other portion of the channel layer17, the portion of the channel layer17having relatively low impurity concentration and the other portion of the channel layer17having relatively high impurity concentration may serve as channel regions and source/drain regions, respectively. The tunnel insulation layer20may be a thermal oxide layer, and thus the interface characteristics and source/drain region function may be improved.

Meanwhile, when the channel layer17is formed of a high-concentration polycrystalline semiconductor material in the above-described embodiment of the present invention, it might be not required to form the pipe gate electrode layer11because the pipe channel transistor maintains to be in an ON state regardless of the voltage applied to the pipe gate electrode layer11. In this case, the pipe gate electrode layer11may be substituted with an insulation layer, such as a nitride layer or an oxide layer, or the pipe gate electrode layer11may be formed of the same semiconductor material as the substrate.

Although the embodiment of the present invention describes the three-dimensional non-volatile memory device having a U-shaped string structure with reference toFIGS. 1 to 10, the scope and concept of the present invention are not limited to it. The technology of the present invention may be applied to all three-dimensional non-volatile memory devices where a memory layer and a gate electrode material are formed in the space from which a sacrificial layer is removed. This is described below with reference toFIGS. 11 to 13. Description on a portion that is substantially the same as that of the embodiment is omitted herein.

FIGS. 11 to 13are cross-sectional views illustrating a non-volatile memory device and a fabrication method thereof in accordance with another embodiment of the present invention.

Referring toFIG. 11, a substrate100having a predetermined understructure is provided. The substrate100may be formed of a semiconductor material such as monocrystalline silicon, and a source region (not shown) doped with an impurity, for example, an N-type impurity, may be formed in a portion of the substrate100.

Subsequently, a plurality of inter-layer dielectric layers130and a plurality of sacrificial layers140are alternately stacked over the substrate100in the perpendicular direction.

Subsequently, channel holes that expose a portion of the substrate100are formed by selectively etching the stacked structure where the inter-layer dielectric layers130and the sacrificial layers140are alternately stacked, and a channel layer170is formed by filling the channel holes with a semiconductor material. Particularly, the channel layer170may be formed of a polycrystalline semiconductor material doped with a high-concentration impurity, which is the same as the above-described embodiment.

Referring toFIG. 12, slits S3are formed by selectively etching the stacked structure of the inter-layer dielectric layers130and the sacrificial layers140. Since the slits S3are used to remove the sacrificial layers140, the slits S3is required to have a thickness that penetrates the lowermost sacrificial layers140and the slits S3might be not required to have a shape stretched in the second direction just as the above-described first slits S1do.

Subsequently, grooves G2are formed to expose the channel layer170by removing the sacrificial layers140that are exposed through the slits S3.

Referring toFIG. 13, an epitaxial layer190filling a portion of each groove G2is formed over the exposed channel layer170by performing a selective epitaxial growth process.

Subsequently, a tunnel insulation layer200, a charge storage layer210, and a charge blocking layer220are sequentially formed to fill a portion of each groove G2, and a gate electrode-forming conductive layer230filling the other portion of the groove G2is formed.

This embodiment of the present invention is substantially the same as the embodiment described earlier, except that linear strings where the source regions are disposed in the lower portion and the bit lines are disposed in the upper portion are formed.

The non-volatile memory device and the fabrication method thereof in accordance with an embodiment of the present invention have a three-dimensional structure and improved electrical characteristics.