Method and apparatus for high voltate transistors

A method includes forming a gate spacer along sidewalls of a gate structure, forming a source region and a drain region on opposite sides of the gate structure, wherein a sidewall of the source region is vertically aligned with a first sidewall of the gate spacer, depositing a dielectric layer over the substrate, depositing a conductive layer over the dielectric layer, patterning the dielectric layer and the conductive layer to form a field plate, wherein the dielectric layer comprises a horizontal portion extending from the second drain/source region to a second sidewall of the gate spacer and a vertical portion formed along the second sidewall of the gate spacer, forming a plurality of metal silicide layers by applying a salicide process to the conductive layer, the gate structure, the first drain/source region and the second drain/source region and forming contact plugs over the plurality of metal silicide layers.

BACKGROUND

The semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components. As semiconductor technologies further evolve, metal oxide semiconductor (MOS) transistors have been widely used in today's integrated circuits. MOS transistors are voltage controlled device. When a control voltage is applied to the gate a MOS transistor and the control voltage is greater than the threshold of the MOS transistor, a conductive channel is established between the drain and the source of the MOS transistor. As a result, a current flows between the drain and the source of the MOS transistor. On the other hand, when the control voltage is less than the threshold of the MOS transistor, the MOS transistor is turned off accordingly.

MOS transistors may include two major categories. One is n-channel MOS transistors; the other is p-channel MOS transistors. According to the structure difference, MOS transistors can be further divided into two sub-categories, planar MOS transistors and vertical MOS transistors. As semiconductor technologies further advance, new power MOS devices have emerged to further improve key performance characteristics such as voltage rating, power handling capability and reliability. For example, lateral double diffused MOS transistors are capable of delivering more current per unit area while maintaining a high breakdown voltage. Lateral double diffused MOS transistors may be alternatively referred to as high voltage MOS transistors.

In order to reduce source, drain and gate resistances of high voltage MOS transistors, a salicide process may be employed to form metal silicide contacts on top of the source, drain and gate electrode regions prior to forming contact plugs connected to the source, drain and gate electrode regions respectively. The most common metal silicide materials are nickel silicide and cobalt silicide. In the salicide process, a thin layer of metal is blanket deposited over the semiconductor substrate. In particular, the thin layer of metal is deposited over the exposed source, drain and gate electrode regions. One or more annealing processes may be applied to the thin layer of metal. These annealing processes cause the metal to selectively react with the exposed silicon of the source, drain and gate electrode regions, thereby forming metal silicide layers on top of the source, drain and gate electrode regions respectively. After the metal silicide layers have been formed, the un-reacted metal is removed. In addition, a plurality of contact plugs may be formed over the source, drain and gate electrode regions.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The present disclosure will be described with respect to embodiments in a specific context, a double-diffused metal oxide semiconductor (MOS) transistor. The embodiments of the disclosure may also be applied, however, to a variety of high voltage MOS transistors such as silicon based high voltage transistors, gallium nitride (GaN) based high voltage transistors and the like. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings.

FIG. 1illustrates a cross sectional view of a MOS transistor in accordance with various embodiments of the present disclosure. The MOS transistor100comprises a first drain/source region124, a second drain/source region126and a gate electrode132. As shown inFIG. 1, the gate electrode132is formed over a gate dielectric layer131. The gate electrode132and the gate dielectric layer131form a gate structure130. The first drain/source region124and the second drain/source region are formed on opposite sides of the gate electrode132. A gate spacer133is formed along sidewalls of the gate structure130. A sidewall of the first drain/source region124is vertically aligned with a sidewall of the gate spacer133.

FIG. 1further illustrates the MOS transistor100comprises a field plate136formed between the gate spacer133and the second drain/source region126. In other words, the second drain/source region126and the gate electrode132are separated by the field plate136. As shown inFIG. 1, the field plate136is formed over a dielectric layer134. The field plate136is a conductive field plate comprising a conductive layer and a metal silicide layer over the conductive layer.

The dielectric layer134comprises a first horizontal portion extending from the sidewall of the gate spacer133to the edge of the second drain/source region126, a vertical portion formed along the sidewall of the gate spacer133and a second horizontal portion formed on top of the gate spacer133. It should be noted that the second horizontal portion shown inFIG. 1is merely an example. A person skilled in the art would understand there may be many variations, modifications and alternatives. For example, the second horizontal portion may extend over the edge of the gate spacer133and partially cover the top surface of the gate electrode132.

The MOS transistor100further comprises a body pickup region122formed adjacent to the first drain/source region124. In some embodiments, the MOS transistor100is an n-type MOS transistor. The first drain/source region124is an n-type source region. The second drain/source region126is an n-type drain region. As shown inFIG. 1, both the body pickup region122and the first drain/source region124are formed in a p-type body region112. The second drain/source region126is formed in an n-type doped drain region114. Both the p-type body region112and the n-type doped drain region114are formed in an n-type well108. The n-type well108is formed in a p-type epitaxial layer104, which is grown over a p-type substrate102.

The MOS transistor100further comprises a plurality of isolation regions106formed over the substrate102, an etch stop layer141and an inter-layer dielectric (ILD) layer142formed over the substrate102. As shown inFIG. 1, a plurality of contact plugs152,154,156,158and160are formed in the ILD layer142and connected to the body pickup region122, the first drain/source region124, the gate electrode132, the field plate136and the second drain/source region126respectively. The detailed formation process of the MOS transistor100will be described below with respect toFIGS. 2-14.

In some embodiments, a metal silicide layer is formed on top of the field plate136. The metal silicide layer may be formed by applying a salicide process to an exposed conductive layer such as a poly-silicon layer. More particularly, the metal silicide layer on the field plate136is formed in a same manner as the metal silicide layers over the body pickup region122, the first drain/source region124, the gate electrode132and the second drain/source region126. As such, the contact plug connected to the field plate136can be formed in the same contact fabrication process as the contact plugs connected to the drain, source and gate regions.

One advantageous feature of having a metal silicide layer on the field plate136is that by employing the salicide process, the contact resistance can be reduced; the extra masks for forming the field plate can be saved; and the contact plug connected to the field plate136can be formed during the back-end-of-line metallization process. As a result, the cost of the MOS transistor100can be reduced. In addition, the reliability of the MOS transistor100can be improved.

FIGS. 2-14illustrate cross section views of intermediate steps of fabricating the MOS transistor shown inFIG. 1in accordance with various embodiments of the present disclosure. It should be noted that the fabrication steps shown inFIGS. 2-14are merely an example. A person skilled in the art will recognize there may be many alternatives, variations and modifications. For example, the fabrication steps inFIGS. 2-14provide methods of forming an n-type MOS transistor. One skilled in the art will realize that the fabrication steps may be applicable to forming p-type MOS transistors by inverting the conductivity types of the respective doped semiconductor regions.

FIG. 2illustrates a cross section view of a semiconductor device after an epitaxial layer has been formed over a substrate in accordance with various embodiments of the present disclosure. The semiconductor device100includes a substrate102and an epitaxial layer104over the substrate102. The substrate102is formed of silicon, although it may also be formed of other group III, group IV, and/or group V elements, such as silicon, germanium, gallium, arsenic, and combinations thereof.

As is known to those of skill in the art, the use of dopant atoms in an implant step may form the substrate102with a particular conductivity type. Depending on different applications, the substrate102may be n-type or p-type. In some embodiments, the substrate102is a p-type substrate. Appropriate p-type dopants such as boron, gallium, indium and/or the like are implanted into the substrate102. Alternatively, the substrate102is an n-type substrate. Appropriate n-type dopants such as phosphorous, arsenic and/or the like are implanted into the substrate102. In embodiments shown inFIGS. 2-14, the substrate102is a p-type substrate.

The epitaxial layer104is grown from the substrate102. In some embodiments, the epitaxial layer104is a p-type epitaxial layer grown from the p-type substrate102. The epitaxial growth of the p-type epitaxial layer104may be implemented by using suitable semiconductor fabrication processes such as chemical vapor deposition (CVD), ultra-high vacuum chemical vapor deposition (UHV-CVD) and the like. In accordance with an embodiment, the p-type epitaxial layer104is of a doping density in a range from about 1014/cm3to about1016/cm3.

FIG. 3illustrates a cross section view of the semiconductor device shown inFIG. 2after a plurality of isolation regions have been formed in accordance with various embodiments of the present disclosure. The isolation regions106may be shallow trench isolation (STI) regions, and may be formed by etching the epitaxial layer104to form a plurality of trenches and filling the plurality of trenches with a dielectric material as is known in the art. For example, the isolation regions106may be filled with a dielectric material such as an oxide material, a high-density plasma (HDP) oxide and/or the like. The dielectric materials are formed using suitable semiconductor deposition techniques such as CVD and/or the like.

A planarization process such as a chemical mechanical planarization (CMP) process may be applied to the top surface of the epitaxial layer104so that the excess dielectric material may be removed as a result. In the CMP process, a combination of etching materials and abrading materials are put into contact with the top surface of the epitaxial layer104and a grinding pad (not shown) is used to grind away the excess dielectric material formed on top of the epitaxial layer104until the top surface of the epitaxial layer104is exposed.

FIG. 4illustrates a cross section view of the semiconductor device shown inFIG. 3after an ion implantation process is applied to the semiconductor device in accordance with various embodiments of the present disclosure. A high voltage n-type well region108is formed in the epitaxial layer104through suitable semiconductor doping techniques such as an ion implantation process. In some embodiments, appropriate n-type dopants such as phosphorous, arsenic and/or the like are implanted into the epitaxial layer104to form the high voltage n-type well region108.

In some embodiments, the doping concentration of the high voltage n-type well region108is in a range from about 1×1015/cm3to about 1×1018/cm3. By controlling the ion implantation energy, the depth of the high voltage n-type well region108may be adjusted accordingly.

One skilled in the art will recognize thatFIG. 4illustrates an ideal profile. The dimensions of the high voltage n-type well region108may vary after subsequent fabrication processes.

FIG. 5illustrates a cross section view of the semiconductor device shown inFIG. 4after a p-type body region and an n-type doped drain region have been formed in accordance with various embodiments of the present disclosure. The p-type body region112and the n-type doped drain region114are formed through suitable semiconductor doping techniques such as an ion implantation process. In some embodiments, appropriate p-type dopants such as boron, gallium, indium and/or the like are implanted into the high voltage n-type well region108to form the p-type body region112Likewise, appropriate n-type dopants such as phosphorous, arsenic and/or the like are implanted into the high voltage n-type well region108to form the doped drain region114.

In some embodiments, the doping concentration of the p-type body region112and the n-type doped drain region114is in a range from about 1×1016/cm3to about 1×1019/cm3. By controlling the ion implantation energy, the depths of the p-type body region112and the n-type doped drain region114may be adjusted accordingly.

One skilled in the art will recognize thatFIG. 5illustrates an ideal profile. The dimensions of the p-type body region112and the n-type doped drain region114may vary after subsequent fabrication processes.

FIG. 6illustrates a cross section view of the semiconductor device shown inFIG. 5after a gate dielectric layer is formed over the substrate in accordance with various embodiments of the present disclosure. The gate dielectric layer131is formed on the top surface of the semiconductor device100. The gate dielectric layer131may be formed of a dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, an oxide, a nitrogen-containing oxide, a combination thereof and/or the like. The gate dielectric layer131may have a relative permittivity value greater than about 4. Other examples of such materials include aluminum oxide, lanthanum oxide, hafnium oxide, zirconium oxide, hafnium oxynitride, combinations thereof and/or the like.

In an embodiment in which the gate dielectric layer131comprise an oxide layer, the gate dielectric layer131may be formed by a plasma enhanced CVD (PECVD) process using tetraethoxysilane (TEOS) and oxygen as a precursor. In accordance with an embodiment, the gate dielectric layer131may be of a thickness in a range from about 8 Å to about 200 Å.

FIG. 7illustrates a cross section view of the semiconductor device shown inFIG. 6after a gate electrode is formed over the gate dielectric layers in accordance with various embodiments of the present disclosure. The gate electrode132is deposited over the gate dielectric layer131. The gate electrode132may comprise a conductive material, such as a metal (e.g., tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, tantalum silicide), a metal nitride (e.g., titanium nitride, tantalum nitride), doped poly-crystalline silicon, other conductive materials, combinations thereof and/or the like.

In an embodiment in which the gate electrode132is formed of poly-silicon, the gate electrode132may be formed by depositing doped or undoped poly-silicon by low-pressure chemical vapor deposition (LPCVD) to a thickness in the range from about 400 Å to about 2,400 Å. After the deposition of doped or undoped poly-silicon, an etching process may be employed to define the gate electrode132.

FIG. 8illustrates a cross section view of the semiconductor device shown inFIG. 7after a gate spacer is formed over the substrate in accordance with various embodiments of the present disclosure. The gate spacer133may be formed by blanket depositing one or more spacer layers (not shown) over the semiconductor device100and removing the horizontal portions. The remaining vertical portions of the dielectric layer form the gate spacer133as shown inFIG. 8. The gate spacer133may comprise suitable dielectric materials such as SiN, oxynitride, SiC, SiON, oxide and/or the like.

FIG. 9illustrates a cross section view of the semiconductor device shown inFIG. 8after body pickup and drain/source regions have been formed in accordance with various embodiments of the present disclosure. In accordance with some embodiments, the drain/source regions (e.g., drain/source regions124and126) and body pickup region (e.g., body pickup region122) may be formed by implanting appropriate dopants.

In accordance with some embodiments, appropriate n-type dopants such as phosphorous, arsenic and/or the like are implanted into the p-type body region112and the n-type doped drain region114respectively to form the drain/source regions124and126. The doping density of the drain/source regions (e.g., drain/source region124) is in a range from about 1018/cm3to about 1×1021/cm3.

In accordance with some embodiments, appropriate p-type dopants such as boron, gallium, indium and/or the like are implanted into the p-type body region112to form the p-type body pickup region122. The doping density of the p-type body pickup region122is in a range from about 1018/cm3to about 1×1021/cm3.

FIG. 10illustrates a cross section view of the semiconductor device shown inFIG. 9after the field plate has been formed over the substrate in accordance with various embodiments of the present disclosure. In some embodiments, the field plate136is formed by blanket depositing a dielectric layer and a conductive layer over the semiconductor device100, and performing an etching step to pattern the dielectric layer and the conductive layer to form the field plate136and the dielectric layer134shown inFIG. 10.

The patterning of the dielectric layer and the conductive layer may be performed using a same lithography mask, and hence the edges of the dielectric layer134are aligned to the respective edges of the field plate136as shown inFIG. 10.

In alternative embodiments, the patterning of the dielectric layer and the conductive layer may be performed using different lithography masks, and hence the edges of the dielectric layer134are not aligned to the respective edges of the field plate136. The detailed fabrication steps of forming the misaligned edges will be described below with respect toFIGS. 16-21.

The conductive layer may comprise a conductive material such as poly-silicon or the like. Alternatively, the conductive layer may be formed of other commonly used conductive materials such as a metal (e.g., tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, tantalum silicide), other conductive materials, combinations thereof, and/or the like. The conductive layer may be deposited using suitable semiconductor deposition techniques.

The dielectric layer134may include silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric material, combinations thereof, or multi-layers thereof. The dielectric layer134may be deposited using suitable semiconductor deposition techniques. The dielectric layer134may be alternatively referred to as a resist protection oxide (RPO) dielectric layer. The dielectric layer134may have a thickness in a range from about 100 Å to about 2,500 Å. It should be noted that the thickness of the dielectric layer134may vary based upon different applications and design needs. In some embodiments, the thickness of the dielectric layer134may be selected based upon the breakdown voltage of the MOS transistor100.

As shown inFIG. 10, the dielectric layer134comprises two horizontal portions and one vertical portion. A first horizontal portion is formed over the drift region, which is between the gate spacer133and the drain region126. A second horizontal portion is formed on top of the gate spacer133. A vertical portion is formed along the sidewall of the gate spacer133. As shown inFIG. 10, the dielectric layer134may be a substantially conformal layer. The thickness of the horizontal portions of the dielectric layer134is substantially equal to the thickness of the vertical portion of the dielectric layer134.

After the field plate has been formed as shown inFIG. 10, a salicide process may be applied to the body pickup region122, the source124, the gate electrode132, the conductive layer and the drain126. In the salicide process, a thin layer of metal is blanket deposited over the semiconductor device100having the exposed silicon regions (e.g., the drain, source, gate electrode and conductive layer shown inFIG. 10). The semiconductor device100is then subjected to one or more annealing steps. This annealing process causes the metal to selectively react with the exposed silicon regions, thereby forming metal silicide layers172,174,176,182and186over the exposed silicon regions. In some embodiments, the metals used in the salicide process include titanium, platinum, cobalt, nickel and the like. However, other metals, such as manganese, palladium and the like, can also be used.

FIG. 11illustrates a cross sectional view of the semiconductor device shown inFIG. 10after a contact etch stop layer (CESL) is formed on the semiconductor device in accordance with various embodiments of the present disclosure. The CESL141may comprise commonly used dielectric materials, such as silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide, combinations thereof, and multi-layers thereof. The CESL141is deposited over the semiconductor device through suitable deposition techniques such as sputtering, CVD and the like.

FIG. 12illustrates a cross section view of the semiconductor device shown inFIG. 11after a dielectric layer is deposited over the CESL layer in accordance with various embodiments of the present disclosure. The dielectric layer142is deposited over the CESL141. The dielectric layer142may be alternatively referred to as an inter-layer dielectric (ILD) layer. The dielectric layer142may be a low-k dielectric layer having a low dielectric constant, for example, less than about 3.5. The dielectric layer142may also comprise a combination of materials, such as silicon nitride, silicon oxy-nitride, high-k dielectrics, low-k dielectrics, CVD poly-silicon or other dielectrics. The dielectric layer142may be deposited using suitable deposition techniques such as sputtering, CVD and the like.

FIG. 13illustrates a cross section view of the semiconductor device shown inFIG. 12after an anisotropic etching process is applied to the dielectric layer and the CESL layer of the semiconductor device in accordance with various embodiments of the present disclosure. A plurality of openings151,153,155,157and159are formed by etching the dielectric layer142. With the help of the CESL layer141, the etching of the dielectric layer142is more precisely controlled. After the CESL layer141and dielectric layer142in the openings151,153,155,157and159have been removed. The underlying metal silicide layers over the gate electrode, drain/source regions, the conductive layer and the body pickup region are exposed.

FIG. 14illustrates a cross section view of the semiconductor device shown inFIG. 13after metal materials are filled in the openings of the semiconductor device in accordance with various embodiments of the present disclosure. A metallic material, which includes tungsten, titanium, aluminum, copper, any combinations thereof and/or the like, is filled into the openings151,153,155,157and159, forming contact plugs152,154,156,158and160. It should be noted that the contact plug configuration shown inFIG. 14is merely an example. A person skilled in the art will recognize there may be many alternatives, modifications and variations. For example, depending on different applications and design needs, the body pickup region122and the first drain/source region124may share a contact plug.

FIG. 15illustrates a flow chart of a method for forming the semiconductor device shown inFIG. 1in accordance with various embodiments of the present disclosure. This flowchart is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various step as illustrated inFIG. 15may added, removed, replaced, rearranged and repeated.

At step1502, an epitaxial layer is grown from a substrate through a suitable epitaxial growth process. At step1504, a plurality of isolation regions are formed in the epitaxial layer. At step1506, an n-type well is formed in the epitaxial layer through an ion implantation process. At step1508, a p-type body region and an n-type doped drain region are formed in the n-type well through suitable ion implantation processes.

At step1510, a gate dielectric layer is deposited over the substrate through suitable semiconductor deposition processes. At step1512, a gate electrode layer is deposited over the gate dielectric layer. A patterning process may be applied to the gate dielectric layer and the gate dielectric layer. The remaining portions of the gate dielectric layer and the gate dielectric layer form a gate structure.

At step1514, a dielectric layer is deposited over the gate structure. The horizontal portions of the dielectric layer are removed by suitable etching processes. The remaining portions of the dielectric layer form gate spacers along sidewalls of the gate structure. At step1516, the drain, the source and the body pickup regions are formed through suitable ion implantation processes.

At step1518, a dielectric layer is formed over the substrate through suitable deposition processes. At step1520, a conductive layer is formed over the dielectric layer through suitable deposition processes. At step1522, a patterning process is applied to the dielectric layer and the conductive layer. The remaining portions of the conductive layer form a field plate extending from the gate structure to the drain region.

At step1524, a salicide process is applied to the semiconductor device. During the salicide process, metal silicide layers are formed on the respective drain, source, gate electrode, body pickup and field plate regions. At step1526, a etch stop layer is deposited over the semiconductor device. At step1528, a dielectric layer or an ILD layer is deposited over the etch stop layer. At step1530, a plurality of openings are formed in the dielectric layer. At step1532, contact plugs are formed in the openings through suitable fabrication processes such as a plating process.

FIGS. 16-21illustrate cross section views of intermediate steps of fabricating another MOS transistor in accordance with various embodiments of the present disclosure. The fabrication steps shown inFIGS. 16-21are similar to the fabrication steps shown inFIGS. 9-14except that two lithography masks are employed during the formation process of the field plate. As shown inFIG. 17, a first mask is employed to define the shape of the conductive layer and form the field plate136. A second mask is employed to define the shape of the dielectric layer134. As shown inFIG. 17, there is a gap between the rightmost edge of the field plate136and the rightmost edge of the dielectric layer134. The distance between the rightmost edge of the field plate136and the rightmost edge of the dielectric layer134is defined as D. The value of D may vary based upon different applications and design needs. The semiconductor device200shown inFIGS. 16-21is similar to the semiconductor device100shown inFIG. 1except that the length of the portion of the dielectric layer over the drift region is greater than the length of the portion of the field plate over the drift region.

FIG. 22illustrates a flow chart of a method for forming the semiconductor device shown inFIGS. 16-21in accordance with various embodiments of the present disclosure. This flowchart is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various step as illustrated inFIG. 22may added, removed, replaced, rearranged and repeated.

The fabrication steps2202-2220and2226-2234are similar to steps1502-1520and1524-1532shown inFIG. 15, and hence are not discussed in detail herein again to avoid unnecessary repetition. At step2222, the conductive layer is patterned using a first mask. At step2224, the dielectric layer is patterned using a second mask. By using two different masks, the shape of the field plate can be controlled accordingly.

FIG. 23illustrates a cross section view of another MOS transistor in accordance with various embodiments of the present disclosure. The MOS transistor300is similar to the MOS transistor100shown inFIG. 1except that a dummy gate structure165is formed between the gate structure130and the drain126. As shown inFIG. 23, the dummy gate structure165includes a gate dielectric layer161, a gate electrode162and a gate spacer63. Furthermore, as shown inFIG. 23, the field plate136is formed between the gate structure130and the dummy gate structure165.

One advantageous feature of having the dummy gate structure165is that the dummy gate structure165helps to further improve the isolation between the drain the gate structure. As a result, the reliability of the MOS transistor300shown inFIG. 23can be improved.

FIG. 24illustrates a flow chart of a method for forming the semiconductor device shown inFIG. 23in accordance with various embodiments of the present disclosure. This flowchart is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various step as illustrated inFIG. 24may added, removed, replaced, rearranged and repeated.

The fabrication steps2402-2410and2416-2430shown inFIG. 24are similar to steps1502-1510and1514-1532shown inFIG. 15, and hence are not discussed in detail herein again to avoid unnecessary repetition. At step2412, both a gate electrode and a dummy gate electrode are formed over the substrate. At step2414, both gate spacers and dummy gate spacers are formed along the respective gate structures.

In accordance with an embodiment, a method comprises forming a gate structure over a substrate, forming a gate spacer along sidewalls of the gate structure, forming a first drain/source region and a second drain/source region on opposite sides of the gate structure, wherein a sidewall of the first drain/source region is vertically aligned with a first sidewall of the gate spacer, depositing a dielectric layer over the substrate, depositing a conductive layer over the dielectric layer, patterning the dielectric layer and the conductive layer to form a field plate, wherein the dielectric layer comprises a horizontal portion extending from the second drain/source region to a second sidewall of the gate spacer and a vertical portion formed along the second sidewall of the gate spacer, forming a plurality of metal silicide layers by applying a salicide process to the conductive layer, the gate structure, the first drain/source region and the second drain/source region and forming contact plugs over the plurality of metal silicide layers.

In accordance with an embodiment, an apparatus comprises a first drain/source region and a second drain/source region on opposite sides of a gate structure, a conductive field plate formed between the gate structure and the second drain/source region, wherein the conductive field plate comprises a metal silicide layer over a conductive layer, and wherein the conductive layer is over a dielectric layer, and wherein a horizontal portion of the dielectric layer extends from the second drain/source region to a sidewall of a gate spacer formed along the gate structure and a vertical portion of the dielectric layer is formed along the sidewall of the gate spacer and a plurality of contact plugs connected to the first drain/source region, the second drain/source region and the conductive layer respectively, wherein the conductive layer and a contact plug are connected through the metal silicide layer formed over the conductive layer.

In accordance with an embodiment, a method comprises growing an epitaxial layer over a substrate, forming a plurality of isolation regions in the epitaxial layer, implanting ions in the epitaxial layer to form a well, forming a body region and a doped drain region in the well, forming a gate structure over the substrate, forming a gate spacer along sidewalls of the gate structure, forming a source region in the body region and a drain region in the doped drain region, wherein the source region and the drain region are on opposite sides of the gate structure, and wherein a sidewall of the source region is vertically aligned with a first sidewall of the gate spacer, depositing a dielectric layer over the substrate, depositing a conductive layer over the dielectric layer, patterning the dielectric layer and the conductive layer to form a field plate, wherein the field plate comprises a horizontal portion formed between the drain region and a second sidewall of the gate structure, and a vertical portion formed along the second sidewall of the gate spacer, applying a salicide process to the conductive layer, the drain region and the source region to from a plurality of metal silicide layers and forming contact plugs over the plurality of metal silicide layers.