Switched capacitor type D/A converter

A switched capacitor type D/A converter receives m-bit (m represents an integer) input data, and outputs an analog signal that corresponds to the input data value. Switch circuits are provided to respective bits of the input data, and are classified into two groups: a first group configured to turn on when the corresponding input data bit is 1, and to turn off when the corresponding input data bit is 0; and a second group configured to turn on when the corresponding input data bit is 0, and to turn off when the corresponding input data bit is 1. Each switch of the first and second switch groups is configured as a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The ground voltage 0 V is applied to the lower power supply terminal of each of the first and second inverters configured to supply a gate signal to each switch.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a switched capacitor type D/A converter.

2. Description of the Related Art

As a D/A converter configured to convert a digital signal into an analog signal, a switched capacitor type D/A converter is known. Such a switched capacitor type D/A converter receives N-bit data, and outputs an analog signal having a voltage level that corresponds to the data thus received.

The D/A converter includes a switch configured to be controlled to turn on/off in synchronization with a clock signal, and switches each configured to be controlled to turn on/off according to a corresponding bit of digital data. As disclosed in Patent document 2, typical switched capacitor type D/A converters employ, as such a switch, an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a transfer gate using such an N-channel MOSFET.

RELATED ART DOCUMENTS

Patent Documents

Japanese Patent Application Laid Open No. 2003-283337[Patent Document 2]

Japanese Patent Application Laid Open No. 2001-111427

The present inventor has investigated such a switched capacitor type D/A converter including such N-channel MOSFETs as such switches, and has come to recognize the following problems.

FIG. 1is a circuit diagram which shows a part of a configuration of a switched capacitor type D/A converter.

The switches included in the switched capacitor type D/A converter can be classified into two groups: a first switch group M11, which are configured to turn on when the corresponding bit of a digital signal is 1; and a second switch group M12, which are configured to turn on when the corresponding bit of the digital signal is 0. With such an arrangement, gate signals G1and G2, which are respectively transmitted via inverters502and504, are supplied to the first switch group M11and the second switch group M12, respectively.

With such an N-channel MOSFET, when a high-level voltage is applied to its gate, the N-channel MOSFET is turned on, and a low-level voltage is applied to its gate, the N-channel MOSFET is turned off. With the gate signals G1and G2, which are respectively output from the inverters502and504, the power supply voltage Vdd is used as a high-level voltage, and the ground voltage Vgnd is used as a low-level voltage. Accordingly, the on resistance of each switch depends on the power supply voltage Vdd. That is to say, if noise is superimposed on the power supply voltage Vdd, the on resistance of each switch fluctuates, leading to a problem of deterioration in the power supply rejection ratio (PSRR) of the D/A converter.

In a case in which the output voltage of a DC/DC converter such as a charge pump circuit, a switching regulator, or the like, is used as the power supply voltage Vdd, such deterioration in the PSRR is particularly conspicuous. If such a D/A converter is used to perform audio signal processing, such an arrangement leads to a problem of deterioration in the sound quality.

SUMMARY OF THE INVENTION

The above-described consideration is by no means within the scope of common and general knowledge in the field of the present invention. Furthermore, it can be said that the present applicant has been the first to arrive at this consideration.

The present invention has been made in order to solve such a problem. Accordingly, it is an exemplary purpose of the present invention to provide a switched capacitor type D/A converter having an improved PSRR.

An embodiment of the present invention relates to a switched capacitor type D/A converter configured to receive m-bit (m represents an integer) input data, and to output an analog signal that corresponds to the value of the input data. The switched capacitor type D/A converter comprises: m switch circuits provided to respective bits of the input data, each switch circuit comprising a first switch group and a second switch group, each switch in the first switch group being on state when the corresponding bit of the input data is 1 and being off state when the corresponding bit of the input data is 0, each switch in the second switch group being on state when the corresponding bit of the input data is 0 and being off state when the corresponding bit of the input data is 1; a first inverter configured to output a gate signal to each switch in the first switch group; and a second inverter configured to output a gate signal to each switch in the second switch group. Each switch in the first switch group and the second switch group is configured as a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The ground voltage is applied to a lower power supply terminal of each of the first inverter and the second inverter.

With such an embodiment, the ground voltage is applied to the gate of each P-channel MOSFET during a period in which the P-channel MOSFET is to be turned on. Thus, fluctuation in the power supply voltage has almost no effect on the on resistance of each of such switches. This provides an improved PSRR.

Also, the back gate of the P-channel MOSFET may be fixed at an electric potential that is lower than the voltage to be input to an upper power supply terminal of each of the first inverter and the second inverter.

The on resistance of each P-channel MOSFET is higher than the on resistance of an N-channel MOSFET. Accordingly, by fixing the back gate of such a P-channel MOSFET at a voltage that is lower than the power supply voltage, instead of being fixed at the power supply voltage, such an arrangement provides a reduction in the on resistance of such a P-channel MOSFET, thereby compensating for the disadvantage of employing such a P-channel MOSFET.

Also, an output voltage of a DC/DC converter may be supplied to an upper power supply terminal of each of the first inverter and the second inverter.

Switching noise is superimposed on the output voltage of the DC/DC converter. However, by employing a P-channel MOSFET as such a switch, such an arrangement provides an advantage of the PSRR characteristics not being subjected to the effects of such switching noise.

Another embodiment of the present invention also relates to a switched capacitor type D/A converter. The switched capacitor type D/A converter comprises: m switch circuits provided to respective bits of the input data, each switch circuit comprising a first switch group and a second switch group, each switch in the first switch group being on state when the corresponding bit of the input data is 1 and being off state when the corresponding bit of the input data is 0, each switch in the second switch group being on state when the corresponding bit of the input data is 0 and being off state when the corresponding bit of the input data is 1; a first inverter configured to output a gate signal to each switch in the first switch group; a second inverter configured to output a gate signal to each switch in the second switch group; a band gap reference circuit configured to generate a reference voltage; and a linear regulator configured to output a voltage that corresponds to the reference voltage. Each switch in the first switch group and the second switch group is configured as an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The output voltage of the linear regulator is supplied to an upper power supply terminal of each of the first inverter and the second inverter.

The linear regulator is configured to generate a voltage according to the reference voltage received from the band gap reference circuit. Accordingly, the output voltage is provided with a high PSRR. Accordingly, the high level voltage of the gate signal output from each of the first and second inverters is provided with a high PSRR. Thus, such an arrangement is capable of suppressing fluctuation in the on resistance of each switch even if an N-channel MOSFET is employed as such a switch. Thus, such an arrangement is capable of suppressing deterioration in the PSRR of the D/A converter, or provides an improved PSRR.

Yet another embodiment of the present invention also relates to a switched capacitor type D/A converter. The switched capacitor type D/A converter comprises: m switch circuits provided to respective bits of the input data, each switch circuit comprising a first transfer gate group and a second transfer gate group, each transfer gate in the first transfer gate group being on state when the corresponding bit of the input data is1and being off state when the corresponding bit of the input data is 0, each transfer gate in the second transfer gate group being on state when the corresponding bit of the input data is 0 and being off state when the corresponding bit of the input data is 1; a first inverter configured to output a gate signal to each N-channel MOSFET in the first transfer gate group and each P-channel MOSFET in the second transfer gate group; a second inverter configured to output a gate signal to each P-channel MOSFET in the first transfer gate group and each N-channel MOSFET in the second transfer gate group; a band gap reference circuit configured to generate a reference voltage; and a linear regulator configured to receive the reference voltage. The ground voltage is applied to a lower power supply terminal of each of the first inverter and the second inverter. The output voltage of the linear regulator is applied to an upper power supply terminal of each of the first inverter and the second inverter.

Such an embodiment is capable of suppressing fluctuation in the on resistance of each of the P-channel MOSFETs and the N-channel MOSFETs. Thus, such an arrangement is capable of suppressing deterioration in PSRR of the D/A converter, or provides an improved PSRR.

Also, the input data may be in the form of a digital audio signal.

With the D/A converter according to any one of the aforementioned embodiments, such an arrangement provides high-quality audio signal processing.

DETAILED DESCRIPTION OF THE INVENTION

In the present specification, the state represented by the phrase “the member A is connected to the member B” includes a state in which the member A is indirectly connected to the member B via another member that does not substantially affect the electric connection therebetween, or that does not damage the functions or effects of the connection therebetween, in addition to a state in which the member A is physically and directly connected to the member B.

Similarly, the state represented by the phrase “the member C is provided between the member A and the member B” includes a state in which the member A is indirectly connected to the member C, or the member B is indirectly connected to the member C via another member that does not substantially affect the electric connection therebetween, or that does not damage the functions or effects of the connection therebetween, in addition to a state in which the member A is directly connected to the member C, or the member B is directly connected to the member C.

FIG. 2is a circuit diagram which shows a configuration of a switched capacitor type D/A converter100according to a first embodiment.

The D/A converter100receives m-bit (m represents an integer) input data Vdata1through Vdatam, and outputs a differential analog signal that corresponds to the value of the input data thus received. Examples of such input data include a digital audio signal.

The D/A converter100includes m switch circuits101through10mprovided to the respective bits Vdata1through Vdatamof the input data, m input capacitor pairs (CiH/CiL)1through (CiH/CiL)mprovided to the respective bits Vdata1through Vdatam, switches SW1through SW4, a first calculation unit20p, and a second calculation unit20n.

An upper reference voltage VH, a middle reference voltage VM, and a lower reference voltage VLare supplied to the respective terminals PH, PM, and PLof the D/A converter100.

The switch circuits101through10mare each configured in the same way. Accordingly, directing attention to the switch circuit101provided for the first bit, description will be made regarding the configuration of the switch circuit10. The switch circuit10includes a first input terminal INH, a second input terminal INL, a first output terminal OUTp, and a second output terminal OUTn.

When the data Vdataiis 1 (high level), the switch circuit10iconnects the first output terminal OUTp and the first input terminal INH, and connects the second output terminal OUTn and the second input terminal INL.

Conversely, when the data Vdataiis 0 (low level), the switch circuit10iconnects the first output terminal OUTp and the second input terminal INL, and connects the second output terminal OUTn and the first input terminal INH.

The switch circuit10iincludes a first switch group and a second switch group. The first switch group comprises switches M1and M4which are on-state when the corresponding bit Vdataiof the input data is 1 and are off-state when the corresponding bit Vdataiof the input data is 0. The second switch group comprises switches M2and M3which are on-state when the corresponding bit Vdataiis 0 and off-state when the corresponding bit Vdataiof the input data is 1.

With the present embodiment, the switches M1through M4are each configured as a P-channel MOSFET. The second inverter14inverts Vdatai, and supplies the data thus inverted as a gate signal to the switches M2and M3of the second switch group. The first inverter12inverts the output signal of the second inverter14, and supplies the output signal thus inverted as a gate signal to the switches M1and M4of the first switch group.

As shown in the lower-right part ofFIG. 2, the ground voltage (0 V) is applied to the lower power supply terminal of each of the first inverter12and the second inverter14. Furthermore, the power supply voltage Vdd is applied to the upper power supply terminal of each of the first inverter12and the second inverter14. The power supply voltage Vdd is generated by a DC/DC converter40.

The back gate of the P-channel MOSFET is fixed at a voltage VHthat is lower than the voltage Vdd input to the upper power supply voltage terminals of the first inverter12and the second inverter14.

The first terminals of input capacitors CiH1through CiHmare connected together so as to form a common first terminal. Furthermore, the second terminal of the input capacitor CiHiis connected to the first input terminal INHof the switch circuit10i. The first terminals of input capacitors CiL1through CiLmare connected together so as to form a common first terminal. Furthermore, the second terminal of the input capacitor CiLiis connected to the second input terminal INLof the switch circuit10i.

The D/A converter100alternately repeats a first state φ1and a second state φ2in synchronization with a clock signal.FIG. 2shows the on/off state of each switch in the first state φ1. That is to say, each switch in the off state shown inFIG. 2is turned on in the second state φ2.

The first switch SW1is arranged between the common first terminal formed by connecting together the first terminals of the input capacitors CiH1through CiHmand a terminal PHto which the upper reference voltage VHis to be applied. The third switch SW3is arranged between the common first terminal formed by connecting together the first terminals of the input capacitors CiH1through CiHmand a terminal PMto which the middle reference voltage VMis to be applied.

The second switch SW2is arranged between the common first terminal formed by connecting together the first terminals of the input capacitors CiL1through CiLmand a terminal PLto which the lower reference voltage VLis to be applied. The fourth switch SW4is arranged between the common first terminal formed by connecting together the first terminals of the input capacitors CiL1through CiLmand the terminal PMto which the middle reference voltage VMis to be applied.

The input terminal Pi of the first calculation unit20pis connected to a common first output terminal formed by connecting together the first output terminals OUTp of the switch circuit101through10m. The first calculation unit20pincludes an operational amplifier22, a first capacitor C1, a second capacitor C2, and a fifth switch SW5through an eighth switch SW8.

A reference voltage is input to the non-inverting input terminal of the operational amplifier22. The fifth switch SW5is arranged between the input terminal Pi and the reference voltage terminal. The sixth switch SW6is arranged between the inverting input terminal of the operational amplifier22and the input terminal Pi. The first capacitor C1is arranged between the inverting input terminal of the operational amplifier22and the output terminal thereof. The seventh switch SW7and the second capacitor C2are sequentially arranged in series between the output terminal of the operational amplifier22and the input terminal Pi thereof. The eighth switch SW8is arranged between the reference voltage terminal and a connection node that connects the seventh switch SW7and the second capacitor C2.

The second calculation unit20nis configured in the same way as the first calculation unit20p. The input terminal Pi of the second calculation unit20nis connected to a common second output terminal formed by connecting together the second output terminals OUTn of the switch circuit101through10m.

The above is the configuration of the D/A converter100. Next, description will be made regarding the operation thereof.

When the gate signal received from the inverter12or14is low level, i.e., the gate signal is set to the ground voltage 0V, the switch groups M1through M4, each configured as a P-channel MOSFET, are turned on. Even if the power supply voltage Vdd fluctuates, such fluctuation in the power supply voltage Vdd has no effect on the ground voltage 0 V, or, even if there is such an effect, it is miniscule.

That is to say, there is almost no fluctuation in the on resistance of each of the switch groups M1through M4even if the power supply voltage Vdd fluctuates.

Thus, with such a D/A converter100shown inFIG. 1, such an arrangement provides improvement in the PSRR characteristics, as compared with an arrangement employing N-channel MOSFETs as the switches M1through M4. Specifically, in a case in which N-channel MOSFETs are employed as the switches M1through M4, such an arrangement provides a PSRR on the order of 60 dB. In contrast, such an arrangement employing P-channel MOSFETs as the switches M1through M4provides an improved PSRR on the order of 90 dB, which is a notable advantage.

As can be understood from the above description, in particular, such a D/A converter100is suitably used to perform audio signal processing that requires a particularly high PSRR.

However, the on resistance of a P-channel MOSFET is greater than that of an N-channel MOSFET of the same size. Accordingly, if there is a desire to provide the same on resistance as that of an N-channel MOSFET, there is a need to form such a P-channel MOSFET with a larger area.

With typical arrangements, the power supply voltage Vdd is applied to the back gate of such a P-channel MOSFET. In contrast, in the D/A converter100shown inFIG. 2, a voltage that is lower than the power supply voltage Vdd, specifically, the upper reference voltage VH, is applied to the back gate of each of the switches M1through M4. Such an arrangement provides a reduction in the on resistance of each P-channel MOSFET. Thus, such an arrangement does not require such a P-channel MOSFET to have such a large area, thereby providing a reduced circuit area.

As described above, the on resistance of each of the transistors M1through M4is not subjected to the effects of the power supply voltage Vdd. Thus, such an arrangement allows the output voltage of a DC/DC converter having a large amount of fluctuation to be employed as the power supply voltage Vdd. The DC/DC converter has a conversion efficiency that is higher than that of a linear regulator. Thus, by employing such a D/A converter100, such an arrangement provides reduced overall power consumption of the system.

Description will be made in the second embodiment regarding a technique for providing an improved PSRR by means of an approach that differs from that used in the first embodiment.

FIG. 3is a circuit diagram which shows a configuration of a power supply unit of a D/A converter100aaccording to a second embodiment. In the second embodiment, switches M1through M4, which compose a switch circuit10of the D/A converter100a, are each configured as an N-channel MOSFET.

A power supply unit of the D/A converter100aincludes a DC/DC converter40, a band gap reference circuit30, a start-up circuit32, a first linear regulator34, and a second linear regulator36.

The DC/DC converter40is configured to receive an input voltage on the order of 3 V, and converts the input voltage thus received into a power supply voltage Vdd on the order of 1.8 V. The input voltage may be supplied as a battery voltage, for example.

The band gap reference circuit30generates a reference voltage VBGRon the order of 1.2 V. The start-up circuit32is arranged in order to start up the band gap reference circuit30. The band gap reference circuit30and the start-up circuit32should be configured using known techniques. A capacitor CBGRis connected to the output terminal of the band gap reference circuit30. It should be noted that the power supply voltage Vdd may be supplied to the power supply terminal of an error amplifier EA of the band gap reference circuit30. Also, a second power supply voltage Vdd′, which is generated by the first linear regulator34arranged as a downstream component, may be supplied to the power supply terminal of the error amplifier EA.

The first linear regulator34includes a voltage follower configured to receive the reference voltage VBGR, and to generate a second power supply voltage Vdd′ on the order of 1.2 V. The second power supply voltage Vdd′ is supplied to the upper power supply terminal of each of the first inverter12and the second inverter14. Furthermore, the first linear regulator34divides the second power supply voltage Vdd′ so as to generate a common voltage Vcom.

The second linear regulator36receives the common voltage Vcom, and generate an upper reference voltage VH, a middle reference voltage VM, and a lower reference voltage VL. A smoothing capacitor C10is externally connected to a terminal of the second linear regulator36at which the upper reference voltage VHdevelops. The upper reference voltage VHis supplied to the upper power supply terminal of each of the first inverter12and the second inverter14.

The above is the configuration of the D/A converter100a. The upper reference voltage VHis generated by the first linear regulator34and the second linear regulator36based on the reference voltage VBGR. Thus, the upper reference voltage VHthus generated is not subject to the effects of fluctuation in the power supply voltage Vdd, thereby providing a stable voltage level. Thus, such fluctuation in the power supply voltage Vdd has almost no effect on the on resistances of the transistors M1through M4each configured as an N-channel MOSFET.

With such a D/A converter100ashown inFIG. 3, such an arrangement provides improved PSRR even if the switches M1through M4are each configured as an N-channel MOSFET.

It should be noted that, with the first embodiment, the second power supply voltage Vdd′ generated by the first linear regulator34shown inFIG. 3may be supplied to the upper power supply terminal of each of the first inverter12and the second inverter14.

A third embodiment can be understood as being a combination of the first and second embodiments.FIG. 4is a circuit diagram showing a part of a configuration of a D/A converter100baccording to the third embodiment. A power supply unit of the D/A converter100bshould be configured in the same way as the power supply unit shown inFIG. 3. Accordingly, the power supply unit of the D/A converter100bis not shown in the drawing.

In the D/A converter100b, each switch that is a component of a switch circuit10bis configured as a transfer gate TG. The transfer gate TG includes a P-channel MOSFET and an N-channel MOSFET. The second power supply voltage Vdd′ is supplied to the upper power supply terminal of each of a first inverter12and the second inverter14. The ground voltage 0 V is supplied to the lower power supply terminal of each of the first inverter12and the second inverter14.

With such a third embodiment, such an arrangement provides a high PSRR while providing a reduction in the on resistance of each switch that is a component of the switch circuit10.

Description has been made regarding the present invention with reference to the embodiments. The above-described embodiment has been described for exemplary purposes only, and is by no means intended to be interpreted restrictively. Rather, it can be readily conceived by those skilled in this art that various modifications may be made by making various combinations of the aforementioned components or processes, which are also encompassed in the technical scope of the present invention. Description will be made below regarding such modifications.

The topology of the capacitors and switches shown inFIG. 2has been described for exemplary purpose only. Also, the present invention can be applied to various kinds of switched capacitor type D/A converters having known or prospectively available topologies.FIG. 5is a circuit diagram which shows a modification of the first calculation unit20pand the second calculation unit20nshown inFIG. 2. InFIG. 5, the first calculation unit20pand the second calculation unit20nare configured such that they share a single differential amplifier23, instead of employing the two operational amplifiers. The topology of the capacitors and the switches is the same as that shown inFIG. 2.

Description has been made in the embodiments regarding a differential output D/A converter. Also, the present invention can be applied to a single-ended D/A converter.