Differential line termination technique

A technique for terminating a differential signal line substantially matches the output impedances of a first node and a second node of a differential node. The power dissipation is substantially less than twice the power delivered to a load impedance coupled to the differential signal line. The technique provides a peak-to-peak, single-ended output voltage on the differential output node that is substantially independent of integrated circuit manufacturing process tolerances. An apparatus includes a differential node coupled to provide a differential signal. The differential node includes a first node and a second node. A first single-ended termination circuit is coupled to the first node and responsive to a first reference voltage. The apparatus includes a second single-ended termination circuit coupled to the second node and responsive to a second reference voltage.

BACKGROUND

1. Field of the Invention

The present invention relates to integrated circuits, and more particularly to input/output buffers of integrated circuits.

2. Description of the Related Art

A differential output buffer on an integrated circuit may drive differential signal lines, e.g., traces on a printed circuit board, which are finite-length transmission lines. To reduce signal reflections on those differential transmission lines and corresponding degradation of signals on those transmission lines, the finite-length transmission lines are coupled to a termination impedance that makes the finite-length transmission lines behave as if they are infinite in length, i.e., the individual transmission lines are terminated by an impedance having a value approximately equal value to the characteristic impedance of a respective transmission line. By integrating termination resistors into the differential output buffer on the integrated circuit, the number of external resistors included on a printed circuit board including the integrated circuit may be reduced.

Although typical termination resistors included in the differential output buffer are designed to be equal to the input impedance of the load to which it is coupled, the actual output impedance may not match the input impedance of the load exactly, due to integrated circuit manufacturing process variations. Accordingly, reflections may degrade the signal and the single-ended, peak-to-peak output voltage level may vary according to the variation in resistor values, thereby reducing the power transferred to the load. Some techniques for impedance matching the load result in mismatches in the output impedances of individual nodes of a differential node, which may degrade the signal and power transfer to the load. In addition, currents flowing through termination resistors may dissipate substantial amounts of power, which decreases battery life in portable applications and increases costs related to packaging and cooling systems.

SUMMARY

A technique for terminating a differential signal line substantially matches the output impedance of a first node of a differential node to the output impedance of a second node of the differential node. The power dissipation associated with the technique is substantially less than twice the power delivered to a load impedance coupled to the differential signal line. In addition, the technique provides a peak-to-peak, single-ended output voltage on the differential output node that is substantially independent of integrated circuit manufacturing process tolerances.

In at least one embodiment of the invention, an apparatus includes a differential node coupled to provide a differential signal. The differential node includes a first node and a second node. The apparatus includes a first single-ended termination circuit that is coupled to the first node and that is responsive to a first reference voltage. The apparatus includes a second single-ended termination circuit that is coupled to the second node and that is responsive to a second reference voltage.

In at least one embodiment of the invention, a method includes single-endedly terminating individual ones of a first node of a differential node and a second node of a differential node. In at least one embodiment of the invention, the method includes maintaining a first voltage on the first node and maintaining a second voltage on the second node. The first voltage and the second voltage are based on at least a target common mode voltage of a signal on the differential node and a target single-ended, peak-to-peak voltage of the signal.

DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

Referring toFIG. 1A, an exemplary low-voltage differential signaling (LVDS) output driver (e.g., integrated circuit100) includes buffer circuit101and termination circuit103coupled to differential output node OUTP and OUTN. The LVDS output driver is coupled to an exemplary 100 ohms (Ω) line (e.g., external impedance108). An exemplary termination circuit103(FIG. 1B) matches external impedance108by including a 100 Ω termination impedance coupled across differential output node OUTP and OUTN, e.g., the impedance formed by resistors104and106. The node between resistors104and106(e.g., node105), which generates the common mode voltage of the output signal on differential output node OUTP and OUTN (e.g., an output signal driven by buffer circuit101), is sensed by transconductance amplifier102. Transconductance amplifier102compares the common mode voltage level of the differential signal on output node OUTP and OUTN (e.g., the voltage on node105) to a fixed reference voltage level equal to a target common mode voltage level (e.g., Vcm). The target common mode voltage level may be generated by a bandgap voltage reference circuit (not shown) or other suitable technique for generating a stable reference voltage level. Transconductance amplifier102maintains the target common mode voltage level on node105by adjusting the output current of transconductance amplifier102.

Current sink110establishes a current through external impedance108and a current through resistors104and106. The current through resistors104and106is approximately equal to the current through external impedance108(e.g., 3.25 mA). Accordingly, current sink110sinks a current (e.g., 6.5 mA) that is approximately twice the current delivered to external impedance108(e.g., 3.25 mA). Thus, only approximately 50% of the current flowing through termination circuit103is transferred to the load.

The peak-to-peak, single-ended (Vppse) output voltage level of exemplary termination circuit103is dependent upon actual resistance values of resistors104and106. Resistors104and106are subject to typical integrated circuit manufacturing process variations (e.g., 15% variation in an exemplary integrated circuit manufacturing process), resulting in variations in the output voltage on differential output node OUTP and OUTN. For example, if resistors104and106(e.g., designed to be 50 Ω each) are actually approximately 15% below the design value (e.g., 42.5 Ω each), the mismatch between the actual impedances of resistors104and106and the impedance of external impedance108changes Vppse to a voltage level (e.g., 299 mV) approximately 8% below the design value (e.g., 325 mV), which may not meet performance specifications in some applications. The efficiency of the circuit may also degrade, e.g., a greater current may flow through resistors104and106(e.g., 3.51 mA) than through external impedance108(e.g., 2.99 mA).

In addition, the impedances looking into individual nodes of differential output node OUTP and OUTN of termination circuit103are mismatched, i.e., the output impedance of OUTP and the output impedance of OUTN are not equal. Referring toFIG. 2A, characteristics of transconductance amplifier102are modeled as an ideal transconductance Gm with a finite output conductance gdso. Rswp models the resistance of a switch that alternately couples transconductance amplifier102to output node OUTP (e.g., for an output signal corresponding to a high data value) or output node OUTN (e.g., for an output signal corresponding to a low data value) according to a data value being conveyed by the output signal. The impedance looking into output node OUTP relative to ground is:

Routp=Rswp+1/gdso1+Gm/gdso.
Assuming that the output conductance of transconductance amplifier102, gdso, is negligible, and that node107, which is maintained at the target common mode voltage level, is a virtual ground, Routp of termination circuit103may be modeled by the circuit inFIG. 2B. However, since no current flows into the input of transconductance amplifier102, output node OUTP is modeled as being at the same potential as the inverting input of transconductance amplifier102(FIG. 2C), resulting in an approximation of the impedance looking into output node OUTP: Routp≈1/Gm. Typically, 1/Gm is approximately 20-50 mA/V and Routp is approximately 20-50 Ω.

Referring toFIG. 3A, the impedance looking into output node OUTN relative to ground is:

Routn=1+Gm*50+gdso⁡(2*50+Rswp)Gm+gdso.
Assuming that the output conductance of transconductance amplifier102, gdso, is negligible, Routn of termination circuit103may be modeled by the circuit inFIG. 3B. In addition, if gdso is negligible, resistance Rswp and resistor104, which are in series with the ideal transconductace Gm may also be ignored (FIG. 3C). However, resistor106cannot be ignored, resulting in an approximation of Routn ≈1/Gm+(resistance of resistor106) (e.g., 1/Gm+50 Ω). Typically, 1/Gm is approximately 20-50 mA/V and Routn is approximately 70-100 Ω. Routp and Routn have an impedance difference approximately equal to the resistance of resistor106(e.g., 50 Ω), which may result in reflections and impact system performance.

Referring toFIG. 4, rather than using a termination circuit having an amplifier driving one node of the differential output node OUTP and OUTN and the amplifier sensing between the termination resistors of termination circuit103, an amplifier in an exemplary termination circuit may drive and sense a node between the termination resistors and between output node OUTP and output node OUTN of the differential output node. Termination circuit403effectively eliminates the impedance mismatch of output node OUTP and output node OUTN of the differential output node by coupling amplifier402to node409, which is between resistors408and410and between output node OUTP and output node OUTN of the differential output node. Termination circuit403includes a current source (e.g., current source404) that provides current that flows through external impedance412and the termination resistors408and410. Although termination circuit403matches the impedances of output node OUTP and output node OUTN, termination circuit403sources and sinks at least twice the current delivered to an external impedance (e.g., external impedance412) and the Vppse output voltage level depends upon actual resistance values of resistors408and410.

A termination circuit consistent with the present invention matches the output impedances of output node OUTP and output node OUTN of a differential output node, provides a peak-to-peak, single-ended output voltage level that is effectively independent of integrated circuit manufacturing process tolerances, and may dissipate substantially less than twice the power delivered to an external impedance. Referring toFIG. 5, in at least one embodiment of the present invention, a termination circuit (e.g., termination circuit503) independently terminates individual nodes (e.g., output node OUTP and output node OUTN) of a differential node (e.g., differential output node OUTP and OUTN). Termination circuit503includes two separate, single-ended termination circuits (e.g., termination circuit505and termination circuit507) and receives two distinct voltage reference levels (e.g., Vcm+Vppse/2 and Vcm−Vppse/2).

Termination circuit505and termination circuit507include operational amplifiers502and504, respectively, and resistors506and508, respectively. In an embodiment, termination resistors506and508are designed to be nominally equal to each other and equal to half the nominal resistance of external impedance514. These values may vary under typical manufacturing conditions. As used herein, a nominal value (e.g., a nominal resistance value) refers to a specified value that is between (typically halfway between) maximum and minimum limits of a tolerance range for the value. Termination circuit505includes current source510and termination circuit507includes current sink512, which source and sink, respectively, a current that flows through external impedance514(e.g., 3.25 mA). Amplifiers502and504are voltage operational amplifiers (i.e., buffered operational amplifiers or low output resistance operational amplifiers). However, in at least one embodiment of the invention, termination circuits505and507may include operational transconductance amplifiers (i.e., unbuffered operational amplifiers, which have output impedances much greater than the load impedance and input impedances much greater than source impedances).

In at least one embodiment of the invention, the non-inverting terminal of operational amplifier502receives a reference voltage level equivalent to the sum of a target common mode voltage level and half of a target peak-to-peak, single-ended voltage level (i.e., Vcm+Vppse/2). The inverting terminal receives the voltage on the output node of operational amplifier502. On the output node of operational amplifier502, operational amplifier502maintains a voltage level equal to the reference voltage level on the non-inverting input (e.g., Vcm+Vppse/2). In at least one embodiment of the invention, no substantial current flows through resistor506because the reference voltage level (i.e., the sum of the target common mode voltage and the target peak-to-peak, single-ended voltage) is equal to the voltage on output node OUTP. Accordingly there is no substantial voltage drop across resistor506.

Operational amplifier504receives a reference voltage level equivalent to the difference of a target common mode voltage and half of a target peak-to-peak, single-ended voltage on the non-inverting terminal (i.e., Vcm−Vppse/2). The inverting terminal receives the voltage on the output node of operational amplifier504. On the output node of operational amplifier504, operational amplifier504maintains a voltage level equal to the reference voltage level on the non-inverting input. In at least one embodiment of the invention, no current flows through resistor508because the reference voltage level (i.e., the difference of the target common mode voltage level and the target peak-to-peak, single-ended voltage level) is equal to the voltage on output node OUTN. Accordingly, there is no substantial voltage drop across resistor508. Termination circuit503sinks current equal to approximately the current through external impedance514, in addition to the currents of operational amplifiers502and504(e.g., a total of approximately 4.75 mA for the entire circuit in at least one embodiment of the invention).

Although an embodiment of termination circuit503that receives the reference voltage levels described above and generates substantially no current through resistors506and508dissipates less power than embodiments that receive different reference voltage levels and generate some current flowing through resistors506and508, the invention is not limited thereto. In some embodiments, some current may flow through resistors506and508, but substantially less than the approximately 50% described in relation toFIGS. 1A and 4. In at least one embodiment of the invention, termination circuits505and507receive reference voltages that vary from a common mode voltage level by a magnitude other than half the peak-to-peak, single-ended voltage level, and generate some current in resistors506and508, respectively. Although some current flows through resistors506and508, such embodiments may dissipate substantially less power than termination circuit103and termination circuit403, which source and sink at least twice the current flowing through an external load. In addition, such embodiments match the output impedance of output node OUTP and output node OUTN of the differential output node.

In at least one embodiment of the invention, amplifier502and amplifier504include at least a portion of resistor506and/or at least a portion of resistor508within amplifier502and amplifier504, respectively. In at least one embodiment of the invention, amplifier502and amplifier504have sufficient voltage headroom (e.g., embodiments coupled to higher power supply voltage levels) to include at least a portion of current source510and/or at least a portion of current sink512within amplifier502and amplifier504, respectively. Such an embodiment reuses current generated by amplifiers502and504to drive the external impedance514, reducing power dissipation of termination circuit503as compared to embodiments that include circuit implementations of current source510and current sink512separate from amplifier502and amplifier504, respectively.

Referring toFIG. 6, in at least one embodiment of the invention, transconductance amplifiers602and604of termination circuit603provide current to external impedance606. For example, amplifier602and amplifier604may have sufficient voltage headroom to provide all or at least a substantial portion of the current driving the external impedance606, and thereby reuse current, or amplifier602and amplifier604may include separate circuit implementations of a current source (e.g., 3.25 mA current source) and a current sink (e.g., 3.25 mA current sink), respectively. The impedance looking into output node OUTP is 1/Gm1 and the impedance looking into output node OUTN is 1/Gm2, where Gm1 and Gm2 are transconductances of amplifiers602and604, respectively. The value of 1/Gm1 is approximately equal to the value of 1/Gm2 (e.g., approximately 50 Ω) and both are approximately equal to half of a nominal differential termination impedance, i.e., external impedance606(e.g., 100 Ω differential line impedance). The output current of amplifier602is equal to the current through external impedance606(e.g., 3.25 mA). Termination circuit603matches the impedance looking into output node OUTP of the differential node and the impedance looking into output node OUTN of the differential node, sources and sinks substantially less than twice the current flowing through external impedance606, and provides a Vppse on differential output node OUTP and OUTN that is substantially independent of process variations. In at least one embodiment of the invention, Gm1 and Gm2 are not approximately equal although the sum of 1/Gm1 and 1/Gm2 is approximately equal to the nominal differential termination impedance.

While circuits and physical structures are generally presumed, it is well recognized that in modern semiconductor design and fabrication, physical structures and circuits may be embodied in computer-readable descriptive form suitable for use in subsequent design, test or fabrication stages. Structures and functionality presented as discrete components in the exemplary configurations may be implemented as a combined structure or component. The invention is contemplated to include circuits, systems of circuits, related methods, and computer-readable medium encodings of such circuits, systems, and methods, all as described herein, and as defined in the appended claims. As used herein, a computer-readable medium includes at least disk, tape, or other magnetic, optical, semiconductor (e.g., flash memory cards, ROM), or electronic medium.

The description of the invention set forth herein is illustrative, and is not intended to limit the scope of the invention as set forth in the following claims. For example, while the invention has been described in an embodiment in which an output buffer is LVDS standard-compliant, one of skill in the art will appreciate that the teachings herein can be utilized with other differential signaling standards. Although in the exemplary electrical systems the load impedance is 100 Ω for a differential signal line, techniques described herein are applicable to other load impedance values. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein without departing from the scope and spirit of the invention as set forth in the following claims.