ADC channel selection and conversion

A microcontroller includes a microcontroller core and an analog-to-digital converter (“ADC”) coupled to said microcontroller core. The ADC has multiple input channel multiplexers that are configured to receive multiple analog input channels. The microcontroller further includes a selection register and a data structure. The data structure comprises a plurality of associated field sets. Each bit position in the selection register indexes to one of the associated field sets in the data structure, and the value contained in each such bit position indicates whether or not to select the corresponding associated field set for selection of an analog input channel. Each associated field set comprises one or more values collectively specifying an analog input channel to select for conversion to digital form.

BACKGROUND

Many microcontrollers are designed for embedded applications, and are used in automatically controlled products and devices such as automobile engine control systems, implantable medical devices, remote controls, office machines, appliances, power tools, toys, etc. Mixed signal microcontrollers integrate analog components needed to control non-digital electronic systems.

An analog-to-digital converter (“ADC”) converts a continuous quantity (e.g. an analog signal) to a series of discrete quantities (e.g. a digital signal). Typically, an ADC is an electronic device that converts an input analog voltage or current to a digital number proportional to the magnitude of the voltage or current. The resolution of the ADC, usually expressed as binary bits, indicates the number of discrete values the ADC can produce over the range of analog values. As such, the number of discrete values available, or “levels,” is usually a power of two. For example, an ADC with a resolution of 8 bits can encode an analog input to one of 256 different levels because an 8-bit binary value can represent 2^8 or 256 discrete quantities. However, the flexibility of coding levels has not resulted in flexibility of input channel selection and conversion timing. Indeed, ADC designs have restrictive and inefficient constraints placed on channel selection and conversion timing.

SUMMARY

The restrictive and inefficient constraints placed on conversion of input channels in ADCs located on microcontrollers are eliminated using this disclosure.

In at least one embodiment, a microcontroller includes a microcontroller core and an analog-to-digital converter (“ADC”) coupled to said microcontroller core. The ADC has multiple input channel multiplexers that are configured to receive multiple analog input channels. The microcontroller further includes a selection register and a data structure. The data structure comprises a plurality of associated field sets. Each bit position in the selection register indexes to one of the associated field sets in the data structure, and the value contained in each such bit position indicates whether or not to select the corresponding associated field set for selection of an analog input channel. Each associated field set comprises one or more values collectively specifying an analog input channel to select for conversion to digital form.

In at least one embodiment, an apparatus includes a microcontroller including an analog-to-digital converter (“ADC”). Multiple channels are selected for conversion in one round of conversion by the ADC via a binary value in a register. A channel identified with a higher index is converted by the ADC core before a channel identified with a lower index in a round of conversion. Each bit of the binary value corresponds to a plurality of address offsets in memory. A value beginning at an address offset, out of the plurality of address offsets, is used to select one of the multiple channels.

In at least one embodiment, a method includes reading a binary value in a channel select register. The method further includes selecting multiple channels for conversion in one round of conversion by an analog-to-digital converter (“ADC”) based on the value. A channel identified with a higher index is converted by the ADC core before a channel identified with a lower index in a round of conversion.

NOTATION AND NOMENCLATURE

Certain terms are used throughout the following claims and description to refer to particular components. As one skilled in the art will appreciate, different entities may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . .” Also, the term “couple” or “couples” is intended to mean an optical, wireless, indirect electrical, or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through an indirect electrical connection via other devices and connections, through a direct optical connection, etc. Additionally, the term “system” refers to a collection of two or more hardware components, and may be used to refer to an electronic device or a subsystem of an electronic device.

DETAILED DESCRIPTION

FIG. 1illustrates a host system100in accordance with various embodiments of the invention. As shown, host system100includes host logic120coupled to one or more microcontroller units (“MCUs”)199, which are coupled to one or more sensors130. The host system100can perform any of a variety of functions. For example, the host system100may be a medical device (e.g., an electrocardiograph), an antilock brake system for an automobile, etc. The host logic120may include a microprocessor, memory (containing software executed by the microprocessor), and other components not shown that imbue the host system100with some or all of its functionality. The sensors130may be any type of sensors relevant to the operation of the host system100, and the sensors are analog sensors in at least one embodiment. Examples of sensors130include temperature sensors, pressure sensors, speed sensors, and the like. Only a single sensor130may be included in some embodiments, while in other embodiments, multiple sensors130may be included.

The embedded MCU199may perform a variety of functions. One such function is to convert one or more analog signals to digital form. For example, the output signals from sensors130may be in analog form (analog current or analog voltage). Such analog signals are provided to the MCU199, which includes an analog-to-digital converter (“ADC”) (not shown). The links between the sensors130and the MCU199are referred to as “channels.” The MCU's199ADC converts the received analog sensor channel signals to digital values and provides those digital values to the host system's100host logic120for use in performing its functionality. Some host systems100may have multiple sensors130or other types of devices that produce analog signals needing conversion to digital form. The MCU199includes selection logic (discussed below) that selects analog input channels for conversion to digital form.

FIG. 2illustrates a preferred embodiment of MCU199. The MCU199ofFIG. 2comprises one or more ADCs197. Each ADC197includes ADC channel selection (ADC CH SEL) logic191coupled to an ADC core195, which is coupled to ADC memory193. Other or different components may be present as well in other embodiments. Each ADC197is coupled to the MCU core202, which is coupled to the MCU memory204. The ADC channel selection logic191receives one or more input channels over which analog signals are provided to the corresponding ADC197. As explained below, the interaction of the ADC core195and ADC channel selection logic191controls which input channel to select at any point in time for conversion to a digital value. The digital value is provided to the MCU core202for use in the various functions of the MCU core202. The digital value may be stored in ADC memory193or in MCU memory204for later use. In accordance with various embodiments of the invention, the analog input channels are selected in a way that provides flexibility and efficiency in conversion time, productivity, and choice.

FIG. 3shows a preferred embodiment of ADC channel selection logic191. The embodiment ofFIG. 3shows one or more multiplexers108which receive the analog input channels106, and one solid state switch110for each multiplexer108. The switches108are controlled by an input multiplexer104. In turn, the input multiplexer104is controlled by the bits of one or more channel-select registers102and a data structure103. As illustrated, the data structure103is a table, but any data structure can be used. Preferably, the data structure comprises a plurality of associated field sets. An associated field set is multiple fields or variables, each capable of containing a value, that are associated or linked in some fashion. In the case of the table data structure, an associated field set is a row and the table comprises multiple rows or multiple associated field sets. The channel-select registers102may reside in the ADC core195or in ADC memory193(FIG. 2). The table103may reside in ADC memory193, which is random access memory (“RAM”) in at least one embodiment.

An index number is assigned to each analog input channel. As shown inFIG. 3, the bottom-most channel has an index of 0 while the top-most channel on that particular multiplexer108has an index of 7. Similarly, the bottom-most channel on the next multiplexer has an index of 8, while the top-most channel on that particular multiplexer108has an index of 15. Accordingly, all 32 channels shown in the example ofFIG. 3are uniquely indexed with an integer from 0-31. In various embodiments, any number of input channels106are supported with any number of analog multiplexers108. For example, 32 analog multiplexers108may be provided in some embodiments to support 1024 input channels. As such, the channels would be indexed with the integers from 0 to 1023.

The input multiplexer104causes the analog input channels106to be selectively coupled to the input of the ADC core195one analog input channel106at a time in at least one embodiment. The ADC core195converts the selected analog input channel106to digital form. In various embodiments, the analog input channels chosen for conversion to digital values are based on one or more of three registers102. The three registers correspond to three conversion groups; although in various embodiments, any number of conversion groups may be used. A conversion group is a set of asserted and unasserted channels that potentially can be converted based on the same “trigger.” A trigger can be any event in hardware or software. For example, a trigger may be an elapse of a fixed time, a read or write to memory or a register, a variable crossing a threshold, etc. Any channel may be part of any conversion group while simultaneously being part of any number of other conversion groups. For the example described herein, the conversion groups are referred to as group1, group2, and event group. As such, there are three registers102: group1(“ADG1SEL”) register, group2(“ADG2SEL”) register, or the event group (“ADEVSEL”) register. The ADG2SEL register and the ADEVSEL register behave similarly to the ADG1SEL register, but the corresponding conversion groups need not be identical. Multiple channels are selected for conversion from analog to digital form in one “round” of conversion via ADG1SEL register102. One round of conversion means to convert the asserted channels in a conversion group based on one activation of a trigger.

Table103in conjunction with ADG1SEL register102identifies which channels are asserted, i.e. selected to be converted to digital form, and which channels are unasserted. As shown, ADG1SEL register102contains a binary value. Specifically, position zero of the register102(the least significant bit) contains a 1, position one contains a 1, position two contains a 0, and positions29-31(the most significant bits) each contain a 1. For purposes of discussion of the example ofFIG. 3, all other bit positions in register102contain a 0. Also for purposes of discussion, a 1 refers to an asserted bit, while a 0 refers to an unasserted bit. However, other embodiments, 0 can represent asserted bits and 1 can represent unasserted bits.

Instead of the bit positions in the binary value representing a channel, the bit positions of the binary value of register102correspond with indices of table103as shown in a vertical column on the left of table103. Specifically, each row of table103has a table index of an integer between 0 and 31 corresponding to the 32 analog input channels. Also, each row of table103comprises external and internal channel identifiers as shown as integers in boxes under the heading “Channel identifiers” in table103. An external channel identifier is a value driven to the analog multiplexers108, which are external to the ADC channel selection logic191in at least one embodiment. An internal channel identifier is a value driven to the switches110, which are internal to the ADC channel selection logic191in at least one embodiment.

In the example ofFIG. 3, there are four 8-to-1 multiplexers108. Each multiplexer108has eight input channels and selects a signal on one of the eight input lines on its single output line based on a control signal105from multiplexer104. The same control signal105is provided to all four multiplexers108. Thus, the corresponding input channels on each multiplexer108are selected based on the control signal104. Further, there is switch110for each multiplexer108. Another control signal107, provided by the multiplexer104, selects one of the four switches110. Thus, control signal105selects which input channel to each multiplexer108is selected as an output from the multiplexers and control signal107causes a specific switch110to select one of the four multiplexer108output signals to provide to the ADC core for conversion to digital format.

One round of conversion is conducted in the order of bit positions0-31in the ADG1SEL register102in at least one embodiment. For example, bit position0is selected. As such, the row with an index of 0 is read from the table103. The external channel identifier is 1. As such, the channels in position1(one above the bottom) on each analog multiplexer108have the potential to be selected. The internal channel identifier is also 1. As such, the analog multiplexer108in position1(one above the bottom) is selected because the corresponding switch108is closed. As a result, the channel with a channel index of 9 is selected for conversion and converted.

Next, bit position1in register102is selected. As such, the row with an index of 1 is read from the table103. The external channel identifier is 4. As such, the channels in position4(fifth from the bottom) on each analog multiplexer108have the potential to be selected. The internal channel identifier is 2. As such, the analog multiplexer108in position2(third from the bottom) is selected because the corresponding switch108is closed. As a result, the channel with a channel index of 20 is selected for conversion and converted.

Next, bit positions2-28are not selected. No action is taken.

Next, bit position29is selected. As such, the row with an index of 29 is read from the table103. The external channel identifier is 5. As such, the channels in position5(sixth from the bottom) on each analog multiplexer108have the potential to be selected. The internal channel identifier is 1. As such, the analog multiplexer108in position1(one above the bottom) is selected because the corresponding switch108is closed. As a result, the channel with a channel index of 13 is selected for conversion and converted. Note that channel20, having a higher index, was converted prior to channel13, having a lower index, in this round.

Next, bit position30is selected. As such, the row with an index of 30 is read from the table103. The external channel identifier is 7. As such, the channels in position7(the top) on each analog multiplexer108have the potential to be selected. The internal channel identifier is 3. As such, the analog multiplexer108in position3(the top) is selected because the corresponding switch108is closed. As a result, the channel with a channel index of 31 is selected for conversion and converted.

Next, bit position31is selected. As such, the row with an index of 31 is read from the table103. The external channel identifier is 0. As such, the channels in position0(the bottom) on each analog multiplexer108have the potential to be selected. The internal channel identifier is 2. As such, the analog multiplexer108in position2(third from the bottom) is selected because the corresponding switch108is closed. As a result, the channel with a channel index of 16 is selected for conversion and converted.

In the preceding example, 5 channels were converted in the round. The order of conversion was channels9,20,13,31, and16. If the row with the index of 31 was re-written to comprise an internal channel identifier of 1 and an external channel identifier of 1 (similar to the row with the index of 0), then the order of conversion on the next round, assuming the same bit positions are asserted, would be channels9,20,13,31, and9. Specifically, channel9would be selected and converted twice to digital form.

FIG. 4illustrates how the table103is implemented in ADC memory193in at least one embodiment. Each bit position of ADEVSEL register102represents an address offset index corresponding to a row, just as in table103. An address offset is the distance away from a reference location in memory. Each row comprises 16 bits, as illustrated in the header row. Each row comprises contains an external 5-bit channel identifier (“EV_EXT_CHN_MUX_SEL”) and an internal 5-bit channel identifier (“EV_INT_CHNSEL”). Instead of decimal values as in table103, the internal and external channel identifiers are binary values. The external channel identifier occupies bits8-12, and the internal channel identifier occupies bits0-4.

Here, the table starts at 0x00, corresponding to bit position0. Next, bit position1corresponds to the row identified with address offset 0x02 and so on until bit position31, which corresponds to the row identified with address offset 0x3E. Next at address offset 0x40, the row corresponding to bit position0for ADG1SEL begins. Next at address offset 0x80, the row corresponding to bit position0for ADG2SEL begins.

In at least one embodiment, the bit positions in a register102correspond to address offsets in memory in a one-to-one ratio. Additionally, the memory is random access memory (“RAM”) of the MCU, and an amount of each address offset is proportional to the significance of the corresponding bit within the binary value.

As such, table103in conjunction with ADG1SEL register102allows a channel identified with a higher index to be converted by the ADC core195before a channel identified with a lower index in the same round of conversion. Also, if each bit in the binary value represented an analog input channel, e.g. position0represented analog input channel0; position1represented analog input channel1; etc., the ADC is not restricted to converting the round in order of increasing significance of each asserted bit. That is, the ADC197would not convert channel0first, channel1second, etc. Rather, the channels can be converted in any order including a customizable order.

Six bits in each row are reserved in at least one embodiment. For example as illustrated, bits5-7and13-15are reserved in each row ofFIG. 4. If not reserved, there are many uses for the bits. For example, the bits can be used to select a number of times to convert one channel in the one round of conversion. Because this region is implemented as a MCU CORE-writeable memory, the order of channels to be converted is easily configured by writing channel identifier values at the address offsets. Just as illustrated in the example using table103, if the value at one address offset is written such that it is equal to a second value at a second address offset, then when both corresponding bit positions are asserted in the register, the same channel is selected twice in one round of conversion. In this way, the same channel can be selected as many times as there are bits in the register for one round of conversion.

In at least one embodiment, a sequencer controls the order and the timing of conversions. Additionally, the conversion groups may be configured for a continuous conversion mode. Continuous conversion mode begins on a trigger, and results in one round of conversion after another until another trigger halts conversion.

The ADC RAM can be initialized automatically using a port in at least one embodiment. Additionally, the initialization can be triggered via one clock pulse. By keeping all input channel-select registers programmed to 0, the ADC will not be in any conversion modes during initialization. The length of the initialization process depends upon the depth of RAM present in the ADC because the entire RAM is initialized to 0 in at least one embodiment. Another pulse indicates that ADC RAM is fully initialized, and a dedicated bit can indicate the status of initialization. If parity memory locations are present, then the parity memory locations corresponding to each memory location can be initialized as well.

Data can be read out of a memory region by either the MCU CORE or, if included, a direct memory access (“DMA”) controller. Each memory region can be read at the same time as a new conversion result is stored in it by the ADC197. If there is an attempt to read out more conversion results than are stored in a conversion group's buffer, an empty flag bit can be set. An empty location is defined as one that does not contain any valid conversion data not yet read. The empty bit can be checked to verify that the conversion data is indeed valid.

In at least one embodiment, the ADC197generates one DMA request for each conversion result written into a conversion group's memory buffer. Therefore, an empty buffer read will not occur during normal operation in this embodiment. However, the empty flag can be checked as a precaution. Additionally, a DMA request can be generated for a block of conversions instead of for each conversion. The number of blocks of conversion is programmable for each conversion group. Finally, there is an option to generate a DMA request when all channels selected for conversion in a group have been converted and the results are stored in the ADC memory193.

If the MCU CORE is used to read from a conversion group's memory buffer, a load multiple (“LDM”) instruction enables the loading of multiple registers from memory with back-to-back read operations. Finally, a group memory overrun occurs when a memory region is full and the MCU core attempts to write data into the region while no data is being read from the region. If this occurs, the ADC memory193blocks the write (does not allow an overwrite to occur) and goes into an “overrun” state. In the overrun state, no new data can be written to the conversion group's memory region (new conversions are lost), but the data already in the region can be read either by the MCU CORE or DMA. Alternatively, the region can be either completely read out or discarded (allowing the data to be overwritten).

Conversion groups1and2are software-triggered in at least one embodiment. A conversion in these groups can be started by writing a non-zero value to the ADG1SEL and ADG2SEL registers, respectively. Additionally, the event group is hardware-triggered, and a conversion in the event group starts when a non-zero value is present in the ADEVSEL register. In both cases, the MCU core202may initiate the writing of the non-zero value based on the trigger and may reset the registers102to zero when conversion is complete. In at least one embodiment, the registers102are registers of the MCU199; although in other embodiments, the registers102are registers of the ADC197. In various embodiments, each of the conversion groups is hardware and software-triggered. Any channel can be selected in any group, and same channel can be selected in more than one group. It is also possible to select all channels or no channels within a group in at least one embodiment.

In at least one embodiment, a microcontroller199comprises two or more analog-to-digital converter (“ADCs”). Each ADC197shares the same input channels; although in other embodiments, each ADC197has unique input channels. Each ADC197comprises three input channel-select registers for a total of six input channel-select registers corresponding to six conversion groups. Additionally, the ADC197has an eight, ten, or twelve-bit resolution with high and low reference voltages. The total sample/hold/convert time is 600 ns, and shift operations can be saved by using only the eight or ten most significant bits of the conversion result. In at least one embodiment, the plurality of address offsets begins 8 kilobytes from an address that begins storing results of conversion by the ADC197.

FIG. 5illustrates a method500beginning at502and ending at510. In at least one embodiment, a trigger starts the method500. At504, a binary value in a channel select register102is read. At506, an address offset is determined for each asserted bit in the binary value. At508, multiple channels are selected for conversion in one round of conversion by an analog-to-digital converter (“ADC”)197based on the value. In at least one embodiment, a channel identified with a higher index is converted by the ADC core195before a channel identified with a lower index in the same round of conversion. Selecting multiple channels for conversion comprises selecting a channel based on a value at an address offset in at least one embodiment. The same channel can be selected more than once in the same round of conversion. Specifically, if two values at two address offsets are equal, then the corresponding channel will be selected more than once if each corresponding bit is asserted.