Jitter injection circuit, pattern generator, test apparatus, and electronic device

Provided is a jitter injection circuit that generates a jittery signal including jitter, including a plurality of delay circuits that receive a supplied reference signal in parallel and that each delay the received reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit. In the jitter injection circuit the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period of the jittery signal.

BACKGROUND

1. Technical Field

The present invention relates to a jitter injection circuit, a pattern generator, a test apparatus, and an electronic device. More particularly, the present invention relates to a jitter injection circuit that generates a jittery signal containing jitter, a pattern generator that generates a data signal containing jitter, a test apparatus that tests a device under test using a test signal into which jitter is injected, and an electronic device provided with a self diagnostic section that tests a circuit under test using a test signal into which jitter is injected.

2. Related Art

A jitter tolerance testing is a type of testing performed for high speed communication devices and high speed serial I/O devices. For example, according to a recommendation from the ITU-T, a testing is defined in which jitter tolerance testing is performed by injecting jitter having a frequency of several hundred MHz into the communication data.

As a method for injecting jitter into a high frequency signal, a method is considered in which jitter is injected into a clock signal generated by a voltage controlled oscillator by injecting a modulated signal into a control input of the voltage controlled oscillator, and a data signal is then generated using the clock signal.

Another method is considered in which a variable delay circuit is disposed at a stage after a generator that generates a clock signal or a data signal and the jitter is injected by changing the delay control input of the variable delay circuit. An example of a jitter injection method using the variable delay circuit is disclosed in Pamphlet No. WO2007/049365.

During actual implementation of the electronic device, it is important to minimize the bit error ratio caused by the high frequency jitter component. Therefore, it is also desirable that the high frequency jitter be injected into the test apparatus testing the electronic device.

In a case where the jitter is generated by modulating the control input of the voltage controlled oscillator as described above, however, it is difficult to quickly modulate the clock signal with the control input, so that a frequency boundary of the generated jitter is only tens of MHz. In a case where the jitter is generated by changing the delay amount of the variable delay circuit, jitter having high frequency and large amplitude cannot be generated because the variable delay circuit requires time to catch up to the change of the delay setting.

SUMMARY

Therefore, it is an object of an aspect of the innovations herein to provide a jitter injection circuit, a pattern generator, a test apparatus, and an electronic device, which are capable of overcoming the above drawbacks accompanying the related art. The above and other objects can be achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the innovations herein.

According to a first aspect related to the innovations herein, one exemplary apparatus may include a jitter injection circuit that generates a jittery signal including jitter, including a plurality of delay circuits that receive a supplied reference signal in parallel and that each delay the received reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit, the jitter injection circuit wherein the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period to be included in the jittery signal.

According to a second aspect related to the innovations herein, one exemplary apparatus may include a test apparatus that tests a device under test, including a jitter injection circuit that generates a jittery signal containing jitter, a test signal generating section that generates a test signal based on the jittery signal and supplies the generated test signal to the device under test, and a measuring section that measures a response signal output by the performance circuit in response to the test signal and makes a judgment concerning pass/fail of the performance circuit based on the measured response signal. In the test apparatus, the jitter injection circuit includes a plurality of delay circuits that receive a supplied reference signal in parallel and that each delay the received reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit. Furthermore, in the test apparatus, the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period to be included in the jittery signal.

According to a third aspect related to the innovations herein, one exemplary apparatus may include an electronic device that houses a performance circuit and a self diagnostic section that tests the performance circuit. In the electronic device, the self diagnostic section includes a jitter injection circuit that generates a jittery signal containing jitter, a test signal generating section that generates a test signal based on the jittery signal and supplies the generated test signal to the performance circuit, and a measuring section that measures a response signal output by the performance circuit in response to the test signal and makes a judgment concerning pass/fail of the performance circuit based on the measured response signal. Furthermore, in the electronic device, the jitter injection circuit includes a plurality of delay circuits that receive a supplied reference signal in parallel and that each delay the received reference signal by a preset delay amount and a signal generating section that generates each edge of the jittery signal according to a timing of the signal output by each delay circuit. Yet further, in the electronic device, the delay amount of at least one delay circuit is set to be a value different from an integer multiple of an average period to be included in the jittery signal.

According to a fourth aspect related to the innovations herein, one exemplary apparatus may include a pattern generator that generates a data signal that includes both jitter and a predetermined logic pattern, including a plurality of delay circuits that receive a supplied reference signal in parallel and that each delay the received reference signal by a preset delay amount; a signal generating section that generates each edge of the data signal according to a timing of the signal output by each delay circuit; and a delay setting section that determines what multiple of the single bit time of the data signal is used in the delay amount to be set for each delay circuit according to a timing of logic value shifts in a logic pattern to be to be included in the data signal, and sets for each delay circuit a value obtained by adding or subtracting a jitter value to be injected to or from each of the determined delay amounts.

According to a fifth aspect related to the innovations herein, one exemplary apparatus may include a test apparatus that tests a device under test, including a pattern generator that generates a test signal that includes both jitter and a predetermined logic pattern and supplies the test signal to the device under test and a measuring section that measures a response signal output by the device under test in response to the test signal and makes a judgment concerning pass/fail of the device under test based on the measured response signal. In the test apparatus, the pattern generator includes a plurality of delay circuits that receive a supplied reference signal in parallel and that each delay the received reference signal by a preset delay amount; a signal generating section that generates each edge of the test signal according to a timing of the signal output by each delay circuit; and a delay setting section that determines what multiple of the single bit time of the test signal is used in the delay amount to be set for each delay circuit according to a timing of logic value shifts in a logic pattern to be to be included in the test signal, and sets for each delay circuit a value obtained by adding or subtracting a jitter value to be injected to or from each of the determined delay amounts.

According to a sixth aspect related to the innovations herein, one exemplary apparatus may include an electronic device that that houses a performance circuit and a self diagnostic section that tests the performance circuit. In the electronic device, the self diagnostic section includes a pattern generator that generates a test signal that includes both jitter and a predetermined logic pattern and supplies the test signal to the device under test and a measuring section that measures a response signal output by the performance circuit in response to the test signal and makes a judgment concerning pass/fail of the performance circuit based on the measured response signal. Furthermore, in the electronic device, the pattern generator includes a plurality of delay circuits that receive a supplied reference signal in parallel and that each delay the received reference signal by a preset delay amount; a signal generating section that generates each edge of the test signal according to a timing of the signal output by each delay circuit; and a delay setting section that determines what multiple of the single bit time of the test signal is used in the delay amount to be set for each delay circuit according to a timing of logic value shifts in a logic pattern to be to be included in the test signal, and sets for each delay circuit a value obtained by adding or subtracting a jitter value to be injected to or from each of the determined delay amounts.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1shows an exemplary configuration of a jitter injection circuit100according to an embodiment. The jitter injection circuit100is a circuit that generates a jittery signal containing jitter, and is provided with a plurality of delay circuits10disposed in parallel, a signal generating section20, and a delay setting section30. When generating the jittery signal, the jitter injection circuit100of the present embodiment generates the jittery signal using the plurality of delay circuits10having fixed delay amounts. More specifically, the jittery signal containing high frequency jitter can be easily generated because the jittery signal can be generated without changing the delay amounts of the delay circuits10.

The plurality of delay circuits10receive in parallel a supplied reference signal CLK0and each delay circuit10delays the signal by a prescribed delay amount. The reference signal CLK0may be a periodic signal having a predetermined period.

The signal generating section20generates each edge of the jittery signal to be output according to the reference signal CLK0and a timing of the signal output by each delay circuit10. For example, the signal generating section20generates one edge of the jittery signal based on the edge of the signal output by one of the delay circuits10. Because of this, a position of each edge of the jittery signal can be set according to the delay amount of the corresponding delay circuit10, so that jitter corresponding to the delay amounts of the plurality of delay circuits10can be injected into the jittery signal.

The signal generating section20of the present embodiment may be an exclusive OR circuit that outputs an exclusive OR of a plurality of signals (from CLK0to CLKn). The exclusive OR of the plurality of signals may be a signal that is logic H during a period in which an odd number of signals from among the plurality of signals (from CLK0to CLKn) indicate logic H and is logic L during a period in which an even number of signals from among the plurality of signals (from CLK0to CLKn) indicate logic H. When a transition timing of each input signal is different, the signal output by the signal generating section20is a signal in which the logic value sequentially inverts at the transition timing of each input signal.

More specifically, the signal generating section20outputs a jittery signal in which the logic values are sequentially inverted at the timing of the delay amounts τ1, τ2, τ3, . . . , τk, . . . , τn (note that τk is the delay amount set by the delay circuit10at a k-th stage) designated by each of the delay circuits10. Here, by setting at least one of the delay amounts τk to be a value different than an integer multiple of the average period TOUTOf the jittery signal (a mean duration of each bit in the jittery signal), a jittery signal can be generated that includes timing jitter according to the delay amount τk. The signal including the timing jitter may refer to a signal in which each edge timing varies in relation to an ideal timing.

For example, in a case where timing jitter having a jitter frequency of fJ(=2 fOUT/(n+1)) and a sine wave with a jitter amplitude AJis injected into the jittery signal, the delay amount τk to be set for the delay circuit10at the k-th stage is calculated by the following formula. The delay setting section30may set the delay amounts of the plurality of delay circuits10according to the formula below.

τk=k2⁢⁢fout+AJ⁢sin⁡(π⁢⁢fJ⁢kfout)
It should be noted that foutindicates the frequency of the jittery signal and is expressed by fout=1/(2 Tout).

The delay setting section30sets the prescribed delay amount in advance for each delay circuit10. Here, in a case where the delay amount of each delay circuit10is set in advance by the jitter injection circuit100to be the predetermined delay amount, the jitter injection circuit100need not be provided with the delay setting section30.

The delay setting section30may set for each delay circuit10a delay amount according to the timing jitter to be injected into each edge of the jittery signal. For example, the delay setting section30may set as the delay amount of each delay circuit10a value obtained by adding or subtracting a value of the timing jitter to be included at each edge of the jittery signal to or from an integer multiple of the average period TOUTto be included in the jittery signal.

Because the delay amount of each delay circuit10is the corresponding edge timing in the jittery signal, a k-th edge of the jittery signal includes timing jitter of τk-k TOUT. The delay setting section30of the present embodiment fixes the delay amounts of the delay circuits10while the jitter injection circuit100generates the jittery signal.

FIG. 2is a timing chart showing an exemplary operation of the jitter injection circuit100shown inFIG. 1. In the present embodiment, an operation of the jitter injection circuit100provided with five stages of delay circuits10is described. Furthermore, the following description uses a signal in which the logic value repeatedly inverts at predetermined time intervals TINas the reference signal CLK0.

The first delay circuit10-1delays the reference signal CLK0by the delay amount τ1and outputs the thus delayed signal. The delay amount τ1may be a value calculated by adding or subtracting a prescribed jitter value to or from the average period (or the average pulse width, which is also possible in all following cases) TOUTof the jittery signal OCLK5to be generated.

Here, the delay setting section30may obtain the average period TOUTof the jittery signal OCLK5by dividing a pulse width (bit duration) TINof the reference signal CLK0by a value equal to the parallel number of the delay circuit10plus one. The delay setting section30may be provided with waveform data of the jitter to be injected. The delay setting section30may set the delay amount of each delay circuit10based on the average period TOUTand the waveform data.

The second delay circuit10-2delays the reference signal CLK0by a delay amount τ2and outputs the thus delayed signal. The delay amount τ2may be a value calculated by adding or subtracting a prescribed jitter value to or from a value that is double the average period TOUTof the jittery signal OCLK5. Furthermore, the delay amount τ2may be a value different from the delay amount τ1.

In the same manner, each delay circuit10delays the reference signal by a value obtained by adding or subtracting a prescribed jitter value to or from an integer multiple of the average period TOUTof the jittery signal OCLK5. By doing this, a plurality of signals indicating each edge timing of the jittery signal to be generated can be input to the signal generating section20, as shown inFIG. 2. The signal generating section20generates a signal in which the logic value sequentially inverts at time intervals τ1, τ2, τ3, τ4, τ5, which correspond to the delay amount of each delay circuit10.

Furthermore, by causing the maximum delay amount (τ5) in the plurality of delay circuits10to be less than the pulse width TINof the reference signal, a jittery signal into which jitter having the prescribed pattern is repeatedly injected for each period of the pulse width TINof the reference signal can be generated easily. In such a case, the signal generating section20generates a plurality of bits of the jittery signal for each single bit of the reference signal.

The plurality of delay circuits10are disposed to correspond to the plurality of edges of the jittery signal generated for each bit of the reference signal. The delay amount of each delay circuit10designates the corresponding edge timing.

In the present embodiment, as shown inFIG. 2, a jittery signal can be generated in which the waveform having the edge timing of τ1, τ2, τ3, τ4, τ5is repeated for each period of the pulse width TINof the reference signal. Because the jitter is generated in the jitter injection circuit100of the present embodiment without dynamically changing the delay times of the delay circuits10, high frequency jitter can be generated easily.

Because the jitter pattern is repeated for each pulse width TINof the reference signal in the jitter injection circuit100of the present embodiment, the frequency of the generated jitter is substantially equal to an integer multiple of the reference signal bit rate (1/TIN).

FIG. 3shows an exemplary configuration of another jitter injection circuit100. The jitter injection circuit100of the present embodiment is further provided with a reference period control section40and selecting sections12in addition to the configuration of the jitter injection circuit100described in relation toFIG. 1. The jitter injection circuit100may have a configuration in which either the reference period control section40or the selecting sections12are not provided.

As described in relation toFIG. 2, it is desirable that the maximum delay amount in the plurality of delay circuits10be less than the pulse width of the reference signal CLK0. In this case, the period of the jitter injected into the jittery signal is equal to the pulse width of the reference signal CLK0or a fraction thereof having a numerator of one. The reference period control section40may control the pulse width of the reference signal CLK0provided to the plurality of delay circuits10according to the period of the jitter to be injected into the jittery signal.

As further described in relation toFIG. 2, the average period (average bit duration) of the jittery signal is a value calculated by dividing the pulse width of the reference signal by a value obtained by adding one to the parallel number n of the delay circuit10. The selecting sections12may select a plurality of signals supplied to the signal generating section20from among the output signals CLK(k) of the plurality of delay circuits10, according to the average period to be had by the jittery signal. For example, in a case where a jittery signal is generated in which the average pulse width is set to 1/a of the pulse width of the reference signal, the selecting sections12select the reference signal CLK0and the output signals CLK1to CLK(a−1) of the delay circuits10and supplies the selected signals to the signal generating section20.

FIG. 4is a timing chart showing an exemplary operation of the jitter injection circuit100shown inFIG. 3. The jitter injection circuit100of the present embodiment has an average period of TIN/4 and generates a jittery signal in which the period of the injected jitter is TIN. The reference period control section40controls the reference signal such that the period (pulse width) of the reference signal CLK0becomes TIN.

Furthermore, because a=4 in the present embodiment, the selecting sections12select the reference signal CLK0and the output signals CLK1to CLK3of the delay circuits10and supplies the selected signals to the signal generating section20. The delay setting section30sets for the first to third delay circuits10delay amounts τ1, τ2, τ3obtained by adding or subtracting each jitter value corresponding to the jitter waveform to be injected to or from the an integer multiple of the average period TIN/4 of the jittery signal. The jitter values according to the jitter waveform to be injected may be values obtained by sequentially sampling the jitter waveform having a period of TINwith a clock having a period of TIN/(n+1) (where n is the parallel number of the delay circuit10). By using such settings, a jittery signal is generated having an average period of TIN/4 and in which the period of the injected jitter is TIN.

FIG. 5is a timing chart showing another exemplary operation of the jitter injection circuit100shown inFIG. 3. In the example described in relation toFIG. 4, the selecting sections12supply an even number of signals to the signal generating section20. The selecting sections12of the present embodiment supply an odd number of signals to the signal generating section20.

In such a case, the waveform of the jittery signal corresponding to areas before and after the edge of the reference signal CLK0is inverted. In the example shown inFIG. 5, the waveform of the jittery signal is inverted in the period from E0to E3in relation to the period E3to E6. The selecting sections12may select an even number or an odd number of signals to supply to the signal generating section20depending on the intended use of the jittery signal.

FIG. 6shows another exemplary configuration of the jitter injection circuit100. The jitter injection circuit100according to the present embodiment is further provided with a pulse generating section24in addition to the configuration of any one of the jitter injection circuits100described in relation toFIGS. 1 to 5.FIG. 6shows an example in which the pulse generating section24is added to the configuration of the jitter injection circuit100shown inFIG. 1.

The pulse generating section24receives the reference signal CLKIN, generates a pulse having a prescribed pulse width for each rising edge of the reference signal CLKIN, and outputs the generated pulse as the reference signal CLK0. The pulse generating section24supplies the reference signal CLK0to the signal generating section20and the plurality of delay circuits10in parallel.

FIG. 7is a timing chart showing an exemplary operation of the jitter injection circuit100shown inFIG. 6. As described above, the pulse generating section24outputs the pulse having the prescribed pulse width for each rising edge of the reference signal CLKIN. It is desirable that the pulse width be less than the maximum delay amount set for the plurality of delay circuits10.

Each delay circuit10receives the pulse output by the pulse generating section24, delays the received pulse by the delay amount τk set for each delay circuit10, and outputs the thus delayed pulse. By doing this, a jitter signal can be easily generated in which timing pulses are arranges according to the delay amounts of the plurality of delay circuits10, as shown inFIG. 7.

The signal generating section20of the present embodiment may be an OR circuit that outputs an OR of the plurality of input signals. The OR of the plurality of input signals may be a signal that is logic H when one of the plurality of input signals indicates logic H and is logic L when all of the input signals indicate logic L. Because the delay setting section30sets in advance a delay amount according to the timing jitter waveform to be injected for each delay circuit10, timing jitter can be injected at each edge of the jittery signal.

Furthermore, the jitter injection circuit100may be further provided with an input switching section that switches between inputting the reference signal CLKINand inputting the pulse generated by the pulse generating section24to the plurality of delay circuits10and the signal generating section20. By using such a configuration, a selection can be made as to whether the jitter injection circuit100is made to operate as described in relation toFIGS. 1 to 5or made to operate as described in relation toFIGS. 6 and 7.

FIG. 8shows another exemplary configuration of the jitter injection circuit100. The jitter injection circuit100of the present embodiment is further provided with a low frequency jitter injecting section80in addition to the configuration of any one of the jitter injection circuits100described in relation toFIGS. 1 to 7. InFIG. 8, the low frequency jitter injecting section80is added to the configuration of the jitter injection circuit100shown inFIG. 1.

The low frequency jitter injecting section80injects into the reference signal jitter that has a frequency lower than a frequency of the jitter generated by the plurality of delay circuits10and the signal generating section20, and inputs the thus achieved signal into the plurality of delay circuits10and the signal generating section20. The low frequency jitter injecting section80may, for example, inject the low frequency jitter into the reference signal using a variable delay circuit in which the delay amount changes dynamically.

FIG. 9shows another exemplary configuration of the jitter injection circuit100. The jitter injection circuit100of the present embodiment is further provided with a low frequency jitter injecting section80in addition to the configuration of any one of the jitter injection circuits100described in relation toFIGS. 1 to 7. InFIG. 9, the low frequency jitter injecting section80is added to the configuration of the jitter injection circuit100shown inFIG. 1.

The low frequency jitter injecting section80of the present embodiment further injects the low frequency jitter described in relation toFIG. 8into the jittery signal output by the signal generating section20. By using the configurations described above, jitter having a wide bandwidth can be generated easily. Instead of providing the low frequency jitter injecting section80, the delay setting section30may change the delay amount of each delay circuit10by a frequency sufficiently lower than the frequency of the reference signal.

FIG. 10shows an exemplary configuration of a data jitter injection circuit200according to an embodiment. The data jitter injection circuit200is a circuit that injects jitter into a data signal and is provided with the jitter injection circuit100and a data jitter injecting section110.

The jitter injection circuit100may be the same as any one of the jitter injection circuits100described in relation toFIGS. 1 to 9. The data jitter injecting section110receives the jittery signal from the jitter injection circuit100and generates a data signal having a bit boundary designated by each edge timing of the jittery signal. Through such a configuration, data jitter can be injected into the data signal.

The data jitter injecting section110of the present embodiment is a LFSR (Linear Feedback Shift Register) that includes a plurality of flip-flops112and exclusive OR circuits114. The plurality of flip-flops112are connected in a cascading manner and commonly receive the jittery signal. Each flip-flop112acquires input data according to one or both of the rising edge and the falling edge of the jittery signal and supplies the acquired data to the flip-flop112at a stage immediately thereafter.

The exclusive OR circuits114generate an exclusive OR of the output signals from two of the flip-flops112selected according to a generator polynomial of the LFSR and supply the exclusive OR to the first stage flip-flop112. By using such a configuration, PRBS (Pseudo-Random Binary Sequence) data into which jitter is injected can be generated.

FIG. 11shows another exemplary configuration of the data jitter injecting section110. The data jitter injecting section110of the present embodiment includes a pattern memory120and a flip-flop122. The pattern memory120stores thereon in advance a logic pattern to be included in the data signal.

The flip-flop122acquires the logic pattern stored in the pattern memory120according to one or both of the rising edge and the falling edge of the jittery signal supplied from the jitter injection circuit100and outputs the acquired logic pattern. By using such a configuration, the jitter can be injected into a data signal having any arbitrary logic value pattern.

Instead of the configurations shown inFIGS. 10 and 11, the data signal into which the jitter is injected can be generated using any one of the jitter injection circuits100described in relation toFIGS. 1 to 9.

FIG. 12is a timing chart showing an exemplary operation of a jitter injection circuit100that injects jitter into a data signal. In the present embodiment, an example is described in which the jitter is injected into a data signal in which the logic pattern “11101000” is repeated. In this case, the reference period control section40may generate a reference signal having a period substantially equal to a value obtained by multiplying the number of bits in the repeating logic pattern by the time of a single bit of the data signal.

The selecting sections12supply to the signal generating section20a number of signals equal to the number of times the logic value shifts in the repeating logic pattern “11101000.” In the present embodiment, because the logic value changes three times in the repeating logic pattern “11101000,” the selecting sections12select the reference signal CLK0and the output signals CLK1to CLK3and supplies the selected signals to the signal generating section20.

The delay setting section30sets the delay amount for each delay circuit10based on the number of consecutive bits having the same logic value in the logic value pattern to be included in the jittery signal. For example, in the repeating logic pattern “11101000” to be included in the jittery signal of the present embodiment, the first logic value “1” is consecutive for three bits. Therefore, the delay setting section30sets as the delay amount τ1of the first delay circuit10-1a value obtained by adding or subtracting the jitter value to be injected to or from a time of three bit units (three times the average period of the jittery signal) in the jittery signal.

Next in the logic pattern “11101000” is one bit having a logic value of zero. Therefore, the delay setting section30sets as the delay amount τ2of the second delay circuit10-2a value obtained by adding or subtracting the jitter value to be injected to or from an OR of the delay amount τ1and the time of one bit unit in the jittery signal.

In the same manner, the delay setting section30sets as the delay amount τ3of the third stage delay circuit10-3a value obtained by adding or subtracting the jitter value to be injected to or from an OR of the of the delay amount τ2and a time of one bit unit in the jittery signal. Through such a process, a data signal can be generated into which jitter is injected by using the jitter injection circuit100.

FIG. 13shows another exemplary configuration of the jitter injection circuit100. The jitter injection circuit100of the present embodiment is further provided with a delay amount calculating section60, a switching section70, a switch16, and a switch18in addition to the configuration of any one of the jitter injection circuits100described in relation toFIGS. 1 to 12, and measures the delay amount of each delay circuit10.FIG. 13shows a configuration in which the jitter injection circuit100described in relation toFIG. 3is provided with the delay amount calculating section60, the switching section70, the switch16, and the switch18.

During measuring of the delay amount of each delay circuit10, the switching section70switches the transmission path of the output signal of each delay circuit10such that the signal forms a loop that returns to the input of the delay circuit10. In the present embodiment, the switching section70operates together with the switch18and the selecting sections12disposed to correspond to each delay circuit10to form the loop.

In a case where the switching section70of the present embodiment is disposed at a stage after the signal generating section20to measure the delay amount of each delay circuit10, the signal output by the signal generating section20is input to each delay circuit10via the switch18. A loop is formed in which the output signal of a delay circuit10whose delay amount is to be measured is fed back to the input of the same delay circuit10because the corresponding selecting section12supplies to the signal generating section20the output signal of the delay circuit10and does not supply to the signal generating section20the output signals of other delay circuits10.

The switch18selects whether the reference signal or a feedback signal from the switching section70is supplied to each delay circuit10. The switch18selects the reference signal when the jittery signal is generated and selects the feedback signal when the delay amount of each delay circuit10is being measured.

The switch16supplies a logic value H to one of the inputs of the signal generating section20when the delay amount of each delay circuit10is measured. By doing this, the logic value H and the signal from the delay circuit10to be measured are input to the signal generating section20. In other words, when the delay amount of each delay circuit10is measured, the signal generating section20inverts the signal from the delay circuit10to be measured and outputs the thus inverted signal.

The delay amount calculating section60calculates the delay amount of a given delay circuit10based on the period of the signal transmitted in the loop formed by the switching section70, the switch18, the delay circuit10to be measured, the selecting section12, and the signal generating section20. For example, the delay amount calculating section60may measure the period of the signal transmitted from the third switching section70-3to the first switching section70-1. Furthermore, the delay amount calculating section60may input a single pulse into the loop to measure the period in which the pulse circles through the loop. The thus measured period corresponds to the delay amount in the delay circuit10.

The delay setting section30sets the delay amount in each delay circuit10further based on the delay amounts calculated by the delay amount calculating section60. The selecting sections12may sequentially select the output signals of each delay circuit10, and the delay amount calculating section60may sequentially measure the delay amounts of each delay circuit10. Through such a configuration, the waveform of the jitter to be injected into the jittery signal can be accurately adjusted.

FIG. 14shows an exemplary configuration of a test apparatus300according to an embodiment coupled with a device under test400. The test apparatus300is an apparatus that tests the device under test400, such as a semiconductor circuit, and is provided with the jitter injection circuit100, a test signal generating section310, and a measuring section340.

The jitter injection circuit100may be the same as any one of the jitter injection circuits100described in relation toFIGS. 1 to 13. As described above, the jitter injection circuit100can generate a jittery signal that includes high frequency jitter.

The test signal generating section310generates a test signal based on the jittery signal and supplies the generated test signal to the device under test400. For example, the test signal generating section310may use the jittery signal as a clock to generate the test signal. The test signal generating section310of the present embodiment includes a pattern generating section320and an equalizer330.

The pattern generating section320includes a predetermined logic pattern and generates a test signal that has a bit boundary designated by each edge of the jittery signal. Through such a configuration, a test signal including high frequency jitter can be generated. The equalizer330compensates the waveform of the test signal in advance according to transmission loss between the test signal generating section310and the device under test400.

The measuring section340makes a judgment concerning pass/fail of the device under test400by measuring a response signal output by the device under test400in response to the test signal. For example, the measuring section340may make a judgment concerning pass/fail of the device under test400based on whether the logic pattern of the response signal matches a prescribed expected value pattern.

The jitter tolerance of the device under test400can be tested by adjusting the frequency and amplitude of the jitter generated by the jitter injection circuit100. For example, the test apparatus300can test whether the device under test400fulfills the jitter tolerance specifications by causing the jitter injection circuit100to generate jitter having a frequency and amplitude designated by the jitter tolerance specifications of the device under test400. The device under test400can be tested using a test signal that includes high frequency jitter.

FIG. 15shows exemplary configurations of the pattern generating section320and the measuring section340. The pattern generating section320of the present embodiment generates a test signal that includes a PRBS (Pseudo-Random Binary Sequence) logic pattern by using an LFSR (Linear Feedback Shift Register). The pattern generating section320includes a plurality of flip-flops322and an exclusive OR circuit324.

Each flip-flop322receives the jittery signal from the jitter injection circuit100in parallel, acquires the signal output by the flip-flop322at the stage immediately prior according to each edge of the jittery signal, and outputs the acquired signal. The first stage flip-flop322acquires the signal output by the exclusive OR circuit324according to the jittery signal. In a case where the jitter injection circuit100is provided with the pulse generating section24as described in relation toFIG. 6, each flip-flop322may operate according to a rising edge of the jittery signal.

The exclusive OR circuit324outputs as the test signal an exclusive OR of the signals output by the flip-flops322selected according to a generator polynomial of the LFSR. By using such a configuration, a PRBS test signal having jitter according to the jittery signal can be generated.

The measuring section340generates the expected value pattern using the LFSR having the same configuration as that of the pattern generating section320. The measuring section340includes a plurality of flip-flops342, an exclusive OR circuit344, and a comparing section346.

The plurality of flip-flops342and the exclusive OR circuit344may have the same function and configuration as the plurality of flip-flops322and the exclusive OR circuit324. However, each flip-flop342operates according to a clock signal into which jitter is not injected. Furthermore, the first stage flip-flop342acquires the response signal of the device under test400according to the clock signal. By using such a configuration, the exclusive OR circuit344can sequentially generate the logic values to be indicated by the response signal of the device under test400.

The comparing section346compares the logic value of the response signal of the device under test400to the logic value of the signal output by the exclusive OR circuit344and outputs an error signal that indicates whether the aforementioned logic values match. Furthermore, the bit error ratio of the device under test400may be measured by measuring a rate at which non-matching logic values occur with the comparing section346.

FIG. 16shows an exemplary configuration according to an electronic device500of an embodiment. The electronic device500may be a device such as a semiconductor chip that outputs an output signal in response to an input signal, for example. The electronic device500is provided with an equalizer520, a self diagnostic section510, a multiplexer530, and a performance circuit540.

The equalizer520compensates the waveform of the input signal according to signal loss in the transmission path of the input signal. The multiplexer530selects the input signal and supplies the selected signal to the performance circuit540when the electronic device500is operating normally.

The self diagnostic section510tests the performance circuit540when the electronic device500performs a self diagnosis. The self diagnostic section510includes the jitter injection circuit100, the test signal generating section310, and the measuring section340. The jitter injection circuit100, the test signal generating section310, and the measuring section340may have the same function and configuration as the elements described using the same reference numerals inFIG. 14. The jitter injection circuit100may receive an input signal supplied from the outside as the reference signal.

The multiplexer530selects the test signal generated by the self diagnostic section510and supplies the selected test signal to the performance circuit540when the electronic device500performs the self diagnosis. The measuring section340makes a judgment concerning pass/fail of the performance circuit540based on the response signal of the performance circuit540.

Through the configuration described above, the electronic device500performs a self diagnostic to determine pass/fail of the performance circuit540. Furthermore, because high frequency jitter can be generated by the jitter injection circuit100, the electronic device500can test the performance circuit540using the test signal that contains the high frequency jitter.

FIG. 17is a flow chart showing an exemplary operation of the test apparatus300. The test apparatus300of the present embodiment performs a test in which low frequency jitter within an operational bandwidth of the device under test400is used and a test in which high frequency jitter outside the operational bandwidth of the device under test400is used.

First, the test apparatus300tests the device under test400using the low frequency jitter within the operational bandwidth of the device under test400(S600). In this case, the jitter injection circuit100generates a first jittery signal into which is injected jitter that includes the frequency that is within the operational bandwidth of the device under test400. For example, in a case where the device under test400includes a PLL circuit, the jitter injection circuit100generates a jittery signal that includes jitter having a frequency within the loop bandwidth of the PLL circuit.

The test signal generating section310supplies the first test signal corresponding to the first jittery signal to the device under test400. Next, the measuring section340makes a judgment concerning pass/fail of the device under test400based on a first response signal output by the device under test400in response to the first test signal. More specifically, the measuring section340makes a judgment as to whether a bit error occurs in the first response signal (S602). In a case where a bit error occurs, the measuring section340determines that the device under test400is a defective product (S610) and ends the testing.

In a case where the bit error does not occur in the low frequency jitter test so that the device under test400is determined to be non-defective, the test apparatus300tests the device under test using the high frequency jitter outside the operational bandwidth of the device under test400(S604). In this case, the jitter injection circuit100generates a second jittery signal that includes jitter having a frequency outside the operational bandwidth of the device under test400. In other words, the jitter injection circuit100sequentially generates the first jittery signal and the second jittery signal.

The test signal generating section310supplies the second test signal corresponding to the second jittery signal to the device under test400. Next, the measuring section340makes a judgment concerning pass/fail of the device under test400based on a second response signal output by the device under test400in response to the second test signal. More specifically, the measuring section340makes a judgment as to whether a bit error occurs in the response signal of the device under test400(S606). In a case where a bit error occurs, the measuring section340determines that the device under test400is a defective product (S610) and ends the testing. In a case where a bit error does not occur, the measuring section340judges the device under test400to be non-defective (S608) and ends the testing.

In the manner described above, the test apparatus300can easily perform testing of jitter tolerance outside of the operational bandwidth of the device under test400because the test apparatus300can easily generate high frequency jitter. Therefore, the test apparatus300can accurately determine pass/fail of the device under test400.

FIG. 18shows another exemplary configuration of the test apparatus300. The test apparatus300of the present embodiment is provided with a pattern generator350, the equalizer330, and the measuring section340. The equalizer330may be the same as the equalizer330described in relation toFIG. 14. The measuring section340measures the response signal of the device under test400to make a judgment concerning pass/fail of the device under test400.

The pattern generator350generates a test signal that includes both jitter and a predetermined logic pattern and supplies the generated test signal to the device under test400. The pattern generator350may be included in the jitter injection circuit100described in relation toFIG. 12and may output the data signal generated by the jitter injection circuit100as the test signal.

FIG. 19shows another exemplary configuration of the electronic device500. The electronic device500of the present embodiment is provided with the equalizer520, the pattern generator350, the measuring section340, the multiplexer530, and the performance circuit540. The equalizer520, the multiplexer530, and the performance circuit540may be the same as the equalizer520, the multiplexer530, and the performance circuit540described in relation toFIG. 16.

The pattern generator350and the measuring section340may be the same as the pattern generator350and the measuring section340described in relation toFIG. 18. Furthermore, the pattern generator350may receive the reference signal from the outside.

As made clear from the above, by using the embodiments of the present invention, a jittery signal that includes high frequency period jitter can be easily generated. Furthermore, by testing a device under test or a performance circuit using the jittery signal, pass/fail of the device under test or the performance circuit can be accurately determined.