POWER SUPPLY SYSTEM AND METHOD OF OPERATING THE SAME

The present disclosure provides a power supply system, including: a power source connected between a first node and a second node for applying an input voltage; a first circuit, connected between the first node and a second circuit; and configured to suppress oscillation caused by load variation of a load circuit that is connected between the first node and the second circuit, and to supply power to the load circuit when the power source is temporarily off; the second circuit, having a first port connected to the first circuit, a second port connected to the load circuit, and a third port connected to the second node; and configured to charge the first circuit and supply power to the load circuit; and a third circuit, connected between the first circuit and the load circuit; and configured to suppress a current flowing into the second circuit.

TECHNICAL FIELD

The present disclosure generally relates to the technical field of electronic technology, and in particular, to a power supply system and a method of operating the power supply system.

BACKGROUND

This section is intended to provide a background to the various embodiments of the technology described in this disclosure. The description in this section may include concepts that could be pursued, but are not necessarily ones that have been previously conceived or pursued. Therefore, unless otherwise indicated herein, what is described in this section is not prior art to the description and/or claims of this disclosure and is not admitted to be prior art by the mere inclusion in this section.

Some of communication devices, such as Radio Units (RUs), work with a load circuit with dynamic load, which may cause oscillation of the input voltage and the input current from a power supply system. Thus, a capacitor with a larger value capacitance (e.g., 8 mF), also called a holdup capacitor, is necessary to be introduced in the power supply system to suppress the oscillation caused by the dynamic load of the load circuit and supply power to the load circuit when the power source (e.g. denoted as100, as shown inFIG.1) is temporarily off. On the other hand, however, the holdup capacitor may cause a surge current in the power supply system.

Generally, a power supply assisting sub-system as shown inFIG.1, e.g., a hot swap circuit, is used in the power supply system to suppress the input surge current when the communication device is powered on.

As shown inFIG.1, a power supply system10includes a power source100, a power supply assisting sub-system101, and a control logic102, and is configured to supply power to a load circuit11of a communication device (not shown).

The power supply assisting sub-system101includes a holdup capacitor (denoted as Choldup), two Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs, denoted as Q1and Q2respectively), two resistors (denoted as Rs1and Rs2respectively), and a filtering capacitor (denoted as Co). In the power supply assisting sub-system101, the holdup capacitor Choldupand the filtering capacitor Coare respectively connected in parallel with the load circuit11, which is connected between Node 1 (Vin+) and the transistor Q1/Q2; the transistor Q1is connected to the holdup capacitor Choldupand to Node 2 (Vin-) via Rs1, respectively; and the transistor Q2is connected to the holdup capacitor Choldupand to Node 2 (Vin-) via Rs2, respectively. Here, the voltage difference between Node 1 and Node 2 that is applied by the power source100is the input voltage, denoted as Vin.

The holdup capacitor Choldupis used for suppressing the oscillation caused by the dynamic load of the load circuit11and supplying power to the load circuit11when the power source Vinis temporarily off, and has a capacitance much larger than that of the filtering capacitor Co, which is used for filtering interference to the load circuit11.

The transistor Q1may be a big Safe Operating Area (SOA) FET that may be used for linear charging the holdup capacitor Choldupto suppress the surge current while the communication device, such as an RU, is powered on. The transistor Q2may be a low Reducing Drain-Source On-resistance Rdson FET, and may be used for assisting to supply power to the load circuit11when the power supply system10is in a normal operation. The resistor Rs1that is in series with the transistor Q1has a resistance much larger than that of the resistor Rs2that is in series with the transistor Q2.

The control logic102is schematically shown to illustrate a control principle of controlling the power supply assisting sub-system101, which may be implemented in any of appropriate ways. Here, Vgs1and Vgs2are control signals for controlling ON/OFF of the transistors Q1and Q2, respectively. Herein, N-type transistors are taken as an example for illustration only. Thus, the N-type transistors Q1and Q2are respectively turned on by Vgs1and Vgs2in a high level, and turned off by Vgs1and Vgs2in a low level. For P-type transistors, although not described herein, it will be understood that the difference between description on P-type transistors and N-type transistors only consists in that the P-type transistors Q1and Q2are respectively turned on by Vgs1and Vgs2in a low level, and turned off by Vgs1and Vgs2in a high level.

Here, VRS1(=I1*RS1), VRS2(=I2*RS2), and Vds_srepresent feedback signals from the power supply assisting sub-system101, wherein VRS1(=I1*RS1) is associated with the current I1flowing through the transistor Q1, VRS2(=I2*RS2) is associated with the current l2flowing through the transistor Q2; and Vds_srepresents a signal for sensing a voltage difference, denoted as Vds, between the input voltage Vinand the voltage, denoted as Vholdup, across the holdup capacitor (Choldup), i.e., Vds= Vin-Vholdup. Thus, Vds_srepresents a signal for characterizing Vds. When Vdsis smaller than a preset reference threshold (Vds_th), the transistor Q2is triggered by Vds_sto be turned on by Vgs2. The magnitude of Vgs1depends on that of VRS1. When VRS1is larger, VRS1pulls the magnitude of Vgs1down. Once Vgs1is decreased, the flow capability of the transistor Q1is reduced, which in turn causes the current I1to be reduced. A smaller Vgs1(e.g. in a middle level) may enable the transistor Q1to operate in the linear mode, wherein the current I1is proportional to VRs1. In the linear mode, the transistor Q1charges the holdup capacitor (Choldup).

Hereinafter, the operating principle of the power supply assisting sub-system101will be described in conjunction withFIG.2.FIG.2schematically shows an operating timing sequence diagram of the power supply assisting sub-system101.

t0: The power supply system10starts to supply power to the communication device (not shown).

t1~t2: The transistor Q1is turned on by Vgs1in e.g. a middle level (which causes the transistor Q1to operate in the linear mode), and the capacitor Choldupis linear charged through the transistor Q1, wherein the charging current is limited to the current I1(a gray line as shown inFIG.2) by comparing VRS1(=I1*RS1) to a preset reference of control.

t2: When Vds(= Vin- Vholdup) is smaller than Vds_th(a preset reference threshold), the transistor Q2is triggered to be turned on by Vgs2.

t2~t3: When the transistor Q2is turned on at t2, the current flows through the transistor Q2(as seen fromFIG.2, I2that is shown in a black line has a peak during t2~t3) but almost does not flow through the transistor Q1any more (as seen fromFIG.2, I1that is shown in a gray line is decreased to nearly zero during t2~t3), since the resistor Rs1that is in series with the transistor Q1has a resistance much larger than that of the resistor Rs2. The capacitor Choldupis quickly charged to Vinby the current I2, which is small since Vds(= Vin- Vholdup) is small at t2. Meanwhile, VRS1(=I1*RS1) is reduced and may not pull Vgs1down any more. Consequently, Vgs1boosts up to its original high level at t3, and thus the transistor Q1enters a switching mode at t3.

t3~t4: The power supply of the power supply system10is normal at t3with the assistance of the power supply assisting sub-system101, and thus a signal indicating power good is sent out. Accordingly, after a shorter delay at t4, the load circuit11of the communication device works normally under the good power supply of the power supply system10with the assistance of the power supply assisting sub-system101.

However, the power supply assisting sub-system101as shown inFIG.1has some drawbacks:

1. When there is overshoot of the input voltage Vinor the input current Iin, or the power supply assisting sub-system works in a hiccup mode, i.e., repetitive ON and OFF due to the abnormal load, there will be a large input surge current.

2. During the normal operation, the transistor Q2can’t be turned off, since the limited current I1of the transistor Q1is too small to support the load current (i.e., the communication device cannot work) after the transistor Q2is off. Since the transistor Q2is always on during the normal operation of the communication device, the surge current, if appears due to some reasons as mentioned above, would almost flow through the transistor Q2only. However, the transistor Q2can’t suppress the surge current, since it does not have such a current limitation function as the transistor Q1has.

3. Due to the above reasons, very big SOA FETs must be used in the power supply assisting sub-system of the power supply system to sustain the surge current, which increases cost.

For example, if lighting attacks an RU’s input port, the input residual voltage could be two times larger than normal operating voltage, it also induces the input surge current as large as hundreds Ampere if there are holdup capacitors with large capacitance. The components used must have higher ratio values to sustain the high voltage and the high current, which increases cost and reduces performance and reliability.

Therefore, a power supply system having a power supply assisting sub-system that can suppress the surge current due to the overshoot of voltage or current is desired.

SUMMARY

In order to solve or at least alleviate the problems as discussed above, the present disclosure provides technical solutions for suppressing the surge current due to the overshoot of voltage or current as follows.

According to a first aspect of the present disclosure, a power supply system is provided. The power supply system includes: a power source connected between a first node and a second node for applying an input voltage; a first circuit, connected between the first node and a second circuit; and configured to suppress oscillation caused by load variation of a load circuit that is connected between the first node and the second circuit, and to supply power to the load circuit when the power source is temporarily off; the second circuit, having a first port connected to the first circuit, a second port connected to the load circuit, and a third port connected to the second node; and configured to charge the first circuit and supply power to the load circuit; and a third circuit, connected between the first circuit and the load circuit; and configured to suppress a current flowing into the second circuit.

In an exemplary embodiment, the power supply system further includes: a fourth circuit, connected between the first node and the load circuit, and configured to filter interference to the load circuit.

In an exemplary embodiment, the first circuit includes a first capacitor, having a first electrode connected to the first node and a second electrode connected to the first port of the second circuit.

In an exemplary embodiment, the filtering circuit includes a second capacitor, having a first electrode connected to the first node and a second electrode connected to the second port of the second circuit.

In an exemplary embodiment, the second circuit includes: a first transistor, having a control terminal, a first terminal connected to the second node via a first resistor, and a second terminal, as the first port, connected to the second electrode of the first capacitor; a second transistor, having a control terminal, a first terminal connected to the second node via a second resistor, and a second terminal, as the second port, connected to the load circuit; the first resistor connected between the second node and the first terminal of the first transistor; and the second resistor connected between the second node and the first terminal of the second transistor, wherein the first resistor has a resistance larger than that of the second resistor.

In an exemplary embodiment, the third circuit includes: a third transistor, having a control terminal, a first terminal connected to the second terminal of the second transistor, and a second terminal connected to the second electrode of the first capacitor.

In an exemplary embodiment, the control terminals of the first transistor, the second transistor, and the third transistor respectively correspond to gate electrodes of the first transistor, the second transistor, and the third transistor; the first terminal of each of the first transistor, the second transistor, and the third transistor corresponds to one of a source electrode and a drain electrode of the corresponding one of the first transistor, the second transistor, and the third transistor; and the second terminal of each of the charging circuit, the second transistor, and the third transistor corresponds to the other of the source electrode and the drain electrode of the corresponding one of the first transistor, the second transistor, and the third transistor.

In an exemplary embodiment, the first transistor, the second transistor, and the third transistor are N-type transistors, each configured to be turned on by a high level control signal at the control terminal, and turned off by a low level control signal at the corresponding control terminal.

In an exemplary embodiment, the first transistor, the second transistor, and the third transistor are P-type transistors, each configured to be turned on by a low level control signal at the control terminal, and turned off by a high level control signal at the corresponding control terminal.

In an exemplary embodiment, the first transistor is configured to be turned on by a control signal at the control terminal of the first transistor to charge the first capacitor, when the input voltage is normal; and the second transistor is configured to be turned on by a control signal at the control terminal of the second transistor to supply power to the load circuit, if a voltage difference between the input voltage and a voltage across the first capacitor is smaller than a preset voltage threshold.

In an exemplary embodiment, the third transistor is configured to be turned off by a control signal at the control terminal of the third transistor to suppress a current flowing through the second transistor, if the current flowing through the second transistor is not smaller than a preset Over-Current (OC) threshold.

In an exemplary embodiment, the third transistor is kept off for a first predetermined period since the current flowing through the second transistor is smaller than the preset OC threshold; and is turned on by the control signal at the control terminal of the third transistor when the first predetermined period is expired.

In an exemplary embodiment, the first predetermined period includes a hiccup period of Over-Current Protection (OCP).

In an exemplary embodiment, if a voltage across the second capacitor is not smaller than a first preset Over-Voltage (OV) threshold, the first transistor and the second transistor are configured to be turned off respectively by respective control signals at the control terminals of the first transistor and the second transistor, and a signal for sensing the voltage difference is disabled.

In an exemplary embodiment, if the voltage across the second capacitor is not larger than a second preset OV threshold, the first transistor and the second transistor are configured to be turned on respectively by the respective control signals at the control terminals of the first transistor and the second transistor, wherein the second preset OV threshold is smaller than the first OV threshold.

In an exemplary embodiment, if a voltage across the second capacitor is not smaller than a first preset OV threshold, the first transistor, the second transistor and the third transistor are configured to be turned off respectively by respective control signals at the control terminals of the first transistor, the second transistor and the third transistor, and a signal for sensing the voltage difference is disabled.

In an exemplary embodiment, if the voltage across the second capacitor is not larger than a second preset OV threshold, the first transistor, the second transistor, and the third transistor are configured to be turned on respectively by the respective control signals at the control terminals of the first transistor, the second transistor and the third transistor, wherein the second preset OV threshold is smaller than the first OV threshold.

In an exemplary embodiment, the signal is enabled when a second predetermined period since the second transistor is controlled to be turned on is expired.

In an exemplary embodiment, the second predetermined period is a period for the first capacitor being fully charged by the current flowing through the second transistor.

According to a second aspect of the present disclosure, a method of operating the power supply system according to the first aspect is provided. The method includes: turning on the first transistor by a control signal at the control terminal of the first transistor to charge the first capacitor, when the input voltage is normal; and turning on the second transistor by a control signal at the control terminal of the second transistor to supply power to the load circuit, if a voltage difference between the input voltage and a voltage across the first capacitor is smaller than a preset voltage threshold.

In an exemplary embodiment, the method further includes: turning off the third transistor by a control signal at the control terminal of the third transistor to suppress a current flowing through the second transistor, if the current flowing through the second transistor is not smaller than a preset OC threshold.

In an exemplary embodiment, the method further includes: keeping the third transistor off for a first predetermined period since the current flowing through the second transistor is smaller than the preset OC threshold; and turning on the third transistor by the control signal at the control terminal of the third transistor when the first predetermined period is expired.

In an exemplary embodiment, the first predetermined period includes a hiccup period of OCP.

In an exemplary embodiment, the method further includes: if a voltage across the second capacitor is not smaller than a first preset OV threshold, turning off the first transistor and the second transistor respectively by respective control signals at the control terminals of the first transistor and the second transistor, and disabling a signal for sensing the voltage difference.

In an exemplary embodiment, the method further includes: if the voltage across the second capacitor is not larger than a second preset OV threshold, turning on the first transistor and the second transistor respectively by the respective control signals at the control terminals of the first transistor and the second transistor, wherein the second preset OV threshold is smaller than the first OV threshold.

In an exemplary embodiment, the method further includes: if a voltage across the second capacitor is not smaller than a first preset OV threshold, turning off the first transistor, the second transistor and the third transistor respectively by respective control signals at the control terminals of the first transistor, the second transistor and the third transistor, and disabling a signal for sensing the voltage difference.

In an exemplary embodiment, the method further includes: if the voltage across the second capacitor is not larger than a second preset OV threshold, turning on the first transistor, the second transistor and the third transistor respectively by the respective control signals at the control terminals of the first transistor, the second transistor and the third transistor, wherein the second preset OV threshold is smaller than the first OV threshold.

In an exemplary embodiment, the method further includes: enabling the signal when a second predetermined period since the second transistor is controlled to be turned on is expired.

In an exemplary embodiment, the second predetermined period is a period for the first capacitor being fully charged by the current flowing through the second transistor.

The technical solutions of the present disclosure may achieve at least the following beneficial technical effects:the surge current during both powering on and normal operation period can be suppressed;smaller SOA FETs can be used to reduce cost; andOver-Voltage Protection (OVP) and OCP functions can be added more reliably.

It should be noted that throughout the drawings, same or similar reference numbers are used for indicating same or similar elements; various parts in the drawings are not drawn to scale, but only for an illustrative purpose, and thus should not be understood as any limitations and constraints on the scope of the present disclosure.

DETAILED DESCRIPTION

Hereinafter, the present disclosure is described with reference to embodiments shown in the attached drawings. However, it is to be understood that those descriptions are just provided for illustrative purpose, rather than limiting the present disclosure. Further, in the following, descriptions of known structures and techniques are omitted so as not to unnecessarily obscure the concept of the present disclosure.

Those skilled in the art will appreciate that the term “exemplary” is used herein to mean “illustrative,” or “serving as an example,” and is not intended to imply that a particular embodiment is preferred over another or that a particular feature is essential. Likewise, the terms “first” and “second,” and similar terms, are used simply to distinguish one particular instance of an item or feature from another, and do not indicate a particular order or arrangement, unless the context clearly indicates otherwise. Further, the term “step,” as used herein, is meant to be synonymous with “operation” or “action.” Any description herein of a sequence of steps does not imply that these operations must be carried out in a particular order, or even that these operations are carried out in any order at all, unless the context or the details of the described operation clearly indicates otherwise.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be liming of example embodiments. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises”, “comprising”, “has”, “having”, “includes” and/or “including”, when used herein, specify the presence of stated features, elements, and/or components etc., but do not preclude the presence or addition of one or more other features, elements, components and/ or combinations thereof. It will be also understood that the terms “connect(s),” “connecting”, “connected”, etc. when used herein, just means that there is an electrical or communicative connection between two elements and they can be connected either directly or indirectly, unless explicitly stated to the contrary.

The term “based on” is to be read as “based at least in part on.” The term “one embodiment” and “an embodiment” are to be read as “at least one embodiment.” The term “another embodiment” is to be read as “at least one other embodiment.” Other definitions, explicit and implicit, may be included below. In addition, language such as the phrase “at least one of X, Y and Z,” unless specifically stated otherwise, is to be understood with the context as used in general to convey that an item, term, etc. may be either X, Y, or Z, or a combination thereof.

Although multiple embodiments of the present disclosure will be described in the following detailed description in conjunction with the accompanying drawings, it should be understood that the present disclosure is not limited to the described embodiments, but instead is also capable of numerous rearrangements, modifications, and substitutions without departing from the present disclosure that as will be set forth and defined within the claims.

Further, it should be noted that although the following description of some embodiments of the present disclosure is given in the context of power supply system of a communication device, the present disclosure is not limited thereto.

The basic principle of the present disclosure consists in that a current suppression circuit is introduced in the power supply assisting sub-system of the power supply system for supplying power to the communication device, so that the surge current can be suppressed by enabling/disabling the current suppression circuit, without impacting the normal working of the communication device.

Hereinafter, a structure of a power supply system according to an embodiment of the present disclosure will be described in detail with reference toFIG.3.

FIG.3schematically shows the structure of the power supply system30according to the embodiment of the present disclosure.

As shown inFIG.3, the power supply system30includes a power source300, a power supply assisting sub-system301, and a control logic302.

In particular, the power source300is connected between Node 1 (Vin+) and Node 2 (Vin-) for applying an input voltage Vin. For example, Node 2 may be 0V or grounded.

The power supply assisting sub-system301is connected between Node 1 (Vin+) and Node 2 (Vin-), and is configured to assist to supply power to a load circuit31of a communication device (not shown) under control of the control logic302.

The control logic302is schematically shown to illustrate a control principle of controlling the power supply assisting sub-system301, which may be implemented in any of appropriate ways.

In an exemplary embodiment, the power supply assisting sub-system301may include:a first circuit3011, connected between Node 1 (Vin+) and a second circuit3012, wherein the first circuit3011is configured to suppress oscillation caused by load variation of a load circuit31that is connected between the Node 1 (Vin+) and the second circuit3012, and to supply power to the load circuit31when the power source300is temporarily off;the second circuit3012, having a first port connected to the first circuit3011, a second port connected to the load circuit31, and a third port connected to Node 2 (Vin-), wherein the second circuit3012is configured to charge the first circuit3011and supply power to the load circuit31; anda third circuit3013, connected between the first circuit3011(i.e., the first port of the second circuit3012) and the load circuit31(i.e., the second port of the second circuit3012), wherein the third circuit3013is configured to suppress a current flowing into the second circuit3012.

Alternatively, the power supply assisting sub-system301may further include: a fourth circuit3014connected between Node 1 (Vin+) and the load circuit31, wherein the fourth circuit3014is configured to filter interference to the load circuit31.

In an exemplary embodiment, the first circuit3011may include a capacitor Choldup, which has a first electrode connected to Node 1 (Vin+) and a second electrode connected to the second circuit3012.

In an exemplary embodiment, the second circuit3012may include: a first transistor Q1, a second transistor Q2, a first resistor Rs1, and a second resistor Rs2.

In particular, the first transistor Q1has a control terminal, a first terminal connected to Node 2 (Vin-) via the first resistor Rs1, and a second terminal (corresponding to the first port of the second circuit3012) connected to the second electrode of the capacitor Choldup; the second transistor Q2has a control terminal, a first terminal connected to Node 2 (Vin-) via the second resistor Rs2, and a second terminal (corresponding to the second port of the second circuit3012) connected to the load circuit31; the first resistor (Rs1) is connected between Node 2 (Vin-) and the first terminal of the first transistor Q1; and the second resistor Rs2is connected between Node 2 (Vin-) and the first terminal of the second transistor Q2. Here, the first resistor Rs1has a resistance much larger than that of the second resistor Rs2.

In an exemplary embodiment, the third circuit3013may include a third transistor Q3, which has a control terminal, a first terminal connected to the second terminal of the second transistor Q2, and a second terminal connected to the second electrode of the capacitor Choldup.

It may be understood that the control terminals of the first transistor Q1, the second transistor Q2, and the third transistor Q3respectively correspond to gate electrodes of the first transistor Q1, the second transistor Q2, and the third transistor Q3; the first terminal of each of the first transistor Q1, the second transistor Q2, and the third transistor Q3corresponds to one of a source electrode and a drain electrode of the corresponding one of the first transistor Q1, the second transistor Q2, and the third transistor Q3; and the second terminal of each of the charging circuit Q1, the second transistor Q2, and the third transistor Q3corresponds to the other of the source electrode and the drain electrode of the corresponding one of the first transistor Q1, the second transistor Q2, and the third transistor Q3.

The control logic302is schematically shown to illustrate a control principle of controlling the power supply assisting sub-system301, which may be implemented in any of appropriate ways. In the control logic302, Vgs1, Vgs2, and Vgs3are control signals for controlling ON/OFF of the transistors Q1, Q2, and Q3respectively. Herein, N-type transistors are taken as an example for illustration only. Thus, the N-type transistors Q1, Q2, and Q3are respectively turned on by Vgs1, Vgs2, and Vgs3in a high level, and turned off by Vgs1, Vgs2, and Vgs3in a low level. For P-type transistors, although not described herein, it will be understood that the difference between description on P-type transistors and N-type transistors only consists in that the P-type transistors Q1, Q2, and Q3are respectively turned on by Vgs1, Vgs2, and Vgs3in a low level, and turned off by Vgs1, Vgs2, and Vgs3in a high level.

In addition, VRS1(=I1*RS1), VRS2(=I2*RS2), and Vds_sin the control logic302represent feedback signals from the power supply assisting sub-system301, wherein VRS1(=I1*RS1) is associated with the current I1flowing through the transistor Q1, VRS2(=I2*RS2) is associated with the current I2flowing through the transistor Q2; and Vds_srepresents a signal for sensing a voltage difference, denoted as Vds, between the input voltage Vinand the voltage, denoted as Vholdup, across the capacitor Choldup, i.e., Vds= Vin-Vholdup. Thus, Vds_srepresents a signal for characterizing Vds. When Vdsis smaller than a preset reference threshold (Vds_th), the transistor Q2is triggered by Vds_sto be turned on by Vgs2. The magnitude of Vgs1depends on that of VRS1. When VRS1is larger, VRS1may pull the magnitude of Vgs1down. Once Vgs1is decreased, the flow capability of the transistor Q1is reduced, which in turn causes the current I1to be reduced. A smaller Vgs1(e.g. in a middle level) may enable the transistor Q1to operate in the linear mode, wherein the current I1is proportional to VRs1. In the linear mode, the transistor Q1charges the capacitor Choldup.

In an exemplary embodiment, the fourth circuit3014may include a capacitor Co, which has a first electrode connected to the first node (Vin+) and a second electrode connected to the second port of the second circuit3012, i.e., the second terminal of the second transistor Q2.

Although in the above exemplary embodiments, the first circuit3011, the second circuit3012, the third circuit3013, and the fourth circuit3014are embodied to respectively include particular element(s), the present disclosure does not limited to these. It should be understood that any circuit structures with any possible combinations of elements that may achieve the functions of the first circuit3011, the second circuit3012, the third circuit3013, and the fourth circuit3014fall into the scope of the present disclosure, either.

The description below will be made by taking the above particular implementations of the first circuit3011, the second circuit3012, the third circuit3013, and the fourth circuit3014as an example, which is for illustration only without any limitations, as understood by the skilled in the art.

In an exemplary embodiment, when the power supply system30starts to supply power to the communication device (not shown), and the input voltage Vinis normal, the first transistor Q1is configured to be turned on by the control signal (Vgs1) in e.g. a middle level (which causes the transistor Q1to operate in the linear mode) at the control terminal of the first transistor Q1to charge the capacitor Choldup, like the process during t1~t2as shown inFIG.2.

If the voltage difference Vdsbetween the input voltage Vinand a voltage, denoted as Vholdup, across the capacitor Choldupis smaller than the preset voltage threshold Vds_th, the second transistor Q2is configured to be turned on by the control signal (Vgs2) in a high level at the control terminal of the second transistor Q2to supply power to the load circuit31. Like the process during t2~t4as shown inFIG.2, when the transistor Q2is turned on at t2, the current flows through the transistor Q2(as seen fromFIG.2, I2that is shown in a black line has a peak during t2~t3) but almost does not flow through the transistor Q1any more (as seen fromFIG.2, I1that is shown in a gray line is decreased to nearly zero during t2~t3), since the resistor Rs1that is in series with the transistor Q1has a resistance much larger than that of the resistor Rs2. The capacitor Choldupis quickly charged to Vinby the current I2, which is small since Vds(= Vin- Vholdup) is small at t2. Meanwhile, VRS1(=I1*RS1) is reduced and may not pull Vgs1down any more. Consequently, Vgs1boosts up to its original high level at t3, and thus the transistor Q1enters a switching mode at t3. At t3, the power supply of the power supply system30is normal with the assistance of the power supply assisting sub-system301, and thus a signal indicating power good is sent out. Accordingly, after a shorter delay at t4, the load circuit31of the communication device works normally under the good power supply of the power supply system30with the assistance of the power supply assisting sub-system301.

Hereinafter, it will be described in conjunction withFIG.4andFIG.5respectively how the power supply assisting sub-system301according to the above embodiments of the present disclosure may alleviate or even eliminate the negative effects of a larger surge current caused by overshoot of the input voltage Vinor the input current lin, or the power supply assisting sub-system301working in a hiccup mode (i.e., repetitive ON and OFF due to the abnormal load), on the power supply assisting sub-system301, especially on the second transistor Q2.

FIG.4schematically shows an exemplary operating timing sequence diagram of the power supply assisting sub-system301included in the power supply system30ofFIG.3, in a case that OC occurs first and in turn leads to OV, before which the power supply of the power supply system30is normal, as described previously with reference toFIG.2.

In this case, a technical solution provided by the embodiment of the present disclosure mainly consists in thatthe third transistor Q3is turned off to suppress the current I2flowing through the second transistor Q2, if the current I2flowing through the second transistor Q2is not smaller than a preset OC threshold, i.e., an OCP threshold for surge current; and is kept off for a first predetermined period T1since the current I2flowing through the second transistor Q2is smaller than the preset OC threshold, wherein the first predetermined period T1comprises a hiccup period of OCP; and is turned on when the first predetermined period T1is expired;alternatively, if a voltage across the capacitor Cois not smaller than a first preset OV threshold, the first transistor Q1and the second transistor Q2are turned off respectively, and a signal for sensing the voltage difference (denoted as Vds) between the input voltage Vinand a voltage (denoted as Vholdup) across the capacitor Choldupis disabled; and if the voltage across the capacitor Cois not larger than a second preset OV threshold, the first transistor Q1and the second transistor Q2are turned on respectively, wherein the second preset OV threshold is smaller than the first OV threshold;wherein the signal sensing the voltage difference Vdsis enabled when a second predetermined period T2since the second transistor is controlled to be turned on is expired, wherein the second predetermined period T2is a period for the capacitor Choldupbeing fully charged by the current I2flowing through the second transistor Q2.

With reference toFIG.4, the exemplary operating timing sequence of the power supply assisting sub-system301according to the embodiment of the present disclosure is described below in detail.

t00: Overshoot of Vinor linoccurs, or the power supply assisting sub-system301works in the hiccup mode.

t00~t01: The current I2flowing through the second transistor Q2is rapidly increased until a preset OC threshold OCthat t01. Meanwhile, the voltage, denoted as Vo, across the capacitor Coand the voltage Vholdupacross the capacitor Choldupare increased together, wherein Vo=Vholdup.

t01: When the current I2is not smaller than the preset OC threshold OCth, i.e., OC occurs, the third transistor Q3is configured to be turned off by the control signal Vgs3in e.g. a low level at the control terminal of the third transistor Q3.

t01~t02: The current I2flowing through the second transistor Q2is suppressed, since only the capacitor Cois charged by the current I2flowing through the second transistor Q2, and the capacitor Choldupis linear charged by the current I1flowing through the first transistor Q1 in the linear mode which is controlled by the control signal Vgs1in e.g. a middle level. As the capacitor Cois charged by the current I2, the voltage Voacross the capacitor Cois continuously increased until a first preset OV threshold, denoted as OVth1, (i.e., a first OVP threshold) at t02. As the capacitor Choldupis linear charged by the current I1which is smaller than l2, the voltage Vholdupacross the capacitor Choldupis continuously increased, but is slower than Vo.

t02: When the voltage Voacross the capacitor Cois not smaller than the first preset OV threshold OVth1, i.e., OV due to OC occurs, the first transistor Q1and the second transistor Q2are configured to be turned off respectively by respective control signals Vgs1and Vgs2e.g. in a low level at the control terminals of the first transistor Q1and the second transistor Q2. At the same time, the signal Vds_sfor sensing the voltage difference Vdsis disabled, so that the second transistor Q2can be turned on rapidly without being subject to the control of Vds<Vds_th.

t02~t03: The voltage Voacross the capacitor Cowhich is larger than the voltage Vholdupacross the capacitor Choldupis decreased until a second preset OV threshold, denoted OVth2, (i.e., a second OVP threshold) at t03, since the capacitor Cosupplies power (discharges) to the load circuit31.

t03: When the voltage Voacross the capacitor Cois not larger than the second preset OV threshold OVth2, the first transistor Q1and the second transistor Q2are configured to be turned on respectively by the respective control signals Vgs1and Vgs2e.g. in a high level at the control terminals of the first transistor Q1and the second transistor Q2, wherein the second preset OV threshold OVth2is smaller than the first OV threshold OVth1.

t03~t04: Since Vinhas resumed to be normal, and the voltage Voacross the capacitor Cois still larger than the voltage Vholdupacross the capacitor Choldup, which is also larger than Vin, the capacitor Cocontinuously supplies power (discharges) to the load circuit31, until Vois reduced to be equal to Vholdupat t04.

t05: the third transistor Q3is turned on by the control signal Vgs3in e.g. a high level at the control terminal of the third transistor Q3, when a first predetermined period T1since the current I2flowing through the second transistor Q2is smaller than the preset OC threshold OCth(i.e., the third transistor Q3 is turned off) is expired. Here, T1= t05- t01. Preferably, T1may be predetermined to include a hiccup period of OCP.

t06: Vo= Vholdup=Vin. Thus, the load circuit31is resumed to be power supplied by the current I2flowing through the second transistor Q2, and I3becomes 0.

Here, the signal Vds_sis enabled when a second predetermined period T2since the second transistor Q2is controlled to be turned on (i.e., the second transistor Q2 is turned on at t03) is expired. Preferably, T2is a period for the capacitor Choldupbeing fully charged by the current I2flowing through the second transistor Q2.

FIG.5schematically shows an exemplary operating timing sequence diagram of the power supply assisting sub-system301included in the power supply system30ofFIG.3, in a case that OV occurs which necessarily leads to OC, before which the power supply of the power supply system30is normal, as described previously with reference toFIG.2.

In this case, a technical solution provided by the embodiment of the present disclosure mainly consists in thatif a voltage Voacross the capacitor Cois not smaller than a first preset OV threshold, the first transistor Q1, the second transistor Q2and the third transistor Q3are turned off respectively, and a signal for sensing the voltage difference (denoted as Vds) between the input voltage Vinand a voltage (denoted as Vholdup) across the capacitor Choldupis disabled; and if the voltage Voacross the capacitor Cois not larger than a second preset OV threshold, the first transistor Q1, the second transistor Q2and the third transistor Q3are turned on respectively, wherein the second preset OV threshold is smaller than the first OV threshold;wherein the signal sensing the voltage difference Vdsis enabled when a second predetermined period T2since the second transistor is controlled to be turned on is expired, wherein the second predetermined period T2is a period for the capacitor Choldupbeing fully charged by the current I2flowing through the second transistor Q2.

With reference toFIG.5, the exemplary operating timing sequence of the power supply assisting sub-system301according to the embodiment of the present disclosure is described below in detail.

t000: Overshoot of Vinor Iinoccurs, or the power supply assisting sub-system301works in the hiccup mode.

t000~t001: The voltage Voacross the capacitor Coand the voltage Vholdupacross the capacitor Choldupare increased until a first preset OV threshold OVth1at t001, wherein Vo=Vholdup. Meanwhile, the current I2flowing through the second transistor Q2is increased rapidly.

t001: When the voltage Voacross the capacitor Cois not smaller than the first preset OV threshold OVth1, i.e., OV occurs, the first transistor Q1, the second transistor Q2, and the third transistor Q3are configured to be turned off respectively by respective control signals Vgs1, Vgs2and Vgs3e.g. in a low level at the control terminals of the first transistor Q1, the second transistor Q2, and the third transistor Q3. At the same time, the signal Vds_sfor sensing the voltage difference Vdsis disabled, so that the second transistor Q2can be turned on rapidly without being subject to the control of Vds<Vds_th.

t001~t002: Since Vholdup= Vo> Vin, both Choldupand Cosupply power (discharge) to the load circuit31, wherein Choldupprovides a current (I3) through the body diode of the third transistor Q3during Q3is off (Here, I3is negative since Vholdup= Vo> Vin). Thus, Vo= Vholdupis continuously decreased until a second preset OV threshold OVth2at t002.

t002. When the voltage Voacross the capacitor Cois not larger than the second preset OV threshold OVth2, the first transistor Q1, the second transistor Q2and the third transistor Q3are configured to be turned on respectively by the respective control signals Vgs1, Vgs2and Vgs3e.g. in a high level at the control terminals of the first transistor Q1, the second transistor Q2and the third transistor Q3, wherein the second preset OV threshold OVth2is smaller than the first OV threshold OVth1.

t003: Vo= Vholdup=Vin. Thus, the load circuit31is resumed to be power supplied by the current I2flowing through the second transistor Q2, and I3becomes 0.

Here, the signal Vds_sis enabled when a second predetermined period T2since the second transistor Q2is controlled to be turned on (i.e., the second transistor Q2 is turned on at t002) is expired. Preferably, T2is a period for the capacitor Choldupbeing fully charged by the current I2flowing through the second transistor Q2.

In connection withFIGS.4and5, the power supply assisting sub-system301included in the power supply system30ofFIG.3may well suppress the surge current especially flowing through the second transistor Q2.

Hereinafter, a method of operating the power supply system30according to an embodiment of the present disclosure will be described in detail in conjunction withFIG.6, which schematically shows an exemplary flowchart of a method of operating the power supply system30according to an embodiment of the present disclosure.

The structure of the power supply system30has been described in detail and the exemplary operating timing sequence diagrams of the power supply assisting sub-system301included in the power supply system30have been described in conjunction withFIG.3~5, and detailed description thereof may be referred to, which thus will not be described here for simplicity.

As shown inFIG.6, in step S601, the power supply system30starts to supply power to the communication device, and the input voltage Vinis normal.

In step S603, the first transistor Q1is configured to be turned on by the control signal Vgs1in e.g. a middle level (which causes the transistor Q1to operate in the linear mode) at the control terminal of the first transistor Q1to charge the capacitor Choldup, like the process during t1~t2as shown inFIG.2.

In step S605, the voltage difference Vdsbetween the input voltage Vinand a voltage, denoted as Vholdup, across the capacitor Choldupis smaller than the preset voltage threshold Vds_th, the second transistor Q2is configured to be turned on by the control signal (Vgs2) in a high level at the control terminal of the second transistor Q2to supply power to the load circuit31, like the process during t2~t3as shown inFIG.2.

In step S607, the power supply of the power supply system30is normal with the assistance of the power supply assisting sub-system301, and thus a signal indicating power good is sent out, like t3as shown inFIG.2. Accordingly, after a shorter delay at t4as shown inFIG.2, the load circuit31of the communication device works normally under the good power supply of the power supply system30with the assistance of the power supply assisting sub-system301.

In connection withFIG.5, once OV occurs due to overshoot of Vinor linoccurs or the power supply assisting sub-system301working in the hiccup mode, the voltage Voacross the capacitor Coand the voltage Vholdupacross the capacitor Choldupare increased.

It is thus determined in step S609whether the voltage Voacross the capacitor Cois not smaller than the first preset OV threshold OVth1, i.e., OV occurs.

If so (‘Y’ from S609), the method proceeds to step S611, in which the first transistor Q1, the second transistor Q2, and the third transistor Q3are configured to be turned off at t001respectively by respective control signals Vgs1, Vgs2and Vgs3e.g. in a low level at the control terminals of the first transistor Q1, the second transistor Q2, and the third transistor Q3; and the signal Vds_sfor sensing the voltage difference Vdsis disabled, so that the second transistor Q2can be turned on rapidly without being subject to the control of Vds<Vds_th.

It is determined in step S613whether the voltage Voacross the capacitor Cois not larger than the second preset OV threshold OVth2.

If so (‘Y’ from S613), the method proceeds to step S615, in which the first transistor Q1, the second transistor Q2and the third transistor Q3are configured to be turned on at t002respectively by the respective control signals Vgs1, Vgs2and Vgs3e.g. in a high level at the control terminals of the first transistor Q1, the second transistor Q2and the third transistor Q3, wherein the second preset OV threshold OVth2is smaller than the first OV threshold OVth1.

Then, the method goes back to step S607, in which the load circuit31is resumed to work normally under the good power supply of the power supply system30with the assistance of the power supply assisting sub-system301.

Preferably, when the second transistor Q2is controlled to be turned on (i.e., the second transistor Q2 is turned on at t002), a timer for a predetermined period T2is started. Preferably, T2is a period for the capacitor Choldupbeing fully charged by the current I2flowing through the second transistor Q2.

Then, it is determined in step S633whether the timer for T2is expired.

If so (‘Y’ from S633), the signal Vds_sis enabled so that On/OFF of the second transistor Q2is triggered by the voltage difference Vds(= Vin,-Vholdup). As previously described, if Vds< Vds_th, the second transistor Q2is controlled to be turned on, and vice versa.

In connection withFIG.4, once OC occurs due to overshoot of Vinor Iinoccurs or the power supply assisting sub-system301working in the hiccup mode, the current I2flowing through the second transistor Q2is rapidly increased; meanwhile, the voltage Voacross the capacitor Coand the voltage Vholdupacross the capacitor Choldupare increased together, wherein Vo=Vholdup.

It is thus determined in step S617whether the current I2is not smaller than the preset OC threshold OCth, i.e., OC occurs.

If so (‘Y’ from S617), the method proceeds to step S619, in which the third transistor Q3is configured to be turned off at t01by the control signal Vgs3in e.g. a low level at the control terminal of the third transistor Q3.

The current I2flowing through the second transistor Q2is thus suppressed, since only the capacitor Cois charged by the current I2flowing through the second transistor Q2, and the capacitor Choldupis linear charged by the current I1flowing through the first transistor Q1 in the linear mode which is controlled by the control signal Vgs1in e.g. a middle level.

Preferably, if the current I2is smaller than the preset OC threshold OCth(‘N’ from S617), a timer for a predetermined period T1is started. Preferably, T1may be predetermined to include a hiccup period of OCP.

Then, it is determined in step S621whether the timer for T1is expired.

If so (‘Y’ from S621), the third transistor Q3is controlled to be turned on in step S623.

In some case, after the third transistor Q3is controlled to be turned on, the method goes back to step S607, in which the load circuit31is resumed to work normally under the good power supply of the power supply system30with the assistance of the power supply assisting sub-system301.

On the other hand, as previously described, the current I2flowing through the second transistor Q2is thus suppressed, since only the capacitor Cois charged by the current I2flowing through the second transistor Q2, and the capacitor Choldupis linear charged by the current I1flowing through the first transistor Q1 in the linear mode which is controlled by the control signal Vgs1in e.g. a middle level. As the capacitor Cois charged by the current I2, the voltage Voacross the capacitor Cois continuously increased until a first preset OV threshold, denoted as OVth1, (i.e., a first OVP threshold) at t02. That is, the OC leads to OV. Here, as the capacitor Choldupis linear charged by the current I1which is smaller than I2, the voltage Vholdupacross the capacitor Choldupis continuously increased, but is slower than Vo.

It is thus further determined in step S625whether the voltage Voacross the capacitor Cois not smaller than the first preset OV threshold OVth1, i.e., OV due to OC occurs.

If so (‘Y’ from S625), the method proceeds to step S627, in which the first transistor Q1and the second transistor Q2are configured to be turned off at t02respectively by respective control signals Vgs1and Vgs2e.g. in a low level at the control terminals of the first transistor Q1and the second transistor Q2. At the same time, the signal Vds_sfor sensing the voltage difference Vdsis disabled, so that the second transistor Q2can be turned on rapidly without being subject to the control of Vds<Vds_th.

Then, the voltage Voacross the capacitor Cowhich is larger than the voltage Vholdupacross the capacitor Choldupis decreased, since the capacitor Cosupplies power (discharges) to the load circuit31.

It is thus determined in step S629whether the voltage Voacross the capacitor Cois not larger than the second preset OV threshold OVth2.

If so (‘Y’ from S629), the method proceeds to step S631, in which the first transistor Q1and the second transistor Q2are configured to be turned on at t03respectively by the respective control signals Vgs1and Vgs2e.g. in a high level at the control terminals of the first transistor Q1and the second transistor Q2, wherein the second preset OV threshold OVth2is smaller than the first OV threshold OVth1.

Then, the method goes back to step S607, in which the load circuit31is resumed to work normally under the good power supply of the power supply system30with the assistance of the power supply assisting sub-system301.

Preferably, when the second transistor Q2is controlled to be turned on (i.e., the second transistor Q2is turned on at t03), a timer for a predetermined period T2is started. Preferably, T2is a period for the capacitor Choldupbeing fully charged by the current I2flowing through the second transistor Q2.

Then, it is determined in step S633whether the timer for T2is expired.

If so (‘Y’ from S633), the signal Vds_sis enabled so that On/OFF of the second transistor Q2is triggered by the voltage difference Vds(= Vin-Vholdup). As previously described, if Vds< Vds_th, the second transistor Q2is controlled to be turned on, and vice versa.

The above technical solutions of the embodiments according to the present disclosure may achieve at least the following beneficial technical effects:the surge current during both powering on and normal operation period can be suppressed;smaller SOA FETs can be used to reduce cost; andOVP and OCP functions can be added more reliably.

The present disclosure has been described with reference to embodiments and drawings. It should be understood that various modifications, alternations and additions can be made by those skilled in the art without departing from the spirits and scope of the disclosure. Therefore, the scope of the present disclosure is not limited to the above particular embodiments but only defined by the claims as attached and equivalents thereof.