Method of fabricating semiconductor device having trench isolation structure

The present invention provides a method of fabricating a semiconductor device having a trench isolation structure. The method includes the following steps. A hard mask layer is formed on the semiconductor substrate having a cell array region and a peripheral circuit region. The hard mask layer is patterned to expose the semiconductor substrate. Thus, a hard mask pattern is formed to define a first isolation region at the cell array region and simultaneously to define a second isolation region at the peripheral circuit region. A sacrificial material layer is conformally formed at the entire surface of the second isolation region and the hard mask pattern of the peripheral circuit region and fills a gap region between the hard mask patterns of the cell array region. The sacrificial material layer and the semiconductor substrate are sequentially etched to form a first trench region and a second trench region at the cell array region and the peripheral circuit region, respectively. The first trench region is shallower than the second trench region.

RELATED APPLICATION

This application relies for priority upon Korean Patent Application No. 2001-34735, filed on Jun. 19, 2001, the contents of which are herein incorporated by reference in their entirety.

FIELD OF THE INVENTION

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device having a trench isolation structure.

BACKGROUND OF THE INVENTION

As semiconductor devices become highly integrated, widths of isolation layers become decreased for electrically isolating devices. Especially, in case of a trench isolation technique which has solved several problems of a LOCOS isolation technique, as semiconductor devices become highly integrated, an aspect ratio of a trench which is formed at a semiconductor substrate is increased, thereby creating a problem whereby it is difficult to fill the trench.

FIGS. 1 through 4 are cross-sectional views for explaining a conventional method of fabricating a trench isolation structure.

Referring to FIG. 1 , a hard mask pattern 102 a is formed to define a first isolation region 104 at a cell array region a and a second isolation region 105 at a peripheral region b . In order to form the hard mask pattern 102 a, a buffer oxide layer 101 and a hard mask layer are formed on the semiconductor substrate and sequentially patterned.

Referring to FIG. 2 , the semiconductor substrate 100 is etched using the hard mask pattern 102 a as an etch mask, to form trench regions T 1 at the cell array region a and the peripheral circuit region b . Thus, the trench regions T 1 for forming a conventional trench isolation layer have the same depth regardless of the cell array region a of a high pattern density and the peripheral circuit regions b of a low pattern density.

Referring to FIG. 3 , an insulation layer 107 is formed over the entire surface of the resultant structure where the trench region T 1 is formed, to fill the trench region. As seen in FIG. 2 , in the conventional method of fabricating the trench isolation, trench regions T 1 of the same depth are formed regardless of the pattern density. Thus, as semiconductor devices become more highly integrated, when the insulation layer 107 is formed to fill the trench region T 1 , a void B can be generated at the cell array region a of the high pattern density. By using a material layer having a superior burial characteristic, for example, a O 3 -TEOS oxide layer or a high density plasma (HDP) CVD layer, as an insulation layer for filling the trench region T 1 , it is possible to increase the burial characteristic of the insulation layer. But, in the conventional method, despite using the material layer having a superior burial characteristic, if the aspect ratio of the trench region is high, there remains a high probability that the void B occurs.

Referring to FIG. 4 , the insulation layer 107 is etched by using a chemical mechanical polishing (CMP) process to expose the top of the hard mask pattern 102 a. And, the hard mask pattern 102 a and the buffer oxide layer 101 are removed to form isolation layers 107 a and 107 b filling the trench region T 1 , and at the same time, to expose active regions between the isolation layers 107 a and 107 b. At this time, at the step of forming the insulation layer 107 , the void B of the cell array region a is exposed, so that a groove B is formed at the top of the isolation layer 107 a of the cell array region of the high pattern density and this produces an undesirable effect on the characteristic of a semiconductor device.

As described above, the conventional method of fabricating trench isolation simultaneously forms trench regions at a cell array region of a high pattern density and at a peripheral circuit region of a low pattern density. Thus, for a device isolation of a peripheral circuit where high voltage is applied, a trench region should be formed deeply, and thus, a void can be generated at a cell array region of high pattern density. Thus, it is required to form a shallow trench at the cell array region of the high pattern density and a relatively deep trench region at the peripheral circuit region.

The Korean laid-open patent number 1999-0042687 provides a method of fabricating trench regions having each different depth at a cell array region and a peripheral circuit region. But, the method includes twice as many photolithography processes for forming the trench regions at the cell array region and the peripheral circuit region. Thus, the process is complicated and has a problem of degrading a characteristic of the interface between an isolation layer and a semiconductor substrate, since a first formed trench region, out of trench regions formed at a cell array region and at a peripheral circuit region, is covered by a photoresist.

SUMMARY OF THE INVENTION

Thus, it is an object of the present invention to provide a method of fabricating a semiconductor device which has trench isolation structures of different thicknesses at a cell array region of a high pattern density, and at a peripheral circuit region of a low pattern density without addition of a photolithography process.

In order to approach the object, the present invention provides a method including the following steps. A hard mask layer is formed on a semiconductor substrate having a cell array region and a peripheral circuit region. The hard mask layer is patterned to expose the semiconductor substrate. Thus, a hard mask pattern is formed to define a first isolation region at the cell array region and a second isolation region at the peripheral circuit region. A sacrificial material layer is formed at the entire surface of the resultant structure where the hard mask pattern is formed. The sacrificial material layer is conformally formed over the entire surface of the second isolation region and the hard mask pattern of the peripheral circuit region, and fills a gap region between the hard mask patterns of the cell array region. The sacrificial material layer and the semiconductor substrate are sequentially etched to form a first and a second trench regions at the cell array region and the peripheral circuit region, respectively. The first trench region is shallower than the second trench region.

Further, after forming an insulation layer filling the first and second trench regions, the insulation layer is etched by using a CMP process to expose the hard mask layer and simultaneously to form an isolation layer at the first and second trench regions. Then, the hard mask layer is removed to expose the semiconductor substrate between the isolation layers.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention will now be described more fully hereinafter with respect to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the attached figures, the thickness of layers and regions is exaggerated for clarity. Also, when it is mentioned that a layer is on another layer or a substrate, the layer can be directly formed on another layer or on a substrate, or a third layer can be interposed therebetween. The same reference numbers indicate the same components throughout the specification.

In figures, a reference mark a indicates a cell array region, and other reference mark b indicates a peripheral circuit region.

Referring to FIG. 5 , a buffer oxide layer 101 and a hard mask layer 102 are sequentially formed on a semiconductor substrate 100 , and a photoresist pattern 103 is formed to define an isolation region on the hard mask layer 102 .

The buffer oxide layer 101 functions to prevent generation of crystalline structure defects at the surface of the semiconductor substrate 100 by alleviating a stress applied at the semiconductor substrate 100 by the hard mask layer 102 . The buffer oxide layer 101 is preferably formed in a thickness of approximately 50 to 200 on the semiconductor substrate.

The hard mask layer 102 is preferably formed of a material layer having an etch selectivity with respect to a sacrificial material layer and an insulation layer formed in a subsequent process, for example, a silicon nitride layer. In this case, the hard mask layer 102 would be preferably thickly formed, considering that the silicon nitride layer is etched in a subsequent step of etching the sacrificial material layer. But in case of thickly forming the hard mask layer 102 with only the silicon nitride layer, a stress applied at the semiconductor substrate 100 would be increased, so that defects of the semiconductor substrate would be further increased. Thus, instead of thickly forming the silicon nitride layer, an oxide layer can be further formed at the top of the silicon nitride layer, thereby forming the hard mask layer 102 composed of the sequentially stacked thin silicon nitride layer and oxide layer.

Referring to FIG. 6 , the hard mask layer 102 and the buffer oxide layer 101 are patterned by using the photoresist pattern 103 as an etch mask, to form a hard mask pattern 102 a on the buffer oxide layer 101 on the semiconductor substrate 100 . As a result, a first isolation region 104 and a second isolation region 105 are defined by exposing the semiconductor substrate at the cell array region a and the peripheral circuit region b , respectively. Then, the photoresist pattern 103 is removed.

Referring to FIG. 7 , a sacrificial material layer 106 is formed at the entire surface of the semiconductor substrate including where the hard mask pattern 102 a is formed. At this time, the sacrificial material layer 106 perfectly fills a gap region between the hard mask patterns 102 a of the cell array region a , and is conformally formed on the second isolation region 105 and the hard mask pattern 102 a of the peripheral circuit region b . Preferably, the sacrificial material layer 106 is thicker than a half of the width of the first isolation region 104 .

The sacrificial material layer 106 is formed of a material layer having an etch selectivity with respect to the hard mask pattern 102 a, for example, preferably, a silicon layer.

Referring to FIG. 8 , the sacrificial material layer 106 is etched by using a method of etching the entire surface, to expose the hard mask pattern 102 a and simultaneously to expose the second isolation region 105 of the peripheral circuit region b . At the same time, the sacrificial material layer 106 is left at the top of the first isolation region 104 of the cell array region a , to form a sacrificial material layer pattern 106 a.

A sacrificial material layer S remaining at the peripheral circuit region b is removed at a subsequent step of etching the semiconductor substrate 100 for forming a trench region. Also, by the thickness of the sacrificial material layer pattern 106 a, it is possible to define a depth difference of trenches formed at the cell array region and the peripheral circuit region in a subsequent step.

Referring to FIG. 9 , the sacrificial material layer pattern 106 a and the semiconductor substrate 100 of the cell array region a are sequentially etched by using the hard mask pattern 102 a as an etch mask, to form a first trench region T 2 . And at the same time, the semiconductor substrate 100 of the peripheral circuit region is etched to form a second trench region T 3 .

At this time, an etch recipe having the same etch selectivity with respect to the sacrificial material layer pattern 106 a and the semiconductor substrate 100 is used. Thus, during etching the sacrificial material layer pattern 106 a at the cell array region a , since the semiconductor substrate of the peripheral circuit region b is etched, the first trench region T 2 is formed more shallowly than the depth of the second trench region T 3 .

Referring to FIG. 10 , an insulation layer 107 is formed to fill the first and second trench regions T 2 and T 3 at the entire surface of the semiconductor substrate where the first and second trench regions T 2 and T 3 are formed. Thus, because the depth of the first trench region T 2 is shallow in comparison with the conventional technique, it is possible to prevent generation of a void at the cell array region a of the high pattern density in case of forming the insulation layer 107 . Before forming the insulation layer 107 , a thermal oxide layer is preferably formed at the surfaces of the first and second trench regions T 2 and T 3 , thereby curing surface defects of the semiconductor substrate 100 during an etching process for forming the trench regions. Also, a thin silicon nitride layer is further formed at the entire surface of the semiconductor substrate where the thermal oxide layer is formed. This prevents the undesirable effect of impurities penetrating at the interface between the isolation layer and the semiconductor substrate in a subsequent process. The insulation layer 107 is preferably formed of a material layer having a superior burial characteristic, for example, a O 3 -TEOS oxide layer or a HDP CVD oxide layer.

Referring to FIG. 11 , the insulation layer 107 is etched by using the CMP process to expose the hard mask pattern 102 a, and to form an isolation layer 107 c in the first and second trench regions T 2 and T 3 . Then, the hard mask pattern 102 a is removed to expose the semiconductor substrate 100 .

At the step of polishing the insulation layer 107 , the partial top surface of the hard mask pattern 102 a is together polished, so that the height of the top surface of the isolation layer 107 c can be somewhat low. But, in case that the top surface of the isolation layer 107 c is higher than the surface of the semiconductor substrate 100 , a conductive layer can be left along the side surface of the isolation layer 107 c protruded over the surface of the semiconductor substrate 100 in a subsequent step of patterning a word line. Thus, in order to prevent this, it is desirable that the top surface of the isolation layer 107 c is recessed to make the height of the isolation layer 107 c similar with that of the surface of the semiconductor substrate 100 , before removing the hard mask pattern 102 a.

In an alternative form of the preferred embodiment of the present invention, there is a method of etching the sacrificial material layer 106 and the semiconductor substrate 100 by using an etch recipe having an identical etch selectivity, after forming the sacrificial material layer 106 .

Referring to FIGS. 7 through 9 , until the step of forming the sacrificial material layer 106 , the method is identical with the preferred embodiment of the present invention as describe above. Then, the sacrificial material layer 106 and the semiconductor substrate 100 are sequentially etched using the etch recipe having the identical etch selectivity with respect to the sacrificial material layer 106 and the semiconductor substrate 100 . At this time, the hard mask pattern 102 a is used as an etch stopping layer during etching the sacrificial material layer 107 and the semiconductor substrate 100 .

Consequently, the sacrificial material layer 106 on the first isolation region 104 is formed more thickly than that on the second isolation region 105 , so that the first trench region T 2 of the cell array region a is formed more shallowly than the second trench region of the peripheral circuit region T 3 . Subsequent processes are identical with the described embodiment.

As described above, the present invention enables to prevent that a void is created when an isolation layer of a region of a high pattern density is formed, and simultaneously to form a semiconductor device having a superior isolation characteristic at a peripheral circuit region including a high voltage-applied region.

A person skilled in the art will be able to practice the present invention in view of the description present in this document, which is to be taken as a whole. In some instances, well-known features have not been described in detail in order not to obscure unnecessarily the invention. While the invention has been disclosed in its preferred form, it should be readily apparent to those skilled in the art in view of the present description that the invention can be modified in numerous ways. The inventor regards the subject matter of the invention to include all combinations and sub-combinations of the various elements, features, functions and/or properties disclosed herein.