Systems and methods for output current regulation in power conversion systems

Systems and methods are provided for regulating power conversion systems. A system controller includes: a first controller terminal configured to receive a first signal related to an input signal for a primary winding of a power conversation system; and a second controller terminal configured to output a drive signal to a switch to affect a current flowing through the primary winding, the drive signal being associated with a switching period including an on-time period and an off-time period. The switch is closed (e.g., being turned on) in response to the drive signal during the on-time period. The switch is opened (e.g., being turned off) in response to the drive signal during the off-time period. A duty cycle is equal to a duration of the on-time period divided by a duration of the switching period. The system controller is configured to keep a multiplication product of the duty cycle and the duration of the on-time period approximately constant.

1. CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No. 201510249026.4, filed May 15, 2015, commonly assigned, incorporated by reference herein for all purposes.

2. BACKGROUND OF THE INVENTION

Certain embodiments of the present invention are directed to integrated circuits. More particularly, some embodiments of the invention provide systems and methods for regulating output currents. Merely by way of example, some embodiments of the invention have been applied to power conversion systems. But it would be recognized that the invention has a much broader range of applicability.

Light emitting diodes (LEDs) are widely used for lighting applications. Oftentimes, approximately constant currents are used to control working currents of LEDs to achieve constant brightness.FIG. 1is a simplified diagram showing a conventional LED lighting system. The LED lighting system100includes a system controller102, resistors104,124,126and132, capacitors106,120and134, a diode108, a transformer110including a primary winding112, a secondary winding114and an auxiliary winding116, a power switch128, a current sensing resistor130, and a rectifying diode118. The system controller102includes terminals (e.g., pins)138,140,142,144,146and148. For example, the power switch128is a bipolar junction transistor. In another example, the power switch128is a MOS transistor. In yet another example, the power switch128is an insulated-gate bipolar transistor.

An alternate-current (AC) input voltage152is applied to the system100. A bulk voltage150(e.g., a rectified voltage no smaller than 0 V) associated with the AC input voltage152is received by the resistor104. The capacitor106is charged in response to the bulk voltage150, and a voltage154is provided to the system controller102at the terminal138(e.g., terminal VCC). If the voltage154is larger than a predetermined threshold voltage in magnitude, the system controller102begins to operate normally and generates a drive signal199through the terminal142(e.g., terminal GATE). The switch128receives a signal156associated with the drive signal199. For example, the drive signal199is a pulse-width-modulation (PWM) signal with a switching frequency and a duty cycle. The switch128is closed (e.g., being turned on) or open (e.g., being turned off) in response to the drive signal199so that the output current158is regulated to be approximately constant.

The auxiliary winding116charges the capacitor106through the diode108when the switch128is opened (e.g., being turned off) in response to the drive signal199so that the system controller102can operate normally. For example, a feedback signal160is provided to the system controller102through the terminal140(e.g., terminal FB) in order to detect the end of a demagnetization process of the secondary winding114(e.g., for charging or discharging the capacitor134using an internal error amplifier in the system controller102). In another example, the feedback signal160is provided to the system controller102through the terminal140(e.g., terminal FB) in order to detect the beginning and the end of the demagnetization process of the secondary winding114. The resistor130is used for detecting a primary current162flowing through the primary winding112, and a current-sensing signal164is provided to the system controller102through the terminal144(e.g., terminal CS) to be processed during each switching cycle. Peak magnitudes of the current-sensing signal164are sampled and provided to the internal error amplifier. The capacitor120is used to maintain an output voltage168so as to keep a stable output current through an output load (e.g., one or more LEDs122). For example, the system100implements a primary-side-regulation scheme with single-stage power factor correction (PFC). As an example, the system100implements a flyback architecture or a buck-boost architecture.

FIG. 2is a simplified conventional diagram showing the system controller102as part of the system100. The system controller102includes a ramp-signal generator202, an under-voltage lock-out (UVLO) component204, a modulation component206, a logic controller208, a driving component210, a demagnetization detector212, an error amplifier216, and a current-sensing component214.

As shown inFIG. 2, the UVLO component204detects the signal154and outputs a signal218. If the signal154is larger than a first predetermined threshold in magnitude, the system controller102begins to operate normally. If the signal154is smaller than a second predetermined threshold in magnitude, the system controller102is turned off. The second predetermined threshold is smaller than or equal to the first predetermined threshold in magnitude. The error amplifier216receives a signal220from the current-sensing component214and a reference signal222and outputs an amplified signal224to the modulation component206. The modulation component206also receives a signal228from the ramp-signal generator202and outputs a modulation signal226. For example, the signal228is a ramping signal and increases, linearly or non-linearly, to a peak magnitude during each switching period. The logic controller208processes the modulation signal226and outputs a control signal230to the driving component210which generates the signal199to turn on or off the switch128. For example, the demagnetization detector212detects the feedback signal160and outputs a signal232for determining the end of the demagnetization process of the secondary winding114. In another example, the demagnetization detector212detects the feedback signal160and outputs the signal232for determining the beginning and the end of the demagnetization process of the secondary winding114. In addition, the demagnetization detector212outputs a trigger signal298to the logic controller208to start a next cycle. The system controller102is configured to keep an on-time period associated with the modulation signal226approximately constant for a given output load.

The system controller102is operated in a voltage-mode where, for example, the signal224from the error amplifier216and the signal228from the oscillator202are both voltage signals and are compared by the comparator206to generate the modulation signal226to drive the power switch128. Therefore, an on-time period associated with the power switch128is determined by the signal224and the signal228.

FIG. 3is a simplified conventional diagram showing the current-sensing component214and the error amplifier216as parts of the system controller102. The current-sensing component214includes a switch302and a capacitor304. The error amplifier216includes switches306and308, an operational transconductance amplifier (OTA)310.

As shown inFIG. 3, the current-sensing component214samples the current-sensing signal164and the error amplifier216amplifies the difference between the signal220and the reference signal222. Specifically, the switch302is closed (e.g., being turned on) or open (e.g., being turned off) in response to a signal314in order to sample peak magnitudes of the current-sensing signal164in different switching periods. If the switch302is closed (e.g., being turned on) in response to the signal314and the switch306is open (e.g., being turned off) in response to the signal232from the demagnetization detector212, the capacitor304is charged and the signal220increases in magnitude. If the switch306is closed (e.g., being turned on) in response to the signal232, the switch308is open (e.g., being turned off) in response to a signal312and the difference between the signal220and the reference signal222is amplified by the amplifier310. The signal312and the signal232are complementary to each other. For example, during the demagnetization process of the secondary winding114, the signal232is at a logic high level and the signal312is at a logic low level. The switch306remains closed (e.g., being turned on) and the switch308remains open (e.g., being turned off). The OTA310, together with the capacitor134, performs integration associated with the signal220. In another example, after the completion of the demagnetization process of the secondary winding114, the signal232is at the logic low level and the signal312is at the logic high level.

Under stable normal operations, an average output current is determined, according to the following equation (e.g., without taking into account any error current):

Io_=12×N×Vref_eaRcs(Equation⁢⁢1)
where N represents a turns ratio between the primary winding112and the secondary winding114, Vref_earepresents the reference signal222and Rcsrepresents the resistance of the resistor130. As shown in Equation 1, the parameters associated with peripheral components, such as N and Rcs, can be properly selected through system design to achieve output current regulation.

For LED lighting, efficiency, power factor and total harmonic are also important. For example, efficiency is often needed to be as high as possible (e.g., >90%), and a power factor is often needed to be greater than 0.9. Moreover, total harmonic distortion is often needed to be as low as possible (e.g., <10%) for some applications. But the system100often cannot satisfy all these needs.

Hence it is highly desirable to improve the techniques of regulating output currents of power conversion systems.

3. BRIEF SUMMARY OF THE INVENTION

Certain embodiments of the present invention are directed to integrated circuits. More particularly, some embodiments of the invention provide systems and methods for regulating output currents. Merely by way of example, some embodiments of the invention have been applied to power conversion systems. But it would be recognized that the invention has a much broader range of applicability.

According to one embodiment, a system controller for regulating a power conversion system includes: a first controller terminal configured to receive a first signal related to an input signal for a primary winding of a power conversation system; and a second controller terminal configured to output a drive signal to a switch to affect a current flowing through the primary winding of the power conversion system, the drive signal being associated with a switching period including an on-time period and an off-time period. The switch is closed in response to the drive signal during the on-time period. The switch is opened in response to the drive signal during the off-time period. A duty cycle is equal to a duration of the on-time period divided by a duration of the switching period. The system controller is configured to keep a multiplication product of the duty cycle and the duration of the on-time period approximately constant.

According to another embodiment, a system controller for regulating a power conversion system includes: a ramp-current generator configured to receive a modulation signal and generate a ramp current based at least in part on the modulation signal; a ramp-signal generator configured to receive the ramp current and generate a ramping signal based at least in part on the ramp current; a modulation component configured to receive the ramping signal and generate the modulation signal based at least in part on the ramping signal; a driving component configured to receive the modulation signal and output a drive signal to a switch to affect a current flowing through a primary winding of a power conversion system, the drive signal being associated with a switching period including an on-time period and an off-time period. The switch is closed in response to the drive signal during the on-time period. The switch is opened in response to the drive signal during the off-time period. A duty cycle is equal to a duration of the on-time period divided by a duration of the switching period. The ramp-current generator is further configured to generate the ramp current approximately proportional to the duty cycle in magnitude.

According to yet another embodiment, a system controller for regulating a power conversion system includes: a first controller terminal configured to provide a compensation signal based on at least information associated with a current flowing through a primary winding of a power conversion system; a ramp-current generator configured to receive a modulation signal, the compensation signal and a first reference signal and generate a ramp current based at least in part on the modulation signal, the compensation signal and the first reference signal; a ramp-signal generator configured to receive the ramp current and generate a ramping signal based at least in part on the ramp current; a modulation component configured to receive the ramping signal and the compensation signal and generate the modulation signal based at least in part on the ramping signal and the compensation signal; and a driving component configured to receive the modulation signal and output a drive signal to a switch to affect the current, the drive signal being associated with a switching period including an on-time period and an off-time period. The switch is closed in response to the drive signal during the on-time period. The switch is opened in response to the drive signal during the off-time period. A duty cycle is equal to a duration of the on-time period divided by a duration of the switching period. The ramp-current generator is further configured to generate the ramp current approximately proportional in magnitude to a multiplication product of the duty cycle and a difference, the different representing the first reference signal minus the compensation signal in magnitude.

In one embodiment, a method for regulating a power conversion system includes: generating a drive signal associated with a switching period including an on-time period and an off-time period; and outputting the drive signal to a switch to affect a current flowing through a primary winding of a power conversion system. The outputting the drive signal to the switch to affect the current includes: outputting the drive signal to close the switch during the on-time period; and outputting the drive signal to open the switch during the off-time period. A duty cycle is equal to a duration of the on-time period divided by a duration of the switching period. The generating the drive signal associated with the switching period includes keeping a multiplication product of the duty cycle and the duration of the on-time period approximately constant.

In another embodiment, a method for regulating a power conversion system includes: receiving a modulation signal; generating a ramp current based at least in part on the modulation signal; receiving the ramp current; generating a ramping signal based at least in part on the ramp current; receiving the ramping signal; generating the modulation signal based at least in part on the ramping signal; receiving the modulation signal; generating a drive signal based at least in part on the modulation signal, the drive signal being associated with a switching period including an on-time period and an off-time period; and outputting the drive signal to a switch to affect a current flowing through a primary winding of a power conversion system. The outputting the drive signal to the switch to affect the current includes: outputting the drive signal to close the switch during the on-time period; and outputting the drive signal to open the switch during the off-time period. A duty cycle is equal to a duration of the on-time period divided by a duration of the switching period. The generating the ramp current based at least in part on the modulation signal includes generating the ramp current approximately proportional to the duty cycle in magnitude.

In yet another embodiment, a method for regulating a power conversion system includes: providing a compensation signal based on at least information associated with a current flowing through a primary winding of a power conversion system; receiving a modulation signal, the compensation signal and a first reference signal; generating a ramp current based at least in part on the modulation signal, the compensation signal and the first reference signal; receiving the ramp current; generating a ramping signal based at least in part on the ramp current; receiving the ramping signal and the compensation signal; generating the modulation signal based at least in part on the ramping signal and the compensation signal; receiving the modulation signal; and outputting a drive signal to a switch to affect the current, the drive signal being associated with a switching period including an on-time period and an off-time period. The outputting the drive signal to the switch to affect the current includes: outputting the drive signal to close the switch during the on-time period; outputting the drive signal to open the switch during the off-time period. A duty cycle is equal to a duration of the on-time period divided by a duration of the switching period. The generating the ramp current based at least in part on the modulation signal, the compensation signal and the first reference signal includes generating the ramp current approximately proportional in magnitude to a multiplication product of the duty cycle and a difference, the different representing the first reference signal minus the compensation signal in magnitude.

Depending upon embodiment, one or more benefits may be achieved. These benefits and various additional objects, features and advantages of the present invention can be fully appreciated with reference to the detailed description and accompanying drawings that follow.

5. DETAILED DESCRIPTION OF THE INVENTION

Certain embodiments of the present invention are directed to integrated circuits. More particularly, some embodiments of the invention provide systems and methods for regulating output currents. Merely by way of example, some embodiments of the invention have been applied to power conversion systems. But it would be recognized that the invention has a much broader range of applicability.

Referring toFIG. 1, to achieve high efficiency (e.g., >90%), the system100may operate in a quasi-resonant (QR) mode, as an example. A peak value of the primary current162is determined as follows:

Iin_peak=(TonLp)·Vbulk(Equation⁢⁢2)
where Iin_peakrepresents a peak value of the primary current162, Tonrepresents an on-time period during which the power switch128is closed (e.g., being turned on), Vbulkrepresents the bulk voltage150, and Lprepresents the inductance of the primary winding112.

For example, assuming the on-time period associated with the power switch128keeps approximately constant for a given input voltage and a given output load and the inductance of the primary winding112keeps approximately constant, the peak value of the primary current162follows the bulk voltage150(e.g., associated with a rectified sine waveform), according to Equation 2. In another example, an average of the primary current162is an average value of the primary current162during one or more switching periods, or is an average value of the primary current162during one or more switching periods that slide over time. In yet another example, the average of the primary current162is determined as follows:

Iin_ave=12⁢D·Iin_peak=Ton2⁢⁢Ts·Iin_peak=(Ton2Lp)·Vbulk2⁢(Ton+Toff)(Equation⁢⁢3)
where Tsrepresents a switching period including an on-time period (e.g., Ton) during which the power switch128is closed (e.g., being turned on) and an off-time period (e.g., Toff) during which the power switch128is open (e.g., being turned off). In addition, D represents a duty cycle associated with the power switch128and is determined as follows:

If the system100operates in the QR mode, the off-time period (e.g., Toff) is the same as a demagnetization period (e.g., Tdemag, associated with a demagnetization process of the secondary winding114). Assuming the on-time period remains approximately constant in duration, the demagnetization period (e.g., Tdemag) changes with the peak value of the primary current162and thus the bulk voltage150. As such, the switching period (e.g., Ts) changes with the bulk voltage150. If the bulk voltage150increases in magnitude, the peak value of the primary current162increases and the switch period (e.g., Ts) increases in duration. As a result, the average of the primary current162does not follow closely the bulk voltage150and thus does not have a similar waveform as the bulk voltage150(e.g., a rectified sine waveform), which may result in poor total harmonic distortion.

FIG. 4is a simplified diagram showing a power conversion system according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The system400includes a system controller402, resistors404,424,426, and432, capacitors406,420, and434, a diode408, a transformer410including a primary winding412, a secondary winding414and an auxiliary winding416, a power switch428, a current sensing resistor430, and a rectifying diode418. The system controller402includes terminals (e.g., pins)438,440,442,444,446, and448. For example, the power switch428includes a bipolar junction transistor. In another example, the power switch428includes a MOS transistor. In yet another example, the power switch428includes an insulated-gate bipolar transistor (IGBT). The system400provides power to an output load422, e.g., one or more LEDs. In some embodiments, the resistor432is removed. For example, the system400operates in a quasi-resonant (QR) mode.

According to some embodiments, the system controller402is implemented to vary the duration of an on-time period (e.g., Ton) during which the power switch428keeps closed (e.g., being turned on) with a bulk voltage450which is associated with an alternate-current (AC) input voltage452. For example, the bulk voltage450(e.g., a rectified voltage no smaller than 0 V) is received by the resistor404. In another example, the capacitor406is charged in response to the bulk voltage450, and a voltage454is provided to the system controller402at the terminal438(e.g., terminal VCC). In yet another example, if the voltage454is larger than a predetermined threshold voltage in magnitude, the system controller402begins to operate normally, and outputs a signal499through the terminal442(e.g., terminal GATE). In yet another example, the switch428is closed (e.g., being turned on) or open (e.g., being turned off) in response to a drive signal456associated with the signal499so that the output current458is regulated to be approximately constant.

According to one embodiment, the auxiliary winding416charges the capacitor406through the diode408when the switch428is opened (e.g., being turned off) in response to the drive signal456so that the system controller402can operate normally. For example, a feedback signal460is provided to the system controller402through the terminal440(e.g., terminal FB) in order to detect the end of a demagnetization process of the secondary winding414for charging or discharging the capacitor434using an internal error amplifier in the system controller402. In another example, the feedback signal460is provided to the system controller402through the terminal440(e.g., terminal FB) in order to detect the beginning and the end of the demagnetization process of the secondary winding414. As an example, the capacitor434is charged or discharged in response to a compensation signal474at the terminal448(e.g., terminal COMP). In another example, the resistor430is used for detecting a primary current462flowing through the primary winding412, and a current-sensing signal464is provided to the system controller402through the terminal444(e.g., terminal CS) to be processed during each switching cycle (e.g., corresponding to each switching period of the power switch428). In yet another example, peak magnitudes of the current-sensing signal464are sampled and provided to the internal error amplifier. In yet another example, the capacitor434is coupled to an output terminal of the internal error amplifier. In yet another example, the capacitor420is used to maintain an output voltage468so as to keep a stable output current through the output load422(e.g., one or more LEDs). For example, the system400implements a primary-side-regulation scheme with single-stage power factor correction (PFC). As an example, the system400implements a flyback architecture or a buck-boost architecture.

According to another embodiment, an average of the primary current162is an average value of the primary current162during one or more switching periods, or is an average value of the primary current162during one or more switching periods that slide over time. For example, the average of the primary current162is determined as follows:

Iin_ave=12⁢D·Iin_peak=12⁢D·TonLp·Vbulk=(Ton2Lp)·Vbulk2⁢(Ton+Toff)(Equation⁢⁢5)
where Tsrepresents a switching period including an on-time period (e.g., Ton) during which the power switch428is closed (e.g., being turned on) and an off-time period (e.g., Toff) during which the power switch428is open (e.g., being turned off). In another example, a sum of the duration of the on-time period (e.g., Ton) and the off-time period (e.g., Toff) is equal to the duration of the switching period Ts. In addition, D represents a duty cycle associated with the power switch428and is determined as follows:

According to certain embodiments, the system controller402is implemented to keep a multiplication product of the duty cycle and the duration of the on-time period constant to achieve low total harmonic distortion as follows:
D×Ton=constant  (Equation 7)
For example, according to Equation 7, if the multiplication product of the duty cycle and the duration of the on-time period is kept constant, the average of the primary current462changes with the bulk voltage450(e.g., associated with a rectified sine waveform).

In some embodiments, the system controller402is implemented to keep a multiplication product of the duty cycle and the duration of the on-time period approximately constant to achieve low total harmonic distortion as follows:
D×Ton≅constant  (Equation 8)
For example, according to Equation 8, if the multiplication product of the duty cycle and the duration of the on-time period is kept approximately constant, the average of the primary current462changes (e.g., approximately linearly) with the bulk voltage450(e.g., associated with a rectified sine waveform). In another example, as shown in Equation 8, the error range of the multiplication product of the duty cycle and the duration of the on-time period being constant is ±5%. In yet another example, as shown in Equation 8, the error range of the multiplication product of the duty cycle and the duration of the on-time period being constant is ±10%. In yet another example, as shown in Equation 8, the error range of the multiplication product of the duty cycle and the duration of the on-time period being constant is ±15%. In yet another example, as shown in Equation 8, the error range of the multiplication product of the duty cycle and the duration of the on-time period being constant is ±20%.

FIG. 5(a)is a simplified diagram showing the system controller402as part of the power conversion system400according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The system controller402includes a ramp-signal generator602, an under-voltage lock-out (UVLO) component604, a modulation component606, a logic controller608, a driving component610, a demagnetization detector612, an error amplifier616, a current-sensing-and-sample/hold component614, a reference-voltage generator640, and a ramp-current generator642.

According to one embodiment, the UVLO component604detects the signal454and outputs a signal618(e.g., por). For example, if the signal454is larger than a first predetermined threshold in magnitude, the system controller402begins to operate normally. If the signal454is smaller than a second predetermined threshold in magnitude, the system controller402is turned off. In another example, the second predetermined threshold is smaller than or equal to the first predetermined threshold in magnitude. In yet another example, the error amplifier616receives a signal620from the current-sensing-and-sample/hold component614and a reference signal622. In yet another example, the error amplifier616generates a current which charges or discharges the capacitor434to generate the compensation signal474(e.g., Vcomp). In yet another example, the compensation signal474(e.g., Vcomp) is provided to the modulation component606. In yet another example, the capacitor434is coupled to the terminal448and forms, together with the error amplifier616, an integrator or a low-pass filter. In yet another example, the error amplifier616is a transconductance amplifier and outputs a current which is proportional to a difference between the reference signal622and the signal620. In yet another example, the error amplifier616together with the capacitor434generates the compensation signal474(e.g., Vcomp) which is a voltage signal.

As an example, the reference-voltage generator640outputs a reference signal636(e.g., Vref1) to the ramp-current generator642, outputs a voltage signal694(e.g., V1) to the ramp-signal generator602, and outputs a reference signal622(e.g., Vref_ea) to the error amplifier616. In another example, the ramp-signal generator602also receives a current signal638(e.g., Iramp) generated by the ramp-current generator642and generates a ramping signal628. In yet another example, the current-sensing-and-sample/hold component614samples the current sensing signal464in response to the control signal630and then holds the sampled signal until the current-sensing-and-sample/hold component614samples again the current sensing signal464.

According to another embodiment, the current638(e.g., Iramp) flows from the ramp-current generator642to the ramp-signal generator602. For example, the current638(e.g., Iramp) flows from the ramp-signal generator602to the ramp-current generator642. In another example, the modulation component606receives the ramping signal628and outputs a modulation signal626. In yet another example, the logic controller608processes the modulation signal626and outputs a control signal630to the current-sensing-and-sample/hold component614and the driving component610. In yet another example, the modulation signal626corresponds to a pulse-width-modulation (PWM) signal. In yet another example, the driving component610generates the signal499related to the drive signal456to affect the switch428. In yet another example, when the signal499is at the logic high level, the signal456is at the logic high level, and when the signal499is at the logic low level, the signal456is at the logic low level.

According to yet another embodiment, the demagnetization detector612detects the feedback signal460and outputs a demagnetization signal632for determining the end of the demagnetization process of the secondary winding414. For example, the demagnetization detector612detects the feedback signal460and outputs the demagnetization signal632for determining the beginning and the end of the demagnetization process of the secondary winding414. In another example, the demagnetization detector612outputs a trigger signal698to the logic controller608to start a next cycle (e.g., corresponding to a next switching period).

In one embodiment, the on-time period (e.g., Ton) is determined as follows:

Ton=Vcomp-V⁢⁢1slp(Equation⁢⁢9)
where Vcomprepresents the compensation signal474(e.g., the output of the error amplifier616), V1represents the signal694, and slp represents a slope of the ramping signal628. For example, the ramping signal628increases, linearly or non-linearly, to a peak magnitude during each switching period, and the signal694(e.g., V1) corresponds to a start point of the increase of the ramping signal628. As an example, the slope of the ramping signal628is determined as follows:

slp=IrampC(Equation⁢⁢10)
where Iramprepresents the current638, and C represents the capacitance of an internal capacitor in the ramp-signal generator602. Combining Equations 8-10, it is determined:

To keep the multiplication product of the duty cycle (e.g., D) and the duration of the on-time period (e.g., Ton) constant, the ramp-current generator642generates the current638(e.g., Iramp) to be proportional in magnitude to the duty cycle (e.g., D), according to some embodiments. For example, the current638(e.g., Iramp) is determined as follows:
Iramp=k1*D(Equation 12)
where k1represents a coefficient parameter (e.g., a constant).

In some embodiments, the ramp-current generator642generates the current638to be approximately proportional in magnitude to the duty cycle (e.g., D) so that the multiplication product of the duty cycle (e.g., D) and the duration of the on-time period (e.g., Ton) is kept approximately constant. For example, the current638(e.g., Iramp) is determined as follows:
Iramp≅k1*D(Equation 13)
where k1represents a coefficient parameter (e.g., a constant). In another example, as shown in Equation 13, the error range of the current638being proportional in magnitude to the duty cycle is ±5%. In yet another example, as shown in Equation 13, the error range of the current638being proportional in magnitude to the duty cycle is ±10%. In yet another example, as shown in Equation 13, the error range of the current638being proportional in magnitude to the duty cycle is ±15%. In yet another example, as shown in Equation 13, the error range of the current638being proportional in magnitude to the duty cycle is ±20%.

As discussed above and further emphasized here,FIG. 5(a)is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, instead of receiving the modulation signal626, the ramp-current generator642receives the signal499associated with the drive signal456. In another example, instead of receiving the modulation signal626, the ramp-current generator642receives the demagnetization signal632. In yet another example, instead of receiving the modulation signal626, the ramp-current generator642receives a signal complementary to the demagnetization signal632.

FIG. 5(b)is a simplified timing diagram for the system controller402as part of the power conversion system400according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform902represents the modulation signal626as a function of time, the waveform904represents the signal499as a function of time, the wave form906represents the demagnetization signal632as a function of time, the waveform908represents the trigger signal698as a function of time, and the waveform910represents the ramping signal628as a function of time.

An on-time period and an off-time period associated with the signal499are shown inFIG. 5(b). The on-time period begins at a time t3and ends at a time t5, and the off-time period begins at the time t5and ends at a time t8. For example, t0≤t1≤t2≤t3≤t4≤t5≤t6≤t7≤t8.

According to one embodiment, at t0, the demagnetization signal632changes from the logic high level to the logic low level. For example, the demagnetization detector612generates a pulse (e.g., between t0and t2) in the trigger signal698to trigger a new cycle. As an example, the ramping signal628begins to increase from a magnitude912to a magnitude914(e.g., at t4). In another example, at t1, the signal626changes from the logic low level to the logic high level. After a short delay, the signal499changes (e.g., at t3) from the logic low level to the logic high level, and in response the switch428is closed (e.g., being turned on). In yet another example, at t4, the signal626changes from the logic high level to the logic low level, and the ramping signal628decreases from the magnitude914to the magnitude912. After a short delay, the signal499changes (e.g., at t5) from the logic high level to the logic low level, and in response, the switch428is open (e.g., being turned off). As an example, at t6, the demagnetization signal632changes from the logic low level to the logic high level which indicates a beginning of a demagnetization process. In another example, at t7, the demagnetization signal632changes from the logic high level to the logic low level which indicates the end of the demagnetization process. In yet another example, the demagnetization detector612generates another pulse in the trigger signal698to start a next cycle. In yet another example, the magnitude912of the ramping signal628is associated with the signal694. In yet another example, the magnitude914of the ramping signal628is associated with the magnitude of the compensation signal474.

According to another embodiment, the magnitude change of the ramping signal628during the on-time period is determined as follows:
ΔVramp=Vcomp−V1=slp×Ton(Equation 14)
where ΔVramprepresents the magnitude changes of the ramping signal628, Vcomprepresents the signal474, V1represents the signal694, slp represents a ramping slope associated with the ramping signal628, and Tonrepresents the duration of the on-time period. For example, V1corresponds to the magnitude912of the ramping signal628. Based on Equation 14, the duration of the on-time period is determined as follows:

As shown in Equation 15, for a given compensation signal (e.g., the signal474), the duration of the on-time period is determined by the ramping slope of the ramping signal628, according to certain embodiments. For example, a slope of the waveform910between t1and t4corresponds to the ramping slope of the ramping signal628.

FIG. 5(c)is a simplified diagram showing the ramp-current generator642as part of the system controller402according to one embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The ramp-current generator642includes an operational amplifier506, a low pass filter508, a voltage-to-current converter510, a NOT gate518, and switches502and504.

According to one embodiment, the switch502is closed or opened in response to the modulation signal626(e.g., PWM), and the switch504is closed or opened in response to a signal512(e.g., PWM_b). For example, the NOT gate518generates the signal512(e.g., PWM_b) which is complementary to the modulation signal626(e.g., PWM). As an example, if the modulation signal626is at the logic high level, the signal512is at the logic low level, and if the modulation signal626is at the logic low level, the signal512is at the logic high level.

In one embodiment, if the modulation signal626(e.g., PWM) is at the logic high level, the switch502is closed (e.g., being turned on) and the operational amplifier506receives the reference signal636(e.g., Vref1) at its non-inverting terminal (e.g., terminal “+”), where the inverting terminal (e.g., terminal “−”) and the output terminal of the amplifier506are connected. For example, the operational amplifier506includes a buffer amplifier with a gain of 1. As an example, the signal512is at the logic low level, and the switch504is open (e.g., being turned off). For example, the low pass filter508receives a signal516from the amplifier506and outputs a filtered signal514(e.g., Vduty). In another example, the filtered signal514(e.g., Vduty) is a voltage signal and is converted by the voltage-to-current converter510to the current638(e.g., Iramp). In yet another example, the signal516is approximately equal (e.g., in magnitude) to the reference signal636.

In another embodiment, if the modulation signal626(e.g., PWM) is at the logic low level and the signal512is at the logic high level, the switch502is open (e.g., being turned off), and the switch504is closed (e.g., being turned on). For example, the operational amplifier506receives a ground voltage520at its non-inverting terminal (e.g., terminal “+”), and changes the signal516. As an example, the signal516is approximately equal to the ground voltage520. As another example, the low pass filter508includes a RC filter which includes one or more resistors and one or more capacitors.
Iramp=k1*D=β(Vref1)*D(Equation 16)
where Vref1represents the reference signal636, and β represents a coefficient parameter (e.g., a constant).

FIG. 5(d)is a simplified diagram showing the ramp-current generator642and the ramp-signal generator602as parts of the system controller402according to some embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The ramp-signal generator602includes an operational amplifier546, switches540and542, and a capacitor544. For example, the switches502,504,540and532each include one or more MOS transistors.

According to one embodiment, the switch540is closed or opened in response to the modulation signal626(e.g., PWM), and the switch542is closed or opened in response to the signal512(e.g., PWM_b). In one embodiment, if the modulation signal626(e.g., PWM) is at the logic low level and the signal512is at the logic high level, the switch540is open (e.g., being turned off) and the switch504is closed (e.g., being turned on). For example, the operational amplifier546receives the signal694(e.g., V1) at its non-inverting terminal (e.g., terminal “+”) and outputs a signal548, where the inverting terminal (e.g., terminal “−”) and the output terminal of the amplifier546are connected together. As an example, the signal548is approximately equal (e.g., in magnitude) to the signal694(e.g., V1), and in response the voltage on the capacitor544becomes approximately equal (e.g., in magnitude) to the signal548and thus the signal694(e.g., V1).

In another embodiment, if the modulation signal626(e.g., PWM) changes to the logic high level and the signal512changes to the logic low level, the switch540is closed (e.g., being turned on) and the switch504is opened (e.g., being turned off). For example, the ramp-current generator642outputs the current638to charge the capacitor544through the closed switch540. As an example, the ramping signal628which corresponds to the voltage on the capacitor544increases (e.g., linearly or non-linearly) from a magnitude approximately equal to the signal694(e.g., V1) to a maximum magnitude (e.g., the compensation signal474) as the current638charges the capacitor544.

As discussed above and further emphasized here,FIGS. 5(a), 5(b), 5(c), and5(d) are merely examples, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the ramp-current generator642generates the current638(e.g., Iramp) based at least in part on a multiplication product of the duty cycle and a difference between the reference signal636and the compensation signal474(e.g., Vcomp), so that the compensation signal474(e.g., Vcomp) does not vary much at different input voltages to reduce the ripple effects of the compensation signal474, e.g., as shown inFIG. 6(a).

FIG. 6(a)is a simplified diagram showing the system controller402as part of the power conversion system400according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The system controller402includes a ramp-signal generator1602, an under-voltage lock-out (UVLO) component1604, a modulation component1606, a logic controller1608, a driving component1610, a demagnetization detector1612, an error amplifier1616, a current-sensing-and-sample/hold component1614, a reference-voltage generator1640, and a ramp-current generator1642.

For example, the ramp-signal generator1602, the under-voltage lock-out (UVLO) component1604, the modulation component1606, the logic controller1608, the driving component1610, the demagnetization detector1612, the error amplifier1616, the current-sensing-and-sample/hold component1614, the reference-voltage generator1640, and the ramp-current generator1642are the same as the ramp-signal generator602, the under-voltage lock-out (UVLO) component604, the modulation component606, the logic controller608, the driving component610, the demagnetization detector612, the error amplifier616, the current-sensing-and-sample/hold component614, the reference-voltage generator640, and the ramp-current generator642, respectively.

According to one embodiment, the UVLO component1604detects the signal454and outputs a signal1618(e.g., por). For example, if the signal454is larger than a first predetermined threshold in magnitude, the system controller402begins to operate normally. If the signal454is smaller than a second predetermined threshold in magnitude, the system controller402is turned off. In another example, the second predetermined threshold is smaller than or equal to the first predetermined threshold in magnitude. In yet another example, the error amplifier1616receives a signal1620from the current-sensing-and-sample/hold component1614and a reference signal1622, and the compensation signal474(e.g., Vcomp) is provided to the modulation component1606and the voltage-to-current-conversion component1642. In yet another example, the capacitor434is coupled to the terminal448and forms, together with the error amplifier1616, an integrator or a low-pass filter. In yet another example, the error amplifier1616is a transconductance amplifier and outputs a current which is proportional to a difference between the reference signal1622and the signal1620. In yet another example, the error amplifier1616together with the capacitor434generates the compensation signal474(e.g., Vcomp) which is a voltage signal.

As an example, the reference-voltage generator1640outputs a reference signal1636(e.g., Vref) to the ramp-current generator1642, outputs a voltage signal1694(e.g., V1) to the ramp-signal generator1602, and outputs a reference signal1622(e.g., Vref_ea) to the error amplifier1616. In another example, the ramp-signal generator1602also receives a current signal1638(e.g., Iramp) generated by the ramp-current generator1642and generates a ramping signal1628. In one embodiment, the current signal1638is equal in magnitude to the current signal638. In another embodiment, the current signal1638is not equal in magnitude to the current signal638.

According to another embodiment, the current1638(e.g., Iramp) flows from the ramp-current generator1642to the ramp-signal generator1602. For example, the current1638(e.g., Iramp) flows from the ramp-signal generator1602to the ramp-current generator1642. In another example, the modulation component1606receives the ramping signal1628and outputs a modulation signal1626. In yet another example, the logic controller1608processes the modulation signal1626and outputs a control signal1630to the current-sensing-and-sample/hold component1614and the driving component1610. In yet another example, the modulation signal1626corresponds to a pulse-width-modulation (PWM) signal.

According to yet another embodiment, the current-sensing-and-sample/hold component1614samples the current sensing signal464in response to the control signal1630and then holds the sampled signal until the current-sensing-and-sample/hold component1614samples again the current sensing signal464. For example, the driving component1610generates the signal499related to the drive signal456to affect the switch428. In another example, if the signal499is at the logic high level, the signal456is at the logic high level, and if the signal499is at the logic low level, the signal456is at the logic low level. As an example, the demagnetization detector1612detects the feedback signal460and outputs a demagnetization signal1632for determining the end of the demagnetization process of the secondary winding414. As another example, the demagnetization detector1612detects the feedback signal460and outputs the demagnetization signal1632for determining the beginning and the end of the demagnetization process of the secondary winding414. In yet another example, the demagnetization detector1612outputs a trigger signal1698to the logic controller1608to start a next cycle (e.g., corresponding to a next switching period).

To keep the multiplication product of the duty cycle (e.g., D) and the duration of the on-time period (e.g., Ton) constant, the ramp-current generator1642generates the current1638(e.g., Iramp) to be proportional in magnitude to the duty cycle (e.g., D), according to some embodiments. For example, the current1638(e.g., Iramp) is determined as follows:
Iramp=k2*D(Equation 17)
where k2represents a coefficient parameter. As an example, k2is proportional to a difference between the reference signal1636(e.g., Vref) and the compensation signal474(e.g., Vcomp). For example, a differential signal is generated based at least in part on the difference between the reference signal1636(e.g., Vref) and the compensation signal474(e.g., Vcomp). In certain embodiments, the current1638(e.g., Iramp) is determined as follows:
Iramp=α(Vref−Vcomp)×D(Equation 18)
where α represents a coefficient parameter (e.g., a constant). In some applications, the compensation signal474(e.g., Vcomp), e.g., the output of the error amplifier1616, represents an output load condition for a given input voltage (e.g., Vbulk), according to certain embodiments.

In some embodiments, the ramp-current generator1642generates the current1638to be approximately proportional in magnitude to the duty cycle (e.g., D) so that the multiplication product of the duty cycle (e.g., D) and the duration of the on-time period (e.g., Ton) is kept approximately constant. For example, the current1638(e.g., Iramp) is determined as follows:
Iramp≅k2*D(Equation 19)
where k2represents a coefficient parameter. As an example, k2is approximately proportional to a difference between the reference signal1636(e.g., Vref) and the compensation signal474(e.g., Vcomp). For example, a differential signal is generated based at least in part on the difference between the reference signal1636(e.g., Vref) and the compensation signal474(e.g., Vcomp). In certain embodiments, the current1638(e.g., Iramp) is determined as follows:
Iramp≅α(Vref−Vcomp)×D(Equation 20)
where a represents a coefficient parameter (e.g., a constant). For example, as shown in Equation 20, the error range of the current1638being proportional in magnitude to a multiplication product of the duty cycle and the difference between the reference signal1636and the compensation signal474is ±5%. In another example, as shown in Equation 20, the error range of the current1638being proportional in magnitude to a multiplication product of the duty cycle and the difference between the reference signal1636and the compensation signal474is ±10%. In yet another example, as shown in Equation 20, the error range of the current1638being proportional in magnitude to a multiplication product of the duty cycle and the difference between the reference signal1636and the compensation signal474is ±15%. In yet another example, as shown in Equation 20, the error range of the current1638being proportional in magnitude to a multiplication product of the duty cycle and the difference between the reference signal1636and the compensation signal474is ±20%.

As discussed above and further emphasized here,FIG. 6(a)is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, instead of receiving the modulation signal1626, the ramp-current generator1642receives the signal499associated with the drive signal456. In another example, instead of receiving the modulation signal1626, the ramp-current generator1642receives the demagnetization signal1632. In yet another example, instead of receiving the modulation signal1626, the ramp-current generator1642receives a signal complementary to the demagnetization signal1632.

FIG. 6(b)is a simplified timing diagram for the system controller402as part of the power conversion system400according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform1902represents the modulation signal1626as a function of time, the waveform1904represents the signal499as a function of time, the wave form1906represents the demagnetization signal1632as a function of time, the waveform1908represents the trigger signal1698as a function of time, and the waveform1910represents the ramping signal1628as a function of time.

An on-time period and an off-time period associated with the signal499are shown inFIG. 6(b). The on-time period begins at a time t13and ends at a time t15, and the off-time period begins at the time t15and ends at a time t18. For example, t10≤t11≤t12≤t13≤t14≤t15≤t16≤t17≤t18.

According to one embodiment, at t10, the demagnetization signal1632changes from the logic high level to the logic low level. For example, the demagnetization detector1612generates a pulse (e.g., between t10and t12) in the trigger signal1698to trigger a new cycle. As an example, the ramping signal1628begins to increase from a magnitude1912to a magnitude1914(e.g., at t14). In another example, at t11, the signal1626changes from the logic low level to the logic high level. After a short delay, the signal499changes (e.g., at t13) from the logic low level to the logic high level, and in response the switch428is closed (e.g., being turned on). In yet another example, at t14, the signal1626changes from the logic high level to the logic low level, and the ramping signal1628decreases from the magnitude1914to the magnitude1912. After a short delay, the signal499changes (e.g., at t15) from the logic high level to the logic low level, and in response, the switch428is open (e.g., being turned off). As an example, at t16, the demagnetization signal1632changes from the logic low level to the logic high level which indicates a beginning of a demagnetization process. In another example, at t17, the demagnetization signal1632changes from the logic high level to the logic low level which indicates the end of the demagnetization process. In yet another example, the demagnetization detector1612generates another pulse in the trigger signal1698to start a next cycle. In yet another example, the magnitude1912of the ramping signal1628is associated with the signal1694. In yet another example, the magnitude1914of the ramping signal1628is associated with the magnitude of the compensation signal474. In yet another example, a ramping slope of the ramp signal1628is modulated by the compensation signal474(e.g., Vcomp), e.g., the output of the error amplifier1616.

According to another embodiment, the magnitude change of the ramping signal1628during the on-time period is determined as follows:
ΔVramp=Vcomp−V1=slp×Ton(Equation 21)
where ΔVramprepresents the magnitude changes of the ramping signal1628, Vcomprepresents the signal474, V1represents the signal1694, slp represents a ramping slope associated with the ramping signal1628, and Tonrepresents the duration of the on-time period. For example, V1corresponds to the magnitude1912of the ramping signal1628. Based on Equation 15, the duration of the on-time period is determined as follows:

As shown in Equation 22, for a given compensation signal (e.g., the output of the error amplifier1616), the duration of the on-time period is determined by the ramping slope of the ramping signal1628, according to certain embodiments. For example, a slope of the waveform1910between t11and t14corresponds to the ramping slope of the ramping signal1628. In some embodiments, the ramping slope of the ramping signal1628is the same as the ramping slope of the ramping signal628. In certain embodiments, the ramping slope of the ramping signal1628is different from the ramping slope of the ramping signal628.

FIG. 6(c)is a simplified diagram showing the ramp-current generator1642as part of the system controller402according to another embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The ramp-current generator1642includes an operational amplifier1506, a low pass filter1508, a voltage-to-current converter1510, a NOT gate1518, a summation component1522, and switches1502and1504. For example, the operational amplifier1506, the low pass filter1508, the voltage-to-current converter1510, the NOT gate1518, and the switches1502and1504are the same as the operational amplifier506, the low pass filter508, the voltage-to-current converter510, the NOT gate518, and the switches502and504, respectively.

According to one embodiment, the switch1502is closed or opened in response to the modulation signal1626(e.g., PWM), and the switch1504is closed or opened in response to a signal1512(e.g., PWM_b). For example, the NOT gate1518generates the signal1512(e.g., PWM_b) which is complementary to the modulation signal1626(e.g., PWM). As an example, if the modulation signal1626is at the logic high level, the signal1512is at the logic low level, and if the modulation signal1626is at the logic low level, the signal1512is at the logic high level. In another example, the summation component1522receives the reference signal1636(e.g., Vref) and the compensation signal474(e.g., Vcomp) and generates a signal1524, where the signal1524is equal (e.g., in magnitude) to a difference between the reference signal1636(e.g., Vref) and the compensation signal474(e.g., Vcomp).

In one embodiment, if the modulation signal1626(e.g., PWM) is at the logic high level, the switch1502is closed (e.g., being turned on) and the operational amplifier1506receives the signal1524at its non-inverting terminal (e.g., terminal “+”), where the inverting terminal (e.g., terminal “−”) and the output terminal of the amplifier1506are connected together. As an example, the signal1512is at the logic low level, and the switch1504is open (e.g., being turned off). For example, the low pass filter1508receives a signal1516from the amplifier1506and outputs a filtered signal1514(e.g., Vduty). In another example, the filtered signal1514(e.g., Vduty) is a voltage signal and is converted by the voltage-to-current converter1510to the current1638(e.g., Iramp). In yet another example, the signal1516is approximately equal (e.g., in magnitude) to the signal1524.

In another embodiment, if the modulation signal1626(e.g., PWM) is at the logic low level and the signal1512is at the logic high level, the switch1502is open (e.g., being turned off), and the switch1504is closed (e.g., being turned on). For example, the operational amplifier1506receives a ground voltage1520at its non-inverting terminal (e.g., terminal “+”), and changes the signal1516. As an example, the signal1516is approximately equal to the ground voltage1520. As another example, the low pass filter1508includes a RC filter which includes one or more resistors and one or more capacitors.

FIG. 6(d)is a simplified diagram showing the ramp-current generator1642and the ramp-signal generator1602as parts of the system controller402according to certain embodiments of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The ramp-signal generator1602includes an operational amplifier1546, switches1540and1542, and a capacitor1544. For example, the switches1502,1504,1540and1542each include one or more MOS transistors.

According to one embodiment, the switch1540is closed or opened in response to the modulation signal1626(e.g., PWM), and the switch1542is closed or opened in response to the signal1512(e.g., PWM_b). In one embodiment, if the modulation signal1626(e.g., PWM) is at the logic low level and the signal1512is at the logic high level, the switch1540is open (e.g., being turned off) and the switch1504is closed (e.g., being turned on). For example, the operational amplifier1546receives the signal1694(e.g., V1) at its non-inverting terminal (e.g., terminal “+”) and outputs a signal1548, where the inverting terminal (e.g., terminal “−”) and the output terminal of the amplifier1546are connected together. In another example, the operational amplifier1546includes a buffer amplifier with a gain of 1. As an example, the signal1548is approximately equal (e.g., in magnitude) to the signal1694(e.g., V1), and in response the voltage on the capacitor1544becomes approximately equal (e.g., in magnitude) to the signal1548and thus the signal1694(e.g., V1).

In another embodiment, if the modulation signal1626(e.g., PWM) changes to the logic high level and the signal1512changes to the logic low level, the switch1540is closed (e.g., being turned on) and the switch1504is opened (e.g., being turned off). For example, the ramp-current generator1642outputs the current1638to charge the capacitor1544through the closed switch1540. As an example, the ramping signal1628which corresponds to the voltage on the capacitor1544increases (e.g., linearly or non-linearly) from a magnitude approximately equal to the signal1694(e.g., V1) to a maximum magnitude (e.g., the compensation signal474) as the current1638charges the capacitor1544.

According to one embodiment, a system controller for regulating a power conversion system includes: a first controller terminal configured to receive a first signal related to an input signal for a primary winding of a power conversation system; and a second controller terminal configured to output a drive signal to a switch to affect a current flowing through the primary winding of the power conversion system, the drive signal being associated with a switching period including an on-time period and an off-time period. The switch is closed in response to the drive signal during the on-time period. The switch is opened in response to the drive signal during the off-time period. A duty cycle is equal to a duration of the on-time period divided by a duration of the switching period. The system controller is configured to keep a multiplication product of the duty cycle and the duration of the on-time period approximately constant. For example, the system controller is implemented according to at leastFIG. 4,FIG. 5(a),FIG. 5(b),FIG. 5(c), and/orFIG. 5(d).

According to another embodiment, a system controller for regulating a power conversion system includes: a ramp-current generator configured to receive a modulation signal and generate a ramp current based at least in part on the modulation signal; a ramp-signal generator configured to receive the ramp current and generate a ramping signal based at least in part on the ramp current; a modulation component configured to receive the ramping signal and generate the modulation signal based at least in part on the ramping signal; a driving component configured to receive the modulation signal and output a drive signal to a switch to affect a current flowing through a primary winding of a power conversion system, the drive signal being associated with a switching period including an on-time period and an off-time period. The switch is closed in response to the drive signal during the on-time period. The switch is opened in response to the drive signal during the off-time period. A duty cycle is equal to a duration of the on-time period divided by a duration of the switching period. The ramp-current generator is further configured to generate the ramp current approximately proportional to the duty cycle in magnitude. For example, the system controller is implemented according to at leastFIG. 4,FIG. 5(a),FIG. 5(b),FIG. 5(c), and/orFIG. 5(d).

According to yet another embodiment, a system controller for regulating a power conversion system includes: a first controller terminal configured to provide a compensation signal based on at least information associated with a current flowing through a primary winding of a power conversion system; a ramp-current generator configured to receive a modulation signal, the compensation signal and a first reference signal and generate a ramp current based at least in part on the modulation signal, the compensation signal and the first reference signal; a ramp-signal generator configured to receive the ramp current and generate a ramping signal based at least in part on the ramp current; a modulation component configured to receive the ramping signal and the compensation signal and generate the modulation signal based at least in part on the ramping signal and the compensation signal; and a driving component configured to receive the modulation signal and output a drive signal to a switch to affect the current, the drive signal being associated with a switching period including an on-time period and an off-time period. The switch is closed in response to the drive signal during the on-time period. The switch is opened in response to the drive signal during the off-time period. A duty cycle is equal to a duration of the on-time period divided by a duration of the switching period. The ramp-current generator is further configured to generate the ramp current approximately proportional in magnitude to a multiplication product of the duty cycle and a difference, the different representing the first reference signal minus the compensation signal in magnitude. For example, the system controller is implemented according to at leastFIG. 4,FIG. 6(a),FIG. 6(b),FIG. 6(c), and/orFIG. 6(d).

In one embodiment, a method for regulating a power conversion system includes: generating a drive signal associated with a switching period including an on-time period and an off-time period; and outputting the drive signal to a switch to affect a current flowing through a primary winding of a power conversion system. The outputting the drive signal to the switch to affect the current includes: outputting the drive signal to close the switch during the on-time period; and outputting the drive signal to open the switch during the off-time period. A duty cycle is equal to a duration of the on-time period divided by a duration of the switching period. The generating the drive signal associated with the switching period includes keeping a multiplication product of the duty cycle and the duration of the on-time period approximately constant. For example, the method is implemented according to at leastFIG. 4,FIG. 5(a),FIG. 5(b),FIG. 5(c), and/orFIG. 5(d).

In another embodiment, a method for regulating a power conversion system includes: receiving a modulation signal; generating a ramp current based at least in part on the modulation signal; receiving the ramp current; generating a ramping signal based at least in part on the ramp current; receiving the ramping signal; generating the modulation signal based at least in part on the ramping signal; receiving the modulation signal; generating a drive signal based at least in part on the modulation signal, the drive signal being associated with a switching period including an on-time period and an off-time period; and outputting the drive signal to a switch to affect a current flowing through a primary winding of a power conversion system. The outputting the drive signal to the switch to affect the current includes: outputting the drive signal to close the switch during the on-time period; and outputting the drive signal to open the switch during the off-time period. A duty cycle is equal to a duration of the on-time period divided by a duration of the switching period. The generating the ramp current based at least in part on the modulation signal includes generating the ramp current approximately proportional to the duty cycle in magnitude. For example, the method is implemented according to at leastFIG. 4,FIG. 5(a),FIG. 5(b),FIG. 5(c), and/orFIG. 5(d).

In yet another embodiment, a method for regulating a power conversion system includes: providing a compensation signal based on at least information associated with a current flowing through a primary winding of a power conversion system; receiving a modulation signal, the compensation signal and a first reference signal; generating a ramp current based at least in part on the modulation signal, the compensation signal and the first reference signal; receiving the ramp current; generating a ramping signal based at least in part on the ramp current; receiving the ramping signal and the compensation signal; generating the modulation signal based at least in part on the ramping signal and the compensation signal; receiving the modulation signal; and outputting a drive signal to a switch to affect the current, the drive signal being associated with a switching period including an on-time period and an off-time period. The outputting the drive signal to the switch to affect the current includes: outputting the drive signal to close the switch during the on-time period; outputting the drive signal to open the switch during the off-time period. A duty cycle is equal to a duration of the on-time period divided by a duration of the switching period. The generating the ramp current based at least in part on the modulation signal, the compensation signal and the first reference signal includes generating the ramp current approximately proportional in magnitude to a multiplication product of the duty cycle and a difference, the different representing the first reference signal minus the compensation signal in magnitude. For example, the method is implemented according to at leastFIG. 4,FIG. 6(a),FIG. 6(b),FIG. 6(c), and/orFIG. 6(d).

For example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components. In another exampl, individually and/or in combination with at least another component, implemene, some or all components of various embodiments of the present invention each areted in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. In yet another example, various embodiments and/or examples of the present invention can be combined.