Semiconductor device and method for fabricating the same

The present inventive concept has been made in an effort to increase the width of a channel in a silicon carbide MOSFET using a trench gate.According to the exemplary embodiment of the present inventive concept, the width of a channel can be increased, compared with the conventional art, by forming a plurality of protrusions extending to the p type epitaxial layer on both sides of the trench.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims benefit of priority to Korean Patent Application No. 10-2012-0157508 filed in the Korean Intellectual Property Office on Dec. 28, 2012, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present inventive concept relates to a semiconductor device including silicon carbide (SiC) and a method for fabricating the same.

BACKGROUND

With the recent trend toward large-sized and large-capacity application apparatuses, a power semiconductor device having a high breakdown voltage, a high current capacity, and high-speed switching characteristics has become necessary.

Accordingly, many researches and developments are being conducted on MOSFETs (metal oxide semiconductor field effect transistors) using silicon carbide (SiC), instead of conventional MOSFETs using silicon. Particularly, there is a lot of development of vertical trench MOSFETs.

In the vertical trench MOSFET, a channel is formed in a p type epitaxial layer on both sides of a trench. The width of the channel is proportional to the thickness of the p type epitaxial layer.

The channel width can be lengthened to increase the amount of conduction current; however, the p type epitaxial layer has to be made thicker because the channel width is proportional to the thickness of the p type epitaxial layer, resulting in an increase in the area of the semiconductor device.

SUMMARY

The present inventive concept has been made in an effort to increase the width of a channel in a silicon carbide MOSFET using a trench gate.

An aspect of the present inventive concept relates to a semiconductor device including: an n+ type silicon carbide substrate; an n− type epitaxial layer, a p type epitaxial layer, and an n+ region sequentially disposed on a first surface of the n+ silicon carbide substrate; a trench penetrating the n+ region and the p type epitaxial layer, disposed on the n− type epitaxial layer, and including a plurality of protrusions disposed on both sides of the trench; a gate insulating film disposed within the trench; a gate electrode disposed on the gate insulating film; an oxide film disposed on the gate electrode; a source electrode disposed on the p type epitaxial layer, the n+ region, and the oxide film; and a drain electrode positioned on a second surface of the n+ type silicon carbide substrate, wherein the plurality of protrusions extend to the p type epitaxial layer.

The protrusions positioned on one side of the trench may be spaced apart from each other.

The plurality of protrusions may be disposed at contact areas between the sides of the trench and the p type epitaxial layer.

An aspect of the present inventive concept encompasses a method for fabricating a semiconductor device, the method including: sequentially forming an n− type epitaxial layer, a p type epitaxial layer, and an n+ region on a first surface of an n+ type silicon carbide substrate; forming a trench by penetrating the n+ region and the p type epitaxial layer and by etching a part of the n− type epitaxial layer; and forming a plurality of protrusions by etching both sides of the trench, wherein the plurality of protrusions extend to the p type epitaxial layer.

The method for fabricating a semiconductor device according to the exemplary embodiment of the present inventive concept may further include: after the forming of a plurality of protrusions, forming a gate insulating film within the trench; forming a gate electrode on the gate insulating film; forming an oxide film on the gate insulating film and the gate electrode; and forming a source electrode on the p type epitaxial layer, the n+ region, and the oxide film, and forming a drain electrode on a second surface of the n+ type silicon carbide substrate.

According to the exemplary embodiment of the present inventive concept, the width of a channel can be increased, compared with the conventional art, by forming a plurality of protrusions extending to the p type epitaxial layer on both sides of the trench.

With the increase in the width of the channel, the channel resistance can be reduced, and the amount of conduction current can be increased.

Moreover, the area of the semiconductor device can be reduced in order to obtain the same amount of current, thus leading to a reduction in production cost.

DETAILED DESCRIPTION

Exemplary embodiments of the present inventive concept will be described in detail with reference to the attached drawings. The present inventive concept may be modified in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, the exemplary embodiments of the present inventive concept are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present inventive concept to those skilled in the art.

In the drawings, the thickness of layers and regions may be exaggerated for clarity. In addition, when a layer is described to be formed on another layer or on a substrate, this means that the layer may be formed on the other layer or on the substrate, or a third layer may be interposed between the layer and the other layer or the substrate. Like numbers refer to like elements throughout the specification.

FIG. 1is a cross-sectional view of a semiconductor device according to an exemplary embodiment of the present inventive concept.FIG. 2is an enlarged view of portion A ofFIG. 1.

Referring toFIG. 1andFIG. 2, in the semiconductor device according to an exemplary embodiment of the present inventive concept, an n− type epitaxial layer200, a p type epitaxial layer300, and an n+ region400may be sequentially disposed on a first surface of an n+ type silicon carbide substrate100.

A trench450may be disposed on the n− epitaxial layer200, the p type epitaxial layer300, and the n+ region400. The trench450may penetrate the n+ region400and the p type epitaxial layer300. A plurality of protrusions455may be disposed on both sides of the trench450. The protrusions455may extend to the p type epitaxial layer300. That is, the protrusions455may be disposed at contact areas between the sides of the trench450and the p type epitaxial layer300. Also, the protrusions455positioned on one side of the trench450may be spaced apart from each other.

A channel350may be disposed in the p type epitaxial layer300on both sides of the trench450. The channel350may be in contact with the protrusions455. As such, the width of the channel350may include a circumference of the protrusions455, and therefore the width of the channel350may be increased by twice the length T (seeFIG. 2) of the protrusions455, compared with the conventional art.

A gate insulating film500may be disposed within the trench450, a gate electrode600may be disposed on the gate insulating film500, and an oxide film510may be disposed on the gate insulating film500and the gate electrode600. The gate electrode600may fill the trench450.

A source electrode700may be formed on the p type epitaxial layer300, the n+ region400, and the oxide film510. A drain electrode800may be formed on a second surface of the n+ silicon carbide substrate100.

In this way, the width of the channel350can be increased compared to the conventional art by forming a plurality of protrusions455extending to the p type epitaxial layer300on both sides of the trench450.

With the increase in the width of the channel350, the resistance of the channel350can be reduced, and the amount of conduction current can be increased.

Moreover, the area of the semiconductor device can be reduced in order to obtain the same amount of current, thus leading to a reduction in production cost.

Now, a method for fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept will be described in detail with reference toFIGS. 3 to 6andFIG. 1.

FIG. 3toFIG. 6are views sequentially showing a method for fabricating a semiconductor device according to an exemplary embodiment of the present inventive concept.

As shown inFIG. 3, an n+ type silicon carbide substrate100may be prepared, then an n− type epitaxial layer200may be formed by first epitaxial growth on a first surface of the n+ type silicon carbide substrate100, then a p type epitaxial layer300may be formed by second epitaxial growth on the n− type epitaxial layer200, and then an n+ region400may be formed by third epitaxial growth on the p type epitaxial layer300.

Although the n+ region400may be formed by the third epitaxial growth in the an exemplary embodiment of the present inventive concept, the n+ region400may be formed by implanting ions into part of the p type epitaxial layer300, without performing epitaxial growth.

As shown inFIG. 4, a trench450may be formed by penetrating the n+ region400and the p type epitaxial layer300and by etching a part of the n− type epitaxial layer200.

As shown inFIG. 5, a plurality of protrusions455may be formed by etching a part of both sides of the trench450. The protrusions455may extend to the p type epitaxial layer300. That is, the protrusions455may be formed at contact areas between the sides of the trench450and the p type epitaxial layer300. Also, the protrusions455positioned on one side of the trench450may be spaced apart from each other.

As shown inFIG. 6, a gate insulating film500may be formed within the trench450, and a gate electrode600may be formed on the gate insulating film500. An oxide film510may be formed on the gate insulating film500and the gate electrode600. A part of the n+ region400may be etched.

A shown inFIG. 1, a source electrode700may be formed on the p type epitaxial layer300, the n+ region400, and the oxide film510. A drain electrode800may be formed on a second surface of the n+ type silicon carbide substrate100.