ESD improvement with dynamic substrate resistance

In some embodiments, an electrostatic discharge (ESD) protection circuit includes a substrate resistance control circuit coupled to a body of a first NMOS transistor. The substrate resistance control circuit increases a resistance of the body of the first NMOS transistor during an ESD event. The first NMOS transistor has a drain coupled to an input/output (I/O) pad and a gate coupled to a first voltage source. The first voltage source is set at ground potential.

FIELD OF DISCLOSURE

The disclosed systems and methods relate to integrated circuits. More specifically, the disclosed systems and methods relate to integrated circuits with improved electrostatic discharge (ESD) protection circuits.

BACKGROUND

With the continued miniaturization of integrated circuit (IC) devices, the current trend is to produce integrated circuits having shallower junction depths, thinner gate oxides, lightly-doped drain (LDD) structures, shallow trench isolation (STI) structures, and self-aligned silicide (salicide) processes, all of which are used in advanced sub-quarter-micron complementary metal oxide semiconductor (CMOS) technologies. All of these processes cause the related CMOS IC products to become more susceptible to damage due to ESD events. Therefore, ESD protection circuits are built onto the chip to protect the devices and circuits on the IC from ESD damage.

FIG. 1Aillustrates a conventional ESD protection circuit100, andFIGS. 1B and 1Dillustrate a plan view and a cross-sectional view of the GGNMOS106illustrated inFIG. 1A. As shown inFIG. 1A, the ESD protection circuit100includes control circuitry102connected to the gate of an output driver104and a gate-grounded NMOS transistor (GGNMOS)106serving as an ESD protection device. The trigger voltage, Vt1, of the output driver104is usually lower than the trigger voltage of the GGNMOS protection device106during an ESD event due to the gate of the output driver106being at an unknown state during the ESD event. The ESD event may damage the circuitry coupled to the output driver104as the voltage across the output driver104will be triggered before the GGNMOS106is triggered due to the higher trigger voltage of the GGNMOS106.

One prior art attempt to reduce the trigger voltage of the GGNMOS106′ is illustrated inFIGS. 1C and 1E. As shown inFIG. 1C, the GGNMOS106′ includes a P+ implantation region in the P-well below the drain. The inclusion of the P+ implantation region reduces the trigger voltage of the GGNMOS106′ and provides enhanced protection from ESD events. However, the additional protection comes at an additional process cost for the P+ implantation.

U.S. Pat. No. 6,465,768 issued to Ker et al. discloses a substrate biasing circuit for providing a higher substrate voltage during ESD events, which, for a given ESD current, enables the trigger voltage of the GGNMOS to be reduced. However, the circuit disclosed in Ker is designed for an RC time constant of 2 μs or greater to provide protection against ESD events and at the same time protect against false triggers during powering up. However, the size of the resistor and capacitor to achieve an RC time constant of approximately 2 μs or more must be quite large taking up valuable area on an integrated circuit.

Accordingly, an improved ESD protection circuit having a relatively small size is desirable.

SUMMARY

In some embodiments, an electrostatic discharge (ESD) protection circuit includes a substrate resistance control circuit coupled to a body of a first NMOS transistor. The substrate resistance control circuit increases a resistance of the body of the first NMOS transistor during an ESD event. The first NMOS transistor has a drain coupled to an input/output (I/O) pad and a gate coupled to a first voltage source. The first voltage source is set at ground potential.

In some embodiments, an electrostatic discharge (ESD) protection circuit includes a first NMOS transistor and a substrate resistance control circuit coupled to a body of the first NMOS transistor for increasing a resistance of the body of the first NMOS transistor during an ESD event. The first NMOS transistor has a gate coupled to ground through a first resistor, a drain coupled to a input/output (I/O) pad, and a source coupled to ground. The substrate resistance control circuit includes a second NMOS transistor and an RC circuit. The second NMOS transistor has a drain coupled to the body of the first NMOS transistor and a source coupled to a body of the second NMOS device and to ground. The RC circuit is coupled to a gate of the second NMOS transistor.

In some embodiments an electrostatic discharge (ESD) protection circuit includes a substrate resistance control circuit coupled to a body of a first NMOS transistor. The first NMOS transistor has a gate coupled to ground, a drain coupled to a input/output (I/O) pad, and a source coupled to ground. The substrate resistance control circuit increases a resistance of the body of the first NMOS transistor during an ESD event and includes a second NMOS transistor, a resistor, and a capacitor. The second NMOS transistor has a drain coupled to the body of the first NMOS transistor and a source coupled to a body of the second NMOS device and to ground. The first resistor is coupled to a first voltage source and to a first node. The first voltage source has a higher voltage potential than ground. The capacitor is coupled to the first node and to ground.

DETAILED DESCRIPTION

FIG. 2illustrates one example of an improved ESD protection circuit200. As shown inFIG. 2, the protection circuit200includes gate-grounded NMOS (GGNMOS) transistor202having a dynamic substrate resistance control circuit206coupled to its body. The dynamic substrate resistance control circuit206includes a resistor208coupled in series with a capacitor210at node214. The dynamic substrate resistance control circuit206also includes an NMOS transistor212having its gate coupled to node214, its source coupled to its body and low voltage source VSS, and its drain coupled to the body of the GGNMOS202. The source of the GGNMOS202is coupled to the I/O pad, PAD, and the drain is coupled to VSS as is the gate of the GGNMOS202through an optional resistor204. The drain and source of the GGNMOS2020form a parasitic lateral bipolar transistor218as illustrated inFIG. 2.

Resistor204may be added to reduce the trigger voltage of GGNMOS. In some embodiments, the resistor204may be a polysilicon (poly) resistor having a resistance of approximately 1 kΩ. One skilled in the art will understand that resistor204may have other resistances and be fabricated from other materials.

Resistor208and capacitor210of the substrate resistance control circuit206may be sized to provide an RC time constant between approximately 0.1 μs and 1 μs. For example, the resistor208may have a resistance between 100 kΩ and 1000 kΩ, and the capacitor may have a capacitance between 0.1 pF and 1 pF. The resistance and capacitance values of resistor208and capacitor210enable the sizes of each of enables the ESD protection circuit200to have a smaller footprint compared to conventional ESD protection circuits.

FIG. 3is a cross-sectional view of the ESD protection circuit200. As illustrated inFIG. 3, the GGNMOS202is formed on a P-type substrate302. A first shallow trench isolation (STI) structure306is formed between a first P+ diffusion region304and a first N+ diffusion region308. The STI structure306may be formed from a dielectric material such as, for example, silicon dioxide. The P+ diffusion regions may be doped with a Group III material including, but not limited to, boron, gallium, aluminum, or the like. The N+ diffusion regions may be doped with a suitable N-type dopant such as arsenic, phosphorus, antimony, or other Group V element.

A second N+ diffusion region310is disposed adjacent to a second STI structure312as is a second P+ diffusion region314. A third STI structure316is disposed adjacent to the second P+ diffusion region314and a third N+ diffusion region318. A fourth STI structure322is disposed between a fourth N+ diffusion region320and a third P+ diffusion region324. The drain of the NMOS212is coupled to each of the P+ regions304,314, and324. The N+ diffusion regions308and320are coupled to VSS and to polysilicon gates326and328through resistors204. N+ diffusion regions310and318are coupled to the PAD.

With reference toFIGS. 2 and 3, the operation of the improved ESD protection circuit200is now described. Under normal operation conditions, e.g., in the absence of an ESD event, node214will be at a voltage approximately equal to the voltage of VDD, and NMOS transistor212will be in the “on” state, e.g., current will be flowing from the source to the drain of NMOS transistor212, and the body of GGNMOS202is effectively coupled to ground. Thus, the voltage at node216will be approximately equal to VSS or ground and the body of GGNMOS202will have a relatively small resistance.

During an ESD event in which the PAD is positively zapped, the ESD voltage pulse causes an avalanche breakdown of transistor202thereby conducting current away from the internal circuit220. For example, when the PAD is zapped, the NMOS212will be switched “off” as its gate will be in a floating state and will effectively be at ground potential. With NMOS212off, little to no current flows from the source to the drain of NMOS212and its resistance, as well as the resistance of the body of the GGNMOS202, approaches infinity. With the body of GGNMOS202having a resistance approaching infinity, a small substrate current is induced by through impact ionization due to the ESD event turns on the parasitic lateral bipolar transistor218. For example, the voltage at node216(V216) will exceed the threshold voltage of the parasitic lateral bipolar transistor218(e.g., 0.7 V) since Vt1=V216=1*R>0.7 V and R approaches infinity. The turning on of the parasitic lateral bipolar transistor218causes an avalanche breakdown of GGNMOS202resulting in GGNMOS202turning on. With GGNMOS202on, current flows from the PAD to VSS through the GGNMOS202and is diverted the from the internal circuit220. Accordingly, due to the higher substrate resistance and lower trigger voltage, the ESD protection circuit200provides ESD protection to internal circuit220.

Advantageously, the ESD protection circuit200provides ESD protection without requiring additional processing such as P+ implantation. Additionally, the design of the ESD protection circuit200enables for smaller RC time constants compared to conventional ESD protection circuits reducing the size of the footprint of the ESD circuit on a substrate.