Method for producing a semiconductor device having SGTS

In a method for producing a semiconductor device, Si pillars that include i-layers, N+ regions that serve as lower impurity regions, N+ regions and a P+ region that serve as upper impurity regions, and i-layers are formed by using SiO2 layers as an etching mask. Thus, surrounding gate MOS transistors (SGTs) are produced in which the upper impurity regions and the lower impurity regions respectively function as impurity layers constituting a source or a drain of the SGTs formed in upper portions and lower portions of the Si pillars.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for producing a semiconductor device having surrounding gate MOS transistors (SGTs).

2. Description of the Related Art

In recent years, the use of SGTs as semiconductor elements that provide highly integrated semiconductor device has become widespread. With this background, higher integration of semiconductor devices having SGTs has been desired.

FIG. 13shows a complementary metal-oxide-semiconductor (CMOS) inverter circuit having typical metal-oxide-semiconductor (MOS) transistors. As shown inFIG. 13, this circuit is constituted by an N-channel type MOS transistor100aand a P-channel type MOS transistor100b. A gate101aof the N-channel type MOS transistor100aand a gate101bof the P-channel type MOS transistor100bare connected to an input terminal Vi. A source102aof the N-channel type MOS transistor100aand a source102bof the P-channel type MOS transistor100bare connected to an output terminal Vo. A drain103bof the P-channel type MOS transistor100bis connected to a power supply terminal Vdd. A drain103aof the N-channel type MOS transistor100ais connected to a ground terminal Vss. In this circuit, in response to the application of an input voltage corresponding to “1” or “0” to the input terminal Vi, an output voltage corresponding to inverted “0” or “1” is taken out from the output terminal Vo. Such a CMOS inverter circuit is used in various circuit chips such as microprocessors. The realization of highly integrated CMOS inverter circuits directly results in the reduction in the size of circuit chips such as microprocessors. This reduction in the size of circuit chips realizes the reduction in the cost of the circuit chips.

FIG. 14is a view showing a cross-sectional structure of a planar CMOS inverter circuit in the related art. As shown inFIG. 14, an N-well region105(hereinafter, a semiconductor region that forms a P-channel MOS transistor and contains a donor impurity is referred to as “N-well region”) is formed in a P-type semiconductor substrate104(hereinafter, a semiconductor substrate containing an acceptor impurity is referred to as “P-type semiconductor substrate”). Element isolation insulating layers106aand106bare formed between a surface layer portion of the N-well region105and a surface layer portion of the P-type semiconductor substrate104. Furthermore, a gate oxide film107afor a P-channel MOS transistor is formed on a surface of the N-well region105, and a gate oxide film107bfor an N-channel MOS transistor is formed on a surface of the P-type semiconductor substrate104. A gate conductor layer108afor the P-channel MOS transistor and a gate conductor layer108bfor the N-channel MOS transistor are respectively formed on the gate oxide films107aand107b. On the left side and the right side of the gate conductor layer108afor the P-channel MOS transistor, a drain P+region109a(hereinafter, a semiconductor region containing an acceptor impurity in a large amount is referred to as “P+region”) and a source P+region109bare respectively formed on a surface of the N-well region105. Similarly, on both sides of the gate conductor layer108bfor the N-channel MOS transistor, a drain N+region110b(hereinafter, a semiconductor region containing a donor impurity in a large amount is referred to as “N+region”) and a source N+region110aare formed on a surface of the P-type semiconductor substrate104. Furthermore, a first interlayer insulating layer111is formed, and contact holes112a,112b,112c, and112dare formed in the first interlayer insulating layer111on the P+regions109aand109band the N+regions110aand110b, respectively. A power supply wiring metal layer Vdd formed on the first interlayer insulating layer111is connected to the drain P+region109aof the P-channel MOS transistor through the contact hole112a. An output wiring metal layer Vo formed on the first interlayer insulating layer111is connected to the source P+regions109bof the P-channel MOS transistor and the source N+region110aof the N-channel MOS transistor through the contact holes112band112c, respectively. A ground wiring metal layer Vss is connected to the drain N+region110bof the N-channel MOS transistor through the contact hole112d. Furthermore, a second interlayer insulating layer113is formed. Contact holes114aand114bare formed in the second interlayer insulating layer113on the gate conductor layer108afor the P-channel MOS transistor and the gate conductor layer108bfor the N-channel MOS transistor, respectively. Furthermore, an input wiring metal layer Vi formed on the second interlayer insulating layer113is connected to the gate conductor layer108afor the P-channel MOS transistor and the gate conductor layer108bfor the N-channel MOS transistor through the contact holes114aand114b, respectively.

In this known example, in order to reduce a surface occupation area of the planar CMOS inverter circuit, it is necessary to reduce two-dimensional sizes of the gate conductor layer108afor the P-channel MOS transistor, the gate conductor layer108bfor the N-channel MOS transistor, the source N+region110aand the drain N+region110bfor the N-channel MOS transistor, the drain P+region109aand the source P+region109bfor the P-channel MOS transistor, the contact holes112a,112b,112c,112d,114a, and114bwhen the surface of the P-type semiconductor substrate104is viewed from above. To achieve this, high-resolution processing techniques such as a lithography technique and an etching technique for further reducing a processing size are necessary.

In the planar MOS transistor, channels of the P-channel MOS transistor and the N-channel MOS transistor are disposed between the source and the drain so as to extend in the horizontal direction along surfaces of the P-type semiconductor substrate104and the N-well region105. In contrast, channels of SGTs are disposed so as to extend in a direction perpendicular to a surface of a semiconductor substrate (refer to, for example, Japanese Unexamined Patent Application Publication Nos. 2-188966, and Hiroshi Takato, Kazumasa Sunouchi, Naoko Okabe, Akihiro Nitayama, Katsuhiko Hieda, Fumio Horiguchi, and Fujio Masuoka: IEEE Transaction on Electron Devices, Vol. 38, No. 3, pp. 573-578 (1991)).

FIG. 15Ais a structural schematic view of an N-channel SGT. As shown inFIG. 15A, N+regions116aand116bare formed on upper and lower positions of a P-type or i-type (intrinsic) Si pillar115(hereinafter, a silicon semiconductor pillar is referred to as “Si pillar”). When one of the N+regions116aand116bfunctions as a source, the other functions as a drain. When one of the N+regions116aand116bfunctions as a drain, the other functions as a source. The Si pillar115located between the source/drain N+regions116aand116bfunctions as a channel region117. A gate insulating layer118is formed so as to surround the channel region117. A gate conductor layer119is formed so as to surround the gate insulating layer118. In the SGT, the source/drain N+regions116aand116b, the channel region117, the gate insulating layer118, and the gate conductor layer119are formed in or on the single Si pillar115. Therefore, the surface occupation area of the SGT apparently corresponds to a single source or drain N+region of a planar MOS transistor. Accordingly, regarding circuit chips including SGTs, a further reduction in the chip size can be realized compared with circuit chips including planar MOS transistors.

FIG. 15Bis a cross-sectional view of an inverter circuit having SGTs (refer to, for example, U.S. Pat. No. 8,188,537). As shown inFIG. 15B, an i-layer121(The term “i-layer” refers to an intrinsic Si layer, and an intrinsic Si layer is hereinafter referred to as “i-layer”.) is formed on an insulating layer substrate120. A Si pillar SP1for a P-channel SGT and a Si pillar SP2for an N-channel SGT are formed on the i-layer121. A source P+region122of the P-channel SGT is formed in the i-layer121connected to a lower portion of the Si pillar SP1for the P-channel SGT so as to be integrated with the i-layer121and to surround a lower portion of the Si pillar SP1. Similarly, a source N+region123of the N-channel SGT is formed so as to be integrated with the i-layer121and to surround a lower portion of the Si pillar SP2. Furthermore, a drain P+region124of the P-channel SGT is formed in an upper portion of the Si pillar SP1for the P-channel SGT, and a drain N+region125of the N-channel SGT is formed in an upper portion of the Si pillar SP2for an N-channel SGT. Gate insulating layers126aand126bare formed so as to surround the Si pillars SP1and SP2, respectively. A gate conductor layer127aof the P-channel SGT and a gate conductor layer127bof the N-channel SGT are formed so as to surround the gate insulating layers126aand126b, respectively. Insulating layers128aand128bare formed so as to surround the gate conductor layers127aand127b, respectively. The source P+region122of the P-channel SGT is connected to the source N+region123of the N-channel SGT through a silicide layer129b. A silicide layer129ais formed on the drain P+region124of the P-channel SGT. A silicide layer129cis formed on the drain N+region125of the N-channel SGT. An i-layer130abetween the P+regions122and124located in a lower portion and an upper portion of the Si pillar SP1functions as a channel of the P-channel SGT. An i-layer130bbetween the N+regions123and125located in a lower portion and an upper portion of the Si pillar SP2functions as a channel of the N-channel SGT.

Subsequently, a SiO2layer131is formed by a chemical vapor deposition (CVD) method so as to cover the insulating layer substrate120, the i-layer121, and the Si pillars SP1and SP2. Contact holes132a,132b, and132care formed in the SiO2layer131on the Si pillar SP1, the Si pillar SP2, and the source P+region122of the P-channel SGT and the source N+region123of the N-channel SGT, respectively. A power supply wiring metal layer Vdd formed on the SiO2layer131is connected to the drain P+region124of the P-channel SGT and the silicide layer129athrough the contact hole132a. An output wiring metal layer Vo formed on the SiO2layer131is connected to the source P+region122of the P-channel SGT, the source N+region123of the N-channel SGT, and the silicide layer129bthrough the contact hole132b. Furthermore, a ground wiring metal layer Vss formed on the SiO2layer131is connected to the drain N+region125of the N-channel SGT and the silicide layer129cthrough the contact hole132c. Furthermore, the gate conductor layer127aof the P-channel SGT and the gate conductor layer127bof the N-channel SGT are connected to each other and connected to an input wiring metal layer (not shown). In this inverter circuit having SGTs, since the P-channel SGT and the N-channel SGT are respectively formed in the Si pillar SP1and the Si pillar SP2, the circuit area when viewed from the vertical direction is reduced. As a result, the size of the inverter circuit can be further reduced as compared with an inverter circuit having planar MOS transistors in the related art.

Further reduction in the size of a circuit chip having SGTs is desired. To meet this need, it has been assumed that the circuit area when viewed from the vertical direction can be reduced by forming two SGTs in a single Si pillar SPa, as shown in a structural schematic view ofFIG. 16(refer to, for example, Hyoungjun Na and Tetsuo Endoh: “A New Compact SRAM cell by Vertical MOSFET for Low-power and Stable Operation”, Memory Workshop (IMW)-2011 3rd IEEE International Digest P1-P4 2011). As shown inFIG. 16, a CMOS inverter circuit is formed in which an N-channel SGT133ais formed in a lower portion of the Si pillar SPa and a P-channel SGT133bis formed on the N-channel SGT133a. A drain N+region134aof the N-channel SGT133ais formed in a lower portion of the Si pillar SPa and is connected to a ground terminal Vss. A channel i-layer136ais formed on the drain N+region134a. A gate insulating layer137ais formed on an outer peripheral portion of the channel i-layer136a. A gate conductor layer138afor the N channel SGT is formed on an outer peripheral portion of the gate insulating layer137a. Furthermore, a source N+region134bis formed on the channel i-layer136a. A source P+region135aof the P-channel SGT133bis formed on the source N+region134bso as to be in contact with the source N+region134b. A channel i-layer136bis formed on the source P+region135a. A gate insulating layer137bis formed on an outer peripheral portion of the channel i-layer136b. A gate conductor layer138bused for the P-channel SGT133bis formed on an outer peripheral portion of the gate insulating layer137b—. Furthermore, a drain P+region135bis formed in a top portion of the Si pillar SPa, the top portion being located on the channel i-layer136b. The drain P+region135bis connected to a power supply terminal Vdd. The gate conductor layer138aof the N-channel SGT133aand the gate conductor layer138bof the P-channel SGT133bare connected to an input terminal Vi. The source N+region134bof the N-channel SGT133aand the source P+region135aof the P-channel SGT133bare connected to an output terminal Vo.

Referring toFIG. 16, in the case where an SGT inverter circuit is formed in the single Si pillar SPa, a problem of difficulty of manufacture occurs. It is necessary to form the source P+region135aof the P-channel SGT133band the source N+region134bof the N-channel SGT133aso that the source P+region135aand the source N+region134bare disposed in the middle of the Si pillar SPa and are in contact with each other. In the case where the planar MOS transistor circuit in the related art shown inFIG. 14is produced, the N+regions110aand110band the P+regions109aand109bcan be formed by an ion implantation method in which accelerated donor and acceptor impurity ions are implanted from an upper surface of the P-substrate104using, as a mask, a photoresist layer formed by using an existing photolithographic technique. Similarly, in the case where the inverter circuit having SGTs and shown inFIG. 15Bis formed, the N+region123and the P+region122can be formed by an ion implantation method in which accelerated donor and acceptor impurity ions are implanted from an upper surface of the insulating layer substrate120using, as a mask, a photoresist layer formed by using a photolithographic technique. In contrast, referring toFIG. 16, in the case where an inverter circuit is formed in the single Si pillar SPa, the N+region134band the P+region135acannot be formed by the ion implantation method used in the related art. This is because ions cannot be implanted from a horizontal direction into a side face of the Si pillar by the ion implanting method used in the related art. Instead of this method, the following method is conceivable: A donor or acceptor impurity is diffused into a Si pillar SPa by diffusing from, for example, a poly-Si or SiO2film that contains the donor or acceptor impurity into a side face near the middle of the Si pillar SPa. For this purpose, the whole Si pillar SPa is covered with a diffusion stopper film, and part of the diffusion stopper film located in a portion to be diffused is then removed. Subsequently, an impurity diffusion film is deposited, and heat treatment is performed to form the N+region134band the P+region135a. In this case, the N+region134band the P+region135acannot be formed at the same time, and thus it is necessary to form the N+region134band the P+region135aseparately. Therefore, it is difficult to form the N+region134band the P+region135ain the vertical direction with a high accuracy.

Furthermore, producing an SGT circuit having a structure in which both an N-channel SGT and a P-channel SGT are provided in a lower portion and both an N-channel SGT and a P-channel SGT are further provided in an upper portion further increases the difficulty of manufacture, for example, as in the case where the structure shown inFIG. 17A, in which a P-channel SGT139ais formed in a lower portion of a single Si pillar SPb and an N-channel SGT139bis formed on the P-channel SGT139a, and the structure shown inFIG. 17B, in which an N-channel SGT140ais formed in a lower portion of a single Si pillar SPc and an N-channel SGT140bhaving the same structure as the N-channel SGT140ais further formed on the N-channel SGT140a, are formed.

SUMMARY OF THE INVENTION

A method for producing a semiconductor device having surrounding gate MOS transistors (SGTs) according to the present invention includes a first impurity-region-forming step of forming one or both of a first impurity region containing a donor impurity and a second impurity region containing an acceptor impurity in a single layer in a surface layer portion of a semiconductor substrate; a first semiconductor-layer-forming step of forming a first semiconductor layer above the semiconductor substrate; a second impurity-region-forming step of forming one or both of a third impurity region containing a donor impurity and a fourth impurity region containing an acceptor impurity in a single layer in a surface layer portion of the first semiconductor layer; a second semiconductor-layer-forming step of forming a second semiconductor layer above the first semiconductor layer; an island-shaped semiconductor-forming step of etching the second semiconductor layer, the first semiconductor layer, and the semiconductor substrate from an upper surface of the second semiconductor layer to form a plurality of first island-shaped semiconductors each of which includes the semiconductor substrate, the first semiconductor layer, and the second semiconductor layer and in which the first impurity region and the second impurity region are overlapped with one or other of the third impurity region and the fourth impurity region in a perpendicular direction with respect to a surface of the semiconductor substrate; a third impurity-region-forming step of forming a fifth impurity region containing a donor impurity in a bottom portion of a first island-shaped semiconductor having the first impurity region and forming a sixth impurity region containing an acceptor impurity in a bottom portion of a first island-shaped semiconductor having the second impurity region; a gate insulating layer-forming step of forming a gate insulating layer so as to surround the first island-shaped semiconductors; a gate conductor layer-forming step of forming a gate conductor layer so as to surround the gate insulating layer; and a fourth impurity-region-forming step of forming a seventh impurity region containing a donor impurity in a top portion of the first island-shaped semiconductor having the third impurity region and forming an eighth impurity region containing an acceptor impurity in a top portion of the first island-shaped semiconductor having the fourth impurity region, the top portions being located above the gate insulating layer and the gate conductor layer. In the method, one or both of a first SGT and a second SGT are formed on the lower portion side of the first island-shaped semiconductors, the first SGT including the first impurity region and the fifth impurity region, one of which functions as a source and the other of which functions as a drain, the semiconductor substrate of the first island-shaped semiconductor which functions as a channel, and the gate conductor layer which functions as a gate, the second SGT including the second impurity region and the sixth impurity region, one of which functions as a source and the other of which functions as a drain, the semiconductor substrate of the first island-shaped semiconductor which functions as a channel, and the gate conductor layer which functions as a gate. In addition, one or both of a third SGT and a fourth SGT are formed on the upper portion side of the first island-shaped semiconductors, the third SGT including the third impurity region and the seventh impurity region, one of which functions as a source and the other of which functions as a drain, the second semiconductor layer of the first island-shaped semiconductor which functions as a channel, and the gate conductor layer which functions as a gate, the fourth SGT including the fourth impurity region and the eighth impurity region, one of which functions as a source and the other of which functions as a drain, the second semiconductor layer of the first island-shaped semiconductor which functions as a channel, and the gate conductor layer which functions as a gate.

The semiconductor device is preferably formed so that a length of each of the third impurity region, the fourth impurity region, the seventh impurity region, and the eighth impurity region in the vertical direction is larger than a diameter of a horizontal cross section of each of the first island-shaped semiconductors.

The semiconductor device is preferably formed so that a length of the third impurity region in the vertical direction is larger than a length of the seventh impurity region in the vertical direction, and a length of the fourth impurity region in the vertical direction is larger than a length of the eighth impurity region in the vertical direction.

In a step of forming the third SGT and the fourth SGT where a diameter of a horizontal cross section of each of the first island-shaped semiconductors, the diameter being determined from a circuit design value, is decreased, the semiconductor device is preferably formed so that a rate of increase in a length of each of the third impurity region and the fourth impurity region in the vertical direction is equal to or larger than a value of the negative second power of a rate of decrease in the diameter of the horizontal cross section of each of the first island-shaped semiconductors.

The semiconductor device is preferably formed so that at least one of a diameter of a horizontal cross section of the seventh impurity region and a diameter of a horizontal cross section of the eighth impurity region is larger than the diameter of the horizontal cross section of each of the first island-shaped semiconductors.

Immediately after the island-shaped semiconductor-forming step, preferably, the first impurity region, the second impurity region, the third impurity region, the fourth impurity region, the fifth impurity region, the sixth impurity region, the seventh impurity region, and the eighth impurity region are not exposed from side faces of the first island-shaped semiconductors.

Immediately before the gate insulating layer-forming step, preferably, the first impurity region, the second impurity region, the third impurity region, the fourth impurity region, the fifth impurity region, the sixth impurity region, the seventh impurity region, and the eighth impurity region are not exposed from side faces of the first island-shaped semiconductors.

In the second impurity-region-forming step, preferably, the third impurity region and the fourth impurity region are not in contact with the first impurity region and the second impurity region.

The first impurity region and the second impurity region are preferably formed in the semiconductor substrate so as to be located more inside than a surface of the semiconductor substrate, and the first semiconductor layer is preferably subsequently formed.

The third impurity region and the fourth impurity region are preferably formed in the first semiconductor layer so as to be located more inside than a surface of the first semiconductor layer, and the second semiconductor layer is preferably subsequently formed.

The method preferably includes the steps of forming a ninth impurity region containing a donor or acceptor impurity inside the semiconductor substrate with respect to a depth direction of the semiconductor substrate; forming a tenth impurity region of the same conductivity type as the ninth impurity region in a surface layer portion of the semiconductor substrate; subsequently forming the first semiconductor layer; and allowing the ninth impurity region to be located in a bottom portion of the first island-shaped semiconductors.

The semiconductor device is preferably formed so that a first channel length of the first SGT and the second SGT and a second channel length of the third SGT and the fourth SGT are different from each other, the first SGT including, as the channel, the semiconductor substrate between the source and the drain constituted by the first impurity region and the fifth impurity region, the second SGT including, as the channel, the semiconductor substrate between the source and the drain constituted by the second impurity region and the sixth impurity region, the third SGT including, as the channel, the second semiconductor layer between the source and the drain constituted by the third impurity region and the seventh impurity region, the fourth SGT including, as the channel, the second semiconductor layer between the source and the drain constituted by the fourth impurity region and the eighth impurity region.

The first SGT or the second SGT is preferably formed in the first island-shaped semiconductor or a second island-shaped semiconductor that is formed separately from the first island-shaped semiconductor, and the gate conductor layer of any of the first SGT and the second SGT is preferably allowed to electrically float or formed so as to have a ground potential so that any of the first SGT and the second SGT is formed so as not to be present on a circuit.

Preferably, the second island-shaped semiconductor includes the first SGT or the second SGT including the electrically floating gate conductor layer, and an impurity region functioning as a source or a drain is not formed in a bottom portion or a top portion of the second island-shaped semiconductor.

One or both of the first island-shaped semiconductor including the first SGT and the third SGT that include the first impurity region, the third impurity region, the fifth impurity region, and the seventh impurity region, and the first island-shaped semiconductor including the second SGT and the fourth SGT that include the second impurity region, the fourth impurity region, the sixth impurity region, and the eighth impurity region are preferably formed, and the gate conductor layer of the first SGT and the gate conductor layer of the third SGT are preferably formed so as to be connected to each other.

According to the present invention, in producing a circuit in which a plurality of SGTs are formed in a single semiconductor pillar in the vertical direction, N+regions or P+regions that contain a donor or acceptor impurity and that constitute sources or drains of the SGTs can be formed at predetermined positions between the SGTs with a high accuracy.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

As described with reference toFIGS. 16,17A, and17B, in a method for producing a semiconductor device having SGTs, a plurality of SGTs are formed in a single Si pillar so as to be stacked in the vertical direction, and a plurality of such Si pillars are formed so that a combination of an N-channel SGT and a P-channel SGT located in an upper portion and a lower portion in the vertical direction is different from adjacent combinations of an N-channel SGT and a P-channel SGT located in an upper portion and a lower portion in the vertical direction. In this method, it is difficult to form N+regions and P+regions that contain a donor or acceptor impurity at particular positions in the middle of the Si pillars with a high accuracy.

Methods for producing a semiconductor device having SGTs according to embodiments of the present invention will now be described with reference to the drawings.

First Embodiment

FIGS. 1A to 1Cand FIGS.2A(a) to2W(c) show a method for producing a semiconductor device having SGTs according to a first embodiment of the present invention.

FIG. 1Ais a circuit diagram of a static random access memory (SRAM) cell according to the present embodiment. As shown inFIG. 1A, the SRAM cell includes two inverter circuits IV1and IV2. The inverter circuit IV1includes a P-channel SGT_P1serving as a load transistor and two N-channel SGTs_N11and N12that serve as drive transistors and that are connected to each other in parallel. The inverter circuit IV2includes a P-channel SGT_P2serving as a load transistor and two N-channel SGTs_N21and N22that serve as drive transistors and that are connected to each other in parallel. The P-channel SGT_P1of the inverter circuit IV1is connected to gates of the N-channel SGTs_N11and N12. A source of the P-channel SGT_P2of the inverter circuit IV2is connected to sources of the N-channel SGTs_N21and N22. Similarly, the P-channel SGT_P2is connected to gates of the N-channel SGTs_N21and N22. A source of the P-channel SGT_P1of the inverter circuit IV1is connected to sources of the N-channel SGTs_N11and N12.

Drains of the P-channel SGTs_P1and P2are connected to a power supply voltage wiring Vdd. Drains of the N-channel SGTs_N11, N12, N21, and N22are connected to a ground wiring Vss. Selection N-channel SGTs_SN1and SN2are provided on both sides of the inverter circuits IV1and IV2. Gates of the selection N-channel SGTs_SN1and SN2are connected to a word line wiring metal layer WL. A source and a drain of the selection N-channel SGT_SN1are respectively connected to the sources of the N-channel SGTs_N11and N12and the P-channel SGT_P1and an inversion bit line wiring metal layer BLB. A source and a drain of the selection N-channel SGT_SN2are respectively connected to the sources of the N-channel SGTs_N21and N22and the P-channel SGT_P2and a bit line wiring metal layer BL. Thus, the SRAM circuit of the present embodiment is constituted by total 8 SGTs including the two P-channel SGTs_P1and P2and the six N-channel SGTs_N11, N12, N21, N22, SN1, and SN2.

FIG. 1Bis a structural schematic view of a case where the SRAM cell circuit shown inFIG. 1Ais formed in four Si pillars H1, H2, H3, and H4. As shown inFIG. 1B, a driving N-channel SGT_N11of an inverter circuit IV1is formed in a lower portion of the Si pillar H1, and a selection N-channel SGT_SN1is formed in an upper portion of the Si pillar H1. A driving N-channel SGT_N12of the inverter circuit IV1is formed in a lower portion of the Si pillar H2, and a load P-channel SGT_P1is formed in an upper portion of the Si pillar H2. A driving N-channel SGT_N22of an inverter circuit IV2is formed in a lower portion of the Si pillar H3, and a load P-channel SGT_P2is formed in an upper portion of the Si pillar H3. A driving N-channel SGT_N21is formed in a lower portion of the Si pillar H4, and a selection N-channel SGT_SN2is formed in an upper portion of the Si pillar H4.

In the driving N-channel SGT_N11formed in the lower portion of the Si pillar H1, a drain N+region1a, a channel i-layer2a, and a source N+region3aare formed so as to be connected from the lower portion to the upper portion of the Si pillar H1in that order. A gate insulating layer4ais formed so as to surround the channel i-layer2a. Furthermore, a gate conductor layer5ais formed so as to surround the gate insulating layer4a. In the selection N-channel SGT_SN1formed in the upper portion of the Si pillar H1, a drain N+region6a, a channel i-layer7a, and a source N+region8aare formed so as to be connected from the lower portion to the upper portion in that order. A gate insulating layer9ais formed so as to surround the channel i-layer7a. Furthermore, a gate conductor layer10ais formed so as to surround the gate insulating layer9a. In the driving N-channel SGT_N12formed in the lower portion of the Si pillar H2, a drain N+region1b, a channel i-layer2b, and a source N+region3bare formed so as to be connected from the lower portion to the upper portion of the Si pillar H2in that order. A gate insulating layer4bis formed so as to surround the channel i-layer2b. Furthermore, a gate conductor layer5bis formed so as to surround the gate insulating layer4b. In the load P-channel SGT_P1formed in the upper portion of the Si pillar H2, a source P+region6b, a channel i-layer7b, and a drain P+region8bare formed so as to be connected from the lower portion to the upper portion. A gate insulating layer9bis formed so as to surround the channel i-layer7b. Furthermore, a gate conductor layer10bis formed so as to surround the gate insulating layer9b.

As shown inFIG. 1B, in the driving N-channel SGT_N22formed in the lower portion of the Si pillar H3, a drain N+region1c, a channel i-layer2c, and a source N+region3care formed so as to be connected from the lower portion to the upper portion of the Si pillar H3in that order. Furthermore, a gate insulating layer4cis formed so as to surround the channel i-layer2c. A gate conductor layer5cis formed so as to surround the gate insulating layer4c. In the load P-channel SGT_P2formed in the upper portion of the Si pillar H3, a source P+region6c, a channel i-layer7c, and a drain P+region8care formed so as to be connected from the lower portion to the upper portion in that order. A gate insulating layer9cis formed so as to surround the channel i-layer7c. Furthermore, a gate conductor layer10cis formed so as to surround the gate insulating layer9c. In the driving N-channel SGT_N21formed in the lower portion of the Si pillar H4, a drain N+region1d, a channel i-layer2d, and a source N+region3dare formed so as to be connected from the lower portion to the upper portion of the Si pillar H4. A gate insulating layer4dis formed so as to surround the channel i-layer2d. Furthermore, a gate conductor layer5dis formed so as to surround the gate insulating layer4d. In the selection N-channel SGT_SN2formed in the upper portion of the Si pillar H4, a source N+region6d, a channel i-layer7d, and a drain N+region8dare formed so as to be connected from the lower portion to the upper portion in that order. Furthermore, a gate insulating layer9dis formed so as to surround the channel i-layer7d. A gate conductor layer10dis formed so as to surround the gate insulating layer9d.

The gate conductor layer10bof the load P-channel SGT_P1of the inverter circuit IV1is connected to the gate conductor layer5aof the N-channel SGT_N11, and the gate conductor layer5bof the N-channel SGT_N12. The gate conductor layers10b,5a, and5bare connected to the source P+region6cof the load P-channel SGT_P2and the source N+regions3dand3cof the driving N-channel SGTs_N21and N22. Similarly, the gate conductor layer10cof the load P-channel SGT_P2is connected to the gate conductor layer5dof the driving N-channel SGT_N21and the gate conductor layer5cof the driving N-channel SGT N22. The gate conductor layers10c,5d, and5care connected to the source P+region6bof the load P-channel SGT_P1and the source N+regions3aand3bof the driving N-channel SGTs_N11and N12.

The drain P+regions8band8cof the load P-channel SGTs_P1and P2are connected to a power supply voltage wiring Vdd. Furthermore, the drain N+regions1a,1b,1d, and1cof the driving N-channel SGTs_N11, N12, N21, and N22are connected to a ground wiring Vss. The gate conductor layers10aand10dof the selection N-channel SGTs_SN1and SN2are connected to a word line wiring metal layer WL. The N+region6aof the selection N-channel SGT_SN1is connected to the source N+regions3aand3bof the N-channel SGTs_N11and N12and the source P+region6bof the load P-channel SGT_P1. The N+region6dof the selection N-channel SGT_SN2is connected to the source N+regions3dand3cof the driving N-channel SGTs_N21and N22, and the source P+region6cof the load P-channel SGT_P2. Furthermore, the N+region8aof the selection N-channel SGT_SN1is connected to an inversion bit line wiring metal layer BLB. The N+region8dof the selection N-channel SGT_SN2is connected to a bit line wiring metal layer BL. In the present embodiment, eight SGTs that constitute the SRAM cell are formed in the four Si pillars H1, H2, H3, and H4as described above.

FIG. 1Cis a plan view of an arrangement of the Si pillars H1, H2, H3, and H4shown in the structural schematic view of the SRAM cell circuit shown inFIG. 1B. As shown inFIG. 1C, a single SRAM cell is formed in a broken line area11including Si pillars H1, H2, H3, and H4. An inverter circuit IV1and a selection N-channel SGT_SN1are formed in a two-dot chain line area12aincluding the Si pillars H1and H2. An inverter circuit IV2and a selection N-channel SGT_SN2are formed in a two-dot chain line area12bincluding the Si pillars H3and H4. Si pillars H5and H6are Si pillars each including a driving N-channel SGT and a selection N-channel SGT of an SRAM cell adjacent in the vertical direction. The Si pillars H1, H2, and H6are arranged on a straight line in the horizontal direction. Similarly, the Si pillars H5, H3, and H4are arranged on a straight line in the horizontal direction. Furthermore, the Si pillars H1and H5are arranged on a straight line in the vertical direction. The Si pillars H2and H3are arranged on a straight line in the vertical direction. The Si pillars H6and H4are arranged on a straight line in the vertical direction. In this SRAM device, the SRAM cell in the broken line area11is two-dimensionally arranged on a substrate.

To illustrate a first production step of a method for producing an SRAM cell circuit, FIGS.2A(a),2A(b) and2A(c) show a plan view and cross-sectional structural views of an area where the Si pillars H1to H6shown inFIG. 1Care arranged. FIG.2A(a) is a plan view, FIG.2A(b) is a cross-sectional structural view taken along line X-X′ (corresponding to line X-X′ inFIG. 1C), and FIG.2A(c) is a cross-sectional structural view taken along line Y-Y′ (corresponding to line Y-Y′ inFIG. 1C). In respective drawings used in the description below, the relationships between (a), (b), and (c) are the same as those in FIGS.2A(a),2A(b) and2A(c).

A method for producing the SRAM cell circuit shown inFIGS. 1A,1B, and1C will now be described with reference to FIGS.2A(a) to2W(c). First, as shown in FIGS.2A(a),2A(b) and2A(c), a SiO2layer14is formed on an i-layer substrate13by, for example, a thermal oxidation method. Arsenic ions (As+) are introduced from above the SiO2layer14by ion implantation to form an N+region15in a surface layer portion of the i-layer substrate13.

Subsequently, as shown in FIGS.2B(a),2B(b) and2B(c), a resist layer20and the SiO2layer14are removed, and an i-layer16is formed on the N+region15by, for example, a low-temperature epitaxial growth process. A SiO2layer17is further formed on the i-layer16by, for example, a CVD method. Subsequently, resist layers18aand18bare formed on the SiO2layer17so as to cover regions where the Si pillars H5, H1, H4, and H6are formed. Furthermore, boron ions (B+), which are acceptor impurity ions, are introduced from the upper surface of the i-layer substrate13by ion implantation. Thus, a P+region19is formed in a portion of the i-layer16, the portion not being covered with the resist layers18aand18b.

Subsequently, as shown in FIGS.2C(a),2C(b) and2C(c), the resist layers18aand18bare removed, and a resist layer20is formed on the SiO2layer17so as to cover a region where the Si pillars H2and H3are present. Arsenic ions (As+), which are donor impurity ions, are introduced from the upper surface of the i-layer substrate13by ion implantation. Thus, N+regions21aand21bare formed in the i-layer16.

Subsequently, as shown in FIGS.2D(a),2D(b) and2D(c), the SiO2layer17is removed, and an i-layer22is formed by, for example, a low-temperature Si epitaxial growth process, on the N+regions21aand21band the P+region19, which are exposed by removing the SiO2layer17.

Subsequently, as shown in FIGS.2E(a),2E(b) and2E(c), the i-layer22, the N+regions21aand21b, the P+region19, the N+region15, and the i-layer substrate13are etched by, for example, a reactive ion etching (RIE) method using SiO2layers23a,23b, and23cas an etching mask to form Si pillars H1to H6. Consequently, in the Si pillar H5, an i-layer24a, an N+region25a, an N+region26a, an i-layer27a, and the SiO2layer23aare formed on and above an i-layer substrate13a. In the Si pillar H3, an i-layer24b, an N+region25b, a P+region26b, an i-layer27b, and the SiO2layer23bare formed on and above the i-layer substrate13a. In the Si pillar H4, an i-layer24c, an N+region25c, an N+region26c, an i-layer27c, and the SiO2layer23care formed on and above the i-layer substrate13a. Regarding the Si pillars H1, H2, and H6, similar structures are formed.

Subsequently, as shown in FIGS.2F(a),2F(b) and2F(c), a SiO2layer is deposited on the i-layer substrate13aand the Si pillars H1to H6by a CVD method. The whole SiO2layer is then etched by an isotropic plasma etching method, whereby the SiO2layer on the side faces of the Si pillars H1to H6is removed and SiO2layers28a,28b,28c, and28dare left on the i-layer substrate13a. This step utilizes a phenomenon that when the SiO2layers28a,28b,28c, and28dare deposited by a CVD method, the SiO2layers are deposited on the side faces of the Si pillars H1to H6so as to have a small thickness and deposited on the i-layer substrate13aso as to have a large thickness. Furthermore, SiO2layers29a,29b,29c,29d,29e, and29fare formed on outer peripheral portions of the Si pillars H1to H6by a thermal oxidation method.

Subsequently, as shown in FIGS.2G(a),2G(b) and2G(c), arsenic ions (As+), which are donor impurity ions, are introduced from the vertical direction into the upper surface of the i-layer substrate13aby ion implantation. Thus, N+regions30a,30b,30c, and30dare formed in a surface layer portion of the i-layer substrate13abetween the Si pillars H1to H6. These N+regions30a,30b,30c, and30dare connected to each other in the surface layer portion of the i-layer substrate13alocated outside the Si pillars H1to H6.

Subsequently, as shown in FIGS.2H(a),2H(b) and2H(c), after the SiO2layers29a,29b,29c,29d,29e, and29fon the outer peripheral portions of the Si pillars H1to H6are removed, gate SiO2layers34a,34b, and34care newly formed on the outer peripheral portions of the Si pillars H1to H6by a thermal oxidation method. Subsequently, a titanium nitride (TiN) layer32serving as a gate metal layer is formed over the entire surface by, for example, an atomic layer deposition (ALD) method, and a SiO2layer35is formed thereon by a CVD method.

Subsequently, as shown in FIGS.2I(a),2I(b) and2I(c), a TiN layer32band a SiO2layer35b, each of which covers and extends over the Si pillars H3and H4, are formed by using a lithography method and an RIE etching method. In addition, a TiN layer32aand a SiO2layer35aare formed at the same time so as to cover the Si pillar H5. Similarly, TiN layers32cand32dand SiO2layers35cand35dare formed on the Si pillars H1, H2, and H6on the plane of (a).

Subsequently, as shown in FIGS.2J(a),2J(b) and2J(c), for example, a silicon nitride (SiN) layer36is formed on the i-layer substrate13aso as to be located on a lower portion of the Si pillars H1to H6. In this step, the SiN layer36is formed so that the surface of the SiN layer36is located within a height range in the vertical direction in which the N+regions25a,25b, and25cof the Si pillars H1to H6are formed.

Subsequently, as shown in FIGS.2K(a),2K(b) and2K(c), a resist layer37is formed on the SiN layer36. Heat treatment is then performed, for example, at about 200° C. to planarize the resist layer37. In this step, the resist layer37is formed so that the surface of the resist layer37is located within a height range in the vertical direction in which the N+regions26aand26cand the P+region26bare formed. Hydrofluoric acid (HF) gas is then supplied to the entire surface. This HF gas is diffused in the resist layer37and reacts with water in the resist layer37to produce liquid HF. This liquid HF etches the SiO2layers35aand35bthat are in contact with the resist layer37. The resist layer37is then removed (regarding the mechanism of the etching, refer to Tadashi Shibata, Susumu Kohyama, and Hisakazu lizuka: “A New Field Isolation Technology for High Density MOS LSI”, Japanese Journal of Applied Physics, Vol. 18, pp. 263-267 (1979)).

Subsequently, as shown in FIGS.2L(a),2L(b) and2L(c), the SiO2layers35aand35bthat are in contact with the resist layer37are etched, and exposed regions38a,38b, and38cof the TiN layers32aand32bappear to outer peripheral portions of the Si pillars H5, H3, and H4, respectively. At the same time, the TiN layers32cand32dlocated at positions that are in contact with the resist layer37are similarly exposed to outer peripheral portions of the Si pillars H1, H2, and H6. Consequently, in the Si pillar H5, a lower portion of the SiO2layer35ais separated to form a SiO2layer35e. In the Si pillar H3, a lower portion of the SiO2layer35bis separated to form a SiO2layer35f. In the Si pillar H4, an upper portion of the SiO2layer35bis separated to form a SiO2layer35i. Similarly, a SiO2layer35gis formed in lower portions of the Si pillars H1and H2, and a SiO2layer35his formed in a lower portion of the Si pillar H6.

Subsequently, as shown in FIGS.2M(a),2M(b) and2M(c), the TiN layers32a,32b,32c, and32dare etched using the SiO2layers35a,35b,35i,35e, and35fas an etching mask. By this etching, in the Si pillar H5, a lower portion of the TiN layer32ais separated to form a TiN layer32e. In the Si pillar H3, a lower portion of the TiN layer32bis separated to form a TiN layer32f. Furthermore, in the Si pillar H4, an upper portion of the TiN layer32bis separated to form a TiN layer32i. Similarly, a TiN layer32gis formed on a lower portion of the Si pillars H1and H2, and a TiN layer32his formed on a lower portion of the Si pillars H6. As shown in (a), a state where the TiN layers32e,32f,32g, and32hare arranged on the Si pillars H1to H6is obtained through the above process, when viewed from the upper surface. Furthermore, as shown in (b), the gate SiO2layers34a,34b, and34care etched using the TiN layers32a,32b,32i,32e, and32fas an etching mask. In the present embodiment, the SiO2layers35aand35bare formed so as to have a larger thickness than the gate SiO2layers34a,34b, and34c. Thus, the SiO2layers35a,35b, and35iare left after the etching of the gate SiO2layers34a,34b, and34c. The gate SiO2layers34a,34b, and34care separated into an upper portion and a lower portion of the Si pillars H5, H3, and H4, respectively. The lower portions of the gate SiO2layers34a,34b, and34cconstitute gate SiO2layers34d,34e, and34f, respectively.

Subsequently, as shown in FIG.2N(b), exposed portions of the TiN layers32a,32b,32i,32e, and32fare oxidized to form titanium oxide (TiO) layers41a,41b,41c,40a,40b, and40c. Furthermore, a SiO2layer42is then formed over the entire surface by a CVD method. In this step, the SiO2layer42is deposited so as to have a small thickness on side faces of the Si pillars H1to H6and a large thickness on top portions of the Si pillars H1to H6and on the surface of the SiN layer36.

Subsequently, as shown in FIGS.2O(a),2O(b) and2O(c), a resist layer43is formed by using the same method as that used in the formation of the resist layer37described above. The resist layer43is formed so that the position of the upper surface of the resist layer43is located within a height range in the vertical direction in which the N+regions26aand26cand the P+region26bof the Si pillars H5, H4, and H3are formed. Hydrofluoric acid (HF) gas is then supplied from the upper surface of the Si pillars H1to H6. Thus, as in FIGS.2K(a),2K(b) and2K(c), the HF gas is diffused in the resist layer43and reacts with water in the resist layer43to produce liquid HF. This liquid HF etches the SiO2layer42that is in contact with the resist layer43.

Subsequently, as shown in FIGS.2P(a),2P(b) and2P(c), when the resist layer43is removed, the SiO2layer42located at positions that are in contact with the resist layer43is etched. Thus, exposed regions44a,44b, and44con side faces of the N+regions25a,25b,25c,26a, and26cand the P+region26bof the Si pillars H5, H3, and H4are obtained. In the present embodiment, a SiO2layer42dwhich is a part of the SiO2layer42and deposited on the SiN layer36is in contact with the resist layer43. However, since the thickness of the SiO2layer42dis larger than that of SiO2layers42a,42b, and42con the side faces of the Si pillars H1to H6, the SiO2layer42dis left on the SiN layer36.

Subsequently, as shown in FIGS.2Q(a),2Q(b) and2Q(c), conductor layers45a,45b,45c, and45dformed by siliciding a poly-Si layer are formed so as to be connected to the N+regions25a,25b,25c,26a, and26cand the P+region26b. The conductor layer45bis formed by connecting the N+region25band the P+region26bof the Si pillar H3and the N+regions25cand26cof the Si pillar H4. The N+regions25aand26aof the Si pillar H5of an adjacent SRAM cell are connected to the conductor layer45a. The conductor layer45cis connected in the Si pillars H1and H2. The conductor layer45dis connected in the Si pillar H6of an adjacent SRAM cell.

Subsequently, as shown in FIGS.2R(a),2R(b) and2R(c), for example, a SiN layer46is formed so that a surface position thereof is located near central portions of the upper i-layers27a,27b, and27cof the Si pillars H1to H6.

Subsequently, as shown in FIGS.2S(a),2S(b) and2S(c), a resist layer is formed by the same method as that described with reference to FIGS.2K(a),2K(b),2K(c),2O(a),2O(b) and2O(c). Hydrofluoric acid (HF) gas is then supplied from the upper surface of the resist layer to etch the SiO2layers35a,35b,35c,42a,42b, and42con the side faces of the Si pillars H5, H3, and H4. Furthermore, conductor layers47a,47b,47c, and47dare formed by the method described with reference to FIGS.2Q(a),2Q(b) and2Q(c). The conductor layer47ais connected to the upper TiN layer32aof the Si pillar H5. The conductor layer47bis connected to the upper TiN layer32bof the Si pillar H3. The conductor layer47dis connected to the upper TiN layer32iof the Si pillar H4. Furthermore, as shown in FIGS.2S(a),2S(b) and2S(c), the conductor layer47ais formed so as to connect the Si pillar H5to the Si pillar H1, and the conductor layer47dis formed so as to connect the Si pillar H4to the Si pillar H6.

Subsequently, as shown in FIGS.2T(a),2T(b) and2T(c), a resist layer48is formed such that a surface position thereof is lower than the top portions of the Si pillars H1to H6.

Subsequently, as shown in FIGS.2U(a),2U(b) and2U(c), the SiO2layers42a,42b,42c,35a,35b, and35c, the TiN layers32a,32b, and32i, and the gate SiO2layers34a,34b, and34care etched using the resist layer48as an etching mask. The resist layer48is then removed. Subsequently, N+regions49d,49c,49a, and49fare respectively formed in top portions of the Si pillars H1, H4, H5, and H6, and P+regions49band49eare respectively formed in top portions of the Si pillars H3and H2by an ion implantation method using, as an ion implantation stopper layer, the SiO2layers42a,42b,42c,35a,35b, and35c, the TiN layers32a,32b, and32i, and the gate SiO2layers34a,34b, and34c.

Subsequently, as shown in FIGS.2V(a),2V(b) and2V(c), a SiO2layer50is formed over the entire surface by a CVD method. A contact hole51ais formed on the N+region49adisposed in the top portion of the Si pillar H5. A contact hole51bis formed on the lower TiN layer32f(above which the conductor layer47bis formed) connected to an outer peripheral portion of the Si pillar H3. Subsequently, a contact hole51cis formed on the P+region49bdisposed in the top portion of the Si pillar H3. A contact hole51dis formed on the conductor layer45b. A contact hole51eis formed on the N+region49cdisposed in the top portion of the Si pillar H4. Subsequently, a contact hole51fis formed on the N+region49ddisposed in the top portion of the Si pillar H1. A contact hole51gis formed on the conductor layer45c. A contact hole51his formed on the P+region49edisposed in the top portion of the Si pillar H2. Subsequently, a contact hole51iis formed on the lower TiN layer32g(above which the conductor layer47cis formed). A contact hole51jis formed on the N+region49fdisposed in the top portion of the Si pillar H6.

Subsequently, a bit line wiring metal layer BLa that is connected to the N+region49adisposed in the top portion of the Si pillar H5through the contact hole51ais formed. An inversion bit line wiring metal layer BLBa that is connected to the N+region49ddisposed in the top portion of the Si pillar H1through the contact hole51fis formed. Subsequently, a metal wiring layer52athat connects the lower TiN layer32fof the Si pillar H3, the conductor layer47b, and the conductor layer45cthrough the contact holes51band51gis formed. A power supply line metal wiring layer Vdd that connects the P+region49bdisposed in the top portions of the Si pillar H3to the P+region49edisposed in the top portion of the Si pillar H2through the contact holes51cand51his formed. A metal wiring layer52bthat connects the lower TiN layer32gof the Si pillar H2, the conductor layer47c, and the conductor layer45bthrough the contact holes51dand51iis formed. Subsequently, a bit line wiring metal layer BLb that is connected to the N+region49cdisposed in the top portion of the Si pillar H4through the contact hole51eis formed. An inversion bit line wiring metal layer BLBb that is connected to the N+region49fdisposed in the top portion of the Si pillar H6through the contact hole51jis formed.

Subsequently, as shown in FIGS.2W(a),2W(b) and2W(c), a SiO2layer53is formed by a CVD method. Contact holes54aand54bare formed on the conductor layers47aand47d, respectively. A word line wiring metal layer WL that connects the conductor layer47ato the conductor layer47dthrough the contact holes54aand54bis formed.

As shown in FIG.2W(b), when a thickness of each of the N+region26a, the P+region26b, and the N+region26cthat are respectively formed under the channel i-layers27a,27b, and27cis represented by Lb, a thickness of each of the N+region49a, the P+region49b, and the N+region49cthat are respectively formed on the channel i-layers27a,27b, and27cis represented by Lt, and a diameter of a horizontal cross section of each of the Si pillars H5, H3, and H4is represented by Dp, each of Lb and Lt is preferably larger than Dp. This is because it is difficult to reduce the size in the horizontal direction of SGTs by using a lithographic technique or other processing techniques, but the processing of SGTs in the vertical direction can be performed more easily than the processing in the horizontal direction. This structure can also apply to the SGTs formed in the Si pillars H1, H2, and H6.

For the purpose of increasing the degree of integration of a circuit, it is assumed that the diameter Dp is decreased by ΔDp so that the size of each of the SGTs formed in upper portions of the Si pillars H5, H3, and H4is reduced. In this case, in order to maintain the number of donor or acceptor impurity atoms contained in the lower impurity regions26a,26b, and26c, the thickness Lb is increased by ΔLb so as to satisfy the following formula.
π(Dp/2)2Lb=π((Dp−ΔDp)/2)2(Lb+ΔLb)  (1)

This formula can be rewritten as follows.
(Lb+ΔLb)/Lb=((Dp−ΔDp)/Dp)−2(2)

Specifically, in the case where the diameter Dp is decreased, a rate of increase in the thickness Lb, that is, (Lb+ΔLb)/Lb is determined so as to be equal to or larger than the negative second power of a rate of decrease in the diameter Dp, that is, (Dp−ΔDp)/Dp. With the reduction in the diameter Dp, the necessary rate of increase in the thickness Lb significantly increases. However, as described above, the processing of SGTs in the vertical direction can be performed more easily than the processing in the horizontal direction, which is limited by a processing technique such as a lithographic technique. Therefore, even such a significant increase does not cause a problem. The above determination can be applied to the thickness Lt of each of the upper impurity regions49a,49b, and49c. Similarly, the determination can be applied to the upper and lower impurity regions of the SGTs formed in the Si pillars H1, H2, and H6.

As described above, the SRAM cell circuit shown in the circuit diagram ofFIG. 1A, the schematic structural view ofFIG. 1B, and the arrangement view of Si pillars ofFIG. 1Cis formed by the production method shown inFIGS. 2A to 2W.

According to the method for producing a semiconductor device according to the first embodiment, as shown in FIGS.2A(a) to2D(c), the N+regions3a,3b,3c,3d,6a,6b,6c, and6dthat are to be formed into sources or drains of SGTs and that are shown inFIG. 1Bare formed in a stacked manner between the i-layer substrate13and the i-layer22before the Si pillars H1to H6are formed. Therefore, it is not necessary that, for example, the regions that are to be formed into source or drain impurity layers of SGTs, the regions being shown in FIGS.2J(a) to2M(c), be formed by diffusing a donor or acceptor impurity after etching of the SiO2layer35, the TiN layers32aand32b, and the gate SiO2layers34a,34b, and34c.

The N+regions25a,25b, and25cin lower portions of the Si pillars H1to H6shown in FIGS.2E(a),2E(b) and2E(c) are formed in a uniform manner by using the N+region15having the same impurity concentration distribution at the same depth, the N+region15being formed by implanting arsenic ions as shown in FIGS.2A(a),2A(b) and2A(c). Similarly, the upper N+regions26aand26cand the P+region26bare respectively formed in a uniform manner by using the N+regions21aand21band the P+region19that have the same impurity concentration distribution at the same depth, the N+regions26aand26cand the P+region26bbeing formed by implanting arsenic ions and boron ions as shown in FIGS.2B(a),2B(b),2B(c),2C(a),2C(b) and2C(c). Consequently, the N+regions25a,25b,25c,26a, and26cand the P+region26bof the Si pillars H1to H6are easily formed inside pillar structures of the Si pillars H1to H6in the vertical direction with a high accuracy.

Second Embodiment

A method for producing a semiconductor device having SGTs according to a second embodiment will now be described with reference to FIGS.3A(a) to3D(c) andFIG. 4(a),4(b) and4(c). In FIGS.2E(a),2E(b),2E(c) of the first embodiment, the Si pillars H1to H6are formed by etching the i-layer22, the N+regions21aand21b, the P+region19, the N+region15, and the i-layer substrate13by, for example, a reactive ion etching (RIE) method using the SiO2layers23a,23b, and23cas an etching mask. As a result of this step, surfaces of the N+regions25a,25b,25c,26a, and26c, which contain a donor impurity in a large amount, and the P+region26b, which contains an acceptor impurity in a large amount, are exposed from the side faces of the Si pillars H1to H6. In the first embodiment, subsequently, as shown in FIGS.2F(a),2F(b) and2F(c), when the SiO2layers29a,29b, and29care formed by a thermal oxidation method, the donor and acceptor impurities are release from the N+regions25a,25b,25c,26a, and26cand the P+region26b, the surfaces of which are exposed to the outside, to the outside and diffuse again into the i-regions24a,24b,24c,27a,27b, and27cthat are formed into channels of SGTs. In this case, characteristics of the SGTs may become insufficient and characteristics of the SGTs may vary. According to a production method described in the present embodiment, these problems can be resolved.

As shown in FIGS.3A(a),3A(b) and3A(c), a SiO2layer14is formed on an i-layer substrate13by, for example, a thermal oxidation method. A resist layer60is formed on the SiO2layer14. Arsenic ions (As+) are introduced from above the i-layer substrate13by ion implantation using the resist layer60as a mask. Thus, N+regions61a,61b,61c,61d,61e, and61fare formed in surface layer portions of the i-layer substrate13.

Subsequently, as shown in FIGS.3B(a),3B(b) and3B(c), the SiO2layer14is removed, and an i-layer16is formed on the N+regions61a,61b,61c,61d,61e, and61fand the i-layer substrate13by, for example, a low-temperature epitaxial growth process. A SiO2layer17is then formed on the i-layer16by, for example, a CVD method. Subsequently, N+regions63a,63b,63c, and63dare formed in the i-layer16so as to be respectively overlapped with the N+regions61a,61c,61d, and61fin the vertical direction by arsenic-ion implantation using a resist layer62as a mask.

Subsequently, as shown in FIGS.3C(a),3C(b) and3C(c), the resist layer62is removed and a new resist layer64is formed. Boron-ion implantation is performed using the resist layer64as a mask. Thus, P+regions65aand65bare formed in the i-layer16so as to be respectively overlapped with the N+regions61band61ein the vertical direction.

Subsequently, as shown in FIGS.3D(a),3D(b) and3D(c), Si pillars H1to H6are formed by the production method shown in FIGS.2D(a),2D(b),2D(c),2E(a),2E(b) and2E(c). In this step, the Si pillars H1to H6are formed such that side faces of the N+regions61a,61b,61c,61d,61e,61f,63a,63b,63c, and63dand the P+regions65aand65bare located inside the Si pillars H1to H6. Subsequently, the production is performed by the method shown in FIGS.2F(a) to2W(c). The donor and acceptor impurities are thermally diffused by heat processing that is performed in the course of the production until the step shown in FIGS.2W(a),2W(b) and2W(c) is performed. Consequently, the N+regions61a,61b,61c,61d,61e,61f,63a,63b,63c, and63dand the P+regions65aand65bare connected to the conductor layers45a,45b,45c, and45d(refer to FIGS.2Q(a),2Q(b) and2Q(c)).

According to the production method of the present embodiment, in a step of oxidizing surfaces of the Si pillars H1to H6and the surface of the i-layer substrate13afrom the state shown in FIGS.3D(a),3D(b) and3D(c), the N+regions61a,61b,61c,61d,61e,61f,63a,63b,63c, and63dand the P+regions65aand65bare not exposed from the side faces of the Si pillars H1to H6. Accordingly, it is possible to prevent the phenomenon that the donor and acceptor impurities are released from the N+regions61a,61b,61c,61d,61e,61f,63a,63b,63c, and63dand the P+regions65aand65bto the outside, and diffused again to the i-regions24a,24b,24c,27a,27b, and27cthat are formed into channels of SGTs. As a result, the problems such as a decrease in characteristics of the SGTs and the generation of variations in characteristics of the SGTs are resolved.

Furthermore, as shown inFIGS. 4(a),4(b) and4(c), the semiconductor device is formed so that the N+regions61a,61b,61c,61d,61e,61f,63a,63b,63c, and63dand the P+regions65aand65bare located inside the Si pillars H1to H6in steps before the structure shown in FIGS.2H(a),2H(b) and2H(c) of the first embodiment is obtained, that is, after the gate SiO2layers34a,34b, and34c, the TiN layer32, and the SiO2layer35are formed on outer peripheral portions of the Si pillars H1to H6. In this case, at least before the gate SiO2layers34a,34b, and34care formed, even though the surfaces of the Si pillars H1to H6are exposed, the N+regions61a,61b,61c,61d,61e,61f,63a,63b,63c, and63dand the P+regions65aand65bare not exposed from the side faces of the Si pillars H1to H6. Thus, it is possible to prevent the donor and acceptor impurities from releasing to the outside.

Third Embodiment

A method for producing a semiconductor device according to a third embodiment will now be described with reference toFIGS. 5(a),5(b) and5(c).

As shown inFIGS. 5(a),5(b) and5(c), an N+region67is formed in a surface layer portion of an i-layer substrate13by arsenic-ion implantation. An i-layer68is formed on the N+region67by, for example, low-temperature Si epitaxial growth. A SiO2layer69is formed on the i-layer68. Subsequently, N+regions70aand70cand a P+region70bare formed in a surface layer portion of the i-layer68by ion implantation of arsenic and boron using the method shown in FIGS.2B(a),2B(b),2B(c),2C(a),2C(b) and2C(c). As a result, an i-layer71in which arsenic ions or boron ions are not implanted is formed in a lower portion of the i-layer68. A difference from the cross-sectional structure in the first embodiment (refer to FIGS.2C(a),2C(b) and2C(c)) is that, at the time when the resist layer20is removed, the i-layer71is present inFIGS. 5(a),5(b) and5(c) whereas a layer corresponding to the i-layer71is not present in FIGS.2C(a),2C(b) and2C(c).

It is desired that each of the N+regions15,21a, and21band the P+region19shown in FIGS.2C(a),2C(b) and2C(c) functions as a source or a drain of an SGT having a low resistance. For this purpose, ion implantation is performed such that the N+regions and the P+region respectively have high arsenic and boron atom concentrations close to the solid-solution limits to Si. In the subsequent heat processing, arsenic and boron are rapidly mixed in a high concentration state at the boundaries between the P+region19and the N+region15, between the P+region19and the N+regions21awhich contacts the N+region15, and between the P+region19and the N+regions21bwhich contacts the N+region15. In this case, crystal defects are easily generated at this boundary portion. When crystal defects are generated in this manner, the crystal defects extend to the i-layers24a,24b,24c,27a,27b, and27cthat are formed into channels of SGTs, which may result in the degradation of characteristics of the SGTs. In contrast, according to the production method of the present embodiment, the i-layer71is present between the N+region67and the upper N+regions70aand70cand P+region70b. Therefore, in heat processing thereafter, interdiffusion between arsenic and boron occurs in low concentrations at an initial stage, and thus the generation of crystal defects described above is suppressed.

Fourth Embodiment

A method for producing a semiconductor device having SGTs according to a fourth embodiment will now be described with reference to FIGS.6A(a),6A(b),6A(c),6B(a),6B(b) and6B(c).

As shown in FIGS.6A(a),6A(b) and6A(c), an N+region67ais formed in a region near a surface layer of an i-layer substrate13by arsenic-ion implantation, and an i-layer71ais formed in a surface layer portion of the i-layer substrate13. The i-layer71ais formed by adjusting an accelerating voltage such that the arsenic impurity distribution in the depth direction of the i-layer substrate13by the arsenic-ion implantation is present in the N+region67a. An i-layer68ais formed on the i-layer71aby, for example, low-temperature Si epitaxial growth. A SiO2layer69ais formed on the i-layer68a. Subsequently, N+regions70aand70cand a P+region70bthat are similar to those shown in FIGS.2B(a),2B(b),2B(c),2C(a),2C(b) and2C(c) are formed in the i-layer68aby ion implantation of arsenic and boron.

The cross-sectional structure of the semiconductor device shown in FIGS.6A(a),6A(b) and6A(c) is the same as that shown inFIGS. 5(a),5(b) and5(c). However, the i-layer71shown inFIGS. 5(a),5(b) and5(c) is formed directly on the N+region67by a low-temperature Si epitaxial growth process, and thus crystal defects are easily generated in the i-layer71. In contrast, in the production method shown in FIGS.6A(a),6A(b) and6a(c), the i-layer68ais formed on the i-layer71a, which does not contain an arsenic impurity in a high concentration, by a low-temperature Si epitaxial growth process. Therefore, the generation of crystal defects in the i-layer68ais suppressed.

Alternatively, as shown in FIGS.6B(a),6B(b) and6B(c), in an i-layer68cformed on an i-layer71aby a Si epitaxial growth process, N+regions70aand70cand a P+region70bare formed in a lower portion of the i-layer68cby ion implantation as in FIGS.6A(a),6A(b) and6A(c) such that an i-layer72remains in a surface layer portion of the i-layer68c. A SiO2layer69ais removed, and an i-layer22is then formed by a low-temperature epitaxial process as shown in FIGS.2D(a),2D(b) and2D(c). Since the i-layer22is formed on the i-layer72, which does not contain a donor or acceptor impurity in a high concentration, by a low-temperature Si epitaxial process, the generation of crystal defects in the i-layer22is suppressed near the boundary with the i-layer72.

Fifth Embodiment

A method for producing a semiconductor device having SGTs according to a fifth embodiment will now be described with reference to FIGS.7A(a),7A(b),7A(c),7B(a),7B(b) and7B(c).

As shown in FIGS.7A(a),7A(b) and7A(c), an N+region73and an i-layer13care continuously formed on an i-layer substrate13bby, for example, a low-temperature Si epitaxial process. Subsequently, an N+region15is formed in a surface layer of the i-layer13c. Subsequently, as shown in FIGS.2D(a),2D(b) and2D(c), N+regions21aand21band a P+region19are formed on the N+region15, and an i-layer22is formed thereon. Thereafter, steps the same as those shown in FIGS.2E(a) to2W(c) are performed without performing the step of forming the N+regions30a,30b,30c, and30dshown in FIGS.2G(a),2G(b) and2G(c).

As a result, as shown in FIGS.7B(a),7B(b) and7B(c), an N+region73ais formed on the i-layer substrate13bso as to extend over lower portions of Si pillars H1to H6. In the production method shown in FIGS.2G(a),2G(b) and2G(c), the N+regions30a,30b,30c, and30dare formed by implanting accelerated arsenic ions from above the i-layer substrate13a. In this case, arsenic ions reflected from a surface of the i-layer substrate13amay be implanted in the i-regions24a,24b,24c,27a,27b, and27cthat are formed into channels of SGTs of the Si pillars H1to H6. Consequently, characteristics of the SGTs formed in the Si pillars H1to H6are degraded. In contrast, since the N+region73is formed before the formation of the Si pillars H1to H6in the production method of the present embodiment, such a degradation of characteristics can be prevented.

Sixth Embodiment

A method for producing a semiconductor device having SGTs according to a sixth embodiment will now be described with reference to FIGS.8A(a),8A(b),8A(c),8B(a),8B(b) and8B(c).

In a method for producing a semiconductor device having SGTs in the related art in which a single SGT is formed in a single Si pillar, a plurality of Si pillars having the same height are formed on a substrate, and a donor or acceptor impurity layer serving as a source or a drain is formed at each of an upper position and a lower position of the respective Si pillars so as to sandwich a channel region. Therefore, in such a semiconductor device having SGTs in the related art in which a single SGT is formed in a single Si pillar, channel lengths of an N-channel SGT and a P-channel SGT that are formed on a substrate are equal to each other unless others steps are added. For this reason, the channel lengths of an N-channel SGT and a P-channel SGT cannot be changed in the circuit design. In contrast, in the present embodiment, since SGTs are formed at an upper position and a lower position of a single Si pillar, the channel lengths of the SGTs disposed at the upper position and the lower position of the single Si pillar can be easily changed on the basis of the design requirement.

As shown in FIGS.8A(a),8A(b) and8A(c), N+regions25a,25b, and25cdisposed in central portions of Si pillars H1to H6are formed at the same time at the same height position, and an N+region26a, a P+region26b, and an N+region26cthat are respectively disposed on the N+regions25a,25b, and25care also formed at the same height position. The heights of the Si pillars H1to H6are each represented by L1. However, by appropriately setting lengths L2, L3, L4, and L5, the channel lengths of SGTs formed at an upper position and a lower position of the Si pillars H1to H6can be changed where L2 represents a length in the vertical direction from a surface of an i-layer substrate13ato the boundary between the N+regions25a,25b, and25c, and the N+regions26aand26cand the P+region26b, L3 represents a length in the vertical direction of the N+regions25a,25b, and25c, L4 represents a length in the vertical direction of the N+regions26aand26cand the P+region26b, and L5 represents a length in the vertical direction of portions where the N+regions49aand49cand the P+region49bthat are to be formed in top portions of the Si pillars H1to H6shown in FIGS.2U(a),2U(b) and2U(c) are to be formed.

As shown in FIGS.8B(a),8B(b) and8B(c), channel lengths Ld and Lu can be controlled to predetermined lengths based on the design requirement by the production method described above where the channel length Ld is determined as a length in the vertical direction of i-regions24a,24b, and24cthat are located between an N+region73adisposed in a lower portion of the Si pillars H1to H6and the N+regions25a,25b, and25c, and the channel length Lu is determined as a length in the vertical direction of i-layers27a,27b, and27cthat are respectively located between the N+region49a, the P+region49b, and the N+region49cdisposed in upper portions of the Si pillars H1to H6and the N4region26a, the P+region26b, and the N+region26c. Unlike an existing planar MOS transistor, in the production method of the present embodiment, an increase in the circuit area due to an increase in a channel width is not generated, and a desired drive capacity of a CMOS transistor can be set on the basis of the design requirement by changing the channel lengths Ld and Lu of SGTs formed at an upper position and a lower position of the Si pillars H1to H6.

In the production method in the related art shown inFIG. 15B, in which a single SGT is formed in a single Si pillar, since the channel lengths of all N-channel and P-channel SGTs become the same, the channel length of an N-channel SGT and the channel length of a P-channel SGT cannot be changed on the basis of the design requirement. In contrast, in the present embodiment, the channel length Ld and the channel length Lu can be easily set to predetermined lengths on the basis of the design requirement.

Seventh Embodiment

A method for producing a semiconductor device having SGTs according to a seventh embodiment will now be described with reference to FIGS.9A to9C(c).

An SRAM cell circuit diagram shown inFIG. 9Ashows an SRAM cell in which the driving N-channel SGTs_N11and N21are not present in the SRAM cell circuit diagram shown inFIG. 1A.

In the present embodiment, as shown in FIGS.9B(a),9B(b) and9B(c), an N+region75is formed in an i-layer substrate13aso as to be located in a bottom portion of a Si pillar H3, and an N+region is not formed in bottom portions of the Si pillars H5and H4. Similarly, an N+region is formed in the i-layer substrate13aso as to be located in a bottom portion of a Si pillar H2, and an N+region is not formed in bottom portions of the Si pillars H1and H6. The TiN layer32f, which is a gate conductor layer extending over a bottom portion of the Si pillars H3and H4in FIGS.2W(a),2W(b) and2W(c), is separated to form an electrically floating TiN layer32jin a lower portion of the Si pillar H4. Similarly, a separated TiN layer32kis formed on the Si pillar H5. For the Si pillars H1, H2, and H6, the separation of the TiN layer is similarly performed. Consequently, a current does not flow in SGTs disposed in the lower portions of the Si pillars H5, H4, H1, and H6, and these SGTs are in an electrically floating state. Thus, the SRAM cell circuit shown in FIGS.9B(a),9B(b) and9B(c) is realized.

Alternatively, as shown in FIGS.9C(a),9C(b) and9C(c), i-layers77a,77b, and77care formed on a SiO2substrate76instead of the i-layer substrate13aused in FIGS.9B(a),9B(b) and9B(c). Si pillars H5, H3, and H4are respectively formed on the i-layers77a,77b, and77c. An N+region is not formed in bottom portions of the Si pillars H5and H4. The TiN layer32f, which is a gate conductor layer extending over a bottom portion of the Si pillars H3and H4, is separated to form an electrically floating TiN layer32jin a lower portion of the Si pillar H4. The Si pillars H1, H2, and H6are formed as in the Si pillars H5, H3, and H4. This method can also realize the SRAM cell circuit shown in FIGS.9B(a),9B(b) and9B(c).

Alternatively, in FIGS.9B(a),9B(b) and9B(c), even in the case where an N+region is formed in bottom portions of the Si pillars H5, H4, H1, and H6, the SGTs may be formed as an enhancement-type SGTs, and the TiN layer32kof the SGTs in the lower portions of the Si pillars H5and H1and the TiN layer32jof the SGTs in the lower portions of the Si pillars H4and H6may be allowed to electrically float or the TiN layers32kand32jmay be connected to a ground metal wiring. The Si pillars H1, H2, and H6are formed as in the Si pillars H5, H3, and H4. With this structure, the same advantage as that in the structure described above can be obtained.

As shown in FIG.9B(b), although an N+region is not formed in the lower portions of the Si pillars H5and H4, the N+region75that is disposed in the bottom portion of the Si pillar H3and is connected through the i-layer substrate13afunctions as an impurity region of a source or a drain. In this case, a current flowing to the i-regions24aand24cwhich are channels is suppressed by the i-layer substrate13ahaving a high resistance. In the case where the SiO2substrate76is included as shown in FIG.9C(b), such a current is not generated and thus it is possible to more efficiently realize a state in which the SGTs in lower portions of the Si pillars H5and H4are not present on the circuit. In FIGS.9C(a),9C(b) and9C(c), even in the case where an N+region is formed in bottom portions of the Si pillars H5and H4, the same advantage as that in the structure described above can be obtained by allowing the N+region to electrically float.

As described above, according to the present embodiment, a semiconductor device can be formed in accordance with the design requirement of the semiconductor device so that SGTs formed in Si pillars are not present on a circuit.

Eighth Embodiment

A method for producing a semiconductor device having SGTs according to an eighth embodiment will now be described with reference toFIGS. 10A and 10B.

FIG. 10Ais a cross-sectional structural view of a semiconductor device after a step corresponding to the step shown in FIGS.2D(a),2D(b) and2D(c) of the first embodiment is performed in the present embodiment. In FIGS.2D(a),2D(b) and2D(c), the single N+region15is formed in a surface layer portion of the i-layer substrate13. In contrast, in the present embodiment, a P+region80and N+regions81aand81bare formed as a layer the same as the N+region15. The P+region80and the N+regions81aand81bare formed by ion implantation of boron (B) and arsenic (As) as in the steps shown in FIGS.2B(a),2B(b),2B(c),2C(a),2C(b) and2C(c). Subsequently, as in the step shown in FIGS.2D(a),2D(b) and2D(c), an N+region21ais formed on the P+region80, a P+region19is formed on the N+region81a, and an N+region21bis formed on the N+region81b, the N+region21a, the P+region19, and the N+region21bbeing disposed in an i-layer16. An i-layer22is then formed on the N+region21a, the P+region19, and the N+region21bby, for example, a low-temperature epitaxial growth process.

FIG. 10Bis a cross-sectional view after the steps corresponding to the steps shown in FIGS.2E(a) to2W(c) of the first embodiment are performed in the present embodiment. In FIGS.2G(a),2G(b) and2G(c), the N+regions30a,30b,30c, and30dare formed in an upper surface of the i-layer substrate13aby implanting arsenic (As) ions. In contrast, in the present embodiment, a P+region82ais formed in an upper surface of an i-layer substrate13aso as to be located in a lower portion of the Si pillar H5, and an N+region82bis formed in an upper portion of the i-layer substrate13aso as to be located in lower portions of the Si pillars H3and H4. Furthermore, an insulating layer85for isolation is formed in an upper portion of the i-layer substrate13a, the upper portion being disposed between the P+region82aand the N+region82b. Consequently, a P-channel SGT that includes the P+region82aand a P+region83aserving as a source and a drain is formed in a lower portion of the Si pillar H5. An N-channel SGT that includes the N+region82band an N+region83bserving as a source and a drain is formed in a lower portion of the Si pillar H3. An N-channel SGT that includes the N+region82band an N+region83cserving as a source and a drain is formed in a lower portion of the Si pillar H4.

As described above, according to the method for producing a semiconductor device according to the present embodiment, an upper SGT and a lower SGT of a single Si pillar can be formed as any of an N-channel SGT and a P-channel SGT in accordance with the design requirement regardless of the presence or absence of an SRAM cell circuit.

Ninth Embodiment

A method for producing a semiconductor device having SGTs according to a ninth embodiment will now be described with reference to the drawings.

InFIG. 10Bof the eighth embodiment, the conductor layer45bis formed so as to extend over the Si pillar H3and the Si pillar H4. In contrast, in the present embodiment, as shown inFIG. 11, a conductor layer84aconnected to an N+region83band a P+region26bof a Si pillar H3and a conductor layer84bconnected to N+regions83cand26cof a Si pillar H10(corresponding to the Si pillar H4inFIG. 10B) are separately formed. The conductor layer84bconnects a TiN layer32eand a TiN layer32i, which are gate conductor layers of SGTs respectively formed in a lower position and an upper position of the Si pillar H10, and is connected to the N+regions83cand26cthat are located in the middle of the Si pillar H10. By allowing the conductor layer84bto electrically float, two SGTs disposed at an upper position and a lower position of a Si pillar can be treated as a sing1eSGT.

Tenth Embodiment

A method for producing a semiconductor device having SGTs according to a tenth embodiment will now be described with reference toFIG. 12.

In the first embodiment, regarding impurity regions included in the SGTs, the thickness of an impurity region formed under a certain channel layer is equal to the thickness of an impurity region formed on the channel layer, and the diameters of these impurity regions are also the same. However, when the sizes of the SGTs are reduced while maintaining this structure, a sufficient PN-junction potential difference may not be obtained. As shown in FIG.2W(b), the thickness of each of the N+region26a, the P+region26b, and the N+region26cthat are respectively formed under the i-regions27a,27b, and27cserving as channel layers is represented by Lb, the thickness of each of the N+region49a, the P+region49b, and the N+region49cthat are respectively formed on the i-regions27a,27b, and27cis represented by Lt, and the diameter of a horizontal cross section of each of the Si pillars H5, H3, and H4is represented by Dp. In this case, for example, when the diameter Dp is reduced to 10 nm or less, even in the case where the thicknesses Lb and Lt are each 20 nm and a donor or acceptor impurity volume density is 1×1020/cm3, which is close to the solid-solution limit to Si, the number of donor or acceptor impurity atoms contained in each of the impurity regions is 10 or less. Accordingly, in this case, it is difficult to obtain a PN-junction potential difference obtained on the basis of the known band theory with respect to the i-regions which are channel layers of corresponding SGTs. Therefore, in the first embodiment, in the case where the diameter of a Si pillar is reduced in order to reduce the size of an SGT, it is necessary to increase the thickness of the upper and lower impurity regions, and furthermore, the height of the Si pillar.

In contrast, in the tenth embodiment, as shown inFIG. 12, a thickness Lt of each of an N+region49a, a P+region49b, and an N+region49cthat are respectively formed on i-regions27a,27b, and27cserving as channel layers is smaller than a thickness Lb of each of an N+region26a, a P+region26b, and an N+region26cthat are respectively formed under the i-regions27a,27b, and27c. In addition, a diameter D of each of the N+region49a, the P+region49b, and the N+region49cis larger than a diameter Dp of each of silicon pillars H5, H3, and H4. The diameter D can be increased by, for example, after the etching step shown in FIGS.2U(a),2U(b), and2U(c), forming an epitaxial Si film containing a donor or acceptor impurity on outer peripheral portions of the N+region49a, the P+region49b, and the N+region49c. With this structure, the concentrations of a donor impurity and an acceptor impurity in the impurity regions provided on and under a channel layer can be balanced. Thus, even in the case where, for the purpose of reducing the size of SGTs, the diameter of each of the Si pillars is reduced and the thickness of the lower impurity region is increased accordingly, the thickness of the upper impurity region can be suppressed and thus the height of the Si pillar need not be increased. The structures of SGTs formed in upper portions of the Si pillars H5, H3, and H4have been described above. However, the structures of the impurity regions can be applied to SGTs formed in the Si pillars H1, H2, and H6.

As described above, according to this embodiment, even when the size of each of the SGTs is reduced, the height of each of the Si pillars can be maintained.

The technical idea according to the first to tenth embodiments of the present invention can be applied to a method for producing another circuit in which an impurity region is formed in the middle of a Si pillar regardless of the presence or absence of an SRAM cell circuit.

In FIGS.2C(a),2C(b) and2C(c), the N+regions21aand21band the P+region19are formed over the entirety of the i-layer16. However, the formation areas of the N+regions21aand21band the P+region19are not particularly limited, regardless of whether or not arsenic or boron ions introduced by ion implantation reach the N+region15formed in a surface layer portion of the i-layer substrate13, as long as the function of a source or a drain of SGTs formed at intermediate positions of the Si pillars H1to H6is not impaired at the final stage of the production of the SGT circuit shown in FIGS.2W(a),2W(b) and2W(c). This also applies to other embodiments according to the present invention.

In FIGS.2C(a),2C(b) and2C(c), the N+regions21aand21band the P+region19are formed by ion implantation. Alternatively, for example, the N+regions21aand21band the P+region19may be formed by forming a hole at a particular position of the SiO2layer17, adsorbing boron or arsenic atoms onto the i-layer16, and then performing heat treatment. In this method, the N+regions21aand21band the P+region19that contain boron or arsenic impurity atoms in high concentrations can be stably formed. Alternatively, the N+regions21aand21band the P+region19may be formed by using a multilayer laminated film obtained by using this adsorption of boron or arsenic atoms and the formation of a Si layer by, for example, an ALD method. In this method, the N+regions21aand21band the P+region19that contain impurity atoms in high concentrations can be more stably formed. This method also applies to the case where the N+region15is formed and other embodiments according to the present invention.

In the above embodiments, the number of donor or acceptor impurity atoms contained in impurity regions included in SGTs can be determined by design values of a source resistance, a drain resistance, a leak current, and the like.

In the first embodiment, a description has been made of a case where, as shown in FIG.2W(b), in the SGTs formed in upper portions of the Si pillars H5, H3, and H4, the thicknesses of the N+region49a, the P+region49b, and the N+region49cthat are respectively formed on the i-regions27a,27b, and27cserving as channel layers are the same value of Lt, and the thicknesses of the N+region26a, the P+region26b, and the N+region26cthat are respectively formed under the i-regions27a,27b, and27care the same value of Lb. Alternatively, these thicknesses may be varied on the basis of the difference in a thermal diffusion coefficient of the donor or acceptor impurity used in the impurity regions. This structure can be applied to the SGTs formed in lower portions of the Si pillars H5, H3, and H4and SGTs formed in the Si pillars H1, H2, and H6. This structure can also be applied to other embodiments according to the present invention.

The i-layer71inFIGS. 5(a),5(b) and5(c), the i-layer71ain FIGS.6A(a),6A(b) and6A(c), and the i-layer72in FIGS.6B(a),6B(b) and6B(c) are intrinsic semiconductor layers that do not contain a donor or acceptor impurity. However, the i-layers71,71a, and72may be layers that contain a donor or acceptor impurity as long as advantages provided by the present invention are obtained. This also applies to other embodiments according to the present invention

The N+region15in FIGS.2A(a),2A(b) and2A(c) may be formed on the i-layer substrate13by epitaxial growth of Si containing a donor impurity.

In FIGS.2C(a),2C(b),2C(c),2D(a),2D(b) and2D(c), the i-layers16and22are formed by, for example, a low-temperature epitaxial growth process. Alternatively, the i-layers16and22may be formed by another method such as an atomic layer deposition (ALD) method. This also applies to other embodiments according to the present invention.

In FIGS.2A(a),2A(b) and2A(c), the N+region15is formed by ion implantation. In the case where a single N+region15is formed over an entire surface, the N+region15may be formed by depositing a Si layer of the same conductivity type using epitaxial growth, ALD, or the like. Similarly, in the step shown in FIGS.2C(a),2C(b) and2C(c), in the case where the N+regions21aand21b, and the P+region19have the same conductivity type, these regions may each be formed by depositing a Si layer of the same conductivity type using epitaxial growth, an ALD method, or the like.

In FIGS.2G(a),2G(b) and2G(c), the N+regions30a,30b,30c, and30dare formed in a surface layer portion of the i-layer substrate13abetween the Si pillars H1to H6by implanting arsenic ions from an upper surface of the i-layer substrate13a. Alternatively, for example, after the step shown in FIGS.2K(a),2K(b) and2K(c) is finished, the N+regions30a,30b,30c, and30dmay be formed in a surface layer portion of the i-layer substrate13a. In this case, the N+regions30a,30b,30c, and30d, each of which is formed into a source or a drain of an SGT, can be formed at bottom portions of the Si pillars.

An impurity atom such as Ge may be incorporated in the N+regions15,21aand21b, and the P+region19to control internal stress of the N+regions15,21aand21b, and the P+region19. As a result, the mobility of SGTs that are formed in the Si pillars H1to H6is improved.

In FIGS.2H(a),2H(b), and2H(c), a description has been made of a case where TiN is used as an example of the gate conductor layer. Alternatively, the gate conductor layer may be another metal layer. Alternatively, the gate conductor layer may be constituted by a multilayer structure including the metal layer and a poly-Si layer, for example. This also applies to other embodiments according to the present invention.

In the above embodiments, a silicon-on-insulator (SOI) substrate may be used instead of each of the i-layer substrates13,13a, and13b.

In FIGS.9B(a),9B(b),9B(c),9C(a),9C(b) and9C(c), a description has been made of a case where SGTs that are not present on a circuit are provided in lower portions of the Si pillars H5, H4, H1, and H6. Alternatively, in another circuit, gate conductor layers of upper SGTs may be allowed to electrically float and source or drain impurity regions in top portions of Si pillars may be allowed to electrically float. Also in such a case, a semiconductor device can be produced in accordance with the design requirement so that the SGTs are not present on a circuit.

In the case where the thickness of each of the N+region26a, the P+region26b, and the N+region26cis represented by Lb, the thickness of each of the N+region49a, the P+region49b, and the N+region49cis represented by Lt, and the diameter of a horizontal cross section of each of the Si pillars H5, H3, and H4is represented by Dp, the semiconductor device may be formed so that, among four relationships described below, two, three, or four relationships are satisfied at the same time. Specifically, the first relationship is the relationship in which each of the thicknesses of Lb and Lt is made larger than the diameter Dp, which has been described in the first embodiment with reference to FIG.2W(b). The second relationship is the relationship in which the thickness Lb is made larger than the thickness Lt. The third relationship is the relationship in which, when the diameter Dp is decreased, the rate of increase in the thickness Lb is determined so as to be equal to or larger than the negative second power of the rate of decrease in the diameter Dp. The fourth relationship is the relationship in which the diameter D of a horizontal cross section of each of the N+region49a, the P+region49b, and the N+region49cis made larger than the diameter Dp, which has been described in the tenth embodiment with reference toFIG. 12. This can also apply to other embodiments according to the present invention.

The second embodiment that has been described with reference toFIGS. 3A to 3DandFIG. 4can be similarly applied to other embodiments according to the present invention.

In the above embodiments, two SGTs are formed in a single Si pillar. In the case where more than two SGTs are formed in a single Si pillar, it is sufficient that a similar production method is added. Thus, the technical idea of the present invention can be applied. In such a case, SGTs are further formed in the top portions of the Si pillars H1to H6.

The technical idea of the present invention is also applicable to a case where an impurity region of a lower layer and an impurity region of an upper layer in a Si pillar are impurity regions having the same conductivity.

In FIGS.2A(a) to2W(c), the i-layer substrate13and other layers are formed of Si layers. Also in the case where layers composed of other semiconductor materials are included, the present invention can be applied. This also applies to other embodiments of the present invention.

It is to be understood that various embodiments and modifications of the present invention can be made without departing from the broad spirit and the scope of the present invention. The embodiments described above are illustrative Examples of the present invention and do not limit the scope of the present invention. Any combination of the Examples and modifications can be made. Furthermore, even when part of the configuration of the above embodiments is removed as required, the embodiments are within the technical idea of the present invention.

According to the method for producing a semiconductor device according to the present invention, a semiconductor device having SGTs and having a high degree of integration can be realized.