Reducing external resistance of a multi-gate device using spacer processing techniques

A method includes depositing a sacrificial gate electrode to one or more multi-gate fins. The sacrificial gate electrode is patterned such that it is coupled to a gate region and substantially no sacrificial gate electrode is coupled to source and drain regions. A dielectric film is formed that is coupled to the source and drain regions. The sacrificial gate electrode is removed and a spacer gate dielectric is deposited to the gate region wherein substantially no spacer gate dielectric is deposited to the source and drain regions. The spacer gate dielectric is etched to completely remove the spacer gate dielectric from the gate region area that is to be coupled with a final gate electrode except a remaining pre-determined thickness of spacer gate dielectric that is to be coupled with the final gate electrode that remains coupled with the dielectric film.

BACKGROUND

Generally, multi-gate devices or non-planar transistors such as tri-gate devices are emerging as a viable option to support future technology scaling.

It will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, if considered appropriate, reference numerals have been repeated among the figures to indicate corresponding and/or analogous elements.

DETAILED DESCRIPTION

Embodiments of reducing external resistance of a multi-gate device using spacer processing techniques are described herein. In the following description, numerous specific details are set forth to provide a thorough understanding of embodiments disclosed herein. One skilled in the relevant art will recognize, however, that the embodiments disclosed herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the specification.

FIG. 1is a process schematic for reducing external resistance of a multi-gate device using spacer processing techniques, according to but one embodiment.FIGS. 1a-dandFIGS. 1i-jinclude top-down representations whileFIGS. 1e-hinclude cross-section representations. Although the depictions are represented sequentially (i.e. a through j), other sequences may be readily apparent and/or may fall within the spirit and scope of this description. In other words, the description is not limited to the particular sequence depicted inFIG. 1.

Multi-gate transistors or non-planar devices100, such as tri-gate devices, may emerge as an option to support future technology scaling of transistor devices. However, drive current in multi-gate devices may be severely hindered by parasitic resistance. The parasitic resistance may result from difficulty in forming low interfacial resistance between epitaxial growth (epi-growth) and fin104surfaces (i.e.—sidewalls). For example, sidewall spacer dielectric may block epi-growth along the sides of the fin104. This may result in forming a low resistance contact only on a portion of the fin104that is not impeded by the spacer dielectric, for example. Such effect may bottleneck the flow of current into the fin104, resulting in a degradation of external resistance (Rext) of the multi-gate transistor.

In an embodiment according toFIG. 1a, an apparatus100includes shallow-trench isolation (STI) material102, one or more multi-gate fins104, and sacrificial gate electrode106, each coupled as shown. The one or more multi-gate fins104may be referred to as diffusion according to an embodiment and may include doped silicon. Fin104may include a source region, a drain region, and a gate region, the gate region being disposed between the source and drain regions. The visible portion of fin104inFIG. 1amay include a source region and a drain region. The portion of fin104covered by the sacrificial gate electrode106may include a gate region (i.e.—the portion of fin104visible inFIG. 1c). In an embodiment, one or more multi-gate fins104are coupled with an underlying semiconductor substrate (not shown). The STI material102may be deposited to the semiconductor substrate.FIG. 1amay depict a tri-gate fin after conventional trench etch and STI isolation processes.

In an embodiment, a sacrificial gate electrode106is deposited to the one or more multi-gate fins104and patterned such that the sacrificial gate electrode106material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins104. The dimensions of the sacrificial gate electrode106may be selected or pre-determined according to several factors. In an embodiment, the thickness, g, of the sacrificial gate electrode106in the direction of the one or more multi-gate fins104is equal to or about equal to the following, where f is a pre-determined final gate electrode critical dimension (CD) (seeFIG. 1j) and where s is a pre-determined spacer gate dielectric thickness (seeFIG. 1i)
g=f+2s(1)

The spacer gate dielectric thickness, s, may be accounted for twice to provide for the spacer gate dielectric110that is to be coupled to the source side of the final gate electrode112and for the spacer gate dielectric110that is to be coupled to the drain side of the final gate electrode112. A spacer gate dielectric thickness may be pre-determined according to size constraints of a multi-gate device, desired dielectric properties, and/or the size of other associated elements such as the final gate electrode112, or the one or more multi-gate fins104, for example. A final gate electrode CD may be pre-determined according to a variety of factors including size constraints of a multi-gate device, or other desired properties of a multi-gate device such as switching speed, among other factors.

In another embodiment, the height of the sacrificial gate electrode106is selected such that the height, h2, of the remaining spacer gate dielectric110(seeFIG. 1f) after etching the spacer gate dielectric110is equal to or about equal to a pre-determined height of the final gate electrode112. For example, the height of the final gate electrode112may be pre-determined according to design size constraints and/or desired properties in a multi-gate device. In a top down view such as inFIG. 1a, the height of the sacrificial gate electrode106may be in the direction coming out of the page. In an embodiment, the height of the sacrificial gate electrode106determines the height of the spacer gate dielectric110.

Etching the spacer gate dielectric110may reduce the height of the spacer gate dielectric110(seeFIGS. 1e-f). Prior to the etching, the spacer gate dielectric110height, h1, may be greater than after the etching (h1>h2). The final gate electrode112height may be determined by the spacer gate dielectric110height, h2, if the final gate electrode112is deposited and/or polished to match the spacer gate dielectric110height, h2, after etching. In an embodiment, the height of the sacrificial gate electrode106is selected to comprehend these downstream effects. In an embodiment, a sacrificial gate electrode106is geometrically upsized in relation to a final gate electrode112.

A sacrificial gate electrode106may include a variety of materials such as polysilicon, metal, or any other suitable gate electrode temporary placeholder for the purposes of defining a region where a final gate electrode112and/or spacer gate dielectric110are to be formed. In an embodiment, the final gate electrode112is a second sacrificial gate electrode to be replaced by another gate electrode material in subsequent process steps. In another embodiment, the final gate electrode112is incorporated in a finished multi-gate device. In other embodiments, a final gate stack includes a high-k dielectric (not shown) coupled with the fin104and a metal gate electrode112coupled with the high-k dielectric.

Other forms of processing may be performed on the structure ofFIG. 1a. For example, a tip implantation may be performed on the gate structure ofFIG. 1ain an embodiment. Tip implantation may include implanting the interface between the fin104and the sacrificial electrode106according to one embodiment. Implant may include p-type or n-type dopant.

In an embodiment according toFIG. 1b, an apparatus100includes a sacrificial gate electrode106coupled with a dielectric film108, each coupled as shown.FIG. 1bmay be a depiction ofFIG. 1aafter a dielectric film108has been deposited and polished. In an embodiment, dielectric film108includes oxide materials such as silicon oxide for example. In other embodiments, dielectric film108includes any suitable sacrificial material upon which spacer gate dielectric110material may be deposited and/or patterned. In an embodiment, a dielectric film108is deposited or formed such that it is coupled to the source and drain regions of the one or more multi-gate fins104. Dielectric film108may be polished or planarized back to the level of a sacrificial gate electrode106.

In an embodiment according toFIG. 1c, an apparatus100includes STI material102, one or more multi-gate fins104, and dielectric film108, each coupled as shown.FIG. 1cmay be a depiction ofFIG. 1bafter the sacrificial gate electrode106has been removed or lifted out. In an embodiment, sacrificial gate electrode106is removed by etching that exposes the underlying gate region of the one or more multi-gate fins104.

In an embodiment according toFIG. 1d, an apparatus100includes STI material102, one or more multi-gate fins104, dielectric film108, and spacer gate dielectric110, each coupled as shown.FIG. 1dmay be a depiction ofFIG. 1cafter deposition and etching of spacer gate dielectric110.

Spacer gate dielectric110may be deposited to the gate region of one or more multi-gate fins104. The source and drain regions of the one or more multi-gate fins104may be protected from spacer110deposition by the dielectric film108that covers these regions. In an embodiment, spacer110deposition includes conformal growth of a nitride material such as silicon nitride on at least the exposed surfaces within the area exposed after the removal of the sacrificial gate electrode106. In an embodiment, the spacer gate dielectric110is conformally grown along the dielectric film108in contrast to a conventional process where spacer110is conformally grown along the gate electrode112.

A first etch may remove the spacer110from the STI surface102and from the top (visible from top-down view inFIG. 1d) of the multi-gate fin104, according to but one embodiment. A second etch, or over-etch process may completely remove the spacer gate dielectric110from the gate region area104to be coupled with a final gate electrode112, except a remaining pre-determined thickness, s, of spacer gate dielectric110(i.e.—the two spacer films110visible inFIG. 1d) to be coupled with the final gate electrode112. After over-etch, the spacer gate dielectric110that remains as depicted inFIG. 1dis coupled to the dielectric film108. In another embodiment, the remaining spacer110is coupled to the one or more multi-gate fins104at an interface region between the source region and the gate region and at an interface region between the drain region and the gate region of the one or more multi-gate fins104.

In an embodiment, a multi-gate fin104includes a tri-gate fin having a top surface, a first sidewall surface, and a second sidewall surface where the deposited spacer110is etched to the extent that it removes substantially all of the spacer110from the top surface, the first sidewall surface, and the second sidewall surface of the gate region area that is to be directly coupled to the final gate electrode112. In other words, spacer110material is substantially or completely removed from the area of fin104including the top and sidewalls of fin104that are to be in direct contact with the final gate electrode112material.

According to an embodiment, no spacer gate dielectric110is deposited to the source and drain regions of the one or more multi-gate fins104at any time during a gate formation process. A gate formation process may include at least the processes described in this specification. The spacer-free source and drain regions104may enable lower interfacial resistance between a semiconductor material epitaxially grown (epi-growth) on the top and sidewall surfaces of the source and drain regions104. For example, spacer110material does not block the epi-growth in these regions, reducing the Rextand improving the drive current of a multi-gate device incorporating such techniques.

In an embodiment according toFIG. 1e, an apparatus100includes one or more multi-gate fins104, dielectric film108, and spacer gate dielectric110, each coupled as shown.FIG. 1emay be a cross-section depiction ofFIG. 1dalong line x, at the intersection of line x and line y. In an embodiment, a spacer gate dielectric110has a height, h1, prior to over-etching. In an embodiment according toFIG. 1f, which may be a depiction ofFIG. 1eafter over-etching, the spacer gate dielectric110height, h2, has been reduced in comparison to h1as a result of etching. In an embodiment,FIGS. 1e-fdepict spacer gate dielectric110conformally grown along a dielectric film108.

In an embodiment according toFIG. 1g, an apparatus100includes a multi-gate fin104and spacer gate dielectric110, each coupled as shown.FIG. 1gmay be a cross-section depiction ofFIG. 1dalong line y at the intersection of line x and line y. In an embodiment, a multi-gate fin104has spacer gate dielectric110coupled to the sidewalls prior to an over-etch process that removes the spacer gate dielectric from the sidewalls, as depicted inFIG. 1h. In an embodiment according toFIG. 1h, spacer gate dielectric is removed or substantially removed from the multi-gate fin104sidewalls in the gate region.

In an embodiment,FIG. 1gdepicts a tri-gate fin104having spacer110coupled to a first sidewall and to a second sidewall, wherein the top surface of the tri-gate fin104is not coupled directly to spacer110. The lack of spacer on the top surface may be due to an etch process that is selective to removing spacer from surfaces along the same plane as the top surface of tri-gate fin104.FIG. 1hmay depict a tri-gate fin after over-etch removes spacer110from the sidewalls in the gate region at the intersection of lines x and y ofFIG. 1d.

In an embodiment according toFIG. 1i, an apparatus100includes dielectric film108, spacer gate dielectric110, and final gate electrode112, each coupled as shown.FIG. 1imay be a depiction ofFIG. 1dafter deposition of a final gate electrode112and planarization of the final gate electrode. The spacer gate dielectric110may have a thickness, s, which may be a pre-determined thickness as already described. In an embodiment, final gate electrode112is grown to a height about equal to the height, h2, of the spacer110. In an embodiment, the final gate electrode112is planarized back to reach a desired final gate electrode height.

In an embodiment according toFIG. 1j, an apparatus100includes STI material102, one or more multi-gate fins104, spacer gate dielectric110, and final gate electrode112, each coupled as shown.FIG. 1jmay be a depiction ofFIG. 1iafter oxide108has been removed. In an embodiment, an etching process removes oxide108. A conventional replacement metal gate process flow may be used to further process apparatus100.

In an embodiment, an apparatus100includes a semiconductor substrate, at least one multi-gate fin104coupled with the semiconductor substrate, the multi-gate fin including a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions. In an embodiment, an apparatus100further includes epitaxially grown semiconductor material (epi-growth) coupled to the source and drain regions of the multi-gate fin104(i.e.—the visible portions of multi-gate fin104inFIG. 1j). In an embodiment, lack of spacer110on the source and drain regions enables lower interfacial resistance between the epi-growth and the multi-gate fin104. A gate electrode112may be further coupled with the gate region of the multi-gate fin104, where a spacer gate dielectric110is coupled to the gate electrode112such that substantially no spacer gate dielectric110is disposed between the gate electrode112and the one or more multi-gate fins104in the gate region. In an embodiment, the semiconductor substrate includes silicon, the multi-gate fin104includes silicon, the gate electrode includes polysilicon, and the spacer gate dielectric includes a nitride material.

In an embodiment, an apparatus100is a non-planar trigate transistor including one or more multi-gate fins104that utilizes a spacer patterning process as described herein. Such apparatus100may be processed such that sacrificial gate electrode106patterning is geometrically upsized to allow for inclusion of spacer110along the final gate electrode112. In an embodiment, the sacrificial gate electrode106is sufficiently tall to allow for spacer110over-etch to remove spacer110material from along the sidewalls of the fin104in the gate-defined region. An apparatus100may include spacer110that grows conformally along a deposited material108such as oxide, for example, rather than a gate electrode material112such as polysilicon or metal, for example. In an embodiment, an apparatus100includes sidewalls along the fin104that never encounter spacer deposition in the contact area (i.e.—source and drain regions). Such apparatus100may demonstrate significantly reduced Rextdue to improved epi-growth to fin104resistance on the sidewalls of the fin104, resulting from no spacer110along the fin104sidewall in the contact area.

In an embodiment, an apparatus100includes a multi-gate fin104having a top surface, a first sidewall surface, and a second sidewall surface wherein the source and drain regions have epi-growth on the top surface, the first sidewall surface, and the second sidewall surface. Coupling epi-growth to the fin104surfaces in the source and drain region may reduce Rextin a multi-gate transistor device. In an embodiment, epi-growth is epitaxially deposited to substantially the entire top, first sidewall, and second sidewall surfaces in the source and drain regions. In another embodiment, the first sidewall surface, and the second sidewall surface of the source and drain regions are substantially free of the spacer gate dielectric110material. In yet another embodiment, the source and drain regions of the multi-gate fin104are not coupled directly to the spacer gate dielectric110material at any time during the spacer gate dielectric110formation process.

FIG. 2is a flow diagram of a method for reducing external resistance of a multi-gate device using spacer processing techniques, according to but one embodiment. In an embodiment, a method200includes preparing one or more multi-gate fins for gate spacer dielectric formation at box202, depositing and patterning a first sacrificial gate electrode to the gate region of the one or more multi-gate fins using particular geometries at box204, performing tip implantation near the gate region of the one or more multi-gate fins at box206, depositing a dielectric film to the source and drain regions of the one or more multi-gate fins at box208, removing the first sacrificial gate electrode material at box210, depositing gate spacer dielectric to the gate region of one or more multi-gate fins at box212, etching to remove gate spacer dielectric completely from the multi-gate fin surfaces in the gate region to be coupled with a second gate electrode at box214, depositing a second gate electrode to the gate region of the one or more multi-gate fins at box216, and removing the dielectric film leaving the gate spacer dielectric coupled with the second gate electrode at box218, where arrows provide but one suggested flow.

In an embodiment, a method includes depositing a sacrificial gate electrode to one or more multi-gate fins204, the one or more multi-gate fins including a gate region, a source region, and a drain region, the gate region being disposed between the source and drain regions, and patterning the sacrificial gate electrode such that the gate electrode material is coupled to the gate region and substantially no sacrificial gate electrode is coupled to the source and drain regions of the one or more multi-gate fins204. In another embodiment, a method200further includes forming a dielectric film coupled to the source and drain regions of the one or more multi-gate fins208and removing the sacrificial gate electrode from the gate region of the one or more multi-gate fins210.

A method200may further include depositing spacer gate dielectric to the gate region of the one or more multi-gate fins212where substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins, the source and drain regions being protected by the dielectric film. In an embodiment, a method200further includes etching the spacer gate dielectric to completely remove the spacer gate dielectric from the gate region area to be coupled with a final gate electrode214, except a remaining pre-determined thickness of spacer gate dielectric to be coupled with the final gate electrode that remains coupled with the dielectric film. The remaining spacer gate dielectric may be the spacer gate dielectric110ofFIG. 1j. The gate region area to be coupled with a final gate electrode may be the region of multi-gate fin104coupled to gate electrode112inFIG. 1j.

In an embodiment, the one or more multi-gate fins include at least one tri-gate fin having a top surface, a first sidewall surface, and a second sidewall surface where etching the spacer gate dielectric214substantially or completely removes the spacer gate dielectric from the top surface, the first sidewall surface, and the second sidewall surface of the gate region area to be coupled with the final gate electrode.

In an embodiment, patterning the sacrificial gate electrode204results in a thickness, g, of the sacrificial gate electrode in the direction of the one or more multi-gate fins that comports with the relationship described in equation (1). In another embodiment, the height of the sacrificial gate electrode is selected during patterning204such that a height of the remaining spacer gate dielectric after etching the spacer gate dielectric214is equal to or about equal to a pre-determined height of the final gate electrode, wherein etching the spacer gate dielectric214reduces the height of the remaining spacer gate dielectric. Forming a dielectric film208may include depositing an oxide material to the sacrificial gate electrode and the source and drain regions of the one or more multi-gate fins, and polishing the oxide material back to the level of the sacrificial gate electrode.

Depositing spacer gate dielectric212to the gate region of the one or more multi-gate fins includes conformally growing a nitride material onto the deposited dielectric film while not conformally growing spacer gate dielectric onto a gate electrode material. In another embodiment, substantially no spacer gate dielectric is deposited to the source and drain regions of the one or more multi-gate fins at any time during a gate formation process.

In other embodiments, a method200includes performing tip implantation206prior to forming a dielectric film208, depositing the final gate electrode to the gate region of the one or more multi-gate fins216such that the final gate electrode is coupled to the pre-determined thickness of spacer gate dielectric that remains after etching the spacer gate dielectric, and removing the dielectric film218such that the pre-determined thickness of spacer gate dielectric remains coupled to the deposited final gate electrode. A method200may include epitaxially depositing a semiconductor material (i.e.—epi or epigrowth) to a top surface, a first sidewall surface and a second sidewall surface of the source and drain regions of one or more multi-gate fins to reduce Rextin a multi-gate transistor device.

FIG. 3is a diagram of an example system in which embodiments of the present invention may be used, according to but one embodiment. System300is intended to represent a range of electronic systems (either wired or wireless) including, for example, desktop computer systems, laptop computer systems, personal computers (PC), wireless telephones, personal digital assistants (PDA) including cellular-enabled PDAs, set top boxes, pocket PCs, tablet PCs, DVD players, or servers, but is not limited to these examples and may include other electronic systems. Alternative electronic systems may include more, fewer and/or different components.

In one embodiment, electronic system300includes an apparatus made using spacer processing techniques100in accordance with embodiments described with respect toFIGS. 1-2. In an embodiment, an apparatus made using spacer processing techniques100as described herein is part of an electronic system's processor310or memory320.

Electronic system300may include bus305or other communication device to communicate information, and processor310coupled to bus305that may process information. While electronic system300may be illustrated with a single processor, system300may include multiple processors and/or co-processors. In an embodiment, processor310includes an apparatus made using spacer processing techniques100in accordance with embodiments described herein. System300may also include random access memory (RAM) or other storage device320(may be referred to as memory), coupled to bus305and may store information and instructions that may be executed by processor310.

Memory320may also be used to store temporary variables or other intermediate information during execution of instructions by processor310. Memory320is a flash memory device in one embodiment. In another embodiment, memory320includes an apparatus made using spacer processing techniques100as described herein.

System300may also include read only memory (ROM) and/or other static storage device330coupled to bus305that may store static information and instructions for processor310. Data storage device340may be coupled to bus305to store information and instructions. Data storage device340such as a magnetic disk or optical disc and corresponding drive may be coupled with electronic system300.

Electronic system300may also be coupled via bus305to display device350, such as a cathode ray tube (CRT) or liquid crystal display (LCD), to display information to a user. Alphanumeric input device360, including alphanumeric and other keys, may be coupled to bus305to communicate information and command selections to processor310. Another type of user input device is cursor control370, such as a mouse, a trackball, or cursor direction keys to communicate information and command selections to processor310and to control cursor movement on display350.

Electronic system300further may include one or more network interfaces380to provide access to network, such as a local area network. Network interface380may include, for example, a wireless network interface having antenna385, which may represent one or more antennae. Network interface380may also include, for example, a wired network interface to communicate with remote devices via network cable387, which may be, for example, an Ethernet cable, a coaxial cable, a fiber optic cable, a serial cable, or a parallel cable.

In one embodiment, network interface380may provide access to a local area network, for example, by conforming to an Institute of Electrical and Electronics Engineers (IEEE) standard such as IEEE 802.11b and/or IEEE 802.11g standards, and/or the wireless network interface may provide access to a personal area network, for example, by conforming to Bluetooth standards. Other wireless network interfaces and/or protocols can also be supported.

IEEE 802.11b corresponds to IEEE Std. 802.11b-1999 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications: Higher-Speed Physical Layer Extension in the 2.4 GHz Band,” approved Sep. 16, 1999 as well as related documents. IEEE 802.11g corresponds to IEEE Std. 802.11g-2003 entitled “Local and Metropolitan Area Networks, Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications, Amendment 4: Further Higher Rate Extension in the 2.4 GHz Band,” approved Jun. 27, 2003 as well as related documents. Bluetooth protocols are described in “Specification of the Bluetooth System: Core, Version 1.1,” published Feb. 22, 2001 by the Bluetooth Special Interest Group, Inc. Previous or subsequent versions of the Bluetooth standard may also be supported.

In addition to, or instead of, communication via wireless LAN standards, network interface(s)380may provide wireless communications using, for example, Time Division, Multiple Access (TDMA) protocols, Global System for Mobile Communications (GSM) protocols, Code Division, Multiple Access (CDMA) protocols, and/or any other type of wireless communications protocol.

In an embodiment, a system300includes one or more omnidirectional antennae385, which may refer to an antenna that is at least partially omnidirectional and/or substantially omnidirectional, and a processor310coupled to communicate via the antennae.

The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit to the precise forms disclosed. While specific embodiments and examples are described herein for illustrative purposes, various equivalent modifications are possible within the scope of this description, as those skilled in the relevant art will recognize.

These modifications can be made in light of the above detailed description. The terms used in the following claims should not be construed to limit the scope to the specific embodiments disclosed in the specification and the claims. Rather, the scope of the embodiments disclosed herein is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.