A digital-to-analog converter and method for transforming a digital value into an analog signal are disclosed. The digital-to-analog converter has a voltage generator, a voltage selector, a multiplexer and a switch array. The voltage generator provides a first and second group of voltages. The voltage selector selectively outputs the first or second group of voltages according to a polarity signal. The multiplexer selectively outputs the digital value or a complementary value of the digital value according to the polarity signal. The switch array outputs one of the voltages received from the voltage selector according to the value output from the multiplexer.

BACKGROUND

1. Field of Invention

The present invention relates to a source driver. More particularly, the present invention relates to a digital-to-analog converter of a source driver.

2. Description of Related Art

FIG. 1shows a function block of a digital-to-analog converter (DAC) of a LCD source driver. Output voltage Vout is selected with a switch array108from gamma voltages Vr0˜Vr2−1nfrom a corresponding decoder input which is controlled by digital codes A0˜An−1. Here, An−1is chosen as Most Significant Bit (MSB) and A0is chosen as Least Significant Bit (LSB).

For a conventional line-inversion LCD, the switch array108as illustrated inFIG. 2requires two full sets of columns118and128, which have different transistor types for the two groups of gamma voltages provided in response to different polarities while the line-inversion LCD displaying, respectively, one set of the columns118having P-type Metal-Oxide-Semiconductor (PMOS) transistors and the other set of the columns128having N-type Metal-Oxide-Semiconductor (NMOS) transistors, and therefore this architecture occupies large area of the source driver chip.

SUMMARY

According to one embodiment of the present invention, a digital-to-analog converter for transforming a digital value into an analog signal is disclosed. The digital-to-analog converter comprises a voltage generator, a voltage selector, a multiplexer and a switch array. The voltage generator provides a first and second group of voltages. The voltage selector selectively outputs the first or second group of voltages according to a polarity signal. The multiplexer selectively outputs the digital value or a complementary value thereof according to the polarity signal. The switch array outputs one of the voltages received from the voltage selector according to the value output from the multiplexer.

According to another embodiment of the present invention, a method for transforming a digital value into an analog signal is disclosed. A first and second group of voltages are provided. The first or second group of voltages is selected according to a polarity signal, and the digital value or a complementary value thereof is selected according to the polarity signal. One of the voltages in the selected group is then output according to the selected value.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 3is a digital-to-analog converter according to one embodiment of the present invention. The digital-to-analog converter300transforms a 6-bit digital value D[5:0] into an analog signal Vout. The digital-to-analog converter300has a voltage generator302, a voltage selector304, a multiplexer306and a switch array308.

The voltage generator302provides a first group of voltages V0˜V63and a second group of voltages V0′˜V63′. The voltage selector304selectively outputs the first group of voltages V0˜V63or the second group of voltages V0′˜V63′ according to a polarity signal POL. The multiplexer (MUX)306selectively outputs a 6-bit digital value D[5:0] or a complementary value thereof D[5:0]B according to the polarity signal POL. The switch array308outputs one of the voltages VV0˜VV63received from the voltage selector304according to the value output from the multiplexer306.

When the digital-to-analog converter300is used, for example, in a source driver of a line-inversion LCD, the digital value D[5:0] can be a pixel value, and the voltages in the first and second group V0˜V63and V0′˜V63′ are gamma voltages.

The switch array308has a first switch array portion318and a second switch array portion328. The first switch array portion318has PMOS transistor columns, and each column receives one of the higher half of the voltages VV0˜VV63output from the voltage selector304. The second switch array portion328has NMOS transistor columns, and each column receives one of the lower half of the voltages VV0˜VV63output from the voltage selector304. That is, the voltages VV0˜VV31with higher voltage levels are input into the first switch array portion318of the PMOS transistors, and the voltages VV32˜VV63with lower voltage levels are input into the second switch portion328of the NMOS transistors.

Moreover, the PMOS transistors in the same column are connected in series, and the NMOS transistors in the same column are connected in series. The gates of the PMOS transistors and NMOS transistors in the same row are all coupled to receive one of the bits with the value D[5:0] or D[5:0]B output from the multiplexer306.

In this embodiment, the voltage generator302has a first string312of resistors R0˜R63(R-string) to provide the first group of voltages V0˜V63and a second string322of resistors R0′˜R63′ to provide the second group of voltages V0′˜V63′.

More particularly, each of the voltages in the first group V0˜V63is a counterpart of one of the voltages in the second group V0′˜V63′, and each of the voltages in the first group and its counterpart in the second group correspond to the same gray level. For example, the voltage V0in the first group is a counterpart of the voltage V0′ in the second group, and both voltages V0and V0′ correspond to the same gray level under different polarities indicated by the polarity signal POL.

The voltage selector304has switches314to selectively output the voltages V0˜V63or V0′˜V63′. Each of the switches314couples one of the voltages in the first group V0˜V63or the counterpart thereof in the second group V0′˜V63′ to one of the outputs of the voltage selector304according to the polarity signal POL. For example, when the polarity signal POL indicates the polarity is high (H), the switches314couples the voltages of the first group V0˜V63to the outputs of the voltage selector304; when the polarity signal POL indicates the polarity is low (L), the switches314couples the voltages of the second group V0′˜V63′ to the outputs of the voltage selector304.

If the voltages of the first and second groups V0˜V63and V0′˜V63′ are properly symmetrical under different polarities, another embodiment of the present invention provides an alternative circuit403to implement the voltage generator and voltage selector, as illustrated inFIG. 4. In the alternative circuit403, one string413of resistors R0˜R63is used to selectively provide the first group of voltages V0˜V63or the second group of voltages V0′˜V63′ from the switches414, which couple different reference voltages to the string413of resistors R0˜R63according to the polarity signal POL.

In addition, referring toFIG. 3, the digital-to-analog converter300further has two latches to transfer the 6-bit digital value D[5:0] to the multiplexer306. One latch is controlled by a clock signal CLK, and the other latch is controlled by a strobe signal STB. According to another embodiment of the present invention, as illustrated inFIG. 5, the digital-to-analog converter can have one latch controlled by the clock signal CLK, transferring the digital value D[5:0] to the multiplexer306, and another latch controlled by the strobe signal STB, transferring the value D[5:0] or D[5:0]B output from the multiplexer306to the switch array308.

In another aspect, a method for transforming a digital value into an analog signal is also disclosed.FIG. 6is a flow chart of the method according to another embodiment of the present invention. The following descriptions are made with reference toFIG. 3andFIG. 6.

Firstly, a first group of voltages V0˜V63and a second group of voltages V0′˜V63′ are provided (step602). The first or second group of voltages V0˜V63or V0′˜V63′ is selected according to a polarity signal POL (step604), and the digital value D[5:0] or a complementary value thereof D[5:0]B is selected according to the polarity signal POL (step606). One of the voltages in the selected group is then output according to the selected value (step608).

When the digital-to-analog converter300is used, for example, in a source driver of a line-inversion LCD, the digital value D[5:0] can be a pixel value, and the voltages in the first and second group V0˜V63and V0′˜V63′ are gamma voltages.

More particularly, each of the voltages in the first group V0˜V63is a counterpart of one of the voltages in the second group V0′˜V63′, and each of the voltages in the first group and its counterpart in the second group correspond to a same gray level. For example, the voltage V0in the first group is a counterpart of the voltages V0′ in the second group, and both of the two voltages V0and V0′ correspond to the same gray level under different polarities indicated by the polarity signal POL.

The embodiments of the present invention modulates the digital value and the gamma voltages in response to different polarities while the LCD displaying, for example, by selecting the corresponding group of voltages and using a multiplexer to obtain the selected value according to the polarity signal of the LCD, and therefore the required columns of transistors in the switch array are decreased and thus the occupied area thereof in the source driver chip is also reduced.