Display substrate having a protruding barrier pattern

A display substrate includes a base substrate, a barrier pattern, a source electrode, a drain electrode, a semiconductor layer, an insulating layer, and a gate electrode. The barrier pattern protrudes from the base substrate. The source and gate electrodes are formed adjacent to opposite sides of the barrier pattern on the base substrate. The semiconductor layer is provided on the barrier pattern to connect the source electrode with the drain electrode, and the insulating layer covers the semiconductor layer, the source electrode, and the drain electrode. The gate electrode is provided on the insulating layer, and is overlapped with the semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application relies for priority upon Korean Patent Application No. 2008-98648 filed on Oct. 8, 2008, the contents of which are herein incorporated by reference in their entirety.

BACKGROUND

1. Field of the Invention

The present invention relates to a display substrate and a method of manufacturing the same. More particularly, the present invention relates to a display substrate capable of reducing leakage current and a method of manufacturing the display substrate.

2. Description of the Related Art

Researches on flexible thin film transistor (TFT) display substrates have been actively carried out. A flexible TFT display substrate employs soluble TFTs such as organic TFTs and oxide TFTs which are suitable for printing processes or ink-jet processes.

Soluble TFTs are classified into top-gate type TFTs having a gate electrode provided on a semiconductor layer and bottom-gate type TFTs having a gate electrode provided below a semiconductor layer. A top-gate type TFT may have a structure in which source and drain electrodes are provided below a channel to be connected to the channel. In such a soluble TFT, current may leak through the channel without an off-operation of the gate electrode.

SUMMARY

Therefore, an exemplary embodiment of the present invention provides a display substrate capable of reducing leakage current of a thin film transistor.

Another exemplary embodiment of the present invention provides a method of manufacturing the display substrate.

In an exemplary embodiment of the present invention, the display substrate includes a base substrate, a barrier pattern, a source electrode, a drain electrode, a semiconductor layer, an insulating layer, and a gate electrode. The barrier pattern protrudes from the base substrate. The source electrode is adjacent to a first side of the barrier pattern on the base substrate. The drain electrode is adjacent to a second side of the barrier pattern on the base substrate. The semiconductor layer is provided on the barrier pattern to connect the source electrode with the drain electrode. The insulating layer covers the semiconductor layer, the source electrode, and the drain electrode. The gate electrode is provided on the insulating layer and overlaps the semiconductor layer.

The barrier pattern is integrally formed with the base substrate.

The barrier pattern may have a thickness equal to or greater than the thicknesses of the source and drain electrodes.

In another exemplary embodiment of the present invention, a method of manufacturing the display substrate is performed as follows.

A barrier pattern is formed on a base substrate. Source and drain electrodes are formed adjacent to two side surfaces of the barrier pattern. Then, a semiconductor layer is formed on the barrier pattern, contacting the source and drain electrodes, and an insulating layer is formed on the source electrode, the drain electrode, and the semiconductor layer. Thereafter, a gate electrode is formed on the insulating layer such that the gate electrode overlaps the semiconductor layer. After forming a protective layer on both the insulating layer and the gate electrode, a pixel electrode is formed on the protective layer to be electrically connected to the drain electrode.

The barrier pattern is formed by patterning a portion of the base substrate.

As described above, the barrier pattern protruding from the base substrate can block current leakage between source and drain electrodes.

The barrier pattern protruding from the base substrate and provided between the source and drain electrodes can be integrally formed with the base substrate, or may be formed on the base substrate by using an insulating material.

DESCRIPTION OF THE EMBODIMENTS

Hereinafter, preferred embodiments of a display substrate and a method of manufacturing the same will be described in detail with reference to accompanying drawings. However, the scope of the present invention is not limited to such embodiments and the present invention may be realized in various forms. The embodiments to be described below are provided to fully disclose the present invention and enable those skilled in the art to understand the present invention. The size of layers and regions shown in the drawings may be simplified or magnified for clarity of explanation. Same reference numerals are used to designate same elements throughout the drawings.

FIG. 1is a plan view of a display substrate10according to an exemplary embodiment of the present invention, andFIG. 2is a cross-sectional view taken along line I-I′ shown inFIG. 1.FIG. 3is an enlarged view of region A ofFIG. 2.

Referring toFIGS. 1,2, and3, the display substrate10includes a base substrate30, a barrier pattern35, a source electrode41, a drain electrode45, a semiconductor layer50, an insulating layer60, a gate electrode71, a protective layer80, and a pixel electrode90.

The base substrate30comprises a flexible and insulating polymer. The base substrate30includes a flexible substrate that is transparent and thin. The base substrate30may comprise polyethylene terephthalate, polyethersulphone, polyetheretherketone, polyetherimide, polyimide, polyethyelene naphtalate, polycarbonate, or fiberglass reinforced plastics.

The barrier pattern35protrudes from the base substrate30. The barrier pattern35is integrally formed with the base substrate30. The barrier pattern35is formed by removing a predetermined thickness from a remaining region of the base substrate30except for a portion thereof. For example, the barrier pattern35may be formed by depositing an insulating materials such as silicon nitride (SiNx) and silicon oxide (SiOx) on the base substrate30and then patterning the insulating material. Alternatively, the barrier pattern35may be an insulator stacked on the base substrate30through a lamination process.

The barrier pattern35may have a thickness greater or equal to the thicknesses of the source and drain electrodes41and45to prevent leakage current from flowing between the source and drain electrodes41and45.

The source electrode41branches from a data line40extending in a first direction of the base substrate30, and is provided in the vicinity of a first side of the barrier pattern35on the base substrate30. For example, the source electrode41may make contact with the first side surface of the barrier pattern35. The source electrode41may have a thickness similar to the thickness of the barrier pattern35.

The drain electrode45is provided in the vicinity of a second side of the barrier pattern35on the base substrate30. The drain electrode45may make contact with the second side surface of the barrier pattern35. The drain electrode45may have a thickness similar to that of the source electrode41.

The semiconductor layer50is provided on the barrier pattern35, the source electrode41, and the drain electrode45. The semiconductor layer50may include a low molecular organic substance such as oligothiophene or pentacene, or a high molecular organic substance such as polythiophene. In addition, the semiconductor layer50may include oxide such as titanium dioxide (TiO2), tin oxide (SnO2), silicon dioxide (SiO2), copper oxide (CuO), zinc oxide (ZnO), zinc titanate (ZnTiO3), and aluminum oxide (Al2O3). The semiconductor layer50is electrically connected to the source and drain electrodes41and45. The semiconductor layer50provides a moving passage for charges55between the source and drain electrodes41and45as shown inFIG. 3. The charges55move on the barrier pattern35between the source and drain electrodes41and45. In the absence of the barrier pattern35, the charges55would move between the source and drain electrodes41and45close to the base substrate30, and would not react with the control of the gate electrode71.

The insulating layer60covers the base substrate30, the semiconductor layer50, the source electrode41, and the drain electrode45. The insulating layer60may include an insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx).

The gate electrode71is formed on the insulating layer60and overlapped with the semiconductor layer50. The gate electrode71branches from a gate line70and crosses the data line40. The gate line70extends in a second direction perpendicular to the first direction. The gate electrode71forms a thin film transistor with the source electrode41, the drain electrode45, and the semiconductor layer50.

The protective layer80covers the gate electrode71and the insulating layer60. The protective layer80insulates the gate electrode71and protects the gate electrode71from external shocks. The protective layer80includes a contact hole85exposing a portion of the drain electrode45. The contact hole85exposes a portion of the drain electrode45by etching a portion of the protective layer80and the insulating layer60.

The pixel electrode90is provided on the protective layer80, and is connected to the drain electrode45through the contact hole85. The pixel electrode90may include a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

Although not shown inFIG. 1, the display substrate10further includes a buffer layer provided on the base substrate30. The buffer layer planarizes the surface of the base substrate30, and prevents the surface of the base substrate30from being damaged by external force. In addition, the buffer layer prevents gas from being discharged from the base substrate30, and prevents moisture or oxygen from infiltrating into the source electrode41, the drain electrode45, and the semiconductor layer50.

Hereinafter, a current-voltage characteristic of the display substrate10according to an exemplary embodiment of the present invention is described in more detail.FIG. 4is a graph showing the current-voltage characteristic of the display substrate10according to an exemplary embodiment of the present invention.

In the graph ofFIG. 4, the X axis represents a voltage (hereinafter, referred to as “gate driving voltage”) of an electric field formed between the gate electrode71and the source electrode41, and the Y axis represents a current (hereinafter, referred to as “driving current”) which flows between the source electrode41and the drain electrode45. A curve120is obtained by providing the barrier pattern35between the source and drain electrodes41and45when the source electrode41, the drain electrode45, the semiconductor layer50, and the gate electrode71form a PMOS structure.

The curve120shows that when the gate driving voltage of about 10V or less is applied, the driving current of about 1E-9A or more flows between the source electrode41and the drain electrode45. In addition, when the gate driving voltage of about 13V or more is applied, the curve120shows that the driving current in the range of about 1E-13A to about 1E-11A flows between the source electrode41and the drain electrode45. The curve120shows that the driving current does not leak between the source electrode41and the drain electrode45when the gate driving voltage has an off level. Accordingly, the curve120shows that the leakage current is reduced between the source electrode41and the drain electrode45by the barrier pattern35.

Hereinafter, a method of manufacturing the display substrate10according to one embodiment of the present invention is described with reference toFIGS. 5 to 22.

FIGS. 5 to 22are views showing a method of manufacturing the display substrate10according to an exemplary embodiment of the present invention.

Referring toFIG. 5, the base substrate30is bonded to a carrier substrate20. The base substrate30is prepared. The base substrate30includes polyethylene terephthalate, polyethersulphone, polyetheretherketone, polyetherimide, polyimide, polyethyelenen napthalate, polycarbonate, or fiberglass reinforced plastics. The base substrate30may be formed through a spin coating method. Then, the carrier substrate20including glass is prepared. Thereafter, an adhesion agent, for example one or more adhesives selected from epoxy resins, urethane resins or acryl resins, is applied between the base substrate30and the carrier substrate20so that the base substrate30is bonded to the carrier substrate20. The carrier substrate20is bonded to the base substrate30such that the base substrate30including a flexible material which can be easily handled.

Subsequently, referring toFIGS. 6,7, and8, the barrier pattern35is formed on the base substrate30. A photoresist material is deposited on the base substrate30to form a photoresist layer32. The photoresist layer32is patterned in a predetermined pattern through a photolithography process. Thereafter, the base substrate30is etched through a dry etch method employing oxygen (O2) gas, thereby forming the barrier pattern35which overlaps the photoresist layer32. Then, the photoresist layer32is removed.

Alternatively, the barrier pattern35may be formed on the base substrate30according to a method shown inFIGS. 9 to 11. In detail, an insulating material is deposited on the base substrate30, thereby forming a coating layer33. The coating layer33may include polyimide, silicon nitride (SiNx), or silicon oxide (SiOx). Thereafter, a photoresist material is deposited on the coating layer33to form the photoresist layer32. Then, the photoresist layer32is patterned to a predetermined pattern through a photolithography process. Subsequently, the coating layer33is etched to form the barrier pattern35. Then, the photoresist layer32is removed.

Although not shown in the figures, the barrier pattern35may be formed on the base substrate30through lamination. For example, an insulator is attached to a roller, and the insulator is laminated on the surface of the base substrate30through the roller to form the barrier pattern35.

Referring toFIGS. 12 and 13, the data line40, the source electrode41, and the drain electrode45are formed on the base substrate30. In detail, one of molybdenum (Mo), copper (Cu), silver (Ag), aluminum (Al), and alloy thereof is deposited on the base substrate30to form a data metal layer. The data metal layer is patterned through a photolithography process to form the data line40extending in the first direction, the source electrode41branching from the data line40, and the drain electrode45spaced apart from the source electrode41. The source electrode41is adjacent to one side of the barrier pattern35, and the drain electrode45is adjacent to the other side of the barrier pattern35. The data metal layer on the barrier pattern35may be removed such that the source electrode41and the drain electrode45make contact with opposite side surfaces of the barrier pattern35, respectively.

Referring toFIGS. 14 and 15, the semiconductor layer50is formed on the barrier pattern35. In this case, a semiconductor material is dropped through an ink-jet method to form the semiconductor layer50. For example, one selected from low molecular organic substances, high molecular organic substances, and oxides is dropped on the barrier pattern35to form the semiconductor layer50which contacts the source and drain electrodes41and45. The semiconductor material may be dropped after a separator provided with a hole to expose portions of the source and drain electrodes41and45and the barrier pattern35is formed on the base substrate30, the source electrode41, and the drain electrode45

Thereafter, referring toFIG. 16, the insulating layer60including an inorganic material is formed on the source electrode41, the drain electrode45, and the semiconductor layer50. The insulating layer60may include silicon nitride (SiNx) or silicon oxide (SiOx).

Referring toFIGS. 17 and 18, the gate line70and the gate electrode71are formed on the insulating layer60. The gate line70extends in the second direction, perpendicular to the first direction, and crosses the data line40. The gate electrode71branches from the gate line70, and overlaps the semiconductor layer50. The gate line70and the gate electrode71may be formed through a metal printing process. For example, a gravure printing device is provided on the insulating layer60and a metal pattern corresponding to the gate line70and the gate electrode71is attached to the surface of the gravure printing device. Thereafter, the metal pattern is printed on the surface of the insulating layer60by using the gravure printing device, thereby forming the gate line70and the gate electrode71.

Referring toFIGS. 19 and 20, an organic material or an inorganic material is deposited on the insulating layer60, the gate line70, and the gate electrode71to form the protective layer80. Thereafter, a portion of the insulating layer60and a portion of the protective layer80, which is overlapped by a portion of the drain electrode45, are removed to form the contact hole85. The contact hole85exposes a portion of the drain electrode45.

Referring toFIGS. 21 and 22, the pixel electrode90including a transparent conductive material is formed on the protective layer80. In detail, one of indium tin oxide (ITO) and indium zinc oxide (IZO) is deposited on the protective layer80and then patterned to form the pixel electrode90that contacts the drain electrode45through the contact hole85.

In the method of manufacturing the display substrate described above, a buffer layer may be further formed on the base substrate30before the data line40, the source electrode41, and the drain electrode45are formed. In detail, silicon nitride (SiNx) is deposited on the base substrate30and the barrier pattern35to form the buffer layer. The buffer layer formed on the barrier pattern35is then removed. The buffer layer planarizes the surface of the base substrate30, and prevents the surface of the base substrate30from being damaged. In addition, the buffer layer prevents moisture or oxygen (O2) from infiltrating into the surface of the base substrate30.