Output circuit, temperature switch IC, and battery pack

An output circuit has a smaller area and restrains outputs from becoming unstable even if a power supply voltage is lower than an operating voltage. A supply terminal of an inverter circuit is provided with switch circuit, and the switch circuit stops the operation of the inverter circuit when the power supply voltage is lower than the operating voltage of the circuit. Further, the output terminal of the inverter circuit is provided with a current source to fix the output to the power supply voltage when the operation of the inverter circuit is stopped.

RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Japanese Patent Application No. 2011-013326 filed on Jan. 25, 2011, the entire content of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an output circuit, the output of one end of which has high impedance and, more particularly, to an output circuit which stably operates when a power supply voltage is low. The present invention further relates to a temperature switch IC and a battery pack, each of which is provided with the aforementioned output circuit.

2. Description of the Related Art

The following will describe a conventional output circuit.FIG. 7is a circuit diagram illustrating a conventional output circuit.

The conventional output circuit includes an inverter97connected to an input terminal, an NMOS transistor93, which is an output driver, a diode-connected NMOS transistor95and a capacitor96, which are provided between a power source and the ground, and an NMOS transistor94controlled thereby.

When the circuit is turned on, a power supply voltage VDD gradually rises. The NMOS transistor95remains nonconductive while the power supply voltage VDD is lower than a threshold voltage Vthn95. The NMOS transistor94turns off, because the gate voltage thereof becomes an earth voltage VSS due to the capacitor96. Hence, the output terminal of the output circuit is in a high-impedance state. This ensures that the output terminal of the output circuit is always set in the high-impedance state if the power supply voltage VDD at the time of, for example, turning the circuit on, is lower than a minimum operating voltage of the circuit.

When the power supply voltage VDD exceeds the threshold voltage Vthn95of the NMOS transistor95, the NMOS transistor95becomes conductive. The capacitor96is charged by the current supplied by the NMOS transistor95. When the gate voltage thereof gradually rises and exceeds a threshold voltage, the NMOS transistor94turns on. When the NMOS transistor94turns on, the function of the NMOS transistor93is rendered valid, transmitting an output of the inverter97to the output terminal. If the voltage of an input terminal of the output circuit is at a low level, then the NMOS transistor93turns on, and an output voltage VOUT of the output terminal becomes the earth voltage VSS. If the voltage at the input terminal of the output circuit is at a high level, then the NMOS transistor93turns off, causing the output voltage VOUT of the output terminal to be set in the high-impedance state (refer to, for example, patent document 1).

In the conventional output circuit, the NMOS transistor94is provided in series with the NMOS transistor93. The NMOS transistor93, which is an output driver, is required to provide a drive capability. For this reason, a large NMOS transistor is used for the transistor93. Thus, the NMOS transistor94is required to provide a drive capacity that is equivalent to or higher than that of the NMOS transistor93.

The conventional output circuit has been posing a problem that the large size of the NMOS transistor94inconveniently leads to a large area of the output circuit.

SUMMARY OF THE INVENTION

The present invention has been made in view of the problem described above, and an object of the invention is to provide an output circuit with a smaller area.

To this end, the present invention provides an output circuit with open-drain output including: an inverter circuit connected to an input terminal of the output circuit; an output MOS transistor having a gate thereof connected to an output terminal of the inverter circuit; a drain thereof connected to an output terminal of the output circuit, and a source thereof connected to a first supply terminal; a switch circuit provided between the inverter circuit and a second supply terminal; and a current source provided between the gate of the output MOS transistor and the first supply terminal, wherein the switch circuit turns off when a power supply voltage is lower than a minimum operating voltage of the output circuit.

The output circuit according to the present invention is configured such that, if a power supply voltage is lower than an operating voltage of the circuit, then the operation of the inverter is interrupted and the gate of an output driver is controlled to turn it off. Hence, a large MOS transistor is no longer required to be provided between the source of the output driver and a power source. This arrangement enables the output circuit to restrain unstable outputs even when the power supply voltage is lower than the operating voltage and to achieve a reduced area.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1is a circuit diagram illustrating an output circuit according to an embodiment of the present invention.

An output circuit10has PMOS transistors11and12, NMOS transistors21and22, and a current source31.

The PMOS transistor11has the gate thereof connected to the input terminal of the output circuit10, the source thereof connected to the drain of the PMOS transistor12, and the drain thereof connected to the gate of the NMOS transistor22. The NMOS transistor21has the gate thereof connected to the input terminal of the output circuit, the source thereof connected to an earth terminal (a power supply terminal at an earth voltage side), and the drain thereof connected to the gate of the NMOS transistor22. The PMOS transistor12has the gate thereof connected to the earth terminal and the source thereof connected to a supply terminal (the power supply terminal at a power supply voltage side). The PMOS transistor12is provided on a power supply line of an inverter36composed of the PMOS transistor11and the NMOS transistor21.

The current source31is provided between the drain of the PMOS transistor11and the earth terminal. The NMOS transistor22has the source thereof connected to the earth terminal and the drain thereof connected to the output terminal of the output circuit10. The NMOS transistor22is an open-drain output driver.

The absolute value |Vthp12| of the threshold voltage of the PMOS transistor12is higher than the absolute value |Vthp11| of the threshold voltage of the PMOS transistor11and indicates the minimum operating power supply voltage of the output circuit10. If a power supply voltage VDD is lower than the minimum operating power supply voltage, then the PMOS transistor12turns off so as not to supply the power supply voltage VDD to the inverter36. Further, the current source31turns the NMOS transistor22off.

The operation of the output circuit10will now be described.

When the power is turned on, the power supply voltage rises. At this time, if the power supply voltage VDD is lower than the absolute value |Vthp12| of the threshold voltage of the PMOS transistor12, then the PMOS transistor12turns off. This prevents the power supply voltage VDD from being supplied to the inverter36. Therefore, the output terminal of the inverter36is pulled down by the current source31, so that the output voltage of the inverter36is an earth voltage VSS. The NMOS transistor22, which is the output driver, turns off because the gate voltage thereof becomes the earth voltage VSS, thus setting the output terminal of the output circuit10in the high impedance state. Hence, the output terminal of the output circuit10is pulled up to the power supply voltage of a circuit in a subsequent stage, the aforementioned output terminal being connected to the input terminal of the circuit in the subsequent stage. This arrangement restrains the circuit in the subsequent stage from malfunctioning.

If the power supply voltage VDD becomes higher than the absolute value |Vthp12| of the threshold voltage of the PMOS transistor12, then the PMOS transistor12turns on. This causes the power supply voltage VDD to be supplied to the inverter36.

If the voltage at the input terminal of the output circuit10is a low level, then the gate voltage of the NMOS transistor22becomes a high level due to the inverter36, causing the NMOS transistor22to turn on and the output voltage VOUT to become the earth voltage VSS. The current source31is designed to have a drive capability that is lower than the drive capability of the PMOS transistor11.

If the voltage at the input terminal of the output circuit10becomes a high level, then the gate voltage of the NMOS transistor22becomes a low level due to the inverter36. This causes the NMOS transistor22to turn off, placing the output terminal of the output circuit10in the high-impedance state.

The output circuit according to the present embodiment is configured such that, when the power supply voltage is lower than the operating voltage of the circuit, the operation of the inverter is interrupted and the gate of the output driver is turned off by the current source, thus obviating the need for providing a large MOS transistor between an output driver and a power source. This permits a reduced area of the output circuit10.

Further, if the power supply voltage VDD at the time of, for example, turning the power on, is lower than the minimum operating power supply voltage of the output circuit10, then the output voltage VOUT always causes high impedance, thus restraining a circuit in a subsequent stage from malfunctioning.

FIG. 2is a circuit diagram illustrating another example of the output circuit according to the present embodiment. The output circuit10inFIG. 2further includes a current source32and a PMOS transistor13.

The PMOS transistor13and the current source32are connected in series between a supply terminal and an earth terminal. The PMOS transistor13has the gate and the drain thereof connected to the earth terminal. The connection point of the current source32and the source of the PMOS transistor13is connected to the gate of the PMOS transistor12.

According to the configuration described above, the minimum operating power supply voltage of the output circuit10is set by the current source32and the two PMOS transistors12and13. More specifically, when a power supply voltage VDD becomes higher than the total voltage of the absolute values of the threshold voltages of the two PMOS transistors12and13, the PMOS transistor12is turned on and the power supply voltage VDD is supplied to an inverter36.

At the output end inFIG. 2, the diode-connected PMOS transistor13is provided between the gate of the PMOS transistor12and the earth terminal. Alternatively, however, a diode-connected NMOS transistor may be provided instead of the PMOS transistor13.

FIG. 3is a circuit diagram illustrating another example of the output circuit according to the present embodiment. As illustrated inFIG. 3, the gate of the NMOS transistor22may be connected to the drain of the PMOS transistor11through the intermediary of a resistor33.

In the aforementioned configuration, a low-pass filter is constituted by the resistor33and the capacitor between the gate and the source of the NMOS transistor22, thus reducing the malfunctions of the NMOS transistor22caused by a surge. The gate of the NMOS transistor22may be connected to the connection point of the resistor33and the drain of the NMOS transistor21.

In the output circuit shown inFIG. 1, the NMOS transistor for controlling the supply of the power supply voltage VDD to the inverter36may be provided between the inverter36and the earth terminal. Further, inFIG. 1, the open-drain NMOS transistor22is used, and the output voltage VOUT becomes the high impedance state in the case where the power supply voltage VDD is lower than the minimum operating power supply voltage of the output circuit10. However, although not shown, an open-drain PMOS transistor may alternatively be used. At this time, the gate of the NMOS transistor for controlling the supply of the power supply voltage VDD to the inverter36is connected to a supply terminal, the source thereof is connected to an earth terminal, and the drain thereof is connected to the source of the NMOS transistor21. The gate of the open-drain PMOS transistor is connected to the output terminal of the inverter36, the source thereof is connected to the supply terminal, and the drain thereof is connected to the output terminal of the output circuit10. The current source31is provided between the supply terminal and the output terminal of the inverter36.

When the power supply voltage VDD becomes higher than the threshold voltage Vthn of the NMOS transistor, the NMOS transistor turns on and the power supply voltage VDD is supplied to the inverter36.

If the power supply voltage VDD is lower than the absolute value |Vthp12| of the threshold voltage of the PMOS transistor12, then the PMOS transistor12turns off. Thus, the power supply voltage VDD is not supplied to the inverter36. Hence, the output terminal of the inverter36is pulled up by the current source31, so that the output voltage of the inverter36becomes the power supply voltage VDD. The PMOS transistor turns off, and the output voltage VOUT becomes the high impedance state.

An application example of the output circuit10will now be described. First, the construction of a temperature switch IC provided with the output circuit10and the construction of a battery pack provided with a battery protection IC will be described. The temperature switch IC detects an abnormal temperature. The battery protection IC protects a battery from overcharge/overdischarge.FIG. 4is a block diagram illustrating the battery pack.FIG. 5is a block diagram illustrating the battery protection IC.FIG. 6is a block diagram illustrating the temperature switch IC.

As illustrated inFIG. 4, a battery pack50includes a battery protection IC51, a temperature switch IC52, p-type FETs53to55, a resistor57, and a battery58. Further, the battery pack50has an external terminal EB+ and an external terminal EB−.

As illustrated inFIG. 5, the battery protection IC51includes reference voltage generating circuits61and62, an overcharge detection comparator64, and an overdischarge detection comparator63. Further, the battery protection IC51has a supply terminal, an earth terminal, a charge control terminal CO, and a discharge control terminal DO.

As illustrated inFIG. 6, the temperature switch IC52has a temperature voltage generating circuit75, reference voltage generating circuits71and72, a high temperature detection comparator73, a low temperature detection comparator74, a NOR circuit76, and an output circuit10. The temperature voltage generating circuit75is constituted of a PNP bipolar transistor and the like, although not shown. Further, the temperature switch IC52has a supply terminal, an earth terminal, and an output terminal DET.

The supply terminal of the battery protection IC51is connected to the positive terminal of the battery58, the earth terminal thereof is connected to the negative terminal of the battery58, the discharge control terminal DO is connected to the gate of the p-type FET53, and the charge control terminal CO is connected to the gate of the p-type FET54and the drain of the p-type FET55. The supply terminal of the temperature switch IC52is connected to the positive terminal of the battery58, the earth terminal thereof is connected to the negative terminal of the battery58, and the output terminal DET thereof is connected to the gate of the p-type FET55.

The resistor57is provided between the external terminal EB+ and the connection point of the output terminal DET and the gate of the p-type FET55. The source and the back gate of the p-type FET53are connected to the positive terminal of the battery58, and the drain thereof is connected to the drain of the p-type FET54. The source and the back gate of the p-type FET54are connected to the external terminal EB+. The source and the back gate of the p-type FET55are connected to the external terminal EB+. The external terminal EB− is connected to the negative terminal of the battery58. In other words, the p-type FETs53and54are provided in series in the charge/discharge path of the battery58.

The reference voltage generating circuits61and62, the overcharge detection comparator64, and the overdischarge detection comparator63are provided between the supply terminal and the earth terminal. The inverting input terminal of the overcharge detection comparator64is connected to the output terminal of the reference voltage generating circuit62, the non-inverting input terminal thereof is connected to the supply terminal, and the output terminal thereof is connected to the charge control terminal CO. The inverting input terminal of the overdischarge detection comparator63is connected to the supply terminal, the non-inverting input terminal thereof is connected to the output terminal of the reference voltage generating circuit61, and the output terminal thereof is connected to the discharge control terminal DO.

The reference voltage generating circuits71and72, the high temperature detection comparator73, the low temperature detection comparator74, the temperature voltage generating circuit75, the NOR circuit76, and the output circuit10are connected between the supply terminal and the earth terminal. The non-inverting input terminal of the high temperature detection comparator73is connected to the output terminal of the reference voltage generating circuit71, while the inverting input terminal thereof is connected to the output terminal of the temperature voltage generating circuit75. The non-inverting input terminal of the low temperature detection comparator74is connected to the output terminal of the temperature voltage generating circuit75, while the inverting input terminal thereof is connected to the output terminal of the reference voltage generating circuit72. The first input terminal of the NOR circuit76is connected to the output terminal of the high temperature detection comparator73, the second input terminal thereof is connected to the output terminal of the low temperature detection comparator74, and the output terminal thereof is connected to the input terminal of the output circuit10. The output terminal of the output circuit10is connected to the output terminal DET.

Upon detection of an abnormal temperature, the temperature switch IC52emits an output current. The resistor57generates a voltage on the basis of the output current. The voltage generated in the resistor57turns the p-type FET55on. This causes the p-type FET54for charge control to turn off, thus controlling charge. If the battery58is overcharged, then the battery protection IC51operates to turn the p-type FET54off. If the battery58is overdischarged, then the battery protection IC51operates to turn the p-type FET53for discharge control off.

The operation of the battery pack50will now be described.

[Operation Performed when the Battery58is Overcharged]

A charger (not shown) is connected to the battery pack50. The reference voltage generating circuit62generates a reference voltage VREF2based on an overcharge voltage indicating that the battery58is in an overcharged state. The overcharge detection comparator64compares a divided voltage of the voltage of the battery58with the reference voltage VREF2, and reverses an output voltage according to the comparison result. More specifically, if the divided voltage of the voltage of the battery58exceeds the reference voltage VREF2, then the output voltage of the overcharge detection comparator64is reversed to a high level. This turns the p-type FET54off, stopping the charging of the battery58.

[Operation Performed when the Battery58is Overdischarged]

A load (not shown) is connected to the battery pack50. The reference voltage generating circuit61generates a reference voltage VREF1based on an overdischarge voltage indicating that the battery58is in an overdischarged state. The overdischarge detection comparator63compares a divided voltage of the voltage of the battery58with the reference voltage VREF1, and reverses an output voltage according to the comparison result. More specifically, if the divided voltage of the voltage of the battery58drops to the reference voltage VREF1or lower, then the output voltage of the overdischarge detection comparator63is reversed to a high level. This turns the p-type FET53off, stopping the discharging of the battery58.

[Operation in Case of Abnormally High Temperature]

The temperature voltage generating circuit75generates a temperature voltage VTEMP based on a temperature. The temperature voltage generating circuit75is characteristic in that the temperature voltage VTEMP drops as the temperature rises. The reference voltage generating circuit71generates a reference voltage VREF3based on an abnormally high temperature to be detected. The high temperature detection comparator73compares the temperature voltage VTEMP with the reference voltage VREF3and reverses the output voltage according to the comparison result. More specifically, as the temperature rises, the temperature voltage VTEMP drops, and the output voltage of the high temperature detection comparator73switches to a high level when the temperature voltage VTEMP drops to the reference voltage VREF3 or less. In other words, if the temperature reaches an abnormally high temperature level or more, then the output voltage of the high temperature detection comparator73is switched to the high level. As a result, the output voltage of the NOR circuit76is set to a low level, the output circuit10is turned on to supply current to the resistor57, a voltage is generated at the resistor57, and the voltage of the output terminal DET is set to the low level. This causes the p-type FET55to turn on and the p-type FET54to turn off, thus stopping the charging of the battery58.

[Operation in Case of Abnormally Low Temperature]

The reference voltage generating circuit72generates a reference voltage VREF4based on an abnormally low temperature to be detected. The low temperature detection comparator74compares the temperature voltage VTEMP with the reference voltage VREF4and reverses the output voltage according to the comparison result. More specifically, as the temperature decreases, the temperature voltage VTEMP rises, and the output voltage of the low temperature detection comparator74switches to a high level when the temperature voltage VTEMP reaches the reference voltage VREF4or more. In other words, if the temperature decreases to an abnormally low temperature level or less, then the output voltage of the low temperature detection comparator74is switched to the high level. This causes the charging of the battery58to be stopped as described above.

Thus, the operation of the aforementioned output circuit10ensures that the output circuit10of the temperature switch IC52always turns off if the power supply voltage VDD is lower than the minimum operating power supply voltage of the output circuit10. As a result, the voltage at the output terminal of the output circuit10, i.e., the voltage at the output terminal DET of the temperature switch IC52is invariably pulled up to the voltage at the external terminal EB+ by the resistor57. Hence, if the power supply voltage VDD is lower than the minimum operating power supply voltage of the output circuit10, the p-type FET55invariably turns off, thereby invariably disabling the temperature switch IC52to control the p-type FET54through the intermediary of the p-type FET55. Accordingly, when, for example, the charging of the battery58is started from a state wherein the voltage thereof is in the vicinity of zero volt, it is possible to prevent the temperature switch IC52from malfunctioning to turn the p-type FET54off due to the low voltage (power supply voltage VDD) of the battery58and erroneously stopping the charging despite that the voltage of the battery58is low.

As illustrated inFIG. 6, the overcharge detection comparator64and the overdischarge detection comparator63are required as the protective functions for the battery pack50. However, in the case where the specifications of the battery pack50do not require the overdischarge detection function as the protective function, the overdischarge detection comparator63may be deleted, although not shown. In this case, the p-type FET53would be also deleted.

Further, illustrated inFIG. 6, the high temperature detection comparator73and the low temperature detection comparator74are required as the protective functions for the battery pack50. However, in the case where the specifications of the battery pack50do not require the low temperature detection function or the high temperature detection function as the protective function, the low temperature detection comparator74or the high temperature detection comparator73may be omitted.

Further, the resistor57, the p-type FET55or the like may be incorporated in the temperature switch IC52.

InFIG. 4, the p-type FETs53and54for controlling charge/discharge are provided between the external terminal EB+ and the positive terminal of the battery58. Alternatively, however, two n-type FETs may be provided between the external terminal EB− and the negative terminal of the battery58, although now shown. In this case, the p-type FET55, the resistor57, the internal circuit of the battery protection IC51, and the internal circuit of the temperature switch IC52would be changed, as necessary.

InFIG. 4, the temperature switch IC52controls only the p-type FET54for charge control. Alternatively, however, the temperature switch IC52may control only the p-type FET53for discharge control, although not shown, or may control both the p-type FETs53and54.