Materials and deposition schemes using photoactive materials for interface chemical control and patterning of predefined structures

Embodiments of the invention include microelectronic devices and methods of forming such devices. In an embodiment, a microelectronic device, includes one or more pre-patterned features formed into a interconnect layer, with a conformal barrier layer formed over the first wall, and the second wall of one or more of the pre-patterned features. A photoresist layer may formed over the barrier layer and within one or more of the pre-patterned features and a conductive via may be formed in at least one of the pre-patterned features.

CROSS-REFERENCE TO RELATED APPLICATION

This patent application is a U.S. National Phase Application under 35 U.S.C. § 371 of International Application No. PCT/US2014/072387, filed Dec. 24, 2014, entitled MATERIALS AND DEPOSITION SCHEMES USING PHOTOACTIVE MATERIALS FOR INTERFACE CHEMICAL CONTROL AND PATTERNING OF PREDEFINED STRUCTURES.

TECHNICAL FIELD

Embodiments of the invention are in the field of semiconductor structures and processing and, in particular, self-aligned via patterning for back end of line (BEOL) interconnects.

BACKGROUND

Integrated circuits commonly include electrically conductive microelectronic structures, which are known in the arts as vias, to electrically connect metal lines or other interconnects above the vias to metal lines or other interconnects below the vias. Vias are typically formed by a lithographic process. Representatively, a photoresist layer may be spin coated over a dielectric layer, the photoresist layer may be exposed to patterned actinic radiation through a patterned mask, and then the exposed layer may be developed in order to form an opening in the photoresist layer. Next, an opening for the via may be etched in the dielectric layer by using the opening in the photoresist layer as an etch mask. This opening is referred to as a via opening. Finally, the via opening may be filled with one or more metals or other conductive materials to form the via.

In the past, the sizes and the spacing of vias has progressively decreased, and it is expected that in the future the sizes and the spacing of the vias will continue to progressively decrease, for at least some types of integrated circuits (e.g., advanced microprocessors, chipset components, graphics chips, etc.). One measure of the size of the vias is the critical dimension of the via opening. One measure of the spacing of the vias is the via pitch.

When patterning extremely small vias with extremely small pitches by such lithographic processes, several challenges present themselves, especially when the pitches are around 70 nanometers (nm) or less and/or when the critical dimensions of the via openings are around 35 nm or less. One such challenge is that the overlay between the vias and the overlying interconnects, and the overlay between the vias and the underlying landing interconnects, generally need to be controlled to high tolerances on the order of a quarter of the via pitch. As via pitches scale ever smaller over time, the overlay tolerances tend to scale with them at an even greater rate than lithographic equipment is able to keep up.

Another such challenge is that the critical dimensions of the via openings generally tend to scale faster than the resolution capabilities of the lithographic scanners. Shrink technologies exist to shrink the critical dimensions of the via openings. However, the shrink amount tends to be limited by the minimum via pitch, as well as by the ability of the shrink process to be sufficiently optical proximity correction (OPC) neutral, and to not significantly compromise line width roughness (LWR) and/or critical dimension uniformity (CDU).

Yet another such challenge is that the LWR and/or CDU characteristics of photoresists generally need to improve as the critical dimensions of the via openings decrease in order to maintain the same overall fraction of the critical dimension budget. However, currently the LWR and/or CDU characteristics of most photoresists are not improving as rapidly as the critical dimensions of the via openings are decreasing.

A further such challenge is that the extremely small via pitches generally tend to be below the resolution capabilities of even extreme ultraviolet (EUV) lithographic scanners. As a result, commonly two, three, or more different lithographic masks may be used, which tend to increase the costs. At some point, if pitches continue to decrease, it may not be possible, even with multiple masks, to print via openings for these extremely small pitches using EUV scanners.

Thus, improvements are needed in the area of via manufacturing technologies.

DESCRIPTION OF THE EMBODIMENTS

As described above, continued scaling of devices has necessitated that the critical dimension and the pitch of via openings formed in an interconnect layer decrease beyond the traditional capabilities of standard BEOL processing equipment. To overcome the limitations of the existing processing equipment, embodiments of the invention may utilize an interconnect layer100that comprises a plurality of pre-patterned features120. Such an interconnect layer100is illustrated in the plan view shown inFIG. 1A. In the illustrated embodiment, the pre-patterned features120may be formed at regular intervals over the interconnect layer100. In the illustrated embodiment, the pre-patterned features120are substantially square, though embodiments are not limited to such configurations.

According to an embodiment, pre-patterned features120may be formed at every potential location where a via could possibly be formed. A photoresist material may then be deposited into each of the pre-patterned features120and the desired locations for the vias may be selectively patterned. Since the photoresist is confined in each pre-patterned feature120, BEOL lithography equipment does not need to have the capability to resolve the critical dimension of the via. Additionally, the photoresist material does not need to be optimized to produce the desired LWR or CDU characteristics since the pre-patterned features define the pattern of the vias. As such, high dosages that are typically needed for roughness control when developing a photoresist material may be reduced. Therefore, the pre-patterned feature approach may be used to circumvent imaging/dose tradeoff which limits the throughput of next generation lithographic processes.

The plan view of the interconnect layer100inFIG. 1Ais depicted as being formed with a single material in order to not unnecessarily obscure the invention. However, according to additional embodiments, the interconnect layer100may be formed from multiple materials. An exemplary illustration of how multiple materials may be used to form the pre-patterned features120in an interconnect layer100is shown in the perspective view of a portion of an interconnect layer100illustrated inFIG. 1B. For example, three different materials are illustrated inFIG. 1B. According to an embodiment of the invention, one or more of the materials may be patterned to form a cross-grating. For example, a grating pattern in a first layer171may be oriented perpendicular to a grating pattern in a second layer172in order to form the cross-grating pattern. A floor layer174may be formed in spaces between the cross-grating pattern formed by the first layer171and the second layer172. Together, the layers may define the pre-patterned feature120. For example, a first wall151of the pre-patterned feature may be defined by a portion of the first layer171, a second wall152of the pre-patterned feature may be defined by a portion of the second layer172, and a floor154of the pre-patterned feature may be defined by a portion of the floor layer174.

Embodiments of the invention may form tightly pitched features that exceed the limits of the BEOL lithography equipment by using a spacer-etching process to form the grating pattern in each layer. Representatively, first sacrificial structures may be formed over a first unpatterned layer171. The first sacrificial structures may have a pitch and a critical dimension that may be produced by the BEOL lithography equipment. First spacers may then be formed along the sidewalls of the first sacrificial structures. The first sacrificial structures may then be etched away, leaving behind the first spacers. Since two spacers are formed for each sacrificial structure, the spacers may have a pitch that is half the pitch of the sacrificial structures. According to an embodiment, the pitch may optionally be halved again by forming an additional set of spacers along the sidewalls of the first spacers. The pattern of the first spacers may then be transferred into the first unpatterned layer with an etching process, using the first spacers as a mask layer to form the first grating pattern. Next, the second layer172may then be deposited over the first grating structure. Thereafter, the spacer-etching process may be repeated with second sacrificial structures and second spacers that are oriented orthogonally to the first grating pattern in order to produce the cross grating pattern illustrated inFIG. 1B.

In an embodiment, each of the layers used to form the interconnect layer100may be different materials. For example, the first layer171and the second layer172may be comprised of one or more materials used in semiconductor fabrication processes, such as, for example, Si, α-Si, oxides (e.g., SiO, TiO, AlO, etc.), nitrides (e.g., SiN, TiN, SiON, TaN, etc.), carbides (e.g., SiC, SiOC, carbon hardmask, etc.). For example, these materials may be formed with various processes, such as spin-on coating, CVD, PVD, ALD, or the like. Various wet cleans may also accompany the etching processes. In general, a final wet clean may be done on the substrate prior to the deposition of the photoresist into the pre-patterned features120. In an embodiment, the floor layer174may be a conductive material, such as a metal contact or an interconnect line of a lower interconnect layer. By way of example, the interconnect line may be copper, tungsten, or any other conductive material used in interconnect lines. Alternatively, the floor layer174may be a dielectric material according to an embodiment.

In embodiments, the interconnect layer100may be formed directly over a semiconducting substrate, such as a silicon substrate, a III-V semiconductor substrate, or the like. Embodiments may include a semiconducting substrate that includes integrated circuitry. Vias and contacts that are formed on and/or through the interconnect layer100may provide electrical contacts to the integrated circuitry. According to an additional embodiment, one or more additional interconnect layers may separate the interconnect layer100from a semiconducting substrate. In such embodiments, conductive lines and vias formed on or through the interconnect layer100may provide electrical connections to contact lines and vias formed in the additional interconnect layers formed below the interconnect layer100.

WhileFIGS. 1A and 1Billustrate a plurality of pre-patterned features120that are approximately square and defined by a cross-grating pattern of multiple material layers, (i.e., “2D pre-patterned features”), it is to be appreciated that embodiments of the invention are not limited to such configurations. For example, pre-patterned features120may also be approximately rectangular in shape and formed with a single grating pattern, (i.e., “1D pre-patterned features”). Pre-patterned features120according to such embodiments are illustrated in the schematic plan view shown inFIG. 1C.

FIGS. 2A-2Care cross-sectional illustrations that depict a process for forming vias in conjunction with the pre-patterned features. As shown inFIG. 2A, a photoresist material222may be disposed into each of the pre-patterned features220that are defined by one or more material layers. For example, each of the pre-patterned features220may be defined by a first material layer271, a second material layer272, and a floor layer274. In an embodiment, the photoresist material222may be spun on. The photoresist may be a positive or a negative photoresist. The photoresist systems used may be compatible with deep ultra violet (DUV) radiation, according to an embodiment. Additional embodiments may also include chemically amplified resist (CAR) systems. In a CAR system, a photoacid generator (PAG) may be included in the resist system. The PAG allows for an acid to be formed upon exposure to a particular wavelength of radiation. For example, in a positive DUV compatible system, radiation that has a 248 nm wavelength may be used to cause the PAG to form an acid. The acid acts as a catalyst in order to “deblock” the blocking group that prevents the resin used for the resist from being soluble in a developer. As such, the areas of the resin that were exposed to the radiation become soluble in a developer. By way of example, the photoresist may be a tert-butyloxycarbonyl protecting group (t-BOC) poly hydroxystyrene (PHS) resin system, an acetal system, an environmentally stable chemically amplified photoresist (ESCAP) system, or the like.

Thereafter, the photoresist material222in one or more of the pre-patterned features220are exposed with radiation285from a radiation source (not shown), as illustrated inFIG. 2B. A mask280may be used to shield certain pre-patterned features from the radiation285in order to allow for vias to be formed at desired locations. When a positive resist system is used, the opening281in the mask is formed where a via is desired, whereas when a negative photoresist system is used, the opening281is formed where a via is not desired.

As illustrated, mask openings281may have a width WMthat is greater than the width WFof the pre-patterned feature220since the photoresist is confined to the dimensions of the pre-patterned features220. Accordingly, the resolution capabilities of the lithographic scanners used do not need to be capable of resolving features with the pitch and critical dimension of the pre-patterned features220. For example, if the mask opening allows for radiation285to contact the portions of the interconnect layer200that are not within the pre-patterned feature220, there will not be any patterning, since the materials surrounding the pre-patterned feature220are non-photolyzable.

Typically, the radiation source interacts with PAGs to release acidic components that alter the chemistry of the photoresist material222. As used herein, the photoresist material that has been chemically altered so that it is developable by the developer may be referred to as developable photoresist material223. For example, the acid may render the photoresist soluble in a developer by deblocking the resin, as described above.

However, some materials that may contact the photoresist material may render the photoresist undevelopable or reduce the effectiveness of the photoresist (e.g., a larger dosage of radiation is needed to develop the photoresist). Such negative interactions between the materials forming the interconnect layer200and the photoresist material222may be referred to herein as “substrate poisoning”. One example of substrate poisoning is when a material used to form a portion of the pre-patterned feature220is porous and retains basic chemicals that were used during a cleaning or etching processes. In such a situation, the acids produced by the PAGs of the photoresist may be neutralized by the diffusion of the basic chemicals from the wall or floor materials as indicated by arrows270inFIG. 2B. As such, the photoresist may not be soluble in the developer.

By way of example, substrate poisoning may occur when the first and second material layers271,272are a SiOC-based porous ILD material and/or the floor layer274is a SiN material. In such embodiments, a final clean of the surface prior to the deposition of the photoresist material222into the pre-patterned feature220may be an ammonia-based clean. After the photoresist is spun-on, exposed, and baked, the PAGs in the photoresist may be neutralized by the basic chemicals from the ammonia-based clean that diffuse from the porous materials used to form the first and second sidewalls251,252and the floor254of the pre-patterned features220. It is to be appreciated that the presence of substrate poisoning that results from the use of an ammonia-based clean in conjunction with porous materials is used for exemplary purposes. Substrate poisoning may be caused by a variety of different etching chemistries, cleaning chemistries, material selections, or combinations thereof.

Examples of the effects of substrate poisoning are illustrated in the cross-sectional views of pre-patterned features220shown inFIGS. 2C and 2D. InFIG. 2C, the photoresist material is not fully removed from the sidewalls and floor of each exposed pre-patterned feature after the interconnect lay is developed. As such, residual portions232of the photoresist material may be left behind. Since the photoresist cannot be completely removed, subsequent processing operations, such as a metal deposition to form a via to the floor254or an etching process through the floor254, may not be effective.

While residual portions of the photoresist may remain on both sidewalls and the floor of each pre-patterned feature220, embodiments are not limited to such configurations. For example,FIG. 2Dillustrates a pre-patterned feature220that includes residual photoresist232along the sidewalls. Such situations may occur when one material leaches a substance that quenches an acid formed from the PAGs, whereas the other materials that form the pre-patterned features220do not. Depending on the degree of substrate poisoning, the residual portion232of the resist may be less than or greater than the amount of residual resist illustrated in the exemplary embodiments described in detail herein. For example, substrate poisoning may result in the photoresist material222in a pre-patterned feature220being entirely undevelopable.

Due to the negative interactions that may occur between materials that form the sidewalls and floors of the pre-patterned features220and the photoresist material222, a process flow for forming an interconnect structure must be carefully engineered in order to minimize negative interactions. For example, the materials, the etching chemistries, the cleaning chemistries, and the photoresist system may be chosen to minimize negative interactions. However, during the process development cycle, it may be necessary to change one or more of the materials, the processing conditions, and/or the processing operations. These changes result in new materials and potential diffusion species that need to be accounted for in order to prevent or minimize the effects of substrate poisoning. As such, it may be necessary to redesign the photoresist system in order to minimize the effect of substrate poisoning whenever there is a change to the process flow. Furthermore, design rules, material constraints, and/or other process limitations may make it impractical, or even impossible, to prevent negative interactions between the materials used for the pre-patterned features220and the photoresist material222.

Accordingly, embodiments of the invention include forming a bather layer between one or more of the surfaces of the pre-patterned features220and the photoresist material222. The barrier layer prevents substrate poisoning that occurs as the result of diffusion of unwanted compounds that may quench the photo-acids produced by the PAGs. The presence of a barrier layer also allows for changes in the materials used to form the pre-patterned features220and/or changes in the chemistries used in the etching and/or cleaning process used to form the pre-patterned features220to be implemented during the process development cycle without having to redesign the photoresist system. Furthermore, the presence of a barrier layer may provide an additional site where PAGs may be anchored. As such, the concentration of a photoactive component (e.g., the PAGs) within the photoresist material may be reduced or eliminated. This may be beneficial because solubility limits of the photoresist resin may limit the concentration of the photoactive compound that may be present in the photoresist material. For example, including additional PAGs in the barrier layer may reduce the dose to clear the photoresist material by two-thirds or greater. Accordingly, the throughput may be significantly increased according to embodiments of the invention.

Referring now toFIG. 3A, a cross-sectional illustration of pre-patterned features320formed into an interconnect layer300is shown. According to an embodiment, the interconnect layer300may include one or more different materials. For example, each surface of the pre-patterned features320illustrated inFIG. 3Ais formed from a different material. As illustrated, the first sidewall351, the second sidewall352, and the floor354are formed with a first material layer371, a second material layer372, and a floor material layer374, respectively. While the pre-patterned feature320is illustrated as having surfaces with three different materials, embodiments of the invention are not limited to such configurations. For example, the first and second sidewalls351,352may be formed from the same material. Additional embodiments may also include a floor material layer374, a first material layer371, and a second material layer372that are formed from the same material. According to an embodiment, the floor material layer374, and the first and second material layers371,372may be common materials used in semiconductor fabrication processes, such as, for example, Si, α-Si, oxides (e.g., SiO, TiO, AlO, etc.), nitrides (e.g., SiN, TiN, SiON, TaN, etc.), carbides (e.g., SiC, SiOC, carbon hardmask, etc.), or the like. In an embodiment, the floor material layer374may be a conductive material, such as a metal contact or an interconnect line of a lower interconnect layer. By way of example, the interconnect line may be copper, tungsten, or any other conductive material used in interconnect lines.

In an embodiment, a conformal bather layer341may be formed over one or more of the exposed surfaces of the pre-patterned feature320. As illustrated inFIG. 3A, the barrier layer341is a conformal layer that is formed over all of the surfaces of the pre-patterned feature320. While illustrated as a continuous layer, embodiments may also include barrier layers such as self-assembled monolayers (SAMs) or polymer brush layers (both described in greater detail below) that may not necessarily cover the entire physical surface of the pre-patterned feature320. However it is to be appreciated that the molecules forming the SAM or polymer brush are formed over the surfaces to a density sufficient to substantially eliminate the diffusion of species from the surfaces of the pre-patterned features320into the photoresist material. In an embodiment, the thickness of the barrier layer341may be less than approximately 5 nm. In an embodiment, the thickness of the barrier layer341may be between approximately 2 nm and approximately 3 nm. Certain embodiments may include a barrier layer341that has a thickness that is less than 1 nm.

In an additional embodiment, the barrier layer may be selectively formed over one or more surfaces of the pre-patterned feature320. For example, the barrier layer may be selectively formed over surfaces that are likely to cause substrate poisoning.FIG. 3Bis a cross-sectional illustration of such an embodiment. InFIG. 3Bthe floor354is not covered by a barrier layer341. In an embodiment, the barrier layer341may be selectively formed over the sidewalls and omitted from the floor because the floor354is a material that does not interact with the barrier layer341to form a bond.

Referring now toFIGS. 4A-4Ga process for patterning photoresist material422deposited in the pre-patterned feature420that includes a SAM barrier layer441is illustrated according to an embodiment of the invention. As illustrated inFIGS. 4A-4G, each molecule in the SAM barrier layer441is schematically illustrated as having a head group461and a chain462. The head group461is a functional group that may be selected so that the SAM barrier layer is selectively formed on surfaces that may cause negative interactions with the photoresist material. The chain462may be any suitable alkyl chain known in the art. In certain embodiments, the head group461may be a silane based molecule. Silane based molecules may be used to selectively form the SAM barrier layer441because the silane head group461readily reacts with hydroxyl groups on the surface of various interlayer dielectric materials to form covalent bonds. By way of example, the head group461may be one or more of alkoxysilanes, aminosilanes, halogen-terminated silanes, and the like.FIGS. 5A-5Fillustrate several exemplary SAMs that may be utilized in embodiments of the invention. InFIGS. 5A-5F“X” may be a halogen, such as Cl, Br, I, etc. and “R” may be CH3-, CH2CH2-, etc.

Referring now to the cross-sectional illustration inFIG. 4A, a SAM barrier layer441has been selectively deposited over the interconnect layer400, according to an embodiment of the invention. As illustrated, the barrier layer441may be selectively deposited over surfaces that are sources of substrate poisoning. For example, the barrier layer441may be formed over the first sidewall451and the second sidewall452of the pre-patterned feature420, and the floor454is not covered by the barrier layer441. In an embodiment, the barrier layer441may optionally be omitted from the floor because it is not a source of substrate poisoning. For example, the floor may be a metallic material. However, embodiments are not limited to such configurations, and embodiments may include a SAM barrier layer441that is also formed over the floor of the pre-patterned feature420.

According to embodiments of the invention, the SAM barrier layer441may be deposited over the interconnect layer400with processes such as spin-coating, vapor phase deposition, solution phase deposition (e.g., soaking), or the like. Additional embodiments may also include heating the interconnect layer400to provide additional energy to the system to assist in the formation of covalent bonds between the head group461and the surfaces of the pre-patterned features420. For example, the interconnect layer400may be heated from between room temperature to approximately 250° C., according to an embodiment.

In an embodiment, PAGs463may optionally be synthesized onto the chains462of the SAM barrier layer441, as illustrated inFIG. 4B. The PAGs463may be any PAG compound that includes a synthetic route to attach the PAG to the chain662. By way of example, the PAG may be tri-sulfonium triflate, bi-sulfonium triflate, mono-sulfonium triflate, diphenyl iodonium triflate, or any other known PAG molecule. The use of a PAG functionalized SAM barrier layer441allows for more flexibility in the design of the photoresist material. The presence of the PAGs on the barrier layer441allows for the concentration of PAGs in the photoresist material to be reduced. In an embodiment, the PAGs may be completely removed from the photoresist material. As such, problems in the design of the photoresist system attributable to the solubility limits of the PAGs in the photoresist resin may be avoided.

According to an embodiment, the PAGs may be synthesized onto the chains462prior to forming the SAM barrier layer441over the surfaces of the pre-patterned features420. In an additional embodiment, the PAGs463may be synthesized onto the chains462after the SAM barrier layer441including the head group461and the chain462are formed on the surfaces of the pre-patterned features420. While embodiments of the invention described in detail herein include the presence of a PAG functionalized SAM barrier layer441, embodiments of the invention are not limited to such configurations. According to additional embodiments, a SAM barrier layer441that is not functionalized with PAGs may also allow for the reduction or elimination of substrate poisoning. In such embodiments, the PAG may be present in the photoresist material only.

Referring now toFIG. 4C, a photoresist material422may be deposited over the interconnect layer400. As illustrated, the deposited photoresist material fills the pre-patterned features420. By way of example, the photoresist material420may be deposited with a spin-coating process. The presence of the barrier layer441prevents the diffusion of compounds from the surfaces of the pre-patterned feature420into the deposited photoresist material422.

The photoresist systems used may be compatible with DUV radiation, according to an embodiment. Additional embodiments may also include CAR systems. By way of example, the photoresist may be a t-BOC PHS resin system, an acetal system, an ESCAP system, or the like. While embodiments of the invention illustrate the use of a positive photoresist system, it is to be appreciated that a negative photoresist system may also be used according to embodiments of the invention.

Referring now toFIG. 4D, the portions of the interconnect layer400where a via is desired are exposed to radiation485from a radiation source (not shown). As illustrated, a mask480may be utilized to block the radiation from exposing pre-patterned features420where a via is not desired. By way of example, radiation from an electron-beam lithography tool or an EUV compatible system (e.g., a system that produces radiation with a 13.5 nm wavelength) may be used to cause the PAGs463of the SAM barrier layer441and/or the PAGs within the photoresist material442to “deblock” the blocking group and render the resin soluble in the developer (i.e., developable photoresist material423).

Referring now toFIG. 4E, the interconnect layer400is exposed to a developer and developable photoresist material423is removed. The developer may be any known developer, such as, for example, a TMAH developer. In an embodiment, the SAM barrier layer441may remain in the pre-patterned features420in which the developable photoresist material423has been removed. Accordingly, embodiments of the invention may also include a process to remove the barrier layer441. By way of example, the SAM barrier layer441may be removed with a high temperature burn off process or an ashing process subsequent to the removal of the developable photoresist material423.

In an embodiment, the unexposed photoresist material422remains after the interconnect layer400is developed. The unexposed photoresist material422remaining in pre-patterned features420may be modified so that it becomes a stable interlayer dielectric material, as illustrated inFIG. 4F. As used herein the modified photoresist material422may be referred to as photoresist424. For example, the unexposed photoresist may be cross-linked with a baking operation. In one such embodiment, the cross-linking provides for a solubility switch upon the baking. In an embodiment the cross-linked material has inter-dielectric properties and, may be retained in a final metallization structure.

Referring now toFIG. 4G, a conductive layer may be deposited into the exposed pre-patterned features420to form vias415, according to an embodiment. Such an embodiment may be useful when the floor is a contact or an interconnect line in a lower interconnect level. In an alternative embodiment, the floor may be etched through prior to depositing a conductive layer in order to expose a contact to a lower interconnect layer. For example, an etchstop layer (not shown) may be formed over a contact to a lower level.

The resulting structure illustrated inFIG. 4Gis shown in a perspective view inFIG. 4Hin order to more clearly illustrate certain aspects of the interconnect layer400. The conformal barrier layer441is omitted fromFIG. 4Hin order to more clearly illustrate certain aspects of the interconnect layer400. In an embodiment, the conductive layer may also extend above the pre-patterned features420and extend over the top surfaces of neighboring photoresist material424to from an interconnect line416. Accordingly, the via415allows for a contact to be made through the interconnect layer400from an interconnect line416, to a contact on a lower level. As illustrated, the resulting structure may include up to three different dielectric material regions (i.e., the first material layer471, the second material layer472, and the photoresist424), according to an embodiment. In one such embodiment, two or more of the first material layer471, the second material layer472, and the photoresist424are composed of a same material. In another such embodiment, the first material layer471, the second material layer472, and the photoresist424are all composed of different ILD materials. Accordingly, in certain embodiments, a vertical seam458between the first material layer471and the photoresist424, and/or a vertical seam459between the second material layer472and the photoresist424, and/or a vertical seam (not visible inFIG. 4H) between the first material layer471and the second material layer472may be observed in the final structure. According to an additional embodiment, the conformal barrier layer441may separate the photoresist424from the first material layer471and the second material layer472. In such embodiments, a vertical seam between the first material layer471and the conformal barrier layer441, and/or a vertical seam between the second material layer472and the conformal barrier layer441may be observed in the final structure.

According to an additional embodiment, the barrier layer may be a polymer brush barrier layer. In such an embodiment, the barrier layer may be formed of a plurality of polymer chains665that are each anchored to the exposed surfaces of the pre-patterned features. According to an embodiment, the molecular weight of the polymer brush may be approximately 10K or less. The polymer chains665used to form the polymer brush bather layer may be any polymer chain665that can be end-functionalized to bond with the surfaces of the interconnect layer. In an embodiment, monomers used to form the polymer chain may include styrenic monomers, acrylic monomers, methacrylic monomers and its derivatives, or the like. By way of example, the monomers used to form the polymer chains665may include methyl acrylate (MA), N,N-dimethylacrylamide (DMA), N,N-dimethylamino ethyl methacrylate (DMAEMA), styrene, methyl methacrylate (MMA), or the like. The polymer chains665extend outward from the exposed surfaces and provide a barrier to diffusion between the materials forming the interconnect layer a photoresist material that will be formed over the polymer brush barrier layer in a subsequent process. A process for using such a polymer brush barrier layer is illustrated with respect toFIGS. 6A-6C.

Referring now to the cross-section illustration inFIG. 6A, polymer chains665of the polymer brush barrier layer641are selectively deposited over the surfaces of the interconnect layer600, according to an embodiment of the invention. As illustrated, the polymer brush barrier layer641may be selectively deposited over surfaces that are sources of substrate poisoning. For example, the polymer brush barrier layer641may be formed over the first sidewall651and the second sidewall652of the pre-patterned feature620, and the floor654is not covered by the polymer brush barrier layer641. In an embodiment, the polymer brush barrier layer641may optionally be omitted from the floor because it is not a source of substrate poisoning. For example, the floor may be a metallic material. However, embodiments are not limited to such configurations, and embodiments may include a polymer brush barrier layer641that is also formed over the floor of the pre-patterned feature620in addition to one or more of the sidewalls.

According to an embodiment, the polymer chains665may be end-functionalized to selectively form a covalent bond to materials that may cause substrate poisoning. By way of example, the end-functionalization of the polymer chain may include functional groups such as hydroxyl, carboxyl, halogen, vinyl, thiol, phosphonic acid, amino, or alkyne groups. According to an additional embodiment, one or more functional groups may be distributed along the length of the polymer chain. In such an embodiment, a solution containing the end-functionalized polymer chains665may be spun-on over the surface of the interconnect layer600. Heat may optionally be applied to the interconnect layer600in order to provide enough energy to allow for chains to covalently bond to the surfaces of the interconnect layer600. Thereafter, excess material from the spun on solution may be rinsed from the interconnect layer600, leaving behind only the polymer chains665that were covalently bonded to the surfaces of the interconnect layer600.

Referring now toFIG. 6B, PAGs663may optionally be synthesized onto the polymer chains665of the polymer brush barrier layer641, as illustrated inFIG. 6B. The PAGs663may be any PAG compound that includes a synthetic route to attach the PAG to the polymer chain665. By way of example, the PAG may be tri-solfonium triflate, bi-solfonium triflate, mono-solfonium triflate, diphenyl iodonium triflate, or any other known PAG molecule. The use of a PAG functionalized polymer brush barrier layer641allows for more flexibility in the design of the photoresist material. The presence of the PAGs on the polymer brush barrier layer641allows for the concentration of PAGs in the photoresist material to be reduced. In an embodiment, the PAGs may be completely removed from the photoresist material. As such, problems in the design of the photoresist system attributable to the solubility limits of the PAGs in the photoresist resin may be avoided.

According to an embodiment, the PAGs may be synthesized onto the polymer chains665prior to forming the polymer brush barrier layer641over the surfaces of the pre-patterned features620. In an additional embodiment, the PAGs663may be synthesized onto the polymer chains665after the polymer brush barrier layer641is formed on the surfaces of the pre-patterned features620. While embodiments of the invention described in detail herein include the presence of a PAG functionalized polymer brush barrier layer641, embodiments of the invention are not limited to such configurations. According to additional embodiments, a polymer brush barrier layer641that is not functionalized with PAGs may also allow for the reduction or elimination of substrate poisoning. In such embodiments, the PAG may be present in the photoresist material only.

Referring now toFIG. 6C, a photoresist material622may be deposited over the interconnect layer600. As illustrated, the deposited photoresist material fills the pre-patterned features620. By way of example, the photoresist material620may be deposited with a spin-coating process. The presence of the barrier layer641prevents the diffusion of compounds from the surfaces of the pre-patterned feature620into the deposited photoresist material622. Accordingly, pre-patterned features620where vias are desired may be patterned without interference from substrate poisoning. Accordingly, the process of forming an interconnect line that is connected to a contact on a lower level may continue in substantially the same manner as described above with respect toFIGS. 4D-4H, and as such will not be repeated herein.

FIG. 7illustrates an interposer1000that includes one or more embodiments of the invention. The interposer1000is an intervening substrate used to bridge a first substrate1002to a second substrate1004. The first substrate1002may be, for instance, an integrated circuit die. The second substrate1004may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer1000is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer1000may couple an integrated circuit die to a ball grid array (BGA)1006that can subsequently be coupled to the second substrate1004. In some embodiments, the first and second substrates1002/1004are attached to opposing sides of the interposer1000. In other embodiments, the first and second substrates1002/1004are attached to the same side of the interposer1000. And in further embodiments, three or more substrates are interconnected by way of the interposer1000.

The interposer may include metal interconnects1008and vias1010, including but not limited to through-silicon vias (TSVs)1012. The interposer1000may further include embedded devices1014, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio-frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer1000.

In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer1000.

FIG. 8illustrates a computing device1200in accordance with one embodiment of the invention. The computing device1200may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, these components are fabricated onto a single system-on-a-chip (SoC) die rather than a motherboard. The components in the computing device1200include, but are not limited to, an integrated circuit die1202and at least one communication chip1208. In some implementations the communication chip1208is fabricated as part of the integrated circuit die1202. The integrated circuit die1202may include a CPU1204as well as on-die memory1206, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STTM-RAM).

Computing device1200may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory1210(e.g., DRAM), non-volatile memory1212(e.g., ROM or flash memory), a graphics processing unit1214(GPU), a digital signal processor1216, a crypto processor1242(a specialized processor that executes cryptographic algorithms within hardware), a chipset1220, an antenna1222, a display or a touchscreen display1224, a touchscreen controller1226, a battery1228or other power source, a power amplifier (not shown), a global positioning system (GPS) device1228, a compass1230, a motion coprocessor or sensors1232(that may include an accelerometer, a gyroscope, and a compass), a speaker1234, a camera1236, user input devices1238(such as a keyboard, mouse, stylus, and touchpad), and a mass storage device1240(such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The processor1204of the computing device1200includes one or more devices, such as transistors that are coupled to one or more interconnect lines that are formed in an interconnect structure that includes vias that are formed through pre-patterned features in an interconnect layer, according to an embodiment of the invention. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip1208may also include one or more devices, such as transistors that are coupled to one or more interconnect lines that are formed in an interconnect structure that includes vias that are formed through pre-patterned features in an interconnect layer, according to an embodiment of the invention.

In further embodiments, another component housed within the computing device1200may contain one or more devices, such as transistors that are coupled to one or more interconnect lines that are formed in an interconnect structure that includes vias that are formed through pre-patterned features in an interconnect layer, according to an embodiment of the invention.

Embodiments of the invention include a microelectronic device, comprising: one or more pre-patterned features formed into a interconnect layer, wherein the one or more pre-patterned features are defined by at least a first wall, a second wall, and a floor; a conformal barrier layer formed over the first wall, and the second wall of one or more of the pre-patterned features; a photoresist layer formed over the barrier layer and within one or more of the pre-patterned features; and a conductive via formed in at least one of the pre-patterned features. An additional embodiment of the invention includes a microelectronic device, wherein the conformal barrier layer is a self-assembled monolayer (SAM) barrier layer or a polymer brush barrier layer. An additional embodiment of the invention includes a microelectronic device, wherein the conformal barrier layer is a SAM barrier layer, and wherein each molecule of the SAM barrier layer includes a head group and a chain. An additional embodiment of the invention includes a microelectronic device, wherein the head group is a silane head group and the chain is an alkyl chain. An additional embodiment of the invention includes a microelectronic device, wherein the silane head group is an alkoxysilane, aminosilane, or a halogen-terminated silane. An additional embodiment of the invention includes a microelectronic device, wherein the conformal barrier layer is a polymer brush barrier layer, and wherein the polymer brush barrier layer is formed from polymer chains that include one or more of styrenic monomers, acrylic monomers, or methacrylic monomers and derivatives thereof. An additional embodiment of the invention includes a microelectronic device, wherein each molecule of the SAM barrier or each polymer chain of the polymer brush bather layer further includes a photoactive component. An additional embodiment of the invention includes a microelectronic device, wherein the photoactive component is a photoacid generator (PAG). An additional embodiment of the invention includes a microelectronic device, wherein the first wall is formed with a first material, the second wall is formed with a second material, and the photoresist is formed with a third material, and wherein the first material, the second material, and the third material are different from each other. An additional embodiment of the invention includes a microelectronic device, wherein a seam is formed between the first material and the second material, and a seam is formed between the first material and the third material, and a seam is formed between the second material and the third material. An additional embodiment of the invention includes a microelectronic device, wherein the via electrically couples a first interconnect line formed in the interconnect layer to a second interconnect line formed in a second interconnect layer that is below the interconnect layer. An additional embodiment of the invention includes a microelectronic device, wherein the via electrically couples a first interconnect line formed in the interconnect layer to an electrical contact on a substrate formed below the interconnect layer. An additional embodiment of the invention includes a microelectronic device, wherein the conformal barrier layer is also formed over the floor of one or more of the pre-patterned features. An additional embodiment of the invention includes a microelectronic device, wherein the pre-patterned features are 2D pre-patterned features. An additional embodiment of the invention includes a microelectronic device, wherein the pre-patterned features are 1D pre-patterned features.

An additional embodiment of the invention includes a method of forming a microelectronic device, comprising: forming a conformal barrier layer over one or more surfaces of a pre-patterned feature in an interconnect layer; disposing a photoresist material over the barrier layer within the pre-patterned features; exposing the photoresist material in one or more of the pre-patterned features with a radiation source; and developing the exposed photoresist material. An additional embodiment includes a method of forming a microelectronic device, wherein the conformal barrier layer is a self-assembled monolayer (SAM) barrier layer. An additional embodiment includes a method of forming a microelectronic device, wherein the SAM barrier layer is formed over one or more surfaces of the patterned feature with a spin-coating process, a vapor phase deposition process, or a solution phase deposition process. An additional embodiment includes a method of forming a microelectronic device, wherein the conformal barrier layer is a polymer brush bather layer. An additional embodiment includes a method of forming a microelectronic device, wherein the conformal barrier layer is formed over one or more surfaces of the pre-patterned feature with a spin-coating process. An additional embodiment includes a method of forming a microelectronic device, wherein the conformal barrier layer is functionalized with a photoacid generator (PAG). An additional embodiment includes a method of forming a microelectronic device, further comprising: cross-linking the unexposed photoresist material; and depositing a conductive material over the interconnect layer to form one or more vias and one or more interconnect lines.

An additional embodiment includes a method of forming a microelectronic device, comprising: forming a plurality of pre-patterned features in an interconnect layer, wherein each pre-patterned feature includes at least a first wall, a second wall, and a floor; forming a conformal barrier layer over the first wall, and the second wall of one or more of the pre-patterned features; functionalizing the barrier layer with photoacid generators (PAGs); disposing a photoresist material over the barrier layer within the pre-patterned features; exposing the photoresist material in one or more of the pre-patterned features with a radiation source; developing the exposed photoresist material to remove the photoresist material to expose one or more of the pre-patterned features; removing the conformal barrier layer from the exposed pre-patterned features; disposing a conductive material into the exposed pre-patterned features to form one or more conductive vias; and forming an interconnect line above the one or more conductive vias. An additional embodiment includes a method of forming a microelectronic device, wherein the conformal barrier layer is a self-assembled monolayer (SAM) barrier layer or a polymer brush barrier layer. An additional embodiment includes a method of forming a microelectronic device, wherein the first wall is formed with a first material, the second wall is formed with a second material, and the photoresist is formed with a third material, and wherein the first material, the second material, and the third material are different from each other, and wherein a seam is formed between the first material and the second material, and a seam is formed between the first material and the third material, and a seam is formed between the second material and the third material.