Current steering digital to analog converters with self-calibration, and systems and methods using the same

A current steering digital to analog converter includes a current source for selectively providing a selected amount of current to an output in response to input data. The current source includes a selected number of sub-current sources for selectively providing fractions of the selected amount of current to the output. Compensation current sources each provide a selected amount of compensation current to the output. Compensation control circuitry, in response to the input data, selectively activates and de-activates selected ones of the sub-current sources and the compensation current sources to provide current compensation at the output.

FIELD OF INVENTION

The present invention relates in general to digital to analog conversion techniques, and in particular, segmented current steering digital to analog converters with self-calibration, and systems and methods using the same.

BACKGROUND OF INVENTION

High performance digital to analog converters (DACs), such as those utilized in digital video encoder systems, typically must support a digital input resolution of twelve (12) or fourteen (14) bits, and clocks speeds In excess of 100 MHz. One very popular DAC architecture, utilized in such high performance applications, is the segmented current steering DAC. Generally, in a segmented current steering DAC, current elements are partitioned into segments, with at least one of the segments controlled by thermometer-encoded data, such that within that segment, the current elements are equally weighted. Advantageously, thermometer encoding and equally weighted current elements help minimize some types of non-linearities.

On the other hand, segmented current steering DACs require a significant amount of chip area. For example, fifteen (15) thermometer-encoded bits are required to represent four (4) binary bits. Hence, a current steering segment converting four (4) binary bits into an analog signal, after thermometer encoding, requires fifteen (15) current elements.

Additionally, most conventional high resolution DACs require that a much higher unit cell area be utilized during device fabrication to reduce random mismatch, and/or sophisticated cell randomization circuitry to reduce gradient mismatch errors. The result is an increase in device chip area and increased circuit complexity. A few reported DACs use calibration methods which are complex and consume high silicon area.

Given the importance of reducing chip-area in order to fabricate economical and efficient DACs, new techniques are required for performing on-chip calibration to compensate for differences between current steering cells in current steering DACs. These techniques also should not significantly increase the overall area and complexity of the embodying DAC, without adversely impacting performance. In particular, these techniques should be particularly applicable to high-resolution segmented current steering DACs, although not necessarily limited thereto.

SUMMARY OF INVENTION

The principles of the present invention are embodied in circuits and methods from compensating for output current errors in current steering DACs. In one particular embodiment, a current steering digital to analog converter is disclosed which includes a current source for selectively providing a selected amount of current to an output in response to an input bit. The current source includes a selected number of sub-current sources for selectively providing fractions of the selected amount of current to the output. Compensation current sources each provide a selected amount of compensation current to the output. Compensation control circuitry, in response to the input data and a stored pre-calculated compensation value, selectively activates and de-activates selected ones of the sub-current sources and the compensation current sources to provide current compensation at the output.

The principles of the present invention realize a number of significant advantages, especially when applied to segmented current steering DACs. For example, the additional analog and digital circuitry required to implement the inventive calibration techniques are low in complexity. Additionally, existing current sources within a current steering DAC are reused, further minimizing the overall size and complexity of the DAC. To further reduce chip-area, the channel width and channel length of the various cells are selected to provide the required currents, while minimizing the sizes of the corresponding current sources. Furthermore, no complex real-time correction computations must be executed. Moreover, calibration circuitry embodying the present invention may be shared across several DACs on chip, if needed. In sum, circuits, systems, and methods embodying the principles of the present invention are both operationally and chip-area efficient.

DETAILED DESCRIPTION OF THE INVENTION

The principles of the present invention and their advantages are best understood by referring to the illustrated embodiment depicted inFIGS. 1–4of the drawings, in which like numbers designate like parts.

FIG. 1is a diagram of an exemplary single-chip video encoder100suitable for describing the principles of the present invention. Video encoder100includes a standard definition processing engine101and a progressive scan-processing engine102.

Standard definition processing engine101receives standard definition input data (SD VIDEO) and associated synchronization signals (SD SYNCS), through input demultiplexer (demux)103, in either of the CCIR-601 or CCIR-656 International Radio Consultative Committee standard formats, and outputs either National Television Systems Committee (NTSC), phase alternation line (PAL), or red-blue-green (RGB) format video data. Progressive scan processing engine102inputs either 4:2:2: or 4:4:4 YCbCr format video data (PS VIDEO) and associated synchronization signals (PS SYNCS) through demux103, and outputs video data in either of the YPbPr or RGB video formats. An internal progressive scan to standard definition (PS-to-SD) converter104supports the conversion of progressive scan video data into standard definition video data for processing by standard definition processing engine101.

Video encoder105includes a block of six (6) digital to analog converters (DACS)105, which supports various output configurations. Depending on the output configuration, an output multiplexer (mux)106switches the video data from either standard definition processing engine101and/or progressive scan processing engine102to the required DACs of DAC block105.

Control of video encoder100is implemented through an I2C and SPI interface107and control register108. Timing is implemented on-chip with a phase-locked loop (PLL)109in response to a received clock signalCLK. Video encoder also includes a current reference110and a bandgap reference111for generating a reference voltageVREF.

FIG. 2is a block diagram of an exemplary segmented current steering DAC200according to the principles of the present invention. DAC200is particularly suitable for utilization in DACs105of video encoder100ofFIG. 1, although there are numerous other applications of current steering DACs embodying the inventive concepts.

In the illustrated embodiment, DAC200is a fourteen-bit current steering DAC which is segmented into a most significant bits (MSB) segment201representing four (4) binary input bits, a mid-range (significant) bits (MID) segment202representing four (4) mid-range (significant) binary input bits, a least significant bits (LSB) segment203representing two (2) least significant binary input bits, and a fourth segment204representing two (2) least significant input bits and two (2) fractional binary input bits, along with a one-half calibration bit. The number of binary input bits, N, may change from the fourteen (14) utilized in the present example, depending on the desired resolution of DAC200.

MSB segment201includes fifteen (15) equally-weighted current sources (M1–M15)205a–205o. Each MSB current source205a–205ois controlled by one (1) of fifteen (15) thermometer encoded bits XM(0)–XM(15), and outputs a nominal current32I, in which I is a selected unit reference current. In the illustrated embodiment, each MSB current source205a–205ois fabricated from a MSB unit cell UcellM, in which UcellM generates sixteen (16) times the current of the LSB unit cell UcellL, discussed below.FIG. 2Cgenerally illustrates the conversion of four (4) binary bits DMSBinto fifteen (15) thermometer encoded bits XM(0)–XM(15). During calibration, MSB current sources205a–205oare controlled by the corresponding control signals S1–S15.

InFIG. 2C, the four (4) binary input MSBs, DMSB, are thermometer encoded by thermometer encoder225into fifteen (15) thermometer-encoded bits XM(1)–XM(15). Similarly, the four (4) binary input mid-range bits, DLSMBare thermometer encoded by thermometer encoder226into fifteen (15) thermometer-encoded bits XLM(1)–XLM(15). The thermometer-encoded bits XM(1)–XM(15)ANDXLM(3)–XLM(17) are latched in a set of latches227. The four (4) binary LSB input bits Dlsbl and two (2) binary fractional bits DFRAC, are directly latched in latches228as bits XLL(1)–XLL(4) and XF(1)–XF(2), respectively. A register229, indexed by bits DMSB, stores correction valuesCAL—REG, discussed in detail below. In conjunction with logic230and latch231, the indexed value ofCAL—REGgenerates a set of control signals E+(1)toE+(6) and E−(0) to E−(6).

An electrical schematic of a representative cell structure300, suitable for constructing either MSB unit cells UcellM or LSB unit cells UcellL, is shown inFIG. 3. InFIGS. 2 and 3, the designations i1and i2represent the current source/unit cell calibration control and data inputs, respectively, and the designations o1and o1represent the current source/unit cell calibration control and data outputs, respectively. As shown inFIG. 2B, each cell is represented by a current source220, outputting a current xl, in which X is the current weight shown inFIG. 2A. During normal operations, the corresponding input bit at input i2switches the current xl to the DAC200output lout ofFIG. 2, through switch222and the output o2. During calibration, the current xl is switched by the complement of the input bit at input i2through switch221and by the corresponding control signal at input i1to the output o1. LSB unit cells UcellL, whose nominal value is equal to I/8, are constructed from MOSFETs having a reference channel width W and a reference channel length L, such that the lower ten (10) bits of DAC200have the required linearity without calibration. MSB unit cells UcellM forming MSB current sources205a–205oare fabricated from MOSFETs each having a channel width to channel length ratio of (8W)/(L/2) to save overall chip area. In other words, the channel width to length ratio W/L for the UcellM transistors is sixteen (16) times the width to length ratio W/L of the UcellL transistors, although, the chip-area of each UcellM is just four (4) times that of UcellL, as the channel length L for UcellM transistors is half that of the channel length L for UcellL transistors.

MID segment202ofFIG. 2Aincludes fifteen (15) current sources (L3–L17)206a–206o, controlled by the fifteen (15) thermometer encoded input bits XLM(3)–XLM(17) ofFIG. 2C. These fifteen thermometer-encoded bits represent four (4) mid-range binary bits DLSBM, also as shown inFIG. 2C. Each MID current source206a–206ois fabricated from sixteen (16) LSB unit cells UcellL, and outputs a nominal current of2l. During calibration, MID segment203current sources (L3–L17)206a–206oare controlled by the CALcontrol signal.

Segment203includes two (2) LSB current sources (L1–L2)207a–207brespectively fabricated by eight (8) and four (4) LSB unit cells UcellL. During normal operation, LSB current sources207a–207bare under the control of binary encoded bits XLL(3)–XLL(4). Current sources207a–207boutput nominal currents of I and1/2I, respectively. During calibration, LSB segment current sources (L1–L2)207a–207bare controlled by the control signal Cal.

Segment204includes current sources (F0–F4)208a–208e, which are controlled, during normal operation, by binary encoded bitsXLL(2)–XLL(1) and XF(1)–XF(2). current sources208a–208eare fabricated from two (2), one (1), one-half (0.5), one-quarter(0.25) and one eighth (0.125) LSB unit cells UcellL, respectively. Current sources208a–208eoutput nominal currents of I/4, I/8, I/16, I/32, and I/64. During calibration, segment current sources (F0–F4)208a–208eare controlled by the c+(0)–c+(4) control signals.

First MSB current source (M1)205a, which nominally outputs a current of32I, includes six (6) sub-current sources (E1–E6)209a–209foutputting a nominal currents of I/32, I/16, I/8, I/4, I/2, I in response to binary weighted bitsE−(1)–E−(6), and a current source210, which outputs a nominal current of30I in response to thermometer encoded bit XM(1), during normal operation. Current source (E0)211, controlled by binary bit E−(0), allows DAC200to operate with two's complement data inputs, without the need of digital adder logic, as discussed further below.

Calibration current sources (D1–D6)212b–212gprovide weighted currents of I, I/2, I/4, I/8, I/16, I/32in response to the control signalsE+(1)–E+(6) during normal operation. During calibration, theC−(0)–C−(4) control signals control calibration current sources D0–D4212a–212e. A current source213(Dext), having a current weight of I/64is provided for two's complement operations under control of the C-EXTcontrol signal during normal operation.

During the calibration routine discussed below, current mirror214and current comparator215compare the current IX, which is the current IMSBifrom the active current source (M1–M15)205a–205o, during a corresponding calibration iteration, as selected by the corresponding control signalS1–S15, with the current IY. IYis nominally equal to the sum of the calibration current ICALand the currents IIsbs, from MID current sources (L3–L17)206a–206o, LSB current sources (L1–L2), fractional current sources208a–208e, and a dummy current source217. Dummy current source217ensures that, nominally, IIsbsis equal to the nominal Imsbcurrent of32I.

Calibration logic216receives the output of current comparator214CMP, the Cal calibration control signal, a test signal CAL—DIS—TEST, and the CLK—CALcalibration clock signal. During calibration, calibration logic216generates theS1–S15,E−(1)–E−(6),E+(0)–E+(6),C−(0)–C−(4),C+(0)–C+(4),A, B, andC−(extra) control signals.

Calibration generally proceeds as follows. One particular routine for performing calibration is discussed in detail below in conjunction withFIG. 4. For each control signalsS1–S15, the current IXis generated by activating the corresponding MSB current source205a–205o. Current mirror214and current comparator215then compare the currents IXand IY. If the current IXis greater than the current IY, one or more current sources (D0–D4)212a–212eare turned on with the control signals C−(0)–C−(4) to make the IXand IYcurrents nominally equal. Alternatively, if the current IXis less than the current IY, one or more of current sources (F0–F4)208a–208eare turned off, by selectively deactivating the control signals C+(0)–C+(4), to make the currents IXand IYnominally equal. The correction required for the current control signalS1–S15is determined from two such readings of the currents IXand IY, by swapping the current mirror214inputs using switches A and B, and taking the average of the two readings,CAL—REQDiin which i is an index from 1 to 15. The two readings cancel any mirror mismatch within current mirror214and comparator offset within current comparator215. Advantageously, the calibration control signalsC−(0)–C−(4) andC+(0)–C+(4), need not be latched, as the settled values of the currents IXand IYare the only values of importance.

This process is repeated for until all current sources haveS1–S15have been tested, to derive correction values for all permutations of the four (4) binary input MSBs, DMSB. Total error correction required for any four-bit MSB binary code with index i=1 to 15 is stored in a calibration registerCAL—REGi. Advantageously, the values ofCAL—REGiare pre-computed during calibration phase, such that no real-time-computation of correction values is needed during normal operation. Subsequently, during normal operation, current sources (D6to D1)212a–212fand current sources (E1–E6)209a–209fare used to correct for the −ve and +ve errors as per data stored in the calibration registerCAL—REGiutilizing the E+ and E− control signals.

FIG. 3is a flow chart illustrating a representative procedure300for generating the calibration values generally described above. At block301, for the first binary MSB value, with index i, i=1 to 15, the control signal S1is activated. In other words, control signal S1is active and control signals S2–S15are inactive. Consequently, MSB current source205aofFIG. 2is on and providing the current IX, and MSB current sources205b–205oare off. Additionally, for the first MSB input bit, the register cal_reg_last is cleared, at Block301.

At block302, switch A of current mirror214is closed and switch B is opened, for the first of the two calibration measurements to be performed for the first current source205a. At block303, the current IXis generated from current source201aactivated by the asserted control signal S1.

A counter, timed by the signal CLK—CALofFIG. 2A, starts to count from −32 to 31 to sequence the assertion of the control signals C+(0)–C+(4) and C−(0)–C−(4). With each count, the new set of asserted control signals C+(0)–C+(4) and C−(0)–C−(4) activate a new combination of fractional bit current sources208a–208dand/or calibration current sources212a–212dto generate a new value of current IY. For example, when the current counter value CNTR is minus thirty-two (−32), all fractional current sources (F0–F4)208a–208eand all calibration current sources (D0–D4)212a–212dare on and contributing to the current IY. When the current counter valueCNTRis zero (0), all fractional current sources (F0–F4)208a–208eare turned-on, but all calibration current sources (D0–D4)212a–212dare turned-off. Finally, when the current counter value CNTR is plus thirty-one (31), then all fractional current sources (F0–F4)208a–208eare turned-off and all calibration current sources (D0–D4)212a–212dare turned-off.

With each new current IYgenerated, a comparison is made at block305with the current IX, until the output of comparator215transitions from a logic zero (0) to a logic one (1). At the transition point of the output of comparator215, the currents IXand IYare nominally equal. Therefore, at block306, a registerCAL—REQA is set to the counter value CNTR at the transition point, which represents the number of half LSBs of correction current required in the current IMSBi

Next, a second set of measurements between the currents IXand IYcommences at block307, at which point the switch A opens and switch B closes to reverse the inputs into current mirror214. The process described above in regard to blocks304and305is then repeated at blocks308and309, with the exception that the transition point is detected when the output of comparator215transitions from a logic one (1) to a logic zero (0).

At block310, the register valueCAL—REG1is calculated as:
CAL—REG1=round_to_—7bits(CAL—REG—LAST+CAL—REQDA+(CNTR),
in whichCAL—REG—LAST, for the first iteration is zero (0), as set at block301,COR—REQDA is the register value set at block306, andCNTRis the counter value at the transition at block309.

For current source Si, theCAL—REG—LASTregister stores a value representing the accumulated error for all previously calibrated current sources up to current source Si-1. The running value in theCAL—REG—LASTregister is stored at full precision, to reduce error accumulation as calibration procedure300iterates from current source S1to current source S15. The correction values for each input MSB are stored in theCAL—REG(I) register with a lower precision, preferably by rounding the lower two (2) LSBs, as per overall performance goals.

If at decision block312the index i has not reached fifteen (15), then at block313, the current value ofCAL—REGiis taken and stored in register as the correction code for binary MSB input code i. At block314, the index i is incremented and the next MSB current source205a–205ois activated by the corresponding control signal S1–S15. The current source or sources205a–205ofor the just-completed iteration is deactivated. Procedure300returns to block302for the next iteration.

If at decision block312, the index i has reached fifteen (15), then the valueCAL—REG15 is stored at the correction could for MSB input code fifteen (15) and procedure300is complete.

FIG. 4is a flow chart illustrating a preferred procedure400which describes the correction operations dynamically performed by calibration logic216ofFIG. 2Aduring normal mode operations of DAC200ofFIG. 2A. At block401, the current four-bit bit MSB code DMSB=K, prior to thermometer-encoding, accesses the corresponding correction codeCAL—REGKfrom registerCAL—REGK, in which k=i, as previously determined by procedure300described above in conjunction withFIG. 3.

At block402a determination is made as to whether the valueCAL—REGKis greater than zero (0), which indicates that positive correction is needed by adding an appropriate number of current sources. If is greater than zero (0), then at block403, the signals E−(0)–E−(6) are all asserted, such that a current sub-elements209a–209fturn-on. At block404control signals E+(1)–E+(6) are asserted to equal the bits of correction codeCAL—REGKto turn-on the corresponding correction current sources212a–212f. As a result,CAL—REGKnumber of LSB unit currents are added to the output IOUTofFIG. 2. At block405, calibration logic216waits for the next input word Dmsb.

If the correction codeCAL—REGKis lesser than or equal to zero (0) at block402, then at block406the control signals E+(1)–E+(6) are all de-asserted and all calibration current sources212a–212fturn-off. At the same, time the signals E−(0)–E−(6) are asserted equal to the bits ofCAL—REGKto deactivate a corresponding number of sub-current sources209a–209f. In this case, a current ofCAL—REGKnumber LSB unit currents are subtracted from the output Iout. Advantageously, 2's complement operation is achieved without adder logic utilizing current source (E0)211. At block403, calibration logic216waits for the next input word.

The principles of the present invention realize a number of significant advantages. For example, the only analog circuitry required to implement the calibration circuitry is a very low-complexity current mirror—current and comparator circuitry. In other words, no operational amplifier or switched-capacitor circuits are necessary. Additionally, the implementation of the correction and calibration reuses most of the existing current sources in the DAC thereby minimizing chip area. This feature is unlike the known art in which dedicated correction DACs are utilized for every current source which is calibrated. Furthermore, the straightforward incrementation approach to calibration simplifiers the digital design. Also, in the illustrated embodiment discussed above, the need to latch calibration related control signals is eliminated, which additionally saves chip area.

Advantageously, the pre-calculation and storage of correction values for the MSB codes are performed directly prior to normal operation of DAC200, instead of on an individual MSB current source basis, which eliminates the need to perform complex real-time correction computations. Also, in the illustrated embodiment, the conventional adder logic normally required for 2's complement operation is eliminated using extra current source (E0)211, which improves the speed of operation and saves chip area. The inventive principles may be applied to any conventional segmented DAC. Finally, the calibration circuitry discussed above may be shared across several DACs on chip, if needed.

It is therefore contemplated that the claims will cover any such modifications or embodiments that fall within the true scope of the invention.