Semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack, a semiconductor device package and an electronic apparatus including the semiconductor chip

A semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack thereof, a semiconductor device package thereof, and an electronic apparatus having the same are disclosed. The semiconductor chip comprising, a substrate including an inner semiconductor circuit, a conductive redistribution structure formed on the substrate including a conductive redistribution interconnection and a conductive redistribution via plug, wherein the redistribution via plug is connected to the inner semiconductor circuit; a conductive chip pad formed on the substrate, and a conductive chip via plug configured to penetrate the substrate and electrically connected to the redistribution structure.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119(a) from Korean Patent Application No. 10-2008-0082516, filed Aug. 22, 2008, the contents of which are hereby incorporated herein by reference in their entirety.

BACKGROUND

1. Field of the Invention

Exemplary embodiments relate to a semiconductor chip, a semiconductor chip stack, a semiconductor device package, and an electronic apparatus including the semiconductor chip.

2. Description of the Related Art

In order to improve integration density, capacity and operating speed of a semiconductor device, a method of stacking a plurality of semiconductor chips has been suggested.

SUMMARY

Example embodiments provide a semiconductor chip including a chip via plug penetrating a substrate.

Exemplary embodiments also provide a semiconductor stack of a plurality of semiconductor chips including a semiconductor chip including a chip via plug penetrating a substrate.

Exemplary embodiments further provide a semiconductor device package including a semiconductor chip including a chip via plug penetrating a substrate.

Exemplary embodiments further provide an electronic apparatus including a semiconductor chip including a chip via plug penetrating a substrate.

According to exemplary embodiments, a semiconductor chip includes a substrate including an inner semiconductor circuit, a conductive redistribution structure formed on the substrate including a conductive redistribution interconnection and a conductive redistribution via plug, wherein the redistribution via plug is connected to the inner semiconductor circuit; a conductive chip pad formed on the substrate, and a conductive chip via plug configured to penetrate the substrate and electrically connected to the redistribution structure.

According to other exemplary embodiments, a semiconductor chip includes a substrate including an inner semiconductor circuit, a conductive redistribution structure formed on a surface of the substrate and electrically connected to the inner semiconductor circuit through a conductive redistribution via plug, and a conductive chip via plug penetrating the substrate, the chip via plug connected to the redistribution structure.

According to still other exemplary embodiments, a semiconductor stack includes a first semiconductor chip, and a second semiconductor chip stacked on the first semiconductor chip, wherein each of the semiconductor chips comprises, a substrate including an inner semiconductor circuit, a conductive redistribution structure formed on the substrate including a conductive redistribution interconnection and a conductive redistribution via plug, wherein the redistribution via plug is connected to the inner semiconductor circuit, a conductive chip pad formed on the substrate, and a conductive chip via plug configured to penetrate the substrate and electrically connected to the redistribution structure, wherein the chip via plug and the chip pad are aligned each other, and wherein the chip via plug of the first semiconductor chip is electrically connected to the chip via plug of the second semiconductor chip.

According to still other exemplary embodiments, a semiconductor device package may include a first semiconductor chip disposed on a package substrate, and a second semiconductor chip stacked on the first semiconductor chip, wherein each of the semiconductor chips comprises, a substrate including an inner semiconductor circuit, a conductive redistribution structure formed on the substrate including a conductive redistribution interconnection and a conductive redistribution via plug, wherein the redistribution via plug is connected to the inner semiconductor circuit, a conductive chip pad formed on the substrate, and a conductive chip via plug configured to penetrate the substrate and to electrically connect to the redistribution structure, wherein the chip via plug of the first semiconductor chip is electrically connected to the chip via plug of the second semiconductor chip, and the chip via plug of the first semiconductor chip is electrically connected to a package substrate pad of the package substrate.

According to still other exemplary embodiments, an electronic apparatus may include a function unit to perform a function thereof, and an semiconductor chip connected to the function unit to control the function, and comprising, a substrate including an inner semiconductor circuit, a conductive redistribution structure formed on a surface of the substrate and electrically connected to the inner semiconductor circuit through a conductive redistribution via plug, and a chip via plug penetrating the substrate, the chip via plug connected to the redistribution structure, wherein one of the chip via plug and the redistribution structure is electrically connected to the function unit.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various exemplary embodiments will now be described more fully with reference to the accompanying drawings in which some exemplary embodiments are shown. This inventive concept may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. These embodiments are provided to ensure that this disclosure is thorough and fully enables those skilled in the art to embody and practice the inventive concept. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity. It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate or intervening layers may also be present. Throughout the drawings, like elements are denoted by like reference numerals.

Exemplary embodiments in this specification will be described with reference to plan views and cross-sectional views of the inventive concept. Therefore, the exemplified drawings may vary according to a fabrication technique and/or an allowable error. Therefore, the exemplary embodiments of the inventive concept are not limited to a specific shape, but include a change in shape that is caused according to a fabrication process. Accordingly, regions illustrated in the drawing are schematic, and the shapes thereof exemplify a specific shape of a device, but are not limited thereto.

In this specification, a semiconductor chip may be construed as being in a wafer state, a semiconductor package may be construed that a plurality of semiconductor chips in a wafer state are electrically connected to each other to be packaged, and a semiconductor device or semiconductor device package may be interpreted that it can be mounted on a substrate including PCB or a module substrate.

“Being electrically connected” may be construed as being serially connected. That is, it may be interpreted that a conductor is physically connected to another conductor. On the other hand, “being electrically insulated” may be construed as being serially insulated. That is, it may be interpreted that a conductor is not directly connected to another conductor, and an insulating material may be interposed therebetween. Therefore, “being electrically connected” or “being electrically insulated” may refer to or exclude alternate connection or insulating. That is, insulating is constituted in series, and connection is constituted alternately. In this point of view, “being connected” may be interpreted as “being coupled” in this specification.

“Vias” may be conductors to transmit electric signals in vertical direction, “interconnections” may be conductors to transmit electric signals in horizontal direction and “pads” may be plane shaped conductors to connect two conductors between thereof.

FIGS. 1A and 1Bare cross-sectional views of semiconductor device packages according to exemplary embodiments of the inventive concept.

Referring toFIG. 1A, a semiconductor device package100according to an exemplary embodiment of the inventive concept includes a plurality of semiconductor chips120stacked on a first package substrate110, chip bumps130electrically connecting the semiconductor chips120to each other, and at least one chip via plugs140penetrating the semiconductor chips120.

InFIG. 1A, it is assumed that it is illustrated that a chip pad (not illustrated) of each semiconductor chip120is formed in the center portion. In the drawing, it is illustrated that just one semiconductor chip120includes just one chip via plug140, and just the chip bumps130corresponding to the illustrated chip via plugs140are illustrated for clarity. However, actually, a plurality of chip via plugs140may be formed on the each semiconductor chip120, and a plurality of chip bumps130may be formed as well.

While it is illustrated that a semiconductor device package100includes four stacked semiconductor chips120, it should not be limited thereto. That is, two semiconductor chips120may be stacked, or eight or more semiconductor chips120may be stacked. For clarity, cases in which four semiconductor chips120are stacked are illustrated in the drawing.

The chip via plugs140are included in each semiconductor chip120, and may be formed to penetrate each semiconductor chip120. Therefore, each of the semiconductor chips120may be disposed to have an active plane either in an upward direction or in a downward direction. In the exemplary embodiment, the active planes of the semiconductor chips120are not regarded as being in a specific direction. For example, when the chip via plugs140are formed to correspond to all chip pads of the semiconductor chips120, every input/output path of the semiconductor chips120is formed through the chip via plugs140. In this case, the active plane of the semiconductor chips120may be stacked in a downward direction, i.e., in the direction of the first package substrate110. The active plane may be one of surfaces (sides) of the semiconductor chips120through which an inner semiconductor circuit can be communicate with an external circuit disposed outside the semiconductor chips120. It is possible that the active plane may be a plane formed on the semiconductor chips120to provide a plurality of communication paths between the inner semiconductor circuit and one or more external circuits.

However, when the chip via plugs140are not formed to correspond to all chip pads of the semiconductor chips120, electrical connection through the chip via plug140and electrical connection through a bonding wire may be simultaneously applied. In this case, disposing the active planes of the semiconductor chips120in an upward direction may facilitate the assembly process of a semiconductor device package. Therefore, the direction of the active planes of the stacked semiconductor chips120are not limited regardless of the direction illustrated in the drawing.

The chip bumps130may electrically connect the chip via plugs140of the semiconductor chips120different from each other. Specifically, the chip bumps130may electrically connect the chip pads of the different semiconductor chips120to the chip via plugs140or electrically connect the chip pads to the other chip pads. The detailed description thereof will be provided below.

The chip bumps130may be an extended part of the chip via plugs140, a chip pad of the semiconductor chip120or a part of a redistribution structure. Alternatively, the chip bumps130may be formed of a separate element. For example, the chip bumps130may be formed in the shape of a hexahedron, a polyhedron, a ball, etc.

The chip via plugs140of the semiconductor chips120disposed at a bottommost portion or the chip bumps130disposed therebelow may be electrically connected to a package substrate bump170. In the exemplary embodiment, it is illustrated that the chip bumps130are electrically connected to package substrate pads160of the first package substrate110through a package substrate hole150. In particular, it is illustrated that the chip bumps130are connected to the package substrate pads160through a wire165.

The package substrate pads160may be electrically connected to the package substrate bumps170through a package substrate interconnection that is not shown. In the drawing, it is illustrated that the package substrate bump170is in the shape of a ball. The package substrate bumps170may be variously formed in terms of shape according to each specification, and in particular, when a chip socket or a module socket is used, since the shape is not restricted, the illustrated package substrate bump170in the shape of a ball is not a restricted element, and should be understood as an example. The detailed description of the first package substrate110will be provided below.

In the exemplary embodiment, the chip via plugs140may electrically connect the package substrate bumps170or the chip pads of the semiconductor chips120that function the same. For example, the chip via plugs140may be electrically connected to the package substrate bumps170or the chip pads of the semiconductor chips120that function as supply voltage nodes (i.e. Vdd node or power nodes). Alternatively, the chip via plugs140may be electrically connected to the package substrate bumps170or the chip pads of the semiconductor chips120that function as ground voltage nodes (i.e. Vss nodes or ground nodes). While the chip via plugs140may connect the chip pads of the semiconductor chips120having various functions and the package substrate bumps170, it is illustrated that the chip via plugs140connect the package substrate bumps170and the chip pads for supplying a supply voltage or a ground voltage. However, it is not limited that the chip via plugs are connected to the package substrate bumps170and the chip pads for supplying a supply voltage or a ground voltage. The detailed descriptions of the shape and structure of the chip via plugs140will be provided below.

The chip via plugs140is connected to an inner semiconductor circuit, such as a memory circuit unit, a processing circuit unit, etc. The inner semiconductor circuit is included in the semiconductor chips120to store a signal or data, to process a signal or data, or to receive or transmit a signal or data, and communicates with an external circuit through the chip via plugs140. The inner semiconductor circuit may include a voltage control circuit. The voltage control circuit may transform and/or generate several internal voltages from external voltage (power) supplied through the chip via plugs140. When the supply voltage is a device power (Vdd), the internal voltages may be an elevated voltage (i.e. highly pumped voltage Vpp using a charge pump), a cell voltage Vcc used in cell array, a reference voltage Vref used on developing signals, a divided voltage dividing any voltages, and etc. used in a semiconductor chip. As the voltages are set forth respectively, particular voltages are not stated in through the specification. And/or, the voltage control circuit may include a ground circuit to ground the inner semiconductor circuit.

The chip via plugs140may be formed to penetrate a body of semiconductor chips120to provide a conductive path between two surfaces (sides), for example, two opposite surfaces (sides) of the body of the semiconductor chips120. The inner semiconductor circuit may have a pad formed on one of the two surfaces, such as the active plane, to be connected to one or more external circuits, conductive lines, or communication lines, and the pad of the inner semiconductor circuit can be connected to an apparatus disposed on the other one of the two surfaces, such as a non-active plane.

In the exemplary embodiment, the stacked semiconductor chips120may be selectively sealed by a package cover180. When the stacked semiconductor chips120are sealed, a space S formed in an inside of the package cover180may be filled with a filling (packing) material180a. In another exemplary embodiment, the stacked semiconductor chips120may be covered with only the packing material180awithout the package cover180. A thermoplastic or thermosetting polymer material or inorganic material, for example, an epoxy resin, benzocyclobutene (BCB), polyimide, or a ceramic material, may be as the packing material180a.

Referring toFIG. 1B, a semiconductor device package200according to an exemplary embodiment of the inventive concept includes a plurality of semiconductor chips220stacked on a second package substrate210, chip bumps230electrically connecting the semiconductor chips220to each other, and a plurality of chip via plugs240penetrating each semiconductor chips220. InFIG. 1B, it is illustrated that chip pads of the semiconductor chips220are formed on the periphery of the semiconductor chips220. In combination withFIG. 1A, it is illustrated that the positions of the chip pads of the semiconductor chips220, the chip via plugs240and the chip bumps230may be variously changed or disposed. That is, the chip pads, the chip via plugs240, and/or the chip bumps230of the semiconductor chips220may be disposed on center rows or areas of the semiconductor chips220.

Also, it is illustrated that the chip bumps230may be electrically connected to input/output bumps270through interconnections (not illustrated) included in the second package substrate210. Compared withFIG. 1A, the chip bumps230and/or input/output bumps270can be electrically connected to each other through a package substrate interconnection (not illustrated) formed in the second package substrate210without forming a package substrate hole (150ofFIG. 1A). However, it is not essential or necessary, and the method illustrated inFIG. 1Amay be compatible with that illustrated inFIG. 1B.

In the exemplary embodiment, the stacked semiconductor chips220may be disposed in the package cover280, and a space S formed in an inside of the package cover280may be filled with a filling (packing) material280a. In another exemplary embodiment, the stacked semiconductor chips220may be covered with only the packing material280awithout the package cover280. A thermoplastic or thermosetting polymer material or inorganic material, for example, an epoxy resin, benzocyclobutene (BCB), polyimide, or a ceramic material, may be as the packing material280a.

FIGS. 2A and 2Bare schematic views of the package substrates110and210illustrated inFIGS. 1A and 1B.

Referring toFIG. 2A, a first package substrate110includes a package substrate hole150formed in a center portion thereof, package substrate pads160and package substrate bumps170that are formed around the package substrate holes150. The first package substrate110is illustrated upside down. The semiconductor chips120ofFIG. 1Aare disposed below the first package substrate110, and the chip bumps130are electrically connected to the package substrate pads160through the package substrate hole150. The package substrate pads160are electrically connected to the package substrate bumps170through package substrate interconnections177. Further, package substrate bump pads175may be formed below the package substrate bumps170. In this case, the package substrate bump pads175may be electrically connected to the package substrate pads160through the package substrate interconnections177.

The shape and arrangement of the package substrate hole150, the package substrate pads160, the package substrate interconnections177and the package substrate bumps170are schematically illustrated for clarity. It is illustrated that the first package substrate110, the package substrate hole150and the package substrate pads160are in the shape of a hexahedron, and the package substrate bumps170are in the shape of a ball. However, the shapes should not be limited thereto.

Referring toFIG. 2B, a second package substrate210includes package substrate pads260formed on a top surface thereof, and package substrate bumps270formed below a bottom surface thereof. In the drawing, a number of package substrate pads260are illustrated for clarity.

The package substrate pads260are connected to the chip bumps230of the semiconductor chips220, and are electrically connected to the package substrate bumps270through package substrate inner interconnections277and package substrate chip via plugs279that are formed in the second package substrate210. The second package substrate210according to the exemplary embodiment may be formed by stacking several sheets (layers) of thin unit package substrates210a,210b, and210c. AlthoughFIG. 2Billustrates three-layer unit package substrates210a,210b, and210cto be stacked, the present general inventive concept is not limited thereto.

As illustrated inFIG. 2B, the package substrate pads260may be disposed on a position different from a position of the package substrate bumps270with respect to a direction A. The positions of the package substrate pads260and the package substrate bumps270may not be disposed on a line parallel to a direction B. The package substrate inner interconnections277may be disposed in the direction A, and the package substrate chip via plugs279may be disposed in the direction B. The direction A may be a horizontal direction and the direction B may be a vertical direction.

The package substrate inner interconnections277may be formed between the adjacent thin unit package substrates210a,210b, and210c. It is possible that the package substrate inner interconnections277may be formed on a surface of a corresponding one of the thin unit package substrates210a,210b, and210c. It is also possible that the package substrate inner interconnections277may be formed in a corresponding one of the thin unit package substrates210a,210b, and210c. The package substrate chip via plugs279may be connected to the package substrate inner interconnections277or may be formed to connect the package substrate inner interconnections277to a corresponding one of the package substrate pads260and the package substrate bumps270.

The package substrate bumps270may be electrically connected to conductive package substrate bump pads275of the second package substrate210.

FIG. 3is a cross-sectional view of a semiconductor device package300according to an exemplary embodiment of the inventive concept.

Referring toFIG. 3, a semiconductor device package300according to another exemplary embodiment includes a plurality of semiconductor chips320a,320b,320c, and320dstacked on a package substrate310, and the semiconductor chips320a,320b,320c, and320dhave at least two specifications or characteristics. The specifications or characteristics may be different from each other. This shows that the technical features of the inventive concept may be applied to a technique of arranging semiconductor chips320a,320b,320c, and320dhaving various functions in a single semiconductor device package300like Multi Chip Package (MCP) or System In a Package (SIP).FIG. 3illustrates that the four semiconductor chips320a,320b,320c, and320dhaving different specifications or characteristics are formed to have a stacked structure in the semiconductor device package300.

A first semiconductor chip320aand a second semiconductor chip320binclude chip via plugs340aand340b, and a third semiconductor chip320cand a fourth semiconductor chip320dmay not include a chip via plug. However, this is to describe that the technical features of the inventive concept may be variously applied when the semiconductor chips320a,320b,320c, and320dhaving different specifications or characteristics are packaged into a single semiconductor device package300. That is, it is possible that only one of the semiconductor chips320a,320b,320c, and320dmay include the chip via plugs340aand340b, and it is also possible that all of the semiconductor chips320a,320b,320c, and320dmay include the chip via plugs340aand340b.

The semiconductor chips320a,320b,320c, and320dmay be electrically connected to each other, and while it is illustrated that the semiconductor chips320a,320b,320c, and320dare connected to each other through chip bumps330a,330band330cin the shape of a mesa, the chip bumps330a,330b, and330cmay be in the shape of a hexahedron, a polyhedron or a ball as described above. Further, the semiconductor chips320a,320b,320c, and320dmay be electrically connected to each other through the chip bumps330a,330band330cwith various structures and shapes.

Moreover, it is illustrated that the chip via plug340aof the first semiconductor chip320aand the chip via plug340bof the second semiconductor chip320bmay be not aligned with each other. This may be interpreted that they may be combined with a redistribution structure, and the detailed description thereof will be provided below.

One of the semiconductor chips320a,320b,320c, and320dmay include an input/output chip pad360aconnected to the package substrate310, and the input/output chip pad360amay be electrically connected to an input/output package substrate pad360cthrough an input/output bump360b.

The input/output package substrate pad360cmay be electrically connected to at least one of package bumps370or at least one of package bump pads375through package substrate interconnections (277ofFIG. 2B). It is possible that a portion of the package substrates110and210ofFIGS. 2A and 2Bmay be used as the package substrate interconnections277. It is also possible that another form of a package substrate310can be used as the package substrate interconnections to electrically connect the input/output package substrate pad360cto a corresponding one of the package bump370and the package bump pad375.

Each of the semiconductor chips320a,320b,320c, and320dmay have a inner semiconductor circuit, such as a memory circuit unit, a processing circuit unit, a data receiving and/or transmitting circuit unit, etc. The inner semiconductor circuit unit can be disposed in a corresponding body of the semiconductor chips320a,320b,320c, and320dto be electrically connected to the chip via plug340aor240bthrough an inner circuit interconnection pad formed on or in a body of the semiconductor chips320a,320b,320c, or320d, and a distribution structure formed on or in a body of the semiconductor chips320a,320b,320c, or320d. The inner semiconductor circuit may include the voltage control circuit and/or the ground circuit as described above.

FIGS. 4A and 4Bare plan views schematically illustrating semiconductor chips according to various exemplary embodiments of the inventive concept. The semiconductor chips according to exemplary embodiments of the inventive concept include substrates including inner semiconductor circuits, conductive redistribution structures and chip pads that are formed on the substrates, and conductive chip via plugs penetrating the substrates. It will be understood that when substrates are referred to as being penetrated, wafers may be penetrated. Alternatively, it may be referred to as vertically penetrating unit semiconductor chips cut by a sawing process.

It is possible that a portion of the chip via plugs can be formed on the wafers of the inner semiconductor circuits and another portion of the chip via plugs can be formed on sealing materials formed around the inner semiconductor circuits to form the substrates such that the chip via plugs can be formed in the wafer and the sealing materials. When the sealing materials are not formed around the inner semiconductor circuit to form the substrates, the chip via plugs may be formed in the inner semiconductor circuits of the substrates. In this case, the chip via plugs may be formed together with the inner semiconductor circuits during inner semiconductor circuits manufacturing process.

The redistribution structures may connect the one or more chip pads of the semiconductor chip to each other.

FIG. 4Ais a plan view of a semiconductor chip400in which chip pads420are arranged in a row in the center portion of a top surface of a substrate410. In the exemplary embodiment, while the chip pads420may be arranged in two or more rows, it is assumed that the chip pads420are arranged in a row for clarity.

Referring toFIG. 4A, the semiconductor chip400according to an exemplary embodiment of the inventive concept includes chip pads420arranged in rows and formed on the substrate410, inner circuit interconnection pads430, and redistribution structures440. The chip pads420may have a shape of, for example, a quadrangle, and chip via plugs450may have a shape of, for example, a circle. Since the redistribution structures440are formed on the chip via plugs450, the chip via plugs450are not seen partially or entirely from the plan view. However,FIG. 4Aillustrates the chip via plugs450to be seen fully from the plan view for clarity. In addition, since most of the redistribution structures440are covered with an insulating passivation layer, they may not be seen as in the drawing. However,FIG. 4Aillustrates the redistribution structures440to be seen well for clarity.

In the exemplary embodiment, the chip via plugs450may be formed to overlap the chip pads420. That is, the chip pads420may be formed on the chip via plugs450or the chip via plugs450may be formed to penetrate the chip pads420. The detailed description thereof will be described below.

The redistribution structures440may electrically connect the chip pads420to the inner circuit interconnection pads430. Specifically, the redistribution structures440may electrically connect the chip pads420to each other, electrically connect the chip pads420to the inner circuit interconnection pads430or electrically connect the inner circuit interconnection pads430to each other. Moreover, the redistribution structures440may be connected to each other. Furthermore, one or more chip pads420may be electrically connected to one or more inner circuit interconnection pads430. For example, the chip pads420providing a supply voltage or ground voltage of the semiconductor chip400constantly provides the same electrical power. Therefore, the chip pads420having such a function may be electrically connected to each other. As described above, the redistribution structures440may be selectively applied in the inventive concept. The redistribution structures440function to distribute and provide an electrical signal provided from one of the chip pads420to several units of the semiconductor chip400. The redistribution structures440are designed to accomplish less signal loss and higher signal transfer speed than an inner semiconductor circuit of the semiconductor chip400. In the exemplary embodiment, the redistribution structures440may be formed of copper (Cu), aluminum (Al), or tungsten (W), or may be formed of a metal, a metal compound or a metal alloy.

The chip via plugs450may be formed to penetrate the semiconductor chip400. In the drawing, it is illustrated that the chip via plugs450are formed to overlap the chip pads420, and the chip via plugs450are formed to correspond to most of the chip pads420for clarity. However, only several chip via plugs may be formed, and even only one chip via plug450may be formed. When there are several chip pads420functioning the same, one chip pad420may be directly connected to the one chip via plug450, and the other chip pads420may be indirectly connected through the redistribution structures440.

The substrate410can include one or more inner semiconductor circuits disposed in a body of the substrate410. The inner semiconductor circuit may have one or more memory circuits or cells to receive data (signal), to store the received data, to read data stored therein, to transmit the read data, and/or to process the data. The substrate410may have the inner circuit interconnection pads430as terminals of the inner semiconductor circuit to be electrically connected to an external apparatus for the data transmission. The inner circuit interconnection pads430may be formed on a surface of the inner semiconductor circuit to be exposed outside thereof. It is possible that the inner circuit interconnection pads430may be formed on a surface of a body of the substrate410to be electrically connected to the inner semiconductor circuit through a conductive communication line (not illustrated) when a terminal of the inner semiconductor circuit is disposed inside of the body of the substrate410.

According to the number of the inner semiconductor circuits, locations of the terminals of the inner semiconductor circuits, and/or input/output methods or structures of the inner semiconductor circuits, locations of the inner circuit interconnection pads430may vary. As illustrated inFIG. 4A, the inner circuit interconnection pads430may be disposed at different locations to correspond to the terminals of the inner semiconductor circuits. Therefore, the redistribution structures440may have different shapes or different forms to correspond to locations of the inner circuit interconnection pads430and/or locations of chip via plugs450. The redistribution structures440may have a first form (structure) extended in both directions X and Y, a second form (structure) extended in one of the directions X and Y, a third form (structure) as a combination of the first form and the second form, or another form extended in a direction having an angle with one of the directions X and Y.

The redistribution structures440may have a width in a direction X or Y, and the width of the redistribution structures440may vary according to locations of the inner circuit interconnection pads430and/or locations of chip via plugs450, and/or locations and widths of other redistribution structures440.

The redistribution structures440may have a width greater than a width of the inner circuit interconnection pads430and/or the chip via plugs450in a direction X or Y or a direction parallel to a major surface of the active plane of the substrate410and/or the inner semiconductor circuits. It is possible that the redistribution structures440may have a portion with a width narrower than a width of the inner circuit interconnection pads430and/or the chip via plugs450. In this case, the portion of the redistribution structures440may be disposed between opposite distal ends of the redistribution structures440, between portions corresponding to the inner circuit interconnection pads430, or between portions corresponding to the inner circuit interconnection pads430and the chip via plugs450.

The chip via plugs450may have an area larger than an area of the inner circuit interconnection pads430in the direction X or Y. However, the present general inventive concept is not limited thereto. It is possible that the area of the chip via plugs450may be smaller than the area of the inner circuit interconnection pads430.

The inner circuit interconnection pads430or the chip via plugs450may be formed on a location to overlap a location of the inner semiconductor circuit along a plane defined by the direction X and Y. It is possible that at least one of the inner circuit interconnection pads430and the chip via plugs450may be formed on a location not to overlap a location of the inner semiconductor circuits along a plane defined by the direction X and Y. In this case, the inner circuit interconnection pads430or the chip via plugs450may be connected to the inner semiconductor circuits through conductive communication lines (not illustrated) or redistribution structures440.

FIG. 4Bis a plan view of a semiconductor chip500in which chip pads520are arranged along the periphery. For example, a region where chip pads520are arranged may be the periphery of a semiconductor chip500, i.e., a scribe lane region or regions adjacent to the scribe lane region. In the exemplary embodiment, chip via plugs550and chip pads520may not be aligned according to the inventive concept. AlthoughFIG. 4Billustrates the chip via plugs550formed along four sides of the semiconductor chip500, the chip via plugs550may be formed along only one side thereof. That is, the chip via plugs550may be formed along one or more sides thereof.

Referring toFIG. 4B, the chip via plugs550may be connected to the chip pads520and inner circuit interconnection pads530using redistribution structures540. In particular, it is illustrated that two or more chip via plugs550are electrically connected to each other. Various connection structures using the redistribution structures540will be described in detail below.

FIGS. 5A to 5Gare cross-sectional views taken along lines I-I′ to VII-VII′ ofFIGS. 4A and 4B, illustrating semiconductor chips in which chip via plugs and other elements are variously applied according to the inventive concept.

Referring toFIG. 5A, it is a cross-sectional view taken along line I-I′ ofFIG. 4A. A structure (or semiconductor chip structure)600ahaving a first and a second redistribution structures640aand642aand a chip via plug650aaccording to an exemplary embodiment of the inventive concept includes an chip pad620aformed on a substrate610a, an inner circuit interconnection pad630a, the first and the second redistribution structures640aand642a, the chip via plug650a, and passivation layers661a,663aand665a. The cross section taken along line I-I′ schematically shows cross-sections of the first redistribution structure640a, the second redistribution structure642a, the chip pad620a, the inner circuit interconnection pad630a, and the chip via plug650a. In this specification, the first redistribution structure640aformed either on the chip pad620aor the inner circuit interconnection pad630amay include a first redistribution via plug645aor a second redistribution via plug647a. However, since a process of forming the first redistribution via plug645aor the second redistribution via plug647amay be selectively performed, it is not separately illustrated in the drawing. That is, although the first redistribution via plug645aor the second redistribution via plug647aare not illustrated in the drawing or described, it should be understood that the first redistribution structure640aformed either on the chip pad620aor the inner circuit interconnection pad630amay include the first redistribution via plug645aor the second redistribution via plug647a, or may include them.

The substrate610amay include one or more inner semiconductor circuit610aaincluding a transistor, passive devices including a capacitor, a resistor or a reactor, vertical circuit via connections, and interconnections. The inner semiconductor circuit may be electrically connected to the inner circuit interconnection pads630athrough inner semiconductor circuit interconnections. The substrate610amay include a material610abto cover or seal the one or more inner semiconductor circuit610aa. The material610abmay be a plastic material, an insulation material, or a non-conductive material.

The inner semiconductor circuit610aamay be disposed inside the substrate610ato be surrounded or covered by the material610ab. In this case, the inner semiconductor circuit610aamay be connected to one or more inner circuit interconnection pads630athrough one or more conductive communication plug615aformed in the material610abbetween one or more terminals of the inner semiconductor circuit610aaand the inner circuit interconnection pad630a. The inner semiconductor circuit610aamay have one or more terminals each connectable to one or more inner circuit interconnection pads630a.

It is possible that the inner circuit interconnection pad630acan be formed on a surface of the inner semiconductor circuit610aa. In this case, the inner circuit interconnection pad630amay be disposed on a same surface of the substrate610aand the inner semiconductor circuit610aa.

The chip pad620aand the inner circuit interconnection pads630amay be formed during the same process. The chip pad620amay be formed larger than the inner circuit interconnection pads630ain view of appearance.

The first redistribution structure640amay be formed of a metal, e.g., copper, by a deposition or plating process.

It is possible that the inner circuit interconnection pads630aand the first redistribution structure640amay be formed as a single monolithic body during the same process. In this case, the redistribution structure may be formed to provide a direct contact with the inner semiconductor circuit610aa.

The chip via plugs650amay include a chip via hole651a, a sidewall barrier layer653a, and a conductive plug655a. The chip via hole651amay be formed in the shape of a empty column vertically penetrating the substrate610a. The chip via hole651amay be formed by various semiconductor patterning techniques such as etching techniques. The chip via hole651amust not have a physical effect on the inner semiconductor circuit. That is, the inner semiconductor circuit may be designed and manufactured not to be formed in a region where the chip via hole651ais formed. In the exemplary embodiment, when the chip via plug650ais formed to overlap the chip pad620a, the inner semiconductor circuit may not be formed in the substrate610acorresponding to a lower portion of the chip pad620a. When the inner semiconductor circuit is formed in the substrate610awhere the chip pad620aor the chip via plug650aare to be formed, the chip pad620aor the chip via plug650amay be formed on the periphery of the semiconductor chip structure600awith reference toFIG. 4B.

The sidewall barrier layer653amay be formed of an insulating layer to electrically insulate the conductive plug655afrom the substrate610a. When the sidewall barrier layer653ais formed of an insulating layer, it facilitates the conductive plug655ato be electrically connected to or insulated from the chip pads620aas necessary. That is, it provides wide design choices. The detailed description thereof will be provided in detail below. The sidewall barrier layer653afunctions to prevent chemical and atomic reactions between the conductive plug655aand the substrate610aand physical effects brought on by them, and to reinforce mutual adhesive strength. A silicon nitride layer, a silicon oxynitride layer, etc. may be applied as the sidewall barrier layer653a, and a silicon oxide layer or other polymer organic materials may be applied as well. Alternatively, in another exemplary embodiment, the sidewall barrier layer653amay be formed of a conductive metal. Here, the sidewall barrier layer653amay be formed of a compound containing Ti/TiN or Ta. Otherwise, the sidewall barrier layer653amay be multiple layers including at least two of an insulating layer, an adhesive layer, and a conductive layer.

The conductive plug655amay be formed of a metal, and various metals may be applied. The conductive plug655ahas a large width of several μm to several tens μm in a direction A, and a great depth (thickness) of several hundreds μm in a direction B. Therefore, while the conductive plug655amay be formed of copper, they may be formed of other metals including tungsten, aluminum, etc. As a result of the experiment, the chip via hole651awas formed up to a depth (thickness) of about 300 μm.

In the drawing, it is illustrated that the chip pad620a, the chip via hole651a, the sidewall barrier layer653a, and the conductive plug655aare sequentially formed. While it is illustrated that the sidewall barrier layer653ahas the same height as the surface of the chip pad620a, it is not necessarily to have the same height. The conductive plug655aprotrudes outward from the surface of the chip pad620aby a first distance. In the experiment, when the conductive plug655aprotrudes outward from the surface of the chip pad620aby a second distance, a contact area with the first redistribution structure640ais increased, so that a contact resistance can be reduced. However, protrusion may not be necessarily formed but may be selectively formed during the process. The first distance and the second distance may be different from each other. However, the present general inventive concept is not limited thereto. It is possible that the first distance and the second distance are same.

The passivation layers661a,663aand665amay be formed of one selected from the group consisting of a silicon oxide layer, a silicon nitride later, a silicon oxynitride layer and a polyimide layer. Here, the polyimide layer may be photosensitive.

The first redistribution structure640amay have a portion640a1to be exposed outside through an opening of the passivation layer665a. The redistribution via plug645amay be formed on the portion640a1as a single integrated body or may be formed with the portion640a1as a single monolithic body. The first redistribution structure640amay be connected to another conductive plug of another substrate of another semiconductor chip. The conductive plug655ahas opposite end portions, one of which is connected to the first redistribution structure640athrough the chip pad620a, and the other one of which is connected to another semiconductor chip through another chip via plug thereof.

Referring toFIG. 5B, it is a cross-sectional view taken along line II-II′ ofFIG. 4A. A structure (or semiconductor chip structure)600bhaving a redistribution structure640band a chip via plug650baccording to another exemplary embodiment of the inventive concept includes an chip pad620bformed on a substrate610b, an inner circuit interconnection pad630b, the redistribution structure640b, the chip via plug650b, passivation layers661b,663band665band a pad insulating layer670b.FIG. 5Billustrates that the chip via plug650bis electrically insulated from the chip pad620b, and is electrically connected to the inner circuit interconnection pad630bdisposed on a different location.

The chip via plug650bmay be insulated from the aligned chip pad620bby the pad insulating layer670b. While the chip via plug650bis connected to the redistribution structure640b, the chip via plug650band the redistribution structure640bare insulated from the aligned chip pad620bby the pad insulating layer670b. When two semiconductor chips having different specifications are connected to each other through the chip via plug650b, this exemplary embodiment may be constituted. The exemplary embodiment may be usefully applied when specifications with respect to positions where the chip pad620band the inner circuit interconnection pad630bare formed are defined as the same, and functions of the chip pad620band the inner circuit interconnection pad630bare defined as different from each other. For example, when the chip via plug650band the aligned chip pad620bare used for an electric die sorting (EDS) test in a semiconductor chip, and are used for control signal transfer in the other semiconductor chip, it is required to connect the chip pad620bformed on different locations in each semiconductor chip. In this case, although the semiconductor chips have different specifications from each other, they may be electrically connected to each other through the chip via plug650b. This exemplary embodiment was previously illustrated with the connection of the first semiconductor chip320ato the second semiconductor chip320binFIG. 3. Additionally, when a plurality of semiconductor chips are stacked and have various specifications, the redistribution structure640bformed on the chip pad620band the inner circuit interconnection pad630bmay be partially exposed to be connected to another chip via plug of the other semiconductor chip.

The chip via plug650bmay include a chip via hole651b, a side wall barrier layer653bformed in the chip via hole651b, and a conductive plug655bdisposed inside the side wall barrier layer653b.

The redistribution structure640bformed either on the chip pad620bor the inner circuit interconnection pads630bmay be formed of a third redistribution via plug645bor a fourth redistribution via plug647b. However, since a process of forming the third redistribution via plug645bor the fourth redistribution via plug647bmay be selectively performed, it is not separately illustrated in the drawing. That is, although the third redistribution via plug645bor the fourth redistribution via plug647bare not illustrated in the drawing or described, it should be understood that the redistribution structure640bformed either on the chip pad620bor the inner circuit interconnection pads630bmay be formed on the third redistribution via plug645bor the fourth redistribution via plug647b, or may include them.

The substrate610bmay include a material610bbto cover or seal the one or more inner semiconductor circuit610ba. The material610bbmay be a plastic material, an insulation material, a non-conductive material, a resilient material, and etc. The material610bbmay be a material to protect the inner semiconductor circuit610bafrom an external force and to prevent the inner semiconductor circuit610bafrom being deformed. It is possible that the substrate610bmay be formed with the inner semiconductor circuit610bawithout the material610bb.

The inner semiconductor circuit610bamay be disposed inside the substrate610ato be surrounded or covered by the material610bb. In this case, the inner semiconductor circuit610bamay be connected to one or more inner circuit interconnection pad630bthrough one or more conductive communication lines formed in the material610bbbetween one or more terminals of the inner semiconductor circuit610baand the inner circuit interconnection pad630b. The inner semiconductor circuit610bamay have one or more terminals each connectable to one or more inner circuit interconnection pads630b.

It is possible that the inner circuit interconnection pad630acan be formed on a surface of the substrate610b, and a surface of the inner semiconductor circuit610bamay be disposed on a same surface of the substrate610bopposite to the surface on which the inner circuit interconnection pad630bcan be formed.

Referring toFIG. 5C, it is a cross-sectional view taken along line III-III′ ofFIG. 4A. A structure (or semiconductor chip structure)600chaving a first and second redistribution structures640cand642cand a chip via plug650caccording to an exemplary embodiment of the inventive concept includes an chip pad620cformed on a substrate610c, the redistribution structures640cand642c, the chip via plug650c, and passivation layers661c,663cand665c. In addition, the chip pad620cand the redistribution structures640cand642cmay not be exposed to the outside. That is, the chip pad620cand the redistribution structures640cand642cmay be covered with at least one passivation layer665c. While the chip via plug650cmay be electrically connected to the chip pad620cand the first redistribution structure640c, the first redistribution structure640cis not connected to other elements of the structure600c. That is, the chip via plug650cillustrated inFIG. 5Cmay be applied when another semiconductor chip is not stacked on the semiconductor chip610c. it is unnecessary to be electrically connected to the stacked semiconductor chip. Alternatively, when the electrical connection to the stacked semiconductor chip is restricted, the chip via plug may be applied. In the exemplary embodiment, the redistribution structure or a redistribution structure pad that are formed over the chip via plug650cmay be omitted.

In the exemplary embodiment, the first redistribution structure640cmay provide possibilities of being electrically connected to the other semiconductor chip, if necessary.

A redistribution via plug645cmay be included in the first redistribution structure640cto connect the chip via plug650cto another semiconductor chip.

The chip via plug650cmay include a chip via hole651c, a side wall barrier layer653cformed in the chip via hole651c, and a conductive plug655cdisposed inside the side wall barrier layer653c.

Referring toFIG. 5D, it is a cross-sectional view taken along line IV-IV′ ofFIG. 4A. A structure (or semiconductor chip structure)600dhaving a redistribution structure640dand a chip via plug650daccording to an exemplary embodiment of the inventive concept includes an chip pad620dformed on a substrate610d, the redistribution structure640d, the chip via plug650d, passivation layers661d,663dand665dand a pad insulating layer670d. Also, a part of the redistribution structure640dmay be externally exposed. It is illustrated that the chip via plug650dis electrically insulated from the chip pad620dusing the pad insulating layer670d, and is electrically connected to the redistribution structure640dinFIG. 5D. When the semiconductor chips are stacked, a specific semiconductor chip may not require an electrical signal provided through the chip via plug650d. For example, when the chip pad620dof the semiconductor chip are disposed at the same location, but have different functions, it is required to insulate an electrical signal provided through the chip via plug650dthat is aligned with or overlaps the chip pad620d. Furthermore, when it is required to transfer an electrical signal that is provided through the chip via plug650dto a chip pad620dor an inner circuit interconnection pad (not illustrated), the method suggested in the exemplary embodiment may be very useful.

A redistribution via plug645dmay be included in the redistribution structure640dto connect the chip via plug650dto another semiconductor chip.

Referring toFIG. 5E, it is a cross-sectional view taken along line V-V′ ofFIG. 4A. A structure (or semiconductor chip structure)600eof a redistribution structure640eand a chip via plug650eaccording to an exemplary embodiment of the inventive concept include an chip pad620eformed on a substrate610e, the redistribution structure640e, the chip via plug650e, and passivation layers661e,663eand665e. The chip via plug650eaccording to the exemplary embodiment that transfers an electrical signal in a vertical direction may be electrically connected to the chip pad620e, and may be electrically connected to another chip via plug included in another semiconductor chip to be stacked on a top portion. In the exemplary embodiment, since it is unnecessary to distribute an electrical signal into the semiconductor chip600ethrough the redistribution structure640e, and the electrical signal is transferred through the aligned chip pad620eto be used, it may be usefully applied when an electrical signal is transferred to the other semiconductor chip.

A redistribution via plug645emay be included in the redistribution structure640eto connect to another redistribution structure of another inner semiconductor circuit.

Referring toFIG. 5F, it is a cross-sectional view taken along line VI-VI′ ofFIG. 4A. A structure (or semiconductor chip structure)600fhaving a redistribution structure640fand a chip via plug650faccording to an exemplary embodiment of the inventive concept includes an chip pad620fformed on a substrate610f, the redistribution structure640f, the chip via plug650f, passivation layers661f,663fand665fand a pad insulating layer670f. In the exemplary embodiment, it is illustrated that the redistribution structure640fis connected to the chip via plug650fand is insulated from the chip pad620f, and a part of the redistribution structure640fis partially exposed to be connected to the other semiconductor chip.

The substrate610fmay have an inner semiconductor circuit610faand/or a material610fb. The inner semiconductor circuit610famay be disposed not to overlap the chip pad620f. In this case, a conductive communication plug615fcan be formed between the inner semiconductor circuit610faand the chip pad620f. The conductive communication plug615fmay have a first portion connected to a terminal of the inner semiconductor circuit610fa, a second portion connected to the chip pad620f, and a third portion formed between the first portion and the second portion. The third portion of the conductive communication plug615fmay have a bent portion with respect to the first portion and the second portion.

Referring toFIG. 5G, it is a cross-sectional view taken along line VII-VII′ ofFIG. 4A. A structure (or semiconductor chip structure)600ghaving a redistribution structure640gand a chip via plug650gaccording to an exemplary embodiment of the inventive concept includes an chip pad620gformed on a substrate610g, the redistribution structure640g, the chip via plug650g, an inner circuit interconnection pad630g, and passivation layers661g,663gand665g. In the exemplary embodiment, the chip via plug650gis electrically connected to the chip pad620gand the inner circuit interconnection pad630gthrough the redistribution structure640g, and the redistribution structure640gis exposed to be connected to the outside.

The redistribution structure640gmay include a redistribution via plug645g. The redistribution structure640gmay further include a first redistribution via plug647gaand a second redistribution via plug647gb. The first redistribution via plug647gamay electrically connect the chip via plug650gto the chip pad620gand the second redistribution via plug647gbmay electrically connect the chip plug650gto the chip pad630g.

The substrate610gmay have an inner semiconductor circuit610gaand/or a material610gb. The inner semiconductor circuit610gamay be disposed not to overlap the chip pad620g. However, it is possible that at least a portion of the inner semiconductor circuit610gamay be disposed not to overlap the chip pad620g. One or more conductive lines (or one or more conductive communication plug) can be formed between the inner semiconductor circuit610gaand the chip pad620gand630g. A first conductive communication plug615g1may be connected between terminals of the inner semiconductor circuit610gaand the chip pad620g, and a second conductive communication plug615g2may be connected between terminals of the inner semiconductor circuit610gaand chip pad630g. At least one of the conductive communication plugs615g1and615g2may have a bent portion between the terminals. It is also possible that at least one terminal of the inner semiconductor circuit610gacan be formed on a plane on which the chip pad620ais formed.

The structure600gmay have a material unit667gformed on a bottom of the substrate610g. The material unit667gmay be an insulation layer or a protection layer to cover a lower side or surface of the substrate610g. When the substrate610gand the inner semiconductor circuit610gahave a common surface, for example, the bottom or lower surface, the material unit667gmay be used as a layer to protect the substrate610gand the inner semiconductor circuit610ga. The material unit667gmay have a portion668gto correspond to an end portion of the chip via plug650g. The portion668gmay not be formed to expose the end portion of the chip via plug650gsuch that the end portion of the chip via plug650gcan be connected to another semiconductor chip structure.

While it is not illustrated inFIGS. 5A to 5F, all of the semiconductor chips may include insulating protection layers formed below the substrates. The insulating protection layers may be entirely formed below the substrate to expose or to cover the chip via plugs. The insulating protection layers may play an important part in stacking the semiconductor chips, and may be described in a different name in the applied exemplary embodiment.

FIGS. 6A to 6Care plan views and cross-sectional views illustrating shapes of openings to connect an chip pad or an inner circuit interconnection pad to a redistribution structure in a semiconductor chip structure according to various exemplary embodiments of the inventive concept. The chip pad and the inner circuit interconnection pad will be referred to as pads to be described. In the drawings, a chip via plug is not illustrated.

FIG. 6Aillustrates that the openings Ola, Olb and Olc of the lower passivation layers761a,761band761cmay be formed different from the openings Oua, Oub and Ouc of the intermediate passivation layers763a,763band763cin view of size. This provides various possible embodiments to those who desire to embody the technical features of the inventive concept, and may be variously applied when a pad insulating layer (not shown) is further formed. For example, when the pad insulating layer is required to be formed, the openings Ola, Olb and Olc of the lower passivation layers761a,761band761cmay be formed smaller than the openings Oua, Oub and Ouc of the intermediate passivation layers763a,763band763cto electrically insulate the pads720a,720band720cfrom the redistribution structures740a,740band740c.

A first drawing ofFIG. 6Aillustrates that the opening Oua of the intermediate passivation layer763ais formed larger than the opening Ola of the lower passivation layer761a, and a second drawing illustrates that the opening Oub of the intermediate passivation layer763bis formed smaller than the opening Olb of the lower passivation layer761b. Further, a third drawing illustrates that a plurality of openings Olc may be formed in a region that a single pad720coccupies. Forming a plurality of openings in the same area may cause less process errors than forming a single large opening. In addition, when a chip via plug has a sufficiently low resistance, forming a plurality of chip via plugs may cause less process errors than forming a single large chip via plug to obtain satisfactory results. In the exemplary embodiments, when a region that the pad720coccupies or a region where the redistribution structure740cis in contact with the pad720cis large enough, the sizes of the openings Olc and Ouc of the passivation layers761cand763cmay be adjusted to obtain optimal results.

Referring toFIG. 6B, widths Wd1and Wd2of redistribution structures840aand840bmay be formed smaller than one of the openings Old1, Oud1, Old2and Oud2. More specifically, while one of the openings Old1, Oud1, Old2and Oud2is formed larger than widths Wd1and Wd2of the redistribution structures840aand840b, one of the openings Old1, Oud1, Old2and Oud2may be formed to extend in a longitudinal direction of the redistribution structures840aand840bor a plurality of openings may be formed. The sizes of the lower openings Old1and Old2and the upper openings Oud1and Oud2may be variously adjusted depending on those who desire to embody the technical features of the inventive concept.

Referring toFIG. 6C, it is illustrated that when two or more openings Ole and Oue may be formed adjacent to each other in a redistribution structure940aor two or more openings Olg and Oug share two or more redistribution structures940band940c, a region where two openings are to be formed may include one opening. While forming a single large opening may cause a higher process error than forming a plurality of openings, this method may simplify the process. Therefore, unless a pattern has an effect on adjacent patterns, the simplified process may be applied to improve productivity.

The openings Oud1and Old1may be disposed in a direction X. The openings Oud1and Old1may be disposed in the same direction to form a single opening having a first side in a direction Y and a second side having a longer length than the first side, in the direction, for example, the direction X.

It is also possible that the openings Oue and Ole can be disposed in a direction Y and may have a side in a direction X longer than other side in a direction Y. It is also possible that openings Oug, Olg1, Ouf, Olf, and Olg2can be arranged in a direction X and in a direction Y, with respect to each other.

While only several exemplary embodiments are simply illustrated and described inFIGS. 6A to 6C, further applications could have been understood and anticipated.

FIGS. 7A and 7Bconceptually illustrate a stacked semiconductor chip in which chip via plugs are electrically connected to each other according to exemplary embodiments of the inventive concept.

Referring toFIG. 7A, a lower chip via plug1110lof a lower semiconductor chip1100lis electrically connected to an upper chip via plug1150uof an upper semiconductor chip1100uthrough a redistribution structure pad1145land a package bump1180. A connection bump pad1125uthat is electrically connected to a lower end of the upper chip via plug1150umay be formed below the upper semiconductor chip1100u. Therefore, the redistribution structure pad1145lof the lower semiconductor chip1100lmay be electrically connected to the connection bump pad1125uof the upper semiconductor chip1100uthrough a connection bump1180.

Lower passivation layers1115uand1117uexposing the connection bump pad1125umay be formed below the upper semiconductor chip1100u. The lower passivation layers1115uand1117umay be formed of at least two layers, the first lower passivation layer1115umay be formed below the upper semiconductor chip1100uto expose the lower end of the upper chip via plug1150u, and the second lower passivation layer1117umay be formed to expose the connection bump pad1125u.

While it is illustrated that the connection bump1180is in the shape of a ball in the exemplary embodiment, it may be formed in the shape of a hexahedron or a polyhedron, or may be formed to have other shapes. In addition, the upper chip via plug1150umay be directly or indirectly connected to the lower chip via plug1150lusing a conductive adhesive without forming the connection bump1180.

In the exemplary embodiment, it is illustrated that the lower chip via plug1150lis connected to the lower redistribution structure pad1120l.

An opening1185on the upper redistribution structure pad1120uof the upper semiconductor chip1100uimplies that another semiconductor chip may be stacked thereon to be electrically connected.

The semiconductor chip apparatus1100may further include passivation layers1160uand1160l, a redistribution structure pad1145u, chip pads1120u, and substrates1110uand1110l.

Referring toFIG. 7B, a lower chip via plug1250lof a lower semiconductor chip1200lis electrically connected to an upper chip via plug1250uof an upper semiconductor chip1200uthrough a redistribution structure1240l. Compared withFIG. 7A, it is illustrated that a connection bump1280is not aligned with the lower chip via plug1250l, and is formed at an extended place to be electrically connected to the upper chip via plug1250uthrough the redistribution structure1240l.

A pad insulating layer1270lmay be formed between the lower chip via plug1250land a lower chip pad1220l. That is, the lower chip via plug1250lmay be insulated from the lower redistribution structure pad1220l.

Also, the redistribution structure1240lmay be insulated from an inner circuit interconnection pad1230l, and the redistribution structure1240lmay be electrically connected to the inner circuit interconnection pad1230l. This could have been sufficiently understood with reference toFIGS. 5Aor5B.

The semiconductor chip apparatus1200may further include passivation layers1260u,1215u,1217u, and1260l, an opening1285, a redistribution structure pad1245u, chip pads1220u, a connecting bump pad1225u, and substrates1210uand1210l

As illustrated inFIG. 7A and 7B, the chip via plugs can be disposed on corresponding lines parallel to a direction A. It is possible that one chip via plug may be spaced apart from another chip via plug by a distance. The distance may be longer than a width of the connecting bump1180or1280in a direction X.

A bottom surface of the upper semiconductor chip1200uand an upper surface of the lower semiconductor chip1200lmay be spaced apart from each other by a height. The height may be smaller than a height of the connecting bump1180or1280in the direction B. It is also possible that the height can be zero according to the height of the connection bump1180or1280.

FIG. 8is a block diagram illustrating an electronic apparatus1300according to an embodiment of the present general inventive concept. The electronic apparatus1300may include a housing1310to accommodate elements or units of the electronic apparatus1300, a memory unit1320, a controller1330, an input/output unit1340, a function unit1350, and/or an interface unit1360to communicate with an external apparatus1390through a wired or wireless communication line to receive and transmit data or signal. At least one of the semiconductor chip, the semiconductor chip stack, and the semiconductor device package illustrated inFIGS. 1 through 7Bcan be used as the memory unit1320. Therefore, the memory unit1320can be referred to as the semiconductor chip, the semiconductor chip stack, or the semiconductor device package. The chip via plugs, chip bumps, or package bumps (as illustrated inFIGS. 1 through 7B) of the memory unit1320can be connected to corresponding terminals of controller1330to receive data to be stored or processed in the inner semiconductor circuit or to transmit the stored or processed data. The data may be input through the input/output unit1340, the function unit1350, and/or the external apparatus1390through the interface unit1360.

The function unit1350may be a unit to perform a function or operation of the electronic apparatus1300. For example, when the electronic apparatus1300is an image processing apparatus, a television apparatus, or a monitor apparatus, the function unit1350may be a display unit to display an image and/or an audio output unit to generate a signal or sound according to the data. When the electronic apparatus is a mobile phone, the function unit1350may be a mobile phone function unit to perform a mobile phone function, for example, dialing, text messaging, photographing using a camera unit formed on the housing1310, audio and video data processing to be displayed on a display unit formed on the housing1310, etc. When the electronic apparatus is an image forming or scanning apparatus, the function unit1350may be an image forming unit to feed a printing medium, to form or print an image on the printing medium, or to scan a document or picture to be stored in the memory unit. When the electronic apparatus1300is a camera or camcorder, the function unit1350may be a unit to photograph an image as a movie or a still image.

The controller1330controls elements and units of the electronic apparatus1300or may be a processor. At least one of the semiconductor chip, the semiconductor chips, and the semiconductor device package illustrated inFIGS. 1 through 7Bcan be used as the controller1330. Therefore, the controller1330can be referred to as the semiconductor chip, the semiconductor chips, the semiconductor device package, or a semiconductor device package unit. The chip via plugs, chip bumps, or package bumps (as illustrated inFIGS. 1 through 7B) of the controller1330may be connected to corresponding terminals of the memory unit1320or other units, for example, the input/output unit1340, function unit1350, and/or the interface unit1360, to transmit or receive data to or from the inner semiconductor circuit of the memory unit820, or other units.

Since a semiconductor chip, a stacked structure of the semiconductor chip, and a semiconductor package including the stacked structure of the semiconductor chip according to exemplary embodiments of the inventive concept exhibit reduced electrical signal loss, high transfer speed, enhanced chip area efficiency and improved input/output impedance matching, various semiconductor chips and packaged semiconductor devices can be provided.