Timing adjustment circuit and semiconductor integrated circuit device

A timing adjustment circuit includes a voltage-controlled delay line, a phase detector, a control voltage generation circuit, and a startup circuit. The voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, a delay amount of each of the multi-phase clocks is changed according to a control voltage. The phase detector detects a phase difference between a first clock and a second clock, the first clock is a reference, the second clock is generated from the voltage-controlled delay line. The control voltage generation circuit generates the control voltage on the basis of the detected phase difference. The startup circuit operates for a certain period after activation, and continuously changes the control voltage between a first voltage and a second voltage.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2013-235911, filed on Nov. 14, 2013, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a timing adjustment circuit and a semiconductor integrated circuit device.

BACKGROUND

Recently, performances of semiconductor memories (for example, DRAM: Dynamic Random Access Memory), processors, and the like used for computers and other information processing devices are significantly improving. Accordingly, it is preferable to correctly and speedily carry out signal transmission among chips mounted on a board and among a plurality of elements and circuit blocks within a chip.

In view of this, for example, there is a known technique in which: a timing adjustment circuit (for example, DLL circuit: Delay Locked Loop Circuit) is provided on the receiving side; a multi-phase clock is generated by delaying the input clock signal through the DLL circuit; and data is read (determined) at appropriate timing.

On the other hand, there is a known SerDes (SERializer/DESerializer) that interconverts serial data and parallel data at a high-speed interface such as a computer bus, and a DLL circuit is adopted in the SerDes as well.

The DLL circuit has a plurality of cascade-connected delay units so as to control, for example, a phase difference between a signal from a first delay unit (0 degree) and a signal from a second delay unit (360 degree) on latter stage of the first delay unit to become 0.

Then, the DLL circuit generates a plurality of signals with different phases (a multi-phase clock) using signals from the delay units between the first delay unit and the second delay unit. Note that a DLL circuit (a timing adjustment circuit) is not only adopted in SerDes but also widely adopted in a variety of electronic circuits (semiconductor integrated circuit devices).

As described above, the DLL circuit that has a plurality of cascade-connected delay units is adopted, for example, in a variety of electronic circuits such as SerDes. With such electronic circuits that adopt the DLL circuit, there is a possibility that the Phase Frequency Detector (PFD: phase detector) in the DLL circuit malfunctions, for example, upon startup by power application.

In other words, when the frequency of the input signal (an input clock signal) of the DLL circuit becomes higher, the operable range of the PFD is narrowed, thus, for example, the PFD malfunctions upon startup, which possibly makes generation of timing-adjusted output signals difficult.

In this regard, various timing adjustment circuits have been proposed.

SUMMARY

According to an aspect of the embodiments, there is provided a timing adjustment circuit including a voltage-controlled delay line, a phase detector, a control voltage generation circuit, and a startup circuit.

The voltage-controlled delay line receives an input clock signal and generates multi-phase clocks, a delay amount of each of the multi-phase clocks is changed according to a control voltage. The phase detector detects a phase difference between a first clock and a second clock, the first clock is a reference, the second clock is generated from the voltage-controlled delay line.

The control voltage generation circuit generates the control voltage on the basis of the detected phase difference. The startup circuit operates for a certain period after activation, and continuously changes the control voltage between a first voltage and a second voltage.

DESCRIPTION OF EMBODIMENTS

First, before describing embodiments of a timing adjustment circuit and a semiconductor integrated circuit device, an example of a timing adjustment circuit and the problematic points thereof are described with reference toFIGS. 1 to 6C.

FIG. 1is a block diagram depicting an example of the timing adjustment circuit (a DLL circuit). InFIG. 1, the reference sign1indicates a Voltage-Controlled Delay Line (VCDL),101to112indicate delay units, and203to211indicate waveform-shaping units. Further, the reference sign3indicates a phase frequency detector (PFD: a phase detector),4indicates a Charge Pump (CP), and5indicates a capacitor.

As depicted inFIG. 1, the VCDL1has a plurality of cascade-connected delay units101to112, and the output signals of the delay units103to111are respectively output via the corresponding waveform-shaping units203to211.

The waveform-shaping units203to211are, for example, buffer circuits that output the output signals of the delay units103to111by amplifying the amplitude level of the output signals to a typical logic level. The buffer circuits are, for example, Complementary Metal-Oxide Semiconductor (CMOS) buffer circuits.

The output signal of the waveform-shaping unit203, i.e., a signal (CK0: reference clock signal) REF obtained by shaping the waveform of the output signal (a signal with 0-degree phase) of the delay unit103is given to one input of the PFD3.

Further, the output signal of the waveform-shaping unit211, i.e., a signal (CK360: feedback clock signal) FB obtained by shaping the waveform of the output signal (a signal with 360-degree phase) of the delay unit111is given to the other input of the PFD3.

The phase frequency detector (PFD)3detects a phase difference between the output signal (reference clock signal) REF of the waveform-shaping unit203and the output signal (feedback clock signal) FB of the waveform-shaping unit211that have been input to the PFD3, and outputs an UP signal UP or a DOWN signal DN to the CP4.

The charge pump (CP)4controls an electric charge that the capacitor5stores according to the signal UP, DN from the PFD3. As such, the control voltage Vcntl is controlled so that the phases of the reference clock signal REF and the feedback clock signal FB synchronize to each other (360 degrees (=0 degree)).

InFIG. 1, seven delay units104to110are provided between the delay unit (first delay unit)103and the delay unit (second delay unit)111. Then, by controlling to synchronize the phases of the signal REF corresponding to the output signal CK0of the first delay unit103and the signal FB corresponding to the output signal CK360of the second delay unit111, eight-phase clocks CK0, CK45, CK90, . . . , CK360may be obtained.

When n and m are positive integers and n is smaller than m, for example, the reference clock signal REF is output from the n-th stage delay unit, and the feedback clock signal FB is output from the m-th stage delay unit.

FIG. 2is a circuit diagram depicting an example of a delay unit in the timing adjustment circuit depicted inFIG. 1.FIGS. 3A and 3Bare diagrams illustrating the operation of the timing adjustment circuit depicted inFIG. 1.FIG. 3Adepicts a relationship among the signals CK0, CK90, CK180, CK270, and CK360;FIG. 3Bdepicts a relationship between the control voltage Vcntl and delay time.

As depicted inFIG. 2, the delay units100(101to112) all have the same circuit configurations, and each has p-channel MOS (pMOS) transistors Qp1to Qp5and n-channel MOS (nMOS) transistors Qn1to Qn4.

Now, take a delay unit108ofFIG. 1as an example depicting the correspondence relationship. The gates of differential pair transistors Qn1and Qn2at the input in the delay unit100(108) depicted inFIG. 2respectively correspond to the differential inputs IN and /IN. The input IN indicates a positive logic (non-inverted logic) input and /IN indicates a negative logic (inverted logic) input.

Further, the connection node of the drain of the transistor Qp2(the gate and drain of the transistor Qp1) and the drain of the transistor Qn1corresponds to the negative logic (inverted logic) output /OUT. Moreover, a connection node of the drain of the transistor Qp3(the gate and drain of the transistor Qp4) and the drain of the transistor Qn2corresponds to the positive logic (non-inverted logic) output OUT.

As depicted inFIG. 2, the control voltage Vcntl is applied to the gates of the nMOS transistors Qn3and Qn4, and the drive capability (flowing current) of the transistors Q3and Q4are controlled by the voltage level of the control voltage Vcntl.

When the voltage level of the control voltage Vcntl is high, the transistor Qn3turns sufficiently ON and the transistor Qn4also turns sufficiently ON, whereby the gate voltages of the transistors Qp2and Qp3are low. In this way, the drive capability of the delay unit100becomes large, shortening the delay time. On the other hand, when the level of the control voltage Vcntl is low, the delay time caused by the delay unit100becomes longer.

In other words, as depicted inFIG. 3B, the control voltage Vcntl is 0 (Vcntl=0) in the initial state, where the VCDL1(delay units101to112) does not propagate a signal. Further, the reference clock signal REF and the feedback clock signal FB that have been input to the PFD3do not transit from 0 (REF=0, FB=0). Thus, the control voltage Vcntl maintains the initial state (Vcntl=0).

Each of the delay units100(101to112) starts operation, for example, when the level (voltage) of the control voltage Vcntl exceeds the threshold voltage Vth of the transistors Qn3and Qn4. As the level (voltage) of the control voltage Vcntl becomes higher, the drive capability of each delay unit becomes higher, thus shortening the delay time.

Note that the waveform-shaping units203to211have all the same circuit configurations, and the delay time of each waveform-shaping unit is fixed. Therefore, for example, when the DLL circuit (timing adjustment circuit) is locked, the eight-phase clock output from the waveform-shaping units203to211corresponds to eight-phase clocks CK0, CK45, CK90, . . . , CK360with phase difference of 45 degrees each, which are output from the delay units103to111.

Next, the output signal from the delay units103to111will be described by eliminating the fixed delay time caused by the waveform-shaping units203to211and considering the output signal as multi-phase clocks CK0to CK360to simplify the description.

Referring toFIG. 3A, the output signal of the delay units103,105,107,109, and111ofFIG. 1will be described as the output signal of the waveform-shaping units203,205,207,209, and211(clock signals CK0, CK90, CK180, CK270, CK360).

The signal CK0is a signal that is obtained by delaying the input clock signal CLK by three stages of the delay units101to103. The input clock signal CLK represents, for example, a differential (complementary) input clock signal of positive and negative logic.

The signal CK90is a signal obtained by delaying the input clock signal CLK by five stages of the delay units101to105, i.e., a signal obtained by delaying the output signal CK0of the delay unit103further by two stages of the delay units104and105.

Further, the signal CK180is a signal obtained by delaying the input clock signal CLK by seven stages of the delay units101to107, i.e., a signal obtained by delaying the output signal CK90of the delay unit105further by two stages of the delay units106and107. Then, other signals CK270, CK360(=CK0) are similarly generated by sequentially delaying by the delay units.

The DLL circuit (timing adjustment circuit) described with reference toFIGS. 1 and 2generates a multi-phase (eight-phase) clock signal by sequentially delaying the input clock signal CLK. The control voltage Vcntl is applied to the gates of the transistors Qn3and Qn4of all the delay units101to112(100) and the level of the control voltage Vcntl is feedback-controlled so as to synchronize the signals REF and FB.

As such, by synchronizing (adjusting to 0 degree) the phases of the reference clock signal REF and the feedback clock signal FB, eight signals (eight-phase clocks: multi-phase clocks) with phase difference of 45 degrees each are obtained from the delay units103to111.

Note that, while the delay units101to112and the waveform-shaping units203to211are of differential configurations, the delay units101to112and the waveform-shaping units203to211may be of single-ended configurations. It is to be appreciated that the configuration of the VCDL1, the number of stages of delay units provided between the first delay unit103and the second delay unit111, the circuit configuration of the delay units and the waveform-shaping units and the like may be modified in a variety of ways.

Meanwhile, in the above-describedFIG. 2, when the control voltage is defined as Vcntl=0V upon startup, the DLL circuit (timing adjustment circuit) as depicted inFIG. 1is not activated as the delay units101to112(100) that configure the VCDL1do not operate. Thus, a case in which a power supply voltage (high potential power supply voltage) VDD is given as a control voltage Vcntl upon startup will be described with reference toFIGS. 4A and 4B.

FIGS. 4A and 4Bare diagrams illustrating a delay of the timing adjustment circuit depicted inFIG. 1upon startup.FIG. 4Adepicts a relationship between the control voltage Vcntl and delay time;FIG. 4Bdepicts a time transition of the control voltage Vcntl upon activation (t0).

First, by giving a power supply voltage (high potential power supply voltage) VDD as the control voltage Vcntl and, then, decreasing the level of the control voltage Vcntl therefrom, the delay time of one delay unit100(101to112) changes as depicted inFIG. 4A.

Further, by giving a power supply voltage VDD as the control voltage Vcntl upon activation and, then, performing feedback control by the above-described timing adjustment circuit (DLL circuit), the control voltage Vcntl changes toward the lock voltage Vlock where stable multi-phase clocks are generated, as depicted inFIG. 4B.

FIGS. 5A,5B,5C and5D are diagrams illustrating the operation of the phase frequency detector in the timing adjustment circuit depicted inFIG. 1for different input clock signals.

FIGS. 5A and 5Cdepict when the input clock signal CLK is a first frequency;FIGS. 5B and 5Ddepict when the input clock signal CLK is a second frequency that is twice as much the first frequency. As the frequency of the input clock signal CLK, for example, approximately several GHz to tens of GHz are assumed.

Further,FIGS. 5A and 5Bdepict the input signals REF, FB and the output signals UP, DN of the PFD3;FIGS. 5C and 5Ddepict a relationship between the input phase and output phase of the PFD3. Note thatFIGS. 5A and 5Bdepict when the reference clock signal REF rises before the rising timing of the feedback clock signal FB (the phase of REF is advanced than the one of FB).

As a control upon activation, for example, the control voltage Vcntl when starting the delay control of the VCDL1is set a voltage higher than the lock voltage Vlock. As such, the reference clock signal REF is masked for a predetermined period, and the reference clock signal REF is output after outputting (rising of) the feedback clock signal FB.

Thus, while not depicted inFIG. 1, for example, a circuit equivalent to mask circuits61,62as will be described inFIG. 7is provided in order to output the reference clock signal REF after the feedback clock signal FB upon activation. Note that, when the REF is output after the FB, a DOWN signal DN is output first from the PFD3.

Further, to avoid the situation in which neither an UP signal UP nor a DOWN signal DN is output, a simultaneous ON period δ1 where both signals UP and DN are output as depicted inFIGS. 5A and 5Bis normally provided. Note that the reference sign δ2 indicates a setup period, during which the PFD3detects a phase difference from the transition (rising timing) of the signals REF and FB and controls the signals (pulses) UP, DN.

As depicted from the comparison ofFIGS. 5A and 5B, even when the frequency of the input clock signal CLK becomes twice as much (a cycle T becomes half: T/2), the simultaneous ON period δ1, during which the signals UP, DN are simultaneously output, and the setup period δ2 of the PFD3do not change.

In other words, as depicted from the comparison ofFIGS. 5C and 5D, even when the frequency of the input clock signal CLK becomes twice as much, the non-operation range Rd (=δ1+δ2) where the PFD3does not properly operate does not change. Then, when the frequency of the input clock signal CLK becomes twice as much in the output phase of the PFD3, the normal operation range (operable phase range) decreases dramatically from Rca to Rcb.

FIGS. 6A,6B and6C are diagrams illustrating a normal operation state and malfunction state of the phase frequency detector in the timing adjustment circuit depicted inFIG. 1.FIGS. 6A and 6Bdepict input and output signals REF, FB, UP, DN of the PFD (phase frequency detector)3.FIG. 6Adepicts the normal operation state;FIG. 6Bdepicts the malfunction state.

Further,FIG. 6Cdepicts a time transition of the control voltage Vcntl in a normal operation state and a malfunction state. InFIG. 6C, a curve La indicates the time transition of the control voltage Vcntl in a normal operation state, while a curve Lb indicates the time transition of the control voltage Vcntl in a malfunction state. Further, inFIG. 6C, the reference sign t0indicates the activation timing, while t1indicates timing when a malfunction occurs.

FIGS. 6A to 6Cdepict when the control voltage Vcntl decreases from the high potential power supply voltage VDD to a lock voltage Vlock where stable multi-phase clocks are generated. The reference clock signal REF rises before the rising timing of the feedback clock signal FB. In other words, the phase of the REF is advanced than the FB.

First, as depicted inFIG. 6A, in the normal operation state, the control voltage Vcntl is controlled to be decreased from the power supply voltage VDD that is higher than the lock voltage Vlock. In other words, as the rising timing of the REF comes before the rising timing of the FB, a long period pulse signal DN of high level “H” is output. Note that, as described above, the reference sign δ1 indicates the simultaneous ON period during which signals UP, DN are simultaneously output, and δ2 indicates the setup period of the PFD3.

Then, by normally performing feedback control as depicted inFIG. 6A, for example, as indicated by the curve La inFIG. 6C, the control voltage Vcntl is controlled to be decreased from the power supply voltage VDD to converge to the lock voltage Vlock.

On the other hand, as depicted inFIG. 6B, in a malfunction state, for example, when the PFD3performs processing by determining that the rising timing of the REF is after the rising timing of the FB, a pulse signal UP of which “H” period is longer than the signal DN is output.

Note that the above-described malfunction state may occur when the next edge of either the reference clock signal REF or the feedback clock signal FB rises in the section of δ1+δ2.

As such, for example, when it is determined that the rising timing of the REF comes after the rising timing of the FB at timing t1, as indicated by the curve Lb ofFIG. 6C, the control voltage Vcntl is controlled to be increased to stay at the power supply voltage VDD. As the result, the DLL circuit becomes difficult to generate timing-adjusted output signals.

The following will describe embodiments of the timing adjustment circuit and the semiconductor integrated circuit device in detail with reference to the appended drawings.FIG. 7is a block diagram depicting a first embodiment of the timing adjustment circuit.

As depicted from the comparison betweenFIG. 7and the above-describedFIG. 1, the timing adjustment circuit (DLL circuit) of the first embodiment has an additional startup circuit7with reference to the timing adjustment circuit depicted inFIG. 1.

Note that, inFIG. 7, mask circuits61,62that are controlled by the output signal of a NAND gate73(a gate signal xstup of a transistor74) are provided, and the reference clock signal REF is output after outputting the feedback clock signal FB′.

The VCDL1includes a plurality of cascade-connected delay units101to112. The output signals of the delay units103to111are respectively output as clock signals (multi-phase clocks) CK0to CK360via the corresponding waveform-shaping units203to211.

In the timing adjustment circuit of the first embodiment, for example, the delay units101to112and the waveform-shaping units203to211may adopt equivalents to those of the timing adjustment circuit as described with reference toFIG. 1or any known techniques. Specifically, the delay unit100depicted inFIG. 2may be adopted as is to the delay units101to112, for example.

The waveform-shaping units203to211are, for example, buffer circuits that output the output signals of the delay units103to111by amplifying the amplitude level of the output signals to a typical logic level. The buffer circuits are, for example, CMOS buffer circuits. A signal (CK0: reference clock signal) REF obtained by shaping the waveform of the output signal (a signal with 0-degree phase) of the delay unit103by the waveform-shaping unit203is masked by the mask circuit61for a predetermined period and is provided as a signal REF′ to one input of the PFD3.

Further, a signal (CK360: feedback clock signal) FB obtained by shaping the waveform of the output signal (a signal with 360 degree phase) of the delay unit111by the waveform-shaping unit211is masked by the mask circuit62for a predetermined period and is provided as a signal FB′ to the other input of the PFD3.

The PFD3detects a phase difference between the input reference clock signal REF′ and the feedback clock signal FB′ and outputs an UP signal UP or a DOWN signal DN to the CP4. The mask circuits61,62are for mask-controlling the REF and FB so as to output the signal REF′ after outputting (rising of) the signal FB′ upon activation, and, for example, controlled by the output signal (xstup) of the NAND gate73.

The CP4controls an electric charge that the capacitor5stores according to the signals UP, DN from the PFD3. As such, the control voltage Vcntl is controlled so that the phases of the reference clock signal REF (REF′) and the feedback clock signal FB (FB′) synchronize to each other (360 degrees (=0 degree)).

Note that, in the same way as described with reference toFIG. 1, inFIG. 7, the number of stages of delay units provided between the first delay unit103and the second delay unit111are not restricted to seven, and a desired number of multi-phase clocks may be generated. Further, it is to be appreciated that the circuit configuration may be a single-ended configuration instead of a differential configuration.

The startup circuit7has, for example, three stages of cascade-connected flipflops711to713, inverters721,722, a NAND gate73, and a pMOS transistor74. The startup circuit7controls the control voltage Vcntl so that the control voltage Vcntl becomes a voltage around the aiming target voltage (lock voltage) Vlock upon activation.

As such, for example, even when the frequency of the input clock signal CLK is high and the operable phase range of the PFD3is narrow, the PFD3does not malfunction, enabling the DLL circuit (timing adjustment circuit) to generate timing-adjusted output signals.

FIG. 8is a circuit diagram depicting the startup circuit in the timing adjustment circuit of the first embodiment depicted inFIG. 7, extracted therefrom;FIG. 9is a timing diagram illustrating the operation of the startup circuit depicted inFIG. 8.

As depicted inFIG. 8, in the startup circuit7, the data input terminal D of the first stage flipflop711among the three stages of cascade-connected flipflops711to713is connected to the high-potential power wiring, so that the high potential power supply voltage VDD may be applied.

Note that, instead of the output signal FB′ of the mask circuit62, the output signal CK360(feedback clock signal FB) of the waveform-shaping unit211is directly input to the clock terminals CK of the flipflops711to713.

The data output terminal Q of the first stage flipflop711is connected to the data input terminal D of the second stage flipflop712, while the data output terminal Q of the second stage flipflop712is connected to the data input terminal D of the third stage flipflop713. The output signal from the data output terminal Q of the third stage flipflop713is supplied to the one input of the NAND gate73via the inverter722.

A signal obtained by logic-inverting the activation signal (power down signal) PD by the inverter721is supplied to the other input of the NAND gate73, then, the output signal of the NAND gate73, as the gate signal xstup of the transistor74, controls the transistor74.

The activation signal PD is a signal that falls from high level “H” to low level “L” upon activation (t0). Further, the data output (Q) of each of the flipflops711to713is “L” at an initial state and maintained to “L” upon activation t0. Therefore, the output signal of the inverter722is “H”.

As depicted inFIG. 9, for example, when the activation signal PD falls from “H” to “L” (the power down is released) at timing t0, both input signals of the NAND gate73become “H” and thus the output signal of the NAND gate73becomes “L”.

As such, the gate signal xstup of the transistor74falls from “H” to “L”, the transistor74turns ON, and the control voltage Vcntl continuously changes and gradually rises.

Although the control voltage Vcntl continuously rises during the period P1from the timing t0to t2, the control voltage Vcntl is lower, for example, than the threshold voltage Vth of the nMOS transistors Qn3, Qn4in each of the delay units100(101to112) as described with reference toFIG. 2(Vcntl<Vth). As such, the respective delay units101to112in the VCDL1do not propagate a signal.

Next, at timing t2, when the control voltage Vcntl exceeds the threshold voltage Vth (Vcntl>Vth), the delay units101to112are actuated, and each delay unit starts signal propagation operation that gives a delay amount according to the control voltage Vcntl to the respective input signals and outputs as an output signal.

Although the control voltage Vcntl further continues to rise during the period P2, the signal is not transmitted to the delay unit111(waveform-shaping unit211), then, at timing t3, a feedback clock signal FB (CK360) is output from the waveform-shaping unit211.

Then, during the period P3, the feedback clock signal FB output at timing t3is processed by the flipflops711to713in the startup circuit7, and, at a third rising timing t4of the signal FB, the transistor74turns OFF.

In other words, the feedback clock signal FB is input to the clock inputs CK of the three stages of the flipflops711to713, and, at the third rising timing t4of the signal FB, the data output (Q) of the flipflop713changes from “L” to “H”.

As such, the output of the inverter722changes from “H” to “L”, the output signal (xstup) of the NAND gate73rises from “L” to “H”, the transistor74turns OFF, and the startup circuit7stops.

By the operation of the startup circuit7(transistor74) upon activation, the control voltage Vcntl becomes a voltage around the target lock voltage Vlock. Note that the operation after timing t4when the transistor74turns OFF, i.e., the operation during the period P4is, for example, the same as described with reference toFIGS. 1 to 5D.

Note that, at timing t4when the startup circuit7stops, the control voltage Vcntl is preferably set to a voltage around the lock voltage Vlock and higher than Vlock (Vcntl>Vlock).

In order to set the control voltage Vcntl appropriate Vcntl>Vlock, for example, the number of stages of the flipflops (711to713) and the size of the pMOS transistor74in the startup circuit7are adjusted. Alternatively, as will be described with reference toFIG. 10, by adjusting the values of capacitors81,82provided at the input of the VCDL1, appropriate Vcntl>Vlock may be realized.

In other words, as the number of stages of the flipflops (711to713) increases, the period during which the startup circuit7operates may be longer, while, as the size of the transistor74becomes larger, the drive capability that pulls up the control voltage Vcntl may be higher. Note that, as the values of the capacitors81,82provided at the input of the VCDL1are larger, the period during which the startup circuit7operates may be longer.

As such, the timing adjustment circuit of the first embodiment may normally operate without malfunctioning, such as the control voltage Vcntl stays at the power supply voltage VDD, for example, even when the frequency of the input clock signal CLK is high and the operable phase range of the PFD3is narrow.

In the above embodiment, as the startup circuit7does not operate except upon startup, i.e., the transistor74is OFF except upon startup, the startup circuit7does not affect generation operation of multi-phase clocks when the timing control circuit is performing normal operation.

Note that, as described above, the reference clock signal REF and the feedback clock signal FB are controlled so that the reference clock signal REF and the feedback clock signal FB are masked by the mask circuits61and62for a predetermined period and the signal REF′ is output after the signal FB′ is output to be given to the PFD3.

In other words, after setting the control voltage Vcntl upon activation by the startup circuit7at timing t4, the feedback clock signal FB′ rises first, then, the reference clock signal REF′ rises. In such a case, the DOWN signal DN is output first from the PFD3. The same is applied to the other embodiments as will be described below.

FIG. 10is a block diagram depicting a second embodiment of the timing adjustment circuit. As depicted from the comparison ofFIG. 10and the above-describedFIG. 7, the timing adjustment circuit of the second embodiment has additional capacitors81,82and resistors83,84with reference to the timing adjustment circuit of the first embodiment.

As such, in the timing adjustment circuit of the second embodiment, differential clock signals CLKp, CLKm are input to differential inputs INp, INm of the first stage delay unit101in the VCDL (voltage-controlled delay line)1via the capacitors81,82. In other words, the input clock signal CLK (CLKp, CLKm) is input to the VCDL1(the first stage delay unit101) via capacitive coupling.

Further, in the first stage delay unit101, a resistor83is provided between the positive logic input INp and the negative logic output OUTm, as well as, a resistor84is provided between the negative logic input INm and the positive logic output OUTp, so as to make the common mode voltage Vcm closer to a predetermined voltage level.

FIG. 11is a diagram illustrating the operation of the timing adjustment circuit of the second embodiment depicted inFIG. 10. InFIG. 11, the reference sign0(VCDL) and Vcm0indicate respectively a differential output signal of the delay unit103and the common voltage, and360(VCDL) and Vcm360indicate respectively a differential output signal of the delay unit111and the common voltage.

As depicted inFIG. 11, when the startup circuit7is activated (transistor74turns ON) at timing t0, the control voltage Vcntl gradually rises during the period P1. However, as the control voltage Vcntl is lower than the threshold voltage Vth, the delay units101to112do not propagate signals.

Next, at timing t2, when Vcntl becomes larger than Vth, the delay units101to112start propagating signals. However, the signals are propagated, the differential output signals0(VCDL),360(VCDL) and the common voltages Vcm0, Vcm360of the delay units103,111as depicted in the period P2ofFIG. 11, yet, the signals become hard to be transmitted to the waveform-shaping units203,211.

In other words, due to the capacitors81,82provided at the first stage delay unit101, the differential output signal360(VCDL) of the delay unit111becomes a signal with small amplitude as the common voltage Vcm360is unstable, which makes hard to drive the waveform-shaping unit (CMOS buffer)211. As such, the period until timing t3when the common voltage Vcm360becomes stable and the waveform-shaping unit211is driven to output the feedback clock signal FB becomes long.

Note that the operation after timing t4when the transistor74turns OFF (the startup circuit7stops), i.e., the operation during the period P4, is, for example, the same as described with reference toFIGS. 1 to 5D.

As such, the timing adjustment circuit of the second embodiment may make the period, during which the startup circuit7operates, longer by inputting the input clock signal CLK to the VCDL1(the first stage delay unit101) via the capacitive coupling. This, for example, allows decreasing the number of stages of the flipflops711to713in the startup circuit7.

FIG. 12is a block diagram depicting a third embodiment of the timing adjustment circuit. As depicted from the comparison ofFIG. 12and the above-described inFIG. 10, the timing adjustment circuit of the third embodiment, an additional common voltage control circuit9is added to the timing adjustment circuit of the second embodiment.

As depicted inFIG. 12, the common voltage control circuit9controls switches91,92using an activation signal (power down signal) PD.

In the second embodiment described with reference toFIG. 10, for example, the common voltage Vcm0of the differential output signal0(VCDL) of the delay unit103and the common voltage Vcm360of the differential output signal360(VCDL) of the delay unit111are unstable upon activation.

Thus, when the timing adjustment circuit is not activated (when power is down), the common voltage (Vcm-90) of the differential output signal of the first stage delay unit101is fixed at a predetermined voltage level (Vbias). As such, when the timing adjustment circuit is not activated, the activation signal PD is “H”, and this activation signal PD of “H” turns the switches91,92ON.

Then, in response to the falling of the activation signal PD from “H” to “L” at timing t0, the switches91,92turn OFF. As such, upon activation of the timing adjustment circuit, the switches91,92turn OFF to make the common voltage (differential output terminals OUTp, OUTm of the first stage delay unit101) a floating state.

In this way, by making the common voltage upon activation a predetermined voltage level (Vbias), for example, the length of the period P2inFIG. 11may be made stable. In other words, the circuit may be designed based on the recognition of the operation period of the startup circuit7caused by inputting a clock signal CLK to the first stage delay unit101via capacitive coupling.

FIG. 13is a block diagram depicting a fourth embodiment of the timing adjustment circuit. As depicted from the comparison ofFIG. 13and the above-describedFIG. 10, the timing adjustment circuit of the fourth embodiment is different from the timing adjustment circuit of the second embodiment in the configuration of the startup circuit7.

The timing adjustment circuit of the fourth embodiment controls the number of stages of the flipflops in the startup circuit7according to the frequency of the input clock signal CLK (CLKp, CLKm), thereby controlling the period during which the startup circuit7operates.

As depicted inFIG. 13, in the timing adjustment circuit of the fourth embodiment, the startup circuit7further includes three stages of cascade-connected flipflops751to753and an OR gate76in addition to the circuit configuration ofFIG. 10.

The feedback clock signal FB is input to the clock terminals CK of the flipflops751to753, and a high potential power supply voltage VDD is applied to the data input terminal D of the first stage flipflop751.

The data output terminal Q of the first stage flipflop751is connected to the data input terminal D of the second stage flipflop752, while the data output terminal Q of the second stage flipflop752is connected to the data input terminal D of the third stage flipflop753. The output signal from the data output terminal Q of the third stage flipflop753is supplied to the one input of the OR gate76.

Note that a selection signal SEL is supplied to the other input of the OR gate76, and the output signal of the OR gate76is supplied to the data input terminal D of the flipflop711in the startup circuit7ofFIG. 10, instead of the high potential power supply voltage VDD.

FIG. 14is a diagram illustrating the operation of the timing adjustment circuit of the fourth embodiment depicted inFIG. 13. InFIG. 14, when the frequency of the input clock signal CLK (CLKp, CLKm) is f1at the time when the selection signal SEL is high level “H” (SEL=H), the frequency of the input clock signal CLK becomes f1×2 at the time when the selection signal SEL is low level “L” (SEL=L).

Further, the reference sign Vcm360H indicates a common voltage of the differential output signal of the delay unit111when the frequency of the input clock signal CLK is f1, while Vcm360L indicates a common voltage of the differential output signal of the delay unit111when the frequency of the clock signal CLK is f1×2.

As depicted inFIG. 14, for example, when the frequency of the input clock signal CLK is f1, the selection signal SEL is “H”, and the output signal of the OR gate76becomes “H”. Therefore, since the data input terminal D of the flipflop711becomes “H”, the startup circuit7functions in the same way as above-describedFIG. 10. In other words, the startup circuit7stops at the third rising timing of the feedback clock signal FB.

On the other hand, for example, when the frequency of the input clock signal CLK is f1×2, the selection signal SEL is “L”, and the output signal of the OR gate76changes according to the signal level of the data output terminal Q of the flipflop753. Thus, the signal of the data output terminal Q of the flipflop753is input to the data input terminal D of the flipflop711, which means six stages of flipflops751to753and711to713are cascade-connected. As such, the startup circuit7stops at the sixth rising timing of the feedback clock signal FB.

In this way, the period during which the startup circuit7adjusts the control voltage Vcntl may be appropriately set whether the frequency of the CLK is, for example, f1or twice as much the f1. Note that the switching of the number of stages of the flipflops is not restricted to switching in correspondence to the two different frequencies of the input clock signal CLK.

As such, according to the timing adjustment circuit of the fourth embodiment, for example, even when an input clock signal CLK with a different frequency is adopted, the ON period of the startup circuit7for adjusting the control voltage Vcntl upon activation may be appropriately set.

FIG. 15is a diagram illustrating the effect of the timing adjustment circuit of each embodiment. InFIG. 15, the reference sign L1indicates a relationship between a control voltage Vcntl using a high-speed (high drive capability) transistor and time, while L3indicates a relationship between a control voltage Vcntl using a low-speed (low drive capability) transistor and time. Further, L2indicates a relationship between a control voltage Vcntl using a middle-speed transistor and time.

Meanwhile, when producing semiconductors, for example, the characteristics of the transistors sometimes vary. According to the timing adjustment circuit of the embodiments, the control voltage Vcntl may be set to the target lock voltage Vlock where stationary operation is performed, regardless of the characteristics of the transistors.

In other words, as depicted by L1ofFIG. 15, when the operation speed of the transistor of a produced timing adjustment circuit is high, the control voltage Vcntl may be set to a lock voltage Vlock1that is suitable for the timing adjustment circuit using the high-speed transistor.

Further, as depicted by L3ofFIG. 15, when the operation speed of the transistor of a produced timing adjustment circuit is low, the control voltage Vcntl may be set to a lock voltage Vlock3that is suitable for the timing adjustment circuit using the low-speed transistor.

Furthermore, as depicted by L2ofFIG. 15, when the operation speed of the transistor of a produced timing adjustment circuit is intermediate, the control voltage Vcntl may be set to a lock voltage Vlock2that is suitable for the timing adjustment circuit using the middle-speed transistor.

In this way, with the timing adjustment circuit of each embodiment, even when the characteristics of the transistors vary, the control voltage Vcntl may be adjusted to a voltage around the lock voltage Vlock (Vlock1to Vlock3) suitable for the characteristics of the transistor.

Thus, for example, even when the frequency of the input clock signal CLK is high and the operable phase range of the PFD3is narrow, the timing adjustment circuit may operate normally by eliminating malfunction of the PFD3.

FIG. 16is a block diagram depicting an example of the semiconductor integrated circuit device that adopts the timing adjustment circuit of the embodiments.FIG. 16depicts a clock data recovery (CDR) circuit.

As depicted inFIG. 16, the CDR circuit includes a timing adjustment circuit (DLL circuit)20, a clock extraction circuit21, and a data reproduction circuit22. InFIG. 16, the timing adjustment circuit of each of the above-described embodiments is adopted as a circuit20. Note that, inFIG. 16, the delay units101to112and the waveform-shaping units203to211are drawn as inverters (delay elements)11to1n.

The serial data Din input from outside is separated into a clock signal CLK and a data signal (data component) SD by the clock extraction circuit21, and the clock signal CLK is input to the timing adjustment circuit20.

The timing adjustment circuit20receives the clock signal CLK, generates a plurality of clocks with different phases (multi-phase clocks) and outputs to the data reproduction circuit22(an internal circuit). The data reproduction circuit22receives the data component SD from the clock extraction circuit21, determines the level according to the multi-phase clocks, and outputs predetermined parallel data Dout.

When the multi-phase clocks received from the timing adjustment circuit20is, for example, eight-phase clocks, the data reproduction circuit22outputs 8-bit parallel data Dout by incorporating the serial data component SD at a rising timing of the eight-phase clocks. Note that when the bit rate of the data component SD (serial data Din) is A [bps], the bit rate of the parallel data Dout becomes A/8 [bps].

Note that the CDR circuit depicted inFIG. 16is merely an example of the semiconductor integrated circuit device that adopts the timing adjustment circuit of the embodiments. The timing adjustment circuit of the embodiments may be widely adopted, for example, in a variety of semiconductor integrated circuit devices that use multi-phase clocks.