SEMICONDUCTOR DEVICE

To provide a semiconductor device with less variations in characteristics. The semiconductor device includes a first circuit region and a second circuit region over a substrate, where the first circuit region includes a plurality of first transistors and a first insulator over the plurality of first transistors; the second circuit region includes a plurality of second transistors and a second insulator over the plurality of second transistors; the second insulator includes an opening portion; the first transistors and the second transistors each include an oxide semiconductor; a third insulator is positioned over and in contact with the first insulator and the second insulator; the first insulator, the second insulator, and the third insulator inhibit oxygen diffusion; and the density of the plurality of first transistors arranged in the first circuit region is higher than the density of the plurality of second transistors arranged in the second circuit region.

TECHNICAL FIELD

One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

Note that in this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, and a storage device are each one embodiment of a semiconductor device. It can be sometimes said that a display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a storage device, a semiconductor circuit, an imaging device, an electronic device, and the like include a semiconductor device.

BACKGROUND ART

In recent years, semiconductor devices have been developed to be mainly used for an LSI, a CPU, a memory, or the like. A CPU is an aggregation of semiconductor elements; the CPU includes a semiconductor integrated circuit (including at least a transistor and a memory) separated from a semiconductor wafer, and is provided with an electrode that is a connection terminal.

A semiconductor circuit (IC chip) of an LSI, a CPU, a memory, or the like is mounted on a circuit board, for example, a printed wiring board, to be used as one of components of a variety of electronic devices.

A technique by which a transistor is formed using a semiconductor thin film formed over a substrate having an insulating surface has been attracting attention. The transistor is used in a wide range of electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to the transistor; in addition, an oxide semiconductor has been attracting attention as another material.

It is known that a transistor using an oxide semiconductor has an extremely low leakage current in an off state. For example, a low-power-consumption CPU utilizing a feature of a low leakage current of the transistor using an oxide semiconductor is disclosed (see Patent Document 1). Furthermore, for example, a storage device that can retain stored contents for a long time by utilizing a feature of a low leakage current of the transistor using an oxide semiconductor is disclosed (see Patent Document 2).

In recent years, demand for an integrated circuit with higher density has risen with reductions in size and weight of electronic devices. Furthermore, the productivity of a semiconductor device including an integrated circuit is required to be improved.

REFERENCE

Patent Document

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

An object of one embodiment of the present invention is to provide a semiconductor device with small variations in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with favorable reliability. Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with a high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

Note that the descriptions of these objects do not preclude the existence of other objects. One embodiment of the present invention does not have to achieve all these objects. Other objects are apparent from the descriptions of the specification, the drawings, the claims, and the like, and other objects can be derived from the descriptions of the specification, the drawings, the claims, and the like.

Means for Solving the Problems

One embodiment of the present invention includes a first circuit region and a second circuit region over a substrate, where the first circuit region includes a plurality of first transistors and a first insulator over the plurality of first transistors; the second circuit region includes a plurality of second transistors and a second insulator over the plurality of second transistors; the second insulator includes an opening portion; the first transistors and the second transistors each include an oxide semiconductor; a third insulator is positioned over and in contact with the first insulator and the second insulator; the first insulator, the second insulator, and the third insulator inhibit oxygen diffusion; and the density of the plurality of first transistors arranged in the first circuit region is higher than the density of the plurality of second transistors arranged in the second circuit region.

One embodiment of the present invention includes a first circuit region, a second circuit region, and a third circuit region over a substrate, where the first circuit region includes a plurality of first transistors and a first insulator over the plurality of first transistors; the second circuit region includes a plurality of second transistors and a second insulator over the plurality of second transistors; the second insulator includes a first opening portion, the third circuit region includes a plurality of third transistors and a third insulator over the plurality of third transistors; the third insulator includes a second opening portion; the first transistors, the second transistors, and the third transistors each include an oxide semiconductor; a fourth insulator is positioned over and in contact with the first insulator, the second insulator, and the third insulator; the first insulator, the second insulator, the third insulator, and the fourth insulator inhibit oxygen diffusion; the density of the plurality of first transistors arranged in the first circuit region is higher than the density of the plurality of second transistors arranged in the second circuit region and the density of the plurality of third transistors arranged in the third circuit region; the density of the plurality of second transistors arranged in the second circuit region is higher than the density of the plurality of third transistors arranged in the third circuit region; and the proportion of the total area of the first opening portion in the second circuit region is higher than the proportion of the total area of the second opening portion in the third circuit region.

The above oxide semiconductor contains at least any one selected from In, Ga, and Zn.

One embodiment of the present invention is a method for manufacturing a semiconductor device, in which first transistors and second transistors are formed in a first region and a second region over a substrate, respectively; a first insulating film is formed over the first transistors and the second transistors; a second insulating film is formed over the first insulating film; oxygen adding treatment is performed on the first insulating film through the second insulating film; a third insulating film is formed over the second insulating film; the second insulating film and the third insulating film are partly removed in the second region to form opening portions exposing the first insulating film; heat treatment is performed; a fourth insulating film is formed over the first insulating film and the third insulating film; and the density of the first transistors arranged in the first region is higher than the density of the second transistors arranged in the second region.

One embodiment of the present invention is a method for manufacturing a semiconductor device, in which first transistors, second transistors, and third transistors are formed in a first region, a second region, and a third region over a substrate, respectively; a first insulating film is formed over the first transistors, the second transistors, and the third transistors; a second insulating film is formed over the first insulating film; oxygen adding treatment is performed on the first insulating film through the second insulating film; a third insulating film is formed over the second insulating film; the second insulating film and the third insulating film are partly removed in the second region and the third region to form opening portions exposing the first insulating film; heat treatment is performed; a fourth insulating film is formed over the first insulating film and the third insulating film; the density of the first transistors arranged in the first region is higher than the density of the second transistors arranged in the second region; the density of the second transistors arranged in the second region is higher than the density of the third transistors arranged in the third region; and the proportion of the total area of the opening portion in the second region is higher than the proportion of the total area of the opening portion in the third region.

In the above, the first transistors, the second transistors, and the third transistors each include an oxide semiconductor containing any one or more selected from In, Ga, and Zn.

In the above, the second insulating film is a silicon oxide film, and the third insulating film is aluminum oxide.

In the above, the oxygen adding treatment is performed by an ion implantation method.

In the above, the heat treatment is performed at higher than or equal to 250° C. and lower than or equal to 650° C.

In the above, the heat treatment is performed at higher than or equal to 350° C. and lower than or equal to 400° C.

Effect of the Invention

According to one embodiment of the present invention, a semiconductor device with small variations in transistor characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with favorable reliability can be provided. According to another embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with a high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided.

Note that the descriptions of these effects do not preclude the existence of other effects. One embodiment of the present invention does not have to have all these effects. Other effects are apparent from the descriptions of the specification, the drawings, the claims, and the like, and other effects can be derived from the descriptions of the specification, the drawings, the claims, and the like.

MODE FOR CARRYING OUT THE INVENTION

In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, they are not limited to the illustrated scale. Note that the drawings schematically illustrate ideal examples, and shapes, values, and the like are not limited to those shown in the drawings. For example, in the actual manufacturing process, a layer, a resist mask, or the like might be unintentionally reduced in size by treatment such as etching, which might not be reflected in the drawings for easy understanding. Furthermore, in the drawings, the same reference numerals are used in common for the same portions or portions having similar functions in different drawings, and repeated description thereof is omitted in some cases. Furthermore, the same hatch pattern is used for the portions having similar functions, and the portions are not especially denoted by reference numerals in some cases.

Furthermore, especially in a top view (also referred to as a “plan view”), a perspective view, or the like, the description of some components might be omitted for easy understanding of the invention. In addition, some hidden lines and the like might not be illustrated.

The ordinal numbers such as “first” and “second” in this specification and the like are used for convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, the term “first” can be replaced with the term “second”, “third”, or the like as appropriate. In addition, the ordinal numbers in this specification and the like do not sometimes correspond to the ordinal numbers that are used to specify one embodiment of the present invention.

Moreover, in this specification and the like, terms for describing arrangement, such as “over” and “under”, are used for convenience to describe the positional relation between components with reference to drawings. The positional relationship between components is changed as appropriate in accordance with a direction in which the components are described. Thus, without limitation to terms described in this specification, the description can be changed appropriately depending on the situation.

When this specification and the like explicitly state that X and Y are connected, for example, the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected are regarded as being disclosed in this specification and the like. Accordingly, without being limited to a predetermined connection relationship, for example, a connection relationship shown in drawings or texts, a connection relationship other than one shown in drawings or texts is regarded as being disclosed in the drawings or the texts. Here, X and Y each denote an object (e.g., a device, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, or a layer).

In this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. In addition, the transistor includes a region where a channel is formed (hereinafter also referred to as a channel formation region) between the drain (a drain terminal, a drain region, or a drain electrode) and the source (a source terminal, a source region, or a source electrode), and a current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, a channel formation region refers to a region through which a current mainly flows.

Furthermore, functions of a source and a drain are sometimes interchanged with each other when transistors having different polarities are used or when the direction of current is changed in circuit operation, for example. Therefore, the terms “source” and “drain” can sometimes be interchanged with each other in this specification and the like.

Note that a channel length refers to, for example, a distance between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is in an on state) and a gate electrode overlap each other or a channel formation region in a top view of the transistor. Note that in one transistor, channel lengths in all regions do not necessarily have the same value. In other words, the channel length of one transistor is not fixed to one value in some cases. Thus, in this specification, the channel length is any one of the values, the maximum value, the minimum value, or the average value in a channel formation region.

The channel width refers to, for example, the length of a channel formation region in a direction perpendicular to a channel length direction in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is in an on state) and a gate electrode overlap each other, or a channel formation region in a top view of the transistor. Note that in one transistor, channel widths in all regions do not necessarily have the same value. In other words, the channel width of one transistor is not fixed to one value in some cases. Thus, in this specification, the channel width is any one of the values, the maximum value, the minimum value, or the average value in a channel formation region.

Note that in this specification and the like, depending on the transistor structure, a channel width in a region where a channel is actually formed (hereinafter also referred to as an “effective channel width”) is sometimes different from a channel width shown in a top view of a transistor (hereinafter also referred to as an “apparent channel width”). For example, in a transistor whose gate electrode covers a side surface of a semiconductor, the effective channel width is larger than the apparent channel width, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor whose gate electrode covers a side surface of a semiconductor, the proportion of a channel formation region formed in the side surface of the semiconductor is increased in some cases. In that case, the effective channel width is larger than the apparent channel width.

In such a case, the effective channel width is sometimes difficult to estimate by actual measurement. For example, estimation of an effective channel width from a design value requires assumption that the shape of a semiconductor is known. Accordingly, in the case where the shape of a semiconductor is not known accurately, it is difficult to measure the effective channel width accurately.

In this specification, the simple term “channel width” refers to an apparent channel width in some cases. Alternatively, in this specification, the simple term “channel width” refers to an effective channel width in some cases. Note that values of a channel length, a channel width, an effective channel width, an apparent channel width, and the like can be determined, for example, by analyzing a cross-sectional TEM image and the like.

Note that impurities in a semiconductor refer to, for example, elements other than the main components of a semiconductor. For example, an element with a concentration lower than 0.1 atomic % can be regarded as an impurity. When an impurity is contained, for example, the density of defect states in a semiconductor increases and the crystallinity decreases in some cases. In the case where the semiconductor is an oxide semiconductor, examples of an impurity which changes the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 13 elements. Group 14 elements, Group 15 elements, and transition metals other than the main components of the oxide semiconductor; hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen are given as examples. Note that water also serves as an impurity in some cases. In addition, oxygen vacancies (also referred to as VO) are formed in an oxide semiconductor in some cases by entry of impurities, for example.

Note that in this specification and the like, silicon oxynitride is a material that contains more oxygen than nitrogen in its composition. Moreover, silicon nitride oxide is a material that contains more nitrogen than oxygen in its composition.

In this specification and the like, the term “insulator” can be replaced with an insulating film or an insulating layer. Furthermore, the term “conductor” can be replaced with a conductive film or a conductive layer. Moreover, the term “semiconductor” can be replaced with a semiconductor film or a semiconductor layer.

In this specification and the like, “parallel” indicates a state where two straight lines are placed at an angle greater than or equal to −10° and less than or equal to 10°. Accordingly, the case where the angle is greater than or equal to −5° and less than or equal to 5° is also included. Furthermore, “substantially parallel” indicates a state where two straight lines are placed at an angle greater than or equal to −30° and less than or equal to 30°. Moreover, “perpendicular” indicates a state where two straight lines are placed at an angle greater than or equal to 80° and less than or equal to 100°. Accordingly, the case where the angle is greater than or equal to 85° and less than or equal to 95° is also included. Furthermore, “substantially perpendicular” indicates a state where two straight lines are placed at an angle greater than or equal to 60° and less than or equal to 120°.

In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also simply referred to as an OS), and the like. For example, in the case where a metal oxide is used in a semiconductor layer of a transistor, the metal oxide is referred to as an oxide semiconductor in some cases. That is, an OS transistor can also be called a transistor including a metal oxide or an oxide semiconductor.

In this specification and the like, “normally off” means that a drain current per micrometer of channel width flowing through a transistor when no potential is applied to a gate or the gate is supplied with a ground potential is 1×10−20A or lower at room temperature, 1×10−18A or lower at 85° C., or 1×10−16A or lower at 125° C.

In this embodiment, examples of a semiconductor device500of embodiments of the present invention and manufacturing methods thereof are described with reference toFIG.1toFIG.26.

The semiconductor device500includes, over the same substrate, a plurality of regions including circuits, and an outer edge of the regions including the circuits, that is, a peripheral region in which the circuits are not included.

FIG.1illustrates an example of the semiconductor device500.FIG.1is a top view of the semiconductor device500. The semiconductor device500includes a plurality of elements, and a circuit region510, a circuit region512, and a circuit region514in each of which a circuit is included. In addition, a peripheral region516is provided between the circuit region510and the circuit region512, between the circuit region512and the circuit region514, and between the circuit region510and the circuit region514. The peripheral region516is also provided between the edge of the substrate and each of the circuit region510, the circuit region512, and the circuit region514.

FIG.2Ais a top view of the circuit region510,FIG.2Bis a top view of the circuit region512, andFIG.2Cis a top view of the circuit region514. As illustrated inFIG.2, each of the circuit regions includes at least a plurality of transistors200and a sealing portion265.

The peripheral region516does not necessarily need to be provided between the circuit regions. For example, the circuit regions may be separated by the sealing portion265provided so as to be shared by the circuit region510and the circuit region512.

In the transistors200, a metal oxide functioning as a semiconductor (hereinafter, also referred to as an oxide semiconductor) is preferably used in a channel formation region.

A transistor including an oxide semiconductor in its channel formation region has an extremely low leakage current in an off state; thus, a semiconductor device with low power consumption can be provided. On the other hand, the transistor including an oxide semiconductor easily has normally-on characteristics (the characteristics are that a channel exists without voltage application to a gate electrode and a current flows in a transistor) owing to impurities and oxygen vacancies in the oxide semiconductor that affect the electrical characteristics.

Therefore, it is preferable to use, as the oxide semiconductor used for the channel formation region of the transistor, a highly purified intrinsic oxide semiconductor in which impurities and oxygen vacancies are reduced. In this specification and the like, a state with a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic state. In order to make the oxide semiconductor highly purified intrinsic, oxygen vacancies in the oxide semiconductor can be compensated for with oxygen to reduce the oxygen vacancies.

Specifically, an insulator containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen) is provided in the vicinity of the oxide semiconductor so that oxygen can be supplied from the insulator to the oxide semiconductor to reduce oxygen vacancies when heat treatment is performed.

In order to provide the insulator containing excess oxygen in the vicinity of the oxide semiconductor, oxygen adding treatment (hereinafter also referred to as oxygen adding treatment, oxygen implantation treatment, or oxygen doping treatment) is preferably performed on the insulator. Specifically, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used for oxygen adding treatment. Plasma treatment may be performed on the insulator to implant oxygen thereinto. A dry etching apparatus, a plasma CVD apparatus, a sputtering apparatus, or the like can be used as a plasma generating apparatus.

The circuit regions are preferably sealed with a material that inhibits oxygen diffusion. When sealed in the circuit regions, in heat treatment, excess oxygen can be inhibited from being released to the outside of the circuit regions and can be supplied to the oxide semiconductor efficiently. A material that inhibits oxygen diffusion may inhibit diffusion of hydrogen, water, and impurities that adversely affect an oxide semiconductor. Thus, sealing each of the circuit regions can inhibit diffusion of impurities from the outside of the substrate and other structure bodies, leading to improvement in the reliability of the semiconductor device.

However, too much oxygen supplied to a source region or a drain region might decrease the on-state current or the field-effect mobility of the transistor. Furthermore, uneven in-plane distribution of oxygen supplied to the source region or the drain region would cause variations in the characteristics of the semiconductor device including the transistor.

Thus, the amount of excess oxygen to be released from the insulator in the vicinity of the oxide semiconductor needs to be adjusted so as to make the oxide semiconductor highly purified intrinsic and not to influence the source region and the drain region.

For example, in the semiconductor device500illustrated inFIG.1andFIG.2, the circuit region510and the circuit region514are different from each other in the density of the transistors200per unit area. Specifically, in the case where the density of transistors arranged in the circuit region510is higher than that in the circuit region514as illustrated inFIG.2, the amount of excess oxygen required in the circuit region510is larger than that required in the circuit region514.

Thus, oxygen adding treatment is performed on the entire surface of the substrate including the circuit region510and the circuit region514. By the oxygen adding treatment, an excess oxygen region is provided in the insulator positioned in the vicinity of the oxide semiconductor of the transistor200. For the oxygen adding treatment, excess oxygen whose amount is required in the circuit region having the highest arrangement density of transistors among the plurality of circuit regions is preferably implanted. Specifically, excess oxygen whose amount is required in the circuit region510having a higher arrangement density of transistors than the circuit region514is preferably implanted.

Next, a film that inhibits oxygen diffusion is provided so as to cover the circuit region510and the circuit region514. Here, a plurality of opening regions400are provided in the film that inhibits oxygen diffusion and covers the circuit region514. After that, heat treatment is performed to release oxygen from the insulator positioned in the vicinity of the oxide semiconductor to supply oxygen to the oxide semiconductor, whereby the oxygen vacancies in the channel formation region are compensated for.

In the circuit region514, when heat treatment is performed, part of excess oxygen released from the insulator positioned in the vicinity of the oxide semiconductor is released from the opening regions400to the outside. Another part of excess oxygen is supplied to the oxide semiconductor, whereby oxygen vacancies in the channel formation region can be compensated for. That is, redundant excess oxygen added by the oxygen adding treatment is released from the opening regions400in the circuit region514, whereby the amount of excess oxygen released from the insulator in the vicinity of the oxide semiconductor can be adjusted so as not to influence the source region and the drain region.

In contrast, in the circuit region510, excess oxygen released when heat treatment is performed is supplied to the oxide semiconductor without being released to the outside, so that oxygen vacancies in the channel formation region can be compensated for.

Hence, according to the present invention, the circuit region510and the circuit region514can be provided over the same substrate without adding a mask.

In the case where the opening regions400are appropriately designed in accordance with the arrangement density of transistors, the plurality of circuit regions can be provided over the same substrate.

For example, the circuit region512, which has a lower arrangement density of transistors than the circuit region510and has a higher arrangement density of transistors than the circuit region514, may be provided. As illustrated inFIG.2B, the circuit region512includes a smaller number of transistors200per unit area than the circuit region510but includes the opening regions400. On the other hand, it is preferable that the circuit region512include a larger number of transistors200per unit area but a smaller area of the opening regions400than the circuit region514. Alternatively, the proportion of the total area of the opening regions400(the product of the area of one of the opening regions400in the top view and the number of opening regions400) in the circuit region512is preferably lower than that in the circuit region514.

In other words, as the density of the transistors200arranged in each of the circuit regions increases, the number of opening regions400is reduced. Alternatively, as the density of the transistors200arranged in each of the circuit regions increases, the ratio of the total area of the opening portions to the area of the circuit region is preferably reduced. The number of transistors200and the number of opening regions400included in each of the circuit regions are not limited to those inFIG.2. The number of opening regions400arranged in each of the circuit regions can be adjusted appropriately in accordance with the density of the transistors200arranged in the circuit region.

Thus, in the case where the plurality of circuit regions having different arrangement densities of transistors are provided over the same substrate, excess oxygen required in the circuit region having a high arrangement density of transistors is added to the insulator positioned in the vicinity of the oxide semiconductor, and then, a film that inhibits oxygen diffusion and includes opening regions is provided and heat treatment is performed, whereby optimal amounts of excess oxygen can be supplied to the respective circuit regions.

In the case where the plurality of circuit regions having different arrangement densities of transistors are included, the number of opening regions400provided is preferably inversely proportional to the arrangement density of the transistors200, for example. Alternatively, it is preferable that the total area of the opening regions400increase as the arrangement density of the transistors200decreases and the total area of the opening regions400decrease as the arrangement density of the transistors200increases.

FIG.3Ais an enlarged view of a region291surrounded by dashed-dotted line inFIG.2C.FIG.3Bis across-sectional view of a portion indicated by dashed-dotted line A1-A2inFIG.3A, i.e., a cross-sectional view in the channel direction of the transistor200and a cross-sectional view of the sealing portion265.FIG.3Cis a cross-sectional view of a portion indicated by dashed-dotted line A3-A4inFIG.3A, i.e., a cross-sectional view of the opening region400and a cross-sectional view of the sealing portion265.

As illustrated inFIG.3A, the transistor200is positioned with a distance L1from the end portion of the transistor200to the end portion of the sealing portion265in the A1-A2direction, and positioned with a distance L2from the end portion of the transistor200to the end portion of the sealing portion265in the direction perpendicular to A1-A2. The opening regions400are positioned at intervals of a distance L3in the direction perpendicular to A1-A2. Here, the distance L3is the distance between the upper portions of the adjacent opening regions in the direction perpendicular to A1-A2. The shape of the opening region400in the top view is not limited to a rectangle illustrated inFIG.3A. Examples of the shape of the opening region400in the top view include a square shape, an elliptical shape, a circular shape, a rhombus shape, and a shape obtained by combining any of these shapes. The distance L1and the distance L2are each greater than or equal to 0.10 μm and less than or equal to 2.0 μm, preferably greater than or equal to 0.15 μm and less than or equal to 1.5 μm. The distance L3is greater than or equal to 1.5 μm and less than or equal to 6.0 μm. Typically, 1.5 μm is employed.

As illustrated inFIG.3BandFIG.3C, the semiconductor device500includes an insulator212over a substrate (not illustrated), an insulator214over the insulator212, the plurality of transistors200over the insulator214, an insulator280over the transistors200, an insulator282over the insulator280, an insulator283over the insulator282, the sealing portion265where part of the top surface of the insulator212is in contact with the insulator283, and the opening regions400opened at parts of the insulator282. In the opening region400, the insulator280may have a depressed portion, and the depth of the depressed portion in the insulator280is greater than or equal to ¼ and less than or equal to ½ of the largest thickness of the insulator280in the semiconductor device500.

When heat treatment is performed after the formation of the opening regions400in the manufacturing process of the semiconductor device500, oxygen contained in the insulator280and hydrogen bonded to the oxygen can be released to the outside through the opening regions400. The hydrogen bonded to oxygen is released as water. Thus, unnecessary oxygen and hydrogen contained in the insulator280can be reduced.

<Structure Example of Semiconductor Device>

A structure example of a semiconductor device including the transistor200and the opening region400is described with reference toFIG.4AtoFIG.4D.FIG.4AtoFIG.4Dare a top view and cross-sectional views of the semiconductor device including the transistor200and the opening region400.FIG.4Ais a top view of the semiconductor device.FIG.4Bto FIG.4D are cross-sectional views of the semiconductor device. Here,FIG.4Bis a cross-sectional view of a portion indicated by the dashed-dotted line A1-A2inFIG.4A, i.e., a cross-sectional view of the transistor200in the channel length direction.FIG.4Cis a cross-sectional view of a portion indicated by the dashed-dotted line A3-A4inFIG.4A, i.e., a cross-sectional view of the transistor200in the channel width direction.FIG.4Dis a cross-sectional view of a portion indicated by dashed-dotted line A5-A6inFIG.4Aand is also a cross-sectional view of the opening region400. For clarity of the drawing, some components are not illustrated in the top view ofFIG.4A.

The semiconductor device of one embodiment of the present invention includes the insulator212over a substrate (not illustrated), the insulator214over the insulator212, the transistor200over the insulator214, the insulator280over the transistor200, the insulator282(an insulator282aand an insulator282b) over the insulator280, the insulator283over the insulator282, an insulator286over the insulator283, and an insulator274over the sealing portion265. The insulator283is in contact with a side surface of the insulator282, a side surface of the insulator280, a side surface of the transistor200, a side surface of the insulator214, and part of the top surface of the insulator212. The insulator212, the insulator214, the insulator280, the insulator282, the insulator283, the insulator286, and the insulator274function as interlayer films. A conductor240(a conductor240aand a conductor240b) that is electrically connected to the transistor200and functions as a plug is also included. An insulator241(an insulator241aand an insulator241b) is provided in contact with side surfaces of the conductor240functioning as a plug. A conductor246(a conductor246aand a conductor246b) that is electrically connected to the conductor240and functions as a wiring is provided over the insulator286and the conductor240.

The insulator241ais provided in contact with the inner wall of an opening in the insulator280, the insulator282, the insulator283, and the insulator286; a first conductor of the conductor240ais provided in contact with a side surface of the insulator241a; and a second conductor of the conductor240ais provided on the inner side thereof. The insulator241bis provided in contact with the inner wall of an opening in the insulator280, the insulator282, the insulator283, and the insulator286; a first conductor of the conductor240bis provided in contact with a side surface of the insulator241b; and a second conductor of the conductor240bis provided on the inner side thereof. Here, the level of the top surface of the conductor240and the level of the top surface of the insulator286in a region overlapping the conductor246can be substantially the same. Note that although the transistor200is illustrated to have a structure in which the first conductor of the conductor240and the second conductor of the conductor240are stacked, the present invention is not limited thereto. For example, the conductor240may be provided as a single layer or so as to have a stacked-layer structure of three or more layers. In the case where a structure body has a stacked-layer structure, layers may be distinguished by ordinal numbers given according to the formation order.

As illustrated inFIG.4AtoFIG.4C, the transistor200includes an insulator216over the insulator214; a conductor205(a conductor205a, a conductor205b, and a conductor205c) placed to be embedded in the insulator214or the insulator216; an insulator222over the insulator216and the conductor205; an insulator224over the insulator222; an oxide230aover the insulator224; an oxide230bover the oxide230a; an oxide243(an oxide243aand an oxide243b) over the oxide230b; a conductor242aover the oxide243a; an insulator271aover the conductor242a; a conductor242bover the oxide243b; an insulator271bover the conductor242b; an insulator250aover the oxide230b; an insulator250bover the insulator250a; a conductor260(a conductor260aand a conductor260b) that is placed over the insulator250band overlaps part of the oxide230b; and an insulator272placed so as to cover the insulator224, the oxide230(the oxide230aand the oxide230b), the oxide243, the conductor242(the conductor242aand the conductor242b), and the insulator271(the insulator271aand the insulator271b). Here, as illustrated inFIG.4BtoFIG.4D, the insulator272includes a region in contact with part of the top surface of the insulator222. The top surface of the conductor260is positioned so as to be substantially aligned with the top surface of the insulator250and the top surface of the insulator280. The insulator282is in contact with the top surfaces of the conductor260, the insulator250, and the insulator280.

Hereinafter, the oxide230aand the oxide230bare collectively referred to as the oxide230in some cases. The insulator250aand the insulator250bare collectively referred to as the insulator250in some cases. The insulator271aand the insulator271bare collectively referred to as the insulator271in some cases.

An opening reaching the oxide230bis provided in the insulator280and the insulator272. The insulator250and the conductor260are placed in the opening. In addition, in the channel length direction of the transistor200, the conductor260and the insulator250are provided between the insulator271a, the conductor242a, and the oxide243a, and the insulator271b, the conductor242b, and the oxide243b. The insulator250includes a region in contact with a side surface of the conductor260and a region in contact with the bottom surface of the conductor260.

The oxide230preferably includes the oxide230aplaced over the insulator224and the oxide230bplaced over the oxide230a. Including the oxide230aunder the oxide230bmakes it possible to inhibit diffusion of impurities into the oxide230bfrom components formed below the oxide230a.

Although a structure in which two layers of the oxide230aand the oxide230bare stacked as the oxide230in the transistor200is described, the present invention is not limited thereto. For example, a single layer of the oxide230bmay be provided as the oxide230, the oxide230may have a stacked-layer structure of three or more layers, or the oxide230aand the oxide230bmay each have a stacked-laver structure.

The conductor260functions as a first gate (also referred to as a top gate) electrode, and the conductor205functions as a second gate (also referred to as a back gate) electrode. The insulator250functions as a first gate insulator, and the insulator222and the insulator224function as a second gate insulator. The conductor242afunctions as one of a source and a drain, and the conductor242bfunctions as the other of the source and the drain. At least part of a region of the oxide230that is overlapped by the conductor260functions as a channel formation region.

Here,FIG.5shows an enlarged view of the vicinity of the channel formation region inFIG.4B. As illustrated inFIG.5, the oxide230bincludes a region230bcfunctioning as the channel formation region of the transistor200and a region230baand a region230bbthat are provided to sandwich the region230bcand function as a source region and a drain region. At least part of the region230bcis overlapped by the conductor260. In other words, the region230bcis provided in a region between the conductor242aand the conductor242b. The region230bais provided so as to be overlapped by the conductor242a, and the region230bbis provided so as to be overlapped by the conductor242b.

The region230bcfunctioning as the channel formation region is a high-resistance region with a low carrier concentration because it includes a smaller amount of oxygen vacancies or has a lower impurity concentration than the region230baand the region230bb. The region230baand the region230bbfunctioning as the source region and the drain region are each a low-resistance region with an increased carrier concentration because it includes a large amount of oxygen vacancies or has a high concentration of an impurity such as hydrogen, nitrogen, or a metal element. In other words, the region230baand the region230bbare each a region having a higher carrier concentration and a lower resistance than the region230bc.

The carrier concentration in the region230bcfunctioning as the channel formation region is preferably lower than or equal to 1×1018cm−3, further preferably lower than 1×1017cm−3, still further preferably lower than 1×1016cm−3, yet further preferably lower than 1×1013cm−3, yet still further preferably lower than 1×1012cm−3. Note that the lower limit of the carrier concentration in the region230bcfunctioning as the channel formation region is not particularly limited and can be, for example, 1×10−9cm−3.

Between the region230bcand the region230baor the region230bb, a region having a carrier concentration that is lower than or substantially equal to the carrier concentrations in the region230baand the region230bband higher than or substantially equal to the carrier concentration in the region230bcmay be formed. That is, the region functions as a junction region between the region230bcand the region230baor the region230bb. The hydrogen concentration in the junction region is sometimes lower than or substantially equal to the hydrogen concentrations in the region230baand the region230bband higher than or substantially equal to the hydrogen concentration in the region230bc. The amount of oxygen vacancies in the junction region is sometimes smaller than or substantially equal to the amounts of oxygen vacancies in the region230baand the region230bband larger than or substantially equal to the amount of oxygen vacancies in the region230bc.

AlthoughFIG.5illustrates an example in which the region230ba, the region230bb, and the region230bcare formed in the oxide230b, the present invention is not limited thereto. For example, the above regions may be formed not only in the oxide230bbut also in the oxide230a.

In the oxide230, the boundaries between the regions are difficult to detect clearly in some cases. The concentration of a metal element and an impurity element such as hydrogen or nitrogen, which is detected in each region, may be gradually changed not only between the regions but also in each region. That is, the region closer to the channel formation region preferably has a lower concentration of a metal element and an impurity element such as hydrogen or nitrogen.

In the transistor200, a metal oxide functioning as a semiconductor (such a metal oxide is hereinafter also referred to as an oxide semiconductor) is preferably used as the oxide230(the oxide230aand the oxide230b) including the channel formation region.

The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. With the use of a metal oxide having such a large band gap, the off-state current of the transistor can be reduced.

As the oxide230, it is preferable to use, for example, a metal oxide such as an In-M-Zn oxide containing indium, an element M, and zinc (the element M is one or more kinds selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like). Alternatively, an In—Ga oxide, an In—Zn oxide, or an indium oxide may be used as the oxide230.

The atomic ratio of In to the element M in the metal oxide used as the oxide230bis preferably greater than the atomic ratio of In to the element M in the metal oxide used as the oxide230a.

The oxide230ais placed under the oxide230b, whereby diffusion of impurities and oxygen into the oxide230bfrom structure bodies formed below the oxide230acan be inhibited.

When the oxide230aand the oxide230bcontain a common element (as the main component) besides oxygen, the density of defect states at an interface between the oxide230aand the oxide230bcan be made low. Since the density of defect states at the interface between the oxide230aand the oxide230bcan be made low, the influence of interface scattering on carrier conduction is small, and a high on-state current can be obtained.

The oxide230bpreferably has crystallinity. It is particularly preferable to use a CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the oxide230b.

The CAAC-OS is a metal oxide having a dense structure with high crystallinity and a small amount of impurities or defects (e.g., oxygen vacancies (VO)). In particular, after the formation of a metal oxide, heat treatment is performed at a temperature at which the metal oxide does not become a polycrystal (e.g., 400° C. to 600° C. inclusive), whereby a CAAC-OS having a dense structure with higher crystallinity can be obtained. When the density of the CAAC-OS is increased in such a manner, diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

On the other hand, a clear crystal grain boundary is difficult to observe in the CAAC-OS: thus, it can be said that a reduction in electron mobility due to the crystal grain boundary is less likely to occur. Thus, a metal oxide including a CAAC-OS is physically stable. Therefore, the metal oxide including a CAAC-OS is resistant to heat and has high reliability.

If impurities and oxygen vacancies exist in a region of an oxide semiconductor where a channel is formed, a transistor using the oxide semiconductor might have variable electrical characteristics and poor reliability. In some cases, hydrogen in the vicinity of an oxygen vacancy forms a defect that is the oxygen vacancy into which hydrogen enters (hereinafter sometimes referred to as VOH), which generates an electron serving as a carrier. Therefore, when the region of the oxide semiconductor where a channel is formed includes oxygen vacancies, the transistor tends to have normally-on characteristics (characteristics with which, even when no voltage is applied to the gate electrode, the channel exists and a current flows through the transistor). Thus, impurities, oxygen vacancies, and VOH are preferably reduced as much as possible in the region of the oxide semiconductor where a channel is formed. In other words, it is preferable that the region of the oxide semiconductor where a channel is formed have a reduced carrier concentration and be of an i-type (intrinsic) or substantially i-type.

As a countermeasure to the above, an insulator containing oxygen that is released by heating (hereinafter, sometimes referred to as excess oxygen) is provided in the vicinity of the oxide semiconductor so that oxygen can be supplied from the insulator to the oxide semiconductor to reduce oxygen vacancies and VOH when heat treatment is performed. However, supply of an excess amount of oxygen to the source region or the drain region might cause a decrease in the on-state current or field-effect mobility of the transistor200. Furthermore, a variation in the amount of oxygen supplied to the source region or the drain region in the substrate plane leads to variable characteristics of the semiconductor device including the transistor.

Therefore, the region230bcfunctioning as the channel formation region in the oxide semiconductor is preferably an i-type or substantially i-type region with reduced carrier concentration, whereas the region230baand the region230bbfunctioning as the source region and the drain region are preferably n-type regions with high carrier concentrations. That is, it is preferable that oxygen vacancies and VOH in the region230bcof the oxide semiconductor be reduced and the region230baand the region230bbnot be supplied with an excess amount of oxygen.

Thus, in this embodiment, microwave treatment is performed in an oxygen-containing atmosphere in a state where the conductor242aand the conductor242bare provided over the oxide230bso that oxygen vacancies and VOH in the region230bcare reduced. Here, the microwave treatment refers to, for example, treatment using an apparatus including a power source that generates high-density plasma with the use of a microwave.

The microwave treatment in an oxygen-containing atmosphere converts an oxygen gas into plasma using a high-frequency waves such as microwaves or RF and activates the oxygen plasma. At this time, the region230bccan be irradiated with the high-frequency waves such as microwaves or RF. By the effect of the plasma, the microwave, or the like, VOH in the region230bccan be cut; thus, hydrogen H can be removed from the region230bcand an oxygen vacancy VOcan be filled with oxygen. That is, the reaction “VOH→H+VO” occurs in the region230bc, so that the hydrogen concentration in the region230bccan be reduced. As a result, oxygen vacancies and VOH in the region230bccan be reduced to lower the carrier concentration.

In the microwave treatment in an oxygen-containing atmosphere, the high-frequency waves such as microwaves or RF, the oxygen plasma, or the like is blocked by the conductor242aand the conductor242band does not affect the region230baand the region230bb. In addition, the effect of the oxygen plasma can be reduced by the insulator271a, the insulator271b, and the insulator280that are provided so as to cover the oxide230band the conductor242. Hence, a reduction in VOH and supply of an excess amount of oxygen do not occur in the region230baand the region230bbin the microwave treatment, preventing a decrease in carrier concentration.

In particular, the above effect is large when the microwave treatment is performed in an oxygen-containing atmosphere after formation of an insulating film to be the insulator250b. It is also preferable that microwave treatment be performed in an oxygen-containing atmosphere after formation of an insulating film to be the insulator250aand another microwave treatment be further performed in an oxygen-containing atmosphere after the formation of the insulating film to be the insulator250b. By performing the microwave treatment in an oxygen-containing atmosphere through the insulator250aor the insulator250bin such a manner, oxygen can be efficiently implanted into the region230bc. The oxygen implanted into the region230bchas any of a variety of forms such as an oxygen atom, an oxygen molecule, an oxygen radical (an atom, a molecule, or an ion having an unpaired electron). Note that the oxygen implanted into the region230bchas any one or more of the above forms, particularly preferably an oxygen radical. The film quality of the insulator250aand the insulator250bcan be improved, leading to higher reliability of the transistor200.

In the above manner, oxygen vacancies and VOH can be selectively removed from the region230bcof the oxide semiconductor, whereby the region230bccan be an i-type or substantially i-type region. Furthermore, supply of an excess amount of oxygen to the region230baand the region230bbfunctioning as the source region and the drain region can be inhibited and the n-type regions can be maintained. As a result, a change in the electrical characteristics of the transistor200can be inhibited, and thus, a variation in the electrical characteristics of the transistors200in the substrate plane can be inhibited.

With the above structure, a semiconductor device with a small variation in transistor characteristics can be provided. A semiconductor device having favorable reliability can also be provided. A semiconductor device having favorable electrical characteristics can be provided.

InFIG.4and the like, a side surface of the opening in which the conductor260and the like are embedded is substantially perpendicular to the formation surface of the oxide230bincluding a groove portion of the oxide230b; however, this embodiment is not limited thereto. For example, a bottom portion of the opening may have a U-shape with a moderate curve. For example, the side surface of the opening may be tilted with respect to the formation surface of the oxide230b.

As illustrated inFIG.4C, a curved surface may be provided between a side surface of the oxide230band the top surface of the oxide230bin a cross-sectional view of the transistor200in the channel width direction. In other words, an end portion of the side surface and an end portion of the top surface may be curved (hereinafter referred to as rounded).

The radius of curvature of the curved surface is preferably greater than 0 nm and less than the thickness of the oxide230bin a region overlapped by the conductor242, or less than half of the length of a region that does not have the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than or equal to 20 nm, preferably greater than or equal to 1 nm and less than or equal to 15 nm, and further preferably greater than or equal to 2 nm and less than or equal to 10 nm. Such a shape can improve the coverage of the oxide230bwith the insulator250and the conductor260.

The oxide230preferably has a stacked-layer structure of a plurality of oxide layers with different chemical compositions. Specifically, the atomic ratio of the element M to a metal element that is a main component in the metal oxide used as the oxide230ais preferably greater than the atomic ratio of the element M to a metal element that is a main component in the metal oxide used as the oxide230b. Moreover, the atomic ratio of the element M to In in the metal oxide used as the oxide230ais preferably greater than the atomic ratio of the element M to In in the metal oxide used as the oxide230b. Furthermore, the atomic ratio of In to the element M in the metal oxide used as the oxide230bis preferably greater than the atomic ratio of In to the element M in the metal oxide used as the oxide230a.

The oxide230bis preferably an oxide having crystallinity, such as a CAAC-OS. An oxide having crystallinity, such as a CAAC-OS, has a dense structure with small amounts of impurities and defects (e.g., oxygen vacancies) and high crystallinity. This can inhibit oxygen extraction from the oxide230bby the source electrode or the drain electrode. This can reduce oxygen extraction from the oxide230beven when heat treatment is performed; thus, the transistor200is stable with respect to high temperatures in a manufacturing process (what is called thermal budget).

Here, the conduction band minimum gradually changes at a junction portion of the oxide230aand the oxide230b. In other words, the conduction band minimum at the junction portion of the oxide230aand the oxide230bcontinuously changes or is continuously connected. To achieve this, the density of defect states in a mixed layer formed at the interface between the oxide230aand the oxide230bis preferably made low.

Specifically, when the oxide230aand the oxide230bcontain a common element as a main component in addition to oxygen, a mixed layer with a low density of defect states can be formed. For example, in the case where the oxide230bis an In-M-Zn oxide, an In-M-Zn oxide, an M-Zn oxide, an oxide of the element M, an In—Zn oxide, indium oxide, or the like may be used as the oxide230a.

Specifically, as the oxide230a, a metal oxide with a composition of In:M:Zn=1:3:4 [atomic ratio] or in the neighborhood thereof, or a composition of In:M:Zn=1:1:0.5 [atomic ratio] or in the neighborhood thereof is used. As the oxide230b, a metal oxide with a composition of In:M:Zn=1:1:1 [atomic ratio] or in the neighborhood thereof, a composition of In:M:Zn=4:2:3 [atomic ratio] or in the neighborhood thereof, or a composition of In:M:Zn=5:1:3 [atomic ratio] or in the neighborhood thereof is used. Note that a composition in the neighborhood includes the range of ±30% of an intended atomic ratio. Gallium is preferably used as the element M.

When the metal oxide is deposited by a sputtering method, the above atomic ratio is not limited to the atomic ratio of the formed metal oxide and may be the atomic ratio of a sputtering target used for forming the metal oxide.

When the oxide230aand the oxide230bhave the above structure, the density of defect states at the interface between the oxide230aand the oxide230bcan be made low. Thus, the influence of interface scattering on carrier conduction is small, and the transistor200can have a high on-state current and excellent frequency characteristics.

At least one of the insulator212, the insulator214, the insulator271, the insulator272, the insulator282, and the insulator283preferably functions as a barrier insulating film, which inhibits diffusion of impurities such as water and hydrogen from the substrate side or above the transistor200into the transistor200. Thus, for at least one of the insulator212, the insulator214, the insulator271, the insulator272, the insulator282, and the insulator283, it is preferable to use an insulating material that has a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (e.g., N2O, NO, or NO2), and a copper atom (through which the impurities are less likely to pass). Alternatively, it is preferable to use an insulating material that has a function of inhibiting diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like) (through which the oxygen is less likely to pass).

Note that in this specification, a barrier insulating film refers to an insulating film having a barrier property. A barrier property in this specification means a function of inhibiting diffusion of a targeted substance (also referred to as having low permeability). Alternatively, a barrier property in this specification means a function of capturing and fixing (also referred to as gettering) a targeted substance.

An insulator having a function of inhibiting diffusion of oxygen and impurities such as water and hydrogen is preferably used for the insulator212, the insulator214, the insulator271, the insulator272, the insulator282, and the insulator283; for example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, silicon nitride, which has a higher hydrogen barrier property, is preferably used for the insulator212and the insulator283. For example, aluminum oxide or magnesium oxide, which has a function of capturing or fixing hydrogen, is preferably used for the insulator214, the insulator271, the insulator272, and the insulator282. In this case, impurities such as water and hydrogen can be inhibited from diffusing to the transistor200side from the substrate side through the insulator212and the insulator214. Impurities such as water and hydrogen can be inhibited from diffusing to the transistor200side from an interlayer insulating film and the like which are provided outside the insulator283. Alternatively, oxygen contained in the insulator224and the like can be inhibited from diffusing to the substrate side through the insulator212and the insulator214. Alternatively, oxygen contained in the insulator280and the like can be inhibited from diffusing to above the transistor200through the insulator282and the like. In this manner, it is preferable that the transistor200be surrounded by the insulator212, the insulator214, the insulator271, the insulator272, the insulator282, and the insulator283, which have a function of inhibiting diffusion of oxygen and impurities such as water and hydrogen.

Here, an oxide having an amorphous structure is preferably used for the insulator212, the insulator214, the insulator271, the insulator272, the insulator282, and the insulator283. For example, a metal oxide such as AlOx(x is a given number greater than 0) or MgOy(y is a given number greater than 0) is preferably used. In such a metal oxide having an amorphous structure, an oxygen atom has a dangling bond and sometimes has a property of capturing or fixing hydrogen with the dangling bond. When such a metal oxide having an amorphous structure is used as the component of the transistor200or provided around the transistor200, hydrogen contained in the transistor200or hydrogen present around the transistor200can be captured or fixed. In particular, hydrogen contained in the channel formation region of the transistor200is preferably captured or fixed. The metal oxide having an amorphous structure is used as the component of the transistor200or provided around the transistor200, whereby the transistor200and a semiconductor device which have favorable characteristics and high reliability can be manufactured.

Although each of the insulator212, the insulator214, the insulator271, the insulator272, the insulator282, and the insulator283preferably has an amorphous structure, a region having a polycrystalline structure may be partly formed. Alternatively, each of the insulator212, the insulator214, the insulator271, the insulator272, the insulator282, and the insulator283may have a multilayer structure in which a layer having an amorphous structure and a layer having a polycrystalline structure are stacked. For example, a stacked-layer structure in which a layer having a polycrystalline structure is formed over a layer having an amorphous structure may be employed.

The insulator272may have a stacked-layer structure. For example, the insulator272may have a stacked-layer structure of aluminum oxide and silicon nitride deposited over the aluminum oxide. Such a stacked-layer structure is preferable because of its high barrier property compared with a single layer of aluminum oxide or a single layer of silicon nitride.

The insulator212, the insulator214, the insulator216, the insulator271, the insulator272, the insulator280, the insulator282, the insulator283, and the insulator286can be formed by a sputtering method, for example. Since a sputtering method does not need to use hydrogen as a deposition gas, the hydrogen concentrations in the insulator212, the insulator214, the insulator216, the insulator271, the insulator272, the insulator280, the insulator282, the insulator283, and the insulator286can be reduced. Note that the deposition method is not limited to a sputtering method, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like can be used as appropriate.

The resistivities of the insulator212and the insulator283are preferably low in some cases. For example, by setting the resistivities of the insulator212and the insulator283to approximately 1×1013Ωcm, the insulator212and the insulator283can sometimes reduce charge up of the conductor205, the conductor242, the conductor260, or the conductor246in treatment using plasma or the like in the manufacturing process of a semiconductor device. The resistivities of the insulator212and the insulator283are preferably higher than or equal to 1×1010Ωcm and lower than or equal to 1×1015Ωcm.

The insulator216, the insulator274, the insulator280, and the insulator286each preferably have a lower dielectric constant than the insulator214. When a material with a low dielectric constant is used for an interlayer film, parasitic capacitance generated between wirings can be reduced. For the insulator216, the insulator274, the insulator280, and the insulator286, silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like is used as appropriate, for example.

The conductor205is placed so as to be overlapped by the oxide230and the conductor260. Here, the conductor205is preferably provided so as to be embedded in an opening formed in the insulator216.

The conductor205includes the conductor205a, the conductor205b, and the conductor205c. The conductor205ais provided in contact with the bottom surface and sidewall of the opening. The conductor205bis provided so as to be embedded in a recessed portion formed in the conductor205a. Here, the top surface of the conductor205bis lower in level than the top surface of the conductor205aand the top surface of the insulator216. The conductor205cis provided in contact with the top surface of the conductor205band a side surface of the conductor205a. Here, the level of the top surface of the conductor205cis substantially the same as the level of the top surface of the conductor205aand the level of the top surface of the insulator216. That is, the conductor205bis surrounded by the conductor205aand the conductor205c.

Here, for the conductor205aand the conductor205c, it is preferable to use a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N2O, NO, NO2, or the like), and a copper atom. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like).

When a conductive material having a function of inhibiting diffusion of hydrogen is used for the conductor205aand the conductor205c, impurities such as hydrogen contained in the conductor205bcan be prevented from diffusing into the oxide230through the insulator224and the like. When a conductive material having a function of inhibiting diffusion of oxygen is used for the conductor205aand the conductor205c, a decrease in the conductivity of the conductor205bbecause of oxidation can be inhibited. As the conductive material having a function of inhibiting diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used. Thus, a single layer or a stacked layer of the above conductive material is used for the conductor205a. For example, titanium nitride is used as the conductor205a.

Moreover, a conductive material containing tungsten, copper, or aluminum as its main component is preferably used for the conductor205b. For example, tungsten is used for the conductor205b.

The conductor205sometimes functions as a second gate electrode. In that case, by changing a potential applied to the conductor205not in conjunction with but independently of a potential applied to the conductor260, the threshold voltage (Vth) of the transistor200can be controlled. In particular, Vth of the transistor200can be higher in the case where a negative potential is applied to the conductor205, and the off-state current can be reduced. Thus, a drain current at the time when a potential applied to the conductor260is 0 V can be lower in the case where a negative potential is applied to the conductor205than in the case where the negative potential is not applied to the conductor205.

The electric resistivity of the conductor205is designed in consideration of the potential applied to the conductor205, and the thickness of the conductor205is determined in accordance with the electric resistivity. The thickness of the insulator216is substantially equal to that of the conductor205. The conductor205and the insulator216are preferably as thin as possible in the allowable range of the design of the conductor205. When the thickness of the insulator216is reduced, the absolute amount of impurities such as hydrogen contained in the insulator216can be reduced, inhibiting the diffusion of the impurities into the oxide230.

As illustrated inFIG.4A, the conductor205is preferably provided so as to be larger than a region of the oxide230that is not overlapped by the conductor242aor the conductor242b. As illustrated inFIG.4C, it is particularly preferable that the conductor205extend to a region outside end portions of the oxide230aand the oxide230bin the channel width direction. That is, the conductor205and the conductor260preferably overlap each other with the insulators therebetween on the outer side of a side surface of the oxide230in the channel width direction. With this structure, the channel formation region of the oxide230can be electrically surrounded by the electric field of the conductor260functioning as a first gate electrode and the electric field of the conductor205functioning as the second gate electrode. In this specification, a transistor structure in which a channel formation region is electrically surrounded by electric fields of a first gate and a second gate is referred to as a surrounded channel (S-channel) structure.

In this specification and the like, a transistor having the S-channel structure refers to a transistor having a structure in which a channel formation region is electrically surrounded by the electric fields of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like is different from a Fin-type structure and a planar structure. With the S-channel structure, resistance to a short-channel effect can be enhanced, that is, a transistor in which a short-channel effect is less likely to occur can be provided.

Furthermore, as illustrated inFIG.4C, the conductor205is extended to function as a wiring as well. However, without limitation to this structure, a structure in which a conductor functioning as a wiring is provided below the conductor205may be employed. In addition, the conductor205does not necessarily need to be provided in each transistor. For example, the conductor205may be shared by a plurality of transistors.

Although the transistor200having a structure in which the conductor205is a stack of the conductor205a, the conductor205b, and the conductor205cis illustrated, the present invention is not limited thereto. For example, the conductor205may be provided so as to have a single-layer structure or a stacked-layer structure of two layers or four or more layers.

The insulator222and the insulator224function as a gate insulator.

It is preferable that the insulator222have a function of inhibiting diffusion of hydrogen (e.g., at least one of a hydrogen atom, a hydrogen molecule, and the like). In addition, it is preferable that the insulator222have a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like). For example, the insulator222preferably has a function of inhibiting diffusion of one or both of hydrogen and oxygen more than the insulator224.

As the insulator222, an insulator containing an oxide of one or both of aluminum and hafnium, which is an insulating material, is preferably used. For the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. In the case where the insulator222is formed using such a material, the insulator222functions as a layer that inhibits release of oxygen from the oxide230to the substrate side and diffusion of impurities such as hydrogen from the periphery of the transistor200into the oxide230. Thus, providing the insulator222can inhibit diffusion of impurities such as hydrogen into the transistor200and inhibit generation of oxygen vacancies in the oxide230. Moreover, the reaction of the conductor205with oxygen contained in the insulator224and the oxide230can be inhibited.

For example, a single layer or stacked layers of an insulator containing what is called a high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3(BST) may be used for the insulator222. As miniaturization and high integration of transistors progress, a problem such as a leakage current may arise because of a thinner gate insulator. When a high-k material is used for an insulator functioning as the gate insulator, a gate potential at the time when the transistor operates can be reduced while the physical thickness is maintained.

Silicon oxide or silicon oxynitride, for example, can be used as appropriate for the insulator224that is in contact with the oxide230.

In a manufacturing process of the transistor200, heat treatment is preferably performed with a surface of the oxide230exposed. For example, the heat treatment is performed at a temperature higher than or equal to 100° C. and lower than or equal to 600° C. preferably higher than or equal to 350° C. and lower than or equal to 550° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This can supply oxygen to the oxide230to reduce oxygen vacancies (VO). The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in a nitrogen gas or inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for released oxygen. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more, and then another heat treatment is successively performed in a nitrogen gas or inert gas atmosphere.

Note that oxygen adding treatment performed on the oxide230can promote a reaction in which oxygen vacancies in the oxide230are repaired with supplied oxygen, i.e., a reaction of “VO+O→null”. Furthermore, hydrogen remaining in the oxide230reacts with supplied oxygen, so that the hydrogen can be removed as H2O (dehydration). This can inhibit recombination of hydrogen remaining in the oxide230with oxygen vacancies and formation of VOH.

Note that the insulator222and the insulator224may each have a stacked-layer structure of two or more layers. In that case, without limitation to a stacked-layer structure formed of the same material, a stacked-layer structure formed of different materials may be employed. The insulator224may be formed into an island shape so as to be overlapped by the oxide230a. In this case, the insulator272is in contact with a side surface of the insulator224and the top surface of the insulator222.

The oxide243aand the oxide243bare provided over the oxide230b. The oxide243aand the oxide243bare provided apart from each other with the conductor260therebetween.

The oxide243(the oxide243aand the oxide243b) preferably has a function of inhibiting passage of oxygen. The oxide243having a function of inhibiting passage of oxygen is preferably placed between the oxide230band the conductor242functioning as the source electrode and the drain electrode, in which case the electric resistance between the oxide230band the conductor242can be reduced. Such a structure can improve the electrical characteristics of the transistor200and the reliability of the transistor200. In the case where the electric resistance between the oxide230band the conductor242can be sufficiently reduced, the oxide243is not necessarily provided.

A metal oxide containing the element M may be used as the oxide243. In particular, aluminum, gallium, yttrium, or tin is preferably used as the element M. The concentration of the element M in the oxide243is preferably higher than that in the oxide230b. Furthermore, gallium oxide may be used for the oxide243. A metal oxide such as an In-M-Zn oxide may be used as the oxide243. Specifically, the atomic ratio of the element M to In in the metal oxide used as the oxide243is preferably greater than the atomic ratio of the element M to In in the metal oxide used as the oxide230b. The thickness of the oxide243is preferably greater than or equal to 0.5 nm and less than or equal to 5 nm, further preferably greater than or equal to 1 nm and less than or equal to 3 nm, still further preferably greater than or equal to 1 nm and less than or equal to 2 nm. The oxide243preferably has crystallinity. In the case where the oxide243has crystallinity, release of oxygen from the oxide230can be favorably inhibited. When the oxide243has a hexagonal crystal structure, for example, release of oxygen from the oxide230can sometimes be inhibited.

It is preferable that the conductor242abe provided in contact with the top surface of the oxide243aand the conductor242bbe provided in contact with the top surface of the oxide243b. Each of the conductor242aand the conductor242bfunctions as a source electrode or a drain electrode of the transistor200.

For the conductor242(the conductor242aand the conductor242b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, a nitride containing titanium and aluminum, or the like is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. As another example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are each a conductive material that is not easily oxidized or a material that maintains the conductivity even after absorbing oxygen.

Note that hydrogen contained in the oxide230bor the like diffuses into the conductor242aor the conductor242bin some cases. In particular, when a nitride containing tantalum is used for the conductor242aand the conductor242b, hydrogen contained in the oxide230bor the like is likely to diffuse into the conductor242aor the conductor242b, and the diffused hydrogen is bonded to nitrogen contained in the conductor242aor the conductor242bin some cases. That is, hydrogen contained in the oxide230bor the like is absorbed by the conductor242aor the conductor242bin some cases.

No curved surface is preferably formed between a side surface of the conductor242and the top surface of the conductor242. When no curved surface is formed in the conductor242, the conductor242can have a large cross-sectional area in the channel width direction. Accordingly, the conductivity of the conductor242is increased, so that the on-state current of the transistor200can be increased.

The insulator271ais provided in contact with the top surface of the conductor242a, and the insulator271bis provided in contact with the top surface of the conductor242b. The top surface of the insulator271ais preferably in contact with the insulator272, and a side surface of the insulator271ais preferably in contact with the insulator250. The top surface of the insulator271bis preferably in contact with the insulator272and a side surface of the insulator271bis preferably in contact with the insulator250. The insulator271preferably functions as at least a barrier insulating film against oxygen. Thus, the insulator271preferably has a function of inhibiting oxygen diffusion. For example, the insulator271preferably has a function of inhibiting diffusion of oxygen more than the insulator280. For example, a nitride containing silicon such as silicon nitride may be used for the insulator271. The insulator271preferably has a function of capturing impurities such as hydrogen. In that case, for the insulator271, a metal oxide having an amorphous structure, for example, an insulator such as aluminum oxide or magnesium oxide, may be used. It is particularly preferable to use aluminum oxide having an amorphous structure or amorphous aluminum oxide for the insulator271because hydrogen can be captured or fixed more effectively in some cases. Accordingly, the transistor200and a semiconductor device which have favorable characteristics and high reliability can be manufactured.

The insulator272is provided so as to cover the insulator224, the oxide230a, the oxide230b, the oxide243, the conductor242, and the insulator271. The insulator272preferably has a function of capturing and fixing hydrogen. In that case, the insulator272preferably includes a metal oxide having an amorphous structure, for example, an insulator such as aluminum oxide or magnesium oxide.

When the above insulator271and the insulator272are provided, the conductor242can be surrounded by the insulators having a barrier property against oxygen. That is, oxygen contained in the insulator224and the insulator280can be prevented from diffusing into the conductor242. As a result, oxidation of the conductor242directly by oxygen contained in the insulator224and the insulator280can be inhibited, so that an increase in resistivity and a reduction in on-state current can be inhibited.

The insulator250functions as a gate insulator. The insulator250is preferably placed in contact with the top surface of the oxide230b. For the insulator250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, or the like can be used. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable.

As in the insulator224, the concentration of impurities such as water and hydrogen in the insulator250is preferably reduced. The thickness of the insulator250is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

In the case where the insulator250has a stacked-layer structure of two layers as illustrated inFIG.4BandFIG.4C, it is preferable that the insulator250athat is a lower layer be formed using an insulator through which oxygen is likely to pass and the insulator250bthat is an upper layer be formed using an insulator having a function of inhibiting oxygen diffusion. With such a structure, oxygen contained in the insulator250acan be inhibited from diffusing into the conductor260. That is, a reduction in the amount of oxygen supplied to the oxide230can be inhibited. In addition, oxidation of the conductor260by oxygen contained in the insulator250acan be inhibited. For example, it is preferable that the insulator250abe provided using any of the above-described materials that can be used for the insulator250and the insulator250bbe provided using an insulator containing an oxide of one or both of aluminum and hafnium. As the insulator, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. The thickness of the insulator250bis greater than or equal to 0.5 nm and less than or equal to 3.0 nm, preferably greater than or equal to 1.0 nm and less than or equal to 1.5 nm.

In the case where silicon oxide, silicon oxynitride, or the like is used for the lower layer of the insulator250, an insulating material that is a high-k material having a high relative dielectric constant may be used for the upper layer of the insulator250. The gate insulator having a stacked-layer structure of the insulator250aand the insulator250bcan be thermally stable and can have a high relative dielectric constant. Thus, agate potential that is applied during operation of the transistor can be reduced while the physical thickness of the gate insulator is maintained. In addition, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced.

A metal oxide may be provided between the insulator250and the conductor260. The metal oxide preferably inhibits diffusion of oxygen from the insulator250into the conductor260. Providing the metal oxide that inhibits diffusion of oxygen inhibits diffusion of oxygen from the insulator250into the conductor260. That is, a reduction in the amount of oxygen supplied to the oxide230can be inhibited. Moreover, oxidation of the conductor260by oxygen in the insulator250can be inhibited.

Note that the metal oxide may function as part of the first gate electrode. For example, a metal oxide that can be used as the oxide230can be used as the metal oxide. In that case, when the conductor260ais formed by a sputtering method, the metal oxide can have a reduced electric resistance value to be a conductor. Such a conductor can be referred to as an OC (Oxide Conductor) electrode.

With the metal oxide, the on-state current of the transistor200can be increased without a reduction in the influence of the electric field from the conductor260. Since a distance between the conductor260and the oxide230is kept by the physical thicknesses of the insulator250and the metal oxide, a leakage current between the conductor260and the oxide230can be inhibited. Moreover, when the stacked-layer structure of the insulator250and the metal oxide is provided, the physical distance between the conductor260and the oxide230and the intensity of electric field applied to the oxide230from the conductor260can be easily adjusted as appropriate.

The conductor260functions as the first gate electrode of the transistor200. The conductor260preferably includes the conductor260aand the conductor260bplaced over the conductor260a. For example, the conductor260ais preferably placed so as to cover the bottom surface and the side surface of the conductor260b. Moreover, as illustrated inFIG.4BandFIG.4C, the top surface of the conductor260is substantially level with the top surface of the insulator250. Although the conductor260has a two-layer structure of the conductor260aand the conductor260binFIG.4BandFIG.4C, the conductor260may have a single-layer structure or a stacked-layer structure of three or more layers.

For the conductor260a, a conductive material having a function of inhibiting diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule, and a copper atom is preferably used. Alternatively, it is preferable to use a conductive material having a function of inhibiting diffusion of oxygen (e.g., at least one of an oxygen atom, an oxygen molecule, and the like).

In addition, when the conductor260ahas a function of inhibiting diffusion of oxygen, a decrease in the conductivity of the conductor260bbecause of oxidation due to oxygen contained in the insulator250can be inhibited. As the conductive material having a function of inhibiting diffusion of oxygen, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide is preferably used.

The conductor260also functions as a wiring; thus, a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as its main component can be used for the conductor260b. The conductor260bmay have a stacked-layer structure; for example, a stacked-layer structure of the conductive material and titanium or titanium nitride may be employed.

In the transistor200, the conductor260is formed in a self-aligned manner to fill the opening formed in the insulator280and the like. The formation of the conductor260in this manner allows the conductor260to be placed certainly in a region between the conductor242aand the conductor242bwithout alignment.

As illustrated inFIG.4C, in the channel width direction of the transistor200, with reference to the bottom surface of the insulator222, the level of the bottom surface of the conductor260in a region where the conductor260and the oxide230bdo not overlap is preferably lower than the level of the bottom surface of the oxide230b. When the conductor260functioning as the gate electrode covers the side surface and the top surface of the channel formation region of the oxide230bwith the insulator250and the like therebetween, the electric field of the conductor26) is likely to act on the entire channel formation region of the oxide230b. Thus, the on-state current of the transistor200can be increased and the frequency characteristics of the transistor200can be improved. When the bottom surface of the insulator222is a reference, the difference between the level of the bottom surface of the conductor260in a region where the conductor260do not overlap the oxide230aand the oxide230band the level of the bottom surface of the oxide230bis greater than or equal to 0 nm and less than or equal to 100 nm, preferably greater than or equal to 3 nm and less than or equal to 50 nm, further preferably greater than or equal to 5 nm and less than or equal to 20 nm.

The opening region400is formed by forming an opening in the insulator282in the manufacturing process of a semiconductor device. At this time, a depressed portion is formed in the insulator280in some cases. By performing heat treatment after the formation of the opening region400, oxygen contained in the insulator280and hydrogen bonded to the oxygen can be released to the outside through the opening region400. The hydrogen bonded to oxygen is released as water. Thus, unnecessary oxygen and hydrogen contained in the insulator280can be reduced. The insulator283over the insulator282is provided in contact with the insulator280in the opening region400, and the insulator274is embedded in the opening region400over the insulator283. The depth of the depressed portion in the insulator280is greater than or equal to ¼ and less than or equal to ½ of the largest thickness of the insulator280in the semiconductor device.

The insulator280is provided over the insulator272, and the opening is formed in a region where the insulator250and the conductor260are to be provided. In addition, the top surface of the insulator280may be planarized.

The insulator280functioning as an interlayer film preferably has a low dielectric constant. When a material with a low dielectric constant is used for an interlayer film, parasitic capacitance generated between wirings can be reduced. The insulator280is preferably provided using a material similar to that for the insulator216, for example. In particular, silicon oxide and silicon oxynitride, which have thermal stability, are preferable. Materials such as silicon oxide, silicon oxynitride, and porous silicon oxide are particularly preferable because a region containing oxygen released by heating can be easily formed.

As for the insulator280, the concentration of impurities such as water and hydrogen in the insulator280is preferably reduced. An oxide containing silicon such as silicon oxide, silicon oxynitride, or the like is used as appropriate for the insulator280, for example.

The insulator282preferably functions as a barrier insulating film that inhibits diffusion of impurities such as water and hydrogen into the insulator280from above and preferably have a function of capturing impurities such as hydrogen. The insulator282preferably functions as a barrier insulating film that inhibits passage of oxygen. For the insulator282, a metal oxide having an amorphous structure, for example, an insulator such as aluminum oxide can be used. The insulator282, which has a function of capturing impurities such as hydrogen, is provided in contact with the insulator280in a region sandwiched between the insulator212and the insulator283, whereby impurities such as hydrogen contained in the insulator280and the like can be captured and the amount of hydrogen in the region can be kept constant. It is particularly preferable to use aluminum oxide having an amorphous structure or amorphous aluminum oxide for the insulator282because hydrogen can be captured or fixed more effectively in some cases. Accordingly, the transistor200and a semiconductor device which have favorable characteristics and high reliability can be manufactured.

The insulator283functions as a barrier insulating film that inhibits diffusion of impurities such as water and hydrogen into the insulator280from above. The insulator283is placed over the insulator282. For the insulator283, a nitride containing silicon such as silicon nitride or silicon nitride oxide is preferably used. For example, silicon nitride deposited by a sputtering method is used for the insulator283. When the insulator283is formed by a sputtering method, a high-density silicon nitride film where a void or the like is less likely to be formed can be formed. To obtain the insulator283, silicon nitride deposited by an ALD method may be stacked over silicon nitride deposited by a sputtering method. Such a structure is preferable because even when a defect, for example, a void is caused in silicon nitride deposited by a sputtering method, the void can be filled with silicon nitride deposited by an ALD method, with which favorable coverage is achieved, to increase sealing capability.

The insulator286is provided over the insulator283and the insulator274.

For the conductor240aand the conductor240b, a conductive material containing tungsten, copper, or aluminum as its main component is preferably used. The conductor240aand the conductor240bmay each have a stacked-layer structure.

In the case where the conductor240has a stacked-layer structure, a conductive material having a function of inhibiting passage of impurities such as water and hydrogen is preferably used for a conductor in contact with the insulator286, the insulator283, the insulator282, the insulator280, the insulator272, and the insulator271. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like is preferably used. The conductive material having a function of inhibiting passage of impurities such as water and hydrogen may be used as a single layer or stacked layers. Moreover, entry of impurities such as water and hydrogen contained in a layer above the insulator283into the oxide230through the conductor240aand the conductor240bcan be inhibited.

For the insulator241aand the insulator241b, for example, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used. Since the insulator241aand the insulator241bare provided in contact with the insulator286, the insulator283, the insulator282, the insulator280, the insulator272, and the insulator271, entry of impurities such as water and hydrogen contained in the insulator280or the like into the oxide230through the conductor240aand the conductor240bcan be inhibited. In particular, silicon nitride is suitable because of its high blocking property against hydrogen. Furthermore, oxygen contained in the insulator280can be prevented from being absorbed by the conductor240aand the conductor240b.

The conductor246(the conductor246aand the conductor246b) functioning as a wiring may be placed in contact with the top surface of the conductor240aand the top surface of the conductor240b. The conductor246is preferably formed using a conductive material containing tungsten, copper, or aluminum as its main component. Furthermore, the conductor may have a stacked-layer structure and may be a stack of titanium or titanium nitride and the conductive material, for example. Note that the conductor may be formed so as to be embedded in an opening provided in an insulator.

<Constituent Materials of Semiconductor Device>

Constituent materials that can be used for the semiconductor device are described below.

As a substrate where the transistor200is formed, an insulator substrate, a semiconductor substrate, or a conductor substrate is used, for example. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate using silicon or germanium as a material and a compound semiconductor substrate containing silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Another example is a semiconductor substrate in which an insulator region is included in the semiconductor substrate, e.g., an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Other examples include a substrate including a metal nitride and a substrate including a metal oxide. Other examples include an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator. Alternatively, these substrates provided with elements may be used. Examples of the element provided for the substrate include a capacitor element, a resistor element, a switching element, a light-emitting element, and a storage element.

Examples of the insulator include an insulating oxide, an insulating nitride, an insulating oxynitride, an insulating nitride oxide, an insulating metal oxide, an insulating metal oxynitride, and an insulating metal nitride oxide.

As miniaturization and high integration of transistors progress, for example, a problem such as a leakage current arises because of a thinner gate insulator, in some cases. When a high-k material is used for the insulator functioning as a gate insulator, the voltage during operation of the transistor can be lowered while the physical thickness of the gate insulator is maintained. In contrast, when a material with a low relative dielectric constant is used for the insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Thus, a material is preferably selected depending on the function of an insulator.

Examples of the insulator with a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

Examples of the insulator with a low relative dielectric constant include silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, and a resin.

When a transistor using a metal oxide is surrounded by an insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, the transistor can have stable electrical characteristics. As the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, a single layer or stacked layers of an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum are used. Specifically, as the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; or a metal nitride such as aluminum nitride, silicon nitride oxide, or silicon nitride can be used.

The insulator functioning as the gate insulator is preferably an insulator including a region containing oxygen released by heating. For example, when a structure is employed in which silicon oxide or silicon oxynitride including a region containing oxygen released by heating is in contact with the oxide230, oxygen vacancies included in the oxide230can be compensated for.

A stack of a plurality of conductive layers formed of the above materials may be used. For example, a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen may be employed. Alternatively, a stacked-layer structure combining a material containing the above metal element and a conductive material containing nitrogen may be employed. Alternatively, a stacked-layer structure combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be employed.

In the case where an oxide is used for the channel formation region of the transistor, the conductor functioning as the gate electrode preferably employs a stacked-layer structure combining a material containing the above metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably provided on the channel formation region side. When the conductive material containing oxygen is provided on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

For the conductor functioning as the gate electrode, it is particularly preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide where the channel is formed. Alternatively, a conductive material containing the above metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon is added may be used. Indium gallium zinc oxide containing nitrogen may be used. With the use of such a material, hydrogen contained in the metal oxide where the channel is formed can be captured in some cases. Alternatively, hydrogen entering from an external insulator or the like can be captured in some cases.

As the oxide230, a metal oxide functioning as a semiconductor (an oxide semiconductor) is preferably used. A metal oxide that can be used as the oxide230of the present invention is described below.

Note that in this specification and the like, a metal oxide containing nitrogen is also collectively referred to as a metal oxide in some cases. A metal oxide containing nitrogen may be referred to as a metal oxynitride.

<Classification of Crystal Structures>

First, the classification of crystal structures of an oxide semiconductor is described with reference toFIG.6A.FIG.6Ais a diagram showing the classification of crystal structures of an oxide semiconductor, typically IGZO (a metal oxide containing In, Ga. and Zn).

As shown inFIG.6A, an oxide semiconductor is roughly classified into “Amorphous”, “Crystalline”, and “Crystal”. The term “Amorphous” includes completely amorphous. The term “Crystalline” includes CAAC (c-axis-aligned crystalline), nc (nanocrystalline), and CAC (cloud-aligned composite). Note that the term “Crystalline” excludes single crystal, poly crystal, and completely amorphous (excluding single crystal and poly crystal). The term “Crystal” includes single crystal and poly crystal.

Note that the structures in the thick frame inFIG.6Aare in an intermediate state between “Amorphous” and “Crystal”, and belong to a new boundary region (New crystalline phase). That is, these structures are completely different from “Amorphous”, which is energetically unstable, and “Crystal”.

A crystal structure of a film or a substrate can be analyzed with an X-ray diffraction (XRD) spectrum. Here,FIG.6Bshows an XRD spectrum, which is obtained by GIXD (Grazing-Incidence XRD) measurement, of a CAAC-IGZO film classified into “Crystalline”. Note that a GIXD method is also referred to as a thin film method or a Seemann-Bohlin method. The XRD spectrum that is shown inFIG.6Band obtained by GIXD measurement is hereinafter simply referred to as an XRD spectrum. The CAAC-IGZO film shown inFIG.6Bhas a composition in the neighborhood of In:Ga:Zn=4:2:3 [atomic ratio]. The CAAC-IGZO film shown inFIG.6Bhas a thickness of 500 nm.

As shown inFIG.6B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis alignment is detected at 2θ of around 31° in the XRD spectrum of the CAAC-IGZO film. As shown inFIG.6B, the peak at 2θ of around 31° is asymmetric with respect to the axis of the angle at which the peak intensity (Intensity) is detected.

A crystal structure of a film or a substrate can also be evaluated with a diffraction pattern obtained by a nanobeam electron diffraction (NBED) method (such a pattern is also referred to as a nanobeam electron diffraction pattern).FIG.6Cshows a diffraction pattern of the CAAC-IGZO film.FIG.6Cshows a diffraction pattern obtained with NBED in which an electron beam is incident in the direction parallel to the substrate. The CAAC-IGZO film inFIG.6Chas a composition in the neighborhood of In:Ga:Zn=4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed with a probe diameter of 1 nm.

As shown inFIG.6C, a plurality of spots indicating c-axis alignment are observed in the diffraction pattern of the CAAC-IGZO film.

Here, the above-described CAAC-OS, nc-OS, and a-like OS will be described in detail.

Note that each of the plurality of crystal regions is formed of one or more fine crystals (crystals each of which has a maximum diameter of less than 10 nm). In the case where the crystal region is formed of one fine crystal, the maximum diameter of the crystal region is less than 10 nm. In the case where the crystal region is formed of a large number of fine crystals, the size of the crystal region may be approximately several tens of nanometers.

In the case of an In-M-Zn oxide (the element M is one kind or two or more kinds selected from aluminum, gallium, yttrium, tin, titanium, and the like), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter, an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter, an (M,Zn) layer) are stacked. Indium and the element M can be replaced with each other. Therefore, indium may be contained in the (M,Zn)layer. In addition, the element M may be contained in the In layer. Note that Zn may be contained in the In layer. Such a layered structure is observed as a lattice image in a high-resolution TEM image, for example.

The CAAC-OS is an oxide semiconductor with high crystallinity in which no clear grain boundary is observed. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is unlikely to occur. Moreover, since the crystallinity of an oxide semiconductor might be decreased by entry of impurities, formation of defects, or the like, the CAAC-OS can be regarded as an oxide semiconductor that has small amounts of impurities and defects (e.g., oxygen vacancies). Thus, an oxide semiconductor including the CAAC-OS is physically stable. Therefore, the oxide semiconductor including the CAAC-OS is resistant to heat and has high reliability. In addition, the CAAC-OS is stable with respect to high temperature in the manufacturing process (what is called thermal budget). Accordingly, the use of the CAAC-OS for the OS transistor can extend the degree of freedom of the manufacturing process.

Next, the above-described CAC-OS will be described in detail. Note that the CAC-OS relates to the material composition.

Note that the atomic ratios of In, Ga, and Zn to the metal elements contained in the CAC-OS in an In—Ga—Zn oxide are denoted with [In], [Ga], and [Zn], respectively. For example, the first region in the CAC-OS in the In—Ga—Zn oxide has [In] higher than that in the composition of the CAC-OS film. Moreover, the second region has [Ga] higher than that in the composition of the CAC-OS film. For example, the first region has higher [In] and lower [Ga] than the second region. Moreover, the second region has higher [Ga] and lower [In] than the first region.

Specifically, the first region includes indium oxide, indium zinc oxide, or the like as its main component. The second region includes gallium oxide, gallium zinc oxide, or the like as its main component. That is, the first region can be referred to as a region containing In as its main component. The second region can be referred to as a region containing Ga as its main component.

For example, energy dispersive X-ray spectroscopy (EDX) is used to obtain EDX mapping, and according to the EDX mapping, the CAC-OS in the In—Ga—Zn oxide has a structure in which the region containing In as its main component (the first region) and the region containing Ga as its main component (the second region) are unevenly distributed and mixed.

In the case where the CAC-OS is used for a transistor, a switching function (on/off switching function) can be given to the CAC-OS owing to the complementary action of the conductivity derived from the first region and the insulating property derived from the second region. The CAC-OS has a conducting function in part of the material and has an insulating function in another part of the material; as a whole, the CAC-OS has a function of a semiconductor. Separation of the conducting function and the insulating function can maximize each function. Accordingly, when the CAC-OS is used for a transistor, high on-state current (Ion), high field-effect mobility (μ), and excellent switching operation can be achieved.

An oxide semiconductor has various structures with different properties. Two or more kinds among the amorphous oxide semiconductor, the polycrystalline oxide semiconductor, the a-like OS, the CAC-OS, the nc-OS, and the CAAC-OS may be included in an oxide semiconductor of one embodiment of the present invention.

Next, the case where the above oxide semiconductor is used for a transistor will be described.

When the above oxide semiconductor is used for a transistor, a transistor with high field-effect mobility can be achieved. In addition, a transistor having high reliability can be fabricated.

A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states and thus has a low density of trap states in some cases.

Accordingly, in order to obtain stable electrical characteristics of a transistor, reducing the impurity concentration in an oxide semiconductor is effective. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable that the impurity concentration in an adjacent film be also reduced. Examples of impurities include hydrogen, nitrogen, an alkali metal, an alkaline earth metal, iron, nickel, and silicon.

Here, the influence of each impurity in the oxide semiconductor will be described.

When silicon or carbon, which is one of Group 14 elements, is contained in the oxide semiconductor, defect states are formed in the oxide semiconductor. Thus, the concentration of silicon or carbon in the channel formation region of the oxide semiconductor and the concentration of silicon or carbon at the interface between, for example, an insulator and the channel formation region of the oxide semiconductor and in the vicinity of the interface (the concentration obtained by secondary ion mass spectrometry (SIMS)) are each set lower than or equal to 2×1018atoms/cm3, preferably lower than or equal to 2×1017atoms/cm3.

Furthermore, when the oxide semiconductor contains nitrogen, the oxide semiconductor easily becomes n-type because of generation of electrons serving as carriers and an increase in carrier concentration. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor is likely to have normally-on characteristics. When nitrogen is contained in the oxide semiconductor, a trap state is sometimes formed. This might make the electrical characteristics of the transistor unstable. Therefore, the concentration of nitrogen in the channel formation region of the oxide semiconductor, which is obtained using SIMS, is set lower than 5×1019atoms/cm3, preferably lower than or equal to 5×1019atoms/cm3, further preferably lower than or equal to 1×1018atoms/cm3, still further preferably lower than or equal to 5×1017atoms/cm3

A semiconductor material that can be used for the oxide230is not limited to the above metal oxides. A semiconductor material that has a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the oxide230. For example, a single element semiconductor such as silicon, a compound semiconductor such as gallium arsenide, or a layered material functioning as a semiconductor (also referred to as an atomic layer material or a two-dimensional material) is preferably used as a semiconductor material. In particular, a layered material functioning as a semiconductor is preferably used as a semiconductor material.

Here, in this specification and the like, the layered material generally refers to a group of materials having a layered crystal structure. In the layered crystal structure, layers formed by covalent bonding or ionic bonding are stacked with bonding such as the Van der Waals force, which is weaker than covalent bonding or ionic bonding. The layered material has high electrical conductivity in a monolayer, that is, high two-dimensional electrical conductivity. When a material that functions as a semiconductor and has high two-dimensional electrical conductivity is used for a channel formation region, a transistor can having a high on-state current can be provided.

Examples of the layered material include graphene, silicene, and chalcogenide. Chalcogenide is a compound containing chalcogen. Chalcogen is a general term of elements belonging to Group 16, which includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Examples of chalcogenide include transition metal chalcogenide and chalcogenide of Group 13 elements.

<Manufacturing Method for Semiconductor Device>

Next, a method for manufacturing the semiconductor device that is one embodiment of the present invention and is illustrated inFIG.4AtoFIG.4Dis described with reference toFIG.7AtoFIG.23D.

InFIG.7AtoFIG.23D, A in each drawing is a top view. Moreover, B of each drawing is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A1-A2in A of each drawing, i.e., a cross-sectional view of the transistor200in the channel length direction. Furthermore, C of each drawing is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A3-A4in A of each drawing, i.e., a cross-sectional view of the transistor200in the channel width direction. Furthermore, D of each drawing is a cross-sectional view of a portion indicated by dashed-dotted line A5-A6in A of each drawing, i.e., a cross-sectional view of the opening region400. For clarity of the drawing, some components are not shown in the top view of A of each drawing.

In the following, an insulating material for forming an insulator, a conductive material for forming a conductor, and a oxide material for forming an oxide can be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.

Examples of the sputtering method include an RF sputtering method in which a high-frequency power source is used as a sputtering power source, a DC sputtering method in which a DC power source is used, and a pulsed DC sputtering method in which a voltage is applied to an electrode while being changed in a pulsed manner. An RF sputtering method is mainly used in the case where an insulating film is formed, and a DC sputtering method is mainly used in the case where a metal conductive film is formed. The pulsed DC sputtering method is mainly used in the case where a compound such as an oxide, a nitride, or a carbide is formed by a reactive sputtering method.

Note that the CVD method can be classified into a plasma CVD (PECVD: plasma Enhanced CVD) method using plasma, a thermal CVD (TCVD) method using heat, a photo CVD method using light, and the like. Moreover, the CVD method can be classified into a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method depending on a source gas to be used.

A high-quality film can be obtained at a relatively low temperature by a plasma CVD method. Furthermore, a thermal CVD method is a deposition method that does not use plasma and thus enables less plasma damage to an object to be processed. For example, a wiring, an electrode, an element (a transistor, a capacitor, or the like), or the like included in a semiconductor device might be charged up by receiving electric charge from plasma. In that case, accumulated electric charge might break the wiring, the electrode, the element, or the like included in the semiconductor device. In contrast, such plasma damage does not occur in the case of a thermal CVD method, which does not use plasma, and thus the yield of the semiconductor device can be increased. In addition, a thermal CVD method does not cause plasma damage during deposition, so that a film with few defects can be obtained.

As an ALD method, a thermal ALD method, in which a precursor and a reactant react with each other only by a thermal energy, a PEALD (Plasma Enhanced ALD) method, in which a reactant excited by plasma is used, and the like can be used.

An ALD method, which enables one atomic layer to be deposited at a time using self-regulating characteristics of atoms, has advantages such as deposition of an extremely thin film, deposition on a component with a high aspect ratio, deposition of a film with a small number of defects such as pinholes, deposition with excellent coverage, and low-temperature deposition. The use of plasma in a PEALD (Plasma Enhanced ALD) method is sometimes preferable because deposition at a lower temperature is possible. Note that a precursor used in an ALD method sometimes contains impurities such as carbon. Thus, in some cases, a film provided by an ALD method contains impurities such as carbon in a larger amount than a film provided by another deposition method. Note that impurities can be quantified by X-ray photoelectron spectroscopy (XPS).

Unlike a deposition method in which particles ejected from a target or the like are deposited, a CVD method and an ALD method are deposition methods in which a film is formed by reaction at a surface of an object to be processed. Thus, a CVD method and an ALD method are deposition methods that enable favorable step coverage almost regardless of the shape of an object to be processed. In particular, an ALD method has excellent step coverage and excellent thickness uniformity and thus is suitable for covering a surface of an opening portion with a high aspect ratio, for example. On the other hand, an ALD method has a relatively low deposition rate, and thus is preferably used in combination with another deposition method with a high deposition rate, such as a CVD method, in some cases.

A CVD method and an ALD method enable control of the composition of a film to be obtained with the flow rate ratio of the source gases. For example, by a CVD method and an ALD method, a film with a certain composition can be formed depending on the flow rate ratio of the source gases. Moreover, for example, by a CVD method and an ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gases during the deposition. In the case where the film is formed while the flow rate ratio of the source gases is changed, as compared with the case where the film is formed using a plurality of deposition chambers, the time taken for the deposition can be shortened because the time taken for transfer and pressure adjustment is not required. Thus, the productivity of the semiconductor device can be increased in some cases.

First, a substrate (not illustrated) is prepared, and the insulator212is formed over the substrate (seeFIG.7AtoFIG.7D). The insulator212is preferably formed by a sputtering method. By using a sputtering method that does not need to use hydrogen as a deposition gas, the hydrogen concentration in the insulator212can be reduced. Without limitation to a sputtering method, the insulator212may be formed by a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.

In this embodiment, for the insulator212, silicon nitride is deposited by a pulsed DC sputtering method using a silicon target in an atmosphere containing a nitrogen gas. The use of a pulsed DC sputtering method can inhibit generation of particles due to arcing on the target surface, achieving more uniform film thickness. In addition, by using the pulsed voltage, rising and falling in discharge can be made steep as compared with the case where a high-frequency voltage is used. As a result, power can be supplied to an electrode more efficiently to improve the sputtering rate and film quality.

The use of an insulator through which impurities such as water and hydrogen are less likely to pass, such as silicon nitride, can inhibit diffusion of impurities such as water and hydrogen contained in a layer below the insulator212. When an insulator through which copper is less likely to pass, such as silicon nitride, is used for the insulator212, even in the case where a metal that is likely to diffuse, such as copper, is used for a conductor in a layer (not illustrated) below the insulator212, upward diffusion of the metal through the insulator212can be inhibited.

Next, the insulator214is formed over the insulator212(seeFIG.7AtoFIG.7D). The insulator214is preferably formed by a sputtering method. By using a sputtering method that does not need to use hydrogen as a deposition gas, the hydrogen concentration in the insulator214can be reduced. Without limitation to a sputtering method, the insulator214may be formed by a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.

In this embodiment, for the insulator214, aluminum oxide is deposited by a pulsed DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas. The use of a pulsed DC sputtering method can achieve more uniform film thickness and improve the sputtering rate and film quality. Here, RF (Radio Frequency) power may be applied to the substrate. The amount of oxygen implanted into a layer below the insulator214can be controlled by the amount of RF power applied to the substrate. The RF power is higher than or equal to 0 W/cm2and lower than or equal to 1.86 W/cm2. In other words, the implantation amount of oxygen can be changed to be appropriate for the characteristics of the transistor, with the RF power used at the time of forming the insulator214. Accordingly, an appropriate amount of oxygen for improving the reliability of the transistor can be implanted. The RF frequency is preferably 10 MHz or higher. The typical frequency is 13.56 MHz. The higher the RF frequency is, the less damage the substrate receives.

A metal oxide having an amorphous structure and an excellent function of capturing or fixing hydrogen, such as aluminum oxide, is preferably used for the insulator214. In this case, the insulator214captures or fixes hydrogen contained in the insulator216and the like and prevents the hydrogen from diffusing into the oxide230. It is particularly preferable to use aluminum oxide having an amorphous structure or amorphous aluminum oxide for the insulator214because hydrogen can be captured or fixed more effectively in some cases. Accordingly, the transistor200and a semiconductor device which have favorable characteristics and high reliability can be manufactured.

Next, the insulator216is formed over the insulator214(seeFIG.7AtoFIG.7D). The insulator216is preferably formed by a sputtering method. By using a sputtering method that does not need to use hydrogen as a deposition gas, the hydrogen concentration in the insulator216can be reduced. Without limitation to a sputtering method, the insulator216may be formed by a CVD method, an MBE method, a PLD method, an ALD method, or the like as appropriate.

In this embodiment, for the insulator216, silicon oxide is deposited by a pulsed DC sputtering method using a silicon target in an atmosphere containing an oxygen gas. The use of a pulsed DC sputtering method can achieve more uniform film thickness and improve the sputtering rate and film quality.

The insulator212, the insulator214, and the insulator216are preferably successively formed without exposure to the air. For example, a multi-chamber deposition apparatus is used. As a result, the amounts of hydrogen in the formed insulator212, insulator214, and insulator216can be reduced, and furthermore, entry of hydrogen into the films in intervals between deposition steps can be inhibited.

Then, an opening reaching the insulator214is formed in the insulator216(seeFIG.7AtoFIG.7D). Examples of the opening include a groove and a slit. A region where an opening is formed is referred to as an opening portion in some cases. Wet etching can be used for the formation of the opening; however, dry etching is preferably used for microfabrication. As the insulator214, it is preferable to select an insulator that functions as an etching stopper film used in forming the groove by etching the insulator216. For example, in the case where silicon oxide or silicon oxynitride is used for the insulator216in which the groove is to be formed, silicon nitride, aluminum oxide, or hafnium oxide is preferably used for the insulator214.

As a dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus including parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus including the parallel plate electrodes may have a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, a structure may be employed in which different high-frequency voltages are applied to one of the parallel plate electrodes. Alternatively, a structure may be employed in which high-frequency voltages with the same frequency are applied to the parallel plate electrodes. Alternatively, a structure may be employed in which high-frequency voltages with different frequencies are applied to the parallel plate electrodes. Alternatively, a dry etching apparatus including a high-density plasma source can be used. As the dry etching apparatus including a high-density plasma source, an inductively coupled plasma (ICP) etching apparatus or the like can be used, for example.

After formation of the opening, a conductive film205A is formed (seeFIG.7AtoFIG.7D). The conductive film205A desirably includes a conductor having a function of inhibiting passage of oxygen. For example, tantalum nitride, tungsten nitride, or titanium nitride can be used. Alternatively, a stacked-layer film of the conductor having a function of inhibiting passage of oxygen and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film205A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

In this embodiment, titanium nitride is deposited for the conductive film205A. When such a metal nitride is used for a layer under the conductor205b, oxidation of the conductor205bby the insulator216or the like can be inhibited. Furthermore, even when a metal that is likely to diffuse, such as copper, is used for the conductor205b, the metal can be prevented from diffusing to the outside through the conductor205a.

Next, a conductive film205B is formed (seeFIG.7AtoFIG.7D). Tantalum, tungsten, titanium, molybdenum, aluminum, copper, a molybdenum-tungsten alloy, or the like can be used for the conductive film205B. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, tungsten is deposited for the conductive film205B.

Next, by performing CMP treatment, the conductive film205A and the conductive film205B are partly removed and the insulator216is exposed (seeFIG.8AtoFIG.8D). As a result, the conductor205aand the conductor205bremain only in the opening portion. Note that the insulator216is partly removed by the CMP treatment in some cases.

Next, an upper portion of the conductor205bis removed by etching (seeFIG.9AtoFIG.9D). This makes the top surface of the conductor205blower in level than the top surface of the conductor205aand the top surface of the insulator216. Dry etching or wet etching can be used for the etching of the conductor205b, and dry etching is preferably used for microfabrication.

Next, a conductive film205C is formed over the insulator216, the conductor205a, and the conductor205b(seeFIG.10AtoFIG.10D). Like the conductive film205A, the conductive film205C desirably includes a conductor having a function of inhibiting passage of oxygen.

In this embodiment, titanium nitride is deposited for the conductive film205C. When such a metal nitride is used for a layer over the conductor205b, oxidation of the conductor205bby the insulator222or the like can be inhibited. Furthermore, even when a metal that is likely to diffuse, such as copper, is used for the conductor205b, the metal can be prevented from diffusing to the outside through the conductor205c.

Next, by performing CMP treatment, the conductive film205C is partly removed and the insulator216is exposed (seeFIG.11AtoFIG.11D). As a result, the conductor205a, the conductor205b, and the conductor205cremain only in the opening portion. In this way, the conductor205with a flat top surface can be formed. Furthermore, the conductor205bis surrounded by the conductor205aand the conductor205c. Thus, impurities such as hydrogen can be prevented from diffusing from the conductor205bto the outside of the conductor205aand the conductor205c, and the conductor205bcan be prevented from being oxidized by oxygen entering from the outside of the conductor205aand the conductor205c. Note that the insulator216is partly removed by the CMP treatment in some cases.

Next, the insulator222is formed over the insulator216and the conductor205(seeFIG.12AtoFIG.12D). An insulator including an oxide of one or both of aluminum and hafnium is preferably formed as the insulator222. Note that as the insulator including an oxide of one or both of aluminum and hafnium, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like is preferably used. The insulator including an oxide of one or both of aluminum and hafnium has a barrier property against oxygen, hydrogen, and water. When the insulator222has a barrier property against hydrogen and water, hydrogen and water contained in structure bodies provided around the transistor200are inhibited from diffusing into the transistor200through the insulator222, and generation of oxygen vacancies in the oxide230can be inhibited.

The insulator222can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, for the insulator222, hafnium oxide is deposited by an ALD method.

Sequentially, heat treatment is preferably performed. The heat treatment is performed at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 300° C. and lower than or equal to 500° C. further preferably higher than or equal to 320° C. and lower than or equal to 450° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, in the case where the heat treatment is performed in a mixed atmosphere of a nitrogen gas and an oxygen gas, the proportion of the oxygen gas may be approximately 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in a nitrogen gas or inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for released oxygen.

The gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment is 1 ppb or less, preferably 0.1 ppb or less, further preferably 0.05 ppb or less. The heat treatment using a highly purified gas can prevent entry of moisture or the like into the insulator222and the like as much as possible.

In this embodiment, as the heat treatment, treatment at 400° C. for one hour is performed with a flow rate ratio of a nitrogen gas and an oxygen gas of 4 slm:1 slm after the formation of the insulator222. By the heat treatment, impurities such as water and hydrogen contained in the insulator222can be removed, for example. In the case where an oxide containing hafnium is used for the insulator222, the insulator222is partly crystallized by the heat treatment in some cases. The heat treatment can also be performed after the formation of the insulator224, for example.

Next, the insulator224is formed over the insulator222(seeFIG.12AtoFIG.12D). The insulator224can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, for the insulator224, silicon oxide is deposited by a sputtering method. By using a sputtering method that does not need to use hydrogen as a deposition gas, the hydrogen concentration in the insulator224can be reduced. The hydrogen concentration in the insulator224is preferably reduced because the insulator224is in contact with the oxide230ain a later step.

Next, an oxide film230A and an oxide film230B are formed in this order over the insulator224(seeFIG.12AtoFIG.12D). Note that it is preferable to form the oxide film230A and the oxide film230B successively without exposure to the air. By the formation without exposure to the air, impurities or moisture from the atmospheric environment can be prevented from being attached onto the oxide film230A and the oxide film230B, so that the vicinity of an interface between the oxide film230A and the oxide film230B can be kept clean.

The oxide film230A and the oxide film230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

For example, in the case where the oxide film230A and the oxide film230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. Increasing the proportion of oxygen contained in the sputtering gas can increase the amount of excess oxygen in the formed oxide films. In the case where the oxide films are formed by a sputtering method, the above In-M-Zn oxide target or the like can be used.

In particular, when the oxide film230A is formed, part of oxygen contained in the sputtering gas is supplied to the insulator224in some cases. Thus, the proportion of oxygen contained in the sputtering gas is higher than or equal to 70%, preferably higher than or equal to 80%, further preferably 100%.

In the case where the oxide film230B is formed by a sputtering method and the proportion of oxygen contained in the sputtering gas for deposition is higher than 30% and lower than or equal to 100%, preferably higher than or equal to 70% and lower than or equal to 100%, an oxygen-excess oxide semiconductor is formed. In a transistor using an oxygen-excess oxide semiconductor for its channel formation region, relatively high reliability can be obtained. Note that one embodiment of the present invention is not limited thereto. In the case where the oxide film230B is formed by a sputtering method and the proportion of oxygen contained in the sputtering gas for deposition is higher than or equal to 1% and lower than or equal to 30%, preferably higher than or equal to 5% and lower than or equal to 20%, an oxygen-deficient oxide semiconductor is formed. In a transistor using an oxygen-deficient oxide semiconductor for its channel formation region, relatively high field-effect mobility can be obtained. Furthermore, when the deposition is performed while the substrate is being heated, the crystallinity of the oxide film can be improved.

In this embodiment, the oxide film230A is formed by a sputtering method using an oxide target with In:Ga:Zn=1:3:4 [atomic ratio]. In addition, the oxide film230B is formed by a sputtering method using an oxide target with In:Ga:Zn=4:2:4.1 [atomic ratio]. Note that each of the oxide films is preferably formed to have characteristics required for the oxide230aand the oxide230bby selecting the deposition conditions and the atomic ratios as appropriate.

Next, an oxide film243A is formed over the oxide film230B (seeFIG.12AtoFIG.12D). The oxide film243A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The atomic ratio of Ga to In in the oxide film243A is preferably greater than the atomic ratio of Ga to In in the oxide film230B. In this embodiment, the oxide film243A is formed by a sputtering method using an oxide target with In:Ga:Zn=1:3:4 [atomic ratio].

Note that the insulator222, the insulator224, the oxide film230A, the oxide film230B, and the oxide film243A are preferably formed by a sputtering method without exposure to the air. For example, a multi-chamber deposition apparatus is used. As a result, the amounts of hydrogen in the formed insulator222, insulator224, oxide film230A, oxide film230B, and oxide film243A can be reduced, and furthermore, entry of hydrogen into the films in intervals between deposition steps can be inhibited.

Next, heat treatment is preferably performed. The heat treatment is performed in a temperature range where the oxide film230A, the oxide film230B, and the oxide film243A do not become polycrystals, i.e., at a temperature higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 400° C. and lower than or equal to 600° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, in the case where the heat treatment is performed in a mixed atmosphere of a nitrogen gas and an oxygen gas, the proportion of the oxygen gas may be approximately 20%. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in such a manner that heat treatment is performed in a nitrogen gas or inert gas atmosphere, and then another heat treatment is performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more in order to compensate for released oxygen.

The gas used in the above heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the above heat treatment is 1 ppb or less, preferably 0.1 ppb or less, and further preferably 0.05 ppb or less. The heat treatment using a highly purified gas can prevent entry of moisture or the like into the oxide film230A, the oxide film230B, the oxide film243A, and the like as much as possible.

In this embodiment, the heat treatment is performed in such a manner that treatment is performed at 400° C. in a nitrogen atmosphere for one hour and then another treatment is successively performed at 400° C. in an oxygen atmosphere for one hour. By the heat treatment, impurities such as water and hydrogen in the oxide film230A, the oxide film230B, and the oxide film243A can be removed, for example. Furthermore, the heat treatment improves the crystallinity of the oxide film230B, thereby offering a dense structure with higher density. Thus, diffusion of oxygen or impurities in the oxide film230B can be reduced.

Next, a conductive film242A is formed over the oxide film243A (seeFIG.12Ato FIG.12D). The conductive film242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, for the conductive film242A, tantalum nitride is deposited by a sputtering method. Note that heat treatment may be performed before the formation of the conductive film242A. This heat treatment may be performed under reduced pressure, and the conductive film242A may be successively formed without exposure to the air. The treatment can remove moisture and hydrogen adsorbed onto the surface of the oxide film243A or the like, and further can reduce the moisture concentration and the hydrogen concentration in the oxide film230A, the oxide film230B, and the oxide film243A. The heat treatment is preferably performed at a temperature higher than or equal to 100° C. and lower than or equal to 400° C. In this embodiment, the heat treatment is performed at 200° C.

Next, an insulating film271A is formed over the conductive film242A (seeFIG.12AtoFIG.12D). The insulating film271A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film271A, an insulating film having a function of inhibiting passage of oxygen is preferably used. For example, for the insulating film271A, aluminum oxide or silicon nitride may be deposited by a sputtering method.

In this embodiment, for the insulating film271A, aluminum oxide is deposited by a pulsed DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas. The RF power applied to the substrate is lower than or equal to 0.62 W/cm2, preferably higher than or equal to 0 W/cm2and lower than or equal to 0.31 W/cm2. With low RF power, the amount of oxygen implanted into the conductive film242A can be reduced and oxidation of the conductive film242A can be prevented.

Note that the conductive film242A and the insulating film271A are preferably formed by a sputtering method without exposure to the air. For example, a multi-chamber deposition apparatus is used. As a result, the amounts of hydrogen in the formed conductive film242A and insulating film271A can be reduced, and furthermore, entry of hydrogen into the films in intervals between deposition steps can be inhibited. In the case where a hard mask is provided over the insulating film271A, a film to be the hard mask is preferably successively formed without exposure to the air.

Next, the oxide film230A, the oxide film230B, the oxide film243A, the conductive film242A, and the insulating film271A are processed into island shapes by a lithography method to form the oxide230a, the oxide230b, an oxide layer243B, a conductive layer242B, and an insulating layer271B (seeFIG.13AtoFIG.13D). A dry etching method or a wet etching method can be used for the processing. Processing by a dry etching method is suitable for microfabrication. The oxide film230A, the oxide film230B, the oxide film243A, the conductive film242A, and the insulating layer271B may be processed under different conditions. In this step, the insulator224may be processed into an island shape so as to be overlapped by the oxide230a.

Note that in a lithography method, first, a resist is exposed to light through a mask. Next, a region exposed to light is removed or left using a developing solution, so that a resist mask is formed. Then, etching process through the resist mask is conducted, whereby a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape. The resist mask is formed through, for example, exposure of the resist to KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Alternatively, a liquid immersion technique may be employed in which a gap between a substrate and a projection lens is filled with liquid (e.g., water) in light exposure. Alternatively, an electron beam or an ion beam may be used instead of the light. Note that a mask is unnecessary in the case of using an electron beam or an ion beam. Note that the resist mask can be removed by dry etching process such as ashing, wet etching process, wet etching process after dry etching process, or dry etching process after wet etching process.

In addition, a hard mask formed of an insulator or a conductor may be used under the resist mask. In the case of using a hard mask, a hard mask with a desired shape can be formed in the following manner: an insulating film or a conductive film that is the material of the hard mask is formed over the conductive film242A, a resist mask is formed thereover, and then the hard mask material is etched. The etching of the conductive film242A and the like may be performed after removing the resist mask or with the resist mask remaining. In the latter case, the resist mask sometimes disappears during the etching. The hard mask may be removed by etching after the etching of the conductive film242A and the like. Meanwhile, the hard mask does not necessarily need to be removed when the hard mask material does not affect later steps or can be utilized in later steps. In this embodiment, the insulating layer271B is used as a hard mask. In the case where the insulating layer271B is used as a hard mask, it is preferable to adjust the thickness of the insulating layer271B as appropriate in order to prevent the insulating layer271B from disappearing during the etching of the conductive film242A or the like.

Here, the insulating layer271B functions as a mask for the conductive layer242B: thus, as illustrated inFIG.13BandFIG.13C, the conductive layer242B does not have a curved surface between the side surface and the top surface. Thus, end portions at the intersections of the side surfaces and the top surfaces of the conductor242aand the conductor242billustrated inFIG.4Bare angular. The cross-sectional area of the conductor242is larger in the case where the end portion at the intersection of the side surface and the top surface of the conductor242is angular than in the case where the end portion is rounded. Accordingly, the resistance of the conductor242is reduced, so that the on-state current of the transistor200can be increased.

Here, the insulator224, the oxide230a, the oxide230b, the oxide layer243B, the conductive layer242B, and the insulating layer271B are formed so as to at least partly overlap the conductor205. It is preferable that the side surfaces of the insulator224, the oxide230a, the oxide230b, the oxide layer243B, the conductive layer242B, and the insulating layer271B be substantially perpendicular to the top surface of the insulator222. When the side surfaces of the insulator224, the oxide230a, the oxide230b, the oxide layer243B, the conductive layer242B, and the insulating layer271B are substantially perpendicular to the top surface of the insulator222, a plurality of transistors200can be provided in a smaller area and at a higher density. Alternatively, a structure may be employed in which an angle formed by the side surfaces of the insulator224, the oxide230a, the oxide230b, the oxide layer243B, the conductive layer242B, and the insulating layer271B and the top surface of the insulator222is a low angle. In that case, the angle formed by the side surfaces of the insulator224, the oxide230a, the oxide230b, the oxide layer243B, the conductive layer242B, and the insulating layer271B and the top surface of the insulator222is preferably greater than or equal to 60° and less than 70°. With such a shape, in later steps, the coverage with the insulator272and the like can be improved, so that defects such as a void can be reduced.

A by-product generated in the etching process is sometimes formed in a layered manner on the side surfaces of the insulator224, the oxide230a, the oxide230b, the oxide layer243B, the conductive layer242B, and the insulating layer271B. In that case, the layered by-product is formed between the insulator272and each of the insulator224, the oxide230a, the oxide230b, the oxide243, the conductor242, and the insulator271. When the manufacturing process of the transistor200proceeds in a state where the layered by-product is formed, the reliability of the transistor200might decrease. Hence, the layered by-product is preferably removed.

Next, the insulator272is formed over the insulator222, the insulator224, the oxide230a, the oxide230b, the oxide layer243B, the conductive layer242B, and the insulating layer271B (seeFIG.14AtoFIG.14D). The insulator272can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, for the insulator272, aluminum oxide is deposited by a pulsed DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas. The RF power applied to the substrate is lower than or equal to 0.62 W/cm2, preferably higher than or equal to 0 W/cm2and lower than or equal to 0.31 W/cm2. With low RF power, the amount of oxygen implanted into the insulator224can be reduced. The insulator272is in close contact with part of the top surface of the insulator222.

The insulator272may have a stacked-layer structure. For example, aluminum oxide may be deposited by a sputtering method and silicon nitride may be deposited over the aluminum oxide by a sputtering method. When the insulator272has such a multilayer structure, the function of inhibiting diffusion of impurities such as water or hydrogen and oxygen is improved in some cases.

In this manner, the oxide230a, the oxide230b, the oxide layer243B, and the conductive layer242B can be covered with the insulator272and the insulating layer271B, which have a function of inhibiting diffusion of oxygen. This can inhibit diffusion of oxygen into the oxide230a, the oxide230b, the oxide layer243B, and the conductive layer242B in a later step.

Next, an insulating film to be the insulator280is formed over the insulator272. The insulating film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. A silicon oxide film is formed by a sputtering method as the insulating film, for example. When the insulating film to be the insulator280is formed by a sputtering method in an oxygen-containing atmosphere, the insulator280containing excess oxygen can be formed. By using a sputtering method that does not need to use hydrogen as a deposition gas, the hydrogen concentration in the insulator280can be reduced. Note that heat treatment may be performed before the insulating film is formed. The heat treatment may be performed under reduced pressure, and the insulating film may be successively formed without exposure to the air. The treatment can remove moisture and hydrogen adsorbed onto the surface of the insulator272and the like, and further can reduce the moisture concentration and the hydrogen concentration in the oxide230a, the oxide230b, the oxide layer243B, and the insulator224. For the heat treatment, the above heat treatment conditions can be used.

Next, the insulating film to be the insulator280is subjected to CMP treatment, so that the insulator280with a flat top surface is formed (seeFIG.14AtoFIG.14D). Note that, for example, silicon nitride may be deposited over the insulator280by a sputtering method and CMP treatment may be performed on the silicon nitride until the insulator280is reached.

Then, part of the insulator280, part of the insulator272, part of the insulating layer271B, part of the conductive layer242B, and part of the oxide layer243B are processed to form an opening reaching the oxide230b. The opening is preferably formed so as to overlap the conductor205. The insulator271a, the insulator271b, the conductor242a, the conductor242b, the oxide243a, and the oxide243bare formed through the formation of the opening (seeFIG.15AtoFIG.15D).

An upper portion of the oxide230bis sometimes removed when the opening is formed. When part of the oxide230bis removed, a groove portion is formed in the oxide230b. The groove portion may be formed in the same step as the formation of the opening or in a step different from the formation of the opening in accordance with the depth of the groove portion.

The part of the insulator280, the part of the insulator272, the part of the insulating layer271B, the part of the conductive layer242B, and the part of the oxide layer243B can be processed by a dry etching method or a wet etching method. Processing by a dry etching method is suitable for microfabrication. The processing may be performed under different conditions. For example, the part of the insulator280may be processed by a dry etching method, the part of the insulator272and the part of the insulating layer271B may be processed by a wet etching method, and the part of the conductive layer242B and the part of the oxide layer243B may be processed by a dry etching method. Processing of the part of the conductive layer242B and processing of the part of the oxide layer243B may be performed under different conditions.

Here, in some cases, impurities are attached to the side surface of oxide230a, the top and side surfaces of the oxide230b, the side surface of the conductor242, and the side surface of the insulator280and diffuse therein. A step of removing the impurities may be performed. A damaged region is formed on the surface of the oxide230bby the dry etching in some cases. Such a damaged region may be removed. The impurities come from components contained in the insulator280, the insulator272, part of the insulating layer271B, and the conductive layer242B: components contained in a member of an apparatus used to form the opening; and components contained in a gas or a liquid used for etching, for instance. Examples of the impurities include hafnium, aluminum, silicon, tantalum, fluorine, and chlorine.

In particular, impurities such as aluminum and silicon hinder the oxide230bfrom becoming a CAAC-OS. It is thus preferable to reduce or remove impurity elements such as aluminum and silicon, which hinder the oxide from becoming a CAAC-OS. For example, the concentration of aluminum atoms in the oxide230band in the vicinity thereof is lower than or equal to 5.0 atomic %, preferably lower than or equal to 2.0 atomic %, further preferably lower than or equal to 1.5 atomic %, still further preferably lower than or equal to 1.0 atomic %, and yet further preferably lower than 0.3 atomic %.

Note that in a metal oxide, a region that is hindered from becoming a CAAC-OS by impurities such as aluminum and silicon and becomes an amorphous-like oxide semiconductor (a-like OS) is referred to as a non-CAAC region in some cases. In the non-CAAC region, the density of the crystal structure is reduced to increase VOH; thus, the transistor is likely to be normally on. Hence, the non-CAAC region in the oxide230bis preferably reduced or removed.

In contrast, the oxide230bpreferably has a layered CAAC structure. In particular, the CAAC structure preferably reaches a lower edge portion of a drain in the oxide230b. Here, in the transistor200, the conductor242aor the conductor242b, and its vicinity function as a drain. In other words, the oxide230bin the vicinity of the lower edge portion of the conductor242a(conductor242b) preferably has a CAAC structure. In this manner, the damaged region of the oxide230bis removed and the CAAC structure is formed in the edge portion of the drain, which significantly affects the drain withstand voltage, so that variations in the electrical characteristics of the transistor200can be further suppressed. In addition, the reliability of the transistor200can be improved.

In order to remove the above impurities and the like, cleaning treatment is performed. Examples of the cleaning method include wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning by heat treatment, and any of these cleanings may be performed in combination as appropriate. The cleaning treatment sometimes makes the groove portion deeper.

As the wet cleaning, cleaning treatment may be performed using an aqueous solution in which ammonia water, oxalic acid, phosphoric acid, hydrofluoric acid, or the like is diluted with carbonated water or pure water; pure water; carbonated water; or the like. Alternatively, ultrasonic cleaning using such an aqueous solution, pure water, or carbonated water may be performed. Alternatively, such cleaning methods may be performed in combination as appropriate.

Note that in this specification and the like, in some cases, an aqueous solution in which commercial hydrofluoric acid is diluted with pure water is referred to as diluted hydrofluoric acid, and an aqueous solution in which commercial ammonia water is diluted with pure water is referred to as diluted ammonia water. The concentration, temperature, and the like of the aqueous solution may be adjusted as appropriate in accordance with an impurity to be removed, the structure of a semiconductor device to be cleaned, or the like. The concentration of ammonia in the diluted ammonia water is higher than or equal to 0.01% and lower than or equal to 5%, preferably higher than or equal to 0.1% and lower than or equal to 0.5%. The concentration of hydrogen fluoride in the diluted hydrofluoric acid is higher than or equal to 0.01 ppm and lower than or equal to 100 ppm, preferably higher than or equal to 0.1 ppm and lower than or equal to 10 ppm.

A frequency greater than or equal to 200 kHz, preferably greater than or equal to 900 kHz is preferably used for the ultrasonic cleaning. Damage to the oxide230band the like can be reduced with this frequency.

The cleaning treatment may be performed a plurality of times, and the cleaning solution may be changed in every cleaning treatment. For example, the first cleaning treatment may use diluted hydrofluoric acid or diluted ammonia water and the second cleaning treatment may use pure water or carbonated water.

As the cleaning treatment in this embodiment, wet cleaning using diluted hydrofluoric acid is performed, and then, wet cleaning using pure water or carbonated water is performed. The cleaning treatment can remove impurities that are attached onto the surfaces of the oxide230a, the oxide230b, and the like or diffused into the oxide230a, the oxide230b, and the like. Furthermore, the crystallinity of the oxide230bcan be increased.

After the etching or the cleaning treatment, heat treatment may be performed. The heat treatment is performed at higher than or equal to 100° C. and lower than or equal to 450° C. preferably higher than or equal to 350° C. and lower than or equal to 400° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. In this case, oxygen can be supplied to the oxide230aand the oxide230bto reduce the amount of oxygen vacancies VO. In addition, the crystallinity of the oxide230bcan be improved by the heat treatment. The heat treatment may be performed under reduced pressure. Alternatively, heat treatment may be performed in an oxygen atmosphere, and then heat treatment may be successively performed in a nitrogen atmosphere without exposure to the air.

Next, an insulating film250A to be the insulator250ais formed (seeFIG.16AtoFIG.16D). Heat treatment may be performed before the formation of the insulating film250A; the heat treatment may be performed under reduced pressure, and the insulating film250A may be formed successively without exposure to the air. The heat treatment is preferably performed in an oxygen-containing atmosphere. Such treatment can remove moisture and hydrogen adsorbed onto the surface of the oxide230band the like, and further can reduce the moisture concentration and the hydrogen concentration in the oxide230aand the oxide230b. The heat treatment is preferably performed at a temperature higher than or equal to 100° C. and lower than or equal to 400° C.

The insulating film250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film250A is preferably formed by a deposition method using a gas in which hydrogen atoms are reduced or removed. This can reduce the hydrogen concentration in the insulating film250A. The hydrogen concentration in the insulating film250A is preferably reduced because the insulating film250A becomes the insulator250that is in contact with the oxide230bin a later step.

The insulating film250A is preferably formed by an ALD method. The thickness of the insulator250, which functions as a gate insulating film of the miniaturized transistor200, needs to be extremely small (e.g., approximately 5 nm to 30 nm) and have a small variation. Since an ALD method is a deposition method in which a precursor and a reactant (oxidizer) are alternately introduced and the film thickness can be adjusted with the number of repetition times of the cycle, precise control of the film thickness is possible. Thus, the accuracy of the gate insulating film required by the miniaturized transistor200can be achieved. Furthermore, as illustrated inFIG.16BandFIG.16C, the insulating film250A needs to be formed on the bottom surface and a side surface of the opening formed in the insulator280and the like so as to have good coverage. One atomic layer can be deposited at a time on the bottom surface and the side surface of the opening, whereby the insulating film250A can be formed in the opening with good coverage.

For example, in the case where the insulating film250A is formed by a PECVD method, the deposition gas containing hydrogen is decomposed in plasma to generate a large amount of hydrogen radicals. Oxygen in the oxide230bis extracted by reduction reaction of hydrogen radicals to form VOH, so that the hydrogen concentration in the oxide230bincreases. In contrast, when the insulating film250A is formed by an ALD method, the generation of hydrogen radicals can be inhibited at the introduction of a precursor and the introduction of a reactant. Thus, the use of the ALD method for forming the insulating film250A can prevent an increase in the hydrogen concentration in the oxide230b.

In the case where the impurities are not removed before the formation of the insulating film250A, the impurities remain between the insulator250aand each of the oxide230a, the oxide230b, the conductor242, the insulator280, and the like in some cases.

Next, microwave treatment may be performed in an oxygen-containing atmosphere (seeFIG.16AtoFIG.16D). Here, dotted lines shown inFIG.16BtoFIG.16Dindicate high-frequency waves such as microwaves or RF, oxygen plasma, oxygen radicals, or the like. For the microwave treatment, a microwave treatment apparatus including a power source for generating high-density plasma using a microwave is preferably used, for example. The microwave treatment apparatus may include a power source for applying RF to the substrate side. The use of high-density plasma enables high-density oxygen radicals to be generated. Furthermore, application of RF to the substrate side allows oxygen ions generated by the high-density plasma to be efficiently introduced into the oxide230b. The microwave treatment is preferably performed under reduced pressure, and the pressure is set to 60 Pa or higher, preferably 133 Pa or higher, further preferably 200 Pa or higher, still further preferably 400 Pa or higher and 700 Pa or lower. Furthermore, the oxygen flow rate ratio (O2/O2+Ar) is lower than or equal to 50%, preferably higher than or equal to 10% and lower than or equal to 30%. The treatment temperature is lower than or equal to 750° C., preferably lower than or equal to 500° C. and is approximately 400° C., for example. After the oxygen plasma treatment, heat treatment may be successively performed without exposure to the air.

As illustrated inFIG.16BtoFIG.16D, the microwave treatment in an oxygen-containing atmosphere can convert an oxygen gas into plasma using high-frequency waves such as microwaves or RF, and apply the oxygen plasma to a region of the oxide230bwhich is between the conductor242aand the conductor242b. At this time, the region230bccan also be irradiated with the high-frequency waves such as microwaves or RF. In other words, the high-frequency waves such as microwaves or RF the oxygen plasma, or the like can be applied to the region230bcinFIG.5. The effect of the plasma, the microwave, or the like enables VOH in the region230bcto be cut, and hydrogen H to be removed from the region230bc. That is, the reaction “VOH→H+VO” occurs in the region230bc, so that the concentration of hydrogen in the region230bccan be reduced. As a result, oxygen vacancies and VOH in the region230bccan be reduced to lower the carrier concentration. In addition, oxygen radicals generated by the oxygen plasma or oxygen contained in the insulator250can be supplied to oxygen vacancies formed in the region230bc, thereby further reducing oxygen vacancies and lowering the carrier concentration in the region230bc.

Meanwhile, the conductor242aand the conductor242bare provided over the region230baand the region230bbillustrated inFIG.5. As illustrated inFIG.16BtoFIG.16D, the effect of the high-frequency waves such as microwaves or RF, the oxygen plasma, or the like is blocked by the conductor242aand the conductor242b, and thus does not reach the region230baand the region230bb. Hence, a reduction in VOH and supply of an excess amount of oxygen due to the microwave treatment do not occur in the region230baand the region230bb, preventing a decrease in carrier concentration.

In the above manner, oxygen vacancies and VOH can be selectively removed from the region230bcin the oxide semiconductor, whereby the region230bccan be an i-type or substantially i-type region. Furthermore, supply of an excess amount of oxygen to the region230baand the region230bbfunctioning as the source region and the drain region can be inhibited and the n-type regions can be maintained. As a result, a change in the electrical characteristics of the transistor200can be inhibited, and thus a variation in the electrical characteristics of the transistors200in the substrate plane can be inhibited.

Thus, a semiconductor device with small variations in transistor characteristics can be provided. A semiconductor device having favorable reliability can be provided. A semiconductor device having favorable electrical characteristics can be provided.

Next, an insulating film250B to be the insulator250bis formed (seeFIG.17AtoFIG.17D). The insulating film250B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulating film250B is preferably formed using an insulator having a function of inhibiting diffusion of oxygen. With such a structure, oxygen contained in the insulator250acan be inhibited from diffusing into the conductor260. That is, a reduction in the amount of oxygen supplied to the oxide230can be inhibited. In addition, oxidation of the conductor260due to oxygen contained in the insulator250acan be inhibited. For example, the insulating film250A can be formed using the above-described material that can be used for the insulator250, and the insulating film250B can be formed using a material similar to that for the insulator222.

Specifically, for the insulating film250B, a metal oxide containing one kind or two or more kinds selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, and the like, or a metal oxide that can be used for the oxide230can be used. In particular, an insulator including an oxide of one or both of aluminum and hafnium is preferably used.

In this embodiment, silicon oxynitride is deposited for the insulating film250A by a CVD method, and hafnium oxide is deposited for the insulating film250B by a thermal ALD method.

After the insulating film250B is formed, microwave treatment may be performed. For the microwave treatment, the conditions for the microwave treatment performed after the formation of the insulating film250A may be used. Alternatively, microwave treatment may be performed after the formation of the insulating film250B without performing microwave treatment after the formation of the insulating film250A.

Heat treatment with the reduced pressure being maintained may be performed after each of microwave treatment after the formation of the insulating film250A and microwave treatment after the formation of the insulating film250B. Such treatment enables hydrogen in the insulating film250A, the insulating film250B, the oxide230b, and the oxide230ato be removed efficiently. Part of hydrogen is gettered by the conductor242(the conductor242aand the conductor242b) in some cases. Alternatively, the step of performing microwave treatment and then performing heat treatment with the reduced pressure being maintained may be repeated a plurality of cycles. The repetition of the heat treatment enables hydrogen in the insulating film250A, the oxide230b, and the oxide230ato be removed more efficiently. Note that the temperature of the heat treatment is preferably higher than or equal to 300° C. and lower than or equal to 500° C.

Furthermore, the microwave treatment improves the film quality of the insulating film250A and the insulating film250B, thereby inhibiting diffusion of hydrogen, water, impurities, and the like. Accordingly, hydrogen, water, impurities, and the like can be inhibited from diffusing into the oxide230b, the oxide230a, and the like through the insulator250in a later step such as formation of a conductive film to be the conductor260or later treatment such as heat treatment.

Next, a conductive film to be the conductor260aand a conductive film to be the conductor260bare formed in this order. The conductive film to be the conductor260aand the conductive film to be the conductor260bcan be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, the conductive film to be the conductor260ais formed by an ALD method, and the conductive film to be the conductor260bis formed by a CVD method.

Then, the insulating film250A, the insulating film250B, the conductive film to be the conductor260a, and the conductive film to be the conductor260bare polished by CMP treatment until the insulator280is exposed, whereby the insulator250a, the insulator250b, and the conductor260(the conductor260aand the conductor260b) are formed (seeFIG.18AtoFIG.18D). Accordingly, the insulator250is placed so as to cover the inner wall (the sidewall and the bottom surface) of the opening reaching the oxide230band the groove portion of the oxide230b. The conductor260is placed to fill the opening and the groove portion with the insulator250therebetween.

Then, heat treatment may be performed under conditions similar to those for the above heat treatment. In this embodiment, treatment is performed at 400° C. in a nitrogen atmosphere for one hour. The heat treatment can reduce the moisture concentration and the hydrogen concentration in the insulator250and the insulator280. After the heat treatment, the insulator282may be formed successively without exposure to the air.

Here, oxygen adding treatment may be performed on the insulator280. Specifically, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used for the oxygen adding treatment. Plasma treatment may be performed on the insulator to implant oxygen into the insulator. A dry etching apparatus, a plasma CVD apparatus, a sputtering apparatus, or the like can be used to generate the plasma.

The amount and depth of oxygen implantation into the insulator280are preferably controlled to the extent that oxygen does not influence the functions of conductors included in the transistor200, such as the conductor260and the conductor242.

Next, the insulator282ais formed over the insulator250, the conductor260, and the insulator280(FIG.19AtoFIG.19D). For the insulator282a, a material that inhibits oxygen diffusion is preferably used. The insulator282ahas such a thickness that inhibits damage caused by the following oxygen adding treatment and does not hinder oxygen implantation into the insulator280.

The insulator282acan be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator282ais preferably formed by a sputtering method. By using a sputtering method that does not need to use hydrogen as a deposition gas, the hydrogen concentration in the insulator282acan be reduced.

In this embodiment, for the insulator282a, aluminum oxide is deposited by a pulsed DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas. The use of a pulsed DC sputtering method can achieve more uniform film thickness and improve the sputtering rate and film quality. The RF power applied to the substrate is lower than or equal to 1.86 W/cm2, preferably higher than or equal to 0 W/cm2and lower than or equal to 0.31 W/cm2. With low RF power, the amount of oxygen implanted into the insulator280can be reduced. In this embodiment, the insulator282ais formed with an RF power of 0 W/cm2applied to the substrate.

Subsequently, oxygen adding treatment is performed on the insulator280through the insulator282a(shown by arrows inFIG.19AtoFIG.19D). Specifically, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or the like can be used for oxygen adding treatment. Plasma treatment may be performed on the insulator to implant oxygen thereinto. A dry etching apparatus, a plasma CVD apparatus, a sputtering apparatus, or the like can be used as a plasma generating apparatus.

The oxygen adding treatment through the insulator282acan inhibit damage on the insulator280. Furthermore, since the insulator282ainhibits oxygen diffusion, oxygen implanted into the insulator280is not released to the outside during the step and can be efficiently implanted into the insulator280.

In the case where an oxide is used as the insulator282a, oxygen may also be added to the insulator282a. Treatment involving heating in a subsequent step makes excess oxygen in the insulator282amove to the insulator280, and oxygen moved to the insulator280can compensate for oxygen vacancies in the oxide semiconductor.

Next, the insulator282bis formed over the insulator282a(seeFIG.20AtoFIG.20D). As in the case of the insulator282a, a material that inhibits oxygen diffusion is preferably used for the insulator282b. The thickness of the insulator282bis preferably larger than that of the insulator282a. When the insulator282bis provided over the insulator282adamaged by the oxygen adding treatment, excess oxygen added to the insulator280can be inhibited from being released to the outside.

The insulator282bcan be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator282bis preferably formed by a sputtering method. By using a sputtering method that does not need to use hydrogen as a deposition gas, the hydrogen concentration in the insulator282bcan be reduced.

In this embodiment, for the insulator282b, aluminum oxide is deposited by a pulsed DC sputtering method using an aluminum target in an atmosphere containing an oxygen gas, as in the case of the insulator282a. The use of the pulsed DC sputtering method can achieve more uniform film thickness and improve the sputtering rate and film quality. The RF power applied to the substrate is lower than or equal to 1.86 W/cm2, preferably higher than or equal to 0 W/cm2and lower than or equal to 0.31 W/cm2. With low RF power, the amount of oxygen implanted into the insulator280can be reduced. In this embodiment, the insulator282bis formed with an RF power of 0.31 W/cm2applied to the substrate.

Next, part of the insulator282aand part of the insulator282bare processed in accordance with the density of the transistors arranged in each of the circuit regions, so that the opening region400is formed (seeFIG.21D). In the opening region400, the insulator280has a depressed portion in some cases. For the processing of the part of the insulator282a, the part of the insulator282b, and part of the insulator280, wet etching can be performed; however, dry etching is preferably used for microfabrication. The depth of the depressed portion in the insulator280is greater than or equal to ¼ and less than or equal to ½ of the largest thickness of the insulator280in the semiconductor device.

Next, the insulator282a, the insulator282b, the insulator280, the insulator272, the insulator222, the insulator216, and the insulator214are processed until the top surface of the insulator212is reached (seeFIG.22AtoFIG.22C). Wet etching can be used for the processing; however, dry etching is preferably used for microfabrication.

Then, heat treatment is performed. The heat treatment is performed at higher than or equal to 250° C. and lower than or equal to 650° C., preferably higher than or equal to 400° C. and lower than or equal to 600° C. Through the heat treatment, excess oxygen contained in the insulator280moves to the oxide230and is supplied to oxygen vacancies in the oxide230. That is, oxygen vacancies in the oxide230are reduced, so that the oxide230becomes highly purified intrinsic.

The temperature of the heat treatment is preferably lower than that of heat treatment performed after formation of the oxide film243A. The heat treatment is performed in an atmosphere of a nitrogen gas or an inert gas. Through the heat treatment, oxygen contained in the insulator280and hydrogen bonded to the oxygen can be released to the outside from a side surface of the insulator280, which is formed by processing the insulator282a, the insulator282b, the insulator280, the insulator272, the insulator222, the insulator216, and the insulator214. In addition, oxygen contained in the insulator280and hydrogen bonded to the oxygen can be released to the outside through the opening region400. The hydrogen bonded to oxygen is released as water. Thus, unnecessary oxygen and hydrogen contained in the insulator280can be reduced.

Heat treatment may be performed after the formation of the opening region400, and then, another heat treatment may be performed after the processing of the insulator280, the insulator272, the insulator222, the insulator216, and the insulator214.

Next, the insulator283is formed over the insulator282b(seeFIG.23AtoFIG.23D). The insulator283is preferably in contact with the insulator280in the opening region400. The insulator283can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The insulator283is preferably formed by a sputtering method. By using a sputtering method that does not need to use hydrogen as a deposition gas, the hydrogen concentration in the insulator283can be reduced. The insulator283may be a multilayer. For example, silicon nitride may be deposited by a sputtering method and silicon nitride may be deposited over the silicon nitride by an ALD method. Surrounding the transistor200by the insulator283and the insulator212having high barrier properties can prevent entry of moisture and hydrogen from the outside.

Next, the insulator274is formed over the insulator283(seeFIG.23AtoFIG.23D). The insulator274can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, for the insulator274, silicon oxide is deposited by a CVD method.

Next, the insulator274is polished by CMP treatment until the insulator283is exposed, whereby the top surface of the insulator274is planarized (seeFIG.23AtoFIG.23D). The top surface of the insulator283is partly removed by the CMP treatment in some cases. In addition, by the CMP treatment, the opening region400is filled with part of the insulator274over the insulator283.

Next, the insulator286is formed over the insulator274and the insulator283(seeFIG.23AtoFIG.23D). The insulator286can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, for the insulator286, silicon oxide is deposited by a sputtering method.

Subsequently, openings reaching the conductor242are formed in the insulator271, the insulator272, the insulator280, the insulator282, the insulator283, and the insulator286(seeFIG.23AtoFIG.23C). The openings are formed by a lithography method. Note that the openings in the top view inFIG.23Aeach have a circular shape; however, the shapes of the openings are not limited thereto. For example, the openings in the top view may each have an almost circular shape such as an elliptical shape, a polygonal shape such as a quadrangular shape, or a polygonal shape such as a quadrangular shape with rounded corners.

Subsequently, an insulating film to be the insulator241is formed and the insulating film is subjected to anisotropic etching, so that the insulator241is formed (seeFIG.23B). The insulating film to be the insulator241can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film to be the insulator241, an insulating film having a function of inhibiting passage of oxygen is preferably used. For example, aluminum oxide is preferably deposited by an ALD method. Alternatively, silicon nitride is preferably deposited by a PEALD method. Silicon nitride is preferable because it has a high blocking property against hydrogen.

For anisotropic etching for the insulating film to be the insulator241, a dry etching method may be employed, for example. When the insulator241is provided on the sidewall portions of the openings, passage of oxygen from the outside can be inhibited and oxidation of the conductor240aand the conductor240bto be formed next can be prevented. Furthermore, impurities such as water and hydrogen can be prevented from diffusing from the conductor240aand the conductor240bto the outside.

Next, a conductive film to be the conductor240aand the conductor240bis formed. The conductive film to be the conductor240aand the conductor240bdesirably has a stacked-layer structure which includes a conductor having a function of inhibiting passage of impurities such as water and hydrogen. For example, a stacked layer of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be employed. The conductive film to be the conductor240can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Then, part of the conductive film to be the conductor240aand the conductor240bis removed by CMP treatment to expose the top surface of the insulator274. As a result, the conductive film remains only in the openings, so that the conductor240aand the conductor240bhaving flat top surfaces can be formed (seeFIG.23B). Note that the top surface of the insulator286is partly removed by the CMP treatment in some cases.

Next, a conductive film to be the conductor246is formed. The conductive film to be the conductor246can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

Then, the conductive film to be the conductor246is processed by a lithography method, thereby forming the conductor246ain contact with the top surface of the conductor240aand the conductor246bin contact with the top surface of the conductor240b. Although not illustrated, part of the insulator286in a region where the insulator286does not overlap the conductor246aand the conductor246bis sometimes removed at this time.

Through the above process, the semiconductor device including the transistor200illustrated inFIG.4AtoFIG.4Dcan be manufactured. As illustrated inFIG.7AtoFIG.23D, the transistor200can be manufactured with the use of the method for manufacturing the semiconductor device described in this embodiment.

A microwave treatment apparatus that can be used for the above method for manufacturing the semiconductor device is described below.

First, a structure of a manufacturing apparatus that hardly allows entry of impurities in manufacturing a semiconductor device or the like is described with reference toFIG.24,FIG.25, andFIG.26.

FIG.24schematically illustrates a top view of a single wafer multi-chamber manufacturing apparatus2700. The manufacturing apparatus2700includes an atmosphere-side substrate supply chamber2701including a cassette port2761for storing substrates and an alignment port2762for performing alignment of substrates; an atmosphere-side substrate transfer chamber2702through which a substrate is transferred from the atmosphere-side substrate supply chamber2701; a load lock chamber2703awhere a substrate is carried in and the pressure inside the chamber is switched from atmospheric pressure to reduced pressure or from reduced pressure to atmospheric pressure; an unload lock chamber2703bwhere a substrate is carried out and the pressure inside the chamber is switched from reduced pressure to atmospheric pressure or from atmospheric pressure to reduced pressure; a transfer chamber2704through which a substrate is transferred in a vacuum; a chamber2706a; a chamber2706b; a chamber2706c: and a chamber2706d.

Furthermore, the atmosphere-side substrate transfer chamber2702is connected to the load lock chamber2703aand the unload lock chamber2703b, the load lock chamber2703aand the unload lock chamber2703bare connected to the transfer chamber2704, and the transfer chamber2704is connected to the chamber2706a, the chamber2706b, the chamber2706c, and the chamber2706d.

Note that gate valves GV are provided in connecting portions between the chambers so that each chamber excluding the atmosphere-side substrate supply chamber2701and the atmosphere-side substrate transfer chamber2702can be independently kept in a vacuum state. Furthermore, the atmosphere-side substrate transfer chamber2702is provided with a transfer robot2763a, and the transfer chamber2704is provided with a transfer robot2763b. With the transfer robot2763aand the transfer robot2763b, a substrate can be transferred inside the manufacturing apparatus2700.

The back pressure (total pressure) in the transfer chamber2704and each of the chambers is, for example, lower than or equal to 1×10−4Pa, preferably lower than or equal to 3×10−5Pa, further preferably lower than or equal to 1×10−5Pa. Furthermore, the partial pressure of a gas molecule (atom) having a mass-to-charge ratio (m/z) of 18 in the transfer chamber2704and each of the chambers is, for example, lower than or equal to 3×10−5Pa, preferably lower than or equal to 1×10−5Pa, further preferably lower than or equal to 3×106Pa. Furthermore, the partial pressure of a gas molecule (atom) having m/z of 28 in the transfer chamber2704and each of the chambers is, for example, lower than or equal to 3×10−5Pa, preferably lower than or equal to 1×10−5Pa, further preferably lower than or equal to 3×10−6Pa. Furthermore, the partial pressure of a gas molecule (atom) having m/z of 44 in the transfer chamber2704and each of the chambers is, for example, lower than or equal to 3×10−5Pa, preferably lower than or equal to 1×10−5Pa, further preferably lower than or equal to 3×10−6Pa.

Note that the total pressure and the partial pressure in the transfer chamber2704and each of the chambers can be measured using a mass analyzer. For example. Qulee CGM-051, a quadrupole mass analyzer (also referred to as Q-mass) produced by ULVAC, Inc. can be used.

Furthermore, the transfer chamber2704and the chambers each desirably have a structure in which the amount of external leakage or internal leakage is small. For example, the leakage rate in the transfer chamber2704and each of the chambers is less than or equal to 3×10−6Pa·m3/s, preferably less than or equal to 1×10−6Pa·m3/s. Furthermore, for example, the leakage rate of a gas molecule (atom) having m/z of 18 is less than or equal to 1×10−7Pa·m/s, preferably less than or equal to 3×10−8Pa·m3/s. Furthermore, for example, the leakage rate of a gas molecule (atom) having m/z of 28 is less than or equal to 1×10−5Pa·m3/s, preferably less than or equal to 1×10−6Pa·m3/s. Furthermore, for example, the leakage rate of a gas molecule (atom) having m/z of 44 is less than or equal to 3×10−6Pa·m3/s, preferably less than or equal to 1×10−6Pa·m3/s.

Note that a leakage rate can be derived from the total pressure and partial pressure measured using the above-described mass analyzer. The leakage rate depends on external leakage and internal leakage. The external leakage refers to inflow of gas from the outside of a vacuum system through a minute hole, a sealing defect, or the like. The internal leakage is due to leakage through a partition, such as a valve, in a vacuum system or released gas from an internal member. Measures need to be taken from both aspects of external leakage and internal leakage in order that the leakage rate can be set to less than or equal to the above-described value.

For example, open/close portions of the transfer chamber2704and each of the chambers are preferably sealed with a metal gasket. For the metal gasket, metal covered with iron fluoride, aluminum oxide, or chromium oxide is preferably used. The metal gasket achieves higher adhesion than an O-ring and can reduce the external leakage. Furthermore, with the use of the metal covered with iron fluoride, aluminum oxide, chromium oxide, or the like, which is in the passive state, the release of gas containing impurities released from the metal gasket is inhibited, so that the internal leakage can be reduced.

Furthermore, for a member of the manufacturing apparatus2700, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which releases a small amount of gas containing impurities, is used. Furthermore, an alloy containing iron, chromium, nickel, and the like covered with the above-described metal, which releases a small amount of gas containing impurities, may be used. The alloy containing iron, chromium, nickel, and the like is rigid, resistant to heat, and suitable for processing. Here, when surface unevenness of the member is reduced by polishing or the like to reduce the surface area, the release of gas can be reduced.

Alternatively, the above-described member of the manufacturing apparatus2700may be covered with iron fluoride, aluminum oxide, chromium oxide, or the like.

The member of the manufacturing apparatus2700is preferably formed using only metal when possible, and in the case where a viewing window formed of quartz or the like is provided, for example, the surface is preferably thinly covered with iron fluoride, aluminum oxide, chromium oxide, or the like to inhibit release of gas.

An adsorbed substance present in the transfer chamber2704and each of the chambers does not affect the pressure in the transfer chamber2704and each of the chambers because it is adsorbed onto an inner wall or the like; however, it causes a release of gas when the transfer chamber2704and each of the chambers are evacuated. Thus, although there is no correlation between the leakage rate and the exhaust rate, it is important that the adsorbed substance present in the transfer chamber2704and each of the chambers be desorbed as much as possible and exhaust be performed in advance with the use of a pump having high exhaust capability. Note that the transfer chamber2704and each of the chambers may be subjected to baking to promote desorption of the adsorbed substance. By the baking, the desorption rate of the adsorbed substance can be increased about tenfold. The baking is performed at higher than or equal to 100° C. and lower than or equal to 450° C. At this time, when the adsorbed substance is removed while an inert gas is introduced into the transfer chamber2704and each of the chambers, the desorption rate of water or the like, which is difficult to desorb simply by exhaust, can be further increased. Note that when the inert gas to be introduced is heated to substantially the same temperature as the baking temperature, the desorption rate of the adsorbed substance can be further increased. Here, a rare gas is preferably used as the inert gas.

Alternatively, treatment for evacuating the transfer chamber2704and each of the chambers is preferably performed a certain period of time after a heated inert gas such as a rare gas, heated oxygen, or the like is introduced to increase the pressure in the transfer chamber2704and each of the chambers. The introduction of the heated gas can desorb the adsorbed substance in the transfer chamber2704and each of the chambers, and impurities present in the transfer chamber2704and each of the chambers can be reduced. Note that this treatment is effective when repeated more than or equal to 2 times and less than or equal to 30 times, preferably more than or equal to 5 times and less than or equal to 15 times. Specifically, an inert gas, oxygen, or the like at a temperature higher than or equal to 40° C. and lower than or equal to 400° C., preferably higher than or equal to 50° C. and lower than or equal to 200° C. is introduced, so that the pressure in the transfer chamber2704and each of the chambers can be kept to be higher than or equal to 0.1 Pa and lower than or equal to 10 kPa, preferably higher than or equal to 1 Pa and lower than or equal to 1 kPa, further preferably higher than or equal to 5 Pa and lower than or equal to 100 Pa in the time range of 1 minute to 300 minutes, preferably 5 minutes to 120 minutes. After that, the transfer chamber2704and each of the chambers are evacuated in the time range of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

Next, the chamber2706band the chamber2706care described with reference to a schematic cross-sectional view illustrated inFIG.25.

The chamber2706band the chamber2706care chambers in which microwave treatment can be performed on an object, for example. Note that the chamber2706bis different from the chamber2706conly in the atmosphere in performing the microwave treatment. The other structures are common and thus collectively described below.

The chamber2706band the chamber2706ceach include a slot antenna plate2808, a dielectric plate2809, a substrate holder2812, and an exhaust port2819. Furthermore, a gas supply source2801, a valve2802, a high-frequency generator2803, a waveguide2804, a mode converter2805, a gas pipe2806, a waveguide2807, a matching box2815, a high-frequency power source2816, a vacuum pump2817, and a valve2818are provided outside the chamber2706band the chamber2706c, for example.

The high-frequency generator2803is connected to the mode converter2805through the waveguide2804. The mode converter2805is connected to the slot antenna plate2808through the waveguide2807. The slot antenna plate2808is placed in contact with the dielectric plate2809. Furthermore, the gas supply source2801is connected to the mode converter2805through the valve2802. Then, gas is transferred to the chamber2706band the chamber2706cthrough the gas pipe2806that runs through the mode converter2805, the waveguide2807, and the dielectric plate2809. Furthermore, the vacuum pump2817has a function of exhausting gas or the like from the chamber2706band the chamber2706cthrough the valve2818and the exhaust port2819. Furthermore, the high-frequency power source2816is connected to the substrate holder2812through the matching box2815.

As the vacuum pump2817, a dry pump, a mechanical booster pump, an ion pump, a titanium sublimation pump, a cryopump, or a turbomolecular pump can be used, for example. Furthermore, in addition to the vacuum pump2817, a cryotrap may be used. The use of the cryopump and the cryotrap is particularly preferable because water can be efficiently exhausted.

Furthermore, for example, the heating mechanism2813is a heating mechanism that uses a resistance heater or the like for heating. Alternatively, a heating mechanism that uses heat conduction or heat radiation from a medium such as a heated gas for heating may be used. For example, RTA (Rapid Thermal Annealing) such as GRTA (Gas Rapid Thermal Annealing) or LRTA (Lamp Rapid Thermal Annealing) can be used. In GRTA, heat treatment is performed using a high-temperature gas. An inert gas is used as the gas.

Furthermore, the gas supply source2801may be connected to a purifier through a mass flow controller. As the gas, a gas whose dew point is −80° C. or lower, preferably −100° C. or lower is preferably used. For example, an oxygen gas, a nitrogen gas, or a rare gas (an argon gas or the like) is used.

As the dielectric plate2809, silicon oxide (quartz), aluminum oxide (alumina), or yttrium oxide (yttria) is used, for example. Furthermore, another protective layer may be further formed on a surface of the dielectric plate2809. For the protective layer, magnesium oxide, titanium oxide, chromium oxide, zirconium oxide, hafnium oxide, tantalum oxide, silicon oxide, aluminum oxide, yttrium oxide, or the like is used. The dielectric plate2809is exposed to an especially high density region of high-density plasma2810described later; thus, provision of the protective layer can reduce the damage. Consequently, an increase in the number of particles or the like during the treatment can be inhibited.

The high-frequency generator2803has a function of generating a microwave of, for example, more than or equal to 0.3 GHz and less than or equal to 3.0 GHz, more than or equal to 0.7 GHz and less than or equal to 1.1 GHz, or more than or equal to 2.2 GHz and less than or equal to 2.8 GHz. The microwave generated by the high-frequency generator2803is propagated to the mode converter2805through the waveguide2804. The mode converter2805converts the microwave propagated in the TE mode into a microwave in the TEM mode. Then, the microwave is propagated to the slot antenna plate2808through the waveguide2807. The slot antenna plate2808is provided with a plurality of slot holes, and the microwave passes through the slot holes and the dielectric plate2809. Then, an electric field is generated below the dielectric plate2809, and the high-density plasma2810can be generated. In the high-density plasma2810, ions and radicals based on the gas species supplied from the gas supply source2801are present. For example, oxygen radicals are present.

At this time, the quality of a film or the like over the substrate2811can be modified by the ions and radicals generated in the high-density plasma2810. Note that it is preferable in some cases to apply a bias to the substrate2811side using the high-frequency power source2816. As the high-frequency power source2816, an RF (Radio Frequency) power source with a frequency of 13.56 MHz, 27.12 MHz, or the like is used, for example. The application of a bias to the substrate side allows ions in the high-density plasma2810to efficiently reach a deep portion of an opening portion of the film or the like over the substrate2811.

For example, in the chamber2706bor the chamber2706c, oxygen radical treatment using the high-density plasma2810can be performed by introducing oxygen from the gas supply source2801.

Next, the chamber2706aand the chamber2706dare described with reference to a schematic cross-sectional view illustrated inFIG.26.

The chamber2706aand the chamber2706dare chambers in which an object can be irradiated with an electromagnetic wave, for example. Note that the chamber2706ais different from the chamber2706donly in the kind of the electromagnetic wave. The other structures have many common portions and thus are collectively described below.

The chamber2706aand the chamber2706deach include one or a plurality of lamps2820, a substrate holder2825, a gas inlet2823, and an exhaust port2830. Furthermore, a gas supply source2821, a valve2822, a vacuum pump2828, and a valve2829are provided outside the chamber2706aand the chamber2706d, for example.

The gas supply source2821is connected to the gas inlet2823through the valve2822. The vacuum pump2828is connected to the exhaust port2830through the valve2829. The lamp2820is provided to face the substrate holder2825. The substrate holder2825has a function of holding a substrate2824. Furthermore, the substrate holder2825includes a heating mechanism2826therein and has a function of heating the substrate2824.

As the lamp2820, a light source having a function of emitting an electromagnetic wave such as visible light or ultraviolet light is used, for example. For example, a light source having a function of emitting an electromagnetic wave which has a peak in a wavelength region of longer than or equal to 10 nm and shorter than or equal to 2500 nm, longer than or equal to 500 nm and shorter than or equal to 2000 nm, or longer than or equal to 40 nm and shorter than or equal to 340 nm is used.

As the lamp2820, a light source such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp is used, for example.

For example, part or the whole of electromagnetic wave emitted from the lamp2820is absorbed by the substrate2824, so that the quality of a film or the like over the substrate2824can be modified. For example, generation or reduction of defects or removal of impurities can be performed. Note that generation or reduction of defects, removal of impurities, or the like can be efficiently performed while the substrate2824is heated.

Alternatively, for example, the electromagnetic wave emitted from the lamp2820may generate heat in the substrate holder2825to heat the substrate2824. In this case, the substrate holder2825does not need to include the heating mechanism2826therein.

For the vacuum pump2828, refer to the description of the vacuum pump2817. Furthermore, for the heating mechanism2826, refer to the description of the heating mechanism2813. Furthermore, for the gas supply source2821, refer to the description of the gas supply source2801.

With the use of the above-described manufacturing apparatus, the quality of a film or the like can be modified while the entry of impurities into an object is inhibited.

<Modification Example of Semiconductor Device>

An example of the semiconductor device of one embodiment of the present invention is described below with reference toFIG.27AtoFIG.27D.

Note that A of each drawing is a top view of the semiconductor device. Moreover, B of each drawing is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A1-A2in A of each drawing. Furthermore, C of each drawing is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A3-A4in A of each drawing. Furthermore, D of each drawing is a cross-sectional view corresponding to a portion indicated by dashed-dotted line A5-A6in A of each drawing. Note that for clarity of the drawing, some components are omitted in the top view of A of each drawing.

Note that in the semiconductor device illustrated in A to D of each drawing, components having the same functions as the components included in the semiconductor device described in <Structure example of semiconductor device> are denoted by the same reference numerals. Note that the materials described in detail in <Structure example of semiconductor device> can also be used as constituent materials of the semiconductor devices in this section.

A semiconductor device illustrated inFIG.27AtoFIG.27Dis a modification example of the semiconductor device illustrated inFIG.4AtoFIG.4D. The semiconductor device illustrated inFIG.27AtoFIG.27Dis different from the semiconductor device illustrated inFIG.4AtoFIG.4Din including an oxide230cand an oxide230d.

The semiconductor device illustrated inFIG.27AtoFIG.27Dfurther includes the oxide230cover the oxide230band the oxide230dover the oxide230c. The oxide230cand the oxide230dare provided in the opening formed in the insulator280and the insulator272. The oxide230cis in contact with a side surface of the oxide243a, a side surface of the oxide243b, a side surface of the conductor242a, a side surface of the conductor242b, a side surface of the insulator271a, aside surface of the insulator271b, and aside surface of the insulator272. The top surface of the oxide230cand the top surface of the oxide230dare in contact with the insulator282.

The oxide230dis placed over the oxide230c, whereby impurities can be inhibited from diffusing into the oxide230bor the oxide230cfrom components formed above the oxide230d. When the oxide230dis placed over the oxide230c, oxygen can be inhibited from diffusing upward from the oxide230bor the oxide230c.

In a cross-sectional view of the transistor in the channel length direction, it is preferable that a groove portion be provided in the oxide230band the oxide230cbe embedded in the groove portion. At this time, the oxide230cis placed so as to cover an inner wall (a sidewall and the bottom surface) of the groove portion. It is preferable that the thickness of the oxide230cbe approximately the same as the depth of the groove portion. With such a structure, even when the opening in which the conductor260and the like are embedded is formed and a damaged region is formed on a surface of the oxide230bat a bottom portion of the opening, the damaged region can be removed. Accordingly, defects in the electrical characteristics of the transistor200due to the damaged region can be reduced.

The atomic ratio of In to the element M in the metal oxide used as the oxide230cis preferably greater than the atomic ratio of In to the metal element M in the metal oxide used as the oxide230aor the oxide230d.

In order to make the oxide230cserve as a main carrier path, the atomic ratio of indium to a metal element that is a main component in the oxide230cis preferably greater than the atomic ratio of indium to a metal element that is a main component in the oxide230b. Furthermore, the atomic ratio of In to the element M in the oxide230cis preferably greater than the atomic ratio of In to the element M in the oxide230b. When a metal oxide having a high content of indium is used for a channel formation region, the on-state current of the transistor can be increased. Accordingly, when the atomic ratio of indium to a metal element that is a main component in the oxide230cis greater than the atomic ratio of indium to a metal element that is a main component in the oxide230b, the oxide230ccan serve as a main carrier path. The conduction band minimum of the oxide230cis preferably farther from the vacuum level than the conduction band minimum of each of the oxide230aand the oxide230bis. In other words, the electron affinity of the oxide230cis preferably larger than the electron affinity of each of the oxide230aand the oxide230b. At this time, the oxide230cserves as a main carrier path.

As the oxide230c, specifically, a metal oxide with a composition of In:M:Zn=4:2:3 [atomic ratio] or in the neighborhood thereof, a composition of In:M:Zn=5:1:3 [atomic ratio] or in the neighborhood thereof, or a composition of In:M:Zn=10:1:3 [atomic ratio] or in the neighborhood thereof, indium oxide, or the like is preferably used.

In addition, a CAAC-OS is preferably used for the oxide230c; the c-axis of a crystal included in the oxide230cis preferably aligned with a direction substantially perpendicular to the formation surface or top surface of the oxide230c. The CAAC-OS has a property of making oxygen move easily in the direction perpendicular to the c-axis. Thus, oxygen contained in the oxide230ccan be efficiently supplied to the oxide230b.

The oxide230dpreferably contains at least one of the metal elements contained in the metal oxide used for the oxide230c, and further preferably contains all of these metal elements. For example, it is preferable that an In-M-Zn oxide, an In—Zn oxide, or an indium oxide be used as the oxide230cand an In-M-Zn oxide, an M-Zn oxide, or an oxide of the element M be used as the oxide230d. Accordingly, the density of defect states at an interface between the oxide230cand the oxide230dcan be decreased.

The conduction band minimum of the oxide230dis preferably closer to the vacuum level than the conduction band minimum of the oxide230cis. In other words, the electron affinity of the oxide230dis preferably smaller than the electron affinity of the oxide230c. In that case, a metal oxide that can be used as the oxide230aor the oxide230bis preferably used as the oxide230d. At this time, the oxide230cserves as a main carrier path.

Specifically, for the oxide230c, a metal oxide with a composition of In:Al:Zn=4:2:3 [atomic ratio] or in the neighborhood thereof, a composition of In:M:Zn=5:1:3 [atomic ratio] or in the neighborhood thereof, or a composition of In:M:Zn=10:1:3 [atomic ratio] or in the neighborhood thereof, or indium oxide may be used. As the oxide230d, a metal oxide with a composition of In:M:Zn=1:3:4 [atomic ratio] or in the neighborhood thereof, a composition of M:Zn=2:1 [atomic ratio] or in the neighborhood thereof, a composition of M:Zn=2:5 [atomic ratio] or in the neighborhood thereof, or an oxide of the element M may be used. Note that a composition in the neighborhood includes the range of ±30% of an intended atomic ratio. Gallium is preferably used as the element M.

The oxide230dis preferably a metal oxide that inhibits diffusion or passage of oxygen more than the oxide230c. Providing the oxide230dbetween the insulator250and the oxide230cenables oxygen to be supplied efficiently to the oxide230bthrough the oxide230c.

When the atomic ratio of In to the metal element that is a main component in the metal oxide used as the oxide230dis smaller than the atomic ratio of In to the metal element that is a main component in the metal oxide used as the oxide230c, diffusion of In to the insulator250side can be inhibited. For example, the atomic ratio of In to the element M in the oxide230dis smaller than the atomic ratio of In to the element M in the oxide230c. Since the insulator250functions as a gate insulator, the transistor exhibits poor characteristics when In enters the insulator250and the like. Thus, the oxide230dprovided between the oxide230cand the insulator250allows the semiconductor device to have high reliability.

Note that the oxide230cmay be provided for each of the transistors200. That is, the oxide230cof the transistor200does not need to be in contact with the oxide230cof the adjacent transistor200. Furthermore, the oxide230cof the transistor200may be apart from the oxide230cof the adjacent transistor200. In other words, a structure in which the oxide230cis not placed between the transistor200and the adjacent transistor200may be employed.

When the above structure is employed for the semiconductor device where a plurality of transistors200are arranged in the channel width direction, the oxide230ccan be independently provided for each transistor200. Accordingly, generation of a parasitic transistor between the transistor200and the adjacent transistor200can be prevented, and generation of the leakage path can be prevented. Thus, a semiconductor device that has favorable electrical characteristics and can be miniaturized or highly integrated can be provided.

An example of the semiconductor device of one embodiment of the present invention is described below with reference toFIG.28.

FIG.28Ashows a top view of the semiconductor device.FIG.28Bis a cross-sectional view corresponding to a portion indicated by dashed-dotted line A3-A4inFIG.28A. The transistor200illustrated inFIG.4Bcan be referred to for a cross-sectional view corresponding to a portion indicated by dashed-dotted line A1-A2inFIG.28A. For clarity of the drawing, some components are not illustrated in the top view ofFIG.28A.

Note that in the semiconductor device illustrated inFIG.28, components having the same functions as the components included in the semiconductor device described in <Structure example of semiconductor device> are denoted by the same reference numerals. Note that the materials described in detail in <Structure example of semiconductor device> can also be used as constituent materials of the semiconductor devices in this section.

The semiconductor device illustrated inFIG.28is a modification example of the semiconductor device illustrated inFIG.4. The semiconductor device illustrated inFIG.28is different from the semiconductor device inFIG.4in that the transistor200includes n oxides230(an oxide230_1to an oxide230_n: n is a natural number). The oxide230_1to the oxide230_neach include a channel formation region.

In the semiconductor device shown inFIG.28, the conductor260is provided over the top surfaces and side surfaces of the plurality of channel formation regions with the insulator250therebetween. The conductor246(the conductor246aand the conductor246b) extends in the A3-A4direction and is electrically connected to the oxide230_1to the oxide230_nthrough the conductor240.

That is, in the semiconductor device illustrated inFIG.28, the transistor200includes a plurality of channel formation regions for one gate electrode. By including the plurality of channel formation regions, the transistor200shown inFIG.28can have a high on-state current. Furthermore, each channel formation region is surrounded by the gate electrode; in other words, an s-channel structure is employed: thus, a high on-state current can be obtained in each channel formation region. In the channel width direction of the transistor200, with reference to the bottom surface of the insulator222, the level of the bottom surface of the conductor260in the region where the conductor260and the oxide230bdo not overlap each other is lower than the level of the interface between the uppermost surface of the oxide230band the oxide230c; therefore, a high on-state current can be obtained in the channel formation regions.

For other components, the components of the semiconductor device shown inFIG.4can be referred to.

An example of the semiconductor device of one embodiment of the present invention is described below with reference toFIG.29.

Note thatFIG.29Ais a top view of the semiconductor device. Moreover,FIG.29Bis a cross-sectional view corresponding to a portion indicated by dashed-dotted line A3-A4inFIG.29A. For a cross-sectional view corresponding to a portion indicated by dashed-dotted line A1-A2inFIG.29A, the transistor200shown inFIG.4Bcan be referred to. Note that for clarity of the drawing, some components are omitted in the top view ofFIG.29A.

Note that in the semiconductor device illustrated inFIG.29, components having the same functions as the components included in the semiconductor device described in <Structure example of semiconductor device> are denoted by the same reference numerals. Note that the materials described in detail in <Structure example of semiconductor device> can also be used as constituent materials of the semiconductor devices in this section.

The semiconductor device illustrated inFIG.29is a modification example of the semiconductor device illustrated inFIG.28. In the semiconductor device illustrated inFIG.29, the transistor200includes n oxides230(the oxide230_1to the oxide230_n; n is a natural number). The oxide230_1to the oxide230_neach include a channel formation region.

In the semiconductor device shown inFIG.29, the conductor260is provided over the top surfaces and side surfaces of the plurality of channel formation regions with the insulator250therebetween. The conductor246(the conductor246aand the conductor246b) extends in the A3-A4direction and is electrically connected to the oxide230_1to the oxide230_nthrough the conductor240.

In the semiconductor device illustrated inFIG.29, the transistor200D including at least an oxide230D is positioned adjacent to the oxide2301positioned in the end portion of the transistor200with the plurality of channel formation regions. In a similar manner, the transistor200D is positioned adjacent to the oxide230npositioned in the end portion of the transistor200.

That is, the semiconductor device illustrated inFIG.29is different from the semiconductor device inFIG.28in that the transistor/transistors200D is/are provided at one side or both sides of the transistor200in the direction where the plurality of channel formation regions lie side by side.

Here, the transistor200D does not need to be electrically connected to any one or all of a gate wiring, a source wiring, and a drain wiring. That is, the transistor200D is provided in a state of not functioning as a transistor, in some cases. Thus, the transistor200D is referred to as a dummy transistor (sacrificial transistor) in some cases.

The shortest distance between the oxide230_D and the oxide230_1is preferably substantially equal to the shortest distance between the oxide230_1and the oxide230_2. Similarly, the shortest distance between the oxide230_D and the oxide230_nis preferably substantially equal to the shortest distance between an oxide230_n−1 and the oxide230_n. When n is 1, the shortest distance between one of the oxides230_D and the oxide230_1is preferably substantially equal to the shortest distance between the other oxide230_D and the oxide230_1.

The shortest distance between the conductor242aand the conductor242bin the oxide230_D is substantially equal to or larger than the shortest distance between the conductor242aand the conductor242bin the oxide230_1, in some cases. Similarly, the shortest distance between the conductor242aand the conductor242bin the oxide230_D is substantially equal to or larger than the shortest distance between the conductor242aand the conductor242bin the oxide230_n, in some cases.

In the case where the plurality of oxides230are formed in parallel, variations in the shapes of the oxides230positioned in the end portions are likely to be caused by processing. Furthermore, in the step of forming an opening by removing part of the insulator280and a stacked layer structure over the channel formation region of the oxide230so that part of the top surface of the oxide230is exposed, variations in the area of the exposed top surface of the oxide230are caused by the influence of the shape of the end portion of the removed region (also referred to as an opening), the distance from the end portion of the opening to the oxide230, or the like, in some cases.

Thus, the transistors200D are provided as illustrated inFIG.29, in which case the shapes of the oxides230formed in a region between the transistors200D are uniform even when a defect is caused in the shapes of the oxides230_D included in the transistors200D or a defect is caused in the shapes of the openings over the oxides230_D.

Accordingly, in the case where the plurality of transistors200are provided, positioning the transistors200D adjacent to the transistor200can reduce variations in the characteristics of the plurality of transistors200.

In the case where the plurality of oxides230are provided at regular intervals in a certain region, the layout of wirings is changed, facilitating circuit design.

In the semiconductor device illustrated inFIG.29, the transistor200includes a plurality of channel formation regions for one gate electrode. By including the plurality of channel formation regions, the transistor200shown inFIG.29can have a high on-state current. Furthermore, each channel formation region is surrounded by the gate electrode: in other words, an s-channel structure is employed; thus, a high on-state current can be obtained in each channel formation region. In the channel width direction of the transistor200, with reference to the bottom surface of the insulator222, the level of the bottom surface of the conductor260in the region where the conductor260and the oxide230bdo not overlap each other is lower than the level of the interface between the uppermost surface of the oxide230band the oxide230c; therefore, a high on-state current can be obtained in the channel formation regions.

For other components, the components of the semiconductor device shown inFIG.4can be referred to.

An example of the semiconductor device of one embodiment of the present invention is described below with reference toFIG.30.

Note thatFIG.30Ais a top view of the semiconductor device. Moreover,FIG.30Bis a cross-sectional view corresponding to a portion indicated by dashed-dotted line A3-A4inFIG.30A. For a cross-sectional view corresponding to a portion indicated by dashed-dotted line A1-A2inFIG.30A, the transistor200shown inFIG.4Bcan be referred to. Note that for clarity of the drawing, some components are omitted in the top view ofFIG.30A.

Note that in the semiconductor device illustrated inFIG.30, components having the same functions as the components included in the semiconductor device described in <Structure example of semiconductor device> are denoted by the same reference numerals. Note that the materials described in detail in <Structure example of semiconductor device> can also be used as constituent materials of the semiconductor devices in this section.

The semiconductor device described in this section is a modification example of the semiconductor device illustrated inFIG.29. Thus, the semiconductor device described in this section is different from the semiconductor device illustrated inFIG.29in that the transistor200includes the oxide230including n channel formation regions (n channel formation regions are a channel formation region235_1to a channel formation region235_n; n is a natural number). The conductor260is provided over the top surfaces and side surfaces of the plurality of channel formation regions with the insulator250therebetween.

The conductor242(the conductor242aand the conductor242b) extends in the A3-A4direction and is electrically connected to the conductor246(the conductor246aand the conductor246b) through the conductor240(the conductor240aand the conductor240b).

Here, for simplification of the description,FIG.30illustrates the case where n is 2. Thus, the transistor200includes the oxide230including two channel formation regions (the channel formation region235_1and the channel formation region235_2).

In the oxide230, a source region and a drain region are electrically connected to the conductor242aand the conductor242b. Therefore, for example, the conductor242aand the conductor246aare electrically connected to each other through at least one conductor240a, so that a voltage can be applied to the plurality of channel formation regions (the channel formation region2351to the channel formation region235_n).

That is, n conductors240do not necessarily need to be provided for the transistor200including the n channel formation regions235. The number of conductors240is preferably larger than or equal to 1, further preferably larger than or equal to 1 and smaller than n with respect to the transistor including the n channel formation regions235.

With miniaturization of the transistor, a plug that electrically connects the transistor and a conductor functioning as a wiring needs to be also miniaturized. Furthermore, a reduction in the contact area between a conductor functioning as a plug and the conductor functioning as a wiring tends to increase wiring resistance.

In the semiconductor device described in this section, less than n plugs are provided for the transistor200including the n channel formation regions: thus, the size of each of the conductors240functioning as a plug can be larger than that of the conductor240described in the semiconductor device illustrated inFIG.29, for example, resulting in a reduction in power consumption.

In the semiconductor device illustrated inFIG.30, the transistor200D including at least an oxide230D is positioned adjacent to the oxide2301positioned in the end portion of the transistor200with the plurality of channel formation regions. In a similar manner, the transistor200D is positioned adjacent to the oxide230_npositioned in the end portion of the transistor200.

Thus, in the semiconductor device shown inFIG.30, the conductor260is provided over the top surfaces and side surfaces of the plurality of channel formation regions with the insulator250therebetween. The conductor246aand the conductor246bextend in the A3-A4direction and are electrically connected to the oxide230_n.

In the semiconductor device illustrated inFIG.30, the transistor200D including at least the oxide230D is positioned adjacent to the channel formation region235_1positioned in the end portion of the transistor200with the plurality of channel formation regions. In a similar manner, the transistor200D is positioned adjacent to the channel formation region235npositioned in the end portion of the transistor200.

That is, the transistor/transistors200D is/are provided at one side or both sides of the transistor200in the direction where the plurality of channel formation regions lie side by side.

Here, the transistor200D does not need to be electrically connected to any one or all of a gate wiring, a source wiring, and a drain wiring. That is, the transistor200D is provided in a state of not functioning as a transistor, in some cases. Thus, the transistor200D is referred to as a dummy transistor (sacrificial transistor) in some cases.

The shortest distance between the oxide230_D and the oxide230_1is preferably substantially equal to the shortest distance between the oxide230_1and the oxide230_2. Similarly, the shortest distance between the oxide230_D and the oxide230_nis preferably substantially equal to the shortest distance between an oxide230_n−1 and the oxide230_n. When n is 1, the shortest distance between one of the oxides230_D and the oxide230_1is preferably substantially equal to the shortest distance between the other oxide230_D and the oxide230_1.

The shortest distance between the conductor242aand the conductor242bin the oxide230_D is substantially equal to or larger than the shortest distance between the conductor242aand the conductor242bin the oxide230_1, in some cases. Similarly, the shortest distance between the conductor242aand the conductor242bin the oxide230_D is substantially equal to or larger than the shortest distance between the conductor242aand the conductor242bin the oxide230_n, in some cases.

The difference between the shortest distance between the conductor242aand the conductor242bin the oxide230_D and the shortest distance between the conductor242aand the conductor242bin the oxide230_1is larger than the difference between the shortest distance between the conductor242aand the conductor242bin the oxide230_1and the shortest distance between the conductor242aand the conductor242bin the oxide230_2, in some cases.

In the case where the plurality of channel formation regions235are formed in parallel, variations in the shapes of the channel formation regions235positioned in the end portions are likely to be caused by processing. Furthermore, in the step of forming an opening by removing part of the insulator280and a stacked layer structure over the channel formation region of the oxide230so that part of the top surface of the oxide230is exposed, variations in the area of the exposed top surface of the oxide230are caused by the influence of the shape of the end portion of the removed region (also referred to as an opening), the distance from the end portion of the opening to the oxide230, or the like, in some cases.

Thus, the transistors200D are provided as illustrated inFIG.30, in which case the shapes of the oxides230formed in a region between the transistors200D are uniform even when a defect is caused in the shapes of the oxides230_D included in the transistors200D or a defect is caused in the shapes of the openings over the oxides230_D.

Accordingly, in the case where the plurality of transistors200are provided, positioning the transistors200D adjacent to the transistor200can reduce variations in the characteristics of the plurality of transistors200.

In the semiconductor device illustrated inFIG.30, the transistor200includes a plurality of channel formation regions for one gate electrode. By including the plurality of channel formation regions, the transistor200shown inFIG.30can have a high on-state current. Furthermore, each channel formation region is surrounded by the gate electrode; in other words, an s-channel structure is employed; thus, a high on-state current can be obtained in each channel formation region. In the channel width direction of the transistor200, with reference to the bottom surface of the insulator222, the level of the bottom surface of the conductor260in the region where the conductor260and the oxide230bdo not overlap each other is lower than the level of the interface between the uppermost surface of the oxide230band the oxide230c; therefore, a high on-state current can be obtained in the channel formation regions.

For other components, the components of the semiconductor device illustrated inFIG.4can be referred to.

<Application Example of Semiconductor Device>

Examples of a semiconductor device including the transistor200of one embodiment of the present invention and the opening region400, which are different from the ones described in the above <Structure example of semiconductor device> and the above <Modification example of semiconductor device>, are described below with reference toFIG.31AandFIG.31B. Note that in the semiconductor devices illustrated inFIG.31AandFIG.31B, components having the same functions as the components included in the semiconductor device described in <Structure example of semiconductor device> (seeFIG.4AtoFIG.4D) are denoted by the same reference numerals. Note that the materials described in detail in <Structure example of semiconductor device> and <Modification example of semiconductor device> can be used as the constituent materials of the transistor200in this section.

FIG.31AandFIG.31Beach illustrate a structure in which a plurality of transistors200_1to200_nare collectively sealed with the insulator283and the insulator212. Note that although the transistor200_1to the transistor200_nappear to be arranged in the channel length direction inFIG.31AandFIG.31B, the present invention is not limited thereto. The transistor200_1to the transistor200_nmay be arranged in the channel width direction or may be arranged in a matrix. Alternatively, the transistors may be arranged without regularity depending on the design.

As illustrated inFIG.31A, the opening region400is provided between the adjacent transistors200. By performing heat treatment after the formation of the opening region400in the manufacturing process of the semiconductor device, oxygen contained in the insulator280and hydrogen bonded to the oxygen can be released to the outside through the opening region400. The hydrogen bonded to oxygen is released as water. Thus, unnecessary oxygen and hydrogen contained in the insulator280can be reduced. A portion where the insulator283is in contact with the insulator212(hereinafter referred to as the sealing portion265in some cases) is formed outside the plurality of transistors200_1to200_n. The sealing portion265is formed to surround the plurality of transistors200_1to200_n. Such a structure enables the plurality of transistors200_1to200_nto be surrounded by the insulator283and the insulator212. Thus, a plurality of transistor groups surrounded by the sealing portion265are provided over a substrate.

A dicing line (sometimes referred to as a scribe line, a dividing line, or a cutting line) may be provided to overlap the sealing portion265. The above substrate is divided at the dicing line, so that the transistor group surrounded by the sealing portion265is taken out as one chip.

Although the plurality of transistors200_1to200_nare surrounded by one sealing portion265in the example illustrated inFIG.31A, the present invention is not limited thereto. As illustrated inFIG.31B, the plurality of transistors200_1to200_nmay be surrounded by a plurality of sealing portions. InFIG.31B, the plurality of transistors200_1to200_nare surrounded by a sealing portion265aand are further surrounded by an outer sealing portion265b.

When the plurality of transistors200_1to200_nare surrounded by the plurality of sealing portions in this manner, a portion where the insulator283is in contact with the insulator212increases, which further can improve adhesion between the insulator283and the insulator212. As a result, the plurality of transistors200_1to200_ncan be more reliably sealed.

In this case, a dicing line may be provided so as to overlap the sealing portion265aor the sealing portion265b, or may be provided between the sealing portion265aand the sealing portion265b.

According to one embodiment of the present invention, a semiconductor with small variations in transistor characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with favorable reliability can be provided. According to another embodiment of the present invention, a semiconductor device having favorable electrical characteristics can be provided. According to another embodiment of the present invention, a semiconductor device with a high on-state current can be provided. According to another embodiment of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to another embodiment of the present invention, a semiconductor device with low power consumption can be provided.

The structure, method, and the like described in this embodiment can be used in an appropriate combination with other structures, methods, and the like described in this embodiment, the other embodiments, or Example.

In this embodiment, embodiments of semiconductor devices are described with reference toFIG.32toFIG.37.

FIG.32illustrates an example of a semiconductor device (a storage device) of one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, the transistor200is provided above a transistor300, and a capacitor100is provided above the transistor300and the transistor200. The transistor200described in the above embodiment can be used as the transistor200.

The transistor200is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the transistor200has a low off-state current, a storage device that uses the transistor200can retain stored data for a long time. In other words, such a storage device does not require refresh operation or has extremely low frequency of the refresh operation, which leads to a sufficient reduction in power consumption of the storage device.

In the semiconductor device illustrated inFIG.32, a wiring1001is electrically connected to a source of the transistor300, and a wiring1002is electrically connected to a drain of the transistor300. In addition, a wiring1003is electrically connected to one of the source and the drain of the transistor200, a wiring1004is electrically connected to the first gate of the transistor200, and a wiring1006is electrically connected to the second gate of the transistor200. A gate of the transistor300and the other of the source and the drain of the transistor200are electrically connected to one electrode of the capacitor100, and a wiring1005is electrically connected to the other electrode of the capacitor100.

The storage devices illustrated inFIG.32can form a memory cell array when arranged in a matrix.

The transistor300is provided on a substrate311and includes a conductor316functioning as a gate, an insulator315functioning as a gate insulator, a semiconductor region313formed of part of the substrate311, and a low-resistance region314aand a low-resistance region314bfunctioning as a source region and a drain region. The transistor300may be a p-channel transistor or an n-channel transistor.

Here, in the transistor300illustrated inFIG.32, the semiconductor region313(part of the substrate311) where a channel is formed has a protruding shape. In addition, the conductor316is provided so as to cover a side surface and the top surface of the semiconductor region313with the insulator315therebetween. Note that a material adjusting the work function may be used for the conductor316. Such a transistor300is also referred to as a FIN-type transistor because it utilizes a protruding portion of a semiconductor substrate. Note that an insulator functioning as a mask for forming the protruding portion may be included in contact with an upper portion of the protruding portion. Furthermore, although the case where the protruding portion is formed by processing part of the semiconductor substrate is described here, a semiconductor film having a protruding shape may be formed by processing an SOI substrate.

Note that the transistor300illustrated inFIG.32is an example and the structure is not limited thereto; an appropriate transistor is used in accordance with a circuit structure or a driving method.

The capacitor100is provided above the transistor200. The capacitor100includes a conductor110functioning as a first electrode, a conductor120functioning as a second electrode, and an insulator130functioning as a dielectric. Here, for the insulator130, the insulator that can be used as the insulator286described in the above embodiment is preferably used.

For example, a conductor112provided over the conductor246and the conductor110can be formed at the same time. Note that the conductor112has a function of a plug or a wiring that is electrically connected to the capacitor100, the transistor200, or the transistor300.

Although the conductor112and the conductor110having a single-layer structure are illustrated inFIG.32, the structure is not limited thereto; a stacked-layer structure of two or more layers may be employed. For example, between a conductor having a barrier property and a conductor having high conductivity, a conductor that is highly adhesive to the conductor having a barrier property and the conductor having high conductivity may be formed.

For example, for the insulator130, a stacked-layer structure of a material with high dielectric strength such as silicon oxynitride and a high dielectric constant (high-k) material is preferably used. In the capacitor100having such a structure, a sufficient capacitance can be ensured owing to the high dielectric constant (high-k) insulator, and the dielectric strength can be increased owing to the insulator with high dielectric strength, so that the electrostatic breakdown of the capacitor100can be inhibited.

Examples of the insulator of a high dielectric constant (high-k) material (a material having a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium.

Examples of a material with high dielectric strength (a material having a low relative dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, and a resin.

Wiring layers provided with an interlayer film, a wiring, a plug, and the like may be provided between the structure bodies. A plurality of wiring layers can be provided in accordance with design. Here, a plurality of conductors functioning as plugs or wirings are collectively denoted by the same reference numeral in some cases. Furthermore, in this specification and the like, a wiring and a plug electrically connected to the wiring may be a single component. That is, there are cases where part of a conductor functions as a wiring and part of a conductor functions as a plug.

For example, an insulator320, an insulator322, an insulator324, and an insulator326are sequentially stacked over the transistor300as interlayer films. A conductor328, a conductor330, and the like that are electrically connected to the capacitor100or the transistor200are embedded in the insulator320, the insulator322, the insulator324, and the insulator326. Note that the conductor328and the conductor330function as a plug or a wiring.

The insulators functioning as interlayer films may also function as planarization films that cover uneven shapes therebelow. For example, the top surface of the insulator322may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve planarity.

A wiring layer may be provided over the insulator326and the conductor330. For example, inFIG.32, an insulator350, an insulator352, and an insulator354are stacked sequentially. Furthermore, a conductor356is formed in the insulator350, the insulator352, and the insulator354. The conductor356functions as a plug or a wiring.

Similarly, a conductor218, a conductor (the conductor205) included in the transistor200, and the like are embedded in an insulator210, the insulator212, the insulator214, and the insulator216. Note that the conductor218has a function of a plug or a wiring that is electrically connected to the capacitor100or the transistor300. In addition, an insulator150is provided over the conductor120and the insulator130.

Here, like the insulator241described in the above embodiment, an insulator217is provided in contact with a side surface of the conductor218functioning as a plug. The insulator217is provided in contact with an inner wall of an opening formed in the insulator210, the insulator212, the insulator214, and the insulator216. That is, the insulator217is provided between the conductor218and each of the insulator210, the insulator212, the insulator214, and the insulator216. Note that the conductor205and the conductor218can be formed in parallel; thus, the insulator217is sometimes formed in contact with the side surface of the conductor205.

As the insulator217, an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide may be used, for example. Since the insulator217is provided in contact with the insulator210, the insulator212, the insulator214, and the insulator222, entry of impurities such as water and hydrogen into the oxide230through the conductor218from the insulator210, the insulator216, or the like can be inhibited. In particular, silicon nitride is suitable because of its high blocking property against hydrogen. Moreover, oxygen contained in the insulator210or the insulator216can be prevented from being absorbed by the conductor218.

The insulator217can be formed in a manner similar to that of the insulator241. For example, silicon nitride is deposited by a PEALD method and an opening reaching the conductor356is formed by anisotropic etching.

Examples of an insulator that can be used as an interlayer film include an insulating oxide, an insulating nitride, an insulating oxynitride, an insulating nitride oxide, an insulating metal oxide, an insulating metal oxynitride, and an insulating metal nitride oxide.

For example, when a material having a low relative dielectric constant is used for the insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Thus, a material is preferably selected depending on the function of an insulator.

For example, as the insulator150, the insulator210, the insulator352, the insulator354, and the like, an insulator having a low relative dielectric constant is preferably included. For example, the insulator preferably includes silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, a resin, or the like. Alternatively, the insulator preferably has a stacked-layer structure of a resin and silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or porous silicon oxide. When silicon oxide or silicon oxynitride, which is thermally stable, is combined with a resin, the stacked-layer structure can have thermal stability and a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon and aramid), polyimide, polycarbonate, and acrylic.

When a transistor using an oxide semiconductor is surrounded by an insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, the electrical characteristics of the transistor can be stable. Thus, the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen can be used for the insulator214, the insulator212, the insulator350, and the like.

As the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, a single layer or stacked layers of an insulator containing, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum are used. Specifically, as the insulator having a function of inhibiting passage of oxygen and impurities such as hydrogen, a metal oxide such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or tantalum oxide; silicon nitride oxide; silicon nitride: or the like can be used.

As the conductor that can be used for a wiring or a plug, a material containing one or more kinds of metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, and the like can be used. Alternatively, a semiconductor having high electrical conductivity, typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used.

For example, for the conductor328, the conductor330, the conductor356, the conductor218, the conductor112, and the like, a single layer or stacked layers of a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material that is formed using the above materials can be used. It is preferable to use a high-melting-point material that has both heat resistance and conductivity, such as tungsten or molybdenum, and it is preferable to use tungsten. Alternatively, it is preferable to form the plugs and wirings with a low-resistance conductive material such as aluminum or copper. The use of a low-resistance conductive material can reduce wiring resistance.

<Wiring or Plug in Layer Provided with Oxide Semiconductor>

In the case where an oxide semiconductor is used in the transistor200, an insulator including an excess-oxygen region is provided in the vicinity of the oxide semiconductor in some cases. In that case, an insulator having a barrier property is preferably provided between the insulator including the excess-oxygen region and a conductor provided in the insulator including the excess-oxygen region.

For example, inFIG.32, the insulator241is preferably provided between the conductor240and each of the insulator224and the insulator280including excess oxygen. Since the insulator241is provided in contact with the insulator222, the insulator282, and the insulator283, the insulator224and the transistor200can be sealed with the insulators having a barrier property.

That is, when the insulator241is provided, excess oxygen contained in the insulator224and the insulator280can be inhibited from being absorbed by the conductor240. In addition, providing the insulator241can inhibit diffusion of hydrogen, which is an impurity, into the transistor200through the conductor240.

For the insulator241, an insulating material having a function of inhibiting diffusion of oxygen and impurities such as water and hydrogen is preferably used. For example, silicon nitride, silicon nitride oxide, aluminum oxide, hafnium oxide, or the like is preferably used. In particular, silicon nitride is preferable because of its high blocking property against hydrogen. Other than that, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide can be used, for example.

As described in the above embodiment, the transistor200may be sealed with the insulator212, the insulator214, the insulator282, and the insulator283. Such a structure can inhibit entry of hydrogen contained in the insulator274, the insulator150, or the like into the insulator280or the like.

Here, the conductor240penetrates the insulator283and the insulator282, and the conductor218penetrates the insulator214and the insulator212; however, as described above, the insulator241is provided in contact with the conductor240, and the insulator217is provided in contact with the conductor218. This can reduce the amount of hydrogen entering the inside of the insulator212, the insulator214, the insulator282, and the insulator283through the conductor240and the conductor218. In this manner, the transistor200is sealed with the insulator212, the insulator214, the insulator282, the insulator283, the insulator241, and the insulator217, so that impurities such as hydrogen contained in the insulator274or the like can be inhibited from entering from the outside.

A dicing line (sometimes referred to as a scribe line, a dividing line, or a cutting line) which is provided when a large-sized substrate is divided into semiconductor elements so that a plurality of semiconductor devices are each formed in a chip form is described below. Examples of a dividing method include the case where a groove (a dicing line) for separating the semiconductor elements is formed on the substrate, and then the substrate is cut along the dicing line to divide (split) it into a plurality of semiconductor devices.

Here, for example, as illustrated inFIG.32, a region in which the insulator283and the insulator212are in contact with each other is preferably designed so as to overlap the dicing line. That is, an opening is provided in the insulator282, the insulator280, the insulator272, the insulator224, the insulator222, the insulator216, and the insulator214in the vicinity of a region to be the dicing line that is provided on an outer edge of the memory cell including the plurality of transistors200.

That is, in the opening provided in the insulator282, the insulator280, the insulator272, the insulator224, the insulator222, the insulator216, and the insulator214, the insulator212is in contact with the insulator283. For example, the insulator212and the insulator283may be formed using the same material and the same method. When the insulator212and the insulator283are formed using the same material and the same method, the adhesion therebetween can be increased. For example, silicon nitride is preferably used.

With the structure, the transistors200can be surrounded by the insulator212, the insulator214, the insulator282, and the insulator283. Since at least one of the insulator212, the insulator214, the insulator282, and the insulator283has a function of inhibiting diffusion of oxygen, hydrogen, and water, even when the substrate is divided into circuit regions each of which is provided with the semiconductor elements described in this embodiment to be processed into a plurality of chips, entry and diffusion of impurities such as hydrogen and water from the direction of the side surface of the divided substrate into the transistor200can be prevented.

With the structure, excess oxygen in the insulator280and the insulator224can be prevented from diffusing to the outside. Accordingly, excess oxygen in the insulator280and the insulator224is efficiently supplied to the oxide where the channel is formed in the transistor200. The oxygen can reduce oxygen vacancies in the oxide where the channel is formed in the transistor200. Thus, the oxide where the channel is formed in the transistor200can be an oxide semiconductor with a low density of defect states and stable characteristics. That is, the transistor200can have small variations in the electrical characteristics and higher reliability.

Note that although the capacitor100of the storage device illustrated inFIG.32has a planar shape, the storage device described in this embodiment is not limited thereto. For example, the capacitor100may have a cylindrical shape as illustrated inFIG.33. Note that the structure below and including the insulator150of a storage device illustrated inFIG.33is similar to that of the semiconductor device illustrated inFIG.32.

The capacitor100illustrated inFIG.33includes the insulator150over the insulator130, an insulator142over the insulator150, a conductor115placed in an opening formed in the insulator150and the insulator142, an insulator145over the conductor115and the insulator142, a conductor125over the insulator145, and an insulator152over the conductor125and the insulator145. Here, at least parts of the conductor115, the insulator145, and the conductor125are placed in the opening formed in the insulator150and the insulator142.

The conductor115functions as a lower electrode of the capacitor100, the conductor125functions as an upper electrode of the capacitor100, and the insulator145functions as a dielectric of the capacitor100. The capacitor100has a structure in which the upper electrode and the lower electrode face each other with the dielectric sandwiched therebetween on a side surface as well as the bottom surface of the opening in the insulator150and the insulator142; thus, the capacitance per unit area can be increased. Thus, the deeper the opening is, the larger the capacitance of the capacitor100can be. Increasing the capacitance per unit area of the capacitor100in this manner can promote miniaturization or higher integration of the semiconductor device.

An insulator that can be used as the insulator280can be used as the insulator152. The insulator142preferably functions as an etching stopper at the time of forming the opening in the insulator150, and an insulator that can be used as the insulator214is used.

The shape of the opening formed in the insulator150and the insulator142when seen from above may be a quadrangular shape, a polygonal shape other than a quadrangular shape, a polygonal shape with rounded corners, or a circular shape including an elliptical shape. Here, the area where the opening and the transistor200overlap each other is preferably large in the top view. Such a structure can reduce the area occupied by the semiconductor device including the capacitor100and the transistor200.

The conductor115is placed in contact with the opening formed in the insulator142and the insulator150. The top surface of the conductor115is preferably substantially level with the top surface of the insulator142. Furthermore, the bottom surface of the conductor115is in contact with the conductor110through an opening in the insulator130. The conductor115is preferably formed by an ALD method, a CVD method, or the like; for example, a conductor that can be used for the conductor205is used.

The insulator145is placed so as to cover the conductor115and the insulator142. The insulator145is preferably formed by an ALD method or a CVD method, for example. The insulator145can be provided to have stacked layers or a single layer using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride. As the insulator145, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used, for example.

For the insulator145, a material with high dielectric strength, such as silicon oxynitride, or a high dielectric constant (high-k) material is preferably used. Alternatively, a stacked-layer structure of a material with high dielectric strength and a high dielectric constant (high-k) material may be used.

Examples of an insulator of a high dielectric constant (high-k) material (a material having a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium. The use of such a high-k material can ensure sufficient capacitance of the capacitor100even when the insulator145has a large thickness. When the insulator145has a large thickness, generation of a leakage current between the conductor115and the conductor125can be inhibited.

Examples of a material with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, porous silicon oxide, and a resin. For example, it is possible to use an insulating film in which silicon nitride (SiNx) deposited by an ALD method, silicon oxide (SiOx) deposited by a PEALD method, and silicon nitride (SiNx) deposited by an ALD method are stacked in this order. Alternatively, an insulating film in which zirconium oxide, silicon oxide deposited by an ALD method, and zirconium oxide are stacked in this order can be used. The use of such an insulator with high dielectric strength can increase the dielectric strength and inhibit electrostatic breakdown of the capacitor100.

The conductor125is placed so as to fill the opening formed in the insulator142and the insulator150. The conductor125is electrically connected to the wiring1005through a conductor140and a conductor153. The conductor125is preferably formed by an ALD method, a CVD method, or the like, and a conductor that can be used as the conductor205is used, for example.

The conductor153is provided over an insulator154and is covered with an insulator156. As the conductor153, a conductor that can be used as the conductor112is used, and as the insulator156, an insulator that can be used as the insulator152is used. Here, the conductor153is in contact with the top surface of the conductor140and functions as a terminal of the capacitor100, the transistor200, or the transistor300.

FIG.34AandFIG.34Beach illustrate an example of a semiconductor device (a storage device) of one embodiment of the present invention.

<Structure Example 1 of Memory Device>

FIG.34Ais a cross-sectional view of a semiconductor device including a memory device290. The memory device290illustrated inFIG.34Aincludes a capacitor device292besides the transistor200illustrated inFIG.4AtoFIG.4D.FIG.34Acorresponds to a cross-sectional view of the transistor200in the channel length direction.

The capacitor device292includes the conductor242b: the insulator271bprovided over the conductor242b; the insulator272provided in contact with the top surface of the insulator271b, a side surface of the insulator271b, and a side surface of the conductor242b; and a conductor294over the insulator272. In other words, the capacitor device292forms a MIM (Metal-Insulator-Metal) capacitor. Note that one of a pair of electrodes included in the capacitor device292, i.e., the conductor242b, can also serve as the source electrode of the transistor. The dielectric layer included in the capacitor device292can also serve as a protective layer provided in the transistor, i.e., the insulator271and the insulator272. Thus, the manufacturing process of the capacitor device292can also serve as part of the manufacturing process of the transistor, improving the productivity of the semiconductor device. Furthermore, one of a pair of electrodes included in the capacitor device292, that is, the conductor242b, also serves as the source electrode of the transistor; therefore, the area in which the transistor and the capacitor device are placed can be reduced.

For the conductor294, a material that can be used for the conductor242is used, for example.

<Structure Example 2 of Memory Device>

FIG.34Bis a cross-sectional view of a semiconductor device including the memory device290, which has a structure different from that illustrated inFIG.34A. The memory device290illustrated inFIG.34Bincludes the capacitor device292besides the transistor200illustrated inFIG.4AtoFIG.4D. Here, part of the capacitor device292illustrated inFIG.34Bis provided in an opening formed in the insulator280, the insulator272, and the insulator271bunlike in the case of the capacitor device292illustrated inFIG.34A.FIG.34Bcorresponds to a cross-sectional view of the transistor200in the channel length direction.

The capacitor device292includes the conductor242b, an insulator293provided over the conductor242b, and the conductor294provided over the insulator293. Here, the insulator293and the conductor294are placed in the opening formed in the insulator280, the insulator272, and the insulator271b. The insulator293is provided in contact with the bottom surface and a sidewall of the opening. That is, the insulator293is in contact with the top surface of the conductor242b, a side surface of the insulator271b, a side surface of the insulator272, and a side surface of the insulator280. The insulator293is provided so as to form a depressed portion along the shape of the opening. The conductor294is placed in contact with the top surface and a side surface of the insulator293so as to fill the depressed portion. Note that the top-surface levels of the insulator293and the conductor294are substantially the same as the top-surface levels of the insulator280, the insulator250, and the conductor260in some cases.

Here, the conductor242bfunctions as a lower electrode of the capacitor device292, the conductor294functions as an upper electrode of the capacitor device292, and the insulator293functions as a dielectric of the capacitor device292. Thus, the capacitor device292forms an MIM capacitor. Note that one of a pair of electrodes included in the capacitor device292, i.e., the conductor242b, can also serve as the source electrode of the transistor. Thus, the manufacturing process of the capacitor device292can also serve as part of the manufacturing process of the transistor, improving the productivity of the semiconductor device. Since the insulator293can be provided independently of the structure of the transistor200, a structure and a material of the insulator293can be selected as appropriate in accordance with performance required for the capacitor device292. Furthermore, one of a pair of electrodes included in the capacitor device292, i.e., the conductor242b, also serves as the source electrode of the transistor; therefore, the area in which the transistor and the capacitor device are placed can be reduced.

A high dielectric constant (high-k) material is preferably used for the insulator293. Examples of an insulator of a high dielectric constant (high-k) material (a material having a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, and a nitride containing silicon and hafnium. Stack of these high dielectric constant materials may be used as the insulator293. As the insulator293, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order can be used, for example.

For the conductor294, a material that can be used for the conductor260can be used, for example. The conductor294may have a stacked-layer structure like the conductor260.

The insulator293and the conductor294may be formed before the formation of the insulator282, that is, before the step illustrated inFIG.20. The insulator293and the conductor294can be formed by a method similar to that for forming the insulator250and the conductor260. That is, the insulator293and the conductor294may be formed in such a manner that an opening is formed in the insulator280, the insulator272, and the insulator271b, a stacked film to be the insulator293and the conductor294is formed so as to be embedded in the opening, and the stacked film is partly removed by CMP treatment.

<Modification Example of Memory Device>

Examples of semiconductor devices of embodiments of the present invention including the transistor200, the opening region400, and the capacitor device292, which are different from the one described above in <Structure example 1 of memory device>, are described below with reference toFIG.35A,FIG.35B,FIG.36, andFIG.37. Note that in the semiconductor devices illustrated inFIG.35A,FIG.35B,FIG.36, andFIG.37, structures having the same function as those included in the semiconductor devices described in the above embodiment and <Structure example 1 of memory device> (seeFIG.34A) are denoted by the same reference numerals. Note that the materials described in detail in the above embodiment and <Structure example 1 of memory device> can be used as constituent materials of the transistor200, the opening region400, and the capacitor device292in this section. The memory devices inFIG.35A,FIG.35B,FIG.36,FIG.37, and the like are the memory device illustrated inFIG.34A, but not limited to this. For example, the memory device illustrated inFIG.34Bor the like may be used.

<<Modification Example 1 of Memory Device>>

An example of a semiconductor device600of one embodiment of the present invention including a transistor200a, a transistor200b, a capacitor device292a, and a capacitor device292bis described below with reference toFIG.35A.

FIG.35Ais a cross-sectional view of the semiconductor device600including the transistor200a, the transistor200b, the capacitor device292a, and the capacitor device292bin the channel length direction. Here, the capacitor device292aincludes the conductor242a; the insulator271aover the conductor242a; the insulator272in contact with the top surface of the insulator271a, a side surface of the insulator271a, and a side surface of the conductor242a: and a conductor294aover the insulator272. The capacitor device292bincludes the conductor242b; the insulator271bover the conductor242b; the insulator272in contact with the top surface of the insulator271b, a side surface of the insulator271b, and a side surface of the conductor242b; and a conductor294bover the insulator272.

The semiconductor device600has a line-symmetric structure with respect to dashed-dotted line A3-A4as illustrated inFIG.35A. A conductor242cserves as one of a source electrode and a drain electrode of the transistor200aand one of a source electrode and a drain electrode of the transistor200b. An insulator271cis provided over the conductor242c. The conductor240functioning as a plug connects the conductor246functioning as a wiring to the transistor200aand the transistor200b. With the above connection structure between the two transistors, the two capacitor devices, the wiring, and the plug, a semiconductor device that can be miniaturized or highly integrated can be provided.

The structure examples of the semiconductor device illustrated inFIG.34Acan be referred to for the structures and the effects of the transistor200a, the transistor200b, the capacitor device292a, and the capacitor device292b.

<<Modification Example 2 of Memory Device>>

In the above description, the semiconductor device including the transistor200a, the transistor200b, the capacitor device292a, and the capacitor device292bis given as a structure example; however, the semiconductor device described in this embodiment is not limited thereto. For example, as illustrated inFIG.35B, a structure may be employed in which the semiconductor device600and a semiconductor device having a structure similar to that of the semiconductor device600are connected through a capacitor portion. Furthermore, a structure may be employed in which the opening region400is positioned between the adjacent semiconductor devices600and between the semiconductor device600and a semiconductor device having a structure similar to that of the semiconductor device600. In this specification, the semiconductor device including the transistor200a, the transistor200b, the capacitor device292a, and the capacitor device292bis referred to as a cell. For the structures of the transistor200a, the transistor200b, the capacitor device292a, and the capacitor device292b, the above description of the transistor200a, the transistor200b, the capacitor device292a, and the capacitor device292bcan be referred to.

FIG.35Bis a cross-sectional view in which the semiconductor device600including the transistor200a, the transistor200b, the capacitor device292a, and the capacitor device292b, and a cell having a structure similar to that of the semiconductor device600are connected through a capacitor portion.

As illustrated inFIG.35B, the conductor294bfunctioning as one electrode of the capacitor device292bincluded in the semiconductor device600also serves as one electrode of a capacitor device included in a semiconductor device601having a structure similar to that of the semiconductor device600. Although not illustrated, the conductor294afunctioning as one electrode of the capacitor device292aincluded in the semiconductor device600also serves as one electrode of a capacitor device included in a semiconductor device on the left side of the semiconductor device600, that is, a semiconductor device adjacent to the semiconductor device600in the A1direction inFIG.35B. The cell on the right side of the semiconductor device601, that is, the cell in the A2direction inFIG.35B, has a similar structure. That is, a cell array (also referred to as a memory device layer) can be formed. With such a structure of the cell array, space between adjacent cells can be reduced, thus, the projected area of the cell array can be reduced and high integration can be achieved. When the cells illustrated inFIG.35Bare arranged in a matrix, a matrix-shape cell array can be formed.

When the transistor200a, the transistor200b, the capacitor device292a, and the capacitor device292bare formed to have the structures described in this embodiment as described above, the area of the cell can be reduced and the semiconductor device including a cell array can be miniaturized or highly integrated.

Furthermore, stacked cell arrays may be used instead of the single-layer cell array.FIG.36illustrates a cross-sectional view of n layers of cell arrays610that are stacked. When a plurality of cell arrays (a cell array610_1to a cell array610_n) are stacked as illustrated inFIG.36, cells can be integrally placed without increasing the area occupied by the cell arrays. In other words, a 3D cell array can be formed.

<Modification Example 3 of Memory Device>

FIG.37illustrates an example in which a memory unit470includes a transistor layer413including a transistor200T and four memory device layers415(a memory device layer415_1to a memory device layer415_4).

The memory device layer415_1to the memory device layer415_4each include a plurality of memory devices420.

The memory device420is electrically connected to the memory device420included in a different memory device layer415and the transistor200T included in the transistor layer413through a conductor424and the conductor205.

The memory unit470is sealed with the insulator212, the insulator214, the insulator282, and the insulator283(such a structure is referred to as a sealing structure below for convenience). The insulator274is provided in the periphery of the insulator283. A conductor440is provided in the insulator274, the insulator283, and the insulator212, and is electrically connected to an element layer411.

The insulator280is provided in the sealing structure. The insulator280has a function of releasing oxygen by heating. Alternatively, the insulator280includes an excess-oxygen region.

A material having a high blocking property against hydrogen is suitable for the insulator212and the insulator283. A material having a function of capturing hydrogen or fixing hydrogen is suitable for the insulator214and the insulator282.

Examples of the material having a high blocking property against hydrogen include silicon nitride and silicon nitride oxide. Examples of the material having a function of capturing hydrogen or fixing hydrogen include aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate).

The crystal structure of materials used for the insulator212, the insulator214, the insulator282, and the insulator283is not particularly limited, and an amorphous or crystalline structure may be employed. For example, it is suitable to use an amorphous aluminum oxide film as the material having a function of capturing hydrogen or fixing hydrogen. Amorphous aluminum oxide sometimes captures or fixes hydrogen more than aluminum oxide with high crystallinity does.

Here, as the model of excess oxygen in the insulator280with respect to the diffusion of hydrogen from an oxide semiconductor in contact with the insulator280, the following model can be given.

Hydrogen in the oxide semiconductor diffuses into other structure bodies through the insulator280in contact with the oxide semiconductor. The hydrogen in the oxide semiconductor reacts with the excess oxygen in the insulator280, which yields the OH bonding to diffuse in the insulator280. The hydrogen atom having the OH bonding reacts with the oxygen atom bonded to an atom (such as a metal atom) in the insulator282in reaching a material that has a function of capturing or fixing hydrogen (typically the insulator282), and is captured or fixed in the insulator282. The oxygen atom which had the OH bonding of the excess oxygen may remain as excess oxygen in the insulator280. That is, it is highly probable that the excess oxygen in the insulator280serves as a bridge in the diffusion of the hydrogen.

A manufacturing process of the semiconductor device is one of important factors for the model.

For example, the insulator280containing excess oxygen is formed over the oxide semiconductor, and then the insulator282is formed. After that, the opening region40(not illustrated) is formed, and then, heat treatment is preferably performed. Specifically, the heat treatment is performed at higher than or equal to 350° C., preferably higher than or equal to 400° C. in a nitrogen-containing atmosphere.

Through the heat treatment, oxygen contained in the insulator280and hydrogen bonded to the oxygen can be released to the outside through the opening region400. The hydrogen bonded to oxygen is released as water. Thus, unnecessary oxygen and hydrogen contained in the insulator280can be reduced.

The insulator283is formed after the heat treatment. The insulator283is a material having a function of a high blocking property against hydrogen, and thus can inhibit entry of hydrogen that has diffused outward or external hydrogen into the inside, specifically, to the oxide semiconductor side or the insulator280side.

For example, the heat treatment may be performed after the transistor layer413is formed or after the memory device layer415_1to the memory device layer415_3are formed. Specifically, the heat treatment is performed at higher than or equal to 350° C., preferably higher than or equal to 400° C. in a nitrogen-containing atmosphere or a mixed atmosphere of oxygen and nitrogen. The heat treatment is performed for one hour or more, preferably four hours or more, further preferably eight hours or more. The heat treatment enables outward diffusion of hydrogen in the oxide of the channel formation region through the insulator280and the insulator282. In other words, the absolute amount of hydrature existing in the oxide of the channel formation region and in the vicinity thereof can be reduced. When the heat treatment diffuses hydrogen outward, hydrogen diffuses to above the transistor layer413or in the lateral direction. Similarly, in the case where heat treatment is performed after the memory device layer415_1to the memory device layer415_3are formed, hydrogen diffuses upward or in the lateral direction.

Through the above manufacturing process, the insulator212and the insulator283are bonded, whereby the above-described sealing structure is formed.

With the above structure and the above manufacturing process, a semiconductor device using an oxide semiconductor with reduced hydrogen concentration can be provided. Accordingly, a semiconductor device with high reliability can be provided. One embodiment of the present invention can provide a semiconductor device with favorable electrical characteristics.

The structure, method, and the like described in this embodiment can be used in an appropriate combination with other structures, methods, and the like described in this embodiment, the other embodiments, or Example.

In this embodiment, a storage device including a transistor in which an oxide is used as a semiconductor (hereinafter, sometimes referred to as an OS transistor) and a capacitor (hereinafter, sometimes referred to as an OS memory device) of one embodiment of the present invention is described with reference toFIG.38A,FIG.38B, andFIG.39AtoFIG.39H. The OS memory device is a storage device that includes at least a capacitor and an OS transistor that controls the charging and discharging of the capacitor. Since the OS transistor has an extremely low off-state current, the OS memory device has excellent retention characteristics and thus can function as a nonvolatile memory.

<Structure Example of Storage Device>

FIG.38Aillustrates a structure example of the OS memory device. A storage device1400includes a peripheral circuit1411and a memory cell array1470. The peripheral circuit1411includes a row circuit1420, a column circuit1430, an output circuit1440, and a control logic circuit1460.

The column circuit1430includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging wirings. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the wirings are connected to memory cells included in the memory cell array1470, and are described later in detail. The amplified data signal is output as a data signal RDATA to the outside of the storage device1400through the output circuit1440. The row circuit1420includes, for example, a row decoder and a word line driver circuit, and can select a row to be accessed.

As power supply voltages from the outside, a low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit1411, and a high power supply voltage (VIL) for the memory cell array1470are supplied to the storage device1400. Control signals (CE, WE, and RE), an address signal ADDR, and a data signal WDATA are also input to the storage device1400from the outside. The address signal ADDR is input to the row decoder and the column decoder, and the data signal WDATA is input to the write circuit.

The control logic circuit1460processes the control signals (CE, WE, and RE) input from the outside, and generates control signals for the row decoder and the column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal RE is a read enable signal. Signals processed by the control logic circuit1460are not limited thereto, and other control signals are input as necessary.

The memory cell array1470includes a plurality of memory cells MC arranged in a matrix and a plurality of wirings. Note that the number of wirings that connect the memory cell array1470to the row circuit1420depends on the structure of the memory cell MC, the number of memory cells MC in a column, and the like. The number of wirings that connect the memory cell array1470to the column circuit1430depends on the structure of the memory cell MC, the number of memory cells MC in a row, and the like.

Note thatFIG.38Aillustrates an example in which the peripheral circuit1411and the memory cell array1470are formed on the same plane; however, this embodiment is not limited thereto. For example, as illustrated inFIG.38B, the memory cell array1470may be provided over the peripheral circuit1411so as to partly overlap the peripheral circuit1411. For example, the sense amplifier may be provided below the memory cell array1470so that they overlap each other.

FIG.39AtoFIG.39Hillustrate structure examples of a memory cell that can be used as the memory cell MC.

FIG.39AtoFIG.39Cillustrate circuit structure examples of a memory cell of a DRAM. In this specification and the like, a DRAM using a memory cell including one OS transistor and one capacitor is referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory) in some cases. A memory cell1471illustrated inFIG.39Aincludes a transistor M1and a capacitor CA. Note that the transistor M1includes a gate (sometimes referred to as a top gate) and a back gate.

A first terminal of the transistor M1is connected to a first terminal of the capacitor CA. A second terminal of the transistor M1is connected to a wiring BIL. The gate of the transistor M1is connected to a wiring WOL. The back gate of the transistor M1is connected to a wiring BGL. A second terminal of the capacitor CA is connected to a wiring LL.

The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring LL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. In the time of data writing and data reading, the wiring LL may be at a ground potential or a low-level potential. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. When a given potential is applied to the wiring BGL, the threshold voltage of the transistor M1can be increased or decreased.

Here, a memory cell1471illustrated inFIG.39Acorresponds to the storage device illustrated inFIG.34AandFIG.34B. That is, the transistor M1and the capacitor CA correspond to the transistor200and the capacitor device292, respectively.

The circuit structure of the memory cell MC is not limited to that of the memory cell1471, and the circuit structure can be changed. For example, as in a memory cell1472illustrated inFIG.39B, the back gate of the transistor M1may be connected not to the wiring BGL but to the wiring WOL in the memory cell MC. Alternatively, for example, the transistor M1may be a single-gate transistor, that is, a transistor without a back gate in the memory cell MC as in a memory cell1473illustrated inFIG.39C.

In the case w % here the semiconductor device described in any of the above embodiments is used in the memory cell1471and the like, the transistor200can be used as the transistor M1, and the capacitor100can be used as the capacitor CA. When an OS transistor is used as the transistor M1, the leakage current of the transistor M1can be extremely low. That is, with the use of the transistor M1, written data can be retained for a long time, and thus the frequency of the refresh operation for the memory cell can be decreased. Alternatively, refresh operation for the memory cell can be omitted. In addition, since the transistor M1has an extremely low leakage current, multi-level data or analog data can be retained in the memory cell1471, the memory cell1472, and the memory cell1473.

In the DOSRAM, when the sense amplifier is provided below the memory cell array1470so that they overlap each other as described above, the bit line can be shortened. This reduces bit line capacitance, which can reduce the storage capacitance of the memory cell.

FIG.39DtoFIG.39Geach illustrate a circuit structure example of a gain-cell memory cell including two transistors and one capacitor. A memory cell1474illustrated inFIG.39Dincludes a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2includes a top gate (simply referred to as a gate in some cases) and a back gate. In this specification and the like, a storage device including a gain-cell memory cell using an OS transistor as the transistor M2is referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM) in some cases.

A first terminal of the transistor M2is connected to a first terminal of the capacitor CB. A second terminal of the transistor M2is connected to a wiring WBL. The gate of the transistor M2is connected to the wiring WOL. The back gate of the transistor M2is connected to the wiring BGL. A second terminal of the capacitor CB is connected to the wiring CAL. A first terminal of the transistor M3is connected to a wiring RBL. A second terminal of the transistor M3is connected to a wiring SL. A gate of the transistor M3is connected to the first terminal of the capacitor CB.

The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. In the time of data writing and data reading, a high-level potential is preferably applied to the wiring CAL. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. The threshold voltage of the transistor M2can be increased or decreased by applying a given potential to the wiring BGL

Here, the memory cell1474illustrated inFIG.39Dcorresponds to the storage device illustrated inFIG.32andFIG.33. That is, the transistor M2, the capacitor CB, the transistor M3, the wiring WBL, the wiring WOL, the wiring BGL, the wiring CAL, the wiring RBL, and the wiring SL correspond to the transistor200, the capacitor100, the transistor300, the wiring1003, the wiring1004, the wiring1006, the wiring1005, the wiring1002, and the wiring1001, respectively.

The circuit structure of the memory cell MC is not limited to that of the memory cell1474, and the circuit structure can be changed as appropriate. For example, as in a memory cell1475illustrated inFIG.39E, the back gate of the transistor M2may be connected not to the wiring BGL but to the wiring WOL in the memory cell MC. Alternatively, for example, the transistor M2may be a single-gate transistor, that is, a transistor without a back gate in the memory cell MC as in a memory cell1476illustrated inFIG.39F. For example, the memory cell MC may have a structure in which the wiring WBL and the wiring RBL are combined into one wiring BIL as in a memory cell1477illustrated inFIG.39G.

In the case where the semiconductor device described in any of the above embodiments is used in the memory cell1474and the like, the transistor200can be used as the transistor M2, the transistor300can be used as the transistor M3, and the capacitor100can be used as the capacitor CB. When an OS transistor is used as the transistor M2, the leakage current of the transistor M2can be extremely low. Consequently, with the use of the transistor M2, written data can be retained for a long time, and thus the frequency of the refresh operation for the memory cell can be decreased. Alternatively, refresh operation for the memory cell can be omitted. In addition, since the transistor M2has an extremely low leakage current, multi-level data or analog data can be retained in the memory cell1474. The same applies to the memory cell1475to the memory cell1477.

Note that the transistor M3may be a transistor containing silicon in a channel formation region (hereinafter, sometimes referred to as a Si transistor). The Si transistor may be either an n-channel transistor or a p-channel transistor. A Si transistor has higher field-effect mobility than an OS transistor in some cases. Therefore, a Si transistor may be used as the transistor M3functioning as a reading transistor. Furthermore, the transistor M2can be stacked over the transistor M3when a Si transistor is used as the transistor M3, in which case the area occupied by the memory cell can be reduced, leading to high integration of the storage device.

Alternatively, the transistor M3may be an OS transistor. When an OS transistor is used as each of the transistor M2and the transistor M3, the circuit of the memory cell array1470can be formed using only n-channel transistors.

FIG.39Hillustrates an example of a gain-cell memory cell including three transistors and one capacitor. A memory cell1478illustrated inFIG.39Hincludes a transistor M4to a transistor M6and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell1478is electrically connected to the wiring BIL, a wiring RWL, a wiring WWL, the wiring BGL, and a wiring GNDL. The wiring GNDL is a wiring for supplying a low-level potential. Note that the memory cell1478may be electrically connected to the wiring RBL and the wiring WBL instead of the wiring BIL.

The transistor M4is an OS transistor with a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4may be electrically connected to each other. Alternatively, the transistor M4does not need to include the back gate.

Note that each of the transistor M5and the transistor M6may be an n-channel Si transistor or a p-channel Si transistor. Alternatively, the transistor M4to the transistor M6may be OS transistors. In that case, the circuit of the memory cell array1470can be formed using only n-channel transistors.

In the case where the semiconductor device described in any of the above embodiments is used in the memory cell1478, the transistor200can be used as the transistor M4, the transistor300can be used as the transistor M5and the transistor M6, and the capacitor100can be used as the capacitor CC. When an OS transistor is used as the transistor M4, the leakage current of the transistor M4can be extremely low.

Note that the structures of the peripheral circuit1411, the memory cell array1470, and the like described in this embodiment are not limited to the above. The arrangement and functions of these circuits and the wirings, circuit components, and the like connected to the circuits can be changed, removed, or added as needed.

In general, a variety of storage devices (memory) are used in semiconductor devices such as a computer in accordance with the intended use. The semiconductor device of one embodiment of the present invention can be suitably used for a memory included as a register in an arithmetic processing device such as a CPU, an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), and a 3D NAND memory.

A memory included as a register in an arithmetic processing device such as a CPU is used for temporary storage of arithmetic operation results, for example, and thus is very frequently accessed by the arithmetic processing device. Accordingly, high operation speed is required rather than storage capacity. The register also has a function of retaining settings of the arithmetic processing device, for example.

An SRAM is used for a cache, for example. The cache has a function of retaining a copy of part of data retained in a main memory. Copying data which is frequently used and retaining the copy of the data in the cache facilitates rapid data access.

A DRAM is used for the main memory, for example. The main memory has a function of retaining a program or data which are read from the storage. The record density of a DRAM is approximately 0.1 to 0.3 Gbit/mm2.

A 3D NAND memory is used for the storage, for example. The storage has a function of retaining data that needs to be stored for a long time and programs used in an arithmetic processing device, for example. Therefore, the storage needs to have a large storage capacity and a high record density rather than operating speed. The record density of a storage device used for the storage is approximately 0.6 to 6.0 Gbit/mm2.

The storage device of one embodiment of the present invention operates fast and can retain data for a long time.

The structure, method, and the like described in this embodiment can be used in an appropriate combination with other structures, methods, and the like described in this embodiment, the other embodiments, or Example.

In this embodiment, an example of a chip1200on which the semiconductor device of the present invention is mounted is described with reference toFIG.40AandFIG.40B. A plurality of circuits (systems) are mounted on the chip1200. A technique for integrating a plurality of circuits (systems) into one chip is referred to as system on chip (SoC) in some cases.

As shown inFIG.40A, the chip1200includes a CPU1211, a GPU1212, one or a plurality of analog arithmetic units1213, one or a plurality of memory controllers1214, one or a plurality of interfaces1215, one or a plurality of network circuits1216, and the like.

A bump (not shown) is provided on the chip1200, and as shown inFIG.40B, the chip1200is connected to a first surface of a printed circuit board (PCB)1201. In addition, a plurality of bumps1202are provided on a rear side of the first surface of the PCB1201, and the PCB1201is connected to a motherboard1203.

Storage devices such as DRAMs1221and a flash memory1222may be provided over the motherboard1203. For example, the DOSRAM described in the above embodiment can be used as the DRAM1221. In addition, for example, the NOSRAM described in the above embodiment can be used as the flash memory1222.

The CPU1211preferably includes a plurality of CPU cores. In addition, the GPU1212preferably includes a plurality of GPU cores. Furthermore, the CPU1211and the GPU1212may each include a memory for temporarily storing data. Alternatively, a common memory for the CPU1211and the GPU1212may be provided in the chip1200. The NOSRAM or the DOSRAM described above can be used as the memory. Moreover, the GPU1212is suitable for parallel computation of a number of data and thus can be used for image processing or product-sum operation. When an image processing circuit or a product-sum operation circuit using an oxide semiconductor of the present invention is provided in the GPU1212, image processing and product-sum operation can be performed with low power consumption.

In addition, since the CPU1211and the GPU1212are provided on the same chip, a wiring between the CPU1211and the GPU1212can be shortened, and the data transfer from the CPU1211to the GPU1212, the data transfer between the memories included in the CPU1211and the GPU1212, and the transfer of arithmetic operation results from the GPU1212to the CPU1211after the arithmetic operation in the GPU1212can be performed at high speed.

The analog arithmetic unit1213includes one or both of an A/D (analog/digital) converter circuit and a D/A (digital/analog) converter circuit. Furthermore, the product-sum operation circuit may be provided in the analog arithmetic unit1213.

The memory controller1214includes a circuit functioning as a controller of the DRAM1221and a circuit functioning as an interface of the flash memory1222.

The interface1215includes an interface circuit for an external connection device such as a display device, a speaker, a microphone, a camera, or a controller. Examples of the controller include a mouse, a keyboard, and a game controller. As such an interface, a USB (Universal Serial Bus), an HDMI (registered trademark) (High-Definition Multimedia Interface), or the like can be used.

The network circuit1216includes a network circuit such as a LAN (Local Area Network). The network circuit1216may further include a circuit for network security.

The circuits (systems) can be formed in the chip1200through the same manufacturing process. Therefore, even when the number of circuits needed for the chip1200increases, there is no need to increase the number of steps in the manufacturing process: thus, the chip1200can be manufactured at low cost.

The motherboard1203provided with the PCB1201on which the chip1200including the GPU1212is mounted, the DRAMs1221, and the flash memory1222can be referred to as a GPU module1204.

The GPU module1204includes the chip1200using SoC technology, and thus can have a small size. In addition, the GPU module1204is excellent in image processing, and thus is suitably used in a portable electronic device such as a smartphone, a tablet terminal, a laptop PC, or a portable (mobile) game machine. Furthermore, the product-sum operation circuit using the GPU1212can perform a method such as a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), an autoencoder, a deep Boltzmann machine (DBM), or a deep belief network (DBN); hence, the chip1200can be used as an AI chip or the GPU module1204can be used as an A1system module.

The structure, method, and the like described in this embodiment can be used in an appropriate combination with other structures, methods, and the like described in this embodiment, the other embodiments, or Example.

In this embodiment, examples of electronic components and electronic devices in which the storage device or the like described in the above embodiment is incorporated are described.

First,FIG.41AandFIG.41Bshow examples of an electronic component including a storage device720.

FIG.41Ais a perspective view of an electronic component70) and a substrate (circuit board704) on which the electronic component700is mounted. The electronic component700inFIG.41Aincludes the storage device720in a mold711.FIG.41Aomits part of the electronic component to show the inside of the electronic component7X). The electronic component700includes a land712outside the mold711. The land712is electrically connected to an electrode pad713, and the electrode pad713is electrically connected to the storage device720via a wire714. The electronic component700is mounted on a printed circuit board702, for example. A plurality of such electronic components are combined and electrically connected to each other on the printed circuit board702, which forms the circuit board704.

The storage device720includes a driver circuit layer721and a storage circuit layer722.

FIG.41Bis a perspective view of an electronic component730. The electronic component730is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component730, an interposer731is provided over a package substrate732(printed circuit board) and a semiconductor device735and a plurality of storage devices720are provided over the interposer731.

The electronic component730using the storage device720as a high bandwidth memory (HBM) is illustrated as an example. An integrated circuit (a semiconductor device) such as a CPU, a GPU, or an FPGA can be used as the semiconductor device735.

As the package substrate732, a ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used. As the interposer731, a silicon interposer, a resin interposer, or the like can be used.

The interposer731includes a plurality of wirings and has a function of electrically connecting a plurality of integrated circuits with different terminal pitches. The plurality of wirings have a single-layer structure or a layered structure. The interposer731has a function of electrically connecting an integrated circuit provided on the interposer731to an electrode provided on the package substrate732. Accordingly, the interposer is sometimes referred to as a “redistribution substrate” or an “intermediate substrate”. A through electrode may be provided in the interposer731to be used for electrically connecting the integrated circuit and the package substrate732. In the case of using a silicon interposer, a TSV (Through Silicon Via) can also be used as the through electrode.

A silicon interposer is preferably used as the interposer731. The silicon interposer can be manufactured at lower cost than an integrated circuit because it is not necessary to provide an active element. Moreover, since wirings of the silicon interposer can be formed through a semiconductor process, the formation of minute wirings, which is difficult for a resin interposer, is easily achieved.

An HBM needs to be connected to many wirings to achieve a wide memory bandwidth. Therefore, an interposer on which an HBM is mounted requires minute and densely formed wirings. For this reason, a silicon interposer is preferably used as the interposer on which an HBM is mounted.

In an SiP, an MCM, or the like using a silicon interposer, a decrease in reliability due to a difference in expansion coefficient between an integrated circuit and the interposer is less likely to occur. Furthermore, a surface of a silicon interposer has high planarity, and a poor connection between the silicon interposer and an integrated circuit provided thereon is less likely to occur. It is particularly preferable to use a silicon interposer for a 2.5D package (2.5D mounting) in which a plurality of integrated circuits are arranged side by side on the interposer.

A heat sink (radiator plate) may be provided so as to overlap with the electronic component730. In the case of providing a heat sink, the heights of integrated circuits provided on the interposer731are preferably equal to each other. In the electronic component730described in this embodiment, the heights of the storage device720and the semiconductor device735are preferably equal to each other, for example.

An electrode733may be provided on the bottom portion of the package substrate732to mount the electronic component730on another substrate.FIG.41Bshows an example in which the electrode733is formed of a solder ball. Solder balls are provided in a matrix on the bottom portion of the package substrate732, whereby a BGA (Ball Grid Array) can be achieved. Alternatively, the electrode733may be formed of a conductive pin. When conductive pins are provided in a matrix on the bottom portion of the package substrate732, a PGA (Pin Grid Array) can be achieved.

The electronic component730can be mounted on another substrate by various mounting methods not limited to BGA and PGA. For example, a mounting method such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), or QFN (Quad Flat Non-leaded package) can be employed.

The structure, method, and the like described in this embodiment can be used in an appropriate combination with other structures, methods, and the like described in this embodiment, the other embodiments, or Example.

In this embodiment, application examples of the storage device using the semiconductor device described in the above embodiment are described. The semiconductor device described in the above embodiment can be applied to, for example, storage devices of a variety of electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital cameras (including video cameras), video recording/reproducing devices, and navigation systems). Here, the computers refer not only to tablet computers, laptop computers, and desktop computers, but also to large computers such as server systems. Alternatively, the semiconductor device described in the above embodiment is applied to a variety of removable storage devices such as memory cards (e.g., SD cards). USB memories, and SSDs (solid state drives).FIG.42AtoFIG.42Eschematically show some structure examples of removable storage devices. The semiconductor device described in the above embodiment is processed into a packaged memory chip and used in a variety of storage devices and removable memories, for example.

FIG.42Ais a schematic view of a USB memory. A USB memory1100includes a housing1101, a cap1102, a USB connector1103, and a substrate1104. The substrate1104is held in the housing1101. The substrate1104is provided with a memory chip1105and a controller chip1106, for example. The semiconductor device described in the above embodiment can be incorporated in the memory chip1105or the like.

FIG.42Bis a schematic external view of an SD card, andFIG.42Cis a schematic view of the internal structure of the SD card. An SD card1110includes a housing1111, a connector1112, and a substrate1113. The substrate1113is held in the housing1111. The substrate1113is provided with a memory chip1114and a controller chip1115, for example. When the memory chip1114is also provided on the back side of the substrate1113, the capacity of the SD card1110can be increased. In addition, a wireless chip with a radio communication function may be provided on the substrate1113. With this, data can be read from and written in the memory chip1114by radio communication between a host device and the SD card1110. The semiconductor device described in the above embodiment can be incorporated in the memory chip1114or the like.

FIG.42Dis a schematic external view of an SSD, andFIG.42Eis a schematic view of the internal structure of the SSD. An SSD1150includes a housing1151, a connector1152, and a substrate1153. The substrate1153is held in the housing1151. The substrate1153is provided with a memory chip1154, a memory chip1155, and a controller chip1156, for example. The memory chip1155is a work memory of the controller chip1156, and a DOSRAM chip can be used, for example. When the memory chip1154is also provided on the back side of the substrate1153, the capacity of the SSD1150can be increased. The semiconductor device described in the above embodiment can be incorporated in the memory chip1154or the like.

The structure, method, and the like described in this embodiment can be used in an appropriate combination with other structures, methods, and the like described in this embodiment, the other embodiments, or Example.

The semiconductor device of one embodiment of the present invention can be used as a processor such as a CPU and a GPU or a chip.FIG.43AtoFIG.43Hshow specific examples of electronic devices including a chip or a processor such as a CPU or a GPU of one embodiment of the present invention.

<Electronic Device and System>

The GPU or the chip of one embodiment of the present invention can be mounted on a variety of electronic devices. Examples of electronic devices include a digital camera, a digital video camera, a digital photo frame, an e-book reader, a mobile phone, a portable game machine, a portable information terminal, and an audio reproducing device in addition to electronic devices provided with a relatively large screen, such as a television device, a monitor for a desktop or notebook information terminal or the like, digital signage, and a large game machine like a pachinko machine. When the GPU or the chip of one embodiment of the present invention is provided in the electronic device, the electronic device can include artificial intelligence.

The electronic device of one embodiment of the present invention may include an antenna. When a signal is received by the antenna, the electronic device can display a video, data, or the like on a display portion. When the electronic device includes the antenna and a secondary battery, the antenna may be used for contactless power transmission.

FIG.43Ashows a mobile phone (smartphone), which is a type of information terminal. An information terminal5100includes a housing5101and a display portion5102. As input interfaces, a touch panel is provided in the display portion5102and a button is provided in the housing5101.

When the chip of one embodiment of the present invention is applied to the information terminal5100, the information terminal5100can execute an application utilizing artificial intelligence. Examples of the application utilizing artificial intelligence include an application for recognizing a conversation and displaying the content of the conversation on the display portion5102; an application for recognizing letters, figures, and the like input to the touch panel of the display portion5102by a user and displaying them on the display portion5102; and an application for performing biometric authentication using fingerprints, voice prints, or the like.

FIG.43Bshows a notebook information terminal5200. The notebook information terminal5200includes a main body5201of the information terminal, a display portion5202, and a keyboard5203.

Like the information terminal5100described above, when the chip of one embodiment of the present invention is applied to the notebook information terminal5200, the notebook information terminal5200can execute an application utilizing artificial intelligence. Examples of the application utilizing artificial intelligence include design-support software, text correction software, and software for automatic menu generation. Furthermore, with the use of the notebook information terminal5200, novel artificial intelligence can be developed.

Note that althoughFIG.43AandFIG.43Bshow a smartphone and a notebook information terminal, respectively, as examples of the electronic device in the above description, an information terminal other than a smartphone and a notebook information terminal can be used. Examples of information terminals other than a smartphone and a notebook information terminal include a PDA (Personal Digital Assistant), a desktop information terminal, and a workstation.

FIG.43Cshows a portable game machine5300as an example of a game machine. The portable game machine5300includes a housing5301, a housing5302, a housing5303, a display portion5304, a connection portion5305, an operation key5306, and the like. The housing5302and the housing5303can be detached from the housing5301. When the connection portion5305provided in the housing5301is attached to another housing (not shown), an image to be output to the display portion5304can be output to another video device (not shown). In that case, the housing5302and the housing5303can each function as an operating unit. Thus, a plurality of players can play a game at the same time. The chip described in the above embodiment can be incorporated into the chip provided on a substrate in the housing5301, the housing5302and the housing5303.

FIG.43Dshows a stationary game machine5400as an example of a game machine. A controller5402is connected to the stationary game machine5400through wired or wireless connection.

Using the GPU or the chip of one embodiment of the present invention in a game machine such as the portable game machine5300and the stationary game machine5400achieves a low-power-consumption game machine. Moreover, heat generation from a circuit can be reduced owing to low power consumption: thus, the influence of heat generation on the circuit, a peripheral circuit, and a module can be reduced.

Furthermore, when the GPU or the chip of one embodiment of the present invention is applied to the portable game machine5300, the portable game machine5300including artificial intelligence can be achieved.

In general, the progress of a game, the actions and words of game characters, and expressions of an event and the like occurring in the game are determined by the program in the game; however, the use of artificial intelligence in the portable game machine5300enables expressions not limited by the game program. For example, it becomes possible to change expressions such as questions posed by the player, the progress of the game, time, and actions and words of game characters.

In addition, when a game requiring a plurality of players is played on the portable game machine5300, the artificial intelligence can create a virtual game player; thus, the game can be played alone with the game player created by the artificial intelligence as an opponent.

Although the portable game machine and the stationary game machine are shown as examples of game machines inFIG.43CandFIG.43D, the game machine using the GPU or the chip of one embodiment of the present invention is not limited thereto. Examples of the game machine to which the GPU or the chip of one embodiment of the present invention is applied include an arcade game machine installed in entertainment facilities (a game center, an amusement park, and the like), and a throwing machine for batting practice installed in sports facilities.

The GPU or the chip of one embodiment of the present invention can be used in a large computer.

FIG.43Eshows a supercomputer5500as an example of a large computer.FIG.43Fshows a rack-mount computer5502included in the supercomputer5500.

The supercomputer5500includes a rack5501and a plurality of rack-mount computers5502. The plurality of computers5502are stored in the rack5501. The computer5502includes a plurality of substrates5504on which the GPU or the chip shown in the above embodiment can be mounted.

The supercomputer5500is a large computer mainly used for scientific computation. In scientific computation, an enormous amount of arithmetic operation needs to be processed at a high speed; hence, power consumption is large and chips generate a large amount of heat. Using the GPU or the chip of one embodiment of the present invention in the supercomputer5500achieves a low-power-consumption supercomputer. Moreover, heat generation from a circuit can be reduced owing to low power consumption: thus, the influence of heat generation on the circuit, a peripheral circuit, and a module can be reduced.

Although a supercomputer is shown as an example of a large computer inFIG.43EandFIG.43F, a large computer using the GPU or the chip of one embodiment of the present invention is not limited thereto. Other examples of large computers in which the GPU or the chip of one embodiment of the present invention is usable include a computer that provides service (a server) and a large general-purpose computer (a mainframe).

The GPU or the chip of one embodiment of the present invention can be applied to an automobile, which is a moving vehicle, and the periphery of a driver's seat in the automobile.

FIG.43Gshows an area around a windshield inside an automobile, which is an example of a moving vehicle.FIG.43Gshows a display panel5701, a display panel5702, and a display panel5703that are attached to a dashboard and a display panel5704that is attached to a pillar.

The display panel5701to the display panel5703can provide a variety of kinds of information by displaying a speedometer, a tachometer, mileage, a fuel gauge, a gear state, air-condition setting, and the like. In addition, the content, layout, or the like of the display on the display panels can be changed as appropriate to suit the user's preference, so that the design quality can be increased. The display panel5701to the display panel5703can also be used as lighting devices.

The display panel5704can compensate for view obstructed by the pillar (a blind spot) by showing an image taken by an imaging device (not shown) provided for the automobile. That is, displaying an image taken by the imaging device provided outside the automobile leads to compensation for the blind spot and an increase in safety. In addition, displaying an image to compensate for a portion that cannot be seen makes it possible for the driver to confirm the safety more naturally and comfortably. The display panel5704can also be used as a lighting device.

Since the GPU or the chip of one embodiment of the present invention can be applied to a component of artificial intelligence, the chip can be used for an automatic driving system of the automobile, for example. The chip can also be used for a system for navigation, risk prediction, or the like. A structure may be employed in which the display panel5701to the display panel5704display navigation information, risk prediction information, or the like.

Note that although an automobile is described above as an example of a moving vehicle, the moving vehicle is not limited to an automobile. Examples of the moving vehicle include a train, a monorail train, a ship, and a flying vehicle (a helicopter, an unmanned aircraft (a drone), an airplane, and a rocket), and these moving vehicles can each include a system utilizing artificial intelligence when the chip of one embodiment of the present invention is applied to each of these moving vehicles.

FIG.43Hshows an electric refrigerator-freezer5800as an example of a household appliance. The electric refrigerator-freezer5800includes a housing5801, a refrigerator door5802, a freezer door5803, and the like.

When the chip of one embodiment of the present invention is applied to the electric refrigerator-freezer5800, the electric refrigerator-freezer5800including artificial intelligence can be achieved. Utilizing the artificial intelligence enables the electric refrigerator-freezer5800to have a function of automatically making a menu based on foods stored in the electric refrigerator-freezer5800, expiration dates of the foods, or the like, a function of automatically adjusting temperature to be appropriate for the foods stored in the electric refrigerator-freezer5800, and the like.

Although the electric refrigerator-freezer is described in this example as a household appliance, examples of other household appliances include a vacuum cleaner, a microwave oven, an electric oven, a rice cooker, a water heater, an IH cooker, a water server, a heating-cooling combination appliance such as an air conditioner, a washing machine, a drying machine, and an audio visual appliance.

The electronic devices, the functions of the electronic devices, the application examples of artificial intelligence, their effects, and the like described in this embodiment can be combined as appropriate with the description of another electronic device.

The structure, method, and the like described in this embodiment can be used in an appropriate combination with other structures, methods, and the like described in this embodiment, the other embodiments, or Example.

In this example, the influence of an oxygen adding step on the conductor260when a semiconductor device including the transistor200illustrated inFIG.4is fabricated was examined. Specifically, a cross section of a region where the conductor260and the insulator282aare in contact with each other in the transistor200inFIG.19Bwas observed before and after oxygen adding treatment inFIG.19and after heat treatment following the oxygen adding treatment.

A semiconductor device fabricated as a sample includes a plurality of transistors formed in the same process. Any two transistors extracted from the same substrate are referred to as Sample 1A and Sample 1B. The design values of a channel length L and a channel width W of Sample 1A and Sample 1B were set to L=60 nm and W=60 nm.

<Fabrication Method for Samples>

Methods for fabricating Sample 1A and Sample 1B are described below.

In Sample 1A and Sample 1B, the oxide230awas formed of an In—Ga—Zn oxide deposited by a sputtering method using a target with In:Ga:Zn=1:3:4 [atomic ratio]. Then, the oxide230bwas formed of an In—Ga—Zn oxide deposited by a sputtering method using an oxide target with In:Ga:Zn=4:2:4.1 [atomic ratio]. The oxide243was formed of an In—Ga—Zn oxide deposited by a sputtering method using a target with In:Ga:Zn=1:3:4 (atomic ratio).

For the insulator280, a silicon oxide film formed by a sputtering method was used. As the insulator250aand the insulator250b, silicon oxynitride and hafnium oxide were used, respectively.

As the conductor260a, titanium nitride deposited by a metal CVD method was used. As the conductor260b, tungsten deposited by a metal CVD method was used.

Next, the insulator282awas formed over the conductor260, the insulator250, and the insulator280. As the insulator282a,5-nm-thick aluminum oxide was deposited by a sputtering method.

Then, oxygen adding treatment was performed on the insulator280through the insulator282aFor the oxygen adding treatment, oxygen (02) was added by an ion implantation method.

After that, heat treatment was performed at 400° C. for one hour in a nitrogen atmosphere.

Through the above steps, Sample 1A and Sample 1B were fabricated.

<Cross-Sectional Observation of Sample 1A and Sample 1B>

Next, cross-sectional observation of Sample 1A and Sample 1B was performed. The cross-sectional observation was performed with a scanning transmission electron microscope (STEM). As an apparatus for the observation, HD-2700 manufactured by Hitachi High-Technologies Corporation was used.FIG.44shows cross-sectional STEM observation results of the samples.

Here, as illustrated inFIG.44, the thickness of the conductor260that was oxidized (the thickness of an oxide generated between the top surface of the conductor260and the insulator282a) is denoted as d.

In Sample 1A, d was 6.9 nm after the formation of the insulator282a,7.3 nm after the oxygen adding treatment, and 7.3 nm after the heat treatment. In Sample 1B, d was 6.2 nm after the formation of the insulator282a,7.3 nm after the oxygen adding treatment, and 8.0 nm after the heat treatment.

Thus, it was found that the oxygen adding treatment and the heat treatment oxidize the top surface of the conductor260in Sample 1A and Sample 1B in some cases. However, expansion due to oxidation through the oxygen adding treatment and the heat treatment after the oxygen adding treatment was not serious enough to cause shape anomaly, which indicates that the oxidation does not influence steps after the formation of the insulator282a.

At least part of this example can be implemented in combination with the other embodiments described in this specification as appropriate.

REFERENCE NUMERALS