Semiconductor device and wafer level package including such semiconductor device

An RDL structure on a passivation layer includes a first landing pad disposed directly above a first on-chip metal pad; a first via in a passivation layer to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad disposed directly above the second on-chip metal pad; a second via in the passivation layer to electrically connect the second landing pad with the second on-chip metal pad; and at least five traces being disposed on the passivation layer and passing through a space between the first landing pad and the second landing pad.

BACKGROUND

The present invention relates to a semiconductor device and package having fine RDL pitch and improved signal integrity.

Cost and size reduction is driving packaging industry to new measures and approaches. Wafer level packaging is one approach, which the packaging industry is looking into for size and cost reduction.

For example, Fan-Out Wafer Level Packaging (FOWLP), which is known in the art, integrates at least two individual integrated circuit (IC) dies in a side-by-side configuration into one molded semiconductor package having fan-out redistribution layer (RDL) and post passivation interconnection (PPI). The two IC dies are interconnected to each other through the RDL. FOWLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FCBGA) packages.

However, as more and more functions are incorporated into one single IC die, the die-to-die signal points have dramatically increased. The increased die-to-die signal points results in considerable loss of routing space in the redistribution layer (RDL). Currently, at most three to four signal traces can be arranged between two adjacent landing pads due to the relatively large size of each landing pad. There is no enough room for disposing the shielding traces. This adversely influences the signal integrity in high-speed applications because of crosstalk between signals.

Accordingly, there is a need in this industry to provide an improved wafer level package with fine RDL pitch and improved signal integrity.

SUMMARY

It is an objective of the claimed invention to provide an improved semiconductor device and package having fine RDL pitch and improved signal integrity.

According to one aspect of the invention, a semiconductor device includes an integrated circuit (IC) die having an active surface, wherein at least a first on-chip metal pad and a second on-chip metal pad in close proximity to the first on-chip metal pad are disposed on the active surface; a passivation layer on the active surface and covering the first on-chip metal pad and the second on-chip metal pad; and a redistribution layer (RDL) structure on the passivation layer. The RDL structure comprises a first landing pad disposed directly above the first on-chip metal pad; a first via in the RDL structure to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad being disposed directly above the second on-chip metal pad; a second via in the RDL structure to electrically connect the second landing pad with the second on-chip metal pad; and at least three traces being disposed on the RDL structure and passing through a space between the first landing pad and the second landing pad.

According to another aspect of the invention, a wafer level package includes an IC die having an active surface, wherein at least a first on-chip metal pad and a second on-chip metal pad in close proximity to the first on-chip metal pad are disposed on the active surface; a passivation layer on the active surface and covering the first on-chip metal pad and the second on-chip metal pad; a molding compound encapsulating the IC die except for the active surface; and a redistribution layer (RDL) structure on the passivation layer and on the molding compound. The RDL structure includes a first landing pad disposed directly above the first on-chip metal pad; a first via in the RDL structure to electrically connect the first landing pad with the first on-chip metal pad; a second landing pad being disposed directly above the second on-chip metal pad; a second via in the RDL structure to electrically connect the second landing pad with the second on-chip metal pad; and at least three traces being disposed on the RDL structure and passing through a space between the first landing pad and the second landing pad.

DETAILED DESCRIPTION

In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the disclosure may be practiced.

These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, chemical, electrical, and procedural changes may be made without departing from the spirit and scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims.

FIG. 1is a schematic, cross-sectional diagram showing an exemplary semiconductor device package according to one embodiment of the invention. The semiconductor device package1may be a Fan-Out Wafer Level Packaging (FOWLP) having molded integrated circuit (IC) dies arranged in a side-by-side configuration, but not limited thereto. Although a multi-die WLP package is illustrated, it is understood that the present invention may be applicable to single-die packages.

As shown inFIG. 1, the exemplary semiconductor device package1comprises two IC dies102and104arranged in a side-by-side configuration and molded by using a molding material20such as epoxy, resin, or other suitable molding compounds. The IC dies102and104have active surfaces102aand104a, respectively (in this figure both facing downward). On the active surfaces102aand104a, on-chip metal pads122and142such as aluminum (Al) pads are provided. These on-chip metal pads122and142are covered with passivation layers120and140, respectively. According to the illustrated embodiment, the passivation layers120and140may comprise silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass, or any combination thereof.

Optionally, dielectric capping layers124and144may be disposed directly on the passivation layers120and140respectively, thereby providing a planar major surface that is substantially flush with a surface of the molding material20surrounding the two IC dies102and104. According to the illustrated embodiment, the dielectric capping layers124and144are in direct contact with the passivation layers120and140, respectively. According to the illustrated embodiment, the dielectric capping layers124and144may comprise a polymeric material such as polyimide, a laminating tape, a backside grinding tape, an adhesive, an UV tap, or the like.

Although not shown in this figure, it is understood that the IC dies102and104may further comprise metal interconnection schemes underneath the passivaiton layers120and140, respectively. For example, the aforesaid metal interconnection schemes may include but not limited to ultra-low-k dielectric layers, inter-layer dielectric (ILD) layers, and multi-layer copper metal layers distributed or damascened in the dielectric capping layers. The metal interconnection schemes may be constructed on a semiconductor substrate such as a silicon substrate in and on which a plurality of semiconductor circuit elements such as transistors may be located. The details of the inner structures under the passivation layers120and140are omitted for the sake of simplicity.

Openings may be formed in the dielectric capping layer124and the passivation layers120and140. Each of the openings may expose a portion of the top surface of each of the metal pads122and142. Conductive pillar bumps126and146such as copper pillar bumps or copper contact plugs may be formed within the openings and fill up the openings on the metal pads122and142, respectively. It is to be understood that in other embodiments the dielectric capping layer124and the conductive pillar bumps126may be omitted.

A redistribution layer (RDL) structure200is formed directly on the dielectric capping layer124and on the molding material20surrounding the two IC dies102and104generally for signal fan-out purposes. According to the illustrated embodiment, the RDL structure200may comprise a plurality of insulating layers201,203,205, and207, for example, and a plurality of metal layers202,204, and206in and on the plurality of insulating layers201,203,205, and207. The insulating layers201,203,205, and207may comprise organic materials or polymeric materials including but not limited to polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), or the like. In other embodiments, the insulating layers201,203,205, and207may comprise inorganic materials.

For example, the metal layer202may comprise circuit features such as via202adisposed directly above each of the conductive pillar bumps126and146, a landing pad202b, and a fine trace202cextending and communicating between via and landing pad, or between landing pad and landing pad on the insulating layer201. InFIG. 1, an exemplary region indicated by the dashed lines310shows the route for die-to-die signal transmitting, which includes but not limited to die-to-die metal pads122aand142a, vias202a, landing pads202bon the metal pads and vias, and fine trace202cbetween the landing pads202b.

As alluded to hereinabove, as more and more functions are incorporated into one single IC die, the die-to-die signal points have dramatically increased. The increased die-to-die signal points results in considerable loss of routing space in the RDL. Conventionally, at most three to four signal traces can be arranged between two adjacent landing pads due to the relatively large size of each landing pad. There is no enough room for disposing the shielding traces. This adversely influences the signal integrity in high-speed applications because of crosstalk between signals. This invention addresses this problem.

Please refer toFIG. 2andFIG. 3.FIG. 2is a perspective plan view showing a portion of the RDL structure of a fan-out wafer level package (FOWLP) according to one embodiment of the invention.FIG. 3is a schematic, cross-sectional diagram taken along line I-I′ inFIG. 2. As shown inFIG. 2andFIG. 3, the RDL structure400fabricated on an IC die100may comprise two adjacent on-chip aluminum (Al) pads (AP), which are indicated by the dashed line301. The Al pads (AP) may be covered with a passivation layer410. According to the illustrated embodiment, the passivation layer410may comprise silicon oxide, silicon nitride, silicon oxynitride, undoped silicon glass, or any combination thereof. In other embodiments, the passivation layer410may comprise organic materials such as polyimide or the like. It is to be understood that more dielectric layers and metal layers may be formed on the passivation layer410for further connection as set forth inFIG. 1.

Openings may be formed in the passivation layer410. Each of the openings may expose a central portion of the top surface of each of the Al pads (AP). A copper via (V), which is indicated by the dashed line302, is formed directly on each of the Al pads (AP). A landing pad (LP) is formed directly on each of the copper vias (V). According to the illustrated embodiment, at least five fine traces S, G, S, G, S may pass through the space between the two adjacent landing pads (LP). The five fine traces S, G, S, G, S may comprise copper, but not limited thereto.

According to the illustrated embodiment, each of the Al pads (AP) may have a rectangular shape or oval shape when viewed from the above. Each of the Al pads (AP) may have a longitudinal length L1and a width W1. According to the illustrated embodiment, the longitudinal direction of each of the Al pads (AP) is in parallel with a reference y-axis, which may be the signal transmitting direction (die-to-die direction) between two IC dies102and104as set forth inFIG. 1. An aspect ratio of the each of the Al pads (AP) is defined as L1/W1, which may range between 2˜3, especially range between 1˜3, for example. The width W1may be one-half the longitudinal length L1, but not limited thereto. In some embodiments, the width W1may be smaller than one-half the longitudinal length L1, but not limited thereto. For not limiting example, longitudinal length L1may range between 35˜55 micrometers, for example, 45 micrometers, and the width W1may range between 15˜30 micrometers, for example, 20 micrometers.

According to the illustrated embodiment, each of the landing pads (LP) may have a rectangular shape or oval shape when viewed from the above. Each of the landing pads (LP) may have a longitudinal length L2and a width W2. According to the illustrated embodiment, the longitudinal direction of each of the landing pads (LP) is in parallel with the reference y-axis, which may be the signal transmitting direction (die-to-die direction) between two IC dies102and104as set forth inFIG. 1. An aspect ratio of the each of the landing pads (LP) is defined as L2/W2, which may range between 2˜3, especially range between 1˜3, for example. The width W2may be one-half the longitudinal length L2, but not limited thereto. In some embodiments, the width W2may be smaller than one-half the longitudinal length L2, but not limited thereto. For not limiting example, longitudinal length L2may range between 30˜50 micrometers, for example, 40 micrometers, and the width W2may range between 10˜25 micrometers, for example, 18 micrometers.

According to the illustrated embodiment, the five fine traces S, G, S, G, S extending along the reference y-axis (or die-to-die direction) between the two adjacent landing pads (LP) may transmit die-to-die signals. According to the illustrated embodiment, the two fine traces G may transmit ground signal and may function as shielding traces interposed between two high-speed signal traces, i.e. fine traces denoted with S. The term “SGS” may refer to a circuit layout structure comprising an intervening reference (e.g. grounded) trace sandwiched by a pair of high-speed or high-frequency signal traces, for example, operated greater than 1 Gb/s. The term “SGSGS” may refer to two intervening reference traces between three high-speed or high-frequency signal traces. By providing such configuration, the signal integrity can be significantly improved.

According to the illustrated embodiment, redistribution layer under the passivation layer410may be provided between the two Al pads (AP). For example, inFIG. 3, at least four aluminum traces (AT), which also extend along the reference y-axis (or die-to-die direction), are provided. It is advantageous to use the present invention because the landing pads (LP) and/or the Al pads (AP), especially those located within the region indicated by the dashed lines310inFIG. 1, have rectangular shape or oval shape when viewed from the above and therefore the space therebetween is widened to thereby accommodating more RDL traces. The SGSGS trace configuration depicted inFIG. 2andFIG. 3improves the signal integrity in the RDL level.

FIG. 4is a perspective plan view showing a portion of aluminum pads, copper vias, traces, and landing pads in the redistribution layer according to another embodiment of the invention. As shown inFIG. 4, when compared to the landing pads inFIG. 2, the landing pads (LP) inFIG. 4has a more slender shape, which has a longitudinal length L3that is greater than L2and a width W3that is smaller than W2. Due to the more slender shape of the landing pads (LP) inFIG. 4, the space between the two adjacent landing pads (LP) is further widened. Therefore, more RDL traces may be arranged in the space. For example, seven traces denoted by SGSGSGS comprising four high-speed signal traces and three reference or grounded traces are shown inFIG. 4. According to the illustrated embodiment, the landing pads (LP) inFIG. 4have substantially the same surface area as that of the landing pads (LP) shown inFIG. 2. In some cases, part of the boundary of the copper via (V) as indicated by the dashed line302may partially overlaps with part of the boundary or peripheral edge of the landing pad (LP).