Current mirror circuit with minimized input to output current error

A current mirror circuit for outputting an output current in proportion to an input current, comprises a first transistor having a collector through which the input current flows, a second transistor having a base connected to a base of the first transistor and a collector through which the output current flows, a third transistor having a base connected to a collector of the first transistor, and an emitter through which a predetermined current flows, and a fourth transistor having a base connected to an emitter of the third transistor, and an emitter connected to the base of the first and second transistors. A variable current source is connected between an emitter of the third transistor and ground to cause the predetermined current to flow through the third transistor. The value of the predetermined current is variable. An input current detecting circuit is provided to detect the input current for controlling the variable current source so as to maintain the predetermined current in proportion to the input current.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a current mirror circuit, and more 
specifically to a current mirror circuit suitable for a received signal 
indicator provided in a receiver for detecting a received electric field 
strength. 
2. Description of Related Art 
A receiver used in a communication system such as a PHS (personal 
handy-phone system) generally includes a received signal indicator for 
detecting a variation of a received electric field strength. 
Referring to FIG. 1, there is shown a block diagram illustrating the 
construction of a conventional received signal indicator. 
The shown received signal indicator, designated with Reference Numeral 102, 
is connected to a multi-stage amplifier 101 composed of a plurality of 
cascaded amplifiers for amplifying a received signal having an input power 
Pin. The received signal indicator 102 includes a detection circuit 103 
for detecting an output power supplied from each of the amplifiers of the 
multi-stage amplifier 101, and a current mirror circuit 104 and a resistor 
R.sub.L for outputting, on the basis of an output of the detection circuit 
103, a detection voltage V.sub.S in proportion to the input power Pin of 
the detection circuit 101. With this construction, a current Iref in 
proportion to the input power Pin of the detection circuit 101 is 
outputted from the detection circuit 103. Since the current mirror circuit 
104 acting as a buffer amplifier is connected to the output of the 
detection circuit 103, an output current I.sub.O of the current mirror 
circuit 104 is caused to flow through the resistor R.sub.L. Thus, the 
detection voltage V.sub.S in proportion to the input power Pin of the 
detection circuit 101 is outputted from between opposite ends of the 
resistor R.sub.L. 
Here, the current mirror circuit is a circuit operating to maintain a 
predetermined ratio between the input current Iref and the output current 
I.sub.O. Referring to FIG. 2, there is shown a circuit diagram of the 
simplest construction of the current mirror circuit, which is well known 
to persons skilled in the art. 
In the circuit construction shown in FIG. 2, however, since a base current 
I.sub.B1 flowing between a base and an emitter of a transistor Q.sub.101 
and a base current I.sub.B2 flowing between a base and an emitter of a 
transistor Q.sub.102 flows into the input current Iref, the output current 
I.sub.O becomes as follows: 
EQU I.sub.O =Iref+I.sub.B1 +I.sub.B2 
In order to reduce the influence of the base currents, a current mirror 
circuit as shown in FIG. 3 has been proposed in the prior art. 
The current mirror circuit shown in FIG. 3 includes a transistor Q.sub.111 
having an emitter connected through a resistor R.sub.111 to a power supply 
voltage V.sub.CC, a transistor Q.sub.112 having a base connected to a base 
of the transistor Q.sub.111 and an emitter connected through a resistor 
R.sub.112 to the power supply voltage V.sub.CC, a transistor Q.sub.113 
having a collector connected to the power supply voltage V.sub.CC and a 
base connected to a collector of the transistor Q.sub.111, a transistor 
Q.sub.114 having an emitter connected the bases of the transistors 
Q.sub.111 and Q.sub.112, a base connected to an emitter of the transistor 
Q.sub.113, and a collector connected to ground, and a constant current 
source 112 having one end connected to the emitter of the transistor 
Q.sub.113 and the other end connected to the ground. 
Here, assume that a collector current of the transistor Q.sub.111 is 
I.sub.C1, a collector current of the transistor Q.sub.112 is I.sub.C2 
(=I.sub.O), a base current of the transistor Q.sub.113 is I.sub.B3, an 
emitter current of the transistor Q.sub.114 is I.sub.E4, a base current of 
the transistor Q.sub.114 is I.sub.B4, and a current of the constant 
current source 112 is Ia. A relation between the output current I.sub.O 
and the input current Iref is expressed as follows: 
##EQU1## 
where h.sub.FEP is a current amplification factor of the PNP transistors 
(Q.sub.111, Q.sub.112 and Q.sub.114) and h.sub.FEN is a current 
amplification factor of the NPN transistors (Q.sub.113). 
As seen from the above equation (1), the prior art current mirror circuit 
shown in FIG. 3 has an error of Ia/(h.sub.FEN +1) between the input 
current Iref and the output current I.sub.O. However, since it is 
generally that h.sub.FEP, h.sub.FEN &gt;&gt;1, the error in the prior art 
current mirror circuit shown in FIG. 3 can be made smaller than that in 
the current mirror circuit shown in FIG. 2. 
However, in the case that the prior art current mirror circuit shown in 
FIG. 3 is incorporated in the received signal indicator, since the value 
of the input current Iref varies in a logarithmic characteristics, the 
error becomes large when the value of the input current Iref becomes 
small. The reason for this is that, since the error of Ia/(h.sub.FEN +1) 
exists between the input current Iref and the output current I.sub.O as 
shown in the equation (1), the smaller the value of the input current Iref 
becomes, the larger the influence of the output current Ia (constant 
value) of the constant current source becomes non-negligibly. In addition, 
since the value of the current amplification factors h.sub.FEP and 
h.sub.FEN greatly varies dependently upon the manufacturing process, if 
the value of the current amplification factors h.sub.FEP and h.sub.FEN 
becomes small, the error between the input current Iref and the output 
current I.sub.O becomes large. 
SUMMARY OF THE INVENTION 
Accordingly, it is an object of the present invention to provide a current 
mirror circuit which has overcome the above mentioned defect of the 
conventional one. 
Another object of the present invention is to provide a current mirror 
circuit having a minimized error of an output current to an input current 
even if the change of the input current is large and even if the variation 
of current amplification factors is large. 
The above and other objects of the present invention are achieved in 
accordance with the present invention by a current mirror circuit for 
outputting an output current in proportion relation to an input current, 
comprising: 
a first transistor having a collector through which the input current 
flows; 
a second transistor having a base connected to a base of the first 
transistor and a collector through which the output current flows; 
a third transistor having a base connected to a collector of the first 
transistor, and an emitter through which a predetermined current flows; 
a fourth transistor having a base connected to an emitter of the third 
transistor, and an emitter connected to the base of the first and second 
transistors; 
a variable current source connected to cause the predetermined current to 
flow through the third transistor, the value of the predetermined current 
being variable; and 
an input current detecting circuit detecting the input current for 
controlling the variable current source so as to maintain the 
predetermined current in proportion to the input current. 
In a preferred embodiment of the current mirror circuit, the input current 
detecting circuit includes: 
a fifth transistor having a base connected to the bases of the first and 
second transistors and a collector through which a current equal to the 
current flowing through the collector of the first transistor flows; 
a sixth transistor connected in series to the fifth transistor; and 
a seventh transistor having a base connected to a collector of the sixth 
transistor and a collector connected to a base of the sixth transistor. 
In addition, the variable current source includes an eighth transistor 
having a base connected to the base of the sixth transistor. 
According to another aspect of the present invention, there is provided a 
current mirror circuit for outputting an output current in proportion to 
an input current, comprising: 
a first transistor having a collector through which the input current 
flows; 
a second transistor having a base connected to a base of the first 
transistor and a collector through which the output current flows; 
a third transistor having a base connected to a collector of the first 
transistor, and an emitter through which a predetermined current flows; 
a variable current source connected to cause the predetermined current to 
flow through the third transistor, the value of the predetermined current 
being variable; and 
an input current detecting circuit detecting the input current for 
controlling the variable current source so as to maintain the 
predetermined current in proportion to the input current. 
In a preferred embodiment of this current mirror circuit, the input current 
detecting circuit includes: 
a fourth transistor having a base connected to the emitter of the third 
transistor and an emitter connected to the bases of the first and second 
transistors; and 
a fifth transistor connected in series to the fourth transistor, and having 
a collector and a base connected to each other. 
In addition, the variable current source includes a sixth transistor having 
a base connected to the base of the fifth transistor. 
In a specific embodiment, the above mentioned input current can be a 
current outputted from a detecting circuit for detecting a received 
electric field strength. 
In the current mirror circuit having the above mentioned construction, the 
predetermined current is caused to flow through the third transistor by 
the variable current source, and the value of the predetermined current is 
variable. In addition, the input current is detected by the input current 
detecting circuit, and the current flowing through the variable current 
source is controlled to be in proportion to the input current by the input 
current detecting circuit. Therefore, if the input current becomes small, 
the current of the variable current source correspondingly becomes small. 
Accordingly, even if the input current greatly changes, the error between 
the input current and the output current in the current mirror circuit can 
be minimized. 
The above and other objects, features and advantages of the present 
invention will be apparent from the following description of preferred 
embodiments of the invention with reference to the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Referring to FIG. 4, there is shown a block diagram illustrating a basic 
construction of the current mirror circuit in accordance with the present 
invention. 
The current mirror circuit shown in FIG. 1 includes a transistor Q.sub.1 
having an emitter connected through a resistor R.sub.1 to a power supply 
voltage V.sub.CC, a transistor Q.sub.2 having a base connected to a base 
of the transistor Q.sub.1 and an emitter connected through a resistor 
R.sub.2 to the power supply voltage V.sub.CC, a transistor Q.sub.3 having 
a collector connected to the power supply voltage V.sub.CC, a base 
connected to a collector of the transistor Q.sub.1, and a transistor 
Q.sub.4 having an emitter connected to the bases of the transistors 
Q.sub.1 and Q.sub.2, a base connected to an emitter of the transistor 
Q.sub.3, and a collector connected to ground. An input current Iref is 
caused to flow from a collector of the transistor Q.sub.1, and an output 
current I.sub.O is taken from a collector of the transistor Q.sub.2. 
The current mirror circuit shown in FIG. 1 also includes a variable current 
source 2 having one end connected to an emitter of the transistor Q.sub.3 
and the other end connected to the ground, and an input current detecting 
circuit 1 detecting the input current Iref of the current mirror circuit 
for controlling the output current Ia of the variable current source 2. 
With this arrangement, the input current detecting circuit 1 detects the 
value of the input current Iref for controlling the variable current 
source 2 so as to maintain the value of the output current Ia of the 
variable current source 2 in proportion to the value of the input current 
Iref. 
Accordingly, if the input current Iref becomes small, the output current Ia 
of the variable current source 2 correspondingly becomes small. Thus, even 
if the input current Iref greatly changes, an error between the input 
current Iref and the output current I.sub.O of the current mirror circuit 
can be minimized. 
As seen from the above, the current mirror circuit in accordance with the 
present invention shown in FIG. 4 is characterized in that, the constant 
current source in the prior art current mirror circuit shown in FIG. 3 is 
replaced with the variable current source 2 having the output current Ia 
which is changed or varied in accordance with the change of the input 
current Iref by the input current detecting circuit 1. 
Referring to FIG. 5, there is shown a circuit diagram of a first embodiment 
of the current mirror circuit in accordance with the present invention. In 
FIG. 5, elements corresponding to those shown in FIG. 4 are given the same 
Reference Numerals, and explanation will be omitted. 
In the current mirror circuit shown in FIG. 5, an input current detecting 
circuit 11 (corresponding to the input current detecting circuit 1 in FIG. 
1) includes a transistor Q.sub.5 having a base connected to the bases of 
the transistors Q.sub.1 and Q.sub.2 and an emitter connected through a 
resistor R.sub.3 to the power supply voltage V.sub.CC, a transistor 
Q.sub.6 having a collector connected to the power supply voltage V.sub.CC 
and a base connected to a collector of the transistor Q.sub.5, and a 
transistor Q.sub.8 having a collector connected to the collector of the 
transistor Q.sub.5 and the base of the transistor Q.sub.6, a base 
connected to an emitter of the transistor Q.sub.6, and an emitter 
connected through a resistor R.sub.5 to the ground. In this input current 
detecting circuit 11, the transistor Q.sub.5 is connected in the same 
circuit connection as that of the transistor Q.sub.1, so that a current 
flowing through the collector of the transistor Q.sub.5 is made equal to 
the input current Iref, with the result that the input current Iref is 
equivalently detected. 
A variable current source 12 (corresponding to the variable current source 
2 in FIG. 1) includes a transistor Q.sub.7 having a collector connected to 
the emitter of the transistor Q.sub.3, an emitter connected through a 
resistor R.sub.4 to the ground and a base connected to the emitter of the 
transistor Q.sub.6 and the base of the transistor Q.sub.8 in the input 
current detecting circuit 11. Here, if an emitter area ratio between the 
transistors Q.sub.7 and Q.sub.8 is expressed by Q.sub.7 :Q.sub.8 =N.sub.1 
:N.sub.2, respective resistance of the resistors R.sub.4 and R.sub.5 are 
in the relation of R.sub.4 .multidot.N.sub.1 =R.sub.5 .multidot.N.sub.2. 
In the construction shown in FIG. 5, assume that a collector current of the 
transistor Q.sub.1 is I.sub.C1, a collector current of the transistor 
Q.sub.2 is I.sub.C2 (=I.sub.O), a base current of the transistor Q.sub.3 
is I.sub.B3, an emitter current of the transistor Q.sub.4 is I.sub.E4, a 
base current of the transistor Q.sub.4 is I.sub.B4, a collector current of 
the transistor Q.sub.5 is I.sub.C5, a base current of the transistor 
Q.sub.6 is I.sub.B6, an emitter current of the transistor Q.sub.6 is 
I.sub.E6, a collector current of the transistor Q.sub.8 is I.sub.C8, and a 
collector current of the transistor Q.sub.7 is I.sub.C7 (=Ia). In this 
condition, a relation between the output current I.sub.O and the input 
current Iref is expressed as follows: 
##EQU2## 
where h.sub.FEP is a current amplification factor of the PNP transistors 
(Q.sub.1, Q.sub.2, Q.sub.4 and Q.sub.5) and h.sub.FEN is a current 
amplification factor of the NPN transistors (Q.sub.3, Q.sub.6, Q.sub.7 and 
Q.sub.8). 
Thus, if the input current Iref changes, the collector current I.sub.C8 of 
the transistor Q.sub.8 changes with the intermediary of the transistor 
Q.sub.5, and the collector current I.sub.C7 of the transistor Q.sub.7 
changes in proportion to the collector current I.sub.C8. 
In addition, as seen from the equation (2), since the output current 
I.sub.O is a function of the input current Iref, if the input current Iref 
becomes a small value, the current I.sub.C7 (=Ia) flowing through the 
variable current source 12 also becomes small, and therefore, the base 
current I.sub.B3 of the transistor Q.sub.3 correspondingly becomes small, 
with the result that the error between the input current Iref and the 
output current I.sub.O becomes small. Since the error is in proportion to 
1/(h.sub.FEN +1).sup.2, even if the value of the current amplification 
factors h.sub.FEN and h.sub.FEP becomes small, the error between the input 
current Iref and the output current I.sub.O becomes small in comparison 
with the prior art current mirror circuit. 
Here, a relation between the input current Iref and the output current 
I.sub.O in the current mirror circuit shown in FIG. 5 becomes as shown in 
the graph of FIG. 6 (where a mirror ratio=1). For reference, the graph of 
FIG. 6 additionally shows the relation between the input current Iref and 
the output current I.sub.O in the prior art current mirror circuit. In 
addition, a relation between the output current to input current ratio 
"I.sub.O /Iref" and the variation of the current amplification factors 
h.sub.FEN and h.sub.FEP in the current mirror circuit shown in FIG. 5 
becomes as shown in the graph of FIG. 7 (where a mirror ratio=1). For 
reference, the graph of FIG. 7 additionally shows the relation between the 
output current to input current ratio "I.sub.O /Iref" and the variation of 
the current amplification factors h.sub.FEN and h.sub.FEP in the prior art 
current mirror circuit. 
It would be understood from FIG. 6 that, in the current mirror circuit of 
the first embodiment, even if the value of the input current Iref greatly 
changes in a range of a few digits, the value of the output current 
I.sub.O closely follows the value of the input current Iref, and even if 
the input current Iref becomes small, the error never becomes large, 
clearly differently from the prior art. In addition, it would be 
understood from FIG. 7 that, in the current mirror circuit of the first 
embodiment, the error is maintained at a small value independently of the 
variation of the current amplification factors h.sub.FEN and h.sub.FEP. 
Referring to FIG. 8, there is shown a circuit diagram of a second 
embodiment of the current mirror circuit in accordance with the present 
invention. In FIG. 8, elements corresponding to those shown in FIG. 4 are 
given the same Reference Numerals, and explanation will be omitted. 
In the current mirror circuit shown in FIG. 8, an input current detecting 
circuit 21 (corresponding to the input current detecting circuit 1 in FIG. 
1) includes a transistor Q.sub.15 having an emitter connected to the bases 
of the transistors Q.sub.1 and Q.sub.2 and a base connected to the emitter 
of the transistor Q.sub.3, and a transistor Q.sub.18 having a collector 
and a base connected in common to a collector of the transistor Q.sub.15 
and an emitter connected through a resistor R.sub.15 to the ground. In 
this input current detecting circuit 21, the transistor Q.sub.15 detects 
the base current of the transistor Q.sub.3 to feed back the detection 
result to the bases of the transistors Q.sub.1 and Q.sub.2, similarly to 
the transistor Q.sub.4 in FIG. 4. In addition, the transistors Q.sub.15 
and Q.sub.18 detect the base currents of the transistors Q.sub.1 and 
Q.sub.2, so that the input current Iref of the current mirror circuit is 
equivalently detected. 
A variable current source 22 (corresponding to the variable current source 
2 in FIG. 1) includes a transistor Q.sub.17 having a collector connected 
to the emitter of the transistor Q.sub.3, an emitter connected through a 
resistor R.sub.14 to the ground and a base connected to the base of the 
transistor Q.sub.18 in the input current detecting circuit 21. Here, if an 
emitter area ratio between the transistors Q.sub.17 and Q.sub.18 is 
expressed by Q.sub.17 :Q.sub.18 =N.sub.1 :N.sub.2, respective resistance 
of the resistors R.sub.14 and R.sub.15 are in the relation of R.sub.14 
.multidot.N.sub.1 =R.sub.15 .multidot.N.sub.2. 
In the construction shown in FIG. 8, assume that a collector current of the 
transistor Q.sub.1 is I.sub.C1, a collector current of the transistor 
Q.sub.2 is I.sub.C2 (=I.sub.O), a base current of the transistor Q.sub.1 
is I.sub.B1, a base current of the transistor Q.sub.2 is I.sub.B2, a base 
current of the transistor Q.sub.3 is I.sub.B3, a base current of the 
transistor Q.sub.15 is I.sub.B15, and a collector current of the 
transistor Q.sub.17 is I.sub.C17 (=Ia). In this condition, a relation 
between the output current I.sub.O and the input current Iref is expressed 
as follows: 
##EQU3## 
where h.sub.FEP is a current amplification factor of the PNP transistors 
(Q.sub.1, Q.sub.2, and Q.sub.15) and h.sub.FEN is a current amplification 
factor of the NPN transistors (Q.sub.3, Q.sub.17 and Q.sub.18). 
In the circuit shown in FIG. 8, since a current mirror circuit is 
constituted of the transistor Q.sub.17 and the transistor Q.sub.18 in the 
input current detecting circuit 21, if the input current Iref changes, the 
collector current I.sub.C18 of the transistor Q.sub.18 changes, and the 
collector current I.sub.C17 of the transistor Q.sub.17 changes in 
proportion to the collector current I.sub.C18. 
In addition, as seen from the equation (3), since the output current 
I.sub.O is a function of the input current Iref, if the input current Iref 
becomes a small value, similarly to the first embodiment, the current 
I.sub.C17 (=Ia) flowing through the variable current source 22 also 
becomes small, and therefore, the base current I.sub.B3 of the transistor 
Q.sub.3 correspondingly becomes small, with the result that the error 
between the input current Iref and the output current I.sub.O becomes 
small. 
Here, a relation between the input current Iref and the output current 
I.sub.O in the current mirror circuit shown in FIG. 8 becomes as shown in 
the graph of FIG. 9 (where a mirror ratio=1). In addition, a relation 
between the output current to input current ratio "I.sub.O /Iref" and the 
variation of the current amplification factors h.sub.FEN and h.sub.FEP in 
the current mirror circuit shown in FIG. 8 becomes as shown in the graph 
of FIG. 10 (where a mirror ratio=1). 
It would be understood from FIG. 9 that, in the current mirror circuit of 
the second embodiment, similarly to the first embodiment, even if the 
value of the input current Iref greatly changes in a range of a few 
digits, the value of the output current I.sub.O closely follows the value 
of the input current Iref, and even if the input current Iref becomes 
small, the error never becomes large, clearly differently from the prior 
art. In addition, it would be understood from FIG. 10 that, in the current 
mirror circuit of the second embodiment, the error is maintained at a 
small value independently of the variation of the current amplification 
factors h.sub.FEN and h.sub.FEP. On the other hand, since the second 
embodiment can be constituted of the transistors of the number smaller 
than that of the transistors required in the first embodiment, the 
necessary circuit area can be reduced. 
Referring to FIG. 11, there is shown a circuit diagram of a third 
embodiment of the current mirror circuit in accordance with the present 
invention. In FIG. 11, elements corresponding to those shown in FIG. 4 are 
given the same Reference Numerals, and explanation will be omitted. 
In the current mirror circuit shown in FIG. 11, an input current detecting 
circuit 31 (corresponding to the input current detecting circuit 1 in FIG. 
1) includes a transistor Q.sub.25 having a base connected to the bases of 
the transistors Q.sub.1 and Q.sub.2 and an emitter connected through a 
resistor R.sub.23 to the power supply voltage V.sub.CC, and a transistor 
Q.sub.28 having a collector and a base connected in common to the 
collector of the transistor Q.sub.25 and the collector of the transistor 
Q.sub.4, and an emitter connected through a resistor R.sub.25 to the 
ground. In this input current detecting circuit 31, the transistor 
Q.sub.25 is connected in the same circuit connection as that of the 
transistor Q.sub.1, so that a current flowing through the collector of the 
transistor Q.sub.25 is made equal to the input current Iref, with the 
result that the input current Iref is equivalently detected. 
A variable current source 32 (corresponding to the variable current source 
2 in FIG. 1) includes a transistor Q.sub.27 having a collector connected 
to the emitter of the transistor Q.sub.3, an emitter connected through a 
resistor R.sub.24 to the ground and a base connected to the base of the 
transistor Q.sub.28 in the input current detecting circuit 31. 
Referring to FIG. 12, there is shown a circuit diagram of a fourth 
embodiment of the current mirror circuit in accordance with the present 
invention. In FIG. 12, elements corresponding to those shown in FIG. 4 are 
given the same Reference Numerals, and explanation will be omitted. 
In the current mirror circuit shown in FIG. 12, an input current detecting 
circuit 41 (corresponding to the input current detecting circuit 1 in FIG. 
1) includes a transistor Q.sub.35 having a base connected to the bases of 
the transistors Q.sub.1 and Q.sub.2 and an emitter connected through a 
resistor R.sub.33 to the power supply voltage V.sub.CC, and a transistor 
Q.sub.38 having a collector connected to the collector of the transistor 
Q.sub.35, a base connected to the collector of the transistor Q.sub.4, and 
an emitter connected through a resistor R.sub.35 to the ground. In this 
input current detecting circuit 41, the transistor Q.sub.35 is connected 
in the same circuit connection as that of the transistor Q.sub.1, so that 
a current flowing through the collector of the transistor Q.sub.35 is made 
equal to the input current Iref, with the result that the input current 
Iref is equivalently detected. 
A variable current source 42 (corresponding to the variable current source 
2 in FIG. 1) includes a transistor Q.sub.37 having a collector connected 
to the emitter of the transistor Q.sub.3, an emitter connected through a 
resistor R.sub.34 to the ground and a base connected to the base of the 
transistor Q.sub.38 in the input current detecting circuit 41. 
In these third and fourth embodiments, similarly to the first and second 
embodiments, if the input current Iref becomes small, the current flowing 
through the variable current source correspondingly becomes small, and 
therefore, the base current of the transistor Q.sub.3 becomes small, with 
the result that the error between the input current Iref and the output 
current I.sub.O becomes small. In addition, since the third and fourth 
embodiments can be constituted of the transistors of the number smaller 
than that of the transistors required in the first embodiment, the 
necessary circuit area can be reduced. 
As mentioned above, the current mirror circuit in accordance with the 
present invention is advantageous in that even if the value of the input 
current Iref greatly changes in a range of a few digits, and even if the 
input current Iref becomes extremely small, the error between the input 
current and the output current can be maintained at a minimized level. In 
addition, the error is maintained at the minimized value independently of 
the variation of the current amplification factors h.sub.FEN and 
h.sub.FEP. 
The invention has thus been shown and described with reference to the 
specific embodiments. However, it should be noted that the present 
invention is in no way limited to the details of the illustrated 
structures but changes and modifications may be made within the scope of 
the appended claims.