Packaging substrate having electrical connection structure and method for fabricating the same

A packaging substrate having an electrical connection structure and a method for fabricating the same are provided. The packaging substrate have a substrate body with a plurality of conductive pads on a surface thereof; a solder mask layer disposed on the substrate body with a plurality of openings corresponding to the conductive pads, the size of each of the openings being larger than each of the conductive pads; and electroplated solder bumps for covering the conductive pads to provide better bond strength and reliability.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to packaging substrates having an electrical connection structure and methods for fabricating the same, and more particularly to, a packaging substrate having an electrical connection structure for electrically connecting a chip and a method for fabricating the same.

2. Description of Related Art

The current flip chip technique involves electrically connecting a semiconductor chip to a packaging substrate, wherein the semiconductor chip has a plurality of electrode pads on an active surface thereof, and the packaging substrate has a plurality of conductive pads corresponding to the electrode pad. A solder structure or other conductive adhesive material is disposed between the electrode pads and the corresponding conductive pads for providing electrical connection and mechanical connection between the semiconductor chip and the packaging substrate.

Referring toFIGS. 1A to 1F, a conventional method for fabricating an electrical connection structure for a packaging substrate is shown. First, as shown inFIG. 1A, a substrate body10with a plurality of conductive pads11on at least one surface thereof is provided. Then, as shown inFIG. 1B, a solder mask layer12is formed on the surface of the substrate body10and a plurality of openings120are formed in the solder mask layer12to expose the conductive pads11. Subsequently, as shown inFIG. 1C, a mold plate13is disposed on the solder mask layer12and the mold plate13has a plurality of openings130corresponding to the openings120of the solder mask layer12. Thereafter, as shown inFIG. 1D, solder bumps14are formed in the openings130of the mold plate13by coating or printing. Then, as shown inFIG. 1E, the mold plate is removed. Finally, as shown inFIG. 1F, the solder bumps14are reflowed to form solder bumps14′ to provide electrical connection for the substrate body10.

In the above-described method, since the solder bumps14are filled in the openings120of he solder mask layer12and the openings130of the mold plate13by coating or printing, the quality of the solder bumps14is not easy to control, which can easily lead to poor uniformity in thickness and size of the solder bumps14, thereby adversely affecting the electrical connection quality.

Further, in a flip-chip bonding packaging process, when the line width and pitch of a packaging substrate are reduced, the joint strength is decreased as the joint size is reduced. When temperature in a thermal recycling process of the fabrication process varies or the completed package is in use, the joint strength is not sufficient to endure the stress caused by a CTE difference between the chip and the substrate, thus15resulting in joint separation or breakage between the solder bumps14′ and the electrode pads and failing to provide a preferred electrical connection.

Therefore, how to overcome the above-described drawbacks has become urgent.

SUMMARY OF THE INVENTION

According to the above drawbacks, an object of the present invention is to provide a packaging substrate having an electrical connection structure and a method for fabricating the same so as to provide fine-pitch electrical connection.

Another object of the present invention is to provide a packaging substrate having an electrical connection structure and a method for fabricating the same such that electroplated solder bumps formed on the surfaces of the conductive pads have a preferred uniformity in thickness and size, thereby improving the product reliability and providing better electrical connection quality.

In order to attain the above and other objects, the present invention provides a packaging substrate having an electrical connection structure, which comprises: a substrate body having a plurality of conductive pads on a surface thereof; a solder mask layer disposed on the surface of the substrate body with a plurality of openings corresponding to the conductive pads, each of the openings being larger in size than each of the conductive pads; and electroplated solder bumps for covering the conductive pads.

In the above-described structure, the electroplated solder bumps are made of a material selected form the group consisting of Sn, Ag, Cu, Bi, Zn, In and alloy thereof. Also, a second conductive seed-layer is disposed between the conductive pad and the electroplated solder bump.

According to another embodiment, a metal bump is disposed between the conductive pad and the electroplated solder bump. The metal bumps protrude above the surface of the solder mask layer, and the metal bumps are made of a material selected form the group consisting of Cu, Ni/Au, Cr, Cu with Ni/Pd/Au surface treatment, Cu with Au surface treatment, and Cu with Ni/Au surface treatment. According to a further embodiment, a metal attachment layer is disposed between the conductive pad and the electroplated solder bump, and the metal attachment layer is made of a material selected form the group consisting of Ni, Ni/Au, Zn and Ni/Pd/Au.

The above-described structure further comprises a first conductive seed-layer disposed between the substrate body and the conductive pad, and a second conductive seed-layer disposed between the conductive pad and the electroplated solder bump or disposed between the conductive pad and the metal bump.

The present invention further provides a method for fabricating a packaging substrate having an electrical connection structure, which comprises: providing a substrate body having a plurality of conductive pads on a surface thereof; forming on the surface of the substrate body a solder mask layer with a plurality of openings for completely exposing the conductive pads; forming a second conductive seed-layer on a surface of the solder mask layer, inner walls of the openings of the solder mask layer and surfaces of the conductive pads; forming on the surface of the second conductive seed-layer a first resist layer with a plurality of first openings to expose a part of the second conductive seed-layer, wherein each of the first openings is larger in size than each of the conductive pads and smaller in size than each of the openings of the solder mask layer; and forming electroplated solder bumps in the first openings through the second conductive seed-layer, allowing the electroplated solder bumps to protrude above the surface of the solder mask layer.

The above-described method further comprises removing the first resist layer and the second conductive seed-layer covered by the first resist layer, and performing a reflowing process. The electroplated solder bumps are made of a material selected form the group consisting of Sn, Ag, Cu, Bi, Zn, In and alloy of a combination thereof.

According to another embodiment, the method comprises forming metal bumps in the first openings through the second conductive seed-layer by electroplating for covering the conductive pads before formation of the electroplated solder bumps. The metal bumps protrude above the surface of the solder mask layer, and the metal bumps are made of a material selected form the group consisting of Cu, Ni/Au, Cr, Cu with Ni/Pd/Au surface treatment, Cu with Au surface treatment, and Cu with Ni/Au surface treatment.

According to a further embodiment, the method comprises forming a metal attachment layer on the surfaces of the conductive pads before formation of the second conductive seed-layer. The metal attachment layer is formed by one of chemical deposition and physical deposition. The metal attachment layer is made of a material selected form the group consisting of Ni, Ni/Au, Zn, and Ni/Pb/Au.

Therefore, the electroplated solder bumps are formed in the openings of the solder mask layer, uniformly formed on the surface of the second conductive seed-layer and covering the conductive pads. Further, since the electroplated solder bumps have less quality variance, after a reflowing process applied thereto, the reflowed electroplated solder bumps are uniform in thickness and size. Further, the electroplated solder bumps with much larger height can reduce joint stress, thereby improving the electrical connection reliability of the electroplated solder bumps and meeting the fine-pitch requirement.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The following illustrative embodiments are provided to illustrate the disclosure of the present invention, these and other advantages and effects can be apparent to those skilled in the art after reading the disclosure of this specification.

First Embodiment

FIGS. 2A to 2Hare sectional diagrams showing a method for fabricating a packaging substrate having an electrical connection structure according to a first embodiment of the present invention.

As shown inFIG. 2A, a substrate body20is provided, a first conductive seed-layer21ais formed on a surface thereof and a patterned resist layer22ais formed on the surface of the first conductive seed-layer21a. The resist layer22ahas a plurality of openings220a,221ato expose a part of the first conductive seed-layer21a.

As shown inFIG. 2B, through an electroplating process, circuit231is formed in the openings220aof the first conductive seed-layer21aand meanwhile conductive pads232are formed in the openings221a. The circuit231and the conductive pads232can be made of copper.

As shown inFIG. 2C, the patterned resist layer22aand the first conductive seed-layer21acovered by the resist layer22aare removed to expose the circuit231and the conductive pads232.

As shown inFIG. 2D, a solder mask layer24is formed on the surface of the substrate body20, and openings240are formed in the solder mask layer24to completely expose the conductive pads232.

As shown inFIG. 2E, a second conductive seed-layer21bis formed on a surface of the solder mask layer24, the inner walls of the openings240and surfaces of the conductive pads232. A first resist layer22bis formed on the surface of the second conductive seed-layer21bwith a plurality of first openings220bto expose a part of the second conductive seed-layer21b. The size of each of the first openings220bis larger than the size of each of the conductive pads232and smaller than the size of each of the openings240of the solder mask layer24.

As shown inFIG. 2F, electroplated solder bumps30are formed in the first openings220bthrough the second conductive seed-layer21bto completely enclose the conductive pads232. The electroplated solder bumps30can be made of a material selected from the group consisting of Sn, Pb, Cu, Ag, Bi, Zn, In and alloy thereof. The electroplated solder bumps30protrude above the surface of the solder mask layer24. Since the electroplating process is isotropic, a concave portion300is formed around the periphery of the top of the electroplated solder bumps30.

As shown inFIG. 2G, the first resist layer22band the second conductive seed-layer21bcovered by the first resist layer22bare removed to expose the electroplated solder bumps30.

As shown inFIG. 2H, the electroplated solder bumps30are reflowed to form electroplated solder bumps30′ that fill the openings240of the solder mask layer24and protrude above the surface of the solder mask layer24. Thus, the electroplated solder bumps30′ that are uniform in thickness and size are formed on the surfaces of the conductive pads232, thereby reducing joint stress for the package in a thermal recycling process or in use and providing better electrical connection quality and meeting the fine-pitch requirement.

Referring toFIG. 2G, the present invention further provides a packaging substrate having an electrical connection structure, which comprises: a substrate body20having a plurality of conductive pads232and circuit231formed on a surface thereof; a solder mask layer24disposed on the surface of the substrate body20and having a plurality of openings240corresponding to the conductive pads232, wherein each of the openings240is larger in size than each of the conductive pads232; and electroplated solder bumps30for completely enclosing the conductive pads232and protruding above the surface of the solder mask layer24. The electroplated solder bumps are made of a material selected from the group consisting of Sn, Ag, Cu, Bi, Zn, In and alloy of a combination thereof.

In the above structure, the electroplated solder bumps30can be reflowed to form electroplated solder bumps30′ that fill the openings240of the solder mask layer24and protrude above the surface of the solder mask layer24. Referring toFIG. 2H, since the electroplated solder bumps30′ formed on the surfaces of the conductive pads232are uniform in thickness and size, joint stress for the package can be reduced, thereby providing better electrical connection quality and meeting the fine-pitch requirement.

Second Embodiment

FIGS. 3A to 3Eare sectional diagrams showing a method for fabricating a packaging substrate having an electrical connection structure according to a second embodiment of the present invention. A difference of the present embodiment from the first embodiment is metal bumps are formed between the conductive pads and the electroplated solder bumps.

As shown inFIG. 3A, a structure as shown inFIG. 2Eis provided, a plurality of first openings220bare formed in the first resist layer22bto expose part of the second conductive seed-layer21b, wherein each of the first openings220bis larger in size than each of the conductive pads232and smaller in size than each of the openings240of the solder mask layer24.

As shown inFIG. 3B, metal bumps28are formed in the first openings220bthrough the second conductive seed-layer21bby electroplating to completely enclose the conductive pads232. The metal bumps28can protrude above the surface of the25solder mask layer24. Since the electroplating process is isotropic, a concave portion280is formed around the periphery of the top of the metal bumps28. The metal bumps28can be made of one of Cu, Ni/Au, Cr, Cu with Ni/Pd/Au surface treatment, Cu with Au surface treatment, and Cu with Ni/Au surface treatment.

As shown inFIG. 3C, electroplated solder bumps30are formed on the surfaces of the metal bumps28. Since the electroplating process is isotropic, a concave portion300is formed around the periphery of the top of the electroplated solder bumps30.

As shown inFIG. 3D, the first resist layer22band the second conductive seed-layer21bcovered by the first resist layer22bare removed to expose the electroplated solder bumps30and the metal bumps28.

As shown inFIG. 3E, the electroplated solder bumps30are reflowed to form electroplated solder bumps30′ that enclose the metal bumps28and fill the openings240of the solder mask layer24.

The present invention further provides a packaging substrate having an electrical connection structure, which has: a substrate body20having a plurality of conductive pads232and circuit231formed on a surface thereof; a solder mask layer24formed on the surface of the substrate body20and having a plurality of openings240corresponding in position to the conductive pads232, wherein each of the openings240is larger in size than each of the conductive pads232; a plurality of metal bumps28for covering the conductive pads232and protruding above surface of the solder mask layer24; and electroplated solder bumps30disposed on the metal bumps28, as shown inFIG. 3D. The electroplated solder bumps30can be reflowed to form electroplated solder bumps30′ to enclose the metal bumps28and fill the openings240of the solder mask layer24, as shown inFIG. 3E.

The above-described structure further comprises a first conductive seed-layer21adisposed between the substrate body20and the circuit231as well as the conductive pad232; and a second conductive seed-layer21bdisposed between the conductive pad232and the metal bump28.

Therefore, a larger bump height is obtained through the metal bumps28and the electroplated solder bumps30′ so as to reduce joint stress for the package in a thermal cycling process or in use, thereby avoiding joint separation or breakage phenomenon and meeting the fine-pitch requirement.

Third Embodiment

FIGS. 4A to 4Eare sectional diagrams showing a method for fabricating a packaging substrate having an electrical connection structure according to a third embodiment of the present invention. A difference of the present embodiment from the above-described embodiments is a metal attachment layer is formed between the conductive pads and the electroplated solder bumps.

As shown inFIG. 4A, a structure as shown inFIG. 2Dis provided, a metal attachment layer26is formed on the surfaces of the conductive pads232by chemical deposition or physical deposition and covering the conductive pads232. The metal attachment layer26can be made of one of Ni, Ni/Au, Zn, and Ni/Pd/Au.

As shown inFIG. 4B, a second conductive seed-layer21bis formed on the surface of the solder mask layer24, the inner walls of the openings240and a surface of the metal attachment layer26. A first resist layer22bis formed on a surface of the second conductive seed-layer21band a plurality of first openings220bare formed in the first resist layer22bto expose a part of the second conductive seed-layer21b.Moreover, each of the first openings220bis larger in size than each of the conductive pads232and smaller in size than each of the openings240of the solder mask layer24.

As shown inFIG. 4C, electroplated solder bumps30are formed in the first openings220bthrough the second conductive seed-layer21b. The electroplated solder bumps30protrude above the surface of the solder mask layer24. Since the electroplating process is isotropic, a concave portion300is formed around the periphery of the top of the electroplated solder bumps30.

As shown inFIG. 4D, the first resist layer22band the second conductive seed-layer21bcovered by the first resist layer22bare removed to expose the electroplated solder bumps30.

As shown inFIG. 4E, the electroplated solder bumps30are reflowed to form electroplated solder bumps30′ that fill the openings240of the solder mask layer24and protrude above the surface of the solder mask layer24. Thus, the electroplated solder bumps30′ that are uniform in thickness and size are formed on the surfaces of the conductive pads232, thereby reducing joint stress for the package in a thermal recycling process or in use and providing better electrical connection quality and meeting the fine-pitch requirement.

The present invention further provides a packaging substrate having an electrical connection structure, which has: a substrate body20having a plurality of conductive pads232and circuit231formed on a surface thereof; a metal attachment layer26for covering the conductive pads232; a solder mask layer24disposed on the surface of the substrate body20and having a plurality of openings240corresponding in position to the conductive pads232, wherein the size of each of the openings240is larger than that of each of the conductive pads232; and electroplated solder bumps30for covering the metal attachment layer26and protruding above surface of the solder mask layer24, as shown inFIG. 4D. The electroplated solder bumps30can be reflowed to form electroplated solder bumps30′ which fill the openings240of the solder mask layer24, as shown inFIG. 4E.

The metal attachment layer26is used to increase the contact area between the conductive pads and the electroplated solder bumps30′ and reduce formation of intermetallic complex between the electroplated solder bumps30′ and the conductive pads232, thereby providing better electrical connection quality and reducing joint stress for the package in a thermal cycling process or in use so as to avoid joint separation or breakage phenomenon and meet the fine-pitch requirement.

The above-described descriptions of the detailed embodiments are only to illustrate the preferred implementation according to the present invention, and it is not to limit the scope of the present invention. Accordingly, all modifications and variations completed by those with ordinary skill in the art should fall within the scope of present invention defined by the appended claims.