Circuit and method for operating a circuit

A circuit and method for operating a circuit is provided that includes a circuit section that has a number of memory elements, a first voltage regulator that can be connected or is connected to the circuit section in order to operate the circuit section, a second voltage regulator that can be connected or is connected to the circuit section in order to preserve an information item stored in the memory elements, a switching device that is connected to the circuit section and is designed to deactivate and activate inputs of the circuit section. The circuit being configured to control a deactivation and activation of the first voltage regulator and the deactivation and activation of the inputs of the circuit section.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a circuit and a method for operating a circuit.

2. Description of the Background Art

Digital circuits can be run in an operating mode for information processing and in a sleep mode (or standby) with reduced power consumption as compared to the operating mode. The information content in memory elements of the digital circuits can be preserved during this process if the memory elements are also supplied with a voltage in the sleep mode. For this purpose, one can provide a battery and/or rechargeable battery, for example, that is connected to the memory elements in sleep mode.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to improve a circuit to the greatest extent possible. Accordingly, a circuit is provided that can be monolithically integrated on a semiconductor chip.

The circuit has a circuit section having a number of memory elements that are, in particular, volatile, such as registers, latches, or flip-flops, for example.

The circuit can have a first voltage regulator that can be connected to the circuit section, in particular through a switch, or is permanently connected to the circuit section, in order to operate the circuit section.

The circuit can have a second voltage regulator that can be connected to the circuit section, in particular through a switch, or is permanently connected to the circuit section, in order to preserve information stored in the memory elements.

The circuit can have a switching device that is connected to the circuit section. The switching device is designed to deactivate and activate inputs of the circuit section. For the purpose of deactivation and activation, the switching device is advantageously connected ahead of the inputs of the circuit section. Preferably, the switching device has switching means, such as semiconductor switches and/or logic elements and/or switchable level shifters, for activation and deactivation of the inputs.

The circuit can be designed to control a deactivation and activation of the first voltage regulator and the deactivation and activation of the inputs of the circuit section. In advantageous fashion, the circuit section is designed and configured for control. Alternatively or in combination, the circuit has additional control means for control.

The invention can have the additional object of specifying a method that is improved to the greatest degree possible. Accordingly, a method for operating a circuit is also provided.

For a sleep mode, inputs of a circuit section of the circuit are deactivated, wherein the circuit section has a number of memory elements. The inputs can be designed and configured for information entering the circuit section, such as individual bits or bit words transmitted serially or in parallel. For deactivation, the input value is preferably switched to a fixed, predetermined logic voltage, for example zero or one.

A first voltage regulator is deactivated after deactivation of the inputs of the circuit section, so that the memory elements of the circuit section are supplied from a second voltage regulator. Preferably the first voltage regulator is deenergized for deactivation.

For an operating mode following the sleep mode, the first voltage regulator is activated in order to supply the circuit section. As compared to the sleep mode, the operating mode can have a higher power consumption, in particular in order to execute a plurality of functions, in particular procedure steps of a program sequence.

For the operating mode, the inputs of the circuit section are activated after activation of the first voltage regulator, in particular in order to process information entering through the inputs of the circuit section.

The invention additionally has the object of specifying a use. Accordingly, the use of a first voltage regulator for an operating mode and of a second voltage regulator for a sleep mode is provided. The first voltage regulator and the second voltage regulator are preferably components of one and the same monolithically integrated circuit. The information processing in the operating mode is significantly increased as compared to the sleep mode. In sleep mode, the power consumption is significantly reduced as compared to the operating mode. The memory content of memory elements of the circuit preferably is not changed in sleep mode.

In the operating mode, the first voltage regulator of a circuit provides a supply voltage and an operating current for a circuit section of the circuit.

The second voltage regulator of the circuit provides a standby voltage and a standby current for the circuit section for the sleep mode.

The second voltage regulator consumes less current than the first voltage regulator of the circuit. Preferably, the first voltage regulator is specifically designed for providing the operating current. Preferably, the second voltage regulator is specifically designed for providing the standby current. Preferably the standby current is smaller than the operating current by at least a factor of 100.

The improvements described refer to the circuit as well as to the use and to the method.

According to an embodiment, the circuit can be designed to control an operating mode with digital state changes of the circuit section and to control a sleep mode with no digital state changes, or with a reduced number of digital state changes as compared to the operating mode. In advantageous fashion, the current consumption in the sleep mode is reduced as compared to the operating mode.

According to another embodiment, the circuit can have an additional circuit section. The additional circuit section can be connected to inputs and/or outputs of the circuit section. In particular, the current consumption of the additional circuit section can be greater in the operating mode than that of the circuit section. Advantageously, the additional circuit section can have functions for transmitting and receiving signals transmitted by radio, in particular digital signal processing.

The circuit can have a switch that is connected to the additional circuit section and to the second voltage regulator. In addition, the switch can also be connected or capable of connection to the first voltage regulator. The circuit is preferably designed to operate the switch for the sleep mode for separating the additional circuit section from the second voltage regulator.

In another embodiment, the switching device can have a number of switchable level shifters. Preferably the circuit has components that are specified for at least two different voltages—for example, 3.3 V and 1.8 V. The level shifters are preferably designed and connected to convert information to and from one of the circuit sections between different logic levels at their inputs.

In another embodiment, the circuit has a reset device that can be designed to issue reset signals for resetting the circuit section and/or the additional circuit section. The reset device can be designed to control the switching device by means of control signals.

According to an embodiment, the reset device can be connected to the first voltage regulator. Preferably the reset device is designed to activate the first voltage regulator upon an initial application of an input voltage—in particular a battery voltage—to the circuit.

In another embodiment, the reset device can have a memory element whose stored value represents an initial application of an input voltage to the circuit.

The reset device can be designed to enable an activation of the first voltage regulator by the circuit section. Preferably the enabling takes place following the initial application of an input voltage.

According to an embodiment, provision is made that only the first voltage regulator of the two voltage regulators has a control loop, which is connected to a supply voltage output of the first voltage regulator, in particular through a voltage divider. Preferably the first voltage divider is connected to a reference voltage source. It is preferred for the reference voltage source to be a band gap reference voltage source. Preferably the second voltage regulator has its own current reference. The second voltage regulator thus generates its own bias current (self biasing). The current reference of the second voltage regulator has a lower precision and constancy than the band gap reference voltage source of the first voltage regulator. Preferably the second voltage regulator has a current-to-voltage converter for generating the supply voltage from the bias current. Preferably the second voltage regulator is connected in parallel with the first voltage regulator, so that the outputs of the first and second voltage regulators are connected to one another. Preferably in this situation, the second voltage regulator has means that act as a diode. The second voltage regulator advantageously has a transistor that is connected as an emitter follower or source follower. The transistor acts as a diode here, so that no significant current flows into the second voltage regulator in the reverse direction of the diode.

DETAILED DESCRIPTION

InFIG. 1, a circuit is schematically represented by a block diagram. A digital circuit section300has a number of memory cells311,312,313such as, e.g., flip-flops or registers. The memory cells311,312,313are volatile, so that the information stored in the memory cells311,312,313is lost when no supply voltage VDD is applied. The circuit in the example embodiment inFIG. 1is supplied by a battery voltage VB. This battery voltage VB can vary, for example in a voltage range up to 3.6 V. The digital circuit section300, in contrast, has components that are specified for a lower supply voltage VDD of a nominal 1.8 V to a maximum 2.0 V.

A first voltage regulator100is connected to the battery voltage VB. The first voltage regulator100is designed to provide at its output the supply voltage VDD for the digital circuit section300. In this context, the first voltage regulator100is designed to output a supply voltage for an operating mode for the digital circuit section300. In the operating mode, the digital circuit section300executes steps of an information processing task, thus for example a calculation, storage, or the like. For this purpose, logic values of basic digital cells, such as gates, flip-flops, or the like, change, wherein this state change causes a charging and discharging of capacitors. A total displacement current through all capacitors is made available in this situation by the first voltage regulator100via the supply current. The first voltage regulator100additionally requires its own operating current of approximately 100 μA in order to regulate the supply voltage VDD to a stable value.

In addition, the circuit shown inFIG. 1can also be run in a sleep mode. To this end, the circuit has means that initiate a sleep mode. For example, the sleep mode can be initiated by the circuit section100itself or by a connected circuit (not shown inFIG. 1). In sleep mode, the current consumption of the circuit should be minimized. For example, the current consumption is approximately 0.1 μA in order to ensure a long battery life.

Because of the high internal current consumption of the first voltage regulator100, said voltage regulator is deactivated in the sleep mode. For deactivation of the first voltage regulator100, it can be switched off by means of a switch (not shown), for example.

In sleep mode, the information stored in the memory cells311,312,313is supposed to be preserved. In contrast to the example embodiment inFIG. 1, it is possible in principle to design the circuit section300with components for the battery voltage VB in such a manner that the circuit section would only have to be connected to the battery voltage VB in sleep mode to preserve the stored information. However, a different solution is provided inFIG. 1.

In the example embodiment fromFIG. 1, connected in parallel to the first voltage regulator100is a second voltage regulator200, which likewise provides the supply voltage VDD and is connected to the first circuit section100in the same manner as the first voltage regulator100. As an alternative toFIG. 1, it is also possible to connect a number of switches between a voltage regulator100or200and the circuit section300in such a manner that the circuit section can be connected to the first voltage regulator100and/or to the second voltage regulator200by means of a switch.

The internal current consumption of the second voltage regulator200is smaller than the internal current consumption of the first voltage regulator100. The first voltage regulator100provides a maximum supply voltage that is greater than the maximum supply voltage of the second voltage regulator200. In the example embodiment inFIG. 1, the first voltage regulator100and the second voltage regulator200are connected in parallel.

In the example embodiment fromFIG. 1, the first voltage regulator100can be activated in a controlled manner through the circuit section300as well as through a reset device500. During the initial startup after the application of an input voltage VB (battery voltage), the first voltage regulator100is activated by the reset device500. A piece of information corresponding to the initial startup is stored in a memory element510, for example a flip-flop, of the reset device500. Subsequently, the control function of activation and deactivation is transferred to the circuit section300by the reset device500. To this end, the reset device500enables the connection between the circuit section300and the first voltage regulator100by means of a switching device400. The circuit section300can now in turn control the activation and deactivation of the first voltage regulator100by means of the control signal en_vdd. In advantageous fashion, the reset device500is also designed to reset the circuit section300, for example upon initial startup.

The switching device400is designed to activate and deactivate inputs E1, E2, E3of the circuit section300. In the example embodiment inFIG. 1, this switching function of activation and deactivation of the inputs E1, E2, E3is controlled by the first voltage regulator100, which outputs a control signal vdd_ok33to the switching device400for activation and deactivation of the inputs E1, E2, E3.

InFIG. 2, another example embodiment is shown schematically as a block diagram of a circuit. A circuit section300with control functions and test functions is supplied through the supply voltages VDD and VSS, each of which is connected to the circuit through a terminal930or920, respectively. A capacitor320is connected in parallel to the circuit section300. An external capacitor910can additionally be connected in parallel by means of the terminals920and930.

The supply voltage VDD (approximately 1.8 V) is produced from an input voltage VB (approximately 3.3 V) present at the terminal900by means of an activatable and deactivatable voltage regulator100(Vreg). In addition, an oscillator circuit700(Xosc) and a band gap reference voltage source710are provided, which are supplied with the voltages EVDD and AVSS at the terminals970and971.

The blocks410,402,403and404of a switching device have multiple functions. The blocks401,402and403have level shifters in order to transfer signals between a voltage of the input voltage VB and a voltage of the supply voltage VDD in the applicable direction. The level shifters of block401and block403convert incoming signals of the voltage of the input voltage VB to corresponding signals with the voltage of the supply voltage VDD. The level shifters of block402convert incoming signals of the voltage of the supply voltage VDD to corresponding signals with the voltage of the input voltage VB.

In addition, a reset device500is provided that is connected to the terminal950to receive a reset signal RSTN. The reset signal RSTN serves to reset the circuit by the external reset signal RSTN, regardless of the present mode. The reset device500has another input that is connected to a signal output of the first voltage regulator100. At the signal output, the first voltage regulator provides a status signal vdd_ok33, which indicates a regulated supply voltage VDD.

As a function of the input signals explained above, the reset device500carries out corresponding reset functions. This is explained in more detail in connection withFIG. 3. In the example embodiment fromFIG. 2as well, the first voltage regulator100is activated by the reset device500during initial startup after the application of the input voltage VB (battery voltage). Subsequently, the control function of activation and deactivation is again transferred to the circuit section300by the reset device500. To this end, the reset device500outputs a control signal to the block402of the switching device, so that the connection between the circuit section300and the first voltage regulator100is enabled. The circuit section300independently controls the activation and deactivation of the first voltage regulator100by means of the control signal en_vdd.

The circuit section300is designed to control the activation and deactivation of the first voltage regulator100. The initiation of a sleep mode is possible through a signal SLP at the terminal940, in that the current consumption of the circuit is reduced as compared to an operating mode. For this purpose, the signal SLP arrives at the input E4through the level shifter of block401to the circuit section300. The circuit section300deactivates the first voltage regulator100through the block402by means of the signal en_vdd. In addition, the circuit section300deactivates the band gap reference voltage source710by means of the signal en_bg through the block402, and deactivates the oscillator circuit700by means of the signal en_osc. Alternatively, it is also possible for the circuit section300to automatically initiate a sleep mode, for example after executing a program sequence.

The status signal vdd_ok33of the deactivated first voltage regulator100arrives at the blocks401and403and at the reset device500. In this process, the switch610is operated through the level shifter of the block403such that an additional circuit section600is isolated from the supply voltage VDD. Once again, a capacitor620is connected in parallel to the additional circuit section600. The additional circuit section600is designed to transmit and receive digital data. In the operating mode, the additional circuit section600is supplied with the supply voltage VDD by the first voltage regulator100. In sleep mode, in contrast, the additional circuit section is isolated from the supply voltage VDD by the switch610.

In sleep mode, only the second voltage regulator200(Vreglo) is active, which has a smaller current consumption than the first voltage regulator100, in particular smaller by at least a factor of100. The supply outputs of the first voltage regulator100and of the second voltage regulator200are connected to one another and to the circuit section300. Since the circuit section300is also supplied with the supply voltage VDD in the sleep mode—by the second voltage regulator200—the information contained in the memory elements311,312,313is also preserved in the sleep mode. The states (low, high) of the digital elements (gates, etc.) of the circuit section300remain defined.

The states of the digital elements (gates, etc.) of the additional circuit section600, in contrast, are not defined because of the isolation by the switch610. So that these undefined states of the additional circuit section600do not affect the circuit section300, a block404of the switching device, designed to deactivate and activate the inputs E2of the circuit section300, is provided in the example embodiment inFIG. 2. If the inputs E2of the circuit section300are deactivated by the switching function of the block404in sleep mode, then no undefined states of the additional circuit section600can arrive at the circuit section300. In like manner, the input E1for the clock signal clk33is deactivated by the switching function of the block401of the switching device in sleep mode so that no clock signal clk18arrives at the circuit section300.

InFIG. 3, a reset device500is shown schematically. This device has a plurality of inverters511,512,514,552,555,556, a plurality of NAND gates513,553,554, flip-flops510,551, and a filter550. An additional terminal980is provided for test purposes. The reset device500has two functions. The reset device500generates a reset signal upon application of the input voltage VB and filters at the terminal950a reset signal rstn generated outside of the circuit.

The RS flip-flop510has a static and dynamic asymmetry of its transistors. This implementation has the effect that the RS flip-flop510enters a defined “on” state upon application of the input voltage VB. The output signal of the RS flip-flop510forces both reset output signals to low potential, which accomplishes a reset of all circuit sections300,600. The RS flip-flop510maintains this state until the supply voltage VDD is ramped up. The status signal vdd_ok33from the first voltage regulator100resets the RS flip-flop510and terminates the reset signals rst_pw33, rst_main33.

The external signal rstn travels through the filter550, which delays the falling edge of the signal in order to avoid spikes in the reset signal. The rising edge, in contrast, is not delayed. The additional flip-flop551stores the reset event in sleep mode. This is necessary because at first there is not yet a supply voltage VDD available to the circuit section300when the input voltage VB is being applied. For this reason, after the ramp-up of the supply voltage VDD, and the status signal vdd_ok33of the first voltage regulator100resets the flip-flop551.

InFIG. 4, the first voltage regulator100and the second voltage regulator200are shown schematically in a circuit diagram.

The first voltage regulator has an operational amplifier110with differential amplifier and driver stage; whose negative input is connected to the band gap reference voltage source710. The gap reference voltage source710provides a reference voltage of 1.25 V here. The output of the operational amplifier100is connected to a P-MOSFET output transistor120, which is configured for the supply current in operating mode to a maximum of 30 mA. The output150of the first voltage regulator100is connected to the drain terminal of the transistor120. Also connected to the drain terminal of the transistor120is a resistor voltage divider with the resistors131and132, wherein the center tap of the resistor voltage divider is connected to the positive input of the operational amplifier110.

This connection from the output through the resistor voltage divider to the input of the operational amplifier110constitutes a control loop. This control loop makes it possible to stabilize load changes at the output150in operating mode. The supply voltage can be held constant at the value of 1.8 V by means of the control loop.

The operational amplifier110can be switched off in sleep mode in order to deactivate the first voltage regulator100. In addition, in sleep mode the resistor voltage divider is isolated from the output150by the switch140. The operational amplifier110required for the control loop is largely responsible for the current consumption of 100 μA in operating mode. The second voltage regulator200is always switched on. The second voltage regulator200has a current source210for a current IBIAS, which is mirrored by means of the two PMOS transistors211,212wired as a current mirror to the series-connected NMOS transistors231,232,233wired as MOS diodes. The current source may be a PTAT circuit, for example.

The voltage dropping across the NMOS transistors231,232,233is also present at the NMOS transistor220wired as a source follower, whose source is connected to the output of the second voltage regulator220and performs voltage regulation. In this arrangement, the second voltage regulator200provides the supply voltage VDD in sleep mode, for example at a level of 1.6 V. The supply voltage in sleep mode can lie in a range between 1.2 V and 2.0 V without the information stored in the memory elements311,312,313of the circuit section300being lost. Thus, the supply voltage VDD can deviate in the operating mode and from that in the sleep mode. In this arrangement, the second voltage regulator200has no control loop connected with the output of the second voltage regulator200.

The invention is not restricted to the variant embodiments shown inFIGS. 1 through 4. For example, it is possible to use different voltage regulator circuits than those explained inFIG. 4. The functionality of the circuit fromFIG. 2can be used to particular advantage for a radio network system, especially in compliance with the IEEE 802.15.4 industry standard for battery operation.