Source driver in liquid crystal display device, output buffer included in the source driver, and method of operating the output buffer

Provided is an output buffer, which may be included in a source driver of a liquid crystal display (LCD) device. The output buffer may include a differential amplification unit and an output unit. The differential amplification unit may generate control currents by amplifying the difference between the voltages of an analog image signal and a signal output from the output buffer. The output unit outputs the amplified analog image signal in response to the control currents. The amount of bias current used to drive the differential amplification unit increases during a charge recycling period, and the amount of quiescent current flowing through the output unit decreases during the charge recycling period. The amount of the bias current used to drive the differential amplification unit decreases during a driving period, and the amount of the quiescent current flowing through the output unit increases during the driving period.

PRIORITY STATEMENT

This application claims the benefit of Korean Patent Application No. 10-2007-0051078, filed on May 25, 2007, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND

1. Field of the Invention

Example embodiments relate to a liquid crystal display (LCD) device, and more particularly, to a source driver included in a LCD device, an output buffer included in the source driver, and a method of operating the output buffer.

2. Description of the Related Art

Liquid crystal display (LCD) devices generally are smaller, thinner, and require less power than the other types of conventional display devices. Accordingly, LCD devices are applied to electronic apparatuses such as notebook computers and mobile phones, for example. In particular, active matrix type LCD devices that use thin film transistors (TFTs) as switch devices are suitable for moving image displays.

FIG. 1is a block diagram of a conventional LCD device100. Referring toFIG. 1, the LCD device100includes an LCD panel110, a gate driver circuit120, and a source driver circuit200.

The gate driver circuit120generates a plurality of signals G1, G2, . . . , Gp for driving a plurality of gate lines GL arranged on the LCD panel110. The source driver circuit200generates source line driving signals S1, S2, . . . , Sm for driving a plurality of source lines SL arranged on the LCD panel110. The source lines are also referred to as data lines or channels.

The LCD panel110includes a plurality of pixels111. Each of the pixels111includes a switch transistor TFT and a liquid crystal capacitor CLC. The switch transistor TFT is turned on or off in response to a signal that drives the gate line GL, and a source terminal of the switch transistor TFT is connected to the source line SL. The liquid crystal capacitor CLC is connected between a drain terminal of the switch transistor TFT and a source of common voltage VCOM. For example, the common voltage VCOM may transition from logic high to logic low (or from logic low to logic high) for every horizontal scan period.

FIG. 2is a circuit diagram of the source driver circuit200illustrated inFIG. 1. Referring toFIG. 2, the conventional source driver circuit200includes a polarity inversion circuit210, a latch circuit220, a gray-scale voltage generator230, a gamma decoder circuit240, an output buffer circuit250, a plurality of first switches260, a plurality of second switches270, an intermediate voltage generator280, and a capacitor290.

The polarity inversion circuit210includes a plurality of exclusive OR (XOR) gates. The polarity inversion circuit210receives a plurality of pieces of n-bit image data D1[n:1], D2[n:1], . . . , Dm[n:1]. The polarity inversion circuit210may or may not invert image data D1[n:1], D2[n:1], . . . , Dm[n:1], in response to a polarity control signal M.

The latch circuit220includes a plurality of D latches. The latch circuit220latches data received from the polarity inversion circuit210and outputs the latched data in response to a latch control signal S_LATCH.

The gray-scale voltage generator230generates 2nanalog gray-level voltages VG and applies them to the gamma decoder circuit240.

The gamma decoder circuit240includes a plurality of gamma decoders. Each of the gamma decoders selects one of the 2nanalog gray-level voltages VG, which corresponds to an output digital value of the corresponding D latch included in the latch circuit220, and then outputs the selected analog gray-level voltage VG.

The output buffer circuit250includes a plurality of output buffers301,302, . . . ,30m. Each of the output buffers301,302, . . . ,30muses a boosted voltage AVDD and ground voltage VSS for supply of power. The boosted voltage AVDD is generated using supply voltage VDD applied from the outside of the source driver circuit200. The output buffers amplify analog image signals received from the gamma decoders and supply the amplified analog image signals A1, A2, . . . , Am to the first switches260, respectively.

The first switches260respectively supply the amplified analog image signals A1, A2, . . . , Am as the source line driving signals S1, S2, . . . , Sm in response to an activated control signal GRAY_ON. The source line driving signals S1, S2, . . . , Sm are supplied to equivalent load capacitance Ceq connected to the source lines of the LCD device100illustrated inFIG. 1.

The intermediate voltage generator280receives an intermediate gray-level voltage VGC from among the 2nanalog gray-level voltages VG generated by the gray-scale voltage generator230, and generates intermediate voltage VCI using the supply voltage VDD applied from the outside of the source driver circuit200. The intermediate voltage VCI is applied to the second switches270.

Each of the second switches270outputs the intermediate voltage VCI received from the intermediate voltage generator280as one of the source line driving signals S1, S2, . . . , Sm in response to an activated charge recycling signal CR_ON. The source line driving signals S1, S2, . . . , Sm precharge the source lines SL of the LCD device100to the intermediate voltage VCI.

The charge recycling signal CR_ON may be an inverted signal of the output control signal GRAY_ON. Since the charge recycling signal CR_ON is activated before the output control signal GRAY_ON is activated, the intermediate voltage VCI is applied to the source line SL before each of the amplified analog image signals A1, A2, . . . , Am is supplied to the corresponding equivalent load capacitance Ceq connected to the source line SL.

The capacitor290stabilizes the intermediate voltage VCI, thus reducing and/or preventing oscillation of the intermediate voltage VCI. Also, whenever the second switch270is activated (or is closed), the capacitor290may be supplied with electric charges stored in a source line SL having a voltage greater than the intermediate voltage VCI and supply the electric charges to a source line SL having a voltage less than the intermediate voltage.

The conventional source driver circuit200includes source drivers that generate the source line driving signals S1, S2, . . . , Sm. Each of the source drivers includes the XOR gate, the D latch, the gamma decoder, the output buffer, the first switch260, and the second switch270.

The digital image data D1[n:1], D2[n:1], . . . , Dm[n:1], the polarity control signal M, the latch control signal S_LATCH, the output control signals GRAY_ON, and the charge recycling signals CR_ON may be generated by a timing controller (not shown) included in the LCD100. The timing controller controls the operation timing of the source driver circuit200.

The second switches270, the intermediate voltage generator280, and the capacitor290control the source driver circuit200to perform a charge recycling operation. In the charge recycling operation, the voltage of a source line driving signal does not transition from a high voltage directly to a low voltage or from the low voltage directly to the high voltage. Instead, the voltage of the source line driving signal transitions from the high voltage to the intermediate voltage VCI and then to the low voltage. The intermediate voltage VCI is a voltage having a value between the high voltage and low voltage. Alternatively, the voltage of the source line driving signal transitions from the low voltage to the intermediate voltage and then to the high voltage. The charge recycling operation reduces the consumption of power in the output buffer circuit250.

FIG. 3is a timing diagram illustrating an operation of the conventional source driver illustrated inFIG. 2. The operation of the source driver will now be described with reference toFIGS. 2 and 3.

Referring toFIG. 3, a polarity control signal M is toggled in time duration units of horizontal scan periods HP.

A latch control signal S_LATCH that transitions to a high value during the horizontal scan period HP causes an amplified analog image signal Am to be generated by the output buffer30m. The polarity of the amplified analog image signal Am may or may not be inverted based on the logic state of the inverted control signal M. The amplified analog image signal Am may be data that swings the full degree between a high voltage VH and a low voltage VL, such as black image data.

In a charge recycling period RP in which a charge recycling signal CR_ON is activated to logic high and thus the second switch270is short-circuited, an intermediate voltage VCI is applied to a source line connected to the second switch270. Then, a source line driving signal Sm transitions from the high voltage to the intermediate voltage VCI or from the low voltage VL to the intermediate voltage VCI.

In a driving period DP in which an output control signal GRAY_ON is activated to logic high and thus the first switch260is short-circuited, the amplified analog image signal Am is applied to the source line connected to the first switch260. Then, the source line driving signal Sm transitions from the intermediate voltage VCI to the low voltage VL (image data having a logic “low” level) or from the intermediate voltage VCI to the high voltage VH (image data having a logic “high” level).

FIG. 4is a circuit diagram illustrating in greater detail the output buffer30millustrated inFIG. 2. Referring toFIG. 4, the output buffer30mincludes a first input stage310, a second input stage320, and an output stage330.

The output buffer30mis a differential amplifier having a voltage follower configuration in which an amplified analog image signal Am output from the output buffer30mis fed back to the first input stage310as an inverted input signal which is one of input signals input to the first input stage310.

A plurality of first bias current sources311drive the first input stage310. A second bias current source321drives the second input stage320, and a bias voltage322of the second input stage320controls quiescent current IB3flowing through the output stage330to be generated. The quiescent current (direct current) IB3is current in a steady state. The steady state refers to a state in which the voltage of an input signal IN supplied to the output buffer30mis equal to the voltage of the amplified analog image signal Am fed back to the first input stage310. The input signal IN supplied to the output buffer30mis received from the gamma decoder of the gamma decoder circuit240illustrated inFIG. 2.

The slew rate SR of the amplified analog image signal Am output from the output buffer30msatisfies the following:
SR∝(IB1/CC)  (1),
wherein IB1denotes the amount of current of the first bias current source311included in the first input stage310, and CC denotes the capacitance of a compensation capacitor331included in the output stage330.

The phase margin of the amplified analog image signal Am may be determined by the poles P1and P2of the transfer functions expressed in following Equations (2) and (3):
P1∝CC  (2)
P2∝(IB3/Ceq)  (3)
Here, the greater the values of the poles P1and P2, the greater the phase margin of the amplified analog image signal Am and the higher the stability of the amplified analog image signal Am.

Referring toFIG. 3, the amplified analog image signal Am must transition to the low voltage VL (or the high voltage VH) before the end of the charge recycling period RP, so that the source line driving signal Sm can rapidly transition to the low voltage VL (or the high voltage VH), whichever is a target voltage in the driving period DP. Thus, in the charge recycling period RP, the slew rate of the amplified analog image signal Am must be increased. If the capacitance CC of the compensation capacitor331expressed in Equation (1) decreases, the stability of the output buffer30malso decreases as expressed in Equation (2), and therefore, the amount of the current IB1in Equation (1) must be increased in order to increase the slew rate of the amplified analog image signal Am. Also, the slew rate of the amplified analog image signal Am may increase in proportion to the amount of current of the second bias current source321of the second input stage320, and therefore, the amount of current IB2of the second bias current source321must also be increased.

In the driving period DP, the equivalent load capacitance Ceq that has a comparatively large load is connected to an output of the output buffer30m. Thus, if it is assumed that the capacitance CC of the compensation capacitor331is fixed in order to maintain the sufficient phase margin of the amplified analog image signal Am, the amount of the quiescent current IB3expressed in Equation (3) must be increased.

As described above, the amount of the driving currents IB1, IB2, and IB3flowing through the output buffer30mincreases so that the output buffer30mcan normally operate in the charge recycling period RP and the driving period DP. Therefore, a conventional output buffer30mmay lead to comparatively large power consumption.

SUMMARY

Example embodiments provide a source driver in a liquid crystal display (LCD) device, which is capable of reducing power consumption, an output buffer included in the source driver, and a method of operating the output buffer.

An example embodiment provides an output buffer included in a source driver of an LCD (liquid crystal display) device. The output buffer may include a differential amplification unit generating control currents by amplifying the difference between voltages of an analog image signal and a signal output from the output buffer, and an output unit outputting a signal obtained by amplifying the analog image signal in response to the control currents. The amount of a bias current for driving the differential amplification unit increases and the amount of a quiescent current flowing through the output unit decreases during a charge recycling period in which a source line of the LCD device is precharged to a precharge voltage. The amount of the bias current for driving the differential amplification unit decreases and the amount of the quiescent current flowing through the output unit increases during a driving period in which the amplified analog image signal is supplied to the source line after the source line is precharged.

According to an example embodiment, the differential amplification unit may be a folded cascade operational transconductance amplifier, and the precharge voltage may be half a maximum gray-level voltage of the analog image signal.

Another example embodiment provides an output buffer included in a source driver of an LCD (liquid crystal display) device. The output buffer may include a differential input unit generating first control currents by amplifying the difference between voltages of an analog image signal and a signal output from the output buffer, a gain unit generating second control currents by adding the first control currents together, and an output unit outputting a signal obtained by amplifying the analog image signal in response to the second control currents. The amounts of bias currents that respectively drive the differential input unit and the gain unit increase and the amount of a quiescent current flowing through the output unit decreases during a charge recycling period in which a source line of the LCD device is precharged to a precharge voltage. The amounts of the bias currents that respectively drive the differential input unit and the gain unit decrease and the amount of the quiescent current flowing through the output unit increases during a driving period in which the amplified analog image signal is supplied to the source line after the source line is precharged.

According to an example embodiment, the differential input unit may include a first bias current source connected to a source of first voltage and providing bias current in the differential input unit during the charge recycling period, a second bias current source connected to a source of second voltage and providing the bias current in the differential input unit during the charge recycling period, a third bias current source connected to the source of first voltage and providing the bias current in the differential input unit during the driving period, and a fourth current source connected to the source of second voltage and providing the bias current in the differential input unit during the driving period. The amount of currents in the first and second bias current sources is greater than the amount of currents in the third and fourth bias current sources.

According to an example embodiment, the differential input unit may further include first and second input transistors receiving the analog image signal and the signal output from the output buffer, and generating the first control currents; a first switch one of connecting the first input transistors to the first bias current source in response to a charge recycling signal indicating the charge recycling period and disconnecting the first input transistors from the first bias current source in response to the charge recycling signal; a second switch one of connecting the second input transistors to the second bias current source in response to the charge recycling signal and disconnecting the second input transistors from the second bias current source in response to the charge recycling signal; a third switch one of connecting the first input transistors to the third bias current source in response to a driving signal indicating the driving period and disconnecting the first input transistors from the third bias current source in response to a driving signal indicating the driving period; and a fourth switch one of connecting the second input transistors to the fourth bias current source in response to the driving signal and disconnecting the second input transistors from the fourth bias current source in response to the driving signal. The driving signal may be an inverted signal of the charge recycling signal.

According to an example embodiment, the gain unit may include a first floating current source providing bias current in the gain unit during the charge recycling period; a second floating current source providing the bias current in the gain unit during the driving period; a first floating voltage source controlling quiescent current to be generated in the output unit during the charge recycling period; and a second floating voltage source controlling quiescent current to be generated in the output unit during the driving period. The amount of current in the first floating current source is greater than the amount of current in the second floating current source, and a voltage of the first floating voltage source is greater than a voltage of the second floating voltage source.

According to an example embodiment, the gain unit may further include a first current mirror circuit receiving a first differential current signal from among the first control currents, the first current mirror circuit being connected to a source of first voltage; a second current mirror circuit receiving a second differential current signal from among the first control currents, the second current mirror circuit being connected to a source of second voltage; a first switch connecting the first current mirror circuit to the second current mirror circuit in response to a charge recycling signal indicating a charge recycling period or disconnecting the first current mirror circuit from the second current mirror circuit in response to the charge recycling signal; a second switch connecting the first current mirror circuit to the second current mirror circuit in response to a driving signal indicating a driving period or disconnecting the first current mirror circuit from the second current mirror circuit in response to the driving signal; a third switch connecting the first current mirror circuit to the second current mirror circuit in response to the charge recycling signal or disconnecting the first current mirror circuit from the second current mirror circuit in response to the charge recycling signal; and a fourth switch connecting the first current mirror circuit to the second current mirror circuit in response to the driving signal or disconnecting the first current mirror circuit from the second current mirror circuit in response to the driving signal. The first floating current source is connected between the first switch and the second current mirror circuit; the second floating current source is connected between the second switch and the second current mirror circuit; the first floating voltage source is connected between the third switch and the second current mirror circuit; and the second floating voltage source is connect between the fourth switch and the second current mirror circuit. The first current mirror circuit and the second current mirror circuit form a current summing circuit, and generate second control currents for driving the output unit. The first current mirror circuit and the second current mirror circuit may form a current summing circuit, and generate second control currents for driving the output unit.

Another example embodiment provides an output buffer included in a source driver of an LCD (liquid crystal display) device. The output buffer may include a differential input unit generating first control currents by amplifying the difference between voltages of an analog image signal and a signal output from the output buffer; a gain unit generating second control currents by adding the first control currents together; and an output unit outputting a signal obtained by amplifying the analog image signal in response to the second control currents. The differential input unit includes first and second bias current sources having a first amount of current during a charge recycling period in which a source line of the LCD device is precharged to a precharge voltage; and third and fourth bias current sources having a second amount of current during a driving period in which the amplified analog image signal is supplied to the source line after the source line is precharged. The second amount of current is less than the first amount of current. The gain unit includes a first floating current source which drives the gain unit and has a third amount of current during the charge recycling period; a second floating current source which drives the gain unit and has a fourth amount of current during the driving period, the fourth amount of current is less than the third amount of current; a first floating voltage source that controls first quiescent current to be generated in the output unit and has a first voltage during the charge recycling period; and a second floating voltage source which controls second quiescent current to be generated in the output unit and has a second voltage during the driving period, where the second voltage is less than the first voltage. The amount of the first quiescent current is less than the amount of the second quiescent current.

Another example embodiment provides a method of operating an output buffer included in a source driver of an LCD (liquid crystal display) device. The method may include generating control currents by amplifying the difference between voltages of an analog image signal and the output buffer; outputting a signal obtained by amplifying the analog image signal in response to the control currents; increasing the amount of bias current for driving a differential amplification unit included in the output buffer and reducing the amount of quiescent current flowing through an output unit included in the output buffer during a charge recycling period in which a source line of the LCD device is precharged to a precharge voltage; and reducing the amount of the bias current for driving the differential amplification unit and increasing the amount of the quiescent current flowing through the output unit during a driving period in which the amplified analog image signal is supplied to the source line after the source line is precharged.

Still another example embodiment provides a method of operating an output buffer included in a source driver of an LCD (liquid crystal display) device. The method may include generating first control currents by amplifying the difference between voltages of an analog image signal and a signal output from the output buffer; generating second control currents by adding the first control currents together; outputting a signal obtained by amplifying the analog image signal in response to the second control currents; increasing the amount of bias currents that respectively drive a differential input unit and a gain unit included in the output buffer and reducing the amount of quiescent current flowing through an output unit included in the output buffer during a charge recycling period in which a source line of the LCD device is precharged to a precharge voltage; and reducing the amount of the bias currents that respectively drive the differential input unit and the gain unit and increasing the amount of the quiescent current flowing through the output unit during a driving period in which the amplified analog image signal is supplied to the source line after the source line is precharged.

Another example embodiment provides a source driver of an LCD (liquid crystal display) device. The source driver may include a gamma decoder transforming a digital image signal into an analog image signal and outputting the analog image signal; and an output unit amplifying and outputting the analog image signal. The amount of bias current for driving a differential amplification unit included in the output buffer increases and the amount of quiescent current flowing through an output unit included in the output buffer decreases during a charge recycling period in which a source line of the LCD device is precharged to a precharge voltage, and the amount of the bias current for driving the differential amplification unit decreases and the amount of the quiescent current flowing through the output unit increases during a driving period in which the amplified analog image signal is supplied to the source line after the source line is precharged.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Various example embodiments will now be described more fully with reference to the accompanying drawings. However, specific structural and functional details disclosed herein are merely representative for purposes of describing example embodiments, and one skilled in the art will appreciate that example embodiments may be embodied in many alternate forms and should not be construed as limited to only the example embodiments set forth herein.

Example embodiments described below with respect to the drawings are provided so that this disclosure will be thorough, complete and fully convey the concept of example embodiments to those skilled in the art. In the drawings, like numbers refer to like elements throughout.

FIG. 5is a circuit diagram of a source driver circuit400according to an embodiment of the present application.

Referring toFIG. 5, the source driver circuit400may include a polarity inversion circuit410, a latch circuit420, a gray-scale voltage generator430, a gamma decoder circuit440, an output buffer circuit450, a plurality of first switches460, a plurality of second switches470, an inverter480, an intermediate voltage generator490, and a capacitor495.

A polarity inversion circuit410may include a plurality of XOR gates, for example. InFIG. 5, the polarity inversion circuit410receives a plurality of pieces of n-bit image data D1[n:1], D2[n:1], . . . , Dm[n:1]. The polarity inversion circuit410may or may not invert n-bit image data D1[n:1], D2[n:1], . . . , Dm[n:1] in response to an inverted control signal M.

A latch circuit420may include a plurality of latches, such as the D latches shown inFIG. 5, for example. The latch circuit420may latch data received from the polarity inversion circuit410and output the latched data in response to latch control signal S_LATCH, for example.

A gray-scale voltage generator430may generate 2nanalog gray-level voltages VG and output them to the gamma decoder circuit440.

A gamma decoder circuit440may include a plurality of gamma decoders. Each of the gamma decoders selects one of 2nanalog gray-level voltages VG, which corresponds to an output digital value of the corresponding D latch included in the latch circuit420, and then outputs the selected analog gray-level voltage VG. That is, each gamma decoder transforms a digital image signal into an analog image signal and outputs the analog image signal.

Still referring toFIG. 5, an output buffer circuit450may include a plurality of output buffers501,502, . . . ,50m. InFIG. 5, each of the output buffers501,502, . . . ,50muses a boosted voltage AVDD and a ground voltage VSS as a power source. The boosted voltage AVDD may be generated from a supply voltage VDD applied from the outside of the source driver circuit400. Each of the output buffers501,502, . . . ,50mamplifies an analog image signal received from the corresponding gamma decoder and then transmits one of the amplified analog image signals A1, A2, . . . , Am to the corresponding first switch460.

According to an example embodiment, each of the output buffers501,502, . . . ,50moperates in response to a charge recycling signal CR_ON and an inverted signal CR_ONB of the charge recycling signal CR_ON. The inverted signal CR_ONB of the charge recycling signal CR_ON is generated by the inverter480in the example embodiment ofFIG. 5. The construction and operation of an output buffer, e.g., the output buffer50m, which may reduce the consumption of power (or current), will be described in greater detail later with reference toFIG. 6.

A first switch460may output the received amplified analog image signal as one of source line driving signals S1, S2, . . . , Sm in response to an activated output control signal GRAY_ON. The source line driving signal may be supplied to an equivalent load capacitance Ceq connected to a source line of a liquid crystal display (LCD) device (not shown). The output control signal GRAY_ON may be the same as the inverted signal CR_ONB of the charge recycling signal CR_ON.

An intermediate voltage generator490may receive an intermediate gray-level voltage VGC of the 2nanalog gray-level voltages VG from the gray-scale voltage generator430, and generates the intermediate voltage VCI from the supply voltage VDD, which may be applied from the outside of the source driver circuit400. An intermediate voltage VCI equal to half the maximum gray-level voltage of the analog image signal is applied to the second switches470according to an example embodiment.

A second switch470may output the intermediate voltage VCI received from the intermediate voltage generator490as one of the source line driving signals S1, S2, . . . , Sm in response to the activated charge recycling signal CR_ON. The source line driving signal precharges the source line of the LCD device to the intermediate voltage VCI. The charge recycling signal CR_ON is activated before the output control signal GRAY_ON is activated, and thus, the intermediate voltage VCI is applied to the source line before the amplified analog image signal is supplied to the equivalent load capacitance Ceq connected to the source line.

In an example embodiment, the source line is precharged to the intermediate voltage VCI by using the intermediate voltage generator490. However, in another example embodiment, a voltage less than the intermediate voltage VCI and greater than a ground voltage VSS may be used as a precharge voltage of the source line, using one of the 2nanalog gray-level voltages VG generated by the gray-scale voltage generator430, for example.

A capacitor495stabilizes the intermediate voltage VCI, thus reducing and/or preventing oscillation of the intermediate voltage VCI. Also, if the second switch470is activated or short-circuited, the capacitor495may be supplied with electric charges of a source line having a voltage greater than the intermediate voltage VCI and then supply the electric charges to a source line having a voltage less than the intermediate voltage VCI.

A source driver circuit400includes source drivers that generate the source line driving signals S1, S2, . . . , Sm. Each of the source drivers may include an XOR gate, a D latch, a gamma decoder, an output buffer, a first switch460, and a second switch470.

Second switches470, an intermediate voltage generator490, and a capacitor495control the source driver circuit400to perform a charge recycling operation. During the charge recycling operation, the source line driving signal does not transition from a high voltage directly to a low voltage, and or from the low voltage directly to the high voltage. Instead, the voltage of the source line driving signal transitions from the high voltage to an intermediate voltage and then from the intermediate voltage to the low voltage. The intermediate voltage is a voltage with a value between the low voltage and high voltage. Alternatively, the value of the source line driving signal transitions from the low voltage to the intermediate voltage and then from the intermediate voltage to the high voltage. The charge recycling operation reduces the consumption of power in the output buffer circuit450.

In one example embodiment, the operation of the source driver may be similar to that of the source driver illustrated inFIG. 3. For example, the source driver operates in time duration units of a charge recycling period RP and a driving period DP. An example construction and operation of an example embodiment of an output buffer50mwill be described with reference toFIGS. 3 and 5.

During a charge recycling period RP in which the charge recycling signal CR_ON is activated to logic high and thus the second switch470is short-circuited (the output control signal GRAY_ON is deactivated to logic low and thus the first switch460is opened), a slew rate of an amplified analog image signal Am must be increased as previously described with reference toFIG. 3. Also, during the charge recycling period RP, the output buffer50mhas a comparatively low parasitic load since the output of the output buffer50mis not supplied to the equivalent load capacitance Ceq. The charge recycling period RP is a period where each source line of the LCD device is precharged to a precharge voltage.

During a driving period DP in which the output control signal GRAY_ON (or the inverted signal CR_ONB of the charge recycling signal CR_ON) is activated to logic high and the first switch460is short-circuited, the voltage of the amplified analog image signal Am has already been maintained at a target voltage and thus, the slew rate of the amplified analog image signal Am need not be increased. Also, during the driving period DP, the output buffer50mhas a comparatively high load since the output of the output buffer50mis supplied to the equivalent load capacitance Ceq. The driving period DP is a period in which the source line is precharged and then the amplified analog image signal Am is supplied to the source line.

In order to satisfy the above slew rate condition during the charge recycling period RP and the driving period DP, the amount of bias current for driving a differential amplification unit (input stage) included in the output buffer50mincreases during the charge recycling period RP but decreases during the driving period DP. The amount of current in the differential amplification unit may correspond to the amount of current IB1expressed in Equation (1) and the amount of current IB2of the second input stage320illustrated inFIG. 4.

Also, in order to maintain sufficient phase margin of the amplified analog image signal Am according to the load condition during the charge recycling period RP and the driving period DP, the amount of quiescent current flowing through an output unit (output stage) included in the output buffer50mdecreases during the charge recycling period RP and increases during the driving period DP. The amount of the quiescent current flowing through the output unit may correspond to the quiescent current IB3expressed in Equation (3).

In summary, during the charge recycling period RP, the amount of bias current for driving the differential amplification unit of the output buffer50mincreases and the amount of quiescent current flowing through the output unit of the output buffer50mdecreases. Further, during the driving period DP, the amount of bias current for driving the differential amplification unit of the output buffer50mdecreases and the amount of quiescent current flowing through the output unit of the output buffer50mincreases.

Thus, according to an example embodiment, the output buffer50mis capable of separately controlling the amount of the bias current (operating current) in the output buffer50mboth during the charge recycling period RP and the driving period DP. As a result, the amount of current consumed in an example embodiment of an output buffer50mmay be significantly less than the amount of current in the conventional output buffer30mofFIG. 4, which increases during both the charge recycling period RP and the driving period DP.

As described above, the output buffer50mmay be controlled by the charge recycling signal CR_ON used in source driver circuit400. A source driver according to an example embodiment of the present application does not require an additional control signal in order to control the output buffer50m.

FIG. 6is a circuit diagram illustrating in greater detail the output buffer50millustrated inFIG. 5according to an embodiment of the present application. Referring toFIG. 6, the output buffer50mincludes a differential input unit600, a gain unit700, and an output unit800.

The output buffer50mmay be a differential amplifier having a voltage follower structure in which the amplified analog image signal Am output from the output buffer50mis fed back to the differential input unit600as an inverted input signal according to an example embodiment. Accordingly, the inverted input signal is one of a plurality of input signals supplied to the output buffer50m. The output buffer50mmay be embodied as a rail-to-rail operational amplifier, for example.

Together, the differential input unit600and the gain unit700form the above described differential amplification unit. The differential amplification unit may be a folded cascade operational transconductance amplifier (OTA), for example.

According to an example embodiment, the differential amplification unit generates control currents IC12and IC22by amplifying the difference between the voltages of an analog image signal IN (input signal) supplied to the output buffer50mand the signal Am output from the output buffer50m. The analog image signal may be received from the gamma decoder of the gamma decoder circuit440illustrated inFIG. 5, for example.

The differential input unit600generates first control currents IC11, IC21, IIC31, and IC41by amplifying the difference between the voltages of the analog image signal IN and the signal Am output from output buffer50m.

The differential input unit600may include a plurality of first input transistors605,608, a plurality of second input transistors606,607, a first bias current source601, a second bias current source611, a third bias current source602, a fourth bias current source612, a first switch603, a second switch609, a third switch604, and a fourth switch610as shown inFIG. 6, for example.

Referring toFIG. 6, the first bias current source601is connected to a source of boosted voltage AVDD (first voltage) and the second bias current source611is connected to a source of ground voltage VSS (second voltage). The first and second bias current sources601and611supply bias current of the differential input unit600during the charge recycling period RP according to an example embodiment.

Still referring toFIG. 6, the third bias current source602is connected to the source of boosted voltage AVDD, and the fourth bias current source612is connected to the source of ground voltage VSS. The third and fourth bias current sources602and612supply bias current of the differential input unit600during the driving period DP according to an example embodiment.

The amounts of current in the first and second bias current sources601,611are greater than those of current in the third and fourth bias current sources602and612. As illustrated inFIG. 6, the amount of current IB1L in the first bias current source601may be equal to the amount of current IB1L in the second bias current source611, and the amount of current IB1S in the third bias current source602may be equal to the amount of current IB1S in the fourth bias current source612.

The first input transistors605and608and the second input transistors606and607may receive the analog image signal IN and the signal Am output from the output buffer50m, and may generate the first control currents IC11, IC21, IC31, and IC41. The first input transistors605and608may be PMOS transistors, and the second input transistors606and607may be NMOS transistors. For example, as shown inFIG. 6, the first input transistor605and the second input transistor606receive the analog image signal IN, whereas the first input transistor608and the second input transistor607receive the signal Am output from the output buffer50m.

The first switch603connects the source terminals of the first bias current source601to both of the first input transistors605and608in response to a charge recycling signal CR_ON or disconnects the source terminals of the first bias current source601from both of the first input transistors605and608in response to the charge recycling signal CR_ON. The charge recycling signal CR_ON indicates the charge recycling period RP. The second switch609connects the source terminals of the second bias current source611to both of the second input transistors606and607in response to the charge recycling signal CR_ON or disconnects the source terminals of the second bias current source611from both of the second input transistors606and607in response to the charge recycling signal CR_ON.

The third switch604connects the source terminals of the third bias current source602to both of the first input transistors605and608in response to a driving signal CR_ONB or disconnects the source terminals of the third bias current source602from both of the first input transistors605and608in response to a driving signal CR_ONB. The driving signal CR_ONB may indicate the driving period DP. The fourth switch610connects the source terminals of the fourth bias current source612to both of the second input transistors606and607in response to the driving signal CR_ONB or disconnects the source terminals of the fourth bias current source612from both of the second input transistors606and607in response to the driving signal CR_ONB. The driving signal CR_ONB may be an inverted signal of the charge recycling signal CR_ON, and may be the same as the output control signal GRAY_ON.

Still referring toFIG. 6, the gain unit700may add the first control currents IC11, IC21,11C31, and IC41together to generate the second control currents IC12and IC22. InFIG. 6, the gain unit700includes a first current mirror circuit720, a second current mirror circuit740, a first floating current source709, a second floating current source710, a first floating voltage source712, a second floating voltage source711, a fifth switch705, a sixth switch706, a seventh switch708, and an eighth switch707.

The first floating current source709may supply bias current of the gain unit700to drive one or more of the first current mirror circuit720, the second current mirror circuit740, and the first floating voltage source712during the charge recycling period RP. The second floating current source710may supply bias current of the gain unit700to drive one or more of the first current mirror circuit720, the second current mirror circuit740, and the second floating voltage source711during the driving period DP. According to an example embodiment, first floating current source709supplies bias current of the gain unit700to drive the first current mirror circuit720, the second current mirror circuit740, and the first floating voltage source712during the charge recycling period RP. Further, the second floating current source710supplies bias current of the gain unit700to drive one or more of the first current mirror circuit720, the second current mirror circuit740, and the second floating voltage source711during the driving period DP. The amount of current IB2L in the first floating current source709is greater than that of current IB2L in the second floating current source710according to an example embodiment.

In the example embodiment ofFIG. 6, the first floating voltage source712controls quiescent current IB3S to be generated in the output unit800during the charge recycling period RP. The second floating voltage source711controls quiescent current IB3L to be generated in the output unit800during the driving period DP. The voltage VBL of the first floating voltage source712is greater than the voltage VBS of the second floating voltage source711according to an example embodiment. Thus, the amount of the quiescent current IB3S generated by the first floating voltage source712is less than that of the quiescent current IB3L generated by the second floating voltage source711.

The first current mirror circuit720receives first differential current signals IC11and IC21from among the first control currents IC11, IC21, IC31, and IC41from the differential input unit600, and is connected to the source of boosted voltage AVDD. The first current mirror circuit720may include transistors. For example, the first current mirror circuit720shown inFIG. 6includes PMOS transistors701,702,703, and704. A bias voltage VB1may be applied to the gates of the PMOS transistors703and704, for example.

Referring toFIG. 6, the second current mirror circuit740shown inFIG. 6receives second differential current signals IC31, IC41from among the first control currents IC11, IC21, IC31, and IC41from the differential input unit600, and is connected to the source of ground voltage VSS. The second current mirror740includes transistors. For example, the second current mirror circuit740includes NMOS transistors713,714,715, and716. The bias voltage VB2may be applied to the gates of the NMOS transistors713and714.

Together, the first current mirror circuit720and the second current mirror circuit740form a current summing circuit, and respectively generate the second control currents IC12and IC22for driving output unit800.

The fifth switch705connects the first current mirror circuit720and the second current mirror circuit740via the first floating current source709in response to the charge recycling signal CR_ON or disconnects the first current mirror circuit720and the second current mirror circuit740from each other, via the first floating current source709, in response to the charge recycling signal CR_ON. The sixth switch706connects the first current mirror circuit720and the second current mirror circuit740in response to the driving signal CR_ONB or disconnects the first current mirror circuit720and the second current mirror circuit740from each other in response to the driving signal CR_ONB. The second floating current source710is connected between the second floating current mirror circuit740and the sixth switch706.

The seventh switch708connects the first current mirror circuit720and the second current mirror circuit740in response to the charge recycling signal CR_ON, or disconnects the first current mirror circuit720and the second current mirror circuit740in response to the charge recycling signal CR_ON. The first floating voltage source712is connected between the seventh switch708and the second current mirror circuit740. The eighth switch707connects the first current mirror circuit720and the second current mirror circuit740in response to the driving signal CR_ONB or disconnects the first current mirror circuit720from the first current mirror circuit740in response to the driving signal CR_ONB. The second floating voltage source711is connected between the eight switch707and the second current mirror circuit740.

According to an example embodiment, the output unit800outputs the signal Am obtained by amplifying the analog image signal IN in response to the control currents IC12and IC22.

Referring toFIG. 6, the output unit800includes a PMOS transistor801, an NMOS transistor802, and a plurality of compensation capacitors. The source of the PMOS transistor801is connected to the source of boosted voltage AVDD, and the source of the NMOS transistor802is connected to the source of ground voltage VSS. The compensation capacitors CC1and CC2are connected between an output node NO for outputting the amplified analog image signal Am and the gain unit700. The compensation capacitors CC1and CC2are capable of preventing or reducing oscillation of the amplified analog image signal AM.

An example embodiment of the output buffer50msuch as the one shown inFIG. 6may include the first through fourth bias current sources601,611,602, and612, the first and second floating current sources709and710, and the first and second floating voltage sources712and711. According to an example embodiment, in the charge recycling period RP, the output buffer50mincreases the amounts of bias currents that respectively drive the differential input unit600and the gain unit700and reduces the amount of quiescent current flowing through the output unit800. Also, in the driving period DP, the output buffer50mreduces the amounts of bias currents that respectively drive the differential input unit600and the gain unit700and increases the amount of quiescent current flowing through the output unit800. That is, an, example embodiment of an output buffer50mis capable of reducing the amount of quiescent current in the charge recycling period RP and the amounts of bias currents that drive the differential input unit and the gain unit in the driving period DP, thereby reducing the consumption of power in the output buffer50m.

FIG. 7is a timing diagram illustrating the operation of the source driver illustrated inFIG. 5, according to an embodiment of the present application. The operation of the source driver is described below with reference toFIGS. 5 through 7.

Referring toFIG. 7, an inverted control signal M is toggled in time duration units of horizontal scan periods HP. A latch control signal S_LATCH that is activated to logic high during a portion of the horizontal scan period HP causes an amplified analog image signal Am to be generated by the output buffer50m. The polarity of the amplified analog image signal Am may or may not be inverted based on the logic state of the inverted control signal M. The amplified analog image signal Am may be data, such as black image data, which swings to the full degree between a high voltage VH and a low voltage VL.

An intermediate voltage VCI is applied to a source line connected to the second switch470in a charge recycling period RP in which a charge recycling signal CR_ON is activated to logic high and thus the second switch470is short-circuited. Then, a source line driving signal Sm transitions from the high voltage VH to the intermediate voltage VCI or from the low voltage VL to the intermediate voltage VCI. The intermediate voltage VCI is a voltage level between the high voltage VH and the low voltage VL.

The amplified analog image signal Am is supplied to a source line connected to the first switch460in a driving period DP in which an output control signal GRAY_ON is activated to logic high and thus the first switch460is short-circuited. Then, the source line driving signal Sm transitions from the intermediate voltage VCI to the low voltage VL (image data of a logic “low” level) or from the intermediate voltage VCI to the high voltage VH (image data of a logic “high” level).

In the charge recycling period RP, the amount of bias current IBI1that drives the differential input unit600increases to IB1L and the amount of bias current IB12that drives the gain unit700increases to IB2L. Also, as the voltage VBI of the floating voltage source included in the gain unit700increases to VBL, the amount of quiescent current IB13flowing through the output unit800decreased to IB3S.

In the driving period RP, the amount of bias current IBI1that drives the differential input unit600decreases to IB1S, which is less than IB1L, and the amount of bias current IB12that drives the gain unit700decreases to IB2S, which is less than IB2L. Further, as the voltage VBI of a floating voltage source included in the gain unit700decreases to VBS, which is less than VBL, the amount of quiescent current IB13flowing through the output unit800increases to IB3L, which is greater than IB3S.

An output buffer included in a source driver of an LCD device and a method of operating the output buffer an according to example embodiments of the present application are capable of individually controlling the amount of internal bias current in a charge recycling period and a driving period, thereby reducing the consumption of power (current). Also, according to example embodiments, the output buffer and the method of operating the same are controlled by a charge recycling signal used in a source driver circuit, and do not use and/or require an additional control signal for controlling the output buffer. Since the source driver of the LCD device according to example embodiments of the present application include the output buffer, the consumption of power in the source driver can be reduced. Accordingly, the source drive can be applied to LCD devices for use in portable devices.

While example embodiments of the present application have been particularly shown with reference to the drawings and described above, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present application.