Electronic circuit

An electronic circuit is obtained that has reduced EMI levels. The circuit includes an integrated circuit, which is a source of noise, a bypass capacitor, and a circuit substrate on which they are mounted. An electronic circuit one electrode terminal of the bypass capacitor and one connecting electrode of the integrated circuit are connected through a first wire interconnect formed in the circuit substrate, and, additionally, another electrode terminal of the bypass capacitor and another connecting electrode of the integrated circuit are connected through a second wire interconnect, and the gap between the first wire interconnect and the second wire interconnect is made smaller than either the gap between the one connecting electrode and the other connecting electrode on the integrated circuit or the gap between the one electrode terminal and the other electrode terminal of the bypass capacitor.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an electronic circuit that suppresses electromagnetic noise emissions from integrated circuits, and, in particular, relates to an electronic circuit that is capable of meeting stricter standards for the suppression of electromagnetic noise emissions.

2. Description of Related Art

A variety of integrated circuits (ICs, LSI chips, etc.) imparted with microcomputer and logic circuit functionalities have been used as the basic components of various electronic and information devices. During the operation of such integrated circuits as active devices, their power consumption does not remain constant and varies from moment to moment, thereby causing the power supply voltage of the power supply lines supplying drive voltage to the integrated circuits to fluctuate from instant to instant in response to variations in load. This voltage fluctuation leads to electromagnetic noise emissions (EMI) from the integrated circuit.

One method used to keep the emission of electromagnetic noise into the environment by such an integrated circuit during its operation in compliance with regulatory values involves in interposing a bypass capacitor between the power supply line of the integrated circuit and the ground. However, when electromagnetic noise emitted from a circuit operating at high frequencies, i.e. an integrated circuit, is suppressed by using a bypass capacitor, the impedance of the traces connected to the integrated circuit cannot be ignored and, therefore, the bypass capacitor has to be placed at a location in close physical proximity to the integrated circuit operating as an active device.

FIG. 9andFIG. 10illustrate the configuration of a conventional electronic circuit fitted with a bypass capacitor as a means for suppressing electromagnetic noise emissions.FIG. 9is an enlarged cross-sectional view of the main body of the conventional electronic circuit, andFIG. 10is an enlarged plan view of the main body. It should be noted thatFIG. 9shows a cross-sectional configuration of the portion shown by the arrow line x-x′ inFIG. 10.

As shown inFIG. 9, the conventional electronic circuit500includes an LSI chip used as an integrated circuit51, a circuit substrate53, and a bypass capacitor57.

The integrated circuit51is flip-chip mounted to the circuit substrate53through multiple bump electrodes52formed on one of its major surfaces,51a. Multiple electrode pads55are formed on the mounting surface53aof the circuit substrate53at locations corresponding to the locations of placement of the bump electrodes52of the integrated circuit51. In addition, device-mounting electrodes56, which are used for mounting the bypass capacitor57, are formed on the back surface53bof the circuit substrate, and the electrode pads55are connected to the device-mounting electrodes56by through wire interconnects54formed in the circuit substrate53. Electrode terminals58at both ends of the bypass capacitors57are connected to the second electrode pads56, thereby mounting the bypass capacitor57on the back surface53bof the circuit substrate53.

FIG. 10shows a planar configuration of the conventional electronic circuit500, as viewed from the back surface53bof the circuit substrate53, in other words, from the side used to mount the bypass capacitor57. It should be noted that, in order avoid overcomplicating the drawing, the first pad electrodes55and through wire interconnects54formed in the circuit substrate53have been omitted from the drawing.

As shown inFIG. 10, in the conventional electronic circuit500, multiple bypass capacitors57are placed on, and secured to, the back surface53bof the circuit substrate53such that the placement locations of the respective electrode terminals58correspond to the locations of formation of the bump electrodes52, which are aligned in a regular two-dimensional matrix configuration on the major surface of the integrated circuit51. Furthermore, in the conventional electronic circuit500, the respective bypass capacitors57are placed such that electric currents flow in the same direction in all of them, and, for this reason, the device-mounting electrodes56formed on the back surface53bof the circuit substrate53are formed in the shape of strips extending vertically inFIG. 10, with the electrode terminals58of the multiple bypass capacitors57connected to the strip-shaped device-mounting electrodes56.

As shown inFIG. 9andFIG. 10, in the conventional electronic circuit500, the bump electrodes52of the integrated circuit51and the electrode terminals58at both ends of the bypass capacitor57are placed such that they are in alignment in the thickness direction of the circuit substrate53together with the through wire interconnects54that provide a connection therebetween. Thus, in the conventional electronic circuit500, the bump electrodes52of the integrated circuit51and the electrode terminals58of the bypass capacitor57are connected across the narrowest distance via the through wire interconnects54of the circuit substrate53, which makes it possible for both of them to be placed in the closest physical proximity and prevents trace impedance from reducing the inhibiting effect on the high-frequency component of the electromagnetic radiation.

Furthermore, other disclosures of technologies for suppressing the emission of electromagnetic noise from integrated circuits using bypass capacitors have described a technology in which bypass capacitors are integrated into ICs in order to bring the integrated circuits and the bypass capacitors closer together (JP 2000-183286A), and a technology that makes use of bypass capacitors with different resonance frequencies, wherein the bypass capacitors are placed such that the closer they are to the power supply terminal, the lower their resonance frequency becomes (JP 2007-48879A).

In recent years, the magnitude of the supply currents required by LSI chips, ICs, and other integrated circuits has been on the increase. In addition, the regulatory values applicable to electromagnetic noise emissions (EMI) gradually have become more stringent due to concerns about preventing adverse effects on the human body and interference with other electronic circuits. In such a situation, it has become increasingly difficult to reduce electromagnetic noise emitted from integrated circuits to within the desired numerical values using the conventional approaches, in which bypass capacitors are placed in the closest possible proximity to the source of the noise, i.e. the integrated circuits.

The object of the invention disclosed in this application, which solves such prior-art problems, is to provide an electronic circuit that includes a circuit substrate having mounted thereon an integrated circuit, i.e. a noise source, and bypass capacitors, and that is capable of satisfying stringent regulatory requirement values for electromagnetic noise emissions.

SUMMARY OF THE INVENTION

In order to solve the problems outlined above, the electronic circuit disclosed herein includes an integrated circuit, a bypass capacitor, and a circuit substrate that has mounted thereon the integrated circuit and bypass capacitor. In the circuit, one electrode terminal of the bypass capacitors and one connecting electrode on the integrated circuit are connected through a first wire interconnect formed in the circuit substrate, while the other electrode terminal of the bypass capacitor and the other connecting electrode of the integrated circuit are connected through a second wire interconnect formed in the circuit substrate. In addition, the gap between the first wire interconnect and the second wire interconnect is narrower than either the gap between the one connecting electrode and the other connecting electrode on the integrated circuit or the gap between the one electrode terminal and the other electrode terminal of the bypass capacitors.

DETAILED DESCRIPTION OF THE INVENTION

The electronic circuit disclosed herein includes an integrated circuit, a bypass capacitor, and a circuit substrate that has mounted thereon the integrated circuit and the bypass capacitor. One electrode terminal of the bypass capacitor and one connecting electrode of the integrated circuit are connected through a first wire interconnect formed in the circuit substrate, while the other electrode terminal of the bypass capacitor and the other connecting electrode of the integrated circuit are connected through a second wire interconnect formed in the circuit substrate. The gap between the first wire interconnect and the second wire interconnect is smaller than either the gap between the one connecting electrode and the other connecting electrode on the integrated circuit or the gap between the one electrode terminal and the other electrode terminal of the bypass capacitor.

As a result, the two wire interconnects, which have electric current flowing therethrough in mutually different directions, can be placed closer together to produce a magnetic field cancellation effect, whereby each of the magnetic stray fields of different polarity generated by the respective wire interconnects cancels out the other magnetic field. This makes it possible to obtain an electronic circuit that produces strong electromagnetic noise emission suppression effects even if an integrated circuit operating at high frequencies is used as the active device.

In the above-mentioned electronic circuit disclosed herein, the integrated circuit is flip-chip mounted to the mounting surface of the circuit substrate through the bump electrodes as the connecting electrodes, the bypass capacitors are mounted on the back surface of the substrate, and both the first wire interconnect and the second wire interconnect are through wire interconnects that connect the mounting surface of the circuit substrate to its back surface. This makes it possible to obtain a flip-chip mounted electronic circuit, in which electromagnetic noise emissions are suppressed efficiently.

In addition, it should be noted that the circuit substrate preferably is a multi-layer substrate formed by laminating multiple substrates, in which the first wire interconnect and the second wire interconnect are formed as unions of through wire interconnects formed in each respective substrate stratum constituting the multi-layer substrate and the gap between the through wire interconnects formed in a substrate located in a central portion in the thickness direction of the multi-layer substrate is smaller than the gap between the through wire interconnects formed in a substrate disposed on the surface of the multi-layer substrate. In this manner, an electronic circuit that has low levels of electromagnetic noise emissions while providing dense integration using a multi-layer substrate can be obtained without changing the locations or shapes of the through wire interconnects formed in the substrates disposed on the surfaces of the multi-layer substrate.

In this case, there are respectively formed multiple through wire interconnects that form the first wire interconnect and the second wire interconnect. This allows for the trace resistance of the through wire interconnects to be reduced.

In addition, the multiple through wire interconnects forming the first wire interconnect preferably are placed in a staggered manner such that they enter the gaps between the multiple through wire interconnects forming the second wire interconnect. This allows for pairs of through wire interconnects having electric current flowing in opposite directions to be placed closer together while ensuring the independence of the respective through wire interconnects.

Furthermore, the bypass capacitors mounted on the back surface of the circuit substrate form groups of two capacitors, and the two bypass capacitors forming such a group are placed at a placement pitch that is narrower than the placement pitch of the bump electrodes of the integrated circuit, to which they are connected respectively, and, at the same time, such that the electric currents flowing through the two bypass capacitors that form the group are oriented in mutually opposite directions. This makes it possible to obtain an electronic circuit that achieves even lower levels of electromagnetic noise emissions based on the magnetic field cancellation effects generated by the electric currents flowing through the bypass capacitors.

In addition, in the wiring pattern formed on the circuit substrate, the integrated circuit preferably is mounted on the circuit substrate using lead frame terminals that serve as the connecting electrodes, and the first wire interconnect and the second wire interconnect preferably are wiring patterns formed on the circuit substrate that connects the lead frame terminals to the electrode terminals of the bypass capacitor. This makes it possible to obtain an electronic circuit that is equipped with a lead frame-bonded integrated circuit and offers low levels of electromagnetic noise emissions.

Specific embodiments of the electronic circuit disclosed herein are described below with reference to the drawings.

It should be noted that, for convenience, only the main components required for describing the invention disclosed herein are shown among the constituent components of the electronic circuits in the drawings referenced hereinbelow. Therefore, the electronic circuit disclosed herein may include optional constituent components not shown in the referenced drawings. In addition, the dimensions of the components in the drawings do not always faithfully represent the size of the actual constituent components and the dimensional proportions etc. of the components.

FIG. 1, which provides an example of the electronic circuit used in the first embodiment, is a cross-sectional view of the main body illustrating the cross-sectional configuration of an electronic circuit, in which an integrated circuit is flip-chip mounted to a circuit substrate.

As shown inFIG. 1, the electronic circuit100includes an LSI chip used as an integrated circuit1, a circuit substrate3, and a bypass capacitor7.

The integrated circuit1is, for example, a flip-chip mounted LSI chip, in which multiple bump electrodes2(2aand2b) used as connecting electrodes for providing a connection to the circuit substrate3are arranged on one of the major surfaces of the integrated circuit1, i.e. its lower surface1aas shown inFIG. 1. Although for convenience only two bump electrodes2aand2bare shown as bump electrodes2inFIG. 1, as shown inFIG. 2, which is described below, the bump electrodes2of the integrated circuit1of the present embodiment are aligned in a matrix configuration that is arranged transversely and longitudinally across the entire major surface of the integrated circuit1. Furthermore, in the flip-chip mounted integrated circuit1of the present embodiment, which is fitted with bump electrodes2, there are no constraints on the arrangement pattern of the bump electrodes2. In addition, as used in the present embodiment, the term “integrated circuit” refers to an electronic component on which a large number of circuit devices are mounted within a narrow surface area using semiconductor techniques, and which typically is represented by components including, but not limited to, LSI chips and ICs.

The circuit substrate3is of the type suitable for the flip-chip mounting of the integrated circuit1. Mounting electrode pads5(5aand5b), which provide a connection to the integrated circuit1, are formed at locations corresponding to the locations where the bump electrodes2of the integrated circuit1are formed on the surface, to which the integrated circuit1is mounted, i.e. on the mounting surface3alocated at the top ofFIG. 1.

The bypass capacitor7is mounted on the rear surface that is opposite the mounting surface3aof the circuit substrate3, i.e. on the back surface3b, which is located at the bottom ofFIG. 1. For this purpose, the device-mounting electrodes6(6aand6b) are formed on the back surface3bof the circuit substrate3so as to match the gap between the electrode terminals8(8aand8b) located at both ends of the bypass capacitor7. In addition, the mounting electrode pads5formed on the mounting surface3aof the circuit substrate3and the device-mounting electrodes6formed on the back surface3bare connected by a first through wire interconnect4aand a second through wire interconnect4bprovided inside via holes passing through the circuit substrate3.

The bypass capacitor7may be, for example, a chip-type ceramic capacitor. The electrode terminals8(8aand8b) formed at both ends thereof are soldered to the device-mounting electrodes6(6aand6b) formed on the back surface3bof the circuit substrate3. In this manner, one of the electrode terminals8aof the bypass capacitor7is connected to the bump electrode2a, which is one of the connecting electrodes of the integrated circuit1, through the device-mounting electrode6aformed on the back surface of the circuit substrate3, the first through wire interconnect4a(which is the first wire interconnect formed in the circuit substrate3), and the mounting electrode pad5aformed on the component-bearing side3aof the circuit substrate3. In addition, the other electrode terminal8bof the bypass capacitor7is connected to the bump electrode2b, which is another connecting electrode of the integrated circuit1, through the device-mounting electrode6bformed on the back surface3bof the circuit substrate3, the second through wire interconnect4b(which is the second wire interconnect formed in the circuit substrate3), and the mounting electrode pad5bformed on the component-bearing side3aof the circuit substrate3.

It should be noted that capacitors of other types, such as electrolytic capacitors, can be used as the bypass capacitors in addition to the ceramic capacitor illustrated above.

As shown inFIG. 1, in the electronic circuit100of the present embodiment, the gap “c” between the first through wire interconnect4a, which connects one of the electrode terminals8aof the bypass capacitor7to the bump electrode2aof the integrated circuit1, and the second through wire interconnect4b, which connects the other electrode terminal8bof the bypass capacitor7to the bump electrode2bof the integrated circuit1, is smaller than the gap “a” between the bump electrodes2aand2bon the integrated circuit1or the gap “b” between the electrode terminals8a,8bof the bypass capacitor7. It should be noted that, as used herein, the term “gap” refers literally to the shortest distance between two components and, as a concept, differs from “placement pitch”, which refers to the center-to-center distance between the two components.

Since the electric current flowing through the first through wire interconnect4aand the electric current flowing through second through wire interconnect4bare opposite in direction, as shown by the white arrows inFIG. 1, the magnetic stray field generated by the current flowing through the first through wire interconnect4aand the magnetic stray field generated by the current flowing through the second through wire interconnect4bhave mutually opposite polarities and cancel each other out. In the electronic circuit of the present invention, making the gap “c” between the first through wire interconnect4aand second through wire interconnect4bshorter than either one of the gap “b” between the electrode terminals8aand8bor the gap “a” between the connecting electrodes2aand2bproduces a magnetic stray field cancellation effect and reduces the electromagnetic noise emitted from the electronic circuit100.

FIG. 2is an enlarged plan view of the main body illustrating the configuration of the back surface3bof the circuit substrate3of the electronic circuit100according to the present embodiment. It should be noted that sinceFIG. 2corresponds toFIG. 10, which shows the planar configuration of the conventional electronic circuit500, the mounting electrode pads5formed on the circuit substrate3and the through wire interconnect4formed on the circuit substrate3are omitted fromFIG. 2in order to avoid overcomplicating the drawing.

As shown inFIG. 2, in the electronic circuit100of the present embodiment, the bypass capacitors7(7a,7b,7c,7d,7e,7f,7g, and7h), which are mounted on the back surface3bof the circuit substrate3, form groups of two adjacent capacitors and the placement pitch of the two bypass capacitors making up such groups, i.e. (7aand7b), (7cand7d), (7eand7f), and (7gand7h), in other words, the center-to-center distance “e” between the bypass capacitors7, is narrower than the placement pitch of the bump electrodes2of the integrated circuit1, in other words, the center-to-center distance “d” between the bump electrodes2, to which the respective bypass capacitors7are connected.

In addition, as shown by the white arrows inFIG. 2for7aand7b, in the electronic circuit100of the present embodiment the grouped bypass capacitors (7aand7b), (7cand7d), (7eand7f), and (7gand7h), which are mounted on the back surface3bof the circuit substrate3, are placed such that the directions of the respective electric currents are mutually opposite.

In this manner, placing the bypass capacitors7close together in groups of two and, at the same time, orienting the electric currents flowing therethrough in mutually opposite directions makes it possible to produce magnetic stray field cancellation effects based on using magnetic fields of opposite polarities generated by electric currents of mutually opposite directions flowing through the bypass capacitors7. For this reason, in addition to the electromagnetic noise emission cancellation effect produced due to the opposite orientation of the electric currents flowing through the first through wire interconnect4aand second through wire interconnect4billustrated inFIG. 1, the circuit is capable of producing even stronger suppression effects on electromagnetic noise emissions.

It should be noted that, as described above, in the electronic circuit100of the present embodiment illustrated inFIG. 2, the electric currents flowing through the bypass capacitors that form closely-spaced groups (7aand7b), (7cand7d), (7eand7f), and (7gand7h), are opposite in direction. On the back surface53bof the circuit substrate53used in the conventional electronic circuit500shown inFIG. 10, the device-mounting electrodes56were formed in the shape of strips and the terminal electrodes58on one side of the multiple bypass capacitors57were connected in common to a single device-mounting electrode56. However, in the present embodiment, the device-mounting electrodes6(6aand6b) of the electronic circuit100are formed in an island-like pattern and only one electrode terminal8of each respective bypass capacitor7is connected.

As explained above with reference toFIG. 1andFIG. 2, in the electronic circuit100of the present embodiment, magnetic stray field cancellation effects are produced and electromagnetic noise emissions are suppressed with the help of the electric currents flowing through the first and second through wire interconnects4aand4b, which connect the bypass capacitors7to the bump electrodes2of the integrated circuit1, i.e. the noise source, as well as with the help of the electric currents flowing through the bypass capacitors7itself.

In order to examine the effects, electromagnetic noise emissions from the electronic circuit100according to the present embodiment and electromagnetic noise emissions from a conventional electronic circuit500, such as the one shown inFIG. 9andFIG. 10, were measured.

It should be noted that the pitch used to form the bump electrodes on the LSI chip, i.e. the integrated circuit, in the electronic circuit used for measurements was 0.6 mm both transversely and longitudinally. In addition, among the 40 bypass capacitors that were used, 24 bypass capacitors had no constraints on the shape of the wiring patterns formed on the circuit substrate and were subjected to electromagnetic noise emission suppression measures described in the present embodiment, that is, wire interconnect gap reduction, and close placement of the bypass capacitors in such a manner that the electric currents flowing through the bypass capacitors are opposite in direction, as explained in the present embodiment described above. Specifically, the gap between the through wire interconnects connected to the 24 bypass capacitors was set to 0.08 mm, i.e. to the limit value for forming adjacent vias in the circuit substrate. In addition, these 24 bypass capacitors were arranged in groups of two and the placement pitch of the bypass capacitors forming such groups on the back surface of the circuit substrate was set to 0.35 mm. Both in the conventional electronic circuit and in the 16 bypass capacitors that had been subjected to the modifications described in the present embodiment, the placement gap of the through wire interconnects and the placement pitch of the bypass capacitors on the back surface of the circuit substrate were set to 0.6 mm, i.e., it was the same as the pitch used to form the bump electrodes.

FIG. 3shows the EMI radiation level measurement results obtained by examining the effects of magnetic stray field noise suppression in the electronic circuit of the present embodiment. The level of EMI radiation is plotted along the Y-axis in db and the frequency bands are plotted in MHz along the X-axis.

In comparison with the level of EMI radiation emitted from the conventional electronic circuit, which is indicated by “B” inFIG. 3, the level of EMI radiation emitted from the electronic circuit of the present embodiment, which is indicated by “A” inFIG. 3, in other words, the electronic circuit in which magnetic field cancellation effects had been applied to the 24 bypass capacitors, decreased in the vicinity of the 150-MHz frequency band and the 300-500-MHz band, and remained at a level of not more 35 dB in all the frequency bands. Therefore, it was confirmed that electromagnetic noise emissions were suppressed in comparison with the conventional electronic circuit, which had a noise level of about 45 dB in the 30˜500-MHz band, that is, in the high frequency band.

It should be noted that the embodiment described above illustrated an example, in which magnetic stray field cancellation effects due to currents flowing through the bypass capacitors7was generated in addition to the magnetic stray field cancellation effect generated by currents flowing through the through wire interconnects4a,4b, i.e., the first wire interconnect and the second wire interconnect that connect the bump electrodes2serving as the connecting electrodes of the circuit substrate1, i.e. the source of the noise, to the terminal electrodes8of the bypass capacitor7. However, in the electronic circuit of the present embodiment, producing a magnetic stray field cancellation effect with the help of the currents flowing through the bypass capacitors is not essential. An electromagnetic radiation noise suppression effect can be achieved using the magnetic stray field cancellation effects generated by the electric currents flowing through the wire interconnects, which offer longer current paths and are easier to place in close proximity.

As described above, the electronic circuit of the present embodiment is an electronic circuit, in which electromagnetic noise emissions are suppressed by a magnetic stray field cancellation effect produced by making both the placement gap between the bump electrodes, i.e. the connecting electrodes of the integrated circuit, and the placement gap between the terminal electrodes of the bypass capacitors wider than the placement gap between the through wire interconnects, i.e. the wire interconnects that are formed in the circuit substrate and that are used to connect them.

As can be understood by comparing the cross-sectional structure of the conventional electronic circuit illustrated inFIG. 9, which is based on an electromagnetic noise emission suppression approach that utilizes the conventional methods, andFIG. 1, which shows the cross-sectional configuration of the electronic circuit of the present embodiment, the placement gap between the through wire interconnects in the electronic circuit of the present embodiment is smaller, as a result of which the path that connects the connecting electrodes of the integrated circuit to the terminal electrodes of the bypass capacitors is made longer than the rectilinear path that connects the connecting electrodes to the terminal electrodes in the conventional electronic circuit. In other words, the electronic circuit of the present embodiment utilizes more effective electromagnetic noise emission suppression means while offering a solution different from that of the conventional means for suppressing electromagnetic noise emissions from active devices operating at high frequencies, which involves placing bypass capacitors in the closest possible physical proximity to the source of the noise, i.e. the integrated circuit.

It should be noted that while the placement gap “a” between the connecting electrodes of the integrated circuit and the placement gap “b” between the electrode terminals at both ends of the bypass capacitors are shown as having nearly identical dimensions in the electronic circuit of the present embodiment illustrated inFIG. 1, the electronic circuit of the present embodiment is not limited thereto. When the placement gap “a” between the connecting electrodes of the integrated circuit and the placement gap “b” between the electrode terminals at both ends of the bypass capacitors are different, the electronic circuit of the present embodiment produces the above-described remarkable actions and effects by making the placement gap “c” between the wire interconnects smaller than either one of them.

An electronic circuit used in a modification of the present embodiment is explained below with reference toFIG. 4.

FIG. 4is an enlarged cross-sectional view of the main body illustrating the schematic configuration of the electronic circuit110used in a modification of the present embodiment.FIG. 4corresponds toFIG. 1, which illustrates the cross-sectional configuration of the electronic circuit100of the present embodiment.

The modified electronic circuit110illustrated inFIG. 4differs from the electronic circuit100of the present embodiment illustrated inFIG. 1in that the circuit substrate30is a multi-layer substrate produced by laminating multiple substrates. For this reason, like parts are designated like reference numerals similar to those used in the electronic circuit100illustrated inFIG. 1and their detailed description is omitted, with the exception of the circuit substrate30.

Specifically, the circuit substrate30is formed by laminating, e.g. the seven substrates31,32,33,34,35,36, and37. Wiring patterns, not shown, are formed on the respective surfaces of the seven substrates31-37and appropriate through wire interconnects are formed in each one of the substrates31-37. In addition, the through wire interconnects and wiring patterns provided in each one of these substrates are interconnected, thereby forming the overall wiring pattern of the circuit substrate30.

In the electronic circuit110illustrated inFIG. 4, the through wire interconnects41-47formed in the respective laminated substrates31-37are interconnected and provide a connection between the mounting electrode pads5and device-mounting electrodes6formed on both exterior surfaces of the circuit substrate30. Among the laminated substrates31-37, the substrates33,34, and35, which are disposed in the central portion of the circuit substrate30, have narrower placement gaps between the through wire interconnects43,44, and45formed in the substrates33,34, and35. At the same time, in the substrates31and37disposed on the surface of the circuit substrate30, the placement gaps between the through wire interconnects41,47formed in the substrates31,37are set to a wider distance. In addition, in the substrates32and36, which are located in between, the placement gaps of the through wire interconnects42,46in the substrates32,36are set to an intermediate width. As a result, as shown inFIG. 4, the through wire interconnects can be formed such that their placement gap is wider in the substrates that are closer to the surfaces of the multi-layer substrate, i.e. the circuit substrate30, and their placement gap is narrower in the substrates located in the central portion of the circuit substrate30.

It should be noted that when the gap between the wire interconnects varies as shown in the electronic circuit110used in the modified example illustrated inFIG. 4, the placement gap between the wire interconnects in the narrowest portion has to be smaller than either the gap between the connecting electrodes of the integrated circuit or the gap between the terminal electrodes of the bypass capacitors. And, quite naturally, in order to generate a sufficiently strong magnetic stray field cancellation effects using the oppositely oriented electric currents flowing through the adjacent wire interconnects, it is preferable to use a design wherein the length of the narrowest portion is equal to or greater than a certain constant value.

In this manner, in the electronic circuit110used in the modified example of the present embodiment, the through wire interconnects serving as the first and second wire interconnects that connect the connecting electrodes2of the integrated circuit1to the electrode terminals8of the bypass capacitors7, are formed by connecting the through wire interconnects41-47such that their placement gap is different in the different substrates31-37that make up the multi-layer substrate. When this is done, the through wire interconnects, which have electric currents flowing therethrough in opposite directions, are brought closer together in the central portion of the circuit substrate30, thereby producing a pronounced magnetic stray field cancellation effect. At the same time, on the surfaces of the circuit substrate30, the through wire interconnects can be formed to match the electrode pads and device-mounting electrodes provided at the locations corresponding to the placement gaps of the interconnected electrode terminals8of the bypass capacitors7and connecting electrodes2of the integrated circuit1.

As a result of changing the locations of the through wire interconnects formed in the substrates, as shown in the electronic circuit110used in the modified example of the present embodiment, it is no longer necessary to increase the surface area of the mounting electrode pads5and device-mounting electrodes6disposed on the surface of the circuit substrate in order to connect the electrode terminals of the bypass capacitors and the through wire interconnects, or the connecting electrodes of the integrated circuit and the through wire interconnects formed with a narrow placement gap therebetween, as shown in the electronic circuit100of the present embodiment illustrated inFIG. 1. Therefore, high design tolerances can be ensured for the placement locations of the electrodes and wiring patterns on the surface of the circuit substrate, and electronic circuits can be obtained, in which multi-layer substrates permitting high-density mounting are used as the circuit substrate. In addition, this has the advantage that electronic circuits traditionally equipped with multi-layer substrate-type circuit substrates can be used without having to redesign the substrates disposed on the outermost sides of the circuit substrate, and conventional substrates thus can be used “as is.”

It should be noted that there are no constraints on the specific configurations of the substrates used when the circuit substrate is a multi-layer substrate. For example, inFIG. 4, the multi-layer substrate, i.e. the circuit substrate30, was formed using seven substrates31-37of roughly the same thickness. However, it goes without saying that the number of the substrates and the thickness of the respective substrates can be appropriately varied.

An electronic circuit in which the integrated circuit is connected to the circuit substrate using lead frame terminals is illustrated hereinbelow as a second embodiment.

FIG. 5is an enlarged plan view of the main body illustrating the planar configuration of the electronic circuit used in the second embodiment.

The electronic circuit200used in the second embodiment, as shown inFIG. 5, has an integrated circuit11disposed on a circuit substrate13. The integrated circuit11used in the electronic circuit200according to the second embodiment is, for example, a packaged LSI chip having lead frame terminals12(12a,12b) extending from one side and used as connecting electrodes.

The distal portions of the lead frame terminals12are bent to follow the surface of the circuit substrate13and are bonded to mounting electrode pads14(14a,14b) disposed on the circuit substrate13using solder etc., not shown.

On the surface of the circuit substrate13, there are formed device-mounting electrodes15(15a,15b) connected to the mounting electrode pads14by wiring patterns16(16a,16b) formed on the surface of the circuit substrate13. The terminal electrodes18(18a,18b) at both ends are aligned with the device-mounting electrodes15(15a,15b) and a bypass capacitor17is mounted and bonded thereto.

In the electronic circuit200of the present embodiment, in the circuit substrate13, the gap “h” between the first wiring pattern16a, i.e. the first wire interconnect that connects the lead frame terminal12aserving as one of the connecting electrodes of the integrated circuit11to one of the terminal electrodes18aof the bypass capacitor17, and the second wiring pattern16b, i.e. the second wire interconnect that connects the lead frame terminal12bserving as the other connecting electrode of the integrated circuit11to the other terminal electrode18bof the bypass capacitor17, is made smaller than either the gap “f” between the lead frame terminal12aand lead frame terminal12bor the gap “g” between the one electrode terminal18aand the other electrode terminal18bof the bypass capacitor17.

In this manner, the first wiring pattern16aand the second wiring pattern16b, that have electric currents flowing therethrough in opposite directions, as indicated by the white arrows inFIG. 5are brought closer together. This produces magnetic stray field cancellation effects and enables efficient suppression of electromagnetic noise emissions.

It should be noted that while the electronic circuit200according to the second embodiment described with reference toFIG. 5is illustrated and described as a circuit, in which the integrated circuit11and bypass capacitors17are mounted on the same surface of the circuit substrate13, the electronic circuit of the present embodiment is not limited thereto and may be a circuit in which the bypass capacitors17are mounted on the back face of the circuit substrate13.

In addition, while inFIG. 5the gap “f” between the lead frame terminals12a,12bserving as the connecting electrodes of the integrated circuit11and the gap “g” between the connecting electrodes18a,18bat both ends of the bypass capacitor17are illustrated as having roughly the same dimensions, the electronic circuit of the present embodiment is not limited thereto. If the gap “f” between the lead frame terminals12a,12band the gap “g” between the connecting electrodes18a,18bat both end of the bypass capacitor17are different, a magnetic stray field cancellation effect generated by the electric currents flowing through the connecting electrodes in opposite directions can be obtained by making the gap “h” between the first wiring pattern16a, i.e. the first wire interconnect, and the second wiring pattern16b, i.e. the second wire interconnect, smaller than the smallest one of them.

It should be noted that, in the electronic circuit200of the present embodiment, the first wiring pattern and second wiring pattern are connected linearly in the horizontal direction ofFIG. 5in order to shorten the path connecting the lead frame terminals of the integrated circuit to the electrode terminals of the bypass capacitor as much as possible. In other words, just like the electronic circuit100of the first embodiment illustrated inFIG. 1, the electronic circuit200of the present embodiment is an innovative circuit designed to suppress electromagnetic noise emissions using a novel configuration that does not depend on conventional means for suppressing electromagnetic noise emissions.

An example of placement of through wire interconnects to provide connections between laminated substrates when the circuit substrate that makes part of the electronic circuit is a multi-layer substrate is described hereinbelow as a third embodiment.

FIG. 6is a partial enlarged plan view that illustrates the locations of placement of through wire interconnects47(47a,47b) formed in the seventh substrate37of the electronic circuit110, in which a multi-layer substrate is used as the circuit substrate30illustrated inFIG. 4. The seventh substrate is on the side on which the bypass capacitor7is placed.

As shown inFIG. 4, the substrate37is the substrate on the surface of the side opposite the first substrate31, on which the integrated circuit1is mounted in the multi-layer substrate30. The bypass capacitor7is placed on its surface. As shown inFIG. 6, on the seventh substrate37, two terminal electrodes,8aand8b, of the bypass capacitor7respectively are connected to the device-mounting electrodes6a,6bformed on the substrate37.

Through wire interconnects47a,47b, which go through the substrate37, are connected to the device-mounting electrodes6a,6bas well as to a wiring pattern, not shown, formed on the sixth substrate36, which is one substrate deeper inside the multi-layer substrate30.

Although for convenience purposes each one of the respective through wire interconnects41-47is shown as a single columnar-shaped object inFIG. 4, the diameter of the through wire interconnects41-47, that go through the substrates31-37making up the multi-layer substrate30, is limited due to the constraints imposed by the method of fabrication, in which the interconnects are formed by injecting metal into via holes formed by etching the substrates31-37. For this reason, as illustrated by the through wire interconnects41-47, which connect the integrated circuit1to the bypass capacitor7and are formed in the substrates31-37of the multi-layer substrate30that forms part of the electronic circuit of the present embodiment, in order to produce through wire interconnects41-47that would provide a trace path with the lowest possible trace resistance, the through wire interconnects41-47that make up a trace path serving as a single wire interconnect are formed as a series of multiple via-traces.

As shown inFIG. 6, in the seventh substrate37of the present embodiment, through wire interconnects41a,47bare formed in each terminal electrode8a,8bof the bypass capacitor7as fifteen via-traces arranged in two rows. It should be noted that, quite naturally, the number of the through wire interconnects47formed in one terminal electrode8, as well as the number of their rows, is selected appropriately depending on the available substrate space and, in particular, on the size of the electrode terminals of the components connected when connecting circuit components such as bypass capacitors and the like.

FIG. 7is an enlarged partial plan view illustrating the placement locations of through wire interconnects44(44a,44b) formed in the fourth substrate34, which is located in the central portion in the stacking direction of the multi-layer substrate30of the electronic circuit110of the present embodiment.

As shown inFIG. 7, the through wire interconnects44a,44bformed in the fourth substrate34are placed such that the position l-44a, which is where the multiple A-side through wire interconnects44aprotrude the most into the B-side occupied by the through wire interconnects44b, is located deeper into the B-side of the through wire interconnects44bthan position l-44b, which is where the multiple B-side through wire interconnects44bprotrude the most into the A-side, where the through wire interconnects44aare located. In other words, the adjacent through wire interconnects are placed in a staggered manner such that multiple through wire interconnects forming the first wire interconnect enter the gaps between the multiple through wire interconnects forming the second wire interconnect. This makes it possible to ensure the respective independence of the multiple through wire interconnects41a,44band, at the same time, reduce the distance between the paths of the electric currents flowing in opposite directions, thereby producing considerable magnetic stray field cancellation effects.

FIG. 8shows a wiring pattern formed on a substrate in an actual electronic circuit.

As shown inFIG. 8, the interconnects are placed in close proximity, such that the through wire interconnects44aand44bform a mutually staggered configuration in the wiring pattern formed on the fourth substrate34.

It should be noted that while inFIG. 5the through wire interconnects44aand through wire interconnects44bare formed such that there are five or six of them in a single row, this is merely an example, and the number of the through wire interconnects44connected to one of the terminals8of the bypass capacitor7, as well as the number of their rows, are set appropriately to ensure that there are as many of them as possible depending on the available surface area on the substrate34.

In addition, as shown inFIG. 4, in the electronic circuit110illustrated in the present embodiment, the through wire interconnects43,44, and45are formed with identical gaps therebetween in the three substrates33,34, and35located in the center in the stacking direction of the multi-layer substrate30. For this reason, through wire interconnects43,45(not shown) are formed in the third substrate33and in the fifth substrate35in the same manner as in the fourth substrate34illustrated inFIG. 7andFIG. 8.

As described above with reference to specific configuration examples, in the electronic circuits of the embodiments described above, the wire interconnects connecting the connecting electrodes of the integrated circuit to the electrode terminals of the bypass capacitor are formed such that the placement gap therebetween is made smaller than either the gap between the connecting electrodes of the integrated circuit and the gap between the electrode terminals of the bypass capacitor, thereby producing a magnetic stray field cancellation effect due to the electric currents flowing through the wire interconnects in opposite directions, and enabling suppression of electromagnetic noise emissions.

Since it is an electronic circuit, in which electromagnetic noise emissions are suppressed even if the circuit is equipped with an integrated circuit used as a high-frequency active device, the electronic circuit disclosed herein can be advantageously employed as a basic component of various electronic and information devices.