Wiring substrate for a semiconductor device having differential signal paths

A semiconductor device is provided with improved resistance to noise. Conductive planes are respectively formed over wiring layers. One wiring layer is provided with a through hole land integrally formed with a through hole wiring. In other wiring layers located over the wiring layer with the through hole land, openings are respectively formed in the conductive planes. The area of each of the openings is larger than the plane area of the through hole land.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2013-044393 filed on Mar. 6, 2013 including the specification, drawings and abstract is incorporated herein by reference in its entirety.

BACKGROUND

The present invention relates to techniques of semiconductor devices, and more specifically, to a technique effectively applied to a semiconductor device having a semiconductor chip mounted on a wiring substrate with a plurality of wiring layers stacked thereover.

Japanese Unexamined Patent Publication No. 2010-219498 (Patent Document 1) discloses a semiconductor device having a void or floating pattern formed in a region of a wiring layer opposed to the surroundings of a solder ball and connected to a single wiring.

Japanese Unexamined Patent Publication No. 2002-100932 (Patent Document 2) discloses a semiconductor device in which a cutout portion is provided in a ground pattern to prevent the ground pattern from being superimposed over a wiring pattern for a piezoelectric vibrator including a monitor electrode pad.

Japanese Unexamined Patent Publication No. 2005-340636 (Patent Document 3) discloses a multilayer wiring substrate having a floating conductive layer positioned to be superimposed over ball pads for connecting balls on a surface of the substrate in the thickness direction.

RELATED ART DOCUMENTS

Patent Documents

SUMMARY

The inventors of the present application have studied techniques for improving the performance of a semiconductor device including semiconductor chips stacked over a wiring substrate. As one of the techniques, the semiconductor device has been studied which includes a semiconductor chip mounted over a wiring substrate with wiring layers stacked thereon.

As a result of the studies, the inventors of the present application have found out that various problems are raised from the viewpoint of improving resistance to noise of the semiconductor device when conductive planes are respectively formed over the respective wiring layers included in the wiring substrate.

Other problems and new features of the present invention will be better understood after a reading of the following detailed description of the present application in connection with the accompanying drawings.

A semiconductor device according to one embodiment of the invention includes a conductive plane formed at each of the wiring layers included in a wiring substrate. The wiring layers include a wiring layer having a through hole land integrally formed with a through hole wiring. The wiring layer formed as an upper layer above, or a lower layer under the wiring layer having the through hole land formed therein is provided with an opening located in the position of the conductive plane superimposed over the through hole land in the thickness direction. An area of the opening is larger than a plane area of the through hole land.

The invention can provide the semiconductor device with improved resistance to noise.

DETAILED DESCRIPTION

Explanation of Description Format and Basic Terms and Usage in Present Application

In the present application, the following preferred embodiments may be described below by being divided into a plurality of sections or the like for convenience, if necessary, which are not independent from each other unless otherwise specified. Regardless of the order of the description of these sections, the sections indicate respective parts in a single example. Alternatively, one of the sections may be the details of a part of the other, or a modified example of a part or all of the other. In principle, parts having the same function will not be described repeatedly. Respective components of the preferred embodiments are not essential unless otherwise specified, except when limiting the number of the components in theory, and except when considered not to be definitely so from the context thereof.

Similarly, in the description of the embodiments, the term “X formed of A” or the like as to material, composition, and the like does not exclude elements other than the element “A”, unless otherwise specified and except when considered not to be definitely so from the context. For example, as to the component, the above term means “X containing A as a principal component”. For example, the term “silicon member” is not limited to pure silicon, and may obviously include a SiGe (silicon-germanium) alloy, or a multi-component alloy containing silicon as a principal component, and another additive. The term “gold plating”, “Cu layer”, or “nickel plating” is not limited to pure one, but can include a member containing gold, Cu, or nickel as a principal component unless otherwise specified.

Even when referring to a specific numeral value or amount, the number of elements or the like may be greater than, or less than the specific numeral number, unless otherwise specified, except when limited to the specific number in theory, and except when considered not to be definitely so from the context.

As to the terms “planar surface and side surface” as used in the present application, the term “planar surface” means a planar surface in parallel to a reference surface which is a surface of a semiconductor chip with a semiconductor element formed thereat. The term “side surface” means a surface intersecting the above-mentioned planar surface. The direction connecting two planar surfaces spaced apart from each other in the side view is referred to as a thickness direction.

It is noted that although the term “upper surface or lower surface” are used in the present application, there are various forms of semiconductor packages, whereby the upper surface of the semiconductor package happens to be located under its lower surface thereof after mounting the semiconductor package. In the present application, one planar surface of the semiconductor chip with the element formed thereat is hereinafter referred to as an upper surface, and the other surface opposite to the upper surface is hereinafter referred to as a lower surface.

In each drawing of the embodiments, the same or like parts are indicated by the same or similar reference character or number, and its description will not be repeated in principle.

In the accompanying drawings, even a cross-sectional view may omit hatching in some cases if the hatching possibly makes the sectional view complicated, or when a cavity or hole is easy to discriminate. In this context, the outline of a hole closed in a planar manner with respect to the background may be omitted when clearly seen from the description or the like. Further, in order to represent a part which is not a cavity or hole, or in order to clearly represent a boundary between regions, a hatching or dot pattern is sometimes given even when the figure is not a cross-sectional view.

PREFERRED EMBODIMENTS

FIG. 1shows a perspective view of a semiconductor device according to one embodiment, andFIG. 2shows a bottom view of the semiconductor device shown inFIG. 1.FIG. 3shows a perspective plan view of an internal structure of the semiconductor device over a wiring substrate with a heatsink shown inFIG. 1removed.FIG. 4shows a cross-sectional view taken along the ling A-A ofFIG. 1. For easy understanding,FIGS. 1 to 4show a small number of terminals. Further, for easy understanding,FIG. 4shows a smaller number of solder balls4than that of an example shown inFIG. 2. The number of terminals (bonding pads2PD, ball lands2LD, solder balls4) is not limited to that of the embodiments described inFIGS. 1 to 4. For example, the invention can be applied to a semiconductor device including about 100 to 10,000 terminals including the bonding pads2PD, lands2D, solder balls4, and the like.

First, the structural outline of a semiconductor device1in this embodiment will be described below usingFIGS. 1 to 4. The semiconductor device1of this embodiment includes a wiring substrate2, and a semiconductor chip3mounted over the wiring substrate2(seeFIG. 4).

As shown inFIG. 4, the wiring substrate2has an upper surface (surface, main surface, first surface, chip mounting surface)2awith the semiconductor chip3mounted thereover, a lower surface (surface, main surface, second surface, lower mounting surface)2bopposed to the upper surface2a, and a plurality of side surfaces2s(seeFIGS. 1 to 3) disposed between the upper surface2aand the lower surface2b. The wiring substrate2has a quadrilateral contour shape in the planar view as shown inFIGS. 2 and 3. In the example shown inFIGS. 2 and 3, the wiring substrate2is a square or a rectangle having an appropriate planar size (size in the planar view, specifically, the sizes of the upper surface2aand the lower surface2b, or the size of the contour), for example, a side length of about 12 to 60 mm. The thickness (height) of the wiring substrate2, that is, a distance between the upper surface2ato the lower surface2bis, for example, about 0.3 to 1.3 mm.

The wiring substrate2is an interposer (relay board) for electrically coupling the semiconductor chip3mounted on the upper surface2aside to a mounting substrate (not shown). The wiring substrate2includes a plurality of wiring layers (six layers in the example shown inFIG. 4) for electrically coupling the upper surface2aside as a chip mounting surface to the lower mounting surface2bas the mount surface. The wiring substrate2is formed by stacking a plurality of wiring layers by a build-up method, over an upper surface2Ca and a lower surface2Cb of the insulating layer (core material, core insulating layer)2CR made of prepreg produced by immersing glass fiber or carbon fiber in resin. The wiring layer on the upper surface2Ca side of the core insulating layer2CR is electrically coupled to the wiring layer on the lower surface2Cb side of the core insulating layer2CR via a plurality of through hole wirings2TW embedded in through-bores (through holes) extending from one of the upper and lower surfaces2Ca and2Cb to the other.

Over the upper surface2aof the wiring substrate2, a plurality of bonding pads (bonding leads, terminals for connection of the semiconductor chip)2PD are formed to be electrically coupled to the semiconductor chip3. Over the lower surface2bof the wiring substrate2, a plurality of ball lands2LD serving as an external input/output terminal of the semiconductor device1are formed. The bonding pads2PD and the ball lands2LD are electrically coupled to each other via wirings2dand through hole wirings2TW formed in the wiring substrate2. The detailed structure of the respective wiring layers included in the wiring substrate2will be described later.

In the example shown inFIG. 4, each of the ball lands2LD is coupled to the solder ball (solder material, external terminal, electrode, or external electrode)4. The solder ball4is a conductive member for electrically coupling the ball lands2LD to terminals (not shown) on the mounting substrate side in mounting the semiconductor device1over the mounting substrate (not shown). The solder ball4is made of, for example, the so-called lead-free soldering material which does not substantially contain Pb or a lead (Pb)-containing Sn—Pb soldering material. For example, the lead-free soldering materials include, for example, only tin (Sn), tin-bismuth (Sn—Bi), bismuth-copper-silver (Bi—Cu—Au), tin-copper (Sn—Cu) and the like. The term “lead-free soldering material” as used herein means a soldering material containing 0.1 wt % or less of lead (Pb), which content complies with the criterion for the RoHS (restriction of hazardous substances).

As shown inFIG. 2, a plurality of solder balls4are arranged in lines (an array or a matrix). Although not shown inFIG. 2, a plurality of ball lands2LD (seeFIG. 4) to which the solder balls4are coupled are also arranged in lines (or a matrix). The thus-obtained semiconductor device including the external terminals (solder balls4and ball lands2LD) arranged in the lines on the lower mounting surface side of the wiring substrate2is called the “area array semiconductor device”. Preferably, the area array semiconductor device can effectively utilize the lower mounting surface (lower surface2b) side of the wiring substrate2as an arrangement space for the external terminals, which can suppress an increase in mounting area of the semiconductor device even though the number of the external terminals is increased. The semiconductor device including a larger number of external terminals with improved function and high integration density can be mounted in a small space.

The semiconductor device1includes the semiconductor chip3mounted over the wiring substrate2. As shown inFIG. 4, each semiconductor chip3includes a front surface (main surface, upper surface)3a, a back surface (main surface, lower surface)3bopposite to the front surface3a, and side surfaces3spositioned between the front surface3aand the back surface3b. The semiconductor chip3has a quadrilateral contour shape whose plane area is smaller than that of the wiring substrate2in the planar view as shown inFIG. 3. In the example shown inFIG. 3, the semiconductor chip3is mounted in the center of the upper surface2aof the wiring substrate2such that the respective four side surfaces3sextend along the four side surfaces2sof the wiring substrate2.

As shown inFIG. 4, a plurality of electrode pads3PD are formed over the front surface3aof the semiconductor chip3. In this embodiment, the electrode pads3PD are arranged in lines (a matrix, an array) over the front surface3aof the semiconductor chip3. Preferably, the arrangement of the electrode pads3PD serving as the electrode of the semiconductor chip3in lines can effectively utilize the front surface3aof the semiconductor chip3as the arrangement space for the electrodes. Even though the number of the electrodes of the semiconductor chip3is increased, a plane area occupied by the pads can be prevented from increasing. Although not shown, as a modified example of this embodiment, the invention can also be applied to a semiconductor chip of a type in which pads are formed at the peripheral edge of the front surface3a.

In the example shown inFIG. 4, the semiconductor chip3is mounted over the wiring substrate2with the front surface3aof the chip3opposed to the upper surface2aof the wiring substrate2. Such a mounting method is called face-down mounting or flip-chip bonding.

Although not shown, a plurality of semiconductor elements (circuit elements) are formed at the main surface of the semiconductor chip3(specifically, a semiconductor element formation region provided at an element formation surface of the semiconductor substrate serving as a base of the semiconductor chip3). The electrode pads3PD are respectively electrically coupled to the semiconductor elements via wirings (not shown) formed in the wiring layers disposed inside the semiconductor chip3(specifically, between the surface3aand the semiconductor element formation region (not shown)).

The semiconductor chip3(specifically, the base of the semiconductor chip3) is formed of, for example, silicon (Si). An insulating film is formed over the front surface3ato cover the base and the wirings of the semiconductor chip3. Each of the electrode pads3PD has its surface exposed from the insulating film at an opening formed in the insulating film. The electrode pads3PD are made of metal. In this embodiment, the electrode pad3PD is made of, for example, aluminum (Al).

As shown inFIG. 4, the electrode pads3PD are respectively coupled to the protruding electrodes3BP. The electrode pads3PD of the semiconductor chip3are electrically coupled to the bonding pads2PD of the wiring substrate2via protruding electrodes3BP. The protruding electrode3BP is a metal member formed to protrude from the front surface3aof the semiconductor chip3. The protruding electrode3BP in this embodiment is the so-called solder bump formed by stacking a soldering material over the electrode pad3PD via an underlayer metal film (under bump metal). The underlayer metal film can be exemplified as a laminated film including a titanium (Ti) film, a copper (Cu) film, and a nickel (Ni) film stacked over the electrode pad3PD from a bonding surface side (in some cases, further including a gold (Au) film formed over the nickel film). The soldering material forming the solder bump can be a lead-containing soldering material, or a lead-free soldering material, like the above soldering ball4. In mounting the semiconductor chip3over the wiring substrate2, the solder bumps are previously formed over both the electrode pads3PD and bonding pads2PD, which are then subjected to heat treatment (reflow process) while the solder bumps are in contact with each other, which integrates the semiconductor bumps together to thereby form the protrusion electrodes3BP. In a modified example of this embodiment, a pillar bump formed of a solder film over a tip of a conductive column made of copper (Cu) or nickel (Ni) can be used as the protrusion electrode3BP.

In this embodiment, the semiconductor chip3includes a circuit into or from which a plurality of signals are input or output at different transmission rates. Although not shown, the semiconductor chip3includes a first circuit to and from which a first signal is input or output at a first transmission rate, and a second circuit to and from which a second signal is input or output at a second transmission rate higher than the first transmission rate. As the second signal, a differential signal is transmitted at a transmission rate of about 10 Gbps (Gigabit per second) to 25 Gbps. Now, in this embodiment, a transmission path through which the second signal is transmitted will be described below as a high speed transmission path. In contrast, a transmission path through which the first signal is transmitted at the first transmission rate lower than the second transmission rate will be described below as a low speed transmission path. Not only the first signal, but also a first driving voltage for driving the first circuit is supplied to the first circuit. Not only the second signal, but also a second driving voltage for driving the second circuit is supplied to the second circuit.

As shown inFIG. 4, an underfill resin (insulating resin)5is disposed between the semiconductor chip3and the wiring substrate2. The underfill resin5is disposed to fill in a space between the front surface3aof the semiconductor chip3and the upper surface2aof the wiring substrate2. The underfill resin5is made of insulating (non-conductive) material (for example, resin), and disposed to seal an electrical coupling part (junctions of the protrusion electrodes3BP) between the semiconductor chip3and the wiring substrate2. The underfill resin5can be disposed to seal the coupling portions of the protrusion electrodes3BP to thereby release the stress caused by the electric coupling portion between the semiconductor chip3and the wiring substrate2.

In the example shown inFIG. 4, a heatsink (heat splitter)6is bonded to the back surface3bof the semiconductor chip3. The heat sink6is a metal plate having a higher thermal conductivity than that of the wiring substrate2, and serves to discharge heat generated by the semiconductor chip3outward. The heatsink6is bonded to the back surface3bof the semiconductor chip3via an adhesive (heat-dissipating resin)7. The adhesive7contains, for example, a number of metal particles and fillers (for example, alumina and the like), and thus has a thermal conductivity higher than that of the underfill resin5.

In the example shown inFIGS. 1 and 4, a support frame (for example, stiffener ring)8supporting the heatsink6surrounds the semiconductor chip3. The heatsink6is bonded and fixed to the back surface3band the support frame8of the semiconductor chip3. The metal support frame8is preferably fixed to surround the semiconductor chip3, which can suppress the warpage of the wiring substrate2to thereby improve the reliability of mounting. The heatsink6can be bonded and fixed to the support frame8provided around the semiconductor chip3to increase the plane area of the heatsink6. That is, the heatsink6is preferably bonded and fixed to the support frame8because the heatsink6can ensure its large superficial area to improve the heat radiation performance and can be stably fixed to the semiconductor chip3.

Next, the details of the wiring substrate2will be described below with reference toFIGS. 5 to 19.FIG. 5shows a plan view of a layout of a wiring layer on a chip mounting surface side (first layer) of the wiring substrate shown inFIG. 4.FIG. 6shows an enlarged plan view of a part of the wiring substrate shown inFIG. 5.FIG. 7shows an enlarged plan view showing another part of the wiring substrate shown inFIG. 5.FIG. 8shows an enlarged cross-sectional view taken along the ling A-A ofFIG. 7.FIG. 9shows an enlarged cross-sectional view of an example of a strip line wiring structure.FIG. 10shows an enlarged cross-sectional view of an example of a microstrip line wiring structure.FIG. 11shows a plan view of a layout of a wiring layer located as one low-level layer (second layer) under the wiring layer shown inFIG. 5.FIG. 12shows an enlarged plan view of a part of the wiring substrate shown inFIG. 11.FIG. 13shows an enlarged plan view of another part of the wiring substrate shown inFIG. 11.FIG. 14shows a plan view of a layout of a wiring layer located as one low-level layer (third layer) under the wiring layer shown inFIG. 11.FIG. 15shows an enlarged plan view of a part of the wiring layer shown inFIG. 14.FIG. 16shows a cross-sectional view taken along the ling A-A ofFIG. 15.FIG. 17shows a plan view of a layout of a wiring layer located as one low-level layer (fourth layer) under the wiring layer shown inFIG. 14.FIG. 18shows a plan view of a layout of a wiring layer located as one low-level layer (fifth layer) under the wiring layer shown inFIG. 17.FIG. 19shows a plan view of a layout of a wiring layer on a lower mounting surface side (sixth layer) over the wiring substrate shown inFIG. 4.

Referring toFIGS. 5 and 11, the first-layer wirings2d1and the second-layer wirings2d2are covered with an insulating layer2e, but for easy understanding of the wiring layout, the first-layer and second-layer wirings2d1and2d2are indicated by a solid line (or two-dot chain line). The first-layer wiring2d1does not actually exist in the second wiring layer WL2shown inFIG. 11, but the first-layer wiring2d1is represented by the two-dot chain line inFIG. 11for easy understanding of the planar positional relationship between the first-layer wiring2d1and the second-layer wiring2d2.FIGS. 6, 7, 12, 13, and 15are all enlarged plan views, but in order to clearly represent the boundary of the conductive pattern, the conductive patterns, including the wirings, via wirings, through hole lands, and conductive plane, are represented by hatching.

As shown inFIG. 5, a wiring layer (first wiring layer) WL1having the upper surface2aof the wiring substrate2as a chip mounting surface includes a plurality of bonding pads2PD. The bonding pads2PD include a plurality of bonding pads (low speed bonding pads)2PDa through which a first signal current flows at the first transmission rate. The bonding pads2PD include bonding pads (high speed bonding pads)2PDb through which a second signal current flows at the second transmission rate higher than the first transmission rate. In this embodiment, the differential signal is transmitted to the high speed bonding pads2PDb at a transmission rate of, for example, 10 to 25 Gbps. Although not shown, the bonding pads2PD include bonding pads (bonding pads for a power source) which supply a power supply potential or reference potential to the circuit with the semiconductor chip3formed thereat as shown inFIG. 4. The bonding pads2PD include the bonding pad to which the reference potential for reference of the signal transmission path is supplied.

The first wiring layer WL1includes a plurality of first via wirings2V1electrically coupled to the bonding pads2PD. As shown inFIG. 6, the first via wirings2V1include a plurality of low speed first via wirings2V1aelectrically coupled to the low speed bonding pads2PDa via a plurality of low speed first-layer wirings2d1a. The low speed first-layer wirings2d1aand low speed first via wirings2V1aform the above-mentioned low speed transmission path. As shown inFIG. 7, the first via wirings2V1include a plurality of high speed bonding pads2PDb and a plurality of high speed first via wirings2V1belectrically coupled to the high speed bonding pads2PDb. The high speed first via wirings2V1bform the above-mentioned high speed transmission path.

The first wiring layer WL1includes a conductive plane (first conductive plane)2PL1spaced apart from the first via wirings2V1around the first via wirings2V1. The first conductive plane2PL1is a plate-like conductive layer (metal layer, conductive pattern) patterned not to be in contact with the bonding pads2PD, the first-layer wirings2d1, and the first via wirings2V1. In this embodiment, the first conductive plane2PL1is formed to cover substantially the entire region of the upper surface2aof the wiring substrate2in which the bonding pads2PD, the first-layer wirings2d1, and the first via wirings2V1are not formed. The first conductive plane2PL1receives the supply of a power supply potential for driving the circuit formed in the semiconductor chip3shown inFIG. 4, or a ground potential (GND) as the reference potential. In the example shown inFIG. 5, the first conductive plane2PL1receives the supply of the ground potential to be supplied to the first and second circuits in common.

The first wiring layer WL1includes an insulating layer (first insulating layer, solder resist film)2e1covering a plurality of first via wirings2V1and the first conductive plane2PL1. As shown inFIG. 5, the first insulating layer2e1is formed to cover the entire upper surface2aof the wiring substrate2. As shown inFIG. 6, pad openings2ek1are respectively formed at the first insulating layer2e1in the regions of the upper surface2aof the wiring substrate2where the bonding pads2PD are formed. At least parts of the bonding pads2PD are exposed from the pad openings2ek1of the first insulating layer2e1. The protruding electrodes3BP shown inFIG. 4are electrically coupled to the bonding pads2PD via the pad openings2ek1shown inFIG. 6. In this way, the bonding pads2PD are respectively exposed from the first insulating layer2e1, so that the electrode pads3PD of the semiconductor chip3can be electrically coupled to the bonding pads2PD of the wiring substrate2as shown inFIG. 4.

A plurality of transmission paths included in the wiring substrate2include a transmission path (high speed transmission path) through which the differential signal is transmitted at a transmission rate of, for example, about 10 to 25 Gbps as described above. When the signal is transmitted at high speed in the transmission path in this way, the strip line wiring structure shown inFIG. 9has more advantages than the microstrip line wiring structure shown inFIG. 10.

In an example of the wiring structure shown inFIG. 9, the conductive planes2PLcu,2PLc1are respectively formed in an upper wiring layer located above the wiring2d, and a lower wiring layer located under the wiring2d. In other words, the wiring2dis sandwiched between the upper conductive plane2PLc1formed in the upper wiring layer, and the lower conductive plane2PLc2formed in the lower wiring layer in the cross-sectional side view. The conductive plane2PLcs is formed in the same wiring layer as the wiring2dto be spaced away from the wiring2d, and the surroundings of the wiring2dare enclosed by the conductive plane2PLcs. The thus-formed wiring structure shown inFIG. 9is called the “strip line”.

In an example of the wiring structure shown inFIG. 10, the conductive plane2PLc1is disposed in the wiring layer under the wiring2d. The conductive plane2PLcs is formed in the same wiring layer as the wiring2dto be spaced away from the wiring2d, and the surroundings of the wiring2dare enclosed by the conductive plane2PLcs. In an example of the wiring structure shown inFIG. 10, however, the wiring2dis formed in the uppermost wiring layer and no conductive plane is formed in the upper layer located above the wiring2d. The thus-formed wiring structure shown inFIG. 10is called the “microstrip line”.

In the microstrip line shown inFIG. 10, the conductive plane2PLc1is disposed in the position that is superimposed over the wiring2din the thickness direction under the wiring2d. Thus, an electric field or a magnetic field is less likely to expand under the wiring2d. Further, the conductive plane2PLcs is formed in the same wiring layer as the wiring2dto be spaced away from the wiring2d, and the surroundings of the wiring2dare enclosed by the conductive plane2PLcs. Thus, the electric field or the magnetic field is less likely to expand around the wiring2din the planar view. However, since a conductive plane is not formed above the wiring2d, the electric field or magnetic field is more likely to expand above the wiring2das compared to under the wiring2d. For this reason, the microstrip line shown inFIG. 10is more apt to be affected by exogenous noise, or noise transmitted from another wiring disposed near the line, as compared to the strip line shown inFIG. 9.

In order to improve the resistance to noise of a transmission path for a signal current, it is important to perform impedance matching in the transmission path. Particularly, the transmission of the differential signal requires a technique for matching the impedance between opposed signal wirings with high accuracy. When the transmission path for the signal tends to be affected by noise, jitter is caused by crosstalk or exogenous noise. Specifically, in order to increase a signal transmission rate, it is necessary to perform the impedance matching in the transmission path with high accuracy. Without taking the measures against noise, the quality of a transmitted signal might be degraded.

The transmission path to which the microstrip line shown inFIG. 10is applied is apt to be affected by noise. The microstrip line does not have a conductive plane on one side, and generally needs to include one thick line to achieve the adequate impedance matching, taking into consideration both the differential and common impedances, as compared to the strip line with the same material/thickness.

In contrast, for the strip line shown inFIG. 9, as mentioned above, the wiring2dis sandwiched between the conductive plane2PLcu formed in the upper wiring layer, and the conductive plane2PLc1formed in the lower wiring layer. Also, in the same wiring layer as that including the wiring2d, another conductive plane2PLcs is formed spaced apart from the wiring2d, and the surroundings of the wiring2dare enclosed by the conductive plane2PLcs. This wiring structure makes it difficult for the electric field or magnetic field to extend above, under, and around the wiring2d.

Under conditions with the same wiring width and arrangement distance, the strip line wiring structure shown inFIG. 9has the high resistance to noise as compared to the microstrip line wiring structure shown inFIG. 10. In other words, the strip line structure can have the smaller width of the wiring2dthan that of the microstrip line structure. For the strip line structure, the distance between the wirings2dcan be made smaller than that of the microstrip line structure. That is, the strip line structure enables the high density design of the high-speed signal path as compared to the microstrip line structure.

As mentioned above, among the transmission paths formed in the wiring substrate2of this embodiment, the transmission path including the high speed bonding pads2PDb and the high speed first via wirings2V1bas shown inFIG. 7needs the high speed transmission and high density design for achieving the impedance matching without being affected by noise, as compared to the transmission path including the low speed bonding pads2PDa, the low speed first-layer wirings2d1a, and the low speed first via wirings2V1aas shown inFIG. 6. The transmission path including the high speed bonding pads2PDb and the high speed first via wirings2V1bas shown inFIG. 7takes the strip line wiring structure described above.

Specifically, as shown inFIG. 8, a high speed first via wiring2V1bserves as an interlayer conductive path for electrically coupling the first wiring layer WL1to the second wiring layer WL2in the transmission path (high speed transmission path) including the high speed bonding pads2PDb. The high speed first via wiring2V1bis disposed in the vicinity of the high speed bonding pad2PDb. The high speed first via wiring2V1bis electrically coupled to the high speed bonding pad2PDb. The high speed second-layer wiring2d2bfor transmitting a signal at high speed is formed in the second wiring layer WL2. The first conductive plane2PL1is formed in the first wiring layer WL1, and the third conductive plane2PL3is formed in the wiring layer (third wiring layer) WL3in the positions where the respective conductive planes are superimposed over the high speed second-layer wirings2d2bin the thickness direction. In other words, in the cross-sectional side view, the high speed second-layer wiring2d2bis sandwiched between the first conductive plane2PL1of the first wiring layer WL1and the third conductive plane2PL3of the third wiring layer WL3. As shown inFIG. 13, the second conductive plane2PL2is formed around the second-layer wiring2d2to be spaced apart from the second-layer wiring2d2. The surroundings of the second-layer wiring2d2are enclosed by the second conductive plane2PL2. In this way, the use of the strip line wiring structure in the high speed transmission path whose transmission rate is very high enables the high density design of the high speed transmission path.

For example, the above microstrip line wiring structure seen inFIG. 10can be used in the transmission path including the low speed bonding pads2PDa, low speed first-layer wirings2d1a, and low speed first via wirings2V1a, that is, the low speed transmission path whose transmission rate is relatively lower, or the transmission path having a margin of the noise resistance. Thus, for example, as shown inFIG. 6, the low speed bonding pad2PDa and the low speed first via wiring2V1aare positioned to be separated by a distance relatively larger than that between the high speed bonding pad2PDb and the high speed first via wiring2V1bshown inFIG. 7. The low speed bonding pad2PDa is electrically coupled to the low speed first via wiring2V1avia the first-layer wiring2d1formed in the first wiring layer WL1. When a space can be ensured for arranging the low speed transmission path in the second wiring layer WL2, the low speed first-layer wiring2d1ashown inFIG. 6may be formed in the second wiring layer WL2.

Next, a wiring layer as the second layer (second wiring layer) WL2shown inFIG. 11includes a plurality of wirings (second-layer wirings)2d2electrically coupled to the first via wirings2V1, and a plurality of second via wirings2V2electrically coupled to the second-layer wirings2d2. As shown inFIG. 12, the second via wirings2V2include a plurality of low speed second via wirings2V2aelectrically coupled to the low speed first via wirings2V1aformed in the second wiring layer WL2(seeFIG. 6). The low speed second via wirings2V2aform the above-mentioned low speed transmission path. As shown inFIG. 13, the second via wirings2V2include the high speed second via wirings2V2belectrically coupled to the high speed first via wirings2V1bvia the high speed second wirings2d2b. The high speed second-layer wirings2d2band the high speed second via wirings2V2bform the above-mentioned high speed transmission path.

As mentioned above, the differential signal is transmitted to the high speed second-layer wirings2d2band the high speed second via wirings2V2b. Thus, among the high speed second-layer wirings2d2b, respective two high speed second-layer wirings2d2bthat achieve the impedance matching make a pair of wirings to form a differential pair. Thus, among the respective high speed second via wirings2V2b, two high speed second via wirings2V2bmake a pair of via wirings to form a differential pair.

As shown inFIG. 11, the second-layer wirings2d2are disposed not to be superimposed over the first-layer wirings2d1in the planar view. In other words, in the planar view, the second-layer wirings2d2do not intersect the first-layer wirings2d1. In an example shown inFIG. 11, the wiring substrate2has a quadrilateral shape in the planar view, and includes a first pair of sides2s1and2s2horizontally extending in the direction X and a second pair of sides2s3and2s4vertically extending in the direction Y perpendicular to the direction X. The first-layer wirings2d1are arranged to extend generally vertically towards the horizontally extending first pair of sides2s1or2s2from a chip mounting region of the center of the wiring substrate2in the planar view. The second-layer wirings2d2are arranged to extend generally horizontally towards the vertically extending second pair of sides2s3or2s4from the chip mounting region of the center of the wiring substrate2in the planar view.

In this way, the first-layer wiring2d1and the second-layer wiring2d2are respectively formed to extend toward the different sides, which can prevent the first-layer wiring2d1and the second-layer wiring2d2from intersecting each other. When the first-layer wiring2d1intersects the second-layer wiring2d2, the electric field or magnetic field caused in the first-layer wiring2d1can cause noise in the second-layer wiring2d2. That is, in this embodiment, the first-layer wiring2d1is disposed not to intersect the second-layer wiring2d2, which can improve the resistance to noise of the high speed transmission path formed of the high speed second-layer wirings2d2b.

The second wiring layer WL2includes a conductive plane (second conductive plane)2PL2disposed spaced away from the second-layer wirings2d2and second via wiring2V2, around the second-layer wirings2d2and second via wirings2V2. The second conductive plane2PL2is a plate-like conductive layer (metal layer, conductive pattern) patterned not to be in contact with the second-layer wirings2d2and the second via wirings2V2. The second conductive plane2PL2receives the supply of the power supply potential for driving the circuit formed in the semiconductor chip3shown inFIG. 4, or the grounding potential (GND) as the reference potential. In an example shown inFIG. 11, the second conductive plane2PL2receives the supply of the ground potential which is to be commonly supplied to the first and second circuits.

As mentioned above, this embodiment includes a reference path to which a reference potential for reference of the signal transmission path is supplied. For example, in this embodiment, the conductive planes2PL1and2PL3(seeFIG. 8) disposed above and below the second-layer wiring2d2, and the second conductive plane2PL2disposed around the second-layer wiring2d2mainly form a reference path. In an example shown inFIG. 13, the reference path via wirings2V2rare respectively disposed closest to the high speed second via wiring2V2bdisposed in one transmission path forming the differential pair, and the high speed second via wiring2V2bdisposed in the other transmission path. These reference path via wirings2V2rcorrespond to the mainly dominant via for reference.

When transmitting the differential signal in a transmission path including the high speed second via wiring2V2bshown inFIG. 13, a differential delay between one transmission path (for example, on a positive side) forming the differential pair, and the other transmission path (for example, on a negative side) is preferably reduced. For this reason, a distance between the transmission path on the positive side and the corresponding reference path is preferably set equal to that between the transmission path on the negative side and the corresponding reference path. In the example shown inFIG. 13, a first distance (for example, center-to-center spacing) L1from the high speed second via wiring2V2bdisposed in one transmission path forming the differential pair to the reference path via wiring2V2rfor reference disposed closest to the high speed second via wiring2V2bis equal to a second distance (for example, center-to-center spacing) L2from the high speed second via wiring2V2bdisposed in the other transmission path to the reference path via wiring2V2rfor reference disposed closest to the high speed second via wiring2V2b. This arrangement can reduce the differential delay between one transmission path (for example, on the positive side) and the other transmission path (for example, on the negative side) forming the differential pair to thereby prevent or suppress the difference in skew between the positive and negative sides.

Referring toFIG. 13, for easy understanding, each transmission path is provided with one reference path via wiring2V2rforming the reference path, but a plurality of reference path via wirings2V2rcan be disposed in each transmission path. In this case, the reference path via wirings2V2rdisposed around one high speed second via wiring2V2b(for example, on the positive side) are arranged to be symmetric with respect to the reference path via wirings2V2rdisposed around the other high speed second via wiring2V2b(for example, on the negative side), which can reduce the differential delay described above. As shown inFIG. 13, other second via wirings2V2can be connected in addition to the above reference path via wiring2V2rfor reference.

In the example shown inFIG. 13, at the second conductive plane2PL2, the first via wirings2V1and the second via wirings2V2are alternatively arranged along the high speed transmission path formed of a pair of paths.FIG. 13illustrates one typical high speed transmission path. However, the same goes for other high speed transmission paths. In this way, the first via wirings2V1and the second via wirings2V2are arranged along the one high speed transmission path forming a pair of paths, which can guard the high speed signal, and can also suppress the noise caused by resonance of the conductive plane.

The second wiring layer WL2includes an insulating layer (second insulating layer)2e2covering the second via wirings2V2and the second conductive plane2PL2. As shown inFIG. 11, the second insulating layer2e2is formed to cover the entire second wiring layer WL2of the wiring substrate2. For example, as shown inFIG. 8, the first via wiring2V1serving as an interlayer conductive path for electrically coupling the first wiring layer WL1shown inFIG. 5to the second wiring layer WL2shown inFIG. 11is formed to penetrate the second insulating layer2e2. In this way, the bonding pad2PD formed in the first wiring layer WL1can be electrically coupled to the second-layer wiring2d2formed in the second wiring layer WL2as shown inFIG. 8.

Next, a wiring layer as the third layer (third wiring layer) WL3shown inFIG. 14includes a plurality of through hole lands (first through hole lands, upper through hole lands)2TL1electrically coupled to the second via wirings2V2. As shown inFIG. 14, the first through hole lands2TL1include low speed first through hole lands2TL1aelectrically coupled to the low speed second via wirings2V2aformed in the second wiring layer WL2(seeFIG. 12). The low speed first through hole lands2TL1ahelp form the above-mentioned low speed transmission path. As shown inFIG. 15, the first through hole lands2TL1includes high speed first through hole lands2TL1belectrically coupled to the second via wirings2V2formed in the second wiring layer WL2(seeFIG. 13). The high speed first through hole lands2TL1bhelp form the above-mentioned high speed transmission path. As shown inFIGS. 15 and 16, the high speed first through hole lands2TL1bare respectively coupled to through main through hole wirings2TWb forming the high speed transmission path.

The high speed first through hole lands2TL1breceive the transmission of the differential signal as mentioned above. In the respective high speed first through hole lands2TL1b, two high speed second via wirings2V2bform a differential pair.

The third wiring layer WL3includes a conductive plane (third conductive plane)2PL3which is disposed around the first through hole lands2TL1, and is spaced apart from the first through hole lands2TL1. The third conductive plane2PL3is a plate-like conductive layer (metal layer, conductive pattern) patterned not to be in contact with the first through hole lands2TL1. In this embodiment, the third conductive plane2PL3is formed to cover the entire region of the third wiring layer WL3of the semiconductor substrate2where the first through hole lands2TL1are not formed. The third conductive plane2PL3receives the supply of the power supply potential for driving the circuit formed in the semiconductor chip3shown inFIG. 4, or the grounding potential (GND) as the reference potential. In the example shown inFIG. 14, the third conductive plane2PL3receives the supply of the ground potential which is to be commonly supplied to the first and second circuits via the through hole wirings2TW.

As shown inFIGS. 15 and 16, the third conductive plane2PL3formed in the third wiring layer WL3is provided with third layer openings2K3to separate the first through hole lands2TL1from the third conductive plane2PL3.

The third wiring layer WL3includes an insulating layer (third insulating layer)2e3covering the first through hole lands2TL1. As shown inFIGS. 14 and 15, the third insulating layer2e3is formed to cover the entire third wiring layer WL3of the wiring substrate2. For example, as shown inFIG. 16, the second via wiring2V2serving as an interlayer conductive path for electrically coupling the second wiring layer WL2shown inFIG. 11to the third wiring layer WL3shown inFIG. 14is formed to penetrate the third insulating layer2e3. In this way, as shown inFIG. 16, the second-layer wiring2d2formed in the second wiring layer WL2can be electrically coupled to the first through hole land2TL1formed in the third wiring layer WL3.

As shown inFIG. 16, the third wiring layer WL3is formed over an upper surface2Ca of the core insulating layer2CR. The core insulating layer2CR has the upper surface (first surface)2Ca with the third wiring layer WL3formed thereover, and a lower surface (second surface)2Cb positioned opposite to the upper surface2Ca. The core insulating layer2CR includes a plurality of through holes2TH (seeFIG. 15) formed to penetrate the layer and extending between the upper first surface2Ca and the lower second surface2Cb. The core insulating layer2CR also has through hole wirings2TW formed to cover the inner walls of the through holes2TH. The through hole wirings2TW are integrally formed with the first through hole land2TL1formed at the upper first surface2Ca of the core insulating layer2CR, and the second through hole land2TL2(lower through hole land) formed at the lower second surface2Cb of the core insulating layer2CR.

The core insulating layer2CR is used as the base when forming the wiring substrate2, for example, by a build-up method. Thus, the thickness of the core insulating layer2CR is larger than that of each of the other insulating films2e1,2e2,2e3,2e4,2e5, and2e6. In the example shown inFIG. 16, the thickness of each of the insulating layers2e2,2e3,2e4, and2e5is in a range of about 30 to 35 μm. In contrast, the thickness of the core insulating layer2CR is, for example, in a range of about 200 to 800 μm.

As mentioned above, this embodiment includes a reference path to which a reference potential for reference of the signal transmission path is supplied. For example, referring toFIG. 15which is an enlarged plan view of a portion ofFIG. 14, reference through hole wirings2TWr are positioned closest to the first main through hole wiring2TWb1disposed in one transmission path forming the differential pair, and the second main through hole wiring2TWb2disposed in the other transmission path. The reference through hole wiring2TWr corresponds to the mainly dominant through hole wiring for reference.

As mentioned above, in transmitting a differential signal, a distance between the transmission path on the positive side and the corresponding reference path is preferably set equal to that between the transmission path on the negative side and the corresponding reference path from the viewpoint of reducing a differential delay between one transmission path (for example, on the positive side) and the other path (for example, on the negative side) which form the differential pair. Specifically, as mentioned above, the thickness of the core insulating layer2CR is more than the thickness of each of other insulating layers2e2,2e3,2e4, and2e5. The through hole wiring2TW is largely affected by the connection distance in the thickness direction of the wiring substrate2rather than by the second via wiring2V2shown inFIG. 13. The asymmetric structure tends to lead to a difference in skew or generation of jitter.

In this embodiment, as shown inFIG. 15, the reference through hole wirings2TWr are arranged such that the distance between the transmission path on the positive side and the reference path is preferably set equal to that between the transmission path on the negative side and the corresponding reference path. Specifically, a first distance (for example, center-to-center spacing) L1from the first main through hole wiring2TWb1disposed in one transmission path forming the differential pair to the first reference through hole wiring2TWr1for reference disposed closest to the through hole wiring first main2TWb1is equal to a second distance (for example, center-to-center spacing) L2from the second main through hole wiring2TWb2disposed in the other transmission path to the second reference through hole wiring2TWr2for reference disposed closest to the second main through hole wiring2TWb2. This arrangement can reduce a differential delay between the one transmission path (for example, on the positive side) and the other transmission path (for example, on the negative side) which form the differential pair to thereby prevent or suppress the difference in skew between the positive and negative sides, so that the impedance of the through hole portion on the positive side can be matched with that on the negative side.

FIG. 15shows one transmission path forming the differential pair, by way of example. As shown inFIG. 14, each of the high speed transmission paths is provided with the reference through hole wiring2TWr forming the reference path, likeFIG. 15.

Then, a fourth wiring layer (fourth wiring layer) WL4is formed over the lower surface2Cb of the core insulating layer2CR. As shown inFIG. 17, the fourth wiring layer WL4includes through hole lands (second through hole lands, lower through hole lands)2TL2. The second through hole lands2TL2are respectively formed integrally with the through holes2TH shown inFIG. 16. The second through hole lands2TL2include low speed second through hole lands2TL2aelectrically coupled to the low speed first through hole lands2TL1ashown inFIG. 14. The low speed second through hole lands2TL2ahelp form the above-mentioned low speed transmission path. The second through hole lands2TL2include high speed second through-hole lands2TL2belectrically coupled to the high speed first through hole lands2TL1bshown inFIG. 14. The high speed second through hole lands2TL2bhelp form the above-mentioned high speed transmission path.

The low speed second through hole lands2TL2aare electrically coupled to the low speed third via wirings2V3a. The high speed second through hole lands2TL2bare electrically coupled to the high speed third via wirings2V3b.

The fourth wiring layer WL4includes a conductive plane (fourth conductive plane)2PL4which is disposed around the second through hole lands2TL2, and is spaced apart from the second through hole land2TL2. The fourth conductive plane2PL4is a plate-like conductive layer (metal layer, conductive pattern) patterned not to be in contact with the second through hole lands2TL2. In this embodiment, the fourth conductive plane2PL4is formed to cover the entire region of the fourth wiring layer WL4of the semiconductor substrate2where the second through hole lands2TL2are not formed. In this embodiment, the fourth conductive plane2PL4receives the supply of power supply potential for driving the circuit formed in the semiconductor chip3shown inFIG. 4, or the ground potential (GND) as the reference potential.

In the example shown inFIG. 17, the ground potential is supplied to the fourth conductive plane2PL4at the peripheral edge of the wiring substrate2, and the power supply potential is supplied to the fourth conductive plane2PL4at the center of the wiring substrate2. In other words, a central conductive plane2PLv for a power supply potential is disposed at the center of the fourth wiring layer WL4shown inFIG. 17. The power supply potential for driving the circuit formed in the semiconductor chip3shown inFIG. 4is supplied to the central conductive plane2PLv for a power supply potential. A peripheral conductive plane2PLg for a reference potential is disposed at the peripheral edge of the fourth wiring layer WL4. The reference potential for driving the circuit formed in the semiconductor chip3shown inFIG. 4is supplied to the peripheral conductive plane2PLg. In order to supply the potential in common to the circuits, the central conductive plane2PLv for the power supply potential can be shared among the circuits. In order to supply different potentials to the circuits formed in the semiconductor chip3, the peripheral conductive plane2PLv for the power supply potential shown inFIG. 17may be divided into a plurality of parts, which are electrically separated from each other.

The fourth wiring layer WL4includes an insulating layer (fourth insulating layer)2e4covering the second through hole lands2TL2. As shown inFIG. 17, the fourth insulating layer2e4is formed to cover the entire fourth wiring layer WL4of the wiring substrate2. For example, the third via wiring2V3serving as an interlayer conductive path for electrically coupling the fourth wiring layer WL4shown inFIG. 16to the fifth wiring layer WL5is formed to penetrate the fourth insulating layer2e4. Thus, as shown inFIG. 16, the fifth layer wiring2d3formed in the fifth wiring layer WL5can be electrically coupled to the second through hole land2TL2formed in the fourth wiring layer WL4by means of the third via wiring2V3.

Next, a wiring layer as a fifth layer (fifth wiring layer) WL5shown inFIGS. 16 and 18is formed as a lower layer under the fourth wiring layer WL4. The fifth wiring layer WL5includes a plurality of via wirings (third via wirings)2V3electrically coupled to the second through hole lands2TL2shown inFIG. 17, and a plurality of wirings (fifth layer wirings)2d3electrically coupled to the third via wirings2V3. As shown inFIG. 17, the third via wirings2V3include a plurality of low speed third via wirings2V3aelectrically coupled to the low speed second through hole lands2TL2aformed in the fourth wiring layer WL4shown inFIG. 17. A plurality of fifth layer wirings2d3include low speed fifth layer wirings2d3aelectrically coupled to the low speed third via wirings2V3a. The low speed fifth layer wirings2d3aand the low speed third via wirings2V3aform the above-mentioned low speed transmission path.

As shown inFIG. 17, the third via wirings2V3include a plurality of high speed third via wirings2V3belectrically coupled to the high speed second through hole lands2TL2bformed in the fourth wiring layer WL4shown inFIG. 17. The fifth layer wirings2d3include high speed fifth layer wirings2d3belectrically coupled to the high speed third via wirings2V3b. The high speed fifth layer wirings2d3band the high speed third via wirings2V3bform the above-mentioned high speed transmission path.

As mentioned above, the differential signal is transmitted to the high speed fifth layer wirings2d3band the high speed third via wirings2V3b. Thus, among the respective high speed fifth layer wirings2d3b, two high speed fifth layer wirings2d3bthat achieve the impedance matching make a pair of wirings to form a differential pair. Thus, among the respective high speed third via wirings2V3b, two high speed third via wirings2V3bmake a pair of via wirings to form a differential pair.

Specifically, as shown inFIG. 16, the fifth layer wirings2d3are electrically coupled to the fourth via wirings2V4, which serves as an interlayer conductive path for electrically coupling the sixth wiring layer WL6to the fifth wiring layer WL5.

As shown inFIG. 18, in the planar view, the fifth layer wirings2d3are disposed not to be superimposed over the first-layer wirings2d1shown inFIG. 5. In other words, the fifth layer wirings2d3do not intersect the first-layer wirings2d1shown inFIG. 5in the planar view. In this way, the high speed fifth layer wirings2d3bare arranged not to intersect the first-layer wirings2d1, which can improve the resistance to noise of the high speed transmission path formed of the high speed fifth layer wirings2d3b.

The fifth wiring layer WL5includes a conductive plane (fifth conductive plane)2PL5which is disposed around the fifth layer wirings2d3and the third and fourth via wirings2V3,2V4, respectively, and is spaced apart from the fifth layer wirings2d3and the third and fourth via wirings2V3,2V4. The fifth conductive plane2PL5is a plate-like conductive layer (metal layer, conductive pattern) patterned not to be in contact with the fifth layer wirings2d3and the third and fourth via wirings2V3,2V4. The fifth conductive plane2PL5receives the supply of the power supply potential for driving the circuit formed in the semiconductor chip3shown inFIG. 4, or the ground potential (GND) as the reference potential. In an example shown inFIG. 18, the firth conductive plane2PL5receives the supply of the ground potential which is to be commonly supplied to the first and second circuits.

The fifth wiring layer WL5includes an insulating layer (fifth insulating layer)2e5covering the fifth layer wirings2d3, the third and fourth via wirings2V3,2V4, and the fifth conductive plane2PL5. As shown inFIG. 18, the fifth insulating layer2e5is formed to cover the entire fifth wiring layer WL5of the wiring substrate2. The fourth via wiring2V4, serving as an interlayer conductive path for electrically coupling the fifth wiring layer WL5to the sixth wiring layer WL6as shown inFIG. 16, is formed to penetrate the fifth insulating layer2e5. As shown inFIG. 16, the fifth layer wiring2d3formed in the fifth wiring layer WL5can be electrically coupled to the ball lands2LD formed in the sixth wiring layer WL6.

Although not shown in the figure, also in the fifth wiring layer WL5, the fourth via wirings2V4for reference are respectively disposed in the high speed transmission paths such that the distance between the transmission path on the positive side and the main dominant reference path forming the differential pair is equal to that between the transmission path on the negative side and the main dominant reference path. The structure of the fourth via wiring2V4for reference has the same as that of the reference path via wiring2V2rfor reference described usingFIG. 13, and thus a repeated description thereof will be omitted.

Next, a wiring layer as a sixth layer (sixth wiring layer) WL6shown inFIG. 19is formed as a lower layer under the fifth wiring layer WL5. The sixth wiring layer WL6includes a plurality of via wirings (fourth via wirings)2V4electrically coupled to the third via wirings2V3shown inFIG. 18, and a plurality of ball lands2LD electrically coupled to the fourth via wirings2V4. The fourth via wirings2V4include a plurality of low speed fourth via wirings2V4aelectrically coupled to the low speed third via wirings2V3aformed in the fifth wiring layer WL5shown inFIG. 18. The low speed fourth via wirings2V4aand the low speed ball lands2LDa electrically coupled to the low speed fourth via wirings2V4aform the above-mentioned low speed transmission path.

As shown inFIG. 18, the fourth via wirings2V4include a plurality of high speed fourth via wirings2V4belectrically coupled to the high speed third via wirings2V3bformed in the fifth wiring layer WL5shown inFIG. 18. The high speed fourth via wirings2V4band the high speed ball lands2LDb electrically coupled to the high speed fourth via wirings2V4bform the above-mentioned high speed transmission path.

As mentioned above, the differential signal is transmitted to the high speed ball lands2LDb and the high speed fourth via wirings2V4b. In the respective high speed fourth via wirings2V4b, two high speed fourth via wirings2V4bform a differential pair. In the respective high speed ball lands2LDb, two high speed ball lands2LDb form a differential pair.

The sixth wiring layer WL6includes the conductive plane (sixth conductive plane)2PL6which is disposed around the ball lands2LDa and2LDb and fourth via wirings2V4aand2V4b, and is spaced apart from the ball lands2LDa and2LDb and fourth via wirings2V4aand2V4b. The sixth conductive plane2PL6is a plate-like conductive layer (metal layer, conductive pattern) patterned not to be in contact with the ball lands2LDa and2LDb and fourth via wirings2V4aand2V4b. The sixth conductive plane2PL6receives the supply of the power supply potential for driving the circuit formed in the semiconductor chip3shown inFIG. 4, or the grounding potential (GND) as the reference potential. In an example shown inFIG. 19, the sixth conductive plane2PL6receives the supply of the ground potential which is to be commonly supplied to the first and second circuits.

The sixth wiring layer WL6includes the insulating layer (sixth insulating layer, solder resist film)2e6covering the ball lands2LD, fourth via wirings2V4, and sixth conductive plane2PL6. As shown inFIG. 19, the sixth insulating layer2e6is formed to cover the entire lower surface2bof the wiring substrate2. In regions with the ball lands2LD formed therein in the lower surface2bof the wiring substrate2, land openings2ek2are formed in the sixth insulating layer2e6as shown inFIG. 16. The ball lands2LD are exposed from the land openings2ek2of the sixth insulating layer2e6. In this way, the ball lands2LD are exposed from the sixth insulating layer2e6, so that the solder balls4can be connected to the exposed surfaces of the ball lands2LD.

In this embodiment, a plurality of land openings2ek2are formed in the sixth insulating film2e6covering the sixth conductive plane2PL6. A part of the sixth conductive plane2PL6is exposed from each land opening2ek2. In other words, the exposed parts of the sixth conductive plane2PL6serves as a land (terminal) that receives the supply of power supply potential for driving the circuit formed in the semiconductor chip3shown inFIG. 4, or the ground potential (GND) as the reference potential. That is, the solder ball4shown inFIG. 4is bonded to the exposed part of the sixth conductive plane2PL6, which is used as a terminal for supplying the power supply potential or reference potential.

As shown inFIG. 20, among the solder balls4, reference potential solder balls4r1and4r2for reference to which the reference potential is supplied are disposed around the high speed solder balls4b1and4b2forming the high speed transmission path for transmitting the above-mentioned differential signal.FIG. 20shows an enlarged plan view of the details of a layout of the solder balls shown inFIG. 2. As shown inFIG. 20, in order to distinguish the high speed solder balls4b1and4b2forming a differential pair from the reference potential solder balls4r1and4r2forming the reference path, the high speed solder balls4b1and4b2are represented by hatching, and the reference potential solder balls4r1and4r2are represented by a dot pattern.

As shown inFIG. 20, the high speed solder balls4b1and4b2form one differential pair. The reference potential solder ball4r1forms the main dominant reference path corresponding to the high speed solder ball4b1, while the reference potential solder ball4r2forms the main dominant reference path corresponding to the high speed solder ball4b2.

As mentioned above, this embodiment includes the reference path to which the reference potential for reference of the signal transmission path is supplied. For example, in describing with reference toFIG. 15, the reference through hole wirings2TWr1,2Twr2are respectively disposed closest to the first main through hole wiring2TWb1disposed in one transmission path forming the differential pair, and the second main through hole wiring2TWb2disposed in the other transmission path. These reference through hole wirings2TWr correspond to the mainly dominant vias for reference.

As mentioned above, in transmitting a differential signal, the distance between the transmission path on the positive side and the main dominant reference path is preferably set equal to that between the transmission path on the negative side and the corresponding main dominant reference path from the viewpoint of performing impedance matching and reducing a differential delay between the one transmission path (for example, on the positive side) and the other transmission path (for example, on the negative side) forming the differential pair. Specifically, the solder balls4are more likely to be affected by the connection distance in the thickness direction of the wiring substrate2(in the height direction of the solder ball4) rather than by the position and configuration of second via wiring2V2shown inFIG. 13. The asymmetric structure might tend to cause the jitter or the difference in skew.

In this embodiment, as shown inFIG. 20, the reference potential solder balls4rare arranged such that the distance between the transmission path on the positive side and the main dominant reference path is preferably set equal to that between the transmission path on the negative side and the corresponding main dominant reference path. A distance (for example, center-to-center spacing) L1from the high speed solder ball4b1disposed in one transmission path forming the differential pair to the mainly dominant reference potential solder ball4r1for reference disposed closest to the high speed solder ball4b1is equal to a distance (for example, center-to-center spacing) L2from the high speed solder ball4b2disposed in the other transmission path to the mainly dominant reference potential solder ball4r2for reference disposed closest to the high speed solder ball4r2. This arrangement can reduce a differential delay between one transmission path (for example, on a positive side), and the other transmission path (for example, on a negative side) forming the differential pair to thereby prevent or suppress the difference in skew between the positive and negative sides, which can match the impedances.

As shown inFIG. 20, likeFIG. 15, the reference potential solder balls4rforming the reference path are formed in the respective high speed transmission paths. This arrangement can prevent or suppress the difference in skew between the positive and negative sides in the respective transmission paths.

<Impedance Matching of High Speed Transmission Path>

Further, the impedance matching of the high speed transmission path will be described in detail below.FIG. 21exemplarily shows an explanatory diagram of an interconnection structure of a high speed transfer path shown inFIG. 16.FIG. 22shows an explanatory diagram of a comparative example to be compared with the interconnection structure ofFIG. 21.FIG. 23shows an enlarged plan view of conductive patterning of the first wiring layer in the enlarged plane shown inFIG. 15.FIG. 24shows an enlarged plan view of the patterning of a conductor of the second wiring layer in the enlarged plane shown inFIG. 15.FIG. 25shows an explanatory diagram of another comparative example to be compared with the interconnection structure ofFIG. 21.

Referring toFIGS. 23 and 24, in order to clarify the planar positional relationship between the main first opening2K1cand the high speed second opening2K2bformed in their respective wiring layers, and the high speed first through hole land2TL1b, high speed second via wiring2V2b, and high speed second-layer wiring2d2b, the contour of the conductive pattern formed in wiring layers other than the wiring layer shown is represented by the two-dot chain line. Specifically, referring toFIG. 23, in order to clarify the magnitude relationship based on a plane area of each of the main first openings2K1cand the high speed ball lands2LDb, the contour of the ball land2LD formed in the sixth wiring layer WL6is indicated by the two-dot chain line likeFIG. 16.FIGS. 23 and 24, which are enlarged plan views, illustrates the conductive patterns, including the wiring, via wiring, through hole land, and conductive plane, by hatching in order to clearly indicate the boundary between the conductive patterns.

As described above usingFIGS. 9 and 10, in a high speed transmission path through which the signal is transmitted at a transmission rate of about 10 to 25 Gbps, the conductive plane2PL to which the reference potential or power supply potential is supplied is disposed around the wiring2d(upper layer, lower layer, or its surroundings in the planar view), which can reduce the influences of the electric field or magnetic field from the surroundings of the transmission path. The use of the strip line wiring structure shown inFIG. 9can narrow the width of the wiring, and also can decrease the distance between the wirings2d, thereby increasing the density of the wiring layout.

As mentioned above, in order to reduce the influence of noise due to the electric field or magnetic field from the surroundings of the high speed transmission path, the distance between each of the conductive planes2PL1,2PL2,2PL3,2PL4,2PL5, and2PL6disposed around the high speed transmission path, and the corresponding high speed transmission path is proposed to be decreased as much as possible, like the wiring substrate2A shown inFIG. 22. In this case, the conductive planes2PL1and2PL2are also arranged in the positions where the planes are superimposed over the first through hole lands2TL1in the thickness direction. However, when the conductive planes2PL1and2PL2are arranged in the positions where the planes are superimposed over the first through hole lands2TL1in the thickness direction, a parasitic capacitance is generated between each of the conductive planes2PL1and2PL2and the corresponding high speed transmission path. For easy understanding,FIG. 22shows the wiring layers WL2, WL3, WL4, and WL5thicker than the actual thickness. The thickness of the insulating layer of each of the wiring layers WL2, WL3, WL4, and WL5is in a range of about 30 to 35 μm, while the conductor-to-conductor distance in the planar direction is about 50 μm. That is, in the wiring layers WL2, WL3, WL4, and WL5, the parasitic capacitance is apt to be generated by the influence in the thickness direction and not in the planar direction.

In order to ensure the reliability of electric coupling, the planar size of the first through hole land2TL1is larger than that of the wiring2d. For example, the width of the wiring2dis about 25 whereas the diameter of the first through hole land2TL1is in a range of about 400 to 500 μm. Thus, a parasitic capacitance Ct generated in the thickness direction of the wiring substrate2A tends to be larger than a parasitic capacitance Cp generated in the planar direction of the wiring substrate2.

The parasitic capacitance Ct generated around the first through hole land2TL1in the high speed transmission path in this way might cause the degradation of reflection due to the mismatching of the impedance. Thus, like the wiring substrate2of this embodiment shown inFIG. 21, preferably, the conductive planes2PL1and2PL2are not preferably provided in the positions where the planes are not superimposed over the first through hole land2TL1in the thickness direction.

That is, as shown inFIGS. 21 and 23, the opening (main first opening)2K1cis preferably formed in the first conductive plane2PL1of the first wiring layer WL1in the positions where the opening is superimposed over the high speed first through hole land2TL1bin the thickness direction. As shown inFIGS. 21 and 24, another opening (high speed second opening)2K2bis preferably formed in the second conductive plane2PL2of the second wiring layer WL2in the positions where the opening is superimposed over the high speed first through hole land2TL1bin the thickness direction.

In contrast, the high speed second-layer wiring2d2b(seeFIG. 21) forming the high speed transmission path uses the strip line wiring structure described above so as to provide the design with a uniform impedance. In order to achieve the differential impedance matching, the wiring structures of the transmission paths are preferably the same. In the respective wiring layers, the conductive planes2PL1,2PL2,2PL3,2PL4,2PL5, and2PL6to which the reference potential or power supply potential is supplied preferably intervene in between the high speed transmission paths at the respective wiring layers. Thus, in order to ensure the differential/common impedance matching of the high speed transmission path, while increasing the density of the wiring layout, like the wiring substrate2of this embodiment shown inFIG. 21, the distance between the high speed second-layer wiring2d2band each of the conductive planes2PL1,2PL2, and2PL3, that is, the distance between the conductive patterns is preferably set small.

As shown inFIG. 23, an area of the main first opening2K1cis larger than a plane area of the high speed first through hole land2TL1b. Thus, in the plane area, the high speed first through hole land2TL1bis positioned within the main first opening2K1c. As shown inFIG. 24, the area of the high speed second opening2K2bis larger than the plane area of the high speed first through hole land2TL1b. In this embodiment, the main first opening2K1cshown inFIG. 23has the same shape and area as those of the high speed second opening2K2bshown inFIG. 24. The main first opening2K1cand the high speed second opening2K2bare arranged to have their contours superimposed on each other in the planar view. Thus, in the planar view, the high speed first through hole land2TL1bis positioned within the high speed second opening2K2b. As shown inFIGS. 23 and 24, the high speed second via wirings2V2bare formed within the openings2K1cand2K2b. This arrangement can greatly decrease the parasitic capacitance Ct generated in the thickness direction of the wiring substrate2A as shown inFIG. 22.

The first conductive plane2PL1is provided with an opening2K1in addition to the main first opening2K1cshown inFIG. 23. For example, a low speed first opening2K1ais formed in the first conductive plane2PL1disposed around the low speed first via wiring2V1ashown inFIG. 6. For example, a high speed first opening2K1bis formed in the first conductive plane2PL1disposed around the high speed first via wiring2V1bshown inFIG. 7. The main first opening2K1cshown inFIG. 23has its opening area determined according to a plane area of the high speed first through hole land2TL1b. Each of the low speed first and high speed first openings2K1aand2K1bshown inFIG. 6 or 7has its opening area determined according to a plane area of each of the first via wirings2V1aand2V1b. The area of the main first opening2K1cis larger than that of each of the low speed first and high speed first openings2K1aand2K1b.

In order to increase the density of the wiring layout by getting the conductive planes2PL1,2PL2, and2PL3close to the wiring2d, the area of the main first opening2K1cis preferably small.

In this embodiment, as shown inFIG. 23, the plane area of the high speed ball land2LDb having the circular shape in the planar view is larger than the plane area of the high speed first through hole land2TL1bhaving the circular shape in the planar view. The area of the main first opening2K1cin the planar view is smaller than the plane area of the high speed ball land2LDb. For example, in one embodiment, the high speed first through hole land2TL1bhas a diameter of 450 whereas the high speed ball land2LDb has a diameter of about 650 μm. The main first opening2K1chas a diameter of, for example, about 500 to 600 μm. In other words, in this embodiment, the area of the main first opening2K1cis minimized as long as the main first opening2K1cis not superimposed over the high speed first through hole land2TL1bin the thickness direction. Thus, a large part of the high speed second-layer wirings2d2bshown inFIG. 23is covered with the first conductive plane2PL1. As a result, the density of the wiring layout can be increased, while ensuring the differential/common impedance matching in the high speed transmission path. That is, the semiconductor device can improve its resistance to noise and reflection characteristics.

As mentioned above, the main first opening2K1cshown inFIG. 23and the high speed second opening2K2bshown inFIG. 24have the same shape and area, and arranged such that the contours of the main first opening2K1cand the high speed second opening2K2bare superimposed over each other in the planar view. That is, in this embodiment, the area of the high speed second opening2K2bis larger than the plane area of the high speed first through hole land2TL1b, and smaller than the plane area of the high speed ball land2LDb shown inFIG. 23.

The second conductive plane2PL2is provided with an opening2K2in addition to the high speed second opening2K2bshown inFIG. 24. For example, the second conductive plane2PL2disposed around the low speed via wirings2V1aand2V2ashown inFIG. 12is provided with a low speed second opening2K2a. The high speed second opening2K2bshown inFIG. 24has its area determined according to the plane area of the high speed first through hole land2TL1b. The low speed second opening2K2ashown inFIG. 12has its area determined according to the plane area of each of the low speed via wirings2V1aand2V2a. Thus, the area of the high speed second opening2K2bis larger than that of the low speed second opening2K2a.

As mentioned above, the area of the high speed second opening2K2bof the second conductive plane2PL2formed in the second wiring layer WL2shown inFIG. 24is minimized as long as the high speed second opening2K2bis not superimposed over the high speed first through hole land2TL1bin the thickness direction. For example, as shown inFIG. 13, when the high speed transmission path of the second wiring layer WL2has a high density, an increase in area of the high speed second opening2K2bcauses the high speed second-layer wiring2d2bof the adjacent transmission path to be superimposed over the high speed second opening2K2b, which makes it difficult to surely dispose the second conductive plane2PL2in between the adjacent transmission paths. In other words, the above states makes it difficult to increase the density of the high speed transmission path.

In this embodiment, the area of the high speed second opening2K2bis minimized as long as the opening is not superimposed over the high speed first through hole land2TL1bin the thickness direction. Then, when increasing the density of the high speed transmission path in the second wiring layer WL2, the second conductive plane2PL2can be surely disposed in between the adjacent transmission paths.FIG. 13shows the example in which the differential signal is allowed to flow through the high speed transmission path, so that two signal wirings forming one pair serves as one high speed transmission path (differential pair). Thus, the second conductive plane2PL2is not disposed between the signal wirings forming the differential pair. The above expression “the second conductive plane2PL2is disposed in between the adjacent transmission paths” can be replaced by an expression “the second conductive plane2PL2is disposed between the adjacent differential pairs”.

In this way, the second conductive plane2PL2to which the power supply potential or reference potential (for example, ground potential) is supplied is disposed in between the adjacent transmission paths (differential pair), which can reduce the interaction between the adjacent differential pair. As a result, the high speed transmission path can improve its resistance to noise.

In this embodiment, as shown inFIG. 16, the first insulating layer2e1is embedded in the entire inside of the main first opening2K1cof the first conductive plane2PL1. In other words, as shown inFIG. 23, no conductive pattern is disposed within the main first opening2K1cof the first conductive plane2PL1. As shown inFIG. 16, the insulating layers2e2and2e3are entirely embedded in the surroundings of the high speed second via wiring2V2band the high speed second-layer wiring2d2bwithin the main first opening2K1cof the first conductive plane2PL1. As shown inFIG. 24, no conductive pattern other than the high speed second via wiring2V2band the high speed second-layer wiring2d2bis disposed within the high speed second opening2K2bof the second conductive plane2PL2.

The inventors of the present application have studied embodiments in which a floating conductive pattern2FL electrically separated from the conductive planes2PL1and2PL2and the high speed transmission path is disposed within the openings2K1cand2K2b, like a wiring substrate2B shown inFIG. 25. When the conductive patterns2FL are provided inside the openings2K1cor2K2b, like the wiring substrate2B shown inFIG. 25, the conductor density of the respective wiring layers can be made more uniform to improve the workability of the wiring substrate. The conductive pattern2FL is disposed spaced apart from the conductive planes2PL1and2PL2or the high speed transmission path (for example, high speed second-layer wiring2d2bor high speed second via wiring2V2b), which can decrease the parasitic capacitance Ct generated in the thickness direction of the wiring substrate2A as shown inFIG. 22.

As can be seen from the result of the studies performed by the inventors of the present application, the provision of the conductive pattern2FL inside the opening2K1cor2K2breduces the resistance to noise at high frequency due to the influence of electromagnetic waves in an environment where the semiconductor device1(seeFIGS. 1 to 4) is set. This is because the conductive pattern2FL disposed in the openings2K1cand2K2bcan serve as an antenna in a high frequency band.

In the shown inFIG. 16, the first insulating layer2e1is embedded inside the entire main first opening2K1cof the first conductive plane2PL1. The second insulating layer2e2is entirely embedded in a region in the vicinity of the high speed second via wiring2V2band the high speed second-layer wiring2d2bwithin the main first opening2K1cof the first conductive plane2PL1. In other words, over the high speed first through hole land2TL1b, there is no conductor other than the conductor (high speed second-layer wiring2d2band high speed second via wiring2V2b) electrically coupled to the high speed first through hole land2TL1b. This reduces the influence of the electromagnetic wave on the setting environment of the semiconductor device1(seeFIGS. 1 to 4), which can improve the resistance to noise of the semiconductor device1.

<Parasitic Capacitance on Mounting Surface Side>

The parasitic capacitance generated around the high speed first through hole land2TL1bwill be described below. In order to easily perform the impedance matching in the high speed transmission path, the parasitic capacitance formed on the lower mounting surface side (on the lower surface2Cb side shown inFIG. 16) of the core insulating layer2CR can also be preferably decreased. The following will refer to a detailed structure in which the parasitic capacitance formed on the lower mounting surface side (on the lower surface2Cb side shown inFIG. 16) of the core insulating layer2CR is also decreased.

FIG. 26shows an enlarged plan view of the conductive patterning of the fourth wiring layer in the enlarged plane shown inFIG. 15.FIG. 27shows an enlarged plan view of the conductive patterning of the fifth wiring layer in the enlarged plane shown inFIG. 15.FIG. 28shows an enlarged plan view of the conductive patterning of the sixth wiring layer in the enlarged plane shown inFIG. 15.

Referring toFIGS. 26 and 27, in order to clarify the planar positional relationship between the fourth-layer opening2K4A and the fifth-layer opening2K5A formed in their respective wiring layers, and the high speed second through hole land2TL2b, high speed via wirings2V3band2V4b, and high speed ball land2LDb, the contour of the conductive pattern formed in wiring layers other than the wiring layer shown is represented by the two-dot chain line. Like the reference path via2V2rfor reference described usingFIG. 13,FIG. 27also shows reference path vias2V4rfor reference included in the reference path of the high speed transmission path for transmitting the differential signal, by a dotted line.FIGS. 26 to 28are enlarged plan views, but hatching is added to the conductive patterns, including the wirings, the via wirings, the through hole lands, the lands, and the conductive planes in order to clarify the boundary between the conductive patterns.

As shown inFIG. 16, the through hole wiring2TW integrally formed with the high speed first through hole land2TL1bextends along a thickness direction of the wiring substrate2. A high speed second through hole land2TL2bformed on the lower surface2Cb side of the core insulating layer2CR is formed to be opposed to the high speed first through hole land2TL1bvia the core insulating layer2CR. As shown inFIG. 26, the fourth conductive plane2PL4formed in the fourth wiring layer WL4is provided with an opening (fourth-layer opening)2K4A disposed not to bring the high speed second through hole land2TL2binto contact with the fourth conductive plane2PL4.

As shown inFIG. 27, the fifth conductive plane2PL5formed in the fifth wiring layer WL5is provided with an opening (fifth-layer opening)2K5A disposed not to bring the fifth conductive plane2PL5into contact with the high speed via wirings2V3band2V4b.

As shown inFIG. 28, the sixth conductive plane2PL6formed in the sixth wiring layer WL6is provided with a sixth layer opening2K6A disposed not to bring the sixth conductive plane2PL6into contact with the via wiring2V4band the high speed ball land2LDb.

In this embodiment, for example, the shape and area of the fifth-layer opening2K5A shown inFIG. 27, and the shape and area of the fourth-layer opening2K4A shown inFIG. 26are the same shape (for example, circular shape) and area of the sixth layer opening2K6A shown inFIG. 28. In the planar view, the contour of the fourth-layer opening2K4A, the contour of the fifth-layer opening2K5A, and the contour of the sixth layer opening2K6A are respectively formed to be superimposed over each other.

In this embodiment, as shown inFIG. 16, the high speed second through hole land2TL2bis superimposed over the high speed ball land2LDb in the thickness direction. As shown inFIG. 26, the plane area of the high speed ball land2LDb is larger than that of the high speed second through hole land2TL2b. The plane shape and area of the high speed second through hole land2TL2bshown inFIG. 26are the same as those of the high speed first through-hole land2TL1bshown inFIG. 15. In the planar view, for example, the high speed first through hole land2TL1band the high speed second through hole land2TL2bare arranged so as to have their contours superimposed with each other. Thus, in order to decrease the parasitic capacitance Ct formed in the thickness direction ofFIG. 22, the high speed ball land2LDb whose plane area is larger than that of the high speed second through hole land2TL2bis preferably arranged not to be superimposed over the fourth and fifth conductive planes2PL4and2PL5in the thickness direction. That is, when the high speed second through hole land2TL2bis superimposed over the high speed ball land2LDb in the thickness direction, the area of each of the openings2K4A and2K5A in the conductive planes2PL4and2PL5is preferably determined according to the plane area of the relatively large high speed ball land2LDb.

As shown inFIG. 26, the area of the fourth-layer opening2K4A is larger than the plane area of the high speed ball land2LDb, and is positioned to be superimposed over the high speed ball land2LDb in the thickness direction. In other words, in the planar view, the high speed ball land2LDb is disposed within the fourth-layer opening2K4A. Each of the high speed via wirings2V3band2V4bis formed within the fourth-layer openings2K4A. As shown inFIG. 16, the high speed ball land2LDb is not superimposed over the fourth conductive plane2PL4in the thickness direction, which can decrease the parasitic capacitance Ct formed in the thickness direction shown inFIG. 22.

As shown inFIG. 27, the area of the fifth-layer opening2K5A is larger than the plane area of the land high speed ball2LDb, and positioned to be superimposed over the high speed ball land2LDb in the thickness direction. In other words, in the planar view, the high speed ball land2LDb is disposed within the fifth-layer opening2K5A. Each of the high speed via wirings2V3band2V4bis formed within the fifth-layer opening2K5A. As shown inFIG. 16, the high speed ball land2LDb is not superimposed over the fifth conductive plane2PL5in the thickness direction, which can decrease the parasitic capacitance Ct formed in the thickness direction shown inFIG. 22.

<Effect of Improvement of Noise Resistance>

The inventors have studied the effect of improvement of the resistance to noise by use of the structure of the wiring substrate2shown inFIG. 21. Now, the results of studies performed by the inventors will be described below.FIG. 29shows an explanatory diagram of the result of evaluation of the electric characteristics on the wiring substrate shown inFIG. 21and the wiring substrate shown in the comparative example ofFIG. 22. In the evaluation as shown inFIG. 29, the structure of the wiring substrate2shown inFIG. 21, and the structure of the wiring substrate2A shown inFIG. 22are evaluated with respect to differential impedance Zdiff [Ω], differential reflection characteristics Sdd11[dB], and differential transmission characteristics Sdd21[dB].

Based on the result of evaluation shown inFIG. 29, an ideal value of a differential impedance is 100Ω. Thus, the differential impedance is preferably close to 100Ω. As to the differential reflection characteristic Sdd11, the maximum loss of the transmission in each substrate was evaluated by changing the frequency until about 10 GHz corresponding to the transmission rate of 20 Gbps, and the result of each substrate was described in Table ofFIG. 29. The result shows that as the differential reflection characteristic Sdd11approaches 0 dB, the reflection becomes larger. As to the differential transmission characteristic Sdd21, a loss of the transmission in each substrate was evaluated at a frequency of 10 GHz, and the result of evaluation was described in Table ofFIG. 29. The result shows that as the differential reflection characteristic Sdd21is further away from 0 dB, the transmission loss becomes larger.

As can be seen fromFIG. 29, the wiring substrate2shown inFIG. 21can improve its differential impedance by about 30Ω, its differential reflection characteristic Sdd11by a maximum −5 dB, and its differential transmission characteristic by about −3 dB, as compared to the wiring substrate2A shown inFIG. 22. That is, the use of the wiring structure shown inFIG. 21can improve the transmission characteristics of the semiconductor device to thereby suppress the reflection of the signal.

<Embodiments of High Speed Transmission Paths Routed Through Wiring Layers>

In the above description of one embodiment with reference toFIG. 16, the through hole lands2TL1and2TL2are arranged over the ball land2LD. In a modified example of this embodiment, all high speed transmission paths can be routed up to the ball land2LD in the second wiring layer WL2shown in, for example,FIG. 11(seeFIG. 19). In this case, the fifth wiring layer WL5shown inFIG. 18can be omitted.

In this embodiment, some of the high speed transmission paths are routed to above the ball lands2LD (seeFIG. 19) in the fifth wiring layer WL5shown inFIG. 18. Thus, some high speed second through hole lands2TL2bforming the transmission paths routed in the fifth wiring layer WL5among the high speed second through hole lands2TL2bshown inFIG. 17are not disposed above the ball lands2LD shown inFIG. 19.

Since in the cross section shown inFIG. 16, the high speed second through hole lands2TL2bare positioned above the high speed ball lands2LDb, the area of each of the openings2K4A and2K5A needs to be larger than the plane area of the high speed ball land2LDb. When the high speed second through hole land2TL2bis not disposed over the high speed ball land2LDb, the area of each of the openings2K4A and2K5A may be smaller than the plane area of the high speed ball land2LDb (seeFIG. 28) as long as the opening area is larger than the plane area of the high speed second through hole land2TL2b.

FIG. 30shows an enlarged plan view of the conductive patterning of the fourth wiring layer WL4(third lowermost wiring layer) in a region different from that shown inFIG. 26.FIG. 31shows an enlarged cross-sectional view taken along the ling A-A ofFIG. 30.FIG. 32shows an enlarged plan view of the conductive patterning of the fifth wiring layer (second lowermost wiring layer) in the enlarged plane shown inFIG. 30.FIG. 33shows an enlarged plan view of the conductive patterning of the sixth wiring layer (first lowermost wiring layer) in the enlarged plane shown inFIG. 30.FIG. 34shows an enlarged plan view of the surroundings of the via wiring connected to the wiring shown inFIG. 32.FIG. 35shows an enlarged cross-sectional view taken along the ling A-A ofFIG. 34.FIG. 36shows an enlarged plan view of the conductive patterning of the fourth wiring layer (third lowermost wiring layer) in the enlarged plane shown inFIG. 34.FIG. 37shows an enlarged plan view of the conductive patterning of the sixth wiring layer (first lowermost wiring layer) in the enlarged plane shown inFIG. 34.

ThroughFIGS. 30 and 37, in order to clarify the planar positional relationship between the openings2K4A (fourth layer opening, third lowermost layer opening) and2K5A (fifth layer opening, second lowermost layer opening) formed in the respective wiring layers, and the high speed second through hole land2TL2b(high speed lower through hole land), high speed third and fourth via wirings2V3band2V4b(high speed second lowermost via wiring and high speed first lowermost via wiring), and high speed ball land2LDb, the contour of the conductive pattern formed in wiring layers other than the wiring layer shown is represented by the two-dot chain line.FIGS. 30, 32 to 34, and 36 and 37are enlarged plan views, but hatching is added to the conductive patterns, including the wirings, the via wirings, the through hole lands, the lands, and the conductive planes in order to clarify the boundary between the conductive patterns. Like the reference path via2V2rfor reference described with reference toFIG. 13,FIG. 34also shows reference path vias2V4rfor reference included in the reference path of the high speed transmission path for transmitting the differential signal, by a dotted line.

In the high speed transmission path shown inFIGS. 30 to 37, first, as shown inFIGS. 30and31, the fourth wiring layer WL4(third lowermost wiring layer) formed over the lower surface2Cb (seeFIG. 31) of the core insulating layer2CR (fourth lowermost insulation layer) is provided with the high speed second through hole land2TL2b(high speed lower through hole land). The structure located over the high speed second through hole land2TL2b(high speed lower through hole land) has the same structure as the wiring structure described with reference toFIGS. 15, 16, 23, and 24, and a redundant description thereof will be described below.

The fifth wiring layer WL5(second lowermost wiring layer) shown inFIGS. 31, 32, 34, and35is provided with the high speed third via wirings2V3b(high speed second lowermost via wirings) (seeFIGS. 31 and 32) electrically coupled to the high speed second through hole lands2TL2b(high speed lower through hole land), and wirings (high speed fifth-layer wirings, high speed second lowermost layer wirings)2d3belectrically coupled to the high speed third via wirings2V3b.

As shown inFIGS. 35 and 37, the sixth wiring layer WL6(first lowermost wiring layer) is provided with the high speed fourth via wiring2V4b(high speed first lowermost via wiring) electrically coupled to the high speed fifth-layer wiring2d3b(high speed second lowermost layer wiring), and a high speed ball land2LDb electrically coupled to the high speed fourth via wiring2V4b. The high speed fourth via wirings2V4b(high speed first lowermost via wiring) shown inFIG. 37are electrically coupled to the high speed third via wirings2V3b(high speed second lowermost via wiring) shown inFIG. 32via the high speed fifth-layer wirings2d3b(high speed second lowermost layer wiring).

That is, the high speed transmission path shown inFIGS. 30 to 37is routed not to be superimposed over the high speed ball land2LDb (seeFIG. 37) in the second wiring layer WL2shown inFIG. 11, and routed to be superimposed over the high speed ball land2LDb (seeFIG. 37) in the fifth wiring layer WL5(second lowermost wiring layer) shown inFIG. 18. Thus, as shown inFIG. 31, no ball land exists directly below the second through hole land2TL2(lower through hole land). And as shown inFIG. 35, no second through hole land2TL2exists directly above the ball land2LD.

When the wiring is routed in the fifth wiring layer WL5(second lowermost wiring layer) as mentioned above, the length of the high speed fifth-layer wirings2d3b(high speed second lowermost layer wiring) formed in the fifth wiring layer WL5shown inFIG. 18is increased according to the distance of the routing. In the example shown inFIG. 18, the fifth wiring layer WL5is provided with the low speed fifth-layer wirings2d3a(low speed second lowermost layer wiring) for electrically coupling the low speed third via wirings2V3a(low speed second lowermost via wiring) to the low speed fourth via wirings2V4a(low speed first lowermost via wiring). The low speed third via wirings2V3a, the low speed fourth via wirings2V4a, and the low speed fifth-layer wirings2d3aform wiring paths electrically connected to the low speed first-layer wirings2d1ashown inFIG. 5, and are routed to the vicinity of the low speed ball lands2LDa (seeFIG. 19) in the first wiring layer WL1, so that the length of the low speed fifth-layer wiring2d3ashown inFIG. 18can be shortened. Thus, the length (path length) of each of the high speed fifth-layer wirings2d3bshown inFIG. 18is larger than that (path length) of the low speed fifth-layer wiring2d3a.

In this embodiment, as shown inFIGS. 31 and 35, in order to be superimposed over the high speed fifth-layer wiring2d3b(high speed second lowermost layer wiring) in the thickness direction, the fourth conductive plane2PL4(third lowermost conductive plane) is formed in the fourth wiring layer WL4(third lowermost wiring layer), and the sixth conductive plane2PL6(first lowermost conductive plane) is formed in the sixth wiring layer WL6(first lowermost wiring layer). In other words, in the side view, the high speed fifth-layer wiring2d3b(high speed second lowermost layer wiring) is sandwiched between the fourth conductive plane2PL4(third lowermost conductive plane) of the fourth wiring layer WL4(third lowermost wiring layer) and the sixth conductive plane2PL6(first lowermost conductive plane) of the sixth wiring layer WL6(first lowermost wiring layer). As shown inFIGS. 32 and 34, the fifth conductive plane2PL5(second lowermost conductive plane) is formed around the high speed fifth-layer wiring2d3b(high speed second lowermost layer wiring) to be spaced away from the high speed fifth-layer wiring2d3b, and the high speed fifth-layer wiring2d3bis enclosed by the fifth conductive plane2PL5(second lowermost conductive plane).

That is, the high speed fifth-layer wiring2d3b(high speed second lowermost layer wiring) takes the strip line wiring structure. In this way, the strip line wiring structure is applied to the transmission path achieving a high transmission rate, which enables the high density design of the high speed signal path.

The transmission path comprised of the low speed third via wiring2V3a(low speed second lowermost via wiring), the low speed fourth via wiring2V4a(low speed first lowermost via wiring), and the low speed fifth-layer wiring2d3a(low speed second lowermost layer wiring) has a relative low transmission rate as compared to that of the transmission path comprised of the high speed third via wiring2V3b(high speed second lowermost via wiring), the high speed fourth via wiring2V4b(high speed second lowermost via wiring), and the high speed fifth-layer wiring2d3b(high speed second lowermost layer wiring) as mentioned above. A wiring structure other than the strip line structure (not shown, bur for example, a wiring structure including a plurality of wirings adjacent to each other without any conductive plane) can be used for the low speed fifth-layer wirings2d3a(low speed second lowermost layer wirings). Unless restricted based on the layout, the strip line structure can also be applied to the low speed fifth-layer wiring2d3a(low speed second lowermost layer wiring).

As shown inFIGS. 30 to 33, when no high speed ball land2LDb (seeFIGS. 34 to 37) is superimposed over the high speed second through hole land2TL2b(high speed lower through hole land) in the thickness direction, an opening, which is formed so as to decrease the parasitic capacitance of the surroundings of the second through hole land2TL2, can be determined by the relationship with the plane area of the high speed second through hole land2TL2b. That is, the area of each of the fourth-layer opening2K4B (third lowermost layer opening) shown inFIG. 30, the fifth-layer opening2K5B (second lowermost layer opening) shown inFIG. 32, and the sixth layer opening2K6B (first lowermost layer opening) shown inFIG. 33is preferably larger than the plane area of the high speed second through hole land2TL2b. In the example shown inFIGS. 30 to 33, the shape and area of each of the openings2K4B,2K5B, and2K6B are the same as those of, for example, the third layer opening2K3shown inFIG. 15.

In the planar view, the contours of the openings2K4B,2K5B, and2K6B are arranged to be superimposed over each other. In the planar view, the high speed second through hole land2TL2b(high speed lower through hole land) is disposed within the openings2K4B,2K5B, and2K6B. The high speed third via wirings2V3b(high speed second lowermost via wirings) are formed within the openings2K4B,2K5B, and2K6B. As described above usingFIG. 22, the parasitic capacitance Ct (seeFIG. 22) caused around the second through hole land2TL2in the thickness direction of the wiring substrate2can be reduced.

As shown inFIGS. 31 and 32, the fifth wiring layer WL5(second lowermost wiring layer) is provided with the high speed fifth-layer wiring2d3b(high speed second lowermost layer wiring) forming the high speed transmission path. The area of each of the openings2K4B,2K5B, and2K6B is preferably minimized as long as the opening is not superimposed over the high speed first through hole land2TL1b(high speed upper through hole land) in the thickness direction.

In this embodiment, the area of each of the openings2K4B,2K5B, and2K6B is smaller than that of the openings2K4A,2K5A, and2K6A shown inFIGS. 34 to 37. In the examples shown inFIGS. 30 to 33, the area of each of the openings2K4B,2K5B, and2K6B is smaller than the plane area of the ball land2LD shown inFIGS. 34 to 37. The area of each of the openings2K4B,2K5B, and2K6B is preferably minimized, whereby the above strip line wiring structure can be applied to most of the high speed fifth-layer wiring2d3b(high speed second lowermost layer wirings). Even when a number of high speed transmission paths are integrated in the fifth wiring layer WL5(second lowermost wiring layer), the fifth conductive plane2PL5(second lowermost conductive plane) can be surely disposed between the adjacent high speed transmission paths (differential pairs) to reduce the influence between the adjacent differential pairs.

When another ball land2LD (for example, a land for supply of a power source potential or a land for supply of a reference potential) needs to be disposed in the position where the sixth layer opening2K6B (first lowermost layer opening) shown inFIG. 31is formed, a modified embodiment can take a structure without the sixth layer opening2K6B. Also in this case, the provision of the fifth-layer opening2K5B (second lowermost layer opening) can decrease the parasitic capacitance of the surroundings of the second through hole land2TL2(lower through hole land).

From the viewpoint of decreasing the parasitic capacitance generated around the high speed ball land2LDb shown inFIGS. 34 to 37, the openings2K4A,2K5A, and2K6A (third lowermost layer opening, second lowermost layer opening and first lowermost layer opening, respectively) are preferably formed not to be superimposed over the high speed ball land2LDb in the thickness direction as shown inFIG. 35. The area of each of the openings2K4A,2K5A, and2K6A can be determined according to the plane area of the high speed ball land2LDb. In the examples shown inFIGS. 34 to 37, the area of each of the openings2K4A,2K5A, and2K6A is the same as that of each of the openings2K4A,2K5A, and2K6A shown inFIG. 16.

In the planar view, the contours of the openings2K4A,2K5A, and2K6A (third lowermost layer opening, second lowermost layer opening and first lowermost layer opening, respectively) are arranged to be superimposed over each other. Also, in the planar view, the high speed ball land2LDb is disposed within the openings2K4A,2K5A, and2K6A. The high speed fourth via wirings2V4bare respectively disposed within the openings2K4A,2K5A, and2K6A. As described above with reference toFIG. 22, the parasitic capacitance Ct (seeFIG. 22) generated around the high speed ball land2LDb (seeFIG. 35) in the thickness direction of the wiring substrate2can be reduced.

In a modified example (not shown) of the embodiment corresponding toFIG. 35, openings can be formed in the wiring layers WL1, WL2, and WL3to be superimposed over the high speed ball land2LDb in the thickness direction. As shown inFIG. 35, a distance between each of the wiring layers WL1, WL2, and WL3and the high speed ball land2LDb is large because of the presence of the core insulating layer2CR (fourth lowermost insulating layer). For this reason, even when the conductive planes2PL1,2PL2, and2PL3are superimposed over the high speed ball land2LDb in the thickness direction, the parasitic capacitance generated between the high speed ball land2LDb and the conductive planes2PL1,2PL2, and2PL3in the thickness direction is small.

Like the high speed transmission path shown inFIGS. 30 to 37, the following will refer to the example to which a structure including wirings routed through wiring layers is effectively applied.FIG. 38is an exemplary diagram showing one example of a pad arrangement on the chip mounting surface side of the wiring substrate shown inFIG. 4.FIG. 39shows an exemplary enlarged plan view of one example of a land arrangement on the lower mounting surface side of the wiring substrate shown inFIG. 4.FIG. 40shows an exemplary explanatory diagram of the state of mounting a plurality of the semiconductor devices shown inFIG. 39over the mounting substrate by cascading connection.

In order to clearly distinguish among different types of terminals, including a terminal for an input signal, a terminal for an output signal, a signal for a reference potential, and a terminal for a power supply potential,FIGS. 38 to 40show different hatching depending on the type of the terminal even in plan views. A bonding pad2PD shown as a plain area inFIG. 38, and a ball land2LD shown as another plain area inFIG. 39include lands for input of a signal, for supply of a reference potential, or for supply of a power supply potential except for the high speed transmission path.

In the example shown inFIG. 38, the high speed bonding pads2PDb on the chip mounting surface side (upper surface2aside) of the wiring substrate2include a plurality of input bonding pads2Pi for input to which an input signal to be supplied to the semiconductor chip3shown inFIG. 4is transmitted. The high speed bonding pads2PDb include a plurality of output bonding pads2Po for output to which an output signal supplied from the semiconductor chip3shown inFIG. 4is transmitted. The bonding pads2PD include a ground bonding pad2Pg for a reference potential for supplying the reference potential (for example, ground potential) to the semiconductor chip3shown inFIG. 4. The bonding pads2PD include a voltage bonding pad2Pv for a power supply potential for supplying a power supply potential to the semiconductor chip3shown inFIG. 4.

The input bonding pads2Pi for input and the output bonding pads2Po for output are electrically coupled to the high speed second-layer wirings2d2bshown inFIG. 11. In other words, an input signal to be input to the semiconductor chip3via the high speed second-layer wirings2d2bis transmitted to the input bonding pads2Pi for input. An output signal to be output from the semiconductor chip3to the high speed second-layer wirings2d2bis transmitted to the output bonding pads2Po for output.

In order to reduce a space for setting an input/output circuit of the semiconductor chip3shown inFIG. 4, the terminal for input and the terminal for output are preferably disposed close to each other. In addition to the input terminal and the output terminal, the terminal for supply of the reference potential and the terminal for supply of the power supply potential are preferably disposed close to each other. In the example shown inFIG. 38, the input bonding pads2Pi for input and the output bonding pads2Po for output are respectively disposed in pairs. Thus, an area occupied by the circuits of the semiconductor chip3can be reduced. That is, the integration degree or density of the semiconductor chip3can be improved.

In the vicinity of the pairs of the input bonding pads2Pi for input and the output bonding pads2Po for output, reference bonding pads2Pr for reference are disposed to form the reference paths for the signal transmission path. In this embodiment, as shown inFIG. 38, the reference bonding pads2Pr are arranged such that a distance between the transmission path on the positive side and the corresponding reference path is preferably set equal to that between the transmission path on the negative side and the corresponding reference path. Specifically, a distance (for example, center-to-center spacing) from the high speed bonding pad2PDb disposed in one transmission path forming the differential pair to the reference bonding pad2Pr for reference disposed closest to the high speed bonding pad2PDb is equal to a distance (for example, center-to-center spacing) from the high speed bonding pad2PDb disposed in the other transmission path to the reference bonding pad2Pr for reference disposed closest to the high speed bonding pad2PDb. Thus, a differential delay between the one transmission path (for example, on the positive side) and the other transmission path (for example, on the negative side) forming the differential pair can be reduced which can prevent or suppress a difference in skew between the positive side and the negative side.

As shown inFIG. 39, a plurality of ball lands2LD are arranged on the lower surface2bas the lower mounting surface of the wiring substrate2. The high speed ball lands2LDb forming the high speed transmission path include input ball lands2Li for input electrically coupled to the input bonding pads2Pi for input (seeFIG. 38), and output ball lands2Lo for output electrically coupled to the output bonding pads2Po for output (seeFIG. 38). The ball lands2LD include ground ball lands2Lg for the reference potential electrically coupled to the ground bonding pads2Pg for the reference potential (seeFIG. 38). The ball lands2LD include voltage ball lands2Lv for the power supply potential electrically coupled to the voltage bonding pads2Pv for the power supply potential (seeFIG. 38).

In an example shown inFIG. 39, the input lands2Li for input and the output ball lands2Lo for output are arranged at the periphery of the lower surface2b. The ground ball lands2Lg for the reference potential and the voltage ball lands2Lv for the power supply potential are disposed at the center of the lower surface2b. The input ball lands2Li for input and the output ball lands2Lo for output are disposed in different positions of the lower surface2bof the wiring substrate2.

Specifically, the wiring substrate2has a quadrilateral shape in the planar view, and includes a first pair of parallel sides2s1and2s2extending in the direction X, and a second pair of parallel sides2s3and2s4extending in the direction Y perpendicular to the direction X. The input ball lands2Li and the output ball lands2Lo are arranged along the second pair of sides2s3and2s4among the four sides of the lower surface2b. The input ball lands2Li on side2s3are collectively arranged closer to side2s1, while the input ball lands2Li on side2s4are collectively arranged closer to side2s2. The output ball lands2Lo on side2s3are collectively arranged closer to side2s2, while the output ball lands on side2s4are collectively arranged closer to side2s1.

As exemplarily shown inFIG. 39, when the terminals for input and the terminals for output are collectively arranged, as shown inFIG. 40, the semiconductor devices1are mounted over the mounting substrate10. In the cascade connection, the arrangements are very useful. That is, as schematically shown inFIG. 40, the terminal for input of the first semiconductor device1and the terminal for output of the second semiconductor device1can be opposed to each other over the mounting surface of the mounting substrate10. This arrangement can reduce a transmission distance between the adjacent semiconductor devices1to thereby decrease the transmission loss. The mounting structure with the semiconductor devices1mounted thereover by the cascade connection can improve its resistance to noise.

As can be seen from comparison betweenFIG. 38andFIG. 39, on the chip mounting surface side, pairs of the input bonding pads2Pi and the output bonding pads2Po are collectively disposed together, while on the lower mounting surface side, the input ball lands2Li for input are grouped apart from the output ball lands2Lo for output. In this case, a signal wiring for input needs to intersect a signal wiring for output at somewhere in the wiring substrate2.

In this embodiment, as mentioned above with reference toFIGS. 30 to 37, the high speed transmission paths are routed in the second wiring layer WL2and the fifth wiring layer WL5. The input signal wiring and the output signal wiring intersect each other between the second wiring layer WL2and the fifth wiring layer WL5.

Specifically, one of the input signal wiring and the output signal wiring is routed to over the high speed ball land2LDb (seeFIG. 19) in the second wiring layer WL2shown inFIG. 11. As shown inFIG. 16, the second through hole lands2TL2employs the wiring structure positioned over the high speed ball land2LDb, which can improve the resistance to noise of the high speed transmission path. The other of the input signal wiring and the output signal wiring is routed to over the high speed ball land2LDb (seeFIG. 19) in the fifth wiring layer WL5shown inFIG. 18. In this case, as described above with reference toFIG. 30toFIG. 37, the use of the wiring structure in which the second through hole land2TL2is not superimposed over the high speed ball land2LDb in the thickness direction can improve the resistance to noise of the high speed transmission path.

<Manufacturing Method of Semiconductor Device>

Now, a manufacturing method (assembly process) of the semiconductor device1described with reference toFIGS. 1 to 40will be described below using a flowchart ofFIG. 41.FIG. 41shows an explanatory diagram of a flowchart of the assembly process of the semiconductor device described above with reference toFIG. 1toFIG. 40. In description of the following manufacturing method, the wiring substrate2previously formed in a product size is provided, and one semiconductor device1is manufactured using the substrate. In a modified example, a multilayout system can also be used, which involves providing a multilayout substrate including a plurality of product formation regions partitioned, assembling semiconductor elements in the respective product formation regions of the substrate, and dividing the substrate into the production formation regions to produce a plurality of semiconductor devices. Thus, a singulating step which is applied to the multilayout system is within a parenthesis.

First, in a substrate provision step shown inFIG. 41, the wiring substrate2shown inFIG. 4is provided. The wiring substrate2provided in this step previously includes the components described usingFIGS. 1 to 40except that the solder balls4shown inFIG. 4are not connected yet and that the heatsink6and the semiconductor chip3are not mounted. Solder material (solder bumps) coupled to the protruding electrodes3BP are previously formed over the bonding pads2PD of the wiring substrate2.

In the semiconductor chip provision step, the semiconductor chip3shown inFIG. 4is provided. An insulating film is formed over the front surface3aof the semiconductor chip3to cover the base and the wirings of the semiconductor chip3. Each of the electrode pads3PD has its surface exposed from the insulating film at an opening formed in the insulating film. The electrode pads3PD are made of metal. In this embodiment, the pad PD is made of, for example, aluminum (Al). The electrode pads3PD are respectively coupled to the protruding electrodes3BP, so that the electrode pads3PD of the semiconductor chip3are electrically coupled to the bonding pads2PD over the wiring substrate2via the protruding electrodes3BP. The protruding electrode3BP in this embodiment is the so-called solder bump formed by stacking a soldering material over the electrode pad3PD via an underlayer metal film (under bump metal).

Then, in a semiconductor chip mounting step, as shown inFIG. 4, the semiconductor chip3is mounted over the upper surface2aas a chip mounting surface of the wiring substrate2. In this embodiment, as shown inFIG. 4, the semiconductor chip is mounted by the face-down mounting method (or flip-chip bonding method) such that the surface3awith the electrode pads3PD is opposed to the upper surface2aof the wiring substrate2. In this case, the solder bumps formed on the protruding electrodes3BP and the solder bumps formed on the substrate bonding pads2PD of the wiring substrate are bonded together to electrically couple the circuit formed in the semiconductor chip3to the circuit (transmission path) formed at the wiring substrate2.

Then, in an underfill charging step, as shown inFIG. 4, underfill resin (insulating resin)55is disposed between the semiconductor chip3and the wiring substrate2. The underfill resin5is disposed to cover a space between the front surface3aof the semiconductor chip3and the upper surface2aof the wiring substrate2. The underfill resin5is made of insulating (non-conductive) material (for example, resin material), and charged to seal an electric connection part (junction of the protruding electrodes3BP) between the semiconductor chip3and the wiring substrate2.

In a modified example of the underfill resin5, before the semiconductor chip mounting step shown inFIG. 41, a film-like or paste-like insulating material (not shown) is applied in advance to the chip mounting region where the semiconductor chip3is to be mounted, and then the semiconductor chip3is pushed against the insulating material, so that the semiconductor chip3can be mounted there rover.

Then, in a heatsink mounting step, as shown inFIG. 4, a heat-dissipating resin (adhesive)7is applied to the back surface3bof the semiconductor chip3, and then the heatsink6provided in the heat sink provision step is bonded to the resin. In this way, the heatsink6is bonded and fixed to the back surface3bof the semiconductor chip3. A support frame8for supporting the heatsink6can be previously bonded and fixed to the wiring substrate2before the heat sink mounting step. Alternatively, the support frame8is previously bonded to the periphery of the heatsink6, and then the heatsink6and the support frame8can be collectively mounted with an adhesive on the lower side of the support frame8.

Then, in a ball mount step, the solder balls4are attached to the lower surface2bas the lower mounting surface of the wiring substrate2. In the present step, the solder balls4are arranged over the ball lands2LD exposed from the sixth insulating layer2e6shown inFIG. 16, and subjected to a reflow process (which involves heating and melting solder components to bond solder balls, and then cooling the solder balls), so that the solder balls are attached to the lands.

In a singulating step, the multilayout substrate is cut along dicing lines (division lines) for partitioning the substrate into the product formation regions, which produces a plurality of semiconductor devices1singulated for every product formation region.

Thereafter, necessary checking and testing, such as an appearance check or an electric test, are performed on each semiconductor device. Then, the semiconductor device is shipped, or mounted on a mounting substrate (not shown).

Other Modified Examples

The invention made by the inventors has been specifically described above based on the preferred embodiments. The invention is not limited to the above embodiments. It is apparent that various modifications and changes can be made to those embodiments without departing the scope of the invention.

For example, in the above embodiments, there are a plurality of transmission paths (first transmission paths, low speed transmission paths) through which the first signal current flows at a first transmission rate, and a plurality of transmission paths (second transmission paths, high speed transmission paths) through which the second signal current flows at a second transmission rate higher than the first transmission rate. The embodiments of the invention can be applied to a modified example in which the transmission paths for all signals are the high speed transmission paths. In this case, for example, the wiring structure described usingFIG. 16is applied to the transmission path coupled to the low speed first-layer wiring2d1ashown inFIG. 5, which can improve the resistance to noise of the transmission paths coupled to the low speed first-layer wirings2d1a.

For example, in the above embodiments, the transmission path through which the differential signal is transferred at a transmission rate of about 10 to 25 Gbps has been described as one example of the high speed transmission path. Even when transferring the signal by any systems other than the system using the differential signal, this embodiment can be applied.

For example, in the embodiments described above, the support frame8is bonded and fixed to the periphery of the semiconductor chip3to support the heatsink6. As a modified example, like the semiconductor device1A shown inFIG. 42, or the semiconductor device1B shown inFIG. 43, the invention can be applied to an embodiment in which the support frame8(seeFIGS. 3 and 4) is not provided, or another embodiment in which the support frame8and the heatsink6are not provided.FIGS. 42 and 43are cross-sectional views showing the semiconductor device as a modified example corresponding toFIG. 4. The semiconductor device1A shown inFIG. 42and the semiconductor device1B shown inFIG. 43can reduce the stress generated on the front surface3aside of the semiconductor chip3by the influence of the support frame8shown inFIG. 4. When a load is applied on the temperature cycle, the stress applied on the front surface3aside of the semiconductor chip3can be reduced as compared to the semiconductor device1shown inFIG. 4.

Specifically, although in the above embodiments, various modified examples have been explained above, the combination of the respective modified examples as described above can be applied.