Semiconductor structure and manufacturing method of the same

A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.

BACKGROUND

Technical Field

The present disclosure relates in general to a semiconductor structure and a manufacturing method thereof, and more particularly to a semiconductor structure with double diffused drains (DDD) and a manufacturing method thereof.

Description of the Related Art

With the developments of semiconductor technology, in addition to high voltage devices, medium voltage devices are widely applied to a variety of electronic products in different fields as well. For example, applications of medium voltage devices include I/O, DAC, OPT, MTP, and etc., and the occupied area of medium voltage devices in the overall device may be up to 20% to 50%. While a double diffused drain (DDD) usually provides a higher breakdown voltage, a DDDMOS device may be included in the applications of medium voltage devices as well. Therefore, researches and developments in the designs of applying such devices in the applications of medium voltage devices have been disclosed.

SUMMARY OF THE INVENTION

The present disclosure is directed to a semiconductor structure and a manufacturing method thereof. According to the embodiments of the present disclosure, the first length of the first portion of the first diffusion region located under the gate is larger than the second length of the second portion of the first diffusion region protruded from a lateral side of the gate, such that the design rule of the first diffusion region under the channel region can be maintained for the desired electrical performance (i.e. Vt stability, desired on-resistance, and etc.), and the total area of the first diffusion region can be reduced for further reducing the device size.

According to an embodiment of the present disclosure, a semiconductor structure is disclosed. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.

According to another embodiment of the present disclosure, a manufacturing method of a semiconductor structure is disclosed. The manufacturing method of the semiconductor structure includes the following steps: providing a semiconductor substrate; providing a photomask having a layout pattern; forming a first diffusion region in the semiconductor substrate according to the layout pattern, wherein the first diffusion region has a first portion and a second portion connected to each other, the first portion has a first length parallel to a first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length; forming a gate on the semiconductor substrate, wherein the gate extends along the first direction, the first portion of the first diffusion region is located underneath the gate, and the second portion of the first diffusion region is protruded from a lateral side of the gate; and forming a second diffusion region in the first diffusion region.

DETAILED DESCRIPTION OF THE INVENTION

According to the embodiments of the present disclosure, a semiconductor structure and a manufacturing method thereof are provided. The embodiments are described in details with reference to the accompanying drawings. The details of the embodiments are for exemplification only, not for limiting the scope of protection of the disclosure. Moreover, the identical or similar elements of the embodiments are designated with the same reference numerals. Also, it is also important to point out that the illustrations may not be necessarily be drawn to scale, and that there may be other embodiments of the present disclosure which are not specifically illustrated. Thus, the specification and the drawings are to be regarded as an illustrative sense rather than a restrictive sense. It is to be noted that the drawings are simplified for clearly describing the embodiments, and the details of the structures and the manufacturing processing steps of the embodiments are for exemplification only, not for limiting the scope of protection of the disclosure. Ones having ordinary skills in the art may modify or change the structures and the manufacturing processing steps according to the embodiments of the present disclosure.

FIG. 1Ashows a top view of a semiconductor structure according to an embodiment of the present disclosure,FIG. 1Bshows a cross-sectional view along the cross-sectional line1B-1B′ inFIG. 1A, andFIG. 10shows a cross-sectional view along the cross-sectional line1C-1C′ inFIG. 1A.

As shown inFIGS. 1A-1C, the semiconductor structure10includes a semiconductor substrate100, a gate200, a first diffusion region300and a second diffusion region400. The gate200is disposed on the semiconductor substrate100and extends along a first direction DR1. The first diffusion region300is formed in the semiconductor substrate100, and the second diffusion region400is formed in the first diffusion region300. The first diffusion region300has a first portion310located underneath the gate200and a second portion320protruded from a lateral side200sof the gate200, the first portion310has a first length L1parallel to the first direction DR1, the second portion320has a second length L2parallel to the first direction DR1, and the first length L1is larger than the second length L2.

As shown inFIG. 1A, in the embodiments, the first length L1is larger than the second length L2by at least 15 nm.

As shown inFIG. 1A, the first portion310and the second portion320of the first diffusion region300form a T-shaped pattern.

In the embodiments, as shown inFIG. 1AandFIG. 1B, the second diffusion region400is formed in the second portion320of the first diffusion region300, and the second diffusion region400has a higher dopant concentration than the first diffusion region300.

As shown inFIGS. 1B and 1C, the semiconductor structure10may further include a shallow trench isolation (STI)500, and the shallow trench isolation500is formed in the semiconductor substrate100defining the first diffusion region300. That is, in the structure as shown inFIGS. 1A-1C, the shallow trench isolation500(not shown inFIG. 1A) abuts the outer edges of the first portion310and the second portion320of the first diffusion region300.

In the embodiments, as shown inFIG. 1A, the outer edge300eof the first diffusion region300is separated from the outer edge400eof the second diffusion region400by a distance W1. When the T-shaped pattern of the first diffusion region300including the first portion310having the first length L1and the second portion320having the second length L2is designed, the first length L1is determined according to the desired electrical performance to be achieved, and then the second length L2is determined by subtracting the first length L1by the distance W1. As such, the distance W1may be regarded as the reduced extent of the second portion320of the first diffusion region300.

In some embodiments, the distance W1may be 9 nm to 17 nm; in other embodiments, the distance W1may vary according to actual needs and is not limited thereto.

In some embodiments, as shown inFIG. 1AandFIG. 1B, the semiconductor structure10further include another first diffusion region300′ and another second diffusion region400′ formed in the semiconductor substrate100, the second diffusion region400′ is formed in the first diffusion region300′, the first diffusion regions300and300′ are located on two opposite sides of the gate200, and the second diffusion regions400and400′ are located on two opposite sides of the gate200. As shown inFIG. 1AandFIG. 1B, the first diffusion region300′ may have the same T-shaped pattern as that of the first diffusion region300.

As shown inFIG. 1BandFIG. 10, the semiconductor structure10may further include an oxide layer210and a spacer220, the oxide layer210is formed between the semiconductor substrate100and the gate200, and the spacer220is formed on the sidewall of the gate200.

As shown inFIG. 1BandFIG. 10, the semiconductor structure10may further include a lightly-doped region110formed in the semiconductor substrate100, and the lightly-doped region110encompasses the first diffusion regions300and300′ and the second diffusion regions400and400′.

In the embodiments, the second diffusion regions400and400′ are such as drain/source regions, the first diffusion regions300and300′ surround the drain/source regions, and the semiconductor structure10is such as a double diffused drains (DDD) MOS device.

In DDDMOS devices, for example, medium voltage (MV) DDDMOS devices, the design rule of the diffusion region under the gate (e.g. channel region) is important to the electrical performance of the MV DDDMOS device, such as stability of threshold voltage (Vt), the prevention of undesired junction breakdown and the desired value of on-resistance. According to the embodiments of the present disclosure, the first length L1of the first portion310of the first diffusion region300is larger than the second length L2of the second portion320of the first diffusion region300, such that the design rule of the first diffusion region300under the channel region can be maintained for the desired electrical performance (i.e. Vt stability, desired on-resistance, and etc.), and the total area of the first diffusion region300can be reduced for further reducing the device size.

Table 1 below shows breakdown voltages of semiconductor structures with the second portions320of the first diffusion regions300having different occupied areas according to some embodiments of the present disclosure. While the area of the second diffusion region400remains constant, the different occupied areas of the second portions320are represented by the different values of the distance W1.

As shown in table 1, as the width W1varies from 17 nm to 9 nm, indicating the occupied area of the second portion320being greatly reduced, the breakdown voltage is only slightly decreased from 13.6V to 12.6V. As such, with the design of the first portion310and the second portion320of the first diffusion region300according to the embodiments of the present disclosure, the desired electrical performance (i.e. Vt stability, desired on-resistance, and etc.) can be maintained, and the breakdown voltages is only slightly influenced yet still remained in the range of the operation voltage of medium voltage devices.

FIG. 2Ashows a top view of a semiconductor structure according to another embodiment of the present disclosure, andFIG. 2Bshows a cross-sectional view along the cross-sectional line2B-2B′ inFIG. 2A. The elements in the present embodiment sharing similar or the same labels with those in the previous embodiment are similar or the same elements, and the description of which is omitted.

As shown inFIG. 2AandFIG. 2B, the semiconductor structure20may further include an additional gate600, an additional first diffusion region700and an additional second diffusion region800. The additional gate600is disposed on the semiconductor substrate100and extends along a second direction DR2which is perpendicular to the first direction DR1. The additional first diffusion region700is formed in the semiconductor substrate100. The additional second diffusion region800is formed in the additional first diffusion region700and separated from the first diffusion region300by a predetermined minimum distance D1.

As shown inFIG. 2AandFIG. 2B, the semiconductor structure20includes two MOS devices arranged vertically to each other; that is, the extending direction of the gate200and the extending direction of the additional gate600are perpendicular to each other. In the embodiments, as shown inFIG. 2B, the shallow trench isolation500is formed in the semiconductor substrate100defining the first diffusion region300, and the shallow trench isolation500may define the additional first diffusion region700as well. That is, in the structure as shown inFIGS. 2A-2B, the shallow trench isolation500(not shown inFIG. 2A) abuts the outer edges of the first portion310and the second portion320of the first diffusion region300, and the shallow trench isolation500may also abut the outer edges of the additional first diffusion region700. As shown inFIG. 2AandFIG. 2B, while the diffusion regions are all formed before the formation of the gate200and the additional gate600, the predetermined minimum distance D1provides the variation tolerance for the implantation processes of the diffusion regions, such that the first diffusion region300of one MOS device does not overlap the channel region630of another MOS device, and thus short circuit can be effectively prevented.

In some embodiments, the predetermined minimum distance D1may be at least 50 nm; in other embodiments, the predetermined minimum distance D1may be less than 50 nm or larger than 50 nm. The predetermined minimum distance D1is determined basically according to the limitations and variation tolerance of the manufacturing processes and thus may vary according to actual situations.

As shown inFIG. 2A, as the pitch size of the semiconductor structure20including multiple MOS devices are determined by the distance between adjacent MOS devices, which is determined from the predetermined minimum distance D1, the distance W1and the second length L2, it is clear that with the design of the first diffusion region300according to the embodiments of the present disclosure, the pitch size of the semiconductor structure20can be effectively reduced.

Table 2 below shows size parameters of semiconductor structures according to some embodiments and a comparative embodiment of the present disclosure. In table 2, “Voltage” refers to the operation voltage, “D2D rule” refers to the distance between the second diffusion region400and the additional second diffusion region800(i.e. the distance between drains of adjacent MOS devices), “L pitch” refers to the distance between the second diffusion region400and another second diffusion region of another MOS device (not shown in drawings) along the first direction DR1, “W pitch” refers to the distance between the second diffusion region400and the additional second diffusion region800, and “Area” refers to the area calculated by “L pitch” multiplied by “W pitch”. In the structure of comparative embodiment 1, the diffusion regions for the drains do not have the structural design of the first diffusion region300according to the embodiments of the present disclosure.

As shown in table 2, the structure of the embodiment 2-1 has a first diffusion region300with the first length L1larger than the second length L2by 18 nm, and while the operation voltages for comparative embodiment 1 and embodiment 2-1 are the same, the pitch area of the structure of embodiment 2-1 is reduced by 5.2%. Similarly, with the design of the first diffusion region300according to the embodiments of the present disclosure, the devices can function well under medium operation voltages with reduced device sizes.

As shown inFIGS. 2A and 2B, the semiconductor structure20may further include an oxide layer610and a spacer620, the oxide layer610is formed between the semiconductor substrate100and the additional gate600, and the spacer620is formed on the sidewall of the additional gate600.

In some embodiments, as shown inFIG. 2AandFIG. 2B, a portion of the additional gate600may be located on the first diffusion region300.

In the embodiments, as shown inFIG. 2AandFIG. 2B, the first diffusion region300and the additional first diffusion region700are separated from each other by a distance D2. In some other embodiments, the first diffusion region300and the additional first diffusion region700may be overlapped (not shown in drawings).

In the embodiments, the additional first diffusion region700may have a T-shaped pattern similar to that of the first diffusion region300. For example, as shown inFIG. 2A, the additional first diffusion region700may have a third portion710and a fourth portion720, the third portion710is located underneath the additional gate600, the fourth portion720is protruded from a lateral side600sof the additional gate600, the third portion710has a third length L3parallel to the second direction DR2, the fourth portion720has a fourth length L4parallel to the second direction DR2, and the third length L3is larger than the fourth length L4.

As shown inFIG. 2AandFIG. 2B, the semiconductor structure20further include another additional first diffusion region700′ and another additional second diffusion region800′ formed in the semiconductor substrate100, the additional second diffusion region800′ is formed in the additional first diffusion region700′, the additional first diffusion regions700and700′ are located on two opposite sides of the additional gate600, and the additional second diffusion regions800and800′ are located on two opposite sides of the additional gate600. As shown inFIG. 2AandFIG. 2B, the additional first diffusion region700′ may have the same T-shaped pattern as that of the additional first diffusion region700.

FIG. 3AtoFIG. 9show a manufacturing method of a semiconductor structure according to an embodiment of the present disclosure. The elements in the present embodiment sharing similar or the same labels with those in the previous embodiments are similar or the same elements, and the description of which is omitted.

Referring toFIG. 3AandFIG. 3B(FIG. 3Ashows a top view of the present step, andFIG. 3Bshows a cross-sectional view along the cross-sectional line3B-3B′ inFIG. 3A), a semiconductor substrate100is provided, and a photomask910having a layout pattern920is provided.

As shown inFIG. 3A, the layout pattern920has a first pattern921and a second pattern922connected to each other, the first pattern921has a first pattern length L5parallel to the first direction DR1, the second pattern922has a second pattern length L6parallel to the first direction DR1, and the first pattern length L5is larger than the second pattern length L6. As shown inFIG. 3A, the first pattern921and the second pattern922of the layout pattern920form a T-shaped pattern.

In the embodiments, an optical proximity correction process may be further performed for the layout pattern920.

As shown inFIG. 3B, a lightly-doped region110is formed in the semiconductor substrate100, and a mask layer950is formed on the semiconductor substrate100.

Referring toFIG. 4AandFIG. 4B(FIG. 4Ashows a top view of the present step, andFIG. 4Bshows a cross-sectional view along the cross-sectional line4B-4B′ inFIG. 4A), the layout pattern920is transferred from the photomask910to the mask layer950to form a patterned mask layer950′ having the transferred layout pattern.

Next, referring toFIG. 5AandFIG. 5B(FIG. 5Ashows a top view of the present step, andFIG. 5Bshows a cross-sectional view along the cross-sectional line5B-5B′ inFIG. 5A), a plurality of trenches T are formed in the semiconductor substrate100by etching the semiconductor substrate100according to the patterned mask layer950′ having the transferred layout pattern.

Next, referring toFIG. 6, an insulating material is filled in the trenches T to form a shallow trench isolation500in the semiconductor structure100.

Next, referring toFIG. 7toFIG. 8, a first diffusion region300is formed in the semiconductor substrate100according to the layout pattern920. The process for forming the first diffusion region300may include the following steps.

As shown inFIG. 7, an implantation process IMP is performed on a region R of the semiconductor substrate100enclosed by the shallow trench isolation500. It is to be noted that in the present implantation process, the region R with dopants is smaller than the first diffusion region300to-be-formed, and the formation of the first diffusion region300will be completed after at least a thermal process is performed on the region R subsequently, as described hereinafter.

Next, as shown inFIG. 8, after at least a thermal process is performed on the region R, the dopants in the region R is driven by the thermal process to diffuse, the doped region is thus enlarged, and then the region R with dopants is expanded until stopped by the shallow trench isolation500, thereby the first diffusion region300is formed.

As shown inFIG. 8, an oxide layer210is formed on the semiconductor substrate100. In the embodiments, the process of forming the oxide layer210requires heating, and the aforementioned thermal process for forming the first diffusion region300may be realized by the process of forming the oxide layer210. That is, as the oxide layer210is formed on the semiconductor substrate100at an elevated temperature, this thermal process facilitates the expansion of the region R with dopants for forming the first diffusion region300. In the embodiments, in addition to the process of forming the oxide layer210, there may be other processes requiring heating performed before the step of forming the gate200on the semiconductor substrate100, and these thermal processes may be included in the aforementioned thermal process for forming the first diffusion region300.

As shown inFIG. 8, after the first diffusion region300is formed in the semiconductor substrate100, the gate200is formed on the semiconductor substrate100.

Next, referring toFIGS. 1A-1CandFIG. 9, the second diffusion region400is formed in the first diffusion region300by such as an implantation process. As shown inFIGS. 1A-1CandFIG. 9, in the as-formed semiconductor structure10, the first diffusion region300has a first portion310located underneath the gate200and a second portion320protruded from a lateral side200sof the gate200, the first portion310has a first length L1parallel to the first direction DR1, the second portion320has a second length L2parallel to the first direction DR1, and the first length L1is larger than the second length L2.

Table 3 below shows some processing deviations in selected steps in the manufacturing process according to some embodiments of the present disclosure, and the aforementioned predetermined minimum distance D1may be determined according to these parameters. In table 3, “CD bar” refers to the critical dimension bar in the step of transferring a layout pattern from a photomask to a mask layer, “AA” refers to the processing deviation in the step of forming trenches according to the mask with the transferred layout pattern, and “Spec limited” refers to the minimum deviation tolerance of the predetermined minimum distance D1determined according to “CD bar” and “AA”. The units are all in “nm”. In embodiment 3-1, the first diffusion region300is N-type doped, and in embodiment 3-2, the first diffusion region300is P-type doped.

According to the results as shown in table 3, the predetermined minimum distance D1is determined to be larger than the value as shown in “Spec limited”; that is, when designing the layout pattern, in the present embodiments for example, a predetermined minimum distance D1of at least larger than 41 nm should be included in the consideration and design of the shape and size of the layout pattern. It is to be noted that table 3 shows an example of how the predetermined minimum distance D1may be determined; however, the present disclosure is not limited thereto.