Pseudo SRAM using resistive elements for non-volatile storage

A memory device includes a first select transistor having a first current electrode coupled to a first bit line, a control electrode and a second current electrode. A second select transistor has a first current electrode coupled to a second bit line, a control electrode and a second current electrode. A first bi-directional resistive element has a cathode coupled to the second current electrode of the first select transistor and an anode coupled to an internal node. A second bi-directional resistive element has a cathode coupled to the internal node and an anode coupled to the second current electrode of the second select transistor. A third transistor has a first current electrode coupled to a third bit line, a second current electrode coupled to the internal node, and a control electrode coupled to a word line.

BACKGROUND

1. Field of the Disclosure

The present disclosure relates in general to semiconductor memories, and more specifically to pseudo SRAM using resistive elements for non-volatile storage.

2. Description of the Related Art

Memories with resistive storage elements under development across the semiconductor industry are geared to replace conventional random access memory (RAM) and non-volatile memory devices. The resistive memory devices include magnetoresistive random access memory (MRAM), Resistive random-access memory (RRAM or ReRAM), and phase-change memory (PCM), among others. Most of the resistive memory devices are implemented in one transistor/one resistive element or one diode/one resistive element memory cell configurations, which require minimal cell area but exhibit relatively slow read and write performance (e.g., approximately 30 nanoseconds or more per operation). Thus, resistive memory devices are not a viable substitute for much of the static RAM in a higher performance system where read/write operations occur within a few clock cycles. It is also difficult to produce a reliable one transistor/one resistive element or one diode/one resistive element memory.

Memory cells with one transistor and one resistive element may eventually replace embedded flash on future SoCs, but it is desirable to use these same elements to replace the static random access memory (SRAM) as well. Potentially, less flash would be needed, or the system could use a more efficient architecture, if the ‘fast’ memory such as SRAM was also compact and non-volatile.

DETAILED DESCRIPTION

Integrated circuit devices and methods are disclosed that utilize resistive storage elements operating as non-volatile storage and a pseudo-SRAM (PSRAM) memory cell with three transistors and one capacitor. Non-volatile resistive elements are coupled to the memory cell and are operable to store and restore the data in the PSRAM. One resistive element is in a high resistive state (HRS) while the other resistive element is in a low LRS, and the comparison of the two resistive elements produces a robust low or high logic state to be sensed. The memory cells include a series pair of resistive elements connected between select transistors. The elements are connected such that they can be ‘programmed’ to HRS and LRS simultaneously. The resistive elements are wired with opposite orientation to each other to enable transition from HRS to LRS for one resistive element and from LRS to HRS for the other resistive element, simultaneously.

FIG. 1is a block diagram of an integrated circuit device including a memory device100according to an embodiment. Memory device100includes memory array102with a plurality of memory cells104,106,108,110coupled to column decode/control112, column multiplexer114, sense amplifiers116,118, and row decoder120. Sense amplifiers116,118are coupled to column decode/control112by column multiplexer114. Row decoder120, column decode/control112, and column multiplexer114can receive addresses for read and write requests from a computer processor (not shown). Data to be written to memory array102is provided from a processor to column decode/control112. Select voltages VSEL0, VSEL1and word lines WL0, WL1are coupled between row decoder120and memory array102.

A memory controller (not shown) controls program and erase procedures of the memory array102through row decoder120and column decode/control112, such as in response to one or more processors. Data is written into or read from the memory array102via column decode/control112.

Bit lines BL0-BL1, BLNV0-BLNV1, BLBNV0-BLBNV1, are coupled between memory array102and column decode/control112, and between sense amplifiers116,118and column decode/control112by way of column multiplexer114. Sense amplifiers116,118provide data (DATA0, DATA1) from respective columns of memory array102to one or more processors.

Although device100is shown with four memory cells104-110, two word lines, two select voltages, and six bit lines, device100can include any suitable number of memory cells, select voltages, word lines and bit lines.

Memory device100may be implemented as part of a System On Chip (SOC) or the like which includes at least one processor coupled to the memory device100via an appropriate interface (not shown), such as a bus or the like with multiple signals or bits. The integrated circuit device may include other circuits, modules or devices, such as other memory devices (not shown), other functional modules (not shown), and external interfaces, such as input, output or input/output (I/O) ports or pins or the like (not shown). In one alternative embodiment, the memory device100is implemented alone in an integrated circuit without any other devices. In another alternative embodiment, memory device100is part of a larger system on the integrated circuit.

Memory cell104includes N-channel discharge or pull-down transistors122,124, two bidirectional resistive elements126,128, capacitor130, and an N-channel access transistor132. Access transistor132has a first current electrode coupled to bit line BL0, a second current electrode coupled to an anode terminal of resistive element126and a cathode terminal of resistive element128, and a gate electrode coupled to word line WL0. Transistor122has a first current electrode coupled to bit line BLNV0, a second current electrode coupled to a cathode terminal of resistive element126, and a gate electrode coupled to select voltage VSEL0. An anode terminal of resistive element126is coupled to a cathode terminal of resistive element128at Node A. Capacitor130has a first terminal coupled to Node A and a second terminal coupled to voltage Vp. Transistor124has a first current electrode coupled to complementary bit line BLBNV0, a second current electrode coupled to an anode terminal of resistive element128, and a gate electrode coupled to select voltage VSEL0.

Memory cell106includes N-channel discharge or pull-down transistors142,144, two bidirectional resistive elements146,148, capacitor150, and an N-channel access transistor152. Access transistor152has a first current electrode coupled to bit line BL0, a second current electrode coupled to an anode terminal of resistive element146and a cathode terminal of resistive element148, and a gate electrode coupled to word line WL1. Transistor142has a first current electrode coupled to bit line BLNV0, a second current electrode coupled to a cathode terminal of resistive element146, and a gate electrode coupled to select voltage VSEL1. An anode terminal of resistive element146is coupled to a cathode terminal of resistive element148at Node A. Capacitor150has a first terminal coupled to Node A and a second terminal coupled to voltage Vp. Transistor144has a first current electrode coupled to complementary bit line BLBNV0, a second current electrode coupled to an anode terminal of resistive element148, and a gate electrode coupled to select voltage VSEL1.

Memory cell108includes N-channel discharge or pull-down transistors162,164, two bidirectional resistive elements166,168, capacitor170, and an N-channel access transistor172. Access transistor172has a first current electrode coupled to bit line BL1, a second current electrode coupled to an anode terminal of resistive element166and a cathode terminal of resistive element168, and a gate electrode coupled to word line WL0. Transistor162has a first current electrode coupled to bit line BLNV1, a second current electrode coupled to a cathode terminal of resistive element166, and a gate electrode coupled to select voltage VSEL0. An anode terminal of resistive element166is coupled to a cathode terminal of resistive element168at Node A. Capacitor170has a first terminal coupled to Node A and a second terminal coupled to voltage Vp. Transistor164has a first current electrode coupled to complementary bit line BLBNV1, a second current electrode coupled to an anode terminal of resistive element168, and a gate electrode coupled to select voltage VSEL0.

Memory cell110includes N-channel discharge or pull-down transistors182,184, two bidirectional resistive elements186,188, capacitor190, and an N-channel access transistor192. Access transistor192has a first current electrode coupled to bit line BL1, a second current electrode coupled to an anode terminal of resistive element186and a cathode terminal of resistive element188, and a gate electrode coupled to word line WL1. Transistor182has a first current electrode coupled to bit line BLNV1, a second current electrode coupled to a cathode terminal of resistive element186, and a gate electrode coupled to select voltage VSEL1. An anode terminal of resistive element186is coupled to a cathode terminal of resistive element188at Node A. Capacitor190has a first terminal coupled to Node A and a second terminal coupled to voltage Vp. Transistor184has a first current electrode coupled to complementary bit line BLBNV1, a second current electrode coupled to an anode terminal of resistive element188, and a gate electrode coupled to select voltage VSEL1.

Bi-directional resistive elements126/128,146/148,166/168and186/188are used as nonvolatile storage for the data in memory cells104-110. The cathode of resistive elements126,146,166,186is connected to a respective one of bit lines BLNV0, BLNV1when respective transistors122,142,162,182are in conducting mode, while the anode of resistive elements128,148,168,188is connected to a respective one of bit lines BLBNV0, BLBNV1when respective transistors124,144,164,184are in conducting mode. As used here, the term ‘anode’ refers to the node which is biased positive to switch from a high resistive state (HRS) to a low resistive state (LRS). If storage node A is pulled to ground when a respective bit lines BL0, BL1, BLNV0, BLNV1, BLBNV0, BLBNV1and word lines WL0, WL1are asserted, resistive elements126,146,166,186will be biased to switch from HRS to LRS, while resistive elements128,148,168,188will switch from LRS to HRS. The anode and cathode terminals of each pair of resistive elements126/128,146/148,166/168and186/188can be swapped, and the cells104-110will function in a similar manner, except that the logical value stored in the cells104-110will be inverted.

Note that during normal PSRAM or DRAM operation, transistors122/124,142/144,162/164and182/184can be placed in non-conducting mode to prevent the changing of the state of node A due to the resistive elements126/128,146/148,166/168and186/188. Node A will be high when the memory cell104,106,108,110including respective capacitors130,150,170,190stores a “1” or high value.

FIG. 2is a timing diagram showing states of signals in memory cell104in the memory array102ofFIG. 1during write and read operations and in a non-volatile (NV) disabled state in accordance with one embodiment.

To write a “1” in resistive elements of selected memory cell104,FIG. 2shows the bit line (BL0), word line (WL0) and select voltage VSEL0are asserted high, while bit lines BLNV0and BLBNV0are low. This will switch resistive element126from HRS to LRS, and resistive element128from LRS to HRS.

To write a “0” in a selected memory cell104, bit line BL0is low while word line WL0, NV bit line BLNV0, complementary NV bit line BLBNV0, and select voltage VSEL0are high. Resistive element126switches from LRS to HRS, and resistive element128switches from HRS to LRS. The data storage state is determined by the voltage divider created by the two resistive elements126,128. Typically, the ratio of resistance in the HRS compared to the LRS is between 5 to 10, so if BLNV0and BLBNV0are biased to 1V/0V, the internal node will float to less than 200 milliVolt or greater than 800 milliVolt, depending on which resistive element126,128is in the LRS and which is in the HRS. Since the voltage at node A is related to the ratio R2/(R1+R2) and is not dependent on an RC constant in the high resistance state, there is a wider choice of process windows for manufacturing resistive elements126,128.

To restore the data in resistive elements126,128to capacitor130, voltage on bit line BL0, non-volatile complementary bit line BLBNV0and word line WL0are set low while the voltage on non-volatile bit line BLNV0and select voltage VSEL0are set high. A regulated voltage is also supplied at the gate electrodes of transistors122,124to ensure read disturb immunity. The voltage at node A goes high if a “1” is being stored, which means resistive element126is in the LRS and resistive element128is in the HRS. Conversely, the voltage at node A goes low if a “0” is being stored, which means resistive element126is in the HRS and resistive element128is in the LRS.

In either case of writing a “1” or a “0” to memory cell104, the write operations can be performed relatively quickly by disabling the non-volatile portion of memory cell104, charging up capacitor130and then transferring the data to resistive elements126,128at a later time. As shown inFIG. 2for the PSRAM write section with the non-volatile portion disabled, bit line BL0and word line WL0are set high to write a “1” with select voltage VSEL0low and non-volatile bit line BLNV0and complementary non-volatile bit line BLBNV0left floating. To write a zero with the non-volatile portion disabled, the bit line BL0is set low while the word line WL0is high, with select voltage VSEL0low and non-volatile bit line BLNV0and complementary non-volatile bit line BLBNV0left floating.

To perform a read operation with the non-volatile portion of memory cell104disabled, the bit line BL0is set high while the word line WL0is high, with select voltage VSEL0low and non-volatile bit line BLNV0and complementary non-volatile bit line BLBNV0left floating.

Note that transistor132will draw current only through the selected memory cell104during all operations. Neighboring memory cells106-110are therefore not affected by operations on memory cell104. Additionally, the layout area requirements for cells104-110are comparable to the area required for conventional SRAM cells while providing non-volatility. Memory cells104-110can be used in extremely low power modes since the resistive elements126/128,146/148,166/168and186/188retain the data while not powered, and thus do not draw refresh current.

By now it should be appreciated that in some embodiments, a memory device can comprise a first select transistor having a first current electrode coupled to a first bit line (BLNV0), a control electrode and a second current electrode. A second select transistor has a first electrode coupled to a second bit line (BLBNV0), a control electrode and a second current electrode. A first bi-directional resistive element (126) has a cathode coupled to the second current electrode of the first select transistor (122) and an anode coupled to an internal node. A second bi-directional resistive element (128) has a cathode coupled to the internal node and an anode coupled to the second current electrode of the second select transistor (124). A third transistor (132) has a first current electrode coupled to a third bit line (BL0), a second current electrode coupled to the internal node, and a control electrode coupled to a word line.

In another aspect, when the first bi-directional resistive element is in a low resistance state, the second bi-directional resistive element is in a high resistance state, the first and second select transistors are in a conductive state, the third transistor is in a conductive state, and voltage at the first and second bit lines is less than a predetermined value, and the voltage at the third bit line is greater than a predetermined value, and the voltage at the third bit line is greater than a predetermined value, the memory cell can store a high logic state during a write operation.

In another aspect, when the first bi-directional resistive element is in a high resistance state, the second bi-directional resistive element is in a low resistance state, the first and second select transistors are in a conductive state, the third transistor is in a conductive state, and voltage at the first and second bit lines is greater than a predetermined value, and the voltage at the third bit line is less than a predetermined value, the memory cell can store a low logic state during a write operation.

In another aspect, the memory device can further comprise a capacitor (130) having a first terminal coupled to the second current electrode of the third transistor and the internal node, and a second terminal coupled to a plate voltage (Vp).

In another aspect, the ratio of high resistance to low resistance can range between 5 and 10 for the first and second bi-directional resistive elements.

In another aspect, when the first bi-directional resistive element is in a low resistance state, the second bi-directional resistive element is in a high resistance state, the first and second select transistors are in a conductive state, the third transistor is in a non-conductive state, voltage at the first bit line is greater than a predetermined value, and voltage at the second bit line is less than a predetermined value, the capacitor can be charged to a high value during a restore operation.

In another aspect, when the first bi-directional resistive element is in a high resistance state, the second bi-directional resistive element is in a low resistance state, the first and second select transistors are in a conductive state, the third transistor is in a non-conductive state, voltage at the first bit line is greater than a predetermined value, and voltage at the second bit line is less than a predetermined value, the capacitor can be discharged to a low value during a restore operation.

In another aspect, the first and second bi-directional resistive elements and the first and second select transistors can be included in a non-volatile portion of the memory device, the third transistor and the capacitor can be included in a volatile portion of the memory device, and during a write operation to the volatile portion, the third transistor can couple the third bit line (BL0) to the internal node. When a voltage at the internal node is at least a predetermined amount less than a voltage of the third bit line, a first logic state can be written to the volatile portion and when the voltage at the internal node can be at least the predetermined amount greater than the voltage of the third bit line, a second logic state can be written to the volatile portion.

In another aspect, during a read operation of the volatile portion, the third transistor can be in a conducting state and voltage sensed at the third bit line indicates whether the capacitor is in a high state or a low state.

In another embodiment, a method of operating can comprise restoring data from the non-volatile portion to the volatile portion including biasing the first and second bi-directional resistive elements in series between the first bit line and the second bit line, and writing data in the non-volatile portion including biasing the first and second bi-directional resistors in parallel between the first and second bit lines. The memory cell can have a volatile portion and a non-volatile portion, the non-volatile portion including a first bi-directional resistive element having a cathode coupled to a first bit line and an anode coupled to an internal node, and a second bi-directional resistive element having a cathode coupled to the internal node and an anode coupled to a second bit line.

In another aspect, during the restoring, biasing the first and second bi-directional resistive elements in series between the first bit line and the second bit line can include setting a first voltage on the first bit line to a value greater than a second voltage on the second bit line.

In another aspect, during the writing, a first state can be written when the first bi-directional resistive element is in a low resistance state and the second bi-directional resistive element is a high resistance state.

In another aspect, during the writing, a second state can be written when the first bi-directional resistive element is in a high resistance state and the second bi-directional resistive element is a low resistance state.

In another aspect, a ratio of resistance between a high resistive state and a low resistive state for the first and second bi-directional resistive elements can be between 5 and 10.

In another aspect, the method can further comprise sensing a third bit line coupled to the volatile portion to determine a logic state stored in the volatile portion.

In still another embodiment, an integrated circuit device (100) can comprise an array of memory cells (102), wherein each memory cell can comprise a non-volatile portion including: a first transistor (122) having a control electrode coupled to a select voltage, a first current electrode, and a second current electrode coupled to a first bit line; a second transistor (124) having a control electrode coupled to the select voltage, a first current electrode, and a second current electrode coupled to a second bit line. A first bi-directional resistive element (126) can have a cathode coupled to the second current electrode of the first transistor and an anode coupled to an internal node. A second bi-directional resistive element (128) can have a cathode coupled to the internal node and an anode coupled to the second current electrode of the second transistor. A volatile portion of each memory cell can include a third transistor (132) having a first current electrode coupled to a third bit line, a control electrode coupled to a word line, and a second current electrode coupled to the internal node. A capacitor can be coupled to the second current electrode of the third transistor and the internal node. Column decode and sense circuitry (112) can be coupled to the first, second and third bit lines of each memory cell of the array of memory cells. Row decode circuitry (120) can be coupled to the select voltage and the word lines of each memory cell of the array of memory cells.

In another aspect, during a read operation of the volatile portion, for each memory cell coupled to an activated word line, the third transistor can be configured to draw current from the third bit line based on a charge state of the capacitor.

In another aspect, during a first write operation, the non-volatile portion can store a high state when the first and second bi-directional elements are biased in parallel, the first bi-directional resistive element is in a low resistive state, and the second bi-directional resistive element is in a high resistive state.

In another aspect, during a second write operation, the non-volatile portion can store a low state when the first and second bi-directional elements are biased in parallel, the first bi-directional resistive element is in a high resistive state, and the second bi-directional resistive element is in a low resistive state.

In another aspect, during a restore operation, the non-volatile portion can store a high state when the first and second bi-directional elements are biased in series, the first bi-directional resistive element is in a low resistive state, and the second bi-directional resistive element is in a high resistive state.

Also for example, in one embodiment, the illustrated elements of systems disclosed herein are circuitry located on a single integrated circuit or within a same device. Alternatively, the systems may include any number of separate integrated circuits or separate devices interconnected with each other. Also for example, a system or portions thereof may be soft or code representations of physical circuitry or of logical representations convertible into physical circuitry. As such, a system may be embodied in a hardware description language of any appropriate type.

Although the present disclosure has been described in considerable detail with reference to certain preferred versions thereof, other versions and variations are possible and contemplated. Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present disclosure without departing from the scope of the disclosure as defined by the appended claims.