Semiconductor structure having a dual-gate non-volatile memory device and methods for making same

A method for making a semiconductor structure includes forming an oxide layer onto non-volatile memory, high, and low voltage device regions of a substrate and forming a first gate material layer over the oxide layer. The first gate material layer is patterned to form a set of memory device select gates in the non-volatile memory device region and a set of gates in the high voltage device region. The patterning is performed while maintaining the oxide and first gate material layers over the low voltage device region. The method also includes forming a second gate material layer over the structure and forming a non-volatile storage layer between the set of select gates and the second gate material layer, from which a set of memory device control gates is patterned. Thereafter, the first gate material layer is patterned to form a set of gates in the low voltage device region.

FIELD

The present disclosure relates generally to semiconductor structures and more particularly to a semiconductor structure having a dual-gate non-volatile memory device and methods for making this structure.

BACKGROUND

The integration, during semiconductor device fabrication, of non-volatile memory (NVM) devices with other device structures, such as high voltage transistors and low voltage logic devices, is challenging. This is at least in part due to the different performance and/or operating requirements of the NVM devices, which store charge, and the other devices, which perform other functions. Accordingly, for some known semiconductor device fabrication processes, the high and low voltage devices are defined together in separate processing steps from the forming of the NVM devices. However, even this approach is becoming increasingly challenging. For example, a much reduced thermal budget and much thinner gate polysilicon and gate spacers make it difficult to obtain satisfactory breakdown voltages for the high voltage devices without incurring additional process cost and complexity.

Embodiments of the present disclosure are illustrated by way of example and are not limited by the accompanying figures. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help to improve understanding of the embodiments.

The apparatus and method components have been represented where appropriate by conventional symbols in the drawings. Some drawings show only those specific details that are pertinent to understanding the embodiments, so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein. Also, the functions included in any flow diagrams do not imply a required order of performing the functionality contained therein.

DETAILED DESCRIPTION

Embodiments are described for making a semiconductor structure having a dual-gate NVM device with a set of select and control gates, a set of high voltage devices, and a set of low voltage devices on a same substrate. An example embodiment provides a method for making a semiconductor structure that includes forming an oxide layer onto non-volatile memory, high voltage, and low voltage device regions of a substrate and forming a first gate material layer over the oxide layer in the non-volatile memory, high voltage, and low voltage device regions. The first gate material layer is patterned to form a set of memory device select gates in the non-volatile memory device region and a set of gates for a first set of high voltage devices in the high voltage device region. The patterning is performed while maintaining the oxide and first gate material layers over the low voltage device region.

The method further includes forming, at least over the set of memory device select gates, a second gate material layer and forming a non-volatile storage layer between the set of memory device select gates and the second gate material layer. The method additionally includes patterning the second gate material layer while maintaining the oxide and first gate material layers over the low voltage device region and removing some of the non-volatile storage layer to form a set of memory device control gates and corresponding charge storage structures between the control gates the select gates. After the patterning to form the gates in the non-volatile memory and high voltage device regions, the first gate material layer is patterned to form a set of gates for a set of low voltage devices in the low voltage device region.

Accordingly, at least one high voltage device shares processing steps with the NVM device. Namely, gates for one or more high voltage devices are simultaneously formed from a same polysilicon layer with the set of select gates for the NVM device. Additionally, for one embodiment, dopant implants (e.g., source/drain implants) for the one or more high voltage devices are annealed with dopant implants for the NVM select gates. Example benefits include one or more of: a thicker gate stack hard mask for the high voltage dopant implants, which lessens implant channeling and penetration through the gate stack and allows for a higher implant energy to be used; use of one or more annealing steps while forming the NVM and high voltage devices to improve the breakdown voltage of the high voltage devices; and flexibility in forming different types of high voltage devices, e.g., n-type metal-oxide-semiconductor (NMOS) devices versus p-type metal-oxide-semiconductor (PMOS) devices.

FIG. 1illustrates a cross-sectional view of a semiconductor structure100at a stage of semiconductor device fabrication or processing. For example, the semiconductor structure100is a part or segment of an integrated circuit, such as a discrete NVM or a micro-controller unit (MCU) having an embedded NVM. For a particular embodiment, the NVM is a dual-gate flash memory, such as a split-gate thin-film storage (TFS) device. However, the present teachings are not limited to these example implementations.

The semiconductor structure100has a substrate102within which isolation regions122,124,126,128,130, and132are formed. Moreover, formed in the substrate102are wells110,114,116,118, and120. An oxide layer104is formed on the substrate102over the isolation regions122,124,126,128,130, and132and the wells110,114,116,118, and120. A first gate material layer106is formed on the oxide layer104, and an anti-reflective coating (ARC) layer108is formed on the first gate material layer106.

At least some of the isolation regions separate out or define regions of the substrate102within and upon which different device types are formed during the course of the fabrication process. Namely, isolation regions122and124define or separate out a non-volatile memory device region134of the substrate102within and upon which a set of one or more NVM memory devices, which in this case includes one or more memory cells also referred to as bit cells, is formed. Isolation regions124and128define or separate out a high voltage device region136of the substrate102within and upon which a set of one or more high voltage devices is formed. Isolation regions128and132define or separate out a low voltage device region138of the substrate102within and upon which a set of one or more low voltage devices is formed. Although not shown, the substrate102could also have other regions such as a medium voltage device region within and upon which one or more medium voltage devices are formed.

For an example, the high voltage devices are metal-oxide-semiconductor field-effect-transistors (MOSFETs) or other devices capable of handling, withstanding, or operating at 9 volts and above. For a particular embodiment, one or more of the high voltage devices formed in the high voltage device region136can be used to program and erase an NVM cell formed in the NVM device region134. For another example, low voltage devices are logic transistors intended for high-speed operation and capable of handling, withstanding, or operating at 0.5 to 2 volts. For a further embodiment, medium voltage devices are capable of handling, withstanding, or operating at between 2 and 9 volts.

The substrate102described herein can be any semiconductor material or combination of materials, such as gallium arsenide, gallium nitride, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, and the like. For a particular example, the substrate102is a p-type substrate. Oxide layer refers to a silicon oxide layer unless otherwise noted. Similarly, nitride layer refers to a silicon nitride layer unless otherwise noted.

For an embodiment, the isolation regions122,124,126,128,130, and132are formed using a shallow trench isolation technique, whereby a pattern of trenches are etched in the substrate102and filled with a dielectric material such as oxide. As used herein, the terms or phrases patterning, patterned etch, and the like, of a material refer to a fabrication process step or steps whereby: a resist (a photoresist as in the case of photolithography) is applied to the material to be patterned (also referred to as the underlying material); a mask (a photomask as in the case of photolithography) is used to transfer a pattern to the resist; and parts, portions, or segments of the underlying material are removed or etched, for instance using a chemical agent, in accordance with the transferred pattern to leave a remaining structure. For an embodiment, the resist further acts as a temporary mask to protect areas where the underlying material is not etched during the patterning process. In a further embodiment, once the resist is no longer needed, it is removed from the underlying material.

The wells110,114,116,118, and120can be formed by selectively implanting a dopant into (also referred to herein as doping) areas at a given dose using a suitable implantation energy. For a particular embodiment, the areas that are to be implanted are defined after forming the isolation regions122,124,126,128,130, and132. This allows the isolation regions to serve as barriers to maintain dopants within certain defined areas. Moreover, the type of dopant implanted, at least in part, determines the type of device formed in the region of the implant.

As illustrated, well110is a p-well formed by doping the area between the isolation regions122and124using a p-type dopant, in order to later form one or more NVM cells, which are part of an NVM array, within the NVM device region134of the substrate102. Well114is a p-well formed by doping the area between the isolation regions124and126using a p-type dopant, in order to later form one or more high voltage NMOS devices within the high voltage device region136of the substrate102. Well116is an n-well formed by doping the area between the isolation regions126and128using an n-type dopant, in order to later form one or more high voltage PMOS devices within the high voltage device region136of the substrate102. Well118is a p-well formed by doping the area between the isolation regions128and130using a p-type dopant, in order to later form one or more low voltage NMOS devices within the low voltage device region138of the substrate102. Well120is an n-well formed by doping the area between the isolation regions130and132using an n-type dopant, in order to later form one or more low voltage PMOS devices within the low voltage device region138of substrate102. Boron and indium are example p-type dopants. Phosphorus, arsenic, and antimony are example n-type dopants.

The oxide layer104is used as a dielectric for gate structures that are formed in the NVM134, high voltage136, and low voltage138device regions of the substrate102and, in one example, is grown rather than deposited for a higher quality. Moreover, although not specifically illustrated, the oxide layer104has different thicknesses in all or some of the regions134,136, and138of the substrate102. The different thicknesses can be accomplished in different regions using multiple thermal oxidation steps. For example, a thicker oxide is grown first and patterned away in the area or areas that require a thinner oxide; then the thinner oxide is grown in the remaining exposed areas. For a particular embodiment, a thicker oxide is grown over the entire structure100and is then patterned away in the low voltage device region138and retained in the NVM device region134to support charge retention in the NVM cells formed thereon. The thicker oxide is also retained in the high voltage device region136to support the higher voltage requirements of the devices formed thereon. A thinner oxide is thereafter grown in the low voltage device region138while masking the thicker oxide in the regions134and136.

Further illustrated, the first gate material layer106, which can be a first polysilicon layer, is deposited on the oxide layer104in all of the regions134,136, and138of the substrate102. The ARC layer108, which can be a layer of silicon nitride, is deposited onto the first polysilicon layer106in all of the regions134,136, and138of the substrate102.

FIG. 2illustrates the semiconductor structure100after patterning the first polysilicon layer106and the ARC layer108to form a set of memory device select gates202and204in the NVM device region134and a set of gates206and208for a first set of high voltage devices to be formed in the high voltage device region136. The gates206and208are also referred to herein as high voltage gates. For one embodiment, the gates206and208are longer than the select gates202and204and are much longer than gates that will be formed in the low voltage device region138. The patterning to form the gates202,204,206, and208is performed while maintaining the oxide104, first polysilicon106, and ARC108layers over the low voltage device region138of the substrate102. Moreover, during the patterning, the ARC layer108minimizes or eliminates reflecting of light off the polysilicon layer106from the photolithography procedure, to enable more accurate patterning. Additionally, after the patterning, portions of the ARC layer108remain over the gates202,204,206, and208to facilitate subsequent processing steps.

For an embodiment, the gates202,204,206, and208are simultaneously or concurrently patterned using the same photomask and photoresist layer. Moreover, the polysilicon of gates202,204, and206can be doped to improve conductivity. For example, the select gates202and204and the gate206for the NMOS device being formed in region136are pre-doped, prior to patterning, using an n-type dopant such as phosphorus. The n-type dopant is implanted while masking other areas that will not be doped.

FIG. 3illustrates the semiconductor structure100after forming dopant regions302and304in the p-well114adjacent (with the exception of the intervening gate oxide104) to sidewalls of the gate206and after forming dopant regions306and308in the n-well116adjacent to sidewalls of the gate208. Although not shown, the dopant regions302,304,306, and308may also extend to some degree under the respective gates, but this is controllable to enable the desirable operating parameters for the devices being formed.

For example, the dopant regions302and304are source/drain regions formed by lightly doping the area adjacent to the gate206to a depth of less than the thickness of the gate stack108/206, or a few hundred A, using an n-type dopant such as phosphorus, arsenic, and/or antimony and are, thereby, referred to herein as lightly doped drain (LDD) implants. Similarly, the dopant regions306and308are LDD source/drain implants formed by lightly doping the area adjacent to the gate208using a p-type dopant such as boron, indium, and/or boron fluoride.

For this embodiment, the implant regions302,304,306, and308are “self-aligned.” Accordingly, the p-well or n-well areas adjacent to the gates206or208are left exposed, while other areas of substrate102are masked by a protective coating to steer the implants302,304, or306, and308into the exposed areas of the substrate102. Edges of the implant regions302and304self-align with the sidewalls of the gate stack108/206, and edges of the implant regions306and308self-align with the sidewalls of the gate stack108/208so that underlaps of the implants with the gate stacks (typically created by implant straggles and subsequent diffusion) is the same on both edges of the gate stacks and are not subject to photo misalignment.

FIG. 4illustrates the semiconductor structure100after forming dopant regions402,404, and406, in the p-well110, adjacent to sidewalls of the select gates202and204. For example, the bit cells being formed in NVM device region134are NMOS devices. Accordingly, the dopant regions402,404, and406are formed by counter-doping the areas adjacent to the gates202and204using an n-type dopant such as phosphorus, arsenic, and/or antimony. These lightly doped implants may extend in a controlled manner underneath one or more of the gates202and204and are also self-aligned. Moreover, as shown, the dopant regions302,304,306,308,402,404, and406are formed while maintaining the oxide104, first polysilicon106, and ARC108layers over the low voltage device region138of the substrate102.

After forming the dopant regions402,404, and406, the structure100is rapid thermal annealed at a temperature that can be, for instance, around 1000° C. for about ten seconds. It should be noted, that for this embodiment (in contrast to the prior art), the devices formed in the high voltage device region136have dopant regions302,304,306, and308that benefit from this anneal. Moreover, a thicker gate stack hard mask for the LDD implants302,304,306, and308in the high voltage device region136, due to the ARC layer108, helps reduce implant channeling and penetration through the gate stack and allows for a higher implant energy to be used than is available in the prior art. The higher implant energy can drive the dopants deeper within the source/drain regions and lead to a higher breakdown voltage of the devices formed in the high voltage device region136without adding to the cost of the semiconductor fabrication process.

FIG. 5illustrates the semiconductor structure100after forming a charge storage layer502onto the structure100, forming a second gate material layer504onto the charge storage layer502, and forming an ARC layer506onto the second gate material layer504. As shown layers502,504, and506are formed in the regions134,136, and138of the substrate102. For one embodiment, the charge storage layer is formed by: depositing an oxide layer onto the structure100; depositing a plurality of nanocrystals, for instance a thin layer of small (e.g., less than 100 Å) silicon islands; and depositing another oxide layer onto and around the nanocrystals. The data state, e.g., a binary 1 or 0, can be persistently stored in the charge storage layer502of one or more NVM cells formed in the NVM device region134.

For other embodiment, the charge storage layer502is formed differently. For one non-limiting example, the charge storage layer502comprises at least one nitride layer. For a particular implementation, the charge storage layer502is an ONO (oxide-nitride-oxide) stack. Such a memory technology is often referred to as SONOS (silicon-oxide-nitride-oxide-silicon).

Furthermore as with layers106and108, the layers504and506can be a second polysilicon layer and a nitride layer, respectively. For an embodiment, the second polysilicon layer504is doped using an n-type dopant such as phosphorus. The n-type dopant can be implanted without masking other areas of the substrate102.

For a particular embodiment, the formation of the charge storage layer502includes one or more anneals at a temperature between 800 and 1000° C. for a period of ten seconds to two hours each. The present teachings allow the LDD implants302,304,306, and308to also receive these anneals, which could drive the dopants deeper within the source/drain regions and further improve the breakdown voltage of the devices formed in the high voltage device region136without adding to the cost of the semiconductor fabrication process.

FIG. 6illustrates the semiconductor structure100after patterning the polysilicon layer504and the ARC layer506to form a set of memory device control gates602and604in the NVM device region134. For an embodiment, a different mask is used to pattern the gates602and604than is used to pattern the gates202,204,206, and208. Moreover, the gates602and604are formed while maintaining the oxide layer104, first polysilicon layer106, and ARC layer108over the low voltage device region138of the substrate. As illustrated, the control gate602is formed at least partially over the select gate202, with the ARC layer108and charge storage layer502therebetween. Similarly, the control gate604is formed at least partially over the select gate204, with the ARC layer108and charge storage layer502therebetween.

FIG. 7illustrates the semiconductor structure100after an etch process, e.g., a dry and/or wet chemical etch, that removes or strips the ARC layer506from above the control gates602and604. The etch process also removes some of the ARC layer108and some of the charge storage layer502from the structure100. The resulting structure100includes a portion702of the ARC layer108and a portion706of the charge storage layer502(also referred to herein as a charge storage structure) between the select gate202and the control gate602of a first NVM cell. The portion702of the ARC layer108partially overlaps the top of the select gate202. The charge storage structure706overlaps the portion702, extends down a side of the portion702, and extends down a sidewall of the select gate202. The charge storage structure706also extends completely beneath the control gate602, thereby, separating the control gate602from the select gate202, the portion702, and the dopant region404.

The resulting structure100also includes a portion704of the ARC layer108and a portion708of the charge storage layer502between the select gate204and the control gate604of a second NVM cell. The portion704of the ARC layer108partially overlaps the top of the select gate204. The charge storage structure708overlaps the portion704, extends down a side of the portion704, and extends down a sidewall of the select gate204. The charge storage structure708also extends completely beneath the control gate604, thereby, separating the control gate604from the select gate204, the portion704, and the dopant region404. The charge storage structures706and708are configured to persistently store data such as a binary 1 or 0. Also, the portions702and704of the ARC layer108can create a higher breakdown voltage within the respective NVM cells.

FIG. 8illustrates the semiconductor structure100after patterning the first polysilicon layer106to form a set of gates802and804for a set of low voltage devices to be formed in the low voltage device region138. The gates802and804are also referred to herein as low voltage gates.FIG. 9illustrates the semiconductor structure100after forming spacer structures, or simply spacers,902,904,906,908,910,912,914,916,918,920,922,924,926, and928adjacent to various sidewalls and after forming dopant regions930,932,934, and936within the low voltage device region138of the substrate.

For an example, the spacers are formed by depositing a spacer material layer, e.g., a composite layer of oxide and nitride, and etching the composite layer back to the thickness desired. As shown, spacer902is formed adjacent to a sidewall of the select gate202. Spacer904is formed adjacent to a first sidewall of the control gate602. Spacer906is formed adjacent to a portion of a second sidewall of the control gate602. Similarly, spacer912is formed adjacent to a sidewall of the select gate204. Spacer910is formed adjacent to a first sidewall of the control gate604. Spacer908is formed adjacent to a portion of a second sidewall of the control gate604. Spacers914and916are formed adjacent to sidewalls of the gate206. Spacers918and920are formed adjacent to sidewalls of the gate208. Spacers922and924are formed adjacent to sidewalls of the gate802. Spacers926and928are formed adjacent to sidewalls of the gate804.

As illustrated, dopant regions930and932are formed in the p-well118adjacent to the sidewalls of the gate802, and dopant regions934and936are formed in the n-well120adjacent to the sidewalls of the gate804. For example, the dopant regions930and932are LDD source/drain implants formed by lightly doping the area adjacent to the gate802using an n-type dopant such as phosphorus, arsenic, and/or antimony. Similarly, the dopant regions934and936are LDD source/drain implants formed by lightly doping the area adjacent to the gate804using a p-type dopant such as boron, indium, and/or boron fluoride. The implants930,932,934, and936may extend in a controlled manner underneath the respective gates802and804and are also self-aligned.

Additionally processing may be performed to further isolate the different elements within the devices, for instance by adding additional dielectric material near the dopant regions402,404, and406in the NVM device region134of the substrate102. The semiconductor fabrication processing for the semiconductor structure100further includes back-end-of-line (BEOL) processing to create metal interconnecting wires that are isolated by dielectric layers (not shown).

FIGS. 1-9illustrate only some embodiments. However, the present teachings enable additional embodiments that allow for flexibility in the semiconductor fabrication processing for the semiconductor structure100. For example,FIG. 9illustrates an embodiment where all of the spacer structures formed in the non-volatile memory134, high voltage136, and low voltage138device regions of the substrate102are simultaneously formed and can have the same thickness and/or be fabricated using the same number of spacer material layers. However,FIG. 10illustrates an alternative embodiment for forming spacer structures.

Particularly, the spacer structures902,904,906,908,910,912,914,916,918, and920are formed in the non-volatile memory134and high voltage136device regions while maintaining the oxide104and first polysilicon106layers over the low voltage device region138. Then, when the spacer structures922,924,926, and928are subsequently formed, additional spacer structures are formed in the non-volatile memory134and high voltage136device regions. Accordingly, the spacer structures formed in the non-volatile memory134and high voltage136device regions have more spacer material layers than the spacer structures formed in the low voltage device region138. This, at least in part, enables thicker spacer structures in the non-volatile memory134and high voltage136device regions to support the higher voltage requirements of the devices formed thereon. Additional thickness in these spacer structures can also, at least in part, be optimized by design.

FIGS. 1-9further illustrate an embodiment where a first anneal is performed after forming dopant regions402,404, and406in the NVM device region134but before forming the second polysilicon504and charge storage502layers. Moreover, all of the dopant regions302,304,306, and308are formed in the high voltage device region136before forming the dopant regions402,404, and406in the NVM device region134. For another embodiment, all the gates206and208formed in the high voltage device region136are formed with the select gates202and204in the NVM device region134as illustrated. However, all or some of the dopant regions302,304,306, and308are formed after forming the dopant regions402,404, and406.

For one example, only the dopant regions302and304for the high voltage NMOS device are formed before forming the dopant regions402,404, and406in the NVM device region134. The dopant regions306and308for the high voltage PMOS device are formed after the anneal (described by reference toFIG. 4) but before depositing the charge storage502, second polysilicon504, and ARC506layers. For another example, only the dopant regions306and308for the high voltage PMOS device are formed before forming the dopant regions402,404, and406in the NVM device region134. The dopant regions302and304for the high voltage NMOS device are formed after the anneal (described by reference toFIG. 4) but before depositing the charge storage502, second polysilicon504, and ARC506layers. For yet another example, all of the dopant regions302,304,306, and308are formed after the anneal (described by reference toFIG. 4) but before depositing the charge storage502, second polysilicon504, and ARC506layers.

The alternative embodiments, described in the preceding paragraph, allow the source/drain regions for the various high voltage devices to see different levels of heat to better control the depth of the dopant implants. Moreover, even where none of the dopant regions receive or see the anneals used to form the NVM device in the NVM device region134, this embodiment could for instance be combined with the embodiment described by reference toFIG. 10to form larger or wider spacer structures adjacent to the sidewalls of the gates206and208formed in the high voltage device region136.

FIGS. 1-9also illustrate an embodiment where all of the gates for the high voltage device region136are formed simultaneously with the select gates in the NVM device region134.FIGS. 11-14illustrate an embodiment where only the set of gates (in this case gate206) for only one or more high voltage NMOS devices is formed with the select gates202and204. Whereas, the gate208is formed simultaneously with forming the gates802and804in the low voltage device region138. By contrast,FIGS. 15-18illustrate an embodiment where only the set of gates (in this case gate208) for only one or more high voltage PMOS devices is formed with the select gates202and204. Whereas, the gate206is formed simultaneously with forming the gates802and804in the low voltage device region138.

Particularly,FIG. 11illustrates the semiconductor structure100ofFIG. 1after patterning the first polysilicon layer106and the ARC layer108to form the select gates202and204in the NVM device region134and the gate206for a first set of high voltage devices to be formed in a first segment, e.g., the HV p-well114, of the high voltage device region136. The patterning to form the gates202,204, and206is performed while maintaining the oxide104, first polysilicon106, and ARC108layers over the low voltage device region138of the substrate102and over a second segment, e.g., the HV n-well116, of the high voltage device region136.FIG. 12illustrates the semiconductor structure100after implanting dopant regions302and304in the p-well114adjacent to the sidewalls of the gate206.

FIG. 13illustrates the semiconductor structure100after implanting the dopant regions402,404, and406in the p-well110of the NVM device region134, patterning the second polysilicon504and the ARC506layers to form the control gates602and604, and stripping the charge storage layer502and ARC layers108and506to form the portions702and704of the ARC layer108and the charge storage structures706and708between the select gates202and204and the control gates602and604.FIG. 14illustrates the semiconductor structure100after patterning the remaining first polysilicon layer106to form a gate1402for a second set of high voltage devices to be formed over the HV n-well116of the high voltage device region136and to form the gates802and804in the low voltage device region138. The processing proceeds as described by reference toFIG. 9and then to the BEOL processing.

FIG. 15illustrates the semiconductor structure100ofFIG. 1after patterning the first polysilicon layer106and the ARC layer108to form the select gates202and204in the NVM device region134and the gate208for a first set of high voltage devices to be formed in a first segment, e.g., the HV n-well116, of the high voltage device region136. The patterning to form the gates202,204, and208is performed while maintaining the oxide104, first polysilicon106, and ARC108layers over the low voltage device region138of the substrate102and over a second segment, e.g., the HV p-well114, of the high voltage device region136.FIG. 16illustrates the semiconductor structure100after implanting dopant regions306and308in the n-well116adjacent to the sidewalls of the gate208.

FIG. 17illustrates the semiconductor structure100after implanting the dopant regions402,404, and406in the p-well110of the NVM device region134, patterning the second polysilicon504and the ARC506layers to form the control gates602and604, and stripping the charge storage layer502and ARC layers108and506to form the portions702and704of the ARC layer108and the charge storage structures706and708between the select gates202and204and the control gates602and604.FIG. 18illustrates the semiconductor structure100after patterning the remaining first polysilicon layer106to form a gate1802for a second set of high voltage devices to be formed over the HV p-well114of the high voltage device region136and to form the gates802and804in the low voltage device region138. The processing proceeds as described by reference toFIG. 9and then to the BEOL processing.

By now it should be appreciated that there has been provided a method for making a semiconductor structure. The method includes forming, in a non-volatile memory device region of a substrate, a non-volatile memory device having at least one non-volatile memory cell comprising a select gate, a charge storage structure, and a control gate operatively coupled and first dopant regions formed within the substrate adjacent to the select gates. The method also includes forming, in a high voltage device region of the substrate, a set of high voltage devices each having a high voltage gate and second dopant, e.g., source and drain, regions formed within the substrate adjacent to the high voltage gates and forming, in a low voltage device region of the substrate, a set of low voltage devices each having a low voltage gate and third dopant, e.g., source and drain, regions formed within the substrate adjacent to the low voltage gates. The one or more select gates and at least a first portion of the high voltage gates are concurrently patterned from a first gate material layer formed on the substrate, wherein the patterning is performed while the first gate material layer covers the low voltage device region. The one or more low voltage gates are patterned from the first gate material layer after patterning the one or more select gates and the first portion of high voltage gates and after patterning the one or more control gates from a second gate material layer.

The method further includes performing a first anneal after forming the first dopant regions within the non-volatile memory device region of the substrate but before patterning the one or more control gates. For one embodiment, a first subset of the second dopant regions formed in the high voltage device region of the substrate is formed before forming the first dopant regions within the non-volatile memory device region of the substrate, and a second subset of the second dopant regions is formed after the first anneal. For another embodiment, all the second dopant regions formed in the high voltage device region of the substrate are formed after the first anneal.

Additionally, a second portion of the high voltage gates may be concurrently patterned from the first gate material layer with the patterning of the low voltage gates. Moreover, the method may include forming spacer structures adjacent to at least one sidewall of the one or more gates in the non-volatile memory device region and adjacent to at least one side wall of the first portion of high voltage gates, wherein the spacer structures are formed before patterning the one or more low voltage gates.

Further disclosed is a semiconductor structure having: a substrate having non-volatile memory, high voltage, and low voltage device regions; a set of memory device select gates formed, in the non-volatile memory device region of the substrate, from a first polysilicon layer; a set of memory device control gates formed, in the non-volatile memory device region of the substrate, from a second polysilicon layer; a set of charge storage structures formed between the set of memory device select gates and memory device control gates; a first set of gates formed, in the high voltage device region of the substrate, from the first polysilicon layer; and a second set of gates formed, in the low voltage device region of the substrate, from the first polysilicon layer. The set of memory device select gates and at least a first portion of the first set of gates are formed using a first mask, and the second set of gates is formed using a second mask.

For one embodiment, a second portion of the first set of gates is formed using the second mask. For another embodiment, the set of charge storage structures includes a plurality of nanocrystals. For yet another embodiment, the semiconductor structure further includes a first set of spacer structures formed adjacent to at least one sidewall of each of the control gates, the select gates, and the first portion of the first set of gates and a second set of spacer structures formed adjacent to at least one sidewall of each of the second set of gates. The spacer structures in the first set of spacer structures have more spacer material layers than the spacer structures in the second set of spacer structures.

For the sake of brevity, conventional techniques related to semiconductor device fabrication (including those using conventional CMOS technology), CMOS devices, MOSFETs, and other functional aspects of the structures (and the individual operating components of the structures) formed thereby, such as the thickness of various layers and the depth of various implants, may not be described in detail. Furthermore, a variety of well-known and common semiconductor materials may be used including those already mentioned and others not specifically referred to herein and combinations thereof.

The terms “configured to”, “configured with”, “arranged to”, “arranged with”, “capable of” and any like or similar terms means that referenced circuit elements have an internal physical arrangement such as by virtue of physical coupling and/or connectivity with other circuit elements in an inactive state. This physical arrangement and/or physical coupling and/or connectivity while in the inactive state enables the circuit elements to perform stated functionality while in the active state of receiving and processing various signals at inputs of the circuit elements to generate signals at the output of the circuit elements. A device or structure that is “configured” in a certain way is configured in at least that way, but may also be configured in ways that are not described. Furthermore, in this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.