Register file circuit and method for improving the minimum operating supply voltage

A register file circuit according to some examples of the disclosure may include a memory cell, a header transistor circuit, and a driver circuit. The header transistor circuit may include one or more PFET headers in series with the PFETs of the memory cell with the gate of the PFET header for the row being written being controlled with a pulse write signal from the driver circuit. In some examples of the disclosure, the header transistor circuit may include an NFET pull-down inserted between a virtual-vdd and ground to discharge the virtual-vdd node reducing the contention during a write operation and a clamping NFET in parallel with the PFET header to clamp the virtual-vdd node to slightly below the threshold voltage of the pull-up PFET in the memory cell to ensure the pull-up PFET is barely off and prevent the virtual-vdd node from discharging all the way to ground.

FIELD OF DISCLOSURE

This disclosure relates generally to register file circuits, and more specifically, but not exclusively, to register file circuits for memory cells.

BACKGROUND

As processors become more complex, the energy used by the processor increases and the need to maximize the energy usage becomes more important. In order to maximize processor energy efficiency, processor designs reduce the supply voltage (VDD) for applications with low-performance requirements (scaling). For example, register file circuits require a minimum operating VDD (VMIN) to successfully perform a write operation. Since register file arrays are distributed across a processor, the register file circuits and the processor logic share the same VDD. For this reason, the register file VMIN for a write operation limits the overall processor VDD scaling and the potential energy benefits. As shown inFIG. 1, the register file VMIN results from a contention path between the NFET transfer device (N4) attempting to bring node “T” to ground and the PFET pull-up device (P1) attempting to hold node “T” to VDD. Because the other NFET transfer device (N3) passes a weak “1” (VDD−Vt), where Vt is the transistor threshold voltage, into the complimentary node “C” and to the gate of P1, the P1device stays partially on and resists the N4device in bringing node “T” to ground. This contention is exacerbated as VDD reduces, especially when the process skews toward slow NFET devices and fast PFET devices. Since designs need to operate across all process corners, this contention limits the VMIN of register file circuits and consequently limits the processor energy efficiency. From simulations of a conventional processor, the register file VMIN results in a loss of more than 26% in processor energy savings.

Accordingly, there are long-felt industry needs for methods that improve upon conventional methods including the improved methods and apparatus provided hereby.

The inventive features that are characteristic of the teachings, together with further features and advantages, are better understood from the detailed description and the accompanying figures. Each of the figures is provided for the purpose of illustration and description only, and does not limit the present teachings.

SUMMARY

The following presents a simplified summary relating to one or more aspects and/or examples associated with the apparatus and methods disclosed herein. As such, the following summary should not be considered an extensive overview relating to all contemplated aspects and/or examples, nor should the following summary be regarded to identify key or critical elements relating to all contemplated aspects and/or examples or to delineate the scope associated with any particular aspect and/or example. Accordingly, the following summary has the sole purpose to present certain concepts relating to one or more aspects and/or examples relating to the apparatus and methods disclosed herein in a simplified form to precede the detailed description presented below.

Some examples of the disclosure are directed to systems, apparatus, and methods for improving the minimum operating voltage needed for write operations of a memory cell, such as a register file bit cell.

In some examples of the disclosure, the system, apparatus, and method includes a memory cell coupled to a virtual supply voltage and a write word line; a first header PFET having a gate, a source, and a drain, wherein the header PFET source is coupled to a system supply voltage, the header PFET gate is coupled to a driver, and the header PFET drain is coupled to the virtual supply voltage; a first header NFET having a gate, a source, and a drain, wherein the first header NFET drain is coupled to the virtual supply voltage, the first header NFET gate is coupled to the driver, and the first header NFET source is coupled to a ground; and a second header NFET having a gate, a source and a drain, wherein the second header NFET drain is coupled to the system supply voltage, the second header NFET gate is coupled to the driver, and the second header NFET source is coupled to the virtual supply voltage.

Other features and advantages associated with the apparatus and methods disclosed herein will be apparent to those skilled in the art based on the accompanying drawings and detailed description.

In accordance with common practice, the features depicted by the drawings may not be drawn to scale. Accordingly, the dimensions of the depicted features may be arbitrarily expanded or reduced for clarity. In accordance with common practice, some of the drawings are simplified for clarity. Thus, the drawings may not depict all components of a particular apparatus or method. Further, like reference numerals denote like features throughout the specification and figures.

DETAILED DESCRIPTION

Methods, apparatus, and systems for an improvement in the minimum operating voltage needed for write operations of a memory cell, such as a register file bit cell, are provided. Some examples of the disclosure describes a register file circuit with a lower VMIN for writing the memory bit cell, thus resulting in a lower overall processor VMIN.

Some examples of the disclosure lower the write VMIN by removing or weakening the write contention in the memory cell by adding a header transistor circuit to quickly discharge or clamp a virtual vdd. The virtual vdd may be clamped low enough to write the memory cell without degrading the write completion. The header transistor circuit may include one or more PFET headers in series with the PFETs of the memory cells, thus creating a virtual VDD node. The gate of the PFET header for the row being written may be controlled with a pulse write signal, which may be generated by the assertion of the write clock. When write clock is activated, the PFET header shuts off the current path to the memory cell PFET contending during the write operation. In some examples of the disclosure, the PFET header may be provided locally for each bit cell. The header transistor circuit may include an NFET pull-down inserted between v_vdd and ground to discharge the virtual VDD node and reduce the contention during the write operation because v_vdd has a large capacitance which otherwise holds the voltage at v_vdd when the PFET header is off. The header transistor circuit may include a clamping NFET placed in parallel with the PFET header to clamp the virtual VDD node to slightly below the threshold voltage of the pull-up PFET in the memory cell to ensure the pull-up PFET is barely off and prevent the virtual VDD node from discharging all the way to ground.

In some examples of the disclosure, the header transistor circuit may include a programmable pulse generator that creates a range of possible pulse widths and locations relative to the write word line when the write clock is activated. The pulse generator may use configuration bits to control the width and the location of the pulse write signal enabling calibration of the optimum pulse width across process variations to minimize the register file VMIN per part or per processor bin.

In the description herein, the term “write” is used synonymously with “store” operations as is known in the art. Likewise, the term “read” is used synonymously with “load.” Further, in the description, references may be made to read/write operations pertaining to “cache blocks,” which may refer to a granularity less than that of an entire cache line. However, it will be understood that such references are merely for illustrative purposes and shall not be construed as limiting the scope of the disclosure. For example, disclosed techniques may be easily extended to operations on any other granularity as applicable, such as a cache word, cache line, etc. Further, it will also be understood that the referenced cache block may comprise data or instructions, even though the description may be provided in terms of write/read operations of data alone. Additionally, references to lower levels of memory hierarchy may include backing storage elements beyond local or first level (L1) caches which may be associated with processors or processing elements. For example, references to lower levels of memory hierarchy herein may refer to second level (L2) caches, main memory, and one or more levels of memory structures which may be present between L2 caches and main memory.

Various aspects are disclosed in the following description and related drawings to show specific examples relating to the disclosure. Alternate examples will be apparent to those skilled in the pertinent art upon reading this disclosure, and may be constructed and practiced without departing from the scope or spirit of the disclosure. Additionally, well-known elements will not be described in detail or may be omitted so as to not obscure the relevant details of the aspects and examples disclosed herein.

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any details described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other examples. Likewise, the term “examples” does not require that all examples include the discussed feature, advantage or mode of operation. Use of the terms “in one example,” “an example,” “in one feature,” and/or “a feature” in this specification does not necessarily refer to the same feature and/or example. Furthermore, a particular feature and/or structure can be combined with one or more other features and/or structures. Moreover, at least a portion of the apparatus described hereby can be configured to perform at least a portion of a method described hereby.

It should be noted that the terms “connected,” “coupled,” or any variant thereof, mean any connection or coupling, either direct or indirect, between elements, and can encompass a presence of an intermediate element between two elements that are “connected” or “coupled” together via the intermediate element. Coupling and/or connection between the elements can be physical, logical, or a combination thereof. As employed herein, elements can be “connected” or “coupled” together, for example, by using one or more wires, cables, and/or printed electrical connections, as well as by using electromagnetic energy. The electromagnetic energy can have wavelengths in the radio frequency region, the microwave region and/or the optical (both visible and invisible) region. These are several non-limiting and non-exhaustive examples.

It should be understood that the term “signal” can include any signal such as a data signal, audio signal, video signal, multimedia signal, analog signal, and/or digital signal. Information and signals can be represented using any of a variety of different technologies and techniques. For example, data, an instruction, a process step, a command, information, a signal, a bit, and/or a symbol described in this description can be represented by a voltage, a current, an electromagnetic wave, a magnetic field and/or particle, an optical field and/or particle, and any combination thereof.

Any reference herein to an element using a designation such as “first,” “second,” and so forth does not limit the quantity and/or order of those elements. Rather, these designations are used as a convenient method of distinguishing between two or more elements and/or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must necessarily precede the second element. Also, unless stated otherwise, a set of elements can comprise one or more elements. In addition, terminology of the form “at least one of: A, B, or C” used in the description or the claims can be interpreted as “A or B or C or any combination of these elements.”

In this description, certain terminology is used to describe certain features. The term “mobile device” can describe, and is not limited to, a mobile phone, a mobile communication device, a pager, a personal digital assistant, a personal information manager, a mobile hand-held computer, a laptop computer, a wireless device, a wireless modem, and/or other types of portable electronic devices typically carried by a person and/or having communication capabilities (e.g., wireless, cellular, infrared, short-range radio, etc.). Further, the terms “user equipment” (UE), “mobile terminal,” “mobile device,” and “wireless device,” can be interchangeable.

Referring toFIG. 2A, a system100that includes a UE200, (here a wireless device), such as a cellular telephone, which has a platform202that can receive and execute software applications, data and/or commands transmitted from a radio access network (RAN) that may ultimately come from a core network, the Internet and/or other remote servers and networks. Platform202can include transceiver206operably coupled to an application specific integrated circuit (“ASIC”208), or other processor, microprocessor, logic circuit, or other data processing device. ASIC208or other processor executes the application programming interface (“API”)210layer that interfaces with any resident programs in memory212of the wireless device. Memory212can be comprised of read-only or random-access memory (RAM and ROM), EEPROM, flash cards, or any memory common to computer platforms. Platform202also can include local database214that can hold applications not actively used in memory212. Local database214is typically a flash memory cell, but can be any secondary storage device as known in the art, such as magnetic media, EEPROM, optical media, tape, soft or hard disk, or the like. Internal platform202components can also be operably coupled to external devices such as antenna222, display224, push-to-talk button228and keypad226among other components, as is known in the art.

Accordingly, an example of the disclosure can include a UE including the ability to perform the functions described herein. As will be appreciated by those skilled in the art, the various logic elements can be embodied in discrete elements, software modules executed on a processor or any combination of software and hardware to achieve the functionality disclosed herein. For example, ASIC208, memory212, API210and local database214may all be used cooperatively to load, store and execute the various functions disclosed herein and thus the logic to perform these functions may be distributed over various elements. Alternatively, the functionality could be incorporated into one discrete component. Therefore, the features of UE200inFIG. 2Aare to be considered merely illustrative and the disclosure is not limited to the illustrated features or arrangement.

The wireless communication between UE200and the RAN can be based on different technologies, such as code division multiple access (CDMA), W-CDMA, time division multiple access (TDMA), frequency division multiple access (FDMA), Orthogonal Frequency Division Multiplexing (OFDM), Global System for Mobile Communications (GSM), 3GPP Long Term Evolution (LTE) or other protocols that may be used in a wireless communications network or a data communications network. Accordingly, the illustrations provided herein are not intended to limit the examples of the disclosure and are merely to aid in the description of aspects of examples of the disclosure.

FIG. 2Bdepicts a functional block diagram of an exemplary processor10, such as an ASIC208configured to incorporate features of the improved low voltage write speed to bitcell. Processor10executes instructions in an instruction execution pipeline12according to control logic14. Control logic14maintains a Program Counter (PC)15, and sets and clears bits in one or more status registers16to indicate, e.g., the current instruction set operating mode, information regarding the results of arithmetic operations and logical comparisons (zero, carry, equal, not equal), and the like. In some examples, pipeline12may be a superscalar design, with multiple, parallel pipelines. Pipeline12may also be referred to as an execution unit. A General Purpose Register (GPR) file20provides a list of general purpose registers24accessible by pipeline12, and comprising the top of the memory hierarchy.

Processor10, which executes instructions from at least two instruction sets in different instruction set operating modes, additionally includes a debug circuit18, operative to compare, upon the execution of each instruction, at least a predetermined target instruction set operating mode to the current instruction set operating mode, and to provide an indication of a match between the two. Debug circuit18is described in greater detail below.

Pipeline12fetches instructions from an instruction cache (I-cache)26, with memory address translation and permissions managed by an Instruction-side Translation Lookaside Buffer (ITLB)28. Data is accessed from a data cache (D-cache)30, with memory address translation and permissions managed by a main Translation Lookaside Buffer (TLB)32. In various examples, ITLB28may comprise a copy of part of TLB32. Alternatively, ITLB28and TLB32may be integrated. Similarly, in various examples of processor10, I-cache26and D-cache30may be integrated, or unified. Further, I-cache26and D-cache30may be L1 caches. Misses in I-cache26and/or D-cache30cause an access to main (off-chip) memory38,40by a memory interface34. Memory interface34may be a master input to a bus interconnect42implementing a shared bus to one or more memory devices38,40that may incorporate the improved low voltage write speed in accordance with some examples of the disclosure. Additional master devices (not shown) may additionally connect to bus interconnect42.

Processor10may include input/output (I/O) interface44, which may be a master device on a peripheral bus, across which I/O interface44may access various peripheral devices48,50via bus46. Those of skill in the art will recognize that numerous variations of processor10are possible. For example, processor10may include a second-level (L2) cache for either or both I and D caches26,30. In addition, one or more of the functional blocks depicted in processor10may be omitted from a particular example. Other functional blocks that may reside in processor10, such as a JTAG controller, instruction pre-decoder, branch target address cache, and the like are not germane to a description of the present disclosure, and are omitted for clarity.

FIG. 3depicts a memory cell or bitcell transistor circuit300with write wordline (WWL) drivers310. A six transistor (6T) bitcell is a single-write port bitcell based on the six transistor (6T) bitcell that decouples write port315in order to eliminate read stability issues. This scheme enables the optimization of the 6T portion to perform writability and increase write speed in write port315. Bitcells on a row share the same WWL and RWL and bitcells on the same column share read bitlines (RBL), word bitlines (WBL), complimentary word bitlines (N_WBL). True node312is a common true node selectively coupled through an n-type pass device (NFET) and a p-type pass device (PFET) in series, and complementary node314is a common complementary node selectively coupled through an NFET and a PFET in series therewith. The common true node is denoted as T and common complimentary node is denoted as C.

In low power CPUs, one of the common ways to reduce power is to reduce supply voltage (VDD). The supply voltage may be connected to a supply rail (not shown). As supply voltage is decreased, the decrease in performance is not linear, and it becomes exponential as the supply is reduced nearer to Vt of the highest-Vt devices which are typically found in memory arrays for leakage control reasons.

In the memory bitcell, these operating characteristics have ramifications for both data retention and write completion speed. As VDD approaches Vt, the hold-Signal Noise Margin (SNM), which is the data retention figure of merit for Static Random Access Memory (SRAM), is degraded because the voltage scale-down causes the leakage current of the NFET to become comparable to the saturation current of the PFET. Write speed, on the other hand, is dependent on 2 operations: writing a “0” phase, which is quickly pulling the T node or the C node to ground through one of the transfer NFET, and followed by the write completion phase which is quickly pulling the C node or T node to VDD by one of the pull-up PFET. This degradation adversely impacts the write completion because at low voltage, the PFETs have to pull up the input to HIGH as the NFETs only get a very weak HIGH. Since the ratio of NFETs/PFETs is usually 2-3×, the PFETs tend to be very weak and this speed will dictate the minimum write time at low voltage (the minimum time WWL310needs to be HIGH in order to write the cell); While this degradation weakens the pull-up PFET device, it is not enough to help with the first write operation. There is a contention path where the pull-up PFET is fighting the transfer NFET device to keep the T node or C node from being pulled to “0”.

The most straightforward way to improve the data retention and write speed with regard to weak PFETs at low voltage is to upsize or use a lower Vt device. However, this is not an optimal solution, since it will make the cell's writability degrade at all voltages (more contention from the PFET means the NFET will have a harder time flipping the node) and this leads to increased leakage.

FIG. 4depicts a register file circuit with in accordance with some examples of the disclosure. As shown inFIG. 4, a register file circuit400may include a plurality of memory or bitcells410, a header circuit480, and a driver circuit495. While a plurality of memory cells410are shown, it should be understood that a single memory cell may be used. Additionally, the memory cells410may include a read circuit (not shown).

Each memory cell410may include a first PFET411having a gate412, a source413and a drain414. The first PFET source413may be coupled to a virtual supply voltage (v_vdd)415. Each memory cell410may include a second PFET416having a gate417, a source418, and a drain419. The second PFET source418may be coupled to the virtual supply voltage415.

Each memory cell410may include a first NFET420having a gate421, a source422, and a drain423. The first NFET source422may be coupled to the first PFET drain414, the first NFET gate421may be coupled to the first PFET gate412, and the first NFET drain423may be coupled to a ground424. Each memory cell410may include a second NFET425having a gate426, a source427, and a drain428. The second NFET source427may be coupled to the second PFET drain419, the second NFET gate426may be coupled to the second PFET gate417, and the second NFET drain428may be coupled to ground424. While not shown, the second NFET gate may be coupled to a read circuit.

Each memory cell410may include a third NFET429having a gate430, a source431, and a drain432. The third NFET gate430may be coupled to a write word line433, the third NFET drain432may be coupled to the second PFET gate417and the second NFET gate426, and the third NFET source431may be coupled to a write bit line (wbl)434. Each memory cell410may include a fourth NFET435having a gate436, a source437, and a drain438. The fourth NFET gate436may be coupled to the write word line433, the fourth NFET drain438may be coupled to the first PFET gate412and the first NFET gate421, and the fourth NFET source may be coupled to a word bit line complement (wbl_1)439.

The header circuit480may include a plurality header PFETs481, a first header NFET482, and a second header NFET483. While a plurality of header PFETs481are shown, it should be understood that a single header PFET481may be used. In addition, while a single header circuit480is shown for the plurality of memory cells410, it should be understood that a separate header circuit480may be provided for each memory cell410. When a separate header circuit480is provided by for each memory cell410, a single common pair of header NFET devices482and483may be used instead of a pair of header NFET devices for each memory cell410.

Each header PFET481may include a gate484, a source485, and a drain486. The header PFET source485may be coupled to a system supply voltage (vdd)487that supplies voltage for the processor coupled to the memory cell, the header PFET gate484may be coupled to driver circuit495, and the header PFET drain486may be coupled to the virtual supply voltage415.

The first header NFET482may have a gate488, a source489, and a drain490. The first header NFET source489may be coupled to the virtual supply voltage415, the first header NFET gate488may be coupled to the driver circuit495, and the first header NFET drain490may be coupled to ground424.

The second header NFET483may have a gate491, a source493, and a drain492. The second header NFET source493may be coupled to the system supply voltage487, the second header NFET gate491may be coupled to the driver circuit495, and the second header NFET drain492may be coupled to the virtual supply voltage415.

The driver circuit495may include a pulse generator494coupled to a write clock signal (wr_clk)496and a write signal output497coupled to the gate or gates of each header PFET481, the first header NFET482, and the second header NFET483.

An exemplary operation of the register file circuit400shown inFIG. 4according to some examples of the disclosure will now be described. The header PFETs481are configured to lower the voltage of the virtual supply voltage415below a threshold voltage (Vt) of the memory cell PFETs411and416. This may be accomplished by a write signal output turning off the header PFETs481while the first header NFET482is turned on when the gates of the header PFETs481and the first header NFET482are coupled to the write signal output generated by the driver circuit495. This configuration will shut the current path to the memory cells410, which turns off the first PFET411and the second PFET416and eliminates the write contention within the memory cells410. To prevent the virtual supply voltage415going to ground or zero, the second header NFET483clamps the virtual supply voltage415to vdd minus Vt of PFETs411and416. This may be accomplished by sizing NFETs482and483to provide a resistor divider ratio voltage desired.

The write signal output of the driver circuit495may include a pulse generator494that provides a pulse write signal of a width designed to prevent complete removal of the write contention during the entire period the write word line433is active. The width of the pulse may be configured and timed (location relative to the write word line signal) to quickly complete the write process while reducing the energy required by keeping the first header NFET482and the second header NFET483on at the same time. The width of the pulse write signal may also be optimized to address process variations that occur in the circuit during the manufacturing or fabrication process.

FIG. 5depicts timing diagrams and completion time graphs of the write process for a register file circuit in accordance with some examples of the disclosure. As shown inFIG. 5, the write word line signal500is activated and rises from zero to vdd. Prior to activation of the write word line signal500, the pulse write signal510is output from the driver circuit raising the voltage on the pulse write signal line from zero to vdd. As the pulse write signal510reaches vdd, the virtual supply voltage signal520dips down below vdd and gets clamped at a voltage dependent upon the ratio of the first header NFET and the second header NFET before the write word line signal500reaches vdd. The width of the pulse write signal is configured to provide enough time for write completion before the pulse write signal voltage drops back to zero. As shown inFIG. 5, a y-axis530shows the normalized delay at 0.9 volts (normalized to a conventional bitcell that does not have any write assist mechanism) and a x-axis540shows the Vmin of a memory cell in volts. The graph of a write completion time for a conventional 6T bitcell550shows a Vmin of 0.55 volts while the graph of a write completion time for a register file circuit according to some examples of the disclosure560shows a Vmin of approximately 0.48 volts during the same delay. This results in an 11% reduction in Vmin, which translates to a 21% energy savings during a write completion. If the desired Vmin of the register file circuit with write assist according to some examples is 0.55 volts, the use of write assist will still result in a 45% reduction in the delay for write completion.

Nothing stated or illustrated depicted in this application is intended to dedicate any component, step, feature, benefit, advantage, or equivalent to the public, regardless of whether the component, step, feature, benefit, advantage, or the equivalent is recited in the claims.

Although some aspects have been described in connection with a device, it goes without saying that these aspects also constitute a description of the corresponding method, and so a block or a component of a device should also be understood as a corresponding method step or as a feature of a method step. Analogously thereto, aspects described in connection with or as a method step also constitute a description of a corresponding block or detail or feature of a corresponding device. Some or all of the method steps can be performed by a hardware apparatus (or using a hardware apparatus), such as, for example, a microprocessor, a programmable computer or an electronic circuit. In some examples, some or a plurality of the most important method steps can be performed by such an apparatus.

The examples described above merely constitute an illustration of the principles of the present disclosure. It goes without saying that modifications and variations of the arrangements and details described herein will become apparent to other persons skilled in the art. Therefore, it is intended that the disclosure be restricted only by the scope of protection of the appended patent claims, rather than by the specific details presented on the basis of the description and the explanation of the examples herein.

In the detailed description above it can be seen that different features are grouped together in examples. This manner of disclosure should not be understood as an intention that the claimed examples require more features than are explicitly mentioned in the respective claim. Rather, the situation is such that inventive content may reside in fewer than all features of an individual example disclosed. Therefore, the following claims should hereby be deemed to be incorporated in the description, wherein each claim by itself can stand as a separate example. Although each claim by itself can stand as a separate example, it should be noted that—although a dependent claim can refer in the claims to a specific combination with one or a plurality of claims—other examples can also encompass or include a combination of said dependent claim with the subject matter of any other dependent claim or a combination of any feature with other dependent and independent claims. Such combinations are proposed herein, unless it is explicitly expressed that a specific combination is not intended. Furthermore, it is also intended that features of a claim can be included in any other independent claim, even if said claim is not directly dependent on the independent claim.

It should furthermore be noted that methods disclosed in the description or in the claims can be implemented by a device comprising means for performing the respective steps or actions of this method.

Furthermore, in some examples, an individual step/action can be subdivided into a plurality of sub-steps or contain a plurality of sub-steps. Such sub-steps can be contained in the disclosure of the individual step and be part of the disclosure of the individual step.