Memory controller

A memory controller for writing data in a first semiconductor memory including a plurality of memory cells having series-connected current paths and charge storage layers includes a host interface which configured to be receivable of first data from a host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with the state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes the first and second data in the first semiconductor memory. When writing the second data, the arithmetic unit does not select a word line adjacent to a select gate line, and selects a word line not adjacent to the select gate line.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2006-194804, filed Jul. 14, 2006, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a memory controller, e.g., a memory controller for controlling the operation of a nonvolatile semiconductor memory chip.

2. Description of the Related Art

With the recent rapid spread of digital cameras and portable audio players, demands for large-capacity nonvolatile semiconductor memories are increasing, and NAND flash memories (to be also simply referred to as flash memories hereinafter) are widely used as the nonvolatile semiconductor memories.

In the NAND flash memory, data is erased from a plurality of memory cells at once. This erase unit will be called a memory block hereinafter. The memory block includes a plurality of NAND cells. Each NAND cell has a selection transistor ST1having a drain connected to a bit line, a selection transistor ST2having a source connected to a source line, and a plurality of memory cell transistors MT having current paths connected in series between the source of the selection transistor ST1and the drain of the selection transistor ST2.

In the conventional NAND flash memory described above, data is written by selecting a certain word line. This technique is described in, e.g., “Jpn. Pat. Appln. KOKAI Publication No. 2005-285184” or “SmartMedia™ (registered trademark) Physical Format Specification Ver 1.21, issued by SSFDC Forum Technical Meeting, May 19, 1999”. However, this technique has the problem that the reliability of the system deteriorates due to the loss of important data.

BRIEF SUMMARY OF THE INVENTION

A memory controller according to the first aspect of the present invention which writes data in a first semiconductor memory including a plurality of memory cells, a first selection transistor, a second selection transistor, a first select gate line, a second select gate line and a plurality of word lines, the plurality of memory cells having current paths connected in series between a source of the first selection transistor and a drain of the second selection transistor, each of the plurality of memory cells having a control gate and a charge storage layer, the first and second select gate lines respectively connected to gates of the first and second selection transistors, and the plurality of word lines respectively connected to the control gates, the memory controller comprising a host interface which is configured to be connectable to a host apparatus and to be receivable of first data from the host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with a state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes, in the first semiconductor memory, the first data from the host interface and the second data held in the second semiconductor memory, wherein when writing the second data, the arithmetic unit does not select the word lines adjacent to the first select gate line and the second select gate line, and selects the word line not adjacent to the first select gate line and the second select gate line.

A memory controller according to the second aspect of the present invention which writes data in a first semiconductor memory including a plurality of memory cells, a first selection transistor, a second selection transistor, a first select gate line, a second select gate line and a plurality of word lines, the plurality of memory cells having current paths connected in series between a source of the first selection transistor and a drain of the second selection transistor, each of the plurality of memory cells having a control gate and a charge storage layer and being configured to hold data having at least two bits, the first and second select gate lines respectively connected to gates of the first and second selection transistors, and the plurality of word lines respectively connected to the control gates, the memory controller comprising a host interface which is configured to be connectable to a host apparatus and to be receivable of first data from the host apparatus, a second semiconductor memory which temporarily holds second data, and an arithmetic unit which generates the second data in accordance with a state of the first semiconductor memory, temporarily holds the second data in the second semiconductor memory, and writes, in the first semiconductor memory, the first data from the host interface and the second data held in the second semiconductor memory, wherein when writing the second data, the arithmetic unit writes one-bit data in the memory cells connected to the word lines adjacent to the first select gate line and the second select gate line, and writes the data having not less than two bits in the memory cell connected to the word line not adjacent to the first select gate line and the second select gate line.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will be explained below with reference to the accompanying drawing. In the following explanation, the same reference numerals denote the same parts throughout the drawing.

First Embodiment

A memory controller according to the first embodiment of the present invention will be explained below with reference toFIG. 1.FIG. 1is a block diagram of a memory system according to this embodiment.

As shown inFIG. 1, this memory system comprises a memory card1and host apparatus2. The host apparatus2has hardware and software for accessing the memory card1connected via a bus interface14. The memory card1operates by receiving power supply when connected to the host apparatus2, and performs processing corresponding to the access from the host apparatus2.

The memory card1exchanges information with the host apparatus2via the bus interface14. The memory card1includes a NAND flash memory chip (to be also simply referred to as a NAND flash memory or flash memory hereinafter)11, a card controller12for controlling the flash memory chip11, and signal pins (first to ninth pins)13.

The signal pins13are electrically connected to the card controller12.FIG. 2shows an example of the assignment of signals to the first to ninth pins of the signal pins13.FIG. 2is a table showing the first to ninth pins and signals assigned to these pins.

Data0, data1, data2, and data3are respectively assigned to the seventh, eighth, ninth, and first pins. The first pin is also assigned to a card detection signal. The second pin is assigned to a command. The third and sixth pins are assigned to a ground potential Vss. The fourth pin is assigned to a power supply potential Vdd. The fifth pin is assigned to a clock signal.

The memory card1can be inserted into and removed from a slot formed in the host apparatus2. A host controller (not shown) of the host apparatus2communicates various signals and data with the card controller12in the memory card1via the first to ninth pins. When writing data in the memory card1, for example, the host controller sends a write command as a serial signal to the card controller12via the second pin. The card controller12receives this write command input to the second pin, in response to the clock signal supplied to the fifth pin.

As described above, the write command is serially input to the card controller12by using only the second pin. As shown inFIG. 2, the second pin assigned to command input is positioned between the first pin for data3and the third pin for the ground potential Vss. The host controller in the host apparatus2and the memory card1communicate with each other by using the signal pins13and the bus interface14corresponding to them.

On the other hand, the flash memory11and card controller12communicate with each other by using a NAND flash memory interface. Although not shown, therefore, the flash memory11and card controller12are connected by, e.g., 8-bit input/output (I/O) lines.

When writing data in the flash memory11, for example, the card controller12sequentially inputs a data input command80H, column address, page address, data, and program command10H to the flash memory11via the I/O lines. “H” of the command80H indicates a hexadecimal number. In practice, an 8-bit signal “10000000” is supplied parallel to the 8-bit I/O lines. That is, this NAND flash memory interface supplies a multi-bit command parallel.

Also, the NAND flash memory interface communicates commands and data with the flash memory11by using the same I/O lines. As described above, the interface for communication between the host controller in the host apparatus2and the memory card1differs from the interface for communication between the flash memory11and card controller12.

The internal arrangement of the card controller of the memory card1shown inFIG. 1will be explained below with reference toFIG. 3.FIG. 3is a block diagram of the card controller.

The card controller12manages the internal physical state (e.g., which physical block address contains what number of logical sector address data, or which block is erasable) of the flash memory11. The card controller12has a host interface module21, MPU (Micro Processing Unit)22, flash controller23, ROM (Read-Only Memory)24, RAM (Random Access Memory)25, and buffer26.

The host interface module21interfaces the card controller12and host apparatus2with each other.

The MPU22controls the overall operation of the memory card1. When power is supplied to the memory card1, the MPU22reads out firmware (a control program) stored in the ROM24onto the RAM25and executes predetermined processing, thereby forming various tables on the RAM25. One of these tables is system information. The RAM25is, e.g., a volatile semiconductor memory such as an SRAM. It is a matter of course that the RAM25may also be a nonvolatile memory. The system information relates to the NAND flash memory11, and the details will be described later. Also, the MPU22receives a write command, read command, and erase command from the host apparatus2, executes predetermined processing on the flash memory11, and controls data transfer via the buffer26.

The ROM24stores the control program controlled by the MPU22. The RAM25is used as a work area of the MPU22, and stores the control program and various tables. The flash controller23interfaces the card controller12and flash memory11with each other.

The buffer26temporarily stores a predetermined amount of data (e.g., one page) when writing data transmitted from the host apparatus2into the flash memory11, and temporarily stores a predetermined amount of data when transmitting data read out from the flash memory11to the host apparatus2.

The internal arrangement of the NAND flash memory11will be briefly explained below.FIG. 4is a block diagram of the NAND flash memory11. As shown inFIG. 4, the NAND flash memory11comprises a memory cell array30, page buffer31, and row decoder32.

The memory cell array30includes memory blocks BLK0to BLKn (n is a natural number of 1 or more). Note that the memory blocks BLK0to BLKn will also be simply referred to as memory blocks BLK hereinafter. Note also that data erase is performed for each memory block BLK. That is, data in one memory block BLK is erased at once. Each memory block BLK includes a plurality of memory cell transistors. The memory block BLK also has word lines WL0, WL1, . . . (to be referred to as word lines WL hereinafter), and bit lines BL0, BL1, . . . (to be referred to as bit lines BL hereinafter) perpendicular to the word lines WL. Memory cell transistors on the same row are connected together to the same word line. Memory cell transistors in the same column are connected, as sets each including a plurality of memory cell transistors, to the bit lines BL. Note that data write and read are performed for each set including a plurality of memory cell transistors, and this memory cell transistor set is called a page. When reading out and writing data, a certain world line WL is selected by a row address, and a certain bit line BL is selected by a column address. In the example shown inFIG. 4, each page of the flash memory11has 2,112 bytes (512-byte data storage portion×4+10-byte redundancy portion×4+24-byte management data storage portion), and each memory block BLK contains, e.g., 128 pages.

The page buffer31performs data input/output with respect to the flash memory11, and temporarily holds data. The page buffer31can hold a data size of 2,112 bytes (2,048 bytes+64 bytes) that is the same as the page size of each memory block BLK. When writing data, for example, the page buffer31executes the data input/output process with respect to the flash memory11, for each page corresponding to its own storage capacity.

When writing and reading out data, the row decoder32selects a certain word line WL.

Details of the arrangement of the memory block will be explained below with reference toFIG. 5.FIG. 5is an equivalent circuit diagram of a certain memory block BLK.

As shown inFIG. 5, the memory block BLK comprises (m+1) NAND cells (m is a natural number of 1 or more) arranged in the direction of the word lines WL. Each NAND cell comprises selection transistors ST1and ST2, and32memory cell transistors MT. The selection transistors ST1of these NAND cells have drains connected to bit lines BL0to BLm, and gates connected together to a select gate line SGD. The selection transistors ST2have sources connected to source lines SL, and gates connected together to a select gate line SGS.

Each memory cell transistor MT is a MOS transistor having a stacked gate formed on a semiconductor substrate via a gate insulating film. The stacked gate includes a charge storage layer (floating gate) formed on the gate insulating film, and a control gate formed on the charge storage layer via an inter-gate insulating film. In each NAND cell, the 32 memory cell transistors MT are arranged such that their current paths are connected in series, between the source of the selection transistor ST1and the drain of the selection transistor ST2. The control gates of the memory cell transistors MT are connected to word lines WL0to WL31in order from the memory cell transistor MT closest to the drain side. Accordingly, the drain of the memory cell transistor MT connected to the word line WL0is connected to the source of the selection transistor ST1, and the source of the memory cell transistor MT connected to the word line WL31is connected to the drain of the selection transistor ST2.

The word lines WL0to WL31connect the control gates of the memory cell transistors MT together between the NAND cells in the memory block. That is, the control gates of the memory cell transistors MT on the same row in the memory block BLK are connected to the same word line WL. Also, the bit lines BL0to BLm connect the drains of the selection transistors ST1together between the memory blocks. That is, the NAND cells in the same column in a plurality of memory blocks BLK are connected to the same bit line BL.

The system information shown inFIG. 3will be explained below with reference toFIG. 6.FIG. 6is a conceptual view showing an example of the system information held in the RAM25.

As shown inFIG. 6, the system information contains an address table and bad block table.

The address table shows the correspondence between a logical address and physical address. The logical address is used when the host apparatus2accesses the memory card1. The physical address indicates a physical position in the memory cell array30of the NAND flash memory11. The logical address and physical address do not always match. Therefore, the MPU22holds the correspondence between the logical and physical addresses as the address table in the RAM25. In this example of the address table shown inFIG. 6, an entry to which each physical block address is allocated holds a corresponding logical block address. In the case shown inFIG. 6, logical block addresses “0”, “1”, and “5” are held in this order from the first entry, so physical block addresses “0”, “1”, and “2” respectively correspond to the logical block addresses “0”, “1”, and “5”.

The bad block table will be explained next. If a defect or the like makes a certain memory block unusable in the NAND flash memory11, the MPU22must grasp this memory block. Therefore, the MPU22holds an unusable memory block as a bad block table in the RAM25. In the example shown inFIG. 6, the use of memory blocks BLK3, BLK12, and BLK48is inhibited.

These pieces of system information are temporarily stored in the RAM25, and written in the NAND flash memory11at a predetermined timing.

A data write method of the memory system described above will be explained below with reference toFIG. 7.FIG. 7is a flowchart showing the processing of the card controller12when writing data.

When the card controller12starts a write operation (step S10), the MPU22first checks whether data to be written is real data supplied from the host apparatus2or the system information held in the card controller12, for example, the RAM25(step S11). If the data is the system information (YES in step S12), the MPU22generates an address in the row direction so as not to select the word lines WL0and WL31(step S13). More specifically, the MPU22first generates a block address so as to select a certain memory block. The MPU22also generates a page address to select a certain page. In this case, the MPU22generates a page address corresponding to not the word lines WL0and WL31but the word lines WL1to WL30. Subsequently, the flash controller23generates a row address on the basis of the block address and page address generated by the MPU22. In addition, the MPU22supplies a write instruction and the system information to the NAND flash memory11via the flash controller23, and the flash controller23supplies the row address to the NAND flash memory11, thereby writing the data (step S14).

In the NAND flash memory11, the row decoder32selects one of the word lines WL1to WL30on the basis of the row address, and a write circuit (not shown) supplies the system information to each bit line. Consequently, the system information is written in the memory cell transistor MT connected to one of the word lines WL1to WL30.

If the MPU22determines in step S12that the data is not the system information (NO in step S12), the MPU22performs a normal write operation. That is, the MPU22generates an address in the row direction to select one of the word lines WL0to WL31including the word lines WL0and WL31(step S15). That is, the MPU22generates a page address corresponding to one of the word lines WL0to WL31. After that, the data is written in step S14.

As described above, the memory system according to the first embodiment of the present invention achieves effect (1) below.

(1) The System Reliability can Improve (No. 1).

FIG. 8is a circuit diagram of the memory block BLK of the flash memory11according to this embodiment, and shows the way the system information is written.

In the memory system according to this embodiment as shown inFIG. 8, the card controller12writes the system information in the memory cell transistors MT connected to the word lines WL1to WL30, and does not write any system information in the memory cell transistors MT connected to the word lines WL0and WL31. In other words, when writing the system information, the card controller12does not select the word lines WL0and WL31adjacent to the select gate lines SGD and SGS, and selects the word lines WL1to WL30not adjacent to the select gate lines SGD and SGS.

In the conventional device, one of the word lines WL0to WL31is selected regardless of the type of data to be written. Accordingly, the word lines WL0and WL31adjacent to the select gate lines may be selected even when writing not only normal data supplied from the host apparatus but also data such as the system information that is important for the system to operate. However, the regularity of the arrangement of the word lines WL breaks in regions where the select gate lines SGD and SGS are formed in the memory block BLK. From the viewpoint of the semiconductor device fabrication process, therefore, defects such as bit errors readily occur on the word lines WL adjacent to the select gate lines SGD and SGS. Consequently, the system reliability deteriorates if data requiring reliability (i.e., data such as the system information required for the system to operate) is written in the memory cell transistors MT connected to the word lines adjacent to the select gate lines SGD and SGS.

When writing data requiring reliability, however, this embodiment selects word lines except for the word lines that readily cause defects, thereby preventing the loss of the data. As a consequence, the reliability of the memory system can improve.

Second Embodiment

A memory controller according to the second embodiment of the present invention will be explained below. When writing data requiring reliability in a multilevel NAND flash memory, this embodiment writes the data in a binary mode when selecting word lines adjacent to select gate lines SGD and SGS. Note that the configuration of a memory system is the same as the first embodiment described above, so a repetitive explanation will be omitted.FIG. 9is a graph showing the threshold distribution of a memory cell transistor MT in a NAND flash memory11according to this embodiment.

The NAND flash memory11according to this embodiment holds data having two bits or more. This flash memory will also be referred to as a multilevel NAND flash memory hereinafter. In this embodiment, the multilevel NAND flash memory11can hold 2-bit data. A mode in which 2-bit data is written in each memory cell transistor MT will be called a quaternary mode (or multilevel mode). A mode in which 1-bit data is written in each memory cell transistor MT will be called a binary mode. Referring toFIG. 9, the abscissa indicates a threshold voltage Vth, and the ordinate indicates the memory cell existence probability.

First, the quaternary mode will be explained. As shown inFIG. 9, the memory cell transistor can hold four data “11”, “01”, “10”, and “00” in ascending order of a threshold voltage Vth. The threshold voltage Vth of a memory cell transistor holding the data “11” is Vth<0V. The threshold voltage Vth of a memory cell transistor holding the data “01” is 0V<Vth<Vth1. The threshold voltage Vth of a memory cell transistor holding the data “10” is Vth1<Vth<Vth2. The threshold voltage Vth of a memory cell transistor holding the data “00” is Vth2<Vth<Vth3.

Next, the binary mode will be explained. As shown inFIG. 9, the memory cell transistor can hold two data “1” and “0” in ascending order of the threshold voltage Vth. The threshold voltage Vth of a memory cell transistor holding the data “1” is Vth<0V. The threshold voltage Vth of a memory cell transistor holding the data “0” is Vth1<Vth<Vth2. That is, the data “1” has a threshold voltage equal to that of the data “11” in the quaternary mode, and the data “0” has a threshold voltage equal to that of the data “10” in the quaternary mode.

In other words, the binary mode is an operation mode using only the lower bit of the 2-bit data in the quaternary mode. A card controller12controls whether to write data in the memory cell transistor in the binary mode or quaternary mode.

Data is written from the lower bit. Assuming that an erased state is “11” (“--”, —means indefinite), the memory cell transistor MT holds “11” (“−1”) or “10” (“−0”) when the lower bit is written. Data write in the binary mode is complete in this state. When writing data in the quaternary mode, the upper bit is then written. As a consequence, the memory cell transistor MT holding “11” (“−1”) holds “11” or “01”, and the memory cell transistor MT holding “10” (“−0”) holds “10” or “00”.

A data write method of the memory system described above will be explained below with reference toFIG. 10.FIG. 10is a flowchart showing the processing of the card controller12when writing data.

Processing up to step S11is the same as in the first embodiment. If data to be written is not the system information (NO in step S12), an MPU22of the card controller12writes the data in any of word lines WL0to WL31in the multilevel mode (in this embodiment, the quaternary mode) (step S20). If the data is the system information (YES in step S12) and the word line WL0or WL31is to be selected (YES in step S21), the MPU22of the card controller12writes the data in the binary mode (step S22). On the other hand, if the word lines WL0and WL31are not to be selected (NO in step S21), the MPU22writes the data in the multilevel mode (step S20).

As described above, the memory system according to the second embodiment of the present invention achieves effect (2) below.

(2) The System Reliability can Improve (No. 2).

FIG. 11is a circuit diagram of a memory block BLK of the flash memory11according to this embodiment, and shows the way the system information is written.

As shown inFIG. 11, when writing the system information in the NAND flash memory11, the card controller12writes the system information in the multilevel mode when selecting the word lines WL1to WL30, and writes the system information in the binary mode when selecting the word lines WL0and WL31. In other words, when writing the system information, the card controller12uses the binary mode when selecting the word lines WL0and WL31adjacent to the select gate lines SGD and SGS, and uses the multilevel mode when selecting the word lines WL1to WL30not adjacent to the select gate lines SGD and SGS.

As explained with reference toFIG. 9, the threshold voltage difference between data is larger in the binary mode than in the quaternary mode. Also, the stress given to the memory cell transistor MT by a write operation is smaller in the binary mode than in the quaternary mode. When written in the binary mode, therefore, the system information can be accurately held even when using the word lines WL0and WL31that readily cause bit errors. As a consequence, the reliability of the memory system can improve.

Note that this embodiment has explained that the binary mode is the operation mode using the lower bit in the quaternary mode. However, the binary mode may also be an operation mode using the upper bit in the quaternary mode. It is possible to selectively use the two operation modes in accordance with, e.g., the data holding characteristic or threshold setting method.

The above embodiment has explained the case that the binary mode is applied only when writing the system information in the word lines WL0and WL31. However, the binary mode can also be applied to write normal data supplied from a host apparatus2into the word lines WL0and WL31.FIG. 12is a flowchart showing the processing of the card controller12in this case. As shown inFIG. 12, the sequence of this processing is obtained by omitting steps S11and S12inFIG. 10. That is, the card controller12first determines whether to select the word line WL0or WL31. Then, regardless of the type of data, the card controller12writes the data in the binary mode (step S22) if the word line WL0or WL31is to be selected (YES in step S21), or writes the data in the quaternary mode if the word lines WL0and WL31are not to be selected (NO in step S21). This method can assure the reliability of normal data as well.

Third Embodiment

A memory controller according to the third embodiment of the present invention will be explained below. This embodiment takes account of bit lines as well in the first embodiment described previously. The configuration of a memory system is almost the same as the first embodiment except that a NAND flash memory11has a column decoder for selecting bit lines.FIG. 13is a flowchart showing the processing of a card controller12when writing data.

Processing up to step S11is the same as in the first embodiment. If data is the system information (YES in step S12), an MPU22generates an address in the row direction so as not to select word lines WL0and WL31(step S13). Subsequently, the MPU22generates an address in the column direction so as not to select bit lines BL0and BLm (step S30). That is, the MPU22selects a column in a memory block BLK selected by a block address so as not to select bit lines positioned at the end portions; the MPU22generates a column address so as to select bit lines BL1to BL(m−1). A row decoder32of the flash memory11receives the row address generated in step S13, and the column decoder receives the column address generated in step S30. The MPU22writes the system information in a memory cell transistor connected to a word line selected by the row decoder32and a bit line selected by the column decoder (step S14).

If the MPU22determines in step S12that the data is not the system information (NO in step S12), the MPU22performs a normal write operation. That is, the MPU22generates an address in the row direction so as to select one of the word line WL0, word lines WL1to WL30, and the word line WL31(step S15). That is, the MPU22generates a page address corresponding to one of the word lines WL0to WL31. Subsequently, the MPU22generates a column address so as to select one of the bit lines BL0to BLm including the bit lines BL0and BLm (step S31). After that, the MPU22writes the data in step S14.

As described above, the memory system according to the third embodiment of the present invention achieves effect (3) below in addition to effect (1) explained in the first embodiment.

(3) The System Reliability can Improve (No. 3).

FIG. 14is a circuit diagram of the memory block BLK of the flash memory11according to this embodiment, and shows the way the system information is written.

In the memory system according to this embodiment as shown inFIG. 14, the card controller12writes the system information in memory cell transistors MT connected to the word lines WL1to WL30and bit lines BL1to BL(m−1), and does not write any system information in memory cell transistors MT connected to the word lines WL0and WL31and bit lines BL0and BLm. In other words, when writing the system information, the card controller12does not select the word lines WL0and WL31adjacent to select gate lines SGD and SGS, and selects the word lines WL1to WL30not adjacent to the select gate lines SGD and SGS. In addition, the card controller12does not select the bit lines BL0and BLm positioned at the end portions in the memory block BLK, and selects the bit lines BL1to BL(m−1) not positioned at these end portions.

Similar to the word lines, the regularity of the arrangement of the bit lines BL breaks in a region at each end portion in the direction of the word lines in the memory block BLK. That is, in this region, another bit line exists on only one adjacent side in the direction of the word lines. Accordingly, from the viewpoint of the semiconductor device fabrication process, defects such as bit errors readily occur in this region.

By contrast, when writing data requiring reliability, this embodiment selects a bit line except for bit lines that readily cause defects. This makes it possible to improve the reliability of the memory system.

Fourth Embodiment

A memory controller according to the fourth embodiment of the present invention will be explained below. This embodiment is a combination of the second and third embodiments described above. That is, when writing data requiring reliability in a multilevel NAND flash memory, the data is written in a binary mode when selecting word lines adjacent to select gate lines SGD and SGS and bit lines positioned at the end portions of a memory block BLK.FIG. 15is a flowchart showing the processing of a card controller12when writing data.

Processing up to step S21is the same as in the second embodiment. If word lines WL0and WL31are selected (YES in step S21), the system information is written in the binary mode in the same manner as in the second embodiment (step S22). If the word lines WL0and WL31are not selected (NO in step S21) and bit lines BL0and BLm are selected (YES in step S40), the system information is similarly written in the binary mode (step S22). If the word lines WL0and WL31are not selected (NO in step S21) and the bit lines BL0and BLm are not selected either (NO in step S40), the system information is written in a multilevel mode (step S20).

As described above, the memory system according to the fourth embodiment of the present invention achieves effect (4) below in addition to effect (2) explained in the second embodiment.

(4) The System Reliability can Improve (No. 4).

FIG. 16is a circuit diagram of the memory block BLK of a flash memory11according to this embodiment, and shows the way the system information is written.

In the memory system according to this embodiment as shown inFIG. 16, when writing the system information in the NAND flash memory11, the card controller12writes the system information in the multilevel mode when selecting word lines WL1to WL30and bit lines BL1to BL(m−1), and writes the system information in the binary mode when selecting the word lines WL0and WL31and bit lines BL0and BLm. In other words, when writing the system information, the card controller12uses the binary mode when selecting the word lines WL0and WL31adjacent to the select gate lines SGD and SGS and the bit lines BL0and BLm at the memory block end portions, and the multilevel mode when selecting the word lines WL1to WL30not adjacent to the select gate lines SGD and SGS and the bit lines BL1to BLm not at the memory block end portions.

As explained in the second embodiment, therefore, when written in the binary mode, the system information can be accurately held even when using the word lines WL0and WL31and bit lines BL0and BLm that readily cause bit errors. As a consequence, the reliability of the memory system can improve.

It is a matter of course that the binary mode may also be an operation mode using the upper bit in the quaternary mode in this embodiment as well. Also, the binary mode can be applied to write normal data supplied from a host apparatus2into the word lines WL0and WL31and bit lines BL0and BLm.

Fifth Embodiment

A memory controller according to the fifth embodiment of the present invention will be explained below. This embodiment is directed to a method of determining whether to apply the first to fourth embodiments described above. The configuration of a memory system is the same as the first to fourth embodiments, so a repetitive explanation will be omitted.FIG. 17is a flowchart of a data write method of a card controller12.

As shown inFIG. 17, an MPU22starts a write operation (step S10), generates a block address (step S50), and checks the reliability of a memory block corresponding to the generated block address (step S52). The reliability herein mentioned relates to the data holding characteristic. If the MPU22determines that the reliability is low (YES in step S52), the MPU22writes data by using the method according to one of the first to fourth embodiments described above (step S53). If the MPU22determines that the reliability is not low (NO in step S52), the MPU22writes the data by a normal method (step S54). That is, the MPU22selects word lines and bit lines regardless of their positions.

Although the determination method in steps S51and S52can be appropriately selected, two examples will be explained below.FIG. 18is a table (to be referred to as an error table hereinafter) showing the relationship between each of memory blocks BLK0to BLKn and an ECC (Error Checking and Correcting) error occurrence ratio. The MPU22counts ECC errors having occurred in the memory blocks BLK0to BLKn, calculates occurrence ratios R0to Rn, and holds them as an error table in a RAM25. The RAM25also holds an occurrence ratio threshold Rth. In step S51, the MPU22reads out an occurrence ratio Ri (i is one of 0 to n) of the memory block corresponding to the generated block address and the occurrence ratio threshold Rth, and determines that the reliability is low if Ri>Rth. For example, if a block address corresponding to the memory block BLK0is generated, the MPU22reads out the occurrence ratio R0and occurrence ratio threshold Rth from the RAM25. If R0>Rth, the MPU22determines that the reliability is low because many ECC errors have occurred in the memory block BLK0(YES in step S52).

The other method will be explained with reference toFIGS. 19A and 19B.FIGS. 19A and 19Bare block diagrams of a memory cell array30, and illustrate the arrangement of the memory blocks BLK. As shown inFIGS. 19A and 19B, the MPU22determines that memory blocks BLK (hatched memory blocks inFIGS. 19A and 19B) positioned at the end portions in the memory cell array30have low reliability. More specifically, as shown inFIG. 19A, when memory blocks (memory blocks not hatched inFIG. 19A) surrounded by other memory blocks are selected, the MPU22determines that the reliability of the selected memory blocks is not low. Alternatively, as shown inFIG. 19B, when memory blocks (memory blocks not hatched inFIG. 19B) each having two opposing sides sandwiched between other memory blocks are selected, the MPU22determines that the reliability of the selected memory blocks is not low.

As described above, the memory system according to this embodiment achieves effect (5) below in addition to effects (1) to (4) explained in the first to fourth embodiments.

(5) The Memory Cell Array can be Efficiently Used.

This embodiment applies the write method explained in the first to fourth embodiments to only memory blocks BLK found to have low reliability, and the conventional method to other memory blocks. This makes it possible to efficiently use word lines and bit lines to which the methods of the above embodiments need not be applied.

As described above, the memory systems according to the first to fifth embodiments of the present invention write data requiring reliability, e.g., the system information by avoiding word lines and bit lines that often cause bit errors. Accordingly, it is possible to improve the system information holding characteristic and reliability of the memory system.

Note that each of the above embodiments has explained the case that word lines are selected by avoiding only the word lines WL0and WL31. As shown in a circuit diagram ofFIG. 20, however, it is also possible to leave the two word lines WL0and WL1on the side of the select gate line SGD and the two word lines WL30and WL31on the side of the select gate line SGS unselected, or write data in these word lines in the binary mode. It is a matter of course that the number of word lines not to be selected need not be two but may also be three or more and the number of word lines not to be selected on the side of the select gate line SGD can be different from that on the side of the select gate line SGS. This is of course similarly applicable to bit lines. That is, it is possible to leave the bit lines BL0and BL1and the bit lines BL(m−1) and BLm at the memory block end portions unselected, or write data in these bit lines in the binary mode. Also, the number of bit lines not to be selected need not be two but may also be three or more, and the number of bit lines not to be selected on the side of the bit line BL0can be different from that on the side of the bit line BLm.

Furthermore, the present invention is also applicable to the case that a dummy word line is formed between the select gate line SGD and word line WL0or/and between the select gate line SGS and word line WL31.FIG. 21is a circuit diagram of a NAND cell. As shown inFIG. 21, this NAND cell has dummy transistors DT1and DT2. The dummy transistor DT1has a drain connected to the source of the selection transistor ST1, and a source connected to the drain of the memory cell transistor MT connected to the word line WL0. The dummy transistor DT2has a source connected to the drain of the selection transistor ST2, and a drain connected to the source of the memory cell transistor MT connected to the word line WL31. The gates of the dummy transistors DT1and DT2are connected to dummy word lines. The dummy word lines are grounded so as not to be selected. Note that the dummy transistors DT1and DT2connected to the dummy word lines have a negative threshold voltage, and are normally ON. That is, no row addresses are allocated to the dummy word lines; row addresses are allocated to only the word lines WL0to WL31.

FIG. 22shows another arrangement including dummy word lines.FIG. 22is a circuit diagram of a NAND cell. As shown inFIG. 22, the arrangement of this NAND cell is the same asFIG. 21except that the dummy word lines are not grounded. In this arrangement shown inFIG. 22, the dummy word lines are also connected to the row decoder32, but the row decoder32does not select these dummy word lines. That is, row addresses are allocated to the dummy word lines as well, but the card controller12generates a page address so as not to select the dummy word lines.

The first to fifth embodiments are also applicable to the arrangements shown inFIGS. 21 and 22to write the system information by avoiding the word lines WL0and WL31or in the binary mode. To avoid word lines having low reliability, however, when writing the system information, it is also possible to use a method that uses the word lines WL0and WL31in the case shown inFIG. 21, and does not use the word lines WL0and WL31in the case shown inFIG. 22.

The first to fifth embodiments can also be applied to semiconductor memories other than the NAND flash memory. That is, the present invention is widely applicable to any semiconductor memory having an arrangement in which a plurality of bit lines are regularly arranged, and bit errors occur when the regularity breaks as in the NAND flash memory. As an example, the present invention is also applicable to “a TC parallel unit series-connected ferroelectric memory” in which the two terminals of a capacitor (C) are connected between the source and drain of a cell transistor (T) to form a unit cell, and a plurality of unit cells are connected in series.FIG. 23is a view showing an example of the arrangement of the main part of this ferroelectric memory.

That is,FIG. 23is a circuit diagram showing a portion of a memory cell array of the TC parallel unit series-connected ferroelectric memory. As shown inFIG. 23, this memory cell array includes cell blocks BLK and block selection transistors BST. The cell block BLK includes a plurality of series-connected memory cells MC. Referring toFIG. 23, the number of memory cells MC included in one memory block is eight. However, the number of memory cells MC is of course not limited to eight, and can also be 16 or 32. The memory cell MC includes a MOS transistor T and ferroelectric capacitor C. The ferroelectric capacitor C is a capacitor element using a ferroelectric material as a capacitor insulating film. As this ferroelectric material, it is possible to use, e.g., lead zirconate titanate (Pb—Zr—Ti—O: PZT) or strontium-bismuth tantalate (Sr—Bi—Ta—O: SBT). The ferroelectric capacitor C has one electrode connected to the source of the cell transistor T, and the other electrode connected to the drain of the cell transistor T. The source of the cell transistor T is connected to the drain of the cell transistor T of an adjacent memory cell MC on one side, and the drain of the cell transistor T is connected to the source of the cell transistor T of an adjacent memory cell MC on the other side. The gate electrodes of the cell transistors T included in the memory cells MC are connected to word lines WL0to WL7. The source of the cell transistor T of the memory cell MC positioned closest to the source and connected to the word line WL7is connected to a plate line PL. The drain of the cell transistor T of the memory cell MC positioned closest to the drain and connected to the word line WL0is connected to a bit line BL via the block selection transistor BST. That is, the block selection transistor BST has a source connected to the drain of the cell transistor T connected to the word line WL0, and a drain connected to the bit line BL. Also, a block selection signal line BS is connected to the gate of the block selection transistor BST.

In the above arrangement, the regularity of the word lines WL breaks in a portion where the word line WL0and block selection signal line BS are adjacent to each other, and in a portion where the word line WL7and plate line PL are connected. When writing data requiring reliability, therefore, a method that does not select the word lines WL0and WL7can be applied.