Self-adaptive program delay circuitry for programmable memories

A self-adaptive programming circuit for EEPROM is used to automatically tune an erase or write delay, providing an improved programming window. The programming circuit may also provide improvements in data retention for programmed memory cells. The invention can be applied more particularly in the field of EEPROM memories capable of page mode writing operations.

INCORPORATION BY REFERENCE

FIELD OF THE INVENTION

The present invention relates to integrated circuit memory architectures. More specifically, the invention relates to a new programming operation protocol and memory architecture for programmable memories allowing “intelligent programming.”

BACKGROUND ART

FIG. 1shows the array architecture of a programmable EEPROM memory, based on a matrix of rows and columns. Each row and each column correspond to a plurality of word lines101,102, . . . ,10n, and a plurality of bit lines201,202, . . . ,20n, (bits are accessible at 2nbits per word) respectively. An exemplary memory cell30is located on each word line10and bit line20intersection. The memory cell30is composed of a select transistor31and a floating gate transistor32connected in series. The gate of the cell select transistor31is connected to the word line10, its drain to the bit line20, and its source to the drain of the floating gate transistor32. A floating gate transistor source34is connected to ground via source line35, and the floating gate transistor's gate36may be logically connected to a Vref line40when enabled by a word select device11.

Data storage in a floating gate transistor is obtained by varying electrical charge that exists on the floating gate. To obtain a logical l value (erased state), electrons must be injected into the floating gate, which increases the threshold voltage of the floating gate transistor32. To obtain a logical 0 value (written state), electrons must be extracted from the floating gate, which decreases the threshold voltage of the floating gate transistor32. A mechanism referred to as Fowler Nordheim Tunneling is used for both erase and program operations on an EEPROM memory. This mechanism is very slow (in the millisecond range) and requires a high voltage source Vppthat is generated by a circuit within the EEPROM memory chip. The Vrefline40is driven to Vppduring an erase operation and grounded during a write operation. The bit line20is left floating during an erase operation and connected to Vppduring a write operation.

Erasing a cell is obtained by applying a high voltage Vppon the gate36of the floating gate transistor32(via word select device11and Vrefline40), and ground to the floating gate transistor's source34(by grounding source lines35). To write the memory cell30, Vppmust be applied to the drain of the floating gate transistor32(via bit line20and cell select transistor31), the floating gate transistor's gate36must be grounded (via word select device11and Vrefline40), and the floating gate transistor's source34is left floating (by floating source lines35).

If memory cells30share the same Vrefline40, multiple memory cells may be grouped into words and may be erased in parallel. Also, each bit (memory cell) may be written independently by driving its corresponding bit line20to Vpp.

Word programming is obtained in two steps. First the word is erased and all of the erased bits are set to a logic 1 value after erase. Secondly, all of the necessary bits in the word are written at the same time, changing all bits to a logic 0 value in order to program the targeted word data.

With reference toFIG. 1, depending on the threshold voltage (Vth) of the floating gate transistor32, each memory cell30will be conducting or not conducting current. If the threshold voltage Vthis higher than the reference voltage Vref, the memory cell30is OFF. If Vthis lower than Vref, the memory cell30is ON. A threshold voltage Vthmay be adjusted by injecting or removing electrons from the floating gate of each floating gate transistor32during a memory cell30or word programming operation. During an erase operation, electrons are injected into the floating gate resulting in a high threshold voltage value Vthhigh. During a write operation, electrons are removed from the floating gate, resulting in a low threshold voltage Vthlow. The difference between the high Vthhighand the low Vthlowis referred to as a program window. The reference voltage value normally applied to the gate of a memory cell30during a read operation is between Vthhighand Vthlow. Due to a possible charge loss from the floating gate, after for example several years, a wide program window is desirable to prevent possible data loss.

The data retention characteristics of each memory cell30will depend on a capability of the memory cell30to reliably maintain voltage thresholds over time, due to an intrinsic floating gate charge loss. In addition, characteristics of a memory cell30may change after several erase and write cycles, resulting from a negative charge trapping phenomenon. These technical characteristics of the memory cell30make it difficult to guarantee an acceptable data retention capability.

Therefore, it is desirable to have a program window that is as wide as possible to compensate for characteristics of a programmable memory cell that may affect the integrity of data stored within a memory cell.

SUMMARY OF THE INVENTION

The present invention is a circuit to produce an automatically tuned programming pulse to compensate for a negative charge trapping phenomenon in the oxide of a floating gate transistor and to compensate for low supply voltage and temperature changes. The programming pulse is tuned according to programming conditions such as temperature and supply voltage. The memory is controlled as necessary to provide improved data reliability under a variety of conditions such as temperature and the number of times the floating gate transistor has been programmed. Using the tuned programming pulse results in better data retention capability even when using a part that has been repeatedly programmed. In addition, because the programming pulse is optimized, the power consumption is also optimized and the memory is stressed less. The present invention is also a method to program and verify a memory cell, using a read voltage that is different than a normal read voltage, after either an erase operation or write operation, and automatically adjusting the parameters of the programming pulse.

DETAILED DESCRIPTION OF THE INVENTION

The present invention is a self-adaptive programming operation that tunes the programming pulse delay time used in an erase or write operation, based on a read operation and comparison to an expected logic value for the memory cell30. Erase and write delays are tuned automatically to maintain an acceptable program window under a variety of conditions. Increasing the programming pulse delay on a cycled part is a method used to recover an acceptable program window and to recover desired memory cell retention characteristics. For example, another programming pulse is applied after a comparison failure, when charges trapped in the oxide of the floating gate transistor32make the programming mechanism less efficient. Endurance, data retention, and power consumption characteristics may also be improved by the present invention.

In an exemplary embodiment of the present invention, an automatic tuning of the number of programming pulses increases to compensate for an erase operation or write operation failure of any memory cell within a programmable EEPROM memory. With reference toFIG. 2, exemplary EEPROM memory device that contains a memory core101, a “data in” block102, a bit line select104, column latch110, address decoders120,130,140, sense circuits105, a charge pump159, control logic155, control lines151, and a write timer154. In addition, a program failure flag152, a dedicated sequencer150, dedicated latch circuitry, a verify timer160, an address counter173, multiplexers170,175, comparator103, and a margin reference voltage (Vref) generator154are necessary to implement the self-adaptive programming. The memory core101represents an array architecture similar to the array architecture of an EEPROM memory as shown inFIG. 1.

In the exemplary embodiment, sequencer150is a state machine used to implement an embodiment of a programming algorithm (details of the programming algorithm are described in detail with respect toFIGS. 6 and 7). In alternate embodiments, the functions of a sequencer150may be performed by a dedicated controller or by a processor. The sequencer150is connected to control logic155, and to write timer153. The control logic155turns charge pump159on or off to provide voltage Vpp. The write timer154controls a programming pulse width. The sequencer150delivers erase and write pulses to the write timer154. During a verification operation, the address counter173generates a required addresses beginning at a first address. Addresses are provided to the Yld120and Yrd140address with and decoders via multiplexers170,175. Any erased memory cell30should be equal to a logic 1 value. An erased word logic value should be equal to a group of 2nbits, each bit having a logical 1 value. For example, an eight bit word should have a hex value of FF after an erase operation. The comparator103also compares a memory cell30or word in the memory array that has been written to the content of column latches containing an expected data or logic value.

The content of at least one programmed memory cell30is verified automatically (see further details below) and a programming operation is completed when a verification of a programmed memory cell30is successful. A read margin mode test is used to verify the quality of a programming operation. A margin voltage reference is used in a read margin mode test. The voltage reference Vrefis increased when reading OFF cells and decreased when reading ON cells and comparison to a normal read voltage reference. For example, a margin of approximately ±0.5 volts is used. Using a margin voltage reference during a read operation guarantees that the memory cell stays OFF when memory cell30is read with Vref+0.5V on its gate, and the memory cell stays ON when memory cell30is read with Vref−0.5V on its gate. During a verification operation, a word in the memory core (array)101is read using a margin mode by applying an internally generated Vrefvalue by the margin Vrefgenerator154.

A programming operation that programs a logic value in at least one memory cell30is divided in three phases or operations: load, erase, and write.

Programming current for a single cell is very small, making programming several bits in parallel possible. To improve the programming speed of EEPROM memory, it is possible to erase or write several words in the same row or multiple words in a page at the same time. However, the data to be programmed must be loaded into a dedicated buffer (latch) before starting a parallel write operation. A column latch110buffer system is composed of one column latch110per bit line20and one column latch per Vrefline40. In an exemplary embodiment, there is a column latch110for each bit line20and a column latch110for each Vrefline40. A memory core101having a column latch110coupled to each bit line provides an erasure operation by word (one or more bits), and a selective write operation (by bit or by word).

The column latch110provides two functions. The column latch stores data and also brings Vppto a corresponding bit line20. Data to be programmed into a memory cell30is loaded into at least one column latch110. A group of 2nbit latches and one Vreflatch (or byte flag) store the data to be programmed on a targeted row. During a load operation, the Yaddress bus AddYld171is decoded by the Ydl-decoder120. A data value is loaded into at least one word of column latches110coupled to the bit lines20. A logical value (flag signal) is also stored in an associated Vrefcolumn latch. Words that will be used to program memory cells30are selected by using the flag signal loaded into the associated Vrefcolumn latches110. Word lines are selected by an Xaddress on Xdecoder input131, which is decoded by an Xdecoder130. When all of the data words have been loaded, erase voltages are applied on selected words.

The latch circuit may be incorporated into the column latch110block shown inFIG. 2.FIG. 3illustrates circuits disclosed in U.S. patent application Ser. No. 10/737,676 titled “EEPROM Architecture and Programming Protocol” that may be used in an embodiment of the present invention. The latch circuit comprises a pass transistor and a pair of feedback inverters to provide a state latch210operation. Column latch210may be used during an erase operation and/or a memory write operation. The column latch circuit210includes a state latch212and a state latch pass transistor220that is controlled by a load control signal applied to a gate230of the state latch pass transistor220. In addition, the column latch circuit210includes circuitry to provide reference and programming voltages Vpp. Data control pass gate240is coupled to the latch output211, and controlled by a data control input241. The data control pass gate240is coupled to a level shift circuit270to provide a voltage to the memory array different than the voltage used in the state latch circuit210. The data control pass gate240is also coupled to a Vpppass gate250to apply a Vppvoltage to a column (bit line20).

During the load period, an input data on input Din201is input to the column latches110using the Yld decoder120. A load control signal is applied to a gate230of the state latch pass transistor220is set to a logic 1 value in order to latch a data input value via Din201into at least one state latch212. The loaded data is a logic 1 value to program a memory cell30that is OFF, and a logic 0 value to program a memory cell30that is ON. In addition, a logic 1 value is loaded into a Vreflatch corresponding to each word to be programmed. The loading period ends when all the words at each desired address have been loaded one by one into each latch that corresponds to a memory cell30targeted for a programming operation. Address counter173is used to count or increment a memory core address as part of a verify operation. AddYint172may start from address location1, and is decoded by both the load and read decoders120,140.

Next after completing a load operation, memory cells30are erased as 2nbit words in parallel. In the erasure stage, electrons are injected into the floating gate structure by holding the gates of floating gate transistor32(inFIG. 1) at an elevated voltage Vpp. A Vppvoltage is provided by at least one Vrefcolumn latch through the word select pass gate11. To implement an erase operation, the X Decoder130as shown inFIG. 2applies Vppon a word line corresponding to an AddX address (corresponding to word line11inFIG. 1). The data control pass transistor240is toggled ON, the Vrefcolumn latch210drives or turns the (voltage) level shifter circuit270on, and applies Vppvia bit line pass transistor250to the control Vrefline(s)40.

The required erase voltage Vppis applied as a pulse having an applied duration. The applied duration is referred to as an erase time delay Terase. Application of the Vppvoltage pulse causes electrons to accelerate to the selected floating gates320. The increase in electrons that are held in the floating gate increases the cell's voltage threshold Vth. The selected words are then erased and each selected bit is set to a logic value of 1. After the erase operation is completed, an erase verification operation is executed300as illustrated by the exemplary algorithm inFIG. 6(described further below).

After an erase operation is completed, a write operation may be executed. During a write operation, the X decoder130(via word select device11) applies Vppon the word line(s)10selected by AddX on Xdecoder input131. As shown inFIG. 3, Vpppass transistor250, controlled by column latch210and applying a control signal241to the gate of pass transistor240, applies Vppto bit lines20(inFIG. 1) that have been selected. In each column latch210, the content of each state latch is connected to the input of the level shift circuit270when the data control pass transistor240turns ON by driving the data control input201. If the state value of latch output211is a logic value 0, then the gate of Vpppass gate250retains a logic 0 value, and the bit line260is left floating. In the case when the state latch output211is a logic value 0, a corresponding memory cell is not written, and remains at a logic 1 value after an erase operation has been completed. If the state latch output211is a logic value 1, then Vpppass gate250is switched to Vppby level shift circuit270. In the case when the state latch output211is a logic value 1, Vpppass gate250is conducting, and voltage Vppis transmitted to bit line(s)260. The selected memory cell is written and a logic value of the memory cell is changed to a logic 0 value.

When the write operation is completed, the write operation is then automatically verified. The written memory cell30is read and its value is compared with an expected data value stored in a corresponding latch.

A verification operation is performed after an erase operation or after a write operation has been performed. A verification operation reads at least one memory cell30and compares the contents of the memory cell30with an expected value. For an erase operation, the expected value of each memory cell is a logical 1 value. An erased word logic value should be equal to a group of 2nbits, each bit having a logical 1 value. For example, an eight bit word should have a hex value of FF after an erase operation. Erased words, for example, will be compared to the value FF. For a write operation, an expected value is the logical value that is stored in the column latch110,210associated with each memory cell30. Both the logical value that is stored in at least one column latch110,210and the value that is stored in at least one memory cell30are read. When verifying a write operation, the logic value of the memory cell30is compared to the logic value that is stored in the corresponding column latch110,210.

In a memory cell30read operation, a reference voltage Vrefis applied to the gate of floating gate transistor32. The reference voltage may be a normal reference voltage or a margin reference voltage. The drain current of floating gate transistor32, measured by sense circuits105(inFIG. 2) indicates whether there are stored electrons in the floating gate of the floating gate transistor32. A programmed cell draws less drain current than a reference cell indicating a stored logic 0 value.

In an exemplary embodiment of a read operation, a reference voltage Vrefis applied via word select device11to the gate36of each selected floating gate transistor32. Additionally, voltage Vddis applied to the gate of select transistor31. A floating gate transistor32is selected by an activated word line10and by activated bit line20. The bit lines20are connected to sense circuits105through the bit line select circuit104. In an alternate embodiment for low voltage applications, twice the Vddvalue is applied to the gate of select transistor31. A voltage under 1 volt is applied to the drain of the word select transistor11.

FIG. 4illustrates an exemplary embodiment of a column latch circuit210containing additional circuitry that may be used during a column latch read operation. In a read operation, the Xaddress decoder130and Yaddress decoder120,140specify locations of a memory cell30and a column latch210to be read. Inverter221is used to isolate output line211from data line Din201. This prevents connecting the output of the state latch212directly to the capacitive load of data line Din201. Without inverter221, inadvertent switching of state latch212may occur from a capacitive charge transfer. For the same reason, the content of state latch212cannot be read directly through state latch pass transistor220. To perform a read operation of the state latch212, a read pass transistor222is activated and the state of state latch212is read on the data line Din201.

A verification process is executed when a memory word is read and compared to an expected logic value. For example when verifying whether a memory cell30has been properly erased, the expected word value is, for example, FF. In an exemplary embodiment, the comparison is performed via a dedicated comparator103. The verification process is automatically executed after a word or plurality of words in the memory array have been erased or written. Comparator103(shown inFIG. 2), compares an erased word's bits to a logic 1 value, and compares a written word to the content of the column latches. For a write operation verification, the logic values of programmed data have been loaded into the column latches210and are readable.

FIG. 5illustrates an exemplary embodiment of a selective Vrefcolumn latch210that contains a separate tag latch224. Tag latch224is used as a Vreftag or word latch. If the Vreftag has been set to a logic 1 value, the tag indicates that the corresponding memory word has been erased. Tag latch224may be loaded using the load tag line226, which controls tag pass transistor223. Load tag line226, may be operated in conjunction with state latch load230to load the same state when state latch pass gate220is active and Din201is stable. Alternatively, the load tag line226may be used separately to load a separate tag logic value into tag latch224. A separate read tag line225controlling tag pass transistor222reads the stored value in the tag latch224during a read operation.

During a verification operation performed during both the erase and write operations, a cell is read using a dedicated margin mode operation and compared to an expected logic 1 value for erased cells or alternatively, the data stored in column latches110for written cells. The dedicated read margin mode ensures that memory cells30are programmed with enough margin to maintain a set logic value over time regardless of the floating gate transistor32that is susceptible to natural charge variations. To verify the quality of a programming operation, Vrefis increased when reading OFF cells and decreased when reading ON cells. During the margin mode read operation, reference generator154, as shown inFIG. 2, generates an internal reference voltage that is higher than a voltage used in a normal read operation. For example, a margin of approximately 0.5 volts guarantees that a memory cell30stays OFF when reading a particular memory cell30with Vref+0.5 volts on its gate and stays ON when reading a particular memory cell30with Vref−0.5 volts on its gate.

A verification operation may be performed using more than one method. A margin mode read operation verifies that the voltage threshold Vthof each cell is high enough to overcome any floating gate variations that are related to environmental conditions (for example, temperature) or to an undesired storage of electrons (for example, trapped oxide charges.

InFIG. 6, and exemplary erase algorithm using an automatic verification operation is shown. After initializing a pulse counter310, a first erase pulse is applied320to the target cells30. A verify operation330initializes an address counter. If memory cells30have been properly erased, an address counter173is incremented and another group of memory cells is verified. If the memory cells have not been properly erased, another pulse is applied332, the pulse counter is incremented332, and the memory cells are verified again330. If a predetermined pulse counter value is reached, the verify operation330will stop, the erase operation will stop331, and a program failure flag152will be set333. If all of the memory cells30pass the erase and verification operations, a final erase pulse may optionally be applied350.

In one embodiment, speed is optimized in the verification operation. If the comparison result confirms that the threshold voltage Vthfor a verified cell or word is correct, Addyint is incremented and the next erase and verification operation is performed on the next word330. If the threshold voltage Vthfor the verified cell or word is not correct, at least one cell is not well erased. When the verify procedure fails, the erase pulse is then applied332again to of all the words to be programmed—even to those that successfully passed a previous verify operation. Additional erase and verify330operations are performed until all of the cells pass verification or until a maximum number of erase pulses have been reached. When the previously failed cells subsequently pass verification, an erase time is optimized. If the erase time maximum is reached by the verify timer160(inFIG. 2) and the cells have not passed verification330, the verify operation using a margin mode stops331and sequencer150(shown inFIG. 1) sets333a programming failure flag152. If all of the cells pass the verification operation (using a margin mode)330, meaning that the desired erase time has been reached, a write phase then begins410. The option of applying a final erase pulse350using an optimized erase time may be executed.

When the erase time has been optimized, the high voltage condition for a memory cell30erase has been applied to all the words to be programmed. Although this verification procedure quickly optimizes the erase time, words that have been previously erased will be erased again each time the program increments the erase time counter. The result may unnecessarily over-stress previously erased cells.

Referring again toFIG. 6, an alternative embodiment of a verification operation may be implemented that avoids unnecessary stress on correctly erased words. Using the modified Vrefcolumn latch210(shown inFIG. 5), tag latch224(inFIG. 5) stores an independent tag indicating that the word has been erased at least once. When a word address is loaded, the tag is latched as an indication that the word has not passed verification. The Vrefcolumn latch will pass Vppduring the first erase pulse. At the application of the first erase pulse320, each word to be programmed is erased. Next, the words are read in margin mode during a verification operation430. After the first erase pulse has been applied320, the erase voltage Vpp is selectively applied to only words that are not well erased (words that fail during the verification).

If a word fails a verification operation, the tag latch212is set to indicate a verification failure. The verification operation proceeds until all the words in memory have been verified. During a verification operation, any properly erased word will not be erased again during an application of a subsequent erase pulse350. An erase pulse350will be applied to all the words in the memory core that have failed verification if at least one Vrefcolumn latch data is set, meaning that at least one word is not correctly erased. When a new erase pulse is applied350, Vppwill not be applied to properly erased words because the corresponding Vrefcolumn latches have been set during the verification operation. The tag latch224state is maintained and will be used during the verification procedure of a subsequent write phase.

As illustrated inFIG. 7, during a write phase400, the application of write voltages420are applied to selected cells and a write verify430will be performed after each writing pulse. The operation of a write verification operation is similar to the erase verification described above. The address counter173(inFIG. 2) that provides an AddYld171and AddYrd176address is initialized410. Similar to an erase verify operation, the Vrefcolumn latch210or224is read. If the Vrefcolumn latch210has not been set, indicating that the corresponding word is not programmed, the Y internal address is incremented. If the Vrefcolumn latch210has been set, the content of the column latch word corresponding to the data to be written is read. The selected word in the memory core101that has been written is read in margin mode430and compared to the state of the column latch212. To verify that ON cells are programmed with enough margin, the gates of the memory cells32are grounded via each pass gate31to each bit line.

If the latch and memory cells do not match, the comparison stops431, indicating that at least one cell has not been correctly written. If a memory cell30fails the verification operation and a maximum number of verify iterations has been reached, the verify operation stops431and sequencer150(shown inFIG. 1) sets433a programming failure flag152.

If the contents of the latch and memory cell comparison match, the address counter173(inFIG. 2) is incremented432. After each verification operation, column latches210corresponding to the words that are correctly written can be reset in order to avoid unnecessary over-write of the word. As each memory cell passes the verification operation, the address counter is iteratively incremented432and another write pulse is applied432, followed by a verify procedure430. When all desired memory cells have passed the verify procedure, the write process ends450.

The proposed invention is the first architecture to provide an intelligent and automatic, self-adaptive EEPROM memory cell programming operation that performs a parallel-write operation. Using specific column latches, dedicated timers, and an internally controlled verify procedure, it is possible to reduce the number of pulses and time required to complete erase and write operations. Using this method, a verification operation adapts to programming conditions such as power supply and temperature variations, individual memory cell programming variations due to cell distributions across the array, and memory cell degradation after repeated erase and write cycles. In addition, the programming power consumption may be optimized, while ensuring reliable program operations over a variety of program conditions. Finally, if a memory cell programming issue occurs, it is detected and a dedicated memory program failure flag is set.

It is to be understood that the above description is intended to be illustrative, and not restrictive. Those of skill in the art will recognize that the invention can be practiced with modification and alteration within the spirit and scope of the appended claims. Embodiment(s) of the invention so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic described. Repeated use of the phrase “in one embodiment” does not necessarily refer to the same embodiment, although it may. Many other embodiments will be apparent to those of skill in the art upon reading an understanding the above description. For example, the present invention would apply to types programmable memory, other than an exemplary EEPROM. The description is thus to be regarded as illustrative instead of limiting. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which said claims are entitled.