Method for forming shallow trench isolation structure

A method for forming a shallow trench isolation structure. A pad oxide layer is formed over a substrate. A hard mask layer is formed over the pad oxide layer. A portion of the hard mask layer, the pad oxide layer and the substrate is removed to form a trench in the substrate. Insulation material is deposited into the trench to form an insulation plug. The hard mask layer is removed to expose the sidewalls of the insulation plug. Spacers are formed on the exposed sidewalls of the insulation plug. Ions are implanted into the substrate. The pad oxide layer, the spacers and a portion of the insulation plug are removed. Finally, a gate oxide layer thicker in region around the edge of the insulation plug is formed over the substrate by oxidation.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
The present invention relates to a method for forming a semiconductor 
device. More particularly, the present invention relates to a method for 
forming shallow trench isolation (STI) structures. 
2. Description of the Related Art 
Advances in the production of integrated circuits have led to an increase 
in the level of integration and the miniaturization of semiconductor 
devices. As the level of integration increases, both the dimensions of 
each device and size of the isolating structures between devices are 
reduced. Consequently, device isolation structures are increasingly harder 
to form. Device isolation structures such as a field oxide layer formed by 
local oxidation (LOCOS) is no longer suitable for small dimensional device 
due to the intensification of bird's beak encroachment problem. Therefore, 
shallow trench isolation (STI) method has been developed for highly 
integrated circuits, and sub-half micron integrated circuits in 
particular. 
In general, a shallow trench isolation (STI) structure is formed by 
performing an anisotropic etching operation using a silicon nitride hard 
mask to form a steep-sided trench in a semiconductor substrate. Oxide 
material is deposited into the trench to form an oxide plug. However, the 
aforementioned method of STI fabrication often results in the formation of 
recess cavities, resulting in locally intensified electric field. This 
leads to an abnormal sub-threshold current leakage in the transistor 
channel, resulting in the intensification of the kink effect. Hence, the 
transistor can no longer operate normally and reliably. 
SUMMARY OF THE INVENTION 
Accordingly, one object of the present invention is to provide a method for 
forming a shallow trench isolation (STI) structure capable of preventing 
the formation of any recess cavities around the edge region of its 
insulation plugs. 
To achieve these and other advantages and in accordance with the purpose of 
the invention, as embodied and broadly described herein, the invention 
provides a method for forming a STI structure. A pad oxide layer is formed 
over a substrate. A hard mask layer is formed over the pad oxide layer. A 
portion of the hard mask layer, the pad oxide layer and the substrate is 
removed to form a trench in the substrate. Insulation material is 
deposited into the trench to form an insulation plug. The hard mask layer 
is removed to expose the sidewalls of the insulation plug. Spacers are 
formed on the exposed sidewalls of the insulation plug. Ions are implanted 
into the substrate. The pad oxide layer, the spacers and a portion of the 
insulation plug are removed and then an oxide layer is formed over the 
substrate by oxidation. 
The invention also provides an alternative method for forming a STI 
structure. A trench is formed in a substrate. Insulation material is next 
deposited into the trench to form an insulation plug that rises to a level 
above the top surface of the substrate. Spacers are formed on the exposed 
sidewalls of the insulation plug. Ions are implanted into the substrate. 
An oxide layer is formed over the substrate by oxidation. 
In this invention, a thicker gate oxide layer is formed around the edge of 
the insulation plugs, so as to reduce the electric field. Therefore, the 
kick effect generated from a locally intensified electric field is 
compensated. 
It is to be understood that both the foregoing general description and the 
following detailed description are exemplary, and are intended to provide 
further explanation of the invention as claimed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
Reference will now be made in detail to the present preferred embodiments 
of the invention, examples of which are illustrated in the accompanying 
drawings. Wherever possible, the same reference numbers are used in the 
drawings and the description to refer to the same or like parts. 
FIGS. 1A through 1H are schematic cross-sectional views showing the 
progression of manufacturing steps for producing a shallow trench 
isolation structure according to this invention. 
As shown in FIG. 1A, a pad oxide layer 102 is formed over a silicon 
substrate 100. The pad oxide layer 102 protects the substrate 100 against 
subsequent processing operations. In general, the pad oxide layer 102 is 
formed by chemical vapor deposition, and is removed before the deposition 
of a gate oxide. A hard mask layer 104 is formed over the pad oxide layer 
102. Using photolithographic and etching processes, the mask layer 104 is 
patterned to expose a portion of the pad oxide layer 102. The exposed pad 
oxide layer 102 and the substrate 100 are sequentially etched to form a 
trench 106 in the substrate 100. 
As shown in FIG. 1B, a liner oxide layer 108 is formed on the exposed 
substrate surface inside the trench 106 by oxidation. 
As shown in FIG. 1C, an insulation layer 110 that also completely fills the 
trench 106 is formed over the hard mask layer 104. The insulation layer 
110 can be an oxide layer formed, for example, by atmospheric pressure 
chemical vapor deposition (APCVD). The insulation layer 110 is next 
densified to form a structurally finer and denser layer. Note that actual 
thickness of the insulation layer 110 is largely determined by the actual 
depth of the trench 106 and thickness of other deposited layers. 
As shown in FIG. 1D, using the hard mask layer 104 as a stop layer, a 
chemical-mechanical polishing (CMP) or an etching back operation is 
carried out to remove a portion of the insulation layer 110. Hence, an 
insulation plug 110a is formed inside the trench 106. 
The hard mask layer 104 is removed to expose a portion of the insulation 
plug 110a and the pad oxide layer 102 as shown in FIG. 1. The hard mask 
layer 104 can be removed, for example, by wet etching. 
As shown in FIG. 1F, spacers 115 are formed on the sidewalls of the exposed 
insulation plug 110a. The spacers 115 are formed, for example, by forming 
a conformal oxide layer over the pad oxide layer 102 and the insulation 
plug 110a followed by an etching back step to remove most of the oxide 
material. Using the insulation plug 110a and the spacers 115 as a mask, an 
ion implantation is carried out to implant N.sub.2 ions into the active 
region of the substrate, resulting in a concentration of about 10.sup.14 
.about.10.sup.15 atoms/cm.sup.3 therein. 
As shown in FIG. 1G, the pad oxide layer 102 (FIG. 1F) is removed by, for 
example, a wet etching operation using a hydrofluoric (HF) acid solution. 
A portion of the spacer 115 (FIG. 1F) and a portion of the isolation plug 
110a are removed while removing the pad oxide layer 102 (FIG. 1F). 
As shown in FIG. 1H, a sacrificial oxide layer (not shown) is formed over 
the substrate 100, and then the sacrificial oxide layer is removed. An 
oxidation process is conducted to form a gate oxide layer 130 inside the 
active region. Since spacers 115 provided a barrier to N.sub.2 ions during 
ion implantation, there are fewer N.sub.2 ions around the edge of the 
insulation plug 110a. Since a higher concentration of N.sub.2 ions in the 
active region delays the formation of oxide in an oxidation process, the 
oxide layer 130 is thicker in the region around the insulation plug 110a. 
The thicker gate oxide around the edge region of the insulation plug 110a 
causes subsequently formed parasitic capacitors to have a low 
sub-threshold current leakage. The low sub-threshold current leakage is 
able to compensate for the low threshold voltage due to a locally 
intensified electric field. 
In summary, a thicker gate oxide around the edge region of the insulation 
plug results in a low sub-threshold current leakage in the subsequently 
formed parasitic capacitors. The low sub-threshold current leakage is able 
to compensate for the low threshold voltage due to a locally intensified 
electric field. 
It will be apparent to those skilled in the art that various modifications 
and variations can be made to the structure of the present invention 
without departing from the scope or spirit of the invention. In view of 
the foregoing, it is intended that the present invention cover 
modifications and variations of this invention provided they fall within 
the scope of the following claims and their equivalents.