Isolation trenches with conductive plates

Methods of forming isolation trenches, semiconductor devices, structures thereof, and methods of operating memory arrays are disclosed. In one embodiment, an isolation trench includes a recess disposed in a workpiece. A conductive material is disposed in a lower portion of the channel. An insulating material is disposed in an upper portion of the recess over the conductive material.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application relates to the following co-pending and commonly assigned U.S. patent application Ser. No. 11/701,198, filed on Feb. 1, 2007, entitled “Resistive Memory Including Buried Wordlines”; Ser. No. 12/033,519, filed on Feb. 19, 2008, entitled “Integrated Circuit Including U-Shaped Access Device”; and Ser. No. 12/033,533, filed on Feb. 19, 2008, entitled “Integrated Circuit Including U-Shaped Access Device”, which applications are hereby incorporated herein by reference.

TECHNICAL FIELD

The present invention relates generally to the fabrication of semiconductor devices, and more particularly to the fabrication of isolation regions.

BACKGROUND

Isolation regions are used in many semiconductor device applications to isolate adjacent active areas or devices from one another. Isolation regions are formed by patterning trenches or recesses in a substrate or workpiece, and filling the trenches with insulating materials. Some isolation regions comprise relatively high aspect ratio trenches formed in the substrate or workpiece, e.g., comprising an aspect ratio of up to 10:1, for example.

As features of semiconductor devices are decreased in size, as is the trend in the semiconductor industry, isolation regions may be insufficient to provide isolation for adjacent active areas or devices, for example. In memory devices, leakage current and parasitic effects may occur between adjacent devices, as examples.

Thus, what are needed in the art are improved methods of forming isolation regions of semiconductor devices and structures thereof.

SUMMARY OF THE INVENTION

These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention, which provide novel methods of forming isolation trenches. The isolation trenches include a conductive plate that is electrically coupled to the substrate or workpiece at the lower portion of the trenches.

In accordance with one embodiment of the present invention, an isolation trench includes a recess disposed in a workpiece. A conductive material is disposed in a lower portion of the recess. An insulating material is disposed in an upper portion of the recess over the conductive material.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

There is a trend in semiconductor technology to reduce the size of devices, to improve performance and reduce power requirements, as examples. The minimum feature size or critical dimension (CD) of semiconductor devices continues to become smaller and smaller. For example, advanced technology nodes are developing 60 nm, 45 nm, and 32 nm CDs, and the trend in reducing CD's is expected to continue towards the 20 nm or less range.

Some features of semiconductor devices may comprise the minimum feature size or CD of a technology node, such as isolation regions, bitlines, and wordlines of memory arrays, which may comprise a minimum size on one side and extend lengthwise on another side, e.g., in a top view.

In semiconductor devices having small geometries, the size effect for wiring lines in a memory array becomes more and more critical. In addition, the distance between adjacent p-n junctions becomes smaller with reduced ground rules, so that latchup effects may become critical in large memory arrays. Attempts to avoid the latchup effects have involved suppression of such effects using highly doped wells, e.g., by forming epitaxial grown substrates. Isolation trenches may comprise long trenches filled with an insulating material between active areas, and current may tend to flow between adjacent active areas as dimensions are decreased. The resistivity of conductive lines such as wordline and bitlines can be high, resulting in a substantial voltage drop across an array, e.g., from an edge of the array to a memory device inside the array.

What are needed in the art are improved methods of fabricating isolation regions of semiconductor devices and structures thereof.

Embodiments of the present invention achieve technical advantages by providing novel methods of forming isolation trenches of semiconductor devices. The isolation trenches include a conductive material in a lower portion of the trenches. The conductive material comprises buried conductive lines within the isolation trenches that provide low ohmic conductive plates in memory arrays, disposed beneath the memory arrays.

The present invention will be described with respect to preferred embodiments in specific contexts, namely implemented in PCRAM arrays. Embodiments of the invention may also be implemented in other semiconductor applications such as other types of memory devices, such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, flash memory devices, or other resistive memory devices such as magnetic random access memory (MRAM) devices or transition metal oxide (TMO) devices, for example. Embodiments of the present invention may also be implemented in logic devices, mixed signal devices, analog devices, or other semiconductor device applications, for example.

FIGS. 1 through 4show cross-sectional views of a semiconductor device100at various stages of manufacturing in accordance with a preferred embodiment of the present invention. To manufacture the semiconductor device100, first, a workpiece102is provided. The workpiece102may include a semiconductor substrate, body, or workpiece comprising silicon or other semiconductor materials and may be covered by an insulating layer, for example. The workpiece102may also include other active components or circuits, not shown. The workpiece102may comprise silicon oxide over single-crystal silicon, for example. The workpiece102may include other conductive layers or other semiconductor elements, e.g., transistors, diodes, etc. Compound semiconductors, GaAs, InP, Si/Ge, or SiC, as examples, may be used in place of silicon. The workpiece102may comprise a silicon-on-insulator (SOI) or a germanium-on-insulator (GOI) substrate, as examples.

A first doped region104and a second doped region106may be formed in the workpiece102, using several methods. The first doped region104may comprise a p type region and the second doped region106may comprise an n type region, or the first doped region104may comprise an n type region and the second doped region106may comprise a p type region, for example. The differently doped first and second doped regions104and106may be formed using implantation processes, epitaxial growth processes, diffusion processes, or any combinations thereof.

For example, a wafer or workpiece102of a first dopant type may be provided, and a top surface of the workpiece102may be counter-doped, e.g., with a second dopant type, forming a first doped region104. A second doped region106resides below the first doped region104, the second doped region106comprising the first dopant type of the workpiece102. Thus, the second doped region106is doped differently than the first doped region104.

Alternatively, a wafer or workpiece102comprising a first dopant type may be provided, and a second dopant type may be implanted beneath the top surface of the workpiece102, forming a second doped region106comprising a different dopant than the first doped region104residing beneath the first doped region104.

Or, in another embodiment, an undoped workpiece102may be provided, and two implantation processes may be used to form the first doped region104and the second doped region106. Alternatively, an undoped workpiece102may be provided, and the second doped region106and the first doped region104may be formed by two sequential epitaxial growth processes, as another example. Combinations of these methods may also be used to form the first doped region104, the second doped region106, and optional additional doped regions, as shown in the embodiments ofFIGS. 8 through 10at third doped region424and fourth doped region426, for example.

Referring again toFIG. 1, the first doped region104and the second doped region106comprise different types of dopants and include a junction at an intersection thereof. The first doped region104may be p type and the second doped region106may be n type, or the first doped region104may be n type and the second doped region106may be p type, for example. The doping concentrations of the second doped region106are relatively high in some embodiments, for example. The differently doped first and second doped regions104and106provide a vertical doping profile for the semiconductor device100. The first and second doped regions104and106may comprise at least a portion of an active area of the workpiece102, for example.

A plurality of recesses108or trenches are formed in the workpiece102in the first doped region104and the second doped region106, as shown inFIG. 2. The recesses108may be formed by depositing a hard mask (not shown) over the workpiece102and forming recesses108in the workpiece102and the hard mask using a lithography process. Alternatively, or additionally, the workpiece102may include a pad nitride disposed thereon that the recesses108are also formed in, not shown.

For example, the recesses108may be formed by depositing a photoresist, patterning the photoresist using a lithography mask and an exposure process, developing the photoresist, removing portions of the photoresist, and then using the photoresist and/or hard mask or pad nitride to protect portions of the workpiece102while other portions are etched away, forming the recesses108in the workpiece102. The etch process to form the recesses108may comprise a wet or dry etch process, and may comprise a reactive ion etch (RIE) process in some embodiments, for example. The photoresist and the optional hard mask or pad nitride may be removed, or the hard mask or pad nitride may be left remaining over the workpiece102after the etch process to form the recesses108.

The recesses108may comprise a depth within a top surface of the workpiece102of about 200 to 400 nm, and may comprise a width of the minimum feature size or CD of the semiconductor device100or greater, although alternatively, the recesses108may comprise other dimensions. The recesses108may comprise a length, e.g., in and out of the paper, of several hundred nanometers to several μm or greater, as an example, although alternatively, the recesses108may comprise other dimensions. The length of the recesses108in and out of the paper may vary depending on the size of the array, e.g., 128×128 cells, up to over 2,000×2,000 cells, as examples. Alternatively, the recesses108may comprise other dimensions depending on the particular application and the technology node used for the manufacturing of the semiconductor device100, for example.

The recesses108comprise voids or trenches formed in a top portion of the workpiece102, e.g., in the first doped region104and the second doped region106of the workpiece102, wherein isolation regions or isolation trenches will be formed in accordance with embodiments of the present invention, to be described further herein. Only three recesses108are shown inFIGS. 2 through 5; however, there may be a plurality of recesses108for isolation trenches formed across a surface of a workpiece102in accordance with embodiments of the present invention, for example, not shown. There may be hundreds or thousands of recesses108formed in a single memory array, depending on the size of the array, for example.

The recesses108comprise regions where isolation trenches will be formed in accordance with embodiments of the present invention. The recesses108are filled with a conductive material110/112in a lower portion of the recesses108, as shown inFIGS. 3 and 4, and an upper portion of the recesses108is filled with an insulating material116as shown inFIG. 4, to be described further herein.

After forming the recesses108in the workpiece102, an optional conductive liner110may be formed over the workpiece102, lining the top surface of the workpiece, and sidewalls and bottom surfaces of the recesses108, as shown inFIG. 3. The conductive liner110may comprise a metal in some embodiments that improves adhesion of a subsequently deposited conductive fill material112to the surface of the workpiece in the recesses108, for example. Alternatively, the conductive liner110may comprise a conductive material that functions as a conductive plate214, as shown inFIG. 6at210, to be described further herein.

The conductive liner110may be deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD), substantially conformally coating the exposed surfaces of the workpiece102, as shown inFIG. 3. Alternatively, the conductive liner110may be formed using a sputter process or physical vapor deposition (PVD), which may result in only the bottom surfaces of the recesses108being coated with the conductive liner, as shown inFIG. 7at310, also to be described further herein.

The conductive liner110may comprise a thickness of about 2 to 5 nm, for example, although alternatively, the conductive liner110may comprise other dimensions. The conductive liner110may be thicker, e.g., comprising a thickness of about 5 to 50 nm in other embodiments, if a conductive fill material is not used.

The conductive liner110may comprise a metal in some embodiments. The conductive liner110may comprise W, WN, WSi, Ti, TiN, Ta, TaN, other metals, combinations thereof, or multiple layers or liners thereof, as examples, although alternatively, the conductive liner110may comprise other materials.

A conductive fill material112is deposited over the workpiece102, e.g., over the conductive liner110, if present, as shown inFIG. 3. The conductive fill material112may extend over a top surface of the workpiece102as deposited, as shown. The conductive fill material112may be deposited using CVD or PVD, although other deposition methods may also be used to form the conductive fill material112. The conductive fill material112may comprise W, WN, WSi, Ti, TiN, Ta, TaN, Ru, Pt, Ir, carbon, polysilicon, doped polysilicon, other semiconductive materials, a silicided semiconducting material such as TiSi, NiSi, CoSi, combinations thereof, or multiple layers or liners thereof, as examples, although alternatively, other materials may also be used for the conductive fill material112.

In some embodiments, the conductive fill material112comprises a metal. In other embodiments, the conductive fill material112comprises a semiconductive material such as silicon. In embodiments wherein the conductive fill material112comprises a semiconductive material, the semiconductive material may be doped or silicided to form a material that has a lower resistivity to the surrounding bulk silicon of the workpiece102, for example. The conductive fill material112may comprise a semiconductive material doped or silicided to form a low ohmic polysilicon material that forms a barrier to the surrounding bulk silicon of the workpiece102in some embodiments, for example.

The conductive fill material112is optional if the conductive liner110is used, e.g., in the embodiment shown inFIG. 6, a conductive fill material112is not included.

The conductive liner110and the conductive fill material112comprise conductive materials that comprise a lower resistance than the workpiece102in the lower portion of the recesses108. For example, the conductive liner110and the conductive fill material112may comprise materials that comprise a lower ohmic material than the second doped region106of the workpiece102, which may be heavily doped.

The conductive material110/112is removed from the upper portion of the recesses108, as shown inFIG. 4. The conductive material110/112may be removed using a chemical mechanical polish process and/or a RIE process, as examples, although alternatively, other etching methods may be used to etch away the conductive material110/112from the upper portion of the recesses108in the workpiece102. The conductive material110/112left remaining in the lower portion of the recesses108may comprise a thickness of about 10 to 50 nm in some embodiments, for example, although alternatively, the conductive material110/112in the lower portion of the recesses108may comprise other dimensions. The depth of the recesses108may be increased to accommodate for the presence of the conductive material110/112in the recesses108, for example.

The conductive material110/112comprises a conductive plate114that is coupled to and makes electrical contact to the second doped region106of the workpiece102. The conductive plate114is electrically coupled to the second doped region106in the lower portion of the workpiece102. The conductive plate114comprising the conductive material110/112may be coupled to a return voltage terminal to assist in the functioning of the semiconductor device100, to be described further herein. The conductive plate114has a lower resistance than a portion of the workpiece102proximate the lower portion of the recesses108, e.g., a lower resistance than the second doped region106of the workpiece102, in some embodiments.

An insulating material116is deposited over the workpiece102, filling in the upper portion of the recesses108, as shown inFIG. 4. The insulating material116may overfill the recesses108as deposited, and a CMP process may be used to planarize the workpiece102and remove a portion of the insulating material116from over the top surface of the workpiece102, or from over the top surface of a pad nitride or hard mask, if present, for example. The insulating material116may comprise a dielectric material such as an oxide material, a nitride material, a low dielectric constant (k) dielectric material having a dielectric constant of less than 3.9, Al2O3, or multiple layers or combinations thereof, as examples, although alternatively, the insulating material116may comprise other materials.

The insulating material116and the conductive plate114comprising the conductive material110/112in the recesses108comprise isolation trenches120, as shown inFIG. 4. The isolation trenches120isolate active areas of the workpiece102between the isolation trenches120from one another, for example. The isolation trenches120are also referred to herein as isolation regions. The isolation regions120may comprise shallow trench isolation (STI) regions, deep trench (DT) isolation regions, field oxide isolation regions, or other insulating regions, as examples.

The active areas of the workpiece102that the isolation trenches120provide isolation for may comprise the first doped regions104and the second doped regions106of the workpiece102in some embodiments, for example. The active areas may also comprise additional doped regions and may comprise other types of regions formed in the workpiece102, for example. The active areas may comprise diodes or transistors in some embodiments, to be described further herein.

FIG. 5shows a top view of a portion of the isolation trenches120comprising the conductive plates114shown inFIG. 4in the view at5-5. The conductive material110/112comprising the conductive plates114of the isolation regions120between each active area in the workpiece102(e.g., between the second doped regions106of the workpiece102) may be coupled together by conductive lines118formed in the same material layer of the workpiece102that the conductive material110/112is formed in. The conductive plates114comprise a lines and spaces pattern in the top view of the workpiece102, for example.

All of the conductive plates114may be coupled together in a single memory array in some embodiments, as shown inFIG. 5. In other embodiments, only some of the conductive plates may be coupled together, for example. The conductive plates114are directly connected to silicon of the workpiece102, e.g., to the second doped region106in the embodiment shown inFIGS. 1 through 5. The second doped region106may comprise highly doped n or p type crystalline silicon in some embodiments, for example.

The conductive plates114comprising the conductive material110/112may be coupled to a voltage return terminal, e.g., using a contact or via122disposed over one of the conductive lines118or one of the conductive plates114. The voltage return terminal may comprise a ground terminal or a negative voltage terminal, as examples, although alternatively, the voltage return terminal may comprise other signals or supply voltages. In some embodiments all of the conductive plates114are connected to the same voltage, e.g., ground or a negative voltage.

FIG. 6shows an embodiment of the present invention wherein the conductive plates214of the isolation trenches220comprise a liner210of a conductive material. Like numerals are used for the various elements that were described inFIGS. 1 through 5. To avoid repetition, each reference number shown inFIG. 6is not described again in detail herein. Rather, similar materials x02, x04, x06, etc . . . are preferably used to describe the various material layers shown as were used to describeFIGS. 1 through 5, where x=1 inFIGS. 1 through 5and x=2 inFIG. 6. As an example, the materials and dimensions described for the conductive liner110in the description forFIGS. 1 through 5may also be used for the conductive liner210shown inFIG. 6.

In the embodiment shown inFIG. 6, the conductive plates214in the lower portion of the recesses or trenches do not include a conductive fill material; rather, the conductive plates214comprise only a conductive liner210. The conductive liner210may comprise one or more layers of conductive material. Rather than having a rectangular shape in a cross-sectional view as in the first embodiment shown inFIGS. 1 through 5, the conductive plates214comprise a U-shape, conforming to the shape of the lower portion of the recesses in the workpiece202. The insulating material216fills in the interior portion of the U-shaped conductive plates214, as shown. The conductive liner210may be thicker in this embodiment, as required to achieve the resistance needed for the conductive plates214, for example. A deposition step for depositing a conductive fill material is advantageously avoided in this embodiment, for example.

After the formation of the conductive liner210, the conductive liner210is removed from the upper portion of the recesses using an etch process. The insulating material216is then formed over the liner210in the lower portion of the recesses208and over the sidewalls of the recesses in the upper portion of the recesses, as shown.

FIG. 7shows an embodiment of the present invention wherein a conductive liner310is formed only on a bottom surface of the isolation trenches320. Again, like numerals are used for the element numbers shown in the previous figures, and to avoid repetition, each element number is not described again herein.

In the embodiments shown inFIGS. 1 through 6, the conductive liner110and210is disposed on a bottom surface and sidewalls of the recesses108in the lower portion of the recesses108. However, in the embodiment shown inFIG. 7, the conductive liner310is disposed only on a bottom surface of the recess of the isolation trenches320. The conductive liner310may be formed using a sputter or PVD process in this embodiment, for example. The sputter process or PVD process may result in the formation of the conductive liner310only on the bottom surface and not on the sidewall of the recesses in the workpiece302, for example. The conductive fill material312is formed over the conductive liner310, and the conductive plates314comprise the conductive fill material312and the conductive liner310over the bottom of the recesses in this embodiment, as shown.

Embodiments of the present invention are particularly advantageously when implemented in memory arrays comprising resistive elements comprising a phase change material, for example. Embodiments of the present invention may also be implemented in other types of memory arrays, or in arrays of other types of devices other than memory devices, as examples.

FIGS. 8 through 12illustrate exemplary memory arrays in which the novel isolation trenches120,220, and320comprising conductive plates114,214, and314in a lower portion thereof may be implemented. Again, like numerals are used for the element numbers shown in the previous figures, and to avoid repetition, each element number is not described again herein. Referring next toFIG. 8, a perspective view of an embodiment of the present invention is shown implemented in a memory array comprising a phase change random access memory (PCRAM) including U-shaped bipolar transistors.FIG. 9shows a cross-sectional view of a portion of the memory array shown inFIG. 8, andFIG. 10shows a cross-sectional view of a portion of the memory array shown inFIGS. 8 and 9rotated by ninety degrees.

The novel isolation trenches420comprising conductive plates414of embodiments of the present invention are illustrated inFIGS. 8 through 10implemented in a memory array of a type described in U.S. patent application Ser. No. 12/033,519, filed on Feb. 19, 2008, entitled “Integrated Circuit Including U-Shaped Access Device”; and Ser. No. 12/033,533, filed on Feb. 19, 2008, entitled “Integrated Circuit Including U-Shaped Access Device”, which applications are hereby incorporated herein by reference. The memory array includes cross-point memory cells that each includes a transistor438and a storage device432. The transistors438comprise U-shaped vertical bipolar select devices that include a base442and an emitter440. The memory cells include a storage device432comprising a resistive memory element coupled to the emitter440of the transistors438. A metallized wordline428is electrically coupled to the base442of the transistors438through conductive material436and a fourth doped region426. The transistors438may comprise a vertical U-shaped p-n-p bipolar transistors, for example. Alternatively, the transistors438may comprise vertical U-shaped n-p-n bipolar transistors, for example, not shown.

The semiconductor device400comprises a plurality of isolation trenches420comprising a plurality of conductive plates414that extend beneath the memory array, as previously described with reference to the embodiments shown inFIGS. 1 through 7herein. The workpiece402in this embodiment includes a plurality of doped regions404,406,424, and426. For example, in the example shown, first doped region404comprises a p type region, second doped region406comprises an n− type region disposed beneath the first doped region404, and third doped region424comprises a p type region disposed beneath the second doped region406. A fourth doped region426is spaced apart from the first doped region404by an insulating material446which may comprise the same insulating material416of the isolation trenches420of embodiments of the present invention. The fourth doped region426may comprise an n+ type region, as shown.

A plurality of wordlines428and bitlines430positioned at substantially orthogonal directions to one another are disposed over the workpiece402. A plurality of storage devices432comprising resistive elements are disposed between the wordlines428and bitlines430, e.g., proximate active areas of the workpiece402. The storage devices432utilize the resistance value of the resistive elements to store one or more bits of data. For example, a resistive element programmed to have a high resistance value may represent a logic “1” data bit value and a memory element programmed to have a low resistance value may represent a logic “0” data bit value.

The storage devices432may comprise resistive elements such as phase change elements (PCE's) comprising a material such as Ge—Sb—Te (GST), as an example, although other phase-changing materials and other types of resistive elements may also be used for the storage elements432. The storage devices432may comprise PCE's comprising a phase change material including one or more of the elements Ge, Sb, Te, Ga, As, In, Se, Bi, and S, as examples, although other materials may also be used for the storage devices432. Storage devices432comprising PCE's may include a phase change material that exhibits at least two different states. The states of the phase change material may comprise an amorphous state and a crystalline state, where the amorphous state involves a more disordered atomic structure and the crystalline state involves a more ordered lattice. The amorphous state usually exhibits higher resistivity than the crystalline state, for example.

The storage devices432are addressable for programming, sensing, or reading the programmed states using the wordlines428, bitlines430, and the active areas of the workpiece402comprising the first doped region404, the second doped region406, the third doped region424, and the fourth doped region426of the workpiece402.

The bitlines430are disposed over the storage elements432, which are coupled to the first doped regions404of the workpiece402by contacts434comprising a conductive material. The wordlines428are disposed beneath the bitlines430and are coupled to the fourth doped regions426of the workpiece402by conductive features436. The device may comprise a 4F2cross-point cell, e.g., comprising an area of about 4 times the minimum feature size F×F of the semiconductor device400(e.g., see the labeled dimension “2F” in the perspective and cross-sectional views inFIGS. 8 and 9).

The conductive plates414are disposed in a plate level beneath a top surface of the workpiece402. The wordlines428are formed in a conductive line level, e.g., a wordline level, over the top surface of the workpiece402. The bitlines430are formed in a conductive line level, e.g., a bitline level, over the wordline level.

The insulating materials416,446, and448disposed between the various elements are not shown in the perspective view inFIG. 8, but are shown in the cross-sectional view inFIGS. 9 and 10. Insulating material446and448may comprise similar materials as described for the insulating material416of the novel isolation trenches420described herein, for example.

The first doped region404, the second doped region406, and the third doped region424of the workpiece402comprise a vertical doping profile that functions as a bipolar transistor, e.g., a bipolar junction transistor (BJT). For example, a schematic of a bipolar transistor is superimposed over a portion of the workpiece402at438inFIG. 8. The first doped region404, the second doped region406, the third doped region424, and the fourth doped region426of the workpiece402together function as a U-shaped bipolar transistor, for example.

One side of storage devices432is electrically coupled to a bitline430, and the other side of the storage devices432is electrically coupled to the emitter of the transistor438, e.g., by contacts434. The collectors of the transistors438are electrically coupled to common or ground. The bases of the transistors438are electrically coupled to a wordline428.

The third doped region424of the workpiece402is electrically coupled to the conductive plates414. The conductive plates414of embodiments of the present invention may be coupled to a return voltage terminal, such as ground, as shown inFIG. 8. When a storage device432comprising a memory device is selected, a current i is applied from a bitline430through the PCE432to the first doped region404which functions as an emitter of the bipolar transistors438. A portion i2of the current i flows through the second doped region406to the third doped region424which functions as a collector of the bipolar transistors438, which is coupled to ground by the conductive plate414of an isolation region420of embodiments of the present invention. A portion i1of the current i also flows from the second doped region406which functions as a base of the bipolar transistors438to the wordline428.

Thus, a memory array may be operated in accordance with embodiments of the present invention by connecting the conductive plates414comprising the conductive material (e.g., material110/112,210, or310/312) in the lower portion of the recesses of the isolation trenches420to a voltage return terminal, and accessing at least one of the memory devices comprising the storage devices432in the memory array. Accessing the memory devices may comprise reading from, writing to, or sensing the memory devices comprising the storage devices432that are coupled to the active areas, e.g., the bipolar transistor438formed in the workpiece402in the doped regions404,406,424, and426, for example.

The conductive plates414of the isolation trenches420may be coupled to a voltage return terminal comprising a ground terminal, to a negative voltage terminal, e.g., comprising about −1 volt or other negative voltage levels, or other voltage terminals comprising other voltage levels, as examples. The conductive plates414in the array may be coupled together at the edges of the array, as shown in the top view inFIG. 5, for example. The conductive plates414in the isolation trenches420of the array may be coupled to the same voltage, e.g., ground or a negative voltage in some embodiments. The conductive plates414of the isolation trenches420may be coupled to the same voltage return terminal comprising a ground terminal or negative voltage terminal that the collector or third doped region424is coupled to, advantageously providing a lower ohmic path for the current i2, for example. The conductive material of the conductive plates414at the lower portion of the isolation trenches420provides a lower p-well resistance, e.g., for the third doped region424.

The memory array shown inFIGS. 8 through 10may include a controller, not shown, wherein the controller comprises a microprocessor, microcontroller, or other suitable logic circuitry for controlling the operation of memory array. The memory array may also include a write circuit and a sense circuit, also not shown. The controller is adapted to control read and write operations of memory array including the application of control and data signals to the memory array using the write circuit and the sense circuit, for example.

To write to and read the storage devices432in the memory array, several methods may be used. The write circuit may be adapted to provide voltage pulses through a signal path (not shown) and the bitlines430to memory cells, e.g., the storage devices432, of the memory array to program the memory cells. Alternatively, the write circuit may be adapted to provide current pulses through a signal path and bit lines430to storage devices432in the memory array to program the storage devices432. The sense circuit is adapted to read each of the two or more states of the storage devices432through the bitlines430and the signal path. The sense circuit may provide current that flows through a storage device, and the sense circuit may be adapted to read the voltage across that one of the storage devices432. Alternatively, the sense circuit may provide a voltage across one of the storage devices432, and the sense circuit may be adapted to read the current that flows through that one of the storage devices432, for example. In other embodiments, the write circuit may be adapted to provide a voltage across or a current through one of the storage devices432, and the sense circuit may be adapted to read the current that flows through or read the voltage across that one of the storage devices, for example. The sense circuit may also be used to determine or sense the resistance of the storage devices, as another example.

FIG. 11shows an embodiment of the present invention implemented in a memory array including a PCRAM device including vertical select devices comprising transistors and having buried wordlines528aand528b. The novel isolation trenches comprising conductive plates514of embodiments of the present invention are illustrated inFIG. 11implemented in a memory array of a type described in U.S. patent application Ser. No. 11/701,198, filed on Feb. 1, 2007, entitled “Resistive Memory Including Buried Wordlines”, which application is incorporated herein by reference.

The select devices may comprise transistors550comprising spacer gate field effect transistors FET's550that may comprise a vertical n-p-n bipolar transistors, for example. Alternatively, the spacer FET's550may comprise vertical p-n-p bipolar transistors, for example, not shown. The memory array may comprise a FET array with double gates and double buried wordlines528aand528b.

The storage elements532comprising PCE's are disposed between the bitlines530and the first doped regions504of the workpiece502. The wordlines528aand528bcomprise buried metal spacer wordlines that are separated by an oxide material or insulating material in regions552from the second doped regions506that function as channel regions of the transistor550. The wordlines528aand528bfunction as gates of the FETs550. A buried metal wordline528aand528bmay be disposed on both sides of the second doped regions506in the array, as shown; thus, the transistors550comprise double gate transistors. The first doped regions504, the second doped regions506, and the third doped region524comprise active areas of the workpiece502that function as spacer FETs550and provide accessibility to the storage elements532, addressable using the wordlines528aand528band bitlines530, in this embodiment.

FIG. 12shows an embodiment of the present invention implemented in a memory array including a PCRAM device including vertical bipolar select devices comprising diodes and having buried wordlines. The novel isolation trenches comprising conductive plates614of embodiments of the present invention are illustrated inFIG. 12implemented in a memory array of a type also described in U.S. patent application Ser. No. 11/701,198, filed on Feb. 1, 2007, entitled “Resistive Memory Including Buried Wordlines”, for example. The first doped region604and the second doped region606comprise active areas of the workpiece602that function as diodes and may be used to access the storage elements632using the buried wordlines628aand628band the bitlines630. A buried wordline628aand628bmay be disposed on both sides of the second doped regions606in the array, as shown. In this embodiment, the buried wordlines628aand628bmay be directly coupled to or connected to the second doped regions606, for example. The storage elements632are disposed between the bitlines630and the first doped regions604of the workpiece602.

Without the presence of the conductive plates614of the isolation trenches620in accordance with embodiments of the present invention, parasitic effects654may impact the closely-spaced active areas of the workpiece602, e.g., the first doped regions604, the second doped regions606, and the third doped regions624. Advantageously, the presence of the conductive plates614of the isolation trenches that are coupled to a voltage return terminal such as ground cause the parasitic effects which may comprise a current, indicated at656inFIG. 12, to flow to ground or another voltage return level rather than to impact an adjacent active area. Thus, the novel conductive plates614in the isolation trenches620suppress undesirable parasitic bipolar effects in the diode memory array shown inFIG. 12.

In the embodiments shown in the perspective views inFIGS. 11 and 12, the insulating materials are omitted so the conductive features and storage elements of the memory arrays may be more clearly seen. Insulating materials are included to separate the various features and elements, similar to the cross-sectional views shown inFIGS. 9 and 10, for example.

The memory arrays shown inFIGS. 11 and 12may function and may be operated, e.g., read, written to, or sensed similar to the description for the embodiments shown inFIGS. 8 through 10, for example.

After the manufacturing processes described herein for the semiconductor devices100,200,300,400,500, and600, the manufacturing process for the semiconductor devices100,200,300,400,500, and600is then continued to complete the fabrication of the devices100,200,300,400,500, and600. Insulating and encapsulating materials may be formed over the semiconductor devices100,200,300,400,500, and600. Metallization layers (not shown) comprising one or more conductive line and via layers may be formed over the workpieces102,202,302,402,502, and602to interconnect the various components of the semiconductor devices100,200,300,400,500, and600. Contacts may be formed on the top surface over the insulating and metallization layers, for example, also not shown.

Embodiments of the present invention may be implemented in applications where memory devices are used, e.g., in memory arrays, as described herein and shown inFIGS. 8 through 12. The storage devices432,532, and632may comprise resistive elements such as PCEs, MRAM stacks, or TMO elements. Alternatively, the storage devices432,532, and632may comprise other types of memory devices, such as DRAMs, SRAMs, or flash memories, although other types of memory devices many also be used. The novel isolation trenches120,220,320,420,520, and620comprising conductive plates114,214,314,414,514, and614may also be implemented in other types of semiconductor device arrays.

The novel isolation trenches120,220,320,420,520, and620comprising conductive plates114,214,314,414,514, and614are particularly beneficial in memory arrays wherein a low ohmic well connection at the bottom of the isolation trenches120,220,320,420,520, and620is needed, for example. The isolation trenches120,220,320,420,520, and620comprising conductive plates114,214,314,414,514, and614described herein are also particularly beneficial in memory arrays comprising very small ground rules or CDs.

Embodiments of the present invention include methods of forming isolation trenches120,220,320,420,520, and620and methods of fabricating the semiconductor devices100,200,300,400,500, and600including the isolation trenches120,220,320,420,520, and620described herein, for example. Embodiments of the present invention also include semiconductor devices100,200,300,400,500, and600and isolation trenches120,220,320,420,520, and620manufactured using the methods described herein. Embodiments of the present invention also include methods of operating memory arrays including the novel isolation trenches120,220,320,420,520, and620including the conductive plates114,214,314,414,514, and614.

Advantages of embodiments of the present invention include providing novel structures and methods for forming isolation trenches120,220,320,420,520, and620of semiconductor devices100,200,300,400,500, and600. The novel isolation trenches120,220,320,420,520, and620include a conductive material in a lower portion of the recesses, which comprise buried conductive plates114,214,314,414,514, and614or conductive lines that function as low ohmic conductive plates114,214,314,414,514, and614in semiconductor devices100,200,300,400,500, and600such as memory arrays.

In some memory arrays, the amount of programming current required to program the storage devices432,532, and532may be relatively large, e.g., comprising several microamperes in some applications. The voltage drop from an edge of the array to the memory cells or storage devices432,532, and632may comprise several millivolts, for example. Embodiments of the present invention advantageously lower the voltage drop, e.g., by lowering the resistance by causing a portion of the programming current to pass through the novel conductive plates114,214,314,414,514, and614of the novel isolation trenches120,220,320,420,520, and620described herein.

As an example, a resistance of a wordline or bitline to a storage device432,532, or632to an edge of an array may comprise about 1 kΩ, and the conductive plates114,214,314,414,514, and614may lower the resistance to about 100Ω. If the programming current is about 100 microamperes to switch a resistive element432,532, or632from one state to another, the voltage drop may be reduced using embodiments of the present invention from about 0.100 Volts to about 0.010 Volts, reducing the voltage drop across the memory array by a factor of about 10×.

Thus, power requirements for the memory array are reduced, and battery life, e.g., of batteries used to power the memory arrays, may be increased, in some applications. Alternatively, the memory array may be made larger and may be increased in size to include a larger number of storage cells432,532, or632, for example.

Embodiments of the present invention are easily implementable in existing manufacturing process flows, with a small or reduced number of additional processing steps being required, for example. Embodiments of the present invention are particularly beneficial in technology nodes having very small minimum feature sizes, such as about 45 nm and below, for example. Alternatively, embodiments of the present invention may also be implemented in applications having ground rules larger than about 45 nm.

Other advantages of embodiments of the present invention include enabling chip size increase due to low ohmic wiring options in an array. The conductive plates in the isolation trenches suppress or prevent latch-up and other cross-talk effects. Embodiments of the present invention improve reliability of semiconductor devices, as a conductive plate instead of a wordline or bitline in an array carries away some of the array current, e.g., in the use of a bipolar transistor or a FET with a metal or conductive plate in a memory device, or with a diode array, as shown inFIG. 12.

The conductive plates114,214,314,414,514, and614of the isolation trenches120,220,320,420,520, and620comprise low ohmic plate connections disposed beneath or under a memory array. The array may comprise crystalline silicon (e.g., the workpiece102may comprise crystalline silicon) without requiring an epitaxial growth of semiconductive material above the conductive plates114,214,314,414,514, and614. For example, in the embodiment shown inFIGS. 8 through 10, the conductive plates414suppress parasitic bipolar effects between storage devices432or memory cells.