Semiconductor device

According to one embodiment, a semiconductor device includes a semiconductor substrate and a first semiconductor element provided on the semiconductor substrate. The first semiconductor element includes: a first semiconductor; a second semiconductor layer; a third semiconductor layer; a first insulating layer; a first base region; a first source region; a first gate electrode; a first drift layer; a first drain region; a first source; and a first drain electrode. A concentration of an impurity element of the first conductivity type included in the first drift layer is lower than a concentration of an impurity element of the first conductivity type included in the first semiconductor layer. The concentration of the impurity element of the first conductivity type included in the first drift layer is higher than a concentration of an impurity element of the first conductivity type included in the second semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2011-207280, filed on Sep. 22, 2011; the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

A lateral DMOS (Double Diffused Metal Oxide Semiconductor) field effect transistor is one example of a power MOS (Metal Oxide Semiconductor) field effect transistor. Generally, in a DMOS field effect transistor, measures are taken to increase the breakdown voltage of the element by increasing the length (the drift length) of the drift region.

However, in the case where measures are taken to increase the drift length as recited above to increase the breakdown voltage of the element, the element surface area of the lateral DMOS field effect transistor undesirably increases.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor device includes a semiconductor substrate and a first semiconductor element provided on the semiconductor substrate. The first semiconductor element includes: a first semiconductor layer of a first conductivity type provided on the semiconductor substrate; a second semiconductor layer of the first conductivity type provided on the first semiconductor layer; a third semiconductor layer of the first conductivity type provided on the first semiconductor layer to be adjacent to the second semiconductor layer; a first insulating layer provided from a surface of the second semiconductor layer into an interior of the second semiconductor layer and from a surface of the third semiconductor layer into an interior of the third semiconductor layer; a first base region of a second conductivity type selectively provided on the surface of the second semiconductor layer; a first source region of the first conductivity type selectively provided on a surface of the first base region; a first gate electrode provided from a surface of the first insulating layer into an interior of the first insulating layer, the first gate electrode being adjacent to the first base region with the first insulating layer interposed; a first drift layer of the first conductivity type provided inside the second semiconductor layer under the first base region to extend from a surface of the first semiconductor layer toward the first base region side; a first drain region of the first conductivity type provided on the surface of the third semiconductor layer to oppose the first source region with the first insulating layer interposed; a first source electrode electrically connected to the first source region; and a first drain electrode electrically connected to the first drain region. A concentration of an impurity element of the first conductivity type included in the first drift layer is lower than a concentration of an impurity element of the first conductivity type included in the first semiconductor layer. The concentration of the impurity element of the first conductivity type included in the first drift layer is higher than a concentration of an impurity element of the first conductivity type included in the second semiconductor layer.

An embodiment will now be described with reference to the drawings. In the description recited below, similar members are marked with like reference numerals, and a description of a member once described is omitted as appropriate.

FIG. 1is a schematic plan view of the semiconductor device according to the embodiment.

FIGS. 2A and 2Bare schematic cross-sectional views of the semiconductor device according to the embodiment.

FIG. 2Aillustrates a cross section ofFIG. 1at the position along line A-B; andFIG. 2Billustrates a cross section ofFIG. 1at the position along line C-D.

As illustrated inFIG. 1, the semiconductor device1includes semiconductor elements (first semiconductor elements)100A and semiconductor elements (second semiconductor elements)100B. The semiconductor elements100A and the semiconductor elements100B are provided in cell units (the portions enclosed with the rectangular broken lines). In the semiconductor device1, the semiconductor elements100A are periodically arranged lengthwise and crosswise in the drawings; and the semiconductor elements100B are arranged periodically lengthwise and crosswise in the drawings. The breakdown voltage of the semiconductor element100A is different from the breakdown voltage of the semiconductor element100B. In other words, the semiconductor device1includes two types of semiconductor elements that have different breakdown voltages.

For example, the breakdown voltage of the semiconductor element100B is higher than the breakdown voltage of the semiconductor element100A. The region where the semiconductor elements100A are disposed is taken as a low breakdown voltage element region100L; and the region where the semiconductor elements100B are disposed is taken as a high breakdown voltage element region100H.

First, the cross-sectional structure of the semiconductor element100A will be described.

The semiconductor element100A illustrated inFIG. 2Ais a lateral DMOS field effect transistor and has a trench gate structure.

In the semiconductor element100A, an n+-type first semiconductor layer12A is provided on a p-type semiconductor substrate10. An n−-type second semiconductor layer14A is provided on the first semiconductor layer12A. An n+-type third semiconductor layer16A is provided on the first semiconductor layer12A to be adjacent to the second semiconductor layer14A. A first insulating layer20A is provided from the surface of the second semiconductor layer14A into the interior of the second semiconductor layer14A and from the surface of the third semiconductor layer16A into the interior of the third semiconductor layer16A.

In the semiconductor element100A, a p-type first base region30A is selectively provided on the surface of the second semiconductor layer14A. An n+-type first source region32A is selectively provided on the surface of the first base region30A. A first gate electrode40A is provided from the surface of the first insulating layer20A into the interior of the first insulating layer20A. The first gate electrode40A is adjacent to the first base region30A with the first insulating layer20A interposed.

The first insulating layer20A which is provided between the first gate electrode40A and the first base region30A functions as a gate insulating film. The thickness of the first insulating layer20A provided between the first gate electrode40A and the second semiconductor layer14A and the thickness of the first insulating layer20A provided between the first gate electrode40A and the third semiconductor layer16A are thicker than the thickness of the first insulating layer20A provided between the first gate electrode40A and the first base region30A. Thereby, the semiconductor element100A has a high breakdown voltage due to the existence of the first insulating layer20A even in the case where a strong electric field is applied between the first gate electrode40A and a first drain region34A described below.

In the semiconductor element100A, an n-type first drift layer18A is provided inside the second semiconductor layer14A under the first base region30A. The first drift layer18A extends from the surface of the first semiconductor layer12A toward the first base region30A side. The n+-type first drain region34A is provided on the surface of the third semiconductor layer16A. The first drain region34A opposes the first source region32A with the first insulating layer20A interposed. A first back gate region36A is provided on the surface of the first base region30A to be adjacent to the first source region32A. The back gate region36A functions as a carrier release region.

A first inter-layer insulating film50A is provided on the first back gate region36A, on the first source region32A, on the first insulating layer20A, on the first gate electrode40A, and on the first drain region34A.

In the semiconductor element100A, a first source electrode52A is electrically connected to the first source region32A and the first back gate region36A via a first source contact51A. A first drain electrode54A is electrically connected to the first drain region34A via a first drain contact53A.

The concentration of the n-type impurity element included in the first drift layer18A is lower than the concentration of the n-type impurity element included in the first semiconductor layer12A. The concentration of the n-type impurity element included in the first drift layer18A is higher than the concentration of the n-type impurity element included in the second semiconductor layer14A.

For example, the right side ofFIG. 2Aillustrates the n-type impurity element concentration profile at positions along line90A. The vertical axis of the impurity element concentration profile is the depth; and the horizontal axis is the impurity concentration.

For example, the concentration of the impurity element of the second semiconductor layer14A is substantially constant in the depth direction (the Z-axis direction). In the first drift layer18A, the concentration of the impurity element increases once toward the first semiconductor layer12A. Then, the concentration of the impurity element conversely decreases toward the first semiconductor layer12A side. In other words, the impurity element concentration profile of the first drift layer18A has a peak P. The concentration of the impurity element of the first semiconductor layer12A is higher than the concentrations of the impurity elements of the second semiconductor layer14A and the first drift layer18A.

In other words, the peak value of the n-type impurity element concentration profile included in the first drift layer18A is lower than the concentration of the n-type impurity element included in the first semiconductor layer12A. The peak value of the n-type impurity element concentration profile included in the first drift layer18A is higher than the concentration of the n-type impurity element included in the second semiconductor layer14A.

It is unnecessary for the peak P of the impurity element concentration profile of the first drift layer18A to be one peak. The peak P may be multiple. In such a case as well, one peak value of the multiple peaks P is lower than the concentration of the n-type impurity element included in the first semiconductor layer12A and higher than the concentration of the n-type impurity element included in the second semiconductor layer14A.

The cross-sectional structure of the semiconductor element100B will now be described.

The semiconductor element100B illustrated inFIG. 2Bis a lateral DMOS field effect transistor and has a trench gate structure.

In the semiconductor element100B, an n+-type fourth semiconductor layer12B is provided on the semiconductor substrate10. An n−-type fifth semiconductor layer14B is provided on the fourth semiconductor layer12B. An n+-type sixth semiconductor layer16B is provided on the fourth semiconductor layer12B to be adjacent to the fifth semiconductor layer14B. A second insulating layer20B is provided from the surface of the fifth semiconductor layer14B into the interior of the fifth semiconductor layer14B and from the surface of the sixth semiconductor layer16B into the interior of the sixth semiconductor layer16B.

In the semiconductor element100B, a p-type second base region30B is selectively provided on the surface of the fifth semiconductor layer14B. An n+-type second source region32B is selectively provided on the surface of the second base region30B. A second gate electrode40B is provided from the surface of the second insulating layer20B into the interior of the second insulating layer20B. The second gate electrode40B is adjacent to the second base region30B with the second insulating layer20B interposed.

The second insulating layer20B provided between the second gate electrode40B and the second base region30B functions as a gate insulating film. The thickness of the second insulating layer20B provided between the second gate electrode40B and the fifth semiconductor layer14B and the thickness of the second insulating layer20B provided between the second gate electrode40B and the sixth semiconductor layer16B are thicker than the thickness of the second insulating layer20B provided between the second gate electrode40B and the second base region30B.

In the semiconductor element1008, an n-type second drift layer18B is provided under the second base region30B. The second drift layer18B extends from the surface of the fourth semiconductor layer12B toward the second base region30B side. An n+-type second drain region34B is provided on the surface of the sixth semiconductor layer16B. The second drain region34B opposes the second source region32B with the second insulating layer20B interposed. A second back gate region36B is provided on the surface of the second base region30B to be adjacent to the second source region32B. The second back gate region36B functions as a carrier release region.

A second inter-layer insulating film50B is provided on the second back gate region36B, on the second source region32B, on the second insulating layer20B, on the second gate electrode40B, and on the second drain region34B.

In the semiconductor element100B, a second source electrode52B is electrically connected to the second source region32B and the second back gate region36B via a second source contact51B. A second drain electrode54B is electrically connected to the second drain region34B via a second drain contact53B.

The concentration of the n-type impurity element included in the second drift layer18B is lower than the concentration of the n-type impurity element included in the fourth semiconductor layer12B. The concentration of the n-type impurity element included in the second drift layer18B is higher than the concentration of the n-type impurity element included in the fifth semiconductor layer14B.

For example, the right side ofFIG. 2Billustrates the n-type impurity element concentration profile at positions along line90B. The vertical axis of the impurity element concentration profile is the depth; and the horizontal axis is the impurity concentration.

For example, the concentration of the impurity element of the fifth semiconductor layer14B is substantially constant in the depth direction. In the second drift layer18B, the concentration of the impurity element increases once toward the fourth semiconductor layer12B. Then, the concentration of the impurity element conversely decreases toward the fourth semiconductor layer12B side. In other words, the impurity element concentration profile of the second drift layer18B has the peak P. The concentration of the impurity element of the fourth semiconductor layer12B is higher than the concentrations of the impurity elements of the fifth semiconductor layer14B and the second drift layer18B.

In other words, the peak value of the n-type impurity element concentration profile included in the second drift layer18B is lower than the concentration of the n-type impurity element included in the fourth semiconductor layer12B. The peak value of the n-type impurity element concentration profile included in the second drift layer18B is higher than the concentration of the n-type impurity element included in the fifth semiconductor layer14B.

It is unnecessary for the peak P of the impurity element concentration profile of the second drift layer18B to be one peak. The peak P may be multiple. In such a case as well, one peak value of the multiple peaks P is lower than the concentration of the n-type impurity element included in the fourth semiconductor layer12B and higher than the concentration of the n-type impurity element included in the fifth semiconductor layer14B.

In the semiconductor device1, the thickness of the first drift layer18A is different from the thickness of the second drift layer18B. Alternatively, the concentration of the n-type impurity element included in the first drift layer18A is different from the concentration of the n-type impurity element included in the second drift layer18B. The configuration of the semiconductor element100A other than the first drift layer18A is the same as the configuration of the semiconductor element100B other than the second drift layer18B.

In the semiconductor device1, the element size of the semiconductor element100A is the same as the element size of the semiconductor element100B. For example, the distance from the first base region30A to the third semiconductor layer16A is the same as the distance from the second base region30B to the sixth semiconductor layer16B.

The first drift layer18A and the second drift layer18B are formed by, for example, ion implantation. The thickness and the impurity concentration can be changed between the first drift layer18A and the second drift layer18B by changing the ion implantation conditions (the acceleration, the dose, etc.) between the first drift layer18A and the second drift layer18B.

The main component of the semiconductor element100A other than the first insulating layer20A is, for example, silicon (Si). The material of the first insulating layer20A is, for example, silicon oxide (SiO2). The main component of the semiconductor element100B other than the second insulating layer20B is, for example, silicon (Si). The material of the second insulating layer20B is, for example, silicon oxide (SiO2).

In the embodiment, there are cases where the n+type, the n−type, and the n type are referred to collectively as the first conductivity type, and the p+type and the p type are referred to collectively as the second conductivity type. The n+type means that the concentration of the n-type impurity is higher than that of the n type; and the n−type means that the concentration of the n-type impurity is lower than that of the n type. The p+type means that the concentration of the p-type impurity is higher than that of the p type. Phosphorus (P), arsenic (As), and the like are examples of the impurity element of the first conductivity type. Boron (B) and the like are examples of the impurity element of the second conductivity type. Generally, the resistivity of the semiconductor layer decreases as the impurity concentration increases.

The first semiconductor layer12A and the fourth semiconductor layer12B may be referred to as n+-type buried layers. The second semiconductor layer14A and the fifth semiconductor layer14B may be referred to as epitaxial layers. The third semiconductor layer16A and the sixth semiconductor layer16B may be referred to as drain deep n+layers. The first base region30A and the second base region30B may be referred to as channel diffusion layers. The thicknesses of the second semiconductor layer14A and the fifth semiconductor layer14B are, for example, 5 μm. The thicknesses of the first insulating layer20A and the second insulating layer20B are, for example, 1.2 μm.

Thus, the semiconductor device1includes the semiconductor elements100A and the semiconductor elements100B on the same semiconductor substrate10.

Effects of the semiconductor device1will now be described.

FIGS. 3A and 3Bare schematic cross-sectional views illustrating effects of the semiconductor device according to the embodiment.

For example, in the semiconductor element100A, the potential difference between the first source region32A and the first gate electrode40A is a voltage that is lower than the threshold; and a positive voltage (a reverse-biased voltage) with respect to the first source region32A is applied to the first drain region34A. Then, a depletion layer extends from the junction portion (the pn junction interface) between the second semiconductor layer14A and the first base region30A into the second semiconductor layer14A side and the first base region30A side. The appearance of the extension of the depletion layer is illustrated in the drawings by arrows d. In such a case, the carriers are driven out of the second semiconductor layer14A and the first base region30A; and the semiconductor element100A is switched to the off-state. In the off-state, a current does not flow between the first source region32A and the first drain region34A.

On the other hand, in the case where a positive voltage with respect to the first source region32A is applied to the first drain region34A and the potential difference between the first source region32A and the first gate electrode40A is a voltage that is higher than the threshold, an inversion layer is formed in the first base region30A proximal to the first insulating layer20A; and a channel is formed in the first base region30A. In such a case, the semiconductor element100A is switched to the on-state. Here, the current tends to flow as much as possible through the semiconductor layers that have low resistivity. In other words, the current flows through the path of the first source region32A/channel region/second semiconductor layer14A/first drift layer18A/first semiconductor layer12A/third semiconductor layer16A/first drain region34A. That is, the current flows between the first source region32A and the first drain region34A.

For example, the flow of the electron current is illustrated by the broken-line arrow e in the drawings. The electron current flows downward from the first source region32A and reaches the first semiconductor layer12A. Continuing, the electron current proceeds through the first semiconductor layer12A substantially parallel to the major surface of the first semiconductor layer12A. Subsequently, the electron current flows upward from the first semiconductor layer12A and reaches the first drain region34A. The effects of the semiconductor element100B are similar to those of the semiconductor element100A.

However, when it is assumed that the impurity concentration of the second drift layer18B is the same as the impurity concentration of the first drift layer18A, the depletion layer d extends more easily in the semiconductor element100B than in the semiconductor element100A in the off-state by the amount that the thickness of the second drift layer18B is thinner than the thickness of the first drift layer18A. Also, the on-resistance of the semiconductor element100B is higher than that of the semiconductor element100A by the amount that the thickness of the second drift layer18B is thinner than the thickness of the first drift layer18A. In other words, the breakdown voltage and the on-resistance of the semiconductor element100B are higher than those of the semiconductor element100A. In the semiconductor elements according to the embodiment, the breakdown voltage and the on-resistance can be adjusted by changing only the thicknesses of the drift layers.

In other words, in the semiconductor device1, semiconductor elements (the semiconductor element100A and the semiconductor element100B) having the same element size and different breakdown voltages and on-resistances can be provided together on the same semiconductor substrate10. In other words, an increase of the size of the semiconductor device1can be suppressed even in the case where the semiconductor element100A which has the low breakdown voltage and the semiconductor element100B which has the high breakdown voltage are provided together on the same semiconductor substrate10.

FIGS. 4A and 4Billustrate the relationships of the breakdown voltage with the thickness of the drift layer and the impurity concentration inside the drift layer.

FIG. 4Aillustrates the relationship between the thickness of the drift layer and the breakdown voltage when it is assumed that the impurity concentrations inside the drift layers are the same. As described above, the breakdown voltage tends to decrease as the thickness of the drift layer increases.

FIG. 4Billustrates the relationship between the impurity concentration inside the drift layer and the breakdown voltage when it is assumed that the thicknesses of the drift layers are the same. Even in the case where the thicknesses of the drift layers are the same, the breakdown voltages of the semiconductor elements can be changed by changing the impurity concentrations included inside the drift layers.

For example, the thickness of the first drift layer18A is the same as the thickness of the second drift layer18B, and the impurity concentration included inside the second drift layer18B is lower than the impurity concentration included inside the first drift layer18A. Thereby, breakdown due to avalanche breakdown occurs less easily inside the semiconductor element100B than inside the semiconductor element100A. As a result, the breakdown voltage of the semiconductor element100B is higher than the breakdown voltage of the semiconductor element100A.

Because the breakdown voltage and the on-resistance run counter to each other, the on-resistance of the semiconductor element increases when the breakdown voltage of the semiconductor element increases.

The first drift layer18A and the second drift layer18B are formed by separate photolithography processes and ion implantation.

Conversely,FIGS. 5A and 5Bare schematic cross-sectional views illustrating effects of a semiconductor device according to a reference example.

In the semiconductor element500according to the reference example as illustrated inFIG. 5A, an n+-type semiconductor layer120is provided on the semiconductor substrate10. An n−-type semiconductor layer140is provided on the semiconductor layer120. A drift layer180is provided from the surface of the semiconductor layer140into the interior of the semiconductor layer140. An insulating layer200is provided from the surface of the drift layer180into the interior of the drift layer180.

In the semiconductor element500, a p-type base region300is selectively provided on the surface of the semiconductor layer140. An n+-type source region320is selectively provided on the surface of the base region300. A gate electrode400is provided from the surface of the insulating layer200into the interior of the insulating layer200. The gate electrode400is adjacent to the base region300with the insulating layer200interposed. The insulating layer200that is provided between the gate electrode400and the base region300functions as a gate insulating film.

In the semiconductor element500, an n+-type drain region340is provided on the surface of the semiconductor layer140. The drain region340opposes the source region320with the insulating layer200interposed. A back gate region360is provided on the surface of the base region300to be adjacent to the source region320.

In the semiconductor element500, the drift layer180does not extend from the surface of the semiconductor layer120toward the base region300side. The drift layer180is formed to cover the bottom surface and the side surface of the insulating layer200.

In the semiconductor element500, the potential difference between the source region320and the gate electrode400is a voltage lower than the threshold; and a positive voltage with respect to the source region320is applied to the drain region340. Then, a depletion layer extends from the junction portion (the pn junction interface) between the drift layer180and the base region300into the drift layer180side and the base region300side. Also, a depletion layer extends from the junction portion (the pn junction interface) between the semiconductor layer140and the base region300into the semiconductor layer140side and the base region300side. In such a case, the carriers are driven out of the drift layer180and the base region300; and the semiconductor element500is switched to the off-state. In other words, a current does not flow between the source region320and the drain region340.

On the other hand, in the case where a positive voltage with respect to the source region320is applied to the drain region340and the potential difference between the source region320and the gate electrode400is a voltage that is higher than the threshold, an inversion layer is formed in the base region300proximal to the insulating layer200; and a channel is formed in the base region300. In such a case, the semiconductor element500is switched to the on-state. Here, the current tends to flow as much as possible through the semiconductor layers that have low resistivity. In other words, the current flows through the path of the source region320/channel region/drift layer180/drain region340. That is, the current flows between the source region320and the drain region340.

For example, the flow of the electron current is illustrated by the arrow e in the drawings. The electron current flows downward from the source region32A and reaches the drift layer180. Continuing, the electron current proceeds through the drift layer180, subsequently flows upward from the drift layer180, and reaches the drain region340.

However, in the semiconductor element500, the first drift layer18A (or the second drift layer18B) described above is not provided. Accordingly, it is necessary to increase the length of the drift layer180(the drift length) as illustrated inFIG. 5Bto increase the breakdown voltage of the semiconductor element500. In other words, in the reference example, the size of the semiconductor device undesirably increases in the case where the semiconductor element that has the low breakdown voltage and the semiconductor element that has the high breakdown voltage are provided together on the same semiconductor substrate10.

FIG. 6is a schematic cross-sectional view of a semiconductor device according to a modification of the embodiment.

In the semiconductor element100A, the first drift layer18A may contact a portion of the first insulating layer20A. In the case of such a mode, a semiconductor element having an even lower breakdown voltage and on-resistance can be provided on the semiconductor substrate10.

Although a trench-type gate electrode is illustrated in the embodiment, a planar-type gate electrode may be used instead of the trench-type gate electrode. Even in the case where the gate electrode is the planar-type, the electron current flows through the path of the first source region32A/channel region/second semiconductor layer14A/first drift layer18A/first semiconductor layer12A/third semiconductor layer16A/first drain region34A in the on-state. Such a mode also is included in the embodiment.