Semiconductor device having vertical MOSFET with super junction structure, and method for manufacturing the same

A method for manufacturing a semiconductor device includes: preparing a semiconductor substrate, in which a first semiconductor layer is formed on a substrate; forming a first concave portion in the first semiconductor layer; forming trenches on the first semiconductor layer in the first concave portion; epitaxially growing a second semiconductor layer for embedding in each trench and the first concave portion; forming a SJ structure having PN columns including the second semiconductor layer in each trench and the first semiconductor layer between the trenches; and forming the vertical MOSFET by: forming a channel layer and a source region contacting the channel layer on the SJ structure; forming a gate electrode over the channel layer through a gate insulating film; forming a source electrode connected to the source region; and forming a drain electrode on a rear of the substrate.

CROSS REFERENCE TO RELATED APPLICATION

This application is a U.S. national stage of International Application No. PCT/JP2013/007064 filed on Dec. 3, 2013 and is based on Japanese Patent Applications No. 2012-268412 filed on Dec. 7, 2012, No. 2012-268413 filed on Dec. 7, 2012 and No. 2013-222256 filed on Oct. 25, 2013, the disclosures of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device having a vertical MOSFET with a super junction (hereinafter referred to as “SJ”) structure in which a second semiconductor layer is epitaxially grown within a trench formed in a first semiconductor layer to form the SJ structure, and a method for manufacturing the same.

BACKGROUND ART

Up to now, semiconductor devices having the SJ structure in which n-type columns and p-type columns are alternately repetitively formed have been known (for example, refer to PTL 1). In manufacturing the semiconductor device of the SJ structure, for example, as illustrated inFIG. 9A, a semiconductor substrate J3in which an n−type layer J2is epitaxially grown on a surface of an n+type silicon substrate J1is used. After trenches J4have been formed in the n−type layer J2as illustrated inFIG. 9B, a p−type layer J5is epitaxially grown within the trenches J4as illustrated inFIG. 9C. Then, as illustrated inFIG. 10A, the p−type layer J5formed outside the trenches J4is removed by flattening and polishing the surface to leave the p−type layer J5only within the trenches J4. As a result, the SJ structure having a PN column in which n type columns formed of the n−type layer J2and p−type columns formed of the p−type layer J5are alternately repeated is formed.

Thereafter, as illustrated inFIG. 10B, after the SJ structure has been formed, a p−type layer J6is epitaxially grown, and then a subsequent device forming process is conducted. For example, as illustrated inFIG. 10C, a process of forming an n+type source region J7, a trench gate structure J8, a surface electrode J9, and a back surface electrode J10is performed in the same technique as that in the conventional art. Through this technique, the vertical MOS transistor of the SJ structure is manufactured.

However, the flattening and polishing of surfaces of the p−type layer J5and the n−type layer J2is performed after the p−type layer J5has been epitaxially grown so as to fill in the trenches J4. A variation in the flattening and polishing is large, and depths of the PN columns are varied, and cannot reach a desired depth with high precision. Aside from a problem on a precision of the epitaxial growth per se, this is further because the flattening and polishing of the p−type layer J5and the n−type layer J2is performed by a process for polishing the same semiconductor material (for example, silicon), and it is difficult to stop the polishing with a target film thickness in principle. When the depths of the PN columns are thus varied, a breakdown voltage of the semiconductor device is varied resulting in such a problem that the device characteristics are deteriorated.

The p−type layer J6is epitaxially grown on the SJ structure after the SJ structure has been formed. However, there also arises such a problem that processing between structures of the surface of the SJ structure and the p−type layer J6causes the p−type layer J6on an upper side thereof to abnormally grow, resulting in the deterioration of the device characteristics. In the present specification, the processing between the structures means the flattening and polishing of the surface of the SJ structure after the SJ structure has been formed, and wafer cleaning before the growth of the p−type layer J6. Crystal defects may occur depending on this processing, and the crystal defects may be taken over to abnormally grow the p-type layer.

Since the process of forming the p−type layer J6is performed, independently, there also arises such a problem that the manufacturing costs rise with an increase in the number of manufacturing processes.

PRIOR ART LITERATURES

Patent Literature

SUMMARY OF INVENTION

It is a first object of the present disclosure to provide a semiconductor device having a vertical MOSFET with a SJ structure, and a method for production of the semiconductor device, which are capable of suppressing the deterioration of device characteristics with the suppression of a variation in the depths of PN columns, and simplifying a manufacturing process. It is a second object of the present disclosure to provide a semiconductor device having a vertical MOSFET of an SJ structure, and a method for production of the semiconductor device, which suppress an abnormal growth of a second conductivity type layer in forming the second conductivity type layer on a first semiconductor layer after a second semiconductor layer of a second conductivity type is embedded in trenches formed in a first semiconductor layer of a first conductivity type to form an SJ structure, and suppress the deterioration of the device characteristics.

According to a first aspect of the present disclosure, a method for manufacturing a semiconductor device having a vertical MOSFET with a super junction structure includes: preparing a semiconductor substrate, in which a first semiconductor layer having a first conductivity type is formed on a surface of a substrate made of a semiconductor material; forming a step in the first semiconductor layer by forming a first concave portion that includes at least a part of a main region of the first semiconductor layer, the main region in which the vertical MOSFET is formed and used as a chip; forming a plurality of trenches by arranging a mask on the first semiconductor layer including an inside of the first concave portion, and etching the first semiconductor layer in the first concave portion of the main region using the mask; epitaxially growing a second semiconductor layer having a second conductivity type on the first semiconductor layer, and embedding the second semiconductor layer in each of the trenches and the first concave portion after removing at least a portion of the mask, which is formed in the first concave portion; forming a super junction structure having PN columns, in which a second conductivity type column provided by the second semiconductor layer left in each of the trenches and a first conductivity type column provided by the first semiconductor layer, which are arranged between the plurality of trenches, are alternately repeated, by flattening and polishing the second semiconductor layer to leave the second semiconductor layer in each of the trenches and the first concave portion; and forming the vertical MOSFET by: forming a channel layer having the first conductivity type and a source region having the second conductivity type in contact with the channel layer on the super junction structure; forming a gate electrode over a surface of the channel layer through a gate insulating film; forming a source electrode electrically connected to the source region on a surface side of the semiconductor substrate; and forming a drain electrode connected to a rear surface of the substrate on a rear surface side of the semiconductor substrate.

In the above method for manufacturing the semiconductor device, the first concave portion is formed in the first semiconductor layer in advance, and the second semiconductor layer is also embedded in the first concave portion when the second semiconductor layer is formed to be embedded in the trenches. For that reason, a portion of the second semiconductor layer which is formed in the first concave portion can be used as the second conductivity type layer formed on the SJ structure. Therefore, the second conductivity type layer for forming the second conductivity type columns and the second conductivity type layer formed on the SJ structure can be configured by the same second semiconductor layer, and can be formed at the same time. As a result, the manufacturing process can be simplified. There is no need to perform processing between the structures of the surface of the PN column and the second semiconductor layer such as the planar polishing of the surface of the PN columns or the wafer cleaning unlike a case of forming the second conductivity type layer on the SJ structure after the SJ structure has been configured. Hence, a variation in the breakdown voltage of the semiconductor device can be suppressed, and the deterioration of the device characteristic can be suppressed.

Alternatively, the method may further includes: forming a third concave portion in an outer peripheral region, which is a peripheral region of the main region where the vertical MOSFET is formed in the first semiconductor layer, before the epitaxially growing of the second semiconductor layer. In the epitaxially growing of the second semiconductor layer, the second semiconductor layer is formed on the first semiconductor layer to embed the second semiconductor layer in the third concave portion. In this case, the third concave portion is formed in the first semiconductor layer in advance, and the second semiconductor layer is also embedded in the third concave portion. With this configuration, even if the second semiconductor layer is removed on the first semiconductor layer, and polished until the first semiconductor layer is exposed in planarly polishing the second semiconductor layer, the second semiconductor layer is left in the third concave portion. For that reason, a resurf layer can be surely configured in the outer peripheral region.

According to a second aspect of the present disclosure, a method for manufacturing a semiconductor device having a vertical MOSFET with a super junction structure, includes: preparing a semiconductor substrate, in which a first semiconductor layer of a first conductivity type is formed on a surface of a substrate made of a semiconductor material; forming a plurality of trenches by etching the first semiconductor layer in a main region, in which the vertical MOSFT is formed and used as a chip, after a mask is arranged on the first semiconductor layer; forming the super junction structure having PN columns, in which a second conductivity type column provided by a second semiconductor layer left in each of the trenches and a first conductivity type column provided by the first semiconductor layer arranged between the plurality of trenches are alternately repeated, by epitaxially growing the second semiconductor layer having a second conductivity type on a part of the first semiconductor layer outside of the trenches, and embedding the second semiconductor layer in each of the trenches; and forming the vertical MOSFET by: forming a channel layer having the first conductivity type and a source region having the second conductivity type in contact with the channel layer on the super junction structure; forming a gate electrode over a surface of the channel layer through a gate insulating film; forming a source electrode electrically connected to the source region on a surface side of the semiconductor substrate; and forming a drain electrode connected to a rear surface of the semiconductor substrate on the rear surface side of the semiconductor substrate.

In the above method for manufacturing the semiconductor device, after the second semiconductor layer has been formed in the trenches formed in the first semiconductor layer, the second semiconductor layer is also continuously formed on a portion of the first semiconductor layer outside the trenches. In other words, the second semiconductor layer is further formed on the portion of the first semiconductor layer outside the trenches without performing the processing between the structures of the first semiconductor layer and the second semiconductor layer such as planar polishing after embedding the second semiconductor layer in the trenches. For that reason, in forming the second conductivity type layer on the first semiconductor layer, the abnormal growth of the second conductivity type layer can be suppressed, and the deterioration of the device characteristics can be suppressed.

According to a third aspect of the present disclosure, a semiconductor device having a vertical MOSFET with a super junction structure, includes: a semiconductor substrate, in which a first semiconductor layer having a first conductivity type is arranged on a surface of a substrate made of a semiconductor material; a first concave portion that is arranged in a part of the first semiconductor layer; a convex portion that is provided by a step arranged in the first semiconductor layer with the first concave portion, and is located in the first semiconductor layer outside the first concave portion; a plurality of trenches that is arranged in the first semiconductor layer on a lower side of the first concave portion; a second semiconductor layer having a second conductivity type that is embedded in each of the trenches and the first concave portion, and epitaxially arranged on the first semiconductor layer; the super junction structure having PN columns, in which a second conductivity type column provided by the second semiconductor in each of the trenches, and a first conductivity type column provided by the first semiconductor layer arranged between the plurality of trenches are alternately repeated; a channel layer having a first conductivity type and a source region having a second conductivity type in contact with the channel layer, which are arranged on the super junction structure; a gate electrode that is arranged over a surface of the channel layer through a gate insulating film; a source electrode that is electrically connected to the source region; and a drain electrode that is connected to a rear surface of the substrate arranged on a rear surface side of the semiconductor substrate.

In the above semiconductor device, the first concave portion is formed in the first semiconductor layer in advance, and the second semiconductor layer is also embedded in the first concave portion when the second semiconductor layer is arranged to be embedded in the trenches. For that reason, a portion of the second semiconductor layer which is formed in the first concave portion can be used as the second conductivity type layer formed on the SJ structure. Therefore, the second conductivity type layer for forming the second conductivity type columns and the second conductivity type layer formed on the SJ structure can be configured by the same second semiconductor layer, and can be formed at the same time. As a result, the manufacturing process can be simplified. There is no need to perform processing between the structures of the surface of the PN column and the second semiconductor layer such as the planar polishing of the surface of the PN columns or the wafer cleaning unlike a case of forming the second conductivity type layer on the SJ structure after the SJ structure has been configured. Hence, a variation in the breakdown voltage of the semiconductor device can be suppressed, and the deterioration of the device characteristic can be suppressed.

According to a fourth aspect of the present disclosure, a method for manufacturing a semiconductor device having a vertical MOSFET with a super junction structure, includes: preparing a semiconductor substrate, in which a first semiconductor substrate having a first conductivity type is formed on a surface of a substrate made of a semiconductor material, and a second semiconductor layer having a second conductivity type is formed on the first semiconductor layer; forming a plurality of trenches that penetrates the second semiconductor layer, and reaches the first semiconductor layer by arranging a mask on the second semiconductor layer, and etching the second semiconductor layer and the first semiconductor layer using the mask; epitaxially growing a third semiconductor layer having a second conductivity type on the second semiconductor layer, and embedding the third semiconductor layer in each of the trenches after removing at least a portion of the mask which is located in a periphery of each of the trenches; forming the super junction structure having PN columns, in which a second conductivity column provided by the third semiconductor layer left in each of the trenches and a first conductivity type column provided by the first semiconductor layer between the plurality of trenches are alternately repeated, by flattening and polishing the third semiconductor layer to expose the second semiconductor layer and to leave the third semiconductor layer in each of the trenches; and forming the vertical MOSFET by: forming a channel layer having the first conductivity type and a source region having the second conductivity type in contact with the channel layer on the super junction structure; forming a gate electrode over a surface of the channel layer through a gate insulating film; forming a source electrode electrically connected to the source region on a surface side of the semiconductor substrate; and forming a drain electrode connected to a rear surface of the substrate on a rear surface side of the semiconductor substrate.

In the above method for producing the semiconductor device, the second semiconductor layer is formed on the first semiconductor layer in advance before the trenches for forming the second conductivity type columns are formed, and the trenches are formed in the surface of the second semiconductor layer. Then, the third semiconductor layer for forming the second conductivity type columns is formed in the trenches and on the second semiconductor layer. For that reason, unlike a case in which the third semiconductor layer is formed after the SJ structure has been configured, the surface of the PN columns are not planarly polished, and there is no need to perform the processing between the structures of the surface of the PN columns and the third semiconductor layer. Therefore, the depth of the PN columns is not affected by planarly polishing the third semiconductor layer. Hence, a variation in the breakdown voltage of the semiconductor device can be suppressed, and the deterioration of the device characteristic can be suppressed.

Alternatively, the preparing of the semiconductor substrate may be performed by: preparing the semiconductor substrate, in which a concave portion is formed in an outer peripheral region of the first semiconductor layer as a peripheral region of a cell region in which the vertical MOSFET is formed, and the second semiconductor layer is formed on the first semiconductor layer to embed the second semiconductor layer in the concave portion. In this case, the concave portion is formed in the first semiconductor layer in advance, and the second semiconductor layer is also embedded in the concave portion. For that reason, even if the second semiconductor layer is removed, and polished until the first semiconductor layer is exposed in planarly polishing the third semiconductor layer, the second semiconductor layer is left in the concave portion. For that reason, a resurf layer can be surely configured in the outer peripheral region.

EMBODIMENTS FOR CARRYING OUT INVENTION

Embodiments of the present disclosure will be described below with reference to the drawings. In the following respective embodiments, parts identical with or equivalent to each other are denoted by the same symbols for description.

First Embodiment

Subsequently, a method for producing a semiconductor device according to a first embodiment of the present disclosure will be described with reference toFIGS. 1A to 2B. A vertical MOSFET of an SJ structure will be exemplified by a semiconductor device having a trench gate vertical MOSFET.

A semiconductor substrate10is prepared. In the semiconductor substrate10, an n−type layer12corresponding to a first semiconductor layer is epitaxially grown on a surface11aof an n+type silicon substrate11as a substrate made of a semiconductor material with the surface11aand the rear surface11b. The n+type silicon substrate11is a portion that functions as a drain region, and set to be higher in an n-type impurity concentration than the n−type layer12. The n−type layer12is a portion that functions as a drift layer and also configures an n-type column in PN columns.

On a surface side of the semiconductor substrate10, an oxide film13is formed on a surface of the n−type layer12through a CVD (chemical vapor deposition) technique or thermal oxidation. Thereafter, a resist not shown is arranged on the oxide film13, the resist is opened in a main region in which a vertical MOSFET is formed and used as a chip, and the resist is also opened in a scribe region, through a photolithography process. In this situation, the resist is left at a boundary position between the main region and the scribe region. Then, an etching process is executed to open the oxide film13at an open position of the resist.

Then, the resist is removed, and anisotropic etching such as an RIE (reactive ion etching) technique or a BOSCH technique is performed with the oxide film13as a mask. In the BOSCH technique, O2and C4F8as well as SF6are alternately repetitively introduced to repetitively perform bottom etching and side wall protection using a polymer film. Specifically, etching is performed to the degree of removing the n−type layer12by a predetermined depth of about 2.5 to 3.5 μm. With this process, a concave portion12ais formed in the main region of the n−type layer12to provide a step between the main region and the scribe region. Simultaneously, a concave portion12bserving as a target of alignment at the time of matching the mask in a post-process is formed in the scribe region. The n−type layer12is left in a concave shape at the boundary position between the main region and the scribe region, specifically, in at least a part of an outer edge of the main region. Thereafter, the oxide film13is removed.

Again, on the surface side of the semiconductor substrate10, an oxide film14is formed in thickness of 0.2 to 0.3 μm so as to cover the n−type layer12through the CVD technique or the thermal oxidation. Thereafter, a resist not shown is arranged on the oxide film14, and the resist is opened at positions where trenches are to be formed, and the oxide film14is opened at the open positions, through a photolithography process. Then, the resist is removed, and anisotropic etching such as the RIE or the BOSCH technique is performed with the oxide film14as a mask. Specifically, the n−type layer12is etched in the concave portion12aby a predetermined depth, for example, a depth equal to or slightly smaller than a thickness of the n−type layer12. With this process, SJ structure formation trenches15which are, for example, stripped are formed at desired positions of the n−type layer12.

A portion of the oxide film14which is formed at a position distant from the trenches15is left, and portions of the oxide film14arranged in the periphery of the opening portions of the trenches15, specifically, portions formed in the concave portion12aare removed.

For example, after a resist is again arranged on the oxide film14, the resist is opened in the main region of the semiconductor substrate10where the vertical MOSFET is formed and used as a chip. Then, etching is performed in a state where the scribe region to be cut at the time of dicing which is a region for forming a target of alignment is covered with a resist to pattern the oxide film14. Alternatively, hydrogen annealing is executed to retract the portions of the oxide film14which are formed around the opening portions of the trenches15of the oxide film14. For example, in a reduced pressure atmosphere of 10.6 kPa (80 Torr) or lower, with the execution of hydrogen annealing at a temperature of 1100° C. for a time of 10 minutes, or hydrogen annealing at a temperature of 1170° C. for a time of 2 minutes, the periphery of the opening portions of the trenches15in the oxide film14can removed.

Thereafter, on the surface side of the semiconductor substrate10, a p−type layer16corresponding to a second semiconductor layer is epitaxially grown on a surface of the n−type layer12including the insides of the concave portion12aand the trenches15so that, for example, a p-type impurity concentration becomes 2×1015to 5×1015cm−3. In this situation, over-epitaxial growth is performed, and in the over-epitaxial growth, the p−type layer16is also formed on the n−type layer12while being completely embedded in the concave portion12aand the respective trenches15. For example, the p−type layer16is formed on the n−type layer12with a thickness of about 5 to 7 μm.

First, a portion of the p−type layer16which protrudes from the semiconductor substrate10more than the oxide film14, that is, a portion protruding from a convex portion other than the concave portion12aformed in the n−type layer12is removed by flattening and polishing of the surface such as CMP (chemical mechanical polishing). In this situation, because the oxide film14different from the p−type layer16to be polished can be used as an end point detection stopper, the flattening and polishing can stop with high precision.

Subsequently, the oxide film14is etched. With this process, the oxide film14is removed in the scribe region and in the vicinity of the scribe region in the main region to form a step between the exposed n−type layer12and the p−type layer16. For that reason, the surface is again flattened and polished through the CMP to flatten and polish the n−type layer12and the p−type layer16so as to eliminate the step. With this process, a structure in which the p-type columns in the SJ structure are configured by portions of the p−type layer16which are formed in the trenches15while the p−type layer16is also formed on the SJ structure is completed.

Because a polishing process of the same semiconductor material (silicon) such as the n−type layer12and the p−type layer16is performed in planarizing the surface, there is nothing functioning as a stopper of the surface planarization. However, because the thickness of the oxide film14is as very thin as 0.2 to 0.3 μm, the flattening and polishing is performed without any large variation by only time control even if there is no stopper. Since the processing between the structures of the surface of the PN columns and the p−type layer16is not conducted, even if a slight variation occurs, a breakdown voltage of the semiconductor device is not largely varied.

The subsequent processes are identical with those in the conventional art. For example, the following manufacturing process is performed. That is, p-type impurities are ion-implanted into a surface layer part of the p−type layer16on the n−type layer12configuring the n-type columns to form a p−type channel layer17. Also, n-type impurities are ion-implanted into a surface layer part of the p−type channel layer17to form an n+type source region18. In this situation, the n-type impurities are also ion-implanted into a portion left in a convex shape in an outer edge of the main region as occasion demands to form an n+type layer27. This makes it possible to perform conduction with the n−type layer12, and the n−type layer12can be fixed to a predetermined potential through the n+type layer27.

The convex portion is left in the outer edge of the main region, and the n+type layer27is formed to enable the potential to be fixed as described above, thereby being capable of ensuring a desired breakdown voltage in the outer peripheral region. That is, in the case of a structure having no convex portion, a potential on the surface side of the n−type layer12cannot be fixed, and the desired breakdown voltage cannot be ensured.

The p-type impurities are ion-implanted mainly into a portion of the p−type channel layer17which is formed on each of the p-type columns to form a p+type body layer19, and also form a p+type contact region20in a surface layer part of the p+type body layer19. Each gate trench21that penetrates through the p−type channel layer17and reaches a portion of the n−type layer12which configures each n-type column is formed. Further, a gate insulating film22is formed to cover an inner wall surface of each gate trench21, and a gate electrode23is formed on the gate insulating film22so as to be embedded in each gate trench21. A process of forming interlayer insulating films24, and a process of forming gate lines and a source electrode25are performed on the surface side of the semiconductor substrate10. On the rear surface side of the semiconductor substrate10, a process of forming a drain electrode26connected to the rear surface11bof the n+type silicon substrate11is performed to form a trench gate vertical MOSFET of an n-channel. Thereafter, the vertical MOSFET is diced into chip units to complete semiconductor devices having the vertical MOSFET of the SJ structure.

In the above method for producing the semiconductor device according to this embodiment as described above, the concave portion12ais formed in the n−type layer12in advance, and the p−type layer16is also embedded in the concave portion12awhen the p−type layer16is formed to be embedded in the trenches15. For that reason, a portion of the p−type layer16which is formed in the concave portion12acan be used as the p-type layer formed on the SJ structure.

Therefore, the p-type layer for forming the p-type columns and the p-type layer formed on the SJ structure can be configured by the same p−type layer16, and can be formed at the same time. As a result, the manufacturing process can be simplified. Unlike a case of forming the p-type layer on the SJ structure after the SJ structure has been configured, the flattening and polishing of the surface of the PN columns is not performed, and there is no need to perform processing between the structures of the surface of the PN columns and the p−type layer16such as the flattening and polishing or the wafer cleaning. Hence, a variation in the breakdown voltage of the semiconductor device can be suppressed, and the deterioration of the device characteristic can be suppressed.

Further, a process of forming the concave portion12ais performed simultaneously with the formation of the concave portion12bserving as a target of alignment formed in the scribe region. For that reason, the process of forming the concave portion12aand the process of forming the concave portion12bcan be commonalized, and the manufacturing process can be simplified.

Second Embodiment

A second embodiment of the present disclosure will be described. In this embodiment, the vertical MOSFET formed in the semiconductor device in the first embodiment is changed to a planar type, and because the other configurations are identical with those in the first embodiment, only portions different from those in the first embodiment will be described.

Subsequently, a method for producing the vertical MOSFET according to this embodiment will be described with reference toFIGS. 4A and 4B.

First, after the processes inFIGS. 1A, 1B, 2A, and 2Bdescribed in the first embodiment is performed, the same process as that inFIG. 3Adescribed in the first embodiment is performed as a process ofFIG. 4A. With this process, a structure in which a p−type layer16is epitaxially grown on the surface of an n−type layer12including the insides of a concave portion12aand trenches15, and the p−type layer16is further left in the concave portion12ais configured on the surface side of a semiconductor substrate10. That is, a structure in which the p−type layer16has already been formed on the p-type columns configuring the SJ structure and the SJ structure is formed. Basically, those processes may be completely identical with those in the first embodiment. The thickness of the p−type layer16left on the SJ structure is set to the extent that an n-type connection layer30to be described later can be formed through the p−type layer16on the SJ structure in forming the n-type connection layer30by ion implantation.

In a process illustrated inFIG. 4B, a manufacturing process for forming the respective components of the planar vertical MOSFET is performed.

That is, p-type impurities are ion-implanted into a surface layer part of the p−type layer16on the SJ structure to form a p−type channel layer17, and n-type impurities are ion-implanted into a surface layer part of the p−type channel layer17to form an n+type source region18. The p-type impurities are ion-implanted mainly into a portion of the p−type channel layer17which is formed on each of the p−type layer16to form a p+type body layer19, and also form a p+type contact region20in a surface layer part of the p+type body layer19. Further, the n-type impurities are ion-implanted at a position spaced from each n+type source region18by a predetermine interval between the adjacent n+type source regions18which are arranged between the respective p+type contact region20, to thereby form the n-type connection layer30that reaches the n−type layer12from the p−type channel layer17. The n-type connection layer30is formed to penetrate through the p−type layer16and reach a portion of the n−type layer12which configures each of the n-type columns while coming in contact with a channel formation part in the p−type channel layer17. With this configuration, the n-type connection layer30forms a current path when the planar vertical MOSFET operates, and serves to reduce an on-resistance.

Further, a gate insulating film22that covers at least a surface of the p−type channel layer17is formed, and a gate electrode23is formed on the gate insulating film22. A process of forming interlayer insulating films24, and a process of forming gate lines and a source electrode25are performed on the surface side of the semiconductor substrate10. On the rear surface side of the semiconductor substrate10, a process of forming a drain electrode26connected to the rear surface11bof the n+type silicon substrate11is performed to form the planar vertical MOSFET of an n-channel. Thereafter, the vertical MOSFET is diced into chip units to complete semiconductor devices having the planar vertical MOSFET of the SJ structure.

As described above, the same manufacturing method as that in the first embodiment can be also applied to the semiconductor device having the planar vertical MOSFET, and the same advantages as those in the first embodiment can be obtained.

Third Embodiment

A third embodiment of the present disclosure will be described. This embodiment is directed to a manufacturing method taking a periphery breakdown voltage structure of the semiconductor device into account, in the second embodiment, and because the other configurations are identical with those in the second embodiment, only portions different from those in the second embodiment will be described.

A method of manufacturing a vertical MOSFET according to this embodiment, that is, a manufacturing method including a process of forming the periphery breakdown structure in the semiconductor device having the planar vertical MOSFET with the SJ structure will be described with reference toFIGS. 5A to 7B.

First, in a process illustrated inFIG. 5A, a substrate made of a semiconductor material with a surface11aand a rear surface11bis prepared. As the substrate, the n−type layer12corresponding to the first semiconductor layer is epitaxially grown on the surface11aof the n+type silicon substrate11. Then, the process illustrated inFIG. 1Bdescribed in the first embodiment is performed to form the concave portions12aand12b. Subsequently, a concave portion12cis formed in a portion corresponding to an outer peripheral region of the n−type layer12through a photo-etching process using a mask not shown. Specifically, a region in which the vertical MOSFET is formed in the main region is set as a cell region, and a resurf layer is formed in the outer peripheral region to form the periphery breakdown voltage structure. The concave portion12cis formed in the portion forming the resurf layer.

Thereafter, in a process illustrated inFIG. 5B, a p−type layer16is epitaxially grown on the surface of the n−type layer12so as to be embedded in the concave portion12c, and the surface is flattened and polished as occasion demands. In this situation, the p−type layer16is left in thickness of 3 to 7 μm, for example, on the surface of the n−type layer12. With this process, the semiconductor substrate10in which the p−type layer16in the concave portion12cis thicker than a portion in which the concave portion12cis not formed is formed.

Thereafter, in processes illustrated inFIGS. 6A, 6B, 7A, and 7B, the same processes as those inFIGS. 2A, 2B, 4A, and 4Bdescribed in the first and second embodiments are performed. With those processes, the semiconductor device having the planar vertical MOSFET of the SJ structure is completed. In the semiconductor device, the p−type layer16is deeply formed in the outer peripheral region of the cell region to configure a resurf layer40as the periphery breakdown voltage structure.

As described above, the manufacturing method taking a case in which the resurf layer is formed as the periphery breakdown voltage structure into account can be taken. Even with this method, the same advantages as those in the second embodiment can be obtained.

Even in the second embodiment, because the p−type layer16is also formed in the outer peripheral region, even if the concave portion12cis not formed, the resurf layer40can be formed in the outer peripheral region through the manufacturing method described in the second embodiment. However, as illustrated inFIG. 7A, the p−type layer16may be removed to the degree that the n−type layer12is exposed when the surface of the p−type layer16is flattened and polished. Similarly, in that case, with the execution of the same process as that inFIG. 7B, the semiconductor device having the planar vertical MOSFET of the SJ structure can be manufactured. In that case, the p−type layer16is not left in the outer peripheral region, and the resurf layer40cannot be formed. Therefore, as in this embodiment, the concave portion12cis formed in the n−type layer12in advance, and the p−type layer16is formed to be thicker than the cell region in the outer peripheral region in advance. As a result, the resurf layer40can be surely formed.

When the flattening and polishing is performed to the extent that the surface of the n−type layer12is exposed, since the n−type layer12may be polished, there is a possibility that the depths of the PN columns are varied. However, because the on-resistance is reduced by the n-type connection layer30, the flattening and polishing may be performed under a condition where the p−type layer16remains, and it is not essential to expose the n−type layer12as in the conventional art. For that reason, even if the n−type layer12is polished, the polishing amount is very small, a variation in the breakdown voltage attributable to a variation in the depth of the PN columns hardly occurs.

Other Embodiments

For example, the manufacturing method taking the periphery breakdown voltage structure into account as described in the third embodiment can be applied to the method for producing the semiconductor device having the trench gate vertical MOSFET described in the first embodiment. Specifically, after the processes including the process inFIG. 7Adescribed in the third embodiment have been performed, the same process as that inFIG. 3Bdescribed in the first embodiment is performed to provide a trench gate vertical MOSFET illustrated inFIG. 8. As described above, similarly, in producing the semiconductor device having the trench gate vertical MOSFET, when the concave portion12cis formed in the n−type layer12in advance, the p−type layer16remains in at least the concave portion12ceven after the flattening and polishing. With this process, the resurf layer40can be formed, and the same advantages as those in the third embodiment can be obtained.

Also, in the above respective embodiments, the MOSFET of the n-channel type in which the first conductivity type is n-type, and the second conductivity type is p-type has been described as an example. Alternatively, this disclosure can be applied to the MOSFET of the p-channel type in which the conductivity type of the respective components is reversed.

Also, in the above embodiment, the concave portion12ais formed so that the step is formed between the main region and the scribe region. Alternatively, the concave portion12amay be formed so that the step is formed in a place other than between those regions. For example, in wafer before being divided into the chip units, aside from the main region and the scribe region, unnecessary regions not chipped are present in the outer peripheral portions of those regions. For that reason, for example, the first concave portion12amay be formed with the inclusion of the main region and the scribe region so that the step is formed between the main region and the scribe region, and the unnecessary regions. Also, the step may be formed in the outer peripheral portion of the main region. In that case, the first concave portion12amay be formed with the inclusion of at least a part of the main region, specifically, with the inclusion of the cell region.

Further, in the above embodiment, the example of forming the first concave portion12aso that the variation in the depth of the PN columns when forming the SJ structure can be suppressed is described. However, the abnormal growth of the p−type layer16based on the process between the structures such as the flattening and polishing can be suppressed regardless of whether the first concave portion12ais formed, or not. That is, the p−type layer16is formed on portions of the n−type layer12outside the trenches15continuously while the p−type layer16is embedded in the trenches15formed in the n−type layer12. As a result, the abnormal growth of the p−type layer16can be suppressed, and the deterioration of the device characteristics can be suppressed.

Fourth Embodiment

Subsequently, a method for producing a semiconductor device according to a fourth embodiment of the present disclosure will be described with reference toFIGS. 11A to 12B. A vertical MOSFET of an SJ structure will be exemplified by a semiconductor device having a trench gate vertical MOSFET.

A semiconductor substrate110is prepared. In the semiconductor substrate110, an n−type layer112corresponding to a first semiconductor layer and a p−type layer113corresponding to a second semiconductor layer are epitaxially grown on a surface111aof an n+type silicon substrate111as a substrate made of a semiconductor material with the surface111aand the rear surface111b. The n+type silicon substrate111is a portion that functions as a drain region, and set to be higher in an n-type impurity concentration than the n−type layer112. The n−type layer112is a portion that functions as a drift layer and also configures an n-type column in PN columns. The p−type layer113is intended to form the channel and configure a breakdown voltage structure in an outer periphery thereof not shown, and has a thickness of, for example, 3 to 7 μm.

On a surface side of the semiconductor substrate110, an oxide film114is formed in thickness of 0.2 to 0.3 μm so as to cover the p−type layer113through a CVD (chemical vapor deposition) technique or thermal oxidation. Thereafter, a resist not shown is arranged on the oxide film114, and the resist is opened at positions where trenches are to be formed, and the oxide film114is opened at the open positions, through a photo etching process. Then, the resist is removed, and anisotropic etching such as an RIE (reactive ion etching) technique or a BOSCH technique is performed with the oxide film114as a mask. In the BOSCH technique, O2and C4F8as well as SF6are alternately repetitively introduced to repetitively perform bottom etching and side wall protection using a polymer film. Specifically, the n−type layer112is etched through the p−type layer113by a predetermined depth, for example, a depth equal to or slightly smaller than a thickness of the n−type layer112. With this process, SJ structure formation trenches115which are, for example, stripped are formed at desired positions of the n−type layer112.

A portion of the oxide film114which is formed at a position distant from the trenches115is left, and portions of the oxide film114arranged in the periphery of the opening portions of the trenches115are removed.

For example, after a resist is again arranged on the oxide film114, the resist is opened in the main region of the semiconductor substrate110where the vertical MOSFET is formed and used as a chip. Then, etching is performed in a state where the scribe region to be cut at the time of dicing which is a region for forming a target of alignment is covered with a resist to pattern the oxide film114. Alternatively, hydrogen annealing is executed to retract the portions of the oxide film114which are formed around the opening portions of the trenches115of the oxide film114. For example, in a reduced pressure atmosphere of 10.6 kPa (80 Torr) or lower, with the execution of hydrogen annealing at a temperature of 1100° C. for a time of 10 minutes, or hydrogen annealing at a temperature of 1170° C. for a time of 2 minutes, the periphery of the opening portions of the trenches115in the oxide film114can be removed.

Thereafter, on the surface side of the semiconductor substrate110, a p−type layer116corresponding to a third semiconductor layer is epitaxially grown on a surface of the p−type layer113including the inside of the trenches115so that, for example, a p-type impurity concentration becomes 2×1015to 5×1015cm−3. In this situation, over-epitaxial growth is performed, and in the over-epitaxial growth, the p−type layer116is also formed on the p−type layer113while being completely embedded in the respective trenches115. For example, the p−type layer116is formed on the p−type layer13with a thickness of about 5 to 7 μm.

First, a portion of the p−type layer116which protrudes from the semiconductor substrate110more than the oxide film114is removed by flattening and polishing of the surface such as CMP (chemical mechanical polishing). In this situation, because the oxide film114different from the p−type layer116to be polished can be used as an end point detection stopper, the flattening and polishing can stop with high precision.

Subsequently, the oxide film114is etched. With this process, the oxide film114is removed in the scribe region and in the vicinity of the scribe region in the main region to form a step between the exposed p−type layer113and the p−type layer116. For that reason, the surface is again flattened and polished through the CMP to flatten and polish the p−type layer113and the p−type layer116so as to eliminate the step. With this process, a structure in which the p−type layer113has already been formed on the p-type columns configuring the SJ structure and the SJ structure is completed.

Because a polishing process of the same semiconductor material (silicon) such as the p−type layer113and the p−type layer116is performed in planarizing the surface, there is nothing functioning as a stopper of the surface planarization. However, because the thickness of the oxide film114is as very thin as 0.2 to 0.3 μm, the flattening and polishing is performed without any large variation by only time control even if there is no stopper. Since the processing between the structures of the surface of the PN columns and the p−type layer113is not conducted, even if a slight variation occurs, a breakdown voltage of the semiconductor device is not largely varied.

The subsequent processes are identical with those in the conventional art. For example, the following manufacturing process is performed. That is, p-type impurities are ion-implanted into a surface layer part of the p−type layer113on the n−type layer112configuring the n-type columns to form a p−type channel layer117. Also, n-type impurities are ion-implanted into a surface layer part of the p−type channel layer117to form an n+type source region118. The p-type impurities are ion-implanted mainly into a portion of the p−type channel layer117which is formed on the p−type layer116to form a p+type body layer119, and also form a p+type contact region120in a surface layer part of the p+type body layer119. Each gate trench121that penetrates through the p−type channel layer117and reaches a portion of the n−type layer112which configures each n-type column is formed. Further, a gate insulating film122is formed to cover an inner wall surface of each gate trench121, and a gate electrode123is formed on the gate insulating film122so as to be embedded in each gate trench121. A process of forming interlayer insulating films124, and a process of forming gate lines and a source electrode125are performed on the surface side of the semiconductor substrate110. On the rear surface side of the semiconductor substrate110, a process of forming a drain electrode126connected to the rear surface111bof the n+type silicon substrate111is performed to form a trench gate vertical MOSFET of an n-channel. Thereafter, the vertical MOSFET is diced into chip units to complete semiconductor devices having the vertical MOSFET of the SJ structure.

According to the method for producing the semiconductor device according to this embodiment as described above, the p−type layer113is formed on the n−type layer112in advance before forming the trenches115for forming the p-type columns, and the trenches115are formed in the surface of the p−type layer113. Then, the p−type layer116for forming the p-type columns is formed in the trenches115and on the p−type layer113.

For that reason, unlike a case of forming the p−type layer113after the SJ structure has been configured, the flattening and polishing of the surface of the PN columns is not performed, and there is no need to perform processing between the structures of the surface of the PN columns and the p−type layer113such as the flattening and polishing or the wafer cleaning. Therefore, the depth of the PN columns is not affected by flattening and polishing the p−type layer116. Hence, a variation in the breakdown voltage of the semiconductor device can be suppressed, and the deterioration of the device characteristic can be suppressed.

Fifth Embodiment

A fifth embodiment of the present disclosure will be described. In this embodiment, the vertical MOSFET formed in the semiconductor device in the fourth embodiment is changed to a planar type, and because the other configurations are identical with those in the fourth embodiment, only portions different from those in the fourth embodiment will be described.

A method for producing the vertical MOSFET according to this embodiment will be described with reference toFIGS. 13A and 13B.

First, after the same processes inFIGS. 11A to 11Cdescribed in the fourth embodiment is performed, the same process as that inFIG. 12Adescribed in the fourth embodiment is performed in a process ofFIG. 13A. With this process, a structure in which the p−type layer113has already been formed on the p-type columns configuring the SJ structure and the SJ structure is formed. Basically, those processes may be completely identical with those in the fourth embodiment. The thickness of the p−type layer113is set to the extent that an n-type connection layer130can be formed through the p−type layer113in forming the n-type connection layer130to be described later by ion implantation.

In a process illustrated inFIG. 13B, a manufacturing process for forming the respective components of the planar vertical MOSFET is performed.

That is, p-type impurities are ion-implanted into a surface layer part of the p−type layer113to form a p−type channel layer117, and n-type impurities are ion-implanted into a surface layer part of the p−type channel layer117to form an n+type source region18. The p-type impurities are ion-implanted mainly into a portion of the p−type channel layer117which is formed on each of the p−type layer116to form a p+type body layer119, and also form a p+type contact region120in a surface layer part of the p+type body layer119. Further, the n-type impurities are ion-implanted at a position spaced from each n+type source region118by a predetermine interval between the adjacent n+type source regions118which are arranged between the respective p+type contact region120, to thereby form the n-type connection layer130that reaches the n−type layer112from the p−type channel layer117. The n-type connection layer130is formed to penetrate through the p−type layer113and reach a portion of the n−type layer112which configures each of the n-type columns while coming in contact with a channel formation part in the p−type channel layer117. With this configuration, the n-type connection layer130forms a current path when the planar vertical MOSFET operates, and serves to reduce an on-resistance.

Further, a gate insulating film122that covers at least a surface of the p−type channel layer117is formed, and a gate electrode123is formed on the gate insulating film122. A process of forming interlayer insulating films124, and a process of forming gate lines and a source electrode125are performed on the surface side of the semiconductor substrate110. On the rear surface side of the semiconductor substrate110, a process of forming a drain electrode126connected to the rear surface111bof the n+type silicon substrate111is performed to form a planar vertical MOSFET of an n-channel. Thereafter, the vertical MOSFET is diced into chip units to complete semiconductor devices having the planar vertical MOSFET of the SJ structure.

As described above, the same manufacturing method as that in the fourth embodiment can be also applied to the semiconductor device having the planar vertical MOSFET, and the same advantages as those in the fourth embodiment can be obtained.

Sixth Embodiment

A sixth embodiment of the present disclosure will be described. This embodiment is directed to a manufacturing method taking a periphery breakdown voltage structure of the semiconductor device into account, in the fifth embodiment, and because the other configurations are identical with those in the fifth embodiment, only portions different from those in the fifth embodiment will be described.

A method of manufacturing a vertical MOSFET according to this embodiment, that is, a manufacturing method including a process of forming the periphery breakdown voltage structure in the semiconductor device having the planar vertical MOSFET with the SJ structure will be described with reference toFIGS. 14A to 16B.

First, in a process illustrated inFIG. 14A, a substrate made of a semiconductor material with a surface111aand a rear surface111bis prepared. As the substrate, the n−type layer112corresponding to the first semiconductor layer is epitaxially grown on the surface111aof the n+type silicon substrate111. Then, a concave portion112ais formed in a portion corresponding to an outer peripheral region of the n−type layer112through a photo-etching process using a mask not shown. Specifically, a region in which the vertical MOSFET is formed is set as a cell region, and a resurf layer is formed in the outer peripheral region to form the periphery breakdown voltage structure. The concave portion112ais formed in the portion forming the resurf layer.

Thereafter, in a process illustrated inFIG. 14B, a p−type layer113is epitaxially grown on the surface of the n−type layer112so as to be embedded in the concave portion112a, and the surface is flattened and polished as occasion demands. In this situation, the p−type layer113is left in thickness of 3 to 7 μm, for example, on the surface of the n−type layer112. With this process, the semiconductor substrate110in which the p−type layer113in the concave portion112ais thicker than a portion in which the concave portion112ais not formed is formed.

Thereafter, in processes illustrated inFIGS. 15A, 15B, 16A, and 16B, the same processes as those inFIGS. 11B and 11Cdescribed in the fourth embodiment andFIGS. 13A and 13Bdescribed in the fifth embodiment are performed. With those processes, the semiconductor device having the planar vertical MOSFET of the SJ structure is completed. In the semiconductor device, the p-type layer116is deeply formed in the outer peripheral region of the cell region to configure a resurf layer140as the periphery breakdown voltage structure.

As described above, the manufacturing method taking a case in which the resurf layer is formed as the periphery breakdown voltage structure into account can be taken. Even with this method, the same advantages as those in the fifth embodiment can be obtained.

Even in the fifth embodiment, because the p−type layer113is also formed in the outer peripheral region, even if the concave portion112ais not formed, the resurf layer140can be formed in the outer peripheral region through the manufacturing method described in the fifth embodiment. However, for example, as illustrated inFIG. 17A, the p−type layer113and the p−type layer116may be removed to the degree that the n−type layer112is exposed when the surfaces of the p−type layer113and the p−type layer116illustrated inFIG. 16Aare flattened and polished. Similarly, in that case, as illustrated inFIG. 17B, with the execution of the same process as that inFIG. 16B, the semiconductor device having the planar vertical MOSFET of the SJ structure can be manufactured. In that case, the p-type layer116is not left in the outer peripheral region, and the resurf layer140cannot be formed. Therefore, as in this embodiment, the concave portion112ais formed in the n−type layer112in advance, and the p−type layer113is formed to be thicker than the cell region in the outer peripheral region in advance. As a result, the resurf layer140can be surely formed.

When the flattening and polishing is performed to the extent that the surface of the n−type layer112is exposed, since the n−type layer112may be polished, there is a possibility that the depths of the PN columns are varied. However, because the on-resistance is reduced by the n-type connection layer130, the flattening and polishing may be performed under a condition where the p−type layer113remains, and it is not essential to expose the n−type layer112as in the conventional art. For that reason, even if the n−type layer112is polished, the polishing amount is very small, a variation in the breakdown voltage attributable to a variation in the depth of the PN columns hardly occurs.

Other Embodiments

For example, the manufacturing method taking the periphery breakdown voltage structure into account as described in the sixth embodiment can be applied to the method for producing the semiconductor device having the trench gate vertical MOSFET described in the fourth embodiment. Specifically, after the same processes as those inFIGS. 13A, 13B, 14A, 14B, and 15Adescribed in the sixth embodiment have been performed, the same process as that inFIG. 12Bdescribed in the fourth embodiment is performed to provide a trench gate vertical MOSFET illustrated inFIG. 18. As described above, similarly, in producing the semiconductor device having the trench gate vertical MOSFET, when the concave portion112ais formed in the n−type layer112in advance, the p−type layer113remains in at least the concave portion112aeven after the flattening and polishing. With this process, the resurf layer140can be formed, and the same advantages as those in the sixth embodiment can be obtained.

Also, in the above respective embodiments, the MOSFET of the n-channel type in which the first conductivity type is n-type, and the second conductivity type is p-type has been described as an example. Alternatively, this disclosure can be applied to the MOSFET of the p-channel type in which the conductivity type of the respective components is reversed.