Pixels of image sensors, image sensors including the pixels, and image processing systems including the image sensors

Pixels of image sensors are provided. The pixels may include a photo diode configured to accumulate photocharges generated therein corresponding to incident light during a first period, a storage diode configured to store photocharges accumulated in the photo diode and a storage gate configured to control transfer of the photocharges accumulated in the photo diode to the storage diode. The storage gate may include a vertical gate structure extending toward the photo diode.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2014-0139915 filed on Oct. 16, 2014, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

Embodiments of the inventive concepts relate to pixels of an image sensor, image sensors including the pixels, and an image processing system including the image sensors, and more particularly, to pixels including transistors which provide improved performance, image sensors including the pixels, and image processing systems including the image sensors.

Image sensors are devices that convert an optical image into an electrical signal. Image sensors are used in digital cameras or other types of image processing devices. Image sensors may include a plurality of pixels.

Mechanical shutter mode and electronic shutter mode are largely used to control an exposure time that determines amount of photocharges corresponding electrical signal. In mechanical shutter mode, a mechanical device blocks light to pixels. Electronic shutter mode is usually used in complementary metal-oxide semiconductor (CMOS) image sensors. In electronic shutter mode, an integration time during which photocharges are generated and accumulated is electrically controlled. Electronic shutter mode includes rolling shutter mode and global shutter mode.

In rolling shutter mode, an integration time is controlled separately for each row in a pixel array. In global shutter mode, an integration time is controlled uniformly throughout all rows in a pixel array.

Global shutter mode has an advantage of eliminating image distortion caused by different integration times among rows. However, it also has some disadvantages in terms of the degree of integration or signal transmission, and therefore, some improvements are desired.

SUMMARY

A pixel of an image sensor may include a photo diode that is configured to accumulate photocharges generated therein corresponding to incident light during a first period, a storage diode that is configured to store photocharges accumulated in the photo diode and a storage gate that is configured to control transfer of the photocharges accumulated in the photo diode to the storage diode. The storage gate may include a vertical gate structure extending toward the photo diode.

In various embodiments, the pixel may further include an overflow gate that is configured to control overflow of the photocharges accumulated in the photo diode into the storage diode during a second period that is different from the first period. The overflow gate may include a vertical gate structure extending toward the photo diode.

According to various embodiments, the pixel may further include a floating diffusion that is configured to receive photocharges stored in the storage diode and a transfer gate that is configured to control transfer of the photocharges stored in the storage diode to the floating diffusion. The transfer gate may include a vertical gate extending toward the storage diode.

According to various embodiments, the vertical gate may be a first vertical gate, and the storage gate may further include a second vertical gate extending toward the storage diode.

In various embodiments, the pixel may also include a photo diode area including the photo diode and a storage diode area including the storage diode. The photo diode area and the storage diode area may be arranged aslant with respect to either of a row direction or a column direction.

In various embodiments, the pixel may also include a floating diffusion that is configured to receive photocharges stored in the storage diode. A voltage level of the floating diffusion may be sensed by an adjacent pixel.

According to various embodiments, the pixel may further include a first deep trench isolation (DTI) at an edge of the pixel for electrical and optical isolation between the pixel and its adjacent pixel.

In various embodiments, the pixel may further include a second deep trench isolation (DTI) between the photo diode and the storage diode to shield the storage diode from the incident light.

In various embodiments, the pixel may also include a light shielding film on the storage diode to shield the storage diode from the incident light.

In various embodiments, the pixel may also include a metal shield on a surface of the storage gate to shield the storage gate from the incident light.

According to various embodiments, the pixel may further include a floating diffusion that is configured to receive photocharges stored in the storage diode, a reset transistor that is configured to control reset of the floating diffusion, a source follower that is configured to generate current corresponding to a voltage level of the floating diffusion and a select transistor that is configured to output the current as a pixel signal.

In various embodiments, an electric potential of the photo diode may be lower than an electric potential of the storage diode.

An image sensor that is configured to operate in global shutter mode may include a pixel array including a plurality of pixels, each of which outputs a pixel signal corresponding to incident light during a first period, a readout circuit that is configured to perform analog-to-digital conversion on the pixel signal to generate a digital pixel signal and a timing generator that is configured to control the pixel array and the readout circuit. Each of the pixels may include a photo diode that is configured to accumulate photocharges generated therein corresponding to the incident light during the first period, a storage diode that is configured to store photocharges accumulated in the photo diode and a storage gate that is configured to control transfer of the photocharges accumulated in the photo diode to the storage diode. The storage gate may include a vertical gate structure extending toward the photo diode.

In various embodiments, each of the plurality of pixels may further include an overflow gate that is configured to control overflow of the photocharges accumulated in the photo diode into the storage diode during a second period that is different from the first period. The overflow gate may include a vertical gate structure extending toward the photo diode.

According to various embodiments, each of the plurality of pixels may further include a floating diffusion that is configured to receive photocharges stored in the storage diode and a transfer gate that is configured to control transfer of the photocharges stored in the storage diode to the floating diffusion. The transfer gate may include a vertical gate extending toward the storage diode.

In various embodiments, the storage gate may also include a vertical gate extending toward the storage diode.

In various embodiments, each of the plurality of pixels may also include a photo diode area including the photo diode and a storage diode area including the storage diode. The photo diode area and the storage diode area may be arranged aslant with respect to either of a row direction or a column direction.

In various embodiments, the image sensor may further include a floating diffusion that is configured to receive photocharges stored in the storage diode. A voltage level of the floating diffusion may be sensed by a pixel adjacent each of the plurality of pixels.

According to various embodiments, each of the plurality of pixels may also include a light shielding unit to shield the storage diode from the incident light.

In various embodiments, the light shielding unit may include a first deep trench isolation (DTI) at an edge of the each of the plurality of pixels for electrical and optical isolation between the each of the plurality of pixels and its adjacent pixel, a second DTI between the photo diode and the storage diode to shield the storage diode from the incident light, a light shielding film on the storage diode to shield the storage diode from the incident light and a metal shield on a surface of the storage gate to shield the storage gate from the incident light.

According to various embodiments, each of the plurality of pixels may further include a floating diffusion that is configured to receive photocharges stored in the storage diode, a reset transistor that is configured to control reset of the floating diffusion, a source follower that is configured to generate current corresponding to a voltage level of the floating diffusion and a select transistor that is configured to output the current as a pixel signal.

A pixel of an image sensor may include a photo diode that is configured to accumulate photocharges generated therein corresponding to incident light, a storage diode that is configured to store photocharges accumulated in the photo diode, a storage gate that is configured to control transfer of the photocharges accumulated in the photo diode to the storage diode during a first period through a vertical storage gate extending toward the photo diode and an overflow gate that is configured to control discharge of photocharges generated in the photo diode during a second period that is different from the first period through a vertical overflow gate that extends toward the photo diode.

In various embodiments, the pixel may further include a floating diffusion that is configured to receive photocharges stored in the storage diode and a transfer gate that is configured to control transfer of the photocharges stored in the storage diode to the floating diffusion. The transfer gate may include a vertical transfer gate extending toward the storage diode.

According to various embodiments, the vertical storage gate may be a first vertical storage gate, and the storage gate may further include a second vertical storage gate extending toward the storage diode.

According to various embodiments, the pixel may also include a light shielding unit that is configured to shield the storage diode from the light incident.

According to various embodiments, the light shielding unit may include a first deep trench isolation (DTI) at an edge of the pixel for electrical and optical isolation between the pixel and its adjacent pixel, a second DTI between the photo diode and the storage diode to shield the storage diode from the incident light, a light shielding film on the storage diode to shield the storage diode from the incident light and a metal shield on a surface of the storage gate to shield the storage gate from the incident light.

An image processing system that is configured to operate in global shutter mode may include an image sensor including a pixel array that may include a plurality of pixels. Each of the plurality of pixels are configured to output a pixel signal corresponding to incident light during a first period and to perform analog-to-digital conversion on the pixel signal to generate a digital pixel signal. The system may also include an image signal processor that is configured to process the digital pixel signal to generate image data. Each of the plurality of pixels may include a photo diode that is configured to accumulate photocharges generated therein corresponding to the incident light during the first period, storage diode that is configured to store photocharges accumulated in the photo diode and a storage gate that is configured to control transfer of the photocharges accumulated in the photo diode to the storage diode. The storage gate may include a vertical gate structure extending toward the photo diode.

A pixel of an image sensor may include a photo diode that is configured to accumulate photocharges generated therein corresponding to incident light, a storage diode that is configured to store photocharges accumulated in the photo diode and a storage gate that is configured to control transfer of the photocharges accumulated in the photo diode to the storage diode. The storage diode and the photo diode may be disposed along a first direction. The storage gate may include a first portion extending in the first direction and a second portion protruding from the first portion and extending toward the photo diode in a second direction that is different from the first direction.

According to various embodiments, the second portion of the storage gate may extend into the photo diode.

In various embodiments, the storage gate may include a third portion protruding from the first portion and extending toward the storage diode.

According to various embodiments, a length of the second portion of the storage gate in the second direction may be greater than a length of the third portion of the storage gate in the second direction.

According to various embodiments, the pixel may further include an overflow gate that is configured to control overflow of the photocharges accumulated in the photo diode into the storage diode. The overflow gate may be spaced apart from the photo diode in the first direction, and the overflow gate may include a third portion extending in the first direction and a fourth portion protruding from the third portion and extending toward the photo diode.

In various embodiments, the pixel may also include a floating diffusion that is configured to receive photocharges from the storage diode and a transfer gate that is configured to control transfer the photocharges stored in the storage diode to the floating diffusion. The storage diode, the transfer gate and the floating diffusion may be arranged in the first direction, and the transfer gate may include a third portion extending in the first direction and a fourth portion protruding from the third portion and extending toward the storage diode.

According to various embodiments, the second direction may be substantially perpendicular to the first direction.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The inventive concepts may be embodied in many different forms, and specific structures or functions are described herein to explain example embodiments of the inventive concepts. The inventive concepts, however, should not be construed as limited to the embodiments set forth herein. The embodiments may be modified in various ways and may have various features and thus illustrated in the drawings and described in detail hereinafter. However, embodiments of the inventive concepts will not be restricted to the specifically disclosed features described below but will include any modifications, equivalents, or substitutes that do not depart from the spirit and scope of the inventive concepts.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other expressions such as “between” and “immediately between” or “adjacent to” and “immediately adjacent to” explaining the relationship between elements will be also interpreted in the same manner.

The inventive concepts now will be described more fully hereinafter by explaining embodiments of the inventive concepts with reference to the accompanying drawings.

FIG. 1is a block diagram of an image processing system100according to some embodiments of the inventive concepts. The image processing system100may be implemented as a portable electronic device such as a laptop computer, a cellular phone, a smart phone, a tablet personal computer (PC), a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, a portable multimedia player (PMP), a mobile internet device (MID), a wearable computer, an internet of things (IoT) device, or an internet of everything (IoE) device.

The image processing system100includes an optical lens103, a complementary metal-oxide-semiconductor (CMOS) image sensor110, a digital signal processor (DSP)200, and a display300. Each of the CMOS image sensor110and the DSP200may be implemented in a chip.

The CMOS image sensor110may generate a digital pixel signal DPS corresponding to an object input (or captured) through the optical lens103. The CMOS image sensor110includes a pixel (or an active pixel sensor (APS)) array120, a row driver130, a timing generator140, a correlated double sampling (CDS) block150, a comparator block152, an analog-to-digital conversion (ADC) block154, a control register block160, a ramp generator170, and a buffer180.

The CMOS image sensor110may perform a global shutter operation. In global shutter operation, an integration time (e.g., Tint inFIG. 9) during which photodiodes (e.g., PD inFIG. 4) in the pixel array120accumulate photocharges may be controlled uniformly throughout all rows in the pixel array120.

The pixel array120includes a plurality of pixels10arranged in a matrix. The structures and operations of the pixel array120and the pixels10will be described in detail with reference toFIGS. 2 through 10Flater. Each of the pixels10may be referred to as a unit pixel in a regard that the pixels10form one pixel array120.

The row driver130may transmit a plurality of control signals OS, RS, SS, TS, SLS, and FDB for controlling the operation of the pixels10to the pixel array120according to the control of the timing generator140. The control signals OS, RS, SS, TS, SLS, and FDB will be described in detail with reference toFIGS. 8 through 10Flater.

The timing generator140may control the operations of the row driver130, the CDS block150, the ADC block154, and the ramp generator170according to the control of the control register block160.

The CDS block150performs correlated double sampling (CDS) on pixel signals P1through Pm (where “m” is a natural number) output from respective column lines formed in the pixel array120. The comparator block152compares pixel signals (e.g., voltage levels) that have been subjected to CDS in the CDS block150with a ramp signal (e.g., a voltage level) output from the ramp generator170and outputs comparison signals according to the comparison result.

The ADC block154converts the comparison signals received from the comparator block152into digital signals and outputs the digital signals to the buffer180. The CDS block150, the comparator block152, and the ADC block154may form a readout circuit.

The control register block160controls the operations of the timing generator140, the ramp generator170, and the buffer180according to the control of the DSP200. The buffer180transmits digital pixel signals DPS corresponding to the digital signals output from the ADC block154to the DSP200. The DSP200includes an image signal processor210, a sensor controller220, and an interface230.

The image signal processor210controls the interface230and the sensor controller220which controls the control register block160. The image sensor110and the DSP200may be respectively implemented in chips in a single package, e.g., a multi-chip package. In some embodiments, the image sensor110and the image signal processor210may be respectively implemented in chips in a single package, e.g., a multi-chip package. In some embodiments, the image sensor110and the image signal processor210may be implemented in a single chip.

The image signal processor210processes the digital pixel signals DPS received from the buffer180and transmits processed image data IDATA to the interface230. The sensor controller220generates various control signals for controlling the control register block160according to the control of the image signal processor210. The interface230transmits the processed image data IDATA from the image signal processor210to the display300.

The display300displays the image data IDATA output from the interface230. The display300may be a thin film transistor-liquid crystal display (TFT-LCD), a light emitting diode (LED) display, an organic LED (OLED) display, or an active-matrix OLED (AMOLED) display.

FIG. 2is a diagram of the pixel array120according to some embodiments of the inventive concepts. Referring toFIGS. 1 and 2, it is assumed that the pixel array120includes only nine pixels10arranged in a 3×3 matrix with three rows and three columns. For convenience' sake in the description, it is described that the pixel array120includes nine pixels10, but inventive concepts are not restricted thereto. The pixel array120may have an n×m matrix format, where “n” and “m” are integer of at least 1.

3×3 pixel regions20are arranged in parallel or vertical to a row direction and a column direction. Each pixel region20may include a micro lens50that focuses incident light coming through the optical lens103on the center of the pixel region20.

Each of the pixels10may include one of photo diode areas PA11through PA33and one of storage diode areas SA11through SA33. For instance, a pixel10at the intersection between a second row and a second column includes the photo diode area PA22and the storage diode area SA22.

The photo diode areas PA11through PA33may include a photo diode (e.g., PD inFIG. 4) that accumulates photocharges generated therein corresponding to incident light. The photo diode PD may occupy most of each of the photo diode areas PA11through PA33. The center of each of the photo diode areas PA11through PA33may coincide with the center of the pixel region20, so that the micro lens50focuses incident light on the photo diode PD of each of the photo diode areas PA11through PA33.

The storage diode areas SA11through SA33may include a storage diode (e.g., SD inFIG. 4) that temporarily stores photocharges accumulated in the photo diode PD in order to realize global shutter mode. The storage diode areas SA11through SA33may be formed at an angle of 45 degrees with respect to the photo diode areas PA11through PA33, respectively. The storage diode SD may occupy most of each of the storage diode areas SA11through SA33.

Each storage diode area, e.g., SA22may be arranged adjacent to a photo diode area, e.g., PA22included in the same pixel10as the storage diode area SA22. The photo diode area PA22and the storage diode area SA22may be arranged aslant with respect to the row direction and/or the column direction. For instance, the photo diode area PA22and the storage diode area SA22may be arranged at an angle of 45 degrees with respect to the row direction and/or the column direction.

The micro lens50may be formed to correspond to the photo diode PD. Here, that the micro lens50corresponds to the photo diode PD may mean that the micro lens50has an area matching an area of the photo diode PD and is formed to overlap most of the area of the photo diode PD. Meanwhile, the micro lens50may be formed not to correspond to the storage diode SD. In other words, the micro lens50may have an area which does not match an area of the storage diode SD and may be formed not to overlap most of the area of the storage diode SD. This means that when micro lenses50are placed in the pixel regions20, a storage diode area, e.g., SA21may be arranged between adjacent micro lenses50, for example, the micro lenses50respectively corresponding to the photo diode areas PA11, PA12, PA21, and PA22.

The photo diode areas PA11through PA33are formed to correspond to the respective micro lenses50as much as possible and the storage diode areas SA11through SA33are formed in areas outside the photo diode areas PA11through PA33, so that the arrangement efficiency or the degree of integration of the pixels10is increased.

In addition, since the micro lenses50are not formed to correspond to the storage diode areas SA11through SA33and formed to correspond to the photo diode areas PA11through PA33only, light absorptance is increased and light leakage is decreased. The light absorptance may be the amount of light that can be absorbed per unit area. The light leakage may be a phenomenon in which noise occurs in the pixel signals P1through Pm because the storage diode SD that is supposed to store photocharges only generated by the photo diode PD stores other photocharges (e.g., photocharges generated from light incident on the storage diode SD).

The storage diode areas SA11through SA33may be formed at an angle of 135, 225 or 315 degrees to the respective photo diode areas PA11through PA33in some embodiments.

FIG. 3is a diagram of a layout of a pixel according to some embodiments of the inventive concepts. Referring toFIGS. 1 through 3, the layout500is a layout of the pixel10positioned at the intersection between the second row and the second column among the pixels10illustrated inFIG. 2. The layout500shows the arrangement of elements included in the pixel10.

The layout500may include the photo diode area PA22and the storage diode area SA22. The photo diode area PA22and the storage diode area SA22may include a deep trench isolation (DTI) region510and an active region515.

The DTI region510may be formed at the edge of the active region515for electrical or optical isolation from an active region (not shown) of an adjacent pixel (not shown). The DTI region510formed using a DTI process may be filled with oxide, for example, such as hafnium oxide, and/or polysilicon. For instance, the DTI region510may be formed of a polysilicon film doped with boron with high reflectance, but the inventive concepts are not limited thereto. The DTI region510may include material other than polysilicon doped with boron.

The DTI region510may reduce or possibly prevent electric crosstalk which causes a signal-to-noise ratio (SNR) to decrease due to exchange of carriers between active regions. In addition, sidewalls of the DTI region510may be doped with a material with high light reflectance, thereby reducing or possibly preventing optical crosstalk which causes an SNR to decrease because light incident on the active region515penetrates an adjacent active region (not shown). For instance, the sidewalls of the DTI region510may be formed of a polysilicon film doped with boron having high reflectance, but the inventive concepts are not limited thereto.

The active region515may include a shallow trench isolation (STI)520, a well530, a gate OG or540of an overflow transistor OX, a gate SG or542of a storage transistor SX, a gate TG or544of a transfer transistor TX, a gate RG or546of a reset transistor RX, a gate SFG or548of a source follower SF, a gate SELG or550of a select transistor SEL, a floating diffusion560, a pixel voltage terminal VP or570, a ground terminal GND or580, and an output terminal590. The arrangement of elements included in the active region515is not limited to that illustrated inFIG. 3and may be modified.

The STI520may be formed around the other elements in the inside of the DTI region510. The STI520may be formed using an STI process to electrically isolate the elements. The STI520may shallower than the DTI region510. The inside of the STI520may be formed of substantially the same material as the DTI region510.

The well area530is doped with p- or n-type impurities. It may be formed to electrically isolate elements from one another. A region highly doped with impurities (e.g., p++ or n++ impurities) may be formed in the well area530. This highly doped region may function as a source terminal and/or drain terminal of each of the overflow transistor OX, the storage transistor SX, the transfer transistor TX, the reset transistor RX, the source follower SF, and the select transistor SEL. The well area530may electrically insulate the highly doped region.

The gate540of the overflow transistor OX, the gate542of the storage transistor SX, the gate544of the transfer transistor TX, the gate546of the reset transistor RX, the gate548of the source follower SF, and the gate550of the select transistor SEL may respectively receive the control signals OS, SS, TS, RS, and SLS, which will be described with reference toFIG. 8later. The gate548of the source follower SF may be connected to the floating diffusion560. The gates540through550may be formed of polysilicon.

The gate540of the overflow transistor OX, the gate542of the storage transistor SX, the gate544of the transfer transistor TX, and the floating diffusion560may be sequentially arranged in a line. As shown inFIG. 8, photocharges accumulated at the photo diode PD are transferred from the photo diode PD to the storage diode SD and then to a floating diffusion FD.

The shorter the length of a channel among the photo diode PD, the storage diode SD, and the floating diffusion FD and the wider the channel, the higher the transfer efficiency of the photocharges. Accordingly, in order to maximize the transfer efficiency of photocharges among the photo diode PD, the storage diode SD, and the floating diffusion FD, the elements540,542,544, and560may be sequentially arranged in a line, as shown inFIG. 3.

The transfer of charges among the photo diode PD, the storage diode SD, and the floating diffusion FD is carried out in a very short section. Therefore, when the transfer efficiency is not satisfactory, all photocharges accumulated in the photo diode PD may not be transferred to the floating diffusion FD. This may cause noise in the pixel signals P1through Pm.

The floating diffusion560may be formed adjacent to the gate544of the transfer transistor TX. The floating diffusion560is a node which photocharges generated in the photo diode PD are transferred to through the storage transistor SX and the transfer transistor TX and accumulated at. The floating diffusion560may be connected to the gate548of the source follower SF, so that the voltage level of the floating diffusion560may be sensed by the source follower SF and the source follower SF may transmit a current corresponding to the voltage level to the select transistor SEL.

In some embodiments, the floating diffusion560may be connected to a gate (not shown) of a source follower of an adjacent pixel (e.g., a pixel including the photo diode area PA13and the storage diode area SA13) instead of the gate548of the source follower SF. The voltage level of the floating diffusion560may be sensed by the source follower included in a photo diode area of the adjacent pixel (e.g., PA13) and the source follower may transfer a current corresponding to the voltage level to a select transistor (not shown) included in a photo diode area of the adjacent pixel (e.g., PA13). Here, the adjacent pixel may be any pixel in a row different from that the layout500is in.

The pixel voltage terminal570may supply a pixel voltage Vpix necessary for the operation of the pixel10corresponding to the layout500. For instance, the pixel voltage terminal570may apply the pixel voltage Vpix to the drain terminal of each of the overflow transistor OX, the reset transistor RX, and the source follower SF. The pixel voltage Vpix may be equal to or lower than a power supply voltage VDD, but the inventive concepts is not limited thereto.

The ground terminal580may supply a ground voltage VSS necessary for the operation of the pixel10corresponding to the layout500. For instance, the ground terminal580may apply the ground voltage VSS to one end of each of the photo diode PD and the storage diode SD. The output terminal590may be connected to the source terminal of the storage transistor SX to output a pixel signal from the source terminal to a column line.

FIG. 4is a cross-sectional view of a pixel700-1having the layout500illustrated inFIG. 3according to some embodiments of the inventive concepts.FIG. 5is a cross-sectional view of a pixel700-2having the layout illustrated inFIG. 3according to some embodiments of the inventive concepts.FIG. 6is a cross-sectional view of a pixel700-3having the layout illustrated inFIG. 3according to some embodiments of the inventive concepts.FIG. 7is a cross-sectional view of a pixel700-4having the layout illustrated inFIG. 3according to some embodiments of the inventive concepts.

Referring toFIGS. 1 through 7, the pixel700-1illustrated inFIG. 4is an example of the cross-section taken along the line A-A′ illustrated inFIG. 3. The pixel700-1may include an incidence layer705, a semiconductor substrate710, and a wiring layer720.

The incidence layer705may include a micro lens701, a first flat layer702, a color filter703, and a second plat layer704. The micro lens701may be formed at the top (which is assumed to be a position at which incident light first arrives) of the pixel700-1to correspond to a photo diode PD or730. The micro lens701may be used to increase a light gathering power and thus to increase image quality. The micro lens701may be the micro lens50illustrated inFIG. 2.

The color filter703may be formed below the micro lens701. The color filter703may selectively transmit light with a predetermined wavelength (e.g., red, green, blue magenta, yellow, or cyan).

The first flat layer702and the second flat layer704may be respectively formed above and below the color filter703to possibly prevent light coming through the micro lens701and the color filter703from being reflected. In other words, the first flat layer702and the second flat layer704transmit incident light efficiently, thereby increasing the performance (such as light absorptance and photosensitivity) of the image sensor110.

The semiconductor substrate710may include the DTI region510, the STI520, the well area530, the gate540of the overflow transistor OX, the gate542of the storage transistor SX, the gate544of the transfer transistor TX, the floating diffusion560, the pixel voltage terminal570, the photo diode730, a storage diode SD or740, a second DTI750, a light shielding film760, and a metal shield770. The elements510,520,530,540,545,544,560, and570illustrated inFIG. 4have been described with reference toFIG. 3. The gate540of the overflow transistor OX, the gate542of the storage transistor SX, and the gate544of the transfer transistor TX may have at least one vertical gate structure.

The gate540of the overflow transistor OX may include a planar gate540P parallel to a plane (formed opposite to the second flat layer704in parallel with the second flat layer704) of the semiconductor substrate710and a vertical gate540V extending toward the photo diode PD. For instance, the vertical gate540V may have a structure extending from the planar gate540P toward the photo diode PD. The gate542of the storage transistor SX may include a planar gate542P parallel to the plane of the semiconductor substrate710, a vertical gate542V1extending toward the photo diode PD, and a vertical gate542V2extending toward the storage diode SD. For instance, the vertical gate542V1may have a structure extending from the planar gate542P toward the photo diode PD, and the vertical gate542V2may have a structure extending from the planar gate542P toward the storage diode SD. The gate544of the transfer transistor TX may include a planar gate544P parallel to the plane of the semiconductor substrate710and a vertical gate544V extending toward the storage diode SD. For instance, the vertical gate544V may have a structure extending from the planar gate544P toward the photo diode PD.

The vertical gate structure may be formed using a trench process. The trench process is a process of forming a trench in the semiconductor substrate710with a certain depth. The trench process may be divided into a DTI process providing a relatively deeper trench and an STI process providing a relatively shallower trench. The trench process may also be divided into a back trench process in which a trench is formed starting from the side of the incidence layer705and a front trench process in which a trench is formed starting from the side of the wiring layer720.

The vertical gate structure may be formed using the front trench process. The gates540,542, and544of the respective transistors OX, SX, and TX may be formed using the DTI or STI process according to the vertical depth of the photo diode730and the vertical depth of the storage diode740. The vertical gate structure may also be formed inserted into the photo diode PD or the storage diode SD, as shown inFIG. 4, but the inventive concepts is not limited thereto. The vertical gate structure may be separated from the photo diode PD or the storage diode SD by a predetermined distance in some embodiments.

The vertical gates540V,542V1,542V2, and544V of the gates540,542, and544of the respective transistors OX, SX, and TX are formed to extend toward the photo diode PD or storage diode SD, so that a channel is readily formed between the pixel voltage terminal570and the photo diode PD, between the photo diode PD and the storage diode SD, and between the storage diode SD and the floating diffusion560. As a result, the transfer efficiency of photocharges is increased.

Since the gates540,542, and544of the respective transistors OX, SX, and TX include the vertical gates540V,542V1,542V2, and544V, the photo diode730and the storage diode740may not need to be formed close to a surface (i.e., the surface on which the elements560and570are formed) of the semiconductor substrate710but may be formed in the middle of the semiconductor substrate710. In other words, the gates540,542, and544of the respective transistors OX, SX, and TX need to be close to the photo diode730or the storage diode740for the normal operation of the pixel700-1. Therefore, when the gates540,542, and544of the respective transistors OX, SX, and TX includes only the planar gates540P,542P, and544P, the photo diode730or the storage diode740should be formed in a narrow area corresponding to each of the gates540,542, and544of the respective transistors OX, SX, and TX. However, when the gates540,542, and544of the respective transistors OX, SX, and TX includes the vertical gates540V,542V1,542V2, and544V as shown inFIG. 4, the photo diode730or the storage diode740may be formed across the entire flat area of the photo diode area PA22or the storage diode area SA22.

Accordingly, when the gates540,542, and544of the respective transistors OX, SX, and TX have the vertical gate structure, the maximum number of storable charges, i.e., full well capacity (FWC) and sensitivity of the photo diode730or the storage diode740are increased.

The FWC of the photo diode730may be defined as the product of the volume of the photo diode730and the electric potential of the photo diode730. When the gates540,542, and544of the respective transistors OX, SX, and TX have the vertical gate structure, the volume of the photo diode730increases. At this time, the electric potential, i.e., pinning voltage of the photo diode730may be designed low by allowing the volume of the photo diode730to increase within a range of the FWC required for the normal operation of the pixel10. The operation of the pixel10in association with the low electric potential of the photo diode730will be described with reference toFIGS. 10A through 10Flater.

A gate insulation layer (not shown) may be formed between the gates540,542, and544of the respective transistors OX, SX, and TX and the semiconductor substrate710. The gate insulation layer may be formed of SiO2, SiON, SiN, Al2O3, Si3N4, GexOyNz, GexSiyOz, or a high-dielectric material. The high-dielectric material may be formed by performing atomic layer deposition using HfO2, ZrO2, Al2O3, Ta2O5, hafnium silicate, zirconium silicate, or a combination thereof.

The photo diode730and the storage diode740may be the photo diode PD and the storage diode SD illustrated inFIG. 8. Each of the photo diode730and the storage diode740may be formed as an n-type or p-type region in the well area530using ion implantation. It is assumed that the well area530is a p-type and the photo diode730and the storage diode740are an n-type, for convenience' sake in the description.

In some embodiments, the photo diode730and the storage diode740may be formed by stacking a plurality of doped regions. In this case, a lower doped region may be formed using implantation of n+ ions and an upper doped region may be formed using implantation of n− ions.

The storage diode740may be formed to have a different thickness than the photo diode730, as shown inFIG. 4, thereby facilitating transfer of photocharges stored in the storage diode740. The photo diode730may be formed across most of the photo diode area PA22except for the DTI region510and the second DTI750to obtain a high fill factor. The fill factor may be defined as a ratio of a light receiving area to a pixel area. The higher the fill factor, the higher the light absorptance. The DTI region510may be referred to as a first DTI.

The second DTI750may be formed between the photo diode730and the storage diode740. The second DTI750may have a first length D1that covers the vertical area of the photo diode730and the storage diode740. The inside of the second DTI750may be formed of substantially the same material as the DTI region510using the back trench process.

In other words, the second DTI750may reduce or possibly prevent electrical crosstalk and optical crosstalk between the photo diode730and the storage diode740. In particular, the second DTI750may block incident light passing through the photo diode area PA22, thereby possibly preventing the storage diode740from storing charges other than those transferred from the photo diode730.

The second DTI750may be separated by a second length D2from the surface of the semiconductor substrate710. The second length D2may be a minimum length to form a channel for transfer of charges between the photo diode730and the storage diode740.

The light shielding film760is formed on or above the storage diode740to have an area corresponding to the storage diode740. The light shielding film760may block light incident on the storage diode740through the incidence layer705. The light shielding film760may be formed of, for example, tungsten, but the inventive concepts are not limited thereto.

The metal shield770is formed on the bottom of the gates542and544of the respective transistors SX and TX to have an area corresponding to the gates542and544of the respective transistors SX and TX. The metal shield770may block light that has been reflected from multi-layer conductive lines722toward the storage diode740.

The DTI region510, the second DTI750, the light shielding film760, and the metal shield770may be form a light shielding unit that blocks light incident on the storage diode SD. In other words, light leakage may be reduced or possibly minimized by the DTI region510, the second DTI750, the light shielding film760, and the metal shield770.

For instance, when the pixel array120includes a plurality of rows operated in global shutter mode, a sampling time for accumulated photocharges is different row by row even though an integration time is uniform throughout all rows. When the light shielding unit does not exist, noise occurs in the pixel signals P1through Pm during the sampling time due to light leakage. The light shielding unit reduce or possibly minimizes the light leakage, thereby reducing or possibly preventing noise from occurring due to different sampling times.

The wiring layer720may include the multi-layer conductive lines722. The multi-layer conductive lines722may transmit the control signals OS, SS, TS, RS, and SLS applied to the transistors OX, SX, TX, RX, and SEL or may transmit a signal between the pixel700-1and the outside. The multi-layer conductive lines722may be formed by patterning a conductive material including metal such as copper or aluminum.

As shown inFIG. 4, the pixel700-1may be formed as a backside illumination (BSI) pixel in which the multi-layer conductive lines722are positioned at an opposite side of the semiconductor substrate710to face the incidence layer705. However, the inventive concepts are not limited thereto.

The pixels700-2,700-3, and700-4illustrated inFIGS. 5 through 7are substantially the same as the pixel700-1illustrated inFIG. 4except for several differences. Thus only these differences will be described.

The pixel700-2illustrated inFIG. 5is the cross-section taken along the line A-A′ illustrated inFIG. 3according to some embodiments of the inventive concepts. The gate542of the storage transistor SX may include only the planar gate542P and the vertical gate542V1extending toward the photo diode PD and may not include the vertical gate542V2extending toward the storage diode SD in the pixel700-2, unlike in the pixel700-1illustrated inFIG. 4.

The pixel700-3illustrated inFIG. 6is the cross-section taken along the line A-A′ illustrated inFIG. 3according to some embodiments of the inventive concepts. The gate544of the transfer transistor TX may include only the planar gate544P and may not include the vertical gate544V extending toward the storage diode SD in the pixel700-3, unlike in the pixel700-1illustrated inFIG. 4.

The pixel700-4illustrated inFIG. 7is the cross-section taken along the line A-A′ illustrated inFIG. 3according to some embodiments of the inventive concepts. Each of the gate542of the storage transistor SX and the gate544of the transfer transistor TX may not include the vertical gate542V2or544V extending toward the storage diode SD in the pixel700-4, unlike in the pixel700-1illustrated inFIG. 4.

FIG. 8is a circuit diagram of a pixel550corresponding to the layout500illustrated inFIG. 3. Referring toFIGS. 1 through 8, the pixel550may operate in global shutter mode. The pixel550includes the photo diode PD, the overflow transistor OX, the storage transistor SX, the transfer transistor TX, a boosting capacitor Cb, the reset transistor RX, the source follower SF, and the select transistor SEL.

The photo diode PD accumulates or collects photocharges generated therein response to incident light. The overflow transistor OX is connected between the pixel voltage terminal VP supplying the pixel voltage Vpix and the photo diode PD. The gate OG of the overflow transistor OX is used to possibly prevent charges generated by the photo diode PD from overflowing into the storage diode SD. The overflow transistor OX is turned on or off in response to the overflow control signal OS. The gate540of the overflow transistor OX may be referred to as an overflow gate OG.

For instance, when the intensity of light incident on the pixel550is high (e.g., when the sun or a light is shot, that is, in case of a white level) or when photocharges generated during a time other than the integration time Tint are collected at the photo diode PD, the overflow transistor OX is used to possibly prevent photocharges (e.g., electrons) generated in the photo diode PD from overflowing into the storage diode SD.

In addition, the overflow transistor OX is also used to remove or reset photocharges that have been accumulated at the photo diode PD right before the start of the integration time Tint.

The storage transistor SX is connected between the photo diode PD and the storage diode SD. Charges transferred from the photo diode PD are stored in the storage diode SD through the storage transistor SX. The storage transistor SX is turned on or off in response to the storage control signal SS applied to its gate SG. The gate542of the storage transistor SX may be referred to as a storage gate SG.

The transfer transistor TX is connected between the storage diode SD and the floating diffusion FD. Charges stored in the storage diode SD are stored or accumulated in the floating diffusion FD through the transfer transistor TX. The transfer transistor TX is turned on or off in response to the transfer control signal TS applied its gate TG. The gate544of the transfer transistor TX may be referred to as a transfer gate TG.

The boosting capacitor Cb has a first end connected to the floating diffusion FD and a second end receiving the boosting signal FDB. The boosting capacitor Cb may be charged in response to the boosting signal FDB and may boost the floating diffusion FD to an electric potential higher than the pixel voltage Vpix at the moment the transfer transistor TX is turned on. Although the boosting capacitor Cb is not illustrated inFIGS. 3 through 7, it may be formed around the floating diffusion FD.

The reset transistor RX is connected between the pixel voltage terminal VP supplying the pixel voltage Vpix and the floating diffusion FD. The reset transistor RX may control transmission of photocharges (e.g., electrons) from the floating diffusion FD to the pixel voltage terminal VP in response to the reset control signal RS. In other words, when the reset transistor RX is turned on, the voltage level of the floating diffusion FD may be reset to the pixel voltage Vpix. The gate546of the reset transistor RX may be referred to as a reset gate RG.

The source follower SF is connected between the pixel voltage terminal VP supplying the pixel voltage Vpix and the select transistor SEL. The source follower SF operates based on a voltage level determined by charges at the floating diffusion FD. The gate548of the source follower SF may be referred to as a source follower gate SFG.

The pixel voltage Vpix is applied in common to the overflow transistor OX, the reset transistor RX, and the source follower SF in the embodiments illustrated inFIG. 8, for convenience' sake in the description. However, operating voltages respectively applied to the overflow transistor OX, the reset transistor RX, and the source follower SF may be designed to be different from one another.

The select transistor SEL may output an output signal (e.g., an analog pixel signal) of the source follower SF to a column line in response to the selection control signal SLS. The gate550of the select transistor SEL may be referred to as a select gate SELG.

FIG. 9is a timing chart showing the operation of the pixel550illustrated inFIG. 8.FIGS. 10A through 10Fare electric potential diagrams at different time points illustrated inFIG. 9. Referring toFIGS. 1 through 10F, the operation of the pixel550in accordance with the control signals OS, RS, SS, TS, FDB, and SLS illustrated inFIG. 8will be described with reference toFIG. 9.

The electric potential diagrams illustrated inFIGS. 10A through 10Fshow electric potential of the overflow gate OG, the photo diode PD, the storage gate SG, the storage diode SD, the transfer gate TG, the floating diffusion FD, and the reset gate RG. The lower the arrow of the electric potential runs, the higher the electric potential.

The overflow control signal OS transits to a high level at a time point T1. As the overflow control signal OS transits to the high level, charges in the photo diode PD are discharged to the pixel voltage terminal VP so that the photo diode PD is reset. At this time, the efficiency of photocharge transfer from the photo diode PD to the pixel voltage terminal VP increases due to the vertical gate540V in the gate540of the overflow transistor OX, so that the complete reset of the photo diode PD is accomplished. After the reset of the photo diode PD is completed at a time point T1′ when the overflow control signal OS transits to a low level, accumulation of photocharges in the photo diode PD starts.

FIG. 10Ais the electric potential diagram obtained between the time points T1and T1′. As the overflow control signal OS transits to the high level, the charges in the photo diode PD are discharged to the pixel voltage terminal VP having the pixel voltage Vpix.

FIG. 10Bis the electric potential diagram obtained between time points T1′ and T2. As the overflow control signal OS transits to the low level, accumulation of photocharges in the photo diode PD starts. During the integration time Tint or first period defined by time points T1′ and T4, the photo diode PD accumulates charges corresponding to incident light.

The boosting signal FDB transits to a high level at the time point T2. As the boosting signal FDB transits to the high level, the boosting capacitor Cb may be charged during a period from the time point T2to a time point T2′.

The transfer control signal TS transits to a high level at a time point T3. The boosting capacitor Cb may boost the floating diffusion FD to a boosting potential Vb higher than the pixel voltage Vpix the moment the transfer transistor TX is turned on. The charges of the storage diode SD are discharged to the floating diffusion FD so that the storage diode SD is reset. Since the difference between an electric potential Vs of the storage diode SD and an electric potential of the floating diffusion FD increases due to the boosting, transfer efficiency also increases.

FIG. 10Cis the electric potential diagram obtained between time points T3and T3′. The charges in the storage diode SD are discharged to the floating diffusion FD having the boosting potential Vb.

The storage control signal SS transits to a high level at the time point T4. When storage control signal SS transits to the high level, an electric potential of the storage diode SD is temporarily increased to an electric potential Vs' due to boosting effect between the storage diode SD and the storage transistor SX. In addition, due to the vertical gate542V1of the gate542of the storage transistor SX and the photo diode730formed deep in the semiconductor substrate710, as shown inFIGS. 4 through 7, the electric potential Vp of the photo diode730may be designed lower than the electric potential Vs of the storage diode SD. As a result, the electric potential difference between the photo diode PD and the storage diode SD increases, so that charges accumulated in the photo diode PD may be completely transferred to and stored in the storage diode SD through the storage transistor SX.

FIG. 10Dis the electric potential diagram obtained between time points T4and T4′. The charges accumulated at the photo diode PD having the low electric potential Vp are completely transferred to and stored in the storage diode SD temporarily having the high electric potential Vs' through the storage transistor SX.

The overflow control signal OS and the reset control signal RS transit to the high level at a time point T5. As the overflow control signal OS transits to the high level, charges in the photo diode PD are discharged to the pixel voltage terminal VP, so that the charges in the photo diode PD do not overflow into the storage diode SD during a period from the time point T5to a time point T9.

As the reset control signal RS transits to the high level, charges at the floating diffusion FD, which have been transferred from the storage diode SD, are discharged to the pixel voltage terminal VP.

FIG. 10Eis the electric potential diagram obtained between time points T5and T5′. As the overflow control signal OS and the reset control signal RS transit to the high level, the photo diode PD and the floating diffusion FD are reset. The select control signal SLS transits to a high level at a time point T6and the reset control signal RS transits to a low level at the time point T5′.

A reset signal is sampled at a time point Trs. The reset signal may be a pixel signal output according to a voltage level of the floating diffusion FD right after the floating diffusion FD is reset to the pixel voltage Vpix. The sampling of the reset signal may be carried out by the CDS block150and the comparator block152.

The boosting signal FDB transits to a high level at a time point T7. As the boosting signal FDB transits to the high level, the boosting capacitor Cb may be charged during a period between time points T7and T7′.

The transfer control signal TS transits to the high level at a time point T8. The boosting capacitor Cb may boost the floating diffusion FD to the boosting potential Vb higher than the pixel voltage Vpix the moment the transfer transistor TX is turned on. As the transfer control signal TS transits to the high level, charges stored in the storage diode SD are transferred to the floating diffusion FD. As described above, since the difference between the electric potential Vs of the storage diode SD and the electric potential of the floating diffusion FD increases due to the boosting, transfer efficiency also increases.

FIG. 10Fis the electric potential diagram obtained between time points T8and T8′. The charges stored in the storage diode SD may be completely transferred to and accumulated at the floating diffusion FD having the boosting potential Vb.

An image signal is sampled at a time point Tss. The image signal may be a pixel signal output according to a voltage level of the floating diffusion FD right after the charges are completely transferred from the storage diode SD to the floating diffusion FD. The sampling of the image signal may be carried out by the CDS block150and the comparator block152. When the select control signal SLS transits to a low level at the time point T9, the sampling operation on the floating diffusion FD is completed.

The gates OG and SG of the transistors OX and SX controlling transfer of charges from the photo diode PD are formed as vertical gates in the image sensor110according to some embodiments of the inventive concepts, so that the FWC of the photo diode PD and the charge transfer efficiency are increased. Due to the increased FWC and charge transfer efficiency, the sensitivity of the image sensor110increases and the occurrence of noise decreases.

Since the electric potential Vp of the photo diode730can be designed low, the pixel voltage Vpix corresponding to an electric potential used by the reset transistor RX to reset the floating diffusion FD can be designed lower than a usual voltage (e.g., the power supply voltage VDD) within a certain range of transfer efficiency. In addition, since the electric potential Vp of the photo diode730can be designed low, the pixel voltage Vpix corresponding to an electric potential used by the overflow transistor OX to reset the photo diode PD can be designed lower than the usual voltage (e.g., the power supply voltage VDD).

Consequently, power consumption of the image sensor110is decreased since the electric potential of the photo diode PD and the voltage Vpix applied to the pixels10are designed low.

FIG. 11is a block diagram of an electronic system800including an image sensor according to some embodiments of the inventive concepts. Referring toFIGS. 1 and 11, the electronic system800may be implemented as a data processing device, such as a cellular phone, a PDA, a PMP, an internet protocol television (IPTV), or a smart phone, which can use or support mobile industry processor interface (MIPI). The electronic system800includes the image sensor110, an application processor810, and a display850.

A camera serial interface (CSI) host812in the application processor810may perform serial communication with a CSI device841in the image sensor110through CSI. An optical deserializer DES and an optical serializer SER may be included in the CSI host812and the CSI device841, respectively.

A display serial interface (DSI) host811in the application processor810may perform serial communication with a DSI device851in the display850through DSI. An optical serializer SER and an optical deserializer DES may be included in the DSI host811and the DSI device851, respectively.

The electronic system800may also include a radio frequency (RF) chip860communicating with the application processor810. A physical layer (PHY)813in the application processor810and a PHY861in the RF chip860may communicate data with each other according to MIPI DigRF.

The electronic system800may further include a global positioning system (GPS)820, a storage870, a microphone (MIC)880, a dynamic random access memory (DRAM)885, and a speaker890. The electronic system800may communicate using worldwide interoperability for microwave access (Wimax)891, wireless local area network (WLAN)893, and/or ultra wideband (UWB)895.

FIG. 12is a block diagram of an electronic system900including an image sensor according to some embodiments of the inventive concepts. Referring toFIGS. 1 and 12, the electronic system900may include the image sensor110, a processor910, a memory920, a display unit930, and an interface940.

The processor910may control the operation of the image sensor110. The processor910may process pixel signals output from the image sensor110and generate image data.

The memory920may store a program for controlling the operation of the image sensor110and may store image data generated by the processor910. The processor910may execute the program stored in the memory920. The memory920may be formed with volatile or non-volatile memory.

The interface940may be formed for the input and output of image data. The interface940may be implemented as a wireless interface.

The inventive concepts can also be embodied as computer readable codes on a computer readable recording medium. The computer readable recording medium is any data storage device that can store data which can be thereafter read by a computer system. Examples of the computer readable recording medium include read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tapes, floppy disks, and optical data storage devices.

The computer readable recording medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion. Also, functional programs, codes, and code segments for accomplishing the inventive concepts can be easily construed by programmers skilled in the art to which the inventive concepts belong.

As described above, according to some embodiments of the inventive concepts, a gate of a certain transistor is formed as a vertical gate in a pixel, thereby increasing the sensitivity of the pixel and decreasing noise in pixel signals in an image sensor and an image processing system. In addition, an electric potential of a photo diode of the pixel and a voltage applied to the pixel are designed low, thereby decreasing power consumption.