PCB based semiconductor package having integrated electrical functionality

A semiconductor package includes a metal baseplate, a semiconductor die having a reference terminal attached to the baseplate and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the baseplate and a second side facing away from the baseplate. The multilayer circuit board includes a plurality of interleaved signal and ground layers. One of the signal layers is at the second side of the multilayer circuit board and electrically connected to the RF terminal of the semiconductor die. One of the ground layers is at the first side of the multilayer circuit board and attached to the metal baseplate. Power distribution structures are formed in the signal layer at the second side of the multilayer circuit board. RF matching structures are formed in a different one of the signal layers than the power distribution structures.

TECHNICAL FIELD

The present application relates to RF power packages, in particular PCB (printed circuit board) based packages RF power applications.

BACKGROUND

Ceramic air-cavity and plastic air-cavity/overmold packages are widely used for RF/microwave discrete power transistors. Both types of packages provide a reliable and easy-to-handle handle mechanical design. However, ceramic air-cavity and plastic air-cavity/overmold packages are difficult to design in an electrical sense due to their stack-up and predetermined physical dimensions.

SUMMARY

According to an embodiment of a semiconductor package, the semiconductor package comprises a metal baseplate having a die attach region and a peripheral region, a transistor die having a reference terminal attached to the die attach region and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the peripheral region and a second side facing away from the baseplate, the multilayer circuit board comprising a plurality of interleaved signal and ground layers. A first one of the signal layers is at the second side of the multilayer circuit board and electrically connected to the RF terminal of the transistor die. A first one of the ground layers is below the first signal layer. A second one of the signal layers is below the first ground layer and electrically connected to the first signal layer by insulated vias which extend through the first ground layer. A second one of the ground layers is at the first side of the multilayer circuit board and attached to the metal baseplate.

According to another embodiment of a semiconductor package, the semiconductor package comprises a metal baseplate, a semiconductor die having a reference terminal attached to the baseplate and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the baseplate and a second side facing away from the baseplate. The multilayer circuit board comprises a plurality of interleaved signal and ground layers. One of the signal layers is at the second side of the multilayer circuit board and electrically connected to the RF terminal of the semiconductor die. One of the ground layers is at the first side of the multilayer circuit board and attached to the metal baseplate. Power distribution structures are formed in the signal layer at the second side of the multilayer circuit board. RF matching structures are formed in a different one of the signal layers than the power distribution structures.

According to an embodiment of a semiconductor assembly, the semiconductor assembly comprises a substrate and a semiconductor package attached to the substrate. The semiconductor package comprises a metal baseplate, a semiconductor die having a reference terminal attached to the baseplate and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the baseplate and a second side facing away from the baseplate. The multilayer circuit board comprises a plurality of interleaved signal and ground layers. One of the signal layers is at the second side of the multilayer circuit board and electrically connected to the RF terminal of the semiconductor die. One of the ground layers is at the first side of the multilayer circuit board and attached to the metal baseplate. Power distribution structures are formed in the signal layer at the second side of the multilayer circuit board. RF matching structures are formed in a different one of the signal layers than the power distribution structures.

DETAILED DESCRIPTION

Described next are embodiments of a PCB (printed circuit board) based power semiconductor package in which the package also is treated as part of the electrical design of the system instead of a just a mechanical component. Doing so provides flexibility into the design, improves integration, and enhances performance while providing a more compact physical size. By combining the concept of a discrete package with a sub-system module in an electrical design sense, design flexibility is still realized while also boosting the electrical performance of the system and reducing the final circuit physical dimensions.

The embodiments described herein provide a multilayer organic PCB based package for high design integration. The PCB has a minimum of four layers, two of which are ground layers. Signal and ground layers can be interleaved to reduce interference and improve performance. RF matching and power distribution and combining structures can be formed in one or more signal layers of the PCB. For example, integrated harmonics resonators for providing harmonics termination can be formed in one or more of the signal layers of the PCB to provide high efficiency power amplifier class functionality. A balanced power combiner network can be formed in one or more of the signal layers of the PCB to provide uniform power distribution across a large die periphery or large pad dimension. In addition or alternatively, the PCB based package can have interleaved ground-signal-ground pad connections for providing a high frequency and high reliability electrical contact between the PCB based package and another circuit board.

FIG. 1illustrates a partial sectional view of a semiconductor package, according to an embodiment. The power semiconductor package comprises a metal baseplate100having a die attach region102and a peripheral region104, a transistor die106attached to the die attach region102of the baseplate100, a multilayer circuit board108such as a PCB for providing electrical connections to the transistor die106, and an optional lid110for enclosing the transistor die106. The baseplate100is made of an electrically and thermally conductive material such as Cu, CPC (copper, copper-molybendum, copper laminate structure), CuW, etc. In some cases, the transistor die106attached to the baseplate100is a power transistor die such as an RF amplifier die. For example, the transistor die106can be an LDMOS (laterally diffused metal oxide semiconductor), vertical power MOSFET (metal oxide semiconductor field effect transistor) or GaN RF power transistor die. The transistor die106has a reference terminal112such as a source or emitter terminal attached to the die attach region102and an RF terminal114such as a drain or collector terminal facing away from the baseplate100. The control (gate) terminal of the transistor die is out of view inFIG. 1. More than one transistor die can be attached to the baseplate100e.g. in the case of a Doherty amplifier in which a main and one or more peaking amplifiers can be attached to the baseplate100.

In general, the multilayer circuit board108has a first side116attached to the peripheral region104of the baseplate100and a second side118facing away from the baseplate100. The multilayer circuit board108extends beyond an exterior sidewall120of the baseplate100for attachment to another circuit board122. The other circuit board122belongs to a sub-system or system that incorporates the semiconductor package. This circuit board122can have a recessed region for receiving the baseplate100of the semiconductor package. A metal slug124can be disposed in the recess for enhancing the thermal and electrical interface with the baseplate100of the semiconductor package. A heatsink126comprising e.g. aluminum of copper can be attached to the backside128of the additional circuit board122.

The part of the multilayer circuit board108which extends beyond the exterior sidewall120of the baseplate100is attached to the front side130of the other circuit board122. The multilayer circuit board108of the semiconductor package comprises a plurality of interleaved signal and ground layers. The example shown inFIG. 1has four layers: two ground layers132,134and two signal layers136,138which are interleaved with one another. In general, the multilayer circuit board108can have two or more signal layers and two or more ground layers. The bottommost layer132is a ground layer having ground pads140which are attached to both the baseplate100of the semiconductor package and to the other circuit board122. That is, the ground pads140of the bottommost layer132of the multi-layer circuit board108are attached to the metal baseplate100and also extend beyond the exterior sidewall120of the baseplate100for attachment to the other circuit board122.

The uppermost layer138of the multilayer circuit board108forms the main RF signal layer of the semiconductor package and is electrically connected to the RF terminal114of the transistor die106by one or more electrical conductors142such as one or more bond wires, ribbons, a metal clip, etc. The main RF signal layer138also can be electrically connected to the front side130of the other circuit board122through insulated signal vias144which extend through the multilayer circuit board108to signal pads146formed in the bottommost ground layer132of the multilayer circuit board108. The signal pads146at the bottommost ground layer132are positioned beyond the exterior sidewall120of the baseplate100and separated from the ground pads140at the bottommost layer132to ensure proper electrical isolation.

An intermediary ground layer134is disposed below the main RF signal layer138, and an intermediary signal layer136is disposed below this ground layer134and above the bottommost ground layer132. The intermediary signal layer136is electrically connected to the main RF signal layer138by insulated signal vias148which extend through the ground layer134interposed between the intermediary signal layer136and the main RF signal layer138. In a similar manner, the ground layers132,134are electrically connected by insulated ground vias150. The multilayer circuit board108can have additional interleaved ground and signal layers if desired.

FIG. 2Aillustrates a sectional view of an embodiment of one of the insulated signal vias144for electrically connecting the uppermost signal layer138of the multilayer circuit board108over the entire thickness of the multilayer circuit board108. According to this embodiment, the insulated signal via144comprises a cap200such as a copper cap in the case of copper vias and a top pad202adjacent the cap200in the uppermost signal layer138. A plated-through hole204extends vertically through the multilayer circuit board108, optionally contacting one or more intermediary signal layers136via a corresponding buried pad202. The bottom of the insulated signal via144comprises a cap206such as a copper cap in the case of copper vias and a bottom pad208formed in the bottommost ground layer132. The bottom cap206and pad208are electrically insulated from the ground metal tracks/pads of the bottommost ground layer132by a dielectric material210of the multilayer circuit board108such as polytetrafluoroethylene, FR-1, FR-2, FR-3, FR-4, FR-5, FR-6, G-10, CEM-1, CEM-2, CEM-3, CEM-4, CEM-5, etc. A non-conductive resin212can fill the plated-through holes204. The ground vias150shown inFIG. 1can have the same or similar construction as shown inFIG. 2A.

FIG. 2Billustrates a sectional view of an embodiment of one of the insulated signal vias148for electrically connecting the uppermost signal layer138of the multilayer circuit board108to an intermediary signal layer136buried in the multilayer circuit board108, according to an embodiment. According to this embodiment, the insulated signal via148comprises a cap220such as a copper cap in the case of copper vias and a top pad222adjacent the cap220in the uppermost signal layer138. A plated blind hole224vertically extends partly through the multilayer circuit board108to the intermediary signal layer136. The bottom of the insulated signal via148comprises a pad226which contacts a signal metal track of the intermediary signal layer136. The plated blind hole224is electrically insulated from the ground layer134in interposed between the uppermost signal layer138and the intermediary signal layer136by a dielectric material228such as the kind described above in connection withFIG. 2A.

By utilizing such a multi-layer circuit board construction, optimized electrical connections to each transistor die106included in the semiconductor package can be realized. For example in the case of the transistor die106being an RF high power amplifier die, the electromagnetic field propagation from the multilayer circuit board108of the semiconductor package to the subsystem/system circuit board122is critical for the high frequency performance of the power amplifier. The electromagnetic field propagation can be optimized to achieve high performance at high frequency. For example, the inductance of the signal vias144,148is reduced with the presence of the ground vias150. The ground vias150provide a smooth vertical transition for the RF return path, reducing the overall loop inductance of the signal vias144,148which in turn reduces return losses. The RF signal current path is highlighted with right-facing arrows and the return path is highlighted with left-facing arrows inFIG. 1.

FIG. 3Aillustrates an embodiment of the interface between the multi-layer circuit board108of the semiconductor package and the subsystem/system circuit board122. The dielectric material of the multi-layer circuit board108is not shown inFIG. 3so that the signal and ground metal tracks, and the signal and ground vias are each at least partly visible. According to this embodiment, the uppermost signal layer138of the multi-layer circuit board108comprises a plurality of signal metal tracks300such as microstrip lines which are electrically connected to respective signal pads146(out of view inFIG. 3A) at the bottom side of the multilayer circuit board108by insulated signal vias302which extend through the multilayer circuit board108. Ground pads140(also out of view inFIG. 3A) at the bottom side of the multilayer circuit board108are separated from and interleaved with the signal pads146. The ground pads140are electrically connected to the ground layers132,134of the multi-layer circuit board108by insulated ground vias304which extend through the multilayer circuit board108. The ground layers132,134can each comprise a single metal sheet306as shown inFIG. 3, however, other configurations are possible such as multiple ground metal tracks such as multiple sheets or striplines. In addition or alternatively, ground metal tracks308can partly extend on the uppermost signal layer138in some embodiments. In each case, the subsystem/system circuit board122has interleaved ground and signal pads310,312which correspond to the interleaved ground/signal pad configuration of the multi-layer circuit board108of the semiconductor package. The circuit boards108,122can be soldered to one another at these connection points, e.g. by respective solder joints152,154,156as shown inFIG. 1.

FIG. 3Bshows the subsystem/system circuit board122prior to placement and attachment of the semiconductor package. The subsystem/system circuit board122can have a recessed region314for receiving the baseplate100of the semiconductor package. The part of the multilayer circuit board108which extends beyond the exterior sidewall120of the baseplate100is shown inFIG. 3Aand is attached to the front side of the subsystem/system circuit board122by the interleaved ground and signal pads310,312. The subsystem/system circuit board122can include insulated ground vias316for connecting to one or more other ground layers of the subsystem/system circuit board122. Similar via connections can be made to the signal metal tracks of the system/system circuit board122, but are not shown for ease of illustration. The interleaved ground-signal-ground configuration shown inFIGS. 3A and 3Bprovides for an efficient vertical propagation of the electric field between the multi-layer circuit board108of the semiconductor package and the subsystem/system circuit board122.

In addition or alternatively to the interleaved ground-signal-ground configuration explained above, RF matching and power distribution and combining structures can be formed in the signal layers136,138of the multi-layer circuit board108of the semiconductor package. This way, the multi-layer circuit board108can incorporate both mechanical and electrical functions into the design of the semiconductor package.

FIG. 4illustrates a high-level schematic representation of different electrical functions at the output side of the semiconductor package which can be incorporated into the multi-layer circuit board108. A single transistor component having a source terminal (S), drain terminal (D) and gate terminal (G) is shown, which can represent one or more physical transistor dies. In this example, the source terminal of the power transistor is electrically connected to ground through the bottommost layer132of the multi-layer circuit board108and the drain terminal of the power transistor is electrically connected to the uppermost signal layer138of the multi-layer circuit board108as previously described herein. The multi-layer circuit board108has one or more additional signal layers136interposed between the uppermost signal layer138and the bottommost ground layer132. An additional ground layer134is interposed between vertically adjacent signal layers136,138also as previously described herein. RF matching and power distribution and combining structures are formed in the signal layers136,138of the multi-layer circuit board108.

For example, the electrical connection between the drain terminal of the power transistor and the uppermost signal layer138of the multi-layer circuit board108is represented by inductance L1inFIG. 4. The uppermost signal layer138of the multi-layer circuit board108can include a power distribution network represented by transmission line TL1. The power distribution network can be coupled to a harmonic termination resonator configured to capture spurious harmonics present in a signal at the RF terminal (e.g. drain) of the transistor. The harmonic termination resonator can include a 2ndorder harmonic termination resonator represented by transmission line TL2, a 3rdorder harmonic termination resonator represented by transmission line TL3, etc. The harmonic termination resonator can be formed in a different signal layer of the multi-layer circuit board108than the power distribution network. In addition to the power distribution network, the uppermost signal layer138can also include a balanced power combiner represented by transmission line TL4for combining the output of the harmonic termination resonator. The electrical connection from the multi-layer circuit board108of the semiconductor package to the subsystem/system circuit board122is represented by inductance L2. The RF matching and power distribution and combining structures described above can be formed in the signal layers136,138of the multi-layer circuit board108.

FIG. 5illustrates a section view of the multi-layer circuit board108of the semiconductor package, with various schematic overlays showing exemplary types of RF matching and power distribution and combining structures which can be formed in the signal layers136,138of the multi-layer circuit board108. For example, a power combiner network (A) and integrated passive components such as output capacitors (B1, B2) and inductors (C1, C2, C3, C4) can be formed in metal tracks which are routed on the uppermost layer138of the multi-layer circuit board108. The integrated passive components form a quasi-lumped transmission line device.

Integrated harmonic termination structures can be formed in one or more signal layers136below the uppermost signal layer138of the multi-layer circuit board108for capturing spurious harmonics present in a signal at the RF terminal of the transistor. For example, an open stub resonator (D1) with an electrical length equal to a quarter wavelength at 2fo (2ndharmonic termination) or at 3fo (3rdharmonic termination), a quasi-lumped resonator (D2), a radial stub resonator (D3), a square-open-loop-resonator (D4), a folded arm square-open-loop-resonator (D5), a meandering line square-open-loop-resonator (D6), a dual-mode square-open-loop-resonator (D7), etc. can be formed in one or more intermediary signal layers136of the multi-layer circuit board108.

In one example, a square-open-loop-resonator can be used to design a quasi-elliptic low pass filter at the output with a high rejection at 2fo, allowing for an increase in the bandwidth of the power amplifier compared to a standard open stub resonator. Still other harmonic termination resonator types and configurations can be formed in the signal layer(s)136below the uppermost signal layer138of the multi-layer circuit board108.

An impedance transformation network can be formed in the same or different intermediary signal layer as the harmonic termination resonator. The impedance transformation network is configured to transform a lower impedance at the RF terminal of the transistor to a higher impedance. In one embodiment, the impedance transformation network comprises a radial stub (D3) formed in one of the signal layers136,138. A ground layer134is interposed between vertically adjacent signal layers136,138as previously described herein.

To achieve high power output, a wide finger length periphery is typically used for the transistor die106. This means a large (wide) transistor die size. For example, a wide finger length periphery can be realized by a parallel arrangement of sub-unit cells each having a pre-defined periphery length for the same transistor die106. The drain bond pad of a conventional transistor die is typically connected to a wide lead, resulting in high current density only on the edge of the lead which implies an unbalanced amplitude and phase shift between the unit cells of the same transistor die.

FIG. 6schematically illustrates an embodiment of the multi-layer circuit board108of the semiconductor package, implemented at the output side of the semiconductor package with a power distribution network400and a balanced power combiner402formed in the uppermost signal layer138of the multi-layer circuit board108. In this example, the transistor die106is shown with eight unit cells (1-8). Each unit cell contributes a portion of the overall transistor die signal capacity. The outputs of the unit cells are arranged in parallel. The uppermost signal layer138of the multi-layer circuit board108includes a separate metal signal track (8*Zi) for each unit cell output. The unit cell outputs can be electrically connected to the respective metal signal tracks by one or more electrical conductors such as one or more bond wires, ribbons, a metal clip, etc. In each case, the power distribution network400continues to fan in at different levels (e.g. from 8 tracks, to 4 tracks, to 2 tracks in this example), the metal signal tracks (X*Zi) in each level doubling in width from the previous level. The balanced power combiner402distributes current equally in amplitude and phase at each metal track (X*Zi) of the power distribution network400. InFIG. 6, Zi represents the impedance looking into each unit cell of the transistor die106and Zo represents the impedance to which the output of the semiconductor package is to be matched (50Ω in this example).

FIG. 7illustrates a top down plan view of the uppermost signal layer138of the multi-layer circuit board108, implemented with the power distribution network400and the balanced power combiner402schematically shown inFIG. 6. The metal signal tracks formed in the uppermost signal layer138to realize the power distribution network400and the balanced power combiner402can comprise patterned copper metallization404in some embodiments.

FIG. 8schematically illustrates an embodiment of an intermediary signal layer136of the multi-layer circuit board108, implemented with a harmonic termination resonator structure500. The intermediary signal layer136is disposed below the uppermost signal layer138of the multi-layer circuit board108. In this example, metal signal tracks are arranged to form a 2ndharmonic termination structure502and a 3rdharmonic termination structure504in the intermediary signal layer136. A ground layer134can be interposed between the intermediary signal layer136with the harmonic termination resonator structure500and the uppermost signal layer138. The harmonic termination resonator structure500can be electrically connected at one end to the power distribution network structure400formed in the uppermost signal layer138by a first group of insulated signal vias (not shown inFIG. 8), and electrically connected at another end to the balanced power combiner402formed in the uppermost signal layer138by a second group of insulated signal vias (also not shown inFIG. 8).

The harmonic termination resonator structure500is formed a different signal layer136of the multi-layer circuit board108than the power distribution network400and balanced power combiner402so as to reduce unwanted parasitic inductive or electrical coupling between the RF matching components and the harmonic termination resonator structure500which in turn reduces losses due to the parasitic coupling effect. The harmonic termination resonator structure500can have a stripline configuration as shown inFIG. 8so as to have a well-controlled dielectric constant, meaning that the harmonic termination resonators502,504have a controlled electrical length and a very precise resonance frequency. In addition, striplines are well shielded by overlying and underlying ground plane layers.

FIG. 9illustrates an embodiment of the semiconductor package with a power distribution network600, a balanced power combiner602and a harmonic termination resonator604e.g. of the kind described above, formed in the multi-layer circuit board108at the output side of the semiconductor package. Several electrical conductors606connect the RF output terminal of a semiconductor die608to a first plurality of signal metal tracks610formed in the uppermost signal layer138of the multi-layer circuit board108. These signal metal tracks610form the power distribution network600which distributes power across the width (W) of the transistor die608. An intermediary signal layer136disposed below the uppermost signal layer138comprises a plurality of signal metal tracks612which form the harmonic termination resonator604.

The uppermost signal layer138also comprises a second plurality of signal metal tracks614separate from the signal metal tracks610which form the power distribution network600. These additional signal metal tracks614of the uppermost signal layer138form the balanced power combiner602. The signal metal tracks612of the intermediary signal layer136which form the harmonic termination resonator604are electrically connected to respective ones of the first signal metal tracks610which form the power distribution network600by a first group of insulated signal vias616, and to respective ones of the second signal metal tracks614which form the balanced power combiner602by a second group of insulated signal vias618. The intermediary ground layer134interposed between the uppermost signal layer138and the intermediary signal layer136and the dielectric material of the multi-layer circuit board108are not shown inFIG. 9so that the signal metal tracks and corresponding signal vias are at least partly visible.

The uppermost signal layer138can further comprise a plurality of ground metal tracks620separate from the first and second signal metal tracks610,614which form the power distribution network600and the balanced power combiner602, respectively. The signal metal tracks614which form the balanced power combiner602and the ground metal tracks620of the uppermost signal layer138can be interleaved at the top side of the multilayer circuit board108as shown inFIG. 9. The ground metal tracks620of the uppermost signal layer138are electrically connected to the bottommost ground layer132at the bottom side of the multilayer circuit board108by insulated ground vias622which extend through the multilayer circuit board108. The signal metal tracks614which form the balanced power combiner602can be electrically connected to respective signal pads624at the bottom side of the multilayer circuit board108by insulated signal vias626which extend through the multilayer circuit board108. The signal pads626and ground pads628at the bottom side of the multilayer circuit board108are separated from and interleaved with each other. As such, the output part of the multi-layer circuit board108to be attached to a subsystem/system circuit board630can have an interleaved ground-signal-ground configuration (GND/SIG/GND/SIG/GND) e.g. as previously described herein in connection withFIGS. 3A and 3B. The subsystem/system circuit board630has the same interleaved ground-signal-ground configuration (GND/SIG/GND/SIG/GND) as the output side of the multi-layer circuit board108.

FIG. 10illustrates a high-level representation of different electrical functions at the input side of the semiconductor package which can be incorporated into the multi-layer circuit board. A single transistor component having a source terminal (S), drain terminal (D) and gate terminal (G) is shown, which can represent one or more physical transistor dies. In this example, the source terminal of the power transistor is electrically connected to ground through the bottommost layer132of the multi-layer circuit board108and the gate terminal of the power transistor is electrically connected to the uppermost signal layer138of the multi-layer circuit board108. The multi-layer circuit board108has one or more additional signal layers136interposed between the uppermost signal layer138and the bottommost ground layer132. An additional ground layer134is interposed between each signal layer136,138also as previously described herein. RF matching and power distribution and combining structures are formed in the signal layers136,138of the multi-layer circuit board at the input side of the semiconductor package.

For example, an integrated matching component such as a radial stub Stub1 can be formed in an intermediary signal layer136below the uppermost signal layer138of the multi-layer circuit board108. The integrated matching component provides impedance matching between the gate of the transistor and the subsystem/system board. The integrated impedance matching component is connected to the subsystem/system board through a transition represented by inductance L3which corresponds to the inductance of the physical connection between the two boards. The uppermost signal layer138of the multi-layer circuit board108has a balanced power combiner and power distribution network schematically represented by transmission line TL1. The power combiner and power distribution network can be disposed in the same signal layer138which is different than the signal layer136which includes the integrated impedance matching component.

The power combiner is electrically connected to the integrated matching component at one end and to the power distribution network at the other end. The opposite end of the power distribution network is electrically connected to the gate terminal of the transistor through an input match network. The input match network includes the electrical connections to the gate terminal which are represented by series inductances L1and L2, a shunt capacitor SRC1and a 2ndharmonic termination structure SLC1. The input match network can be integrated into one or more signal layers1326,138of the multi-layer circuit board108or provided as discrete passive components e.g. such as integrated passive devices in the case of the capacitors.

FIG. 11illustrates an embodiment of the semiconductor package with RF matching and power distribution and combining structures e.g. of the kind previously described above in connection withFIG. 10, formed in the multi-layer circuit board108at the input side of the semiconductor package. The input match network is implemented as wire bond connections700and discrete capacitors702according to this embodiment. The input match network connects to the gate terminal704of a transistor die706at one end and to a power distribution network708at the other end. The power distribution network708comprises a first plurality of metal signal tracks710formed in the uppermost signal layer138of the multi-layer circuit board108. A balanced power combiner712is formed by a second plurality of metal signal tracks714formed in the uppermost signal layer138. An integrated impedance matching component formed as a radial stub716is disposed in one of the underlying intermediary signal layers136of the multi-layer circuit board108. The radial stub716is electrically connected to respective ones of the second signal metal tracks714which form the balanced power combiner712by one or more insulated signal vias718. The intermediary ground layer134interposed between the uppermost signal layer138and the intermediary signal layer136with the radial stub716and the dielectric material of the multi-layer circuit board108are not shown inFIG. 11so that the signal metal tracks and corresponding signal vias are at least partly visible.

The uppermost signal layer138can further comprise a plurality of ground metal tracks720separate from the metal tracks714of the balanced power combiner712. The balanced power combiner712and the ground metal tracks720formed in the uppermost signal layer138can be interleaved at the top side of the multilayer circuit board108as shown inFIG. 11. The ground metal tracks720of the uppermost signal layer138can be electrically connected to the bottommost ground layer132at the bottom side of the multilayer circuit board108by insulated ground vias722which extend through the multilayer circuit board108. The balanced power combiner712is electrically connected to a signal pad at the bottom side of the multilayer circuit board108by insulated signal vias724which extend through the multilayer circuit board108. The ground and signal pads (both out of view inFIG. 11) at the bottom side of the multilayer circuit board108are separated from and interleaved with each other. As such, the input part of the multi-layer circuit board108to be attached to a subsystem/system circuit board726can have an interleaved ground-signal-ground configuration (GND/SIG/GND). The subsystem/system circuit board726has the same interleaved ground-signal-ground configuration (GND/SIG/GND) as the input side of the multi-layer circuit board108.