Systems and methods for adaptive equalization control for high-speed wireline communications

Methods and systems for conditioning wireline communications to remove intersymbol interference are provided that used adaptive equalization. The method and systems include using a digital finite state machine to control two feedback loops that adjust the gain and power of the input signal relative to a supplied reference. The eye height of the input signal is conditioned by a gain feedback loop so that signal equalization can be performed in a known state. The digital finite state machine allows the loops to be flexibly run in sequence or concurrently. The adaptation functions can be shut off when adequate signal equalization has been achieve, thus saving power.

BACKGROUND

1. Technical Field

The present disclosure relates to the field of signal conditioning in high-speed wireline communications. More specifically, the present disclosure relates to systems and methods for using adaptive equalization control to condition signals for high-speed wireline communications.

2. Discussion of Related Art

Whenever electrical signals are transmitted over wires, the integrity of the signal can be degraded. The signal that was originally placed on the wire will have some differences from the signal that is received at the other end of the wire. This is due to inherent physical properties of the wire.

In a digital signal, the frequency components of a bit of data can spread apart as the higher and lower frequency components travel at slightly different rates through the wireline. This can cause intersymbol interference (ISI) in which one bit can interfere with the preceding and subsequent bits. In recent years, as data has been required to travel with higher data rates over longer distances of wirelines, the problems of maintaining signal integrity and minimizing ISI have increased.

Several techniques have been developed to deal with ISI. Some of these techniques include, for example, error correction coding, separating signals in time, and using an equalizer. Equalizers can be used in an effort to correct for the distortions caused by the non-uniform frequency response of the wireline. However, the equalizers that have been developed to date have not been satisfactory in every respect.

SUMMARY

Embodiments of a receiver are provided herein for facilitating adaptive equalization control. The receiver includes a variable gain amplifier configured to receive an input signal at a signal input, an equalizer peaking amplifier coupled to an output of the variable gain amplifier, a regulated amplifier coupled to an output of the equalizer peaking amplifier; and an adaptation block coupled to the variable gain amplifier, the equalizer peaking amplifier, and the regulated amplifier.

Embodiments of a method for conditioning transmissions in a high-speed wireline communications are also provided. Such a method may include receiving an input signal at a voltage gain amplifier, providing a reference voltage level. The method may include steps of controlling a voltage gain amplifier with a digital finite state machine, the digital finite state machine controlling the voltage gain amplifier based at least in part on the reference voltage level, and the voltage gain amplifier modifying the input signal; and controlling an equalizer peaking amplifier with a digital finite state machine, the digital finite state machine controlling the equalizer peaking amplifier based at least in part on the reference voltage level, the equalizer peaking amplifier modifying the input signal. In the method, controlling the voltage gain amplifier and controlling the equalizer peaking amplifier are performed to equalize the input signal.

Additionally, embodiments of another method for conditioning transmissions in a high-speed wireline communications are provided. The embodiments may include receiving an input signal at a voltage gain amplifier, controlling the voltage gain amplifier so as to condition an eye height of the input signal to match a reference level, and tuning an equalizer peaking amplifier to control equalizer peaking of the input signal after the input signal has been matched to the reference level.

These and other embodiments will be described in further detail below with respect to the following figures.

In the drawings, elements having the same designation have the same or similar functions.

DETAILED DESCRIPTION

FIG. 1shows a diagram of an adaptively equalized receiver100for conditioning high-speed wireline communication signals according to some embodiments of the present invention. Receiver100includes a variable gain amplifier102that may be configured to receive a data input from a high-speed wireline, for example a Universal Serial Bus (USB) connection or other high speed connection. The output signal from variable gain amplifier102may be coupled to an equalizer peaking amplifier104. The output signal from equalizer peaking amplifier104may be coupled to a regulated amplifier106. Regulated amplifier106may have an output signal that is routed to particular destinations.

FIG. 1also depicts an adaptation block108. Adaptation block108may be coupled to receive signals from equalizer peaking amplifier104and the data output of regulated amplifier106. Adaptation block108may also be coupled to transmit control signals to variable gain amplifier102, equalizer peaking amplifier104, and regulated amplifier106. WhileFIG. 1depicts the signal path as showing variable gain amplifier102first, equalizer peaking amplifier104second, and regulated amplifier106third in the data path, the blocks may be arranged in any order without departing from the scope of the invention.

In operation, embodiments of receiver100as depicted inFIG. 1may receive an incoming high-speed communications signal at the input of variable gain amplifier102. As indicated, application block108may be coupled to variable gain amplifier102so that application block108may send a signal to adjust the gain of variable gain amplifier102. This adjustment may be based on a feedback control loop that includes a generated reference signal. The output of the variable gain amplifier102may be adjusted by equalizer peaking amplifier104so as to substantially restore the original frequency components of the signal to that of the originally sent signal. As such, Equalizing peaking amplifier104may include a series of one or more individual peaking amplifiers such as that described in U.S. Pat. No. 8,081,031 to Han Bi, issued on Dec. 20, 2011, which is herein incorporated by reference in its entirety. Each of the equalizing peak amplifiers may amplify different ranges of signal frequencies.

As shown in the embodiment ofFIG. 1, equalizer peaking amplifier104receives control signals from adaption block108. The control signals from adaption block108may be adapted to control the amplification provided by each of the serially coupled peak amplifiers. Therefore, based on the control signal from adaptation block108, equalizer peaking amplifier104may adjust the frequency response correction applied to data input signal. The adjustments made to equalizer peaking amplifier104may be based on all frequencies contained in the received data signals, and not on a subset of signal frequencies. The adjustment may be based on a feedback loop which includes the output of regulated amplifier106.

FIG. 2depicts an embodiment of adaptively equalized receiver100, which in some embodiments improves signal integrity in high-speed wireline communications. As shown inFIG. 2variable gain amplifier102is coupled to receive the data input signal, an equalizer peaking amplifier104is coupled to receive the signal from amplifier102, and a regulated amplifier106is coupled to receive the signal from equalizer peak amplifier104. Each of variable gain amplifier102, equalizer peaking amplifier104, and regulated amplifier106may be coupled to receive control signals from adaptation block108.

As shown inFIG. 2, adaptive block108includes a digital finite state machine (FSM)202. FSM202may be configured to receive differential error control signals and to output control signals to variable gain amplifier102, equalizer peaking amplifier104, and regulated amplifier106. FSM202may output a gain control signal to variable gain amplifier102, the gain control signal may adjust, by an increase or decrease, the gain applied by variable gain amplifier102to the data input signal. The gain of variable gain amplifier102may be increased or decreased to cause an eye height of the data input signal to be within a desired range or at a desired level. As is well known, an eye pattern or eye diagram is a diagram of a data transmission signal formed on an oscilloscope display where the digital signal is applied to the vertical input and the data rate triggers the horizontal sweep. The variable gain amplifier102may thereby control the low frequency swing of the data input signal by adjusting the eye height of the data input signal.

FSM202may also output a peaking control signal to equalizer peaking amplifier104. The peaking control signal may adjust the amplification of certain frequency ranges present in the input signal. This can, for example, be accomplished by adjusting individual peak amplifiers that are serially coupled in equalizer peak amplifier104. Thus, the equalizer peaking amplifier may adjust components in particular frequency ranges, for example the high frequency components of the data input signal.

As illustrated inFIG. 2, a reference voltage is input to a reference generator204. Further, the output signal from equalizer peaking amplifier104is input to peak detector206. Reference generator204generates reference peak levels while peak detector206determines the peak levels of the signal from equalizing peak amplifier104. A peak level error signal210is determined by convoluting the signals from reference generator204and peak detector206in combiner214. The peak level error signal210is then input to finite state machine202. In some embodiments, peak level error signal210includes a digital up or down signal, instructing FSM202to increase or decrease gain.

As is further shown, the output signal from equalizer peaking amplifier104and the data output signal are input to power rectifier208. Power rectifier208rectifies those signals to determine the average power of the signal from equalizer peaking amplifier104and the data output signal. Those two signals are convoluted in combiner214to generate a peaking error signal212. Peaking error signal212may also be a digital up or down signal indicating to FSM202either to increase or decrease the overall gain of variable gain amplifier102and equalizer peaking amplifier104.

As indicated above, FSM202receives the peak level error signal210and the power output error signal212and determines the gain and peaking control signals to variable gain amplifier102and equalizer peaking amplifier104. FSM202may produce the control signals as part of two feedback loops. In a gain control loop, the signal output from variable gain amplifier102may be received and altered by equalizer peaking amplifier104. The resulting equalized signal may be routed to a peak detector204. Peak detector204may be configured to compare the eye height of the equalized signal with the level of a reference signal.

Therefore, as illustrated inFIG. 2, receiver100includes an automatic peak boosting loop and an automatic gain control. In this control loop, after the equalized signal leaves equalizer peaking amplifier104it may be received at the input of regulated amplifier106. Regulated amplifier106may also receive the same reference voltage that is applied to reference generator204in the automatic gain control loop. The reference voltage may cause the output of regulated amplifier106to have the same swing value as the output of reference generator206. The output of regulated amplifier106may be the data output of system100. Additionally, the output of regulated amplifier106, the regulated signal, may be sent to power rectifier208, which may also receive the equalized signal from the output of equalizer peaking amplifier104. Power rectifier208may detect a power difference between the equalized signal and the regulated signal. In some embodiments power rectifier208may include two separate power rectifiers, one for each of the two signals. The power difference from combiner216may be sent on as a peaking error signal. The peaking error signal may be quantized before transmission to FSM202. FSM202may use the peaking error signal to determine a peaking control signal, which is then sent to equalizer peaking amplifier104. The peaking control signal may cause equalizer peaking amplifier104to adjust so as to control the power of the output signal from regulated amplifier106. This may be accomplished by selectively increasing or decreasing the magnitude of certain frequency components in the signal. This may complete the automatic peak boosting loop.

In both of the above-described loops, FSM202may use one of several locking algorithms in communicating with the variable gain amplifier102and the equalizer peaking amplifier104. FSM202may use a locking algorithm to ensure proper communication with variable gain amplifier102and equalizer peaking amplifier104. In some embodiments, the gain control signal and the peaking control signal may be multi-bit (e.g., 3 bit) signals, or may be a series of multi-bit signals. In some embodiments, the automatic gain control loop (the AGC loop) may operate first, while the automatic peak boosting loop (the boost loop) may operate second. In other embodiments, both the AGC loop and the boost loop may operate concurrently.

As indicated, adaptation block108may include a reference voltage. Additionally, the adaptation block may include a clock signal, a configuration signal, and a control signal. These three signals may be included as inputs to FSM202. In some embodiments, the clock, configuration, and control signals may be the same for the AGC loop and the boost loop. In other embodiments, the clock, configuration, and control signals may be programmable independently for the automatic gain control and automatic peak boosting loops. This may allow greater flexibility to optimize performance of each control loop.

When the eye height of the corrected signal matches that produced by reference generator204and the equalized signal power matches the regulated signal power, adaptation block108may turn off to decrease the power consumption of the adaptive equalization system. However, the gain control and peaking control signals may be maintained even when adaptation block108is shut off.

FIG. 3depicts a flowchart for a method300for conditioning signals transmitted in high-speed wireline communications systems by using adaptive equalization control. Method300may be implemented using an adaptive equalization system such as system100as described above. Those systems will be used herein to provide details regarding the operation of method300. However, method300should not be understood as limited to implementation in those particular systems.

Method300may begin in step302, when the system receives an input signal that may need equalization due to channel-loss introduced intersymbol interference. Step304includes providing a reference voltage to the system. Steps306and308may be performed by finite state machine202. So, in step306, the receiver100may control a voltage gain amplifier using finite state machine202. Finite state machine202may exert control based in part on the provided reference voltage to modify the eye height of the input signal received by the system. In step308, the system may control an equalizer peaking amplifier based in part on the reference voltage to modify the power of the input signal. The system may control the equalizer peaking amplifier with the same finite state machine as used in step308.

Using receiver100as a non-limiting example, method300may begin when a voltage gain amplifier102receives an input signal at its input (step302). The input signal may exhibit a degree of intersymbol interference to be corrected. Adaptation block108may be provided with a reference voltage (step304). The reference voltage may be coupled to a reference generator204that may generate a reference signal. The reference voltage may also be coupled to a regulated amplifier106to regulate its output swing.

Adaptation block108may exert control of voltage gain amplifier102. This may be accomplished through adjustments to an automatic gain control loop. The loop may begin at the output of voltage gain amplifier102which may be routed through an equalizer peaking amplifier104, producing an equalized signal. A peak detector206may detect the difference between an eye height of the equalized signal and the reference voltage.

The difference may be quantized to produce a gain error signal that can be transmitted to an FSM202. FSM202may determine an appropriate gain control signal to transmit to variable gain amplifier102, based on the gain error signal (step306).

System100may also exert control of equalizer peaking amplifier104. This may be accomplished through adjustments to an automatic peak boosting loop. The loop may begin at the output of equalizer peaking amplifier104with the equalized signal. The equalized signal may be routed to a regulated amplifier106and a power rectifier208. The output of regulated amplifier106may also be routed to power rectifier208, where power rectifier208may detect a difference between the regulated and the equalized signals. The difference is quantized and provided to the FSM202. FSM202may then use the quantized difference to determine a peaking control signal, which FSM202may transmit to equalizer peaking amplifier104. Equalizer peaking amplifier104may be adjusted by the peaking control signal to minimize the power difference between the equalized and regulated signals (step308).

FIG. 4depicts a flowchart of a method400for conditioning signals transmitted in high-speed wireline communications systems by using adaptive equalization control. As was the case forFIG. 3, method400may be implemented using an adaptive equalization system such as in receiver100, as described above. While those systems may be used to provide details regarding the operation of method400, the explanatory use of system100herein should not be understood as limiting method400to any particular system.

Method400may begin in step402, when an adaptive equalization system receives an input signal at a voltage gain amplifier. In step404, a peak detector may compare an eye height of the input signal to a generated reference signal. The difference between the two signals may be to create a gain error signal. The gain error signal may be used to provide feedback to the voltage gain amplifier. The system may adjust the voltage gain amplifier so that the eye height of the input signal matches the generated reference signal, in step406.

Method400may continue in step408, when a power rectifier may detect a power difference between an equalized signal with a regulated signal. The difference between the equalized signal and the regulated signal may be used to create a peaking error signal. The peaking error signal may be used by the system to provide feedback to an equalizer peaking amplifier. The equalizer peaking amplifier104may be tuned so that the power of the equalized signal matches the power of the regulated signal, in step410. The tuning of the equalizer peaking amplifier may be performed after the eye height of the input signal has been matched to the reference level.

Using adaptive equalization system100as an example, method400may begin when an input signal transmitted over a high-speed wireline is received by a voltage gain amplifier102(Step402). The signal may be altered and transmitted to an equalizer peaking amplifier104. After the signal has passed through equalizer peaking amplifier104it may be transmitted to a peak detector206. Peak detector206may compare the eye height of the input signal to a reference signal generated from a reference voltage by a reference generator204. The comparison performed by peak detector206may provide a gain error signal. In some embodiments, the gain error signal may be quantized and transmitted to a digital finite state machine, such as FSM202. The gain error signal may be used to produce a gain control signal. In turn, the gain control signal may be transmitted to variable gain amplifier102and may adjust it so that the eye height of the input signal matches the generated reference signal (Step406).

The output of equalizer peaking amplifier104may also be routed to a power rectifier208. Power rectifier208may also receive the output of a regulated amplifier106. Power rectifier208may compare the power of the equalized signal with the power of the regulated signal to determine a power difference (Step408). This power difference may serve as a peaking error signal (Step408). The peaking error signal may, in some embodiments, then be quantized and transmitted to FSM202. FSM202may generate a peaking control signal from the peaking error signal. The peaking control signal may be transmitted to equalizer peaking amplifier104. Equalizer peaking amplifier104may respond by adjusting so that the power of the equalized signal matches the power of the regulated signal (Step410).

After equalizer peaking amplifier104has been properly tuned, the eye height of the input signal will match the reference level, and the power of the equalized and regulated signals will match as well. In these conditions, adaptation block108as seen inFIGS. 1 and 2may shut off to conserve power. In such an instance, the gain control and peaking control signals may be maintained so that the state of adaptive equalization system continues to equalize the input signal. In those embodiments of method400that include quantizing and transmission to FSM202, the gain and peaking control signals may be digital signals of multiple-bit word lengths transmitted in parallel, or a series thereof.

FIGS. 5A and 5Billustrate an embodiment of a loop that is operated by FSM202. In general, FSM202includes two control logic loops. One loop, which may be referred to as an automatic gain control loop, receives signal210and outputs a gain control signal to variable gain amplifier102. The other loop, also referred to as the boost loop, receives signal212and outputs a gain control signal to equalizer peaking amplifier104. In some embodiments, signals210and212are digital signals, either 1 or 0. Signal210, which is the input to the AGC loop, is 1 if the signal from peak detector206is greater than the signal from reference generator204, and 0 if the signal from peak detector206is less than the signal from reference generator204. Similarly, signal212, which is the input signal for the boost loop, is 1 if the regulated signal from regulated amplifier106is greater than the regulated signal from equalizer peaking amplifier104and 0 if the regulated signal from equalizer peaking amplifier104is greater than the regulated signal from regulated amplifier106.

The control algorithm for the AGC loop and the Boost loop are substantially the same. In some embodiments, the algorithm executed by FSM202includes AGC and Boost initial gains and the two loops working in sequence. In some embodiments, the two loops operate simultaneously.FIG. 6Cillustrates the AGC loop and the Boost loop working in sequence.FIG. 7Cillustrates the AGC loop and the Boost loop working simultaneously. FSM202may include a processor that executes code to perform the control algorithm. Alternatively, FSM202may include hardware that performs the steps of the control algorithm.

FIG. 5Aillustrates an embodiment of a control algorithm500that can be executed by FSM202. Control algorithm500can represent either the AGC loop or the Boost loop of FSM202. As shown inFIG. 5A, control algorithm500begins at start502. In start502the loop is initialized by loading an initial gain value and setting a cycle number to zero. Control algorithm500then proceeds to step504where the input signal (signal210or signal212) is sampled. In some embodiments, step504is performed every clock cycle so that an input signal is sampled every clock cycle. In step506, if the input signal is 1, algorithm500proceeds to step508. If the input signal is 0, algorithm500proceeds to step510.

In step508, the algorithm500determines if the gain signal is saturated at a high level. If not, then algorithm500proceeds to step512where the gain signal is incremented by 1. If step508determines that the gain is saturated, then algorithm500proceeds to step514where the gain is not changed.

In step510, algorithm500determines if the gain is saturated at a low level. If not, then algorithm500proceeds to step518where the gain is decremented by 1. If the gain is saturated, the algorithm500proceeds to step516where the gain is not changed.

From steps512,514,516, or518, algorithm proceeds to step520. In step520, algorithm500makes a loop lock condition judgment. Algorithm500saves previous values of the input signal (for example the last six values—last continuous five values and the current value). In some embodiments, if six values are kept, and the last six values are equal to “101010” or “010101” or “100110” or “100101” or “101001” or “011001” or “011010” or “010110” and the current cycle number, which is incremented on each clock cycle, is larger than a set value (for example 12, but any number can be used) then the loop lock condition is considered to be met.

FIG. 5Billustrates the loop lock condition. As shown inFIG. 5B, if the gain remains in a small range (e.g., from g−1 to g+1, where g is a constant) in a multiple of clock cycles, for example six clock cycles, then the loop has converged. If the condition occurs after a larger number of clock cycles, for example 12 clock cycles, then the loop lock may be more reliable. Therefore, in loop520, algorithm500checks for the loop lock condition described above and that the number of cycles has exceed a minimum number before declaring the condition.

If, in step520, algorithm500determines that the loop lock condition is satisfied, then algorithm520proceeds to end equalization524. In step524, an external host may be notified that equalization has ended. The gain is set at its current value for the duration of operation, or until the external host restarts the equalization by returning loop algorithm500to start502.

If, in step520, algorithm500determines that the loop lock condition is not satisfied, then algorithm500proceeds to step522. In step522, if the cycle number has exceed a maximum number, for example 31 cycles, then algorithm500“times out” and proceeds to end equalization524. Otherwise, algorithm522returns to step504to sample another input signal.

In this fashion, loop algorithm500quickly cycles and locks onto a gain value. Gain high or low saturation occurs because the gain is a quantized code. Saturation occurs to prevent the gain code from overflow or underflow conditions. When the host starts the adaptive equalization of loop algorithm500depends on which application field is utilizing the equalization. For example, a USB3.0 host starts algorithm500when a super-speed signal (5 Gbps signal) is detected. Generally, the first super-speed signal will be training symbols transmitted directly after link initialization. If the USB 3.0 device is removed and re-connected, the host will restart loop algorithm500.

In general, FSM202may include any number of loops such as loop algorithm500. As shown inFIG. 2, there are the AGC loop providing a gain signal to variable gain amplifier102and a boost loop providing a gain signal to equalizer peaking amplifier104.

FIGS. 6A,6B, and6C illustrate an example of operation of some embodiments of receiver100according to the present invention.FIG. 6Aillustrates an eye diagram of a data input signal to receiver100.FIG. 6Billustrates an eye diagram of a data output signal from receiver100. As can be seen inFIG. 6B, much of the intersymbol interference has been removed from the data signal.FIG. 6Cillustrates operation of error signals210and212. As illustrated inFIG. 5C, the automatic gain control (AGC) can be on or off. When AGC is on, signal210provides up or down control signals to FSM202. Further, Automatic peaking boost control can be on or off. When boost is on, signal212provides up or down control signals to FSM202.

FIGS. 7A,7B, and7C illustrate another example of operation of some embodiments of receiver100according to the present invention.FIG. 7Aillustrates an eye diagram of a data input signal to receiver100.FIG. 7Billustrates an eye diagram of a data output signal from receiver100. As can be seen inFIG. 7B, much of the intersymbol interference has been removed from the data signal.FIG. 7Cillustrates operation of error signals210and212. As illustrated inFIG. 7C, the automatic gain control (AGC) can be on or off. When AGC is on, signal210provides up or down control signals to FSM202. Further, Automatic peaking boost control can be on or off. When boost is on, signal212provides up or down control signals to FSM202.

In the detailed description above, specific details have been set forth describing certain embodiments. It will be apparent, however, to one skilled in the art that the disclosed embodiments may be practiced without some or all of these specific details. The specific embodiments presented are meant to be illustrative, but not limiting. One skilled in the art may realize other material that, although not specifically described herein, is still within the scope and spirit of this disclosure.