Multi-level optical structure and method of manufacture

A multi-level optical device includes a substrate having a baseline level. At least one feature is disposed at a level above the baseline level. At least one feature is disposed at a level below the baseline level, or in the feature above the baseline level is located at a distance apart from the feature below the baseline level. The distance has an accuracy inn the range of approximately ±0.05 μm to less than approximately ±1.0 μm.A method of fabricating an optical device includes forming at least one feature at a level of above a baseline level of a substrate; and forming at least one feature at a baseline level below the baseline level of the substrate, wherein the feature at a level above the baseline level and the feature at a level below the baseline level are patterned in a single-mask step using a multi-level mask.

FIELD OF THE INVENTION

The present invention relates generally to optical integrated circuits and optical benches. More particularly, the present invention relates to multi-level optical integrated circuits (OIC's) and optical benches.

BACKGROUND OF THE INVENTION

OIC and optical bench fabrication often involves transferring patterns to a substrate. These patterns may be used to form a variety of structures to include conductive circuit lines, planar waveguides, mesas and recesses. Typically, the desired structures are formed using lithography. Lithography may be achieved by techniques such as photolithography, x-ray lithography and e-beam lithography.

In photolithography, for example, a layer of photo-reactive film, known as photoresist, may be formed over the substrate. A photolithographic mask containing the image of a desired pattern is then placed in contact with the photoresist film. Radiation of a wavelength to which the photoresist is sensitive is incident upon the mask. The radiation passes through the transparent areas of the mask and the exposed areas of the photoresist are reactive to the radiation. The photoresist film is then chemically developed, leaving behind a pattern of photoresist substantially identical to the pattern on the mask.

The patterned photoresist on the substrate may be used in a variety of applications to form the structures referenced above. For example, a pattern photoresist may act as a mask for selective etching of a substrate. This selective etching may be used to fabricate recesses and as mesas in the substrate. In OIC and optical bench technologies, the mesas and recesses may be used for a variety of purposes, including passive alignment of optical elements.

The above described photolithographic process is often referred to as contact printing, because the mask is placed in contact with the substrate. Contact printing has facilitated the fabrication of highly integrated structures in both electrical and optical integrated circuits. However, conventional contact printing techniques have certain limitations. For example, conventional contact printing techniques generally are useful only in processing flat substrates. If a substrate has a relief (i.e. has a non-planar topography) it is exceedingly difficult to fabricate structures on the substrate by flat conventional contact printing techniques. To this end, conventional photolithographic masks are substantially flat. As a result, it is exceedingly difficult to place the mask in contact with, or in close enough proximity to, all points on the surface of a substrate to enable accurate image projection onto the substrate. In regions of the substrate where the photolithographic mask is not in contact with, or in close enough proximity to, the substrate, diffractive effects result in poor resolution and ultimately a poor transfer of the pattern from the mask to the photoresist.

The above referenced limitations of image lithography processing typically result in inaccurate location and spacing of features in a multi-level substrate. These inaccuracies are unacceptable as the integration of various elements at multiple levels in OIC's and optical bench technologies gains industry acceptance. Accordingly, what is needed are optical integrated circuits and optical benches which incorporate a variety of features at multiple levels which overcome the inaccuracies of conventional structures and methods of manufacture as referenced above.

SUMMARY OF THE INVENTION

According to an exemplary embodiment of the present invention, a multi-level optical device includes a substrate having a baseline level. At least one feature is disposed at a level above the baseline level. At least one feature is disposed at a level below the baseline level, wherein the feature above the baseline level is located at a horizontal distance apart from the feature below the baseline level. The horizontal distance has an accuracy of approximately ±0.05 μm to approximately less than ±1.0 μm.

According to an another exemplary embodiment of the present invention, a method of fabricating an optical device includes forming at least one feature at a level of above a baseline level of a substrate; and forming at least one feature at a level below the baseline level of the substrate, where the feature at a level above the baseline level and the feature at a level below the baseline level are patterned in a single- mask step using a multi-level mask.

DEFINED TERMS

As used herein, “non-planar” means having multiple levels or regions above and/or below a principal planar surface (baseline level) of a substrate.

As used herein, “opaque” means electromagnetic radiation of a particular wavelength or wavelength spectrum is substantially absorbed and/or substantially reflected, so that blocked radiation does not expose radiation sensitive layer(s) during lithography.

As used herein, “transparent” means electromagnetic radiation of a particular wavelength or wavelength spectrum is neither substantially absorbed nor substantially reflected, so that transmitted radiation can be used to expose a radiation sensitive layer(s) during lithography.

As used herein, the term “close proximity” means close enough to an object that diffractive effects are substantially negligible.

DETAILED DESCRIPTION

In the following detailed description, for purposes of explanation and not limitation, exemplary embodiments disclosing specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be apparent to one having ordinary skill in the art having had the benefit of the present disclosure, that the present invention may be practiced in other embodiments that depart from the specific details disclosed herein. Moreover, descriptions of well-known devices, methods and materials may be omitted so as to not obscure the description of the present invention.

For the purpose of clarity of discussion, the description of the illustrative embodiments described below will center primarily on ultraviolet (UV) photolithography, where UV light is used for photoresist patterning. Therefore, unless otherwise specified, the materials and structural dimensions are specific to UV photolithography. Of course, the present invention may be used in other lithographic techniques. These include, but are not limited to, lithography using other electromagnetic radiation. Illustratively, photolithography using other portions of the optical spectrum and x-ray lithography may be used. As disclosed fully in the parent application, the multi-level mask have materials and dimensions specific to the chosen lithography technique. In addition, the materials and dimensions used for the various elements used to form the multi-level structure of the invention of the present disclosure may be different than those disclosed herein, which are illustrative of those used in UV-photolithography. Again, these materials and dimensions are chosen for the specific type of lithography used. Finally, in addition to the lithography specific transparent properties, opaque properties and radiation sensitivity properties, these materials may have to exhibit etch-selectivity to enable fabrication of various features. These materials and dimensions within the purview of one having ordinary skill in the art.

FIG. 1is a perspective view of structure100in accordance with an exemplary embodiment of the present invention. Illustratively, structure100is a portion of an optical integrated circuit, or a portion of an optical bench. The structure100includes a substrate101. The substrate101is illustratively silicon or other suitable material. Conductive elements102may be disposed over the substrate101. The conductive elements102may be used for bonding of an optoelectronic device such as a laser or photodetector (not shown). Moreover, the conductive elements102may be useful in providing electrical connection between an optoelectronic device and electronic devices (not shown) of an OIC.

Illustratively, conductive elements102are metal. Grooves103, which are illustratively v-shaped grooves are formed in the substrate101. The grooves103are illustratively used to hold optical fibers104. The grooves are accurately located and have accurate dimensions, which enables accurate alignment of the optical fibers104to optical waveguides of the OIC. Of course, this is merely illustrative, and the optical fibers could be coupled to an optoelectronic device (not shown) such as laser, light emitting diode (LED) or photodetector. Moreover, grooves103are illustrative of a variety of recesses which may be formed in substrate101. These recesses may also be for example, inverted pyramidal-shaped pits for holding spherical elements, such as microlenses.

Planar waveguides105, having waveguide cores106and cladding layer107disposed thereabout, are coupled to the optical fibers in an accurate manner by virtue of the accurate location of the planar waveguides105and the optical fibers104. To this end, the planar waveguides105are fabricated above baseline level108of substrate101, whereas the grooves103are fabricated below the baseline level108of the substrate101. As explained in further detail herein, the grooves103and the waveguide cores106may be defined in a single-mask step using a multi-level mask by virtue of the fabrication sequence according to an illustrative embodiment of the present invention.

This single-mask step enables accurate location of the grooves103relative to the waveguide cores106, which facilitates accurate optical coupling between an optical fiber communication system and a terminal interface such as structure101which may be an OIC or an optical bench. Moreover, the conductive elements102may also be accurately located and fabricated according to an illustrative embodiment of the present invention. The accurate location of the conductive elements relative to planar waveguides105fosters accurate optical coupling between an optoelectronic device disposed over conductive elements102and planar optical waveguides105, for example. As will be described in further detail herein, the accuracy of the horizontal distance between the features formed at different levels of structure100is in the range of approximately ±0.05 μm to less than approximately ±1.0 μm.

It is of interest to note that other devices beside the planar waveguides105could be coupled to optical fibers104. For example, the optical fibers104could be optically coupled to an optoelectronic device (not shown), which is disposed at a level above baseline level108. In this exemplary embodiment, the single mask step, using the multi-level mask described in the above referenced parent application, enables the formation of conductive pads (such as conductive elements102) to be accurately located and accurately spaced from grooves103. As such, the tolerance of the horizontal distance between features (e.g. conductive pads and grooves) at different level is in the range of approximately ±0.05 μm to approximately less than ±1.0 μm . Ultimately, this fosters accurate coupling between the optical fiber(s) and the optoelectronic device.

Finally, it is of interest to note that other elements may be formed over the substrate at levels above the baseline level108or be disposed in recesses formed below the baseline level. These include passive optical devices such as filters, gratings, isolators, multiplexers, as well as others within the purview of one having ordinary skill in the art.

FIG. 2shows a cross-sectional view of a structure200having planar waveguides201above a baseline level205of a substrate202. Conductive elements203are disposed above baseline level205, but at a different level than planar waveguides201. Finally, a recess204is disposed below baseline level205of substrate202. As can be readily appreciated, planar waveguides201, conductive elements203and recess204may be elements of structure100shown inFIG. 1. An illustrative technique for fabricating a structure, such as structure200is described presently. As discussed above, as well as discussed in the above captioned parent application, the illustrative fabrication sequence centers on photolithography, particularly UV photolithography. Of course, this is merely illustrative, and is in no way limiting of the present invention.

FIG. 3(a) is a cross-sectional view of a substrate301having a lower cladding layer302disposed thereover. A core layer303is disposed over the lower cladding layer302. In the illustrative embodiment shown inFIG. 3(a), the substrate301is illustratively silicon. The lower cladding layer302may be silica, silicon oxynitride, glass or a doped material such as doped glass. The core layer303may be silica, silicon oxynitride, glass, doped material (e.g. doped glass), silicon, GaAs ,InP or polymer. Of course, these are merely illustrative, and alternative materials may be used for a variety of applications in keeping with the present invention. The lower cladding layer302and core layer303have accurately determined thicknesses. Illustratively, the core layer303has a thickness in the range of approximately 2 μm to approximately 5 μm. The lower cladding layer302has a thickness in the range of approximately 10 μm to approximately 20 μm. The lower cladding layer302and core layer303may be fabricated of a variety of materials.

FIG. 3(b) shows a portion of lower cladding layer302and core layer303having been selectively removed from the top surface of substrate301. This removal may be done relatively inaccurately, and by standard etching techniques.

FIG. 3(c) shows a multi-level mask304disposed over substrate301and over the core layer303. The multi-level mask304is illustratively a two-level mask having a base layer305and a mesa306, which are transparent. The mask further includes opaque portions307used during an image lithography step. Further details of multi-level mask304may be found in the above captioned parent application. In the illustrative embodiment shown inFIG. 3(c), the multi-level mask304is useful in patterning conductive elements308over the core layer303and substrate301. The conductive elements308over core layer303are at a level above baseline level312of substrate301, while conductive elements308over substrate301are at another level above baseline level312. The conductive elements308are illustratively metal, such as chromium. The conductive elements308may be patterned using standard lift-off techniques or undercut etch techniques well known to one having ordinary skill in the art.

Conductive elements308may be used as masks during selective etching to form features useful in OIC and optical bench applications. Moreover, conductive elements308may be used as mounting pads for optoelectronic devices as well as to provide electrical connections between optoelectronic devices and electronic devices on an OIC. Finally, the accuracy of the formation of the conductive elements308is due to the single-mask step at multiple levels enabled by multi-level mask304. Because the conductive elements308are accurately located and accurately spaced apart, etched features formed using conductive elements308as masks are accurately located and spaced. The accuracy of the horizontal distance between these etched features is in the range of approximately ±0.05 μm to less than approximately ±1.0 μm. Further details of this accurate spacing and location of features are described herein and in the above captioned parent application.

While the conductive elements308are illustratively chromium, these elements may be tantalum, gold, nickel, aluminum, or titanium or combinations thereof. Moreover, conductive elements308may be fabricated from other materials such as conductive metal oxides (e.g. titanium sub-oxide), conductive nitrides or conductive silicides. The choice of materials is also dictated by the chemical reactivity of the materials used for the cladding layer302and the core layer303; and by their suitability as opaque mask elements used in the fabrication of waveguide cores.

FIG. 3(d) shows an etching step to remove unprotected portions of core layer303to form waveguide cores314. The illustrative etching step may be a reactive-ion-etching step or other standard dry-etching technique. The substrate301may be protected during this etch-step by a resist mask309shown inFIG. 3(e).

As shown inFIG. 3(f), the elements308have been removed from the top surface of waveguide cores314. This removal step may be effected by a standard technique, and may require a separate masking step.

FIG. 3(g) shows the disposition of the optional upper cladding layer310. However, a waveguide may be formed with lower cladding layer302, waveguide layer314and air above. Upper cladding layer310may be formed over the lower cladding layer302, the waveguide cores314and the substrate301. The upper cladding layer310is illustratively of the same material as lower cladding layer302. The upper cladding layer310may be silica, glass, doped glass, polymer or silicon oxynitride. Of course, the lower cladding layer302and the upper cladding layer310have a lower index of refraction than waveguide cores314.

Next, as shown inFIG. 3(h), a resist311is disposed over the portion of the upper cladding layer310that is over the waveguide cores314and lower cladding layer302. The resist311protects the structure thereunder, and the upper cladding layer310is selectively removed from the unprotected portion of the substrate301and conductive elements308. The removal of the upper cladding layer310may be achieved by a standard dry-etch or wet-etch technique. If removal is by a wet-etch technique, conductive elements308may need to be protected with a relatively thin film of protective material (e.g. tantalum oxide in the case of a hydrofluoric acid etch).

FIG. 3(i) shows the application of a resist311over a portion of upper cladding layer310, core layer303, lower cladding layer302and substrate301. Exposed portion313of the substrate301is the region to be selectively etched (micromachined). As can be readily appreciated, the conductive elements308in the exposed portion313define the area to be selectively etched (i.e. micromachined). The conductive elements308used as a mask for the selective etching step are fabricated during the single-mask step described above, and are accurately located and spaced from other features of the multi-level structure. This accuracy ultimately fosters accurate location of recesses, and thereby of elements (e.g. optical fibers) disposed therein.

FIG. 3(j) shows the selectively etched recess in the exposed portion313defined by the conductive elements308. The selective etch step may be effected using a standard dry or wet etch techniques.

FIG. 3(k) shows the resultant structure after removal of resist311. As can be readily appreciated, the resultant structure has planar waveguides316including upper cladding layer310, cores314and lower cladding layer302. The planar waveguides316are disposed above a baseline level312at a first level. The conductive elements308are disposed above a baseline level312at a second level. Finally, the recess315is disposed below the baseline level312. Accordingly, a multi-level structure has been formed using a multi-level mask in a single-mask step.

As mentioned above, the formation of conductive elements308over the substrate301and core layer303is accurately defined at multiple levels by virtue of the single-mask step using the multi-level mask306. Because the conductive elements308may be used to fabricate features such as waveguide cores314and recess315, the location of and spacing between these elements is accurately defined. To this end, the relative location of planar waveguides316, waveguide cores314, conductive elements308and recess315is well defined. Illustratively, the horizontal distances317,318,319,320,321and322, between various features at multiple levels above and below baseline312each have an accuracy in the range of approximately ±0.05 μm to less than approximately ±1.0 μm. This degree of accuracy is far greater than that which may be achieved in multi-level structures using conventional lithography techniques.

FIGS. 4(a)-4(g) show an alternative fabrication sequence according to an exemplary embodiment of the present invention. Particularly, the illustrative embodiment shown inFIGS. 4(a)-4(g) demonstrates the applicability of the present invention for use with photosensitive waveguide materials.

FIG. 4(a) shows a substrate401, a lower cladding layer402and a core layer403. The substrate401and lower cladding layer402are illustratively the same as those described in connection with the exemplary embodiment ofFIGS. 3(a)-3(k). However, the core layer403is a photosensitive core layer. The core layer403may be made from a photosensitive glass or a photosensitive polymer. The core layer403and cladding layer402each have accurately determined thicknesses. The core layer403has a thickness in the range of approximately 2 μm to approximately 5 μm. The lower cladding layer402has a thickness in the range of approximately 10 μm to approximately 20 μm.

FIG. 4(b) shows the removal of a portion of upper cladding layer402and a portion of core layer403, in areas above baseline level413of substrate401where there will be no planar waveguides. This removal step may be effected relatively inaccurately (e.g. having an accuracy of ±10 μm to ±50 μm).

FIG. 4(c) shows a multi-level mask404disposed over substrate401and core layer403. The multi-level mask404may be used to pattern conductive elements405on the substrate401and core layer403. The patterning of the metal layer to form conductive elements405may be effected by standard lift-off or undercut etch techniques. As referenced above, the conductive elements405may be a variety of metals, or other materials previously described. As can be appreciated from a review ofFIG. 4(c), the multi-level mask404enables the fabrication of metal elements405at multiple levels in a single-mask step. This formation of metal elements405in a single-mask step facilitates accurate location of and horizontal distance between features of an OIC or optical bench. Further details of the single-mask step and the advantages thereof may be found above and in the above captioned parent application. pFIG. 4(d) shows exposure of the photosensitive core403to form waveguide cores406. As can be readily appreciated by one having ordinary skill in the art, exposure of core layer403to a particular wavelength or wavelength band of radiation results in an increase in the index of refraction of the exposed portion of core layer403. As such, waveguide cores406have an increased index of refraction relative to the lower cladding layer402and the unexposed portion of photosensitive core layer403.FIG. 4(e) shows the removal of mask elements405from above photosensitive layer403. As referenced previously, this removal is by standard technique, and may require a mask step.

FIGS. 4(f) and4(g) show the disposition and selective removal of optional upper cladding layer407. The formation of the upper cladding layer407is carried out in a manner identical that described in connection with the illustrative embodiment ofFIGS. 3(a)-3(k). Again, this optional and air may form the cladding above waveguide cores406.

Next, although not shown, the micro-machined features, such as a recess may be carried out using conductive elements405disposed over the baseline level413of substrate401. The micro-machined features by selective etching may be effected in a manner identical to that described in connections with the illustrative embodiment ofFIGS. 3(a)-3(k).

Finally, as shown inFIG. 4(g), the horizontal distances between and locations of various features formed in the multi-layer structure are very accurately defined. Again, by virtue of the single-mask step, conductive elements405may be accurately located and separated from one another at various levels above baseline level413. These conductive elements are then used as masks in various processing steps described above. Ultimately, the horizontal distances408,409,410,411and412between features formed at various levels above and below a baseline of substrate401are accurately defined. The accuracy of these distances is in the range of approximately ±0.05 μm to less than approximately ±1.0 μm.

FIG. 5shows a cross-sectional view of a multi-layer structure500having a multi-level mask501disposed thereover. The multi-level mask501is as described in the above captioned parent application. The multi-level mask501may be used to pattern conductive elements505over a substrate506. The multi-level mask501having opaque elements508may be used to directly expose a photosensitive core layer503disposed over lower cladding layer507. By using the multi-level mask501to form waveguide cores504, the need for conductive elements505over the photosensitive core layer503is eliminated. Moreover, the conductive elements505may be also formed in the single-mask step used to form the waveguide cores504. As such, the accuracy of the location of and horizontal distance between various features formed using the single-mask step shown inFIG. 5are virtually identical to that of the illustrative embodiment shown inFIG. 4(g). The embodiment shown illustratively inFIG. 5is substantially the same as that shown inFIGS. 4(a)-4(g). Similar processing to that described in connection therewith will result in the fabrication of a structure very similar to that shown inFIG. 4(g).

The invention being thus described, it would be obvious that the same may be varied in many ways by one of ordinary skill in the art having had the benefit of the present disclosure. Such variations are not regarded as a departure from the spirit and scope of the invention, and such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims and their legal equivalents.