Printed circuit board structure for solid state drives

A printed circuit board (PCB) structure is provided for a solid state drive. In an embodiment, a solid state drive includes top and bottom layers, multiple intermediate layers and a ground cage. Each of top and bottom layers includes a plurality of components for operation of the solid state drive. The multiple intermediate layers enable electrical signals to pass between components on the top and bottom layers, one of the multiple intermediate layers including a power plane having a high voltage relative to each of the other planes. The ground cage shields signal traces on the same layer as the power plane and planes in adjacent layers from noise generated by the power plane.

BACKGROUND

Embodiments of the present disclosure relate to a printed circuit board structure.

2. Description of the Related Art

The computer environment paradigm has shifted to ubiquitous computing systems that can be used anytime and anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has rapidly increased. These portable electronic devices generally use a memory system having memory device(s), that is, data storage device(s). The data storage device is used as a main memory device or an auxiliary memory device of the portable electronic devices.

An electronic device such as a data storage device may be implemented with a printed circuit board (PCB).

SUMMARY

Aspects of the present invention include a printed circuit board (PCB) structure for a data storage device such as a solid state drive.

In one aspect, a solid state drive includes: top and bottom layers, each of which includes a plurality of components for operation of the solid state drive; multiple intermediate layers configured to enable electrical signals to pass between components on the top and bottom layers, one of the multiple intermediate layers including a power plane having a high voltage relative to each of the other planes; and a ground cage configured to shield the noisy high voltage power planes, which greatly minimizes the noise coupled to the victim power planes or signal traces around the neighboring or adjacent layers.

In another aspect, a printed circuit board for a solid state drive, includes: top and bottom layers, each of which includes a plurality of components for operation of the solid state drive; and multiple intermediate layers disposed between the top and bottom layers and configured to enable electrical signals to pass between components on the top and bottom layers. The multiple intermediate layers include: a first intermediate layer including a high power plane (100) having a high voltage and first and second signal traces (200A,200B) adjacent to the high power plane; a second intermediate layer (400) formed above the first intermediate layer and below the top layer and including a first low power plane (410or430) having a low voltage less than the high voltage; a third intermediate layer (500) formed below the first intermediate layer and above the bottom layer and including a second low power plane (510or530) having the low voltage; and a ground cage (300A,300B,300C) configured to enclose the high power plane such that capacitive and inductive paths between the high power plane and each of the first and second signal traces and capacitive and inductive paths between the high power plane and each of the first and second low power planes are blocked.

Additional aspects of the present invention will become apparent from the following description.

DETAILED DESCRIPTION

Various embodiments are described below in more detail with reference to the accompanying drawings. The present invention may, however, be embodied in different forms and thus should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure is thorough and complete and fully conveys the scope of the present invention to those skilled in the art. Moreover, reference herein to “an embodiment,” “another embodiment,” or the like is not necessarily to only one embodiment, and different references to any such phrase are not necessarily to the same embodiment(s). Throughout the disclosure, like reference numerals refer to like parts in the figures and embodiments of the present invention.

The invention can be implemented in numerous ways, including as a process; an apparatus; a system; a computer program product embodied on a computer-readable storage medium; and/or a processor, such as a processor suitable for executing instructions stored on and/or provided by a memory coupled to the processor. In this specification, these implementations, or any other form that the invention may take, may be referred to as techniques. In general, the order of the steps of disclosed processes may be altered within the scope of the invention. Unless stated otherwise, a component such as a processor or a memory described as being suitable for performing a task may be implemented as a general component that is temporarily configured to perform the task at a given time or a specific component that is manufactured to perform the task. As used herein, the term ‘processor’ or the like refers to one or more devices, circuits, and/or processing cores suitable for processing data, such as computer program instructions.

A detailed description of embodiments of the invention is provided below along with accompanying figures that illustrate aspects of the invention. The invention is described in connection with such embodiments, but the invention is not limited to any embodiment. The scope of the invention is limited only by the claims. The invention encompasses numerous alternatives, modifications and equivalents within the scope of the claims. Numerous specific details are set forth in the following description in order to provide a thorough understanding of the invention. These details are provided for the purpose of example; the invention may be practiced according to the claims without some or all of these specific details. For clarity, technical material that is known in technical fields related to the invention has not been described in detail so that the invention is not unnecessarily obscured.

FIG. 1is a block diagram illustrating an example of a data processing system10.

Referring toFIG. 1, the data processing system10may include a host device50and a storage device (which may be implemented as a memory system)100. The storage device100may receive a request from the host device50and operate in response to the received request. For example, the storage device100may store data to be accessed by the host device50.

The host device50may be implemented with any of various kinds of electronic devices. In various embodiments, the host device50may include an electronic device such as a desktop computer, a workstation, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, and/or a digital video recorder and a digital video player. In various embodiments, the host device50may include a portable electronic device such as a mobile phone, a smart phone, an e-book, an MP3 player, a portable multimedia player (PMP), and/or a portable game player.

The storage device100may include a controller110, a memory device120and a power supply130. The controller110may exchange a signal SGL (which may represent multiple signals) with the host device50through a signal connector SC. The signal SGL may include a command, an address, and data. The signal connector SC may be configured as any of various types of connectors according to an interface scheme between the host device50and the storage device100.

The controller110may control overall operation of the memory device120in response to a signal SGL from the host device50. For example, the controller110may control the memory device120to perform one or more erase, program, and read operations.

The memory device120may be coupled to the controller110through one or more channels. The memory device120may be implemented with a plurality of nonvolatile memory devices. The controller110and the memory device120may be implemented with any of various kinds of storage devices such as a solid state drive (SSD) and a memory card.

The power supply130may provide components in the storage device100with power PWR inputted through a power connector PC from the host device50.

FIG. 2is a diagram illustrating an example of the power supply130for the storage device100.

Referring toFIG. 2, the power supply130may include a plurality of capacitors C1to Cn, a voltage step-up regulator RU and a voltage step-down regulator RD. Although not shown inFIG. 1, the storage device100may further include a power switch140and a power controller150coupled to the power supply130, as shown inFIG. 2.

The power switch140may provide a normal power delivery path or a power loss protection (PLP) delivery path under control of the power controller150. In the normal power delivery path, power provided from the host device50is delivered through the power switch140, the power controller150, and the voltage step-up regulator RU to the plurality of capacitors C1to Cn. The voltage step-up regulator RU may convert a low input voltage from the host device50to a high voltage (e.g., 35V or more). The high voltage may be used to charge the plurality of capacitors C1to Cn. The power supply130may include a first path (i.e., V_High_Bus) to pass power (i.e., a high voltage) between the voltage regulator RU, RD and the plurality of capacitors C1to Cn, and a second path (i.e., V_Low_Bus) to pass power (i.e., a low voltage) between the voltage regulator RU, RD and the host device50through the power switch140. Further, the power supply130may include a third path to pass a signal to the voltage regulator RU, RD from the power controller150.

When power to the storage device100from the host device50is interrupted or cut-off, the plurality of capacitors C1to Cn may be discharged and the energy stored therein may be delivered through the PLP delivery path including the voltage step-down regulator RD, the power switch140, the power controller150and internal power regulators. The storage device100may use the plurality of capacitors as a power source to back up data from an internal memory of the controller110(e.g., volatile memory) to the memory device120(e.g., NAND flash device).

As such, the plurality of capacitors C1to Cn may form a capacitor array to provide sufficient energy to maintain power rail voltages for data back-up transfer from the controller110to the memory device120. The capacitor array or a large bulk capacitor may serve as a power loss protection (PLP) capacitor for the storage device100. The step-up regulator RU may be implemented with a voltage regulator including switching components (e.g., FETs), which is normally used for high power conversion efficiency. The step-up regulator RU may be connected to the PLP capacitor through the power path V_High_Bus. The power paths V_High_Bus and V_Low_Bus may be implemented in a printed circuit board (PCB) of the storage device100(e.g., a solid state drive (SSD)) by using one or more power planes or layer.

Parasitic capacitance and parasitic inductance may exist along electrical paths and within electrical components. As the switching components of the voltage regulator are turned on and off at high frequency (e.g., 1 MHz or more) and thus suddenly change current paths, intense voltage ringing noise at a few hundred MHz may occur, and a significantly high current inrush spike may also occur during the charge process and discharge process of the PLP capacitor, as shown inFIGS. 3A and 3B.

FIG. 4is a view illustrating an example of a multi-layer printed circuit board (PCB).

Referring toFIG. 4, the PCB may have a structure of multiple layers. In the illustrated example, the PCB has 12 layers including a top conductor layer, a bottom conductor layer, and ten conductive layers L02to L11disposed between the top and bottom conductive layers. A surface dielectric layer may be disposed between an upper surface of the PCB and the top conductor layer, and another surface dielectric layer may be disposed between a lower surface of the PCB and the bottom conductor layer. Components of a particular circuit (e.g., a power supply130ofFIG. 2) may be installed on the top conductor layer and the bottom conductor layer. Each of the second conductor layer L02to the eleventh conductor layer L11may pass power or a signal or may form a ground. In an example, the second conductor layer L02to the eleventh conductor layer L11are used as shown in the following Table1:

In Table1, each trace may be a thin copper conductor for passing signals and each plane may be a fat copper conductor for passing power.

Further, the PCB may include through holes TH1, TH2between the upper surface and the lower surface, and vertical vias V1, V2, V3used to make electrical connections between layers.

On the PCB as described above, structural mutual capacitance and structural mutual inductance may exist between neighboring layers and between neighboring power planes or signal traces on the same layer. In other words, a certain power plane (i.e., aggressor) may cause power noise to be coupled to other power planes or signal traces (i.e., victims). The power noise coupling situation has been found to be even worse in a circuit area where a voltage could be several times higher than the rest circuit areas on the PCB. For example, when the power supply130ofFIG. 2is implemented with a PCB with multiple layers as shown inFIG. 4, inventors observed that a power plane for the path V_High_Bus causes voltage ringing noise and current inrush spike to occur in other planes or traces. Such a power noise coupling contamination is not tolerable because it will ultimately cause signal integrity issues and lead to system malfunction of a storage device.

FIG. 5is a sectional view illustrating an example of a printed circuit board (PCB) section with noisy power planes and neighboring planes or traces.

Referring toFIG. 5, the PCB may include the noisy power planes, which may be individually and collectively referred to as the aggressor, and the neighboring planes or traces, which are victims. In the illustrated example, the PCB may include 3 noisy power planes which are electrically connected together on the PCB. Each noisy power plane may be one or more layers depending on the specific design of the PCB. A victim plane may be on the same layer as a noisy power plane or on a neighboring layer. Gaps between aggressor planes and victim planes may be filled with dielectric material.

Noise coupling from the aggressor to the victims is analyzed as below with reference toFIGS. 6A and 7B.

FIGS. 6A and 6Billustrate the capacitive coupling path through the electrostatic field, and its equivalent circuit. The coupling path may be on the same layer (FIG. 6A), and between neighboring layers (FIG. 6B). The coupled voltage on the victim plane or trace can be expressed as:
Vn=jωCRVs(1)

In Equation (1), ω=2πf, f is the ringing noise frequency, C is the coupling path mutual capacitance, R is load impedance, and Vs is the voltage ringing noise of a power plane (e.g., the power plane V_High_Bus of the PLP capacitor inFIG. 2).

It can be seen from Equation (1) that, when C is large enough, the higher frequency and high voltage ringing noise can be coupled to the victim plane or trace as Vn.

FIGS. 7A and 7Billustrate the inductive coupling path through the electrostatic field, and its equivalent circuit. The coupling path may be on the same layer (FIG. 7A), and between neighboring layers (FIG. 7B). The coupled voltage on the victim plane or trace can be expressed as:
Vn=jωMIs(2)

In Equation (2), ω=2πf, f is the inrush spike frequency, M is the coupling path mutual inductance, and Is is the current inrush spike of a power plane (e.g., the power plane V_High_Bus of the PLP capacitor inFIG. 2).

It can be seen from Equation (2) that, when M is large enough, the higher frequency and high current spiking can be coupled to the victim plane or trace as Vn.

As described above, in a printed circuit board, voltage ringing noise and a current inrush spike may occur in an electrical path for a storage device (e.g., a power supply130inFIG. 2). Accordingly, it is desirable to provide a structure capable of avoiding high energy ringing noise and a current inrush spike in a printed circuit board (PCB). Embodiments provide a PCB structure used to encapsulate one or more high voltage power planes as the aggressor, where the high voltage power planes are enclosed by several ground planes. As a result, the power noise coupling paths to the victim planes or traces are effectively blocked or terminated.

FIGS. 8A and 8Bare views illustrating a structure of a printed circuit board (PCB) in accordance with embodiments of the present invention.

Referring toFIGS. 8A and 8B, the PCB may include a high voltage power plane100as the aggressor and two neighboring planes or traces200A,200B, collectively referred to as the victim element. In some embodiments, the high voltage power plane100may be a power path V_High_Bus between the regulators RU, RD and the PLP capacitors, as shown in the power supply130inFIG. 2. Two neighboring planes or traces200A,200B may be a power path V_Low_Bus between the regulators RU, RD and the power switch140or a signal path between the regulators RU, RD and the power controller150.

The high voltage power plane100may be enclosed (or encapsulated) by an enclosure component. In some embodiments, the enclosure component may be implemented with a ground cage including multiple ground planes. In the illustrated example, the enclosure component may include a first ground plane300A, a second ground plane300B and a third ground plane300C. The first ground plane300A may be arranged at the same layer as the high voltage power plane100(i.e., a noisy power plane). The second ground plane300B may be arranged above the first ground plane300A. The third ground plane300C may be arranged below the first ground plane300A. The first ground plane300A may horizontally enclose the periphery of the high voltage power plane100, and the second ground plane300B and the third ground plane300C may cooperate to vertically enclose the high voltage power plane100. In other words, the first ground plane300A to the third ground plane300C may form the ground cage to enclose the high voltage power plane100. The high voltage power plane100may include one or more power planes. As such, embodiments provide a special PCB structure to effectively shield the high voltage plane or planes so that the high energy ringing noise and a current inrush spike may be constrained within the structure without adding extra components or costs. The special PCB structure may be referred to as “a sandwiched PCB structure.” Thus, mutual capacitance and mutual inductance between the noisy power plane as the aggressor and power planes or traces as the victim element may be minimized.

FIG. 9is a sectional view illustrating a printed circuit board (PCB) structure for a storage device (e.g., SSD) in accordance with embodiments of the present invention.

Referring toFIG. 9, the PCB structure may include first layers, a second layer400and a third layer500. Each of the first layers may include a first plane configured to pass power as a high voltage power plane (i.e., aggressor), and second and third planes (i.e., victim) adjacent to the first plane. By way of example and without any limitation, the first layers may include 3 first layers including top, intermediate and bottom first layers. The top first layer may include a first plane100-1, a second plane200A-1and a third plane200B-1. The intermediate first layer may include a first plane100-2, a second plane200A-2and a third plane200B-2. The bottom first layer may include a first plane100-3, a second plane200A-3and a third plane200B-3. In some embodiments, each of the second and third planes may include a power plane to pass power or a signal trace to pass a signal.

The second layer400may be formed over the top first layer. For example, the second layer400may include multiple planes410,420,430. The third layer500may be formed below the bottom first layer. For example, the third layer500may include multiple planes510,520,530. In some embodiments, each of the second and third layers400,500may include a power plane to pass power or a trace to pass a signal.

The PCB structure may include an enclosure component including a ground cage configured to horizontally and vertically enclose the first planes100-1,100-2,100-3, which form the aggressor. In some embodiments, the ground cage may include multiple ground planes which are arranged horizontally and vertically such that capacitive and inductive paths between the aggressor and the victim are blocked.

The ground cage may include a fourth plane300A-11between the first plane100-1and the second plane200A-1and a fifth plane300A-12between the first plane100-1and the third plane200B-1. The ground cage may include a fourth plane300A-21between the first plane100-2and the second plane200A-2and a fifth plane300A-22between the first plane100-2and the third plane200B-2. The ground cage may include a fourth plane300A-31between the first plane100-3and the second plane200A-3and a fifth plane300A-32between the first plane100-3and the third plane200B-3. Further, the ground cage may include a fourth layer300B formed between the top first layer and the second layer400, and a fifth layer300C formed between the bottom first layer and the third layer500. Multiple ground planes of the ground cage may be electrically coupled.

In some embodiments, thicknesses and widths of layers and planes may be adjusted such that mutual coupling capacitance and mutual coupling inductance are minimized.

For each first layer, the first to fifth planes may have the same thickness T2. For the top first layer, a fourth plane300A-11between the first plane100-1and the second plane200A-1and a fifth plane300A-12between the first plane100-1and the third plane200B-1may have the thickness T2. The fourth plane300A-11and the fifth plane300A-12may have the same width W2. For the intermediate first layer, a fourth plane300A-21between the first plane100-2and the second plane200A-2and a fifth plane300A-22between the first plane100-2and the third plane200B-2may have the thickness T2. The fourth plane300A-21and the fifth plane300A-22may have the same width W2. For the bottom first layer, a fourth plane300A-31between the first plane100-3and the second plane200A-3and a fifth plane300A-32between the first plane100-3and the third plane200B-3may have the thickness T2. The fourth plane300A-31and the fifth plane300A-32may have the same width W2.

The fourth layer300B and the fifth layer300C may have the same thickness T1and may have the same width W1.

The PCB structure may include gaps between layers and gaps between planes in each layer. In some embodiments, these gaps may be filled with a dielectric material (e.g., epoxy laminate material).

The top first layer may include a first gap, which may have length G2, between the first plane100-1and the fourth plane300A-11, a second gap, which also may have a length G2, between the first plane100-1and the fifth plane300A-12, a third gap between the second plane200A-1and the fourth plane300A-11and a fourth gap between the third plane200B-1and the fifth plane300A-12. The intermediate first layer may include a first gap between the first plane100-2and the fourth plane300A-21, a second gap between the first plane100-2and the fifth plane300A-22, a third gap between the second plane200A-2and the fourth plane300A-21and a fourth gap between the third plane200B-2and the fifth plane300A-22. The bottom first layer may include a first gap between the first plane100-3and the fourth plane300A-31, a second gap between the first plane100-3and the fifth plane300A-32, a third gap between the second plane200A-3and the fourth plane300A-31and a fourth gap between the third plane200B-3and the fifth plane300A-32.

The PCB structure may include a fifth gap, which may have a length G1, between the top first layer and the fourth layer300B, a sixth gap between the second layer400and the fourth layer300B, a seventh gap between the bottom first layer and the fifth layer300C, and an eighth gap between the third layer500and the fifth layer300C.

In some embodiments, gaps between layers and gaps between planes may be adjusted such that mutual coupling capacitance and mutual coupling inductance are minimized. In some embodiments, the PCB structure may have multiple layers as shown inFIG. 4and the multiple layers have a thickness of less than 1 mm, where G1is less than 50 um and G2is less than 100 um such that the high voltage ringing noise and high current inrush spike at high frequency could cross over the gaps vertically and horizontally, reaching the victim planes or traces.

FIG. 10Ais a three-dimensional (3D) perspective view of a printed circuit board (PCB) structure for a storage device, i.e., the PCB structure shown inFIG. 9, in accordance with embodiments of the present invention. The PCB structure is shown relative to an XYZ coordinate system.FIG. 10Bis a sectional view of a printed circuit board (PCB) structure shown inFIG. 10Aalong the Y axis.FIG. 10Cis a sectional view of a printed circuit board (PCB) structure shown inFIG. 10Aalong the X axis.

Referring toFIGS. 10A to 10C, high voltage power planes100-1,100-2,100-3are enclosed by an enclosure component including multiple ground planes300A-10,300A-20,300A-30,300B,300C. The enclosure component is disposed and configured to block or significantly reduce the coupling of noise (i.e., voltage ringing noise and current inrush spike) from the high voltage power planes100-1,100-2,100-3to victim power planes or signal traces200B-1,200B-2,200B-3,410,420,510,520.

As described above, embodiments provide a structure capable of avoiding power noise coupling (e.g., high energy ringing noise and current inrush spike) in a printed circuit board (PCB) for an electronic device such as a storage device (e.g., SSD). In accordance with embodiments, the PCB structure encapsulates one or more high voltage power planes by using several ground planes. Accordingly, embodiments block power noise coupling from the high voltage power planes to victim power planes or signal traces.

Although the foregoing embodiments have been illustrated and described in some detail for purposes of clarity and understanding, the present invention is not limited to the details provided. There are many alternative ways of implementing the invention, as one skilled in the art will appreciate in light of the foregoing disclosure. The disclosed embodiments are thus illustrative, not restrictive. The present invention is intended to embrace all modifications and alternatives that fall within the scope of the claims.