Stacked chip package structure with leadframe having bus bar

The present invention provides a chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips that stacked together and set on the die pad, the plurality of chips and the plurality of inner leads being electrically connected with each other; and an encapsulant covering over the chip-stacked package structure and the leadframe, in which the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an offset chip-stacked package structure, and more particularly, to an offset chip-stacked structure with leadframe having bus bar.

2. Description of the Prior Art

In semiconductor post-processing, many efforts have been made for increasing scale of the integrated circuits such as memories while minimizing the occupied area. Accordingly, the development of three-dimensional (3D) packaging technology is in progress and the idea of making up a chip-stacked structure has been disclosed.

The prior art has taught that a chip-stacked structure can be formed by firstly stacking a plurality of chips and then electrically connecting the chips to the substrate in a wire-bonding process.FIG. 1Ais a cross-sectional view of a prior chip-stacked package structure stacked by chips of same or similar size. As shown inFIG. 1A, a conventional chip-stacked package structure100includes a package substrate110, chips120aand120b, a spacer130, wires140, and an encapsulant150. The package substrate110has a plurality of pads112thereon, and the chips120aand120bare also respectively provided with the pads122aand122barranged in peripheral type. The chip120ais provided on the substrate110, while the chip120bis provided on the chip120awith a spacer130intervened there-between. The chip120ais electrically connected to the substrate110by bonding two ends of one of the wires140to the pads112and122arespectively. The chip120bis electrically connected to the substrate110in similar manner. The encapsulant150is then provided on the substrate110to cover the chips120aand120band the wires140.

Since the pads122aand122bare respectively provided at the peripheral of the chip120aand the120b, there is a need to apply the spacer130to prevent the chip120bfrom directly contacting with the chip120afor performing the subsequent wire-bonding. However, the use of spacer130increases the thickness of the chip-stacked package structure100.

Another prior chip-stacked package structure for different-sized chips has been disclosed. Referring toFIG. 1B, another conventional chip-stacked package structure10includes a package substrate110, chips120cand120d, wires140, and an encapsulant150. The substrate110has pads112on it. The chip120cis larger than the chip120din size. The chips120cand120dare respectively provided with peripherally arranged pads122cand122d. The chip120cis provided on the substrate110while the chip120dis provided on the chip120c. The chip120cis electrically connected to the substrate110by bonding two ends of one of the wires140to the pads112and122crespectively. The chip120dis electrically connected to the substrate110in similar manner. The encapsulant150is then provided on the substrate110to cover the chips120cand120dand the wires140.

Since the chip120dis smaller than the chip120c, the chip120dwould not covered over the pads122cof the chip120cwhen the chip120dis stacked on the chip120c. However, the condition that the upper chip must have size smaller than that of the lower chip limits number of the chips to be stacked in the chip-stacked package structure10.

In other words, the above-mentioned chip-stacked package structures have drawbacks of either increasing thickness as shown inFIG. 1Aor limiting number of the chips to be stacked as shown inFIG. 1B.

SUMMARY OF THE INVENTION

In view of the drawbacks and problems of the prior chip-stacked package structure as mentioned above, the present invention provides a three-dimensional chip-stacked structure for packaging multi-chips with similar size.

It is an object of the present invention is to provide a leadframe structure provided with bus bar for offset chip stacking and packaging and so as to the package has higher density and thinner thickness.

It is another object of the present invention to provide an offset chip-stacked structure for packaging with a leadframe that having bus bar structure and so as to make the circuit design more flexible and gain higher reliability.

According to abovementioned objects, the present invention provides an offset chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a plurality of stacked semiconductor chip structures being misaligned for forming an offset chip-stacked structure on the die pad, the plurality of chips on the offset chip-stacked structure and the plurality of inner leads being electrically connected with each other; and an encapsulant covering the plurality of semiconductor chip structures and the leadframe; wherein the leadframe comprises at least a bus bar, which is provided between the plurality of inner leads arranged in rows facing each other and the die pad.

The present invention then provides an offset chip-stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of outer leads, a plurality of inner leads arranged in rows facing each other, and a die pad, wherein the die pad is provided between the plurality of inner leads and is vertically distant from the plurality of inner leads; a plurality of offset chip-stacked structures set on the die pad and electrically connected to the plurality of inner leads arranged in rows facing each other; and an encapsulant covering the plurality of offset chip-stacked structures and the leadframe, the plurality of outer leads extending out of the encapsulant; wherein the leadframe comprises at least a bus bar provided between the plurality of inner leads and the die pad.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments are shown. In the following, the well-known knowledge regarding the chip-stacked structure of the invention such as the formation of chip and the process of thinning the chip would not be described in detail to prevent from arising unnecessary interpretations. However, this invention will be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

According to the semiconductor packaging process, a Front-End-Process experienced wafer is performed a thinning process to reduce the thickness to a value between 2 mil and 20 ml, and then the polished wafer is applied with a polymer material such as a resin or a B-Stage resin by coating or printing. Next, a post-exposure baking or lighting process is applied to the polymer material so that the polymer material becomes a viscous semi-solidified gel-like material. Subsequently, a removable tape is attached to the gel-like material with capable of viscous semi-solidified, and then the wafer is sawed into chips or dies. At last, these chips or dies are stacked on and connected to a substrate to form a chip-stacked structure.

Referring toFIGS. 2A and 2B, a chip200experiencing the above-mentioned processes has an active surface210and a back surface220in opposition to the active surface210with an adhesive layer230that is formed on the back surface220. It is to be noted that the adhesive layer230is not limited to the above-mentioned semi-solidified gel-like material and can be any adhesive material, such as die-attached film, for joining the chip200and a substrate together. Moreover, the active surface210is thereon provided with a plurality of pads240arranged along a side edge. Accordingly, an offset chip-stacked structure30as shown inFIG. 2Ccan be formed. The offset chip-stacked structure30is a ladder-like structure formed by aligning the side edge of upper chips with the edge line260of the bonding area250on lower chips. The edge line260herein is a presumed line for reference only but not a line exists on chip200.

Referring toFIG. 2D, the uppermost chip of the structure30can further have same pads as the pads240on the other side for providing more connections with the substrate. Referring toFIG. 2E, the uppermost chip of the structure30can have size smaller than that of the lower one. The arrangement of the pads240or the size of the chips described herein is for embodying but not limiting the invention. Any chip-stacked structure satisfying the above-mentioned statement would be regarded as an aspect of the invention.

Referring toFIGS. 3A to 3C, the process of making a chip with a redistribution layer is disclosed. According to the present invention, the redistribution layer (RDL) is formed with a plurality of pads provided on one side edge of the chip and the details are described as follows.

As shown inFIG. 3A, the chip310has first pads312aand second pads312bon the active surface and along side edges. The first pads312aare located inside a bonding area320, while the second pads312bare located outside the bonding area320. As shown inFIG. 3B, a first passivation layer330with a plurality of first openings332for exposing the first pads312aand the second pads312bis first formed on the chip310, and a redistribution layer340with a plurality of conductive wires342and a plurality of third pads344is then formed on the first passivation layer33. The third pads344are located inside the bonding area320and the plurality of conductive wires342that is electrically connected to the second pads312band the third pads344. The redistribution layer340is made up of conductive materials such as gold, copper, nickel, titanium tungsten, titanium or others. As shown inFIG. 3C, the chip structure300is completed by forming a second passivation layer350with a plurality of second openings352on the redistribution layer340to cover the area rather than the first pads312aand the third pads344but expose the first pads312aand the third pads344.

It is to be noted that the first pads312aand the second pads312bcan be arranged on the surface of the chip310not only in the above-mentioned peripheral type but also in an area array type or other types rather than the above-mentioned types, provided that the second pads312bare electrically connected with the third pads344via the conductive wires342. Moreover, the third pads344can be arranged in a manner of being along side edge of the chip310and in parallel to the pads312asuch as shown inFIG. 3Bor other manners provided that the third pads344are located inside the bonding area320.

Referring now toFIGS. 4A and 4B, show the cross-section views drawn along section lines A-A′ and B-B′. As shown inFIGS. 4A and 4B, the whole chip structure300is composed of the chip310and the redistribution layer400. The redistribution layer400is composed of first passivation layer330, redistribution layer340, and second passivation layer350. The presumed bonding area320of the chip310is a side edge adjacent to the chip310. Moreover, the chip310has a plurality of first pads312aand second pads312b, wherein the first pads312aare inside the bonding area320and the second pads312bare outside the bonding area320.

The first passivation layer330disposed on the chip310has a plurality of first openings332to expose these first pads312aand second pads312b. The redistribution layer340with a plurality of third pads344is disposed on the first passivation layer330and extends from second pads312bto presumed bonding area320, where the third pads are located. The second passivation layer350covers the redistribution layer340and expose first pads312aand third pads344through a plurality of second openings352. Since the first pads312aand third pads344are in the presumed bonding area320, the area rather than the bonding area320on the second passivation layer350is capable of carrying another chip structure and therefore accomplishing an offset chip-stacked structure.

Referring toFIG. 5, shows an offset chip-stacked structure50of the present invention. An offset chip-stacked structure50includes a plurality of stacked chips500. Each of the chips500is formed with a redistribution layer400so that each of the chips500can be provided with pads inside the bonding area320on each chip. In this way, the offset chip-stacked structure50is formed by aligning the side edge of upper chips with a presumed edge line of the bonding area320on lower chips and an adhesive layer230formed by a polymer material is used to connect any two chips among the plurality of chips500. Moreover, as shown in the present embodiment inFIG. 5B, the uppermost chip of the offset chip-stacked structure50can further have same pads as the pads312on the other side for providing more connections with the substrate and the method for forming this kind of structure is as shown inFIG. 4. Referring toFIG. 5C, the uppermost chip of the offset chip-stacked structure50can have size smaller than that of the lower one. The arrangement of the pads312and344or the size of the chips500described herein is for embodying but not limiting the invention. Any chip-stacked structure satisfying the above-mentioned statement would be regarded as an aspect of the invention. For example, each of the chips500can be formed with bonding areas that are not only on the right side as shown inFIGS. 5A to 5Bbut also on the left side.

In the following, two offset chip-stacked structures each connected with leadframes according to the present invention will be disclosed, in which the above-mentioned offset chip-stacked structure50will be taken as an example for illustration. However, the following descriptions can also be applied to the above-mentioned offset chip-stacked structure30.

Referring toFIGS. 6A and 6B, shows the plane views of a chip-stacked package structure of the present invention. As shown inFIGS. 6A and 6B, the chip-stacked package structure comprises a leadframe600and an offset chip-stacked structure50, wherein the leadframe600is composed of a plurality of inner leads610arranged in rows facing each other, a plurality of outer leads (not shown), and a die pad620. The die pad620is provided between the plurality of inner leads610and is vertically distant from the plurality of inner leads. In the present embodiment, the offset chip-stacked structure50is fixedly connected to the die pad620with an adhesive layer230. The adhesive layer230in the present invention is not limited to the above-mentioned semi-solidified gel-like material and can be any adhesive material, such as die attached film, for joining the offset chip-stacked structure50and the die pad620together. Then metal wires640are provided for connecting chip-stacked structure50and the inner leads610of leadframe600.

Then, referring toFIGS. 6A and 6B, the leadframe600of chip-stacked package structure of the present invention further comprises at least a bus bar630provided between the die pad620and the plurality of inner leads610arranged in rows facing each other, wherein the bus bar630can be arranged in a stripe-shaped configuration, as shown inFIGS. 6A and 6B; meanwhile, the bus bar630can also be arranged in a ring-shaped configuration, as shown inFIGS. 7A and 7B. Moreover, as what is described above, the pads312/344in the bonding area320of chip500can be arranged in single row, as shown inFIGS. 6 and 7, or two rows, as shown inFIGS. 8A and 8B, and is not limited in the present invention.

The description will go to the part of using the bus bar630to accomplish jumping connections of metal wires640, referring toFIG. 6A. Referring again toFIG. 6A, the pad with letter “b” and the pad with letter “b′” on the chip500are connected to the inner lead6103and the inner lead6123respectively. Apparently, the bus bar6301and the bus bar6302can be served as transferring pads for making jumping connections between the pads with letter “b” and with “b′” and the inner leads6103and6123and thus the metal wires640would not cross each other. For example, a metal wire640has its one end connected to the pads with letter “b” and with “b′” on chip500and the other end connected to the bus bars6301and6302; then another wire640has its one end connected to the bus bars6301and6302and the other end connected to the inner leads6103and6123. Thus, the connection between the pads with letter “b” and with “b′” and the inner leads6103and6123can be made without crossing the wire connecting the pad with letter “c” and the inner lead6102. And in another embodiment, as shown inFIG. 6B, the jumping connection of two pads on chip500can be accomplished with a plurality of bus bar structures630. Referring toFIG. 6B, the pads with letter “a” and with “c′” on chip500are connected to the inner leads6103and6101. The bus bar6301can be served as a transferring pad for the pad with letter “a”. A metal wire640first connects the pad with letter “a” and the bus bar6301, and another metal wire640connects the bus bar6301and the inner lead6103. The bus bar6302can be served as a transferring pad for the connection between the pad with letter “c” and the inner lead6101with a metal wire640. Moreover, on another side of the leadframe600, the bus bar6303can be served as a transferring pad for the pad with letter “b′”. A metal wire640connects the pad with letter “b′” and the bus bar6303, and another metal wire640connects the bus bar6303and the inner lead6123. Consequently, the bus bars630in the leadframe600according to the present invention provides a plurality of transfer pads for jumping connections to prevent metal wires from crossing each other and avoid unnecessary short. Meanwhile, the bus bars630make the circuit design more flexible and raise the reliability in package processing. The connection of metal wires can also be performed in the embodiments inFIGS. 7 and 8according to the structure of bus bars630.

It is to be noted that the offset chip-stacked structure50is set on the leadframe600and the chips500can be that having same size and performing same function such as memory chips or chips having different sizes and performing different functions such as the case shown inFIGS. 2E and 5C(the chips on the uppermost layer being drive chips and the rest being memory chips). The detailed description for size and function of these chips is omitted hereinafter.

Referring toFIG. 9, which is a cross-sectional view of the offset chip-stacked package structure inFIG. 6Adrawn along section line A-A or inFIG. 7Adrawn along section line B-B. As shown inFIG. 9, the leadframe600and the offset chip-stacked structure50are connected with a plurality of metal wires640, wherein the leadframe600is composed of a plurality of inner leads610arranged in rows facing each other, a plurality of outer leads (not shown), and a die pad620. The die pad620is provided between the plurality of inner leads610and is vertically distant from the plurality of inner leads610, at least a bus bar630being provided between the inner leads610and the die pad620. In the present embodiment, the bus bar630and the die pad620are vertically at the same height. The metal wire640ahas one end connected to the first pad312aor third pad344of the chip500a(first pad312aor third pad344described inFIG. 3for example) and has the other end connected to the first pad312aor third pad344of the chip500bin a wire-bonding process. Similarly, the metal wire640bhas one end that connected to the first pad312aor third pad344of the chip500band has the other end that connected to the first pad312aor the third pad344of the chip500cvia a wire-bonding process. The metal wire640chas one end that connected to the first pad312aor third pad344of the chip500cand has the other end that connected to the first pad312aor the third pad344of the chip500dvia a wire-bonding process. The metal wire640dhas one end connected to the first pad312aor third pad344of the chip500aand has the other end connected to the inner leads610in a wire-bonding process. In this way, the chips500a,500b,500cand500dare electrically connected to the leadframe600when the wire-bonding processes of the metal wires640a,640b,640c, and640dare completed, wherein these metal wires640can be gold made wires.

Moreover, the leadframe600is provided with bus bar630as transferring pad for electrical connections such as power connections, ground connections, or signal connections. For example, when the bus bar630is served as transferring pad for electrical connection, the metal wire640ehas its one end connected to a pad (pad with letter “b′” for example) of the chip500aand has its other end connected to a bus bar (the bus bar6302for example), and the metal wire640hhas its one end connected to the bus bar6302and has its other end connected to one of the inner leads (inner lead6122for example). Moreover, the uppermost chip500dof the structure50can further have same pads as the pads312and344on the other side such as the arrangement shown inFIGS. 2D and 5B. Therefore, on the other side of chip500d, a plurality of metal wires640fare used to connect the chip500d(pad with letter “a” for example) and the inner leads610(inner lead6102for example), while a metal wire640ghas its one end connected to a pad (pad with letter “b” for example) of chip500dand the other end connected to a bus bar (bus bar6301for example) and a metal wire640iis used to connect the bus bar6301and one of the inner leads (inner lead6103for example).

It is to be noted that the chip500bis stacked on and adhered to the area outside the bonding area320of the chip500avia a polymer material made adhesive layer. However, the wire-bonding sequence of the metal wires640is not limited herein, which means it is also allowable to first bond the uppermost chip500dand finally bond the lowermost chip500aand then connect the chip500awith the leadframe600.

Referring toFIG. 10, which is a cross-sectional view of another embodiment of offset chip-stacked package structure inFIG. 6Adrawn along section line A-A or inFIG. 7Adrawn along section line B-B. As shown inFIG. 10, the leadframe600and the offset chip-stacked structure50are connected with a plurality of metal wires640, wherein the leadframe600is composed of a plurality of inner leads610arranged in rows facing each other, a plurality of outer leads (not shown), and a die pad620. The die pad620is provided between the plurality of inner leads610and is vertically distant from the plurality of inner leads610, at least a bus bar630being provided between the inner leads610and the die pad620. In the present embodiment, the bus bar630and the inner leads610are vertically at the same height. After the offset chip-stacked structure50and the leadframe600are connected, the wire bonding process between the leadframe600and the offset chip-stacked structure50is then performed. The process of connecting the leadframe600and the offset chip-stacked structure50with metal wires640is the same as what is described above and would not be given unnecessary detail. Meanwhile, the leadframe600in the present embodiment is provided with bus bar630which can be used for electrical connections such as power connections, ground connections or signal connections via the connection of metal wires640.

Then, referring toFIG. 11, which is a cross-sectional view of another embodiment of offset chip-stacked package structure inFIG. 6Awhich drawn along section line A-A or inFIG. 7Awhich drawn along section line B-B. The only difference between the leadframe and the offset chip-stacked structure50inFIG. 11and those inFIGS. 9 and 10is that the bus bar630is vertically at different heights, wherein the bus bar630inFIG. 11is provided between the inner leads610and the die pad620of leadframe600, the bus bar630being vertically distant from the inner leads610and the die pad620. Similarly, after the offset chip-stacked structure50and the leadframe600are connected, the wire bonding process of metal wires640between the leadframe600and the offset chip-stacked structure50is then performed. The process of connecting the leadframe600and the offset chip-stacked structure50with metal wires640is the same as what is described above and would not be given unnecessary detail. Meanwhile, the leadframe600in the present embodiment is provided with bus bar630which can be used for electrical connections such as power connections, ground connections or signal connections.

Then, referring toFIG. 12, which is a cross-sectional view of still another embodiment of offset chip-stacked package structure inFIG. 6Adrawn along section line A-A or inFIG. 7Adrawn along section line B-B. The leadframe600in the present embodiment is composed of a plurality of inner leads610arranged in rows facing each other, a plurality of outer leads (not shown), and a die pad620. The die pad620is provided between the plurality of inner leads610and is vertically at the same height as the plurality of inner leads610, at least a bus bar630being provided between the inner leads610and the die pad620. The bus bar630is vertically distant from the inner leads610and the die pad620. Similarly, after the offset chip-stacked structure50and the leadframe600are connected, the wire bonding process of metal wires640between the leadframe600and the offset chip-stacked structure50is then performed. The process of connecting the leadframe600and the offset chip-stacked structure50with metal wires640is the same as what is described above and would not be given unnecessary detail. Meanwhile, the leadframe600in the present embodiment is provided with bus bar630which can be used for electrical connections such as power connections, ground connections or signal connections.

As described in the above embodiments, the number of the chips of the chip-stacked structure50is not limited, and any skilled in the art could manufacture a chip-stacked structure including at least three chips according to the above-disclosed method. Meanwhile, the direction toward which the offset of each chip occurs in forming the structure50is not so limited by the above-disclosed embodiments. The chip-stacked structure can be formed with each chip having an offset toward the direction opposite to the original one disclosed in the above embodiments, as shown inFIG. 13. Referring toFIG. 13, the connection method for the chips of the structure70and the wire-bonding method for the chips and the leadframe are similar to that disclosed in the above-mentioned embodiments and would not be given unnecessary details herein.

Moreover, the present invention proposes a combination structure in which two offset chip-stacked structure with chips of each structure being offset toward opposite directions are combined together. An example of such is shown inFIG. 14. Referring toFIG. 14, the structures50and70are provided together on a die pad620of a leadframe600. The connection method for the chips of the structures70and50and the wire-bonding method for the chips and the leadframe are similar to that disclosed in the above-mentioned embodiments and would not be given unnecessary details herein. Moreover, the leadframe600in the present embodiment is provided with bus bar630as transferring pad for electrical connections such as power connections, ground connections, or signal connections. It is to be noted that the configuration and the number of the bus bar630here are examples only and do not limit the structure and the number of bus bar630when different circuit designs are considered.