Method and system for generating an integrated circuit chip facility waveform from a series of chip snapshots

Methods and corresponding test systems for generating a chip facility waveform from a series of chip snapshots. The methods including, (i) testing an integrated chip multiple times, each time increasing a clockstop delay delaying a clockstop generated by triggered error condition each time determining the state of state holding elements of the integrated circuit and (ii) testing an integrated circuit chip one time to generate a error condition and determining multiple times the states of state holding elements of the integrated circuit based on previous states of the state holding elements.

FIELD OF THE INVENTION

The present invention relates to the field of error management in integrated circuit chip technology; more specifically, it relates a method and system for generating a chip facility waveform from a series of chip snapshots.

BACKGROUND OF THE INVENTION

Complex integrated circuit chips can experience a type error conditions that is data dependent and generates a clockstop condition making it difficult to determine the origin of the error condition. Therefore, there is a need to mitigate the deficiencies and limitations described hereinabove.

SUMMARY OF THE INVENTION

A first aspect of the present invention is a method, comprising: (a) selecting a set of state holding elements of an integrated circuit; (b) configuring a clockstop request delay to an initial number of clock cycles; (c) generating an error condition in the integrated circuit chip; (d) generating a clockstop request in response to the error condition; (e) delaying the clockstop request by a number of clock cycles equal to the clockstop request delay; after (e), (f) reading out a state of each state holding element of the set of state holding elements; after (f), (g) incrementing the clockstop request delay by a fixed number of clock cycles; and after (g), (h) repeating steps (c) through (f) a predetermined number of times or until an instruction to stop.

A second aspect of the present invention is a test system including a computer comprising a processor, an address/data bus coupled to the processor, and a computer-readable memory unit coupled to communicate with the processor, the memory unit containing instructions that when executed by the processor implement a method for generating a chip facility waveform, the method comprising the computer implemented steps of: (a) selecting a set of state holding elements of an integrated circuit; (b) configuring a clockstop request delay to an initial number of clock cycles; (c) generating an error condition in the integrated circuit chip; (d) generating a clockstop request in response to the error condition; (e) delaying the clockstop request by a number of clock cycles equal to the clockstop request delay; after (e), (f) reading out a state of each state holding element of the set of state holding elements; after (f), (g) incrementing the clockstop request delay by a fixed number of clock cycles; and after (g), (h) repeating steps (c) through (f) a predetermined number of times or until an instruction to stop.

A third aspect of the present invention is a method comprising: (a) selecting a set of state holding elements of an integrated circuit; (b) generating an error condition in the integrated circuit chip; (c) generating and executing a clockstop request in response to the error condition; after (c), (d) generating a snapshot of actual states of each of the state holding elements of the set of state holding elements; (e) determining next previous states of each state holding element of the set of state holding elements based on respective states of each state holding element of the set of state holding element of a last generated snapshot and based on a description of circuit elements of the integrated circuit chip and interconnections between the circuit elements; after (e), (f) generating a snapshot of the next previous states of each state holding element of the set of state holding elements; and after (f), (g) repeating steps (e) and (f) a predetermined number of times or until an instruction to stop.

A fourth aspect of the present invention is a test system including a computer comprising a processor, an address/data bus coupled to the processor, and a computer-readable memory unit coupled to communicate with the processor, the memory unit containing instructions that when executed by the processor implement a method for generating a chip facility waveform, the method comprising the computer implemented steps of: (a) selecting a set of state holding elements of an integrated circuit; (b) generating an error condition in the integrated circuit chip; (c) generating and executing a clockstop request in response to the error condition; after (c), (d) generating a snapshot of actual states of each of the state holding elements of the set of state holding elements; (e) determining next previous states of each state holding element of the set of state holding elements based on respective states of each state holding element of the set of state holding element of a last generated snapshot and based on a description of circuit elements of the integrated circuit chip and interconnections between the circuit elements; after (e), (f) generating a snapshot of the next previous states of each state holding element of the set of state holding elements; and after (f), (g) repeating steps (e) and (f) a predetermined number of times or until an instruction to stop.

DETAILED DESCRIPTION OF THE INVENTION

A clock signal is defined as a repeating pulsed signal and a clock cycle is defined at the time between adjacent rising edges of the pulsed signal. A state holding element is defined as an element that may be in a logical zero state or a logical one state. Examples of state holding elements include but are not limited to latches and memory elements. Examples of memory elements include but are not limited to dynamic random access memory cells, and static random access memory cells.

FIG. 1illustrates basic components of an integrated circuit chip to which embodiments of the present invention may be applied. The exemplary integrated circuit chip ofFIG. 1is an I/O subsystem integrated circuit chip100that performs protocol conversions and checking as well as fan-out functionality in a computer network environment. Chip100includes a higher link unit105connected to a root complex of functional units110,115,120and125arranged in a logical tree (the arrangement is exemplary of any cone of logic or arrangement of functional circuits), and lower link units130,135,140and145. In one example, upper link unit105and lower links units130,135,140and145support a same link protocol. Chip100also includes a clockstop-trace stop preparation logic (CTPL)150, which includes a clock cycle counter152, a clock control unit155, a trace unit and an error-handling unit165. Data paths (for transferring data packets) from higher link unit105, through functional logic units110,115,120and125to lower link units130,135,140, and145are labeled “DATA.” Clockstop request paths are labeled “CSR”, trace stop request paths are labeled TSR and inter-chip clockstop communications are labeled “ICC.” CTPL150and trace unit160are linked to a tester170and initialization, control signals and data collected in trace unit160are passed between CTPL150and trace unit160and tester170by paths labeled “TEST.”

In operation, when an error condition that is too severe to handled within functional unit125is detected by an internal error detection unit in functional unit125, a clockstop request is generated which is transmitted to error handling unit165. Error handling unit165generates a clockstop request, which is transmitted to CTPL150and delayed based on the contents of counter152before being transmitted to clock control unit155(as a delayed clockstop request), which will stop the functional chip clock (the clocks for higher link unit105, functional units110,115,120and125and lower link units130,135,140and145, but not non-functional clocks for the other components of chip100. Clock cycle counter152is initialized (e.g., to 0) by tester170to an initial number of counts. After each clock cycle starting with a clock cycle on which a clockstop request is issued by functional circuit125, clock cycle counter152is incremented (e.g., by 1 clock cycle). When clock cycle counter152reaches a predefined number clock cycles CTPL then passes the clockstop request as a delayed clockstop request to clock control unit155. At this time CTPL150also can be setup to transmit a trace stop request to trace unit160, which collects the current state of selected state holding elements of chip100and transmits the data to tester170. The specific state holding elements from which data is collected is also determined during initialization. Alternatively, the chip may be designed to perform a “chip dump” which is a readout of the state of all the state holding elements (e.g., latches in scan chains) of the chip so only a chip dump command is required. Tester170also initializes chip100and sends test data into higher link unit105via the normal DATA path.

In one example CTPL150is implemented in hardware. In one example, CTPL150is implemented as a software application.

While an I/O subsystem chip has been used as an example circuit, the embodiments of the present invention may be applied to other integrated circuit chips such as processors and memory controllers] having a CTPL configured according to the operational requirements of those chips.

FIG. 2is a flowchart of a method of generating a chip facility waveform according to a first embodiment of the present invention. In step200, for a particular integrated circuit chip, a reproducible error condition that generates a clockstop request and a trigger (e.g., in the example ofFIG. 1, processing a particular data packet) for that error condition are selected. In step,205the chip to be tested is initialized. Initialization includes “normal” initialization tasks such as initialing clocks, routings, and loading data (other than the trigger data). Initialization can also include selecting which state holding elements will be read out after a clockstop request is executed. Again, alternatively, the chip may be designed to perform a “chip dump” which is a readout of the state of all the state holding elements (e.g., latches in scan chains) of the chip so only a chip dump command is required. In step210, the chip is configured to generate a clockstop request when the error condition occurs. In step215, a clockstop request delay is configured to either an initial number of clock cycles the first time through step215or to an incremented number of clock cycles on subsequent times through step215. In step220, the error condition is generated, for example, by inputting trigger data (e.g., from a data file225) to the chip that is known to cause the error condition. In the example of chip100ofFIG. 1, this would be a data packet introduced into higher link unit105(seeFIG. 1). As processing of the trigger data by the chip progresses at some point the trigger data causes a clockstop request in step230. In step235, the clockstop is delayed by the initialized number of clock cycles and in step240, the clockstop is executed stopping further processing of data. In step245, the data from the selected state holding elements along with the clock cycle number since the start of processing of the trigger data is readout and stored (e.g., in a snapshot file250). The selected state holding elements may include all (if a chip dump is performed) or a subset of the state holding elements (selected during initialization step205) of the chip. In step255, it is determined if additional snapshots are required.

If in step255, additional snapshots are required the method proceeds to step260where the clockstop request delay is incremented by a fixed number of clock cycles and then back to step205to start another loop. This looping is repeated as many times as required to build up the snapshots required to generate a chip facility waveform, each loop generating a snapshot at a later clock cycle then the previous loop. The only difference between loops is the delay in the execution of the clockstop request becoming progressively longer.

If in step255, no additional snapshots are required then in step265a chip facility waveform is generated from the snapshots stored in snapshot file250. Alternatively, step265may be executed after each loop is completed and the chip facility waveform displayed as an animation of a group of snapshots with the older snapshots dropping off left side of the display as new snapshots are added to the right side of the display. The number of loops can be pre-programmed into the tester or stopped by an operator observing the animation.

It should be appreciated that steps205,210,215,245,255,260and265are performed by a tester connected to a physical chip under test and steps220,230,235and240are automatically performed by the chip. The tester includes a computer or is linked to a computer.

Because the clockstop may not occur for several clock cycles after introducing trigger data into the chip, the tester may be configured to readout snapshots of these earlier clock cycles by inserting optional step270between steps215and220and linking step270to file250. Physically this capability may reside in trace unit160ofFIG. 1or within the tester itself.

FIG. 3is a flowchart of a method of generating a chip facility waveform according to a second embodiment of the present invention. In step300, for a particular integrated circuit chip, a reproducible error condition that generates a clockstop request and a trigger (e.g., in the example ofFIG. 1, processing a particular data packet) for that error condition are selected. In step,305the chip to be tested is initialized. Initialization includes “normal” initialization tasks such as initialing clocks, routings, and loading data (other than the trigger data). Initialization also includes selecting which state holding elements will be read out after a clockstop is executed. Again, alternatively, the chip may be designed to perform a “chip dump” which is a readout of the state of all the state holding elements (e.g., latches in scan chains) of the chip so only a chip dump command is required. In step310, the error condition is generated, for example, by inputting trigger data (e.g., from a data file315) to the chip that is known to cause a fail. In the example of chip100ofFIG. 1, this would be a data packet introduced into higher link unit105(seeFIG. 1). As processing of the trigger data by the chip progresses at some point the trigger data results in a clockstop request being generated and executed in step320. In step325, the actual states of the selected state holding elements are determined and stored with a corresponding clock cycle value as a snapshot.

It should be appreciated that steps305and310are performed by a tester connected to a physical chip under test and step320is automatically performed by the chip. Subsequent steps330,335,340,350and355are performed using a simulator running on a computer that is linked to or part of the tester.

In a first time through step330, the states of the state holding elements determined in step325are combined with circuit design information (e.g., from a netlist335) to determine next previous states of the selected state holding elements. Thereafter, each time through step330the last determined states of the selected state holding elements, which are also the states of the last generated snapshot, are used to calculate next previous states of the selected state holding elements. The selected state holding elements may include all (if a chip dump is performed) or a subset of the state holding elements (selected during initialization step305) of the chip. In step340, the determined state holding element states along with the clock cycle associated with the determined state holding element states are stored in a snapshot file345. In step350, it is determined if additional snapshots are required.

Next previous states of state holding elements are defined as the state of the state holding elements one clock cycle before the clock cycle associated with the last generated snapshot. If the clock cycle of the first (and actual) snapshot is n, then the next previous states of the state holding elements occur in sequence at clock cycle n−1, n−2, n−3 etc. The n snapshot contains actual state holding element states. The n−1 snapshot contains calculated state holding element states based on the actual state holding element states of the n snapshot. The n−2 through n−x (where x is one less than the total number of snapshots) contain calculated state holding element states based on previously calculated state holding element states of the n−1 through x snapshots respectively.

A netlist is a data file describing circuit elements such as logic gates, state holding elements, registers, memory elements, to give a few examples, and interconnections between the elements. In the example ofFIG. 1, the portion of the netlist of chip100of interest in step330is higher link unit105, functional units110,115,120and125and lower link units130,135,140and150. Other types of data files besides netlists, such as high level description language files (e.g., VHDL, verilog, SystemC) or any other suitable description of the circuit elements and interconnections between the circuit elements may be used.

If in step350, additional snapshots are required the method loops back to step330where the next previous states of the selected state holding elements are calculated one clock cycle earlier than the clock cycle than the clock cycle to the last loop through step330using netlist335and the state holding element states of the previous snapshot. This looping is repeated as many times as required to build up the snapshots required to generate a chip facility waveform/chip facility waveform, each loop generating a snapshot at an earlier clock cycle. It should be understood that it may not be possible to determine a state of any given state holding element after several loops and provision should be made to include indications of “unknown” states in snapshots.

If in step350, no additional cycles are required then in step355a chip facility waveform is generated from the snapshots stored in snapshot file345. Alternatively, step355may be executed after each loop is completed and the chip facility waveform displayed as an animation of a group of snapshots with the older snapshots dropping left side of the display as new snapshots are added to the right side if the display. The number of loops can be pre-programmed into the simulator or stopped by an operator observing the animation. The looping may also be automatically terminated when the number of “unknown” states exceeds a predetermined threshold value (e.g., 50%).

FIG. 4is an exemplary chip faculty waveform generated by the embodiments of the present invention. InFIG. 4, a chip facility waveform includes a row for each selected state holding element, a first column of state holding element names, a second column of the value of the state holding element at a particular clock cycles, and a waveform section having a waveform for each state holding element extending over a number of clock cycles. Because there may be hundreds of clock cycles, when a chip facility waveform is displayed on display device such as a computer screen, the waveform section may be scrollable left and right and a cursor provided (dashed line) to select the values displayed in second column.

FIG. 5is a schematic block diagram of a computer portion of a tester for practicing the embodiments of the present invention. Generally, the method described herein with respect to a method for generating a chip facility waveform from a series of chip snapshots is practiced with a computer linked to or included in a test system and the methods described supra in the flow diagrams ofFIGS. 2 and 3may be coded as a set of instructions on removable or hard media for use by the computer.

InFIG. 5, computer400has at least one microprocessor or central processing unit (CPU)405. CPU405is interconnected via a system bus410to a random access memory (RAM)415, a read-only memory (ROM)420, an input/output (I/O) adapter425for a connecting a removable data and/or program storage device430and a mass data and/or program storage device435, a user interface adapter440for connecting a keyboard445and a mouse450, a port adapter455for connecting a data port460and a display adapter465for connecting a display device470. The tester may be connected to computer system400through an additional port adapter455.

ROM420contains the basic operating system for computer system400. The operating system may alternatively reside in RAM415or elsewhere as is known in the art. Examples of removable data and/or program storage device630include magnetic media such as floppy drives and tape drives and optical media such as CD ROM drives. Examples of mass data and/or program storage device435include electronic, magnetic, optical, electromagnetic, infrared, and semiconductor devices. Examples of a computer-readable medium include a semiconductor or solid-state memory, magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disk-read/write (CD-R/W) and DVD. In addition to keyboard445and mouse450, other user input devices such as trackballs, writing tablets, pressure pads, microphones, light pens and position-sensing screen displays may be connected to user interface440. Examples of display devices include cathode-ray tubes (CRT) and liquid crystal displays (LCD).

A computer program with an appropriate application interface may be created by one of skill in the art and stored on the system or a data and/or program storage device to simplify the practicing of this invention. In operation, information for or the computer program created to run the present invention is loaded on the appropriate removable data and/or program storage device430, fed through data port460or typed in using keyboard445.

Thus the embodiments of the present invention provide a method and system for generating a chip facility waveform from a series of chip snapshots that allow enhanced determination of the origin of integrated circuit chip clockstops and subsequent chip fails.