Current sensor integrated circuit with common mode voltage rejection

A current sensor integrated circuit to sense a current through a resistor includes a substrate, a tub disposed in the substrate, an analog front end disposed in the tub and comprising an amplifier having inputs coupled across the resistor and a charging circuit configured to bias the analog front end and the tub to a bias voltage that is a predetermined offset voltage greater than a common mode voltage associated with the resistor. In embodiments, the analog front end is biased to a first bias voltage and the tub is biased to a second, different bias voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

Not Applicable.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH

Not Applicable.

FIELD

This disclosure relates generally to current sensor integrated circuits (ICs) and more particularly such ICs including common mode voltage rejection circuitry and techniques.

BACKGROUND

Current sensor integrated circuits (ICs) are used in a wide variety of applications including motors, in which current through one or more motor windings is measured by measuring a voltage across a sense resistor coupled in series or “in-line” with the motor winding. Such current sensor ICs generate an analog or digital output signal indicative of the motor phase current as may be used in controlling motor position and speed.

In-line current sensing in a motor application and other applications can be complicated by relatively large common mode voltages experienced by the sense resistor and thus also by the circuitry coupled to detect the current through the sense resistor. For example, the voltage across the sense resistor can swing between ground and a high input supply voltage level. Further, because of the inductive nature of motor windings, the resistor voltage can in fact swing beyond the supply voltage range.

Various techniques are used to electrically isolate sense circuitry from sensed elements subjected to large common mode voltages. For example, in some arrangements, a multi-chip solution entails the use of multiple integrated circuits to isolate the sense circuitry from large common mode voltages.

SUMMARY

The present disclosure provides a current sensor integrated circuit and associated methods for biasing regions of the integrated circuit containing the sensing circuitry to a predetermined offset voltage greater than the common mode voltage. The described circuitry and methods can improve the accuracy of the resulting current sensing by rejecting the common mode voltage.

In one aspect, a current sensor integrated circuit includes a substrate, a tub disposed in the substrate, an analog front end disposed in the tub and including an amplifier having inputs coupled across a resistor, and a charging circuit configured to bias the analog front end and the tub to a bias voltage that is a predetermined offset voltage greater than a common mode voltage associated with the resistor.

The current sensor may include one or more of the following features. The common mode voltage associated with the resistor may be coupled to the analog front end and to the tub as a reference potential. The analog front end may further include a regulator configured to power the amplifier and coupled to receive the bias voltage as a regulator supply input voltage. The current sensor integrated circuit may further include a boot capacitor having a first terminal coupled to the charging circuit and to the regulator to provide the regulator supply input voltage and a second terminal coupled to the regulator to provide a reference potential to the regulator. The charging circuit may include a plurality of switches configured to selectively couple a fly capacitor to a charge pump voltage during a first clock phase and to decouple the fly capacitor from the charge pump voltage and couple the fly capacitor to the boot capacitor during a second clock phase. The predetermined offset voltage can be selected to prevent forward biasing of a junction between the tub and the substrate.

The charging circuit may include a first charging circuit portion configured to bias the analog front end to a first bias voltage that is a first predetermined offset voltage greater than the common mode voltage associated with the resistor and a second charging circuit portion configured to bias the tub to a second bias voltage that is a second predetermined offset voltage greater than the common mode voltage associated with the resistor, wherein the second predetermined offset voltage is different than the first predetermined offset voltage. The second predetermined offset voltage can be selected to prevent forward biasing of a junction between the tub and the substrate. The current sensor integrated circuit may further include a tub boot capacitor having a first terminal coupled to the second charging circuit portion and to the tub and a second terminal coupled to a p-well region disposed in the tub. The second charging circuit portion may include a plurality of switches configured to selectively couple a fly capacitor to a charge pump voltage during a first clock phase and to decouple the fly capacitor from the charge pump voltage and couple the fly capacitor to the tub boot capacitor during a second clock phase.

The substrate can be a semiconductor substrate comprised of a p-type material and the tub is an epitaxial tub comprised of an n-type material. The analog front end may further include an analog-to-digital converter coupled to an output of the amplifier to generate a digital signal having a value indicative of the current through the resistor. The current sensor integrated circuit may further include an output isolator coupled between the analog-to-digital converter and a digital processor, wherein the digital processor is configured to generate a sensor output signal indicative of the current through the resistor. The current sensor integrated circuit may further include an input isolator coupled between the digital processor and the analog front end and configured to transmit a clock signal from the digital processor to the analog front end for synchronization and use by the analog-to-digital converter.

According to a further aspect, a method of sensing a current through a resistor with a current sensor integrated circuit includes providing a substrate, forming an analog front end of the current sensor in a tub disposed in the substrate, wherein the analog front end includes an amplifier, amplifying, with the amplifier, a differential voltage across the resistor, and biasing the analog front end and the tub to a bias voltage that is a predetermined offset voltage greater than a common mode voltage associated with the resistor.

The method may include one or more of the following features. Forming the analog front end may include providing a regulator coupled to receive the bias voltage as a supply input voltage. Biasing the analog front end may include charging a fly capacitor to a charge pump voltage during a first clock phase and decoupling the fly capacitor from the charge pump voltage and coupling the fly capacitor to a boot capacitor coupled to the analog front end and the tub during a second clock phase.

Biasing the analog front end and the tub may include biasing the analog front end to a first bias voltage that is a first predetermined offset voltage greater than the common mode voltage associated with the resistor and biasing the tub to a second bias voltage that is a second predetermined offset voltage greater than the common mode voltage associated with the resistor, wherein the second predetermined offset voltage is different than the first predetermined offset voltage. The second predetermined offset voltage may be selected to prevent forward biasing of a junction between the tub and the substrate. Biasing the tub may include charging a fly capacitor to a charge pump voltage during a first clock phase and decoupling the fly capacitor from the charge pump voltage and coupling the fly capacitor to a tub boot capacitor coupled to the tub during a second clock phase.

Also described is a current sensor integrated circuit including a substrate, a tub disposed in the substrate, an analog front end disposed in the tub and including an amplifier having inputs coupled across the resistor and means for biasing the analog front end and the tub to a bias voltage that is a predetermined offset voltage greater than a common mode voltage associated with the resistor. The biasing means may include first biasing means for biasing the analog front end to a first bias voltage that is a first predetermined offset voltage greater than the common mode voltage associated with the resistor and second biasing means for biasing the tub to a second bias voltage that is a second predetermined offset voltage greater than the common mode voltage associated with the resistor, wherein the second predetermined offset voltage is different than the first predetermined offset voltage.

DETAILED DESCRIPTION

Referring toFIG. 1, a current sensor integrated circuit (IC)10is coupled to a resistor12ato sense a current through the resistor. The current sensor10has an analog front end20that includes a signal path32and a regulator22. The signal path32includes an amplifier24having inputs coupled across the sense resistor12aand an analog-to-digital converter (ADC)28coupled to an output of the amplifier24to generate a digital signal having a value indicative of the voltage across, and thus also the current through, the resistor12a.

Digital portions of the current sensor IC10, including a digital processor34, are coupled to the analog front end20through level-translating isolators30including output and input isolators30a,30b, respectively. Isolators30permit bidirectional communication between the analog front end20and low voltage digital circuitry. The isolators30can take various forms, including but not limited to differential capacitive isolators.

An analog front end (AFE) clock circuit80and AFE registers82form part of the analog front end20and are responsive to a clock signal from the digital processor34. With this arrangement, the analog front end clock is synchronized with the processor clock. Registers82can store configuration bits as may be used for various functions such as trimming a reference voltage.

Digital processor34is configured to generate one or more signals indicative of the current through the resistor12a. An interface38is coupled to the digital processor34and operates to generate one or more sensor output signals40in a desired format, including but not limited to a SPI format, a SENT format, or an VC format, for communication of the sensed current to external circuits and systems. Depending on the format, additional signal lines can include inputs to the interface38, as shown for the example SPI interface.

In some applications for the current sensor IC10, the sense resistor12acan experience significant common mode voltages. For example, referring also to the example motor control system application shown inFIG. 2, the resistor12acan be coupled in series with a motor winding and current sensor IC10can be thus, configured to sense a motor phase current. More particularly, a motor control system200includes a motor204as may be a three-phase brushless motor as one example, containing a plurality of windings, each coupled to a driver208. In this example, two of three motor windings are coupled to the driver208through a respective sense resistor12a,12b. The sense resistors12a,12bcan be coupled to the current sensor IC10(FIG. 1) for sensing the respective phase current. To this end, the current sensor IC10may include multiple channels (e.g., channel A14aand channel B14binFIG. 1), each having connections VINPx, VINNx coupled across a respective sense resistor12a,12b, as shown for sense resistor12ainFIG. 1. Output signals40of the current sensor IC10can be coupled to a motor controller220that is configured to generate motor control signals Hx70′, Lx72′.

More particularly, driver208includes pairs of switches coupled in parallel between a supply voltage VBUS216and ground218. In some automotive applications, the supply voltage VBUS216can have a nominal value of +48V. Nodes SA, SB, and SC between each pair of driver switches are coupled to an end of a respective motor coil. The illustrated switches are provided in the form of FETs, each having a gate terminal coupled to receive a control signal from motor control circuit220, which turns the switches on and off in a preordered sequence in order to selectively couple and decouple each motor winding to and from supply voltage VBUS216and ground218. In this way, motor control circuit220provides power to the motor204. For example, driver switches210,212are coupled together at node SA, which node is coupled to sense resistor12a. In the context ofFIG. 1, node SA is represented by IC connection Sx. The control signals for switches210,212are labeled Hx70′, Lx72′, respectively.

In the example application ofFIG. 2, the common mode voltage associated with each sense resistor12a,12bnominally can swing between VBUS216and ground218. However, because of the inductive nature of the motor windings and the rapid transitions of the driver control signals, some undershoot and overshoot can occur. In this arrangement in which the sense resistor's common mode voltage is driven through a large dynamic range, the resistor can be described as “flying” and the common mode voltage range can extend beyond the rails of the IC (i.e., extend beyond the range between the nominal IC supply voltage VCC68and ground218). In an example embodiment in which the VBUS voltage216is nominally +48V, the voltage at the sense resistors12a,12bcan swing from as high as +80V to as low as −16V. Sensing the current through the sense resistors12a,12bis complicated by the fact that the differential voltage across the resistors can be on the order of millivolts.

Referring again toFIG. 1, in order to reject the common mode voltage associated with the sense resistor12a, according to an aspect of the disclosure, the analog front end20is biased to a bias voltage F_VTUB42that is a predetermined offset voltage greater than a common mode voltage associated with the resistor. For example, the bias voltage F_VTUB42can be the first predetermined offset voltage greater than an externally driven common mode voltage as seen at IC connection Sx (referred to herein as common mode voltage Sx).

The current sensor IC10receives a supply voltage VCC68and can have a reference, or ground connection66(that can be the same as the ground connection218in the motor system application ofFIG. 2). The system voltage VBUS64(that can be the same as VBUS216in the motor system application ofFIG. 2) can provide a reference voltage for the sensor IC10. The current sensor IC10can further receive control signals Hx70, Lx72(as may be the same as or similar to the signals Hx70′, Lx72′ provided by the motor controller220to control driver switches210,212, respectively, in the motor system application ofFIG. 2) for use in generating the bias voltage F_VTUB42as will be explained. The signals Hx70, Lx72can be logically equivalent to motor control signals Hx70′, Lx72′ but may have different voltage levels. For example, the motor control signals Hx70′, Lx72′ may be amplified and level-shifted versions of control signals Hx70, Lx72(FIG. 1) to permit the motor driver FETs to be properly turned on and off.

The analog front end20includes a regulator22coupled to an IC connection Cx to receive the bias voltage F_VTUB42as a positive supply voltage input and to IC connection Sx (which is the externally driven resistor common mode voltage) to receive a F_VNEG reference voltage44as a negative supply voltage input. The regulator22is configured to generate a regulated voltage F_VREG26to power the amplifier24and other circuitry of the signal path32. In one example embodiment, the nominal regulated voltage F_VREG26can be 3.3 volts. With this arrangement, the amplifier24is powered by the F_VREG voltage26referenced to the negative supply voltage input F_VNEG44(which F_VNEG voltage44is also the resistor common mode voltage at connection Sx), thereby rejecting common mode voltage in the differential measurement of the voltage across the resistor12a.

Referring also to the simplified cross-sectional view of the current sensor IC inFIG. 3, the current sensor IC10can include a substrate316and a tub318disposed in the substrate, with the analog front end20disposed in the tub. In the current sensor IC10ofFIG. 1, both the analog front end20and the tub318are biased to the bias voltage F_VTUB42. It will be appreciated that tub318need not be a single tub, but rather, can be split into more than one tub which tubs may be biased to the same voltage. In order to provide voltage isolation between the commonly biased analog front end20and tub318and the low voltage circuitry supported by the substrate, in some embodiments, the bias voltage F_VTUB42can be on the order of +15V greater than the common mode voltage Sx in order to prevent forward biasing of the junction320between the tub and substrate. In the embodiment ofFIG. 5, the analog front end20and the tub318are biased to different bias voltages as will be explained.

The analog front end circuitry20is formed in p-well regions326a-326din the tub318. More particularly, regulator22can be formed in p-well region326aand additional active front end circuitry can be constructed in p-type regions326b,326c,326d, as shown.

The substrate316can be a semiconductor substrate or wafer, as may be comprised of a p-type material. The tub318can be formed by an epitaxial process and can be an n-type material. It will be appreciated that other processes and/or materials may be possible.

A junction (i.e., a p-n silicon junction)320between the substrate316and tub318is pictorially represented by a diode that forms an isolation barrier (i.e., an open circuit) when the n-side is biased higher than the p-side. Additional p-n junctions330a,330b,330c,330dare shown between the p-type regions326a,326b,326c,326dand the tub318, respectively.

Substrate316is coupled to ground66(FIG. 1). The tub318is coupled to the bias voltage F_VTUB42and the regulator22is coupled to receive the bias voltage F_VTUB42referenced to negative supply voltage F_VNEG44, as shown. P-well regions326a-326dare coupled to reference voltage F_VNEG44and front end circuitry within p-well regions326b-326dis coupled to receive the regulated voltage F_VREG26referenced to reference voltage F_VNEG44, as shown.

By biasing the tub318to a potential that prevents the junction320from becoming forward biased (i.e., to a potential approximately 16V higher than the substrate316), an isolation barrier between the analog front end20and the substrate316is achieved even when the voltage at sense resistor12ais below ground, as is desirable to protect the circuitry within the substrate316from the high voltages experienced by the biased tub318. The tub318biased in this manner can be referred to as an isolation tub.

Furthermore, by biasing the p-well regions326a-326dto reference voltage F_VNEG44, a reverse bias is provided across their junctions330a-330dwith the n-epi tub318that is biased to F_VTUB42. In this way, another isolation layer or barrier is formed between the analog front end20and the substrate316. More particularly, while the 16V bias F_VTUB42is a large enough potential to maintain the isolation at junction320during the undershoots that can occur during the commutation of the motor, it may be too large a voltage for many of the devices used in the AFE20(e.g., some such devices may have a maximum voltage between terminals of 6.5V or even 3.5V). These lower voltage AFE devices are contained in p-wells326b,326c,326dand thus, see a maximum voltage of F_VREG-F_VNEG.

Referring again toFIG. 1, to generate the bias voltage F_VTUB42, the current sensor IC10can include a charging circuit or block50, a charge pump54that boosts an IC supply voltage VCC68to a charge pump voltage VCP, a charge control circuit or block56, digital buffers58, a fly capacitor CFLY62, and a boot capacitor CBOOT52, all coupled as shown. The bias voltage F_VTUB42can be generated across the boot capacitor52such that the boot capacitor has a first terminal (at which the bias voltage F_VTUB42is provided) coupled to the charging circuit50and to the analog front end20and tub (at connection Cx) and a second terminal coupled to provide the reference potential F_VNEG44to the analog front end and tub (at connection Sx). It will be appreciated that while the charge pump54is not shown to be connected to an external capacitor, it is possible that one or more capacitors external to the IC10may be necessary depending on the voltage and current demands placed on the generated bias voltage F_VTUB42in the particular application.

As will be explained further in connection withFIGS. 4A-4Cbelow, the charging circuit50can include switches configured to selectively couple the fly capacitor CFLY62to a supply voltage (e.g., charge pump voltage VCP generated by charge pump54) during a first clock phase and to decouple the fly capacitor62from the supply voltage and couple the fly capacitor to the boot capacitor52during a second clock phase. In some embodiments, the first clock phase does not overlap with the second clock phase. When the fly capacitor62is being charged in the first clock phase, the boot capacitor52continues to supply power to the analog front end20. Thus, the boot capacitor52is selected to be large enough to supply power to the analog front end20without a large voltage droop between the refresh cycles. With this arrangement, the fly capacitor62is charged during the first clock phase and charge is transferred from the fly capacitor62to the boot capacitor52during the second clock phase.

It will be appreciated that the control signals for controlling the switches of the charging circuit50can be generated in various ways. For example, the control signals Hx, Lx can be externally generated, can be user programmable, preset, and/or derived from internal circuitry which monitors the voltage at Sx. In some embodiments, as explained in connection withFIGS. 4-4C, the control signals Hx70, Lx72can be application specific signals selected for use based on the expected common mode voltage Sx. More particularly, and as will become apparent, by using the motor control signals Hx70, Lx72to control the charging circuit50, charging modes are established based on the common mode voltage, as is desirable in order to maintain the desired voltage across the boot capacitor52so as to maximize the resulting common mode voltage rejection.

Referring toFIG. 4, operation of the charging circuit50will be explained in connection with example waveforms400, including an example common mode voltage waveform Sx (which common mode voltage provides the bias reference potential of F_VNEG44) and control signals Hx70, Lx72by which the common mode voltage Sx is generated. By control of signals Hx70, Lx72, motor driver switches (e.g., switches210,212ofFIG. 2) cause the voltage at node Sx (e.g., node SA ofFIG. 2) to have the relative shape and timing shown by example waveform of the reference voltage F_VNEG44inFIG. 4.

Control signals Hx70, Lx72are coupled to the charging control circuit56through buffers58, which charging control circuit56generates control signals for switches of the charging circuit50based on the state of motor control signals Hx70, Lx72. To this end, the charging control circuit56can include logic gates for example, in order to generate switch control signals according to the charging scheme explained in connection withFIGS. 4A-4C. Selective opening and closing of switches within the charging circuit50cause the fly capacitor62and boot capacitor52to be coupled in different configurations based on the state of the motor switches (e.g., switches210,212ofFIG. 2), which motor switch state is indicated by states of the motor control signals Hx70, Lx72.

As is apparent, control signals Hx, Lx are complementary in the sense that when one is high, the other is low and there is dead time404when both control signals are low. This is typical of motor driver control signals to ensure that there is no time during which paired high and low side switches are both on (e.g., switches210,212ofFIG. 2).

Charging of the boot capacitor52can be achieved in three example time periods or charging modes of operation of the charging circuit50(here labelled modes4A,4B,4C to reflect that they correspond to the configurations shown inFIGS. 4A, 4B, 4C, respectively) under the control of motor driver control signals Hx70, Lx72. Thus, each ofFIGS. 4A-4Ccorresponds to a different mode of the charging circuit50and thus, a different corresponding configuration of the switches of the charging circuit50. As will be apparent, only the closed switches are shown the various views ofFIGS. 4A-4Cfor simplicity of illustration. The left side of each suchFIG. 4A-4Ccorresponds to a first clock phase Φ1(i.e., a first portion of a clock cycle) and the right side corresponds to a second clock phase Φ2(i.e., a second, different portion of the clock cycle). Clock phases Φ1and Φ2are non-overlapping, with a dead time to account for delay mismatch.

The charging mode ofFIG. 4Acorresponds to a time when the Hx control signal70is at a logic low level and the Lx control signal72is at a logic high level and thus, when the low side driver switch (e.g., switch212ofFIG. 2) couples the sense resistor12ato ground (e.g., to ground connection218in the context ofFIG. 2). Thus, mode4A can be referred to as low-side charging. During the first clock phase Φ1of charging mode4A (shown on the left side ofFIG. 4A), the charging circuit50is configured to couple a first terminal of the fly capacitor CFLY62to the charge pump voltage VCP and a second terminal of the fly capacitor62to ground through closed switches420,422, respectively. Also during this first clock phase Φ1of theFIG. 4Acharging mode, the boot capacitor52is coupled to provide the analog front end20with the bias voltage F_VTUB42referenced to the common mode voltage F_VNEG44at connection Sx, as shown. In this configuration, the fly capacitor62is charged by VCP and the boot capacitor52powers the analog front end20.

Referring to the second clock phase Φ2of charging mode4A (shown on the right side ofFIG. 4A), the charging circuit50is now configured to decouple a first terminal of the fly capacitor62from the VCP voltage (e.g., by opening switch420) and instead to couple the first terminal of the fly capacitor62to the boot capacitor52with a closed switch424. The second terminal of the fly capacitor62remains coupled to ground through switch422. During this second clock phase Φ2of theFIG. 4Acharging mode, the boot capacitor52remains coupled to provide the analog front end20with the bias voltage F_VTUB42referenced to the common mode voltage F_VNEG44at connection Sx, as shown. In this configuration, the charge on the fly capacitor62is transferred to the boot capacitor52to refresh the boot capacitor charge and the analog front end20remains powered by the boot capacitor52, as shown.

The charging mode ofFIG. 4Bcorresponds to a time when the Hx control signal70is at a high level and the Lx control signal72is at a logic low level, and thus, when the high side driver switch (e.g., switch210ofFIG. 2) couples the sense resistor12ato the bus voltage VBUS (e.g., to connection216in the context ofFIG. 2). Thus, mode4B can be referred to as high-side charging. During the first clock phase Φ1of the charging mode ofFIG. 4B(shown on the left side ofFIG. 4B), the charging circuit50is configured to couple a first terminal of the fly capacitor62to the VCP voltage and a second terminal of the fly capacitor62to ground through switches420,422, respectively. Also during this first clock phase Φ1of theFIG. 4Bcharging mode, the boot capacitor52is coupled to provide the analog front end20with the bias voltage F_VTUB42referenced to the common mode voltage F_VNEG44at connection Sx, as shown. In this configuration, the fly capacitor62is charged by VCP and the boot capacitor52powers the analog front end20.

Referring to the second clock phase Φ2of the4B charging mode (shown on the right side ofFIG. 4B), the charging circuit50is now configured to decouple the first terminal of the fly capacitor62from VCP (e.g., by opening switch420) and instead to couple the first terminal of the fly capacitor62to the boot capacitor52with a closed switch424. The charging circuit50is further configured to couple the second terminal of the fly capacitor62to the bus voltage VBUS (e.g., connection64ofFIG. 1 or 216ofFIG. 2) through a closed switch426. During this second clock phase Φ2of theFIG. 4Bcharging mode, the boot capacitor52remains coupled to provide the analog front end20with the bias voltage F_VTUB42referenced to the common mode voltage F_VNEG44at connection Sx, as shown. In this configuration, the charge on the fly capacitor62is transferred to the boot capacitor52to refresh the boot capacitor charge and the analog front end20remains powered by the boot capacitor52, as shown.

As shown inFIG. 4, a third mode of the charging circuit50, charging mode4C, occurs between modes4A and4B. Mode4C can be considered a “standby” mode in which the fly capacitor62is not coupled to the boot capacitor52to refresh its charge. The purpose of this standby mode4C is to ensure that during transitions of the motor driver switches210,212(FIG. 2), when Sx is transitioning between at least ground and VBUS or vice versa, the fly capacitor62is not coupled to the boot capacitor52as is desirable to prevent unknown charging/discharging since the boot capacitor voltage is unknown during this transition time. The omission of a connection from Sx to either VBUS or to ground inFIG. 4Cis intended to illustrate that this mode4C occurs during times of transition between such connections.

More particularly, during the first clock phase Φ1of standby modeFIG. 4C(shown on the left side ofFIG. 4C), the charging circuit50is configured to couple a first terminal of the fly capacitor62to the VCP voltage and a second terminal of the fly capacitor62to ground in order to thereby charge the fly capacitor. Also during this first clock phase Φ1of mode4C, the boot capacitor52is coupled to provide the analog front end20with the bias voltage F_VTUB42referenced to the common mode voltage F_VNEG44at connection Sx, as shown, and is decoupled from the motor driver switches (both the high and low side switches210,212, respectively). In this configuration, the fly capacitor62is charged by VCP and the boot capacitor52powers the analog front end20.

The second clock phase Φ2of mode4C (shown on the right side ofFIG. 4C), is identical to the first clock phase Φ1of mode4C. Thus, the charging circuit50remains configured to couple the fly capacitor62between VCP and ground66. Also, the boot capacitor52is coupled to provide the analog front end20with the bias voltage F_VTUB42referenced to the common mode voltage F_VNEG44at connection Sx, as shown, and is decoupled from the motor driver switches (both the high and low side switches210,212, respectively).

ConsideringFIG. 4Cin connection withFIG. 4, the standby mode includes dead time404and a blanking time408a,408b. More particularly, when the motor control signal Lx72goes low at time t0, mode4C commences with dead time404. Once dead time404has lapsed at a time labeled t1with the motor control signal Hx being driven high, a blanking time408acommences to account for the delay required for the motor driver to drive Sx to its final value. This “blanking time” delay can programmable, including user programmable such as via EEPROM, to permit flexible implementation of the motor driver.

After the blanking time408a, at a time t2, Sx will have been driven high and it is considered safe to charge the boot capacitor52in mode4B as illustrated by the high-side charging on the right ofFIG. 4B.

The standby mode4C is repeated at the negative transition of Sx. At a time labeled t3, control signal Hx70goes low to initiate mode4C with dead time404. After the dead time404at a time t4, control signal Lx72goes high to commence blanking time408b(which can be the same as or different from the rising edge blanking time408a). Mode4A is entered after the blanking time408belapses at a time t5at which point Sx will have been driven low and it is considered safe to charge the boot capacitor52as illustrated on the right side ofFIG. 4A(low-side charging).

It will be appreciated that it is desirable that the standby mode4C not be any longer than necessary since during this time, the boot capacitor52is powering the analog front end20without being refreshed. For example, the Sx signal could have a period on the order of 100 μs with a duty cycle ranging from 10% to 90%. The blanking period (mode4C) can typically last a couple of microseconds.

As will be apparent to those of ordinary skill in the art, with the charging arrangement ofFIGS. 4-4C, the boot capacitor52is charged in a manner that leverages knowledge of the motor driver connections and thus of the common mode voltage associated with the sensed resistor12a. With this arrangement of controlling the charging circuit switches based on an indicator of the common mode voltage, the AFE circuitry is properly powered over the entire common mode range.

Referring toFIG. 5(in which like reference characters refer to like elements ofFIG. 1) and according to a further aspect of the disclosure, in connection with a further current sensor IC500, the analog front end520and the tub in which it is formed may be biased to different bias voltages. In particular, in the current sensor IC500, the analog front end520can be biased to a first bias voltage F_VCC514that is a first predetermined offset voltage greater than the common mode voltage associated with the resistor12a(as seen at IC connection Sx) and the tub318(FIG. 3) can be biased to a second bias voltage F_VTUB510that is a second, different predetermined offset voltage greater than the common mode voltage associated with the resistor (as seen at IC connection Sx).

Elements of the analog front end520can include regulator522(that can be the same as or similar to regulator22ofFIG. 1except for its supply voltage being F_VCC514rather than F_VTUB510) and signal path532(that can be the same as or similar to signal path32ofFIG. 1. Thus, signal path532can include amplifier524, ADC528, isolators530including output isolator530aand input isolator530b, clock circuit580and registers582, which elements can be the same as or similar to amplifier24, ADC28, isolators30including output isolator30aand input isolator30b, clock circuit80and registers82ofFIG. 1, respectively.

Generation of the first bias voltage F_VCC514can be achieved with a VREG charging circuit572, a fly capacitor CFLY562, a VREG charge pump574, and a charge pump capacitor CPUMP570, which operate to develop the first bias voltage F_VCC514across a first boot capacitor CBOOT1518, as will be explained. Thus, the first boot capacitor CBOOT1518is coupled to the analog front end520and more particularly to the regulator522, as shown. Generation of the second bias voltage F_VTUB510can be achieved with a VTUB charging circuit576and a VTUB charge pump578, which operate to develop the second bias voltage F_VTUB510across a second boot capacitor CBOOT2516, as will be explained. Thus, the second boot capacitor CBOOT2516is coupled to the tub318(FIG. 6) to provide the voltage isolation between the tub and substrate.

In embodiments, the first bias voltage F_VCC514is selected to ensure that the regulator522is supplied with a voltage and current sufficient to permit regulated voltage F_VREG526to be reliably generated for powering the analog front end circuitry and the second bias voltage F_VTUB510is selected to ensure that the junction320(FIG. 3) between the tub318and the substrate316does not become forward biased. In general, the first bias voltage F_VCC514can provide a higher current and lower voltage bias than the second bias voltage F_VTUB510and in one particular example, the first bias voltage F_VCC514can be on the order of +5V referenced to the common mode resistor voltage and the second bias voltage F_VTUB510can be on the order of +16V referenced to the common mode resistor voltage.

Referring also to the cross-sectional view of current sensor500inFIG. 6, it can be seen that the first bias voltage F_VCC514is coupled to the analog front end regulator522and the second bias voltage F_VTUB510is coupled to the tub318. This arrangement is in contrast to the current sensor IC ofFIG. 1(as may be referred to as a single bias implementation) in which F_VTUB provides a single bias to both regulator22and to the tub318. In this embodiment, analog front end circuitry within the tub318(other than the regulator522) can be powered by the first bias voltage F_VCC514or by the regulated voltage F_VREG526as is illustrated. In one particular example, the F_VCC bias voltage514can be on the order of 5V and the regulated voltage F_VREG526can be on the order of 3.3V.

With this biasing arrangement (as in the case of the biasing of current sensor10as shown inFIG. 1), the forward biasing of the junction320between the tub318and the substrate316is prevented as is desirable to protect low voltage circuitry from the high voltages of the flying tub318. Also, forward biasing of the junctions330a-330dbetween the p-well regions326a-326dand the tub318is likewise prevented as is desirable to protect low voltage circuitry from the high voltages of the flying tub318.

By separating the bias voltages to the analog front end520and to the tub318in the current sensor IC500ofFIG. 5, power consumption can be reduced. This is because the analog front end regulator522and other circuitry can operate with much lower voltage than is necessary to bias the tub318to prevent forward biasing of the junction320. Separating the bias into a higher voltage tub bias F_VTUB510and a lower bias F_VCC514allows for lower power dissipation. The tub bias F_VTUB510draws very little current, so power dissipation is not a concern with this bias signal.

A further advantage to separating the bias voltages to the analog front end520and to the tub318in the current sensor IC500ofFIG. 5is reduced noise presented to the regulator input at F_VCC514and thus also reduced noise on the regulated output F_VREG526. The isolation tub318presents a relatively large capacitive load on the tub bias voltage F_VTUB510, driven by boot capacitor CBOOT2516. This capacitance, on the order of 50-100 pF, is formed by the inherent reverse-biased diode capacitance between the isolation tub318and the substrate316. As the common mode voltage experiences rapid changes in voltage (fast transitions on connection Sx), this large capacitance demands large current from the boot capacitor516, resulting in sharp drops in boot capacitor voltage F_VTUB510. If this bias voltage F_VTUB510powered the regulator522, then these sharp drops in voltage could be seen at the input of the regulator and could partially or completely pass through to the regulator output. Separating the two bias voltages removes these sharp voltage drops from the regulator input signal and consequently, less power-supply noise is seen by all analog front end circuitry.

Referring again toFIG. 5and the example manner in which the first and second bias voltages are generated, consider first generating the first bias voltage F_VCC514. The VREG charging circuit572has as its input supply a charge pump voltage provided by VREG charge pump574. In an example embodiment, the charge pump574and CPUMP capacitor570operate to increase the VCC voltage568(e.g., 5V) to a slightly higher voltage level (e.g., 6.5V) as may be necessary to ensure that the regulator522can power analog front end circuitry at start up of the IC500. The VREG charging circuit572can include switches that are selectively opened and closed under the control of control signals Hx70, Lx72in order to charge the fly capacitor CFLY562and transfer the charge to the first boot capacitor CBOOT1518in the same general manner as explained above in connection withFIGS. 4-4C.

Now considering generating the second bias voltage F_VTUB510, VTUB charge pump578increases the VCC voltage568to supply a charge pump voltage to the VTUB charging circuit576. In the case of the VTUB charge pump578, there is no separate (e.g., external) capacitor shown as the charge pump capacitor may be internal to the IC500in some embodiments. The VREG charge pump574is shown coupled an external capacitor CPUMP570because of the higher current demand for the first bias voltage F_VCC.

The VTUB charging circuit576can include switches that are selectively opened and closed under the control of control signals Hx70, Lx72in order to charge a fly capacitor (not shown, but in the illustrated embodiment such fly capacitor is internal to the charging circuit576) and transfer the charge to the second boot capacitor CBOOT2516in the same general manner as explained above in connection withFIGS. 4-4C.

Having described preferred embodiments, it will now become apparent to one of ordinary skill in the art that other embodiments incorporating their concepts may be used. For example, it will be appreciated that components described in connection with the current sensor IC10(FIG. 1) and500(FIG. 5) can in some instances be external to the IC including, but not limited to the fly capacitors, boot capacitors, charging circuit, charging control circuit, and charge pumps. It will also be appreciated that various circuitry and techniques are possible for generating the described bias voltages, including circuitry external to the IC.

As used herein, the terms “processor” and “controller” are used to describe electronic circuitry that performs a function, an operation, or a sequence of operations. The function, operation, or sequence of operations can be hard coded into the electronic circuit or soft coded by way of instructions held in a memory device. The function, operation, or sequence of operations can be performed using digital values or using analog signals. In some embodiments, the processor or controller can be embodied in an application specific integrated circuit (ASIC), which can be an analog ASIC or a digital ASIC, in a microprocessor with associated program memory and/or in a discrete electronic circuit, which can be analog or digital. A processor or controller can contain internal processors or modules that perform portions of the function, operation, or sequence of operations. Similarly, a module can contain internal processors or internal modules that perform portions of the function, operation, or sequence of operations of the module.

While electronic circuits shown in figures herein may be shown in the form of analog blocks or digital blocks, it will be understood that the analog blocks can be replaced by digital blocks that perform the same or similar functions and the digital blocks can be replaced by analog blocks that perform the same or similar functions. Analog-to-digital or digital-to-analog conversions may not be explicitly shown in the figures but should be understood.

It is felt therefore that these embodiments should not be limited to disclosed embodiments, but rather should be limited only by the spirit and scope of the appended claims.