Synchronized solid-state imaging element, imaging device, and electronic device

There is provided a solid-state imaging element in which a first substrate in which a pixel circuit including a pixel array unit is formed and a second substrate in which a plurality of signal processing circuits are formed are laminated, and a common reference clock is supplied to the plurality of signal processing circuits that are formed on the second substrate.

TECHNICAL FIELD

The present disclosure relates to a solid-state imaging element, an imaging device and an electronic device, and specifically, to a solid-state imaging element, an imaging device and an electronic device through which it is possible to implement a configuration using divided exposure at a low cost.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a U.S. National Stage Application under 35 U.S.C. § 371, based on International Application No. PCT/JP2017/010849, filed in the Japanese Patent Office as a Receiving Office on Mar. 17, 2017, entitled “SOLID-STATE IMAGING ELEMENT, IMAGING DEVICE, AND ELECTRONIC DEVICE”, which claims priority under 35 U.S.C. § 119(a)-(d) or 35 U.S.C. § 365(b) to Japanese Patent Application JP 2016-072954, filed in the Japanese Patent Office on Mar. 31, 2016, the entire contents of each of which are hereby incorporated herein by reference.

BACKGROUND ART

In the related art, when a solid-state imaging element whose area is greater than an exposure range of an exposure device is manufactured, divided exposure in which a solid-state imaging element is divided into a plurality of regions and an exposure is performed for each of the divided regions is used (for example, refer to PTL 1).

In addition, in the related art, in order to increase an aperture ratio of a solid-state imaging element, a lamination technology in which a pixel circuit including a pixel array unit and a signal processing circuit are formed in different semiconductor substrates, and the two semiconductor substrates are laminated and are electrically connected is used (for example, refer to PTL 2).

Therefore, for example, when a solid-state imaging element having a lamination structure whose area is greater than an exposure range of an exposure device is manufactured, divided exposure is performed for each of the semiconductor substrates.

However, in the divided exposure, a different photomask is used for each of the divided regions, high-precision alignment is necessary in a connection portion of the divided regions, a manufacturing process is complex, and a manufacturing cost increases.

Therefore, a technology in which a first substrate in which a pixel circuit including a pixel array unit is formed and a second substrate in which a plurality of signal processing circuits are formed are laminated and thus a cost is reduced is proposed (for example, refer to PTL 3).

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

Incidentally, in the above-described technology in PTL 3, when a plurality of substrates in which a signal processing circuit is provided are arranged and laminated in a pixel circuit, substrates in which the same wiring is formed are arranged and laminated.

Here, when it is possible to implement all processes of a device with any one block among the same blocks that are provided in a plurality of arranged substrates that are laminated in a pixel circuit, a block of any one substrate among the plurality of substrates is caused to function and blocks of the other substrates are changed to a standby state that is a state in which a function is disabled.

Accordingly, the blocks in the standby state become a useless configuration. As a result, there is a risk of a manufacturing cost increasing.

In addition, in divided exposure, in order to provide a different function according to a position of a divided region, a substrate including different signal processing circuits having functions according to divided positions is prepared or corresponding different signal processing circuits are laminated according to divided positions, which consume much time and effort. As a result, there is a risk of a manufacturing cost increasing.

Further, in the divided exposure, even if all divided regions have the same circuit pattern, a difference is generated in electrical characteristics for each of the divided regions. Therefore, there is a risk of signal processes being not synchronized, and signal processing results being not unified. As a result, there is a risk of image quality decreasing.

The present disclosure has been made in view of the above-described circumstances. Specifically, the present disclosure is provided to achieve high image quality in a configuration using divided exposure at a low cost.

Solution to Problem

According to a first aspect of the present disclosure, there is provided a solid-state imaging element in which a first substrate in which a pixel circuit including a pixel array unit is formed and a second substrate in which a plurality of signal processing circuits are formed are laminated, and a common reference clock is supplied to the plurality of signal processing circuits that are formed on the second substrate.

A multiplier unit configured to multiply a reference clock supplied to the plurality of signal processing circuits may further be included. The plurality of signal processing circuits may use a clock signal multiplied by the reference clock by the multiplier unit for signal processing.

A reference clock may be supplied to one of the plurality of signal processing circuits and a signal processing circuit to which the reference clock is supplied may supply the reference clock to another signal processing circuits.

The multiplier unit configured to multiply the reference clock may be included in one of the plurality of signal processing circuits, and a reference clock may be supplied to the one of the plurality of signal processing circuits, and a clock signal multiplied by the multiplier unit may be supplied to the a signal processing circuit other than the one signal processing circuit among the plurality of signal processing circuits.

The reference clock and the clock signal multiplied by the reference clock may be supplied to the plurality of signal processing circuits.

A multiplier unit configured to multiply a reference clock supplied to the plurality of signal processing circuits may further be included. The signal processing circuit may include an analog signal processing unit configured to perform analog signal processing on a clock signal multiplied by the reference clock by the multiplier unit, and a digital signal processing unit configured to perform digital signal processing on a clock signal multiplied by the multiplier unit in another signal processing circuit to which the reference clock is supplied.

According to the first aspect of the present disclosure, there is provided an imaging device in which a first substrate in which a pixel circuit including a pixel array unit is formed and a second substrate in which a plurality of signal processing circuits are formed are laminated, and a common reference clock is supplied to the plurality of signal processing circuits that are formed on the second substrate.

According to the first aspect of the present disclosure, there is provided an electronic device in which a first substrate in which a pixel circuit including a pixel array unit is formed and a second substrate in which a plurality of signal processing circuits are formed are laminated, and a common reference clock is supplied to the plurality of signal processing circuits that are formed on the second substrate.

According to the first aspect of the present disclosure, a pixel circuit including a pixel array unit is formed and a second substrate in which a plurality of signal processing circuits are formed are laminated, and a common reference clock is supplied to the plurality of signal processing circuits that are formed on the second substrate.

According to a second aspect of the present disclosure, there is provided a solid-state imaging element in which a first substrate in which a pixel circuit including a pixel array unit is formed by a plurality of exposures and a second substrate in which a plurality of signal processing circuits are formed by a plurality of exposures are laminated, the solid-state imaging element including: a plurality of clamp computing units configured to compute a reference level based on output signals of a group of analog digital converting circuits (ADCs) that are included in the plurality of signal processing circuits of the second substrate; and a reference voltage output unit configured to convert a digital signal of the reference level computed by the clamp computing unit into a reference voltage of an analog signal, and supply the converted value to the ADCs of the ADC group.

The clamp computing unit is caused to compute a reference level based on outputs of an ADC group configured to convert signals of right pixels and an ADC group configured to convert left pixels at an exposure boundary of the first substrate.

An exposure boundary of the first substrate may match boundaries of the plurality of signal processing circuits of the second substrate.

The clamp computing unit may compute a reference level based on outputs of an ADC group in the vicinity of an exposure boundary of the second substrate.

According to the second aspect of the present disclosure, there is provided an imaging device in which a first substrate in which a pixel circuit including a pixel array unit is formed by a plurality of exposures and a second substrate in which a plurality of signal processing circuits are formed by a plurality of exposures are laminated, the imaging device including: a plurality of clamp computing units configured to compute a reference level based on output signals of a group of analog digital converting circuits (ADCs) that are included in the plurality of signal processing circuits of the second substrate; and a reference voltage output unit configured to convert a digital signal of the reference level computed by the clamp computing unit into a reference voltage of an analog signal, and supply the converted value to the ADCs of the ADC group.

According to the second aspect of the present disclosure, there is provided an electronic device in which a first substrate in which a pixel circuit including a pixel array unit is formed by a plurality of exposures and a second substrate in which a plurality of signal processing circuits are formed by a plurality of exposures are laminated, the electronic device including: a plurality of clamp computing units configured to compute a reference level based on output signals of a group of analog digital converting circuits (ADCs) that are included in the plurality of signal processing circuits of the second substrate; and a reference voltage output unit configured to convert a digital signal of the reference level computed by the clamp computing unit into a reference voltage of an analog signal, and supply the converted value to the ADCs of the ADC group.

According to the second aspect of the present disclosure, a first substrate in which a pixel circuit including a pixel array unit is formed by a plurality of exposures and a second substrate in which a plurality of signal processing circuits are formed by a plurality of exposures are laminated, a plurality of clamp computing units computes a reference level based on output signals of a group of analog digital converting circuits (ADCs) that are included in the plurality of signal processing circuits of the second substrate, and a reference voltage output unit converts a digital signal of the reference level computed by the clamp computing unit into a reference voltage of an analog signal, and supplies the converted value to the ADCs of the ADC group.

Advantageous Effects of Invention

According to an aspect of the present disclosure, it is possible to achieve high image quality in a configuration using divided exposure at a low cost.

DESCRIPTION OF EMBODIMENTS

Hereinafter, forms (hereinafter referred to as “embodiments”) for implementing the present technology will be described. The description will proceed in the following order.

1. First embodiment (example in which wiring layer having different left and right wiring patterns is formed on uppermost layer of wiring layer by one-shot exposure)

2. Second embodiment (example in which functions of left and right signal processing circuits are switched according to disposition)

3. Third embodiment (example in which reference clock signal is supplied to left and right signal processing circuits)

4. Fourth embodiment (example in which characteristic difference of ADC group is corrected)

5. Examples of application to electronic device

6. Use examples of solid-state imaging element

1. First Embodiment

FIG. 1is a perspective view schematically illustrating a configuration example of a solid-state imaging element1according to a first embodiment of the present technology. Here, while a case in which the solid-state imaging element1is a complementary metal oxide semiconductor (CMOS) image sensor is exemplified, the present technology is not limited to application to the CMOS image sensor.

The solid-state imaging element1is a semiconductor chip with a structure in which a pixel substrate11and a logic substrate12are laminated (a so-called lamination structure). In addition, the solid-state imaging element1is a back-illuminated CMOS image sensor and in which a wiring layer of the pixel substrate11and a wiring layer of the logic substrate12are laminated to be adjacent to each other. The present technology is not limited to application to the back-illuminated CMOS image sensor.

The pixel substrate11is a semiconductor substrate in which a pixel circuit21including a pixel array unit (a pixel unit)31in which unit pixels32including a photoelectric conversion element are two-dimensionally arranged in a matrix form is formed. In addition, although not illustrated, in a peripheral portion surrounding the pixel array unit31of the pixel circuit21, for example, a pad for electrical connection with the outside and a via for electrical connection with the logic substrate12are provided. A pixel signal obtained from each of the unit pixels32of the pixel array unit31is an analog signal, and the analog pixel signal is transmitted from the pixel substrate11to the logic substrate12through the via or the like.

The logic substrate12is a semiconductor substrate in which a signal processing circuit41L and a signal processing circuit41R whose circuit patterns are the same are formed to be arranged at the left and right through a scribing region42. In this drawing, a width of the scribing region42is widely exaggerated so that the drawing can be more easily understood. This is similar in subsequent drawings.

The signal processing circuit41L performs, for example, predetermined signal processing including digitization (AD conversion) of an analog pixel signal read from each of the unit pixels32within a left half region of the pixel array unit31and stores the signal-processed pixel data. In addition, the signal processing circuit41L reads, for example, the stored pixel data in a predetermined order and outputs the data to the outside of the chip. Accordingly, image data obtained by the unit pixel32within the left half region of the pixel array unit31is output from the signal processing circuit41L.

The signal processing circuit41R performs, for example, predetermined signal processing including digitization (AD conversion) of an analog pixel signal read from each of the unit pixels32within a right half region of the pixel array unit31and stores the signal-processed pixel data. In addition, the signal processing circuit41R reads, for example, the stored pixel data in a predetermined order and outputs the data to the outside of the chip. Accordingly, image data obtained by the unit pixel32within the right half region of the pixel array unit31is output from the signal processing circuit41R.

In addition, the signal processing circuit41L and the signal processing circuit41R are synchronized with, for example, the pixel circuit21, and control units of the solid-state imaging element1.

In this manner, according to a lamination structure of the pixel substrate11and the logic substrate12, an area of the pixel substrate11and an area of the pixel array unit31can be substantially the same. As a result, it is possible to reduce a size of the solid-state imaging element1and thus reduce a size of the entire chip. In addition, it is possible to increase an aperture ratio of the solid-state imaging element1.

Further, since a process appropriate for preparing the unit pixel32or the like can be applied to the pixel substrate11and a process appropriate for preparing the signal processing circuits41L and41R can be applied to the logic substrate12, it is possible to optimize the process when the solid-state imaging element1is manufactured.

The pixel circuit21has an area that is larger than an exposure range of an exposure device and thus divided exposure is necessary. On the other hand, the signal processing circuit41L and the signal processing circuit41R have areas that are smaller than the exposure range of the exposure device and one-shot exposure is possible.

Hereinafter, the signal processing circuit41L and the signal processing circuit41R will be simply designated as a signal processing circuit41when not being individually distinguished.

FIG. 2is a circuit diagram illustrating a specific configuration of the pixel circuit21of the pixel substrate11side and the signal processing circuits41L and41R of the logic substrate12side of the solid-state imaging element1. As described above, the pixel circuit21and the signal processing circuits41L and41R are electrically connected through a via (not illustrated).

First, a configuration of the pixel circuit21of the pixel substrate11side will be described. In the pixel circuit21, in addition to the pixel array unit31in which the unit pixels32are two-dimensionally arranged in a matrix form, a row selecting unit33configured to select each of the unit pixels32of the pixel array unit31in units of rows based on an address signal provided from the logic substrate12side is provided. Here, while the row selecting unit33is provided on the pixel substrate11side, it can be provided on the logic substrate12side.

The unit pixel32includes, for example, a photodiode51, as a photoelectric conversion element. In addition, the unit pixel32includes four transistors, for example, a transfer transistor (a transfer gate)52, a reset transistor53, an amplifying transistor54, and a selection transistor55, in addition to the photodiode51.

Here, as the four transistors52to55, for example, N channel transistors are used. However, a combination of conductivity types of the transfer transistor52, the reset transistor53, the amplifying transistor54, and the selection transistor55exemplified here is only an example, and the present disclosure is not limited to such a combination. In other words, a combination of P channel transistors can be used as necessary.

A transfer signal TRG, a reset signal RST, and a selection signal SEL that are drive signals for driving the unit pixel32are appropriately provided to the unit pixel32from the row selecting unit33. That is, the transfer signal TRG is applied to a gate electrode of the transfer transistor52, the reset signal RST is applied to a gate electrode of the reset transistor53, and the selection signal SEL is applied to a gate electrode of the selection transistor55.

The photodiode51has an anode electrode that is connected to a low potential side power supply (for example, a ground), photoelectrically converts received light (incident light) into light charges (here, photoelectrons) of a charge amount corresponding to a light intensity thereof, and accumulates the light charges. A cathode electrode of the photodiode51is electrically connected to a gate electrode of the amplifying transistor54through the transfer transistor52. A node56that is electrically connected to the gate electrode of the amplifying transistor54is referred to as a floating diffusion (FD) unit (a floating diffusion region).

The transfer transistor52is connected between the cathode electrode of the photodiode51and the FD unit56. A transfer signal TRG having a high level (for example, a VDDlevel) of active (hereinafter referred to as “High active”) is provided from the row selecting unit33to the gate electrode of the transfer transistor52. In response to the transfer signal TRG, the transfer transistor52is changed to a conductive state, and transfers light charges that are photoelectrically converted in the photodiode51to the FD unit56.

The reset transistor53includes a drain electrode that is connected to a pixel power supply VDDand a source electrode that is connected to the FD unit56. A reset signal RST of High active is provided from the row selecting unit33to the gate electrode of the reset transistor53. In response to the reset signal RST, the reset transistor53is changed to a conductive state, discards charges of the FD unit56to the pixel power supply VDDand thus resets the FD unit56.

The amplifying transistor54includes a gate electrode that is connected to the FD unit56and a drain electrode that is connected to the pixel power supply VDD. Therefore, the amplifying transistor54outputs a potential of the FD unit56that has been reset by the reset transistor53as a reset signal (reset level) Vreset. The amplifying transistor54further outputs a potential of the FD unit56after a signal charge is transferred by the transfer transistor52as a light accumulation signal (signal level) Vsig.

The selection transistor55includes, for example, a drain electrode that is connected to a source electrode of the amplifying transistor54and a source electrode that is connected to a signal line34. A selection signal SEL of High active is provided from the row selecting unit33to the gate electrode of the selection transistor55. In response to the selection signal SEL, the selection transistor55is changed to a conductive state, the unit pixel32is changed to a selection state, and a signal output from the amplifying transistor54is read in the signal line34.

As can be clearly understood from the above, from the unit pixel32, the reset potential of the FD unit56is read as a reset level Vreset, and the potential of the FD unit56after the signal charge is transferred is read as a signal level Vsigin order in the signal line34. Incidentally, the signal level Vsigalso includes a component of the reset level Vreset.

Here, while the selection transistor55has a circuit configuration that connects the source electrode of the amplifying transistor54and the signal line34, it can have a circuit configuration that connects the pixel power supply VDDand the drain electrode of the amplifying transistor54.

In addition, a pixel configuration of the unit pixel32is not limited to a pixel configuration including the four transistors. For example, a pixel configuration including three transistors in which the amplifying transistor54has a function of the selection transistor55, and a pixel configuration in which transistors subsequent to the FD unit56are shared among a plurality of photoelectric conversion elements (among pixels) may be used, and any configuration of the pixel circuit may be used.

Next, a configuration of the signal processing circuits41L and41R of the logic substrate12side will be described. As described above, the signal processing circuit41L and the signal processing circuit41R have the same circuit pattern. Here, the description will proceed, focusing on a configuration of the signal processing circuit41L.

The signal processing circuit41L is a circuit configured to process mainly a pixel signal from the unit pixel32within the left half region of the pixel array unit31. The signal processing circuit41L includes a current source61L, a decoder62L, a control unit63L, a row decoder64L, a signal processing unit65L, a column decoder/sense amplifier66L, a memory unit67L, a data processing unit68L, and an interface (IF) unit69L.

The current source61L is connected to each signal line34in which a signal is read from each of the unit pixels32of the pixel array unit31for each pixel column. The current source61L has, for example, a configuration of a so-called load MOS circuit including a MOS transistor in which a gate potential is biased to a constant potential so that a constant current is supplied to the signal line34. The current source61L including the load MOS circuit supplies a constant current to the amplifying transistor54of the unit pixel32of a selected row and causes the amplifying transistor54to operate as a source follower.

When each of the unit pixels32of the pixel array unit31is selected in units of rows under control of the control unit63L, the decoder62L provides an address signal for designating an address of the selected row to the row selecting unit33.

When pixel data is written in the memory unit67L or pixel data is read from the memory unit67L under control of the control unit63L, the row decoder64L designates a row address.

The signal processing unit65L includes at least AD converters81L-1to81L-n that perform digitization (AD conversion) of an analog pixel signal that is read from each of the unit pixels32of the pixel array unit31through the signal line34. Therefore, the signal processing unit65L has a configuration in which signal processing (column-parallel AD) of the analog pixel signal is performed in units of pixel columns in parallel. Hereinafter, the AD converters81L-1to81L-n will be simply designated as an AD converter81L when not being individually distinguished.

The signal processing unit65L further includes a reference voltage generating unit82L configured to generate a reference voltage that is used when AD conversion is performed in each of the AD converters81L. The reference voltage generating unit82L generates a reference voltage of a so-called ramp waveform (a slope-shaped waveform) whose voltage value is changed stepwise as a time has elapsed. The reference voltage generating unit82L can have a configuration using, for example, a digital-analog conversion (DAC) circuit.

The AD converter81L is provided, for example, for each pixel column of the pixel array unit31, that is, for each signal line34. In other words, the AD converter81L is a so-called column-parallel AD converter that is disposed only in a number of pixel columns of the left half of the pixel array unit31. Therefore, each of the AD converters81L generates, for example, a pulse signal having a size (a pulse width) in a time axis direction corresponding to a size of a level of a pixel signal, measures a length of a period of the pulse width of the pulse signal, and thus performs an AD converting process.

More specifically, for example, the AD converter81L-1has a configuration including at least a comparator (COMP)91L-1and a counter92L-1, as illustrated inFIG. 2. The comparator91L-1compares two inputs in which the analog pixel signal (the above-described signal level Vsigand reset level Vreset) read from the unit pixel32through the signal line34is used as a comparison input, and a reference voltage Vrefof a ramp wave supplied from the reference voltage generating unit82L is used as a reference input.

Therefore, the comparator91L-1has, for example, an output that is changed to a first state (for example, a high level) when the reference voltage Vrefis greater than a pixel signal, and has an output that is changed to a second state (for example, a low level) when the reference voltage Vrefis equal to or lower than a pixel signal. An output signal of the comparator91L-1is changed to a pulse signal having a pulse width corresponding to a level size of the pixel signal.

For example, an up/down counter is used for the counter92L-1. In the counter92L-1, a clock CK is provided at the same timing as a supply start timing of the reference voltage Vreffor the comparator91L. The counter92L-1, which is an up/down counter, performs down count or up count in synchronization with the clock CK, and thus measures a period of a pulse width of an output pulse of the comparator91L-1, that is, a comparison period from when a comparison operation starts until the comparison operation ends. When the measurement operation is performed, the counter92L-1performs down count for the reset level Vresetand performs up count for the signal level Vsigwith respect to the reset level Vresetand the signal level Vsigthat are sequentially read from the unit pixel32.

According to an operation of the down count/up count, it is possible to obtain a difference between the signal level Vsigand the reset level Vreset. As a result, in the AD converter81L-1, a correlated double sampling (CDS) process is performed in addition to the AD converting process. Here, the CDS process is a process in which a difference between the signal level Vsigand the reset level Vresetis obtained, and reset noise of the unit pixel32and pixel-specific fixed pattern noise such as a threshold value variation of the amplifying transistor54are removed. Therefore, a count result (a count value) of the counter92L-1is changed to a digital value in which the analog pixel signal is digitized.

Since the AD converters81L-2to81L-n also have the same configuration as the AD converter81L-1, repeated descriptions thereof will be omitted. In addition, hereinafter, the comparators91L-1to91L-n will be simply designated as a comparator91L when not being individually distinguished, and the counters92L-1to92L-n will be simply designated as a counter92L when not being individually distinguished.

FIG. 3is a block diagram illustrating an example of a specific configuration of the signal processing unit65L. The signal processing unit65L includes a data latch unit83L and a parallel to serial (hereinafter referred to as “parallel-serial”) converting unit84L in addition to the AD converter81L and the reference voltage generating unit82L. Therefore, the signal processing unit65L has a pipeline configuration in which pixel data digitized in the AD converter81L is pipeline-transferred to the memory unit67L. In this case, the signal processing unit65L performs a digitization process by the AD converter81L within one horizontal period and performs a process in which the digitized pixel data is transferred to the data latch unit83L within one horizontal period.

On the other hand, the column decoder/sense amplifier66L is provided at the memory unit67L as a peripheral circuit thereof. While the above-described row decoder64L (refer toFIG. 2) designates a row address for the memory unit67L, the column decoder designates a column address for the memory unit67L. In addition, the sense amplifier amplifies a weak voltage read from the memory unit67L through a bit line to a level that can be handled as a digital level. Therefore, pixel data read through the column decoder/sense amplifier66L is output to the outside of the logic substrate12through the data processing unit68L and the interface unit69L.

Here, while a case in which one column-parallel AD converter81L is provided has been exemplified, the present disclosure is not limited thereto. A configuration in which two or more AD converters81L are provided and a digitization process is performed in the two or more AD converters81L in parallel can be used.

In this case, the two or more AD converters81L are disposed, for example, in a direction in which the signal line34of the pixel array unit31extends, that is, disposed to be divided at upper and lower sides of the pixel array unit31. When the two or more AD converters81L are provided, two data latch units83L, two parallel-serial converting units84L, and two memory units67L (two systems) are provided in correspondence thereto.

In this manner, in the solid-state imaging element1having a configuration in which, for example, the AD converters81L of two systems are provided, row scanning is performed in parallel for every two pixel rows. Therefore, a signal of each pixel of one pixel row is read at one side in a vertical direction of the pixel array unit31, a signal of each pixel of the other pixel row is read at the other side in the vertical direction of the pixel array unit31, and a digitization process is performed in the two AD converters81L in parallel. Similarly, the subsequent signal processes are performed in parallel. As a result, compared to when row scanning is performed for one pixel row, it is possible to read pixel data at a high speed.

Although detailed drawings and descriptions are omitted, the signal processing circuit41R also has a configuration similar to that of the signal processing circuit41L. Therefore, the signal processing circuit41R mainly performs a process of a pixel signal from the unit pixel32within the right half region of the pixel array unit31.

Hereinafter, in signs of components of the signal processing circuit41R which are not illustrated, the letter R replaces the letter L in signs assigned to components of the signal processing circuit41L.

{1-3. Layout of Logic Substrate12}

FIG. 4shows an example of a layout of the logic substrate12. As illustrated inFIG. 4, the signal processing circuit41L and the signal processing circuit41R of the logic substrate12have the same layouts that are bilaterally symmetrical.

In the signal processing circuit41L, an AD converting unit101L-1, a memory unit102L-1, a logic unit103L, a memory unit102L-2, and an AD converting unit101L-2are laminated from the top to the bottom. In addition, an interface unit104L-1and an interface unit104L-2are disposed at the left and right of the lamination portion. Further, vias105L-1to105L-4are disposed at vertical and horizontal ends of the signal processing circuit41L.

In the AD converting units101L-1and101L-2, for example, the current source61L, the AD converters81L-1to81L-n, the reference voltage generating unit82L, the data latch unit83L and the parallel-serial converting unit84L illustrated inFIG. 2andFIG. 3are separately disposed.

In this example, in the AD converting units101L-1and101L-2, the AD converter81L and a circuit portion associated therewith are laminated and disposed in three stages. That is, in the signal processing circuit41L, the AD converter81L and a circuit portion associated therewith are separately disposed into six systems. Therefore, the signal processing circuit41L performs row scanning, for example, for every six pixel rows, in parallel.

In addition, a pixel signal from each of the unit pixels32of the pixel array unit31is supplied to each of the AD converters81L that are disposed in the AD converting units101L-1and101L-2through the vias105L-1to105L-4.

In the memory units102L-1and102L-2, for example, the column decoder/sense amplifier66L and the memory unit67L illustrated inFIG. 3are separately disposed. Therefore, the memory unit102L-1stores pixel data supplied from the AD converting unit101L-1, and the memory unit102L-2stores pixel data supplied from the AD converting unit101L-2.

In the logic unit103L, for example, the decoder62L, the control unit63L, the row decoder64L, and the data processing unit68L illustrated inFIG. 2are disposed.

In the interface units104L-1and104L-2, for example, the interface unit69L illustrated inFIG. 2is disposed.

Since the signal processing circuit41R has the same layout as the signal processing circuit41L, repeated descriptions thereof will be omitted.

In addition, the above-described configuration and layout of the signal processing circuits41L and41R are only examples, and a configuration and a layout other than the above-described configuration and layout can be used.

{1-4. Image Process of Solid-State Imaging Element1}

Next, an image process of the solid-state imaging element1will be briefly described with reference toFIG. 5andFIG. 6.

FIG. 5shows an example of a method of connecting the signal processing circuits41L and41R of the solid-state imaging element1and an external signal processing LSI121. Specifically, the signal processing LSI121is connected to the interface unit104L-1of the signal processing circuit41L and an interface unit104R-2of the signal processing circuit41R.

For example, when a subject141ofFIG. 6is imaged by the solid-state imaging element1, a pixel signal from the unit pixel32within the left half region of the pixel array unit31is supplied to the signal processing circuit41L, and a pixel signal from the unit pixel32within the right half region thereof is supplied to the signal processing circuit41R, that is, a pixel signal corresponding to the left half of the subject141is supplied to the signal processing circuit41L and a pixel signal corresponding to the right half of the subject141is supplied to the signal processing circuit41R.

The signal processing circuit41L generates image data142L corresponding to the left half of the subject141based on a pixel signal supplied from the pixel circuit21. Similarly, the signal processing circuit41R generates image data142R corresponding to the right half of the subject141based on a pixel signal supplied from the pixel circuit21.

Therefore, the signal processing circuit41L outputs the generated image data142L from the interface unit104L-1and supplies the data to the signal processing LSI121. The signal processing circuit41R outputs the generated image data142R from the interface unit104R-2and supplies the data to the signal processing LSI121.

The signal processing LSI121generates one piece of image data143by synthesizing the image data142L and the image data142R, and outputs the generated image data143.

In this manner, in the solid-state imaging element1, since left and right pieces of image data are independently generated, it is possible to perform a process at a high speed.

{1-5. Detailed Configuration of Signal Processing Circuits41L and41R}

Incidentally, a case in which the signal processing circuits41L and41R have the same circuit pattern has been described above. Although circuit patterns for the same actual function are the same, there are configurations in which it is sufficient for them to be provided not in both but in any of the signal processing circuits41L and41R when pixel signals from the unit pixel32within the region of the pixel array unit31, which will be subjected to signal processing on the left and right, are processed.

In particular, there is a configuration in which, within the logic substrate12described with reference toFIG. 4, it is sufficient for the logic units103L and103R to be provided at either side thereof.

For example, as illustrated on the left inFIG. 7, since the signal processing circuits41L and41R have the same circuit pattern, blocks A to C having different functions are provided in the signal processing circuits41L and41R.

Here, when it is sufficient for the blocks B and C to be provided in either of the signal processing circuits (chips)41L and41R, in general, for example, as indicated by a shaded portion on the left inFIG. 7, the block B is changed to the standby state in the signal processing circuit41L, and the block C is changed to the standby state in the signal processing circuit41R.

Here, the standby state is, for example, a state in which a wire for inputting and outputting a signal is not connected to the blocks B and C provided in a substrate layer, for example, according to a configuration of a wiring layer, and is a state in which the blocks B and C are not substantially used and configurations in the standby state are indicated by shaded portions inFIG. 7.

That is, in a case in which a plurality of signal processing circuits41having the same circuit pattern are used, when any one among the same blocks provided in each of the signal processing circuits41functions, if it is not necessary for the others to function, in general, as illustrated on the left inFIG. 7, only necessary blocks remain and the other blocks are changed to the standby state in which they are not used.

However, in such a configuration, blocks that are in the standby state and do not function are wasted and a mounting area is occupied by blocks that do not function.

Therefore, as illustrated on the right inFIG. 7, in uppermost layers of the signal processing circuits41L and41R and further, in regions corresponding to the signal processing circuits41L and41R, one-shot exposure wiring layers that are different wiring layers are provided. Accordingly, blocks A and C are provided in a wiring layer of the uppermost layer of the signal processing circuit41L and blocks A and B are provided in a wiring layer of the uppermost layer of the signal processing circuit41R.

More specifically, as illustrated in a side cross-sectional view ofFIG. 8, in the signal processing circuits41L and41R, in a substrate layer151of a lowermost layer, the same element is formed in the same pattern, and a wiring layer152is provided in a layer thereabove. The wiring layer152includes wiring layers161and162from the bottom in the drawing.

The wiring layer161is formed in a region corresponding to the signal processing circuits41L and41R and is formed in the same wiring pattern that is formed by divided exposure. The general signal processing circuits41L and41R include only the substrate layer151and the wiring layer161. However, in the present disclosure, furthermore, the wiring layer162having wiring patterns in which regions corresponding to the signal processing circuits41L and41R are different (left and right are different) according to one-shot exposure is provided as the uppermost layer.

That is, according to the wiring layer161having the same wiring pattern on which divided exposure is performed, a basic cell such as an AND circuit or an OR circuit is formed.

Since the wiring layer162has a wiring structure whose left and right are different according to one-shot exposure, when connection between basic cells such as an AND circuit or an OR circuit of the wiring layer161is changed, blocks having different functions are formed in the signal processing circuits41L and41R.

As a result, as described above, a wiring pattern can be independently formed in each of the signal processing circuits41L and41R. In the signal processing circuits41L and41R, it is possible to reduce the number of blocks that are in the standby state, that is, do not function. Therefore, it is possible to reduce wasted blocks and increase the number of blocks having a mounting function.

In particular, within the logic substrate12described with reference toFIG. 4, the wiring layers162of the logic units103L and103R have different wiring patterns. For example, a block that is adequate when provided on either side can be provided on either side.

Modified Example of First Embodiment

An example in which, on the substrate layer151, the wiring layer161is formed in regions corresponding to the signal processing circuits41L and41R according to divided exposure, and in a layer thereabove, the wiring layer162having different wiring patterns is formed in regions corresponding to the signal processing circuits41L and41R according to one-shot exposure has been described above. Alternatively, in all wiring layers above the substrate layer151, different wiring patterns are formed in regions corresponding to the signal processing circuits41L and41R according to one-shot exposure.

As illustrated inFIG. 9, a wiring layer171formed according to one-shot exposure is formed in a layer above the substrate layer131. That is, inFIG. 9, all wiring layers corresponding to the wiring layer152including the wiring layer161formed according to divided exposure and the wiring layer162formed according to one-shot exposure inFIG. 8are configured by the wiring layer171in which different wiring patterns are formed in regions corresponding to the signal processing circuits41L and41R according to one-shot exposure.

In such a configuration, it is possible to mount a block having a function of a higher degree of freedom.

2. Second Embodiment

A case in which, in the wiring layer of the uppermost layer, in regions of the signal processing circuits41L and41R, different wiring patterns are formed according to one-shot exposure and thus different functions are implemented in the signal processing circuits41L and41R has been described above. However, the signal processing circuits41L and41R have, for example, two functions that are different from each other. According to Hi or Low in a 1-bit switching signal supplied through a signal line in each of the signal processing circuits41, the two different functions may be switched.

For example, as illustrated inFIG. 10, in the signal processing circuits (Chips in the drawing)41L and41R having both functions of a left image process and a right image process, terminals181L and181R configured to receive a switching signal are provided. A switching signal in a fixed state from a signal line through terminals152L and152R formed by the wiring layer152inFIG. 8formed according to a processing procedure is supplied to the terminals181L and181R.

When the switching signal is Low, the signal processing circuit41enables the function of the left image process and disables the function of the right image process. Similarly, when the switching signal is Hi, the signal processing circuit41enables the function of the right image process and disables the function of the left image process.

Therefore, when a configuration in which a switching signal of Low is supplied to the terminal181L through the terminal152L and a switching signal of Hi is supplied to the terminal181R through the terminal152R is provided, the signal processing circuit41L in the drawing can function as a signal processing circuit configured to perform the left image process and the signal processing circuit41R can function as a signal processing circuit configured to perform the right image process.

Accordingly, when disposed in the logic substrate12, if the signal processing circuit41is disposed without distinguishing the left and right, it is possible to implement a function according to a disposed position.

As a result, the preparation of the signal processing circuit41having different functions is unnecessary, time and effort for distinguishing disposition for each signal processing circuit41having different functions can be reduced, and thus it is possible to reduce a manufacturing cost.

It should be noted that there are two types, the signal processing circuits41L and41R, in the above, and thus the switching signal is a 1-bit signal. Alternatively, when one or more, for example, 2n, signal processing circuits41have 2ntypes of different functions, an n-bit switching signal is switched and supplied according to the disposed position, and it is possible to switch a function according to each position.

First Modified Example of Second Embodiment

An example in which the switching signal supplied by the wiring layer152is supplied to the terminals181L and181R has been described. Alternatively, as illustrated inFIG. 11, signal lines through which the switching signal is supplied to the logic substrate12may be connected at bondings12L and12R.

In such a configuration, the signal processing circuits41L and41R can appropriately switch the function of the left image process and the function of the right image process according to Hi or Low of the fixed switching signal supplied through the bondings12L and12R.

Second Modified Example of Second Embodiment

In addition, as illustrated inFIG. 12, registers201L and201R may be provided in the signal processing circuits41L and41R, respectively. The registers201L and201R write and store a predetermined value by a control device of a device that is not illustrated and output a switching signal of Hi or Low according to the stored value.

In such a configuration, the signal processing circuits41L and41R can switch a function based on Hi or Low of the switching signal stored in the registers (reg in the drawing)201L and201R through the terminals181L and181R.

Here, the registers201L and201R may store a fixed switching signal by a control device of a device that is not illustrated, for example, whenever the device starts.

Third Modified Example of Second Embodiment

Further, as illustrated inFIG. 13, in the signal processing circuits41L and41R, eFuses (fuse in the drawing)221L and221R capable of switching an output value only once according to stress of electromagnetic waves including electricity or light such as ultraviolet light may be provided. The eFuses (fuse in the drawing)221L and221R store a predetermined value with each process according to stress of electromagnetic waves including electricity or light such as ultraviolet light and output a switching signal of Hi or Low according to the stored value.

In such a configuration, the signal processing circuits41L and41R can switch a function based on Hi or Low of the switching signal output by the eFuses221L and221R through the terminals181L and181R.

Fourth Modified Example of Second Embodiment

In addition, as illustrated inFIG. 14, in the signal processing circuits41L and41R, for example, Electrically Erasable Programmable Read-only Memories (EEPROMs) (e2p in the drawing)241L and241R serving as non-volatile memories capable of controlling an output value from the outside by a control device (not illustrated) may be provided. The EEPROMs241L and241R write and store a predetermined output value from the outside by a control device of a device that is not illustrated and output a switching signal of Hi or Low according to the stored output value.

In such a configuration, the signal processing circuits41L and41R can switch a function based on Hi or Low of the switching signal output by the EEPROMs241L and241R through the terminals181L and181R.

Fifth Modified Example of Second Embodiment

Further, as illustrated inFIG. 15, external terminals251L and251R may be provided in the signal processing circuits41L and41R, respectively.

In such a configuration, the signal processing circuits41L and41R can switch a function based on Hi or Low of the switching signal supplied to the terminals181L and181R through the external terminals251L and251R.

A configuration in which different functions are implemented in the signal processing circuits41L and41R has been described above. Alternatively, in order to implement an operation in which the signal processing circuits41L and41R are synchronized, the same reference clock signal may be supplied to the signal processing circuits41L and41R.

That is, as illustrated inFIG. 16, when signal processing units271L and271R having the same function are provided in the signal processing circuits41L and41R, respectively, a reference clock signal (Input Clock in the drawing) is supplied to the signal processing circuits41L and41R. It should be noted that the term “the signal processing units271L and271R” generally refers to blocks that execute various functions performed by the above-described signal processing circuits41L and41R.

Accordingly, in the signal processing circuits41L and41R, the signal processing units271L and271R can execute signal processing based on the supplied reference clock signal.

As a result, since the signal processing units271L and271R execute an operation using the reference clock signal, it is possible to synchronize processes, for example, achieve left and right synchronization of a captured image, suppress image quality reduction caused by non-synchronization of signal processing performed by left and right image groups, and achieve high image quality.

First Modified Example of Third Embodiment

While an example in which the signal processing units271L and271R use the supplied reference clock signal without change has been described above, a clock signal multiplied by a reference clock signal at a predetermined ratio using a multiplication function including a phase locked loop (PLL) may be used.

FIG. 17shows a configuration example in which the signal processing units271L and271R having the same function are provided in the signal processing circuits41L and41R, respectively, the reference clock signal is supplied to the signal processing circuits41L and41R and multiplier units (PLL in the drawing)281L and281R are provided at a previous stage of the signal processing units271L and271R.

As a result, since the signal processing units271L and271R execute an operation using a clock signal multiplied by the reference clock signal by the multiplier units281L and281R, it is possible to synchronize processes, and for example, achieve left and right synchronization of a captured image, and achieve high image quality.

Second Modified Example of Third Embodiment

While an example in which the reference clock signal is supplied to the signal processing circuits41L and41R has been described above, the reference clock signal may be supplied to any of the signal processing circuits41L and41R, and the signal processing circuit41to which the reference clock signal is supplied may supply the reference clock signal to the signal processing circuit41to which no reference clock signal is supplied.

That is, as illustrated inFIG. 18, the reference clock signal is supplied to the signal processing circuit41L, and the signal processing circuit41L to which the reference clock signal is supplied may supply the reference clock signal to the signal processing circuit41R to which no reference clock signal is supplied.

In such a configuration, for the same reason as described above, it is possible to achieve high image quality and reduce the number of external terminals.

It should be noted that, while an example in which the signal processing circuit41L receives the supplied reference clock signal and supplies the result to the signal processing circuit41R has been described inFIG. 18, the signal processing circuit41R may receive the supplied reference clock signal and supply the signal to the signal processing circuit41L. In addition, when two or more signal processing circuits41are provided, any of the signal processing circuits41may receive the supplied reference clock signal and supply the reference clock signal to the other signal processing circuit41to which no reference clock signal is supplied.

Third Modified Example of Third Embodiment

An example in which the reference clock signal is supplied to any of the signal processing circuits41L and41R, the signal processing circuit41to which the reference clock signal is supplied supplies the reference clock signal to the signal processing circuit41to which no reference clock signal is supplied has been described above.

However, further, the reference clock signal is supplied to any of the signal processing circuits41L and41R, and additionally, the signal processing circuit41to which the reference clock signal is supplied performs multiplication of the reference clock signal. Then, a clock signal multiplied by the reference clock signal may be supplied to the signal processing circuit41to which no reference clock signal is supplied.

That is, as illustrated inFIG. 19, the reference clock signal is supplied to the signal processing circuit41L. In the signal processing circuit41L to which the reference clock signal is supplied, the multiplier unit281L performs multiplication of the reference clock signal. Then, a clock signal multiplied by the reference clock signal is supplied to the signal processing circuit41R to which no reference clock signal is supplied.

In such a configuration, for the same reason as described above, it is possible to achieve high image quality and reduce the number of external terminals.

It should be noted that, while an example in which the signal processing circuit41L receives the supplied reference clock signal, performs multiplication and then supplies the result to the signal processing circuit41R has been described inFIG. 19, the signal processing circuit41R may receive the supplied reference clock signal, perform multiplication and then supply the result to the signal processing circuit41L. In addition, when two or more signal processing circuits41are provided, any of the signal processing circuits41may receive the supplied reference clock signal, perform multiplication, and supply a clock signal multiplied by the reference clock signal to the other signal processing circuit41. In addition, a multiplier unit281R′ indicated by a shaded portion inFIG. 19indicates that the multiplier unit281R inFIG. 17is in the standby state.

Fourth Modified Example of Third Embodiment

While an example in which any of a reference clock signal and a clock signal multiplied by a reference clock signal is supplied to any of the signal processing circuits41L and41R has been described above, these may be supplied in a mixed state.

That is, as illustrated inFIG. 20, an analog signal processing unit291L, a digital signal processing unit292L, and multiplier units281L-1and281L-2are provided in the signal processing circuit41L. In addition, in the signal processing circuit41R, an analog signal processing unit291R, a digital signal processing unit292R, and the multiplier unit281R are provided.

Therefore, the signal processing circuit41L receives the supplied reference clock signal, the multiplier unit281L-1performs multiplication of the reference clock signal and supplies the result to the digital signal processing units292L and292R, and the multiplier unit281L-2performs multiplication of the reference clock signal and supplies the result to the analog signal processing unit291L.

On the other hand, the signal processing circuit41R receives the supplied reference clock signal, and the multiplier unit281R performs multiplication of the reference clock signal and supplies the result to the analog signal processing unit291R.

In such a configuration, in the signal processing circuit41R, the reference clock signal is supplied from the outside and a clock signal multiplied by the reference clock signal by a signal processing circuit441L is supplied.

In any case, since it is possible to implement an operation in which the analog signal processing units291L and291R and the digital signal processing units292L and292R are synchronized, it is possible to achieve high image quality.

It should be noted that a configuration in which the configuration of the signal processing circuits41L and41R inFIG. 20is replaced may be used. In addition, a multiplier unit281R′-2indicated by a shaded portion inFIG. 20indicates that the multiplier unit281R-2corresponding to the multiplier unit281L-2is in the standby state.

While an example in which the supplied reference clock signal is received and operations of the signal processing units of the signal processing circuits41L and41R are synchronized has been described above, references of ADC groups provided in the signal processing circuits41L and41R are aligned, and therefore, a difference of characteristics according to the ADC may be corrected.

FIG. 21shows a configuration example of the signal processing circuits41L and41R in which reference voltages (references) of ADC groups (groups of a plurality of AD converters81) provided in the signal processing circuits41L and41R are aligned, and thus a difference of characteristics according to the AD converter81is corrected.

The upper part inFIG. 21shows the pixel array unit31on the pixel substrate11that is used as a processing range for each of the signal processing circuits41L and41R and that includes the left half of n columns and the right half of m columns, and pixel groups formed by dividing the region into upper and lower half processing regions. In this case, the upper left is a first pixel group31L-1, the upper right is a second pixel group31R-1, the lower left is a third pixel group31L-2, and the lower right is a fourth pixel group31R-2.

In addition, in the logic substrate12, in the signal processing circuit41L, the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101L-2described with reference toFIG. 4, and a clamp computing unit301L, a digital analog converting unit (DAC)302L, and a characteristic difference storage unit303are provided.

Further, in the signal processing circuit41R, an AD converting unit (ADC group)101R-1, an AD converting unit (ADC group)101R-2, a clamp computing unit301R and a DAC302R are provided.

The AD converting unit (ADC group)101L-1, the AD converting unit (ADC group)101R-1, the AD converting unit (ADC group)101L-2, and the AD converting unit (ADC group)101R-2perform analog digital conversion of pixel signals of the first pixel group31L-1, the second pixel group31R-1, the third pixel group31L-2, and the fourth pixel group31R-2and output the converted signals.

Therefore, the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1supply the pixel signals of the pixel group of the upper left and right half in the pixel array unit31that are converted into digital signals to the clamp computing unit301L. In addition, the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2supply the pixel signals of the pixel group of the lower left and right half in the pixel array unit31that are converted into digital signals to the clamp computing unit301R. In this case, the AD converting unit (ADC group)101L-1, the AD converting unit (ADC group)101R-1, the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2output the pixel signals to subsequent stages (described as “output” in the drawing). Here, the output pixel signal is subjected to parallel-to-serial conversion and is output as a pixel signal that is output by the signal processing unit65ofFIG. 3described above.

The clamp computing unit301L computes reference levels based on pixel signals of pixels of a light-blocking region (not illustrated) provided in a peripheral region of the first pixel group31L-1and the second pixel group31R-1of the pixel array unit31, which are converted into digital signals by the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1. Therefore, the clamp computing unit301L outputs any of an average value, a minimum value and a maximum value of the reference levels to the DAC302L as a correction level. The clamp computing unit301L repeats a similar process in real time and repeatedly outputs the correction level.

Similarly, the clamp computing unit301R computes reference levels based on pixel signals of pixels of a light-blocking region (not illustrated) provided in a peripheral region of the third pixel group31L-2and the fourth pixel group31R-2of the pixel array unit31, which are converted into digital signals by the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2. Therefore, the clamp computing unit301R outputs any of an average value, a minimum value and a maximum value of the reference levels to the DAC302R as a correction level. The clamp computing unit301R repeats a similar process in real time and repeatedly outputs the correction level.

The DAC302L supplies a signal of the correction level supplied by the clamp computing unit301L to the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1as a reference voltage (reference) that is converted from a digital signal into an analog signal. In this case, the DAC302L outputs the reference voltage (reference) while a gain is controlled so that mutual characteristic differences are corrected by the characteristic difference storage unit303.

The DAC302R supplies a signal of the correction level supplied by the clamp computing unit301R to the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2as a reference voltage (reference) that is converted from a digital signal into an analog signal. In this case, the DAC302R outputs the reference voltage (reference) while a gain is controlled so that mutual characteristic differences are corrected by the characteristic difference storage unit303.

That is, the DACs302L and302R function as the above-described reference voltage generating unit82L inFIG. 2.

When power supply of the solid-state imaging element1is turned off, the characteristic difference storage unit303images all pixels of the pixel array unit31as light-blocking pixels, and stores a difference thereof as a characteristic difference based on pixel signals that are converted into digital signals by the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1, and the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2.

More specifically, the characteristic difference storage unit303calculates and stores an output difference between the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1and an output difference between the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2as a characteristic difference between the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1and a characteristic difference between the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2. Therefore, the characteristic difference storage unit303controls gains of the DACs302L and302R to cancel the stored characteristic difference.

The clamp computing unit301L obtains a correction level for controlling reference voltages (references) of the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1according to computation and outputs the obtained level.

Similarly, the clamp computing unit301R obtains a correction level for controlling reference voltages (references) of the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2according to computation and outputs the obtained level.

Therefore, almost the same reference voltage (reference) is supplied to the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1. Accordingly, the balance of development of color of the first pixel group31L-1and the second pixel group31R-1is regulated and substantially white balance is adjusted. Therefore, characteristics of the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1are regulated.

Similarly, almost the same reference voltage (reference) is supplied to the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2. Accordingly, the balance of development of color of the third pixel group31L-2and the fourth pixel group31R-2is regulated and substantially white balance is adjusted. Therefore, characteristics of the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2are regulated.

However, the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1and the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2are provided in the signal processing circuits41L and41R, respectively, as illustrated inFIG. 21. Due to differences thereof, parasitic capacitances are not the same and different characteristics are generally provided.

Therefore, in the first pixel group31L-1and the second pixel group31R-1and the third pixel group31L-2and the fourth pixel group31R-2, development of color is regulated between pixels in regions thereof. However, characteristics between a first ADC group including the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1and a second ADC group including the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2are different. As a result, there is a difference albeit in development of color between the first pixel group31L-1and the second pixel group31R-1and between the third pixel group31L-2and the fourth pixel group31R-2, and thus there is a risk of image quality being reduced.

Therefore, the characteristic difference storage unit303images a black image by setting all pixels in a light-blocking state immediately before power supply is turned off, sets gains of the DACs302L and302R at this time to a maximum value, measures and stores an output difference between the first pixel group31L-1and the second pixel group31R-1and the third pixel group31L-2and the fourth pixel group31R-2as a characteristic difference. The characteristic difference is a difference that is generated by a difference of characteristics between ADC groups, the first ADC group including the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1and the second ADC group including the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2. When the characteristic difference is stored according to a characteristic difference correcting process which will be described with reference toFIG. 23, the characteristic difference storage unit303adjusts a gain between the DACs302L and302R to correct the stored characteristic difference and outputs a reference voltage (reference) in an ADC characteristic difference storing process which will be described with reference toFIG. 22.

Accordingly, when the characteristic difference between ADC groups is corrected, it is possible to suppress a difference in development of color that occurs between the first pixel group31L-1and the second pixel group31R-1and the third pixel group31L-2and the fourth pixel group31R-2within the pixel array unit31, and it is possible to implement a high-speed process according to the plurality of ADC groups.

It should be noted that the term “characteristic difference” includes an offset component and a gain component. The offset component indicates a deviation of reference levels in digital signals output by the AD converting unit (ADC group)101L-1, the AD converting unit (ADC group)101R-1, the AD converting unit (ADC group)101L-2, and the AD converting unit (ADC group)101R-2, which are adjusted by the clamp computing units301L and301R.

In addition, the gain component indicates a deviation of linearity with respect to correction levels supplied by the clamp computing units301L and301R of the first ADC group including the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1and the second ADC group including the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2, which are adjusted by the clamp computing units301L and301R.

<ADC Group Characteristic Difference Correcting Process>

Next, a process of correcting a difference between ADC groups performed by the signal processing circuits41L and41R ofFIG. 21will be described with reference to a flowchart ofFIG. 22. It should be noted that, in the process, it is assumed that pixel signals obtained from analog signals that are sequentially generated by photodiodes of pixels within the pixel array unit31according to photoelectric conversion are sequentially supplied.

In Step S11, the AD converting unit (ADC group)101L-1converts an analog signal supplied by the first pixel group31L-1into a digital signal, supplies the result to the clamp computing unit301L and the characteristic difference storage unit303, and outputs the result as a pixel signal.

In Step S12, the AD converting unit (ADC group)101R-1converts an analog signal supplied by the second pixel group31R-1into a digital signal, supplies the result to the clamp computing unit301L and the characteristic difference storage unit303, and outputs the result as a pixel signal.

In Step S13, the clamp computing unit301L determines whether a current pixel is a light-blocking pixel provided in a peripheral region of the pixel array unit31, and when it is determined as a light-blocking pixel, the process advances to Step S14.

In Step S14, the clamp computing unit301L computes and stores an offset based on a reference level according to pixel signals obtained from digital signals output by the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1serving as the first ADC group whose targets are the first pixel group31L-1and the second pixel group31R-1. That is, pixel values supplied from light-blocking pixels should be supplied as signals of reference levels. However, according to characteristics of the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1, there may be a pixel value that is deviated from the reference level. Therefore, the clamp computing unit301L calculates an amount of the deviation as an offset and stores the offset for a plurality of pixels.

In Step S15, the clamp computing unit301L multiplies an average value, a minimum value or a maximum value of the stored offsets of the plurality of pixels by pixel signals of the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1to set a correction level and outputs the result to the DAC302L. That is, the clamp computing unit301L sets a correction level in order for pixel values of light-blocking pixels to be reference levels and for a reference voltage (reference) from the DAC302L to be deviated only by the stored offset, and outputs the result to the DAC302L. It should be noted that, in Step S13, when it is determined that a current pixel is not a light-blocking pixel, the process of Step S14is skipped.

In Step S16, the DAC302L converts a digital signal of the correction level supplied by the clamp computing unit301L into an analog signal, and outputs the converted signal to the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1serving as the first ADC group whose targets are the first pixel group31L-1and the second pixel group31R-1as a reference voltage (a reference).

In Step S17, the AD converting unit (ADC group)101L-2converts an analog signal supplied by the third pixel group31L-2and the fourth pixel group31R-2into a digital signal, supplies the converted signal to the clamp computing unit301R and the characteristic difference storage unit303, and outputs the result as a pixel signal.

In Step S18, the AD converting unit (ADC group)101R-2converts an analog signal supplied by the third pixel group31L-2and the fourth pixel group31R-2into a digital signal, supplies the converted signal to the clamp computing unit301R and the characteristic difference storage unit303, and outputs the result as a pixel signal.

In Step S19, the clamp computing unit301R determines whether a current pixel is a light-blocking pixel that is provided in a peripheral region of the pixel array unit31, and when it is determined as a light-blocking pixel, the process advances to Step S20.

In Step S20, the clamp computing unit301R computes an offset based on a reference level according to pixel signals obtained from digital signals output by the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2serving as the ADC group whose targets are the third pixel group31L-2and the fourth pixel group31R-2and stores the offset for a plurality of pixels.

In Step S21, the clamp computing unit301R multiplies an average value, a minimum value or a maximum value of the store offsets of the plurality of pixels by pixel signals of the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2to set a correction level and outputs the result to the DAC302R. It should be noted that, in Step S19, when it is determined that a current pixel is not a light-blocking pixel, the process of Step S20is skipped.

In Step S22, the DAC302R converts a digital signal of the correction level supplied by the clamp computing unit301R into an analog signal and outputs the converted signal to the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2serving as the second ADC group whose targets are the third pixel group31L-2and the fourth pixel group31R-2as a reference voltage (reference). In this case, the DAC302R outputs the reference voltage (the reference) multiplied by a gain according to the characteristic difference (gain component) stored in the characteristic difference storage unit303.

According to the above-described process, when a pixel signal outside the light-blocking region is supplied, based on the characteristic difference of the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2using the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1as references, which is stored in the characteristic difference storage unit303, a gain of the DAC302R is adjusted and the reference voltage is output. Therefore, the reference voltage (reference) is supplied to the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2such that a gain component of characteristic differences of the first ADC group including the AD converting unit (ADC group)101L-1and the AD converting unit (ADC group)101R-1and the second ADC group including the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2is absorbed.

In this case, since the correction level set based on the offset is supplied to the DACs302L and302R, the offset component in the characteristic difference is also corrected. That is, the offset component in the characteristic component is independently corrected in the first pixel group31L-1and the second pixel group31R-1, and the third pixel group31L-2and the fourth pixel group31R-2by the clamp computing units301L and301R. In addition, the gain component in the characteristic component is relatively corrected based on the characteristic difference obtained as the output difference between the first pixel group31L-1and the second pixel group31R-1, and the third pixel group31L-2and the fourth pixel group31R-2by the characteristic difference storage unit303.

As a result, when an operation is performed for the characteristic difference between different ADC groups to be absorbed, it is possible to implement development of appropriate colors of the pixel array unit31as a whole, and it is possible to achieve high image quality. In addition, since it is possible to dynamically correct the characteristic difference (in particular, the offset component), it is possible to maintain development of appropriate colors for a long time, and ensure image quality for a long time. In addition, since the characteristic difference between ADC groups is caused by a change in the parasitic capacitance due to the layout, the layout of the ADC group has a symmetrical basis so far and is adjusted by other know-how and trial and error. However, since the layout may not be influenced by the parasitic capacitance, it is possible to increase degrees of freedom of the ADC layout. It should be noted that a process of storing the characteristic difference will be described below with reference toFIG. 23.

In addition, when a pixel signal of the light-blocking region is supplied, the offset component serving as the characteristic difference of the AD converting unit (ADC group)101L-1, the AD converting unit (ADC group)101R-1, the AD converting unit (ADC group)101L-2and the AD converting unit (ADC group)101R-2is computed and adjusted and the reference voltage (reference) is dynamically corrected.

Next, a characteristic difference storing process will be described with reference to a flowchart ofFIG. 23.

In Step S41, a control unit (not illustrated) configured to control an operation of the pixel array unit31determines whether an operation in which power supply of the solid-state imaging element1is turned off is performed and repeats a similar process until it is determined to be turned off. Then, in Step S41, when it is determined that power supply is turned off, the process advances to Step S42.

In Step S42, the pixel array unit31images a black image while the entire region is blocked from light. That is, all pixels are light-blocking pixels and can be processed as light-blocking pixels while any of the pixels is read.

In Step S43, the characteristic difference storage unit303maximizes gains of the DACs302L and302R and supplies reference voltages (references) to the AD converting unit (ADC group)101L-1, the AD converting unit (ADC group)101R-1, the AD converting unit (ADC group)101L-2, and the AD converting unit (ADC group)101R-2.

In Step S44, the AD converting unit (ADC group)101L-1converts a pixel value of the first pixel group31L-1into a digital signal, and outputs the result to the clamp computing unit301L and the characteristic difference storage unit303as a pixel signal.

In Step S45, the AD converting unit (ADC group)101R-1converts a pixel value of the second pixel group31R-1into a digital signal and outputs the result to the clamp computing unit301L and the characteristic difference storage unit303as a pixel signal.

In Step S46, the AD converting unit (ADC group)101L-2converts a pixel value of the third pixel group31L-2into a digital signal and outputs the result to the clamp computing unit301R and the characteristic difference storage unit303as a pixel signal.

In Step S47, the AD converting unit (ADC group)101R-2converts a pixel value of the fourth pixel group31R-2into a digital signal, and outputs the result to the clamp computing unit301R and the characteristic difference storage unit303as a pixel signal.

In Step S48, the characteristic difference storage unit303stores a difference value of a digital signal of any pixel of the first pixel group31L-1to the fourth pixel group31R-2as a characteristic difference.

According to the above-described process, whenever power supply is turned off, a black image is captured while a maximum gain is obtained, a characteristic difference (a gain component) at this time is obtained, and gains of the DACs302L and302R are relatively adjusted to cancel the characteristic difference (the gain component) in the characteristic difference correcting process. As a result, since it is possible to implement development of appropriate colors, it is possible to ensure image quality for a long time.

In addition, an example in which, in measuring of the characteristic difference, when a black image is imaged, a difference of the pixel signal when a gain is maximized is obtained as the characteristic difference, and in the ADC characteristic difference correcting process, the characteristic difference when a gain is maximized is absorbed has been described above. However, the characteristic difference according to a size of the gain may be obtained and used. For example, immediately before power supply is turned off, a black image in which a gain is maximized and a black image in which a gain is minimized are imaged, the characteristic difference according to the gain is stored from linearity of each of the obtained characteristic differences. In the characteristic difference correcting process, a gain according to the characteristic difference is set and thus the characteristic difference may be cancelled.

Further, an example in which a divided exposure boundary in the pixel array unit31includes the left half of n columns and the right half of m columns as illustrated in the upper part inFIG. 21has been described above. However, a boundary of the signal processing circuits41L and41R in the logic substrate12may match a boundary of the signal processing circuits41L and41R. In this case, n may be equal to m.

In addition, the above-described process is performed to suppress generation of vertical stripe-shaped noise that is generated by a difference of a stray capacitance in the vicinity of the boundary of the signal processing circuits41L and41R. Therefore, for example, the ADC group characteristic difference correcting process and the characteristic difference storing process may be executed using only an ADC group corresponding to pixels in the vicinity of the divided exposure boundary as a processing target.

5. Examples of Application to Electronic Device

The above-described solid-state imaging element1can be applied to various electronic devices, for example, an imaging device such as a digital still camera and a digital video camera, a mobile phone having an imaging function, or other devices having an imaging function.

FIG. 24is a block diagram illustrating a configuration example of an imaging device as an electronic device to which the present technology is applied.

An imaging device501illustrated inFIG. 24includes an optical system502, a shutter device503, a solid-state imaging element504, a drive circuit505, a signal processing circuit506, a monitor507and a memory508, and can image a still image and a moving image.

The optical system502includes one or a plurality of lenses, guides light (incident light) from a subject to the solid-state imaging element504, and forms an image on a light receiving surface of the solid-state imaging element504.

The shutter device503is disposed between the optical system502and the solid-state imaging element504, and controls a light illumination period and a light-blocking period of the solid-state imaging element504under control of the drive circuit505.

The solid-state imaging element504includes a package having the above-described solid-state imaging element. The solid-state imaging element504accumulates signal charges for a constant period according to light whose image is formed on a light receiving surface through the optical system502and the shutter device503. The signal charges accumulated in the solid-state imaging element504are transferred according to a drive signal (a timing signal) supplied from the drive circuit505.

The drive circuit505outputs a drive signal for controlling a transfer operation of the solid-state imaging element504and a shutter operation of the shutter device503and drives the solid-state imaging element504and the shutter device503.

The signal processing circuit506performs various types of signal processing of signal charges output from the solid-state imaging element504. An image (image data) obtained by signal processing performed by the signal processing circuit506is supplied to and displayed on the monitor507, and is supplied to and stored (recorded) in the memory508.

In the imaging device501configured in this manner as well, the solid-state imaging element1is applied instead of the above-described solid-state imaging element504. Therefore, it is possible to reduce cost.

6. Use Examples of Solid-State Imaging Element

FIG. 25is a diagram illustrating use examples in which the above-described solid-state imaging element1is used.

The above-described imaging element can be used for, for example, various cases in which light such as visible light, infrared light, ultraviolet light, or X-rays is detected as follows.

Devices that take images used for viewing, such as a digital camera and a portable appliance with a camera function.

Devices used for traffic, such as an in-vehicle sensor that takes images of the front and the back of a car, surroundings, the inside of the car, and the like, a monitoring camera that monitors travelling vehicles and roads, and a distance sensor that measures distances between vehicles and the like, which are used for safe driving (e.g., automatic stop), recognition of the condition of a driver, and the like.

Devices used for home electrical appliances, such as a TV, a refrigerator, and an air conditioner, to takes images of a gesture of a user and perform appliance operation in accordance with the gesture.

Devices used for medical care and health care, such as an endoscope and a device that performs angiography by reception of infrared light.

Devices used for security, such as a monitoring camera for crime prevention and a camera for personal authentication.

Devices used for beauty care, such as skin measurement equipment that takes images of the skin and a microscope that takes images of the scalp.

Devices used for sports, such as an action camera and a wearable camera for sports and the like.

Devices used for agriculture, such as a camera for monitoring the condition of the field and crops.

A solid-state imaging element in which a first substrate in which a pixel circuit including a pixel array unit is formed and a second substrate in which a plurality of signal processing circuits are formed are laminated, and a common reference clock is supplied to the plurality of signal processing circuits that are formed on the second substrate.

The solid-state imaging element according to (1), further including

a multiplier unit configured to multiply a reference clock supplied to the plurality of signal processing circuits,

wherein the plurality of signal processing circuits use a clock signal multiplied by the reference clock by the multiplier unit for signal processing.

The solid-state imaging element according to (1) or (2),

wherein a reference clock is supplied to one of the plurality of signal processing circuits and a signal processing circuit to which the reference clock is supplied supplies the reference clock to another signal processing circuits.

The solid-state imaging element according to (1),

wherein the multiplier unit configured to multiply the reference clock is included in one of the plurality of signal processing circuits, and

a reference clock is supplied to the one of the plurality of signal processing circuits, and a clock signal multiplied by the multiplier unit is supplied to the a signal processing circuit other than the one signal processing circuit among the plurality of signal processing circuits.

The solid-state imaging element according to (4),

wherein the reference clock and the clock signal multiplied by the reference clock are supplied to the plurality of signal processing circuits.(6)The solid-state imaging element according to (1), further includinga multiplier unit configured to multiply a reference clock supplied to the plurality of signal processing circuits,wherein the signal processing circuit includesan analog signal processing unit configured to perform analog signal processing on a clock signal multiplied by the reference clock by the multiplier unit, anda digital signal processing unit configured to perform digital signal processing on a clock signal multiplied by the multiplier unit in another signal processing circuit to which the reference clock is supplied.(7)An imaging device in which a first substrate in which a pixel circuit including a pixel array unit is formed and a second substrate in which a plurality of signal processing circuits are formed are laminated, and a common reference clock is supplied to the plurality of signal processing circuits that are formed on the second substrate.(8)An electronic device in which a first substrate in which a pixel circuit including a pixel array unit is formed and a second substrate in which a plurality of signal processing circuits are formed are laminated, and a common reference clock is supplied to the plurality of signal processing circuits that are formed on the second substrate.(9)A solid-state imaging element in which a first substrate in which a pixel circuit including a pixel array unit is formed by a plurality of exposures and a second substrate in which a plurality of signal processing circuits are formed by a plurality of exposures are laminated, the solid-state imaging element including:a plurality of clamp computing units configured to compute a reference level based on output signals of a group of analog digital converting circuits (ADCs) that are included in the plurality of signal processing circuits of the second substrate; anda reference voltage output unit configured to convert a digital signal of the reference level computed by the clamp computing unit into a reference voltage of an analog signal, and supply the converted value to the ADCs of the ADC group.(10)The solid-state imaging element according to (9),wherein the clamp computing unit computes a reference level based on outputs of an ADC group configured to convert signals of right pixels and an ADC group configured to convert left pixels at an exposure boundary of the first substrate.(11)The solid-state imaging element according to (9) or (10),wherein an exposure boundary of the first substrate matches boundaries of the plurality of signal processing circuits of the second substrate.(12)The solid-state imaging element according to (9),wherein the clamp computing unit computes a reference level based on outputs of an ADC group in the vicinity of an exposure boundary of the second substrate.(13)An imaging device in which a first substrate in which a pixel circuit including a pixel array unit is formed by a plurality of exposures and a second substrate in which a plurality of signal processing circuits are formed by a plurality of exposures are laminated, the imaging device including:a plurality of clamp computing units configured to compute a reference level based on output signals of a group of analog digital converting circuits (ADCs) that are included in the plurality of signal processing circuits of the second substrate; anda reference voltage output unit configured to convert a digital signal of the reference level computed by the clamp computing unit into a reference voltage of an analog signal, and supply the converted value to the ADCs of the ADC group.(14)An electronic device in which a first substrate in which a pixel circuit including a pixel array unit is formed by a plurality of exposures and a second substrate in which a plurality of signal processing circuits are formed by a plurality of exposures are laminated, the electronic device including:a plurality of clamp computing units configured to compute a reference level based on output signals of a group of analog digital converting circuits (ADCs) that are included in the plurality of signal processing circuits of the second substrate; anda reference voltage output unit configured to convert a digital signal of the reference level computed by the clamp computing unit into a reference voltage of an analog signal, and supply the converted value to the ADCs of the ADC group.

REFERENCE SIGNS LIST

1solid-state imaging element

31pixel array unit

41L,41R signal processing circuit

67L,67R memory unit

68L,68R data processing unit

69L,69R interface unit

81L-1to81R-n AD converter

101L-1to101R-2AD converting unit

103L,103R logic unit

251,251L,251R external terminal

271,271L,271R signal processing unit

291,291L,291R analog signal processing unit

292,292L,292R digital signal processing unit

301,301L,301R clamp computing unit

302,302L,302R DAC,303characteristic difference storage unit