DISPLAY PANEL AND DISPLAY DEVICE

The present disclosure provides a display panel and a display device. The display panel includes a display area and a peripheral area. The display area includes a plurality of sub-pixels on a substrate. The peripheral area including: a bending area; a plurality of multiplexers on a side of the bending area away from the display area and on the substrate, and each multiplexer is at least connected with a signal input line and two signal output lines; and a bonding area on a side of the plurality of multiplexers away from the bending area. The plurality of multiplexers are electrically connected to the plurality of sub-pixels through the bending area. The signal input line is electrically connected to the bonding area. An orthographic projection of the signal input line on the substrate does not overlap with an orthographic projection of the bending area on the substrate.

TECHNICAL FIELD

The present disclosure relates to a display panel and a display device.

BACKGROUND

During the process of narrowing a lower frame of an OLED (Organic Light Emitting Diode) display screen, a circuit layout design of a Pad area in a backplane of the display device is particularly important. A driving method of the OLED is complicated. In addition, in order to improve the resolution of the display, pixels within a display area of the display may be increased, so that more signal lines need be arranged and designed to control these pixels. This results in that IC (Integrated Circuit) requires more pins to output pixel driving signals. However, excessive pins may lead to complex bonding of the integrated circuit, and may make the implementation of COP (Chip on Plastic) process or COF (Chip On Film) process more difficult. Therefore, in the related art, a multiplexer (referred to as Mux for short) circuit is provided to reduce the number of pins in the integrated circuit.

In the related art, a plurality of multiplexers are provided in the display panel. Each multiplexer may use one data signal source in the IC to drive two columns of sub-pixels in the display panel. In this way, the number of pins in the IC can be reduced, the process difficulty of the module can be lessened and the size of the IC can be reduced. Since the multiplexer has the above-described advantages, the multiplexer is increasingly applied in the display panel (for example, AMOLED (Active-matrix Organic Light Emitting Diode) display panel).

SUMMARY

According to an aspect of embodiments of the present disclosure, a display panel is provided. The display panel comprises: a display area comprising a pixel array on a substrate, the pixel array comprising a plurality of sub-pixels; and a peripheral area surrounding the display area, the peripheral area comprising: a bending area on a side of the display area; a plurality of multiplexers on a side of the bending area away from the display area, wherein the plurality of multiplexers are on the substrate, the plurality of multiplexers are electrically connected to the plurality of sub-pixels through the bending area, and each of the plurality of multiplexers is at least connected with a signal input line and two signal output lines, an orthographic projection of the signal input line on the substrate does not overlap with an orthographic projection of the bending area on the substrate; and a bonding area on a side of the plurality of multiplexers away from the bending area, wherein the bonding area is electrically connected to the signal input line.

In some embodiments, the plurality of multiplexers comprise a first multiplexer and a second multiplexer, the second multiplexer being further away from the bending area than the first multiplexer.

In some embodiments, each of the two signal output lines is electrically connected to a column of sub-pixels.

In some embodiments, the two signal output lines of the second multiplexer are between two first multiplexers adjacent to the second multiplexer.

In some embodiments, the display panel further comprises: a first fanout area between the bending area and the display area; a second fanout area between the bending area and the plurality of multiplexers; and a third fanout area between the plurality of multiplexers and the bonding area; wherein the bonding area is electrically connected to the plurality of multiplexers through the third fanout area, and the plurality of multiplexers are electrically connected to the plurality of sub-pixels through the second fanout area, the bending area and the first fanout area.

In some embodiments, the display panel further comprises: a cell test area between the plurality of multiplexers and the second fanout area, wherein the cell test area is electrically connected to the plurality of sub-pixels through the second fanout area, the bending area and the first fanout area; and an electrostatic discharge area between the cell test area and the plurality of multiplexers, wherein the electrostatic discharge area is electrically connected to the plurality of multiplexers, and the electrostatic discharge area is electrically connected to the cell test area.

In some embodiments, each of the plurality of multiplexers comprises: a first transistor comprising a first electrode, a second electrode, and a control electrode, wherein the first electrode is electrically connected to the bonding area through the signal input line, the first electrode is configured to receive a data signal, the second electrode of the first transistor is electrically connected to a first column of sub-pixels through one signal output line of the two signal output lines, and the control electrode of the first transistor is configured to receive a first control signal; and a second transistor comprising the first electrode shared with the first transistor, a second electrode, and a control electrode, wherein the second electrode of the second transistor is electrically connected to a second column of sub-pixels through another signal output line of the two signal output lines, and the control electrode of the second transistor is configured to receive a second control signal.

In some embodiments, each of the plurality of sub-pixels comprises: a third transistor comprising: an active layer; a first insulating layer covering the active layer; a gate on a side of the first insulating layer away from the active layer; a second insulating layer covering the gate; an interlayer insulating layer on a side of the second insulating layer away from the gate; and a source and a drain on a side of the interlayer insulating layer away from the second insulating layer, the source and the drain each being electrically connected to the active layer; and a capacitor comprising: a first conductive layer in the same layer as the gate, wherein the first conductive layer is covered by the second insulating layer; and a second conductive layer on a side of the second insulating layer away from the first conductive layer, wherein the second conductive layer is covered by the interlayer insulating layer.

In some embodiments, in each of the plurality of multiplexers, the first electrode, the second electrode of the first transistor, and the second electrode of the second transistor are all in the same layer as the source and the drain, and the control electrode of the first transistor and the control electrode of the second transistor are in the same layer as the gate.

In some embodiments, the signal input line of the first multiplexer and the signal input line of the second multiplexer are in different layers.

In some embodiments, the first electrode of the first multiplexer is electrically connected to the signal input line of the first multiplexer, and the signal input line of the first multiplexer is in the same layer as the second conductive layer; and the first electrode of the second multiplexer is electrically connected to the signal input line of the second multiplexer, and the signal input line of the second multiplexer is in the same layer as the gate.

In some embodiments, the two signal output lines comprise: a first signal output line in the same layer as the second conductive layer, wherein the first signal output line is electrically connected to the second electrode of the first transistor; and a second signal output line in the same layer as the gate, wherein the second signal output line is electrically connected to the second electrode of the second transistor.

In some embodiments, each of the plurality of sub-pixels further comprises: a third insulating layer covering the source and the drain; a first planarization layer on a side of the third insulating layer away from the source and the drain; a third conductive layer on a side of the first planarization layer away from the third insulating layer, wherein the third conductive layer is electrically connected to the source or the drain; a second planarization layer covering the third conductive layer; an anode layer on a side of the second planarization layer away from the third conductive layer, wherein the anode layer is electrically connected to the third conductive layer; a pixel defining layer on the second planarization layer, the pixel defining layer comprising an opening exposing at least a part of the anode layer; a functional layer in the opening and connected to the anode layer; and a cathode layer on a side of the functional layer away from the anode layer.

In some embodiments, the bending area comprises a plurality of first wires, each of which is in the same layer as the third conductive layer, and is electrically connected to the display area through a second wire or a third wire, wherein the second wire is in the same layer as the gate, and the third wire is in the same layer as the second conductive layer.

According to another aspect of embodiments of the present disclosure, a display device is provided. The display device comprises the display panel as described previously.

Other features and advantages of the present disclosure will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings.

It should be understood that the dimensions of the various parts shown in the accompanying drawings are not necessarily drawn according to the actual scale. In addition, the same or similar reference signs are used to denote the same or similar components.

DETAILED DESCRIPTION

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative and is in no way intended as a limitation to the present disclosure, its application or use. The present disclosure may be implemented in many different forms, which are not limited to the embodiments described herein. These embodiments are provided to make the present disclosure thorough and complete, and fully convey the scope of the present disclosure to those skilled in the art. It should be noticed that: relative arrangement of components and steps, material composition, numerical equations, and numerical values set forth in these embodiments, unless specifically stated otherwise, should be explained as merely illustrative, and not as a limitation.

The use of the terms “first”, “second” and similar words in the present disclosure do not denote any order, quantity or importance, but are merely used to distinguish between different parts. A word such as “comprise”, “include” or similar words means that the element before the word covers the element(s) listed after the word without excluding the possibility of also covering other elements. The terms “up”, “down”, “left”, “right”, or the like are used only to represent a relative positional relationship, and the relative positional relationship may be changed correspondingly if the absolute position of the described object changes.

In the present disclosure, when it is described that a particular device is located between the first device and the second device, there may be an intermediate device between the particular device and the first device or the second device, and alternatively, there may be no intermediate device. When it is described that a particular device is connected to other devices, the particular device may be directly connected to said other devices without an intermediate device, and alternatively, may not be directly connected to said other devices but with an intermediate device.

All the terms (comprising technical and scientific terms) used in the present disclosure have the same meanings as understood by those skilled in the art of the present disclosure unless otherwise defined. It should also be understood that terms as defined in general dictionaries, unless explicitly defined herein, should be interpreted as having meanings that are consistent with their meanings in the context of the relevant art, and not to be interpreted in an idealized or extremely formalized sense.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, these techniques, methods, and apparatuses should be considered as part of this specification.

FIG. 10is a schematic view showing a structure of a display panel in a related art. As shown inFIG. 10, the display panel comprise a display area10, a substrate201, a bending area210, a bonding area230, a first fanout area240, a fan-shaped circuit connection area1010and a plurality of multiplexers1020. As shown inFIG. 10, the multiplexer1020is disposed between the display area10and the bending area210. The multiplexer1020is below the display area10.FIG. 11is an enlarged schematic view showing a partial structure of a display panel in a related art at block1040shown inFIG. 10. As shown inFIG. 11, the display panel also comprises a GOA circuit (Gate Driver on Array, also i.e., a gate driving circuit)1102at the frame of the display panel.

The inventors of the present disclosure have found that, as shown inFIG. 11, in the related art, since the multiplexer1020is disposed between the display area10and the bending area210, and a signal line of the GOA circuit at a lower fillet or corner position of the display panel is required to be transversely connected to the sub-pixels of the display area, the signal line of the GOA circuit and the multiplexer1020placed vertically at the fillet are likely to cause a wiring conflict.

In view of this, the inventors of the present disclosure propose a display panel to reduce the wiring conflict between the multiplexer and the signal line of the GOA circuit. The display panel according to some embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

FIG. 1is a schematic view showing a structure of a display panel according to an embodiment of the present disclosure.

As shown inFIG. 1, the display panel comprises a display area10and a peripheral area20surrounding the display area10. The display area10comprises a pixel array on a substrate (for example, a substrate201shown inFIG. 3BorFIG. 5later). The pixel array comprises a plurality of sub-pixels101. The peripheral area20comprises a bending area210on a side of the display area10, a plurality of multiplexers221and222on a side of the bending area210away from the display area10, and a bonding area230on a side of the plurality of multiplexers away from the bending area210. The multiplexers221and222are on the substrate.

It should be noted that, in the embodiments of the present disclosure, the display area may comprise a part of the substrate below the display area, and the peripheral area may comprise another part of the substrate below the peripheral area.

In some embodiments, as shown inFIG. 1, each multiplexer is at least connected with one signal input line2210and two signal output lines2201and2202. The signal input line2210is electrically connected to the bonding area230. An orthographic projection of the signal input line2210on the substrate does not overlap with an orthographic projection of the bending area210on the substrate. In some embodiments, each signal output line2201or2202is electrically connected to a column of sub-pixels101. In this way, it is possible to reduce the number of pins in the integrated circuit, and lessen the process difficulty and cost of the module.

For example, the bonding area230comprises bonding terminals (for example, COP) for bonding an integrated circuit, or a signal input line for COF. The bonding area230is electrically connected to the plurality of multiplexers. The plurality of multiplexers are electrically connected to the plurality of sub-pixels101through the bending area210.

So far, a display panel according to some embodiments of the present disclosure is provided. The display panel comprises a display area and a peripheral area surrounding the display area. The display area comprises a pixel array on a substrate. The pixel array comprises a plurality of sub-pixels. The peripheral area comprises: a bending area on a side of the display area; a plurality of multiplexers on a side of the bending area away from the display area; and a bonding area on a side of the plurality of multiplexers away from the bending area. The plurality of multiplexers are on the substrate. Each multiplexer is at least connected with one signal input line and two signal output lines. The bonding area is electrically connected to the plurality of multiplexers. The plurality of multiplexers are electrically connected to the plurality of sub-pixels through the bending area. The signal input line is electrically connected to the bonding area. An orthographic projection of the signal input line on the substrate does not overlap with an orthographic projection of the bending area on the substrate. In the display panel, the plurality of multiplexers are disposed between the bending area and the bonding area, that is, below the bending area, so that a wiring conflict between the multiplexer and a signal line of a GOA circuit may be reduced. In addition, such design may also reduce the signal interference between the multiplexer and the signal line of the GOA circuit.

In addition, in the related art, since the multiplexer is provided between the display area and the bending area, the multiplexer is likely to be affected by a bending crack in the bending area. In the embodiments of the present disclosure, the multiplexer is disposed below the bending area. In this way, on the one hand, the number of the pins of the integrated circuit is reduced, and the cost of the integrated circuit and the difficulty of bending are lessened; on the other hand, a risk of a bending crack is also avoided as much as possible, thereby improving the yield.

In some embodiments, as shown inFIG. 1, the plurality of multiplexers comprise a first multiplexer221and a second multiplexer222. The second multiplexer222is further away from the bending area210than the first multiplexer221. For example, the signal output lines of the second multiplexer222are between two first multiplexers221adjacent to the second multiplexer222. In other words, the signal output lines of the second multiplexer222pass between the two first multiplexers adjacent to the second multiplexer.

In the embodiment, the plurality of multiplexers comprise two rows of multiplexers. The two rows of multiplexers comprise a first multiplexer and a second multiplexer arranged in a staggered manner. The first multiplexer is in a first row, and the second multiplexer is in a second row. In other words, in the case where a certain multiplexer is in the first row, a multiplexer adjacent to the multiplexer is in the second row; and in the case where a certain multiplexer is in the second row, a multiplexer adjacent to the multiplexer is in the first row.

In the above-described embodiment, by arranging the plurality of multiplexers into two rows of multiplexers, a transverse width of the Pad area in the peripheral area (that is, a width of the Pad area is in a row direction of the plurality of multiplexers) can be reduced, and a length of the wiring of the multiplexers at both ends away from the bonding area can be reduced, thereby reducing the impedance of the wiring and improving the stability of the signal.

It should be noted that, although two rows of multiplexers are shown inFIG. 1, those skilled in the art can understand that three or more rows of multiplexers may be provided. Therefore, the scope of the embodiments of the present disclosure is not limited thereto.

FIG. 2is a schematic view showing a structural connection of a peripheral area of a display panel according to an embodiment of the present disclosure. As shown inFIG. 2, the display panel comprises the bending area210, the plurality of multiplexers221and222, and the bonding area230.

In some embodiments, as shown inFIG. 2, the display panel further comprises a first fanout area240between the bending area210and the display area10. In some embodiments, as shown inFIG. 2, the display panel further comprises a second fanout area250between the bending area210and the plurality of multiplexers221and222. In some embodiments, as shown inFIG. 2, the display panel further comprises a third fanout area260between the plurality of multiplexers221and222and the bonding area230. The bonding area230is electrically connected to the plurality of multiplexers through the third fanout area260. The plurality of multiplexers are electrically connected to the plurality of sub-pixels in the display area10through the second fanout area250, the bending area210, and the first fanout area240.

In some embodiments, as shown inFIG. 2, the display panel further comprises a cell test (referred to as CT for short) area270between the plurality of multiplexers221and222and the second fanout area250. The cell test area270is electrically connected to the plurality of sub-pixels through the second fanout area250, the bending area210, and the first fanout area240.

In some embodiments, as shown inFIG. 2, the display panel further comprises an electrostatic discharge area280between the cell test area270and the plurality of multiplexers221and222. The plurality of multiplexers are electrically connected to the electrostatic discharge area280. The electrostatic discharge area (referred to as ESD for short)280is electrically connected to the cell test area270.

So far, the structure of the peripheral area of the display panel according to some embodiments of the present disclosure is provided. For example, the data signal may sequentially pass through the bonding area230, the third fanout area260, the plurality of multiplexers221or222, the electrostatic discharge area280, the cell test area270, the second fanout area250, the bending area210and the first fanout area240, and is transmitted to the sub-pixels in the display area10to drive the sub-pixels to emit light. In this way, the display function of the display panel may be realized.

FIG. 3Ais a schematic cross-sectional view showing a display panel in a related art.

FIG. 3Ashows the display area10, the multiplexer1020, the first fanout area240, the bending area210, the Pad area310, and the substrate201. In the embodiment, the Pad area310may comprise: the second fanout area, the cell test area, the electrostatic discharge area, the third fanout area, and the bonding area. The lower frame of the display panel comprises a portion of the peripheral area from the multiplexer1020to a bending portion of the bending area210. The inventors of the present disclosure have found that in the related art, since the multiplexer1020is disposed between the display area10and the bending area210, it is not favorable for narrowing the lower frame.

FIG. 3Bis a schematic cross-sectional view showing a display panel according to an embodiment of the present disclosure.

FIG. 3Bshows the display area10, the first fanout area240, the bending area210, the multiplexer221or222, the Pad area320, and the substrate201. In the embodiment, the Pad area320may comprise: the second fanout area, the cell test area, the electrostatic discharge area, the multiplexer221or222, the third fanout area, and the bonding area. In the embodiment, since the multiplexer221or222is disposed below the bending area, that is, the multiplexer is disposed on the back of the display panel, compared to the display panel shown inFIG. 3A, the display panel of some embodiments of the present disclosure may apparently narrow the lower frame. For example, the lower frame of the display panel in the embodiment may be reduced by about190micrometers (pm). Therefore, the display panel of the embodiments of the present disclosure may not only reduce a conflict between the multiplexer and the signal line of the GOA circuit, but also make the lower frame of the display panel narrower, thereby promoting the realization of a full screen.

Here, the bending area refers to an area from a starting position of a surface curvature of the substrate to an ending position of the surface curvature of the substrate, or may also be considered to refer to a position interval where a curvature of the substrate changes, as shown inFIG. 3B.

FIG. 4is a schematic view showing a circuit connection of a multiplexer according to an embodiment of the present disclosure.

As shown inFIG. 4, each multiplexer221(or222) comprises a first transistor M1and a second transistor M2. The first transistor M1and the second transistor M2share a first electrode401. The first electrode401is electrically connected to the bonding area230through the signal input line. The first electrode is configured to receive a data signal SD.

A second electrode412of the first transistor M1is electrically connected to a first column of sub-pixels through one signal output line of the two signal output lines. A control electrode413of the first transistor M1is configured to receive a first control signal SG1. The first transistor M1is configured to be turned on or off under the control of the first control signal SG1.

A second electrode422of the second transistor M2is electrically connected to a second column of sub-pixels through the other signal output line of the two signal output lines. The second column of sub-pixels are different from the first column of sub-pixels. A control electrode423of the second transistor M2is configured to receive a second control signal SG2. The second transistor M2is configured to be turned on or off under the control of the second control signal SG2.

So far, the circuit structure of the multiplexer according to some embodiments of the present disclosure is provided. In the multiplexer, the first control signal is used to control the first transistor, and the second control signal is used to control the second transistor, so that the data signal received by the common electrode (i.e., the first electrode) of the two switching transistors is transmitted to a corresponding sub-pixel through the first transistor or the second transistor, so as to implement that the sub-pixel emits light. The multiplexer may reduce the number of pins of the integrated circuit and lessen the difficulty and cost of the module process.

In some embodiments, the first transistor M1and the second transistor are NMOS (N-channel Metal Oxide Semiconductor) transistors. In other embodiments, the first transistor M1and the second transistor are PMOS (P-channel Metal Oxide Semiconductor) transistors.

FIG. 5is a schematic cross-sectional view showing a sub-pixel of a display panel according to an embodiment of the present disclosure. As shown inFIG. 5, each sub-pixel comprises a pixel circuit for driving the sub-pixel to emit light. The pixel circuit comprises a third transistor510and a capacitor530. That is, each sub-pixel comprises the third transistor510and the capacitor530. The third transistor510and the capacitor530are both above the substrate201. For example, the third transistor510is a switching transistor or a driving transistor.

In some embodiments, the above-described pixel circuit may be a pixel circuit such as 2T1C, 3T1C, 7T1C, 7T2C, 9T1C, or 9T2C. Here, “T” represents a transistor, and “C” represents a capacitor. For example, 2T1C represents a pixel circuit comprising 2 transistors and 1 capacitor. Of course, those skilled in the art can understand that the pixel circuit herein is not limited to the pixel circuit disclosed here, but may also be a pixel circuit with other structures, as long as it may drive the light-emitting device to emit light.

As shown inFIG. 5, the third transistor510comprises an active layer (for example, it may be referred to as a first active layer)511. For example, the active layer511is on the buffer layer501. The buffer layer501is on the substrate201. For example, the active layer511comprises a semiconductor layer. For example, a material of the active layer511comprise at least one of polysilicon or amorphous silicon.

As shown inFIG. 5, the third transistor510further comprises a first insulating layer512covering the active layer511. For example, the first insulating layer512is an inorganic insulating layer. For example, a material of the first insulating layer512comprises silicon dioxide, silicon nitride, or the like.

As shown inFIG. 5, the third transistor510further comprises a gate513on a side of the first insulating layer512away from the active layer511. For example, a material of the gate513comprises a metal such as molybdenum (Mo).

As shown inFIG. 5, the third transistor510further comprises a second insulating layer514covering the gate513. For example, a material of the second insulating layer514is an inorganic insulating layer, such as silicon dioxide, silicon nitride, or the like.

As shown inFIG. 5, the third transistor510further comprises an interlayer insulating layer516on a side of the second insulating layer514away from the gate513. For example, a material of the interlayer insulating layer516comprises an inorganic insulating material. For example, the inorganic insulating material comprises silicon dioxide, silicon nitride, or the like.

As shown inFIG. 5, the third transistor510further comprises a source517and a drain518on a side of the interlayer insulating layer516away from the second insulating layer514. For example, a material of the source517and a material of the drain518comprise at least one of titanium (Ti) or aluminum (Al). For example, the source517and the drain518each comprises such a three-layer structure as Ti layer/Al layer/Ti layer. The source517and the drain518are electrically connected to the active layer511. For example, the source517is electrically connected to the active layer511through a first conductive via521passing through the first insulating layer512, the second insulating layer514, and the interlayer insulating layer516. For another example, the drain518is electrically connected to the active layer511through a second conductive via522passing through the first insulating layer512, the second insulating layer514, and the interlayer insulating layer516.

So far, the third transistor of the sub-pixel according to some embodiments of the present disclosure has been described.

In some embodiments, as shown inFIG. 5, the capacitor530comprises a first conductive layer531in the same layer as the gate513. For example, a material of the first conductive layer531is the same as a material of the gate513. This may facilitate the manufacture of the display panel. The first conductive layer531is covered by the second insulating layer514. As shown inFIG. 5, the capacitor530further comprises a second conductive layer532on a side of the second insulating layer514away from the first conductive layer531. The second conductive layer532is covered by the interlayer insulating layer516. For example, the materials of the first conductive layer531and the second conductive layer532both comprise metals such as molybdenum. The capacitor530may function to store data.

It should be noted that the “the same layer” in the embodiments of the present disclosure refers to a film layer on the same structural layer. In other words, for example, the film layer in the same layer may be a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate to pattern the film layer through a single patterning process. Depending on different specific patterns, a single patterning process may comprise multiple exposing, developing or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

For example, the first conductive layer531is in the same layer as the gate513. The first conductive layer531and the gate513are both on the first insulating layer512. For example, the first conductive layer531and the gate513may be formed by the same patterning process.

In some embodiments, as shown inFIG. 5, each sub-pixel further comprises a third insulating layer541covering the source517and the drain518. For example, a material of the third insulating layer541comprises silicon dioxide, silicon nitride, or the like.

As shown inFIG. 5, the sub-pixel further comprises a first planarization layer542on a side of the third insulating layer541away from the source517and the drain518. For example, a material of the first planarization layer542comprises an organic insulating material.

As shown inFIG. 5, the sub-pixel further comprises a third conductive layer543on a side of the first planarization layer542away from the third insulating layer541. The third conductive layer543is electrically connected to the source517or the drain518. For example, a material of the third conductive layer543comprises at least one of titanium (Ti) or aluminum (Al). For example, the third conductive layer543may comprise such a three-layer structure as Ti layer/Al layer/Ti layer. For example, the third conductive layer543is electrically connected to the source517or the drain518through a third conductive via523passing through the third insulating layer541and the first planarization layer542.

As shown inFIG. 5, the sub-pixel further comprises a second planarization layer544covering the third conductive layer543. For example, a material of the second planarization layer544comprises an organic insulating material.

As shown inFIG. 5, the sub-pixel further comprises an anode layer545on a side of the second planarization layer544away from the third conductive layer543. The anode layer545is electrically connected to the third conductive layer543. For example, the anode layer545is electrically connected to the third conductive layer543through a fourth conductive via524passing through the second planarization layer544.

As shown inFIG. 5, the sub-pixel further comprises a pixel defining layer546on the second planarization layer544. The pixel defining layer comprising an opening5461exposing at least a part of the anode layer545.

As shown inFIG. 5, the sub-pixel further comprises a functional layer547in the opening5461and connected to the anode layer545. For example, the functional layer547comprises a light-emitting layer or the like.

As shown inFIG. 5, the sub-pixel further comprises a cathode layer548on a side of the functional layer547away from the anode layer545. In the embodiments of the present disclosure, the light emitting device comprises the anode layer545, the functional layer547, and the cathode layer548.

In some embodiments, the display panel comprises an encapsulation layer549covering the cathode layer548.

So far, the structure of the sub-pixel of the display panel according to some embodiments of the present disclosure is provided. The sub-pixels may comprise the third transistor, the capacitor, the light emitting device, and the like. Of course, those skilled in the art may understand that the sub-pixel may also comprise other structures or layers, which will not be described in detail here.

FIG. 6Ais a top view showing a multiplexer according to an embodiment of the present disclosure.FIG. 6Bis a schematic view showing a cross-section of a multiplexer according to an embodiment of the present disclosure taken along a line A-A′ inFIG. 6A.

FIG. 6Ashows the multiplexers221and222. As shown inFIG. 6A, each multiplexer221or222comprises the second electrode412and the control electrode413of the first transistor, the second electrode422and the control electrode423of the second transistor, and the first electrode401shared by the first transistor and the second transistor. In addition,FIG. 6Aalso shows an anti-static unit282of the electrostatic discharge area280.

In some embodiments, as shown inFIG. 6A, in each multiplexer221or222, the first electrode401, the second electrode412of the first transistor, and the second electrode422of the second transistor are all in the same layer as the source517and the drain518. For example, the first electrode401, the second electrodes412and422, the source517, and the drain518are all on the interlayer insulating layer516. As shown inFIG. 6B, the first electrode401, the second electrode412of the first transistor, and the second electrode422of the second transistor are all on the interlayer insulating layer516. Such design as to be in the same layer may facilitate the manufacture of the display panel and save the cost.

In some embodiments, as shown inFIG. 6A, the control electrode413of the first transistor and the control electrode423of the second transistor are in the same layer as the gate513. For example, the control electrode413of the first transistor, the control electrode423of the second transistor and the gate513are all on the first insulating layer512. As shown inFIG. 6B, the control electrode413of the first transistor and the control electrode423of the second transistor are both on the first insulating layer512. Such design as to be in the same layer may facilitate the manufacture of the display panel and save the cost.

In some embodiments, as shown inFIG. 6B, in each multiplexer, the first transistor and the second transistor share an active layer (which may be referred to as a second active layer)414. The second active layer414is on the buffer layer501. Therefore, the second active layer414and the active layer (i.e., the first active layer)511of the third transistor are in the same layer.

As shown inFIG. 6B, the first electrode401is electrically connected to the second active layer414through a fifth conductive via431. The fifth conductive via431passes through the interlayer insulating layer516, the second insulating layer514, and the first insulating layer512. The second electrode412of the first transistor is electrically connected to the second active layer414through a sixth conductive via432. The sixth conductive via432passes through the interlayer insulating layer516, the second insulating layer514, and the first insulating layer512. The second electrode422of the second transistor is electrically connected to the second active layer414through a seventh conductive via433. The seventh conductive via433passes through the interlayer insulating layer516, the second insulating layer514, and the first insulating layer512. Here, the second electrode412of the first transistor is electrically connected to one end of the second active layer414, and the second electrode422of the second transistor is electrically connected to the other end of the second active layer414.

FIG. 6Cis a schematic view showing a cross-section of a multiplexer according to an embodiment of the present disclosure taken along a line B-B′ inFIG. 6A.

In some embodiments, as shown inFIGS. 6A and 6C, the signal input line2210(for example, which may be referred to as a first signal input line2211) of the first multiplexer221and the signal input line2210(for example, which may be referred to as a second signal input line2212) of the second multiplexer222are in different layers.

In some embodiments, the first electrode401of the first multiplexer221is electrically connected to the signal input line2210(i.e., the first signal input line2211) of the first multiplexer221. The signal input line of the first multiplexer221is in the same layer as the second conductive layer532. For example, the signal input line of the first multiplexer221and the second conductive layer532are both on the second insulating layer514. As shown inFIG. 6C, the first signal input line2211is on the second insulating layer514.

In some embodiments, the first electrode401of the second multiplexer222is electrically connected to the signal input line2210(i.e., the second signal input line2212) of the second multiplexer222. The signal input line of the second multiplexer222is in the same layer as the gate513. For example, the signal input line of the second multiplexer222and the gate513are both on the first insulating layer512. As shown inFIG. 6C, the second signal input line2212is on the first insulating layer512.

In the above-described embodiment, the signal input line of the first multiplexer is in the same layer as the second conductive layer, and the signal input line of the second multiplexer is in the same layer as the gate, so that it is possible to facilitate the manufacture of the display panel and save the cost. In addition, it is also possible to avoid a risk of short-circuit of the signal input lines of different multiplexers.

FIG. 7Ais an enlarged schematic view showing a partial structure of a multiplexer according to an embodiment of the present disclosure at block610shown inFIG. 6A.

In some embodiments, as shown inFIGS. 6A and 7A, the display panel may further comprise a first scan signal line601and a second scan signal line602which are electrically connected to each multiplexer. The first scan signal line601is electrically connected to the control electrode413of the first transistor. The first scan signal line601may transmit the first control signal to the first transistor. The second scan signal line602is electrically connected to the control electrode423of the second transistor. The second scan signal line602may transmit the second control signal to the second transistor. This can realize the control of the multiplexer.

In some embodiments, as shown inFIG. 7A, a number of conductive vias may be provided between two layer structures required to be electrically connected to each other (for example, between the first scan signal line601and the control electrode413of the first transistor, or the like), which may reduce a connection impedance between the two layer structures.

FIG. 7Bis a schematic view showing a cross-section of a structure taken along a line C-C′ inFIG. 7A.

As shown inFIG. 7B, the first scan signal line601is located on the interlayer insulating layer516. Therefore, the first scan signal line601may be on the same layer as the source517and the drain518of the third transistor. The first scan signal line is electrically connected to the control electrode413of the first transistor through the eighth conductive via711. The eighth conductive via711passes through the interlayer insulating layer516and the second insulating layer514. In addition, the manner in which the second scan signal line602is electrically connected to the control electrode423of the second transistor is similar to the manner in which the first scan signal line is electrically connected to the control electrode413of the first transistor, and thus will not be described in detail here.

FIG. 7Cis a schematic view showing a cross-section of a structure taken along a line D-D′ inFIG. 7A.

As shown inFIG. 7C, the first electrode401of the first multiplexer221is electrically connected to the first signal input line2211through a ninth conductive via712. The ninth conductive via712passes through the interlayer insulating layer516. In this way, the electrical connection between the first electrode and the first signal line is realized.

In other embodiments, the first electrode401of the second multiplexer222is electrically connected to the second signal input line2212through a tenth conductive via (not shown). The tenth conductive via passes through the interlayer insulating layer516and the second insulating layer514.

FIG. 8Ais an enlarged schematic view showing a partial structure of a multiplexer according to an embodiment of the present disclosure at block620shown inFIG. 6A.FIG. 8Bis a schematic view showing a cross-section of a structure taken along a line E-E′ inFIG. 8A.

As shown inFIGS. 6A and 8A, the two signal output lines of each multiplexer comprise a first signal output line2201and a second signal output line2202. As shown inFIGS. 8A and 8B, the second electrode412of the first transistor is electrically connected to the first signal output line2201. The first signal output line2201is in the same layer as the second conductive layer532. For example, the first signal output line2201and the second conductive layer532are both on the second insulating layer514. Such design as to be in the same layer may facilitate the manufacture of the display panel and save the cost.

As shown inFIG. 8B, the first signal output line2201is on the second insulating layer514. The second electrode412of the first transistor is electrically connected to the first signal output line2201through an eleventh conductive via811. The eleventh conductive via811passes through the interlayer insulating layer516.

The second electrode422of the second transistor is electrically connected to the second signal output line2202. The second signal output line2202is in the same layer as the gate513. For example, the second signal output line2202and the gate513are both on the first insulating layer512. Such design as to be in the same layer may facilitate the manufacture of the display panel and save the cost.

As shown inFIG. 8B, the second signal output line2202is on the first insulating layer512. The second electrode422of the second transistor is electrically connected to the second signal output line2202through a twelfth conductive via812. The twelfth conductive via812passes through the interlayer insulating layer516and the second insulating layer514.

In other embodiments, if the signal input lines are not connected to other structures (for example, electrodes) in a layer-change manner, the signal input lines may be integrally formed. In other embodiments, if the signal output lines are not connected to other structures (for example, electrodes)s in a layer-change manner, the signal output lines may be integrally formed.

FIG. 9is a schematic view showing a structure of a bending area of a display panel according to an embodiment of the present disclosure.

As shown inFIG. 9, the bending area210comprises a plurality of first wires211. Each of the plurality of first wires211is in the same layer as the third conductive layer543. For example, the first wire211and the third conductive layer543are both on the first planarization layer542. Such design as to be in the same layer may facilitate the manufacture of the display panel and save the cost.

As shown inFIG. 9, each first wire211is electrically connected to the display area through a second wire902or a third wire903. The second wire902is in the same layer as the gate513. For example, the second wire902and the gate513are both on the first insulating layer512. The third wire903is in the same layer as the second conductive layer532. For example, the third wire903and the second conductive layer532are both on the second insulating layer514. Such design may avoid short-circuit between the second wire and the third wire as much as possible.

In an embodiment of the present disclosure, a display device is also provided. The display device comprises the display panel as described above. For example, the display device is any product or member having a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or the like.

Hereto, various embodiments of the present disclosure have been described in detail. Some details well known in the art are not described to avoid obscuring the concept of the present disclosure. According to the above description, those skilled in the art would fully know how to implement the technical solutions disclosed herein.

Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for the purpose of illustration and are not intended to limit the scope of the present disclosure. It should be understood by those skilled in the art that modifications to the above-described embodiments or equivalently substitution of part of the technical features may be made without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.