Fin structure formation including partial spacer removal

A method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate.

BACKGROUND

This disclosure relates generally to semiconductor device fabrication, and more particularly to fin structure formation including partial spacer removal for formation of a semiconductor device.

Field effect transistors (FETs) are used to make semiconductor chips for various applications, such as application specific integrated circuit (ASIC) chips, microprocessor chips, and static random access memory (SRAM) chips. Complementary metal-oxide-semiconductor (CMOS) processing technology is used to form FET devices.

Technology advances have scaled FETs on semiconductor chips to increasingly small dimensions, allowing power per logic gate to be dramatically reduced, and further allowing a very large number of FETs to be fabricated on a single semiconductor chip. However, scaling of FETs runs into physical limitations. Gate oxides have become thin enough that leakage occurs through the gate oxides. Further scaling of gate oxide thickness may cause an exponential increase in leakage. Power dissipated by leakage currents has become a significant portion of total chip power, and an exponential increase in leakage results in unacceptable power dissipation for many types of chips.

A finFET is a type of FET device that utilizes three dimensional techniques to pack a large number of FETs in a given area of a semiconductor chip while reducing some of the problems described above. A finFET may include a relatively tall, thin semiconductor fin structure comprising a semiconductor material. Formation of a finFET fin structure may include forming mandrels on a substrate, forming spacers around the mandrels, removing the mandrels, and etching the spacer pattern into the substrate to form the fin structures. A cut mask may then be applied to the fin structures to remove any portions of the fin structures that are undesired in the finFET device. However, application of a cut mask to the fin structures may have a relatively small margin of error, and misalignment of the cut mask to a fin structure that is being removed may lead to undesired cutting of adjacent fin structures.

SUMMARY

In one aspect, a method of forming a semiconductor device includes forming a mandrel on top of a substrate; forming a first spacer adjacent to the mandrel on top of the substrate; forming a cut mask over the first spacer and the mandrel, such that the first spacer is partially exposed by the cut mask; partially removing the partially exposed first spacer; and etching the substrate to form a fin structure corresponding to the partially removed first spacer in the substrate.

In another aspect, a method of forming a semiconductor device includes forming a plurality of mandrels on top of a substrate; forming a plurality of spacers on top of the substrate, wherein each of the plurality of spacers is located adjacent to one of the plurality of mandrels; forming a cut mask over the plurality of mandrels and the plurality of spacers, such that a first portion of the plurality of spacers are exposed by the cut mask, and a second portion of the plurality of spacers are covered by the cut mask; removing the first portion of the plurality of spacers; removing the cut mask; removing the plurality of mandrels after removing the cut mask; and etching the substrate to form a plurality of fin structures corresponding to the second portion of the plurality of spacers in the substrate.

In another aspect, a semiconductor device precursor structure, includes a substrate; a first spacer located on top of a first portion of the substrate; and a second spacer located on top of a second portion of the substrate, adjacent to the first spacer; and a cut mask located over the first spacer and the second spacer, wherein the first spacer is partially exposed by the cut mask and wherein the second spacer is fully covered by the cut mask, and wherein a width of the first spacer is the same as a width of the second spacer, and a height of the first spacer is less than a height of the second spacer.

Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings.

DETAILED DESCRIPTION

Embodiments of methods for fin structure formation including partial spacer removal, and a device formed by methods for fin structure formation including partial spacer removal, are provided, with exemplary embodiments being discussed below in detail. The cut mask may be applied to the spacers and the mandrels before mandrel removal. If there is cut mask misalignment and a spacer corresponding to a fin structure that needs to be present in the final device is partially exposed by the cut mask, the cut mask and the mandrel adjacent to the spacer may together protect the partially exposed spacer during spacer removal, such that the partially exposed spacer is only partially removed. The partially removed spacer may then be used to form a corresponding fin structure in the substrate. In some embodiments, the fin structures may comprise a semiconductor material such as silicon for a finFET device. In other embodiments, the fin structures that are formed using partial spacer removal may comprise gates, conductive lines, or dielectric lines.

The height of the spacers may be significantly greater than the width of the spacers. For example, a spacer may be about 10 nanometers (nm) wide, and from about 70 nm tall to about 100 nm tall, in some embodiments. Because the mandrel and the cut mask both protect the partially exposed spacer during the spacer etch, only a top portion of the partially exposed spacer may be removed. Therefore, a partially removed spacer is shorter than a non-partially-removed spacer, but has the same width. This results in formation of a fin structure in the substrate corresponding to the partially removed spacer that has the same dimensions as a fin structure that is formed using a non-partially-removed spacer, as, while the fin structure width is determined by the spacer width, the fin structure height is independent of the spacer height. The partially removed spacer only needs to have sufficient height to withstand the etching of the spacer pattern into the substrate.

FIG. 1illustrates a flowchart of an embodiment of a method100for fin structure formation including partial spacer removal. In some embodiments, fin structures that are formed using method100may comprise a semiconductor material, while in other embodiments, the fin structures that are formed by method100may comprise gates, conductive lines, or dielectric lines.FIG. 1is discussed with reference toFIGS. 2A and 2Bthrough8A and8B. First, in block101, mandrels and spacers that surround the mandrels are formed on a hardmask layer that is located on a substrate. The hardmask, mandrels, and spacers may each comprise any appropriate material and may be formed over the substrate in any appropriate manner. In some embodiments, the spacers may be formed using a sidewall image transfer (SIT) technique. In some embodiments, the mandrels may be polysilicon, the spacers may be nitride, and the hardmask may be oxide. In other embodiments, the hardmask may comprise nitride, the mandrels may comprise amorphous carbon, and the spacers may comprise a metal, such as titanium nitride (TiN), or oxide. In various embodiments, the substrate may comprise a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In further embodiments, the substrate may also include various semiconductor device structures, including but not limited to isolation regions comprising dielectric material, gate material, and/or metal contacts.FIGS. 2A and 2Billustrate, respectively, a top view and cross-section of an embodiment of a device200with mandrels203that are surrounded by spacers204. The mandrels203and spacers204are located on a hardmask201, and hardmask201is located on top of a substrate202. In some embodiments, mandrels203are polysilicon, spacers204are a nitride, and hardmask201is an oxide.FIG. 2is shown for illustrative purposes only; a device including mandrels and spacers on a substrate that is formed during block101ofFIG. 1may have any appropriate number of mandrels and associated spacers, and the mandrels and spacers may have any appropriate configuration.

Flow of method100proceeds from block101to block102, in which a cut mask is formed over the mandrels and spacers. The cut mask defines exposed areas of the finished device in which a fin structure is not desired. The cut mask may comprise photoresist in some embodiments, and may be formed by applying a layer of photoresist over the device, exposing the layer of photoresist to light through a mask, and removing the portions of the photoresist that were exposed to the light. In other embodiments, the cut mask my comprise spin-on-glass that is patterned using lithography and etching.FIGS. 3A and 3Bshow the device200ofFIGS. 2A and 2Bafter formation of a cut mask301over the mandrels203and the spacers204. Portions of the mandrels203and spacers204are exposed by cut mask301in exposed areas302A,302B and302C, such as fully exposed spacer304in exposed area302B, a cross section of which is shown inFIG. 3B. The cut mask301may be misaligned to the spacers204, as illustrated by partially exposed spacer303in exposed area302B. Partially exposed spacer303is located partially underneath the cut mask301. Cut mask301of the semiconductor device precursor structure ofFIG. 3is shown for illustrative purposes only; a cut mask may cover any appropriate areas of a device, and may fully and/or partially expose any appropriate amount of spacers.

Next, in block103ofFIG. 1, the spacers that are located in the exposed areas are etched. Etching of the spacers comprises an isotropic etch, and may comprise any appropriate etch chemistry. In some embodiments, the etch that is performed during block103of method100may include a wet etch with an etch solution comprising a phosphoric acid (H3PO4) etch or a dry etch such as chemical downstream etch with an etchant comprising CH3F, CH2F2, and/or CF4in conjunction with O2. The fully exposed spacers in the exposed areas are fully removed by the spacer etch that is performed during block103, while the partially exposed spacers are only partially removed. The partially exposed spacers are only partially removed because the partially exposed spacers are protected by adjacent mandrels and partially covered by the cut mask during the spacer etch of block103.FIGS. 4A and 4Bshow the device300ofFIGS. 3A and 3Bafter etching of the spacers204(including partially exposed spacer303and fully exposed spacer304in exposed area302B ofFIGS. 3A and 3B) in the exposed areas302A,302B and302C. Any spacers204in exposed areas302A,302B and302C such as fully exposed spacer304in exposed area302B, that were fully exposed by cut mask301are completely removed by the spacer etch that is performed in block103, exposing hardmask201. The partially exposed spacer303in exposed area302B that was shown inFIGS. 3A and 3Bis only partially removed by the spacer etch, forming partially removed spacer401. Partially removed spacer401has a height that is less than the height of spacers204that were fully covered by the cut mask301during the spacer etch of block103, and a width that is the same than the width of covered spacers204.

Returning now toFIG. 1, flow proceeds to block104, in which the cut mask is removed from the device. The cut mask may be removed in any appropriate manner. For example, in the case that the cut mask comprise photoresist, it may be removed using a dry etch, such as ashing, or wet etch comprising sulfuric peroxide.FIGS. 5A and 5Bshow the device400ofFIGS. 4A and 4Bremoval of the cut mask301. The mandrels203and spacers204/401are left on the hardmask201after removal of the cut mask301. As shown inFIG. 5B, partially removed spacer401is shorter than the spacers204that were protected by cut mask301during the spacer etch of block103. Then, in block105of method100, the mandrels are also removed. The mandrels may be removed in any appropriate manner; the technique used to remove the mandrels may depend on the material that comprises the mandrels.FIGS. 6A and 6Bshow the device500ofFIGS. 5A and 5Bafter removal of the mandrels203, leaving spacers204and partially removed spacer401on the hardmask201.

Next, in block106ofFIG. 1, fin structures corresponding to the spacers are formed in the substrate. Fin structure formation as is performed in block106may comprise a two-step etch in some embodiments; first, the hardmask may be etched, using the spacers as a mask with a first etch chemistry, and then the substrate may be etched to form the fin structures in the substrate, using the etched hardmask as a mask with a second etch chemistry. In embodiments in which the substrate comprises bulk silicon, the height of the fin structures that are formed in block106may be determined by the etch time of the etch of the substrate. In embodiments in which the substrate comprises an SOI substrate, the height of the fin structures may be determined by the depth of a buried oxide (BOX) layer in the substrate. In embodiments in which the substrate comprises other semiconductor metal contacts, the metal contacts may be etched during fin structure formation to form fin structures comprising conductive lines. In further embodiments, the substrate may comprise gate or dielectric material that is etched during fin structure formation to form fin structures comprising gates or dielectric lines.FIGS. 7A and 7Bshow the device600ofFIGS. 6A and 6Bafter etching of hardmask201and substrate202to form etched hardmask701and fin structures702. The locations of fin structures702correspond to the locations of spacers204/401. The fin structure702that is located underneath partially removed spacer401has the same dimensions as the fin structures702that are located underneath the other spacers204. The fin structures702may comprise silicon fin structures, gates, conductive lines, or dielectric lines in various embodiments.

Lastly, in block107ofFIG. 1, the spacers are removed, leaving a semiconductor device with fin structures formed thereon. The spacers may be removed in any appropriate manner.FIGS. 8A and 8Bshow the device700ofFIGS. 7A and 7Bafter removal of the spacers204/401, leaving etched hardmask701and fin structures702on substrate202. Any appropriate semiconductor processing steps may be subsequently applied to device800ofFIGS. 8A and 8B, as necessary, to form a finished semiconductor device, such as a finFET.

The technical effects and benefits of exemplary embodiments include reduced effects due to misalignment of the cut mask in a semiconductor device that includes fin structures.