Apparatus and method for integrated circuit design with improved delay variation calculation based on power supply variations

An integrated circuit design apparatus is provided with a power supply voltage variation analysis tool calculating variations of power supply voltages of respective instances integrated within a target circuit; a determination module comparing the variations of the power supply voltages with first and second reference levels, the second reference level being smaller than the first reference level; a redesign module adapted to redesign the target circuit when at least one of the variations of the power supply voltages is larger than the first reference level; a delay variation calculation module adapted to correct circuit delay data of the respective instances based on the variations of the power supply voltages of the respective instances; a static timing analysis tool performing timing verification of the target integrated circuit. The timing verification in connection with each of the instances is performed based on the corrected circuit delay data, when a variation of a power supply voltage of the each of the instances is in a range from the second reference level to the first reference level, and performed based on the circuit delay data uncorrected, when the variation of the power supply voltage of the each of the instances is smaller than the second reference level.

INCORPORATION BY REFERENCE

This application claims the benefit of priority based on Japanese Patent Application No. 2007-163332, filed on Jun. 21, 2007, the disclosure of which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an apparatus, method and computer program product for design verification of semiconductor integrated circuits. More specifically, the present invention relates to power supply variation analysis and delay variation calculation based on power supply variations.

2. Description of the Related Art

In recent years, there are remarkable technology progresses in power supply voltage reduction and operation speed enhancement of semiconductor integrated circuits. On the other hand, the power supply voltage reduction and operation speed enhancement, as well as the increase in the interconnection resistance due to the reduction in dimensions of layout patterns, lead to the situation in which the variations in the power supply voltage are not negligible for ensuring the stable operations of the semiconductor integrated circuit.

Recently, attention is paid to power supply variation analysis for power supply noise, that is, variations in the power supply voltage and the ground voltage caused by semiconductor integrated circuit operations. For example, Lin et al. discloses a vectorless dynamic power-ground noise analysis approach in a non-patent document entitled: S Lin, M. Nagata, K. Shimazaki, K. Satoh, M. Sumita, H. Tsujikawa, A. T. Yang, “Full-chip Vectorless Dynamic Power Integrity Analysis and Verification Against 100 uV/100 ps-Resolution Measurement”, Proceedings of Custom Integrated Circuits Conference 2004, October 2004, Pp. 509-512. In the power supply variation analysis, variations in the power supply voltage and the ground voltage are calculated for desired one(s) of instances integrated within in the semiconductor integrated circuit.

InFIG. 5, typical models of power supply variation analysis are shown. InFIG. 5, instances A and B are instances incorporated within an integrated circuit for which the power supply variation analysis is to be performed. The output signals of the respective instances vary in response to signal level changes of the respective input signals. The signal level changes in the output signals cause generation of power supply currents through the power and ground lines, and the power supply currents cause variations in the voltage levels of the power and ground lines due to the resistances thereof. When the resistances of the power and ground lines of the instance B are larger than those of the instance A, the instance B experiences larger power supply variations. The magnitude of the power supply variations depends not only on the resistance of the power and ground lines but also by the buffer's drive capability, the output load capacitance, the slew rate of the input signal, the capacitance between the power and ground lines, and so on. The power supply variation analysis needs to be performed in light of these various factors.

One issue is that the analysis time necessary for power supply variation analysis undesirably increases as the increase in the integrated circuit scale, when the variations in the power supply voltage are analyzed for all instances integrated within the integrated circuit.

Also, one proposed approach for the reduction of the power supply variations is to integrate decoupling capacitors (or capacitor cells) within the integrated circuit. However, this approach suffers from the increase in the calculation time for determining the positions and capacitances of the decoupling capacitors.

Japanese Laid-Open Patent Application No. 2005-4268 (referred to as the '268 application, hereinafter) discloses a conventional method and apparatus for power supply variation analysis. A description is given of the disclosed method and apparatus in the following, referring toFIGS. 24 and 25.

FIG. 24is a flowchart showing the power supply variation analysis method disclosed in the '268 application. The disclosed method is directed to calculation time reduction of the power supply variation analysis by dividing the voltage calculation range, which is defined as the time period between the switching of the input signal Vin and the switching of the output signal Vout, into multiple time segments, by averaging or characterizing the voltage waveforms in the respective time segments.

A description is given next of the configuration of the power supply variation analysis apparatus disclosed in the '268 application, referring toFIG. 25.FIG. 25is a block diagram of the conventional power supply variation analysis apparatus. Layout data of the target LSI (large scale integrated circuit) are generated by the placement and routing section101and circuit connection data extracted from the layout data are fed to a power supply variation analysis section102. The power supply variation analysis section102analyzes the power supply variations to generate power supply variation report data103indicative of the power supply variations. The power supply variation report data103is fed to a delay calculation section104. The delay calculation section104performs delay calculation and outputs SDF (standard delay format) data which are circuit delay data associated with circuit blocks for which STA (static timing analysis) is to be performed later. The SDF data are inputted to an STA (static timing analysis) section105, and the STA section105generates timing report data106. The timing report data106is fed to an optimization section107, and the optimization section107performs circuit optimization.

Furthermore, Japanese Laid-Open Patent Application No. 2000-99554 (referred to as the '554 application, hereinafter) discloses an example of a delay library used for the power supply variation analysis. In detail, the '554 application discloses that buffer delay times are expressed in the delay library with three parameters: the slew rate of the input signal, the output load capacitance, and the power supply voltage.

The '554 application also discloses a integrated design technique which involves obtaining operating voltage distributions of the respective logic blocks depending on the positions of the power supply lines, performing initial schematic placement of the logic blocks, calculating the delay times of the respective logic blocks using the delay library, performing schematic placement of the logic blocks again so as to reduce the calculated delay time for the improvement of the operation timings of the logic blocks, and then performing detailed placement of the logic blocks.

In the conventional techniques (such as the technique disclosed in the '268 application), delay calculation is followed by timing analysis based on the delay calculation result. This is followed by cell arrangement optimization based on the timing analysis result, such as insertion of capacitor cells or movement of instances, when any timing error is discovered by the timing analysis. This undesirably necessitates performing the power supply variation analysis and timing analysis again after the cell arrangement optimization to determine whether the problem is solved by the cell arrangement optimization. This approach undesirably requires a longer time for converging the calculation result.

Furthermore, an operation of a certain circuit may cause a malfunction of another circuit when the integrated circuit suffers from large power supply voltage variations; however, such malfunction is often overlooked by ordinary static timing verification. The above-described conventional techniques give no considerations to this problem.

SUMMARY

According to the study of the inventor and his associates, it is substantially unnecessary to consider the influence of the power supply variation on the delay time variation, when the influence of the power supply variations on the delay variations is smaller than the influence of other factors (such as manufacture variations) on the delay variations, because the influence of the power supply variations on the delay variations is negligible when the power supply variations are sufficiently reduced.

In such a case, delay calculation is desirably performed without using the results of the power supply variation analysis; the use of the results of the power supply variation analysis undesirably increases the calculation time necessary for the delay calculation.

In an aspect of the present invention, an integrated circuit design apparatus is provided with a power supply voltage variation analysis tool calculating variations of power supply voltages of respective instances integrated within a target circuit; a determination module comparing said variations of said power supply voltages with first and second reference levels, said second reference level being smaller than said first reference level; a redesign module adapted to redesign said target circuit when at least one of said variations of said power supply voltages is larger than said first reference level; a delay variation calculation module adapted to correct circuit delay data of said respective instances based on said variations of said power supply voltages of said respective instances; and a static timing analysis tool performing timing verification of said target integrated circuit. In said timing verification, said corrected circuit delay data are used for a specific instance out of said instances within said target circuit, when a variation of a power supply voltage of said specific instance is in a range from said second reference level to said first reference level, and said circuit delay data uncorrected are used for said specific instance, when said variation of said power supply voltage of said specific instance is smaller than said second reference level.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First Embodiment

FIG. 1is a schematic diagram explaining an overall configuration of an integrated circuit design apparatus of a first embodiment of the present invention.

The integrated circuit design apparatus shown inFIG. 1is provided with the placement and routing tool1-1, a delay calculation tool1-2, the power supply variation analysis tool1-4, a determination module1-7, a margin data generator module1-13, a delay variation calculation tool1-9, a jitter analyze tool1-10, a redesign module1-8, a delay variation library generator1-16, a STA (static timing analysis) tool1-15, and a convergence analysis tool1-19.

The placement and routing tool1-1performs placement and routing for a target circuit, and thereby generates layout data indicative of the layout of the target circuit. The delay calculation tool1-2performs delay calculation on the basis of the layout data, and thereby generates SDF (standard delay format) data1-3which include circuit delay data indicative of delay times of respective interconnections and instances within the target circuit.

The power supply variation analysis tool1-4performs power supply variation analysis based on the layout data generated by the placement and routing tool1-1and thereby generates power supply variation report data1-5indicative of the variations in the power supply voltages of the respective instances within the target circuit. The determination module1-7determines the magnitudes of the power supply variations on the basis of the power supply variation report data1-5by comparing the variations in the power supply voltages of the respective instances described in the power supply variation report data1-5with reference levels Va and Vb described in reference level data1-6. It should be noted that the reference level Va is smaller than the reference level Vb.

The redesign module1-8is used to implement redesign of the target circuit, such as optimization of decoupling capacitors, insertion of additional decoupling capacitors, repositioning of the instances.

The delay variation calculation tool1-9is used to calculate delay variations of the respective instances caused by the dynamic noise (that is, the power supply variations), and to provide correction of circuit delay data described within the SDF data1-3in accordance with the calculated delay variations of the respective instances. The delay variation calculation tool1-9uses a delay variation library1-17generated by the delay variation library generator1-16in correcting the circuit delay data within the SDF data1-3. The SDF data1-3after the correction are referred to as the corrected SDF data1-11, hereinafter. The circuit delay data of a specific instance described in the corrected SDF data1-11are used in timing verification for the specific instance when the variation of the power supply voltage of the specific instance is relatively large, more specifically, in the range from the reference level Va to the reference level Vb.

The jitter analyze tool1-10analyzes jitters caused by the dynamic noise (that is, the power supply variations) to generate jitter margin data1-12indicative of margins to be used in timing verification implemented by the STA tool1-15. The magnitudes of the margins described in the jitter margin data1-12depends on the variations in the power supply voltages of the respective instances. The jitter margin data1-12are used for timing verification of specific ones of the instances in which the variations in the power supply voltages are relatively large.

The margin data generator module1-13generates margin data1-14indicative of margins to be used in timing verification implemented by the STA tool1-15for specific ones of the instances in which the variations in the power supply voltages are relatively small, more specifically, below the reference level Vb. The magnitudes of the margins described in the margin data1-14are constant regardless of the magnitude of the variation in the power supply voltage.

The delay variation generator1-16generates the delay variation library1-17and provides the delay variation library1-17for the delay variation calculation tool1-9.

The STA tool1-15performs static timing analysis for the target circuit to thereby generate timing report data1-18. As described later, the STA tool1-15uses the corrected SDF data1-11and the jitter margin data1-12for instances in which the power supply variations calculated by the power supply variation analysis tool1-5are relatively large, and uses the SDF data1-3and the margin data1-14for instances in which the power supply variations are relatively small.

The convergence analysis tool1-19determines on the basis of the timing report data1-18generated by the STA tool1-15whether the operation timing of the target circuit converges.

The SDF data1-3, The power supply variation report data1-5, the reference level data1-6, the corrected SDF data1-11, the jitter margin data1-10, the margin data1-12, the delay variation library1-17, and the timing report data1-18are stored in a storage unit such as a hard disk drive and a memory device provided within the integrated circuit design apparatus.

The integrated circuit design apparatus described above may be implemented with software, hardware, or combinations thereof. In one embodiment, the integrated circuit design apparatus may be implemented as a computer such as an EWS (engineering workstation) onto which software programs are installed.

A description is given next of the circuit design procedure implemented by the integrated circuit design apparatus of the first embodiment, referring toFIG. 2. At the step S-1-1, the placement and routing tool1-1performs the placement and routing for instances, macros and the like within the target circuit to thereby generate the layout data of the target circuit.

At the step S-1-2, the delay calculation tool1-2performs delay calculation to thereby generate the SDF data1-3for the target circuit. The SDF data1-3include circuit delay data of the respective instances of the target circuit.

At the step S-1-3, the power supply variation analysis tool1-4performs power supply variation analysis for the target circuit on the basis of the layout data generated by the placement and routing tool1-1to generate the power supply variation report data1-5. The power supply variation report data1-5are provided for the determination module1-7.

At the step S-1-4, the determination module1-7determines whether the variations in the power supply voltages of the respective instances are larger than the reference level Va indicated by the reference level data1-6. For instances in which the variations in the power supply voltages thereof are not larger than the reference level Va, the margin data generator module13generates the margin data1-14in which the margins are described as constant independently of the magnitude of the variation in the power supply voltage, at the step S-1-12. For instances in which the variations in the power supply voltages thereof are larger than the reference level Va, the procedure goes to the step S-1-5.

The reference level Va may be selected from a plurality of reference levels depending on the function of the target circuit. For examples, the reference level Va may be selected from a reference level V1for the variation in the power supply voltage within the CPU core, a reference level V2for the variation in the power supply voltage of the jitter, a reference level V3for the variation in the power supply voltage within the analogue circuitry. In such case, minimum one out of the reference levels V1to V3are selected as the reference level Va. This is because the reference voltage Va is desirably determined depending on the susceptibility to the power supply variation.

At the step S-1-5, the determination module1-7determines whether the variations in the power supply voltages of the respective instances indicated by the power supply variation report data1-5outputted from the power supply variation analysis tool1-4are larger than the reference level Vb indicated by the reference level data1-6. For instances in which the variations of the power supply voltages are not larger than the reference level Vb, the delay variation calculation tool1-9calculates delay variations caused by the dynamic noise (that is, the variations of the power supply voltages), and corrects the circuit delay data of the SDF data1-3on the basis of the calculated delay variations to generate the corrected SDF data1-11at the step S-1-8. Further, the jitter analyze tool1-10calculates jitter margins to generate the jitter margin data1-12at the step S-1-9for the instances in which the variations of the power supply voltages are not larger than the reference level Vb.

At the step S-1-13, the STA tool1-15implements static timing analysis to provide timing verification for the target circuit, and thereby generates the timing report data1-18indicative of the result of the static timing analysis. In timing verification, the circuit delay data of the SDF data1-3and the margin data1-14are used for the instances in which the variations of the power supply voltages are not larger than the reference level Va, and the corrected circuit delay data of the corrected SDF data1-11and the jitter margin data1-12are used for the instances in which the variations of the power supply voltages are in the range between the reference level Va and Vb. At the step S-1-15, the STA tool1-15outputs the timing report data1-18. At the step S-1-15, the convergence analysis tool1-19determines whether the timing of the target circuit converges successfully. If the timing converges successfully (that is, no timing error is found), the procedure is completed. If the timing does not converge (that is, one or more timing errors are found), the procedure returns to the step S-1-1and the design procedure restarts from the placement and routing. In this case, additional constraint conditions, such as addition of decoupling capacitances, may be provided for the placement and routing tool1-1, so that the timing of the target circuit converges as a result of modifications in the placement and routing.

If at least one of the variations in the power supply voltages of the instances of the target circuit is larger than the reference level Vb, the redesign module1-8performs the redesign of the target circuit. In such case, it would be apparent without timing verification that the target circuit will suffer from a timing error with high possibility. Therefore, at the step S-1-7, the power supply variation report data1-5is fed to the redesign module1-8, and the redesign module1-8offers design modification, such as optimization of the decoupling capacitances. The result of the redesign is fed back to the placement and routing tool1-1. Namely, the timing verification is omitted and the redesign is directly made when the power supply variation is large, thereby saving time for the unnecessary timing analysis.

[Detail of Power Supply Variation Analysis]

A description is given next of details of the power supply variation analysis.FIG. 3is a block diagram showing a detailed configuration of the power supply variation analysis tool1-4in the first embodiment. The power supply variation analysis tool1-4includes a circuit operation pattern generator2-5, a power supply variation analysis engine2-8, and an instance operation determination module2-7.

The circuit operation pattern generator2-5generates a circuit operation pattern used in the power supply variation analysis implemented by the power supply variation analysis engine2-8on the basis of a netlist2-1and initial state data2-2, and then generates circuit operation pattern data2-6indicative of the generated circuit operation pattern. Here, the netlist2-1is circuit connection data indicative of the connectivity of the target circuit. The initial state data2-2is indicative of initial states of respective nodes within the target circuit. Further as described later, operation rate data2-3and/or power consumption data2-4may be additionally fed to the circuit operation pattern generator2-5, wherein the operation rate data2-3are indicative of The operation rate data2-3describes operation rates of the respective instances, and the power consumption data2-4are indicative of the consumption power of the target circuit. It should be noted that the “operation rate” means the number of times for a specific instance to switch the state thereof per clock cycle. For example, the operation rate of a specific instance is 0.5 when the specific instance switches the state thereof once for two clock cycles. The operation rate data2-3and/or the power consumption data2-4may be prepared in advance in consideration of the operation rates and power consumption in actual operations.

The instance operation determination module2-7determines whether all instances operate at least once when the target circuit operates in accordance with the circuit operation pattern described in the circuit operation pattern data2-6generated by the circuit operation pattern generator2-5. The circuit operation pattern generator2-5repeatedly generates the circuit operation pattern in a try-and-error fashion until the circuit operation pattern generator2-5successfully generates the circuit operation pattern so as to operate all the instances at least once. The power supply variation analysis engine2-8performs power supply variation analysis on the basis of the circuit operation pattern data2-6. The power supply variation analysis is also based on RLC network data2-10, instance current waveform data2-11, and instance static capacity data2-12, which are extracted from the layout data generated by the placement and routing tool1-1. The result of the power supply variation analysis is outputted as the power supply variation report data1-5.

The circuit operation pattern generator2-5may include a circuit operation pattern merge module3-3as shown inFIG. 9. The circuit operation pattern merge module3-3merges or combines circuit operation pattern data3-1,3-2, . . . each indicative of a circuit operation pattern to generate the circuit operation pattern data2-6. The power supply variation analysis engine2-8performs the power supply variation analysis on the basis of the circuit operation pattern data2-6.

The circuit operation pattern merge module3-3allows separately-generated circuit operation patterns to be combined into one circuit operation pattern. For example, as shown inFIG. 6, a first circuit operation pattern is generated to allow selected instances to be operated, and then a second circuit operation pattern is generated to allow other selected instances to be operated. In this way, N circuit operation patterns are generated and then the N circuit operation patterns are combined to thereby generate the circuit operation pattern data2-6so as to allow all the instances to operate at least once.

In some cases, it is desirable that the circuit operation pattern data2-6are generated in view of the operation rate data2-3and/or the power consumption data2-4. When the target circuit is provided with a scan path test circuitry including chains of sequential circuits, for example, one possible circuit operation pattern is a pattern which causes all the sequential circuits to operate simultaneously in connection with the operation of the scan paths. In actual operations, however, all the sequential circuits do not operate simultaneously. Therefore, the power supply variation analysis in consideration of the operation in which all the sequential circuits operate simultaneously may lead to estimating an excessively large power supply variation, often resulting in defining excessive margins in design verification of the target circuit. The use of the operation rate data2-3and/or the power consumption data2-4effectively avoids such problem; the operation rate data2-3and/or the power consumption data2-4provides restriction conditions of the maximum number of sequential circuits operating simultaneously, avoiding the generation of a circuit operation pattern in which the operation rate and power consumption are excessively higher than those in actual operations. This effectively prevents the power supply variation analysis and timing verification based on excessive margins.FIG. 7shows an example of the circuit operation pattern data2-6in which the number of sequential circuits operating simultaneously is restricted on the basis of the operation rate data2-3. A circuit operation pattern in which all of the sequential circuits operate simultaneously may be possible in connection with the operation of the scan path test circuit; however, the assumption that all the sequential circuits operate simultaneously would lead to estimating an excessively large power supply variation, resulting in excessive margins. InFIG. 7, such problem is avoided. Namely, circuit operation patterns in which the number of sequential circuits operating simultaneously is restricted are generated. The generated circuit operation patterns are combined later into the circuit operation pattern data2-6which allows all the sequential circuits to operate at least once. InFIG. 7, hatchings indicate sequential circuits actually selected to operate in the respective circuit operation patterns, and the symbols “U” indicates sequential circuits which are selectable (but not actually selected) as sequential circuits which operate in the respective circuit operation patterns. White boxes indicate sequential circuits selected not to operate the respective circuit operation patterns.

In an alternative embodiment, as shown inFIG. 8, the power consumption data2-4may be used in place of the operation rate data2-3in order to provide restriction conditions of the maximum number of sequential circuits operating simultaneously. The circuit operation pattern data2-6are generated by combining circuit operation pattern data3-1to3-N each indicative of one circuit operation pattern.

A description is next given in detail of a circuit operation pattern generated by combining a plurality of circuit operation patterns thereinto, referring toFIG. 11. InFIG. 11, a resultant circuit operation pattern is generated by combining circuit operation patterns #1to #4, wherein the circuit operation pattern #1allows instances #1to4to operate, the circuit operation pattern #2allows instances #5to #8to operate, and the circuit operation pattern #3allows instances #9to #12to operate. In the resultant circuit operation pattern, only the instances #1to #4operate in the first cycle; the instances #5to #12do not operate in the first cycle. Likewise, only the instances #5to #8operate in the second cycle, and only the instances9to12operate in the third cycle. As thus described, the maximum number of instances operating simultaneously is restricted to or below a predetermined number based on the operation rate data2-3and/or the power consumption data2-4. In the example shown inFIG. 11, the maximum number of instances allowed to operate simultaneously is four. As shown inFIG. 12, a circuit operation pattern used in power supply variation analysis which covers a long analysis time may be generated by repeatedly combining a plurality of circuit operation patterns.

In this way, the circuit operation pattern merge module3-3outputs one circuit operation pattern data thus combined and the power supply variation analysis tool3-5can analyze the power supply voltage change based on the combined circuit operation pattern data.

A description is given next of the operation of the power supply variation analysis tool1-2referring toFIG. 4, which shows an operation flowchart of the power supply variation analysis tool1-2.

At the step S-2-1, the netlist2-1and the initial state data2-2are provided for the power supply variation analysis tool1-2. In addition, the operation rate data2-3and/or the power consumption data2-4are provided for the power supply variation analysis tool1-2.

At the step S-2-2, the circuit operation pattern generator2-5determines the maximum number of instances allowed to operate simultaneously for each clock cycle on the basis of the operation rates indicated by the operation rate data2-3and/or the power consumption indicated by the power consumption data2-4, and generates a circuit operation pattern based on the determined maximum number of the instances allowed to operate simultaneously. It should be noted that the circuit operation pattern indicates which instance operates in which clock cycle.

At the step S-2-3, the circuit operation pattern generator2-5determines whether the circuit operation pattern generated at the step S-2-2is generated so that all the instances operate at least once. When the circuit operation pattern generated at the step S-2-2do not allow all the instances to operate at least once, the circuit operation pattern generator2-5generate a supplemental circuit operation pattern and merge the newly-generated circuit operation pattern into the previously-generated circuit operation pattern at step S-2-4. It should be noted that the circuit operation pattern generator2-5generates the supplemental circuit operation pattern at the step S-2-4so that the supplemental circuit operation pattern allows instances which do not operate in accordance with the previously-generated circuit operation pattern to operate. The steps S-2-3and S-2-4are repeated until the circuit operation pattern generator2-5successfully generates a circuit operation pattern in which all the instances are allowed to operate at least once. When a circuit operation pattern which allows all the instances to operate at least once is successfully generated, the circuit operation pattern generator2-5completes the circuit operation pattern generation.

At the step S-2-5, the generated circuit operation pattern is fed to the power supply variation analysis engine2-8. At the step S-2-7, the RLC network data2-10, the instance current waveform data2-11, and the instance static capacity data2-12are fed to the power supply variation analysis engine2-8. At the step S-2-6, the power supply variation analysis engine2-8performs power supply variation analysis and outputs the power supply variation report data1-5.

InFIG. 4, the determination is made at the step S-2-3with respect to one circuit operation pattern generated by combining a newly-generated circuit operation pattern to a previously-generated circuit operation pattern at step the S-2-4. Alternatively, a plurality of circuit operation patterns are generated so that the generated circuit operation patterns allows all the instances to operate at least one in total, and then the generated circuit operation patterns are combined to generate a resultant circuit operation pattern.FIG. 10shows a flowchart related to this alternative.

[Generation of Delay Variation Library]

A description is given next of generation of the delay variation library1-15by the delay variation library generator1-16shown inFIG. 1.

FIG. 13is a block diagram showing the configuration of the delay variation library generator1-16. Input signal slew rate data5-1, output load capacitance data5-2, power supply voltage data5-3, and pin state data5-4stored in the storage unit of the integrated circuit design apparatus1are fed to the delay variation library generator1-16. The delay variation library generator1-16generates the delay variation library1-17from the input signal slew rate data5-1, the output load capacitance data5-2, the power supply voltage data5-3, and the pin state data5-4. One feature of the delay variation library generation in the first embodiment is that the delay variation library1-17is generated in view of states of pins of the respective instances.

FIG. 14shows the operation of the delay variation library generator1-16. At the step S-5-1, input signal slew rate data5-1, which are indicative of slew rates of input signals, are fed to the delay variation library generator1-16. At the step S-5-2, the output load capacitance data5-2, which are indicative of output load capacitances, are fed to the delay variation library generator1-16. At the step S-5-3, the power supply voltage data5-3, which are indicative of variations in the power supply voltage, are fed to the delay variation library generator1-16. At the step S-5-4, the pin status data5-4, which are indicative of the states of pins of the respective instances, are fed to the delay variation library generator1-16. At the step S-5-5, the delay variation library generator1-16calculates the delay variations by circuit simulation for the respective kinds of instances, with the input signal slew rates, the output load capacitances, the power supply voltages, and the states of pins varied over desired ranges. The result of the calculation is archived in the delay variation library1-17.

A detailed description is given of the generation of the delay variation library1-17referring toFIG. 15.FIG. 15shows the delay variation data described in the delay variation library1-17for a combinational circuit having three input pins A, B, and C and an output pin Y. The input signals are fed to the pins A, B, and C and the output signal is outputted from the output pin Y. The generation of the delay variation data for a certain kind of instance (target instance) involves steps (1-1) to (1-3) as follows:

The delay variation library generator1-16generates input/output patterns for all the timing arcs involved in signal transition on the basis of the input signal slew rate data5-1, the output load capacitance data5-2, the power supply voltage data5-3, and the pin state data5-4. It should be noted that the timing arc is the timing path from any input to any output.

The delay variation library generator1-16calculates variations in the delay times of the target instance caused by the variations in the power supply voltage and the ground voltage with the power supply and ground voltages varied over desired voltage ranges for respective allowed states of the input pins. InFIG. 15, the variations in the delay times are indicated by the “delay11”, “delay12”, . . . , “delay21”, “delay21”, . . . , “delay31”, and “delay32”,

The delay variation library generator1-16defines a delay variation function which represents the variation in the delay time against the variations in the power supply and ground voltages for each allowed input pin state. The delay variation functions are defined by using the least square method. In this embodiment, the delay variation functions are expressed by delay variation factors DF which are the ratio of the variation in the delay time to the variations in the power supply and ground voltages.

The delay variation library generator1-16implements the steps (1-1) to (1-3) for all the possible states of the input pins with the differences between the power supply and ground voltages varied, to thereby complete the delay change delay variation library1-17shown inFIG. 15.

The delay variation calculation tool1-9calculates the variations in the delay times of the respective instances within the target circuit by assigning the variation in the power supply voltage calculated by the power supply variation analysis tool1-2to the delay variation function described in the delay variation library1-15. The delay variation calculation tool1-9then corrects the SDF data1-3in accordance with the calculated variations in the delay times of the respective instances to generate the corrected SDF data1-11.

Second Embodiment

In a second embodiment, the integrated circuit design apparatus is configured to implement delay variation calculation on the basis of the power supply current Ivdd and the ground current Ignd in addition to the variation in the power supply voltage.

FIG. 16is a block diagram showing the main part of the integrated circuit design apparatus of the second embodiment. The integrated circuit design apparatus of the second embodiment is identical in the configuration and operation to that of the first embodiment shown inFIGS. 1 and 3except for including a power supply variation analysis tool6-2, a power supply current data merge module6-7, a power supply voltage variation data merge module6-8, and a delay variation calculation tool6-11in place of the power supply variation analysis tool1-4, the delay variation calculation tool1-9. InFIG. 16, components of the integrated circuit design apparatus which are identical in the configuration and operation to those shown inFIGS. 1 and 3may be not shown for simplicity, and descriptions thereof are not given in the following.

In the integrated circuit design apparatus shown inFIG. 16, the power supply variation analysis tool6-2performs power supply voltage variation analysis on the basis of the RLC network data2-10, instance current waveform data2-11, instance static capacitance data2-12, and the circuit operation pattern data2-6, which are extracted from the layout data generated by the placement and routing tool1-1, to generate power supply voltage variation report data6-6and ground voltage variation report data6-5. The power supply voltage variation report data6-6are indicative of the variations in the power supply voltages of the respective instances, and the ground voltage variation report data6-5are indicative of the variations in the ground voltages of the respective instances. Further, the power supply variation analysis tool6-2also generates power supply current report data6-4and ground current report data6-3. The power supply current report data6-4are indicative of the variations in the power supply currents Ivdd of the respective instances, and the ground current report data6-3are indicative of the variations in the ground currents Ignd of the respective instances. The power supply current data merge module6-7merges the ground current report data6-3and the power supply current report data6-4to generate (Ivdd+Ignd) current report data6-9which are indicative of the variations in the sum of the power supply currents Ivdd and the ground currents Ignd of the respective instances for each unit time period (simply referred to as, Ivdd+Ignd). The power supply voltage variation data merge module6-8merges the power supply voltage variation report data6-6and the ground voltage variation report data6-5to generate (VDD−GND) variation report data6-10which are indicative of the variations in the differences between the power supply voltages and the ground voltages within the respective instances for each unit time period (simply referred to as VDD−GND, hereinafter). The delay variation calculation tool6-11performs delay variation calculation on the basis of the (Ivdd+Ignd) current report data6-9, the (VDD−GND) variation report data6-10, and the delay variation library1-17, and corrects the SDF data1-3in accordance with the result of the delay variation calculation to generate the corrected SDF data1-11.

A description is given next of the procedure of the delay variation calculation in the second embodiment, referring to the flowchart ofFIG. 17. At the step S-6-1, the layout data generated by the placement and routing tool1-1is fed to the power supply variation analysis tool6-2. At the step S-6-2, the power supply variation analysis tool6-2analyzes the power supply and ground currents for the target circuit operation pattern, and generates the power supply current report data6-4and the ground current report data6-3. At the step S-6-3, the power supply current data merge module6-7merges the ground current report data6-3and the power supply current report data6-4to generate the (Ivdd+Ignd) current report data6-9which are indicative of the variations in Ivdd+Ignd (that is, the sums of the power supply currents Ivdd and the ground currents Ignd of the respective instances), and feeds the (Ivdd+Ignd) current report data6-9to the delay variation calculation tool6-11. At the step S-6-5, the power supply variation analysis tool6-2analyzes the variations in the power supply voltages and the ground voltages of the respective instances to generate the power supply voltage variation report data6-6and the ground voltage variation report data6-5. At the step S-6-6, the power supply voltage variation data merge module6-8merges the power supply voltage variation report data6-6and the ground voltage variation report data6-5to generate the (VDD−GND) variation report data6-10which are indicative of the variations in VDD−GND (that is, the variations in the differences between the power supply voltages and the ground voltages of the respective instances). The (VDD−GND) variation report data6-10are fed to the delay variation calculation tool6-11. At the step S-6-7, the delay variation library1-17is fed to the delay variation calculation tool6-11.

A procedure of the delay variation calculation depending on the variations of the power supply voltages and the power supply currents will be described in detail.FIGS. 18 and 19are graphs explaining the delay variation calculation method in this embodiment.

At steps (2-1) to (2-3) described below, the delay variation calculation tool6-11first calculates a calculation start time and end time used in the delay variation calculation on the basis of the currents through the respective instances,

Step (2-1): Acquisition of Output Load Capacitance

The delay variation calculation tool6-11calculates the output load capacitance Cout of each instance from RLC network data2-20of the power supply and signal lines extracted from the layout data generated by the placement and routing tool1-1. Alternatively, the delay variation calculation tool1-9may calculate the output load capacitance Cout of each instance from the current level of the current through each instance. Details of the procedure of calculating the output load capacitance Cout from the current through each instance will be described later. This step is a pre-process performed by the power supply variation analysis tool6-2.

Step (2-2): Determination of Calculation Start Time T0

Referring to the graph of the current waveform shown inFIG. 18, the start time T0is determined as being the time at which the sum of the power supply and ground currents (that is, Ivdd+Ignd) described in (Ivdd+Ignd) current report data6-9exceeds a predetermined reference current Istart.

Step (2-3): Determination of Calculation End Time T1

A process of calculating the end time T1differs depending on how the output load capacitance Cout is specified. There are two possible methods to specify the output load capacitance Cout of each instance: (1) a first method is to obtain the output load capacity Cout from the RLC network data2-10of the power supply and signal lines, and (2) a second method is to obtain the load capacity Cout from the current through the instance. The end time T1is calculated in different ways depending on the selection of the method of specifying the output load capacitance Cout as described below.

(2-3-1): Case when the Output Load Capacity Cout is Obtained from the RLC Network Data2-10of the Power Supply and Signal Lines

In this case, the end time T1is calculated based on the integration of the power supply current Ivdd or the ground current Ignd, in the time domain. The output voltage Vout of the instance is expressed as follows:

Vout=∫T⁢⁢0T⁢⁢1⁢i⁡(t)⁢ⅆtCout,
where i(t)=Ivdd, or i(t)=Ignd. As shown inFIG. 18, the end time T1is defined as the time when the output voltage Vout is increased up to a threshold voltage Vth. It should be noted that the threshold voltage Vth is a value externally specified in advance. That is, the end time T1is calculated so that it holds:

Vout=∫T⁢⁢0T⁢⁢1⁢i⁡(t)⁢ⅆtCout=Vth,(1)
(2-3-2) Case when the Output Load Capacitance Cout is Obtained from the Level of the Current Through the Instance

When the output load capacitance Cout of the target instance is not described in the RLC network data2-10, the end time T1is calculated by additionally using the following equation:

Vdd=∫T⁢⁢0∞⁢i⁡(t)⁢ⅆtCout,(2)
where Vdd is the ideal power supply voltage for the case that the power supply voltage does not experience variations. By normalizing the equation (1) with the equation (2), the following equation (3) is obtained:

The end time T1is defined to satisfy the equation (3). The use of the equation (3) enables to calculate the end time T1without the information on the output load capacitance Cout.

At steps (2-4) and (2-5) described below, delay variations are calculated on the basis of the power supply voltage variations and the power supply currents.

Step (2-4): Normalization of Current Through Instance

At the step (2-4), the current through the instance is normalized by using the following equation:

inorm⁡(t)=i⁡(t)∫T⁢⁢0T⁢⁢1⁢i⁡(t)⁢ⅆt=i⁡(t)Qtotal,(4)
where i(t)=Ivdd or i(t)=Ignd, and inorm(t) is the normalized current. It should be noted that the power supply currents Ivdd of the respective instances are described in the power supply current report data6-3and the ground currents Ignd of the respective instances are described in the ground current report data6-4. It should be also noted that the start time T0and the end time T1are obtained at the step (2-3).
(2-5) Calculation of Delay Variations

The delay variations are calculated from the above-described normalized current inorm(t) and the power supply voltage variations defined as ΔVDD(t)−ΔGND(t), which is described in the (VDD−GND) variation report data6-10, where
ΔVDD(t)=VDDideal−VDD(t), and
ΔGND(t)=GNDideal−GND(t)

Here, VDDidealand GNDidealare the power supply and ground voltages, respectively, for the case in which the target circuit does not experience power supply variations. The power supply and ground voltages VDD(t) and GND(t) are described in the power supply voltage variation report data6-5and the ground voltage variation report data6-6, respectively.

In detail, the delay variation Δdelay of a target instance is calculated as the integration of the product of the normalized current inorm(t) and ΔVDD(t)−ΔGND(t) with respect to the time period from the start time T0to the end time T1, further multiplied by the delay variation factor DF described in the delay variation library1-17. In other words, it holds:

Δ⁢⁢delay=∫T⁢⁢0T⁢⁢1⁢DF·(Δ⁢⁢VDD⁡(t)-Δ⁢⁢GND⁡(t))·inorm⁡(t)⁢ⅆt,(5)
The delay variation Δdelay is calculated from the equation (5).

Third Embodiment

In the second embodiment, the delay variation is calculated under the assumption that the power supply current is free from the influence of the power supply voltage variations. However, the power supply current through an actual circuit is often varied by the influence of the power supply voltage variation and the power supply current variation is not negligible in the delay variation calculation in some case. In a third embodiment, the delay variation calculation is performed with higher accuracy in view of the power supply current variation depending on the power supply voltage variation.

FIG. 20is a block diagram of an integrated circuit design apparatus according to the third embodiment. InFIG. 20, the same numerals denote the same elements shown inFIGS. 1,3, and16. InFIG. 20, components of the integrated circuit design apparatus which are identical in the configuration and operation to those shown inFIGS. 1,3and16may not be shown for simplicity, and descriptions thereof are not given in the following. Power supply current data7-3collectively denote the power supply current report data6-4the ground current report data6-3and, and power supply voltage data7-4collectively denote the power supply voltage variation report data6-6and the ground voltage variation report data6-5. It should be noted that the power supply current data7-3describes the power supply and ground currents for the case when the target circuit does not experience the power supply variations.

The integrated circuit design apparatus of the third embodiment additionally includes a correction tool7-5differently from those of the first and second embodiments. The correction tool7-5corrects the power supply and ground currents described in the power supply current data7-3on the basis of the variation of the power supply and ground voltages described in the power supply voltage variation data7-4, and thereby generates corrected power supply current data7-7indicative of the corrected power supply currents Ivddcrctand ground currents Igndcrctof the respective instances.

Further, the correction tool7-5corrects the power supply and ground voltages described in the power supply voltage variation data7-4on the basis of the corrected power supply current data7-7in view of the correction of the power supply and ground currents. The correction tool7-5generates corrected power supply voltage variation data7-6indicative of the corrected power supply voltages VDDcrctand the corrected ground voltages GNDcrctof the respective instances. The power supply voltage variation data merge module6-8generates (VDD−GND) variation report data7-10from the corrected power supply voltage variation data7-6, the generated (VDD−GND) variation report data7-10being indicative of the difference between the corrected power supply voltage VDDcrctand the corrected ground voltage GNDcrctof each instance at each timing. Correspondingly, the power supply current data merge tool6-7generates (Ivdd+Ignd) current report data7-11from the corrected power supply current data7-7, the generated (Ivdd+Ignd) current report data7-11being indicative of the sum of the corrected power supply current Ivddcrctand the corrected ground current Igndcrct.

FIG. 21is a flowchart showing the generation procedure of the (VDD−GND) variation report data7-10and the (Ivdd+Ignd) current report data7-11in the third embodiment. At the step S-7-1, the RLC network data2-10, the instance current waveform data2-11, the instance static capacity data2-12, which are extracted from layout data generated by the placement and routing tool1-1as well as the circuit operation pattern data2-6are fed to the power supply voltage variation analysis tool6-2. At the step S-7-2, the power supply voltage variation analysis tool6-2performs power supply variation analysis to thereby generate the power supply voltage variation data7-4. The power supply voltage variation analysis tool6-2also calculates the waveforms of the power supply and ground currents to generate the power supply current data7-3. At the step S-7-3, the power supply voltage variation analysis tool6-2feeds the power supply voltage variation data7-4and the power supply current data7-3to the correction tool7-5. At the step S-7-4, the correction tool7-5corrects the power supply and ground currents described in the power supply current data7-3on the basis of the variations in the power supply voltages of the respective instances described in the power supply voltage variation data7-4to generate the corrected power supply current data7-7in view of the power supply voltage variations. At the step S-7-5, the correction tool7-5corrects the power supply voltage variation data7-4based on the corrected power supply current data7-7to generate the corrected power supply voltage variation data7-6in view of the variations in the power supply and ground currents. At the step S-7-6, the power supply voltage variation data merge module6-8calculates the difference between the corrected power supply voltage VDDcrctand the corrected ground voltage GNDcrctdescribed in the corrected power supply voltage variation data7-6to generate the (VDD−GND) variation report data7-10. The (VDD−GND) variation report data7-10are fed to the delay variation calculation tool6-11. At the step S-7-7, the correction tool7-5calculates the sum of the corrected power supply current Ivddcrctand the ground current Igndcrctdescribed in the corrected power supply current data7-7to generates the (Ivdd+Ignd) current data7-11.

A description is given next of the procedure for the correction tool7-5to correct the power supply current Ivdd and the ground current Ignd of each instance in view of the power supply voltage variation. The correction of the power supply and ground currents Ivdd and Ignd is based on the power supply voltage variation ΔV(t) defined as follows:
ΔV(t)=ΔVDD(t)−ΔGND(t),
where
ΔVDD(t)=VDDideal−VDD(t), and
ΔGND(t)=GNDideal−GND(t).
It should be noted that VDD(t) is the power supply voltage described in the power supply voltage variation data7-4and GND(t) is the ground voltage described in the power supply voltage variation data7-4. The corrected power supply current Ivdd(t)′ and corrected ground current Ignd(t)′ are calculated as follows:

A description is then given of the procedure for the correction tool7-5to further correct the power supply voltage VDD(t) and the ground voltage GND(t) in view of the correction of power supply and ground currents.

The corrected power supply voltage VDD(t)′ and the corrected ground voltage GND(t)′ are calculated by the equations (7a) and (7b):

VDD⁡(t)′=β·Ivdd⁡(t)′Ivdd⁡(t)·VDD⁡(t),(7⁢a)GND⁡(t)′=β·Ignd⁡(t)′Ignd⁡(t)·GND⁡(t),(7⁢b)
where β is a conversion coefficient specified externally. In the delay variation calculation of this embodiment, ΔVDD(t) and ΔGND(t) in the equation (5) are calculated by using the corrected power supply voltage VDD(t)′ and the corrected ground voltage GND(t)′ in place of the power supply voltage VDD(t) and the ground voltage GND(t).

Fourth Embodiment

In the third embodiment, the power supply and ground currents are corrected based on the calculation result of the variations in the power supply and ground voltages, and the power supply and ground voltages are then corrected based on the correction of the power supply and ground currents.

It is preferable, however, that corrections of the power supply and ground currents and the power supply and ground voltages are repeated recursively until the corrected voltages and currents converges in predetermined ranges in order to improve the accuracy of the delay variation calculation.

In a fourth embodiment, such corrections of the voltages and currents are repeated to improve the accuracy of the delay variation calculation.

FIG. 22is a block diagram showing the configuration of a main portion of the integrated circuit design apparatus of the fourth embodiment. InFIG. 22, the same numerals denote the same elements shown inFIG. 16. InFIG. 22, components of the integrated circuit design apparatus which are identical in the configuration and operation to those shown inFIGS. 1,3,16, and22may be not shown for simplicity, and descriptions thereof are not given in the following.

In the fourth embodiment, as shown inFIG. 22, a current correction module8-4and a voltage correction module8-6are used in place of the correction tool7-5of the third embodiment. The current correction module8-4corrects the power supply currents Ivdd(t) and the ground currents Ignd(t) of the respective instances described in the power supply current data7-3based on the power supply voltage variations ΔV(t) of the respective instances in the same way as the third embodiment, and thereby generates corrected power supply current data8-5indicative of corrected power supply currents Ivdd(t)′ and the corrected ground currents Ignd(t)′ of the respective instances. The voltage correction module8-6corrects the power supply voltages VDD(t) and the ground voltages GND(t) of the respective instances described in the power supply voltage variation data7-5based on the corrected power supply currents Ivdd(t)′ and the ground currents Ignd(t)′ of the respective instances in the same way as the third embodiment, and thereby generates corrected power supply voltage variation data8-7indicative of corrected power supply voltages VDD(t)′ and the ground voltages GND(t)′ of the respective instances.

Additionally, the integrated circuit design apparatus of the fourth embodiment includes a current variation determination module8-9which make comparison of the difference of the corrected and uncorrected power supply currents with a current difference reference ΔIREFand comparison of the difference of the corrected and uncorrected power supply currents with the current difference reference ΔIREFfor each instance. It should be noted that, inFIGS. 22 and 23, the uncorrected power supply and ground currents Ivdd(t) and Ignd(t) are collectively referred to as I(t) and the corrected power supply and ground currents Ivdd(t)′ and Ignd(t)′ are collectively referred to as I(t)′. The current variation determination module8-9is responsive of the results of the comparisons for outputting corrected power supply current data8-1and power supply voltage variation data8-11or repeating the corrections of the power supply and ground currents Ivdd(t) and Ignd(t) and the power supply and ground voltages VDD(t) and GND(t), wherein the corrected power supply current data8-1describe the corrected power supply and ground currents Ivdd(t)′ and Ignd(t)′ of the respective instances and the power supply voltage variation data8-11describe the power supply voltage variations ΔV(t)′ of the respective instances, wherein ΔV(t)′ is defined as follows:
ΔV(t)′=ΔVDD(t)′−ΔGND(t)′,
ΔVDD(t)′=VDDideal−VDD(t)′, and
ΔGND(t)′=GNDideal−GND(t)′.
The delay variation Δdelay of a specific instance is calculated from the equations (4) and (5) with ΔV(t)′ used in place of ΔVDD(t)−ΔGND(t) in the equation (5) and with Ivdd(t)′ or Ignd(t)′ used in place of i(t) in the equation (4)

FIG. 23shows a procedure of corrections of the power supply and ground currents Ivdd(t) and Ignd(t) and the power supply and ground voltages VDD(t) and GND(t) for a specific instance.

At step S-8-6, the current difference reference ΔIREFis prepared in advance in the storage unit of the integrated circuit design apparatus. At step S-8-1, similarly to the second and third embodiments, the power supply variation analysis tool6-2calculates the variations in the power supply and ground voltages VDD(t) and GND(t) and the power supply and ground currents Ivdd(t) and Ignd(t). At the step S-8-2, similarly to the third embodiment, the corrected power supply and ground currents Ivdd(t)′ and Ignd(t)′ are calculated on the basis of the variation ΔV(t) in the power supply and ground voltages VDD(t) and GND(t).

At step S-8-3, similarly to the third embodiment, the corrected power supply and ground voltages VDD(t)′ and GND(t)′ are calculated. At the step S-8-4, the difference between the corrected and original power supply currents Ivdd(t)′ and Ivdd(t) and the difference between the corrected and original ground current Ignd(t)′ and Ignd(t) are calculated, and then compared with the current difference reference ΔIREFat the step S-8-5. When any of |Ivdd(t)′−Ivdd(t)| and |Ignd(t)′−Ignd(t)| exceeds the current difference reference ΔIREF, the procedure returns to step S-8-2, replacing Ivdd(t) with Ivdd(t)′, Ignd(t) with Ignd(t)′, VDD(t) with VDD(t)′, and GND(t) with GND(t)′.

When both of |Ivdd(t)′−Ivdd(t)| and |Ignd(t)′−Ignd(t)| are smaller than the current difference reference ΔIREF, at the step S-8-7, the corrected power supply current data8-1and the power supply voltage variation data8-11are outputted to complete the power supply voltage analysis, wherein the corrected power supply current data8-1describe the corrected power supply and ground currents Ivdd(t)′ and Ignd(t)′ of the respective instances and the power supply voltage variation data8-11describe the power supply voltage variations ΔV(t)′ of the respective instances.

In the above-described procedure, the determination at the step S-8-5are based on the difference between the corrected and original power supply currents Ivdd(t)′ and Ivdd(t), and the difference between the corrected and original ground currents Ignd(t)′ and Ignd(t). Alternatively, the determination at the step S-8-5may be based on the difference between corrected and original power supply voltage variation |ΔV(t)′−ΔV(t)| in place of or in addition to |Ivdd(t)′−Ivdd(t)| and |Ignd(t)′−Ignd(t)|. When the determination at the step S-8-5is based on the difference between corrected and original power supply voltage variation |ΔV(t)′−ΔV(t)| in addition to |Ivdd(t)′−Ivdd(t)| and |Ignd(t)′−Ignd(t)|, the corrections at the steps S-8-2and S-8-3are repeated as long as any of |ΔV(t)′−ΔV(t)| |Ivdd(t)′−Ivdd(t)|, and |Ignd(t)′−Ignd(t)| exceeds the associated voltage or current difference reference, and the power supply variation analysis is completed when all of |ΔV(t)′−ΔV(t)|, |Ivdd(t)′−Ivdd(t)| and |Ignd(t)′−Ignd(t)| are reduced below the associated voltage or current difference reference.

It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope of the invention.