Electrical current measurement system

A test system for measuring electrical current consumption of a device under test (DUT) includes a capacitor with power and ground terminals; a voltage regulator with input and output terminals; first and second switching elements; and a controller. The voltage regulator generates a DUT operating voltage based on its input voltage. The first switching element is arranged between a direct current (DC) voltage source and the regulator input, and the second switching element is arranged between the DC voltage source and the capacitor. The controller operates the switching elements to charge the capacitor, and to configure the test system for measuring operating current of the DUT using the capacitor as the power source.

TECHNICAL FIELD

Embodiments of the subject matter described herein relate generally to a test system for measuring electrical current consumed by a device under test, and to a current-isolated voltage regulator suitable for use in the test system.

BACKGROUND

Electronic devices, systems, and components are routinely subjected to electrical tests during manufacturing and/or in an ongoing manner after deployment. For example, an electronic device can be tested to measure the amount of electrical current it consumes during different operating modes. An unusually low or high measured current can be an indicator of a fault, error, or manufacturing defect.

A low power consumption electronic device, such as a battery powered medical device, may utilize a switch-mode power supply (SMPS) that provides an as-needed switching scheme at low load currents that occur during the device's standby mode. In such a device, the switching during standby mode occurs on an as-needed basis. Accordingly, the switching period is often increased to a point where input filter capacitors become ineffective at smoothing the current. This results in a discontinuous input current that typically resembles a pulse train having high dynamic range. In this regard, the non-switching currents between “wake up” current pulses may be four to five orders of magnitude less than the switching pulses. As the switching period increases for a given pulse width (i.e., the duty cycle decreases), the overall current measurement accuracy becomes increasingly affected by the non-switching current. The combination of these factors adversely impact the effectiveness and accuracy of most readily available electrical current measurement systems, which are primarily designed to measure continuous current and/or current having a low dynamic range. As a result, measurement accuracy of discontinuous electrical current with high dynamic range suffers when such devices are tested with conventional (and economically feasible) current measurement equipment.

A test system that measures electrical current may include a voltage regulator to provide operating power to the device under test. A conventional low-dropout or linear voltage regulator utilizes the regulator input voltage to source certain components, such as an internal voltage reference and an error amplifier. Consequently, the input current of this type of voltage regulator will always be higher than the output current. Although this type of voltage regulator is appropriate in some applications, it may not be suitable in certain applications where it is desirable to have the output current match the input current.

BRIEF SUMMARY

Disclosed herein is a test system and related current measurement technique that can accurately and effectively measure the electrical current consumed by a device under test, where the current exhibits discontinuous and high dynamic range characteristics. Also disclosed herein are linear voltage regulators that operate in a current-isolated manner such that the regulator output current closely matches the regulator input current. Other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.

A test system for measuring electrical current consumption of a device under test (DUT) is disclosed herein. The test system includes: a power capacitor with a power terminal and a ground terminal, and configured to provide capacitor voltage at the power terminal; a voltage regulator having a regulator input terminal and a regulator output terminal, and configured to generate a DUT operating voltage at the regulator output terminal based on an input voltage at the regulator input terminal; a switching circuit to regulate electrical connections between a direct current (DC) voltage source, the power capacitor, and the voltage regulator; and a controller coupled to the power capacitor, the voltage regulator, and the switching circuit. The controller is configurable to: control the switching circuit to place the test system into a charging state to charge the power capacitor with the DC voltage source; after the power capacitor has reached a charged voltage, control the switching circuit to place the test system into a measurement state such that the power capacitor provides the capacitor voltage to the voltage regulator; and after the power capacitor has reached a discharged voltage in response to loading, calculate electrical current provided by the power capacitor in a time period recorded during operation of the test system in the measurement state. The electrical current is calculated based on a sampled value of the charged voltage, a sampled value of the discharged voltage, and discharge characteristics of the power capacitor.

In accordance with certain embodiments, a test system for measuring electrical current consumption of a DUT includes: a power capacitor with a power terminal and a ground terminal, and configured to provide capacitor voltage at the power terminal; a voltage regulator with a regulator input terminal and a regulator output terminal, and configured to generate a DUT operating voltage at the regulator output terminal based on an input voltage at the regulator input terminal; a first switching element between a DC voltage source and the regulator input terminal; a second switching element between the DC voltage source and the power terminal of the power capacitor; and a controller coupled to the power capacitor, the voltage regulator, the first switching element, and the second switching element. The controller is configurable to: close the first and second switching elements to charge the power capacitor with the DC voltage source; after the power capacitor has reached a charged voltage, open the first and second switching elements such that the power capacitor provides the capacitor voltage to the voltage regulator; record a measurement start time associated with opening of the first switching element when the second switching element is open; after the power capacitor has reached a discharged voltage in response to loading, close the first switching element; record a measurement end time associated with closing of the first switching element when the second switching element is open; and calculate electrical current provided by the power capacitor between the measurement start time and the measurement end time, based on a sampled value of the charged voltage of the power capacitor, a sampled value of the discharged voltage of the power capacitor, and discharge characteristics of the power capacitor.

Also disclosed herein is an automated method of measuring electrical current of a DUT with a test system having a power capacitor, a voltage regulator to generate a DUT operating voltage for the DUT, a switching circuit to regulate electrical connections between a direct current (DC) voltage source, the power capacitor, and the voltage regulator, and a processor-based controller. The method involves: automatically controlling the switching circuit with the controller to place the test system into a charging state, such that the DC voltage source charges the power capacitor; after the power capacitor has reached a charged voltage, automatically controlling the switching circuit with the controller to transition the test system into a measurement state, such that the power capacitor provides capacitor voltage to the voltage regulator while the test system is in the measurement state, wherein the DUT is coupled to a regulator output terminal of the voltage regulator while the test system is in the measurement state; recording, with the controller, a measurement start time; after the power capacitor has reached a discharged voltage in response to operation of the DUT, automatically controlling the switching circuit with the controller to transition the test system into a post-measurement state; recording, with the controller, a measurement end time; calculating electrical current consumed by the DUT between the measurement start time and the measurement end time, based on a sampled value of the charged voltage, a sampled value of the discharged voltage, and discharge characteristics of the power capacitor; and generating the calculated electrical current as an output of the test system.

A linear voltage regulator is also disclosed herein. The linear voltage regulator includes: an input voltage terminal for a regulator input voltage; an output voltage terminal for a regulator output voltage; a series pass field-effect transistor coupled between the input voltage terminal and the output voltage terminal; a voltage reference source to provide a reference voltage for the linear voltage regulator, the voltage reference source powered by an independent voltage supply that is isolated from the input voltage terminal; a buffer amplifier with a buffer output, a positive buffer input coupled to the output voltage terminal, and a negative buffer input coupled to the buffer output, the buffer amplifier powered by the independent voltage supply; a feedback divider network coupled between the buffer output and a ground terminal, the feedback divider network providing a scaled output voltage at a divider output; and an error amplifier with an error output coupled to the transistor, a positive error input coupled to the divider output to receive the scaled output voltage, and a negative error input coupled to the voltage reference source to receive the reference voltage, the error amplifier powered by the independent voltage supply. Output of the error amplifier is based on a difference between the reference voltage and the scaled output voltage. The output of the error amplifier controls impedance of the transistor to adjust a regulator output voltage at the output voltage terminal.

Another embodiment of a linear voltage regulator is also disclosed. The linear voltage regulator includes: an input voltage terminal for a regulator input voltage; an output voltage terminal for a regulator output voltage; a series pass field-effect transistor coupled between the input voltage terminal and the output voltage terminal; a buffer amplifier with a buffer output, a positive buffer input coupled to the output voltage terminal, and a negative buffer input coupled to the buffer output, the buffer amplifier powered by an independent voltage supply that is isolated from the input voltage terminal; a feedback divider network coupled between the buffer output and a ground terminal, the feedback divider network providing a scaled output voltage at a divider output; an analog-to-digital converter (ADC) with an analog voltage input coupled to the divider output to receive the scaled output voltage, and having a first digital output interface to provide a digital representation of the scaled output voltage, the ADC powered by the independent voltage supply; a digital processing core having a first digital input interface coupled to the first digital output interface, and having a second digital output interface, the digital processing core configured to generate a digital control output at the second digital output interface based on a difference between the digital representation of the scaled output voltage and a digital representation of a reference voltage, the digital processing core powered by the independent voltage supply; and a digital-to-analog converter (DAC) with a second digital input interface coupled to the second digital output interface, and having an analog output coupled to the transistor. The DAC is configured to convert the digital control output into an analog control voltage and to provide the analog control voltage at the analog output. The analog control voltage controls impedance of the transistor to adjust a regulator output voltage at the output voltage terminal. The DAC is powered by the independent voltage supply.

A linear voltage regulator system is also disclosed herein. The system includes: an input voltage terminal for a regulator input voltage; an output voltage terminal for a regulator output voltage; a reference voltage terminal for a reference voltage; a series pass field-effect transistor coupled between the input voltage terminal and the output voltage terminal; and an error amplifier with an error output coupled to the transistor, a positive error input directly connected to the output voltage terminal to receive the regulator output voltage, and a negative error input coupled to the reference voltage terminal to receive the reference voltage. The error amplifier is powered by an independent voltage supply that is isolated from the input voltage terminal. An output of the error amplifier is based on a difference between the reference voltage and the regulator output voltage. The output of the error amplifier controls impedance of the transistor to adjust the regulator output voltage at the output voltage terminal.

DETAILED DESCRIPTION

When implemented in software or firmware, various elements of the systems described herein are essentially the code segments or instructions that perform the various tasks. In certain embodiments, the program or code segments are stored in a tangible processor-readable medium, which may include any medium that can store or transfer information. Examples of a non-transitory and processor-readable medium include an electronic circuit, a semiconductor memory device, a ROM, a flash memory, an erasable ROM (EROM), a floppy diskette, a CD-ROM, an optical disk, a hard disk, or the like.

“Coupled”—The following description may refer to elements or nodes or features being “coupled” together. As used herein, unless expressly stated otherwise, “coupled” means that one element/node/feature is directly or indirectly joined to (or directly or indirectly communicates with) another element/node/feature, and not necessarily mechanically. Thus, although the schematic shown inFIG.2depicts one exemplary arrangement of elements, additional intervening elements, devices, features, or components may be present in an embodiment of the depicted test system. Furthermore, the connecting lines shown in the various figures contained herein are intended to represent exemplary functional relationships and/or physical couplings between the various elements. It should be noted that many alternative or additional functional relationships or physical connections may be present in an embodiment of the subject matter.

FIG.1is a block diagram that depicts an embodiment of a test system100in a typical testing environment that includes a device under test (DUT)102coupled to the test system100in a way that allows the test system100to perform one or more electrical tests on the DUT102. The test system100may be implemented as a “bench test” component having a chassis or housing that contains various devices, elements, and electronic components. In certain embodiments, the test system100includes a power cord104with a standard alternating current (AC) power plug106to connect with a mains power source. Alternatively or additionally, the test system100can receive direct current (DC) operating voltage from an external power supply108, which obtains AC voltage from a mains power source via a power cord110and AC power plug112. In such an arrangement, the test system100may include at least one input interface114to obtain the DC voltage from the external power supply108(e.g., cable plug sockets, clip terminals, a connector, or the like).

The test system100includes at least one DUT power interface118that establishes an electrical connection120between a voltage regulator of the test system100and the DUT102. The DUT power interface118can be implemented in various form factors, depending on the configuration of the DUT102, the native power supply of the DUT102, the manner in which the DUT102is to be tested, and the like. For example, the DUT power interface118may include or cooperate with any of the following, without limitation: an electrical connector; cable plug sockets, clip terminals, an adapter, or the like. In certain embodiments, the DUT power interface118includes or cooperates with a DC voltage cord or cable that terminates with structure that emulates the shape and size of a battery that is normally used as the power source of the DUT102(such as a 1.5 volt AA battery). The terminating structure includes electrical contacts that simulate the positive and negative terminals of the DUT's battery, such that the voltage regulator of the test system100can provide operating voltage to the DUT102during testing.

The DUT102can be any electronic device having operating voltage and current specifications that are supported by the test system100. In this regard, the test system100must be able to generate sufficient DC operating voltage and current to power the DUT102during testing. In certain applications, the DUT102is a portable battery powered medical device, such as a personal insulin infusion device. In certain embodiments, the DUT102operates in a low power standby mode that is characterized by a discontinuous and high dynamic range standby current waveform. In accordance with a nonlimiting example, the standby current waveform includes discontinuous pulses that peak at approximately 100 mA and persist for only tens of microseconds, with intervening current of approximately 1.00 μA between the pulses, which may occur every 10-100 milliseconds. As mentioned previously, conventional current meters struggle to accurately measure current having such a high dynamic range.

The test system100disclosed here represents an effective, low cost, and elegant solution to the problem outlined above. The test system100employs a method of current measurement that is based on the charging and discharging characteristics of a power capacitor having a known, calibrated capacitance. The power capacitor serves as the source of power for the DUT102, and the charge on the capacitor is directly linked to the current being sourced or sinked, which is defined by physics and the electrical characteristics of the capacitor. The test system100uses the power capacitor to measure the total current consumed by the DUT102during a measurement time period, independent of the DUT's current waveform type, dynamic range, etc. As explained in more detail below, the test system100employs a circuit configuration that is automatically controlled to isolate the current path from the power capacitor to the DUT102. Any leakage current or quiescent current consumed by components of the test system100is negligible relative to the amount of current to be measured, or is isolated such that it has no impact on the current measurement.

FIG.2is a schematic diagram that depicts an embodiment of the test system100coupled to the DUT102. For the embodiment ofFIG.2, all of the illustrated items (other than the DUT102) are part of the test system100. For the sake of clarity and simplicity, the power cord104, AC power plug106, input interface114, and DUT power interface118(seeFIG.1) are not shown inFIG.2. The illustrated embodiment of the test system100includes, without limitation: a power capacitor202; a voltage regulator204; a switching circuit having a first switching element206and a second switching element208; a controller210; a controller clock212; a display device214; a DC voltage source216; one or more isolated power sources217; a first current-isolating buffer218; a second current-isolating buffer220; a third current-isolating buffer222; a diode223; a capacitance calibration circuit224; and various electrically conductive paths, traces, interconnects, or elements that serve to couple the components of the test system100together as needed.

The first switching element206is coupled between the DC voltage source216and a regulator input terminal230of the voltage regulator204. The second switching element208is coupled between the DC voltage source216and a power terminal232of the power capacitor202(the power terminal232is electrically coupled to the positive conductor or plate of the power capacitor202, as depicted inFIG.2). The power capacitor202has a ground terminal234that is electrically coupled to a ground potential of the test system100. The diode223has an anode236coupled to the power terminal232of the power capacitor202, and a cathode238coupled to the regulator input terminal230of the voltage regulator204. The voltage regulator204has a regulator output terminal240that can be coupled to the DUT102for testing purposes. In this regard, the DUT102can be removably connected to the test system100to establish the electrical coupling between the regulator output terminal240and the electronics of the DUT102.

The controller210is coupled to at least the power capacitor202, the voltage regulator204, the first switching element206, the second switching element208, the display device214, and the controller clock212. In accordance with the depicted implementation: the controller210is coupled to the voltage regulator204via an analog output port or terminal244; the third current-isolating buffer222is coupled between the regulator output terminal240and the controller210via an analog input port or terminal246; the controller210is coupled to the display device via a display output interface248; the controller210is coupled to the controller clock via a clock interface250; the second current-isolating buffer220is coupled between the power terminal232of the power capacitor202and a second voltage input terminal252of the controller210; the controller210is coupled to the first switching element206via a first switch control port or terminal254; the controller210is coupled to the second switching element208via a second switch control port or terminal256; and the first current-isolating buffer218is coupled between the regulator input terminal230and a first voltage input terminal258of the controller210. InFIG.2, the SW1and SW2labels represent switch control signals that are used to control the switching states of the first switching element206and the second switching element208, respectively.

The isolated power source(s)217are coupled to certain components, devices, or features of the test system100as appropriate to the particular embodiment. For the sake of clarity and simplicity, the various couplings associated with the isolated power source(s) are not depicted inFIG.2. The capacitance calibration circuit224may be realized as a separate circuit module (as depicted inFIG.2), or it may be implemented with at least some of the other components and features of the test system100, such as the controller210, the voltage regulator204, the diode223, and corresponding interconnections. For the sake of clarity and simplicity, the various couplings associated with the capacitance calibration circuit are not depicted inFIG.2.

The DC voltage source216provides operating voltage(s) for the test system100. In certain embodiments, the test system100includes the DC voltage source216, as depicted inFIG.2. If internal to the test system100, the DC voltage source216can be powered by the mains power source. In some embodiments, however, the DC voltage source216may be external to the test system100. The DC voltage source216charges the power capacitor202when the second switching element208is closed, and provides a DC input voltage to the voltage regulator204when the first switching element206is closed. The voltage regulator204is configured and controlled to generate an appropriate DUT operating voltage at the regulator output terminal240, based on the DC input voltage that is present at the regulator input terminal230. Accordingly, the DC voltage source216provides a DC voltage that is high enough to charge the power capacitor202to its charged voltage level, and high enough to allow the voltage regulator204to generate the necessary operating voltage for the DUT102. In certain nonlimiting embodiments, the nominal operating voltage of the DUT102is 1.5 VDC, and the DC voltage source216provides 12.0 VDC.

The switching circuit includes at least the first switching element206and the second switching element208. The switching elements206,208may be implemented as solid state (transistor-based) switches, or as electromechanical relays. Ideally, the switching elements206,208consume little to no current. Transistor-based switches are appropriate if the amount of switch leakage current is low enough to be considered negligible, relative to the expected amount of DUT current to be measured. For example, if the measured DUT current is expected to be in the range of about one nanoamp or greater, then switches having leakage current in the picoamp range may be suitable for use in the test system (such that the ratio of measurement current to leakage current is at least 1000:1). Relays typically exhibit little to no leakage current and, therefore, are suitable for use in the test system100.

For this particular application, the capacitance of the power capacitor202should be stable across different working voltages, operating temperatures, environmental conditions, and the like. Accordingly, the type (composition) of the power capacitor202should provide a tightly controlled capacitance. For example, the power capacitor202may be a polypropylene film type, high voltage capacitor (e.g., generally greater than 100 volts). The capacitance can be selected to suit the needs and requirements of the particular application. For the example mentioned here (where the DC voltage source216provides 12 VDC, and the DUT102is powered by a 1.5 VDC source), the capacitance of the power capacitor202can be a value within the range of about 1.0 mF to about 10.0 mF (for smaller, low power devices). These capacitor sizes are readily available in polypropylene film.

The diode223is a passive component that may be a conventional off-the-shelf item. The diode223has very low reverse leakage, which should be in the range of about 1,000 times less than the intended measurement current. Accordingly, a silicon diode is best suited for this application (rather than a Schottky diode). The diode223does not consume any measurable quiescent current and, therefore, it can appear in the measured current flow path (as depicted inFIG.2).

The voltage regulator204is digitally controlled by the controller210such that the current consumed by the voltage regulator204is isolated, separated, or otherwise not considered in the measurement of the DUT current. The controller samples the regulator output voltage (at the analog input terminal246) and generates an appropriate control signal (at the analog output terminal244) to increase or decrease the regulator output voltage as needed in an ongoing manner. As explained in more detail below, the voltage regulator204is sourced by the isolated power source(s)217rather than by the DC voltage that appears at the regulator input terminal230. Consequently, the quiescent current consumed by the voltage regulator204is associated with the isolated power source(s)217, and the voltage regulator204operates in a current-isolated manner relative to the current consumed by the DUT102during testing. Additional details of the voltage regulator204are described below with reference toFIGS.5-7.

Each of the current-isolating buffers218,220,222may be implemented as a unity gain operational amplifier having a conventional layout and configuration. Although not shown inFIG.2, the current-isolating buffers218,220,222may include or cooperate with a simple voltage divider circuit if needed for compatibility with the analog inputs of the controller210. The current-isolating buffers218,220,222allow the controller210to sample the respective voltages, without consuming any measurable current. The current-isolating buffers218,220,222are powered by the isolated power source(s)217, and they have very low input leakage current. The input leakage current is low enough to make it negligible relative to the amount of DUT current that is to be measured. Thus, the measured DUT current remains accurate and precise even though the current-isolating buffers218,220,222branch off of the measurement current flow path. Stated another way, the buffers218,220,222are suitably configured and arranged to isolate the controller210from the test current flow path between the power capacitor202and the DUT102.

The test system100calculates the electrical current consumed by the DUT102during a measurement period of time, and generates the calculated current as an output. The display device214represents one type of output device that can be used to display the calculated current as an output. The display device214may be integrated with the housing or chassis of the test system100, or it may be realized as a separate peripheral component that connects to and/or communicates with the test system100. Any type of display technology and form factor can be utilized with the display device214, and the specific implementation details of the display device214will not be described here. In addition to, or instead of, the display device214, the test system100may include or cooperate with other output devices or systems, such as a printer, an audio transducer, a mechanical output device, or an interface that sends a notification, an email, a text message, an electronic report, or the like.

The controller210may be realized as one or more physical devices, such as a microcontroller unit, a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system on a chip (SOC), or the like. In certain embodiments, the controller210is realized as a “single device” microcontroller unit that includes a processor core (e.g., a CPU), a storage medium for processor executable program instructions, an input/output interface, at least one digital-to-analog converter (DAC), at least one analog-to-digital converter (ADC), memory (volatile and nonvolatile), and other peripheral components or elements as needed. The controller210may be based on an off-the-shelf component that is programmed, configured, and/or customized for use in the test system100. To this end, the controller210is configurable to carry out the various processes, methods, operations, and functions described herein.

As mentioned previously, the test system100is designed, configured, and operated such that the current consumed by the DUT102can be accurately and precisely measured in an isolated manner. To this end, leakage current, quiescent current, and/or operating current consumed by certain components, devices, and elements of the test system100are minimized to the point where their contribution is negligible, or the sources of such current are isolated from the test current flow path. In this regard, the isolated power source(s)217may be utilized to provide operating voltage to one or more of the following items: the first switching element206; the second switching element208; the voltage regulator204; the controller210; the display device214; the controller clock212; the first current-isolating buffer218; the second current-isolating buffer220; the third current-isolating buffer222; and the capacitance calibration circuit224.

As explained in more detail below, the known capacitance of the power capacitor202is used to calculate the current consumed by the DUT102during the measurement time period. Although the power capacitor202is chosen such that its capacitance is relatively stable and constant, it can still be susceptible to slight variation over time. Thus, it is important to have an accurate calibrated capacitance value. The capacitance calibration circuit224is couplable to the power capacitor202to calibrate the capacitance of the power capacitor202. Calibration may occur whenever the test system100is powered up, before each current measurement, daily, weekly, or the like. The capacitance calibration circuit224can be implemented to self-calibrate the test system100using, for example, a constant and known current source, which may cooperate with other components of the test system100to perform a calibration routine. When performing a calibration, the fixed current source (e.g., a constant 1.0 mA current) takes the place of the DUT102. For calibration, the unknown variable is the capacitance, which can be calculated based on the discharge characteristics of the power capacitor202. The calibrated capacitance can be saved for use as a known value for subsequent current measurements, where the unknown variable is the current consumed by the DUT102. The test system100itself may also be calibrated as needed, such as annually, monthly, or the like. Calibration of the test system100may require external calibration equipment to calibrate the voltage sources, the fixed current source that is used to obtain the calibrated capacitance, the ADCs and DACs of the controller210, etc.

The switching circuit is configured and controlled by the controller210to regulate electrical connections between the DC voltage source, the power capacitor202, and the voltage regulator204. In this regard, the controller210is configurable to control the switching circuit by independently opening and closing the switching elements206,208as needed. The controller210activates or actuates the switching elements206,208to place the test system100into different states or operating modes including, without limitation: a charging state; a measurement state; and a post-measurement state.

For the charging state, the controller210keeps the first and second switching elements206,208closed to charge the power capacitor202with source voltage provided by the DC voltage source216. When both of the switching elements206,208are closed, the diode223is not forward biased and, therefore, current does not flow through the diode223. Thus, the voltage of the power capacitor202can be sampled and monitored by the controller210via the second voltage input terminal252. While operating in the charging state, the source voltage of the DC voltage source216is present at the regulator input terminal230, which enables the voltage regulator204to generate a regulated DUT operating voltage for the DUT102. The DUT operating voltage can operate the DUT102while the power capacitor202is being charged. Accordingly, the DUT102can be initialized, prepared for testing, placed into its low current standby mode, or the like, while being sourced by the DC voltage source216.

For the measurement state, the controller210keeps the first and second switching elements206,208open to provide the capacitor voltage to the regulator input terminal230. Opening the switching elements206,208isolates the DC voltage source216from the other components of the test system100. Thus, while in the measurement state, the power capacitor202functions as the voltage source instead of the DC voltage source216—the power capacitor202provides its capacitor voltage to the voltage regulator204via the diode223. When both of the switching elements206,208are open, the diode223is forward biased by the capacitor voltage and, therefore, the diode permits discharge of the power capacitor202by way of a test current flow path270. The test current flow path (depicted in dashed lines) runs from the power capacitor202, through the diode223, through the voltage regulator204, and to the DUT102, which represents the electrical load that consumes the power provided by the power capacitor202. While operating in the measurement state, the capacitor voltage is present at the regulator input terminal230, which enables the voltage regulator204to generate the regulated DUT operating voltage for the DUT102(assuming that the capacitor voltage remains high enough). While operating in the measurement state, the capacitor voltage can be sampled by the controller210(via the second voltage input terminal252), and the voltage present at the regulator input terminal230can be sampled by the controller210(via the first voltage input terminal258).

For the post-measurement state, the controller210keeps the first switching element206closed and the second switching element208open. While the test system100is in the post-measurement state, the DC voltage source216provides its voltage to the regulator input terminal230and to the cathode238of the diode223, via the first switching element206. In the post-measurement state, the diode223is reverse biased and, therefore, inhibits further discharge of the power capacitor202. Accordingly, the source voltage generated by the DC voltage source216can be sampled by the controller210(via the first voltage input terminal258), and the discharged voltage of the power capacitor202can be sampled by the controller210(via the second voltage input terminal252) when the test system100is in the post-measurement state.

Operation of the test system100will now be described with reference toFIG.3, which is a flow chart that illustrates an embodiment of an automated current measurement process300. The process300is performed by the test system100to measure electrical current consumed by the DUT102. The description of the process300may refer to elements mentioned above in connection withFIGS.1and2. It should be appreciated that the process300may include any number of additional or alternative tasks, the tasks shown inFIG.3need not be performed in the illustrated order, and the process300may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. Moreover, one or more of the tasks shown inFIG.3could be omitted from an embodiment of the process300as long as the intended overall functionality remains intact.

The process300may begin by calibrating the capacitance of the power capacitor202(task302). As explained above, calibration need not be performed for each measurement and, therefore, task302may be performed periodically, in accordance with a particular schedule, or the like. Nonetheless, task302is shown for the sake of completeness. The following description of the process300assumes that the test system100has an accurate calibrated value of the capacitance, which can be used to calculate the amount of current consumed by the DUT102during the measurement period. The DUT102is connected to the test system100in an appropriate manner (task304) to establish an electrical coupling between the regulator output terminal240and the electronics of the DUT102. In this way, the voltage regulator204can serve as the power source of the DUT102.

After the DUT102has been connected to the test system100, the current measurement routine begins. The test may begin automatically in response to connecting the DUT102, or it may require a user instruction or command. In certain embodiments, the test system100automatically controls the switching circuit with the controller210to place the test system into the charging state (task306). As mentioned above, the controller210keeps the first and second switching elements206,208closed while the test system100is in the charging state, such that the DC voltage source216charges the power capacitor202. Moreover, the DC voltage source216provides an input voltage to the voltage regulator204, which in turn provides an appropriate operating voltage to the DUT102. Accordingly, the DUT102can be initialized and otherwise prepared for the current measurement routine.

The charging state is maintained until the power capacitor202is charged (e.g., the capacitor voltage has reached a charged voltage level). If the power capacitor202has not reached the charged voltage (the “No” branch of query task308), then the test system remains in the charging state. If the power capacitor202has reached the charged voltage (the “Yes” branch of query task308), then the process300continues by automatically controlling the switching circuit with the controller210to transition the test system100from the charging state into the measurement state (task310). In some embodiments, query task308involves comparing the capacitor voltage against a charged voltage threshold, such that the switching circuit is automatically controlled to place the test system100into the measurement state when the capacitor voltage reaches the charged voltage threshold. The controller210can sample the capacitor voltage at the second voltage input terminal252for purposes of this comparison. In some embodiments, query task308involves monitoring elapsed time after entering the charging state, such that the switching circuit is automatically controlled to place the test system into the measurement state when the elapsed time exceeds a charging time threshold. The controller210can maintain a counter or a timer (based on operation of the controller clock212) to monitor the elapsed time.

This example assumes that the power capacitor202has reached its charged voltage and that the test system100has transitioned to the measurement state. As mentioned above, the controller210opens the first and second switching elements206,208to place the test system100into the measurement state, and keeps them open while the test system operates in the measurement state. For the measurement state, the DC voltage source216is disconnected from the remaining components, and the power capacitor202provides its capacitor voltage to the voltage regulator204. In response to the transition to the measurement state, the controller210begins (or resumes) sampling the voltages at the first voltage input terminal258and the second voltage input terminal252(task312), and records a measurement start time (task314). In certain embodiments, tasks310,312, and314are performed concurrently such that the measurement start time is recorded, the voltages are sampled, and the switching elements206,208are opened at the same time. Thus, the measurement start time is associated with opening of the switching elements206,208.

The measurement state is maintained until the power capacitor202has reached a discharged voltage in response to loading, i.e., operation of the DUT102. In this regard, the capacitor voltage drops over time due to current consumed by the DUT102. If the power capacitor202has not reached the discharged voltage (the “No” branch of query task316), then the test system100remains in the measurement state. If the power capacitor202has reached the discharged voltage (the “Yes” branch of query task316), then the process300continues by automatically controlling the switching circuit with the controller210to transition the test system100from the measurement state into the post-measurement state (task318). The test system100is designed and operated such that the power capacitor202is not discharged too much during the measurement state, to ensure that the voltage characteristics of the power capacitor remain linear.

In some embodiments, query task316involves comparing the capacitor voltage against a minimum capacitor voltage threshold, such that the switching circuit is automatically controlled to place the test system100into the post-measurement state when the capacitor voltage is less than or equal to the minimum capacitor voltage threshold. The controller210can sample the capacitor voltage at the second voltage input terminal252for purposes of this comparison. For the example presented here, where the DC voltage source216provides 12 VDC, the minimum capacitor voltage threshold may be about 8 VDC. In some embodiments, query task316involves monitoring elapsed time after entering the measurement state (i.e., after opening of the switching elements206,208), such that the switching circuit is automatically controlled to place the test system100into the post-measurement state when the elapsed time is greater than or equal to a maximum time threshold. The controller210can maintain a counter or a timer (based on operation of the controller clock212) to monitor this elapsed time. For the example presented here, the maximum time threshold may be on the order of one to two seconds.

This example assumes that the power capacitor202has reached the discharged voltage and that the test system100has transitioned to the post-measurement state. As mentioned above, the controller210closes the first switching element206and keeps the second switching element208open to place the test system100into the post-measurement state, and maintains those switch conditions while the test system100operates in the post-measurement state. For the post-measurement state, the DC voltage source216is coupled to: the cathode238of the diode223; the input of the first current-isolating buffer218; and the regulator input terminal230. The open state of the second switching element208, however, keeps the DC voltage source216disconnected from: the power capacitor202; the anode236of the diode223; and the input of the second current-isolating buffer220. Accordingly, the diode223is reverse biased, the power capacitor202no longer discharges, and the capacitor voltage (which is sampled at the second voltage input terminal252) remains stable in the post-measurement state. Moreover, the voltage provided by the DC voltage source216, which corresponds to the charged voltage of the power capacitor202, can be sampled at the first voltage input terminal258in the post-measurement state.

In response to the transition to the post-measurement state, the controller210records a measurement end time (task320). In certain embodiments, tasks318and320are performed concurrently such that the first switching element206is closed and the measurement end time is recorded at the same time. Thus, the measurement end time is associated with closing of the first switching element206. The controller210may stop sampling the voltages at the first voltage input terminal258and the second voltage input terminal252(task322) at any suitable time following the transition to the post-measurement state. For reasons explained below, the controller210continues sampling these voltages in the post-measurement state for a period of time, to ensure that the voltages have stabilized.

The process300continues by calculating the electrical current provided by the power capacitor202(and consumed by the DUT102) in a time period recorded during operation of the test system100in the measurement state (task324). For this example, the time period is defined by the recorded measurement start time and the recorded measurement end time, and the calculation is based on a sampled value of the charged voltage of the power capacitor202, a sampled value of the discharged voltage of the power capacitor202, and discharge characteristics of the power capacitor202—namely, the relationship between capacitance and capacitor voltage over time with respect to electrical current. More specifically, the controller210calculates the electrical current consumed by the DUT102between the recorded measurement start time and the recorded measurement end time in accordance with the expression

i=C⁢Vc-Vdtf-ti,
where: C is the known (calibrated) capacitance of the power capacitor; Vcis the sampled value of the charged voltage; Vdis the sampled value of the discharged voltage; tiis the recorded measurement start time; and tfis the recorded measurement end time. The controller210records the measurement start and end times, samples the capacitor voltage at the second voltage input terminal252, and samples the input voltage of the voltage regulator204at the first voltage input terminal258. Thus, the current consumed by the DUT102can be easily determined at task324.

The process300continues by generating the calculated electrical current as an output of the test system100(task326). For example, the display device214can be controlled and driven in an appropriate manner to display the calculated electrical current in any desired format, e.g., a numerical readout. For this particular example, the test system100displays the standby current consumed by the DUT102during the measurement time period, which is typically several seconds. The standby current represents an average of the instantaneous current measured over the recorded time period.

FIG.4is a graph that includes plots of voltage levels over time, as sampled during a typical current measurement test performed by the test system100shown inFIG.2. The horizontal time axis indicates the measurement start time (ti) and the measurement end time (tf). The vertical voltage axis indicates the charged voltage (Vc) and the discharged voltage (Vd) of the power capacitor202. InFIG.4, the dashed line plot402corresponds to the voltage present at the regulator input terminal230, the cathode238of the diode223, and the input of the first current-isolating buffer218. In other words, the plot402represents the voltage sampled at the first voltage input terminal258of the controller210. The solid line plot404corresponds to the voltage present at the power terminal232of the power capacitor202, the anode236of the diode223, and the input of the second current-isolating buffer220. In other words, the plot404represents the voltage sampled at the second voltage input terminal252of the controller210. The two plots402,404, track each other during the charging state (before the measurement start time) and during the measurement state (between the measurement start time and the measurement end time), due to the status of the switching elements206,208during that period of time. The two plots402,404diverge at the measurement end time, due to the closure of the first switching element206(the second switching element208remains open). As explained above, the transition from the measurement state to the post-measurement state reconnects the DC voltage source216to the voltage regulator204, which makes the source voltage (i.e., the charged voltage) immediately available for sampling at the first voltage input terminal258. The capacitor voltage, however, remains stable in the post-measurement state. Accordingly, the discharged voltage of the power capacitor202is available for sampling at the second voltage input terminal252.

For the embodiment shown inFIG.2, it is assumed that the charged voltage of the power capacitor202equals the voltage generated by the DC voltage source216. Accordingly, the charged voltage value may be sampled at the first voltage input terminal258at a sampling time that occurs before the measurement start time and/or at a sampling time that occurs after the measurement end time (i.e., while the test system100is in the post-measurement state). Alternatively or additionally, the charged voltage value may be sampled at the second voltage input terminal252at a sampling time that occurs before the measurement start time.

The embodiment of the test system100shown inFIG.2samples the discharged voltage at the second voltage input terminal252at a sampling time that occurs after the measurement end time, while the capacitor voltage remains constant. For example, the test system100may wait a number of sampling periods or a designated amount of time before sampling the discharged voltage, or it may continue to sample the discharged voltage level but only consider sampled values obtained after the designated amount of time (e.g., 100 ms, one second, or the like). This sampling scheme takes into account the equivalent series resistance (ESR) of the power capacitor202. The effect of ESR on the sampled voltages is schematically depicted inFIG.4. At the measurement start time, both plots402,404exhibit a sudden voltage drop. This drop occurs when the switching elements206,208are opened to insert the power capacitor202into the current flow path270; the voltage drop is caused by the ESR of the power capacitor202. At the measurement end time, however, the power capacitor202is removed from the current flow path270. Consequently, the ESR of the power capacitor202results in a quick voltage recovery before the capacitor voltage stabilizes to its discharged voltage level. The controller210uses a sampled value of the stabilized capacitor voltage to calculate the current consumed by the DUT102.

Referring again to task324and the expression used to calculate the measured current, the charged voltage (Vc) may be sampled: at the first voltage input terminal258of the controller210at a sampling time that occurs before the measurement start time; at the first voltage input terminal258of the controller210at a sampling time that occurs after the measurement end time; and/or at the second voltage input terminal252of the controller210at a sampling time that occurs before the measurement start time. The discharged voltage (Vd) is sampled at the second voltage input terminal252at a sampling time that occurs after the measurement end time. Although not required, the charged voltage and the discharged voltage can be sampled at the same sampling time (while the test system100is in the post-measurement state).

The current measurement procedure described here can reliably and accurately measure the average current consumed by a DUT, even when the current exhibits a very high dynamic range and relatively low peak current values. The test system100described here can be fabricated from inexpensive and readily available parts and components, and can be modified as needed to effectively support different types of DUTs having different functional specifications, voltage requirements, and current consumption characteristics.

As mentioned above, the voltage regulator204is suitably configured and controlled such that its output current very closely matches its input current (i.e., any quiescent current consumed by the voltage regulator204is negligible relative to the amount of DUT current being measured). Linear voltage regulators are used to produce a constant output voltage from a varying input voltage of higher magnitude. Linear voltage regulators typically include a series pass transistor (which may be a MOSFET or a BJT), an error amplifier, a voltage reference, and a feedback divider network. The voltage reference establishes a fixed voltage value that is used for comparison purposes. The feedback divider network produces a scaled version of the output voltage with a reduction ratio equal to the desired output voltage divided by the reference voltage. The error amplifier compares the scaled output voltage against the reference voltage, and drives the series pass transistor to vary its resistance. Ideally, the transistor is driven to minimize the difference between the output voltage and the reference voltage.

A typical linear voltage regulator that follows conventional design methodologies includes three terminals: an input voltage terminal (VIN); an output voltage terminal (VOUT); and a ground terminal (GND). The input voltage is applied between the VIN and GND terminals, and the regulated output voltage is supplied between the VOUT and GND terminals. The series pass transistor places the VIN and VOUT terminals in a series circuit. Theoretically, the current flowing into the VIN terminal (IIN) should be equal to the current flowing out of the VOUT terminal (IOUT). However, IINis always higher than IOUT(for such conventional voltage regulators) because the regulator inherently consumes an amount of current that is associated with operation of the voltage reference, the error amplifier, and the feedback divider network. Depending on the topology and implementation of the voltage regulator, the magnitude of the difference between IINand IOUTis highly variable and may also vary depending on the applied load.

In some applications (e.g., the test system100described above), it may be desirable to have IINmatch IOUT. For example, such a scenario exists when it is necessary to precisely measure the applied load current without affecting the voltage on the VOUT terminal. If the IINis identical to IOUT, then a shunt resistor can be placed in series with the VIN terminal, and the voltage drop across the shunt resistor will be directly proportional to the magnitude of the IOUTcurrent. In this situation, the voltage drop across the shunt resistor will not affect the regulated output voltage of the voltage regulator, because the regulator will naturally account for the drop on the VIN terminal.

In accordance with certain embodiments described here, the current consumed by the voltage regulator itself is isolated from the current supplied to the load. The current-isolating design and configuration of the voltage regulator results in matching values of IINand IOUT, wherein any difference is negligible or de minimis relative to the magnitude of IINand IOUT. In this regard,FIG.2depicts an implementation where the controller210controls the voltage regulator204without consuming current from the power capacitor202. Moreover, the voltage regulator204, the controller210, and the third current-isolating buffer222obtain operating voltage from the isolated power source(s)217rather than from the power capacitor202.FIGS.5-7depict embodiments of a linear voltage regulator having isolated supply current. The test system100can be modified (if needed) to use the voltage regulators shown inFIGS.5-7.FIG.5depicts a linear voltage regulator500that is based on an analog design,FIG.6depicts a linear voltage regulator600that includes or cooperates with an ADC, a DAC, and a processing core, andFIG.7depicts a linear voltage regulator700that includes or cooperates with a DAC.

Referring toFIG.5, the linear voltage regulator500generally includes, without limitation: a series pass transistor502; an error amplifier504; a voltage reference source506to provide a reference voltage for the voltage regulator500; a buffer amplifier508; a feedback divider network that includes a first resistor510and a second resistor512; an input voltage terminal514(labeled VIN) for the regulator input voltage; an output voltage terminal516(labeled VOUT) for the regulator output voltage; a supply voltage terminal518(labeled VSPLY); and a ground terminal520(labeled GND).

To achieve appropriate current isolation, the series pass transistor502is a metal-oxide-semiconductor field-effect transistor (MOSFET). For the depicted embodiment, the transistor502is a p-channel enhancement mode MOSFET. The transistor502is coupled between the input voltage terminal514and the output voltage terminal516. More specifically, the source of the transistor502is coupled to the input voltage terminal514, the drain of the transistor502is coupled to the output voltage terminal516, and the gate of the transistor is coupled to the error output530of the error amplifier504. The feedback divider network is coupled between the buffer output548and the ground terminal520. A negative error input532of the error amplifier504is coupled to a positive terminal534of the voltage reference source506, and a positive error input536of the error amplifier504is coupled to the feedback divider network. More specifically, the positive error input536is coupled between the first and second resistors510,512, which are connected in series with one another. Notably, the error amplifier504is powered by an independent voltage supply, which can be coupled between the supply voltage terminal518and the ground terminal520(the lines leading from the error amplifier504to the supply voltage terminal518and the ground terminal520represent the supply voltage connection). A negative terminal540of voltage reference source506is coupled to the ground terminal520, and the voltage reference source506is powered by the independent voltage supply (the voltage reference source506is coupled to the supply voltage terminal518to obtain the supply voltage).

The buffer amplifier508is configured as a unity gain follower having a high input impedance. The positive buffer input544of the buffer amplifier508is coupled to the drain of the transistor502and to the output voltage terminal516. The negative buffer input546of the buffer amplifier508is coupled to the buffer output548of the buffer amplifier508and to a first end550of the first resistor510. Notably, the buffer amplifier508is powered by the independent voltage supply (the lines leading from the buffer amplifier508to the supply voltage terminal518and the ground terminal520represent the supply voltage connection). The second end552of the first resistor510is coupled to a first end554of the second resistor512and to the positive error input536of the error amplifier504, as mentioned above. The second end556of the second resistor512is coupled to the ground terminal520, thus establishing the feedback divider network. The resistor values are chosen such that the feedback divider network provides a scaled output voltage (that ideally matches the reference voltage) at the divider output, which corresponds to the node defined by the second end552of the first resistor510, the first end554of the second resistor512, and the positive error input536of the error amplifier504.

The basic operating principle of the linear voltage regulator500is similar to that described above for a traditional three-terminal voltage regulator. In this regard, the output of the error amplifier504controls the impedance of the transistor502to adjust the regulator output voltage that appears at the output voltage terminal516. The output of the error amplifier504is produced based on the difference between the reference voltage that appears at the negative error input532and the scaled output voltage that appears at the positive error input536. For example, if the scaled output voltage is higher than the reference voltage, then the output voltage of the error amplifier504can be adjusted to incrementally increase the series pass resistance of the transistor502to reduce the regulator output voltage. Conversely, if the scaled output voltage is lower than the reference voltage, then the output voltage of the error amplifier504can be adjusted to incrementally decrease the series pass resistance of the transistor502to increase the regulator output voltage.

The voltage regulator500achieves supply current isolation by way of the buffer amplifier508. The buffer amplifier508is configured and arranged to operate as a unity gain (1:1) follower, such that the voltage at the buffer output548matches the voltage at the positive buffer input544(the output of the buffer amplifier508, rather than the transistor502, drives the feedback divider network). Current isolation is further achieved through the use of the supply voltage terminal518and the ground terminal520, which are coupled to provide source voltage and operating current to the error amplifier504, the voltage reference source506, and the buffer amplifier508—these components are powered by an independent voltage supply that is coupled to the supply voltage terminal518, which is isolated from the input voltage terminal514. Accordingly, the input voltage terminal514supplies current only to the output voltage terminal516, via the transistor502. The inherently high input impedance of the buffer amplifier508results in only a negligible amount of current drawn from the output voltage terminal516.

The transistor502is realized as a MOSFET (either NMOS or PMOS, althoughFIG.2depicts a PMOS implementation) to take advantage of the extremely low gate-source and gate-drain currents. A MOSFET operating in near steady-state conditions has negligible gate-source and gate-drain currents, relative to the amount of series pass current. Furthermore, the high input impedance of the positive buffer input544of the buffer amplifier508ensures that the current flow into the positive buffer input544is negligible compared to the desired current measurement resolution (e.g., less than 1:1000). In this regard, the buffer amplifier508isolates the current flow path from the input voltage terminal514to the output voltage terminal516, such that the ratio of current flowing into the positive buffer input544to current flowing in the current flow path is less than 1:1000. As an example, if the desired current measurement resolution is 1.0 μA, the input impedance of the buffer amplifier508should be on the order of 1.0 GΩ or higher, such that the input current is 1.0 nA or less.

The independent voltage supply (which feeds the supply voltage terminal518) supplies the quiescent current needed to operate the error amplifier504, the voltage reference source506, and the buffer amplifier508. This arrangement provides additional current isolation because the quiescent current is separate and distinct from the current that flows through the transistor502.

Referring toFIG.6, the voltage regulator600generally includes, without limitation: a series pass transistor602; a buffer amplifier608; a feedback divider network that includes a first resistor610and a second resistor612; an input voltage terminal614(labeled VIN); an output voltage terminal616(labeled VOUT); a supply voltage terminal618(labeled VSPLY); a ground terminal620(labeled GND); an ADC670; a digital processing core672; and a DAC674. The arrangement and configuration of the voltage regulator600are similar to that described above for the voltage regulator500. The illustrated embodiment of the voltage regulator600, however, replaces the error amplifier504with the combination of the ADC670, the processing core672, and the DAC674. Accordingly, for the sake of brevity and convenience, common or equivalent aspects of the voltage regulators500,600will not be redundantly described in detail with reference toFIG.6.

The series pass transistor602is realized as a MOSFET having its source coupled to the input voltage terminal614, its drain coupled to the output voltage terminal616, and its gate coupled to an analog output630of the DAC674. An analog voltage input636of the ADC670is coupled to the divider output of the feedback divider network to receive a scaled output voltage produced by the feedback divider network. More specifically, the analog voltage input636is coupled between the first and second resistors610,612, which are connected in series with one another. The positive buffer input644of the buffer amplifier608is coupled to the drain of the transistor602and to the output voltage terminal616. The negative buffer input646of the buffer amplifier608is coupled to the buffer output648of the buffer amplifier608and to a first end650of the first resistor610. The second end652of the first resistor610is coupled to a first end654of the second resistor612and to the analog voltage input636of the ADC670, as mentioned above. The second end656of the second resistor612is coupled to the ground terminal620, thus establishing the feedback divider network.

Although depicted as separate blocks inFIG.6, the ADC670, the processing core672, and the DAC674can be combined into a single device or component, depending on the desired implementation. For example, the ADC670, the processing core672, and the DAC674can be realized as features or elements of a microcontroller device. For the illustrated embodiment, the ADC670is coupled to the processing core672in an appropriate manner to communicate digital information to the processing core672. Likewise, the processing core672is coupled to the DAC674in an appropriate manner to communicate digital information to the DAC674. In this regard, the ADC670has a digital output interface680, which is coupled to a digital input interface682of the processing core672. Moreover, the processing core672has a digital output interface684, which is coupled to a digital input interface686of the DAC674.

The DAC674cooperates with a voltage reference source688, which provides a reference voltage for the digital-to-analog conversion. Similarly, the ADC670cooperates with a voltage reference source690, which provides a reference voltage for the analog-to-digital conversion. The reference voltage used by the DAC674will typically be higher than the reference voltage used by the ADC670. Accordingly, the voltage reference source688can be distinct and separate from the voltage reference source690(as shown). The ADC670, the processing core672, the DAC674, the buffer amplifier608, the voltage reference source688, and the voltage reference source690are powered by an independent voltage supply (as described above). Accordingly, these components are coupled to the supply voltage terminal618and the ground terminal620. For simplicity and clarity,FIG.6does not show separate connections between the supply voltage terminal618and the voltage reference sources688,690.

The basic operating principle of the linear voltage regulator600is similar to that described above for the voltage regulator500. The feedback divider network provides the scaled output voltage to the ADC670. The digital output interface680of the ADC670provides a digital representation of the scaled output voltage that appears at the analog voltage input636. The processing core672receives the digital representation of the scaled output voltage by way of its digital input interface682. The processing core672implements an algorithm that attempts to minimize the difference between the sampled voltage and a specified reference voltage. In this regard, the processing core672calculates a difference between the digital representation of the scaled output voltage and a digital representation of a programmed, stored, or otherwise designated reference voltage. The processing core672generates a digital control output at its digital output interface684, wherein the digital control output is based on the calculated difference. The digital control output is provided to the DAC674, by way of the digital input interface686.

The DAC674is configured and operated to convert the digital control output into a corresponding analog control voltage, which appears at the analog output630of the DAC674. The analog control voltage controls the impedance of the transistor602to adjust the regulator output voltage that appears at the output voltage terminal616.

As described above with reference to the voltage regulator500, the transistor602, the buffer amplifier608, and the independent voltage supply (that feeds the supply voltage terminal618) cooperate to provide current isolation for the voltage regulator600. Accordingly, the input voltage terminal614supplies current only to the output voltage terminal616, via the transistor602.

Referring toFIG.7, the voltage regulator700generally includes, without limitation: a series pass transistor702; an error amplifier704; an input voltage terminal714(labeled VIN) for the regulator input voltage; an output voltage terminal716(labeled VOUT) for the regulator output voltage; a supply voltage terminal718(labeled VSPLY) for an independent voltage supply; a ground terminal720(labeled GND); and a reference voltage terminal721(labeled VREF) for a reference voltage. Certain aspects of the voltage regulator700are similar to that described above for the voltage regulators500,600. Accordingly, for the sake of brevity and convenience, common or equivalent aspects of the voltage regulators500,600,700will not be redundantly described in detail with reference toFIG.7.

The series pass transistor702is realized as a MOSFET having its source coupled to the input voltage terminal714, its drain coupled to the output voltage terminal716, and its gate coupled to the error output730of the error amplifier704. A negative error input732of the error amplifier704is coupled to the reference voltage terminal721to receive the reference voltage. In certain embodiments, a positive error input736of the error amplifier704is directly connected to the drain of the transistor702and to the output voltage terminal716(in other words, no intervening components, devices, or elements are arranged between the output voltage terminal716and the positive error input736). Thus, the error amplifier704directly receives the regulator output voltage in a feedback path. The error amplifier704is powered by an independent voltage supply, which can be coupled between the supply voltage terminal718and the ground terminal720. As mentioned previously, the independent voltage supply is isolated from the input voltage terminal714.

The illustrated embodiment of the voltage regulator700employs an external DAC750and an associated reference voltage source752. The DAC750and the reference voltage source752take the place of an internal voltage reference for the error amplifier704, a feedback divider network, and a 1:1 buffer amplifier (which are described above in the context of the voltage regulators500,600). The DAC750and the reference voltage source752obtain operating power from a source other than the voltage that serves as the input to the voltage regulator700. For example, the DAC750and the reference voltage source752may be powered by the independent voltage supply and/or by another auxiliary voltage supply (not shown inFIG.7).

The DAC750generates a fixed analog voltage that is equal to the desired regulator output voltage. The error amplifier704compares the voltage at the output voltage terminal716against the voltage applied to the reference voltage terminal721, and drives the series pass transistor702to maintain the minimum possible difference. The positive error input736of the error amplifier704has a very high impedance (as mentioned above with reference to the buffer amplifier508) to limit the amount of current drawn from the output voltage terminal716by the error amplifier704.

The DAC750functions as a fixed reference voltage source, and its analog output is coupled to the reference voltage terminal721. The DAC750represents a digitally programmable component that can be configured to provide the desired reference voltage, up to a maximum voltage that is based on the voltage generated by the reference voltage source752. Thus, the reference voltage provided by the DAC750can be digitally programmed and adjusted to match the expected regulator output voltage present at the output voltage terminal716. In alternative implementations, a suitably configured analog voltage source or fixed voltage supply can be utilized instead of the DAC750. For example, if the regulator output voltage is expected to be 1.5 VDC, then an external 1.5 VDC voltage source can be coupled to the reference voltage terminal721.

The basic operating principle of the linear voltage regulator700is similar to that described above for the voltage regulator500. The regulator output voltage (not a scaled version of it) is fed directly to the positive error input736of the error amplifier704, and the external DAC750provides the desired reference voltage to negative error input732of the error amplifier704, by way of the reference voltage terminal721. The error amplifier704generates its output based on the difference between the reference voltage and the regulator output voltage, and the output controls the impedance of the transistor to adjust the regulator output voltage as needed.