Semiconductor memory device having preamble function

A semiconductor memory device includes a data controller for generating a data signal in response to data generated at an internal circuit of the semiconductor memory device when a latency signal, which sets the latency of the semiconductor memory device, is activated. The device includes an output driver for generating a data strobe signal in response to the data signal, a preamble controller for outputting a preamble control signal in response to a read command input to the semiconductor memory device, and a preamble unit for preambling the data strobe signal by changing an output signal of the output driver from a logic high level to a logic low level, when the preamble control signal is activated. Data output from the semiconductor memory device has a satisfactory preamble section.

This application claims the priority of Korean Patent Application No. 2002-29110, filed May 25, 2002, the entire contents of which are hereby incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a preamble function.

2. Description of the Related Art

Data output from a semiconductor memory device having a preamble function, such as dual data rate synchronous dynamic random access memory (DDR SDRAM), is output after the preamble section ends.

FIG. 1 is a timing diagram of a conventional semiconductor memory device having a preamble function. Referring to FIG. 1 , when a read command (READ) is in synchronization with an external clock signal (ECLK) and an input to a semiconductor memory device (notshown), a latency control signal (Latencyds) is in synchronization with an internal clock signal (DLL CLK). Moreover, the latency control signal (Latencyds) is activated under such conditions. During the activation of the latency control signal (Latencyds), an output data strobe signal (DQS) output from the semiconductor memory device is changed from a logic high level to a logic low level. As a result, output data (DQ) has a preamble section tp. The preamble section tp is maintained for one cycle of the internal clock signal (DLL CLK), and the output data strobe signal (DQS) is activated and output external to the semiconductor memory device when a latency signal (Latency) is activated.

As described above, according to the conventional semiconductor memory device, the preamble section tp is maintained only for one cycle of the internal clock signal (DLL CLK). Therefore, it is possible to maintain the preamble section tp when the operational frequency of the semiconductor memory device is low. However, if the operational frequency of the semiconductor memory device is high, e.g., the operational frequency is more than 300 MHz, the duty cycle of the internal clock signal (DLL CLK) becomes very short. In this case, a starting point of the preamble section tp may be delayed or the preamble section tp may not be present, which prevents the semiconductor memory device from stably outputting data.

In conclusion, the higher the operational frequency of a semiconductor memory device, the more difficult it is to maintain a preamble section tp.

SUMMARY OF THE INVENTION

An exemplary embodiment of the present invention provides a semiconductor memory device in which a preamble section is sufficiently secured.

An exemplary embodiment of the present invention provides a semiconductor memory device having a preamble function, including an output driver for generating a data strobe signal and, outputting the same external to the semiconductor memory device. The embodiment also includes a preamble unit for preambling the data strobe signal by changing an output signal of the output driver from a high impedance status to a logic low level. This is achieved in synchronization with an activation of a read command input to the semiconductor memory device.

In addition, an exemplary embodiment of the present invention provides a semiconductor memory device having a preamble function, including a data controller for generating a data signal in response to data generated at an internal circuit of the semiconductor memory device when a latency signal, which sets the latency of the semiconductor memory device, is activated. The semiconductor memory device may also include an output driver for generating a data strobe signal in response to the data signal, a preamble controller for outputting a preamble control signal in response to a read command input to the semiconductor memory device, and a preamble unit for preambling the data strobe signal by changing an output signal of the output driver from a high impedance status to a logic low level, when the preamble control signal is activated.

Furthermore, an exemplary embodiment of the present invention provides a semiconductor memory device having a preamble function, including an output driver having a pull-up unit for generating a data strobe signal in response to a data signal and a control signal generated at an internal circuit of the semiconductor memory device. The pull-up unit is activated to output the data strobe signal to a logic high level when the data signal is at a logic low level. Furthermore, the pull-down unit is activated to output the data strobe signal to a logic low signal when the control signal is at a logic high level. The semiconductor memory device may further include a logic unit for outputting the control signal to a logic high level and sending the same to the pull-down unit when at least one of the data signal and the preamble control signal generated in response to a read command input to the semiconductor memory device is at a logic high level. According to an exemplary embodiment of the present invention, an output of the output driver is maintained at a high impedance status during a stand-by state, the pull-down unit is activated when the preamble control signal becomes active, and then, the output of the output driver is changed from the high impedance status to a logic low level; therefore, the data strobe signal output from the semiconductor memory device is preambled.

Still further, an exemplary embodiment of the present invention provides a semiconductor memory device having a preamble function. The semiconductor memory device includes a data controller for outputting a data signal in response to data generated at an internal circuit of the semiconductor memory device. The foregoing occurs when a latency signal, which sets the latency of the semiconductor memory device, is activated. The semiconductor device further includes an output driver for generating an output data strobe signal, a pull-up unit being activated to output the data strobe signal to a logic high level when the data signal output from the data controller is at a logic low level, and a pull-down unit being activated to output the data strobe signal to a logic low level when the input control signal is at a logic high level. Furthermore, the device includes a preamble controller for outputting a preamble control signal in response to a read command input to the semiconductor memory device, and a logic unit for outputting an output signal to a logic high and inputting the same to the pull-down unit when at least one of the preamble control signal and the data signal is at a logic high level. The logic unit is for preambling the data strobe signal by changing the data strobe signal to a logic low level when the preamble control signal is activated.

An exemplary embodiment of the present invention provides a semiconductor memory device having a preamble function. The semiconductor device includes an output driver for outputting a data strobe signal to the outside of the semiconductor memory device, and a preamble unit for receiving a read command in synchronization with a clock of an external clock signal input to the semiconductor memory device and outputting a control signal. The output driver also may output a control signal to change the data strobe signal from a high impedance status to a logic low level in response to the control signal in synchronization with the clock of the external clock signal.

Furthermore, an exemplary embodiment of the present invention provides a semiconductor memory device having a preamble function. The device includes a data controller for generating a data signal in response to data generated at an internal circuit of the semiconductor memory device when a latency signal, which sets the latency of the semiconductor memory device, is activated. Furthermore, the semiconductor device includes an output driver for outputting a data strobe signal in response to the data signal, a preamble controller for receiving a read command in synchronization with a clock of an external clock signal input to the semiconductor memory device and outputting a preamble control signal in synchronization with a clock of the external clock signal to which the read command is input, and a preamble unit for changing the data strobe signal from a high impedance status to a logic low level when the preamble control signal is activated.

In addition, an exemplary embodiment of the present invention provides a semiconductor memory device having a preamble function. The semiconductor device includes an output driver for generating a data strobe signal in response to a data signal and a control signal generated at an internal circuit of the semiconductor memory device. The output driver includes a pull-up unit being activated to output the data strobe signal to a logic high level when the data signal is at a logic low level, and a pull-down unit being activated to output the data strobe signal to a logic low level when the control signal is at a logic high level. Furthermore, a logic unit is provided for outputting the control signal to a logic high level and sending the same to the pull-down unit, when a read command is input to the semiconductor memory device in synchronization with a clock of an external clock signal input to the semiconductor memory device and at least one of a preamble control signal. The preamble control signal is generated in synchronization with a clock of the external clock signal to which the read command is input, and the data signal is at a logic high level, wherein an output of the output driver is maintained at a logic high level during a stand-by state, and the pull-down unit is activated to change the output of the output driver from the high impedance status to a logic low level when the preamble control signal is activated, thereby preambling the data strobe signal.

Furthermore, an exemplary embodiment of the present invention provides a semiconductor memory device having a preamble function. The semiconductor device includes a data controller for outputting a data signal in response to data generated at an internal circuit of the semiconductor memory device when a latency signal, which sets the latency of the semiconductor memory device, is activated. Moreover, the device includes an output driver for generating an output data strobe signal, the output driver having a pull-up unit for generating a data strobe signal being output to a logic high level when the data signal output from the data controller is at a logic low level, and a pull-down unit being activated to output the data strobe signal to a logic low level when the control signal is at a logic high level. The output driver further includes a preamble controller for receiving a read command in synchronization with a clock of an external clock signal input to the semiconductor memory device and outputting a preamble control signal in synchronization with a clock of the external clock signal to which the read command is input, and a logic unit for outputting an output signal to a logic high level and sending the same to the pull-down unit when at least one of the preamble control signals and the data signal is at a logic high level. The logic unit preambles the data strobe signal by changing the data strobe signal to a logic low level.

According to the embodiments of the present invention, it may be possible to sufficiently secure a preamble section in a data strobe signal output from a semiconductor memory device.

DETAILED DESCRIPTION OF THE INVENTION

Exemplary embodiments of the present invention will now be described more fully with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, the exemplary embodiments are merely provided to convey the concept of the present invention to those skilled in the art. The same reference numerals in different drawings represent the same element.

FIG. 2 is block diagram of a semiconductor memory device 201 having a preamble function, according to a first exemplary embodiment of the present invention. Referring to FIG. 2 , the semiconductor memory device 201 includes a latency controller 211 , a data controller 221 , an output driver 231 , a preamble controller 241 , and a preamble unit 251 .

The latency controller 211 receives an internal clock signal (DLL CLK), a column address strobe (CAS) latency information signal (CLINF), and a read command (READ), and generates a latency signal (LAT). The read command (READ) is input to the latency controller 211 in synchronization with an external clock signal (ECLK). The CAS latency information signal (CLINF) is input to the latency controller 211 in synchronization with the internal clock signal (DLL CLK). The CAS latency information signal (CLINF) sets the length of the latency of the semiconductor memory device 201 to be, for example, CL (CAS Latency) 2 , CL 3 , and CL 4 .

The data controller 221 receives the latency signal (LAT), and internal data Dout output from memory cells (not shown) of the semiconductor memory device 201 . When the internal data Dout is input to the data controller 221 and the latency signal (LAT) is activated, the data controller 221 generates an output control signal D 1 . The output control signal D 1 may be a clock signal similar to the external clock signal (ECLK), and the data controller 221 may be a multiplexer.

The output driver 231 buffers the output control signal D 1 output from the data controller 221 and outputs the same to the outside of the semiconductor memory device 201 . The output driver 231 inverts the output control signal D 1 and outputs it as an output data strobe signal DQS output from the semiconductor memory device 201 . If the output control signal D 1 is deactivated, the output driver 231 maintains the output data strobe signal DQS at a high impedance status.

The preamble controller 241 outputs a preamble control signal P 1 in response to the read command (READ). That is, the preamble controller 241 activates the preamble control signal P 1 when the read command (READ) is activated. More specifically, the read command (READ) is input to the semiconductor memory device 201 in synchronization with a clock of the external clock signal (ECLK) applied to the semiconductor memory device 201 , and the preamble control signal P 1 is output from the preamble controller 241 in synchronization with a clock of the external clock signal (ECLK).

When the preamble control signal P 1 is activated, the preamble unit 251 is activated to change the output data strobe signal DQS from a high impedance status to a logic low level, thereby preambling the output data strobe signal DQS. The output data DQ is output to the outside of the semiconductor memory device 201 at an instant in time a preamble section, which corresponds to the preamble section tp, of the output data strobe signal DQS ends.

According to a first exemplary embodiment of the present invention, an output terminal of the output driver 231 is changed from a high impedance status to a logic low level in synchronization with the activation of the read command (READ), which is input to the semiconductor memory device 201 . Accordingly, the output data strobe signal DQS is preambled. That is, the read command (READ) is input to the semiconductor memory device 201 in synchronization with a clock of the external clock signal (ECLK) applied to the semiconductor memory device 201 . As a result, the preamble control signal P 1 changes the output data strobe signal DQS from a logic high level to a logic low level in synchronization with a clock of the external clock signal (ECLK) in which the read command (READ) is input, thereby preambling the output data strobe signal DQS.

Accordingly, since the output data strobe signal DQS is preambled prior to the activation of the latency signal (LAT), a preamble section of the output data strobe signal DQS may be secured sufficiently. Thus, the output data DQ may be stably output from the semiconductor memory device 201 .

FIG. 3 is a circuit diagram of the output driver 231 of FIG. 2 . Referring to FIG. 3 , the output driver 231 includes a pull-up unit 311 and a pull-down unit 321 .

The pull-up unit 311 is activated and outputs an output data strobe signal DQS to a logic high level when an output control signal D 1 is at a logic low level. When the output control signal D 1 is at logic high level, the pull-up unit 311 is deactivated and thus does not affect the output data strobe signal DQS. The pull-up unit 311 includes a PMOS transistor having a gate to which the output control signal D 1 is input. Although a PMOS transistor is illustrated as being used with this exemplary embodiment of the present invention, other types of transistors may also be used. For example, an MOS, NMOS, or the like, transistor may also be used if it is configured properly with the pull-up unit 311 .

The pull-down unit 321 is activated and outputs the output data strobe signal DQS to a logic low level when the output control signal D 1 is at a logic high level but is deactivated and does not affect the output data strobe signal DQS when the output control signal D 1 is at a logic low level. The pull-down unit 321 includes an NMOS transistor having a gate to which the output control signal D 1 is input. Although an NMOS transistor is illustrated as being used with this exemplary embodiment of the present invention, other types of transistors may also be used. For example, an MOS, PMOS, or the like, transistor may also be used if it is configured properly with the pull-down unit 321 .

FIG. 4 is a circuit diagram of the preamble unit 251 of FIG. 2 . Referring to FIG. 4 , the preamble unit 251 includes a pull-down transistor such as an NMOS transistor having a gate to which a preamble control signal P 1 is input. The preamble unit 251 is activated when the preamble control signal P 1 is at a logic high level and pulls down an output data strobe signal DQS to a logic low level, and is deactivated and does not affect the output data strobe signal DQS when the preamble control signal P 1 is at a logic low level.

FIG. 5 is a circuit diagram of the preamble controller 241 of FIG. 2 . Referring to FIG. 5 , the preamble controller 241 includes a transmission gate 511 , a latch unit 521 , a delayer 531 , a transmission gate controller 541 , an output controller 551 , and first and second reset units 561 and 571 .

The transmission gate 511 receives a read command (READ) and transmits it to the latch unit 521 . The transmission gate 511 is activated and transmits the read command (READ) to the latch unit 521 when a signal output from the transmission gate controller 541 is at a logic low level, and is deactivated and does not transmit the read command (READ) to the latch unit 521 when a signal output from the transmission gate controller 541 is at a logic high level.

The latch unit 521 latches the read command (READ) transmitted from the transmission gate 511 .

The delayer 531 delays a signal output from the latch unit 521 for a predetermined time. The predetermined time is adjustable according to the size of the delayer 531 . The preamble controller 241 may not include the delayer 531 , if desired.

The transmission gate controller 541 receives a signal output from the delayer 531 and an external control signal ACT 1 . The transmission gate controller 541 outputs a signal to a logic high level and activates the transmission gate 511 , only when the signal output from the delayer 531 is at a logic low level and the external control signal ACT 1 is at a logic high level.

The output controller 551 activates a preamble control signal P 1 to a logic high level if both the signal output from the delayer 531 and a signal output from the second reset unit 571 are at logic high levels.

The first reset unit 561 includes a NOR gate 563 and a PMOS transistor 565 . The first reset unit 561 outputs a power source voltage Vdd and resets the preamble control signal P 1 to a logic low level when one of a precharge signal PREC and a write signal WR is activated to a logic high level.

The second reset unit 571 resets the preamble control signal P 1 to a logic low level when a data output control signal Dout 1 is activated to a logic high level.

Hereinafter, the overall operations of the preamble controller 241 will be described with reference to FIG. 5 .

During the latency of the semiconductor memory device 201 , the read command (READ) is at a logic high level, and thus, the preamble control signal P 1 is maintained at a logic low level. However, when the read command (READ) and the external control signal ACT 1 are activated to a logic low level and a high level, respectively, the transmission gate 511 is activated to transmit the read command (READ) to the latch unit 521 . At this time, the data output control signal Dout 1 is at a logic low level, and therefore, the output controller 551 activates the preamble control signal P 1 to a logic high level. In this case, if at least one of the precharge signal PREC and the write signal WR is activated to a logic high level, a signal output from the first reset unit 561 is activated to a logic high level and the preamble control signal P 1 is deactivated to a logic low level. Also, when the data output control signal Dout 1 is activated to a logic high level, a signal output from the second reset unit 571 is deactivated to a logic low level and the preamble control signal P 1 is reset to a logic low level.

FIG. 6 is a timing diagram of the semiconductor memory device 201 of FIG. 2 having the preamble unit 251 that has a large pull-down transistor. As shown in FIG. 6 , in case that the preamble unit 251 has a large pull-down transistor, an output data strobe signal DQS is rapidly changed from a high impedance status to a logic low level at the moment a read command (READ) is activated. That is, a preamble section tp of the output data strobe signal DQS, which is output from the semiconductor memory device 201 , is sufficiently present. Therefore, the semiconductor memory device 201 may stably output the output data DQ even if the operational frequency of the semiconductor memory device 201 becomes high.

FIG. 7 is a timing diagram of the semiconductor memory device 201 having the preamble unit 251 of FIG. 2 that has a small pull-down transistor. As shown in FIG. 7 , if the preamble unit 251 has a small pull-down transistor, an output data strobe signal DQS is gradually changed from a high impedance status to a logic low level at the moment of activation of a read command (READ). In this case, a preamble section tp of the output data strobe signal DQS, which is output from the semiconductor memory device 201 , is shorter than that of the semiconductor memory device 201 of FIG. 2 having the preamble unit 251 that has a large pull-down transistor. Nevertheless, the preamble section tp is secured, and thus, the output data DQ may be stably output from the semiconductor memory device 201 without an error. This is achieved independently of the operational frequency of the semiconductor memory device 201 .

FIG. 8 is a block diagram of a semiconductor memory device 801 according to a second exemplary embodiment of the present invention. Referring to FIG. 8 , the semiconductor memory device 801 includes a latency controller 811 , a data controller 821 , an output driver 831 , a preamble controller 841 , and a logic unit 851 .

The latency controller 811 receives an internal clock signal (DLL CLK), a column address strobe (CAS) latency information signal (CLINF), and a read command (READ), and generates a latency signal (LAT). The read command (READ) is input to the latency controller 811 in synchronization with an external clock signal (ECLK). The CAS latency information signal (CLINF) is input to the latency controller 811 in synchronization with the internal clock signal (DLL CLK). The CAS latency information signal (CLINF) sets the length of the latency of the semiconductor memory device 201 to be, for example, CL 2 , CL 3 , and CL 4 .

The data controller 821 receives the latency signal (LAT), and internal data Dout output from memory cells (not shown) of the semiconductor memory device 801 , and generates an output control signal D 1 . When the internal data Dout is input to the data controller 821 and the latency signal (LAT) is activated, the data controller 821 activates the output control signal D 1 . The output control signal D 1 may be a clock signal similar to the external clock signal (ECLK), and the data controller 821 may be a multiplexer.

The preamble controller 841 generates a preamble control signal P 1 in response to the read command (READ). That is, the preamble controller 841 activates the preamble control signal P 1 when the read command (READ) is activated. In other words, the read command (READ) is input to the preamble controller 841 in synchronization with the external clock signal (ECLK) applied to the semiconductor memory device 801 , and the preamble control signal P 1 is generated by the preamble controller 841 in synchronization with a clock of the external clock signal (ECLK) to which the read command (READ) is input.

The logic unit 851 receives the preamble control signal P 1 and the output control signal D 1 . The logic unit 851 changes the output data strobe signal DQS from a high impedance status to a logic low level when the preamble control signal P 1 is activated, thereby preambling the output data strobe signal DQS output from the semiconductor memory device 801 . The output data DQ output from the semiconductor memory device 801 is output to the outside of the semiconductor memory device 801 at an instant of time a preamble section tp of the output data strobe signal DQS ends (shown in FIG. 11 ). The logic unit 851 outputs a signal output from the data controller 821 when the preamble control signal P 1 is at a logic low level.

The output driver 831 buffers the output control signal D 1 output from the data controller 821 and outputs the same external of the semiconductor memory device 801 . The output driver 831 inverts the output control signal D 1 and outputs it as an output data strobe signal DQS output from the semiconductor memory device 801 . If the output control signal D 1 is deactivated, the output driver 831 maintains the output data strobe signal DQS to have a high impedance status.

According to the second exemplary embodiment of the present invention, the output data strobe signal DQS output from the semiconductor memory device 801 is preambled at the moment the read command (READ) is activated. That is, the output data strobe signal DQS is preambled prior to the activation of the latency signal (LAT), thereby securing a preamble section of the output data strobe signal DQS. Thus, the output data DQ can be output stably from the semiconductor memory device 801 even if the operational frequency of the semiconductor memory device 801 is high.

FIG. 9 is a circuit diagram of the output driver 831 of FIG. 8 . Referring to FIG. 9 , the output driver 831 includes a pull-up unit 911 and a pull-down unit 921 .

The pull-up unit 911 is activated to output an output data strobe signal DQS to a logic high level when an output control signal D 1 is at a logic low level, and is inactivated and does not affect the output data strobe signal DQS when the data strobe signal D 1 is at a logic high level. The pull-up unit 911 includes a PMOS transistor having a gate to which the output control signal D 1 is input. Although a PMOS transistor is illustrated as being used with this exemplary embodiment of the present invention, other types of transistors may also be used. For example, an MOS, NMOS, or the like, transistor may also be used if it is configured properly with the pull-up unit 911 .

The pull-down unit 921 is activated to output an output data strobe signal DQS to a logic low level when a signal P 2 output from the logic unit 851 is at a logic high level, and is inactivated and does not affect the output data strobe signal DQS when the signal P 2 output from the logic unit 851 is at a logic low level. The pull-down unit 921 includes an NMOS transistor having a gate to which the signal P 2 output from the logic unit 851 is input. Although an NMOS transistor is illustrated as being used with this exemplary embodiment of the present invention, other types of transistors may also be used. For example, an MOS, PMOS, or the like, transistor may also be used if it is configured properly with the pull-up unit 911 .

FIG. 10 is a circuit diagram of the logic unit 851 of FIG. 8 . Referring to FIG. 10 , the logic unit 851 includes a NOR gate 1011 that receives an output control signal D 1 and a preamble control signal P 1 , and an inverter 1021 that inverts an output of the NOR gate 1011 . The logic unit 851 outputs an output signal P 2 to a high level when at least one of the output control signal D 1 and the preamble control signal P 1 is at a logic high level, and outputs the output signal P 2 to a low level when both the output control signal D 1 and the preamble control signal P 1 are at logic low levels. The NOR gate is used by way of example only. In particular, one of ordinary skill in the art is well aware that substitute logic circuits may be used to mimic the functionality of the NOR gate. For example, an OR gate may be used in conjunction with an inverter at the output thereof to produce the same logic results as a NOR gate.

FIG. 11 is a timing diagram of the semiconductor memory device of FIG. 8 . As shown in FIG. 11 , an output data strobe signal DQS is rapidly changed from a high impedance status to a logic low level at the moment of activation of a read command (READ). As a result, a preamble section tp of the output data strobe signal DQS can be sufficiently secured, and thus, output data DQ is output stably from the semiconductor memory device 801 even if the operational frequency of the semiconductor memory device 801 becomes high.

The structure and operations of the preamble controller 841 are the same as those of the preamble controller 241 shown in FIG. 5 , and therefore, descriptions thereof will be omitted.

The semiconductor memory devices 201 and 801 according to exemplary embodiments of the present invention may be any semiconductor memory devices having preamble functions.

As described above, according to exemplary embodiment of the present invention, it is possible to sufficiently secure preamble sections tp of output data strobe signals DQS output from the semiconductor memory devices 201 and 801 . Accordingly, output signals can be output stably from the semiconductor memory devices 201 and 801 irrespective of the operational frequencies of the semiconductor memory devices 201 and 801 .