SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

A method for forming a semiconductor device is provided. The method includes forming first bonding features and a first alignment mark including first patterns in a top die and forming second bonding features and a second alignment mark in a bottom wafer. The method also includes determining a first benchmark and a second benchmark. The method further includes aligning the top die with the bottom wafer using the first alignment mark and the second alignment mark. In a top view, at least two of the first patterns are oriented along a first direction, and at least two of the first patterns are oriented along a second direction that is different from the first direction. The top die is aligned with the bottom wafer by adjusting a virtual axis passing through the first benchmark and the second benchmark to be substantially parallel with the first direction.

BACKGROUND

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. The individual dies are typically packaged separately. A package not only provides protection for semiconductor devices from environmental contaminants, but also provides a connection interface for the semiconductor devices packaged therein.

Three dimensional integrated circuits (3DICs) are a recent development in semiconductor packaging in which multiple semiconductor dies are stacked upon one another, such as package-on-package (POP) and system-in-package (SiP) packaging techniques. Some 3DICs are prepared by placing dies over dies on a semiconductor wafer level. 3DICs provide improved integration density and other advantages, such as faster speeds and higher bandwidth, because of the decreased length of interconnects between the stacked dies, for example. However, there are many challenges related to 3DICs.

DETAILED DESCRIPTION

Further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range considering variations that inherently arise during manufacturing as understood by one of ordinary skill in the art. For example, the number or range of numbers encompasses a reasonable range including the number described, such as within ±10% of the number described, based on known manufacturing tolerances associated with manufacturing a feature having a characteristic associated with the number. For example, a material layer having a thickness of “about 5 nm” may encompass a dimension range from 4.25 nm to 5.75 nm where manufacturing tolerances associated with depositing the material layer are known to be ±15% by one of ordinary skill in the art. For avoidance of doubts, the X, Y and Z directions in figures of the present disclosure are perpendicular to one another.

Typically, when two or more semiconductor components are bonded together to form a semiconductor device, an alignment process for aligning such semiconductor components may be performed to improve the performance of the resulting semiconductor device. For example, bonding structures formed on respective semiconductor components may be aligned to increase bond strength between such semiconductor components. During the alignment process, one or more alignment mark formed in the semiconductor components may be used, and a recognition system may be used. The recognition system may include a capturing apparatus capturing the images of the semiconductor device and a recognition apparatus recognizing the one or more alignment marks, thereby determining bond accuracy. However, the existing alignment marks have some drawbacks, such as IR (infrared) distortion and shadow issues. Therefore, bond accuracy can be further enhanced. The present disclosure provides some different examples of alignment marks in a semiconductor device, which effectively enhance bond accuracy.

Please refer toFIG.1, which illustrates a top view of a semiconductor device50, in accordance with some embodiments. In the top view, the semiconductor device50includes a top die region100R of a top die100(details regarding the top die100are shown inFIG.2), a bottom wafer region200R of a bottom wafer200(details regarding the bottom wafer200are shown inFIG.3), and a seal ring structure region300R of a seal ring structure300(details regarding the seal ring structure300are shown inFIG.2) between the top die region100R and the bottom wafer region200R. In some embodiments, the seal ring structure region300R includes different corners. In some embodiments, the corners are trapezoid-shaped.

Next, please refer toFIG.2, which illustrates a cross-sectional view of the top die100of the semiconductor device50, in accordance with some embodiments. In some embodiments, the top die100includes active devices and possibly passive devices, which are represented as an integrated circuit device104. In some embodiments, the top die100is free from active devices, and may or may not include passive devices. In some embodiments, the top die100includes a substrate102and the features formed over the top surface of the substrate102. The substrate102may include crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and the like. The substrate102may also be a bulk semiconductor substrate or a Semiconductor-On-Insulator (SOI) substrate. Shallow Trench Isolation (STI) regions (not shown) may be formed in the substrate102to isolate the active regions in the substrate102. Although not shown, through-vias may (or may not) be formed to extend into the substrate102, and the through-vias are used for electrical connection.

The integrated circuit device104may be formed on the top surface of the substrate102. The integrated circuit device104may include Complementary Metal-Oxide Semiconductor (CMOS) transistors, resistors, capacitors, diodes, and the like. The details regarding the integrated circuit device104are not illustrated herein. In some embodiments, the top die100is used for forming interposers (which are free from active devices), and the substrate102may be a semiconductor substrate or a dielectric substrate.

An Inter-Layer Dielectric (ILD)106may be formed over the substrate102and fills the spaces between the gate stacks of transistors (not shown) in the integrated circuit device104. In some embodiments, the ILD106is formed of or includes Phospho Silicate Glass (PSG), Boro Silicate Glass (BSG), Boron-doped Phospho Silicate Glass (BPSG), Fluorine-doped Silicate Glass (FSG), silicon oxide, silicon nitride, silicon oxynitride (SiOxNy), low-k dielectric materials, and the like. The ILD106may be formed using spin coating, Chemical Vapor Deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Low Pressure Chemical Vapor Deposition (LPCVD), and the like.

A plurality of contact plugs108may be formed in the ILD106, and the contact plugs108are used for electrical connection, for example, the contact plugs108may be electrically connected to the integrated circuit device104. In some embodiments, the contact plugs108may include a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and/or multi-layers thereof. The formation of the contact plugs108may include forming contact openings in the ILD106, filling a conductive material(s) into the contact openings, and performing a planarization process (such as a Chemical Mechanical Polish (CMP) process or a mechanical grinding process) to level the top surfaces of the contact plugs108with the top surface of the ILD106.

A plurality of metal lines112and a plurality of vias114may be formed over the ILD106and the contact plugs108. Contact plugs and the overlying metal lines and vias are collectively referred to as an interconnect structure110. The metal lines112and the vias114may be formed in different dielectric layers116(may be referred to as Inter-metal Dielectrics (IMDs)). The metal lines112and the vias114may include copper or copper alloys, and they may also include other metals. In some embodiments, the dielectric layers116may include low-k dielectric materials. The dielectric constants (k values) of the low-k dielectric materials may be lower than about 3.0, for example. The dielectric layers116may include carbon-containing low-k dielectric materials, Hydrogen silsesquioxane (HSQ), Methylsilsesquioxane (MSQ), and the like. In some embodiments, the formation of the dielectric layers116includes depositing a porogen-containing dielectric material in the dielectric layers116and then performing a curing process to drive out the porogen, and hence the remaining the dielectric layers116are porous.

The formation of the metal lines112and the vias114in the dielectric layers116may include single damascene processes and/or dual damascene processes. In a single damascene process for forming a metal line or a via, a trench or a via opening is first formed in one of the dielectric layers116, followed by filling the trench or the via opening with a conductive material. A planarization process such as a CMP process is then performed to remove the excess portions of the conductive material higher than the top surface of the dielectric layer, leaving a metal line or a via in the corresponding trench or via opening. In a dual damascene process, both of a trench and a via opening may be formed in a dielectric layer, with the via opening underlying and connected to the trench. Conductive materials are then filled into the trench and the via opening to form a metal line and a via, respectively. The conductive materials may include a diffusion barrier layer and a copper-containing metallic material over the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, and the like.

For ease of illustration, the topmost dielectric layer of the dielectric layers116is denoted as a top dielectric layer116T. The metal lines in the top dielectric layer116T are denoted as top metal lines112T. The topmost vias114in the top dielectric layer116T are denoted as top vias114T. In some embodiments, the top surface of top dielectric layer116T and the top surface of the metal lines112T are on the same plane. In some embodiments, the top surface of the top dielectric layer116T and the top surface of the metal lines112T are not on the same plane.

A first alignment mark118may be formed in the top dielectric layer116T. For example, a sacrificial layer may be deposited over the top dielectric layer116T, and the sacrificial layer may be patterned to form openings. The openings may be filled with an alignment mark material to form the first alignment mark118. In some embodiments, the alignment mark material includes a conductive material, such as copper, tungsten, gold, silver, aluminum, lead, tin, tantalum, and the like. In some embodiments, the alignment mark material includes an insulating material, such as polybenzoxazole (PBO), polyimide (PI), an epoxy, and the like. In some embodiments, the first alignment mark118does not overlap the metal lines112and the vias114vertically.

A first bonding structure120is formed over the top dielectric layer116T, the top metal lines112T, and the top vias114T. The first bonding structure120includes a plurality of first bonding features122embedded in a first insulating layer124. The first bonding features122may include conductive materials, such as tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and other applicable materials. In some embodiments, the first insulating layer124may include inorganic dielectric material materials, such as silicon nitride (SiNx), silicon oxide (SiO2), silicon oxy-nitride (SiONx), silicon oxy-carbide (SiOCx), and the like, combinations thereof, and/or multi-layers thereof. In some embodiments, the first insulating layer124may include polymer materials, such as benzocyclobutene (BCB) polymer, polyimide (PI), or polybenzoxazole (PBO).

As shown inFIG.2, the top die100may include a seal ring structure300. In some embodiments, in the top view, the seal ring structure300is formed as a full ring (without breaks therein) surrounding the first bonding features122. In some embodiments, in the top view, the seal ring structure300encloses the first bonding features122. The seal ring structure300may prevent semiconductor components in the top die100from being damaged due to mist ingress or stress. For example, multi-gate components, such as fin-like field effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors may be more prone to damages, and an adequate seal ring structure300may be required.

The seal ring structure300may include a plurality of contact plugs308SR, a plurality of metal lines312SR, and a plurality of vias314SR. The contact plugs308SR, the metal lines312SR, and the vias314SR may be formed at the same time and share the same formation processes as the respective contact plugs108, metal lines112, and vias114. Each of the contact plugs308SR, metal lines312SR, and vias314SR in seal ring structure300may be physically joined with the overlying and underlying ones of these features to form an integrated seal ring. In some embodiments, the seal ring structure300may be a single-layer structure. For example, the seal ring structure300may be formed in the top dielectric layer116T and not be formed in the rest dielectric layers116.

In some embodiments, the contact plugs308SR are electrically connected to the substrate102. There may be (or may not be) silicide regions between and physically joining contact plugs308SR and the substrate102. In some embodiments, the contact plugs308SR are in physical contact with the substrate102. In some embodiments, the contact plugs308SR are spaced apart from the substrate102by a dielectric layer, such as the ILD106, and the like.

Please refer toFIG.3, which illustrates a cross-sectional view of the bottom wafer200of the semiconductor device50, in accordance with some embodiments. The bottom wafer200may include various semiconductor structures, such as active regions, gate structures disposed over channel regions of the active regions, source/drain features disposed over source/drain regions of the active regions, source/drain contacts disposed over source/drain features, and gate contact vias disposed over the gate structures. The active regions may include silicon (Si) or a suitable semiconductor material. Each of the segmented gate structures includes a gate dielectric layer and a gate electrode layer over the gate dielectric layer. In some embodiments, the gate dielectric layer includes an interfacial layer and a high-k gate dielectric layer. The interfacial layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method. The high-k dielectric materials, as used and described herein, include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The high-k gate dielectric layer may include hafnium oxide. Alternatively, the high-k gate dielectric layer may include other high-k dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3(STO), BaTiO3(BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3(BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, and the like. The high-k gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and the like.

The gate electrode layer of the segmented gate structures may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy or a metal silicide. By way of example, the gate electrode layer may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials or a combination thereof. In various embodiments, the gate electrode layer may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process.

Source/drain features may include silicon (Si) doped with an n-type dopant, such as phosphorus (P) or arsenic (As) or silicon germanium (SiGe) doped with a p-type dopant, such as boron (B) or boron difluoride (BF2). The sourced/drain contacts may include a barrier layer, a silicide layer, and a metal filler layer disposed over the silicide layer. The barrier layer may include titanium nitride or tantalum nitride. The silicide layer may include titanium silicide, tantalum silicide, cobalt silicide, nickel silicide, or tungsten silicide. The silicide layer interfaces the source/drain features to reduce contact resistance. The metal fill layer may include ruthenium (Ru), copper (Cu), nickel (Ni), cobalt (Co), or tungsten (W).

For ease of illustration,FIG.3is simplified, and only some components in the bottom wafer200are illustrated. In particular, the bottom wafer200may include a second alignment mark218, a third alignment mark219, and a second bonding structure220. The second bonding structure220includes a plurality of second bonding features222embedded in a second insulating layer224. The formation and materials of the second alignment mark218and the third alignment mark219may be similar to those of the first alignment mark118. In addition, the formation and materials of the second bonding structure220(i.e. the second bonding features222and the second insulating layer224) may be similar to those of the first bonding structure120(i.e. the first bonding features122and the first insulating layer124). The bottom wafer200may also include interconnect structures including metal lines and vias formed in different dielectric layers. The related description is not repeated.

Next, please refer toFIG.4andFIG.5.FIG.4illustrates a cross-sectional view of the semiconductor device50, in accordance with some embodiments.FIG.5illustrates an enlarged top view of a portion of the semiconductor device50illustrated inFIG.4, in accordance with some embodiments. The top die100may be flipped upside down and then bonded to the bottom wafer200to form the semiconductor device50. In some embodiments, keep-out zones130in which no first bonding features122and second bonding features222are formed may be formed in the top die100and the bottom wafer200. Similarly, keep-out zones230in which no second bonding features222are formed may be formed in the bottom wafer200. That is, in the keep-out zones130,230, none of the first alignment mark118, the second alignment mark218, and the third alignment mark219overlaps any bonding features vertically.

When the top die100is attached to bottom wafer200, an alignment process for aligning the top die100and the bottom wafer200may be performed, so the performance of the resulting semiconductor device50may be improved. For example, the top die100may be aligned with the bottom wafer200in the first direction D1and/or the second direction D2. The second direction D2is different from the first direction D1. In some embodiments, the second direction D2is substantially perpendicular to the first direction D1. For example, the first direction D1may be parallel with the X-direction shown inFIG.5, and the second direction may be parallel with the Y-direction shown inFIG.5.

During the alignment, the first alignment mark118in the top die100, the second alignment mark218in the bottom wafer200, and the third alignment mark219in the bottom wafer200may be used to ensure that the top die100is aligned with the bottom wafer200. For example, the alignment process may ensure each of the first bonding features122is aligned with, and in contact with, the corresponding second bonding feature222, thereby increasing bond strength between the top die100and the bottom wafer200. Furthermore, a recognition system may be used to recognize the first alignment mark118, the second alignment mark218and/or the third alignment mark219. By recognizing the positional relationship between the first alignment mark118and the second alignment mark218and/or the positional relationship between the first alignment mark118and the third alignment mark219, bond accuracy may be determined and improved.

In some embodiments, in the top view, the first alignment mark118, the second alignment mark218, and the third alignment mark219all include a plurality of patterns. Due to the patterns of the alignment mark, it may be easier for the recognition system to recognize the alignment mark, thereby improving bond accuracy. For example, since multiple patterns may include more edges than a single pattern, it may be easier for the recognition system to recognize the periphery of the patterns. In the embodiments illustrated inFIG.5, the first alignment mark118includes four first patterns1181-1184, the second alignment mark218includes four second patterns2181-2184, and the third alignment mark219includes four third patterns2191-2194. However, the number, the shape, the configurations of the patterns may vary according to actual needs.

In some embodiments, a first benchmark118BM of the first patterns1181-1184of the first alignment mark118, a second benchmark218BM of the second patterns2181-2184of the second alignment mark218, and a third benchmark219BM of the third patterns2191-2194of the third alignment mark219may be determined. It should be noted that the benchmark of the patterns of the alignment mark may be arbitrarily determined. For example, the benchmark of the patterns of the alignment mark may be the central point of the entire alignment mark. Alternatively, the benchmark of the patterns of the alignment mark may be the central point of any patterns of the alignment mark, but the position of the benchmark is not limited thereto.

The top die100may be aligned with the bottom wafer200by adjusting the virtual axis VA1passing through the first benchmark118BM and the second benchmark218BM to be substantially parallel with the first direction D1and/or adjusting the virtual axis VA2passing through the first benchmark118BM and the third benchmark219BM to be substantially parallel with the second direction D2. In detail, if the top die100and the bottom wafer200are misaligned, the virtual axis VA1may not be parallel with the first direction D1and/or the virtual axis VA2may not be parallel with the second direction D2. By adjusting the positions of the top die100and/or the bottom wafer200to make the virtual axis VA1parallel with the first direction D1and the virtual axis VA2parallel with the second direction D2, the top die100may be aligned with the bottom wafer200.

In some embodiments, in the top view, each first pattern1181-1184may be square-like. For ease of illustration, the first patterns1181-1184are referred to as a first square1181, a second square1182, a third square1183, and a fourth square1184. The first square1181and the second square1182are oriented along the first direction D1. The third square1183and the fourth square1184are also oriented along the first direction D1. The first square1181and the third square1183are oriented along the second direction D2. The second square1182and the fourth square1184are also oriented along the second direction D2.

Examples of different configurations of an alignment mark can also be found inFIG.6AtoFIG.6C.FIG.6AtoFIG.6Cillustrate different configurations of an alignment mark, in accordance with some embodiments. For ease of illustration, the alignment mark is denoted as the first alignment mark118, but the configurations may also be applied to the second alignment mark218and the third alignment mark219. In the top view, at least two patterns are oriented along the same direction (e.g. the first direction D1), and at least two patterns are oriented along another direction (e,g, the second direction D2). In some embodiments, for each alignment mark, the shape of each pattern may be substantially the same. In addition, in some embodiments, for each alignment mark, the size of each pattern may also be substantially the same. Furthermore, the patterns may be arranged in different ways.

For example, as shown inFIG.6A, each pattern may be quadrilateral and the multiple patterns may be arranged in a way that the entire alignment mark also seems like a quadrilateral. For example, as shown inFIG.6BandFIG.6C, each pattern may be quadrilateral and the multiple patterns may be arranged in a way that the entire alignment mark seems like an irregular polygon. The configurations of the patterns of the alignment mark and the arrangements of different alignment marks are not limited thereto. Any circumstances in which the virtual axis passing through benchmarks of alignment marks may be adjusted to be parallel with a direction along which at least two patterns are oriented fall within the scope of the present disclosure.

Please refer back toFIG.6A. In some embodiments, the distance118D between any two adjacent first patterns1181-1184is substantially the same. In some embodiments, the distance118D is in a range from about 1.5 μm to 4.5 μm, such as 2.0 μm to 4.0 μm, but the distance118D is not limited thereto. In some embodiments, the width118W of each pattern1181-1184is substantially the same. In some embodiments, the width118W is in a range from about 6.0 μm to about 20.0 μm, such as 9.0 μm to 12.0 μm, but the width118W is not limited thereto. If the distance118D is greater than 4.5 μm and/or the width118W is greater than 20.0 μm, the area that the entire first alignment mark118occupied in the top die100may be too big, and fewer components can be integrated into the top die100. If the distance118D is less than 1.5 μm and/or the width118W is less than 6.0 μm, it's difficult for the recognition system to recognize the first alignment mark118. In some embodiments, the distance118D between two adjacent patterns1181-1184of the first alignment mark118is less than the width118W of each pattern1181-1184of the first alignment mark118.

After the alignment is performed, the top die100may be bonded to the bottom wafer200by heating the top die100and the bottom wafer200to a certain range of temperature and/or a certain range of pressure, so the first bonding features122and the second bonding features222are bonded together, and/or the first insulating layer124and the second insulating layer224are bonded together. In some embodiments, such bonding may provide both covalent bonds (non-metal to non-metal) and metallic bonds (metal to metal), so the top die100and the bottom wafer200may bond together in a more stable way. In other words, the top die100may be attached to the bottom wafer200via the first bonding features122and the second bonding features222.

Next, please refer toFIG.7.FIG.7illustrates an enlarged top view of the configuration of the first alignment mark118and the first bonding features122, in accordance with some embodiments. InFIG.7, some of the dashed lines are used to distinguish quadrilateral portions118P1and L-shaped portions118P2of the first alignment mark118. In some embodiments, the first bonding features122overlap the quadrilateral portions118P1of the first patterns1181-1184of the first alignment mark118vertically without overlapping the L-shaped portions118P2of the first patterns1181-1184of the first alignment mark118vertically. In addition, in the top view, two horizontally-adjacent L-shaped portions118P2are substantially symmetrical relative to the virtual axis VA3. The virtual axis VA3is between two horizontally-adjacent L-shaped portions118P2and substantially perpendicular to the first direction D1. Similarly, in the top view, two vertically-adjacent L-shaped portions118P2are substantially symmetrical relative to the virtual axis VA4. The virtual axis VA4is between two vertically-adjacent L-shaped portions118P2and substantially perpendicular to the second direction D2.

The edges of the L-shaped portions118P2may be the edges of the alignment mark118. In some embodiments, a surrounding portion118P3in which no first bonding features122are formed may be further formed around the L-shaped portions118P2. In some embodiments, the size118P2S1of the L-shaped portions118P2in the first direction D1is in a range from about 0.5 μm to 2.0 μm, such as 1.0 μm, but the size118P2S1is not limited thereto. In some embodiments, the size118P2S2of the L-shaped portions118P2in the second direction D2is in a range from about 0.5 μm to 2.0 μm, such as 1.0 μm, but the size118P2S2is not limited thereto. In some embodiments, the size118P2S1is substantially the same as the size118P2S2.

In some embodiments, the distance118D2between the outer edge of the L-shaped portions118P2and the outer edge of the surrounding portion118P3is in a range from about 0.5 μm to 2.0 μm, such as 1.0 μm, but the distance118D2is not limited thereto. In some embodiments, the distance118D2is substantially the same as the size118P2S1and the size118P2S2. The L-shaped portions118P2and the surrounding portion118P3may be part of the keep-out zones130(denoted inFIG.4). Due to the keep-out zones130(including but not limited to the L-shaped portions118P2and the surrounding portion118P3) that do not overlap the first bonding features122vertically and/or the symmetrical arrangement of the L-shaped portions118P2, IR distortion and shadow issues caused by the first bonding features122may be reduced, and noise generated during image processing may also be reduced. Therefore, the image quality captured by the recognition system may be enhanced.

Next, please refer toFIG.8, which illustrates an enlarged top view of another semiconductor device350, in accordance with some embodiments. In the top view, the semiconductor device350includes a top die region400R of a top die, a bottom wafer region500R of a bottom wafer, and a seal ring structure region600R of a seal ring structure between the top die region400R and the bottom wafer region500R. In this embodiment, a first alignment mark418is formed in the seal ring region600R. In other words, the first alignment mark418at least partially overlapping the seal ring structure without overlapping a plurality of first bonding structures422in the top die. Since the first alignment mark418is formed in the seal ring region600R, more components may be integrated into the top die, thereby enhancing the performance of the semiconductor device350. A second alignment mark518and a third alignment mark519are formed in the bottom wafer. It should be noted that the positions of the second alignment mark518and the third alignment mark519are changed correspondingly.

Next, please refer toFIG.9AtoFIG.9C, which illustrate enlarged top views of another semiconductor device650, in accordance with some embodiments. In the top view, the semiconductor device650includes a top die region700R of a top die, a bottom wafer region800R of a bottom wafer, and a seal ring structure region900R of a seal ring structure between the top die region700R and the bottom wafer region800R. In this embodiment, a first alignment mark718having four first patterns7181-7184(may be referred to as a first square7181, a second square7182, a third square7183, a fourth square7184) is formed in the top die region700R.

The shape and the arrangement of the first patterns7181-7184inFIG.9AtoFIG.9Cmay be substantially the same as those of the first patterns1181-1184illustrated inFIG.6AtoFIG.6C, respectively. InFIG.9A, the first square7181and the second square7182are oriented along the first direction D1. The third square7183and the fourth square7184are also oriented along the first direction D1. The first square7181and the third square7183are oriented along the second direction D2. The second square7182and the fourth square7184are also oriented along the second direction D2. InFIG.9B, the first square7181and the second square7182are oriented along the first direction D1. The third square7183and the fourth square7184are also oriented along the first direction D1. The second square7182and the third square7183are oriented along the second direction D2, while the first square7181and the fourth square7184are misaligned in both the first direction D1and the second direction D2. InFIG.9C, the first square7181and the third square7183are oriented along the second direction D2. The second square7182and the fourth square7184are also oriented along the second direction D2. The first square7181and the fourth square7184are oriented along the first direction D1, while the second square7182and the third square7183are misaligned in both the first direction D1and the second direction D2. In addition, a first benchmark718BM is set as the central point of the entire first alignment mark718.

A second alignment mark818including a plurality of second patterns and a third alignment mark819including a plurality of third patterns are formed in the bottom wafer region800R. A second benchmark818BM of the second patterns of the second alignment mark818and a third benchmark819BM of the third patterns of the third alignment mark819may be determined. For example, the second benchmark818BM is set as the central point of the entire second alignment mark818, and the third benchmark819BM is set as the central point of the entire third alignment mark819.

In this embodiment, a fourth alignment mark838is also formed in the bottom wafer region800R. The fourth alignment mark838includes a plurality of fourth patterns8381-8384(may be referred to as a first square8381, a second square8382, a third square8383, a fourth square8384)). The fourth patterns8381-8384are arranged in a way that the first patterns7181-7184are arranged.

InFIG.9A, the first square8381and the second square8382are oriented along the first direction D1. The third square8383and the fourth square8384are also oriented along the first direction D1. The first square8381and the third square8383are oriented along the second direction D2. The second square8382and the fourth square8384are also oriented along the second direction D2. InFIG.9B, the first square8381and the second square8382are oriented along the first direction D1. The third square8383and the fourth square8384are also oriented along the first direction D1. The second square8382and the third square8383are oriented along the second direction D2, while the first square8381and the fourth square8384are misaligned in both the first direction D1and the second direction D2. InFIG.9C, the first square8381and the third square8383are oriented along the second direction D2. The second square8382and the fourth square8384are also oriented along the second direction D2. The first square8381and the fourth square8384are oriented along the first direction D1, while the second square8382and the third square8383are misaligned in both the first direction D1and the second direction D2. In addition, a fourth benchmark838BM is set as the central point of the entire fourth alignment mark838. The fourth alignment mark838may be used to know how IR distortion and shadow issues affect the captured images, and thus the fourth alignment mark838may be referred to as “a calibration alignment mark.”

During the alignment, a first-direction deviation devX and/or a second-direction deviation devY may be calculated to know how IR distortion and shadow issues affect the captured images and then determine the real deviation/misalignment between the top die and the bottom wafer. That is, the first-direction deviation devX and the second-direction deviation devY may represent the overlay (OVL) deviation caused by IR distortion and shadow issues in the X-direction and in the Y-direction, respectively. Furthermore, bond accuracy can be determined based on the first-direction deviation devX and the second-direction deviation devY.

For ease of illustration, different coordinates (xa, ya), (xb, yb), (xc, yc), (xd, yd), (xf, yf), (xg, yg), (xi, yi), (xj, yj), (xk, yk), (xl, yl) are denoted inFIG.9AtoFIG.9C. Corners of the first patterns7181-7184may be set as (xa, ya), (xb, yb), (xc, yc), (xd, yd). The central point of the second alignment mark818(i.e., the second benchmark818BM) may be set as (xf, yf). The central point of the third alignment mark819(i.e., the third benchmark819BM) may be set as (xg, yg). Corners of the fourth patterns8381-8384may be set as (xi, yi), (xj, yj), (xk, yk), (xl, yl). In this embodiment, the first-direction deviation devX and/or the second-direction deviation devY may be used to know real bond accuracy in the X-direction (trueX) and real bond accuracy in the Y-direction (true Y). The real bond accuracy in the X-direction trueX and the real bond accuracy in the Y-direction (true Y) can be described by the following equations:

If the first-direction deviation devX and the second-direction deviation devY approach zero, IR distortion and shadow issues may be resolved. In short, due to the fourth alignment mark838, IR distortion and shadow issues may be reduced, and real bond accuracy of the top die and the bottom wafer in the first direction and the second direction can be known. In some embodiments, a correction term may be added to the equations because of different reasons, such as the selected coordinates. Also, the correction term may be determined in advance.

Furthermore, in some embodiments, a seal ring alignment mark918may be formed in the seal ring structure region900R and one or more additional alignment marks858corresponding to the seal ring alignment mark918may be formed in the bottom wafer region800R. The seal ring alignment mark918and the additional alignment marks858may be used to help determine and improve bond accuracy. In some embodiments, the shape of the first alignment mark718is different from the shape of the seal ring alignment mark918. For example, the seal ring alignment mark918may be L-shaped or cross-shaped. In some embodiments, the shape of the first alignment mark718is different from the shape of the additional alignment marks858. For example, the additional alignment marks858may be two-concentric-square-like. In some embodiment, the shape and the arrangement of the seal ring alignment mark918may be substantially the same as those of the first alignment mark718illustrated inFIG.9AtoFIG.9C.

Please refer toFIG.10, which illustrates a flow chart of a method1000for forming a semiconductor device, in accordance with some embodiments. In the operation1010, the method1000includes forming a plurality of first bonding features in a top die. In the operation1020, the method1000includes forming a first alignment mark including a plurality of first patterns in the top die. In the operation1030, the method1000includes determining a first benchmark of the first patterns of the first alignment mark. In the operation1040, the method includes forming a plurality of second bonding features in a bottom wafer. In the operation1050, the method1000includes forming a second alignment mark including a plurality of second patterns in the bottom wafer. In the operation1060, the method1000includes determining a second benchmark of the second patterns of the second alignment mark.

In the operation1070, the method1000includes attaching the top die to the bottom wafer via the first bonding features and the second bonding features. In the operation1080, the method1000includes aligning the top die with the bottom wafer using the first alignment mark and the second alignment mark by adjusting a virtual axis passing through the first benchmark and the second benchmark to be substantially parallel with a first direction along which at least two of the first patterns are oriented.

The present disclosure provides some different examples of alignment marks in a semiconductor device, which effectively enhance bond accuracy. The alignment mark includes a plurality of patterns, with at least two of them oriented along a first direction and at least two of them oriented along a second direction different from the first direction. In some embodiments, the patterns are squares. Different benchmarks of different alignment marks may be determined, and the virtual lines passing through the benchmarks may be adjusted to be parallel with the first direction and the second direction, thereby aligning the top die with the bottom wafer. In addition, due to the keep-out zones that do not overlap bonding features vertically, IR distortion and shadow issues caused by the bonding features may be reduced, and noise generated during image processing may also be reduced. Therefore, the image quality captured by the recognition system may be enhanced. In some embodiments, a calibration alignment mark may also be used to reduce IR distortion and shadow issues. In some embodiments, the alignment mark may overlap the seal ring structure vertically, allowing more components to be integrated into the top die. In some embodiments, a seal ring alignment mark may be added to help determine and improve bond accuracy.

Some embodiments of the present disclosure provide a method for forming a semiconductor device. The method includes forming a plurality of first bonding features in a top die, forming a first alignment mark including a plurality of first patterns in the top die, and determining a first benchmark of the first patterns of the first alignment mark. The method also includes forming a plurality of second bonding features in a bottom wafer, forming a second alignment mark including a plurality of second patterns in the bottom wafer, and determining a second benchmark of the second patterns of the second alignment mark. The method further includes attaching the top die to the bottom wafer via the first bonding features and the second bonding features and aligning the top die with the bottom wafer using the first alignment mark and the second alignment mark. In a top view, at least two of the first patterns are oriented along a first direction, at least two of the first patterns are oriented along a second direction that is different from the first direction, and the top die is aligned with the bottom wafer by adjusting a virtual axis passing through the first benchmark and the second benchmark to be substantially parallel with the first direction.

Some embodiments of the present disclosure provide a method for forming a semiconductor device. The method includes forming a seal ring structure, a plurality of first bonding features, and a first alignment mark at least partially overlapping the seal ring structure without overlapping the first bonding structures in a top die. The method also includes forming a plurality of second bonding features and a second alignment mark in a bottom wafer. The method further includes attaching the top die to the bottom wafer via the first bonding features and the second bonding features and aligning the top die with the bottom wafer using the first alignment mark and the second alignment mark. In a top view, the first alignment mark includes four patterns, and a shape of each of the patterns of the first alignment mark is substantially the same.

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a top die including a plurality of first bonding features and a first alignment mark including a plurality of patterns. The semiconductor device includes bottom wafer including a plurality of second bonding features in contact with the first bonding features. In a top view, a distance between two adjacent of the patterns of the first alignment mark is less than a width of each of the patterns of the first alignment mark.

Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.