Image processing device

An image processing device improves processing performance at low cost. The image processing device is provided with a memory controller that divides up and assigns banks accessed by a video inputter, a drawer, and a video outputter to multiple frame memories. The image processing device arbitrates access requests from master units, such as the video inputter, the drawer, and the video outputter, and controls data transmission so that the multiple master units can access both the frame memories in parallel.

TECHNICAL FIELD

The present invention relates to an image processing apparatus that displays video input images and graphics superimposed on each other.

BACKGROUND ART

In recent years, there are a growing number of systems that display a plurality of images superimposed on each other. In the case of a car-mounted display in particular, various images such as an air-conditioner operation screen, car navigation screen, DVD (Digital Versatile Disk) or TV images need to be displayed superimposed on each other.

Conventionally, as a method for displaying a plurality of images superimposed on each other, there is a proposal of a method having a plurality of video input images, drawings and frame memories corresponding thereto (e.g., see Patent Literature 1).

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

However, such a conventional image processing apparatus has the following problems.

(1) Having frame memories corresponding to a plurality of video input images and graphics results in a cost increase.

(2) If each memory has a double buffering region and is a general single port memory, a memory write operation and a memory read operation contend each other, deteriorating processing performance.

The present invention has been made in view of the above described problems, and it is therefore an object of the present invention to provide an image processing apparatus capable of improving processing performance at low cost.

Solution to Problem

The image processing apparatus of the present invention adopts a configuration provided with a plurality of frame memories, a plurality of master sections that access the plurality of frame memories, a memory controller section that arbitrates between access requests from the plurality of master sections and controls data transfers so that the plurality of master sections can access the respective frame memories in parallel, a video input section that writes image input data to the plurality of frame memories via the memory controller section, and a video output section that reads the data stored in the plurality of frame memories through the memory controller section and displays the data on a display, wherein the memory controller section divides and allocates a plurality of banks accessed by the video input section and the video output section between/to the plurality of frame memories, and the video output section reads the last bank to which the video input section completed a write.

Advantageous Effects of Invention

According to the present invention, providing a memory controller section that controls data transfer so as to be accessible to a plurality of master sections in parallel, eliminates the necessity to have frame memories corresponding to respective video input images and drawings, can perform access to frame memories for video input, drawing and display in parallel, and can thereby improve processing performance at low cost.

DESCRIPTION OF EMBODIMENTS

FIG. 1is a block diagram illustrating a configuration of an image processing apparatus according to Embodiment 1 of the present invention. The present embodiment is an example where the present invention is applied to an image processing apparatus that displays video input images and graphics superimposed on each other.

InFIG. 1, image processing apparatus100is comprised of system memory110, frame memory120, frame memory130, video input section140, drawing section150, video output section160, display170, control section180and memory controller section190Furthermore, camera210, DVD211and TV212are connected to video input section140via video selection section213. Video selection section213selects an image signal outputted from camera210, DVD211or TV212.

System memory110stores application programs such as control of video input/output and drawing control, and texture data used for drawing. A ROM or flash memory is used as system memory110, but a RAM such as SRAM or DRAM may also be used.

Frame memories120and130store video input images, drawing data and calculation results. A DRAM is generally used for frame memories120and130, but an SRAM, flash memory or hard disk may also be used. Furthermore, both frame memory120and frame memory130may be incorporated in a system LSI or one or both of the two may also be configured as external circuitry.

Video input section140writes video input data to frame memories120and130via memory controller section190. Video input section140receives a video signal selected by video selection section213and video input section140writes video data to frame memory120or frame memory130via memory controller section190based on a vertical synchronization signal and a horizontal synchronization signal of the inputted video.

Camera210, DVD211and TV212are merely taken as examples of blocks that output a video signal, and may also output other video signals.

Drawing section150reads texture data stored in system memory110via memory controller section190and writes drawing data resulting from applying texture mapping or alpha blending processing to graphics such as a line, triangle and rectangle based on a command from control section180to frame memory120or frame memory130via memory controller section190. The internal configuration of drawing section150will be described later inFIG. 2.

A data bus to access system memory110and a data bus to access frame memory120or frame memory130may be independent of each other or shared.

Video output section160reads data stored in frame memories120and130via memory controller section190and displays the data on display170. Video output section160reads image data stored in frame memory120or frame memory130via memory controller section190, applies layer synthesis or image quality adjustment processing and then displays the data on display170.

Video input section140and video output section160above divide and allocate a plurality of banks accessed between/to a plurality of frame memories120and130and video output section160above reads the last bank to which video input section140completed a write.

Control section180controls video input section140, drawing section150, video output section160and memory controller section190based on the application program stored in system memory110. Furthermore, control section180writes calculation results such as JPEG decoding to frame memory120or frame memory130via memory controller section190. To be more specific, control section180writes the calculation results to frame memories120and130which are in a non-access state based on memory access start/end timing of video input section140and video output section160and information as to which of frame memories120and130is being accessed.

Memory controller section190arbitrates between access requests from blocks (master sections) that access frame memories120and130and control data transfers so that a plurality of master sections can access respective frame memories120and130in parallel. Here, memory controller section190arbitrates between memory access requests from master sections such as video input section140, drawing section150, video output section160and control section180and controls data transfers so that the plurality of master sections can access system memory110, frame memory120and frame memory130in parallel.

For example, when control section180requests access to system memory110, video input section140requests access to frame memory120, drawing section150requests access to frame memory130and video output section160requests access to frame memory130, memory controller section190performs control so that data transfers between control section180and system memory110, between video input section140and frame memory120, and between video output section160and frame memory130are performed in parallel. Thus, data transfer of drawing section150is started after the data transfer of video output section160is finished.

On that basis, when each master section determines which bank to access next, memory controller section190selects a bank allocated to the frame memory having the least factor to be accessed based on the situation of access of each master section to each frame memory120or130.

Memory controller section190divides and allocates a plurality of banks accessed by drawing section150and video output section160between/to the plurality of frame memories120and130, and when drawing section150determines which bank to access next, memory controller section190selects a bank allocated to frame memory120or130having the least factor to be accessed based on information about which of frame memories120and130video input section140and video output section160are accessing or which of frame memories120and130input section140and video output section160will access next when they are accessing none of frame memories120and130, and information about the bank to which drawing section150completed access last time.

FIG. 2is a diagram illustrating an internal configuration of drawing section150above.

InFIG. 2, drawing section150is comprised of a plurality of texture memories151and152, texture load section153and pixel generation section154.

Texture memories151and152are memories for storing texture data.

Texture load section153reads texture data stored in system memory110via memory controller section190and writes the texture data to one of texture memory151and texture memory152.

Pixel generation section154reads texture data stored in texture memory151or texture memory152and writes drawing data generated by applying texture mapping or alpha blending processing to graphics such as a line, triangle or rectangle to frame memory120or frame memory130via memory controller section190.

At the same time as pixel generation section154writes drawing data to frame memories120and130, texture load section153reads texture data of the next graphics from frame memories120and130.

Furthermore, in the present embodiment, after the texture data is transferred from system memory110to frame memories120and130, drawing section150reads texture data from frame memories120and130.

Drawing section150reads video data written by video input section140to frame memories120and130as texture data.

Texture load section153and pixel generation section154perform data transfers to/from memory controller section190in parallel. For this reason, data buses through which texture load section153and pixel generation section154access memory controller section190need to be independent of each other.

Hereinafter, operation of image processing apparatus100configured as described above will be described.

FIG. 3is a diagram illustrating a valid data region and a blanking region of a video input of video input section140.

Horizontal synchronization signal VIHSYNC is inputted to video input section140in a cycle of period VIHC.

Vertical synchronization signal VIVSYNC is inputted to video input section140in a cycle of period VIVC.

Using a fall of VIHSYNC as a reference, a period from the number of cycles VIHDS to VIHDE at video input clock VICLK (not shown) is a valid data region in the horizontal direction, and using a fall of VIVSYNC as a reference, a period from the number of horizontal lines VIVDS to VIVDE is a valid data region in the vertical direction.

In the case of WVGA (800 pixels (W)×480 pixels (H)), a frequency of 33 MHz is used for VICLK. On the other hand, the frequency for VICLK varies depending on the total number of pixels.

FIG. 4is a timing chart illustrating processing timing of video input section140.

InFIG. 4, a period from VIVDS to VIVDE is a vertical processing period and a period from VIHDS to VIHDE is a horizontal processing period. Video input section140writes video data to frame memory120or frame memory130via memory controller section190during the horizontal processing period. Furthermore, video input section140outputs a flag to control section180at timings of VIVDS, VIVDE, VIHDS and VIHDE.

FIG. 5is a diagram illustrating a valid display region and a blanking region of video output of video output section160.

Horizontal synchronization signal VOHSYNC is outputted from video output section160and inputted to display170in a cycle of period VOHC.

Vertical synchronization signal VOVSYNC is outputted from video output section160and inputted to display170in a cycle of period VOVC.

Using a fall of VOHSYNC as a reference, a period from the number of cycles VOHDS to VOHDE at video output clock VOCLK (not shown) is a valid display region in the horizontal direction, and using a fall of VOVSYNC as a reference, a period from the number of horizontal lines VOVDS to VOVDE is a valid display region in the vertical direction.

In the case of WVGA (800 pixels (W)×480 pixels (H)), a frequency of 33 MHz is used for VOCLK. Furthermore, the frequency of VOCLK varies depending on a total number of pixels.

FIG. 6is a timing chart illustrating processing timing of video output section160.

InFIG. 6, a period from VOVDS to VOVDE is a vertical processing period and a period from VOHDS to VOHDE is a horizontal processing period. Video output section160reads image data from frame memory120or frame memory130via memory controller section190during a horizontal processing period and outputs the image data to display170. Furthermore, video output section160outputs a flag to control section180at timings of VOVDS, VOVDE, VOHDS and VOHDE.

[When Three Banks (Banks0to2) are Allocated to Frame Memories120and130]

FIG. 7is a diagram illustrating memory contents when three banks (banks0to2) accessed by video input section140and video output section160are allocated to frame memory120and frame memory130.

Control section180sets image sizes and base addresses of the banks allocated to frame memory120and frame memory130in video input section140and video output section160. In the example ofFIG. 7, bank0and bank2which are even-numbered banks are allocated to frame memory120and bank1which is an odd-numbered bank is allocated to frame memory130.

First, a case where VIVSYNC and VOVSYNC have the same cycle will be described.

FIG. 8is a timing chart illustrating timing at which video input section140and video output section160access banks allocated to frame memory120and frame memory130when VIVSYNC and VOVSYNC have the same cycle.

The period during which video input section140writes data to each bank is the same as the vertical processing period inFIG. 4. Furthermore, the period during which video output section160reads data from each bank is the same as the vertical processing period inFIG. 6.

During period1-A, video input section140writes data to bank0allocated to frame memory120.

Control section180recognizes to which bank video input section140starts writing data from a VIVDS flag outputted from video input section140and recognizes that video input section140has ended the data write from a VIVDE flag.

During period1-B, at the same time as video input section140writes data to bank1allocated to frame memory130, video output section160reads data of bank0allocated to frame memory120.

Video output section160is controlled by control section180so as to read the last bank to which video input section140completed a data write. Video output section160may receive the VIVDE flag outputted from video input section140and video output section160may recognize the last bank to which video input section140completed a data write without going through control section180.

During period1-C, at the same time as video input section140writes data to bank2allocated to frame memory120, video output section160reads the data of bank1allocated to frame memory130.

During period1-D, video input section140writes data to bank0allocated to frame memory120and video output section160reads data of bank2allocated to frame memory120. Since video input section140and video output section160access the same frame memory120during this period, there is a period during which those sections cannot access the memory simultaneously and need to wait for processing.

During period1-B and period1-C, a memory write by video input section140and a memory read by video output section160can be realized simultaneously, and therefore processing can be performed at a high speed.

Furthermore, since control section180can keep track of memory access start/end timing of video input section140and video output section160and which frame memory is being accessed, control section180recognizes that only frame memory130is in a non-access state during period1-A and period1-D and both frame memory120and frame memory130are in a non-access state during periods except periods1-A to1-D.

Thus, control section180can perform processing such as calculation on a frame memory in a non-access state and can thereby improve overall system performance.

Furthermore, by adopting a total of four banks such as bank0and bank2for frame memory120and bank1and bank3for frame memory130, it is possible to prevent video input section140and video output section160from accessing the same frame memory as in the case of period1-D.

Next, a case where the cycle of VIVSYNC is shorter than the cycle of VOVSYNC will be described.

FIG. 9is a timing chart illustrating timing at which video input section140and video output section160access banks allocated to frame memory120and frame memory130when the cycle of VIVSYNC is shorter than the cycle of VOVSYNC.

During period2-A, video input section140writes data to bank0allocated to frame memory120.

During period2-B, video input section140writes data to bank1allocated to frame memory130.

During period2-C, at the same time as video input section140writes data to bank1allocated to frame memory130, video output section160reads the data of bank0allocated to frame memory120.

During period2-D, video output section160reads the data of bank0allocated to frame memory120.

During period2-E, video input section140writes data to bank2allocated to frame memory120.

During period2-F, video output section160reads the data of bank2allocated to frame memory120. Video output section160reads not the data of bank1but bank2because bank2is the last bank to which video input section140completed a data write. Thus, the display of bank1is skipped.

During period2-G, video input section140writes data to bank0allocated to frame memory120and video output section160reads data of bank2allocated to frame memory120. Since video input section140and video output section160access the same frame memory120during this period, there is a period during which those sections cannot access the memory simultaneously and need to wait for processing.

During period2-H, video input section140writes data to bank0allocated to frame memory120.

During period2-I, video output section160reads data of bank0allocated to frame memory120.

During period2-J, at the same time as video input section140writes data to bank1allocated to frame memory130, video output section160reads the data of bank0allocated to frame memory120.

During period2-C and period2-J, since a memory write by video input section140and a memory read by video output section160can be performed simultaneously, processing can be performed at a high speed.

Furthermore, control section180recognizes that only frame memory120is in a non-access state during period2-B, only frame memory130is in a non-access state during period2-A and period2-D to2-I, and both frame memory120and frame memory130are in a non-access state during periods except period2-A to2-J, and can thereby perform processing such as calculations on frame memories in a non-access state and improve overall system performance.

Next, a case where the cycle of VIVSYNC is longer than the cycle of VOVSYNC will be described.

FIG. 10is a timing chart illustrating timings at which video input section140and video output section160access banks allocated to frame memory120and frame memory130when the cycle of VIVSYNC is longer than the cycle of VOVSYNC.

During period3-A, video input section140writes data to bank0allocated to frame memory120.

During period3-B, video output section160reads the data of bank0allocated to frame memory120.

During period3-C, at the same time as video input section140writes data to bank1allocated to frame memory130, video output section160reads the data of bank0allocated to frame memory120.

During period3-D, video input section140writes data to bank1allocated to frame memory130.

During period3-E, video output section160reads the data of bank1allocated to frame memory130.

During period3-F, video input section140writes data to bank2allocated to frame memory120.

During period3-G, at the same time as video input section140writes data to bank2allocated to frame memory120, video output section160reads the data of bank1allocated to frame memory130. Video output section160also reads the data of bank during period3-G following period3-E because video input section140has not completed the data write to bank2and bank1is the last bank to which the data write was completed.

During period3-H, video output section160reads the data of bank1allocated to frame memory130.

During period3-I, video input section140writes data to bank0allocated to frame memory120.

During period3-J, video input section140writes data to bank0allocated to frame memory120and video output section160reads the data of bank2allocated to frame memory120. During this period, since video input section140and video output section160access the same frame memory120, there is a period during which those sections cannot access the memory simultaneously and need to wait for processing.

During period3-C and period3-G, since a memory write by video input section140and a memory read by video output section160can be performed simultaneously, processing can be performed at a high speed.

Furthermore, control section180recognizes that only frame memory120is in a non-access state during periods3-D to3-E and period3-H, only frame memory130is in a non-access state during periods3-A and3-B and period3-F, periods3-1and3-J, and both frame memory120and frame memory130are in a non-access state during periods except periods3-A to3-J, can perform processing such as calculations on frame memories in a non-access state and can thereby improve overall system performance.

[When Three Banks (Banks0to2) are Allocated to Frame Memories120and130, and Moreover Four Banks (Banks RA0, RA1, RB0, RB1) Accessed by Drawing Section150and Video Output Section160are Allocated]

FIG. 11is a diagram illustrating memory contents when three banks (banks0to2) accessed by video input section140and video output section160are allocated to frame memory120and frame memory130, and moreover four banks (banks RA0, RA1, RB0, RB1) accessed by drawing section150and video output section160are allocated.

Control section180sets image sizes and base addresses of the banks allocated to frame memory120and frame memory130in drawing section150and video output section160.

A double buffer configuration is generally provided which switches between two banks; a bank corresponding to drawing and a bank corresponding to display so that images being drawn are not displayed. As shown inFIG. 11, the present embodiment provides two banks in each of frame memory120and frame memory130so that video input section140, drawing section150and video output section160can perform parallel processing efficiently.

FIG. 12is a diagram illustrating the bank that control section180commands drawing section150to access next according to the access situations of video input section140and video output section160.

InFIG. 12, frame memory120or frame memory130is described in the access situation field of video input section140or video output section160and this means which frame memory should be accessed next when control section180determines which bank to access next by drawing section150, according to which frame memory video input section140and video output section160are each accessing or which frame memory frame memory video input section140and video output section160will access next when they are accessing none of the frame memories. The bank to which drawing section150completed access last time is accessed by video output section160to read data to be displayed.

As a reference for drawing section150to determine the bank to access next, a bank allocated to the frame memory having the least factor to be accessed is selected based on the access situation of video input section140, the access situation of video output section160and the bank to which drawing section150completed access last time.

This increases the frequency with which video input section140, drawing section150and video output section160can access frame memory120and frame memory130in parallel and can thereby improve performance.

Furthermore, also when a total of two banks accessed by drawing section150and video output section160are allocated; one to frame memory120and one to frame memory130, it is possible to improve performance by specifying a bank allocated to the frame memory having the least factor to be accessed as the bank to access next by drawing section150based on the access situation of video input section140, the access situation of video output section160and the bank to which drawing section150completed access last time.

For video input section140as in the case of drawing section150, a bank allocated to the frame memory having the least factor to be accessed may be selected as the bank to access next based on the access situation of video input section140, the access situation of drawing section150, the access situation of video output section160and the bank to which video input section140completed access last time.

Next, operation of drawing section150will be described.

FIG. 13is a timing chart illustrating timing at which texture load section153and pixel generation section154access texture memories151and152and memory controller section190.

During period4-A, texture load section153reads texture data of graphics (1) stored in system memory110and writes the texture data to texture memory151.

During period4-B, at the same time as texture load section153reads texture data of graphics (2) stored in system memory110and writes the texture data to texture memory152, pixel generation section154reads the texture data of graphics (1) stored in texture memory151, generates drawing data of graphics (1) and writes the drawing data to frame memory120or frame memory130.

During period4-C, at the same time as texture load section153reads texture data of graphics (3) stored in system memory110and writes the texture data to texture memory151, pixel generation section154reads the texture data of graphics (2) stored in texture memory152, generates drawing data of graphics (2) and writes the drawing data to frame memory120or frame memory130.

During period4-D, pixel generation section154reads texture data of graphics (3) stored in texture memory151, generates drawing data of graphics (3) and writes the drawing data to frame memory120or frame memory130.

During period4-B and period4-C, processing by texture load section153and that by pixel generation section154can be executed simultaneously and processing can thereby be performed at a high speed.

When, for example, system memory110is a low-speed memory such as flash memory and frame memory120or frame memory130is a high-speed memory such as SDRAM, after transferring texture data from system memory110to frame memory120or frame memory130, texture load section153may read the texture data from frame memory120or frame memory130.

Furthermore, texture load section153may also read the video data written by video input section140to frame memory120or frame memory130as texture data.

As described above, the present embodiment eliminates the necessity for video input section140and drawing section150to have respective dedicated frame memories, allows video input section140, drawing section150and video output section160to process the two frame memories in parallel, further allows drawing section150to process two graphics in parallel, and can thereby improve processing performance at low cost.

As described in detail above, according to the present embodiment, image processing apparatus100is provided with memory controller section190that divides and allocates banks accessed by video input section140, drawing section150and video output section160between/to a plurality of frame memories120and130, arbitrates between access requests from master sections such as video input section140, drawing section150and video output section160and controls data transfers so that the plurality of master sections can access frame memories120and130in parallel and memory controller section190selects, when each master section determines which bank to access next, a bank allocated to the frame memory having the least factor to be accessed based on the access situation of each master section to each frame memory120or130.

For example, memory controller section190divides and allocates a plurality of banks accessed by drawing section150and video output section160between/to a plurality of frame memories120and130and selects, when drawing section150determines which bank to access next, a bank allocated to a frame memory120or130having the least factor to be accessed based on information about which of frame memories120and130video input section140and video output section160are each accessing or information about which of frame memories120and130is to access next when none of frame memories120and130is being accessed and information of the bank to which drawing section150completed access last time.

Furthermore, memory controller section190selects, when video input section140determines which bank to access next, a bank allocated to frame memory120or130having the least factor to be accessed based on information about which of frame memories120and130drawing section150and video output section160are each accessing or information about which of frame memories120and130is to access next when none of frame memories120and130is being accessed.

In the conventional example, a frame memory having a double buffering region corresponding to a plurality of video input images and graphics is used. In contrast to this, in the present embodiment, such a function is realized by memory controller section190selecting a bank allocated to the frame memory having the least factor to be accessed based on the access situation of each master section. This eliminates the necessity of having frame memories corresponding to video input images and drawings, can perform access to frame memories for video input, drawing and display in parallel, and can thereby improve processing performance at low cost.

FIG. 14is a block diagram illustrating a configuration of an image processing apparatus according to Embodiment 2 of the present invention. The same components as those inFIG. 1will be assigned the same reference numerals and overlapping descriptions thereof will be omitted.

Video input section311writes video data to frame memory120or frame memory130via memory controller section310based on a vertical synchronization signal and a horizontal synchronization signal of video outputted from camera210.

Video input section312writes video data to frame memory120or frame memory130via memory controller section310based on a vertical synchronization signal and a horizontal synchronization signal of video outputted from DVD211.

Video input section312writes video data to frame memory120or frame memory130via memory controller section310based on a vertical synchronization signal and a horizontal synchronization signal of video outputted from TV212.

Memory controller section310arbitrates between memory access requests from master sections such as video input section311, video input section312, video input section313, drawing section150, video output section160and control section180and controls data transfers so that a plurality of master sections can access system memory110, frame memory120and frame memory130in parallel.

FIG. 15is a diagram illustrating memory contents when three banks accessed by video input section311, video input section312, video input section313and video output section160, a total of nine banks (banks AO to2, banks BO to2, banks CO to2) are allocated to frame memory120and frame memory130, and further four banks (banks RA0, RA1, RB0, RB1) accessed by drawing section150and video output section160are allocated.

Thus, by causing banks for video input section311, video input section312, video input section313and drawing section150to be divided and allocated between/to frame memory120and frame memory130and by specifying a bank allocated to the frame memory having the least factor to be accessed as the bank to access next by drawing section150based on the access situations of video input section311, video input section312and video input section313, the access situation of video output section160and the bank to which drawing section150completed access last time, the frequency with which video input section311, video input section312, video input section313, drawing section150and video output section160can access frame memory120and frame memory130in parallel, and can thereby improve performance.

As in the case of drawing section150, for video input section311, video input section312and video input section313, a bank allocated to the frame memory having the least factor to be accessed may also be selected as the bank to access next based on the access situations of other video input sections, the access situation of drawing section150, the access situation of video output section160and the banks to which video input section311, video input section312and video input section313completed access last time respectively.

As described above, according to the present embodiment, memory controller section310arbitrates between memory access requests from master sections such as video input section311, video input section312, video input section313, drawing section150, video output section160and control section180and controls data transfers so that a plurality of master sections can access system memory110, frame memory120and frame memory130in parallel, and it is thereby possible to perform parallel processing with drawing section150and video output section160even in the configuration having a plurality of video input sections, and thereby improve processing performance.

The above descriptions are illustrative of the preferred embodiments of the present invention, but the scope of the present invention is not limited to this. For example, the above described embodiments have described a case where the present invention is applied to various electronic devices, but the present invention is likewise applicable to any device that displays an input target in a space.

A term “image processing apparatus” has been used in the above described embodiments, but it goes without saying that this is for convenience of explanation, and the term may also be an “image processing system,” “image output apparatus” or the like.

Furthermore, the type, number and connection method or the like of each apparatus such as memory making up the above described image processing apparatus are not limited to those of the aforementioned embodiments.

The disclosure of Japanese Patent Application No. 2008-209271, filed on Aug. 15, 2008, including the specification, drawings and abstract, is incorporated herein by reference in its entirety.

INDUSTRIAL APPLICABILITY

The present invention can process video inputs, drawings and displays at a high speed, and can thereby speedily display various images such as an operation screen of an air conditioner, car navigation screen, video of DVD and TV superimposed on each other on, for example, a car-mounted display. The present invention is also widely applicable to an image processing system in each electronic device other than a car-mounted display.

REFERENCE SIGNS LIST