Designed-based interconnect structure in semiconductor structure

Semiconductor structures are provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate and a contact formed adjacent to the gate structures over the substrate. The semiconductor structure further includes a plurality of metal layers formed over the gate structures. In addition, some of the metal layers include metal lines extending in the first direction, and some of the metal layers include metal lines extending in a second direction substantially perpendicular to the first direction. Furthermore, the gate structures follow the following equation:Pgate min is the minimum value among gate pitches of the gate structures. Lgate min is the minimum value among gate lengths of the gate structures. Hgate min is the minimum value among gate heights of the gate structures.

BACKGROUND

For example, as the semiconductor industry has progressed into nanometer-technology process nodes in pursuit of higher device density, higher performance, and lower costs, challenges from both fabrication and design have resulted in the development of multilayer (or three dimensional) integrated devices. The multilayer devices may include a plurality of dielectric layers each including one or more conductive layers which are aligned and connected with other conductive layers. However, as the scaling-down continues, forming and aligning conductive layers has proved difficult. Accordingly, although existing multilayer devices and methods of fabricating multilayer devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects.

DETAILED DESCRIPTION

Embodiments of semiconductor structures are provided in accordance with some embodiments of the disclosure. The semiconductor structures may include interconnection structures. The interconnection structures may include metal lines formed over gate structures, and the metal lines may be designed in accordance with the sizes and/or the layout of the gate structures, such that the interconnect structures can have better performance.

FIG. 1Ais a top-view representation of a semiconductor structure100ain accordance with some embodiments.FIG. 1Bis a cross-sectional representation of semiconductor structure100aalong lines A-A′ shown inFIG. 1Ain accordance with some embodiments.FIG. 1Cis a cross-sectional representation of semiconductor structure100aalong lines B-B′ shown inFIG. 1Ain accordance with some embodiments.

As shown inFIGS. 1A to 1C, semiconductor structure100aincludes a substrate102in accordance with some embodiments. In addition, a diffusion region104and an isolation structure106are formed in substrate102. Substrate102may be a semiconductor wafer such as a silicon wafer. Alternatively or additionally, substrate102may include elementary semiconductor materials, compound semiconductor materials, and/or alloy semiconductor materials. Examples of the elementary semiconductor materials may be, but are not limited to, crystal silicon, polycrystalline silicon, amorphous silicon, germanium, and/or diamond. Examples of the compound semiconductor materials may be, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide. Examples of the alloy semiconductor materials may be, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP.

In some embodiments, diffusion region104is an oxide diffusion region formed in substrate102. Diffusion region104may be a P-type doping region or an N-type doping region. In some embodiments, diffusion region104further includes source and drain regions. Isolation structure106may be used to separate diffusion region104from other diffusion regions (not shown). In some embodiments, isolation structure106is a shallow trench isolation (STI) structure.

Gate structures108are formed over substrate102, as shown inFIG. 1A to 1Cin accordance with some embodiments. Gate structures108are formed extending in a first direction substantially parallel to substrate102. As shown inFIGS. 1A and 1B, each gate structure108has its gate length Lgate 108and its gate height Hgate 108, and it should be noted that gate lengths Lgate 108and gate heights Hgate 108of different gate structures108may be the same or different.

Gate length Lgate 108is defined as the channel length of one gate structure108. For example, gate length Lgate 108of one gate structure108is defined as the distance between two sidewalls of the gate structure108in a second direction substantially perpendicular to the first direction. As shown inFIG. 1B, the second direction is also substantially parallel to substrate102.

Gate height Hgate 108is defined as the height of one gate structure108measured in a third direction substantially perpendicular to the substrate102. As shown inFIGS. 1A and 1B, the first direction and the second direction are both substantially parallel to the substrate102but are substantially perpendicular to each other, and the third direction is substantially perpendicular to both the first direction and the second direction.

In addition, gate structures108has a gate pitch Pgate 108, as shown inFIGS. 1A and 1B. Gate pitch Pgate 108is defined as the distance between the center of one gate structure108to the center of another gate structure108. As shown inFIG. 1B, gate pitch Pgate 108may be measured along the second direction.

Gate structures108may include gate dielectric layers and gate electrodes. In some embodiments, gate dielectric layers are made of high-k dielectric materials, such as metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, or oxynitrides of metals. Examples of the high-k dielectric material include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), silicon nitride, silicon oxynitride, zirconium oxide, titanium oxide, aluminum oxide, hafnium dioxide-alumina (HfO2—Al2O3) alloy, and other applicable dielectric materials.

Gate electrodes may be formed over gate dielectric layers. In some embodiments, gate electrodes are made of conductive materials, such as polysilicon, metal, metal alloy, and/or metal silicide. In some embodiments, gate electrodes are made of aluminum, tungsten, cobalt, tantalum, titanium aluminum, copper, or doped polysilicon.

Gate structures108may be formed by a procedure that includes deposition, photolithography patterning, and etching processes. The deposition processes may include chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), high-density plasma CVD (HDPCVD), metal organic CVD (MOCVD), or plasma-enhanced CVD (PECVD). The photolithography patterning processes may include photoresist coating (e.g. spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g. hard baking), and/or other applicable processes. The etching processes may include dry etching, wet etching, and/or other etching methods (e.g. reactive ion etching).

Contacts112are formed adjacent to gate structures108over substrate102, as shown inFIG. 1A to 1Cin accordance with some embodiments. More specifically, contacts112are formed in diffusion region104of substrate102in accordance with some embodiments. As shown inFIG. 1A, each contact112has a contact width Wcontact 112. Contact width Wcontact 112is defined as the length of one contact112in diffusion region104along the first direction. It should be noted that a contact may include a number of portions aligned in the first direction in a diffusion region, and its contact width is defined as the sum of all portions of the contact.

After gate structures108and contacts112are formed over substrate102, an interconnect structure is formed to electrically connect with gate structures108and contacts112. As shown inFIG. 1A, the interconnect structure includes first level vias116, first level metal lines120, second level vias124, second level metal lines128, third level vias132, and third level metal lines136in accordance with some embodiments. In addition, first level vias116, first level metal lines120, second level vias124, second level metal lines128, third level vias132, and third level metal lines136are formed in inter-metal dielectric (IMD) layer117.

More specifically, a first level via layer114is formed over gate structures108, as shown inFIG. 1A to 1Cin accordance with some embodiments. First level via layer114includes first level vias116formed in inter-metal dielectric layer117in accordance with some embodiments. In addition, each first level via116has a via length Lvia 116, which is measured along the second direction.

In some embodiments, first level vias116are made of a highly-conductive metal, low-resistive metal, elemental metal, transition metal, or the like. Examples of conductive materials used to form first level vias116may include, but are not limited to, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), gold (Au), cobalt (Co), and tantalum (Ta).

In some embodiments, inter-metal dielectric layer117includes multilayers made of multiple dielectric materials, such as a low dielectric constant or an extreme low dielectric constant (ELK) material. Examples of the dielectric materials may include, but are not limited to, oxide, SiO2, borophosphosilicate glass (BPSG), tetraethyl orthosilicate (TEOS), spin on glass (SOG), undoped silicate glass (USG), fluorinated silicate glass (FSG), high-density plasma (HDP) oxide, or plasma-enhanced TEOS (PETEOS).

After first level via layer114is formed, a first level metal layer118is formed over first level via layer114, as shown inFIG. 1Bin accordance with some embodiments. First level metal layer118includes first level metal lines120formed in inter-metal dielectric layer117in accordance with some embodiments. As shown inFIG. 1B, one of contacts112, which is formed adjacent to gate structures108over substrate102, is in direct contact with one of first level vias116, and the first level via116is in direct contact with one of first level metal lines120. In addition, one of first level metal line120is formed over one of gate structures108and is separated from the gate structure108by a distance D measured in the third direction. In some embodiments, distance D is larger than or equal to 0.25 times gate length Lgate 108of the gate structure108.

In addition, a metal line pitch Pmetal line 120of first level metal lines120is defined as the distance between the center of one first level metal line120to the center of another first level metal line120, as shown inFIG. 1A.

In some embodiments, first level metal lines120are made of a highly-conductive metal, low-resistive metal, elemental metal, transition metal, or the like. Examples of conductive materials used to form first level metal lines120may include, but are not limited to, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), gold (Au), cobalt (Co), or tantalum (Ta).

After first level metal layer118is formed, a second level via layer122is formed over first level metal layer118, and a second level metal layer126is formed over second level via layer122, as shown inFIG. 1A to 1Cin accordance with some embodiments. In some embodiments, second level via layer122includes second level vias124formed in inter-metal dielectric layer117, and second level metal later126includes second level metal lines128formed in inter-metal dielectric layer117.

Similarly, each second level via124has a via length Lvia 124measured along the second direction. In addition, second level metal lines128have a metal line pitch Pmetal line 128defined as the distance between the central of one second level metal line128to the central of another second level metal line128. Materials used to form second level vias124and second level metal lines128may be the same as, or similar to, those used to form first level vias116and first level metal lines120and are not repeated herein.

After second level metal layer126is formed, a third level via layer130is formed over second level metal layer126, and a third level metal layer134is formed over third level via layer130, as shown inFIG. 1A to 1Cin accordance with some embodiments. In some embodiments, third level via layer130includes third level vias132formed in inter-metal dielectric layer117, and third level metal layer134includes third level metal lines136formed in inter-metal dielectric layer117.

Similarly, each third level via132has a via lengths Lvia 132measured along the second direction. In addition, third level metal lines136have a metal line pitch Pmetal line 136defined as the distance between the central of one third level metal line136to the central of another third level metal line136. Materials used to form third level vias132and third level metal lines136may be the same as, or similar to, those used to form first level vias116and first level metal lines120and are not repeated herein.

The layout and sizes of the structures in semiconductor structure100aare designed to perform better and to reduce the manufacturing cost in accordance with some embodiments. In some embodiments, a contact in semiconductor structure100aare designed to follow the following equation (1):
Wcontact≧1.4Lgate min(1)

In equation (1), Lgate minis the minimum value among gate lengths of the gate structures in a semiconductor structure. In some embodiments, all gate structures have the same gate length, and Lgate minis referred to the gate length of any one of the gate structures. In some other embodiments, the gate structures have various gate lengths, and Lgate minrefers to the smallest gate length among all of the gate lengths of the gate structures.

As shown inFIG. 1A, gate structures108in semiconductor100ahave the same gate length Lgate 108, and therefore gate length Lgate 108can be seen as Lgate minin equation (1). In some embodiments, at least one of contacts112has a contact width Wcontact 112greater than or equal to (i.e. no less than) 1.4 times gate length Lgate 108(i.e. Lgate min.). In some embodiments, contact width Wcontact 112is equal to 3 times gate length Lgate 108and therefore is greater than 1.4 times gate length Lgate 108.

It is found that if the contact width of a contact is relatively too small, the resistance of the contact may be too great. In some embodiments, one contact112in semiconductor structure100ais designed to follow the following equation (1.1):
30Lgate min>Wcontact≧1.4Lgate min(1.1)

In some embodiments, gate structures108in semiconductor structure100aare designed to follow the following equation (2):

In equation (2), Pgate minis the minimum value among gate pitches of the gate structures. Lgate minis the minimum value among gate lengths of the gate structures. Hgate minis the minimum value among gate heights of the gate structures. It is found that the value of Pgate minwill relate to the capacitance in the second direction and the cell resistance of semiconductor structure100a. In addition, the value of Lgate minwill relate to the capacitance in the second direction and the third direction. The value of Hgate minwill relate to the capacitance in the third direction. Therefore, when semiconductor structure100ais designed to follow equation (2), the capacitance of semiconductor structure100amay be improved.

In some embodiments, gate structures108of semiconductor structure100afollows the following equation:

In some embodiments, semiconductor structure100ais designed to follow both equations (1) and (2). In some embodiments, gate structures108in semiconductor structure100aare designed to follow the following equation (2.1):

In some embodiments, two metal layers in semiconductor structure100aare designed to follow the following equation (3):
Pmetal line≦0.76Pgate min(3)

In equation (3), Pgate minis the minimum value among gate pitches of the gate structures. That is, the pitch of the metal lines in semiconductor structure100amay be designed to be relatively small, such that the interconnect structure can have a higher routing density. Therefore, the resulting semiconductor structure100amay have a better chip arrangement and appropriate route sizes.

In some embodiments, at least two metal line pitches in two metal layers of semiconductor structure100afollow equation (3). In addition, the two metal line pitches are measured from two different metal layers. In some embodiments, Pmetal line 120of first level metal lines120is less than or equal to (i.e. no greater than) 0.76 times Pgate 108of gate structure108, and Pmetal line 136of third level metal lines136is less than or equal to (i.e. no greater than) 0.76 times Pgate 108of gate structures108, as shown inFIG. 1Ain accordance with some embodiments. In some embodiments, Pmetal line 120of first level metal lines120is equal to 0.666 times Pgate 108of gate structure108and therefore less than 0.76 times Pgate 108of gate structures108.

It should be noted that the metal lines in other metal layers may additionally or alternatively follow equation (3). That is, Pmetal linein equation (3) is not limited to the pitches of metal lines120and136.

In some embodiments, the structures in semiconductor structure100aare designed to follow the following equation (3.1):
0.1Pgate min≦Pmetal line≦0.76Pgate min(3.1)

In some embodiments, the first metal layer having metal lines extending in the first direction in semiconductor structure100ais designed to follow the following equation (4):
P1st metal line min≧0.5Pgate min+0.55Lgate min+0.18Hgate min(4)

As described above, Pgate minis the minimum value among gate pitches of the gate structures, and Lgate minis the minimum value among gate lengths of the gate structures. Hgate minis the minimum value among gate heights of the gate structures. In addition, a first metal layer is defined as the first metal layer having metal lines extending in a direction substantially parallel to the gate structures (e.g. in the first direction.) P1st metal line minis the minimum value among the pitches of the metal lines of the first metal layer. It is found that pitch P1st metal line minshould be large enough to release the resistance of the semiconductor structure. In addition, when the first metal layer has a relatively low density, the lithography process for forming the structure may be less complicated, and the cost of forming the structure may be reduced.

More specifically, the first metal layer is the metal layer positioned closest to the gate structures among all the metal layers which include metal lines extending in the first direction. That is, the distance between the first metal layer and gate structures108(or substrate102) is smaller than the distance between gate structures108(or substrate102) and all other metal layers having metal lines extending in the first direction.

As shown inFIG. 1A, although second metal layer126is formed over first level metal layer118, first level metal lines118do not extend in the first direction but in the second direction. Therefore, second level metal layer126, which has second level metal lines128extending in the first direction, can be seen as the first metal layer in equation (4). In addition, pitch Pmetal line 128of second level metal lines128can be seen as P1st metal line minin equation (4). Therefore, Pmetal line 128of second level metal lines128is greater than or equal to (i.e. no less than) the sum of 0.5 times Pgate 108of gate structures108and 0.55 times Lgate 108of gate structures108and 0.18 times Hgate 108of gate structures108in accordance with some embodiments.

In some embodiments, Pmetal line 128of second level metal lines128is equal to the sum of 0.62 times Pgate 108of gate structures108and 0.65 times Lgate 108of gate structures108and 0.23 times Hgate 108of gate structures108. In some embodiments, semiconductor structure100ais designed to follow both equations (3) and (4). In some embodiments, the structures in semiconductor structure100aare designed to follow the following equation (4.1):
5Pgate min+5.5Lgate min+1.8Hgate min≧P1st metal line min≧5Pgate min+0.55Lgate min+0.18Hgate min(4.1)

In some embodiments, one of the metal lines in the first metal layer in semiconductor structure100ais designed to follow the following equation (5):
T1st metal line≧0.6Pgate min+0.45Lgate min+0.15Hgate min(5)

As described previously, Pgate minis the minimum value among gate pitches of the gate structures, and Lgate minis the minimum value among gate lengths of the gate structures. Hgate minis the minimum value among gate heights of the gate structures. The first metal layer is defined as the first metal layer having metal lines extending in the first direction, and the metal lines in the first metal layer are called first metal lines. In addition, thickness T1st metal lineis the thickness of one of the first metal lines in the first metal layer. It is found that when the thickness of the first metal line is relatively thick, the resistance will be reduced.

In some embodiments, second level metal line128can be seen as the first metal line, and thickness Tmetal line 128of second level metal line128can be seen as T1st metal linein equation (5). In some embodiments, thickness Tmetal line 128of second level metal line128is greater than or equal to (i.e. no less than) the sum of 0.6 times Pgate 108of gate structures108and 0.45 times Lgate 108of gate structures108and 0.15 times H gate structures108. It should be gate108of noted that, as shown inFIG. 1A, the first metal layer (e.g. second level metal layer126) may include more than one metal line, and T1st metal linein equation (5) may be chosen from any one of the metal lines in the first metal layer.

In some embodiments, thickness Tmetal line 128of second level metal line128is equal to the sum of 0.64 times Pgate 108of gate structures108and 0.65 times Lgate 108of gate structures108and 0.23 times Hgate 108of gate structures108. In some embodiments, the first metal line in semiconductor structure100aare designed to follow the following equation (5.1):
6Pgate min+4.5Lgate min+1.5Hgate min≧T1st metal line≧6Pgate min+0.45Lgate min+0.15Hgate min(5.1)

In some embodiments, one of the first metal lines in the first metal layer in semiconductor structure100ais designed to follow the following equation (6):
W1st metal line≧0.38Pgate min+0.23Lgate min+0.13Hgate min(6)

As described previously, Pgate minis the minimum value among gate pitches of the gate structures, and Lgate minis the minimum value among gate lengths of the gate structures. Hgate minis the minimum value among gate heights of the gate structures. The first metal layer is defined as the first metal layer having metal lines extending in the first direction. In addition, W1st metal lineis the width of the first metal line in the first metal layer. Since the first metal line in the first metal layer is substantially parallel to the gate structures, the width of the metal line is measured alone the second direction substantially perpendicular to the first direction. It is found that when the width of the first metal line in the first metal layer is relatively wide, the resistance can be reduced. However, the width of the first metal line should not be too wide, or the risk of circuit short may increase.

In some embodiments, width Wmetal line 128of second level metal line128can be seen as W1st metal linein equation (6), and width Wmetal line 128of second level metal line128is greater than or equal to (i.e. no less than) the sum of 0.38 times Pgate 108of gate structures108and 0.23 times Lgate 108of gate structures108and 0.13 times Hgate 108of gate structures108. In some embodiments, at least one of the metal lines in the first metal layer follows equation (6). In some embodiments, all metal lines in the first metal layer follow equation (6).

In some embodiments, width Wmetal line 128of second level metal line128is equal to the sum of 0.43 times Pgate 108of gate structures108and 0.35 times Lgate 108of gate structures108and 0.15 times Hgate 108of gate structures108. In some embodiments, the first metal lines in semiconductor structure100aare designed to follow the following equation (6.1):
3.8Pgate min+2.3Lgate min+1.3Hgate min≧W1st metal line≧0.38Pgate min+0.23Lgate min+0.13Hgate min(6.1)

In some embodiments, a via connected to one first metal line in semiconductor structure100ais designed to follow the following equation (7):
Lvia≧0.26Pgate min+0.11Lgate min+0.12Hgate min(7)

As described previously, Pgate minis the minimum value among gate pitches of the gate structures, and Lgate minis the minimum value among gate lengths of the gate structures. Hgate minis the minimum value among gate heights of the gate structures. The first metal layer is defined as the first metal layer having metal lines extending in the first direction. Lviais the length of a via connecting to the first metal line of the first metal layer. It is found that when the length of the via connecting to the first metal line in the first metal layer is relatively wide, the resistance can be reduced.

In some embodiments, length Lvia 124of second level via124can be seen as Lviain equation (7), as shown inFIG. 1A. As shown inFIG. 1A, Lviais measured along the second direction. In some embodiments, length Lvia 124of second level via124is greater than or equal to (i.e. no less than) the sum of 0.26 times Pgate 108of gate structures108and 0.11 times Lgate 108of gate structures108and 0.12 times Hgate 108of gate structures108.

It should be noted that Lviain equation (7) may refer to the length of any via formed below or above any one of the first metal lines in the first metal layer. Therefore, in some embodiments, Lviain equation (7) can be referred to length Lvia 132of third level via132. In some embodiments, at least one of the vias connecting to the first metal line follows equation (7). In some embodiments, all vias connecting to the first metal lines follow equation (7). In some embodiments, length Lvia 124of second level via124is equal to the sum of 0.43 times Pgate 108of gate structures108and 0.35 times Lgate 108of gate structures108and 0.15 times Hgate 108of gate structures108. In some embodiments, a via connecting one of the first metal lines in semiconductor structure100ais designed to follow the following equation (7.1):
2.6Pgate min+1.1Lgate min+1.2Hgate min≧Lvia≧0.26Pgate min+0.11Lgate min+0.12Hgate min(7.1)

In some embodiments, semiconductor structure100afollows at least one equation in equations (1) to (7). In some embodiments, semiconductor structure100afollows equations (1) to (4) and one of equations (5) to (7). In some embodiments, semiconductor structure100afollows all equations (1) to (7) and results in 4.8% of the performance gain.

It should be noted that, althoughFIGS. 1A to 1Cdescribed above show two metal lines formed in each metal layer, the metal layer may actually include any number of metal lines. In addition, semiconductor structure100amay further include various conductive features in various dielectric layers.

In addition, the conductive features described above, such as metal lines and vias, may further include a liner and/or a barrier layer. The liner (not shown) may be either tetraethylorthosilicate (TEOS) or silicon nitride, although any other applicable dielectric may alternatively be used. The liner may be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other applicable processes, such as physical vapor deposition or a thermal process, may alternatively be used.

The barrier layer (not shown) may be formed over the liner (if present) and may cover the sidewalls and bottom of the opening. The barrier layer may be formed using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced CVD (PECVD), plasma enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other applicable deposition processes. The barrier layer may be made of tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, may also be used.

FIG. 2Ais a top-view representation of a semiconductor structure100bin accordance with some embodiments.FIG. 2Bis a cross-sectional representation of semiconductor structure100balong lines C-C′ shown inFIG. 2Ain accordance with some embodiments.

Similar to semiconductor structure100a, semiconductor structure100balso includes substrate102, diffusion region104, and isolation structure106. In addition, gate structures208a,208b, and208care formed in inter-level dielectric layer110over substrate102in accordance with some embodiments. As shown inFIG. 2B, gate structures208a,208b, and208crespectively have various gate lengths Lgate 208a, Lgate 208b, and Lgate 208c, and gate length Lgate 208cis the smallest among all gate structures208ato208cin accordance with some embodiments. Therefore, the Lgate minin diffusion region104in semiconductor structure100brefers to gate length Lgate 208cof gate structure208c.

In addition, gate structures208a,208b, and208chave the same height Hgate, and therefore Hgate minrefers to Hgateof any one of gate structures208a,208b, and208c. Furthermore, gate structures208aand gate208bhave a gate pitch Pgate 208ab, and gate structures208band208chave a gate pitch Pgate 208bc, which is larger than gate pitch Pgate 208ab, as shown inFIG. 2Ain accordance with some embodiments. Therefore, Pgate minin diffusion region104in semiconductor structure100brefers to gate pitch Pgate 208ab.

Materials and methods used to form gate structures208a,208b, and208cmay be similar to, or the same as, gate structures108shown inFIGS. 1A to 1C, and therefore the details of forming gate structures208a,208b, and208care not repeated herein.

Contacts212, similar to contacts112, are formed adjacent to gate structures208a,208b, and208cover substrate102, as shown inFIGS. 2A and 2Bin accordance with some embodiments. As shown inFIG. 2A, each contact212has a contact width Wcontact 212in accordance with some embodiments.

After gate structures208a,208b, and208cand contacts212are formed over substrate102, an interconnect structure is formed to electrically connect with gate structures208a,208b, and208cand contacts212. As shown inFIG. 2A, the interconnect structure includes first level vias216, first level metal lines220, second level vias224, second level metal lines228, third level vias232, third level metal lines236, fourth level vias240, and fourth level metal lines244formed in inter-metal dielectric layer117in accordance with some embodiments.

Similar to the metal lines and vias shown inFIG. 1Aand described above, a first level via layer214including first level vias216formed over gate structures208ato208c, and a first level metal layer218including first level metal lines220is formed over first level via layer214, as shown inFIG. 2Ain accordance with some embodiments. In addition, a second level via layer222including second level vias224is formed over first level metal layer218, and a second level metal layer226including second level metal lines228is formed over second level via layer222.

Next, a third level via layer230including third level vias232is formed over second level metal layer226, and a third level metal layer234including third level metal lines236is formed over third level via layer230. Afterwards, a forth level via layer238including fourth level vias240is formed over third level metal layer234, and a fourth level metal layer242including fourth level metal lines244is formed over fourth level via layer234. Materials and method used to form the metal lines and via shown inFIG. 2Amay be similar to, or the same as, those used to form the metal lines and vias shown inFIGS. 1A to 1C, and therefore the details are not repeated herein.

The layout and sizes of the structures in semiconductor structure100bare designed to follow at least one of equations (1) to (7) described previously, such that semiconductor structure100bcan have a better performance.

In some embodiments, contact width Wcontact 212of one of contacts212in semiconductor structure100bis greater than 1.4 times gate length Lgate 208cof gate structure208c(i.e. Lgate min). That is, contact width Wcontact 212in diffusion region104in semiconductor structure100bis designed to follow equation (1) described previously.

The gate structures208ato208cin semiconductor structure100bmay be designed to follow equation (2) described previously. In some embodiments, gate structures208a,208b, and208care designed to follow the following equation:

As shown inFIG. 2A, first level metal lines220, second level metal lines228, third level metal lines236, and fourth level metal lines244respectively have metal line pitches Pmetal line 220, Pmetal line 228, Pmetal line 236, and Pmetal line 244. The metal lines in semiconductor structure100bmay be designed to follow equation (3) described previously. In some embodiments, at least two of the metal line pitches in semiconductor structure100bare smaller than or equal to 0.76 times Pgate 208ab(i.e. Pgate min). For example, Pmetal line 236and Pmetal line 244are both smaller than or equal to 0.76 times Pgate 208ab.

As described previously, the first metal layer is defined as the first metal layer having metal lines extending in the direction substantially parallel to the gate structures (e.g. in the first direction.) As shown inFIG. 2A, the first metal layer in semiconductor structure100bmay be referred to second level metal layer226. Accordingly, P1st metal line minin equation (4) refers to Pmetal line 228, and Pmetal line 228is greater than or equal to the sum of 0.5 times Pgate 208ab(i.e. Pgate min) and 0.55 times Lgate 208cof gate structure208c(i.e. Lgate min) and 0.18 times Hgateof any one of gate structures208ato208c(i.e. Hgate min) in accordance with some embodiments. That is, second level metal layer226, which can be seen as the first metal layer in semiconductor structure100b, may be designed to follow equation (4) described previously.

In some embodiments, as shown inFIG. 2B, metal layers in semiconductor structure100bincludes a first metal layer including metal lines extending in the first direction (e.g. second level metal layer226), a first type metal layers including metal lines extending in the first direction (e.g. fourth level metal layer242), and a second type metal layers including metal lines extending in the second direction (e.g. first level metal layer218and third level metal layer234). In addition, the first type metal layers is formed over the first metal layer, such that the first metal layer is the first metal layer is the metal line being closest to substrate102among all metal layers including metal lines extending in the first direction.

As shown inFIG. 2B, second level metal line228has a thickness Tmetal line 228, which can be seen as T1st metal linein equation (5). In some embodiments, Tmetal line 228(i.e. T1st metal line) is larger than or equal to the sum of 0.6 times Pgate 208ab(i.e. Pgate min) and 0.45 times Lgate 208cof gate structure208c(i.e. Lgate min) and 0.15 times Hgateof any one of gate structures208ato208c(i.e. Hgate min). That is, second level metal line228may be designed to follow equation (5) as previously described.

As shown inFIG. 2A, second level metal line228has a width W line228, which can be seen as W1st metal linein semiconductor structure100b. In some embodiments, Wmetal line 228of second level metal line228is larger than or equal to the sum of 0.38 times Pgate 208ab(i.e. Pgate min) and 0.23 times Lgate 208cof gate structure208c(i.e. Lgate min) and 0.13 times Hgateof any one of gate structures208ato208c(i.e. Hgate min). That is, second level metal line228may be designed to follow equation (6) described previously.

As shown inFIG. 2A, via224is connected to second metal line228, and via224has a length Lvia 224, which can be seen as Lviain equation (7). In some embodiments, Lvia 224(i.e. Lvia) is larger than or equal to the sum of 0.26 times Pgate 208ab(i.e. Pgate min) and 0.11 times Lgate 208cof gate structure208c(i.e. Lgate min) and 0.12 times Hgateof any one of gate structures208ato208c(i.e. Hgate min). That is, via224is designed to follow equation (7) described previously.

It should be noted that semiconductor structure100bmay further include various conductive features in various dielectric layers, such as various metal layers and via layers, and the scope of the disclosure is not intended to be limiting.

FIG. 3is a top-view representation of a semiconductor structure100cin accordance with some embodiments. Similar to semiconductor structures100aand100b, semiconductor structure100calso includes substrate102and isolation structure106formed in substrate102. In addition, a first diffusion region304aand a second diffusion region304bare formed on opposite sides of isolation structure106. First diffusion region304aand second diffusion region304bmay be doped with different types of dopants. In some embodiments, first diffusion region304ais a p-type diffusion region and second diffusion region304bis an n-type diffusion region.

Materials and methods for forming first diffusion region304aand second diffusion region304bmay be similar to, or the same as, those for forming diffusion region104shown inFIG. 1Aand are not repeated herein.

Gate structures308are formed over substrate102, and contacts312ato312hare formed adjacent to gate structures308, as shown inFIG. 3in accordance with some embodiments. As shown inFIG. 3, contacts312ato312hhave various contact widths. In addition, contact312aincludes a first portion313aand a second portion313a′, and contact width Wcontact 312ais defined as the sum of width Wcontact 313aof first portion313aand width Wcontact 313a′of second portion313a′. That is, contact width is defined as the sum of the widths of the contacts in the same line in the second direction (i.e. substantially parallel to the gate structures) in the same diffusion region.

In some embodiments, the sum of width Wcontact 313aand width Wcontact 313a′is larger than 1.4 times gate length Lgate 308of gate structure308(i.e. Lgate min). That is, contact width Wcontact 312ain first diffusion region104in semiconductor structure100cmay be designed to follow equation (1) described previously.

Similar to semiconductor structures100aand100b, semiconductor structure100cfurther includes an interconnect structure electrically connected with gate structures308and contacts312ato312f. As shown inFIG. 3, the interconnect structure includes first level vias316, first level metal lines320, second level vias324, second level metal lines328, third level vias332, third level metal lines336, fourth level vias340, and fourth level metal lines344in accordance with some embodiments.

In addition, a first level via layer including first level vias316is formed over gate structures308, and a first level metal layer including first level metal lines320is formed over the first level via layer. A second level via layer including second level vias324is formed over the first level metal layer, and a second level metal layer including second level metal lines328is formed over the second level via layer.

Next, a third level via layer including third level vias332is formed over the second level metal layer, and a third level metal layer including third level metal lines336is formed over the third level via layer. Afterwards, a forth level via layer including fourth level vias340is formed over the third level metal layer, and a fourth level metal layer including fourth level metal lines344is formed over the fourth level via layer. Materials and method used to form the metal lines and via shown inFIG. 3may be similar to, or the same as, those used to form the metal lines and vias shown inFIGS. 1A to 1C, and therefore the details of them are not repeated herein.

Semiconductor structure100cmay follow at least one of the equations (1) to (7) described previously. The second level metal layer including second level metal lines328may be seen as the first metal layer in semiconductor structure100c. In some embodiments, pitch Pmetal line 328is larger than or equal to the sum of 0.5 times Pgate min(e.g. pitch Pgate 308of gate structure308) and 0.55 times Lgate min(e.g. length Lgate 308of gate structure308) and 0.18 times Hgate min(e.g. the minimum height among gate structures308). That is, second level metal lines328in semiconductor structure100cmay be designed to follow equation (4) described previously in accordance with some embodiments.

FIG. 4is a top-view representation of a semiconductor structure100din accordance with some embodiments. Similar to semiconductor structure100c, semiconductor structure100dalso includes substrate102, isolation structure106, first diffusion region304a, and second diffusion region304bin accordance with some embodiments.

Gate structures408are formed over substrate102, and contacts412are formed adjacent to gate structures408, as shown inFIG. 4in accordance with some embodiments.

Similar to semiconductor structures100ato100c, semiconductor structure100dincludes an interconnect structure electrically connected with gate structures408and contacts412. As shown inFIG. 4, the interconnect structure includes first level vias416, first level metal lines420, second level vias424, second level metal lines428, third level vias432, and third level metal lines436in accordance with some embodiments.

In addition, a first level via layer including first level vias416is formed over gate structures408, and a first level metal layer including first level metal lines420is formed over the first level via layer. A second level via layer including second level vias424is formed over the first level metal layer, and a second level metal layer including second level metal lines428is formed over the second level via layer. Next, a third level via layer including third level vias432is formed over the second level metal layer, and a third level metal layer including third level metal lines436is formed over the third level via layer.

Materials and method used to form the gate structures, the contacts, the metal lines, and the via shown inFIG. 4may be similar to, or the same as, those shown inFIGS. 1A to 1Cand described previously, and therefore the details of them are not repeated herein.

Semiconductor structure100dmay follow at least one of the equations (1) to (7) described above. As shown inFIG. 4, the first metal layer having the metal lines extending in the first direction is the first level metal layer including first level metal lines420. Therefore, the first level metal layer including first level metal lines420may be seen as the first metal layer in semiconductor structure100d. In some embodiments, pitch Pmetal line 420is larger than or equal to the sum of 0.5 times Pgate min(e.g. pitch Pgate 408of gate structure408) and 0.55 times Lgate min(e.g. length Lgate 408of gate structure408) and 0.18 times Hgate min(e.g. the minimum height among gate structures408). That is, first level metal lines420in semiconductor structure100dmay be designed to follow equation (4) described above.

It should be noted that, although the first metal layer in semiconductor structure100ais referred to as second level metal layer126, a first metal layer in other semiconductor structures may be referred to another metal layer, as long as the metal layer is the metal layer closest to the gate structures among all metal layers having metal lines extending in a direction substantially parallel to its gate structures (e.g. the first direction.) For example, the first metal layer in semiconductor structure100dis referred to as the first level metal layer including first level metal lines420, instead of the second level metal layer including second level metal lines428.

In addition, it should be noted that the layout shown inFIG. 1AtoFIG. 4are merely examples, and the scope of the disclosure is not intended to be limited. For examples, metal layers and via layers may additionally or alternatively be formed in the semiconductor structures, such as semiconductor structures100ato100d, as long as they are designed to follow at least one of the equations (1) to (7).

Generally, one method to increase functional density in a device is to increase the density of the units formed in the device, such as to reduce the pitch of the gate structures or the metal lines. However, as the size of the device shrinks, the manufacturing processes become very complicated. For example, the manufacturing processes may include a great amount of alignment and lithography processes. In addition, it is found that even if the device has an interconnect structure with high metal line density, its performance may not necessary be improved.

Therefore, in some embodiments, a semiconductor structure (e.g. semiconductor structures100ato100d) is designed to follow at least one of the equations (1) to (7) described previously. For example, the metal lines (e.g. metal lines120,128, and136) are designed according to the size and layout of the gate structure (e.g. gate structure108). As a result, the performance of the semiconductor structure may be improved without forming complicated or high-density metal line structure. That is, fewer lithography processes and alignment processes are required. Therefore, the processes of forming the semiconductor structure may be simplified and the cost for forming it may be reduced.

Embodiments for forming a semiconductor structure are provided. The semiconductor structure includes gate structures and an metal lines formed over the gate structures. The layout and/or size of the metal lines is designed according to the layout and/or size of the gate structures, such that the semiconductor structure can have a better performance, such as a lower resistance and/or a higher capacitance.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate and a contact formed adjacent to the gate structures over the substrate. The semiconductor structure further includes a plurality of metal layers formed over the gate structures. In addition, some of the metal layers include metal lines extending in the first direction, and some of the metal layers include metal lines extending in a second direction substantially perpendicular to the first direction. Furthermore, the gate structures follow the following equation:

Pgate minis the minimum value among gate pitches of the gate structures. Lgate minis the minimum value among gate lengths of the gate structures. Hgate minis the minimum value among gate heights of the gate structures.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a plurality of gate structures extending in a first direction formed over a substrate and a contact formed adjacent to the gate structures over the substrate. The semiconductor structure further includes a plurality of metal layers formed over the gate structures. The metal layers include a first metal layer including first metal lines extending in the first direction and a plurality of the first type metal layers including metal lines extending in the first direction formed over the first metal layer. The metal layers include a plurality of the second type metal layers including metal lines extending in a second direction substantially perpendicular to the first direction. In addition, the gate structures and the contact follow the following equation:

Wcontactis the contact width of the contact, and Pgate minis the minimum value among gate pitches of the gate structures. Lgate minis the minimum value among gate lengths of the gate structures, and Hgate minis the minimum value among gate heights of the gate structures.

In some embodiments, a semiconductor structure is provided. The semiconductor structure includes a plurality of gate structures formed over a substrate and a contact formed adjacent to one of the gate structures over the substrate. The semiconductor structure further includes a plurality of metal layers formed over the gate structures. The metal layers include a first metal layer including first metal lines extending in a first direction substantially parallel to the gate structures and a plurality of first type metal layers including metal lines extending in the first direction. The metal layers include a plurality of second type metal layers including metal lines extending in a second direction substantially perpendicular to the first direction. In addition, a distance between the first metal layer and the substrate is smaller than a distance between any one of the first type metal layers and the substrate. Furthermore, pitches of the first metal lines follow the following equation:
P1st metal line min≧0.5Pgate min+0.55Lgate min+0.18Hgate min,

P1st metal line minis the minimum value among pitches of the first metal lines of the first metal layer, and Pgate minis the minimum value among all gate pitches of the gate structures. Lgate minis the minimum value among all gate lengths of the gate structures, and Hgate minis the minimum value among all gate heights of the gate structures.