Protective surface layer on under bump metallurgy for solder joining

A method of fabricating an under-bump metallurgy (UBM) structure that is free of gold processing includes forming a titanium layer on top of a far back of line (FBEOL) of a semiconductor. A first copper layer is formed on top of the titanium layer. A photoresist (PR) layer is formed on top of the first copper layer between traces of the FBEOL to provide a cavity to the FBEOL traces. A top copper layer is formed on top of the first copper layer. A protective surface layer (PSL) is formed on top of the top copper layer.

BACKGROUND

Technical Field

The present disclosure generally relates to semiconductor devices, and more particularly, to creating solder joining interfaces where gold is not desired and methods of manufacturing the same.

Description of the Related Art

Today, integrated circuits are typically produced on semiconductor wafers that undergo various processing steps. Integrated circuits typically include active devices, such as transistors, inductors, capacitors, etc., which are initially isolated, but are interconnected to form functional circuits during these processing steps. To that end, horizontal metal lines as well as vertical interconnects (e.g., vias) can be used. On top of the interconnect structures, solder joining interfaces such as bond pads are formed and exposed on the surface of the respective chip. Electrical connections are made through bond pads to connect the chip to a package substrate or another die. Bond pads can be used for wire bonding or flip-chip bonding, sometimes referred to as controlled collapse chip connection (C4). Such flip-chip packaging uses bumps to establish electrical contact between a chip's I/O pads and the substrate or lead frame of the opposing package. Structurally, a bump includes the bump itself and a so-called under bump metallurgy (UBM) located between the bump and an I/O pad. Receiving pads that accept solder ball during joining/attachment typically have a coating of gold to provide a layer of protection, such that subsequent bonding is not inhibited. The gold layer is easily absorbed into the solder joint during the soldering process.

An UBM generally includes an adhesion layer, a barrier layer and a wetting layer, arranged in this order on the I/O pad. The bumps themselves, based on the material used, are classified as solder bumps, gold bumps, copper pillar bumps and bumps with mixed metals. Copper can be used as an interface to accept the solder balls. However, copper has a tendency to be oxidized during manufacturing processes. The oxidized copper post may lead to poor adhesion of the electronic component to a substrate. The poor adhesion may result in reliability concerns. The oxidized copper post may also lead to underfill cracking along the interface of the underfill and the copper post. The cracks may propagate to low-k layers or the solder used to bond the copper post to the substrate. Gold is typically used as a protective layer to prevent oxidation of the UBM.

SUMMARY

According to one embodiment, an under-bump metallurgy (UBM) structure that is free of gold processing includes a titanium layer on top of a metal layer of a semiconductor. A first copper layer is on top of the titanium layer. A protective surface layer (PSL) is on top of the first copper layer.

In various embodiments, the PSL is selective or non-selective.

In one embodiment, a second copper layer is on top of the first copper layer and below the top copper layer. There may be a nickel layer on top of the second copper layer. The top copper layer may be directly on top of the nickel layer.

In one embodiment, the PSL is removed before the UBM accepts a solder ball to connect to a second semiconductor structure. The PSL can be selected from: titanium (Ti); tungsten-titanium (TiW); chromium (Cr); cobalt (Co); cobalt/tungsten/phosphorus (CoWP); and benzotriazole (BTA).

In one embodiment, the PSL is configured not to be removed before the PSL accepts a solder ball to connect to a second semiconductor structure. The PSL can be selected from: ruthenium (Ru); rhodium (Rh); iridium (Ir); osmium (Os); palladium (Pd); and platinum (Pt).

According to one embodiment, a method of fabricating an under-bump metallurgy (UBM) structure that is free of gold processing includes forming a titanium layer on top of the far back end of the line (BEOL) metal level of a semiconductor. A first copper layer is formed on top of the titanium layer. A photoresist (PR) layer is formed on top of the first copper layer between traces of a metal wiring of the semiconductor to provide a cavity to the metal wiring traces. A top copper layer is formed on top of the first copper layer. A protective surface layer (PSL) is formed on top of the top copper layer.

In one embodiment, a nickel (Ni) layer is deposited on top of the first or second copper layer and below a final top copper layer. The Ni layer may have a thickness of 1 um to 3 um. A second copper layer that is on top of the first copper layer and below the Ni layer can be formed.

In one embodiment, the PSL is removed before the UBM accepts a solder ball to connect to a second semiconductor structure.

In one embodiment, the semiconductor is connected to a second semiconductor by way of a solder bond between the semiconductor and the second semiconductor. The connection may be one of a die to die (D2D), a wafer to wafer (W2W), or die to wafer (D2W).

DETAILED DESCRIPTION

Overview

In one aspect, spatially related terminology such as “front,” “back,” “top,” “bottom,” “beneath,” “below,” “lower,” above,” “upper,” “side,” “left,” “right,” and the like, is used with reference to the orientation of the Figures being described. Since components of embodiments of the disclosure can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. Thus, it will be understood that the spatially relative terminology is intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, for example, the term “below” can encompass both an orientation that is above, as well as, below. The device may be otherwise oriented (rotated 90 degrees or viewed or referenced at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly.

As used herein, the terms “lateral” and “horizontal” describe an orientation parallel to a first surface of a semiconductor substrate or semiconductor body. For example, substrate can be the surface of a wafer or a die.

As used herein, the term “vertical” describes an orientation that is arranged perpendicular to the first surface of the semiconductor substrate or semiconductor body.

As used herein, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together—intervening elements may be provided between the “coupled” or “electrically coupled” elements. In contrast, if an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. The term “electrically connected” refers to a low-ohmic electric connection between the elements electrically connected together.

Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized or simplified embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, may be expected. Thus, the regions illustrated in the figures are schematic in nature and their shapes do not necessarily illustrate the actual shape of a region of a device and do not limit the scope.

It is to be understood that other embodiments may be used and structural or logical changes may be made without departing from the spirit and scope defined by the claims. The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments.

In the interest of not obscuring the presentation of embodiments of the present disclosure, some processing steps or operations may have been combined together for presentation and for illustration purposes and in some instances may have not been described in detail. In other instances, some processing steps or operations may not be described at all. It should be understood that the following description is rather focused on the distinctive features or elements of various embodiments of the present disclosure.

The present invention relates generally to semiconductor structures and methods of manufacture and, more particularly, to providing a protective layer to solder balls in environments where gold is not desired during processing. Today, integrated circuits communicate with devices outside of the chip by way of bond pads. In some scenarios, silicon is joined with silicon by way of under bump metallurgy (UBM) located between the bump and an I/O pad. Receiving pads that accept solder ball during joining/attachment typically have a coating of gold to provide a layer of protection, such that the pads are not contaminated during processing, before the silicon is joined with silicon. The bumps themselves, based on the material used, are classified as solder bumps, gold bumps, copper pillar bumps, as well as bumps with mixed metals. Many of these materials are subject to oxidation, which may lead to poor adhesion when silicon is coupled to silicon to create 3D structures. The poor adhesion causes reliability concerns, such as high leakage currents and poor signal transfer. Such pads that accept solder ball(s) during joining/attachment typically have a coating of gold on their top surface. However, gold processing is not possible in all fab environments. For example, gold can diffuse into Si devices and poison their electrical properties. What is provided herein are structures and methods of solderable receiving pads that are free of gold processing. A protective surface layer allows for a clean solderable surface on a receiving pad that can be applied in most semiconductor fabrication and/or outsourced assembly and test (OSAT) environments.

Example PSL Structure

FIG.1is a cross-section view of a top surface of a semiconductor pad configured to receive a solder ball, consistent with an illustrative embodiment. The semiconductor structure100relates to an under-bump metallization (UBM) of an integrated circuit (IC), which is part of an advanced packaging process that involves creating a thin film metal layer stack between the IC or metal pillars and solder bumps in a flip chip package. The UBM is a structure on top of a far back end of the line (FBEOL) stack of a semiconductor. The level104, representing the final metal wiring layer of the of the FBEOL, may be aluminum (Al) or copper (Cu). There is a titanium layer on top of the FBEOL of the semiconductor. There is a first copper layer (212) on top of the titanium layer. In one embodiment, there is a second copper layer (216) on top of the first copper layer (212). There is a nickel layer (218) on top of the second copper layer. In some embodiments, there is a top copper layer on top of the second copper layer. There is a patterned dielectric layer110, which may be polyimide, which is used to create regions where the UBM discussed herein is formed. The openings created by the dielectric layer110define the wettable area for joining with another silicon. A protective surface layer (PSL)120is then formed thereon. The structure200is ready to receive a solder bond without worry of corrosion and/or contamination of the UBM, thereby providing a reliable solderable surface. Significantly, no gold is used in the formation of the UBM structure or protection thereof. In various embodiments, the PSL is resistant to oxygen plasma reactive ion etch (RIE), is immiscible with copper (Cu), is immiscible with adhesive, resistant to solvent cleaning (e.g., N-methylpyrrolidone (NMP)), and can even be readily removed using a chemical that does not attack the Cu below it. The materials and the manufacturing process related to the PSL are discussed in more detail later.

Example Formation of the PSL Structure

Reference now is made toFIGS.2A to2H, which show different processing steps in the formation of a UBM for non-selectively deposited PSL and selectively deposited PSL, respectively, consistent with illustrative embodiments. As illustrated inFIG.2A, after forming the last (or “far”) back end of the line (FBEOL) metal wiring levels (e.g.,208), the wafer is encapsulated in a final layer of silicon nitride (e.g., nitride passivation204). Various known semiconductor deposition technique can be used, such as chemical vapor deposition (CVD) to deposit the silicon nitride204. In one embodiment, the last metal wiring level208is either Cu or Al and provides connectivity to the back side of the wafer by way of through silicon vias (e.g.,202).

After the nitride204deposition step, a layer of dielectric (which can be polyimide)206is deposited and patterned to expose the sections of the uppermost FBEOL208metal structures that will receive the solder connections of the second chip to be joined, sometimes referred to herein as the second silicon.

FIG.2Billustrates a layer of Ti (e.g., ˜100 to 300 nm in thickness) being deposited on top of the polyimide layer206.FIG.2Cillustrates a second layer of Cu (e.g., ˜100 to 400 nm), which, in one embodiment, is deposited by physical vapor deposition (PFD), sometimes referred to as sputtering, on top of the Ti layer210. For example, the Ti layer210serves as a Cu diffusion barrier and adhesion layer, while the Cu is the seed layer for the subsequent electroplating step.

FIG.2Dillustrates a deposition of a photoresist (PR)214. Standard techniques can be used for the patterning of the PR214. In one embodiment, a layer of Cu (e.g., ˜1-10 um)216is electrodeposited to build up Cu pad structures, as illustrated inFIG.2E. In an alternative embodiment ofFIG.2F, a pad structure comprising a first electrodeposited Cu layer216(e.g., 1-3 um), followed by a plated Ni layer218(e.g., 1-3 um), and a final Cu top layer (e.g., 1-3 um)219is employed. For example, these layers are formed by a sequential plating of Cu216, Ni218, and then Cu219.

FIG.2Gillustrates a subsequent stripping of the PR layer214with a solvent, which may be followed by a chemical etch that is operative to remove the Cu seed216and Ti210layers between the Cu pad structures. Since the wet etch is optimized to have minimal undercut of the pads, the Cu and Ti beneath the pads is not appreciably etched. This top metal structure contacting the last FBEOL metal level is known as the under-bump metallurgy (UBM)220since it will be beneath the solder once the second chip is joined to the current chip.

Next, the protective surface layer PSL230is deposited on top of the UBM structures. For non-selective deposition, the protective surface layer (PSL) coats the entire top surface of the wafer, while selectively deposited layers only grow on the top surface of the Cu owing to its catalytic nature. The PSL protects the UBM from corrosion during processing until the UBM receives a solder ball such that another wafer or chip is coupled thereon.

Example Process

With the foregoing description of a PSL structure100ofFIG.1and the formation thereof as discussed in the context ofFIGS.2A to2G, reference now is made toFIGS.3to9, which describe different processing steps in a 3D wafer flow for a TSV structure.FIG.3illustrates an arrangement300of a carrier structure310aligned above a semiconductor wafer320, consistent with an illustrative embodiment. The carrier310(sometimes referred to herein as a carrier wafer or handler) may comprise a material such as undoped or lightly doped silicon, as well as glass. In some embodiments, the carrier wafer310is transparent to infrared (IR) radiation. The carrier302may have a height ranging from approximately 400 μm to approximately 1000 μm and an overall diameter that corresponds to the diameter of a corresponding semiconductor wafer320that is later coupled thereto. It should be noted that the thickness of the handler can vary depending on its diameter and the requirements for structural stability. The carrier structure310includes a carrier wafer302, a release layer304formed on a bottom surface of the carrier302and an adhesive layer306formed on a bottom surface of the release layer304.

In various embodiments, the release layer304, sometimes referred to herein as the sacrificial layer, may be severable by way of a chemical process and/or infrared (IR) radiation. For the latter, the release layer304may be aluminum (Al) or any other Light-To-Heat-Conversion Release Coating (LTHC) layer that is able to absorb IR radiation efficiently (e.g., materials with a higher IR absorption performance are preferred, but materials with lower IR absorption performance need not be excluded). The release layer304may be deposited on the bottom surface of the carrier302(e.g., below the IR coating202), using a conventional deposition technique, such as, without limitation, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), thermal CVD (THCVD), sputtering, spin-on deposition, etc. In one embodiment, the carrier wafer302, adhesive layer306, and the PSL are each400C resistant.

The semiconductor wafer320may be a typical wafer and may include multiple layers and materials. The multiple layers may comprise semiconductor materials, dielectric materials, and conductive materials. The semiconductor materials may include any known semiconductor materials, such as, for example, undoped Si, n-doped Si, p-doped Si, single crystal Si, polycrystalline Si, amorphous Si, Ge, SiGe, SiC, SiGeC, Ga, GaAs, InAs, InP and all other III/V or II/VI compound semiconductors. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. Typically, the semiconductor wafer may be, for example, several hundred microns thick and may have been thinned from 780 um to approximately 100 um or lower.

In various embodiments, the semiconductor wafer320may include various circuits and structures consistent with integrated circuits. The semiconductor wafer320includes a PSL322on its top side, facing the adhesive layer306of the carrier structure310. The different compositions of the PSL322, the corresponding deposition method, selectivity, and removal thereof are provided inFIG.10. Selectivity relates to whether there is a blanket approach toward the entire wafer/chip or the layer is formed with a specific pattern. Before the wafer or chip is coupled to another wafer or chip, the PSL is removed to allow a strong and reliable bond between the two pieces of silicon. In this regard,FIG.10provides a table1000of example removable PSLs, deposition methods, and removal thereof. The fourth column of table1000provides example ways of removing the PSL. It should be noted that the combination of materials, deposition methods, and removal thereof are provided by way of example and not limitation.FIG.11provides a table1100of different deposition methods of specific PSL material. The materials provided in table1100represent permanent PSLs, which need not be removed before soldering. Some alloys may form intermetallics with Sn, thereby improving solder joint quality.

FIG.4illustrates a semiconductor structure400of a carrier structure310that is bonded to the semiconductor wafer320, consistent with an illustrative embodiment. Upon aligning the carrier structure310with the semiconductor wafer320, the adhesive layer306is used to connect to the PSL322on top of the semiconductor wafer320. By virtue of coupling the carrier structure310to the semiconductor wafer, various desired semiconductor processing steps can be performed, which would not have been able to without the additional structural support offered by the carrier structure310, in view of the fragility of the semiconductor wafer320independently. For example, the thickness of the semiconductor wafer320can be substantially reduced by way of a backside thinning (e.g., from 780 um to 100 um). Various appropriate techniques, such as grinding, can be used to thin the semiconductor wafer320. In this way, the through silicon vias (TSV) can be captured and coupled to pads, a redistribution layer (RDL) provided, flip chip (C4) compatible structure provided (e.g., Cu pedestal/pillar and solder cap404), etc. There is a coating layer402, which may be a silicon nitride, which is used to protect and seal the semiconductor wafer320and the TSV's mechanical integrity during a TSV reveal and capture process. In other embodiments, coating layer402can also be any other dielectric material that has a predetermined level of electrical barrier properties and mechanical strength (e.g., silicon oxynitrides, silicon carbonitrides, and other similar materials not based on silicon). For simplicity and to avoid clutter, a non-selective PSL322is illustrated inFIG.4, while it will be understood that a selective PSL is supported by the teachings herein as well.

In some scenarios, the semiconductor structure400can be further enhanced by further processing to add and/or add additional functionality to the circuits of the semiconductor wafer320. In this regard,FIG.5illustrates a semiconductor structure that includes a second carrier502coupled to the semiconductor structure ofFIG.4, consistent with an illustrative embodiment. In various embodiments, the second carrier can be aligned and held together by tape or any appropriate adhesive606(e.g., to maximize flexibility in processing depending on the application, especially in cases where high topography may require the use of an adhesive layer), which may be removable by subsequent laser and/or chemical processes. In this way, the first carrier structure310can later be removed, while maintaining the structural integrity of the semiconductor wafer320for further processing. Further processing can include, for example, additional wafers coupled and in electrical communication with the semiconductor wafer320. In some embodiments, the second carrier502includes a release layer504on a top surface of the second carrier502. The release layer502, sometimes referred to herein as the second release layer with reference to the first release layer304, can be de-bonded by way of laser and/or chemical processes. For example, the amount of energy applied by a laser to de-bond the first release layer304may be different from that of the second release layer504. In other example, the chemical process to de-bond the first release layer304is different from that of the second release layer504, thereby controlling which release layer to be released at a different stage. In yet another example, one release layer may be de-bonded by IR radiation while the other by chemical processes.

FIG.6illustrates a separation600of the first carrier302from the semiconductor wafer320and the second carrier502, consistent with an illustrative embodiment. In various embodiments, chemical and/or laser techniques may be used to de-bond the first carrier from the remaining structure. For example, IR (i.e., mid IR) laser radiation can be applied through the first carrier302to the release layer604to release the first carrier302from the remaining structure of the semiconductor wafer320. The IR radiation910is operative to break the bonds in the release layer304and de-bond the top of the semiconductor wafer320from the first carrier302. The dashed release layer604indicates breakage in the release layer during the separation from the first carrier302.

FIG.7illustrates the semiconductor structure600ofFIG.6with its first carrier structure302removed, consistent with an illustrative embodiment. Any remaining release layer604can be removed, for example, by a chemical etching process. The semiconductor wafer320is protected by the PSL322. More specifically, the PSL322protects the top of the UBM, which may be copper (Cu), from corrosion during the entire process, including a final cleaning. In some embodiments, the PSL322is removed at a point of readiness for joining (e.g., when the semiconductor wafer320is coupled to another receiving semiconductor wafer320to provide a mechanical and electrical connection therewith. The Cu surface below the PSL is readily cleaned (by flux or other chemical approaches) for top die bond and assembly (B&A). The Cu surface is the top portion of the black metal pads on top of the TSVs.

FIG.8illustrates a semiconductor structure800having one or more die electrically connected to a semiconductor wafer320, consistent with an illustrative embodiment. The bonding of the top die810and812may be performed as die to wafer (D2W), die to die (D2D), or a 3D die to laminate first, and then a top die to 3D die, or any combination thereof. The underfill material802is typically an epoxy that serves to encapsulate the solder structures and provide mechanical integrity to the interface; this underfill enables structural coupling of the top die to the bottom chiplet on the wafer. There is a molding compound817between the top die810and812.

For example, in various embodiments, individual semiconductor devices, such as transistors, resistors, inductors, capacitors, resistors, etc., can be interconnected with wiring of the semiconductor wafer320through the BEOL wiring to the top die810and/or812. Accordingly, electrical connectivity can be provided between the top die810and the semiconductor wafer320. In this way, the semiconductor wafer320is able to communicate outside of the semiconductor wafer320, to one or more semiconductors (e.g., top die810and/or812) electrically connected thereto. Significantly, gold was not used for the processing of the UBM and the stacking of one or more semiconductor structures on top of one another. Indeed, the process may be repeated to create a stacked architecture having multiple levels that are all interconnected based on the teachings herein without the use of gold as a protective layer. Instead, the protection is provided by the PSL.

FIG.9illustrates a semiconductor structure900having underfilling over molding, consistent with an illustrative embodiment. For example, the second carrier502is de-bonded from the semiconductor waver320by way of the release layer504(e.g., by way of a chemical and/or laser release). After dicing the dual die stack with overmolding is joined to packaging substrate such as an organic laminate904.

While the manufacture of a single semiconductor wafer with a die layer on top is being shown for simplicity, it will be understood that any desired number of semiconductor wafers can be stacked based on the teachings herein. Further, while the term wafer is used for discussion purposes, it will be understood that diced chips can be used as well.

CONCLUSION