Bipolar transistor and method of forming the bipolar transistor with a backside contact

NPN and PNP bipolar junction transistors are formed on a wafer in a fabrication process that eliminates the heavily-doped buried layers and the lightly-doped epitaxial layer by forming back side collector contacts that are electrically connected to an interconnect structure on the top side of the wafer with through-the-wafer contacts.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to bipolar transistors and, more particularly, to a bipolar transistor and a method of forming the bipolar transistor with a backside contact.

2. Description of the Related Art

A bipolar transistor is a well-known semiconductor device that is commonly used in integrated circuits. Structurally, a bipolar transistor has three regions, which include an emitter region, a base region, and a collector region. The emitter, base, and collector regions have alternating conductivity types with either an npn or a pnp sequence. One common method of fabricating a bipolar transistor is to vertically arrange the alternating conductivity types.

FIGS. 1A-1Qshow a series of cross-sectional views that illustrate a prior-art method of fabricating vertically-arranged npn and pnp bipolar transistors. As shown inFIG. 1A, the method, which utilizes a p− semiconductor wafer110, begins by implanting the top surface of p− semiconductor wafer110to form an n+ buried layer114in the top surface of p-type semiconductor wafer110. N+ buried layer114can be formed with multiple implant energies to form a thick buried layer.

After n+ buried layer114has been formed, as further shown inFIG. 1A, a mask115is formed and patterned on the top surface of semiconductor wafer110. Following this, the exposed regions of the top surface of p− semiconductor wafer110are implanted to form a p+ buried layer116in the top surface of n+ buried layer114. As a result, p+ buried layer116is separated from p-type semiconductor wafer110by n+ buried layer114. Once p+ buried layer116has been formed, mask115is removed.

After mask115has been removed, as shown inFIG. 1B, an epitaxial layer120is grown on the top surface of p-type semiconductor wafer110. Next, a mask122is formed and patterned on the top surface of epitaxial layer120. Following this, the exposed regions of epitaxial layer120are implanted to form a p− region120P within epitaxial layer120. Epitaxial layer120is formed to have an n-type conductivity and an n− dopant concentration. As a result, the formation of p− region120P also defines an n− region120N within epitaxial layer120. After the implant, mask122is removed.

As shown inFIG. 1C, following the removal of mask122, a number of deep trench isolation regions124and shallow trench isolation regions126are conventionally formed in epitaxial layer120. The deep trench isolation regions124extend down below buried layer114to laterally isolate adjacent n+ buried layers114.

As shown inFIG. 1D, once the trench isolation regions124and126have been formed, a mask130is formed and patterned on the top surface of epitaxial layer120. Following this, the exposed regions of epitaxial layer120are implanted to form a p− base region132within n− region120N of epitaxial layer120. Mask130is then removed.

Next, a mask (not shown) is formed and patterned on the top surface of epitaxial layer120. Following this, the exposed regions of epitaxial layer120are implanted to form an n− base region134within p− region120P of epitaxial layer120. Once n− base region134has been formed within p− region120P, the mask is removed.

After this, as shown inFIG. 1E, a mask136is formed and patterned on the top surface of epitaxial layer120. Following this, the exposed regions of epitaxial layer120are implanted to form an n+ sinker region140within n− region120N of epitaxial layer120. Once n+ sinker region140has been formed, mask136is removed. N+ buried layer114, n− region120N, and n+ sinker region140function as the collector of the npn transistor.

Next, a mask (not shown) is formed and patterned on the top surface of epitaxial layer120. Following this, the exposed regions of epitaxial layer120are implanted to form a p+ sinker region142within p− region120P of epitaxial layer120. Once p+ sinker region142has been formed within p− region120P, the mask is removed. P+ buried layer116, p− region120P, and p+ sinker region142function as the collector of the pnp transistor.

The emitter regions and the base/emitter contact structures can be formed in a number of ways. For example, in a first process, as shown inFIG. 1F, once mask136has been removed, a mask144is formed and patterned on the top surface of epitaxial layer120. Following this, the exposed regions of epitaxial layer120are implanted to form a p+ base contact region150in p− base region132, and a p+ emitter152in n− base region134. Mask144is then removed.

Next, as shown inFIG. 1G, a mask154is formed and patterned on the top surface of epitaxial layer120. After mask154has been formed and patterned, the exposed regions of epitaxial layer120are implanted to form an n+ emitter region156in p− base region132, and an n+ base contact region158in n− base region134. Mask154is removed.

Once mask154has been removed, as shown inFIG. 1H, an isolation layer160is formed over the top of epitaxial layer120. After this, a number of contacts162are conventionally formed to extend through isolation layer160to make electrical connections with n+ sinker region140, p+ sinker region142, p+ base contact region150, p+ emitter region152, n+ emitter region156, and n+ base contact region158.

As shown inFIG. 1I, after the emitter regions and the base/emitter contact structures have been formed, the method next forms an interconnect structure164using conventional fabrication processes. Interconnect structure164includes an insulation region164-I that contacts isolation layer160, a number of metal-1 traces164-M1that are connected to the contacts162, a number of metal-2 traces164-M2, a number of metal pads164-P, and a number of metal vias164-V that connect the metal-1 traces164-M1and the metal-2164-M2traces together, and the metal-2 traces164-M2and the pads164-P together. (Only two metal layers are shown for purposes of clarity. Additional metal layers can also be used.)

The formation of interconnect structure164completes the wafer fabrication sequence, which produces vertically-arranged npn and pnp bipolar transistors. The npn transistor has n+ emitter region156that lies over a portion of p− base region132which, in turn, lies over n− region120N and n+ buried layer114. The pnp transistor has p+ emitter region152that lies over a portion of n− base region134which, in turn, lies over p− region120P and p+ buried layer116.

In a second process of forming the emitter regions and the emitter/base contact structures, as shown inFIG. 1J, once the n+ and p+ sinker regions140and142have been formed, a layer of first poly (poly1)166is deposited on the top surface of epitaxial layer120. Next, a mask168is formed and patterned on the top surface of poly1 layer166. Following this, the exposed regions of poly1 layer166are implanted to form a p+ region166P in poly layer166. After p+ region166P has been formed, mask168is removed.

Next, a mask (not shown), which protects p+ region166P, is formed and patterned on the top surface of poly1 layer166. Following this, the exposed regions of poly1 layer166are implanted to form an n+ region166N in poly1 layer166. Once n+ region166N has been formed in poly1 layer166, the mask is removed.

After the mask has been removed, as shown inFIG. 1K, a non-conductive layer170is formed on the p+ and n+ regions166P and166N of poly1 layer166. A mask172is then formed and patterned on non-conductive layer170. Following this, as shown inFIG. 1L, the exposed regions of non-conductive layer170and poly1 layer166are etched to form a base contact structure174that includes a p+ poly1 region174P with an overlying non-conductive cap174C, a base contact structure176that includes a p+ poly1 region176P with an overlying non-conductive cap176C, a base contact structure178that includes an n+ poly1 region178P with an overlying non-conductive cap178C, and a base contact structure180that includes an n+ poly1 region180P with an overlying non-conductive cap180C. Mask172is then removed.

Once mask172has been removed, as shown inFIG. 1M, an isolation layer is deposited and then anisotropically etched back to form isolation spacers182. Once isolation spacers182have been formed, a layer of second poly (poly2)184is deposited on non-conductive caps174C,176C,178C, and180C and isolation spacers182. Next, a mask186is formed and patterned on the top surface of poly2 layer184. Following this, the exposed regions of poly2 layer184are implanted to form an n+ region184N in poly2 layer184. After n+ region184N has been formed, mask186is removed.

Next, a mask (not shown), which protects n+ region184N, is formed and patterned on the top surface of poly2 layer184. Following this, the exposed regions of poly2 layer184are implanted to form a p+ region184P in poly2 layer184. Once p+ region184P has been formed in poly2 layer184, the mask is removed.

As shown inFIG. 1N, after n+ and p+ regions184N and184P have been formed in poly2 layer184, a mask190is formed and patterned on the top surface of poly2 layer184. Following this, as shown inFIG. 1O, the exposed regions of poly2 layer184are etched to form an n+ emitter contact structure192and a p+ emitter contact structure194. Mask190is then removed.

After this, as shown inFIG. 1P, an isolation layer196is formed over the top of epitaxial layer120. After this, a number of contacts198are conventionally formed to extend through isolation layer196to make electrical connections with n+ emitter contact structure192, n+ sinker region140, p+ emitter contact structure194, and p+ sinker region142; through both isolation layer196and isolation caps174C and176C to contact the p+ poly1 regions174P and176P; and through both isolation layer196and isolation caps178C and180C to contact the n+ poly1 regions178P and180P.

As shown inFIG. 1Q, the method next forms interconnect structure164shown inFIG. 1Iusing conventional fabrication processes. Interconnect structure164includes insulation region164-I that contacts isolation layer196, metal-1 traces164-M1that are connected to the contacts198, metal-2 traces164-M2, metal pads164-P, and metal vias164-V that connect the metal-1 traces164-M1and the metal-2164-M2traces together, and the metal-2 traces164-M2and the pads164-P together.

The formation of interconnect structure164completes the wafer fabrication sequence, which produces vertically-arranged npn and pnp bipolar transistors. The npn transistor has n+ emitter region192A that lies over a portion of p− base region132which, in turn, lies over n− region120N and n+ buried layer114. The pnp transistor has p+ emitter region194A that lies over a portion of n− base region134which, in turn, lies over p− region120P and p+ buried layer116.

Although the above method forms vertically-arranged npn and pnp bipolar transistors, there is a need for alternate methods of forming bipolar transistors.

DETAILED DESCRIPTION OF THE INVENTION

FIGS. 2A-2Nshow a series of cross-sectional views that illustrate an example of a method of fabricating a vertically-arranged npn bipolar transistor and a vertically-arranged pnp bipolar transistor in accordance with the present invention. As described in greater detail below, the present invention utilizes back side collector contacts and through-the-wafer contacts to form vertically-arranged npn and pnp bipolar transistors.

As shown inFIG. 2A, the method utilizes a conventionally-formed p-type semiconductor wafer210that includes a number of deep trench isolation regions212. As further shown inFIG. 2A, the method begins by forming and patterning a mask214on the top surface of p− semiconductor wafer210to expose a region of the top surface of p− semiconductor wafer210.

After mask214has been patterned, the exposed region of p− semiconductor wafer210is implanted to form an n− collector region216of a to-be-formed npn bipolar transistor. Following this, the exposed region of p− semiconductor wafer210is again implanted to form a p− base region218of the to-be-formed npn bipolar transistor. Mask214is then removed.

Once mask214has been removed, as shown inFIG. 2B, a mask220is formed and patterned on the top surface of p− semiconductor wafer210to expose a region of the top surface of p− semiconductor wafer210. After mask220has been patterned, the exposed region of p− semiconductor wafer210is implanted to form an n+ region221. Next, the exposed region of p− semiconductor wafer210is again implanted to form a p− collector region222of a to-be-formed pnp bipolar transistor.

Following this, the exposed region of p− semiconductor wafer210is further implanted to form an n− base region224of the to-be-formed pnp bipolar transistor. Mask220is then removed. (The p-type implant that forms p− collector region222can be omitted if the dopant concentration of semiconductor wafer210is equal to the desired dopant concentration of the pnp collector region.)

The emitter regions and the emitter/base contact structures are next formed in a conventional manner. For example, as shown inFIG. 2C, after following the first process (with respect to the emitter regions and the emitter/base contact structures) as described above and shown inFIGS. 1F-1H, wafer210includes a p+ base contact region150in p− base region218, an n+ emitter region156in p− base region218, an n+ base contact region158in n− base region224, and a p+ emitter region152in n− base region224. In addition, wafer210includes an isolation layer160and a number of contacts162that extend through isolation layer160to make electrical connections with p+ base contact region150, n+ emitter region156, n+ base contact region158, and p+ emitter region152.

In accordance with the present invention, as shown inFIG. 2C, n− collector region216is spaced apart from every contiguous region of n-type conductivity that touches the top surface of semiconductor wafer210, while p− collector region222is spaced apart from every contiguous region of p-type conductivity that touches the top surface of semiconductor wafer210.

As shown inFIG. 2D, after the conventional formation of contacts162, the method of the present invention continues by forming and patterning a mask226on the top surface of isolation layer160. Following this, the exposed regions of isolation layer160and underlying semiconductor wafer210are etched to form a number of deep openings230. Mask226is then removed.

Next, as shown inFIG. 2E, a layer of non-conductive material232is formed to line the bottom and side wall surfaces of the deep openings230. Once non-conductive layer232has been formed, a layer of conductive contact material is deposited on the top surface of isolation layer160to fill up the deep openings230. The layer of contact material is then planarized to form a number of deep contacts234.

As shown inFIG. 2F, the method next forms interconnect structure164shown inFIG. 1Iusing conventional fabrication processes. Interconnect structure164includes insulation region164-I that contacts isolation layer160, metal-1 traces164-M1that are electrically connected to the contacts162and234, metal-2 traces164-M2, pads164-P, and vias164-V that connect the metal-1 traces164-M1and the metal-2164-M2traces together, and the metal-2 traces164-M2and the pads164-P together.

As shown inFIG. 2G, after the conventional formation of interconnect structure164, the bottom surface of semiconductor wafer210is planarized until the deep contacts234are exposed. (The following figures show wafer210flipped over so that the processes performed to the bottom surface are shown performed to the top of the figure.)

After the planarization, as shown inFIG. 2H, an isolation layer236is formed on the bottom surface of semiconductor wafer210to touch the deep contacts234. Next, a mask240is formed and patterned on isolation layer236. Following this, the exposed regions of isolation layer236, semiconductor wafer210, n+ region221, and p− collector region222are etched to form a number of collector openings242. Mask240is then removed.

Once mask240has been removed, as shown inFIG. 2I, a non-conductive layer244is formed on isolation layer236to line the side wall and bottom surfaces of the collector openings242. After this, the bottom surfaces of the collector openings242are implanted to form p+ collector contact regions246in p− collector region222.

As shown inFIG. 2J, following the formation of the p+ collector contact regions246, non-conductive layer244is anisotropically etched to remove non-conductive layer244from isolation layer236and the bottom surfaces of the collector openings242. Next, a layer of conductive contact material is deposited on isolation layer236to fill up the collector openings242. The layer of contact material, which touches the p+ collector contact regions246, is then planarized to form back side collector contacts250.

After this, a mask (not shown) is formed and patterned on isolation layer236. Following this, as shown inFIG. 2K, the exposed regions of isolation layer236, semiconductor wafer210, and n− collector region216are etched to form a number of collector openings252. The mask is then removed. Once the mask has been removed, a non-conductive layer254is formed on isolation layer236to line the side wall and bottom surfaces of the collector openings252.

After non-conductive layer254has been formed, the bottom surfaces of the collector openings252are implanted to form n+ collector contact regions256in n− collector region216. Following the formation of n+ collector contact regions256, non-conductive layer254is anisotropically etched to remove non-conductive layer254from isolation layer236and the bottom surfaces of the collector openings252.

Next, a layer of conductive contact material is deposited on isolation layer236to fill up the collector openings252. The layer of contact material, which touches the n+ collector contact regions256, is then planarized to form back side collector contacts260as shown inFIG. 2K. Once back side contacts260have been formed, as shown inFIG. 2L, a mask262is formed and patterned on isolation layer236. Following this, the exposed regions of isolation layer236are etched to form openings264that expose the deep contacts234. Mask262is then removed. After mask262has been removed, as shown inFIG. 2M, a layer of conductive material266is deposited on isolation layer236to fill up openings264. Once material266has been deposited, a mask268is formed and patterned on conductive material layer266.

Following this, as shown inFIG. 2N, the exposed regions of conductive contact layer266are etched to form a back side pnp collector line270that makes electrical connections to a deep contact234and the back side collector contacts250, and a back side npn collector line272that makes electrical connections to a deep contact234and the back side collector contacts260. Mask268is then removed.

Thus, as shown by the hatched lines inFIG. 2N, a conductive (e.g., metallic) line extends from the backside contacts250to collector line270to deep contact234to metal-1 trace164-M1, via164-V, and metal-2 trace164-M2. Similarly, a conductive (e.g., metallic) line extends from the backside contacts260to collector line272to deep contact234to metal-1 trace164-M1, via164-V, and metal-2 trace164-M2. After the removal of mask268, a layer of protective material274is formed on isolation layer236and the collector lines270and272.

Thus, a method of forming vertically-arranged npn and pnp bipolar transistors has been described. One of the advantages of the present invention is that the present invention eliminates the need to form a buried layer and an epitaxial layer. As further shown inFIG. 2N, the region R1of semiconductor wafer210that lies between n− collector region216and the bottom surface of semiconductor wafer210, and touches n− collector region216and the bottom surface of semiconductor wafer210has a substantially uniform dopant concentration, being free of an n+ buried layer. Similarly, the region R2of semiconductor wafer210that lies between p− collector region222and the bottom surface of semiconductor wafer210, and touches p− collector region222and the bottom surface of semiconductor wafer210has a substantially uniform dopant concentration, being free of a p+ buried layer.

An additional advantage of the present invention is that by utilizing backside and through-the-wafer contacts instead of the conventional heavily-doped sinker region, the present invention also substantially reduces the collector resistance, and increases the operating speed of the npn and pnp bipolar transistors.

FIG. 3shows a cross-sectional view of an example of a vertically-arranged npn bipolar transistor and a vertically-arranged pnp bipolar transistor in accordance with an alternate embodiment of the present invention. The bipolar transistor structures shown inFIG. 3are similar to the bipolar transistor structures shown inFIGS. 2A-2Nand, as a result, utilize the same reference numerals to designate the structures which are common to both.

As shown, the vertically-arranged npn bipolar transistor and the vertically-arranged pnp bipolar transistor ofFIG. 3lack the through-the-die deep contacts234. As a result, the vertically-arranged transistors are more compact than the vertically-arranged transistors ofFIG. 2. The vertically-arranged npn bipolar transistor and the vertically-arranged pnp bipolar transistor ofFIG. 3are formed in the same manner as inFIGS. 2A-2Cand2E-2K, except that one of the deep trench isolation regions212between each laterally adjacent transistor has been eliminated. In addition, the processes associated withFIGS. 2D and 2Erelating to the formation of the through-the-die deep contacts234, and the processes associatedFIGS. 2L-2Nrelating to the formation of the backside traces have been eliminated. As shown inFIG. 3, after the structure inFIG. 2Khas been formed, solder balls310are connected to the back side collector contacts250and260.

FIGS. 4A-4Eshow a series of cross-sectional views that illustrate another example of a method of fabricating a vertically-arranged npn bipolar transistor and a vertically-arranged pnp bipolar transistor in accordance with the present invention. The bipolar transistor structures shown inFIGS. 4A-4Eare similar to the bipolar transistor structures shown inFIGS. 1A-1QandFIGS. 2A-2Nand, as a result, utilize the same reference numerals to designate the structures which are common to both. As noted above, in the present invention, the emitter regions and the emitter/base contact structures of the transistors are formed in a conventional manner.FIGS. 4A-4Eillustrate the present invention with another emitter/base contact structure.

The method of the present invention follows the processes discussed above and described with respect toFIGS. 2A-2Bto form the structure shown inFIG. 4A. Following this, the method follows the second process (with respect to the emitter regions and the emitter/base contact structures) discussed above and described with respect toFIGS. 1J-1Pto form the structure shown inFIG. 4B. As a result, wafer210includes p+ poly1 region174P, non-conductive cap174C, p+ poly1 region176P, non-conductive cap176C, n+ poly1 region178P, non-conductive cap178C, n+ poly1 region180P, non-conductive cap180C, isolation spacers182, n+ emitter contact structure192, and p+ emitter contact structure194. Wafer210includes isolation region196and contacts198.

Further, as above, n− collector region216is spaced apart from every contiguous region of n-type conductivity that touches the top surface of semiconductor wafer210, while p− collector region222is spaced apart from every contiguous region of p-type conductivity that touches the top surface of semiconductor wafer210.

After forming the emitter regions and the emitter/base contact structures as shown inFIGS. 1J-1P, the method of the present invention follows the processes discussed above and described with respect toFIGS. 2D-2Eto form the structure shown inFIG. 4C. After this, the method follows the processes discussed above and described with respect toFIG. 1Qto form the structure shown inFIG. 4D. Next, the method follows the processes discussed above and described with respect toFIGS. 2G-2Nto form the structure shown inFIG. 4E. Thus, a method of forming vertically-arranged npn and pnp bipolar transistors which are free of an n+ buried layer in region R1, an n+ sinker region, a p+ buried layer in region R2, a p+ sinker region, and an epitaxial layer has been described.

FIG. 5shows a cross-sectional view of an example of a vertically-arranged npn bipolar transistor and a vertically-arranged pnp bipolar transistor in accordance with an alternate embodiment of the present invention. The bipolar transistor structures shown inFIG. 5are similar to the bipolar transistor structures shown inFIGS. 4A-4Eand, as a result, utilize the same reference numerals to designate the structures which are common to both.

As shown, the vertically-arranged npn bipolar transistor and the vertically-arranged pnp bipolar transistor ofFIG. 5also lack the through-the-die deep contacts234. As a result, the vertically-arranged transistors are more compact than the vertically-arranged transistors ofFIGS. 4A-4E. The vertically-arranged npn bipolar transistor and the vertically-arranged pnp bipolar transistor ofFIG. 5are formed in the same manner as inFIGS. 4A,4B,4D, and2G-2K, except that one of the deep trench isolation regions212between each laterally adjacent transistor has been eliminated. In addition, the processes associated withFIG. 4C(FIGS. 2D and 2E) relating to the formation of the through-the-die deep contacts234, and the processes associatedFIGS. 2L-2Nrelating to the formation of the backside traces have been eliminated. As shown inFIG. 5, after the structure inFIG. 2Khas been formed, solder balls510are connected to the back side collector contacts250and260.

It should be understood that the above descriptions are examples of the present invention, and that various alternatives of the invention described herein may be employed in practicing the invention. For example, in the present discussion, n+ region221floats. However, contacts similar to the back side collector contacts250(with non-conductive layer244) can be formed through isolation layer236and semiconductor wafer210to make an electrical connection to n+ region221to set a bias voltage on n+ region221, via solder balls or the through-the-die conductive structures. Thus, it is intended that the following claims define the scope of the invention and that structures and methods within the scope of these claims and their equivalents be covered thereby.