Semiconductor memory device

A semiconductor memory device includes a plurality of auxiliary patterns formed over a semiconductor substrate, a plurality of gate line patterns disposed in parallel with one another over the semiconductor substrate between the plurality of auxiliary patterns, and an air gap formed between the plurality of gate line patterns and between each of the plurality of gate line patterns and each of the auxiliary patterns.

CROSS-REFERENCE TO RELATED APPLICATION

Priority is claimed to Korean patent application number 10-2012-0086886, filed on Aug. 8, 2012, the entire disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

1. Field of Invention

Exemplary embodiments of the present invention relate to a semiconductor memory device and a method of manufacturing the same and, more particularly, to a semiconductor memory device including an air gap and a method of manufacturing the same.

2. Description of Related Art

A semiconductor memory device includes a plurality of memory cells configured to store data and devices configured to perform various operations. High-density integration techniques have become necessary to achieve a large data capacity and light weight of a semiconductor memory device. In particular, since memory cells occupy large space in a semiconductor chip, a reduction in size of the memory cells has become a concern.

Among semiconductor memory devices, a NAND flash memory device includes memory cells arranged in units of strings. Isolation layers including insulating materials are filled between these strings, i.e., at isolation regions. The isolation layers function to block electrical influence between adjacent strings, e.g., interference therebetween.

However with increasing integration degree of the semiconductor memory device, the isolation layers including the insulating materials may have limitations in blocking interference between the strings, which may deteriorate reliability of the semiconductor memory device.

BRIEF SUMMARY

Exemplary embodiments of the present invention relate to a semiconductor memory device in which since auxiliary patterns are arranged at both ends of gate line pattern, an air gap is formed between the gate line patterns, and formed between each of the gate line patterns and each of the auxiliary patterns during subsequent processes of depositing an interlayer insulating layer, and a method of manufacturing the same.

Another exemplary embodiments of the present invention relate to a semiconductor memory device in which since adjacent gate line patterns have different lengths from each other, an air gap is formed between the gate line patterns during subsequent processes of depositing an interlayer insulating layer and an air gap is also formed to have a greater length than a shorter gate line pattern among the adjacent gate line patterns, and a method of manufacturing the same.

A semiconductor memory device according to an exemplary embodiment of the present invention may include a plurality of auxiliary patterns formed over a semiconductor substrate; a plurality of gate line patterns disposed in parallel with one another over the semiconductor substrate, and between the plurality of auxiliary patterns; and an air gap formed between the plurality of gate line patterns and formed between each of the plurality of gate line patterns and each of the plurality of auxiliary patterns.

A semiconductor memory device according to another exemplary embodiment of the present invention may include a plurality of gate line patterns disposed in parallel with one another over a semiconductor substrate; and a plurality of air gaps formed between the plurality of gate line patterns, respectively, wherein each of the plurality of gate line patterns has a different length from a gate line pattern adjacent thereto.

A method of manufacturing a semiconductor memory device according to still another exemplary embodiment of the present invention may include forming a plurality of gate line patterns over a semiconductor substrate; forming a plurality of auxiliary patterns over the semiconductor substrate, wherein the plurality of auxiliary patterns are adjacent to both ends of the plurality of gate line patterns; forming an insulating layer over an entire structure including the plurality of gate line patterns and the plurality of auxiliary patterns; and forming an air gap between each of the plurality of gate line patterns and each of the plurality of auxiliary patterns.

DESCRIPTION OF EMBODIMENTS

Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The figures are provided to allow those having ordinary skill in the art to understand the scope of the embodiments of the disclosure. The present invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

It should be readily understood that the meaning of “on” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” means not only “directly on” but also “on” something with an intermediate feature(s) or a layer(s) therebetween, and that “over” means not only directly on top but also on top of something with an intermediate feature(s) or a layer(s) therebetween.

FIGS. 1 to 5Bare cross-sectional views and plan views of a semiconductor memory device according to an embodiment of the present invention for illustrating a method of manufacturing the semiconductor memory device.

Referring toFIG. 1, a tunnel insulating layer101and a first conductive layer102configured as a floating gate may be sequentially formed over a semiconductor substrate100where active regions and isolation regions are defined. The tunnel insulating layer101may include an oxide layer. The first conductive layer102may include a polysilicon layer. For example, the first conductive layer102may include a doped polysilicon layer into which impurities are implanted, or an undoped polysilicon layer into which no impurities are implanted. Subsequently, though not illustrated inFIG. 1, isolation layers may be formed by performing a general isolation process.

Then, a dielectric layer103, a second conductive layer104configured as a control gate, a metal gate layer105and a hard mask layer106may be sequentially stacked over the first conductive layer102. The dielectric layer103may have an ONO structure in which an oxide layer, a nitride layer and an oxide layer are sequentially stacked on top of one another. The dielectric layer103may include a nitride layer and an oxide layer sequentially stacked on top of the other, or include a single layer formed of a high dielectric material. The second conductive layer104may include a polysilicon layer, e.g., a doped polysilicon layer. The metal gate layer105may include a tungsten layer or a titanium layer. The hard mask layer106may include any one of an oxide layer and a nitride layer, or have a dual layer structure including an oxide layer and a nitride layer.

Referring toFIG. 2A, a patterning process may be performed to form gate line patterns107and auxiliary patterns108. The gate line patterns107may be arranged in a direction crossing the isolation regions, and the auxiliary patterns108may be arranged at both ends of the gate line patterns107. The gate line patterns107may be disposed in parallel with one another.

InFIG. 2A, X-X′ refers to a direction vertical to the gate line patterns107, i.e. a direction horizontal to the isolation regions, and Y-Y′ refers to a direction horizontal to the gate line patterns107. Referring toFIG. 2A, a region where the gate line patterns107are adjacent to the auxiliary pattern108is taken along a direction Y-Y′.

Each of the gate line patterns107may include the tunnel insulating layer101, the first conductive layer102, the dielectric layer103, the second conductive layer104, the metal gate layer105and the hard mask layer106that are sequentially stacked over the semiconductor substrate100. In addition, each of the auxiliary patterns108arranged at both ends of the gate line patterns107may include the tunnel insulating layer101, the first conductive layer102, the dielectric layer103, the second conductive layer104, the metal gate layer105and the hard mask layer106that are sequentially stacked over the semiconductor substrate100.

Subsequently, though not shown inFIG. 2A, top portions of the isolation layers of the isolation regions to be exposed may be etched so that the top portions of the isolation layers may be lower than a surface level of the tunnel insulating layer101. In this manner, during subsequent process of forming an air gap, a surface level of the air gap may be lower than that of the tunnel insulating layer101.

FIG. 2Bis a plan view illustrating the semiconductor memory device on which the processes described above with reference toFIG. 2Ais performed. Referring toFIG. 2B, the plurality of gate line patterns107disposed in parallel with one another over the semiconductor substrate100may be spaced apart from each other by a distance d2. In addition, the auxiliary patterns108arranged at both ends of the gate line patterns107may be spaced apart from both ends of the gate line patterns107by a distance d1, wherein the distance d2may be substantially the same as the distance d1.

Referring toFIG. 3, a first insulating layer109may be formed over the entire structure including the gate line patterns107and the auxiliary patterns108. The first insulating layer109may be a spacer insulating layer for forming spacers along sidewalls of gate line patterns configured as a select transistor, among the gate line patterns107. When the first insulating layer109is formed, the gate line patterns107may not be completely filled with the first insulating layer109due to narrow spaces between the gate line patterns107, thereby forming air gaps A1. When the first insulating layer109is formed between the gate line patterns107, and formed between each of the gate line patterns107and each of the auxiliary patterns108, protrusions may be formed at top portions of these patterns, which may result in the formation of the air gaps A1.

Referring toFIG. 4, an etch-back process may be performed to expose the air gaps A1formed between the gate line patterns107and the air gaps A1formed between each of the gate line patterns107and each of the auxiliary patterns108. As a result, top portions of the air gaps A1may have openings. The first insulating layer109may be etched using the above-described etch-back process, so that the first insulating layer109may remain on sidewalls of the gate line patterns107configured as a select transistor.

Referring toFIG. 5A, a second insulating layer110may be formed over the entire structure including the air gaps. The second insulating layer110may be an interlayer insulating layer or may include an oxide layer.

When the second insulating layer110is formed, the openings of the air gaps A1formed by exposing the top portions thereof may be closed off by the second insulating layer110.

FIG. 5Bis a plan view illustrating the semiconductor memory device on which the processes described above with reference toFIG. 5Ahave been performed. Referring toFIG. 5B, an air gap A2may be formed between the gate line patterns107and between each of the gate line patterns107and each of the couple of auxiliary patterns108. In other words, the air gap A2may have a greater length than each of the gate line patterns107. In addition, all of the remaining gate line patterns except for the outermost gate line patterns among the gate line patterns107may be surrounded by the air gap A2.

Each plan view ofFIGS. 6 and 7illustrates a semiconductor memory device with the same configuration as the semiconductor memory device ofFIGS. 1 to 5B, except for changes in shape of auxiliary patterns and changes in shape of air gap.

Referring toFIG. 6, auxiliary patterns108-2may be formed over the semiconductor substrate100. Any two auxiliary patterns facing each other, among the auxiliary patterns108-2, may be disposed at both ends of each of the gate line patterns107. An air gap A2-2may be formed between the gate line patterns107, and formed between each of the gate line patterns107and each of the auxiliary patterns108-2, and between the auxiliary patterns108-2. Each of the auxiliary patterns108-2may have a rectangular shape.

Referring toFIG. 7, auxiliary patterns108-3may be formed over the semiconductor substrate100. Any two auxiliary patterns facing each other, among the auxiliary patterns108-3, may be disposed at both ends of each of the gate line patterns107. An air gap A2-3may be formed between the gate line patterns107, between the gate line patterns107and the auxiliary patterns108-3, and between the auxiliary patterns108-3. Each of the auxiliary patterns108-3may have a triangular shape.

As described above with reference toFIGS. 6 and 7, the auxiliary patterns may vary in shape. The auxiliary patterns may be spaced apart from both ends of the gate line patterns by a predetermined distance, respectively, so that the air gap may have a greater length than each of the gate line patterns.

As described above, according to an embodiment of the preset invention, since auxiliary patterns are arranged at both ends of gate line patterns, an air gap may be formed between the gate line patterns and between each of the gate line patterns and each of the auxiliary patterns during subsequent processes of depositing an interlayer insulating layer. In other words, the air gap may be formed in the spaces between the gate line patterns and in the spaces between each of the gate line patterns and each of the auxiliary patterns, so that electrical interference between the gate line patterns may be avoided.

FIGS. 8 to 12Bare cross-sectional views and plan views of a semiconductor memory device according to another embodiment of the present invention for illustrating the semiconductor memory device.

Referring toFIG. 8, a tunnel insulating layer201and a first conductive layer202configured as a floating gate may be formed over a semiconductor substrate200where active regions and isolation regions are defined. The tunnel insulating layer201may include an oxide layer. The first conductive layer202may include a polysilicon layer. For example, the first conductive layer202may include a doped polysilicon layer into which impurities are implanted, or an undoped polysilicon layer into which no impurities are implanted. Subsequently, though not illustrated inFIG. 8, a general isolation process may be performed to form isolation layers.

Subsequently, a dielectric layer203, a second conductive layer204configured as a control gate, a metal gate layer205and a hard mask layer206may be sequentially formed over the first conductive layer202. The dielectric layer203may have an ONO structure formed by sequentially stacking an oxide layer, a nitride layer and an oxide layer on top of one another. The dielectric layer203may include a nitride layer and an oxide layer sequentially stacked on top of the other, or include a single layer formed of a high dielectric material. The second conductive layer204may include a polysilicon layer, e.g., a doped polysilicon layer. The metal gate layer205may include a tungsten layer or a titanium layer. The hard mask layer206may include any one of an oxide layer and a nitride layer, or include a dual layer structure of an oxide layer and a nitride layer.

Referring toFIG. 9A, gate line patterns207may be formed by performing a patterning process. The gate line patterns207may be arranged in a direction crossing the isolation regions. In addition, the gate line patterns207may be disposed in parallel with one another.

InFIG. 9A, X-X′ refers to a direction vertical to the gate line patterns207, i.e., a direction horizontal to the Isolation regions.

Each of the gate line patterns207may include the tunnel insulating layer201, the first conductive layer202, the dielectric layer203, the second conductive layer204, the metal gate layer205and the hard mask layer206that are stacked over the semiconductor substrate200.

Subsequently, though not illustrated inFIG. 9A, top portions of isolation layers of the isolation regions to be exposed may be etched so that the top portions of the isolation layers may be lower than a surface level of the tunnel insulating layer201. In this manner, during subsequent processes of forming an air gap, a surface level of the air gap may be lower than that of the tunnel insulating layer201.

FIG. 9Bis a plan view illustrating the semiconductor memory device on which the processes described above with reference toFIG. 9Ahave been performed. Referring toFIG. 9B, the gate line patterns207disposed in parallel with one another over the semiconductor substrate200may have different lengths from each other. In other words, each of the gate line patterns207may be longer or shorter than a gate line pattern adjacent thereto, by a predetermined length d3.

Referring toFIG. 10, a first insulating layer208may be formed over the entire structure including the gate line patterns207. The first insulating layer208may be a spacer insulating layer for forming spacers along sidewalls of outermost gate line patterns configured as a select transistor, among the gate line patterns207. When the first insulating layer208is formed, since the gate line patterns207are not completely filled with the first insulating layer208due to narrow spaces between the gate line patterns207, of air gaps A3may be formed. In other words, when the first insulating layer208is formed between the gate line patterns207, the air gaps A3may be formed due to protrusions that are formed at top portions of the gate line patterns207.

Referring toFIG. 11, an etch-back process may be performed to expose the air gaps A3formed between the gate line patterns207. As a result, top portions of the air gaps A3may have openings. The first insulating layer208may be performed using the above-described etch-back process, so that the first insulating layer208may remain on sidewalls of the gate line patterns207configured as a select transistor.

Referring toFIGS. 12A, a second insulating layer209may be formed over the entire structure including the air gaps having the openings. The second insulating layer209may be an interlayer insulating layer or may include an oxide layer.

When the second insulating layer209is formed, the openings of the air gaps formed by exposing the top portions thereof may be closed off by the second insulating layer209.

FIG. 12Bis a plan view illustrating the semiconductor memory device on which the processes described above with reference toFIG. 12Ahave been performed. With reference toFIG. 12B, air gaps A4may be formed between the gate line patterns207. Each of the air gaps A4may have a greater length than a shorter one among gate line patterns adjacent thereto.

Each plan view ofFIGS. 13 and 14illustrates a semiconductor memory device with the same configuration as the semiconductor memory device ofFIGS. 8 to 12B, except for changes in length of gate line patterns and in length of air gaps.

Referring toFIG. 13, among the gate line patterns207, odd-numbered gate line patterns may be shorter than even-numbered gate line patterns. Therefore, the air gaps A4-2formed between the gate line patterns207may have a greater length than the odd-numbered gate fine patterns.

As illustrated inFIG. 14, the gate line patterns207may gradually increase in length to a certain point and then slowly decrease in length. Therefore, for example, one of two gate line patterns adjacent to each other among the gate line patterns207may be longer than the other. Each of the air gaps A4-3formed between the two adjacent gate line patterns may be longer than a shorter one among adjacent gate line patterns.

As described above, according to another embodiment of the present invention, since adjacent gate line patterns have different lengths from each other, an air gap formed between the adjacent gate line patterns may have a greater length than a shorter gate line pattern, so that electrical interference between the gate line patterns may be avoided.

FIG. 15block diagram illustrating the configuration of a memory system according to an embodiment of the present invention.

As illustrated inFIG. 15, a memory system1100according to an embodiment of the present invention may include a non-volatile memory device1120and a memory controller1110.

The non-volatile memory device1120may have the semiconductor memory device described with reference to the above-described embodiments in connection withFIGS. 5B,6,7,12B,13and14. In addition, the non-volatile memory device1120may be a multi-chip package composed of a flash memory chips.

The memory controller1110may be configured to control the non-volatile memory device1120. The memory controller1110may include SRAM1111, a CPU1112, a host interface1.113, an ECC1114and a memory interface1115. The SRAM1111may function as an operation memory of the CPU1112. The CPU1112may perform the general control operation for data exchange of the memory controller1110. The host interface1113may include a data exchange protocol of a host being coupled to the memory system1100. In addition, the ECC1114may detect and correct errors included in a data read from the non-volatile memory device1120. The memory interface1115may interface with the non-volatile memory device1120. The memory controller1110may further include RCM that stores code data to interface with the host.

The memory system1100having the above-described configuration may be a solid state disk (SSD) or a memory card in which the memory device1120and the memory controller1110are combined. For example, when the memory system1100is an SSD, the memory controller1110may communicate with the outside (e.g., a host) through one of the interface protocols including USB, MMC, PCI-E, SATA, PATH, SCSI, ESDI and IDE.

FIG. 16is a block diagram illustrating the configuration of a computing system according to an embodiment of the present invention.

As illustrated inFIG. 16, a computing system1200according to an embodiment of the present invention may include a CPU1220, RAM1230, a user interface1240, a modem1250and a memory system1210that are electrically coupled to a system bus1260. In addition, when the computing system1200is a mobile device, a battery may be further included to apply operating voltage to the computing system1200. The computing system1200may further include application chipsets, a Camera Image Processor (CIS) and mobile DRAM.

As described above in connection withFIG. 15, the memory system210may include a non-volatile memory1212and a memory controller1211.

According to an embodiment of the present invention, an air gap may be formed between gate line patterns and between each of the gate line patterns and each of auxiliary patterns, so that electrical interference between the gate line patterns may be avoided.

In addition, according to another embodiment of the present invention, adjacent gate line patterns may have different lengths from each other, and an air gap formed between the gate line patterns may have a greater length than a shorter gate line pattern, so that electrical interference between the gate line patterns may be avoided.