Stacked-chip packages in package-on-package apparatus, methods of assembling same, and systems containing same

A stacked-chip apparatus includes a package substrate and an interposer with a chip stack disposed with a standoff that matches the interposer. A package-on-package stacked-chip apparatus includes a top package disposed on the interposer.

TECHNICAL FIELD

Disclosed embodiments relate to semiconductor microelectronic devices and processes of packaging them.

DETAILED DESCRIPTION

Reference will now be made to the drawings wherein like structures may be provided with like suffix reference designations. In order to show the structures of various embodiments most clearly, the drawings included herein are diagrammatic representations of integrated circuit structures. Thus, the actual appearance of the fabricated structures, for example in a photomicrograph, may appear different while still incorporating the claimed structures of the illustrated embodiments. Moreover, the drawings may only show the structures necessary to understand the illustrated embodiments. Additional structures known in the art may not have been included to maintain the clarity of the drawings. Although a processor chip and a memory chip may be mentioned in the same sentence, it should not be construed that they are equivalent structures.

Reference throughout this disclosure to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with which the embodiment is included in at least one embodiment of the present invention. The appearance of the phrases “in one embodiment” or “in an embodiment” in various places throughout this disclosure are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Terms such as “upper” and “lower” may be understood by reference to the X-Z or Y-Z coordinates, and terms such as “adjacent” may be understood by reference to the illustrated X-Y coordinates.

FIG. 1ais a cross-section elevation of a mounting substrate and interposer apparatus100for a stacked-chip package according to an example embodiment. The apparatus100is depicted vertically (Z-direction) in exploded view including a package substrate110and an interposer130. The package substrate110includes a die side112to accept a processor, and a land side114for coupling to outside communication such as a board. The “board” may be an external- or near-external structure for a hand-held device such as a wireless communicator. The package substrate110includes a bottom-chip footprint116on the die side112. The bottom-chip footprint116may be ascertained in subsequent drawings disclosed herein by projecting illustrated processors on respective die sides of illustrated mounting substrates.

The package substrate110includes a land-side ball-grid array, one ball pad of which is indicated with reference numeral118. In an embodiment, the ball pad118includes a surface finish120. The surface finish120is configured to be a less electronegative metal than the ball pad118. The surface finish120is formed by electroplating according to an embodiment. Alternatively, the surface finish120is formed by electroless plating.

In an example embodiment, the ball pad118is copper and the surface finish120is a nickel-palladium-gold alloy plated onto the copper. In an embodiment, the surface finish120is a nickel-gold alloy plated onto the copper. In an embodiment, the surface finish120is copper-gold plated onto the copper.

In an example embodiment, the ball pad118is copper and the surface finish120is an organic solderability preservative (OSP) composition such as aryl-phenylimidazole. In an example embodiment, the surface finish120has a thickness from 1,000 Å to 2,000 Å and is aryl-phenylimidazole.

Similarly, the package substrate110includes a die-side ball-grid array, one ball pad of which is indicated with reference numeral122and the ball pad122includes a surface finish124. The ball pad122and surface finish124may be an embodiment similar to those found on the board side114. In an embodiment, the die-side ball-grid array122is defined by a solder resist126. Similarly, the solder resist126may define die-bump pads found within the bottom chip footprint116, and one of which is indicated with reference numeral128. The package substrate110is depicted between the die side112and the land side114with interconnect and interlayer dielectric structures that are illustrative but not limiting.

The apparatus100is assembled with the interposer130that mates to the die-side ball grid array122. The interposer130includes a die side132and a top side134and has an offset height136configured to match an offset height138above the package substrate110for a multiple die stack (MDS) that will occupy the bottom-chip footprint116. The interposer130may include a core140and interconnects142. In an embodiment, die-side electrical bumps144and top-side electrical bumps146are coupled to the interconnects142.

FIG. 1bis a cross-section elevation of the apparatus depicted inFIG. 1aafter further processing according to an embodiment. The apparatus101illustrates that the interposer offset height136matches the package-substrate offset height138(FIG. 1a). The bottom-chip footprint116is surrounded by the interposer130and will surround the multiple-die stack that is to be assembled as part of the apparatus101.

FIG. 1cis a cross-section elevation of the apparatus depicted inFIG. 1bafter further processing according to an embodiment. The apparatus102has been fortified with an interposer fill material148that stabilizes bonding between the package substrate110and the interposer130.

A bottom chip150is placed within the bottom-chip footprint116(FIG. 1b). In an embodiment, the bottom chip150is a flip chip150that has been flip-chip bonded though a chip ball array, one electrical bump of which is referenced with numeral152. In an embodiment, an underfill154has been flowed to fortify bonding between the bottom chip150and the package substrate110. In a processing embodiment, reflow of the electrical bumps152is carried our during simultaneous curing of the underfill154. In a processing embodiment, reflow of the electrical bumps152is carried our during simultaneous curing of the fill material148.

In an embodiment, the bottom chip150is processed to reflow the electrical bumps152, followed by placement of the underfill154after bump reflow.

FIG. 1dis a cross-section elevation of the apparatus depicted inFIG. 1cafter further processing according to an embodiment. The apparatus102depicted inFIG. 1chas been further processed to achieve a mixed-die apparatus103that will become part of a package-on-package (PoP) stacked chip apparatus. The mixed-die apparatus103includes an inter-die adhesive156that has been formed on the bottom chip150, and a top chip158has been mounted on the adhesive156. The top chip158is supported by the bottom chip150. Hereinafter, a chip stack that originates with a bottom chip (e.g. chip150) disposed on the package substrate110and that terminates with a subsequent chip (e.g. chip158) may also be referred to as a 3-dimensional (3D) chip stack.

In an embodiment, the top chip158is coupled to the package substrate110by wire bonds, one of which is indicated by reference numeral160. Consequently, the mixed-stack apparatus103includes a flip chip150mounted on the package substrate110and a wire-bond chip158disposed above the flip chip150. The offset height136of the interposer130therefore accommodates the height of the mixed-stack that includes the wire bonds160as well as the top chip158the adhesive156, the bottom chip150, and the offset created by the electrical bumps152(seen inFIG. 1c).

In a process embodiment, a stack encapsulation162has been filled to isolate the mixed-die stack and to further prevent the bond wires160from moving. The stack encapsulation162may be used also to protect the mixed-die stack from environmental and handling dangers. The stack encapsulation162may also be used to facilitate heat transfer away from the mixed-die stack. In an embodiment, no stack encapsulation is used.

In an embodiment, the bottom chip150is a processor and the top chip158is a radio-frequency (RF) device. The mixed-die stack may be used in a wireless communicator (e.g. a cellular telephone) such as a smart phone.

FIG. 1eis a cross-section elevation of a package-on-package (PoP) stacked chip apparatus104that has assembled with the apparatus depicted inFIG. 1dafter further processing according to an example embodiment. The bottom chip150and the top chip158are set within the interposer offset136and a top package164has been mated to the top side134of the interposer130. The top package164may have a mounting substrate170for communication to the bottom chip150and/or the top chip158. The top package164is depicted as a wire-bond enabling solution such as for an original-equipment manufacturer. Two wire-bonded dice are depicted in the top package164. A die located in the top package164may be referred to as a microelectronic device. In an embodiment, the mixed-stack apparatus103depicted inFIG. 1dis provided to accommodate a top package164such as for a smart phone, where smart-phone specific microelectronic devices are in the top package164and support microelectronic devices are in the chip stack.

In an embodiment, a top-package fill material172stabilizes bonding between the interposer130and the top package164.

It can be seen that the mixed stack of the bottom chip150and top chip158have been accommodated by the interposer offset136such that the top package164does not interfere with the mixed stack. Consequently, the PoP stacked-chip apparatus is assembled with sufficient interposer offset136to accommodate an offset height of the chip stack that may vary depending upon a specific application.

FIG. 2ais a cross-section elevation of a mounting substrate and interposer apparatus200for a stacked-die package according to an example embodiment. The apparatus200is similar to the apparatus103depicted inFIG. 1dand has been processed similarly by seating an interposer230upon a package substrate210.

A stacked-chip apparatus200is depicted. The stacked-chip apparatus200includes a bottom chip250and a top chip258. In an embodiment, the bottom chip250is a processor and the top chip258is a memory die that is coupled by through-silicon via (TSV) technology. A single TSV274is detailed within the dashed circle. In an embodiment, the top chip258is a level-2 (L2) memory cache (where L0 and L1 are within the processor250) such as a static random-access memory (SRAM) for the processor250. The bottom chip250and the top chip258are a 3D

Consequently, the stacked-chip apparatus200includes the flip chip250mounted on the package substrate210and the TSV-coupled chip258disposed above the flip chip250. The offset height236of the interposer230therefore accommodates the height of the stacked-chip configuration. Processing of the bottom chip250may be done by any embodiment disclosed with respect to the bottom chip150depicted inFIG. 1cand elsewhere.

In an embodiment, the top chip258is a memory die such as a random-access memory (RAM) die258. In an embodiment, the top chip258is a memory die such as a dynamic random-access memory (DRAM) die258. In an embodiment, the top chip258is a memory die such as a static random-access memory (SRAM) die258. In an embodiment, the top chip258is a memory die such as a erasable programmable memory (EPROM) die258. Other memory die configurations may be used according to a specific application.

In an embodiment, the top chip258includes a radio-frequency device (RF) tag. In an embodiment, the top chip258includes a radio-frequency device for wireless communication.

In a process embodiment, a stack encapsulation262has been filled to isolate the chip stack. The stack encapsulation262may be used also to protect the chip stack from environmental and handling dangers. The stack encapsulation262may also be used to facilitate heat transfer away from the chip stack. In an embodiment, no stack encapsulation is used.

FIG. 2bis a cross-section elevation of a PoP stacked-chip apparatus201that has assembled from the apparatus depicted inFIG. 2aafter further processing according to an example embodiment. The bottom chip250and the top chip258are set within the interposer offset236and a top package264has been mated to the top side234of the interposer230. The top package264may have a mounting substrate270for communication to the bottom chip250and/or the top chip258. The top package is depicted as TSV enabling solution such as for an original-equipment manufacturer. In an embodiment, the chip stack apparatus200depicted inFIG. 2ais provided to accommodate a top package264such as for a smart phone.

It can be seen that the chip stack of the bottom chip250and top chip258have been accommodated by the interposer offset236such that the top package264does not interfere with the chip stack.

Details illustrated and described with respect toFIG. 1emay also be inferred by observing similar structures and spaces depicted inFIG. 2bwhere appropriate.

It can now be understood that processing to achieve the PoP stacked-chip apparatus201may be similar to processing to achieve the PoP stacked-chip apparatus104depicted inFIG. 1e.

In an example embodiment, I/O density between the bottom chip150and the top chip158is in a range between 128 bits per die (such as when the top chip258is a DRAM die) and 252 bits/die. In an example embodiment, I/O speed between the processor250and the subsequent chip258is between 10 Gb/s and 1 Tb/s (tera bits per second). Along a 10 mm edge section of the subsequent chip250as a DRAM device, total bandwidth is from 160 GB/s to 320 GB/s. As a package, the PoP apparatus201has a total package bandwidth between 640 GB/s to 6400 GB/s according to an embodiment, where the processor250and the subsequent chip258each may operate at or above 256 bits. The I/O speed may run slower below 10 Gb/s (such as below 7 Gb/s) where a given application may be useful at this range.

FIG. 3ais a cross-section elevation of a mixed-die apparatus300during processing according to an example embodiment. A bottom chip350is placed on a package substrate310that may be similar to the package substrate110depicted inFIG. 1c.In an embodiment, the bottom chip350is a flip chip350that has been flip-chip bonded though a chip ball array, one electrical bump of which is referenced with numeral352. In an embodiment, an underfill354has been flowed to fortify bonding between the bottom chip350and the package substrate310. In a processing embodiment, reflow of the electrical bumps352is carried our during simultaneous curing of the underfill354.

Processing of the bottom chip350may be done by any embodiment disclosed with respect to the bottom chips150,250, and elsewhere depicted in this disclosure.

FIG. 3bis a cross-section elevation of the apparatus depicted inFIG. 3aafter further processing according to an embodiment. The apparatus301depicted inFIG. 3bhas been further processed to achieve a mixed-stack apparatus301that will be part of a PoP stacked-chip apparatus. The mixed-stack apparatus301includes an inter-die adhesive356that has been formed on the bottom chip350, and a top chip358has been mounted on the adhesive356. The top chip358is supported by the bottom chip350.

In an embodiment, the top chip358is coupled to the package substrate310by wire bonds, one of which is indicated by reference numeral360. Consequently, the mixed-stack apparatus301includes a flip chip350mounted on the package substrate310and a wire-bond chip358disposed above the flip chip350. An offset height336will be matched by the offset height of an interposer in further processing. It will now be clear that assembly of the mixed-stack precedes assembly of an interposer to the package substrate310.

Similar to the mixed-die stack apparatus embodiment depicted inFIG. 1d, the interposer to be assembled will accommodate the height of the mixed-die stack that includes the wire bonds360as well as the top chip358the adhesive356, the bottom chip350and the offset created by the electrical bumps352. In an embodiment, no stack encapsulation is used.

In an embodiment, the bottom chip350is a processor and the top chip358is a RF device. The mixed-die stack may be used in a wireless communicator such as a smart phone. Details illustrated and described with respect to previously disclosed embodiments may also be inferred by observing similar structures and spaces depicted inFIG. 3bwhere appropriate. Additionally, previously disclosed I/O and bandwidth capabilities may be inferred with respect to the PoP stacked-chip embodiments depicted and described inFIG. 3b.

FIG. 4is a cross-section elevation of a mounting substrate and interposer apparatus400for a stacked-die package according to an example embodiment. The apparatus400is similar to the apparatus200depicted inFIG. 2aexcept assembly of an interposer is carried out after assembly of the stacked dice450and458.

A stacked-chip apparatus400is depicted. The stacked-chip apparatus400includes a bottom chip450and a top chip458. In an embodiment, the bottom chip450is a processor and the top chip458is a memory die that is coupled by through-silicon via (TSV) technology. A single TSV474is detailed within the dashed circle. In an embodiment, the top chip558is a level-2 (L2) memory cache (where L0 and L1 are within the processor450) such as a static random-access memory (SRAM) for the processor450. Processing of the bottom chip450may be done by any embodiment disclosed with respect to the bottom chips150,250,350, and elsewhere depicted in this disclosure.

Consequently, the stacked-chip apparatus400includes the flip chip450mounted on the package substrate410and the TSV-coupled chip458disposed above the flip chip450. The offset height436of the stacked chips450and458will be matched by an interposer that will be assembled. The interposer will therefore accommodate the height of the stacked-chip configuration.

In an embodiment, the top chip458is a memory die such as a random-access memory (RAM) die458. In an embodiment, the top chip458is a memory die such as a dynamic random-access memory (DRAM) die458. In an embodiment, the top chip458is a memory die such as a static random-access memory (SRAM) die458. In an embodiment, the top chip458is a memory die such as a erasable programmable memory (EPROM) die458. Other memory die configurations may be used according to a specific application.

In an embodiment, the top chip458includes a radio-frequency device (RF) tag. In an embodiment, the top chip458includes a radio-frequency device for wireless communication. In a process embodiment, a stack encapsulation will be filled into the recess the interposer will form around the chip stack.

Details illustrated and described with respect to previously disclosed embodiments may also be inferred by observing similar structures and spaces depicted in4where appropriate. Additionally, previously disclosed I/O- and bandwidth capabilities may be inferred with respect to the PoP stacked-chip embodiments depicted and described inFIG. 4.

FIG. 5is a cross-section elevation of a mixed-die apparatus500that will support a package-on-package apparatus according to an embodiment. The mixed-die apparatus500includes a bottom chip550, a top chip558, and an intermediate chip551. The top chip558and the intermediate chip551are supported by the bottom chip550. The bottom chip550is a flip chip that may be referred to as a first chip, the intermediate chip551is a TSV-coupled chip that may be referred to as a second chip551, and the top chip558is a wire-bonded chip that may be referred to as a subsequent chip558. In an embodiment, the number of TSV-coupled chips disposed immediately above the bottom chip550is in a range from 2 to 8, followed by the top chip556. Processing of the bottom chip550may be done by any embodiment disclosed with respect to the bottom chips depicted in this disclosure.

In an embodiment, the top chip558is coupled to the package substrate510by wire bonds, one of which is indicated by reference numeral560. The offset height536of the interposer530therefore accommodates the height of the mixed-die stack that includes the wire bonds560as well as the top chip558, the intermediate chip551, the bottom chip550, and the offset created by the electrical bumps and inter-chip adhesives and spacers as illustrated.

In a process embodiment, a stack encapsulation562has been filled to isolate the mixed-die stack and to further prevent the bond wires560from moving. The stack encapsulation562may be used also to protect the mixed-die stack from environmental and handling dangers. The stack encapsulation562may also be used to facilitate heat transfer away from the mixed-die stack. In an embodiment, no stack encapsulation is used.

In an embodiment, the first chip550is a processor, the intermediate chip551is a TSV RAM chip, and the top chip558is an RF device. The mixed-die stack may be used in a wireless communicator such as a smart phone.

Details illustrated and described with respect to previously disclosed embodiments may also be inferred by observing similar structures and spaces depicted inFIG. 5where appropriate. Additionally, previously disclosed I/O and bandwidth capabilities may be inferred with respect to the PoP stacked-chip embodiments depicted and described inFIG. 5.

FIG. 6is a cross-section elevation of a mixed-die apparatus600that will support a PoP mixed-die apparatus according to an embodiment. The mixed-die apparatus600includes a bottom chip650, a top chip659, and several intermediate chips651,653, and658. The top chip659and the intermediate chips651,653, and658are supported by the bottom chip650. Processing of the bottom chip650may be done by any embodiment disclosed with respect to the bottom chips depicted in this disclosure.

The mixed-die apparatus600is an embodiment with multiple TSV chips and multiple wire-bond chips. The bottom chip650is a flip chip that may be referred to as a first chip. The intermediate chip651is a TSV-coupled chip that may be referred to as a second chip651. The intermediate chip653is a TSV-coupled chip that may be referred to as a third chip653. The intermediate chip658is a wire-bonded chip that may be referred to as a fourth chip658. And the top chip659is a wire-bonded chip that may be referred to as a subsequent chip659. In an embodiment, the number of TSV-coupled chips disposed immediately above the bottom chip550and below the wire-bond chip658is in a range from 2 to 8.

In an embodiment, both the wire-bond chip658and the wire-bond chip559are coupled to the package substrate610by wire bonds660and661, respectively. The offset height636of the interposer630therefore accommodates the height of the mixed-die stack that includes the wire bonds660and661as well the entire chip stack and electrical bumps and inter-chip adhesives and spacers as illustrated.

In a process embodiment, a stack encapsulation662has been filled to isolate the mixed-die stack and to further prevent the bond wires660and661from moving. The stack encapsulation662may be used also to protect the mixed-die stack from environmental and handling dangers. The stack encapsulation662may also be used to facilitate heat transfer away from the mixed-die stack. In an embodiment, no stack encapsulation is used.

Details illustrated and described with respect to previously disclosed embodiments may also be inferred by observing similar structures and spaces depicted inFIG. 6where appropriate. Additionally, previously disclosed I/O and bandwidth capabilities may be inferred with respect to the PoP stacked-chip embodiments depicted and described inFIG. 6.

FIG. 7is a cross-section elevation of a mixed-die apparatus700that will support a package-on-package apparatus according to an embodiment. The mixed-die apparatus700includes a bottom chip750, a top chip759, and several intermediate chips751,753, and758. The top chip759and the intermediate chips751,753, and758are supported by the bottom chip750. The mixed-die apparatus700is an embodiment with multiple TSV chips and multiple wire-bond chips where a wire-bond chip is below a TSV chip.

The bottom chip750is a flip chip that may be referred to as a first chip. The intermediate chip751is a TSV-coupled chip that may be referred to as a second chip751. The intermediate chip758is a wire-bonded chip that may be referred to as a third chip758. The intermediate chip753is a TSV-coupled chip that may be referred to as a fourth chip753. And the top chip759is a wire-bonded chip that may be referred to as a subsequent chip759. In an embodiment, the second chip751is a memory cache chip that supports the bottom chip750. Processing of the bottom chip750may be done by any embodiment disclosed with respect to the bottom chips depicted in this disclosure.

In an embodiment, the fourth chip753is a TSV memory cache chip the supports the subsequent chip759. In an example embodiment, the mixed-die apparatus700is part of a PoP stacked-chip apparatus such as a super-smart phone. The bottom chip750in this embodiment is a processor and the second chip751is a memory cache. The intermediate chip758is a wire-bonded device for processing online communications. The top chip759is a global-positioning system (GPS) chip that is supported by the fourth chip753, which acts as a cache for the GPS chip759. Further in an example embodiment, a top package

In an embodiment, the fourth chip753is used as a support and interface between the intermediate chip758and the top chip759. For example, the fourth chip753has a TSV that allows direct communication between the top chip759and the intermediate chip758.

In an embodiment, both the wire-bond chip758and the wire-bond chip759are coupled to the package substrate710by wire bonds760and761, respectively. The offset height736of the interposer730therefore accommodates the height of the mixed-die stack that includes the wire bonds760and761as well the entire chip stack and electrical bumps and inter-chip adhesives and spacers as illustrated.

In a process embodiment, a stack encapsulation762has been filled to isolate the mixed-die stack and to further prevent the bond wires760and761from moving. The stack encapsulation662may be used also to protect the mixed-die stack from environmental and handling dangers. The stack encapsulation762may also be used to facilitate heat transfer away from the mixed-die stack. In an embodiment, no stack encapsulation is used.

Details illustrated and described with respect to previously disclosed embodiments may also be inferred by observing similar structures and spaces depicted inFIG. 6where appropriate. Additionally, previously disclosed I/O and bandwidth capabilities may be inferred with respect to the PoP stacked-chip embodiments depicted and described inFIG. 6.

FIG. 8is a process and method flow diagram800according to an example embodiment.

At810, a process includes forming an interposer on a package substrate. The interposer is configured to have an offset that will match a chip stack to be placed on the package substrate.

At820, the process includes forming a chip stack on the package substrate. Where process820precedes process810, the interposer is placed on the package substrate after forming the chip stack. Where process820follows process810, the chip stack is formed within a recess left by the interposer. In an embodiment, the process commences at810and terminates at820.

At830, the process includes filling a stack encapsulation to isolate the chip stack. In an embodiment, the process commences at810and terminates at830.

At840the process includes forming a top package on the interposer. In an embodiment, the process commences and terminates at840.

FIG. 9is a schematic of a computer system900according to an embodiment. The computer system900(also referred to as the electronic system900) as depicted can embody a PoP stacked-chip apparatus according to any of the several disclosed embodiments and their equivalents as set forth in this disclosure. In an embodiment, the electronic system900is a computer system that includes a system bus920to electrically couple the various components of the electronic system900. The system bus920is a single bus or any combination of busses according to various embodiments. The electronic system900includes a voltage source930that provides power to the integrated circuit910. In some embodiments, the voltage source930supplies current to the integrated circuit910through the system bus920.

The integrated circuit910is electrically coupled to the system bus920and includes any circuit, or combination of circuits according to an embodiment. In an embodiment, the integrated circuit910includes a processor912that can be of any type. As used herein, the processor912may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. In an embodiment, SRAM embodiments are found in memory caches of the processor. Other types of circuits that can be included in the integrated circuit910are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit914for use in wireless devices such as cellular telephones, pagers, portable computers, two-way radios, and similar electronic systems. In an embodiment, the processor910includes on-die memory916such as static random-access memory (SRAM) and the SRAM may include a 6T SRAM cell with independent S/D sections of the access and pull-down regions. In an embodiment, the processor910includes embedded on-die memory916such as embedded dynamic random-access memory (eDRAM).

In an embodiment, the electronic system900also includes an external memory940that in turn may include one or more memory elements suitable to the particular application, such as a main memory942in the form of RAM, one or more hard drives944, and/or one or more drives that handle removable media946, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory940may also be embedded memory948such as the microelectronic die embedded in a processor mounting substrate according to an embodiment.

In an embodiment, the electronic system900also includes a display device950, an audio output960. In an embodiment, the electronic system900includes an input device such as a controller970that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system900.

As shown herein, the integrated circuit910can be implemented in a number of different embodiments, including a PoP stacked-chip apparatus according to any of the several disclosed embodiments and their equivalents, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a PoP stacked-chip apparatus according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the several disclosed PoP stacked-chip apparatus embodiments and their equivalents.

It will be readily understood to those skilled in the art that various other changes in the details, material, and arrangements of the parts and method stages which have been described and illustrated in order to explain the nature of this invention may be made without departing from the principles and scope of the invention as expressed in the subjoined claims.