Display driver and built-in-phase-calibration circuit thereof

A phase-calibration circuit including a pattern generator, a phase adjuster, a rotate register unit, a detector unit, and an optimization unit is disclosed. The pattern generator generates a clock pattern and a data pattern for a target circuit. The phase adjuster adjusts a phase between a first clock and a first data output from the target circuit according to a control data for outputting a second clock and a second data. The rotate register unit provides the control data to the phase adjuster. The detector unit detects phase relationship between the second clock and the second data for outputting a detection result. The optimization unit records the control data output from the rotate register unit in accordance with the detection result, and selects one of the control data as a calibration control data, and controls the rotate register unit to output the calibration control data to the phase adjuster.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a signal phase calibration method. More particularly, the present invention relates to a signal phase calibration circuit and a display driver with a built-in-phase-calibration circuit.

2. Description of Related Art

Signal offsets may occur due to factors such as fabrication process, environment, signal transmission path, and etc., and therefore cause a setup time problem and a hold time problem.FIG. 1Ais a diagram illustrating a signal path.FIG. 1Bis a timing diagram of the signals ofFIG. 1A. A signal source (a transmitter110) transmits the signals (clock CLK10and data D10) to a receiver130via a signal path120. Therefore, the receiver130may output a corresponding clock CLK11and a data D11to a secondary circuit (not shown) according to the received clock CLK10and the data D10.

The clock CLK11and the data D11may have signal offsets during transmission. InFIG. 1B, signal offsets occur such that the transition of the data D11is close to the rising edge of the clock CLK11. Thus a set-up time problem is caused because the rising edge of the clock CLK11appears within the required setup time for the transition of the data D11, and the data D11would be erroneously sampled by the secondary circuit (not shown) based on the rising edge of the clock CLK11. Moreover, a hold time problem may be caused if the hold time of the clock CLK11after the rising edge is not long enough.

FIG. 2Ais a block diagram illustrating a conventional system that uses delay buffer for modifying signal offsets.FIG. 2Bis a timing diagram of the signals ofFIG. 2A. The delay buffer240with a fixed delay time may be applied to delay the clock CLK11, so as to generate a clock CLK12for eliminating the signal offsets. However, the fixed delay buffer cannot flexibly modify the offsets of the digital signals along with a fabrication process variation and a voltage variation etc.

SUMMARY OF THE INVENTION

Accordingly, the present invention is directed to a phase-calibration circuit, which may detect a fabrication process variation and a working voltage variation, and flexibly select a required delay time, so as to calibrate a setup problem and a hold time problem occurred due to delay offsets of digital signals within a chip.

The present invention is directed to a display driver having a built-in-signal phase calibration circuit, by which a required delay time may be flexibly selected along with a fabrication process variation and a working voltage variation, so as to calibrate a delay offset of a receiver.

In accordance with the aforementioned objectives of the present invention, a phase-calibration circuit for calibrating a target circuit is provided. The phase-calibration circuit includes a pattern generator, a phase adjuster, a rotate register unit, a detector unit, and an optimization unit. The pattern generator generates a clock pattern and a data pattern for a target circuit. The phase adjuster receives a first clock and a first data from the target circuit and adjusts the phase relationship between the first clock and the first data according to a control data for outputting a second clock and a second data. The rotate register unit provides the control data to the phase adjuster and changes the control data according to a predetermined timing. The detector unit is coupled to the phase adjuster and detects a phase relationship between the second clock and the second data for outputting a detection result. The optimization unit is coupled to the detector unit and the rotate register unit and records the control data output from the rotate register unit in accordance with the detection result to select one of the control data as a calibration control data, and controls the rotate register unit to output the calibration control data to the phase adjuster.

The present invention provides a display driver including a receiver and a phase-calibration circuit. The receiver is used for receiving an external signal. The phase-calibration circuit is built within the display driver for calibrating the receiver. The phase-calibration circuit includes a pattern generator, a phase adjuster, a rotate register unit, a detector unit, and an optimization unit. The pattern generator generates a clock pattern and a data pattern for the receiver. The phase adjuster receives a first clock and a first data from the receiver and adjusts the phase relationship between the first clock and the first data according to a control data for outputting a second clock and a second data. The rotate register unit provides the control data to the phase adjuster and changes the control data according to a predetermined timing. The detector unit is coupled to the phase adjuster and detects a phase relationship between the second clock and the second data for outputting a detection result. The optimization unit is coupled to the detector unit and the rotate register unit and records the control data output from the rotate register unit in accordance with the detection result to select one of the control data as a calibration control data, and controls the rotate register unit to output the calibration control data to the phase adjuster.

The phase-calibration circuit of the present invention may detect an output of the target circuit via a detector unit and dynamically select a required delay time according to the detection result. Therefore, the setup problem and the hold time problem occurred due to delay offsets of digital signals may be dynamically calibrated according to the present invention.

DESCRIPTION OF EMBODIMENTS

FIG. 3is a block diagram illustrating an integrated circuit with a built-in-phase-calibration circuit according to an embodiment of the present invention. The integrated circuit with the built-in-phase-calibration circuit is exemplified by a display driver300. The display driver300includes an interface circuit310and a channel340for receiving a signal from a transmitter200to drive a panel (not shown).

The interface circuit310includes a receiver320and a phase-calibration circuit330. The receiver320utilizes, for example, a reduced swing differential signalling (RSDS) transmission interface or other transmission interfaces to receive signals from the transmitter200. If necessary, the receiver320may also convert the received signals into another signal format required by the interior of the display driver300. The phase-calibration circuit330includes a pattern generator331, a replicate receiver336, a replicate phase adjusters332, a phase adjusters337, a rotate register unit335, a detector unit333, and an optimization unit334. The phase-calibration circuit330receives a clock and a data from a target circuit (e.g. the receiver320) and adjusts a phase between the clock and the data, so as to output an adjusted clock and an adjusted data to a secondary circuit (e.g. the channel340).

The circuit design of the replicate receiver336may be identical to that of the receiver320, and the circuit designs of the replicate phase adjuster332may be identical to the phase adjuster337. Since the replicate receiver336and the receiver320are all disposed in the display driver300, the two receivers (320and336) are fabricated by the same fabrication process, and the features (including delay offset of the signals) of the two receivers are almost identical. In other words, the replicate receiver336and the replicate phase adjuster332may be regarded as respective replicas of the receiver320and the phase adjuster337.

In the calibration stage, the pattern generator331generates a clock pattern and a data pattern for the replicate receiver336, and the replicate receiver336outputs a first clock and a first data to the replicate phase adjuster332according to the clock pattern and the data pattern. Then the replicate phase adjuster332adjusts the phase relationship between the first clock and the first data according to the control data output from the rotate register unit335, so as to output a second clock and a second data. The rotate register unit335generates the control data according to a predetermined timing and provides the control data to the replicate phase adjusters332and the phase adjuster337. The detector unit333is coupled to the replicate phase adjuster332and detects a phase relationship between the second clock and the second data for outputting a detection result. The optimization unit334is coupled to the detector unit333and the rotate register unit335, and records the control data output from the rotate register unit335in accordance with the detection result output from the detector unit333to select one of the control data as a calibration control data, and controls the rotate register unit335to output the control data to the phase adjusters332and337. Operation of the phase-calibration circuit330will be described in detail below.

It should be noted that the integrated circuit with the built-in-phase-calibration circuit is not limited to the aforementioned embodiment. For example,FIG. 4is a block diagram illustrating an integrated circuit with a built-in-phase-calibration circuit according to another embodiment of the present invention. The integrated circuit is exemplified by a display driver400. The display driver400includes an interface circuit410and a channel440for receiving a signal from the transmitter200to drive a panel (not shown).

The interface circuit410includes a receiver420and a phase-calibration circuit430. The receiver420utilizes, for example, a reduced swing differential signalling (RSDS) transmission interface or other transmission interfaces to receive signals from the transmitter200. If necessary, the receiver420may also convert the received signals into another signal format required by the interior of the display driver400. The phase-calibration circuit430is built in the display driver400for calibrating the target circuit (e.g. the receiver420). The phase-calibration circuit430includes a pattern generator431, a phase adjuster432, a rotate register unit435, a detector unit433, and an optimization unit434. The phase-calibration circuit430receives a clock and a data from the receiver420and adjusts a phase relationship between the clock and the data, so as to output an adjusted clock and an adjusted data to a secondary circuit (e.g. the channel440) in the interior of the display driver400.

In the calibration stage, the selector436outputs a clock pattern and a data pattern from the pattern generator431to the receiver420. The receiver420outputs a first clock and a first data to the phase adjuster432according to the clock pattern and the data pattern. The phase adjuster432receives the first clock and the first data from the receiver420and adjusts the phase relationship between the first clock and the first data according to the control data output from the rotate register unit435, so as to output a second clock and a second data. The rotate register unit435changes the control data according to a predetermined timing and provides the control data to the phase adjuster432. The detector unit433is coupled to the phase adjuster432and detects a phase relationship between the second clock and the second data for outputting a detection result. The optimization unit434is coupled to the detector unit433and the rotate register unit435, and records the control data output from the rotate register unit435in accordance with the detection result output from the detector unit433to select one of the control data as a calibration control data, and controls the rotate register unit435to output the calibration control data to the phase adjusters432.

The operations of the phase-calibration circuits330and/or430are illustrated by the equivalent circuit ofFIG. 5. The phase-calibration circuit ofFIG. 5is used for calibrating a target circuit520. The target circuit520are equivalent to the replicate receiver336ofFIG. 3, and are equivalent to the receiver420ofFIG. 4.

Referring toFIG. 5, the phase-calibration circuit includes a pattern generator531, a phase adjuster532, a detector unit533, an optimization unit534, and a rotate register unit535, which are respectively equivalent to the pattern generator331, the replicate phase adjuster332, the detector unit333, the optimization unit334and the rotate register335ofFIG. 3, and are respectively equivalent to pattern generator431, the phase adjuster432, the detector unit433, the optimization unit434and the rotate register435ofFIG. 4.

FIG. 6is a signal timing diagram of the phase-calibration circuit shown inFIG. 5. Referring toFIG. 5andFIG. 6, the pattern generator531generates a clock pattern rs_clk and a data pattern rs_data for the target circuit520. Signal offset of the clock pattern rs_clk and/or the data pattern rs_data may be occurred after the clock pattern rs_clk and the data pattern rs_data pass through signal paths within the target circuit520.

The rotate register unit535provides a control data DC_con[n:1] to the phase adjuster532, and changes the control data DC_con[n:1] according to a predetermined timing. For example, assuming n=6 (i.e. the control data DC_con[n:1] has 6 bits), the rotate register unit535then sequentially outputs the control data DC_con[n:1] as 000001b, 000010b, 000100b, 001000b, 010000b, 100000b, 000001b, 000010b, and etc. Decimally, the control data DC_con[n:1] changes to 1, 2, 4, 8, 16, 32, 1, 2, . . . according to the predetermined timing.

The phase adjuster532receives the first clock test_clk and the first data test_data from the target circuit520, and adjusts a phase relationship between the first clock test_clk and the first data test_data according to the control data DC_con[n:1] to output a second clock clk_delay and a second data data_delay. In one embodiment, the phase of the first clock test_clk is not changed by the phase adjuster532(i.e. test_clk=clk_delay), and the phase of the first data test_data is adjusted by the phase adjuster532according to the control data DC_con[n:1], so as to output the second data data_delay. If the control data DC_con[n:1]=1, the second data data_delay output from the phase adjuster532then may be shown as a waveform data_delay(1) ofFIG. 6. If the control data DC_con[n:1]=2 (i.e. 000010b), the second data data_delay output from the phase adjuster532then may be shown as a waveform data_delay(2) ofFIG. 6. Deduced by analogy, if the control data DC_con[n:1]=32 (i.e. 100000b), the second data data_delay output from the phase adjuster532then may be shown as a waveform data_delay(32) ofFIG. 6.

The detector unit533is coupled to the phase adjuster532for receiving the second clock clk_delay and the second data data_delay, and detects the phase relationship between the second clock clk_delay and the second data data_delay for outputting a detection result detect_result. It is assumed that the detector unit533samples the second data data_delay according to a rising edge of the second clock clk_delay (which is identical to the phase of the first clock test_clk). Therefore, if the control data DC_con[n:1]=2, the second data data_delay (i.e. the waveform data_delay(2) ofFIG. 6) sampled by the detector unit533is “0”, and if the control data DC_con[n:1]=8, the second data data_delay (i.e. a waveform data_delay(8) ofFIG. 6) sampled by the detector unit533is “1”. According to the phase relationship between the clock pattern rs_clk and the data pattern rs_data generated by the pattern generator531, the second data data_delay sampled by the detector unit533should be “1”. Therefore, the detector unit533may judge whether an adjusting result of the phase adjuster532is correct according to the sampled second data data_delay, and may output the detection result detect_result according to the above judgement.

The optimization unit534is coupled to the detector unit533and the rotate register unit535for recording the control data Dc_con[n:1] output from the rotate register unit535according to the detection result detect_result to select one of the control data as a calibration control data, and controlling the rotate register unit535to output the calibration control data to the phase adjusters532. For example, the control data DC_con[n:1] output from the rotate register unit535constantly changes in a sequence of 1, 2, 4, 8, 16, 32, 1, 2 . . . . According to the detection result detect_result, the optimization unit534may judge that when the control data DC_con[n:1] is 4, 8, or 16, the adjusting results of the phase adjuster532are correct. Therefore, the optimization unit534may select one of the control data 4, 8, and 16 as the calibration control data (for example, a middle value “8” is selected), and may control the rotate register unit535according to a signal Optimal_Signal to output the calibration control data “8” (i.e. DC_con[n:1]=001000b) to the phase adjusters532. Therefore, the phase adjuster532may adjust the phase relationship between the first clock test_clk and the first data test_data output from the target circuit520according to the calibration control data “8” (control data DC_con[n:1]), so as to output the second clock clk_delay and the second data data_delay (referring to waveforms test_clk and data_delay(8) ofFIG. 6).

FIG. 7Ais an example of the pattern generator531ofFIG. 5according to an embodiment of the present invention. The pattern generator531may include an oscillator710, a pattern unit720and a differential interface unit730. The oscillator710provides a clock pattern o_clk for the pattern unit720. The pattern unit720provides a clock pattern p_clk and a data pattern p_data for the differential interface unit730according to the clock pattern o_clk. The differential interface unit730converts the clock patter p_clk and the data pattern p_data output from the pattern unit720into the clock pattern rs_clk and the data pattern rs_data. The pattern unit720may include a delayer721. In the present embodiment, the pattern unit720directly outputs the clock pattern o_clk as the clock pattern p_clk, and outputs the clock pattern o_clk via the delayer721as the data pattern p_data.

However, embodiment of the pattern unit720is not limited thereof. For example,FIG. 7Bis another example of the pattern generator531ofFIG. 5according to an embodiment of the present invention. In this embodiment, the pattern unit720may include a delayer722. The pattern unit720directly outputs the clock pattern o_clk as the data pattern p_data, and outputs the clock pattern o_clk via the delayer722as the clock pattern p_clk.

The differential interface unit730may convert the clock patter p_clk and the data pattern p_data output from the pattern unit720into signals in accordance with the RSDS transmission interface or other signal transmission interfaces. Certainly, the differential interface unit730may also be omitted, such that the pattern generator531may directly output the clock pattern p_clk and the data pattern p_data output from the pattern unit720as the clock pattern rs_clk and the data pattern rs_data.

FIG. 8is an example of the differential interface unit730ofFIG. 5according to an embodiment of the present invention. The differential interface unit730includes inverters810and820, and resistors811,812,813,814,815,816,821,822,823,824,825and826. An input terminal of the inverter810receives the clock pattern p_clk, and an input terminal of the inverter820receives the data pattern p_data. The resistors811-813are serially connected between the clock pattern p_clk and a ground voltage, wherein a common node between the resistor812and the resistor813is coupled to a reference voltage VDC, and a common node between the resistor811and the resistor812may output a signal rs_c. The resistors814-816are serially connected between an output terminal of the inverter810and the ground voltage, wherein a common node between the resistor815and the resistor816is coupled to the reference voltage VDC, and a common node between the resistor814and the resistor815may output a signal rs_cB. The signals rs_c and rs_cB are the output clock pattern rs_clk of the differential interface unit730. Moreover, the resistors821-823are serially connected between the data pattern p_data and the ground voltage, wherein a common node between the resistor822and the resistor823is coupled to the reference voltage VDC, and a common node between the resistor821and the resistor822may output a signal rs_d. The resistors824-826are serially connected between an output terminal of the inverter820and the ground voltage, wherein a common node between the resistor825and the resistor826is coupled to the reference voltage VDC, and a common node between the resistor824and the resistor825may output a signal rs_dB. The signals rs_d and rs_dB are the output data pattern rs_data of the differential interface unit730.

Here, the control data DC_con[n:1] is also assumed to be a 6-bits data (i.e. DC_con[6:1]).FIG. 9is an example of the phase adjuster532ofFIG. 5according to an embodiment of the present invention. The phase adjuster532includes a delay selector900for receiving the first data test_data output from the target circuit520, and delaying the first data test_data according to the control data DC_con[6:1] to output the second data data_delay. In the present embodiment, the phase adjuster532directly outputs the first clock test_clk output from the target circuit520as the second clock clk_delay, and adjusts the phase of the first data test_data output from the target circuit520via the delay selector900.

Referring toFIG. 9, the delay selector900includes a delayer unit string and switches921,922,923,924,925and926. The delayer unit string is formed by serially connecting the delayers911,912,913,914,915and916. Wherein, an input terminal of the first delayer911of the delayer unit string receives the first data test_data from the target circuit520. A first end of the switch921receives the first data test_data. The first ends of the switches922,923,924,925and926are respectively coupled to the output terminals of the delayers912-915. The second ends of the switches921-926are connected with each other for outputting the second data data_delay. One of the switches921-926is turned on under control of one of the bits (i.e. DC_con[1], DC_con[2], DC_con[3], DC_con[4], DC_con[5] or DC_con[6]) of the control data DC_con[6:1], so as to output the second data data_delay. Therefore, the phase relationship between the second data data_delay and the second clock clk_delay may be adjusted according to the control data DC_con[6:1].

Embodiment of the phase adjuster532is not limited to that shown inFIG. 9, and it will be apparent to those skilled in the art that other kinds of phase adjusters may also be applied. For example, the delay selector may be coupled between the first clock test_clk and the second clock clk_delay, such that the delay selector may delay the first clock test_clk output from the target circuit according to the control data DC_con[6:1], so as to obtain the second clock clk_delay. Moreover, the first data test_data may also be directly output as the second data data_delay.

FIG. 10is an example of the detector unit533ofFIG. 5according to an embodiment of the present invention. In the present embodiment, the detector unit533includes a flip-flop1010and a comparator1020. The flip-flop1010latches the second data data_delay according to the second clock clk_delay. The comparator1020detects whether or not the latched data of the flip-flop1010is correct, and outputs the detection result detect_result. According to the phase relationship between the clock pattern rs_clk and the data pattern rs_data generated by the aforementioned pattern generator531, the comparator1020may compare whether the second data data_delay latched by the flip-flop1010is “1”. Therefore, the detector unit533may judge whether or not the adjusting result of the phase adjuster532is correct according to the latched second data data_delay, and may output the detection result detect_result according to the above judgement.

The comparator1020may be embodied by an AND gate (not shown). Wherein, a first input terminal of the AND gate is coupled to an output terminal of the flip-flop1010, a second input terminal of the AND gate receives a logic value (logic “1”), and an output terminal of the AND gate outputs the detection result detect_result. Certainly, embodiment of the aforementioned comparator1020is not limited thereof.

Embodiments of the present invention are not limited by the aforementioned description. For example,FIG. 11is an example of another phase-calibration circuit according to an embodiment of the present invention. The embodiment ofFIG. 11is similar to that ofFIG. 5, the detailed description thereof will not be repeated. Compared to the embodiment ofFIG. 5, the detector unit1130ofFIG. 11may further output a pattern setup signal setup_result to the pattern generator1110according to the phase relationship between the second clock clk_delay and the second data data_delay, and the pattern generator1110may further adjust the phase of the data pattern rs_data according to the pattern setup signal setup_result. For example, when the pattern setup signal setup_result is logic “0”, the phase relationship between the clock pattern rs_clk and the data pattern rs_data generated by the pattern generator1110is in accordance with a system setup time, and when the pattern setup signal setup_result is logic “1”, the phase relationship between the clock pattern rs_clk and the data pattern rs_data generated by the pattern generator1110is in accordance with a system hold time.

Here, an initial value of the pattern setup signal setup_result is assumed to be logic “0”, which is referred to as a setup time testing mode. Since the pattern setup signal setup_result is logic “0”, the pattern generator1110generates the clock pattern rs_clk and the data pattern rs_data that are in accordance with the system setup time. The first clock test_clk and the first data test_data are generated after the clock pattern rs_clk and the data pattern rs_data pass through the target circuit520. The rotate register unit535circularly outputs the control data DC_con[n:1] to the phase adjuster532. The phase adjuster532then determines a delay time of the second clock clk_delay and the second data data_delay under control of the control data DC_con[n:1]. The detector unit1130detects the phase relationship between the second clock clk_delay and the second data data_delay to judge whether or not a correct data may be latched. As the control data DC_con[n:1] changes, when the detector unit1130latches the correct data, the detector unit1130then outputs the pattern setup signal setup_result with logic “1” to the pattern generator1110. Then, the phase-calibration circuit may perform a hold time testing.

When the pattern setup signal setup_result is logic “1”, a hold time testing mode is presented. Since the pattern setup signal setup_result is logic “1”, the pattern generator1110generates the clock pattern rs_clk and the data pattern rs_data that are in accordance with the system hold time. The rotate register unit535circularly outputs the control data DC_con[n:1] to the phase adjuster532. The phase adjuster532determines a delay time of the second clock clk_delay and the second data data_delay under control of the control data DC_con[n:1]. The detector unit1130detects the phase relationship between the second clock clk_delay and the second data data_delay to judge whether or not a correct data may be latched.

When the detector unit1130latches the correct data for a first time, the detection result detect_result output from the detector unit1130then changes from logic “0” to logic “1”, which may cause a counter within the optimization unit534to count once. Meanwhile, a register within the optimization unit534may record a value of the present control data DC_con[n:1]. Then, the value stored in the register of the optimization unit534will not change along with the detection result detect_result.

The rotate register unit535circularly changes the value of the control data DC_con[n:1]. When the control data DC_con[n:1] changes, the detection result output from the detector unit1130changes from logic “1” to logic “0”, and then whether or not the detection result detect_result is again changed from logic “0” to logic “1” is determined by whether or not the correct data is latched. Therefore, when the detection unit1130continuously detects that the phase relationship between the second clock clk_delay and the second data data_delay is enough for latching the correct data, as the control data DC_con[n:1] circularly changes, the detection result detect_result may be changed in a sequence as 0, 1, 0, 1 . . . accordingly. The counter within the optimization unit534may also count variations of the detection result detect_result, until the detection result detect_result maintains the logic “0”. Therefore, the value recorded by the counter of the optimization unit534is the number of the control data DC_con[n:1] being detected.

Since the rotate register unit535may circularly change the value of the control data DC_con[n:1], and therefore when the value of the control data DC_con[n:1] is cycled back to the value recorded within the register of the optimization unit534, and since the value recorded by the counter of the optimization unit534is the number of the control data DC_con[n:1] being detected, and thus when the control data DC_con[n:1] again changes a number of times equals to “the value recorded within the register of the optimization unit534/2”, the optimization unit534may control the rotate register535according to the signal Optimal_signal to maintain the control data DC_con[n:1] for no longer changing circularly.

For example, referring toFIG. 6, when the value of the control data DC_con[n:1] is 4, the detector unit1130latches the correct data for the first time, and accordingly the detection result detect_result output from the detector unit1130changes from logic “0” to logic “1”, such that the counter within the optimization unit534may count once. Meanwhile, the register within the optimization unit534may record the value of the present control data DC_con[n:1] as 4. Next, when the control data DC_con[n:1] is 8 and 16, the detection result detect_result is logic “1”, and when the control data DC_con[n:1] is 32, the detection result detect_result is logic “0”, it means when the control data DC_con[n:1]=4, 8 and 16, the phase adjuster532may respectively output a suitable phase relationship, and therefore the value recorded by the register within the optimization unit534is 3. The rotate register unit535may circularly change the value of the control data DC_con[n:1], and when the value of the control data DC_con[n:1] is again cycled back to 4 (identical to the value recorded within the register of the optimization unit534), the optimization unit534counts from the control data DC_con[n:1]=4. When the control data DC_con[n:1] again changes a number of times equals to “3/2” (i.e. counting value of the counter within the optimization unit534is shifted 1 bit rightward, and therefore 3/2=1), namely, when the value of the control data DC_con[n:1] is again changed to 8, the optimization unit534may control the rotate register535according to the signal Optimal_signal to maintain the control data DC_con[n:1] as 8 for no longer changing circularly.

FIG. 12is an example of the pattern generator1110ofFIG. 11according to an embodiment of the present invention. The pattern generator1110includes an oscillator1210, a first delayer1220, a second delayer1230and a switcher1240. The oscillator1210provides the clock pattern rs_clk. The first delayer1220and the second delayer1230respectively receive and delay the clock pattern rs_clk. The switcher1240selects one of the outputs of the first delayer1220and the second delayer1230as the output data pattern rs_data under control of the pattern setup signal setup_result.

Considering a specification of the system signals, a signal conversion circuit may also be allocated within the pattern generator1110. For example,FIG. 13is another example of the pattern generator1110ofFIG. 11according to an embodiment of the present invention. The pattern generator1110includes an oscillator1210, a first delayer1220, a second delayer1230, a switcher1240and a differential interface unit1310. The oscillator1210provides the original clock p_clk. The first delayer1220and the second delayer1230respectively receive and delay the original clock p_clk. The switcher1240selects one of the outputs of the first delayer1220and the second delayer1230as the output original data p_data under control of the pattern setup signal setup_result. The differential interface unit1310may convert the original clock p_clk and the original data p_data into the clock pattern rs_clk and the data pattern rs_data with a differential mode. The clock pattern rs_clk and the data pattern rs_data may be signals in accordance with the RSDS or other signal transmission interfaces. The circuit illustrated inFIG. 8may also be taken as an embodiment of the differential interface unit1310.

FIG. 14is an example of the detector unit1130ofFIG. 11according to an embodiment of the present invention. In this embodiment, the detector unit1130includes a flip-flop1410and a comparator1420. The flip-flop1410latches the second data data_delay according to the second clock clk_delay. The comparator1420detects whether or not the data latched by the flip-flop1410is correct, and outputs the detection result detect_result and the pattern setup signal setup_result. According to the phase relationship between the clock pattern rs_clk and the data patter rs_data generated by the pattern generator1110, the comparator1420may compare whether or not the second data data_delay latched by the flip-flop1410is “1”. Therefore, the detector unit1130may judge whether or not the adjusting result of the phase adjuster532is correct according to the latched second data data_delay, and may output the detection result detect_result and the pattern setup signal setup_result according to the above judgement.

The comparator1420includes an AND gate1421, an OR gate1422and a second flip-flop1423. A first input terminal of the AND gate1421is coupled to an output terminal of the flip-flop1410, a second input terminal of the AND gate1421receives a logic value (logic “1”), and an output terminal of the AND gate outputs the detection result detect_result. A first input terminal of the OR gate1422receives the second clock clk_delay. The trigger terminal of the second flip-flop1423is coupled to an output terminal of the OR gate1422, an input terminal of the second flip-flop1423is coupled to the output terminal of the AND gate1421, and an output terminal of the second flip-flop1423is coupled to a second input terminal of the OR gate1422. Wherein, the output terminal of the second flip-flop1423outputs the pattern setup signal setup_result to the pattern generator1110, such that the pattern generator1110may further adjust the phase of the data pattern rs_data and/or the clock pattern rs_clk according to the pattern setup signal setup_result.

In summary, according to the aforementioned embodiments, the phase-calibration circuit may detect the output of the target circuit via the detector unit, and may dynamically select the required delay time according to the detection result. Therefore, the setup time problem and the hold time problem occurred due to delay offset may be dynamically modified according to the embodiments of the present invention.