RUTHENIUM CARBIDE FOR DRAM CAPACITOR MOLD PATTERNING

Methods of forming electronic devices and film stacks comprising depositing a ruthenium carbide hard mask on a capacitor mold formed on a substrate. A hard mask oxide and patterned photoresist are formed, and the pattern of the patterned photoresist are transferred into the ruthenium carbide hard mask. Film stacks comprising the ruthenium carbide hard mask on the capacitor mold are also described.

TECHNICAL FIELD

Embodiments of the disclosure generally relate to the fabrication of integrated circuits. In particular, embodiments of the disclosures are related to film stacks and methods of forming film stacks for electronic devices using a ruthenium carbide hard mask.

BACKGROUND

Reliably producing submicron and smaller features is one of the key requirements of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, with the continued miniaturization of circuit technology, the dimensions of the size and pitch of circuit features, such as interconnects, have placed additional demands on processing capabilities. The various semiconductor components (e.g., interconnects, vias, capacitors, transistors) require precise placement of high aspect ratio features. Reliable formation of these components is critical to further increases in device and density.

Additionally, the electronic device industry and the semiconductor industry continue to strive for larger production yields while increasing the uniformity of layers deposited on substrates having increasingly larger surface areas. These same factors in combination with new materials also provide higher integration of circuits per unit area on the substrate.

During formation of many electronic devices, hard masks are used to protect portions of a substrate from being removed. Hard masks are commonly used in patterning operations. Once patterning has been completed, the hard mask is frequently removed, leaving the protected portion of the substrate. Removal of the hard mask material may occur separately from or in conjunction with other etch processes. The ability to remove the hard mask material without affecting other surface features (also referred to as etch selectivity) is a useful feature.

The development of hard mask materials having high etch selectivity is important for patterning new generation NAND and DRAM devices. For devices at each technology node, a 30% selectivity improvement of the capacitor mold hard mask over previous nodes is needed. Currently, boron-doped silicon is used in DRAM capacitor mold patterning for the N to N+2 nodes.

As the N+2 node has been proposed, the dopant concentration is boron dominant. Therefore, increasing the boron dopant concentration is not likely to continue to improve the hard mask selectivity sufficiently.

Therefore, there is an ongoing need in the art for capacitor mold hard mask with improved selectivity.

SUMMARY

One or more embodiments of the disclosure are directed to methods comprising depositing a ruthenium carbide hard mask on a capacitor mold formed on a substrate. A hard mask oxide is formed on the ruthenium carbide layer. A patterned photoresist is formed on the hard mask oxide. The pattern of the patterned photoresist is transferred to the ruthenium carbide hard mask to form a patterned ruthenium carbide hard mask.

Additional embodiments of the disclosure are directed to methods comprising forming a capacitor mold on a substrate. The capacitor mold comprises a silicon oxide (SiO) layer and a silicon carbon nitride (SiCN) layer or silicon nitride (SiN) layer on the silicon oxide layer. The silicon oxide (SiO) layer has a thickness in the range of 1 μm to 3 μm and the SiCN layer or SiN layer having a thickness up to 1000 Å. One or more of an amorphous silicon film or carbon film is optionally deposited directly on the capacitor mold. A ruthenium carbide hard mask is deposited on the capacitor mold and on the optional amorphous silicon film or carbon film, if present. The ruthenium carbide hard mask comprises in the range of 20 to 45 at. % ruthenium and in the range of 5 to 15 at. % hydrogen. The sum of thicknesses of the optional amorphous silicon film or carbon film and the ruthenium carbide hard mask in the range of 2500 to 3500 Å. A hard mask oxide is formed on the ruthenium carbide layer. An anti-reflective coating comprising one or more of a dielectric anti-reflective coating (DARC) or bottom anti-reflective coating (BARC) is formed on the hard mask oxide. A photoresist having a pattern is formed on the anti-reflective coating. The pattern of the photoresist is transferred to the anti-reflective coating, the hard mask oxide and the ruthenium carbide hard mask by exposing the substrate to an etchant plasma comprising an oxygen content, a chlorine content and a carbonyl sulfide content to form a patterned hard mask oxide, a patterned ruthenium carbide hard mask and remove the anti-reflective coating. The chlorine content is in the range of 5% to 15% of the oxygen content, on a molar basis, the carbonyl sulfide content is in the range of 5% to 10% of the oxygen content, on a molar basis. Remaining photoresist and anti-reflective coating is removed to leave a patterned hard mask oxide and patterned ruthenium carbide hard mask. The pattern of the patterned hard mask oxide and patterned ruthenium carbide hard mask is optionally transferred into the optional amorphous silicon film or carbon film.

Further embodiments of the disclosure are directed to film stacks comprising: a capacitor mold; a ruthenium carbide hard mask on the capacitor mold; a hard mask oxide on the ruthenium carbide hard mask; and a patterned photoresist on the hard mask oxide.

DETAILED DESCRIPTION

A “substrate” as used herein, refers to any substrate or material surface formed on a substrate upon which film processing is performed during a fabrication process. For example, a substrate surface on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon doped silicon oxides, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, without limitation, semiconductor wafers. Substrates may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, e-beam cure and/or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the film processing steps disclosed may also be performed on an underlayer formed on the substrate as disclosed in more detail below, and the term “substrate surface” is intended to include such underlayer as the context indicates.

The term “on” indicates that there is direct contact between elements. The term “directly on” indicates that there is direct contact between elements with no intervening elements.

Some embodiments of the disclosure advantageously provide new hard mask materials with improved selectivity relative to boron-doped silicon. In some embodiments, a ruthenium carbide film is used as a hard mask that is selective relative to adjacent hard mask oxides and/or capacitor mold components. Some embodiments provide ruthenium carbide hard masks that can be ashed or etched from the substrate surface.

FIG.1is a schematic representation of an exemplary substrate processing system132, which can be used for ruthenium carbide deposition, or other processes, according to embodiments described herein. Examples of suitable processing chambers and tools include, but are not limited to, the CENTURA® systems which may use a DxZ™ process chamber, PRECISION 5000® systems, PRODUCER™ systems, such as the PRODUCER SE™ process chamber and the PRODUCER GT™ process chamber, all of which are commercially available from Applied Materials, Inc., of Santa Clara, Calif. It is contemplated that the processes described herein may be performed on other substrate processing systems, including those from other manufacturers.

The substrate processing system132illustrated inFIG.1, includes a process chamber100coupled to a gas panel130and a controller110. The process chamber100generally includes a top124, a side101and a bottom wall122that define an interior processing volume126. A support pedestal150is provided in the interior processing volume126of the chamber100. The pedestal150is supported by a stem160or pedestal support and may be typically fabricated from aluminum, ceramic, and other suitable materials. The pedestal150may be moved in a vertical direction inside the chamber100using a displacement mechanism (not shown) or rotated around a central axis of the stem160using a suitable rotary mechanism (not shown).

The pedestal150illustrated includes an embedded heating element170suitable for controlling the temperature of a substrate190supported on a surface192of the pedestal150. The pedestal150may be resistively heated by applying an electric current from a power supply106to the heater element170. The heater element170may be made of a nickel-chromium wire encapsulated in a nickel-iron-chromium alloy (e.g., INCOLOY®) sheath tube. The electric current supplied from the power supply106is regulated by the controller110to control the heat generated by the heater element170, thereby maintaining the substrate190and the pedestal150at a substantially constant temperature during film deposition. The supplied electric current may be adjusted to selectively control the temperature of the pedestal150between about 100° C. to about 700° C.

A temperature sensor172, such as a thermocouple, may be embedded in the support pedestal150to monitor the temperature of the pedestal150in a conventional manner. The measured temperature is used by the controller110to control the power supplied to the heating element170to maintain the substrate at a desired temperature.

A vacuum pump102is coupled to a port formed in the bottom of the chamber100. The vacuum pump102is used to maintain a desired gas pressure in the process chamber100. The vacuum pump102also evacuates post-processing gases and by-products of the process from the chamber100.

The processing system132may further include additional equipment for controlling the chamber pressure, for example, valves (e.g. throttle valves and isolation valves) positioned between the process chamber100and the vacuum pump102to control the chamber pressure.

A showerhead120having a plurality of apertures128is disposed on the top of the process chamber100above the substrate support pedestal150. The apertures128of the showerhead120are utilized to introduce process gases into the chamber100. The apertures128may have different sizes, number, distributions, shape, design, and diameters to facilitate the flow of the various process gases for different process requirements. The showerhead120is connected to the gas panel130that allows various gases to supply to the interior processing volume126during process. A plasma is formed from the process gas mixture exiting the showerhead120to enhance thermal decomposition of the process gases resulting in the deposition of material on a surface191of the substrate190.

The gas panel130may also be used to control and supply various vaporized liquid precursors. While not shown, liquid precursors from a liquid precursor supply may be vaporized, for example, by a liquid injection vaporizer, and delivered to the process chamber100in the presence of a carrier gas. The carrier gas is typically an inert gas, such as nitrogen, or a noble gas, such as argon or helium. Alternatively, the liquid precursor may be vaporized from an ampoule by a thermal and/or vacuum enhanced vaporization process.

The showerhead120and substrate support pedestal150may form a pair of spaced apart electrodes in the interior processing volume126. One or more RF power sources140provide a bias potential through a matching network138to the showerhead120to facilitate generation of plasma between the showerhead120and the pedestal150. Alternatively, the RF power sources140and matching network138may be coupled to the showerhead120, substrate pedestal150, or coupled to both the showerhead120and the substrate pedestal150, or coupled to an antenna (not shown) disposed exterior to the chamber100. In one embodiment, the RF power sources140may provide between about 50 Watts and about 10,000 Watts at a frequency of about 50 kHz to about 100 MHz. In another embodiment, the RF power sources140may provide between about 500 Watts and about 1,800 Watts at a frequency of about 50 kHz to about 13.6 MHz.

The controller110includes a central processing unit (CPU)112, a memory116, and a support circuit114utilized to control the process sequence and regulate the gas flows from the gas panel130. The CPU112may be of any form of a general purpose computer processor that may be used in an industrial setting. The software routines can be stored in the memory116, such as random access memory, read only memory, floppy, or hard disk drive, or other form of digital storage. The support circuit114is conventionally coupled to the CPU112and may include cache, clock circuits, input/output systems, power supplies, and the like. Bi-directional communications between the controller110and the various components of the processing system132are handled through numerous signal cables collectively referred to as signal buses118, such as illustrated inFIG.1.

Referring toFIGS.2A-2D, an exemplary process for forming an electronic device is illustrated using a schematic cross-sectional representation of the electronic device. Shading illustrated in the Figures is used to show the different components and should not be taken as representing any particular material of construction unless specified.

FIG.2Aillustrates an electronic device200with a capacitor mold210formed on a substrate205. The capacitor mold210of some embodiments comprises one or more of silicon oxide (SiO), silicon carbide (SiC), or silicon carbon nitride (SiCN). As used in this specification and the appended claims, unless otherwise specified, chemical formulae are merely representative of the elemental identities of the film and are not intended to be stoichiometric. For example, a SiO film comprises silicon and oxygen atoms. The typical silicon oxide film comprises primarily silicon dioxide (SiO2), which implies a particular stoichiometric relationship. In some embodiments, the elemental formula of a layer means that the layer is greater than or equal to about 95%, 98%, 99% or 99.5% of the stated elements, on an atomic basis. The skilled artisan will recognize that interlayer diffusion of atoms may unintentionally occur, affecting the overall composition of the stated layer. Thus, for example, in a silicon oxide (SiO) layer, the sum of silicon atoms and oxygen atoms make up greater than or equal to 95%, 98%, 99% or 99.5% of the total atoms in that layer, allowing for a small amount of contamination and interlayer diffusion atoms. Stated differently, the layer “consists essentially of” the stated elements, where consisting essentially of means that the stated elements make up greater than or equal to 95%, 98%, 99% or 99.5%, on an atomic basis. The term “consists essentially of” can be applied to any of the individual layer described herein and is not limited to the example of silicon oxide.

The capacitor mold210of some embodiments comprises a silicon oxide (SiO) layer212and a second layer214comprising one or more of a silicon carbon nitride (SiCN) layer or a silicon nitride (SiN) layer. The silicon oxide layer212of some embodiments has a thickness in the range of 0.5 μm to 5 μm, or in the range of 1 μm to 3 μm. In some embodiments, the silicon oxide layer212has a thickness up to 3.5 μm.

The second layer214of some embodiments comprises a silicon carbon nitride (SiCN) layer. In some embodiments, the second layer214comprises a silicon nitride (SiN) layer. The second layer214, or SiCN layer or SiN layer has a thickness up to 10,000 Å, or 5,000 Å or 1,000 Å. In some embodiments, the second layer214has a thickness in the range of 100 Å to 1000 Å, or in the range of 500 Å to 900 Å.

The silicon oxide layer212and second layer214can be formed by any suitable technique known to the skilled artisan. For example, the layers can be formed by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), physical vapor deposition (PVD).

The substrate205and/or capacitor mold210of some embodiments has a substantially planar surface. Alternatively, the substrate205and/or capacitor mold210of some embodiments has patterned structures, a surface having trenches, holes, or vias formed therein. While the substrate205is illustrated as a single body, the skilled artisan will understand that the substrate may contain one or more material layers used in forming semiconductor devices such as metal contacts, trench isolations, gates, bit-lines, or any other interconnect features. The substrate205may comprise one or more metal layers, one or more dielectric materials, semiconductor material, and combinations thereof utilized to fabricate semiconductor devices. For example, the substrate205may include an oxide material, a nitride material, a polysilicon material, or the like, depending upon application. In one embodiment where a memory application is desired, the substrate205may include the silicon substrate material, an oxide material, and a nitride material, with or without polysilicon sandwiched in between.

In some embodiments, the substrate205includes a plurality of alternating oxide and nitride materials (i.e., oxide-nitride-oxide (ONO)) deposited on a surface of the substrate (not shown). In various embodiments, the substrate205may include a plurality of alternating oxide and nitride materials, one or more oxide or nitride materials, polysilicon or amorphous silicon materials, oxides alternating with amorphous silicon, oxides alternating with polysilicon, undoped silicon alternating with doped silicon, undoped polysilicon alternating with doped polysilicon, or updoped amorphous silicon alternating with doped amorphous silicon. The substrate205may be any substrate or material surface upon which film processing is performed. For example, the substrate205may be a material such as crystalline silicon, silicon oxide, silicon oxynitride, silicon nitride, strained silicon, silicon germanium, tungsten, titanium nitride, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or non-patterned wafers, silicon on insulator (SOI), carbon doped silicon oxides, silicon nitrides, doped silicon, germanium, gallium arsenide, glass, sapphire, low k dielectrics, and combinations thereof.

FIG.2Billustrates the electronic device220after formation of an optional hard mask underlayer222on the capacitor mold210. The hard mask underlayer222of some embodiments comprises one or more of an amorphous silicon (a-Si) film or a carbon (C) film. In some embodiments, the hard mask underlayer222comprises an amorphous silicon film. In some embodiments, the hard mask underlayer222comprises a carbon film. The hard mask underlayer222of some embodiments is formed directly on the capacitor mold210without an intervening layer.

An optional seed layer224is illustrated as being formed on the hard mask underlayer222. In some embodiments, the optional seed layer224is formed directly on the hard mask underlayer222. In some embodiments, the optional seed layer224is formed directly on the capacitor mold210and the hard mask underlayer222is omitted. In one or more embodiments, the optional seed layer224comprises boron. In some embodiments, the optional seed layer224has a thickness up to 100 Å, or in the range of 10 Å to 100 Å, or in the range of 20 Å to 60 Å.

A ruthenium carbide hard mask226is formed on the capacitor mold210. In the illustrated embodiment, the ruthenium carbide hard mask226is formed directly on the optional seed layer224on the hard mask underlayer222. In some embodiments, the optional hard mask underlayer222and optional seed layer224are omitted and the ruthenium carbide hard mask226is formed directly on the capacitor mold210. In some embodiments, the hard mask underlayer222is omitted and the ruthenium carbide hard mask226is formed directly on the optional seed layer224which is formed on capacitor mold210.

The ruthenium carbide hard mask226can be an amorphous, semi-crystalline or crystalline material. The hard mask may also be referred to as a ruthenium doped carbon film. However, the skilled artisan will recognize the term ruthenium doped carbon film is interchangeable with ruthenium carbide film and may depend on the level of crystallinity of the material.

The ruthenium carbide hard mask226of some embodiments has a ruthenium composition in the range of 20 to 45 atomic percent ruthenium. In some embodiments, the composition of the ruthenium carbide hard mask226comprises in the range of greater than 0 to 50 at. % ruthenium, 5 to 50 at. % ruthenium, 10 to 45 at. % ruthenium, 20 to 45 at. % ruthenium, or in the range of 25 to 40 at. % ruthenium, or in the range of 30 to 35 at. % ruthenium.

The ruthenium carbide hard mask226of some embodiments has a hydrogen composition in the range of 2 to 20 atomic percent hydrogen. In some embodiments, the composition of the ruthenium carbide hard mask226comprises in the range of 5 to 15 at. % hydrogen, or in the range of 8 to 12 at. % hydrogen. In some embodiments, the composition of the ruthenium carbide hard mask226comprises less than or equal to 15 at. % hydrogen, less than or equal to 10 at. % hydrogen, or less than or equal to 5 at. % hydrogen.

In some embodiments, the ruthenium carbide hard mask226comprises in the range greater than 0 to 50 atomic percent ruthenium and less than or equal to 15 atomic percent hydrogen with the remainder being carbon. In some embodiments, the ruthenium carbide hard mask226comprises in the range 10 to 45 atomic percent ruthenium and less than or equal to 10 atomic percent hydrogen with the remainder being carbon. In some embodiments, the ruthenium carbide hard mask226comprises in the range 20 to 45 atomic percent ruthenium and 5 to 15 atomic percent hydrogen with the remainder being carbon. In some embodiments, the ruthenium carbide hard mask226comprises in the range of 20 to 45 atomic percent ruthenium and less than or equal to 15, 10 or 5 atomic percent hydrogen with the remainder being carbon.

The ruthenium carbide hard mask226of some embodiments has a thickness in the range of 500 Å to 4000 Å, or in the range of 1000 Å to 4000 Å, or in the range of 1500 Å to 3500 Å. In some embodiments, the thickness of the ruthenium carbide hard mask is in the range of 2500 Å to 3500 Å. In some embodiments, the optional hard mask underlayer222has a thickness in the range of 100 Å to 500 Å and the ruthenium carbide hard mask226has a thickness in the range of 2500 Å to 3400 Å. In some embodiments, the combination of the optional hard mask underlayer222and the ruthenium carbide hard mask226have a thickness in the range of 2500 Å to 3500 Å. In some embodiments, the thickness of the combination of the optional hard mask underlayer222, the optional seed layer224and the ruthenium carbide hard mask226is in the range of 500 Å to 4000 Å.

In the illustrated embodiment, a hard mask oxide228is formed on the ruthenium carbide hard mask226. The hard mask oxide228can be any suitable material known to the skilled artisan that is etch selective relative to the ruthenium carbide hard mask226. The hard mask oxide228of some embodiments has a thickness in the range of 500 Å to 1500 Å.

In the illustrated embodiments, an advanced patterning film (APF)230is formed on the hard mask oxide228. The advanced patterning film230of some embodiments comprises a carbon or diamond-like carbon film. In some embodiments, the advanced patterning film230has a thickness in the range of 500 Å to 1500 Å. In some embodiments, the advanced patterning film230has a thickness greater than 0 Å and less than or equal to 1500 Å, or 1000 Å.

A dielectric anti-reflective coating (DARC)232is formed on the advanced patterning film230. The DARC232can be formed by any suitable technique known to the skilled artisan. The dielectric anti-reflective coating232of some embodiments comprises silicon oxynitride (SiON). In some embodiments, the DARC232has a thickness in the range of 250 Å to 500 Å. In some embodiments, the DARC232has thickness of greater than 0 Å and less than or equal to 500 Å.

A bottom anti-reflective coating (BARC)234is formed on the DARC232. The BARC234can be formed by any suitable technique known to the skilled artisan. In some embodiments, the BARC234has a thickness in the range of 100 Å to 500 Å. In some embodiments, the BARC234has a thickness greater than 0 Å and less than or equal to 500 Å.

A photoresist236is formed on the BARC234. The photoresist236can be deposited by any suitable technique known to the skilled artisan. The photoresist236is patterned by any suitable technique (e.g., lithography) to form a patterned photoresist and expose a top surface235of the BARC234. In some embodiments, the photoresist236is an energy sensitive resist material that can be patterned by exposing the energy sensitive resist material to UV radiation through a patterning device, such as a mask (not shown), and subsequently developing the energy sensitive resist material in an appropriate developer. After the energy sensitive resist material has been developed, a defined pattern of through openings237is present in the photoresist236.

FIG.2Cillustrates the electronic device220after the pattern of the photoresist236has been transferred to the anti-reflective coatings232,234, the advanced patterning film230, the hard mask oxide228and the ruthenium carbide hard mask226. Transferring the pattern of the photoresist236in some embodiments removes the photoresist236, the BARC234, the DARC232, and the advanced patterning film230, leaving a patterned hard mask oxide248and patterned ruthenium carbide hard mask246. In the illustrated embodiments, the pattern transfer also forms a patterned hard mask underlayer242and patterned seed layer244. In some embodiments, the optional hard mask underlayer222and optional seed layer224are present and are not patterned with the ruthenium carbide hard mask226.

Pattern transfer in some embodiments occurs by exposing the substrate to an etchant plasma using the photoresist236as a mask. The etchant plasma of some embodiments comprises an oxygen (O2) content and a chlorine (Cl2) content. The chlorine content of the etchant plasma of some embodiments is in the range of 5% to 15% of the oxygen content, on a molar basis. In some embodiments, the chlorine content of the etchant plasma is less than or equal to 15%, 10% or 5% of the oxygen content, on a molar basis.

In some embodiments, the etchant plasma comprises a carbonyl sulfide (COS) content. The COS content of some embodiments is in the range of 1% to 10% of the oxygen content, on a molar basis.

In some embodiments, the etchant plasma comprises oxygen, chlorine and carbonyl sulfide. The composition of the etchant plasma of some embodiments is 1-10% COS, 5-15% Cl2based on the amount of 02 on a molar basis.

In some embodiments, the photoresist236, anti-reflective coatings232,234and advanced patterning film230are removed at the same time as the pattern transfer. In some embodiments, one or more of the photoresist236, anti-reflective coatings232,234or advanced patterning film230remain after pattern transfer and are removed in a separate process.

FIG.2Dillustrates an embodiment of the electronic device240after transferring the pattern into the capacitor mold210to form electronic device260with patterned capacitor mold262. The patterned capacitor mold262in the illustrated embodiment comprises patterned silicon oxide layer264and patterned second layer266.

FIG.2Dshows the electronic device240after removing the patterned hard mask oxide248, patterned ruthenium carbide hard mask246, patterned optional seed layer244and patterned optional hard mask underlayer242. The patterned hard mask oxide248, patterned ruthenium carbide hard mask246, patterned optional seed layer244and patterned optional hard mask underlayer242can be removed at the same time as the pattern transfer into the capacitor mold210or in one or more separate processes. In some embodiments, a plasma comprising an oxygen content and a chlorine content is used to remove the patterned ruthenium carbide hard mask246, the patterned optional seed layer244and the patterned optional hard mask underlayer242.