Comparator and relaxation oscillator employing same

A relaxation oscillator has a comparator that includes first through third bias current transistors coupled to a first supply rail. First and second input transistors form a pair of parallel coupled transistors connected to the first bias current transistor. A first current mirror control transistor connects the first input transistor to a second supply rail. A first current mirror output transistor is coupled to the first current mirror control transistor, and connects the second bias current transistor to the second supply rail. A second current mirror control transistor connects the second input transistor to the second supply rail. A second current mirror output transistor is coupled to the second current mirror control transistor, and connects the third bias current transistor to the second supply rail. A transition time reduction transistor, coupled across the third bias current transistor, is coupled to the second bias current transistor, and provides a comparator output.

BACKGROUND OF THE INVENTION

The present invention relates to generation of clock signals for integrated circuits and, more particularly, to comparators and relaxation oscillators that use comparators.

Relaxation oscillator circuits are found in many electronic circuit applications and are often used for generating clock signals that control the timing of such electronic circuits. For example, relaxation oscillator circuits can be used DC/DC converters, counters, shifting modules, microcontrollers and modulation circuitry. Typically, the period of the clock signal provided by a relaxation oscillator circuit is determined primarily by charging and discharging of two capacitors. Such charging and discharging is often controlled by current sources or current mirrors supplying charge currents to the capacitors and the discharging is effected by controlling transistors coupled across the capacitors.

The charging and discharging of the capacitors typically provides ramp or saw-tooth waveform inputs to complementary comparators and the outputs of these comparators provides pulses that form an output waveform of the oscillator circuit. However, comparators have inherent low to high and high to low transition delays that can affect the upper limits and accuracy of the frequency of the oscillator circuit. Furthermore, such inherent transition delays are undesirable for comparator circuits that require a rapid response time.

Comparators are often designed to have rapid response times in order to reduce either or both of the low to high and high to low transition delays. However, such rapid response times are obtained at the expense of relatively large and undesirable quiescent currents that flow through either or both pull up and pull down transistors. It would therefore be beneficial to both relaxation oscillator circuits and comparators in general if the rapid response times are obtained without the use of relatively large quiescent currents.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The detailed description set forth below in connection with the appended drawings is intended as a description of presently preferred embodiments of the invention, and is not intended to represent the only forms in which the present invention may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the invention. In the drawings, like numerals are used to indicate like elements throughout. Furthermore, the terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that module, circuit, device components, method steps and structures that comprises a list of elements may include other elements not expressly listed or inherent to such module, circuit, steps or device components. Similarly, an element or step proceeded by “comprises” does not, without more constraints, preclude the existence of additional identical elements or steps that comprises the element or step. In this specification the terms gate, source and drain may be interchanged respectively with the terms base, emitter and collector. Furthermore, the terms coupled and connecting can refer to both direct and indirect connections between elements.

In one embodiment, the present invention provides a comparator comprising first, second and third bias current transistors each having a first node coupled to a first power supply rail and each of the transistors having a gate coupled to a regulating input. A first input transistor and a second input transistor form a pair of parallel coupled transistors having common nodes coupled to a second node of the first bias current transistor. The first input transistor has a gate providing a comparator first input port and the second input transistor has a gate providing a comparator second input port. A first current mirror control transistor couples the first input transistor to a second power supply rail and a first current mirror output transistor has a gate coupled to a gate of the first current mirror control transistor. The first current mirror output transistor couples a second node of the second bias current transistor to the second power supply rail.

A second current mirror control transistor couples the second input transistor to the second power supply rail and a second current mirror output transistor has a gate coupled to a gate of the second current mirror control transistor. The second current mirror output transistor couples a second node of the third bias current transistor to the second power supply rail. A transition time reduction transistor is coupled across the third bias current transistor such that a first node of the transition time reduction transistor is coupled to the first power supply rail and a second node of the transition time reduction transistor is coupled to the second node of the third bias current transistor. A gate of the transition time reduction transistor is coupled to the second node of the second bias current transistor, and the second node of the transition time reduction transistor provides an output port for the comparator.

In another embodiment the present invention provides a relaxation oscillator comprising a set discharge transistor coupled across a set capacitor and a reset discharge transistor coupled across a reset capacitor. A set reset latch has a set output coupled to a gate of the set discharge transistor and a reset output of the latch is coupled to a gate of the reset discharge transistor. A set comparator with a set comparator output port is coupled to a set input of the set reset latch, a set comparator first input port coupled to a reference voltage node, a set comparator second input port coupled to an electrode of the set capacitor. A reset comparator with a reset comparator output port is coupled to a reset input of the set reset latch, a reset comparator first input port coupled to a reference voltage node and a reset comparator second input port coupled to an electrode of the reset capacitor. The set comparator includes first, second and third bias current transistors each having a first node coupled to a first power supply rail and each of the transistors having a gate coupled to a regulating input.

A first input transistor and a second input transistor form a pair of parallel coupled transistors having common nodes coupled to a second node of the first bias current transistor. The first input transistor has a gate providing the set comparator first input port and the second input transistor has a gate providing the set comparator second input port. A first current mirror control transistor couples the first input transistor to a second power supply rail and a first current mirror output transistor has a gate coupled to a gate of the first current mirror control transistor. The first current mirror output transistor couples a second node of the second bias current transistor to the second power supply rail.

A second current mirror control transistor couples the second input transistor to the second power supply rail and a second current mirror output transistor has a gate coupled to a gate of the second current mirror control transistor. The second current mirror output transistor couples a second node of the third bias current transistor to the second power supply rail. A transition time reduction transistor is coupled across the third bias current transistor such that a first node of the transition time reduction transistor is coupled to the first power supply rail and a second node of the transition time reduction transistor is coupled to the second node of the third bias current transistor. A gate of the transition time reduction transistor is coupled to the second node of the second bias current transistor, and the second node of the transition time reduction transistor provides the set comparator output port.

In a further embodiment the present invention provides a relaxation oscillator comprising a transistor coupled across a capacitor. First, second and third bias current transistors are provided, each having a first node coupled to a first power supply rail and a gate coupled to a regulating input. A first input transistor and a second input transistor form a pair of parallel coupled transistors having common nodes coupled to a second node of the first bias current transistor. The first input transistor has a gate providing a comparator first input port coupled to a reference voltage node and the second input transistor has a gate providing a comparator second input port coupled to the capacitor. A first current mirror control transistor couples the first input transistor to a second power supply rail and a first current mirror output transistor has a gate coupled to a gate of the first current mirror control transistor. The first current mirror output transistor couples a second node of the second bias current transistor to the second power supply rail.

A second current mirror control transistor couples the second input transistor to the second power supply rail and a second current mirror output transistor has a gate coupled to a gate of the second current mirror control transistor. The second current mirror output transistor couples a second node of the third bias current transistor to the second power supply rail. A transition time reduction transistor is coupled across the third bias current transistor such that a first node of the transition time reduction transistor is coupled to the first power supply rail and a second node of the transition time reduction transistor is coupled to the second node of the third bias current transistor. A gate of the transition time reduction transistor is coupled to the second node of the second bias current transistor, and the second node of the transition time reduction transistor provides an output port for the comparator.

Referring toFIG. 1, a circuit diagram of a conventional relaxation oscillator100is shown. The relaxation oscillator100includes a constant current source101coupled between a supply voltage node VDD on one side and a drain and a gate electrode of a first bias transistor102on the other side. The gate electrode of the first bias transistor102is coupled to a gate electrode of a first mirror transistor103and the source electrodes of both transistors102,103are coupled to a return voltage node (ground or GND).

A second bias transistor104with a source electrode coupled to the supply voltage node VDD and a gate electrode of the second bias transistor104is coupled to its own drain electrode, and to both a drain electrode of the first mirror transistor103and to a gate electrode of a second mirror transistor105. A source electrode of the second mirror transistor105is coupled to the supply voltage node VDD and a drain electrode of the second mirror transistor105is coupled to a first electrode of a set capacitor106. A second electrode of the set capacitor106is coupled to ground GND and the first electrode of the set capacitor106is further coupled to both a drain electrode of a set discharge transistor107and a positive input of a set comparator108.

The relaxation oscillator100further includes a Set-Reset latch109with a set input S coupled to an output of the set comparator108. There is also a third mirror transistor110that has a source electrode coupled to the supply voltage node VDD, a gate electrode coupled to the gate electrode of the second bias transistor104, and a drain electrode that is coupled to a first electrode of a reset capacitor111. A second electrode of the reset capacitor111is coupled to ground GND and the first electrode of the reset capacitor111is also coupled to both a drain electrode of a reset discharge transistor112and a positive input of a reset comparator113. An output of the reset comparator113is coupled to a reset input R of the Set-Reset latch109and negative inputs of both comparators108,113are coupled to a common threshold voltage reference node VREF.

An output QBAR of the Set-Reset latch109is coupled to a gate electrode of the reset discharge transistor112and output Q of the Set-Reset latch109is coupled to a gate electrode of the set discharge transistor107. The set discharge transistor107and reset discharge transistor112have source electrodes coupled to ground GND and as shown an oscillator output node114is coupled to the output Q of the Set-Reset latch109. However, if desired, the oscillator output node114can be coupled to output QBAR of the Set-Reset latch109. As will be apparent to a person skilled in the art, an output signal SOUT is provided to the oscillator output node114and the frequency of this output signal SOUT is dependent on charging rates of the set and reset capacitors106,111. However, the accuracy and available maximum frequency of the output signal SOUT are dependent on the reaction times of the low to high and high to low transitions of the comparators108,113.

Referring toFIG. 2, a waveform diagram illustrating waveforms generated by the conventional relaxation oscillator100are shown. As illustrated, a substantially saw-tooth waveform S1is generated at the positive input of the set comparator108. This saw-tooth waveform S1has a rising ramp portion caused by a charging of the set capacitor106and a falling portion caused by a discharging of the set capacitor106. Ideally, once the saw-tooth waveform S1reaches a potential equal to a threshold reference voltage VTH supplied from the reference node VREF, an output pulse P1at the output of the set comparator108transitions from low to high. However, there is an inherent low to high transition delay DLH caused by the response times of the internal circuitry of the set comparator108. As a result, the output pulse P1does not immediately transition from low to high once the saw-tooth waveform S1reaches a potential equal to a threshold reference voltage VTH. Also, the saw-tooth waveform S1does not immediately fall to zero volts after the pulse P1transition from low to high due to inherent delays in the Set-Reset latch109and a response time of the set discharge transistor107.

When the saw-tooth waveform S1falls below the threshold reference voltage VTH, there is an inherent high to low transition delay DHL caused by the response times of the internal circuitry of the set comparator108. This high to low transition delay DHL increases the transitioning time of pulse P1from high to low.

A substantially saw-tooth waveform S2also is generated at the positive input of the reset comparator113. This saw-tooth waveform S2is caused by a charging and discharging of the reset capacitor111. Ideally, once the saw-tooth waveform S2reaches a potential equal to a threshold reference voltage VTH supplied from the reference node VREF, an output pulse P2at the output of the reset comparator113transitions from low to high. However, again there is an inherent low to high transition delay DLH caused by the response times of the internal circuitry of the reset comparator113. As a result, the output pulse P2does not immediately transition from low to high once the saw-tooth waveform S2reaches a potential equal to a threshold reference voltage VTH. Also, the saw-tooth waveform S2does not immediately fall to zero volts after the pulse P2transition from low to high due to inherent delays in the Set-Reset latch109and a response time of the reset discharge transistor112.

In a similar fashion to the above, when the saw-tooth waveform S2falls below the threshold reference voltage VTH, there is an inherent high to low transition delay DHL caused by the response times of the internal circuitry of the reset comparator113. This high to low transition delay DHL increases the transitioning time of pulse P2from high to low.

The pulses P1and P2control the outputs Q and QBAR of the Set-Reset latch109, which results in respective output signals SOUT and SOUT1, wherein SOUT1is anti-phase to SOUT. As will be apparent to a person skilled in the art, the accuracy of the frequency Fout of output signals SOUT and SOUT1is dependent on the low to high transition delay DLH of each comparator108,113. Thus, if the low to high transition delay DLH of each comparator108,113varies then the accuracy of the frequency Fout of output signals SOUT and SOUT1will also vary. It would therefore be beneficial to reduce the low to high transition delay DLH of each comparator108,113so that variations in this delay will be reduced. Similarly, the high to low transition delay DHL for each comparator108,113affects the available maximum frequency Fout of output signals SOUT and SOUT1and therefore it would again be beneficial to reduce this delay.

Referring toFIG. 3, a circuit diagram of a comparator300in accordance with a first preferred embodiment of the present invention is illustrated. The comparator300includes a first bias current transistor301, second bias current transistor302and a third bias current transistor303. Each of the bias current transistors301,302,303has a first node coupled to a first power supply rail VDD and each of the bias current transistors301,302,303has a gate coupled to a common regulating input VB. The first, second and third bias current transistors301,302,303are identical and therefore have the same conductivity properties across their channels. In operation they each provide a bias current IB that has identical maximum current flow limits in each of the first, second and third bias current transistors301,302,303.

There is a first input transistor304and a second input transistor305forming a pair of parallel coupled transistors306having common nodes coupled to a second node of the first bias current transistor301. The first input transistor304has a gate providing a comparator first input port VREF and the second input transistor305has a gate providing a comparator second input port VIN. The first input transistor304and second input transistor305are identical and when equal potentials are applied to the comparator first input port VREF and comparator second input port VIN, equal currents of IB/2 flow through both the first input transistor304and the second input transistor305.

There is a first current mirror control transistor307coupling the first input transistor304to a second power supply rail GND. There is also a first current mirror output transistor308with a gate coupled to a gate of the first current mirror control transistor307. The first current mirror output transistor308couples a second node of the second bias current transistor302to the second power supply rail GND and the first current mirror output transistor308is larger than the first current mirror control transistor307. More specifically, the first current mirror output transistor308has a width to length ratio (W/L) of at least twice that of the width to length ration (W/L) of the first current mirror control transistor307.

A second current mirror control transistor309couples the second input transistor305to the second power supply rail GND. There is also a second current mirror output transistor310with a gate coupled to a gate of the second current mirror control transistor309. The second current mirror output transistor310couples a second node of the third bias current transistor303to the second power supply rail GND and the second current mirror output transistor310is larger than the second current mirror control transistor309. Again, more specifically, the second current mirror output transistor310has a width to length ratio (W/L) of at least twice that of a width to length ratio (W/L) of the second current mirror control transistor309.

The comparator300also includes a transition time reduction transistor311coupled across the third bias current transistor303. A first node of the transition time reduction transistor311is coupled to the first power supply rail VDD and a second node of the transition time reduction transistor is coupled to the second node of the third bias current transistor303. A gate of the transition time reduction transistor311is coupled to the second node of the second bias current transistor302, and the second node of the transition time reduction transistor311provides an output port VOUT for the comparator300. There is also another output port VOUT1which is coupled to the output port VOUT through an inverter314and simply provides an inverted output of a signal or voltage level at output port VOUT.

There is a first isolating transistor312inserted between the first current mirror output transistor308and the second bias current transistor302. There is also a second isolating transistor313inserted between the second current mirror output transistor310and the third bias current transistor303. Gates of the both the first isolating transistor312and second isolating transistor313are coupled to a bias voltage which in this embodiment is a common isolating transistor bias voltage VCAS. As will be apparent to a person skilled in the art, the first isolating transistor312and second isolating transistor313reduce the capacitance loading effects of the first current mirror output transistor308and second current mirror output transistor310respectively. Hence, the inclusion of the first isolating transistor312and second isolating transistor313provides for a reduction in response time at the output port VOUT.

In this embodiment transistors301,302,303,304,305and311are P Channel Field Effect Transistors (FET) and transistors307,308,309,310,312and313are N Channel FETs. Also, in operation VDD would typically be set to approximately 3.3 volts, VB would be set to about 2.3 volts and VCAS would be set to about 1.1 Volts. Furthermore, VREF can be set to a low voltage of about 0.4 volts for high frequency and low power applications.

If a saw-tooth waveform S1is supplied to the comparator second input port VIN, whilst the comparator first input port VREF is supplied with a constant threshold reference voltage VTH, then when the saw-tooth waveform S1is at zero volts all of the bias current IB supplied through the first bias current transistor301will flow through the second input transistor305. All of the bias current IB supplied through the first bias current transistor301will therefore flow through the second current mirror control transistor309. In this state of operation, the transistors304,307and308will be in a non-conducting (off) state and therefore the second bias current transistor302pulls the gate of the transition time reduction transistor311to approximately VDD. The transition time reduction transistor311is therefore in a non-conducting state and since the second current mirror output transistor310is in a conducting (ON) state the output port VOUT will be pulled towards GND (zero volts).

When the voltage of the saw-tooth waveform S1is slightly greater than the threshold reference voltage VTH, most of the bias current IB supplied through the first bias current transistor301will flow through the first input transistor304. This results in a greater proportion of the bias current IB flowing in the first current mirror control transistor307as compared that flowing in the second current mirror control transistor309. Accordingly, the second current mirror output transistor310is essentially transitioning to a non-conducting state whereas the first current mirror output transistor308is in a conducting state which pulls the gate of the transition time reduction transistor311towards GND. When the gate voltage of the transition time reduction transistor311drops to VDD-VT (where VT is the transistor's conducting threshold voltage) transistor311begins conducting and therefore connects the output port VOUT to VDD.

Since the width to length ratio (W/L) of the transition time reduction transistor311is relatively large, it rapidly transitions the state of the output port VOUT from zero volts (GND) to VDD thereby reducing the inherent low to high transition delay DLH of the comparator300. Similarly, when the voltage of the saw-tooth waveform S1decays so that it is slightly less than the threshold reference voltage VTH, most of the bias current IB supplied through the first bias current transistor301will again flow through the second input transistor305. As a result, the second current mirror output transistor310will rapidly pull the output port VOUT from VDD to zero volts (GND) thereby reducing the inherent high to low transition delay DHL of the comparator300. It will be apparent to a person skilled in the art that the comparator first input port VREF and comparator second input port VIN can be interchanged so that the saw-tooth waveform S1is applied to the inverting input instead of the non-inverting of the comparator300. In this regard, depending on the operational requirements of comparator300application, either or both output ports VOUT or VOUT1can be used as an output port of the comparator300.

Referring toFIG. 4, a circuit diagram of a comparator400in accordance with a second preferred embodiment of the present invention is shown. The comparator400includes a first bias current transistor401, second bias current transistor402and a third bias current transistor403. Each of the bias current transistors401,402,403has a first node coupled to a first power supply rail GND and each of the bias current transistors401,402,403has a gate coupled to a common regulating input VB. The first, second and third bias current transistors401,402,403are identical and therefore have the same conductivity properties across their channels. In operation they each provide a bias current IB that has identical maximum current flow limits in each of the first, second and third bias current transistors401,402,403.

There is a first input transistor404and a second input transistor405forming a pair of parallel coupled transistors406having common nodes coupled to a second node of the first bias current transistor401. The first input transistor404has a gate providing a comparator second input port VIN and the second input transistor405has a gate providing a comparator first input port VREF. The first input transistor404and second input transistor405are identical and when equal potentials are applied to the comparator first input port VREF and comparator second input port VIN, equal currents of IB/2 flow through both the first input transistor404and the second input transistor405.

There is a first current mirror control transistor407coupling the first input transistor404to a second power supply rail VDD. There is also a first current mirror output transistor408with a gate coupled to a gate of the first current mirror control transistor407. The first current mirror output transistor408couples a second node of the second bias current transistor402to the second power supply rail VDD and the first current mirror output transistor408is larger than the first current mirror control transistor407. More specifically, the first current mirror output transistor408has a width to length ratio (W/L) of at least twice that of the width to length ration (W/L) of the first current mirror control transistor407.

A second current mirror control transistor409couples the second input transistor405to the second power supply rail VDD. There is also a second current mirror output transistor410with a gate coupled to a gate of the second current mirror control transistor409. The second current mirror output transistor410couples a second node of the third bias current transistor403to the second power supply rail VDD and the second current mirror output transistor410is larger than the second current mirror control transistor409. Again, more specifically, the second current mirror output transistor410has a width to length ratio (W/L) of at least twice that of a width to length ratio (W/L) of the second current mirror control transistor409.

The comparator400also includes a transition time reduction transistor411coupled across the third bias current transistor403. A first node of the transition time reduction transistor411is coupled to the first power supply rail GND and a second node of the transition time reduction transistor is coupled to the second node of the third bias current transistor403. A gate of the transition time reduction transistor411is coupled to the second node of the second bias current transistor402, and the second node of the transition time reduction transistor411provides an output port VOUT for the comparator400. There is also another output port VOUT1which is coupled to the output port VOUT through an inverter414and simply provides an inverted output of a signal or voltage level at output port VOUT.

There there is a first isolating transistor412inserted between the first current mirror output transistor408and the second bias current transistor402. There is also a second isolating transistor413inserted between the second current mirror output transistor410and the third bias current transistor403. Gates of the both the first isolating transistor412and second isolating transistor413are coupled to a bias voltage which in this embodiment is a common isolating transistor bias voltage VCAS. The first isolating transistor412and second isolating transistor413reduce the capacitance loading effects of the first current mirror output transistor408and second current mirror output transistor410respectively. Hence, as above, the inclusion of the first isolating transistor412and second isolating transistor413provides for a reduction in response time at the output port VOUT.

In this embodiment transistors401,402,403,404,405and411are N Channel FETs and transistors407,408,409,410,412and413are P Channel FETs. Also, in operation VDD would typically be set to approximately 3.3 volts, VB would be set to about 1 volt and VCAS would be set to about 2.2 Volts. It would therefore be apparent that in this embodiment VREF must be at least 1.2 volts and therefore it may not be able to operate at the same high frequency and low power applications as the comparator300.

If a saw-tooth waveform S1is supplied to the comparator second input port VIN, whilst the comparator first input port VREF is supplied with a constant threshold reference voltage VTH, then when the saw-tooth waveform S1is at zero volts all of the bias current IB through the first bias current transistor401will flow through the second input transistor405. All of the bias current IB flowing through the first bias current transistor401will therefore flow through the second current mirror control transistor409. In this state of operation, the transistors404,407and408will be in a non-conducting (off) state and therefore the second bias current transistor402pulls the gate of the transition time reduction transistor411to GND. The transition time reduction transistor411is therefore in a non-conducting state and since the second current mirror output transistor410is in a conducting (ON) state the output port VOUT will be pulled towards VDD.

When the voltage of the saw-tooth waveform S1is slightly greater than the threshold reference voltage VTH, most of the bias current IB flowing through the first bias current transistor401will flow through the first input transistor404. This results a greater proportion of the bias current IB flowing in the first current mirror control transistor407as compared that flowing in the second current mirror control transistor409. Accordingly, the second current mirror output transistor410is essentially transitioning to a non-conducting state whereas the first current mirror output transistor408is in a conducting state which pulls the gate of the transition time reduction transistor411towards VDD. When the gate voltage of the transition time reduction transistor411rises to GND+VT (where VT is the transistor's conducting threshold voltage) transistor411begins conducting and therefore connects the output port VOUT to GND.

Since the width to length ratio (W/L) of the transition time reduction transistor411is relatively large, it rapidly transitions the state of the output port VOUT from VDD volts to GND thereby reducing the inherent high to low transition delay DHL of the comparator400. Similarly, when the voltage of the saw-tooth waveform S1decays so that it is slightly less than the threshold reference voltage VTH, most of the bias current IB flowing through the first bias current transistor401will again flow through the second input transistor405. As a result, the second current mirror output transistor410will rapidly pull the output port VOUT from GND to VDD volts thereby reducing the inherent low to high transition delay DLH of the comparator400. As above, it will be apparent to a person skilled in the art that the comparator first input port VREF and comparator second input port VIN can be interchanged so that the saw-tooth waveform S1is applied to the non-inverting input instead of the inverting of the comparator400. In this regard, depending on the operational requirements of comparator300application, either or both output ports VOUT or VOUT1can be used as an output port of the comparator400.

Referring toFIG. 5, a circuit diagram of a relaxation oscillator500in accordance with a third preferred embodiment of the present invention is shown. The relaxation oscillator500is an improved version of the prior art relaxation oscillator300and to avoid repetition only the differences will be described. The relaxation oscillator500has a set comparator508which is the comparator300with the common isolating transistor bias voltage VCAS and the common regulating input VB. As shown, the set comparator second input port (+) is coupled to an electrode of the set capacitor106and the discharge transistor107is coupled across the set capacitor106.

The relaxation oscillator500also has a reset comparator513which is the comparator300with the common isolating transistor bias voltage VCAS and the common regulating input VB. The reset comparator second input port (+) is coupled to an electrode of the reset capacitor111and the reset discharge transistor112is coupled across the reset capacitor111. Furthermore, the set comparator output port is coupled to the set input of the set reset latch109and the reset comparator output port is coupled to the reset input of the set reset latch109. The oscillator output node OUT is coupled to the output Q of the Set-Reset latch109but, if required, it can be coupled to output QBAR of the Set-Reset latch109.

Referring toFIG. 6, a circuit diagram of a relaxation oscillator600in accordance with a fourth preferred embodiment of the present invention is illustrated. The relaxation oscillator600has constant current source601coupled between a supply voltage node VDD on one side and a drain and a gate electrode of a first bias transistor602on the other side. The gate electrode of the first reference transistor602is coupled to a gate electrode of a first mirror transistor603and the source electrodes of both transistors602,603are coupled to a return voltage node (ground GND).

A second reference transistor604with a source electrode is coupled to the supply voltage node VDD and a gate electrode of the second reference transistor604is coupled to its own drain electrode, and to both a drain electrode of the first mirror transistor603and to a gate electrode of a second mirror transistor605. A source electrode of the second mirror transistor605is coupled to the supply voltage node VDD and a drain electrode of the second mirror transistor605is coupled to a first electrode of a capacitor606. A second electrode of the capacitor606is coupled to ground GND and the first electrode of the set capacitor606is further coupled to both a drain electrode of a discharge transistor607and a positive input of a comparator608. Hence, the discharge transistor607coupled across a capacitor606.

The comparator608is the comparator300with the common isolating transistor bias voltage VCAS and the common regulating input VB. The output of the comparator608is coupled to the gate of the discharge transistor607through a delay circuit609. Furthermore, the oscillator output node OUT is coupled to the output of the comparator608and the output node OUT may be coupled through buffering circuitry if required.

As will be apparent to a person skilled in the art, although the oscillators500and600use the comparator300, the comparator400can also be used. Furthermore, the inverting and non-inverting inputs of these comparators300,400can be interchanged with minor adjustments to the oscillator circuitry. In this regard either or both output ports VOUT or VOUT1can be used as an output port of the comparator300or400.

Advantageously, the present invention provides for reducing or alleviating inherent low to high transition delays DLHs and/or high to low transition delays DHL in comparators. More specifically, then bias current IB can be relatively small and thus power consumption of the comparator300,400is smaller than conventional rapid response comparators. The present invention is also especially beneficial for relaxation oscillators that use such relatively low power consumption comparators where either or both inherent low to high transition delays DLHs and/or high to low transition delays DHL are undesirable.

The description of the preferred embodiments of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or to limit the invention to the forms disclosed. It will be appreciated by those skilled in the art that changes could be made to the embodiments described above without departing from the broad inventive concept thereof. It is understood, therefore, that this invention is not limited to the particular embodiment disclosed, but covers modifications within the spirit and scope of the present invention as defined by the appended claims.