Semiconductor device and method of fabricating the same

MOSFETs and methods of making MOSFETs are provided. According to one embodiment, a semiconductor device includes a substrate and a Metal-Oxide-Semiconductor (MOS) transistor that includes a semiconductor region formed on the substrate, a source region and drain region formed in the semiconductor region that are separated from each other, a channel region formed in the semiconductor region that separates the source region and the drain region, an interfacial oxide layer (IL) formed on the channel region into which at least one element disparate from Si, O, or N is incorporated at a peak concentration greater than 1×1019 atoms/cm2, and a high-k dielectric layer formed on the interfacial oxide layer having a high-k/IL interface at a depth substantially adjacent to the IL. In addition, at least one depth of peak density of the incorporated element(s) is located substantially below the high-k/IL interface.

FIELD

Embodiments described herein relate generally to Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) and methods for fabricating MOSFETs.

BACKGROUND

Silicon large-scale integrated circuits, among other device technologies, are increasing in use in order to provide support for the advanced information society of the future. To produce an integrated circuit with highly sophisticated functions, semiconductor devices that yield high performance, such as MOSFETs or CMOSFETs (Complementary MOSFETs), can be utilized to constitute an integrated circuit.

In the design of a MOSFET, CMOSFET, and/or similar devices, formation of gate electrodes having respective optimum threshold voltage(s) according to factors such as device structure, conductivity types, operation voltage, etc., can complicate the production process of such devices. This added complication can, in turn, increase the production costs for such devices and/or introduce a loss of efficiency or other such effects. Accordingly, it would be desirable to implement techniques for controlling the threshold voltage of each electrode corresponding to a MOSFET, CMOSFET, or the like through simple, easily implementable procedures.

DETAILED DESCRIPTION

The subject innovation provides respective semiconductor devices having third elements, which are not the main components of the high-k and/or interfacial oxide layers, doped in the gate dielectric and/or interfacial oxide layer. In various embodiments, one of the peak density depth regions is located channel-side below the high-k/interfacial oxide interface. In various other embodiments, an additional layer is introduced into a semiconductor device above or at the high-k/interfacial oxide interface, thereby introducing two depths of peak doping density. In further embodiments, methods of fabricating semiconductor devices according to at least the above are provided.

According to one embodiment, a semiconductor device includes a substrate and a Metal-Oxide-Semiconductor (MOS) transistor. The MOS transistor includes a semiconductor region formed on the substrate, a source region and drain region formed in the semiconductor region that are separated from each other, a channel region formed in the semiconductor region that separates the source region and the drain region, an interfacial oxide layer (IL) formed on the channel region into which at least one element disparate from Si, O, or N is incorporated at a peak concentration greater than 1×1019atoms/cm2, and a high-k dielectric layer formed on the interfacial oxide layer having a high-k/IL interface at a depth substantially adjacent to the IL. Within the semiconductor device, at least one depth of peak density of the element(s) incorporated into the IL is located substantially below the high-k/IL interface. The MOS transistor can be a p-channel MOS or pMOS transistor, in which case elements that can be incorporated into the IL include Al and Ge. Additionally or alternatively, the MOS transistor can be an n-channel MOS or nMOS transistor, in which case elements that can be incorporated into the IL include La, Y, Mg, Lu, Gd, Ba, and Ti.

According to another embodiment, a semiconductor device includes a substrate and a MOS transistor. The MOS transistor includes a semiconductor region formed on the substrate, a source region and drain region formed in the semiconductor region that are separated from each other, a channel region formed in the semiconductor region that separates the source region and the drain region, an interfacial oxide layer (IL) formed on the channel region into which at least one element disparate from Si, O, or N is incorporated at a peak concentration greater than 1×1019atoms/cm2, a high-k dielectric layer formed on the interfacial oxide layer having a high-k/IL interface at a depth substantially adjacent to the IL, and a supplemental layer adjacent to the high-k dielectric layer that is substantially composed of the element(s) incorporated into the IL or at least one oxide of said element(s). Within the semiconductor device, at least a first depth of peak density of the element(s) incorporated into the IL is located substantially below the high-k/IL interface, and at least a second depth of peak density of the element(s) incorporated into the IL is located at a depth corresponding to the supplemental layer. The supplemental layer can be located at a depth corresponding to the high-k/IL interface and/or a depth located substantially above the high-k dielectric layer. In addition, the MOS transistor can be a p-channel MOS or pMOS transistor, in which case elements that can be incorporated into the IL and/or the supplemental layer include Al and Ge. Additionally or alternatively, the MOS transistor can be an n-channel MOS or nMOS transistor, in which case elements that can be incorporated into the IL and/or the supplemental layer include La, Y, Mg, Lu, Gd, Ba, and Ti.

According to a further embodiment, a method of fabricating a semiconductor device includes producing a substrate, forming a channel region in the substrate, forming an IL on the channel region, doping at least one element that is disparate from Si, O, or N into the channel region and/or the IL, and depositing a high-k dielectric upon the IL. The at least one element can be doped into the IL between formation of the IL and high-k deposition. Alternatively, the at least one element can be doped into the channel region prior to IL formation. In the event that the at least one element is doped into the channel region, an anneal can be performed between IL formation and high-k deposition. Doping can in some cases be conducted such that a peak position of the at least one element is greater than 1A from a surface of the region into which the at least one element is doped. Further, doping can in some cases be conducted via ion implantation (e.g., at an energy level substantially less than 10 keV).

The following description and the annexed drawings set forth certain illustrative aspects of the specification. These aspects are indicative, however, of but a few of the various ways in which the principles of the specification may be employed. Other advantages and novel features of the specification will become apparent from the following detailed description of the disclosed information when considered in conjunction with the drawings.

Referring first toFIG. 1, a cross-sectional illustration of an example semiconductor device100is provided in accordance with an embodiment. As shown inFIG. 1, semiconductor device100can include a substrate and a p-channel MOS transistor or MOSFET, also referred to herein as a pMOS transistor. The pMOS transistor includes an n-type semiconductor region formed on the substrate and a source region102and drain region104, wherein the source and drain regions are formed in the n-type semiconductor region and are separated from each other. In addition, the pMOS transistor can include a channel region formed in the n-type semiconductor region that separates the source region102and drain region104. The pMOS transistor can further include an interfacial oxide layer (IL)106situated upon the channel and located between the gate and source/drain regions. In addition, the pMOS transistor can include a gate or high-k dielectric108having a high dielectric constant k, upon which a gate electrode110can be placed.

In a specific, non-limiting example, IL106can contain a channel material (e.g., Si, Ge, C, etc.). Additionally, oxygen, and optionally nitrogen, can be incorporated. In another non-limiting example, high-k dielectric108can exhibit a thickness between approximately 0.1 nm and approximately 25 nm. Further, high-k dielectric108can be constructed using a variety of metal-Si materials and/or any other suitable material(s) having a high dielectric constant. For example, materials that can be utilized for high-k dielectric108can include compositions having the following chemical formulae: HfxSi1-xO2, HfxSi1-xON, ZrxSi1-xO2, ZrxSi1-xON, LaxSi1-xO2, LaxSi1-xON, GdxSi1-xO2, GdxSi1-xON, HfZrSiO, HfZrSiON, HfLaSiO, and HfGdSiO, where x is between 0 and 1. It should be appreciated, however, that the preceding list is provided merely by way of example and that other compositions could also be utilized. In a further non-limiting example, gate electrode110can be formed using a metal or metallic alloy. Specific examples of compositions that can be utilized for gate electrode110include metals such as Ti, Hf, Ta, W, Al, Ru, Pt, Re, Cu, Ni, Pd, Ir, and/or Mo; nitrides and carbides such as TiN, TaN, TiC, TaC, WN, WC, and/or HfN; conductive oxides such as RuOx and/or ReOx; metal-metal-alloys such as Ti—Al, Hf—Al, Ta—Al, and/or TaAlN; multi-stacked structures of the preceding compositions, such as TiN/W, TiN/Ti—Al, Ta/TiN/Ti—Al, or the like. According to an embodiment, one or more of the above compositions can be stacked with a Si and metal-silicide, such as NiSix, PtSix, PdSix, CoSix, TiSix, WSix, etc. It should be appreciated, however, that the preceding list is provided by way of example and that other compositions could be utilized for gate electrode110.

With respect to the construction of semiconductor device100, as well as various other semiconductor devices as illustrated and described herein, it can be appreciated that the formation of gate electrodes having the respective optimum threshold voltages according to device structure, conductivity types, operation voltage, etc., can in some cases complicate the production process of a related CMOSFET and/or other semiconductor device, thereby increasing the production costs and/or introducing other negative effects. Accordingly, it can be appreciated that methods for controlling the threshold voltage of each electrode through simple procedures are desirable. Thus, according to an embodiment, third elements, which are not the main components of the high-k and interfacial oxide layers in a semiconductor device, can be doped in the gate dielectric and/or interfacial oxide layer. In one example, at least one resulting peak density depth region can be located below the high-k/interfacial oxide interface, channel-side. By constructing a semiconductor device in this manner, it can be appreciated that a work function can be easily modulated via a smaller amount of dosing compared to conventional methods, resulting in improvement of device performance.

With respect to the above and the embodiments that follow, it can be appreciated that whileFIG. 1and the respective other illustrations provided herein show examples of semiconductor devices for which the embodiments can be implemented, the embodiments described herein can also be applicable for novel channel devices (e.g., SiGe, SiC, SiGeC, III-V materials, etc.), novel device structures (e.g., Si on insulator (SOI), 3-dimensional transistors (e.g., finFET, verticalFET, nanowire, nanotube, . . . ), etc.), and/or any other suitable device type(s). In addition, it can be appreciated that incorporation of Al (and/or Ge or any other suitable element(s)) can be utilized for high-threshold voltage (Vt) nMOS in addition to, or in place of, the pMOS transistor illustrated in relation to semiconductor device100.

According to an embodiment, enhanced threshold voltage modulation for semiconductor device100can be achieved by introducing one or more third elements (e.g., an element not utilized as the main component(s) of IL106or high-k dielectric108) to IL106and/or high-k dielectric108. By way of example, as shown inFIG. 1, Al can be incorporated into IL106, thereby effecting a positive threshold voltage shift for semiconductor device100. This technique is in contrast to conventional semiconductor fabrication techniques, wherein a layer of Al and/or another suitable material is inserted at one or more depths within the semiconductor device. For example, as shown byFIG. 2, graph202shows the depth profile of the density of Al within a semiconductor device having an Al inserted layer on the high-k layer, and graph204illustrates the depth profile of the density of Al within a semiconductor device having an Al inserted layer at the high-k/IL layer. Contrastingly, by incorporating one or more third elements into IL106and/or high-k dielectric108of semiconductor device100, a depth profile of the density of Al within semiconductor device100can be substantially similar to that illustrated by graph300inFIG. 3. As shown by graph300, the Al peak density depth region of semiconductor device100can be located below the high-k interfacial oxide interface and on the Si channel side, in contrast to the conventional approaches illustrated by graphs202and204.

Referring again toFIG. 1, and as noted above, Al in one embodiment can be incorporated at least in IL106. In one example, Al in IL106can be utilized to modulate the threshold voltage Vtof semiconductor device100, which corresponds to a positive work function modulation depending on the concentration of Al. According to another embodiment, the peak concentration of Al in IL106can be approximately 1019atoms/cm2to approximately 1022atoms/cm2.

While semiconductor device100illustrates a MOS transistor having Al incorporated in the interfacial oxide layer, it should be appreciated that other implementations can be utilized. For example, Al can be incorporated in the channel or high-k dielectric108of semiconductor device100in addition to or in place of IL106. Further, other elements, such as Ge or the like, can be incorporated in addition to, or in place of, Al.

According to an embodiment, graph400inFIG. 4illustrates example data showing the relationship between Al concentration in a semiconductor device according to various incorporation methods and the baseline threshold voltage Vtlinof the semiconductor device. It should be appreciated, however, that while graph400shows data for the specific example case of Al incorporation, similar results could be achieved in the case of Ge incorporation and/or the incorporation of other suitable materials.

With further reference to graph400, line402represents threshold voltage data obtained via Al ion implantation (I/I) at a substantially high energy and line404represents threshold voltage data obtained via Al ion implantation at a substantially low energy. In the case of both lines402and404, Al ions are ion implanted to the interfacial oxide layer of a semiconductor device prior to high-k deposition. Further, Al is incorporated at a dose range of 1013to 1016ions/cm2and an energy range of less than 1 keV. It should be appreciated, however, that the dose and energy utilized for implantation can in some cases depend on element species.

In both cases of Al ion implantation to the interfacial oxide layer as illustrated by lines402and404, it can be observed from graph400that a substantially larger amount of threshold voltage modulation can be achieved at a comparable Al density to conventional threshold voltage modulation approaches, illustrated by lines412through418. In particular, line412illustrates threshold voltage modulation results obtained via fluorine ion implantation to the channel, line414illustrates threshold voltage modulation results based on Al layer insertion at the high-k/IL interface (e.g., as shown by graph204), line416illustrates threshold voltage modulation results based on Al ion implantation through the metal gate and high-k layers, and line418illustrates threshold voltage modulation results using Al layer insertion at the top of the high-k layer (e.g., as shown by graph202).

According to an embodiment, a pMOS transistor (e.g., such as that illustrated by semiconductor device100inFIG. 1) having Al and/or another suitable element incorporated via ion implantation can suppress Vtlinfluctuation via resist-strip reworking and/or other suitable techniques. For example, diagram500inFIG. 5illustrates a comparison of Vtlinfor cases with and without Al incorporation into the IL for various resist-strip wet processing iterations. In the examples illustrated by diagram500, resist-strip wet processing is performed before the Al I/I step to simulate the CMOS integration process flow. As diagram500illustrates, although the Vtlinvalues shift negatively in the cases without Al I/I to the IL, a Vtlinthat is substantially stable against wet etching can be realized by adding Al. It can be appreciated that this benefit can be supplemental to other benefits described herein, such as positive Vtlinshifts. While the above example is illustrated for the specific case of Al incorporation, however, it should be appreciated that this improvement of Vtlinstability can also be achieved via the incorporation of any other suitable element(s) as generally described herein.

Turning next toFIG. 6, a cross-sectional illustration of an example semiconductor device600is provided in accordance with an embodiment. As shown inFIG. 6, semiconductor device600can include a substrate and an n-channel MOS transistor or MOSFET, also referred to herein as an nMOS transistor. The nMOS transistor includes a p-type semiconductor region formed on the substrate and a source region602and drain region604, wherein the source and drain regions are formed in the p-type semiconductor region and are separated from each other. In addition, the nMOS transistor can include a channel region formed in the p-type semiconductor region that separates the source region602and the drain region604. The nMOS transistor can further include an interfacial oxide layer (IL)606situated upon the channel region and located between the gate and source/drain regions. In addition, the nMOS transistor can include a gate or high-k dielectric608having a high dielectric constant k, upon which a gate electrode610can be placed.

According to an embodiment, IL606, high-k dielectric608, and gate electrode610can be constructed to exhibit similar properties and/or to utilize similar compositions to those described above with respect to semiconductor device100. More particularly, and by way of non-limiting example, IL606can contain a channel material (e.g., Si, Ge, C, etc.), to which oxygen, and optionally nitrogen, can be incorporated. In another non-limiting example, high-k dielectric608can exhibit a thickness between approximately 0.1 nm and approximately 25 nm. Further, high-k dielectric608can be constructed using a variety of metal-Si materials and/or any other suitable material(s) having a high dielectric constant. For example, materials that can be utilized for high-k dielectric608can include compositions having the following chemical formulae: HfxSi1-xO2, HfxSi1-xON, ZrxSi1-xO2, ZrxSi1-xON, LaxSi1-xO2, LaxSi1-xON, GdxSi1-xO2, GdxSi1-xON, HfZrSiO, HfZrSiON, HfLaSiO, and HfGdSiO, where x is between 0 and 1. It should be appreciated, however, that the preceding list is provided merely by way of example and that other compositions could also be utilized. In a further non-limiting example, gate electrode610can be formed using a metal or metallic alloy. Specific examples of compositions that can be utilized for gate electrode610include metals such as Ti, Hf, Ta, W, Al, Ru, Pt, Re, Cu, Ni, Pd, Ir, and/or Mo; nitrides and carbides such as TiN, TaN, TiC, TaC, WN, WC, and/or HfN; conductive oxides such as RuOx and/or ReOx; metal-metal-alloys such as Ti—Al, Hf—Al, Ta—Al, and/or TaAlN; multi-stacked structures of the preceding compositions, such as TiN/W, TiN/Ti—Al, Ta/TiN/Ti—Al, or the like. According to an embodiment, one or more of the above compositions can be stacked with a Si and metal-silicide, such as NiSix, PtSix, PdSix, CoSix, TiSix, WSix, etc. It should be appreciated, however, that the preceding list is provided by way of example and that other compositions could be utilized for gate electrode610.

According to another embodiment as illustrated byFIG. 6, La can be incorporated at least in the IL606of semiconductor device600. In one example, La in IL606can be utilized to facilitate modulation of the threshold voltage Vtof semiconductor device600via a negative shift of the threshold voltage of semiconductor device600. Such modulation can, in one example, correspond to negative effective work function modulation. According to a further embodiment, the peak concentration of La in IL606can be approximately 1019atoms/cm2to approximately 1022atoms/cm2.

While semiconductor device600illustrates a MOS transistor having La incorporated in the interfacial oxide layer, it should be appreciated that other implementations can be utilized. For example, La can be incorporated in the channel or high-k dielectric608of semiconductor device600in addition to or in place of IL606. Further, other elements, such as Y, Mg, Lu, Gd, Ba, Ti, or the like, can be incorporated in addition to, or in place of, La. According to an embodiment, La (and/or one or more of the other elements listed above and/or any other suitable element(s)) can be utilized for high-VtpMOS in addition to, or in place of, the nMOS transistor shown in relation to semiconductor device600. Further, while semiconductor device600illustrates a MOS transistor, it is to be appreciated that the embodiments described herein can also be applicable for novel channel devices (e.g., SiGe, SIC, SiGeC, III-V materials, etc.), novel device structures (e.g., Si on insulator (SOI), 3-dimensional transistors (e.g., finFET, verticalFET, nanowire, nanotube, . . . ), etc.), and/or any other suitable device type(s).

Referring next toFIG. 7, a cross-sectional illustration of another example semiconductor device700is provided in accordance with an embodiment. As shown byFIG. 7, semiconductor device700can include a pMOS transistor, which can be constructed using a source region102, a drain region104, an interfacial oxide layer106, a high-k dielectric108, and a gate electrode110in a similar manner to that described above in relation to semiconductor device100. According to an embodiment, Al (and/or Ge or any other suitable element(s)) can be incorporated into at least IL106of semiconductor device700, thereby facilitating enhanced threshold voltage modulation for semiconductor device700via positive threshold voltage shifting in a similar manner to that described above with respect to semiconductor device100. According to another embodiment, semiconductor device700can additionally include a supplemental layer702of Al or AlOx(and/or Ge or GeOx, or any other suitable element or metal-oxide) at the high-k/gate interface of semiconductor device700. According to a further embodiment, supplemental layer702can exhibit a thickness between approximately 0.1 nm and approximately 3 nm.

By incorporating a supplemental layer702at the high-k/gate interface of semiconductor device700, it can be appreciated that the depth profile of the density of Al (or Ge) within semiconductor device700can be substantially similar to that illustrated by graph800inFIG. 8. As graph800illustrates, by incorporating one or more supplemental layers within the semiconductor device, more than one depth of peak density can exist. For example, a first depth of peak density can be below the high-k/IL interface due to dosing of one or more third elements as described with relation to semiconductor device100, and a second depth of peak density can be above or at the high-k/IL interface due to incorporation of a supplemental layer as described with relation to semiconductor device700.

Additionally or alternatively, although not shown inFIG. 7, a supplemental layer can be implemented at the high-k/IL interface of semiconductor device700. By including one or more supplemental layers702into semiconductor device700in addition to dosing of at least IL106as described above, it can be appreciated that a Vtshift that is larger than conventional techniques as well as the structure shown byFIG. 1can be obtained.

To illustrate the Vtshift achievable by semiconductor device700inFIG. 7, graph900inFIG. 9illustrates baseline threshold voltage data relating to various semiconductor device implementations as a function of gate dielectric thickness under inversion (Tinv). In particular, line902in graph900represents a semiconductor device for which both Al ion implantation in the IL and an Al layer on the high-k layer have been implemented, line904represents a semiconductor device for which only an Al layer on the high-k layer has been implemented, and line906represents a semiconductor device for which only Al ion implantation on the IL has been implemented. Further, the points below lines902-906represent a control device, for which neither Al ion implantation nor an Al layer have been implemented. Accordingly, as shown by graph900, both the Al ion implantation technique and the Al layer technique yield a higher amount of threshold voltage modulation than the control case. As further shown by graph900, the combination of the Al ion implantation technique and the Al layer technique yield a greater amount of threshold voltage modulation than either technique performed separately.

Turning toFIG. 10, a cross-sectional illustration of yet another example semiconductor device900is provided in accordance with an embodiment. As shown byFIG. 10, semiconductor device1000can include an nMOS transistor, which can be constructed using a source region602, a drain region604, an interfacial oxide layer606, a high-k dielectric608, and a gate electrode610in a similar manner to that described above in relation to semiconductor device600. Further, La (or Y, Mg, Lu, Gd, Ba, Ti, and/or any other suitable element(s)) can be incorporated into at least IL606of semiconductor device1000, thereby facilitating enhanced threshold voltage modulation for semiconductor device1000via negative threshold voltage shifting in a similar manner to that described above with respect to semiconductor device600. According to another embodiment, semiconductor device900can additionally include a supplemental layer1002of La or LaOx(and/or Y, Mg, Lu, Gd, Ba, Ti, any other suitable element(s), or any metal-oxide of such element(s)) at the high-k/gate interface of semiconductor device1000. According to a further embodiment, supplemental layer1002can exhibit a thickness from approximately 0.1 nm to approximately 3 nm.

By incorporating a supplemental layer1002at the high-k/gate interface of semiconductor device1000, it can be appreciated that more than one depth of peak density can exist, in a similar manner to that shown by graph800in relation to semiconductor device700. For example, a first depth of peak density can be below the high-k/IL interface due to dosing of one or more third elements as described with relation to semiconductor device600, and a second depth of peak density can be above or at the high-k/IL interface due to incorporation of a supplemental layer as described with relation to semiconductor device1000.

Additionally or alternatively, although not shown inFIG. 10, a supplemental layer can be implemented at the high-k/IL interface of semiconductor device1000. By including one or more supplemental layers1002into semiconductor device1000in addition to dosing of at least IL606as described above, it can be appreciated that a Vtshift that is larger than conventional techniques as well as the structure shown byFIG. 6can be obtained.

According to an embodiment, various semiconductor devices, such as semiconductor devices100,600,700, and/or1000or any other suitable semiconductor device(s), can be combined in various manners to form additional device structures. Examples of such device structures that can be formed based on respective semiconductor devices as described herein are illustrated byFIGS. 11 through 14. Referring first toFIG. 11, a CMOS semiconductor device1100is illustrated, which includes a pMOS transistor1102and an nMOS transistor1104. According to an embodiment, pMOS transistor1102and nMOS transistor1104can have one or more third elements incorporated in at least their respective interfacial oxide layers, thereby facilitating enhanced threshold voltage modulation in a similar manner to semiconductor devices100and600, respectively.

FIG. 12illustrates an example multi-VtpMOS semiconductor device1200that can be utilized according to another embodiment, which can include a first pMOS transistor1202and a second pMOS transistor1204. In one example, the pMOS transistors1202and1204can have at least one third element incorporated into at least their respective interfacial oxide layers, in a similar manner to that described above relating to pMOS transistor1102and semiconductor device100. In addition, the second pMOS transistor1204can have a supplemental layer of Al, AlOx, and/or any other suitable element(s) or metal-oxide(s) in a similar manner to semiconductor device700, thereby facilitating threshold voltage modulation that is substantially higher than that of the first pMOS transistor1202and enabling the multi-Vtoperation of semiconductor device1200.

FIG. 13illustrates an example multi-VtnMOS semiconductor device1300that can be utilized according to yet another embodiment, which can include a first nMOS transistor1302and a second nMOS transistor1304. In one example, the nMOS transistors1302and1304can have at least one third element incorporated into at least their respective interfacial oxide layers, in a similar manner to that described above relating to nMOS transistor1104and semiconductor device600. In addition, the second nMOS transistor1304can have a supplemental layer of La, LaOx, and/or any other suitable element(s) or metal-oxide(s) in a similar manner to semiconductor device1000, thereby facilitating threshold voltage modulation that is substantially higher than that of the first nMOS transistor1302and enabling the multi-Vtoperation of semiconductor device1300.

Referring next toFIG. 14, a second CMOS semiconductor device1400is illustrated according to an additional embodiment, which includes a pMOS transistor1402and an nMOS transistor1404. According to an embodiment, pMOS transistor1402and nMOS transistor1404can have one or more third elements incorporated in at least their respective interfacial oxide layers, thereby facilitating enhanced threshold voltage modulation in a similar manner to semiconductor devices100and600, respectively. Further, pMOS transistor1402and nMOS transistor1404can additionally include at least one supplemental metal or metal-oxide layer in a similar manner to semiconductor devices700and1000, respectively, thereby facilitating a greater amount of threshold voltage modulation than that which can be achieved via ion implantation or the supplemental layers individually.

Turning next toFIGS. 15-18, various techniques for fabricating a semiconductor device according to at least the embodiments described above are presented. It should be appreciated, however, that the semiconductor devices described above can be created using any suitable process or combination of processes and that the following description is provided by way of non-limiting example. Further, it should be appreciated that the processes presented in the following description can be utilized to fabricate any suitable product(s) and are not intended to be limited to the semiconductor devices described above.

With reference first toFIG. 15, a first example procedure for semiconductor device fabrication in accordance with an embodiment of the subject innovation is illustrated via a diagram1500. As diagram1500illustrates, upon formation of the interfacial oxide layer, Al (or other suitable element(s)) can be incorporated into the interfacial oxide layer via various techniques such as ion implantation (e.g., at an energy of less than 10 keV and/or any other suitable energy level), plasma doping, low-temperature ion implantation, in which wafer temperature is decreased below room temperature during ion implantation process, and/or any other suitable techniques or combination of techniques for incorporating material into the interfacial oxide layer. In a specific, non-limiting example, the peak position of the element(s) doped into the semiconductor device during the incorporation step can be substantially greater than 1A from the surface of the semiconductor device at the time of the incorporation step (e.g., the surface of the interfacial oxide layer). Following incorporation of Al and/or other suitable materials into the interfacial oxide layer, the semiconductor fabrication process can continue via high-k deposition and/or any other suitable act(s). In one example, further annealing, gate formation, and/or any other suitable acts can occur following the high-k deposition. In another example, in the event that one or more supplemental layers (e.g., an Al/AlOxlayer or other suitable layer as shown inFIG. 7, a La/LaOxlayer or other suitable layer as shown inFIG. 10, etc.) is desired, formation of supplemental layer(s) can be conducted prior to and/or after high-k deposition in accordance with various techniques as generally known in the art.

According to an embodiment, an example methodology for conducting at least partial fabrication of a semiconductor device is illustrated by flow diagram1600inFIG. 16. As flow diagram1600illustrates, an example semiconductor device fabrication methodology can include channel generation at1602, followed by formation of an interfacial oxide layer to the channel at1604and ion implantation to the interfacial oxide layer at1606. Following ion implantation, high-k deposition can be conducted at1608.

Referring next toFIG. 17, a second example procedure for semiconductor device fabrication in accordance with an embodiment of the subject innovation is illustrated via diagrams1702and1704. As initially illustrated by diagram1702, Al (or other suitable element(s)) can be incorporated into the channel surface of a semiconductor device. Techniques that can be utilized for incorporation of third elements into the channel include, e.g., ion implantation (e.g., at an energy of less than 10 keV and/or any other suitable energy level), plasma doping, low-temperature ion implantation, and/or any other suitable techniques or combination of techniques for incorporating material. In a specific, non-limiting example, the peak position of the element(s) doped into the semiconductor device during the incorporation step can be substantially greater than 1A from the surface of the semiconductor device at the time of the incorporation step (e.g., the channel surface). In the case of Ge doping, dose range of 1013to 3×1015ions/cm2and an energy range of less than 5 keV is prefer to obtain large Vt shift with maintaining good crystallinity of channel (high hole/electron mobility channel). Upon incorporation of one or more third elements into the channel, the interfacial oxide layer can be formed onto the channel, as shown by diagram1704. Additionally, an Al segregation anneal (and/or annealing corresponding to any suitable material(s) incorporated into the channel) can be performed in connection with the interfacial oxide layer formation. Following formation of the interfacial oxide layer and annealing, the semiconductor fabrication process can continue via high-k deposition and/or any other suitable act(s). In one example, further annealing, gate formation, and/or any other suitable acts can occur following the high-k deposition. In another example, in the event that one or more supplemental layers (e.g., an Al/AlOxlayer or other suitable layer as shown in FIG.7, a La/LaOxlayer or other suitable layer as shown inFIG. 10, etc.) is desired, formation of supplemental layer(s) can be conducted prior to and/or after high-k deposition in accordance with various techniques as generally known in the art.

According to another embodiment, another example methodology for conducting at least partial fabrication of a semiconductor device is illustrated by flow diagram1800inFIG. 18. As flow diagram1800illustrates, an example semiconductor device fabrication methodology can include channel generation at1802, followed by ion implantation to the channel surface at1804. Formation of an interfacial oxide layer to the channel at1806, and segregation annealing at1808, can then occur. Following interfacial oxide layer formation and annealing, high-k deposition can be conducted at1810.

According to a further embodiment, a screen layer of Si oxide or nitride can be formed at1803prior to ion implantation at1804. Screen layer formation at1803can be performed, for example, to reduce physical damage in the channel during the ion implantation step, such as in the case of heavy ion implantation cases (e.g., Ge, La, etc.). In one example, a screen Si oxide or nitride thickness between approximately 1 nm and approximately 30 nm can be utilized to realize both a shallow depth profile and reduced channel damage.

According to an additional embodiment, a re-crystallization anneal can be performed at1805between ion implantation at1804and IL formation at1806to improve the crystallinity of the channel. Techniques that can be utilized for the re-crystallization anneal at1805can include, but are not limited to, furnace anneal, spike anneal, rapid thermal anneal (RTA), and millisecond anneal. By way of non-limiting example, in the case of RTA or spike anneal, the temperature range used for annealing can be between approximately 700° C. and 1300° C. And adding thin epitaxial Si, SiGe, SiC, or SiGeC layer at the top of the ion implanted layer after re-crystallization anneal is a effective way to improve the hole/electron mobility. The thin epitaxial later thickness at the range of 0.5 nm to 5 nm prefers to realize both large Vt shift and high carrier mobility.

What has been described above includes examples of the disclosed innovation. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the disclosed innovation, but one of ordinary skill in the art can recognize that many further combinations and permutations of the disclosed innovation are possible. Accordingly, the disclosed innovation is intended to embrace all such alterations, modifications and variations that fall within the spirit and scope of the appended claims. Furthermore, to the extent that the term “contain,” “includes,” “has,” “involve,” or variants thereof is used in either the detailed description or the claims, such term can be inclusive in a manner similar to the term “comprising” as “comprising” is interpreted when employed as a transitional word in a claim.

With respect to any figure or numerical range for a given characteristic, a figure or a parameter from one range may be combined with another figure or a parameter from a different range for the same characteristic to generate a numerical range.

Other than in the operating examples, or where otherwise indicated, all numbers, values and/or expressions referring to quantities of ingredients, reaction conditions, etc., used in the specification and claims are to be understood as modified in all instances by the term “about.”

In addition, it should be appreciated that while the respective methodologies provided above are shown and described as a series of acts for purposes of simplicity, such methodologies are not limited by the order of acts, as some acts can, in accordance with one or more aspects, occur in different orders and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all illustrated acts may be required to implement a methodology in accordance with one or more aspects.