1394 module and data processing system with 1394 module

A 1394 module comprises a 1394 controller and a 1394 physical layer. The 1394 controller is connected to the system bus for transmitting bus signals. The 1394 physical layer is connected to an electronic device for transmitting differential signals. The 1394 controller and the 1394 physical layer have a two-way communication by a data signal and a control signal. In addition, a one-way communication by a link request signal, a link power status signal and a clock signal for accessing the internal register of the 1394 physical layer, assigning the power status of the 1394 controller, and synchronizing the request signal, the control signal, and the data signal.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to FIG. 1, a block diagram of a data processing system with a 1394 module according to a preferred embodiment of the invention is shown. The data processing system 100 comprises a CPU (Central Processing Unit), a north bridge 110 , a south bridge (not shown), a system bus 130 , and a 1394 module 150 . In general, the system bus 130 is a Peripheral Component Interconnect (PCI) bus and a bus signal 120 is used for transmitting data between the system bus 130 and the north bridge 110 . On the other hand, the bus signal 120 is also used for connecting the system bus 130 and the 1394 module 150 . When the 1394 module 150 is connected to the electronic device 190 , data is transmitted between the 1394 module 150 and the electronic device 190 via a differential signal 170 in packet. The data processing system 100 mentioned above can be a personal computer or a notebook and the electronic device 190 can be a digital camera, a hard disk drive, a scanner, or a printer compatible to the 1394 module 150 . The invention stated in FIG. 1 can be wildly applied into the daily life. For example, the user may take photos on his digital camera, and since the memory storage of a digital camera is limited, the user needs to transmit the image data (photos) from the digital camera to his hard disk in order to empty the memory storage space for the next time. The process of transmitting the image data is as follows: first, the image data is converted into a differential signal 170 and the differential signal 170 is transmitted into the 1394 module 150 . Then the 1394 module 150 converts the differential signal 170 into a bus signal 120 and sends the bus signal 120 to the system bus 130 . The CPU sends a read/write request to the hard disk drive via the chipset (it is the south bridge in this case), and after the bus signal 120 is converted, the bus signal 120 is sent to the hard disk drive. Referring to FIG. 2 A, it illustrates a block diagram of the 1394 module 150 . The 1394 module 150 comprises a 1394 controller 210 and a 1394 physical layer 260 . The 1394 controller 210 is connected to the system bus 130 in order to transmit the bus signal 120 , and the 1394 physical layer is connected to the electronic device 190 in order to transmit the differential signal 170 . The differential signal 170 consists of a differential signal TPA and a differential signal TPB, and the differential signal TPA contains positive differential signal TPA&plus; and negative differential signal TPA−, the differential signal TPB contains positive differential signal TPB&plus; and negative differential signal TPB−. The transmission rate of the differential signal can be 100 Mbit/sec, 200 Mbit/sec or 400 Mbit/sec. The data signal DATA is a 8 bits two-way signal for sending data between the 1394 controller 210 and the 1394 physical layer 260 . The width of the data signal DATA is decided by the transmission rate of the packet, for example, when the transmission rate is 100 Mbit/sec, bit 0 and bit 1 of the data signal DATA is used for transmitting the data. When the transmission rate is 200 Mbit/sec, bit 0 to bit 3 of the data signal DATA is used for transmitting the data. When the transmission rate is 400 Mbit/sec, the bit 0 to bit 7 of the data signal DATA is used for transmitting the data. The 1394 controller can be, but not limited to, Geode CS4103 of National Semiconductor, TSB41LV02 of Texas Instruments, etc. The control signal CTRL is a 2 bits, two-way signal for assigning the type of communication such as idle, status, receive, and transmit between the 1394 controller 210 and the 1394 physical layer 260 . The link request signal LREQ, the link power status signal LPS and the clock signal CLK are all single bit, one-way signal. The link request signal LREQ is sent from the 1394 controller 210 to the 1394 physical layer 260 for accessing the internal registers of the 1394 physical layer 260 . The link power status signal LPS is sent from the 1394 controller 210 to the 1394 physical layer 260 for assigning the power status of the 1394 controller 210 . When the link power status signal LPS is at logic 0, it indicates that the 1394 controller 210 is not powered so it disables the control signal CTRL, data signal DATA, and the clock signal CLK. The frequency of the clock signal CLK is 49.152 MHZ and is sent from the 1394 physical layer 260 to the 1394 controller 210 . The clock signal CLK is for synchronizing the link request signal LREQ, the control signal CTRL, and the data signal DATA between the 1394 controller 210 and the 1394 physical layer 260 . Referring to FIG. 2 B, it illustrates a detailed block diagram of the 1394 controller and the 1394 physical layer. The 1394 controller 210 comprises a system bus interface 213 , a physical layer interface 215 , and a clock and power managing device 217 . The 1394 physical layer 260 comprises a link interface 265 , a phase lock loop (PLL) 267 and a transceiver 269 . The system bus interface 213 is connected to the system bus for transmitting the bus signal 120 . The physical layer interface 215 is connected to the link interface 213 for transmitting the data signal DATA, the control signal CTRL, and the link request signal LREQ. The clock/power control device 217 is connected to the phase lock loop 267 for transmitting the clock signal CLK and link power status signal LPS. The transceiver 269 is connected to the electronic device for transmitting the differential signal TPA and the differential signal TPB. The functions of each signal are described in the paragraph above and will not be stated again. While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiment. To the contrary, it is intended to cover various modifications and similar arrangements and procedures, and the scope of the appended claims therefore should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements and procedures.