Method of accessing data in storage device, method of managing data in storage device and storage device performing the same

A method of accessing data in a storage device including first and second nonvolatile memories of different types is provided. The method includes setting a meta data attribute table by classifying a plurality of meta data based on a plurality of data attributes and accessible memory types, detecting a data attribute of first meta data among the plurality of meta data based on the meta data attribute table in response to receiving a first access request for the first meta data, determining a target memory optimized for the first meta data from among the first and second nonvolatile memories based on the detected data attribute of the first meta data, and performing an access operation on the target memory based on the first meta data. The plurality of meta data are used for controlling an operation of the storage device.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2018-0092826, filed on Aug. 9, 2018 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated by reference in its entirety herein.

BACKGROUND

1. Technical Field

Exemplary embodiments relate generally to storage devices, and more particularly to methods of accessing and managing data in storage devices, and storage devices performing the methods.

2. Discussion of Related Art

Data storage devices may include one or more semiconductor memory devices. Examples of such data storage devices include solid state drives (SSDs). Solid state drives have various design and performance advantages over conventional hard disk drives (HDDs). Examples of these advantages include the absence of moving mechanical parts, higher data access speeds, improved stability and durability, and low power consumption. Solid state drives typically include nonvolatile memory devices such as flash memories. Recently, data storage devices having two or more different types of nonvolatile memory devices have been researched.

SUMMARY

At least one exemplary embodiment of the present inventive concept provides a method for efficiently accessing or managing meta data in a storage device that includes two or more different types of nonvolatile memories.

At least one exemplary embodiment of the present inventive concept provides a storage device performing the method for accessing or managing meta data.

According to an exemplary embodiment of the inventive concept, a method of accessing data in a storage device is provided. The storage device includes a first nonvolatile memory and a second nonvolatile memory that are different types of memories. The method includes setting a meta data attribute table by classifying a plurality of meta data based on a plurality of data attributes and accessible memory types, detecting a data attribute of first meta data among the plurality of meta data based on the meta data attribute table in response to receiving a first access request for the first meta data, determining a target memory optimized for the first meta data from among the first and second nonvolatile memories based on the detected data attribute of the first meta data, and performing an access operation on the target memory based on the first meta data. The plurality of meta data is used for controlling an operation of the storage device.

According to an exemplary embodiment of the inventive concept, a method of managing data in a storage device is provided. The storage device includes a first nonvolatile memory and a second nonvolatile memory that are different types of memories. The method includes generating a meta data attribute table including a plurality of entries, where each entry corresponds to one of a plurality of meta data used for controlling an operation of the storage; for each entry, selecting one of a plurality of data attributes that is appropriate for the meta data of the corresponding entry, and inserting the selected one data attribute into the corresponding entry; for each entry, selecting an optimized memory type from among the first and second nonvolatile memories based on the corresponding data attribute, and inserting the selected optimized memory type into the corresponding entry; and storing the meta data attribute table.

According to an exemplary embodiment of the inventive concept, a storage device including a first nonvolatile memory, a second nonvolatile memory, and a controller is provided. The first nonvolatile memory and the second nonvolatile memory are different types of memories. The controller controls an operation of the first nonvolatile memory and the second nonvolatile memory, sets a meta data attribute table by classifying a plurality of meta data based on a plurality of data attributes and accessible memory types, detects a data attribute of first meta data among the plurality of meta data based on the meta data attribute table in response to receiving a first access request for the first meta data, determines a target memory optimized for the first meta data from among the first and second nonvolatile memories based on the attribute of the first meta data, and performs an access operation on the target memory based on the first meta data. The plurality of meta data are used for controlling an operation of the storage device.

According to an exemplary embodiment of the inventive concept, a storage device including first and second nonvolatile memories and a controller is provided. The first nonvolatile memory and the second nonvolatile memory are different types of memories. The controller is configured to store a table comprising a plurality of entries, where each entry identifies one of a plurality of different data types and one of a plurality of different reliability types. The controller is configured to update each entry of the table to identify one of the first and second nonvolatile memories based on the corresponding data type and the corresponding reliability type. The controller is configured to receive a request including one of the plurality of data types, select one of the entries that match the included data type, and perform a command within the request on the memory identified by the selected entry.

The data attributes of the plurality of meta data may be checked, analyzed and classified in advance to set the meta data attribute table. When an access request for meta data is received, an optimized nonvolatile memory for the access-requested meta data may be determined based on the meta data attribute table and the data attribute of the access-requested meta data. Accordingly, the plurality of meta data may be efficiently managed and accessed with relatively high performance and reliability.

DETAILED DESCRIPTION OF THE EXEMPLARY EMBODIMENTS

The inventive concept will be described more fully with reference to the accompanying drawings, in which exemplary embodiments thereof are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Like reference numerals refer to like elements throughout this application.

FIG. 1is a flow chart illustrating a method of accessing data in a storage device according to an exemplary embodiment of the inventive concept.

Referring toFIG. 1, a method of accessing data according to an exemplary embodiment of the inventive concept is executed or performed by a storage device that includes a first nonvolatile memory and a second nonvolatile memory. The first and second nonvolatile memories are different types of memories. Detailed configurations of the storage device will be described with reference toFIGS. 2 through 4.

In the method of accessing data in the storage device according to an exemplary embodiment of the inventive concept, a meta data attribute table is set by classifying a plurality of meta data based on a plurality of data attributes and accessible memory types (step S100). The plurality of meta data are used for controlling an operation of the storage device. For example, the plurality of meta data may include at least one of register data and program sequence data that are generated and updated while firmware is executed. In an embodiment, the plurality of meta data additionally or alternately include at least one of address mapping data and bad block data, which are managed by a flash translation layer (FTL), a garbage collection operation and/or a wear leveling operation.

When an access request for one meta data of the plurality of meta data (e.g., a first access request for first meta data) is received, an attribute of the one meta data is detected based on the meta data attribute table (step S200) in response to receiving the access request for the one meta data. For example, the meta data attribute table may be searched based on information included in the first access request to detect an attribute of the first meta data. For example, the first access request may include an identifier that uniquely identifies one of the meta data listed in the meta data attribute table.

A target memory is determined based on the attribute of the access-requested meta data (e.g., the first meta data) (step S300). The target memory is optimized or best-fitted for the access-requested meta data and is one of the first nonvolatile memory and the second nonvolatile memory. For example, the meta data attribute table may be searched to determine a memory type optimized or best-fitted for the attribute of the first meta data. For example, the meta data attribute table may include an entry for each meta data of the plurality of meta data, where each entry indicates an attribute associated with the corresponding metadata and identifies one of the first and second nonvolatile memories (i.e., a target memory) in which data of the corresponding meta data is stored.

An access operation is performed on the target memory based on the access-requested meta data (e.g., the first meta data) (step S400). For example, the access operation may include at least one of read/program/erase operations for the first meta data.

In the method of accessing data in the storage device according to an exemplary embodiment of the inventive concept, the attributes of the plurality of meta data may be checked, analyzed and classified in advance to set the meta data attribute table. When an access request for meta data is received, an optimized nonvolatile memory for the access-requested meta data is determined based on the meta data attribute table and the attribute of the access-requested meta data. Accordingly, the plurality of meta data may be efficiently managed and accessed with relatively high performance and reliability.

FIG. 2is a block diagram illustrating a computing system including a storage device according to an exemplary embodiment of the inventive concept.

Referring toFIG. 2, a computing system10includes a host20(e.g., a host device) and a storage device100that communicates with the host20.

The host20may be driven by executing an operating system (OS). For example, the host20may include a memory storing the OS and a processor that executes the OS. The operating system may include a file system for file management and a device driver for controlling peripheral devices including the storage device100at the operating system level. The file system may manage at least one of file names, file extensions, file attributes, file sizes, and cluster information of files accessed by requests from the host20or applications executed by the host20. The file system may generate, delete and manage data on a file basis. The device driver may be a software module of a kernel for controlling the storage device100. The host20or the applications executed by the host20may request read/program/erase operations to the storage device100via the device driver. The host20may execute a plurality of applications that provide various services. For example, the host20may execute a video application, a game application, a web browser application, etc.

In some exemplary embodiments, the host20may be one of various electronic systems such as a personal computer, a laptop computer, a mobile phone, a smart phone, a tablet computer, a personal digital assistants (PDA), an enterprise digital assistant (EDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, a wearable device, an internet of things (IoT) device, an internet of everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, etc.

The storage device100includes a controller110(e.g., a control circuit), at least one first nonvolatile memory (NVM1)120and a plurality of second nonvolatile memories (NVM2)130. For example, the storage device100may be attached to the host20or inserted into the host20.

The controller110controls an operation of the nonvolatile memories120and130, e.g., read/program/erase operations, based on a command and data that are received from the host20.

The controller110may include a data distributor112. The data distributor112may execute or perform the method of accessing data described with reference toFIG. 1. In an embodiment, the data distributor112is implemented by a processor that executes the method. For example, the data distributor112sets a meta data attribute table114by classifying a plurality of meta data based on a plurality of data attributes and accessible memory types, detects an attribute of first meta data among the plurality of meta data based on the meta data attribute table114in response to receiving a first access request for the first meta data, determines a target memory optimized for the first meta data based on the attribute of the first meta data, and performs an access operation on the target memory based on the first meta data. The plurality of meta data are used for controlling an operation of the storage device100, and the target memory is one of the first nonvolatile memory120and the second nonvolatile memory130.

In an exemplary embodiment, as will be described with reference toFIGS. 6 and 7, the first access request for the first meta data is received from the host20that is located outside the storage device100. In another exemplary embodiment, as will be described with reference toFIGS. 8 and 9, the first access request for the first meta data is received from one of the first nonvolatile memory120and the second nonvolatile memory130that are located inside the storage device100.

In an exemplary embodiment, the meta data attribute table114is set and stored at an initial operation time, and the pre-stored meta data attribute table114is loaded or restored to use after the initial operation time. For example, the meta data attribute table114may be set and stored in advance at a design/development phase or a manufacturing phase of the storage device100. In an exemplary embodiment, the meta data attribute table114is set and stored whenever the storage device100is booted (e.g., powered on). For example, the meta data attribute table114may be stored in one of the nonvolatile memories120and130or in an additional memory (not shown) in the storage device100.

In an exemplary embodiment, if the meta data attribute table114is set and stored at the initial operation time and the pre-stored meta data attribute table114is loaded or restored to use after the initial operation time as described above, an operation of setting the meta data attribute table114(e.g., step S110inFIG. 1) is replaced with an operation of loading the pre-stored meta data attribute table114whenever the storage device100is booted.

In an exemplary embodiment, the meta data attribute table114is updated in real-time or during runtime according to an operation of the storage device100. For example, newly generated meta data and associated information may be added to the meta data attribute table114, and/or meta data that is no longer in use and associated information may be deleted from the meta data attribute table114.

As will be described with reference toFIG. 2, the data distributor112may execute or perform a method of managing data according to exemplary embodiments.

Although not illustrated inFIG. 2, the controller110may further include an element associated with the FTL, and/or elements for performing the garbage collection operation and/or the wear leveling operation.

In an exemplary embodiment of the inventive concept, the first nonvolatile memory120and the second nonvolatile memory130are different types of memories. For example, the first nonvolatile memory120may have relatively high operating speed and high endurance and may be used as a buffer memory or a cache memory. The second nonvolatile memory130may have relatively large storage capacity and may be used as a primary data storage medium. In an exemplary embodiment, a given one of the second memory devices130has a larger storage capacity and a lower access speed than the first nonvolatile memory120.

In an exemplary embodiment, the first nonvolatile memory120includes a phase change random access memory (PRAM), and the second nonvolatile memory130includes a flash memory. For example, the second nonvolatile memory130may include a NAND flash memory. In other exemplary embodiments, each of the first nonvolatile memory120and the second nonvolatile memory130may include any nonvolatile memory, e.g., a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a thyristor random access memory (TRAM), etc.

In some exemplary embodiments, the storage device100may be one of a solid state drive (SSD), a multi media card (MMC), an embedded multi media card (eMMC) and a universal flash storage (UFS). In other exemplary embodiments, the storage device100may be a secure digital (SD) card, a micro SD card, a memory stick, a chip card, a universal serial bus (USB) card, a smart card, or a compact flash (CF) card.

FIG. 3is a block diagram illustrating an example of a nonvolatile memory included in a storage device according to an exemplary embodiment of the inventive concept.

Referring toFIG. 3, a nonvolatile memory200includes a memory cell array210, a row decoder220(e.g., a row decoding circuit), a page buffer circuit230, a data input/output (I/O) circuit240, a voltage generator250and a control circuit260. The nonvolatile memory200may be one of the first nonvolatile memory120and the second nonvolatile memory130inFIG. 2.

The memory cell array210is connected to the row decoder220via a plurality of string selection lines SSL, a plurality of wordlines WL and a plurality of ground selection lines GSL. The memory cell array210is further connected to the page buffer circuit230via a plurality of bitlines BL. The memory cell array210may include a plurality of memory cells that are connected to the plurality of wordlines WL and the plurality of bitlines BL. The memory cell array210may be divided into a plurality of memory blocks BLK1, BLK2, . . . , BLKz, each of which includes some of the memory cells. For example, if the nonvolatile memory200is a flash memory, the plurality of memory cells may be flash memory cells (e.g., NAND flash memory cells). If the nonvolatile memory200is a PRAM, the plurality of memory cells may be PRAM cells.

In some exemplary embodiments, the memory cell array210is a two-dimensional memory cell array, which is formed on a substrate in a two-dimensional structure (or a planar structure). In other exemplary embodiments, the memory cell array210is a three-dimensional memory cell array, which is formed on a substrate in a three-dimensional structure (or a vertical structure). In an example where the memory cell array210has the three-dimensional structure, the memory cell array210includes a plurality of cell strings (e.g., a plurality of vertical cell strings) that are vertically oriented such that at least one memory cell is located over another memory cell.

A three-dimensional vertical array structure may include vertical cell strings that are vertically oriented such that at least one memory cell is located over another memory cell. The at least one memory cell may include a charge trap layer. The following patent documents, which are hereby incorporated by reference in their entirety, describe suitable configurations for a memory cell array including a 3D vertical array structure, in which the three-dimensional memory array is configured as a plurality of levels, with wordlines and/or bitlines shared between levels: U.S. Pat. Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and US Pat. Pub. No. 2011/0233648.

The control circuit260receives a command CMD and an address ADDR from a memory controller (e.g., the controller110inFIG. 2), and controls erasure, programming and read operations of the nonvolatile memory200based on the command CMD and the address ADDR. An erasure operation may include performing a sequence of erase loops, and a program operation may include performing a sequence of program loops. Each program loop may include a program operation and a program verification operation. The program verification operation may be used to verify whether data was successfully programmed using the program operation. Each erase loop may include an erase operation and an erase verification operation. The erase verification operation may be used to verify whether data was successfully deleted using the erase operation. The read operation may include a normal read operation and data recover read operation.

For example, the control circuit260may generate control signals CON, which are used for controlling the voltage generator250, may generate a control signal PBC for controlling the page buffer circuit230, based on the command CMD, and may generate a row address R_ADDR and a column address C_ADDR based on the address ADDR. The control circuit260may provide the row address R_ADDR to the row decoder220and may provide the column address C_ADDR to the data I/O circuit240. In an embodiment, the row address R_ADDR identifies one of the word lines WL and the column address C_ADDR identifies one of the bitlines BL.

The row decoder220may be connected to the memory cell array210via the plurality of string selection lines SSL, the plurality of wordlines WL and the plurality of ground selection lines GSL.

For example, in the data erase/program/read operations, the row decoder220may determine at least one of the plurality of wordlines WL as a selected wordline, and may determine the rest or remainder of the plurality of wordlines WL other than the selected wordline as unselected wordlines, based on the row address R_ADDR.

In addition, in the data erase/program/read operations, the row decoder220may determine at least one of the plurality of string selection lines SSL as a selected string selection line, and may determine the rest or remainder of the plurality of string selection lines SSL other than the selected string selection line as unselected string selection lines, based on the row address R_ADDR.

Further, in the data erase/program/read operations, the row decoder220may determine at least one of the plurality of ground selection lines GSL as a selected ground selection line, and may determine the rest or remainder of the plurality of ground selection lines GSL other than the selected ground selection line as unselected ground selection lines, based on the row address R_ADDR.

The voltage generator250may generate gate voltages VG that are required for an operation of the nonvolatile memory200based on a power PWR and the control signals CON. The gate voltages VG may be applied to the plurality of wordlines WL, the plurality of string selection lines SSL and the plurality of ground selection lines GSL via the row decoder220. In addition, the voltage generator250may generate an erase voltage that is required for the data erase operation based on the power PWR and the control signals CON.

For example, during the erase operation, the voltage generator250may apply the erase voltage to a common source line and/or the bitlines BL of a memory block and may apply an erase permission voltage (e.g., a ground voltage) to all wordlines of the memory block or a portion of the wordlines via the row decoder220. In addition, during the erase verification operation, the voltage generator250may apply an erase verification voltage simultaneously to all wordlines of the memory block or sequentially to the wordlines one by one.

For example, during the program operation, the voltage generator250may apply a program voltage to the selected wordline and may apply a program pass voltage to the unselected wordlines via the row decoder220. In an embodiment, a level of the program voltage differs from a level of the program pass voltage. In addition, during the program verification operation, the voltage generator250may apply a program verification voltage to the selected wordline and may apply a verification pass voltage to the unselected wordlines via the row decoder220. In an embodiment, a level of the program verification voltage differs from a level of the verification pass voltage.

In addition, during the normal read operation, the voltage generator250may apply a read voltage to the selected wordline and may apply a read pass voltage to the unselected wordlines via the row decoder220. In an embodiment, a level of the read voltage differs from a level of the read pass voltage. During the data recover read operation, the voltage generator250may apply the read voltage to a wordline adjacent to the selected wordline and may apply a recover read voltage to the selected wordline via the row decoder220. In an embodiment, a level of the read voltage differs from a level of the recover read voltage.

The page buffer circuit230may be connected to the memory cell array210via the plurality of bitlines BL. The page buffer circuit230may include a plurality of page buffers. In some exemplary embodiments, each page buffer is connected to one bitline. In other exemplary embodiments, each page buffer is connected to two or more bitlines.

The page buffer circuit230may store data DAT to be programmed into the memory cell array210or may read data DAT sensed from the memory cell array210. In other words, the page buffer circuit230may operate as a write driver or a sensing amplifier according to an operation mode of the nonvolatile memory device200.

The data I/O circuit240may be connected to the page buffer circuit230via data lines DL. The data I/O circuit240may provide the data DAT from an outside of the nonvolatile memory200(e.g., from the controller110inFIG. 2) to the memory cell array210via the page buffer circuit230or may provide the data DAT from the memory cell array210to the outside of the nonvolatile memory200, based on the column address C_ADDR.

FIG. 4is a block diagram illustrating an example of a controller (e.g., a control circuit) included in a storage device according to exemplary embodiment of the inventive concept.

Referring toFIG. 4, a controller300includes at least one processor310, a data distributor320, a buffer memory330, a host interface340and a memory interface350. For example, the controller110ofFIG. 2may be implemented by controller300.

The processor310may control an operation of the controller300in response to a command received via the host interface340from a host (e.g., the host20inFIG. 2). In some exemplary embodiments, the processor310controls respective components by employing firmware for operating the storage device100.

The buffer memory330may store instructions and data executed and processed by the processor310. For example, the buffer memory330may be implemented with a volatile memory device, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM). In an exemplary embodiment, the buffer memory330is a cache memory for the processor310.

The data distributor320sets and stores a meta data attribute table322, and determines an optimized nonvolatile memory for meta data based on an attribute of the meta data when an access request for the meta data is received. The data distributor320and the meta data attribute table322may be substantially the same as the data distributor112and the meta data attribute table114inFIG. 2, respectively.

In some exemplary embodiments, at least a part of the data distributor320is implemented by hardware. For example, the data distributor320may be a part of the processor310or an additional processing unit for performing a data processing operation, and the meta data attribute table322may be stored in the buffer memory330. In other exemplary embodiments, at least a part of the data distributor320is implemented as software (e.g., a software program). For example, the data distributor320may include instruction codes and/or program routines that are executed by the processor310and are stored in the buffer memory330. In an embodiment, the data distributor320is a dedicated memory storing the instruction codes and/or program codes that are executed by the processor310.

The host interface340may provide physical connections between the host and the storage device100. The host interface340may provide an interface corresponding to a bus format of the host for communication between the host and the storage device100. In some exemplary embodiments, the bus format of the host may be a small computer system interface (SCSI) or a serial attached SCSI (SAS) interface. In other exemplary embodiments, the bus format of the host may be a USB, a peripheral component interconnect (PCI) express (PCIe), an advanced technology attachment (ATA), a parallel ATA (PATA), a serial ATA (SATA), or a nonvolatile memory (NVM) express (NVMe) format.

The memory interface350may exchange data with the nonvolatile memory (e.g., the first nonvolatile memory120or the second nonvolatile memory130inFIG. 2). The memory interface350may transfer data to the nonvolatile memory, or may receive data read from the nonvolatile memory. In some exemplary embodiments, the memory interface350is connected to the at least one nonvolatile memory via one channel. In other exemplary embodiments, the memory interface350is connected to the at least one nonvolatile memory via two or more channels.

Although not illustrated inFIG. 4, the controller300may further include an error correction code (ECC) block (e.g., an error correction circuit). The ECC block for error correction may perform coded modulation using a Bose-Chaudhuri-Hocquenghem (BCH) code, a low density parity check (LDPC) code, a turbo code, a Reed-Solomon code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), or a block coded modulation (BCM), or may perform ECC encoding and ECC decoding using the above-described codes or other error correction codes.

FIG. 5is a diagram illustrating an example of a meta data attribute table included in a storage device and used in a method of accessing data according to an exemplary embodiment of the inventive concept.

Referring toFIG. 5, a meta data attribute table MDA_TABLE includes a plurality of meta data MDAT1, MDAT2, MDAT3, MDAT4, . . . , a plurality of data attributes ATTR1, ATTR2, ATTR3, ATTR4, . . . , and an access allowed memory (e.g., an accessible memory type or an optimized memory type) for each meta data. The meta data attribute table114may be implemented by the meta data attribute table MDA_TABLE. Relationships of the plurality of meta data, the plurality of data attributes and the optimized memory type may be arranged as a table (e.g., the meta data attribute table MDA_TABLE). For example, each entry of the meta data attribute table MDA_TABLE may identify one of the plurality of meta data, one of the data attributes, and one of two different types of nonvolatile memories to access.

In some exemplary embodiments, the plurality of data attributes include at least one of a first data attribute ATTR1, a second data attribute ATTR2, a third data attribute ATTR3and a fourth data attribute ATTR4. The first data attribute ATTR1may represent reliability for program/erase (P/E) cycles. For example, different types of memory can withstand a different number of P/E cycles before leading to a failure. The second data attribute ATTR2may represent reliability for temperature. For example, a memory may have trouble retaining data when operating beyond a certain temperature, where that certain temperature varies according to the type of memory used. The third data attribute ATTR3may represent reliability for data retention. The fourth data attribute ATTR4may represent reliability for read disturbance. For example, reading a cell in a given memory can cause a nearby cell to change its value, and the likelihood of this occurring may vary according to the type of memory used.

In other exemplary embodiments, the plurality of data attributes further include at least one of other key parameters, such as performance. For example, the performance may include a read delay time (e.g., tR) representing a time to transfer data in a memory cell array to an output buffer, a program delay time (e.g., tPROG) representing a time to write data in an input buffer to a memory cell array, etc.

In some exemplary embodiments, when setting the meta data attribute table MDA_TABLE (e.g., step S100inFIG. 1), the plurality of meta data MDAT1, MDAT2, MDAT3and MDAT4is listed, each of the plurality of meta data MDAT1, MDAT2, MDAT3and MDAT4is matched with a respective one of the plurality of data attributes ATTR1, ATTR2, ATTR3and ATTR4, an optimized memory type for each of the plurality of meta data MDAT1, MDAT2, MDAT3and MDAT4is set to one of the first nonvolatile memory NVM1and the second nonvolatile memory NVM2based on the plurality of data attributes ATTR1, ATTR2, ATTR3and ATTR4, and the meta data attribute table MDA_TABLE is stored based on relationships of the plurality of meta data MDAT1, MDAT2, MDAT3and MDAT4, the plurality of data attributes ATTR1, ATTR2, ATTR3and ATTR4, and the optimized memory types NVM1and NVM2.

In an example ofFIG. 5, the first meta data MDAT1has the first data attribute ATTR1, and an optimized memory type for the first meta data MDAT1is set to the first nonvolatile memory NVM1. Similarly, the second meta data MDAT2has the second data attribute ATTR2, and an optimized memory type for the second meta data MDAT2is set to the second nonvolatile memory NVM2. The third meta data MDAT3may has the third data attribute ATTR3, and an optimized memory type for the third meta data MDAT3is set to the second nonvolatile memory NVM2. The fourth meta data MDAT4has the fourth data attribute ATTR4, and an optimized memory type for the fourth meta data MDAT4is set to the first nonvolatile memory NVM1.

FIG. 6is a flow chart illustrating a method of accessing data according to an exemplary embodiment of the inventive concept.FIG. 7is a diagram for describing an operation of accessing data ofFIG. 6.

Referring toFIGS. 1, 5, 6 and 7, to execute or perform the method of accessing data according to an exemplary embodiments, the meta data attribute table (e.g., the meta data attribute table MDA_TABLE inFIG. 5or the meta data attribute table114inFIG. 7) is classified, set and stored in advance in step S100, and may be recognized by firmware that is executed by the controller110and/or the data distributor112.

When detecting the attribute of the meta data (step S200), the controller110and/or the data distributor112may receive a first access request REQ1for the first meta data MDAT1, and the attribute of the first meta data MDAT1may be detected based on the meta data attribute table MDA_TABLE in response to receiving the first access request REQ1. For example, the first access request REQ1may include the first meta data MDAT1, a first command CMD1, a first address ADDR1and first information INFL The first command CMD1and the first address ADDR1may be associated with the first access request REQ1, and the first information INF1may be associated with the first meta data MDAT1. The meta data attribute table MDA_TABLE may be searched based on the first meta data MDAT1or the first information INF1included in the first access request REQ1to detect the attribute of the first meta data MDAT1.

In an exemplary embodiment, as illustrated inFIG. 5, the attribute of the first meta data MDAT1is the first data attribute ATTR1representing reliability for P/E cycles. For example, if the first meta data MDAT1is security data that is used in a secure mode and requires a P/E operation to be executed a number of times greater than a reference number, the attribute of the first meta data MDAT1may correspond to the first data attribute ATTR1. In addition, if the first meta data MDAT1is the security data, the first access request REQ1for the first meta data MDAT1may be provided from the external host20. For example, the security data could be a login identifier (ID) of a user or a password of the user, where it is desirable to have such data stored in a memory device capable of withstanding a certain minimum number of P/E cycles.

When determining the target memory (step S300), when the attribute of the first meta data MDAT1corresponds to the first data attribute ATTR1representing reliability for P/E cycles (step S310: YES), the first nonvolatile memory120may be selected as the target memory (step S350). The first nonvolatile memory120may have reliability for P/E cycles (e.g., durability) higher than that of the second nonvolatile memory130. For example, the first nonvolatile memory120may include a PRAM.

When performing the access operation on the target memory (step S400), at least one of read/program/erase operations may be performed on the first nonvolatile memory120(step S410). For example, if the first command CMD1included in the first access request REQ1is a write command, the first meta data MDAT1is programmed or stored in the first nonvolatile memory120based on the first address ADDR1. For example, the first meta data MDAT1may be stored in a location of the first nonvolatile memory120associated with the first address ADDR1. If the first command CMD1included in the first access request REQ1is a read command, the first meta data MDAT1is retrieved or read from the first nonvolatile memory120based on the first address ADDR1. For example, the first meta data MDAT1may be read from a location of the first nonvolatile memory120associated with the first address ADDR1. If the first command CMD1included in the first access request REQ1is an erase command, the first meta data MDAT1is erased or deleted from the first nonvolatile memory120based on the first address ADDR1. For example, the first meta data MDAT1may be deleted from a location of the first nonvolatile memory120associated with the first address ADDR1.

When the attribute of the first meta data MDAT1does not correspond to the first data attribute ATTR1representing reliability for P/E cycles (step S310: NO), steps S350and S410are not performed, and an operation of searching the meta data attribute table MDA_TABLE may be repeated until the attribute of the first meta data MDAT1is detected.

FIG. 8is a flow chart illustrating a method of accessing data according to an exemplary embodiment of the inventive concept.FIG. 9is a diagram for describing an operation of accessing data ofFIG. 8. The descriptions repeated withFIGS. 6 and 7may be omitted.

Referring toFIGS. 1, 5, 8 and 9, when detecting the attribute of the meta data (step S200), the controller110and/or the data distributor112may receive a second access request REQ2for the second meta data MDAT2, and the attribute of the second meta data MDAT2may be detected based on the meta data attribute table MDA_TABLE in response to receiving the second access request REQ2. As with the first access request REQ1, the second access request REQ2may include the second meta data MDAT2, a second command CMD2, a second address ADDR2and second information INF2. The meta data attribute table MDA_TABLE may be searched based on the second meta data MDAT2or the second information INF2included in the second access request REQ2to detect the attribute of the second meta data MDAT2.

In an exemplary embodiment, as illustrated inFIG. 5, the attribute of the second meta data MDAT2is the second data attribute ATTR2representing reliability for temperature. For example, if the second meta data MDAT2is debugging data that is used in a high temperature environment having a temperature higher than a reference temperature, the attribute of the second meta data MDAT2corresponds to the second data attribute ATTR2. In addition, if the second meta data MDAT2is the debugging data, the second access request REQ2for the second meta data MDAT2may be provided from an internal memory (e.g., the second nonvolatile memory130).

Typically, the debugging data may be used for analyzing defective units when the defective units are recalled from customers and/or end users after a plurality of storage devices100have completely fabricated and shipped. To analyze the defective units, the storage device100and/or the nonvolatile memories120and130that are attached on a printed circuit board (PCB) should be detached from the PCB by heat, and thus the debugging data needs to be stored in a memory having higher reliability for temperature.

When determining the target memory (step S300), when the attribute of the second meta data MDAT2corresponds to the second data attribute ATTR2representing reliability for temperature (step S320: YES), the second nonvolatile memory130may be selected as the target memory (step S360). The second nonvolatile memory130may have reliability for temperature (e.g., strong against high temperature) higher than that of the first nonvolatile memory120. For example, the first nonvolatile memory120may include a PRAM, and the second nonvolatile memory130may include a flash memory. Data stored in a PRAM may be overwritten and damaged when memory cells of a PRAM is heated, and thus a PRAM may have lower reliability for temperature.

When performing the access operation on the target memory (step S400), at least one of read/program/erase operations may be performed on the second nonvolatile memory130(step S420). For example, if the second command CMD2included in the second access request REQ2is a write command, the second meta data MDAT2may be programmed or stored in the second nonvolatile memory130based on the second address ADDR2. If the second command CMD2included in the second access request REQ2is a read command, the second meta data MDAT2may be retrieved or read from the second nonvolatile memory130based on the second address ADDR2. If the second command CMD2included in the second access request REQ2is an erase command, the second meta data MDAT2may be erased or deleted from the second nonvolatile memory130based on the second address ADDR2.

When the attribute of the second meta data MDAT2does not correspond to the second data attribute ATTR2representing reliability for temperature (step S320: NO), steps S360and S420are not performed, and an operation of searching the meta data attribute table MDA_TABLE may be repeated until the attribute of the second meta data MDAT2is detected.

FIGS. 10 and 11are flow charts illustrating a method of accessing data according to an exemplary embodiment of the inventive concept. The descriptions repeated withFIGS. 6 through 9may be omitted.

Referring toFIGS. 1, 5 and 10, when detecting the attribute of the meta data (step S200), the controller110and/or the data distributor112may receive a third access request for the third meta data MDAT3, and the attribute of the third meta data MDAT3may be detected based on the meta data attribute table MDA_TABLE in response to receiving the third access request.

In an exemplary embodiment, as illustrated inFIG. 5, the attribute of the third meta data MDAT3is the third data attribute ATTR3representing reliability for data retention. For example, if the third meta data MDAT3is firmware data that requires a retention time longer than a reference time, the attribute of the third meta data MDAT3corresponds to the third data attribute ATTR3. In addition, as with an example illustrated inFIG. 7, if the third meta data MDAT3is the firmware data, the third access request for the third meta data MDAT3may be provided from the external host20.

When determining the target memory (step S300), when the attribute of the third meta data MDAT3corresponds to the third data attribute ATTR3representing reliability for data retention (step S330: YES), the second nonvolatile memory130may be selected as the target memory (step S360). The second nonvolatile memory130may have reliability for data retention higher than that of the first nonvolatile memory120. For example, the second nonvolatile memory130may include a flash memory. In addition, when performing the access operation on the target memory (step S400), at least one of read/program/erase operations may be performed on the second nonvolatile memory130(step S420). Steps S360and S420inFIG. 10may be substantially the same as steps S360and S420inFIG. 8, respectively.

When the attribute of the third meta data MDAT3does not correspond to the third data attribute ATTR3representing reliability for data retention (step S330: NO), steps S360and S420are not performed, and an operation of searching the meta data attribute table MDA_TABLE may be repeated until the attribute of the third meta data MDAT3is detected.

Referring toFIGS. 1, 5 and 11, when detecting the attribute of the meta data (step S200), the controller110and/or the data distributor112may receive a fourth access request for the fourth meta data MDAT4, and the attribute of the fourth meta data MDAT4may be detected based on the meta data attribute table MDA_TABLE in response to receiving the fourth access request.

In an exemplary embodiment, as illustrated inFIG. 5, the attribute of the fourth meta data MDAT4is the fourth data attribute ATTR4representing reliability for read disturbance. For example, if the fourth meta data MDAT4is data that requires a read operation to be executed a number of times greater than a reference number, the attribute of the fourth meta data MDAT4may correspond to the fourth data attribute ATTR4. In addition, as with an example illustrated inFIG. 7, if the fourth meta data MDAT4is the data that requires a read operation to be executed a number of times greater than the reference number, the fourth access request for the fourth meta data MDAT4may be provided from the external host20.

When determining the target memory (step S300), when the attribute of the fourth meta data MDAT4corresponds to the fourth data attribute ATTR4representing reliability for read disturbance (step S340: YES), the first nonvolatile memory120may be selected as the target memory (step S350). The first nonvolatile memory120may have reliability for read disturbance higher than that of the second nonvolatile memory130. For example, the first nonvolatile memory120may include a PRAM. In addition, when performing the access operation on the target memory (step S400), at least one of read/program/erase operations may be performed on the first nonvolatile memory120(step S410). Steps S350and S410inFIG. 11may be substantially the same as steps S350and S410inFIG. 6, respectively.

When the attribute of the fourth meta data MDAT4does not correspond to the fourth data attribute ATTR4representing reliability for read disturbance (step S340: NO), steps S350and5410are not performed, and an operation of searching the meta data attribute table MDA_TABLE may be repeated until the attribute of the fourth meta data MDAT4is detected.

Examples of selecting the target memory optimized for the meta data are not limited to examples described with referenceFIGS. 6, 8, 10 and 11and may be changed according to exemplary embodiments. For example, the target memory optimized for the meta data may be selected by determining whether the attribute of the meta data corresponds to two or more data attributes. In other words, the target memory optimized for the meta data may be selected by combining two or more steps5310inFIG. 6, S320inFIG. 8, S330inFIGS. 10and S340inFIG. 11. For another example, the target memory optimized for the meta data may be selected by determining whether the attribute of the meta data corresponds to other various attributes (e.g., other key parameters such as performance).

FIG. 12is a flow chart illustrating a method of managing data in a storage device according to an exemplary embodiment of the inventive concept. The descriptions repeated withFIG. 1may be omitted.

Referring toFIG. 12, a method of managing data according to an exemplary embodiment is executed or performed by a storage device that includes a first nonvolatile memory and a second nonvolatile memory. The first and second nonvolatile memories are different types of memories. Detailed configurations of the storage device may be substantially the same as the storage device100described with reference toFIGS. 2 through 4.

In the method of managing data in the storage device according to an exemplary embodiment, a plurality of meta data used for controlling an operation of the storage device are listed (step S500). Each of the plurality of meta data is matched with a respective one of a plurality of data attributes (step S600). An optimized memory type for each of the plurality of meta data is set to one of the first nonvolatile memory and the second nonvolatile memory based on the plurality of data attributes (step S700). A meta data attribute table is stored based on relationships of the plurality of meta data, the plurality of data attributes and the optimized memory type (step S800). For example, steps S500, S600, S700and S800may be executed or performed by the controller110and/or the data distributor112inFIG. 2, and the meta data attribute table MDA_TABLE inFIG. 5may be set as a result of steps S500, S600, S700and S800.

In an exemplary embodiment, the meta data attribute table is set and stored at an initial operation time (e.g., in advance at a design/development phase, a manufacturing phase or a boot time), and the pre-stored meta data attribute table is loaded or restored to use after the initial operation time. In addition, the meta data attribute table may be updated in real-time or during runtime according to an operation of the storage device.

In an exemplary embodiment, steps S500, S600, S700and S800are executed or performed as a part of step S100inFIG. 1. In other words, an operation of setting the meta data attribute table in step S100ofFIG. 1may be executed or performed by sequentially executing or performing steps S500, S600, S700and S800.

FIG. 13is a diagram for describing a method of accessing data according to an exemplary embodiment of the inventive concept.

Referring toFIGS. 5 and 13, the nonvolatile memories NVM1and NVM2may be accessed through a volume interface including various volumes and a memory interface, and the target memory may be determined or selected and may be accessed based on the meta data attribute table MDA_TABLE.

For example, meta data (e.g., the first meta data MDAT1) which is the security data or has a security volume may be accessed from the first nonvolatile memory NVM1through a first nonvolatile memory interface. Meta data (e.g., the second meta data MDAT2) which is the debugging data or has a debug volume, and meta data (e.g., the third meta data MDAT3) which is the firmware data or has a firmware (F/W) volume may be accessed from the second nonvolatile memory NVM2through a second nonvolatile memory interface. Data other than the meta data and user data which has a user volume may be accessed from the second nonvolatile memory NVM2through the second nonvolatile memory interface, without considering the meta data attribute table MDA_TABLE.

Although exemplary embodiments are described based on the storage device100including two different types of nonvolatile memories120and130, the inventive concept is not limited thereto. For example, the storage device may include three of more different types of nonvolatile memories, and an optimized nonvolatile memory for each meta data may be determined from one of three of more different types of nonvolatile memories based on an attribute of the meta data.

As will be appreciated by those skilled in the art, the inventive concept may be embodied as a system, method, computer program product, and/or a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon. The computer readable program code may be provided to a processor of a general purpose computer, a special purpose computer, or other programmable data processing apparatus. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. For example, the computer readable medium may be a non-transitory computer readable medium.

FIG. 14is a block diagram illustrating a mobile device including a storage device according to an exemplary embodiment of the inventive concept.

Referring toFIG. 14, a mobile device1000includes an application processor1100, a communication module1200(e.g., a transceiver), a display/touch module1300, a storage device1400, and a buffer RAM1500.

The application processor1100controls operations of the mobile device1000. The application processor1100may execute an application or a program such as a video, a game, a web browser, etc. The communication module1200is implemented to perform wireless or wire communications with an external device. The display/touch module1300is implemented to display data processed by the application processor1100and/or to receive data through a touch panel. The storage device1400is implemented to store user data.

The storage device1400may be implemented by the storage device100according to an exemplary embodiment, and may perform one of the above-described methods of accessing data according to an exemplary embodiment of the inventive concept. For example, the attributes of the plurality of meta data may be checked, analyzed and classified in advance to set the meta data attribute table. When an access request for meta data is received, an optimized nonvolatile memory for the access-requested meta data may be determined based on the meta data attribute table and the attribute of the access-requested meta data. Accordingly, the plurality of meta data may be efficiently managed and accessed with relatively high performance and reliability.

The buffer RAM1500temporarily stores data used for processing operations of the mobile device1000. For example, the buffer RAM1500may be DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, or RDRAM.

The inventive concept may be applied to various devices and systems that include a storage device. For example, the inventive concept may be applied to systems such as a personal computer, a laptop computer, a mobile phone, a smart phone, a tablet computer, a laptop computer, a PDA, an EDA, a PMP, a digital camera, a music player, a portable game console, a navigation device, a wearable device, an IoT device, an IoE device, a VR device, or an AR device.

The foregoing is illustrative of exemplary embodiments of the inventive concept and is not to be construed as limiting thereof. Although some exemplary embodiments have been described, many modifications are possible in these exemplary embodiments without materially departing from the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept.