Semiconductor devices having through-electrodes and methods for fabricating the same

The present inventive concepts provide semiconductor devices and methods for fabricating the same. The method includes forming an inter-metal dielectric layer including a plurality of dielectric layers on a substrate, forming a via-hole vertically penetrating the inter-metal dielectric layer and the substrate, providing carbon to at least one surface, such as a surface including carbon in the plurality of dielectric layers exposed by the via-hole, forming a via-dielectric layer covering an inner surface of the via-hole, and forming a through-electrode surrounded by the via-dielectric layer in the via-hole.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit of and priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2013-0147475, filed on Nov. 29, 2013, the disclosure of which is hereby incorporated herein by reference in its entirety.

BACKGROUND

The present inventive concepts relate to a semiconductor and, more particularly, to semiconductor devices having through-electrodes and methods for fabricating the same.

Through-electrodes penetrating a substrate may be used to electrically connect a semiconductor device to another semiconductor device or a printed circuit board. Through-electrodes may be used for a three-dimensional mounting technique and may provide a faster data transmitting speed as compared with conventional solder balls or solder bumps. New formation processes and new structures for through-electrodes may be desired to improve electrical characteristics of semiconductor devices.

SUMMARY

Embodiments of the present inventive concepts may provide semiconductor devices capable of preventing through-electrodes from being damaged by formation processes of the through-electrodes and methods for fabricating the same.

In some embodiments, the method may include: forming an inter-metal dielectric layer including a plurality of dielectric layers on a substrate; forming a via-hole vertically penetrating the inter-metal dielectric layer and the substrate; providing carbon to at least one surface exposed by the via-hole; forming a via-dielectric layer covering an inner surface of the via-hole; and forming a through-electrode surrounded by the via-dielectric layer in the via-hole. In some embodiments, the at least one surface includes a surface of a layer of the plurality of dielectric layers including carbon.

In some embodiments, forming the inter-metal dielectric layer may include alternately stacking a capping layer and a low-k dielectric layer on the substrate. The low-k dielectric layer may have a dielectric constant lower than that of silicon dioxide. In some embodiments, the inter-metal dielectric layer may include a plurality of alternately stacked capping layers and low-k dielectric layers.

In some embodiments, the capping layers may include SiCN, and the low-k dielectric layers may include SiCOH.

In some embodiments, providing carbon to at least one surface may include substituting Si—OH bonds in the low-k dielectric layers with Si—CH3bonds by providing surfaces of the low-k dielectric layers with a gas including carbon and optionally at least one of silicon (Si), hydrogen (H), oxygen (O) and nitrogen (N).

In some embodiments, providing carbon to at least one surface may include hydrophobically treating surfaces of the low-k dielectric layers by providing the surfaces of the low-k dielectric layers with a gas including carbon and optionally at least one of silicon (Si), hydrogen (H), oxygen (O) and nitrogen (N).

In some embodiments, providing carbon to at least one surface may include hydrophobically treating a surface of the substrate exposed through the via-hole.

In some embodiments, forming the via-hole may include forming a mask layer on the inter-metal dielectric layer; patterning the inter-metal dielectric layer and the substrate to form the via-hole by an etching process using the mask layer as an etch mask; and removing the mask layer by an ashing process using a gas including CO, CO2, N2/H2, O2, or any combination thereof at a temperature of about 200° C. or less.

In some embodiments, providing carbon to at least one surface may include hydrophobically treating an inner surface of the via-hole by providing the via-hole with a gas including carbon and optionally at least one of silicon (Si), hydrogen (H), oxygen (O) and nitrogen (N).

In some embodiments, forming the via-hole may include forming a vertical hole completely penetrating the inter-metal dielectric layer and partially penetrating the substrate by an etching process.

In some embodiments, the method may further include before and/or after providing carbon to at least one surface, providing the via-hole with diluted hydrofluoric acid (DHF) to hydrophobically treat a surface of the substrate exposed through the via-hole.

In another aspect, the semiconductor device may include a semiconductor substrate on which an integrated circuit is disposed; an inter-metal dielectric layer provided on the semiconductor substrate, the inter-metal dielectric layer including at least one metal interconnection electrically connected to the integrated circuit; and a through-electrode vertically penetrating the inter-metal dielectric layer and the semiconductor substrate. The inter-metal dielectric layer may include a carbon-containing low-k dielectric layer having a dielectric constant lower than that of silicon dioxide. The low-k dielectric layer may include a surface adjacent to the through-electrode; and a bulk distal to the through-electrode in a horizontal direction. A carbon concentration of the low-k dielectric layer may become reduced and then increased from the surface of the low-k dielectric layer toward the bulk of the low-k dielectric layer.

In some embodiments, the carbon concentration of the low-k dielectric layer may include a first concentration at the surface of the low-k dielectric layer; a second concentration in a surface-nearby region adjacent to the surface of the low-k dielectric layer, the second concentration lower than the first concentration; and a third concentration in the bulk, the third concentration higher than the second concentration.

In some embodiments, the first concentration may be equal to or higher than the third concentration.

In some embodiments, the inter-metal dielectric layer may further include an insulating capping layer covering the low-k dielectric layer.

In some embodiments, the low-k dielectric layer may include SiCOH, and the insulating capping layer may include SiCN.

In some embodiments, a method may be provided, the method including providing a semiconductor substrate including at least one dielectric layer and a via-hole vertically penetrating the at least one dielectric layer and the semiconductor substrate, the at least one dielectric layer having a first portion exposed by the via-hole with a first concentration of carbon and a second portion with a second concentration of carbon, wherein the first concentration is less than the second concentration; and adding carbon to at least the first portion of the at least one dielectric layer. In some embodiments, the method may be a method for fabricating a semiconductor device.

In some embodiments, the at least one dielectric layer may be a low-k dielectric layer, such as an ultra low-k dielectric layer. In some embodiments, the first portion may be a surface region of the at least one dielectric layer that may be adjacent to a through-electrode, and the second portion may include an end region of the at least one dielectric layer that is opposite the first portion.

In some embodiments, adding carbon to at least the first portion of the at least one dielectric layer includes converting a hydrophilic property in the first portion to a hydrophobic property. Some embodiments provide that the hydrophilic property includes a SiOH bond and that the hydrophobic property includes a Si—CH3bond.

In some embodiments, adding carbon to at least the first portion of the at least one dielectric layer includes contacting a gas to at least the first portion of the at least one dielectric layer, the gas including carbon and optionally silicon, hydrogen, oxygen, and/or nitrogen.

In some embodiments, adding carbon to at least the first portion of the at least one dielectric layer is carried out at a temperature in a range of about 200° C. to about 500° C. in an oxidation or inert atmosphere.

DETAILED DESCRIPTION OF EMBODIMENTS

Example embodiments are described below with reference to the accompanying drawings. Many different forms and embodiments are possible without deviating from the spirit and teachings of this disclosure and so the disclosure should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will convey the scope of the disclosure to those skilled in the art. In the drawings, the sizes and relative sizes of layers and regions may be exaggerated for clarity. Like reference numbers refer to like elements throughout the description.

It will be understood that when an element is referred to as being “coupled,” “connected,” or “on,” another element, it can be directly coupled, connected, or on, the other element, or intervening elements may also be present. In contrast, when an element is referred to as being “directly coupled,” “directly connected,” or “directly on,” another element, there are no intervening elements present. As used herein the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a “first” element could be termed a “second” element without departing from the teachings of the present embodiments.

FIGS. 1A to 1Hare cross-sectional views illustrating a method for fabricating a semiconductor device according to some embodiments of the present inventive concepts.FIG. 2Ais a cross-sectional view illustrating a portion ofFIG. 1Baccording to some embodiments of the present inventive concepts.FIG. 2Bis a schematic diagram illustrating bonding states of a surface region of a general low-k dielectric layer according to some embodiments of the present inventive concepts.FIG. 2Cis a schematic diagram illustrating bonding states of a surface region of a low-k dielectric layer in which a carbon loss has occurred according to some embodiments of the present inventive concepts.FIG. 2Dis a schematic diagram illustrating bonding states of a surface region of a low-k dielectric layer that has been supplemented with carbon by a recovery process according to some embodiments of the present inventive concepts.

Referring toFIG. 1A, a semiconductor substrate100may be provided which has a top surface100aand a bottom surface100b. An interlayer dielectric (ILD) layer110including an integrated circuit111, and an inter-metal dielectric (IMD) layer120including a metal interconnection125may be sequentially formed on the top surface100aof the substrate100. An upper dielectric layer130may be further formed on the inter-metal dielectric layer120. The upper dielectric layer130may cover the inter-metal dielectric layer120. The semiconductor substrate100may be a wafer including a semiconductor such as silicon. The integrated circuit111may include a memory circuit, a logic circuit, or a combination thereof. At least one of the interlayer dielectric layer110and the upper dielectric layer130may include a silicon oxide layer or a silicon nitride layer. For example, at least one of the interlayer dielectric layer110and the upper dielectric layer130may include a tetraethylorthosilicate (TEOS) oxide layer formed by a chemical vapor deposition (CVD) process.

The inter-metal dielectric layer120may include a low-k dielectric having a dielectric constant lower than that of silicon dioxide (SiO2). In some embodiments, the low-k dielectric may be an ultra low-k dielectric. For example, the inter-metal dielectric layer120may include a silicon-based polymeric dielectric (e.g., fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, hydrogen silsesquioxane (HSG), or methylsilsesquioxane (MSG)), an organic polymeric dielectric (e.g., polyimide), SiCOH, SiLK™ from Dow Chemical Company, or AURORA™ from ASM International Company. The inter-metal dielectric layer120is not limited to the materials described above. In some embodiments, the inter-metal dielectric layer120may include any dielectric having a dielectric constant in a range of about 1.8 to about 3.5.

The metal interconnection125may have a multi-layered structure and the inter-metal dielectric layer120may have a multi-layered structure. In some embodiments, the metal interconnection125may have a multi-layered structure having first to fourth metal interconnections125a,125b,125cand125dwhich are vertically stacked and electrically connected to the integrated circuit111. The inter-metal dielectric layer120may include a plurality of dielectric layers123provided between the first to fourth metal interconnections125a,125b,125cand125d. The dielectric layers123may include a low-k dielectric, such as, for example, an ultra low-k dielectric. For example, the dielectric layers123may include SiCOH. In some embodiments, some or all of the dielectric layers of the plurality of dielectric layers123may have different constituents from each other.

The four metal interconnections125ato125dare described as an example in the present specification. Accordingly, the number of the metal interconnections125ato125dis not limited to four. In some embodiments, the number of stacked metal interconnections may be greater than or smaller than four. Hereinafter, the dielectric layer123is defined as a low-k dielectric layer for convenience of explanation. The low-k dielectric layer123may include a low-k dielectric and/or an ultra low-k dielectric.

The inter-metal dielectric layer120may further include insulating capping layers121which reduce or prevent a metal element of the metal interconnection125from being diffused. The capping layers121may include a low-k dielectric, for example, SiCN. The capping layers121may be provided between the low-k dielectric layers123, between a lowermost low-k dielectric layer123and the interlayer dielectric layer110, and/or between an uppermost low-k dielectric layer123and the upper dielectric layer130.

Referring toFIG. 1B, a mask layer80may be formed on the upper dielectric layer130, and a via-hole101may then be formed by an etching process using the mask layer80as an etch mask. For example, a photoresist may be coated on the upper dielectric layer130, and the coated photoresist may then be patterned to form the mask layer80. The upper dielectric layer130, the inter-metal dielectric layer120, the interlayer dielectric layer110, and the semiconductor substrate110may be patterned to form the via-hole101by a dry etching process using the mask layer80as an etch mask. A bottom surface of the via-hole101may not reach the bottom surface100bof the semiconductor substrate100. Sidewalls of the upper dielectric layer130, the inter-metal dielectric layer120, and the interlayer dielectric layer110may be exposed through the via-hole101.

The mask layer80may be removed by an ashing process. An ashing gas may include CO, CO2, N2/H2, O2, or any combination thereof. The ashing process may be performed at a high temperature (e.g., 200° C. or more) or a low temperature (e.g., less than 200° C.). In some embodiments, the mask layer80may be removed by a high temperature O2ashing process of about 280° C. In some embodiments, the mask layer80may be removed by a low temperature CO2ashing process of about 100° C. or less, which can minimize ashing damage of the low-k dielectric layers123. An organic strip process capable of removing a residue (e.g., the photoresist) may be further performed after the ashing process.

The inter-metal dielectric layer120may be damaged by at least one of the etching process and the ashing process. In some embodiments, the damage may be due to the loss of carbon, such as, but not limited to, the loss of carbon-containing groups (e.g., alkyl groups such as methyl groups, ethyl groups, etc.) in the inter-metal dielectric layer120. In some embodiments, the carbon loss may be in a low-k dielectric layer123in the inter-metal dielectric layer120. For example, referring now toFIGS. 2A-2D, a surface region123aincluding a surface123sexposed by the via-hole101of the low-k dielectric layer123may be damaged by at least one of the etching process and the ashing process, as illustrated inFIG. 2A.

In some embodiments, if the low-k dielectric layer123includes SiCOH as illustrated inFIG. 2B, a carbon loss may occur by the etching process and/or ashing process such that the surface region123aof the low-k dielectric layer123may lose —CH3groups as illustrated inFIG. 2C. Since the low-k dielectric layer123loses —CH3groups, the low-k characteristic of the low-k dielectric layer123may be deteriorated.

A surface100sof the semiconductor substrate100, which is exposed by the via-hole101, may have a hydrophilic property, such as, for example, it may include a Si—OH group, by at least one of the etching process and the ashing process. Thus, a strip process using diluted hydrofluoric acid (DHF) may be performed to hydrophobically treat the surface100sof the semiconductor substrate100. However, if the carbon loss occurs in the low-k dielectric layers123, the surfaces123sof the low-k dielectric layers123may have no resistance to the DHF such that the surface regions123aof the lower-k dielectric layers123may be etched during the DHF strip process. In some embodiments, a recovery process supplementing the carbon loss may be performed in order to maintain a low-k characteristic of the low-dielectric layer123and/or in order to secure resistance to a DHF strip process of the low-k dielectric layer123, as later mentioned with reference toFIG. 1C.

Referring toFIG. 1C, the recovery process may be capable of supplementing the low-k dielectric layer123with carbon. The recovery process may be performed by providing a gas including carbon or carbon inclusive of at least one of silicon (Si), hydrogen (H), oxygen (O) and nitrogen (N) to the low-k dielectric layer123. In some embodiments, the gas may include carbon and at least one of silicon (Si), hydrogen (H), oxygen (O) and nitrogen (N). For example, the provided gas may include SiC, SiCO, SiCN, or any combination thereof. In some embodiments, the gas may be provided such that the gas contacts at least a portion of a low-k dielectric layer123such as, for example, a surface123sand/or surface region123aof the low-k dielectric layer123. The recovery process may be performed at a temperature in a range of about 200° C. to about 500° C. under an oxidation or inert atmosphere. The recovery process may be performed using a thermal process or an ultraviolet (UV) curing process. In some embodiments, the recovery process may substitute the —OH group of the Si—OH bond shown inFIG. 2Cwith a —CH3group to form a Si—CH3bond such that the carbon loss of the low-k dielectric layer123may be supplemented. The surface region123ain which the carbon loss occurs may be recovered to have Si—CH3bonds by the supplement of the carbon, so that the low-k dielectric layer123may maintain its low-k characteristic and/or may have resistance to a DHF strip process.

The low-k dielectric layer123may have a non-uniform carbon concentration as a result of the carbon loss and the recovery process. After performing a recovery process, the carbon concentration of the low-k dielectric layer123may become reduced and then increased from the surface123stoward a bulk region123bof the low-k dielectric layer123. Referring toFIG. 2D, in some embodiments, the surface123smay have a first carbon concentration, and a surface-nearby region123cadjacent to the surface123smay have a second carbon concentration lower than the first carbon concentration. The bulk region123bmay have a third carbon concentration higher than the second carbon concentration. In some embodiments, the first carbon concentration of the surface123smay be equal or similar to the third carbon concentration of the bulk region123b. In some embodiments, the first carbon concentration of the surface123smay be different from the third carbon concentration of the bulk region123b. For example, if the number of Si—CH3bonds is greater at the surface123s, the first carbon concentration may be higher than the third carbon concentration.

The surface123sof the low-k dielectric layer123may be converted from having a hydrophilic property to having a hydrophobic property by the recovery process. For example, due to the carbon loss caused by the etching process and/or ashing process, the surface123sof the low-k dielectric layer123may include a Si—OH bond, thereby providing a hydrophilic property at the surface123s, as illustrated inFIG. 2C. In some embodiments, by using the recovery process, the surface123sof the low-k dielectric layer123may be converted from a hydrophilic surface to a hydrophobic surface. As described later with reference toFIG. 1D, the hydrophilic property due to the Si—OH bond may reduce a deposition rate of a dielectric layer140a, which may cause imperfect and/or defective deposition and/or non-uniformity of a thickness of the dielectric layer140a. Since the surface123sof the low-k dielectric layer123may be substituted with a Si—CH3bond having a hydrophobic property by the recovery process, good deposition of the dielectric layer140amay be induced.

The surface100sof the semiconductor substrate100exposed through the via-hole101may be hydrophobically treated by the recovery process. Thus, there may be no need to perform the DHF strip process for hydrophobically treating the surface100s. As illustrated inFIG. 2A, the recovery process may hydrophobically treat a surface110sof the interlayer dielectric layer110, a surface121sof the capping layer121, and a surface130sof the upper dielectric layer130, which are exposed by the via-hole101.

If the recovery process is not performed, it may be required to perform a DHF strip process for hydrophobically treating the surface100sof the semiconductor substrate100. The DHF strip process may cause removal of the surface region123aof the low-k dielectric layer123and/or imperfections and/or defects in the deposition process of the dielectric layer140adue to the hydrophilic property of the surfaces123s. In some embodiments, the recovery process may be performed to cure etching damage in the low-k dielectric layer123, to maintain the low-k characteristic of the low-k dielectric layer123, and/or to hydrophobically treat the surface123s. In addition, the surface100sof the semiconductor substrate110can be hydrophobically treated by the recovery process without the DHF strip process. In some embodiments, the DHF strip process may be further performed before and/or after the recovery process.

An inner surface of the via-hole101consisting of the surfaces100s,110s,121s,123s, and130sexposed by the vi-hole101may have a heterogeneous surface state because at least some surfaces, such as for example surfaces123sand100s, may have a hydrophilic property by the influence of the etching process and/or ashing process. However, after the recovery process, the inner surface of the via-hole101may have a homogeneous surface state having a hydrophobic property.

Referring toFIG. 10, the dielectric layer140amay be formed to cover the inner sidewall of the via-hole101and a top surface of the upper dielectric layer130. The dielectric layer140amay include a silicon oxide layer deposited by a CVD process. The dielectric layer140amay be formed by depositing a high-aspect-ratio process (HARP) oxide using a sub-atmospheric chemical vapor deposition (SACVD) process. Next, a conductive layer155amay be formed on the semiconductor substrate100to fill the via-hole101. In some embodiments, since the inner surface of the via-hole101is hydrophobically treated, the dielectric layer140amay be deposited very well on the inner surface of the via-hole101.

The conductive layer155amay be formed of poly-silicon, copper, tungsten, and/or aluminum by a deposition technique and/or a plating technique. If the conductive layer155ais formed of copper or a conductive material including copper, a metal layer151acapable of preventing diffusion of copper may be further formed on the dielectric layer140a. The metal layer151amay be formed by depositing a metal including titanium (Ti), titanium nitride (TiN), chrome (Cr), tantalum (Ta), tantalum nitride (TaN), nickel (Ni), tungsten (W), tungsten nitride (WN), or any combination thereof. The metal layer151amay be formed to extend along the dielectric layer140a.

In some embodiments, the conductive layer155amay be formed by electroplating copper. For example, a seed layer153amay be formed on the dielectric layer140aor the metal layer151a, and the conductive layer155amay then be formed by an electroplating process using the seed layer153a. The seed layer153amay be formed of a metal, for example, copper or a metal including copper (e.g., copper-manganese (CuMn)) by a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process.

After the formation of the conductive layer155a, the upper dielectric layer130or the dielectric layer140aon the upper dielectric layer130may be exposed by a planarization process. For example, a chemical mechanical polishing (CMP) process may be performed until the upper dielectric layer130is exposed.

Referring toFIG. 1E, the dielectric layer140amay be transformed into a via-dielectric layer140and the conductive layer155amay be transformed into a through-electrode155by the planarization process. The seed layer153amay correspond to a portion of the through-electrode155. The through-electrode155may completely penetrate the upper dielectric layer130, the inter-metal dielectric layer120, and the interlayer dielectric layer110and may partially penetrate the semiconductor substrate100.

The via-dielectric layer140may have a cup-shape surrounding a sidewall and a bottom surface of the through-electrode155. In some embodiments, if the dielectric layer140ais used as a polishing stop layer during the CMP process, the via-dielectric layer140may surround the sidewall and the bottom surface of the through-electrode155and may further extend onto the top surface of the upper dielectric layer130.

In the event that the metal layer151ais further formed, the metal layer151amay be transformed into a barrier layer151preventing an element (e.g., copper) of the through-electrode155from being diffused into the semiconductor substrate100or the integrated circuit111by the planarization process.

Referring toFIG. 1F, an upper interconnection170electrically connected to the through-electrode155may be formed on the semiconductor substrate100. In some embodiments, the upper interconnection170contacting the through-electrode155may be formed on the upper dielectric layer130using a deposition process or a damascene process. In some embodiments, the upper interconnection170may be formed together with the through-electrode155by an electroplating process. The upper interconnection170may be electrically connected to the metal interconnection125(e.g., the fourth metal interconnection125d) through a via177penetrating the upper dielectric layer130, so as to electrically connect the through-electrode155to the integrated circuit111. A second upper dielectric layer160may be further formed on the semiconductor substrate100. The second upper dielectric layer160may act as an electrically insulating layer between adjacent upper interconnection170and/or a protecting layer. In some embodiments, an upper terminal175may be formed on the upper interconnection170. The upper terminal175may be formed of a lead (Pb)-free solder.

Referring toFIG. 1G, the semiconductor substrate100may be recessed until the through-electrode155protrudes. For example, the bottom surface100bof the semiconductor substrate100may be recessed by at least one of a grinding process, a chemical mechanical polishing process and an etching process which use an etchant or slurry capable of selectively removing the material (e.g., silicon) of the semiconductor substrate100. The recess process may be performed until a third bottom surface100dis exposed. The third bottom surface100dmay be more adjacent to the top surface100athan the bottom surface100b, and the through-electrode155may protrude from the third bottom surface100d. For example, the bottom surface100bof the semiconductor substrate100may be chemically-mechanically polished to emerge a second bottom surface100cthrough which the through-electrode155is not exposed, and the second bottom surface100cmay then be dry-etched to reveal the third bottom surface100dthrough which the through-electrode155is exposed. In some embodiments, the bottom surface100bof the semiconductor substrate100may be ground to expose the second bottom surface100c, and the second bottom surface100cmay then be chemically and mechanically polished to expose the third bottom surface100d.

A carrier95may be adhered to the top surface100aof the semiconductor substrate100by an adhesive layer90, and the protruding process of the through-electrode155may be then performed. The semiconductor substrate100may be overturned such that the bottom surface100bmay face upward, and the protruding process may then be performed under a condition that the bottom surface100bfaces upward. The top surface100amay be hereinafter referred to as an active surface, and the third bottom surface100dmay be hereinafter referred to as an inactive surface.

Referring toFIG. 1H, a lower dielectric layer180may be formed on the inactive surface100dof the semiconductor substrate100. In some embodiments, a silicon oxide layer or a silicon nitride layer may be deposited on the inactive surface100dso as to cover the through-electrode155, and a chemical mechanical polishing process may then be performed on the deposited silicon oxide layer or silicon nitride layer to form a planarized lower dielectric layer180. The through-electrode155may be exposed through the lower dielectric layer180. Next, a lower terminal190electrically connected to the through-electrode155may be formed on the lower dielectric layer180. The lower terminal190may have a pad-shape or a solder ball-shape. A semiconductor device1including the through-electrode155may be fabricated according to the embodiments described above.

In some embodiments, the low-k dielectric layers123constituting the inter-metal dielectric layer120may reduce parasitic capacitance between the first to fourth metal interconnections125ato125d, thereby reducing or removing data errors caused by noise, delay and/or loss of electrical signals transmitted through the first to fourth metal interconnections125ato125d.

FIGS. 3A to 3Gare cross-sectional views illustrating a method for fabricating a semiconductor device according to some embodiments of the present inventive concepts.

Referring toFIG. 3A, an interlayer dielectric layer110including an integrated circuit111may be formed on an active surface100aof a semiconductor substrate100having a bottom surface100b, and a capping layer121and a low-k dielectric layer123may be repeatedly and alternately stacked on the interlayer dielectric layer110. First to third metal interconnections125a,125band125cmay be included in the low-k dielectric layers123. An uppermost layer of the stacked layers on the semiconductor substrate100may be the low-k dielectric layer123or the capping layer121. In some embodiments, the uppermost layer being the low-k dielectric layer123will be described as an example. However, features of the present embodiments may be applied when the uppermost layer is the capping layer121.

Referring toFIG. 3B, a mask layer80may be formed on the low-k dielectric layer123of the uppermost layer, and a dry etching process using the mask layer80may be performed to form a via-hole101. The via-hole101may not reach the bottom surface100bof the semiconductor substrate100. The mask layer80may be removed by, for example, a low temperature CO2ashing process of about 100° C. or less. Etching damage and/or a carbon loss may occur in a surface region123aof the low-k dielectric layer123by the etching process and/or the ashing process.

Referring toFIG. 3C, in order to cure the damage and/or carbon loss, a recovery process of supplementing the low-k dielectric layer123with carbon may be performed by providing a gas including carbon or carbon inclusive of at least one of silicon (Si), hydrogen (H), oxygen (O) and nitrogen (N) (e.g., SiC, SiCO, SiCN, or any combination thereof). The surface region123aof the low-k dielectric layer123may be supplemented with carbon by the recovery process such that a Si—OH bond having a hydrophilic property in the surface region123amay be substituted with a Si—CH3bond having a hydrophobic property. A surface100sof the semiconductor substrate100, which is exposed through the via-hole101, may be changed to have a hydrophobic property by the recovery process such that it may be possible to skip a DHF strip process for hydrophobically treating the surface100sof the semiconductor substrate100. Alternatively, the DHF strip process may be further performed before and/or after the recovery process.

Referring toFIG. 3D, a via-dielectric layer140and a through-electrode155may be formed. The via-dielectric layer140may cover an inner surface of the via-hole101, and a sidewall and a bottom surface of the through-electrode155may be surrounded by the via-dielectric layer140. A barrier layer151may be further formed between the through-electrode155and the via-dielectric layer140. Since the inner surface of the via-hole101may be uniformly hydrophobically treated by the recovery process, a deposition process of the via-dielectric layer140may be excellent.

Referring toFIG. 3E, a fourth metal interconnection125dand a low-k dielectric layer123dmay be formed on the semiconductor substrate100. The fourth metal interconnection125dmay be electrically connected to the through-electrode155and may be disposed in the low-k dielectric layer123d. An upper dielectric layer130may be formed on the fourth metal interconnection125d, and a capping layer121dmay be formed between the upper dielectric layer130and the low-k dielectric layer123d. The fourth metal interconnection125dmay be connected to the third metal interconnection125cto electrically connect the through-electrode155to the integrated circuit111. The first to fourth metal interconnections125ato125dmay constitute a metal interconnection125having a multi-layered structure (e.g., a four-layered structure). The low-k dielectric layers123and123dand the capping layers121and121dmay constitute an inter-metal dielectric layer120.

An upper terminal175may be formed on the upper dielectric layer130. The upper terminal175may penetrate the upper dielectric layer130so as to be electrically connected to the fourth metal interconnection125d. In some embodiments, the upper terminal175may be formed in a redistribution pad shape.

Referring toFIG. 3F, a carrier95may be adhered to the active surface100aof the semiconductor substrate100by an adhesive layer90, and the bottom surface100bof the semiconductor substrate100may then be recessed such that the through-electrode155may protrude. In some embodiments, the bottom surface100bof the semiconductor substrate100may be chemically-mechanically polished or grinded to emerge a second bottom surface100cthrough which the through-electrode155is not exposed and then the second bottom surface100cmay be dry-etched or chemically-mechanically polished to expose an inactive surface100dthrough which the through-electrode155is protruded.

Referring toFIG. 3G, a silicon oxide layer or a silicon nitride layer may be deposited to cover the through-electrode155on the inactive surface100dof the semiconductor substrate100, and a chemical-mechanical polishing process may then be performed on the deposited silicon oxide layer or silicon nitride layer to form a planarized lower dielectric layer180. Next, a lower terminal190electrically connected to the through-electrode155may be formed on the lower dielectric layer180. The lower terminal190may have a pad-shape or a solder ball-shape. A semiconductor device2including the through-electrode155may be fabricated according to the embodiments described above.

FIG. 4Ais a schematic block diagram illustrating a memory card including a semiconductor device according to some embodiments of the present inventive concepts.FIG. 4Bis a schematic block diagram illustrating an information processing system applied with a semiconductor device according to some embodiments of the present inventive concepts.

Referring toFIG. 4A, a memory device1210including at least one of semiconductor devices1and2according to embodiments of the present inventive concepts may be applied to a memory card1200. For example, the memory card1200may include a memory controller1220that controls data communication between a host1230and the memory device1210. A static random access memory (SRAM) device1221may be used as a working memory of a central processing unit (CPU)1222. A host interface unit1223may be configured to include a data communication protocol between the memory card1200and the host1230. An error check and correction (ECC) block1224may detect and correct errors of data which are read out from the memory device1210. A memory interface unit1225may interface with the memory device1210. The CPU1222controls an overall operation of the memory controller1220. The CPU1222may include at least one of the semiconductor devices1and2according to embodiments of the present inventive concepts.

Referring toFIG. 4B, an information processing system1300may include a memory system1310including at least one of the semiconductor devices1and2according to embodiments of the present inventive concepts. The information processing system1300may include a mobile device or a computer. For example, the information processing system1300may include a modem1320, a central processing unit (CPU)1330, a random access memory (RAM)1340, and a user interface unit1350that are electrically connected to the memory system1310through a system bus1360. The memory system1310may include a memory device1311and a memory controller1312. The memory system1310may have substantially the same structure as the memory card1200illustratedFIG. 4A. At least one of the CPU1330and the RAM1340may include at least one of the semiconductor devices1and2according to embodiments of the present inventive concepts.

The memory system1310may store data processed by the CPU1330or data inputted from an external system. The information processing system1300may be realized as a memory card, a solid state disk (SSD) device, a camera image sensor, and/or another type of application chipset. For example, if the memory system1310is realized as the SSD device, the information processing system1300may stably and reliably store massive data.

As described above, by an etching process and/or ashing process for the formation of a via-hole, an inter-metal dielectric layer may be damaged and/or carbon loss may occur in the inter-metal dielectric layer. According to some embodiments of the present inventive concepts, by performing a recovery process as described herein, the inter-metal dielectric layer may be supplemented with carbon and/or the low-k characteristic of the inter-metal dielectric layer may be maintained. Some embodiments provide that, after a recovery process as described herein, the inter-metal dielectric layer may have a hydrophobic property and/or resistance to a DHF strip process. In some embodiments, a recovery process as described herein may allow for the low-k dielectric layer to not be removed after a DHF strip process and/or for the low-k characteristic of the inter-metal dielectric layer to be maintained after a DHF strip process. In some embodiments, a recovery process as described herein may allow for a DHF strip process to be skipped and/or to be unnecessary. Thus, the integrity of the semiconductor device may be secured and/or the electrical characteristics of the semiconductor device may be improved. In some embodiments, a surface of a semiconductor substrate exposed by the via-hole may have a hydrophobic property due to the recovery process, so the DHF strip process may be skipped. In some embodiments, a low-temperature CO2ashing process may be performed to minimize damage of the low-k dielectric layer. Some embodiments provide that fabricating processes of the semiconductor device may be simplified.