SEMICONDUCTOR DEVICE

A semiconductor device includes a first semiconductor chip, a second semiconductor chip, and a redistribution layer. The first semiconductor chip and the second semiconductor chip are arranged spaced apart from each other in a second direction orthogonal to a first direction. The redistribution layer is disposed across over the first semiconductor chip and the second semiconductor chip. The redistribution layer includes a first inductor and a second inductor. The first inductor and the second inductor are spaced apart and face each other in a third direction orthogonal to the first direction and the second direction. The first inductor and the second inductor are electrically connected to the first semiconductor chip and the second semiconductor chip, respectively. The first inductor and the second inductor are wound across over the first semiconductor chip and the second semiconductor chip in a plane orthogonal to the third direction.

CROSS-REFERENCE TO RELATED APPLICATIONS

The disclosure of Japanese Patent Application No. 2022-077552 filed on May 10, 2022, including the specification, drawings and abstract is incorporated herein by reference in its entirety.

BACKGROUND

The present disclosure relates to a semiconductor device.

There are disclosed techniques listed below.

A semiconductor device described in Patent Document 1 includes a first semiconductor chip and a second semiconductor chip, and a redistribution layer. A thickness direction of the semiconductor device is defined as a first direction. A direction orthogonal to the first direction is defined as a second direction. The first semiconductor chip and the second semiconductor chip are arranged spaced apart from each other in the second direction.

The redistribution layer is disposed across over the first semiconductor chip and the second semiconductor chip. The redistribution layer includes a first inductor and a second inductor. The first inductor and the second inductor are spaced apart and face each other in the first direction. The redistribution layer includes a plurality of wirings stacked in the first direction. The first inductor is configured by winding one of the plurality of wirings included in the redistribution layer in a plane orthogonal to the first direction. The second inductor is configured by winding another one of the plurality of wirings included in the redistribution layer in a plane orthogonal to the first direction.

SUMMARY

In the semiconductor device described in Patent Document 1, since the first inductor and the second inductor are configured by winding wirings included in the redistribution layer in a plane orthogonal to the first direction, the occupied area of the first inductor and the second inductor in plan view increases. Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

A semiconductor device according to the present disclosure includes a first semiconductor chip, a second semiconductor chip, and a redistribution layer. The first semiconductor chip and the second semiconductor chip are arranged spaced apart from each other in a second direction orthogonal to a first direction which is a thickness direction of the semiconductor device. The redistribution layer is disposed across over the first semiconductor chip and the second semiconductor chip. The redistribution layer includes a first inductor and a second inductor. The first inductor and the second inductor are spaced apart and face each other in a third direction orthogonal to the first direction and the second direction. The first inductor is electrically connected to the first semiconductor chip. The second inductor is electrically connected to the second semiconductor chip. The first inductor and the second inductor are wound across over the first semiconductor chip and the second semiconductor chip in a plane orthogonal to the third direction.

According to the semiconductor device of the present disclosure, it is possible to reduce the occupied area of the first inductor and the second inductor in plan view.

DETAILED DESCRIPTION

Details of embodiments of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and redundant description will not be repeated.

First Embodiment

A semiconductor device according to the first embodiment will be described. The semiconductor device according to the embodiment is defined as a semiconductor device DEV1. Configuration of Semiconductor Device DEV1

FIG.1is a schematic configuration diagram of the semiconductor device DEV1. As shown inFIG.1, the semiconductor device DEV1includes a semiconductor chip CHP1, a semiconductor chip CHP2, an inductor ID1, and an inductor ID2. The inductor ID1is electrically connected to the semiconductor chip CHP1. The inductor ID2is electrically connected to the semiconductor chip CHP2. The inductor ID1and the inductor ID2are magnetically coupled. The inductor ID1and the inductor ID2are electrically isolated from each other.

The semiconductor chip CHP1can transmit and receive signals to and from the semiconductor chip CHP2via the inductor ID1and the inductor ID2in a state that the semiconductor chip CHP1is electrically isolated from the semiconductor chip CHP2. The semiconductor device DEV1is a digital isolator. However, the semiconductor device DEV1is not limited to the digital isolator.

FIG.2is a plan view of the semiconductor device DEV1. InFIG.2, the illustration of the redistribution layer FOL is omitted, and the inductor ID1and the inductor ID2are indicated by dotted lines.FIG.3is a cross-sectional view in III-III inFIG.2.FIG.4is a cross-sectional view in IV-IV inFIG.2.FIG.5is a cross-sectional view in V-V inFIG.2.FIG.6is an enlarged cross-sectional view of the semiconductor chip CHP1.FIG.7is an enlarged cross-sectional view of the semiconductor chip CHP2. As shown inFIGS.2to7, the semiconductor device DEV1includes the semiconductor chip CHP1, the semiconductor chip CHP2, a sealing resin ER, and the redistribution layer FOL.

The semiconductor chip CHP1includes a semiconductor substrate SUB1, element isolation films ISL1, gate dielectric films GI1, gate electrodes G1, sidewall spacers SWS1, and a wiring layer WL1. The wiring layer WL1includes an interlayer dielectric film ILD1a, contact plugs CP1, an interlayer dielectric film ILD1b, wirings WL1a, a plurality of interlayer dielectric films ILD1c, a plurality of wirings WL1b, and a plurality of via plugs VP1.

The semiconductor substrate SUB1has a first surface FS1and a second surface SS1. The first surface FS1and the second surface SS1are end surfaces along a thickness direction of the semiconductor substrate SUB1. The second surface SS1is an opposite surface of the first surface FS1. The semiconductor substrate SUB1is formed of, for example, monocrystalline silicon (Si).

The semiconductor substrate SUB1includes source regions SR1, drain regions DR1, and well regions WR1. The source region SR1and the drain region DR1are formed in the first surface FS1so as to be spaced apart from each other. The conductivity types of the source region SR1and the drain region DR1are the first conductivity type.

The source region SR1includes a first portion SR1aand a second portion SR1b. The first portion SR1ais closer to the drain region DR1than the second portion SR1b. The drain region DR1includes a first portion DR1aand a second portion DR1b. The first portion DR1ais closer to the source region SR1than the second portion DR1b. The dopant concentration in the first portion SR1ais lower than the dopant concentration in the second portion SR1b, and the dopant concentration in the first portion DR1ais lower than the dopant concentration in the second portion DR1b. That is, the source region SR1and the drain region DR1have an LDD (Lightly Doped Diffusion) structure.

The well region WR1is formed in the first surface FS1so as to surround the source region SR1and the drain region DR1. The conductivity type of the well region WR1is the second conductivity type. The second conductivity type is a conductivity type opposite the first conductivity type.

The gate dielectric film GI1is disposed on the first surface FS1. More specifically, the gate dielectric film GI1is disposed on the first surface FS1between the source region SR1and the drain region DR1. The gate dielectric film GI1is formed of, for example, silicon oxide. The gate electrode G1is disposed on the gate dielectric film GI1. That is, the gate electrode G1faces the well region WR1between the source region SR1and the drain region DR1with the gate dielectric film GI1interposed therebetween. The gate electrode G1is formed of, for example, polycrystalline silicon containing dopants. The source region SR1, the drain region DR1, the well region WR1, the gate dielectric film GI1, and the gate electrode G1constitute a transistor.

The sidewall spacer SWS1is disposed on the first surface FS1. More specifically, the sidewall spacers SWS1are disposed on the first portion SR1aand the first portion DR1aso as to be in contact with side surfaces of the gate electrode G1. The sidewall spacer SWS1is formed of, for example, silicon nitride. The element isolation film ISL1is disposed on the first surface FS1so as to surround the well region WR1in plan view. More specifically, trenches TR1aextending toward the second surface SS1are formed in the first surface FS1. The element isolation film ISL1is embedded in the trench TR1a. The element isolation film ISL1is formed of, for example, silicon oxide.

The wiring layer WL1is disposed on the first surface FS1. The interlayer dielectric film ILD1ais disposed on the first surface FS1so as to cover the gate electrode G1, the sidewall spacer SWS1, and the element isolation film ISL1. The interlayer dielectric film ILD1ais formed of, for example, silicon oxide. Contact holes CH1are formed in the interlayer dielectric film ILD1a. The source region SR1, the drain region DR1, or the gate electrode G1is exposed from the contact hole CH1. The contact plug CP1is embedded in the contact hole CH1. The lower end of the contact plug CP1is electrically connected to the source region SR1, the drain region DR1, or the gate electrode G1. The contact plug CP1is formed of, for example, tungsten (W).

The interlayer dielectric film ILD1bis disposed on the interlayer dielectric film ILD1a. The interlayer dielectric film ILD1bis formed of, for example, silicon oxide. Trenches TR1bare formed in the interlayer dielectric film ILD1b. The trench TR1bpenetrates through the interlayer dielectric film ILD1balong the thickness direction. The wiring WL1ais embedded in the trench TR1b. The wiring WL1ais formed of, for example, copper (Cu). The wiring WL1ais electrically connected to an upper end of the contact plug CP1.

The plurality of interlayer dielectric films ILD1care laminated and disposed on the interlayer dielectric film ILD1b. The interlayer dielectric film ILD1cis formed of silicon oxide. Trenches TR1care formed in an upper surface of the interlayer dielectric film ILD1c. Via holes VH1are formed in the interlayer dielectric film ILD1c. The via hole VH1penetrates through the interlayer dielectric film ILD1calong the thickness direction. An upper end of the via hole VH1is open at the bottom surface of the trench TR1c, and a lower end of the via hole VH1is open at the lower surface of the interlayer dielectric film ILD1c.

The wiring WL1bis embedded in the trench TR1c. The via plug VP1is embedded in the via hole VH1. The wiring WL1band the via plug VP1are integrally formed. The wiring WL1band the via plug VP1are formed of copper. The via plug VP1connects the wiring WL1ato the lowermost wiring WL1b, and connects two adjacent wirings WL1balong the thickness direction of the wiring layer WL1.

The semiconductor chip CHP2includes a semiconductor substrate SUB2, element isolation films ISL2, gate dielectric films GI2, gate electrodes G2, sidewall spacers SWS2, and a wiring layer WL2. The wiring layer WL2includes an interlayer dielectric film ILD2a, contact plugs CP2, an interlayer dielectric film ILD2b, wirings WL2a, a plurality of interlayer dielectric films ILD2c, a plurality of wirings WL2b, and a plurality of via plugs VP2.

The semiconductor substrate SUB2has a first surface FS2and a second surface SS2. The first surface FS2and the second surface SS2are end surfaces along the thickness direction of the semiconductor substrate SUB2. The second surface SS2is an opposite surface of the first surface FS2. The semiconductor substrate SUB2is formed of, for example, monocrystalline silicon.

The semiconductor substrate SUB2includes source regions SR2, drain regions DR2, and well regions WR2. The source region SR2and the drain region DR2are formed in the first surface FS2so as to be spaced apart from each other. The conductivity types of the source region SR2and the drain region DR2are the first conductivity type.

The source region SR2includes a first portion SR2aand a second portion SR2b. The first portion SR2ais closer to the drain region DR2than the second portion SR2b. The drain region DR2includes a first portion DR2aand a second portion DR2b. The first portion DR2ais closer to the source region SR2than the second portion DR2b. The dopant concentration in the first portion SR2ais lower than the dopant concentration in the second portion SR2b, and the dopant concentration in the first portion DR2ais lower than the dopant concentration in the second portion DR2b. That is, the source region SR2and the drain region DR2have an LDD structure.

The well region WR2is formed in the first surface FS2so as to surround the source region SR2and the drain region DR2. The conductivity type of the well region WR2is the second conductivity type. The second conductivity type is a conductivity type opposite to the first conductivity type.

The gate dielectric film GI2is disposed on the first surface FS2. More specifically, the gate dielectric film GI2is disposed on the first surface FS2between the source region SR2and the drain region DR2. The gate dielectric film GI2is formed of, for example, silicon oxide. The gate electrode G2is disposed on the gate dielectric film GI2. That is, the gate electrode G2faces the well region WR2between the source region SR2and the drain region DR2with the gate dielectric film GI2interposed therebetween. The gate electrode G2is formed of, for example, polycrystalline silicon containing dopants. The source region SR2, the drain region DR2, the well region WR2, the gate dielectric film GI2, and the gate electrode G2constitute a transistor.

The sidewall spacer SWS2is disposed on the first surface FS2. More specifically, the sidewall spacers SWS2are disposed on the first portion SR2aand the first portion DR2aso as to be in contact with the side surfaces of the gate electrode G2. The sidewall spacer SWS2is formed of, for example, silicon nitride. The element isolation film ISL2is disposed on the first surface FS2so as to surround the well region WR2in plan view. More specifically, trenches TR2aextending toward the second surface SS2are formed in the first surface FS2. The element isolation film ISL2is embedded in the trench TR2a. The element isolation film ISL2is formed of, for example, silicon oxide.

The wiring layer WL2is disposed on the first surface FS2. The interlayer dielectric film ILD2ais disposed on the first surface FS2so as to cover the gate electrode G2, the sidewall spacer SWS2, and the element isolation film ISL2. The interlayer dielectric film ILD2ais formed of, for example, silicon oxide. Contact holes CH2are formed in the interlayer dielectric film ILD2a. The source region SR2, the drain region DR2, or the gate electrode G2is exposed from the contact hole CH2. The contact plug CP2is embedded in the contact hole CH2. A lower end of the contact plug CP2is electrically connected to the source region SR2, the drain region DR2, or the gate electrode G2. The contact plug CP2is formed of, for example, tungsten.

The interlayer dielectric film ILD2bis disposed on the interlayer dielectric film ILD2a. The interlayer dielectric film ILD2bis formed of, for example, silicon oxide. Trenches TR2bare formed in the interlayer dielectric film ILD2b. The trench TR2bpenetrates through the interlayer dielectric film ILD2balong the thickness direction. The wiring WL2ais embedded in the trench TR2b. The wiring WL2ais formed of, for example, copper. The wiring WL2ais electrically connected to an upper end of the contact plug CP2.

The plurality of interlayer dielectric films ILD2care laminated and disposed on the interlayer dielectric film ILD2b. The interlayer dielectric film ILD2cis formed of silicon oxide. Trenches TR2care formed in an upper surface of the interlayer dielectric film ILD2c. Via holes VH2are formed in the interlayer dielectric film ILD2c. The via hole VH2penetrates through the interlayer dielectric film ILD2calong the thickness direction. An upper end of the via hole VH2is open at the bottom surface of the trench TR2c, and a lower end of the via hole VH2is open at the lower surface of the interlayer dielectric film ILD2c.

The wiring WL2bis embedded in the trench TR2c. The via plug VP2is embedded in the via hole VH2. The wiring WL2band the via plug VP2are integrally formed. The wiring WL2band the via plug VP2are formed of copper. The via plug VP2connects the wiring WL2ato the lowermost wiring WL2b, and connects two adjacent wirings WL2balong the thickness direction of the wiring layer WL2.

The sealing resin ER seals the semiconductor chip CHP1and the semiconductor chip CHP2such that an upper surface of the wiring layer WL1and an upper surface of the wiring layer WL1are exposed. The sealing resin ER has a first surface FS3and a second surface SS3. The first surface FS3and the second surface SS3are end surfaces of the sealing resin ER in the thickness direction. The first surface FS3is flush with the upper surface of the wiring layer WL1and the upper surface of the wiring layer WL2. The second surface SS3is an opposite surface of the first surface FS3. The sealing resin ER is formed of a thermosetting resin material such as an epoxy resin.

The redistribution layer FOL is disposed on the first surface FS3across over the semiconductor chip CHP1(wiring layer WL1) and the semiconductor chip CHP2(wiring layer WL2). The redistribution layer FOL is disposed on the first surface FS3so as to overlap with the semiconductor chip CHP1(wiring layer WL1) and the semiconductor chip CHP2(wiring layer WL2). The redistribution layer FOL includes an interlayer dielectric film ILD3a, an interlayer dielectric film ILD3b, an interlayer dielectric film ILD3c, wirings WL3a, wirings WL3b, and wirings WL3c.

The interlayer dielectric film ILD3ais disposed on the first surface FS3across over the semiconductor chip CHP1(wiring layer WL1) and the semiconductor chip CHP2(wiring layer WL2). The interlayer dielectric film ILD3ais disposed on the first surface FS3so as to overlap with the semiconductor chip CHP1(wiring layer WL1) and the semiconductor chip CHP2(wiring layer WL2). The interlayer dielectric film ILD3ais formed of, for example, a resin material such as polyimide. Via holes VH3aare formed in the interlayer dielectric film ILD3a. The via hole VH3apenetrates through the interlayer dielectric film ILD3aalong the thickness direction.

The wiring WL3ais disposed on the interlayer dielectric film ILD3a. The wiring WL3ais also embedded in the via hole VH3a. Thus, the wiring WL3ais electrically connected to the uppermost wiring WL1bor the uppermost wiring WL2b. The wiring WL3ais formed of, for example, copper.

The interlayer dielectric film ILD3bis disposed on the interlayer dielectric film ILD3a. The interlayer dielectric film ILD3bis formed of, for example, a resin material such as polyimide. Via holes VH3bare formed in the interlayer dielectric film ILD3b. The via hole VH3bpenetrates through the interlayer dielectric film ILD3balong the thickness direction. The wiring WL3bis disposed on the interlayer dielectric film ILD3b. The wiring WL3bis also embedded in the via hole VH3b. Thus, the wiring WL3bis electrically connected to the wiring WL3a. The wiring WL3bis formed of, for example, copper.

The interlayer dielectric film ILD3cis disposed on the interlayer dielectric film ILD3b. The interlayer dielectric film ILD3cis formed of, for example, a resin material such as polyimide. Via holes VH3care formed in the interlayer dielectric film ILD3c. The via hole VH3cpenetrates through the interlayer dielectric film ILD3calong the thickness direction. The wiring WL3cis disposed on the interlayer dielectric film ILD3c. The wiring WL3cis also embedded in the via hole VH3c. Thus, the wiring WL3cis electrically connected to the wiring WL3b. The wiring WL3cis formed of, for example, copper.

The wiring WL3cincludes a pad electrode PAD1and a pad electrode PAD2. The pad electrode PAD1is electrically connected to the semiconductor chip CHP1by the wiring WL3band the wiring WL3a. The pad electrode PAD2is electrically connected to the semiconductor chip CHP2by the wiring WL3aand the wiring WL3b. Note that the wiring WL3a, the wiring WL3b, and the wiring WL3chave a base film BF as their base. The base film BF is configured by a barrier metal layer and a seed layer disposed on the barrier metal layer.

A thickness direction of the semiconductor device DEV1is defined as a first direction D1. A direction orthogonal to the first direction D1is defined as a second direction D2. A direction orthogonal to the first direction D1and the second direction D2is defined as a third direction D3. The semiconductor chip CHP1and the semiconductor chip CHP2are arranged spaced apart from each other in the second direction D2.

The inductor ID1is wound across over the semiconductor chip CHP1and the semiconductor chip CHP2in a plane orthogonal to the third direction D3. The inductor ID1is formed so as to overlap with the semiconductor chip CHP1and the semiconductor chip CHP2. The inductor ID1is configured by the wiring WL3aand the wiring WL3b. More specifically, the wiring WL3ahas a straight portion WL3aaand a straight portion WL3ab, and the wiring WL3bhas a straight portion WL3ba. The straight portion WL3aa, the straight portion WL3ab, and the straight portion WL3baextend along the second direction D2in a cross-sectional view orthogonal to the third direction D3.

One end (the right side inFIG.3) of the straight portion WL3aain the second direction D2is electrically connected to the semiconductor chip CHP1by the wiring WL3aembedded in the via hole VH3a. The other end (the left side inFIG.3) of the straight portion WL3abin the second direction D2is electrically connected to the semiconductor chip CHP1by the wiring WL3aembedded in the via hole VH3a. Both ends of the straight portion WL3bain the second direction D2are electrically connected to the other end of the straight portion WL3aain the second direction D2and one end of the straight portion WL3abin the second direction D2by the wiring WL3bembedded in the via hole VH3b, respectively.

The inductor ID2is wound across over the semiconductor chip CHP1and the semiconductor chip CHP2in a plane orthogonal to the third direction D3. The inductor ID2is formed so as to overlap with the semiconductor chip CHP1and the semiconductor chip CHP2. The inductor ID2is configured by the wiring WL3aand the wiring WL3b. More specifically, the wiring WL3ahas a straight portion WL3acand a straight portion WL3ad, and the wiring WL3bhas a straight portion WL3bb. The straight portion WL3ac, the straight portion WL3ad, and the straight portion WL3bbextend along the second direction D2in a cross-sectional view orthogonal to the third direction D3.

One end of the straight portion WL3acin the second direction D2is electrically connected to the semiconductor chip CHP2by the wiring WL3aembedded in the via hole VH3a. The other end of the straight portion WL3adin the second direction D2is electrically connected to the semiconductor chip CHP2by the wiring WL3aembedded in the via hole VH3a. Both ends of the straight portion WL3bbin the second direction D2are electrically connected to the other end of the straight portion WL3acin the second direction D2and one end of the straight portion WL3adin the second direction D2by the wiring WL3bembedded in the via hole VH3b.

The inductor ID1and the inductor ID2are spaced apart and face each other in the third direction D3. The inductor ID1and the inductor ID2are insulated from each other by the interlayer dielectric film ILD3a, the interlayer dielectric film ILD3b, and the interlayer dielectric film ILD3c. The inductor ID1and the inductor ID2are magnetically coupled to each other. Therefore, the semiconductor chip CHP1and the semiconductor chip CHP2can transmit and receive signals via the inductor ID1and the inductor ID2while being insulated from each other.

Manufacturing Method of Semiconductor Device DEV1

A manufacturing method of the semiconductor device DEV1is described below.

FIG.8is a process diagram showing the manufacturing method of the semiconductor device DEV1. As shown inFIG.8, the manufacturing method of the semiconductor device DEV1includes a preparation step S1, a resin sealing step S2, and a redistribution step S3. The resin sealing step S2is performed after the preparation step S1. The redistribution step S3is performed after the resin sealing step S2.

The resin sealing step S2includes a first step S21and a second step S22. The second step S22is performed after the first step S21. The redistribution step S3includes a first step S31, a second step S32, a third step S33, a fourth step S34, and a fifth step S35. The second step S32is performed after the first step S31. The third step S33is performed after the second step S32. The fourth step S34is performed after the third step S33. The fifth step S35is performed after the fourth step S34.

In the preparation step S1, the semiconductor chip CHP1and the semiconductor chip CHP2are prepared. A manufacturing method of the semiconductor chip CHP1and the semiconductor chip CHP2may be performed by conventionally known methods, and therefore will not be described here.

FIG.9is a cross-sectional view showing the first step S21. As shown inFIG.9, in the first step S21, the semiconductor chip CHP1and the semiconductor chip CHP2are bonded to a support substrate SSUB by an adhesive AD. At this time, the semiconductor chip CHP1on the wiring layer WL1side and the semiconductor chip CHP2on the wiring layers WL2side are bonded to the support substrate SSUB.

FIG.10is a cross-sectional view showing the second step S22. As shown inFIG.10, in the second step S22, a sealing resin ER is disposed on the support substrate SSUB so as to cover the semiconductor chip CHP1and the semiconductor chip CHP2. After the sealing resin ER is disposed on the support substrate SSUB, the second surface SS3is polished and planarized. This polishing is performed, for example, by CMP (Chemical Mechanical Polishing). After this polishing is performed, the support substrate SSUB is removed from the semiconductor chip CHP1and the semiconductor chip CHP2.

FIG.11is a cross-sectional view showing the first step S31. As shown inFIG.11, in the first step S31, the interlayer dielectric film ILD3ais formed. In the forming the interlayer dielectric film ILD3a, first, a constituent material of the interlayer dielectric film ILD3ais formed on the first surface FS3. Second, the via holes VH3aare formed by exposing and developing the formed constituent material of the interlayer dielectric film ILD3a.

FIG.12is a cross-sectional view showing the second step S32. As shown inFIG.12, in the second step S32, the base film BF is formed on the interlayer dielectric film ILD3a, on the inner wall surface of the via hole VH3a, and on the wiring WL1b(wiring WL2b) exposed from the via hole VH3a.FIG.13is a cross-sectional view showing the third step S33. As shown inFIG.13, in the third step S33, a resist pattern RP is formed on the base film BF. The resist pattern RP is formed by forming a photoresist material on the base film BF, exposing, developing and patterning the formed photoresist material.

FIG.14is a cross-sectional view showing the fourth step S34. As shown inFIG.14, in the fourth step S34, the wiring WL3ais formed on the base film BF exposed from the resist pattern RP. The wiring WL3ais formed by performing electroplating on the base film BF which is exposed from the resist pattern RP by energizing the base film BF.FIG.15is a cross-sectional view showing the fifth step S35. As shown inFIG.15, in the fifth step S35, after the resist pattern RP is removed, the base film BF underlying the resist pattern RP is removed by etching.

By repeating the same steps from the first step S31to the fifth step S35, the interlayer dielectric film ILD3b, the wirings WL3b, the interlayer dielectric film ILD3cand the wirings WL3care formed. After the redistribution step S3is performed, it is singulated into the semiconductor device DEV1. Thus, the semiconductor device DEV1having the structure shown inFIG.2is formed.

Effects of Semiconductor Device DEV1

The effects of the semiconductor device DEV1are described below.

In the semiconductor device DEV1, the inductor ID1and the inductor ID2are wound in a plane orthogonal to the third direction D3. Therefore, in the semiconductor device DEV1, the occupied area of the inductor ID1and the inductor ID2in plan view can be made smaller than when the inductor ID1and the inductor ID2are wound in a plane orthogonal to the first direction D1.

In the semiconductor device DEV1, since the inductor ID1and the inductor ID2are formed across over the semiconductor chip CHP1and the semiconductor chip CHP2, the inductance value of the inductor ID1and the inductor ID2can be ensured because the length of wiring configuring the inductor ID1and the inductor ID2can be ensured.

When the inductor ID1and the inductor ID2are spaced apart and face each other in the first direction D1, the dielectric breakdown voltage between the inductor ID1and the inductor ID2is determined by the thickness of the interlayer dielectric film of the redistribution layer FOL between the inductor ID1and the inductor ID2. A modification in the thickness of the interlayer dielectric film of the redistribution layer FOL between the inductor ID1and the inductor ID2increases the manufacturing cost. When the thickness of the interlayer dielectric film of redistribution layer FOL increases, the semiconductor chip CHP1and the semiconductor chip CHP2are bent due to stresses from the interlayer dielectric film.

On the other hand, in the semiconductor device DEV1, the dielectric breakdown voltage between the inductor ID1and the inductor ID2is determined by the distance between the inductor ID1and the inductor ID2in the third direction D3. The distance between the inductor ID1and the inductor ID2in the third direction D3can be freely set, and the breakdown voltage between the inductor ID1and the inductor ID2can be easily secured in the semiconductor device DEV1. In addition, in the semiconductor device DEV1, since the thickness of the interlayer dielectric film of the redistribution layer FOL does not need to be increased in order to secure the dielectric breakdown voltage between the inductor ID1and the inductor ID2, it is possible to prevent the semiconductor chip CHP1and the semiconductor chip CHP2from being bent.

Second Embodiment

A semiconductor device according to the second embodiment will be described. The semiconductor device according to the second embodiment is defined as a semiconductor device DEV2. Here, differences from the semiconductor device DEV1will be mainly described, and redundant description will not be repeated.

Configuration of Semiconductor Device DEV2

The configuration of the semiconductor device DEV2is described below.

FIG.16is a plan view of the semiconductor device DEV2. InFIG.16, the illustration of the redistribution layer FOL is omitted, and the inductor ID1and the inductor ID2are indicated by dotted lines. As shown inFIG.16, in the semiconductor device DEV2, one end part (the right side inFIG.16) of the inductor ID1in the second direction D2is at a position shifted in the second direction D2from one end part of the inductor ID2in the second direction D2. In the semiconductor device DEV2, the other end (the left side inFIG.16) of the inductor ID1in the second direction D2is at a position shifted in the second direction D2from the other end of the inductor ID2in the second direction D2.

More specifically, in the semiconductor device DEV2, a width of the inductor ID1in the second direction D2is smaller than a width of the inductor ID2in the second direction D2, and one end part of the inductor ID1and the other end part of the inductor ID1in the second direction D2are inside in the second direction D2than one end part of the inductor ID2and the other end part of the inductor D2in the second direction D2, respectively. In these respects, the configuration of the semiconductor device DEV2is different from the configuration of the semiconductor device DEV1. Although not shown, the width of the inductor ID1in the second direction D2may be larger than the width of the inductor ID2in the second direction D2, and one end part of the inductor ID1and the other end part of the inductor ID1in the second direction D2may be outside in the second direction D2than one end part of the inductor ID2and the other end part of the inductor ID2in the second direction D2, respectively.

FIG.17is a plan view of the semiconductor device DEV2according to a modified example. InFIG.17, the illustration of the redistribution layer FOL is omitted, and the inductor ID1and the inductor ID2are indicated by dotted lines. As shown inFIG.17, in the semiconductor device DEV2, one end part of the inductor ID1and the other end part of the inductor ID1in the second direction D2may be at positions shifted in the second direction D2from one end part of the inductorID2 and the other end part of the inductor ID2in the second direction D2, and the width of the inductor ID1in the second direction D2may be equal to the width of the inductor ID2in the second direction D2.

Effects of Semiconductor Device DEV2

The effects of the semiconductor device DEV2are described below.

Electric field concentration is likely to occur at both end parts of the inductor ID1and the inductor ID2in the second direction D2. In the semiconductor device DEV2, one end part of the inductor ID1and the other end part of the inductor ID1in the second direction D2are at positions shifted in the second direction D2from one end part of the inductor ID2and the other end part of the inductor ID2in the second direction D2, respectively, so that the position where the electric field concentration is likely to occur in the inductor ID1and the position where the electric field concentration is likely to occur in the inductor ID2are at positions shifted from each other. Therefore, according to the semiconductor device DEV2, the dielectric breakdown voltage between the inductor ID1and the inductor ID2is easily secured.

Third Embodiment

A semiconductor device according to the third embodiment will be described. The semiconductor device according to the third embodiment is defined as a semiconductor device DEV3. Here, differences from the semiconductor device DEV1will be mainly described, and redundant description will not be repeated.

The configuration of the semiconductor device DEV3is described below.

FIG.18is a plan view of the semiconductor device DEV3. InFIG.18, the illustration of the redistribution layer FOL is omitted, the inductor ID1, the inductor ID2, the inductor ID3and the inductor ID4are shown by the dotted line.FIG.19is a cross-sectional view in XIX-XIX inFIG.18.FIG.20is a cross-sectional view in XX-XX inFIG.18. As shown inFIGS.18to20, the semiconductor device DEV3further includes an inductor ID3and an inductor ID4. The inductor ID3is wound across over the semiconductor chip CHP1and the semiconductor chip CHP2in a plane orthogonal to the third direction D3. The inductor ID3is formed so as to overlap with the semiconductor chip CHP1and the semiconductor chip CHP2. The inductor ID3is configured by the wiring WL3aand the wiring WL3b. The inductor ID3is electrically connected to the semiconductor chip CHP1.

The inductor ID4is wound across over the semiconductor chip CHP1and the semiconductor chip CHP2in a plane orthogonal to the third direction D3. The inductor ID4is formed so as to overlap with the semiconductor chip CHP1and the semiconductor chip CHP2. The inductor ID4is configured by the wiring WL3aand the wiring WL3b. The inductor ID4is electrically connected to the semiconductor chip CHP2. The inductor ID3and the inductor ID4are spaced apart and face each other in the third direction D3. That is, the inductor ID3and the inductor ID4are magnetically coupled while being electrically insulated from each other. The inductor ID2is located, for example, between the inductor ID1and the inductor ID3in the third direction D3. The inductor ID3is located, for example, between the inductor ID2and the inductor ID4in the third direction D3.

A distance between the inductor ID2and the inductor ID3in the third direction D3is defined as a first distance. A distance between the inductor ID1and the inductor ID2in the third direction D3is defined as a second distance, and a distance between the inductor ID3and the inductor ID4in the third direction D3is defined as a third distance. The first distance is, for example, larger than the second distance and the third distance. The first distance is preferable 10 times or more than the second distance and the third distance.

The inductor ID1and the inductor ID3are independent of each other. The inductor ID2and the inductor ID4are independent of each other. In these respects, the configuration of the semiconductor device DEV3is different from the configuration of the semiconductor device DEV1.

Effects of Semiconductor Device DEV3

The effects of the semiconductor device DEV3are described below.

In the semiconductor device DEV3, the inductor ID1and the inductor ID3are independent of each other, and the inductor ID2and the inductor ID4are independent of each other. Therefore, in the semiconductor device DEV3, a signal can be transmitted and received between the semiconductor chip CHP1and the semiconductor chip CHP2via the inductor ID1and the inductor ID2, and a signal can be transmitted and received between the semiconductor chip CHP1and the semiconductor chip CHP2via the inductor ID3and the inductor ID4. As described above, according to the semiconductor device DEV3, signal transmission and signal reception in multichannel can be performed between the semiconductor chip CHP1and the semiconductor chip CHP2.

Incidentally,FIGS.18to20show that there are two channels for transmitting and receiving signals between the semiconductor chip CHP1and the semiconductor chip CHP2, but if the number of inductors is increased, signals can be transmitted and received between the semiconductor chip CHP1and the semiconductor chip CHP2in three or more channels.

When the first distance is larger than the second distance and the third distance, interference between a channel for transmission and reception of a signal configured by the inductor ID1and the inductor ID2and a channel for transmission and reception of a signal configured by the inductor ID3and the inductor ID4is suppressed. The coupling coefficient between the inductors is proportional to the square of the dielectric distance between the inductors. Therefore, for example, if the first distance is 10 times or more than the second distance and the third distance, it is possible to reduce the interference between the channel of the transmission and reception of the signal configured by the inductor ID1and the inductor ID2and the channel of the transmission and reception of the signal configured by the inductor ID3and the inductor ID4to 1% or less.

Fourth Embodiment

A semiconductor device according to the fourth embodiment will be described. The semiconductor device according to the fourth embodiment is defined as a semiconductor device DEV4. Here, differences from the semiconductor device DEV3will be mainly described, and redundant description will not be repeated.

The configuration of the semiconductor device DEV4is described below.

FIG.21is a plan view of the semiconductor device DEV4. InFIG.21, the illustration of the redistribution layer FOL is omitted, the inductor ID1, the inductor ID2, the inductor ID3and the inductor ID4are shown by the dotted line. InFIG.21, the wiring WL1bin the uppermost layer and the wiring WL2bin the uppermost layer are indicated by dotted lines.

As shown inFIG.21, in the semiconductor device DEV4, the inductor ID1and the inductor ID3are electrically connected to each other by the wiring WL1bin the uppermost layer. In the semiconductor device DEV4, the inductor ID2and the inductor ID4are electrically connected to each other by the wiring WL2bin the uppermost layer. In these respects, the configuration of the semiconductor device DEV4is different from the configuration of the semiconductor device DEV3.

Effects of Semiconductor Device DEV4

The effects of the semiconductor device DEV4are described below.

In the semiconductor device DEV4, the inductor ID1and the inductor ID3are electrically connected to each other by the wiring WL1bin the uppermost layer, and the inductor ID2and the inductor ID4are electrically connected to each other by the wiring WL2bin the uppermost layer. Therefore, according to the semiconductor device DEV4, the differential transformer can be configured by the inductor ID1and the inductor ID3, and the differential transformer can be configured by the inductor ID2and the inductor ID4.

Fifth Embodiment

A semiconductor device according to the fifth embodiment will be described. The semiconductor device according to the fifth embodiment is defined as a semiconductor device DEV5. Here, differences from the semiconductor device DEV1will be mainly described, and redundant description will not be repeated.

The configuration of the semiconductor device DEV5will be described below.

FIG.22is a plan view of the semiconductor device DEV5. InFIG.22, the illustration of the redistribution layer FOL is omitted, and the inductor ID1and the inductor ID2are indicated by dotted lines.FIG.23is a schematic perspective view of the inductor ID1.FIG.24is a schematic perspective view of the inductor ID2. As shown inFIGS.22to24, in the semiconductor device DEV5, the inductor ID1includes a first portion ID1aand a second portion ID1b. In the semiconductor device DEV5, the inductor ID2includes a first portion ID2aand a second portion ID2b.

Each of the first portion ID1aand the second portion ID1bis wound across the semiconductor chip CHP1and the semiconductor chip CHP2in a plane orthogonal to the third direction D3. Each of the first portion ID1aand the second portion ID1bis formed so as to overlap with the semiconductor chip CHP1and the semiconductor chip CHP2. The first portion ID1aand the second portion ID1bare spaced apart and face each other in the third direction D3. One end of the first portion ID1aand the other end of the second portion ID1bare electrically connected to the semiconductor chip CHP1. The other end of the first portion ID1aand one end of the second portion ID1bare electrically connected to each other by the wiring WL3a(connecting portion WL3ae). The connecting portion WL3ae extends along the third direction D3.

Each of the first portion ID2aand the second portion ID2bis wound across the semiconductor chip CHP1and the semiconductor chip CHP2in a plane orthogonal to the third direction D3. Each of the first portion ID2aand the second portion ID2bis formed so as to overlap with the semiconductor chip CHP1and the semiconductor chip CHP2. The first portion ID2aand the second portion ID2bare spaced apart and face each other in the third direction D3. One end of the first portion ID2aand the other end of the second portion ID2bare electrically connected to the semiconductor chip CHP1. The other end of the first portion ID2aand one end of the second portion ID2bare electrically connected to each other by the wiring WL3a(connecting portion WL3af). The connecting portion WL3af extends along the third direction D3. In these respects, the configuration of the semiconductor device DEV5is different from the configuration of the semiconductor device DEV1.

In the examples shown inFIGS.22to24, the number of windings of each of the inductor ID1and the inductor ID2is 2, but the number of windings of each of the inductor ID1and the inductor ID2may be 3 or more. Further, in the examples shown inFIGS.22to24, the inductor ID1and the inductor ID2are each plural, but the number of windings of either one of the inductor ID1and the inductor ID2may not be plural.

Effects of Semiconductor Device DEV5

The effects of the semiconductor device DEV5are described below.

In the semiconductor device DEV5, the number of windings of each of the inductor ID1and the inductor ID2is plural. Therefore, according to the semiconductor device DEV5, it is possible to increase the coupling coefficient of the inductor ID1and the inductor ID2.

Although the invention made by the present inventors has been described in detail based on the embodiments, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist thereof.