Via architecture for increased density interface

Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.

BACKGROUND

Packaging sizing for semiconductor products can contribute to overall device scale. For mobile devices, packaging size can facilitate an overall form factor reduction. Packaging size can limit product performance due to restrictions in board layout and density.

Figures may not be drawn to scale.

DETAILED DESCRIPTION

Package z-height is a differentiator for today's semiconductor products, especially in the mobile arena. Two of the limiting factors for z-height reduction include power delivery and input/output (I/O) routing.

This disclosure describes an architecture for the top package substrate layers that include a via configuration that can increase I/O routing density that can lead to z-height reduction due to layer count reduction and/or layer thickness reduction by using self-aligned vias (SAVs) or zero-misaligned vias (ZMVs) and a patterned top metal layer. The use of lithographically defined SAVs or ZMVs and the use of a closely spaced ground plane allows for single ended or differential pair high speed I/Os to be routed in a single metal layer instead of across multiple metal layers. The via configuration facilitates a 1:1 ground-to-signal trace ratio in the routing layer. This via configuration allows for a wide range of impedances to be closely matched. For example, by increasing the distance to the top ground (GND) plane, impedance can be changed, while changing the thickness distance to the bottom GND changes the impedance less-so. The via configuration described herein also decreases crosstalk between neighboring signal traces.

FIG. 1Ais a schematic diagram of a cross-sectional view of a package substrate100that includes a via architecture in accordance with embodiments of the present disclosure. The package substrate100includes a substrate102. The package substrate can include a plurality of metallization interconnect layers for integrated circuits. A package substrate may include alternating metal and dielectric layers. Among the metal layers, some may form ground or power planes and others may be used for signal traces.

The substrate102includes metallization interconnect layers for integrated circuits. Based on aspects of the present disclosure, the number of metal layers can be reduced (e.g., by a metal layer pair, such as a top and bottom metal layer). InFIG. 1A, the substrate102includes three metal layers: M1104, M2106, and M3108, each separated by a dielectric layer. In at least some embodiments, the substrate102includes interconnects, for example, vias, configured to connect the metallization layers M1104, M2106, and M3108.

The M3 metal layer108is typically formed first. Here, the M3 metal layer generally includes a M3 ground plane110. The M3 ground plane110can be interconnected to upper layers by a via112. The M3 metal layer108also includes power routing lines118and corresponding vias. The M3 ground plane110can also be coupled to the M2 metal layer106by a ground via114. In the M2 metal layer, a ground pad116can electrically couple the M2 ground traces (e.g., ground trace120) to the M3 ground plane110.

The M2 metal layer106generally includes the high speed input/output signal traces (e.g., signal trace124) and the ground traces (e.g., ground trace120). The signal trace124is electrically coupled to the M1 signal pad132by a SAV or ZMV126. Likewise, the ground trace120can be electrically coupled to the M1 metal layer ground plane130by a SAV or ZMV122. The M2 metal layer also includes other vias and interconnects, such as the M2 ground landing pad128and the M2 power landing pad129.

The top metal layer or M1 metal layer104can include first level interconnect (FLI) pads, such as the signal pad132and the power interconnect pad134. The M1 metal layer104can also include a surface metal that can serve as an M1 ground plane130. Solder bumps144a-144ccan be used to interconnect the various circuit elements to other chips. The M1 metal layer104can also include a solder resist142.

The M1 metal layer104is coupled to the M2 metal layer106by SAV or ZMV coupled to traces in the M2 metal layer106. The SAV or ZMV126connects the signal trace124to signal bump144b. The ground trace120is coupled to the M1 ground plane130by an SAV or ZMV291122. Certain ground traces in the M2 metal layer106can be coupled to the ground pad116in the M2 metal layer106. These ground traces would be coupled to the M1 metal layer ground plane130by the M3 ground plane110. The M1 metal layer ground plane130is connected to ground bump144aon the die as well as to the M3 ground plane110in the substrate. This helps adjust impedance, tie all ground lines to the same potential, reduce cross talk, and enable the high speed input/output (HSIO) SAV/ZMV I/O to reach optimum performance.

FIG. 1Bis a schematic diagram of a cross-sectional view of another example package substrate150that includes a via architecture in accordance with embodiments of the present disclosure. The via architecture of package substrate150is similar to that shown inFIG. 1A. The surface metal of the M1 ground plane130in the embodiments illustrated byFIG. 1Acan be a standard thickness metal layer (which is usually 10-15 μm thick). However, if such metal thickness is not required (for instance all I/Os, whether high speed or low speed, can be routed on M2) the top metal can serve only as first level interconnect (FLI) pads. For example, pad162can serve as a signal pad, while pad164can serve as a power pad. The M1 ground plane160can replace the thicker M1 metal layer ground plane130shown inFIG. 1A. The FLI pads can be made as thin as possible considering FLI requirement. To facilitate signaling, a copper thickness of only 1.5 μm is sufficient as an effective ground plane. To have a stable FLI, this copper (Cu) layer can be followed by a barrier layer of nickel (Ni) and then palladium (Pd) and gold (Au) (thin layers). The total thickness can be at or below 5 μm, which can further reduce the package thickness.

The thin metal layer for the M1 ground plane160on top has a thickness between 2-6 μm and can be formed from copper. Other metals typical for a surface finish can also be used depending on the application.

The SAV and ZMV do not need a large pad to land, so the density of the traces can be increased and can be formed on a single metal layer (e.g., M2106). Because the traces are on a single metal layer, ground traces can be formed between each signal trace (except for differential pairs). For example, ground trace120resides between signal trace156and signal trace152. Signal trace152resides between ground traces120and154. To provide grounding, the ground traces can be connected to the top/surface ground layer (e.g., M1 metal layer ground plane130) and by a ground plane below (e.g., M3 ground plane110).

In general, the via architecture described herein lowers the z-height of the package substrate and reduces near-end and far-end cross talk. Due to the use of SAV or ZMV, a higher I/O density can be achieved with the goal of routing all critical HSIO lines in a single layer. This is achieved without changing design rules, such as by using new or advanced patterning equipment.

One of the constraints of an increase of the number of I/O lines in a single metal layer is that crosstalk can be increased as signaling lines get closer together. The increased line density of the via architecture described herein allows for the placement of ground lines on both sides of every signal line and ground lines on both sides of differential pair lines, satisfying impedance targets and improving far- and near-end crosstalk.

To meet the impedance requirements and improve signaling, the ground lines should have the same potential. Since there is no alignment margin for downward vias (that are not SAV or ZMV), the thin metal layer/surface finish of the M1 ground plane160used for FLI attach is used to connect all ground lines. The ground connectivity is completed by vias going down to the package substrate GND layers (e.g., through M3 ground plane110) wherever alignment margin allows it. This is what is illustrated by the ground pad116and corresponding ground via114inFIG. 1A-1B.

Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from devices through the one or more metal (interconnect) layers. The one or more interconnect layers M1104, M2106, and M3108may form a metallization stack (also referred to as an “interlayer dielectric stack”) of the package substrate.

The routing traces (e.g., signal trace124and ground trace120) may be arranged within the M2 metal layer106to route electrical signals according to a wide variety of designs. In some embodiments, the routing traces may include traces filled with an electrically conductive material such as a metal.

The interconnect layers may include a dielectric material disposed between the interconnect structures. For example, the M2 metal layer106can include a dielectric material158between the traces and other M2 metal layer structures. In some embodiments, the dielectric material158disposed between the interconnect structures in different ones of the interconnect layers M1104, M2106, and M3108may have different compositions; in other embodiments, the composition of the dielectric material158between different interconnect layers M1104, M2106, and M3108may be the same.

The package substrate100may include a solder resist material142(e.g., polyimide or similar material) and one or more conductive contacts131,132, and134formed on the M1 metal layer104. InFIG. 1A, the conductive contacts131,132, and134are illustrated as taking the form of bond pads. The conductive contact132may be electrically coupled with the SAV/ZMV126and configured to route the electrical signals using signal trace124in the M2 metal layer106. Likewise, conductive contact131may be electrically coupled with the SAV/ZMV122and configured to be a ground line routed by ground trace120.

Solder bump144amay be formed on the ground conductive contacts131to mechanically and/or electrically couple a package including the package substrate100with another component (e.g., a circuit board). The package substrate100may include additional or alternate structures to route the electrical signals from the metal layers104-108; for example, the conductive contacts may include other analogous features (e.g., posts) that route the electrical signals to external components.

FIG. 2is a schematic diagram of top view200of a package substrate100that includes a via architecture and a ground plane in accordance with embodiments of the present disclosure.FIG. 2illustrates a package substrate202that includes a bump field that includes solder bump landing pads (e.g., signal pads204a-b, and ground pad216). The M1 ground plane206is illustrated. The ground traces and signal are also illustrated, though it is understood that the ground traces are in the M2 metal layer and are shown for illustrative purposes. The SAV and ZMV are also illustrated, and likewise, it is understood that the SAV and ZMV are in the M2 metal layer.

For example,FIG. 2illustrates a signal trace208arouted to solder bump signal pad204aand connected by a SAV/ZMV210a, signal trace208brouted to solder bump204band connected by a SAV/ZMV210b. The signal traces are in the M2 metal layer and are presented for illustrative purposes.

FIG. 2also illustrates a ground trace between each signal trace. For example, signal trace208ais adjacent to ground traces coupled to ground SAV/ZMV214aand SAV/ZMV214b. Signal trace208ais shown to wind between the adjacent ground traces to reach the signal pad204a. The ground traces may extend as far as they can before termination.

FIG. 2also illustrates the ground trace routing. A ground pad216can be electrically connected to the M1 ground plane206. The ground pad216can be connected to the M2 ground trace by a ground SAV/ZMV214a(the ground trace is not shown). The M1 ground plane206can be patterned to connect to the ground pad216.FIG. 2shows an M1 patterned ground line212acoupling the grounding pad216to the M1 ground plane206.FIG. 2illustrates how the M1 ground plane can be patterned to accommodate the increased density of signal lines. Another example is shown as ground SAV/ZMV214c, which couples to the M1 ground plane206by a patterned M1 metal line212cand couples to the M1 ground plane206at a location218. The signal trace208bis in a lower layer (e.g., M2 layer) than the patterned M1 metal line212c, highlighting the ability to couple M2 layer ground traces to a common ground using the SAV/ZMV configuration.

FIGS. 3-6illustrate various embodiments for the M1 metal layer ground plane configuration. Each embodiment facilitates a decrease in near-end and far-end crosstalk. It is understood thatFIGS. 3-6illustrate example configurations, and are not limiting. Other ground plane configurations can also be used to achieve similar results.FIGS. 3-6further illustrate how the signal traces are adjacent to ground traces, with the exception of differential pair traces, which are two signal traces adjacent to a ground trace (shown inFIG. 6).

FIG. 3is a schematic diagram of a perspective cutaway view of an example package substrate300in accordance with embodiments of the present disclosure. Package substrate300includes small patches of metal on the surface302that are connected to the ground traces with SAV/ZMV. The surface metal configuration ofFIG. 3uses minimal surface finish to tie the ground traces on the routing layer (M2 metal layer) to the main ground structure and to the ground bump304.

For example, a patterned ground line320acan electrically couple ground trace306awith ground trace306b. Likewise, patterned ground line320bcan electrically couple ground trace306cwith ground traces306dand306e. Surface ground plane patches322aand322bcan be coupled with an M3 ground plane (not shown) by a via.

FIG. 4is a schematic diagram of a perspective cutaway view of another example package substrate400in accordance with embodiments of the present disclosure. The surface ground plane404resides on the package surface402and extends from the location of die-level ground bump field408to the edge of the die410. This surface ground plane404also has a slot414(i.e. opening) over differential pair signal lines412. The surface ground plane404also includes a pad406for connecting the surface ground plane404to the M3 metal ground plane (not shown).

FIG. 5is a schematic diagram of a perspective cutaway view of another example package substrate500in accordance with embodiments of the present disclosure. The package substrate500is similar to the package substrate400. The package substrate500includes a larger surface ground plane502that does not include a slot for differential pair traces. The surface ground plane502extends from the bump field508for the entire length of the traces to the location where the single traces via down to the second layer interconnect field. The surface ground plane502also includes a pad504for connecting the surface ground plane502to the M3 metal ground plane (not shown).

FIG. 6is a schematic diagram of a perspective cutaway view of another example package substrate600in accordance with embodiments of the present disclosure. Package substrate600can be considered as a combination of the surface ground plane configuration illustrated inFIGS. 4 and 5. The surface ground plane602extends from the bump field608to the end of the routing. The surface ground plane602includes a slot610over differential pair signal traces612. The surface ground plane602also includes a pad604for connecting the surface ground plane602to the M3 metal ground plane (not shown).

FIG. 7is a process flow diagram700for forming a package substrate that includes self-aligned or ZMVs and a top metal layer in accordance with embodiments of the present disclosure. A core metal material can be provided (702). The core metal material can be patterned to form the M3 metal layer structures, such as the M3 ground plane (704). The core metal material can be further processed to form the M2 metal layer structures. For example, the M2 metal layer routing traces can be patterned and formed (706). The M2 metal layer SAVs and/or ZMVs can be patterned and formed (708). The formation of SAV and ZMV can be performed by known techniques, as can the patterning and formation of the routing traces. The formation of SAV or ZMV can result in a via that has a width that is substantially similar to a width of the connected trace. The length of the SAV or ZMV can be changed to suit the connections and trace routing. The z-height of the via can be controlled based on a desired overall z-height of the M2 metal layer and/or the overall package z-height.

By way of an example, a zero-misaligned via (ZMV) formation process can use a dual-tone photoresist that includes two layers of a photomask. The photomask is rigid and substantially planar, and can be formed using known techniques that are more precise than standard via-pad registration techniques. Therefore, via-pad misalignment can be small, which allows the size of the pad to be reduced to a size the same as, or similar to, the size of the via. In some example cases, the use of a ZMV can facilitate an I/O connection density of greater than 20 I/O/mm/layer, such as between 50-80 I/O/mm/layer and above, including as many as 100-250 I/O/mm/layer.

Similarly, a mask can be used to form self-aligned vias (SAVs). Self-aligned vias can be formed using known techniques. For example, an SAV can be created by forming an Mx+1 layer over the Mx layer traces (and insulating layer(s)). The Mx+1 layer can be patterned using a hardmask or via mask to form a trench exposing the Mx metal layer trace. The SAV metal (e.g., copper) can be deposited within the trench on the trace using known metal deposition techniques. The resulting via (i.e., SAV) can have the same or similar width as the underlying trace. The length and height of the SAV can be controlled based on implementation choices.

The M1 metal layer (e.g., M1 ground plane) can be patterned and formed (710). The patterning and formation of the top metal layer M1 can be achieved using substrate semi-additive manufacturing (including seed layer deposition, lithography, plating, resist removal, and seed layer etch), or using subtractive or additive processing approaches. One advantage of additive manufacturing may be that the process flow is simplified by combining the deposition and patterning into one step, instead of requiring the multiple steps used in conventional semi-additive manufacturing. Thus, the M1 metal layer ground plane with patches and slots can be created in a single step.

Some examples of additive processing include:

1. Cold spray, in which powders of the conductive material to be deposited are accelerated through a nozzle at high speeds, forming a mechanical bond upon impact with the substrate surface. Patterning can be achieved by controlling the nozzle dimensions and movement, and/or by spraying the powders through a shadow mask with fine features. This approach is likely to produce high conductivity films due to the absence of organic binders or solvent, and the ability to keep the substrate at room temperature during spraying, thus reducing oxidation.

2. Inkjet printing in which conductive inks are printed (e.g., using an aerosol jet printer) directly on the substrate and subsequently cured or sintered to remove the solvent. This approach is likely to produce very thin films and small feature sizes (e.g., ˜12 um line width has been demonstrated using an aerosol jet printer).

3. Stencil printing of a conductive paste.

4. Laser assisted selective electroless plating, in which the regions to be patterned with the conductive layer are first functionalized using self-assembled monolayers and laser exposure, followed by electroless plating which only occurs in the functionalized areas.

The package substrate can then undergo solder resist patterning, surface finishing, and solder bump formation (712).

The use of zero-misalignment via-pad structures or self-aligned via-pad structures, as described herein, substantially decreases the via and pad sizes while increasing achievable density such as input/output connections/mm/layer. Aspects of the present embodiments have advantages, such as a decrease in manufacturing costs, a decrease in z-height, and increased electrical performance for off-package I/O connections. Embodiments to provide self-aligned or zero-misaligned via-pad structures as described herein advantageously enable 2.5D packaging (e.g., co-packaging at least two of a central processing unit (CPU), a memory, and a graphics processing unit (GPU); die splitting; quasi-monolithic integration; and other 2.5D packaging techniques). Embodiments can facilitate a reduction in manufacturing cost, decreased package z-height, increased electrical performance, and increased scalability.

FIG. 8is a schematic diagram of a computing device in accordance with embodiments of the present disclosure. The computing device800can include a processor, as well as a memory and communications circuitry. The processor and other circuitry can be supported by a package substrate. The substrate can include routing traces in a single metal layer (e.g., the M2 metal layer) by using self-aligned or ZMVs as well as a surface ground plane (e.g., M1 metal layer ground plane). The routing traces can alternate between signal traces and ground traces so that the density of the traces increases while also providing ground shielding against cross talk between signal traces.

The computing device800illustrated inFIG. 8in accordance with one embodiment of the disclosure may include a number of components. In one embodiment, these components are attached to one or more motherboards. In an alternate embodiment, some or all of these components are fabricated onto a single system-on-a-chip (SoC) die. The components in the computing device800include, but are not limited to, an integrated circuit chip802and at least one communications logic unit808. In some implementations, the communications logic unit808is fabricated within the integrated circuit chip802while in other implementations the communications logic unit808is fabricated in a separate integrated circuit chip that may be bonded to a substrate or motherboard that is shared with or electronically coupled to the integrated circuit chip802. The integrated circuit chip802may include a CPU804as well as on-die memory806, often used as cache memory, that can be provided by technologies such as embedded DRAM (eDRAM) or spin-transfer torque memory (STTM or STT-MRAM).

Computing device800may include other components that may or may not be physically and electrically coupled to the motherboard or fabricated within an SoC die. These other components include, but are not limited to, volatile memory810(e.g., DRAM), non-volatile memory812(e.g., ROM or flash memory), a GPU814, a digital signal processor (DSP)816, a crypto processor842(a specialized processor that executes cryptographic algorithms within hardware), a chipset820, an antenna822, a display (e.g., a touchscreen display)824, a touchscreen controller826, a battery828or other power source, a power amplifier (not shown), a voltage regulator (not shown), a global positioning system (GPS) device830, a compass, a motion coprocessor or sensors832(that may include an accelerometer, a gyroscope, and a compass), a speaker834, a camera836, user input devices838(such as a keyboard, mouse, stylus, and touchpad), and a mass storage device840(such as hard disk drive, compact disc (CD), digital versatile disk (DVD), and so forth).

It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated inFIGS. 1-8. The subject matter may be applied to other microelectronic device and assembly applications, as well as any appropriate heat removal application, as will be understood to those skilled in the art.

These modifications may be made to the disclosure in light of the above detailed description. The terms used in the following claims should not be construed to limit the disclosure to the specific implementations disclosed in the specification and the claims.

The following paragraphs provide examples of various ones of the embodiments disclosed herein.

Example 1 is a package substrate that includes a substrate including a first metal layer and a second metal layer; a ground plane residing on the first metal layer; a first signal trace residing in the second metal layer, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via, the first signal via including a width substantially similar to a width of the first signal trace; a second signal trace residing in the second metal layer, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via, the second signal via including a width substantially similar to a width of the second signal trace; and a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via, the ground via including a width substantially similar to a width of the ground trace.

Example 2 may include the subject matter of example 1, wherein the ground trace is a first ground trace electrically coupled to the ground plane by a first ground via, the package substrate further including a second ground trace residing in the second metal layer, the second ground trace electrically coupled to the ground plane by a second ground via, the second ground via including a width substantially similar to a width of the second ground trace; wherein the first signal trace resides between the first ground trace and the second ground trace.

Example 3 may include the subject matter of example 2, wherein the first ground trace is electrically connected the second ground trace by the ground plane.

Example 4 may include the subject matter of example 3, wherein the ground plane includes a patterned metal line electrically coupled to the first ground via and the second ground via.

Example 5 may include the subject matter of example 3, wherein the ground plane includes a ground plane on the first metal layer spanning an area of the first metal layer that covers the first signal trace.

Example 6 may include the subject matter of example 5, package substrate includes two signal traces in the second metal layer, the two signal traces defining a differential pair of signal traces; and wherein the ground plane includes a gap in a region of the first metal layer above the differential pair of signal traces.

Example 7 may include the subject matter of any of examples 1-6, wherein the ground plane is a first ground plane, the package substrate further including a third metal layer, the third metal layer including a second ground plane, the second metal layer between the first metal layer and the third metal layer, the second ground plane electrically connected to the ground trace by the first ground plane in the first metal layer.

Example 8 may include the subject matter of any of examples 1-7, wherein the first ground plane is electrically coupled to the first ground plane by a via traversing the second metal layer.

Example 9 may include the subject matter of any of examples 1-8, wherein the ground via includes one of a self-aligned via or a zero-misaligned via.

Example 10 may include the subject matter of any of examples 1-9, wherein the first signal via and the second signal via include one of a self-aligned via or a zero-misaligned via.

Example 11 may include the subject matter of any of examples 1-10, wherein the package substrate includes a plurality of signal traces in the second metal layer and a plurality of ground traces in the second metal layer, and wherein a number of signal traces is equal to a number of ground traces.

Example 12 may include the subject matter of any of examples 1-11, wherein the ground plane includes a thickness between 10-15 μm thick.

Example 13 may include the subject matter of any of examples 1-12, wherein the ground plane includes a thickness below 6 μm.

Example 14 may include the subject matter of any of examples 1-13, wherein the ground plane includes copper.

Example 15 may include the subject matter of any of examples 1-14, and can also include a signal solder bump electrically coupled to the first signal pad; a ground pad on the first metal layer, the ground pad electrically coupled to the ground plane; and a ground solder bump electrically coupled to the ground pad.

Example 16 may include the subject matter of example 15, wherein the first signal pad is a first level interconnect (FLI).

Example 17 may include the subject matter of example 16, wherein the FLI includes copper of a thickness between 1.4 μm and 1.6 μm.

Example 18 may include the subject matter of any of examples 1-17, wherein the first signal trace and the second signal trace are high speed input/output traces.

Example 19 may include the subject matter of any of examples 1-18, wherein the package substrate includes a die edge, and wherein the ground plane includes a surface metal on the first metal layer extending to the die edge.

Example 20 is a method of forming a package substrate that includes forming a substrate ground plane in a third metal layer of a substrate; forming a plurality of traces including a predetermined trace width in a second metal layer of the substrate, forming a signal via on a first subset of traces of the plurality of traces, wherein forming the signal via includes forming the signal via to a width of substantially similar width as the predetermined trace width, and wherein the first subset of traces includes alternating traces; forming a ground via on a second subset of traces of the plurality of traces, the second subset different from the first subset of traces, wherein forming the ground via includes forming the ground via to a width of substantially similar width as the predetermined trace width, and wherein the second subset of traces includes alternating traces; and forming a surface ground plane on a first metal layer, the surface ground plane on the first metal layer electrically connected to at least one ground trace by the ground via.

Example 21 may include the subject matter of example 20, and can also include forming a signal pad on the first metal layer, the signal pad electrically connected to at least one signal trace by the signal via.

Example 22 may include the subject matter of any of examples 20-21, further including forming a substrate ground via in the second metal layer, the substrate ground via electrically connected to the substrate ground plane and to the surface ground plane.

Example 23 may include the subject matter of any of examples 20-22, wherein forming the surface ground plane includes an additive processing to form a patterned metal layer on the first metal layer of the package substrate.

Example 24 may include the subject matter of example 23, wherein the additive processing includes one or more of cold spray, inkjet printing, stencil printing of a conductive paste, laser assisted selective electroless plating.

Example 25 is a computing device that includes a processor mounted on a substrate; a communications logic unit within the processor; and a memory within the processor. The substrate can include a first metal layer and a second metal layer; a ground plane residing on the first metal layer; a first signal trace residing in the second metal layer, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via, the first signal via including a width substantially similar to a width of the first signal trace; a second signal trace residing in the second metal layer, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via, the second signal via including a width substantially similar to a width of the second signal trace; and a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via, the ground via including a width substantially similar to a width of the ground trace.

Example 26 may include the subject matter of example 25, wherein the ground trace is a first ground trace and the ground via is a first ground via. The substrate can include a second ground trace residing in the second metal layer, the first signal trace between the first ground trace and the second ground trace, the second ground trace comprising electrically coupled to the ground plane by a second ground via, the second ground via comprising a width substantially similar to a width of the second ground trace; and a third ground trace residing in the second metal layer, the second signal trace between the first ground trace and the third ground trace, the third ground trace comprising electrically coupled to the ground plane by a third ground via, the third ground via comprising a width substantially similar to a width of the third ground trace.