Apparatuses including Finfets having different gate oxide configurations, and related computing systems

Fin field effect transistors (FinFETs) having various different thicknesses of gate oxides and related apparatuses, methods, and computing systems are disclosed. An apparatus includes first FinFETs, second FinFETs, and third FinFETs. The first FinFETs include a first gate oxide material, a second gate oxide material, and a third gate oxide material. The second FinFETs include the second gate oxide material and the third gate oxide material. The third FinFETs include the third gate oxide material. A method includes forming the first gate oxide material on first fins, second fins, and third fins; removing the first gate oxide material from the second fins and the third fins; forming a second gate oxide material over the first fins, the second fins, and the third fins; and removing the second gate oxide material from the third fins.

TECHNICAL FIELD

This disclosure relates generally to fin field effect transistors (FinFETs) having variable thicknesses of gate oxides and/or variable fin heights.

BACKGROUND

The demand for ever smaller and/or denser devices in semiconductor devices drove semiconductor device manufacturers to reduce gate lengths in planar transistors to the point where leakage currents were difficult to prevent. Voltage potentials applied to gate terminals of these planar transistors did not sufficiently prevent leakage currents in active material that was relatively far from material of the gate terminal because gate terminals in these planar transistors were typically positioned at only one side of the active materials. By contrast, FinFETs include gate material at two or more sides of the active material. Accordingly, voltage potentials applied to gate terminals of FinFETs may influence substantially the entire active material. As a result, FinFETs, as compared to planar transistors, generally have reduced leakage currents because the active material is at least partially surrounded by the gate material.

DETAILED DESCRIPTION

The illustrations presented herein are not meant to be actual views of any particular method, system, device, or structure, but are merely idealized representations that are employed to describe the embodiments of the present disclosure. In some instances similar structures or components in the various drawings may retain the same or similar numbering for the convenience of the reader; however, the similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other property.

It will be readily understood that the components of the embodiments as generally described herein and illustrated in the drawings could be arranged and designed in a wide variety of different configurations. Thus, the following description of various embodiments is not intended to limit the scope of the present disclosure, but is merely representative of various embodiments. While the various aspects of the embodiments may be presented in the drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

Unless the context indicates otherwise, the materials described herein may be formed by any suitable technique including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), atomic layer deposition (ALD), plasma enhanced ALD (PEALD), physical vapor deposition (PVD) (e.g., sputtering), or epitaxial growth. Depending on the specific material to be formed, the technique for depositing or growing the material may be selected by a person of ordinary skill in the art. In addition, unless the context indicates otherwise, removal of materials described herein may be accomplished by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor etching), ion milling, abrasive planarization (e.g., chemical-mechanical planarization (CMP)), or other known methods.

As used herein, “insulative material” means and includes electrically insulative material, such one or more of at least one dielectric oxide material (e.g., one or more of a silicon oxide (SiOx), phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicate glass, an aluminum oxide (AlOx), a hafnium oxide (HfOx), a niobium oxide (NbOx), a titanium oxide (TiOx), a zirconium oxide (ZrOx), a tantalum oxide (TaOx), and a magnesium oxide (MgOx)), at least one dielectric nitride material (e.g., a silicon nitride (SiNy)), at least one dielectric oxynitride material (e.g., a silicon oxynitride (SiOxNy)), at least one dielectric oxycarbide material (e.g., silicon oxycarbide (SiOxCy)), at least one hydrogenated dielectric oxycarbide material (e.g., hydrogenated silicon oxycarbide (SiCxOyHz)), and at least one dielectric carboxynitride material (e.g., a silicon carboxynitride (SiOxCzNy)). Formulae including one or more of “x,” “y,” and “z” herein (e.g., SiOx, AlOx, HfOx, NbOx, TiOx, SiNy, SiOxNy, SiOxCy, SiCxOyHz, SiOxCzNy) represent a material that contains an average ratio of “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if any) for every one atom of another element (e.g., Si, Al, Hf, Nb, Ti). As the formulae are representative of relative atomic ratios and not strict chemical structure, an insulative material may comprise one or more stoichiometric compounds and/or one or more non-stoichiometric compounds, and values of “x,” “y,” and “z” (if any) may be integers or may be non-integers. As used herein, the term “non-stoichiometric compound” means and includes a chemical compound with an elemental composition that cannot be represented by a ratio of well-defined natural numbers and is in violation of the law of definite proportions. In addition, an “insulative structure” means and includes a structure formed of and including insulative material.

As used herein, the term “high permittivity dielectric material,” or equivalently “high-k dielectric material,” refers to a material having a higher relative permittivity than silicon dioxide (SiO2). The relative permittivity of silicon dioxide is substantially 3.9 at room temperature (i.e., substantially 20 degrees centigrade). Hafnium oxide (HfO2) is one example of a high-k dielectric material because the relative permittivity of Hafnium oxide is greater than that of silicon dioxide (e.g., up to substantially 25). Other examples of high-k dielectric materials include zirconium dioxide (ZrO2, relative permittivity of substantially 25), zirconium silicate (ZrSiO4, relative permittivity of substantially 5 to 12), and hafnium silicate (HfSiO4, relative permittivity of substantially 11).

As used herein, the term “semiconductor material” refers to a material having a conductivity between those of electrically insulating materials and electrically conductive materials. For example, a semiconductor material may have a conductivity of between about 10−8Siemens per centimeter (S/cm) and about 104S/cm (106S/m) at room temperature. Examples of semiconductor materials include elements found in column IV of the period table of elements such as silicon (Si), germanium (Ge), and carbon (C). Other examples of semiconductor materials include compound semiconductor materials such as binary compound semiconductor materials (e.g., gallium arsenide (GaAs)), ternary compound semiconductor materials (e.g., AlXGa1-XAs), and quaternary compound semiconductor materials (e.g., GaXIn1-XAsYP1-Y), without limitation. Compound semiconductor materials may include combinations of elements from columns III and V of the period table of elements (III-V semiconductor materials) or from columns II and VI of the period table of elements (II-VI semiconductor materials), without limitation. Semiconductor devices often include crystalline semiconductor materials. By way of non-limiting examples, transistors and diodes include crystalline semiconductor materials.

As used herein, the term “intrinsic semiconductor material” refers to a semiconductor material having a relatively small density of impurities (e.g., a lower density of impurities than electron and hole densities resulting from thermal generation at room temperature).

As used herein, the term “doped semiconductor material” refers to a semiconductor material having a higher density of impurities introduced thereto than intrinsic semiconductor materials (e.g., a higher density of impurities than electron and hole densities resulting from thermal generation at room temperature). A doped semiconductor material may be doped predominantly with donor impurities such as phosphorus (P), antimony (Sb), bismuth (Bi), and arsenic (As), without limitation. Each donor impurity in a crystal lattice of semiconductor material adds a free electron, which increases the conductivity of the semiconductor material relative to the intrinsic form of the semiconductor material. Doped semiconductor materials that have been doped predominantly with donor impurities are referred to herein as “N-type semiconductor materials.” A doped semiconductor may instead be doped predominantly with trivalent or acceptor impurities such as boron (B), indium (In), aluminum (Al), and gallium (Ga), without limitation. Each trivalent or acceptor impurity in a crystal lattice of semiconductor material adds an electron hole (referred to herein as “hole”), which increases the conductivity of the semiconductor material relative to the intrinsic form of the semiconductor material. Doped semiconductor materials that have been doped predominantly with trivalent or acceptor impurities are referred to herein as “P-type semiconductor materials.”

As used herein, the term “active material” refers to a semiconductor material that has been doped to function as a channel material in a metal oxide semiconductor (MOS) field effect transistor (FET) (MOSFET). A MOSFET transistor having a channel material that has been doped predominantly with donor impurities is referred to herein as an N-type MOS (NMOS) transistor because the active material serving as the channel material for the NMOS transistor includes N-type semiconductor material. Similarly, a MOSFET transistor having a channel material that has been doped predominantly with trivalent or acceptor impurities is referred to herein as a P-type MOS (PMOS) transistor because the active material serving as the channel material for the PMOS transistor includes P-type semiconductor material.

FinFETs are examples of MOSFET transistors that include fin-shaped active materials, or “fins,” and gate materials on at least two sides of the fins. Some FinFET transistors include gate materials on three sides of the fins, such as on lateral and top sides of the fins. Gate oxide materials electrically isolate the fins from the gate materials.

In some semiconductor devices (e.g., memory devices, without limitation) some FinFETs may be exposed to higher voltage potentials than other FinFETs. In other words, higher voltage potential differences may be applied across terminals of some FinFET s than others. As a specific, non-limiting example, some CMOS periphery circuitry for dynamic random access memory (DRAM) devices may include FinFETs that may be exposed to relatively high voltage potentials and other FinFETs that may be exposed to relatively low voltage potentials. In general, FinFETs with thicker gate oxide materials have higher transistor breakdown voltage potential ratings than FinFETs with thinner gate oxide materials. As a result, FinFETs that may have higher voltage potentials applied across their terminals may be manufactured with thicker gate oxide materials than FinFETs that may have lower voltage potentials applied across their terminals to prevent transistor breakdown.

Manufacturing thicker gate oxide materials, however, may result in fins becoming too thin (e.g., less than four nanometers) as silicon consumption to form thicker gate oxides may consume a relatively large amount of the active material of the fins. By way of non-limiting example, radical oxides (e.g., in-situ steam generated (ISSG) oxides) may consume nearly 45% of the active material of the fin during manufacturing. Structural instability of the fins and/or performance degradation (e.g., degraded carrier mobility) due to quantum confinement and/or stress on the fin material may result if the fins are too thin (e.g., less than four nanometers thin).

Designers of electronic circuitry including FinFETs that may be used for high-voltage operation (e.g., periphery circuitry for memory devices such as periphery circuitry for dynamic random access memory (DRAM)) may be faced with a choice between using thin gate oxide FinFETs, which may break down during high voltage operation, and thick gate oxide FinFETs, which may suffer from performance degradation related to fin consumption. Since the thin gate oxide FinFETs may break down during high voltage operation, such FinFETs may not be used for electronic circuitry that may be used for high-voltage operation. As a result, high-voltage circuitry such as DRAM periphery circuitry may be implemented using thick gate oxide FinFETs, which may result in degraded performance of the high-voltage circuitry.

Disclosed herein are FinFETs including gate oxides of various different thicknesses. Rather than limiting designers to choose between two different gate oxide thicknesses, embodiments disclosed herein enable manufacturing of intermediate gate oxide thicknesses between thick gate oxides and thin gate oxides. The availability of multiple different gate oxide thicknesses may provide designers flexibility, and enable designers to tailor transistors for efficient design and performance enhancement while reducing overall area.

Various embodiments disclosed herein relate to methods of manufacturing FinFETs including gate oxides of various different thicknesses. Rather than relying solely on the use of radical oxidation to form intermediate and thick gate oxides, which may result in degrading levels of fin consumption, various methods of manufacturing FinFETs disclosed herein may employ deposition processes such as atomic layer deposition (ALD) to form at least a portion of the oxide material of the thick and/or intermediate-thickness gate oxides. As a result, designers of electronic devices such as DRAM periphery circuitry may use FinFETs including gate oxides having intermediate-thickness that is more resilient to break down than thin gate oxide FinFETs, but that do not manifest performance degradation associated with thick gate oxide FinFETs. Even where thick gate oxide FinFETs are used, the use of at least some deposited oxide in such thick gate oxide FinFETs may result in less performance degradation than FinFETs that include gate oxides formed solely using radical oxidation, which consumes the material of the fins.

In some embodiments thicker gate oxide materials may be accompanied by lower fin heights than higher fin heights that may be accompanied by thinner gate oxide materials due to removal of a portion of shallow trench isolation (STI) oxide material from between fins during removal of excess gate oxide material of thinner gate oxide material FinFETs. As used herein, the term “fin height” refers to a height of active material of a fin in a FinFET that is overlapped with a gate material. Lower fin heights may result in poorer transistor performance than that of higher fin heights (e.g., because the effective gate width is less for lower fin heights than for higher fin heights). By contrast, the increased fin height of the thinner gate oxide material FinFETs may increase the effective gate width, leading to a performance boost without an accompanying area penalty.

In some embodiments FinFETs having three different gate oxides and three different fin heights may be used for CMOS circuitry (e.g., sense amplifier circuitry, buffer circuitry, decoder circuitry, word decoder circuitry, periphery circuitry, without limitation) in memory devices (e.g., DRAM devices, without limitation) may be used. By tuning a fin reveal process, fin height may be adjusted during removal of oxide from the fins by also removing oxide surrounding the fins. Accordingly, fin height may be increased in thin gate oxide and intermediate thickness gate oxide devices as compared to fin height of thicker gate oxide devices.

FIG.1is a perspective view of a portion of an apparatus100, according to some embodiments. The apparatus100includes first FinFETs102, second FinFETs104, and third FinFETs106. The first FinFETs102include a first gate oxide108including a first gate oxide material114, a second gate oxide material116, and a third gate oxide material118. The first FinFETs102also include first fins130including an active material. The first FinFETs102further include a work function metal124, which serves as a gate terminal to the first FinFETs102. Drain and/or source terminals of the first FinFETs102may be at portions of the first fins130that are not overlapped by the work function metal124(e.g., at spacers138). In some embodiments the first gate oxide material114is an in-situ steam generated (ISSG) oxide material (e.g., an ISSG silicon dioxide). In some embodiments the second gate oxide material116is an atomic layer deposition (ALD) oxide material (e.g., an ALD silicon dioxide). In some embodiments the third gate oxide material118of the first FinFETs102includes a high-k dielectric material122.

The second FinFETs104include a second gate oxide110including the second gate oxide material116and the third gate oxide material118. In some embodiments the third gate oxide material118of the second FinFETs104includes the high-k dielectric material122. The second FinFETs104are substantially free of the first gate oxide material114. The second FinFETs104also include second fins132including the active material. The second FinFETs104further include the work function metal124, which serves as a gate terminal to the second FinFETs104. Drain and/or source terminals of the second FinFETs104may be at portions of the second fins132that are not overlapped by the work function metal124(e.g., at spacers138).

The third FinFETs106include a third gate oxide112including the third gate oxide material118. The third FinFETs106are substantially free of the first gate oxide material114and the second gate oxide material116. The third gate oxide material118of the third FinFETs106includes an interfacial layer (IL) oxide material120and the high-k dielectric material122on the IL oxide material120. The third FinFETs106also include third fins134including the active material. The third FinFETs106further include the work function metal124, which serves as a gate terminal to the second FinFETs104. Drain and/or source terminals (not shown) of the third FinFETs106may be at portions of the third fins134that are not overlapped by the work function metal124(e.g., at spacers138).

The first gate oxide108of the first FinFETs102is thicker than the second gate oxide110of the second FinFETs104and the third gate oxide112of the third FinFETs106. Also, the second gate oxide110is thicker than the third gate oxide112, but is thinner than the first gate oxide108of the first FinFETs102. Since the first gate oxide108of the first FinFETs102is thicker than the second gate oxide110of the second FinFETs104and the third gate oxide112of the third FinFETs106, the first FinFETs102may be used for higher voltage potential operation than the second FinFETs104and the third FinFETs106. Also, since the third gate oxide112is thinner than the first gate oxide108of the first FinFETs102and the second gate oxide110of the second FinFETs104, the third FinFETs106may be used for lower voltage potential operation than the first FinFETs102and the second FinFETs104. Furthermore, since the second gate oxide110of the second FinFETs104is thinner than the first gate oxide108of the first FinFETs102but thicker than the third gate oxide112of the third FinFETs106, the second FinFETs104may be used for voltage potential operation that is between high voltage potential operation and low voltage potential operation.

The apparatus100also includes a semiconductor material128(e.g., silicon) over which the first FinFETs102, the second FinFETs104, and the third FinFETs106are formed. The first fins130, the second fins132, and the third fins134may be formed of this semiconductor material128. The first fins130, the second fins132, and the third fins134may be separated at their lower portions by a shallow trench isolation (STI) oxide136(e.g., silicon dioxide). A conductive material126, such as tungsten, may be formed on the first FinFETs102, the second fins132, and the third fins134(i.e., on the work function metal124). In some embodiments the work function metal124between the conductive material126and the third gate oxide material118may include both n-type and p-type work function metals. By way of non-limiting example, the n-type work function metal may include titanium nitride (TiN). Also by way of non-limiting example, the p-type work function metal may include titanium aluminide (TiAl).

In some embodiments an apparatus includes first FinFETs, second FinFETs, and third FinFETs. The first FinFETs include a first gate oxide material, a second gate oxide material, and a third gate oxide material. The second FinFETs include the second gate oxide material and the third gate oxide material. The second FinFETs are substantially free of the first gate oxide material. The third FinFETs include the third gate oxide material. The third FinFETs are substantially free of the first gate oxide material and the second gate oxide material.

FIG.2is a segment200of the perspective view ofFIG.1. As illustrated inFIG.2, a first fin height202of the first FinFETs102is less than a second fin height204of the second FinFETs104and a third fin height206of the third FinFETs106. Also, the second fin height204of the second FinFETs104is less than the third fin height206of the third FinFETs106. The first fin height202may be a height of a portion of the first fins130that is overlapped by the work function metal124. Similarly, the second fin height204may be a height of a portion of the second fins132that is overlapped by the work function metal124. Also, the third fin height206may be a height of a portion of the third fins134that is overlapped by the work function metal124.

Since the third fin height206of the third FinFETs106is greater than the first fin height202of the first FinFETs102and the second fin height204of the second FinFETs104, the third FinFETs106may have better performance than the first FinFETs102and the second FinFETs104. Also, since the second fin height204of the second FinFETs104is greater than the first fin height202of the first FinFETs102, the second FinFETs104may have better performance than the first FinFETs102. Furthermore, since the first fin height202of the first FinFETs102is less than the second fin height204of the second FinFETs104and the third fin height206of the third FinFETs106, the performance of the first FinFETs102may be inferior to that of the second FinFETs104and the third FinFETs106.

FIG.3Ais a flowchart illustrating a method300of manufacturing a semiconductor device (e.g., such as the apparatus100ofFIG.1), according to some embodiments.

FIG.3BthroughFIG.3Qare perspective views of a workpiece334illustrating the method300ofFIG.3A. Referring toFIGS.3A and3Btogether, at operation302the method300includes forming first fins130, second fins132, and third fins134of an active material. TheFIG.3Billustrates a semiconductor material128and first fins130, second fins132, and third fins134individually formed to extend from the semiconductor material128. By way of non-limiting example, photo resist336may be applied to portions of the semiconductor material128that will be formed into the fins, and then trenches338may be etched into the semiconductor material128to form the first fins130, the second fins132, and the third fins134.

Referring toFIGS.3A and3Ctogether, at operation304the method300includes filling a lower portion of the trenches338between the fins (e.g., the first fins130, the second fins132, and the third fins134) with insulative material (e.g., dielectric oxide material). The photo resist336(FIG.3B) may also be removed from the first fins130, the second fins132, and the third fins134(e.g., fin reveal).FIG.3Cillustrates an STI material136formed in the lower portions of the trenches338and the photo resist336(FIG.3B) removed from the first fins130, the second fins132, and the third fins134. In some embodiments filling the lower portion of the trenches338includes spinning on the STI material136. The STI material136may comprise insulative material, such as dielectric oxide material (e.g., as silicon dioxide, without limitation).

Referring toFIGS.3A and3Dtogether, at operation306the method300includes forming a first gate oxide material114(e.g., silicon dioxide) on the fins (e.g., the first fins130, the second fins132, and the third fins134).FIG.3Dillustrates the first fins130, the second fins132, and the third fins134with the first gate oxide material114formed thereon. In some embodiments forming the first gate oxide material114on the first fins130, the second fins132, and the third fins134includes forming an ISSG oxide material on the first fins130, the second fins132, and the third fins134(e.g., using an ISSG process). As a result, some of the active material of the first fins130, the second fins132, and the third fins134may be consumed to form the first gate oxide material114.

Referring toFIGS.3A and3Etogether, at operation308the method300includes forming a first photo resist material340over the first fins130. The first photo resist material340may be formed on portions of the first gate oxide material114overlying the first fins130.FIG.3Eillustrates the first photo resist material340formed to cover the first fins130, but not formed to cover the second fins132or the third fins134. The first photo resist material340is positioned over the first fins130to prevent removal of the first gate oxide material114overlying the first fins130. The first photo resist material340does not cover the second fins132and the third fins134. Accordingly, the first photo resist material340does not prevent removal of portions of the first gate oxide material114formed on the second fins132and the third fins134at operation310.

Referring toFIGS.3A and3Ftogether, at operation310the method300includes removing the first gate oxide material114from the second fins132and the third fins134. In some embodiments removing the first gate oxide material114from the second fins132and the third fins134includes removing the first gate oxide material114using a vapor etch process.FIG.3Fillustrates the second fins132and the third fins134having the first gate oxide material114removed therefrom. Because of the first photo resist material340on the first fins130, however, the first gate oxide material114remains on the first fins130.

In some embodiments removing the first gate oxide material114from the second fins132and the third fins134includes increasing, relative to a first fin height of the first fins130, a second fin height of the second fins132and a third fin height of the third fins134by removing a top portion of the STI material136between the second fins132and the third fins134.FIG.3Fillustrates that the top portion of the STI material136has been removed in the vicinity of the second fins132and the third fins134, but not in the vicinity of the first fins130. The top portion of the STI material136in the vicinity of the second fins132and the third fins134is removed because the first photo resist material340does not shield the STI material136from being etched. By contrast, the STI material136in the vicinity of the first fins130is not removed because the first photo resist material340shields the STI material136in the vicinity of the first fins130from being etched.

Referring toFIGS.3A and3Gtogether, at operation312the method300includes removing remaining portions of the first photo resist material340(FIG.3F) overlying the first fins130.FIG.3Gillustrates the workpiece334with the first photo resist material340(FIG.3F) removed from remaining portions of the first gate oxide material114covering the first fins130. The first gate oxide material114remains on the first fins130, but not on the second fins132or the third fins134.

Referring toFIGS.3A and3Htogether, at operation314the method300includes forming a second gate oxide material116on the first fins130, the second fins132, and the third fins134.FIG.3Hillustrates the first fins130, the second fins132, and the third fins134with the second gate oxide material116formed thereover. Forming the second gate oxide material116over the first fins130may include forming the second gate oxide material116on the first gate oxide material114on the first fins130. Forming the second gate oxide material116over the second fins132and the third fins134may include forming the second gate oxide material116on the second fins132and the third fins134.

In some embodiments forming the second gate oxide material116over the first fins130, the second fins132, and the third fins134includes forming dielectric oxide material over the first fins130, the second fins132, and the third fins134by way of an ALD process. Dielectric oxide material formed through an ALD process is referred to herein as “ALD oxide material.” Since an ALD oxide material is deposited without consuming active material of the fins (the first fins130, the second fins132, and the third fins134), the second gate oxide material116may not reduce dimensions (e.g., vertical dimensions, horizontal dimensions) of the second fins132and the third fins134. As a result, a relatively thick gate oxide (e.g., the first gate oxide108and the second gate oxide110ofFIG.1) may be achieved without undesirably removing portions of the active material of the second fins132and the third fins134.

Referring toFIGS.3A and3Itogether, at operation316the method300includes forming a sacrificial gate material342over the first fins130, the second fins132, and the third fins134.FIG.3Iillustrates the sacrificial gate material342formed on the second gate oxide material116overlying the first fins130, the second fins132, and the third fins134. In some embodiments forming the sacrificial gate material342over the first fins130, the second fins132, and the third fins134includes forming polysilicon material over the first fins130, the second fins132, and the third fins134. In some embodiments forming the sacrificial gate material342includes depositing polysilicon material and planarizing the polysilicon material (e.g., using a chemical mechanical planarization (CMP) process, without limitation).

Referring toFIGS.3A and3Jtogether, at operation318the method300includes forming spacers138in the sacrificial gate material342.FIG.3Jillustrates the sacrificial gate material342with the spacers138formed therein. In some embodiments forming the spacers138in the sacrificial gate material342includes forming trenches (e.g., substantially perpendicular to the trenches338ofFIG.3BandFIG.3Cthrough the sacrificial gate material342, the second gate oxide material116and the first gate oxide material114), forming spacers on lateral sides of the forming (e.g., epitaxially growing, without limitation) source and/or drain materials (e.g., epitaxial silicon phosphide (SiP) for NMOS transistors, epitaxial silicon germanium (SiGe) for PMOS transistors) on surfaces of the active material of the first fins130, the second fins132, and the third fins134, forming interlayer dielectric (ILD) material in the trenches to substantially fill remaining, unfilled portions of trenches, and planarizing the workpiece334(e.g., using CMP) to remove portions of the ILD material and the source and/or drain materials outside of the boundaries (e.g., vertical boundaries, horizontal boundaries) of the trenches to form the spacers138.

Referring toFIGS.3A and3Ktogether, at operation320the method300includes removing remaining portions of the sacrificial gate material342(FIG.3J).FIG.3Killustrates the workpiece334with the sacrificial gate material342(FIG.3J) removed from the second gate oxide material116. Removing the remaining portions of the sacrificial gate material342may expose portions of the second gate oxide material116previously covered by the remaining portions of the sacrificial gate material342at the end of operation318. The spacers138formed at operation318may remain as part of the workpiece334after the removal of the remaining portions of the sacrificial gate material342at operation320.

Referring toFIGS.3A and3Ltogether, at operation322the method300includes forming a second photo resist material344over the first fins130and the second fins132. The second photo resist material344may shield portions of the second gate oxide material116overlying the first fins130and the second fins132, as well as the STI material136in the vicinity of the first fins130and the second fins132, from being removed at operation324. The second photo resist material344may, however, leave additional portions of the second gate oxide material116overlying the third fins134exposed to facilitate subsequent removal of the additional portions of the second gate oxide material116on the third fins134, as well as upper portions of the STI material136in the vicinity of the third fins134.

Referring toFIGS.3A and3Mtogether, at operation324the method300includes removing the exposed portions of the second gate oxide material116covering the third fins134. By way of non-limiting example, the exposed portions of the second gate oxide material116may be removed using an etch process (e.g., a vapor etch process).FIG.3Millustrates the workpiece334with the second gate oxide material116removed from the third fins134.FIG.3Malso illustrates the first gate oxide material114and the second gate oxide material116remaining over the first fins130, as well as the second gate oxide material116remaining over the second fins132.

In some embodiments removing the exposed portions of the second gate oxide material116from the third fins134includes increasing, relative to a first fin height of the first fins130and a second fin height of the second fins132, a third fin height of the third fins134by removing a portion of a the STI material136between the third fins134. As was previously discussed with reference toFIG.3F, top portions of the STI material136in the vicinity of the second fins132and the third fins134were already removed at operation310. Accordingly, further removal of top portions of the STI material136in the vicinity of the third fins134at operation324may result in the third fin height of the third fins134being greater than the second fin height of the second fins132, which in turn may be greater than the first fin height of the first fins130, as illustrated inFIG.3M.

Referring toFIGS.3A and3Ntogether, at operation326the method300includes removing the second photo resist material344(FIG.3M).FIG.3Nillustrates the workpiece334with the second photo resist material344(FIG.3M) removed, so as to expose the portions of the second gate oxide material116and the spacers138previously covered thereby. As illustrated inFIG.3N, the second gate oxide material116on the first fins130and the second fins132may be exposed, as well as the third fins134and the STI material136in the vicinity of the third fins134.

Referring toFIGS.3A and3Otogether, at operation328the method300includes forming an IL oxide material120(e.g., silicon dioxide, without limitation) of a third gate oxide material118on the third fins134.FIG.3Oillustrates the third fins134with the IL oxide material120formed thereon. In some embodiments forming the IL oxide material120includes forming the IL oxide material120using a wet process chemical oxide. Accordingly, the IL oxide material120may be grown on the active material of the third fins134. Since the active material of the first fins130and the second fins132is covered by the second gate oxide material116, the IL oxide material120may not be formed over the first fins130and the second fins132. Also, if a wet process chemical oxide is used, the IL oxide material120may not grow on the spacers138. If a deposition processes (e.g., ALD) is instead used, the IL oxide material120may be deposited over the first fins130and the second fins132in addition to on the third fins134, and on the spacers138(unless deposition is blocked).

Referring toFIGS.3A and3Ptogether, at operation330the method300includes forming a high-k dielectric material122(e.g., hafnium oxide, without limitation) of the third gate oxide material118over the first fins130, the second fins132, and the third fins134. Accordingly, forming the third gate oxide material118over the first fins130, the second fins132, and the third fins134includes forming the IL oxide material120on at least the third fins134(operation328), and then forming the high-k dielectric material122over the first fins130, the second fins132, and the third fins134(operation330). As illustrated inFIG.3P, the high-k dielectric material122may be formed on the IL oxide material120, which was formed at operation328. In the vicinity of the first fins130and the second fins132the third gate oxide material118may include only the high-k dielectric material122. In the vicinity of the third fins134the third gate oxide material118may include both the IL oxide material120and the high-k dielectric material122. It is noted that in some embodiments formation of the high-k dielectric material122on the spacers138may be blocked.

FIG.3Pillustrates the first gate oxide material114, the second gate oxide material116, and the third gate oxide material118over the first fins130; the second gate oxide material116and the third gate oxide material118over the second fins132; and the third gate oxide material118over the third fins134. As a result, different gate oxide thicknesses may be achieved for the first fins130, the second fins132, and the third fins134according to embodiments disclosed herein.

Referring toFIGS.3A and3Qtogether, at operation332the method300includes forming one or more gate structures may formed of and including conductive material on the third gate oxide material118. An individual gate structure may include the work function metal124(e.g., both n-type and p-type work function metals such as titanium nitride (TiN) and titanium aluminide (TiAl), respectively, without limitation) and conductive material126(e.g., a relatively low electrical resistance material such as tungsten, without limitation) on or over the work function metal124.FIG.3Qillustrates the work function metal124and the conductive material126over the third gate oxide material118. A planarization process (e.g., CMP) may be used to planarize the conductive material126.

In some embodiments a method of manufacturing a semiconductor device includes forming a first gate oxide material on first fins for first fin field effect transistors (FinFETs), second fins for second FinFETs, and third fins for third FinFETs. The first fins, the second fins, and the third fins each include an active material. The method also includes removing the first gate oxide material from the second fins and the third fins, and forming a second gate oxide material on remaining portions of the first gate oxide material on the first fins, and on the second fins and the third fins. The method further includes removing the second gate oxide material from the third fins, and forming a third gate oxide material on remaining portions of second gate oxide material overlying the first fins and the second fins, and on the third fins.

FIG.4is a block diagram of a computing system400, according to some embodiments. The computing system400includes one or more processors404operably coupled to one or more memory devices402, one or more non-volatile data storage devices410, one or more input devices406, and one or more output devices408. In some embodiments the computing system400includes a personal computer (PC) such as a desktop computer, a laptop computer, a tablet computer, a mobile computer (e.g., a smartphone, a personal digital assistant (PDA), etc.), a network server, or other computer device.

In some embodiments the one or more processors404may include a central processing unit (CPU) or other processor configured to control the computing system400. In some embodiments the one or more memory devices402include random access memory (RAM), such as volatile data storage (e.g., dynamic RAM (DRAM), static RAM (SRAM), without limitation). In some embodiments the one or more non-volatile data storage devices410include a hard drive, a solid state drive, Flash memory, erasable programmable read only memory (EPROM), other non-volatile data storage devices, or any combination thereof. In some embodiments the one or more input devices406include a keyboard414, a pointing device418(e.g., a mouse, a track pad, without limitation), a microphone412, a keypad416, a scanner420, a camera428, other input devices, or any combination thereof. In some embodiments the output devices408include an electronic display422, a speaker426, a printer424, other output devices, or any combination thereof.

The memory devices402may include periphery circuitry430including the first FinFETs102, the second FinFETs104, and the third FinFETs106. The first FinFETs102include a first gate oxide (first gate oxide108ofFIG.1). The second FinFETs104include a second gate oxide (second gate oxide110ofFIG.1). The second gate oxide is thinner than the first gate oxide. The third FinFETs106include a third gate oxide (third gate oxide112ofFIG.1). The third gate oxide is thinner than the second gate oxide. By way of non-limiting example, complementary metal-oxide-semiconductor (CMOS) circuitry of the periphery circuitry430may be implemented using the second FinFETs104, which may strike a balance between resilience to transistor breakdown and device performance.

In some embodiments a computing system includes FinFETs including a first gate oxide, second FinFETs including a second gate oxide, and third FinFETs including a third gate oxide. The second gate oxide is thinner than the first gate oxide. The third gate oxide is thinner than the second gate oxide.

As used in the present disclosure, the term “combination” with reference to a plurality of elements may include a combination of all the elements or any of various different subcombinations of some of the elements. For example, the phrase “A, B, C, D, or combinations thereof” may refer to any one of A, B, C, or D; the combination of each of A, B, C, and D; and any subcombination of A, B, C, or D (e.g., A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D).

While the present disclosure has been described herein with respect to certain illustrated embodiments, those of ordinary skill in the art will recognize and appreciate that the present invention is not so limited. Rather, many additions, deletions, and modifications to the illustrated and described embodiments may be made without departing from the scope of the invention as hereinafter claimed along with their legal equivalents. In addition, features from one embodiment may be combined with features of another embodiment while still being encompassed within the scope of the invention as contemplated by the inventor.