Semiconductor device and manufacturing method of the same

A semiconductor device according to the present invention includes: a semiconductor substrate; a channel layer formed on the semiconductor substrate; a donor layer formed on the channel layer; a first Schottky layer formed on the donor layer; a second Schottky layer formed on the first Schottky layer; a first gate electrode formed on the first Schottky layer to form a Schottky barrier junction with the first Schottky layer; a first source electrode and a first drain electrode formed so as to sandwich the first gate electrode and electrically connected to the channel layer; a second gate electrode formed on the second Schottky layer and made of a material different from the first gate electrode to form a Schottky barrier junction with the second Schottky layer; and a second source electrode and a second drain electrode formed so as to sandwich the second gate electrode and electrically connected to the channel layer.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates to a semiconductor device and a manufacturing method of the same. In particular, the present invention relates to a semiconductor device in which two or more kinds of field-effect transistors having different threshold voltages are integrated on a compound semiconductor substrate, and to a manufacturing method of the same.

(2) Description of the Related Art

Field-effect transistors made of GaAs (hereinafter referred to as GaAsFET) formed on semiconductor substrates have been used as power amplifiers or switches of communication equipment such as mobile telephone terminals due to its high performance. Particularly, monolithic microwave integrated circuits in which active elements such as a GaAsFET and passive elements such as a resistance element and a capacitance element are integrated (hereinafter referred to as GaAsMMIC) have been widely and practically used.

In recent years, higher function and higher performance are required in the GaAsMMIC. In such a situation, it is desired to have a GaAsMMIC incorporating the power amplifier and the switch including a depression-mode FET (hereinafter referred to as D-FET) and a logic circuit including an enhancement-mode FET (hereinafter referred to as E-FET), that is, an E/D-FET in which the E-FET and the D-FET are mounted in a mixed manner on the identical substrate.

As a conventional E/D-FET, a semiconductor device described in Japanese Unexamined Patent Application Publication No. 8-116034 and a semiconductor device described in Japanese Unexamined Patent Application Publication No. 5-121451 have been known, for example.

Hereinafter, such a conventional E/D-FET is described. First, the conventional semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 8-116034 is described.

FIG. 1is a cross-sectional view showing a structure of the semiconductor device described in Japanese Unexamined Patent Application Publication No. 8-116034.

A semiconductor device400shown inFIG. 1includes an E-FET region41in which an E-FET is formed and a D-FET region42in which a D-FET is formed. The semiconductor device400includes a substrate401made of a semi-insulating GaAs, a buffer layer402, a channel layer403, a donor layer (also referred to as a donor supply layer)404, a threshold control layer405, an etching-stopper layer406, a contact layer407, an isolation region408, an insulating film409, a sidewall protection film412, gate electrodes413and414, and ohmic electrodes415.

The buffer layer402, made of undoped GaAs, is formed on the substrate401.

The channel layer403, made of undoped InGaAs, is formed on the buffer layer402.

The donor layer404, made of n-type AlGaAs, is formed on the channel layer403.

The threshold control layer405, made of n-type AlGaAs, is formed on the donor layer404.

The etching-stopper layer406, made of n-type AlGaAs, is formed on the threshold control layer405.

The contact layer407, made of n-type GaAs, is formed on the etching-stopper layer406.

The isolation region408is formed by ion implantation, which electrically isolates the E-FET region41from the D-FET region42.

The insulating film409is formed on the contact layer407.

The sidewall protection film412, made of SiO2, isolates the contact layer407from the gate electrode413or414.

The gate electrode413contacts the threshold control layer405and the etching-stopper layer406, and forms a Schottky barrier junction with the donor layer404.

The gate electrode414forms a Schottky barrier junction with the etching-stopper layer406.

The ohmic electrodes415are formed in openings formed in the insulating film409, each of which is electrically connected to the contact layer407.

Next, a method of manufacturing the conventional semiconductor device400is described.FIGS. 2 to 4are diagrams showing sectional structures in a manufacturing process of the semiconductor device400.

First, on the substrate401made of a semi-insulating GaAs, the GaAs buffer layer402, the InGaAs channel layer403, the AlGaAs donor layer404, the AlGaAs threshold control layer405, the AlGaAs etching-stopper layer406and the GaAs contact layer407are epitaxially grown sequentially by using the MOCVD method, the MBE method or the like. The isolation region408is formed by implanting boron ions by using a photoresist mask (not illustrated) to thereby form the E-FET region41and the D-FET region42(FIG. 2).

Next, the insulating film409made of SiO2is formed, and a predetermined region in the insulating film409is dry-etched selectively to the contact layer407by using a photoresist mask (not illustrated). Further, the GaAs contact layer407is dry-etched selectively to the etching-stopper layer406to thereby form the gate openings410and411. Further, an insulating film made of SiO2is formed and then etched back by dry etching, whereby the sidewall protection film412is formed (FIG. 3).

Next, the gateway opening411is covered with a photoresist mask (not illustrated), and the AlGaAs etching-stopper layer406in the gate opening410is wet-etched to thereby expose the AlGaAs threshold control layer405. The AlGaAs threshold control layer405is dry-etched selectively to the donor layer404. Further, the photoresist pattern is removed and WSi and W are laminated, and dry etching is performed on the laminated WSi and W other than a predetermined region by using a photoresist mask (not illustrated) to thereby simultaneously form the E-FET gate electrode413and the D-FET gate electrode414(FIG. 4).

Next, a predetermined region of the insulating film409is opened by using a photoresist mask (not illustrated), and the ohmic electrode415made of AuGeNi is formed by the vacuum evaporation and lift-off method. Through the steps described above, the structure of the conventional semiconductor device400shown inFIG. 1is formed.

Next, the conventional semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 5-121451 is described.

FIG. 5is a cross-sectional view showing a structure of the semiconductor device described in Japanese Unexamined Patent Application Publication No. 5-121451.

A semiconductor device500shown inFIG. 5includes an E-FET region51in which an E-FET is formed, and a D-FET region52in which a D-FET is formed. The semiconductor device500includes a substrate501made of semi-insulating GaAs, a channel layer502, a donor layer503, cap layers504,505and506, an isolation region507, an insulating film508, ohmic electrodes509, and gate electrodes512and513.

The channel layer502, made of undoped GaAs, is formed on the substrate501.

The donor layer503, made of n-type InGaP, is formed on the channel layer502. The thickness d1of the donor layer503of the E-FET region51is formed to be thinner compared with the thickness d2of the donor layer503of the D-FET region52.

The cap layer504, made of undoped GaAs, is formed on the donor layer503.

The cap layer505, made of n-type InGaP, is formed on the cap layer504.

The cap layer506, made of n-type GaAs, is formed on the cap layer505.

The isolation region507is formed by ion implantation, which electrically isolates the E-FET region51from the D-FET region52.

The insulating film508is formed on the cap layer506.

The ohmic electrodes509are formed in the openings formed in the insulating film508, each of which is electrically connected to the cap layer506.

The gate electrode512is formed in the opening formed in the insulating film508and the cap layers504to506of the E-FET region51, and forms a Schottky barrier junction with the donor layer503.

The gate electrode513is formed in the opening formed in the insulating film508and the cap layers504to506of the D-FET region52, and forms a Schottky barrier junction with the donor layer503.

Next, a method of manufacturing the semiconductor device500is described.FIGS. 6 and 7are diagrams showing sectional structures in a manufacturing process of the semiconductor device500.

First, on the substrate501made of semi-insulating GaAs, the GaAs channel layer502and the InGaP donor layer503are formed sequentially by using the MOCVD method or the MBE method. By using a photoresist mask (not illustrated), the thickness of a part in a predetermined region of the InGaP donor layer503is wet-etched. After removing the photoresist mask, the GaAs cap layer504, the InGaP cap layer505and the GaAs cap layer506are further formed sequentially. Further, the isolation region507is formed by implanting O2ions by using a photoresist mask (not illustrated) to thereby form the E-FET region51and the D-FET region52(FIG. 6).

Next, the insulating film508made of SiO2is formed, and a predetermined region is wet-etched selectively to the GaAs cap layer506by using a photoresist mask (not illustrated). Further, the ohmic electrodes509made of AuGe/Au, making an ohmic contact with the GaAs cap layer506, are formed by the vacuum evaporation and lift-off method (FIG. 7).

Next, a predetermined region of the insulating film508is wet-etched selectively to the GaAs cap layer506by using a photoresist mask (not illustrated) to thereby form gate openings for forming the gate electrodes512and513. The GaAs cap layer506in the gate opening is wet-etched selectively to the InGaP cap layer505to thereby expose the InGaP cap layer505. Next, the InGaP cap layer505is wet-etched selectively to the GaAs cap layer504to thereby expose the GaAs cap layer504. Next, the GaAs cap layer504is dry-etched selectively to the InGaP donor layer503to thereby expose the InGaP donor layer503. Further, the E-FET gate electrode512and the D-FET gate electrode513are formed by means of the vacuum evaporation and lift-off method using Ti/Pt/Au material. Through the steps described above, the structure of the semiconductor device500shown inFIG. 5is formed.

SUMMARY OF THE INVENTION

However, in a semiconductor device in which E/D-FET are mounted in a mixed manner on an identical substrate, the E-FET and the D-FET are used for different purposes, so required characteristics and accuracy are also different. As an element for determining the characteristics of an FET, a gate electrode material is important. Further, it is necessary to select a combination of a gate electrode material and a material of a semiconductor layer with which the gate electrode forms a Schottky barrier junction. In the semiconductor device400described in Japanese Unexamined Patent Application Publication No. 8-116034, as the gate electrodes of E-FET and D-FET, the gate electrodes414and415both of which are made of WSi/W are formed. With such a structure, the gate resistance increases, whereby the characteristics of the D-FET constituting a switch can not be sufficiently obtained particularly. Further, in the semiconductor device500described in Japanese Unexamined Patent Application Publication No. 5-121451, as the gate electrodes of the E-FET and the D-FET, the gate electrodes512and513both of which are made of Ti/Pt/Au are used. Further, as a semiconductor layer which forms a Schottky barrier junction with the gate electrodes512and513, the InGaP donor layer503is used. Since Ti/Pt/Au is used for the gate electrodes, an increase in the gate resistance of the D-FET can be reduced. However, each of the gate electrodes512and513forms a Schottky barrier junction with InGaP. With this structure, InGaP and Ti may react due to an effect of a process temperature, whereby the threshold voltage may fluctuate. In particular, in the E-FET, the controllability and the stability of the threshold voltage are important. If the threshold voltage fluctuates, the required characteristics can not be achieved, causing the yield to drop. That is, a conventional semiconductor device, in which E/D-FET are mounted in a mixed manner, can not be realized while achieving the characteristics required for both of the E-FET and the D-FET.

In view of the above, the present invention has been developed to solve the problems described above. It is therefore an object of the present invention to provide a semiconductor device and a manufacturing method of the same, capable of realizing the characteristics required for both of an E-FET and a D-FET.

In order to achieve the aforementioned object, the semiconductor device according to the present invention: a semiconductor substrate; a channel layer formed on the semiconductor substrate; a donor layer formed on the channel layer; a first Schottky layer formed on the donor layer; a second Schottky layer formed on the first Schottky layer; a first gate electrode formed on the first Schottky layer, the first gate electrode forming a Schottky barrier junction with the first Schottky layer; a first source electrode and a first drain electrode which are formed so as to sandwich the first gate electrode, and are electrically connected to the channel layer; a second gate electrode which is formed on the second Schottky layer, forming a Schottky barrier junction with the second Schottky layer, and made of a material different from the first gate electrode; and a second source electrode and a second drain electrode which are formed so as to sandwich the second gate electrode, and are electrically connected to the channel layer.

According to this structure, in the semiconductor device according to the present invention, the first gate electrode which is a gate electrode of the E-FET and the second gate electrode which is a gate electrode of the D-FET are made of different materials. Thereby, by using a material having less reactivity to the first Schottky layer caused by an effect such as a process temperature, as the material constituting the gate electrode of the E-FET, it is possible to improve the controllability and the stability of a threshold voltage required for the E-FET. Further, by using a material having low resistance as the material constituting the gate electrode of the D-FET, it is possible to reduce the gate resistance of the D-FET and to improve the characteristics. Thereby, the semiconductor device according to the present invention can realize the characteristics required for both of the E-FET and the D-FET.

Furthermore, it is possible that the semiconductor device includes a third electrode which is formed on the first gate electrode, and made of a material same as the second gate electrode.

According to this structure, even in the case of using a material having less reactivity caused due to an effect of a process temperature with the first Schottky layer and having a high resistance value, as the material constituting the gate electrode of the E-FET, the third electrode made of a material of low resistance can be laminated on the first gate electrode. In other words, it is possible to reduce an increase in gate resistance caused when the stability of a threshold voltage of the E-FET is improved. Further, the third gate electrode is simultaneously made of the identical material as the gate electrode of the D-FET. Therefore, in the case where the gate electrode of the E-FET has a two-layer structure, an increase in the process steps can be reduced. Namely, an increase in the process cost can be reduced.

Furthermore, it is possible that the first source electrode, the second source electrode, the first drain electrode, and the second drain electrode are made of a material same as the second gate electrode.

According to this structure, the source electrodes and the drain electrodes of the E-FET and the D-FET are simultaneously formed of the identical material as the gate electrode of the D-FET. Thereby, the process steps can be reduced. This enables to reduce the process cost.

Furthermore, it is possible that the first gate electrode is made of one of W, WSi and WSiN.

According to this structure, the first gate electrode is made of a material constituting the first Schottky layer (e.g., InGaP) and W, WSi, WSiN or the like which has less reactivity caused due to an effect of a process temperature or the like. Thereby, the controllability and the stability of a threshold voltage of the E-FET can be improved.

Furthermore, it is possible that the first Schottky layer is formed in at least a single layer, and a top layer thereof is made of InGaP.

According to this structure, the first Schottky layer is made of the material of the first gate electrode (e.g., WSiN) and InGaP having less reactivity caused due to an effect of a process temperature or the like. Thereby, the controllability and the stability of a threshold value of the E-FET can be improved.

Furthermore, it is possible that the second Schottky layer is formed in at least a single layer, and a bottom layer thereof is made of one of AlGaAs and GaAs. Furthermore, it is possible that the semiconductor substrate is made of one of GaAs and InP.

Furthermore, the manufacturing method of a semiconductor device according to the present invention is a manufacturing method of a semiconductor device including an enhancement-mode field-effect transistor and a depression-mode field-effect transistor, and includes: forming a channel layer on a semiconductor substrate; forming a donor layer on the channel layer; forming a first Schottky layer on the donor layer; forming a second Schottky layer on the first Schottky layer; forming a first opening for exposing the first Schottky layer, in the second Schottky layer; forming a first electrode in the first opening, the first electrode being a gate electrode of the enhancement-mode field-effect transistor and forming a Schottky barrier junction with the first Schottky layer; and forming a second electrode on the second Schottky layer, the second electrode forming a Schottky barrier junction with the second Schottky layer, being a gate electrode of the depression-mode field-effect transistor, and being made of a material different from the first gate electrode.

According to this structure, the first gate electrode which is the gate electrode of the E-FET and the second gate electrode which is the gate electrode of the D-FET are made of different materials. Thereby, by using a material having less reactivity to the first Schottky layer caused due to an effect such as a process temperature, as the material constituting the gate electrode of the E-FET, it is possible to improve the controllability and the stability of a threshold voltage required for the E-FET. Further, by using a material of low resistance as the material constituting the gate electrode of the D-FET, it is possible to reduce the gate resistance of the D-FET and to improve the characteristics. Thereby, the semiconductor device formed by the manufacturing method according to the present invention can realize the characteristics required for both of the E-FET and the D-FET.

Furthermore, in the forming of the second electrode, it is possible that the second gate electrode and a third gate electrode formed on the first gate electrode are formed simultaneously and made of an identical material.

According to this structure, even in the case of using a material having less reactivity caused due to an effect of a process temperature with the first Schottky layer and having a high resistance value, as the material constituting the gate electrode of the E-FET, the third electrode made of a material of low resistance can be laminated on the first gate electrode, whereby the total resistance value of the gate electrode can be reduced. In other words, it is possible to reduce an increase in gate resistance caused when the stability of a threshold voltage of the E-FET is improved. Further, the third gate electrode is simultaneously made of the identical material as the gate electrode of the D-FET. Therefore, an increase in the process steps in the case where the gate electrode of the E-FET has a two-layer structure can be reduced. Namely, an increase in the process cost can be reduced.

Furthermore, it is possible that in the forming of the second electrode, the second electrode, a first source electrode and a first drain electrode, and a second source electrode and a second drain electrode are simultaneously formed and made of an identical material, the first source electrode and the first drain electrode being formed so as to sandwich the first gate electrode and being electrically connected to the channel layer, and the second source electrode and the second drain electrode being formed so as to sandwich the second gate electrode and being electrically connected to the channel layer.

According to this structure, the source electrodes and the drain electrodes of the E-FET and the D-FET are simultaneously formed of the identical material as the gate electrode of the D-FET. Thereby, the process steps can be reduced. This enables to reduce the process cost.

The present invention is capable of providing a semiconductor device and a manufacturing method of the same in which the characteristics required for both of the E-FET and the D-FET can be realized.

The disclosure of Japanese Patent Application No. 2006-176429 filed on Jun. 27, 2006 including specification, drawings and claims is incorporated herein by reference in its entirety.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Hereinafter, a semiconductor device according to an embodiment of the present invention is described with reference to the drawings.

In a semiconductor device according to the embodiment of the present invention, a gate electrode of an E-FET and a gate electrode of a D-FET are made of different materials. This enables to improve the characteristics of the E-FET and the D-FET.

First, a structure of the semiconductor device according to the embodiment of the present invention is described.

FIG. 8is a cross sectional view showing the structure of the semiconductor device according to the embodiment of the present invention.

A semiconductor device100shown inFIG. 8includes an E-FET region11in which an E-FET is formed, and a D-FET region12in which a D-FET is formed. The semiconductor device100includes a substrate101which is a semiconductor substrate made of semi-insulating GaAs, an epitaxial layer110, an isolation region111, insulating films112and113, gate electrodes114,115aand115b, and ohmic electrodes115cand115d.

The epitaxial layer110is formed by crystal-growing a semiconductor layer on the substrate101. The epitaxial layer110includes buffer layers102and103, a channel layer104, a spacer layer105, a donor layer106, Schottky layers107and108, and a contact layer109.

The buffer layer102is formed on the substrate101. The buffer layer102is made of undoped GaAs with a thickness of 1 μm for example. The buffer layer103, made of undoped AlGaAs, is formed on the buffer layer102. The buffer layers102and103relax the lattice mismatching between the epitaxial layer110and the substrate101.

The channel layer104, made of undoped In0.2Ga0.8As with a thickness of 10 nm, is formed on the buffer layer103. The channel layer104is a layer in which carriers travel.

The spacer layer105, made of undoped AlGaAs with a thickness of 5 nm, is formed on the channel layer104.

The donor layer106is made of AlGaAs with a thickness of 10 nm in which Si that is an n-type impurity ion is doped, and is formed on the spacer layer105.

The Schottky layer107is formed on the donor layer106. The Schottky layer107includes two layers, that is, a threshold control layer107aand an etching-stopper layer107b. The threshold control layer107a, made of undoped AlGaAs with a thickness of 10 nm, is formed on the donor layer106. The etching-stopper layer107b, made of InGaP with a thickness of 5 nm, is formed on the threshold control layer107a.

The Schottky layer108, made of undoped AlGaAs with a thickness of 10 nm, is formed on the Schottky layer107. The Schottky layer108also serves as a threshold control layer.

The contact layer109is formed on the Schottky layer108. The contact layer109is divided into four regions, to each of which the ohmic electrode115cor115dis connected. The contact layer109includes a contact layer109aand a contact layer109b. The contact layer109a, made of n-type GaAs with a thickness of 50 nm, is formed on the Schottky layer108. The contact layer109b, made of n-type In GaAs with a thickness of 50 nm, is formed on the contact layer109a.

The isolation region111is formed by ion implantation, which electrically separates the E-FET region11and the D-FET region12.

The insulating film112, made of SiN for example, is formed on the epitaxial layer110and the isolation region111. The insulating film113, made of SiO2for example, is formed on the insulating film112.

The gate electrode114is formed so as to be embedded in the opening formed in the insulating films112and113and the Schottky layer108of the transistor region11. The gate electrode114is made of WSiN for example. The gate electrode114corresponds to the gate part of the E-FET, and forms a Schottky barrier junction with the etching-stopper layer107bof the Schottky layer107.

The gate electrode115ais formed so as to be embedded in the opening formed in the insulating films112and113of the transistor region12. The gate electrode115ais made of Ti/Al/Ti for example. The gate electrode115acorresponds to the gate part of the D-FET, and forms a Schottky barrier junction with the Schottky layer108.

The gate electrode115bis formed on the gate electrode114. The gate electrode115bis made of a material different from that of the gate electrode114. Further, the gate electrode115bis simultaneously formed of the identical material as that of the gate electrode115a. For example, the gate electrode115bis made of Ti/Al/Ti.

The ohmic electrodes115care a source electrode and a drain electrode of the E-FET, respectively, and are formed so as to sandwich the gate electrode114. Each of the ohmic electrodes115cis electrically connected to the channel layer104via the contact layer109, the Schottky layers107and108, the donor layer106and the spacer layer105. Each of the ohmic electrodes115cis formed so as to be embedded in the opening formed in the insulating films112and113of the transistor region11. The ohmic electrode115cmakes an ohmic contact with the contact layer109of the ohmic parts (drain part and source part) of the E-FET formed in the transistor region11.

The ohmic electrodes115dare a source electrode and a drain electrode of the D-FET, respectively, and are formed so as to sandwich the gate electrode115a. Each of the ohmic electrodes115dis electrically connected to the channel layer104via the contact layer109, the Schottky layers107and108, the donor layer106and the spacer layer105. Each of the ohmic electrodes115dis formed so as to be embedded in the opening formed in the insulating films112and113of the transistor region12. The ohmic electrode115dmakes an ohmic contact with the contact layer109of the ohmic parts (drain part and source part) of the D-FET formed in the transistor region12. Further, the ohmic electrodes115cand115dare simultaneously made of the identical material as that of the gate electrodes115aand115b. The ohmic electrodes115cand115dare made of Ti/Al/Ti for example.

Next, a method of manufacturing the semiconductor device100shown inFIG. 8is described.

FIGS. 9 to 15are diagrams showing sectional structures in the manufacturing process of the semiconductor device100.

First, the GaAs buffer layer102, the AlGaAs buffer layer103, the InGaAs channel layer104, the AlGaAs spacer layer105, the AlGaAs donor layer106, the AlGaAs threshold control layer107a, the InGaP etching-stopper layer107b, the AlGaAs Schottky layer108, the GaAs contact layer109aand the InGaAs contact layer109bare epitaxially grown sequentially on the substrate101made of a semi-insulating GaAs by using the MOCVD method or the MBE method. The entire area from the buffer layer102to the contact layer109each of which has been epitaxially grown is referred to as an epitaxial layer110. Further, the threshold control layer107aand the etching-stopper layer107bare collectively referred to as a Schottky layer107. Further, the contact layers109aand109bare collectively referred to as a contact layer109. Through the steps described above, the structure shown inFIG. 9is formed.

Next, the contact layer109other than a predetermined region is removed using a photoresist mask (not illustrated) to thereby form the E-FET region11and the D-FET region12. Further, in order to electrically isolate the E-FET region11from the D-FET region12, an isolation region111is formed by implanting boron ions for example. Through the steps described above, the structure shown inFIG. 10is formed.

Next, the contact layer109other than a predetermined region is removed in the E-FET region11and the D-FET region12by using a photoresist mask (not illustrated) to thereby form the ohmic contact region11ain the E-FET region11and the ohmic contact region12aof the D-FET region12. For example, the contact layer109is removed by dry etching using a mixed gas of SiCl4/SF6/N2for example. Through the steps described above, the structure shown inFIG. 11is formed.

Next, the insulating film112made of SiN and the insulating film113made of SiO2are formed. Through the step, the structure shown inFIG. 12is formed.

Next, predetermined regions respectively in the insulating films112and113within the E-FET region11are dry-etched selectively to the AlGaAs threshold control layer108, by using a photoresist mask (not illustrated). For example, dry etching using a mixed gas of CHF3/SF6is performed. Next, the AlGaAs threshold control layer108is selectively wet-etched to the InGaP etching-stopper layer107bformed underneath thereof, by using a mixed liquid of phosphoric acid, hydrogen peroxide solution and water. Thereby, the gate opening11bfor exposing the Schottky layer107of the E-FET region11is formed. Through the steps described above, the structure shown inFIG. 13is formed.

Next, WSiN, for example, is sputtered all over the surface and dry etching is performed on the WSiN other than a predetermined region by using a photoresist mask (not illustrated) to thereby form the gate electrode114. For example, dry etching using a mixed gas of Cl2/O2is performed. Through the steps described above, the structure shown inFIG. 14is formed.

Next, predetermined regions respectively in the insulating films112and113within the E-FET region11and the D-FET region12are dry-etched selectively to the AlGaAs threshold control layer108and the InGaAs contact layer109bwhich are formed underneath thereof, by using a photoresist mask (not illustrated). For example, dry etching using a mixed gas of CHF3/SF6is performed. Thereby, the ohmic opening11cof the E-FET region11, the gate opening12bof the D-FET region12, and the ohmic opening12cof the D-FET region12are formed. Through the steps described above, the structure shown inFIG. 15is formed.

Next, Ti/Al/Ti, for example, is evaporated all over the surface, and dry etching is performed by using a photoresist mask (not illustrated) to thereby form the gate electrode115blaminated on the gate electrode114in the E-FET region11, the ohmic electrodes115cformed in the E-FET region11, and the gate electrode115aof the D-FET region12, and the ohmic electrodes115din the D-FET region12. For example, dry etching using a mixed gas of Cl2/BCl3is performed. Through the steps described above, the structure of the semiconductor device100shown inFIG. 8is formed.

Through the steps described above, in the semiconductor device100according to the present embodiment, the gate electrodes of the E-FET and the D-FET are made of different electrode materials. Thereby, it is possible to satisfy the characteristics required for the E-FET and the D-FET, respectively. Specifically, the gate electrode of the D-FET is made of an electrode material having low resistance such as Ti/Al/Ti, whereby the gate resistance of the D-FET can be reduced, enabling to improve the characteristics of the D-FET. If Ti/Al/Ti is also used as the electrode material of the gate electrode of the E-FET, InGaP constituting the etching-stopper layer107band Ti constituting the gate electrode may react due to an effect of a process temperature so as to cause the threshold voltage of the E-FET to fluctuate. Particularly, for the E-FET, controllability and stability of the threshold voltage are important. If the threshold voltage fluctuates, the required characteristics may not be obtained, causing the yield to drop. On the other hand, in the semiconductor device100according to the present embodiment, an electrode material which is less reactive to InGaP, such as WSiN, is used for the gate electrode114. Thereby, the controllability and stability of the threshold voltage of the E-FET can be improved. Therefore, the yield of the semiconductor device100can be improved.

Further, in the semiconductor device100according to the present invention, the gate electrode115bis laminated on the gate electrode114of the E-FET. Thereby, even in the case where WSiN or the like having higher resistance value than Ti/Al/Ti or the like, which is the electrode material of the gate electrode115aand the like of the D-FET, is used as the electrode material of the gate electrode114of the E-FET, the total gate resistance of the E-FET can be reduced. This can improve the characteristics of the E-FET.

Further, in the semiconductor device100according to the present invention, all ohmic electrodes115cand115dof the E-FET and the D-FET are formed simultaneously when the gate electrode115aof the D-FET is formed. Further, the gate electrode115bis laminated on the gate electrode114of the E-FET simultaneously as the gate electrode115aand the ohmic electrodes115cand115d. Therefore, it is possible to prevent an increase in the process steps which may be caused by improving the capacity and realizing stable accuracy. Further, since the identical material can be used, simple and inexpensive processing can be realized.

Further, in the semiconductor device100according to the present invention, the ohmic electrodes115cof the E-FET and the ohmic electrodes115dof the D-FET are made of an electrode material having low resistance such as Ti/Al/Ti. Therefore, it is possible to reduce the source resistance and the drain resistance of the E-FET and the D-FET to thereby improve the characteristics of the E-FET and the D-FET.

The semiconductor device and the method of manufacturing thereof according to the embodiment of the present invention have been described above. However, the present invention is not limited to this embodiment.

For example, although a gate electrode having a two-layer structure is used in the E-FET in the above description, it is also acceptable to only use the gate electrode114made of WSiN or the like.

Further, although the gate electrode114is made of WSiN in the above description, the material is not limited to this, provided that it is a material having low reactivity to the material constituting the etching-stopper layer107b(InGaP in the above example) and is capable of increasing the controllability of the threshold voltage of the E-FET. For example, the gate electrode114may be made of W or WSi.

Further, in the description above, the gate electrode115aof the D-FET, the gate electrode115bof the second layer of the E-FET, the ohmic electrodes115cof the E-FET, and the ohmic electrodes of the D-FET are made of Ti/Al/Ti, but the material is not limited to this. Any electrode material having low resistance is acceptable. For example, the gate electrode115aof the D-FET, the gate electrode115bof the second layer of the E-FET, the ohmic electrodes115cof the E-FET, and the ohmic electrodes of the D-FET may be made of Ti/Pt/Au.

Further, in the description above, the Schottky layer108is made of AlGaAs, but it may be made of GaAs or the like. Further, although the semiconductor substrate101is a GaAs substrate in the description above, it may be a compound semiconductor substrate such as an InP substrate.

INDUSTRIAL APPLICABILITY

The present invention is applicable to a semiconductor device and a manufacturing method of the same. Particularly, it is applicable to GaAsMMIC in which an E-FET and a D-FET are integrated. Further, the present invention is applicable to a communication equipment using GaAsMMIC. Particularly, it is applicable to a power amplifier, a switch and the like of a mobile telephone terminal and the like.