Method and apparatus for graphics processing using state and shader management

A method and apparatus for graphics processing using state and shader management includes at least one state and shader cache coupled to a compiler for compiling a hardware state and shader vector from an abstract state vector. Also included is an abstract state vector register containing the abstract state vector that is provided to the state and shader cache and the compiler. The state and shader cache receives the abstract state vector and determines whether a cache entry for that abstract state vector already exists. If the cache entry exists, the hardware state and shader vector is provided to hardware. If the entry does not exist, the state and shader cache provides a miss signal to the compiler, whereupon the compiler compiles the abstract state vector and generates a hardware state and shader vector. Thereupon the hardware state and shader vector is provided to the hardware.

FIELD OF THE INVENTION

The invention relates generally to graphics processing and more particularly to the utilization of state and shader management in graphics processing.

BACKGROUND OF THE INVENTION

When processing graphics for visual display, prior to rendering the graphics, the system receives and must compile new vector inputs. This process can be a time consuming step, due to the amount of information which must be compiled. Once all of the input vector information is compiled, a hardware state and shader vector is created and then provided to a graphics processor. The graphics processor utilizes the state and shader vector to produce a visual output.

This graphics processing system can be extremely inefficient when a large input vector needs to be compiled and provided to the processor. Furthermore, to increase optimization for the best performance of the graphics processor, the compiler may require a long compile time to properly compile the large input vector.

In conventional processing systems, it is not uncommon to have the compiler recompiling commonly occurring large input vectors. Recompilation of the same input vector is redundant and wasteful.

FIG. 1illustrates how a hardware state and shader vector100is generated by a compiler102in accordance with the prior art system. The compiler102receives an abstract state vector, shown generally at104, which consists of an abstract render state106, vertex shader programs108, vertex shader constants110, pixel shader programs112and pixel shader constants114. The abstract state vector104is thereupon provided to the compiler102where the compiler compiles the input information, in accordance with well-known compiler techniques. Once the abstract state vector104has been compiled by the compiler102, thereby generating a hardware state and shader vector100, the hardware state and shader vector100is provided to a hardware116, such as graphics processor or any other suitable hardware as recognized by one skilled in the art.

The compilation process illustrated inFIG. 1must be executed for every hardware state and shader vector to be provided to the hardware. When the compiler102must recompile the abstract state vector104, this creates an inefficient graphics pre-processing system. Therefore, there currently exists a need for an improved graphics processing unit using state and shader management of hardware state and shader vectors.

The disclosed invention is an apparatus and method for graphics processing including providing an abstract state vector to a state and shader cache and determining if a cache entry exists within the state and shader cache for the abstract state vector, wherein the cache entry contains a hardware state and shader vector. If the cache entry exists, the hardware state and shader vector which is within the cache entry is provided to a graphics processor. Also, when the abstract state vector is provided to the state and shader cache, it is also provided to a compiler. Therefore, if the cache entry does not exist in the hardware state and shader vector, the compiler compiles the abstract state vector to thereupon produce the hardware state and shader vector. The state and shader cache generates a cache entry for the abstract state vector which was not contained therein and when the compiler has completed the compilation process, the hardware state and shader vector is written to the state and shader cache in the data entry having the abstract state vector. Thereupon, the state and shader cache provides the hardware state and shader vector to the graphics processor.

The abstract state vector is comprised of a vertex shader intermediate form, vertex shader constants, pixel shader intermediate form, pixel shader constants, and abstract render state. The cache entry within the state and shader cache is comprised of the abstract state vector and the hardware state and shader vector.

FIG. 2illustrates a graphic processor using state and shader management in accordance with one embodiment of the present invention. The processing system120uses a data register122to hold an abstract state vector. As recognized by one skilled in the art, the abstract state vector may be provided directly from another application or other source, but has been illustrated in a data register for clarity purposes only. The processing system120further contains a state and shader cache124and a compiler126. The state and shader cache124contains a plurality of cache entries, such as127, which contain an abstract state vector and a hardware state and shader vector.

The abstract state vector122is provided to the state and shader cache124and the compiler126via connection128. The state and shader cache124is further operably coupled with the compiler126via connection130, wherein the state and shader cache124can provide the compiler126an indication when a miss has occurred. Furthermore, the compiler126is coupled to the state and shader cache124via connection132, whereupon the compiler126can provide the compilation output to the state and shader cache124. The state and shader cache124is further operably coupled to a hardware134via connection136, wherein the state and shader cache124provides the hardware state and shader vector to the hardware134. In one embodiment, the hardware may be a graphics processor134or any other suitable hardware device capable of recognizing or transferring the hardware state and shader vector.

FIG. 3illustrates the graphics processor120ofFIG. 2providing a greater level of detail regarding the compiler126and where the abstract state vector, stored in the register122, is derived. In graphics processing, the flow of input data is provided into the compiler to be provided to the hardware, where the input contains specific vertex and pixel information. Vertex shader information140is provided into the compiler and so is pixel shader142information. In one embodiment, this shader information is processed not only directly into the compiler, but also through an optimizer144. Whereupon, in conjunction with abstract render state146, the abstract state vector is a compilation of a vertex shader intermediate form, which is the output of the vertex shader optimization, and vertex shader constants which were not a part of the optimization, and pixel shader intermediate form, the output of the pixel shader optimization, and pixel shader constants. Thereupon, the abstract state vector contained within the register122contains a vertex shader intermediate form, vertex shader constants, pixel shader intermediate form, pixel shader constants, and abstract render state. The compiler126utilizes all of this information to assemble and compile the hardware state and shader vector which is thereupon provided to the hardware134.

Also illustrated inFIG. 3, the compiler126is further comprised of a shader assembler148and a compiler150. The shader assembler receives the abstract state vector whereupon an intermediate form for the vertex shader and an intermediate form for the pixel shader is created by combining the input intermediate forms with the abstract render state. As illustrated inFIG. 3, the new vertex shader intermediate form created by the shader assembler148is provided to the compiler150via connection152and the new pixel shader intermediate form created by the shader assembler148is provided to the compiler150via connection154. The compiler150thereupon executes the compilation in accordance with well-known techniques and thereby generates a vertex shader for the hardware158and a pixel shader for the hardware160. The shader assembler148further provides a plurality of register writes162. As illustrated inFIG. 2, the compiler126provides the compiler150and shader assembler162output to the state and shader cache124via connection132. Thereupon, the state and shader cache124can provide the hardware state and shader vector to the hardware134via the connection136.

FIG. 4illustrates the steps of state and shader management in graphics processing in accordance with one embodiment of the present invention, more specifically, in accordance with the system illustrated inFIGS. 2 and 3. The process begins, step200, by providing an abstract state vector to the state and shader cache124and the compiler126, shown at step202. As discussed above and as illustrated in the register122, the abstract state vector is comprised of a vertex shader intermediate form, vertex shader constants, pixel shader intermediate form, pixel shader constants, and abstract render state, shown at204.

The next step,206, is determining if a cache entry127exists within the state and shader cache124for the abstract state vector. As illustrated inFIGS. 2 and 3, the cache entry127within the state and shader cache124is comprised of the abstract state vector and the hardware state and shader vector, designated at208. If the cache entry for the abstract state vector does not exist, the next step is providing a miss signal to the compiler, designated at210. The miss signal is simply an indicator that the state and shader cache124does not contain the appropriate cache entry for the abstract state vector. The shader assembler148receives the miss signal and thereupon must compile the received abstract state vector. Therefore, the next step is compiling the abstract state vector to produce the hardware state and shader vector which is not currently stored in the state and shader cache124, designated at step212. The next step is generating a cache entry127for the abstract state vector within the state and shader cache124. Thereupon, when the compiler has completed the compilation process, the next step216is writing the hardware state and shader vector to the state and shader cache.

Once the cache entry127has been completed, the hardware state and shader data within the cache entry127is provided to a graphics processor, such as the hardware134shown generally inFIGS. 2 and 3, designated at step218. Furthermore, looking back up at step206where the determination was made if the cache entry exists, should it be determined that a cache entry does in fact exist within the state and shader cache, step218is re-executed and the hardware state and shader vector is provided to the graphics processor.

Thereupon, the graphics processor ofFIGS. 2 and 3, in accordance with the method inFIG. 4, illustrates efficient graphics processing through using state and shader management. When the compiler has already compiled the same abstract state vector, the state and shader cache simply provides the hardware state and shader vector to the hardware, instead of having to delay processing speed to recompile the abstract state vector.

Moreover, it is also important for the state and shader cache to quickly and efficiently determine whether or not the abstract state vector has already been compiled and there is a cache entry containing the hardware state and shader vector. In one embodiment, a sub-vector approach is utilized to quickly and efficiently compare received abstract state vectors and compare them with abstract state vectors stored in the state and shader cache.

FIG. 5illustrates representation of an abstract state vector, shown generally at230which is composed of a plurality of abstract state sub-vectors,232. Illustrated inFIG. 5, the abstract state vector230is composed of eight abstract sub-vectors232, abstract state sub-vector A through abstract state sub-vector H is for illustration purposes only and is not herein so limiting. As recognized by one skilled in the art, the abstract state vector may be parsed into as many abstract state sub-vectors as required to efficiently determine whether a cache entry exists for the abstract state vector230. Extracted from the abstract state sub-vectors232are a plurality of indices234, which represent each of the abstract state sub-vectors232.

Concurrent with the abstract state sub-vector index234, an array of the abstract state sub-vectors236, wherein the abstract state sub-vector data is stored therein, is created. Each abstract state sub-vector index234, looks up the corresponding abstract state sub-vector data236in that array. An array of state and shader hardware vectors238is created and data is added to this array each time the compiler is run. The combination of all indices234is used to index or address the array of state and shader hardware vectors238. The combination of the indices234to create an addressing key may be a concatenation of the indices, a hash function or other method apparent to one of ordinary skill in the art. Thereupon, an array of the state and shader vectors is created wherein it is addressed by composite index, specifically the index A through H,234.

If all of the abstract state sub-vectors are found, the next step is searching for a composite index in an array of composite indices and hardware state and shader vectors, step246. Designated at248if the composite index is found, it is determined that a cache entry exists, designated at250. If an abstract state sub-vector is not found, step244or the composite index is not found in the array of composite indices248, it is determined that a cache entry does not exist, step252. Thereupon the state and shader cache can make a determination whether to send a miss signal to the compiler, step254.

It should be understood that the implementation of other variations and modifications of the invention and its various aspects will be apparent to those of ordinary skill in the art, and that the invention is not limited by the specific embodiments described herein. For example, the state and shader cache may contain more information beyond the abstract state vector, the hardware state and shader vector for each individual cache entry, as may be used by the hardware connected to the state and shader cache. It is therefore contemplated to cover by the present invention, any and all modifications, variations, or equivalents that fall within the spirit and scope of the basic underlying principles disclosed and claimed herein.