Circuit board assembly and packaged integrated circuit device with power and ground channels

A packaged integrated circuit device and a circuit board assembly are disclosed that include a semiconductor die and a package substrate that includes a first grid array of contact pads that are electrically coupled to corresponding contact pads on the semiconductor die. The first grid array of contact pads includes a first set of adjacent rows or columns of contact pads that are coupled to a first channel that extends within a ground plane of the package substrate. The first grid array of contact pads includes a second set of adjacent rows or columns of contact pads that are electrically coupled to a second channel that extends within a power plane of the package substrate. The contact pads in the first set of adjacent rows or columns of contact pads directly overlie a portion of the first channel and the contact pads in the second set of adjacent rows or columns of contact pads directly overlie a portion of the second channel. A circuit board assembly is disclosed that includes a first grid array of contact pads disposed on a top side of a circuit board. The circuit board includes a first channel that extends within a ground plane of the circuit board and a second channel that extends within a power plane of the circuit board. The circuit board assembly can include decoupling capacitors disposed on the top side of the circuit board and the packaged integrated circuit device can include decoupling capacitors attached to the top of the package substrate.

BACKGROUND

Conventional flip-chip integrated circuit devices include a grid array of contact pads for electrically and mechanically connecting the flip-chip integrated circuit device to external circuitry. Typically, the contact pads in the array are arranged such that power and ground contact pads are located near the center of the array. Data pins are typically located in various locations throughout the array and are located around the periphery of the array.

This conventional “pin-out” arrangement works well for grid array patterns having 1 millimeter pitch or greater and intermediate frequency integrated circuit devices. However, with high frequency and high current integrated circuit devices and smaller pitch grid arrays, this conventional package substrate design may not provide adequate power and ground connectivity for the integrated circuit device to properly function.

More particularly, openings within power planes and ground planes in the package substrate and in the circuit board allow vias to connect to underlying structures. This significantly reduces the contiguous surface area of the ground plane and the power plane under the flip-chip. In addition, vias in the package substrate that connect to signal pins and some vias in the circuit board that connect to signal pins must pass through both the ground plane and the power plane. Isolation rings extend around these microvias to prevent noise that can disrupt the data signals. Though the isolation rings are effective for noise reduction, they further reduce the size of the ground plane and the size of the power plane.

As a result of the aforementioned reduction in surface area of power and ground planes under the flip-chip, in packages having a high pin count and small-pitch there may not be enough contiguous power plane area and ground plane area to effectively couple power and ground to the integrated circuit device. Moreover, the reduced surface area increases the impedance of the interconnect path. This increased impedance can render the flip-chip integrated circuit device inoperable in high frequency, high current applications.

Accordingly, there is a need for a method and apparatus that will allow for effectively coupling power and ground to flip-chip integrated circuit devices.

SUMMARY

An integrated circuit device is disclosed that includes a grid array of contact pads, where some of the contact pads for coupling power are arranged in a first set of adjacent rows or columns of contact pads and some of the contact pads for coupling ground are arranged in a second set of adjacent rows or columns of contact pads. This provides sufficient contiguous surface area in the power plane and in the ground plane to effectively couple power and ground to the semiconductor die.

A packaged integrated circuit device is disclosed that includes a semiconductor die and a package substrate that includes a first grid array of contact pads that are electrically coupled to corresponding contact pads on the semiconductor die. The first grid array of contact pads includes a first set of adjacent rows or columns of contact pads that are coupled to a first channel that extends within a ground plane of the package substrate. The first grid array of contact pads includes a second set of adjacent rows or columns of contact pads that are electrically coupled to a second channel that extends within a power plane of the package substrate. The contact pads in the first set of adjacent rows or columns of contact pads directly overlie a portion of the first channel and the contact pads in the second set of adjacent rows or columns of contact pads directly overlie a portion of the second channel.

In one embodiment the packaged integrated circuit device includes a plurality of decoupling capacitors that are disposed on the same side of the package substrate as the semiconductor die, wherein each of the decoupling capacitors are electrically coupled to the first channel and to the second channel.

A circuit board assembly is disclosed that includes a first grid array of contact pads disposed on a top side of the circuit board. This first grid array of contact pads includes a first set of adjacent rows or columns of contact pads that are coupled to a first channel that extends within a ground plane of the circuit board and a second set of adjacent rows or columns of contact pads that are coupled to a second channel that extends within a power plane of the circuit board. The contact pads in the first set of adjacent rows or columns of contact pads directly overlie a portion of the first channel and the contact pads in the second set of adjacent rows or columns of contact pads directly overlie a portion of the second channel. The circuit board assembly also includes a plurality of decoupling capacitors disposed on the top side of the circuit board. Each of the plurality of decoupling capacitors extend directly over a portion of the first channel and directly over a portion of the second channel, and each of the plurality of decoupling capacitors are electrically coupled to the first channel and electrically coupled to the second channel.

The use of adjacent rows or columns that consist entirely of contact pads for coupling power to the integrated circuit device provides for a contiguous channel in each power plane that extends completely across each array of contact pads. Similarly, the use of adjacent rows or columns that consist entirely of contact pads for coupling ground to the integrated circuit device provides for a contiguous channel in the ground plane that extends completely across each array of contact pads. The channels in the ground plane and the power plane lower the impedance of the package substrate, providing low impedance pathways for coupling power and ground to the integrated circuit device. Moreover, embodiments of the present invention that include decoupling capacitors provide sufficient capacitance to power high frequency and high current integrated circuit devices such as content addressable memory devices. These and other advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments, which are illustrated in the various drawing figures.

DETAILED DESCRIPTION

FIGS. 1-3show a package substrate3that includes a grid array of contact pads2. Grid array of contact pads2includes a first set of adjacent rows of contact pads15that are coupled to a first channel45that extends within a ground plane7of package substrate3. Grid array of contact pads2includes a second set of adjacent rows of contact pads16that are electrically coupled to a second channel46that extends within a power plane8of the package substrate3. The contact pads in first grid array of contact pads15directly overlie a portion of the first channel45and the contact pads in the second grid array of contact pads16directly overlie a portion of the second channel46.

In order to more clearly show the concepts of the present invention, only 14 rows (rows31-44) and 14 columns are illustrated in the Figures. However, integrated grid array of contact pads2and grid array of contact pads4will include many more rows and columns. In addition, the number of rows may not be the same as the number of columns. Also, the number of rows and columns on grid array of contact pads2may not be the same as on grid array of contact pads4.

First set of rows of contact pads15includes all of the contact pads in row34, all of the contact pads in adjacent row of contact pads35and all of the contact pads in adjacent row of contact pads36. In this embodiment, first set of rows of contact pads15includes three rows. However, it is appreciated that first set of rows of contact pads15can include only two rows or can include more rows, where each row is adjacent to another row in first set of rows of contact pads15.

Second set of rows of contact pads16includes all of the contact pads in row37, all of the contact pads in row38, and all of the contact pads in row39. Each row of contact pads37-39is adjacent to another row in second set of rows of contact pads16. More particularly, row of contact pads37is adjacent to row of contact pads38and row of contact pads38is adjacent to row of contact pads39. In this embodiment, second set of rows of contact pads16includes three rows. However, alternatively, second set of rows of contact pads16can include only two rows or can include more than three rows, where each row is adjacent to another row in second set of rows of contact pads16.

Referring now toFIGS. 2-3, a second grid array of contact pads4is disposed on the opposite side of package substrate3from the first grid array of contact pads2. Second grid array of contact pads4includes a third set of adjacent rows of contact pads25that are coupled to first channel45and a fourth set of adjacent rows of contact pads26that are electrically coupled to second channel46. Third set of adjacent rows of contact pads25directly underlie a portion of first channel45and fourth set of adjacent rows of contact pads26directly underlie a portion of second channel46.

Third set of adjacent rows of contact pads25includes all of the contact pads in rows85-86. Each row85-86is adjacent to another row in third set of adjacent rows of contact pads25since row of contact pads85is adjacent to row of contact pads86. Fourth set of adjacent rows of contact pads26includes all of the contact pads in rows87-89. Each row87-89is adjacent to another row in second set of adjacent rows of contact pads26. More particularly, row of contact pads87is adjacent to row of contact pads88and row of contact pads88is adjacent to row of contact pads89.

Decoupling capacitors11-12are disposed on the top side of package substrate3. Each of decoupling capacitors11-12is electrically coupled to first channel45and to second channel46. In the present embodiment, each decoupling capacitor11-12is a discrete device that extends directly over a portion of first channel45and directly over a portion of second channel46. Decoupling capacitor11extends proximate one end of first channel45and second channel46, and decoupling capacitor12extends proximate the opposite end of the channel45and second channel46.

In the present embodiment first grid array of contact pads2includes a fifth set of adjacent rows of contact pads17that are electrically coupled to a third channel47that extends within ground plane7of package substrate3. Fifth set of rows of contact pads17includes all of the contact pads2in adjacent rows40-42.

Second grid array of contact pads4includes a sixth set of adjacent rows or rows of contact pads27that directly underlie a portion of third channel47. Each of contacts4in sixth set of adjacent rows of contact pads27is electrically coupled to third channel47. Sixth set of adjacent rows of contact pads27includes all of the contact pads4in rows90-91.

Additional decoupling capacitors13-14are electrically coupled to second channel46and to third channel47. In the present embodiment, each of additional decoupling capacitors13-14is a discrete device that extends directly over a portion of second channel46and directly over a portion of third channel47.

In the present embodiment vias60attach to contact pads in row34, vias61attach to contact pads2in row35, vias62attach to contact pads2in row36, vias63attach to contact pads2in row37, vias64attach to contact pads2in row38, vias65attach to contact pads2in row39, vias66attach to contact pads2in row40, vias67attach to contact pads2in row41, vias68attach to contact pads2in row42, vias71attach to contact pads4in row85, vias72attach to contact pads4in row86, vias73attach to contact pads4in row87, vias74attach to contact pads4in row88, vias75attach to contact pads4in row89, vias76attach to contact pads4in row90and vias77attach to contact pads4in row91. Each via60-62and71-72contacts channel45, with vias71-72extending through openings in power plane8. Each via63-65and73-75contacts channel46, with vias63-65extending through openings in ground plane7. Similarly, each via66-68and76-77contacts channel47, with vias76-77extending through openings in power plane8.

Package substrate3can be formed by integrating layers of dielectric and conductive material, and patterning top and bottom conductive layers to form grid array of contact pads2and grid array of contact pads4. Alternatively, grid array of contact pads2and4can be formed by selective deposition of a conductive material such as metal on the top surface of package substrate3. Vias60-68and71-77can be formed by etching or drilling openings, and filing the openings with conductive material. In the present embodiment, dielectric material extends within ground plane7and power plane8to electrically isolate vias63-65from ground plane7, and to electrically isolate vias71-72and76-77from power plane8.

FIGS. 4-6show a packaged integrated circuit device10that is formed by coupling a semiconductor die1to package substrate3. Solder bumps5electrically and mechanically couple semiconductor die1to package substrate3. In the present embodiment grid array of contact pads2corresponds to a grid array of contact pads on semiconductor die1. More particularly, in the present embodiment, grid array of contact pads2has the same number of rows, the same number of rows, and approximately the same pitch as the grid array of contact pads on semiconductor die1. In one embodiment grid array of contact pads2has a 0.2 millimeter pitch and grid array of contact pads4has a pitch of 1 millimeter. In the present embodiment, integrated circuit device10is a flip-chip packaged integrated circuit device that includes a semiconductor die1that is a high frequency, high current, device. In one specific embodiment semiconductor die1is a content addressable memory.

In the present embodiment each of the contact pads in sets of adjoining rows of contact pads15,17,25and27couple a ground voltage level to semiconductor die1. Each of the contact pads in set of columns of contact pads16and26couple a power voltage level to integrated circuit device10. Remaining rows31-33and43-44,81-84and92-94can couple power, ground or signals between semiconductor die1and external circuitry.

Channel45extends directly under rows of contact pads34-36and above rows of contact pads85-86, providing a low impedance pathway for coupling ground to semiconductor die1. Channel46extends directly under rows of contact pads37-39and above rows of contact pads87-89, providing a low impedance pathway for coupling power to semiconductor die1. Channel47extends directly under rows of contact pads40-42and over rows of contact pads90-91, providing an additional low impedance pathway for coupling ground to semiconductor die1.

Referring now toFIGS. 5-6decoupling capacitors11-14are disposed over the top surface of package substrate3, and electrically coupled to ground plane7and power plane8. In the present embodiment, vias83electrically connect to power plane8and are attached to each decoupling capacitor11-14using solder or conductive adhesive. Vias84electrically connect to ground plane7and are attached to each decoupling capacitor11-14using solder or conductive adhesive.

In the present embodiment channels45-47extend laterally past decoupling capacitors11-14. Therefore, the contiguous metallization of channel45extends directly under rows of contact pads34-36, under portions of decoupling capacitors11-12and directly over rows of contact pads85-86. The contiguous metallization of channel46extends directly under rows of contact pads37-39, under portions of decoupling capacitor11-14and directly over rows of contact pads87-89. The contiguous metallization of channel47extends directly under rows of contact pads40-42, under portions of decoupling capacitors13-14and directly over rows of contact pads90-91.

Because each of channels45-47extend under more than one row of contact pads, they each have significant width. Moreover, channels45and47are not interrupted by vias that couple to power, signal pins or isolation rings and channel46is not interrupted by vias that couple to ground, signal pins or isolation rings. Accordingly, channels45-47provide a significant amount of contiguous metallization. In addition, since decoupling capacitors11-14are connected directly to a power channel and a ground channel by a via, sufficient capacitance is provided to provide power and ground a semiconductor die1that is a high frequency, high current integrated circuit device.

Referring now toFIG. 7, a circuit board assembly100is shown that includes a circuit board103that includes a first grid array of contact pads102disposed on a top side of circuit board103. In the present embodiment grid array of contact pads102corresponds to grid array of contact pads4. More particularly, in the present embodiment, grid array of contact pads102has the same number of columns, the same number of rows, and approximately the same pitch as grid array of contact pads4.

Grid array of contact pads102includes a first set of adjacent rows of contact pads115that are coupled to a first channel145that extends within a ground plane107of circuit board103and a second set of adjacent rows of contact pads116that are coupled to a second channel146that extends within a power plane108of the circuit board103. In the present embodiment, first set of adjacent rows of contact pads115includes all of the contact pads in row135and all of the contact pads in adjacent row of contact pads136. Second set of adjacent rows of contact pads116includes all of the contact pads102in rows137-139. Contact pads102in the first set of adjacent rows of contact pads115directly overlie a portion of the first channel145and the contact pads102in the second set of adjacent rows of contact pads116directly overlie a portion of second channel146.

Grid array of contact pads102includes a third set of adjacent rows of contact pads117that directly overlie a portion of a third channel147that extends within ground plane107of circuit board103. Third set of rows of contact pads117includes all of the contact pads in rows140-141.

In the present embodiment each of the contact pads in rows135-136and140-141couple ground to packaged integrated circuit device110and each of the contact pads in rows137-139couple power to packaged integrated circuit device10. Remaining rows131-134and142-144can include contact pads102for coupling power, ground or signals between the internal circuitry of packaged integrated circuit device10and external circuitry.

FIGS. 8-10show a circuit board assembly110that includes circuit board assembly100ofFIG. 7and packaged integrated circuit device10ofFIGS. 1-6. In the present embodiment package integrated circuit device10is attached to grid array of contact pads102using solder balls105.

Decoupling capacitors111-112are disposed on the top side of circuit board103. Each decoupling capacitor111-112is electrically coupled to first channel145and electrically coupled to second channel146, and extends directly over a portion of first channel145and directly over a portion of second channel146. Decoupling capacitor111extends proximate one end of first channel145and second channel146, and decoupling capacitor112extends proximate the opposite end of first channel145and second channel146. In the present embodiment decoupling capacitors111-112are discrete devices that are electrically coupled to a via184that contacts first channel145and a via183that contacts second channel146. In the present embodiment, each decoupling capacitor111-112attaches to vias183and184using solder or conductive adhesive.

Additional decoupling capacitors113-114are disposed on the top side of circuit board103. Each of additional decoupling capacitors113-114extends directly over a portion of second channel146and directly over a portion of third channel147. Each decoupling capacitor113-114is electrically coupled to second channel146and electrically coupled to third channel147. In the present embodiment each of additional decoupling capacitors113-114is a discrete device that is electrically coupled to a via that attaches to second channel146and a different via that attaches to third channel147. In the present embodiment, solder or conductive adhesive is used to attach each decoupling capacitor111-114to a conductive structure on the top surface of circuit board103.

Circuit board103can be formed by integrating layers of dielectric and conductive material, and patterning a top conductive layer to form grid array of contact pads102. Vias161-167can be formed by etching or drilling openings, and filing the openings with conductive material to isolate vias165-167from ground plane7.

In the present embodiment channels145-147extend laterally past decoupling capacitors111-114. Therefore, the contiguous metallization of channel145extends directly under rows of contact pads134-136and under portions of decoupling capacitor111-112. The contiguous metallization of channel146extends directly under rows of contact pads137-139and under portions of decoupling capacitor111-114. The contiguous metallization of channel147extends directly under rows of contact pads140-141and under portions of decoupling capacitor113-114. Because each of channels145-147extends under more than one row of contact pads, they each have significant width. Moreover, channels145and147are not interrupted by vias that couple to power, signal pins or isolation rings, and channel146is not interrupted by vias that couple to ground, signal pins or isolation rings. Accordingly, circuit board103provides a significant amount of contiguous metallization that is used to provide power and ground to a semiconductor die1. In addition, because decoupling capacitors11-14are connected directly to a power channel and a ground channel by a via, and because the contiguous metallization of channels145-147extends directly under each decoupling capacitor111-114, power and ground are effectively coupled between decoupling capacitors111-114and integrated circuit device10. When this is combined with the corresponding channels45-47and capacitors11-14on integrated circuit device10, a circuit board assembly110is obtained that can effectively provide power and ground to high frequency, high current devices such as content addressable memories.

InFIG. 11, an a circuit board assembly200is shown that has all of the features of the embodiment shown inFIGS. 7-10, and that includes one or more additional decoupling capacitor180that is coupled to the bottom of circuit board103. In the present embodiment a first via181that attaches to first channel145couples ground to decoupling capacitor180and a second via182that attaches to channel146couples power to decoupling capacitor180. In the present embodiment, decoupling capacitor180is a discrete device that is attached to vias181-182using solder or conductive adhesive. ThoughFIG. 11shows a single decoupling capacitor180on the bottom of circuit board103, in one embodiment multiple decoupling capacitors are disposed on the bottom of circuit board103.

InFIG. 12, a circuit board assembly is shown that includes a packaged integrated circuit device210having additional decoupling capacitors231-234on the top surface of package substrate3. Decoupling capacitors231-232extend over and are electrically coupled to channels45-46; and decoupling capacitors233-234extend over and are electrically coupled to channels46-47. Additional capacitors221-228are attached to the top surface of circuit board103. More particularly, decoupling capacitors221-224extend over and are electrically coupled to channels145-146; and decoupling capacitors225-228extend over and are electrically coupled to channels146-147.

Though the embodiments ofFIGS. 1-12are shown to include three channels45-47, alternatively, packaged integrated circuit device10could have fewer or more channels. In one alternate embodiment package substrate3only includes two channels. In this embodiment package substrate3only includes sets of adjacent rows of contact pads15-16and25-26, includes only channels45and46, and includes only decoupling capacitors11-12. Also, circuit board assembly103could include fewer or more channels. In one alternate embodiment circuit board assembly103only includes sets of adjacent rows of contact pads115-116, only channels145-146and only decoupling capacitors111-112.

In the embodiments shown inFIGS. 1-12, sets of adjacent rows of contact pads are used to form channels. Alternatively, sets of adjacent columns of contact pads could be used. Accordingly, each set of adjacent rows of contact pads can be a set of adjacent rows or columns of contact pads.

Although the methods and apparatus of the present invention are discussed with reference to the use of channels for coupling power and ground, it is appreciated that the methods of the present invention can be used to provide multiple different voltage levels to die1. In one embodiment, a separate channel is used to provide each voltage level to die1, with some or all of the different voltages coupled to decoupling capacitors as is illustrated inFIGS. 1-12.

In one embodiment that is illustrated inFIG. 13, board assembly1100includes a semiconductor die1101that utilizes three voltage levels, a first voltage level that is coupled to the die through a first plane1107, a second voltage level that is coupled to die1101through a second plane1108and a third voltage level that is coupled to die1101through a third plane1109. In the present embodiment package substrate1133includes a first channel1102that extends within first plane1107, a second channel1103that extends within second plane1108and a third channel1104that extends within third plane1109. Vias1121couple corresponding contacts on the top and bottom of package substrate1133to channels1102-1104.

Continuing withFIG. 13, circuit board1134includes a first plane1117within which a first channel1112extends, a second plane1118within which a second channel1113extends, and a third plane1119within which a third channel1114extends. Vias1122couple channels1112-1114to corresponding contacts on the top of circuit board1134. In one embodiment the first voltage level is a first supply voltage level VDD1, the second voltage level is a second supply voltage level VDD2and the third voltage level is a voltage level VSS. In one embodiment VSSis ground (e.g., 0 volts), VDD1is 1.0 volt and VDD2is 0.65 volts. In the present embodiment channels1102-1104are coupled to decoupling capacitors on the top of package substrate1133and channels1112-1114are coupled to decoupling capacitors on the top of circuit board1134in the same manner as shown in the embodiments ofFIGS. 1-12. In one embodiment one or more of channels1112-1114are also coupled to capacitors on the bottom of circuit board1134.

In the embodiments shown inFIGS. 1-13, sets of adjacent rows of contact pads are used to form channels. Alternatively, sets of adjacent columns of contact pads could be used. Accordingly, each set of adjacent rows of contact pads can be a set of adjacent rows or columns of contact pads.