Specially shaped contact via and integrated circuit therewith

An integrated circuit device including a contact via having a non-cylindrical bottom portion is disclosed. Also a contact via with non-parallel side walls is disclosed. The contact vias are selectively positioned in the integrated circuit device.

BACKGROUND OF THE INVENTION

1. Technical Field

This invention relates to integrated circuit devices and a process of making the same, and in particular, this invention relates to microcavity structures which utilize a pinning layer to pin the microcavity structures in selected areas, applications thereof and process of making the same. This invention also relates to the specially shaped contact vias created with the process and the integrated circuit therewith.

2. Related Art

As integrated circuit devices become smaller, spacing between electronic components and conductors becomes ever more critical. Such components and/or conductors are typically separated and isolated by a dielectric material. A vacuum has the best relative dielectric constant (1.0). The dielectric constant of air is just slightly higher than that of a vacuum.

Doped glass is commonly used as an integrated circuit dielectric because its melting point can be made significantly lower than that of regular glass or of other dielectric materials. Boro-Phosphorus Silicate Glass (BPSG) is one exemplary type of doped glass. After deposition over a pattern of polysilicon conductors, for example, a BPSG dielectric layer can be put through a high temperature reflow process, usually at about 900° C., which reflows the BPSG, smooths its surface, and eliminates ‘as deposited’ voids between the polysilicon conductors for facilitating subsequent processing steps.

A typical BPSG material, however, has a significantly higher relative dielectric constant, e.g., about 3.6 to 4.6. One technique which has been used to reduce the relative dielectric constant of BPSG glass is to allow cavities to form in the material at appropriate locations. The cavities can form during the chemical vapor deposition (CVD) process in spaces between raised features, such as conductors or semiconductor mesas. These cavities are essentially air or vacuum filled and therefore constitute a low dielectric constant region between the raised features. In this manner, for example, capacitive coupling between adjacent conductors can be reduced, thereby enhancing device signal speed.

Despite speed improvements, which voids in BPSG films can provide, their proper size and shape formation is presently difficult to control. For example, voids between adjacent conductors are formed when a BPSG layer is deposited on top of a polysilicon conductive pattern. However, during the reflow process, the voids may disappear if the spaces between polysilicon conductors are large enough or the deposited film is thin enough. The voids formed when a BPSG layer of about 7000 Angstroms is deposited over a circuit topography of conductors separated by about 1.0 micron are typically eliminated during reflow. Unfortunately, it is not possible to forgo the reflow process without also losing the smoothness and related benefits such a structure can provide in subsequent processing.

Thus, as with the above-discussed example, there is a need for an improved method for controllably fabricating cavities for semiconductor and micro-machine applications, such as for pressure sensing, chromatography, fabrication of capacitive components, and selectively isolating components and conductors, etc. Further, there is a need for a method to create self-aligned contact vias which do not short circuit to neighboring conductors. Further there is a need to be able to shape contact vias.

SUMMARY OF THE INVENTION

Microcavity structures or voids are controlled for providing structures, such as self-aligned contact vias, by pinning a microcavity in selected areas using a pinning layer which is then selectively removed. A structure such as the contact via is formed in a method which steps include: providing a layer having a pair of raised features; depositing a void forming material over said layer; depositing a pinning material over said void forming material, wherein the pinning material acts to pin a void in said void forming material; and annealing the materials.

Another method of this invention includes the steps of: providing a substrate with topography; depositing a void forming material over said substrate to thereby form voids; depositing a pinning material over said void forming material wherein the pinning material pins the void forming material; patterning said pinning material to remove the pinning material from areas where void formation is not desired; and annealing the voids in areas where the pinning material remains to seal the void forming material in areas where the second material has been selectively removed.

The contact via and method for making the same saves both time and expense over existing methods. For example, it does not require the use of pressurizing the microcavities to prevent collapse of the microcavity structures. Another advantage is more accurate control of size, shape and location of void formation. Numerous other advantages and features of the method will become readily apparent from the following detailed description of the preferred embodiment, the accompanying drawings and the appended claims.

In another embodiment in accordance with the present invention is provided an integrated circuit device comprising a contact via having a non-cylindrical bottom portion. The integrated circuit device may have either a frustoconical or arrowhead shaped bottom portion.

In a further embodiment, a contact via having non-parallel side walls is provided.

In yet another embodiment in accordance with the present invention is provided a contact via for use in a semiconductor device, the contact via having non-parallel side walls. The contact via may also have either a frustoconical or arrowhead shaped bottom portion.

The above devices allow for contact vias with non-cylindrical shape.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Various types of microcavity formation are described in detail in U.S. Pat. No. 5,508,234, which is assigned to International Business Machines Corp., and is hereby incorporated by reference.

Referring toFIGS. 1 and 7a, a layer12of, e.g., polysilicon, is provided. The layer12may be built up by semiconductor processing steps to include a conductor or source/drain region (S/D)24. A plurality of raised features20,22,120,122such as conductors (e.g., polylines), or semiconductor mesas, having an aspect ratio greater than 2 are then formed on layer12. The size and shape of the raised features20,22,120,122may vary depending upon the particular application and the desired size and shape of the resultant void18. The raised features20,22,120,122are formed such that a layer disposed thereabove would not entirely fill the space therebetween (i.e., a void would be formed). The aspect ratio/pair spacing is critical to determining where the void will form. For instance, as shown inFIG. 7a, the space between raised features22and120is such that no void18is formed therebetween. Accordingly, the positioning of voids18can be controlled by the spacing between raised features20,22,120,122.

A layer or film14of material, such as a glass or more particularly Boro-Phosphorus Silicate Glass (BPSG), is deposited over the layer12and raised features20,22,120,122by a deposition process, such as preferably Sub-atmospheric Chemical Vapor Deposition (SACVD). Other deposition processes may be used such as Plasma Enhanced Chemical Vapor Deposition (PECVD), Liquid Phase Chemical Vapor Deposition (LPCVD), etc. The layer of material14is a relatively low density film. Voids18are formed between the raised features20,22and120,122in any desired number, shape or geometry, such as microtunnels. Preferably, the layer of material14is deposited to a thickness of greater than 0.5 of the space between the pair of raised features.

Care should be taken to ensure that during the anneal step the relatively low density material14does not contract. During annealing the material14tends to contract (e.g., relatively low density BPSG tends to contract by about 3%), resulting in the void moving toward the top of a surface of the layer14one vacancy at a time (literally one atom at a time). This may result in the undesired effect of elimination of the void18. Thus, in order to determine the desired void shape and geometry of void18, a layer of pinning material16is deposited over the layer14before annealing. The pinning layer16changes the shape of the void. The preferred annealing step is a Rapid Thermal Anneal (RTA). The layer16is formed from a relatively high density material such as silicon dioxide (SiO2), phosphorous doped SiO2, boron phosphorous doped SiO2, or any material which would shrink less than the layer14during the anneal, adheres well to the layer14, and is fairly rigid such that it does not expand or shrink during the anneal relative to layer14. Such materials include sputtered silicon, silicon nitride, CVD or sputtered metal. The layer16is deposited by a deposition process, such as Plasma Enhanced Chemical Vapor Deposition (PECVD). As shown inFIGS. 7band7c, the material16may be selectively removed, by lithographically patterning and etching above the raised portions or polysilicon lines, to form open areas200above chosen voids, hence, selectively removing chosen voids18as the voids18rise through layer14during the anneal, i.e., through void diffusion.

Referring toFIG. 2, a self-aligned contact via30is shown between the raised features20,22.

Referring toFIGS. 3 and 4, a top view of a self-aligned contact via is shown in which void creation/movement is illustrated. In the case of a self-aligned contact via, the raised features may include, for example, a word line or gate42and44, formed from a material such as polysilicon, which form parallel lines which diverge at70to form a semi-circular like configuration and then converge at71to resume as parallel lines. If the aspect ratio is sufficiently high (2), a void99is formed during BPSG deposition. During anneal, if a pinning layer is over the BPSG, the voids50,51are formed so that they coalesce to, i.e., move towards, the contact regions80,81. The contact regions80,81are sized to allow a void to exist. Although other techniques are contemplated, the pinning layer16is only on top of the contact regions80,81. The pinning layer16is lithographically patterned over the contact regions80,81. The material is etched through the top two layers16,14down to expose the voids50,51, then down to the source/drain region24as will be more fully discussed infra.

Referring now toFIGS. 2 and 5a-6d, the specially shaped contact vias88,188and the dielectric10,110in which they can be formed by the above processes are shown. As illustrated in the figures, the contact via areas78,178in accordance with the present invention have non-parallel side walls80,82,180,182.

In a first preferred embodiment, as shown inFIGS. 2 and 5a-5c, the void18has been opened to provide a contact via areas30,78having a frustoconical bottom portion. The upper portion of the contact via areas can be constructed to be cylindrical and can extend through a number of layers, e.g., layers14,16, as shown inFIGS. 5a-5c. The contact via areas30,78shown extends between the raised features or polylines20,22. However, the contact via area78may be selectively provided anywhere desired in accordance with the above-identified process.

FIGS. 5aand5balso illustrate how the contact via88may be opened at the bottom-most portion, i.e., above the S/D region24, to provide a variety of differing size openings. For instance, the contact via area78may extend downwardly to a point contact as shown inFIG. 5aand be almost conical in shape, or it may be opened to a broader surface as shown inFIG. 5b, the process of creating of which will be discussed later.

Once the contact via area78has been sized and shaped as desired, it may be provided with a liner90of a titanium-based conductor, such as titanium nitride, titanium with an overlay of titanium nitride, tantalum nitride, tantalum nitride with an overlay of tantalum, or other permutations. Preferably titanium nitride is used. Finally, the contact via area78is filled with a conductive material92to provide the completed contact via88as shown inFIG. 5c. The conductive material92can be any conductive material known in the art, such as tungsten, copper or aluminum either in pure form or in an alloy form.

FIGS. 6a-6dillustrate a second preferred embodiment in which the contact via188has an arrowhead or heart shaped bottom portion. An arrowhead shape is the general shape of a triangle but having a third side extend inwardly upon itself at its midpoint with a linear member extending outwardly from that midpoint. In this embodiment, the void19has a heart shape rather than an oval shape18. The side walls180,182diverge upwardly and then converge inwardly towards the center of the via. As with the first embodiment, the contact via area178may also have a cylindrical upper portion and differing size openings above the S/D region24created by etching back the bottom portion of the voids to increase the separation between the bottom of side walls184,186as shown inFIG. 6c. (This would be done prior to creation of the S/D region24so as to prevent duplication of processes). Further, the contact via may extend between the raised portions or polylines20,22, or be placed anywhere desired in accordance with the above process.

Also similar to the first embodiment, the completed contact via188may include a titanium-based conductor liner190of, for example, titanium nitride. The contact via188is filled with a conductive material192as shown inFIG. 6d. Again, the conductive material may be any conductive material known in the art.

Referring toFIGS. 8a-8c, a second process of creating frustoconically shaped contact vias78,178is shown. In this process, as shown inFIG. 8a, a second pinning material216may be deposited across the layers12,14,16as shown inFIG. 7c, i.e., after anneal to remove selective voids, to further aid in maintaining the selectively created void218. Then, as shown inFIG. 8b, both pinning layers16,216are etched and/or planarized to remove the layers16,216. The bottom layer212may also be etched and/or planarized to the bottom portion of the void218and, hence, create a frustoconical bottom. Next, the layer212is replaced and the S/D regions224are created according to conventional processes. The resulting void278can then be filled as discussed above. The resulting void exhibits a frustoconical shape as shown inFIG. 8c.

Referring toFIGS. 9a-9d, a process of creating a contact via having a substantially oval bottom with a rectangular or square top portion, is shown. As shown inFIG. 9a, the wafer ofFIG. 8ahas been planarized to level the first pinning layer16and second pinning layer216. At this stage, a layer of photoresist320is laid upon the wafer except over the void318, as shown inFIG. 9b. An etching step follows, as shown inFIG. 9c, which opens the void318and contact via area378removes the photoresist320, and thus forms the oval with rectangular top shaped opening. As shown inFIG. 9d, this contact via388may also include an etch back step for the bottom of the wafer to form the frustoconical bottom of the contact via380,382. As also shown inFIG. 9d, the contact via388may be filled with conductive material and lined as discussed above with the other embodiments.

Those skilled in the art will understand from the above discussion that many other implementations of the various applications are possible, and within the scope of the present invention as defined by the appended claims.

While the invention has been described in detail herein in accordance with certain preferred embodiments thereof, many modifications and changes therein may be effected by those skilled in the art. Accordingly, it is intended by the appended claims to cover all such modifications and changes as fall within the true spirit of the invention.