Scaled-down phase change memory cell in recessed heater

A semiconductor structure configurable for use as a nonvolatile storage element includes a first electrode, an insulating layer formed on at least a portion of an upper surface of the first electrode, and a pillar traversing the insulating layer and being recessed relative to an upper surface of the insulating layer. The pillar includes a heater formed on at least a portion of the upper surface of the first electrode and a collar formed on sidewalls of the insulating layer proximate the heater and on at least a portion of an upper surface of the heater. The structure further includes a PCM layer formed on at least a portion of the upper surface of the insulating layer and substantially filling a volume defined by the upper surface of the heater and at least a portion of an upper surface of the collar. A second electrode is formed on at least a portion of an upper surface of the phase change material layer.

FIELD OF THE INVENTION

The present invention relates generally to memory devices, and more particularly relates to phase change memory cells.

BACKGROUND OF THE INVENTION

Non-volatile memory is an integral part of many electronic devices from mobile phones, digital cameras, and set-top boxes, to automotive engine controllers primarily because of its ability to store data even when power is turned off. One type of non-volatile memory, namely, phase change (PC) memory, is aimed at eventually supplanting flash memory technology which is used abundantly in such electronic devices. Modern phase change random access memory (PRAM) typically requires that a PC memory cell employed therein be compatible with existing field-effect transistor (FET) technology. However, PC memory cell volume must be very small so as to ensure that set and reset currents in the PC memory cell are smaller then a maximum FET current, which is difficult to achieve using present complementary metal-oxide semiconductor (CMOS) fabrication technology, such as, for example, a 90 nanometer (nm) process.

As is known, PC memory cells are generally based on storage elements which utilize a class of materials, such as chalcogenides, that have the property of switching between two distinct states, the electrical resistance of which varies according to the crystallographic structure of the material. A high-resistance, reset state is obtained when an active region of the phase change material (PCM) is in an amorphous phase, whereas a low-resistance, set state is obtained when the PCM is in a crystalline or polycrystalline phase. The PCM can be selectively switched between the two phases by application of set and reset currents to the PC memory cell.

Reducing the amount of current required by a PCM layer to change its crystalline phase can beneficially decrease power dissipation and improve reliability during operation of the PC memory cell. Consequently, attempts have been made to define current flow in the PC memory cell so as to provide more efficient self-heating (e.g., Joule heating) of the PCM in the cell. Existing solutions for defining current flow in a PC memory cell, which in turn defines an active PC memory cell volume, rely predominantly on pushing lithography and etching capabilities to their limits. Presently, existing lithography, including, for example, deep ultraviolet (DUV), e-beam, etc., is limited to a line resolution of about 45 nm. Such lithography techniques are already challenging, especially when forming small features having an island shape (preferably circular).

In particular, one of the smallest elements in a conventional PC memory cell is a heater which is typically located on one side of the PCM. The small heater is often ineffective and challenging to manufacture, and thus adds significantly to the cost of the PC memory cell. In order to achieve satisfactory results using small set/reset currents, the heater in the PC memory cell needs to be localized well inside the PCM. Moreover, a common failure mechanism in PC memory cells results from an open circuit condition due primarily to repeated stress associated with a set/reset operation, and therefore it is even more desirable to minimize the set/reset currents in the PC memory cell so as to ensure reliability of the cell.

Accordingly, there exists a need for improved techniques for defining current flow in a PC memory cell that does not suffer from one or more of the problems exhibited by conventional PC memory cells.

SUMMARY OF THE INVENTION

The present invention addresses the above-identified need by providing, in illustrative embodiments thereof, a PCM-based memory cell that allow the precise tuning of the switching current pulse. Advantageously, these designs provide high localized switching current density and increased heating efficiency so that a magnitude of the switching current pulse may be beneficially reduced to a value that is compatible with modern integrated circuits.

In accordance with an embodiment of the invention, a semiconductor structure configurable for use as a nonvolatile storage element includes a first electrode, an insulating layer formed on at least a portion of an upper surface of the first electrode, and a pillar traversing the insulating layer and being recessed relative to an upper surface of the insulating layer. The pillar includes a heater formed on at least a portion of the upper surface of the first electrode and a collar formed on sidewalls of the insulating layer proximate the heater and on at least a portion of an upper surface of the heater. The structure further includes a PCM layer formed on at least a portion of the upper surface of the insulating layer and substantially filling a volume defined by the upper surface of the heater and at least a portion of an upper surface of the collar. A second electrode is formed on at least a portion of an upper surface of the phase change material layer. A conductive barrier layer may optionally be formed between the second electrode and the phase change material layer.

Preferably, the collar is configured so as to constrict a flow of current in at least a portion of the phase change material layer proximate the heater to thereby create a region of localized heating in at least a portion of the phase change material layer when a switching current signal is applied between the first and second electrodes. The region of localized heating may be confined to a portion of the phase change material substantially filling the volume defined by the upper surface of the heater and at least a portion of the upper surface of the collar.

In accordance with another aspect of the invention, a memory circuit includes a plurality of nonvolatile memory cells and a plurality of bit lines and word lines operatively coupled to the memory cells for selectively accessing one or more of the memory cells. At least a given one of the memory cells includes a first electrode, an insulating layer formed on at least a portion of an upper surface of the first electrode, and a pillar traversing the insulating layer and being recessed relative to an upper surface of the insulating layer. The pillar includes a heater formed on at least a portion of the upper surface of the first electrode and a collar formed on sidewalls of the insulating layer proximate the heater and on at least a portion of an upper surface of the heater. The structure further includes a PCM layer formed on at least a portion of the upper surface of the insulating layer and substantially filling a volume defined by the upper surface of the heater and at least a portion of an upper surface of the collar. A second electrode is formed on at least a portion of an upper surface of the phase change material layer.

In accordance with another aspect of the invention, a method of forming a semiconductor structure configurable for use as a nonvolatile storage element includes the steps of: forming a first electrode; forming an insulating layer on at least a portion of an upper surface of the first electrode; forming a pillar traversing the insulating layer and being recessed relative to an upper surface of the insulating layer, the pillar comprising a heater formed on at least a portion of the upper surface of the first electrode and a collar formed on sidewalls of the insulating layer proximate the heater and on at least a portion of an upper surface of the heater; forming a phase change material layer on at least a portion of the upper surface of the insulating layer and substantially filling a volume defined by the upper surface of the heater and at least a portion of an upper surface of the collar; and forming at least a second electrode on at least a portion of an upper surface of the phase change material layer.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will be illustrated herein in conjunction with exemplary memory cells for use in integrated circuits, and methods of forming such memory cells. It should be understood, however, that the invention is not limited to the particular materials, features and processing steps shown and described herein. Rather, modifications to the illustrative embodiments will become apparent to those skilled in the art in view of the teachings herein.

Particularly with respect to processing steps, it is emphasized that the descriptions provided herein are not intended to encompass all of the processing steps which may be required to successfully form a fully functional integrated circuit device. Rather, certain processing steps which are conventionally used in forming integrated circuit devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for ease of explanation. However one skilled in the art will readily recognize those processing steps omitted from these generalized descriptions. Additionally, certain processing steps described herein may be considered optional, and thus may be omitted. Details of processing steps used to fabricate such integrated circuit devices may be found in a number of publications, for example, S. Wolf and R. N. Tauber,Silicon Processing for the VLSI Era, Volume1, Lattice Press, 1986 and S. M. Sze,VLSI Technology, Second Edition, McGraw-Hill, 1988.

The term “phase-change material” (PCM) as used herein is intended to encompass any material displaying more than one programmable electrical resistance state for use in integrated circuits. It is recognized that this definition may encompass more materials than are customarily included within this term. PCMs as used herein comprise, for example, various chalcogenides and transition metal oxides and include, but are not limited to, doped or undoped GeSb, SbTe, Ge2Sb2Te5(GST), SrTiO3, BaTiO3, (Sr,Ba)TiO3, SrZrO3, In2Se3, Ca2Nb2O7, (Pr,Ca)MnO3, Ta2O5, NiOxand TiOx, as well as other suitable materials.

It should be understood that the various layers and/or regions shown in the accompanying figures may not be drawn to scale. Furthermore, one or more semiconductor layers of a type commonly used in such integrated circuit structures may not be explicitly shown in a given figure for economy of description. This does not imply that the semiconductor layers not explicitly shown are omitted in the actual integrated circuit device.

FIG. 1is a cross-sectional view depicting at least a portion of an exemplary memory cell100, formed in accordance with an illustrative embodiment of the invention. The exemplary memory cell100comprises a bottom electrode101, a top electrode108, and a PCM-based storage element109formed between the top and bottom electrodes. Specifically, storage element109preferably comprises an insulating layer102, which may also be referred to herein as a barrier layer or a dielectric layer, formed on an upper surface of bottom electrode101, and a PCM layer120formed on an upper surface of at least a portion of the insulating layer. An optional conductive barrier layer107may be formed on an upper surface of PCM layer120, between storage element109and top electrode108. Top electrode10sis formed on an upper surface of conductive barrier layer107. For embodiments in which conductive barrier layer107is omitted from memory cell100, top electrode108may be formed directly on an upper surface of PCM layer120. It is to be appreciated that, in accordance with other aspects of the invention, memory cell100may comprise more or less than two electrode layers, more than one PCM layer, and/or more than one insulating layer.

Bottom and top electrodes101,108provide access to the memory cell100essentially by providing electrical connection to storage element109therein. The bottom and top electrodes101,108are preferably formed of an electrically conductive material, such as, but not limited to, a metal, an alloy, a metal oxynitride, a conductive carbon compound, etc. For example, top and bottom electrodes108and101, respectively, may comprise aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), molybdenum (Mo), niobium (Nb), WN, MoN, NbN, TiSiN, TiAlN, MoAlN, TaSiN, TaAlN, TiW, TaSi, and/or TiSi. The two electrodes101,108need not be formed of the same material. In a preferred embodiment, bottom electrode101is comprised of tungsten and top electrode108is comprised of copper.

As previously stated, PCM layer120is preferably comprised of, for example, various chalcogenides and/or transition metal oxides including, but are not limited to, doped or undoped GeSb, SbTe, Ge2Sb2Te5(GST), SrTiO3, BaTiO3, (Sr,Ba)TiO3, SrZrO3, In2Se3, Ca2Nb2O7, (Pr,Ca)MnO3, Ta2O5, NiOxand TiOx, as well as other suitable materials exhibiting two distinct phases of differing resistivities. Chalcogenide materials suitable for use with the present invention include, but are not limited to, tellurium (Te), selenium (Se), germanium (Ge), antimony (Sb), bismuth (Bi), lead (Pb), tin (Sn), arsenic (As), sulfur (S), silicon (Si), phosphorus (P), any mixture thereof, and/or any alloy thereof. In a preferred embodiment of the invention, PCM layer120comprises GST. PCM layer120may be deposited on at least a portion of one or more surfaces of the storage element using a standard deposition process (e.g., sputtering, spraying, chemical vapor deposition (CVD), etc.), although the invention is not limited to forming the PCM layer in this manner.

Storing data in memory cell100preferably involves placing some portion of the total volume of PCM layer120, referred to herein as the “switchable volume”106, into either a lower electrical resistance polycrystalline state or a higher electrical resistance amorphous state. Transitions between these states are accomplished primarily by heating the switchable volume106of PCM layer120, for example by applying a pulse of switching current to the memory cell through the bottom and top electrodes101,108. The duration of the switching current pulse is preferably between about one and 500 nanoseconds (ns) and has a fast falling edge (e.g., less than about 10 ns), although the invention is not limited to any particular duration and/or rise or fall time of the switching current pulse. The fast falling edge acts to freeze the switchable volume106of PCM layer120in its electrical resistance state without allowing additional time for the bonds within the material to continue to rearrange.

Subsequently, reading the state of memory cell100can be accomplished by applying a sensing voltage to the memory cell, again via the bottom and top electrodes101,108. The ratio of the electrical resistances between the higher and lower electrical resistance states in a typical PCM-based memory cell is between about 100:1 and about 1000:1. The sensing voltage is preferably of low enough magnitude to provide negligible ohmic heating in PCM layer120. Accordingly, the electrical resistance state of PCM layer120can be determined in this manner without disturbing its written electrical resistance state. Data integrity is thereby maintained while reading the data.

As previously stated, an embodiment of the invention may also include conductive barrier layer107between top electrode108and storage element109. Conductive barrier layer107, when used, preferably prevents or substantially inhibits a chemical reaction between PCM layer120and top electrode108. Conductive barrier layer107is ideally comprised of an electrically conductive material which is substantially inert at least with respect to the materials of which top electrode108and PCM layer120are comprised. Examples of such electrically conductive but chemically inert materials include, but are not limited to, cobalt, ruthenium, tantalum, tantalum nitride (TaN), indium oxide, and titanium nitride (TiN). In a preferred embodiment of the invention where top electrode108comprises copper and PCM layer120comprises GST, conductive barrier layer107preferably comprises TiN or TaN. Both TiN and TaN exhibit a low diffusion rate for metallic elements. As a result, forming conductive barrier layer107out of these materials substantially prevents metallic elements contained in top electrode108from diffusing into PCM layer120.

Insulating layer102is preferably formed of an oxide, nitride, or an alternative material which is substantially electrically non-conductive (e.g., having a resistance in the gigohm range). Insulating layer102may be formed using, for example, a standard oxide growth process, although alternative methodologies for forming the insulating layer are similarly contemplated (e.g., deposition process). The material used to form insulating layer102should be stable at temperatures higher than a melting point of the PCM in PCM layer120at the set and reset temperatures, which may be greater than about 500 degrees Celsius, so that compounds do not form between the PCM and the insulating layer material during operation of the storage element109. Additionally, insulating layer102and PCM layer120should be mutually insoluble so as to further reduce the likelihood that compounds form between the PCM layer and the insulating layer. A cross-sectional thickness, d, of insulating layer102is preferably about 10 nm to about 100 nm, although the invention is not limited to any particular thickness. In a preferred embodiment, insulating layer102comprises silicon dioxide or silicon nitride.

With continued reference toFIG. 1, storage element109includes a pillar104traversing insulating layer102and in electrical contact with bottom electrode101. Pillar104preferably comprises a heater103, formed on an upper surface of bottom electrode101, and a collar105formed on at least a portion of an upper surface of the heater. A cross-sectional thickness of heater103(measured as a height of the heater above the bottom electrode) is preferably less than a cross-sectional thickness of the insulating layer102, such that a recess is formed in the insulating layer. Collar105is formed on sidewalls of the recess in insulating layer102. An extension of PCM layer120(e.g., switchable volume106) is formed on an upper surface of collar105.

Pillar104is preferably substantially circular in a horizontal plane parallel to a plane defined by the interface between the pillar and lower electrode101(i.e., when the pillar is viewed top down). Such a shape may, for example, be advantageous with respect to a packing density of a plurality of such memory cells in an integrated circuit. In this instance, collar105is preferably shaped substantially as a toroid (e.g., doughnut). Nevertheless, other shapes for the pillar104and collar105(and the resultant recess in the insulating layer) are similarly contemplated and would still come within the scope of the invention. Pillar104could be, for instance, elliptical or rectangular in the horizontal plane defined above. These and other shapes may allow the switchable volume106of the PCM in PCM layer120to be beneficially increased without concomitantly causing the current density to be substantially reduced at any point within the switchable volume during application of the switching current pulse.

As apparent from the figure, collar105preferably creates a constriction for reducing the volume106of PCM in PCM layer120which is in contact with heater103. In this manner, collar105is configured to constrict a flow of current in at least a portion of PCM layer120proximate heater103to thereby create a region of localized heating in at least a portion of the PCM layer when a switching current signal is applied between the top and bottom electrodes108,101. Collar105preferably comprises a dielectric (e.g., an oxide, nitride, etc.), or an alternative material which is substantially electrically non-conductive (e.g., having a resistance in the gigohm range).

Heater103is preferably comprised of an electrically conductive material which is substantially chemically inert when in contact with materials used to form PCM layer120, insulating layer102, bottom electrode101, and collar105. Examples of such electrically conductive but chemically inert materials include carbon, TiN, and TaN, although the invention is not limited to these materials. In a preferred embodiment where PCM layer120comprises GST, heater103preferably comprises TiN. When a signal is applied to the bottom and top electrodes101,108of memory cell100, a volume106of PCM layer120proximate to heater103, which is substantially more conductive than the surrounding insulating layer102, will experience a current density which is substantially higher compared to a current density in the remainder of the PCM as a result of the constriction created, at least in part, by collar105. The concentration of current in and around pillar104will, in turn, result in localized self-heating of the PCM. When the applied signal reaches a certain threshold so as to cause a localized heating of the PCM proximate to heater103to a certain critical temperature value, a phase transition of at least a portion of the PCM will occur.

Advantageously, these unique design features act to force the switching current to pass through a confined volume106of the PCM in PCM layer120. As a result, this memory cell design provides high localized switching current density so that the magnitude of the switching current pulse can be reduced to a value that is compatible with modern integrated circuits.

The confinement of the switching current to the narrow switching volume106of the PCM which is in direct contact with the heater (e.g., within the pillar and within the collar) results in a high localized current density in this volume, and, in turn, high ohmic heating. For this reason, this volume forms the switchable volume106of the PCM layer120in the memory cell100. Outside of this switchable volume, the current density is insufficient to cause the transition between electrical resistance states. Accordingly, the switching current needed to effect an electrical resistance state change in the memory cell will largely be determined by the narrow volume of the PCM that forms part of the periphery of the recess in insulating layer102. The magnitude of this required switching current pulse will be substantially less than that which would be required to cause a state transition in the remainder of the PCM volume.

Moreover, in addition to restricting the switchable volume106of the PCM in PCM layer120to that region defined by collar105, heater103and insulating layer102, memory cell100also acts to thermally isolate this switchable volume. Reference toFIG. 1shows that the non-switching portion of the PCM is located above the switchable volume106of the PCM, while dielectric material in the form of collar105and insulating layer102surround the switchable volume laterally. Since PCMs such as GST and insulating materials such as silicon dioxide and silicon nitride have relatively low thermal conductivities when compared to conductive materials (e.g., metals), this arrangement tends to trap heat within the switchable volume. Advantageously, this thermal isolation causes the heating efficiency of this switchable volume to be increased, again allowing the magnitude of the switching current pulse to be reduced.

FIG. 2is a simplified flow diagram showing an exemplary method200for forming a memory cell, in accordance with an aspect of the present invention.FIGS. 3-8are cross-sectional views depicting illustrative steps in a semiconductor fabrication process which may be used in forming a memory cell of the type shown inFIG. 1, in accordance with an embodiment of the invention. This fabrication process comprises the deposition of several layers upon a semiconductor substrate; this deposition may be accomplished using a variety of deposition techniques known to those skilled in the art, including but not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), atomic layer deposition (ALD), etc.

With reference first toFIG. 2, the method200begins in210with, for example, a semiconductor structure300such as that shown inFIG. 3. This exemplary middle-of-the-line structure300may comprise a first insulating layer301, at least one electrode302(which may correspond to bottom electrode101shown inFIG. 1), a first conductor303, which may be a bit line, and a second conductor305, which may be a word line. Electrode302, as well as first and second conductors303,305, preferably comprise a metal or an alternative conductive material (e.g., polysilicon). Electrode302, first and second conductors303,305need not be formed of the same material. The word line preferably serves to bias one or more FETs devices (omitted from the drawings for clarity), each FET device being used to selectively access a corresponding memory cell. This represents a starting point of the portion of the semiconductor fabrication process described herein.

This particular arrangement is merely illustrative and a number of other arrangements would still come within the scope of the invention. For example, rather than being formed of a metal, electrode302may be a metal contact (e.g., a stud) on which the memory cell is formed. This metal contact could, for example, be operative to electrically connect the memory cell to a FET that resides at a different level in the integrated circuit. These and other variations on the placement of the memory cell within the metallization of an integrated circuit will be familiar to one skilled in the art.

In step220, a conductive layer (e.g., conductive layer404shown inFIG. 4) to be used for the heater (e.g., heater103shown inFIG. 1) is deposited on an upper surface of semiconductor structure300. Next, in step225, this layer of heater material is patterned to form one or more pillars using fabrication methods known to persons having skill in the art. For example, conventional photolithography may be utilized to form a photoresist masking feature406, or alternative protective layer or film, on an upper surface of conductive layer404in which the desired pillar is to be formed, resulting in the film stack shown inFIG. 4. With this photoresist masking feature406in place, an anisotropic etching technique, preferably reactive ion etching (RIE), is used to remove portions of the conductive layer404where photoresist masking feature406is not present. Once the anisotropic etching process is complete, the photoresist masking feature406is stripped from the upper surface of conductive layer404, leaving one or more pillars507, each pillar being formed on an upper surface of a corresponding electrode302, as shown inFIG. 5. Pillar507may correspond to pillar104depicted inFIG. 1.

It should be noted that modern semiconductor processing techniques allow a pillar (e.g., pillar507inFIG. 5) to optionally be formed with a width substantially smaller than the photoresist masking feature (e.g., photoresist masking feature406inFIG. 4) utilized to define the pillar. For example, the RIE processing step that patterns the pillar can be made to have a substantial “etch bias” that narrows the feature being etched in relation to the size of the photoresist masking feature. Additionally, or alternatively, after RIE, the pillar can be exposed to a timed wet etch, or alternative etching process, to reduce the size of the pillar. Hydrofluoric acid, for example, can be utilized to precisely etch features comprising silicon dioxide. Hot phosphoric acid may, alternatively, be utilized to etch features comprising silicon nitride.FIG. 5illustrates the result of these steps.

It should be noted that although fabrication method200is described herein as using photolithography for patterning the conductive layer (404inFIG. 4) which will form the heater in a corresponding memory cell, any patterning process may be utilized to form the pillars (406inFIG. 4), as will be appreciated by one having skill in the art. Furthermore, it should be noted that an alternative patterning process may not require the use of a photoresist masking feature406.

After the pillar has been formed, in step230an insulating layer (insulating layer506inFIG. 5), which may correspond to insulating layer102depicted inFIG. 1, is preferably formed on an upper surface of semiconductor structure300and surrounding pillars507, so as to substantially fill the gaps between the pillars. Insulating layer506may be formed, for example, using a deposition process as discussed above or an oxide growth process, although alternative methods for forming the insulating layer are similarly contemplated, as will be known by those skilled in the art. A polishing step (e.g., chemical mechanical polishing (CMP)) may also be performed such that insulating layer506is substantially planar with the pillars507.FIG. 5illustrates result of these steps.

Next, in step240a recess601is formed in each pillar507such that an upper surface of the pillars is below an upper surface of insulating layer506, as depicted inFIG. 6. Recess601may be formed, for example, using a process which can obtain a smaller diameter than is possible using conventional photolithography. This may be accompanied by RIE using a plasma which will etch pillar507but not insulating506. In a preferred embodiment of the invention in which the pillar507comprises TiN and the insulating layer506comprises silicon dioxide, a combination of flouroform (CHF3) and chlorine (Cl2) within an argon diluent (Ar) satisfies these properties. Next, in step250a conformal spacer layer602is substantially uniformly deposited on an upper surface of the structure, including upper surfaces of insulating layer506and pillars507.FIG. 6illustrates results of these steps.

In step255, an anisotropic etching process (e.g., directional RIE) may be used to remove portions of the conformal spacer layer602on upper surfaces of insulating layer506and pillars507, thereby at least partially exposing the pillars, as shown inFIG. 7. By using anisotropic etching, portions of the conformal spacer layer (e.g.,602inFIG. 6) will remain on sidewalls of the insulating layer defining the recess (e.g., recess601inFIG. 6). In this manner, the conformal spacer layer will form a collar701on sidewalls of the recess. The collar701further constricts a volume702within the recess of the pillar507.FIG. 7shows results of this step.

In step260, a PCM layer (e.g., PCM layer801shown inFIG. 8), which may correspond to PCM layer120inFIG. 1, is formed on an upper surface of insulating layer506and filling the volume702(seeFIG. 7) in the recess defined by the upper surface of pillar507and collar701. The PCM filling volume702preferably corresponds to the switchable volume in PCM layer801, as described above. In step265, a barrier layer802, which may correspond to conductive barrier107depicted inFIG. 1, may be optionally deposited on an upper surface of PCM layer801. Finally, in step270a top electrode layer803, which may correspond to top electrode108inFIG. 1, is formed on an upper surface of barrier layer802, for example by deposition, photolithography and RIE or, in a preferred embodiment in which the top electrode layer is copper, by a damascene process (e.g., patterning of silicon dioxide, copper deposition and CMP). The method ends at280.

FIG. 9is a schematic diagram illustrating an exemplary nonvolatile memory circuit900in which the memory cell of the present invention can be employed, in accordance with another aspect of the present invention. The memory circuit900preferably comprises a plurality of PCM-based memory cells902, at least a subset of which are formed in accordance with techniques of the invention described above, and corresponding access transistors904connected thereto. Access transistors904are selectively activated by application of appropriate signals, WL1, WL2, to corresponding word lines906in the memory circuit900. Each of the access transistors904is preferably operative to connect a first electrode of the corresponding memory cell902to ground, or an alternative voltage source.

Memory circuit900further includes a plurality of current sources912,916and920, supplying currents Iread, Iset and Ireset, respectively, to the memory cells902via a bit line multiplexer (BL mux)910, or an alternative switching arrangement. Each of the current sources912,916,920is preferably connected to the multiplexer910through a corresponding switch,914,918and922, respectively, which may comprise a transistor as shown. The current Iread is preferably configured for selectively reading a logical state of the memory cells902, while the currents Iset and Ireset are preferably configured for performing a set and reset operation, respectively, for selectively writing a logical state of the cells.

At least a portion of the methodologies of the present invention may be implemented in an integrated circuit. In forming integrated circuits, die are typically fabricated in a repeated pattern on a surface of a semiconductor wafer. Each of the die includes a device described herein, and may include other structures or circuits. Individual die are cut or diced from the wafer, then packaged as integrated circuits. One skilled in the art would know how to dice wafers and package die to produce integrated circuits. Integrated circuits so manufactured are considered part of this invention.