Clock tree circuit and memory controller

A clock tree circuit includes a clock source and a tree circuit. The clock source generates a signal. The tree circuit at least includes five driving units and a metal connection element. A first driving unit has an input terminal for receiving the signal, and an output terminal coupled to a first node. A second driving unit has an input terminal coupled to the first node, and an output terminal coupled to a second node. A third driving unit has an input terminal coupled to the first node, and an output terminal coupled to a third node. A fourth driving unit has an input terminal coupled to the second node. A fifth driving unit has an input terminal coupled to the third node. The metal connection element is coupled between the second node and the third node, and configured as a short-circuited element.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The disclosure generally relates to a clock tree circuit, and more particularly, to a clock tree circuit for reducing clock skew and clock jitter.

2. Description of the Related Art

Clock tree circuits are commonly used in the field of digital circuit design. However, since driving paths in clock tree circuits often have different lengths, they tend to result in clock skew and/or clock jitter and degrade the performance of the clock tree circuits. The different lengths of driving paths may also be caused by on-chip variation (OCV), which is unpredictable and uncontrollable. Accordingly, there is a need to design a novel clock tree circuit to solve the above problem.

BRIEF SUMMARY OF THE INVENTION

In a preferred embodiment, the disclosure is directed to a clock tree circuit, including: a first clock source, generating a first signal; and a first tree circuit, including: a first driving unit, wherein the first driving unit has an input terminal for receiving the first signal, and an output terminal coupled to a first node; a second driving unit, wherein the second driving unit has an input terminal coupled to the first node, and an output terminal coupled to a second node; a third driving unit, wherein the third driving unit has an input terminal coupled to the first node, and an output terminal coupled to a third node; a fourth driving unit, wherein the fourth driving unit has an input terminal coupled to the second node, and an output terminal; a fifth driving unit, wherein the fifth driving unit has an input terminal coupled to the third node, and an output terminal; and a metal connection element, coupled between the second node and the third node, and configured as a short-circuited element.

In some embodiments, the metal connection element is configured to reduce clock skew and clock jitter in the first tree circuit. In some embodiments, the first tree circuit further includes: a sixth driving unit, wherein the sixth driving unit has an input terminal coupled to the second node, and an output terminal; and a seventh driving unit, wherein the seventh driving unit has an input terminal coupled to the third node, and an output terminal. In some embodiments, the first driving unit, the second driving unit, the third driving unit, the fourth driving unit, the fifth driving unit, the sixth driving unit, and the seventh driving unit are implemented with buffers and/or inverters. In some embodiments, a width of the metal connection element is from 2 to 10 times greater than a minimum metal width in a process for manufacturing the clock tree circuit. In some embodiments, the first tree circuit further includes: one or more metal shielding elements, disposed adjacent to the metal connection element. In some embodiments, spacing between the metal connection element and each metal shielding element is from 2 to 10 times greater than a minimum metal width in a process for manufacturing the clock tree circuit. In some embodiments, the first tree circuit further includes: a plurality of additional metal shielding elements; and a plurality of via elements, wherein the additional metal shielding elements are coupled through the via elements to the metal shielding elements, so as to form a closed loop structure for surrounding the metal connection element. In some embodiments, the clock tree circuit further includes: a first independent power source, supplying a part or a whole of the first tree circuit. In some embodiments, the clock tree circuit is applied to a memory device, and the first signal outputted by the first clock source is a data strobe signal (DQS). In some embodiments, the clock tree circuit further includes: a second clock source, generating a second signal; and a second tree circuit, disposed adjacent to the first tree circuit, and receiving the second signal, wherein the second tree circuit is similar or identical to the first tree circuit. In some embodiments, the clock tree circuit further includes: a first independent power source, supplying a part or a whole of the first tree circuit; and a second independent power source, supplying a part or a whole of the second tree circuit.

In another preferred embodiment, the disclosure is directed to a memory controller, including: a first tree circuit, including: a first driving unit, wherein the first driving unit has an input terminal for receiving a first data strobe signal (DQS), and an output terminal coupled to a first node; a second driving unit, wherein the second driving unit has an input terminal coupled to the first node, and an output terminal coupled to a second node; a third driving unit, wherein the third driving unit has an input terminal coupled to the first node, and an output terminal coupled to a third node; a fourth driving unit, wherein the fourth driving unit has an input terminal coupled to the second node, and an output terminal; a fifth driving unit, wherein the fifth driving unit has an input terminal coupled to the third node, and an output terminal; and a metal connection element, coupled between the second node and the third node, and configured as a short-circuited element; and a plurality of first transceivers, transmitting or receiving a plurality of first bits, wherein the first transceivers are driven by the first tree circuit.

In some embodiments, the memory controller further includes: a second tree circuit, disposed adjacent to the first tree circuit, and receiving a second data strobe signal (DQS), wherein the second tree circuit is similar or identical to the first tree circuit; and a plurality of second transceivers, transmitting or receiving a plurality of second bits, wherein the second transceivers are driven by the second tree circuit.

DETAILED DESCRIPTION OF THE INVENTION

In order to illustrate the purposes, features and advantages of the invention, the embodiments and figures of the invention are disclosed in detail as follows.

FIG. 1is a diagram of a clock tree circuit100according to an embodiment of the invention. As shown inFIG. 1, the clock tree circuit100at least includes a first clock source101and a first tree circuit110. The first clock source101is configured to generate a first signal S1. For example, the first signal S1may be a normal clock signal. In alternative embodiments, when the clock tree circuit100is applied to a memory device or a memory controller, the first signal S1outputted by the first clock source101may be a data strobe signal (DQS) for use in a sampling process.

The first tree circuit110at least includes a first driving unit111, a second driving unit112, a third driving unit113, a fourth driving unit114, a fifth driving unit115, and a metal connection element119. The first driving unit111has an input terminal for receiving the first signal S1, and an output terminal coupled to a first node N1. The second driving unit112has an input terminal coupled to the first node N1, and an output terminal coupled to a second node N2. The third driving unit113has an input terminal coupled to the first node N1, and an output terminal coupled to a third node N3. The fourth driving unit114has an input terminal coupled to the second node N2, and an output terminal. The fifth driving unit115has an input terminal coupled to the third node N3, and an output terminal. In some embodiments, the first tree circuit110further includes a sixth driving unit116and a seventh driving unit117(optional elements). The sixth driving unit116has an input terminal coupled to the second node N2, and an output terminal. The seventh driving unit117has an input terminal coupled to the third node N3, and an output terminal. The first driving unit111, the second driving unit112, the third driving unit113, the fourth driving unit114, the fifth driving unit115, the sixth driving unit116, and the seventh driving unit117may be implemented with buffers and/or inverters according to different design requirements. Each buffer may be made by cascading two inverters. For example, a part of these driving units may be implemented with buffers so as to provide 0-degree clock phases, and the other driving units may be implemented with inverters so as to provide 180-degree clock phases. The first driving unit111may form a first driving stage of the first tree circuit110. The second driving unit112and the third driving unit113may form a second driving stage of the first tree circuit110. The fourth driving unit114, the fifth driving unit115, the sixth driving unit116, and the seventh driving unit117(if the sixth driving unit116and the seventh driving unit117exist) may form a third driving stage of the first tree circuit110. These driving stages can buffer (invert) the original first signal S1and provide sufficient output driving currents for subsequent corresponding stages. For example, the output terminals of the third driving stage (i.e., the output terminals of the fourth driving unit114, the fifth driving unit115, the sixth driving unit116, and the seventh driving unit117) may be further coupled to a variety of next-stage circuits, such as functional circuits or next-stage driving units (not shown).

It should be noted that since the driving paths in the clock tree circuit100have different lengths, they tend to result in serious clock skew and/or clock jitter. For example, a first driving path may be formed from the first clock source101through the first node N1to the second node N2, and a second driving path may be formed from the first clock source101through the first node N1to the third node N3. There may be different clock phases at the second node N2and the third node N3because of the non-uniform lengths of the first and second driving paths. However, ideally, all output terminals of the same driving stage should have the same clock phase. In the invention, the metal connection element119is proposed and incorporated into the first tree circuit110so as to solve the problem. The metal connection element119is added and coupled between the second node N2and the third node N3, and it is configured as a short-circuited element. Because the second node N2and the third node N3are tied together by the short-circuited metal connection element119, the clock phases at the second node N2and the third node N3are unified and become consistent with each other. This effectively eliminates different path delay times and different clock phases at the output terminals of the second driving unit112and the third driving unit113, and therefore solves the problem of clock skew and/or clock jitter in the clock tree circuit100. In some embodiments, the width W1of the metal connection element119is from 2 to 10 times greater than the minimum metal width in the process for manufacturing the clock tree circuit100, such that the resistance of the metal connection element119is sufficiently low as a short-circuited element. Preferably, the width W1of the metal connection element119may be from about 5 to 6 times greater than the minimum metal width. In alternative embodiments, if the sixth driving unit116and the seventh driving unit117are added, two ends of the metal connection element119may further extend and reach the input terminals of the sixth driving unit116and the seventh driving unit117. Although there are merely three driving stages and seven driving units shown inFIG. 1, it should be understood that the invention is not limited thereto. In other embodiments, the first tree circuit110may include more driving stages and driving units, and more metal connection elements119may be added and coupled to the output terminals of driving units arranged in the same driving stage, so as to reduce the clock skew and/or clock jitter in the clock tree circuit100.

FIG. 2is a diagram of a clock tree circuit200according to an embodiment of the invention.FIG. 2is similar toFIG. 1. The difference from the embodiments ofFIG. 1is that the first tree circuit110of the clock tree circuit200further includes one or more metal shielding elements230, which are disposed adjacent to the metal connection element119. For example, the metal shielding elements230may be disposed on the left, the right, the top, or the bottom of the metal connection element119. The metal shielding elements230are configured to suppress the crosstalk effect between the metal connection element119and other transmission lines. The first tree circuit110including the metal shielding elements230can generate pure and clear output signals for driving next-stage circuits. In some embodiments, the spacing D1between the metal connection element119and each metal shielding element230is from 2 to 10 times greater than the minimum metal width in the process for manufacturing the clock tree circuit200. Preferably, the spacing D1may be from about 5 to 6 times greater than the minimum metal width. In some embodiments, the metal shielding elements230are further coupled to a ground voltage node or a power supply node (not shown). Other features of the clock tree circuit200ofFIG. 2are similar to those of the clock tree circuit100ofFIG. 1. Accordingly, the two embodiments can achieve similar levels of performance.

FIG. 3Ais a cross-sectional view of the metal connection element119and the metal shielding elements230according to an embodiment of the invention. In the embodiment ofFIG. 3A, the metal connection element119and the metal shielding elements230are formed on the same metal layer (M3), and the metal shielding elements230are disposed on the left and the right of the metal connection element119.FIG. 3Bis a cross-sectional view of the metal connection element119and the metal shielding elements230according to an embodiment of the invention. In the embodiment ofFIG. 3B, additional metal shielding elements231and232are further included, and they are formed on different metal layers (M2and M4) and disposed on the top and the bottom of the metal connection element119, respectively. The additional metal shielding elements231and232may be further coupled through via elements234and236to the metal shielding elements230, so as to form a closed loop structure for surrounding the metal shielding elements230and further reduce the crosstalk effect. It should be understood that the arrangements ofFIGS. 3A and 3Bare just exemplary, and they are not limitations of the invention.

FIG. 4is a diagram of a clock tree circuit400according to an embodiment of the invention.FIG. 4is similar toFIG. 1. The difference from the embodiments ofFIG. 1is that the clock tree circuit400further includes a first independent power source410. For example, the first independent power source410may be a low dropout regulator (LDO). The first independent power source410is configured to supply a part or a whole of the first tree circuit110. For example, the first independent power source410may supply all of the driving units of the first tree circuit110, or may only supply the fourth driving unit114, the fifth driving unit115, the sixth driving unit116, and the seventh driving unit117. The first independent power source410is different from the main power source (not shown), which supplies the circuits other than the first tree circuit110. With such a design, the first tree circuit110is not affected by the other circuits or the main power source, and it can provide pure and clear output signals. Other features of the clock tree circuit400ofFIG. 4are similar to those of the clock tree circuit100ofFIG. 1. Accordingly, the two embodiments can achieve similar levels of performance.

FIG. 5is a diagram of a clock tree circuit500according to an embodiment of the invention.FIG. 5is similar toFIG. 1. The difference from the embodiments ofFIG. 1is that the first tree circuit110of the clock tree circuit500further includes one or more metal shielding elements230, and the clock tree circuit500further includes a first independent power source410. Generally, the clock tree circuit500may be considered as a combination of the embodiments ofFIG. 2andFIG. 4, and it can further improve the quality of output signals. Other features of the clock tree circuit500ofFIG. 5are similar to those of the clock tree circuit100ofFIG. 1. Accordingly, the two embodiments can achieve similar levels of performance.

FIG. 6is a diagram of a clock tree circuit600according to an embodiment of the invention.FIG. 6is similar toFIG. 1. The difference from the embodiments ofFIG. 1is that the clock tree circuit600further includes a second clock source102and a second tree circuit120. The second clock source102is configured to generate a second signal S2, which may be a normal clock signal or a data strobe signal (DQS). The phase of the second signal S2may be the same as or different from that of the first signal S1. For example, the phase difference between the second signal S2and the first signal S1may be 0, 45, 90, 135, or 180 degrees. The second tree circuit120may include an eighth driving unit121, a ninth driving unit122, a tenth driving unit123, an eleventh driving unit124, a twelfth driving unit125, a thirteenth driving unit126, and a fourteenth driving unit127(the thirteenth driving unit126and the fourteenth driving unit127are optional). The second tree circuit120is disposed adjacent to the first tree circuit110, and is arranged to receive the second signal S2(e.g., the eighth driving unit121may have an input terminal for receiving the second signal S2) and drive next-stage circuits (not shown) accordingly. It should be understood that the inner structure of the second tree circuit120is similar or identical to that of the first tree circuit110, and the aforementioned inner structure has been described in the embodiments ofFIGS. 1-5. The first tree circuit110and the second tree circuit120can drive their respective next-stage circuits, which may be used to support similar functions. Other features of the clock tree circuit500ofFIG. 5are similar to those of the clock tree circuit100ofFIG. 1. Accordingly, the two embodiments can achieve similar levels of performance.

FIG. 7is a diagram of a clock tree circuit700according to an embodiment of the invention.FIG. 7is similar toFIG. 6. The difference from the embodiments ofFIG. 6is that the clock tree circuit700further includes a first independent power source410. The first independent power source410is configured to supply a part or a whole of the first tree circuit110and the second tree circuit120. For example, the first independent power source410may supply all of the driving units of the first tree circuit110and the second tree circuit120, or may only supply the fourth driving unit114, the fifth driving unit115, the sixth driving unit116, the seventh driving unit117, the eleventh driving unit124, the twelfth driving unit125, the thirteenth driving unit126, and the fourteenth driving unit127. Other features of the clock tree circuit700ofFIG. 7are similar to those of the clock tree circuit600ofFIG. 6. Accordingly, the two embodiments can achieve similar levels of performance.

FIG. 8is a diagram of a clock tree circuit800according to an embodiment of the invention.FIG. 8is similar toFIG. 6. The difference from the embodiments ofFIG. 6is that the clock tree circuit800further includes a first independent power source410and a second independent power source420. For example, the first independent power source410and the second independent power source420may be low dropout regulators. The first independent power source410and the second independent power source420may have the same or different supply voltages. The first independent power source410is configured to supply a part or a whole of the first tree circuit110, and the second independent power source420is configured to supply a part or a whole of the second tree circuit120. Other features of the clock tree circuit800ofFIG. 8are similar to those of the clock tree circuit600ofFIG. 6. Accordingly, the two embodiments can achieve similar levels of performance.

In some embodiments, the first tree circuit110and the second tree circuit120ofFIGS. 6-8each include one or more metal shielding elements230described in the embodiments ofFIGS. 2,3A, and3B, so as to further improve the quality of output signals.

FIG. 9is a diagram of a memory controller900according to an embodiment of the invention. The memory controller900is configured to control a memory device950, such as dynamic random-access memory (DRAM). As shown inFIG. 9, the memory controller900at least includes a first tree circuit110and multiple first transceivers961,962,963, and964. The inner structure of the first tree circuit110has been described in the embodiments ofFIGS. 1-5. In the embodiment ofFIG. 9, an input terminal of a first driving unit111of the first tree circuit110is arranged to receive a first data strobe signal (DQS) DQS1from the memory device950, and output terminals of a fourth driving unit114, a fifth driving unit115, a sixth driving unit116, and a seventh driving unit117of the first tree circuit110are arranged to drive the first transceivers961,962,963, and964, respectively. More particularly, the operations of the first tree circuit110and the first transceivers961,962,963, and964may be as follows. When performing a writing process, the first transceivers961,962,963, and964transmit multiple first bits SB1to the memory device950(e.g., to multiple DRAM cells). When performing a reading process, the first transceivers961,962,963, and964receive multiple first bits SB1from the memory device950(e.g., from multiple DRAM cells). The above writing and reading processes are performed according to the first data strobe signal DQS1, which are transmitted through the first tree circuit110from the memory device950. The first data strobe signal DQS1may be discontinuous and aperiodic, and it may be used as a clock signal for sampling the first bits SB1in the writing and reading processes. For example, the first data strobe signal DQS1may be outputted by the memory device950to the memory controller900only when the writing process or the reading process is performed. The first tree circuit110is used to buffer the first data strobe signal DQS1and reduce clock skew and/or clock jitter in the memory controller900. It should be understood that any one or more features of the embodiments ofFIG. 1-5, including the metal connection elements, the metal shielding elements, and the independent power sources, may be applied to the memory controller900so as to improve its performance, and these detailed features will be not described again here.

FIG. 10is a diagram of a memory controller910according to an embodiment of the invention.FIG. 10is similar toFIG. 9. The difference from the embodiments ofFIG. 9is that the memory controller910further includes a second tree circuit120and multiple second transceivers971,972,973, and974. The second tree circuit120is disposed adjacent to the first tree circuit110. The inner structure of the second tree circuit120is similar or identical to that of the first tree circuit110. In the embodiment ofFIG. 10, an input terminal of an eighth driving unit121of the second tree circuit120is arranged to receive a second data strobe signal (DQS) DQS2from the memory device950, and output terminals of an eleventh driving unit124, a twelfth driving unit125, a thirteenth driving unit126, and a fourteenth driving unit127of the second tree circuit120are arranged to drive the second transceivers971,972,973, and974, respectively. When performing a writing process, the second transceivers971,972,973, and974transmit multiple second bits SB2to the memory device950. When performing a reading process, the second transceivers971,972,973, and974receive multiple second bits SB2from the memory device950. The above writing and reading processes are performed according to the second data strobe signal DQS2. The second data strobe signal DQS2may be discontinuous and aperiodic, and it may be used as a clock signal for sampling the second bits SB2in the writing and reading processes. The second data strobe signal DQS2may be outputted by the memory device950to the memory controller910only when the writing process or the reading process is performed. The second tree circuit120is used to buffer the second data strobe signal DQS2and reduce clock skew and/or clock jitter in the memory controller910. It should be understood that any one or more features of the embodiments ofFIG. 1-8, including the metal connection elements, the metal shielding elements, and the independent power sources, may be applied to the memory controller910so as to improve its performance, and these features will be not described again here.

Although there are merely four or eight transceivers shown inFIGS. 9 and 10, it should be understood that the invention is not limited thereto. In other embodiments, the memory controller may include more transceivers for communicating with the memory device, and the tree circuit may include more driving units for driving the transceivers.