An example phase interpolator includes: a ring oscillator having a plurality of delay stages and a plurality of injection switches, each of the plurality of injection switches responsive to a differential reference clock signal and a first differential control signal; a supply control circuit configured to provide a regulated supply voltage to the ring oscillator in response to a first component of a second differential control signal; and a ground control circuit configured to provide a regulated ground voltage to the ring oscillator in response to a second component of the second differential control signal.

TECHNICAL FIELD

Examples of the present disclosure generally relate to electronic circuits and, in particular, to an injection-locked phase interpolator.

BACKGROUND

In a transceiver, such as a serializer/deserializer (SERDES), a dock delivery system can include a phase-locked loop (PLL) that generates one or more dock signals for use in transmitting and receiving data. A phase interpolator (PI) can be used to interpolate a dock signal by shifting its phase by a discrete amount over a given range. In a receiver, a PI is used to adjust the phase of the sampling dock used to sample the received data.

Conventional PIs tend to consume significant power, which may present challenges in low-power applications. An injection-locked oscillator (ILO) based PI is a low-power alternative. However, a conventional ILO-based PI has a limited range, especially across process, voltage, and temperature (PVT) variations. It is desirable to provide a PI that consumes less power than conventional PIs while having increased range as compared to conventional ILO-based PIs.

SUMMARY

In an example, a phase interpolator includes: a ring oscillator having a plurality of delay stages and a plurality of injection switches, each of the plurality of injection switches responsive to a differential reference clock signal and a first differential control signal; a supply control circuit configured to provide a regulated supply voltage to the ring oscillator in response to a first component of a second differential control signal; and a ground control circuit configured to provide a regulated ground voltage to the ring oscillator in response to a second component of the second differential control signal.

In another example, a receiver includes: sampling circuitry configured to sample an input signal based on a plurality of sampling clock signals; a clock and data recovery (CDR) circuit configured to generate a control signal in response to data and error samples output by the sampling circuitry; a clock generator configured to generate the plurality of sampling clock signals; and a phase interpolator configured to provide a plurality of clock signals to the clock generator in response to the control signal from the CDR circuit. The phase interpolator includes: a ring oscillator having a plurality of delay stages and a plurality of injection switches, each of the plurality of injection switches responsive to a differential reference clock signal and a first differential control signal; a supply control circuit configured to provide a regulated supply voltage to the ring oscillator in response to a first component of a second differential control signal; and a ground control circuit configured to provide a regulated ground voltage to the ring oscillator in response to a second component of the second differential control signal.

In another example, a method of phase interpolation includes: providing a differential reference clock signal and a first differential control signal to a plurality of injection switches in a ring oscillator; providing a regulated supply voltage to the ring oscillator in response to a first component of a second differential control signal; and providing a regulated ground control voltage to the ring oscillator in response to a second component of the second differential control signal.

DETAILED DESCRIPTION

Techniques for providing an injection-locked phase interpolator are described. In an example, the phase interpolator includes a divide-by-two injection-locked oscillator (ILO) that increases the deskew range by a factor of two across process, voltage, and temperature (PVT) variations while generating a four-phase in-phase (I) and quadrature (Q) clock. In addition, the divide-by-two ILO guarantees the quadrature accuracy. In an example, the phase interpolator includes a ring oscillator having a plurality of delay stages and a plurality of injection switches, where each of the plurality of injection switches responsive to a differential reference clock signal and a first differential control signal. A supply control circuit is configured to provide a regulated supply voltage to the ring oscillator in response to a first component of a second differential control signal. A ground control circuit configured to provide a regulated ground voltage to the ring oscillator in response to a second component of the second differential control signal.

The techniques described herein can be further understood with reference to basic ILO theory. The phase deskew (θ) from an ILO is dependent on the difference of the natural frequency of the VCO (f0) and the injected frequency (finj). In particular, if f1is in the locking range, then the following holds true:

Here, θ represents the phase shift of the ILO output with respect to the injecting clock. Now maximum deskew is fixed to ±90° from the equation above. However, given a lower frequency, there is more time to deskew the output clock. In particular, as employed by the techniques described herein, if the f0of a divide-by-two ILO is altered, then the deskew time is doubled for the same phase shift, as compared to an ILO with no division. Apart from doubling the deskew range, the techniques described herein also exploit the symmetric injection of a four-stage ring oscillator to avoid any tradeoff between the amount of deskew and quadrature accuracy. This allows generation of an accurate four-phase IQ clock for all amounts of deskew. These and further aspects are described below with respect to the drawings.

FIG. 1is a block diagram depicting an example of a serial communication system100. The serial communication system100comprises a transmitter112coupled to a receiver126over transmission medium160. The transmitter112can be part of a serializer-deserializer (SerDes)116. The receiver126can be part of a SerDes122. The transmission medium160comprises an electrical path between the transmitter112and the receiver126and can include printed circuit board (PCB) traces, vias, cables, connectors, decoupling capacitors, and the like. The receiver of the SerDes116, and the transmitter of the SerDes122, are omitted for clarity. In some examples, the SerDes116can be disposed in an integrated circuit (IC)110, and the SerDes122can be disposed in an IC120.

The transmitter112drives serial data onto the transmission medium160using a digital baseband modulation technique. In general, the serial data is divided into symbols. The transmitter112converts each symbol into an analog voltage mapped to the symbol. The transmitter112couples the analog voltage generated from each symbol to the transmission medium160. In some examples, the transmitter112uses a binary non-return-to-zero (NRZ) modulation scheme. In binary NRZ, a symbol is one bit of the serial data and two analog voltages are used to represent each bit. In other examples, the transmitter uses multi-level digital baseband modulation techniques, such as pulse amplitude modulation (PAM), where a symbol includes a plurality of bits of the serial data and more than two analog voltages are used to represent each bit.

The receiver126receives an analog signal from the transmission medium160. The receiver126includes a phase interpolator (PI)104for generating clocks to sample the analog signal. In an example, the PI104is a divider-based injection-locked oscillator (ILO). For example, the PI104can be a divide-by-two ILO that generates a four-phase clock (e.g., 0, 90, 180, and 270 degree phases). The receiver126provides recovered data to physical coding sublayer (PCS) circuitry128in SerDes122for decoding and further processing.

FIG. 2is a block diagram depicting the receiver126according to an example. The receiver126includes a continuous time linear equalizer (CTLE)203, an automatic gain control (AGC) circuit202, sampling circuitry204, deserializer208, a clock and data recovery (CDR) circuit210, the phase interpolator (PI)104, a clock generator206, and an adaptation circuit214. An output of the CTLE203is coupled to an input of the AGC circuit202. An output of the AGC circuit202is coupled to inputs of the sampling circuitry204. An output of the clock generator206is coupled to inputs of the sampling circuitry204. An output the sampling circuitry204is coupled to an input of the deserializer208. An output of the deserializer208is coupled to an input of the CDR circuit210. Outputs of the CDR circuit210are coupled to an input of the adaptation circuit214and an input of the PI104, respectively. Another input of the PI104is coupled to an output of a phase locked loop (PLL) circuit212. In an example, an output of the PI104is coupled to an input of the clock generator206. An output of the clock generator206is coupled to an input of the sampling circuitry204. Outputs of the adaptation circuit214are coupled to the CTLE203, the AGC circuit202, and the PCS circuitry128, respectively. In an example, the sampling circuitry204can be part of a decision feedback equalizer (DFE)205. In such case, another output of the adaptation circuit214is coupled to the DFE205.

In operation, the CTLE203receives an analog signal from the transmission medium160. The CTLE203operates as a high-pass filter to compensate for the low-pass characteristics of the transmission medium160. The peak of the frequency response of the CTLE203can be adjusted based on a CTLE adjust signal provided by the adaptation circuit214. The AGC circuit202receives the equalized analog signal from the CTLE203. The AGC circuit202adjusts the gain of the equalized signal based on a gain adjust signal provided by the adaptation circuit214. In another example, the AGC circuit202can precede the CTLE circuit203.

The sampling circuitry204generates data and crossing samples from the output of the AGC circuit202based in-phase (I) and quadrature (Q) clock signals output by the clock generator206. The sampling circuitry204can generate the data samples using the I clock signal and the crossing samples using the Q clock signal. In example, the sampling circuitry204is part of the DFE205. The DFE205equalizes the output of the AGC circuit202to minimize inter-symbol interference (ISI). The sampling circuitry204can include one or more data samplers216configured to generate data samples based on the I clock signal, and one or more edge samplers218configured to generate crossing samples based on the Q clock signal.

Each data and crossing sample includes one or more bits depending on the type of modulation scheme employed (e.g., one bit samples for binary NRZ and multi-bit samples for PAM). The deserializer208groups data samples and crossing samples to generate a deserialized signal. The deserializer208unifies the two separate parallel data and crossing sample streams into a deserialized signal to be processed by the CDR circuit210.

The CDR circuit210generates a PI control signal from the deserialized signal generated by the deserializer208. The PI104receives the PI control signal from the CDR circuit210and a reference clock signal from the PLL212. The PI104outputs a plurality of clock signals in response to the PI control signal and the reference clock signal. For example, the PI104can output four clock signals to the clock generator206successively shifted in phase by 90 degrees (e.g., 0, 90, 180, and 270 degree phases). The clock generator206generates the I and Q sampling clock signals from the clock signals output by the PI104.

The CDR circuit210outputs a data signal to the adaptation circuit214. The data signal includes the data samples output by the sampling circuitry204. The adaptation circuit214generates control signals for the CTLE203and the AGC circuit202based on data signal using known algorithms. If the DFE205is present, the adaptation circuit214generates a control signal for adjusting the taps of the DFE205using a known algorithm. The adaptation circuit214outputs the data signal to the PCS circuitry128. The PCS circuitry128processes the data signal to recover the transmitted data.

FIG. 3is a block diagram depicting the PI104and the clock generator206according to an example. The PI104includes a ring oscillator302, a supply control circuit306, and a ground control circuit308. The clock generator206includes a pulse generator310and an ILO312.

The supply control circuit306generates a voltage Vcc_reg from a supply voltage Vcc. The ground control circuit308generates a voltage Vss_reg from a ground voltage Vss. The supply control circuit306receives an M-bit signal, deskew_b, and an N-bit signal, calib_b, where M and N are positive integers. The ground control circuit308receives an M-bit signal, deskew, and an N-bit signal, calib. The M logic signals comprising the deskew signal are logical complements of the M logic signals comprising the deskew_b signal (denoted by the suffix “_b”). Likewise, the N logic signals comprising the calib signal are logical complements of the N logic signals comprising the calib_b input. The supply control circuit306generates the voltage Vcc_reg based on the deskew_b and calib_b signals, as described further below. The ground control circuit308generates the voltage Vss_reg based on the deskew and calib signals, as described further below. The deskew and deskew_b signals are provided by the CDR circuit210. The calib and calib_b signals can be provided by the CDR210or by another control circuit (not shown).

The ring oscillator302includes a plurality of delay stages305and a plurality of injection switches304. The ring oscillator302receives a differential clock comprising a clock signal clk and its logical complement clk_b. The ring oscillator302also receives a K-bit signal injs and its logical complement injs_b, where K is a positive integer. The ring oscillator302outputs an in-phase (I) clock and its logical complement I_b. The ring oscillator302also outputs a quadrature (Q) clock signal and its logical complement Q_b. The Q clock signal is ninety degrees out of phase with respect to the I clock signal. The ring oscillator302receives the supply voltage Vcc_reg from the supply control circuit306and the ground voltage Vss_reg from the ground control circuit308. The ring oscillator302includes a plurality of injection switches304that inject the frequency of the clk signal into the ring oscillator302. In examples discussed below, the ring oscillator302includes four delay stages305and two injection switches304, where the injection switches304are positioned after the first and third delay stages. The injs signal controls the strength of the injection performed by the injection switches304.

In operation, the CDR circuit210generates the differential deskew signal as at least a portion of the PI control signal. The differential deskew signal (deskew and deskew_b) controls the Vcc_reg and Vss_reg voltages, which in turn controls the oscillation frequency of the ring oscillator302. By adjusting the Vcc_reg and Vss_reg voltages, the natural frequency of the ring oscillator302is changed. When the supply voltage applied to the ring oscillator302is reduced, the oscillation frequency is reduced and vice versa. Both the supply control circuit306and the ground control circuit308are controlled in unison so that the common mode of the output of the ring oscillator302remains at Vcc/2. This obviates the need for AC coupling of the output of the ring oscillator302to the clock generator206. The differential calib signal (calib and calib_b) can be used to provide a PVT calibration. For example, a PVT calibration can be performed by observing the frequency of the unlocked ring oscillator302and altering the calib signal to bring the oscillation frequency near the injected frequency.

The pulse generator310generates a sequence pulses in response to the differential I and Q clock signals output by the ring oscillator302. The pulses output by the pulse generator310are injected into the ILO312, which outputs I and Q sampling clock signals.

FIG. 4is a schematic diagram depicting the ring oscillator302according to an example. The ring oscillator302includes inverters4021-2,4041-2,4061-2, and4081-2. The inverter pair4021-2implements a first delay stage305, the inverter pair4041-2implements a second delay stage305, the inverter pair4061-2implements a third delay stage305, and the inverter pair4081-2implements a fourth delay stage305. The inverters4021through4081are coupled in series output-to-input. Likewise, the inverters4022through4082are coupled in series output-to-input. An output of the inverter4081is coupled to an input of the inverter4022. An output of the inverter4082is coupled to an input of the inverter4021. Each of the inverters402receives the supply voltage Vcc_reg and the ground voltage Vss_reg.

The ring oscillator302also includes a first cross-coupled pair of inverters4101and4102, a second cross-coupled pair of inverters4121and4122, a third cross-coupled pair of inverters4141and4142, and a fourth cross-coupled pair of inverters4161and4162. The first cross-coupled pair of inverters410is coupled between the output of the inverter4021and the output of the inverter4022. The second cross-coupled pair of inverters412is coupled between the output of the inverter4041and the output of the inverter4042. The third cross-coupled pair of inverters414is coupled between the output of the inverter4061and the output of the inverter4062. The fourth cross-coupled pair of inverters416is coupled between the output of the inverter4081and the output of the inverter4082. The cross-coupled inverter pairs are provided to satisfy the oscillation criteria of the ring oscillator302.

The ring oscillator302includes two injection switches3041and3042. The injection switch3041is coupled between the output of the inverter4021and the output of the inverter4022. The injection switch3042is coupled between the output of the inverter4061and the output of the inverter4062. The output of the inverter4041supplies the I clock signal, and the output of the inverter4042supplies the I_b clock signal. The output of the inverter4081supplies the Q clock signal, and the output of the inverter4082supplies the Q_b clock signal. In this manner, the ring oscillator302provides a divide-by-two ILO.

FIG. 5is a schematic diagram depicting an injection switch304according to an example. The injection switch includes a plurality of stages506, e.g., three stages5061through5063. In such case, the injs signal includes K=3 bits (one per stage506). Each stage506includes n-channel field effect transistors (FETs) MN1through MN3(e.g., N-type metal oxide semiconductor FETs (MOSFETs)) and p-channel FETs MP1through MP3(e.g., P-type MOSFETs). A drain of the transistor MN1is coupled to a node502. A source of the transistor MN1is coupled to the drain of the transistor MN2. A source of the transistor MN2is coupled to a drain of the transistor MN3. A source of the transistor MN3is coupled to a node504. A source of the transistor MP1is coupled to the node502. A drain of the transistor MP1is coupled to a source of the transistor MP2. A drain of the transistor MP2is coupled to a source of the transistor MP3. A drain of the transistor MP3is coupled to the node504. The source of the transistor MN1, the drain of the transistor MP1, the drain of the transistor MN2, and the source of the transistor MP2is a common node. The source of the transistor MN2, the drain of the transistor MP2, the drain of the transistor MN3, and the source of the transistor MP3is another common node.

For each stage506, the gate of the transistor MN2receives one component of the differential reference clock (e.g., clk) and the gate of the transistor MP2receives the other component of the differential reference clock (e.g. clk_b). For the stages5061through5063, the gate of each transistor MN1receives a respective one of injs<0> through injs<2> (where injs<x> is the xth logic signal of the 3-bit injs signal). For the stages5061through5063, the gate of each transistor MN3receives a respective one of injs<0> through injs<2>. For the stages5061through5063, the gate of each transistor MP1receives a respective one of injs_b<0> through injs_b<2>. For the stages5061through5063, the gate of each transistor MP3receives a respective one of injs_b<0> through injs_b<2>.

In operation, the differential reference clock provided by the PLL212is coupled to the gates of the transistors MN2, MP2in each stage506. The injection switch304is coupled between inverter outputs at the nodes502,504. The differential injection signal injs controls the injection strength of the clock signal clk.

FIG. 6is a schematic diagram depicting the supply control circuit306according to an example. The supply control circuit306includes a first plurality of stages602, e.g., stages6021through6023. The supply control circuit306includes a second plurality of stages604, e.g., stages6041through6045. In such an example, the calib_b signal includes 3 bits (e.g., N=3) and the deskew_b signal includes 5 bits (e.g., M=5). Each stage602,604includes a p-channel FET MPcc and a resistor Rcc. The source of the transistor MPcc is coupled to a supply voltage Vcc. A drain of the transistor MPcc is coupled to the resistor Rcc. The resistor Rcc is coupled between the drain of the transistor MPc and the node supplying the regulated voltage Vcc_reg. In the present example, the regulated supply voltage is generated using eight control bits (e.g., 3 bits of the calib signal and 5 bits of the deskew signal). The CDR circuit210provides the deskew signal and can also provide the calib signal. Alternatively, the calib signal can be provided by another control circuit. Adjusting the value of the deskew and calib signals adjusts the value of Vcc_reg, which in turn adjusts the oscillation frequency of the ring oscillator302.

FIG. 7is a schematic diagram depicting the ground control circuit308according to an example. The ground control circuit308includes a first plurality of stages702, e.g., stages7021through7023. The ground control circuit308includes a second plurality of stages704, e.g., stages7041through7045. In such an example, the calib signal includes 3 bits (e.g., N=3) and the deskew signal includes 5 bits (e.g., M=5). Each stage702,704includes an n-channel FET MNss and a resistor Rss. The source of the transistor MNss is coupled to a supply voltage Vss. A drain of the transistor MNss is coupled to the resistor Rss. The resistor Rss is coupled between the drain of the transistor MNss and the node supplying the regulated voltage Vss_reg. In the present example, the regulated ground voltage is generated using eight control bits (e.g., 3 bits of the calib signal and 5 bits of the deskew signal). The CDR circuit210provides the deskew signal and can also provide the calib signal. Alternatively, the calib signal can be provided by another control circuit. Adjusting the value of the deskew and calib signals adjusts the value of Vss_reg, which in turn adjusts the oscillation frequency of the ring oscillator302.

The PI104described above can be implemented within an integrated circuit, such as a field programmable gate array (FPGA) or like type programmable circuit.FIG. 8illustrates an architecture of FPGA800that includes a large number of different programmable tiles including multi-gigabit transceivers (“MGTs”)1, configurable logic blocks (“CLBs”)2, random access memory blocks (“BRAMs”)3, input/output blocks (“IOBs”)4, configuration and clocking logic (“CONFIG/CLOCKS”)5, digital signal processing blocks (“DSPs”)6, specialized input/output blocks (“I/O”)7(e.g., configuration ports and clock ports), and other programmable logic8such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (“PROC”)10. FPGA800can include one or more instances of SerDes122described above.

In some FPGAs, each programmable tile can include at least one programmable interconnect element (“INT”)11having connections to input and output terminals20of a programmable logic element within the same tile, as shown by examples included at the top ofFIG. 8. Each programmable interconnect element11can also include connections to interconnect segments22of adjacent programmable interconnect element(s) in the same tile or other tile(s). Each programmable interconnect element11can also include connections to interconnect segments24of general routing resources between logic blocks (not shown). The general routing resources can include routing channels between logic blocks (not shown) comprising tracks of interconnect segments (e.g., interconnect segments24) and switch blocks (not shown) for connecting interconnect segments. The interconnect segments of the general routing resources (e.g., interconnect segments24) can span one or more logic blocks. The programmable interconnect elements11taken together with the general routing resources implement a programmable interconnect structure (“programmable interconnect”) for the illustrated FPGA.

In an example implementation, a CLB2can include a configurable logic element (“CLE”)12that can be programmed to implement user logic plus a single programmable interconnect element (“INT”)11. A BRAM3can include a BRAM logic element (“BRL”)13in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements included in a tile depends on the height of the tile. In the pictured example, a BRAM tile has the same height as five CLBs, but other numbers (e.g., four) can also be used. A DSP tile6can include a DSP logic element (“DSPL”)14in addition to an appropriate number of programmable interconnect elements. An10B4can include, for example, two instances of an input/output logic element (“IOL”)15in addition to one instance of the programmable interconnect element11. As will be clear to those of skill in the art, the actual I/O pads connected, for example, to the I/O logic element15typically are not confined to the area of the input/output logic element15.

Some FPGAs utilizing the architecture illustrated inFIG. 8include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, processor block10spans several columns of CLBs and BRAMs. The processor block10can various components ranging from a single microprocessor to a complete programmable processing system of microprocessor(s), memory controllers, peripherals, and the like.