Self-aligned charge-trapping layers for non-volatile data storage, processes of forming same, and devices containing same

A discrete storage element film is disposed above a tunneling dielectric film against a shallow trench isolation structure and under conditions to resist formation of the discrete storage element film upon vertical exposures of the shallow trench isolation structure. A discrete storage element film is also disposed above a tunneling dielectric film against a recessed isolation structure. A microelectronic device incorporates the discrete storage element film. A computing system incorporates the microelectronic device.

TECHNICAL FIELD

Embodiments of the present invention relate generally to semiconductor devices and more particularly to processes for forming non-volatile semiconductor memory devices.

TECHNICAL BACKGROUND

Semiconductor miniaturization creates challenges that can affect semiconductor device performance and reliability. For non-volatile memory (NVM) devices, such as electrically erasable programmable read-only memory (EEPROM) devices, the leakage of charge stored in a memory cell's floating gate can be a challenge.

DETAILED DESCRIPTION

The present disclosure relates to discrete storage element formation for non-volatile memory semiconductor fabrication.

The following description includes terms, such as upper, lower, first, second, etc. that are used for descriptive purposes only and are not to be construed as limiting. The embodiments of an apparatus or article described herein can be manufactured, used, or shipped in a number of positions and orientations. The terms “die” and “chip” generally refer to the physical object that is the basic workpiece transformed by various process operations into the desired integrated circuit device. A die is usually singulated from a wafer, and wafers may be made of semiconducting, non-semiconducting, or combinations of semiconducting and non-semiconducting materials. A board is typically a resin-impregnated fiberglass structure that acts as a mounting substrate for the die.

The term “discrete storage element” can mean a nano-sized crystalline material that has been located upon a tunneling dielectric film. The term “nanocrystal memory” can mean the nano-sized crystalline material that has been located upon a tunneling dielectric film and that has been incorporated into a memory device such as a nonvolatile memory structure.

Discrete storage element (nanocrystal) memory gates use isolated semiconductive or conductive nanocrystals as discrete storage elements to store the charge in the floating gate. The isolated nature of the nanocrystals reduces the vulnerability of the floating gate to charge leakage that can result from defects in the tunnel dielectric layer. Instead of providing a leakage path for the entire floating gate, the defect(s) provide a leakage path only for individually charged nanocrystals.

Important considerations with respect to nanocrystal fabrication include the density of nanocrystals and the uniformity of the nanocrystal electronic tunneling distance. Higher nanocrystal densities lead to an increased change in the threshold voltage and less overall variability in the distribution of threshold voltages across the memory array. Uniform tunneling distances facilitate reproducible charging and discharging of the floating gate.

Reference will now be made to the drawings wherein like structures will be provided with like reference designations. In order to show the structures of embodiments most clearly, the drawings included herein are diagrammatic representations of various embodiments. Thus, the actual appearance of the fabricated structures, for example in a photomicrograph, may appear different while still incorporating the structures of embodiments. Moreover, the drawings show only the structures useful to understand the embodiments. Additional structures known in the art have not been included to maintain the clarity of the drawings.

FIG. 1Ais a cross-section elevation of a microelectronic device100during processing according to an embodiment. A substrate110is depicted with a gate oxide layer112disposed on one surface. In an embodiment, the substrate110is a semiconductive material and the gate oxide layer112is a thermally grown oxide film that can be prepared by a wafer supplier. The gate oxide layer112can also be referred to as a tunneling oxide or a tunneling dielectric layer.

FIG. 1Bis a cross-section elevation of the microelectronic device depicted inFIG. 1Aafter further processing according to an embodiment. The microelectronic device101has been processed with a bulk dielectric film114such as a nitride layer including for example, Si3N4and more generically SixNy. The microelectronic device101can also be processed with a bulk dielectric film114such as polysilicon. The microelectronic device101can also be processed with a bulk dielectric film114such as an oxide layer that has a different etch response from other oxide structures it may be near. The bulk dielectric film114can be a non-oxide dielectric in an embodiment.

FIG. 1Cis a cross-section elevation of the microelectronic device depicted inFIG. 1Bafter further processing according to an embodiment. The microelectronic device102has been processed by patterning the bulk dielectric film114(FIG. 1B) to a shallow-trench isolation pattern (STI) film115, and an STI structure116has been filled into the STI pattern film115, and into the substrate110. Further processing is also depicted inFIG. 1C, such that etchback processing has given the STI structure116a height118above a repaired gate oxide layer113for a given application.

FIG. 1Dis a cross-section elevation of the microelectronic device depicted inFIG. 1Cafter further processing according to an embodiment. The microelectronic device103has been processed to remove the STI pattern film115(FIG. 1C, which was a sacrificial film115). During processing, a wet etch has been done, according to an embodiment, and the gate oxide layer112(FIG.1C) has acted as an etch stop. The gate oxide layer113, however, has been slightly altered and is referred to herein as an etch stop layer113. The STI structure116exhibits a prominence above the etch stop layer113. Further, the STI structure116exhibits a sidewall104.

FIG. 1Eis a cross-section elevation of the microelectronic device depicted inFIG. 1Dafter further processing according to an embodiment. The microelectronic device109exhibits a repaired etch stop layer113(FIG. 1D). In an embodiment, the repaired etch stop layer113has been thermally regrown to form a tunneling dielectric layer120.

FIG. 1Fis a cross-section elevation of the microelectronic device depicted inFIG. 1Eafter further processing according to an embodiment. The microelectronic device105has been sputter treated to form a discontinuous film of discrete nanocrystals122. The nanocrystals122are also referred to as a charge-trapping layer122. In an embodiment, the nanocrystals122are formed from a sputtered metallic target such as a silver target. In an embodiment, the nanocrystals122are sputtered from nickel. In an embodiment, the nanocrystals122are sputtered from copper. In an embodiment, the nanocrystals122are sputtered from platinum or a platinum-group metal. In an embodiment, a non-metallic material is used as the charge-trapping layer122. In an embodiment, the nanocrystals122are sputtered from a silicon nitride target. The silicon nitride can be Si3N4or another silicon nitride such as SiN. In an embodiment, the silicon nitride is a non-stoichiometric blend of silicon and nitrogen.

In an embodiment, formation of the charge-trapping layer122is done by collimated sputtering. In an embodiment, formation of the charge-trapping layer122is done by a directional plasma deposition.

In any of the disclosed embodiments of forming the charge-trapping layer122, the sidewall104acts as another separator between charge-trapping layers.

FIG. 1Falso depicts incidental nanocrystals124that are located upon the STI structure116. As depicted inFIG. 1Fhowever, the height118of the STI structure116along with the directional deposition of the charge-trapping layer122, has created a self-aligned breach between the charge-trapping layer122as deposited above the tunneling dielectric layer120where it is required, and the incidental nanocrystals124. Consequently, the proclivity for charge leaking through a given layer of incidental nanocrystals125is significantly reduced across a given STI structure117, between a first active area126and a second active area127. Because of the topology of the STI structure117and because no extra processing is needed to create the isolation of the charge-trapping layer122between the STI structures116and117, a significant reduction in charge leaking is achieved. Similarly, because of the directional formation of the charge-trapping layer122, the likelihood of the nanocrystals to be found upon the vertical sidewall104is also significantly reduced. This topology is sometimes referred to as “reentrant”, meaning that it is difficult to form deposits upon the substantially vertical structures with respect to a directional deposition. This topology is also referred to as a “reentrant undercut” form factor.

Further, as the charge-trapping layer122is formed as discrete sections, the granular quality of the charge-trapping layer122also contributes to reduced charge leaking at a boundary. In an embodiment, the height118is about 7 nm and the width of a given active area126is about 35 nm.

FIG. 1Gis a cross-section elevation of the microelectronic device depicted inFIG. 1Fafter further processing according to an embodiment. The microelectronic device106has been processed with a control gate dielectric130deposition to seal up the charge-trapping layer122. The control gate dielectric130is a high-k dielectric material according to an embodiment. In an embodiment, the control gate dielectric130is an undoped chemical vapor deposition (CVD) oxide layer. Incidental formation of the dielectric is located on the STI structure116at item132. In an embodiment, the control gate dielectric130is formed using other deposition processes and includes other dielectric materials or combinations of dielectric materials, such as an oxide-nitride-oxide (ONO) film stack, or the like.

FIG. 1His a cross-section elevation computer-enhanced photomicrograph of a microelectronic device during processing according to an embodiment. The photomicrograph107depicts a scale of 100 nanometers (nm). The photomicrograph107was taken from a structure such as the microelectronic device106depicted inFIG. 1G. The control gate dielectric130has been computer enhanced for clarity. The charge-trapping layer122and the STI structures116and117have also been computer enhanced. A control gate film134is depicted as having been deposited over the substrate110and the topology built upon the substrate110. The control gate film134has also been computer enhanced. In an embodiment, the control gate film134is a doped polycrystalline silicon material. In an embodiment, the control gate film134is a metallic material.

FIG. 1Halso illustrates a distinct breach between the charge-trapping layer122and the incidental nanocrystals124, due to the pillar form-factor of the STI structures116and117, and the directional deposition of the charge-trapping layer122that has formed a reentrant quality upon the tunneling dielectric layer120.

FIG. 1Jis a cross-section elevation of the microelectronic device depicted inFIG. 1Hafter further processing according to an embodiment. The microelectronic device108has been processed such that the control gate film134(FIG. 1H) has been planarized. In an embodiment, the control gate film135is planarized by chemical-mechanical planarization (CMP) until a selected depth is achieved.

FIG. 2is a cross-section elevation of the microelectronic device depicted inFIG. 1J, taken from a different view according to an embodiment. The section line2-2inFIG. 1Jreveals the view depicted inFIG. 2. The substrate110and the tunneling dielectric layer120support the charge-trapping layer122. The control gate dielectric130insulates the charge-trapping layer122from the control gate film135. As depicted a floating gate stack200is illustrated.

FIG. 3is a cross-section elevation of the microelectronic device300according to an embodiment. The elevation inFIG. 3is similar in cross-section as the elevation depicted inFIG. 2. A substrate310and a tunneling dielectric layer320support a charge-trapping layer322that has been directionally and self-aligning deposited as described herein. A control gate dielectric330insulates the charge-trapping layer322from a control gate film335A dielectric spacer336has been formed as part of the floating gate stack.

FIG. 4is a flow chart400that describes process flow embodiments.

At410, the process includes forming an STI structure with a prominence and a sidewall, above a substrate that includes a tunneling dielectric layer.

At420, the process includes forming a discrete storage element film on the tunneling dielectric film that is adjacent and contiguous to the STI structure. The process is carried out to minimize formation of the discrete storage element film upon the sidewall.

At430, a control gate (word line) is formed above the discrete storage element film to form a microelectronic device.

At440the microelectronic device is installed into a computing system.

FIG. 5is a cross-section elevation of a microelectronic device500during processing according to an embodiment. A substrate510is depicted with a thermally regrown tunneling dielectric layer520disposed on one surface. The structure depicted inFIG. 5essentially an inverted topology compared to the structure depicted inFIG. 1J. In other words, an isolation structure517exhibits depressed topology compared to a prominence of the substrate510between two occurrences of the isolation structure517. Further processing has been carried out to achieve a charge-trapping layer according to an embodiment, such that the microelectronic device500has been sputter treated to form a discontinuous film of discrete nanocrystals522. The nanocrystals522are also referred to as a charge-trapping layer522. In an embodiment, the nanocrystals522are formed from a sputtered metallic target such as a silver target. In an embodiment, the nanocrystals522are sputtered from nickel. In an embodiment, the nanocrystals522are sputtered from copper. In an embodiment, the nanocrystals522are sputtered from platinum or a platinum-group metal. In an embodiment, a non-metallic material is used as the charge-trapping layer522. In an embodiment, the nanocrystals522are sputtered from a silicon nitride target. The silicon nitride can be Si3N4or another silicon nitride such as SiN. In an embodiment, the silicon nitride is a non-stoichiometric blend of silicon and nitrogen.

In any of the disclosed embodiments of forming the charge-trapping layer522, the tunneling dielectric520acts as another separator between charge-trapping layers.FIG. 5also depicts incidental nanocrystals524that are located upon the isolation structure517. As depicted inFIG. 5, however, the depth518of the isolation structure517, along with the directional deposition of the charge-trapping layer522, has created a self-aligned breach between the charge-trapping layer522as deposited above the tunneling dielectric layer520where it is required, and the incidental nanocrystals524. Consequently, the proclivity for charge leaking through a given layer of incidental nanocrystals524is significantly reduced across a given isolation structure517, between a first active area526and a second active area527. Because of the topology of the isolation structure517and because no extra processing is needed to create the isolation of the charge-trapping layer522between the isolation structures516and517, a significant reduction in charge leaking is achieved.

Further, as the charge-trapping layer522is formed as discrete sections, the granular quality of the charge-trapping layer522also contributes to reduced charge leaking at a boundary. In an embodiment, the depth518is about 7 nm and the width of a given active area526is about 35 nm.

FIG. 5illustrates further processing with a control gate dielectric530deposition to seal up the charge-trapping layer522. The control gate dielectric530is a high-k dielectric material according to an embodiment. In an embodiment, the control gate dielectric530is an undoped CVD oxide layer. Incidental formation of the dielectric is located on the isolation structure517at item532.

The microelectronic device500has also been processed such that a control gate film535has been deposited and planarized. The view taken along the line2-2is also useful inFIG. 5, when viewed in side-section atFIG. 2.

FIG. 6is a flow chart600that describes process flow embodiments that relate to the structure depicted inFIG. 5.

At610, the process includes forming an isolation structure below an upper surface of a substrate that includes a tunneling dielectric layer.

At620, the process includes forming a discrete storage element film on the tunneling dielectric film that is adjacent and contiguous to the isolation structure.

At630, a control gate (word line) is formed above the discrete storage element film to form a microelectronic device.

At640, the microelectronic device is installed into a computing system.

FIG. 7is a schematic of an electronic system700according to an embodiment. The electronic system700, also referred to as a computing system700, incorporates at least one microelectronic device, such as an IC die with a floating gate with a discrete storage element film as illustrated inFIGS. 1J,2, and3. In an embodiment, the electronic system700is a computer system that includes a system bus720to electrically couple the various components of the electronic system700. The system bus720is a single bus or any combination of busses according to various embodiments. The electronic system700includes a voltage source730that provides power to the integrated circuit710. In some embodiments, the voltage source730supplies current to the integrated circuit710through the system bus720.

The integrated circuit710is electrically coupled to the system bus720and includes any circuit or combination of circuits according to an embodiment. In an embodiment, the integrated circuit710includes a processor712that can be of any type. As used herein, the processor712can be referred to as a “first die.” The processor means any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. Accordingly, a floating gate with a discrete storage element film can be part of the electronic system that seats at least one die such as a processor or a die selected from a processor or another die that is part of a chipset. Other types of circuits that can be included in the integrated circuit710are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit714for use in wireless devices such as cellular telephones, pagers, portable computers, two-way radios, and similar electronic systems. In an embodiment, the integrated circuit710includes on-die memory716such as static random-access memory (SRAM). In an embodiment, the integrated circuit710includes on-die memory716such as embedded dynamic random-access memory (eDRAM).

In an embodiment, the electronic system700also includes an external memory740that in turn may include one or more memory elements suitable to the particular application, such as a main memory742in the form of random-access memory (RAM), one or more hard drives744, and/or one or more drives that handle removable media746, such as diskettes, compact disks (CDs), digital video disks (DVDs), flash memory keys with a floating gate with a discrete storage element film, and other removable media known in the art. In an embodiment, any portion or all of the external memory740can be referred to as a “second die.”

In an embodiment, the electronic system700also includes a display device750and an audio output760. In an embodiment, the electronic system700includes an input770, such as a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other device that inputs information into the electronic system700.

As shown herein, the integrated circuit710can be implemented in a number of different embodiments, including an electronic package, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes the floating gate with a discrete storage element film as set forth herein in the various embodiments and their art-recognized equivalents. The electronic system can be contained within a housing780, such as the skin of a hand-held device, for example, a cell phone or a personal digital assistant (PDA). The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular packaging requirements.

This Detailed Description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosed embodiments. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present disclosure. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments.

The term “horizontal” as used in this document is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The Detailed Description is, therefore, not to be taken in a limiting sense, and the scope of this disclosure is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

It will be readily understood to those skilled in the art that various other changes in the details, material, and arrangements of the parts and method stages that have been described and illustrated in order to explain the nature of these embodiments may be made without departing from the principles and scope of the inventions as expressed in the subjoined claims.