Integrated circuit scan testing with stop-clock and auto-step features

Apparatus having corresponding methods and computer-readable media comprise a function module to operate according to a clock signal; a clock control module to provide a clock gate signal; and a clock gate module to provide the clock signal to the function module only until the clock control module provides the clock gate signal; wherein the function module includes a plurality of storage elements, wherein the storage elements form a scan chain in response to a mode signal; and wherein the scan chain is configured to shift data stored therein out of the scan chain.

FIELD

The present invention relates generally to testing integrated circuits. More particularly, the present invention relates to scan testing of integrated circuits.

BACKGROUND

Modern integrated circuits generally comprise a large number of circuit elements. It is desirable to test these circuit elements in order to ensure the proper operation of the integrated circuit. However, the number of test points (that is, locations where signals can be measured) is limited by the number of terminals of the integrated circuit, which are vastly outnumbered by the number of circuit elements to be tested.

Consequently, designers of modern integrated circuits often employ test techniques referred to herein as “scan testing.” According to scan testing, a mode signal can be asserted that causes predetermined storage elements within an integrated circuit to connect serially to form a scan chain. Data can be shifted into, and out of, the scan chain. Before a test begins, a test vector can be shifted into the scan chain to provide a known starting point for the test. At the end of the test, data can be shifted out of the scan chain for analysis. During the test, the mode signal is negated, thereby breaking the scan chain, so that the integrated circuit can be tested in its nominal configuration. The clock signal is then toggled slowly to simulate nominal operation.

However, it is desirable to test integrated circuits with the clock at full speed, rather than at reduced speed, in order to identify problems that only appear during full-speed operation.

SUMMARY

In general, in one aspect, an embodiment features an apparatus comprising a function module to operate according to a clock signal; a clock control module to provide a clock gate signal; and a clock gate module to provide the clock signal to the function module only until the clock control module provides the clock gate signal; wherein the function module includes a plurality of storage elements, wherein the storage elements form a scan chain in response to a mode signal; and wherein the scan chain is configured to shift data stored therein out of the scan chain.

Embodiments of the apparatus can include one or more of the following features. In some embodiments, the clock control module provides the clock gate signal responsive to one or more monitored signals. Some embodiments comprise a clock module to provide the clock signal. In some embodiments, the clock control module comprises: a cycle register to store an offset integer N; a clock counter to count cycles of the clock signal subsequent to a trigger signal; and a comparator to provide the clock gate signal responsive to the clock counter counting N cycles of the system clock. Some embodiments comprise a trigger module to provide the trigger signal responsive to the one or more monitored signals. Some embodiments comprise an auto-step module to increment offset integer N in the cycle register subsequent to the data stored in the scan chain being shifted out of the scan chain. In some embodiments, the clock gate module provides the clock signal to the function module, subsequent to the auto-step module incrementing offset integer N, until the clock control module provides the clock gate signal; the storage elements form a scan chain in response to the mode signal; and data stored in the scan chain is shifted out of the scan chain. Some embodiments comprise an integrated circuit comprising the apparatus. Some embodiments comprise a field-programmable gate array comprising the apparatus. Some embodiments comprise a mode module to provide the mode signal; and a test data module to capture the data stored in the scan chain.

In general, in one aspect, an embodiment features a method for testing an integrated circuit, wherein the integrated circuit includes a clock module to provide a clock signal and a function module to operate according to the clock signal, the method comprising providing the clock signal to the function module only until a clock gate signal is provided, wherein the function module includes a plurality of storage elements; providing a mode signal subsequent to provision of the clock gate signal, wherein the storage elements form a scan chain in response to the mode signal; and capturing data stored in the scan chain subsequent to provision of the mode signal.

Embodiments of the method can include one or more of the following features. Some embodiments comprise providing the clock gate signal responsive to one or more monitored signals. Some embodiments comprise providing a trigger signal responsive to the one or more monitored signals; and providing the clock gate signal N cycles of the clock signal subsequent to provision of the trigger signal. Some embodiments comprise incrementing N subsequent to capturing the data stored in the scan chain. Some embodiments comprise providing the clock signal to the function module, subsequent to incrementing N, only until the clock gate signal is provided; providing the mode signal subsequent to provision of the clock gate signal, wherein the storage elements form a scan chain in response to the mode signal; and capturing data stored in the scan chain subsequent to provision of the mode signal.

In general, in one aspect, an embodiment features computer-readable media embodying instructions executable by a computer to perform a method for testing an integrated circuit, wherein the integrated circuit includes a clock module to provide a clock signal and a function module to operate according to the clock signal, the method comprising providing the clock signal to the function module only until a clock gate signal is provided, wherein the function module includes a plurality of storage elements; providing a mode signal subsequent to provision of the clock gate signal, wherein the storage elements form a scan chain in response to the mode signal; and capturing data stored in the scan chain subsequent to provision of the mode signal.

Embodiments of the computer-readable media can include one or more of the following features. In some embodiments, the method further comprises: providing the clock gate signal responsive to one or more monitored signals. In some embodiments, the method further comprises: providing a trigger signal responsive to the one or more monitored signals; and providing the clock gate signal N cycles of the clock signal subsequent to provision of the trigger signal. In some embodiments, the method further comprises: incrementing N subsequent to capturing the data stored in the scan chain. In some embodiments, the method further comprises: providing the clock signal to the function module, subsequent to incrementing N, only until the clock gate signal is provided; providing the mode signal subsequent to provision of the clock gate signal, wherein the storage elements form a scan chain in response to the mode signal; and capturing data stored in the scan chain subsequent to provision of the mode signal.

The leading digit(s) of each reference numeral used in this specification indicates the number of the drawing in which the reference numeral first appears.

DETAILED DESCRIPTION

Embodiments of the present disclosure provide integrated circuit scan testing with a stop-clock feature. That is, the internal function clock of the integrated circuit can be stopped at a predetermined time, upon the occurrence of one or more predetermined conditions, and the like. This stop-clock feature allows an integrated circuit to be operated at full speed until the clock is stopped, at which time a scan chain can be formed to extract data from the integrated circuit for analysis.

Some embodiments of the present disclosure also provide an auto-step feature. This auto-step feature allows the stop-clock feature to stop the function clock at each of a plurality of consecutive clock cycles to create a time sequence of analysis data. According to the auto-step feature, the stop-clock feature is used to stop the function clock N cycles after a predetermined time, or after the occurrence of one or more predetermined conditions, where N is a non-negative integer. After the scan data is extracted, the auto-step feature increments N and then employs the stop-clock feature again, and extracts the resulting data. This process can be repeated as many times as desired to create a time sequence of test data of any length.

The stop-clock and auto-step features can be implemented in integrated circuits in silicon for post-silicon testing, as a field-programmable gate arrays (FPGA) for FPGA validation, or the like. Post-silicon validation is a common and critical step in verifying a design. Post-silicon embodiments permit post-silicon validation using the internal function clock. Test data can therefore be referenced to the function clock, rather than to an external scan clock.

In conventional FPGA validation, an FPGA chip is programmed to represent the design. Then tests are run on the FPGA platform at frequencies that are generally much slower than those to be used in the final product. However, to probe the internal design nodes, it is necessary to make the nodes available for probing. According to conventional techniques, probe nodes must be added to the design and connected to FPGA input/output (I/O) terminals. The effort of connecting internal nodes to IO terminals is very time-consuming. In addition, due to the limitation on IO terminal count, many iterations are required to observe all of the desired nodes. That is, the observation must be reduced to fit into the FPGA platform. For large numbers of probe nodes, time-domain multiplexing schemes can be used, but such schemes add complexity and require more resources and time to debug.

According to one embodiment disclosed herein, scan test features are incorporated in an FPGA implementation. The scan insertion can be done at register transfer level (RTL), by a post-synthesis process, or the like. Almost every register node can be included in the scan chain. To read out internal signals, it is not necessary to re-synthesize the design to bring out signals to IO terminals. Instead scan testing techniques are used to shift out the contents of the nodes in the scan chain. This technique eliminates the iterative and time-consuming aspects of conventional FPGA validation, while reducing time to market.

FIG. 1shows elements of an integrated circuit scan test system100according to one embodiment. Although in the described embodiments the elements of scan test system100are presented in one arrangement, other embodiments may feature other arrangements. For example, elements of scan test system100can be implemented in hardware, software, or combinations thereof.

Referring toFIG. 1, scan test system100includes an integrated circuit102and a scan test module104for performing scan tests on integrated circuit102. Integrated circuit102can be implemented in silicon, as a field-programmable gate array (FPGA), or the like. Integrated circuit102includes a function module106to be scan tested. Function module106operates according to a clock signal Clk, and includes logic circuits122and a plurality of storage elements that form a scan chain124in response to a Mode signal.

Integrated circuit102also includes a multiplexer108that provides either a function clock signal Fclk or a scan clock signal Sclk as clock signal Clk in accordance with the Mode signal. Integrated circuit102also includes a clock module110that provides a system clock signal Sysclk and a clock gate module112that provides system clock signal Sysclk as function clock signal Fclk based on a clock gate signal ClkGate, which is provided by a clock control module114in accordance with one or more monitored signals. Scan test module104includes a scan clock module116to provide scan clock Sclk, a mode module118to provide the Mode signal, and a test data module120to capture data Sout from scan chain124. In some embodiments, test data module120also provides test vectors Sin to scan chain124to provide starting points for scan tests.

FIG. 2shows elements of function module106ofFIG. 1according to one embodiment. Although in the described embodiments the elements of function module106are presented in one arrangement, other embodiments may feature other arrangements. For example, elements of function module106can be implemented in hardware, software, or combinations thereof.

Referring toFIG. 2, function module106includes two logic circuits122A and122B, four flip-flops204A-204D, and four multiplexers206A-206D. As shown inFIG. 2, multiplexers206are controlled by the Mode signal. During scan testing, the Mode signal is first negated, allowing integrated circuit102to operate nominally. In nominal operation, multiplexer108(FIG. 1) provides function clock signal Fclk as clock signal Clk. Multiplexer206A passes a function input Fin1 to flip-flop204A, which passes the function input to logic circuit122A under the control of function clock Fclk. Similarly, multiplexer206B passes a function input Fin2 to flip-flop204B, which passes the function input to logic circuit122B under the control of function clock Fclk. Multiplexer206D passes a function output Fout1 to flip-flop204D, which passes the function output under the control of function clock Fclk. Similarly, multiplexer206C passes a function output Fout2 to flip-flop204C, which passes the function output under the control of function clock Fclk.

As part of scan testing, flip-flops204of function module106interconnect in series to form scan chain124in response to the Mode signal. In particular, multiplexer206A passes scan input Sin to flip-flop204A, multiplexer206B connects the output of flip-flop204A to the input of flip-flop204B, multiplexer206C connects the output of flip-flop204B to the input of flip-flop204C, and multiplexer206D connects the output of flip-flop204C to the input of flip-flop204D, which provides scan output Sout. In addition, multiplexer108provides scan clock Sclk as clock Clk. Scan clock module toggles scan clock Sclk to shift data through scan chain124.

FIG. 3shows a process300for integrated circuit scan test system100ofFIG. 1according to one embodiment. Although in the described embodiments the elements of process300are presented in one arrangement, other embodiments may feature other arrangements. For example, in various embodiments, some or all of the steps of process300can be executed in a different order, concurrently, and the like.

Referring toFIG. 3, at302integrated circuit scan test system100is reset. At304, integrated circuit scan test system100is initialized. In particular, clock control module114is programmed to assert clock gate signal ClkGate upon the occurrence of one or more predetermined conditions, for example, when one or more monitored signals assume predetermined values.

At306, function module106begins nominal operations at full clock speed. In particular, clock module110generates system clock signal Sysclk, and clock gate module112passes system clock signal Sysclk as function clock signal Fclk. During nominal operation, clock control module114monitors one or more signals, which are referred to herein as “monitored signals.” The monitored signals can include signals generated internally by integrated circuit102such as interrupts and special test register outputs, signals provided by devices external to integrated circuit102, or both.

At308, upon the occurrence of one or more predetermined conditions, clock gate module112stops function clock signal Fclk. In particular, when the one or more monitored signals assume predetermined values, clock control module114asserts clock gate signal ClkGate. In response, clock gate module112ceases to pass system clock signal Sysclk, thereby stopping function clock signal Fclk.

Next, the test data is captured from function module106for analysis. At310scan test module104forms scan chain124. At312, scan test module104shifts the data out of scan chain124. In particular, scan clock module116toggles scan clock signal Sclk, which shifts test data Sout from scan chain124into test data module120. At this point the test data is ready for analysis in test data module120.

As described above, function clock Fclk can be stopped automatically upon the occurrence of one or more predetermined conditions. Some embodiments provide a delay stop-clock feature, where function clock Fclk can be stopped automatically after the occurrence of one or more predetermined conditions by a predetermined number of cycles N.FIG. 4shows elements of clock control module114ofFIG. 1according to one such embodiment. Although in the described embodiments the elements of clock control module114are presented in one arrangement, other embodiments may feature other arrangements. For example, elements of clock control module114can be implemented in hardware, software, or combinations thereof.

Referring toFIG. 4, clock control module114includes an auto-step module402, a cycle register404, a trigger module406, a clock counter408, and a comparator410. According to the delay stop-clock feature, cycle register404is loaded with a non-negative offset integer N, and trigger module406monitors one or more monitored signals. When the monitored signals assume predetermined values, trigger module406asserts a trigger signal, which causes clock counter408to begin counting cycles of system clock signal Sysclk. After N cycles, comparator410asserts clock gate signal ClkGate. In response, clock gate module112stops function clock signal Fclk.

FIG. 5is a timing diagram illustrating an operation of clock control module114ofFIG. 4according to one embodiment. Referring toFIG. 5, clock gate module112passes system clock signal Sysclk until N=7 cycles following assertion of the Trigger signal. At that point, clock gate module112stops function clock Fclk. Then the test data can be shifted out of scan chain124for analysis.

Some embodiments include an auto-step feature. According to the auto-step feature, after function clock Fclk is stopped, and the test data is extracted from scan chain124, auto-step module402increments the value of N in cycle register404, resets function module106by asserting a Reset signal, and repeats the scan test. In this manner, test data for successive cycles of function clock signal Fclk can be obtained automatically, thereby forming a time series of test data for analysis.

FIG. 6shows an auto-step process600for integrated circuit scan test system100ofFIG. 1according to one embodiment. Although in the described embodiments the elements of process600are presented in one arrangement, other embodiments may feature other arrangements. For example, in various embodiments, some or all of the steps of process600can be executed in a different order, concurrently, and the like. For clarity, process600does not include the loading of test vectors into scan chain124. However, the loading of test vectors into scan chain124can easily be incorporated into process600.

Referring toFIG. 6, at602integrated circuit scan test system100is reset. At604integrated circuit scan test system100is initialized. In particular, clock control module114is programmed to assert clock gate signal ClkGate upon the occurrence of one or more predetermined conditions, for example, when one or more monitored signals assume predetermined values. In addition, auto-step module402loads an initial value for offset integer N into cycle register404. At606, function module106begins nominal operations at full clock speed. Nominal operations continue until upon the occurrence of one or more predetermined conditions at608. Then at610, clock control module counts N cycles of system clock signal Sysclk before stopping function clock Fclk at612. In particular, when the monitored signals assume predetermined values, trigger module406asserts the Trigger signal, which causes clock module408to begin counting cycles of system clock signal Sysclk. When the count reaches N, comparator410stops function clock signal Fclk by asserting clock gate signal ClkGate. In response, clock gate module112ceases to pass system clock signal Sysclk, thereby stopping function clock signal Fclk.

At614test data module120captures the test data from scan chain124of function module106for analysis. At616, auto-step module402increments the value of N in cycle register404and asserts the Reset signal, which resets function module106and the count held by clock module408. In some embodiments, the value of N is incremented by 1 each time. In other embodiments, other values can be used. The scan testing the continues with the resumption of nominal operations at606. This process can be repeated as many times as desired to obtain a time series of test data of any length for analysis.

A number of implementations have been described. Nevertheless, various modifications may be made without departing from the scope of the disclosure. Accordingly, other implementations are within the scope of the following claims.