Circuit and method for combining SPAD outputs

A combining network for an array of SPAD devices includes: synchronous sampling circuits, wherein each synchronous sampling circuit is coupled to an output of a corresponding SPAD device and is configured to generate a pulse or an edge each time an event is detected; and a summation circuit coupled to an output of each of the synchronous sampling circuits and configured to count a number of pulses or edges to generate a binary output value.

PRIORITY CLAIM

This application claims the priority benefit of European Application for Patent No. 19180963.1, filed on Jun. 18, 2019, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law.

TECHNICAL FIELD

The present disclosure relates generally to the field of time of flight ranging devices, and, in particular, to a circuit and method for combining the outputs of an array of single-photon avalanche diodes (SPADs).

BACKGROUND

The ability of time-of-flight (ToF) cameras based on SPADs to provide precise photon arrival times makes them popular candidates for light detection and ranging (LiDAR) sensors. Such ToF cameras generally comprise a laser source such as a vertical cavity surface-emitting laser (VCSEL) that emits, into an image scene, optical pulses or an optical waveform, and an array of SPADs for detecting the return signal.

In the case of direct ToF (dToF), the time delay of each return pulse with respect to the corresponding transmitted pulse is estimate in order to determine the time-of-flight, which can be converted into a distance measurement.

In the case of indirect ToF (iToF), the phase of the returned waveform is compared with that of the emitted waveform in order to estimate the time-of-flight, which is then converted into a distance measurement.

Scene imaging in certain environments, such as for LiDAR automotive applications, faces challenges due to scanning a wide field-of-view, variations in the target reflectivity, and the harsh ambient conditions.

There is thus a need in the art for a circuit and method for ToF ranging that addresses one or more of these challenges. There is a need in the art to at least partially address one or more needs in the art.

SUMMARY

According to one aspect, there is provided a combining network for an array of SPAD (single-photon avalanche diode) devices, the combining network including: a plurality of synchronous sampling circuits, each synchronous sampling circuit being coupled to the output of a corresponding SPAD device and being configured to generate a pulse or an edge each time an event is detected; and a summation circuit coupled to an output of each of the synchronous sampling circuits and configured to count the number of pulses or edges to generate a binary output value.

According to one embodiment, the summation circuit comprises an adder tree configured to convert an N-bit input into an L-bit output, where N is equal to 4 or more, and L=log2N or L=log2N+1.

According to one embodiment, each of the plurality of synchronous sampling circuits comprises a flip-flop having its data input coupled to the output of the corresponding SPAD device, the flip-flops being clocked by a clock signal.

According to one embodiment, the event is in the form of a pulse of a first duration on the output of the corresponding SPAD device, and the clock signal has a period of less than half the first duration.

According to one embodiment, each of the plurality of synchronous sampling circuits comprises an edge detection device configured to detect an edge of a pulse generated by the corresponding SPAD device.

According to one embodiment, each edge detection device includes: a first flip-flop having its data input coupled to the output of the corresponding SPAD device; a second flip-flop having its data input coupled to a data output of the first flip-flop, wherein the first and second flip-flops are clocked by a clock signal; and a logic gate coupled to the data outputs of the first and second flip-flops and configured to detect a rising and/or falling edge at the output of the corresponding SPAD device based on data outputs of the first and second flip-flops.

According to a further aspect, there is provided a ranging device comprising: an array of SPAD devices; the above combining network coupled to the outputs of the array; and a histogram generation circuit configured to accumulate count values generated by the summation circuit in a plurality of time bins.

According to a further aspect, there is provided a method of detecting events in a SPAD (single-photon avalanche diode) array, the method including: generating, by a plurality of synchronous sampling circuits, a pulse or an edge each time an event is detected at an output of a corresponding SPAD device of the SPAD array; and counting, by a summation circuit coupled to an output of each of the synchronous sampling circuits, the number of pulses or edges to generate a binary output value.

According to one embodiment, the method also includes converting, using an adder tree of the summation circuit, an N-bit input into an L-bit output, where N is equal to 4 or more, and L=log2N or L=log2N+1.

According to one embodiment, generating the pulse or edge each time an event is detected at an output of the corresponding SPAD device includes sampling, using a flip-flop, the output of the corresponding SPAD device based on a clock signal.

DETAILED DESCRIPTION

Like features have been designated by like references in the various figures. In particular, the structural and/or functional features that are common among the various embodiments may have the same references and may dispose similar or identical structural, dimensional and material properties.

Unless indicated otherwise, when reference is made to two elements connected together, this signifies a direct connection without any intermediate elements other than conductors, and when reference is made to two elements linked or coupled together, this signifies that these two elements can be connected or they can be linked or coupled via one or more other elements.

FIG.1schematically illustrates a ranging device100. The ranging device100comprises a SPAD array102comprising, in the example ofFIG.1, 16 SPAD devices104labelled 1 to 16 and arranged in a four by four grid. The output of each SPAD device is provided on a corresponding line of a 16-bit output link106to a combining network (COMBINING NETWORK)118.

An output line120of the combining network118is for example provided to a histogram generation circuit (HISTOGRAM GENERATION)122, which for example attributes the samples from the SPAD array102to different time bins in order to allow the arrival time of a received light pulse, or phase of a received optical waveform, to be determined.

By providing a SPAD array102formed of a plurality of SPAD devices104, the dynamic range can be increased with respect to the use of a single SPAD device of the same dimensions. The role of the combining network118is to condense the outputs from the SPAD devices of the array102onto a single output line120. As will be described in more detail below, the combining network118may comprise an OR tree for combining the SPAD outputs.

FIG.2schematically illustrates the combining network118of the ranging device ofFIG.1based on an OR-tree implementation, and according to a simplified example based on the output signals of four SPAD devices (SPAD+FE)104forming the SPAD array102. Each SPAD device for example includes a front end (FE) circuit comprising a MOS transistor for quench/recharge, and an inverter used to re-buffer the leading edge of the SPAD into a digital pulse.

An output (SPAD1to SPAD4) of each SPAD device104is provided to a corresponding pulse shaper (PS)202, which transforms an event detected by the SPAD device104into a pulse of fixed duration. The outputs of the pulse shapers202are coupled to an OR-tree204, which comprises three OR gates206in the example ofFIG.2, one of the OR gates having its two inputs respectively coupled to the outputs of two of the pulse shapers202, another of the OR gates having its two inputs respectively coupled to the outputs of the other two pulse shapers202, and the third OR gate having its two inputs respectively coupled to the outputs of the other two OR gates. The output of the third OR gate corresponds to the single output line120of the combining network118.

Each of the pulse shapers202, for example, has its input coupled to one input of an AND gate208, and also to the second input of the AND gate208via an inverter210.

A drawback of the combining network118based on the OR tree ofFIG.2is that it suffers from photon pile-up distortion, as will now be described in more detail with reference toFIG.3.

FIG.3is a timing diagram representing signals in the circuit ofFIG.2. In particular,FIG.3illustrates examples of the output signals SPAD1to SPAD4of the four SPAD devices104ofFIG.2, of a signal OR TREE that would be present at the output of the OR tree204in the absence of the pulse shapers202, and a signal PS+OR TREE corresponding to the signal on the output line120of the combining network118ofFIG.2. A duration tp corresponds to the duration of a pulse on the lines SPAD1to SPAD4resulting from a SPAD detection event. This pulse duration is reduced to a duration tps by the pulse shapers202, the dashed lines in the signal PS+OR TREE representing the end of each pulse. However, it can be seen inFIG.3that when events occur relatively close together, for example because of high ambient light, saturation of the combining network occurs. This results in photon pile-up distortion in which some events are partially or entirely missed. In a first example inFIG.3, three events302,304and306are separated by less than the shortened duration tps, leading to a distorted output pulse duration that is shorter than 3*tps. In a further example inFIG.3, two events308,310occur within a duration tps, and thus the resulting pulse has a duration shorter than 2*tps. Furthermore, a further event312at the output of SPAD1occurs directly after the event308, and thus the event312does not cause a shortened pulse to be generated, and is thus missed entirely.

FIG.4schematically illustrates the combining network118of the ranging device ofFIG.1based on an XOR tree implementation, and according to the same simplified example ofFIG.2based on four SPAD devices104forming the SPAD array102. An output (SPAD1to SPAD4) of each SPAD device (SPAD+FE)104is provided to a corresponding toggle device (T)402, which transforms an event detected by the SPAD device104into a binary transition from logic “0” to logic “1” or from logic “1” to logic “0”. The outputs of the toggle devices402are coupled to an XOR tree404, which comprises three XOR gates406in the example ofFIG.4, one of the XOR gates having its two inputs respectively coupled to the outputs of two of the toggle devices402, another of the XOR gates having its two inputs respectively coupled to the outputs of the other two toggle devices402, and the third XOR gate having its two inputs respectively coupled to the outputs of the other two XOR gates. The output of the third XOR gate corresponds to the single output line120of the combining network118.

Each of the toggle devices402has its input coupled to a clock input of a D-type flip-flop408, an inverted output Qn of the flip-flop408being connected to the data input D of the flip-flop408.

Like for the OR TREE embodiment ofFIG.2, the XOR TREE embodiment ofFIG.4can suffer from photon pile-up due to saturation, as will now be described with reference toFIG.5.

FIG.5is a timing diagram representing signals in the circuit ofFIG.4. In particular,FIG.5illustrates examples of the output signals SPAD1to SPAD4of the four SPAD devices104ofFIG.4, and of a signal XOR TREE corresponding to the signal on the output line120of the combining network118ofFIG.4. A duration tp corresponds to the duration of a pulse on the lines SPAD1to SPAD4resulting from a SPAD detection event.

FIG.5illustrates the same examples of SPAD events302to312as shown inFIG.3. However, while the SPAD events302to310cause corresponding transitions502to510in the output signal, like in the example ofFIG.3, the event312is missed, as represented by an arrow512without any transition. Furthermore, as the rate of incoming photons increases, the frequency of the XOR tree increases. High ambient light can therefore lead to very close 0 to 1 to 0 transitions in the XOR tree, leading to events being missed.

FIG.6schematically illustrates the combining network of the ranging device ofFIG.1. The combining network118comprises, for example, coupled to the output of each SPAD device104forming the SPAD array102, a corresponding synchronous sampling device602. In the example ofFIG.6, the synchronous sampling devices602are D-type flip-flops clocked by a clock signal CLK, although other implementations of the synchronous sampling devices602would be possible. Each D-type flip-flop602, for example, has its data input D coupled to the output of the corresponding SPAD104, and its data output Q coupled to a summation circuit604, which converts N outputs signals from the N synchronous sampling devices602into an L-bit signal SST′, where L=log2N, or L=log2N+1 including an overflow bit (described in more detail below), based on the number of sampled signals that are asserted at each edge of the clock signal CLK. The output signal SST′ is for example provided to the data input D of a further L-bit D-type flip-flop606clocked by the clock signal CLK, and which provides, at its data output Q, an L-bit output signal SST forming the output of the combining network118. The number N of SPAD devices104is for example at least 4.

Operation of the circuit ofFIG.6will now be described with reference toFIG.7.FIG.7is a timing diagram representing signals in the circuit ofFIG.6, based on an example of four SPAD devices104.FIG.7illustrates in particular examples of output signals SPAD1to SPAD4of the four SPAD devices104, a series of signals701representing pulse additions, and the output signal SST, which is a 4-bit signal in this example (although a 2-bit signal could be used).

A duration tp inFIG.7corresponds to the duration of a pulse on the lines SPAD1to SPAD4resulting from a SPAD detection event. In one embodiment, this duration is equal to around 5 ns, although other durations would be possible. The period of the clock signal CLK is for example equal to or less than half the duration tp, and in some embodiments is at least four times shorter than the duration tp.

The synchronous sampling devices602, for example, sample the signals SPAD1to SPAD4on each rising edge of the clock signal CLK. Thus, the generated output pulses have rising and falling edges synchronized with the clock signal CLK. These pulses are represented by the signals701, in which overlapping pulses of the signals SPAD1to SPAD4are shown stacked, as these pulses will be added by the summation circuit604. The output signal SST thus represents, at each significant edge of the clock signal CLK, the number of signals SPAD1to SPAD4that is asserted.

In the example, ofFIG.7, initially none of the signals SPAD1to SPAD4are asserted, and thus the signal SST is at zero. A pulse702initially occurs on the signal SPAD3, causing the signal SST to rise to 1, e.g. a 4-bit binary value of “0001”. A pulse704then occurs shortly thereafter on the signal SPAD1, causing the signal SST to rise to 2, e.g. a 4-bit binary value of “0010”, followed by a pulse706on the signal SPAD2, causing the signal SST to rise to 3, e.g. a 4-bit binary value of “0011”. The ends of the pulses702,704and706then arrive one after the other, respectively causing the output signal SST to fall back to 2, and then to 1, and then to zero.

In another example inFIG.7, a pulse708initially occurs on the signal SPAD1, causing the signal SST to rise to 1, e.g. a 4-bit binary value of “0001”. A pulse710then occurs shortly thereafter on the signal SPAD2, causing the signal SST to rise to 2, e.g., a 4-bit binary value of “0010”, followed by a pulse712on the signal SPAD3, causing the signal SST to rise to 3, e.g., a 4-bit binary value of “0011”. A further pulse714then occurs on the signal SPAD1directly after the pulse708. However, in view of the sampling of the signal SPAD1, this pulse714having no rising edge is not missed, and causes the signal SST to remain at 3, e.g., the 4-bit binary value of “0011”, after the end of the pulse708. The ends of the pulses710,712and714then arrive one after the other, respectively causing the output signal SST to fall back to 2, and then to 1, and then to zero.

FIG.7illustrates an example according to which the summation circuit604generates output count values when the number of high pulses changes, corresponding to the starts and ends of each pulse of the input signals. In alternative embodiments, the summation circuit604is configured to generate a count value based on a regular sampling of the SPAD signals, and in particular based on the number of pulses currently asserted, as will now be described in more detail with reference toFIG.8.

FIG.8is a timing diagram representing signals in the circuit ofFIG.6according to continuous synchronous sampling method.FIG.8illustrates the same example of the SPAD output signals SPAD1, SPAD2, SPAD3and SPAD4ofFIG.7, and also illustrates three examples801,802and803of the output signal SST based respectively on sampling periods Bin of 500 ps, 1 ns and 2 ns. The signals801,802and803ofFIG.8use vertical arrows to indicate the output count signal SST at each sampling time. The number of generated samples can be reduced in the example ofFIG.8by increasing the sampling period, as represented by the examples802and803, at the expense of reduced precision concerning the pulse timing.

FIG.9schematically illustrates the combining network118of the ranging device ofFIG.1. The embodiment ofFIG.9is similar to that ofFIG.6, except that, rather than being implemented by flip-flops602, the synchronous sampling devices are implemented by edge detection devices (EDGE DETECT)902each of which is clocked by the clock signal CLK.

FIG.10schematically illustrates one of the detection devices902ofFIG.9in more detail. Each of the devices902ofFIG.9is, for example, implemented by a similar circuit to that ofFIG.10. The device902for example comprises a flip-flop1002having its data input D receiving the corresponding output signal SPADi from one of the SPAD device104, and its data output Q coupled to the date input D of a further flip-flop1004. The further flip-flop1004has its inverted output Qn coupled to one input of an AND gate1006, the other input of which is coupled to the date output Q of the flip-flop1002. The flip-flops1002,1004are each clocked by the clock signal CLK.

Thus, the edge detection device902samples the signals SPADi on each significant edge of the clock signal CLK, but outputs a high signal when a rising edge is detected. Of course, in the case that the SPAD devices104output falling edges in response to a detected event, the edge detection devices902could be modified to detect falling edges by coupling the AND gate input and the data input D of the flip-flop1004to an inverted output Qn of the flip-flop1002rather that to its data output Q, and by coupling the input of the AND gate1006to the data output Q of the flip-flop1004rather than to its inverted output Qn.

FIG.11is a timing diagram representing signals in the circuit ofFIGS.9and10.FIG.11illustrates the same example of the SPAD output signals SPAD1, SPAD2, SPAD3and SPAD4ofFIG.7, and also illustrates three examples1101,1102and1103of different frequencies of the sampling clock signal CLK and of the corresponding output signal SST. The sampling periods Bin of the examples1101,1102and1103are respectively of 500 ps, 1 ns and 2 ns in the example ofFIG.11.

It can be seen that in the example ofFIG.11, the output count value SST corresponds to the number of edges detected during a period of the clock signal CLK.

FIG.12schematically illustrates the histogram generation circuit122of the ranging device ofFIG.1for a dToF implementation, based on the signal SST generated by the summation circuit604ofFIG.6or9.

The example ofFIG.12is based on M histogram bins, where M is equal to 8 in the example ofFIG.12. The circuit122for example comprises a shift-register (SHIFT-REGISTER)1202receiving the L-bit values SST, where L is equal to 4 in the example ofFIG.12. The shift-register1202stores M values of the signal SST, which are shifted at the frequency of the clock signal CLK. Every time that M values have been brought into the shift-register1202, a load signal LOAD is asserted causing the L-bit value in each of the bins of the shift-register1202to be output to a corresponding one of M counters C. Each counter C is for example a K-bit counter, and permits a histogram to be generated for J received pulses, where K is for example equal to between 4 and 32, and J is for example equal to at least 10 and typically equal to several hundred.

The histogram resulting from the cumulative count values of the M counters C can be used to determine an average time-of-flight of the light pulses, and thus determine a range, while also detecting and cancelling cross-talk.

FIG.13schematically illustrates a histogram generation circuit of the ranging device ofFIG.1for an iToF implementation, based on the signal SST generated by the summation circuit604ofFIG.6or9. The circuit122ofFIG.13is the same as that ofFIG.12, except that the shift-register1202ofFIG.13has a number of bins M adapted to the detection of a phase of a waveform. For example, in the case of an iToF implementation, the number M of bins can be as low as 2 bins, and in the example ofFIG.13there are 6 bins.

FIG.14schematically illustrates an adder tree1400for implementing the summation circuit604ofFIGS.6and9. The example ofFIG.14is based on full adders (FA) and half adders (HA), and on 16 input bits IN(0) to IN(15), which for example correspond to the signals provided by corresponding ones of the flip-flips602ofFIG.6or the edge detection devices902ofFIG.9.

Each full adder FA has inputs A and B, a carry input Ci, a sum output S and carry output Co. Each half adder HA has inputs A and B, a sum output S, and a carry output Co.

The adder tree1400for example comprises: a full adder1402receiving at its inputs A, B and Ci the signals IN(0), IN(1) and IN(2) respectively, and providing, at its sum output S, a sum value S0, and at its carry output Co, a carry value C0; a full adder1404receiving at its inputs A, B and Ci the signals IN(3), IN(4) and IN(5) respectively, and providing, at its sum output S, a sum value S1, and at its carry output Co, a carry value C1; a half adder1406receiving at its inputs A and B the signals IN(6) and IN(7) respectively, and providing, at its sum output S, a sum value S2, and at its carry output Co, a carry value C2; a full adder1408receiving at its inputs A, B and Ci the signals IN(8), IN(9) and IN(10) respectively, and providing, at its sum output S, a sum value S3, and at its carry output Co, a carry value C3; a full adder1410receiving at its inputs A, B and Ci the signals IN(11), IN(12) and IN(13) respectively, and providing, at its sum output S, a sum value S4, and at its carry output Co, a carry value C4; and a half adder1412receiving at its inputs A and B the signals IN(14) and IN(15) respectively, and providing, at its sum output S, a sum value S5, and at its carry output Co, a carry value C5.

The adder tree1400also for example comprises: a full adder1414receiving at its inputs A, B and Ci the values S0, S1and S2respectively, and providing, at its sum output S, a sum value S6, and at its carry output Co, a carry value C6; a full adder1416receiving at its inputs A, B and Ci the values C0, C1and C2respectively, and providing, at its sum output S, a sum value S7, and at its carry output Co, a carry value C7; a full adder1418receiving at its inputs A, B and Ci the values S3, S4and S5respectively, and providing, at its sum output S, a sum value S8, and at its carry output Co, a carry value C8; and a full adder1420receiving at its inputs A, B and Ci the values C3, C4and C5respectively, and providing, at its sum output S, a sum value S9, and at its carry output Co, a carry value C9.

The adder tree1400also for example comprises: a half adder1422receiving at its inputs A and B the values S6and S8respectively, and providing, at its sum output S, a sum value S10, and at its carry output Co, a carry value C10; a full adder1424receiving at its inputs A, B and Ci the values C10, C6and C8respectively, and providing, at its sum output S, a sum value S11, and at its carry output Co, a carry value C11; a full adder1426receiving at its inputs A, B and Ci the values S11, S9and S7respectively, and providing, at its sum output S, a sum value S12, and at its carry output Co, a carry value C12; a full adder1428receiving at its inputs A, B and Ci the values C12, C7and C9respectively, and providing, at its sum output S, a sum value S13, and at its carry output Co, a carry value C13; a half adder1430receiving at its inputs A and B the values C11and S13respectively, and providing, at its sum output S, a sum value S14, and at its carry output Co, a carry value C14; and a half adder1432receiving at its inputs A and B the values C13and C14respectively, and providing, at its sum output S, a sum value S15, and at its carry output Co, a carry value C15.

The sum values S10, S12, S14and S15for example provide the 4-bit output value OUT(0) to OUT(3) of the adder tree respectively, and the carry value C15for example provides a carry output. This carry output is for example used as an overflow flag, in which case the number of output bits L is for example equal to log2N+1. For example, when asserted, the count value is held at a maximum value, thereby avoiding a case in which the count value will roll-over to zero if the maximum count value is exceeded.

FIG.15is a graph representing a detected photon rate as a function of an incident photon rate for four different types of combining networks. The photon rates are expressed in counts per second (cps).

A curve1502inFIG.15represents a simulated detected photon rate based on the OR tree combining network ofFIG.2, but without the pulse shapers202.

A curve1504inFIG.15represents a simulated detected photon rate based on the OR tree combining network ofFIG.2with the pulse shapers202.

A curve1506inFIG.15represents a simulated detected photon rate based on the combining network ofFIG.9with synchronous sampling devices in the form of edge detection devices902.

A curve1508inFIG.15represents a simulated detected photon rate based on the combining network ofFIG.6with synchronous sampling devices in the form of flip-flops602.

Crosses close to each of the curves1502to1508show measured detected photon rates.

It can be seen from the curves1506and1508ofFIG.15that, advantageously, significant improvements in the detected photon rate can be achieved when synchronous sampling devices are used to sample the SPAD outputs, and a summation circuit is then used to evaluate the number of detected events. In particular, the detected photon rate is relatively high even when the incident photon rate exceeds 109cps and approaches 1010cps.

Various embodiments and variants have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and other variants will readily occur to those skilled in the art. For example, it will be apparent to those skilled in the art that the particular implementation of the adder tree ofFIG.14is merely one example, and that there are various other implementations that would be possible.