Semiconductor device

In a semiconductor device, a first contact-diffusion-layer is in a first well to be connected to the first well and extends in a channel width direction of a first transistor in a first well. A second contact-diffusion-layer is in the first well so as to be electrically connected to the first well and extends in a channel-length direction of the first transistor. A first contact on the first contact-diffusion-layer has a shape with a diameter in the channel-width direction larger than that in the channel-length direction when viewed from above the substrate. A second contact on the second contact-diffusion-layer has a shape with a diameter in the channel-width direction smaller than that of the first contact and a diameter in the channel-length direction almost equal to that of the first contact when viewed from above the substrate. A wiring is electrically connected to the first transistor through the second contact.

FIELD

The embodiments of the present invention relate to a semiconductor device.

BACKGROUND

A well contact diffusion layer (a so-called “guard ring”) is frequently used in a semiconductor device to electrically connect semiconductor elements such as a transistor to a well diffusion layer. Contacts connecting wirings from a semiconductor device to a guard ring are often formed to be circular or elongated-circular in a planar shape.

In terms of reducing a chip size of a semiconductor device, contacts of a guard ring are desirably circular-hole contacts having a circular shape. However, if all the contacts of a guard ring are circular-hole contacts, contact resistances to wells are increased when some of the circular-hole contacts are not opened.

On the other hand, in terms of reducing contact resistances to wells, contacts of a guard ring are desirably elongated-hole contacts having an elongated shape. However, if all the contacts of a guard ring are elongated-hole contacts, the chip size may be increased. For example, the width of the guard ring needs to be increased to match the major axis of the elongated-hole contacts. Alternatively, distances between adjacent wirings need to be increased to match the major axis of the elongated-hole contacts.

DETAILED DESCRIPTION

A semiconductor device according to an embodiment provides a semiconductor substrate. A first well of a first conductivity type is provided on the semiconductor substrate. A first transistor is provided in the first well. A first contact diffusion layer is provided in the first well so as to be electrically connected to the first well and extends in a channel width direction of the first transistor. A second contact diffusion layer is provided in the first well so as to be electrically connected to the first well and extends in a channel length direction of the first transistor. A first contact is provided on the first contact diffusion layer and has a shape with a diameter in the channel width direction larger than that in the channel length direction when the first contact is viewed from above the semiconductor substrate. A second contact is provided on the second contact diffusion layer and has a shape with a diameter in the channel width direction smaller than that of the first contact and a diameter in the channel length direction almost equal to that of the first contact when the second contact is viewed from above the semiconductor substrate. A wiring is electrically connected to at least a part of the first transistor through the second contact.

Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments.

Embodiments described below can be applied to various types of memories that have a well contact diffusion layer (a so-called “guard ring”), such as a magnetic random access memory (MRAM), a resistance random access memory (ReRAM), a phase-change random access memory (PRAM), and a ferroelectric random access memory (FeRAM). The embodiments mentioned below can be also applied to arbitrary semiconductor devices other than the memories as long as the semiconductor devices have a well contact diffusion layer.

First Embodiment

FIG. 1is a plan view showing a configuration of a semiconductor device according to a first embodiment. In the first embodiment, the semiconductor device is a memory10and includes a core area12and a peripheral circuit area14. The memory10is formed as one semiconductor chip.

The core area12includes memory cell arrays MCA, row decoders RD, and sense amplifiers SA. Each of the memory cell arrays MCA includes a plurality of memory cells MC arranged two-dimensionally in a matrix, for example. Each of the memory cells MC is connected to a bit line BL and a word line WL. The memory cell MC is connected to the sense amplifier SA via the bit line BL and connected to the row decoder RD via the word line WL. The core area12further includes a driver that drives the bit lines BL or the word lines WL, a buffer that temporarily stores data therein, and the like (not shown).

The peripheral circuit area14includes an analog circuit ANC including a booster circuit that boosts a power-supply voltage, an I/O circuit, and the like, and a logic circuit LGC including a control circuit for the core area12, and the like. The analog circuit ANC is designed by using a semi-custom layout or a full-custom layout. The logic circuit LGC is designed by using an automatic placement and routing tool (APR).

Generally, contacts in the core area12are designed according to a design rule different from that of contacts in the peripheral circuit area14. The contacts in the peripheral circuit area14according to the first embodiment are explained below.

FIG. 2is a schematic plan view showing a configuration of the analog circuit ANC in the peripheral circuit area14.FIG. 3is a cross-sectional view along the line3-3inFIG. 2.

The analog circuit ANC includes a well diffusion layer20provided on a semiconductor substrate (for example, a p-type silicon substrate)15as shown inFIG. 3. Active areas AA and isolation areas STI are formed on the well diffusion layer20. Semiconductor elements such as transistors Tr are formed in the active areas AA. The isolation areas STI are provided between adjacent ones of the active areas AA and electrically isolate the active areas AA from each other.

Furthermore, a well contact diffusion layer30is provided on the well diffusion layer20. The well contact diffusion layer30is formed of an impurity diffusion layer of the same conductivity type as that of the well diffusion layer20in order to electrically connect a part of the respective transistors Tr to the well diffusion layer20(or the semiconductor substrate15). That is, the well contact diffusion layer30is a so-called guard ring electrically connected to the well diffusion layer20. However, the shape of the well contact diffusion layer30is not limited to a ring shape as long as the well contact diffusion layer30has a function of electrically connecting a part of the respective transistors Tr to the well diffusion layer20.

As shown inFIG. 2, the well contact diffusion layer30includes first contact diffusion layers30_1and second contact diffusion layers30_2. The first contact diffusion layers30_1are parts of the well contact diffusion layer30, which parts extend in a channel width direction DW of the transistors Tr. The second contact diffusion layers30_2are parts of the well contact diffusion layer30, which parts extend in a channel length direction DL of the transistors Tr. The channel width direction DW can be also referred to as an extension direction of first-layer metal wirings (M0)60or the first contact diffusion layers30_1. The channel length direction DL can be also referred to as an extension direction of the second contact diffusion layers30_2.

The two first contact diffusion layers30_1are provided on both sides of the channel length direction DL of the periphery of the analog circuit ANC, respectively. The two second contact diffusion layers30_2are provided on both sides of the channel width direction DW of the periphery of the analog circuit ANC, respectively. Accordingly, the well contact diffusion layer30is arranged in a rectangular ring shape in the planar layout so as to surround the transistors Tr of the analog circuit ANC. However, the well contact diffusion layer30is not limited to the ring shape as mentioned above. For example, the well contact diffusion layer30can be arranged in a U shape as required according to the layout design.

A plurality of first contacts40are formed on the first contact diffusion layers30_1. A diameter in the channel width direction DW of the first contacts40is larger than that in the channel length direction DL thereof when the first contacts40are viewed from above a surface of the semiconductor substrate15. That is, the first contacts40are elongated-hole contacts having an elongated planar shape. For example, a planar shape of the first contacts40can be substantially elliptical, substantially elongate-circular, substantially rectangular, or the like. Even when the planar shape of the first contacts40is rectangular in a photolithography mask, the planar shape of the first contacts40to be actually formed becomes elongated-circular or elliptical in many cases.

A plurality of second contacts50are formed on the second contact diffusion layers30_2. A diameter in the channel width direction DW of the second contacts50is smaller than that of the first contacts40and a diameter in the channel length direction DL thereof is almost equal to that of the first contacts40when the second contacts50are viewed from above the surface of the semiconductor substrate15. In the first embodiment, the second contacts50have almost the same diameters in the channel width direction DW and in the channel length direction DL and are circular-hole contacts having a circular (or a rectangular) shape. For example, a planar shape of the second contacts50can be substantially circular, substantially square, or the like. However, it suffices that the planar shape of the second contacts50is more like a square or a circle as compared to the first contacts40, and the shape is not specifically limited to a substantial circle or a substantial square. Even when the planar shape of the second contacts50is square in the photolithography mask, the planar shape of the second contacts50to be actually formed becomes circular in many cases. Therefore, as mentioned above, the second contacts50are also referred to as “circular-hole contacts”.

The diameter in the channel length direction DL (length of one short side) of the first contacts40and the diameter (length of one side) of the second contacts50are almost equal to a minimum processing size F (Feature size) which is the minimum size of a line or a space processed by using a lithography technique and an etching technique in a semiconductor manufacturing process. Accordingly, a layout area of the analog circuit ANC can be decreased.

The first and second contacts40and50are formed to be embedded into an inter-layer dielectric film ILD formed on the well contact diffusion layer30and are connected to the first-layer metal wirings60formed on the inter-layer dielectric film ILD.

Contacts DC and SC of each of the transistors Tr have such a shape that has a diameter in the channel width direction DW is larger than that in the channel length direction DL when the contacts DC and SC are viewed from above the surface of the semiconductor substrate15. That is, the contacts DC and SC of each of the transistors Tr are elongated-hole contacts having the major axes in the same direction as that of the first contacts40. In this case, DC denotes a drain contact and SC denotes a source contact. G denotes a gate electrode of the transistor Tr.

The first-layer metal wirings (M0)60are provided on the inter-layer dielectric film ILD and the first and second contacts40and50. In the first embodiment, the first-layer metal wirings60extend in the channel width direction DW. Because the second contacts50are the circular-hole contacts and have the diameter in the channel length direction DL almost equal to the feature size F, distances between the first-layer metal wirings60adjacent to each other can be reduced. Accordingly, the layout area of the analog circuit ANC can be decreased.

Connection wirings in the channel length direction DL can be formed by using second-layer metal wirings (M1)70, third-layer metal wirings (M2)80, or the like, which are upper layers than the first-layer metal wirings60as shown inFIG. 3. For example, in a standard cell or the like used in a peripheral circuit area of a NAND flash memory, a signal line is arranged to extend in the channel width direction DW and a power line is arranged to extend in the channel length direction DL. The power line is formed by using a metal wiring on an upper layer than the signal line. Therefore, the signal line is formed as the first-layer metal wiring60, for example, and the power line is formed as the second-layer metal wiring70, for example. InFIG. 2, only the first-layer metal wirings60are shown, and the second-layer metal wirings70and the third-layer metal wirings80on the upper layers are not shown.

As shown inFIG. 3, the second-layer metal wirings70are electrically connected to the first-layer metal wirings60through via contacts V1. The third-layer metal wirings80are electrically connected to the second-layer metal wirings70through via contacts V2.

The first-layer metal wirings60electrically connect at least a part of the respective transistors Tr to the well contact diffusion layer30through the second contacts50. For example, the first-layer metal wiring60electrically connects the source contact SC of the transistor Tr to the second contact diffusion layer30_2through the second contact50as shown inFIG. 2.

The cross section of the first contact40in the channel length direction DL is the same as that of the second contact50shown inFIG. 3and the cross section of the first contact40in the channel width direction DW is the same as that of the source contact SC shown inFIG. 3. Therefore, the cross section of the first contact40is not shown.

In the first embodiment, the analog circuit ANC includes N-FETs formed in the P-well20and having a high current drive capability. However, the analog circuit ANC can include P-FETs formed in an N-well.

In the first embodiment, the first contacts40are the elongated-hole contacts having the major axis in the channel width direction DW (the extension direction of the first-layer metal wirings60and the first contact diffusion layers30_1). Accordingly, the first contacts40can connect between the first-layer metal wirings60and the well contact diffusion layer30with low resistances. When a potential of the well20is set from outside of the semiconductor device through the first contacts40, the well20can be appropriately set to a desired potential because the resistances between the first-layer metal wirings60and the well contact diffusion layer30are low. As a result, a risk of latch-up in the analog circuit ANC can be decreased.

The first contacts40have the major axis in the same direction as the extension direction of the first-layer metal wirings60and the first contact diffusion layers30_1. Therefore, the layout area of the analog circuit ANC itself is not increased even when the first contacts40are the elongated-hole contacts.

The planar shape of the first contacts40has the major axis in the same direction as that of major axes of a source layer S and a drain layer D of each of the transistors Tr. The first-layer metal wirings60extend in the major axis direction of the source layer S and the drain layer D to be connected to the source layer S and the drain layer D with low resistances even when the width of the first-layer metal wirings60is small. Therefore, by setting the major axis direction of the first contacts40to be the same as that of the source layer S and the drain layer D, the layout area of the analog circuit ANC is not increased even when the first contacts40are the elongated-hole contacts as mentioned above. Furthermore, because the width of the first-layer metal wirings60is narrow and the second contacts50are the circular-hole contacts, distances between adjacent ones of the first-layer metal wirings60can be reduced.

The second contacts50are circular-hole contacts and have axis lengths almost equal to the feature size F. Therefore, distances (pitches) between the first-layer metal wirings60adjacent to each other can be reduced as mentioned above. Furthermore, the width of the second contact diffusion layers30_2can be narrowed. For example, if the second contacts50are long in the channel length direction DL, the distances between the first-layer metal wirings60adjacent to each other need to be increased to match the major axis of the second contacts50. If the second contacts50are long in the channel width direction DW, the width (a width in the channel width direction DW) of the second contact diffusion layers30_2needs to be increased to match the major axis of the second contacts50. In these cases, the layout area of the analog circuit ANC is increased.

On the other hand, the second contacts50are the circular-hole contacts in the first embodiment and thus the distances between the first-layer metal wirings60adjacent to each other can be reduced and the width of the second contact diffusion layers30_2can be narrowed. As a result, the layout area of the analog circuit ANC can be decreased.

When the second contacts50are the circular-hole contacts, resistances between the first-layer metal wirings60and the well contact diffusion layer30are increased and a concern about a risk of latch-up rises. However, because the first contacts40connect the first-layer metal wirings60to the well contact diffusion layer30with low resistances in the first embodiment, the risk of latch-up is decreased. That is, in the first embodiment, it is possible to decrease the layout area of the semiconductor device while reducing the resistances between the first-layer metal wirings60and the well contact diffusion layer30by a combined use of the first contacts40(elongated-hole contacts) and the second contacts50(circular-hole contacts).

To reduce a contact resistance between the transistor Tr and the well contact diffusion layer30, two or more second contacts50can be arranged within a certain distance from each of the transistors Tr. This further reduces the resistance between the first-layer metal wiring60and the well contact diffusion layer30and thus further decreases the risk of latch-up. By placing the second contacts50within a certain distance from each of the transistors Tr, even if some of the second contacts50are not opened, opening of the other second contacts50enables the transistor Tr to be connected to the well contact diffusion layer30in the vicinity of the some of second contacts50. The certain distance is set based on impurity concentrations of the well contact diffusion layer30and of the well20, the size of the second contacts50, and the like.

The analog circuit ANC is sometimes mounted in a mixed manner with a logic circuit. The well contact diffusion layer30, the first contacts40, and the second contacts50according to the first embodiment can be also applied to such a mixedly mounted circuit having an analog circuit and a logic circuit. In this case, it suffices to form the well contact diffusion layer30, the first contacts40, and the second contacts50to surround the mixedly mounted circuit in the same manner as in the arrangement shown inFIG. 2.

Second Embodiment

FIG. 4is a schematic plan view showing a configuration of a logic circuit LGC in the peripheral circuit area14.FIG. 5is a cross-sectional view along the line5-5inFIG. 4. In a second embodiment, the first and second contacts mentioned above are applied to the logic circuit LGC.

Generally, a layout of the logic circuit LGC is formed by a combination of standard functional blocks (standard cells) configured by using the APR. Therefore, the logic circuit LGC often has a well structure in which P-wells21and N-wells22are alternately and regularly arranged. Generally, the P-well21in which N-FETs are formed is set at a reference voltage (VSS) and the N-well22in which P-FETs are formed is connected to a power-supply voltage (VDD). In some cases, an N-type transistor Trn in the P-well21and a P-type transistor Trp in the N-well22are connected between the P-well21and the N-well22adjacent to each other. That is, the logic circuit LGC includes a CMOS (Complementary Metal-Oxide Semiconductor) structure in some cases.

In this case, a planar layout of each of well contact diffusion layers31and32in the logic circuit LGC is formed in an H shape. That is, the well contact diffusion layers31and32can be divided into first contact diffusion layers31_1and32_1extending in the channel width direction DW and second contact diffusion layers31_2and32_2extending in the channel length direction DL, respectively. The contact diffusion layers31_1and31_2are included in a P+contact diffusion layer31formed in the P-well21and the contact diffusion layers32_1and32_2are included in an N+contact diffusion layer32formed in the N-well22.

The contact diffusion layers31_1(or32_1) are provided on both sides of the channel length direction DL of the periphery of the logic circuit LGC, respectively. The second contact diffusion layer31_2(or32_2) is provided to traverse a central part of the logic circuit LGC between the contact diffusion layers31_1(or32_1) on the both sides of the logic circuit LGC.

By forming each of the well contact diffusion layers31and32in the H shape in this way, first-layer metal wirings61for well contacts can be arranged inside the wells21and22, respectively. Accordingly, congestion of the first-layer metal wirings61at a boundary between the P-well21and the N-well22adjacent to each other can be suppressed. However, shapes of the well contact diffusion layers31and32are not limited to the H shape and can be changed as required according to the layout design.

Other configurations in the wells21and22of the logic circuit LGC can be basically the same as corresponding configurations in the analog circuit ANC. However, because intended uses of the transistors of the logic circuit LGC and the transistors of the analog circuit ANC are different, these transistors may be greatly different in sizes (W/L) or the like. Configurations in the N-well22of the logic circuit LGC can be basically the same as those in the P-well21while conductivity types thereof are different from those of the configurations in the P-well21.

Planar shapes of contacts41and51are explained below. A plurality of first contacts41are formed on the first contact diffusion layers31_1and32_1. A planar shape of the first contacts41has a diameter in the channel width direction DW larger than that in the channel length direction DL when the first contacts41are viewed from above the surface of the silicon substrate15. That is, the first contacts41are elongated-hole contacts as the contacts40.

A plurality of second contacts51are formed on the second contact diffusion layers31_2and32_2. A planar shape of the second contacts51has a diameter in the channel width direction DW smaller than that of the first contacts41and a diameter in the channel length direction DL is almost equal to that of the first contacts41when the second contacts51are viewed from above the silicon substrate15. For example, the second contacts51are circular-hole contacts as the contacts50.

The diameter in the channel length direction DL (length on one short side) of the first contacts41and the diameter (length on one side) of the second contacts51are almost equal to the feature size F in the semiconductor manufacturing process. Accordingly, a layout area of the logic circuit LGC can be decreased.

The first and second contacts41and51are formed to be embedded into an inter-layer dielectric film ILD and are connected to the first-layer metal wirings61formed on the inter-layer dielectric film ILD, respectively.

The first-layer metal wirings (M0)61are provided on the inter-layer dielectric film ILD and the first and second contacts41and51. In the second embodiment, the first-layer metal wirings61other than those located on the second contact diffusion layers31_2and32_2extend in the channel width direction DW. The first-layer metal wirings61electrically connect at least a part of the transistors Trp and Trn to the well contact diffusion layers31and32through the second contacts51. Because the second contacts51are the circular-hole contacts and have the diameter in the channel length direction DL almost equal to the feature size F, distances between the first-layer metal wirings61adjacent to each other can be reduced. Accordingly, the layout area of the logic circuit LGC can be decreased. Furthermore, connection wirings in the channel length direction DL can be formed by using second-layer metal wirings (M1)71, third-layer metal wirings (M2)81, or the like, which are upper layers than the first-layer metal wirings61as shown inFIG. 5, as in the first embodiment.

As shown inFIG. 5, the second-layer metal wirings71are electrically connected to the first-layer metal wirings61through the via contacts V1. The third-layer metal wirings81are electrically connected to the second-layer metal wirings71through the via contacts V2.

According to the second embodiment, the first contacts41are the elongated-hole contacts having the major axis in the channel width direction DW (the extension direction of the first-layer metal wirings61and the first contact diffusion layers31_1and32_1). The second contacts51are the circular-hole contacts and have the diameter almost equal to the feature size F. Accordingly, the logic circuit LGC according to the second embodiment can obtain advantages identical to those of the first embodiment. That is, in the second embodiment, it is possible to decrease the layout area of the semiconductor device while reducing the resistances between the first-layer metal wirings and the well contact diffusion layers31and32by a combined use of the first contacts41(elongated-hole contacts) and the second contacts51(circular-hole contacts).

Also in the second embodiment, two or more second contacts51can be arranged within a certain distance from each of the transistors Tr as in the first embodiment. This further reduces the resistance between the first-layer metal wiring61and the well contact diffusion layer31or32. Even if some of the second contacts51are not opened, opening of the other second contacts51enables the transistor Tr to be connected to the well contact diffusion layer31or32in the vicinity of the some of the second contacts51.

The embodiments described above are applied to a single-well structure. However, these embodiments can be applied to a double-well structure or a triple-well structure. Also in these cases, the first contacts40and41connect between wells and a power supply with low resistances, thereby it is possible to suppress a potential of each of the wells from floating.

The analog circuit ANC according to the first embodiment and the logic circuit LGC according to the second embodiment can be combined. Accordingly, the entire layout size of the semiconductor device can be further decreased.