Support structures for wirebond regions of contact pads over low modulus materials

A semiconductor device (200) having support structures (218, 226, 236) beneath wirebond regions (214) of contact pads (204) and a method of forming same. Low modulus dielectric layers (216, 222, 232) are disposed over a workpiece (212). Support structures (218, 226, 236) are formed in the low modulus dielectric layers (216, 222, 232), and support vias (224, 234) are formed between the support structures (218, 226, 236). A high modulus dielectric film (220, 230) is disposed between each low modulus dielectric layer (216, 222, 232), and a high modulus dielectric layer (256) is disposed over the top low modulus dielectric layer (232). Contact pads (204) are formed in the high modulus dielectric layer (256). Each support via (234) within the low modulus dielectric layer (232) resides directly above a support via (224) in the underlying low modulus dielectric layer (222), to form a plurality of via support stacks within the low modulus dielectric layers (216, 222, 232).

TECHNICAL FIELD

The present invention relates generally to semiconductor devices, and more particularly to a structure and method of providing mechanical support for contact pads of integrated circuits.

BACKGROUND OF THE INVENTION

Semiconductor devices are used in integrated circuits for a wide variety of electronics applications, such as televisions, radios and cellular phones, as examples. There is a trend in the electronics industry towards miniaturization of electronic components, so that electronic devices can be made smaller and lighter. Integrated circuits may comprise multiple levels of metallization for interconnections, and multiple layers of dielectric and semiconductor materials. These layers are patterned using lithography to form conductive lines, transistors, and other elements of integrated circuits.

For a long time, silicon dioxide has been commonly used as a dielectric to isolate conductive lines and various components within the various layers. More recently, low-K materials (e.g., materials having a low dielectric constant K) are being used as insulators in semiconductor devices. Using low-k materials provides the benefit of reduced RC time constants of the metallization layers and lower cross-talk, leading to faster speeds and smaller devices.

However, low-K dielectric materials typically have a low modulus and are structurally weak compared to silicon dioxide. The modulus of a material refers to the Young's modulus or elastic modulus, which is a constant for any given material up to its elastic stress limit. The elastic modulus of a material indicates the linear deflection of a material under normal stress, and the modulus is represented by a ratio of this normal stress to linear strain. Low modulus dielectric materials strain and deform easily, thus providing less structural stability for metallization embedded in the low-k dielectric.

An integrated circuit chip or die includes contact pads that are wirebonded, typically using gold wire, to contacts of a package to allow electrical connection to the die when the IC is packaged. Wirebonding typically comprises a welding process, wherein heat is applied to the contact pads and wires to ensure a good connection. Some welding processes include an ultrasonic process that vibrates the wire laterally being bonded to the contact pad, and also applies a downward pressure against the contact pad.

Wirebonding contact pads having low-K dielectric materials disposed beneath the pads is problematic. In the wirebond process, some of the welding stress is transmitted down into the structure of the die below the contact pad. This mechanical stress from the wirebond welding process can damage the contact pads and underlying structures, and cause the contact pads to lift or tear from the silicon substrate, destroying the semiconductor device and decreasing yields. Because low-K materials have a low modulus and are structurally weak, the die is more susceptible to welding damage, resulting in high levels of mechanical failure due to lifts and tears of the contact pads.

SUMMARY OF THE INVENTION

The present invention achieves technical advantages as a structure and method of providing support beneath the contact pads of integrated circuits. Support structures are disposed within metallization layers, and a plurality of support vias is placed between support structures in the various low modulus material layers. The support vias preferably run the entire thickness of the low modulus material layers, and provide increased mechanical support for the contact pad wirebond region. The support structures may comprise conductive lines arranged unidirectionally or orthogonal to one another within adjacent low modulus material layers. Alternatively, the support structures may comprise a plurality of discrete support pads arranged in a grid, circular, or other repeating pattern.

In one embodiment, a semiconductor device includes a workpiece having a contact pad region, with at least one integrated circuit being formed within the workpiece, and a plurality of contact pads being formed within the contact pad region. At least one contact pad is coupled to a signal of the at least one integrated circuit. A first metallization layer is disposed over the workpiece, the first metallization layer including a plurality of first support structures beneath at least the bond portion of the contact pads. A first dielectric layer is disposed between at least the first support structures. A second metallization layer is disposed over the first vias, the second metallization layer including a plurality of second support structures beneath at least the bond portion of the contact pads. A plurality of first support vias is coupled between the top surface of each first support structure and the bottom surface of an overlying second support structure. A first low modulus dielectric layer is disposed between the first support vias and the second support structures. A high modulus dielectric layer is disposed over the first low modulus dielectric layer. The plurality of contact pads is disposed over the high modulus dielectric layer, each contact pad having a bond portion.

In another embodiment, a semiconductor device includes a workpiece having a contact pad region. At least one integrated circuit is formed within the workpiece. The contact pad region includes a plurality of contact pads each having a bond portion, at least one of the contact pads being coupled to an integrated circuit. A plurality of low modulus dielectric layers is disposed over the workpiece. A plurality of metallization layers are formed within the low modulus dielectric layers. Each metallization layer includes a plurality of support structures beneath at least the bond portion of the contact pads. A plurality of support vias are coupled between each support structure of adjacent metallization layers. A high modulus dielectric film is disposed over the low modulus dielectric layers. A first high modulus dielectric layer is disposed over the top low modulus dielectric layer. At least one contact pad is disposed over the first high modulus dielectric layer in the contact pad region. The support vias within the low modulus dielectric layer reside directly above support vias in each underlying low modulus dielectric layer, forming a plurality of via support stacks within the low modulus dielectric layers.

In yet another embodiment, a method of forming a semiconductor device is disclosed. The method includes providing a workpiece comprising a contact pad region, at least one integrated circuit being formed within the workpiece. A plurality of low modulus dielectric layers are formed over the workpiece, and a plurality of support vias are formed within the low modulus dielectric layers, the support vias having a bottom end and a top end. A plurality of support structures are formed within each low modulus dielectric layer in at least the contact pad region, the support structures being coupled to the top ends of the support vias, wherein the bottom ends of the support vias are coupled to support structures in an underlying low modulus dielectric layer. A high modulus dielectric layer is disposed over the top low modulus dielectric layer, and at least one contact pad is formed in the contact pad region within the high modulus dielectric layer.

Advantages of the invention include providing a structural support within low-modulus material layers beneath the wirebond region of contact pads, decreasing the chance of damaging the die during the wirebonding process and increasing yields. The support structures may be coupled to integrated circuits of the semiconductor device and may function as signal lines or power distribution busses. Interconnect lines for the integrated circuits also may be run between adjacent support structures within each low modulus dielectric layer. Support vias coupled between support structures in adjacent low modulus dielectric layers may be positioned directly over one another, forming a via support stack for exceptional mechanical support under the contact pads.

Corresponding numerals and symbols in the different figures refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be discussed, followed by a discussion of the advantages thereof.

FIG. 1illustrates a top view of a semiconductor device100in accordance with embodiments of the present invention that comprises at least one contact pad region102. The contact pad region102contains a plurality of contact pads104located at the top surface of the semiconductor device100. The contact pad region102may be located at the perimeter or edge of the semiconductor device100, as shown; however, alternatively, the contact pad region102may comprise other areas of the semiconductor device100, such as the central region, as an example. The device100includes one or more integrated circuits108formed therein, in underlying layers, for example.

In accordance with embodiments of the invention, two or more layers of support structures are formed within the low modulus, low-K material layers of the semiconductor device beneath at least the wirebond area of the contact pads. A plurality of support vias is formed between the low-K material layers, between the support structures. The support structures and support vias provide mechanical support in the vertical direction for the contact pads. The support structures may comprise unidirectional conductive lines, orthogonal conductive lines, or discrete support pads, to be described further herein.

FIG. 2shows a cross-sectional view of an embodiment of the present invention, in which unidirectional support structures are disposed within each low modulus low-K material layer, with support vias being disposed between the support structures in adjacent low modulus dielectric layers, beneath the wirebond region of the contact pad. The semiconductor device100includes a semiconductor wafer workpiece112comprising a substrate. The workpiece112includes contact pad regions102in which contact pads104will be formed. The workpiece112preferably comprises a semiconductor wafer comprising single-crystal silicon. The workpiece112may alternatively comprise other semiconductors such as GaAs, InP, Si/Ge, SiC, or other compound semiconductors, as examples. Non-semiconductor substrates such as quartz, sapphire or printed circuit board materials may alternatively be used.

The workpiece112preferably comprises one or more integrated circuits108formed therein. The integrated circuits108may be formed outside of the contact pad region102, or in accordance with embodiments of the present invention, the integrated circuits108may also be formed in the contact pad region102, to be described further herein. The workpiece112may also include other conductive layers or other semiconductor elements such as transistors or diodes, as examples, that comprise the integrated circuits108. The integrated circuits108may comprise logic circuits or memory devices, as examples.

Each contact pad104includes a wirebond region114comprising the available area of the contact pad104for bonding to a wire. The wirebond region114is also referred to herein as the bond portion of the contact pad104. The contact pad bond portion114is later used to weld or connect a wire or other connecting device, such as a ribbon, for example, to a contact on an integrated circuit package (not shown). The contact pad104may be about 65 μm wide and 65-130 μm long, for example. The contact pad bond portion114may have an approximate width of 60 μm and a length of 60-120 μm, as examples. A dielectric170will later be disposed around the upper perimeter of the contact pad104, making the contact pad perimeter unavailable for bonding, for example.

A first dielectric material layer116is formed over the workpiece112. The first dielectric material layer116preferably comprises a low-K material, and may alternatively comprise other dielectric materials having a high modulus, for example. When the first dielectric material layer116comprises a low-K material, the low-K material preferably comprises a material having a dielectric constant less than that of silicon dioxide, for example. The low-K materials described herein have a low structural strength and a low elastic modulus. A low modulus dielectric material is defined herein as a dielectric material having a modulus of about 20 GPa or less. The first dielectric material116is preferably about 0.1 to 0.4 μm thick, for example.

A high modulus dielectric film (not shown) is formed over the first dielectric material layer116. The high modulus dielectric film is preferably thin, e.g. 200 Angstroms, and preferably comprises a dielectric such as silicon carbide, an oxide or nitride, or a bi-layer of two materials, as example. The high modulus dielectric film may comprise silicon nitride, for example. A high modulus dielectric material is defined herein as a dielectric material having a modulus of approximately 30 GPa or greater. The high modulus dielectric film functions as an etch stop and protective buffer when forming the support structures118, to be described further herein.

A plurality of first support structures118is formed within the first dielectric material layer116and high modulus dielectric film. The first support structures118are preferably formed within a first metallization layer, e.g., along with interconnects for other regions of the semiconductor device100. Interconnects for the integrated circuits108may be formed at the same time the support structures118are formed (not shown), for example.

Preferably, the first support structures118are formed using a single damascene process. In a damascene process, the dielectric layer116and high modulus dielectric film (not shown) are patterned using lithography and are etched to remove unpatterned portions. A conductive material is used to fill the spaces within the patterned first dielectric material116to form the support structures118. A chemical-mechanical polish (CMP) process is then used to remove any excess conductive material from the top surface of the high modulus dielectric film. The high modulus dielectric film acts as a buffer to prevent erosion of dielectric material layer116in the CMP process.

The support structures118are formed in at least the wirebond region114of the contact pads, and the first support structures118have a top surface. In this embodiment, the support structures118comprise a plurality of discrete unidirectional first conductive lines running parallel to one another in a first direction along either the entire length or width of the contact pad wirebond region114. The conductive lines118may be approximately 2.25×60-100 μm, and may comprise other dimensions depending on the ground rules and feature size of the semiconductor device100, for example.

A high modulus dielectric film120is formed over the high modulus dielectric film on the first dielectric material layer116and over the top surface of the support structures118. The high modulus dielectric film120is referred to herein as a first high modulus dielectric film120. The high modulus dielectric film120is preferably thin, e.g. 200 Angstroms, and preferably comprises a dielectric such as silicon carbide, an oxide or nitride, or a bi-layer of two materials, as example. The high modulus dielectric film120may comprise silicon nitride, for example.

A first low-K material layer122is formed over the first high modulus dielectric film120. The first low-K material layer122preferably comprises a material having a dielectric constant less than that of silicon dioxide, for example. The thickness of the first low-K material layer122is preferably greater than the thickness of the first dielectric material layer116. For example, the first low-K material layer122is preferably about 0.1 to 0.7 μm thick.

A plurality of first support vias124is formed within the first low-K material layer122over each first support structure118. The term “support via” is defined herein as a portion of conductive material disposed within a dielectric layer of a semiconductor device for mechanical support. A support via can, but is not required, to also provide an electrical connection between a conductive layer with an underlying or overlying adjacent conductive layer.

The first support vias124make mechanical and electrical contact with the top surface of the first support structures118. The thin high modulus dielectric film120is preferably removed in the support via124regions to enable the support vias124to make contact with the underlying support structures118, for example. The first support vias124preferably comprise a material the same as or similar to the material of the first support structures118. In accordance with embodiments of the invention, the support vias124are preferably small, e.g., comprising a minimum feature size, such as 0.2-0.5 μm, and the support vias124are preferably spaced apart by the minimum feature,size. The vias124may be 0.3 μm tall, e.g., in the vertical direction, as an example. The support vias124may comprise a number of shapes, and may comprise via bars comprising a minimum feature size in the width direction and longer than the minimum feature size in the length direction, for example.

A plurality of second support structures126is formed within the first low-K material layer122over the first support vias124. The second support structures126preferably comprise a material the same as the material of the first support vias124. Each second support structure126makes contact with a plurality of the underlying first support vias124. The second support structures126may be formed in a second metallization layer; for example, interconnect lines128may be formed in the same processing step the second support structures126are formed in. The second support structures126are preferably disposed directly above the first support structures118, for example. In this embodiment, the second support structures126comprise a plurality of discrete unidirectional second conductive lines running parallel to one another in the first direction (e.g., the same direction as the first support structures118) along either the entire length or width of the contact pad wirebond region114. The conductive lines126may be approximately 2.24 μm×60 to 100 μm, and may comprise other dimensions depending on the ground rules and feature size, for example.

Preferably, a dual damascene process may be used to form the first support vias124and second support structures126. In a dual damascene process, the low-K material layer122is deposited over the first high modulus dielectric layer120, and the low-K material layer122is patterned with the support via pattern. Another lithography process is used to pattern the low-K material layer122with the second support structure pattern. The thin high modulus dielectric layer120functions as an etch stop during the patterning of the low-K material layer122, preventing corrosion and over-etching of the underlying metal support structures118. The exposed thin high modulus dielectric layer120in the support via region is removed, preferably using the same mask used to pattern the support vias124, for example. The patterned areas of the low-K material layer122are filled with a conductive material to form the first support vias124and second support structures126simultaneously. A chemical-mechanical polish (CMP) process is then used to remove excess conductive material from the top surface of the low-K material layer122, for example. Prior to patterning the low-K material layer122, a thin high modulus dielectric layer (not shown) is preferably formed over the low-K material layer122to act a protective buffer during the removal of the excess conductive material.

Alternatively, forming a plurality of first support vias124may comprise a single damascene process, and forming a plurality of second support structures126comprise a single damascene process, for example. A non-damascene process may also be used to form the first support vias124and second support structures126. For example, the vias124may be formed and a low-K material layer122deposited thereon. The support structures126may then be formed, followed by the formation of the remainder of the low-K material layer122.

A plurality of low modulus, low-K material layers132/142/150may be disposed over the first low-K material layer122.FIG. 2depicts a total of four low-K material layers122/132/142/150, as an example, although the number of low-K material layers preferably ranges from one to six or more, in accordance with embodiments of the present invention. The number of low-K material layers is dependent upon the number of metallization layers required for the semiconductor device100, for example.

Within each low-K material layer132/142/150, a plurality of support vias134/144/152is formed that are coupled between adjacent support structures in adjacent metallization layers. Support structures136/146/154are formed within the low-K material layers132/142/150over the support vias134/144/152, as shown.

A high modulus dielectric film130/140/148may be disposed above and below the low-K material layers122/132/142/150. Each high modulus dielectric film120/130/140/148may comprise a bi-layer, with a first layer being formed over the low-K material layer prior to patterning, and a second layer being formed over the low-K material layer and support structure after a CMP step to remove excess conductive material. The high modulus dielectric films120/130/148/157act as an etch stop and provide structural support during CMP after dual damascene fills, for example.

Preferred and alternative materials for the elements will next be described. The low-K material layers122/132/142/150preferably comprise a polymer or spin-on material, such as Silk™, and alternatively may comprise porous hydrocarbon/polymer, carbon doped oxides, polyimides, or hydrogen silsequioxanes, as examples. The support vias124/134/144/152and support structures118/126/136/146/154preferably comprise a metal such as copper, and may alternatively comprise aluminum, tungsten, other conductive materials, or combinations of metals, as examples. The support vias124/134/144/152and support structures118/126/136/146/154may be formed by an electroplating process, for example, which is particularly beneficial if copper is used for the support vias and structures. The thin high modulus dielectric films120/130/140/148preferably comprise an oxide or nitride, and more preferably comprise about 200 Angstroms of silicon nitride. Alternatively, the thin high modulus dielectric films may comprise silicon carbide, nitrogen doped silicon carbide, or TEOS (tetraethyl orthosilicate), as examples. The interconnect lines172/174/176/178/180/138/164/160and vias162preferably comprise a metal such as copper, and may alternatively comprise aluminum, tungsten, other conductive materials, or combinations of metals, as examples.

Preferably, the support vias134/144/152are disposed immediately above the underlying support vias124/134/144, respectively, to form a plurality of via support stacks that extend completely through the low-K material layers122/132/142/150and high modulus dielectric films120/130/140/148. The via support stacks provide improved support beneath the contact pad104in at least the wirebond region114. Alternatively, the support vias134/144/152may be staggered or not aligned with underlying support vias124/134/144, for example.

In one embodiment, optional conductive lines172may be disposed between or interleaved between adjacent support structures118within low-K material layer116. Similarly, optional conductive lines174/176/178/180may be disposed between adjacent support structures126/136/146/154, respectively, within low-K material layers122/132/142/150, respectively. The conductive lines172/174/176/178/180may be coupled to interconnect vias or lines elsewhere along the length of the lines (not shown), to connect to a signal line of an integrated circuit108in the workpiece112, for example.

Furthermore, the support structures136may be coupled to interconnect lines138that run from the contact pad region102to couple to an integrated circuit108signal line. For example, one or more support structures126/136/146/154may be coupled to ground or power, or other signal lines of the semiconductor device100.

After the fabrication of the metallization layers is complete, a dielectric layer156is deposited over the high modulus dielectric film157, as shown in FIG.2. The dielectric layer156preferably comprises a high modulus dielectric, and has a dielectric constant greater than the dielectric constant of the low-K material layers, for example. The dielectric layer156is preferably thicker than the low-K material layers, and may be approximately 0.5 to 2.5 μm thick, for example. The dielectric layer156may comprise a layer of oxide and a layer of nitride, for example, a composite or bi-layer of silicon dioxide and silicon nitride. The dielectric layer156may alternatively comprise other dielectric materials. Because the dielectric layer156comprises a high modulus, support structures and support vias are not required in this dielectric layer.

Preferably, using a reactive ion etch (RIE) process, for example, a tapered via158is formed is formed in the dielectric layer156. The contact pad104is formed preferably by physical vapor deposition (PVD) of a conductive material disposed over dielectric layer156, as an example. The conductive material is patterned and etched preferably using a subtractive RIE process, to remove the excess conductive material from the field area. The contact pad104preferably comprises aluminum and may alternatively comprise other conductors, as examples. Alternatively, contact pad104may be formed by a damascene process. Only one via158and contact pad104are shown, although many vias158and contact pads104are simultaneously formed in the dielectric layer156. The via158also makes contact through the high modulus dielectric film157to the interconnect line160, as shown. The number of contact pads104is dependent upon the required number of input/output (I/O) signals of the semiconductor device100, for example.

The via158is larger than the support vias124/134/144/152and may be 2-5 μm wide, for example. The tapered via158is preferably fully landed on the underlying interconnect line160within the low-K dielectric layer150, to prevent ingress of chemicals from subsequent processing down into the structures below, which may cause corrosion or oxidation. The interconnect line160may be coupled to an underlying interconnect line164in another low-K dielectric layer142by a via162, as shown. Using interconnect lines160/164and vias162/158, the contact pad104is coupled to a signal line of an integrated circuit108.

After the contact pads104are formed, an oxide layer166, comprising silicon dioxide, for example, is deposited over the entire workpiece. A nitride layer168is deposited over the oxide layer166. Layer168preferably comprises silicon nitride, and may alternatively comprise other nitride materials, as examples. A polyimide layer170is deposited over nitride layer168. Polyimide layer170preferably comprises photosensitive polyimide that is used as a resist to pattern underlying oxide and nitride layers166and168. The photosensitive polyimide is then cured, which hardens the polyimide170. The polyimide170is left remaining over the semiconductor device100in regions that will not be wirebonded, and the polyimide acts as a cushion to buffer against stress, for example. Alternatively, the polyimide layer170may comprise other dielectric films and polymers, for example. Layers166,168and170are opened to expose the wirebond region114of the contact pad104so that the contact pads104may later be wirebonded to a contact of an IC package (not shown).

Only two support structures118/126/136/146/154are shown in the wirebond region114inFIG. 2; however, there may be many support structures disposed within the wirebond region114. For example, for a 60×100 μm wirebond region114, there may be approximately 20 parallel conductive support lines disposed within each low modulus dielectric layer122/132/142/150, provided for support. Preferably, the total area of the vias comprises at least 7% of the wirebond region area, and more preferably, at least 18% of the wirebond region area, to provide sufficient structural support for the contact pad104.

FIG. 3shows a top view of the unidirectional support structure embodiment shown inFIG. 2at line3—3of the top dielectric layer, showing the support structures154comprising a plurality of parallel conductive lines. Optional interconnect lines180are disposed between each support structure154, running parallel to the support structures154. The expanded view in the inset illustrates the plurality of support vias152residing below each parallel support conductive line154. The support vias152are shown as having a rectangular shape inFIG. 3; however, the support vias152may be square, rounded, elliptical, bar-shaped (e.g. 0.2 μm×2.0 μm), or may comprise other shapes, as examples.

FIG. 4shows a cross-sectional view of another embodiment of the present invention, in which orthogonal support structures218/226/236are disposed in alternating low modulus/low-K material layers216/222/232beneath the wirebond region214of the contact pad204. A similar process flow and materials may be used to fabricate the semiconductor device200as described for the embodiment shown inFIGS. 2 and 3. As inFIG. 2, the bottom dielectric material layer216may alternatively comprise a high modulus, high dielectric constant material layer.

While three metallization layers are shown inFIG. 4, the semiconductor device200may include more low modulus dielectric layers, but preferably no fewer than one, in accordance with embodiments of the invention. The first support structures218comprise a plurality of first conductive lines running parallel to one another in a first direction along either the entire length or width of the contact pad wirebond region214. The second support structures226comprise a plurality of second conductive lines running parallel to one another in a second direction along either the entire width or length of the contact pad wirebond region214, the second direction being substantially perpendicular to the first direction. A plurality of first support vias224is disposed at each intersection of the first and second conductive lines. The first support vias224are coupled between the top surface of each first support structure and the bottom surface of an overlying second support structure.

The semiconductor device200may further comprise an optional at least one third conductive line282(not shown inFIG. 4; seeFIG. 5) disposed within the first metallization layer between two adjacent first conductive lines, wherein the third conductive line282is coupled to a signal line of an integrated circuit208in the workpiece212(not shown). The semiconductor device200may further comprise an optional at least one fourth conductive line274disposed within the second metallization layer between two adjacent second conductive lines226, wherein the fourth conductive line274is coupled elsewhere to a signal line of an integrated circuit208(not shown).

High modulus films220/330are disposed between adjacent low modulus/low-K material layer. A high modulus dielectric layer256is disposed over the top high modulus film257, and a contact pad204and a tapered via258are formed in the high modulus layer256. Dielectric layers266,268and270are deposited over the high modulus dielectric layer256, and layers266,268and270are opened to expose the wirebond region214of the contact pad204.

FIG. 5shows a top view of the orthogonal support structure embodiment shown inFIG. 4at line5—5. Support vias224are disposed between the metallization layers at the intersection of the support lines218and226. Support vias224are preferably not disposed between the metallization layers at the intersection of the optional interconnect lines274/282, e.g., to prevent shorting of the interconnect lines274/282with the support lines218or226.

FIG. 6shows a top view of another embodiment of the present invention wherein the support structures326comprise a plurality of discrete support pads within each low-K material layer322beneath the wirebond region314of the contact pad. Rather than comprising conductive lines that extend the entire length or width of the wirebond region314as in the other embodiments, the discrete support pads326preferably are substantially rectangular or square shaped as shown inFIG. 6, although the discrete support pads326may comprise other shapes, such as circles, or polygons, as examples. The discrete support pads326are preferably disposed directly over one another in the various low modulus dielectric layers (not shown in FIG.6: see the cross-sectional view of FIG.2). Alternatively, the support structures may be staggered or not aligned. The discrete support pads326may comprise a plurality of discrete support pads arranged in a grid, circular, or other repeating pattern, for example. In a preferred embodiment, the support pads326comprise dimensions of 2×2 μm to 3×3 μm, for example.

A plurality of support vias324are disposed between each adjacent support pad within the low modulus dielectric layer322, as in the other embodiments described herein. The support vias324are preferably aligned with underlying support vias to form a support via stack, although alternatively, the support vias324in the dielectric layers may not be aligned. Optionally, at least one of the discrete support pads326may be coupled to a signal line of an integrated circuit in the workpiece (not shown). Another option is to dispose a conductive line between two adjacent first support pads, wherein the first conductive line is coupled to a signal line of an integrated circuit in the workpiece (not shown inFIG. 6; seeFIG. 2at line6—6).

In each embodiment, including unidirectional support structures, orthogonal support structures, and discrete support pads, preferably, support vias reside in 18% or greater of the wirebond region of each contact pad. In particular, the wirebond region comprises an area which equals the wirebond region length×width. Each support via comprises an area that equals the support via length×width. The total of all support via areas within one low modulus dielectric layer in the wirebond region preferably comprises at least 18% of the area of the wirebond region of the contact pads. At a minimum, the total of all support via areas within a low modulus dielectric layer in the wirebond region preferably comprises at least 7% of the area of the wirebond region of the contact pads, in accordance with embodiments of the minimum.

A relationship exists between the percentage of via support area to wirebond region area, and the thickness of the high modulus dielectric layer156/256. The lower the percentage of via support area, the greater the thickness of the high modulus dielectric layer over the low modulus dielectric material stack is required to be. However, if the high modulus dielectric layer156/256is too thick, the aspect ratio of the via158/258is large, and a good fill may not be achieved when forming the vias158/258. If at least 18% of the wirebond region is supported by support vias, then 1-2.5 μm is a sufficient thickness of the high modulus dielectric layer156/256, for example.

Furthermore, preferably, as described herein, the support vias in each low modulus dielectric layer for each embodiment described herein are aligned positionally, creating a via support stack beneath the wirebond region.

In one embodiment of the present invention, shown inFIG. 7, the plurality of support vias424/434are formed in a high modulus, high dielectric material layer422′/432′. The device400shown inFIG. 7is formed using similar processes and materials as shown inFIG. 4, for example. The support structures418/426/436may comprise unidirectional conductive lines, orthogonal conductive lines or discrete support pads, as described for other embodiments herein.

The high modulus dielectric layers422′ and432′ preferably comprise silicon carbide, oxides or nitrides, or a combination thereof, for example. Support vias424/434may be formed in a single damascene process. Alternatively, support vias and support structures may be formed in a dual damascene process, as described for other embodiments herein. In such a dual damascene process, high modulus dielectric layer422′ is deposited over thin high modulus film420, and low modulus dielectric layer422is deposited over the high modulus dielectric layer422′. A first portion of thin high modulus layer430is deposited over the low modulus dielectric layer422. The dielectric layers430/422/422′ are patterned and etched using two masks, for example, and more than one RIE step, to form the pattern for both support vias424and support structures426. Conductive material is deposited over the dielectric layers430/422/422′, and a CMP process is used to remove excess conductive material from the surface of the device400, stopping on the thin high modulus film430. A second portion of thin high modulus layer430is deposited over the low modulus dielectric layer422and the conductive material prior to depositing other low-K dielectric layers. A similar process is used to A form other support structures and support vias in subsequently deposited low-K dielectric layers.

Another embodiment of the present invention comprises a method of forming a semiconductor device. The method includes providing a workpiece comprising a contact pad region, wherein at least one integrated circuit has been formed within the workpiece. A plurality of low modulus dielectric layers are formed over the workpiece, and a plurality of support vias are formed within each low modulus dielectric layer, the support vias having a bottom end and a top end. A plurality of first support structures are within each low modulus dielectric layer in at least the contact pad region, the first support structures being coupled to the top ends of the support vias, wherein the bottom ends of the support vias are coupled to first support structures in an underlying low modulus dielectric layer. A high modulus dielectric layer is formed over the top low modulus dielectric layer, and at least one contact pad is formed in the contact pad region within the high modulus dielectric layer.

In one embodiment, forming the plurality of support structures comprises forming a plurality of conductive lines running parallel to one another in a first direction along at least the length of the contact pad wirebond region. At least one of the conductive lines may be coupled to a signal line of an integrated circuit in the workpiece. A signal-conducting line may be formed within at least one metallization layer between two adjacent conductive lines, wherein the signal-conducting line is coupled to a signal line of an integrated circuit in the workpiece.

In another embodiment, forming the support structures comprises forming support structures in odd alternating low modulus dielectric layers by disposing a plurality of first conductive lines parallel to one another in a first direction along at least the length of the contact pad wirebond region. Forming support structures in even alternating low modulus dielectric layers comprises disposing a plurality of second conductive lines parallel to one another in a second direction along at least the width of the contact pad wirebond region, the second direction being substantially perpendicular to the first direction. Preferably, forming the support vias comprises disposing the support vias at the intersection of the first and second conductive lines. A signal-conducting line may be disposed within at least one metallization layer between two adjacent first and/or second conductive lines. The signal-conducting line may be coupled to a signal line of an integrated circuit in the workpiece.

In yet another embodiment, forming the support structures comprises forming a plurality of discrete support pads. At least one of the support pads may be coupled to a signal line of an integrated circuit in the workpiece. At least one first conductive line may be disposed between two adjacent support pads within the metallization layer, and the first conductive line may be coupled to a signal line of an integrated circuit in the workpiece.

The method may include disposing a high modulus dielectric film between each two adjacent low modulus dielectric layers, and positioning the plurality of support vias over one another within each low modulus dielectric layer to form a via support stack.

The present invention provides several advantages over prior art contact pad support structures. Because interconnect lines may be run underneath the contact pad, a staggered wirebond pitch may be achieved, which increases the I/O density of the semiconductor device. A structural support is provided within low-modulus material layers beneath the wirebond region of contact pads, reducing damage to the die during the wirebonding process, and thus, increasing yields. The support structures may be used for mechanical support only, or alternatively, the support structures may be coupled to integrated circuits of the semiconductor device and function as signal lines. Because the support structures comprise a plurality of discrete lines or pads, not only may the discrete support lines and pads be coupled to more than one signal, furthermore, interconnect lines may be positioned within each low modulus dielectric layer beneath the wirebond region. The interconnect lines for the integrated circuits also may be interleaved between adjacent support structures within each low modulus dielectric layer. Support vias coupled between support structures in adjacent low modulus dielectric layers may be positioned directly over one another, forming a via support stack for exceptional mechanical support under the contact pads.

Running interconnect lines between the support structures is advantageous because not only is silicon area conserved, additionally, in the unidirectional and orthogonal embodiments, the support structures function as a shield and reduce noise on the interconnect lines. The support structures may be coupled to a ground or other signal of the integrated circuits to further reduce noise. The orthogonal embodiment of the invention provides the flexibility to run conductive lines in more than one direction beneath the wirebond region. Wiring interconnect through the orthogonal support structure prevents line-to-line capacitance coupling.

While the support via and support structures have been described herein as being formed in single or dual damascene processes, alternatively, the support vias and support structures may be made by depositing a conductive material, patterning the conductive material to form the support vias and support structures, and forming the low-K material layers over the conductive material, using conventional metallization layer formation techniques. Furthermore, the invention has been described with reference to low-K dielectric material layers. However, embodiments of the invention have application when low modulus material layers of any type are formed beneath contact pads of a semiconductor device.

While the invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications in combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. In addition, the order of process steps may be rearranged by one of ordinary skill in the art, yet still be within the scope of the present invention. It is therefore intended that the appended claims encompass any such modifications or embodiments. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.