Fast acquisition phase-lock loop

A PLL frequency detector or comparator is provided having an up-down counter, responsive to beat signals produced by the input periodic waveforms of the VCO reference signals and the input data signals, to produce top and bottom output signals which enable multivibrators connected to each of the input signal lines to transmit overflow and underflow output pulses, whose sum is proportional to the difference in frequency of the input signals up to a predetermined maximum level, as control signals for the PLL loop filter. The up-down counter may include three or more states with buffer states which prevent generation of overflow or underflow output signals when the PLL is within a predetermined region of phase-lock and the sign of the beat signal oscillates. The up-down counter may also be employed simultaneously as a phase detector or comparator, wherein the top and bottom output signals are combined so as to produce control signals for the PLL loop filter when the overflow and underflow output signals are not generated.

BACKGROUND AND SUMMARY OF THE INVENTION 
The present invention relates generally to phase-lock loop circuits and, 
more particularly, to such circuits having frequency detectors for fast 
lock acquisition. 
Phase lock loops (hereinafter referred to as "PLLs") are often employed 
with data communications equipment such as frequency and signal 
synthesizers and jitter measurement circuits. With PLLs having narrow, 
flat gain bandwidths on the order of 1 Hz, stability constraints result in 
a lock acquisition time for phase-lock which can be several seconds. In 
present high speed circuits, this represents a considerable delay. 
Second order phase-lock loops typically include frequency detector or 
comparator means to assist in acquiring lock when an extended range of 
input data signal frequencies is expected. Such a conventional PLL circuit 
is shown in block diagram form in FIG. 1. Frequency detector 10 and phase 
detector 15 each receive frequency signals f.sub.1 and f.sub.2. Frequency 
f.sub.1 is of the system input data signal and f.sub.2 is of the reference 
signal generated by voltage controlled oscillator (hereinafter referred to 
as "VCO") 30. Frequency detector 10 and phase detector 15 may be referred 
to generally as the PLL input stage and serve to compare the frequency and 
phase of signals f.sub.1 and f.sub.2, respectively. The frequency and 
phase difference between these signals is used to generate error signals 
V.sub.f and V.sub.d, respectively, which are fed back to VCO 30 through 
loop filter 20 to control the frequency f.sub.2 so as to reduce the phase 
and frequency difference with respect to f.sub.1. As will be readily 
understood by those skilled in the art, frequency detector 10 provides a 
coarse tuning of VCO 30, and phase detector 15 provides a fine tuning of 
VCO 30. 
Frequency synthesizers and jitter measurement circuits often employ a PLL 
having a bandwidth on the order of 1 Hz. Even with frequency detectors, 
the lock acquisition time for such conventional PLLs is typically greater 
than ten seconds. While such a long acquisition time is satisfactory for 
machine-only environments, it is desirable to reduce waiting time to 
fractions of a second when human operators are involved. 
Lock acquisition time for PLLs is largely a function of the loop filter 
response to frequency and phase difference signals from the corresponding 
detector means. FIG. 2 shows a schematic diagram of a conventional loop 
filter 20 suitable for use in the PLL circuit of FIG. 1. Operational 
amplifier 22 has its positive terminal grounded, and input signal voltage 
V.sub.d from phase detector 15 connected to its negative terminal across 
resistor 24. Input signal voltage V.sub.f from frequency detector 10 is 
connected to capacitor 28 in the feedback loop across resistor 25 and to 
the negative terminal of operational amplifier 20 across resistors 25 and 
26 in series. Loop filter 20 provides control voltage V.sub.c to VCO 30 to 
reset f.sub.2 to match the system input signal f.sub.1. 
In order to acquire lock, capacitor 28 must be charged to a voltage that 
will set the VCO to the proper frequency. The frequency detector is 
primarily responsible for charging capacitor 28. For PLLs with a narrow 
bandwidth and wide input frequency range, capacitor 28 must be larger and, 
thus, it often takes a longer time to charge. It has been found that 
modifying the frequency detector will permit modification of this charging 
time. 
Combined phase and frequency detectors in PLLs have been employed to aid in 
lock acquisition and have been realized through the use of up-down 
counters. The output voltage versus frequency characteristic of such 
devices when employed as a frequency detector in a PLL is shown 
graphically in FIG. 3. While a signal representing the sign of the 
frequency difference of the input data and clock signals is provided, such 
a device gives little or no indication of the magnitude of the difference 
in frequency. As a result, capacitor 28 is charged at a generally constant 
rate, and the acquisition time is proportional to the initial frequency 
difference detected. Mathematically, the relationship may be represented 
by: 
EQU T.sub.p =2.DELTA.f/(.pi..sup.2 f.sub.BW) Eq. 1 
where T.sub.p is the acquisition time, .DELTA.f is the initial detected 
frequency difference, and f.sub.BW is the PLL bandwidth. 
T.sub.p can be reduced by amplifying frequency detector output signal 
V.sub.f to charge capacitor 28 sooner. It has been suggested alternatively 
(because of the different technologies involved) to achieve this by 
increasing the pulse rate of V.sub.f or by increasing the signal amplitude 
of V.sub.f as the frequency difference increases. However, if V.sub.f 
becomes too large when f.sub.1 is approximately equal to f.sub.2, the PLL 
will overshoot the lock region and become unstable. To make V.sub.f larger 
overall but small where f.sub.1 -f.sub.2 is approximately zero, V.sub.f 
should be made proportional to f.sub.1 -f.sub.2. Prior PLL devices, such 
as the quadricorrelator and the rotational frequency detector, have 
attempted to do this, but have only been successful within a relatively 
small frequency range. FIG. 4 shows graphically the output voltage versus 
frequency characteristics for these devices when employed as frequency 
detectors in a PLL. 
As can be seen, V.sub.f is proportional to f.sub.1 -f.sub.2 only over a 
small frequency difference of approximately .+-.25%. In this range the 
acquisition time can be expressed as: 
EQU T.sub.p =(4.pi.f.sub.BW).sup.-1 ln(.DELTA.f/2.pi.f.sub.BW) Eq. 2 
This logarithmic function of .DELTA.f grows relatively slowly. For example, 
if f.sub.BW =1 Hz and .DELTA.f=50 Hz, then T.sub.p= 0.17 seconds. Under 
the same conditions, the frequency detector represented by Equation 1 
would result in an acquisition time of ten seconds. If .DELTA.f is 
increased to 100 Hz, the device of Equation 2 would have a T.sub.p of 0.22 
seconds while the device of Equation 1 would have a T.sub.p of 20 seconds. 
Thus, such quadricorrelator devices perform satisfactorily if .DELTA.f is 
approximately less than one quarter of f.sub.1. 
However, if .DELTA.f becomes greater that f.sub.1 /2, quadricorrelator and 
rotational frequency detectors cannot be used in PLLs to effectively 
charge capacitor 28 and acquire phase-lock. Therefore, it is desirable to 
provide a frequency detector wherein V.sub.f is proportional to f.sub.1 
-f.sub.2 over an extended range. 
An object of the present invention is to provide a frequency comparator for 
phase-lock loop circuits having fast lock acquisition time. 
Another object of the present invention is the provision of a frequency 
detector in a phase-lock loop circuit whose output voltage signal is 
proportional to the difference between the frequencies of its input 
signals over an extended frequency range. 
A further object of the present invention is the provision of a combined 
phase and frequency comparator for a plurality of input periodic waveforms 
having fast lock acquisition time and increased loop stability. 
These and other objects of the present invention are attained in the 
provision of a PLL frequency detector or comparator having an up-down 
counter, responsive to beat signals produced by the input periodic 
waveforms of the VCO reference signals and the input data signals, to 
produce top and bottom output signals which enable multivibrators 
connected to each of the input signal lines to transmit overflow and 
underflow output pulses, whose average is proportional to the difference 
in frequency of the input signals up to a predetermined maximum level, as 
control signals for the PLL loop filter. The up-down counter may also 
include three or more states with buffer states which prevent generation 
of overflow or underflow output signals when the PLL is within a 
predetermined region of phase-lock and the sign of the beat signal 
oscillates. The up-down counter may also be employed simultaneously as a 
phase detector or comparator, wherein the top and bottom output signals 
are combined so as to produce control signals for the PLL loop filter when 
the overflow and underflow output signals are not generated. 
Other objects, advantages and novel features of the present invention will 
become apparent from the following detailed description of the invention 
when considered in conjunction with the accompanying drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS 
The especially preferred embodiments of the present invention to be 
described are employed in the conventional PLL circuit shown in FIG. 1 
with the below described improvements and modifications. 
FIG. 5 illustrates, in block diagram form, a preferred embodiment of a 
proportional frequency detector of the present invention. This 
proportional frequency detector includes an up-down counter 50 having 
circuit input data signals of frequency f.sub.1, applied to its "Up" 
signal input and VCO-generated input reference signals of frequency 
f.sub.2 applied to its down or "Dwn" signal input. The same circuit input 
data signals and reference signals applied to counter 50 as "Up" and "Dwn" 
inputs are also input to monostable multivibrators 56 and 58, 
respectively. "Top" output line 52 and "bottom" output line 54 from 
counter 50 provides enabling signals T and B to multivibrators 56 and 58, 
respectively. The outputs from multivibrators 56 and 58 are algebraically 
summed at 60 and provide control or input signals V.sub.f to loop filter 
20 which charge capacitor 28 (shown in FIGS. 1 and 2, respectively). 
Thus, counter 50 provides output signals at a rate which is a function of 
the difference between f.sub.1 and f.sub.2. When f.sub.1 is greater than 
f.sub.2, counter 50 produces output pulses along top output line 52. When 
f.sub.2 is greater than f.sub.1, counter 50 produces output pulses along 
bottom output line 54. These output pulses enable multivibrators 56 and 58 
which are then triggered by the input signals having frequencies f.sub.1 
and f.sub.2, respectively. To simplify the discussion below, input signals 
to multivibrator 56 will be referred to as "Up signals," and input signals 
to multivibrator 58 will be referred to as "Dwn signals." Thus, 
multivibrators 56 and 58 and summer 60 in combination function as an 
overflow and underflow transmission gate 62. Since the output pulses are, 
in the simplest case, produced at a rate proportional to .vertline.f.sub.1 
-f.sub.2 .vertline. and the multivibrators are enabled at this same rate, 
the output pulse rate from multivibrators 56 and 58 is also proportional 
to the difference between f.sub.1 and f.sub.2. Specifically, multivibrator 
56 passes responsive pulses of input frequency f.sub.1 at a rate of 
f.sub.1 -f.sub.2 when f.sub.1 is greater than f.sub.2, but is not enabled 
when f.sub.2 exceeds f.sub.1. Likewise, multivibrator 58 passes responsive 
pulses of input frequency f.sub.2 at a rate of f.sub.2 -f.sub.1 when 
f.sub.2 is greater than f.sub.1, but is not enabled when f.sub.1 exceeds 
f.sub.2. 
Multivibrators 56 and 58 produce output pulses of width .tau.. These pulses 
are input to algebraic summer 60 and output therefrom as signals V.sub.f. 
These output signals V.sub.f are inputs to loop filter 20 and represent, 
over time, the average of the multivibrator output pulses. It will be 
readily understood by those skilled in the art that negative values of 
V.sub.f result from the output pulses of multivibrator 58, when f.sub.2 
exceeds f.sub.1. Since the multivibrator pulse rate is proportional to 
.vertline.f.sub.1 -f.sub.2 .vertline., V.sub.f is also proportional to 
f.sub.1 -f.sub.2, at least until the saturation level is reached. When 
.vertline.f.sub.1 -f.sub.2 .vertline.&gt;1/.tau., the multivibrator output 
pulses will overlap and, thus, V.sub.f cannot be increased. At this point 
V.sub.f is considered saturated. The saturation frequency is given by 
f.sub.sat =1/.tau., and represents the highest frequency at which the 
given frequency detector produces a V.sub.f proportional to f.sub.1 
-f.sub.2. 
FIG. 6 shows graphically the output voltage versus frequency 
characteristics (V.sub.f versus f.sub.1 -f.sub.2) of the frequency 
detector illustrated in FIG. 5. As can be seen, the proportionality of 
V.sub.f with respect to the magnitude and polarity f.sub.1 -f.sub.2 is 
extended until a predetermined .+-.f.sub.sat. After .+-.f.sub.sat is 
reached, V.sub.f levels off to a fixed value. 
A comparison of FIGS. 3 and 4 with FIG. 6 shows the dramatic improvement of 
the subject invention over prior PLLs. In particular, where f.sub.1 
-f.sub.2 is approximately zero, substantially linear proportionality is 
provided by the subject invention for either polarity or sign of .DELTA.f. 
This permits increased stability and shorter acquisition time, especially 
as compared with the PLL of FIG. 3. That prior device provides output 
signals indicative primarily of the polarity of f.sub.1 -f.sub.2 as 
.DELTA.f approaches zero. A quantum jump is made through zero as polarity 
changes. Thus, if f.sub.2 approaches f.sub.1 too quickly, that PLL has a 
tendency to become unstable as phase-lock is overshot. 
As compared with the quadricorrelator device of FIG. 4, the subject 
invention provides a greatly extended effective range and avoids 
periodicity after .+-.f.sub.1 /4. The PLL of the subject invention 
provides a substantially constant output beyond .+-.f.sub.sat. By careful 
selection of circuit elements determinative of .tau., f.sub.sat can be 
established at any desired level. This constant output may be established 
as the positve or negative maximum output, as shown in FIG. 6. 
Both inputs to counter 50 of the frequency detector are periodic waveforms. 
Digital data and clock signals have been typically applied as such inputs 
in prior PLLs and, thus, a wide range has not been achievable. Further, 
counter 50 responds to beat signals produced every time the input signals 
pass through phase. 
FIG. 7 shows a circuit diagram for an up-down counter 70 suitable for use 
in the frequency detector of FIG. 5. Counter 70 includes D-type flip-flops 
72 and 74 having data inputs D.sub.1 and D.sub.2 and outputs Q.sub.1 and 
Q.sub.2, respectively. Flip-flops 72 and 74 receive Up and Dwn input 
signals, respectively, as clock inputs. The outputs of both flip-flops are 
inputs to logic element 76 which produces an exclusive NOR output gate on 
top output line 52 and an exclusive OR output gate on bottom output line 
54. Further, the output of flip-flop 72 from Q.sub.1 is an input to 
flip-flop 74 at D.sub.2, and the output of flip-flop 74 from Q.sub.2 is an 
input to flip-flop 72 at D.sub.1. 
Briefly, counter 70 causes a signal T to be produced on top output line 52, 
but not on bottom output line 54, when the frequency of Up input signals 
exceeds that of Dwn input signals. Likewise, a signal B is produced on 
bottom output line 54, but not on top output line 52, when the frequency 
of Dwn input signals exceeds that of the Up input signals. As the Up and 
Dwn input signals pass through phase, the output signals change from one 
output line to another. A state diagram for two state up-down counter 70 
is shown in FIG. 8. 
FIG. 9 shows a circuit diagram for another up-down counter 80 suitable for 
use in the frequency detector of FIG. 5. Similar circuits may be found in 
commercially available counters such as Motorola MC4044 or MC12040. 
Counter 80 includes D-type flip-flops 82, 84, 86 and 88. Flip-flops 82 and 
84 receive Up input signals as clock inputs, and flip-flops 86 and 88 
receive Dwn input signals as clock inputs. The Q output of flip-flop 82 is 
applied as one of the two inputs of exclusive OR gate 90 and as one of the 
two inputs of exclusive NOR gate 98. The Q output of flip-flop 86 is 
applied as the other of the two inputs of exclusive OR gate 90 and as one 
of the two inputs of the exclusive OR gate 96. The output of exclusive OR 
gate 90 is applied as one of the two inputs to exclusive OR gate 92 and as 
one of the two inputs to exclusive OR gate 94. The output of exclusive OR 
gate 92 is the D input to flip-flop 84. The output of exclusive OR gate 94 
is the D input to flip-flop 88. The Q output of flip-flop 84 is applied as 
the other of the two inputs to exclusive OR gate 96, as the other of the 
two inputs to exclusive OR gate 94 and as the D input to flip-flop 86. The 
Q output of flip-flop 88 is applied as the other of the two inputs to 
exclusive NOR gate 98, as the other of the two inputs to exclusive OR gate 
92 and as the input to inverter 91. The output of inverter 91 is the D 
input to flip-flop 82. The output of exclusive OR gate 96 is applied to 
top output line 52. The output of exclusive NOR gate 98 is applied to 
bottom output line 54. 
Briefly, as the operation of the counter 80 will now be readily understood 
by those skilled in the art, counter 80 is a three state counter which 
will cause an overflow signal to be produced on output line 63, but not on 
underflow output line 64, when counter 80 is already in its top state and 
the frequency of Up input signals continue to exceed the frequency of D 
input signals. Similarly, an underflow signal will be produced on 
underflow output line 64, but not on overflow output line 63, when counter 
80 is already in its bottom state and the frequency of the Dwn input 
signals continues to exceed the frequency of the Up input signals. 
However, if the Up signal frequency does not continue to exceed the Dwn 
signal frequency when counter 80 is in its top state, or if the Dwn signal 
frequency does not continue to exceed the Up signal frequency when counter 
80 is in its bottom state, or if counter 80 is in its middle or "buffer" 
state, then no signals will be output on either line 63 or line 64. 
The state diagram for three-state up-down counters such as counter 80 is 
shown in FIG. 10. The presence of an internal buffer state allows the 
counter to be used as a phase detector with a range of .+-.360 degrees, as 
well as frequency detector. 
The present invention contemplates that any number of buffer states may be 
employed as desired in a given up-down counter of a particular embodiment 
of the present invention. FIG. 11 shows a general state diagram for 
counters having N states with N-2 buffer states. By comparison, counter 
70, as shown in FIG. 7, has no buffer state such that a signal T or B is 
always present at either output line 52 or 54, respectively. 
In particular applications, either counter 70 or counter 80 will perform 
adequately in the proportional frequency detector of FIG. 5. However, 
often when incorporating a proportional frequency detector in the PLL of 
FIG. 1, considerable savings may be realized by using a single device for 
two functions. In particular, the up-down counter of the proportional 
frequency detector may also be employed within the phase detector. Such an 
arrangement is illustrated in FIG. 12. It has been found to be often 
preferable to use at least a three state counter for such dual function 
detector circuits because of its greater phase range as compared to 
up-down counters without buffer states. 
FIG. 12 shows a PLL 100 having up-down counter 150 with circuit input data 
signals of frequency f.sub.1 applied as Up signals to the counter's up 
input and reference signals of frequency f.sub.2 applied as Dwn signals to 
the counter's down input. Counter 150 produces T and B output signals as a 
function of (f.sub.1 -f.sub.2) along top output line 152 and bottom output 
line 154, respectively, as described herein above. 
In the frequency detector portion of PLL 100, the T signals are data inputs 
to D-type flip-flop 151 and the B signals are data inputs to D-type 
flip-flop 153. Flip-flop 151 receives Up signals as clock inputs and 
flip-flop 153 receives Dwn signals as clock inputs. The Q output of 
flip-flop 151 is received as an input by AND gate 155. The circuit input 
data signals, or Up signals, are applied to the other input of AND gate 
155. The Q output of flip-flop 153 is received as an input by AND gate 
157. VCO generated reference signals, or Dwn signals, are applied to the 
other input of AND gate 157. The output of AND gates 155 and 157 are 
received as clock inputs by monostable multivibrators 156 and 158, 
respectively. MC10198 is a commercially available device which may be 
adopted to provide each of the combination of elements 151, 155 and 156 
and the combination of elements 153, 157 and 158. For example, to form the 
latter combination, B signals may be applied to the E+ enable input and 
Dwn signals applied to the trigger input of MC10198. 
The signals output from multivibrator 158 are applied to inverter 161, and 
the output from that inverter is applied to resistor 125, having 
resistance value R.sub.3, of loop filter 120. The signals output from 
multivibrator 156 are applied to another resistor 125, in parallel with 
the resistor receiving inverter 161 output signals and of the same R.sub.3 
value. The signals output from these resistors 125 are combined and 
applied as V.sub.f to capacitor 128 and, across resistor 126 of resistance 
value R.sub.2, to the negative input of operational amplifier 122. 
Capacitor 128 is included in loop filter 120 and is connected across the 
feedback loop of operational amplifier 122. 
The phase detector portion of PLL 100 includes counter 150 and inverter 
163, providing T and B as inputs to loop filter 120. This inverter 
receives B signals as inputs and produces output signals to resistor 124, 
having resistance value R.sub.1, of loop filter 120. T signals from 
counter 150 are applied to another resistor 124, in parallel with the 
resistor receiving inverter 163's output signals and of the same R.sub.1 
value. The output signals produced by these resistors 124 are both applied 
as V.sub.P to the negative input of operational amplifier 122. The 
positive input of that operational amplifier has a threshold voltage 
V.sub.TH applied thereto. 
The output of loop filter 120 is applied to voltage controlled oscillator 
130 to control the frequency f.sub.2 of the reference signal applied to 
counter 150 and output from PLL 100. In general, the size of R.sub.3 
determines the strength of the frequency acquisition. In many embodiments, 
the PLL will overshoot and become unstable if R.sub.3 is not greater than 
or equal to (R.sub.1 .tau.)/(2R.sub.2 C). R.sub.1, R.sub.2, and .tau. are 
as defined above. C is the capacitance value of capacitor 128. The 
acquisition time of Equation 2 is realized when this R.sub.3 boundary is 
just met. 
In summary, the present invention provides a proportional frequency 
detector for PLLs which permits significant decreases in acquisition time 
by quickly charging the loop filter capacitance. The pull-in time (or lock 
acquisition time) versus the range (or bandwidth) is a logarithmic 
relation. Thus, small increases in acquisition time permit great gains in 
pull-in range. However, at the same time that V.sub.f is made large enough 
to quickly charge the loop filter and achieve this fast pull-in, means are 
provided to prevent the PLL from jumping over the lock acquisition range. 
Further, the present invention provides circuits of increased versatility. 
The PLL cost may be significantly reduced since the frequency detector and 
phase detector circuits share components. 
From the preceeding description of the preferred embodiments, it is evident 
that the objects of the invention are attained. Although the invention has 
been described and illustrated in detail, it is to be clearly understood 
that the same is by way of illustration and example only and is not to be 
taken by way of limitation. The spirit and scope of the invention are to 
be limited only by the terms of the appended claims.