Semiconductor device manufacture method and semiconductor device

A semiconductor device manufacture method includes: forming an insulating film above a semiconductor substrate; etching the insulating film to form a dummy groove having a first depth, a wiring groove having a second depth deeper than the first depth, and a via hole to be disposed on a bottom of the wiring groove; depositing a conductive material in the dummy groove, wiring groove and via hole and above the insulating film; and polishing and removing the conductive material above the insulating film.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application JP2010-149354, filed on Jun. 30, 2010, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a semiconductor device manufacture method and a semiconductor device.

BACKGROUND

In order to obtain low resistance fine wirings, wirings are formed by a damascene method by using copper (Cu) or copper alloy as wiring material. According to a general damascene method, a barrier metal film is formed on an interlayer insulating film, covering a wiring trench formed in the interlayer insulating film, a seed film is formed on the barrier metal film, and a Cu film for example is formed by a plating method on the seed film. Unnecessary portions of the Cu film and barrier metal film on the interlayer insulating film are removed by chemical mechanical polishing (CMP) to leave wirings in the wiring trenches.

If a conductive layer such as a barrier metal film is left on the interlayer insulating film after polishing, this conductive layer may cause leak between wirings. In order to prevent the conductive layer from being left on the interlayer insulating film, an upper portion of the interlayer insulating film is cut to some depth during CMP for the conductive layer to perform so-called over polishing.

An interlayer insulating film using low dielectric material having a dielectric constant of, e.g., 3.0 or lower has been proposed recently in order to reduce a parasitic capacitance (e.g., refer to Japanese Patent Laid-open Publication No. 2006-156519). The low dielectric constant film of this type contains methyl groups (CHx) and the like and is hydrophobic. Therefore, the surface of the low dielectric constant film have a tendency to repel CMP polishing slurry, and polishing is hard to progress.

An interlayer insulating film having the structure that a hydrophilic cap film made of, e.g., silicon oxide (SiO2) is formed on a hydrophobic low dielectric constant film has therefore been proposed. The cap film is over-polished. The low dielectric constant film has low tight adhesion to the underlying insulating film, and is likely to have film stripping. Polishing is stopped by leaving the cap film to some thickness from the viewpoint of preventing film stripping.

However, since silicon oxide (SiO2) has a dielectric constant of over 3.0, if this film is left on the low dielectric constant film, parasitic capacitance between wirings becomes high. In order to avoid high parasitic capacitance, techniques of directly polishing a hydrophobic low dielectric constant film without using a cap film have been developed.

In polishing an interlayer insulating film using a hydrophobic low dielectric constant film, polishing slurry has high wettability in an area where wirings are disposed densely, whereas polishing slurry has low wettability in an area where wirings are disposed coarsely. In the area where wirings are disposed coarsely, dishing and erosion are likely to occur. Dishing and erosion do not occur only when an interlayer insulating film using a hydrophobic low dielectric constant film is polished, but dishing and erosion may occur when a polishing target having a plurality of different materials such as an insulating film having a buried conductive Cu film is polished.

Techniques of providing a uniform wiring density in a wafer plane by disposing dummy wirings between wirings have been proposed to suppress dishing and erosion. Parasitic capacitance is, however, formed between dummy wirings and wirings, and a wiring delay occurs.

SUMMARY

According to one aspect of the present invention, a semiconductor device manufacture method includes: forming an insulating film above a semiconductor substrate; etching the insulating film to form a dummy groove having a first depth, a wiring groove having a second depth deeper than the first depth, and a via hole to be disposed on a bottom of the wiring groove; depositing a conductive material in the dummy groove, wiring groove and via hole and above the insulating film; and polishing and removing the conductive material above the insulating film.

According to another aspect of the present invention, a semiconductor device manufacture method includes: forming an insulating film above a semiconductor substrate; forming a dummy groove having a first depth in the insulating film; burying a burying material in the dummy groove; forming a wiring groove having a second depth deeper than the first depth; removing the burying material from the dummy groove; depositing a conductive material in the dummy groove, wiring groove and above the insulating film; and polishing and removing the conductive material above the insulating film.

DESCRIPTION OF EMBODIMENTS

Description will be made first on a wiring forming method by a single damascene method according to the first embodiment.FIGS. 1A to 1Kare schematic cross sectional views illustrating main processes of a wiring forming method according to the first embodiment.

Reference is made toFIG. 1A. An element separation insulating film2is formed in a semiconductor substrate, e.g., a silicon substrate by shallow trench isolation (STI) to define active regions. A MOS transistor3is formed in the active region.

For example, silicon oxide (SiO2) is deposited on the semiconductor substrate1to a thickness of 300 nm to 1000 nm by chemical vapor deposition (CVD) to form an interlayer insulating film4covering the MOS transistor3. Contact holes for connection of the source/drain regions of the MOS transistor3are formed through the interlayer insulating film4by photolithography and etching. Tungsten (W) is buried in the contact holes through, e.g., titanium nitride (TiN) layer to form a contact plug5.

For example, silicon carbide (SiC) is deposited on the interlayer insulating film4to a thickness of 10 nm to 200 nm by CVD to form an etching stopper insulating film6. In addition to silicon carbide, silicon carbonitride (SiCN), silicon nitride (SiN) and the like may be used for the etching stopper film6. The etching stopper film6may have a lamination structure combining a silicon carbide film, a silicon carbonitride film, and a silicon nitride film with a silicon oxide film, a silicon carbooxide film (SiOC) or the like.

An interlayer insulating film7is formed on the etching stopper insulating film6. A thickness of the interlayer insulating film7is, e.g., 100 nm to 1000 nm. This thickness is a thickness necessary for the interlayer insulating film added to a thickness to be removed by a later polishing process.

The interlayer insulating film7is a low dielectric constant insulating film having a dielectric constant of, e.g., 3.0 or lower and containing, e.g., an organic material. The interlayer insulating film7is formed by one of, or a combination of CVD, plasma enhanced CVD (PE-CVD) and spin coating by using a material selected from a group consisting of organic silane having methyl group and organic siloxane having methyl group.

The other materials suitable for the spin coating method may be LKD (product name) of JSR Company, porous SiLK (product name) of The Dow Chemical Company, scalable porous silica of ULVAC Company or Mitsui Chemicals and the like. The materials suitable for CVD may be Black Diamond (product name) of AMAT Company, Aurora (product name) of ASM Company, CORAL (product name) of Novellus and the like.

Reference is made toFIG. 1B. For example, silicon oxide is deposited on the interlayer insulating film7to a thickness of 10 nm to 150 nm by physical vapor deposition (PVD) to form a hard mask film8. In addition to silicon oxide, an insulating film of silicon carbide, silicon carbooxide, silicon carbonitride, silicon nitride or the like may be used as the hard mask film8. A metal film may also be used as the hard mask film8. The hard mask film8may be a lamination film of two or more films selected from a group consisting of a silicon oxide film, a silicon carbide film, a silicon carbooxide film, a silicon carbonitride film, a silicon nitride film, and a metal film.

Considering workability of an etching process and a chemical mechanical polishing (CMP) process to be described later, it is desired to form the hard mask film8of silicon oxide (SiO2). The hard mask film8is not essential for the present invention, and it may be omitted.

Reference is made toFIG. 1C. Photoresist is coated on the hard mask film8, exposed and developed to form a resist pattern9rphaving openings of the shape corresponding to grooves10(hereinafter called dummy grooves10) in which dummy wirings are formed.

By using the resist pattern9rpas a mask, the hard mask film8is etched by reactive ion etching (RIE) to form a hard mask8m. Etching gas for the hard mask8may be, e.g., CF4.

By using the resist pattern9rpand hard mask8mas a mask, the interlayer insulating film7is etched by RIE to form dummy grooves10in the interlayer insulating film7. Etching gas for the interlayer insulating film7may be, e.g., CF4. A depth of the dummy groove10is desired to be shallower by 0 nm to 30 nm than a film thickness to be removed by a polishing process to be described later.

Reference is made toFIG. 1D. After the dummy grooves10are formed, the resist pattern9rpis removed by ashing.

Reference is made toFIG. 1E. Photoresist is coated on the hard mask8mto form a resist film11. The resist film11buries the dummy grooves10.

Reference is made toFIG. 1F. The resist film11is exposed and developed to form a resist pattern11rphaving openings of the shape corresponding to wiring grooves (trenches)12in which wirings are formed. By using the resist pattern11rpas a mask, the hard mask8mis etched by RIE to form openings of the shape corresponding to the wiring grooves12. By using the resist pattern11rpand hard mask8mas a mask, the interlayer insulating film7is etched by RIE to form openings of the shape corresponding to the wiring grooves12. Next, by changing the etching gas to a mixture gas of CF4and O2, the etching stopper insulating film6is etched to expose the contact plugs5.

Reference is made toFIG. 1G. The resist pattern11rpburying in the dummy grooves10is removed by ashing. The dummy grooves10and wiring grooves12are thus formed.

As described above, in the first embodiment the dummy grooves10are first formed and the dummy grooves10are buried with burying material, and thereafter the wiring grooves12are formed and then the burying material is removed. As a modification of the first embodiment, wiring grooves12may be formed first, and the wiring grooves12are buried with burying material, and thereafter dummy grooves10are formed and the burying material may be removed threreafter. Since the grooves of the first embodiment to be buried with the burying material are shallower than those of the modification, it becomes easy to remove the burying material.

Reference is made toFIG. 1H, for example, tantalum nitride (TaN) is deposited on the hard mask8mto a thickness of 1 nm to 30 nm by PVD (e.g., by sputtering), covering the inner surfaces of the dummy grooves10and wiring grooves12to form a conductive film13as a barrier metal film. The barrier metal film suppresses wiring material copper (Cu) to be formed on the barrier metal film from diffusing into the interlayer insulating film7. The deposition conditions of the conductive film13are, e.g., to flow N2gas and Ar gas at a flow ratio of N2:Ar=20:80 and to supply electric power of 1 kW to 40 kW by using a Ta target to react Ta and N2gas.

As the conductive film13, one or a plurality of metals or their nitride may be used being selected from a group consisting of titanium (Ti), nickel (Ni), cobalt (Co), zirconium (Zr), chrome (Cr), palladium (Pd), manganese (Mn), silver (Ag), aluminum (Al), tin (Sn), tantalum (Ta), rhenium (Re), tungsten (W), platinum (Pt), vanadium (V), ruthenium (Ru), gold (Au). The conductive film13may be formed not only by PVD, but also by one of, or a combination of CVD, PE-CVD, atomic layer deposition (ALD), plasma enhanced ALD (PE-ALD).

The conductive film13may be formed under the conditions that the conductive film13is grown at the same time when at least a portion of the conductive film13is etched, like high density plasma CVD. Attachment to the side wall is therefore improved.

For example, Cu is deposited on the conductive film13to a thickness of 1 nm to 100 nm by PVD (e.g., sputtering) to form a seed film14. The deposition conditions of the seed film14are, e.g., supply of an electric power of 1 kW to 40 kW by using a Cu target in an Ar gas atmosphere. The seed film14may be formed not only by PVD, but also by CVD, PE-CVD, ALDS, and PE-ALD. One or two or more elements may be mixed into the seed film14, being selected from a group consisting of Ti, Ni, Co, Zr, Cr, Pd, Mn, Ag, Al, Sn, Ta, Re, W, Pt, V, Ru, Au, Si, Ge, C, S, O, Cl, P, B, H, Hf, F, and N.

Reference is made toFIG. 1I. Wiring material Cu is precipitated on the seed film14by electrolytic plating using the seed film14as a feeder portion to form a plated film15and bury the dummy grooves10and wiring grooves12. The seed film14is omitted inFIG. 1Iand following drawings. A thickness of the plated film15is set thicker than a thickness of the interlayer insulating film7, e.g., 1.2 micrometers. The dummy grooves10and wiring grooves12are buried with the conductive material Cu and Cu is deposited also on the upper surface of the hard mask8mto a predetermined thickness. One or two or more elements may be mixed into the wiring material Cu, being selected from a group consisting of Ti, Ni, Co, Zr, Cr, Pd, Mn, Ag, Al, Sn, Ta, Re, W, Pt, V, Ru, Au, Si, Ge, C, S, O, Cl, P, B, H, Hf, F, and N. Instead of the plated conductive layer15, a conductive layer15deposited by CVD, PE-CVD, ALD, or PE-ALD may be used.

Reference is made toFIG. 11J. A first polishing process is performed to remove the plated film15and the seed film14above the hard mask8mby CMP. The polishing method may be, e.g., a rotary polishing method. The polishing conditions are, e.g., a revolution number of 70 rpm of a work table, a revolution number of 71 rpm of a polishing head. A polishing pressure is, e.g., 1.4000×104 Pa (2.0 psi).

Polishing is performed by supplying polishing slurry to a polishing pad having polyurethane as a base material bonded to a work table. Polishing slurry has preferably a higher polishing rate of the plated film15and seed film14than a polishing rate of the conductive film13and interlayer insulating film7.

The polishing slurry is used having the constituent components of, e.g., colloidal silica abrasive grains containing chemicals such as dispersant, oxidant, anticorrosive, and chelate. Abrasive grains are used containing one of colloidal silica, fumed silica, cerium, alumina, and silicon carbide. The oxidant may be, e.g., ammonium persulfate, or hydrogen peroxide. The anticorrosive may be, e.g., benzotriazole (BTA). The chelate may be, e.g., citric acid, malic acid, quinaldinic acid, oleic acid and the like. The polishing slurry suitable for polishing may be HS-H635 (product name) and HS-C930 (product name) of Hitachi Chemical, CMS74 series and CMS75 series of JSR Company, and the like.

When the conductive film13on the hard mask8mis exposed, the first polishing process is terminated. With the first polishing process, the plated dummy wirings15din the dummy grooves10and the plated real wirings15win the wiring grooves12are separated. The real wirings are simply called wirings.

Reference is made toFIG. 1K. A second polishing process is performed to remove the conductive film13on the hard mask8m, the hard mask8mand the upper portion of the interlayer insulating film7by CMP. It is desired that the polishing slurry to be used by the second polishing process has a higher polishing rage of the conductive film13than a polishing rate of the interlayer insulating film7.

The polishing slurry to be adopted is, e.g., a polishing slurry capable of polishing the conductive film13, dummy wirings15d, wirings15wand hard mask8mat a similar polishing rate and polishing the interlayer insulating film7at a lower polishing rate. Polishing abrasive liquid suitable for this polishing may be, e.g., acid liquid of T605-8 (product name) of Hitachi Chemical, and alkaline liquid of CMS8201/8252 (product name), CMS8501/8552 (product name) of JSR Company, and the like.

As the conductive film13on the upper surface of the hard mask8mis removed after the second polishing process starts, the dummy wirings15dand wirings15ware electrically separated. As the hard mask8mis removed, the upper surface of the interlayer insulating film7is exposed.

A portion of the interlayer insulating film7(and dummy wirings15dand wirings15w) are polished to terminate the second polishing process. A polishing amount of the interlayer insulating film7is set to, e.g., 20 nm to 100 nm. With the wiring forming method of the first embodiment, as a portion of the interlayer insulating film7is polished, the dummy wirings15dare also polished and removed. The wirings15wand barrier metal films13are left in the wiring grooves12. Wirings of the single damascene method of the first embodiment are formed in this manner.

Since the dummy wirings15dare disposed, a copper material distribution (Cu occupancy factor) in the interlayer insulating film7is averaged in the wafer plane more than without dummy wirings. Polishing rates in the wafer plane are therefore uniformized so that erosion and the like are suppressed. Disposing dummy wirings during polishing is therefore effective.

The smaller the dummy wirings15dleft on the wiring structure, the better in order to suppress a wiring delay after polishing. In the first embodiment, as a depth of the dummy grooves10formed in the interlayer insulating film7is set equal to or shallower than a polishing amount of the interlayer insulating film7, the dummy wirings15dare removed by polishing.

A portion of the dummy wirings15dmay be left in the interlayer insulating film7after polishing. The left dummy wirings15dare indicated by broken lines inFIG. 1K. Even in this case, since a volume of the left dummy wirings15dis small, the influence upon a wiring delay is small. The dummy wirings15dleft in the wiring structure after polishing are not connected to the wirings15win the same layer and wirings in the lower and upper layers, and in an electrically independent floating state.

With reference toFIGS. 2A to 2D, description will be made on an example of a plan layout of wirings and dummy wirings. Each ofFIGS. 2A to 2Dis a schematic plan view illustrating a plan layout of wirings and dummy wirings, the lower portions being schematic cross sectional views illustrating wirings and dummy wirings.FIGS. 2A to 2Dillustrate variations of a plan layout of dummy wirings. In each ofFIGS. 2A to 2D, the left side is a layout area for wirings wi, and dummy wirings du are disposed in the right area of the layout area of the wirings wi, to average the Cu occupancy rates in the in-plane more than without dummy wirings du.

InFIG. 2A, dummy wirings du of a square shape are disposed in a square matrix shape. A plan shape of the dummy wiring du is not limited to a square, but may be a rectangle or the like. The layout is not limited to a square matrix shape. It is proper that the size of each dummy wiring du has, a side of about 0.1 micron to 1.0 micron. A Cu occupancy factor in the dummy wiring layout area is preferably 20% to 40%.

InFIG. 2B, square dummy wirings du are disposed in a zigzag shape.

InFIG. 2C, rhomboid dummy wirings du are disposed in a zigzag shape.

Next, description will be made on a dual damascene wiring forming method of the second embodiment.

FIGS. 3A to 3Kare schematic cross sectional views illustrating main processes of the wiring forming method of the second embodiment.

Reference is made toFIG. 3A. First, in a manner similar to the first embodiment, processes up to a process of forming wirings15win the interlayer insulating film7by single damascene are performed. An etching stopper film16is formed on the interlayer insulating film7in a manner similar to the method of forming the etching stopper film6described in the first embodiment. An interlayer insulating film17is formed on the etching stopper film16in a manner similar to the method of forming the interlayer insulating film7described in the first embodiment. A hard mask film18is formed on the interlayer insulating film17in a manner similar to the method of forming the hard mask film8described in the first embodiment.

Reference is made toFIG. 3B. Photoresist is coated on the hard mask film18, exposed and developed to form a resist pattern19rphaving openings of a shape corresponding to dummy grooves20dand grooves20v′ where via holes are to be formed.

By using the resist pattern19rpas a mask, the hard mask film18is etched by RIE to form a hard mask18m. By using the resist pattern19rpand hard mask18mas a mask, the interlayer insulating film17is etched by RIE to form dummy grooves20dand grooves20v′ in the interlayer insulating film17.

In the second embodiment, the dummy grooves20dand grooves20v′ are formed by the same process and have the same depth. The grooves20v′ are made deeper by a wiring groove etching process to be described later to form via holes20vto be connected to wirings15win an underlying layer.

Reference is made toFIG. 3C. The resist pattern19rpis removed by ashing.

Reference is made toFIG. 3D. Photoresist is coated on the hard mask18mto form a resist film21. The resist film21buries the dummy grooves20dand grooves20v′.

Reference is made toFIG. 3E. The resist film21is exposed and developed to form a resist pattern21rphaving openings of a shape corresponding to wiring grooves. By using the resist pattern21rpas a mask, the hard mask18mis etched by RIE to form openings of a shape corresponding to wiring grooves in the hard mask18m. Grooves20v′ are disposed on the bottoms of the wiring grooves.

Reference is made toFIG. 3F. By using the resist pattern21rpand hard mask18mas a mask, the interlayer insulating film17is etched by RIE to form wiring grooves22through the interlayer insulating film17. As the wiring grooves22are formed, the grooves20v′ are etched further to form via holes20v. As the bottom of the via hole20vreaches the etching stopper film16, the etching gas is changed to etch the etching stopper film.

Reference is made toFIG. 3G. The resist pattern21rpburying the dummy grooves20dis removed by ashing. The dummy grooves20d, via holes20vand wiring grooves22are formed in the manner described above.

Reference is made toFIG. 3H. A conductive film23as a barrier metal film is formed on the hard mask18m, covering the inner surfaces of the dummy grooves20d, via holes20vand wiring grooves22, in the manner similar to the method of forming the conductive film13described in the first embodiment. A seed film24is formed on the conductive film23in the manner similar to the method of forming the seed film14described in the first embodiment.

Reference is made toFIG. 3I. A plated film25is formed on the seed film24by using conductive material, e.g., Cu, in the manner similar to the method of forming the plated film15described in the first embodiment, to bury the dummy grooves20d, via holes20vand wiring grooves22. The conductive material is buried in the dummy grooves20d, via holes20vand wiring grooves22, and deposited also on the hard mask18m.

Reference is made toFIG. 33. The plated film25above the hard mask18mand the seed film24are removed by CMP in the manner similar to the first polishing process described in the first embodiment to expose the conductive film23on the hard mask18m.

Reference is made toFIG. 3K. The conductive film23on the hard mask18m, the hard mask18mand an upper portion of the interlayer insulating film17are removed by CMP in the manner similar to the second polishing process described in the first embodiment. The interlayer insulating film17, dummy wirings25dand wirings25ware polished to form vias25vin the via holes20vand wirings25win the wiring grooves22. The barrier metal film23is sandwiched between the interlayer insulating film17and the conductor including the via25vand wiring25w. The dual damascene wirings of the second embodiment are formed in the manner described above. The dummy wirings25dare formed shallower than the wirings25w.

Next, description will be made on a dual damascene wiring forming method of the third embodiment different from the second embodiment. In the second embodiment, the dummy grooves20dand the grooves20v′ corresponding to the via holes were formed at the same time as illustrated inFIG. 3C. In the third embodiment, the dummy grooves, via holes and wiring grooves are formed by independent processes. It is therefore possible to form the dummy grooves to a desired depth shallower than the wiring grooves.FIGS. 4A to 4Iare schematic cross sectional views illustrating main processes of the wiring forming method of the third embodiment.

Reference is made toFIG. 4A. Constituent elements up to the interlayer insulating film17are formed in the manner similar to the second embodiment. A hard mask film is formed on the interlayer insulating film17in the manner similar to the method of forming the hard mask film18described in the second embodiment. Photoresist is coated on the hard mask film, exposed and developed to form a resist pattern29rphaving openings of a shape corresponding to dummy grooves30.

By using the resist pattern29rpas a mask, the hard mask film is etched by RIE to form a hard mask28m. By using the resist pattern29rpand hard mask28mas a mask, the interlayer insulating film17is etched by RIE to form dummy grooves30in the interlayer insulating film17.

Reference is made toFIG. 4B. The resist pattern29rpis removed by ashing.

Reference is made toFIG. 4C. Photoresist is coated on the hard mask28mto form a resist film31. The resist film31buries the dummy grooves30.

Reference is made toFIG. 4D. The resist film31is exposed and developed to form a resist pattern31rphaving openings of a shape corresponding to via holes32v. By using the resist pattern31rpas a mask, the hard mask28mis etched by RIE to form openings of a shape corresponding to the via holes32v.

By using the resist pattern31rpand hard mask28mas a mask, the interlayer insulating film17is etched by RIE to form via holes32vthrough the interlayer insulating film17. When the bottom of the via hole32vreaches the etching stopper film16, the etching gas is changed to etch the etching stopper film16to expose wirings15win the lower layer.

Reference is made toFIG. 4E. The resist pattern31rpburying the dummy grooves is removed by ashing.

Reference is made toFIG. 4F. Photoresist is coated on the hard mask28mto form a resist film33. The resist film33buries the dummy grooves30and via holes32v.

Reference is made toFIG. 4G. The resist film33is exposed and developed to form a resist pattern33rphaving openings of a shape corresponding to wiring grooves32w. By using the resist pattern33rpas a mask, the hard mask28mis etched by RIE to form openings of a shape corresponding to the wiring grooves32w. By using the resist pattern33rpand hard mask28mas a mask, the interlayer insulating film17is etched by RIE to form wiring grooves32win the interlayer insulating film17. The resist film33as the burying material is left in the via holes32vunder the bottoms of the wiring grooves32w.

Reference is made toFIG. 4H. The resist pattern33rpburying the dummy grooves30and the resist films33left in the via holes32vare removed by ashing. The dummy grooves30, via holes32vand wiring grooves32W of the third embodiment are formed in the manner described above.

Similar to the second embodiment, a conductive film34as the barrier metal film is thereafter formed on the hard mask28m, covering the inner surfaces of the dummy grooves30, via holes32vand wiring grooves32w, a Cu seed film is formed on the conductive film34, and Cu is deposited on the Cu seed film by a plating method to form a plated film35(Refer toFIG. 3I).

Further, similar to the second embodiment, the plated film35on the hard mask28mand the seed film are removed by CMP (Refer toFIG. 3J).

Reference is made toFIG. 4I, further, similar to the second embodiment, the conductive film34on the hard mask28m, the hard mask28mand an upper portion of the interlayer insulating film17are removed by CMP. Vias35vin the via holes32vand wirings35win the wiring grooves32W are therefore formed. The barrier metal film34is sandwiched between the interlayer insulating film17and the conductor including the via35vand wiring35w. The dual damascene wirings of the third embodiment are formed in the manner described above.

In the third embodiment, as illustrated inFIGS. 4B and 4D, it is possible to independently form the dummy grooves30vand via holes32v.FIG. 4Iillustrates an example wherein all dummy wirings are removed. Also in the third embodiment, a portion of the dummy wirings35dmay be left in the interlayer insulating film17(Refer toFIG. 3K). Also in this case, since a volume of the left dummy wirings35dis small, the influence upon a wiring delay is small.

In the third embodiment, the dummy grooves were formed first, and then the via holes32vand wiring grooves32wwere formed. As a modification of the third embodiment, the via holes32vand wiring grooves32wmay be formed first, and then the dummy grooves30may be formed.

In the third embodiment, although the via holes32vwere formed first, and then wiring grooves32wwere formed, the wiring grooves32wmay be formed first, and then the via holes32vmay be formed. In the above modification of the third embodiment, the via holes32vmay be formed first, and then the wiring grooves32wmay be formed, or the wiring grooves32wmay be formed first, and then the via holes32vmay be formed.

As a process sequence modification example, a process of forming the dummy grooves may be executed between a process of forming the via holes32vand a process of forming the wiring grooves32wor between a process of forming the wiring grooves32W and a process of forming the via holes32v.

In the third embodiment, the dummy grooves30are buried by the process illustrated inFIG. 4Cbefore the via holes32vare formed and by the process illustrated inFIG. 4Fbefore the wiring grooves32ware formed. The recess formed first is buried the largest number of times and has the largest number of processes of removing the burying material. From the viewpoint of facilitating to remove the burying material, the shallowest dummy grooves30are preferably formed first. If wide and deep wiring grooves are to be buried, the amount of the burying material becomes largest and the burying material becomes hard to be removed. In order not to bury the wiring grooves32w, the wiring grooves32ware preferably formed last.

Also in forming dual damascene wirings of the second and third embodiments, similar to forming single damascene wirings of the first embodiment, the dummy wirings25dand35duniformize the polishing rates in the in-plane of the interlayer insulating film17having a low dielectric constant, and erosion and the like are suppressed. Since the dummy wirings25dand35dare formed shallower than at least the wirings25wand35w, a volume of dummy wirings left after polishing is able to be made small and a wiring delay to be caused by the dummy wirings is suppressed. The flexibility of dummy wiring layout is improved.

Even if the dummy wirings25dand35dof dual damascene of the second and third embodiments are left on the wiring structure after polishing, the dummy wirings are not connected to the wirings25wand35wof the same layer and the wirings of the lower and upper layers, and are in an electrically independent floating state, similar to the dummy wirings of single damascene of the first embodiment.

As described in the first to third embodiments and corresponding modifications, erosion and the like are able to be suppressed and a wiring delay to be caused by left dummy wirings is able to be suppressed, by forming dummy wirings shallower than at least single or dual damascene wirings. The dummy grooves are shallower than the wiring grooves. A volume of the conductive material in the dummy grooves is easy to be made small.