MEMORY DEVICE AND MANUFACTURING THEREOF

Embodiments of the present disclosure relates to an integrated circuit including an array of memory cells connected to word lines and bit lines located on opposite sides of the memory cells. The memory cell may include gate all around transistors. A memory circuit according to the present disclosure also includes edge cells having word line tap structures configured to connect front side word lines with back side word lines. Some embodiments of the present disclosure provide an IC chip having memory cells with power rail on the front side and logic cells with power rail on the back side.

BACKGROUND

The semiconductor integrated circuit (IC) industry has produced a wide variety of digital devices to address issues in a number of different areas. Some of these digital devices are electrically coupled to static random-access memory (SRAM) devices for the storage of digital data. As ICs have become smaller and more complex, for example, by introducing gate all around (GAA) transistors in SRAM, the effects of cross talk and wiring resistance further affect IC performance. For example, routing conductors, such as Word lines and Bit lines in a memory circuit, would generate RC delay as well as coupling noise. The RC delay and coupling noises of the routing conductors may slow down the cell speed and/or limit scaling ratio.

Therefore, there is a need to lower RC loading in embedded memory and SOC (system-on-chip) IC products to meet speed requirements while scaling down.

DETAILED DESCRIPTION

The foregoing broadly outlines some aspects of embodiments described in this disclosure. While some embodiments described herein are described in the context of nanosheet channel FETs, implementations of some aspects of the present disclosure may be used in other processes and/or in other devices, such as planar FETs, Fin-FETs, GAA (Gate All Around) FETs, such as Horizontal Gate All Around (HGAA) FETs, and Vertical Gate All Around (VGAA) FETs, and other suitable devices. A person having ordinary skill in the art will readily understand other modifications that may be made are contemplated within the scope of this disclosure. In addition, although method embodiments may be described in a particular order, various other method embodiments may be performed in any logical order and may include fewer or more steps than what is described herein. In the present disclosure, a source/drain refers to a source and/or a drain. A source and a drain are interchangeably used.

Embodiments of the present disclosure relates to an integrated circuit including an array of memory cells connected to word lines and bit lines formed opposite sides of the memory cells. A memory circuit according to the present disclosure also includes edge cells having word line tap structures configured to connect front side word lines with back side word lines. Some embodiments of the present disclosure provide an IC chip having memory cells with power rail on the front side and logic cells with power rail on the back side.

FIG. 1is a simplified diagram of an integrated circuit10in accordance with some embodiments of the present disclosure. The integrated circuit10includes a memory circuit20and a logic circuit40. In some embodiments, the memory circuit20and logic circuit40include GAA transistors.

The memory circuit20may include one or more memory array30of multiple memory cells arranged in rows and columns. In some embodiments, the memory cells in the memory array30may have the same circuit configuration and the same semiconductor structure. In some embodiments, the logic circuit40may be the controller for accessing the memory circuit20. In some embodiments, the logic circuit40includes circuits configured to perform a specific function or operation according to data stored in the memory circuit20. The logic circuit40includes multiple logic cells50. In some embodiments, the logic cell50may be a standard cell (STD cell), e.g., inverter (INV), AND, OR, NAND, NOR, Flip-Flop, SCAN and so on. In some embodiments, the logic cells50corresponding to the same function or operation may have the same circuit configuration with different semiconductor structures for providing various threshold voltages (Vth or Vt). In some embodiments, the integrated circuit10may be a system on chip (SOC) circuit with embedded memory circuits.

FIG. 2Aschematically illustrates the memory array30the embodiments of the present disclosure. In some embodiments, the memory array30is a static random-access memory (“SRAM”) array including a plurality of bit cells102. The bit cells102are arranged in a number, n, of rows and a number, m, of columns. Each bit cell102is coupled to a word line, WL (one of WL1to WLn), that extends horizontally across the memory array30(i.e., in an x-direction) and two complementary bit lines BL (one of BL1to BLm) and its complement BLB (one of BLB1to BLBm) that extend vertically across the memory array30(i.e., in a y-direction).

FIG. 2Bis a schematic diagram of the bit cell102according to embodiments of the present disclosure. The bit cell102is a six-transistor (“6T”) SRAM cell. Each bit cell102includes a latch108formed by a pair of cross coupled inverters110,112. The inverter110includes a PMOS (p-channel metal-oxide semiconductor) transistor114and a NMOS (n-channel metal-oxide semiconductor) transistor118. The PMOS transistor114includes a source coupled to a high-voltage source, VDD at a node1401, and a drain coupled to a node116. The node116serves as the output of the inverter110. The NMOS transistor118of the inverter110has a source coupled to low-voltage source VSS at a node1381, and a drain coupled to the node116. Gates of the transistors114and118are coupled together at a node120. The node120serves as the input of the inverter110and the output of the inverter112. The inverter112includes a PMOS transistor122and a NMOS transistor124. The PMOS transistor122has a source coupled to VDD at a node1402, a gate coupled to the node116, and a drain coupled to the node120. The NMOS transistor124has a source coupled to VSS at a node1382, a drain coupled to the node120, and a gate coupled to the node116. In some embodiment, the nodes1381,1382are larger in dimension than the nodes132,136,1401,1402.

The bit cell102also includes a pair of pass transistors126,128. In some embodiments, the pass transistors126,128are NMOS transistors, although one skilled in the art will understand that the pass transistors126,128may be implemented as PMOS transistors. The pass transistor126has a gate coupled to the word line WL at a node130, a source coupled to the node116, and a drain coupled to the bit line BL at a node132. The transistor128has a gate coupled to the word line WL at a node134, a source coupled to the node116, and a drain coupled to the complementary bit line BLB at a node136.

The transistors of the bit cell102may be formed in one or more doped regions of a semiconductor substrate using various technologies. In some embodiments, the transistors of the bit cell102may be GAA FETs, such as HGAA-FETs, VGAA FETs, and other suitable devices. Alternatively, the transistors of the bit cell102may be formed in any suitable transistors, such as bulk planar metal oxide field effect transistors (“MOSFETs”), bulk Fin-FETs having one or more fins or fingers, semiconductor on insulator (“SOI”) planar MOSFETs, SOI Fin-FETs having one or more fins or fingers, or combinations thereof. The gates of the transistors in the bit cell102may include a polysilicon (“poly”)/silicon oxynitride (“SiON”) structure, a high-k/metal gate structure, or combinations thereof. Examples of the semiconductor substrate include, but are not limited to, bulk silicon, silicon-phosphorus (“SiP”), silicon-germanium (“SiGe”), silicon-carbide (“SiC”), germanium (“Ge”), silicon-on-insulator silicon (“SOI-Si”), silicon-on-insulator germanium (“SOI-Ge”), or combinations thereof.

FIGS. 3A-3Lare various views of the bit cell102according to embodiments of the present disclosure.FIG. 3Ais a schematic perspective sectional view of the bit cell102.FIGS. 3B-3Gare schematic layouts of various layers of the bit cell102. As shown inFIG. 3A, which is a perspective view of the bit cell102with a section along the line Xcut-0ofFIG. 3B, the bit cell102may be formed on and in a semiconductor substrate. Dotted lines indicate a cell boundary102cbof the bit cell102. The bit cell102may be a 6-transistor SRAM cell as shown inFIG. 2B. For example, the transistors114,118,122,124,126,128of the bit cell102.

The transistors114,118,122,124,126,128may be formed on a semiconductor substrate during FEOL (front end of line) processes and embedded in a STI (shallow trench isolation) layer206and an ILD (interlayer dielectric layer IL) layer208(collectively as a device layer). As shown inFIG. 3A, conductive features connected to gate electrodes and/or source/drain features of the transistors may be formed on the front side of the device layer in MEOL (middle end of line) processes and embedded in an ILD layer210.

The bit cell102includes front side interconnect features in a front side IMD (inter-metal dielectric) layer212. The front side IMD layer212is formed over the ILD layer210. The front side IMD layer212may include one or more dielectric layers of dielectric materials with layers of conductive lines and vias embedded therein. One or more conductive layers may be formed in the front side IMD layer212. Each conductive layer defines a plane in the x-direction and y-direction and may be separated from each other by dielectric material in the front side IMD layer212. As will be understood by one skilled in the art, vias extend in the vertical direction, i.e., z-direction, to provide interconnects between conductive layers in the front side IMD layer212.

InFIG. 3A, a first conductive layer (or M1)218and a second conductive layer (or M2)220are show embedded the front side IMD layer212. Conductive vias219are formed to connect conductive features in the first conductive layer218and conductive features in the second conductive layer220. Additional conductive layers may be formed over the second conductive layer220in the front side IMD layer212. In some embodiments, the first conductive layer (or M1)218includes bit lines, and conductive features for connecting the bit cell102to the low-voltage power source VSS and the high-voltage power source VDD. The second conductive layer (or M2)220includes conductive features to form a power mesh to the low-voltage power source VSS.

The bit cell102may include a back side dielectric layer214having back side gate contact features215formed therein. The back side dielectric layer214may be formed under the transistors and the STI layer206. The bit cell102further includes back side interconnect features in a back side IMD (inter-metal dielectric) layer216. In some embodiments, the back side IMD layer216may be formed under the back side dielectric layer214. The back side IMD layer216may include one or more dielectric layers of dielectric materials with layers of conductive lines and vias embedded therein. One or more conductive layers may be formed in the back side IMD layer216. Each conductive layer defines a plane in the x- and y-direction and may be separated from each other by dielectric material in the back side IMD layer216. As will be understood by one skilled in the art, vias extend in the vertical direction, i.e., z-direction, to provide interconnects between conductive layers in the back side IMD layer216. InFIG. 3A, a first conductive layer (or BM1)222and an optional second conductive layer (or BM2)224are show embedded the back side IMD layer216. Conductive vias (not shown) are formed to connect conductive features in the first conductive layer222and conductive features in the second conductive layer224. Additional conductive layers may be formed in the back side IMD layer216. In some embodiments, the first conductive layer (or BM1)222includes a word line. The second conductive layer (or BM2)224includes a second word line electrically connected to the word line in the first conductive layer (or BM1)222.

FIG. 3Bis a schematic layout of the transistors in the bit cell102ofFIG. 3Aaccording to one embodiment of the present disclosure. The bit cell102is formed within the cell boundary102cbhaving a length102bpthat extends in the x-direction a width102wpthat extends in the y-direction. In some embodiments, the bit cell102is a thin style cell in rectangular shape having the length102pblonger than the width102wp. In some embodiments, the ratio the length102pbto the width102wpis greater than 2.

In some embodiments, as show inFIGS. 3A-3L, the bit lines in a memory array, such as the memory array30, are arranged along the y-direction, the length102bprepresents the bit line pitch of the memory array; and the word lines of the memory array are arranged along the x-direction, the width102wprepresents the word line pitch of the memory array. Arranging the bit lines along the short edge of a rectangular bit cell is frequently used for embedded SRAM circuits because it is lithograph friendly, for example, fin structure layout, sacrificial gate structure patterning, and contact feature patterning, as well as bit line for speed improvement. As IC scaling down, each word line is connected to an increasing number of bit cells resulting in longer word lines and increased conductor resistance in the word lines. By arranging the word lines and bit lines on opposite sides of the bit cell102, embodiments of the present disclosure enable wider word lines, thus reducing word line resistance.

Transistors of the bit cell102are formed over a pair of p-wells226pand a n-well226npositioned between the pair of p-well226p. Fin structures228a,228b,228c,228dare formed along the y-direction. Gate structures230a,230bare formed along the x-direction over the fin structures228a,228b,228c,228d. Each of the fin structures228a,228b,228c,228dincludes two or more nano-sheet semiconductor channels228.FIG. 3Bschematically illustrates positions of the fin structures228a,228b,228c,228dprior to formation of source/drain features. During fabrication, portions of the fin structures228a,228b,228c,228dnot covered by the gate structures230a,230bare etched back, and epitaxial source/drain structures are then formed on both sides of the gate structures230a,230bto form the transistors.

The fin structures228a,228dare formed over the two p-wells226prespectively. The fin structures228a,228dmay have a width w1along the x-direction. The fin structures228b,228care formed over the n-well226n. The fin structure228b,228cmay have a width w2along the x-direction. In some embodiments, the width w1is greater than the width w2. In some embodiments, in an array of bit cells102, the fin structures228a,228dare formed continuously along the y-direction, and the fin structures228b,228care formed in sections in each bit cell102. The pull-down transistor118and pass transistor126are n-type transistors formed over one p-well226p, and the pull-down transistor124and pass transistor128are n-type transistors formed over the other p-well226p. The pull-up transistors114and122are p-type transistors formed over the n-well226n. Gates of the pull-down transistor118and the pull-up transistor114are connected. Gates of the pull-down transistor124and the pull-up transistor122are connected.

As shown inFIG. 3A, the transistors in the bit cell102are GAA transistors having two or more vertically stacked semiconductor channels228. The gate structure230a,230bincludes a gate dielectric layer231and a gate electrode layer232formed around each of two or more semiconductor channels228. The gate structure230ais formed over the pull-down transistor118, the pull-up transistor114, and the pass transistor128, and is cut into two portions by a gate isolator236between the pull-down transistor118and the pass transistor128. Similarly, the gate structure230bis formed over the pass transistor126, the pull-up transistor122, and the pull-down transistor124, and is cut into two portions by another gate isolator236between the pass transistor126and the pull-up transistor122.

FIG. 3Cis a schematic layout of the source/drain contact features and gate contact features in the bit cell102ofFIG. 3Aaccording to one embodiment of the present disclosure. Source/drain contact features114s,114d,118s,118d,122s,122d,124s,124d,126s,126d,128s,128dare formed over on source/drain features of the transistors114,118,122,124,126,128. In some embodiments, the source/drain contact features126s,118d,114dare connected to one another, and the source/drain contact features122d,124d,128sare connected to one another. The node116connects the gates of the pull-down transistor124and the pull-up transistor122to the source/drain contact features126s,118d,114d. The node120connects the gates of the pull-down transistor118and the pull-up transistor114to the source/drain contact features122d,124d,128s.

FIG. 3Dis a schematic layout of the first conductive layer218formed in the front side IMD layer212of the bit cell102ofFIG. 3A. As discussed above, the first conductive layer (or M1)218includes bit lines and conductive features for connecting the bit cell102to the low-voltage power source VSS and the high-voltage power source VDD.

The conductive layer218includes conductive routing lines218vss1,218b1,218vdd,218b1b, and218vss2arranged along the y-direction. The conductive routing lines218vss1,218b1,218cvdd,218b1b, and218vss2are substantially parallel to one another. The conductive routing lines218vss1,218vss2are configured to connect to a power mesh to the low-voltage source VSS. The conductive routing line218vddis to be connected to the high-voltage source VDD. The conductive routing line218b1is the bit line BL, and the conductive routing line218b1bis the bit line BLB.

As shown inFIG. 3D, the conductive routing line218vddto be connected to the high-voltage source VDD is positioned near the center of the bit cell102. The conductive routing lines218vss1,218vss2may be disposed at the boundary102cpof the bit cell102. The conductive routing line218bl/the bit line BL is disposed between the low-voltage power supply line/conductive routing lines218vss1and the high-voltage power supply line/conductive routing line218vdd. The conductive routing line218blb/the complementary bit line BLB is disposed between the low-voltage power supply line/conductive routing line218vss2and the high-voltage power supply line/conductive routing line218vdd. This arrangement allows the high voltage power supply line/conductive routing line218vddto separate bit lines BL and BLB.

The nodes132,136,1381,1382,1401,1402inFIG. 1Bmay be implemented in form of conductive vias to connect the conductive layer218and the source/drain contact features114s,118s,122s,124s,126d,128d. As shown inFIG. 3D, the node132couples the source/drain contact feature126dof the pass transistor126to the bit line BL, and the node136couples the source/drain contact feature128dof the pass transistor128to the complementary bit line BLB. The nodes1381,1382couple the pull-down transistors118and124to the low-voltage source VSS through the conductive routing lines218vss1,218vss2respectively. The nodes1401,1402couple the pull-up transistors114and122to the high-voltage source VDD through the conductive routing line218vdd.

FIG. 3Eis a schematic layout of the second conductive layer220formed in the front side IMD layer212of the bit cell102ofFIG. 3A. As discussed above, the second conductive layer (or M2)220includes conductive features to form a power mesh to the low-voltage power source VSS. The second conductive layer220may include a conductive routing line220vssto be connected to the low-voltage source VSS. In some embodiments, the conductive line220vssmay be formed along the x-direction or perpendicular to the conductive routing lines218vss1and218vss2in the first conductive layer218. Conductive vias2191,2192are used to connect the conductive routing lines218vss1and218vss2to the conductive routing line220vss. In some embodiments, additional conductive layers may be formed over the second conductive layer220as a power mesh to the low-voltage power source VSS.

FIG. 3Fis a schematic layout of the first conductive layer222formed in the back side IMD layer216of the bit cell102ofFIG. 3A. As shown inFIG. 3F, the first conductive layer (or BM1)222includes a conductive line222wlextending across the bit cell102along the x-direction. The conductive line222wlis a word line. The conductive line222wlis connected to the gate of the pass transistor126at the node130. The conductive line222wlis connected to the gate of the pass transistor128at the node134. The nodes130,134may be implemented by conductive vias215formed in the backside dielectric layer214. By positioning the word line on the back side of the transistor layer, the conductive line222wl/word line may have a width along the y-direction that extends across both of the gate structures230a,230b, thus, reducing resistance of the word line.

FIG. 3Gis a schematic layout of the second conductive layer224formed in the back side IMD layer216of the bit cell102ofFIG. 3A. The second conductive layer (or BM2)224includes a second word line electrically connected to the word line in the first conductive layer (or BM1)222. The second conductive layer (or BM2)224includes a conductive line224wlextending across the bit cell102along the x-direction. The conductive line224wlmay be connected to the conductive line222wlby one or more conductive vias223. The conductive line222wland the conductive layer224are parallelly connected, thus, further, reducing resistance of the word line. In some embodiments, the second conductive layer224may be omitted. In other embodiments, additional back side conductive layer may be formed to include more conductive lines to further reduce the resistance of the word line.

FIGS. 3H-3Lare various sectional views of the bit cell102showing detailed structures.FIG. 3His a sectional view of the bit cell102along the line of xcut-3inFIG. 3B. Particularly,FIG. 3His a sectional view of between the gate structures230a,230band parallel to the gate structures230a,230b.FIG. 3Iis a sectional view of the bit cell102along the line of xcut-2inFIG. 3B. Particularly,FIG. 3Iis a sectional view along the gate structure230a.FIG. 3Jis a sectional view of the bit cell102along the line of Ycut-4inFIG. 3B. Particularly,FIG. 3Jis a sectional view along the fin structure228dacross the gate structures230a,230b.FIG. 3Kis a sectional view of the bit cell102along the line of Ycut-5inFIG. 3B. Particularly,FIG. 3Kis a sectional view along the fin structure228cacross the gate structures230a,230b.FIG. 3Lis a sectional view of the bit cell102along the line of xcut-1inFIG. 3B. Particularly,FIG. 3Lis a sectional view along the long edge of the cell boundary102cb.

The sectional views inFIGS. 3H-3Lexpand over the cell boundary102cbof the bit cell102to show a portion of the neighboring bit cells102in a memory array. In some embodiments, the neighboring bit cells102are mirror images of each other. The conductive routing lines218vss1,218vss2are formed on two short edges of the cell boundary102cband shared by two neighboring bit cells102. The conductive routing line220vssis formed on one long edge of the cell boundary102cband shared by the bit cells102on both sides of the cell boundary102cb.

As shown inFIGS. 3H-3L, each of the transistors114,118,122,124,126,128includes two epitaxial source/drain features114ep,118ep,122ep,124ep,126ep,128epformed on two ends of two or more semiconductor channels228. The gate dielectric layer231and the gate electrode layer232are formed around each of the semiconductor channels228. Sidewall spacers242and inner spacers244are formed between the epitaxial source/drain features114ep,118ep,122ep,124ep,126ep,128epand the gate dielectric layer231. A self-aligned contact layer234is formed over the gate electrode layer232to provide electrical isolation to the gate electrode layer232and alignment for subsequent gate contact formation.

The ILD layer208is formed over the epitaxial source/drain features114ep,118ep,122ep,124ep,126ep,128epto provide electrical isolation. A contact etch stop layer (CESL), not shown, is typically formed between the epitaxial source/drain features114ep,118ep,122ep,124ep,126ep,128epand the ILD layer208. The contact features114s,114d,118s,118d,122s,122d,124s,124d,126s,126d,128s,128dare formed in the ILD layer208on a front side of the epitaxial source/drain features114ep,118ep,122ep,124ep,126ep,128epin each of the transistors114,118,122,124,126,128. In some embodiments, a silicide layer240is formed between the epitaxial source/drain features114ep,118ep,122ep,124ep,126ep,128epand the corresponding contact features.

A front gate contact246(also referred to as butt contact, corresponding to the node116) connects the gates of the pull-down transistor124and the pull-up transistor122to the source/drain contact features126s,118d,114d. A front gate contact248(also referred to as butt contact, corresponding to the node120) connects the gates of the pull-down transistor118and the pull-up transistor114to the source/drain contact features122d,124d,128s.

The ILD layer210is formed over the ILD layer208, the front gate contact features246,248, and the source/drain contact features114s,114d,118s,118d,122s,122d,124s,124d,126s,126d,128s,128d. Conductive vias250are formed in the ILD layer210to selectively connect the source/drain contact features114s,114d,118s,118d,122s,122d,124s,124d,126s,126d,128s,128dto the conductive routing lines in the first conductive layer218embedded in the front side IMD layer212. Particularly, one of the conductive via250(corresponding to the node132) connects the source/drain contact feature126dto the conductive routing line218b1(corresponding to BL); one of the conductive via250(corresponding to the node136) connects the source/drain contact feature128dto the conductive routing line218b1b(corresponding to BLB). Two conductive vias250(corresponding to the nodes1381,1382) connect the pull-down transistors118and124to the low-voltage source VSS through the conductive routing lines218vss1,218vss2respectively. Two conductive vias250(corresponding to the nodes1401,1402) couple the pull-up transistors114and122to the high-voltage source VDD through the conductive routing line218vdd.

The conductive routing line220vss, as part of the VSS power mesh, is form in the second conductive layer220in the front side IMD layer212. In some embodiments, the conductive routing line220vssis formed along the x-direction, i.e. along a direction perpendicularly to the conductive routing lines218vss1and218vss2in the first conductive layer218. In some embodiments, the conductive routing line220vssis formed on the cell boundary102cand shared by two neighboring bit cells102. The conductive vias2191,2192are formed in the front side IMD layer212between the first conductive layer218and the second conductive layer220to connect the conductive routing lines218vss1and218vss2to the conductive routing line220vss.

The back side dielectric layer214may be formed by replacing the substrate on which the fin structures228a,228b,228c,228dand the epitaxial source/drain features114ep,118ep,122ep,124ep,126ep,128epare formed. The backside dielectric layer214is contact with a back side of the epitaxial source/drain features114ep,118ep,122ep,124ep,126ep,128ep, the STI layer206, the gate dielectric layer231, the inner spacers244, and the gate spacer242. The back side gate contact features215may be formed in an opening through the back side dielectric layer214and the gate dielectric layer231to connect the gate electrode layer232.

The back side IMD layer216is formed over the back side dielectric layer214. The first conductive layer (or BM1)222including the conductive line222wl, which functions as the word line, is formed in the back side IMD layer216. The back side gate contact features215(corresponding to the nodes130and134) connects the gate electrode layer232to the conductive line222wl. As shown inFIGS. 3F and 3I, the back side gate contact features215may be formed on the short edge of the cell boundary102cp.

The conductive line222wlextends across the bit cell102along the x-direction. The conductive line222wlmay be positioned below the gate structures230a,230b. The conductive line222wlmay have a width w3along the y-direction. In some embodiments, a ratio of the w3over the word pitch or the cell width102wpin a range between about 40% and 80%. A ratio lower than 40% may not be wide enough to have enough overlapping with the gate structures230a,230bestablish connection through the contact features215, or not enough resistance reducing benefit. A ratio higher than 80% may not have enough spacing for dielectric material between neighboring word lines to conform with design rules.

Optionally, the second conductive layer (or BM2)224including the conductive line224wl, which also functions as the word line, is formed over the first conductive layer222in the back side IMD layer216. The conductive via223is formed between the first and second conductive layers222,224to connect the conductive lines222wland224wl. In some embodiments, the conductive via223may be formed near the central portion of the bit cell102. The conductive line224wlmay have a width w4along the y-direction. In some embodiments, a ratio of the w4over the word pitch or the cell width102wpin a range between about 40% and 80%. A ratio lower than 40% may not be wide enough to have enough resistance reducing benefit. A ratio higher than 80% may not have enough spacing for dielectric material between neighboring word lines to conform with design rules.

FIG. 4is a block diagram of a memory circuit400according to embodiments of the present disclosure. In some embodiments, the memory circuit400may be used in place of the memory circuit20in the integrated circuit10ofFIG. 1. The memory circuit400may include a memory cell array402, a word line decoder404, a multiplexer406, and a write driver408. In some embodiments, the memory cell array402, the word line decoder404, the multiplexer406, and the write driver408are formed on the same substrate. The word line decoder404, the multiplexer406, and the write driver408are periphery circuit to the memory cell array402and configured to facilitate read and write operation to each bit cell102in the memory cell array402. In some embodiments, the word line decoder404, the multiplexer406, and the write driver408may be logic circuit or devices including components such as inverters, NAND gates, NOR gates, flip-flops, or combinations thereof.

The memory cell array402includes an array of bit cells, such as the bit cell102described above. The memory cell array402may include m rows by n columns of the bit cells, where m is an integer corresponding to the number of rows and n is an integer corresponding to the number of columns. The memory cell array402further includes two rows of strap cells418positioned above the first row and below the last row of the bit cells102. The memory cell array402further includes two column of edge cells421,422positioned on two ends of each row of the bit cells102.

The bit cells102in each column1to n share one bit line4101to410n(collectively410), one bit line bar4121to412n(collectively412), one low-voltage power line4141to414n(collectively414), and one high-voltage power line4161to416n(collectively416). The bit cells102in each row1to m share one word line4201to420m(collectively420).

The strap cells418may be configured to supply bulk terminal voltages, and the low-voltage power lines414and the high-voltage power lines416are connected to the strap cells418. The bit lines410and bit line bars412are connected to the multiplexer406, which is further connected to the write driver408to read and write the value in each bit cell102.

The word lines420extend across each row of the bit cells102from the edge cells421to the edge cells422. In some embodiments, the edge cells422may include a word line signal line426(4261to426m) to connect to the word line decoder404. As disclosed above, the bit line and word line of the bit cell102are arranged on opposite sides of the transistors. In the example above, the bit word line is positioned on a backside of the bit cell102while the bit lines and the power supply lines are positioned on the front of the bit cell102. In some embodiments, the word line decoder404are standard logic cells having signal lines formed located on the front side of the substrate, the word line signal lines426are located on the front side of the substrate. Each edge cell422may include a word line tap structure424configured to connect the word lines420located on the back side of the substrate to the word line signal lines426located on the front side of the substrate.

FIGS. 5A and 5Bare schematical sectional views of the edge cell422according to embodiments of the present disclosure.FIG. 5Ais a sectional view of the edge cell422along the line5A-5A inFIG. 4.FIG. 5Bis a sectional view of the edge cell422along the line5B-5B inFIG. 4. In some embodiments, the word line signal line426is formed in the second conductive layer220in the front side IMD layer212. The edge cell422includes the word line tap structure424electrically connecting the word line420on the back side to the word line signal line426on the front side. The word line tap structure424may include multiple conductors formed embedded in various layers. The components in the word line tap structure424may be formed in multiple operations during fabrication the bit cell102in the corresponding layers.

In some embodiments, the word line tap structure424includes a conductive tap via430extending from the back side conductive layer222, wherein the word line420is formed in the bit cell102, through the back side dielectric layer214and the STI layer206. The conductive tap via430is connected to a transistor layer conductor432formed through the ILD layer208. The transistor layer conductor432is connected to a conductive via434is formed through the ILD layer210. A word line contact plate436is formed in the first conductive layer218in the front side IMD layer212. The word line contact plate436may be a section of conductive line parallel to the bit lines. A contact via438is formed between the word line contact plate436and the word line signal line426.

FIG. 5Cis a schematic sectional view of an edge cell422aaccording to another embodiment of the present disclosure. The edge cell422aincludes a word line tap structure424a. The word line tap structure424ais similar to the word line tap structure422ofFIG. 5Aexcept that the conductive tap via430extends through the back side dielectric layer214, the STI layer206, and part the ILD layer208.

FIG. 5Dis a schematic sectional view of an edge cell422baccording to another embodiment of the present disclosure. The edge cell422bincludes a word line tap structure424b. The word line tap structure424bis similar to the word line tap structure422ofFIG. 5Aexcept that the conductive tap via430extends through the back side dielectric layer214, the STI layer206, and the entire ILD layer208.

FIG. 5Eis a schematic sectional view of an edge cell422caccording to another embodiment of the present disclosure. The edge cell422cincludes a word line tap structure424c. The word line tap structure424cis similar to the word line tap structure422ofFIG. 5Aexcept that the conductive tap via430extends through the back side dielectric layer214, the STI layer206, the ILD layer208, and a portion of the front side IMD layer212.

Even though the word line signal line426is shown to be in the second conductive layer220in the front side IMD layer212, the word line426may be embedded other layers within the front side IMD layer212.

Referring back toFIG. 1, the integrated circuit10according to the represent disclosure may include the memory circuit20and logic circuit40include GAA transistors. In some embodiments, the logic circuit40may include standard logic cells. Similarly, the peripheral circuits, such as word line decoders, multiplexers, write drivers, of the memory circuit20may include standard logic cells. In some embodiments, the integrated circuit10according of present disclosure includes one or more standard cells having a back side power rail.

FIGS. 6A-6Dare various views of a standard logic cell600according to embodiments of the present disclosure.FIG. 6Ais a schematic front side routing layout of the standard logic cell600according to one embodiment of the present disclosure.FIG. 6Bis a schematic back side routing layout of the standard logic cell600.FIG. 6Cis a schematic sectional view of the standard logic cell600along the6C-6C line inFIG. 6A.FIG. 6Dis a schematic sectional view of the standard logic cell600along the6D-6D line inFIG. 6A. The standard logic cell600may be used in an IC chip having embedded memory cells, such as the bit cell102described above. The standard logic cell600may be any suitable logic cells, such as inverter (INV), AND, OR, NAND, NOR, Flip-Flop, SCAN, a random combination thereof, or a specific functional circuit.

In some embodiments, the standard logic cell600may be fabricated on the same substrate with the bit cells102described above. Thus, one or more layers, such as the STI layer206, the ILD layer208, the ILD layer210, the front side IMD layer212, the back side dielectric layer214, and the back side IMD layer216, may be fabricated during the same processes in the standard logic cell600and the bit cells102.

The standard logic cell600may be formed on and in a semiconductor substrate. Dotted lines602indicates a cell boundary of the standard logic cell600. Transistors of the standard logic cell600are formed over a p-well626P and a n-well626N. Fin structures628a,628bare formed along a first direction, such as the y-direction. Gate structures630a,630b,630care formed along a second direction, such as the x-direction over the fin structures628a,628b. Each of the fin structures628a,628bincludes two or more nano-sheet semiconductor channels628.FIGS. 6A and 6Bschematically illustrates positions of the fin structures628a,628bprior to formation of source/drain features. During fabrication, portions of the fin structures628a,628bcovered by the gate structures630a,630b,630care etched back, and epitaxial source/drain features656, shown inFIG. 6D, are then formed on both sides of the gate structures630a,630b,630cto form the transistors. As shown inFIG. 6C, the fin structure628amay have a width w5along the x-direction, and the fin structure628bmay have a width w6along the x-direction.

One or more p-type transistors are formed along the fin structure628aover the n-well626N. One or more N-type transistors are formed along the fin structure628bover the p-well626P. The transistors are formed on a semiconductor substrate during FEOL processes and embedded in the STI layer206and the ILD layer208. Front side source/drain contact features658p,658nare formed over one or more of the epitaxial source/drain features656in MEOL processes and embedded in then ILD layer210. In some embodiments, the front side source/drain contact features658p,658nmay be used to connect the corresponding source/drain features656to signal lines. Back side source/drain contact features652p,652nare formed under one or more of the epitaxial source/drain features656, during back side process. In some embodiments, a silicide layer6208may be formed between the back side source/drain contact features652p,652nand the epitaxial source/drain features656. In some embodiments, the back side source/drain contact features652p,652nmay be used to connect the corresponding source/drain features656to a power source.

As shown inFIG. 6A, conductive routing lines618are formed in the first conductive layer218formed in the front side IMD layer212. In some embodiments, the conductive routing lines618are substantially parallel to each other and may be arranged along the y-direction. Alternatively, the conductive routing lines618may be arranged along the x-direction. In some embodiments, the conductive routing lines618are signal lines configured to provide signal communication to the transistors.

In the embodiment shown inFIG. 6A, the conductive routing lines618include conductive routing lines618a618b,618c,618d,618e. The conductive routing lines618a,618c,618eare used to provide signal communication to the gate structures630c,630b,630arespectively. Gate contact features646a,646bare formed through the ILD layer210. The conductive routing lines618eand618care connected to the gate structures630a,630bby the gate contact features646a,646brespectively.

The conductive routing line618bis used to provide signal communication with the source/drain features656along the fin structure628aand the conductive routing line618dis used to provide signal communication with the source/drain features656along the fin structure628b. Conductive vias650p,650nare formed through the ILD layer210. The conductive routing lines618band618dare connected to the front side source/drain contact features658p,658nby the conductive vias650p,650nrespectively.

InFIGS. 6A-6D, two back side conductor layers622,624are embedded in the back side IMD layer216to provide power supply to the transistors in the standard logic cell600. Less or more embedded conductor layers may be included in the back side IMD layer216according to circuit design.

FIG. 6Bschematically illustrates the layout of back side power rail. The first back conductive layer622includes a conductive routing line622vssconfigured to connect to the low-voltage source VSS and a conductive routing line622vddconfigured to connect to the high-voltage source VDD. In some embodiments, the conductive routing lines622vss,622vddmay be formed along the y-direction or a direction parallel to the fin structures628a,628b. Alternatively, the conductive routing lines622vss,622vddmay be formed along the x-direction or a direction perpendicular to the fin structures628a,628b. Conductive vias615vss,615vddare formed through the back side dielectric layer214. The conductive routing lines622vssand622vddare connected to the back side source/drain contact features652n,652pby the conductive vias615vss,615vddrespectively.

The first back conductive layer624includes a conductive routing line624vssconfigured to connect to the low-voltage source VSS and a conductive routing line624vddconfigured to connect to the high-voltage source VDD. In some embodiments, the conductive routing lines624vss,624vddmay be formed along the x-direction or a direction perpendicular to the conductive routing lines622vss,622vdd. Conductive vias623vss,623vddare formed through the back side IMD layer216. The conductive routing lines624vssand624vddare connected to the conductive routing lines622vss,622vddby the conductive vias623vss,623vddrespectively.

In some embodiments, the integrated circuit10of the present disclosure further includes one or more power conductor tap structures for connecting power routing lines in the front side IMD layer212and power routing lines in the back side IMD layer216.FIG. 7schematically illustrates power conductor tap structures724vssand724vddaccording to some embodiments of the present disclosure. The power conductor tap structures724vssand724vddmay be positioned in suitable place in the integrated circuit10, for example, adjacent the standard logic cells600or adjacent the memory circuit400.

The power conductor tap structures724vssand724vddmay include one or more conductive components formed through the back side dielectric layer214, the STI layer205, the ILD layer208, and the ILD layer210. The power conductor tap structure724vssmay be positioned to connect the front side conductive line218vssto the back side conductive line622vss. The power conductor tap structure724vddmay be positioned to connect the front side conductive line218vddto the back side conductive line622vdd.

In some embodiments, the power conductor tap structure724vss,724vddincludes a conductive tap via730extending from the back side conductive layer622, wherein the conductive line622vssor622vddis formed, through the back side dielectric layer214and the STI layer206. The conductive tap via730is connected to a transistor layer conductor732formed through the ILD layer208. The transistor layer conductor732is connected to a conductive via734is formed through the ILD layer210. The conductive via734is connected to the front side conductive lines218vssor218vdd.

FIG. 8is a flow chart of a method800for fabricating the integrated circuit10according to embodiments of the present disclosure.FIGS. 9A-9B, 10A-10B, 11A-11B, 12A-12B, 13A-13C, 14A-14C, and 15A-15Cschematically illustrate various stages of manufacturing the integrated circuit10according to the method800. As discussed above, the integrated circuit10includes logic circuits and embedded memory cells. Only a portion of the integrated circuit10corresponding to a bit cell102is shown inFIGS. 9A-9B, 10A-10B, 11A-11B, 12A-12B, 13A-13C, 14A-14C, and15A-15C, as an example. Other portions of the integrated circuit10are manufactured during the same process operations with suitable designs. Additional operations can be provided before, during, and after operations/processes in the method800, and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable.

The method800begins at operation802where a plurality of fin structures228a,228b,228c,228dare formed over a substrate200as shown inFIGS. 9A and 9B. The substrate200may include a single crystalline semiconductor material such as, but not limited to Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. The substrate200may include various doping configurations depending on circuit design. For example, different doping profiles, e.g., n-wells, p-wells, may be formed in the substrate200in regions designed for different device types, such as n-type field effect transistors (NFET), and p-type field effect transistors (PFET). In some embodiments, the substrate200may be a silicon-on-insulator (SOI) substrate including an insulator structure (not shown) for enhancement.

The substrate200has a front surface200fand a back surface200b. A semiconductor stack may be deposited on the front surface200fof the substrate200. The semiconductor stack includes alternating semiconductor layers made of different materials to facilitate formation of nanosheet channels in a multi-gate device, such as nanosheet channel FETs. In some embodiments, the semiconductor stack includes first semiconductor layers202interposed by second semiconductor layers228. The first semiconductor layers202and second semiconductor layers228have different oxidation rates and/or etch selectivity.

In later fabrication stages, portions of the second semiconductor layers228form nanosheet channels in a multi-gate device. Three first semiconductor layers202and three second semiconductor layers228are alternately arranged as illustrated inFIGS. 9A-9Bas an example. More or less semiconductor layers202,228may be included in the semiconductor stack depending on the desired number of channels in the semiconductor device to be formed. In some embodiments, the number of semiconductor layers228is between 2 to 6.

The semiconductor layers202,228may be formed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. In some embodiments, the semiconductor layers228include the same material as the substrate200. In some embodiments, the semiconductor layers202,228include different materials than the substrate200. In some embodiments, the semiconductor layers202and228are made of materials having different lattice constants. In some embodiments, the first semiconductor layers202include an epitaxially grown silicon germanium (SiGe) layer and the second semiconductor layers228include an epitaxially grown silicon (Si) layer. Alternatively, in some embodiments, either of the semiconductor layers202and228may include other materials such as Ge, a compound semiconductor such as SiC, GeAs, GaP, InP, InAs, and/or InSb, an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and/or GaInAsP, or combinations thereof.

In some embodiments, each second semiconductor layer228has a thickness in a range between about 4 nm and about 8 nm. In some embodiments, the second semiconductor layers228in the semiconductor stack are uniform in thickness. The first semiconductor layers202in channel regions may eventually be removed and serve to define a vertical distance between adjacent channel regions for a subsequently formed multi-gate device. In some embodiments, the thickness of the first semiconductor layer202is equal to or greater than the thickness of the second semiconductor layer228. In some embodiments, each semiconductor layer202has a thickness in a range between about 6 nm and about 15 nm.

The fin structures228a,228b,228c,228dmay be formed by patterning a hard mask (not shown) formed on the semiconductor stack and one or more etching processes. InFIG. 9A, the fin structures228a,228b,228c,228dare formed along the y direction. A width the fin structures228a,228b,228c,228dalong the x direction is in a range between about 4 nm and about 70 nm.

The STI layer206is formed in the trenches between the fin structures228a,228b,228c,228d, as shown inFIG. 9A. The STI layer206is formed over the substrate200to cover the well portion the fin structures228a,228b,228c,228d. The STI layer206may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD), or other suitable deposition process. In some embodiments, the STI layer206may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof. In some embodiments, the STI layer206is formed to cover the fin structures228a,228b,228c,228dby a suitable deposition process, such as atomic layer deposition (ALD), and then recess etched using a suitable anisotropic etching process to expose the active portions of the fin structures228a,228b,228c,228d.

In operation804, sacrificial gate structures230including a sacrificial gate dielectric layer270and sacrificial gate electrode layer272are formed over the fin structures228a,228b,228c,228das shown inFIGS. 10A and 10B. The sacrificial gate electrode layer272may include silicon such as polycrystalline silicon or amorphous silicon. The sacrificial gate electrode layer272may be deposited using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable process, and then etched back. In some embodiment, the gate structure230may have a gate length L1along the x-direction in a range between 6 nm and 20 nm.

In operation806, the sidewall spacers242are formed on sidewalls of each sacrificial gate structure as shown inFIGS. 10A and 10B. The sidewall spacers242may be formed by a blanket deposition of an insulating material followed by anisotropic etch to remove insulating material from horizontal surfaces. The sidewall spacers242may have a thickness in a range between about 4 nm and about 12 nm. In some embodiments, the insulating material of the sidewall spacers242may include materials selected from a group consist of SiO2, Si3N4, carbon doped oxide, nitrogen doped oxide, porous oxide, air gap, or combination

In operation808, the fin structures228a,228b,228c,228don opposite sides of the sacrificial gate structure230are recess etched to form source/drain spaces and the inner spacers244are formed as shown inFIGS. 10A-10B. The first semiconductor layers202and the second semiconductor layers228in the fin structures228a,228b,228c,228dare etched down on both sides of the sacrificial gate structure230using etching operations. In some embodiments, all layers in the semiconductor stack of the fin structures228a,228b,228c,228dare etched to expose the well portion of the fin structure228a,228b,228c,228d. The inner spacers244are formed on exposed ends of the first semiconductor layers202under the sacrificial gate structure230. The first semiconductor layers202exposed to the source/drain spaces are first etched horizontally along the y-direction to form cavities. In some embodiments, the first semiconductor layers202can be selectively etched by using a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions. In some embodiments, the amount of etching of the first semiconductor layer202is in a range between about 4 nm and about 12 nm along the y direction. After forming cavities in the first semiconductor layers202, the inner spacers244can be formed in the cavities by conformally deposit and then partially remove an insulating layer. The insulating layer can be formed by ALD or any other suitable method. The subsequent etch process removes most of the insulating layer except inside the cavities, resulting in the inner spacers244.

The inner spacers244may include a single layer or multiple layers. In some embodiments, the inner spacers244may include SiO2, Si3N4, SiON, SiOC, SiOCN base dielectric material, air gap, or combination. In some embodiments, the effective dielectric constant K of the inner spacer244is higher than the dielectric constant K of the sidewall spacers242. The inner spacers244have a thickness T1along the y direction. In some embodiments, the thickness T1of the inner spacers244in a range from about 4 nm to about 12 nm.

In operation810, epitaxial source/drain features274(corresponding to the epitaxial source/drain features656in the standard logic cell600or the epitaxial source/drain features114ep,118ep,122ep,124ep,126ep,128epin the bit cell102) are formed in the source/drain spaces, as shown inFIGS. 10A-10B. The epitaxial source/drain features274may be formed by an epitaxial growth method using CVD, ALD or molecular beam epitaxy (MBE). The epitaxial source/drain features274may include one or more layers of Si, SiP, SiC and SiCP for n-type FET or Si, SiGe, Ge for a PFET. For the p-type FET, p-type dopants, such as boron (B), may also be included in the epitaxial source/drain features274.

In operation812, a contact etch stop layer (CESL) layer, not shown is formed over the epitaxial source/drain features274, and the interlayer dielectric (ILD) layer208is formed over the CESL layer. The materials for the ILD layer208include compounds comprising Si,0, C, and/or H, such as silicon oxide, SiCOH and SiOC. Organic materials, such as polymers, may be used for the ILD layer208. After the ILD layer208is formed, a planarization operation, such as CMP, is performed to expose the sacrificial gate electrode layer272for subsequent removal.

In operation814, replacement gate process sequence is performed to form the gate dielectric layer231and the gate electrode layer232, as shown inFIGS. 11A-11B. The sacrificial gate electrode272is first removed using plasma dry etching and/or wet etching to expose the fin stack within the gate region. The first semiconductor layers202are removed leaving the second semiconductor layers228as nano-sheet channels connecting the epitaxial source/drain features274. The first semiconductor layers202can be removed using an etchant that can selectively etch the first semiconductor layers202against the second semiconductor layers228. When the first semiconductor layers202are Ge or SiGe and the second semiconductor layers228are Si, the first semiconductor layers202can be selectively removed using a wet etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution.

The gate dielectric layer231is formed around each nanosheet of the second semiconductor layers228, and a gate electrode layer232is formed on the gate dielectric layer231. The gate dielectric layer231and the gate electrode layer232may be referred to as a replacement gate structure. The gate dielectric layer231may be formed by CVD, ALD or any suitable method. In one embodiment, the gate dielectric layer231is formed using a highly conformal deposition process such as ALD in order to ensure the formation of a gate dielectric layer231having a uniform thickness around each of the second semiconductor layers228. In some embodiments, the thickness of the gate dielectric layer231is in a range between about 1 nm and about 6 nm.

In some embodiments, an interfacial layer (not shown) is formed between the second semiconductor layer16and the gate dielectric layer231. In some embodiments, one or more work function adjustment layers (not shown) are interposed between the gate dielectric layer231and the gate electrode layer232.

The gate electrode layer232is formed on the gate dielectric layer231to surround each of the second semiconductor layer16(i.e., each channel) and the gate dielectric layer231. The gate electrode layer232includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. In some embodiments, the gate electrode layer232is formed by work-function metal selected from a group consisting of TiN, TaN, TiAl, TiAlN, TaAl, TaAlN, TaAlC, TaCN, WNC, Co, Ni, Pt, W, or combination. The work-function metal in n-type MOSFET and p-type MOSFET can be formed by same, or different material.

The gate electrode layer232may be formed by CVD, ALD, electro-plating, or other suitable method. After the formation of the gate electrode layer232, a planarization process, such as a CMP process, is performed to remove excess deposition of the gate electrode material and expose the top surface of the ILD layer208.

In some embodiments, a cut gate process is performed to remove a portion of the gate electrode layer232and fill in a dielectric material to form the gate isolator236. The gate isolator236electrically isolates the gates of the transistors on the opposite sides of the gate isolator236. The gate isolator236may be include materials selected from a group consisting of oxide Si3N4, nitride-base dielectric, Carbon-base dielectric, high K material (K>=9), or combination.

In some embodiments, the sidewall spacers242, the gate electrode232, and the gate dielectric layer231are etched back to form a trench over the gate top. A dielectric material is filled in the trench to form the self-aligned contact (SAC) layer234. The SAC layer234may include multiple dielectric material and selected from a group consisting of oxide, SiOC, SiON, SiOCN, nitride base dielectric, metal oxide dielectric, Hf oxide (HfO2), Ta oxide (Ta2O5), Ti oxide (TiO2), Zr oxide (ZrO2), Al oxide (Al2O3), Y oxide (Y2O3, or combination. In some embodiments, the SAC layer234may have a thickness in the z-direction in a range of 2 nm to 60 nm.

In operation816, front side contacts, such as front side gate contact features246, and front side source/drain contact features276are formed, as shown in FigureFIGS. 12A-12C. The front side source/drain contact features276(corresponding to the source/drain contact features114s,114d,118s,118d,122s,122d,124s,124d,126s,126d,128s,128din the bit cell102and the front side source/drain contact features658n,658pin the standard logic cell600) are through the ILD layer208as shown inFIGS. 12A-12C. Prior to forming the front side source/drain contact features276, contact holes are formed in the ILD layer208. Suitable photolithographic and etching techniques are used to form the contact holes through various layers, including the ILD layer208and the CESL to expose the epitaxial source/drain features274. After the formation of the contact holes, the silicide layer240is selectively formed over an exposed top surface of the epitaxial source/drain features274. The silicide layer240conductively couples the epitaxial source/drain features274to the subsequently formed front side source/drain contact features276. The silicide layer240may be formed by depositing a metal source layer over the substrate200to cover the epitaxial source/drain features274and performing a rapid thermal annealing process. In some embodiments, the metal source layer includes a metal layer selected from W, Co, Ni, Ti, Mo, and Ta, or a metal nitride layer selected from tungsten nitride, cobalt nitride, nickel nitride, titanium nitride, molybdenum nitride, and tantalum nitride. After the formation of the metal source layer, a rapid thermal anneal process is performed, for example, a rapid anneal a rapid anneal at a temperature between about 700° C. and about 900° C. During the rapid anneal process, the portion of the metal source layer over the epitaxial source/drain features274reacts with silicon in the epitaxial source/drain features274to form the silicide layer240. Unreacted portion of the metal source layer is then removed. In some embodiments, the silicide layer240includes one or more of WSi, CoSi, NiSi, TiSi, MoSi, and TaSi. In some embodiments, the silicide layer240has a thickness in a range between about 4 nm and 10 nm.

After the silicide layer240is formed, the front side source/drain contact features276are formed in the contact holes by CVD, ALD, electro-plating, or other suitable method. The front side source/drain contact features276may be in contact with the silicide layer240. The front side source/drain contact features276may include one or more of Co, Ni, W, Ti, Ta, Cu, Al, TiN and TaN. In some embodiments, a barrier layer, not shown, may be formed on sidewalls of the contact holes prior to forming the front side source/drain contact features276.

The front side source/drain contact features276are selectively formed over some of the epitaxial source/drain features274according to circuit design. The front side source/drain contact features276may be connected to signal lines in the subsequent formed front side interconnect structure, such as in the standard logic cell600. In some embodiments, the front side source/drain contact features276are formed over the epitaxial source/drain features274to a power rail, such as VDD or VSS, such as in the bit cell102. In other embodiments, the front side source/drain contact features276are formed over the epitaxial source/drain features274, but without any further connection, for structural balance in the device.

After formation of the front side source/drain contact features276, the ILD layer210is deposited over the substrate. The gate contact features246are then formed by forming openings in the ILD layer210and in the SAC layer234, and filling a conductive material in the opening. In some embodiments, the gate contact features246are further connected to signal lines in the front side IMD layer212, such as in the standard logic cell600. In other embodiments, the gate contact features246may be connect to one of the source/drain contact features276to form a butt contact, as in the bit cell102. The conductive vias250may also be formed through the ILD layer210to connect with the front side source/drain contact features276.

In operation818, a front side interconnect structure is formed over on the second ILD layer210and electrically connected to the active semiconductor devices on the substrate200, as shown inFIGS. 13A-13C. The front side interconnect structure includes the front side IMD layer212having multiple layers of conductive lines and vias formed therein. The front side IMD layer212may include multiple sets of inter-layer dielectric (ILD) layers. In some embodiment, the front side interconnect structure may include bit lines and power mesh as in the bit cell102. In other embodiments, the front side interconnect structure includes signal lines, as in the standard logic cell600.

In operation820, after the formation of the front side interconnect structure a carrier wafer278is temporarily bonded to a top side of the front side interconnect structure, as shownFIGS. 14A-C. The carrier wafer278serves to provide mechanical support for the front side interconnect structure and devices formed on the substrate200. After the carrier wafer278is bond to the substrate200, the carrier wafer278along with the substrate200is flipped over so that the backside of the substrate200(i.e., the back surface10b) is facing up for backside processing.

In operation822, grinding and etching process may be performed to remove semiconductor material from the backside, and then depositing a dielectric material to form the back side dielectric layer214.

In operation824, back side contact features, such as the back side gate conductive vias215in the bit cell102and the back side source/drain contact features652and conductive vias615, are formed through the back side dielectric layer214, as shown inFIGS. 14A-14C. The gate conductive vias215or the source/drain conductive vias615may include multiple metal material composition. The materials are selected from a group consisting of Ti, TiN, TaN, Co, Ru, Pt, W, Al, Cu, or combination.

In operation826, a backside interconnect structure is formed over the back side dielectric layer214, as shown inFIGS. 15A-15C. The back side interconnect structure includes the back side IMD layer216having multiple layers of conductive lines and vias formed therein. The back side IMD layer216may include multiple sets of inter-layer dielectric (ILD) layers. In some embodiment, the back side interconnect structure may include one or more layers of word lines, as in the bit cell102. In other embodiments, the back side interconnect structure includes a back side power rail, as in the standard logic cell600.

Various embodiments or examples described herein offer multiple advantages over the state-of-art technology. By using GAA transistors in memory cells, ICs according to the present disclosure provide more channel width with least area than conventional planar transistor or FinFET transistor, and also allow channel length continues scaling. By positioning the word lines on the back side, the ICs according to the present disclosure also improve routing efficiency, thus, removing bottleneck of further scaling both SRAM cell. By using back side power rail in standard logic cells in ICs with embedded memory cells and standard logic STD cells, the ICs further scaling in the logic cells.

Some embodiments of the present provide a memory cell comprising a device layer having transistors formed therein, a first front side conductive layer disposed above the device layer, wherein the first front side conductive layer includes, a bit line, a high-voltage line, and a low-voltage line, wherein the bit line, the high-voltage line, and the low-voltage line extend along a first direction, and a first back side conductive layer disposed below the device layer, wherein the first back side conductive layer includes a first word line extending along a second direction perpendicular to the first direction.

Some embodiments of the present disclosure provide an integrated circuit chip comprising a memory cell array including a plurality of SRAM (static random-access memory) cells arranges in columns and rows, a plurality of word line routing conductors extending along a first direction on a back side of the memory cell array, and a column of edge cells located at an edge of the memory cell array, wherein each edge cell includes a word line tap structure connected between the plurality of word line routing conductors on the back side and a plurality of word line signal lines located on a front side the memory cell array.

Some embodiments of the present disclosure an integrated circuit chip comprising a plurality of a plurality of SARM (static random-access memory) cells, wherein each SRAM cell comprises a word line located in a first back side conductive layer, and a front side voltage line located in a first front side conductive layer, and a plurality of standard logic cells, wherein each standard logic cell comprises a back side voltage line located in the first back side conductive layer.