Semiconductor device

A semiconductor device includes a semiconductor substrate having an electrode and a conductive pad; a resin projection formed on the semiconductor substrate; and a wiring electrically connected to the electrode, the wiring having a first portion formed on the electrode, a second portion formed on the conductive pad and a third portion formed on the resin projection between the first portion and the second portion.

The entire disclosure of Japanese Patent Application No. 2005-223804, filed Aug. 2, 2005 is expressly incorporated by reference herein.

BACKGROUND

1. Technical Field

The invention relates to a semiconductor device.

2. Related Art

For the sake of down-sizing of electronic parts, a smaller contour of the semiconductor device is preferred. However, as a roll of the semiconductor device is diversified, high integration of an integrated circuit formed on a semiconductor chip advances. Accordingly, the number of pins for the semiconductor chip becomes large. In other words, such a semiconductor device that can concurrently satisfy two requirements such as the down-sizing of the semiconductor device and the high integration of the integrated circuit is currently under development.

The semiconductor device of a type including a wiring formed on the semiconductor chip is come under spotlight as the one which meets the above stated requirements. In this type of semiconductor device, since the contour of the semiconductor device can be made to have the generally same contour of the semiconductor chip, the down-sizing of the semiconductor device is achievable in comparison with the known semiconductor packages.

The above stated advantageous semiconductor device is also required for a reliability equal to or more than the known semiconductor device. Therefore, the semiconductor device may be subjected to various checks. In order to guarantee the reliability of the semiconductor device, it is important to conduct an electric property check that is highly reliable.

JP-A-02-272737 is an example of related art.

SUMMARY

An advantage of the invention is to provide a semiconductor device capable of being subjected to the electric property check that is highly reliable.

According to an aspect of the invention, a semiconductor device includes a semiconductor substrate having an electrode and a conductive pad, a resin projection formed on the semiconductor substrate, and a wiring which is electrically connected to the electrode and which has a first portion formed on the electrode, a second portion formed on the conductive pad and a third portion formed on the resin projection between the first portion and the second portion. According to an aspect of the invention, the semiconductor device capable of being subjected to the electric property check that is highly reliable can be provided.

In the above stated semiconductor device of the invention, an integrated circuit is formed on the semiconductor substrate, the electrode is electrically connected to the integrated circuit within the semiconductor substrate, but the conductive pad is not necessarily electrically connected to the integrated circuit within the semiconductor substrate.

In the above stated semiconductor device of the invention, the electrode and the conductive pad may be electrically connected to each other within the semiconductor substrate.

In the above stated semiconductor device of the invention, the electrode and the conductive pad may be formed of one piece of conductive member.

In the above stated semiconductor device of the invention, the resin projection may be formed at least between the electrode and the conductive pad.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

Embodiments of the invention will now be described hereinafter with reference to the attached drawings. However, it should be appreciated that the invention is not limited to the embodiments as set forth below.

The semiconductor device according to an embodiment of the invention is explained hereinafter referring to the attached drawings.FIGS. 1A to 3are illustration for showing the semiconductor device according to the embodiment of the invention. Here,FIG. 1Ais a schematic view of the semiconductor device1according to the embodiment of the invention.FIG. 1Bis a cross sectional view taken along a line IB-IB ofFIG. 1A.

The semiconductor device according to the embodiment of the invention includes a semiconductor substrate10. The semiconductor substrate10may be, for example, a silicon made semiconductor substrate. The semiconductor substrate10may be formed into a chip shape as shown inFIG. 1A. In other words, the semiconductor substrate10may be a semiconductor chip. Alternatively, the semiconductor substrate10may be formed into a wafer shape, not shown here. The semiconductor substrate10may include an area to be a plurality of semiconductor devices. The semiconductor substrate10may include the integrated circuit12formed thereon. SeeFIG. 1B. The integrated circuit12may have any structure, and may include, for example, an active element such as a transistor and a passive element such as a resistance, a coil or a condenser. In a case that the semiconductor substrate10is formed in the chip shape, a surface or an active surface on which the integrated circuit12of the semiconductor substrate10is formed may have a rectangular shape. SeeFIG. 1A. Here, however, the active surface of the semiconductor substrate10may have a square shape.

The semiconductor substrate10has an electrode14as shown inFIG. 1B. The electrode14may be electrically connected to an electric conductor provided in the semiconductor substrate10. Here, the electrode14may be electrically connected to the integrated circuit12. Alternatively, the electrode14may include the electric conductor which is not electrically connected to the integrated circuit12. The electrode14may be a portion of an interior wiring of the semiconductor substrate10. Here, the electrode14may be a portion of the interior wiring of the semiconductor substrate10which is utilized for establishing the electrical connection with the exterior section. The electrode14may be formed of metal such as aluminum or copper. The semiconductor substrate10may have a plurality of electrodes14. Here, these electrodes14may be arranged along a straight line. These electrodes14may be arranged along a side of the active surface. In a case where the active surface of the semiconductor substrate10has the rectangular shape, these electrodes14may be arranged along a longitudinal side of the rectangular shape of the active surface.

The semiconductor substrate10has a conductive pad16as shown inFIG. 1B.

The conductive pad16may be a conductive member which is not electrically connected to the electrode14within the semiconductor substrate10. The conductive pad16may also be the conductive member which is not electrically connected to the integrated circuit12within the semiconductor substrate10. The conductive pad16may be formed so as to electrically connected to no conductive member within the semiconductor substrate10. Here, the conductive pad16may be referred to as the so-called dummy pad. The conductive pad16may be formed of metal such as aluminum or copper. The conductive pad16may be formed of the same material as the electrode14. Further, the conductive pad16may be formed of a material having a spreading property. More specifically, the conductive pad16may be formed of the material having the spreading property higher than that of a passivation film18or the so-called interlayer insulation film which will be described later. The semiconductor substrate10may have a plurality of conductive pads16. Here, these conductive pads16may be arranged along a straight line. These conductive pads16may be arranged in parallel with a line of electrodes14. The conductive pad16may be formed on the passivation film18which is not shown here but will be described later.

The semiconductor substrate10, as shown inFIG. 1B, may have the passivation film18. The passivation film18may be so formed that at least a portion of the electrode14and a portion of the conductive pad16are exposed. The passivation film18may have openings through which the electrode14and the conductive pad16expose. Also, the passivation film18may be formed under the conductive pad16. The passivation film18may be an inorganic insulation film such as SiO2 or SiN. The passivation film18may be an organic insulation film such as polyimide resin.

The semiconductor device according to the embodiment of the invention, as shown inFIGS. 1A and 1B, includes a resin projection20formed on the semiconductor substrate10. The resin projection20is formed on a surface on which the electrode14of the semiconductor substrate10is also formed. The resin projection20may be formed on the passivation film18. The resin projection20is so formed that at lease a portion of the electrode14and a portion of the conductive pad16are exposed. The resin projection20may be formed so as not to overlap the electrode14. Also, the resin projection20may be formed so as not to overlap the conductive pad16. Further, the resin projection20may be arranged between the electrode14and the conductive pad16. Here, the resin projection20may be so formed that at least a portion thereof is arranged between the electrode14and the conductive pad16. The resin projection20may be formed of any materials including the publicly known materials. For example, the resin projection20may be formed of resin such as polyimide resin, silicon modified polyimide resin, epoxy resin, silicon modified epoxy resin, benzocyclobutene (BCB), polybenzoxazole (PBO), and phenolic resin. Also, the resin projection20is not limited to a specific shape. For example, the resin projection20may be formed into a straight line shape. SeeFIG. 1A. Here, the resin projection20may be formed so as to extend along a side of the semiconductor substrate10. When the contour of the semiconductor substrate10has the rectangular shape, the resin projection20may be formed so as to extend along a longitudinal side of the semiconductor substrate as shown inFIG. 1A. Also, as seen inFIG. 1B, a surface of the resin projection20may be formed into a curved surface. Here, the cross sectional shape of the resin projection20may be a semicircle shape. The resin projection20, however, may be a hemispherical shape, which is not shown here.

The semiconductor device according to the embodiment of the invention includes a wiring30. The wiring30is formed so as to reach the resin projection20. The wiring30is drawn out from the electrode14to surmount the resin projection20, resulting in reaching the conductive pad16. In other words, the wiring30is formed to have a first portion31formed on the electrode14, a second portion32formed on the conductive pad16and a third portion33formed on the resin projection20between the first portion31and the second portion32. The semiconductor device according to the embodiment of the invention may include a plurality of wirings30. Here, the plurality of wirings30may be formed so as to surmount one resin projection20. Here, such a formation, not shown, may also be acceptable that one resin projection20is provided with only one wiring30. When one resin projection20is provided with only one wiring30, the resin projection20may have the hemispherical shape, not shown. The wiring30may be formed so as to contact the electrode14and the conductive pad16. Accordingly, the wiring30may be electrically connected to the electrode14and the conductive pad16. Alternatively, the wiring30may be formed so as to be electrically connected only to the electrode14. Namely, the wiring30may be formed so as not to be electrically connected to the conductive pad16. The wiring30may be formed with a concave portion17. The concave portion17may be positioned so as to overlap the conductive pad16. The concave portion17may be formed, for example, through the use of a step of the opening of the passivation film18. The wiring30may have any structures and may be formed of any materials. The wiring30may be formed, for example, into a single layer. Alternatively, the wiring30may be formed into a multiple layer. Here, the wiring30may include a first layer formed of titanium tungsten or titanium and a second layer formed of gold, not shown.

The semiconductor device1according to the embodiment of the invention may have the above described structure.FIG. 2illustrates a state that the semiconductor device1is mounted on the wiring substrate40. Here, the wiring substrate40may be formed of a rigid board such as a glass board or a silicon board, or a flexible board such as a film board. The wiring substrate40has an electrical connection section42. The electrical connection section42may be a portion of a wiring pattern formed on the wiring substrate40. The semiconductor device1may be mounted on the wiring substrate40in such a manner that a surface including the wiring30faces to the wiring substrate40. Here, the electrical connection section42of the wiring substrate40and the wiring30may be electrically connected to each other through a contact therebetween. More specifically, a portion of the wiring30overlapping the resin projection20contacts the electrically connection section42of the wiring substrate40in order to establish the electrical connection therebetween. Accordingly, an elastic power of the resin projection20allows the wiring30to press against the electrical connection section42. As such, the semiconductor device having a good electrical connection reliability can be provided. The semiconductor device1may be bonded on the wiring substrate40by an adhesive50. The semiconductor device1may be secured on the wiring substrate40by the adhesive50. An elastic deformation of the resin projection20may be kept by keeping a distance between the semiconductor device1and the wiring substrate40by means of the adhesive50.

FIG. 3shows an electronic module1000on which the semiconductor device1is mounted. The electronic module1000may be a display device. The display device may include, for example, a liquid crystal display or an EL display, namely, an electrical luminescence display. The semiconductor device1may be a driver IC for controlling the display device.

According to the semiconductor device1according to the embodiment of the invention, it is possible to provide the semiconductor device which is readily subjected to the check process and is capable of avoiding a lowering of the reliability of the semiconductor device after the check process thereof. The advantageous result produced therefrom will be described below.

A semiconductor device is subjected to various checks in order to guarantee a reliability. To check an electric property of the semiconductor device, a probe check is ordinary conducted. In the probe check, it is necessary to electrically connect a probe with an object to be checked. Therefore, such a method that the probe is pressed against the object to be checked to establish a electric connection therebetween is generally taken in the probe check.

The semiconductor device includes the integrated circuit formed therein. In a case that the object to be checked is provided on the integrated circuit, there is a fear that the property of the integrated circuit may change due to a load exerted onto the integrated circuit if the object to be checked is provided on the integrated circuit. If the property of the integrated circuit changes, it becomes difficult to conduct the electric property check having a good reliability. Also, if a frangible material is used immediately below the object to be checked against which the probe is pressed, a pressing force by the probe may destroy the frangible material. If the semiconductor device is destroyed, it becomes difficult to conduct the property check having a good reliability. Furthermore, it becomes impossible to use the semiconductor device as a product.

In the semiconductor device according to the embodiment of the invention, the wiring30is formed so as to reach the conductive pad16. Namely, the wiring30is formed so as to overlap the conductive pad16. The conductive pad16is made of a conductive material and has the spread ability. Accordingly, if a large force is exerted onto the conductive pad16, the conductive pad16deforms by itself to absorb the force. That is to say, even if the force is exerted on the conductive pad16from the above, the force is hardly transferred to a lower layer of the conductive pad16. Since the conductive pad16is deformable, the conductive pad16is nonbreakable. Accordingly, use of an area on the conductive pad16corresponding to the wiring30will enable the electric property check having a good reliability. Namely, pressing the probe against the area on the conductive pad16corresponding to the wiring30will enable a high reliable electric property check. More specifically, pressing the probe against the area of the conductive pad16corresponding to the wiring30will enable an establishment of the electric connection between the probe and the wiring30without changing the property of the integrated circuit. Further, in a case that the concave portion17is formed on the wiring30, the electric property check having the good reliability can be preformed efficiently since slipping of the probe is avoidable. Further, in a case that the electrode14and the conductive pad16are arranged on each side of the resin projection20, respectively, the reliability of the semiconductor device1shall be secured even if a portion of the wiring30is destroyed by the probe. That is, in the semiconductor device1as shown inFIG. 2, the area or the third portion33of the wiring30which overlaps the resin projection20is used as an exterior terminal. Therefore, if no destruction of the wiring30occurs between the electrode14and a top of the resin projection20, it is possible to secure the electrical reliability of the semiconductor device1. The conductive pad16is arranged opposite to the electrode14with respect to the resin projection20. Accordingly, if the destruction occurs in an area of the wiring30near the conductive pad16, the electrical reliability of the semiconductor device1still can be secured. The area of the wiring30, which overlaps the conductive pad16, may be referred to as a check area.

FIG. 4illustrates a modification of the semiconductor device according to the embodiment of the invention.

The semiconductor device according to the embodiment of the invention includes a semiconductor substrate60. The semiconductor substrate60includes an electrode64and a conductive pad66. The electrode64and the conductive pad66may be electrically connected within the semiconductor substrate60. Here, the conductive pad66may be referred to as a second electrode. The electrode64and the conductive pad66may be formed of one piece of conductive member65. Namely, the electrode64and the conductive pad66may be a portion of the conductive member65, respectively. Here, the electrode64and the conductive pad66may be areas of the conductive member65exposed from the passivation film. The conductive member65may be the interior wiring of the semiconductor substrate60.

The semiconductor device in accordance with the embodiment of the invention includes the wiring30. The wiring30may be formed so as to be electrically connected to the electrode64and the conductive pad66.

With the semiconductor device as set forth above, the electric property check of high reliability can be performed. Also, the semiconductor device has a structure in which one wiring30contacts one signal line at two points. Accordingly, the semiconductor device having electrically high reliability can be provided.

It should be appreciated that the invention is not limited to the above described embodiments but includes various modifications. For example, the invention includes a structure as substantially identical to the structure described in the above embodiment, more specifically, a structure having the same functions, methods and results, or a structure having the same advantages and effects. The invention also includes such a structure that inessential parts of the above stated structure of the embodiment is substituted with the other parts. The invention further includes a structure which can produce the same advantageous result as the above stated structure of the embodiment or a structure which can achieve the same advantage as the above stated structure of the embodiment. The invention still further includes a structure including known art in addition to the structure explained in the above embodiment.