Semiconductor wafer, semiconductor device, and semiconductor device manufacturing method

A semiconductor wafer includes a plurality of chip areas, a scribe line area, a bonding pad, a probing pad, and a pad connection wiring. The plurality of chip areas are configured to be arranged in a matrix form. The scribe line area is configured to separate the plurality of chip areas from each other. The bonding pad is configured to be connected with an external terminal. The probing pad is configured to be contacted with a probe wire. The pad connection wiring is configured to electrically connect the bonding pad to the probing pad. The bonding pad and the probing pad are located at a predetermined distance from each other in each of the plurality of chip areas. The pad connection wiring has a portion located in the scribe line area.

TECHNICAL FIELD

This patent specification relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device capable of effectively suppressing a short circuit and a manufacturing method thereof.

DISCUSSION OF THE RELATED ARTS

Generally, semiconductor wafers have a plurality of chip areas that are separated from each other by a scribe line area. Each chip area is provided with elements and components to form a semiconductor device. The semiconductor wafer is diced along the scribe line area into individual pieces of the semiconductor devices.

In a related semiconductor wafer, each chip area is provided with a bonding pad and a probing pad. The bonding pad is electrically connected with an external connection terminal, such as a bonding wire or a solder bump. On the other hand, the probing pad is contacted with a probe wire during a wafer test. In a related semiconductor wafer, as illustrated inFIG. 1, a bonding pad9may be located adjacent to an input-and-output cell7in a chip area3. On the other hand, recently, a multilayer metal wiring structure has been increasingly employed in semiconductor wafers. The multilayer structure allows the bonding pad to be located on the top of the input-and-output cell, thereby facilitating reduction of the size of the semiconductor device.

When the bonding pad is located on the top of the input-and-output cell, however, a contact of the probing wire during a wafer test may cause significant damage to layers under the bonding pad. For this reason, the probing pad is not configured to also perform the function of the bonding pad. The probing pad and the bonding pad are separately provided on the input-and-output cell.

FIGS. 2A and 2Bare schematic diagrams illustrating a portion (hereinafter, “pad adjacent portion”) adjacent to a bonding pad9and a probing pad11in a chip area3of another related semiconductor wafer.FIG. 2Ais a plan view of the pad adjacent portion, whileFIG. 2Bis a cross-sectional view of the pad adjacent portion seen from a section A-A inFIG. 2A. Incidentally, inFIGS. 2A and 2B, a final protection film and elements, such as a transistor, constituting the input-and-output cell are not illustrated.

In the related semiconductor wafer, the bonding pad9and the probing pad11are located on the top of the input-and-output cell7as illustrated inFIG. 2A.

The related semiconductor wafer is provided with a semiconductor substrate13, a poly-metal inter-layer insulation film15, metal wiring layers17-1to17-5, and inter-layer insulation layers19-1to19-4.

The poly-metal inter-layer insulation layer15is formed on the semiconductor substrate13. The poly-metal inter-layer insulation layer15insulates a polysilicon layer and the semiconductor substrate from the metal wiring layers17-1to17-5.

The metal wiring layers17-1to17-5are sequentially formed from bottom up on the poly-metal inter-layer insulation layer15. The inter-layer insulation layers19-1to19-4are formed between any two adjacent layers of the metal wiring layers17-1to17-5.

The bonding pad9and the probing pad11are formed in the metal wiring layer17-5. A metal wiring layer17-5cis formed between the bonding pad9and the probing pad11. Through the metal wiring layer17-5c, the bonding pad9and the probing pad5are electrically connected to each other on the input-and-output cell7.

In the above-described case, since the probing pad11is located on the top of the input-and-output cell7, some measure should be taken to suppress the damage of the probing pad11, which can be caused by the contact of a probe wire during the wafer test. Therefore, in the above related semiconductor wafer, a protection metal layer17-4cis formed under the probing pad11as a portion of the metal wiring layer17-4. The metal wiring layer17-4has via holes, through which the probing pad11and the protection metal layer17-4care electrically connected to each other.

An internal wiring17-3cis located under the protection metal layer17-4cas a portion of the metal wiring layer17-3. The internal wiring17-3cis used as a power supply wiring, a ground wiring, a signal wiring, and so forth.

In the related semiconductor wafer as illustrated inFIGS. 2A and 2B, the bonding pad9and the probing pad11are located at a given distance from each other. Alternatively, in another related semiconductor wafer, the bonding pad9and the probing pad11may be located adjacent to each other.

As described above, when the bonding pad9and the probing pad11are separately provided on the semiconductor wafer, a contact scar of the probing pad11may be left on the surface of the probing pad11, but not on the surface of the bonding pad9. Thus, an increased reliability may be obtained for the connection between the bonding pad9and the external connection terminal, such as a bonding wire or a solder bump.

Further, in the related semiconductor wafer as illustrated inFIGS. 2A and 2B, the protection metal layer17-4cis located under the probing pad11so that the damage of the probing pad11can be caused by the contact of the probe wire may not spread to the layers under the protection metal layer17-4c(for example, see Japanese Patent Application Laid-Open No. 2002-329742).

However, when a probing operation with the probing pad11is executed at high-temperature, further significant damage may be caused in the probing pad11. Consequently, the damage may spread to the layers under the protection metal layer17-4c.

For example, as illustrated inFIG. 3, when the probing pad11is contacted with a probe wire21, a crack23may be generated in the inter-layer insulation film19-4and the inter-layer insulation film19-3. Then, the crack23may cause a corrosion over time, further resulting in a short circuit between the probing pad11and the internal wiring17-3c.

That is, even when a failure is not found in the wafer test, the probing operation with the probing pad11may cause the short circuit between the probing pad11and the internal wiring17-3c. In the above-described related semiconductor wafer as illustrated inFIGS. 2A,2B, and3, the probing pad11is connected to the bonding pad9via the metal wiring layer17-5c. Therefore, a short circuit may be generated between the bonding pad9and the internal wiring17-3c, which should be essentially insulated from each other. Subsequently, the short circuit may cause damage to an integrated circuit in the semiconductor device, thus deteriorating the reliability thereof.

To suppress such a failure, for example, as illustrated inFIG. 4, a protection metal layer17-3dmay be located under the protection metal layer17-4cas a portion of the metal wiring layer17-3.

In the configuration as illustrated inFIG. 4, however, the addition of the protection metal layer17-3dmay decrease freedom in layout of the internal wiring located on the input-and-output cell. For example, a reduction or a relocation of a power supply wiring located on the input-and-output cell may have an effect on the performance of the integrated circuit. Therefore, the addition of the protection metal layer under the probing pad is not so advantageous.

Accordingly, a need exists for a semiconductor wafer, a semiconductor device, and a method for manufacturing the semiconductor device which are capable of effectively suppressing a short circuit which can be caused by the probing operation with the probing pad.

BRIEF SUMMARY

In an aspect of this disclosure, there are provided a semiconductor wafer, a semiconductor device, and a method for manufacturing the semiconductor device which are capable of effectively suppressing a short circuit which can be caused by the probing operation with the probing pad.

In at least one exemplary embodiment, there is provided a semiconductor wafer including a plurality of chip areas, a scribe line area, a bonding pad, a probing pad, and a pad connection wiring. The plurality of chip areas are arranged in a matrix form. The scribe line area separates the plurality of chip areas from each other. The bonding pad is connected with an external terminal. The probing pad is contacted with a probe wire. The pad connection wiring electrically connects the bonding pad to the probing pad. The bonding pad and the probing pad are located at a predetermined spacing from each other in each of the plurality of chip areas. The pad connection wiring has a portion located in the scribe line area.

In at least one exemplary embodiment, there is provided a semiconductor device including the above-described semiconductor wafer. The semiconductor device is formed by cutting the semiconductor wafer along the scribe line area. The bonding pad and the probing pad are electrically separated from each other. The scribe line area has a cut surface including a section of the pad connection wiring connected to the bonding pad and a section thereof connected to the probing pad.

In at least one exemplary embodiment, there is provided a method for producing the above-described semiconductor device. The method includes performing a wafer test while contacting the probe wire to the probing pad, cutting the scribe line area, cutting the pad connection wiring, and electrically separating the bonding pad and the probing pad from each other.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

In describing exemplary embodiments illustrated in the drawings, specific terminology is employed for the sake of clarity. However, the disclosure of this patent specification is not intended to be limited to the specific terminology so selected and it is to be understood that each specific element includes all technical equivalents that operate in a similar manner. Referring now to the drawings, wherein like reference numerals designate identical or corresponding parts throughout the several views, exemplary embodiments of the present patent specification are described.

First, referring toFIGS. 5A,5B and6-8, a semiconductor wafer100according to an exemplary embodiment of the present specification is described.

FIG. 5Ais an enlarged plan view illustrating a pad adjacent portion of the semiconductor wafer100according to the present exemplary embodiment.FIG. 5Bis a cross-sectional view of the pad adjacent portion seen from a section B-B inFIG. 5A.

FIG. 6is a cross-sectional view illustrating a state of the pad adjacent portion during a wafer test.FIG. 7is an overall plan view of the semiconductor wafer100.FIG. 8is an enlarged plan view of a portion indicated by a dashed circle line4ofFIG. 7.

Incidentally, elements, such as a transistor, are not illustrated inFIGS. 5A,5B, and6. Further, a final protection film is not illustrated inFIGS. 5A,5B,6, and8.

Furthermore, as illustrated inFIG. 7, the semiconductor wafer100is provided with a plurality of chip areas3that are arranged in a matrix form. The plurality of chip areas3are separated from each other by a scribe line area5. A plurality of elements and pads (not illustrated) for process monitoring are located on the scribe line area5.

As illustrated inFIG. 8, a plurality of input-and-output cells7are arranged in the periphery of each of the plurality of chip areas3. A bonding pad9and a probing pad11are located on each of the plurality of input-and-output cells7. The bonding pad9is electrically connected with an external terminal. The probing pad11is contacted with a probe wire.

Next, referring toFIGS. 5A and 5B, a configuration of the pad adjacent portion is described.

The semiconductor wafer100includes the bonding pad9, the probing pad11, a semiconductor substrate13, a poly-metal inter-layer insulation film15, metal wiring layers17-1to17-5, and inter-layer insulation film19-1to19-4.

The semiconductor substrate13is provided with an element, such as a transistor, and an element separation oxide film (neither of which is illustrated) thereon. The poly-metal inter-layer insulation film15is formed on the semiconductor substrate13. The poly-metal inter-layer insulation film15has a contact hole at a given position. A conductive material such as tungsten is filled into the contact hole.

The metal wiring layers17-1to17-5are sequentially superimposed on the poly-metal inter-layer insulation layer15. The inter-layer insulation layers19-1to19-4are formed between the metal wiring layers17-1to17-5. The bonding pad9and the probing pad11are formed in the metal wiring layer17-5, which is configured as an uppermost metal wiring layer. The bonding pad9and the probing pad11are located at a predetermined distance from each other.

The final protection layer (not illustrated) is formed on the inter-layer insulation layer19-4and the metal wiring layer17-5. The final protection layer has openings at positions corresponding to the bonding pad9and the probing pad11. Thus, the metal wiring layer17-5are partially exposed at the openings.

The metal wiring layer17-5includes a metal wiring layer17-5aand a metal wiring layer17-5b. The metal wiring layer17-5ais extended from the bonding pad9, and is electrically connected to a metal wiring layer17-1athrough a via hole, a metal wiring layer17-4a, a via hole, a metal wiring layer17-3a, a via hole, a metal wiring layer17-2a, and a via hole.

One end of the metal wiring layer17-5bis extended from the probing pad11, and is located in the scribe line area5. A metal wiring layer17-4b, a metal wiring layer17-3b, and a metal wiring layer17-2bare formed under the metal wiring layer17-5bin the scribe line area5. The metal wiring layer17-4b, the metal wiring layer17-3b, and the metal wiring layer17-2bare electrically connected through via holes.

The metal wiring layer17-2bis connected to the metal wiring layer17-2a, an opposite end of the metal wiring layer17-2. Further, the metal wiring layer17-2ais electrically connected to the bonding pad9. Specifically, the probing pad11is electrically connected to the probing pad11through the metal wiring layers17-5b,17-4b,17-3b,17-2b,17-2a,17-3a,17-4a,17-5a, and the via holes. The metal wiring layers17-2b,17-3b,17-4b, and17-5bconstitutes a wiring (hereafter, “pad connection wiring”) to connect the bonding pad9to the probing pad11.

A protection metal layer17-4c, which constitutes a portion of a fourth metal wiring layer, is formed under the probing pad11. The probing pad11and the protection metal layer17-4care electrically connected to each other through via holes.

An internal wiring17-3c, which constitutes a portion of a third metal wiring layer, is located under the protection metal layer17-4c.

During a wafer test, the probing pad11and the probe wire21are kept in contact with each other, as illustrated inFIG. 6. Then, the contact of the probe wire21may cause a crack23in the inter-layer insulation layers19-3and19-4.

Incidentally, as described above, if the above-described state is left over time, the crack23may cause corrosion, resulting in a short circuit between the metal wiring layers. In this configuration as illustrated inFIG. 6, a short circuit may be caused between the probing pad11and the internal wiring17-3a.

Therefore, according to the present exemplary embodiment, as described below, the bonding pad9and the probing pad11are electrically separated from each other so as to suppress the short circuit when the scribe line area5is cut out.

FIG. 9is a cross-sectional view illustrating a pad adjacent portion of a semiconductor device25formed by cutting the semiconductor wafer100illustrated inFIG. 5A. The semiconductor device25is formed by cutting out the chip area3along the scribe line area5of the semiconductor wafer100illustrated inFIG. 5A.

Below, a method for manufacturing the semiconductor device25is described with reference toFIGS. 6 and 9.

After a wafer test is performed while contacting the probe wire21to the probing pad11as illustrated inFIG. 6, the semiconductor wafer100is diced along the scribe line area5. At this time, an end of the metal wiring layer17-5bopposite to the probing pad11, the metal wiring layer17-4b, the metal wiring layer17-3b, and an end of the metal wiring layer17-2bopposite to the metal wiring layer17-2aare removed together with the scribe line area5. Thus, the bonding pad9and the probing pad11are electrically separated from each other.

Next, a configuration of the semiconductor device25is described with reference to theFIG. 9.

As described above, the semiconductor device25according to the present exemplary embodiment has a configuration in which the bonding pad9and the probing pad11are electrically separated from each other. Further, cross sections of the metal wiring layer17-5band the metal wiring layer17-2bare exposed on a cut surface25aof the scribe line area5. The metal wiring layer17-5bis electrically connected to the bonding pad9, while the metal wiring layer17-2bis electrically connected to the probing pad11.

The semiconductor wafer100has a configuration in which the bonding pad9and the probing pad11are located at a given distance from each other in the chip area3. As illustrated inFIG. 5A, the semiconductor wafer100also includes the metal wiring layers17-2b,17-3b,17-4b, and17-5b. A portion of each of the metal wiring layers17-2band17-5band an entire portion of each of the metal wiring layers17-3band17-4bare located in the scribe line area5.

Then, the chip area3is cut out from the semiconductor wafer100along the scribe line area5so as to form the semiconductor device25. At this time, the portion of each of the metal wiring layers17-2band17-5band the entire portion of each of the metal wiring layers17-3band17-4bare cut off. Therefore, in the semiconductor device25, the bonding pad9and the probing pad11are electrically separated from each other.

Thus, as illustrated inFIG. 9, even when the internal wiring17-3cis located under the probing pad11, and a crack23is caused under the probing pad11by the contact of the probing wire21, a short circuit can be suppressed between the internal wiring17-3cand the bonding pad9.

At this time, a short circuit may be caused between the internal wiring17-3cand the probing pad11by the crack23. However, as described above, the short circuit can be suppressed between the internal wiring17-3cand the bonding pad9. Further, since the pad connection wiring is cut off in cutting out the semiconductor device25, the probing pad11becomes electrically in a floating state. Therefore, a failure possibly caused by the crack23can be effectively suppressed in the semiconductor device25.

According to the present exemplary embodiment, the metal wiring layer17-2b, which constitutes a portion of the pad connection wiring, is located under the probing pad11. Alternatively, as illustrated inFIGS. 10A and 10B, the metal wiring layer17-2bmay be located at a position that is not under the probing pad11in order to connect between the metal wiring layers17-2band17-2a.

FIG. 11is a cross-sectional view illustrating a pad adjacent portion of a semiconductor device25formed by cutting the semiconductor wafer100illustrated inFIGS. 10A and 10B. Specifically, the semiconductor device25is formed by cutting out the chip area3along the scribe line area5of the semiconductor wafer100as illustrated inFIGS. 10A and 10B.

Below, a method for manufacturing the semiconductor device25is described with reference toFIGS. 10A,10B, and11.

After a wafer test is performed while contacting a probe wire to the probing pad11, the semiconductor wafer100is diced along the scribe line area5. At this time, an end of the metal wiring layer17-5bopposite to the probing pad11, the metal wiring layer17-4b, the metal wiring layer17-3b, and end of the metal wiring layer17-2bopposite to the metal wiring layer17-2aare removed together with the scribe line area5. Thus, the bonding pad9and the probing pad11are electrically separated from each other as illustrated inFIG. 11.

According to the present exemplary embodiment, even when a crack23is caused under the internal wiring23by the contact of the probe wire, a short circuit can be suppressed between the bonding pad9and the probing pad11.

In the present exemplary embodiment as illustrated inFIGS. 10A,10B, and11, the bonding pad9and the probing pad11are electrically connected to each other by disposing the metal wiring layer17-2bso as to straddle the chip area3and the scribe line area5. However, the exemplary embodiment of the present specification is not limited to the configuration as illustrated inFIGS. 10A,10B, and11. Any metal wiring layer may be located so as to straddle the chip area3and the scribe line area5to electrically connect the bonding pad9to the probing pad11.

FIGS. 12A and 12Bare enlarged views of a pad adjacent portion of a semiconductor wafer100according to another exemplary embodiment of the present specification.FIG. 12Ais a plan view of the pad adjacent portion, whileFIG. 12Bis a cross-sectional view of the pad adjacent portion seen from a section D-D inFIG. 12A. InFIGS. 12A and 12B, components substantially similar in function to components inFIGS. 5A and 5Bare indicated by identical codes, and repeated descriptions of the components are omitted.

In the present exemplary embodiment illustrated inFIGS. 12A and 12B, the metal wiring layer17-5bis extended from the probing pad11, is led into the scribe line area5, and is turned back into the chip area3to be connected to the metal wiring layer17-5a.

Further, unlike the exemplary embodiment illustrated inFIGS. 5A and 5B, the semiconductor device100illustrated inFIGS. 12A and 12Bdoes not include the metal wiring layers17-2b,17-3b, and17-4b, and the via holes through which the metal wiring layers17-2b,17-3b, and17-4bis connected to the metal wiring layer17-5b. Therefore, according to the present exemplary embodiment, the metal wiring layer17-5bconstitutes a portion of the pad connection wiring to connect the bonding pad9to the probing pad11.

FIG. 13is a cross-sectional view illustrating a semiconductor device25formed by cutting the semiconductor wafer100illustrated inFIGS. 12A and 12B. Specifically, the semiconductor device25is formed by cutting out the chip area3along the scribe line area5of the semiconductor wafer100illustrated inFIGS. 12A and 12B.

Below, a manufacturing method of the semiconductor device25is described with reference toFIGS. 12A,12B, and13.

After a wafer test is performed while contacting a probe wire to the probing pad11, the semiconductor wafer100is diced along the scribe line area5. At this time, a portion of the metal wiring layer17-5blocated in the scribe line area5is removed together with the scribe line area5. Thus, the bonding pad9and the probing pad11are electrically separated from each other as illustrated inFIG. 13.

According to the present exemplary embodiment, even when a crack23is caused under the probing pad11by the contact of the probe wire, a short circuit can be suppressed between the bonding pad9and the probing pad11.

Further, since the bonding pad9, the probing pad11, and the metal wiring layer17-5bare formed in an uppermost metal wiring layer, the bonding pad and the probing pad are easy to form. Alternatively, the bonding pad9, the probing pad11, and the pad connection wiring may be formed in any other metal wiring layer than the uppermost metal wiring layer.

Furthermore, since the bonding pad9, the probing pad11, and the metal wiring layer17-5bconstituting the pad connection wiring are formed in a single metal wiring layer, the wiring structure of the pad connection wiring can be simplified. Thus, the present exemplary embodiment is applicable to a semiconductor device having a single-layer metal wiring structure of chip area.

According to the present exemplary embodiment illustrated inFIGS. 12A,12B, and13, the bonding pad9is located near the center of the chip area3on the input-and-output cell7. On the other hand, the probing pad11is located near the scribe line area5on the input-and-output cell7. Alternatively, the probing pad11may be located near the center of the chip area3on the input-and-output cell7, while the bonding pad9may be located near the scribe line area5.

Moreover, according to the present exemplary embodiment, the bonding pad9and the probing pad11are located on the input-and-output cell7. However, the positions of the bonding pad9and the probing pad11are not limited to the above disposition.

In addition, according to the present exemplary embodiment, the probing pad11is entirely located in the chip area3. Alternatively, a portion of the probing pad11may be located in the scribe line area5.

FIGS. 14A and 14Bare enlarged diagrams illustrating a pad adjacent portion of the semiconductor wafer100according to another exemplary embodiment of the present specification.FIG. 14Ais a plan view of the pad adjacent portion, whileFIG. 14Bis a cross-sectional view of the pad adjacent portion seen from a section E-E inFIG. 14A.

InFIGS. 14A and 14B, components substantially similar in function to components inFIGS. 5A and 5Bare indicated by identical codes, and repeated descriptions of the components are omitted. Incidentally, according to the present exemplary embodiment, as described above, a portion of the probing pad11is located in the scribe line area5.

FIG. 15is a cross-sectional view illustrating a pad adjacent portion of a semiconductor device25formed by cutting the semiconductor wafer100illustrated inFIGS. 14A and 14B. Specifically, the semiconductor device25is formed by cutting out the chip area3along the scribe line5of the semiconductor wafer300illustrated inFIGS. 14A and 14B.

Below, a manufacturing method of the semiconductor device25is described with reference toFIGS. 14A,14B, and15.

After a wafer test is performed while contacting a probe wire to the probing pad11, the semiconductor wafer100is diced along the scribe line area5. At this time, a portion of the probing pad11located in the scribe line area5, the metal wiring layer17-5b, the metal wiring layer17-4b, the metal wiring layer17-3b, and an end of the metal wiring layer17-2bopposite to the metal wiring layer17-2aare removed together with the scribe line area5. Thus, the bonding pad9and the probing pad11are electrically separated from each other as illustrated inFIG. 15.

Next, referring toFIG. 15, a configuration of the semiconductor device25is described.

As described above, in the semiconductor device25, the bonding pad9and the probing pad11are electrically separated from each other. Cross sections of the metal wiring layer17-2band the residue of the probing pad11are exposed on a cut surface25aof the scribe line area5. The metal wiring layer17-2bis electrically connected to the bonding pad9.

According to the present exemplary embodiment, even when a crack23is caused under the probing pad11by the contact of the probe wire, a short circuit can be suppressed between the bonding pad9and the probing pad11. Further, since a portion of the probing pad11is located in the scribe line area5, an area occupied by the probing pad11in the chip area3can be reduced. Therefore, the chip area3can be downsized.

The above configuration, in which a portion of the probing pad11is located in the scribe line area5, is applicable to the above-described exemplary embodiments as illustrated inFIGS. 10A,10B,11,12A,12B, and13. In those exemplary embodiments, the chip area3can be effectively downsized similar to the present embodiment.

Alternatively, an entire portion of the probing pad11may be located in the scribe line area5as illustrated inFIGS. 16A and 16B.

FIGS. 16A and 16Bare enlarged diagrams illustrating a pad adjacent portion of a semiconductor wafer100according to another exemplary embodiment of the present specification.FIG. 16Ais a plan view of the pad adjacent portion, whileFIG. 16Bis a cross-sectional view of the pad adjacent portion seen from a section F-F inFIG. 16A. InFIGS. 16A and 16B, components substantially similar in function to components inFIGS. 5A and 5Bare indicated by identical codes, and repeated descriptions of the components are omitted.

According to the present exemplary embodiment illustrated inFIGS. 16A and 16B, an entire portion of the probing pad11is located in the scribe line area5. Further, the semiconductor device100according to the present exemplary embodiment does not include the metal wiring layer17-5band the protection metal layer17-4c. The metal wiring layers17-2b,17-3b,17-4b, and via holes are formed under the probing pad11, and constitute the pad connection wiring for connecting the bonding pad9and the probing pad11. Since the entire portion of the probing pad11is located in the scribe line area5, the internal wiring17-3cis not located under the probing pad11.

FIG. 17is a cross-sectional view illustrating of a pad adjacent portion of a semiconductor device25formed by cutting the semiconductor wafer100illustrated inFIGS. 16A and 16B. Specifically, the semiconductor device25is formed by cutting out the chip area3along the scribe line area5of the semiconductor wafer100illustrated inFIGS. 16A and 16B.

Below, a manufacturing method of the semiconductor device25is described with reference toFIGS. 16A,16B, and17.

After a wafer test is performed while contacting a probe wire to the probing pad11, the semiconductor wafer100is diced along the scribe line area5. At this time, the probing pad11, the metal wiring layer17-4b, the metal wiring layer17-3b, and an end of the metal wiring layer17-2bopposite to the metal wiring layer17-2aare removed together with the scribe line area5as illustrated inFIG. 17.

Next, a configuration of the semiconductor device25is described referring toFIG. 17.

The semiconductor device25does not include the probing pad11. A cross section of the metal wiring layer17-2bis exposed on a cut surface25aof the scribe line area5. The metal wiring layer17-2bis electrically connected to the bonding pad9.

According to the present exemplary embodiment, the internal wiring17-3cis not located under the probing pad11. Further, even when damage is caused under the probing pad11by the contact of the probe wire, a short circuit can be suppressed between the internal wiring23and the bonding pad9because the probing pad11has been cut off together with the scribe line area5.

Further, an area occupied by the probing pad11in the chip area3can be eliminated. Therefore, the chip area3can be effectively downsized.

According to the present exemplary embodiment illustrated inFIGS. 16A,16B, and17, the metal wiring layers17-2b,17-3b,17-4b, and via holes, which constitute the pad connection wiring, are located under the probing pad11. Further, the metal wiring layers17-2aand17-2bare connected to each other so as to electrically connect the probing pad11and the bonding pad9.

In this configuration, the via holes may be formed at positions that are not under the probing pad11. For example, the metal wiring layer17-5is extended from the probing pad11, and the via holes are provided at positions that are not under the probing pad11. Thus, the probing pad11and the metal wiring layer17-2amay be electrically connected to each other through the metal wiring layer17-5, and the metal wiring layers17-2b,17-3b, and17-4b. In this configuration, the via holes may be formed in any of the chip area3and the scribe line area5.

The above-described configuration, in which the probing pad11is entirely located in the scribe line area5, is applicable to the above-described exemplary embodiments illustrated inFIGS. 10A,10B,11,12A,12B, and13. In those exemplary embodiments, the chip area3can be effectively downsized similar to the present embodiment.

In the present exemplary embodiment, the above-described configuration is applied to a five-layer metal wiring structure of semiconductor wafer. Alternatively, the above-described configuration may be applied to a semiconductor wafer having a metal wiring structure of one or more layers. Further, the above-described configuration may be applied to a manufacturing method of a semiconductor device from the semiconductor wafer, and the resultant semiconductor device.

In the above-described exemplary embodiments having the probing pad11in the chip area3, the protection metal layer17-4cis located under the probing pad11. Alternatively, the protection metal layer17-4cmay be omitted.

The above-described exemplary embodiments of this patent specification may be conveniently implemented using a conventional general purpose digital computer programmed according to the teachings of the present specification, as will be apparent to those skilled in the computer art. Appropriate software coding can readily be prepared by skilled programmers based on the teachings of the present disclosure, as will be apparent to those skilled in the software art. The subject matter of the present disclosure may also be implemented by the preparation of application specific integrated circuits or by interconnecting an appropriate network of conventional component circuits, as will be readily apparent to those skilled in the art.

This patent specification is based on Japanese patent applications, No. JP2006-055998 filed on Mar. 2, 2006 in the Japan Patent Office, the entire contents of which are incorporated by reference herein.