Image pickup device and electronic apparatus

The present technology relates to an image pickup device and an electronic apparatus capable of preventing degradation of the picture quality. A plurality of current sources can be selectively connected to an output terminal for outputting a reference signal having a level that varies, and a plurality of terminating resistors are connected to the output terminal. The terminating resistors that are to supply current of current sources that are connected to the output terminal are connected by a plurality of switches, and current of current sources that are not connected to the output terminal is supplied to the switches. The present technology can be applied, for example, to image pickup devices that perform AD conversion using a reference signal and so forth.

CROSS REFERENCNE TO RELATED APPLICATIONS

This application is a U.S. National Phase of International Patent Application No. PCT./JP2016/070260 file on Jul. 8, 2016, which claims priority benefit of Japanese Patent Application No. JP 2015-144836 filed in the Japan Patent Office on Jul. 22, 2015. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present technology relates to an image pickup device and an electronic apparatus, and particularly to an image pickup device and an electronic apparatus capable of preventing, for example, degradation of the picture quality.

BACKGROUND ART

In recent years, a CMOS (Complementary Metal Oxide Semiconductor) image sensor is widely used as a (solid-state) image pickup device from the point of view of the cost and so forth.

In the CMOS image sensor, a slope type AD conversion circuit is widely utilized for AD (Analog to Digital) conversion of an electric signal outputted from a pixel (hereinafter referred to also as pixel signal). In the slope type AD conversion circuit, a ramp signal is used as a reference signal (voltage) and the reference signal and the pixel signal are compared with each other by a comparator, and a time period before an output of the comparator reverses is counted by a counter to perform AD conversion of the pixel signal (for example, refer to PTL 1).

According to the slope type AD conversion circuit, a column AD conversion circuit can be configured in which, for example, a slope type AD conversion circuit is arrayed for each pixel column and the AD conversion is performed at the same time for all columns.

CITATION LIST

Patent Literature

SUMMARY

Technical Problem

Where a ramp signal used as the reference signal in the slope type AD conversion circuit disperses, a pixel value obtained by AD conversion performed using the reference signal is dispersed and hence the picture quality of an image obtained by an image pickup device is degraded.

The present technology has been made in view of such a situation as described above, and it is an object of the present technology to make it possible to prevent degradation of the picture quality.

Solution to Problem

The image pickup device of the present technology is an image pickup device including a pixel having a photoelectric conversion device that performs photoelectric conversion and configured to output an electric signal, a reference signal generation unit configured to generate a reference signal having a level that varies, a comparison unit configured to compare the electric signal and the reference signal with each other, and a counting unit configured to perform AD (Analog to Digital) conversion of the electric signal by performing counting of a count value in response to a result of the comparison between the electric signal and the reference signal. The reference signal generation unit includes a plurality of current sources whose connection to an output terminal for outputting the reference signal is selectable, a plurality of terminating resistors connected to the output terminal, and a plurality of switches configured to select the terminating resistors that are to supply current of the current sources that are connected to the output terminal, and is configured so as to supply current of the current sources that are not connected to the output terminal to the switches.

The electronic apparatus of the present technology is an electronic apparatus including an optical system configured to collect light, and an image pickup device configured to receive the light to pick up an image. The image pickup device includes a pixel having a photoelectric conversion device that performs photoelectric conversion and configured to output an electric signal, a reference signal generation unit configured to generate a reference signal having a level that varies, a comparison unit configured to compare the electric signal and the reference signal with each other, and a counting unit configured to perform AD (Analog to Digital) conversion of the electric signal by performing counting of a count value in response to a result of the comparison between the electric signal and the reference signal. The reference signal generation unit includes a plurality of current sources whose connection to an output terminal for outputting the reference signal is selectable, a plurality of terminating resistors connected to the output terminal, and a plurality of switches configured to select the terminating resistors that are to supply current of the current sources that are connected to the output terminal, and is configured so as to supply current of the current sources that are not connected to the output terminal to the switches.

In the image pickup device and the electronic apparatus of the present technology, a reference signal is generated, and an electric signal outputted from the pixel and the reference signal are compared with each other. Then, in response to a result of the comparison between the electric signal and the reference signal, counting of a count value is performed to perform AD conversion of the electric signal. The reference signal is generated by supply of current of the plurality of current sources, whose connection to the output terminal for outputting the reference signal is selectable, to the terminating resistors connected to the output terminal. The terminating resistors to which current of the current sources connected to the output terminal is to be supplied are selected by switches. To the switches, current of the current sources that are not connected to the output terminal is supplied.

It is to be noted that the image pickup device may be an independent device or may be an internal block configuring one apparatus.

Advantageous Effect of Invention

With the present technology, degradation of the picture quality can be prevented.

It is to be noted that the effect described here is not necessarily restrictive and may be any of the effects described in the present disclosure.

DESCRIPTION OF EMBODIMENT

<One Embodiment of Image Pickup Device to which the Present Technology is Applied>

FIG. 1is a block diagram depicting an example of a configuration of an embodiment of an image pickup device to which the present technology is applied.

InFIG. 1, the image pickup device includes a semiconductor substrate1, a pixel array unit2, a row scanning unit3, a column signal processing unit4, a column scanning unit5, a system controlling unit6, pixel driving lines7, VSLs (Vertical Signal Lines) (vertical signal lines)8, a transfer line9, and an output terminal10.

The components from the pixel array unit2to the output terminal10are formed on the semiconductor substrate1.

For example, hereinafter described, the pixel array unit2is configured by arraying pixels110(FIG. 2), which perform photoelectric conversion, in a two-dimensional matrix by H×V horizontally and vertically.

The pixel array unit2outputs a pixel signal obtained by photoelectric conversion by each pixel110to a VSL8under the control of the row scanning unit3.

The row scanning unit3controls (drives) the pixels110connected to the pixel driving lines7through the pixel driving lines7under the control of the system controlling unit6. Here, one or more pixel driving lines7are arrayed for each row of the pixels110.

The column signal processing unit4is connected, for example, to H pixels110arrayed in each row through H VSLs8such that pixel signals that are electric signals (voltages) outputted from the pixels110to the VSLs8are supplied as voltages of the VSLs8(VSL voltages).

The column signal processing unit4performs AD conversion of VSL voltages (pixel signals), which are supplied through the VSLs8from the H pixels110arrayed in each row, in parallel under the control of the system controlling unit6. Further, the column signal processing unit4outputs digital data obtained as a result of the AD conversion of the VSL voltages as pixel values (pixel data) of the pixels110to the transfer line9under the control of the column scanning unit5. The pixel values outputted to the transfer line9are transferred to the output terminal10and outputted to the outside.

Here, the column signal processing unit4can perform AD conversion of the pixel signals of all of H pixels110arrayed on one row in parallel and further can perform AD conversion of pixel signals of a plural number of pixels smaller than H from the H pixels110in parallel.

However, in the following description, in order to simplify the description, it is assumed that the column signal processing unit4performs AD conversion of the VSL voltage of all of the H pixels110arrayed in one column in parallel.

The column scanning unit5controls the column signal processing unit4to output a result of the AD conversion of the VSL voltages (pixel signals) to the transfer line9under the control of the system controlling unit6.

The system controlling unit6controls the row scanning unit3, the column signal processing unit4, and the column scanning unit5.

In the image pickup device configured in such a manner as described above, each pixel110(FIG. 2) in the pixel array unit2performs photoelectric conversion of light incident thereto. Pixel signals that are electric signals obtained as a result of the photoelectric conversion by the pixels110are outputted from each H pixels110in one row beginning with the pixels110in the first row to the VSLs8under the control of the row scanning unit3through the pixel driving lines7.

The VSL voltages on the VSLs8obtained from the pixel signals outputted to the VSLs8are AD converted in column parallel for each row by the column signal processing unit4under the control of the system controlling unit6, and pixel values that are a result of the AD conversion are outputted from the output terminal10through the transfer line9.

<Example of Configuration of Pixel Array Unit2and Example of Configuration of Column Signal Processing Unit4>

FIG. 2is a block diagram depicting an example of a configuration of the pixel array unit2and an example of a configuration of the column signal processing unit4.

The pixel array unit2has a plurality of pixels110that perform photoelectric conversion. In the pixel array unit2, the plurality of pixels110are arrayed in a two-dimensional matrix by H×V horizontally and vertically.

The VSLs8are wired, for example, for each column of the pixels110, and each pixel110outputs a pixel signal obtained as a result of the photoelectric conversion to a VSL8.

The pixel signal outputted from the pixel110to the VSL8is supplied as a VSL voltage to the column signal processing unit4.

The column signal processing unit4includes, for example, H bias circuits120, comparators140, and counters150equal to the number of VSLs8, a reference signal generation circuit130and a reference clock generation circuit131and configures a column AD conversion circuit.

Each bias circuit120is a current source and supplies current to a VSL8to control the VSL8to a predetermined voltage.

The reference signal generation circuit130is configured, for example, from a DAC (Digital to Analog Converter), and generates a ramp (ramp) signal whose level (voltage) varies from a predetermined initial value to a predetermined final value in a fixed inclination as a reference signal to be used for AD conversion and supplies the ramp signal to one of two input terminals of H comparators140.

The reference clock generation circuit131generates a reference clock that is a clock used by a counter150to count a count value and supplies the reference clock to the H counters150.

Each comparator140is connected at the other input terminal thereof to a VSL8. Accordingly, a VSL voltage (pixel signal) is supplied to the other input terminal of the comparator140through the VSL8.

Here, capacitors141and142are individually connected to the two input terminals of the comparator140. A reference signal from the reference signal generation circuit130is supplied to the comparator140through the capacitor141, and a VSL voltage from the VSL8is supplied to the comparator140through the capacitor142.

The comparator140compares the reference signal and the VSL voltage supplied to the two input terminals thereof with each other, and outputs a result of the comparison as a comparator output.

Here, where the reference signal is higher than the VSL voltage (or the reference signal is equal to or higher than the VSL voltage), the comparator140outputs, for example, an H level from between an H (High) level and an L (Low) level as a comparator output. Further, where the reference signal is not higher than the VSL voltage, the comparator140inverts the comparator output and outputs the L level.

The comparator output is supplied from the comparator140to the counter150.

The counter150performs counting of a count value in synchronism with a reference clock supplied thereto from the reference clock generation circuit131.

In the counter150, counting of the count value is performed in response to the comparator output from the comparator140.

In particular, the counter150performs counting of the count value, for example, when the comparator output exhibits the H level, and stops the counting when the level of the comparator output is inverted to the L level.

The counter150counts the time required for variation of the level of the reference signal before the VSL voltage and the reference signal (voltage) become coincident with each other (before the relationship in magnitude between the VSL voltage and the reference signal is reversed) in such a manner as described above to perform AD conversion of the VSL voltage (pixel signal).

The counter150outputs its count value, namely, a result of the AD conversion of the VSL voltage (pixel signal) as a pixel value to the transfer line9(FIG. 1).

In the column signal processing unit4ofFIG. 2, one set of a comparator140and a counter150configures one slope type AD conversion circuit together with the reference signal generation circuit130and the reference clock generation circuit131.

It is to be noted that, while, inFIG. 2, one set of a comparator140and a counter150, which is one slope type AD conversion circuit, is provided for each one column (of the pixels110), the set of a comparator140and a counter150can be provided for each of a plurality of columns such that AD conversion of the plurality of columns is performed time-divisionally.

<Example of Configuration of Pixel110>

FIG. 3is a circuit diagram depicting an example of a configuration of a pixel110.

Referring toFIG. 3, the pixel110includes a PD (Photo Diode)101and four FETs (Field Effect Transistors)102,103,104, and105each in the form of an NMOS (negative channel MOS).

Further, in the pixel110, the drain of the FET102, source of the FET103, and gate of the FET104are connected to each other, and an FD (Floating Diffusion) (capacitor)106for converting charge into a voltage is formed at the connection point of them.

The PD101is an example of a photoelectric conversion device that performs photoelectric conversion, and receives incident light to accumulate electric charge corresponding to the incident light to perform photoelectric conversion.

The PD101is connected (grounded) at the anode thereof to the ground, and is connected at the cathode thereof to the source of the FET102.

The FET102is an FET for transferring the electric charge accumulated in the PD101from the PD101to the FD106and is hereinafter referred to also as transfer Tr102.

The transfer Tr102is connected at the source thereof to the cathode of the PD101and is connected at the drain thereof to the FD106.

Further, the transfer Tr102is connected at the gate thereof to a pixel driving line7, and a transfer pulse TRF is supplied to the gate of the transfer Tr102through the pixel driving line7.

Here, controlling signals to be supplied to the pixel driving lines7in order for the row scanning unit3to drive (control) the pixel110through the pixel driving lines7include not only the transfer pulse TRF but also a reset pulse RST and a selection pulse SEL hereinafter described.

The FET103is an FET for resetting the electric charge (voltage (potential)) accumulated in the FD106and is hereinafter referred to also as reset Tr103.

The reset Tr103is connected at the drain thereof to a power supply Vdd.

Further, the reset Tr103is connected at the gate thereof to a pixel driving line7such that the reset pulse RST is supplied to the gate of the reset Tr103through the pixel driving line7.

The FET104is an FET for amplifying (buffering) a voltage of the FD106and is hereinafter referred to also as amplification Tr104.

The amplification Tr104is connected at the gate thereof to the FD106and is connected at the drain thereof to the power supply Vdd. Further, the amplification Tr104is connected at the source thereof to the drain of the FET105.

The FET105is an FET for selecting an output of an electric signal (VSL voltage) to the VSL8and is hereinafter referred to also as selection Tr105.

The selection Tr105is connected at the source thereof to the VSL8.

Further, the selection Tr105is connected at the gate thereof to a pixel driving line7such that a selection pulse SEL is supplied to the gate of the selection Tr105through the pixel driving lines7.

Here, the amplification Tr104is connected at the source thereof to the bias circuit120(FIG. 2) that serves as a current source through the selection Tr105and the VSL8to configure an SF (Source Follower) (circuit) from the amplification Tr104and the bias circuit120. Accordingly, the voltage of the FD106becomes a VSL voltage on the VSL8through the SF.

The FD106is a region that is formed at a connection point among the drain of the transfer Tr102, source of the FET103, and gate of the FET104and converts the charge into a voltage like a capacitor.

It is to be noted that the pixel110can be configured without the selection Tr105.

Further, as a configuration of the pixel110, a configuration (FD sharing type) of a sharing pixel in which a plurality of sets of a PD101and a transfer Tr102share the components from the reset Tr103to the FD106can be adopted.

Further, as a configuration of the pixel110, a configuration can be adopted in which the pixel110has a memory function for storing charge obtained by the PD101and can perform operation of a global shutter.

In the pixel110configured in such a manner as described above, the PD101receives incident light thereto and performs photoelectric conversion to start accumulation of electric charge corresponding to a light amount of the received incident light. It is to be noted here that, for the simplification of the description, it is assumed that the selection pulse SEL has the H level and the selection Tr105has an on state.

If predetermined time (exposure time) elapses after accumulation of electric charge into the PD101is started, then the row scanning unit3(FIG. 1) temporarily sets the transfer pulse TRF (from the L (Low) level) to the H (High) level.

Since the transfer pulse TRF temporarily becomes the H level, the transfer Tr102is temporarily placed into an on state.

When the transfer Tr102is placed into an on state, the charge accumulated in the PD101is transferred to and charged into the FD106through the transfer Tr102.

The row scanning unit3temporarily sets, before it temporarily sets the transfer pulse TRF to the H level, the reset pulse RST to the H level to temporarily place the reset Tr103into an on state.

By placing the reset Tr103into an on state, the FD106is connected to the power supply Vdd through the reset Tr103, and consequently, the charge in the FD106is swept out to the power supply Vdd through the reset Tr103to reset the charge.

Here, that the FD106is connected to the power supply Vdd to reset the charge in the FD106in such a manner as described above is resetting of the pixel110.

After the charge in the FD106is reset, the row scanning unit3temporarily sets the transfer pulse TRF to the H level as described hereinabove. Consequently, the transfer Tr102is temporarily placed into an on state.

Since the transfer Tr102is placed into an on state, the electric charge accumulated in the PD101is transferred to and accumulated into the FD106after resetting through the transfer Tr102.

The voltage (potential) corresponding to the electric charge accumulated in the FD106is outputted to the VSL8as the VSL voltage through the amplification Tr104and the selection Tr105.

In the set (FIG. 2) of the comparator140and the counter150connected to the VSL8, a reset level that is a VSL voltage immediately after resetting of the pixel110is performed is AD converted.

Further, in set of the comparator140and the counter150, a signal level (including the reset level and a level that becomes a pixel value) that is a VSL voltage (voltage accumulated in the PD101and corresponding to the charge transferred to the FD106) after the transfer Tr102is temporarily placed into an on state is AD converted.

Further, for example, in set of the comparator140and the counter150, CDS (Correlated Double Sampling) for determining the difference between an AD conversion result of the reset level (hereinafter referred to also as reset level AD value) and an AD conversion result of the signal level (hereinafter referred to also as signal level AD value) as a pixel value is performed.

It is to be noted that it is possible to perform the CDS after AD conversion of the reset level and the signal level and also possible to perform the CDS during AD conversion of the reset level and the signal level.

For example, the CDS can be performed during AD conversion of the reset level and the signal level by starting counting by the counter150as AD conversion of the signal level using, as an initial value, a complement of the count value of the counter150as an AD conversion result of the reset level.

<Outline of Operation of Image Pickup Device>

FIG. 4is a view illustrating an outline of operation of the image pickup device (FIG. 1).

It is to be noted that, inFIG. 4, the axis of abscissa represents time and the axis of ordinate represents a voltage.

FIG. 4is a waveform diagram depicting an example of the VSL voltage supplied from the pixel110to the comparator140through the VSL8and the reference signal (voltage) supplied from the reference signal generation unit130to the comparator140.

It is to be noted that, inFIG. 4, also the transfer pulse TRF supplied to (the gate of) the transfer Tr102(FIG. 3), reset pulse RST supplied to the reset Tr103, and comparator output of the comparator140are depicted together with the VSL voltage and the reference signal.

In the image pickup device, the reset pulse RST is temporarily set to the H level and, as a result, the pixel110is reset.

In the resetting of the pixel110, as described hereinabove with reference toFIG. 3, the FD106is connected to the power supply Vdd through the reset Tr103and the charge in the FD106is reset. Therefore, the VSL voltage outputted from the pixel110, namely, the VSL voltage on the VSL8in the pixel110outputted from the FD106through the amplification Tr104and the selection Tr105, increases and becomes a voltage corresponding to the power supply Vdd at time t1.

The VSL voltage maintains the voltage corresponding to the power supply Vdd within a time period within which the FD106remains connected to the power supply Vdd, and, if the reset pulse RST is thereafter set to the L level at time t2, then a little charge enters the FD106by movement of some charge in the pixel110and, as a result, the VSL voltage drops a little.

InFIG. 4, the VSL voltage drops a little from time t2, at which the reset pulse RST changes to the L level, to time t3later than time t2by movement of charge in the pixel110.

The drop of the VSL voltage that appears after resetting of the pixel110in such a manner as described above is called reset feed-though.

Thereafter, an auto zero process is performed, and the comparator140is set such that the relationship in magnitude between the VSL voltage and the reference signal can be decided (compared) with reference to that the VSL voltage and the reference signal provided to the comparator140upon the auto zero process coincide with each other.

In the auto zero process, the capacitors141and142(FIG. 2) are charged such that the voltages to be applied to the two input terminals of the comparator140become equal to each other.

As a result, (the waveform of) the reference signal is formed such that the voltage dropping by the reset feed-though from the VSL voltage while the pixel110is reset is made, as it were, a reference.

The reference signal generation circuit130raises the reference signal by a predetermined voltage at time t4after the auto zero process is completed (ended).

Here, to raise the reference signal by the predetermined voltage at time t4after the auto zero process is ended is hereinafter referred to as start offset.

Further, while the reference signal generation circuit130gradually decreases the voltage of the reference signal at a fixed rate for the AD conversion of the VSL voltage, a portion of a ramp signal in the reference signal at which the voltage decreases at the fixed rate is referred to also as slope.

The reference signal generation circuit130performs, at time t4, start offset for offsetting the reference signal by a predetermined voltage in the opposite direction to the direction of the slope (direction in which the voltage of the reference signal varies).

Thereafter, the reference signal generation circuit130gradually decreases (lowers) the voltage of the reference signal at a fixed rate within an AD conversion period of the reset level provided as a fixed period from time t5to time t7.

Accordingly, the reference signal within the period from time t5to time t7forms a slope.

The slope of the reference signal within the period from time t5to time t7is a slope for AD converting the reset level of the VSL voltage (VSL voltage of the pixel110immediately after resetting (VSL voltage after the pixel110is reset and a drop of the voltage by the reset feed-through occurs)), and the period of the slope (period from time t5to time t7) is hereinafter referred to also as P (Preset) phase. Further, the slope of the P phase is referred to also as P-phase slope.

Here, since the comparator140is set by the auto zero process after resetting of the pixel110such that the VSL voltage and (the voltage of) the reference signal upon the auto zero process coincide with each other, according to the start offset by which the reference signal is raised by the predetermined voltage at time t4after the auto zero process is ended, the reference signal becomes higher in voltage than the VSL voltage (reset level). Accordingly, the comparator output of the comparator140becomes the H level representing that the reference signal is higher than the VSL voltage at starting time t5of the P phase.

The counter150starts counting of a reference clock at a start timing of the AD conversion period of the reset level, namely, at starting time t5of the P-phase slope.

In the P phase, (the voltage of) the reference signal gradually decreases, and inFIG. 4, at time t6of the P phase, the reference signal and the VSL voltage as a reset level become coincident with each other, and the relationship in magnitude between the reference signal and the VSL voltage is reversed from that upon starting of the P phase.

As a result, the comparator output of the comparator140inverts (reverses) from the H level upon starting of the P phase to the L level.

When the comparator output of the comparator140becomes the L level, the counter150stop its counting of a reference clock and the count value of the counter150at the time becomes an AD conversion result of the reset level (reset level AD value).

After the end of the P phase, in the image pickup device, the level of the transfer pulse TRF changes from the L level to the H level and the H level is maintained for the period from time t8to time t9, and as a result, the charge accumulated in the PD101by photoelectric conversion in the pixel110(refer toFIG. 3) is transferred to and accumulated into the PD106through the transfer Tr102.

Since charge is accumulated into the PD106, the VSL voltage corresponding to the charge accumulated in the PD106drops, and when the transfer pulse TRF changes from the H level to the L level at time t9, the transfer of charge from the PD101into the PD106ends and the VSL voltage becomes a signal level (voltage) corresponding to the charge accumulated in the PD106.

Further, after the end of the P phase, the reference signal generation circuit130raises the reference signal to a voltage equal to that, for example, upon starting of the P phase.

Since the VSL voltage becomes a voltage corresponding to charge accumulated in the PD106and the reference signal rises to a voltage equal to that upon starting of the P phase as described above, the relationship in magnitude between the reference signal and the VSL voltage reverses again.

As a result, the comparator output of the comparator140becomes the H level.

After the reference signal generation circuit130raises the reference signal to a voltage equal to that upon starting of the P phase, it gradually decreases the voltage of the reference signal, for example, at a rate equal that of the variation in the case of the P phase within an AD conversion period of the signal level provided by a fixed period from time t10to time t12(the period need not be coincident with the fixed period (P phase) from time t5to time t7).

Accordingly, the reference signal within the period from time t10to time t12becomes a ramp signal and forms a slope similarly to the reference signal of the P phase from time t5to time t7.

The slope of the reference signal within the period from time t10to time t12is a slope for AD converting the signal level of the VSL voltage (VSL voltage immediately after transfer of charge from the PD101to the PD106in the pixel110(FIG. 3)), and the period of this slope (period from time t10to time t12) is hereinafter referred to also as D (Data) phase. Further, the slope of the D phase is referred to also as D-phase slope.

Here, at starting time t10of the D phase, the reference signal is higher than the VSL voltage similarly as in the case of that at starting time t5of the P phase. Accordingly, the comparator output of the comparator140becomes, at starting time t10of the D phase, the H level that indicates that the reference signal is higher than the VSL voltage.

The counter150starts counting of a clock at a starting timing of the AD conversion period of the signal level, namely, for example, at starting time t10of the D-phase slope.

In the D phase, (the voltage of) the reference signal gradually decreases, and inFIG. 4, the reference signal and the VSL voltage as the signal level become coincident with each other at time t11of the D phase and the relationship in magnitude between the reference signal and the VSL voltage reverses from that upon starting of the D phase.

As a result, also the comparator output of the comparator140reverses from the H level upon starting of the D phase to the L level.

When the comparator output reverses to the L level, the counter150ends the counting of the reference clock. Then, the count value of the counter150at the time becomes an AD conversion result of the signal level (signal level AD value).

The column signal processing unit4performs AD conversion for determining a reset level AD value in the P phase in such a manner as described above and performs AD conversion for determining a signal level AD value in the D phase, and further performs CDS for determining the difference between the reset level AD value and the signal level AD value. Then, the difference obtained as a result of the CDS is outputted as a pixel value.

It is to be noted that the counter150can execute the CDS while performing AD conversion of the P phase and the D phase.

In particular, the CDS can be performed together with AD conversion of the P phase and the D phase, for example, by performing counting as AD conversion of the P phase in the negative direction and performing counting as AD conversion of the D phase in the forward direction using a result of the counting of the P phase as an initial value.

Further, the CDS can be performed together with AD conversion of the P phase and the D phase, for example, by performing counting of the P phase in the forward direction and performing counting of the D phase in the forward direction using a complement of a counting result of the P phase (value of the counting result whose sign is changed to the negative) as an initial value.

It is to be noted that, although a reference signal whose voltage decreases with a fixed inclination in the P phase and the D phase is adopted here, as the reference signal, a signal can be adopted whose voltage increases with a fixed inclination in the P phase and the D phase.

<First Example of Configuration of Reference Signal Generation Circuit130>

FIG. 5is a circuit diagram depicting a first example of a configuration of the reference signal generation circuit130ofFIG. 2.

Referring toFIG. 5, the reference signal generation circuit130includes an operational amplifier21, FETs22,23,24, and25, a gain controlling DAC26, an FET27, a counter28, a ramp generation DAC29, an output terminal30, an input resistor RI, and a terminating resistor RO. The FETs22and25are NMOS FETs, and the FETs23,24, and27are PMOS FETs. Which one of an NMOS FET and a PMOS FET is to be used for each of the FETs can be selected suitably in accordance with a circuit configuration or the like.

Further, inFIG. 5, as controlling signals for controlling the reference signal generation circuit130, a gain controlling signal and a counter controlling signal are supplied from the system controlling unit6to the reference signal generation circuit130.

A reference voltage BGR is supplied to the non-negated input terminal (+) of the operational amplifier21. The negated input terminal (−) of the operational amplifier21is connected to one end of an input resistor RI that is connected at the other end thereof to the ground GND. The operational amplifier21is connected at an output terminal thereof to the gate of the FET22.

The FET22is connected at the drain thereof to the drain of the FET23and is connected at the source thereof to a connection point of the negated input terminal (−) of the operational amplifier21and the input resistor RI.

The FET23is connected at the gate thereof to the gate of the FET24and the drain of the FET23and is connected at the source thereof to a power supply VDD.

The FET24is connected at the source thereof to the power supply VDD and is connected at the drain thereof to the drain of the FET25.

Here, the FET23and the FET24configure a current mirror circuit. The current mirror circuit has a mirror ratio provided by a value corresponding to the ratio in size between the FETs23and24, and current (mirror current) equal to mirror ratio times the current flowing through the FE23(between the source and the drain) flows through the FET24(between the source and the drain).

The FET25is connected at the gate thereof to the drain of the FET25and the gate of a plurality of FETs41that configure the gain controlling DAC26. The FET25is connected at the source thereof to the ground GND.

The gain controlling DAC26controls the analog gain of the image pickup device ofFIG. 1, namely, the inclination of the slope of the reference signal, under the control of the system controlling unit6.

In particular, the gain controlling DAC26includes a plurality of NMOS FETs41, and switches42, whose numbers are equal to the number of FETs41.

The FETs41are connected at the gate thereof to the gate of the FET25and are connected at the drain thereof to the drain of the FET27through the switches42. The FETs41are connected at the source thereof to the ground GND.

Here, the FET25and the FETs41configure a current mirror circuit. The current mirror circuit has a mirror ratio provided by a value corresponding to the ratio in size between the FET25and the FETs41, and current equal to mirror ratio times the current flowing through the FET25flows to the FETs41.

The switches42are switched on/off in accordance with a gain controlling signal from the system controlling unit6to switch on/off the connection between the drain of the FETs41and the drain of the FET27.

In the gain controlling DAC26, if a switch42or switches42are switched on, then to an FET41or FETs41to which the switch42or switches42in an on state are connected, current equal to the mirror ratio times the current flowing through the FET25flows.

Accordingly, as the number of the switches42that indicate an on state increases, current i1that flows through the FET27to which the FETs41are connected increases, and as a result, the variation amount of current flowing to the terminating resistor RO from the ramp generation DAC29hereinafter described (equal to current corresponding to the current i1) increases.

Here, in the reference signal generation circuit130ofFIG. 5, a voltage drop of the terminating resistor RO is outputted as a reference signal from the output terminal30. As the variation amount of current flowing through the terminating resistor RO increases, the variation amount of the voltage drop of the terminating resistor RO, namely, the inclination of the slope (ramp signal) of the reference signal, increases.

As the inclination of the slope of the reference signal increases, the count value of the counter150(FIG. 2) regarding the variation of the VSL voltage, namely, the variation of the AD conversion result, decreases, and consequently, the analog gain of the image pickup device decreases.

From the foregoing, in order to decrease the analog gain of the image pickup device, the current i1to flow to the FET27is increased, and consequently, the inclination of the slope of the reference signal increases.

On the other hand, in order to increase the analog gain of the image pickup device, the current i1flowing to the FET27is decreased, and consequently, the inclination of the slope of the reference signal decreases.

The FET27is connected at the gate thereof to the drain of the FET27and the gate of a plurality of FETs51that configure the ramp generation DAC29, and is connected at the source thereof to the power supply VDD.

The counter28counts a count value (hereinafter referred to as connection number count value) as a connection number by which the FETs51hereinafter described configuring the ramp generation DAC29are connected to the output terminal30under the control of the system controlling unit6. Further, the counter28controls switches52hereinafter described, which configure the ramp generation DAC29, in accordance with the connection number count value to connect FETs51, whose numbers are equal to the connection number count value, to the output terminal30.

The ramp generation DAC29generates current for obtaining a voltage to be made a reference signal under the control of the counter28. In particular, for example, the ramp generation DAC29generates current that decreases with a fixed inclination in order to form a slope of a reference signal.

The ramp generation DAC29includes a plurality of FETs51as a plurality of current sources, and switches52, whose numbers are equal to the number of the plurality of FETs51.

Here, the number of the plurality of FETs41and switches42configuring the gain controlling DAC26and the number of the plurality of FETs51and switches52configuring the ramp generation DAC29can be determined independently of each other.

The FETs51are connected at the gate thereof to the gate of the FET27and are connected at the drain thereof to the switches52. The FETs51are connected at the source thereof to the power supply VDD.

Here, the FET27and the FETs51configure a current mirror circuit. The current mirror circuit has a mirror ratio provided by a value corresponding to the ratio in size between the FET27and the FETs51, and current equal to mirror ratio times the current i1flowing to the FET27flows to the FETs51.

The switches52select the terminal #0connected to the ground GND or the terminal #1connected to the output terminal30under the control of the counter28.

Accordingly, (the drain of) an FET51as a current source is connected to the ground GND in a case where a switch52selects the terminal #0but is connected to the output terminal30in a case where the switch52selects the terminal #1.

As described above, the FET51as a current source can select connection to the output terminal30(or connection to the ground GND) by the switch52.

Here, the sum of current supplied by the FETs51connected to the output terminal30in the ramp generation DAC29, namely, by the FETs51connected to the switch51that select the terminal #1, is referred to also as current i2.

Upon starting of the P phase and the D phase, the plurality of switches52configuring the ramp generation DAC29all select the terminal #1, and thereafter, the switches52are switched one by one or by every predetermined number equal to or greater than 2 so as to select the terminal #0as time passes until an end of the P phase and the D phase.

As a switch52is switched from the terminal #1to the terminal #0, the number of the FETs51connected to the output terminal30decreases and the current i2supplied by the ramp generation DAC29decreases.

The output terminal30is connected to the drain of the FETs51through (the terminal #1of) the switches52. Further, the output terminal30is connected to one end of the terminating resistor RO that is connected at the other end thereof to the ground GND.

Accordingly, current supplied from the FETs51connected to the output terminal30, namely, the current i2supplied by the ramp generation DAC29, flows to the terminating resistor RO connected to the output terminal30.

The voltage drop caused by the terminating resistor RO at this time is outputted as a reference signal from the output terminal30.

In the reference signal generation circuit130configured in such a manner as described above, a predetermined number of switches42in the gain controlling DAC26are switched on in accordance with a gain controlling signal.

On the other hand, current in accordance with the reference voltage BGR and the input resistor RI flows to the FET22. The current flowing through the FET22flows to the FET23, and current equal to mirror ratio times the current flowing through the FET23flows to the FET24.

The current flowing through the FET24flows to the FET25, and current equal to mirror ratio times the current flowing through the FET25flows to the FETs41connected to the switches42that are in an on state in the gain controlling DAC26.

To the FET27, current i1that is the sum of current flowing through the FETs41connected to the switches42that are on, and to the respective FETs51of the ramp generation DAC29, current equal to mirror ratio times the current i1flowing to the FET27flows.

The current i2that is the sum of current flowing to the FETs51connected to the switches52by which the terminal #1is selected from among the plurality of FETs51configuring the ramp generation DAC29flows to the terminating resistor RO connected to the output terminal30.

The voltage drop of the terminating resistor RO caused by the current i2flowing through the terminating resistor RO is outputted as a reference signal from the output terminal30.

In the ramp generation DAC29, upon starting of the P phase and the D phase, the plurality of switches52configuring the ramp generation DAC29all select the terminal #1, and thereafter, the switches52are switched, for example, one by one from the terminal #1to the terminal #0as time passes till an end of the P phase and the D phase.

If one switch52is switched from the terminal #1to the terminal #0, then the current i2decreases by the current flowing to the FET51to which the switch52is connected.

Accordingly, as the switches52are switched one by one from the terminal #1to the terminal #0, the current i2decreases by an amount of current flowing through one FET51, and as a result, the voltage drop of the terminating resistor RO as a reference signal decreases.

Consequently, a reference signal having a P-phase slope and a D-phase slope along which the voltage (level) decreases at a fixed rate is generated.

It is to be noted that, while here a reference signal whose voltage decreases at a fixed rate is generated by switching the switches52one by one from the terminal #1to the terminal #0, namely, by decreasing the number of the FETs51as power supply sources to be connected to the output terminal30, a reference signal whose voltage conversely increases at a fixed rate can otherwise be generated.

In particular, by switching the switches52, for example, one by one from the terminal #0to the terminal #1to increase the number of the FETs51as current sources to be connected to the output terminal30, a reference signal whose voltage increases at a fixed rate can be generated.

FIG. 6is a view illustrating an example of operation of the reference signal generation circuit130ofFIG. 5when the analog gain is set to a maximum value.

In order to set the analog gain to a maximum value, the switches42of the gain controlling DAC26are controlled such that the current i1flowing to the FET27is minimized.

InFIG. 6, when two switches42are switched on, the current i1corresponding to a maximum analog gain (minimum value of the current i1) is the sum of current flowing to the FETs41connected to each of the two switches42, and therefore, two switches42are on.

When the current i1has a minimum value, also the current flowing to the respective FETs51of the ramp generation DAC29has a minimum value.

Accordingly, the slope of the reference signal indicates a voltage having a gentle (small) inclination and decreasing voltage by voltage corresponding to the minimum value of current flowing through the FETs51.

It is to be noted that the FET27is configured with a size with which it operates in a saturation region when the current i1of the minimum value flows. Also the FETs51of the ramp generation DAC29are configured with a size with which they operate in a saturation region when current corresponding to the minimum value of the current i1flows.

FIG. 7is a view illustrating an example of operation of the reference signal generation circuit130ofFIG. 5when the along gain is set to a minimum value.

When the analog gain is set to a minimum value, the switches42of the gain controlling DAC26are controlled such that the current i1flowing to the FET27is maximized.

InFIG. 7, the current i1corresponding to the minimum analog gain (maximum value of the current i1) is the sum of current flowing to all of the FETs41configuring the gain controlling DAC26. Therefore, all of the switches42configuring the gain controlling DAC26are on.

When the current i1has a maximum value, also the current flowing to the respective FETs51of the ramp generation DAC29indicates a maximum value.

Accordingly, the slope of the reference signal indicates a voltage of a steep (great) inclination along which the voltage successively decreases by a voltage corresponding to the maximum value of current flowing to the FETs51.

Incidentally, if the analog gain is set to a low value in the reference signal generation circuit130, then the current i1flowing to the FET27becomes great and overdrive voltage Vdsat that is a minimum value of the drain-source voltage when the FET27operates in a saturation region becomes high. Similarly, also the overdrive voltage Vdsat of the FETs51of the ramp generation DAC29becomes high.

As the overdrive voltage Vdsat of the FET27and the FETs51becomes high, the dynamic range of the reference signal generation circuit130, and hence the dynamic range of (the slope of) the reference signal, is compressed.

<Second Example of Configuration of Reference Signal Generation Circuit130>

FIG. 8is a circuit diagram depicting a second example of a configuration of the reference signal generation circuit130ofFIG. 2.

It is to be noted that, inFIG. 8, portions corresponding to those ofFIG. 5are denoted by the same reference symbols, and in the following description, description of them is omitted suitably.

Referring toFIG. 8, the reference signal generation circuit130includes an operational amplifier21, FETs22to25, a gain controlling DAC26, an FET27, a counter28, a ramp generation DAC29, an output terminal30, a termination unit60, and an input resistor RI.

Accordingly, inFIG. 8, the reference signal generation circuit130is common to that ofFIG. 5in that it includes the components from the operational amplifier21to the output terminal30, and the input resistor RI.

However, the reference signal generation circuit130ofFIG. 8is different from that ofFIG. 5in that it includes the termination unit60in place of the terminating resistor RO.

Further, inFIG. 8, as controlling signals for controlling the reference signal generation circuit130, gain controlling signals #1and #2and a counter controlling signal are supplied from the system controlling unit6to the reference signal generation circuit130.

The gain controlling signal #1and the counter controlling signal are used to control the switch42and the counter28, respectively, similarly as in the case ofFIG. 5. The gain controlling signal #2is used to control switches61hereinafter described that configure the termination unit60.

The termination unit60includes a plurality of terminating resistors RO, and switches61, whose numbers are equal to the number of the plurality of terminating resistors RO.

Here, the number of terminating resistors RO and switches61configuring the termination unit60can be determined independently of the number of FETs41and switches42configuring the gain controlling DAC26and of the number of FETs51and switches52configuring the ramp generation DAC29.

In the termination unit60, the terminating resistors RO are connected at one end thereof to the output terminal30and at the other end thereof to the ground GND thorough the switches61.

Accordingly, the plurality of terminating resistors RO configuring the termination unit60are connected in parallel to each other through the switches61.

The switches61are configured, for example, from an NMOS FET and switches on/off in accordance with the gain controlling signal #2.

If a switch61is switched on, then the corresponding terminating resistor RO connected at one end thereof to the output terminal30is connected at the other end thereof to the ground GND through the switch61having switched on. Consequently, current of the FETs51connected to the output terminal30, namely, at least part of the current i2supplied from the ramp generation DAC29, flows to the terminating resistor RO.

Accordingly, the switches61can be considered switches that select the terminating resistors RO from which current of the FETs51as current sources connected to the output terminal30is to be supplied.

InFIG. 8, a voltage drop of the termination unit60is outputted as a reference signal from the output terminal30.

Since, in the termination unit60, as the number of the switches61that are on increases, an increased number of terminating resistors RO are connected in parallel, and therefore, the impedance of the termination unit60decreases and the voltage drop of the termination unit60decreases.

When the voltage drop of the termination unit60is small, the variation amount of the voltage drop of the termination unit60with respect to the variation of the current i2, namely, the inclination of the slope (ramp signal) of the reference signal, decreases and the analog gain increases.

On the other hand, when the voltage drop of the termination unit60is great, the variation amount of the voltage drop of the termination unit60with respect to the variation of the current i2, namely, the inclination of the slope of the reference signal, increases and the analog gain decreases.

Accordingly, by controlling the switches61to increase or decrease the number of terminating resistors RO connected in parallel to each other, the analog gain can be adjusted.

Further, in the reference signal generation circuit130ofFIG. 8, similarly as in the case ofFIG. 5, upon starting of the P phase and the D phase, the plurality of switches52configuring the ramp generation DAC29all select the terminal #1, and thereafter, the switches52are switched, for example, one by one from the terminal #1to the terminal #0as time passes till an end of the P phase and the D phase.

When one switch52is switched from the terminal #1to the terminal #0, then the current i2decreases by current that is to flow to the FET51to which the switch52is connected, and the voltage drop of the termination unit60as a reference signal decreases by the decrease of the current i2.

Consequently, a reference signal having a P-phase slope and a D-phase slope along which the voltage (level) decreases at a fixed rate is generated.

Now, the mirror ratio of the current mirror circuit configured from the FET23and the FET24is represented by MR1; the mirror ratio of the current mirror circuit configured from the FET25and the FETs41is represented by MR2; and the mirror ratio of the current mirror circuit configured from the FET27and the FETs51is represented by MR3.

In this case, (the voltage of) the reference signal VR can be represented by an expression (1).
VR=(BGR/RI)*MR1*(MR2*NGA)*(MR3*NRMP)*(RO+Rsw)/NRO(1)

NGArepresents the number of switches42that are on under the control of the gain controlling signal #1, namely, the number of FETs41through which current is flowing.

NRMPrepresents the number of the switches52by which the terminal #1is selected, namely, the number of the FETs51connected to the output terminal30.

NROrepresents the number of the switches61that are on under the control of the gain controlling signal #2, namely, the number of the terminating resistors RO connected in parallel between the output terminal30and the ground GND.

RSWrepresents the on resistance of the switches61when the switches61are on.

The step voltage of the reference signal VR represented by the expression (1), namely, the step voltage ΔVR that is a variation amount of (the voltage of) the reference signal VR when one switch52is switched, can be represented by an expression (2).
ΔVR={(BGR/RI)*MR1*(MR2*NGA)*(MR3*(NRMP+1))*(RO+Rsw)/NRO}−{(BGR/RI)*MR1*(MR2*NGA)*(MR3*NRMP)*(RO+Rsw)/NRO}=(BGR/RI)*MR1*MR2*NGA*MR3*(RO+Rsw)NRO(2)

Further, the analog gain GA of the reference signal generation circuit130ofFIG. 8can be represented by an expression (3).
GA=(NGA,0dB/NGA)*(NRO/NRO,0dB)  (3)

NGA,0dBis the number of switches42to be switched on when the analog gain is to be set to 0 dB, namely, the number of FETs41to which current is to be supplied.

NRO,0dBrepresents the number of switches61to be switched on when the analog gain is to be set to 0 dB, namely, the number of terminating resistors RO to be connected in parallel.

Here, the analog gain of the reference signal generation circuit130ofFIG. 5is represented by NGA,0dB/NGA. Accordingly, when an analog gain of the same range as that of the reference signal generation circuit130ofFIG. 5is to be implemented, the reference signal generation circuit130can suppress the difference in current (current variation width) flowing to the FETs27,41, and51by the amount of NRO/NRO,0dBof the expression (3) between the current when the analog gain is in the maximum and the current when the analog gain is in the minimum.

As a result, in a case where the analog gain is to be set to the minimum in the reference signal generation circuit130ofFIG. 8, since the current flowing to the FETs27,41, and51decreases in comparison with that in the reference signal generation circuit130ofFIG. 5, the dynamic range of the reference signal generation circuit130and hence the dynamic range of the reference signal can be secured.

Incidentally, the on resistance Rsw has an influence on both the reference signal VR of the expression (1) and the step voltage (variation amount) ΔVR of the reference signal of the expression (2).

The on resistance Rsw depends upon the PVT (Process, Voltage and Temperature). Therefore, the reference signal VR of the expression (1) and the step voltage (variation amount) ΔVR of the reference signal of the expression (2) disperse relying upon the PVT, and also a pixel value obtained by AD conversion performed using such a reference signal as just described suffers from a dispersion, and hence, the picture quality of an image obtained by the image pickup device is deteriorated.

Here, in the image pickup device (FIG. 1), as described hereinabove with reference toFIGS. 3 and 4, CDS is performed by which the difference between a reset level AD value (AD conversion result of the reset level) and a signal level AD value (AD conversion result of the signal level) is determined as a pixel value.

Accordingly, even if the reference signal VR itself is influenced by the on resistance Rsw, if the step voltage ΔVR of the reference signal is not influenced by the on resistance Rsw, then a pixel value obtained as a result of the CDS does not suffer from dispersion arising from the on resistance Rsw.

<Third Example of Configuration of Reference Signal Generation Circuit130>

FIG. 9is a circuit diagram depicting a third example of a configuration of the reference signal generation circuit130ofFIG. 2.

It is to be noted that, inFIG. 9, portions corresponding to those ofFIG. 8are denoted by the same reference symbols, and in the following description, description of them is omitted suitably.

Referring toFIG. 9, the reference signal generation circuit130includes an operational amplifier21, FETs22to25, a gain controlling DAC26, an FET27, a counter28, a ramp generation DAC29, an output terminal30, a termination unit70, and an input resistor RI.

Accordingly, inFIG. 9, the reference signal generation circuit130is common to that ofFIG. 8in that it includes the components from the operational amplifier21to the output terminal30, and the input resistor RI.

However, the reference signal generation circuit130ofFIG. 9is different from that ofFIG. 8in that it includes the termination unit70in place of the termination unit60.

The termination unit70includes a plurality of terminating resistors RO, and switches61and62, whose numbers are equal to the number of the plurality of terminating resistors RO.

Accordingly, the termination unit70is common to the termination unit60ofFIG. 8in that it includes a plurality (set) of terminating resistors RO and switches61.

However, the termination unit70is different from the termination unit60ofFIG. 8in that the switches62are provided newly.

The termination unit70is configured such that current of the FETs51that are not connected to the output terminal30from among the FETs51configuring the ramp generation DAC29and serving as a plurality of current sources is supplied to the switches61.

In particular, inFIG. 9, the terminal #0of the switches52is connected not to the ground GND but to switches62.

Further, inFIG. 9, in the termination unit70, the switches62are connected to the terminal #0of the switches52configuring the ramp generation DAC29and to each connection point between a terminating resistor RO and a switch61.

Accordingly, the switches62switch on/off the connection between the FETs51connected to the switches52by which the terminal #0is selected, namely, the FETs51serving as current sources that are not connected to the output terminal30, and the connection points between the terminating resistors RO and the switches61.

Each switch62is switched on/off in accordance with the gain controlling signal #2similarly to the switches61. Accordingly, each switch62is switched on/off in synchronism with a switch61.

In the reference signal generation circuit130configured in such a manner as described above, when a switch61in the termination unit70is switched on, a terminating resistor RO that is connected at one end thereof to the output terminal30is connected at the other end thereof to the ground GND through the switch61that is on similarly as in the case of the termination unit60ofFIG. 8.

As a result, to the terminating resistors RO that are connected to the ground GND through the switches61having an on state, current of the FETs51connected to the output terminal30from among the FETs51of the ramp generation DAC29, namely, of the FETs51connected to the switches52by which the terminal #1is selected, flows.

Here, the sum of current flowing to the terminating resistors RO connected to the ground GND through the switches61that have an on state is equal to the sum (current i2) of current of the FETs51connected to the output terminal30(FETs51connected to the switches52by which the terminal #1is selected).

Further, if attention is paid only to current of the FETs51connected to the output terminal30, then the sum of the current flowing to the switches61that are in an on state is equal to the sum (current i2) of current of the FETs51connected to the output terminal30.

On the other hand, inFIG. 9, current of the FETs51connected to the output terminal30from among the FETs51of the ramp generation DAC29, namely, of the FETs51connected to the switches52by which the terminal #0is selected, flows through the switches62that are in an on state, to the switches61, which are in an on state in synchronism with the switches62to the ground GND.

Here, if attention is paid only to current of the FETs51that are not connected to the output terminal30(FETs51connected to the switches52by which the terminal #0is selected), then the sum of current flowing to the switches61that are in an on state is equal to the sum of current of the FETs51that are not connected to the output terminal30.

As described above, if attention is paid only to current of the FETs51connected to the output terminal30, then the sum of current flowing to the switches61that are in an on state is equal to the sum of current of the FETs51connected to the output terminal30(current i2). Further, if attention is paid only to current of the FETs51that are not connected to the output terminal30, then the sum of current flowing to the switches61that are in an on state is equal to the sum of current of the FETs51that are not connected to the output terminal30.

Accordingly, the sum of current flowing to the switches61that are in an on state is equal to the sum of current to all of the plurality of FETs51configuring the ramp generation DAC29and is fixed. As a result, the voltage drop caused by the switches61that are in an on state is fixed irrespective of the number NRMof the FETs51connected to the output terminal30(number of the FETs51connected to the switches52by which the terminal #1is selected).

Here, adjustment of the analog gain of the reference signal generation circuit130ofFIG. 9and operation for generation of a reference signal having a P-phase slope and a D-phase slope along which the voltage (level) decreases at a fixed rate are similar to those in the case ofFIG. 8, and therefore, description of them is omitted.

Since, in the reference signal generation circuit130ofFIG. 9, the sum of current flowing to the switches61that are in an on state is normally equal to the sum of current through all of the plurality of FETs51configuring the ramp generation DAC29, the reference signal VR outputted from the output terminal30can be represented by an expression (4).
VR=(BGR/RI)*MR1*(MR2*NGA)*MR3*(NRMP*RO+NRMP,all*Rsw)/NRO(4)

NRMP,allrepresents the total number of the FETs51configuring the ramp generation DAC29.

The step voltage of the reference signal VR represented by the expression (4), namely, the step voltage ΔVR of the reference signal VR when one switch52is switched can be represented by an expression (5).
ΔVR={(BGR/RI)*MR1*(MR2*NGA)*MR3*((NRMP+1)*RO+NRMP,all*Rsw)/NRO}−{(BGR/RI)*MR1*(MR2*NGA)*MR3*(NRMP*RO+NRMP,all*Rsw)/NRO}=(BGR/RI)*MR1*MR2*NGA*MR3*RO/NRO(5)

Meanwhile, the analog gain GA of the reference signal generation circuit130ofFIG. 9can be represented by an expression (6) similar to the expression (3).
GA=(NGA,0dB/NGA)*(NRO/NRO,0dB)  (6)

Accordingly, in the reference signal generation circuit130ofFIG. 9, the difference in current (current variation width) flowing to the FETs27,41, and51can be suppressed by NRO/NRO,0dBof the expression (6) between the current when the analog gain is in the maximum and the current when the analog gain is in the minimum similarly as in the case ofFIG. 8. As a result, the dynamic range of the reference signal generation circuit130, and hence, the dynamic range of the reference signal, can be secured.

Further, in the reference signal generation circuit130ofFIG. 9, although the on resistance Rsw has an influence on the reference signal VR of the expression (4), the on resistance Rsw does not have an influence on the step voltage ΔVR of the reference signal of the expression (5).

As described above, in the reference signal generation circuit130ofFIG. 9, since the on resistance Rsw does not have an influence on the step voltage ΔVR of the reference signal, a pixel value obtained as a result of the CDS is not dispersed arising from the on resistance Rsw. Accordingly, deterioration of the picture quality of an image obtained by the image pickup device arising from that the on resistance Rsw disperses depending upon the PVT can be prevented.

It is to be noted that each switch61can be configured, for example, from an NMOS FET as described hereinabove. Switching on of an FET as the switch61can be performed by applying, for example, the power supply voltage VDD to the gate of the FET. In this case, when the FET switches on as the switch61, the gate-source voltage of the FET is kept fixed and does not vary depending upon the magnitude of the voltage of the reference signal. Accordingly, the on resistance Rsw of the FET as the switch61does not vary depending upon the magnitude of the reference signal.

From the foregoing, although (the voltage of) the reference signal VR of the expression (4) is influenced by the on resistance Rsw, the on resistance Rsw does not vary depending upon the magnitude of the voltage of the reference signal VR.

Accordingly, the reference signal generation circuit130ofFIG. 9can prevent the linearity of the reference signal VR (that the slope varies at a fixed rate) from being damaged by a variation of the on resistance Rsw by the magnitude of the voltage of the reference signal VR. In other words, the linearity of the reference signal VR can be assured. This similarly applies also to the reference signal generation circuit130ofFIG. 8.

<Fourth Example of Configuration of Reference Signal Generation Circuit130>

FIG. 10is a circuit diagram depicting a fourth example of a configuration of the reference signal generation circuit130ofFIG. 2.

It is to be noted that, inFIG. 10, portions corresponding to those ofFIG. 9are denoted by the same reference symbols, and in the following description, description of them is omitted suitably.

Referring toFIG. 10, the reference signal generation circuit130includes an operational amplifier21, FETs22to25, a gain controlling DAC26, an FET27, a counter28, a ramp generation DAC29, an output terminal30, a termination unit80, and an input resistor RI.

Accordingly, inFIG. 10, the reference signal generation circuit130is common to that ofFIG. 9in that it includes the components from the operational amplifier21to the output terminal30, and the input resistor RI.

However, the reference signal generation circuit130ofFIG. 10is different from that ofFIG. 9in that it includes the termination unit80in place of the termination unit60.

The termination unit80includes a plurality of terminating resistors RO, and switches81and82, whose numbers are equal to the number of the plurality of terminating resistors RO.

Here inFIG. 10, in order to simplify the description, the termination unit80has, for example, four terminating resistors RO as the plurality of terminating resistors RO. It is to be noted that the number of terminating resistors RO is not limited to four.

As described above, inFIG. 10, since the termination unit80has the four terminating resistors RO, it includes four switches81and82the number of which is equal to the number of terminating resistors RO.

In the termination unit80, the four terminating resistors RO as the plurality of terminating resistors RO are connected in series. Further, the four terminating resistors RO connected in series are connected at one end thereof to the output terminal30and at the other end thereof to the ground GND.

Here, in the termination unit80, each of the terminating resistors RO forms a set together with a switch81and a switch82.

In the following description, the terminating resistor RO that is ith in a direction from the output terminal30toward the ground GND from among the four terminating resistors RO connected in series in the termination unit80is referred to merely as ith terminating resistor RO. Further, switches81and82that form a set together with the ith terminating resistor RO are individually referred to also as ith switches81and82.

The ith switch81switches on/off the connection between one end of the ith terminating resistor RO on the ground GND side and the ground GND in accordance with a gain controlling signal #2from the system controlling unit6.

The ith switch82switches on/off the connection between the connection point between the ith terminating resistor RO and the switch81and the terminal #0of the switch52configuring the ramp generation DAC29in accordance with a gain controlling signal #2from the system controlling unit6.

Here, the switches81and82that form a set with the terminating resistor RO are switched on/off in synchronism with each other in accordance with the gain controlling signal #2.

Further, among the switches81and82of the four sets as the plurality of sets, only the switches81and82of one set are switched on while the switches81and82of the other sets are switched off in accordance with the gain controlling signal #2.

In the reference signal generation circuit130configured in such a manner as described above, if (only) the ith switches81and82are switched on in the termination unit80, then the sum of current supplied from the FETs51connected to the switches52by which the terminal #1is selected (FETs51connected to the output terminal30) flows through the first to ith terminating resistors RO and the ith switch81to the ground GND.

In the reference signal generation circuit130ofFIG. 10, the voltage drop caused by the first to ith terminating resistors RO and the ith switch81is outputted as a reference signal from the output terminal30. Accordingly, as the switches81and82of a set nearer to the output terminal30are switched on, the inclination (of the slope) of the reference signal outputted from the output terminal30decreases and the analog gain increases.

From the foregoing, the reference signal generation circuit130can perform adjustment of the analog gain by switching on only the switches81and82of one set from among the switches81and82of the four sets as the plurality of sets.

Here, if (only) the ith switches81and82in the termination unit80is switched on, then the sum (current i2) of current supplied from the FETs51connected to the switches52by which the terminal #1is selected (FETs51connected to the output terminal30) flows through the first to ith terminating resistors RO and the ith switch81to the ground GND.

Accordingly, if attention is paid only to the current of the FETs51connected to the output terminal30, then the sum of current flowing to the ith switch81that is in an on state is equal to the sum (current i2) of current of the FETs51connected to the output terminal30.

On the other hand, inFIG. 10, current of the FETs51not connected to the output terminal30from among the FETs51of the ramp generation DAC29, namely, of the FETs51connected to the switches52by which the terminal #0is selected flows through the ith switch82that is in an on state to the ith switch81that is on in synchronism with the switch82and then flows into the ground GND.

Accordingly, if attention is paid only to the FETs51not connected to the output terminal30(FETs51connected to the switches52by which the terminal #0is selected), then the sum of current flowing to the ith switch81that is in an on state is equal to the sum of current of the FETs51that are not connected to the output terminal30.

As described above, if attention is paid only to the current of the FETs51connected to the output terminal30, then the sum of current flowing to the ith switch81that is in an on state is equal to the sum (current i2) of the FETs51connected to the output terminal30. Further, if attention is paid only to the current of the FETs51not connected to the output terminal30, then the sum of current flowing to the ith switch81that is in an on state is equal to the sum of current of the FETs51that are not connected to the output terminal30.

Accordingly, the sum of current flowing to the ith switch81that is in an on state is normally equal to the sum of current of all of the plurality of FETs51that configure the ramp generation DAC29and is fixed. As a result, the voltage drop caused by the ith switch81that is in an on state is fixed irrespective of the number NRMof FETs51connected to the output terminal30(number of FETs51connected to the switches52by which the terminal #1is selected).

Here, operation of the reference signal generation circuit130ofFIG. 10for generation of a reference signal having a P-phase slope and a D-phase slope along which the voltage (level) decreases at a fixed rate is similar to that in the case ofFIG. 8, and therefore, description of the operation is omitted.

Since, in the reference signal generation circuit130ofFIG. 10, the sum of current flowing to the switches81that are in an on state is normally equal to the sum of current of all of the plurality of FETs51configuring the ramp generation DAC29, the reference signal VR outputted from the output terminal30can be represented by an expression (7).
VR=(BGR/RI)*MR1*(MR2*NGA)*MR3*(NRMP*RO*NRO′+NRMP,all*Rsw)   (7)

NRO′ represents what numbered switch the switch81(and82) that is in an on state under the control of the gain controlling signal #2is, namely, the number of terminating resistors RO through which the current i2of the ramp generation DAC29flows.

The step voltage of the reference signal VR represented by the expression (7), namely, the step voltage ΔVR of the reference signal VR when one switch52is witched, can be represented by an expression (8).
ΔVR={(BGR/RI)*MR1*(MR2*NGA)*MR3*((NRMP+1)*RO*NRO′+NRMP,all*RSW)}−{(BGR/RI)*MR1*(MR2*NGA)*MR3*(NRMP*RO*NRO′+NRMP,all*Rsw)}=(BGR/RI)*MR1*MR2*NGA*MR3*RO*NRO(8)

Meanwhile, the analog gain GA of the reference signal generation circuit130ofFIG. 10can be represented by an expression (9).
GA=(NGA,0dB/NGA)*(NRO′/NRO,0dB)  (9)

Accordingly, the reference signal generation circuit130ofFIG. 10can suppress the difference in current flowing to the FETs27,41, and51by the amount of NRO′/NRO,0dBof the expression (9) between the current when the analog gain is in the maximum and the current when the analog gain is in the minimum. As a result, the dynamic range of the reference signal generation circuit130, and hence the dynamic range of the reference signal, can be secured.

Further, in the reference signal generation circuit130ofFIG. 10, although the on resistance Rsw has an influence on the reference signal VR of the expression (7), the on resistance Rsw does not have an influence on the step voltage ΔVR of the reference signal of the expression (8).

As described above, in the reference signal generation circuit130ofFIG. 10, since the on resistance Rsw does not have an influence on the step voltage ΔVR of the reference signal, a pixel value obtained as a result of the CDS does not suffer from a dispersion arising from the on resistance Rsw. Accordingly, deterioration of the picture quality of an image obtained by the image pickup device arising from that the on resistance Rsw disperses depending upon the PVT can be prevented.

<Fifth Example of Configuration of Reference Signal Generation Circuit130>

FIG. 111is a circuit diagram depicting a fifth example of a configuration of the reference signal generation circuit130ofFIG. 2.

It is to be noted that, inFIG. 11, portions corresponding to those ofFIG. 10are denoted by the same reference symbols, and in the following description, description of them is omitted suitably.

Referring toFIG. 11, the reference signal generation circuit130includes an operational amplifier21, FETs22to25, a gain controlling DAC26, an FET27, a counter28, a ramp generation DAC29, an output terminal30, a termination unit90, and an input resistor RI.

Accordingly, inFIG. 11, the reference signal generation circuit130is common to that ofFIG. 10in that it includes the components from the operational amplifier21to the output terminal30, and the input resistor RI.

However, the reference signal generation circuit130ofFIG. 11is different from that ofFIG. 10in that it includes the termination unit90in place of the termination unit60.

Further, inFIG. 11, the switches52configuring the ramp generation DAC29are different from those in the case ofFIG. 10in which the terminal #0is connected to the switches82in that the terminal #0is connected to the ground GND similarly as in the cases ofFIGS. 5 and 8.

The termination unit90includes a plurality of terminating resistors RO, and switches91and92, whose numbers are equal to the number of the plurality of terminating resistors RO.

Here inFIG. 11, in order to simplify the description, the termination unit90has, for example, four terminating resistors RO as the plurality of terminating resistors RO similarly as inFIG. 10. It is to be noted that the number of terminating resistors RO is not limited to four.

As described above, inFIG. 11, since the termination unit90has the four terminating resistors RO, it includes four switches91and92the number of which is equal to the number of terminating resistors RO.

In the termination unit90, the four terminating resistors RO as the plurality of terminating resistors RO are connected in series, and the four terminating resistors RO connected in series are connected at one end thereof to the ground GND.

Here, in the termination unit90, each of the terminating resistors RO forms a set together with a switch91and a switch92.

In the following description, the terminating resistor RO that is ith in a direction toward the ground GND from among the four terminating resistors RO connected in series in the termination unit90is referred to merely as ith terminating resistor RO. Further, a switch91and a switch92that form a set together with the ith terminating resistor RO are individually referred to also as ith switches91and92.

The ith switches91and92are connected in series and switch on/off in synchronism with each other in accordance with a gain controlling signal #2from the system controlling unit6.

The ith switches91and92connected in series are connected at one end thereof to the terminal #1of a switch52configuring the ramp generation DAC29and at the other end thereof to the output terminal30.

Further, a connection point between the ith switches91and92connected in series is connected to one of the opposite ends of the ith terminating resistor RO, which is a farther end from the ground GND.

Here, among the switches91and92of the four sets as the plurality of sets, only the switches91and92of one set are switched on while the switches91and92of the other sets are switched off in accordance with the gain controlling signal #2.

In the reference signal generation circuit130configured in such a manner as described above, if (only) the ith switches91and92are switched on in the termination unit90, then current i2of the ramp generation DAC29, namely, the sum of current supplied from the FETs51connected to the switches52by which the terminal #1is selected (FETs51connected to the output terminal30) flows through the ith switch91and the ith to fourth terminating resistors RO and then flows into the ground GND.

In the reference signal generation circuit130ofFIG. 11, the voltage drop caused by the ith to fourth4-i+1 terminating resistors RO is outputted as a reference signal from the output terminal30. Accordingly, as the switches91and92of a set nearer to the output terminal30are switched on, the inclination (of the slope) of the reference signal outputted from the output terminal30increases and the analog gain decreases.

From the foregoing, the reference signal generation circuit130inFIG. 11can perform adjustment of the analog gain by switching on only the switches91and92of one set from among the switches91and92of the four sets as the plurality of sets.

Further, in the reference signal generation circuit130ofFIG. 11, since the voltage drop caused by the ith to fourth4-i+1 terminating resistors RO is outputted as a reference signal from the output terminal30as described above, the reference signal is not influenced by the on resistance Rsw of the switches91or92.

Accordingly, since the on resistance Rsw does not have an influence on the step voltage of the reference signal (variation amount (of the voltage) of the reference signal when one switch52is switched) either, a pixel value obtained as a result of the CDS does not suffer from a dispersion arising from the on resistance Rsw. As a result, deterioration of the picture quality of an image obtained by the image pickup device arising from that the on resistance Rsw disperses depending upon the PVT can be prevented.

Further, in the reference signal generation circuit130ofFIG. 11, the difference in current flowing to the FETs27,41, and51between the current when the analog gain is in the maximum and the current when the analog gain is in the minimum can be suppressed similarly as in the cases ofFIGS. 8 to 10. As a result, the dynamic range of the reference signal generation circuit130, and hence the dynamic range of the reference signal, can be secured.

It is to be noted that operation of the reference signal generation circuit130ofFIG. 11for generation of a reference signal having a P-phase slope and a D-phase slope along which the voltage (level) decreases at a fixed rate is similar to that in the case ofFIG. 8, and therefore, description of the operation is omitted.

<Example of Use of Image Pickup Device>

FIG. 12is a view depicting an example of use in which the image pickup device ofFIG. 1is used.

The image pickup device described hereinabove can be used, for example, in various electronic apparatus in which light such as visible rays, infrared rays, ultraviolet rays, and X rays is sensed as described below.Electronic apparatus by which an image that is provided for viewing is picked up such as a digital camera or a portable apparatus with a camera functionElectronic apparatus provided for traffic such as automotive sensors for image pickup of the front, the rear, the surroundings, the inside and so forth of an automobile for safe driving such as automatic stopping, recognition of a state of the driver and so forth, a security camera for monitoring a traveling vehicle or the road, a distance measurement sensor for measuring the distance between vehicles and so forthElectronic apparatus provided for consumer electronics such as a TV, a refrigerator, or an air conditioner for picking up an image of a gesture of a user to perform apparatus operation in accordance with the gestureElectronic apparatus provided for medical or health care use such as an endoscope, an electronic microscope, or an apparatus that performs angiography by reception of infrared raysElectronic apparatus provided for use for security such as a surveillance camera for security use or a camera for people authentication purposeElectronic apparatus for use for beauty such as a skin measuring instrument for picking up an image of the skin or a microscope for picking up an image of the scalpElectronic apparatus provided for use for sports such as an action camera or a wearable camera for sports applications and so forthElectronic apparatus provided for agricultural use such a camera for monitoring the state of a field or crops

<Digital Camera to which Image Pickup Device is Applied>

FIG. 13is a block diagram depicting an example of a configuration of an embodiment of a digital camera that is one of electronic apparatus to which the image pickup device ofFIG. 1is applied.

The digital camera can pick up an image of both a still picture and a moving picture.

Referring toFIG. 13, the digital camera includes an optical system401, an image pickup device402, a DSP (Digital Signal Processor)403, a frame memory404, a recording apparatus405, a display apparatus406, a power supply system407, an operation system408, and a bus line409. In the digital camera, the components from the DSP403to the operation system408are connected to each other through the bus line409.

The optical system401collects light from the outside on the image pickup device402.

The image pickup device402is configured similarly to the image pickup device ofFIG. 1, and receives and photoelectrically convers light from the optical system401, and outputs image data as an electric signal.

The DSP403performs signal processing necessary for image data outputted from the image pickup device402.

The frame memory404temporarily stores image data, for which the signal processing has been performed by the DSP403, in a unit of a frame.

The recording apparatus405records image data of a still picture or a moving picture picked up by the image pickup device402into a recording medium such as a semiconductor memory or a hard disk.

The display apparatus406is configured from a panel type display apparatus such as, for example, a liquid crystal panel or an organic EL (Electro Luminescence) panel or the like and displays an image (moving picture or still picture) corresponding to image data stored in the frame memory404.

The power supply system407supplies necessary power to the components from the image pickup device402to the display apparatus406and the operation system408.

The operation system408outputs an operation instruction for various functions the digital camera has in accordance with an instruction by the user.

It is to be noted that the embodiment of the present technology is not limited to the embodiment described above and various changes can be made without departing from the subject matter of the present technology.

In particular, the present technology can be applied to an image pickup device that adopts, in addition to column AD conversion by which AD conversion of a pixel signal of a pixel110simultaneously for all columns, area AD conversion by which, for example, the pixels110are separated into a plurality of areas and AD conversion of an image signal of a pixel110is performed simultaneously for the all areas.

Further, the advantageous effects described in the present specification are only examples and not limitative of the present technology, and there may be some other advantageous.

It is to be noted that the present technology can have the following configurations.

An image pickup device including:

a pixel having a photoelectric conversion device that performs photoelectric conversion and configured to output an electric signal;

a reference signal generation unit configured to generate a reference signal having a level that varies;

a comparison unit configured to compare the electric signal and the reference signal with each other; and

a counting unit configured to perform AD (Analog to Digital) conversion of the electric signal by performing counting of a count value in response to a result of the comparison between the electric signal and the reference signal, in which

the reference signal generation unit includesa plurality of current sources whose connection to an output terminal for outputting the reference signal is selectable,a plurality of terminating resistors connected to the output terminal, anda plurality of switches configured to select the terminating resistors that are to supply current of the current sources that are connected to the output terminal, and

the reference signal generation unit is configured so as to supply current of the current sources that are not connected to the output terminal to the switches.

The image pickup device according to <1>, in which

the switches are connected in series to the terminating resistors, and,

when any of the switches is switched on, current of the current source connected to the output terminal flows through the terminating resistor connected to the switch.

The image pickup device according to <2>, in which

current of the current sources that are not connected to the output terminal is supplied to the switches connected to the terminating resistors to which current of the current sources connected to the output terminal flows.

The image pickup device according to <2> or <3>, further including:

a different switch configured to switch on/off connection of the current sources that are not connected to the output terminal to a connection point between the terminating resistors and the switches;

the different switch being switched on/off in synchronism with the switches.

The image pickup device according to any one of <1> to <4>, in which,

as the number of the current sources connected to the output terminal increases or decreases, the level outputted from the output terminal varies.

An electronic apparatus including:

an optical system configured to collect light; and

an image pickup device configured to receive the light to pick up an image, in which

the image pickup device includesa pixel having a photoelectric conversion device that performs photoelectric conversion and configured to output an electric signal,a reference signal generation unit configured to generate a reference signal having a level that varies,a comparison unit configured to compare the electric signal and the reference signal with each other, anda counting unit configured to perform AD (Analog to Digital) conversion of the electric signal by performing counting of a count value in response to a result of the comparison between the electric signal and the reference signal,

the reference signal generation unit includesa plurality of current sources whose connection to an output terminal for outputting the reference signal is selectable,a plurality of terminating resistors connected to the output terminal, anda plurality of switches configured to select the terminating resistors that are to supply current of the current sources that are connected to the output terminal, and

the reference signal generation unit is configured so as to supply current of the current sources that are not connected to the output terminal to the switches.

REFERENCE SIGNS LIST