Apparatus and methods for limiting surges in load current

Apparatus and methods related to limiting surge current are provided. An under-voltage condition on a node is sensed and respective signals are provided in response. The under-voltage condition correlates to a surge in load current drawn from the node. A foldback signal is provided to a power controller to adjust the voltage on the node. The foldback signal is nullified when the surge current condition has been curtailed. Printers, computers and other apparatus can include surge current-limiting accordingly.

BACKGROUND

Printers, computers and other apparatus require electrical energy in order to perform their respective normal functions. Surges in electrical current consumption of such an apparatus can occur as a result of circuit faults, overloads, temperature-related variances, and other factors. Evolving rule and law in this area mandate systems and methods that respond quickly to curtail electrical surges in the interest of energy conservation, device protection and other considerations. The present teachings address the foregoing and related concerns.

DETAILED DESCRIPTION

Introduction

The Apparatus and methods related to limiting surge currents within printer, computers and other devices are provided. An under-voltage condition on a node is sensed, and respective signals are provided in response. The under-voltage condition correlates to a surge in load current drawn from that node. A foldback signal is generated and provided to a power controller so as to adjust the voltage on the node. The foldback signal is nullified when the surge current condition has been curtailed. Various apparatus can include surge current-limiting circuitry or methodology according to the present teachings.

In one example, an electronic circuit is configured to detect an under-voltage condition at a power output node, and to provide an undervolt signal in accordance with the detecting. The electronic circuit is also configured to provide a hold-track signal that is derived by way of the undervolt signal, and to provide a peak level signal by way of sampling a voltage correspondent to a load current. The electronic circuit is also configured to provide a foldback signal in accordance with a comparison of the hold track signal with the peak-level signal. The electronic circuit is configured to couple the foldback signal to a current sensing input of a power controller, so as to limit a surge in the load current.

In another example, a method includes generating an undervolt signal in response to sensing an under-voltage condition at an electrical node. The method also includes generating a hold-track signal by way of the undervolt signal. The method additionally includes generating a peak level signal by way of sampling a voltage correspondent to a load current. The method further generating a foldback signal in accordance with a comparison of the hold track signal with the peak-level signal. The foldback signal is characterized so as to cause a power controller to adjust a voltage at the electrical node.

First Illustrative Embodiment

An embodiment of surge current-limiting circuitry (circuitry) according to the present teachings is now described. Such circuitry is shown by way ofFIGS. 2-7, collectively.FIG. 1is block schematic diagram100depicting the overall cooperative relationship of the circuitry depicted inFIGS. 2-7. Other embodiments of surge current-limiting circuitry can also be used in accordance with the present teachings.

With reference toFIG. 1, a source of twelve volt direct-current energy (source)102is provided and an output of twenty-four volt energy104is derived there from. The output104is also referred to as a power output node104for purposes herein. Such derivation (or generation) is performed by way of a switching-type voltage-boost power controller as depicted inFIG. 5. The other circuitry, as collectively represented byFIGS. 2-4and6-7, perform respective functions in accordance with the present teachings.

With reference toFIG. 2, an under-voltage detection circuit (UV circuit)200according to the present teachings is depicted. The UV circuit200includes an operational amplifier (i.e., op-amp) configured to operate as a comparator202. The comparator202is connected to twelve volt direct-current (DC) energy at a node204and to ground potential at a node206. In one non-limiting example, the comparator202is defined by a model LM358 op-amp, as available from Texas Instruments Incorporated, Dallas, Tex., USA. Other suitable op-amps or comparators can also be used. A capacitor224filters the voltage at the node204.

The comparator202is coupled to a reference of five volts potential at a node208by way of a resistor210and a filter capacitor212. In one non-limiting example, the resistor210is 100 K-Ohms in value, and the capacitor212is 0.1 microfarads in value, respectively. Other respective values can also be used. The comparator202is also coupled to the node104by way of respective resistors216and218. In one non-limiting example, the resistor216is 30 K-Ohms in value, and the resistor218is 11 K-Ohms in value, respectively. Other respective values can also be used. The resistors216and218are connected to define a voltage divider that derives a signal at a node220that is of lesser voltage than that at the power output node104.

The node104provides twenty-four volts potential under normal operating conditions. The UV circuit200operates to detect an under-voltage condition on the node104by way of comparing the voltage at the node208with that at the node220. An undervolt signal (24 V-UV) is provided (or asserted) at a node222(“A”) in response to detecting such an under-voltage condition at the power output node104.

Referring now toFIG. 3, a hold-track circuit (HT circuit)300according to the present teachings is depicted, The HT circuit300includes an operational amplifier op-amp) configured to operate as an integrator302. In one non-limiting example, the integrator302is defined by a model LM358 op-amp, as available from Texas Instruments. Other suitable op-amps can also be used. The integrator302is connected to reference signal (REF) at a node304.

The integrator302is coupled to the undervolt signal at the node222by way of a resistor306, a diode308, a resistor310and a capacitor312. In one non-limiting example, the resistor306is 1 K-Ohm in value, the diode308is a model 1N914 silicon small-signal diode, the resistor310is 100 K-Ohm in value and the capacitor312is 1.0 microfarad in value. Other suitable component values or definitions can also be used for elements306-312, respectively.

The integrator302is also coupled to receive a bias voltage derived by a voltage divider defined by a resistor314and a resistor316. In one non-limiting example, the resistor314is 330 K-Ohm in value and the resistor316is 22 K-Ohm in value. Other suitable resistors314or316can also be used. A parallel combination of a resistor318and capacitor320define a feedback circuit for the integrator302.

During normal operation, the undervolt signal at node222is coupled to the capacitor312by way of the diode308. The capacitor312stores a charge corresponding to a most recent peak value in the undervolt signal which, in the absence of new undervolt signal input at the node222, decays over time toward the bias voltage value by way of resistors310,314and316. Thus, a time constant is defined for the HT circuit300. In turn, a signal derived from the undervolt signal at node222is compared with the reference voltage at node304and a resulting signal is time-integrated to define an output from the integrator302. The output is coupled to a node324by way of a resistor322, defining a hold-track (H-T) signal. In one non-limiting example, the resistor322is 360 K-Ohm in value. Other resistors values can also be used.

Reference is now made toFIG. 4, which depicts a foldback circuit400according to the present teachings. The foldback circuit400includes an operational amplifier (i.e., op-amp) configured to operate as a comparator402. The comparator402is connected to twelve volt direct-current (DC) energy at the node204and to ground potential at the node206. A capacitor404functions to filter the voltage at the node204. In one non-limiting example, the comparator402is defined by a model LM358 op-amp, as available from Texas Instruments. Other suitable op-amps or comparators can also be used.

The comparator402is coupled to receive the H-T signal at the node324. A capacitor406and a resistor408couple the node324to ground potential at node206. In one non-limiting example, the capacitor406is 0.01 microfarads in value and the resistor408is 7.5 K-Ohm in value. Other suitable values can also be used. The foldback circuit400also includes a transistor410configured to operate as a switch according to a driving signal (DRV) at a node412, by way of a resistor414. In one non-limiting example, the transistor410is a model 2N7002 N-channel enhancement mode MOSFET, as available from Fairchild Semiconductor, San Jose, Calif., USA, while the resistor414is 100.0-Ohm in value. Other suitable components or values can also be used.

The transistor410is coupled to the comparator402by way of a resistor416and a resistor418and a capacitor420and a resistor422and a capacitor424. In one non-limiting example, the resistor416is 100.0-Ohm in value, the resistor418is 100 K-Ohm in value, the capacitor420is 0.1 microfarads in value, the resistor422is 1.0 M-Ohm in value and the capacitor424is 1.0 microfarads in value. Other suitable values can also be used. The capacitor424and the resistor422are configured to define a time constant for the foldback circuit400.

The foldback circuit400also includes a resistor426electrically connected to both circuit ground potential at node206, and power buss ground potential at a node428. Another resistor430couples the resistor426to a current sensing (CS+) node432. The power controller represented inFIG. 5senses a voltage corresponding to load current by way of the CS+ node432. In one non-limiting example, the resistor426is 0.01-Ohm in value and the resistor430is 30.0-Ohm in value. Other suitable values can also be used. In an optional example, a resistor434is also connected between the node432and ground potential at node206.

The foldback circuit400further includes a transistor436and a resistor438and a light-emitting diode (LED)440and a resistor442, collectively configured to define a constant-current circuit444. In one non-limiting example, the transistor436is a model 2N3904 bipolar transistor, as available from Fairchild Semiconductor, while the resistor438is 100 K-Ohm in value, the LED440has a forward voltage of about 1.8 volts DC at 5.0 milli-amperes, and the resistor442is 270.0-Ohm in value. Other suitable components or values can also be used.

Typical normal operations of the foldback circuit400are as follows: load current (e.g., to a print engine, a computer circuit card, or other) is sensed as a voltage at the CS+ node432. A pulse-width modulated (PWM) DRV signal at the node412is provided by the power controller ofFIG. 5. The transistor410is triggered by the DRV signal to provide voltage pulses corresponding to peak-level load-current values to the comparator402by way of the elements416-424, inclusive. Thus, the load current through resistor426is sampled at (about) peak-level instances and a corresponding voltage signal is present across the capacitor424. Concurrently, the HT signal at node324is provided to the comparator402by way of the elements406-408, inclusive.

The comparator402compares the HT signal and the peak-level signal and provides a resulting output to the constant-current circuit444. The constant-current circuit444derives a foldback signal450that is coupled to the CS+ node432. The general result is that the current sense signal at node432is biased toward a greater voltage value, in response to detecting a surge in load current by way of an under-voltage condition on the power output node104.

The power controller (FIG. 5) responds to the increased voltage at the CS+ node432by causing a decrease in the voltage present at the power output node104. Thus, a negative feedback control loop is defined, and surges in load current are limited or curtailed in accordance with the present teachings.

Attention is now directed toFIG. 5, which depicts a block diagram of a power controller500. The power controller500is illustrative and non-limiting with respect to the present teachings. Other power controllers, related or peripheral circuitry, and so on can also be used.

In one non-limiting example, the power controller500includes or is defined by a model MAX668 step-up PWM boost controller, as available from Maxim Integrated Products, Sunnyvale, Calif., USA. Other suitable power controllers or integrated circuits can also be used.

The power controller500provides a reference voltage output at the REF node304introduced above. In one example, the voltage at the node304is about 1.250 volts DC. The power controller500senses load-current input at the CS+ node432introduced above. The power controller also provides a PWM transistor drive-signal at the DRV node412introduced above. The power controller500also provides a low-dropout regulation (LDO) signal at a node502. In one example, the voltage at the LDO node502is about 5.0 volts DC.

During typical normal operation, the power controller500provides the PWM signal at the DRV node412to a transistor of a switching-type voltage-boost circuit504. In turn, the power controller500senses load current at the node CS+ node432by way of a current sense resistor of the circuit504.

An inductor of the circuit504is coupled to twelve volts DC power at a node506as provided the switch circuit ofFIG. 7. PWM control of the circuit504modulates current flow through the inductor, resulting in twenty-four volts DC potential at the power output node104. The power controller500is also coupled to circuitry in accordance with the present teachings as depicted byFIGS. 2,3,4,6and7, inclusive, and responds to the respective signals provided there from so as to limit surge current to a load.

Attention is now turned toFIG. 6, which depicts a disable circuit600according to the present teachings. The disable circuit600includes an operational amplifier (i.e., op-amp) configured to operate as a comparator602. The comparator602is connected to twelve volts DC at the node204and to ground potential at the node206. In one non-limiting example, the comparator602is defined by a model LM358 op-amp, as available from Texas Instruments. Other suitable op-amps or comparators can also be used.

The comparator602is coupled to sense the voltage at the node204by way of voltage divider defined by a resistor604and a resistor606. In one non-limiting example, the resistor604is 12 K-Ohm in value and the resistor606is 11 K-Ohm in value. Other suitable values can also be used. The comparator602is also coupled to sense the voltage at the LDO node502by way of a resistor608. In one example, the resistor608is 10 K-Ohm in value. Other resistive values can also be used.

The disable circuit600includes a resistor610coupled to define a positive-feedback pathway between an output and a non-inverting input of the comparator602. Thus, the disable circuit600is characterized by hysteresis during normal operation. In one example, the resistor610is 330 K-Ohm in value. Other values can also be used. The disable circuit600further includes a transistor612configured to operate as a switch in accordance with an output signal of the comparator602. In one non-limiting example, the transistor612is defined by a model 2N7002 N-channel enhancement mode MOSFET, as available from Fairchild Semiconductor. Other suitable transistors can also be used.

The comparator602compares the voltage divider signal to the LDO signal at the node502. When the voltage at node204decreases below a lesser threshold value (e.g., 10.3 volts DC), the comparator602output causes the transistor612to pull the REF node304to (or toward) ground potential. In turn, the power controller500responds to a (near) ground potential at the node304by ceasing the provision of twenty-four volts potential to the power output node104.

When the voltage at the node204increases above a greater threshold value (e.g., 11.3 volts DC), the comparator602causes the transistor to essentially switch off, allowing the REF node304to return to normal voltage (e.g., 1.250 volts DC). The power controller500responds to the voltage at the node304by returning to normal operations, providing twenty-four volts (nominal) potential to the power output node104. Thus, the disable circuit600causes a disabling of output from the power controller500in response to an under-voltage condition at the node204.

Reference is now made toFIG. 7, which depicts a switch circuit700in accordance with the present teachings. The switch circuit700includes a transistor702configured to couple (i.e., switch) a twelve volt source of electrical energy at the node102to an output node506. In one non-limiting example, the transistor702is defined by a model NTD4806, as available from ON Semiconductor, Phoenix, Ariz., USA. The transistor702is coupled to be biased into an electrically conductive (“on”) state by way of resistor704coupled to the power output node104.

The switch circuit700also includes a resettable fuse706. In one non-limiting example, the resettable fuse706is defined by a positive temperature-coefficient device model Polyswitch RXE Series 0.75A, as available from Tyco Electronics Corporation, Menlo Park, Calif., USA. Other suitable models can also be used. The resettable fuse706is coupled between the nodes102and506, in parallel circuit relationship with the transistor702. The resettable fuse706carries essentially all electrical current flow from the node102to the node506when the transistor702is biased into an electrically non-conductive (“off”) state, as described below. Otherwise, the resettable fuse706carries little or no current when the transistor702is biased “on”.

The switch circuit700also includes a transistor708coupled to the node222by way of resistor710. In one non-limiting example, the transistor is a model 2N7002 as available from Fairchild Semiconductor, and the resistor710is 1 K-Ohm in value. Other suitable models or values can also be used. The transistor708is configured to bias the transistor702into a non-conductive state when the 24 V-UV signal at node222is asserted, and to have essentially no effect on the transistor702otherwise.

Generally, the switch circuit700is configured to couple source potential from the node102to the node506by way of the transistor702when the power output node104is at about normal potential. Conversely, the switch circuit700is configured to bias the transistor702“off” when the undervolt signal at the node222is asserted, such that the resettable fuse706performs a protective, current-limiting function.

The switch circuit also includes a transistor712coupled between ground node206and a thermal (THERM) node714. The transistor712can be defined by a model 2N7002 available from Fairchild Semiconductor. Other suitable transistors can also be used. The transistor712is coupled to the 24 V-UV signal at the node222by way of a resistor716. In one non-limiting example, the resistor716is 100 K-Ohms in value. Other suitable values can also be used.

The transistor712is configured to pull the THERM node714to (or toward) ground potential when the 24 V-UV signal is asserted, and to have essentially no effect on the node714otherwise. The THERM node714provides a signal that is asserted “low” when the 24 V-UV signal is asserted “high”, which can be used for any suitable purpose not germane to the present teachings.

Illustrative Printer

Reference is now directed toFIG. 8, which depicts block diagram of a printer800. The printer800is illustrative and non-limiting in nature. Other printers, devices, apparatus and systems are contemplated by the present teachings.

The printer800includes a print controller802. The print controller802is configured to control numerous normal operations of the printer800. The print controller802can be defined by or include any constituency including, without limitation, a processor, a microcontroller, an application-specific integrated circuit (ASIC), a state machine, digital or analog or hybrid circuitry, and so on. One having ordinary skill in the printer control or related arts is familiar with printer controllers and further elaboration on the print controller802is not germane to the present teachings.

The printer800also includes a print engine804. The print engine804is configured to form images on media806in accordance with electronic signaling from the print controller802. In one example, the print engine804includes an ink jetting print head. Other print engines are also contemplated. The printer800also includes a power supply808configured to receive line-level voltage810from, for example, a utility source and to provide one or more outputs of regulated DC electrical energy. The power supply can be variously defined, and specific elaboration thereon is not germane to the present teachings.

The printer800also includes a power controller812configured to receive an electrical energy input814of from the power supply808, and to provide an electrical energy output816of at a voltage greater than that at the input814. In one non-limiting example, the power controller812is configured to receive twelve volts DC at the input814and to provide twenty-four volts DC at the output816. Other voltage combinations can also be used. As depicted, the print engine804operates by way of the electrical energy provided at output (or node)816.

The printer800also includes other resources818, which can include, without limitation, a user interface, network communications circuitry, wireless resources, optical scanning capability, an electronic display, and so on. Other constituents or elements can also be included within the other resources818. One having ordinary skill in the printing or related arts is familiar with resources and features of various printing apparatus, and further elaboration is not needed for an understanding of the present teachings.

The printer800also includes surge current (SCL)820. The SCL820can be defined by any electronic circuit (or plurality of cooperative circuits) consistent with the present teachings. In one non-limiting example, the SCL820is collectively defined by the respective circuits100,200,300,400,600and700, inclusive, as described above. Other circuitry can also be used.

The SCL820is configured to sense at least the respective voltages at the input814and the output816, and to affect the operation of the power controller812in response to under-voltage conditions, surges in load current (e.g., to the print engine804), and so on. In particular, the SCL820is configured to detect a surge in load current and cause the power controller804to decrease the voltage at the output816by way of foldback signaling. The SCL820can perform other functions consistent with the present teachings, as well.

The printer800is just one illustrative example of an apparatus including surge current limiting according to the present teachings. Other apparatus that can include surge current limiting such as computers, file servers, network communications devices and so on are also contemplated by the present teachings.

Illustrative Method

Reference is now made toFIG. 9, which depicts a flow diagram of a method according to another example of the present teachings. The method ofFIG. 9includes particular steps and proceeds in a particular order of execution. However, it is to be understood that other respective methods including other steps, omitting one or more of the depicted steps, or proceeding in other orders of execution can also be used. Thus, the method ofFIG. 9is illustrative and non-limiting with respect to the present teachings. Reference is also made toFIGS. 1-7in the interest of understanding the method ofFIG. 9.

At900, an under-voltage condition is detected on a twenty-four volt node. For purposes of a present example, the under-voltage detection circuit200detects an under-voltage condition (i.e., below threshold) on the power output node104and provides an undervolt signal (i.e., 24 V-UV) at the node222. The under-voltage condition is understood to be caused by a surge in load current.

At902, a hold-track signal is provided to a foldback comparator. For purposes of the present example, the undervolt signal at the node222is compared to the reference voltage (i.e., REF) at the node304, resulting in the hold-track (i.e., H-T) signal at the node324. The node324is coupled to a comparator402of the foldback circuit400.

At904, the hold-track signal is compared with a current peak-sampling signal. For purposes of the present example, a voltage signal corresponding to sampled peak-level load current values are compared to the hold-track signal by the comparator402. In particular, the peak-level voltage signal is present across the capacitor424of the foldback circuit400.

At906, a foldback signal is provided to the power controller in accordance with the comparison. In the present example, the comparator402provides an output to the constant-current circuit444according to the comparison of the peak-level signal and the hold-track signal. The constant-current circuit444provides (or derives) the foldback signal450accordingly. The foldback signal450is coupled to the current sense input node432, causing the power controller500to reduce voltage at the power output node104.

At908, it is determined if the surge current condition is still present. If yes, then the method returns to step902above and the hold-track signal continues accordingly. If no, then the method proceeds to step910below.

At910, the foldback signal is nullified and the surge current limiting circuitry ceases its active operating mode. For purpose of the present example, the undervolt signal at node222is de-asserted, resulting in a de-assertion of the hold-track signal at the node324“high”. In turn, the foldback comparator402provides a reduced output signal. The resulting decrease in the foldback signal450has essentially no effect by way of the current sense node432, and the power controller500returns to (or toward) normal, twenty-four volt output at the power output node104. Surge current being drawn from the power output node104is this limited or curtailed. In one example, effective limiting operations occur in five seconds or less. Other performance values can also be used.

The method described above results in limiting or curtailing surge current being drawn from the power output node104. In one example, effective limiting operations occur in five seconds or less. Other performance values can also be used. The immediately foregoing method is described as a sequence of discrete steps in the interest of clarity. However, it is to be understood that methods or circuits of the present teachings can operate in a very rapid, essentially contemporaneous manner.

Another Illustrative Method

Attention is turned now toFIG. 10, which depicts a flow diagram of a method according to another example of the present teachings. The method ofFIG. 10includes particular steps and proceeds in a particular order of execution. However, it is to be understood that other respective methods including other steps, omitting one or more of the depicted steps, or proceeding in other orders of execution can also be used. Thus, the method ofFIG. 10is illustrative and non-limiting with respect to the present teachings. Reference is also made toFIGS. 1-7in the interest of understanding the method ofFIG. 10.

At1000, an under-voltage condition is detected on a twelve volt node. For purposes of a present example, an under-voltage condition at the node204is detected by a comparator602. An output from the comparator602drives a transistor612into conduction, pulling a reference signal (i.e., REF) at a node304“low”—that is, toward ground potential.

At1002, a power controller is disabled. For purposes of the present example, the “low” signal at the node304causes the power controller500to cease voltage-boosting operations. Specifically, the power controller500halts generation of twenty-four volts at the power output node104by ceasing operation of the switching-type voltage-boost circuit504.

At1004, it is determined if the under-voltage condition is still present. If yes, then the method returns to step1002above and the power controller disable signal continues to be provided. If no, then the method proceeds to step1006below.

At1006, the power controller is re-enabled. For purposes of the present example, the comparator602detects that the under-voltage condition on node204is no longer present, and ceases to bias the transistor612into conduction. In response, the REF signal at node304returns to normal (e.g., 1.250 volts). In turn, the power controller500assumes normal operations, causing the voltage-boost circuit504to provide twenty-four volts DC at the power output node104.

The immediately foregoing method is described as a sequence of discrete steps in the interest of clarity. However, it is to be understood that methods or circuits of the present teachings can operate in a very rapid, essentially contemporaneous manner.

In general and without limitation, the present teachings contemplate electronic circuitry (a circuit or circuits) that effect the operation of a power controller so as to curtail or limit surges in load current. The respective circuits200,300,400,600and700are depicted and described individually in the interest of clarity. It is to be understood that any number, or all, of these circuits can be suitably combined to define one or more overall circuits, or that such combination(s) can be defined by integrated circuits.