Passive optical network (PON) synchronization and clock recovery

An ONU is provided. The ONU comprises a receiver configured to receive a first PON frame from an OLT, the first PON frame comprising a first PSBd field, the first PSBd field comprising a first PSync field, the first PSync field comprising first bits, and a first quantity of the first bits being greater than 64 bits; and a processor coupled to the receiver and configured to perform synchronization of the first PON frame by matching the first bits to a pre-stored sequence.

TECHNICAL FIELD

The disclosed embodiments relate to optical networks in general and PON synchronization and clock recovery in particular.

BACKGROUND

Optical networks are networks that use optical signals to carry data. Light sources such as lasers generate optical signals. Modulators modulate the optical signals with data to generate modulated optical signals. Various components transmit, propagate, amplify, receive, and process the modulated optical signals. Optical networks may implement multiplexing to achieve high bandwidths. Optical networks implement data centers, metropolitan networks, PONs, long-haul transmission systems, and other applications.

SUMMARY

A first aspect relates to an ONU, the ONU comprising: a receiver configured to receive a first PON frame from an OLT, the first PON frame comprising a first PSBd field, the first PSBd field comprising a first PSync field, the first PSync field comprising first bits, and a first quantity of the first bits being greater than 64 bits; and a processor coupled to the receiver and configured to perform synchronization of the first PON frame by matching the first bits to a pre-stored sequence.

In a first implementation form of the ONU according to the first aspect as such, the receiver further configured to receive a second PON frame, the second PON frame comprising a second PSBd field and the second PSBd field comprising a second PSync field, the second PSync field comprising second bits, a second quantity of the second bits being greater than 64 bits, and the processor being further configured to perform synchronization of the second PON frame by matching the second bits to the pre-stored sequence.

In a second implementation form of the ONU according to the first aspect as such or any preceding implementation form of the first aspect, the receiver further configured to: receive the first PON frame at a first time; and receive the second PON frame at a second time, a time interval between the first time and the second time being a multiple of a PON cycle period.

In a third implementation form of the ONU according to the first aspect as such or any preceding implementation form of the first aspect, the first quantity is 128 bits.

In a fourth implementation form of the ONU according to the first aspect as such or any preceding implementation form of the first aspect, the first quantity is 192 bits.

In a fifth implementation form of the ONU according to the first aspect as such or any preceding implementation form of the first aspect, the matching requires a maximum number of (K) to be greater than 10.

In a sixth implementation form of the ONU according to the first aspect as such or any preceding implementation form of the first aspect, the matching requires K to be less than 30.

In a seventh implementation form of the ONU according to the first aspect as such or any preceding implementation form of the first aspect, the pre-stored sequence comprises a first sub-sequence and a second sub-sequence.

In an eighth implementation form of the ONU according to the first aspect as such or any preceding implementation form of the first aspect, the second sub-sequence is an inverted form of the first sub-sequence.

In a ninth implementation form of the ONU according to the first aspect as such or any preceding implementation form of the first aspect, the first PON frame is a downstream PON frame.

In a tenth implementation form of the ONU according to the first aspect as such or any preceding implementation form of the first aspect, the processor is further configured to perform clock recovery using the pre-stored sequence.

A second aspect relates to a method implemented by an ONU, the method comprising: receiving a first PON frame from an OLT, the first PON frame comprising a first PSBd, the first PSBd comprising a first PSync field, the first PSync field comprising first bits, and a first quantity of the first bits being greater than 64 bits; and performing synchronization of the first PON frame by matching the first bits to a pre-stored sequence.

In a first implementation form of the method according to the second aspect as such, the method further comprises: receiving a second PON frame, the second PON frame comprising a second PSBd field and the second PSBd field comprising a second PSync field, the second PSync field comprising second bits, a second quantity of the second bits being greater than 64 bits; and performing synchronization of the second PON frame by matching the second bits to the pre-stored sequence.

In a second implementation form of the method according to the second aspect as such or any preceding implementation form of the second aspect, the method further comprises: receiving the first PON frame at a first time; and receiving the second PON frame at a second time, a time interval between the first time and the second time being a multiple of a PON cycle period.

In a third implementation form of the method according to the second aspect as such or any preceding implementation form of the second aspect, the first quantity is 128 bits.

In a fourth implementation form of the method according to the second aspect as such or any preceding implementation form of the second aspect, the first quantity is 192 bits.

In a fifth implementation form of the method according to the second aspect as such or any preceding implementation form of the second aspect, the matching requires a maximum number of allowed error bits (K) to be greater than 10.

In a sixth implementation form of the method according to the second aspect as such or any preceding implementation form of the second aspect, the matching requires K to be less than 30.

In a seventh implementation form of the method according to the second aspect as such or any preceding implementation form of the second aspect, the pre-stored sequence comprises a first sub-sequence and a second sub-sequence.

In an eighth implementation form of the method according to the second aspect as such or any preceding implementation form of the second aspect, the second sub-sequence is an inverted form of the first sub-sequence.

In a ninth implementation form of the method according to the second aspect as such or any preceding implementation form of the second aspect, the first PON frame is a downstream PON frame.

In a tenth implementation form of the method according to the second aspect as such or any preceding implementation form of the second aspect, the processor is further configured to perform clock recovery using the pre-stored sequence.

A third aspect relates to an OLT, the OLT comprising: a processor configured to generate a PON frame comprising a PSBd field, the PSBd field comprising a PSync field, a SFC structure field, and a PON-ID structure field, the PSync field comprising first bits, a first quantity of the first bits being greater than 64 bits, the SFC structure field comprising a superframe counter field and a first HEC field, and the PON-ID structure field comprising a PON-ID field and a second HEC field; and a transmitter coupled to the processor and configured to transmit the PON frame to an ONU.

In a first implementation form of the OLT according to the third aspect as such, the SFC structure field is 8 bytes, the PON-ID structure field is 8 bytes, the superframe counter field is 51 bits, the first HEC field is 13 bits, the PON-ID field is 51 bits, and the second HEC field is 13 bits.

A fourth aspect relates to a method implemented by an OLT, the method comprising: generating a PON frame comprising a PSBd field, the PSBd field comprising a PSync field, a SFC structure field, and a PON-ID structure field, the PSync field comprising first bits, a first quantity of the first bits being greater than 64 bits, the SFC structure field comprising a superframe counter field and a first HEC field, and the PON-ID structure field comprising a PON-ID field and a second HEC field; and transmitting the PON frame to an ONU.

Any of the above embodiments may be combined with any of the other above embodiments to create a new embodiment. These and other features will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims.

DETAILED DESCRIPTION

The following abbreviations apply:

BER: bit error rate

CO: central office

CPU: central processing unit

DSP: digital signal processor

HEC: hybrid error control

ODN: optical distribution network

OLT: optical line terminal

ONT: optical network terminal

ONU: optical network unit

PON: passive optical network

PSBd: DS physical synchronization block

PSBu: US physical synchronization block

PSync: physical synchronization sequence

RF: radio frequency

RX: receiver unit

SRAM: static RAM

TX: transmitter unit

FIG. 1is a schematic diagram of a PON100. The PON100comprises an OLT110, ONUs120, and an ODN130that couples the OLT110to the ONUs120. The PON100is a communications network that may not require active components to distribute data between the OLT110and the ONUs120. Instead, the PON100may use passive optical components in the ODN130to distribute data between the OLT110and the ONUs120.

The OLT110communicates with another network and the ONUs120. Specifically, the OLT110is an intermediary between the other network and the ONUs120. For instance, the OLT110forwards data received from the other network to the ONUs120and forwards data received from the ONUs120to the other network. The OLT110comprises a transmitter and a receiver. When the other network uses a network protocol that is different from the protocol used in the PON100, the OLT110comprises a converter that converts the network protocol to the PON protocol and vice versa. The OLT110is typically located at a central location such as a CO, but it may also be located at other suitable locations.

The ODN130is a data distribution network that comprises optical fiber cables, couplers, splitters, distributors, and other suitable components. The components include passive optical components that do not require power to distribute signals between the OLT110and the ONUs120. The ODN130extends from the OLT110to the ONUs120in a branching configuration as shown, but the ODN130may be configured in any other suitable P2MP configuration.

The ONUs120communicate with the OLT110and customers, and can act as intermediaries between the OLT110and the customers. For instance, the ONUs120forward data from the OLT110to the customers, and the ONUs120also forward data from the customers to the OLT110. The ONUs120comprise optical transceivers that receive optical signals from the OLT110, convert the optical signals into electrical signals, and provide the electrical signals to the customers. The transceivers also receive electrical signals from the customers, convert the electrical signals into optical signals, and transmit the optical signals to the OLT110. ONUs120and ONTs are similar, and the terms may be used interchangeably. The ONUs120are typically located at distributed locations such as customer premises, but they may also be located at other suitable locations.

FIG. 2is a schematic diagram of a typical PSBd200in an XG-PON. When the PON100implements an XG-PON, the OLT110transmits the PSBd200to the ONUs120to perform synchronization. The PSBd200comprises a PSBd field210. The PSBd field210comprises a PSync field220of 8 bytes, an SFC structure field230of 8 bytes, and a PON-ID structure field240of 8 bytes. Thus, the PSBd field210has commonly been only 24 bytes in length. The PSync field220therefore comprises a fixed pattern of N=64 bits. The SFC structure field230comprises a superframe counter field250of 51 bits and an HEC field260of 13 bits. The PON-ID structure field240comprises a PON-ID field270of 51 bits and an HEC field280of 13 bits.

FIG. 3is a DS ONU synchronization state machine300. The DS ONU synchronization state machine300comprises a hunt state310, a pre-sync state320, a sync state330, and a re-sync state340. An ONU120begins in the hunt state310. From the hunt state310, the ONU120proceeds to the pre-sync state320, the sync state330, or the re-sync state340, or the ONU120proceeds back to the hunt state310. The ONU120does so based on matching of the PSync field220in the PSBd200to a pre-stored sequence and based on verification of the SFC structure field230in the PSBd200. M is a counter indicating a maximum number of consecutive PSync field220match failures and SFC structure field230verification failures. In an XG-PON, M=3. An initial synchronization stage corresponds to the hunt state310, the pre-sync state320, and the sync state330. A tracking stage corresponds to the sync state330and the re-sync state340.

Currently, the PON100may implement an XG-PON using the PSBd200and the DS ONU synchronization state machine300. As mentioned above, typical values of N=64 and M=3 can be used for an XG-PON. In addition, the ONUs120determine a PSync field220match failure based on K, a maximum number of allowed error bits in PSync field220matching, and based on Pe, a BER reference level. In an XG-PON, typical values of K=2 and Pe=1e−3can be used. With N=64, M=3, K=2, and Pe=1e−3, the probability of the ONUs120missing a synchronization or having a false synchronization is greater than 5e−14. That probability corresponds to an average of about 80 years between ONU120synchronization failures, which is an acceptable time.

In the future, the PON100may implement a 50G-PON using a new PSBd and the downstream ONU synchronization state machine300. The 50G-PON will use advanced signal processing such as LDPC, which will allow the ONUs120to operate at a higher BER reference level of Pe=2e−2. However, if values of N=64, M=3, K=2 were employed as in an XG-PON, along with the Pe=2e−2, then the probability of the ONUs120missing a synchronization or having a false synchronization in the 50G-PON is greater than 2e−11. That probability corresponds to an average of about 0.2 years between synchronization failures, which is not an acceptable time. There is therefore a desire for a PSync field that provides more reliable synchronization.

Disclosed herein are embodiments for PON synchronization and clock recovery. The embodiments comprise a PSync field that provides more reliable synchronization. The PSync field in embodiments disclosed herein allows for a variably-sized field, with N values greater than N=64 bits. The PSync field in embodiments disclosed herein has a larger length N. For instance, in example embodiments, values of N=128 bits or N=192 bits can be employed. Because N is larger in the embodiments herein, then the ONUs may determine PSync field match failures based on a higher value of K. In one example, the PSync field according to any of the embodiments herein results in greatly reduced synchronization failures, such as synchronization failures occurring at intervals of only about 39.5 years to 17,400 years. In addition, the PSync field according to any of the embodiments herein may implement inverted and repeating sequences to maintain computational capacity and thus conserve power. Finally, the ONUs may use the PSync field to perform clock recovery.

FIG. 5is a schematic diagram of a PON frame500. The PON frame500may implement the DS PON frames, such as in step410ofFIG. 4. The PON frame500comprises a PSBd510and a payload520. The PSBd510facilitates synchronization in the ONUs120as described below. The payload520comprises data intended for users of the ONUs120. The PON frame500is typically about 125 μs long, which corresponds to a PON cycle time.

FIG. 6is a schematic diagram of a PSBd600in a 50G-PON according to an embodiment of the disclosure. The PSBd600may implement the PSBd510inFIG. 5. The PSBd600is similar to the PSBd200inFIG. 2. Specifically, the PSBd600comprises a PSBd field610similar to the PSBd field210. The PSBd field610comprises a PSync field620, an SFC structure field630, and a PON-ID structure field640similar to the PSync field220, the SFC structure field230, and the PON-ID structure field240, respectively. The SFC structure field630comprises a superframe counter field650and an HEC field660similar to the superframe counter field250and the HEC field260, respectively. The PON-ID structure field640comprises a PON-ID field670and an HEC field680similar to the PON-ID field270and the HEC field280, respectively. However, unlike the PSync field220inFIG. 2, which has a fixed and predefined length N=64 bits (8 bytes), in the embodiment ofFIG. 6the PSync field620has an increased length N′. As a result, the PSBd field610has an increased PSBd field610length X, allowing the PSync field length N to also be increased. Consequently, the PSBd field610length X according to the disclosed embodiments comprises an integer greater than 24, such as X=(24+8) bytes=32 bytes (or 256 bits), or X=(24+16) bytes=40 bytes (or 320 bits). In some embodiments, the PSync field620comprises a length N′ of N′=16 bytes (128 bits). When the PSync field620comprises a length N′ of N′=16 bytes, then the PSBd field610length X=16+16=32 bytes. In other embodiments, the PSync field620comprises a length N′ of N′=24 bytes (192 bits). When the PSync field620comprises a length N′ of N′=24 bytes, then the PSBd field610length X=24+16=40 bytes. It should be understood that other or additional PSync field lengths can be employed.

To increase the time between ONU synchronization failures in a 50G-PON, at least two changes may be made. First, the OLT110increases the PSync field620length N′, which is enabled by increasing the PSBd field610length X For instance, N′=9, 10, . . . , 30 bytes. The SFC structure field630and the PON-ID structure field640together occupy a fixed 16 bytes (or 128 bits). Therefore, if N′>8 bytes (i.e. N′=16 or 24 bytes), then the PSBd field610length X will be greater than 24 bytes. For instance, the PSBd field610length X can comprise X=25, 26, . . . , 46 bytes. In a first embodiment, the PSBd field610length X comprises X=32 bytes where the PSync field620length N′ comprises N′=16 bytes (128 bits). In a second embodiment, the PSBd field610length X comprises X=40 bytes where the PSync field620length N′ comprises N′=24 bytes (192 bits).

Second, the ONUs120increase the value of K. Specifically, K>2. For instance, K =3, 4, . . . , 30. In a first embodiment, 10<K<30. In a second embodiment, 15<K<25. In a third embodiment, K is determined based on its approximate value where a first curve corresponding to a probability of a missed synchronization intersects with a second curve corresponding to a probability of a false synchronization such that the probability of the missed synchronization is about the same as the probability of the false synchronization. In a fourth embodiment, K is determined based on its approximate value where a third curve corresponding to a number of years between missed synchronizations intersects with a fourth curve corresponding to a number of years between false synchronizations such that the number of years between missed synchronizations is about the same as the number of years between false synchronizations. In this context, the approximate value of K may be its value rounded down or rounded up to the nearest whole number. When the PSync field620length N′=16 bytes (128 bits), and assuming M=3 and Pe=5e−2, that intersection occurs when K=22 during the initial synchronization stage and when K=19 during the tracking stage. The higher K values are possible because of the higher PSBd length X values, and thus higher PSync field620length values N′, allowing for the ONUs120to receive more bits of the PSync field620in error.

In an example, N=16 bytes (128 bits), K=22 in the initial synchronization stage, and K=19 in the tracking stage. Even assuming a relatively high Pe=5e−2, the PSync field620provides for an acceptable time between ONU120synchronization failures. Specifically, the ONUs120would have missed synchronizations an average of every 417 years in the initial synchronization stage and an average of every 17,400 years in the tracking stage. In addition, the ONUs120would have false synchronizations an average of every 39.5 years in the initial synchronization stage and an average of every 3,430 years in the tracking stage. Thus, the PSync field620according to any of the embodiments herein provides for more reliable synchronization.

FIGS. 7A-7Dare schematic diagrams of PSync fields that may implement the PSync field620ofFIG. 6.FIG. 7Ais a schematic diagram of a PSync field700according to a first embodiment of the disclosure. The PSync field700comprises a first sub-sequence705and a second sub-sequence710. The first sub-sequence705comprises a sequence S, and the second sub-sequence710comprises an inverted sequence S, denoted as ˜S. For instance, if S is a binary sequence101, then ˜S is a binary sequence 010.

FIG. 7Bis a schematic diagram of a PSync field715according to a second embodiment of the disclosure. The PSync field715comprises a first sub-sequence720and a second sub-sequence725. The first sub-sequence720comprises ˜S, and the second sub-sequence725comprises S.

FIG. 7Cis a schematic diagram of a PSync field730according to a third embodiment of the disclosure. The PSync field730comprises a first sub-sequence735, a second sub-sequence740, and a third sub-sequence745. The first sub-sequence735comprises S, the second sub-sequence740comprises ˜S, and the third sub-sequence745comprises S.

FIG. 7Dis a schematic diagram of a PSync field750according to a fourth embodiment of the disclosure. The PSync field750comprises a first sub-sequence755, a second sub-sequence760, and a third sub-sequence765. The first sub-sequence755comprises ˜S, the second sub-sequence760comprises S, and the third sub-sequence765comprises ˜S.

S may be a Gold sequence or an m-sequence, which are known in the art. By using S and ˜S, and by repeating the S or the ˜S in various patterns, the ONUs120may need to implement only a correlator of S or only a correlator of ˜S instead of a correlator for both S and ˜S. Thus, the OLT110may increase the PSBd length X and therefore also increase the length N′ of the PSync field620without the ONUs120needing to increase their computational capacity. Maintaining the same amount of computational capacity conserves power. In an embodiment, S is 64 bits long, so the PSync fields700,715are N′=64 X 2=16 bytes (128 bits) and the PSync fields730,750are N′=64 X 3=24 bytes (192 bits).

In a first alternative, the PSync field620has more than three fields. In a second alternative, all of the fields in the PSync field620are the same. For instance, a first field and a second field are both S, or the first field and the second field are both ˜S.

Returning toFIG. 4, at step420, the OLT110transmits a signal stream. The signal stream comprises the DS PON frames from step410. At step430, an ONU120obtains a PSync field for each DS PON frame. The PSync fields may be the PSync field620.

At step440, the ONU120performs synchronization of each DS PON frame. The ONU120does so by implementing the DS ONU synchronization state machine300and using the PSync field620from each DS PON frame. Specifically, the ONU120matches bits of the PSync field620to a pre-stored sequence. The ONU120stores the pre-stored sequence at least before the ONU120receives the PON frame500. The pre-stored sequence is the same as the PSync field620when originally transmitted by the OLT110. For instance, when the PSync field620is the PSync field730or750, the ONU120performs the matching by performing a 3-tap L-Bit spaced sum, where L is a positive integer.

At step450, the ONU120performs clock recovery. The clock recovery aligns the clock of the ONU120with the clock of the OLT110. The ONU120performs clock recovery as shown or at another suitable time. For instance, the ONU120performs clock recovery when the ONU120joins the PON100.FIG. 8further describes step450.

FIG. 8is a clock recovery state machine800according to an embodiment of the disclosure. The clock recovery state machine800may implement step450inFIG. 4. The clock recovery state machine800comprises an initial search state810, a pull-in state820, and a tracking state830. The ONU120begins in the initial search state810.

In the initial search state810, the ONU120implements an algorithm to detect a first synchronization correlation peak. The synchronization correlation peak occurs when the PSync field620matches a pre-stored sequence. The algorithm is described below. The ONU120uses a relatively high threshold to reduce the likelihood of a false detection. For example, the threshold level may be set as twice a mean level of correlator outputs. When the ONU120detects the first synchronization correlation peak, the ONU120moves to the pull-in state820.

In the pull-in state820, the ONU120implements the algorithm to detect a second synchronization correlation peak in a search window next to the first synchronization correlation peak. A maximum pull-in range determines the size of the search window. The ONU120estimates a clock frequency offset from the first synchronization correlation peak and the second synchronization correlation peak. The ONU120uses the clock frequency offset to adjust a VCXO. When the VCXO settles, the ONU120moves to the tracking state830.

In the tracking state830, the ONU120narrows the search window to reduce a false detection. For example, the ONU120may narrow the search window to be about twice the PSync period.

FIG. 9is a flowchart illustrating a method900of synchronization word detection according to an embodiment of the disclosure. The method900may implement the algorithm in the clock recovery state machine800. At step910, a cross-correlation (r) between a synchronization word and a received signal is calculated, where r is an N-point cross-correlation. The synchronization word is an N-point sequence, for instance a Gold sequence, with suitable auto-correlation properties that produce a relatively high synchronization peak. At step920, ravgis obtained using a sliding window mean operation. The sliding window is a 128-point sliding window or a 256-point sliding window, for example. At step930, a synchronization detection threshold (T) is set. Finally, at step940, a synchronization correlation peak is detected when r(n) >T*ravg(n), where n is an index of received waveform samples.

FIG. 10is a schematic diagram of a US PON frame1000according to an embodiment of the disclosure. The US PON frame1000may implement the US PON frames generated in step460inFIG. 4. The US PON frame1000in this example embodiment comprises a PSBu1010and a payload1020. The US PSBu1010may be similar to the DS PSBd510inFIG. 5. The US PSBu1010facilitates synchronization in the OLT110. The payload1020comprises data from users of the ONUs120. The US PON frame1000is 125 μs long.

Returning toFIG. 4, at step470the ONU120transmits bursts to the OLT110. The bursts comprise the US PON frames from step460.

FIG. 11is a flowchart illustrating a method1100of synchronization according to an embodiment of the disclosure. At step1110, a first PON frame is received in an ONU from an OLT. The first PON frame comprises a first PSBd. The first PSBd comprises a first PSync field, the first PSync field comprises first bits, and a first quantity of the first bits is greater than 64 bits. The first PON frame may be a DS PON frame transmitted from the OLT110to the ONU120. For instance, an ONU120receives the PON frame500comprising the PSync field620as described above. At step1120, synchronization of the first PON frame is performed by matching the first bits to a pre-stored sequence. For instance, the ONU120performs synchronization as described for step440inFIG. 4.

A second DS PON frame may be received. The second DS PON frame may comprise a second PSBd, the second PSBd may comprise a second PSync field, the second PSync field may comprise second bits, and a second quantity of the second bits may be greater than 64 bits. Synchronization of the second PON frame may be performed by matching the second bits to the pre-stored sequence. The first PON frame and the second PON frame may form part of a signal stream. The first PON frame may be further received at a first time. The second PON frame may be further received at a second time. A time interval between the first time and the second time may be a multiple of a PON cycle period. The PON cycle period may be 125 μs.

The first quantity may be 128 bits. Alternatively, the first quantity may be 192 bits. However, other PSync field lengths N′ are contemplated and are within the scope of the description and claims. The matching may require K to be greater than 10. The matching may require K to be less than 30. The matching may require K to be its approximate value where a probability of a missed synchronization is about the same as a probability of a false synchronization.

The matching may comprise cross-correlation. The cross-correlation may be based on a T-spaced waveform, where T is a modulation symbol period. The cross-correlation may be based on a T/2-spaced waveform.

The pre-stored sequence may be a Gold sequence. The pre-stored sequence may be an m-sequence. The pre-stored sequence may comprise a first sub-sequence and a second sub-sequence. The second sub-sequence may be an inverted form of the first sub-sequence.

Clock recovery may be performed using the pre-stored sequence. The clock recovery may comprise an initial search state. The clock recovery may further comprise a pull-in state. The clock recovery may further comprise a tracking state.

FIG. 12is a flowchart illustrating a method1200of synchronization according to another embodiment of the disclosure. At step1210, a DS PON frame comprising a PSBd field is generated. The PSBd field comprises a PSync field, an SFC structure field, and a PON-ID structure field. The PSync field comprises first bits. A quantity of the first bits is greater than 64 bits. The SFC structure field comprises a superframe counter field and a first HEC field. The PON-ID structure field comprises a PON-ID field and a second HEC field. For instance, the OLT110generates the PON frame500as described for step410inFIG. 4. At step1220, the DS PON frame is transmitted to an ONU. For instance, the OLT110transmits the PON frame to the ONU120as described for step420inFIG. 4.

The SFC structure field may be 8 bytes. The PON-ID structure field may be 8 bytes. The superframe counter field may be 51 bits. The first HEC field may be 13 bits. The PON-ID field may be 51 bits. The second HEC field may be 13 bits.

FIG. 13is a schematic diagram of an apparatus1300according to an embodiment of the disclosure. The apparatus1300may implement the disclosed embodiments. The apparatus1300comprises ingress ports1310and an RX1320or receiving means to receive data; a processor,1330or logic unit, baseband unit, CPU, or processing means to process the data; a TX1340or transmitting means and egress ports1350to transmit the data; and a memory1360or data storage means to store the data. The apparatus1300may also comprise OE components, EO components, or RF components coupled to the ingress ports1310, the RX1320, the TX1340, and the egress ports1350to provide ingress or egress of optical signals, electrical signals, or RF signals.

The processor1330is any combination of hardware, middleware, firmware, or software. The processor1330comprises any combination of one or more CPU chips, cores, FPGAs, ASICs, or DSPs. The processor1330communicates with the ingress ports1310, the RX1320, the TX1340, the egress ports1350, and the memory1360. In some embodiments, the processor1330includes a synchronization and clock recovery component1370, wherein the synchronization and clock recovery component1370comprises instructions that implement the disclosed embodiments when executed by the processor1330. The inclusion of the synchronization and clock recovery component1370therefore provides a substantial improvement to the functionality of the apparatus1300and effects a transformation of the apparatus1300to a different state. Alternatively, the memory1360stores the synchronization and clock recovery component1370as instructions, and the processor1330executes those instructions.

The memory1360comprises any combination of disks, tape drives, or solid-state drives. The memory1360may store instructions for execution by the processor1330. The memory1360may store data and/or working or intermediate values. The memory1360may store processing results. The apparatus1300may use the memory1360as an over-flow data storage device to store programs when the apparatus1300selects those programs for execution and to store instructions and data that the apparatus1300reads during execution of those programs, for instance as a computer program product. The memory1360may store additional or other data not mentioned herein. The memory1360may be volatile or non-volatile and may be any combination of ROM, RAM, TCAM, or SRAM.

A computer program product may comprise computer-executable instructions stored on a non-transitory medium, for instance the memory1360, that when executed by a processor, for instance the processor1330, cause an apparatus to perform any of the embodiments.

An ONU is in a PON. The ONU comprises a receiving means and a processing means. The receiving means is configured to receive a first PON frame from an OLT. The first PON frame comprises a first PSBd field. The first PSBd field comprises a first PSync field. The first PSync field comprises first bits. A first quantity of the first bits is greater than 64. The processing means is coupled to the receiving means and is configured to perform synchronization of the first PON frame by matching the first bits to a pre-stored sequence.