Gated filament structures for a field emission display

A gated filament structure for a field emission display includes a plurality of filaments. Included is a substrate, an insulating layer positioned adjacent to the substrate, and a metal gate layer position adjacent to the insulating layer. The metal gate layer has a plurality of gates, the metal gate layer having an average thickness "s" and a top metal gate layer planar surface that is substantially parallel to a bottom metal gate layer planar surface. The metal gate layer includes a plurality of apertures extending through the gates. Each aperture has an average width "r" along a bottom planar surface of the aperture. Each aperture defines a midpoint plane positioned parallel to and equally distant from the top metal gate layer planar surface and the bottom metal gate layer planar surface. A plurality of filaments are individually positioned in an aperture. Each filament has a filament axis. The intersection of the filament axis and the midpoint plane defines a point "O". Each filament includes a filament tip terminating at a point "A". A majority of all filament tips of the display have a length "L" between each filament tip at point A and point O along the filament axis where, EQU L.ltoreq.(s+r)/2.

BACKGROUND OF THE INVENTION 
1. Field of Use 
This invention relates to gated filament structures for a field emission 
display with filaments positioned in apertures. The relative position of 
the majority of each filament tip to its associated aperture is 
substantially the same for a majority of the filament tips of the display. 
This relationship is maintained even for large displays where there are 
nonuniformities in the thickness of the insulating layer or in the plating 
of the filaments. 
2. Description of the Related Art 
Field emission displays include a faceplate, a backplate and connecting 
walls around the periphery of the faceplate and backplate, forming a 
sealed vacuum envelope. In some field emission displays, the envelope is 
held at vacuum pressure, which can be about 1.times.10.sup.-7 torr or 
less. The interior surface of the faceplate is coated with light emissive 
elements, such as phosphor or phosphor patterns, which define an active 
region of the display. Field emission cathodes, such as cones and 
filaments, are located adjacent to the backplate. Application of an 
appropriate voltage at the extraction electrode releases electrons which 
are accelerated toward the phosphors on the faceplate. The accelerated 
electrons strike their targeted phosphors, causing the phosphors to emit 
light seen by the viewer at the exterior of the faceplate. Emitted 
electrons for each of the sets of emitters are intended to strike only 
certain targeted phosphors. 
A variety of methods for forming field emitters are known. 
U.S. Pat. No. 3,655,241 discloses fabricating field emitters using a screen 
with arrays of circular or square openings that is placed above a 
substrate electrode. A deposition is performed simultaneously from two 
sources. One of the sources consists of an emitter-forming metal, such as 
molybdenum, and atoms are deposited in a direction perpendicular to the 
substrate electrode. The other source consists of a closure material, such 
as a molybdenum-alumina composite. Atoms of the closure material are 
caused to impinge on the screen at a small angle to the substrate. The 
closure material progressively closes the openings in the screen. Thus the 
emitter-forming metal is deposited in the shape of cones or pyramids, 
depending on whether the screen openings are circular or square. 
Another method of creating field emitters is disclosed in U.S. Pat. No. 
5,164,632. Part of an aluminum plate is anodically oxidized to create a 
thin alumina layer having pores that extend nearly all the way through the 
alumina. An electrolytic technique is used to fill the pores with gold for 
the field emitters. An address line is formed over the filled pores along 
the alumina side of the structure, after which the remaining aluminum and 
part of the adjoining alumina are removed along the opposite side of the 
structure to re-expose the gold in the pores. Part of the re-exposed gold 
is removed during an ion-milling process utilized to sharpen the field 
emitters. Gold is then evaporatively deposited onto the alumina and partly 
into the pores to form the gate electrode. 
Field emitters are fabricated in U.S. Pat. No. 5,150,192 by creating 
openings partway through a substrate by etching through a mask formed on 
the bottom of the substrate. Metal is deposited along the walls of the 
openings and along the lower substrate surface. A portion of the thickness 
of the substrate is removed along the upper surface. A gate electrode is 
then formed by a deposition/planarization procedure. Cavities are provided 
along the upper substrate surface after which the hollow metal portions in 
the openings are sharpened to complete the field emitter structures. 
However, large area field emission displays require a relatively strong 
substrate for supporting the field emitters extending across the large 
emitter area. The requisite substrate thickness is typically several 
hundred microns to 10 mm or more. 
The fabrication methods in U.S. Pat. Nos. 5,164,632 and 5,150,192 make it 
very difficult to attach the field emitters to the substrates of thickness 
required for large area displays. 
In U.S. Pat. No. 4,940,916, a gated area field emitter consists of cones 
formed on a highly resistive layer that overlies a highly conductive layer 
situated on an electrically insulating supporting structure. For a 
thickness of 0.1 to 1 microns, the highly resistive layer has a 
resistivity of 10.sup.4 to 10.sup.5 ohm-cm. The resistive layer limits the 
currents through the electron-emissive cones so as to protect the field 
emitter from breakdown and short circuits. 
It is desirable to have uniformity of emission from the cathodes. A field 
emission cathode relies on there being a very strong electric field at the 
surface of a filament or generally on the surface of the cathode. Creation 
of the strong field is dependent on, (i) the sharpness of the cathode tip 
and (ii) the proximity of the extraction electrode (gate) and the cathode. 
Application of the voltage between these two electrodes produces the 
strong electric field. Emission nonuniformity is related to the 
nonuniformity in the relative positions of the emitter tip and the gate. 
Emission nonuniformity can also result from differences in the sharpness 
of the emitting tips. 
Busta, "Vacuum Microelectronics-1992," J. Micromech. Microeng., Vol. 2, 
1992 pp. 43-74 provides a general review of field-emission devices. Among 
other things, Busta discusses Utsumi, "Keynote Address, Vacuum 
Microelectronics: What's New and Exciting," IEEE Trans. Elect. Dev., 
October 1990, pp. 2276-2283, who suggests that a filament with a rounded 
end is the best shape for a field emitter. Also of interest is Fischer et 
al., "Production and Use of Nuclear Tracks: Imprinting Structure on 
Solids," Rev. Mod. Phys., October 1983, pp. 907-948, which deals with the 
use of charged-particle tracks in manufacturing field emitters according 
to a replica technique. 
A well collimated source of evaporant, as taught in U.S. Pat. No. 
3,655,241, is necessary in order to obtain uniformity of cone or filament 
formation across the entire field emission display. In order to maintain a 
collimated source, the majority of evaporant is deposited on interior 
surfaces of the evaporation equipment. The combination of the expensive of 
the evaporation equipment, and the wastage of evaporant, is undesirable 
for commercial manufacturing and is compounded as the size of the display 
increases. With large displays, there are nonuniformities in the thickness 
of the insulating layer and the plating of the filaments. 
It would be desirable to provide a gated filament structure for a field 
emission display where each filament and filament tip is positioned in a 
gate aperture. It would further be desirable to provide a large field 
emission display in which the relative positions of the filament tips to 
their associated apertures are substantially the same for a majority of 
the filament tips of the display. There is a need to maintain this 
relationship for large displays which have more nonuniformities in the 
thickness of the insulating layer and in the plating of the filaments. 
SUMMARY 
Accordingly, it is an object of the invention to provide gated filament 
structures for large field emission displays. 
Another object of the invention is to provide gated filament structures for 
large field emission displays that have nonuniformities in the thickness 
of the insulating layer or nonuniformity of plating of the filaments. 
A further object of the invention is to provide gated filament structures 
for a large field emission display where the gate is used to define the 
position of the filament tip. 
Still another object of the invention is to provide gated filament 
structures for a large field emission display where the gate is used to 
define the geometry of the filament tip. 
Yet another object of the invention is to provide gated filament structures 
which have sharpened filament tip geometries. 
Another object of the invention is to provide gated filament structures 
which have sharpened filament tip geometries that are positioned between a 
top planar surface and a bottom planar surface of the gate. 
A further object of the invention is to provide gated filament structures 
that are electroplated. 
Another object of the invention is to provide gated filament structures for 
a large field emission display that are vertically self aligned in its 
associated aperture. 
These and other objects of the invention are achieved in a gated filament 
structure for a field emission display that includes a plurality of 
filaments. A gated filament structure for a field emission display 
includes a plurality of filaments. Included is a substrate, an insulating 
layer positioned adjacent to the substrate, and a metal gate layer 
including a plurality of gates positioned adjacent to the insulating 
layer. The metal gate layer has an average thickness "s" and a top metal 
gate layer planar surface that is substantially parallel to a bottom metal 
gate layer planar surface. A plurality of apertures extending through each 
gate formed in the metal gate layer. Each aperture has an average width 
"r" along a bottom planar surface of the aperture. Each aperture defines a 
midpoint plane positioned parallel to and equally distant from the top 
metal gate layer planar surface and the bottom metal gate layer planar 
surface. A plurality of gated filaments are individually positioned in an 
aperture. Each filament has a filament axis. The intersection of the 
filament axis and the midpoint plane defines a point "O". Each filament 
includes a filament tip terminating at a point "A". A majority of all 
filapement tips of the display have a length "L" between each filament tip 
at point A and point O along the filament axis where, 
EQU L.ltoreq.(s+r)/2. 
It is preferred that at least 75% of all filament tips of the display have 
this relationship for points A and O, more preferably at least 90% of the 
filament tips have this relationship. 
The majority of filament tips can, (i) extend between the top and bottom 
metal gate layer surfaces, (ii) extend below the bottom metal gate layer 
surface, or (iii) extend above the top metal gate layer surface. 
Each filament of the display can be electroplated. 
In another embodiment, the gated filament structure for a field emission 
device includes a substrate. 
Additionally, the majority of the filament tips can extend beyond the top 
metal gate layer planar surface, or below the bottom metal gate layer 
planar surface. 
Further, each filament can be electroplated. Each filament is vertically 
self aligned in its associated aperture.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
For purposes of this disclosure, a large area field emission display is 
defined as having at least a 6 inch diagonal screen, more preferably at 
least an 8 inch diagonal screen, yet more preferably at least a 10 inch 
diagonal screen, and still more preferably at least a 12 inch diagonal 
screen. 
The ratio of length to maximum diameter of a filament is at least 2, and 
normally at least 3. The length-to-maximum-diameter ratio is preferably 5 
or more. 
A gated filament structure 10 is created, as illustrated in FIG. 1, from a 
multi-layer structure which includes a substrate 12, a metal row electrode 
14, a resistive layer 16 on top of row electrode 14, an insulating layer 
18 on a top surface of resistive layer 16, a metal gate layer 20, and a 
filament 22 in an insulating pore. Insulating layer 18 is positioned 
between substrate 12 and metal gate layer 20. It will be appreciated that 
insulating layer 18 is positioned adjacent to substrate 12 and there can 
be additional layers between insulating layer 18 and substrate 12 in this 
adjacent relationship. Thus, adjacent is used herein to mean one layer on 
top of another layer as well as the possibly of adjacent layers can have 
intervening layers between them. A portion of insulating layer 18 adjacent 
to filament 22 has been removed. Filaments are typically cylinders of 
circular transverse cross section. However, the transverse cross section 
can be somewhat non-circular. The insulating pore is formed with spacers 
and reactive ion etching. For definitional purposes, substrate means, (i) 
a conductive or semi-conductive substrate with an insulating layer on a 
top surface of the substrate, (ii) a conductive or semi-conductive 
substrate with patterned insulating regions or (iii) an insulating 
substrate. 
Referring now to FIG. 2, the initial multi-layer structure also includes a 
tracking resist layer 24 positioned on a top surface of metal gate 20. 
Suitable materials for the multi-layer structure include the following: 
substrate 12--glass or ceramic 
metal row electrode 14--Ni 
resistive layer 16--cermet, CrO.sub.x or SiC 
insulating layer 18--SiO.sub.2 
metal gate layer 20--Cr and/or Mo 
tracking resist layer 24--polycarbonate 
filament 22--Ni or Pt 
Multi-layer structure of FIG. 1 can be irradiated with energetic charged 
particles, such as ions, to produce charged particle tracks in tracking 
resist layer 24. Alternatively, other methods, such as the use of spheres, 
can be used in place of charged particle tracks to create the gate, as 
disclosed by Spindt et al., "Research in Micron-Size Field-Emission 
Tubes", IEEE Conference Record of 1966 Eighth Conference on Tube 
Techniques, September 1966 pp. 143-147, incorporated herein by reference. 
The other methods include but are not limited to conventional lithography, 
such as photolithography, x-ray lithography and electron beam lithography. 
When charged particles are used, they impinge on tracking resist layer 24 
in a direction that is substantially perpendicular to a flat lower surface 
of substrate 12, and therefore are generally perpendicular to tracking 
resist layer 24. The charged particles pass through tracking resist layer 
24 in a straight path creating a continuous damage zone along the path. 
Particle tracks are randomly distributed across the multi-layer structure 
with a well defined average spacing. The track density can be as much as 
10.sup.11 tracks/cm.sup.2. A typical value is 10.sup.8 tracks/cm.sup.2, 
which yields an average track spacing of 1 micron. 
In one embodiment, a charged particle accelerator forms a well collimated 
beam of ions which are used to form tracks. The ion beam is scanned 
uniformly across tracking resist layer 24. A preferred charged particle 
species is ionized Xe with an energy typically in the range of about 4 MeV 
to 16 MeV. Alternatively, charged particle tracks can be created from a 
collimated source of nuclear fission particles produced, for example, by 
the radioactive element Californium 252. 
Once the particle tracks have been formed, a chemical etch, including but 
not limited to KOH or NaOH, etches and can over-etch the track formed in 
tracking resist layer 24 (FIG. 3). Instead of forming a cylindrical pore 
etched along the track, it is widened to open up an aperture 26 in 
tracking resist layer 24 that is conical with a generally trapezoidal 
cross-section. Aperture 26 has a diameter of about 50 to 1000 nm, such as 
by way of example 200 nm, at gate layer 20. Tracking resist layer 24 is 
used as a mask to etch gate layer 20 to produce, in one embodiment a 200 
nm diameter gate hole 28 (FIG. 4). The etching can be reactive ion etching 
such as Cl.sub.2 for Cr and SF.sub.6 for Mo. The depth of reactive ion 
etching into insulating layer 18 is minimized. A variety of mechanisms are 
available to ensure that the reactive ion etching stops at insulating 
layer 18 including but not limited to, monitoring the process and stopping 
it at the appropriate time, the use of feedback devices, such as sensors, 
and use of a selective etch. Excess tracking resist 24 material is 
stripped away, leaving a gate 30 on the top of insulating layer 18. 
Referring now to FIG. 5(a), a conformal layer 32 is applied on top of gates 
30 and into apertures 28. Suitable materials for conformal layer 32 
include but are not limited to silicon nitride, amorphous or small grained 
polycrystalline Si, and SiO.sub.2. Methods for applying conformal layer 
include but are not limited to CVD. 
As shown in FIG. 5(b) when conforming layer 32 is anisotropicaly etched 
material is removed. Material is removed from conformal layer 32 at 
surfaces which are parallel to a plane 33 defined by insulating substrate 
12, e g., surface 35 is not etched. The anisotropic etching step removes 
the material, thus forming a spacer 36 at a step 34. 
It is seen in FIG. 6 that spacer 36 leaves an aperture 38 at the top of 
insulating layer 18. The size of spacers 36 is controlled to define the 
size of aperture 38, which can be, in one instance about 100 nm in width. 
As shown in FIG. 7, spacers 36 are used as a mask for etching, e.g., a 
highly anisotropic selective etch in order to etch substantially only 
insulating layer 18 and form an insulating pore 40. Other structures are 
minimally etched. During the etch process, polymer is formed on the walls 
of insulating pores due to the use of CH.sub.4 in the plasma. This forms a 
polymer on side and bottom walls of insulating pores 40. The polymer 
protects the walls from chemical attack but does not protect the walls 
from the energetic particles. Because the energetic particles come 
straight down and hit only the bottom of insulating pore 40, the polymer 
is removed only from the bottom of insulating pore 40 and not along the 
sidewalls. The walls are protected from chemical attack, and etching is 
only in a direction towards resistive layer 16 because of the anisotropic 
nature of the reactive ion etching. There is substantially no undercutting 
of insulating layer 18 because of polymer formation along the vertical 
walls of insulating pore 40 perpendicular to the plane of insulating 
substrate 12. Insulating pore 40 does not extend substantially into 
resistive layer 16. The control of limiting the etching of resistive layer 
16 is accomplished with a variety of mechanisms, including but not limited 
to, (i) employing a selective etch that etches resistive layer 16 very 
slowly, (ii) determination of an end point when the etching will be 
completed by timing and the like, and (iii) monitoring to determine the 
point when resistive layer 16 begins to be etched. 
Following reactive ion etching, it may be desirable to apply a chemical 
treatment on insulating pore 40 to remove the polymer. Suitable chemical 
treatments include but are not limited to, a plasma of CF.sub.4 with 
O.sub.2, or commercially available polymer strippers used in the 
semiconductor industry well known to those skilled in the art. Thereafter, 
an electrochemical cell is used, such as shown in FIG. 7. 
Referring now to FIG. 8, insulating pore 40 is then filled with a filament 
material. The plating extends into patterned gate 30. Suitable plating 
materials include but are not limited to Ni, Pt and the like. Plating can 
be achieved by pulse plating, with resistance layer 16 as the cathode, and 
an external anode. The voltage of resistive layer 16 and patterned gate 30 
is controlled so that plating does not occur on metal gate layer 20. 
Spacers 36 are subsequently removed with a removal process, including but 
not limited to selective plasma etching and wet etching. Thereafter, 
insulating layer 16 adjacent to filament 22 can be removed with an 
isotropic plasma or wet chemical (dilute HF) etch. The amount of 
insulating layer 18 removed is almost down to resistive layer 16. 
Alternatively, insulating layer 18 is not removed (FIG. 9). 
The use of spacers 36 along with reactive ion etching defines insulating 
pores 40 which are used to create filaments 22. An alternative process is 
to use tracking of the insulating layer 18 and chemical etching along the 
particle tracks. 
With reference once again to FIG. 1, filament 22 is created and its tip 
preferably is between a top planar surface 41 of gate layer 20, and a 
bottom planar surface 43 of gate layer 20. In another embodiment, the 
filament tip is formed above planer surface 41. Less preferably, filament 
tip is formed below planar surface 43. The tip of filament 22 can be 
polished/etched to form a desired tip geometry. 
Filaments 22 can have a variety of geometries such as flat topped 
cylinders, rounded top cylinders, sharp cones and the like, which can be 
created by polishing/etching. 
If there are nonuniformities in the thickness of insulating layer 18, or 
nonuniformities in plating, another embodiment of the invention, 
illustrated in FIGS. 10 through 21, may be more suitable for producing 
filaments 22 with the same position relative to each respective gate 30, 
as more fully described hereafter. With reference now to FIGS. 10 and 20, 
filament 22 is formed above patterned gate 30 by the inclusion of a gate 
encapsulation layer 42. As shown in FIG. 20 patterned gate 30 is then used 
to define the point of filament 22, e.g., the tip geometry of filament 22, 
which allows for accommodation of non-uniformity in plating and 
non-uniformity in thickness of the dielectric. This defines the 
self-alignment of filament 22. Suitable gate encapsulation layer 42 
materials include but are not limited to Si, SiO.sub.2 and Si.sub.3 
N.sub.4. 
The initial multi-layer structure is illustrated in FIG. 10 and includes a 
substrate 12, a metal row electrode 14 positioned on a top surface of 
substrate 12, a resistive layer 16 on a top surface of metal row electrode 
14, an insulating layer 18 on a top surface of resistive layer 16, a metal 
gate layer 20 positioned on a top surface of insulating layer 18, a gate 
encapsulation layer 42 positioned on a top surface of metal gate layer 20 
and optionally a tracking resist layer 24 positioned on a top surface of 
gate encapsulation layer 42. It will be appreciated that tracking resist 
layer 24 need not be included in this embodiment. The appropriate choice 
of material for gate encapsulation layer 42 may permit gate encapsulation 
layer 42 to be used also as the tracking resist layer. The only 
differences between the multi-layer structure in the two embodiments is 
the inclusion of gate encapsulation layer 42, with or without tracking 
resist layer 24. Gate encapsulation layer 42 provides two functions, (i) 
it encapsulates patterned gate 30 and (ii) allows for the formation of 
taller spacers 36, permitting plating filament 22 above patterned gate 30. 
Particle tracking is utilized, as practiced in the first embodiment, and 
tracking resist layer 24 is etched (FIG. 11). A reactive ion etch through 
gate encapsulation layer 42 and gate layer 20 is performed (FIG. 12), 
creating gate hole 28 and patterned gate 30. Tracking resist layer 24 need 
not be included if gate encapsulation layer 42 can be tracked, etched and 
used as a resist for patterning gate 30. It will be appreciated that the 
same methods employed in the embodiment illustrated in FIGS. 1 through 9 
are employed in this second embodiment, illustrated in FIGS. 10 through 
21. The detailed descriptions of the multiplicity of steps utilized will 
not be repeated here. 
Tracking resist layer 24, if included, is removed and a spacer conformal 
layer 32 is formed over gate layer 20 and into gate hole 28 (FIG. 13). 
With the proper selection of materials for gate encapsulation layer 42 and 
spacer conformal layer 32, gate layer 20 is completely insulated; 
therefore eliminating concerns regarding controlling voltage on patterned 
gate 30 to ensure that plating will not occur on patterned gate 30. 
With the anisotropic etching of spacer conformal layer 32, the resulting 
spacers 36 have a height equal to the height of gate layer 20 plus 
encapsulation layer 42 (FIG. 14). 
Insulating pore 40 is formed (FIG. 15) and can have a width in the range of 
50 to 1000 nm. A suitable width is about 100 nm. Insulating pore 40 is 
then filled (FIG. 16). 
Referring now to FIGS. 17 and 18, the effects of nonuniformity of the 
thickness of insulating layer 18 of gated filament structure 10, and 
nonuniformity of plating are illustrated. Assuming that all insulating 
pores 40 fill at the same rate, then where insulating layer 18 is thin, 
insulating pores will be filled more quickly and there will be overplating 
(FIG. 17). Due to plating nonuniformity some insulating pores 40 will fill 
faster than others (FIG. 18). It is difficult to achieve uniformity of 
plating, particularly in large field emission displays because it is 
arduous to build suitable equipment to achieve uniform plating. The 
requirements of such equipment are that it provides, (i) uniform current 
density and (ii) efficiently stirs the electrolyte to avoid concentration 
gradients and depletion of the electrolyte. In any event, even with these 
nonuniformities, the relationship between filament 22 and its respective 
gate aperture 28 is maintained, as more fully described hereafter. 
Conformal layer 32 and spacers 36 are removed, leaving a filament 22 that 
extends beyond patterned gate 30. (FIG. 19). Patterned gate 30 can be used 
to electro-polish filament 22 with the circuitry illustrated in FIG. 19. 
Thus, patterned gate 30 is used to define the point where a tip 44 of 
filament 22 will be (FIG. 20). Patterned gate 30 serves as the cathode for 
the electro-polishing. A suitable electrolyte is well known to those 
skilled in the art. This essentially pinches off filament 22 so that 
excess material becomes free and can be washed away. The remaining 
filament 22 has a tip 44 geometry that is sharp. 
Tip 44 of filament 22 is now located at the position of patterned gate 30. 
Filament 22 and filament tip 44 are positioned in gate aperture 28 to 
establish a relative position for filament tip 44 with its associated gate 
aperture 28. Referring now to FIG. 21, the relative position of filament 
tip 44 to its associated gate aperture 28 is defined as the position of 
tip 44 relative to a top planar surface 41 of gate layer 20 and a bottom 
planar surface 43 of gate layer 20. 
Metal gate layer 20 has an average thickness "s" and a top metal gate 
planar surface 20(a) that is substantially parallel to a bottom metal gate 
planar surface 20(b). Metal gate layer 20 includes a plurality of pores 40 
extending through metal gate 30. Each pore 40 has an average width "r" 
along a bottom planar surface of the aperture. Each pore defines a 
midpoint plane 46 positioned parallel to and equally distant from top 
metal gate planar surface 20(a) and bottom metal gate planar surface 
20(b). A plurality of filaments 22 each have a filament tip 44 which 
terminates at a point "A" and a filament axis 48 that extends along a 
length of the filament through filament tip 44. At the intersection of 
filament axis 48 and midpoint plane 46, a point "O" is defined. A majority 
of all filament tips 44 of the display have a length "L" between each 
filament tip 44 at point A and point O along filament axis 48, where, 
EQU L.ltoreq.(s+r)/2. 
Preferably, at least 75% of all filament tips 44 have this relationship 
between point A and point O, more particularly, it is at least 90%. 
The majority of filament tips 44 of the display can have, (i) point A above 
top metal gate layer planar surface 20(a), (ii) point A between top metal 
gate layer planar surface 20(a) and bottom metal gate layer planar surface 
20(b), or (iii) point A below bottom metal gate layer planar surface 
20(b). 
With the method of the present invention every insulating pore 40 is 
overplated and vertical self-alignment is utilized. Patterned gate 30 is 
used to do the polishing/etching. With the inclusion of gate encapsulation 
layer 42 filament 22 is plated above patterned gate 30. Additionally, 
there may be more plating at the edges of the field emission display than 
in the middle. This can occur because of (i) current crowding effects and 
(ii) electrolytic depletion effects. As long as the plating is above 
patterned gate 30 in all places two advantages are achieved, (i) a 
tolerance on thickness uniformity of deposited insulating layer 18 is 
provided, and (ii) a high tolerance for the uniformity of plating is 
possible. 
The result is the creation of filaments 22 for the field emission display 
and the position of each filament 22 is the same within each pore 40 
(vertical alignment). Polished filament tips 44 can be created. Further, 
cones can be formed, as well as filaments using electroless deposition and 
selective deposition processes well known to those skilled in the art. 
In another embodiment, the gate can be patterned and used as a mask to 
completely etch the insulating layer. The conformal layer is then 
deposited into the created pore. This can lead to complete encapsulation 
of the gate, making plating easier. Excess material formed on a bottom of 
the pore is removed with a suitable method including but not limited to 
plasma or wet etch. The pore is then overplated. Conformal layer is 
subsequently substantially removed chemically, and the desired filament 
tip is then electrochemically etched to created the desired geometry. 
The foregoing description of preferred embodiments of the present invention 
has been provided for the purposes of illustration and description. It is 
not intended to be exhaustive or to limit the invention to the precise 
forms disclosed. Obviously, many modifications and variations will be 
apparent to practitioners skilled in this art. The embodiments were chosen 
and described in order to best explain the principles of the invention and 
its practical application, thereby enabling others skilled in the art to 
understand the invention for various embodiments and with various 
modifications as are suited to the particular use contemplated. It is 
intended that the scope of the invention be defined by the following 
claims and their equivalents.