MuGFET circuit for increasing output resistance

In an embodiment, an apparatus includes a MuGFET device coupled to a reference source, the MuGFET device configured to receive an input signal at a gate thereof; and Also includes a further MuGFET device coupled between the MuGFET device and a first terminal of a load, a second terminal of the load coupled to a further reference source, the further MuGFET device configured to receive a further input signal at a gate thereof, and wherein the MuGFET device and the further MuGFET device are disposed above a substrate and configured to provide an output signal at the first terminal of the load.

TECHNICAL FIELD

Various embodiments described herein relate to semiconductor devices and, more particularly, to field effect transistors.

BACKGROUND

Multi-gate field effect transistor devices are often designed for applications with scaled-down extremely small devices which operate at low supply voltages. Moreover, multi-gate devices have gates on multiple sides of the conducting channel thereby providing better control of the semiconductor device.

DETAILED DESCRIPTION

In the following description, the terms “wafer” and “substrate” may be used interchangeably to refer generally to any structure on which integrated circuits are formed and also to such structured during various stages of integrated circuit fabrication. The term “substrate” is understood to include a semiconductor wafer. The term “substrate” is also used to refer to semiconductor structures during processing and may include other layers that have been fabricated thereupon. Both “wafer” and “substrate” include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art.

The term “multiple gate field effect transistor” (MuGFET) is used interchangeably with FinFET herein for the general class of semiconductor devices having field effect transistors formed above a buried oxide layer of a substrate. Embodiments of the invention may be realized using MuGFETs having either p type or n type channel doping of the fins. Thus source and drain terminals may sometimes be referred to herein as “source/drain” terminals.

The term “conductor” is understood to generally include n-type and p-type semiconductors and the term “insulator” or “dielectric” is defined to include any material that is less electrically conductive than the materials referred to as “conductors.” The following detailed description is, therefore, not to be taken in a limiting sense.

The following disclosure relates in general to providing for operation of structures employing multiple circuit blocks, some of which include MuGFET devices. Multiple MuGFET devices are formed above a buried oxide contact region of a single substrate and supported by the substrate. In general, this is different from planar CMOS devices which have a conducting channel only at the surface of the silicon. Bulk CMOS devices require increased doping levels with increased scaling. This adversely affects carrier mobility and junction capacitance. Additionally, planar devices usually only have a single gate on the surface of the silicon to control the channel on the surface of the semiconductor as opposed to their MuGFET counterparts which can have multiple gates formed around a raised channel. Moreover, the multiple gate configuration provides for greater control of the conducting channel and reduces detrimental performance due to short channel effects. Furthermore, multi-gate semiconductor devices provide better turn-on characteristics and have lower leakage current characteristics compared to planar CMOS devices.

In some embodiments, because the MuGFET devices are electrically insulated from the substrate and each other by being formed above the buried oxide region, individual devices can be connected to separate sources of reference potential and to separate power supplies. Other semiconductor devices may also be formed above and supported by the substrate in contact regions thereof which are not insulated by the buried oxide contact region. The various circuit blocks can be coupled to each other by a suitable coupling element or coupling network despite their being operatively coupled to different sources of reference potential. In some embodiments the circuit blocks are driven from different power sources.

FIG. 1a simplified schematic of a conventional MuGFET device102. Device102has a source terminal thereof coupled to a source of reference potential such as ground, a gate coupled to an input terminal104, and an output terminal106. The small signal impedance of device102is expressed as rdswhich is the output impedance of MuGFET102at terminal106.

FIG. 2is a simplified schematic of a conventional MuGFET circuit200. Circuit200comprises a p channel MuGFET device202having its source coupled to one terminal of a load such as resistor RL, the other terminal of which is coupled to a source of reference potential which may be ground. The drain terminal of MuGFET202is connected to an output terminal208and the gate is coupled to an input terminal204. The output resistance of MuGFET circuit200is:
Rout=gm*rds*RL
where gmis the transconductance and rdsis the small signal drain-to-source resistance of MuGFET202.

In some embodiments, multiple MuGFET devices can be connected in a cascode configuration which provides high output resistance and allows for reduction of Miller effect from other connection configurations. This type of configuration provides for better high-frequency performance and higher output resistance. An amplifier stage having a cascode configuration can be used as the gain element in amplifier stages when the Miller effect is an issue. Cascode stages are also used in circuits having current sources and as non-linear loads where the output resistance of a single transistor stage is not sufficient. As devices are made smaller and faster, the output resistance often suffers. The cascode configuration offers a way of improving performance in such circuits.

FIG. 3is a simplified schematic of a MuGFET cascode circuit300, according to some embodiments of the invention. In some embodiments, circuit300includes a first MuGFET device302having a source/drain terminal coupled to a terminal306, and a source/drain terminal coupled to a source/drain terminal of a second MuGFET303the source/drain of which is coupled to a source of reference potential such as ground. MuGFET302has a gate coupled to an input terminal306which, in some embodiments is connected to a source of bias voltage, Vcase. MuGFET303has a gate coupled to an input terminal304which is connected to receive a signal Vin.

MuGFET circuit300has an output terminal306. The small signal output resistance of MuGFET circuit300at terminal306is:
Rout=gm2*rds2*rds1
where gm2is the transconductance of MuGFET302and rds1and rds3are the small signal drain-to-source resistance of MuGFETs302and303respectively. Replacing RLwith MuGFET303allows a more efficient use of chip area because a resistor consumes much more chip area for the same resistance as does a MuGFET.

FIG. 4is a more detailed schematic of some circuit embodiments of the MuGFET circuit ofFIG. 3. In some embodiments, circuit400includes a MuGFET device402having a drain coupled to a voltage source, VDby a load such as resistor408, and a source coupled to drain of a MuGFET device403, the source of which is coupled by a load such as resistor411to a source of reference potential such as ground. In some embodiments, a relatively low impedance resistor411may be connected between ground and the source region of MuGFET403to couple the source of MuGFET403to ground. MuGFET402has a gate coupled to an input terminal405which, in some embodiments is connected to a source of bias voltage413, Vcase.

In circuit400, the voltage available at the gate of MuGFET402is determined by the magnitude of supply voltage VDmultiplied by the ratio of resistor412to resistor414, since the resistance at the gate of MuGFET402is very high in some embodiments. MuGFET403has a gate coupled to an input terminal404which is connected to receive a signal Vinwhich, in some embodiments is applied across an input resistor416. In some embodiments, the signal Vinis provided by an input circuit417selected from a group of front end circuits consisting of amplifiers, pre-amplifiers, amplitude modulation circuits, and reference voltage sources.

In the circuit shown inFIG. 4, upper MuGFET402acts as a load for lower MuGFET403. Because capacitor418acts effectively as a ground, the source voltage of upper MuGFET402is held at a nearly constant voltage during operation, thereby reducing the Miller feedback capacitance from the drain to the gate of lower MuGFET403, compared to what would occur if upper MuGFET402were a typical inductive/resistive load and the output were taken from the drain of MuGFET403. Thus the only terminals with substantial voltage swings are input terminal404and output terminal406, and those terminals are separated by the central connection of nearly constant voltage and the physical separation of MuGFETs402and403.

The inclusion of MuGFET402permits MuGFET403to operate at maximum input impedence and minimum negative feedback (i.e., Miller effect feedback), improving its gain. Miller effect performance limitations are avoided because the gate of MuGFET402is electrically grounded and stray capacitance from its drain to its source will not reduce its gain because the voltages are in-phase.

The cascode arrangement of circuit400has improved performance stability. The output at terminal406is proportional to the input signal Vin, is effectively isolated from the input at terminal404both electrically and physically. In some embodiments, the output at terminal406is input to further utilization circuitry420selected from the group consisting of further amplifier stages, output stages and circuits for receiving a compensated current from a current mirror.

In some embodiments, the saturation drain-to-source saturation current of MuGFET402is higher than that of MuGFET403or drain voltage of MuGFET402to prevent it from falling too low and causing it to leave saturation. In some embodiments, both MuGFETs402and403are biased with a drain to source voltage, VDS, sufficient to facilitate their performance.

FIG. 5is a simplified perspective view of the MuGFET device500corresponding to the circuit300shown in the schematic diagram ofFIG. 3, according to some embodiments of the invention. In order to simplifyFIG. 5, it does not illustrate the metallization layers which, in some embodiments, connect the gate, source and drain terminals of MuGFETs302and303and does not illustrate the resistors408,411,412,414,416, capacitor418, or the upstream, downstream and bias circuits417,420,413which are all shown in the embodiment illustrated in the more detailed schematic ofFIG. 4.

MuGFETs302and303may be p-doped or an n-doped fin transistors. Each has at least one fin310. The fins may be disposed above an insulating surface315of a substrate320. In some embodiments, substrate320is preferably mono-crystalline silicon, although it is also possible to use any other desired semiconductor substrates, such as silicon on insulator (SOI), and germanium or other Group III-IV semiconductors. In some embodiments, the insulating surface may be a buried oxide or other insulating layer315over a silicon or other semiconductor substrate320. A gate dielectric structure330is formed over the top and on the sides of the semiconductor fins310. A gate electrode335is formed over the top and on the sides of the gate dielectric330and may include a metal layer. Source/drain regions340and345may be formed on either side of the gate electrode335, and those regions may be laterally expanded to engage multiple fins310, in various embodiments.

Each fin310has a top surface350and laterally opposite sidewalls355. Each fin310has a height or thickness equal to T and a width equal to W. The gate width of a single fin MuGFET transistor is equal to the sum of the gate widths of each of the three gates formed on the semiconductor body, or, T+W+T, which provides high gain. In some embodiments, the lateral cross-section of the fin is substantially in the shape of a rectangle. In other embodiments, the lateral cross-section of the fin is substantially in the shape of a rectangle with rounded corners. In an embodiment, the height-to-width ratio of the fin is substantially in the range of 3:1 to 5:1. In an embodiment, the width of the fin is substantially 20 nm.

In some embodiments described above, the fin310is made of silicon. In some embodiments, the fin310can be made of other semiconductor materials, like germanium, silicon carbide, gallium arsenide, as well as indium phosphide. In some embodiments, the fin310may be coated with a thin film of silicate, for example, with a thickness of approximately 10 nm. In some embodiments such as shown inFIG. 5, a plurality of fins may be used as opposed to a single fin310. In such configurations the increase in the number of fins allows for increasing the amount of current conducted through the conducting channel (provided by the multiple fins) between the source and drain regions.

Better noise immunity results from forming the transistors on an insulator. Formation on the insulator provides isolation between devices, and hence the better noise immunity. It further alleviates the need for multiple large well areas to reduce leakage currents, further leading to reduced real estate needs. Having the gate traverse two or more sides of the fin or channel results in much quicker off current than prior bulk CMOS or planar devices. Further, the current characteristics of p-doped MuGFET devices may exhibit similar or higher gain than corresponding n-doped MuGFET devices. This may reduce the potential effects of degradation of devices over time. Since the channels are formed by the use narrow fins, improved matching of the devices is significantly easier than in bulk or planar CMOS devices, allowing better control of their current characteristics.

Such embodiments of the inventive subject matter may be referred to herein, individually and/or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. In the previous discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including”, but not limited to . . . ”