Fin interconnects for multigate FET circuit blocks

In an embodiment, an apparatus includes a first field effect transistor including a first source contact region, a first drain contact region and a first plurality of fins overlying a substrate, a first gate overlying the first plurality of fins, the first source contact region coupled to first ends of the first plurality of fins, and a second field effect transistor including a second source contact region, a second drain contact region, and a second plurality of fins overlying the substrate, a second gate overlying the second plurality of fins, and an interconnection contact region overlying the substrate, electrically coupling the first drain contact region and the second source contact region and abutting the first and the second pluralities of fins.

TECHNICAL FIELD

Embodiments described herein relate generally to semiconductor circuits which include multigate field effect transistor devices.

BACKGROUND

Multigate field effect transistor devices are often designed for applications using circuits with down-scaled, extremely small devices. Circuits using multigate field effect transistor devices have large source/drain contact regions.

DETAILED DESCRIPTION

The following detailed description refers to the accompanying drawings that show, by way of illustration, specific details and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the invention. The various embodiments are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one. In this document, the term “or” is used to refer to nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated.

In the following description, the terms “wafer” and “substrate” may be used interchangeably to refer generally to any structure on which integrated circuits are formed and also to such structures during various stages of integrated circuit fabrication. The term “substrate” is understood to include a semiconductor wafer. The term “substrate” is also used to refer to semiconductor structures during processing and may include other layers that have been fabricated thereupon. Both “wafer” and “substrate” include doped and undoped semiconductors, epitaxial semiconductor layers supported by a base semiconductor or insulator, as well as other semiconductor structures well known to one skilled in the art.

The term “multiple gate field effect transistor” (MuGFET) is used interchangeably with FinFET herein for the general class of semiconductor devices having non-planar field effect transistors formed on fins of semiconductor material.

The term “conductor” is understood to generally include n-type and p-type semiconductors and the term “insulator” or “dielectric” is defined to include any material that is less electrically conductive than the materials referred to as “conductors.” The following detailed description is, therefore, not to be taken in a limiting sense.

The term “contact region” is understood to generally include a region that provides electrical connectivity to other devices, circuits, or reference potential sources.

The following disclosure relates in general to providing for operation of structure employing multiple circuit blocks, some of which include MuGFET devices. Multiple MuGFET devices are typically formed above a buried oxide region of a single substrate and supported by the substrate. Because the MuGFET devices are electrically insulated from the substrate and each other by being formed above the buried oxide region, individual devices can be connected to separate sources of reference potential and to separate power supplies. Other semiconductor devices and circuit blocks may also be formed above and supported by the substrate in contact regions thereof which are not insulated by the buried oxide region. The various circuit blocks can be coupled to each other by a suitable coupling element, coupling network or interconnection contact region despite their being operatively coupled to different sources of reference potential. In some embodiments, the source/drain regions of multiple MuGFET devices are shared by the same contact region. In some embodiments, the circuit blocks are driven from different power sources.

Typically, in circuits formed using semiconductor devices, a number of independent devices such as pFET or nFET are used to form various types of analog or digital circuits. Each of the pFET or nFET devices are fabricated on the substrate separately with each device having independent source/drain and gate regions. This type of arrangement of pFET and nFET devices leads to the use of a considerable amount of area available on the semiconductor wafer. In general, circuit using FINFET or MUGFET technology consumes a large source/drain contact region. Moreover, limitations in the pitch of fins in such devices prevents further reduction in area of the circuit on the semiconductor wafer. On the contrary, according to some embodiments of the invention, a shared source/drain region architecture as described below provides for a reduction in the area used on the semiconductor wafer.

FIG. 1Aillustrates a top view of an apparatus100showing a fin interconnect, according to some embodiments of the invention. In some embodiments, apparatus100includes two devices20and40coupled at an interconnection region120. In some embodiments, device20includes contact regions101, a set of fins104and gate105and a first portion122of interconnect region120. In some embodiments, device40includes contact regions111, a set of fins114and gate115and a second portion124of interconnect region120.

Contact region101includes a landing pad102having multiple contact elements103. Contact region111includes a landing pad112having multiple contact elements113. Gate105includes a landing pad106having a contact element107and a gate line108. Gate115includes a landing pad116having a contact element117and gate line118. Set of fins104includes a first end50and a second end52. Set of fins114includes a first end60and a second end62. Second end52of set of fins104abuts and is electrically coupled to the second end62of set of fins114at the interconnection region120.

In some embodiments, interconnect region120includes a landing pad126. The second end52of the set of fins104is coupled to the first portion122and the second end62of the set of fins114is coupled to the second portion124. Additionally, in some embodiments, the first portion122and the second portion124are coupled to the landing pad126. Landing pad126includes contact elements123and125. In some embodiments, the contact elements123and125function as a source/drain regions of a pFET or an nFET device. In some embodiments contact elements123and125are coupled to other devices or circuits that may be located elsewhere on the semiconductor wafer.

In some embodiments, contact elements103,113and123,125are source/drain regions for a pFET or an nFET device. In some embodiments, region under mask130(FIG. 1A) is doped with an n-type dopant and remaining region including contact region101, gate105and set of fins104are doped with a p-type dopant. In some embodiments, region under mask130(FIG. 1A) is doped with a p-type dopant and remaining region including contact region101, gate105and set of fins104are doped with n-type dopant. In some embodiments, the number of fins included in set of fins104is different to the number of fins included in set of fins114.

FIG. 1Billustrates a perspective view of a cross-section of a portion of apparatus100shown inFIG. 1A, according to some embodiments of the invention. In some embodiments, apparatus100is fabricated over a semiconductor substrate50. Semiconductor substrate50used is preferably mono-crystalline silicon, although it is also possible to use any other desired semiconductor substrates, such as silicon on insulator (SOI), Germanium or III-IV semiconductors.

FIG. 2illustrates a top view of an apparatus200showing a fin interconnect, according to some embodiments of the invention. In some embodiments, apparatus200includes three devices70,80and90coupled using an interconnection region120and an extender220. In some embodiments, device70includes contact region101, a set of fins104, a gate105, the interconnect region120, an extender220and contact region224. In some embodiments, device80includes contact region111, a set of fins114, a gate115, the interconnection region, the extender220and contact region224. In some embodiments, device90includes contact regions224, a set of fins222, a gate230, the interconnect region120, the extender220and any one or both of contact regions101and111.

As described above, contact regions101,111include landing pads102,112having multiple contact elements103,113, respectively. Gates105,115include gate lines108,118and landing pads106,116having contact elements107,117, respectively. Gate230includes a gate line234, a landing pad232having a contact element233. Additionally, set of fins104and set of fins114are coupled to contact regions101and111, respectively at one end and at the other end are abutted and electrically coupled to each other and the interconnection region120. Set of fins222is coupled to contact region224at one end and couple to extender220at the other end. In some embodiments, extender220provides electrical coupling between the interconnection region120and other circuits and/or devices.

In some embodiments, contact elements103,113and226are source/drain regions of a pFET or an nFET device. In some embodiments, various portions of apparatus200are doped with an n-type dopant using a mask and remaining region is doped with a p-type dopant. In some embodiments, various portions of apparatus200are doped with a p-type dopant using a mask and remaining region is doped with an n-type dopant. In some embodiments, the number of fins included in set of fins104is different to the number of fins included in set of fins114and the number of fins in set of fins222.

FIG. 3illustrates a top view of an apparatus showing a fin interconnect, according to some embodiments of the invention. In some embodiments, apparatus300includes silicon302deposited in between the fins shown in apparatusFIG. 1A. Typically, silicon may be grown on the sides of the fins using a selective epitaxial growth (SEG) process. The selective epitaxial growth process is performed after the formation of gates105and115on top of set of fins104and114, respectively. Typically, during the SEG process, a silicon film grows only in those areas where single-crystal silicon is present and is suppressed elsewhere.

FIG. 4illustrates a top view of an apparatus400showing shared local interconnects and shared gates, according to some embodiments of the invention.

In some embodiments, apparatus400includes contact regions401and411, set of fins104,114,404and414, interconnect contact regions120and430, gates105and115. One end of set of fins104and404is coupled to contact region401. One end of set of fins114and414is coupled to contact region411. In some embodiments, the remaining end of set of fins104and114are abutted and electrically coupled to interconnect region120. In some embodiments, the remaining end of set of fins404and414abut and are electrically coupled to interconnect region430. Interconnect region120includes a landing pad122having contact elements123and125. Interconnect region430includes a landing pad432having contact elements433and435. In some embodiments, the number of fins in set of fins104is different from the number of fins in set of fins114. In some embodiments, the number of fins in set of fins404is different from the number of fins in set of fins414. Gates105,115include gate lines108,118, landing pads106,116having contact elements107,117, respectively.

In some embodiments, apparatus400shown inFIG. 4includes multiple devices sharing the same gate. In some embodiments, apparatus400includes multiple devices sharing a source/drain region. In some embodiments contact elements123,125,433and435are coupled to other devices or circuits that may be located elsewhere on the semiconductor wafer.

FIG. 5illustrates a top view of an apparatus500showing a fin interconnect, according to some embodiments of the invention. In some embodiments, apparatus500includes contact regions501and520, gates505and515, interconnect contact region518, and a set of fins504and514. Contact regions501,520include landing pads502,522each having contact elements503,521, respectively. In some embodiments, the number of fins that make up the set of fins504differ from the number of fins in set of fins514. In some embodiments, the number of contact elements503differ from the number of contact elements521. Gates505,515include landing pads506,516and gate lines508,519, respectively. Landing pads506,516include contact elements507,517, respectively. In some embodiments, contact regions501,520are coupled to source/drain.

FIG. 6illustrates a top view of an apparatus600showing a fin interconnect with contact elements, according to some embodiments of the invention. In some embodiments, apparatus600includes contact regions601and616, set of fins609and612, gates605and613, and interconnect contact region610. In some embodiments, contact region601,616include landing pads602,618, respectively. Landing pads602,618include contact elements603,617, respectively. Gates605,613include gate lines608,616and landing pads606,614, respectively. Landing pads606,614include contact elements607,615, respectively. In some embodiments, interconnect contact region610includes multiple contact elements611. In some embodiments, contact elements603,617and611are coupled to source/drain. In some embodiments contact elements603,617and611are coupled to other devices, circuits or reference potentials.

FIG. 7illustrates a top view of an apparatus700showing shared source and drain regions of stacked transistors using a part of the common fin without dedicated contact regions, according to some embodiments of the invention.

In some embodiments such as shown inFIG. 7provides for a savings in the area of an interconnect contact region provided between stacked transistors. This can be easily seen by comparing to the embodiment shown inFIG. 6. In700, there are no contact elements present for the shared region. The region of the fin709between the gates708and712is either homogenously implanted by a first implantation according to the implantation type of the landing pads702and713or receives a first implant close to the gate708and a second implant close to gate712according to the implant of region702and713, respectively. The border between the implantation of first type and second type on fin709between gates708and712is defined by a lithographic mask. In some embodiments, such as in the case of implantation of different types, the ohmic contact is ensured by a common silicide region between gate708and712.

FIG. 8illustrates a method of fabrication of a fin interconnect, according to some embodiments of the invention.

At802, the method includes forming a mask layer on a top surface of a silicon on insulator substrate. In some embodiments, the substrate is made of silicon. In other embodiments, the substrate can be made of other semiconductor materials, like germanium, and gallium arsenate. In an embodiment, the substrate can be of a BOX (Buried Oxide) structure. In another embodiment, the substrate can be of a SOI (Silicon On Insulator) structure.

At804, the method includes forming a first fin pattern and a second fin pattern on the mask layer. In some embodiments, the first fin pattern and the second fin pattern include a shared region interposed between their adjacent edges.

At806, the method includes forming a first plurality of fins determined by the first fin pattern. The method also includes forming a second plurality of fins determined by the second fin pattern. In some embodiments, the first plurality of fins and the second plurality of fins include an interconnect contact region corresponding to the shared region. In some embodiments, the method includes doping the first plurality of fins using a p-type dopant and doping the second plurality of fins using an n-type dopant.

At808, the method includes forming a first gate line operatively coupled and supported by the first plurality of fins and a second gate line operatively coupled and supported by the second plurality of fins.

At810, the method includes forming source and drain regions coupled to the first and second plurality of fins. In some embodiments, the method includes growing silicon in between each of the first plurality of fins and the second plurality of fins using a selective epitaxial growth (SEG) process.

In some embodiments described above, the fin is made of silicon. In other embodiments, the fin can be made of other semiconductor materials, like germanium, silicon carbide, gallium arsenate, as well as indium phosphate. In some embodiments, the fin may be coated with a thin film of silicide, for example, with a thickness of 10 nm approximately.

In some embodiments, the contact element is made of tungsten. In other embodiments, the contact element is made of materials such as tungsten, copper, silver, gold, and/or aluminum. The contact element may be produced by using conventional etching process, for example, etching an opening (or a hole) selectively to the bottom or the side of the fin, then filling the opening with tungsten (or other conductive material), thus forming the contact element, which partially wraps around the fin. Alternatively, before filling the opening, a thin film of TiN can be applied to the opening as a liner.

In some embodiments, the fin is substantially in the shape of a rectangle. In other embodiments, the fin is substantially in the shape of a rectangle with corners rounded. In an embodiment, the height to width ratio of the fin can be substantially in the range of 3:1 to 5:1. In an embodiment, the width of the fin is substantially 20 nm.

Such embodiments of the inventive subject matter may be referred to herein, individually and/or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description. In the previous discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including”, but not limited to . . . .”