SOLID-STATE IMAGING DEVICE AND ELECTRONIC EQUIPMENT

PLS is further suppressed. A solid-state imaging device includes: a first semiconductor substrate including a first semiconductor layer provided with a plurality of photoelectric conversion units that performs photoelectric conversion, and a first wiring layer provided on a surface side opposite to a light incident surface of the first semiconductor layer; a second semiconductor substrate including a second semiconductor layer provided with a charge holding unit that holds signal charge generated in the photoelectric conversion unit and a second wiring layer provided on one surface side of the second semiconductor layer, and overlapped with and bonded to the first semiconductor substrate such that the second wiring layer is positioned between the first wiring layer and the second semiconductor layer; and a light shielding layer provided in at least one of the first wiring layer or the second wiring layer at a position facing the charge holding unit in a thickness direction.

TECHNICAL FIELD

The present technology (technology according to the present disclosure) relates to a solid-state imaging device and electronic equipment, and particularly relates to a solid-state imaging device and electronic equipment including a charge holding unit.

BACKGROUND ART

Conventionally, a charge holding unit such as a floating diffusion has been used as a memory that temporarily holds signal charge photoelectrically converted by a photoelectric conversion unit such as a photodiode. However, in a case where signal charge is temporarily held in the floating diffusion, parasitic light sensitivity (PLS) may become a problem due to stray light. More specifically, when stray light enters the floating diffusion, photoelectric conversion is also performed inside the floating diffusion to generate signal charge, and the signal charge is erroneously detected. Therefore, in the following Patent Document 1, the position of the floating diffusion is separated from the optical center of the pixel in order to better inhibit stray light as compared with the related art.

CITATION LIST

Patent Document

SUMMARY OF THE INVENTION

Problems to be Solved by the Invention

An object of the present technology is to provide a solid-state imaging device and electronic equipment capable of further suppressing PLS.

Solutions to Problems

According to an aspect of the present technology, there is provided a solid-state imaging device including: a first semiconductor substrate including a first semiconductor layer provided with a plurality of photoelectric conversion units that performs photoelectric conversion, and a first wiring layer provided on a surface side opposite to a light incident surface of the first semiconductor layer; a second semiconductor substrate including a second semiconductor layer provided with a charge holding unit that holds signal charge generated in the photoelectric conversion unit and a second wiring layer provided on one surface side of the second semiconductor layer, and overlapped with and bonded to the first semiconductor substrate such that the second wiring layer is positioned between the first wiring layer and the second semiconductor layer; and a light shielding layer provided in at least one of the first wiring layer or the second wiring layer at a position facing the charge holding unit in a thickness direction.

According to another aspect of the present technology, there is provided electronic equipment including the solid-state imaging device and an optical system that forms an image of image light from a subject on the solid-state imaging device.

According to another aspect of the present technology, there is provided a solid-state imaging device including: a first semiconductor layer including a first region including a first semiconductor material and a second region including a second semiconductor material of which a quantum efficiency indicating a probability that photons are converted into electrons is lower than that of the first semiconductor material, and including a photoelectric conversion unit that performs photoelectric conversion and a charge holding unit that holds signal charge generated by the photoelectric conversion unit, in which the photoelectric conversion unit is provided in a region including at least the first region out of the first region and the second region, and the charge holding unit is provided in the second region.

According to another aspect of the present technology, there is provided electronic equipment including the solid-state imaging device and an optical system that forms an image of image light from a subject on the solid-state imaging device.

MODE FOR CARRYING OUT THE INVENTION

A preferred embodiment for implementing the present technology will be described below with reference to the drawings. Note that the embodiment hereinafter described shows an example of the representative embodiment of the present technology, and the scope of the present technology is not narrowed by the example.

In the following drawings, the same or similar parts are denoted by the same or similar reference numerals. It should be noted that the drawings are schematic, and a relationship between a thickness and planar dimensions, a ratio of the thicknesses between layers, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Furthermore, it is needless to say that the drawings include portions having different dimensional relationships and ratios.

Furthermore, the first to fourth embodiments shown below exemplify devices and methods for embodying the technical idea of the present technology, and the materials, shapes, structures, arrangements, and the like of the components are not specified as follows. Various modifications can be made to the technical idea of the present technology within the technical scope defined by the claims described in the claims.

The description will be made in the following order.1. First Embodiment2. Modification Example 1 of First Embodiment3. Modification Example 2 of First Embodiment4. Modification Example 3 of First Embodiment6. Second Embodiment7. Modification Example 1 of Second Embodiment8. Modification Example 2 of Second Embodiment9. Modification Example 3 of Second Embodiment10. Modification Example 4 of Second Embodiment11. Modification Example 5 of Second Embodiment12. Modification Example 6 of Second Embodiment13. Third Embodiment14. Fourth Embodiment

First Embodiment

The present embodiment will describe an example in which the present technology is applied to a solid-state imaging device1that is a back illumination type complementary metal oxide semiconductor (CMOS) image sensor. More specifically, the present embodiment will describe an example in which the present technology is applied to a distance image sensor that measures a distance by a time-of-flight (ToF) method, which is an example of the solid-state imaging device1.

As shown inFIG.1, a solid-state imaging device1according to the first embodiment of the present technology mainly includes a semiconductor chip2having a rectangular two-dimensional planar shape in plan view. That is, the solid-state imaging device1as a distance image sensor is mounted on the semiconductor chip2. The semiconductor chip2includes a rectangular pixel region2A arranged in a central portion, and a peripheral region2B arranged outside the pixel region2A to surround the pixel region2A, in a two-dimensional plane.

The pixel region2A is a light receiving surface that receives light condensed by an optical system202inFIG.29. As shown inFIG.1, in the pixel region2A, a plurality of pixels3is provided in an array along a row direction (X direction) and a column direction (Y direction) intersecting the row direction. Each pixel3includes a photoelectric conversion unit that performs photoelectric conversion. The thickness direction of the semiconductor chip2is parallel to the Z direction. The X direction and the Y direction are orthogonal to each other in the example ofFIG.1, but are not limited to the orthogonal state as long as they intersect each other. The Z direction is orthogonal to the X direction and the Y direction. Here, the Z direction is a thickness direction of the semiconductor chip2, that is, a thickness direction of a first semiconductor substrate20to be described later, and is also a thickness direction of a second semiconductor substrate40, a first semiconductor layer21, a first wiring layer31, a second semiconductor layer41, and a second wiring layer51to be described later.

A plurality of electrode pads14is arranged in the peripheral region2B. Each of the plurality of electrode pads14is arranged, for example, along four sides in a two-dimensional plane of the semiconductor chip2. Each of the plurality of electrode pads14is an input/output terminal used when the semiconductor chip2is electrically connected to an external device (not shown).

As shown inFIG.2, the semiconductor chip2includes a logic circuit13including a vertical drive circuit4, a column signal processing circuit5, a horizontal drive circuit6, an output circuit7, a control circuit8, and the like. The logic circuit13includes, for example, a complementary MOS (CMOS) circuit including an n-channel conductive type metal oxide semiconductor field effect transistor (MOSFET) and a p-channel conductive type MOSFET as field effect transistors.

The logic circuit13(specifically, the output circuit7) outputs the output voltage for each pixel3to the outside. The vertical drive circuit4sequentially selects the plurality of pixels3row by row, for example. In addition, the vertical drive circuit4controls application of a bias voltage VB to an anode24of a light absorption unit23to be described later. The column signal processing circuit5performs, for example, correlated double sampling (CDS) processing on the pixel signal output from each pixel3in the row selected by the vertical drive circuit4. The column signal processing circuit5extracts a signal level of a pixel signal by performing CDS processing, for example, and holds pixel data corresponding to the amount of light received by each pixel3. The horizontal drive circuit6sequentially outputs the pixel data held in the column signal processing circuit5to a horizontal signal line12, for example. The output circuit7performs signal processing on pixel signals sequentially supplied from each of the column signal processing circuits5through the horizontal signal line12, and outputs the signals. The control circuit8controls driving of each block (the vertical drive circuit4, the column signal processing circuit5, the horizontal drive circuit6, and the output circuit7) in the logic circuit13, for example.

FIG.3is an equivalent circuit diagram showing a configuration example of the pixel3. As shown inFIG.3, a bias voltage VB which is a negative voltage is applied to the anode24of the light absorption unit23, and a source of the transfer transistor43which is an active element is connected to a cathode25of the light absorption unit23. A floating diffusion44in a floating state is connected to the drain of the transfer transistor43. The floating diffusion44is connected to the source of the reset transistor45which is an active element and the gate of an amplification transistor47which is an active element. The source of the amplification transistor47is connected to the drain of a selection transistor46which is an active element, and the drain of the amplification transistor47is connected to a power source Vdd. The source of the selection transistor46is connected to a vertical signal line11. The drain of the reset transistor45is connected to the power source Vdd.

As shown in the longitudinal sectional view ofFIG.4A, the semiconductor chip2includes a first semiconductor substrate (photoelectric conversion substrate unit)20and a second semiconductor substrate (circuit substrate unit)40which are bonded to face each other. The first semiconductor substrate20includes the above-described pixel region2A, and the second semiconductor substrate40includes at least a part of the logic circuit such as a readout circuit. Here, the first semiconductor substrate20and the second semiconductor substrate40are overlapped with and bonded to each other with a bonding surface S as a boundary. In addition, the semiconductor chip2includes a planarization film71and a microlens layer72.

The first semiconductor substrate20includes a first semiconductor layer21which is an element side substrate and a first wiring layer31. The first semiconductor layer21has a first surface S1and a second surface S2positioned on sides opposite to each other in the thickness direction (Z direction). Here, the first surface S1may be referred to as a light incident surface or a back surface, and the second surface S2may be referred to as a surface opposite to the light incident surface or an element forming surface. The first wiring layer31is provided on the second surface S2of the first semiconductor layer21, and the planarization film71and the microlens layer72are laminated in this order on the first surface S1. The first wiring layer31has a third surface S3and a fourth surface S4positioned on sides opposite to each other in the thickness direction. The third surface S3is a surface on the first semiconductor layer21side and is in contact with the second surface S2. The fourth surface S4is a surface opposite to the surface on the first semiconductor layer21side (third surface S3). Note that the microlens layer72will be omitted inFIG.5and subsequent drawings.

The second semiconductor substrate40includes a second semiconductor layer41which is a circuit side substrate and a second wiring layer51. The second semiconductor layer41has a fifth surface S5and a sixth surface S6positioned on sides opposite to each other in the thickness direction. Here, the fifth surface S5may be referred to as a back surface, and the sixth surface S6may be referred to as one surface, an element forming surface, or a surface on the first semiconductor layer21side. The second wiring layer51is provided on the sixth surface S6of the second semiconductor layer41. The second wiring layer51has a seventh surface S7and an eighth surface S8positioned on sides opposite to each other in the thickness direction. The seventh surface S7is a surface on the second semiconductor layer41side and is in contact with the sixth surface S6. The eighth surface S8is a surface opposite to the surface on the second semiconductor layer41side (the seventh surface S7).

The second semiconductor substrate40is overlapped with and bonded to the first semiconductor substrate20such that the second wiring layer51is positioned between the first wiring layer31and the second semiconductor layer41. Specifically, the first semiconductor substrate20and the second semiconductor substrate40are overlapped and bonded by being overlapped with and bonded to the fourth surface S4of the first wiring layer31and the eighth surface S8of the second wiring layer51. The first semiconductor substrate20and the second semiconductor substrate40are also electrically connected.

<Configuration of First Semiconductor Substrate>

As shown inFIGS.4A and4B, the first semiconductor substrate20includes a separation unit22that divides the first semiconductor layer21into a plurality of regions21a. The separation unit22electrically and optically separates the adjacent regions21afrom each other. The separation unit22is, for example, a groove-shaped separation unit. The separation unit22has, for example, a single-layer structure including silicon oxide (SiO2) or a multilayer structure in which both sides of a metal film are sandwiched between insulating films.

(Configuration of First Semiconductor Layer)

As shown inFIG.4A, each of the regions21aof the first semiconductor layer21includes the light absorption unit23, a first contact region24which is a first conductive type (for example, p-type) diffusion region, and a second contact region25which is a second conductive type (for example, n-type) diffusion region that is different from the first conductive type. As the first semiconductor layer21, for example, a semiconductor substrate including single crystal silicon is used.

When light L enters the light absorption unit23from the first surface S1side (light incident surface side), the light absorption unit23performs photoelectric conversion. That is, the light absorption unit23functions as a photoelectric conversion unit that absorbs the light L and generates electrons (signal charge). The light absorption unit23is a first conductive type or second conductive type semiconductor region, but will be described as the first conductive type semiconductor region. The impurity concentration of the light absorption unit23is lower than the impurity concentration of the first contact region24and the second contact region25.

A bias voltage VB is applied to the first semiconductor layer21in order to push out signal charge generated in the light absorption unit23from the first semiconductor substrate20side to the second semiconductor substrate40side. More specifically, the bias voltage VB is applied to the first contact region24which is the first conductive type diffusion region. The bias voltage VB is a negative voltage. When the bias voltage VB is applied to the first contact region24, a potential gradient is formed in the light absorption unit23, and signal charge is collected in the second conductive type second contact region25by the potential gradient. The first contact region24is provided in the first semiconductor layer21at a position closer to the first surface S1, and more specifically, a part thereof faces the first surface S1. In addition, the bias voltage VB is applied to the first contact region24via a via26a, a wiring26b, a through-silicon via (TSV)26cpenetrating the first semiconductor layer21, a wiring (not shown), and the like, which are included in the first semiconductor substrate20. The first contact region24reduces ohmic contact resistance with the via26aand functions as an anode.

The second contact region25, which is a diffusion region of the second conductive type, is provided in the first semiconductor layer21at a position closer to the second surface S2, and more specifically, a part thereof faces the second surface S2. The second contact region25reduces ohmic contact resistance with a via33to be described later and functions as a cathode. The second contact region25outputs signal charge from the first semiconductor layer21.

(Configuration of First Wiring Layer)

The first wiring layer31includes a first interlayer insulating film (insulating film)32, a via33, and a first metal film M1on the element side. The first wiring layer31has a structure formed by laminating the first metal film M1on the element side with the first interlayer insulating film32interposed therebetween.

The first metal film M1on the element side includes a first connection pad34. The first connection pad34is a connection pad provided in the first wiring layer31. The first connection pad34faces the fourth surface S4of the first wiring layer31. In addition, the first connection pad34is provided at a position facing the floating diffusion44(hereinafter represented as FD44) in the Z direction as shown in the longitudinal sections ofFIGS.4A and5. The first connection pad34includes metal. The first connection pad34includes, for example, copper (Cu). Furthermore, the first connection pad34also functions as a light shielding layer60that shields light that has entered from the light incident surface side.

The via33electrically connects the first semiconductor layer21and the first connection pad34. More specifically, the via33electrically connects the second contact region25and the first connection pad34. The via33includes metal.

<Configuration of Second Semiconductor Substrate>

(Configuration of Second Semiconductor Layer)

As shown inFIGS.4A and4C, the second semiconductor layer41includes a third contact region42, the transfer transistor43, the FD44, the reset transistor45, the selection transistor46, the amplification transistor47, and a well contact48. As the second semiconductor layer41, for example, a semiconductor substrate including single crystal silicon is used.

The third contact region42is a diffusion region of the same conductive type as the second contact region25, that is, the second conductive type. The third contact region42is electrically connected to the second contact region25, and receives signal charge from the second contact region25when the bias voltage VB is applied to the first contact region24. The third contact region42reduces ohmic contact resistance with a via53to be described later.

The transfer transistor43is, for example, an n-channel MOSFET. The transfer transistor43is provided to form a channel between the third contact region42and the FD44, and includes a gate insulating film (not shown) and a transfer gate electrode43G sequentially laminated on the sixth surface S6.

The transfer transistor43transfers the signal charge obtained by photoelectric conversion of the light absorption unit23to the FD44. More specifically, the transfer transistor43transfers the signal charge from the third contact region42that functions as the source region to the FD44that functions as the drain region according to the voltage between the gate and the source. The transfer transistor43is conventionally provided in the first semiconductor layer21, but is repositioned to the second semiconductor layer41in the present technology.

The FD44is a charge accumulation region that temporarily accumulates the signal charge transferred from the third contact region42. That is, the FD44functions as a charge holding unit. The FD44is a floating diffusion region of the same conductive type as the second contact region25, that is, the second conductive type. The FD44is provided in the second semiconductor layer41. Specifically, the FD44is embedded in the second semiconductor layer41. The FD44is conventionally provided in the first semiconductor layer21, but is repositioned to the second semiconductor layer41in the present technology.

The reset transistor45is, for example, an n-channel MOSFET. The reset transistor45includes a gate insulating film (not shown) and a reset gate electrode (RST)45G sequentially laminated on the sixth surface S6. The reset transistor45resets the potential of the FD44to a predetermined potential according to the voltage between the gate and the source.

The selection transistor46is, for example, an n-channel MOSFET. The selection transistor46includes a gate insulating film (not shown) and a selection gate electrode (SEL)46G sequentially laminated on the sixth surface S6. The selection transistor46controls the output timing of the pixel signal from the readout circuit according to the voltage between the gate and the source.

The amplification transistor47is, for example, an re-channel MOSFET. The amplification transistor47includes a gate insulating film (not shown) and an amplification gate electrode (AMP)47G sequentially laminated on the sixth surface S6. When the selection transistor46is in an on state, the amplification transistor47amplifies the potential of the FD44.

The well contact48is fixed at a predetermined potential.

(Configuration of Second Wiring Layer)

As shown inFIG.4A, the second wiring layer51includes a second interlayer insulating film (insulating film)52, the first metal film M1to a fifth metal film M5on the circuit side, and the via53. The second wiring layer51has a structure in which the first metal film M1to the fifth metal film M5on the circuit side are laminated in this order from the seventh surface S7side via the second interlayer insulating film52.

The first metal film M1on the circuit side includes a metal layer54, the second metal film M2includes a metal layer55, the third metal film M3includes a metal layer56, the fourth metal film M4includes a metal layer57, and the fifth metal film M5includes a second connection pad58. For example, the first metal film M1on the circuit side includes a plurality of metal layers54. The plurality of metal layers54is formed by the same process. The same applies to the first metal film M1and the second metal film M2to the fifth metal film M5on the element side.

The metal layer54to the metal layer57include metal. The metal layers54to57include, for example, copper (Cu) or aluminum (Al). The second connection pad58includes metal. The second connection pad58includes, for example, copper (Cu).

Among the plurality of metal layers54, the metal layer54provided at a position facing the FD44in the Z direction is referred to as a metal layer54ain order to be distinguished from the other metal layers54. Furthermore, among the plurality of metal layers55, the metal layer55provided at a position facing the FD44in the Z direction is referred to as a metal layer55ain order to be distinguished from the other metal layers55. Each of the metal layer54a, the metal layer55a, and the second connection pad58functions as the light shielding layer60that shields light that has entered from the light incident surface side.

The via53electrically connects metal films of different layers. The via53electrically connects any two of the first metal film M1to the fifth metal film M5on the circuit side. For example, the via53electrically connects the metal layer54and the metal layer55. Further, the via53electrically connects the metal film and the gate electrode. For example, the via53electrically connects the metal layer54and the transfer gate electrode43G. Moreover, the via53electrically connects the second semiconductor layer41, more specifically, the third contact region42and the first metal film M1. For example, the via53electrically connects the third contact region42and the metal layer54. The via53includes metal.

The second connection pad58is a connection pad provided in the second wiring layer51. The second connection pad58faces the eighth surface S8of the second wiring layer51. The second connection pad58is provided at a position facing the FD44in the Z direction. The second connection pad58is electrically connected to the second semiconductor layer41, more specifically, the third contact region42via at least one of the via53or the wiring. For example, as shown in the drawing, the second connection pad58is electrically connected to the third contact region42from the metal layer54via the metal layer57and the via53. The second connection pad58is bonded to first connection pad34. As a result, the first semiconductor layer21of the first semiconductor substrate20and the second semiconductor layer41of the second semiconductor substrate40are electrically connected. More specifically, the second contact region25and the third contact region42are electrically connected.

<Configuration of Light Shielding Layer>

Hereinafter, the light shielding layer60will be described with reference toFIGS.4A,4C, and5. The light shielding layer60has a role of shielding at least a part of the light that has entered from the light incident surface before the light reaches the FD44. Therefore, the light shielding layer60is provided closer to the light incident surface than the sixth surface S6of the second semiconductor layer41provided with the FD44in the thickness direction of the solid-state imaging device1. More specifically, the light shielding layer60is provided between the first semiconductor layer21and the second semiconductor layer41, that is, in the first wiring layer31and the second wiring layer51. Furthermore, the light shielding layer60is provided at a position facing the FD44in the Z direction. That is, the position of the light shielding layer60in the horizontal direction is a position facing the FD44. Here, the horizontal direction is a direction perpendicular to the Z direction.

A plurality of light shielding layers60is provided. The light shielding layer60includes the first metal film M1, the second metal film M2, and the fifth metal film M5on the circuit side and the first metal film M1on the element side, which are provided in the first wiring layer31and the second wiring layer51. That is, the light shielding layer60includes the second connection pad58including the metal layer54aincluding the first metal film M1on the circuit side, the metal layer55aincluding the second metal film M2, and the fifth metal film M5, and the first connection pad34including the first metal film M1on the element side.

FIG.4Cis a diagram showing a relative relationship between the respective components when the second semiconductor layer41is viewed in cross section on the surface of the sixth surface S6. InFIG.4C, a contour54bof the metal layer54a, a contour34bof the first connection pad34, and a contour58bof the second connection pad58are projected. In plan view, the metal layer54a, the first connection pad34, and the second connection pad58overlap the entire FD44. In other words, in plan view, the contour54band the contours34band58bare outside the contour44bof the FD44. Further, the contours34band58bare outside the contour54b. When the light shielding layer60overlaps the entire FD44, the effect of covering the FD44increases. Therefore, the light L traveling along the thickness direction of the second wiring layer51hardly enters the FD44. Furthermore, the larger the area of the light shielding layer60, the greater the effect of covering the FD44. Therefore, the light L traveling along the oblique direction hardly enters the FD44. The oblique direction is a direction intersecting the Z direction.

The light shielding layer60is preferably a metal layer closer to the second semiconductor layer41, more specifically, the FD44in the thickness direction of the second wiring layer51. The metal layer54ais a metal layer closest to the second semiconductor layer41in the thickness direction of the second wiring layer51among the plurality of light shielding layers60provided at positions facing the FD44in the Z direction in the second wiring layer51.

Furthermore, the light shielding layer60preferably includes a metal film closer to the second semiconductor layer41, more specifically, the FD44in the thickness direction of the second wiring layer51. The metal layer54aincludes the first metal film M1on the circuit side which is a metal film closest to the second semiconductor layer41, more specifically, the FD44in the thickness direction of the second wiring layer51among the plurality of layers of the first metal film M1to the fifth metal film M5on the circuit side provided in the second wiring layer51.

The light shielding effect of the light shielding layer60increases as the distance between the light shielding layer60and the second semiconductor layer41in the thickness direction of the second wiring layer51, more specifically, the distance between the light shielding layer60and the FD44decreases. Therefore, from the viewpoint of the distance distribution in the thickness direction of the second wiring layer51, the metal layer54ais more advantageous in light shielding than the other light shielding layers60.

A distance in the thickness direction of the second wiring layer51between the metal layer54aand the FD44is represented as a distance a. As the distance a is smaller, it is more advantageous for light shielding. That is, as the distance a decreases, the metal layer54acomes closer to the FD44, and the effect that the metal layer54acovers the FD44increases. Then, the light L traveling along the oblique direction hardly enters the FD44.

In addition, a distance in the thickness direction of the second wiring layer51between the metal layer54aand the second connection pad58is represented as a distance b. Comparing the distance a with the distance b, the distance a is equal to or less than the distance b (a b). Furthermore, the distance a may be significantly smaller than the distance b (a<<b).

As shown inFIGS.4A and5, the second connection pad58is a light shielding layer closest to the light incident surface among the light shielding layers60provided in the second wiring layer51, and is a light shielding layer farthest from the FD44. In a case where a plurality of metal layers is present between the second connection pad58and the metal layer54a, it may be difficult to reduce the distance b. However, increasing the width f and the area of the second connection pad58is less restricted than increasing the area of the metal layer54a. Therefore, the area of the second connection pad58can be made significantly larger than the area of the metal layer54a. The second connection pad58having the large width f and area is effective as the light shielding layer60even when the second connection pad58is far from the FD44.

The first connection pad34is a light shielding layer closest to the light incident surface among the light shielding layers60provided in the first wiring layer31and the second wiring layer51, and is a light shielding layer farthest from the FD44. The first connection pad34also has the same configuration and effect as those of the second connection pad58.

As shown inFIG.5, the width d of the metal layer54ain the X direction is larger than the width c of the FD44in the X direction. On the other hand, the width e of the metal layer55ain the X direction is smaller than the width c of the FD44in the X direction. The metal layer54adoes not overlap the entire FD44, and overlaps only a part of the FD44. As described above, even in a case where the light shielding layer60overlaps only a part of the FD44, at least a part of the light L can be shielded. Then, the greater the overlap between the light shielding layer60and the FD44, the greater the light shielding effect of the light shielding layer60.

In addition, although the metal layer54a, the metal layer55a, the first connection pad34, and the second connection pad58function as the light shielding layer60alone, the light shielding effect is further increased by combining the plurality of light shielding layers60. This is because, when the light L travels from the light incident surface side to the second semiconductor layer41side, the light L is sequentially blocked by the light shielding layers60provided at different positions in the thickness direction of the first wiring layer31and the second wiring layer51.

In particular, the combination of the metal layer54aclosest to the second semiconductor layer41in the thickness direction of the second wiring layer51among the plurality of metal layers provided in the second wiring layer51at positions facing the FD44in the Z direction, and at least one of a connection pad out of the first connection pad34provided in the first wiring layer31and the second connection pad58provided in the second wiring layer51and bonded to the first connection pad34is useful. This is because the combination of the first connection pad34or the second connection pad58having a large area and the metal layer54aclosest to the FD44can take advantage of each other's strengths.

<Reset Operation of FD and Light Absorption Unit>

Next, a reset operation of the FD44and the light absorption unit23will be described with reference to the timing chart ofFIG.6. By resetting the FD44and the light absorption unit23, parasitic light sensitivity (PLS) can be further suppressed.

A period from time t0to time t1is a first reset period in which the FD44and the light absorption unit23are reset. A period from time t1to time t2is an accumulation period in which signal charge generated by photoelectric conversion is accumulated. A period from time t2to time t3is a transfer period in which the signal charge accumulated by the transfer transistor43is transferred to the FD44. A period from time t3to time t4is a second reset period in which the light absorption unit23is reset.

Furthermore,FIG.6shows on/off timing of the reset transistor45(RST), timing of application of the bias voltage VB to the light absorption unit23, and on/off timing of the transfer transistor43(TRG). The reset transistor45is in an on state only during the first reset period. The bias voltage VB is applied to the light absorption unit23only during the accumulation period. Then, the transfer transistor43is in an on state only during the transfer period.

In the first reset period, the reset transistor45is turned on, and the signal charge remaining in the FD44is discharged. In addition, the application of the bias voltage VB to the light absorption unit23is stopped. When the application of the bias voltage VB to the light absorption unit23is stopped, the signal charge generated by the photoelectric conversion is recombined in the light absorption unit23and disappears. In this manner, PLS can be suppressed by removing the signal charge remaining in the FD44and the light absorption unit23.

During the next accumulation period, signal charge is generated by photoelectric conversion of the light absorption unit23. In addition, during this accumulation period, the bias voltage VB is applied to the light absorption unit23in order to push out signal charge from the first semiconductor substrate20side to the second semiconductor substrate40side.

During the transfer period, the signal charge pushed out to the second semiconductor substrate40side is transferred to the FD44by the transfer transistor43. In addition, during the transfer period, the application of the bias voltage VB to the light absorption unit23is stopped, and the signal charge in the light absorption unit23is recombined and disappears.

During the last second reset period, a state where the application of the bias voltage VB to the light absorption unit23is stopped continues, and the signal charge in the light absorption unit23is recombined and disappears.

In the solid-state imaging device1according to the first embodiment, since the FD44conventionally provided in the first semiconductor layer21is repositioned to the second semiconductor layer41, the metal layers provided in the first wiring layer31and the second wiring layer51can be used as the light shielding layer60that suppresses incidence of the light L on the FD44.

Furthermore, the light shielding layer60is provided at a position facing the FD44in the Z direction. Therefore, since at least a part of the light L traveling toward the FD44is blocked by the light shielding layer60, it is possible to suppress photoelectric conversion from being performed in the FD44. As a result, PLS can be suppressed.

Furthermore, in the solid-state imaging device1according to the first embodiment, since the light shielding layer60overlaps the entire FD44in plan view, the effect of covering the FD44is increased. The light L traveling along the thickness direction of the solid-state imaging device1can be shielded.

Furthermore, the metal layer54ais a light shielding layer closest to the second semiconductor layer41in the thickness direction of the second wiring layer51among the plurality of light shielding layers60provided at positions facing the FD44in the Z direction in the second wiring layer51. In addition, the metal layer54aincludes a metal film closer to the second semiconductor layer41in the thickness direction of the second wiring layer51. As a result, the distance a in the thickness direction of the second wiring layer51between the metal layer54awhich is the light shielding layer60and the FD44can be reduced, and thus the light L traveling along the oblique direction hardly enters the FD44.

In the present first embodiment, the metal layer54aoverlaps the entire FD44in plan view, but may overlap only a part of the FD44similar to the metal layer55a.FIG.7is an example of such a configuration. Among the four sides54b-1,54b-2,54b-3, and54b-4constituting the contour54bof the metal layer54a, some or all of the sides may be positioned inside the contour44bof the FD44. Even with such a configuration, the metal layer54acan block at least a part of the light L, and thus, has a light shielding effect. Then, the greater the overlap between the light metal layer54aand the FD44, the greater the light shielding effect of the metal layer54a.

In addition, in the present first embodiment, the light shielding layer60such as the metal layer54aand the metal layer55amay be a metal layer dedicated to light shielding or may have a function as an electrical conduction path or a terminal. In the present first embodiment, the first connection pad34and the second connection pad58electrically connect the first semiconductor substrate20and the second semiconductor substrate40, but may be a metal layer dedicated to light shielding.

Note that, in the present first embodiment, the solid-state imaging device1is a distance image sensor that performs distance measurement by the ToF method, but the solid-state imaging device1may be a solid-state imaging device that captures a two-dimensional image having no distance information. In that case, the solid-state imaging device1may include a color filter or the like.

Furthermore, the present technology can be applied to both a global shutter that simultaneously shuts off the shutter in all rows and a rolling shutter that shuts off the shutter in each row. Since the global shutter has a slower reading speed than the rolling shutter, the effect of applying the present technology is greater from the viewpoint of PLS suppression.

In the present first embodiment, the bias voltage VB is a negative voltage, but may be fixed to the ground (reference potential).

In addition, the number of layers of the metal film on the element side and the number of layers of the metal film on the circuit side are not limited to the number of layers described in the first embodiment.

Modification Example 1 of First Embodiment

Modification Example 1 of the first embodiment of the present technology shown inFIG.8will be described below. The solid-state imaging device1according to Modification Example 1 of the present first embodiment is different from the solid-state imaging device1according to the first embodiment described above in the position of the first contact region, and the other configurations of the solid-state imaging device1are basically similar to those of the solid-state imaging device1according to the first embodiment described above. Note that the components already described will be denoted by the same reference numerals, and the description thereof will be omitted.

The first contact region24is provided in the first semiconductor layer21at a position closer to the second surface S2, and more specifically, a part thereof faces the second surface S2. In addition, the bias voltage VB is applied to the first contact region24via the via26d, the wiring26e, and the like of the first semiconductor substrate20.

Even in the solid-state imaging device1according to Modification Example 1 of the first embodiment, the same effects as those of the solid-state imaging device1according to the first embodiment described above can be obtained.

Modification Example 2 of First Embodiment

Modification Example 2 of the first embodiment of the present technology shown inFIGS.9A and9Bwill be described below. The solid-state imaging device1according to Modification Example 2 of the present first embodiment is different from the solid-state imaging device1according to the first embodiment described above in that a discharge transistor49is provided, and the other configurations of the solid-state imaging device1are basically similar to those of the solid-state imaging device1according to the first embodiment described above. Note that the components already described will be denoted by the same reference numerals, and the description thereof will be omitted.

The second semiconductor layer41includes the third contact region42, the transfer transistor43, the FD44, the reset transistor45, the selection transistor46, the amplification transistor47, the well contact48, and the discharge transistor49.

The discharge transistor49is, for example, an n-channel MOSFET. The discharge transistor49that includes a gate insulating film (not shown) and a discharge gate electrode (OFG)49G which are sequentially laminated on the sixth surface S6has the third contact region42as a source, and discharges the signal charge from the third contact region42according to the voltage between the gate and the source.

<Reset Operation of FD and Light Absorption Unit>

Next, a reset operation of the FD44and the light absorption unit23will be described with reference to the timing chart ofFIG.10. Note that the same components as those ofFIG.6of the first embodiment will be denoted by the same reference numerals, and the description thereof will be omitted.

FIG.10further shows on/off timing of the discharge transistor49(OFG). Then, the discharge transistor49is in an on state during the first reset period and the second reset period, and in an off state during the accumulation period and the transfer period. Furthermore, unlike the case of the first embodiment described above, the bias voltage VB is applied to the light absorption unit23during all the periods of the first reset period, the accumulation period, the transfer period, and the second reset period.

When the discharge transistor49is turned on during the first reset period and the second reset period, signal charge is discharged from the third contact region42during the same period. As a result, PLS can be suppressed even when the bias voltage VB is constantly applied to the light absorption unit23.

Even in the solid-state imaging device1according to Modification Example 2 of the first embodiment, the same effects as those of the solid-state imaging device1according to the first embodiment described above can be obtained.

Note that, as shown inFIG.11, the solid-state imaging device1according to Modification Example 1 of the first embodiment may include the discharge transistor49.

Modification Example 3 of First Embodiment

Modification Example 3 of the first embodiment of the present technology shown inFIGS.12A and12Bwill be described below. The solid-state imaging device1according to Modification Example 3 of the present first embodiment is obtained by applying the technology of the first embodiment described above to a memory-holding type global shutter, and other configurations of the solid-state imaging device1are basically similar to those of the solid-state imaging device1of the first embodiment described above. Note that the components already described will be denoted by the same reference numerals, and the description thereof will be omitted.

The second semiconductor layer41includes a first transfer transistor431having a first transfer gate electrode431G and a second transfer transistor432having a second transfer gate electrode432G instead of the transfer transistor43of the first embodiment. The second semiconductor layer41further includes a memory44M and an MC gate44MG. Other configurations are equivalent to those of the first embodiment.

The first transfer transistor431transfers the signal charge from the third contact region42to the memory44M. The memory44M is a charge accumulation region that temporarily accumulates the signal charge transferred from the third contact region42. That is, the memory44M functions as a charge holding unit. The memory44M is a floating diffusion region of the same conductive type as the second contact region25, that is, the second conductive type. The memory44M is provided in the second semiconductor layer41. Specifically, the memory44M is embedded in the second semiconductor layer41. The memory44M is conventionally provided in the first semiconductor layer21, but is repositioned to the second semiconductor layer41in the present technology. The second transfer transistor432transfers the signal charge accumulated in the memory44M to the FD44. The FD44is a charge accumulation region that temporarily accumulates the signal charge transferred from the memory44M. That is, the FD44functions as a charge holding unit.

<Configuration of Light Shielding Layer>

The light shielding layer60shields at least a part of the light that has entered from the light incident surface before the light reaches the FD44and the memory44M. InFIG.12A, the metal layer54to the metal layer57will be omitted in the drawing, but at least one of the metal layers functions as the light shielding layer60of the memory44M.

Even in the solid-state imaging device1according to Modification Example 3 of the first embodiment, the same effects as those of the solid-state imaging device1according to the first embodiment described above can be obtained.

Second Embodiment

The second embodiment of the present technology shown inFIGS.13A to13Cwill be described below. The solid-state imaging device1according to the present second embodiment is different from the solid-state imaging device1according to the first embodiment described above in that, in the first semiconductor layer21, the photoelectric conversion unit is provided in the first region including the first semiconductor material, and the floating diffusion is provided in the second region including the second semiconductor material having a lower quantum efficiency than that of the first semiconductor material, and other configurations of the solid-state imaging device1are basically similar to those of the solid-state imaging device1according to the first embodiment described above. Note that the components already described will be denoted by the same reference numerals, and the description thereof will be omitted.

<Configuration of First Semiconductor Substrate>

(Configuration of First Semiconductor Layer)

As shown inFIG.29, distance image equipment201acquires a distance image according to a distance to a subject by receiving light (modulated light or pulsed light) projected from a light source device211toward the subject and reflected on a surface of the subject. At that time, the light source device211emits light of a specific wavelength or a certain wavelength band, and the solid-state imaging device receives the light. In the second embodiment of the present technology, the first semiconductor material and the second semiconductor material having different sensitivities to light emitted from the light source device211are used.

The first semiconductor layer21includes a first region27including a first semiconductor material and a second region28including a second semiconductor material having a quantum efficiency lower than that of the first semiconductor material. Here, the quantum efficiency indicates a probability (efficiency) that photons are converted into electrons. That is, for light of a specific wavelength, the quantum efficiency of the second semiconductor material is lower than the quantum efficiency of the first semiconductor material. The combination of the first semiconductor material and the second semiconductor material is a combination of two different materials of silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), and copper indium gallium selenium (CIGS), and the second semiconductor material is a material having lower quantum efficiency out of the two materials. In addition, silicon has the lowest quantum efficiency among the above-described materials. Therefore, the second semiconductor material may be silicon, and the first semiconductor material combined with the second semiconductor material may be any one of germanium, silicon germanium, gallium arsenide, indium gallium arsenide, and copper indium gallium selenium.

In the second embodiment of the present technology, a description will be given on the assumption that the light source device211emits IR light (infrared light) and the solid-state imaging device receives IR light. Furthermore, in the second embodiment of the present technology, a combination of germanium (first semiconductor material) and silicon (second semiconductor material) will be described as an example.

Each of the regions21aof the first semiconductor layer21includes a first region27including germanium and a second region28including silicon. The first region27and the second region28are three-dimensional regions. The second region28is formed, for example, by cutting a part of a wafer including germanium and embedding silicon in the cut part. Furthermore, as another example, the second region28may be formed by growing silicon at a scraped part of the germanium wafer, or the like. Silicon is lower in quantum efficiency and sensitivity to IR light than germanium.

As shown inFIG.13A, the second region28is provided in the first semiconductor layer21at a position closer to the second surface S2in the thickness direction of the first semiconductor layer21. In addition, the second region28faces the second surface S2which is a surface opposite to the light incident surface among surfaces of the first semiconductor layer21. More specifically, as shown inFIG.13B, the second region28faces the second surface S2only in the first range S21that is a part of the second surface S2. The first range S21is a region surrounded by a contour line21b.

The first region27is present around a surface other than the surface facing the first range S21of the second region28. In particular, only the first region27is provided as a region at a part of the first semiconductor layer21closer to the light incident surface than the second region28in the thickness direction. In addition, the first region27faces the entire partial surface of the second surface S2other than the first range S21.

Each of the regions21aof the first semiconductor layer21includes a photodiode29, the transfer transistor43, a floating diffusion441(hereinafter referred to as an FD441), and the discharge transistor49.

The photodiode29is provided in the first region27including germanium. That is, a material having sensitivity in a long wavelength band as compared with silicon is used for the photodiode29. When the light L enters the photodiode29from the first surface S1side (light incident surface side), the photodiode29performs photoelectric conversion. That is, the photodiode29functions as a photoelectric conversion unit that absorbs the light L and generates electrons (signal charge).

The transfer transistor43is, for example, an n-channel MOSFET. The transfer transistor43is provided to form a channel between the photodiode29and the FD441, and includes the gate insulating film (not shown) and the transfer gate electrode43G sequentially laminated on the second surface S2.

The transfer transistor43transfers the signal charge from the photodiode29that functions as the source region to the FD441that functions as the drain region according to the voltage between the gate and the source.

The FD441is provided in the second region28including silicon. The FD441is a charge accumulation region that temporarily accumulates the signal charge transferred from the photodiode29. That is, the FD441functions as a charge holding unit. The FD441is, for example, a floating diffusion region of the second conductive type.

The discharge transistor49is, for example, an n-channel MOSFET. The discharge transistor49that includes a gate insulating film (not shown) and the discharge gate electrode (OFG)49G which are sequentially laminated on the second surface S2has the photodiode29as a source, and discharges the signal charge from the photodiode29according to the voltage between the gate and the source.

(Configuration of First Wiring Layer)

The first wiring layer31includes the first interlayer insulating film (insulating film)32, the via33, and the first connection pad34. The via33electrically connects the FD441and the first connection pad34.

<Configuration of Second Semiconductor Substrate>

(Configuration of Second Semiconductor Layer)

As shown inFIGS.13A and13C, the second semiconductor layer41includes a floating diffusion442(hereinafter represented as an FD442), the reset transistor45, the selection transistor46, the amplification transistor47, and the well contact48. As the second semiconductor layer41, for example, a semiconductor substrate including single crystal silicon is used.

The FD442is a charge accumulation region that is electrically connected to the FD441and temporarily accumulates signal charge generated by photoelectric conversion. That is, the FD442functions as a charge holding unit. The FD442is, for example, a floating diffusion region of the second conductive type.

The reset transistor45resets the potential of the FD442to a predetermined potential according to the voltage between the gate and the source.

(Configuration of Second Wiring Layer)

The second wiring layer51includes the second interlayer insulating film (insulating film)52, the via53, a metal layer59which is a wiring, and the second connection pad58.

The FD442and the second connection pad58are electrically connected via the via53. The FD442and the second connection pad58may be electrically connected via a metal layer (not shown) in addition to the via53.

The second connection pad58is bonded to the first connection pad34. As a result, the FD441and the FD442are electrically connected. In addition, the amplification gate electrode47G and the second connection pad58are electrically connected via the via53and the metal layer59.

The IR light is light having a wavelength of approximately 780 nm to 1 mm. Germanium is sensitive to light mainly in a long wavelength band of 1000 nm to 1500 nm. That is, germanium performs photoelectric conversion mainly on light of 1000 nm to 1500 nm. In contrast, silicon exhibits sensitivity mainly to light of 400 nm to 800 nm. That is, silicon performs photoelectric conversion mainly on light of 400 nm to 800 nm. That is, the sensitivity of silicon to IR light is lower than the sensitivity of germanium. In other words, for IR light, the quantum efficiency of silicon is lower than the quantum efficiency of germanium.

In a case where germanium and silicon are irradiated with IR light of the same intensity, the signal charge generated by photoelectric conversion with silicon is sufficiently smaller than the amount of signal charge generated by photoelectric conversion with germanium. Therefore, in a case where the photodiode29provided in the first region27including germanium and the FD441provided in the second region28including silicon are irradiated with IR light of the same intensity, the amount of signal charge generated by photoelectric conversion in the FD441is sufficiently smaller than the amount of signal charge generated by photoelectric conversion in the photodiode29.

As described above, in the solid-state imaging device1according to the second embodiment, different materials are used for the FD441and the photodiode29. Thereby, the photoelectric conversion in the FD441can be suppressed while maintaining the photoelectric conversion in the photodiode29using the difference in quantum efficiency of the material. As a result, the influence of PLS can be suppressed.

In addition, in the solid-state imaging device1according to the second embodiment, the first region27including germanium is present in a region of the first semiconductor layer21closer to the light incident surface than the second region28in the thickness direction of the first semiconductor layer21. Therefore, since the IR light incident on the first semiconductor layer21from the light incident surface is first absorbed by germanium, the intensity thereof is weakened before reaching the FD441. As described above, since the first region27including germanium absorbs light to play a role of light shielding, photoelectric conversion in the FD441can be further suppressed. As a result, the influence of PLS can be further suppressed.

Note that the solid-state imaging device1according to the second embodiment of the present technology has a configuration in which the first semiconductor substrate20and the second semiconductor substrate40are bonded to each other, but as shown inFIG.14, only the first semiconductor substrate20may be included as a substrate. In that case, the reset transistor45, the selection transistor46, and the amplification transistor47are also provided in the first semiconductor layer21. Further, the reset transistor45, the selection transistor46, and the amplification transistor47are provided in the second region28of the first semiconductor layer21.

Modification Example 1 of Second Embodiment

Modification Example 1 of the second embodiment of the present technology shown inFIGS.15A and15Bwill be described below. The solid-state imaging device1according to Modification Example 1 of the present second embodiment is different from the solid-state imaging device1according to the second embodiment described above in that the second region28faces the entire surface of the second surface S2, and is present with the same film thickness in the FD441and a part of the photodiode29, and the other configurations of the solid-state imaging device1are basically similar to those of the solid-state imaging device1according to the second embodiment described above. Note that the components already described will be denoted by the same reference numerals, and the description thereof will be omitted.

<Configuration of First Semiconductor Substrate>

(Configuration of First Semiconductor Layer)

As shown inFIG.15A, the second region28is provided in the first semiconductor layer21at a position closer to the second surface S2in the thickness direction of the first semiconductor layer21. In addition, as shown inFIG.15B, the second region28faces the entire surface of the second surface S2which is a surface opposite to the light incident surface among surfaces of the first semiconductor layer21. That is, the first semiconductor layer21has the first region27and the second region28provided in layers. The film thickness of the second region28is uniformly provided in the first semiconductor layer21. As shown inFIG.15A, the thickness h, which is the thickness of the FD441in the Z direction, is equal to or less than the thickness g, which is the thickness (film thickness) of the second region28in the Z direction (h g). In addition, only the first region27is provided as a region at a part of the first semiconductor layer21closer to the light incident surface than the second region28in the thickness direction.

The photodiode29is provided in a region including both the first region27including germanium and the second region28including silicon. That is, the photodiode29contains both germanium and silicon. Here, the quantum efficiency of silicon with respect to IR light is lower than that of germanium. However, the photodiode29has the first region27including germanium at a position closer to the light incident surface and the second region28including silicon at a position closer to the second surface S2opposite to the light incident surface, in the thickness direction of the first semiconductor layer21. Therefore, the photodiode29performs photoelectric conversion mainly in the first region27. Since the first region27is positioned far from the light incident surface side in the photodiode29, the first region27does not greatly contribute to the photoelectric conversion of the photodiode29. The FD441is provided in the second region28including silicon. Furthermore, since the second region28has a uniform film thickness, the second region28is present with the same film thickness in the FD441and a part of the photodiode29.

Even in the solid-state imaging device1according to Modification Example 1 of the second embodiment, the same effects as those of the solid-state imaging device1according to the second embodiment described above can be obtained.

Furthermore, in the solid-state imaging device1according to Modification Example 1 of the second embodiment, since the second region28is uniformly provided in a planar shape, the manufacturing process becomes easy. As a result, mass productivity of the solid-state imaging device1can be enhanced.

Furthermore, since the photodiode29performs photoelectric conversion using the first region27including germanium formed at a position closer to the light incident surface side than the second region28, a sufficient photoelectric conversion amount can be obtained even when the second region28including silicon is included.

Note that the solid-state imaging device1according to Modification Example 1 of the second embodiment of the present technology has a configuration in which the first semiconductor substrate20and the second semiconductor substrate40are bonded to each other, but as shown inFIG.16, only the first semiconductor substrate20may be included as a substrate.

Modification Example 2 of Second Embodiment

Modification Example 2 of the second embodiment of the present technology shown inFIGS.17A and17Bwill be described below. The solid-state imaging device1according to Modification Example 2 of the present second embodiment is different from the solid-state imaging device1according to the second embodiment described above in that the second region28is provided with a different film thickness with steps, and the other configurations of the solid-state imaging device1are basically similar to those of the solid-state imaging device1according to the second embodiment described above. Note that the components already described will be denoted by the same reference numerals, and the description thereof will be omitted.

<Configuration of First Semiconductor Substrate>

(Configuration of First Semiconductor Layer)

As shown inFIG.17A, the second region28is provided in the first semiconductor layer21at a position closer to the second surface S2in the thickness direction of the first semiconductor layer21. As shown inFIG.17B, the second region28includes a first part281facing the first range S21that is a part of the second surface S2, and a second part282facing a second range S22that is a part of the second surface S2different from the first range S21. The first range S21is a region surrounded by the contour line21bindicated by an alternate long and short dash line. Here, the second range S22is the entire partial surface of the second surface S2other than the first range S21.

As shown inFIG.17A, the thickness g, which is the thickness (film thickness) of the first part281in the Z direction, is larger than the thickness i, which is the thickness (film thickness) of the second part282in the Z direction (i<g). As described above, the second region28has a configuration in which there is a step between the first part281provided with the FD441and the other second part282. The FD441is provided at the first part281having a large thickness. The thickness h, which is the thickness of the FD441in the Z direction, is equal to or less than the thickness g of the first part281and is larger than the thickness i of the second part282(i<h≤g).

Only the first region27is provided as a region at a part of the first semiconductor layer21closer to the light incident surface than the second region28in the thickness direction. The photodiode29is provided in the first region27. As shown inFIG.17A, the first region27includes a first part271provided at a part closer to the light incident surface than the first part281in the thickness direction, and a second part272provided at a part closer to the light incident surface than the second part282. The thickness k, which is the thickness (film thickness) of the second part272in the Z direction, is larger than the thickness j, which is the thickness (film thickness) of the first part271in the Z direction (j<k). The photodiode29is provided at the second part272having a large thickness.

Even in the solid-state imaging device1according to Modification Example 2 of the second embodiment, the same effects as those of the solid-state imaging device1according to the second embodiment described above can be obtained.

Furthermore, in the solid-state imaging device1according to Modification Example 2 of the second embodiment, in the second region28, the second part282which is a region other than the first part281provided with the FD441is provided to be thinner than the first part281and the FD441. As a result, the thickness k of the second part272of the first region27can be made larger than the thickness j of the first part271, and the photodiode29can be configured only with the first region27. As a result, since the photodiode29is formed not to include a bonding part between different materials such as silicon (second semiconductor material) and germanium (first semiconductor material), the performance of the solid-state imaging device1is improved.

Note that the second range S22is the entire partial surface of the second surface S2other than the first range S21, but as shown inFIG.18, the second range S22may be a part of the second surface S2other than the first range S21. The second range S22is only required to be a part of the second surface S2different from the first range S21.

In addition, the photodiode29includes only the first region27, but may include both the first region27including germanium and the second part282of the second region28including silicon. In this case, although the photodiode29contains silicon, the amount of silicon contained in the photodiode29is smaller than that in the case of Modification Example 1 of the second embodiment described above. Therefore, the amount of germanium used for photoelectric conversion increases in the photodiode29, and the performance of the photodiode29is improved.

Note that the solid-state imaging device1according to Modification Example 2 of the second embodiment of the present technology has a configuration in which the first semiconductor substrate20and the second semiconductor substrate40are bonded to each other, but as shown inFIG.19, only the first semiconductor substrate20may be included as a substrate.

Modification Example 3 of Second Embodiment

Modification Example 3 of the second embodiment of the present technology shown inFIG.20will be described below. The solid-state imaging device1according to Modification Example 3 of the present second embodiment is different from the solid-state imaging device1according to the second embodiment described above in that the bias voltage VB is applied to the first semiconductor layer21from the first surface S1side in order to assist in pushing out the signal charge generated in the photodiode29from the first semiconductor substrate20side toward the second semiconductor substrate40side, and other configurations of the solid-state imaging device1are basically similar to those of the solid-state imaging device1according to the second embodiment described above. Note that the components already described will be denoted by the same reference numerals, and the description thereof will be omitted.

The bias voltage VB is applied to the first contact region24, which is a first conductive type diffusion region, provided in the first semiconductor layer21. The first contact region24is provided in the first semiconductor layer21at a position closer to the first surface S1, and more specifically, a part thereof faces the first surface S1. In addition, the bias voltage VB is applied to the first contact region24via a via26a, a wiring26b, a through-silicon via (TSV)26cpenetrating the first semiconductor layer21, a wiring (not shown), and the like, which are included in the first semiconductor substrate20.

Even in the solid-state imaging device1according to Modification Example 3 of the second embodiment, the same effects as those of the solid-state imaging device1according to the second embodiment described above can be obtained.

Note that the solid-state imaging device1according to Modification Example 3 of the second embodiment of the present technology has a configuration in which the first semiconductor substrate20and the second semiconductor substrate40are bonded to each other, but as shown inFIG.21, only the first semiconductor substrate20may be included as a substrate.

Modification Example 4 of Second Embodiment

Modification Example 4 of the second embodiment of the present technology shown inFIG.22will be described below. The solid-state imaging device1according to Modification Example 4 of the present second embodiment is different from the solid-state imaging device1according to the second embodiment described above in that the bias voltage VB is applied to the first semiconductor layer21from the second surface S2side in order to assist in pushing out the signal charge generated in the photodiode29from the first semiconductor substrate20side toward the second semiconductor substrate40side, and other configurations of the solid-state imaging device1are basically similar to those of the solid-state imaging device1according to the second embodiment described above. Note that the components already described will be denoted by the same reference numerals, and the description thereof will be omitted.

The first contact region24is provided in the first semiconductor layer21at a position closer to the second surface S2, and more specifically, a part thereof faces the second surface S2. In addition, the bias voltage VB is applied to the first contact region24via the via26d, the wiring26e, and the like of the first semiconductor substrate20.

Even in the solid-state imaging device1according to Modification Example 4 of the second embodiment, the same effects as those of the solid-state imaging device1according to the second embodiment described above can be obtained.

Note that the solid-state imaging device1according to Modification Example 4 of the second embodiment of the present technology has a configuration in which the first semiconductor substrate20and the second semiconductor substrate40are bonded to each other, but as shown inFIG.23, only the first semiconductor substrate20may be included as a substrate.

Modification Example 5 of Second Embodiment

Modification Example 5 of the second embodiment of the present technology shown inFIGS.24A to24Cwill be described below. The solid-state imaging device1according to Modification Example 5 of the present second embodiment is obtained by applying the technology according to the second embodiment described above to the solid-state imaging device1which is an indirect time of flight (iToF) sensor, and the other configurations of the solid-state imaging device1are basically similar to those of the solid-state imaging device1according to the second embodiment described above. Note that the components already described will be denoted by the same reference numerals, and the description thereof will be omitted.

Each of the regions21aof the first semiconductor layer21includes the first region27, a second region28L, and a second region28R. In addition, each of the regions21aof the first semiconductor layer21includes one photodiode29. The photodiode29is provided in the first region27. More specifically, the photodiode29is provided at a third part273positioned between the second region28L and the second region28R in the first region27.

The solid-state imaging device1includes two readout circuits15L and15R for one photodiode29. Each of the readout circuits15L and15R reads out the signal charge accumulated in the photodiode29and outputs a signal (pixel signal) based on the signal charge. Each of the readout circuits15L and15R includes the transfer transistor43, the FD441, the FD442, the reset transistor45, the selection transistor46, and the amplification transistor47. The readout circuits15L and15R are provided between the photodiode29and the vertical signal line11inFIG.2.

As shown inFIG.24A, the second region28L is provided at a position on the readout circuit15L side in the region21a, and the second region28R is provided at a position on the readout circuit15R side in the region21a. That is, the second region28L corresponds to the readout circuit15L, and the second region28R corresponds to the readout circuit15R. The FD441of the readout circuit15L is provided in the second region28L, and the FD441of the readout circuit15R is provided in the second region28R. Then, the transfer transistor43of the readout circuit15L transfers the signal charge accumulated in the photodiode29to the FD441of the readout circuit15L. Similarly, the transfer transistor43of the readout circuit15R transfers the signal charge accumulated in the photodiode29to the FD441of the readout circuit15R. As described above, the solid-state imaging device1includes, for each photodiode29, two sets each including the FD441, the transfer transistor43that transfers the signal charge accumulated in the photodiode29to the FD441, and the second region28.

The light source device211shown inFIG.29shines or disappears at a constant cycle when irradiating the subject with light. Then, the solid-state imaging device1alternately turns on and off the transfer transistor43of the readout circuit15L and the transfer transistor43of the readout circuit15R at the same cycle as the light source device211. As a result, the solid-state imaging device1distributes and transfers the signal charge obtained by photoelectric conversion by the photodiode29to the FD441of the readout circuit15L and the FD441of the readout circuit15R. The distance to the subject is obtained by the ratio of the distributed signal charge.

Even in the solid-state imaging device1according to Modification Example 5 of the second embodiment, the same effects as those of the solid-state imaging device1according to the second embodiment described above can be obtained.

Furthermore, even in a case where two readout circuits15L and15R are provided for one photodiode29, the second regions28are provided for each of the two readout circuits. Therefore, each FD441of the two readout circuits can also be formed in the second region28.

Note that the number of readout circuits provided for one photodiode29is not limited to two, and may be three or more. Similarly, the solid-state imaging device1includes, for each photodiode29, a plurality of sets each including the FD441, the transfer transistor43that transfers the signal charge accumulated in the photodiode29to the FD441, and the second region28.

Note that the solid-state imaging device1according to Modification Example 5 of the second embodiment of the present technology has a configuration in which the first semiconductor substrate20and the second semiconductor substrate40are bonded to each other, but as shown inFIGS.25A and25B, only the first semiconductor substrate20may be included as a substrate.

Modification Example 6 of Second Embodiment

Modification Example 6 of the second embodiment of the present technology shown inFIGS.26A to26Cwill be described below. The solid-state imaging device1according to Modification Example 6 of the present second embodiment is different from the solid-state imaging device1according to the second embodiment described above in that a pixel sharing structure in which one FD441is shared by the plurality of photodiodes29is provided, and the other configurations of the solid-state imaging device1are basically similar to those of the solid-state imaging device1according to the second embodiment described above. Note that the components already described will be denoted by the same reference numerals, and the description thereof will be omitted.

FIGS.26A to26Cshow an example in which four photodiodes29share one FD441. Each of the regions21aincludes one photodiode29and one transfer transistor43. The pixel sharing structure is configured with the plurality of photodiodes29, the plurality of transfer transistors43, the plurality of discharge transistors49, one shared FD441, and other pixel transistors shared one by one (the reset transistor45, the selection transistor46, and the amplification transistor47). That is, in the shared pixels, the photodiode29and the transfer transistor43that configure a plurality of unit pixels share one FD44and other pixel transistors shared one by one. That is, the FD44is provided to be able to hold signal charge from the plurality of photodiodes29, for each of the photodiodes29.

The FD441to be shared is provided in the second region28. Each of the photodiodes29is provided in the first region27.

Even in the solid-state imaging device1according to Modification Example 6 of the second embodiment, the same effects as those of the solid-state imaging device1according to the second embodiment described above can be obtained.

Note that the solid-state imaging device1according to Modification Example 6 of the second embodiment of the present technology has a configuration in which the first semiconductor substrate20and the second semiconductor substrate40are bonded to each other, but as shown inFIGS.27A and27B, only the first semiconductor substrate20may be included as a substrate.

Third Embodiment

The third embodiment of the present technology shown inFIG.28will be described below. The solid-state imaging device1according to the present third embodiment is obtained by combining the technology according to the second embodiment described above with the solid-state imaging device1according to the first embodiment described above, and the other configurations of the solid-state imaging device1are basically similar to those of the solid-state imaging device1according to the second embodiment described above. Note that the components already described will be denoted by the same reference numerals, and the description thereof will be omitted.

In the first embodiment described above, a semiconductor substrate including the same material, for example, single crystal silicon is used for the first semiconductor layer21and the second semiconductor layer41. In the present third embodiment, the first semiconductor layer21includes a first region27including a first semiconductor material, and the second semiconductor layer41includes a second region28including a second semiconductor material. For example, the first semiconductor layer21includes a first semiconductor material (for example, germanium), and the second semiconductor layer41includes a second semiconductor material (for example, silicon) of which quantum efficiency is lower than that of the first semiconductor material. The FD44is provided in the second region28. The solid-state imaging device1according to the present third embodiment has the same configuration as the solid-state imaging device1according to the first embodiment except for the above.

Even in the solid-state imaging device1according to the third embodiment, the same effects as those of the solid-state imaging device1according to the first embodiment described above can be obtained.

Furthermore, germanium is more sensitive to the light L such as IR light than silicon. Since there is such a difference in sensitivity, the light L is absorbed when passing through germanium first, and further, the light shielding layer60is present, it is possible to suppress a case where the light L reaches the FD44, and even when the light L can reach the FD44, photoelectric conversion in silicon can be suppressed due to the difference in sensitivity.

Fourth Embodiment

In the present fourth embodiment, a configuration example of electronic equipment will be described. As shown inFIG.29, the distance image equipment201as electronic equipment includes an optical system202, a semiconductor chip (sensor chip)2X, an image processing circuit203, a monitor204, and a memory205. The distance image equipment201may acquire a distance image according to the distance to the subject by receiving light (modulated light or pulsed light) projected from the light source device211toward the subject and reflected on a surface of the subject.

The optical system202includes one or a plurality of optical lenses, and guides image light from the subject (incident light) to the semiconductor chip2X to form an image on a light receiving surface (sensor unit) of the semiconductor chip2X.

As the semiconductor chip2X, the semiconductor chip2on which the solid-state imaging device1of the first embodiment described above is mounted is applied, and a distance signal indicating a distance obtained from a light reception signal (APD OUT) output from the semiconductor chip2X is supplied to the image processing circuit203.

The image processing circuit203performs image processing of constructing the distance image on the basis of the distance signal supplied from the semiconductor chip2X, and the distance image (image data) obtained by the image processing is supplied to and displayed on the monitor204, or supplied to and stored (recorded) in the memory205.

In the distance image equipment201configured as described above, by applying the semiconductor chip2described above, it is possible to calculate the distance to the subject on the basis of only the light reception signal from the pixel3having high stability and to generate a highly accurate distance image. That is, the distance image equipment201can acquire a more accurate distance image.

Note that, although the semiconductor chip2on which the solid-state imaging device1according to the first embodiment of the present technology is mounted is applied as the semiconductor chip2X, the semiconductor chip2on which the solid-state imaging device1according to any one of Modification Examples 1 to 3 of the first embodiment, the second embodiment and Modification Examples 1 to 6 thereof, and the third embodiment, or a combination thereof is mounted may be applied.

<Usage Example of Image Sensor>

The semiconductor chip2(image sensor) described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-ray as described below, for example.A device which takes an image to be used for viewing such as a digital camera and portable equipment with a camera functionA device for traffic purpose such as an in-vehicle sensor which takes images of the front, rear, surroundings, interior and the like of an automobile, a surveillance camera for monitoring traveling vehicles and roads, and a ranging sensor which measures a distance between vehicles and the like for safe driving such as automatic stop, recognition of a driver's condition and the like.A device for home appliance such as a television, a refrigerator, and an air conditioner that images a user's gesture and performs equipment operation according to the gestureA device for medical and health care use such as an endoscope and a device that performs angiography by receiving infrared lightA device for security use such as a security monitoring camera and an individual authentication cameraA device for beauty care such as a skin measuring instrument that images skin and a microscope that images scalpA device for sports use such as an action camera and a wearable camera for sports use and the likeA device used for agriculture, such as a camera for monitoring a condition of a field or crop.

Other Embodiments

As described above, the present technology is described according to the first to fourth embodiments and modification examples thereof, but it should not be understood that the description and drawings forming a part of this disclosure limit the present technology. Various alternative embodiments, examples, and operation techniques will be apparent to those skilled in the art from this disclosure.

For example, in the second embodiment and the modification examples thereof, the discharge transistor49may not be provided. In addition, the configuration of applying the bias voltage VB described in Modification Example 3 and Modification Example 4 of the second embodiment may be applied to the Modification Examples 1, 2, 5, and 6 which are other modification examples of the second embodiment, or may be a configuration that does not apply the bias voltage VB in the second embodiment and the modification examples thereof.

In addition, the technical ideas described in the first to fourth embodiments and the modification examples thereof can be combined with each other. For example, in the solid-state imaging device1according to the third embodiment described above, the technical idea of using different semiconductor materials described in the second embodiment described above is combined with the solid-state imaging device1according to the first embodiment, but the same idea may be combined with the solid-state imaging devices1according to Modification Examples 1 to 3 of the first embodiment. Furthermore, for example, the technical idea of shielding the FD44on the second semiconductor substrate40side with the light shielding layer60described in the first embodiment described above may be combined with the solid-state imaging device1according to the second embodiment and Modification Examples 1 to 6 thereof. In addition, for example, the structure of the iToF sensor according to Modification Example 5 of the second embodiment or the structure sharing the FD441according to Modification Example 6 of the second embodiment can be applied to Modification Examples 1 to 4 of the second embodiment, and various combinations according to the respective technical ideas are possible.

As described above, it is needless to say that the present technology includes various embodiments and the like that are not described herein. Therefore, the technical scope of the present technology is defined only by the matters specifying the invention described in the claims appropriate from the above description.

Furthermore, the effects described in the present specification are merely examples and are not limited, and other effects may be provided.

It is to be noted that the present technology may also have the following configurations.

A solid-state imaging device including:a first semiconductor substrate including a first semiconductor layer provided with a plurality of photoelectric conversion units that performs photoelectric conversion, and a first wiring layer provided on a surface side opposite to a light incident surface of the first semiconductor layer;a second semiconductor substrate including a second semiconductor layer provided with a charge holding unit that holds signal charge generated in the photoelectric conversion unit and a second wiring layer provided on one surface side of the second semiconductor layer, and overlapped with and bonded to the first semiconductor substrate such that the second wiring layer is positioned between the first wiring layer and the second semiconductor layer; anda light shielding layer provided in at least one of the first wiring layer or the second wiring layer at a position facing the charge holding unit in a thickness direction.

The solid-state imaging device according to (1), in whichthe light shielding layer overlaps at least a part of the charge holding unit in plan view.

The solid-state imaging device according to (2), in whichthe light shielding layer overlaps the entire charge holding unit in plan view.

The solid-state imaging device according to any one of (1) to (3), in whichthe light shielding layer includes a metal film closest to the second semiconductor layer in a thickness direction of the second wiring layer among a plurality of layers of metal films provided in the second wiring layer.

The solid-state imaging device according to any one of (1) to (3), in whichthe light shielding layer is the metal layer closest to the second semiconductor layer among a plurality of metal layers provided in the second wiring layer at positions facing the charge holding unit in the thickness direction.

The solid-state imaging device according to any one of (1) to (3), in whichthe light shielding layer is at least one connection pad out of a first connection pad provided in the first wiring layer and a second connection pad provided in the second wiring layer and bonded to the first connection pad.

The solid-state imaging device according to any one of (1) to (3), in whicha plurality of the light shielding layers is provided.

The solid-state imaging device according to (7), in whichthe light shielding layer includes the metal layer closest to the second semiconductor layer in the thickness direction of the second wiring layer among the plurality of metal layers provided in the second wiring layer at positions facing the charge holding unit in the thickness direction, and at least one connection pad out of a first connection pad provided in the first wiring layer and a second connection pad provided in the second wiring layer and bonded to the first connection pad.

The solid-state imaging device according to any one of (1) to (8), in whichthe second semiconductor layer includes a transfer transistor that transfers signal charge obtained by photoelectric conversion to the charge holding unit.

The solid-state imaging device according to any one of (1) to (9), in whichthe first semiconductor layer includes a first semiconductor material, and the second semiconductor layer includes a second semiconductor material having a quantum efficiency, which indicates a probability that photons are converted into electrons, lower than that of the first semiconductor material.

Electronic equipment including:a solid-state imaging device; andan optical system that forms an image of image light from a subject on the solid-state imaging device, in whichthe solid-state imaging device includesa first semiconductor substrate including a first semiconductor layer provided with a plurality of photoelectric conversion units that performs photoelectric conversion, and a first wiring layer provided on a surface side opposite to a light incident surface of the first semiconductor layer,a second semiconductor substrate including a second semiconductor layer provided with a charge holding unit that holds signal charge generated in the photoelectric conversion unit and a second wiring layer provided on one surface of the second semiconductor layer, and overlapped with and bonded to the first semiconductor substrate such that the second wiring layer is positioned between the first wiring layer and the second semiconductor layer, anda light shielding layer provided in at least one of the first wiring layer or the second wiring layer at a position facing the charge holding unit in a thickness direction.

A solid-state imaging device including:a first semiconductor layer including a first region including a first semiconductor material and a second region including a second semiconductor material of which a quantum efficiency indicating a probability that photons are converted into electrons is lower than that of the first semiconductor material, and including a photoelectric conversion unit that performs photoelectric conversion and a charge holding unit that holds signal charge generated by the photoelectric conversion unit, in whichthe photoelectric conversion unit is provided in a region including at least the first region out of the first region and the second region, andthe charge holding unit is provided in the second region.

The solid-state imaging device according to (12), in whichthe second region faces a second surface that is a surface on a side opposite to a light incident surface among surfaces of the first semiconductor layer.

The solid-state imaging device according to (13), in whichthe second region faces the second surface only in a first range that is a part of the second surface.

The solid-state imaging device according to (13), in whichthe second region faces an entire surface of the second surface.

The solid-state imaging device according to (13), in whichthe second region includes a first part facing a first range that is a part of the second surface, and a second part facing a second range that is a part of the second surface different from the first range,a dimension of the first part in a thickness direction of the first semiconductor layer is larger than a dimension of the second part in the thickness direction of the first semiconductor layer, andthe charge holding unit is provided at the first part.

The solid-state imaging device according to any one of (12) and (13), in whicheach one of the photoelectric conversion units includes a plurality of sets including the charge holding unit, a transfer transistor that transfers the signal charge accumulated in the photoelectric conversion unit to the charge holding unit, and the second region.

The solid-state imaging device according to any one of (12) to (16), in whichone of the charge holding units is provided to be able to hold the signal charge from a plurality of the photoelectric conversion units, for each of the photoelectric conversion units.

The solid-state imaging device according to any one of (12) to (18), in whichthe first semiconductor material is germanium, silicon germanium, gallium arsenide, indium gallium arsenide, or copper indium gallium selenium, andthe second semiconductor material is silicon.

Electronic equipment including:a solid-state imaging device; andan optical system that forms an image of image light from a subject on the solid-state imaging device, in whichthe solid-state imaging device includesa first semiconductor layer including a first region including a first semiconductor material and a second region including a second semiconductor material of which a quantum efficiency indicating a probability that photons are converted into electrons is lower than that of the first semiconductor material, and including a photoelectric conversion unit that performs photoelectric conversion and a charge holding unit that holds signal charge generated by the photoelectric conversion unit,the photoelectric conversion unit is provided in a region including at least the first region out of the first region and the second region, andthe charge holding unit is provided in the second region.

The scope of the present technology is not limited to the illustrated and described embodiments, and includes all embodiments that provide effects equivalent to the effects intended to be provided by the present technology. Furthermore, the scope of the present technology is not limited to the combinations of the features of the invention defined by the claims, and may be defined by any desired combination of specific features among all the disclosed features.

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