Amplifier arrangement and method for amplifying a signal

A power amplifier comprises a control signal generator providing a first and a second signal, a first amplifier comprising a first transistor and a first cascode transistor for the amplification of the first signal, a second amplifier comprising a second transistor and a second cascode transistor for the amplification of the second signal, and an output coupler which couples an output of the first amplifier and an output of the second amplifier to an output terminal of the amplifier arrangement.

FIELD OF THE INVENTION

The invention relates to the field of electronics and primarily to an amplifier arrangement comprising a first branch and a second branch, and to a method for amplifying a signal.

BACKGROUND OF THE INVENTION

Amplifier arrangements are used in a number of areas of electronics such as, for example, communications technology and industrial electronics. An amplifier arrangement may be provided as an individual, integrated circuit. An amplifier arrangement may also be realized together with further circuit modules on an extensive integrated circuit.

A power amplifier is used, for example, in mobile communication devices. As mobile communication devices use more and more digital circuitry, there is a need for a power amplifier which can be controlled by digital signals.

SUMMARY OF THE INVENTION

The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present one or more concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.

According to one embodiment of the invention, an amplifier arrangement is disclosed, and comprises multiple branches. In one example each branch is coupled to a common current combiner. In accordance with a desired power, none, one or both branches are active and participate in forming the output signal.

To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which one or more aspects of the present invention may be employed. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the annexed drawings.

DETAILED DESCRIPTION OF THE INVENTION

Components having the same function and/or effect have the same reference symbols. Where the components and functions of the circuit parts match, their description will not be repeated for each of the following figures.

FIG. 1Ashows an exemplary embodiment of an amplifier arrangement comprising a control logic2, a first, a second, a third, a fourth, a fifth and a sixth branch30,50,70,90,110and a current combiner3. The control logic2comprises six output terminals200to205and two input terminals206,207. A first branch10comprises a first transistor11, a first inverter13and a further inverter14. The output terminal200of the control logic2is coupled to an input terminal of the further inverter14. An output terminal of the further inverter14is coupled by the first inverter13to a control terminal of the first transistor11. The first terminal of the first transistor11is connected to a reference potential terminal8. A second terminal of the first transistor11is coupled to the current combiner3. The second branch30of the amplifier arrangement comprises a second transistor31, a second inverter33and a further inverter34. The output terminal201of the control logic2is coupled to an input terminal of the further inverter34. An output terminal of the further inverter34is coupled by the second inverter33to a control terminal of the second transistor31. A first terminal of the second transistor31is connected to the reference potential terminal8and a second terminal of the second transistor31is coupled to the current combiner3. The control terminal of the first transistor11is coupled to the control terminal of the second transistor31via the first impedance15. The first impedance15in this embodiment comprises a coil. An input terminal of the first inverter13is coupled to an input terminal of the second inverter33via a second impedance16. The second impedance16also comprises a coil in this example.

The third branch50of the amplifier arrangement comprises a third transistor51and a third inverter53, a further inverter54. The output terminal202of the control logic2is coupled to a control terminal of the third transistor51by a series circuit comprising the third inverter53and the further inverter54. A first terminal of the third transistor51is connected to the reference potential terminal8and a second terminal of the third transistor51is coupled to the current combiner3. A fourth branch70of the amplifier arrangement comprises a fourth transistor71, a fourth inverter73and a further inverter74. The output terminal203of the control logic2is coupled to an input terminal of the fourth transistor71by a series circuit comprising the fourth inverter73and the further inverter74. A first terminal of the fourth transistor71is coupled to the current combiner3and a second terminal of the fourth transistor71is coupled to the current combiner3.

A fifth branch90of the amplifier arrangement comprises a fifth transistor91, a fifth inverter93and a further inverter94. The output terminal204of the control logic2is coupled to a control terminal of the fifth transistor91via a series circuit comprising the fifth inverter93and the further inverter94. A first terminal of the fifth transistor91is connected to the reference potential terminal8and a second terminal of the fifth transistor91is coupled to the current combiner3. A sixth branch110of the amplifier arrangement comprises a sixth transistor111, a sixth inverter113and a further inverter114. The output terminal205of the control logic2is coupled to a control terminal of the sixth transistor111via a series circuit comprising the sixth inverter113and the further inverter114. A first terminal of the sixth transistor111is connected to the reference potential terminal8and a second terminal of the sixth transistor111is coupled to the current combiner3.

The current combiner3comprises a circuitry4for impedance transformation and a Balun (BALanced-Unbalanced)5. The second terminals of the six transistors11,31,51,71,91,111are connected to input terminals of the circuitry4for impedance transformation. The circuitry4for impedance transformation comprises two output terminals, which are connected to two input terminals of the balun5. An output terminal of the balun5is coupled to an antenna6. The balun5is also connected to the reference potential terminal8.

The control logic2receives a data signal IN at the first input terminal206of the control logic2and a power control signal SP at the second input terminal207of the control logic2. By the use of the data signal IN and of the power control signal SP, the control logic2generates six signals S1to S6which are provided at the corresponding output terminals200to205. The first signal S1and the second signal S2have a phase difference of approximately 180 degrees with respect to each other. The first signal S1is amplified by the further inverter14and the inverter13so that an amplified first signal S1controls the control terminal of the first transistor11. In an analogous way, the second signal S2is amplified by the second inverter33and the further inverter34and controls the control terminal of the second transistor31. The current flowing through the first transistor11is controlled by the signal at the control terminal of the first transistor11and also a current flowing through the second transistor31is controlled by the signal at the control terminal of the second transistor31. The first transistor11and the second transistor31have the same capability for driving a current. The first and the second transistor11,31in this embodiment comprise a width WB.

The four signals S3to S6are amplified by the inverters comprised by the third, the fourth, the fifth, and the sixth branches50,70,90,110, respectively, and control the control terminals of the third, the fourth, the fifth, and the sixth transistors51,71,91,111, respectively, and, therefore, control a current which flows from the current combiner3through the four transistors51,71,91,111to the reference potential terminal8. The third signal S3has a phase difference of approximately 180 degrees with respect to the fourth signal S4. In an analogous manner, the fifth signal S5has a phase difference of approximately 180 degrees with respect to the sixth signal S6.

The six signals S1to S6are generated in dependency of or as a function of the power control signal SP. To achieve a maximum power at the output terminal of the current combiner3, the six signals S1to S6are generated using the data signal IN. To achieve the maximum power, the first, the third, and the fifth signal S1, S3, S5are equal and the second, the fourth, and the sixth signal S2, S4, S6are also equal. To achieve a smaller output power at the output terminal of the current combiner3, the fifth and the sixth transistor91,111are switched off, for example, by an appropriate constant value of the fifth and the sixth signal S5, S6. The six transistors are implemented in this embodiment using metal-oxide-semiconductor field-effect transistors, (MOSFETs). The six MOSFETs are designed in this exemplary embodiment as n-channel MOSFETs with a positive threshold value. Therefore, a fifth and a sixth signal S5, S6with a value of 0 switches the fifth and the sixth transistor91,111off.

The circuitry4of the current combiner3generates a signal SRF1at a first output terminal and a second signal SRF2at a second output terminal using the current flowing through the six transistors11,31,51,71,91,111. The balun5generates a radio frequency signal SRF by the use of the first and the second signal SRF1, SRF2. The radio frequency signal SRF is provided to the antenna6.

According to an embodiment, the first and the second branch10,30can be implemented as a so-called base amplifier which contributes with a gate width WB to the radio frequency signal SRF. The third and the fourth branches50,70contribute with a gate width W0and the fifth and the sixth branches90,110contribute with a gate width W1to the radio frequency signal SRF. The contribution may be implemented, for example, in a binary digit configuration. The gate width W0can be the gate width of the least significant bit amplifier.

In an embodiment, the six branches can be switched on and off by the use of the control logic2in such a way that the necessary phase and amplitude of the radio frequency signal SRF can be achieved. The amplifier arrangement can also be used as a power digital-to-analog converter. The first and the second impedances15,16are used for compensation of parasitic capacitances of the input terminals of the inverters13,33and the transistors11,31.

In one embodiment, the 12 inverters13,14,33,34,53,54,73,74,93,94,113,94,114are scaled with reference to the widths of the six transistors. The capability to provide a current of the six inverters13,33,53,73,93,113corresponds to the widths WB, W0, W1of these six transistors11,31,51,71,91,111. The six inverters13,33,53,73,93,113have a higher capability to provide a current in comparison to the six further inverters14,34,54,74,94,114.

In an embodiment, the first, the third and the fifth signals S1, S3, S5have approximately the same phase. The second, the fourth and the sixth signals S1, S4, S6also have approximately the same phase which has a phase difference of 180 degrees with respect to the phase of the first, the third and the fifth signals S1, S3, S5.

In a further development, a first phase difference φ0 between the third signal S3and the first signal S1is represented by φ0. The fourth signal S4has the first phase difference φ0 with respect to the second signal S2. A second phase difference φ1 between the fifth signal S5and the first signal S1is represented by φ1. The sixth signal S6has the phase difference φ1 with respect to the second signal S2.

In an alternative embodiment, the third signal has a phase difference of 90 degrees with respect to the first signal S1and the fourth signal S4has a phase difference of approximately 270 degrees with respect to the first signal S1. The first, the second, the third, and the fourth transistor11,31,51,71show the same capability for driving a current. The four transistors11,31,51,71show the same width WB. By the use of four different phases, an alternative current combiner3can be obtained in a more cost-effective way in comparison with the current combiner3designed for combining signals comprising a phase difference of 180 degrees.

In an alternative embodiment, which is not shown, the first and the second impedances15,16are realized using generalized impedance converters or gyrators.

In an alternative embodiment, which is not shown, the input terminals of the third and the fourth transistor51,71and the input terminals of the fifth and the sixth transistor91,111are also coupled together by impedances which comprise coils. In an alternative embodiment, the input terminals of the third and the fourth inverter53,73and the input terminals of the fifth and the sixth inverter93,113are also connected together using impedances which comprise coils.

In another alternative embodiment, which is not shown, the amplifier arrangement comprises further branches which are realized similarly in comparison to the first and the second branch10,30. The further branches are connected in parallel to the six branches10,30,50,70,90,110.

In an alternative embodiment, the six transistors11,31,51,71,91,111are implemented as p-channel MOSFETs.

In an alternative embodiment, the coil which is comprised by the first impedance15is a switchable coil and the coil comprised by the second impedance16is also a switchable coil. MOSFETs can be coupled to the coils to switch on and off turns or winding sections of the coils.

FIG. 1Bshows another exemplary embodiment of an amplifier arrangement comprising the control logic2, the first, the second, the third, the fourth, the fifth and the sixth branch10,30,50,70,90,110and a current combiner3. The first branch10comprises the first transistor11, the first inverter13and the further inverter14. The first branch10couples the output terminal200of the control logic2to an input terminal of the current combiner3. The second, the third, the fourth, the fifth and the sixth branches30,50,70,90,110are implemented in analog manner to the first branch10. According to the exemplary embodiment shown inFIG. 1B, the different branches10,30,50,70,90,110are not coupled together either directly or via impedances. A coupling is only provided by the control logic2and the current combiner3.

The first transistor11has a width WB of the gate and of the channel, respectively. The second transistor31has the same width WB. The third and the fourth transistors51,71have a further width W0. The fifth and the sixth transistors91,111have an additional further width W1.

The control logic2provides, at the six output terminals200to205of the control logic2, six signals S1, S2, S3, S4, S5, S6which are fed to the six branches10,30,50,70,90,110, respectively. The second signal S2equals to the first signal S1besides a phase difference of approximately 180 degrees with respect to each other. The third signal S3and the first signal S1have the first phase difference φ0 with respect to each other. The fourth signal S4and the first signal S1have a phase difference of approximately 180 degrees plus the first phase difference φ0 with respect to each other. The fifth signal S5and the first signal S1have the second phase difference φ1 with respect to each other. The sixth signal S6and the first signal S1have a phase difference of approximately 180 degrees plus the second phase difference φ1 with respect to each other.

In an embodiment, the first, the third and the fifth signal S1, S3, S5have approximately the same phase. The second, the fourth, and the sixth signal S2, S4, S6have approximately the same further phase. The power of the radio frequency signal SRF depends on the branches which are switched to active by the signals S1to S6.

In one embodiment, the current combiner3comprises the circuitry4for impedance transmission and the balun5which are shown inFIG. 1A.

In an embodiment, the six further inverters14,34,54,74,94,114and the six inverters13,33,53,73,93,113do not comprise transistors of the same size. The capability for driving a current of the six inverters13,33,53,73,93,113is higher than the capability for driving a current of the six further inverters14,34,54,74,94,114. The widths of the transistors of the 12 inverters depend on the widths of the first to the sixth transistor11,31,51,71,91,111so that the 12 inverters are scaled according to the widths of the six transistors11,31,51,71,91,111.

FIG. 1Cshows another exemplary embodiment of an amplifier arrangement which is a further development of the amplifier arrangement shown inFIG. 1A. According toFIG. 1Cnot only the first transistor11and the second transistor31are coupled together by the first impedance15but also the third and the fourth transistor51,71are coupled together by a further impedance65. The fifth and the sixth transistor91,111are coupled together by an additional impedance105. Also not only the first and the second inverter13,33are coupled together by the second impedance16but also the third and the fourth inverter53,73as well as the fifth and the sixth inverter93,113are coupled together, respectively, by similar impedances56,96. The control terminal of the third transistor51is coupled to the control terminal of the fourth transistor71via a series circuit of two coils57,77. A node between the two coils57,77is coupled to the reference potential terminal8via a parallel circuit of a capacitor55and a resistor56. In an analog way the control terminals of the fifth and the sixth transistors91,111are coupled together via the further impedance105which comprises two coils97,117. A node between the two coils97,117is coupled to the reference potential terminal8by a parallel circuit of a capacitor95and a resistor96.

The input terminal of the third inverter53is coupled to the input terminal of the fourth inverter73via the impedance56, comprising two coils58,78. A node between the two coils58,78is coupled to the supply voltage terminal9via a parallel circuit of a capacitor59and a resistor60. An input terminal of the fifth inverter93is coupled to an input terminal of the sixth inverter113via the impedance96, comprising two coils98,118. A node between the two coils98,118is coupled to the supply voltage terminal9via a parallel circuit comprising a capacitor99and a resistor100.

The six signals S1to S6which are provided by the logic circuit2are generated in the way the six signals S1to S6are generated according toFIG. 1B.

In one embodiment, the six inverters13,33,53,73,93,113have a higher capability for driving a circuit in comparison to the six inverters14,34,54,74,94,114. The inverters of each branch are scaled in accordance with the width of the transistor to which they are coupled to in the respective branch.

FIG. 2shows another exemplary embodiment of an amplifier arrangement. The amplifier arrangement comprises four branches10,30,50,70. In comparison to the first branch10according toFIGS. 1A to 1C, the first branch10comprises a first cascode transistor12which couples the second terminal of the first transistor11to an input terminal305of the current combiner3. In an analogous way, a second, a third, and a fourth cascode transistor32,52,72couple the second terminals of the second, the third, and the fourth transistors31,51,71to a second, a third, and a fourth input terminal306,315,316of the current combiner3, respectively.

The first impedance15comprises, according toFIG. 2, two impedances17,37which are coupled in series between the control terminals of the first and the second transistor11,31. A node between the impedance17and the impedance37is coupled to the reference potential terminal8via a parallel circuit of a capacitance35and a resistor36. The impedances17,37are implemented in this embodiment using coils.

The second impedance16is similarly designed using a series circuit of two impedances18,38which are coupled between the input terminals of the first and the second inverter30,33. A node between the impedance18and the impedance38is coupled to a supply voltage terminal9via a parallel circuit of a capacitor19and a resistor20. The impedances18,38are realized in this embodiment using coils.

The input terminals of the four cascode transistors12,32,52,72are connected to the supply voltage terminal9, so that the four cascode transistors12,32,52,72show the maximum conductivity.

The control logic2comprises four AND gates210to213. The first input terminal206and the second input terminal207of the control logic2are coupled to the input terminals of the first AND gate210. An output terminal of the AND gate210is coupled to the output terminal200of the control logic2. The second input terminal207and a third input terminal208of the control logic2are connected to the input terminals of the second AND gate211which comprises an output terminal which is connected to the second output terminal201of the control logic2. The first input terminal206and a fourth input terminal209of the control logic2are connected to the input terminals of the third AND gate212which comprises an output terminal which is connected to the third output terminal202. The third input terminal208and the fourth input terminal209are connected to the input terminals of the fourth AND gate213. An output terminal of the fourth AND gate213is coupled to the fourth output terminal203of the control logic2.

The current combiner3comprises a transformer300with two output terminals and six input terminals. The transformer comprises five coils301,303,311,313,320. The first coil301couples a second terminal of the first cascode transistor12to the supply voltage terminal9. A second terminal of the second cascode transistor32is coupled to the supply voltage terminal9via the second coil303. A second terminal of the third cascode transistor52is coupled to the supply terminal9via the third coil and a second terminal of the fourth cascode transistor72is coupled to the supply terminal9via the fourth coil313. Five capacitors302,304,312,314,321are connected parallel to the five coils301,303,311,313,320, respectively.

A data signal IN is applied to the first input terminal206of the control logic2. An inverted data signal INN is supplied to the third input terminal208. A power-select signal PS0is provided to the second input terminal207and a second power-select signal PS1is applied to the fourth input terminal209of the control logic2. The first and the third signal S1, S3depend on the data signal IN, while the second and the fourth signal S2, S4depend on the inverted data signal INN. Therefore, there is a phase difference of 180 degrees between the first signal S1and the second signal S2and also between the third signals S3and the fourth signal S4.

The power of the radio frequency signal SRF at the output terminal322of the current combiner3depends on the first and the second power-select signal PS1, PS2. If both signals PS1, PS2are received with a value 1, a maximum power is achieved at the output terminal322of the current combiner3. If both signals PS1, PS2equal 0, there is no output at the output terminal322. If one of the two power-select signals PS0, PS2equal 0 and the other of the two signals PS0, PS1equal 1, an intermediate value for the output power of the frequency signal SRF at the output terminal222can be achieved.

The first, the second, the third, and the fourth transistor11,31,51,71are isolated from the output terminal322via the cascode transistors12,32,52,72, respectively, and the transformer300.

The balun5is implemented, according toFIG. 2, using the transformer300. It is an advantage of a balun5that the differential signals provided at the four input terminals305,306,315,316of the current combiner3are converted to an arrangement with a single-ended output322while the other output terminal323is connected to a reference-potential terminal800.

In one embodiment, the reference-potential terminal8is connected to the further reference-potential terminal800. In an alternative embodiment, the two reference-potential terminals8,800are not connected together and are set independently of each other.

In an alternative embodiment, which is not shown, the input terminals of the cascode transistors12,32,52,72are not directly connected to the supply voltage terminal9. The control terminals of these four cascode transistors12,32,52,72are coupled to further output terminals of the control logic2. In this way, the power of the radio frequency signal SRF can be further controlled by setting the conductivity of the four cascode transistors12,32,52,72.

In an alternative embodiment, which is not shown, the transformer is replaced by a transformation network which may comprise capacitors and coils. The transformation network may comprise programmable components, switchable components or tunable components.

FIGS. 3A and 3Bshow exemplary tables comprising a width of transistors in an amplifier arrangement for two gain levels. The power P of the radio frequency signal SRF which is transferred to a load resistor RL is related to the current of the radio frequency signal SRF by the following equation:
P=RL ·I2,
wherein P is the power of the radio frequency signal SRF, RL is the value of the load resistor, and I is the current value of the radio frequency signal SRF. In the case where the first to the sixth transistors11,31,51,71,91,111are implemented as MOSFETs, the power P1generated by the use of the first transistor11is related to the power P2generated by the third transistor51according to the following equation:

P⁢⁢2P⁢⁢1=10k/10=(I⁢⁢2I⁢⁢1)2=(W⁢⁢2W⁢⁢1)2,
wherein I2is the current value generated by the third transistor51, I1is the current value generated by the first transistor11, W2is the width of the third transistor51, W1is the width of the first transistor11, and k is the power ratio in dB. The width of a MOSFET can also be understood as the gate width or the channel width. Therefore, the width ratio W2/W1is a function of the power ratio k in dB according to the following equation:

In an alternative embodiment, the first to the sixth transistors11,31,51,71,91,111are implemented as bipolar transistors, the power P1generated by the use of the first transistor11is related to the power P2generated by the third transistor51according to the following equation:

P⁢⁢2P⁢⁢1=10k/10=(I⁢⁢2I⁢⁢1)2=(A⁢⁢2A⁢⁢1)2,
wherein A2is the effective emitter area of the third transistor51and A1is the effective emitter area of the first transistor11. Therefore, the above and the following descriptions are also valid for bipolar transistors and can be used correspondingly by replacing the width W of a MOSFET by the effective emitter area A of a bipolar transistor.

In an embodiment, several branches of the amplifier arrangement are implemented which are to be switched on or off to control the power of the radio frequency signal SRF for each required gain setting.

In an embodiment, the several branches of the amplifier arrangement are implemented in a binary digit control configuration. By this binary digit control configuration, a simplified control scheme and chip layout can be achieved.

The number of different output power levels equals 2Nto control the power of the radio frequency signal SRF with binary digits of N bits in k dB steps. The optimum gate width WN which is required for each control step n can be derived from the above equation and equals:

In an embodiment, the different widths Wn of the different transistors are designed independent from each other and fulfill the above-mentioned equation.

In an alternative embodiment, the first to the sixth transistors11,31,51,71,91,111are implemented as multi-finger transistors. Therefore, the width of a transistor is a multiple of the width of one finger of the multi-finger transistor. In an exemplary method to determine several values of the width of the multi-finger transistors, the following equation is used:
W−F(w)=0,
wherein W is a constant vector which represents the optimum gate width for dB-linear characteristic and F(w) is a function which returns a vector. F(w) is the approximate function for the optimum gate width vector W. The widths Wn are the components of the vector W.

In an exemplary embodiment, a −10 dB low-power mode for a power of the transmitted signal SRF is requested. Therefore, the number of control bits of N equals 1. The value k equals −10 dB.

FIG. 3Ashows a table for the width WB of the first and the second transistors11,31and the width W0of the third and the fourth transistors51,71. The width according toFIG. 3Ais normalized in such a way that the sum of the widths equals 1. All four branches10,30,50,70have to be switched on to achieve a maximum power of the radio frequency signal SRF. The first and the second branch10,30are switched on in case of the −10 dB low power mode. If only the third and the fourth branch50,70are switched on, a −3.3 dB decreased output power of the radio frequency signal SRF is available.

FIG. 3Bshows an embodiment of a power control characteristic and width requirements for binary digit output power control. In this case, the optimum gate width equals the approximate gate width. The desired gain equals the gain realized with the selected width.

FIGS. 4A to 4Cshow exemplary tables comprising a width of transistors of an amplifier arrangement for eight gain levels. The power of the radio frequency signal SRF is controlled by using N=3 bits. Therefore, the amplifier arrangement comprises eight branches. The power ratio k equals −1 dB gain steps. Therefore, the gain control range comprises 7 dB.

FIG. 4Ashows a table of an embodiment with the widths of four different transistors using the binary digit approximation. The widths are normalized so that the sum of the widths equals 1.

FIG. 4Bcomprises the values of the specified gain in dB and of the specified optimum width of the transistors as well as the values of the approximate gain and of the approximate width of the transistors according to an embodiment. Because of the realization of the transistors11,31,51,71,91,111and so on in the form of multi-finger transistors, the approximate width of the transistors slightly differs from the specified gate width and, therefore, the approximate gain also differs from the specified gain.

FIG. 4Cshows a comparison of the specified gain and the approximate gain as a function of the different power control values. The values of the specified gain are on a straight line, while the approximate gain values are higher than the specified gain values in most cases.

FIGS. 5A to 5Cshow exemplary tables comprising a width of transistors of an amplifier arrangement for sixteen gain levels.

FIG. 5Ashows a table of an embodiment of the widths of the five transistors for the binary digit approximation.

The widths are normalized according to the table inFIG. 5A. The power of the radio frequency signal SRF is controlled with N=4 bits. The power ratio k equals −1 dB. Therefore, a gain control range of 15 dB is specified. The amplifier arrangement comprises ten branches.

FIG. 5Bshows a table of an embodiment with 16 different power control levels starting with a specified gain of −15 dB and ending with a specified gain of 0 dB. This results in a specified normalized width ranging from 0.1778 to 1.0000.

FIG. 5Cshows an embodiment of the specified gain and the approximate gain as a function of the 16 different power control levels.FIG. 5Cexhibits a difference between the specified gain values and the approximate gain values.

In an alternative embodiment, sub-ranging techniques could be implemented which use different sizes of the width WB of the base amplifier. It is an advantage of this alternative embodiment that the accuracy of approximation is increased.

FIG. 6Ashows an exemplary embodiment of an amplifier arrangement comprising two branches.FIG. 6Bshows an embodiment of measurement results obtained by using the amplifier arrangement ofFIG. 6A.

FIG. 6Ashows an amplifier arrangement which is a further development of the first and the second branch10,30of the amplifier arrangement shown inFIG. 2. The amplifier arrangement comprises a further control logic250which can be replaced by the control logic2shown inFIG. 2, the first and the second branches10,30and the current combiner3.

In accordance with the first branch10shown inFIG. 2, the first branch10comprises the first transistor11, the cascode transistor12, the first converter13, and the further inverter14. The second branch30comprises the second transistor31, the second cascode transistor32, the second inverter33, and the further inverter34. The series circuit comprising the first transistor11and the first cascode transistor12is arranged between the input terminal305of the current combiner3and the reference potential terminal8. In a similar way, the series circuit comprising the second transistor31and the second cascode transistor32is arranged between the second input terminal306of the current combiner3and the reference-potential terminal8.

The amplifier arrangement comprises a second supply voltage terminal900which is coupled to the reference-potential terminal8using two resistors24,25. A node in the series circuit of the two resistors24,25is coupled to the control terminal of the first and of the second cascode transistor12,32. The node in the series circuit of the two resistors24,25is coupled to the reference potential terminal8via a capacitor26.

The first impedance15couples the control terminal of the first and of the second transistor11,31. The second impedance16couples the input terminals of the first inverter13and of the second inverter32. The first and the second impedance15,16are designed in accordance with the first and the second impedance15,16shown inFIG. 2. A control terminal of the further inverter14is coupled to a control terminal of the further inverter34via a third impedance26. The third impedance26comprises two coils23,43, a capacitor45and a resistor44. A series circuit, comprising the two coils23,43, couples the input terminals of the two further inverters14,34together. A node between the coil23and the coil43is coupled to the reference potential terminal8via a parallel circuit of the capacitor45and the resistor44. The amplifier arrangement further comprises capacitors21,22,41,42which couple the supply voltage terminal9to the reference-potential terminal8.

The further control logic250comprises a first and a second Schmitt-Trigger gate251,252, four capacitors253to256, and four resistors257to260. An input terminal272of the further control logic250is coupled to an output terminal270of the further control logic250via a series circuit of the capacitor253and the Schmitt-Trigger gate251. In an analogous way, an input terminal273of the further control logic250is coupled to an output terminal271of the further control logic250via the capacitor254and the Schmitt-Trigger gate252. The supply voltage terminal9is connected to the reference-potential terminal8via the capacitors255and256, to the input terminal272via the resistor258, and to an input terminal of the Schmitt-Trigger gate251via the resistor257, to the input terminal273via the resistor260and to an input terminal of the Schmitt-Trigger gate252via a resistor259.

The data signal IN is provided to an input terminal272and a negative data signal IN− is provided to a further input terminal273of the further control logic250. The Schmitt-Trigger gates251,252generate digital signals S1, S2at the output terminals270,271of the further control logic250. The Schmitt-Trigger gates251,252generate the signals S1, S2in a digital form even if the data signal IN or the negative data signal IN− are not digital signals. The Schmitt-Trigger gates251,252are matched to a 50Ω system. The signal S1is amplified by the further inverter14, the first inverter13and the series circuit comprising the first transistor11and the first cascode transistor12. In an analogous manner, the signal S2is amplified by the further inverter34, the second inverter32and the series circuit comprising the second transistor31and the second cascode transistor32. The first, the second, and the third impedance15,16,26are used to compensate the capacitive input characteristics of the four inverters13,14,33,34and the first and the second transistors11,31. The first, the second, and the third impedances15,16,26define a power-up preconditioning voltage for a zero output current of the radio frequency signal SRF. The capacitors35,19,45help to suppress common mode oscillations and provide a defined supply voltage ramp-up preconditioning for the inverter logic states.

The amplified signals are provided to the input terminals305,306of the current combiner3. A voltage at the control terminals of the first and the second cascode transistors12,32can be determined by a second supply voltage VDD1provided at the second supply voltage terminal900and the two resistors24,25. Therefore, a fine adjustment of the power of the radio frequency signal SRF at the output of the current combiner3can be achieved.

A chip comprising the amplifier arrangement was produced in a 0.13 μm complimentary metal oxide semiconductor integration technique. According to this exemplary embodiment shown inFIG. 6A, the amplifier arrangement operates at a frequency of 1.9 GHz and achieves a gain of 28 dBm during a test. The supply voltage is about 1.5 V.

FIG. 6Bshows measurement results of the power of the radio frequency signal SRF at different values of the second supply voltage VDD1which is supplied at the second supply voltage terminal900. The second supply voltage VDD1ranges from 1.5 V to 2.5 V. The power is shown as a function of the frequency of the radio frequency signal SRF.

In an alternative embodiment, the amplifier arrangement comprises further branches which are designed similar to the first and the second branch10,30. The values of the widths of the several transistors may be chosen according to the tables inFIGS. 3A,3B,4A,4B,5A, and5B.

FIGS. 7A and 7Bshow another exemplary embodiment of an amplifier arrangement, comprising two branches and show measurement results obtained by using the amplifier arrangement.

FIG. 7Ashows an amplifier arrangement according to yet another embodiment which is a further development of the first and the second branch10,30of the amplifier arrangement shown inFIG. 6A. The amplifier arrangement comprises the further control logic250, the first and the second branch10,30and the current combiner3. The amplifier arrangement comprises the first supply voltage terminal9, the second supply voltage terminal900and a third supply voltage terminal901. The supply voltage VDD is supplied at the supply voltage terminal9, the second supply voltage VDD1is supplied at the second supply voltage terminal900, and the third supply voltage VDD3is supplied at the third supply voltage terminal901. The further control logic250is coupled to the supply voltage terminal9and operates with the supply voltage VDD. The further inverter14of the first branch10and the further inverter34of the second branch30are coupled to the supply voltage terminal9and the second supply voltage terminal900and, therefore, use the supply voltage VDD and the second supply voltage VDD1for operation. The first and the second inverter13,33are coupled to the second supply voltage terminal900and are operated using the second supply voltage VDD1. The series circuit comprising the resistors24,25is coupled between the third supply voltage terminal901and the reference-potential terminal8. Therefore, the voltage which is provided to the control terminals of the first and the second cascode transistors12,32is generated by the use of the third supply voltage VDD2.

Therefore, the further inverters14,34operate as level shifter between the further control logic250and the further parts of the first and the second branch10,30.

In an embodiment, the first and the second inverter13,33and the current combiner3are directly connected to a battery. A control logic2or a further control logic250can be operated by the supply voltage which has a lower value than the second and the third supply voltage.

In an embodiment, the amplifier arrangement shown inFIG. 7Awas tested at the frequency of the signals S1, S2of 900 MHz. The specified gain was 36 dBm.

FIG. 7Bshows measurement results of the power of the radio frequency signal SRF as a function of the frequency f of the signals S1, S2and the radio frequency signal SRF.FIG. 7Bshows the power with different values for the first supply voltage VDD2.

In an alternative embodiment, the amplifier arrangement according toFIG. 7Acomprises further branches.

FIG. 8Ashows a multi-finger transistor400which can be used for the implementation of the first to sixth transistors11,31,51,71,91,111shown in theFIGS. 1A to 1Cand of the transistors shown inFIGS. 2,6A, and7A. The multi-finger transistor400can also be used for implementation of the values of the approximate width in the tables ofFIGS. 3B,4B, and5B. The multi-finger transistor400shown inFIG. 8Ais implemented as a MOSFET. It comprises three source areas401,402,403and two drain areas404,405which are arranged in parallel. The three source areas401to403are coupled to a first terminal406of the multi-finger transistor400and the two drain areas404,405are coupled to a second terminal407of the multi-finger transistor400. Four gate electrodes408to411are arranged between the source and the drain areas and are coupled to the control terminal412of the multi-finger transistor400. The width of the source areas and of the drain areas has the value WSF.FIG. 8Ashows a multi-finger transistor400with a width of 4 WSF.

In an alternative embodiment, an additional drain area is added to the multi-finger transistor400shown inFIG. 8A. Therefore, the width of the alternative multi-finger transistor has the value 5 WSF.

In an alternative embodiment, the multi-finger transistor400comprises one source area401and one drain area404and, therefore, shows a width with the value WSF.

According to an embodiment, the width of a transistor is a multiple of the value WSF. Therefore, the values of the approximate width in the tables ofFIGS. 3B,4B, and5B differ from the values of the specified width in these three tables.

FIG. 8Bshows another example for a multi-finger transistor500which can be used for the implementation of the transistors shown inFIGS. 6A, and7A and for implementation of the values of the approximate width in the tables ofFIGS. 3B,4B, and5B.

The multi-finger transistor500comprises three source areas501,502,503and two drain areas504,505which extend in a main direction and are arranged in parallel. The three source areas501to503are coupled to a first terminal506of the multi-finger transistor500and the two drain areas504,505are coupled to a second terminal507of the multi-finger transistor500. Four gate electrodes508to511are arranged between the source and the drain areas. Three gate electrodes508to510of the four gate electrodes508to511are coupled to the control terminal512of the multi-finger transistor500and the gate electrode511is coupled to a further control terminal513of the multi-finger transistor500.FIG. 8Bshows a multi-finger transistor500comprising a transistor514with a width of 3 WSF and a further transistor515with a width of 1 WSF.

The control terminal512is coupled to the first inverter13. The further control terminal513is coupled to the first inverter13via a switch516. The state of the switch516is controlled by the control logic2. By closing the switch516, the current flowing through the multi-finger transistor500and the power of the radio frequency signal SRF are increased.

In an alternative embodiment, the multi-finger transistor500comprises more than two control terminals and is divided in more than two transistors.

FIG. 8Cshows an exemplary embodiment of a multi-finger transistor600which can be used for the implementation of the transistors shown inFIGS. 1A to 1Cand2, and for implementation of the values of the approximate width in the tables ofFIGS. 3B,4B, and5B.

The multi-finger transistor600comprises three source areas601to603and two drain areas604,605which extend in a main direction and are arranged parallel. The three source areas601to603are coupled to the first terminal606of the multi-finger transistor600and the two drain areas604,606are coupled to the second terminal607of the multi-finger transistor600. Four gate electrodes608to611are arranged between the source and the drain areas. Three gate electrodes608to610of the four gate electrodes608to611are coupled to the control terminal612of the multi-finger transistor600. The gate electrode611is coupled to the further control terminal613of the multi-finger transistor600.FIG. 8C, therefore, shows an embodiment of a multi-finger transistor600comprising the first transistor614with a width of 3 WSF and the second transistor615with a width of one WSF.

An output terminal of an inverter617is coupled to the control terminal612and an output terminal of a further inverter618is coupled to the further control terminal613.

In an embodiment, the multi-finger transistor600is inserted as the first transistor11and the third transistor51in the amplifier arrangement according toFIG. 1A. The inverter617corresponds to the first inverter13and the further inverter618corresponds to the third inverter53, shown inFIG. 1A.

In an alternative embodiment, the multi-finger transistor600comprises further drain and source areas and gate electrodes so that the multi-finger transistor600also comprises the fifth transistor91shown inFIG. 1A.

FIG. 8Dshows an exemplary embodiment of a multi-finger transistor700and a cascode transistor750. The cascode transistor750is also implemented in the form of a multi-finger transistor. The multi-finger transistor700and the cascode transistor750can be used for implementation of the transistors and the cascode transistors shown inFIGS. 2,6A, and7A and for implementation of the values of the approximate width in the tables ofFIGS. 3B,4B and5B, for example.

The multi-finger transistor700corresponds to the multi-finger transistor600shown inFIG. 8Cbesides that the multi-finger transistor700comprises a third terminal720. The drain area704is coupled to the second terminal707and the drain area705is coupled to the third terminal720.

The cascode transistor750comprises two source areas751,752and three drain areas753,754,755. The source area751is coupled to a first terminal756of the cascode transistor750and the source area752is coupled to a third terminal758of the cascode transistor750.

The three drain areas753to755are coupled to a second terminal757of the cascode transistor750. Four gate electrodes759to762are arranged between the source and the drain areas and are coupled to a control terminal763of the cascode transistor750. Therefore, the source area751of the cascode transistor750is coupled to the drain area704of the multi-finger transistor700. In a similar way the source area752of the cascode transistor750is coupled to the drain area705of the multi-finger transistor700.

FIG. 8Eshows another exemplary embodiment of a multi-finger transistor800and a cascode transistor850which is a further development of the transistors shown inFIG. 8D. The multi-finger transistor800and the cascode transistor850can be used for implementation of the transistors and the cascode transistors shown in theFIGS. 2,6A, and7A and for implementation of the values of the approximate width in the tables ofFIGS. 3B,4B and5B. The multi-finger transistor800corresponds to the multi-finger transistor700shown inFIG. 8D. The cascode transistor850corresponds to the cascode transistor750shown inFIG. 8Dbesides the features that the four gate areas859to862are not connected together. Three gate areas859to861are coupled to an inverter870and one gate area862is coupled to a further inverter871.

In an embodiment, the second terminal857of the cascode transistor850is coupled to the current combiner3which is not shown inFIG. 8E. The input terminals of the two inverters870,871are coupled to the control logic2which is not shown inFIG. 8E. As a result of this coupling the power generated at the output of the current combiner3can be further controlled by signals which are provided by the control logic2to the two inverters870,871.

FIG. 8Fshows another exemplary embodiment of a multi-finger transistor900which can be used for implementation of the transistors shown in the figures before. The multi-finger transistor900comprises three source areas901to903and two drain areas904,905which extend in a main direction and are arranged in parallel. The three source areas901to903are coupled to a first terminal906of the multi-finger transistor900and the two drain areas904,905are coupled to a second terminal907of the multi-finger transistor900. InFIG. 8Fan embodiment of a multi-finger dual-gate MOSFET is shown. Therefore, two gate electrodes908,909are arranged between the source areas901and the drain area904. Two further gate electrodes910,911are arranged between the drain area904and the source area902. Further gate electrodes912,913and additional gate electrodes914,915are arranged between the further drain and source areas. Four gate electrodes908,911,912,915are coupled to a first control terminal916. The other four gate electrodes909,910,913,914are coupled to a second control terminal917.

The multi-finger dual-gate MOSFET900can, for example, be used as the first transistor11inFIG. 1. In one embodiment, the first control terminal916can be coupled to the output terminal of the first inverter13. The second control terminal917can be coupled to a further output terminal of the control logic2. By the use of a signal provided to the second control terminal917the power which is provided by the transistor900and, therefore, the power provided by the radio frequency signal SRF can be adjusted.

FIG. 8Gshows another exemplary embodiment of a multi-finger transistor950which is a dual-gate transistor and can be used inFIGS. 1A to 1CandFIG. 2. The multi-finger transistor950can be inserted, for example, as the first transistor11and the third transistor51. The transistor950comprises three source areas951to953and two drain areas954,955. The three source areas951to953are coupled to a first terminal956of the multi-finger transistor950and the two drain areas954,955are coupled to a second terminal957of the multi-finger transistor950. Eight gate electrodes958to965are arranged between the source and the drain areas. A pair of two gate electrodes is located between a source and a drain area. The gate electrodes958,961,962are coupled to a first control terminal970. The gate electrodes959,960,963are coupled to a second control terminal971. The gate electrode964is coupled to a third control terminal972and gate electrode965is coupled to a fourth control terminal973. The first control terminal970corresponds to a control terminal of the first transistor11, while the third control terminal972corresponds to the control terminal of the third transistor51. Four inverters974to977are shown inFIG. 8G.

In an embodiment, the first inverter974corresponds to the first inverter13inFIG. 1Awhile the third inverter976corresponds to the third inverter53inFIG. 1A. The second control terminal971is coupled to an output terminal of the logic circuit2which is not shown inFIG. 8Gvia the second inverter975. Also the fourth control terminal973is coupled to an output terminal of the control logic2via the fourth inverter977. Using the control terminals971,973the output power provided by the transistor950can be further adjusted.

The transistors shown inFIGS. 8F and 8Gcan be used to implement switching-mode circuit functions such as switching-mode amplifiers, power digital analogue converters and switching-mode mixers.

In an alternative embodiment, the size of each finger can be designed to be different.

In another alternative embodiment, dummy fingers are arranged at the border of the transistor structure.

In yet another alternative embodiment, the transistors shown inFIGS. 8A to 8Gcan be implemented as bipolar transistors.

In one embodiment of the invention, an amplifier arrangement comprises a control logic, a first branch, a second branch and a current combiner. The first branch comprises a first transistor comprising a control terminal, which is coupled to the control logic to provide a first signal to the control terminal, a first terminal, which is coupled to a reference potential terminal, and a second terminal and a first cascode transistor comprising a control terminal, a first terminal, which is coupled to the second terminal of the first transistor, and a second terminal. The second branch comprises a second transistor comprising a control terminal, which is coupled to the control logic to provide a second signal to the control terminal, a first terminal, which is coupled to the reference potential terminal, and a second terminal, and a second cascode transistor comprising a control terminal, a first terminal, which is coupled to the second terminal of the second transistor, and a second terminal. The current combiner couples the second terminal of the first cascode transistor and the second terminal of the second cascode transistor to an output terminal of the amplifier arrangement and to a power supply terminal.

In another embodiment of the invention, an amplifier arrangement comprises a control logic, a first branch, a second branch and a current combiner. The first branch comprises a first multi-finger transistor comprising a first control terminal and a further control terminal, which are coupled to the control logic to provide a first signal to the first control terminal and a further signal to the further control terminal, a first terminal, which is coupled to a reference potential terminal, and a second terminal. The second branch comprises a second multi-finger transistor comprising a first control terminal and a further control terminal, which are coupled to the control logic to provide a second signal to the first control terminal and a further signal to the further control terminal, a first terminal, which is coupled to the reference potential terminal, and a second terminal. The current combiner couples the second terminal of the first multi-finger transistor and the second terminal of the second multi-finger transistor to an output terminal of the amplifier arrangement and to a power supply terminal.

In an further embodiment of the invention, a power amplifier comprises a control signal generator providing a first and a second signal, a first amplifier comprising a first transistor and a first cascode transistor for amplification of the first signal, a second amplifier comprising a second transistor and a second cascode transistor for amplification of the second signal, an output coupler which couples an output of the first amplifier and an output of the second amplifier to an output terminal of the amplifier arrangement.

In an embodiment of the invention, a method for amplifying a signal comprises feeding a first signal to a first branch of an amplifier arrangement; feeding a second signal to a second branch of the amplifier arrangement; amplifying the first signal by a first transistor and a first cascode transistor of the first branch and providing a first output signal; amplifying the second signal by a second transistor and a second cascode transistor of the second branch and providing a second output signal; combining the first output signal and the second output signal.

In another embodiment of the invention, a method for amplifying a signal comprises feeding a first signal to a first branch of an amplifier arrangement; feeding a second signal to a second branch of an amplifier arrangement; amplifying the first signal by a first multi-finger transistor comprised by the first branch and providing a first output signal; amplifying the second signal by a second multi-finger transistor comprised by the second branch and providing a second output signal; combining the first output signal and the second output signal.

In an additional embodiment of the invention, a method for designing an amplifier arrangement comprises calculating a width Wn according to the equation

Wn=W⁢⁢0*10k*(2N-1-n)20⁢⁢forn=0,1,…⁢⁢(2N-1),
wherein Wn is the width of a transistor of a branch, W0is a width of a basis transistor, N is the number of bits of the binary digits of an output level in dB and k are the dB steps.

In an embodiment, the first signal, the second signal, and the further signals are provided as digital signals by the control logic.

In a further embodiment, the second signal differs from the first signal. In an embodiment, the fourth signal differs from the third signal.

In an embodiment, the phase difference of the first and the second signal equals approximately 180 degrees and also the phase difference of the third and the fourth signal equals approximately 180 degrees.

In an embodiment, the first and the second transistor have the same value of the width-to-length ratio W/L. The third and the fourth transistor can also have the same value for the width-to-length ratio W/L. In a further embodiment, the width-to-length ratio W/L of the first and the second transistor differs from the width-to-length ratio W/L of the third and the fourth transistor.

In an embodiment, the lengths L of the first to the fourth and of the further transistors are approximately equal and the width of the first and of the second transistors differs from the width of the third and of the fourth transistors.

In an embodiment, an output terminal of the control logic is directly coupled to the control terminal of the first transistor of the first branch and corresponding output terminals are directly coupled to the control terminals of the corresponding transistors of the further branches. In an alternative embodiment, the output terminal of the control logic is coupled to the control terminal of the first transistor of the first branch via a first inverter. In a second alternative embodiment, the output terminal of the control logic is coupled to the control terminal of the first transistor of the first branch via two or more inverters. The further branches can by designed in an analogous manner.

In an embodiment, the signals which are provided to the control terminals of the cascode transistors of each branch are constant during a first mode of operation. In a further development, the power of a radio frequency signal provided at the output terminal of the current combiner is adjusted by the value of the signals provided to the control terminals of the cascode transistors.

In an alternative embodiment, the control terminals of the cascode transistors of each branch are coupled to further output terminals of the logic circuit. Therefore, the control logic is designed to adjust the power of the radio frequency signal in a second mode of operation.

In an embodiment, the current combiner comprises a balun. Therefore, two signals which are provided in a differential way to the current combiner can be converted in a single-ended signal. The single-ended signal can be provided to an antenna.

In an embodiment, the first to the fourth transistor of the first to the fourth branch comprise multi-finger transistors. In an embodiment, the multi-finger transistors comprise a first and a second terminal and at least two control terminals. The at least two control terminals of the multi-finger transistors are coupled to output terminals of the control logic. Therefore, different signals can be provided to the different control terminals of the multi-finger transistors. It is an advantage of this embodiment that the current flowing through a multi-finger transistor with two or more control terminals can be adjusted by the signal provided to the two or more control terminals.

In an embodiment, a signal is provided to the first control terminal of the multi-finger transistor and the signal is also provided to the second control terminal of the multi-finger transistor, depending on the state of a switch. In an embodiment, the switch may be arranged between the first control terminal of a multi-finger transistor and the second control terminal of the multi-finger transistor.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art, that any arrangement which is calculated to achieve the same purpose may be substituted of the specific embodiments shown. It is to be understood, that the above description is intended to be illustrative and not restrictive. This application is intended to cover any adaptations or variations of the invention. Combinations of the above embodiments and many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the invention includes any other embodiments and applications in which the above structures and methods may be used. The scope of the invention should, therefore, be determined with reference to the appended claims along with the scope of equivalents to which such claims are entitled.