Fast descriptor access for virtual network devices

A system includes a memory and a processor in communication with the memory. The processor is configured to execute a dependency mixing function that includes a first descriptor address of a descriptor and an artificial dependency. The dependency mixing function sets a second descriptor address as a dependency of a validity value. The processor is also configured to output a result from the dependency mixing function. When a respective validity value is valid, the second descriptor address is set to the first descriptor address. Responsive to the validity value being valid, the processor is configured to access the descriptor through the second descriptor address.

BACKGROUND

Computer systems may routinely copy memory entries from one memory to a different memory. For example, while forwarding incoming networking traffic to a physical or virtual machine, packets may be received and later copied to another memory location. Processors may execute instructions to read, write, and copy memory entries, such as packet addresses to forward networking traffic to different machines. In some instances, data may be validated and memory ordering may require memory barriers such as a read memory barrier to ensure that accessed data is valid.

SUMMARY

The present disclosure provides new and innovative systems and methods for fast descriptor access for virtual network devices. In an example, a system includes a memory and a processor in communication with the memory. The processor is configured to execute a dependency mixing function that includes a first descriptor address of a descriptor and an artificial dependency. The dependency mixing function sets a second descriptor address as a dependency of a validity value. The processor is also configured to output a result from the dependency mixing function. When a respective validity value is valid, the second descriptor address is set to the first descriptor address. Responsive to the validity value being valid, the processor is configured to access the descriptor through the second descriptor address.

In an example, a method includes executing, by a processor, a dependency mixing function that includes a first descriptor address of a descriptor and an artificial dependency. The dependency mixing function sets a second descriptor address as a dependency of a validity value. The method also includes outputting, by the processor, a result from the dependency mixing function. When a respective validity value is valid, the second descriptor address is set to the first descriptor address. Responsive to the validity value being valid, the method includes accessing, by the processor, the descriptor through the second descriptor address.

In an example, a method includes receiving, by a hypervisor, a data structure including data and a pointer with a pointer value. The hypervisor reads the pointer to determine the pointer value and executes a dependency mixing function to output a result based on the pointer and the pointer value. Responsive to determining a status of the result as satisfying a condition, the hypervisor performs a memory operation on the data structure.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Techniques are disclosed for fast descriptor access for virtual network devices. Communication overhead remains high for communication across security boundaries. Typically, the fastest communications are asynchronous using shared memory, which allows batching to reduce overheads and polling to remove the need for signaling. However, even with the batching and polling, typical network configurations often involve high overheads. For example, one such typical design may include a virtual network card with a descriptor that includes data, such as a packet address, supplied by a guest of a virtual machine. The data may be received by a hypervisor for transmission.

Typically, the data may include a descriptor with a valid flag or field, which allows detection that the data can be accessed by the hypervisor safely. The hypervisor may periodically read part of the descriptor to check that the descriptor is valid (e.g., by checking the valid flag or field). The descriptor may include a valid flag within the descriptor. The descriptor may be invalid if the data is not up to date or if the data is currently being modified. The hypervisor may periodically check the descriptor to determine when new data is ready for transmission. After determining that the descriptor is valid, the hypervisor may then read the rest of the descriptor to retrieve the actual data, such as the packet address. In an example, after transmitting the data, the hypervisor may set the descriptor to invalid until new data is received for transmission.

However, on most processor types, the two reads (e.g., (1) reading the valid flag or field and (2) reading the actual data such as the packet address) can be reordered by the processor. If the two reads are reordered, then at the time of reading the descriptor (e.g., packet address), the descriptor may not actually be valid yet. If the descriptor is not valid, the data such as the packet address may be dirty or inaccurate. To avoid reordering, a read memory barrier instruction may be issued that ensures that the descriptor read follows the valid flag read. Unfortunately, read memory barriers are computationally expensive and may significantly slow down execution especially for read memory barriers executed on Advanced RISC Machines (“ARMs”).

In some instances, a computer system may use a special API, such as a load acquire API that orders all accesses after a read. However, the use of an API such as the load acquire API is computationally expensive as it requires a sync instruction, such as a light-weight sync (“lwsynkc”). The light-weight sync instruction is used to control ordering for storage accesses to system memory. However, using the load acquire API generally only orders accesses between CPUs and is not effective when a driver is used with a hardware device that directly accesses memory (e.g., DMAs into memory).

In other instances, a device may replace a valid bit with an address in shared memory, and then the address is read to detect a valid descriptor, which is then later used for accessing the descriptor. However, this approach requires an extra memory access, which typically creates more pressure on the cache and negatively affects performance.

To address the problems discussed above, a dependency mixing function is implemented to safely access the descriptor after checking that the descriptor is valid, but without a memory barrier. Even though many CPU types reorder reads, most CPU architectures do not reorder a read of data at an address before a read of the address. Typically, a descriptor address is not a dependency of valid flag or field (e.g., validity value or validity bit). By using the dependency mixing function, the descriptor address is artificially made dependent on the valid flag or field. Specifically, given a validity value and the descriptor address, the dependency mixing function may include a series of instructions that calculate a function of the descriptor address and the validity value that is an identity function of the address when the validity value is valid. Then, the descriptor may safely be accessed through the calculated value (e.g., the calculated descriptor address that is dependent on the validity value) without the added latency of a read memory barrier.

The techniques discussed herein elide or avoid read memory barriers. By eliding read memory barriers, the systems and methods disclosed herein advantageously reduce overhead by using a less computationally expensive method of accessing a descriptor, thereby improving performance, throughput and latency for cross-security domain communication. Additionally, the techniques discussed herein may be used for ordering memory access between CPUs and with device drivers and hardware devices that DMA into memory.

Vendors using a hypervisor (e.g., Kernel-based Virtual Machine (“KVM”)) on an operating system, such as Red Hat® Enterprise Linux® (“RHEL”) may utilize the systems and methods disclosed herein for communication between virtual machines and the hypervisor. When handling network traffic and communication across security boundaries, hypervisor vendors and operating system (“OS”) vendors often attempt to improve performance, throughput and latency. By safely accessing a descriptor while eliding a memory barrier, the computational cost of memory barriers and other special APIs that order reads is avoided, and performance may be improved.

FIG. 1depicts a high-level component diagram of an example computing system100in accordance with one or more aspects of the present disclosure. The computing system100may include an operating system (e.g., host OS186), one or more virtual machines (VM170A-B), and nodes (e.g., nodes110A-C).

Virtual machines170A-B may include a guest OS, guest memory, a virtual CPU (VCPU), virtual memory devices (VMD), and virtual input/output devices (VI/O). For example, virtual machine170A may include guest OS196A, guest memory or virtual machine memory195A, a virtual CPU190A, a virtual memory devices192A, and virtual input/output device194A. Virtual machine memory195A may include one or more memory pages. Similarly, virtual machine170B may include guest OS196B, virtual machine memory195B, a virtual CPU190B, a virtual memory devices192B, and virtual input/output device194B. Virtual machine memory195B may include one or more memory pages.

The computing system100may also include a hypervisor180and host memory184. Hypervisor180may manage host memory184for the host operating system186as well as memory allocated to the virtual machines170A-B and guest operating systems196A-B such as guest memory or virtual machine memory195A-B provided to guest OS196A-B. Host memory184and virtual machine memory195A-B may be divided into a plurality of memory pages that are managed by the hypervisor180. Virtual machine memory195A-B allocated to the guest OS196A-B may be mapped from host memory184such that when a guest application198A-D uses or accesses a memory page of virtual machine memory195A-B, the guest application198A-D is actually using or accessing host memory184.

In an example, the hypervisor180may receive a data structure, such as a descriptor that includes data. A pointer may point to a validity value or pointer value within the data structure. The hypervisor180may determine the validity value and execute a dependency mixing function to output a result based on the address of the data structure (e.g., descriptor address) and the validity value. If the data structure is valid, the hypervisor180may perform a memory operation on the data structure (e.g., descriptor) without executing a memory barrier. For example, the hypervisor180may non-speculatively read the data contained in the data structure. Other memory operations includes reading the data structure and writing a new value into the data structure.

In an example, a virtual machine170A may execute a guest operating system196A and run applications198A-B which may utilize the underlying VCPU190A, VIVID192A, and VI/O device194A. One or more applications198A-B may be running on a virtual machine170A under the respective guest operating system196A. A virtual machine (e.g., VM170A-B, as illustrated inFIG. 1) may run on any type of dependent, independent, compatible, and/or incompatible applications on the underlying hardware and OS. In an example, applications (e.g., App198A-B) run on a virtual machine170A may be dependent on the underlying hardware and/or OS186. In another example, applications198A-B run on a virtual machine170A may be independent of the underlying hardware and/or OS186. For example, applications198A-B run on a first virtual machine170A may be dependent on the underlying hardware and/or OS186while applications (e.g., application198C-D) run on a second virtual machine (e.g., VM170B) are independent of the underlying hardware and/or OS186A. Additionally, applications198A-B run on a virtual machine170A may be compatible with the underlying hardware and/or OS186. In an example, applications198A-B run on a virtual machine170A may be incompatible with the underlying hardware and/or OS186. For example, applications198A-B run on one virtual machine170A may be compatible with the underlying hardware and/or OS186A while applications198C-D run on another virtual machine170B are incompatible with the underlying hardware and/or OS186A. In an example, a device may be implemented as a virtual machine (e.g., virtual machine170A-B).

The computer system100may include one or more nodes110A-C. Each node110A-C may in turn include one or more physical processors (e.g., CPU120A-E) communicatively coupled to memory devices (e.g., MD130A-D) and input/output devices (e.g., I/O140A-C). Each node110A-C may be a computer, such as a physical machine and may include a device, such as hardware device. In an example, a hardware device may include a network device (e.g., a network adapter or any other component that connects a computer to a computer network), a peripheral component interconnect (PCI) device, storage devices, disk drives, sound or video adaptors, photo/video cameras, printer devices, keyboards, displays, etc. Virtual machines170A-B may be provisioned on the same host or node (e.g., node110A) or different nodes. For example, VM170A and VM170B may both be provisioned on node110A. Alternatively, VM170A may be provided on node110A while VM170B is provisioned on node110B.

As used herein, physical processor or processor120A-E refers to a device capable of executing instructions encoding arithmetic, logical, and/or I/O operations. In one illustrative example, a processor may follow Von Neumann architectural model and may include an arithmetic logic unit (ALU), a control unit, and a plurality of registers. In a further aspect, a processor may be a single core processor which is typically capable of executing one instruction at a time (or process a single pipeline of instructions), or a multi-core processor which may simultaneously execute multiple instructions. In another aspect, a processor may be implemented as a single integrated circuit, two or more integrated circuits, or may be a component of a multi-chip module (e.g., in which individual microprocessor dies are included in a single integrated circuit package and hence share a single socket). A processor may also be referred to as a central processing unit (CPU).

As discussed herein, a memory device130A-D refers to a volatile or non-volatile memory device, such as RAM, ROM, EEPROM, or any other device capable of storing data. As discussed herein, I/O device140A-C refers to a device capable of providing an interface between one or more processor pins and an external device capable of inputting and/or outputting binary data.

Processors120A-E may be interconnected using a variety of techniques, ranging from a point-to-point processor interconnect, to a system area network, such as an Ethernet-based network. Local connections within each node, including the connections between a processor120A-E and a memory device130A-D may be provided by one or more local buses of suitable architecture, for example, peripheral component interconnect (PCI).

FIG. 2illustrates a block diagram of a descriptor200as well as an example dependency mixing function250. The descriptor200may include a validity value220or pointer value (e.g., such as a validity flag) and a pointer210that points to the validity value220. The descriptor200may have a descriptor address240and may also include data230. The descriptor200may include metadata about a packet, length information, and other data structures. In an example, the data230may be one or more packet addresses for data packets that are ready for transmission. In an example, the validity value220or pointer value (e.g., a validity flag) may be set to valid when new data230is ready to be transmitted. For example, a guest OS (e.g., guest OS196A) may supply a descriptor200or data230of the descriptor200(e.g., packet addresses) to the hypervisor180for transmission. When the guest OS196A supplies the descriptor200or data230, the guest OS196A may set the validity value220as valid. After the hypervisor180transmits the data, the hypervisor180may set the validity value220as invalid.

The descriptor200may be a structure that contains information that describes data. In an example, the descriptor200, such as a data descriptor may be used in a compiler. In another example, the descriptor200may be used as a software structure at run time. For example, the descriptor200may be used at run-time to pass argument information to a called subroutine. Additionally, the descriptor200may be used as a hardware structure in a computer system.

The dependency mixing function250may artificially introduce a dependency into a descriptor address240to ensure that the descriptor address240is read before the data230is read. Since the dependency mixing function250makes the descriptor address240dependent on the descriptor200being valid, the data230can be obtained with certainty of its validity with performing a computationally expensive memory barrier.

FIG. 3illustrates a flowchart of an example method300for fast descriptor access according to an example embodiment of the present disclosure. Although the example method300is described with reference to the flowchart illustrated inFIG. 3, it will be appreciated that many other methods of performing the acts associated with the method300may be used. For example, the order of some of the blocks may be changed, certain blocks may be combined with other blocks, blocks may be repeated, and some of the blocks described are optional. The method300may be performed by processing logic that may comprise hardware (circuitry, dedicated logic, etc.), software, or a combination of both.

The example method300includes executing a dependency mixing function that includes a first descriptor address of a descriptor and an artificial dependency (block210). For example, a processor120may execute a dependency mixing function250that includes a first descriptor address240of a descriptor200and an artificial dependency. The dependency mixing function250may set a second descriptor address as a dependency of a validity value220. The method also includes outputting a result from the dependency mixing function (block320). For example, the processor120may output a result from the dependency mixing function250. When a respective validity value220is valid, the second descriptor address is set to the first descriptor address240. For example, when a validity value220is valid, the second descriptor address and the first descriptor address240are the same such that the dependency mixing function250operates as an identity function. Then, method300includes accessing the descriptor through the second descriptor address (block330). For example, responsive to the validity value220being valid, the processor120may access the descriptor200through the second descriptor address. When the processor120reads the descriptor200through the descriptor address, the CPU120is blocked from reading speculatively. By accessing the descriptor200through the second descriptor address, method300advantageously allows for safely accessing the descriptor200while eliding a memory barrier.

For example, by making the descriptor address240artificially dependent on the validity value, the descriptor address240is read (and therefore the validity value is checked) prior to reading the data230. Specifically, the dependency mixing function250advantageously prevents speculative reads or out-of-order reads. The data230may be periodically updated and modified by other processes and out-of-order reads may result in a read of the data before the data is confirmed as valid. The dependency mixing function prevents a read of invalid data, which may result in a dirty read or transmitting old data. By artificially ordering the reads of the descriptor address240and then the descriptor200, memory barrier instructions may be elided or avoided, which reduces consumption of system resources.

FIG. 4illustrates a flowchart of an example method400for r fast descriptor access according to an example embodiment of the present disclosure. Although the example method400is described with reference to the flowchart illustrated inFIG. 4, it will be appreciated that many other methods of performing the acts associated with the method400may be used. For example, the order of some of the blocks may be changed, certain blocks may be combined with other blocks, blocks may be repeated, and some of the blocks described are optional. The method400may be performed by processing logic that may comprise hardware (circuitry, dedicated logic, etc.), software, or a combination of both.

The example method400includes receiving a data structure including data and a pointer value (block410). For example, a hypervisor180may receive a data structure including data230and a pointer value (e.g., a validity value220). For example, a pointer210may point to the pointer value (e.g., validity value220), which may indicate whether the data structure (e.g., descriptor200) is valid. In the example illustrated inFIG. 2, the data230of the descriptor200is valid when the pointer value (e.g., validity value220) is equal to “1”. Method400also includes reading a pointer to determine the pointer value (block420). For example, the hypervisor180may read a pointer210to determine the pointer value (e.g., validity value220). Additionally, method400includes executing a dependency mixing function to output a result based on the pointer and the pointer value (block430). The hypervisor180may execute a dependency mixing function250to output a result based on the pointer210and the pointer value (e.g., validity value220). For example, the dependency mixing function250may ensure that the pointer210is read to avoid a read of the data230of the data structure (e.g., descriptor200). Then, method400includes performing a memory operation on the data structure (block440). For example, responsive to determining a status of the results as satisfying a condition, the hypervisor180may perform a memory operation on the data structure (e.g., descriptor200).

FIG. 5illustrates a flowchart of an example method500for fast descriptor access for virtual network devices in accordance with an example embodiment of the present disclosure. Although the example method500is described with reference to the flowchart illustrated inFIG. 5, it will be appreciated that many other methods of performing the acts associated with the method500may be used. For example, the order of some of the blocks may be changed, certain blocks may be combined with other blocks, blocks may be repeated, and some of the blocks described are optional. For example, a hypervisor180may communicate with a guest OS196to perform example method500. The hypervisor180may use a dependency mixing function250for fast descriptor access.

In the illustrated example, the guest OS (e.g., guest OS196A or196B), referred to generally as guest OS196, may send a first descriptor200A to a hypervisor180(blocks502and504). Then, the hypervisor180may receive the first descriptor200A (block506). After receiving the first descriptor200A, the hypervisor180may determine whether the descriptor200A is valid (block508). Unlike typical designs where the hypervisor180periodically reads part of the descriptor to check if it is valid and then reading the descriptor to retrieve the actual data, which may require a memory read barrier to prevent the reads from being reordered, method500uses a dependency mixing function250to determine whether the descriptor200A is valid.

For example, the dependency mixing function250may include instructions to read a pointer (e.g., PTR1) to determine a validity value (blocks510and512). In the illustrated example, the pointer may store a memory address of the validity value and when the validity value is “1”, the descriptor200A is valid. Then, the dependency mixing function250includes an instruction to calculate the difference between the descriptor address240a(e.g., ADR_1) and a predetermined integer value of “1” (block514). For example, the dependency mixing function250may include an instruction to determine an intermediate result (“IntRes”) that is the difference of the descriptor address240aand a predetermined integer value of “1”, which is the same integer value as a valid validity value. The intermediate results (“IntRes”) is the descriptor address240a(“ADR_1”) minus “1” (e.g., ADR_1-1). Then, the dependency mixing function250may include another instruction to calculate the sum of the intermediate result (“IntRes”) and the validity value (e.g., “1”) (block516). For example, in the illustrated example, the final result of the dependency mixing function250is the intermediate result (“IntRes”=ADR_1-1) plus the validity value (e.g., “1”), which provides a final result of “ADR_1-1+1=ADR_1.” The final result of “ADR_1” ensures that the descriptor address240ais the same.

The dependency mixing function250returns the same descriptor address240a(e.g., ADR_1) of the first descriptor200A, which indicates that the descriptor200A is valid (block518). If the descriptor200A was invalid (e.g., perhaps by having a validity value of “0”), then the final result of the dependency mixing function would not have returned “ADR_1.” Then, the hypervisor180accesses the first descriptor200A non-speculatively and without performing a read memory barrier (block520).

At a later time, the guest OS196may send a second descriptor200B to the hypervisor180(blocks522and524). Then, the hypervisor180receives the second descriptor200B (block526). The hypervisor180determines whether the second descriptor200B is valid (block528). For example, similar to the first descriptor200A, the hypervisor180may determine whether the second descriptor200B is valid by using the dependency mixing function250.

According to the dependency mixing function250, the hypervisor180may read the pointer (e.g., PTR_2) (block530) and determine the validity value to be “0” (block532), which indicates that the descriptor200B is invalid. Then, the hypervisor180may calculate the difference between the descriptor address240b(e.g., ADR_2) and the predetermined integer value of “1” (block534). For example, the dependency mixing function250may include an instruction to determine an intermediate result (“IntRes”) that is the difference of the descriptor address240b“ADR_2” and a predetermined integer value of “1”. Then, the dependency mixing function250may include another instruction to calculate the sum of the intermediate result (“IntRes”) and the validity value (e.g., “0”) (block536). For example, in the illustrated example, the final result of the dependency mixing function250is the intermediate result (“IntRes”=ADR_2-1) plus the validity value (e.g., “0”), which provides a final result of “ADR_2-1+0=ADR_2-1.” The final result of “ADR_2-1” results in a different descriptor address that does not equal “ADR_2” (block536).

The dependency mixing function250returns a different descriptor address (e.g., “ADR_2-1”) of the second descriptor200B (block538), which indicates that the descriptor200B is invalid (block540). Then, the hypervisor180may execute a read memory barrier to ensure that the descriptor200B is valid before it is accessed (block542).

In another example, the dependency mixing function may introduce a dependency artificially by:

And used as

More generally, given a valid value that has been calculated to detect that the descriptor200is valid, and given the descriptor address240, the dependency mixing function250includes a series of instructions that calculate a function of the descriptor address240and validity value that is an identity function of the descriptor address240when the descriptor200is valid. In another example, the dependency mixing function250may include an “exclusive or” (“XOR”) operation between the descriptor address240and the validity value to obtain an intermediate result followed by another XOR of the intermediate result and the validity value.

An “exclusive or” (XOR) is a binary operation where the resulting bit evaluates to one if only exactly one of the bits is set. Additionally, a XOR gate may provide a true output, which may be considered a “1” or “HIGH” output when the number of true inputs is odd. For example, the output is true if the inputs are not alike otherwise the output is false.

The dependency mixing function250may include various different comparisons, calculations and modifications. For example, the dependency mixing function250may use arithmetic such as addition, subtraction, multiplication and division between the descriptor address240, the validity value220and other predetermined values. For example, if a validity value220is valid when the validity value220is “1”, the dependency mixing function250may multiply the descriptor address240by the validity value220and then divide by a predetermined value of “1” so that when the descriptor200is valid, the result of the dependency mixing function250will be the same descriptor address240. In some examples, where the validity value220or other predetermined values are known to be a constant, the dependency mixing function250may be simplified or some of the operations may be omitted.

The systems and methods discussed herein may also be applied to artificially order a write after read by making the write dependent on the read.

FIG. 6is a block diagram of an example fast descriptor access system600according to an example embodiment of the present disclosure. System600includes a memory610and a processor620in communication with the memory610. The processor620may be configured to execute a dependency mixing function630that includes a first descriptor address642A of a descriptor642and an artificial dependency644. The dependency mixing function630sets a second descriptor address642B as a dependency646of a validity value648. The processor620may also be configured to output a result650from the dependency mixing function630. When a respective validity value648is valid, the second descriptor address642B is set to the first descriptor address642A (e.g., the second descriptor address642B and the first descriptor address642A are the same when a respective validity value648is valid). Responsive to the validity value648being valid, the processor620may also be configured to access the descriptor642through the second descriptor address642B while eliding read memory barriers660.

By eliding read memory barriers, the fast descriptor access system600advantageously reduces overhead while safely accessing the descriptor642, thereby improving performance, throughput and latency for cross-security domain communication.

FIG. 7is a block diagram of another example fast descriptor access system700according to an example embodiment of the present disclosure. System700includes a memory710, a processor720in communication with the memory710, a guest operating system730, and a hypervisor740executing on the processor720. The hypervisor740may be configured to receive, from the guest OS730, a data structure750including data752and a pointer value754. The hypervisor740may also be configured to read a pointer756to determine the pointer value754and execute a dependency mixing function760that outputs a result770based on the pointer756and the pointer value754. Responsive to determining a status780of the result770as satisfying a condition782, the hypervisor740may be configured to perform a memory operation790on the data structure750.

Aspects of the subject matter described herein may be useful alone or in combination with one or more other aspects described herein. In a 1st exemplary aspect of the present disclosure a system includes a memory and a processor in communication with the memory. The processor is configured to execute a dependency mixing function that includes a first descriptor address of a descriptor and an artificial dependency. The dependency mixing function sets a second descriptor address as a dependency of a validity value. The processor is also configured to output a result from the dependency mixing function. When a respective validity value is valid, the second descriptor address is set to the first descriptor address. Responsive to the validity value being valid, the processor is configured to access the descriptor through the second descriptor address.

In accordance with a 2nd exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 1st aspect), accessing the descriptor occurs while eliding a read memory barrier.

In accordance with a 3rd exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 1st aspect), the descriptor is accessed non-speculatively.

In accordance with a 4th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 1st aspect), the validity value is a valid bit.

In accordance with a 5th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 1st aspect), the descriptor includes data and the data is a packet address.

In accordance with a 6th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 1st aspect), executing the dependency mixing function includes (i) calculating a difference between the first descriptor address and an integer to obtain an intermediate result, and (ii) calculating a sum of the intermediate result and the validity value to obtain the result.

In accordance with a 7th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 1st aspect), the dependency mixing function includes a XOR operation.

In accordance with an 8th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 1st aspect), the validity value is a fixed value.

In accordance with a 9th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 1st aspect), the result is the second descriptor address when the validity value is valid.

In accordance with a 10th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 1st aspect), the dependency mixing function is an identity function when the validity value is valid.

In accordance with an 11th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 1st aspect), executing the dependency mixing function includes (i) modifying the first descriptor address by a constant via an arithmetic operation to obtain an intermediate result and (ii) modifying the intermediate result by the value to obtain the result.

Aspects of the subject matter described herein may be useful alone or in combination with one or more other aspects described herein. In a 12th exemplary aspect of the present disclosure a method includes executing, by a processor, a dependency mixing function that includes a first descriptor address of a descriptor and an artificial dependency. The dependency mixing function sets a second descriptor address as a dependency of a validity value. The method also includes outputting, by the processor, a result from the dependency mixing function. When a respective validity value is valid, the second descriptor address is set to the first descriptor address. Responsive to the validity value being valid, the method includes accessing, by the processor, the descriptor through the second descriptor address.

In accordance with a 13th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 12th aspect), the accessing the descriptor occurs while eliding a read memory barrier.

In accordance with a 14th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 12th aspect), accessing the descriptor includes non-speculatively accessing the descriptor.

In accordance with a 15th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 12th aspect), the validity value is a valid bit.

In accordance with a 16th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 12th aspect), the descriptor includes data and the data is a packet address.

In accordance with an 17th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 12th aspect), executing the dependency mixing function includes calculating, by the processor, a difference between the first descriptor address and an integer to obtain an intermediate result, and calculating, by the processor, a sum of the intermediate result and the validity value to obtain the result.

In accordance with an 18th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 12th aspect), the dependency mixing function includes a XOR operation.

In accordance with a 19th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 12th aspect), the validity value is a fixed value.

In accordance with a 20th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 12th aspect), the result is the second descriptor address when the validity value is valid.

In accordance with a 21st exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 12th aspect), the dependency mixing function is an identity function.

In accordance with a 22nd exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 12th aspect), executing the dependency mixing function includes modifying the first descriptor address by a constant via an arithmetic operation to obtain an intermediate result, and modifying the intermediate result by the value to obtain the result.

Aspects of the subject matter described herein may be useful alone or in combination with one or more other aspects described herein. In a 23rd exemplary aspect of the present disclosure a non-transitory machine-readable medium stores code, which when executed by a processor, is configured to execute a dependency mixing function that includes a first descriptor address of a descriptor and an artificial dependency. The dependency mixing function sets a second descriptor address as a dependency of a validity value. The non-transitory machine-readable medium is also configured to output a result from the dependency mixing function. When a respective validity value is valid, the second descriptor address is set to the first descriptor address. Additionally, the non-transitory machine-readable medium is configured to access the descriptor through the second descriptor address responsive to the validity value being valid.

Aspects of the subject matter described herein may be useful alone or in combination with one or more other aspects described herein. In a 24th exemplary aspect of the present disclosure a system includes a means for executing a dependency mixing function that includes a first descriptor address of a descriptor and an artificial dependency. The dependency mixing function sets a second descriptor address as a dependency of a validity value. The system also includes a means for outputting a result from the dependency mixing function. When a respective validity value is valid, the second descriptor address is set to the first descriptor address. Additionally, the system includes a means for accessing the descriptor through the second descriptor address responsive to the validity value being valid.

Aspects of the subject matter described herein may be useful alone or in combination with one or more other aspects described herein. In a 25th exemplary aspect of the present disclosure a system includes a memory, a processor in communication with the memory, a guest operating system, and a hypervisor executing on the processor. The hypervisor is configured to receive, from the guest OS, a data structure including data and a pointer value. The hypervisor is also configured to read a pointer to determine the pointer value and execute a dependency mixing function that outputs a result based on the pointer and the pointer value. Responsive to determining a status of the result as satisfying a condition, the hypervisor is configured to perform a memory operation on the data structure.

In accordance with a 26th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 25th aspect), the condition is the result being valid.

In accordance with a 27th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 25th aspect), the memory operation occurs while eliding a read memory barrier.

In accordance with a 28th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 25th aspect), the memory operation is a non-speculative memory operation.

In accordance with a 29th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 25th aspect), the memory operation includes accessing the data structure.

In accordance with a 30th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 25th aspect), the memory operation includes reading the data structure.

In accordance with a 31st exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 25th aspect), the memory operation includes writing a new value into the data structure.

In accordance with a 32nd exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 25th aspect), the pointer value is a bit.

In accordance with a 33rd exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 25th aspect), the data includes a packet address.

In accordance with a 34th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 25th aspect), executing the dependency mixing function includes (i) calculating a difference between the pointer and an integer to obtain an intermediate result, and (ii) calculating a sum of the intermediate result and the pointer value to obtain the result.

In accordance with a 35th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 25th aspect), the dependency mixing function includes a XOR operation.

In accordance with a 36th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 25th aspect), the pointer value is a fixed value.

In accordance with a 37th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 25th aspect), the data structure is accessed through the result.

In accordance with a 38th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 25th aspect), executing the dependency mixing function includes (i) modifying the pointer by a constant via an arithmetic operation to obtain an intermediate result and (ii) modifying the intermediate result by the pointer value to obtain the result.

In accordance with a 39th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 25th aspect), the hypervisor is configured to determine the status of the result as one of valid and invalid.

Aspects of the subject matter described herein may be useful alone or in combination with one or more other aspects described herein. In a 40th exemplary aspect of the present disclosure a method includes receiving, by a hypervisor, a data structure including data and a pointer value. The method also includes reading, by the hypervisor, a pointer to determine the pointer value and executing, by the hypervisor, a dependency mixing function to output a result based on the pointer and the pointer value. Responsive to determining a status of the result as satisfying a condition, the method includes performing, by the hypervisor, a memory operation on the data structure.

In accordance with a 41st exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 40th aspect), the condition is the result being valid.

In accordance with a 42nd exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 40th aspect), the memory operation occurs while eliding a read memory barrier.

In accordance with a 43rd exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 40th aspect), the memory operation is a non-speculative memory operation that includes one of accessing the data structure, reading the data structure, and writing a new value into the data structure.

In accordance with a 44th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 40th aspect), executing the dependency mixing function includes (i) calculating a difference between the pointer and an integer to obtain an intermediate result, and (ii) calculating a sum of the intermediate result and the pointer value to obtain the result.

In accordance with a 45th exemplary aspect of the present disclosure, which may be used in combination with any one or more of the preceding aspects (e.g., the 40th aspect), executing the dependency mixing function includes (i) modifying the pointer by a constant via an arithmetic operation to obtain an intermediate result and (ii) modifying the intermediate result by the pointer value to obtain the result.

Aspects of the subject matter described herein may be useful alone or in combination with one or more other aspects described herein. In a 46th exemplary aspect of the present disclosure a non-transitory machine-readable medium stores code, which when executed by a processor, is configured to receive a data structure including data and a pointer value, read a pointer to determine the pointer value, and execute a dependency mixing function that outputs a result based on the pointer and the pointer value. Responsive to determining a status of the result as satisfying a condition, the non-transitory machine-readable medium is configured to perform a memory operation on the data structure.

Aspects of the subject matter described herein may be useful alone or in combination with one or more other aspects described herein. In a 47th exemplary aspect of the present disclosure a system includes a means for receiving a data structure including data and a pointer value, a means for reading a pointer to determine the pointer value, a means for executing a dependency mixing function that outputs a result based on the pointer and the pointer value, and a means for perform a memory operation on the data structure responsive to determining a status of the result as satisfying a condition.

To the extent that any of these aspects are mutually exclusive, it should be understood that such mutual exclusivity shall not limit in any way the combination of such aspects with any other aspect whether or not such aspect is explicitly recited. Any of these aspects may be claimed, without limitation, as a system, method, apparatus, device, medium, etc.