SEMICONDUCTOR DEVICE

A semiconductor device includes: a first semiconductor element; a second semiconductor element; a first insulating base member including a fifth face and a sixth face; a second insulating base member including a seventh face and an eighth face; a first wiring that penetrates through the first insulating base member, and disposed on the sixth face; a second wiring that penetrates through the second insulating base member, and disposed on the eighth face; a first wiring member that faces the second face of the first semiconductor element; and a second wiring member that is provided on the second wiring. The first wiring member is provided on the seventh face of the second insulating base member. A current flows in a first direction in the first wiring member, and flows in a second direction opposite to the first direction in the second wiring member.

This application claims priority from Japanese Patent Application No. 2021-183971, filed on Nov. 11, 2021, the entire contents of which are herein incorporated by reference.

BACKGROUND

Technical Field

The present disclosure relates to a semiconductor device.

Background Art

There has been known a semiconductor device in which each of semiconductor elements is attached to a film of a resin such as polyimide through an adhesive layer and a wiring layer is formed on a face of the resin film on an opposite side to the adhesive layer (e.g. see JP-A-2016-046523).

On the other hand, further reduction of inductance generated in the semiconductor device is demanded to achieve high-speed switching operation of the semiconductor device.

The present disclosure aims to provide a semiconductor device capable of reducing inductance.

SUMMARY

A certain embodiment provides a semiconductor device. The semiconductor device includes: a first semiconductor element including a first face and a second face opposite to the first face, wherein a first electrode is provided in the first face and a second electrode is provided in the second face; a second semiconductor element including a third face and a fourth face opposite to the third face, wherein a third electrode is provided in the third face and a fourth electrode is provided in the fourth face; a first insulating base member including a fifth face to which the first face of the first semiconductor element is adhesively bonded, and a sixth face opposite to the fifth face; a second insulating base member including a seventh face to which the third face of the second semiconductor element is adhesively bonded, and an eighth face opposite to the seventh face; a first wiring that penetrates through the first insulating base member to be electrically connected to the first electrode, and that is disposed on the sixth face of the first insulating base member; a second wiring that penetrates through the second insulating base member to be electrically connected to the third electrode, and that is disposed on the eighth face of the second insulating base member; a first wiring member that faces the second face of the first semiconductor element, and that is electrically connected to the second electrode; and a second wiring member that is provided on the second wiring to be electrically connected to the second wiring. The first wiring member is provided on the seventh face of the second insulating base member. The first wiring member and the second wiring member face each other and are electrically connected to each other. A current flows in a first direction in the first wiring member, and flows in a second direction opposite to the first direction in the second wiring member.

A certain embodiment provides a semiconductor device. The semiconductor device includes: a first semiconductor element including a first face and a second face opposite to the first face, wherein a first electrode is provided in the first face and a second electrode is provided in the second face; a second semiconductor element including a third face and a fourth face opposite to the third face, wherein a third electrode is provided in the third face and a fourth electrode is provided in the fourth face; a first insulating base member including a fifth face to which the first face of the first semiconductor element is adhesively bonded, and a sixth face opposite side to the fifth face; a second insulating base member including a seventh face to which the third face of the second semiconductor element is adhesively bonded, and an eighth face opposite to the seventh face; a first wiring that penetrates through the first insulating base member to be electrically connected to the first electrode, and that is disposed on the sixth face of the first insulating base member; a second wiring that penetrates through the second insulating base member to be electrically connected to the third electrode, and that is disposed on the eighth face of the second insulating base member; and a first wiring member that faces the second face of the first semiconductor element, and that is electrically connected to the second electrode. The first wiring member is provided on the seventh face of the second insulating base member. The first wiring member and the second wiring face each other, and are electrically connected to each other. A current flows in a first direction in the first wiring member, and flows in a second direction opposite to the first direction in the second wiring.

DESCRIPTION OF EMBODIMENTS

Embodiments of the present disclosure will be described below specifically with reference to the accompanying drawings. Incidentally, in the description of the present disclosure and the drawings, constituent elements that have substantially the same functional configurations will be designated by the same reference signs correspondingly and respectively, and duplicated explanation about these constituent elements may be therefore omitted. In addition, in the present disclosure, an X1-X2direction, a Y1-Y2direction and a Z1-Z2direction are set as directions mutually orthogonal to one another. A plane including the X1-X2direction and the Y1-Y2direction will be described as XY plane, a plane including the Y1-Y2direction and the Z1-Z2direction will be described as YZ plane, and a plane including the Z1-Z2direction and the X1-X2direction will be described as ZX plane. Incidentally, for convenience, the Z1-Z2direction will be set as an up-down direction, with the Z1side being an upper side and the Z2side being a lower side. In addition, the term “plan view” will mean a view of an object from the Z1side, and the term “planar shape” will mean the shape of the object viewed from the Z1side. However, a semiconductor device can be used in a vertically inverted state, or can be disposed at any angle.

First Embodiment

First, a first embodiment will be described. The first embodiment relates to a semiconductor device.

First, a sectional configuration of the semiconductor device according to the first embodiment will be described.FIG.1is a sectional view showing the semiconductor device according to the first embodiment.

As shown inFIG.1, the semiconductor device1according to the first embodiment has a semiconductor element10, a semiconductor element20, a flexible wiring substrate40, and a flexible wiring substrate80. For example, a device using silicon (Si) or silicon carbide (SiC) can be used as each of the semiconductor elements10and20. For example, a device using gallium nitride (GaN), gallium arsenide (GaAs) etc. also can be used as the semiconductor element10,20. For example, a semiconductor element acting as an active element (e.g. a silicon chip such as a CPU), an insulated gate bipolar transistor (IGBT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a diode, etc. can be used as the semiconductor element10,20. The semiconductor element10,20according to the present embodiment is a semiconductor element which includes electrodes provided in its front and back faces. The semiconductor element10,20can be set to have any shape and any size in terms of the planar shape. The semiconductor element10,20is, for example, formed into a rectangular shape in terms of the planar shape. Thickness of the semiconductor element10,20can be, for example, set in a range of about 50 μm to 500 μm.

The semiconductor element10has one face10A, and the other face10B located on an opposite side to the face10A. In addition, the semiconductor element10has a body portion15, electrodes11, an electrode12, and an electrode13. The electrodes11and the electrode13are provided in the face10A, and the electrode12is provided in the other face10B. For example, the electrodes11, the electrode12, and the electrode13can be set as source electrodes, a drain electrode, and a gate electrode, respectively.

The semiconductor element20has one face20A, and the other face20B located on an opposite side to the face20A. In addition, the semiconductor element20has a body portion25, electrodes21, an electrode22, and an electrode23. The electrodes21and the electrode23are provided in the face20A, and the electrode22is provided in the other face20B. For example, the electrodes21, the electrode22, and the electrode23can be set as source electrodes, a drain electrode, and a gate electrode, respectively.

For example, any of metals such as aluminum (Al) and copper (Cu), or an alloy containing at least one metal selected from these metals can be used as the material of the electrodes11, the electrode12, the electrode13, the electrodes21, the electrode22, and the electrode23(which may be hereinafter generically referred to as “electrodes”). Incidentally, if occasions demand, a surface treatment layer may be formed on each of surfaces of the electrodes. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer/Au layer (a metal layer in which the Ni layer and the Au layer are deposited in the named order), an Ni layer/palladium (Pd) layer/Au layer (a metal layer in which the Ni layer, the Pd layer, and the Au layer are deposited in the named order), etc. For example, a metal layer formed by an electroless plating method (an electroless plated metal layer) can be used as each of the Au layer, the Ni layer, and the Pd layer. In addition, the Au layer is a metal layer made of Au or an Au alloy, and the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy.

The flexible wiring substrate40has an insulating base member41, an insulating adhesive layer42, and a wiring layer45. The insulating base member41has one face41A, and the other face41B located on an opposite side to the face41A. The adhesive layer42is provided under the face41A, and the wiring layer45is provided on the other face41B. The wiring layer45is deposited on the other face41B. The wiring layer45has a seed layer43and a metal layer44.

The flexible wiring substrate80has an insulating base member81, an insulating adhesive layer82, and a wiring layer85. The insulating base member81has one face81A, and the other face81B located on an opposite side to the face81A. The adhesive layer82is provided on the face81A, and the wiring layer85is provided under the other face81B. The wiring layer85is deposited on the other face81B. The wiring layer85has a seed layer83and a metal layer84.

For example, a resin film etc. can be used as each of the insulating base members41and81. An insulating resin such as a polyimide-based resin, a polyethylene-based resin or an epoxy-based resin can be used as the material of the resin film. The insulating base member41,81has, for example, flexibility. Here, the term “flexibility” means a property of being able to be bent or flexed. The insulating base member41,81can be set to have any shape and any size in terms of the planar shape. The insulating base member41,81is, for example, formed into a rectangular shape in terms of the planar shape. Thickness of the insulating base member41,81can be, for example, set in a range of about 50 μm to 100 μm.

The semiconductor device1further has a lead terminal110, a lead terminal120, and a lead terminal130. Each of the lead terminals110,120, and130is, for example, formed from a lead frame. The lead terminal110,120,130is an example of a wiring member.

The semiconductor element10and the lead terminal130are adhesively bonded to the face41A of the insulating base member41by the adhesive layer42. The face10A of the semiconductor element10faces the face41A of the insulating base member41. Moreover, one face (Z1side) of the lead terminal130faces the face41A of the insulating base member41. Through holes51where the electrodes11are exposed, through holes53where the lead terminal130is exposed, and a through hole54where the electrode13is exposed are formed in the insulating base member41and the adhesive layer42.

As the material of the adhesive layer42, for example, an adhesive agent such as an epoxy-based adhesive agent, a polyimide-based adhesive agent, or a silicone-based adhesive agent can be used. Thickness of the adhesive layer42can be, for example, set in a range of about 20 μm to 40 μm.

For example, the electrodes11and the through holes51are located on an X2side of the electrode13and the through hole54, and the electrodes21and through holes52are located on an X1side of the electrode23and a through hole55. Pairs of the electrodes11and the through holes51may be provided, and pairs of the electrodes21and the through holes52may be provided.

The wiring layer45has a wiring61connected to the electrodes11through the through holes51, and a wiring63connected to the electrode13through the through hole54. The wiring61is also connected to the lead terminal130through the through holes53.

The wiring61includes via wirings filled in the through holes51, via wirings filled in the through holes53, and a wiring pattern formed on the other face41B of the insulating base member41. The wiring63includes a via wiring filled in the through hole54, and a wiring pattern formed on the other face41B of the insulating base member41.

The seed layer43covers the other face41B of the insulating base member41and inner faces of the through holes51,53and54. The seed layer43is formed to continuously cover the other face41B of the insulating base member41, the inner faces of the through holes51,53and54, and faces of the electrodes11,12, and13and a face of the lead terminal130exposed at the bottoms of the through holes51,53, and54. A metal film (sputtered film) formed by a sputtering method can be used as the seed layer43. For example, a metal film with a two-layer structure in which a titanium (Ti) layer made of Ti and a copper (Cu) layer made of Cu are sequentially deposited on the other face41B of the insulating base member41and the inner faces of the through holes51,53, and54can be used as the seed layer43formed by the sputtering method. In this case, thickness of the Ti layer can be, for example, set in a range of about 10 nm to 300 nm, and thickness of the Cu layer can be, for example, set in a range of about 100 nm to 1000 nm. Incidentally, the Ti layer functions as a close contact layer that improves close contactability of the seed layer43with the insulating base member41and the electrodes etc. In addition, the Ti layer also functions as a metal barrier layer that restrains copper from diffusing from the Cu layer etc. into the insulating base member41etc. In addition to the Ti, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), chrome (Cr), etc. can be used as the material of such a metal film functioning as the close contact layer and the metal barrier layer.

The semiconductor element20and the lead terminal110are adhesively bonded to the face81A of the insulating base member81by the adhesive layer82. The face20A of the semiconductor element20faces the face81A of the insulating base member81. The through holes52where the electrodes21are exposed and the through hole55where the electrode23is exposed are formed in the insulating base member81and the adhesive layer82.

For example, an adhesive agent such as an epoxy-based adhesive agent, a polyimide-based adhesive agent, or a silicone-based adhesive agent can be used as the material of the adhesive layer82. Thickness of the adhesive layer82can be, for example, set in a range of about 20 μm to 40 μm.

The wiring layer85has a wiring62connected to the electrodes21through the through holes52, and a wiring64connected to the electrode23through the through hole55.

The wiring62includes via wirings filled in the through holes52, and a wiring pattern formed on the other face81B of the insulating base member81. The wiring64includes a via wiring filled in the through hole55, and a wiring pattern formed on the other face81B of the insulating base member81.

The seed layer83covers the other face81B of the insulating base member81and inner faces of the through holes52and55. The seed layer83is formed to continuously cover the other face81B of the insulating base member81, the inner faces of the through holes52and55, and faces of the electrodes exposed at the bottoms of the through holes52and55. A metal film (sputtered film) formed by a sputtering method can be used as the seed layer83. For example, a metal film with a two-layer structure in which a titanium (Ti) layer made of Ti and a copper (Cu) layer made of Cu are sequentially deposited on the other face81B of the insulating base member81and the inner faces of the through holes52and55can be used as the seed layer83formed by the sputtering method. In this case, thickness of the Ti layer can be, for example, set in a range of about 10 nm to 300 nm, and thickness of the Cu layer can be, for example, set in a range of about 100 nm to 1000 nm. Incidentally, the Ti layer functions as a close contact layer that improves close contactability of the seed layer83with the insulating base member81and the electrodes etc. In addition, the Ti layer also functions as a metal barrier layer that restrains copper from diffusing from the Cu layer etc. into the insulating base member81etc. In addition to the Ti, titanium nitride (TiN), tantalum nitride (TaN), tantalum (Ta), chrome (Cr), etc. can be used as the material of such a metal film functioning as the close contact layer and the metal barrier layer.

For example, copper or a copper alloy can be used as the material of the metal layers44and84. For example, a metal layer formed by an electrolytic plating method (an electrolytic plated metal layer) can be used as each of the metal layers44and84.

One face (Z1side) of the lead terminal110is bonded to the electrode12of the semiconductor element10by an electrically conductive adhesive layer71. Moreover, the other face (Z2side) of the lead terminal110is adhesively bonded to the adhesive layer82. One face (Z1side) of the lead terminal120is bonded to the wiring62of the wiring layer45by an electrically conductive adhesive layer72. One face (Z2side) of the lead terminal130is bonded to the electrode22of the semiconductor element20by an electrically conductive adhesive layer73. Moreover, the other side (Z1side) of the lead terminal130is adhesively bonded to the adhesive layer42to be electrically connected to the wiring61. Each of the electrically conductive adhesive layers71to73is, for example, a solder layer or a sintered metal layer. The electrically conductive adhesive layer71,72,73may be made of an electrically conductive paste.

The semiconductor element10and the semiconductor element20are arranged side by side in a horizontal direction, e.g., in the X1-X2direction. The semiconductor element20is positioned on an X2side of the semiconductor element10.

The lead terminals110and120extend in parallel with each other toward the X1side, as viewed from the semiconductor element10. Accordingly, the semiconductor element20is disposed on an opposite side of the semiconductor element10to the direction in which the lead terminals110and120extend, as viewed from the semiconductor element10. A distance between the lead terminals110and120is nearly comparable to thickness of the flexible wiring substrate80. The distance between the lead terminals110and120is, for example, 1 mm or less (preferable in a range of 50 μm to 100 μm). Moreover, the lead terminal130extends toward the X2side, as viewed from the semiconductor element10. The lead terminals110and120face each other in the Z1-Z2direction, and are electrically connected to each other.

For example, thickness T1of the semiconductor element10and thickness T2of the semiconductor element20are equal to each other. Moreover, thickness T3of the lead terminal110and thickness T4of the lead terminal130are equal to each other. Therefore, thickness T5of a laminate structure body of the lead terminal110and the semiconductor element10and thickness T6of a laminate structure body of the semiconductor element20and the lead terminal130are equal to each other. Incidentally, the term “equal” in the present disclosure does not mean that the both are mathematically perfectly consistent with each other, but rather means that the both are in such a relationship that the both can be said to be “equal” to each other under socially accepted conventions. For example, one of the both is in a range of about 90% to 110% of the other.

The electrode12of the semiconductor element10is electrically connected to the lead terminal110. The electrodes21of the semiconductor element20are electrically connected to the lead terminal120through the wiring62. The electrodes11of the semiconductor element10and the electrode22of the semiconductor element20are electrically connected to the lead terminal130through the wiring61. Moreover, a lead terminal (not shown) is also connected to the wiring63of the wiring layer45, and this lead terminal is electrically connected to the electrode13of the semiconductor element10. In the same manner or a similar manner, a lead terminal (not shown) is also connected to the wiring64of the wiring layer85, and this lead terminal is electrically connected to the electrode23of the semiconductor element20.

Here, a circuit configuration of the semiconductor device1according to the first embodiment will be described.FIG.2is a circuit diagram showing the semiconductor device according to the first embodiment.

As shown inFIG.2, the electrode12of the semiconductor element10is electrically connected to a P terminal through the lead terminal110. The electrodes21of the semiconductor element20are electrically connected to an N terminal through the lead terminal120. Moreover, the electrodes11of the semiconductor element10and the electrode22of the semiconductor element20are electrically connected to an O terminal through the lead terminal130. The P terminal is a positive input terminal, the N terminal is a negative input terminal, and the O terminal is an output terminal. Accordingly, a current flows in the lead terminal110in a reverse direction to a direction in which the current flows in the lead terminal120.

[Method for Manufacturing Semiconductor Devices]

Next, a method for manufacturing the semiconductor devices according to the first embodiment will be described.FIGS.3A to3C,FIGS.4A to4C,FIGS.5A and5B, andFIGS.6A and6Bare sectional views showing the method for manufacturing the semiconductor devices according to the first embodiment. In the following description, a so-called multiple-piece manufacturing method will be described. That is, a part corresponding to a large number of semiconductor devices1is produced by batch and then divided into individual pieces to manufacture the semiconductor devices1. Incidentally, for convenience of explanation, portions that will finally become constituent elements of each of the semiconductor devices1will be designated by the same reference signs as those for the final constituent elements.

First, as shown inFIG.3A, a large-sized insulating base member41having one face41A and the other face41B is prepared. In the large-sized insulating base member41, for example, a plurality of individual regions in each of which a semiconductor device1should be formed are consecutively provided in a matrix form. Here, the individual regions are regions each of which will be finally cut into an individual piece along predetermined cutting lines to form the individual semiconductor device1. Incidentally, the number of the individual regions contained in the large-sized insulating base member41is not limited particularly. An insulating adhesive layer42that covers the entire face41A of the insulating base member41is provided on the face41A.

Next, as shown inFIG.3B, through holes51,53, and54are formed at required places in the insulating base member41and the adhesive layer42to penetrate through the insulating base member41and the adhesive layer42in a thickness direction. The through holes51,53and54can be formed, for example, by a laser machining method using a CO2laser, a UV-YAG laser, etc. or by a punching method. For example, the through holes51are formed on an X2side of the through hole54, and the through holes53are formed on an X2side of the through holes51.

Next, as shown inFIG.3C, a semiconductor element10and a lead terminal130are adhesively bonded to the insulating base member41by the adhesive layer42. On this occasion, alignment is performed to make one face10A of the semiconductor element10face the face41A of the insulating base member41, so that electrodes11overlap with the through holes51and an electrode13overlaps with the through hole54in plan view. In addition, alignment is performed to make the lead terminal130overlap with the through holes53in plan view.

Next, as shown inFIG.4A, a wiring layer45including a seed layer43and a metal layer44is formed on the other face41B of the insulating base member41. The wiring layer45can be formed, for example, by a semi-additive method.

Specifically, the seed layer43is formed to cover the entire other face41B of the insulating base member41and entire inner faces of the through holes51,53and54. The seed layer43can be formed, for example, by a sputtering method or an electroless plating method. In the case where, for example, the seed layer43is formed by the sputtering method, first, titanium is deposited by sputtering to form a Ti layer to thereby cover the other face41B of the insulating base member41and the inner faces of the through holes51,53, and54. Then, copper is deposited on the Ti layer by sputtering to form a Cu layer. Thus, the seed layer43having a two-layer structure (the Ti layer/the Cu layer) can be formed. Moreover, in the case where the seed layer43is formed by the electroless plating method, for example, the seed layer43consisting of a Cu layer (one-layer structure) can be formed by an electroless copper plating method.

Next, a plating resist layer (not shown) is formed on the seed layer43. The plating resist layer has opening portions provided in a portion where the wiring layer45should be formed, i.e. the portion where a wiring61and a wiring63should be formed. Successively, a metal layer44made of copper or the like is formed in the opening portions of the plating resist layer by an electrolytic plating method using the seed layer43as a plating power feed path. Then, the plating resist layer is removed. Next, with the metal layer44used as a mask, the seed layer43is removed by wet etching. In this manner, the wiring layer45including the seed layer43and the metal layer44can be formed. The wiring layer45has the wirings61and63. A flexible wiring substrate40is constituted by the insulating base member41, the adhesive layer42, and the wiring layer45.

Moreover, as shown inFIG.4B, a large-sized insulating base member81having one face81A and the other face81B is prepared. In the large-sized insulating base member81, for example, a plurality of individual regions in each of which the semiconductor device1should be formed are consecutively provided in a matrix form. Here, the individual regions are regions each of which will be finally cut into an individual piece along predetermined cutting lines to form the individual semiconductor device1. Incidentally, the number of the individual regions contained in the large-sized insulating base member81is not limited particularly. An insulating adhesive layer82that covers the entire face81A of the insulating base member81is provided on the face81A. Incidentally,FIGS.4B to5Billustrate a state in which the large-sized insulating base member81is rotated 180° around the Y1-Y2direction with respect toFIG.1.

Next, as shown inFIG.4C, through holes52and55are formed at required places in the insulating base member81and the adhesive layer82to penetrate through the insulating base member81and the adhesive layer82in the thickness direction. The through holes51and54can be formed, for example, by a method the same as or similar to the through holes52and55. For example, the through holes52are formed on an X1side of the through hole55.

Next, as shown inFIG.5A, a semiconductor element20and a lead terminal110are adhesively bonded to the insulating base member81by the adhesive layer82. On this occasion, alignment is performed to make one face20A of the semiconductor element20face the face81A of the insulating base member81, so that electrodes21overlap with the through holes52and an electrode23overlaps with the through hole55in the plan view. In addition, the lead terminal110is positioned on an X1side of the semiconductor element20.

Next, as shown inFIG.5B, a wiring layer85including a seed layer83and a metal layer84is formed on the other face81B of the insulating base member81. The wiring layer85can be formed, for example, by a method the same as or similar to the wiring layer45. The wiring layer85has wirings62and64. A flexible wiring substrate80is constituted by the insulating base member81, the adhesive layer82and the wiring layer85.

Next, as shown inFIG.6A, the flexible wiring substrate80is inverted vertically. Then, an electrically conductive adhesive layer71is provided on the lead terminal110, an electrically conductive adhesive layer72is provided on a Z2-side face of the wiring62of the wiring layer85, and an electrically conductive adhesive layer73is provided on a face20B of the semiconductor element20B. The electrically conductive adhesive layers71to73are in an uncured state.

Next, as shown inFIG.6B, an electrode12is bonded to the lead terminal110by the electrically conductive adhesive layer71, and the lead terminal130is bonded to an electrode22by the electrically conductive adhesive layer73. Moreover, a lead terminal120is bonded to the wiring62by the electrically conductive adhesive layer72. During the bonding, the electrically conductive adhesive layers71to73are cured.

In this manner, the semiconductor device1according to the first embodiment can be manufactured.

In the semiconductor device1according to the first embodiment, current flows from the P terminal toward the N terminal. Therefore, in the lead terminal110, the current flows from the X1side toward the X2side, and in the lead terminal120, the current flows from the X2side toward the X1side. Thus, inductance is generated between the lead terminal110and the lead terminal120. Moreover, in the present embodiment, the distance between the lead terminal110and the lead terminal120is nearly comparable to the thickness of the flexible wiring substrate80. Therefore, the distance between the lead terminal110and the lead terminal120becomes sufficiently small due to the thickness of the flexible wiring substrate80. Accordingly, the inductance between the lead terminal110and the lead terminal120which are parallel reciprocating conducting lines can be reduced. Thus, it is possible to provide the semiconductor device1that can achieve high-speed switching operation.

Moreover, the wiring layer45can be formed on the other face41B of the insulating base member41finely and with high accuracy by the semi-additive method, and the wiring layer85can be formed on the other face81B of the insulating base member81finely and with high accuracy by the semi-additive method. The wiring layer45may be alternatively formed on the other face41B of the insulating base member41by a subtractive method, and the wiring layer85may be alternatively formed on the other side81B of the insulating base member81by a subtractive method. Furthermore, the semiconductor element10is adhesively bonded to the face41A of the insulating base member41by the adhesive layer42so that the position of the semiconductor element10can be fixed to the insulating base member41and the wiring layer45, and the semiconductor element20is adhesively bonded to the face81A of the insulating base member81by the adhesive layer82so that the position of the semiconductor element20can be fixed to the insulating base member81and the wiring layer85. Therefore, according to the present embodiment, it is possible to obtain excellent positional accuracy and connection reliability. Particularly, the semiconductor elements10and20can be aligned with high accuracy. Further, it is possible to secure high connection reliability between the semiconductor element10and the insulating base member41, and it is possible to secure high connection reliability between the semiconductor element20and the insulating base member81.

Assume that a semiconductor device (power module) in which each of semiconductor elements is fixed to a metal foil (such as a copper foil) provided on the surface of an insulating substrate (such as a ceramic substrate) is manufactured as a reference example. In manufacturing such a semiconductor device, solder reflow is performed to fix the semiconductor element, so that the semiconductor element may be considerably misaligned during this reflow process. Therefore, a relatively large margin is required for the placement of the semiconductor element in a design phase.

On the other hand, in the present embodiment, the semiconductor element10is adhesively bonded to the insulating base member41in which the through holes51and54have been formed, and the wiring layer45is formed by the semi-additive method. In addition, the semiconductor element20is adhesively bonded to the insulating base member81in which the through holes52and55have been formed, and the wiring layer85is formed by the semi-additive method. Therefore, excellent positional accuracy and connection reliability can be obtained so that large margins as in the reference example are not required.

Furthermore, the thickness T5of the laminate structure body of the lead terminal110and the semiconductor element10and the thickness T6of the laminate structure body of the semiconductor element20and the lead terminal130are equal to each other. Therefore, it is easy to perform alignment to bond the electrode12to the lead terminal110by the electrically conductive adhesive layer71and bond the lead terminal130to the electrode22by the electrically conductive adhesive layer73.

Second Embodiment

Next, a second embodiment will be described.FIG.7is a sectional view showing a semiconductor device according to the second embodiment.

As shown inFIG.7, the semiconductor device2according to the second embodiment has a lead terminal210in place of the lead terminal110, and has a lead terminal230in place of the lead terminal130. Each of the lead terminals210and230is formed, for example, from a stepped lead frame. The lead terminal210,230is an example of a wiring member.

The lead terminal210has a junction portion211and an extension portion212. The junction portion211is thicker than the extension portion212. For example, thickness of the extension portion212is equal to the thickness T3of the lead terminal110in the first embodiment, and thickness T7of the junction portion211is larger than the thickness T3. The junction portion211is bonded to an electrode12of a semiconductor element10by an electrically conductive adhesive layer71, and adhesively bonded to one face81A of an insulating base member81by an adhesive layer82. The extension portion212extends from the junction portion211toward an X1side. For example, a Z1-side face of the junction portion211and a Z1-side face of the extension portion212are flush with each other. The junction portion211is an example of a first junction portion, and the extension portion212is an example of a first extension portion.

The lead terminal230has a junction portion231and an extension portion232. The junction portion231is thicker than the extension portion232. For example, thickness of the extension portion232is equal to the thickness T4of the lead terminal130in the first embodiment, and thickness T8of the junction portion231is larger than the thickness T4. The junction portion231is bonded to an electrode22of a semiconductor element20by an electrically conductive adhesive layer73, and adhesively bonded to one face41A of an insulating base member41by an adhesive layer42. The extension portion232extends from the junction portion231toward an X2side. For example, a Z2-side face of the junction portion231and a Z2-side face of the extension portion232are flush with each other. The junction portion231is an example of a second junction portion, and the extension portion232is an example of a second extension portion. The lead terminal210and a lead terminal120face each other in an X1-X2direction, and are electrically connected to each other.

For example, the thickness T7of the junction portion211and the thickness T8of the junction portion231are equal to each other. Therefore, thickness T9of a laminate structure body of the junction portion211and the semiconductor element10and thickness T10of a laminate structure body of the semiconductor element20and the junction portion231are equal to each other.

The remaining configuration is the same as or similar to that in the first embodiment.

In order to manufacture the semiconductor device2according to the second embodiment, the lead terminals210and230are prepared in advance. Then, the lead terminal210is bonded to the semiconductor element10and the insulating base member81in place of the lead terminal110, and the lead terminal230is bonded to the semiconductor element20and the insulating base member41in place of the lead terminal130. In this manner, the semiconductor device2can be manufactured.

In the semiconductor device2according to the second embodiment, current also flows from a P terminal toward an N terminal. Therefore, in the lead terminal210, the current flows from the X1side toward the X2side, and in the lead terminal120, the current flows from the X2side toward the X1side. Thus, inductance is generated between the lead terminal210and the lead terminal120. On the other hand, a distance between the lead terminal210and the lead terminal120is defined by the sum of a difference in thickness between the junction portion211and the extension portion212and thickness of a flexible wiring substrate80. Accordingly, the distance between the lead terminal210and the lead terminal120becomes sufficiently small. Thus, the inductance between the lead terminal210and the lead terminal120which are parallel reciprocating conducting lines can be reduced. Accordingly, it is possible to provide the semiconductor device2that can achieve high-speed switching operation and it is possible to sufficiently dissipate heat generated from the semiconductor element10by the junction portion211. Moreover, the semiconductor device2having excellent positional accuracy and connection reliability can be provided in a manner the same as or similar to that in the first embodiment.

Furthermore, the thickness T9of the laminate structure body of the junction portion211and the semiconductor element10and the thickness T10of the laminate structure body of the semiconductor element20and the junction portion231are equal to each other. Therefore, it is easy to perform alignment to bond the electrode12to the lead terminal210by the electrically conductive adhesive layer71, and bond the junction portion231to the electrode22by the electrically conductive adhesive layer73.

In addition, the junction portion211is thicker than the extension portion212. Therefore, the lead terminal210is separated from the lead terminal120so as to make it easy to prevent a short circuit between the lead terminals210and120.

Third Embodiment

Next, a third embodiment will be described.FIG.8is a sectional view showing a semiconductor device according to the third embodiment.

As shown inFIG.8, in the semiconductor device3according to the third embodiment, a flexible wiring substrate80extends along a Z2-side face of a lead terminal110toward an X1side. In addition, a lead terminal120is absent. The lead terminal110and a wiring62face each other in an X1-X2direction, and are electrically connected to each other.

The remaining configuration are the same as or similar to that in the first embodiment.

For example, to adhesively bond the lead terminal110to one face81A of an insulating base member81in order to manufacture the semiconductor device3according to the third embodiment, alignment has to be performed to make the lead terminal110and the wiring62extend in a common direction (toward the X1side) as viewed from a semiconductor element10.

In the semiconductor device3according to the third embodiment, the wiring62of a wiring layer85exerts a function the same as or similar to the lead terminal120. Thus, inductance is generated between the lead terminal110and the wiring62. On the other hand, a distance between the lead terminal110and the wiring62becomes sufficiently small due to thickness of the flexible wiring substrate80. Thus, the inductance between the lead terminal110and the wiring62, which are parallel reciprocating conducting lines, can be reduced more than that in the first embodiment. In addition, the semiconductor device3having excellent positional accuracy and connection reliability can be provided in a manner the same as or similar to that in the first embodiment. Furthermore, a step required for bonding the lead terminal120can be omitted.

Although the preferred embodiments etc. have been described above in detail, the present disclosure is not limited to the aforementioned embodiments etc., but various modifications and substitutions can be made on the aforementioned embodiments etc. without departing from the scope described in Claims.