Source driver circuit, method for driving display panel and display device

The present disclosure provides a source driver IC. A first sub-driver circuit is provided to, within a time period, control polarities of driving voltages for a first subpixel and a third subpixel in pixel units at odd-numbered positions in a pixel row to be reverse to polarities of driving voltages for a second subpixel and a fourth subpixel in the pixel units at the odd-numbered positions in the pixel row, and a second sub-driver circuit is provided to, within the time period, control polarities of driving voltages for a first subpixel and a third subpixel in the pixel units at even-numbered positions to be identical to polarities of driving voltages for the second subpixel and the fourth subpixel in the pixel units at the odd-numbered positions but reverse to polarities of driving voltages for the second subpixel and the fourth subpixel in the pixel units at the even-numbered positions.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims a priority of the Chinese patent application No. 201410433197.8 filed on Aug. 28, 2014, which is incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present disclosure relates to the field of display technology, in particular to a source driver circuit applicable to a four-primary-color pixel unit, a method for driving a display panel and a display device.

DESCRIPTION OF THE PRIOR ART

Driver circuits for a thin film transistor liquid crystal display (TFT-LCD) include a power integrated circuit (Power IC), a timing controller IC, a grayscale IC, a source driver IC, a gate driver IC, and a system interface (System I/F), etc.

As shown inFIG. 1, the timing controller circuit generates display-related drive control signals and data based on image data inputted from the outside, and transmits them to the source driver IC, so that the source driver circuit converts the display-related drive control signals into corresponding analog voltage signals and outputs them to a display panel. These drive control signals may include a polarity reversal signal (POL) for controlling a polarity of the data outputted by the source driver circuit within each frame.

FIG. 2is a schematic view showing the data output between an existing source driver circuit and a display panel with a three-primary-color pixel unit (Dot). As shown inFIG. 2, an existing pixel driving method may be used to enable polarities of driving voltages, i.e., positive and negative, for subpixels at odd-numbered positions and at even-numbered positions in the three-primary-color pixel unit to be different from each other, i.e., to achieve a phase difference of 180°. In addition, the subpixels at identical positions in adjacent pixel units are also of different polarities. As a result, horizontal polarity inclination may be prevented, and then the occurrence of crosstalk may be avoided. InFIG. 2, Dn represents an nthdata line connecting the source driver circuit to the pixel unit, an unshaded region, e.g., R1and B1, represents a region where the subpixel is in a positive polarity drive mode, a shaded region, e.g., G1, R2, represents a region where the subpixel is in a negative polarity drive mode. Rn, Gn and Bn represent positions of subpixels for displaying corresponding primary colors in an nthpixel unit, respectively. The same reference signs in the other drawings have the same meaning.

Along with the development of the display technology, the subpixels included in each pixel unit of the existing display panel are changed from being in the three primary colors (Red, Green and Blue) to being in the four primary colors (Red, Green, Blue and White), so as to provide rich and natural colors.

However, if the existing pixel driving method is adopted, there is such a phenomenon as shown inFIG. 3for the four-primary-color pixel unit, i.e., the polarities of the driving voltages for the subpixels at the same positions (e.g., R1and R2) in the adjacent pixel units are the same, resulting that crosstalk occurs at the display panel.

SUMMARY OF THE INVENTION

The present disclosure provides a source driver IC, a method for driving a display panel, and a display device, which can prevent the occurrence of crosstalk at a display panel and thus ensure the image quality.

Technical solutions provided in the present disclosure are as follows.

One embodiment of the present disclosure provides a source driver circuit connected to a display panel. The display panel includes a plurality of pixel units, each of which includes a first subpixel, a second subpixel, a third subpixel and a fourth subpixel arranged sequentially in a horizontal direction.

The source driver circuit includes:

a first sub-driver circuit connected to pixel electrodes corresponding to pixel units at odd-numbered positions in each pixel row and configured to, within a time period, transmit voltage signals at corresponding potentials to the pixel electrodes corresponding to the pixel units at the odd-numbered positions, so as to control, within the time period, polarities of driving voltages for the first subpixels and the third subpixels in the pixel units at the odd-numbered positions to be reverse to polarities of driving voltages for the second subpixels and the fourth subpixels in the pixel units at the odd-numbered positions; and

a second sub-driver circuit connected to pixel electrodes corresponding to pixel units at even-numbered positions in each pixel row and configured to, within the time period, transmit voltage signals at corresponding potentials to the pixel electrodes corresponding to the pixel units at the even-numbered positions, so as to control polarities of driving voltages for the first subpixels and the third subpixels in the pixel units at the even-numbered positions to be identical to the polarities of the driving voltages for the second subpixels and the fourth subpixels in the pixel units at the odd-numbered positions, and control, within the time period, polarities of driving voltages for the second subpixels and the fourth subpixels in the pixel units at the even-numbered positions to be identical to the polarities of the driving voltages for the first subpixels and the third subpixels in the pixel units at the odd-numbered positions.

Optionally, the first sub-driver circuit includes:

a first control module configured to generate a first voltage signal at a first potential greater than a potential of a common electrode in the display panel based on a logic digital signal, and connected to a logic digital signal generation unit, a first analog voltage input end and a second analog voltage input end;

a second control module configured to generate a second voltage signal at a second potential less than the potential of the common electrode based on the logic digital signal, and connected to the logic digital signal generation unit, the second analog voltage input end and a third analog voltage input end;

a first output end configured to transmit the first voltage signal or the second voltage signal to the pixel electrodes corresponding to the first subpixels and the third subpixels in the pixel units at the odd-numbered positions, and connected to the pixel electrodes corresponding to the first subpixels and the third subpixels in the pixel units at the odd-numbered positions;

a second output end configured to transmit the second voltage signal or the first voltage signal to the pixel electrodes corresponding to the second subpixels and the fourth subpixels in the pixel units at the odd-numbered positions, and connected to the pixel electrodes corresponding to the second subpixels and the fourth subpixels in the pixel units at the odd-numbered positions; and

a first selection switch configured to, based on a control logic, connect the first output end to the first control module and connect the second output end to the second control module within a first display duration of the time period so that the first output end outputs the first voltage signal and the second output end outputs the second voltage signal, and connect the first output end to the second control module and connect the second output end to the first control module within a second display duration of the time period so that the first output end outputs the second voltage signal and the second output end outputs the first voltage signal, the first selection switch being connected to the first control module, the second control module, the first output end and the second output end, and the first display duration and the second display duration alternating within the time period.

Optionally, the first control module includes:

a first level shifter configured to select from the logic digital signals a first digital voltage signal corresponding to the first voltage signal, and connected to the logic digital signal generation unit;

a first digital-to-analog converter configured to convert the first digital voltage signal into a corresponding first analog voltage signal, and connected to the first level shifter, the first analog voltage input end and the second analog voltage input end; and

a first amplifier configured to amplify the first analog voltage signal, and connected to the first digital-to-analog converter and the first selection switch.

Optionally, the second control module includes:

a second level shifter configured to select from the logic digital signals a second digital voltage signal corresponding to the second voltage signal, and connected to the logic digital signal generation unit;

a second digital-to-analog converter configured to convert the second digital voltage signal into a corresponding second analog voltage signal, and connected to the second level shifter, the second analog voltage input end and the third analog voltage input end; and

a second amplifier configured to amplify the second analog voltage signal, and connected to the second digital-to-analog converter and the first selection switch.

a third control module configured to generate a third voltage signal at a third potential greater than the potential of the common electrode in the display panel based on the logic digital signal, and connected to the logic digital signal generation unit, the first analog voltage input end and the second analog voltage input end;

a fourth control module configured to generate a fourth voltage signal at a fourth potential less than the potential of the common electrode based on the logic digital signal, and connected to the logic digital signal generation unit, the second analog voltage input end and the third analog voltage input end;

a third output end configured to transmit the fourth voltage signal or the third voltage signal to the pixel electrodes corresponding to the second subpixels and the fourth subpixels in the pixel units at the even-numbered positions, and connected to the pixel electrodes corresponding to the second subpixels and the fourth subpixels in the pixel units at the even-numbered positions;

a fourth output end configured to transmit the third voltage signal or the fourth voltage signal to the pixel electrodes corresponding to the first subpixels and the third subpixels in the pixel units at the even-numbered positions, and connected to the pixel electrodes corresponding to the first subpixels and the third subpixels in the pixel units at the even-numbered positions; and

a second selection switch configured to, based on a control logic, connect the third output end to the fourth control module and connect the fourth output end to the third control module within the first display duration of the time period so that the third output end outputs the fourth voltage signal and the fourth output end outputs the third voltage signal, and connect the third output end to the third control module and connect the fourth output end to the fourth control module within the second display duration of the time period so that the third output end outputs the third voltage signal and the fourth output end outputs the fourth voltage signal, the second selection switch being connected to the third control module, the fourth control module, the third output end and the fourth output end, and the first display duration and the second display duration alternating within the time period.

Optionally, the third control module includes:

a third level shifter configured to select from the logic digital signals a third digital voltage signal corresponding to the third voltage signal, and connected to the logic digital signal generation unit;

a third digital-to-analog converter configured to convert the third digital voltage signal into a corresponding third analog voltage signal, and connected to the third level shifter, the first analog voltage input end and the second analog voltage input end; and

a third amplifier configured to amplify the third analog voltage signal, and connected to the third digital-to-analog converter and the second selection switch.

Optionally, the fourth control module includes:

a fourth level shifter configured to select from the logic digital signals a fourth digital voltage signal corresponding to the fourth voltage signal, and connected to the logic digital signal generation unit;

a fourth digital-to-analog converter configured to convert the fourth digital voltage signal into a corresponding fourth analog voltage signal, and connected to the fourth level shifter, the second analog voltage input end and the third analog voltage input end; and

a fourth amplifier configured to amplify the fourth analog voltage signal, and connected to the fourth digital-to-analog converter and the second selection switch.

One embodiment of the present disclosure provides a method for driving a display panel. The display panel includes a plurality of pixel units, each of which includes a first subpixel, a second subpixel, a third subpixel and a fourth subpixel arranged sequentially in a horizontal direction.

The method includes steps of:

within a time period, transmitting voltage signals at corresponding potentials to pixel electrodes corresponding to the pixel units at odd-numbered positions in each pixel row, so as to control, within the time period, polarities of driving voltages for the first subpixels and the third subpixels in the pixel units at the odd-numbered positions to be reverse to polarities of driving voltages for the second subpixels and the fourth subpixels in the pixel units at the odd-numbered positions; and

within the time period, transmit voltage signals at corresponding potentials to the pixel electrodes corresponding to the pixel units at even-numbered positions, so as to control, within the time period, polarities of driving voltages for the first subpixels and the third subpixels in the pixel units at the even-numbered positions to be identical to the polarities of the driving voltages for the second subpixels and the fourth subpixels in the pixel units at the odd-numbered positions, and control, within the time period, polarities of driving voltages for the second subpixels and the fourth subpixels in the pixel units at the even-numbered positions to be identical to the polarities of the driving voltages for the first subpixels and the third subpixels in the pixel units at the odd-numbered positions.

Optionally, the step of within a time period, transmitting voltage signals at corresponding potentials to pixel electrodes corresponding to the pixel units at odd-numbered positions in each pixel row, so as to control, within the time period, polarities of driving voltages for the first subpixels and the third subpixels in the pixel units at the odd-numbered positions to be reverse to polarities of driving voltages for the second subpixels and the fourth subpixels in the pixel units at the odd-numbered positions includes:

generating a first voltage signal at a first potential greater than a potential of a common electrode in the display panel and a second voltage signal at a second potential less than the potential of the common electrode in the display panel based on a logic digital signal; and

based on a control logic, connecting a first output end to a first control module and connecting a second output end to a second control module within a first display duration of the time period so that the first output end outputs the first voltage signal and the second output end outputs the second voltage signal, and connecting the first output end to the second control module and connecting the second output end to the first control module within a second display duration of the time period so that the first output end outputs the second voltage signal and the second output end outputs the first voltage signal, the first display duration and the second display duration alternating in the time period.

Optionally, the step of, within the time period, transmitting voltage signals at corresponding potentials to the pixel electrodes corresponding to the pixel units at even-numbered positions, so as to control, within the time period, polarities of driving voltages for the first subpixels and the third subpixels in the pixel units at the even-numbered positions to be identical to the polarities of the driving voltages for the second subpixels and the fourth subpixels in the pixel units at the odd-numbered positions, and control, within the time period, polarities of driving voltages for the second subpixels and the fourth subpixels in the pixel units at the even-numbered positions to be identical to the polarities of the driving voltages for the first subpixels and the third subpixels in the pixel units at the odd-numbered positions includes:

based on the logic digital signal, generating a third voltage signal at a third potential greater than the potential of the common electrode in the display panel and a fourth voltage signal at a fourth potential less than the potential of the common electrode in the display panel; and

based on the control logic, connecting a third output end to a fourth control module and connecting a fourth output end to a third control module within the first display duration of the time period so that the third output end outputs a fourth voltage signal and the fourth output end outputs a third voltage signal, and connecting the third output end to the third control module and connecting the fourth output end to the fourth control module within the second display duration of the time period so that the third output end outputs the third voltage signal and the fourth output end outputs the fourth voltage signal, the first display duration and the second display duration alternating within the time period.

One embodiment of the present disclosure provides a display device including the above-mentioned source driver IC.

According to the source driver IC, the method for driving the display panel and the display device of the present disclosure, the first sub-driver circuit is provided to, within the time period, control the polarities of the driving voltages for the first subpixels and the third subpixels in the pixel units at the odd-numbered positions in the pixel row to be reverse to the polarities of the driving voltages for the second subpixels and the fourth subpixels in the pixel units at the odd-numbered positions in the pixel row, and the second sub-driver circuit is provided to, within the time period, control the polarities of the driving voltages for the first subpixels and the third subpixels in the pixel units at the even-numbered positions to be identical to the polarities of the driving voltages for the second subpixels and the fourth subpixels in the pixel units at the odd-numbered positions but reverse to the polarities of the driving voltages for the second subpixels and the fourth subpixels in the pixel units at the even-numbered positions. As a result, the occurrence of crosstalk at the display panel may be prevented, thereby to ensure the image quality.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In order to make the objects, the technical solutions and the advantages of embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described hereinafter in a clear and complete manner in conjunction with the drawings. Obviously, the following embodiments merely relate to a part of, rather than all of, the embodiments of the present disclosure, and based on them, a person skilled in the art can obtain other embodiments, which also fall within the scope of the present disclosure.

One embodiment of the present disclosure provides a source driver circuit connected to a display panel. The display panel may include a plurality of pixel units, each of which includes a first subpixel, a second subpixel, a third subpixel and a fourth subpixel arranged sequentially in a horizontal direction.

As shown inFIG. 4, the source driver circuit provided in one embodiment of the present disclosure may include:

a first sub-driver circuit1connected to pixel electrodes corresponding to pixel units at odd-numbered positions in each pixel row of the display panel and configured to, within a time period, transmit voltage signals at corresponding potentials to the pixel electrodes corresponding to the pixel units at the odd-numbered positions, so as to control, within the time period, polarities of driving voltages for the first subpixel and the third subpixel in the pixel units at the odd-numbered positions to be reverse to polarities of driving voltages for the second subpixel and the fourth subpixel in the pixel units at the odd-numbered positions; and

a second sub-driver circuit2connected to pixel electrodes corresponding to pixel units at even-numbered positions in each pixel row of the display panel and configured to, within the time period, transmit voltage signals at corresponding potentials to the pixel electrodes corresponding to the pixel units at the even-numbered positions, so as to control polarities of driving voltages for the first subpixel and the third subpixel in the pixel units at the even-numbered positions to be identical to the polarities of the driving voltages for the second subpixel and the fourth subpixel in the pixel units at the odd-numbered positions, and control, within the time period, polarities of driving voltages for the second subpixel and the fourth subpixel in the pixel units at the even-numbered positions to be identical to the polarities of the driving voltages for the first subpixel and the third subpixel in the pixel units at the odd-numbered positions.

According to the source driver circuit of this embodiment, in the four-primary-color display panel, the polarities of the driving voltages for the subpixels at the same positions in the adjacent pixel units are controlled to be reverse to each other within a display duration. As a result, the occurrence of crosstalk may be prevented when an image is displayed at the display panel, thereby ensuring the image quality.

For example, as shown inFIG. 5, the source driver circuit of this embodiment may enable the polarities of the driving voltages for the subpixels at the same positions in the adjacent pixel units to be reverse to each other. As shown inFIG. 5, the polarities of the driving voltages for the subpixels at positions R1, R2, R3and R4may be positive, negative, positive and negative, respectively, so that the polarities of the driving voltages for the subpixels for displaying a red color in the adjacent pixel units are different from each other, and as a result, so as to prevent the occurrence of crosstalk.

InFIG. 5, Rn may represent a position of the subpixel for displaying a red color in an nthpixel unit in a pixel row, and similarly, Gn, Bn and Wn may represent positions of the subpixels for displaying green, blue and white colors, respectively.

In an optional embodiment, as shown inFIG. 6, the first sub-driver circuit1specifically includes:

a first control module11configured to generate a first voltage signal V1at a first potential based on a logic digital signal.

The first control module11may specifically be connected to a logic digital signal generation unit3, a first analog voltage input end and a second analog voltage input end. The logic digital signal generation unit3may be configured to generate the corresponding logic digital signals including display-related information such as display grayscale information. The first analog voltage input end and the second analog voltage input end may be configured to input corresponding analog voltage signals (AVDD), so that the first control module11generates the first voltage signal V1.

In this embodiment, the first analog voltage input end may input an analog voltage signal at the greatest potential, the second analog voltage input end may input an analog voltage signal at a potential half the greatest potential, and a third analog voltage input end may input an analog voltage signal, e.g., at 0V.

The first voltage signal V1generated by the first control module11may be at a high level, i.e., a positive voltage signal. In other words, the potential of the first voltage signal V1may be greater than a potential of a common electrode (Vcom) in the display panel, so that the driving voltage for the subpixel that receives the first voltage signal is positive.

The logic digital signal generation unit3in this embodiment may be a device of an existing source driver IC.

As shown inFIG. 6, the first sub-driver circuit1may further include:

a second control module12configured to generate a second voltage signal V2at a second potential based on the logic digital signal generated by the logic digital signal generation unit3.

The second control module12may be connected to the logic digital signal generation unit3, the second analog voltage input end and the third analog voltage input end. The second analog voltage input end and the third analog voltage input end may be used to input the corresponding analog voltage signals, so that the second control module12generates the second voltage signal V2.

The second voltage signal V2generated by the second control module12may be at a low level, i.e., a negative voltage signal. In other words, the potential of the second voltage signal V2may be less than the potential of the common electrode in the display panel, so that the driving voltage for the subpixel that receives the second voltage signal V2is negative.

As shown inFIG. 6, the first sub-driver circuit1may further include:

a first output end (OUT1)13configured to transmit the first voltage signal V1or the second voltage signal V2to the pixel electrodes (not shown inFIG. 6) corresponding to the first subpixel (e.g., the subpixels at positions R1and R3inFIG. 5) and the third subpixel (e.g., the subpixels at positions B1and B3inFIG. 5) in the pixel units at the odd-numbered positions, and connected to the pixel electrodes corresponding to the first subpixel and the third subpixel in the pixel units at the odd-numbered positions; and

a second output end (OUT2)14configured to transmit the second voltage signal V2or the first voltage signal V1to the pixel electrodes corresponding to the second subpixel (e.g., the subpixels at positions G1and G3inFIG. 5) and the fourth subpixel (e.g., the subpixels at positions W1and W3inFIG. 5) in the pixel units at the odd-numbered positions, and connected to the pixel electrodes corresponding to the second subpixel and the fourth subpixel in the pixel units at the odd-numbered positions.

As shown inFIG. 6, the first sub-driver circuit1may further include:

a first selection switch (SW1)15configured to, based on a control logic, connect the first output end13to the first control module11and connect the second output end14to the second control module12within a first display duration of the time period so that the first output end13outputs the first voltage signal V1and the second output end14outputs the second voltage signal VG2, and connect the first output end13to the second control module12and connect the second output end14to the first control module11within a second display duration of the time period so that the first output end13outputs the second voltage signal V2and the second output end14outputs the first voltage signal V1, the first selection switch15being connected to the first control module11, the second control module12, the first output end13and the second output end14.

In this embodiment, as shown inFIG. 7, the first display duration and the second display duration each may be a duration desired for displaying a frame, and within the time period (i.e., a display period), the first display duration and the second display duration alternate.

In other words, in this embodiment, the first selection switch15may be used to, with the first display duration or the second display duration as a switching period (e.g., the time desired for displaying a frame), enable the first output end13to be connected to the first control module11and the second control module12alternately and meanwhile enable the second output end14to be connected to the second control module12and the first control module11alternately within the time period, so as to enable the first output end13and the second output end14to output different driving signals for the pixel electrodes synchronously. As a result, in one pixel row, the polarities of the driving voltages for the first subpixel and the third subpixel in the pixel units at the odd-numbered positions are controlled to be reverse to the polarities of the driving voltages for the second subpixel and the fourth subpixels in the pixel units at the odd-numbered positions, thereby to prevent the occurrence of crosstalk.

For example, within the first display duration, the first selection switch15enables the first signal output end13to be connected to the first control module11and enables the second signal output end14to be connected to the second control module12, so that the first signal output end13outputs the first voltage signal V1(the positive voltage signal) and the second signal output end14outputs the second voltage signal V2(the negative voltage signal). Within the second display duration, the first selection switch15enables the first signal output end13to be connected to the second control module12and enables the second signal output end14to be connected to the first control module11, so that the first signal output end13outputs the second voltage signal V2(the negative voltage signal) and the second signal output end14outputs the first voltage signal V1(the positive voltage signal).

In one embodiment, as shown inFIG. 8, the first control module11may specifically include:

a first level shifter111configured to select from the logic digital signals a first digital voltage signal corresponding to the first voltage signal V1, and connected to the logic digital signal generation unit3;

a first digital-to-analog converter (DAC)112configured to convert the first digital voltage signal into a corresponding first analog voltage signal, and connected to the first level shifter111, the first analog voltage input end and the second analog voltage input end; and

a first amplifier (AMP)113configured to amplify the first analog voltage signal, and connected to the first digital-to-analog converter112and the first selection switch15.

In one embodiment of the present disclosure, the first level shifter111, the first digital-to-analog converter112and the first amplifier113each may use any known device in the related art, which is not particularly defined herein.

As shown inFIG. 9, in one embodiment of the present disclosure, the second control module12may include:

a second level shifter121configured to select from the logic digital signals a second digital voltage signal corresponding to the second voltage signal V2, and connected to the logic digital signal generation unit3;

a second digital-to-analog converter122configured to convert the second digital voltage signal into a corresponding second analog voltage signal, and connected to the second level shifter121, the second analog voltage input end and the third analog voltage input end; and

a second amplifier123configured to amplify the second analog voltage signal, and connected to the second digital-to-analog converter122and the first selection switch15.

In an optional embodiment, as shown inFIG. 10, the second sub-driver circuit2may include:

a third control module21configured to generate a third voltage signal V3at a third potential based on an input logic digital signal.

The third control module21may be connected to the logic digital signal generation unit3, the first analog voltage input end and the second analog voltage input end.

The third voltage signal V3generated by the third control module21may be at a high level, i.e., a positive voltage signal. In other words, the potential of the third voltage signal V3may be greater than the potential of the common electrode in the display panel, so that the driving voltage for the subpixel that receives the third voltage signal is positive.

As shown inFIG. 10, the second sub-driver circuit2may further include:

a fourth control module22configured to generate a fourth voltage signal V4at a fourth potential based on the logic digital signal.

The fourth control module22may be connected to the logic digital signal generation unit3, the second analog voltage input end and the third analog voltage input end.

The fourth voltage signal V4generated by the fourth control module22may be at a low level, i.e., a negative voltage signal. In other words, the potential of the fourth voltage signal V4may be less than the potential of the common electrode in the display panel, so that the driving voltage for the subpixel that receives the fourth voltage signal V4is negative.

As shown inFIG. 10, the second sub-driver circuit2may further include:

a third output end (OUT3)23configured to transmit the fourth voltage signal V4or the third voltage signal V3to the pixel electrodes corresponding to the second subpixel (e.g., the subpixels at positions G2and G4inFIG. 5) and the fourth subpixel (e.g., the subpixels at positions W2and W4inFIG. 5) in the pixel units at the even-numbered positions, and connected to the pixel electrodes corresponding to the second subpixel and the fourth subpixel in the pixel units at the even-numbered positions; and

a fourth output end (OUT4)24configured to transmit the third voltage signal V3or the fourth voltage signal V4to the pixel electrodes corresponding to the first subpixel (e.g., the subpixels at positions R2and R4inFIG. 5) and the third subpixel (e.g., the subpixels at positions B2and B4inFIG. 5) in the pixel units at the even-numbered positions, and connected to the pixel electrodes corresponding to the first subpixel and the third subpixel in the pixel units at the even-numbered positions.

As shown inFIG. 10, the second sub-driver circuit2may further include:

a second selection switch25configured to, based on the control logic, connect the third output end23to the fourth control module22and connect the fourth output end24to the third control module21within the first display duration so that the third output end23outputs the fourth voltage signal V4and the fourth output end24outputs the third voltage signal V3, and connect the third output end23to the third control module21and connect the fourth output end24to the fourth control module22within the second display duration so that the third output end23outputs the third voltage signal V3and the fourth output end24outputs the fourth voltage signal V4, the second selection switch25being connected to the third control module21, the fourth control module22, the third output end23and the fourth output end24.

In this embodiment, the second selection switch25may be used to, with the first display duration or the second display duration as a switching period (e.g., the time desired for displaying a frame), enable the third output end23and the fourth output end24to be alternately connected to the third control module21and the fourth control module22, respectively, within the display period, so as to enable the third output end23and the fourth output end24to output different driving signals for the pixel electrodes synchronously. As a result, in one pixel row, the polarities of the driving voltages for the first subpixel and the third subpixel in the pixel units at the even-numbered positions are controlled to be reverse to the polarities of the driving voltages for the second subpixel and the fourth subpixels in the pixel units at the even-numbered positions (but identical to the polarities of the driving voltages for the second subpixel and the fourth subpixel in the pixel units at the odd-numbered positions), thereby to prevent the occurrence of crosstalk.

For example, within the first display duration, the second selection switch25enables the third signal output end23to be connected to the fourth control module22, and enables the fourth signal output end24to be connected to the third control module21, so that the third signal output end23outputs the fourth voltage signal V4(the negative voltage signal) and the fourth signal output end24outputs the third voltage signal V3(the positive voltage signal). Within the second display duration, the second selection switch25enables the third signal output end23to be connected to the third control module21and enables the fourth signal output end24to be connected to the fourth control module22, so that the third signal output end23outputs the third voltage signal V3(the positive voltage signal) and the fourth signal output end24outputs the fourth voltage signal V4(the negative voltage signal).

As shown inFIG. 10, in one embodiment, the third control module21may include:

a third level shifter211configured to select from the logic digital signals a third digital voltage signal corresponding to the third voltage signal V3, and connected to the logic digital signal generation unit3;

a third digital-to-analog converter212configured to convert the third digital voltage signal into a corresponding third analog voltage signal, and connected to the third level shifter211, the first analog voltage input end and the second analog voltage input end; and

a third amplifier213configured to amplify the third analog voltage signal, and connected to the third digital-to-analog converter212and the second selection switch25.

As shown inFIG. 10, in one embodiment, the fourth control module22may include:

a fourth level shifter221configured to select from the logic digital signals a fourth digital voltage signal corresponding to the fourth voltage signal V4, and connected to the logic digital signal generation unit3;

a fourth digital-to-analog converter222configured to convert the fourth digital voltage signal into a corresponding fourth analog voltage signal, and connected to the fourth level shifter221, the second analog voltage input end and the third analog voltage input end; and

a fourth amplifier223configured to amplify the fourth analog voltage signal, and connected to the fourth digital-to-analog converter22and the second selection switch25.

In the above embodiments, the present disclosure is described by taking the source driver circuit merely provided with a set of driving ICs (i.e., the first sub-driver circuit1and the second sub-driver circuit2) so as to control the polarities of the driving voltages for the pixel units at the odd-numbered positions and the even-numbered positions in the pixel row as an example. However, in other embodiments, the source driver circuit may also be provided with two or more sets of driver ICs connected to the corresponding pixel units, so as to control the polarities of the driving voltages for the subpixels at the corresponding positions in the pixel units to be different from each other, thereby to achieve the purpose of the present disclosure.

One embodiment of the present disclosure further provides a method for driving a display panel. The display panel includes a plurality of pixel units, each of which includes a first subpixel, a second subpixel, a third subpixel and a fourth subpixel arranged sequentially in a horizontal direction.

The method includes the steps of:

within a time period, transmitting voltage signals at corresponding potentials to pixel electrodes corresponding to the pixel units at odd-numbered positions in each pixel row, so as to control, within the time period, polarities of driving voltages for the first subpixel and the third subpixel in the pixel units at the odd-numbered positions to be reverse to polarities of driving voltages for the second subpixel and the fourth subpixel in the pixel units at the odd-numbered positions; and

within the time period, transmit voltage signals at corresponding potentials to the pixel electrodes corresponding to the pixel units at even-numbered positions, so as to control, within the time period, polarities of driving voltages for the first subpixel and the third subpixel in the pixel units at the even-numbered positions to be identical to the polarities of the driving voltages for the second subpixel and the fourth subpixel in the pixel units at the odd-numbered positions, and control, within the time period, polarities of driving voltages for the second subpixel and the fourth subpixel in the pixel units at the even-numbered positions to be identical to the polarities of the driving voltages for the first subpixel and the third subpixel in the pixel units at the odd-numbered positions.

In an optional embodiment, the step of, within a time period, transmitting voltage signals at corresponding potentials to pixel electrodes corresponding to the pixel units at odd-numbered positions in each pixel row, so as to control, within the time period, polarities of driving voltages for the first subpixel and the third subpixel in the pixel units at the odd-numbered positions to be reverse to polarities of driving voltages for the second subpixel and the fourth subpixel in the pixel units at the odd-numbered positions specifically includes:

generating the first voltage signal V1at a first potential greater than a potential of the common electrode in the display panel and the second voltage signal V2at a second potential less than the potential of the common electrode in the display panel based on a logic digital signal; and

based on a control logic, connecting the first output end13to the first control module11and connecting the second output end14to the second control module12within a first display duration of the time period so that the first output end13outputs the first voltage signal V1and the second output end14outputs the second voltage signal V2, and connecting the first output end13to the second control module12and connecting the second output end14to the first control module11within a second display duration of the time period so that the first output end13outputs the second voltage signal V2and the second output end14outputs the first voltage signal V1, the first display duration and the second display duration alternating within the time period.

In an optional embodiment, the step of, within the time period, transmit voltage signals at corresponding potentials to the pixel electrodes corresponding to the pixel units at even-numbered positions, so as to control, within the time period, polarities of driving voltages for the first subpixel and the third subpixel in the pixel units at the even-numbered positions to be identical to the polarities of the driving voltages for the second subpixel and the fourth subpixel in the pixel units at the odd-numbered positions, and control, within the time period, polarities of driving voltages for the second subpixel and the fourth subpixel in the pixel units at the even-numbered positions to be identical to the polarities of the driving voltages for the first subpixel and the third subpixel in the pixel units at the odd-numbered positions specifically includes:

based on the logic digital signal, generating the third voltage signal V3having a third potential greater than the potential of the common electrode in the display panel and the fourth voltage signal V4at a fourth potential less than the potential of the common electrode in the display panel; and

based on the control logic, connecting the third output end23to the fourth control module22and connecting the fourth output end24to the third control module21within the first display duration of the time period so that the third output end23outputs the fourth voltage signal V4and the fourth output end24outputs the third voltage signal V3, and connecting the third output end23to the third control module21and connecting the fourth output end24to the fourth control module22within the second display duration of the time period so that the third output end23outputs the third voltage signal V3and the fourth output end24outputs the fourth voltage signal V4.

One embodiment of the present disclosure further provides a display device including the above-mentioned source driver IC.

The display device may be any electronic product having a display function.

According to the present disclosure, the first sub-driver circuit is provided to, within the time period, control the polarities of the driving voltages for the first subpixel and the third subpixel in the pixel units at the odd-numbered positions in the pixel row to be reverse to the polarities of the driving voltages for the second subpixel and the fourth subpixel in the pixel units at the odd-numbered positions in the pixel row, and the second sub-driver circuit is provided to, within the time period, control the polarities of the driving voltages for the first subpixel and the third subpixel in the pixel units at the even-numbered positions to be identical to the polarities of the driving voltages for the second subpixel and the fourth subpixel in the pixel units at the odd-numbered positions but reverse to the polarities of the driving voltages for the second subpixel and the fourth subpixel in the pixel units at the even-numbered positions. As a result, the occurrence of crosstalk at the display panel may be prevented, thereby to ensure the image quality.

The above are merely the optional embodiments of the present disclosure. It should be appreciated that, a person skilled in the art may make further improvements and modifications without departing from the principle of the present disclosure, and these improvements and modifications shall also fall within the scope of the present disclosure.