Reconfigurable storage controller, storage device, and method of operating storage device

A storage controller includes a host interface which real-time analyzes a command received from a host, a programmable logic unit which loads an optimal image adaptively selected from a plurality of images in response to at least one of a current operating state of the storage controller and the command, and a processor which performs an operation on a nonvolatile memory device using the programmable logic unit after the optimal image is loaded.

This application claims the benefit of Korean Patent Application No. 10-2019-0126908 filed on Oct. 14, 2019 in the Korean Intellectual Property Office, the subject matter of which is hereby incorporated by reference.

BACKGROUND

The inventive concept relates generally to storage controllers, storage devices, methods of operating a storage controller, and methods of operating a storage device.

2. Description of the Related Art

Various storage devices may be used to store and retrieve data under the control of a host device. There are many different types of host devices, such as computers, smartphones, smart pads, etc. There are also many different types of storage devices, such as hard disk drives (HDDs), solid state drives (SSDs), memory cards, etc. However, most contemporary storage devices use one or more semiconductor memories, particularly including nonvolatile memories. Nonvolatile memories include read-only memories (ROMs), programmable ROMs (PROMs), erasable PROMs (EPROMs), electrically erasable PROMs (EEPROMs), flash memories, phase-change random access memories (PRAMs), magnetic RAMs (MRAMs), resistive RAMs (RRAMs), and ferroelectric RAMs (FRAMs).

The development of improved semiconductor fabrication technologies has allowed notable increases in the speed with which any host devices are able to communicate information with storage devices. Such information includes increasingly voluminous content data. The requirements to receive and write (and/or read and provide) such large volumes of information at high speed place serious demands on storage devices. Accordingly, storage devices may be efficiently capable of reconfiguration to ensure appropriate use of hardware resources.

SUMMARY

Aspects of the inventive concept relate to more efficiently using internal resources of a storage device in response to an optimal image loaded into a programmable logic unit. The programmable logic unit may be adaptively reconfigured in response to a command, without interference by a host.

However, aspects of the inventive concept are not restricted to those specifically set forth herein. The above and other aspects of the present disclosure will become more apparent to one of ordinary skill in the art upon consideration of the subject disclosure together with the accompanying drawings.

In one aspect, the inventive concept provides a storage controller including a host interface which real-time analyzes a command received from a host, a programmable logic unit which loads an optimal image adaptively selected from a plurality of images in response to at least one of a current operating state of the storage controller and the command, and a processor which performs an operation on a nonvolatile memory device using the programmable logic unit after the optimal image is loaded.

In another aspect, the inventive concept provides a method of operating a storage device including a storage controller and a nonvolatile memory device. The method includes; real-time analyzing a command received from a host, determining whether or not a current operating state of the storage device is suitable for performing the command, if the current operating state of the storage device is suitable for performing the command, operating the storage device using the current operating state, else changing the operating state of the storage device, and generating a result output and communicating the result output to the host.

In another aspect, the inventive concept provides a storage device including; a nonvolatile memory device and a storage controller which receives a command from a host. The storage controller includes an internal memory, a programmable logic unit, a processor configured to control operation of the storage device and access the internal memory, and a nonvolatile memory device (NVM) controller configured to control operation of the nonvolatile memory device, wherein the storage controller is configured to select an optimal image from a plurality of images in response to an analyzing of a pattern of the command, and load the optimal image into the programmable logic unit, and the processor is further configured to control operation of the storage device in response to the optimal image.

DETAILED DESCRIPTION

Certain embodiments of a storage controller, a storage device, as well as methods of operating a storage device according to embodiments of the inventive concept will be described in some additional detail with reference toFIGS. 1 through 9, inclusive.

FIG. 1is a block diagram illustrating a storage system according to an embodiment of the inventive concept.FIG. 2is a block diagram further illustrating in one example a storage controller100ofFIG. 1.

The storage system illustrated inFIGS. 1 and 2generally includes a host10and a storage device20, which are mutually capable of transmitting and/or receiving (hereafter, generically “communicating”) various command(s), addresses(es) and/or data using one or more interfaces. For example, the host10may communicate a command and associated data to the storage device20requesting that the storage device20perform a data access operation, such as a read operation, a write operation, or an erase operation. Alternately, the host10may request that the storage device20perform another type of operation, such as a housekeeping operation, among possibly many other types of operations.

Here, the host10may be a central processing unit (CPU), a processor, a microprocessor, an application processor (AP), etc. In certain embodiments of the inventive concept, the host10may be implemented as a system-on-chip (SoC).

Information may be communicated between the host10and the storage device using one or more interface(s), such as the advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI-express (PCI-E), IEEE 1394, universal serial bus (USB), secure digital (SD) card, multimedia card (MMC), embedded multimedia card (eMMC), and compact flash (CF) card interfaces.

The storage system may be, as examples, a solid state drive (SSD), an eMMC, a universal flash storage (UFS), a compact flash (CF), a secure digital (SD), a micro-SD, a mini-SD, an extreme digital (xD), a memory stick, etc.

With the foregoing configuration, the host10may be used to control the performing (or execution) of various operations by the storage device20through the one or more interface(s).

As illustrated inFIG. 1, the storage device20may include the storage controller100and a nonvolatile memory devices200. In some embodiments, each of the nonvolatile memory devices200may include a flash memory or a resistive memory such as a resistive random access memory (ReRAM), a phase-change RAM (PRAM) or a magnetic RAM (MRAM). Alternatively, each of the nonvolatile memory devices200may include an integrated circuit including a processor and a RAM, for example, may include a storage device or a processing in memory (PIM).

In some embodiments, a flash memory included in each of the nonvolatile memory devices200may be a two-dimensional (2D) or three-dimensional (3D) memory array. In the 3D memory array memory devices, an active region is disposed on a silicon substrate and circuits related to the operation of memory cells are formed on the substrate or in the substrate and the 3D memory array are monolithically formed at least one physical level. The term “monolithic” denotes that a layer at each level of an array are directly stacked on a layer at each lower level of the array. The 3D memory array includes vertical NAND strings which are vertically oriented such that at least one memory cell is located over other memory cells. The at least one memory cell may include a charge trap layer.

The storage controller100may be used to control the execution of an operation by each of the nonvolatile memory devices200. In some embodiments, the storage controller100may be connected to each of the nonvolatile memory devices200through at least one channel in order to directly communicate information (e.g., data). According to embodiments, the storage controller100may be an element included in a storage device such as an SSD or a memory card.

Referring toFIG. 2, the storage controller100may include a host interface110, a programmable logic unit120, a processor130, a memory controller140, a RAM150, and a nonvolatile memory (NVM) controller160.

The host10may provide one or more commands CMD and associated address(es) and data to control the execution of various data access operations, as well as memory management operations, etc.

The host interface110may be configured to provide at least one communication connection between the host10and the storage device20, such that various command(s), address(es) and/or data may be communicated to execute a desired operation.

Consistent with the example illustrated inFIG. 2, certain embodiments of the inventive concept may use the host interface110of the storage controller100to real-time analyze a command received from the host10. In this context, the term “real-time analyze” means the host interface110will process a received command as soon as received from the host10without materially delaying the processing or storing the command prior to processing.

Additionally or alternately, the host interface110may be used to real-time communicate an operating state of the storage device20to the host10. Here, the term “real-time communicate” means the host interface110will communicate the operating state of the storage device without necessarily storing the operating state information or waiting for a specific request from the host10.

Alternately or additionally, the host interface110may be used to analyze a pattern of command(s) received from the host10. For example, an analyzed pattern of command(s) may denote change(s) in the use, request, execution and/or sequence of one or more command(s) in response to change(s) in the operating state of the storage device20.

In some embodiments, the programmable logic unit120may be embedded-field programmable gate arrays (eFPGAs). Thus, the programmable logic unit120may include a configurable logic block (CLB), an input output block (IOB), and a configurable connection circuit which connects the CLB and the IOB. Here, the programmable logic unit120may be used to perform an operation in response to a loaded image T. In certain embodiments of the inventive concept, the programmable logic unit120may be a programmable logic device (PLD), such as those widely used to design digital circuits that perform a specific operation according to an image. The term “image”, as used herein, denotes a hardware/software image of a specific operation performed by the programmable logic unit120and may be referred to as a bit stream, a kernel, or a lookup table according to various embodiments.

The storage device20may be used to store a plurality of images. Each of the images may be a program for each of the various situations in which the storage device20operates based on the operating state of the storage device20or a command received from the host10.

In the example illustrated inFIG. 1, the processor130may be used to control the overall operation of the storage controller100. That is, the processor130may control the execution of data access operations by the nonvolatile memory devices200, the communication of information related to the execution of the data access operations (e.g., information communicated between storage controller100and the host10, and the operation of the storage controller100itself. In this regard, the processor130may control the operation of the host interface110, the programmable logic unit120, the memory controller140, the RAM105, and/or the NVM controller160.

Thus, the processor130may perform a control operation associated with the operation of the programmable logic unit120. According to embodiments, the processor130may dynamically manage power applied to the storage controller100in response to the operation of the programmable logic unit120in order to effectively dynamically manage associated with the operation of the nonvolatile memory devices200.

In certain embodiments of the inventive concept like the one illustrated inFIG. 2, the memory controller140may be connected to a memory300, and the storage controller100may temporarily store data received from the host10in the memory300, provide the stored data to the nonvolatile memory devices200, and/or provide data read from the nonvolatile memory devices200to the host10.

According to embodiments, the memory300may be a buffer memory. According to embodiments, the memory300may include a cache, a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically erasable PROM (EEPROM), a PRAM, a flash memory, a static random access memory (RAM) (SRAM), or a dynamic RAM (DRAM). The memory300may be integrated into the storage controller100as an internal memory or may exist outside the storage controller100according to embodiments. The memory300may store preset information, programs, or commands related to the operation or state of the storage controller100.

The RAM150may be used as an internal working memory and may be implemented as various memories. According to embodiments, the RAM150may be a volatile memory or a nonvolatile memory. For example, the RAM150may be implemented as at least one of a cache, a DRAM, an SRAM, a PRAM, an MRAM, an RRAM, and a flash memory device.

The NVM controller160may access each of the nonvolatile memory devices200and control the operation of each of the nonvolatile memory devices200.

According to certain embodiments, the NVM controller160may include an advanced encryption standard (AES) module. Each of the nonvolatile memory devices200may store AES-encoded data as security data. The processor130may compare AES-decoded data with predetermined data and determines whether AES decoding has been successful based on the comparison result. Each of the nonvolatile memory devices200may store information about whether security decoding (AES decoding) has been performed successfully in a register (not illustrated) as result data of the security decoding.

Alternately or additionally, the NVM controller160may include a randomization circuit RND for removing pattern dependency of data. The randomization circuit may provide randomized data by performing randomization using seed values corresponding to a target page during a write operation. In addition, the randomization circuit may provide de-randomized data by performing de-randomization using seed values corresponding to a source page during a read operation.

Alternately or additionally, the NVM controller160may include an error correction code (ECC) engine. The ECC engine may perform error bit correction and include an ECC encoder and an ECC decoder. The ECC engine may perform error bit correction in data units of an ECC sector.

Each of the nonvolatile memory devices200may include a memory cell array, a row select circuit, a page buffer circuit, a column select circuit, a data processor, an input/output interface, and control logic. Here, the memory cell array may include a plurality of memory cells connected to a plurality of word lines WL and a plurality of bit lines BL, respectively. The memory cells may be NAND or NOR flash memory cells according to embodiments and may be arranged in a 2D array structure or a 3D vertical array structure according to embodiments. According to embodiments, the memory cells may be various types of resistive memory cells.

According to embodiments, each of the memory cells may be a single level memory cell (SLC) which stores one data bit or a multi-level memory cell (MLC) which stores a plurality of data bits.

FIG. 3is a flowchart illustrating a method of operating a storage controller according to embodiments of the inventive concept.

Referring toFIGS. 2 and 3, the storage controller100receives a command from the host10(S10), and analyzes it to identify the command (S11). The storage controller100may be used to monitor in real-time, a current operating state of the storage device20(S12).

If the current operating state of the storage device20is suitable for performing the received command (S12=YES)—that is, is the current operating state is characterized by a resource distribution appropriate to the execution of the received command—the storage controller100will maintain the current operating state (S14) (e.g., continue with (or operating on) the current operating state).

However, if the current operating state of the storage device20is not suitable for performing the received command (S12=NO), the storage controller100will set about changing the operating state to one more suitable (e.g., perform the method steps S13, S14and S15described hereafter, as one example). This changing of the operating state may be understood in certain aspects as a redistribution of internal hardware resources within the storage controller100and/or the nonvolatile memory devices200.

For example, the storage controller100may adaptively select a more “optimal” (e.g., best adapted) image from the plurality of images stored in the storage device20. In this regard, the selection of the optimal image may be based on the current operating state of the storage device20and/or the command received from the host10. According to various embodiments, at least one of the plurality of images may be stored in at least one of the RAM150, the buffer memory300, and/or nonvolatile memory devices200of the storage controller100.

In certain embodiments of the inventive concept, the storage controller100may select the optimal image corresponding to a resource input state most efficient (or appropriate) for the performing of the received command from the plurality of stored images. Once selected, the optimal image may be loaded into the programmable logic unit120. Here, the selecting and loading of the optimal image may involve using the host interface110, the programmable logic unit120, and/or the processor130.

Returning toFIG. 3, the programmable logic unit120may load the optimal image to better control the operating state of the storage controller100. That is, in certain embodiments, the programmable logic unit120may be used to dynamically manage power consumption by reconfiguring hardware resources of the storage controller100in accordance with (or in response to) the optimal image (S15), and in certain embodiments, the programmable logic unit120may dynamically manage power independently for each one of a plurality of hardware modules included in the storage device20. In this regard, in certain embodiments, the terms “independently” or “independent” mean without further intervention by the host10after communicating the command.

The storage controller100may communicate a result output indicating (or characterizing) its operating state following execution of an operation in accordance with the optimal image to the host10(S16). And in response, the host10may prepare a next operation in accordance with the result output.

FIG. 4is another flowchart illustrating a method of operating a storage controller according to embodiments of the inventive concept.

That is, if the current operating state of the storage device20is suitable for performing the received command (S22=YES)—that is, is the current operating state is characterized by a resource distribution appropriate to the execution of the received command—the storage controller100will maintain the current operating state (S24) (e.g., continue with (or operating on) the current operating state).

However, if the current operating state of the storage device20is not suitable for performing the received command (S22=NO), the storage controller100will set about changing the operating state to one more suitable (e.g., perform the method steps S23, S24and S25described hereafter, as one example). This changing of the operating state may be understood in certain aspects as a redistribution of internal hardware resources within the storage controller100and/or the nonvolatile memory devise200.

For example, an optimal software-related (SW) image may be uploaded from the processor130to the eFPGA120(S23), and the storage controller100may be operated based on the loaded optimal image (S24) to reconfigure the processor130(S26) and generate a corresponding result output (S27).

As before, the storage controller100may adaptively select an optimal image from the plurality of stored images in response to the current operating state of the storage device20and/or the command received from the host10. That is, the processor130may be sued to select the optimal image (e.g., an image corresponding to a resource input state most efficient to performing the received command from among the plurality of stored images) and load the selected optimal image into the programmable logic unit120.

Once loaded (or updated) with the optimal image, the programmable logic unit120may be used to control the operation of the storage controller100in response to the optimal image (S25). Thus, in certain embodiments of the inventive concept, the programmable logic unit120may be used to dynamically manage power by reconfiguring resources of the processor130according to the optimal image (S26). For example, the loaded programmable logic unit120may be used to adjust (i.e., increase or decrease) the operating frequency of one or more components (e.g., clocks) within the processor130in response to command received from the host10.

Then, the host interface110may be used to communicate the output result associated with operation in response to the optimal image to the host10(S27).

As described above, since the storage controller100may be used to control the operation of the processor130by adaptively changing an image according to the operating state of the storage device20and/or the received command, the processor130may be operated with optimal use of its constituent resource.

FIG. 5is another flowchart illustrating a method of operating a storage controller according to embodiments of the inventive concept.

Here, however, an optimal hardware-related (HW) image may be uploaded from one or more of the nonvolatile memory devices200to the eFPGA120(S33). And following operation of the storage controller100in response to the uploaded image (S35), the NVM controller160may be reconfigured to provide a more optimal allocation (or definition) of resources (S36).

Thus, the programmable logic unit120may be used to dynamically control at least one of a power cutoff operation, a power supply voltage adjustment operation, an operating frequency adjustment operation, a randomizing operation, an error correction operation, and a compression operation associated with (or controlled by) the NVM controller160.

In this manner, the programmable logic unit120—after being loaded with an optimal image—may perform a control operation on the NVM controller160using the processor130. According to embodiments, when as errors in the date read from the nonvolatile memory devices200increase, the NVM controller160may be responsively controlled to provide or change an error correction operation. According to embodiments, when the remaining memory capacity of the nonvolatile memory devices200is insufficient, the NVM controller160may be controlled to perform a data compression operation. According to embodiments, when input/output operations per second (IOPS) levels of the nonvolatile memory devices200get worse, the NVM controller160may be controlled to perform a high-performance arithmetic operation. According to embodiments, when any one of the nonvolatile memory devices200is not used for a predetermined period of time, the nonvolatile memory device200may be reduced in operating frequency or may be turned OFF (or alternately, may be turned ON). Alternately or additionally, the level of one or more power supply voltage(s) associated with the nonvolatile memory devices200may be adjusted.

Of note, the host interface110may be used to communicate information following operation in response to the optimal image and provide a corresponding result output to the host10(S37).

In this manner, since the storage controller100is enabled to control the operation of the nonvolatile memory devices200by adaptively changing an image in response to the current operating state of the storage device20and/or a command received from the host10, the nonvolatile memory devices200may be made to operate with optimal resource allocations and/or operating state definitions (e.g., efficient power consumption).

FIGS. 6, 7, 8 and 9are respective block diagrams illustrating in various embodiments the storage controller100according to embodiments of the inventive concept. For clarity of description, only material differences between these respective embodiments and the embodiment described in relation toFIG. 2will be emphasized.

The general description of the nonvolatile memory devices200ofFIG. 2is replaced by a more detailed description inFIG. 6. Here, a plurality of images that may be loaded into the programmable logic unit120may be stored in a particular nonvolatile memory device210(NVM1) from among a plurality of nonvolatile memory devices including nonvolatile memory devices220.

A plurality of nonvolatile memory devices210and220may be connected to (and accessed by) the storage controller100.

According to embodiments, the nonvolatile memory devices210and220may be accessed by separate NVM controllers160or may be accessed by one NVM controller160.

According to embodiments, a plurality of images I may be stored in any one210of the nonvolatile memory devices210and220. An optimal image selected from the images I stored in the nonvolatile memory device210may be accessed by the NVM controller160through a channel CH1and loaded into the programmable logic unit120. Data requested to be read or written by a host10other than images may be accessed in the nonvolatile memory devices220through channels CH2through CHk (where k is a natural number of 3 or more).

According to embodiments, the images I may be stored in at least one nonvolatile memory device210from among the nonvolatile memory devices210and220. The at least one nonvolatile memory device210may be used to store the images I only and may not store other data. The images I stored in the at least one nonvolatile memory device210can only be read through the channel CH1and cannot be written or erased by the host10. In this case, the host10can read, write, and erase data only for the nonvolatile memory devices220connected through the channels CH2through CHk.

According to embodiments, the storage controller100monitors the state of each of the nonvolatile memory devices200(210and220), and the programmable logic unit120controls an access operation to the nonvolatile memory devices200(210and220) according to a selected optimal image when performing a command received from the host10.

InFIG. 7, one or more images that may be loaded into the programmable logic unit120are stored in an internal memory155of the storage controller100. According to embodiments, the internal memory155may include a nonvolatile memory and a volatile memory, and a plurality of images may be stored in the nonvolatile memory NVRAM. According to embodiments, the internal memory155may be a register, an MRAM, a PRAM, or the like.

InFIG. 8, images that may be loaded into the programmable logic unit120include at least a first type image I1and a second type image I2. According to embodiments, the first type image I1and the second type image I2may be distinguished according to data size, operating nature (or classification), a target of a control operation, etc.

The storage controller100may store the first type image I1in the internal memory155as a bit stream having a small volume. In contrast, the storage controller100may store the second type image I2in the nonvolatile memory devices200as a bit stream having a larger volume than a preset data volume.

Alternatively, the storage controller100may store the first type image I1in the internal memory155to control the operation of certain hardware modules (e.g., one or more of the hardware components110,120,130,140and160ofFIG. 2) within the storage controller100. Here, the internal memory155may be a nonvolatile RAM, such as a register, an MRAM, or a PRAM. The second type image I2may be stored in the nonvolatile memory devices200to control the operation of each of the nonvolatile memory devices200, and/or to control the operation of the NVM controller160.

InFIG. 9, images that may be loaded into the programmable logic unit120may be stored in an external memory400associated with the storage controller100. Here, the external memory400is shown directly connected to the programmable logic unit120, but this is just one possible configuration.

The external memory400may be a nonvolatile memory, a buffer memory, or a register according to embodiments. The external memory400may store a plurality of images to be loaded into the programmable logic unit120. The programmable logic unit120may operate by loading any one image from the external memory400.

As described above, a storage controller consistent with embodiments of the inventive concept may be used to efficiently reallocate and/or redefine hardware resources in response to a current operating state of the storage controller in view of a command received from a host. The storage controller may real-time analyze the received command and dynamically manage the operating characteristics (e.g., power consumption) of the storage controller and/or associated storage devices without intervention by the host (i.e., independently).