Storage apparatus, data processing method and storage system wherein compressed data is read in parallel, said data stored in buffer by size and read from said buffer, in order of when said data is stored in said buffer

A management controller controls a data buffer and a flash controller, which controls I/O of data to and from flash memories, based on a search request. A data decompression engine includes a plurality of data decompression circuits for decompressing, in parallel, the compressed data transferred from the data buffer. A data search engine includes a plurality of data search circuits for searching, in parallel, data which satisfies search conditions among the respective data that were decompressed by the data decompression circuits, and transfers, to the search request source, the data obtained in the search performed by the data search circuits, wherein the flash controller reads, in parallel, a plurality of compressed data requested in the search request, and transfers the read compressed data to the data buffer, and the management controller transfers the compressed data to the data decompression engine when the compressed data is stored in the data buffer.

TECHNICAL FIELD

The present invention relates to a storage apparatus, a data processing method and a storage system having a function of storing and searching for data.

BACKGROUND ART

As an apparatus having a function of storing and searching for data, for instance, there is an apparatus including a magnetic storage device which stores target data, and a reconfigurable logical device, wherein, when the reconfigurable logical device receives a search inquiry using a data key and reads the target data from a magnetic storage medium, the match between the target data and the data key is determined (refer to PTL 1). Since this apparatus uses a magnetic storage medium as its storage medium, it is insufficient for speeding up the I/O processing of data.

Meanwhile, in recent years, proposed is a storage apparatus capable of speeding up the I/O processing of data by using a flash memory as the storage device for storing data. When a flash memory is used as the storage medium, a configuration of storing compressed data in the flash memory is adopted in order to store large volumes of data.

CITATION LIST

Patent Literature

SUMMARY OF INVENTION

Technical Problem

When a magnetic storage medium is used as the storage medium, data needs to be read sequentially in order to read data from the magnetic storage medium. Meanwhile, when a flash memory is used as the storage medium, the reading speed of data can be sped up since data can be read from the flash memory in parallel.

When processing data stored in the flash memory as the data to be searched, in order to speed up the reading speed of data, processing is executed for reading data (compressed data) from the flash memory in parallel, temporarily storing the read data (compressed data) in a data buffer (temporary storage device), subsequently decompressing the data (compressed data) retained in the data buffer, and searching for the decompressed data. Here, even if the data (compressed data) is read from the flash memory in parallel, if the data decompression/search processing is not sped up, it is not possible to quickly process the data read from the flash memory, and the processing of reading data from the flash memory becomes a bottleneck.

An object of the present invention is to provide a storage apparatus, a data processing method and a storage system capable of preventing the processing of reading data from flash memories from becoming a bottleneck.

Solution to Problem

In order to achieve the foregoing object, the present invention comprises a plurality of flash memories which store a plurality of compressed data, a flash controller which controls I/O of data to and from the flash memories, a data buffer which temporarily stores the compressed data, a management controller which controls I/O of data to and from the data buffer based on a search request from a search request source, a data decompression engine which includes a plurality of data decompression circuits for decompressing, in parallel, the compressed data transferred from the data buffer, and a data search engine which includes a plurality of data search circuits for searching, in parallel, data which satisfies search conditions requested in the search request among the respective data that were decompressed by each of the data decompression circuits, and transfers, to the search request source, the data obtained in the search performed by each of the data search circuits, wherein the flash controller reads, in parallel, a plurality of compressed data belonging to the search source data from two or more flash memories, and transfers the read compressed data to the data buffer, and the management controller transfers the compressed data to the data decompression engine each time the compressed data belonging to the search source data is stored in the data buffer.

Advantageous Effects of Invention

According to the present invention, it is possible to prevent the processing of reading data from flash memories from becoming a bottleneck.

DESCRIPTION OF EMBODIMENTS

An embodiment of the present invention is now explained with reference to the appended drawings.

FIG. 1is an overall configuration diagram of a storage apparatus equipped with a database assist function. InFIG. 1, a storage apparatus100is arranged on a board (not shown) together with a host CPU (Central Processing Unit)101and a host primary storage device102.

The storage apparatus100is configured from a host interface (host I/F)103, a data DMA (Direct Memory Access) circuit104, a management CPU105, a logical/physical address management table106, a data buffer (DRAM)107, a plurality of flash controllers108, a plurality of flash memories109, a plurality of data decompression circuits110, a plurality of data search circuits111, a search result output buffer/DMA circuit112, a database (DB) page size register113, and a data compression circuit114.

The host CPU101is a host computer comprising a memory, an I/O interface and other information processing resources, and is, for example, a central processing unit on which a database application is run. By issuing, to the storage apparatus100, an access request such as a write request, a read request or a search request designating a logical volume (logical address) provided by the storage apparatus100, the host CPU101can access that logical volume. Here, the host CPU101is configured as an access request source or a search request source, sends and receives information to and from the host primary storage device102, and sends and receives information to and from the storage apparatus100via the host interface103. The host primary storage device102is configured as a primary storage area in which a database application is run.

The host interface103is an interface which connects the storage apparatus100and the host CPU101, and becomes the interface when the host CPU101uses the assist function of the storage apparatus100.

The data DMA circuit104sends and receives information to and from the host interface103, the management CPU105and the data buffer107, and, for example, sends and receives data to and from the host primary storage device102via the host interface103when the host CPU101issues a read request or a write request of data. Here, the data DMA circuit104reads the read data stored in the host primary storage device102, and transfers, to the primary storage device102, the write data read from the data buffer107.

The management CPU105controls the activation of the data DMA circuit104, the respective flash controllers108and the respective data decompression circuits110, and is configured as a management controller which uses the logical/physical address management table106to manage the read/write operation of the respective flash controllers108, and control the I/O of data to and from the data buffer107.

The logical/physical address management table106is a table for managing the relationship of the logical address of the page data of the database managed based on the database application, and the physical address (flash memory block address) which indicates the actual storage area of the page data. The logical/physical address management table106is used upon converting a logical address, which was added to a read request, a write request or a search request, into a physical address when the management CPU105receives a read request, a write request or a search request from the host CPU101.

The data buffer107is configured as a storage area for temporarily storing the compressed data read from the flash memory109and the compressed data to be stored in the flash memory109.

Each flash controller108sends and receives data to and from the data buffer107, and controls the I/O of data to and from each flash memory109.

Each flash memory109is configured as a block write/erase type storage device including a plurality of blocks as the storage area of data. Data is written into each flash memory109in block units and data is erased from each flash memory109in block units. The writing of data into and the erasure of data from each flash memory109are managed by the management CPU105. Furthermore, each block of the flash memory109stores, for each page unit, compressed data which is obtained by compressing data in which the data size before data compression is managed in page units of the database, for example, if the page unit is set to be 8 KB, data which is managed at a capacity of 8 KB or less.

The database page size register113is a register for storing information related to the page size of the database as information which is set by the host CPU101. Note that the database page size register113may also store information, such as a search key, a comparison key or search conditions, to be added to the search request issued from the host CPU101.

The data compression circuit114is used upon writing data into the flash memory109, and data that is temporarily stored in the data buffer107is subject to compression processing, and then written into the flash memory109via the flash controller108. Here, data compression is performed by using the value of the DB page size register113to decide the size of the unit in which the data is to be compressed. As a result of performing compression based on the value of the DB page size register113, the data decompression circuit110can subsequently decompress data in DB page units when reading data.

Each data decompression circuit110retrieves the compressed data from the data buffer107, and decompresses the retrieved compressed data according to the information stored in the database page size register113. In other words, each data decompression circuit110decompresses the compressed data in decompression units corresponding to page units (decompression units=page units), which are the units in which the data was compressed by the data compression circuit114, and transfers the decompressed data to each data search circuit111as the data in page units.

Each data search circuit111searches for data to be searched according to the search conditions stored in the database page size register113with the decompressed data transferred from each data decompression circuit110, and which are data in page units, as the data to be searched, searches for data which satisfies the search conditions among the data in page units, and transfers the search result to the search result output buffer/DMA circuit112. Note that information such as search conditions to be added to the search request (request) issued by the host CPU101may also be retained in a register that is different from the database page size register113.

The search result output buffer/DMA circuit112executes a DMA operation of compiling the search results of each data search circuit111and transferring the compiled contents to the host primary storage device102via the host interface103, and transferring, to the host primary storage device102, the processing result of the database application running on the host CPU101.

The operation of writing data of the database into the flash memory109is foremost explained. Prior to starting the write processing to the storage apparatus100, the host CPU101sets information of the page size of the database, which is managed with the database application, in the database page size register113via the host interface103. When the management CPU105receives a write request from the host CPU101, the management CPU105stores, in the data buffer107, data of the database to be received subsequently. The management CPU105compresses the stored database page data with the data compression circuit114and gives write an instruction to each flash controller108, and the compressed data is written into the flash memory109. Here, the data compression circuit divides data into each page size that is set in the database page size register113, and then compresses and stores the divided data. The compressed and stored data become the data to be decompressed into the page sizes set in the database page size register when they are read.

The search operation using the foregoing compressed data is now explained. Prior to starting the search processing to the storage apparatus100, the host CPU101sets information of the page size of the database, which is managed with the database application, in the database page size register113via the host interface103, and thereafter sends a search request (request) including the logical address, search conditions and the like to the management CPU105via the host interface103and the data DMA circuit104. Here, the host CPU101may also set, in the database page size register113, information to be added to the search request such as a search key, a comparison key, and search conditions.

When the management CPU105receives a search request from the host CPU101, the management CPU105activates each flash controller108and gives an instruction to each flash controller108to read a plurality of compressed data belonging to the search source data which was requested in the search request. Each flash controller108reads, in parallel, the plurality of compressed data belonging to the search source data according to the instruction given by the management CPU105from two or more flash memories among the plurality of flash memories109, transfers the read compressed data to the data buffer107, and sequentially stores the respective compressed data in the data buffer107.

Subsequently, each time the respective compressed data read from the respective blocks of each flash memory109are stored in the data buffer107, the management CPU105sequentially transfers, to one of the data decompression circuits110, the respective compressed data stored in the data buffer107, irrespective of the reading order. Each data decompression circuit110decompresses the compressed data transferred from the data buffer107in decompression units, and sequentially transfers the decompressed data to the data search circuit111as data in page units. Each data search circuit110searches for data to be searched according to the search conditions with the decompressed data transferred from each data decompression circuit110, and which are data in page units, as the data to be searched, and transfers the search result of the data in page units to the search result output buffer/DMA circuit112. The search result output buffer/DMA circuit112compiles the search results of each data search circuit111and transfers the compiled contents to the host primary storage device102via the host interface103.

The size before compression of the compressed data stored in the respective blocks of the flash memory109is the page unit of the database, and because the decompression unit of each data decompression circuit110is set to be a unit corresponding to the page unit of the database, even if the compressed data is read from the data buffer107in random order upon decompressing the respective compressed data belonging to the search source data with each data decompression circuit110, it is possible to execute the decompression processing to the read compressed data in the order that the reading of the compressed data is completed, and process the decompressed data, which are data in page units, as the data to be searched. Thus, it is possible to speed up the decompression processing of the read compressed data even when the respective compressed data belonging to the search source data are read from the data buffer107in random order, as well as cause the data in page units to be the data to be searched even when the decompressed data are to be the data to be searched, and it is thereby possible to speed up the search processing of the data to be searched.

FIG. 2is a configuration diagram of a database page size register. InFIG. 2, the database page size register113is configured as a register for storing a set value201that is set by the host CPU101. The set value201stores, for example, a value of 8 KB when the host CPU101sets 8 KB as the page size of the database, and information indicating the page size of the database, and which is the page unit (information of the decompression unit corresponding to the page unit). Moreover, the database page size register113stores information such as the search conditions included in the search request. Here, the database page size register113configures a first register for storing information which is set by the host CPU101(search request source) and which is information of the decompression unit corresponding to the page unit, and a second register for storing information to be added to the search request from the host CPU101(search request source) and which is information indicating the search conditions requested in the search request.

FIG. 3is an explanatory diagram explaining the configuration of a logical/physical address management table. InFIG. 3, the logical/physical address management table106is configured from a logical address field301and a flash memory block address field302, and stored in a memory (not shown) which is managed by the management CPU105.

The logical address is an address for identifying page data303of the database, and the logical address field301stores information (A1 to A4, . . . ) related to the identifier for identifying the page data303of the database. Note that the page data303is configured, for example, as data in page units at a capacity of 8 KB or less.

The flash memory block address is an address for identifying the blocks (data storage areas)305to308formed in the flash memory109. The flash memory block address field302stores information (B1•1, B2•1, B2•2, B2•3, . . . ) related to the block address for identifying the blocks305to308of the flash memory109.

Meanwhile, the respective blocks305to308of the flash memory109store, for each page unit, the compressed data which were obtained by compressing data in which the data size before data compression is managed in page units. For example, the page data303of the logical address A1 and the page data303of the logical address A2 are respectively stored in the block305of the flash memory109. Moreover, the page data303of the logical address A3 is stored in the block306, and the page data303of the logical address A4 is stored in the block308. In other words, the page data303of the logical address A3 is prohibited from being stored across the block306and the block307, and the page data303of the logical address A4 is prohibited from being stored across the block307and the block308. This is in order to prevent the data management from becoming complicated and causing performance deterioration in the reclamation operation, which is an operation that is unique to the flash memory109. Note that the respective blocks305to308may also store, for each page unit, the compressed data of an integral multiple of the page data303of the database.

FIG. 4is a configuration diagram of a data decompression engine and a data search engine. InFIG. 4, the data decompression engine is configured from a plurality of data decompression circuits110, and the data search engine is configured from a plurality of data search circuits111and a search result output buffer/DMA circuit112.

Each data decompression circuit110comprises a compressed data buffer401for temporarily retaining the compressed data transferred from the data buffer107. The compressed data buffer401can store one or more pages worth of compressed data obtained by compressing the page data303. Thus, even when a plurality of compressed data are read from the data buffer107in parallel, the respective compressed data can be sequentially stored in each compressed data buffer401, and it is thereby possible to prevent the data buffer107from becoming a bottleneck. Moreover, each data decompression circuit110determines the consistency of a plurality of check codes, for instance, a header check code part and a footer check code part, to be added to the decompressed data upon decompressing the compressed data, and transfers the decompressed data to each data search circuit111on the condition that there is consistency, and prohibits the transfer of the decompressed data when there is no consistency.

Each data search circuit111comprises a database (DB) page buffer402for storing, for each page unit, data in page units which were decompressed by each data decompression circuit110. Each data search circuit111searches for data which satisfies the search conditions among the data to be searched with the data in page units stored in the database page buffer402as the data to be searched, and transfers, to the search result output buffer/DMA circuit112, the data obtained in the search as the search result.

The search result output buffer/DMA circuit112comprises a search result buffer403for storing the search result of each database search circuit111, and additionally comprises a DMA buffer404for retrieving and storing the contents stored in each search result buffer403. The contents of the search result stored in the DMA buffer404are sent from the DMA buffer404to the host primary storage device102via the host interface103through DMA.

FIG. 5is a diagram explaining the configuration of a data decompression circuit. InFIG. 5, the data decompression circuit110is configured from a compressed data buffer401, a compressed data decompression circuit501and a check code confirmation circuit502, and the compressed data decompression circuit501is connected to the database page size register113and the compressed data buffer401, and the check code confirmation circuit502is connected to the database page buffer402of the data search circuit111.

When the compressed data in decompression units are transferred from the compressed data buffer401, the compressed data decompression circuit501decompresses the compressed data according to the page unit set in the database page size register113, and processes the decompressed data as data in page units. The compressed data decompression circuit501is a circuit for decompressing lossless compressed data, and the LZ method may be adopted as the compression method.

The check code confirmation circuit502confirms the consistency of the decompressed data, and, when the data have consistency and are authentic, adds a message to such effect to the decompressed data and transfers the decompressed data to the database buffer402. Here, the check code confirmation circuit502confirms, as described later, the consistency of the header check code part and the footer check code part of the database page which is prescribed in a database page format.

FIG. 6is a diagram explaining the configuration of a database data search circuit. InFIG. 6, the data search circuit111is a circuit for searching for the data of the database, and is configured from a database page buffer402, a data match comparison circuit601, a data match result buffer602and a data segmentation circuit603. The data match comparison circuit601is connected to the database page buffer402and the database page size register113, and the data segmentation circuit603is connected to the database page buffer402, the database page size register113, and the search result buffer403of the search result output buffer/DMA circuit112.

The data match comparison circuit601retrieves as the data to be searched, from the database page buffer402, the decompressed data which are data in page units, retrieves, from the database page size register113, information of the search key added to the search request, refers to the data to be searched for each line, determines for each line whether data that matches the search key exists in the data to be searched, and stores the matched data in the data match result buffer602in cases where matched data exists in the data of each line.

The data segmentation circuit603retrieves as the data to be searched, from the database page buffer402, the data in page units, retrieves information of the search key from the database page size register113, refers to the data of each line stored in the data match result buffer602, segments the data of the column which matches the search key among the data of each line, and transfers the data of the segmented column to the search result buffer403as the data of the search result.

FIG. 7is a diagram explaining the configuration of a data match comparison circuit. InFIG. 7, the data match comparison circuit601is configured from a comparative data segmentation circuit701, a segmentation position register702, a comparison key register703, a comparison key selection circuit704, a comparator705, a key match storage register706, a comparison key logical register707, and a logical operation circuit708. The comparative data segmentation circuit701is connected to the database page size register113and the database page buffer402, and the logical operation circuit708is connected to the data match result buffer602of the data search circuit111.

InFIG. 7, the segmentation position register702stores information (information of the segmentation position) of the position of the comparison target section to be segmented among the data of the database (database data) which are being managed in page units. The comparative data segmentation circuit701retrieves the set value of the page unit from the database page size register113, retrieves, from the database page buffer402, the decompressed data, which are data in page units, as the data to be searched, segments the data of the comparative target section which was set in the segmentation position register702, and which is data of the comparative target section existing in each line, among the data to be searched in page units, and transfers the segmented data to the comparator705.

Meanwhile, the comparison key register703stores information such as the comparison key (data key) and the comparison conditions (match, size, etc.) among the information that was added to the search request. The comparison key selection circuit704selects the comparison key and the comparison conditions to be used by the comparator705from the comparison key register703, and transfers information of the selected comparison key and comparison conditions to the comparator705.

The comparator705compares the data transferred from the comparative data segmentation circuit701(data of the comparative target section existing in each line) and the comparison key and the comparison conditions transferred from the comparison key selection circuit704, and stores, in the key match storage register706, the data which matches the comparison key and satisfies the comparison conditions as the data of the comparison result among the data of the comparative target section existing in each line.

The comparison key logical register707stores information of a logical formula to be used in the logical operation circuit708, for example, information of AND, OR and the like. The logical operation circuit708retrieves the data stored in the key match storage register706, performs a logical operation using the logical formula stored in the comparison key logical register707, extracts data which satisfies the logical formula among the data stored in the key match storage register706, and transfers the extracted data to the data match result buffer602as the data indicating the comparison result of a match.

FIG. 8is a diagram explaining the configuration of a data segmentation circuit. InFIG. 8, the data segmentation circuit603is configured from a data read circuit801, a segmentation position register802, and a data position packing circuit803. The data read circuit801is connected to the database page size register113, the database page buffer402and the data match result buffer602, and the data position packing circuit803is connected to the search result buffer403of the search result output buffer/DMA circuit112.

InFIG. 8, the segmentation position register802stores information indicating the segmentation position of the data to be used by the data read circuit801. The data read circuit801retrieves information of the set value201indicating the page unit from the database page size register113, additionally retrieves the decompressed data, which are data in page units, from the database page buffer402, further retrieves the data indicating the comparison result of the data match comparison circuit601(hit data indicating the match comparison result) from the data match result buffer602of the data search circuit111, reads the data of the segmentation position of the data set in the segmentation position register802among the data retrieved from the data match result buffer602, and transfers the read data to the data position packing circuit803. The data position packing circuit803sequentially performs the position packing of the data transferred from the data read circuit801according to the segmentation position of the data set in the segmentation position register802, and transfers the position-packed data to the search result buffer403as the data of the search result.

FIG. 9is a configuration diagram of a database page format. InFIG. 9, the database page format is a format which prescribes the structure for storing data in pages units, for example, data having a capacity of 8 KB or less (page data303of the database), in the database page901. The database page901is configured from a database page header902, a line 1 data903, a line 2 data904, . . . , a database page footer905, a line 1 pointer906, a line 2 pointer907. . . .

The line 1 data903is configured from a line header908, a column 1 data909, a column 2 data910, . . . , and a last column data911. The database page header902is configured from a header check code part912, and header and other information913. The database page footer905is configured from a footer check code part914, and footer and other information915.

FIG. 10is an explanatory diagram explaining the read processing of comparative data based on a database page format. InFIG. 10, when reading data in page units, the data search circuit111calculates the position of the line header as the line pointer that is adjacent to the database page footer905by using, for example, the addresses stored in the line 1 pointer906and the line 2 pointer907, adds the foregoing calculated value and the offset of each column (address indicating the segmentation position of each column) stored in the segmentation position register702, calculates the address of the read destination based on the foregoing added value, and reads the data of the column identified with the calculated read destination address for each line.

For example, the data search circuit111adds the address stored in the line 1 pointer906and the offset of the column 1 segmentation position stored in the segmentation position register702, calculates the address of the read destination from the added value, and reads the line 1, column 1 data1002as the data that is identified with the calculated read destination address. Moreover, the data search circuit111adds the address stored in the line 1 pointer906and the offset of the column 2 segmentation position stored in the segmentation position register702, calculates the address of the read destination from the added value, and reads the line 1, column 2 data1003as the data that is identified with the calculated read destination address.

FIG. 11is an explanatory diagram explaining the procedure for comparing the database page data and the comparison key based on a database page format. InFIG. 11, when comparing the read data (page data303of the database) and the comparison key after the column data of each line has been read in the comparative data read processing, the data search circuit111, for example, compares the line 1, column 1 data1002and the column 1 comparison key stored in the comparison key register703, and performs a logical operation to the line 1, column 1 data1002based on the logical formula stored in the comparison key logical register707when the contents of the line 1, column 1 data1002and the column 1 comparison key are a match, or when data which coincides with the comparison key exists in the line 1, column 1 data1002.

Subsequently, when data which satisfies the logical formula exists in the line 1, column 1 data1002, the data search circuit111determines that it is a match, and transfers the line 1, column 1 data1002to the data match result buffer602. The data search circuit111performs this processing separately for each column, and transfers the comparison result of each column to the data match result buffer602.

FIG. 12is an explanatory diagram explaining the data segmentation procedure based on a database page format. InFIG. 12, when it is determined that data which satisfies the search conditions exists in the line 1, column 1 data among the data existing in the page data of the database, the data search circuit111executes processing for reading the data of line 1, column 2. Here, the data search circuit111adds the address stored in the line 1 pointer906and the address indicating the column 2 segmentation position stored in the segmentation position register802to calculate the top address indicating the data read destination, reads the data of the line 1, column 2 data1003as the data that is identified with the calculated address, and processes the read data as the data that was segmented from the data match result buffer602.

As a result of repeating the processing shown inFIG. 10toFIG. 12, it is possible to read the data of each line and each column which coincides with the search conditions among the page data303of the database, which are data in page units.

FIG. 13is an explanatory diagram explaining the parallel reading of compressed data. InFIG. 13, in cases where compressed data 1, 2, 3 having different data sizes after compression are respectively stored in blocks305,306,310of three flash memories109, the parallel reading of the compressed data 1, 2, 3 into the data buffer107is not dependent on the data size after compression, and the read processing of the compressed data 1, 2, 3 is started simultaneously.

Here, the compressed data 1, 2, 3 are each sequentially stored in the data storage areas1304,1305,1306of the data buffer107by the flash controller108. With regard to the data size after compression, the compressed data 1 is the largest, the compressed data 2 is the second largest, and the compressed data 3 is the smallest. Thus, after the compressed data 3 is entirely stored in the data storage area1306, the compressed data 2 is then entirely stored in the data storage area1305, and the compressed data 1 is thereafter entirely stored in the data storage area1304. In other words, the compressed data is stored in the respective data storage areas in order from the compressed data having the smallest data size after compression.

Here, since the data size after compression is different, even when the flash controller108reads, in parallel, the compressed data 1, 2, 3 from each flash memory109, the time required for entirely restoring the respective compressed data 1, 2, 3 in the data buffer107will differ. Nevertheless, the management CPU105sequentially transfers, to one of the data decompression circuit110, the compressed data read into the data buffer107in the order of its arrival (order that the compressed data is entirely stored), and activates each data decompression circuit110to which the compressed data was transferred.

The management CPU105monitors whether the compressed data, including data in page units, have been entirely stored in one of the data storage areas1304,1305,1306of the data buffer107, transfers, to one of the data decompression circuits110, the compressed data in the data storage area where the compressed data, including data in page units, have been entirely stored, on the condition that the compressed data, including data in page units, have been entirely stored in one of the data storage areas, and activates data decompression circuit110to which the compressed data was transferred.

For example, the management CPU105foremost transfers the compressed data 3 in the data storage area1306to the data decompression circuit110, thereafter transfers the compressed data 2 in the data storage area1305to the data decompression circuit110, and finally transfers the compressed data 1 in the data storage area1304to the data decompression circuit110. Each data decompression circuit110decompresses the transferred compressed data, and transfers the decompressed data to the data search circuit111as the data in page units.

As described above, since the compressed data, including data in page units, are stored in the data buffer107upon reading, in parallel, a plurality of compressed data 1, 2, 3 having a different data size after compression and storing the read compressed data in the data buffer107, and decompressing the respective compressed data 1, 2, 3 stored in the data buffer107with each data decompression circuit110according to the decompression unit, even if the compressed data stored in the data buffer107is transferred to the data decompression circuit110in order without determining whether the data to be searched, which are data in search units, have been entirely stored in the data buffer107, the data decompression circuit110can transfer the decompressed data to the data search circuit111as the data in page units by decompressing the transferred compressed data in decompression units, and the data search circuit111can search the data to be searched with the data in page units as the data to be searched; that is, with the data in page units as the data to be searched and as the data in search units.

According to this embodiment, since the compressed data which were read in parallel from the flash memory109into the data buffer107are retrieved by each data decompression circuit110, the compressed data is decompressed in parallel by each data decompression circuit110, and the decompressed data is searched in parallel by each data search circuit111, it is possible to prevent the processing of reading the compressed data from the flash memory109from becoming a bottleneck, and consequently speed up the data decompression/search processing of the data requested in the search request. Moreover, upon storing for each page unit, in the flash memory109, the compressed data obtained by compressing the data in which the data size before compression is the page unit as the search source data and reading the data requested in the search request from the flash memory109, since the compressed data is read in parallel from the flash memory109into the data buffer107, the respective read compressed data are decompressed by each data decompression circuit110in decompression units corresponding to page units, the decompressed data is managed in page units, and each data search circuit111manages the data to be searched based on the data in page units, it is possible to speed up the data decompression search processing of the data requested in the search request since there is no need to determine whether the data to be searched have entirely been stored in the data buffer107. In other words, since the decompression unit of each data decompression circuit110is set to a unit corresponding to the page unit of the database, even if the compressed data is read from the data buffer107in random order upon decompressing the respective compressed data belonging to the search source data with each data decompression circuit110, it is possible to execute the decompression processing of the read compressed data in the order that the reading of the compressed data is completed, and process the decompressed data, which are data in page units, as the data to be searched. Thus, it is possible to speed up the decompression processing of the read compressed data even when the respective compressed data belonging to the search source data are read from the data buffer107in random order, as well as speed up the search processing of the data to be searched.

Moreover, according to this embodiment, since the blocks305to308of each flash memory109store the page data303for each page unit and the page data303is not stored across a plurality of blocks, it is possible to prevent the data management from becoming complicated and causing performance deterioration in the reclamation operation, which is an operation that is unique to the flash memory109.

FIG. 14is an overall configuration diagram showing Embodiment 2 of a database assisted storage apparatus. InFIG. 14, the storage apparatus100in this embodiment is configured by additionally comprising a database page size table1401, and the remaining configuration is the same as Embodiment 1. Note that the blocks of each flash memory109store a plurality of compressed data of different page sizes (page units).

InFIG. 14, the database page size table1401is a table for storing information related to the page size of the database, and is a table for associating and managing the area of the logical address (area address) which is managed by the logical/physical address management table106, and the page size which is set in the database page size register113. Information recorded in the database page size table1401is managed by the management CPU105, and the data decompression circuit110, the data search circuit111and the data compression circuit114are used upon processing the data.

FIG. 15is a configuration diagram of a database page size table. InFIG. 15, the database page size table1401is a size table for recording the relationship of an area address which is added to the search request from the host CPU101and identifies the storage destination of the search source data, and a plurality of page sizes corresponding to different page units, and is configured from an area address field1501and a database page size field1502.

The area address is an identifier which is added to the search request and identifies the storage destination of the search source data. The respective items1503,1505,1507of the area address field1501store information (A, B, C, . . . ) indicating the area address. The database page size is information for identifying the page size of the database. The respective items1504,1506,1508of the database page size field1502store, for example, information of “8 KB” as information related to the database size. Parallel operation is enabled even in cases where the page size of a plurality of databases is different by separating and setting the area regarding the base size of a plurality of data.

A case where, for example, the search source data requested in the search request is data designated based on a plurality of area addresses A, B is now explained.

When data is written, the host CPU101sets the relationship of the area address which identifies the storage destination of the search source data and a plurality of page sizes corresponding to different page units, and the database data is compressed by the data compression circuit114in these areas and stored in the flash memory109via the flash controller108. Here, since data is compressed after being divided into the size set as the area according to the setting of the database page size table1401, data decompression is enabled for each such size upon executing the search.

Upon executing the search, the management CPU105refers to the database page size table1401, gives an instruction to each flash controller108to read the search source data identified based on the area addresses A, B, and each flash controller108refers to the database page size table1401and reads from each flash memory109, in parallel, a plurality of compressed data belonging to the search source data identified based on the area addresses A, B and which have different page sizes (page units), for example, compressed data of 8 KB and compressed data of 16 KB, and transfers the read compressed data to the data buffer107.

After confirming that the compressed data of 8 KB and the compressed data of 16 KB have been respectively stored in the data buffer107, the management CPU105transfers the compressed data of 8 KB and the compressed data of 16 KB to each data decompression circuit110. Each data decompression circuit110refers to the database page size table1401and deems that base size=decompression unit, and one data decompression circuit110decompresses the compressed data of 8 KB in a decompression unit of 8 KB and transfers the decompressed data as data of 8 KB to the data search circuit111, and the other data decompression circuit1110decompresses the compressed data of 16 KB in a decompression unit of 16 KB and transfers the decompressed data as data of 16 KB to the data search circuit111. Each data search circuit111refers to the database page size table1401and deems that base size=search unit, and one data search circuit111searches for the data to be searched with the data of 8 KB as the data to be searched, and the other data search circuit111searches for the data to be searched with the data of 16 KB as the data to be searched.

According to this embodiment, in addition to being able to yield the same effects as Embodiment 1, it is possible to execute, in parallel, data decompression/search processing to the data that was requested in the search request even in cases where the page size of a plurality of databases is different by separating and setting the area regarding the base size of a plurality of data.

FIG. 16is a configuration diagram of a storage system including a database assisted storage apparatus. InFIG. 16, the storage system is configured by connecting the storage apparatus100and the host CPU101via a network interface1601and a network1602, and the configuration of the storage apparatus100is the same as Embodiment 2.

In this embodiment, even when the storage apparatus100is connected to the host CPU101via the network1602and the network interface1601, the storage apparatus100can execute data decompression processing and data search processing according to information of the page size recorded in the database page size register111or the database page size table1401.

According to this embodiment, the same effects as Embodiment 1 and Embodiment 2 can be yielded even when the storage apparatus100is connected to the host CPU101via the network1602and the network interface1601.

Note that the present invention is not limited to the embodiments described above, and also covers various modified examples. For example, it is also possible to use a controller having the functions of the management CPU105and each flash controller108, and which controls the I/O of data to and from the data buffer107and each flash memory109with a controller which governs the control of the overall storage apparatus100. Furthermore, the foregoing embodiments were described in detail for explaining the present invention in an easy-to-understand manner, and the present invention is not necessarily limited to the configurations comprising all of the components. Moreover, a part of the configuration of a certain embodiment may be replaced with the configuration of another embodiment, and the configuration of a certain embodiment may be added to the configuration of another embodiment. Moreover, a different configuration may be added to, deleted from or replaced with a part of the configuration of the respective embodiments.

Moreover, a part or all of the respective configurations, functions, processing units and processing means described above may be realized with hardware such as by designing integrated circuits. Moreover, the respective configurations and functions described above may also be realized with software by a processor interpreting and executing the programs that realize the respective functions. Information such as programs, tables and files for realizing the respective functions may be recorded and stored in a storage device such as a memory, a hard disk, or an SSD (Solid State Drive), or in a recording medium such as an IC (Integrated Circuit) card, an SD (Secure Digital) memory card, or a DVD (Digital Versatile Disc).

REFERENCE SIGNS LIST

100storage apparatus,101host CPU,102host primary storage device,103host interface,104data DMA circuit,105management CPU,106logical/physical address management table,107data buffer,108flash controller,109flash memory,110data decompression circuit,111data search circuit,112search result output buffer/output DMA circuit,113database page size register,114data compression circuit,201database page size register,301logical address item,302flash memory block address item,303database page data,304flash memory,305flash memory block storing two logical address data,306flash memory block storing one logical address data in two blocks,307flash memory block storing two logical address data in one block,308flash memory block storing one logical address data in two blocks,401compressed data buffer,402database page buffer,403search result buffer,404result DMA buffer,501compressed data decompression circuit,502check code confirmation circuit,601data match comparison circuit,602data match result buffer,603data segmentation circuit,701comparative data segmentation circuit,702segmentation position register,703comparison key register,704comparison key selection circuit,705comparator,706key match storage register,707comparison key logical register,708logical operation circuit,801data read circuit,802segmentation position register,803data position packing circuit,901database page,902database page header,903line 1 data,904line 2 data,905database page footer,906line 1 pointer,907line 2 pointer,908line header,909column 1 data,910column 2 data,911last column data,912header check code part,913header and other information,914footer check code part,915footer and other information,1001line 1 header,1002line 1, column 1 data,1003line 1, column 2 data,1004line 1, column 2 data,1005line 2 header,1006line 2, column 1 data,1007line 2, column 2 data,10082 line, 2 column data,1009column 1 segmentation position register,1010column 2 segmentation position register,310part three of compressed data in flash memory,1304part one of compressed data read into data buffer,1305part two of compressed data read into data buffer,1306part three of compressed data read into data buffer,1401database page size table.