METHOD OF CLEANING BOTTOM OF VIA HOLE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

In a method of cleaning a bottom of a via hole, a copper oxide on a surface of an underlying Cu wiring exposed at the bottom of the via hole is removed before forming a Cu wiring in a trench and the via hole extended between the trench and the underlying Cu wiring. The trench and the via hole are formed in a predetermined pattern in an interlayer insulating film of a substrate. Reducing species containing a metal in a state capable of reducing the copper oxide is supplied to the bottom of the via hole. The metal has a higher oxidation tendency than Cu and an oxide of the metal has a lower electrical resistance than the copper oxide. The copper oxide is removed by reducing the copper oxide and the oxide of the metal is generated through a reaction between the metal in the reducing species and the copper oxide.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Japanese Patent Application No. 2015-047015 filed on Mar. 10, 2015, the entire contents of which are incorporated herein by reference.

FIELD OF THE INVENTION

The disclosure relates to a method of reducing and removing a copper oxide formed on a surface of a Cu wiring at the bottom of a via hole and a method of manufacturing a semiconductor device.

BACKGROUND OF THE INVENTION

As an integration density of a semiconductor device is increased, a geometric dimension of an internal wiring or a semiconductor element is miniaturized. Due to demands for a high speed, miniaturization and high integration of the semiconductor device, there is employed a multilayer interconnection structure in which Cu wirings having a low resistance and a low electromigration are buried in multilayers in an interlayer insulating film. Such a multilayer interconnection structure is formed by a dual damascene method. In other words, a trench as a wiring groove is formed in the interlayer insulating film and a via hole to be connected to an underlying Cu wiring is formed at a bottom portion of the trench. Then, the trench and the via hole are filled with Cu. Before they are filled with Cu, a barrier film for preventing diffusion of Cu is formed on inner walls of the trench and the via hole.

A surface of Cu is easily oxidized in the atmosphere. Therefore, before the trench and the via hole are filled with Cu, copper oxide is formed on a surface of the underlying Cu wiring which is exposed at the bottom of the via hole. The copper oxide is an insulating material and increases resistance. Therefore, before the formation of the barrier film, there is performed a cleaning process for reducing and removing the copper oxide at the bottom of the via hole.

As a technique for removing an oxide such as copper oxide, there is known a reduction process using H2such as H2annealing, H2radical processing, H2plasma processing or the like. In addition, dry cleaning using an organic acid such as formic acid is suggested (e.g., Japanese Patent Application Publication No. 2009-043976). Further, a method for removing an oxide by argon sputtering etching is suggested (e.g., Japanese Patent Application Publication No. 2010-192467).

However, the reduction process using H2such as the H2annealing, the H2radical processing, the H2plasma processing or the like may adversely affect the device due to its high processing temperature. In the H2annealing, it is not possible to sufficiently reduce the copper oxide. In the H2radical processing and the H2plasma processing, an effect of reduction in a narrow pattern is insufficient. Further, in the H2plasma processing, the underlying insulating film may be damaged.

The organic acid dry cleaning is disadvantageous in that copper scatters due to the insufficient reduction of copper oxide.

The removal method using argon sputtering etching is disadvantageous in that the effect of removal in the narrow pattern is insufficient and also in that the damage to the underlying insulating film or the scattering of Cu may occur.

SUMMARY OF THE INVENTION

In view of the above, the disclosure provides a method of cleaning the bottom of a via hole, which is capable of preventing an adverse effect on an underlying insulating film and scattering of Cu and realizing low resistance by effectively removing copper oxide formed on a surface of a Cu wiring at the bottom of the via hole even in a narrow pattern, and a method of manufacturing a semiconductor device.

In accordance with a first aspect, there is provided a method of cleaning a bottom of a via hole which removes a copper oxide on a surface of an underlying Cu wiring exposed at the bottom of the via hole before formation of a Cu wiring in a trench and the via hole extended between the trench and the underlying Cu wiring. The trench and the via hole are formed in a predetermined pattern in an interlayer insulating film of a substrate. In the method, reducing species containing a metal in a state capable of reducing the copper oxide is supplied to the bottom of the via hole. The metal has a higher oxidation tendency than Cu and whose oxide has a lower electrical resistance than the copper oxide. The copper oxide is removed by reducing the copper oxide and the oxide of the metal is generated through a reaction between the metal contained in the reducing species and the copper oxide on the surface of the underlying Cu wiring.

In the first aspect, the metal may be Mn, Zn, Sn or In. The metal is deposited as the reducing species by PVD on a surface of the substrate which includes the bottom of the via hole, and the deposited metal and the copper oxide on the surface of the underlying Cu wiring can also react with each other by heating. In this case, it is preferable to remove moisture by performing a degas process on the substrate before the cleaning of the bottom of the via hole.

In accordance with a second aspect, there is provided a method of cleaning a bottom of a via hole which removes a copper oxide on a surface of an underlying Cu wiring exposed at the bottom of the via hole before formation of a Cu wiring in a trench and the via hole extended between the trench and the underlying Cu wiring. The trench and the via hole are formed in a predetermined pattern in an interlayer insulating film of a substrate. In the method, Mn-containing material which contains Mn in a state capable of reducing the copper oxide is supplied to the bottom of the via hole as reducing species. The copper oxide is removed by reducing the copper oxide and a manganese oxide is generated through a reaction between the Mn-containing material and the copper oxide on the surface of the underlying Cu wiring.

In the second aspect, Mn is deposited as the Mn-containing material by PVD on a surface of the substrate which includes the bottom of the via hole, and the deposited Mn and the copper oxide on the surface of the underlying Cu wiring can react with each other by heating. A manganese film is formed by CVD on a surface of the substrate which includes the bottom of the via hole by using an organic Mn compound gas as the Mn-containing material, and the manganese film and the copper oxide on the surface of the underlying Cu wiring can also react with each other. In this case, it is preferable to remove moisture by performing a degas process on the substrate before the cleaning of the bottom of the via hole.

In accordance with a third aspect, there is provided a method of a method of manufacturing a semiconductor device, which forms a Cu wiring connected to an underlying Cu wiring by filling a Cu-based film in a trench and the via hole extended between the trench and the underlying Cu wiring. The trench and the via hole are formed in a predetermined pattern in an interlayer insulating film of a substrate. In the method, a bottom of the via hole is cleaned by supplying reducing species containing a metal which has a higher oxidation tendency than Cu and whose oxide has a lower electrical resistance than a copper oxide formed on the surface of the underlying Cu wiring, in a state capable of reducing the copper oxide. The copper oxide is removed by reducing the copper oxide and the oxide of the metal is generated through a reaction between the metal contained in the reducing species and the copper oxide. Next, a barrier film is formed on a surface of the interlayer insulating film. A Cu-based film is filled in the trench and the via hole. A Cu wiring is formed by polishing a surface of the substrate including the Cu-based film.

In accordance with a forth aspect, there is provided a method of manufacturing a semiconductor device, which forms a Cu wiring connected to an underlying Cu wiring by filling a Cu-based film in a trench and a via hole extended between the trench and the underlying Cu wiring. The trench and the via hole are formed in a predetermined pattern in an interlayer insulating film of a substrate. In the method, the bottom of the via hole is cleaned by supplying to the bottom of the via hole a Mn-containing material which contains Mn in a state capable of reducing a copper oxide formed on the surface of the underlying Cu wiring as reducing species, and the copper oxide is removed by reducing the copper oxide and generating a manganese oxide through a reaction between the Mn-containing material and the copper oxide. Next, a barrier film is formed on the surface of the interlayer insulating film. The Cu-based film is filled in the trench and the via hole. A Cu wiring is formed by polishing a surface of the substrate including the Cu-based film.

In the third aspect and the forth aspect, the filling the Cu-based film in the trench and the via hole may be performed by Cu plating.

The filling the Cu-based film in the trench and the via hole may be performed by PVD. In this case, before the filling the Cu-based film in the trench and the via hole, a layer to be wetted may be further formed on the surface of the barrier film. The layer to be wetted is made of a metal which can be wetted by Cu or Cu alloy. It is preferable to form the Cu-based film in the trench and the via hole by PVD under a condition in which the Cu-based film is movable on the layer. The layer is preferably made of Ru or Co. The layer is preferably formed by CVD.

DETAILED DESCRIPTION OF THE EMBODIMENTS

<Method of Cleaning Via Hole Bottom>

First, a method of cleaning the bottom of a via hole according to an embodiment will be described.FIGS. 1A to 1Cschematically show concept of the method of cleaning the bottom of the via hole according to the embodiment.

Here, a via hole bottom cleaning process is performed on a semiconductor wafer (hereinafter, simply referred to as “wafer”) W in which an interlayer insulating film202that is an Si-containing film, such as an SiO2film, a low dielectric constant (low-k) film (SiCO, SiCOH or the like) or the like, is formed on a lower structure201(details thereof are omitted) including a underlying Cu wiring211, and a trench203and a via hole204connected to the underlying Cu wiring211from a bottom portion of the trench203are formed in a predetermined pattern in the interlayer insulating film202, as shown inFIG. 1A. Specifically, a copper oxide212is formed on a surface of the underlying Cu wiring211exposed at a via hole bottom, i.e., a bottom of the via hole. The copper oxide is removed by reduction. The copper oxide is Cu2O or CuO. Hereinafter, both of Cu2O and CuO are referred to as CuOx.

In the cleaning of the via hole bottom, reducing species containing a metal, which has a higher oxidation tendency than Cu and whose oxide has a lower electrical resistance than copper oxide (CuOx), in a state capable of reducing copper oxide is supplied to the via hole bottom. Such a metal may be, e.g., Mn. As shown inFIG. 1B, a Mn-containing material220capable of reducing copper oxide is supplied as reducing species to the wafer W having the above-described structure. As shown inFIG. 1C, by applying predetermined heat energy, Mn in the Mn-containing material becomes a manganese oxide213by attracting oxygen around, and the copper oxide212at the via hole bottom is reduced by Mn in the reducing species to be a metal Cu.

The manganese oxide may be MnO, Mn3O4, Mn2O3, MnO2and the like. Therefore, those oxides are expressed by “MnOx” inFIGS. 1A to 1Cand the following description.

The oxidation tendency of metals can be found in the standard free energy-temperature diagram (Ellingham diagram) of oxide formation (Iron and Steel Handbook 1st Edition, Iron and Steel Institute of Japan) illustrated inFIG. 2. In the oxide formation line below the line of 4Cu+O2=2Cu2O shown inFIG. 2, the oxide formation free energy is lower than Cu (negative side is large), so that the oxidation tendency is increased. The intensity of the oxidation tendency can be determined by comparing the oxide formation free energy.

As can be seen from the Ellingham diagram, in the case of using the Mn-containing material as the reducing species, the oxidation tendency of Mn is stronger than that of Cu. For example, at 300K, the standard free energy of Cu2O per one mole of oxygen is −295 kJ, whereas the standard free energy of MnO is −725 kJ which is larger in a negative side. Further, in the copper oxide (CuOx), the number of oxygen atoms that can be bonded to a single Cu atom is 0.5 to 1. On the other hand, in the manganese oxide (MnOx), the number of oxygen atoms that can be bonded to a single Mn atom is 1 or 2 so that Mn attracts a larger number of oxygen atoms compared to Cu. Therefore, by supplying a Mn-containing material to the via hole bottom, the copper oxide is reduced by Mn and a manganese oxide is generated, as shown inFIGS. 1A to 1C. As some kinds of the manganese oxide, e.g., MnO2, have a lower electrical resistance than copper oxide that is an insulator, it is expected that resistance is decreased overall when the manganese oxide is generated by reducing the copper oxide compared to when the copper oxide is formed at the via hole bottom.

Zn, Sn, In or the like besides Mn may be used as a metal which has a higher oxidation tendency than copper oxide and whose oxide has a lower electrical resistance than copper oxide. ZnO, SnO2and In2O3are generated as oxides of Zn, Sn and In, respectively.

As a specific method for performing cleaning by supplying such reducing species to the via hole bottom, there may be employed PVD (Physical Vapor Deposition) and CVD (Chemical Vapor Deposition).

PVD includes, e.g., a sputtering method. For example, ionized PVD (iPVD) in which a film is formed by attracting ions to the wafer may be preferably used. The via hole bottom can be cleaned by supplying, e.g., a metal Mn, as reducing species by PVD.

FIG. 3is a cross sectional view of an ICP (Inductively Coupled Plasma) sputtering apparatus as an example of a PVD apparatus for performing cleaning by supplying the metal Mn as the reducing species to the via hole bottom.

As shown inFIG. 3, a plasma sputtering apparatus70includes a processing chamber1that is grounded and made of a metal such as aluminum or the like. A gas exhaust port2and a gas inlet port3are provided at a bottom portion of the processing chamber1. A gas exhaust line4is connected to the gas exhaust port2. A throttle valve5and a vacuum pump6for pressure control are connected to the gas exhaust line4. A gas supply line7is connected to the gas inlet port3. A gas supply source8for supplying a plasma excitation gas, e.g., Ar gas or the like, is connected to the gas supply line7. A gas control unit9including a gas flow rate controller, a valve and the like is installed in the gas supply line7.

Provided in the processing chamber1is a mounting table10for mounting thereon a wafer W as a substrate to be processed. The mounting table10is supported by a cylindrical support11. The mounting table10is made of a metal, e.g., an aluminum alloy or the like. The mounting table10is grounded via the support11. The mounting table10has therein a cooling jacket12through which a coolant of a predetermined temperature circulates and a resistance heater13coated with an insulator. The mounting table10is controlled to a predetermined temperature by the cooling jacket12and the resistance heater13.

A lower portion of the support11extends downward through an insertion hole14formed at a bottom central portion of the processing chamber1. The support11is vertically moved by an elevation unit (not shown) and the mounting table10is vertically moved by the vertical movement of the support11.

An extensible/contractible metal bellows15surrounds the support11. The metal bellows15has an upper end coupled to a bottom surface of the mounting table10and a lower end coupled to a top surface of the bottom portion of the processing chamber1. The mounting table10can be vertically moved while maintaining the airtightness in the processing chamber1.

A plurality of, e.g., three (only two are shown inFIG. 3) supporting pins16are vertically provided on the top surface of the bottom portion of the processing chamber1. A plurality of insertion holes17through which the supporting pins16are inserted are formed in the mounting table10. Therefore, when the mounting table10is lowered, the wafer W can be received by upper end portions of the supporting pins16that have penetrated through the insertion holes17, and then can be transferred to and from a transfer arm (not shown) that has entered from the outside. Provided at a lower sidewall of the processing chamber1is a loading/unloading port18through which the transfer arm enters. The loading/unloading port18can be opened and closed by a gate valve19.

A high frequency power supply21for bias is connected to the mounting table10through a power feed line20. A high frequency bias power is applied to the wafer W on the mounting table10by the high frequency power supply21. The high frequency bias power preferably has a frequency ranging from 400 kHz to 60 MHz, e.g., 13.56 MHz.

A transmitting plate22made of a dielectric material is airtightly provided at a ceiling portion of the processing chamber1through a seal member23. An induction coil24for generating a plasma in the processing space S in the processing chamber1is provided above the transmitting plate22. A high frequency power supply25for plasma generation is connected to the induction coil24. By supplying a high frequency power having a frequency of, e.g., 13.56 MHz, from the high frequency power supply25to the induction coil24, an induction field is generated in the processing space S through the transmitting plate22. A plasma of Ar gas supplied into the processing chamber1is generated by the induction field thus generated.

A baffle plate26is provided immediately below the transmitting plate22. An annular Mn target27having an inwardly inclined cross section (truncated cone shape) is provided below the baffle plate26to surround the upper portion of the processing space S. A DC power supply28for supplying a DC power for attracting Ar ions is connected to the target27. An AC power supply may be used instead of the DC power supply.

A magnet29is provided at an outer side of the target27. The target27is sputtered by Ar ions in the plasma, so that Mn is released therefrom. Most of the metal Mn is ionized while passing through the plasma.

A cylindrical protection cover member30made of a metal, e.g., aluminum, copper, or the like, is provided below the target27to surround the processing space S. The protection cover member30is grounded.

Next, the cleaning operation using the metal Mn as the reducing species in the plasma sputtering apparatus70configured as described above will be described with reference toFIGS. 4A and 4B.FIGS. 4A and 4Bshow states of the underlying Cu wiring existing at the via hole bottom in the case of cleaning the via hole bottom.

The wafer W having the structure shown inFIGS. 1A to 1Cis loaded into the processing chamber1shown inFIG. 3and then mounted on the mounting table10. The mounting table10is controlled to a predetermined temperature by controlling the power supply to the resistance heater13and the coolant supply to the cooling jacket12.

In that state, Ar gas is supplied at a predetermined flow rate, and the processing chamber1is evacuated by the vacuum pump6and maintained at a predetermined vacuum level while controlling the throttle valve5. Thereafter, the DC power is applied from the DC power supply28to the target27, and the high frequency power (plasma power) is applied from the high frequency power supply25to the induction coil24. A predetermined high frequency bias power is applied from the high frequency power supply21to the mounting table10.

As a consequence, in the processing chamber1, an Ar plasma is generated by the high frequency power applied to the induction coil24, thereby generating Ar ions. The Ar ions are attracted to the Mn target27by the DC voltage applied to the Mn target27. Thus, the Mn target27is sputtered and the metal Mn particles are released from the Mn target27.

The particles from the Mn target27are mostly ionized while passing through the plasma. The ionized particles are scattered downward. The ionization rate at this time is controlled by the high frequency power supplied from the high frequency power supply25.

When the ions are introduced into an ion sheath region, which is formed above the wafer W with a thickness of about a few mm, by the high frequency bias power applied from the high frequency power supply21to the mounting table10, the ions are attracted with strong directivity to be accelerated toward the wafer W. Accordingly, as shown inFIG. 4A, the metal Mn221as the Mn-containing material is supplied to the surface of the wafer W and deposited on the surface of the wafer W including the underlying Cu wiring211existing at the via hole bottom. At this time, as it is preferable to supply the amount of the metal Mn221which is enough to reduce the copper oxide (CuOx), an average film thickness of a few nm may be obtained by flash film formation. The step coverage of the PVD is not so good. Thus, in such the flash film formation, the metal Mn is deposited on the field portion or the bottom portion of the trench203or the via hole204and is hardly deposited on the sidewall of the trench203or the via hole204. Further, a discontinuous state such as an island shape or the like may occur even at the portion where the metal Mn is deposited. Since, however, the metal Mn serving as the reducing species is supplied in order to attract ambient oxygen, the film may not be necessarily continuous and may be discontinuous. In this case, it is preferable that at least 50% of the surface of the wafer W is covered by the metal Mn.

In the plasma sputtering process, the wafer W is heated and sputtered by controlling the temperature of the mounting table10to 100° C. to 300° C., or the wafer W is sputtered at a room temperature and then annealed at 100° C. to 300° C. As a consequence, as shown inFIG. 4B, the deposited metal Mn221reacts with the copper oxide (CuOx) 212 on the surface of the underlying Cu wiring211exposed at the bottom portion of the via hole204; the copper oxide (CuOx)212is reduced to metal Cu and becomes a part of the underlying Cu wiring211; and the metal Mn221is oxidized to the manganese oxide (MnOx)213.

The PVD is not limited to iPVD, and a conventional sputtering, ion plating or the like may be used. Further, it is preferable to substantially completely remove moisture adhered to the wafer W by performing a degas process on the wafer W at about 250° C. before the PVD process.

In the case of using CVD as a method for supplying reducing species, a metal Mn film is deposited by using an organic Mn compound gas as reducing species. As the organic Mn compound, it is preferable to use a cyclopentadienyl-based manganese compound. The cyclopentadienyl-based manganese compound may be bis(alkylcyclopentadienyl)manganese expressed by a general formula Mn(RC5H4)2such as Cp2Mn[═Mn(CH5)2], (MeCp)2Mn[═Mn(CH3CH4)2], (EtCp)2Mn[═Mn(C2H5C5H4)2], (i-PrCp)2Mn[═Mn(C3H7C5H4)2], and (t-BuCp)2Mn[═Mn(C4H9C5H4)2].

As another manganese compound, it is also possible to use a carbonyl-based manganese compound, a betadiketone-based manganese compound, an amidinate-based manganese compound, and an amideaminoalkane-based manganese compound.

The amidinate-based manganese compound may be bis (N,N′-dialkylacetamidinate) manganese expressed by a general formula Mn(R1N—CR3—NR2)2which is disclosed in U.S. Patent Application Publication No. US2009/0263965 A1.

The amideaminoalkane-based manganese compound may be bis(N,N′-1-alkylamide-2-dialkylaminoalkane) manganese expressed by a general formula Mn(R1N—Z—NR22)2which is disclosed in PCT Publication No. 2012/060428. Here, the notations R, R1, R2and R3in the general formula denote functional groups expressed by —CnH2n+1(n being an integer greater than or equal to 0) and the notation Z denotes a functional group expressed by —CnH2n— (n being an integer greater than or equal to 1).

The organic Mn compound is in a solid or a liquid state at a room temperature. For example, a gas obtained by heating the organic Mn compound to about 80° C. is used as reducing species. In the case of performing a CVD process by supplying the organic Mn compound as the reducing species, the degas process is performed on the wafer W at about 250° C. before the CVD process so that moisture or the like adhered to the wafer W can be substantially completely removed. This is because, if the degas process is not performed, the moisture adhered to the wafer W reacts with the organic Mn compound and the manganese oxide is deposited on the interlayer insulating film of the pattern as well as on the copper oxide at the via hole bottom.

FIG. 5is a cross sectional view showing an example of a CVD apparatus for performing cleaning by supplying an organic Mn compound as reducing species to the via hole bottom.

The CVD apparatus80includes a tubular processing chamber41made of, e.g., aluminum or the like. In the processing chamber41, a mounting table42made of ceramic, e.g., AlN or the like, for mounting thereon the wafer W is provided. A heater43is provided in the mounting table42. The wafer W is heated by the heater43through the mounting table42.

A shower head44for introducing a processing gas for film formation, a purge gas, or the like into the processing chamber41in a shower shape is provided at a ceiling of the processing chamber41to face the mounting table42. A gas inlet port45is formed at an upper portion of the shower head44. A gas diffusion space46is formed in the shower head44. A plurality of gas injection holes47is formed on a bottom surface of the shower head44. A gas supply line48is connected to the gas inlet port45. A gas supply source49for supplying an organic Mn compound gas for film formation, a purge gas, or the like is connected to the gas supply line48. A gas control unit50including a gas flow rate controller, a valve, and the like is installed in the gas supply line48.

In the gas supply source49, the organic Mn compound maintained in a liquid state by heating is vaporized at about 80° C. by a bubbling container or a vaporizer, and then supplied to the gas supply line48

A gas exhaust port51is provided at a bottom portion of the processing chamber41. A gas exhaust line52is connected to the gas exhaust port51. A throttle valve53and a vacuum pump54for pressure control are installed in the gas exhaust line52, so that the processing chamber41can be evacuated.

Three wafer supporting pins56(only two being shown) for transferring the wafer can protrude beyond and retreat below the surface of the mounting table42. The wafer supporting pins56are fixed on a supporting plate57. The wafer supporting pins56are vertically moved together with the supporting plate57by vertically moving a rod59by a driving unit58such as an air cylinder or the like. Reference numeral60denotes a bellows. A wafer loading/unloading port61is formed at a sidewall of the processing chamber41. The wafer loading/unloading port61can be opened/closed by a gate valve62. The loading/unloading of a wafer W can be performed in a state where the gate valve62is opened.

Hereinafter, a cleaning operation using an organic Mn compound as reducing species in the CVD apparatus80configured as described above will be described with reference toFIGS. 6A to 6C.FIGS. 6A to 6Cshow states of the underlying Cu wiring existing at the via hole bottom in the case of cleaning the via hole bottom.

After the moisture is removed by performing the degas process on the wafer W having the structure shown inFIGS. 1A to 1Cat about 250° C., the gate valve62is opened and the wafer W that has been subjected to the degas process is mounted on the mounting table42. Then, the gate valve62is closed and the processing chamber41is exhausted by the vacuum pump54. The pressure in the processing chamber41is controlled to a predetermined level, and the wafer W on the mounting table42is heated to a predetermined temperature by the heater43. In that state, the organic Mn compound gas is introduced as reducing species from the gas supply source49into the processing chamber41through the gas supply line48and the shower head44. An organic Mn compound gas222is supplied to the wafer W as shown inFIG. 6A. At this time, the heating temperature of the wafer W can be appropriately set depending on purposes. When Mn is selectively supplied to the copper oxide exposed at the via hole bottom without being supplied onto the interlayer insulating film, it is preferable to set the heating temperature of the wafer W to be lower than a thermal decomposition temperature of the organic Mn compound (e.g., 250° C. in the case of bis(N,N′-1-alkylamide-2-dialkylaminoalkane)manganese). When it is required to ensure strong reducing power due to a thick film of the copper oxide exposed at the via hole bottom, it is preferable to set the heating temperature of the wafer W to be higher than the thermal decomposition temperature of the organic Mn compound.

When the organic Mn compound gas222is adsorbed onto the surface of the wafer W, a ligand223or the like of the organic Mn compound is separated and the metal Mn221is supplied to the surface of the wafer W and deposited on the surface of the wafer W including the surface of the underlying Cu wiring211at the via hole bottom, as shown inFIG. 6B. As shown inFIG. 6C, the metal Mn221supplied to the via hole bottom obtains oxygen from the copper oxide (CuOx) on the surface of the underlying Cu wiring211, thereby generating the manganese oxide (MnOx)213. The copper oxide (CuOx)212is reduced to a metal Cu and becomes a part of the underlying Cu wiring211. The deposited film thickness of the manganese oxide (MnOx)213at this time may be about a few nm. However, it is preferable to change the deposited film thickness of the manganese oxide depending on the degree of oxidation of the underlying Cu wiring surface.

The degas process may be performed by the CVD apparatus. The degas process may be performed at a temperature higher than or equal to that in the CVD process. For example, when the degas process is performed at a pressure of 1330 Pa and the CVD process is performed at a pressure of 13 Pa, the heat transfer to the wafer W is changed even if the temperature of the mounting table is maintained at a constant level. Therefore, the temperature of the degas process can be set to be higher than the temperature of the CVD process. In that case, a degas apparatus may not be provided separately.

Effect of the Embodiment

As described above, in the present embodiment, the copper oxide on the surface of the underlying Cu wiring is reduced by supplying to the via hole bottom the reducing species containing Mn having a higher oxidation tendency than Cu, and the manganese oxide having a lower electrical resistance than the copper oxide is generated. Therefore, the copper oxide can be reliably reduced even in a narrow pattern. As a result, it is possible to obtain the low resistance and prevent the damage to the underlying insulating film or the scattering of Cu.

Hereinafter, the result of the test in which the copper oxide is reduced by using the organic Mn compound as the reducing species will be described.

First, a Cu film (blanket film) was formed on a CVD-SiO2film on a Si wafer by PVD (plasma sputtering). Then, copper oxide was formed on the surface thereof by residual oxygen in the film forming apparatus and a degas process was performed. Next, (EtCp)2Mn as an organic Mn compound was vaporized and introduced into the processing chamber and the CVD process was performed at a wafer temperature of 200° C. for 600 sec. Thereafter, a Cu film was formed thereon by the PVD (plasma sputtering), for convenience.

FIG. 7shows a TEM (Transmission Electron Microscope) image of a cross section of a sample which is obtained by the above test.FIG. 8shows a result of backside SIMS (Secondary Ion Mass Spectrometry) analysis. As shown inFIG. 7, a discontinuous film having a thickness of 5 nm to 10 nm is formed between an upper and a lower Cu film. As shown inFIG. 8, the amount of Mn and O was increased at a portion where the CVD process using (EtCp)2Mn was performed and the concentration of Mn and that of O was substantially the same. Therefore, it is clear that the copper oxide on the surface of the underlying Cu film is removed and the manganese oxide is formed. Since the copper oxide that is an insulator is replaced by the manganese oxide having a lower electrical resistance than the copper oxide, the low resistance of the wiring can be realized. Further, as shown inFIG. 7, the manganese oxide is generated discontinuously and the upper Cu film and the lower Cu film are connected at the portion where the manganese oxide does not exist, which is advantageous in realizing the low resistance of the wiring.

Next, a trench and a via hole are formed as a dual damascene pattern in the interlayer insulating film made of a CVD-SiO2film formed on the underlying Cu wiring of the Si wafer. By exposing the dual damascene pattern to the atmosphere, copper oxide was generated on the surface of the underlying Cu wiring at the via hole bottom. Then, the degas process was performed and (EtCp)2Mn as an organic Mn compound was vaporized and introduced into the processing chamber. Next, the CVD process was performed at a wafer temperature of 200° C. for 600 sec. Thereafter, the via hole and the trench were filled with Cu by the PVD (plasma sputtering) and, then, the annealing process was performed at 400° C.

FIG. 9shows a TEM image of the cross section at that time. As shown inFIG. 9, the manganese oxide film is discontinuously formed between the underlying Cu wiring and the embedded Cu. A twin crystal grain boundary is formed between the underlying Cu wiring and the embedded Cu. The underlying Cu wiring and the embedded Cu are continuously formed. In addition, as a result of the analysis of crystal grain plane orientation using EBSD (Electron Back Scatter Diffraction), it is clear that Cu in the via hole and the underlying Cu wiring have the same plane orientation and become integrated. From the above, it can be thought that copper oxide which is an insulator can be replaced by manganese oxide having a lower electrical resistance by performing a process using reducing species containing Mn. Further, it can be thought that the low resistance is obtained by the integration of the underlying Cu wiring with the embedded Cu which is supposed to be separated by copper oxide continuously formed on the surface of the underlying Cu wiring at the via hole bottom.

<Method of Manufacturing Semiconductor Device>

Hereinafter, a semiconductor device manufacturing method including the above-described via hole cleaning method will be described.

First Example

A first example of the semiconductor device manufacturing method will be described with reference to the flowchart ofFIG. 10and the cross sectional view ofFIGS. 11A to 11G.

There is prepared a wafer W in which the interlayer insulating film202is formed on the lower structure201(details thereof are omitted) including the underlying Cu wiring211. The interlayer insulating film202is formed of a SiO2film, a low-k film (SiCO, SiCOH or the like) or the like. The trench203and the via hole204are formed in a predetermined pattern in the interlayer insulating film202. Moisture or the like adhered to the wafer W is removed by performing the degas process on the wafer W at, e.g., about 250° C., if necessary (step1,FIG. 11A). At this time, the copper oxide (CuOx)212is formed on the surface of the underlying Cu wiring211exposed at the via hole bottom.

Next, the reducing species, e.g., the Mn-containing material220, is supplied to the via hole bottom, and the copper oxide (CuOx)212on the surface of the underlying Cu wiring211is reduced and removed as described above (step2,FIG. 11B). By heating the wafer W during the supply of the reducing species, the copper oxide (CuOx) is reduced and the metal (e.g., Mn) contained in the reducing species is oxidized to generate the manganese oxide (MnOx)213at least on the surface of the underlying Cu wiring211. When the wafer W is at a room temperature, the above reaction may occur by performing an annealing process. Further, the above reaction may occur in a subsequent process including heating.

Next, the barrier film205which suppresses diffusion of Cu is formed on the surface of the wafer W including the surfaces of the trench203and the via hole204(step3,FIG. 11C).

As the barrier film205, it is preferable to use a film having a high barrier property to Cu and a low resistance, e.g., a Ti film, a TiN film, a Ta film, a TaN film, a dual film of Ta/TaN, a dual film of Ti/TiN, a dual film of Ti/TaN. Further, it is also possible to use a TaCN film, a W film, a WN film, a WCN film, a Zr film, a ZrN film, a V film, a VN film, a Nb film, a NbN film or the like. The resistance of the Cu wiring is decreased as the volume of Cu filled in the trench or the via hole is increased. Therefore, it is preferable to form a thin barrier film, and thus, the thickness thereof is preferably 1 nm to 10 nm and more preferably 1 nm to 5 nm. The barrier film can be formed by iPVD, e.g., plasma sputtering. Further, the barrier film may be formed by another PVD such as conventional sputtering, ion plating or the like, or by CVD, ALD, or CVD or ALD using a plasma.

Next, a Cu-based seed film206made of Cu or a Cu alloy is formed on the surface of the barrier film205by PVD (step4,FIG. 11D). A thickness of the Cu-based seed film206is preferably 5 nm to 60 nm.

In the case of using a Cu alloy for the Cu-based seed film206, Cu—Al and Cu—Mn may be representatively used. In addition, it is also possible to use Cu—Mg, Cu—Ag, Cu—Sn, Cu—Pb, Cu—Zn, Cu—Pt, Cu—Au, Cu—Ni, Cu—Co, Cu—Ti or the like.

The technique of the PVD used for forming the Cu-based seed film206is not limited. In order to form the Cu-based seed film206on an inner wall of a narrow trench or a narrow via hole, it is preferable to use iPVD for forming a film while attracting ions to the wafer. At this time, the PVD is preferably performed at a low temperature (e.g., −30° C. to 60° C.) so that Cu is not agglomerated.

Next, a Cu plating layer207is formed on the surface of the wafer W by Cu plating and, then, the trench203and the via hole204are filled with Cu (step5,FIG. 11E). Thereafter, an annealing process is performed (step6,FIG. 11F).

Then, the surface of the wafer W is planarized by removing the Cu plating layer207, the Cu-based seed film206, and the barrier film205by CMP (Chemical Mechanical Polishing) (step7,FIG. 11G). Accordingly, a Cu wiring210connected to the underlying Cu wiring211is formed.

Second Example

A second example of the semiconductor device manufacturing method will be described with reference to the flowchart ofFIG. 12and the cross sectional views ofFIGS. 13A to 13H.

As in the step1of the first example, there is provided a wafer W in which the interlayer insulating film202is formed on the lower structure201(details thereof are omitted) including the underlying Cu wiring211. The interlayer insulating film202is formed of a SiO2film, a low-k film (SiCO, SiCOH or the like) or the like. The trench203and the via hole204are formed in a predetermined pattern in the interlayer insulating film202. Moisture or the like adhered to the wafer W is removed by performing a degas process on the wafer W at, e.g., about 250° C., if necessary (step11,FIG. 13A). At this time, the copper oxide (CuOx)212is formed on the surface of the underlying Cu wiring211exposed at the via hole bottom.

Next, as in the step2of the first example, the Mn-containing material220is supplied as the reducing species and the copper oxide (CuOx)212on the surface of the underlying Cu wiring211exposed at the via hole bottom is reduced and removed as described above (step12,FIG. 13B). At this time, the copper oxide (CuOx) is reduced by heating and the metal (e.g., Mn) contained in the reducing species is oxidized to generate the manganese oxide (MnOx)213at least on the surface of the underlying Cu wiring211.

Next, as in the step3of the first example, a barrier film205suppresses diffusion of Cu is formed on the surface of the wafer W including the trench203and the via hole204(step13,FIG. 13C).

Next, a liner film214as a layer to be wetted is formed on the barrier film205in order to ensure a wettability to a Cu alloy or Cu filled in the trench203and the via hole204(step14,FIG. 13D). As the liner film214, it is preferable to use a Ru film or a Co film having an excellent wettability to Cu or a Cu alloy. The liner film214is preferably formed with a small thickness of, e.g., 1 nm to 5 nm, in order to obtain a low resistance of a wiring by increasing a volume of Cu to be filled. Due to the liner film214, when Cu or a Cu alloy is filled by the following PVD, the mobility thereof can be improved and the generation of overhang that blocks the opening of the trench or the via hole can be prevented. Therefore, Cu can be reliably filled by the PVD without generating a void in the fine trench or the fine via hole.

The liner film214is preferably formed by CVD. Accordingly, a thinner liner film214can be formed while ensuring a good step coverage. In the case of using a Ru film as the liner film214, it is preferable to form a film by thermal CVD while using ruthenium carbonyl (Ru3(CO)12) as a film forming material. Another film forming material other than Ru3(CO)12may be a pentadienyl compound of ruthenium, e.g., (cyclopentadienyl) (2,4-dimethylpentadienyl) ruthenium, bis(cyclopentadienyl) (2,4-methylpentadienyl)ruthenium, (2,4-dimethylpentadienyl) (ethylcyclopentadienyl) ruthenium, bis(2, 4-methylpentadienyl) (ethylcyclopentadienyl)ruthenium. Instead of the CVD, ALD or PVD may also be used for film formation. In the case of using a Co film, the film formation may be carried out by CVD, ALD, or PVD.

Next, a Cu-based film215made of Cu or a Cu alloy is formed on the surface of the liner film214by PVD under the condition that the mobility of Cu or a Cu alloy on the liner film214can be ensured, and the Cu-based film215is filled in the trench203and the via hole204(step15,FIG. 13E). The film formation at this time is preferably performed by iPVD in which ions are attracted to the wafer where the mobility of Cu or Cu alloy on the liner film214can be relatively easily ensured.

In the conventional film formation using the PVD, the overhang that blocks the opening of the trench or the hole is easily formed due to agglomeration of Cu. However, when the iPVD is applied, the film forming action of Cu ions and the etching action of ions (Ar ions) of the plasma generation gas are controlled by adjusting the bias power applied to the wafer so that Cu or Cu alloy can be moved on the liner film214having a high wettability to Cu or Cu alloy without agglomeration to thereby suppress the formation of the overhang. As a consequence, good fillability can be obtained without generating a void even in a narrow trench or a narrow hole. At this time, in order to ensure mobility of Cu and obtain good fillability, it is preferable to perform a high-temperature process (in a temperature ranging from 65° C. to 400° C. and more preferably ranging from 230° C. to 350° C.) in which Cu is migrated. By performing the film formation using the PVD at such a high temperature, Cu crystal grains can grow, thereby reducing the resistance of the Cu wiring.

When a Cu alloy is used as the Cu-based film215, Cu—Al and Cu—Mn may be used. As another Cu alloy, it is also possible to use Cu—Mg, Cu—Ag, Cu—Sn, Cu—Pb, Cu—Zn, Cu—Pt, Cu—Au, Cu—Ni, Cu—Co, Cu—Ti or the like.

Next, if necessary, a deposit layer216is formed on the Cu-based film215by performing Cu plating on the surface of the wafer W in order to prepare a planarization process to be performed later (step16,FIG. 13F). Then, annealing is performed (step17,FIG. 13G)). The deposit layer216may be formed by PVD.

Thereafter, as in the step7of the first example, the planarization process is performed by CMP to remove the deposit layer216, the Cu-based film215, the liner film214, and the barrier film205which are laminated on the surface of the wafer W (step18,FIG. 13H). Accordingly, the Cu wiring210connected to the underlying Cu wiring211is formed.

Hereinafter, a film forming system used for performing the semiconductor device manufacturing method will be described.

(Film Forming System Used for First Example)

FIG. 14schematically shows a film forming system used in the first example of the semiconductor device manufacturing method.

The film forming system100includes a first processing unit110for forming a barrier film and a Cu-based seed film, a second processing unit120for supplying a Mn-containing material that is reducing species to a via hole bottom, a loading/unloading unit130, and a control unit140. The film forming system100performs processes from a degas process up to formation of a Cu-based seed film on the wafer W having a trench and a via hole formed in a predetermined pattern.

The first processing unit110includes a first vacuum chamber111, a barrier film forming apparatus112and a Cu-based seed film forming apparatus113which are connected to walls of the first vacuum chamber111. The barrier film forming apparatus112and the Cu-based seed film forming apparatus113are disposed at opposite positions. The barrier film forming apparatus112forms the above-described barrier film205. The Cu-based seed film forming apparatus113forms the above-described Cu-based seed film206. The barrier film forming apparatus112and the Cu-based seed film forming apparatus113are configured as a PVD apparatus. As the PVD apparatus, an iPVD apparatus is preferably used. The plasma sputtering apparatus shown inFIG. 3may be preferably used.

Degas chambers114aand114beach for performing a degas process on the wafer W are connected to walls of the first vacuum transfer chamber111which face the second processing unit120. Further, a delivery chamber115through which the wafer W is transferred between the first vacuum transfer chamber111and a second vacuum transfer chamber121to be described later is connected to a wall of the first vacuum transfer chamber111which is disposed between the degas chambers114aand114b.

The barrier film forming apparatus112, the Cu-based seed film forming apparatus113, the degas chambers114aand114b, and the delivery chamber115are connected to the respective sides of the first vacuum transfer chamber111through gate valves G. They communicate with the first vacuum transfer chamber111by opening the corresponding gate valves G and are isolated from the first vacuum transfer chamber111by closing the corresponding gate valves G.

The inside of the first vacuum transfer chamber111is maintained at a predetermined vacuum atmosphere. Provided in the first vacuum transfer chamber111is a first transfer mechanism116for loading and unloading the wafer W. The first transfer mechanism116is disposed substantially at the center of the first vacuum transfer chamber111and has a rotatable and extensible/contractible portion117. The rotatable and extensible/contractible portion117has, at its leading end, two holding arms118aand118bfor holding the wafer W. The first transfer mechanism116loads and unloads the wafer W into and from the barrier film forming apparatus112, the Cu-based seed film forming apparatus113, the degas chambers114aand114b, and the delivery chamber115.

The second processing apparatus120includes: a second vacuum transfer chamber121and two Mn film forming apparatuses122aand122brespectively connected to opposite walls of the second vacuum transfer chamber121. The Mn film forming apparatuses122aand122bmay be used to supply a Mn-containing material as the reducing species to the via hole bottom. As the Mn film forming apparatuses122aand122b, the CVD apparatus shown inFIG. 5or the plasma sputtering apparatus shown inFIG. 3may be used. The Mn film forming apparatuses122aand122bare disposed at opposite positions.

The degas chambers114aand114bare connected to walls of the second vacuum transfer chamber121which face the first processing unit110, and the delivery chamber115is connected to a wall of the second vacuum transfer chamber121between the degas chambers114aand114b. In other words, the delivery chamber115and the degas chambers114aand114bare provided between the first vacuum transfer chamber111and the second vacuum transfer chamber121, and the degas chambers114aand114bare disposed at both sides of the delivery chamber115. Moreover, load-lock chambers124aand124bcapable of atmospheric transfer and vacuum transfer are respectively connected to walls of the second vacuum transfer chamber121which face the loading/unloading unit130.

The Mn film forming apparatuses122aand122b, the degas chambers114aand114b, and the load-lock chambers124aand124bare connected to the respective sides of the second vacuum transfer chamber121through gate valves G. They communicate with the second vacuum transfer chamber121by opening the corresponding valves G and are isolated from the second vacuum transfer chamber121by closing the corresponding gate valves G. The delivery chamber115is connected to the second transfer chamber121without providing a gate valve therebetween.

The inside of the second vacuum transfer chamber121is maintained at a predetermined vacuum atmosphere. Provided in the second vacuum transfer chamber121is a second transfer mechanism126for loading and unloading the wafer W into and from the Mn film forming apparatuses122aand122b, the degas chambers114aand114b, the load-lock chambers124aand124band the delivery chamber115. The second transfer mechanism126is disposed substantially at the center of the second vacuum transfer chamber121and has a rotatable and extensible/contractible portion127. The rotatable and extensible/contractible portion127has, at its leading end, two holding arms128aand128bfor holding the wafer W. The two holding arms128aand128bare attached to the rotatable and extensible/contractible portion127to face opposite directions.

The loading/unloading unit130is provided opposite to the second processing unit120with the load-lock chambers124aand124binterposed therebetween. The loading/unloading unit130has an atmospheric transfer chamber131connected to the load-lock chambers124aand124b. A filter (not shown) for forming a downflow of clean air is provided at an upper portion of the atmospheric transfer chamber131. Gate valves G are provided between the load-lock chambers124aand124band a wall of the atmospheric transfer chamber131. Provided at a wall of the atmospheric transfer chamber131opposite to the wall connected to the load-lock chambers124aand124bthrough the Gate valves G are two connection ports132and133each for connecting carriers C accommodating therein wafers W as substrates to be processed. Further, an alignment chamber134is provided at a side of the atmospheric transfer chamber131, and alignment of the wafer W is executed therein. Provided in the atmospheric transfer chamber131is an atmospheric transfer mechanism136for loading and unloading the wafer W into and from the carrier C and the load-lock chambers124aand124b. The atmospheric transfer mechanism136has two multi-joint arms and can move on a rail138along the arrangement direction of the carriers C. The atmospheric transfer mechanism136transfers wafers W while mounting the wafer W on each of hands137provided at leading ends of the respective arms.

The controller140is configured to control the respective components of the film forming system100. The controller140includes a process controller having a microprocessor (computer) for controlling the respective components, a user interface and a storage unit. The user interface includes a keyboard through which an operator inputs a command to manage the film forming system100, a display for visually displaying the operational states of the film forming system100and the like. The storage unit stores therein control programs to be used in realizing various processes performed in the film forming system100under the control of the process controller, and programs, i.e., processing recipes, to be used in controlling the respective components of the processing apparatuses to carry out processes under processing conditions and various data. The processing recipes are stored in a storage medium. The storage medium may be a hard disk, a portable medium such as a CD-ROM and a DVD, a semiconductor memory such as a flash memory or the like. A specific recipe is read out from the storage unit under an instruction from the user interface and is executed by the process controller. Accordingly, a desired process is performed in the film forming system100under the control of the process controller.

In the film forming system100, the wafer W having the trench and the via hole formed in a predetermined pattern is unloaded from the carrier C and is loaded into the load-lock chamber124aor124bby the atmospheric transfer mechanism136. After the pressure in the load-lock chamber124aor124bis decreased to a vacuum level substantially equivalent to that in the second vacuum transfer chamber121, the wafer W is unloaded from the load-lock chamber124aor124bto be loaded into the degas chamber114aor114bthrough the second vacuum transfer chamber121by the second transfer mechanism126. Thus, the wafer W is subjected to the degas process. Thereafter, the wafer W is unloaded from the degas chamber114aor114band is loaded into the Mn film forming apparatus122aor122bby the second transfer mechanism126. Thus, the via hole bottom cleaning process is performed by supplying a Mn-containing material to the wafer W, thereby reducing and removing copper oxide of the underlying Cu wiring. Then, the wafer W is unloaded from the Mn film forming apparatus122aor122bto be loaded into the delivery chamber115by the second transfer mechanism126. Next, the wafer W is unloaded from the delivery chamber115and loaded into the barrier film forming apparatus112through the first vacuum transfer chamber111by the first transfer mechanism116. Thus, the barrier film is formed as described above. After the barrier film is formed, the wafer W is unloaded from the barrier film forming apparatus112by the first transfer mechanism116and loaded into the Cu-based seed film forming apparatus113. Thus, a Cu-based seed film made of Cu or Cu alloy is formed. Next, the wafer W is unloaded by the first transfer mechanism116and transferred to the delivery chamber115. Then, the wafer W is unloaded from the delivery chamber115and transferred to the load-lock chamber124aor124bby the second transfer mechanism126. After the pressure in the load-lock chamber is returned to the atmospheric pressure, the wafer W having the Cu-based seed film is unloaded and is returned to the carrier C by the atmospheric transfer mechanism136. Such processes are repeated for all of wafers W in the carrier C.

In accordance with the film forming system100, via hole bottom cleaning, forming the barrier film, and forming the Cu-based seed film can be performed in the vacuum atmosphere without being exposed to the atmosphere. Accordingly, oxidation between layers can be prevented and a high-performance semiconductor device can be obtained.

The wafer W unloaded from the film forming system100is transferred to the Cu plating device and subjected to Cu plating, and then the wafer W is transferred to the CMP device and subjected to CMP processing.

(Film Forming System Used for Second Example)

FIG. 15schematically shows a film forming system used in the second example of the semiconductor device manufacturing method.

A film forming system101includes a first processing unit110′ for barrier film formation, liner film formation and Cu-based film formation, the second processing unit120for supplying an Mn-containing material as reducing species to a via hole bottom, the loading/unloading unit130and the control unit140. The film forming apparatus122aor122bperforms on the wafer W processes from a degas process up to forming the Cu-based film by filling the trench and the via hole with Cu or Cu alloy.

As in the case of the first processing unit110of the film forming system100shown inFIG. 14, the first processing unit110′ includes a first vacuum transfer chamber111, a barrier film forming apparatus112, degas chambers114aand114b, a delivery chamber115, and a first transfer mechanism116. In this example, an embedded Cu-based film forming apparatus113′ is provided instead of the Cu-based seed film forming apparatus113of the first processing unit110. Further, two liner film forming apparatuses119aand119bare connected to other walls of the first vacuum transfer chamber111. The Cu-based film forming apparatus113′ fills Cu or Cu alloy in the trench and the via hole by forming the Cu-based film215as described above. The Cu-based film forming apparatus113′ is configured as an iPVD apparatus. The plasma sputtering apparatus shown inFIG. 3may be preferably used as the Cu-based film forming apparatus113′. The liner film forming apparatuses119aand119bform a liner film214as a layer to be wetted. The CVD apparatus shown inFIG. 5may be preferably used as the liner film forming apparatuses119aand119b.

The second processing unit120, the loading/unloading unit130and the control unit140have the same configurations as those of the film forming system100.

In this film forming system101, the wafer W having the trench and the via hole formed in a predetermined pattern is unloaded from the carrier C and is loaded into the load-lock chamber124aor124bby the atmospheric transfer mechanism136. After the pressure in the load-lock chamber124aor124bis decreased to a vacuum level substantially equivalent to that in the second vacuum transfer chamber121, the wafer W is unloaded from the load-lock chamber124aor124bto be loaded into the degas chamber114aor114bthrough the second vacuum transfer chamber121by the second transfer mechanism126. Thus, the wafer W is subjected to the degas process. Thereafter, the wafer W is unloaded from the degas chamber114aor114band is loaded into the Mn film forming apparatus122aor122bby the second transfer mechanism126. The via hole bottom cleaning is performed by supplying a Mn-containing material to the wafer W. Thus, copper oxide of the underlying Cu wiring is reduced and removed. Then, the wafer W is unloaded from the Mn film forming apparatus122aor122bto be loaded into the delivery chamber115by the second transfer mechanism126. Next, the wafer W is unloaded from the delivery chamber115and loaded into the barrier film forming apparatus112through the first vacuum transfer chamber111by the first transfer mechanism116. Thus, the barrier film as described above is formed. After the barrier film is formed, the wafer W is unloaded from the barrier film forming apparatus112and loaded into the liner film forming apparatus119aor119bby the first transfer mechanism116. Thus, the liner film, e.g., a Ru film, is formed. After the liner film is formed, the wafer W is unloaded from the liner film forming apparatus119aor119band loaded into the Cu-based film forming apparatus113′ by the first transfer mechanism116. Thus, the Cu-based film made of Cu or Cu alloy is formed to fill the trench and the via. Next, the wafer W is unloaded from the Cu-based film forming apparatus113′ and transferred to the delivery chamber115by the first transfer mechanism116. Then, the wafer W is unloaded from the delivery chamber115and transferred to the load-lock chamber124aor124bby the second transfer mechanism126. After the pressure in the load-lock chamber is returned to the atmospheric pressure, the wafer W in which the trench and the via hole are filled by the formation of the Cu-based film is unloaded and is returned to the carrier C by the atmospheric transfer mechanism136. Such processes are repeated for all of wafers W in the carrier C.

In accordance with the film forming system101, the via hole bottom cleaning, forming the barrier film, forming the liner film, and forming the Cu-based film can be performed in the vacuum atmosphere without being exposed to the atmosphere. Accordingly, oxidation between layers can be prevented and a high-performance semiconductor device can be obtained.

The wafer W unloaded from the film forming system101is transferred to the Cu plating device, if necessary. Thus, an additional layer is formed by Cu plating. Then, the wafer W is transferred to the CMP device and subjected to CMP processing. The additional layer may be formed by the Cu-based film forming apparatus113′ of the film forming system101.

While the embodiments have been described, the present disclosure may be variously modified without being limited to the above-described embodiments. For example, in the above-described embodiments, a technique for supplying the reducing species to the via hole bottom by PVD or CVD has been applied. However, the technique is not limited thereto as long as an appropriate amount of the reducing species can be supplied to the via hole bottom.

For example, in the above-described embodiments, the semiconductor wafer has been described as an example of the substrate to be processed. However, the semiconductor wafer includes a compound semiconductor such as GaAs, SiC, GaN or the like as well as a typical silicon wafer. The substrate is not limited to the semiconductor wafer, and the present disclosure may also be applied to a glass substrate used for a FPD (flat panel display) such as a liquid crystal display or the like, a ceramic substrate, or the like.

The film forming system is not limited to a system divided into the first processing unit and the second processing unit shown inFIGS. 14 and 15, and may also be a system having another configuration in which the first processing unit and the second processing unit are formed as one unit.

While the disclosure has been shown and described with respect to the embodiments, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the scope of the disclosure as defined in the following claims.