De-spreader operative with selectable operational clock for spread spectrum communication and a method for the same

A de-spreading device for a spread spectrum communication system includes a first and a second correlator assigned to a regular and a power-saving operation mode, respectively. The first correlator performs sampling with a regular operational clock while the second correlator performs sampling with an operational clock higher in rate than the regular operational clock for thereby saving power. The regular or the power-saving operation mode is selected in accordance with radio channel quality estimated on the basis of a peak value detected from a correlation value, which is output from the first or the second correlator. De-spreading can therefore be implemented by an optimum operational clock matching with radio channel quality while consuming a minimum of current.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a de-spreading device applicable to a direct sequence spread spectrum (DS-SS) communication system and operable in a power-saving mode, and a method for the same.

2. Description of the Background Art

It is a common practice with a demodulator for a spread spectrum communication system to compare a signal output from a detector with a preselected threshold value to generate bi-level virtual chip data, which are of (logical) ZERO or (logical) ONE, to in turn execute correlation operation on the virtual chip data by use of a correlator, and then, based on the peak value of a correlation value, to estimate the optimum timing of symbol data decision and detect symbol data.

Japanese patent laid-open publication No. 2003-283369, for example, discloses a correlation detector configured to use a replica spread code to de-spread a digital spread-spectrum received signal with a correlator and then demodulate the resulting signal with a demodulator. More specifically, a matched filter produces a correlation from a digital spread spectrum code sequence while a correlation peak detector detects a correlation peak value out of the above correlation. Subsequently, a synchronous tracing circuit determines, on the basis of the correlation peak value, a timing for generating a replica spread code. In response to the timing thus determined, a replica spread code generator generates a replica spread code. Particularly, the matched filter includes bit-based filter segments each implemented by an Exclusive OR (EX-OR) gate and an adder.

The correlation detector taught in the document mentioned above compares demodulated data not subjected to error correction with demodulated data subjected to error correction bit by bit to thereby determine the number of bit errors, calculates, on the basis of the number of bit errors, a bit error rate with a receipt quality decision circuit, compares the bit error rate thus determined with a preselected threshold value to thereby determine receipt quality, and then selects, based on the determined receipt quality, the bit-based filter portions to be enabled by a search controller. When receipt quality is high, the correlation detector enables only a minimum necessary number of bit-based filter portions capable of detecting a correlation peak higher than the current correlation peak. This condition is held so long as receipt quality is high. It is therefore possible to reduce power consumption by the matched filter, which inherently consumes much more power, to a minimum necessary level.

Generally, the demodulation characteristic of a demodulator can be enhanced if the sampling frequency of a correlator is increased to improve the accuracy of timing for symbol data decision for thereby reducing symbol data decision errors. With such a correlator, a significantly high sampling frequency may not be required in a high C/N (Carrier-to-Noise) ratio environment. In a low C/N ratio environment, however, the sampling rate must be increased to some extent in order to achieve a desired characteristic. In this respect, a conventional demodulator has the following problem left unsolved.

In a conventional demodulator, an operational clock signal input to a correlator has its frequency fixed. The operational clock signal is therefore usually so determined as to satisfy a desired characteristic even when radio channel quality is low, e.g. when sensitivity is at the lowest limit that should be guaranteed. It follows that when radio channel quality is high a demodulator adapted for operating with a preselected operational clock signal without regard to radio channel quality wastefully consumes excessive current.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a de-spreading device for a spread spectrum communication system operable in a power-saving mode that reduces power consumption more effectively and a method for the same.

A de-spreading device of the present invention includes a comparator for comparing a detection output of a received signal, which is subjected to spectrum spread by a direct sequence system, with a predetermined comparative value to produce virtual chip data. A frequency divider divides the frequency of a master clock signal to generate an operational clock signal. A correlation circuit uses a predetermined spread code to perform correlation operation on the virtual chip data to produce a correlation value. A timing estimator detects a correlation peak value out of the correlation value to produce a timing signal based on the correlation peak value. Further, a decision circuit decides the correlation value in response to the timing signal and then outputs the correlation value as symbol data. With this configuration, the de-spreading device is selectively operable in any one of a plurality of modes including a first mode for regular operation and a second mode lower in power consumption than the first mode. The correlation circuit performs the correlation operation with, in the first mode, a first operational clock signal assigned to the regular operation, and, in the second mode, a second operational clock signal lower in rate than the first operational clock signal.

A de-spreading method for the above device is also disclosed.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring toFIG. 1of the accompanying drawings, a de-spreading device embodying the present invention is generally designated by the reference numeral10. Generally, the de-spreading device10includes a comparator12configured to feed virtual chip data106to correlators16and18. Each of the correlators16and18is also fed with a particular operational clock signal from a frequency divider14. Either one of the correlators16and18is selected in response to a mode select signal128output from a channel quality estimator26and is enabled to perform correlation operation to produce a correlation value. The correlation value thus output from the correlator16or18is selected by a selector20. The peak of the correlation value selected by the selector20is determined by a timing estimator22for thereby estimating an optimum timing for deciding symbol data. A symbol data decision circuit24decides symbol data on the basis of the correlation value and optimum timing mentioned above. Further, the channel quality estimator26produces an appropriate mode select signal in accordance with the peak of the correlation value.

It should be noted that parts and elements not directly relevant to the understanding of the present invention are not shown, and a detailed description thereof will not be made in order to avoid redundancy.

Whereas the illustrative embodiment shown inFIG. 1is provided with two correlators16and18only, the de-spreading device10may be provided with a more number of correlators, if desired. In the illustrative embodiment, a mode select signal128output from the channel quality estimator26is indicative of either one of a regular and a power-saving mode.

Specifically, in the illustrative embodiment, the comparator12is adapted to receive a detection signal102output from a detector, not shown, and a preselected threshold value104and compares the detection signal102with the threshold value104to determine symbol data to produce the result of comparison in the form of bilevel virtual chip data106. More specifically, the comparator12compares, e.g. an FSK (Frequency Shift Keying) detection signal with a threshold value which is equal to, e.g. its middle point, to produce, as the virtual chip data106, (logical) ONE if the detection signal is greater than or equal to the threshold value or otherwise (logical) ZERO. The virtual chip data106are fed to the correlators16and18.

The frequency divider14is adapted to divide the frequency of a master or reference clock signal108in matching relation to the number of times of sampling per symbol, i.e. a sampling frequency particular to a correlator. In the illustrative embodiment, the frequency divider14divides the master clock signal108by numbers, NA and NB, to produce operational clock signals110and112, respectively, and delivers the operational clock signals110and112to the correlators16and18, respectively.

The correlators16and18are adapted for using preselected spread codes114and115, respectively, to calculate correlations of the virtual chip data106and deliver the resulting correlation values116and118to the selector20. The correlators16and18may each be implemented by respective shift registers230,FIG. 2, having 1+k×(m−1) consecutive stages232arranged, where k and m are representative of the number of times of sampling for one chip and the number of chips assigned to one symbol, respectively. The spread codes114and115input to the correlators16and18, respectively, may be identical with each other, if desired.

In the illustrative embodiment, the correlators16and18are adapted to operate in the regular mode and power-saving mode, respectively, and have respective shift registers230different in length from each other. For example, the shift register length of the correlator18may be one-half of the shift register length of the correlator16. Either one of the correlators16and18is made active in response to the mode select signal128output from the channel quality estimator26. In the illustrative embodiment, the correlators16and18are rendered active and inactive, respectively, when the mode select signal128is indicative of the regular mode, or rendered inactive and active, respectively, when the signal128is indicative of the power-saving mode. Each of the correlators16and18may have its enable terminal interconnected for receiving the mode select signal128.

The selector20is adapted to select either one of the correlation values116and118output from the correlators16and18, respectively, in response to the mode select signal128and outputs the selected one as a correlation value120. For example, the selector20selects the correlation value116when the mode select signal128is indicative of the regular mode, or selects the correlation value118when the signal128is indicative of the power-saving mode.

The timing estimator22is adapted for receiving the correlation value120output from the selector20to detect symbol by symbol the peak value of the correlation value120appearing around a symbol timing. In the illustrative embodiment, the timing at which the peak value appears is delivered from the timing estimator22to the symbol data decision circuit24as an optimum timing signal122. Particularly, in the illustrative embodiment, the timing estimator22is connected to feed the peak value126to the channel quality estimator26.

The symbol data decision circuit24is adapted to decide the input correlation value120in response to the optimum timing signal122received from the timing estimator22and then output the result of decision as symbol data124. At this instant, the symbol data decision circuit24may be adapted to output the symbol data124at a timing defined by a self-running symbol clock.

The channel quality estimator26is adapted for estimating radio channel quality on the basis of the peak value126of the correlation value input from the timing estimator22and outputting the mode select signal128in accordance with the estimated circuit quality. In the illustrative embodiment, the mode select signal128initially output from the channel quality estimator26is indicative of the regular mode.

The illustrative embodiment has its number of chips assigned to a single symbol, i.e. a spread ratio set to a predetermined number “11” (eleven) by way of example. Then, the channel quality estimator26determines that radio channel quality is high when the correlation peak value126is “11”. Further, when such high radio channel quality continues over a period of time corresponding to a preselected number of consecutive symbols, the channel quality estimator26determines that the radio channel quality is significantly high, and then replaces the regular mode represented by the mode select signal128with the power-saving mode. Subsequently, in the power-saving mode, as soon as the correlation peak value126decreases below a preselected lower limit or threshold value, the channel quality estimator26determines that the radio channel quality has become low, and again switches the mode select signal128from the power-saving mode to the regular mode.

A specific operation of the de-spreading device10will be described hereinafter with the correlators16and18each implemented by 1+k×(m−1) stages232of the shift register230mentioned earlier. In the procedure to be described, m is assumed to be “11”. Further, with the specific configuration of the illustrative embodiment, the correlators16and18are implemented, where k is “16” and “8”, by one hundred and sixty-one (161) consecutive stages232of the shift register230and eighty-one (81) consecutive stages232of the shift register230, respectively, as shown inFIGS. 2 and 3.

First, a detection signal102output from the detector, not shown, is fed to the comparator12and compared with a preselected threshold value104thereby. In response, the comparator12outputs virtual chip data106which are ONE if the detection signal102is greater than or equal to the threshold value104or ZERO otherwise. The virtual chip data106are fed to the correlators16and18. At this stage of operation, in the comparator12, the virtual chip data106are not synchronized to the clock of the chip timing yet. At this time, the frequency divider14divides the frequency of the input master clock signal108and delivers the resulting operational clock signals110and112to the comparators16an18, respectively. For example, to output the operational clock signals110and12, the frequency divider14divides the frequency of the master clock signal108in accordance with the numbers k of times of sampling or sampling frequencies that are “16” and “8”, respectively.

Subsequently, either one of the correlators16and18is selected in response to the mode select signal128output from the channel quality estimator26and operates under the control of the operational clock signal110or112, respectively. Initially, the mode select signal128is indicative of the regular mode and renders the correlators16and18active and inactive, respectively.

The correlator16thus enabled determines a correlation between the consecutive virtual chip data106and the spread code114. More specifically, in the regular mode, all the 1+16×(m−1) stages232of the shift register230shown inFIG. 2are enabled to sample the virtual chip data106at a sixteen times higher sampling rate. On the other hand, the other correlator18disabled does not operate. In the illustrative embodiment, the correlators16and18may each be configured to oversample a single chip so as to determine a chip timing on the basis of the resulting data.

In the illustrative embodiment, in the correlator16, eleven chips of the virtual chip data stored in the “1+16×(n−1)”-th shift register stage (n being 1, 2, . . . , 11) each are Exclusive-NORed (EX-NORed,234) with corresponding part of the spread code114. The sum total (236) of such correlation operations is fed from the correlator16to the selector20as a correlation value116. The correlation value116output is “μl”, which is greatest, if all the virtual chip data106are identical with the spread code114, or is “0”, which is smallest, if none of the former is identical with the latter. In this manner, the correlation value output from the correlator16increases with an increase in the number of chips identical with the spread code114. This is also true with the other correlator18.

The mode select signal128input to the selector20is indicative of the regular mode also. Therefore, the selector20selects the correlation value116output from the correlator16and delivers it to the timing estimator22as a correlation value120. In response, the timing estimator22detects a peak value126around the symbol timing out of the correlation value120. The timing estimator22then feeds the timing of the peak value126thus detected to the symbol data decision circuit24as an optimum timing signal122for symbol data decision.

The accuracy of estimation of the timing signal122is dependent on the time resolution of the correlator16or18, i.e. the operational clock signal of the shift registers230constituting a correlator. More specifically, the correlators16and18each are allowed to sample the virtual chip data106more finely as the operational clock signal110or112, respectively, becomes higher in rate, so that the timing signal122detected by the timing estimator22is brought closer to the ideal timing. In this manner, by increasing the rate of an operational clock signal input to a correlator, it is possible to improve the demodulation characteristic and therefore to reduce, if radio channel quality is high enough to free chip data from errors, the rate of the operational clock signal without any noticeable influence on demodulation.

The correlation value120output from the selector20is fed to the symbol data decision circuit24as well and decided thereby. The result of decision is output from the symbol data decision circuit24as symbol data124.

The correlation peak value126detected by the timing estimator22is fed to the channel quality estimator26. The channel quality estimator26estimates radio channel quality on the basis of the peak value126and outputs the mode select signal128representative of the estimated radio channel quality.

Generally, in a de-spreading circuit for spread spectrum communication, the peak value output from a correlator rises when radio channel quality is high, or falls when it is low. Stated another way, the correlation value per se is representative of the degree of radio channel quality. In the illustrative embodiment, when the peak value126continuously indicates the spread ratio of “11” over a preselected number of symbols in the regular mode represented by the mode select signal128, the channel quality estimator26determines that radio channel quality is significantly high, and switches the mode select signal128from the regular mode to the power-saving mode.

The mode select signal126indicative of the power-saving mode renders the correlators16and18inactive and active, respectively. In response, the correlator18uses the spread code115to determine the correlation of the virtual chip data106. More specifically, as shown inFIG. 3, all the 1+8×(m−1) stages232of the shift register230are operated in the power-saving mode so as to sample the virtual chip data106at an eight times higher chip rate. In the correlator18, eleven chips of the virtual chip data stored in the “1+8×(n−1)”-th stage of the shift register230(n being 1, 2, . . . , 11) each are EX-NORed (234) with corresponding part of the spread code115in the same manner as in the correlator16. The sum total (236) of the correlation operations is fed from the correlator18to the selector20as a correlation value118.

The selector20selects the correction value118in response to the mode select signal128indicative of the power-saving mode and outputs the correction value118as a correlation value120.

On the other hand, when a correlation peak value126smaller than the preselected lower limit or threshold is detected while the mode select signal128output from the channel quality estimator26is indicative of the power-saving mode, the channel quality estimator switches the mode select signal128from the power-saving mode to the regular mode.

As stated above, in the illustrative embodiment, the channel quality estimator26determines a correlation peak value126to estimate radio channel quality, and then selects either one of the regular mode and power-saving mode to be indicated by the mode select signal128in accordance with the radio channel quality. Therefore, either one of the correlators16and18different in operational clock from each other can be selected in response to the mode select signal128. This successfully accomplishes de-spreading with an optimum operational clock and adequate current consumption matching with instantaneous radio channel quality.

The illustrative embodiment has been shown and described on the assumption that the spread ratio is eleven times and that the sampling frequencies for a single symbol assigned to the regular mode and power-saving mode are sixteen times and eight times, respectively. If desired, the illustrative embodiment may be modified to select a sampling frequency for one symbol as low as, e.g. four times so as to further promote power consumption. Further, the number of modes available with the illustrative embodiment may be increased to implement more delicate control.

Reference will be made toFIG. 4for describing an alternative embodiment of the present invention. InFIG. 4, parts and elements like those shown inFIG. 1are designated by identical reference numerals, and a detailed description thereof will not be made in order to avoid redundancy. As shown, a de-spreading device, generally200, is also adapted to estimate radio channel quality by the channel quality estimator26on the basis of the correlation peak value126to output the mode select signal128in accordance with the estimated radio channel quality.

In the illustrative embodiment, the de-spreading device200includes a variable frequency divider202, which is adapted to divide the frequency of the master or reference clock signal108in response to the mode select signal128output from the channel quality estimator26for thereby generating an operational clock signal212. A correlator204is provided to determine the correlation of the virtual chip data106in response to the operational clock signal212output from the variable frequency divider202.

More specifically, in the illustrative embodiment, the variable frequency divider202divides the frequency of the master clock signal108selectively by a number, NA or NB, in response to the mode select signal128. If the divider ratio NA is set to be greater than the other divider ratio NB, then the ratios NA and NB should preferably be assigned to the regular and power-saving modes, respectively.

The correlator204is responsive to the operational clock signal212to determine the correlation of the virtual chip data106output from the comparator12by use of a spread code214for thereby outputting a correlation value120. Particularly, in the illustrative embodiment, the correlator204is selectively operable in the regular or power-saving mode in response to the mode select signal128, i.e. adequately operable at a clock frequency matching with the operational mode. The system may preferably adapted to interlock the mode switching thus effected in the correlator204to the division ratio switching effected in the variable frequency divider202.

A specific operation of the alternative embodiment will be described hereinafter on the assumption that the correlator204is implemented by 1+k×(m−1) consecutive stages232of the shift register230. Again, the number of chips mallocated to a single symbol, i.e. the spread ratio is assumed to be “11”. Further, the clock frequency is assumed to be, in the regular mode, sixteen times as high as the chip rate, i.e. k=16, and, in the power-saving mode, eight times as high as the same, i.e. k=8.FIGS. 5 and 6conceptually show the operating conditions of the correlator204to hold in the regular and power-saving modes, respectively. As shown, the correlator204is implemented by one hundred and sixty-one consecutive stages of the shift register230.

First, the comparator12compares the detection signal102with the preselected threshold value104. The comparator12then outputs virtual chip data106which is ONE if the detection signal102is greater than or equal to the threshold value104, or ZERO otherwise, as stated earlier. The virtual chip data106are fed to the correlator204. At this instant, the variable frequency divider202divides the frequency of the master clock signal108in accordance with the mode indicated by the mode select signal128. Because the mode select signal128is initially indicative of the regular mode, the frequency divider202feeds the correlator204with an operational clock signal212whose frequency is sixteen times as high as the chip rate.

Subsequently, the correlator204responds to the mode select signal128indicative of the regular mode and uses the spread code214to determine the correlation of the virtual chip data106. More specifically, as shown inFIG. 5, all the 1+k×(m−1) consecutive stages232of the shift register230of the correlator204are enabled in the regular mode in order to sample the virtual chip data106at a frequency sixteen times as high as the chip rate, thereby calculating a correlation between eleven values stored in the “1+16×(n−1)” shift register stages232(n being 1, 2, . . . , 11) and the spread code214. The correlation thus calculated is output as a correlation value120. The correlation value120is “11” if the virtual chip data106all are identical with the corresponding spread code214, or “0” if none of the former is identical with the latter. In this manner, the correlation value120output from the correlator204increases with an increase in the number of chips identical with the spread code214.

The timing estimator22, receiving the correlation value120output from the correlator204, detects a peak value126appearing around a symbol timing symbol by symbol and feeds the peak value126to the channel quality estimator26. The timing estimator22delivers the timing at which the peak value appears to the symbol data decision circuit24as an optimum timing signal122. The correlation value120is fed to the symbol data decision circuit24as well. The symbol data decision circuit24decides the correlation value120in response to the optimum timing signal122output from the timing estimator22and then outputs the correction value120as symbol data124.

The channel quality estimator26estimates radio channel quality on the basis of the correlation peak value126and then switches the operation mode represented by the mode select signal128to one indicative of the estimated radio channel quality. More specifically, when the peak value126continuously indicates the spread ratio of “11” over a preselected number of symbols in the regular mode represented by the mode select signal128, the channel quality estimator26determines that radio channel quality is significantly high, and switches the mode select signal128from the regular mode to the power-saving mode. The mode select signal128thus indicative of the power-saving mode is delivered to the variable frequency divider202and correlator204. In response, the variable frequency divider202feeds to the correlator204an operational clock signal212whose frequency is eight times as high as the chip rate.

The correlator204receives the mode select signal128indicative of the power-saving mode, and uses the spread code214to determine the correlation of the virtual chip data106. More specifically, as shown inFIG. 6, in the power-saving mode, the first to the “1+8×(m−1)”-th stages232of the shift register230are all enabled while the remaining shift register stages232aare disenabled. Consequently, the correlator204samples the virtual chip data106at a frequency eight times as high as the chip rate, calculates a correlation between eleven values stored in the “1+8×(n−1)” shift register stages232(n being 1, 2, . . . , 11) and the spread code214, and then outputs a correlation value120representative of the correlation thus calculated.

On the other hand, if a correlation peak value126smaller than the preselected lower limit or threshold is detected when the mode select signal128output from the channel quality estimator26is indicative of the power-saving mode, then the channel quality estimator26switches the mode select signal128from the power-saving mode to the regular mode.

As stated above, in the illustrative embodiment, the channel quality estimator26determines a correlation peak value126to estimate channel quality and then selects either one of the regular mode and power-saving mode to be indicated by the mode select signal128in accordance with the channel quality. The variable frequency divider202can switch the operational clock signal in response to the mode select signal128and cause the correlator204to vary the operating condition of the shift registers included therein

The illustrative embodiment may also be modified to select a mode having any other sampling frequency for a single symbol that further promotes power consumption. Alternatively, the number of modes available with the illustrative embodiment may be increased to implement more delicate control. In any case, the circuit scale of the illustrative embodiment is determined by the number of shift registers enabled in a mode in which the sampling frequency is highest, so that the number of modes can be increased without scaling up the entire circuitry. More specifically, because the maximum sampling frequency is so determined as to satisfy required reception sensitivity, the circuit scale substantially does not increase even if the number of modes is increased.

In summary, in a de-spreading device of the present invention selectively operable in a regular or power-saving mode, a correlator samples, in the power-saving mode, virtual chip data with a high-frequency operational clock in order to determine a correlation value, thereby bringing the timing of symbol data decision estimated from the peak value of the correlation value closer to the ideal timing. The use of a high-frequency operational clock improves the demodulation characteristic of the de-spreading device. The operational clock can therefore be reduced in rate without affecting demodulation so long as radio channel quality is high enough to free chip data from errors.

More specifically, the frequency of the operational clock signal is lowered if radio channel quality represented by the correlation value is remarkably high, or raised if radio channel quality is lowered. This saves current to be consumed without affecting actual data demodulation and is therefore particularly desirable for the correlator of a de-spreading device including a number of shift registers. Further, the correlator in accordance with the invention will particularly effectively be applicable in terms of electric power consumption to the cases where a spread ratio is significantly large, i.e. numerous shift register stages are required, or a chip rate is high, i.e. an excessively high operational clock rate is required.

Moreover, in accordance with the present invention, a variable frequency divider is used to control not only the operational clock signal frequency but also the operating condition of shift registers constituting a single correlator. Stated another way, a single correlator is used operable with a plurality of operational clock signals, successfully scaling down the entire circuitry. This allows the number of operation modes to be increased without substantially scaling up the circuitry.

The entire disclosure of Japanese patent application No. 2004-217192 filed on Jul. 26, 2004, including the specification, claims, accompanying drawings and abstract of the disclosure is incorporated herein by reference in its entirety.

While the present invention has been described with reference to the particular illustrative embodiments, it is not to be restricted by the embodiments. It is to be appreciated that those skilled in the art can change or modify the embodiments without departing from the scope and spirit of the present invention.