Current mode data sensing and propagation using voltage amplifier

A method and a circuit for current mode data sensing and propagation by using voltage amplifier are provided. Example embodiments may include providing an output signal from a voltage amplifier in response to the voltage amplifier receiving an input signal. The method may include providing a current output signal from a voltage-to-current converter in response to the voltage-to-current converter receiving the output signal. The output signal may be used to drive a current sense amplifier.

TECHNICAL FIELD

Example embodiments relate generally to the technical field of microelectronics and their manufacture.

BACKGROUND

The speed of Very Large Scale Integration (VLSI) chips is increasingly limited by signal delay in long interconnect lines. In particular, with the progress of Integrated Circuit (IC) technology into the very deep submicron regime, signal propagation on long interconnects is becoming a major bottleneck in the performance of large circuits. For example, in memory devices, e.g., Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc., data signals collected may be propagated from individual memory arrays to input/output (I/O) pads wherein the data may be made accessible to users.

DETAILED DESCRIPTION

Example methods and circuits for current mode data sensing and propagation by using voltage amplifier will be described. In the following description, for purposes of explanation, numerous examples, having example-specific details are set forth in order to provide a thorough understanding of example embodiments. It will be evident, however, to one skilled in the art that the present examples may be practiced without these example-specific details.

Some example embodiments described herein may include providing an output signal from a voltage amplifier in response to the voltage amplifier receiving an input signal. The method may include providing a current output signal from a voltage-to-current converter in response to the voltage-to-current converter receiving the output signal. The output signal may be used to drive a current sense amplifier. Current-mode signal propagation used in this application is known to make major speed improvements as compared to voltage-mode signal transport techniques. The use of low-resistance current-signal circuits may play a key role in reducing the impedance level and the voltage swings on long interconnect lines.

FIG. 1is a high-level diagram illustrating an example embodiment of a device100for current mode data sensing and propagation by voltage amplifier. The device100may include a memory device consisting of one or more memory arrays110including multiple memory cells. The data stored in these memory cells may be accessed using one or more pairs of complementary digit lines122and124using the shown arrangement of a voltage amplifier (V.A.)125, a voltage-to-current (V to I) converter120, and a current sense amplifier (CSA)140. As shown inFIG. 1, the voltage amplifier125and the voltage-to-current converter120may be provided on the memory array110of a chip, while the current sense amplifier may be positioned in a periphery area130of the same chip.

According to an example embodiment, the voltage amplifier125may be configured to receive an input signal from the pair of complementary digit lines122and124. The voltage amplifier125may operatively provide an output signal to the voltage-to-current converter120. The voltage-to-current converter120may generate a current output signal based on the output signal received from the voltage amplifier125. The current sense amplifier140may be responsive to the current output signal received from the voltage-to-current converter120.

In example embodiments, the current output signal from the voltage-to-current converter120may propagate to the current sense amplifier140using the signal paths132and134. The signal paths132and134may also be referred to as global input/output (GIO) lines of memory array110. The output voltage of the current sense amplifier140may be coupled to the I/O pads of the memory device100through I/O lines142and144.

FIG. 2is illustrates an example embodiment of a flip-flop voltage amplifier210and a voltage-to-current converter240driving a current sense amplifier250. The schematic200may include a cross-coupled voltage amplifier210, a voltage-to-current converter240, and a current sense amplifier250. The voltage amplifier210may receive an input signal, which, in an example embodiment, may include a pair of complimentary input signals received from the I/O lines202and204. The voltage amplifier210is configured to operatively provide an output signal. The voltage-to-current converter240may generate a current output signal, based on the output signal received from the voltage amplifier210through the coupling lines232and234. The current sense amplifier250may be responsive to the current output signal received from the voltage-to-current converter240through the lines252and254. In an example embodiment, the current sense amplifier may be a cross-coupled amplifier.

In an example embodiment, the voltage amplifier210may include a flip-flop amplifier225formed by cross-coupled P-transistors220and222and cross-coupled N-transistors224and226. Gates of the P-transistor220and N-transistor224may be connected to the I/O line202through the control transistor212. In addition, the gates of the P-transistor222and the N-transistor226may be coupled to the I/O line204through the control transistor214. Transistors212and214, when turned off, may isolate the voltage amplifier210from the inputs (I/O lines202and204). Drains of the P-transistors220and222may be coupled to the supply voltage VCCand the sources of the N-transistor224and226may be connected to a ground through the coupling transistor230. According to an example embodiment, the voltage amplifier210may be replaced by an operational amplifier (op-amp).

According to an example embodiment, the voltage-to-current converter240may include a pair of source followers formed by N-transistors244and246, the drain of which may be connected to VCCthrough an enabling transistor242. In an example embodiment, all transistors used in the flip-flop voltage amplifier210and the voltage-to-current converter240may be implemented using Complementary Metal Oxide Semiconductor (CMOS) technology.

FIG. 3shows an example sense amplifier330coupled to memory cells315through complementary digit lines122and124(DL, DL*). The sense amplifier330and the memory cells315may be part of the memory array110ofFIG. 1, which are shown here to facilitate understanding of the formation of signals across the complementary digit lines122and124(DL and DL*) and the input/output lines10and10*. I/O lines202and204ofFIG. 2may be coupled to the complementary digit lines DL and DL* through column select transistors350and352. The signals on the complementary digit lines DL and DL* may be driven to their corresponding logic levels by the sense amplifier330. The sense amplifier may sense the data stored on memory cells coupled to the complementary digit lines DL and DL*.

In an example embodiment, the sense amplifier330may be connected via the sense lines S, S* to the complimentary digit lines DL and DL*. Also shown inFIG. 3are P-transistor340, an N-transistor342(coupled to PSENSE and NSENSE lines described below, respectively), column-select (CS) line, and column select transistors350and352. In operation, the complimentary digit lines DL and DL* are normally pre-charged to a level equal to one-half of the supply voltage, i.e., VCC/2. Each of the memory cells315may include an access transistor320and a memory cell capacitor310coupled between the transistor320and cell plate312. The cell plate312may be generally biased at one-half the supply voltage, i.e., VCC/2. A gate of each access transistor320may be coupled to respective word lines WL0or WL1.

The sense amplifier330may sense a voltage developed between the complimentary digit lines DL and DL* and then drive the complimentary digit lines to corresponding logic levels (VCCor ground). Sense amplifier330may use the cross-coupled P-transistors332and334and cross-coupled N-transistors336and338to couple the digit lines to VCCor the ground via P-transistor340and N-transistor342, respectively. The formation of the DL and DL* signals may be demonstrated by the waveforms shown inFIG. 4. The WL signal may represent the WL1signal applied to the gate of the access transistor320to enable coupling of the digit line DL* to the capacitor310. The capacitor310may store a voltage equal to either VCCor ground. The assumption here is that the capacitor310was at ground level at the time that the WL signal was applied. As soon as the NSENSE and the PSENSE lines turn on the N-transistors342and the P-transistor340, a separation between the DL and DL* starts to develop. The driving of the digit lines by the sense amplifier takes place by coupling the DL line to the VCCthrough ON P-transistors334and340and DL* line to the ground through the ON N-transistors338and342. However, the transition of these lines may be quite slow due to the large capacitances of the digit lines DL and DL*.

As the CS line is driven high, the column select transistors350and352couple the I/O lines (which are pre-charged to VCC) to the complementary digit lines DL and DL*, causing the I/O* line to be pulled towards the ground (seeFIG. 4, I/O line signals410and420).FIG. 4also shows the effect of the length of the CS pulse on the separation of digit lines DL and DL*. The separation of the DL and DL* towards their corresponding levels (in this case Vcc and ground) may be expedited by applying a short CS pulse (e.g., signal440), as compared to a long CS pulse (e.g., signal430). The slow transition is exacerbated in this example by the early application of the CS pulse as discussed below. The CS pulse may be applied early to accommodate an early column access such as an early read command.

Application of short CS pulses may not be plausible in the conventional voltage sensing and current propagating methods, because the separation between the I/O and I/O* lines may not be sufficient to prevent data disruption at the CSA250, due to noise on the lines. However, using long CS pulses may not be desirable, as it may cause the disruption of the digit lines and may also prolong the data access time (seeFIG. 5, CSA output signals550and560, for long CS pulse, and compare with signal570and580, for short CS pulse). Embodiments of the voltage amplifier assisted data sensing and propagation method make use of short CS pulses plausible, as demonstrated in the following discussion.

Returning toFIG. 2, in an example embodiment, the AMP FIRE line may be turned high (see signal520inFIG. 5) sometime after applying the CS pulse. Before turning the AMP FIRE line high, the coupling transistors212and214are in a conductive state, thereby, connecting the gates of P-transistor220and N-transistor224to the DL line, and the gates of P-transistor222and N-transistor226to the DL* line. That is to say, the gate of the N-transistor224is connected to a slightly higher voltage than the gate of the N-transistor226. Right after the AMP FIRE line is turned high, the coupling transistor230turns into a conductive state, connecting sources of the N-transistors224and226to ground. At this time, the coupling transistors212and214are in an OFF state, thereby, isolating the voltage amplifier210from the digit lines DL and DL*, and enabling the latch function of the amplifier210to force the I/O line (e.g., coupling line232) and the I/O* line (e.g., coupling line234) to VCCand ground, respectively. (See signals530and540ofFIG. 5).

The differential voltage developed between coupling lines232and234may then be converted to a differential current signal by the source followers formed by the transistors244and246, once the enabling transistor242is turned ON by a high level of ENABLE line (EN). In an example embodiment, the different current signal developed between the lines252and254may be transmitted to the current sense amplifier250, which may be positioned off the memory array110on the periphery area130near the I/O pads of the memory device100.

FIG. 6is a high-level flow diagram illustrating an example embodiment of a method600for voltage amplifier assistant current mode data sensing and propagation. The method600starts at operation610, where an output signal may be provided by the voltage amplifier210in response to receiving an input signal. In example embodiment, the input signal may include a pair of complimentary input signals received from I/O lines202and204. The output signals may also include a pair of complimentary output signals provided at coupling lines232and234. At operation620, the voltage-to-current converter240may be used to provide current output signal in response to receiving the output signal from the voltage amplifier210.

The current sense amplifier250may be driven, at operation630, using the current output signal from the voltage-to-current converter240. In an example embodiment, the voltage amplifier210and the voltage-to-current converter240may be part of the memory array110. Whereas, the current sense amplifier250may be rendered in the periphery, near an output pad of the memory device. In this example embodiment, the current output signal from the voltage-to-current converter240may be transmitted through the lines252and254to the current sense amplifier250.

FIG. 7is a high-level flow diagram illustrating an example embodiment of a method700for voltage amplifier assistant current mode data sensing and propagation. The method700may start at operation710where, as shown inFIG. 8, current signal from voltage-to-current converter820may be provided in response to receiving an input voltage. According to an example embodiment, the input voltage may include the voltage difference between the digit lines122and124ofFIG. 1.

At operation720, current sense amplifier830may be driven by the current signal provided by the voltage-to-current converter820to provide a voltage signal. At operation730, the voltage signal from the current sense amplifier may be amplified by voltage amplifier840to provide the voltage output signal. According to an example embodiment, the current sense amplifier830and the voltage amplifier840may be positioned between the memory array810and the I/O paths850. In an example embodiment, the voltage amplifier840may include latch function capabilities.

FIG. 9is a block diagram illustrating in an example embodiment a synchronous dynamic random access memory (SDRAM)900device using the current mode data sensing and propagation by using voltage amplifier ofFIG. 2or some other embodiment discussed above. The voltage amplifier assisted current mode data sensing and propagation ofFIG. 2or other embodiments can also be used in other DRAM devices and other memory devices, such as SRAM devices, FLASH memory devices, etc.

The operation of the SDRAM900is controlled by a command decoder904responsive to high-level command signals received on a control bus906. These high level command signals, which are typically generated by a memory controller (not shown inFIG. 9), are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, a column address strobe signal CAS*, and a data mask signal DM, in which the “*” designates the signal as active low.

The command decoder904may generate a sequence of command signals responsive to the high-level command signals to carry out the function (e.g., a read or a write) designated by each of the high-level command signals. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these command signals will be omitted.

The SDRAM900includes an address register912that receives row addresses and column addresses through an address bus914. The address bus914is generally coupled to a memory controller (not shown inFIG. 9). A row address is generally first received by the address register912and applied to a row address multiplexer918. The row address multiplexer918couples the row address to a number of components associated with either of two memory banks920,922depending upon the state of a bank address bit forming part of the row address. Associated with each of the memory arrays920,922is a respective row address latch926, which stores the row address, and a row decoder928, which decodes the row address and applies corresponding signals to one of the arrays920or922. The row address multiplexer918also couples row addresses to the row address latches926for the purpose of refreshing the memory cells in the arrays920,922. The row addresses are generated for refresh purposes by a refresh counter930, which is controlled by a refresh controller932. The refresh controller932is, in turn, controlled by the command decoder904.

After the row address has been applied to the address register912and stored in one of the row address latches926, a column address is applied to the address register912. The address register912couples the column address to a column address latch940. Depending on the operating mode of the SDRAM900, the column address is either coupled to the burst counter942, which applies a sequence of column addresses to the column address buffer944, starting at the column address output by the address register912, or through a burst counter942to a column address buffer944. In either case, the column address buffer944applies a column address to a column decoder948.

Data to be read from one of the arrays920,922is coupled to column circuitry950,952(i.e., sense amplifiers, I/O gating, Dynamic Queue Manager (DQM) & Wide-Pulse Blanking (WPB) mask logic, block write col./byte mask logic) for one of the arrays920,922, respectively. The column circuitry950,952may include, for each column of memory cells in the arrays920,922, and the sense amplifier330ofFIG. 3or a sense amplifier according to some other embodiment. The data bits developed by the sense amplifier330are then coupled to a data output register956. Data to be written to one of the arrays920,922are coupled from the data bus958through a data input register960. The write data are coupled to the column circuitry950,952, where they are transferred to one of the arrays920,922, respectively. A mask register964responds to a data mask DM signal to selectively alter the flow of data into and out of the column circuitry950,952, such as by selectively masking data to be read from the arrays920,922.

FIG. 10shows an embodiment of a computer system1000that may use the SDRAM900or some other memory device that uses the current mode data sensing and propagation by using voltage amplifier ofFIG. 2or some other example embodiment. The computer system1000may include a processor1002for performing various computing functions, such as executing specific software to perform specific calculations or tasks. The processor1002may include a processor bus1004that normally includes an address bus, a control bus, and a data bus. In addition, the computer system1000includes one or more input devices1014, such as a keyboard or a mouse, coupled to the processor1002to allow an operator to interface with the computer system1000.

Typically, the computer system1000also includes one or more output devices1016coupled to the memory controller1030; such output devices are typically a printer or a video terminal. One or more data storage devices1018are also typically coupled to the memory controller1030to store data or retrieve data from external storage media (not shown). Examples of typical storage devices1018may include hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). The processor1002is also typically coupled to a cache memory1026, which may usually be a SRAM and to the SDRAM900through a memory controller1030. The memory controller1030may include an address bus914(FIG. 10) to couple row addresses and column addresses to the DRAM900. The memory controller1030also includes a control bus that couples command signals to a control bus906of the SDRAM900. The external data bus958of the SDRAM900is coupled to the data bus of the processor1002, either directly or through the memory controller1030.

A method and a circuit for current mode data sensing and propagation by using voltage amplifier have been described. Although the present embodiments have been described, it will be evident that various modifications and changes may be made to these embodiments. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.