Magnetic memory cell structure with spin device elements and method of operating the same

A magnetic memory includes a plurality of memory cells and a data identification circuit. Each of the memory cells includes: a first bias node to which a first voltage is applied in data reading, the first voltage being a positive voltage; a second bias node to which a second voltage is applied in the data reading, the second voltage being a negative voltage having substantially the same absolute value as the first voltage; a connection node; a first spin device element connected between the first bias node and the connection node; and a second spin device element connected between the connection node and the second bias node. The first and second spin device elements operate differentially. The data identification circuit identifies data stored in each of the memory cells based on a polarity of a voltage generated on the connection node.

CROSS REFERENCE

This application claims priority of Japanese Patent Application No. 2015-075407, filed on Apr. 1, 2015, the disclosure which is incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a magnetic memory and a method of operating the same.

BACKGROUND ART

Magnetic memories are devices storing a data as the direction of a spontaneous magnetization (hereinafter, simply referred to as “magnetization”) of a magnetic layer. Extensive research and development activities have been conducted for magnetic memories, since they are expected as non-volatile memories with high speed operation, large capacity and reduced power consumption. Most typically, a magnetic memory is configured to achieve data reading by using a magnetoresistance effect, such as a tunnel magnetoresistance effect (TMR effect) and a giant magnetoresistance effect (GMR). An element including two magnetic layers and a spacer layer disposed therebetween (hereinafter, referred to as “spin device element”) exhibits a resistance depending on the relative direction of the magnetizations of the two magnetic layers due to the magnetoresistance effect. Most typically, a spin device element is placed into the “low resistance” state when the magnetizations of the two magnetic layers are directed in “parallel” and placed into the “high resistance” state when the magnetizations of the two magnetic layers are directed in “antiparallel”. In a magnetic memory which incorporates a spin device element in each memory cell, data stored in each memory cell can be identified from the signal level of a voltage or current signal generated so as to depend on the resistance value of the spin device element.

FIG. 1is a conceptual diagram illustrating an exemplary read operation of a magnetic memory. Discussed below is the case in which a spin device element is used as a memory cell101and the memory cell101can take two states: the “high resistance” state of a resistance value RHighand the “low resistance” state of a resistance value RLow, where RHigh>RLow.

Most typically, a read current Isenseis fed to the memory cell101when data reading from the memory cell101is performed. When the read current Isenseflows through the memory cell101, a read voltage Vmemoryis generated across the memory cell101. The read voltage Vmemory, which depends on the state of the memory cell101, that is, the resistance value of the memory cell101, can be used as a read signal obtained from the memory cell101. It is possible to identify the data stored in the memory cell101by comparing the read voltage Vmemorygenerated across the memory cell101with a predetermined reference voltage Vref, for example, with a sense amplifier102and providing a value as the “OUTPUT” shown inFIG. 1. In detail, the data stored in the memory cell101can be identified by comparing the read voltage Vmemorywith a reference voltage Vrefadjusted between voltages Vhighand VLow, where VHigh(=RHigh·Isense) is an expected value of the read voltage Vmemoryfor the high resistance state and VLow(=RLow·Isense) is an expected value of the read voltage Vmemoryfor the low resistance state. In the case when the “high resistance” state is associated with data “0” and the “low resistance” state is associated with data “1”, for example, the data stored in the memory cell101can be identified as data “0” if the read voltage Vmemoryis higher than the reference voltage Vrefand as data “1” if the read voltage Vmemoryis lower than the reference voltage Vref.

In the above-described read operation, the effective signal window for data identification based on the read signal obtained from the memory cell101is the difference ΔV between the voltages VHighand VLow. The data stored in the memory cell101can be identified more surely, as the signal window ΔV is increased.

Although the read voltage Vmemorydependent on the data stored in the memory cell101is obtained by feeding a given read current Isensethrough the memory cell101in the above-described operation, a read current dependent on the data stored in the memory cell101may be obtained in a read operation by applying a given read voltage across the memory cell101. In this case, the effective signal window of the read signal obtained from a memory cell101is the difference between a current flowing through the memory cell101placed into the “low resistance” state and the current flowing through the memory cell101placed into the “high resistance” state.

One current issue of the magnetic memory is the insufficiency in the effective signal window of the read signal obtained from the memory cell. Read signals obtained from memory cells have a distribution due to variations in the resistance value of the spin device elements (that is, the memory cells) and variations in the interconnection resistance of long interconnections. In the meantime, the signal level of a reference signal (the reference voltages Vrefobtained in the operation illustrated inFIG. 1) also have a distribution due to variations in the circuitry which generates the reference signal.FIG. 2illustrates one example of the distributions in the signal levels of the read signals and the reference signal.FIG. 2illustrates the distributions of the reference voltage Vref, the read voltage VHighobtained as the read voltage Vmemorywhen the memory cell101is placed in the high-resistance state, and the read voltage VLowobtained as the read voltage Vmemorywhen the memory cell101is placed in the low-resistance state. The horizontal axis of the graph illustrated inFIG. 2corresponds to the voltage V and the horizontal axis corresponds to the frequency N. As is understood fromFIG. 2, an insufficient effective signal window of the read signal undesirably causes read errors due to the overlap of the distributions of the read voltage VLowand the reference voltage Vrefand the overlap of the distributions of the read voltage VHighand the reference voltage Vref.

It is preferable to sufficiently increase the MR (magnetoresistance) ratio of a spin device element incorporated in a memory cell for achieving a sufficient signal window, because the effective signal window of the read signal obtained from the memory cell depends on the MR ratio of the spin device element. The current technology, however, does not offer an MR ratio for obtaining a sufficient signal window. It is technologically difficult to achieve an increase in the MR ratio, because it requires a remarkable breakthrough in materials used in spin device elements.

Related art documents are listed in the following. U.S. Patent Application Publication No. 2013/0121066 A1 discloses the structure of a memory cell which includes four spin device elements. U.S. Pat. No. 6,424,562 B1 discloses read/write architecture for a magnetoresistive random access memory (MRAM). U.S. Patent Application Publication No. 2013/0272059 A1 discloses a differential MRAM structure.

SUMMARY OF INVENTION

Therefore, an objective of the present invention is to increase an effective signal window of a read signal obtained from a memory cell of a magnetic memory. Other objectives and new features of the present invention would be understood by a person skilled in the art from the attached drawings and the following disclosure.

In an aspect of the present invention, a magnetic memory includes a plurality of memory cells and a data identification circuit. Each of the memory cells includes: a first bias node to which a first voltage is applied in data reading, the first voltage being a positive voltage; a second bias node to which a second voltage is applied in the data reading, the second voltage being a negative voltage having substantially the same absolute value as the first voltage; a connection node; a first spin device element connected between the first bias node and the connection node; and a second spin device element connected between the connection node and the second bias node. Each of the first and second spin device elements is configured to have a first magnetization which is reversible and to take a first or second state depending on a direction of the first magnetization. The resistance of each of the first and second spin device elements in a case when each of the first and second spin device elements is placed in the first state is higher than the resistance of each of the first and second spin device elements in a case when each of the first and second spin device elements is placed in the second state. The second spin device element is placed in the second state when the first spin device element is placed in the first state, and placed in the first state when the first spin device element is placed in the second state. The data identification circuit identifies data stored in each of the memory cells based on a polarity of a voltage generated on the connection node.

In another aspect of the present invention, a magnetic memory includes a memory cell and a data identification circuit. The memory cell includes: a first bias node to which a first voltage is applied in data reading from the memory cell; a second bias node to which a second voltage lower than the first voltage is applied in the data reading; a first connection node; a second connection node; a first spin device element connected between the first bias node and the first connection node; a second spin device element connected between the first connection node and the second bias node; a third spin device element connected between the first bias node and the second connection node; and a fourth spin device element connected between the second connection node and the second bias node. Each of the first to fourth spin device elements is configured to have a first magnetization which is reversible and to take selected one of first and second states depending on a direction of the first magnetization. The resistance of each of the first to fourth spin device elements in a case when each of the first to fourth spin device elements is placed in the first state is higher than the resistance of each of the first to fourth spin device elements in a case when each of the first to fourth spin device elements is placed in the second state. The first and fourth spin device elements have the same state selected from the first and second states and the second and third spin device elements have the same state selected from the first and second states. The second and third spin device elements are placed in the second state when the first and fourth spin device elements are placed in the first state, and placed in the first state when the first and fourth spin device elements are placed in the second state. The data identification circuit identifies data stored in the memory cell based on a third voltage generated on the first connection node and a fourth voltage generated on the second connection node.

In still another aspect of the present invention, a magnetic memory includes a memory cell and a data identification circuit. The memory cell includes: a first bias node to which a first voltage is applied in data reading from the memory cell; a second bias node to which a second voltage lower than the first voltage is applied in the data reading; a first connection node; a second connection node; a first spin device element connected between the first bias node and the first connection node; a first resistor element connected between the first connection node and the second bias node; a second resistor element connected between the first bias node and the second connection node; and a second spin device element connected between the second connection node and the second bias node. Each of the first and second spin device elements is configured to have a first magnetization which is reversible and to take selected one of first and second states depending on a direction of the first magnetization. The resistance of each of the first and second spin device elements in a case when each of the first and second spin device elements is placed in the first state is higher than the resistance of each of the first and second spin device elements in a case when each of the first and second spin device elements is placed in the second state. The first and fourth spin device elements have the same state selected from the first and second states. The data identification circuit identifies data stored in each of the memory cells based on a third voltage generated on the first connection node and a fourth voltage generated on the second connection node.

In still another aspect of the present invention, a method of operating a magnetic memory is provided, which includes a plurality of memory cells each comprising first and second bias nodes, a connection node, a first spin device element connected between the first bias node and the connection node, and a second spin device element connected between the connection node and the second bias node. Each of the first and second spin device elements is configured to have a first magnetization which is reversible and to take selected one of first and second states depending on a direction of the first magnetization. The resistance of each of the first and second spin device elements in a case when each of the first and second spin device elements is placed in the first state is higher than the resistance of each of the first and second spin device elements in a case when each of the first and second spin device elements is placed in the second state. The second spin device element is placed in the second state when the first spin device element is placed in the first state, and placed in the first state when the first spin device element is placed in the second state. The method includes:

applying a first voltage to the first bias node, the first voltage being a positive voltage;

applying a second voltage to the second bias node, the second voltage being a negative voltage having substantially the same absolute value as the first voltage; and

identifying data stored in each of the memory cells based on a polarity of a voltage generated on the connection node.

In still another aspect of the present invention, a method of operating a magnetic memory is provided, which includes a memory cell comprising: first and second bias nodes; first and second connection nodes; a first spin device element connected between the first bias node and the first connection node; a second spin device element connected between the first connection node and the second bias node; a third spin device element connected between the first bias node and the second connection node; and a fourth spin device element connected between the second connection node and the second bias node. Each of the first to fourth spin device elements is configured to have a first magnetization which is reversible and to take selected one of first and second states depending on a direction of the first magnetization. The resistance of each of the first to fourth spin device elements in a case when each of the first to fourth spin device elements is placed in the first state is higher than the resistance of each of the first to fourth spin device elements in a case when each of the first to fourth spin device elements is placed in the second state. The first and fourth spin device elements have the same state selected from the first and second states and the second and third spin device elements have the same state selected from the first and second states. The second and third spin device elements are placed in the second state when the first and fourth spin device elements are placed in the first state, and placed in the first state when the first and fourth spin device elements are placed in the second state. The method includes:

applying a first voltage to the first bias node;

applying a second voltage lower than the first voltage to the second bias node; and

identifying data stored in the memory cell based on a third voltage generated on the first connection node and a fourth voltage generated on the second connection node.

The present invention effectively increases the effective signal window of a read signal obtained from a memory cell of a magnetic memory.

DESCRIPTION OF PREFERRED EMBODIMENTS

The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art would appreciate that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposed. It would be appreciated that the same or similar components may be denoted by the same or corresponding reference numerals in the description of the preferred embodiments. It would be also appreciated that for simplicity and clarity of illustration, elements in the Figures have not necessary drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements.

(Configuration and Operation of Magnetic Memory)

FIG. 3illustrates an exemplary configuration of a magnetic memory10in one embodiment of the present invention. The magnetic memory10includes a plurality of memory cells1arrayed in row and columns, a row selection circuit3, a column selection circuit4, a sense amplifier circuit5and a write circuit6. The row selection circuit3selects a desired row of the memory cells1and the column selection circuit4selects a desired column of the memory cells1. In read and write operations, a memory cell1to be accessed is selected by the row selection circuit3and the column selection circuit4. The sense amplifier circuit5includes sense amplifiers12. In read operation, data stored in a selected memory cell1is identified by the corresponding sense amplifier12. The write circuit6feeds a write current to a selected memory cell1in a write operation.

FIG. 4Ais a circuit diagram illustrating a schematic configuration of each memory cell1of the magnetic memory10. In one embodiment, each memory cell1includes two spin device elements11Aand11B. It should be noted that the spin device elements11Aand11Bmay be collectively referred to as the spin device elements11if they are not distinguished from each other.

FIG. 4Bis a sectional view illustrating an exemplary structure of each spin device element11. In the present embodiment, each spin device element11includes a reference layer21, a spacer layer22and a recording layer23. The reference layer21and the recording layer23are opposed to each other across the spacer layer22. In the structure illustrated inFIG. 4B, the spacer layer22is coupled with the upper surface of the reference layer21and the recording layer23is coupled with the upper surface of the spacer layer22. It should be noted that the positions of the reference layer21and the recording layer23may be exchanged.

The reference layer21and the recording layer23, which are both configured to exhibit a magnetization, include at least one magnetic film. The spacer layer22is formed of non-magnetic material. The magnetization direction of the referent layer21is fixed, while the magnetization direction of the recording layer23is reversible. In one embodiment, the reference layer21and the recording layer23both have perpendicular magnetic anisotropy. In this case, the reference layer21is formed so that the magnetization thereof is fixed in a film thickness direction, and the recording layer23is formed so that the magnetization thereof is reversible between the film thickness directions. Illustrated inFIG. 4Bis the structure in which the magnetization of the reference layer21is fixed in the upward direction (+Z direction) and the magnetization of the recording layer23is reversible between the upward and downward directions (+Z and −Z directions). It should be noted however that the reference layer21and the recording layer23may have in-plane magnetic anisotropy instead.

The reference layer21and the recording layer23may be formed of an elementary substance of magnetic metal, such as iron (Fe), cobalt (Co) and nickel (Ni), or a ferromagnetic alloy including at least one of these magnetic metals, for example. The reference layer21and the recording layer23may be formed of magnetic metal or alloy doped with one or more non-magnetic elements. Non-magnetic elements which may be contained in the reference layer21and the recording layer23include boron, carbon, nitrogen, oxygen, aluminum, silicon, titanium, vanadium, chromium, manganese, copper, zinc, zirconium, niobium, molybdenum, ruthenium, rhodium, palladium, silver, hafnium, tantalum, tungsten, iridium, platinum and gold.

In one embodiment, the spacer layer22may be formed of a dielectric film having such a thin thickness that a tunnel current can flow through the spacer layer22. In this case, the spin device element11operates as a TMR (tunnel magnetoresistance) element that exhibits a TMR effect. To obtain a sufficiently large TMR effect, it is preferable that the spacer layer22is formed of, for example, magnesium oxide (MgO), aluminum oxide (AlOx) or the like. Alternatively, the spacer layer22may be formed of oxide, nitride or oxynitride of magnesium (Mg), aluminum (Al), silicon (Si), zirconium (Zr), hafnium (Hf), tantalum (Ta) or the like.

The spacer layer22may be formed of a metal conductor to reduce the resistance of the spin device element11. In this case, the spin device element11is configured as a spin valve element that exhibits a giant magnetoresistance (GMR) effect. To achieve a sufficiently large GMR effect, the spacer layer22may be formed of non-magnetic metal, such as copper (Cu), gold (Au), silver (Ag) and aluminum (Al) or an alloy of these non-magnetic metals. A composite spacer layer that includes an oxide matrix and metal columns penetrating through the oxide matrix in the thickness direction may be used as the spacer layer22. In this case, the oxide matrix of the composite spacer layer may be formed of aluminum oxide and the metal columns, which penetrates through the oxide matrix in the thickness direction, may be formed of copper (Cu). The spacer layer22preferably has a thickness of 1 to 3 nm.

Each spin device element11thus structured is allowed to have two states: the “low resistance” state and the “high resistance” state. In detail, a spin device element11is placed into the “low resistance” state when the magnetizations of the reference layer21and the recording layer23are directed in “parallel” and the spin device element11is placed into the “high resistance” state when the magnetizations of the reference layer21and the recording layer23are directed in “antiparallel”. This implies that the spin device element11functions as a variable resistor element exhibiting a resistance value depending on the relative direction of the reference layer21and the recording layer23.

Although the simplest structure of the spin device element11is illustrated inFIG. 4B, the structure of the spin device element11may be variously modified. For example, the reference layer21may be formed of a film stack including a magnetic film and an antiferromagnetic film that fixes the magnetization of the magnetic film. The recording layer23may be formed of a film stack including multiple magnetic layers and one or more non-magnetic films each providing ferromagnetic coupling between adjacent two of the magnetic layers.

Referring back toFIG. 4A, the two spin devices elements11Aand11Bare connected in series between a node Nbias1and a node Nbias2in the memory cell1, where the nodes Nbias1and Nbias2are first and second bias nodes to which bias voltages are applied in a read operation. In detail, the spin device element11Ais connected between the node Nbias1and a node N1and the spin device element11Bis connected between the node N1and the node Nbias2, where the node N1is a connection node which provides electrical connection between the spin devices elements11Aand11B.

The memory cell1illustrated inFIG. 4Ais configured to offer two allowed states with two spin device elements11and to thereby store one bit data. In the configuration illustrated inFIG. 4A, as illustrated inFIG. 5A, each memory cell1stores one-bit data, correlating one of the first and second states defined below with data “0” and the other with data “1”:

First state: a state in which the spin device element11Ais placed in the “low resistance” state and the spin device element11Bis placed in the “high resistance” state, and

Second state: a state in which the spin device element11Ais placed in the “high resistance” state and the spin device element11Bis placed in the “low resistance” state.

FIG. 5Aillustrates two allowed states of the memory cell1in the case when the first state is correlated with data “0” and the second state is correlated with data “1”.

Data reading from a memory cell1configured as illustrated inFIG. 4Ais achieved by determining the polarity of the voltage V1generated on the node N1with a data identification circuit, e.g. a sense amplified12, in the state in which a positive bias voltage +Vbiasis applied to the node Nbias1and a negative bias voltage −Vbiasis applied to the node Nbias2. It should be noted that the bias voltages applied to the nodes Nbias1and Nbias2have substantially the same absolute value (magnitude) but have opposite polarities. In an actual implementation, the absolute values of the bias voltages applied to the nodes Nbias1and Nbias2may slightly differ from each other due to manufacturing process variations or other reasons; however, the bias voltages applied to the nodes Nbias1and Nbias2are adjusted to have at least substantially the same absolute value. In the example illustrated inFIG. 5A, in which the first state is correlated with data “0” and the second state is correlated with data “1”, the data stored in the memory cell1is identified as data “0” when the polarity of the voltage V1is positive and as data “1” when the polarity of the voltage V1is negative.

The memory cell configuration illustrated inFIG. 4Aeffectively offers a large signal window even when the MR ratios of the spin device elements11are not so large, due to the differential operation using the two spin device elements11. Accordingly, as illustrated inFIG. 5B, the reliability of data reading from the memory cell1can be effectively improved even when the voltage V1on the node N1varies on some level. Note that the signal window is denoted by symbol ΔV1inFIG. 5B. Additionally, the memory cell configuration illustrated inFIG. 4Aallows identifying the data stored in the memory cell1with a simple method; the data identification can be achieved by determining the polarity of the voltage V1.

FIG. 6is a circuit diagram illustrating the schematic structure of each memory cell1of the magnetic memory10in another embodiment of the present invention. In the present embodiment, each memory cell1includes four spin device elements11. It should be noted that, suffixes “A1”, “A2”, “B1” and “B2” may be used in the following, if the spin device elements11are distinguished from one another.

The four spin device elements11forms a bridge circuit in each memory cell1of the magnetic memory10in the present embodiment. More specifically, the spin device element11A1is connected between a node Nbias1and a node N1and the spin device element11B1is connected between the node N1and a node Nbias2, where the node Nbias1is a first bias node to which a first voltage is applied in a read operation and the node Nbias2is a second bias node to which a second voltage lower than the first voltage is applied in the read operation. In one embodiment, in the read operation, a positive bias voltage +Vbiasis applied to the node Nbias1while the node Nbias2is grounded. The node N1is a first connection node which provides an electrical connection between the spin device elements11A1and11B1. Furthermore, the spin device element11B2is connected between the node Nbias1and a node N2and the spin device element11A2is connected between the node N2and the node Nbias2, where the node N2is a second connection node which provides an electrical connection between the spin device elements11B2and11A2.

The memory cell1illustrated inFIG. 6is configured to offer two allowed states with four spin device elements11and to thereby store one bit data.FIG. 7illustrates the two allowed states of the memory cell1in the present embodiment. In the present embodiment, each memory cell1stores one-bit data, correlating one of the first and second states defined below with data “0” and the other with data “1”:

First state: a state in which the spin device elements11A1and11A2are placed in the “low resistance” state and the spin device elements11B1and11B2are placed in the “high resistance” state, and

Second state: a state in which the spin device elements11A1and11A2are placed in the “high resistance” state and the spin device elements11B1and11B2are placed in the “low resistance” state.FIG. 7illustrates two allowed states of the memory cell1in the case when the first state is correlated with data “0” and the second state is correlated with data “1”. It should be noted that the spin device elements11A1and11A2are a pair of spin device elements which are always placed in the same state and the spin device elements11B1and11B2are another pair of spin device elements which are always placed in the same state. It should be also noted that the state of the spin device elements11A1and11A2is always different from the state of the spin device elements11B1and11B2.

Data reading from a memory cell1configured as illustrated inFIG. 6is achieved by comparing the voltages V1and V2generated on the nodes N1and N2by using a data identification circuit, e.g. a sense amplifier12, in the state in which a first voltage is applied to the node Nbias1and a second voltage lower than the first voltage is applied to the node Nbias2. In one example, the voltages V1and V2generated on the nodes N1and N2are compared by the sense amplifier12in the state in which a positive bias voltage Vbiasis applied to the node Nbias1and the node Nbias2is grounded. When a first voltage is applied to the node Nbias1and a second voltage lower than the first voltage is applied to the node Nbias2(for example, when a positive bias voltage +Vbiasis applied to the node Nbias1with the node Nbias2grounded), a read current Isense1flowing through the spin device elements11A1and11B1and a read current Isense2flowing through the spin device elements11A2and11B2are generated and the voltages V1and V2are generated by the read currents Isense1and Isense2on the nodes N1and N2, respectively. In the example illustrated inFIG. 7, in which the first state is correlated with data “0” and the second state is correlated with data “1”, the data stored in the memory cell1is identified as data “0” when the voltage V1is higher than voltage V2and as data “1” when the voltage V1is lower than voltage V2.

The above-described memory cell1, in which the four spin device elements11form a bridge circuit generating a pair of differential signals, effectively offers a large signal window ΔV even when the MR ratios of the spin device elements11are not so large. Accordingly, as illustrated inFIG. 8, the reliability of data reading from the memory cell1can be effectively improved even when the voltages V1and V2on the nodes N1and N2vary on some level.

Additionally, when the four spin device elements11are arranged closed to each other, this effectively suppresses the influences of variations in the properties of the spin device elements11. Even when a manufacturing process of the magnetic memory suffers from manufacturing process variations, the influences of the manufacturing process variations on the voltages V1and V2on the nodes N1and N2can be effectively suppressed, because spin device elements placed close to each other exhibit reduced property variations.

FIG. 9Ais a circuit diagram illustrating a modification of the memory cell1in the present embodiment. In the configuration of the memory cell1illustrated inFIG. 9A, two spin device elements11and two resistor elements13with a fixed resistance form a half bridge circuit. It should be noted that, suffixes “A1”, “A2”, “B1” and “B2” may be used in the following, if the resistor elements13are distinguished from one another.

The configuration of the memory cell1illustrated inFIG. 9Ais derived from that of the memory cell1illustrated inFIG. 6by replacing the spin device elements11B1and11B2with resistor elements with a fixed resistance value. More specifically, the memory cell1illustrated inFIG. 9Aincludes two spin device elements11A1,11A2and two resistor elements13B1and13B2having a fixed resistance value. The spin device element11A1is connected between the node Nbias1and the node N1and the resistor element13B1is connected between the node N1and the node Nbias2. Furthermore, the resistor element13B2is connected between the node Nbias1and the node N2and the spin device element11A2is connected between the node N2and the node Nbias2. As described above, the node Nbias1is a first bias node to which a first voltage is applied in a read operation and the node Nbias2is a second bias node to which a second voltage lower than the first voltage is applied in the read operation.

Preferably, the resistance value Rxof the resistor elements13B1and13B2is in the range between the resistance values RHighand RLow, where RHighis the resistance value of the spin device element11A1and11A2in the case when the spin device element11A1and11A2are placed in the “high resistance” state, and RLowthe resistance value of the spin device element11A1and11A2in the case when the spin device element11A1and11A2are placed in the “low resistance” state. More preferably, the resistance value Rxof the resistor elements13B1and13B2is adjusted to the average value of the resistance values RHighand RLow. In an actual implementation, it is preferable that the design value of the resistance value Rxof the resistor elements13B1and13B2is determined as the average of the design values of the resistance values RHighand RLowof the spin device elements11A1and11B2, since the resistance values RHighand RLowactually vary due to manufacturing process variations.

The memory cell1illustrated inFIG. 9Ais configured to offer two allowed states with two spin device elements11and to thereby store one bit data.FIG. 10illustrates the two allowed states of the memory cell1configured as illustrated inFIG. 9A. The memory cell1configured as illustrated inFIG. 9Astores one-bit data, correlating one of the first and second states defined below with data “0” and the other with data “1”:

First state: a state in which the spin device elements11A1and11A2are placed in the “low resistance” state, and

Second state: a state in which the spin device elements11A1and11A2are placed in the “high resistance” state.

FIG. 10illustrates two allowed states of the memory cell1in the case when the first state is correlated with data “0” and the second state is correlated with data “1”. It should be noted that the spin device elements11A1and11A2are a pair of spin device elements which are always placed in the same state.

Data reading from a memory cell1configured as illustrated inFIG. 9Ais achieved by comparing the voltages V1and V2generated on the nodes N1and N2by using a data identification circuit, e.g. a sense amplifier12, in the state in which a first voltage is applied to the node Nbias1and a second voltage lower than the first voltage is applied to the node Nbias2. In one embodiment, the voltages V1and V2generated on the nodes N1and N2are compared by the sense amplifier12in the state in which a positive bias voltage +Vbiasis applied to the node Nbias1and the node Nbias2is grounded. In the example illustrated inFIG. 10, in which the first state is correlated with data “0” and the second state is correlated with data “1”, the data stored in the memory cell1is identified as data “0” when the voltage V1is higher than voltage V2and as data “1” when the voltage V1is lower than voltage V2.

The memory cell1illustrated inFIG. 9A, in which the two spin device elements11and the two resistor elements13form a bridge circuit generating a pair of differential signals, effectively offers a large signal window ΔV even when the MR ratios of the spin device elements11are not so large. Accordingly, the reliability of data reading from the memory cell1can be effectively improved even when the voltages V1and V2on the nodes N1and N2vary on some level.

FIG. 9Bis a circuit diagram illustrating another modification of the memory cell1in the present embodiment. Also in the configuration of the memory cell1illustrated inFIG. 9B, two spin device elements11and two resistor elements13with a fixed resistance form a half bridge circuit.

The configuration of the memory cell1illustrated inFIG. 9Bis derived from that of the memory cell1illustrated inFIG. 6by replacing the spin device elements11A1and11A2with resistor elements with a fixed resistance value. More specifically, the memory cell1illustrated inFIG. 9Bincludes two spin device elements11B1,11B2and two resistor elements13A1and13A2having a fixed resistance value. The resistor element13A1is connected between the node Nbias1and the node N1and the spin device element11B1is connected between the node N1and the node Nbias2. Furthermore, the spin device element11B2is connected between the node Nbias1and the node N2and the resistor element13A2is connected between the node N2and the node Nbias2.

The memory cell1illustrated inFIG. 9Bis also configured to offer two allowed states with four spin device elements11and to thereby store one bit data, as is the case with that illustrated inFIG. 9A. The memory cell1configured as illustrated inFIG. 9Bstores one-bit data, correlating one of the first and second states defined below with data “0” and the other with data “1”:

First state: a state in which the spin device elements11B1and11B2are placed in the “high resistance” state, and

Second state: a state in which the spin device elements11B1and11B2are placed in the “low resistance” state.

It should be noted that the spin device elements11B1and11B2are a pair of spin device elements which are always placed in the same state.

Data reading from a memory cell1configured as illustrated inFIG. 9Bis achieved by comparing the voltages V1and V2generated on the nodes N1and N2by using a data identification circuit, e.g. a sense amplifier12, in the state in which a first voltage is applied to the node Nbias1and a second voltage lower than the first voltage is applied to the node Nbias2, similarly to that from a memory cell1configured as illustrated inFIG. 9A. In one embodiment, the voltages V1and V2generated on the nodes N1and N2are compared by the sense amplifier12in the state in which a positive bias voltage +Vbiasis applied to the node Nbias1and the node Nbias2is grounded. When the first state is correlated with data “0” and the second state is correlated with data “1”, for example, the data stored in the memory cell1is identified as data “0” when the voltage V1is higher than voltage V2and as data “1” when the voltage V1is lower than voltage V2.

The memory cell1illustrated inFIG. 9A, in which the two spin device elements11and two resistor elements13form a bridge circuit generating a pair of differential signals, also offers a large signal window ΔV even when the MR ratios of the spin device elements11are not so large. Accordingly, the reliability of data reading from the memory cell1can be effectively improved even when the voltages V1and V2on the nodes N1and N2vary on some level.

In the following, a description is given of more specific configurations of the memory cells of the magnetic memory in the present embodiment. It should be noted that the memory cell configuration described below is designed to facilitate data writing into the memory cells.

FIG. 11Ais a diagram conceptually illustrating one example of the configuration of each memory cell1A, when the magnetic memory10of the present embodiment is configured as an STT-MRAM (Spin Transfer Torque Magnetoresistive Random Access Memory). In an STT-MRAM, a spin transfer torque is used in data writing into a memory cell. The configuration of the memory cell1A illustrated inFIG. 11Acorresponds to that illustrated inFIG. 4A. In the following, a description is given of the configuration of the memory cell1A illustrated inFIG. 11A.

The memory cell1A includes two spin device elements11Aand11B. Each of the spin device elements11includes a reference layer21, a spacer layer22and a recording layer23. The structure of the spin device elements11is as described above with reference toFIG. 4B.

The spin device elements11Aand11Bare formed on the upper surfaces of lower electrodes24Aand24B, respectively. In detail, the reference layers21of the spin device elements11Aand11Bare formed on the upper surfaces of the lower electrodes24Aand24B, respectively. In each of the spin device elements11Aand11B, the spacer layer22is formed on the upper surface of the reference layer21and the recording layer23is formed on the upper surface of the spacer layer22.

The lower electrode24Ais connected to a node Nbias1and the lower electrode24Bis connected to a node Nb1as2where the nodes Nbias1and Nbias2are bias nodes to which bias voltages are applied in read and write operations. The lower electrode24Afunctions as an interconnection which electrically connects the spin device element11Ato the node Nbias1and the lower electrode24Bfunctions as an interconnection which electrically connects the spin device element11Bto the node Nbias2.

An upper electrode25is coupled with the upper surfaces of the spin device elements11Aand11B. The upper electrode25, which functions as an interconnection that provides an electrical connection between the spin device elements11Aand11B, is a circuit component which corresponds to the node N1of the memory cell1illustrated inFIG. 4A.

As illustrated inFIG. 11B, the spin device elements11Aand11Bmay be electrically connected to each other via a lower electrode24. In this case, an upper electrode25Aformed on the upper surface of the spin device element11Ais connected to the node Nbias1, and an upper electrode25Bformed on the upper surface of the spin device element11Bis connected to the node Nbias2.

It should be noted that the positions of the reference layer21and the recording layer23may be exchanged in each spin device element11in both of the configurations illustrated inFIGS. 11A and 11B.

The memory cells1A illustrated inFIGS. 11A and 11B, similarly to the memory cell1illustrated inFIG. 4A, are configured to store one-bit data, correlating one of the first and second states defined below with data “0” and the other with data “1”:

First state: a state in which the spin device element11Ais placed in the “low resistance” state and the spin device element11Bis placed in the “high resistance” state, and

Second state: a state in which the spin device element11Ais placed in the “high resistance” state and the spin device element11Bis placed in the “low resistance” state.

It should be noted that, in the configurations illustrated inFIGS. 11A and 11B, the reference layers21of the two spin device elements11Aand11Bare connected to each other (seeFIG. 11B) or the recording layers23of the two spin device elements11Aand11Bare connected to each other (seeFIG. 11A). Such a connection aims at placing the memory cell1A into the first or second state by feeding a write current which flows between the node Nbias1and Nbias2. When a write current is caused to flow through the memory cell1A, one of the spin device elements11Aand11B, in which the directions of the write currents are different, is placed into the “high resistance” state and the other is placed into the “low resistance” state, since the direction into which the magnetization is directed in the magnetization reversal based on the spin transfer torque depends on the direction of the write current. In the configuration illustrated inFIG. 11A, for example, when a write current which flows from the node Nbias1to the node Nbias2is fed, the write current flows from the reference layer21to the recording layer23in the spin device element11Aand from the recording layer23to the reference layer21in the spin device element11B. This allows placing the memory cell1A into the first state defined above. When a write current is fed from the node Nbias2to the node Nbias1, the write current flows from the recording layer23to the reference layer21in the spin device element11Aand the write current flows from the reference layer21to the recording layer23in the spin device element11B. This allows placing the memory cell1A into the second state defined above. A person skilled in the art would appreciate it that this discussion also applies to the configuration illustrated inFIG. 11B.

Next, a description is given of data writing and reading into and from the memory cell1A illustrated inFIG. 11A.FIGS. 12A and 12Billustrate data writing into the memory cell1A illustrated inFIG. 11A. It should be noted thatFIGS. 12A and 12Billustrates a write operation in the case when the first state is correlated with data “0” and the second state is correlated with data “1”. As described above, the first state is the state in which the spin device element11Ais placed in the “low resistance state” and the spin device element11Bis placed in the “high resistance” state” and the second state is the state in which the spin device element11Ais placed in the “high resistance” state and the spin device element11Bis placed in the “low resistance” state.

In data writing, bias voltages are applied to the nodes Nbias1and Nbias2depending on data to be written into the memory cell1A to generate a write current IWbetween the nodes Nbias1and Nbias2.

In detail, to write data “0”, a voltage lower than the voltage on the node Nbias2is applied to the node Nbias1as illustrated inFIG. 12A. In the operation illustrated inFIG. 12A, the node Nbias2is grounded and a negative bias voltage −Vbiasis applied to the node Nbias1. This causes a write current to flow from the node Nbias2to the node Nbias1, directing the magnetizations of the reference layer21and the recording layer23in “parallel” in the spin device element11A, and in “antiparallel” in the spin device element11B. As a result, the memory cell1A is placed into the first state, in which the spin device element11Ais in the “low resistance” state and the spin device element11Bis in the “high resistance” state.

To write data “1”, on the other hand, a voltage higher than the voltage on the node Nbias2is applied to the node Nbias1as illustrated inFIG. 12B. In the operation illustrated inFIG. 12B, the node Nbias2is grounded and a positive bias voltage Vbiasis applied to the node Nbias1. This causes a write current to flow from the node Nbias1to the node Nbias2, directing the magnetizations of the reference layer21and the recording layer23in “antiparallel” in the spin device element11Aand in “parallel” in the spin device element11B. As a result, the memory cell1A is placed into the second state, in which the spin device element11Ais in the “high resistance” state and the spin device element11Bis in the “low resistance” state.

FIG. 13illustrate data reading from the memory cell1A illustrated inFIG. 11A. In data reading, a positive bias voltage +Vbiasis applied to the node Nbias1and a negative bias voltage −Vbiasis applied to the node Nbias2. It should be noted that the bias voltages applied to the nodes Nbias1and Nbias2have substantially the same absolute value (magnitude) but have opposite polarities. When the positive bias voltage +Vbiasis applied to the node Nbias1and the negative bias voltage −Vbiasis applied to the node Nbias2, a read current IRflowing through the spin device elements11Aand11Bis generated and a voltage V1is generated by the read current IRon the upper electrode25, which corresponds to the node N1.

The data stored in the memory cell1A is identified in the same way as the memory cell1illustrated inFIG. 4A. When the first state is correlated with data “0” and the second state is correlated with data “1”, for example, the data stored in the memory cell1A is identified as data “0” if the polarity of the voltage V1is positive and as data “1” if the polarity of the voltage V1is negative.

FIG. 14Aschematically illustrates another example of the configuration of each memory cell1B, when the magnetic memory10of the present embodiment is configured as an STT-MRAM. The configuration of the memory cell1B illustrated inFIG. 14Acorresponds to that illustrated inFIG. 6. In the following, a description is given of the configuration of the memory cell1B illustrated inFIG. 14A.

The memory cell1B includes four spin device elements11A1,11A2,11B1,11B2and switching elements SW1and SW2. Each of the four spin device elements11includes a reference layer21, a spacer layer22and a recording layer23. The configuration of each spin device element11is as described above with reference toFIG. 4B.

The spin device elements11A1,11A2,11B2and11B2are formed on the upper surfaces of lower electrodes24A1,24A2,24B1and24B2, respectively. In detail, the reference layers21of the spin device elements11A1,11A2,11B2and11B2are formed on the upper surfaces of the lower electrodes24A1,24A2,24B1and24B2, respectively. In each of the spin device elements11A1,11A2,11B2and11B2, the spacer layer22is formed on the reference layer21and the recording layer23is formed on the spacer layer22.

The lower electrode24A1is connected to a node N11and the lower electrode24B2is connected to a node N12, where the nodes N11and N12are connection nodes used to establish electrical connections with the spin device elements11A1and11B2. In other words, the lower electrode24A1functions as an interconnection which electrically connects the spin device element11A1to the node N11and the lower electrode24B2functions as an interconnection which electrically connects the spin device element11B2to the node N12. The node N11is connected to the node Nbias1and the node N12is connected to the switching element SW1. As described layer, the node Nbias1is a bias node to which a bias voltage is applied in data writing and data reading.

The lower electrodes24B1and24A2are commonly connected to a node N13. In other words, the lower electrodes24B1and24A2function as interconnections which electrically connect the spin device elements11B1and11A2to the node N13. The node N13is a connection node which provides an electrical connection between the spin device elements11B1and11A2.

An upper electrode251is coupled with the upper surfaces of the spin device elements11A1and11B1, and an upper electrode252is coupled with the upper surfaces of the spin device elements11A2and11B2. The upper electrode251, which functions as an interconnection which provides an electrical connection between the spin device elements11A1and11B1, is a component corresponding to the node N1illustrated inFIG. 6. The upper electrode252, which functions as an interconnection which provides an electrical connection between the spin device elements11A2and11B2, is a component corresponding to the node N2illustrated inFIG. 6.

The switching element SW1connects the node N12to selected one of the nodes Nbias1and Nbias3, where the node Nbias3is a bias node which is kept at a predetermined voltage; in the present embodiment, the node Nbias3is grounded. As described later, the node Nbias3is used in write operations. The switching element SW2electrically connects or disconnects the node N13to or from the node Nbias2, where the node Nbias2is a bias node which kept at a predetermined voltage level; in the present embodiment, the node Nbias2is grounded. As described later, the node Nbias2is used in read operations. The switching elements SW1and SW2are used to switch the memory cell1B between data writing and data reading. In data writing, the switching element SW1is placed into a state in which the node N12is connected to the node Nbias3(that is, the circuit ground), and the switching element SW2is placed into the off-state. In data reading, on the other hand, the switching element SW1is placed into a state in which the node N12is connected to the node Nbias1, and the switching element SW2is placed into the on-state.

The memory cell1B illustrated inFIG. 14A, similarly to the memory cell1illustrated inFIG. 6, is configured to store one-bit data, correlating one of the first and second states defined below with data “0” and the other with data “1”:

First state: a state in which the spin device elements11A1and11A2are placed in the “low resistance” state and the spin device elements11B1and11B2are placed in the “high resistance” state, and

Second state: a state in which the spin device elements11A1and11A2are placed in the “high resistance” state and the spin device elements11B1and11B2are placed in the “low resistance” state.

It should be noted that the spin device elements11A1and11A2are always placed in the same state, and the spin device elements11B1and11B2are always placed in the same state. It should be also noted that the state of the spin device elements11A1and11A2is always different from the state of the spin device elements11B1and11B2.

In the configuration illustrated inFIG. 14A, the spin device elements11A1,11B1,11A2and11B2are serially connected in this order between the nodes N11and N12. It should be noted that a connection between adjacent two spin device elements11is achieved by connecting the reference layers21of the adjacent two spin device elements11each other or by connecting the reference layers23of the adjacent two spin device elements11each other. In detail, the recording layers23of the spin device elements11A1and11B1are electrically connected to each other via the upper electrode251and the recording layers23of the spin device elements11B2and11A2are electrically connected to each other via the upper electrode252. Furthermore, the reference layers21of the spin device elements11B1and11A2are electrically connected via the lower electrode24B1, the node N13and the lower electrode24A2.

As thus described, when a write current is caused to flow through the memory cell1B, in which the reference layers21or recording layers23of adjacent two spin device elements21are connected to each other, the directions of the write currents flowing between the reference layers21and the recording layers23via the space layers22are different between the spin device elements11A1and11B1. One of the spin device elements11A1and11B1, in which the directions of the write currents are different, is placed into the “high resistance” state and the other is placed into the “low resistance” state, since the direction into which the magnetization is directed in the magnetization reversal based on the spin transfer torque depends on the direction of the write current. This discussion also applies to the spin device elements11A2and11B2. The above-described electrical connections allow placing one of adjacent two spin device elements11into the “high resistance” state and the other into the “low resistance state”.

Accordingly, the memory cell1B, configured as described above, can be placed into the first or second state by causing a write current to flow between the node N11and N12. When a write current which flows from the node N11to the node N12is generated, for example, the write current flows from the reference layer21to the recording layer23in the spin device elements11A1and11A2, and the write current flows from the recording layer23to the reference layer21in the spin device elements11B1and11B2. This allows placing the memory cell1B into the first state. When a write current which flows from the node N12to the node N11is generated, on the other hand, the write current flows from the recording layer23to the reference layer21in the spin device elements11A1and11A2, and the write current flows from the reference layer21to the recording layer23in the spin device elements11B1and11B2. This allows placing the memory cell1B into the second state described above.

It should be noted that the positions of the reference layer21and the recording layer23may be exchanged in each of the spin device elements11, as illustrated inFIG. 14B. Also in this case, with respect to every adjacent two spin device elements11, the reference layers21of the adjacent two spin device elements11are connected to each other, or the recording layers23of the adjacent two spin device elements11are connected to each other. In detail, also in the configuration illustrated inFIG. 14B, the reference layers21of the spin device elements11A1and11B1are electrically connected to each other via the upper electrode251and the reference layers21of the spin device elements11A2and11B2are electrically connected to each other via the upper electrode252. Furthermore, the recording layers23of the spin device elements11B1and11A2are electrically connected to each other via the lower electrode24B1, the node N13and the lower electrode24A2. A person skilled in the art would appreciate that the memory cell1B illustrated inFIG. 14Bcan be also placed into the first or second state by feeding a write current flowing between the nodes N11and N12.

Although the memory cell1B illustrated inFIG. 14Ais configured so that the node N11is connected to the node Nbias1and the switch element SW1connects the node N12to selected one of the node Nbias1and Nbias3, the memory cell1B may be configured so that the node N12is connected to the node Nbias1and the switch element SW1connects the node N11to selected one of the node Nbias1and Nbias3, as illustrated inFIG. 14C. Also in this case, the positions of the reference layer21and the recording layer23may be exchanged in each of the spin device elements11as illustrated inFIG. 14D.

In an alternative embodiment, as illustrated inFIG. 14E, the memory cell1B may be configured so that the spin device elements11A1and11B1are electrically connected to each other via a lower electrode241and the spin device elements11B2and11A2are electrically connected to each other via a lower electrode242. In this case, an upper electrode25A1formed on the upper surface of the spin device element11A1is connected to the node N11is connected, and an upper electrode25B2formed on the upper surface of the spin device element11B2is connected to the node N12. Also, upper electrodes25B1and25A2respectively formed on the upper surfaces of the spin device elements11B1and11A2are commonly connected to the node N13. It should be noted that, also in this configuration, with respect to every adjacent two spin device elements11, the reference layers21of the adjacent two spin device elements11are connected to each other, or the recording layers23of the adjacent two spin device elements11are connected with each other.

As illustrated inFIG. 14F, the memory cell1B may be configured so that the node N12is connected to the node Nbias1and the switching element SW1connects the node N11to selected one of the nodes Nbias1and Nbias3, also in the case when the spin device elements11A1and11B1are electrically connected to each other via the lower electrode241and the spin device elements11B2and11A2are electrically connected to each other via the lower electrode242. It should be noted that the positions of the reference layer21and the recording layer23may be exchanged in each spin device element11, also in the configurations illustrated inFIGS. 14E and 14F.

Next, a description is given of data writing and reading into and from the memory cell1B illustrated inFIG. 14A.FIGS. 15A and 15Billustrate data writing into the memory cell1B illustrated inFIG. 14A. It should be noted thatFIGS. 15A and 15Billustrates a write operation in the case when the first state is correlated with data “0” and the second state is correlated with data “1”. As described above, the first state is the state in which the spin device elements11A1and11A2are placed in the “low resistance state” and the spin device elements11B1and11B2are placed in the “high resistance” state” and the second state is the state in which the spin device elements11A1and11A2are placed in the “high resistance” state and the spin device elements11B1and11B2are placed in the “low resistance” state.

In data writing, the switching element SW1is placed into the state in which the node N12is connected to the node Nbias3and the switching element SW2is placed into the off-state. Furthermore, a bias voltage depending on write data is applied to the node Nbias1to generate a write current IWwhich flows between the nodes N11and N12.

In detail, to write data “0”, as illustrated inFIG. 15A, a bias voltage lower than the voltage on the node Nbias3is applied to the node Nbias1. In the present embodiment, in which the node Nbias3is grounded, a negative bias voltage −Vbiasis applied to the node Nbias1. This allows the write current to flow from the node N12to the node N11, resulting in that the magnetizations of the reference layer21and the reference layer23are directed in “parallel” in each of the spin device elements11A1and11A2and directed in “antiparallel” in each of the spin device elements11B1and11B2. This operation places the memory cell1B into the first state, in which the spin device elements11A1and11A2are placed in the “low resistance” state and the spin device elements11B1and11B2are placed in the “high resistance” state. It should be noted that a pair of the “low resistance” state and the “high resistance” state is generated in this operation, because the write current flows in different directions in the adjacent spin device elements11A1and11B1. The same applies to the spin device elements11A2and11B2.

To write data “1”, on the other hand, as illustrated inFIG. 15B, a bias voltage higher than the voltage on the node Nbias3is applied to the node Nbias1. In the present embodiment, in which the node Nbias3is grounded, a positive bias voltage +Vbiasis applied to the node Nbias1. This allows the write current to flow from the node N11to the node N12, resulting in that the magnetizations of the reference layer21and the reference layer23are directed in “antiparallel” in each of the spin device elements11A1and11A2and directed in “parallel” in each of the spin device elements11B1and11B2. This operation places the memory cell1B into the second state, in which the spin device elements11A1and11A2are placed in the “high resistance” state and the spin device elements11B1and11B2are placed in the “low resistance” state.

FIGS. 16A and 16Billustrates data reading from the memory cell1B illustrated inFIG. 14A. In data reading, the switching element SW1is placed into a state in which the node N12is connected to the node Nbias1, and the switching element SW2is placed into the on-state. Furthermore, a bias voltage higher than the voltage on the node Nbias2is applied to the node Nbias1. In the present embodiment, in which the node Nbias2is grounded, a positive bias voltage +Vbiasis applied to the node Nbias1. This operation generates a read current Isense1flowing through the spin device elements11A1and11B1and a read current Isense2flowing through the spin device elements11B2and11A2. The read currents Isense1and Isense2generate a voltage V1on the upper electrode251, which corresponds to the node N1, and a voltage V2on the upper electrode252, which corresponds to the node N2.

The data stored in the memory cell1B is identified in the same way as the memory cell1illustrated inFIG. 6. When the voltage V1generated on the upper electrode251is higher than the voltage V2generated on the upper electrode252, as illustrated inFIG. 16A, the data stored in the memory cell1B is identified as data “0”, because the spin device elements11A1and11A2are placed in the “low resistance” state and the spin device elements11B1and11B2are placed in the “high resistance” state. When the voltage V2generated on the upper electrode252is higher than the voltage V1generated on the upper electrode251, as illustrated inFIG. 16B, the data stored in the memory cell1B is identified as data “1”, because the spin device elements11A1and11A2are placed in the “high resistance” state and the spin device elements11B1and11B2are placed in the “low resistance” state.

Data reading and data writing can be similarly achieved when the configurations illustrated inFIGS. 14B to 14Fare used instead. In data writing, the switching element SW1is placed into the state in which the node N11or N12is connected to the node Nbias3(that is, the circuit ground) and the switching element SW2is placed into the off-state. Furthermore, a bias voltage depending on write data is applied to the node Nbias1to generate a write current IWwhich flows between the nodes N11and N12. In data reading, the switching element SW1is placed into a state in which the node N11or N12is connected to the node Nbias1, and the switching element SW2is placed into the on-state.

FIG. 17Ais a plan view illustrating one example of the configuration of a memory cell10in the case when the magnetic memory10in the present embodiment is configured to achieve data writing with a current-induced magnetic field, andFIG. 17Bis a side view illustrating the configuration of the memory cell10. Also in the configuration illustrated inFIG. 17A, the memory cell10includes four spin device elements11A1,11A2,11B1and11B2. When data writing is achieved with a current-induced magnetic field, a write current line26is additionally provided close to each memory cell1C. The write current line26is disposed to extend in the X-axis direction. The spin device elements11A1and11A2are positioned opposed to the spin device elements11B1and11B2across the write current line26. More specifically, the spin device elements11A1and11A2are positioned shifted in the +Y direction (a first direction) from the write current line26and the spin device elements11B1and11B2are positioned shifted in the −Y direction (a second direction opposite to the first direction) from the write current line26. This arrangement allows generating such a magnetic field that the magnetizations of the recoding layers23of the spin device elements11A1and11A2and those of the recoding layers23of the spin device elements11B1and11B2are directed in opposite directions, by using only one write current line26. Note that the spin device element11A2is positioned shifted from the spin device element11A1in the +X direction, and the spin device element11B1is positioned shifted from the spin device element11B2in the +X direction.

FIGS. 17C and 17Dare cross-sectional views illustrating the structure of the memory cell10on sections A-A and B-B indicated inFIG. 17A, respectively. As illustrated inFIGS. 17C and 17D, the spin device elements11A1and11A2are formed on the upper surfaces of the lower electrodes24A1and24A2, respectively, and the spin device elements11B1and11B2are formed on the upper surfaces of the lower electrodes24B1and24B2, respectively. In detail, the reference layers21of the spin device elements11A1,11A2,11B1and11B2are formed on the upper surfaces of the lower electrodes24A1,24A2,24B1and24B2, respectively. In each of the spin device elements11A1,11A2,11B1and11B2, the spacer layer22is formed on the upper surface of the reference layer21, and the recording layer23is formed on the upper surface of the spacer layer22. The upper electrodes25A1,25A2,25B1and25B2are formed on the upper surfaces of the recording layers23of the spin device elements11A1,11A2,11B1and11B2, respectively.

Data writing into the memory cell1C illustrated inFIGS. 17A to 17Dcan be achieved by generating a current-induced magnetic field with a write current Iw flowing through the write current line26. The direction of the write current Iw is determined depending on data to be written into the memory cell1C.

Discussed below is the case when a first state is correlated with data “0” and a second state is correlated with data “1”, where the first state is a state in which the spin device elements11A1and11A2are placed in the “low resistance” state and the spin device elements11B1and11B2are placed in the “high resistance” state and the second state is a state in which the spin device elements11A1and11A2are placed in the “high resistance” state and the spin device elements11B1and11B2are placed in the “low resistance” state.

To write data “0”, as illustrated inFIG. 18A, a write current Iw is generated which flows through the write current line26in the +X direction. When the write current Iw flows in the +X direction, a current-induced magnetic field having a +Z component is applied to the recording layers23of the spin device elements11A1and11A2and a current-induced magnetic field having a −Z component is applied to the recording layers23of the spin device elements11B1and11B2. This allows directing the magnetizations of the recording layers23of the spin device elements11A1and11A2in the +Z direction to place the spin device elements11A1and11A2into the “low resistance” state and directing the magnetizations of the recording layers23of the spin device elements11B1and11B2in the −Z direction to place the spin device elements11B1and11B2into the “high resistance” state. As thus described, data “0” can be written into the memory cell1C by feeding a write current Iw flowing in the +X direction.

To write data “1”, on the other hand, as illustrated inFIG. 18B, a write current Iw is generated which flows through the write current line26in the −X direction. When the write current Iw flows in the −X direction a current-induced magnetic field having a −Z component is applied to the recording layers23of the spin device elements11A1and11A2and a current-induced magnetic field having a +Z component is applied to the recording layers23of the spin device elements11B1and11B2. This allows directing the magnetizations of the recording layers23of the spin device elements11A1and11A2in the −Z direction to place the spin device elements11A1and11A2into the “high resistance” state and directing the magnetizations of the recording layers23of the spin device elements11B1and11B2in the +Z direction to place the spin device elements11B1and11B2into the “low resistance” state. As thus described, data “1” can be written into the memory cell1C by generating a write current Iw flowing in the −X direction.

FIG. 19is a perspective view conceptually illustrating electrical connections among the spin device elements11A1,11A2,11B1and11B2in the memory cell1C for achieving data reading. The electrical connections among the spin device elements11A1,11A2,11B1and11B2in the memory cell1C are similar to those in the memory cell1illustrated inFIG. 6.

In detail, the lower electrode24A1and24B2, which are coupled with the spin device elements11A1and11B2, respectively, are connected to the node Nbias1and the lower electrode24A2and24B1, which are coupled with the spin device elements11A2and11B1, respectively, are connected to the node Nbias2. The upper electrode24A1and24B1, which are connected coupled with the spin device elements11A1and11B1, respectively, are commonly connected to the node N1, and the upper electrode24B2and24A2, which are coupled with the spin device elements11A2and11B2, respectively, are commonly connected to the node N2.

Data reading from the memory cell1C is achieved by comparing the voltages V1and V2generated on the nodes N1and N2by using a sense amplifier12, in the state in which a voltage higher that the voltage on the node Nbias2is applied to the node Nbias1. In the read operation illustrated inFIG. 19, a positive bias voltage +Vbiasis applied to the node Nbias1with the node Nbias2grounded. When the positive bias voltage +Vbiasis applied to the node Nbias1, a read current Isense1flowing through the spin device elements11A1and11B1and a read current Isense2flowing through the spin device elements11A2and11B2are generated and the voltages V1and V2are generated by the read currents Isense1and Isense2on the nodes N1and N2, respectively. When the first state is correlated with data “0” and the second state is correlated with data “1”, for example, the data stored in the memory cell1is identified as data “0” if the voltage V1is higher than voltage V2and as data “1” if the voltage V1is lower than voltage V2.

(Integration of Spin Device Element on Deformable Base Plate)

One known issue in commercialization of magnetic memories is a difficulty in concurrently satisfying these three requirements: data read sensitivity, data stability and data write power (electric power consumed in a data writing operation). This issue involves three types of conflicts. When the MR (magnetoresistance) ratio is increased to improve the data read sensitivity and to thereby reduce the error rate in read operations, for instance, this makes it difficult to reduce the data write power required for generating a spin transfer torque. The opposite also applies. As for the relation between the data write power and data stability, the data stability increases proportionally with the magnetic anisotropy energy KuV (where Ku is the magnetic anisotropy constant and V is the volume) while the data write power also increases proportionally with the magnetic anisotropy energy KuV. Accordingly, the improvement in the data stability inevitably increases the data write power. As thus discussed, although it is possible to individually satisfy each of the above-described three requirements with the current technologies, it is difficult to satisfy the three requirements at the same time with the current technologies, due to the trade-off relationship. If a conflict between two of the three above-described requirements is resolved, this would effectively contribute commercialization of magnetic memories.

To address the above-described trade-off relationship, as one approach to relieve a conflict between the data stability and data write power in a magnetic memory, the inventor has been studying a technique in which spin device elements of a memory cell are integrated on a deformable base plate and a bending mechanism which bends the deformable base plate is also integrated. Further details are disclosed in U.S. patent application Ser. No. 14/728,651, filed on Jun. 2, 2015, the disclosure of which is incorporated herein by reference. A mechanism which uses a piezoelectric effect or a mechanism which uses a force exerted between a pair of capacitor electrodes may be used as the bending mechanism to bend the deformable base plate.

In a magnetic memory thus configured, a mechanical stress is applied to each spin device element when the deformable base plate is bent and this stress generates a strain in each spin device element. When the strain is generated in each spin device element, the magnetization direction of the recording layer of each spin device element is tilted from the original magnetization direction, which is determined depending on the magnetic anisotropy of the recording layer, due to a magnetostrictive effect. The magnetostrictive effect is knowns as a phenomenon in which the strain of a magnetic body varies depending on the magnetization status and the magnetization status of a magnetic body varies depending on the strain applied to the magnetic body. Strictly, the latter effect should be referred to as an inverse magnetostrictive effect; however, these effects are collectively referred to as the magnetostrictive effect in the present application, since the magnetostrictive effect in the broad sense usually means to encompass both of the magnetostrictive effect and inverse magnetostrictive effect in the narrow sense. The magnetization of a recording layer is easily reversed in the state in which the magnetization direction of the recording layer is tilted from the original magnetization direction of the recording layer. By making use of this phenomenon, it is possible to achieve data writing with a reduced data write power, even if the recording layer of each spin device element is formed of material superior in the data stability. In the following, a description is given of embodiments in which spin device elements forming a memory cell are integrated on a deformable base plate.

FIG. 20is a plan view illustrating an example of the configuration of a memory cell array of a magnetic memory in one embodiment, andFIG. 21is a plan view illustrating the configuration of each block of the memory cell array illustrated inFIG. 20. Note that a block is one unit structure of the memory cell array and each block includes a plurality of memory cells as described later.FIGS. 20 and 21conceptually illustrate the configuration of the memory cell array and that of each block in the case when the magnetic memory of the present embodiment is configured as an STT-MRAM.

As illustrated inFIG. 20, the memory cell array includes blocks2arranged in rows and columns in the present embodiment. As illustrated inFIG. 21, each block2includes a plurality of memory cells1B. In the structure illustrated inFIGS. 20 and 21, each block2includes four memory cells1B. The configuration of each memory cell1B is basically similar to that illustrated in any ofFIGS. 14A to 14F, and therefore the memory cells included in each block2are denoted by the same reference numeral “1B”.

FIG. 22Ais a cross-sectional view illustrating the structure of each block2on section C-C indicated inFIG. 21,FIG. 22Bis a cross-sectional view illustrating the structure of each block2on section D-D indicated inFIG. 21, andFIG. 23is a perspective view illustrating the configuration of each block2. As illustrated inFIGS. 22A and 22B, each block2includes a deformable base plate33. The deformable base plate33is configured to be deformable so that the deformable base plate33can be bent. The deformable base plate33may be formed of silicon, silicon oxide, silicon nitride, silicon oxynitride or the like. Materials and processes used in a SON (Si-on-nothing) technology may be used for the formation of the deformable base plate33. The deformable base plate33preferably has a thickness of 200 nm to 5 μm, for example.

The lower electrodes24A1,24A2,24B1and24B2are formed on the upper surface of the deformable base plate33and the spin device elements11A1,11A2,11B1and11B2are formed on the upper surfaces of the lower electrodes24A1,24A2,24B1and24B2, respectively. The upper electrodes25A1,25A2,25B1and25B2are formed on the upper surfaces of the spin device elements11A1,11A2,11B1and11B2, respectively. The upper electrodes25A1and25B1are electrically connected to each other via an interconnection and, the upper electrodes25B2and25A2are electrically connected to each other via an interconnection. It would be understood that such electrical connections correspond to the configuration in which the upper electrode251is coupled with the upper surfaces of the spin device elements11A1and11B1and the upper electrode252is coupled with the upper surfaces of the spin device elements11B2and11A2, as illustrated inFIGS. 14A to 14F.

Piezoelectric layers34and35are coupled with both of the side surfaces (the surfaces facing the X-axis directions) of the deformable base plate33. The piezoelectric layers34and35are formed of piezoelectric material, such as AlN, lead zirconate titanate (PZT) and zirconium oxide (ZrOx). As described later, the deformable base plate33is bent by using a piezoelectric effect occurring in the piezoelectric layers34and35. The piezoelectric layers34and35are coupled and fixed on the upper surface of a fixture base32. The fixture base32is coupled with the upper surface of a semiconductor substrate31in which a transistor circuit are integrated.

Electrode layers36and37are coupled with the surfaces of the piezoelectric layers34and35opposing to the surfaces coupled to the side surfaces of the deformable base plate33. An additional electrode layer (not illustrated) on which a potential difference is generated with respect to the electrode layer36may be coupled with the piezoelectric layer34. Similarly, an additional electrode layer (not illustrated) on which a potential difference is generated with respect to the electrode layer37may be coupled with the piezoelectric layer35. Although the additional electrode layers on which potential differences are respectively generated with respect to the electrode layers36and37are not illustrated inFIGS. 22A and 22B, the additional electrode layers may be also used as the lower electrodes24connected to the spin device elements11or other electrodes.

In the present embodiment, the deformable base plate33is formed so that at least one of the lower surface (that is, the surface opposed to the surface on which the spin device elements11are formed) and the upper surface (that is, the surface on which the spin device elements11are formed) of the deformable base plate33faces a “space which is not filled with solid substance”. The “space which is not filled with solid substance” referred to herein may be filled with fluid, including gas (such as air, nitrogen) and liquid. Alternatively, the “space which is not filled with solid substance” may be vacuumed. The structure in which at least one of the lower and upper surfaces of the deformable base plate33faces the “space which is not filled with solid substance” allows the deformable base plate33to be deformed with a sufficiently large displacement. This is effective for generating a sufficiently-large strain, that is, a magnetostrictive effect in the recording layer23of each spin device element11.

Referring back toFIG. 20, every two deformable base plates33of the blocks2adjacent to each other in the Y-axis direction are separated by a gap39in the present embodiment. The gap39is a space which is not filled with solid substance, as is the case with the space38.FIG. 24is a cross-sectional view schematically illustrating the structure on section E-E indicated inFIG. 20. Two deformable base plates33adjacent to each other in the Y-axis direction are opposed across the gap39. The gap39is formed to communicate with the space38. In this structure, two deformable base plates33adjacent to each other in the Y-axis direction are mechanically separated and this allows individually bending two deformable base plates33adjacent to each other in the Y-axis direction.

In the magnetic memory thus structured, the deformable base plate33can be bent by applying electric fields to the piezoelectric layers34and35with electrode layers coupled with the piezoelectric layers34and35(the electrode layers36,37and the additional electrode layers (not illustrated)). More specifically, when electric fields are applied to the piezoelectric layers34and35, strains are generated in the piezoelectric layers34and35due to the piezoelectric effect. A force is applied to the deformable base plate33due to the strains of the piezoelectric layers34and35, and thereby the deformable base plate33is bent. The conflict between the data stability and data write power is effectively relieved by feeding to the spin device elements11a write current Iw in the state in which the deformable base plate33is bent.

It should be also noted that substantially no current is generated (other than a leakage current and a temporary charging current) to bend the deformable base plate33in the structure of the magnetic memory illustrated inFIGS. 20 to 24in the present embodiment. In the structure of the magnetic memory illustrated inFIGS. 20 to 24, in which a piezoelectric effect is used to bend the deformable base plate33, it is not necessary to feed a current to bend the deformable base plate33. This is advantageous for reducing the data write power (electric power consumed in a data writing operation).

FIG. 25AtoFIG. 25Dare cross-sectional views illustrating an exemplary data write procedure into a memory cell1B of the memory cell array illustrated inFIGS. 20 to 24.FIG. 25Aillustrates the initial state of a selected memory sell1B into which a data is to be written. InFIG. 25A, the states of only the spin device elements11A1and11B1of the selected memory cell1B is illustrated. Discussed below is the case when the memory cell1B stores data “1” in the initial state. In this state, the spin device element11A1is placed in the “high resistance” state and the spin device element11B1is placed in the “low resistance” state. Although not illustrated inFIG. 25A, a person skilled in the art would understand that the spin device element11A2is placed in the “high resistance” state and the spin device element11B2is placed in the “low resistance” state.

As illustrated inFIG. 25B, the deformable base plate33is bent in data writing into the memory cell1B. As described above, the deformable base plate33can be bent by applying electric fields to the piezoelectric layers34and35with the electrode layers coupled with the piezoelectric layers34and35(that is, the electrode layers36,37and the additional electrode layers (not illustrated)). When the deformable base plate33is bent, a strain is generated in each of the spin device electrode11and the magnetization direction of the recording layer23of each spin device element11is tilted from the original magnetization direction of the recording layer23, which is determined by the magnetic anisotropy thereof, due to a magnetostrictive effect.

By tilting the magnetization direction of the recording layer23from the original magnetization direction, the recoding layer23is placed into a state in which the magnetization of the recoding layer23is easily reversible. This means that applying a strain to each spin device element11by bending the deformable base plate33allows temporarily placing each spin device element11into a state in which data stability is low. To apply a sufficiently-large strain to each spin device element11, it is effective to increase the displacement (bending amount) of the deformable base plate33. It is also preferable to increase the magnetostriction of the recording layer23to enhance the magnetostrictive effect.

It should be noted that the structure in which at least one of the lower and upper surfaces of the deformable base plate33faces a “space which is not filled with solid substance” in the present embodiment allows deforming the deformable base plate33with a sufficiently-large displacement. The “space which is not filled with solid substance” referred to herein may be filled with fluid, including gas (such as air, nitrogen) and liquid. Alternatively, the space which is not filled with solid substance may be vacuumed.

More specifically, as illustrated inFIGS. 22A and 22B, the lower surface of the deformable base plate33(the surface of the deformable base plate33opposite to the surface on which the spin device elements11are formed) partially faces the space38which is not filled with solid substance, and the spin device elements11are disposed opposed to the space38across the deformable base plate33. This structure is especially advantageous for increasing the displacement of the deformable base plate33and thereby increasing the strain generated in each spin device element11. It should be noted that the portion of the upper surface of the deformable base plate33on which the spin device elements11are not formed may be covered with a dielectric film for protection.

As illustrated inFIG. 25C, a write current Iw for writing a desired data is generated which flows through the spin device elements11of the selected memory cell1B in the state in which the deformable base plate33bent. Since the magnetostrictive effect is a uniaxial effect rather than a unidirectional effect, it is impossible to direct the magnetization direction of the recording layer23of each spin device element11(which corresponds to data “0” or “1) into the desired direction only with the magnetostrictive effect; the magnetostrictive effect exerted in the recording layer23only achieves an effect of tilting the magnetization of the recording layer23by about 90 degree from the direction of the magnetic anisotropy of the recording layer23at the maximum. The write current Iw corresponding to the desired data is fed to each spin device element11to limit the magnetization direction of the recording layer23to only one direction.

Illustrated inFIG. 25Cis the operation for writing data “0”. The write current Iw is generated in such a direction that the magnetizations of the reference layers21and the recording layers23are directed in “parallel” in the spin device elements11A1and11A2and those of the reference layers21and the recording layers23are directed in “antiparallel” in the spin device elements11B1and11B2. This allows placing the selected memory cell1B into the first state in which the spin device elements11A1and11A2are placed in the “low resistance” state and the spin device elements11B1and11B2are placed in the “high resistance” state.

This is followed by stopping bending the deformable base plate33. This completes the data writing.FIG. 25Dillustrates the state of the selected memory cell1B after the data writing is completed. InFIG. 25D, the magnetizations of the recording layers23of the spin device elements11A1and11B1are illustrated as being directed in the opposite directions to those in the original state (initial state) illustrated inFIG. 25A.

Since the data writing is assisted by the magnetostrictive effect caused by the strain applied to each spin device element11, the above-described operation effectively achieves data writing with a reduced data write power, even if magnetic material exhibiting superior data stability is used as the recording layer23of each spin device element11in the memory cell1B. In other words, the magnetic memory and data writing method in the present embodiment advantageously relieves a conflict between the data stability and data write power.

Although the mechanism illustrated inFIGS. 20 to 24uses a piezoelectric effect to bend the deformable base plate33, various other mechanisms may be used to bend the deformable base plate33. For example, the deformable base plate33may be bent by using a force exerted between a pair of capacitor electrodes.FIGS. 26A and 26Bare cross-sectional views illustrating the configuration of each block2in this case.

In the configuration illustrated inFIGS. 26A and 26B, a capacitor electrode41is partially embedded in the fixture base32. The capacitor electrode41includes a flat plate section41aand a contact section41b. The lower surface of the flat plate41afaces a space38A which is not filled with solid substance.

The deformable base plate33is coupled on the upper surface of the fixture base32. The deformable base plate33is opposed to the flat plate41aof the capacitor electrode41across a space38B which is not filled with solid substance. In other words, the lower surface of the deformable base plate33faces the space38B which is not filled with solid substance.

The deformable base plate33includes a dielectric layer42, a capacitor electrode layer43and a main body44. The dielectric layer42is coupled with the upper surface of the fixture base32and the capacitor electrode layer43is coupled with the upper surface of the dielectric layer42. The main body44is coupled with the upper surface of the capacitor electrode layer43. The capacitor electrode layer43is opposed to the flat plate section41aof the capacitor electrode41across the dielectric layer42and the space38B which is not filled with solid substance, and a capacitor is formed with the capacitor electrode41and the capacitor electrode layer43.

The lower electrodes24A1,24B1,24A2and24B2are formed on the upper surface of the deformable base plate33(that is, the upper surface of the main body44) and the spin device elements11A1,11B1,11A2and11B2are formed on the upper surfaces of the lower electrodes24A1,24B1,24A2and24B2, respectively. The structure of each spin device element11is as described above with reference toFIG. 4B. The upper electrodes25A1,25B1,25A2and25B2are formed on the upper surfaces of the recording layers23of the spin device elements11A1,11B1,11A2and11B2, respectively.

This structure allows bending the deformable base plate33by applying a voltage between the capacitor electrode41and the capacitor electrode layer43. In detail, when a voltage is applied between the capacitor electrode41and the capacitor electrode layer43, an electric field is generated between the capacitor electrode41and the capacitor electrode layer43, and this electric field works on charges generated on the surface of the capacitor electrode layer43to generate an attracting force which pulls the capacitor electrode layer41towards the capacitor electrode43, that is, an attracting force which pulls the deformable base plate33towards the capacitor electrode41. Since the lower surface of the deformable base plate33is only partially coupled with the fixture base32and faces the space38B which is not filled with solid substance, the deformable base plate33is bent by the force attracting the deformable base plate33towards the capacitor electrode41.

It should be noted here that, in the structure illustrated inFIGS. 26A and 26B, a part of the lower surface of the deformable base plate33faces the space38B which is not filled with solid substance. The structure in which the surface of the deformable base plate33opposed to the surface on which the spin device elements11is formed faces the space38B which is not filled with solid substance effectively enlarges the displacement of the deformable base plate33.

It should be noted that substantially no current is generated (other than a leakage current and a temporary charging current) to bend the deformable base plate33also in the structure illustrated inFIGS. 26A and 26B. The structure illustrated inFIGS. 26A and 26Beliminates the need for feeding a current to bend the deformable base plate33, since the deformable base plate33is bent with a force exerted between capacitor electrodes. This effectively reduces the data write power (that is, the power consumed in a write operation).

In an alternative embodiment, the memory cells1B illustrated inFIGS. 11A and 11B, which each includes two spin device elements11, may be integrated on the deformable base plate33.FIG. 27is a plan view illustrating the configuration of each block2in a magnetic memory thus structured andFIG. 28is a cross-sectional view illustrating the structure of each block2on section F-F indicated inFIG. 27.

The lower electrodes24Aand24Bare formed on the upper surface of the deformable base plate33and the spin device elements11Aand11Bare formed on the upper surfaces of the lower electrodes24Aand24B. The upper electrode25is coupled with the upper surfaces of the spin device elements11Aand11B. The upper electrode25functions as a connection node which provides an electrical connection between the spin device elements11Aand11B.

Also in the structure illustrated inFIGS. 27 and 28, data writing is achieved by feeding a write current through each of the spin device elements11Aand11Bof a selected memory cell1A in the state in which the deformable base plate33is bent. More specifically, the deformable base plate33is bent when a desired data is written into the selected memory cell1A. As described above, the deformable base plate33can be bent by applying electric fields to the piezoelectric layers34and35with the electrode layers coupled with the piezoelectric layers34and35(that is, the electrode layers36,37and the additional electrode layers (not illustrated)). When the deformable base plate33is bent, a strain is generated in each of the spin device electrode11and the magnetization direction of the recording layer23of each spin device element11is tilted from the original magnetization direction of the recording layer23, which is determined by the magnetic anisotropy thereof, due to a magnetostrictive effect. By tilting the magnetization direction of the recording layer23from the original magnetization direction, the recoding layer23is placed into a state in which the magnetization of the recoding layer23is easily reversible.

A write current is fed to the selected memory cell1A in the state in which the deformable base plate33is bent. The direction of the write current is determined on the basis of the value of the data to be written into the selected memory cell1A. This operation effectively allows writing the desired data into the selected memory cell1A. This is followed by stopping bending the deformable base plate33to complete the data writing.

Also in the structure illustrated inFIGS. 27 and 28, the above-described operation effectively achieves data writing with a reduced data write power, since the data writing is assisted by the magnetostrictive effect caused by the strain generated in each spin device element11. It should be noted that the mechanism which uses a force exerted between a pair of capacitor electrodes as illustrated inFIGS. 26A and 26Bmay be used as the bending mechanism to bend the deformable base plate33.

Also in the structure in which the spin device elements11of the memory cells are formed on the deformable base plate33, data writing into a selected memory may be achieved with a current-induced current.FIG. 29is a perspective view illustrating the configuration of each block of the memory cell array in the case when data writing into a selected memory1C is achieved with a current-induced magnetic field, andFIG. 30is a plan view illustrating the structure of each block.

In the structure illustrated inFIGS. 29 and 30, a write current line26is provided close to each memory cell10.FIGS. 29 and 30illustrate a structure in which the write current lines26are provided under the deformable base plate33. The write current lines26are formed to extend in the X-axis direction. The spin device elements11A1and11A2of each memory cell10are positioned opposed to the spin device elements11B1and11B2across the write current line26. More specifically, as illustrated inFIG. 30, the spin device elements11A1and11A2of each memory cell10are positioned shifted from the write current line26corresponding to each memory cell10in the +Y direction (a first direction), and the spin device elements11B1and11B2of each memory cell10are positioned shifted from the write current line26corresponding to each memory cell10in the −Y direction (a second direction opposite to the first direction). This arrangement preferably allows generating such a magnetic field that the magnetizations of the recoding layers23of the spin device elements11A1and11A2and those of the recoding layers23of the spin device elements11B1and11B2are directed in opposite directions with only one write current line26. Note that the spin device element11A2is positioned shifted from the spin device element11A1in the +X direction, and the spin device element11B1is positioned shifted from the spin device element11B2in the +X direction.

Although electrical connections among the spin device elements11A1,11A2,11B1and11B2in each memory cell10are not illustrated inFIGS. 29 and 30, a person skilled in the art would appreciate that the spin device elements11A1,11A2,11B1and11B2may be electrically connected in a similar way to the configuration illustrated inFIG. 19.

Also in the configuration illustrated inFIGS. 29 and 30, data writing into a selected memory cell10can be achieved by applying a current-induced magnetic field to the recording layer23of each spin device element11of the selected memory cell10in the state in which the deformable base plate33is bent. In detail, the deformable base plate33is bent in data writing into the selected memory cell10. As described above, the deformable base plate33can be bent by applying electric fields to the piezoelectric layers34and35with the electrode layers coupled with the piezoelectric layers34and35(that is, the electrode layers36,37and the additional electrode layers (not illustrated)). When the deformable base plate33is bent, a strain is generated in each of the spin device electrode11and the magnetization direction of the recording layer23of each spin device element11is tilted from the original magnetization direction of the recording layer23, which is determined by the magnetic anisotropy thereof, due to a magnetostrictive effect. By tilting the magnetization direction of the recording layer23from the original magnetization direction, the recoding layer23is placed into a state in which the magnetization of the recoding layer23is easily reversible.

Furthermore, a write current Iw flowing through the write current line26corresponding to the selected memory cell1C is generated in the state in which the deformable base plate33is bent. The direction of the write current Iw is determined depending on data to be written into the memory cell1C. By the write current Iw flowing through the corresponding write current line26, a current-induced magnetic field is applied to the recording layer23of each spin device element11of the selected memory cell1C, and a desired data is thereby written into the selected memory cell1C. This is followed by stopping bending the deformable base plate33to complete the data writing.

Also in the case when data writing is achieved by using a current-induced magnetic field, the above-described operation effectively achieves data writing with a reduced data write power, since the data writing is assisted by the magnetostrictive effect caused by the strain generated in each spin device element11. It should be noted that the mechanism which uses a force exerted between a pair of capacitor electrodes as illustrated inFIGS. 26A and 26Bmay be used as the bending mechanism to bend the deformable base plate33.

Although various specific embodiments of the present invention have been described in the above, the present invention must not be construed as being limited to the above-described embodiments. It would be apparent to a person skilled in the art that the present invention may be implemented with various modifications without departing from the scope of the invention.