Isolation testing circuit and testing circuit optimization method

In order to avoid generation of a routing complexity of LSI and a signal rounding due to insertion of the isolation testing circuit, if a plurality of IPs are incorporated into LSI, the present invention provides an isolation testing circuits having test switching selectors 731 to 736 for selecting any one of a test input signal (or a test input transit signal) and a normal input signal, and test signal transit buffers 721 to 726 for relaying the test input signal (or the test input transit signal) are formed in respective IP blocks 701 to 706 incorporated into an LSI. Adjacent isolation testing circuits are connected mutually based on a floor plan or layout placement information such that a wiring length of a test input signal 709 and test input transit signals 710 to 714, which are connected in a single stroke of a pen, can be reduced shortest.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an isolation testing circuit and a testing circuit optimization method for executing an isolation test of a plurality of IPs incorporated into an LSI.

2. Description of the Related Art

The number of IPs incorporated into the LSI becomes huge nowadays pursuant to the larger scale of the LSI. In order to check functions of incorporated IPs, the isolation testing circuit for leading input/output terminals of respective IPs to external terminal of the LSI must be inserted. Since the input/output terminals of respective IPs are connected to share the external terminal of the LSI, the external terminal of the LSI and respective IPs are connected via enormous wirings. In this case, the related art concerned with the IP test is disclosed in Patent Reference 1(JP-A-2001-267510), and so forth.

FIG. 10is a configurative view of LSI showing an isolation testing circuit configuration in the related art. InFIG. 10, a test input signal1009input from the external device via a test input terminal1007is connected to IP blocks1001to1006incorporated into the LSI via one wiring respectively. Also, test output signals1017to1022of respective IP blocks1001to1006are connected to a test output terminal1015via a test switching selector1037in such a manner that all wirings are converged into the test output terminal1015. Such wirings are inserted as many as the number of the test input signals used in the isolation test.

However, according to the method in the related art, a large number of wirings that are extended from the external terminal to respective IPs in a one-to-multiple fashion and wirings that are converged into one location must be inserted. As a result, problems such as a routing complexity, a signal rounding, etc. were caused in a layout design of LSI, so that a floor plan of LSI often failed and an increase of a chip size and a delay of a development term were brought about.

SUMMARY OF THE INVENTION

The present invention has been made to overcome the above problems in the related art, and it is an object of the present invention to provide an isolation testing circuit and a testing circuit optimization method capable of avoiding generation of a routing complexity of LSI and a signal rounding due to insertion of the isolation testing circuit, in the LSI into which a plurality of IPs are incorporated.

In order to achieve this object, an isolation testing circuit set forth in Claim1provides an isolation testing circuit added to an IP (internal circuit107) that is incorporated into an LSI (IP block108), which comprises a test switching selector (test switching selector103) for selecting a test input signal (test input signal101) or a normal input signal (normal input signal102) to input into the IP; and a test-signal transit buffer (test-signal transit buffer104) for obtaining a test input transit signal that relays the test input signal to propagate to another IP.

According to the above configuration, the overall testing circuit can be constructed in such a manner that the test input signal is propagated as the test input transit signal through respective IP blocks to which the isolation testing-circuit is added. Therefore, the wirings of the test input signal are never provided to extend from one terminal to a plurality of IPs in a one-to-multiple fashion. As a result, the routing complexity caused by the test input signal can be relaxed and also the signal rounding of the test input signal can be suppressed because the signal is relayed by the test signal transit buffer.

In the isolation testing circuit set forth in Claim1, the isolation testing circuit according to claim2further comprises a timing adjusting flip-flop (timing adjusting flip-flop206) for adjusting a delay time of the test input signal; wherein the test switching selector selects the test input signal a timing of which is adjusted or the normal input signal.

According to the above configuration, in addition to the effect of the isolation testing circuit set forth in Claim1, since the test input signal is input into the IP via the timing adjusting flip-flop, a delay time of the test input signal due to the propagation can be adjusted. Therefore, the influence of the delay of the test input signal can be eliminated, and a stable testing can be implemented.

An isolation testing circuit set forth in Claim3provides an isolation testing circuit added to an IP (internal circuit307) that is incorporated into an LSI (IP block308), which comprises a test switching selector (test switching selector303) for selecting an external test output signal (external test output signal301) or an internal test output signal (internal test output signal302) to output to another IP.

According to the above configuration, the overall testing circuit can be constructed in such a manner that the test output signal is propagated through respective IP blocks to which the isolation testing circuit is added. Therefore, a large number of wirings of the test output signal are never converged into one location of the LSI, and the routing complexity caused by the test output signal can be relaxed

A testing circuit optimization method set forth in Claim4provides a testing circuit optimization method of an LSI into which a plurality of IPs to which the isolation testing circuit set forth in Claim1or Claim2or Claim3or having an equivalent function is added are incorporated, which comprises the step of executing a testing-circuit adjacent connecting process of connecting adjacent isolation testing circuits sequentially in a single stroke of a pen based on floor plan information of the LSI before a layout placing process is executed.

According to the above configuration, the isolation testing circuits inserted into respective IP blocks can be connected mutually via the shortest wiring in a single stroke of the pen. Therefore, the routing complexity caused by the test input signal or the test output signal can be relaxed and the signal rounding of the test input signal or the test output signal can be suppressed.

A testing circuit optimization method set forth in Claim5provides a testing circuit optimization method of an LSI into which a plurality of IPs to which the isolation testing circuit set forth in Claim1or Claim2or Claim3or having an equivalent function is added are incorporated, which comprises the step of executing a testing-circuit adjacent connecting process of connecting adjacent isolation testing circuits sequentially in a single stroke of a pen based on actual placement information of the LSI after a layout placing process is executed.

According to the above configuration, the isolation testing circuits inserted into respective IP blocks can be connected mutually via the shortest wiring in a single stroke of the pen to take account of actual positional relationships of respective IP blocks. Therefore, the routing complexity caused by the test input signal or the test output signal can be relaxed and the signal rounding of the test input signal or the test output signal can be suppressed.

A testing circuit optimization method set forth in Claim6provides a testing circuit optimization method of an LSI into which a plurality of IPs to which the isolation testing circuit set forth in Claim1or Claim2or Claim3or having an equivalent function is added are incorporated, which comprises the steps of removing wirings provided by a testing-circuit adjacent connecting process using the testing circuit optimization method set forth in Claim4after a layout placing process is executed by using a net list that is formed by applying the testing circuit optimization method set forth in Claim4; and executing a testing-circuit adjacent reconnecting process of connecting adjacent isolation testing circuits sequentially in a single stroke of a pen based on actual placement information after the layout placing process is executed.

According to the above configuration, the isolation testing circuits inserted into respective IP blocks can be connected mutually, then these wirings are removed after the layout placing process, and then respective signals are connected once again via the shortest wiring in a single stroke of the pen to take account of actual positional relationships of respective IP blocks. Therefore, the implementation and the layout of the testing circuits can be achieved such that the routing complexity caused by the test input signal or the test output signal can be reduced at its maximum and the signal rounding of the test input signal or the test output signal can be suppressed.

In the drawings, a reference numeral101,201refers to a test input signal input terminal;102,202to a normal input signal input terminal;103,203,303to a test switching selector;104,204to a test signal transit buffer;105,205to a test input transit signal output terminal;206to a timing adjusting flip-flop;107,207,307to an internal circuit;108,208,308to an IP block;301to an external test output signal input terminal;302to an internal test output signal;304to a test output signal output terminal;401,601,901to an initial net-list inputting step;402,602,902to an isolation testing-circuit inserting step;403,903to a floor-plan block placement information extracting step;405,605,905to a testing-circuit adjacent connecting step;406,606,906to a testing-circuit connected net-list generating step;607to a testing-circuit inserted net-list generating step;408,608,908to a layout placing step;909to a testing-circuit wiring cutting step;610,910to a layout placement information extracting step;911to a testing-circuit adjacent reconnecting step;912to a testing-circuit reconnected net-list generating step;413,613,913to a layout routing step;501to506,701to706to an IP block;801to806,1001to1006to an IP block;507,707,1007to a test input terminal;508,708,1008to a test input terminal x;509,709,1009to a test input signal;510to514,710to714to a test input transit signal;515,815to a test output terminal;516,816to a test output terminal y;517to522,817to822to a test output signal;721to726to a test signal transit buffer; and731to736,831to836to a test switching selector.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Isolation testing circuits and testing circuit optimization methods according to embodiments of the present invention will be explained with reference to the drawings hereinafter.

FIG. 1is a block diagram showing a configuration of an isolation testing circuit in a first embodiment of the present invention. InFIG.1,101is a test input signal input terminal,102is a normal input signal input terminal,103is a test switching selector,104is a test-signal transit buffer,105is a test-input transit signal output terminal,107is an internal circuit of IP installed into the IP block, and108is an IP block.

In the IP block108, any one of a test input signal from the test input signal input terminal101and a normal input signal from the normal input signal input terminal102is selected by the test switching selector103and then input into the internal circuit107. Also, a test input signal is transited through the test-signal transit buffer104and then output from the test-input transit signal output terminal105to the outside.

Since the isolation testing circuit shown inFIG. 1is formed in each IP block incorporated into the LSI and these circuits are connected in compliance with a testing circuit optimization method described later, an optimum isolation testing circuit can be constructed in the LSI. As a result, the routing complexity caused by the test input signal can be relaxed and the signal rounding of the test input signal can be suppressed.

FIG. 2is a block diagram showing a configuration of an isolation testing circuit in a second embodiment of the present invention. InFIG. 2,201is a test input signal input terminal,202is a normal input signal input terminal,203is a test switching selector,204is a test signal transit buffer,205is a test-input transit signal output terminal,206is a timing adjusting flip-flop,207is an internal circuit of IP installed in the IP block, and208is an IP block.

In the IP block208, a test input signal from the test input signal input terminal201is input into the timing adjusting flip-flop206to eliminate the influence of the delay, and then one of an output of the timing adjusting flip-flop206and a normal input signal from the normal input signal input terminal202is selected by the test switching selector203and then input into the internal circuit207. Also, a test input signal is transited through the test-signal transit buffer204and then output from the test-input transit signal output terminal205to the outside.

Since the isolation testing circuit shown inFIG. 2is formed in each IP block incorporated into the LSI and these circuits are connected in compliance with a testing circuit optimization method described later, an optimum isolation testing circuit can be constructed in the LSI. As a result, the routing complexity caused by the test input signal can be relaxed and the signal rounding of the test input signal can be suppressed. In addition, the influence of the delay of the test input signal can be eliminated, and a stable testing can be implemented.

FIG. 3is a block diagram showing a configuration of an isolation testing circuit in a third embodiment of the present invention. InFIG. 3,301is an external test output signal input terminal,302is an internal test output signal,303is a test switching selector,304is a test output signal output terminal,307is an internal circuit of IP installed in the IP block, and308is an IP block.

In the IP block308, one of an external test output signal from the external test output signal input terminal301and the internal test output signal302output from the internal circuit307is selected by the test switching selector303and then output from the test output signal output terminal304.

Since the isolation testing circuit shown inFIG. 3is formed in each IP block incorporated into the LSI and these circuits are connected in compliance with a testing circuit optimization method described later, an optimum isolation testing circuit can be constructed in the LSI. As a result, the routing complexity caused by the test output signal can be relaxed and the signal rounding of the test output signal can be suppressed.

FIG. 4is a view showing steps of a testing circuit optimization method in a fourth embodiment of the present invention.FIG. 5is a configurative view showing an isolation testing circuit of LSI, to which the testing circuit optimization method in the fourth embodiment of the present invention is applied.

In the present embodiment, first, in step401, an initial net-list used to layout the LSI is input. Then, in step402, the isolation testing circuits shown inFIG. 1andFIG. 2andFIG. 3are inserted into respective IP blocks501to506.

Then, in step403, floor-plan block placement information are extracted to connect mutually the isolation testing circuits inserted into respective IP blocks. Then, in step405, a testing-circuit adjacent connecting process of connecting the test input signal509, the test input transit signals510to514, and the test output signals517to522in a single stroke of the pen based on the extracted information is carried out such that a wiring length can be reduced shortest with regard to positional relationships among respective IP blocks501to506. Then, in step406, the result is generated as a testing-circuit connected net-list.

In the end, in step408, a layout placing process is carried out by using the testing-circuit connected net-list. Then, in step413, a layout routing process is carried out, whereby the layout of the LSI into which the isolation testing circuits are incorporated is completed.

According to this, the isolation testing circuits inserted into respective IP blocks can be connected mutually via the shortest wiring in a single stroke of the pen. Therefore, the implementation and the layout of the testing circuits can be attained such that the routing complexity caused by the test input signal and the test output signal can be relaxed and the signal rounding of the test input signal and the test output signal can be suppressed.

FIG. 6is a view showing steps of a testing circuit optimization method in a fifth embodiment of the present invention.FIG. 7andFIG. 8are configurative views showing an isolation testing circuit of LSI, to which the testing circuit optimization method in the present embodiment of the present invention is applied, respectively.

InFIG. 8,801to806are IP blocks,815is a test output terminal,816is a y-th test output terminal,817to822are test output signals, and831to836are test switching selectors.

In the present embodiment, first, in step601, an initial net-list used to layout the LSI is input. Then, in step602, the isolation testing circuits shown inFIG. 1andFIG. 2andFIG. 3are inserted into respective IP blocks701to706,801to806. Then, in step607, the result is generated as a testing-circuit inserted net-list.

Then, in step608, a layout placing process is carried out by using the testing-circuit inserted net-list. Then, in step610, a layout placement information extraction of the test signal transit buffers721to726and the test switching selectors731to736,831to836is carried out.

Then, in step605, a testing-circuit adjacent connecting process of connecting the test input signal709, the test input transit signals710to714, and the test output signals817to822in a single stroke of the pen is carried out based on the extracted information such that a wiring length can be reduced shortest to take account of actual positional relationships among respective IP blocks. Then, in step606, the result is generated as a testing-circuit connected net-list.

Finally, in step613, a layout routing process is executed by using the testing-circuit connected net-list, whereby the layout of the LSI into which the isolation testing circuits are incorporated is completed

According to this, the isolation testing circuits inserted into respective IP blocks can be connected mutually via the shortest wiring in a single stroke of the pen to take account of actual positional relationships of respective IP blocks. Therefore, the implementation and the layout of the testing circuits can be attained such that the routing complexity caused by the test input signal and the test output signal can be relaxed and the signal rounding of the test input signal and the test output signal can be suppressed.

FIG. 9is a view showing steps of a testing circuit optimization method in a sixth embodiment of the present invention. The present embodiment will be explained with reference to the configurative views showing the isolation testing circuits of LSIs inFIG. 5andFIG. 7andFIG. 8hereunder.

In the present embodiment, first, in step901, an initial net-list used to layout the LSI is input. Then, in step902, the isolation testing circuits shown inFIG. 1andFIG. 2andFIG. 3are inserted into respective IP blocks501to506or701to706or810to806.

Then, in step903, floor-plan block placement information are extracted to connect mutually the isolation testing circuits inserted into respective IP blocks. Then, in step905, a testing-circuit adjacent connecting process of connecting the test input signal509, the test input transit signals510to514, and the test output signals517to522in a single stroke of the pen is carried out based on the extracted information such that a wiring length can be reduced shortest with regard to positional relationships among respective IP blocks501to506. Then, in step906, the result is generated as a testing-circuit connected net-list.

Then, in step908, a layout placing process is carried out by using the testing-circuit connected net-list. Then, in step909, a testing-circuit wiring cutting process of removing the wirings that are provided in the testing circuit adjacent connecting process in step905is carried out.

Then, in step910, extraction of layout placement information of the test signal transit buffers721to726and the test switching selectors731to736,831to836is carried out. Then, in step911, a testing-circuit adjacent reconnecting process of connecting the test input signal709, the test input transit signals710to714, and the test output signals817to822in a single stroke of the pen is carried out based on the extracted information such that a wiring length can be reduced shortest to take account of actual positional relationships among respective IP blocks. Then, in step912, the result is generated as a testing-circuit reconnected net-list.

Here, the layout placement information extraction in step910may be carried out before the testing-circuit wiring cutting process in step909is executed. Then, in step913, a layout routing process is executed based on the wiring connection information in the testing-circuit reconnected net-list, whereby the layout of the LSI into which the isolation testing circuits are incorporated is completed.

In this manner, the isolation testing circuits inserted into respective IP blocks can be connected mutually via the shortest wiring, then these wirings are removed after the layout placing process is done, and then respective signals are connected once again via the shortest wiring in a single stroke of the pen to take account of actual positional relationships among respective IP blocks. Therefore, the implementation and the layout of the testing circuits can be achieved such that the routing complexity caused by the test input signal and the test output signal can be further reduced and the signal rounding of the test input signal and the test output signal can be suppressed.

As explained above, according to the present invention, since the function of relaying the test input signal and the test output signal is installed into the isolation testing circuits that are added to the IP incorporated into the LSI, the overall testing circuit can be constructed in such a manner that the test input-signal and the test output signal are propagated through respective IP blocks. Therefore, the wirings of the test input signal and the test output signal are never provided to extend from one terminal to a plurality of IPs in a one-to-multiple fashion, and also a large number of wirings are never converged into one location. As a result, the routing complexity caused by the test input signal and the test output signal can be relaxed and also the signal rounding of the test input signal and the test output signal can be suppressed because these signals are relayed by the test signal transit buffer or the test switching selector.

In addition, according to the present invention, since the testing circuit optimization method of connecting the adjacent isolation testing circuits sequentially in a single stroke of the pen based on the floor plan and the layout placement information is employed, the routing complexity caused by the testing circuits can be reduced at its maximum and thus the excellent effect can be brought about on the layout of the LSI into which the isolation testing circuits are incorporated.