Cache directory that determines current state of a translation in a microprocessor core cache

A cache structure implemented in a microprocessor core include a set predictor and a logical directory. The set predictor contains a plurality of predictor data sets containing cache line information, and outputs a first set-ID indicative of an individual predictor data set. The logical directory contains a plurality of logical data sets containing cache line information. The cache structure selectively operates in a first mode such that the logical directory receives the first set-ID that points to an individual logical data set, and a second mode such that the logical directory receives a currently issued micro operational instruction (micro-op) containing a second set-ID that points to an individual logical data set. The logical directory performs a cache lookup based on the first set-ID in response to operating in the first mode, and performs a cache lookup based on the second set-ID in response to operating in the second mode.

BACKGROUND

The present invention relates to the field of digital computer systems, and more particularly, to microprocessor cores including a logical directory.

Microprocessor core cache designs can be based on a logically indexed, absolute tagged cache directories (also referred to as absolute directories), or logically indexed, logically tagged directories (referred to herein as logical directories). Logically or absolute indexed, absolute tagged cache directories typically implement a hardware structure called a “translation lookaside buffer” (TLB) to store currently available translations. Logical directory cache structures, however, do not employ a separate TLB. Instead, the directory entries in the logical directory carry the translation information.

SUMMARY

Various non-limiting embodiments of the present invention are directed a cache structure implemented in a microprocessor core comprises a set predictor and a logical directory. The set predictor contains a plurality of predictor data sets, where each predictor data set contains cache line information. The set predictor is configured to output a first set-ID indicative of an individual predictor data set among the plurality of predictor data sets. The logical directory contains a plurality of logical data sets, where each logical data set contains cache line information. The cache structure selectively operates in a first mode such that the logical directory receives the first set-ID that points to an individual logical data set among the plurality of logical data sets, and a second mode such that the logical directory receives a currently issued micro operational instruction (micro-op) containing a second set-ID that points to an individual logical data set among the plurality of logical data sets. The logical directory performs a cache lookup based on the first set-ID in response to operating in the first mode, and performs a cache lookup based on the second set-ID in response to operating in the second mode.

One or more additional non-limiting embodiments of the present invention are directed to a computer-implemented method of determining a current state of an address translation in a microprocessor core cache, the method comprising storing a plurality of predictor data sets containing cache line information in a set predictor, and outputting a first set-ID indicative of an individual predictor data set among the plurality of predictor data sets. The method further comprises storing a plurality of logical data sets in a logical directory, where each logical data set contains cache line information. The method further includes selectively operating a cache structure in a first mode such that the logical directory receives the first set-ID, and a second mode such that the logical directory receives a currently issued micro operational instruction (micro-op) containing a second set-ID that points to an individual logical data set among the plurality of logical data sets. The method further comprises performing a cache lookup in the logical directory based on the second set-ID in response to operating in the second mode, and determining the current state of the address translation based on the cache lookup.

One or more additional non-limiting embodiments of the invention are directed to a computer program product to control a cache structure to determine a current state of an address translation in a microprocessor core cache. The computer program product includes a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by an electronic computer processor to control the cache structure to perform operations comprising storing a plurality of predictor data sets containing cache line information in a set predictor, and outputting a first set-ID indicative of an individual predictor data set among the plurality of predictor data sets. The method further comprises storing a plurality of logical data sets in a logical directory, where each logical data set contains cache line information. The method further includes selectively operating a cache structure in a first mode such that the logical directory receives the first set-ID, and a second mode such that the logical directory receives a currently issued micro operational instruction (micro-op) containing a second set-ID that points to an individual logical data set among the plurality of logical data sets. The method further comprises performing a cache lookup in the logical directory based on the second set-ID in response to operating in the second mode, and determining the current state of the address translation based on the cache lookup.

DETAILED DESCRIPTION

Turning now to an overview of technologies that are more specifically relevant to aspects of the invention, microprocessor core cache designs including logical directories typically implement a separate predictor cache (sometimes referred to as a “set predictor”) to facilitate a fast access of a cache entry without relying on the results of a traditional TLB or directory lookup. Logical directory designs can also use the set predictor cache to select a single logical directory entry to read and validate the specific set selected by the set predictor rather than reading and validating all sets in parallel from the logical directory in order to save circuitry and power. However, conventional set predictors are capable of accessing the logical directory entry only when it currently points to the directory set containing the targeted directory entry which can result in missing a “hit” event.

Software or hardware implementations of address translations in the microprocessor core can realize temporality illegal states, sometimes referred to as “bugs.” Therefore, it is necessary to perform a frequency “debug read” operation of the translation information. Because a logical directory entry is only accessed if the set predictor currently points to the directory set containing the targeted directory entry, the set predictor may encounter a “miss-wrong” error. A miss-wrong error is typically referred to as an event where a given directory entry exists that should “hit”, but the translation information cannot be read due to the miss by the set predictor, i.e., the set predictor was not pointing to the logical directory at the correct time.

Turning now to an overview of the aspects of the invention, one or more embodiments of the invention address the above-described shortcomings of the prior art by providing microcontroller core including a logical directory, which is capable of determining the current state of a translation in a logically indexed, logically tagged (also called a “logical cache”) directory where only one set can be read at a time, with minimal additional hardware overhead and execution delay. In at least one non-limiting embodiment, various microarchitectural mechanisms are modified to implement reading the translation information from a logical directory directly. A separate instruction cracking function is used to break (or “crack”) a complex instruction into multiple smaller or micro operational instructions referred to as, “micro-ops”. Each micro-op contains a memory operand logical address field inherited from the original instruction that corresponds to a particular index LA(50:55) and tag LA(0:49) in the logical directory and is assigned a micro-op number that identifies a given micro-op. Thus, the instruction can be cracked into a sufficient number of micro-ops such that the micro-op number assigned to a given micro-op can be used to point to a particular set in the logical directory. It should be appreciated that the index LA(50:55) described herein is an example range, it is not intended to limit the scope of the invention to any particular range. In at least one embodiment, the complex instruction utilized is a “LOAD MULTIPLE” instruction, which is broken or divided into multiple internal “load” micro-ops. Each of those micro-ops is then separately issued to a Load/Store Unit (LSU) that implements the logical cache. In one example, the LOAD MULTIPLE instruction is split such that each “load” micro-op loads one 16 byte register with values from memory (or the cache subsystem), instead of executing the whole architected operation of reading the entire operand from memory and writing multiple registers in one step. Thus, the index LA(50:55) of a given micro-op can be used to determine the particular row of the logical directory and the micro-op number of a given micro-op can be used to determine the particular set in the logical directory on which to perform a lookup.

With respect toFIG. 1,FIG. 1illustrates a computer system100in accordance with an example of the present disclosure. The computer system100may be based on the z/Architecture, offered by International Business Machines (IBM). Computer system100may use a set-associative cache memory structure. Computer system100comprises at least one processing unit101. In one example, the computer system100may be used as a hardware resource in a virtualized environment such as z/VM of IBM. For example, the processing unit101may receive requests from virtual machines or a guest running under a hypervisor in a logical partition.

The processing unit101may be connected to various peripheral devices, including input/output (I/O) devices114(such as a display monitor, keyboard, and permanent storage device), memory device116(such as random-access memory or RAM) that is used by the processing units to carry out program instructions, and firmware118whose primary purpose is to seek out and load an operating system from one of the peripherals whenever the computer is first turned on. AlthoughFIG. 1depicts a two-level cache hierarchy, multi-level cache hierarchies can be provided where there are many levels of serially connected caches. For example, the components of processing unit101may be packaged on a single integrated chip.

Processing unit101communicates with the peripheral devices (e.g. firmware118, I/O devices114and memory116) by various means, including a generalized interconnect or bus120. Processing unit101includes a processor core122having a plurality of registers and execution units, which carry out program instructions in order to operate the computer. An exemplary processing unit includes the PowerPC™ processor marketed by International Business Machines Corporation. The processing unit101also can have one or more caches. For example, the processing unit101is shown as comprising two caches126and130. Caches are used to temporarily store values that might be repeatedly accessed by a processor, in order to speed up processing by avoiding the longer step of loading the values from memory116.

Caches126and130are set-associative caches which enable the processor to achieve a relatively fast access time to a subset of data or instructions previously transferred from a memory116. The cache126may be integrally packaged with the processor core122. The cache126may comprise instruction arrays (not shown) and data arrays141which are implemented using high-speed memory devices. Instructions and data may be directed to the respective cache by examining a signal that is indicative of whether the processor core is requesting an operation whose operand is instruction versus data.

The cache126includes a logical directory140that is associated with a data array141. Each cache line in the data array141has a corresponding entry in the logical directory140. The logical directory140can indicate whether the data identified by a logical address (also referred to as an effective address) is stored in the data array141. For example, a processor instruction that references logical address can be provided to the cache126. If the logical address is in the logical directory140, then the processor is aware that the referenced data can be obtained from the data array141subject to access criteria being fulfilled, wherein access criteria may require that the valid bit is set, etc. For example, the logical address includes a tag field, a line index field, and a byte field. The tag field of the logical address is utilized to provide cache “hit” information as described herein. The line index field of the logical address is utilized to get N cache lines e.g. within data cache array141, which are indexed by the line index field, where N is the number of sets in a N-associative cache memory. One of the N cache lines may be selected using a set identifier (as part of a late select) and the byte field of the logical address is utilized to index a specific byte within the selected cache line.

The logical directory140is constructed according to a logical cache design, which provides a logically indexed, logically tagged directory sometimes referred to as a “virtual directory.” In at least one non-limiting embodiment, the logical directory140is defined as having a page size of 4,096 bytes, a cache line size of 256 bytes, and a 64 bit address space. The cache entries of the logical directory140carry translation information. Accordingly, address translations operations associated with the logical directory140translate logical address bits (LA) 0:51 into different absolute address bits (AA) 0:51. LA(0:51) to specify a given page of virtual memory. The given page holds the 16 different cache lines that all have the same LA(0:51), while address LA(52:55) are different among the entries. Address LA(56:63) describes the byte offset within a cache line.

The data array141and the logical directory140may be constructed from conventional memory arrays, such as are readily available in configurations of, for example, 4 M or 8 M chip arrays. The cache126is associated with a cache controller (not shown) that for example manages the transfer of data between the processor core122and the caches.

The data cache array141has many cache lines which individually store the various data values. The cache lines are divided into groups of cache lines called “sets.” An exemplary cache line includes a state-bit field, an exclusivity-bit field, and a value field for storing the actual instruction or data. The state-bit field and inclusivity-bit fields are used to maintain cache coherency in a multiprocessor computer system. The address tag is a subset of the full address of the corresponding memory block. A compare match of an incoming logical address with one of the tags within the address-tag field indicates a cache “hit.” The collection of all of the address tags in a cache (and sometimes the state-bit and inclusivity-bit fields) is referred to as a directory, and the collection of all of the value fields is the cache entry array.

FIG. 3illustrates a directory structure of a logical directory140. The logical directory140is indexed with a plurality of rows (e.g., 64 rows deep), with each row having assigned thereto a local address LA(50:55). Each row of the directory contains 8 columns or 8 “sets”, where each set holds cache line information. Thus, each row holds information about eight cache lines in its eight “sets”. To identify a particular cache line in the logical directory140, all eight sets corresponding to a given index LA(50:55) are read out, and all the “tags” stored in the logical directory140are compared. A “hit” in the cache set occurs when one set matches the tag of the cache line in question.

Referring again toFIG. 1, the cache126may be referred to as level 1 (L1) cache and cache130, may be referred to as a level 2 (L2) cache since it supports the (L1) cache126. For example, cache130may act as an intermediary between memory116and the L1 cache and can store a larger amount of information (instructions and data) than the L1 cache can, but at a longer access penalty. For example, cache130may have a storage capacity of 256 or 512 kilobytes, while the L1 cache may have 64 kilobytes of total storage. Cache130is connected to bus120, and all loading of information from memory116into processor core122may come through cache130.

Also shown inFIG. 1is a translation lookaside buffer (TLB)143for translating logical address to a corresponding absolute address. The TLB143can translate the page number portion of logical address to a corresponding real page number. For example, the tag field of a logical address may be sent to TLB143to be translated to a corresponding real page number.

FIG. 2is a block diagram illustrating a diagram for accessing cache structure200of a cache memory with two-level cache via a logical address (or logical address or virtual address)201in accordance with an example of the present disclosure. The cache memory is a set associative cache comprising for example m sets in L1 cache and n sets in L2 cache. M may or may not equal to n. The cache structure200comprises a L1 cache226and L2 cache230. The L1 cache226comprises a data cache array141, a logical directory140, a set predictor203(sometimes referred to as a set directory)203and a logical directory205(sometimes referred to as a validation directory). The L2 cache230comprises a cache directory242, a cache array (not shown), and a TLB143.

The set predictor203can be constructed as a directory that is logically indexed using line index bits of a line index field210of the logical address201and logically tagged using a first group of bits212aof the tag field212of the logical address201. The logical directory205is constructed as a directory logically indexed using line index bits of the line index field210of the logical address201and set bits.

The logical directory205is logically tagged using a second group of bits212bof the tag field212of the logical address201. The first and second groups of bits212aand212bare shown non-overlapping for exemplification purpose. However, the first group and second of bits may overlap. For example, the second group of bits may comprise bits 0:49 which may enable to have set directory update rules that are relaxed e.g. that allows that the set directory and the validation directory do not have to be strictly in sync at all times.

For simplifying the description ofFIG. 2, a simplified example of L1 cache may be considered. In this example, the L1 cache has 64 rows and 8 sets (i.e. m=8), and a cache line is addressed using logical address having 64 bits (0:63) (abbreviated LA(0:63)). Therefore, the line size in this example is 256 bytes. In this example, the set predictor203may use LA(37:49) as a tag (the first group of bits). The tag of the logical directory205may be LA(0:49) or LA(0:36), plus additional information required to differentiate between different address spaces.

The logical directory205may be referred to as a “Stacked” logical directory as the validation directory is built from one physical array structure that holds one directory entry per row. Following the above example, the validation directory comprises 8×64 rows=512 rows, instead of eight array structures that each has 64 rows. The benefit of such a structure may be that an array row can only have a limited number of bits (for physical reasons). Adding more rows comes with a comparatively low overhead relative to extending the width of a row or adding more array structures. The “stacked” approach may be advantageous as it may use less area and power. The L1 logical directory140has, however, an eight array structures that each has 64 rows.

When operating in a normal mode, the set predictor203can perform a cache lookup which receives as input the index LA(50:55) and first group of bits referred to as the tag LA(37:49). Based on these inputs, the set predictor203generates or predicts the data set having a set ID referred to as Set(0:7) that holds the requested cache line. For example, the set predictor203may be searched in order to find the set ID.

The L1 cache226can further include a hit detector circuit215which confirms a cache hit. For example, using the set ID (e.g., Set(0:7)) in addition to the index LA(50:55), the hit detector circuit looks up the logical directory205to confirm the cache hit using tag compare220, which may result in identifying a corresponding directory entry in the logical directory205. In one example, the set ID determined by the set predictor203is used to select one of the eight 64-row sections, and LA(50:55) is used to select the row within the section.

In at least one embodiment, the cache structure200can switch between the normal operating mode described above, and a read translation mode. The read translation mode can be invoked based on the bit state of a translation mode signal225. When the read translation mode signal225is set to a first state, e.g., binary “0”, the normal “cache lookup” and “cache miss” operations are performed as described above. When, however, the read translation mode signal225is set to a second state, e.g., binary “1”, the system may perform alternative operations, e.g., the normal “cache miss” described above is bypassed or omitted. For example, invoking the read translation mode prevents no lookup of the TLB143or L2 directory242in response to detecting a miss event from reading the logical directory205. Also, there is no update/invalidation of the set directory in response to a miss/no validation event from the logical directory205. There is also no detection of “miss” from the set predictor203since it is bypassed. Instead, the index LA(50:55) indicated by the currently issued micro-op is set as the directory result, i.e., is used to indicate the particular logical directory set on which to perform a lookup.

As described herein, software and hardware implementations of address translations in the microprocessor core can realize temporality illegal states, sometimes referred to as “bugs.” Therefore, “debug read” operations are frequently performed on the translation information. Because a logical directory entry is only accessed if the set predictor currently points to the directory set containing the targeted directory entry, the set predictor may encounter a “miss-wrong” error, where a given directory entry exists that should “hit”, but the translation information is not read due to the miss by the set predictor, i.e., the predictor was not pointing to the directory at the correct time.

Turning now toFIG. 4, a cache structure200included in the computer system100is illustrated according to a non-limiting embodiment. The cache structure200includes a set predictor203, an instruction sequencing unit (ISU)402, a data selector404, a logical directory205, a hit detector circuit215, and a translation state register406. In at least one embodiment, the cache structure200is capable of reading the current state of the address translations, and when a hit occurs, the relevant translation state information is stored in a hardware register (e.g., the translation state register406) which can be accessed by computer system100(e.g., firmware) via a read path. In this manner, the computer system100implementing a logically indexed, logically tagged directory (e.g., the logical directory205) can determine the current state of an address translation.

The relevant translation state information stored in the translation state register406can vary depending on the instruction set architecture (ISA). In any ISA, however, the cache structure can support a “read register” operation which reads the relevant translation information stored in the translation state register406to determine whether a polled address translation exists in the validation directory (logical directory). In other words, the relevant translation information can indicate whether or not the requested translation achieved a “hit” in the validation directory, and can also indicate that the checked/polled translation is a “valid” and “existing” translation in the validation directory as part of the “current translation state” of the logical directory.

In additional non-limiting embodiments, other information that could be provided about the “valid”/“existing” translation that was hit and found in the logical directory can be whatever is decided to be “interesting” for that particular processor implementation for that particular ISA. When implemented in the z/Architecture processor described herein, for example, possible other information that is interesting based on a translation or translation page may include, but is not limited to: (1) Storage Key (access-control bits and/or Fetch-Protection bit); (2) DAT Protect bit; (3) Common Segment bit; (4) Private Space bit; and (5) Real Space control bit. It should be appreciated that other information can be targeted as relevant information to be stored in the register406if the cache structure200is implemented in another computer architectural system where that ISA would likely have some other translation specific information that would be targeted as of interest for that ISA.

Still referring toFIG. 4, the set predictor203and the logical directory are working on the same UOP of the same instruction. That is, for a given UOP, the same LA(50:55) of the UOP is input to both the set predictor203and the local directory205. The logical directory205is indexed with LA(50:55), and each “row” of the directory (e.g., 64 rows) holds information about the cache lines (e.g., eight cache lines) in its eight “sets”. The set predictor203has a similar structure as the logical directory205in that it utilizes the index LA(50:55) to access one of its rows (e.g., 1 row out of 64 total rows), and each of the rows (e.g., 64 rows) includes a “set” (e.g., 8 sets). Accordingly, there is a one-to-one correlation between the set predictor203and the logical directory205. For example, a specific location of the set predictor203for a LA(50:55) in a particular set is designed to be a one-to-one mapping to the same exact location in the logical directory205for that LA(50:55) and that set.

The set predictor203includes a first input that receives the index LA(50:55), and a second input that receives the tag LA(37:49). The index LA(50:55) indicates a particular row in the set predictor, while the tag LA(37-49) indicates a particular predictor data set in a respective row. Thus, based on these inputs, the set predictor203predicts the set having a set ID referred to as Set(0:7) that holds the requested cache line, and outputs a set ID signal indicative of the predicted set ID. The predicted set ID can be viewed as an 8-bit decoded signal. Each bit (0-7) in the decoded signal represents a possible directory set (e.g., among the 8 sets) to be compared. Setting one of the bits to “1” indicates the specific directory set that is selected for comparison, while all the remaining bits are set to “0” to indicate that they are excluded from the comparison. Thus, whichever bit is set to “1” indicates the set-ID that is selected for the hit detection operation discussed below.

The ISU402performs an instruction cracking function403, which “cracks (or “breaks”) a complex instruction into multiple smaller operations referred to as, “micro-ops”. Each micro-op is then assigned a micro-op ID number indicative of its respective operation. For example, the L1 cache226(seeFIG. 2) can provide loading of instruction streams in conjunction with an instruction fetch unit (not shown), which pre-fetches instructions and may include speculative loading and branch prediction capabilities. The fetched instructions are then broken or “cracked” using the instruction cracking function403to generate units of operation (UOPs) made up of instruction text (itext) of the original instruction, and the UOPs may be distributed among multiple processing paths, pipelines, execution units, etc. Although the instruction cracking function403is illustrated as residing in the ISU402, the location of the cracking function403is not limited thereto. For example, the instruction cracking function403could reside in an instruction dispatch unit (IDU), for example.

The fetched instructions, including the cracked UOPs are decoded by an instruction decode unit (IDU) into instruction processing data. Although not shown, the instruction decode unit107may contain the instruction cracking function403, or the ISU402itself may independently perform the cracking operation in connection with a decode operation.

Based on the UOPs of the decoded (non-cracked and cracked) instructions, the ISU402controls the issuing of the instructions and UOPs of non-cracked and cracked instructions. In at least one embodiment, the ISU402is in signal communication with one or more load/store units (LSUs) (not shown) which implements a virtual cache. The multiple LSU pipelines are treated as execution units for performing loads and stores and address generation for branches. The ISU402can also exchange data with various resources, such as general-purpose registers (GPR) (not shown) and floating point registers (not shown). The GPR and FPR can provide data value storage for data values loaded and stored from the L1 cache226by the load store unit (LSU).

In at least one embodiment, the complex instruction utilized is a “LOAD MULTIPLE” instruction, which is cracked or divided into multiple internal “load” micro-ops. Each of the micro-ops are assigned a load number and are then separately issued to a Load/Store Unit (LSU) that implements the logical cache. In one example, the LOAD MULTIPLE instruction is split such that each “load” micro-op loads one 16 byte register with values from memory (or the cache subsystem), instead of executing the whole architected operation of writing multiple registers in one step.

The data selector404can be constructed as a multiplexer (MUX) or switch, which outputs either the predicted set-ID signal generated by the set predictor203or the micro-op load number signal generated by the instruction cracking function403. The data selector404includes a first data input that receives the set ID signal indicating the predicted set-ID (0:7), and a second data input that receives the micro-op load number signal indicative of the load number corresponding to the currently issued load micro-op.

The data selector404also includes a control input that receives the read translation mode signal225. When the read translation mode signal225is set to the first state (e.g., binary “0”), the predicted set-ID signal generated by the set predictor203is output from the data selector404. When, however, the read translation mode signal225set to the second state (e.g., binary “1”), the read translation mode is invoked. Accordingly, the data selector404outputs the micro-op load number signal indicating the currently issued micro-op and the index LA(50:55) on which to perform the lookup. Thus, in response to invoking the read translation mode, the currently issued micro-op is utilized to perform the lookup.

The logical directory205includes a first input that receives the index LA(50:55), and a second input that receives the selector output signal. When the read translation mode is disabled, the logical directory205receives the set-ID(0:7) output from the set predictor. When, however, the read translation mode is enabled, the second input receives the micro-op load number signal. Accordingly, the predicted set-ID signal generated by the set predictor203is effectively ignored, and a lookup compare is performed based on the index LA(50:55) indicated by the currently issued micro-op. Logical directory information in the form of a logical directory tag corresponding t is then retrieved and output from the logical directory205.

The hit detector circuit215includes a comparator408and an enabler410. The comparator408compares the logical directory tag with the information included in the read translation mode signal225. When information does not match, the comparator408outputs a first signal (e.g., a binary “0”). Accordingly, the enabler410blocks information from being delivered to the translation state register406.

When, however, the information matches, the comparator408outputs a second signal (e.g., a binary “1”), the enabler410outputs the relevant translation information to the translation state register406. The relevant translation information can vary depending on the ISA. In any architecture, however, the relevant translation information indicates whether the translation as set up to be checked/polled according to the read translation mode does exist in the logical directory205. For example, the relevant information can indicate whether or not the requested translation “hit” in the logical directory, along with indicating whether the checked/polled translation is a “valid” and “existing” translation in the logical directory as part of the logical directory's205current translation state.

The enabler410can also selectively deliver additional translation related information to the translation state register406based on whether or not the comparator408indicates a hit. In terms of the z/Architecture recited herein, for example, the additional translation related information can include, but is not limited to, 1) a Storage Key (access-control bits and/or Fetch-Protection bit); 2) a DAT Protect bit; 3) a Common Segment bit; 4) a Private Space bit; and 5) a Real Space control bit. For other processor architectures, other information specific to that processor architecture can be output from the enabler410to the translation state register406when a hit is detected.

In at least one embodiment, the cache structure200further includes a multi-hit detector circuit412. The multi-hit detector circuit412is configured to determine whether multiple “hits” occurred for a given translation. That is, the multi-hit detector circuit412can compare a currently detected cache hit, with previous cache hits recorded in the translation state register406. When a multi-hit is detected, the multi-hit detector circuit412can set an error condition. The information indicating multiple hits also describes the “current translation state” of the logical directory (being in an invalid or “error” state to have multiple entries for the same translation).

With reference toFIG. 5, a method of determining a current state of an address translation in a microprocessor core cache using a cache directory is illustrated according to a non-limiting embodiment. The method begins at operation500, and at operation502a hardware register (e.g., the translation state register406) is cleared. In at least one embodiment, firmware118can initialize the translation state register406to an empty value indicating that a valid translation is not found. At operation504, the operating mode of the cache structure200is switched from a normal operating mode to a read translation mode. The read translation mode is invoked in response to setting a bit value of a read translation mode signal225from a first binary state (e.g., a binary “0”) to a second binary state (e.g., a binary “1”). In at least one embodiment, invoking the read translation mode forces the cache structure200to ignore the predicted set-ID signal generated by the set predictor203. In addition, invoking the read translation mode can command the processor unit101to prevent changes from occurring in the logical directory205(e.g., prevent writes to the logical directory205) and/or prevents execution of any out-of-order or other parallel processes.

At operation506a complex instruction (e.g., a LOAD MULTIPLE instruction) is issued, and at operation508the complex instruction is cracked into several independent micro-ops. In at least one embodiment, the read translation mode can command the processor unit101to execute only the currently issued complex instruction (e.g., the issued LOAD MULTIPLE instruction) until the read translation mode is disabled. At operation510, a currently issued micro-op is executed. In at least one embodiment, execution of the micro-op includes performing a logical directory lookup based on the index LA(50:54) indicated by the currently issued micro-op.

At operation512, a determination as to whether a hit in the logical directory205is detected. When a hit is detected, the current translation state is stored in the translation state register406at operation514. At operation516, a determination is made as to whether the final micro-op among the all the cracked micro-ops has been executed. When the final micro-op has not been executed (i.e., additional micro-ops exists), then the method returns to operation510, and the operations described above are repeated. When, however, the last micro-op is detected at operation516, the translation read mode is disabled at operation518, and the method ends at operation520.

Referring again to operation512, when a hit is not detected at, translation information is blocked from delivery to the translation state register406at operation522, and a determination is made as to whether the final micro-op among the all the cracked micro-ops has been executed at operation524. When the final micro-op has not been executed (i.e., additional micro-ops exists), then the method returns to operation510, and the operations described above are repeated. When, however, the last micro-op is detected at operation524, the translation read mode is disabled at operation526, and the method ends at operation520. In at least one embodiment, the method can be automatically repeated for multiple LA(52:55) combinations, if needed.