Linearizing technique for power amplifiers

Embodiments described herein relate to amplification circuits. In some embodiments the amplification circuit includes a power amplifier, a feedforward error compensation loop, and phase feedback and amplitude feedback error compensation loops nested within the feedforward loop. The two nested feedback loops provide a “pre-cleaning” action, which reduces the amount of rejection required in the feedforward loop. In some embodiments, the amplification circuit includes a power amplifier and an enhanced feedforward loop comprising a phase control circuit that maintains a phase balance needed to reduce distortion in the output signal of the amplification circuit. In some embodiments, the amplification circuit includes a power amplifier, a feedforward error compensation loop, and phase feedback and amplitude feedback error compensation loops nested within the feedforward loop and the feedforward loop comprises the phase control circuit.

TECHNICAL FIELD

The described embodiments relate to amplification circuits, and more particularly to power amplification circuits with improved linearity.

BACKGROUND

The linearization of class A/B high power amplifiers has been a challenge faced by the radar and telecommunications industries for many years. Current linearization schemes include use of a predistortion circuit, a feedback error compensation loop or a feedforward error compensation loop.

With a predistortion circuit, the input to the amplifier is pre-distorted based on the characteristics of the amplifier to compensate for the distortion introduced by the amplifier. However, this technique offers very limited improvement as it ignores memory effects and is generally considered by the power amplifier community to be primarily an addition to a feedforward error compensation loop.

With a feedback error compensation loop, the input and output signals of the amplifier are compared and used to adjust the input to the amplifier. Many variations of feedback error compensation loops exist. For example, the adjustments can be proportional to magnitude and phase error between the two signals, or can be proportional to in-phase and quadrature amplitude error.

One problem with feedback error compensation loops is that the level of linearization achieved is somewhat modest due to limitations imposed by stability criteria. This is particularly true when the feedback error compensation loop is applied to a power amplifier operating in the high frequency range.

With a feedforward error compensation loop, the output of the amplifier is adjusted. Generally, a feedforward error compensation loop generates an error signal by comparing the input signal to the amplifier and the output signal produced by the amplifier, and then amplifying and filtering the result to obtain an error correction signal. By vectorial summation of the error correction signal and the output signal produced by the amplifier, the error or distortion introduced by the amplifier can be reduced. Specifically, the distortion is reduced because the distortion components in the error correction signal are in antiphase with the distortion components in the output signal produced by the amplifier.

While a higher level of linearization can be achieved with a feedforward error compensation loop, the feedforward error compensation loop is highly sensitive to device aging or component drift and the amplitude and phase matching must be maintained to a very high degree of accuracy over the band of interest.

SUMMARY

In one aspect, at least one of the embodiments described herein provides an analog amplification circuit. The analog amplification circuit comprises: an input port for receiving an input signal; a first signal path coupled to the input port, the first signal path comprising: a pre-amplification processing circuit configured to apply a first phase shift to the input signal to produce a processed input signal, wherein the first phase shift is controlled by a first phase control signal; a power amplifier coupled to the pre-amplification processing circuit, the power amplifier configured to divide the pre-processed input signal into a plurality of sub-signals, amplify the plurality of sub-signals to produce a plurality of intermediate signals, and combine the plurality of intermediate signals to produce an amplified signal, wherein the amplification is controlled by a plurality of gain control signals, and a combiner coupled to the power amplifier, the combiner configured to combine the amplified signal and an error correction signal to produce an output signal; a second signal path coupled to the input port, the second signal path comprising a phase comparator circuit configured to produce the first phase control signal based on a phase comparison of a delayed version of the input signal and one intermediate signal; a third signal path coupled to the input port, the third signal path comprising an amplitude comparator circuit configured to produce the plurality of gain control signals, wherein each gain control signal is based on the amplitude of the input signal and the amplitude of one of the intermediate signals; a fourth signal path coupled to the input port, the fourth signal path comprising an error detection circuit configured to produce the error correction signal based on a second delayed version of the input signal and the amplified signal; and an output port for outputting the output signal.

In another aspect, at least one of the embodiments described herein provides an analog amplification circuit comprising: an input port for receiving an input signal; a first signal path coupled to the input port, the first signal path comprising: a power amplifier coupled to the input port, the power amplifier configured to amplify the input signal to produce an amplified signal, and a first combiner coupled to the power amplifier, the first combiner configured to combine the amplified signal and an error correction signal to produce an output signal; a second signal path coupled to the input port, the second signal path comprising a carrier cancellation circuit configured to generate an error signal based on a delayed version of the input signal, a version of the amplified signal and a first phase balance control signal, wherein the error signal represents the distortion introduced by the power amplifier; an error cancellation circuit configured to generate the error correction signal based on the error signal and a second phase balance control signal; and a phase control circuit coupled to the carrier cancellation circuit, the phase control circuit configured to generate the first phase balance control signal based on the delayed version of the input signal and the version of the amplified signal and to generate the second phase balance control signal based on the first phase balance control signal and frequency related delays in the error cancellation circuit, wherein the first phase balance control signal is updated upon receiving a trigger signal to track a carrier frequency of the input signal; and an output port for outputting the output signal.

In a further aspect, at least one of the embodiments described herein provides a method for amplifying an input signal. The method comprising: applying a first phase shift to the input signal to generate a first phase shifted input signal, wherein the first phase shift is controlled by a first phase control signal; dividing the first phase shifted input signal into a plurality of sub-signals using a first stage of a power amplifier; amplifying the plurality of sub-signals to produce a plurality of intermediate signals using a second stage of the power amplifier, wherein the amplification is controlled by a plurality of gain control signals; combining the plurality of intermediate signals to produce an amplified signal using a third stage of the power amplifier; generating the first phase control signal based on a phase comparison of a delayed version of the input signal and one of the intermediate signals; generating the plurality of gain control signals, wherein each gain control signal is based on the amplitude of the input signal and the amplitude of one of the intermediate signals; generating an error correction signal based on a delayed version of the input signal and a version of the amplified signal; and combining the amplified signal and the error correction signal to produce an output signal.

In a further aspect, at least one of the embodiments described herein provides a method for amplifying an input signal, the method comprising: amplifying the input signal to produce an amplified signal using a power amplifier, wherein the amplified signal includes distortion introduced by the power amplifier; generating first and second phase control signals based on a delayed version of the input signal and the amplified signal wherein the first phase balance control signal represents a phase difference between the delayed version of the input signal after phase shifting and the version of the amplified signal and is updated upon receipt of a trigger signal to track a carrier frequency of the input signal; generating an error signal based on the delayed version of the input signal, the second phase balance control signal and the version of the amplified signal wherein the error signal represents distortion introduced by the power amplifier; generating an error correction signal based on the error signal; and combining the amplified signal and the error correction signal to produce an output signal, wherein the output signal includes less distortion than the amplified signal.

Further aspects and advantages of the embodiments described will appear from the following description taken together with the accompanying drawings.

DETAILED DESCRIPTION

It will be appreciated that numerous specific details are set forth in order to provide a thorough understanding of the example embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein may be practiced without these specific details. In other instances, well-known methods, procedures and components have not been described in detail so as not to obscure the embodiments described herein. Furthermore, this description is not to be considered as limiting the scope of the embodiments described herein in any way, but rather as merely describing the implementation of the various embodiments described herein.

Embodiments described herein relate to amplification circuits. In some embodiments the amplification circuit includes a power amplifier, a feedforward error compensation loop, and phase feedback and amplitude feedback error compensation loops nested within the feedforward loop. The two nested feedback loops provide a “pre-cleaning” action, which reduces the amount of rejection required in the feedforward loop. In some embodiments the amplification circuit includes a power amplifier and an enhanced feedforward loop comprising a phase control circuit. The phase control circuit maintains a phase difference of 180 degrees between a delayed version of the input signal to the power amplifier and the output signal produced by the power amplifier. This reduces the effect of component drift, aging, humidity and the like on the feedforward loop. In some embodiments, the amplification circuit includes a power amplifier, a feedforward error compensation loop, and phase feedback and amplitude feedback error compensation loops nested within the feedforward loop and the feedforward loop comprises the phase control circuit.

Reference is now made toFIG. 1, in which a block diagram of an analog amplification circuit100in accordance with a first embodiment is illustrated. The amplification circuit100comprises an input port104that receives an input signal116, four signal paths106,108,110and112that process the input signal116, and an output port114for outputting an output signal134. In some cases the input signal116is a radio frequency (RF) pulse coded signal.

The input signal116can be a variety of different types of signals. For example, the input signal116can be a radar signal such as a High Frequency Radio Frequency signal (HF-RF) that is input to radar transmitters for a variety of applications including high frequency surface wave radar (HFSWR). Such signals are typically pulses of amplitude modulated signals at a given carrier frequency. The generation of these signals is controlled by a pulse trigger signal, the use of which is described in further detail below. Alternatively, the input signal116can be a continuous wave signal that is used by telecommunication transmitters in base and repeater stations and the like. In either case, for some of the embodiments described herein the timing associated with the input signal (i.e. the pulse trigger signals for radar signals) is used for phase correction. This is described in further detail below.

In the main signal path106, the input signal116is sent to a pre-amplification processing circuit118, which alters the characteristics of the input signal116to produce a pre-processed input signal120. The pre-amplification processing circuit118applies a phase shift to the input signal116. In this embodiment the phase shift is controlled by an external phase control signal122. The phase shift may be performed at the carrier frequency instead of at base-band or intermediate frequency (IF). In other cases the pre-amplification processing circuit118also adjusts the amplitude of the input signal116.

The pre-processed input signal120is then passed to the power amplifier102. The power amplifier102may be any solid-state amplifier that works with an input signal116having a high peak to average ratio content or is pulsed. A first stage of the power amplifier102divides the pre-processed input signal120into a plurality of sub-signals. Each sub-signal is then amplified by a second stage of the power amplifier102to produce a plurality of intermediate signals124. The amplification is controlled by external gain control signals126. The intermediate signals124are then combined by a third stage of the power amplifier102to form an amplified signal128. In addition to amplifying the pre-processed input signal120, the power amplifier102also inherently introduces distortion into the intermediate and amplified signals124,128.

The amplified signal128is then sent to a combiner130. The combiner130is configured to combine the amplified signal128with an error correction signal132to produce an output signal134. Ideally the combination removes the distortion in the amplified signal128so that the output signal134comprises a non-distorted and amplified version of the input signal116.

The second signal path108includes a phase comparator circuit136which together with the main signal path106forms a phase feedback loop. Phase feedback loops generally adjust the phase of the input signal based on a dynamic comparison of the phase of the input signal to a power amplifier and the phase of the output signal produced by the power amplifier. However, the phase comparator circuit136does not compare the amplified signal128with the input signal116as do most phase feedback loops, but alternatively compares the phase of the input signal116to the phase of one of the intermediate signals124. By taking an internal or intermediate signal within the power amplifier102after amplification but before combination, the largest delay (i.e. the delay associated with power combining) is removed from the phase feedback loop.

Based on a phase comparison of the input signal116and one of the intermediate signals124, the phase comparator circuit136generates a phase control signal122. The phase control signal122is then transmitted to the pre-amplification processing circuit118in the main signal path106, where it is used to control the phase shift applied to the input signal116. Ideally, the phase shift applied to the input signal116prior to amplification will result in intermediate signals124that are in-phase with the original input signal116.

The third signal path110includes an amplitude comparator circuit138, which together with the main signal path106forms an amplitude feedback loop. Similar to phase feedback loops, amplitude feedback loops generally adjust the amplitude or amplification of the input signal based on a comparison of the amplitude of the input signal to a power amplifier and the amplitude of the output signal produced by the power amplifier. However, the amplitude comparator circuit138does not compare the amplified signal128with the input signal116as do most amplitude feedback loops, but alternatively compares the amplitude of the input signal116to the amplitude of one of the intermediate signals124. By taking an internal or intermediate signal within the power amplifier102after amplification but before combination, the largest delay (i.e. the delay associated with power combining) is removed from the amplitude feedback loop.

The amplitude comparator circuit138typically generates one gain control signal126for each in-phase pair of power unit amplifiers within the power amplifier102. For example, if the power amplifier102divides the input signal116into four sub-signals, each of the four sub-signals are then amplified by a power unit amplifier to produce intermediate signals124, and the intermediate signals124are then combined to form the amplified signal128. The power unit amplifiers are typically in pairs and each amplifier within a pair is in-phase with the other power unit amplifier of the pair, but each pair of amplifiers is phase offset from the other pair of amplifiers. Accordingly, in this example, two gain control signals126would be generated. One gain control signal is used for the first pair of in-phase power unit amplifiers and the other gain control signal is used for the second pair of in-phase power unit amplifiers.

Each gain control signal126is based on the comparison of the amplitude of the input signal116and the amplitude of one intermediate signal124generated by the pair of unit amplifiers. For example, say first and second power unit amplifiers of the power amplifier102are a pair, then the corresponding gain control signal may be based on a comparison of the amplitude of the input signal116and the amplitude of the intermediate signal124produced by either the first or second power unit amplifier. In traditional amplitude feedback loops the gain control signals126are used to control a pre-amplifier. However, in the present embodiment the gain control signals126are fed directly to the power amplifier102where they are used to control the amplification applied to the pre-processed input signal120.

Together the phase feedback loop and the amplitude feedback loop form a vector feedback loop.

The fourth signal path112includes an error detection circuit140which together with the main signal path106forms a feedforward error correction circuit. The error detection circuit140receives the input signal116and a signal142that is a version of the amplified signal128. The error detection circuit140then applies a delay to the input signal116that is preset to correspond as closely as possible with the amount of time that it takes for the input signal to be processed by the pre-amplification processing circuit118and the power amplifier102. The error detection circuit140then generates an error correction signal132based on a delayed version of the input signal116and the version of the amplified signal128. The error correction signal132is used to remove or at least reduce the distortion in the amplified signal128introduced by the power amplifier102. The signal142can be the same as the amplified signal128or it can be an attenuated version of the amplified signal128. The delayed input signal is then phase shifted to be in antiphase with or 180 degrees offset from the signal142. The delayed and phase shifted input signal is then combined with the signal142to produce an error signal. Ideally the combination of the signals cancels or removes the carrier signal in the signal142such that the error signal represents only the distortion imposed by the power amplifier102. The error signal is then amplified and phase adjusted to produce the error correction signal132. The error correction signal132is then combined with the amplified signal128by the combiner130to produce the output signal134, which is an amplified signal without the distortion or at least with reduced distortion.

Adding the nested phase feedback and amplitude feedback loops to the feedforward error correction loop reduces the amount of rejection required in the feedforward loop. Specifically, the two nested feedback loops perform a “pre-cleaning action”. They reduce the amount of distortion in the amplified signal128(and by extension signal142) and therefore less amplification of the error signal is required to remove the distortion. In some implementations, the amount of rejection required is reduced to about 20 dB.

Reference is now made toFIG. 2, in which a circuit diagram of an example of the amplification circuit100is illustrated. Amplification circuit100′ is shown as comprising a 1 kilowatt (kW) high frequency (HF) power amplifier102′ comprising a driver unit amplifier208, four power unit amplifiers210a,210b,210cand210d, a combiner212and a coupler213. However, the amplification circuit100′ may include power amplifiers with other configurations or that operate at other frequencies or over other frequency ranges.

As described with reference toFIG. 1, the main signal path106comprises a pre-amplification processing circuit118′, a power amplifier102′ and a combiner130. The main signal path106also includes an isolation amplifier202athat is coupled between the input port104and the pre-amplification processing circuit118′. The isolation amplifier202aelectrically isolates the components in the main signal path106from the circuit which produces the input signal116. The isolation amplifier202adrives the pre-amplification processing circuit118′. In some cases the isolation amplifier202ais optional.

The pre-amplification processing circuit118′ includes a phase shifter264which applies a phase shift to the input signal116to produce a phase shifted input signal206. The amount of the phase shift is controlled by a phase control signal122generated by a phase comparator circuit136′. The phase shifter264may be any suitable linear phase shifter.

The pre-amplification processing circuit118′ also includes a pre-amplifier204coupled to the phase shifter264. The pre-amplifier204amplifies the phase shifted input signal206to produce the pre-processed input signal120. The pre-processed input signal120is then fed to the power amplifier102′. The pre-amplifier204may be any suitable linear amplifier such as an APS148. In some cases the pre-amplifier204is optional.

The power amplifier102′ receives the pre-processed input signal120. The driver unit amplifier208divides the pre-processed input signal120into a plurality of sub-signals214a,214b,214cand214d. Each sub-signal214a,214b,214c,214dis fed to a power unit amplifier210a,210b,210cand210dand amplified to produce a plurality of intermediate signals124a,124b,124cand124d. In addition to providing amplification, the power unit amplifiers210a,210b,210cand210dtypically inherently introduce distortion in the intermediate signals124a,124b,124cand124d. The intermediate signals124a,124b,124cand124dare then combined by the combiner212to produce the amplified signal128. The power amplifier102′ also includes a directional coupler213for coupling a part of the power of the amplified signal128to produce the signal142. Accordingly, in this case the signal142is an attenuated version of the amplified signal128.

The amplified signal128is then sent to the combiner130where it is combined with the error correction signal132to produce the output signal134. In some cases the combiner130is a directional coupler that both isolates the power amplifier102′ from the error amplifier252of the error detection circuit140′ and provides resistive input impedances.

As described with reference toFIG. 1, the second signal path108includes the phase comparator circuit136′ that together with the main signal path106forms a phase feedback loop. The phase comparator circuit136′ compares the phase of the input signal116with the phase of an intermediate signal124dto generate a phase control signal122. Only one phase comparator circuit and resultant phase control signal122is required since the phase distortion is the same for all power unit amplifiers210a,210b,210cand210d.

In the embodiment shown inFIG. 2, the phase comparator circuit136′ includes a first delay circuit215, a pre-amplifier216, a phase comparator218, and a reference comparator220. The first delay circuit215imposes a delay on the input signal116to produce a first delayed input signal217. Typically the first delay circuit215is designed to impose the same delay imposed by the main signal path106up to and including the power unit amplifiers210a,210b,210cand210dof the power amplifier102′. The delays are designed to be equal so that when the phase comparator218compares the first delayed and pre-amplified input signal222and the intermediate signal124d, the two signals are aligned in time.

The first delayed input signal217is then fed to the pre-amplifier216. The pre-amplifier216amplifies the first delayed input signal217to produce a first delayed and pre-amplified input signal222. The first delayed and pre-amplified input signal222is then fed to the phase comparator218. One of the intermediate signals124dis extracted from the power amplifier102′ and also fed to the phase comparator218. The intermediate signal124dmay be extracted from the power amplifier102′ using a resistive divider (not shown) to avoid any additional delays in the second signal path108. The phase comparator218then generates a phase control signal122based on a comparison of the phase of the two signals as explained previously. In some cases the phase comparator218is a mixer such as a double balance mixer.

The phase control signal122is then fed to a reference comparator220, which compares the phase control signal122to a DC reference signal DC_ref1224. The DC reference signal224is selected so that this comparison reduces the dynamic phase nonlinearity by the loop gain. In order to avoid the injection of amplified thermal noise into the phase feedback loop and to avoid any unwanted phase transients, the gain of this loop is maintained to a low value. In one embodiment the gain of this loop is configured for approximately 50 degrees phase margin. This preserves the speed of the phase feedback loop and low loop phase distortion.

As described with reference toFIG. 1, the third signal path108comprises an amplitude comparator circuit138′, which together with the main signal path106forms an amplitude feedback loop. The amplitude comparator circuit138′ compares the amplitude of the input signal116to the amplitude of one or more intermediate signals124to generate one or more gain control signals126depending on the number of pairs of power unit amplifiers. In this case, since there are two pairs of power unit amplifiers, the amplitude of the input signal116is compared to the amplitude of two intermediate signals124aand124d, for example, to produce two gain control signals126a,126b.

In the embodiment shown inFIG. 2, the amplitude comparator circuit138′ comprises the first delay circuit215, a reference envelope detector226, two signal envelope detectors228a,228b, and two envelope comparators230a,230b. However, there can be alternative embodiments such as having multiple signal envelope detectors to take advantage of the Wiener-Khintchine theorem for uncorrelated random processes. In this case, the multiple signal envelope detectors operate in parallel and all receive the same input signal. For example, the envelope detectors226,228aand228bcan each be replaced by several envelope detectors connected in parallel with one another. The output signals from each group of multiple signal envelope detectors that are connected in parallel with one another are then averaged together. This compensates for variability in the transfer function of the envelope detectors since each group of envelope detectors will have an average transfer function that are close to one another so that when the outputs of the envelope detectors are compared by the envelope comparators230a,230b, additional distortion due to variability of the transfer function for multiple envelope detectors will be reduced.

As described above, the first delay circuit215imposes a delay on the input signal116to produce a first delayed input signal217. Typically the first delay circuit215is designed to impose the same delay as the delay imposed by the main signal path106up to and including the power unit amplifiers210a,210b,210c,210d.

The first delayed input signal217is then sent to the reference envelope detector226. The reference envelope detector226generates an envelope reference signal232from the first delayed input signal217. Each of the signal envelope detectors228a,228breceive an intermediate signal124a,124dand produce an envelope output signal234a,234b.

Each of the envelope comparators230a,230breceive the envelope reference signal232and one envelope output signal234aor234band produce an amplitude control signal126a,126bbased on a comparison of the envelope reference signal232and the envelope output signal234aor234b. Specifically, the envelope comparators230a,230bcompare the envelope shape of one of envelope output signals234a,234bagainst the envelope shape of the envelope reference signal232to determine the amount of distortion in the corresponding intermediate signal124and thus how much the gain should be increased or decreased to reduce the distortion. The amplitude control signals126a,126bare then fed to the corresponding power unit amplifier210a,210b,210c,210dto control the amplification imposed by the corresponding power unit amplifier210a,210b,210c,210dto reduce the amount of distortion.

In the embodiment shown inFIG. 2there are two signal envelope detectors228a,228band two envelope comparators230a,230bdue to the configuration of the power amplifier102. Specifically, the power amplifier102contains four power unit amplifiers210a,210b,210cand210dconfigured in pairs. The two power unit amplifiers that form a pair are in phase with each other, but the two pairs are 90 degrees offset from one another. Specifically, the first and second power unit amplifiers210a,210bform a first pair, and the third and fourth power unit amplifiers210c,210dform a second pair. The first and second power unit amplifiers210a,210bare in phase with each other and the third and fourth power unit amplifiers210c,210dare in phase with each other, but the first and second power amplifiers210a,210bare 90 degrees offset from the third and fourth power amplifiers210c,210d. Each pair then requires a different amplitude control signal. Accordingly, power amplifiers with different configurations (e.g. a different number of power unit amplifier pairs) may require a different number of second envelope detectors228and envelope comparators230.

In at least some implementations, the reference and signal envelope detectors226,228a,228bhave a push-pull configuration, followed by in-phase summation, to eliminate the carrier feed-through at low operating frequencies.

As described above, the phase feedback loop and the amplitude feedback loop form a full vector feedback loop.

As described with reference toFIG. 1, the fourth signal path110includes an error detection circuit140′, which together with the main signal path106forms a feedforward error correction loop. The error detection circuit140′ extracts an error signal236representative of the distortion in the amplified signal128′ and generates an error correction signal132based on the error signal236which is used to remove or at least reduce the distortion in the amplified signal128.

In the embodiment shown inFIG. 2, the error detection circuit140′ comprises a carrier cancellation circuit260and an error cancellation circuit262.

The carrier cancellation circuit260receives the input signal116and the signal142and generates an error signal236that represents the distortion in the amplified signal128. In the embodiment shown inFIG. 2, the carrier cancellation circuit260comprises a second delay circuit237, a phase shifter238, an amplifier240and a combiner242.

The second delay circuit237imposes a delay on the input signal116to produce a second delayed input signal243. Typically the second delay circuit237is designed to impose the same delay as the delay imposed by the main signal path106up to and including the power amplifier102. The same delay is imposed so that when the carrier cancellation circuit260combines the amplified signal246and the signal142the two signals are ideally aligned in time.

The phase shifter238applies a phase shift to the second delayed input signal243to produce a phase shifted signal244. The amplifier240then amplifies the phase shifted signal244to produce an amplified signal246. The amplified signal246is then sent to the combiner242where it is combined with signal142to produce an error signal236. The combiner242may be a high isolation hybrid or any other suitable combiner.

Typically the phase shifter238and the amplifier240are configured so that amplified signal246is in anti-phase or at a180degree offset with the signal142and equal in amplitude with the signal142so that when they are combined by the combiner242the carrier in the signal142is cancelled or removed, leaving only the distortion in the resultant error signal236.

The error cancellation circuit262receives the error signal236and generates an error correction signal132that, when combined with the amplified signal128by the combiner130, removes or at least reduces the distortion imposed by the power amplifier102′.

In the embodiment shown inFIG. 2, the error cancellation circuit262includes a phase shifter248, a low pass filter250, an error amplifier252and three isolation amplifiers254,256and258. In some cases, depending on the type of input signal116, the isolation amplifiers254,256and258may be optional. The isolation amplifiers254,256,258electrically isolate the electrical components directly following the isolation amplifiers from the preceding circuits. Specifically, the first isolation amplifier254electrically isolates the phase shifter248from the preceding circuits, the second isolation amplifier256electrically isolates the low pass filter250from the preceding circuits and the third isolation amplifier258electrically isolates the error amplifier252from the preceding circuits.

The phase shifter248applies a phase shift to the error signal236to produce a phase shifted error signal266. Typically the phase shifter248applies a phase shift that will result in the error correction signal132being in antiphase or at a180degree offset from the amplified signal128.

The low pass filter250receives the phase shifted error signal266and filters out all of the high frequencies to produce a filtered error signal268. The cutoff frequency of the filter250is selected such that it does not exceed one octave of the operating frequency of the amplifier102so that the second and higher harmonics of the signal266are removed. Removal of the high frequencies by the low pass filter250also allows the error amplifier252to have lower power requirements and therefore be a physically smaller amplifier.

The error amplifier252receives the filtered error signal268and amplifies it to produce the error correction signal132. Typically the error amplifier252amplifies the filtered error signal268so that the error correction signal132will have the same amplitude as the distortion in the amplified signal128.

Typically the larger the error signal236the larger the required amplification and thus the larger the error amplifier252. The larger the error amplifier252, the greater the power consumption and the lower the efficiency of the amplification circuit. Since the phase feedback and amplitude feedback error correction loops reduce the distortion in the amplified signal128and thus reduce the error signal236, a smaller error amplifier252can be used in the feedforward error correction loop than would be required in a feedforward loop without the feedback loops.

Reference is now made toFIG. 3in which a block diagram of an amplification circuit300in accordance with a second embodiment is illustrated. The amplification circuit300is similar to the amplification circuit100except that it only has two signal paths106and112and the error detection circuit140is enhanced with a phase control circuit302.

As with amplification circuit100, the input port104receives an input signal116which is coupled to the two signal paths106,112. In the main signal path106, the input signal116is sent to a pre-amplification processing circuit118, which alters the characteristics of the input signal116to produce a pre-processed input signal120. The pre-amplification processing circuit118applies a phase shift to the input signal116. The phase shift may be performed at the carrier frequency instead of at base-band or intermediate frequency (IF). In other cases the pre-amplification processing circuit118also adjusts the amplitude of the input signal116.

The pre-processed input signal120is then passed to the power amplifier102. As described above, the power amplifier102divides the pre-processed input signal120into a plurality of sub-signals. The sub-signals are then amplified to produce a plurality of intermediate signals. In addition to amplifying the sub-signals, the power amplifier102also inherently introduces distortions in the intermediate signals. The intermediate signals are then combined to form an amplified signal128′. It should be understood that in alternative embodiments other structures can be used for the power amplifier102. Accordingly, in this embodiment it is not necessary to produce and use intermediate signals in the power amplifier102as was described previously.

The amplified signal128′ is then sent to the combiner130. The combiner130is configured to combine the amplified signal128′ with an error correction signal332to produce an output signal334. Ideally, the combination removes the distortion from the amplified signal128′ and leaves only the amplified input signal in the output signal334.

The signal path112includes an error detection circuit340which together with the main signal path106forms a feedforward error correction loop. The error detection circuit340generates an error correction signal332that when combined with the amplified signal128′ will remove or at least reduce the distortion in the amplified signal128′. The error detection circuit340comprises a carrier cancellation circuit260, an error cancellation circuit262and a phase control circuit302.

The carrier cancellation circuit260generates an error signal336which is representative of the distortion in the amplified signal128′. Typically the generation of the error signal336involves imposing a delay on the input signal116by the delay block237where the delay amount is equal to the delay imposed by the main signal path106up to and including the power amplifier102. The delayed input signal is then phase shifted so that it is in antiphase or at a 180 degree offset from signal142′, which is a version of the amplified signal128′. For example, signal142′ can be the same as the amplified signal128′ or it can be an attenuated version of the amplified signal128′. The delayed and phase shifted input signal is then combined with signal142′ to produce the error signal336which is representative of the distortion in the amplified signal128′. The closer the two signals are to being exactly 180 degrees apart, the more accurate the error signal336will be. Specifically, the closer the phase offset is to 180 degrees, the more the carrier signal is cancelled or removed from signal142′. In many applications a phase error of less than two degrees is acceptable.

The error cancellation circuit262receives the error signal336produced by the carrier cancellation circuit260and produces an error correction signal332that when combined with the amplified signal128′ by the combiner130removes or at least reduces the distortion introduced by the power amplifier102. Typically this involves adjusting the phase and amplitude of the error signal336so that the error correction signal332is in antiphase or at a 180 degree offset with respect to the amplified signal128′ and has the same amplitude as the distortion of the amplified signal128′. The closer the two signals are to being exactly 180 degrees offset, the more effective the error correction signal332will be at removing the distortion.

The phase control circuit302is designed to maintain a 180 degree offset between (1) a phase-shifted delayed-version of the input signal116and signal142′; and (2) the error correction signal332and the amplified signal128′. The phase control circuit302generates two phase balance control signals304and338. The first phase balance control signal304controls the phase shift applied in the carrier cancellation circuit260to the delayed version of the input signal116. The phase control circuit302compares the delayed version of the input signal116to signal142′ and updates the phase balance control signal304based on a certain timing for the input signal116which is described in further detail below with respect toFIG. 4. By dynamically maintaining the 180 degree offset between a phase-shifted version of the input signal116and signal142, the effect of component drift, aging, humidity, and the like, on the linearity of the power amplifier102is significantly reduced.

The second phase balance control signal338controls the phase shift applied to the error signal336in the error cancellation circuit262. In some cases, the second phase balance control signal338is generated by passing the first phase balance control signal304through a level translation circuit. The level translation circuit adjusts the level of the first phase signal304so it compensates for any frequency specific delays in the error cancellation circuit262. This is described in further detail with respect toFIG. 4.

Reference is now made toFIG. 4in which a circuit diagram of an example implementation of a power amplification circuit300′ ofFIG. 3is illustrated. The main signal path106including the pre-amplification processing circuit118′, the power amplifier102′, and the combiner130, operates in the manner described in relation toFIG. 2. The carrier cancellation circuit260′ and error cancellation circuit262′ also operate in the manner described in relation toFIG. 2with the exception that the phase shifter238of the carrier cancellation circuit260′ is controlled by the first phase balance control signal304generated by the phase control circuit302′, and the phase shifter248of the error cancellation circuit262′ is controlled by the second phase balance control signal338generated by the phase control circuit302′.

The phase control circuit302′ compares the phase of amplified signal246and the phase of signal142′ and generates the two phase balance control signals304and338. The first phase balance control signal304controls phase shifter238of the carrier cancellation circuit260′ and the second phase balance control signal338controls phase shifter248of the error cancellation circuit262′.

In the embodiment shown inFIG. 4, the phase control circuit302′ comprises a phase comparator402, an amplifier404, a sample and hold circuit406, a pulse generator408, a level translation circuit410, three isolation amplifiers412,414, and416and a fixed phase shifter418. The fixed phase shifter418, phase comparator402and amplifier404can be considered to be a phase comparator stage. The three isolation amplifiers412,414,416are used to isolate the circuits immediately following the isolation amplifier from the preceding circuit. Specifically, the first isolation amplifier412isolates the phase comparator402from the preceding circuit, the second isolation amplifier414isolates the level translation circuit410from the preceding circuit, and the third isolation amplifier416isolates the phase shifter248from the preceding circuit. In some cases, depending on the particular application of the power amplification circuit300′ and the nature of the input signal116, the isolation amplifiers412,414and416may be optional.

The phase comparator402compares the phase of the amplified signal246and the phase of the signal142′ and generates a phase difference signal420. The phase comparator402may be a double balance mixer or any other suitable phase comparator. Prior to this comparison, the fixed phase shifter418applies a fixed preset phase shift so that the phase of the amplified signal246falls within the dynamic range of the mixer that is used to implement the phase comparator402. The fixed preset phase shift can be determined since the delay experienced by the signal142′ can be approximated by measurement and the dynamic range of the phase comparator402is known which may be on the order of 90 degrees.

The phase control circuit302′ operates to maintain the amplified signal246and the signal142′ in quadrature with one another. The first phase balance control signal304is adjusted and applied to the phase shifter248to achieve the quadrature of these two signals. Accordingly, the phase difference signal420is a quasi-DC signal which is roughly proportional to the cosine of the phase difference between the amplified signal246and the signal142′. The phase difference signal420and a DC reference signal DC_ref2422are then fed to the amplifier404which produces a phase balance signal424. The gain of the amplifier404provides a loop gain for a frequency tracking loop that exists from the phase shifter238to the sample and hold circuit406. The frequency tracking loop tracks the carrier frequency of the input signal as well as tracking changes due to operational drift of the amplifier102′ due to temperature, aging and the like.

The phase balance signal424is fed to a sample and hold circuit406. The sample and hold circuit406can be in one of two states, sample or hold. In the sample state, the sample and hold circuit406stops generating the phase balance control signal304and reads the phase balance signal424produced by the amplifier404and determines a new value for the phase balance control signal304. The sample and hold circuit406switches to the sample state when it receives a trigger signal426from the pulse generator408. The pulse generator408also generates the input signal116. Accordingly, the trigger signal426is in sync with the input signal116. The sample and hold circuit406then stays in the sample state for a predetermined period and then switches back to the hold state until it receives the next trigger signal426. For example, for a radar application in which pulse quadrature phase codes are used for the input signal116, the predetermined period may be equal to between 15 and 30 samples of the pulsed quadrature phase code. In the hold state, the sample and hold circuit406produces a DC value for the phase balance control signal304according to the last determined value. The DC value encodes the instantaneous carrier frequency of the input signal116. In this manner, the phase control circuit302′ is able to react to changes in the carrier frequency of the input signal in order to maintain a correct, constant phase balance inside the feedforward loop.

Referring now toFIG. 5, shown therein are several signals to illustrate the sampling that is performed by the sample and hold circuit406for a radar application. Signal450is a gate signal comprising pulses, one of which is shown. The signal450is used for generating radar pulses. The signal452shows the envelope for an amplitude modulated radar pulse which is used in the input signal116. It should be understood that within the envelope is a quickly varying signal at a certain carrier frequency which has not been shown to simplify the figure. The gate signal450can be used as the trigger signal to signify when the sample and hold circuit406should sample the phase balance signal424. The dotted lines454show the sampling period. Sampling is done to determine the value of the carrier frequency of the input signal116. However, the sampling is done on the phase balance signal424as shown. In this example, the phase balance control signal304encoded a previous carrier frequency at a frequency of F1and now encodes a carrier frequency at a frequency of F2. The phase balance control signal304also includes a transient during the transition in the determination of the carrier frequency during the operation of the frequency tracking loop. Accordingly, the output of the sample and hold circuit406is essentially a DC signal with transients (i.e. phase transients) when a new carrier frequency value is determined and in which the amplitude encodes the carrier frequency value. The sampling timing and duration is chosen to have minimum impact on the amplified signal spectrum.

Simulations show that the short phase transient in the phase control balance signal304will not degrade the linearization achieved by the circuit. In fact, the effect of the phase transients can only be seen below −100 dBC, which is not typically measurable.

The phase balance control signal304is also fed to a level translation circuit410which translates the phase balance control signal304to adjust its amplitude and produce the second phase balance control signal338for the phase shifter248of the error cancellation circuit262′. The second phase balance control signal338is used to maintain the error cancellation loop as balanced as possible so that the amplified signal128′ and the error correction signal332have a 180 degree phase difference between them even while the carrier frequency of the input signal116changes. Since the group delay of the filter250changes with frequency, the level translation circuit410applies a non-linear transfer function when adjusting the amplitude of the first phase balance control signal424. This adjustment compensates for the change in the group delay of the filter250with frequency when the frequency encoded in the phase balance control signal424changes in order to maintain the phase balance between the amplified signal128′ and the error correction signal332when they are combined to produce the output signal334.

Reference is now made toFIG. 6in which a block diagram of an analog amplification circuit500in accordance with a third embodiment is illustrated. The analog amplification circuit500is a combination of the two previously described analog amplification circuits100and300which results in an enhanced linear analog amplification circuit.

Specifically, the amplification circuit500comprises an input port104which receives an input signal116, four signal paths106,108,110, and112which process the input signal, and an output port114which outputs the output signal534. The main signal path106comprises a pre-amplification processing circuit118, a power amplifier102and a combiner130. The second signal path108comprises a phase comparator136, the third signal path110comprises an amplitude comparator138and the fourth signal path112comprises an error detection circuit340. The error detection circuit340comprises a carrier cancellation circuit260, an error cancellation circuit262and a phase control circuit302. Each of these components has been described in detail above.

Reference is now made toFIG. 7in which a circuit diagram of an example implementation of the analog amplification circuit500is illustrated. Each of these blocks have been previously described. With the analog amplification circuit500′ shown inFIG. 7, it is possible to produce an output signal534that is indistinguishable from the input signal116down to −74 dBC for any octave band between 3 and 20 MHz. Where operation above 20 MHz is required, some of the amplifiers may be replaced with high frequency devices. In addition, where the operating frequency of the power amplifier102′ is to switch instantaneously between two different octaves, for example 3 to 5 MHz and 10 to 20 MHz, then the delay circuits215and237and the filter250may be RF switched.

The linearization technique described herein is applicable to any solid state amplifier that is used with input signals having a high peak to average ratio or are pulsed. Examples of the linearization technique described herein related to the amplification of signals used in radar transmitters. The linearization techniques can provide amplified pulse-coded waveforms with reduced sidelobes.

The linearization technique with the enhanced feedforward processing described herein can be applied to any feedforward application regardless of carrier frequency, provided that the RF envelope of the input signal is not constant and has a high peak to average ratio. Since this is often the case with digital modulation, the enhanced feedforward technique described herein can be applied to telecommunication applications even if the carrier signal appears to be a continuous wave signal. In this case, the pulse generator408is modified to provide the timing required for the trigger signal426so that the sample and hold circuit406samples the phase balance signal424in a timely fashion to be able to determine changes in the carrier frequency of the input signal116. Otherwise, the remainder of the linearization techniques described herein can be applied without any further modifications for telecommunication applications.