MOS transistor having lower gate-to-source/drain breakdown voltage and one-time programmable memory device using the same

A MOS transistor includes a semiconductor substrate, a drain region and a source region in the semiconductor substrate, a channel region between the drain region and the source region, a gate electrode on the channel region, and a gate dielectric layer between the gate electrode and the semiconductor substrate. The gate dielectric layer has different thicknesses. The MOS transistor has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present disclosure relates generally to the field of semiconductor technology. More particularly, the present disclosure relates to a metal-oxide-semiconductor (MOS) transistor having lower gate-to-source/drain breakdown voltage and one-time programmable (OTP) memory devices using such MOS transistor.

2. Description of the Prior Art

As known in the art, non-volatile memory retains stored information even after power is removed from the non-volatile memory circuit. Some non-volatile memory designs permit reprogramming, while other designs only permit one-time programming. Thus, one form of non-volatile memory is a One-Time Programmable (OTP) memory.

An OTP memory may contain an antifuse. An antifuse functions oppositely to a fuse by initially being nonconductive. When programmed, the antifuse becomes conductive. To program an antifuse, a dielectric layer such as an oxide is subjected to a high electric field to cause dielectric breakdown or oxide rupture. After dielectric breakdown, a conductive path is formed through the dielectric and thereby makes the antifuse become conductive.

To read the memory cell, a current passing through the ruptured or unruptured oxide is typically required. However, some ruptured oxides could be in a soft breakdown condition. The leakage current of the oxide in soft breakdown condition could be small. Therefore, a complicate sensing amplifier is often needed to compare the source side and drain side gate oxide leakage currents.

SUMMARY OF THE INVENTION

It is one objective of the present disclosure to provide a MOS transistor having lower gate-to-source/drain breakdown voltage and OTP memory devices using such MOS transistor.

One aspect of the present disclosure provides a MOS transistor including a semiconductor substrate; a drain region and a source region in the semiconductor substrate; a channel region between the drain region and the source region; a gate electrode on the channel region; and a gate dielectric layer between the gate electrode and the semiconductor substrate, wherein the gate dielectric layer has different thicknesses, and wherein the MOS transistor has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage.

According to some embodiments, a first portion of the gate dielectric layer that is situated directly between the drain region and the gate electrode is thinner than a second portion of the gate dielectric layer that is situated directly between the channel region and the gate electrode.

According to some embodiments, a third portion of the gate dielectric layer that is situated directly between the source region and the gate electrode is thinner than the second portion of the gate dielectric layer that is situated directly between the channel region and the gate electrode.

According to some embodiments, the gate electrode comprises a main gate portion disposed directly above the channel region, and a first extension gate portion and a second extension gate portion disposed on two opposite sidewalls of the main gate portion, respectively.

According to some embodiments, the first extension gate portion of the gate electrode is situated directly on the first portion of the gate dielectric layer and the second extension gate portion of the gate electrode is situated directly on the third portion of the gate dielectric layer.

According to some embodiments, the first extension gate portion of the gate electrode is in direct contact with the first portion of the gate dielectric layer and the second extension gate portion of the gate electrode is in direct contact with the third portion of the gate dielectric layer.

According to some embodiments, the main gate portion, the first extension gate portion and the second extension gate portion of the gate electrode are composed of doped polysilicon, silicide, or metal.

According to some embodiments, the first extension gate portion of the gate electrode is covered with a first dielectric spacer and the second extension gate portion of the gate electrode is covered with a second dielectric spacer.

According to some embodiments, a first vertical PN junction, which is between the drain region and the channel region and is proximate to a top surface of the semiconductor substrate, is situated directly underneath the main gate portion of the gate electrode.

According to some embodiments, a second vertical PN junction, which is between the source region and the channel region and is proximate to the top surface of the semiconductor substrate, is situated directly underneath the main gate portion of the gate electrode.

Another aspect of the present disclosure pertains to a method for fabricating a metal-oxide-semiconductor (MOS) transistor. A semiconductor substrate having thereon a gate dielectric layer and a first conductive layer is provided. The first conductive layer is patterned into a main gate portion. An ion implantation process is performed to form a drain region and source region in the semiconductor substrate on two sides of the main gate portion, respectively. A channel region is formed between the drain region and the source region. By thinning down the gate dielectric layer after patterning the first conductive layer into the main gate portion, a first portion of the gate dielectric layer on the drain region, a second portion of the gate dielectric layer between the channel region and the main gate portion, and a third portion of the gate dielectric layer on the source region are formed. A first extension gate portion and a second extension gate portion are formed on two opposite sidewalls of the main gate portion, respectively, wherein the main gate portion, the first extension gate portion and the second extension gate portion constitute a gate electrode of the MOS transistor.

According to some embodiments, the method further includes: forming a first dielectric spacer and a second dielectric spacer on the first extension gate portion and the second extension gate portion, respectively.

According to some embodiments, the method further includes: forming a first salicide layer on the drain region and a second salicide layer on the source region.

According to some embodiments, the first portion and the third portion of the gate dielectric layer are thinner than the second portion of the gate dielectric layer.

According to some embodiments, the first extension gate portion of the gate electrode is situated directly on the first portion of the gate dielectric layer and the second extension gate portion of the gate electrode is situated directly on the third portion of the gate dielectric layer.

According to some embodiments, the first extension gate portion of the gate electrode is in direct contact with the first portion of the gate dielectric layer and the second extension gate portion of the gate electrode is in direct contact with the third portion of the gate dielectric layer.

According to some embodiments, a first vertical PN junction, which is between the drain region and the channel region and is proximate to a top surface of the semiconductor substrate, is situated directly underneath the main gate portion of the gate electrode.

According to some embodiments, a second vertical PN junction, which is between the source region and the channel region and is proximate to the top surface of the semiconductor substrate, is situated directly underneath the main gate portion of the gate electrode.

According to some embodiments, the MOS transistor has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage.

Another aspect of the present disclosure provides a one-time programmable (OTP) memory device comprising at least one MOS transistor, wherein the MOS transistor has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and a gated source/drain junction breakdown voltage.

DETAILED DESCRIPTION

Advantages and features of embodiments may be understood more readily by reference to the following detailed description of preferred embodiments and the accompanying drawings. Embodiments may, however, be embodied in many different forms and should not be construed as being limited to those set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey exemplary implementations of embodiments to those skilled in the art, so embodiments will only be defined by the appended claims. Like reference numerals refer to like elements throughout the specification.

Embodiments are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). Thus, these embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the embodiments.

It will be appreciated that although some conductivity types have been used for illustrative purposes, the invention may be practiced with opposite conductivity types. For example, an NMOS transistor in one embodiment may be replaced with a PMOS transistor in another embodiment without departing from the spirit and scope of the invention.

The present invention pertains to a MOS transistor having lower gate-to-source/drain breakdown voltage and OTP memory devices using such MOS transistor. The OTP memory devices may comprise a plurality of three-transistor (3T) bit cell structures in the OTP memory array. The OTP memory array utilizes the channel current, instead of ruptured or unruptured dielectric leakage current, for read operations. This invention has a great advantage over the prior art because the state “1” bit current is the transistor “on” current that is consistently high without too much variation other than those caused by manufacture process fluctuation, while the state “0” bit current is the very small transistor “off” current.

One aspect of the invention provides a semiconductor device including at least an OTP unit cell. A programming path for programming the OTP unit cell is different from a reading path for reading the OTP unit cell. According to some embodiments, the OTP unit cell comprises a programmable MOS transistor that is electrically programmed to “1” state or “0” state. According to some embodiments, the programmable MOS transistor is programmed to the “1” state by rupturing a gate dielectric layer between a gate and a drain of the MOS transistor. According to some embodiments, the programmable MOS transistor is programmed to “0” state by rupturing the gate dielectric layer between the gate and a source of the MOS transistor. According to some embodiments, the gate of the programmable MOS transistor is switched between ground and floating by a switching MOS transistor.

FIG. 1is a cross section of a semiconductor memory cell (or OTP unit cell) in accordance with one embodiment of the invention. According to one embodiment of the invention, the illustrated semiconductor memory cell may be a 3T bit cell structure that is included in an OTP memory array. As shown inFIG. 1, the semiconductor memory cell (or OTP unit cell)1comprises a read select transistor TRSthat is in series connection with a data storage transistor TDSfor storing a digit “1” or a digital “0” data. The read select transistor TRSand the data storage transistor TDSmay be constructed on the first active area101that is isolated by a first trench isolation structure TI1. The first active area101may be defined on a semiconductor substrate100having a first conductivity type, for example, P type. According to one embodiment, for example, the semiconductor substrate100may be a silicon substrate or a silicon-on-insulator (SOI) substrate, but not limited thereto.

The read select transistor TRSmay be used to “select” a memory cell for reading. According to one embodiment of the invention, the read select transistor TRScomprises a first gate G1, a first gate dielectric layer OX1between the first gate G1and the semiconductor substrate100, a first drain region D1in the semiconductor substrate100on one side of the first gate G1, and a first source region S1in the semiconductor substrate100on the other side of the first gate G1. According to one embodiment of the invention, the read select transistor TRSmay be an NMOS transistor, and the first drain region D1and the first source region S1may be N+doping regions. The first gate G1may be a single polysilicon (or single poly) layer or a metal gate.

According to one embodiment of the invention, the data storage transistor TDScomprises a second gate G2, a second gate dielectric layer OX2between the second gate G2and the semiconductor substrate100, a second drain region D2in the semiconductor substrate100on one side of the second gate G2, a second source region S2in the semiconductor substrate100on the other side of the second gate G2, and a channel region CH between the second drain region D2and the second source region S2. According to one embodiment of the invention, the data storage transistor TDSmay be an NMOS transistor, and the second drain region D2and the second source region S2may be N+doping regions. Likewise, the second gate G2may be a single polysilicon layer or a metal gate. Therefore, the read select transistor TRSand the data storage transistor TDSconstitute two serially connected NMOS transistors on the first active area101. The N+doping region132between the first gate G1and the second gate G2in the semiconductor substrate100is commonly shared by the read select transistor TRSand the data storage transistor TDS.

According to one embodiment of the invention, the portions204and206of the second gate dielectric layer OX2that are situated directly between and the second gate G2and, respectively the second drain region D2and the second source region S2are thinner than the portion202of the second gate dielectric layer OX2that is situated directly between the channel region CH and the second gate G2. Therefore, the second gate dielectric layer OX2has different thicknesses, thereby achieving a lower gate-to-source/drain breakdown voltage of the data storage transistor TDS.

Please refer toFIG. 16for the detailed MOS transistor structure.FIG. 16is a cross section of an exemplary MOS transistor suited for the data storage transistor having lower gate-to-source/drain breakdown voltage according to one embodiment of the invention, wherein like layers, elements or regions are designated by like numeral numbers or labels. As shown inFIG. 16, the MOS transistor T comprises a semiconductor substrate100, a drain region104and a source region106in the semiconductor substrate100, a channel region CH between the drain region104and the source region106, a gate electrode210disposed on the channel region CH, a gate dielectric layer200between the gate electrode210and the semiconductor substrate100. The gate dielectric layer200has different thicknesses. According to one embodiment of the invention, the portions204and206of the gate dielectric layer200that are situated directly between the gate electrode210and, respectively, the drain region104and the source region106are thinner than the portion202of the gate dielectric layer200that is situated directly between the channel region CH and the gate electrode210.

According to one embodiment of the invention, the gate electrode210comprises a main gate portion212disposed directly above the channel region CH and two extension gate portions214and216disposed on two opposite sidewalls of the main gate portion212. The extension gate portion214of the gate electrode210is situated directly on the portion204of the gate dielectric layer200and the extension gate portion216of the gate electrode210is situated directly on the portion206of the gate dielectric layer200. The extension gate portion214of the gate electrode210is in direct contact with the portion204of the gate dielectric layer200and the extension gate portion216of the gate electrode210is in direct contact with the portion206of the gate dielectric layer200. According to one embodiment of the invention, the main gate portion212, the extension gate portion214, and the extension gate portion216of the gate electrode210may be composed of doped polysilicon, silicide, or metal, but is not limited thereto.

The outer surface of the extension gate portion214of the gate electrode210is covered with a dielectric spacer224and the outer surface of the extension gate portion216of the gate electrode210is covered with a dielectric spacer226. According to one embodiment of the invention, for example, the dielectric spacers224and226may comprise silicon nitride, silicon oxynitride or silicon oxide, but is not limited thereto. According to one embodiment of the invention, an end surface204aof the portion204may be aligned with an outer surface of the dielectric spacer224and an end surface206aof the portion206may be aligned with an outer surface of the dielectric spacer226. According to one embodiment of the invention, the dielectric spacer224may be situated on the portion204of the gate dielectric layer200and the dielectric spacer226may be situated on the portion206of the gate dielectric layer200.

According to one embodiment of the invention, the MOS transistor T further comprises a self-aligned silicide (or salicide) layer232on the gate electrode210, a salicide layer234on the drain region104, and a salicide layer236on the source region106. According to one embodiment of the invention, salicide layers232,234and236may comprise NiSi, CoSi, TiSi, or WSi, but is not limited thereto. According to one embodiment of the invention, the salicide layer234is contiguous with the end surface204aof the portion204, and the salicide layer236is contiguous with the end surface206aof the portion206.

According to one embodiment of the invention, the vertical PN junctions104aand106a, which are proximate to the top surface of the semiconductor substrate100and are between the channel region CH and, respectively, the drain region104and the source region106are situated directly underneath the main gate portion212of the gate electrode210. By providing such configuration, a higher gated source/drain junction breakdown voltage can be provided. According to one embodiment of the invention, the MOS transistor T has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and the gated source/drain junction breakdown voltage.

Adverting toFIG. 1, the semiconductor memory cell1further comprises a program select transistor TPSthat is used to “select” a memory cell for programming. The program select transistor TPSis constructed on the second active area102that is isolated by a second trench isolation structure TI2. The second active area102may be disposed in close proximately to the first active area101. According to one embodiment of the invention, the program select transistor TPScomprises a third gate G3, a third gate dielectric layer OX3between the third gate G3and the semiconductor substrate100, a third drain region D3in the semiconductor substrate100on one side of the third gate G3, and a third source region S3in the semiconductor substrate100on the other side of the third gate G3. The third drain region D3is electrically coupled to the second gate G2.

According to one embodiment of the invention, the program select transistor TPSmay be an NMOS transistor, and the third drain region D3and the third source region S3may be N+doping regions. Likewise, the third gate G3may be a single polysilicon layer or a metal gate.

In another embodiment, as shown inFIG. 2, the semiconductor memory cell1acomprising the read select transistor TRS, the data storage transistor TDS, and the program select transistor TPSmay be constructed on a triple well structure comprising a deep N well110in the P type semiconductor substrate (P Substrate)100and a P well120isolated from the P type semiconductor substrate100by the deep N well110. During program or read operations, the P well may be biased to a predetermined P well voltage through a P well pickup region (not shown in this figure). It is understood that the illustrated transistors inFIG. 1andFIG. 2may further comprise other elements such as spacers on sidewalls of the gates or lightly doped drain (LDD) regions merged with the heavily doped source/drain regions, which are not explicitly shown in the figures for the sake of simplicity.

According to one embodiment of the invention, during operation, the first drain region D1is electrically coupled to a bit line voltage VBL, the first source region S1and the second drain region D2(i.e., the N+doping region132) are electrically floating, the second source region S2is electrically coupled to a source line voltage VSL, the third source region S3is electrically coupled to ground (GND), the first gate G1is electrically coupled to a read select voltage VRsel, and the third gate G3is electrically coupled to a program select voltage VPsel.

FIG. 3is a diagram showing an exemplary semiconductor memory array composed of the semiconductor memory cell as depicted inFIG. 1. It is understood that although only a 2×3 cell array are shown inFIG. 3, the semiconductor memory array may be an arbitrary N by M array comprising memory cells arranged in N rows and M columns, where N and M are arbitrary numbers. For example, the memory cell MC0at the crosspoint of the row R0and the column C0comprises the read select transistor TRS, the data storage transistor TDS, and the program select transistor TPSas described inFIG. 1. The first drain region D1of the read select transistor TRSis electrically connected to a bit line BL0, the second source region S2of the data storage transistor TDSis electrically connected to a source line SL0, the first gate G1of the read select transistor TRSis electrically connected to a read select line Rsel0, and the third gate G3of the program select transistor TPSis electrically connected to a program select line Psel0.

Please refer to Table 1 below,FIG. 4,FIG. 5, and briefly toFIG. 1andFIG. 2.FIG. 4shows the selected memory cell (or bit unit) of the semiconductor memory array.FIG. 5is a cross section of the selected data storage transistor TDSduring the program “1” operation. Table 1 shows exemplary bias conditions for programming digital “1” to the selected semiconductor memory cell inFIG. 4.

According to one embodiment of the invention, to program the selected bit unit to “1” state, the following bias conditions may be implemented:

(i) a program select voltage VPselof about 1-3V is applied to the selected program select line Psel(selected Psel) to turn on the program select transistor TPS;

(ii) a high enough read select voltage VRselranging between, for example, 3-10V may be applied to the selected read select line Rsel(selected Rsel);

(iii) all the unselected program select lines Psel(unselected Psel) and unselected read select lines Rsel(unselected Rsel) are connected to ground GND (or 0V);

(iv) the semiconductor substrate100(e.g., P Substrate) is usually connected to ground (VPSub=0V), and for the triple well structures as set forth inFIG. 2, the deep N well110is connected to ground (VDNW=0V) while the P well120may be floating or connected to ground (VPW=0V or floating);

(v) all the source lines SL and unselected bit lines BL are floating or connected to ground (0V); and

(vi) the selected bit line voltage VBLis ramped up, preferred to be through a current limiter to prevent overloading the bit line voltage supply circuit, until a sudden increase in current A and a sudden drop in voltage across the second gate dielectric layer OX2, indicating dielectric breakdown B, inFIG. 5, directly above the second drain region D2of the selected data storage transistor TDS.

Alternatively, the dielectric breakdown B may be caused by simply applying a pre-set bit line voltage VBLthat is higher than gate dielectric breakdown voltage (i.e., portion204OX2breakdown voltage), to the selected bit line, which is also preferred to be done through a current limiter to prevent overloading the bit line voltage supply circuit.

It is one technical feature of the invention that to write digital “1”, only the thinner portion204of the second gate dielectric layer OX2that is adjacent to the second drain region D2(i.e. drain side dielectric) is ruptured, while the portion206of the second gate dielectric layer OX2that is adjacent to the second source region S2(i.e. source side dielectric) and the portion202directly over the channel region CH (i.e. channel dielectric) are remained intact.

Preferably, the data storage transistor TDSmay have source junction breakdown voltage and drain junction breakdown voltage, which are higher than the gate dielectric breakdown voltage of the data storage transistor. However, this is not necessary for the embodiments with triple well structures as described inFIG. 2. Further, the gate dielectric breakdown voltage and the junction breakdown voltage of the read select transistor TRSare both higher than the gate dielectric breakdown voltage of the data storage transistor TDS. This can be achieved by using thicker gate dielectric or cascoding two transistors for the read select transistor TRS.

Please refer to Table 2 below,FIG. 6,FIG. 7, and briefly toFIG. 1andFIG. 2.FIG. 6shows the selected memory cell (or bit unit) in the semiconductor memory array.FIG. 7is a cross section of the selected data storage transistor TDsduring the program “0” operation. Table 2 shows exemplary bias conditions for programming digital “0” to the selected semiconductor memory cell inFIG. 6.

According to one embodiment of the invention, to program the selected bit unit to “0” state, the following bias conditions may be implemented:

(i) a program select voltage VPselof about 1-3V is applied to the selected program select line Psel(selected Psel) to turn on the program select transistor TPS;

(ii) all the unselected program select lines Psel(unselected Psel) are connected to ground (or 0V);

(iii) all the read select lines Rselare connected to 0V or don't care;

(iv) the semiconductor substrate100(e.g., P Substrate) is usually connected to ground (0V), and for the triple well structures as set forth inFIG. 2, the deep N well110is connected to ground (VDNW=0V) while the P well120may be floating or connected to ground (VPW=0V or floating);

(v) all the bit lines BL and unselected source lines SL are floating or connected to ground; and

(vi) the selected source line voltage VSLis ramped up, preferred to be through a current limiter to prevent overloading the source line voltage supply circuit, until a sudden increase in current A and a sudden drop in voltage across the second gate dielectric layer OX2, indicating dielectric breakdown B, inFIG. 7, directly on the second source region S2of the selected data storage transistor TDS.

Alternatively, the dielectric breakdown B may be caused by simply applying a pre-set source line voltage VSLthat is higher than gate dielectric breakdown voltage (i.e., portion206of OX2breakdown voltage), to the selected source line, which is also preferred to be through a current limiter to prevent overloading the source line voltage supply circuit.

It is another technical feature of the invention that to write digital “0”, only the portion206of the second gate dielectric layer OX2that is adjacent to the second source region S2(i.e. source side dielectric) is ruptured, while the portion204of the second gate dielectric layer OX2that is adjacent to the second drain region D2(i.e. drain side dielectric) and the portion202directly over the channel region CH (i.e. channel dielectric) are remained intact.

Please refer to Table 3 below,FIG. 8andFIG. 9.FIG. 8is a cross section of the data storage transistor TDSwith “1” state during read operation.FIG. 9is a cross section of the data storage transistor TDSwith “0” state during read operation. Table 3 shows exemplary bias conditions for reading data storage transistor TDS.

To read a memory cell, the following exemplary bias conditions may be implemented:

(i) all the program select lines Pselare connected to ground (0V) to turn off all program select transistors TPSso that all the second gates G2of the data storage transistors TDSare isolated from the outside bias. Therefore, voltage of the second gate G2of the data storage transistors TDSis the same as that of second drain region D2if the dielectric breakdown B, caused during the programming procedure, is on the drain side, and the same as that of second source region S2if the dielectric breakdown B is on the source side;

(ii) a read select voltage VRselof about 1-3V is applied to the selected read select lines Rselso that drain of the selected data storage transistors TDSis connected to the selected bit line BL to which a bit line voltage VBLof 0.5-2V is applied; and

(iii) all the other terminals are connected to ground (0V).

Under the aforesaid read bias conditions, the data storage transistors TDShas a high channel current CL if the dielectric breakdown B is on the drain side because the gate voltage is high, same as the voltage applied to the second drain region D2, and the data storage transistors TDS(“1” state) is turned on, as shown inFIG. 8. On the other hand, for the data storage transistors TDSin “0” state, there is no channel current (or only an insignificant amount of off-current) because the voltage coupled to the second gate G2is low, same as the voltage applied to the second source region S2, and the data storage transistors TDS(“0” state) is turned off, as shown inFIG. 9. Therefore, the read current path is not through the ruptured dielectric, but is through the channel region CH of the data storage transistor TDS.

According to some embodiments, all the isolated second gates G2of the data storage transistors TDSmay be pre-charged by turning on all read select transistors TRsimultaneously and applying 0.5-2V to all bit lines and 0V to all source line for a short period of time (e.g., 3 ms) prior to reading the entire OTP memory array. This can prevent those soft breakdown bits from errors due to slow charging.

FIG. 10toFIG. 17are schematic diagrams showing an exemplary method for fabricating a MOS transistor having lower gate-to-source/drain breakdown voltage according to one embodiment of the invention, wherein like layers, elements or regions are designated by like numeral numbers or labels.

As shown inFIG. 10, a semiconductor substrate100such as a P type silicon substrate is provided. A gate dielectric layer200such as silicon dioxide (SiO2), silicon oxynitride (SiON) or hafnium dioxide (HfO2), or the combination of two or more is deposited on the semiconductor substrate100. According to one embodiment, the gate dielectric layer200may have a thickness of about 2-20 nm, but is not limited thereto. A first conductive layer210asuch as N-doped polysilicon, silicide or metal is then deposited on the gate dielectric layer200. For example, the first conductive layer210ais an N-doped polysilicon layer. According to one embodiment, the first conductive layer210amay have a thickness of about 80-200 nm, but is not limited thereto. Optionally, a cap nitride layer230may be deposited on the first conductive layer210a. For example, the cap nitride layer230may be a silicon nitride layer and may have a thickness of about 5-10 nm.

It will be appreciated that although some conductivity types have been used for illustrative purposes, the invention may be practiced with opposite conductivity types.

Subsequently, as shown inFIG. 11, a photoresist pattern PR is formed on the cap nitride layer230to define gate area. An anisotropic etching process500is then performed to remove the cap nitride layer230and the first conductive layer210anot covered by the photoresist pattern PR, thereby forming a main gate portion212. At this point, the gate dielectric layer200is substantially not etched.

As shown inFIG. 12, the remaining photoresist pattern PR is removed. An ion implantation process600is then performed to implant N type dopants into the semiconductor substrate100, thereby forming N+drain region104and N+source region106. According to one embodiment, the N+drain region104and N+source region106may be formed with graded junction, which may be formed by using, for example, doubly diffused method, for higher junction breakdown voltage.

As shown inFIG. 13, an etching process is performed to remove an upper portion of the gate dielectric layer200, thereby forming a thinner portions204and206on the N+drain region104and N+source region106, respectively. The portions204and206may be thinned down to thickness of 30-70% of the original thickness. According to one embodiment, the etching process may be a wet etching process, but is not limited thereto. It is understood that in some embodiments the ion implantation process600inFIG. 12may be performed after gate dielectric thinning down.

As shown inFIG. 14, a second conductive layer210bsuch as N-doped polysilicon, silicide or metal is deposited on the semiconductor substrate100. The second conductive layer210bconformally covers the main gate portion212and the thinner portions204and206. The second conductive layer210bis in direct contact with the sidewalls of the main gate portion212. For example, the second conductive layer210bis an N-doped polysilicon layer. According to one embodiment, the second conductive layer210bmay have a thickness of about 20-100 nm,

As shown inFIG. 15, an anisotropic etching process700is then performed to etch the second conductive layer210b, thereby forming extension gate portions214and216on the opposite sidewalls of the main gate portion212. The extension gate portion214is situated directly on the portion204of the gate dielectric layer200and the extension gate portion216of the gate electrode210is situated directly on the portion206of the gate dielectric layer200.

As shown inFIG. 16, the cap nitride layer230is removed, optionally. After the removal of the cap nitride layer230, the top surface of the main gate portion212is revealed. Subsequently, a dielectric spacer224and a dielectric spacer226are formed on the gate dielectric layer200and the extension gate portions214and216of the gate electrode210, respectively. Removal of cap nitride layer230can also be achieved during formation of spacer224and spacer226. The formation of the dielectric spacers224and226may involve conformal deposition of a spacer material layer and anisotropic etch of the spacer material layer. In some embodiments, the cap nitride layer230is not removed prior to the conformal deposition of the spacer material layer, and the cap nitride layer230can be removed during anisotropic etch of the spacer material layer.

The outer surface of the extension gate portion214of the gate electrode210is covered with the dielectric spacer224and the outer surface of the extension gate portion216of the gate electrode210is covered with the dielectric spacer226. According to one embodiment of the invention, for example, the dielectric spacers224and226may comprise silicon nitride, silicon oxynitride or silicon oxide, but is not limited thereto. According to one embodiment of the invention, an end surface204aof the portion204is aligned with an outer surface of the dielectric spacer224and an end surface206aof the portion206is aligned with an outer surface of the dielectric spacer226.

A self-aligned silicidation process is then performed to form a salicide layer232on the gate electrode210, a salicide layer234on the drain region104, and a salicide layer236on the source region106. According to one embodiment of the invention, salicide layers232,234and236may comprise NiSi, CoSi, TiSi, or WSi, but is not limited thereto. According to one embodiment of the invention, the salicide layer234is contiguous with the end surface204aof the portion204, and the salicide layer236is contiguous with the end surface206aof the portion206. According to one embodiment of the invention, the salicide layer234is not in direct contact with the dielectric spacer224, and salicide layer236is not in direct contact with the dielectric spacer226.

According to one embodiment of the invention, the vertical PN junctions104aand106aproximate to the top surface of the semiconductor substrate100are situated directly underneath the main gate portion212of the gate electrode210. By providing such configuration, a higher gated source/drain junction breakdown voltage can be provided. According to one embodiment of the invention, the MOS transistor T has a gate-to-source/drain breakdown voltage that is lower than a gate-to-channel breakdown voltage and the gated source/drain junction breakdown voltage.

As shown inFIG. 17, an interlayer dielectric (ILD) layer240is then deposited on the semiconductor substrate100. The ILD layer240covers the MOS transistor T. Subsequently, a contact plug244and a contact plug246may be formed in the ILD layer240. An interconnect structure254and an interconnect structure256may be formed on the ILD layer240. The interconnect structure254is electrically connected to the drain region104through the contact plug244. The interconnect structure256is electrically connected to the source region106through the contact plug246.