STRUCTURES FOR A VERTICAL VARACTOR DIODE AND RELATED METHODS

Structures for a varactor diode and methods of forming same. The structure comprises a first semiconductor layer including a section on a substrate, a second semiconductor layer on the section of the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, and a doped region in the section of the first semiconductor layer. The section of the first semiconductor layer and the doped region have a first conductivity type, and the second semiconductor layer comprises silicon-germanium having a second conductivity type opposite to the first conductivity type, and the third semiconductor layer has the second conductivity type. The doped region contains a higher concentration of a dopant of the first conductivity type than the section of the first semiconductor layer. The second semiconductor layer abuts the first section of the first semiconductor layer along an interface, and the doped region is positioned adjacent to the interface.

BACKGROUND

The disclosure relates generally to semiconductor devices and integrated circuit fabrication and, in particular, to structures for a varactor diode and methods of forming a structure for a varactor diode.

Varactor diodes are electronic devices implemented in radiofrequency technologies to support applications like voltage-controlled oscillators, parametric amplifiers, and frequency multipliers. Varactor diodes are designed to exploit the voltage-dependent capacitance of a reversed-biased junction. Varactor diodes can be manufactured as either abrupt varactor diodes or hyperabrupt varactor diodes through a selection of the dopant concentration profile in the device cathode.

Improved structures for a varactor diode and methods of forming a structure for a varactor diode are needed.

SUMMARY

In an embodiment, a structure for a varactor diode is provided. The structure comprises a substrate, a first semiconductor layer including a section on the substrate, a second semiconductor layer on the section of the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, and a doped region in the section of the first semiconductor layer. The section of the first semiconductor layer and the doped region have a first conductivity type, and the second semiconductor layer comprises silicon-germanium having a second conductivity type opposite to the first conductivity type, and the third semiconductor layer has the second conductivity type. The doped region contains a higher concentration of a dopant of the first conductivity type than the section of the first semiconductor layer. The second semiconductor layer abuts the first section of the first semiconductor layer along an interface, and the doped region is positioned adjacent to the interface.

In an embodiment, a method of forming a structure for a varactor diode is provided. The method comprises forming a first semiconductor layer including a section on a substrate, forming a second semiconductor layer on the section of the first semiconductor layer, forming a third semiconductor layer on the second semiconductor layer, and forming a doped region in the section of the first semiconductor layer. The section of the first semiconductor layer and the doped region have a first conductivity type, the second semiconductor layer comprises silicon-germanium has a second conductivity type opposite to the first conductivity type, the third semiconductor layer has the second conductivity type, and the doped region contains a higher concentration of a dopant of the first conductivity type than the section of the first semiconductor layer. The second semiconductor layer abuts the section of the first semiconductor layer along an interface, and the doped region is positioned adjacent to the interface.

DETAILED DESCRIPTION

With reference toFIG.1and in accordance with embodiments of the invention, a semiconductor substrate10includes a semiconductor layer12, a dielectric layer14beneath the semiconductor layer12, and a substrate16beneath the dielectric layer14. The dielectric layer14has an upper interface with the semiconductor layer12and a lower interface with the substrate16, and the upper and lower interfaces are separated by the thickness of the dielectric layer14. The substrate16may be comprised of a semiconductor material, such as single-crystal silicon. The dielectric layer14may be comprised of a dielectric material, such as silicon dioxide, that is an electrical insulator. The semiconductor layer12may be separated, and electrically isolated, from the substrate16by the dielectric layer14. In an embodiment, the semiconductor layer12may be a device layer of a semiconductor-on-insulator substrate and the dielectric layer14may be a buried insulator layer of the semiconductor-on-insulator substrate.

A hardmask18may be formed on the semiconductor layer12. The hardmask18may be a bilayer that includes a layer of silicon dioxide on the semiconductor layer12and a layer of silicon nitride on the silicon dioxide layer. The hardmask18may be patterned by lithography and etching processes to define an opening that exposes a surface area of the semiconductor layer12.

A trench20may be formed that penetrates through the semiconductor layer12and the dielectric layer14to the substrate16. The trench20may be formed at the location of the opening in the hardmask18by an etching process with reliance on the hardmask18as an etch mask. The bottom of the trench20may be coextensive with the substrate16.

A doped region22is formed in the substrate16adjacent to the bottom of the trench20. The doped region22is positioned in elevation below the dielectric layer14. In an embodiment, the doped region22may be coextensive (i.e., share a boundary) with the substrate16at the bottom of the trench20. The doped region22may be formed by introducing a dopant by, for example, ion implantation into the substrate16. The hardmask18may operate as an implantation mask that defines a selected area that is exposed for the implantation of ions and that self-aligns the implantation. The opening in the hardmask18determines the location and horizontal dimensions of the doped region22adjacent to the bottom of the trench20. The hardmask18has a thickness and stopping power sufficient to block the implantation of ions in masked areas. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to tune the electrical and physical characteristics of the doped region22. In an embodiment, the doped region22may be doped with a concentration of an n-type dopant (e.g., arsenic) to provide n-type conductivity. The bottom of the trench20may be temporarily covered by a pad layer comprised of, for example, silicon dioxide during implantation, and a drive-in anneal may be performed following implantation.

With reference toFIG.2in which like reference numerals refer to like features inFIG.1and at a subsequent fabrication stage, a semiconductor layer24is formed inside the trench20on the substrate16at the bottom of the trench20and over the doped region22. The dielectric layer14is positioned on the substrate16adjacent to semiconductor layer24and may surround the semiconductor layer24. A portion of the semiconductor layer24extends in a vertical direction above the dielectric layer14. The semiconductor layer24may be formed by a non-selective epitaxial growth process and may be planarized by chemical-mechanical polishing. The semiconductor layer24may be comprised of a single-crystal semiconductor material (e.g., single-crystal silicon). The crystal structure of the single-crystal semiconductor material of the substrate16at the bottom of the trench20serves as a crystalline template for the epitaxial growth of the semiconductor layer24. The semiconductor layer24may be doped during epitaxial growth with a concentration of a dopant, such as an n-type dopant (e.g., arsenic) to provide n-type conductivity. The hardmask18may be removed after forming the semiconductor layer24.

With reference toFIG.3in which like reference numerals refer to like features inFIG.2and at a subsequent fabrication stage, a hardmask25may be formed that includes sections positioned on the semiconductor layer24. The hardmask25may be a bilayer that includes a layer of silicon dioxide on the semiconductor layer24and a layer of silicon nitride on the silicon dioxide layer. The hardmask25may be patterned by lithography and etching processes to define the sections that are positioned on the semiconductor layer24.

The semiconductor layer24is patterned to form trenches that define a section26, a section28, and a thinned section30that connects the sections26,28. The semiconductor layer24may be patterned by an etching process with reliance on the hardmask25as an etch mask. The hardmask25covers and protects the sections26,28during the etching process, and the etching process is controlled to not penetrate fully through the semiconductor layer24. The section30is positioned in a vertical direction between the sections26,28and the substrate16, and the sections26,28project in a vertical direction away from the section30. In an embodiment, the sections26,28of the semiconductor layer24may be positioned in elevation above the dielectric layer14, and the thinned section30may have the same elevation as the dielectric layer14. The section30may have a thickness T, the sections26,28may have a height H that is greater than the thickness T, and the sum of the height H and the thickness T may be equal to the original thickness of the semiconductor layer24.

With reference toFIG.4in which like reference numerals refer to like features inFIG.3and at a subsequent fabrication stage, the hardmask25is removed, and shallow trench isolation regions32are formed by filling the spaces around and between the sections26,28of the semiconductor layer24with a dielectric material. In particular, one of the shallow trench isolation regions32is positioned between the section26and the section28. In an embodiment, the dielectric material may be silicon dioxide that is deposited and planarized by chemical-mechanical polishing.

With reference toFIG.5in which like reference numerals refer to like features inFIG.4and at a subsequent fabrication stage, a doped region34may be formed in the section28of the semiconductor layer24and the portion of the section30underlying the section28. The doped region34and the doped region22contribute to a reach-through connection to the section26of the semiconductor layer24. In an embodiment, the doped region34may extend over the full height of the section28of the semiconductor layer24and the thickness of the section30of the semiconductor layer24beneath the section28. In an embodiment, the doped region34may abut or adjoin the doped region22. The doped region22extends laterally in the substrate16from the section26of the semiconductor layer24to the section28of the semiconductor layer24such that the doped region34is coupled to the section26of the semiconductor layer24.

The doped region34may be doped to have the same conductivity type as the doped region22, as well as the same conductivity type as the section26of the semiconductor layer24. In an embodiment, the doped region34may contain a concentration of an n-type dopant (e.g., arsenic) to provide n-type conductivity. The doped region22and the doped region34may each contain a higher dopant concentration than the section26of the semiconductor layer24.

The doped region34may be formed by introducing a dopant by, for example, ion implantation into the section28of the semiconductor layer24. A patterned implantation mask may be formed that exposes the section28of the semiconductor layer24for the implantation of ions. The implantation mask may include a layer of an organic photoresist that is applied and patterned to form an opening aligned with the section28of the semiconductor layer24. The implantation mask has a thickness and stopping power sufficient to block the implantation of ions in masked areas. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to tune the electrical and physical characteristics of the doped region34.

With reference toFIG.6in which like reference numerals refer to like features inFIG.5and at a subsequent fabrication stage, dielectric layers36,38are formed and patterned by lithography and etching processes to define an opening that exposes the section26of the semiconductor layer24. In an embodiment, the dielectric layer36may be comprised of silicon nitride, and the dielectric layer38may be comprised of silicon dioxide.

A semiconductor layer40is formed that includes a section inside the opening in the dielectric layers36,38and on the section26of the semiconductor layer24. The semiconductor layer40is positioned in elevation above the dielectric layer14. The semiconductor layer40, which has a top surface41, may abut or adjoin the section26of the semiconductor layer24along an interface43.

The semiconductor layer40on the section26of the semiconductor layer24may contain single-crystal semiconductor material that is epitaxially grown. In that regard, the semiconductor layer40may be formed by the epitaxial growth of semiconductor material from the surface of the section26of the semiconductor layer24, which is exposed by the opening in the dielectric layers36,38. In an embodiment, the semiconductor material of the semiconductor layer40may be comprised of silicon-germanium. In an embodiment, the semiconductor material of the semiconductor layer40may be comprised of silicon-germanium including silicon and germanium with the silicon content ranging from 95 atomic percent to 50 atomic percent and the germanium content ranging from 5 atomic percent to 50 atomic percent. In an embodiment, the semiconductor layer40may have a germanium content that is graded, for example, in a vertical direction, which may be accomplished during epitaxial growth by varying the reactant mixture. In an embodiment, the semiconductor layer40may be in situ doped during epitaxial growth with a concentration of a dopant, such as a p-type dopant (e.g., boron) that provides p-type conductivity. In an embodiment, the semiconductor layer40may be uniformly doped with a p-type dopant.

A doped region42may be formed in an upper portion of the section26of the semiconductor layer24and below the semiconductor layer40. The doped region42is positioned in elevation above the dielectric layer14. In an embodiment, the doped region42may be doped (i.e., lightly doped) with a concentration of an n-type dopant (e.g., arsenic) to provide n-type conductivity. The doped region42may be formed by introducing a dopant by, for example, ion implantation into the section26of the semiconductor layer24. A patterned implantation mask may be formed that exposes the semiconductor layer40over the section26of the semiconductor layer24for the implantation of ions. The implantation mask may include a layer of an organic photoresist that is applied and patterned to form an opening aligned with the section26of the semiconductor layer24. The implantation mask has a thickness and stopping power sufficient to block the implantation of ions in masked areas. The implantation conditions (e.g., ion species, dose, kinetic energy) may be selected to tune the electrical and physical characteristics of the doped region42. The dielectric layers36,38mask the section28of the semiconductor layer24during the formation of the doped region42.

The doped region42may be doped to have an opposite conductivity type from the semiconductor layer40. In an embodiment, the doped region42may be coextensive with the interface43at which the semiconductor layer40abuts the section26of the semiconductor layer24. The doped region42has the same conductivity type as the portion of the section26of the semiconductor layer24between the doped region42and the doped region22. The doped region42contains a higher dopant concentration than the portion of the section26of the semiconductor layer24between the doped region42and the doped region22. The doped region42provides a locally-increased dopant concentration in the section26of the semiconductor layer24that is positioned adjacent to the interface43between the section26and the semiconductor layer40, which results in a non-uniform vertical dopant profile in the section26.

With reference toFIG.7in which like reference numerals refer to like features inFIG.6and at a subsequent fabrication stage, a semiconductor layer44is formed on the top surface41of the semiconductor layer40. The semiconductor layer44is positioned in elevation above the dielectric layer14. The semiconductor layer40is positioned in a vertical direction between the semiconductor layer44and the section26of the semiconductor layer24. In an embodiment, the semiconductor layer44may adjoin the semiconductor layer40. In an embodiment, the semiconductor layer44may directly contact the semiconductor layer40along an interface at the top surface41. The semiconductor layer44may have a different composition than the semiconductor layer40. In an embodiment, the semiconductor layer44may comprise a semiconductor material, such as silicon or silicon-germanium, that is doped to have the same conductivity type as the semiconductor layer40. In an embodiment, the semiconductor layer44may comprise silicon-germanium containing a germanium concentration that is less than the germanium concentration in the semiconductor layer40. In an embodiment, the semiconductor layer44may comprise silicon-germanium containing a germanium concentration of less than or equal to than 20 atomic percent. In an embodiment, the semiconductor layer44may be doped (e.g., heavily doped) with a concentration of a dopant, such as a p-type dopant (e.g., boron) that provides p-type conductivity. In an embodiment, the semiconductor layer44may have a higher dopant concentration than the semiconductor layer40.

With reference toFIG.8in which like reference numerals refer to like features inFIG.7and at a subsequent fabrication stage, the semiconductor layer40and the semiconductor layer44are patterned by lithography and etching processes using a hardmask to provide device isolation for a varactor diode. The semiconductor layer40is positioned in a vertical direction between the semiconductor layer44and the section26of the semiconductor layer24. The doped region42is positioned in the section26adjacent to the interface43with the semiconductor layer40.

With reference toFIG.9in which like reference numerals refer to like features inFIG.8and at a subsequent fabrication stage, a dielectric layer46is deposited and planarized, and contacts48,50are formed in the dielectric layer46. The dielectric layer46is comprised of a dielectric material, such as silicon dioxide, that is an electrical insulator. The contacts48,50are comprised of a metal, such as tungsten, and may be formed in openings patterned in the dielectric layer46. The contact48is physically and electrically coupled to the semiconductor layer44, and the contact50is physically and electrically coupled to the section28of the semiconductor layer24. The doped region34in the section28of the semiconductor layer24and the doped region22in the substrate16physically and electrically couple the contact50to the section26of the semiconductor layer24. The dielectric layers36,38may be removed from over the section28of the semiconductor layer44, and a silicide layer (not shown) may be formed on the semiconductor layer44and the section28of the semiconductor layer24.

The device structure may be characterized as a vertical varactor diode that includes the section26of the semiconductor layer24as a cathode, which is formed on the substrate16. The doped region34in the section28of the semiconductor layer24provides a cathode reach-through connection that extends through the dielectric layer14to the doped region22in the substrate16, which is coupled to the cathode. The vertical varactor diode includes an anode defined by the semiconductor layer40and a semiconductor layer44, which are arranged in elevation over the dielectric layer14. The doped region42, which is included in the cathode, provides a perturbation to the dopant concentration profile within the section26of the semiconductor layer24. In particular, the vertical varactor diode may be characterized as a hyperabrupt varactor diode because of the doped region42that abuts, and defines a p-n junction with, the oppositely-doped semiconductor layer44. The vertical hyperabrupt varactor diode may exhibit an enhanced capacitive tuning ratio and a high quality factor.

In an alternative embodiment, the section26may be positioned between the section28and another section of the semiconductor layer24to provide a symmetrical construction for the vertical varactor diode. The section26of the semiconductor layer24may be symmetrically positioned in a lateral direction between the section28of the semiconductor layer24and the added section of the semiconductor layer24. The added section of the semiconductor layer24may include a doped region, similar to the doped region34, that provides another cathode reach-through connection that extends through the dielectric layer14to the doped region22in the substrate16.

The formation of the varactor diode may be integrated into a silicon-germanium BiCMOS process flow forming a vertical heterojunction bipolar transistor on the semiconductor substrate10. For example, the semiconductor material of the semiconductor layer40may be used to form an intrinsic base of the vertical heterojunction bipolar transistor, and the semiconductor material of the semiconductor layer44may be used to form an extrinsic base of the vertical heterojunction bipolar transistor.

With reference toFIG.10and in accordance with alternative embodiments, a modified region54may be formed in the substrate16. The modified region54may have a higher electrical resistivity than unmodified portions of the substrate16adjacent to the modified region54. In an embodiment, the modified region54may include argon and boron introduced by implantations into the substrate16, which may be performed early in the process flow. In an embodiment, the modified region54may surround the doped region22on multiple sides and may fully separate the doped region22unmodified portions of the substrate16adjacent to the modified region54. The modified region54may be effective to reduce the capacitance of the varactor diode in order to further improve the capacitive tuning ratio and may also be effective to improve the breakdown voltage.

With reference toFIG.11and in accordance with alternative embodiments, the shallow trench isolation regions32may be recessed relative to the sections26,28of the semiconductor layer24such that the sections26,28extend above the shallow trench isolation regions32and such that corners of an upper portion of the section26and an upper portion of section28are exposed. The semiconductor layer40, when formed, may wrap about the exposed corners of the upper portion of the section26of the semiconductor layer24. As a result, the semiconductor layer40is positioned adjacent to the doped region42at the sidewall of each exposed corner, as well as adjacent to the doped region42at a top surface of the section26of the semiconductor layer24that is coextensive with the interface43. The interface43between the semiconductor layer40and the section26of the semiconductor layer24is positioned above the shallow trench isolation regions32, and the doped region42may be positioned at least in part above the shallow trench isolation regions32.

References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction in the frame of reference perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction in the frame of reference within the horizontal plane.