Fermi threshold field effect transistor

A field effect transistor (FET) operates in the enhancement mode without requiring inversion by setting the device's threshold voltage to twice the Fermi potential of the semiconductor material. The FET, referred to as a Fermi Threshold FET or Fermi-FET, has a threshold voltage which is independent of oxide thickness, channel length, drain voltage and substrate doping. The vertical electric field in the channel becomes zero, thereby maximizing carrier mobility, and minimizing hot electron effects. A high speed device, substantially independent of device dimensions is thereby provided, which may be manufactured using relaxed groundrules, to provide low cost, high yield devices. Temperature dependence of threshold voltage may also be eliminated by providing a semiconductor gate contact which neutralizes the effect of substrate contact potential. Source and drain subdiffusion regions may be provided to simultaneously maximize the punch-through and impact ionization voltages of the devices, so that the short channel devices do not require scaled-down power supply voltages. Multi gate devices may be provided. An accelerator gate, adjacent the drain, may further improve performance.

FIELD OF THE INVENTION 
This invention relates to field effect transistor devices, and more 
particularly to high speed field effect transistors having operational 
characteristics which are independent of device dimensions, operating 
temperature and doping concentrations. 
BACKGROUND OF THE INVENTION 
Field Effect Transistors (FET's) have become the dominant active device for 
Very Large Scale Integration (VLSI) and Ultra Large Scale Integration 
(ULSI) applications, because the integrated circuit FET is by nature a 
high impedance, high density, low power device. Much research and 
development activity has focused on improving speed and density of FETs, 
and on lowering the power consumption thereof. 
As is well known to those having skill in the art there are two types of 
FET devices: the Insulated Gate FET (IGFET) and the Junction FET (JFET). 
Most present day integrated circuit technology employs the IGFET because 
of its simplified construction for integrated circuit applications. An 
IGFET typically comprises source and drain regions in a semiconductor 
substrate at a first surface thereof, and a gate region therebetween. The 
gate comprises an insulator on the first substrate surface between the 
source and drain regions, with a gate electrode or contact on the 
insulator. A channel is formed in the semiconductor substrate beneath the 
gate electrode, and the channel current is controlled by a voltage at the 
gate electrode. 
In the most common configuration of an IGFET, an oxide layer is grown or 
otherwise formed on the first semiconductor surface, between the source 
and drain regions, and a metal or other gate electrode is formed on the 
oxide layer. This structure is commonly called a Metal Oxide Semiconductor 
Field Effect Transistor (MOS or MOSFET). The terms MOS and MOSFET are now 
used interchangeably with IGFET to include devices in which the insulator 
is a material other than an oxide (for example a nitride), and the gate 
electrode is a material other than metal (for example polysilicon). These 
terms will be used interchangeably herein. 
Two types of channels may be provided in MOS devices. The first is referred 
to as an "induced channel", in which gate voltage induces a field in the 
substrate under the gate to thereby draw electrons (for a P-type 
substrate) into the region beneath the gate. As a result, this region 
changes conductivity type (e.g. P-type to N-type), and an induced channel 
is formed. The induced change of semiconductor material from one 
conductivity type to opposite conductivity type is called "inversion". 
Increasing gate voltage enhances the availability of electrons in the 
channel, so that an induced channel MOS device is referred to as operating 
in an "enhancement" mode. 
The second type of channel is a "diffused channel" in which a channel 
having conductivity opposite that of the substrate is formed beneath the 
gate electrode. In such a device, current flows between source and drain 
even in the absence of gate voltage. Decreasing gate voltage causes 
current to decrease as the diffused channel is depleted of carriers. 
Increasing gate voltage causes the gate current to increase as the 
diffused channel is enhanced. Accordingly, a diffused channel MOS device 
may operate in "enhancement" or "depletion" modes. 
Enhancement mode (induced channel) devices are preferred for digital 
integrated circuit applications because these devices are off at zero gate 
voltage. Both enhancement and depletion mode devices have a threshold 
voltage associated therewith. The threshold voltage is the value of gate 
voltage needed to initiate device conduction. Threshold voltage is an 
important MOS characteristic and must be well controlled to provide 
satisfactory integrated circuit devices. 
Unfortunately, the threshold voltage of known MOS devices typically varies 
as a function of the oxide thickness, the length of the channel, drain 
voltage, and the substrate doping concentration. Since each of these 
parameters can vary dramatically from one integrated circuit to another, 
very strict manufacturing tolerances (often referred to as "groundrules") 
must be provided to ensure device uniformity. However, strict 
manufacturing ground rules lower device yields. Moreover, since device 
dimensions and doping levels become more difficult to control as the 
devices become smaller, increases in device density and operating speed 
are difficult to obtain. 
The threshold voltage of conventional MOS devices also varies as a function 
of device temperature. Unfortunately, device operating temperature varies 
considerably from one integrated circuit to another, depending upon the 
application. In fact, operating temperatures vary considerably within an 
integrated circuit, depending upon the duty cycle of the individual 
devices. MOS devices must be designed to operate properly despite the 
variation in threshold voltage with temperature. As such, lower 
performance and lower speed must be specified to ensure proper operation 
at all operating temperatures. 
Many techniques have been proposed in an attempt to control threshold 
voltage while maintaining acceptable process groundrules; however such 
techniques cannot fully overcome the inherent variability of threshold 
voltage in the conventional FET structure. Other attempts have been made 
to improve the basic structure of the FET to provide improved 
characteristics. For example, a publication entitled A Normally-Off Type 
Buried ChanneI MOSFET For VLSI Circuits, by K. Nishiuchi et al. (IEDM 
Technical Digest, 1979, pages 26-29) discloses a buried channel, MOSFET 
that uses a bulk region as a conducting channel in contrast with the 
surface channel of a conventional device. Another publication entitled The 
Junction MOS (JMOS) Transistor--A High Speed Transistor For VLSI, by E. 
Sun et al. (IEDM Digest, 1980, pages 791-794) discloses a MOS device using 
a layered N-P P-junction structure beneath a MOS gate region. 
The art has heretofore not exhaustively investigated the origin of 
threshold voltage in FETs and the reasons for variation of threshold 
voltage with device characteristics. Accordingly, the art has heretofore 
not provided an FET design which minimizes variations of threshold voltage 
by eliminating those characteristics which contribute to this variation. 
Miniaturization of MOS devices for VLSI and ULSI designs has also created 
other problems. For example, short channel devices are increasingly prone 
to breakdown due to well known punch-through and impact ionization 
effects. In order to prevent such breakdown, short channel devices have 
employed scaled down input (supply) voltage, for example, 3 V instead of 
the standard 5 V supplies heretofore employed. However, as is well known 
to those having skill in the art, decreasing supply voltage causes 
threshold voltage to become a greater fraction of the supply voltage, 
thereby reducing device speed and negating the advantage of short channel 
devices. 
Finally, as device density further increases, it has become more difficult 
to provide ohmic (i.e. non-rectifying) contacts to these devices. Complex 
contact metallurgy schemes have been developed in an attempt to provide 
satisfactory, high density ohmic contacts. Complex contact metallurgy 
creates manufacturing problems and cannot fully compensate for poor ohmic 
contacts themselves. 
SUMMARY OF THE INVENTION 
It is therefore an object of the invention to provide improved field effect 
transistor devices. 
It is another object of the invention to provide improved MOS devices. 
It is yet another object of the invention to provide high speed MOS 
devices. 
It is still another object of the invention to provide high speed MOS 
devices having a threshold voltage which is independent of insulator 
thickness, channel length, drain voltage, substrate doping and 
temperature. 
It is a further object of the invention to provide high density, high speed 
MOS devices which may be manufactured with relaxed ground rules to thereby 
increase device yields. 
It is yet a further object of the invention to provide high density MOS 
devices which operate at full supply voltage without the risk of breakdown 
due to punch-through or impact ionization. 
It is still a further object of the invention to provide high density ohmic 
contacts for high density MOS devices. 
These and other objects are provided by a MOS device according to the 
present invention, which operates in the enhancement mode without 
requiring inversion, by setting the device's threshold voltage to twice 
the Fermi potential of the semiconductor material. As is well known to 
those having skill in the art, Fermi potential is defined as that 
potential for which a semiconductor material has a probability of one half 
of being occupied by an electron. Accordingly, the FET device according to 
the present invention may be referred to as a Fermi Threshold FET or 
Fermi-FET. 
It has been found, according to the invention, that when the threshold 
voltage is set to twice the Fermi potential, the dependance of the 
threshold voltage on oxide thickness, channel length, drain voltage and 
substrate doping is eliminated. It has also been found, according to the 
invention, that when the threshold voltage is set to twice the Fermi 
potential, the vertical electric field at the first surface of the 
semiconductor substrate in the channel is minimized, and is in fact 
substantially zero. Carrier mobility in the channel is thereby maximized, 
leading to a high speed MOS device with greatly reduced hot electron 
effects. 
Stated another way, according to the invention it has been found that 
dependance of threshold voltage on oxide thickness, channel length, drain 
voltage and doping level is a result of the voltage developed across the 
gate oxide layer which is necessary to establish inversion in conventional 
MOSFET's. According to the invention, by providing a threshold voltage 
equal to twice the Fermi potential, inversion is prevented, leading to a 
high speed device substantially independent of device dimensions. 
In a preferred embodiment of the invention it has been found that the above 
described Fermi-FET criteria may be met by forming a contra doped channel 
region having a carrier concentration or dopant density .alpha. times the 
dopant density of the substrate and having a channel depth Y.sub.o which 
is specified as: 
##EQU1## 
where e.sub.s is the dielectric constant of the semiconductor material 
(Farads/cm), q is the electric charge (1.6.times.10.sup.-19 C), and 
N.sub.s is the substrate doping density. 
According to another aspect of the invention it has been found that the 
contact potentials (referred to as a "flat-band voltages") generated by 
conventional FET substrate and gate contacts may adversely effect the 
threshold voltage of FET devices, in a manner not accounted for in 
previous FET designs. According to the invention, it has been found that 
the FET gate contact may be selected to be a semiconductor having a 
conductivity type and dopant density which generates a gate contact 
potential which is equal and opposite to that of the substrate contact 
potential, thereby neutralizing the effect of flat-band voltages. 
Dependence of threshold voltage on temperature is thereby eliminated. In 
order to neutralize the substrate flat-band voltage, the gate electrode is 
selected to be the same semiconductor as the substrate, having the same 
conductivity type and similar doping density as the substrate. In a 
preferred embodiment, when the substrate is monocrystalline silicon, the 
gate electrode is polysilicon. 
Flat-band voltage compensation may be employed to improve the performance 
of conventional FET's, in order to make P- and N-channel threshold 
voltages symmetric and less dependent upon temperature. Moreover, since 
the threshold voltage of the Fermi-FET is already independent of other 
device parameters, the use of flat-band voltage compensation further 
enhances the performance thereof. 
According to yet another aspect of the present invention a drain 
subdiffusion region may be provided in the semiconductor substrate 
adjacent the drain, to thereby minimize the effect of both punch-through 
and avalanche breakdown voltages on the device. In particular, the drain 
and has a dopant density which is a factor times the dopant density of the 
substrate. The factor may be selected to simultaneously maximize 
punch-through breakdown and avalanche breakdown voltages between the drain 
and substrate. A similar source subdiffusion may also be provided. 
Immunity to avalanche breakdown and punch-through are thereby both 
maximized, so that short channel FET devices may operate with full power 
supply voltage; i.e. a scaled down supply voltage is not needed. 
The subdiffusion regions of the present invention may be employed to 
improve the performance of conventional FET's, to make them less immune to 
avalanche and punch-through breakdown. Subdiffusion regions may also be 
employed to further enhance the performance of the Fermi-FET. 
The Fermi-FET of the present invention particularly lends itself to the use 
of multiple gate electrodes, for use in complementary MOS (CMOS) or other 
logic technologies which require connecting of transistors in series to 
achieve the desired logic function while maintaining essentially zero idle 
power. When multiple gate Fermi-FET devices are employed, it has been 
found that performance is improved when the gate immediately adjacent the 
drain is maintained at a full "on" value. This gate, referred to as an 
accelerator electrode, reduces the threshold voltage for the remaining 
gate or gates in the multi-gate Fermi-FET device.

DETAILED DESCRIPTION OF THE INVENTION 
The present invention now will be described more fully hereinafter with 
reference to the accompanying drawings, in which a preferred embodiment of 
the invention is shown. This invention may, however, be embodied in many 
different forms and should not be construed as limited to the embodiment 
set forth herein; rather, applicant provides this embodiment so that this 
disclosure will be thorough and complete, and will fully convey the scope 
of the invention to those skilled in the art. For ease of illustration the 
thickness of layers has been exaggerated. Like numbers refer to like 
elements throughout. It will be understood by those having skill in the 
art that the Fermi-FET of the present invention is applicable to both P 
and N channel devices and to silicon, germanium and other semiconductor 
materials. 
FET Design Analysis 
Before describing the Fermi-FET of the present invention, an analysis of 
FET design relationships will be developed. Throughout this specification, 
the terms MOS, FET, MOSFET and IGFET will be employed as synonyms to 
describe a field effect transistor structure having an insulated gate, 
wherein the insulation may be, but is not necessarily, an oxide, and 
wherein the gate may be, but is not necessarily, metal. 
An induced channel MOSFET requires a gate voltage to induce an inversion 
layer of minority carriers that act to conduct current between the source 
and drain. A gate threshold voltage condition is achieved when the surface 
potential .phi..sub.s of the semiconductor substrate, below the gate, is 
elevated sufficiently to bend the intrinsic energy band of the 
semiconductor material, down below the Fermi level. This rise in substrate 
surface potential is the result of increasing gate voltage V.sub.g to 
induce a depletion layer, with depth W.sub.do, in the substrate below the 
gate. 
Using Poisson's equation, the potential rise across the depletion layer is 
.phi..sub.s =(q/2e.sub.s)(N.sub.a W.sub.do.sup.2), where q is the electron 
charge in Coulombs, e.sub.s is the dielectric constant of the 
semiconductor material (Farads/cm), N.sub.a is the substrate acceptor 
concentration level, and W.sub.do is the depletion depth. Depletion depth 
W.sub.do is defined as W.sub.do =.sqroot.(2e.sub.s .phi..sub.s 
/(qN.sub.a)). The electric field at the substrate surface is E.sub.s 
=.gtoreq.(2.phi..sub.s qN.sub.a /e.sub.s). When the surface potential 
.phi..sub.s reaches twice the Fermi potential 2.phi..sub.f, the ionization 
concentration N.sub.p, within a p- substrate, becomes equal to the 
substrate acceptor concentration N.sub.a. Surface potential .phi..sub.s 
need only be increased slightly above threshold voltage 2.phi..sub.f in 
order to achieve inversion. 
Unfortunately, charge is accumulated on the gate as a result of creating 
the inversion layer. The density of this gate charge is qN.sub.a W.sub.do 
Coulombs per cm.sup.2. Gate threshold voltage V.sub.t is the sum of the 
voltage developed across the gate oxide layer and the rise in substrate 
potential 2.phi..sub.f. The gate oxide field is qN.sub.a W.sub.do 
/e.sub.1, and the voltage V.sub.ox is qN.sub.a W.sub.do /C.sub.i, where 
C.sub.i =e.sub.i /T.sub.ox and T.sub.ox is the oxide thickness. Therefore, 
##EQU2## 
Where; 
.phi..sub.s =2.phi..sub.f, 
L*=Effective channel length, as described in detail below, 
V.sub.cs =substrate contact potential, and 
V.sub.cg =gate contact potential. 
When voltage is applied to the drain and source regions, a potential V(X) 
is introduced at position X along the channel between the drain and 
source. This potential is described in detail below. The oxide threshold 
voltage term in Equation 1 increases with voltage V(X) in accordance with 
Equation 2: 
##EQU3## 
Thus, the threshold voltage contribution due to gate charge Equation 2 is 
complex and causes difficulties in both digital and analog circuit design 
and device fabrication. In particular, high speed short channel C-MOS 
logic design is severely compromised by this threshold voltage term. 
Threshold voltage sensitivity to substrate surface doping also hinders 
corrective measures needed to eliminate drain-source punch-through in 
conventional short channel MOSFET devices. 
The Fermi - FET Concept 
According to the present invention, Fermi-FET design is achieved by a 
grounded source FET device devoid of the complex threshold voltage term 
shown in Equation 1 above. The basic N-Channel Fermi-FET is illustrated by 
FIG. 1A. A P-channel Fermi-FET is fabricated the same way but with 
opposite conductivity materials. 
Referring noW to FIG. 1A, a Fermi-FET 10 according to the present invention 
is fabricated in a semiconductor substrate 11 having an acceptor 
concentration N.sub.a. It will be understood by those haVing skill in the 
art that semiconductor substrate 11 may be silicon (for example 
monocrystalline silicon having 100 orientation), gallium arsenide or other 
semiconductors, and may be an epitaxial or "tub" region formed in a 
semiconductor substrate. Source region 12 and drain region 13 are formed 
in the semiconductor substrate. Source and drain regions 12 and 13 are of 
opposite conductivity from substrate region 11 and have a higher donor 
concentration (i.e. they are doped N.sub.d.sup.+). Source electrode 19 and 
drain electrode 20 form external contacts for these regions. A thin gate 
oxide layer 14 is formed on the surface of substrate 11. A gate contact is 
formed on the gate oxide 14. In the embodiment illustrated the gate 
contact comprises a polysilicon gate contact 18 and a metal gate electrode 
23 for reasons described more fully below. A substrate contact region 21 
is formed within the semiconductor substrate 11. Contact 21 is typically 
of the same conductivity as substrate 11 but more highly doped (e.g. it is 
doped N.sub.a.sup.+). Finally, field oxide regions 17 isolate devices from 
one another. 
According to the present invention, a channel having the same conductivity 
type as the source and drain regions and opposite conductivity to the 
substrate is formed for example by implanting through thin gate oxide 
layer 14. The channel has a depth Y.sub.o and a donor doping level 
N.sub.d. The depth, doping and channel are critical for forming the 
Fermi-FET device of the present invention. In one embodiment, the 
substrate is a P-type substrate while source drain and channel regions are 
N-type. 
It will be shown according to the present invention that when channel 15 
has the proper doping level and depth, a depletion region 16 is formed in 
substrate 11 and the channel 15 is completely self-depleted, as shown in 
FIG. 1A. 
Still referring to FIG. 1A, the basic criteria for an N-channel Fermi-FET 
will now be described. The criteria for P-channel devices are the same 
except donor and acceptor ion types are interchanged. The nominal implant 
depth Y.sub.o of the channel is governed by Equation 3A and the effective 
donor concentration N.sub.d * is defined by Equation 3C. 
##EQU4## 
Given proper dose and depth, the implanted channel 15 is completely 
self-depleted as shown in FIG. 1A. Complete channel self-depletion is the 
result of electron and hole diffusion across the junction between the 
channel 15 and the substrate 11. This carrier diffusion process is 
required to establish a constant Fermi potential across that P-N junction 
region. There are critical conditions for the implant depth and dose. The 
entire implanted channel with depth Y.sub.o, (Equation 3A), must be 
depleted of mobile electrons when the electric field E.sub.o at the 
channel-substrate junction reaches the value needed to terminate carrier 
diffusion across that junction. The total voltage V.sub.o developed across 
the depleted substrate 16 and channel region 15 (Equation 3B) raises the 
substrate surface potential .phi..sub.s to twice the Fermi potential 
2.phi..sub.f, if and only if N.sub.p *=N.sub.a. In general, N.sub.s 
defines the substrate doping density and N.sub.c, the channel doping 
density. This threshold voltage condition 2.phi..sub.f is achieved without 
introducing charge on the gate. This condition is true since the normal 
component of electric field, due to depletion effects, is zero at the 
surface of the semiconductor below the gate. The total threshold voltage 
expression for the Fermi-FET is therefore; 
##EQU5## 
Where 
V.sub.s =Source voltage, 
##EQU6## 
.alpha.=N.sub.p */Na 
Given the special condition N.sub.p *=N.sub.a, i.e. .alpha.=1, the correct 
implant depth (Equation 3A) becomes 
##EQU7## 
e.sub.s =dielectric constant of silicon, 
N.sub.s =Acceptor concentration of substrate (N-channel), and 
N.sub.i =Intrinsic carrier concentration. 
Table 1 lists nominal values for implant depth Y.sub.o in silicon as a 
function of substrate doping for .alpha.=1. The correct implant depth is 
subject to the condition N.sub.d *=N.sub.as for an N-channel device or 
N.sub.a *=N.sub.ds for a P-channel device. Subscript s denotes the 
substrate. 
TABLE 1 
______________________________________ 
N.sub.as or N.sub.ds 
Critical Implant Depth, 
(cm.sup.-3) Y.sub.o (Angstroms) 
______________________________________ 
1 .times. 10.sup.17 
714 
5 .times. 10.sup.16 
988 
2 .times. 10.sup.16 
1523 
1 .times. 10.sup.16 
2087 
8 .times. 10.sup.15 
2314 
5 .times. 10.sup.15 
2875 
1 .times. 10.sup.15 
6008 
______________________________________ 
The Fermi-FET design of the present invention achieves the objective of 
eliminating the complex oxide threshold voltage first term (Equation 1) 
typical of conventional enhancement MOSFET's. It will be shown 
subsequently that fabrication of the Fermi-FET is relatively simple and is 
applicable to long, medium, and short P- and N-channel devices. The 
benefits of the Fermi-FET are: high manufacturing yield, high speed 
circuit capabilities (low giga-hertz range), control of punch-through and 
avalanche breakdown, minimization of hot electron effects, and greatly 
simplified user design groundrules for both analog and digital circuits. 
Fermi - FET Operation 
Referring again to FIGS. 1A through FIG. 1C, as gate voltage V.sub.g is 
increased above threshold voltage V.sub.t, electric field and potential 
increase at the substrate surface directly below the gate. This rise in 
surface electric field and potential occurs as mobile electrons fill the 
holes in the depleted implant channel region 15. The holes in the depleted 
channel 15 are uniformly filled as gate voltage is increased above 
threshold. The half full and full channel conditions are illustrated by 
FIGS. 1B and FIG. 1C respectively. For each hole filled in the depleted 
channel 15, a unit of positive charge (1.6.times.10.sup.-19 Coulombs) 
appears on the gate electrode in order to conserve charge. Filling the 
empty donor sites of the implanted channel with electrons allows 
conduction current to flow between the source and drain. The channel is 
totally charge neutral when all of the empty holes are filled with 
electrons. When charge neutrality occurs, the volume density of conduction 
carriers corresponds to the donor concentration N.sub.d. Increasing gate 
voltage to induce the full channel value, V.sub.g *, fills the entire 
depleted channel region with electrons. 
The full channel condition is illustrated by FIG. 1C. When "full" channel 
conditions are achieved, positive charge density on the gate electrode is 
uniform and has the value qN.sub.a Y.sub.o Coulombs/cm.sup.2 for 
.alpha.=1. The electric field developed across the oxide layer is E.sub.ox 
=(qN.sub.a Y.sub.o)/e.sub.i, and the electric field at the surface of the 
semiconductor and across the "full" implanted region is (qN.sub.a 
Y.sub.o)/e.sub.s since .DELTA..multidot.D=0 there and in the oxide layer. 
The oxide potential is V.sub.ox =(qN.sub.a Y.sub.o T.sub.ox)/e.sub.i. Gate 
voltage V.sub.g * at the "full" channel condition, is the sum of the oxide 
potential V.sub.ox and potential .phi..sub.s developed across the channel 
15 and the ionized region of the substrate below the channel. 
Referring now to FIG. 1D, when gate voltage V.sub.g exceeds the "full" 
channel value V.sub.g *, excess charge (mobile carriers) becomes available 
in the implanted channel region 15. These excess carriers account for the 
increase in channel current in proportion to gate over-drive voltage, 
V.sub.g &gt;V.sub.g *. A unit of positive charge also appears on the gate 
electrode for each excess electron created in the channel. 
FIGS. 2A-2D illustrate the charge distribution, electric field, and 
potential for the "empty", "half-full", "full", and "enhanced" channel 
conditions illustrated in FIGS. 1A-1D respectively, for the case N.sub.d 
*=N.sub.a. These conditions depend on gate voltage V.sub.g. 
Referring to the "full" channel condition (FIG. 2C), gate to substrate 
voltage V.sub.g * is given by: 
EQU V.sub.g *=V.sub.ox +V.sub.ch +V.sub.j (6) 
Where in general: 
##EQU8## 
For the special case, N.sub.d *=N.sub.a, the following relations apply: 
##EQU9## 
Substituting the appropriate Equation 8A-8H into Equation 6, the following 
relationship is obtained: 
##EQU10## 
Accordingly, for the depleted (empty) channel condition, (FIG. 2A), the 
potential rise .phi..sub.s at the first semiconductor surface, under the 
gate, is .phi..sub.s =2.phi..sub.f volts given N.sub.d *=N.sub.a and no 
source voltage. Therefore, the potential applied to the gate electrode 
must exceed the surface potential (.phi..sub.s =2.phi..sub.f) in order to 
start filling the depleted channel with conduction electrons. The gate 
threshold voltage is .phi..sub.s in general (Equation 7F), and 
2.phi..sub.f in particular when N.sub.d *=N.sub.a. This is a very simple 
criterion for threshold voltage when compared to the threshold criteria 
for a conventional MOSFET. The nominal grounded source Fermi-FET 
configuration completely eliminates the oxide voltage term (Equation 10) 
characteristic of conventional MOS device threshold voltage. (Note that 
the origin of L* will be described in detail below): 
##EQU11## 
The nominal Fermi-FET has a threshold voltage expression given by Equation 
4, which includes effects of source voltage V.sub.s. Elimination of the 
conventional MOSFET oxide threshold voltage component significantly 
enhances Fermi-FET performance. This is a result of eliminating threshold 
voltage dependance on channel length, oxide thickness, drain voltage, and 
the doping level of the semiconductor surface. 
One method of preventing punch-through in short channel devices is to 
simply increase substrate doping. Threshold voltage for the Fermi-FET does 
not include the complex term (Equation 10), and therefore low threshold 
voltage can be maintained virtually independent of substrate doping. 
Substrate doping affects threshold voltage in the Fermi-FET only slightly 
due to the logarithmic dependence of the Fermi potential term .phi..sub.f. 
A method for further enhancing the resistance to punch-through will be 
described below. 
Referring to Equation 9, the net gate voltage V.sub.g *-V.sub.t required to 
fill the I-channel with conduction electrons may be obtained. Since 
threshold voltage is 2.phi..sub.f, it follows that: 
##EQU12## 
When drain voltage V.sub.d is increased, (source at ground potential), a 
critical drain ("pinch-off") saturation condition is attained (described 
in detail below) for a given gate voltage V.sub.g. Carrier concentration 
within the conduction channel diminishes to a minimum value at the drain. 
When "pinch-off" is achieved, drain current saturates. The saturation 
condition is illustrated by FIG. 1D. 
The effects in the channel when gate voltage V.sub.g exceeds the "full" 
channel value V.sub.g * will now be described. This analysis assumes an 
N-channel Fermi-FET device with source and substrate voltage at ground 
potential. When gate voltage V.sub.g &gt;V.sub.g *, channel conduction 
capability is enhanced by increasing the volume density of conduction 
electrons N.sub.p * in the channel 15 above the donor value N.sub.d 
*&lt;N.sub.a. See FIG. 2D. Gate oxide potential V.sub.ox is proportional to 
the total channel charge qN.sub.p *Y.sub.o, where N.sub.p * is the total 
volume concentration of conduction carriers in the enhanced channel. Since 
the implanted channel is N-type, the Fermi level is already close to the 
conduction band. The conduction energy band need not be bent down very far 
to increase the number of conduction carriers in the implanted channel 
region. The increase in surface potential .phi..sub.s, needed to realize a 
carrier concentration N.sub.p * greater than N.sub.a, is .phi..sub.s =KT/q 
ln(N.sub.p */N.sub.a). An increase in surface potential of 18 mv is 
required for the case where N.sub.p *=2N.sub.a. 
In view of the Fermi-FET structure, it follows that most of the enhanced 
carrier concentration (N.sub.p *-N.sub.a) will be confined to a maximum 
depth prescribed by depth Y.sub.o of the implanted channel, because the 
ionized P-substrate region 16, located below the channel implant region 
15, has a maximum potential .phi..sub.f at the junction between the 
implanted channel and the substrate when N.sub.d *=N.sub.a. The remote 
location of the ionized substrate region from the surface and the junction 
potential .phi..sub.f results in a carrier concentration near the 
intrinsic value N.sub.i =1.5.times.10.sup.10 cm.sup.-3 for silicon. Thus a 
majority of the gate enhanced excess carrier concentration (N.sub.p 
*-N.sub.a) is located below the surface of the substrate and resides 
within the critical implant depth Y.sub.o. If gate voltage V.sub.g is less 
than V.sub.g *, the implanted channel is only partially filled, a factor 
F.ltoreq.1 applies. For enhanced channel conditions, F&gt;1. For the general 
condition 0&lt;F: 
##EQU13## 
where 
F=N.sub.p */N.sub.a, 
##EQU14## 
V.sub.ch =.phi..sub.f (1+F), and 
V.sub.j =.phi..sub.f. 
From Equation 12 it may be seen that V.sub.g =V.sub.t =2.phi..sub.f when 
the channel filling factor F=N.sub.p */N.sub.a =0. Evaluating Equation 12 
for the full channel condition (F=1) under the following conditions, 
Na=5.times.10.sup.16 cm.sup.-3 
.phi..sub.f =0.39 volts 
e.sub.s =1.times.10.sup.-12 Farads/cm 
q=1.6.times.10.sup.-19 Coulombs 
C.sub.i =1.5.times.10.sup.-7 Farads/cm.sup.2 
Y.sub.o =9.87.times.10.sup.-6 cm 
F=1.0 
the following results are obtained: 
V.sub.g *=1.69 Volts=4.34.phi..sub.f 
V.sub.g *-V.sub.t =0.916 Volts=2.43.phi..sub.f 
V.sub.t =2.phi..sub.f =0.78 Volts 
FIG. 3A is a plot of Equation 12 as a function 0.ltoreq.F.ltoreq.1 for 
different values for acceptor concentration N.sub.a. FIG. 3B is a plot of 
gate voltage V.sub.g as a function of F in the range 0.ltoreq.F.ltoreq.10 
and different substrate acceptor concentration N.sub.a. When F&gt;1, excess 
carriers exist in the implanted channel and account for increased channel 
current. The linear behavior of V.sub.s with F&gt;1 should be noted. This 
linear relationship is a distinct and useful advantage of the Fermi-FET. 
Equations 13A-13D present a comparison of threshold voltage for a 
conventional MOSFET with the ideal Fermi-FET and the deep and shallow 
versions resulting from errors introduced during channel implant. 
##EQU15## 
Method of Fabricating the Fermi-FET 
Referring now to FIG. 4, a method of fabricating a Fermi-FET according to 
the present invention will now be described. In the method illustrated 
herein, a P-type polysilicon gate is provided for an N-channel Fermi-FET. 
Conversely, an N-type polysilicon gate is provided for a P-channel 
Fermi-FET. As described in detail below, metal-semiconductor contact 
potentials may significantly influence threshold voltage of any FET 
including the Fermi-FET. To avoid this extraneous variation in threshold 
voltage, a polysilicon gate is provided. 
Referring now to FIG. 4A, a portion of p-substrate region 11 having 
acceptor concentration N.sub.a is illustrated. This substrate region may 
be formed by implanting and driving a dopant in an unmasked area of an 
intrinsic 4.mu. silicon epitaxial layer grown on a silicon, sapphire or 
other substrate. Thick and thin oxide layers, 17 and 14 respectively, are 
also shown. All P-channel devices are covered with photo-resist material 
(not shown) while low energy N-type ions (phosphorous or arsenic for 
example) are implanted in the direction shown by arrows 26 through the 
thin oxide layer 14, into the surface of the P-doped substrate. This 
implant provides an N-type channel region 15 with proper depth Y.sub.o. 
The implant dose must also be controlled such that the average doping 
value achieves the condition N.sub.d *=.alpha.N.sub.a, where N.sub.d * is 
defined by Equation 3C. P-channel implant follows similar procedures 
except opposite ions are implanted. This implant step is critical for both 
the P- and N-channel devices. Care must be exercised to achieve the proper 
implant energy and dose. 
Referring to FIG. 4B, after appropriate masking and implanting both P- and 
N-channels 15 through the thin oxide region 14, all photoresist material 
is removed and intrinsic polysilicon 18 is deposited over the entire 
surface of the wafer. 
It will be understood that the wafer may contain both P- and N-channel 
areas. While these figures show only N-channel areas, the P-channel areas 
may be formed as follows: Regions of the wafer containing intended 
P-channel devices, for example, may be masked with photoresist material 
leaving exposed polysilicon that overlays the N-channel devices. P-type 
ions (e.g. Boron) may then be implanted into the exposed polysilicon 
layer, thereby converting the intrinsic polysilicon to P.sup.++ type. 
Then, the photoresist masking material, covering the P-channel devices, 
may be removed and a new masking layer of photoresist material may be 
deposited over all N-channel devices. N-type ions are then implanted into 
the exposed polysilicon overlaying the P-channel devices, thereby 
converting those polysilicon regions to N.sup.++ type. The energy of both 
doping implants must be low enough, for the given thickness of the 
polysilicon layer, not to penetrate the full depth of that layer. The next 
step in the process is to remove the photoresist material. This step is 
then followed by covering the entire exposed polysilicon surface with 
photoresist material. The depth must be thick enough to block subsequent 
implantation from penetrating non-etched regions of this barrier layer. 
Referring now to FIG. 4C, a self-aligned poly gate mask 27 is applied next. 
This gate mask is aligned to the center region of the implanted P- and 
N-channel devices, and provides the definition for the polysilicon gate. 
Next, all of the exposed barrier and polysilicon layers are etched away 
leaving the appropriately doped polysilicon gate region with an overlaying 
photoresist layer as shown in FIG. 4C. 
Referring now to FIG. 4D, photoresist material is then applied to mask the 
P-channel devices, while drain and sOurce contact regions 12 and 13 
respectively, and optional field reducing regions 28 and 29, are implanted 
in the N-channel devices. The functions of field reducing regions 28 and 
29 will be described below. Then, this photoresist material is removed 
from the P-channel devices and new material is applied over the N-channel 
devices. The P-type source and drain regions of the P-channel devices are 
then implanted. The photoresist used to mask the N-channel devices is then 
removed, and the source and drain regions of the P-channel devices are 
formed. An oxidation step may then form oxide on the side-walls of the 
polysilicon gates previously defined, and may also anneal the implants. 
This oxidation also thickens the oxide layer over the source and drain 
regions. The remaining steps in the process need not be described here 
since they comprise well known and conventional steps for fabricating FET 
devices. These process steps include removal of oxide over the source, 
drain, gate, and substrate contact regions, and the application of surface 
passivation and contact metal to these exposed regions. 
An alternative method of fabricating Fermi-FETs according to the invention, 
using in-situ poly-gate doping will now be described. According to this 
method, after appropriate masking and implanting both P- and N-channels 
through the thin oxide region, all photoresist material is removed, and an 
in-situ P.sup.+ doped polysilicon layer is deposited over the entire 
surface of the wafer as shown in FIG. 4B. The dopant density of the 
P.sup.+ polysilicon should be high enough to permit Ohmic-metal contact to 
its surface. P-channel areas may also be simultaneously formed during this 
process as follows: Regions of the wafer containing intended N-channel 
devices are masked with photo-resist material, leaving exposed polysilicon 
that overlays the P-channel devices. N-type ions such as phosphorous or 
arsenic are then implanted into the exposed polysilicon layer, thereby 
converting the in-situ doped P.sup.+ poly-silicon to N.sup.+ type. The 
dopant density of the N-polysilicon should be high enough to permit 
Ohmic-metal contact to its surface. 
Then, the photo-resist masking material, covering the N-channel devices, is 
removed. The energy of the doping implant must be low enough for the given 
thickness of the polysilicon layer, so that it does not penetrate the full 
depth of that layer. A subsequent anneal activates and homogenizes this 
implant concentration. The next step in the process is to remove the 
photo-resist material. This step is followed by covering the entire 
exposed polysilicon surface with photoresist material. The depth of this 
photoresist barrier must be thick enough to block subsequent implantation 
from penetrating non-etched regions. The self-aligning poly gate mask is 
applied next. The remaining steps are the same as previously described. 
Fermi-FET Channel Doping Considerations 
The effects of channel implant concentration N.sub.c =.alpha.N.sub.s, has a 
significant effect on drain current properties of the Fermi-FET device. 
Pinch-off voltage has already been described for the special case where 
.alpha.=1. This restricted the implant concentration (Equation 3C) to 
equal the substrate concentration with a critical depth characteristic of 
that condition. Below, the general expression for pinch-off Voltage 
V.sub.p for .alpha. in the range 1&gt;.alpha.&gt;4 is provided (FIG. 6). 
Computer plots of n-channel devices are also presented for N.sub.a 
=1e.sup.17 and .alpha.=0.2, 1.0, and 5.0 (FIG. 5). Referring to these 
figures, it will be seen that Fermi-FET devices with low pinch-off voltage 
are attained when .alpha.&gt;1. A preferred value is .alpha.=2. This value 
for .alpha. leads to high transconductance and low saturation drain 
conductance for sub-micron channel length devices. 
The general expression for pinch-off voltage is as follows: 
##EQU16## 
where 
##EQU17## 
Referring now to FIG. 5A, a plot of gate voltage as a function of drain 
current and drain voltage for channel length of 1 .mu.m, .mu..sub.o =750, 
N.sub.a =1.times.10.sup.17, T.sub.ox =200.ANG., and .alpha.=0.2 is 
provided. Gate voltage is shown in steps of 0.5 V, starting at 0 V. FIG. 
5B presents the same series of plots under the same conditions except that 
.alpha.=1.0. FIG. 5C presents the same series of plots for o=5.0. 
The computer generated plots of FIG. 6 illustrate the influence of channel 
implant factor .alpha. on the rising current (low drain voltage) property 
of the Fermi-FET device. FIG. 6A illustrates drain current as a function 
of channel implant factor .alpha. with V.sub.d =1 V, L=0.5.mu., Z=3 .mu.m 
and 1 Volt per step for gate voltage, N.sub.a =5.times.10.sup.16, 
.mu..sub.oo =1200, E.sub.i =2.5.times.10.sup.5 V/cm. FIG. 6B shows drain 
current as a function of channel implant factor .alpha. with V.sub.d =0.5 
V, L=0.5.mu., Z=3 .mu.m, 1 Volt per step for gate voltage, N.sub.a 
=5.times.10.sup.16, .mu..sub.oo =1200, E.sub.i =2.5.times.10.sup.5 V/cm. 
It is apparent that most of the change occurs when .alpha.=N.sub.c 
/N.sub.s &lt;2. i.e., drain resistance decreases with increasing .alpha.. 
N.sub.c is the implanted channel impurity concentration and N.sub.s 
represents the substrate impurity concentration, in Ions/cm.sup.3. 
Accordingly, in designing Fermi-FET devices, one should strive to use a 
channel implant factor .alpha. of about 2.0. 
FIG. 7 illustrates the junction between the implanted channel 15 and the 
substrate 11 of FIG. 1A. The peak electric field E.sub.o and the potential 
.phi..sub.o are shown at the stochastic junction between the implant and 
the substrate. The depletion depth developed in the substrate is Y.sub.p 
and the depleted implant depth is defined as Y.sub.n. Since 
##EQU18## 
.phi..sub.o may be expressed in terms of surface potential .phi..sub.s. 
From FIG. 7, the following is obtained; 
##EQU19## 
Based on the definition of .phi..sub.o, the following is obtained: 
##EQU20## 
Now, if the implant concentration varies in depth then: 
##EQU21## 
Multiplying Equation 24 top and bottom by Y.sub.n 
##EQU22## 
The last integral in Equation 25 represents an average value. Thus, 
##EQU23## 
Accordingly, the necessary conditions for the channel implant at depth 
Y.sub.n are: 
##EQU24## 
After an anneal process depth spreading may be expected, so that: 
##EQU25## 
The integrals of Equations 28 and 29 must be the same since charge is 
conserved. Therefore, 
##EQU26## 
The depth of the depletion region in the substrate, Y.sub.p remains the 
same, before and after the anneal, since the total implant charge is 
unaltered. 
##EQU27## 
Tables 2 and 3 illustrates values of implant channel depth Y.sub.o in cm 
for various values of .alpha. and N.sub.a. 
TABLE 2 
______________________________________ 
.alpha. = N.sub.c /N.sub.s 
Y.sub.o @N.sub.a =1.times.10.sup.16 
Y.sub.o @N.sub.a =1.times.10.sup.17 
______________________________________ 
1.0000000 2.0876457e-05 7.1460513e-06 
1.2500000 1.7677658e-05 6.0474366e-06 
1.5000000 1.5360821e-05 5.2522975e-06 
1.7500000 1.3597864e-05 4.6475990e-06 
2.0000000 1.2207786e-05 4.1710276e-06 
2.2500000 1.1081721e-05 3.7851283e-06 
2.5000000 1.0149919e-05 3.4659164e-06 
2.7500000 9.3654684e-06 3.1972686e-06 
3.0000000 8.6955825e-06 2.9679200e-06 
3.2500000 8.1166127e-06 2.7697490e-06 
3.5000000 7.6110519e-06 2.5967449e-06 
3.7500000 7.1656491e-06 2.4443597e-06 
4.0000000 6.7701829e-06 2.3090859e-06 
4.2500000 6.4166374e-06 2.1881738e-06 
4.5000000 6.0986353e-06 2.0794361e-06 
4.7500000 5.8110371e-06 1.9811105e-06 
5.0000000 5.5496537e-06 1.8917608e-06 
5.2500000 5.3110354e-06 1.8102046e-06 
5.5000000 5.0923150e-06 1.7354593e-06 
5.7500000 4.8910894e-06 1.6667014e-06 
______________________________________ 
TABLE 3 
______________________________________ 
.alpha.=N.sub.c /N.sub.s 
Y.sub.o @N.sub.a =3.times.10.sup.16 
Y.sub.o @N.sub.a =6.times.10.sup.16 
______________________________________ 
0.50000000 2.0226885e-05 1.4648398e-05 
0.75000000 1.5399139e-05 1.1148451e-05 
1.0000000 1.2537030e-05 9.0743104e-06 
1.2500000 1.0612724e-05 7.6801600e-06 
1.5000000 9.2194980e-06 6.6709817e-06 
1.7500000 8.1596633e-06 5.9034214e 06 
2.0000000 7.3241990e-06 5.2984395e 06 
2.2500000 6.6475555e-06 4.8085218e-06 
2.5000000 6.0877463e-06 4.4032386e-06 
2.7500000 5.6165406e-06 4.0621323e-06 
3.0000000 5.2142104e-06 3.7709088e-06 
3.2500000 4.8665300e-06 3.5192616e-06 
3.5000000 4.5629693e-06 3.2995624e-06 
3.7500000 4.2955597e-06 3.1060392e-06 
4.0000000 4.0581550e-06 2.9342402e-06 
4.2500000 3.8459362e-06 2.7806752e-06 
4.5000000 3.6550694e-06 2.6425677e-06 
4.7500000 3.4824655e-06 2.5176806e-06 
5.0000000 3.3256069e-06 2.4041908e-06 
5.2500000 3.1824202e-06 2.3005973e-06 
______________________________________ 
Controlling Punch-through and Avalanche Breakdown Voltage 
There are two voltage breakdown phenomena that limit the success of short 
channel FET technology. Punch-through occurs when the depletion boundary 
surrounding the drain touches the depletion boundary surrounding a 
grounded source. This condition causes injection to occur at the 
source-substrate junction. Impact ionization occurs when drain voltage 
reaches a value that stimulates the generation of electron-hole pairs at 
the junction between the drain diffusion and substrate. Electron-hole pair 
generation gives rise to an avalanche break-down mechanism that produces a 
rapid increase in drain current. Substrate current flows when avalanche 
breakdown occurs in support of the increase in drain current. 
According to the invention, substrate dopant level and the 
subdiffusion--drain implant doping factor K.sub.d, may be used to 
simultaneously control both voltage breakdown mechanisms. 
Referring now to FIG. 8, an FET structure having subdiffusion regions to 
minimize punch-through and avalanche breakdown is shown. P-doped substrate 
11 has an acceptor concentration N.sub.a. Source and drain regions 12 and 
13 respectively are heavily doped N-type regions. N-doped channel 15 has 
doping concentration N.sub.d. ln a preferred embodiment channel 15 meets 
the requirements of a Fermi-FET Equation 3A, although a conventional FET 
may also be employed. Associated with source 12 and drain 13 are source 
and drain subdiffusion regions 28 and 29, respectively, having donor 
doping concentrations N.sub.d =K.sub.d N.sub.a. It will be understood by 
those having skill in the art that punch-through and avalanche breakdown 
are more likely to occur at the drain rather than the source, so that a 
drain subdiffusion 29 alone may be employed. 
The value of the subdiffusion implant doping factor K.sub.d will now be 
described. Increasing punch-through break-down requires increasing 
substrate doping N.sub.a. On the other hand, breakdown voltage due to 
impact ionization is inversely dependant on substrate doping. The solution 
to this dilemma is to control the dopant concentration K.sub.d of the 
subdiffusion region, FIG. 8, in the vicinity of the substrate such that 
the peak field crossing the substrate to subdiffusion junction is 
minimized for a given drain voltage. The ionization field of approximately 
3.times.10.sup.5 Volts per cm is eventually reached for some drain 
voltage. The object is to operate Fermi-FET devices below this field value 
with as high a drain voltage as possible. Equation 33 below describes 
avalanche break-down as a function of the ionizing field E.sub.i, 
substrate doping N.sub.a, and diffusion dopant factor K.sub.d : 
##EQU28## 
Equation (34) describes breakdown voltage V.sub.p due to the punch-through 
mechanism. The dependance of these breakdown mechanisms on substrate 
doping has opposite effects. One voltage increases while the other 
decreases. Maximum substrate doping occurs when Equations 34 and 35 are 
equal, for a given subdiffusion concentration factor K.sub.d. The drain 
sub-diffusion concentration factor K.sub.d, for dopant concentration below 
the depth of the implanted channel region of the Fermi-FET, has a 
pronounced effect on drain breakdown voltage. This effect is illustrated 
in FIG. 9A. Break-down is illustrated for several values for the 
concentration factor K.sub.d. The nominal value E.sub.i for silicon is 
2.5.times.10 V/cm at room temperature for the computed range of substrate 
doping N.sub.a. Channel length L was 0.5.mu.. The minimum value for the 
subdiffusion implant depth W.sub.no, (FIG. 8), was computed assuming 
complete depletion at a drain voltages V.sub.d =10 V and 6 V and is 
defined in FIG. 9D and 9E respectively as a function of N.sub.a and 
K.sub.d. 
Referring to FIG. 9A, both punch-through (rising curve) and avalanche 
breakdown voltage (falling curve) are shown as a function of K.sub.d and 
N.sub.a. Their intersection specifies the maximum substrate doping level 
N.sub.a that simultaneously maximizes both breakdown voltages. Factor 
K.sub.d is shown in the range 0.2&lt;K.sub.d &lt;1. Higher breakdown voltage 
occurs when K.sub.d =0.2. The channel is 0.5.mu. long. Ionization field 
E.sub.i =2.5.times.10.sup.5 V/cm. It is apparent that a breakdown of 20 
Volts is quite possible for this channel length. 
Referring to FIG. 9B, both punch-through (rising curve) and avalanche 
breakdown voltage (falling curve is shown. Their intersection specifies 
the maximum substrate doping level N.sub.a that maximizes both breakdown 
voltages. K.sub.d is shown in the range 0.2&lt;K.sub.d &lt;1. The highest 
breakdown voltage occurs when K.sub.d =0.2. The channel is 0.3.mu. long. 
It is apparent that a breakdown of 20 Volts is quite possible for this 
channel length. 
Referring now to FIG. 9C, both punch-through (rising curve) and avalanche 
breakdown voltage (falling curve) are shown for a channel L=1 .mu.m. FIGS. 
9D and 9E illustrate the minimum depth W.sub.no of the sub-diffusion 
region given 10 and 6 Volts on the drain for full depletion, respectively. 
The highest running parameter is K.sub.d =0.2. The lowest is K.sub.d =1.0 
Subdiffusion concentration factor K.sub.d should correspond approximately 
to twice the channel length L in number value. For example, if L=0.5 .mu.m 
then K.sub.d =1. Under these circumstances, break-down voltage is about 10 
V for E.sub.i =2.5.times.10.sup.5 V/cm. The nominal substrate dopant 
concentration N.sub.a is about 4.6.times.10.sup.16 cm.sup.-3 for a channel 
length, L=0.5 .mu.m, N.sub.a =8.times.10.sup.16 for L=0.3 .mu.m, and 
N.sub.a =2.times.10.sup.16 for a channel length of 1 .mu.m. 
The channel implant factor .alpha. for the Fermi-FET is based on substrate 
concentration N.sub.s and the desired channel depth Y.sub.o. The nominal 
value for .alpha. is about 2.0. The heavily doped drain and source contact 
diffusions, FIG. 8, should have the same depth as the channel, and have 
resistance less than 200.OMEGA. per square. Some latitude in this depth is 
provided by the choice of the channel implant factor .alpha.. For example, 
the source and drain contact diffusions may be up to twice as deep as the 
channel depth Y.sub.o. 
The Fermi-FET body effect, i.e. threshold voltage variation with substrate 
voltage, is dramatically influenced by the channel implant factor .alpha.. 
This influence by factor .alpha. is unique to the Fermi-FET and is 
illustrated in FIG. 9F for N.sub.s =N.sub.a =5.times.10.sup.16 /cm.sup.3. 
FIG. 9F illustrates threshold voltage as a function of substrate voltage 
given N.sub.a =5.times.10.sup.16 and channel factor .alpha. as the running 
parameter; .alpha.=a*n, a=0.5. Note that threshold is fairly flat if 
.alpha.=0.7, T.sub.ox =120A. 
Ohmic Contact Junction Potential Compensation 
The effect of junction potentials of ohmic metal semiconductor contacts on 
threshold voltage and FET design will now be described. FIGS. 10A-10D 
illustrate various contact potentials that occur at the substrate-metal, 
diffusion-metal, and polysilicon gate-metal junctions. FIGS. 10A-10B 
illustrate N-channel devices and FIGS. 10C-10D illustrate P-channel 
devices. 
The analysis heretofore presented assumes that drain, source, and gate 
voltages are referenced to the substrate potential. No provisions were 
made to include effects of metal contact potentials. It will become 
apparent from the following analysis that metal-poly gate contact 
potential may be employed to compensate for metal-substrate flat-band 
voltage for both conventional and Fermi-FET devices. It will be shown that 
the doping polarity and concentration of the polysilicon gates, for both 
P- and N-channel devices, may be chosen to compensate for substrate 
contact potential, thus eliminating this undesired source of threshold 
voltage. 
Referring to the N-channel technology, FIGS. 10A and 10B, contact to the 
substrate 11 is made by depositing metal 22 on a heavily doped P.sup.++ 
region 21 provided at the surface of the substrate 11. A potential is 
developed across this P.sup.++ metal junction. The potential V.sub.jx is 
given below for metal to P- and N-type diffusions: 
##EQU29## 
N.sub.a is the acceptor concentration of the P.sup.++ pocket, N.sub.d is 
the donor concentration and N.sub.d " is the effective density of 
conduction electrons in the contacting metal. The depletion depth within 
the P.sup.++ pocket region, resulting from metal contact, must be shallow 
by design to allow electron tunneling to occur in order to achieve 
Ohmic-contact properties of the metal-semiconductor junction. Depletion 
depth within the P.sup.++ pocket region is approximated by: 
##EQU30## 
This depletion depth needs to be less than about 1.5.times.10.sup.-6 cm in 
order to support the tunneling mechanism. Assuming N.sub.d "=10.sup.21 
cm.sup.-3 and N.sub.a =10.sup.19 cm.sup.-3, then V.sub.jx =1.17 Volts, 
X.sub.d =1.17.times.10.sup.-6 cm, and the electric field at the junction 
is qN.sub.a X.sub.d /e.sub.s =1.87.times.10.sup.6 V/cm. A significant 
result is realized when the aluminum--substrate contact is grounded. This 
ground connection places the substrate potential below true ground 
potential. i.e. -V.sub.js. 
Accordingly, to assess true MOSFET threshold voltage, of the quiescent 
substrate to gate voltage must be considered. Referring to FIG. 10A, the 
N-polysilicon gate-metal contact potential, KT/q ln(N"/N.sub.d), is 
negligible, (for example 150 mv), and assumed to be small compared to 
V.sub.js. Therefore, grounding the gate yields a net positive 
gate-to-substrate voltage V.sub.js =1.02 Volts. Therefore, the total 
MOSFET threshold voltage is reduced by the difference in contact 
potential, V.sub.js -V.sub.jg. Given a grounded source N-channel Fermi-FET 
provided with a N-poly gate, threshold voltage V.sub.t would be V.sub.t 
=2.phi..sub.f -V.sub.js and quite likely, threshold voltage will have a 
net negative value. 
Referring now to FIG. 10B, it is shown that the poly-gate 18 is doped 
P.sup.++. If the doping density of the polysilicon gate body region is 
identical to the substrate doping, and aluminum is used in both cases for 
contacts 22 and 23, the polysilicon-aluminum contact potential will match 
the metal-substrate junction voltage V.sub.jx. For this case, when the 
gate electrode 23 is grounded, the net contact induced threshold potential 
is V.sub.jg -V.sub.js =0. Thus, no extraneous threshold potential exists 
due to contacts, for any N-channel MOSFET configured with a P-polysilicon 
gate. The grounded source Fermi-FET device will simply have a threshold 
voltage V.sub.t =2.phi..sub.f. Thus, an N-channel Fermi-FET structure 
needs a P-polysilicon gate to eliminate contact potentials from affecting 
threshold voltage. 
The unconnected source and drain diffusion potential V.sub.j of the 
N-channel device is V.sub.j =V.sub.o -V.sub.js where V.sub.o is the source 
or drain diffusion-substrate junction potential. The potential contour 
integral through the substrate, from contact 19 to contact 22, is zero if 
the same metal is used for both contacts. Grounding the 
diffusion--aluminum contact and substrate contact slightly reverse biases 
the diffusion--substrate junction. 
Referring now to FIGS. 10C and 10D, a P-channel device is illustrated. 
Substrate contact is made by depositing aluminum 22 on an N.sup.++ pocket 
21 implanted at the surface of an N-type substrate 11. The junction 
potential V.sub.j of this Ohmic contact is given by Equation 38B, since 
both materials are majority N-type. Therefore, grounding the aluminum 
contact 22, places the substrate surface under the gate, slightly below 
ground potential. 
Referring to FIG. 10C, an aluminum contact 23 is made to a P-polysilicon 
gate. A junction potential V.sub.jg is developed across this contact that 
is similar in value to V.sub.js developed at the P-substrate-aluminum 
contact (FIG. 10B). Therefore, grounding the P-channel gate places the 
gate potential, -V.sub.jg, below the surface potential of the substrate, 
thereby lowering the threshold voltage of the P-channel device by this 
junction potential. This offset in threshold voltage is eliminated by the 
structure shown in FIG. 10D. In that structure, an N-poly gate is used 
with a P-channel device. Any junction potential V.sub.jp developed across 
the aluminum--N-polysilicon junction can be made to be identical to the 
aluminum--substrate junction potential V.sub.js. Grounding the aluminum 
contact on the N-poly gate eliminates gate-to-substrate potential, and 
therefore no extraneous threshold voltage term exists due to metal 
contacts. 
In conclusion, a significant contact potential exists between aluminum and 
P.sup.++ semiconductor material. In order to avoid introducing this 
contact potential as part of the threshold voltage, the following FET 
conditions must be met: N-channel FET's require a P-polysilicon gate, 
while P-channel FET's require an N-polysilicon gate. 
The above described matching of implant doping eliminates extraneous 
threshold voltage as well as thermally introduced variations. It will be 
understood by those having skill in the art that the prior art has ignored 
or not totally understood the full implications of metal--semiconductor 
contact potentials (flat-band voltage). 
Threshold Voltage Sources - Summary 
Equations (40) and (46) reveal all important sources of threshold voltage 
for N- and P-channel FET devices. 
##EQU31## 
For the conventional ground source enhancement FET, there are four separate 
threshold voltage terms. From left to right they are; surface potential 
.phi..sub.s, oxide potential V.sub.ox, flat-band voltage at the 
substrate-metal Ohmic contact V.sub.cs, and flat-band voltage at the 
polysilicon gate Ohmic contact V.sub.cg. Comparing Equation 40 with 
Equation 46, for N- and P-channel devices, it is evident that the polarity 
of both flat-band voltage terms is unaltered. Their magnitudes, however, 
are different. 
Fermi-FET device design according to the present invention completely 
eliminates oxide potential V.sub.ox, the second term in Equations 40 and 
46. However, if the channel of the Fermi-FET is implanted with a dose 
greater than the nominal value, a fraction of the oxide potential term 
reappears but with a polarity opposite that indicated in Equation 40 and 
46, as will be described below in connection with modifying Fermi-FET 
threshold voltage. 
By examining Equations 40 and 46, it may be seen that threshold voltage for 
the Fermi-FET reduces to surface potential .phi..sub.s if both substrate 
and poly-gate flat-band voltages cancel one another. Equations 43 through 
45 give expressions for poly-gate flat-band voltage V.sub.cg for N-channel 
devices, given a metal gate, and N.sup.+ or P.sup.+ polysilicon gates. 
Equations 48 through 51 give the appropriate expressions for P-channel 
devices. The net flat-band voltage, V.sub.fb =V.sub.cs -V.sub.cg, 
approaches zero if the N-channel device is provided with a P-poly gate and 
the P- channel device is provided with an N-poly gate. Note that the 
dopant concentration at the surface of the poly gates must be high enough 
to achieve ohmic-metal contacts. The intrinsic carrier concentration 
N.sub.i * of polysilicon is greater than that in crystalline silicon by 
about an order of magnitude. It is estimated that the intrinsic carrier 
concentration N.sub.i * in polysilicon is about 1.8.times.10.sup.11 
cm.sup.-3 at 300 degrees Kelvin. This value should be used when 
calculating flat-band voltage at metal--poly gate junctions. 
Finally, it will be understood from the above analysis that conventional N- 
and P-channel FET devices should avoid use of metal gates. Instead they 
should be provided with contra-doped poly gates in order to achieve 
symmetric fabrication and equal threshold voltage. However, only the 
Fermi-FET device design eliminates oxide voltage from the threshold 
expression thereby attaining all of the performance advantages previously 
described. 
The above analysis may be applied to specific examples as follows: 
Case 1 
Metal gate P- and N-channel MOS devices. 
Threshold voltage for metal gate N- and P-channel devices becomes 
##EQU32## 
Flat-band voltage at the N-channel--substrate contact V.sub.cs is 
approximately 1.0 Volt, and depends on substrate acceptor concentration 
N.sub.a. For the P-channel device, V.sub.cs is about 0.2 V depending on 
donor concentration N.sub.d, assuming that surface potential .phi..sub.s 
=2.phi..sub.f and therefore is about 0.7 V. For the N-channel device, 
threshold voltage becomes; 
##EQU33## 
Threshold voltage for the P-channel device becomes; 
##EQU34## 
The oxide potential term is all that remains to control threshold voltage. 
For the N-channel case, oxide potential needs to be about 1.0 V at 
inversion. Two options are available to attain this voltage; i.e. use 
thick oxide, and/or implant additional acceptor ions at the channel 
surface. This solution for the N-channel threshold voltage yields a device 
very sensitive to short channel and hot electron effects. The P-channel 
device has a different problem. Threshold voltage is too high even if 
oxide potential is zero. The only practical solution for a conventional 
P-channel device is to use an N-poly-gate to eliminate flat-band voltage 
effects. The result is; 
##EQU35## 
Case 2 
N-poly gates used for both P- and N-channel devices. 
As in Case 1, the net flat-band voltage is zero for the p-channel device. 
Its threshold voltage expression reduces to the following: 
##EQU36## 
To reduce the contribution of the oxide potential term, the surface of the 
substrate, in the channel region, can be compensated with donor ions. 
The N-channel device has a different problem. The net flat-band voltage 
(-V.sub.cs +V.sub.cg) is about 0.8 volts. Threshold voltage becomes: 
##EQU37## 
The oxide potential term can be adjusted as in Case 1 by increasing the 
donor concentration N.sub.a in the channel region. As in Case 1, this is a 
poor solution since the device is still sensitive to short channel and hot 
electron effects because of the large oxide potential term. 
Case 3 
N-channel device with P-poly gate and P-channel device with N-poly gate. 
These combinations eliminate flat-band voltage and lead to balanced 
threshold voltages for the P- and N-channel devices. 
##EQU38## 
Increasing substrate doping N.sub.a for the N-channel device and N.sub.d 
for the P-channel device, is one method to control punch-through voltage 
for short channel devices. Unfortunately when used for conventional FET 
devices, this technique increases oxide potential, thus requiring channel 
surface compensation to be used to minimize the effect. 
Case 4 
Fermi-FET with contra doped polysilicon gates. 
The threshold voltage for the N- and P-channel devices are: 
V.sub.tn =+.phi..sub.s =2.sub.f 
V.sub.tp =-.phi..sub.s =-2.phi..sub.f 
This simplicity comes about since oxide potential is zero by design and all 
flat-band voltages are cancelled. Under these ideal circumstances, both P- 
and N-channel Fermi-FET's can be optimized for punch-through and avalanche 
breakdown and maximized for transconductance without affecting threshold 
voltage. Of great importance is the insensitivity to short channel effects 
including hot electron trapping. Finally, Fermi-FET devices fabricated 
with channel length's as short as 0.3 .mu.m should not require scaling 
down the standard power supply voltage of 5 volts. 
Modifying Fermi-FET Threshold Voltage 
For some circuit designs, it is desirable to fabricate depletion mode 
Fermi-FET devices. A depletion mode device is fabricated like an 
enhancement Fermi-FET device except the channel implant dose is increased 
by factor G while maintaining the same implant energy needed to achieve 
the critical implant depth prescribed by Equation 3A. By using Poisson's 
Equation to calculate surface potential at X=0 when excess dose factor 
G.sub.i is present, and given the nominal implant depth Y.sub.o, the 
threshold voltage V.sub.td for a depletion mode or low threshold device 
may be defined in terms of the excess implant factor G.sub.i as follows: 
##EQU39## 
Equation 52 is plotted in FIG. 11A as a function of G.sub.i for different 
values of channel implant factor .alpha. with a silicon substrate doped 
with 5e.sup.16 acceptor ions per cm.sup.3 and having an oxide thickness of 
120.ANG.. All threshold voltage values that are negative, correspond to an 
equivalent imaginary gate voltage responsible for conduction of the 
undepleted portion of the implant channel. For N-channel devices, a 
negative voltage is required to shut-off the channel. For example, given a 
substrate impurity concentration of 5e.sup.16 cm.sup.-3 and G.sub.i =4, 
and .alpha.=2, the channel conducts as though it was an enhancement device 
supplied with an effective gate voltage 1.3 volts above threshold. A gate 
voltage of -1.3 Volts is required to terminate N-channel conduction. 
Accordingly, FIG. 11A defines the additional implant dose factor G.sub.i 
required to modify a Fermi-FET device to have depletion mode properties or 
to lower its positive threshold voltage below the Fermi value .phi..sub.s. 
Referring to FIGS. 11B and 11C, it is shown that a positive threshold 
voltage may be achieved, for an N-channel Fermi-FET device, that is below 
the Fermi value .phi..sub.s. This is accomplished by using an excess 
implant dose factor G.sub.i, restricted to a value less than about 2.0. 
FIG. 11B uses the same parameters as FIG. 11A, except the V.sub.t and 
G.sub.i scales are changed. FIG. 11C uses the same parameters as FIGS. 11A 
and 11B, except that N.sub.a 32 2e.sup.16. The same excess dose procedure 
may be employed to lower threshold voltage of P-channel Fermi-FET devices. 
Opposite voltage polarities apply for P-channel devices. 
Effective Channel Length in FETs 
Previous analysis employed an effective channel length L*. The origin of 
this term will now be described in connection with the formation of a 
channel by application of gate voltage V.sub.g, when the depletion regions 
already surround the drain and source diffusions. 
Referring now to FIG. 12A, a MOSFET is shown having a depletion 
configuration without a channel, and with source 12 and drain 13 at ground 
potential and gate 23 below threshold. FIG. 12A illustrates depletion 
regions 31 and 32 respectively, in the substrate 11, surrounding the 
source and drain diffusions 12 and 13 respectively, resulting from these 
P-N junctions. A junction voltage V.sub.o appears on the diffusion at the 
stochastic junction between the diffusion and the substrate. This voltage 
is the result of achieving a constant Fermi potential across the junction. 
Junction voltage V.sub.o is given below for an abrupt junction: 
##EQU40## 
The width W.sub.d of the depletion region (31 or 32) extending into the 
p-substrate from the drain or source diffusions is expressed as follows: 
##EQU41## 
If the donor concentration N.sub.d of the drain and source diffusions is 
much greater than acceptor concentration N.sub.a, Equation 53 may be 
simplified. This simplification has been used above: 
##EQU42## 
The effect of these depletion regions upon channel formation will now be 
described. When gate voltage is applied, a uniform equipotential situation 
must occur, which blends the equipotential contours below the channel, 
with those contours already surrounding the diffusions. The result is 
illustrated in FIG. 12B. In order to satisfy the equipotential criterion, 
the ionized P-region under the gate oxide layer, as a result of gate 
voltage, does not extend all the way to the diffusions. Neither does the 
channel 15. 
The penetration distance X.sub.c of the channel and its associated 
depletion region into the drain and source depletion regions, may be 
calculated as follows: Assuming an abrupt junction, FIG. 13 illustrates 
the potential vs. distance from the stochastic junction of the source or 
drain depletion regions. 
For Poisson's equation the following expression describes junction contact 
potential V.sub.o and potential V(X) at position X measured from the end 
of the diffusion depletion region: 
##EQU43## 
where 
##EQU44## 
Solving Equations 56 and 57 for V(X) in terms of W.sub.d and V.sub.o : 
##EQU45## 
Using the expression given by Equation 58B, Equation 59 becomes 
##EQU46## 
The channel spacing distances S may be described in terms of depletion 
potential V(X) at position X as follows: 
##EQU47## 
In order to establish the equipotential contours within the depletion 
region surrounding the drain and source diffusions, FIG. 12B, Voltage V(X) 
must be equal to the potential .phi..sub.s (X) at the ends of the channel 
region. The expression for .phi..sub.s has been previously obtained and is 
repeated below for convenience: 
##EQU48## 
where W.sub.dc is the depth of the depletion region in the substrate below 
the oxide layer. 
##EQU49## 
Potential .phi..sub.s must be equal to diffusion potential V(X). Thus from 
Equations 62 and 60: 
##EQU50## 
Solving Equation 64 for S/W.sub.d, the following expression for the ratio 
of spacing to depletion width is obtained: 
##EQU51## 
It will be understood from Equation 65 that channel spacing disappears 
when .phi..sub.s =V.sub.o. This condition requires that N.sub.p *=N.sub.d 
and is a situation that never occurs. In fact, surface potential 
.phi..sub.s remains close to twice the Fermi potential, 2.phi..sub.f, for 
all practical values of gate voltage. Therefore Equation 65 may be 
conveniently approximated as: 
##EQU52## 
Thus, at threshold, there is a channel-to-diffusion spacing at each end of 
the channel having the value specified by Equation 66. This 
channel-diffusion spacing distance S may be minimized by diminishing 
depletion width W.sub.d by increasing acceptor concentration N.sub.a 
and/or using lightly doped drain and source extension regions. 
The analysis presented above assumes that no voltage is applied to the 
drain or source diffusions. If voltage V is applied, the width of the 
diffusion depletion region increases. This effect is given by Equation 66. 
##EQU53## 
The above analysis may be repeated for an applied voltage V.sub.o. The 
result is that spacing distance, S.sub.d, has the same form as Equation 66 
except that depletion width W.sub.d &gt;W.sub.do due to voltage V. 
##EQU54## 
Accordingly, the effective channel length L* may be defined as follows: 
EQU L*=L-(S.sub.d +S.sub.s), (69) 
where S.sub.s is the channel--diffusion spacing at the source, and S.sub.d 
is the channel--diffusion spacing at the drain. 
For long-channel devices, S.sub.d and S.sub.s remain a small fraction of 
length L. However, for short-channel devices, (S.sub.s +S.sub.d) can be a 
significant fraction of diffusion spacing length L particularly when drain 
voltage is applied. The increase in voltage at the drain end of the 
channel, for example, resulting from drain voltage V.sub.d 
.ltoreq.V.sub.dsat, is modified by the factor 2.phi..sub.f /V.sub.o. Thus: 
EQU V(X)=(2.phi..sub.f /V.sub.o)V.sub.d (70) 
At pinch-off, the following condition applies: 
EQU (2.phi..sub.f /V.sub.o)V.sub.d =(V.sub.g -V.sub.t) (71) 
Solving Equation 70 for pinch-off voltage, one obtains a value greater than 
that reported in the literature: 
##EQU55## 
When drain voltage exceeds pinch-off voltage, the depletion region around 
the drain diffusion expands and the end-of-the-channel region must slip 
back toward the source to maintain potential equilibrium, such that 
V(X)=(V.sub.g -V.sub.t). This effect is the origin of drain conductance: 
##EQU56## 
Note that if 2.phi..sub.f =V.sub.o, drain conductance would be zero. If 
acceptor concentration N.sub.a is too high, in the vicinity of the drain 
diffusion adjacent the channel, impact ionization break-down will occur at 
relatively low drain voltage. To summarize the results of effective 
channel length L*, it appears that in conventional FETs, the inversion 
channel never touches the drain or source diffusions due to the self 
depletion regions surrounding these diffusions in the vicinity of the 
intended channel region. Channel conduction requires injection at the 
source. It would also appear that the channel L* is shorter than L by the 
sum of the channel spacing factors S.sub.s +S.sub.d. Thus, the channel 
shrinking effect may be significant in short channel conventional FET 
devices if substrate doping is not increased to accommodate the effect. L* 
is the origin of threshold voltage variation with channel length and drain 
voltage. It will be understood by those having skill in the art that the 
Fermi-FET totally eliminates this problem. Finally, it would appear that 
in conventional FET designs, pinch-off voltage is greater than (V.sub.g 
-V.sub.t) by the factor V.sub.o /2.phi..sub.f. 
Multiple Gate Fermi-FET 
It will be understood by those having skill in the art that many 
applications of FET's require transistors to be connected in series. For 
example, CMOS (complementary MOS) logic technology requires connecting 
transistors in series to achieve the desired logic function while 
maintaining essentially zero idle power. For typical (non-Fermi) FET's, a 
series arrangement of transistors limits circuit performance in several 
ways. First, the threshold voltage for each of the series transistors, at 
best, corresponds to the threshold voltage along the gate of a single 
transistor whose total channel length is equal to the sum of the channel 
length's of all series transistors. In contrast, threshold voltage 
computed for the Fermi-FET is shown in FIG. 14 as a function of position 
along the channel, for a typical P- and N-Channel device. It is apparent 
that threshold voltage remains below V.sub.dd /2 along 80% of the total 
channel length. Based on the above, according to the invention, a separate 
gate may be provided at the drain end of the channel in a Fermi-FET, the 
potential of which is always at the full "on" value. In particular, the 
potential is the power supply voltage, V.sub.dd, for N-channel devices and 
is at ground for P-channel devices. This gate is called an accelerator 
electrode, and is illustrated in FIG. 15, at 23a. The polysilicon gate 
contact is illustrated at 18a. 
The threshold voltage for the remaining gate or gates located along the 
channel of a Fermi-FET device, is reduced substantially by use of the 
accelerator gate technique. Turn on delay is thereby minimized. Variance 
in threshold voltage of series connected transistors adds delay to the 
response time of the circuit and depends on the rise time of each of the 
gate input functions of a conventional CMOS configuration. The current 
capability of the series transistor configuration is diminished by factor 
N from the current conduction capability of a single transistor. It may be 
shown that switching frequency depends inversely on the square of the 
channel length and therefore on N.sup.2, where N is the number of 
transistors connected in series. Therefore, response time varies directly 
with the square of the CMOS Fan-in factor, i.e. N.sup.2. Part of the 
voltage drop along conventional FET transistors, includes differences in 
the depletion potential at both ends of the channel due to diffusions 
contacting the substrate. The Fermi-FET device completely eliminates this 
source of potential drop and therefore is better suited for CMOS than 
conventional FET devices. 
The non-inversion mechanism of filling the self depleted implant channel of 
the Fermi-FET with conduction carriers, permits construction of the 
multi-gate FET design shown in FIG. 16A. FIG. 16B illustrates the 
multi-gate structure operating at pinch-off. 
This plural gate structure is ideal for use in logic circuits or other 
applications requiring transistors connected in series, such as CMOS. The 
multi-gate structure has diffusion rails 33a, 33b that separate one 
transistor channel region from another. These diffusion rails need not 
have contact metal as needed by individual transistors connected in 
series. The depth of the diffusion rails are the same as the source and 
drain regions and nominally have the same depth Y.sub.o as the implemented 
channel. The resistance of the source, drain and rail regions should be 
less than 200.OMEGA. per square. Alternatively, the source drain and rails 
may be deeper than the channel, for example, up to twice as deep. The 
diffusion rail design lowers diffusion capacity and eliminates one 
diffusion per transistor region, thus minimizing the space occupied by the 
circuit. The ends of each poly gate region overlap the rails of width W 
and length L, to ensure proper gate induced channel filling with 
conduction carriers. FIG. 16A does not illustrate a minimum geometry 
configuration. In that case, rail width W would be the same as channel 
length L. 
In the drawings and specification, there have been disclosed typical 
preferred embodiments of the invention and, although specific terms are 
employed, they are used in a generic and descriptive sense only and not 
for purposes of limitation, the scope of the invention being set forth in 
the following claims.