High-frequency ceramic packages with modified castellation and metal layer architectures

In examples, a semiconductor package comprises a ceramic substrate and a horizontal metal layer covered by the ceramic substrate. The metal layer is configured to carry signals in the 5 GHz to 38 GHz frequency range. The package also includes a vertical castellation on an outer surface of the ceramic substrate, the castellation coupled to the metal layer and having a height ranging from 0.10 mm to 0.65 mm.

BACKGROUND

Semiconductor chips are housed inside packages that protect the chips from deleterious environmental influences, such as heat, moisture, and debris. A packaged chip generally communicates with electronic devices outside the package via conductive members (e.g., leads) that are exposed to surfaces of the package. Some packages include substrates on which the semiconductor die is positioned. The substrate may include multiple metal layers, or traces, that carry electrical signals or power.

SUMMARY

In examples, a semiconductor package comprises a ceramic substrate and a horizontal metal layer covered by the ceramic substrate. The metal layer is configured to carry signals in the 5 GHz to 38 GHz frequency range. The package also includes a vertical castellation on an outer surface of the ceramic substrate, the castellation coupled to the metal layer and having a height ranging from 0.10 mm to 0.65 mm.

In examples, a semiconductor package comprises a ceramic substrate and first and second horizontal metal layers covered by the ceramic substrate and coupled to each other by way of one or more vias. The first and second metal layers are configured to carry signals in the 5 GHz to 38 GHz frequency range. The package also includes a vertical castellation on an outer surface of the ceramic substrate, the castellation coupled to the first metal layer at a first location and to the second metal layer at a second location, the first and second locations separated by a vertical distance that is at least 50 percent of the height of the castellation.

In examples, an electronic device, comprises a printed circuit board (PCB) having a conductive trace, and a semiconductor package coupled to the PCB and to the conductive trace by way of a solder fillet. The semiconductor package includes a ceramic substrate, a semiconductor die, and a horizontal metal layer covered by the ceramic substrate and coupled to the semiconductor die by way of one or more vias. The metal layer is configured to carry signals in the 5 GHz to 38 GHz frequency range. The metal layer is coupled to the solder fillet and not coupled to a vertical castellation.

DETAILED DESCRIPTION

Ceramic semiconductor packages are hermetically sealed packages containing ceramic substrates that cover multiple metal layers. A ceramic substrate in such a package may include a cavity at the top of the package, and a semiconductor die may be positioned on the floor of this cavity. The metal layers of the ceramic substrate may be coupled to each other and to the semiconductor die through a network of metallic vias. One or more of the metal layers may be configured to carry high-frequency signals, such as in the 5 Gigahertz (GHz) to 38 GHz frequency range.

The bottom metal layer in the ceramic substrate is used to couple the network of metal layers, vias, and the semiconductor die within the package to electronic components (e.g., conductive traces on a printed circuit board (PCB)) outside the package. However, the bottom metal layer is thin, so it can be difficult to use solder fillets to couple the bottom metal layer to conductive traces on a PCB. To facilitate the coupling of solder fillets to the bottom metal layer of the package, vertical conductive members, called castellations, are provided on the outer surfaces of the package. A castellation couples to the bottom metal layer and thus provides a larger and more vertical surface area to which the solder fillet may couple. In this way, solder fillets form more mechanically stable connections to the bottom metal layer of the package.

The structural configuration of castellations, however, introduces significant drawbacks. In particular, the thin, horizontal bottom metal layer of the package couples to a vertical castellation, and the vertical castellation and the bottom metal layer together couple to a solder fillet, and the solder fillet, in turn, couples to a conductive trace on a PCB. The resulting structure may broadly be described as a thin conductive base layer and a vertical component (e.g., the castellation and solder fillet) that is coupled to the thin conductive base layer, essentially forming a conductive “T” shape. This structure behaves as a quarter wavelength resonator when carrying signals in the GHz range, meaning that the resonance produced by the structure (and more specifically, by the vertical castellation) significantly attenuates high-frequency signals and causes highly problematic insertion losses in frequency bands of interest (e.g., 20 GHz to 30 GHz). The insertion losses negatively impact package performance significantly.

Disclosed herein are various examples of a ceramic package with modified castellations and/or modified metal layer architectures that mitigate the challenges described above. The ceramic packages described herein make it possible to use castellations (e.g., to provide stable solder fillet connections) in high-frequency applications while simultaneously resolving the quarter wavelength resonance and insertion loss challenges described above. In some examples, a castellation height is reduced relative to castellation heights in other solutions, thereby pushing the resonance frequency beyond the frequency bands of interest and mitigating insertion losses. In some examples, multiple metal layers carrying high-frequency signals are coupled to a castellation, thereby reducing the length of castellation that is able to generate resonant signals. Consequently, the resonance frequency is pushed beyond the frequency bands of interest and insertion losses are mitigated. In some examples, a castellation's height is reduced as described above and multiple metal layers are coupled to the castellation as described above, thereby achieving significant mitigation of insertion losses. In some examples, the castellations are omitted, thus achieving significant mitigation of insertion losses.

FIG.1Ais a perspective view of a semiconductor package98in accordance with various examples. In some examples, the package98is a ceramic package that includes a ceramic substrate100. In some examples, the package98may be hermetically sealed. In some examples, the package98includes multiple conductive contacts102. The conductive contacts102are adapted to be coupled to a semiconductor die (not expressly shown). For example, the conductive contacts102may extend through or be exposed to a bottom surface of a cavity103in the ceramic substrate100. A semiconductor die may be positioned in the cavity103and coupled to the conductive contacts102.

The conductive contacts102are coupled to a network of metal layers104and vias108in the package98. The specific configuration of the network of metal layers104and vias108may vary depending on the application. The vias108couple different metal layers104to each other, and at least some of the metal layers104terminate at conductive members, such as vertical castellations110, that are exposed to an exterior of the package98. In this way, a semiconductor die in the package98is able to communicate and/or receive power from electronic devices outside of the package98. The metal layers104may have differing configurations and may be positioned in different horizontal planes relative to one another. At least some of the metal layers104are configured to carry high-frequency signals, such as in the 5 GHz to 38 GHz range. The metal layers104may include conductive traces, such as conductive traces106, that are configured to carry high-frequency signals. Although enumerated using a numeral106, the conductive traces106are instances of, or parts of, metal layers104. The conductive traces106couple to the conductive contacts102, or, alternatively, the conductive traces106couple to other conductive members (e.g., vias108) that couple to the conductive contacts102. The conductive traces106, like other metal layers104, may terminate at the castellations110. In some examples, only one metal layer104(e.g., the bottom-most metal layer among the metal layers104) couples to a castellation110. In some examples, two metal layers104couple to a castellation110. In some examples, three or more metal layers104couple to a castellation110. In the example ofFIGS.1A-1C, the bottom-most metal layer104and the conductive traces106couple to the castellations110, and the remainder of the metal layers104do not couple to the castellations110.

As described above, in other solutions, a vertical castellation can generate the undesirable resonance of high-frequency signals in a frequency band of interest (e.g., a frequency band that is intended to be used in a particular application). Accordingly, in some examples, multiple metal layers may be coupled to a castellation, thereby reducing the length of the castellation in which resonant signals may be generated. Because the length of the castellation in which resonant signals can be generated is reduced, the resonant frequency is increased and is pushed beyond the frequency range of interest. For example, as shown inFIG.1A, the bottom-most metal layer104and the conductive traces106are coupled to the castellations110, and the remaining metal layers104are not coupled to the castellations110. Because multiple metal layers104(including the conductive traces106) are coupled to the castellations110, the portion of each castellation110that is between the point of contact with the metal layers104does not generate resonance. Instead, only the portion of each castellation110that extends above the metal layer104that is most distal from the bottom-most metal layer104generates resonance. The length of the portion of the castellation110that generates resonance is significant because it determines the resonant frequency per expression (1):

L=λ4=c4⁢fres⁢ε(1)
where L is the length of the portion of the castellation110that generates resonance, λ is the wavelength of the signal in the castellation110, c is the speed of light in a vacuum, fresis the resonant frequency generated by the castellation110, and ε is the dielectric constant of the ceramic material that encloses the metal layers. In examples including multiple metal layers104coupling to a castellation110(such as the bottom-most metal layer104and a conductive trace106), L is reduced and equals the length of the castellation110extending beyond the top-most metal layer104that couples to the castellation110. When L is reduced, fresincreases. Accordingly, L can be controlled to produce a fresthat is beyond the frequency band of interest. When fresis beyond the frequency band of interest, insertion losses are also beyond the frequency band of interest, thereby significantly improving insertion losses in the frequency band of interest.FIG.1Bis a top-down view of the structure ofFIG.1A, andFIG.1Cis a profile view of the structure ofFIG.1A.

FIG.2is a simplified schematic diagram of the network of metal layers and vias in the ceramic substrate100. In particular,FIG.2shows conductive contacts102, vias108coupled to the conductive contacts102, metal layers104coupled to the various vias108, and a castellation110. The metal layers104include metal layers104aand104b, which are in different horizontal planes. Metal layer104ais the bottom-most metal layer104in the ceramic substrate100, and metal layer104bis neither the top-most nor the bottom-most metal layer104in the ceramic substrate100(although in some examples, the metal layer104bmay be the top-most metal layer104in the ceramic substrate100). The metal layer104bincludes the conductive traces106(FIG.1A). Both the metal layers104a,104bare coupled to the castellation110. The remaining metal layers104are not coupled to the castellation110, although in some examples, additional metal layers104may be coupled to the castellation110.

In operation, and as indicated by the arrows shown inFIG.2, a semiconductor die coupled to the conductive contacts102provides high-frequency signals (e.g., 5 GHz to 38 GHz) to vias108, which, in turn, provide the signals to the metal layer104b. Vias108provide the signals to the metal layer104a. Metal layers104aand104bprovide the high-frequency signals to the castellation110. The segment of the castellation110between the metal layers104aand104bdoes not generate resonant signals, but the segment of the castellation110that extends above the metal layer104bdoes generate resonant signals. However, the coupling of the metal layer104bto the castellation110reduces the portion of the castellation110that would resonate from the entire castellation110to only the segment of the castellation110that extends above the metal layer104b. Thus, the quantity L in expression (1) above is reduced, and thus fresin expression (1) is increased. The specific location at which the metal layer104bcouples to the castellation110may be adjusted to result in a value of L that produces a value of fresthat is outside the frequency band of interest.

The distance between the locations at which metal layers104aand104bcontact the castellation110may vary, but will be at least 50% of the total height of the castellation110. A distance falling below this range is disadvantageous at least because it results in an unacceptably low resonant frequency in the frequency band of interest and thus unacceptable insertion losses in the frequency band of interest. In some examples, this distance is 100% of the total height of the castellation110to achieve optimal insertion loss mitigation.

FIGS.3A1-3E1are perspective views of metal layers in a semiconductor package in accordance with various examples, and FIGS.3A2-3E2are top-down views of metal layers in a semiconductor package in accordance with various examples. Each pair of drawings (e.g.,3A1and3A2;3B1and3B2, etc.) depicts different structures that may be used as part of conductive traces106, and more specifically, the portion of conductive traces106that couple to castellations110and to the vias108most proximal to the castellations110, as shown.

FIG.4is a graph depicting improvements in insertion loss associated with the package98. Curve400depicts insertion losses as a function of the frequency of signals carried through the network of metal layers and vias in a conventional package. As shown, insertion losses are significant in the 20 GHz to 30 GHz range, which is the frequency range at which the castellation of the conventional package resonates. The insertion losses in the range of 45 GHz and beyond are irrelevant as they are outside the frequency band of interest (e.g., 5 GHz to 38 GHz). Curve402depicts insertion losses as a function of the frequency of signals carried through the network of metal layers and vias in the package98. As shown, the insertion losses are still present, but they have been pushed to the highest end, and beyond the highest end, of the frequency band of interest (e.g., 5 GHz to 38 GHz). Within the frequency band of interest, such as from 5 GHz to 38 GHz, insertion losses are generally superior in the package98relative to insertion losses in a conventional package.

As described above, the length of the segment of a castellation110that produces resonant signals determines the resonant frequency. Thus, reducing the length of this segment L (expression (1) above) by coupling another metal layer104to the castellation110increases the resonant frequency fresto a range that is outside the frequency band of interest. In some examples, however, this principle is leveraged in a different way. Specifically, instead of coupling another metal layer104to the castellation110to reduce L as described above, in some examples, L may be reduced by reducing the height of the castellation110. In such examples, a single metal layer104(e.g., the bottom-most metal layer104, such as metal layer104ainFIG.2) is coupled to the castellation110, but the castellation110height is reduced, thereby reducing L in expression (1) and realizing the improvements in insertion losses in the frequency band of interest as described above.

FIG.5Ais a perspective view of a semiconductor package500in accordance with various examples. Package500is similar, but not identical, to package98described above, with like numerals referring to like components, with the exceptions described below. InFIG.5A, only the bottom-most metal layer104is coupled to the castellation110. However, the height of the castellation110is reduced relative to castellation heights used in other solutions. The height of a castellation110ranges from 0.10 mm to 0.65 mm as measured from a bottom surface of the ceramic substrate100, with a height greater than this range resulting in an unacceptably high degree of resonance and insertion losses, and with a height lower than this range resulting in solder fillets having heights that produce unacceptably low levels of mechanical stability, as solder fillets are used to couple the castellations110to a PCB.FIG.5Bis a top-down view of the structure ofFIG.5A, andFIG.5Cis a profile view of the structure ofFIG.5A.FIG.6is a diagram of a network of metal layers and vias in a semiconductor package in accordance with various examples. AsFIG.6shows, the total height of the castellation110is reduced compared to other solutions in which the castellation110typically extends along the full height of the ceramic substrate100. The height of the castellation110is within the range provided above. Furthermore, the only metal layer104to make contact with the castellation110is the bottom-most metal layer104, as shown, although in some examples, a different metal layer104may contact the castellation110. Because the height of the castellation110is reduced, L (expression (1) above) is reduced, thereby increasing the resonant frequency Fres(expression (1) above) and mitigating the insertion loss challenges described above.

The castellation height reduction of package500and the multiple metal layer-to-castellation contacts of package98may be combined to mitigate the insertion losses described above. These insertion losses are mitigated because the distance L in expression (1) is reduced relative to other, prior solutions.FIG.7Ais a perspective view of a semiconductor package700in accordance with various examples. Package700is similar, but not identical, to packages98and500described above, with like numerals referring to like components, with the exceptions described below. In package700, the heights of the castellations110are reduced as in package500(FIGS.5A-5C and6), and there are multiple metal layers104that make contact with the castellations110as in package98(FIGS.1A-1C and2).FIG.7Bis a top-down view of the structure ofFIG.7A,FIG.7Cis a profile view of the structure ofFIG.7A, andFIG.8is a schematic diagram of the network of metal layers and vias in the package700. In package700, the castellation110height ranges from 0.10 mm to 0.65 mm, with castellation heights outside this range having the disadvantages described above. Further, the distance between the points at which the metal layers104aand104bcontact the castellation110(FIG.8) may vary, but will be at least 50% of the total height of the castellation110. A distance falling below this range is disadvantageous at least because it results in an unacceptably low resonant frequency in the frequency band of interest and thus unacceptable insertion losses in the frequency band of interest. In some examples, this distance is 100% of the total height of the castellation110to achieve optimal insertion loss mitigation.

FIG.9is a graph depicting improvements in insertion loss associated with semiconductor package700, in accordance with various examples. Curve900depicts insertion losses as a function of operating frequency in prior solutions, and curve902depicts insertion losses as a function of operating frequency in the package700. As shown, both curves900,902demonstrate insertion losses, but the insertion losses in curve902are outside of the frequency band of interest (e.g., 5 GHz to 38 GHz). Within the frequency band of interest (e.g., 5 GHz to 38 GHz), insertion losses are generally superior for the curve902than for the curve900.

FIG.10is a graph depicting phase variation improvements associated with a semiconductor package that is in accordance with various examples.FIG.11is a graph depicting phase and magnitude improvements associated with a semiconductor package that is in accordance with various examples.FIG.12is a graph depicting peaking and loss improvements associated with a semiconductor package that is in accordance with various examples. In particular, the graph ofFIG.10includes a top plot and a bottom plot. The top plot demonstrates the phase behavior in degrees as a function of frequency in Hertz (Hz). The bottom plot demonstrates loop gain in decibels (dB) as a function of frequency in Hz. Curves1000and1004demonstrate the behavior of other solutions, and curves1002and1006demonstrate the behavior of packages in accordance with various examples of this disclosure. Curve1000demonstrates significant phase variation, while curve1002demonstrates greater phase stability. This increase in phase stability occurs because there is no resonance observed in-band from the package parasitics, resulting in improved package insertion losses and return losses. Curve1004demonstrates less ringing, while curve1006demonstrates greater ringing.

The graph ofFIG.11includes a top plot and a bottom plot. The bottom plot demonstrates the phase behavior in degrees as a function of frequency in Hertz (Hz). The top plot demonstrates loop gain in decibels (dB) as a function of frequency in Hz. Curves1100and1104demonstrate the behavior of other solutions, and curves1102and1106demonstrate the behavior of packages in accordance with various examples of this disclosure. Curve1104demonstrates significant phase variation, while curve1106demonstrates greater phase stability. This increase in phase stability occurs because there is no resonance observed in-band from the package parasitics. Curve1100demonstrates more ringing, indicating worse stability, while curve1102demonstrates less ringing, indicating superior stability.

The graph ofFIG.12includes a top plot and a bottom plot. The top plot demonstrates chip and package amplification gain on the y-axis in dB as a function of frequency in Hz, and the bottom plot demonstrates chip, package and PCB amplification gain on the y-axis in dB as a function of frequency in Hz. Curves1200and1204demonstrate the behavior of other solutions, and curves1202and1206demonstrate the behavior of packages in accordance with various examples of this disclosure. Curve1200demonstrates better ringing and worse amplification performance because of the resonance caused by package castellation, while curve1202demonstrates less ringing and improved amplification performance because the resonance is reduced or eliminated by using the structures described herein. Curve1204demonstrates greater ringing and worse amplification performance because of the resonance caused by package castellations, while curve1206demonstrates less ringing and improved amplification performance because the resonance is mitigated using the structures described herein.

In some examples, one or more castellations may be omitted so as to eliminate castellation-related resonance. In such examples, solder fillets on a PCB are coupled directly to one or more metal layers (e.g., the bottom-most metal layer in the package).FIG.13Ais a perspective view of a semiconductor package1300in accordance with examples. As shown, castellations are omitted from the package1300. Consequently, the resonance and attendant insertion losses described above as being generated by castellations110are absent from the package1300, thus significantly improving insertion loss performance.FIG.13Bis a top-down view of the package1300, andFIG.13Cis a profile view of the package1300.FIG.14is a schematic diagram of a network of metal layers and vias in a semiconductor package in accordance with various examples. As shown, the lack of a castellation results in no castellation-induced resonance. The bottom-most metal layer104amay couple directly with a solder fillet on a PCB and not to a castellation.

FIG.15is a graph depicting improvements in insertion loss associated with a semiconductor package1300in accordance with various examples. The y-axis represents insertion losses, and the x-axis represents frequency in GHz. Curve1500demonstrates the behavior of other solutions, and curve1502demonstrates the behavior of the package1300. As shown, curve1500demonstrates significant insertion losses in the frequency band of interest (e.g., 5 GHz to 38 GHz), while curve1502demonstrates no significant insertion losses.

FIG.16is a flow diagram of a method1600in accordance with various examples. The method1600begins with forming an array of ceramic substrates layer by layer including punching via and castellation orifices, filling the via and castellation orifices with metal, and screen printing the metal layers (1602). Step1602is performed iteratively, layer by layer, until the array of ceramic substrates is complete. The precise manner in which the orifices are punched and filled with metal, as well as the precise screen printing patterns used, are application specific. The castellations and metal layers may be formed in accordance with one or more examples described herein. The method1600includes performing a singulation technique on the array to produce an individual ceramic substrate (1604). The method1600includes co-firing the ceramic substrate (1606) (e.g., at a temperature up to 1600 degrees Celsius) and brazing and plating the ceramic substrate (1608). The method1600includes positioning a semiconductor die in a cavity of the ceramic substrate (1610) and covering the cavity with a lid using a vacuum technique to hermetically seal the cavity (1612).

FIG.17is a block diagram of an electronic device1700in accordance with various examples. The electronic device1700may include a personal electronic device (e.g., smartphones, laptop computers, desktop computers, tablets, notebooks, artificial intelligence assistants), an electronic appliance (e.g., refrigerators, microwave ovens, toaster ovens, dishwashers), a networking or enterprise-level electronic device or system (e.g., servers, routers, modems, mainframe computers, wireless access points), an automobile or aviation device or system (e.g., control panels, entertainment devices, navigation devices, power electronics), or any of a variety of other electronic devices or systems. The electronic device1700may include a PCB1702. A semiconductor package1704, such as any of the packages described herein, may be coupled to the PCB1702.

A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or re-configurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value means+/−10 percent of the stated value. Modifications are possible in the described examples, and other examples are possible within the scope of the claims.