Semiconductor device and methods of formation

A cladding sidewall layer footing is removed prior to formation of a hybrid fin structure. Removal of the cladding sidewall layer footing prevents a metal gate footing from forming under the hybrid fin structure when the cladding sidewall layer is removed to enable the metal gate to be formed around the nanostructure channels of a nanostructure transistor. Cladding sidewall layers can be formed in an asymmetric manner to include different lengths and/or angles, among other examples. The asymmetric cladding sidewall layers enable asymmetric metal gate structures to be formed for p-type and n-type nanostructure transistors while preventing metal gate footings from forming under hybrid fin structures for p-type and n-type nanostructure transistors. This may reduce a likelihood of short channel effects and leakage within the nanostructure transistors yield of nanostructure transistors formed on a semiconductor substrate.

BACKGROUND

As semiconductor device manufacturing advances and technology processing nodes decrease in size, transistors may become affected by short channel effects (SCEs) such as hot carrier degradation, barrier lowering, and quantum confinement, among other examples. In addition, as the gate length of a transistor is reduced for smaller technology nodes, source/drain (S/D) electron tunneling increases, which increases the off current for a transistor (the current that flows through the channel of the transistor when the transistor is in an off configuration). Silicon (Si)/silicon germanium (SiGe) nanostructure transistors such as nanowires, nanosheets, and gate-all-around (GAA) devices are potential candidates to overcome short channel effects at smaller technology nodes. Nanostructure transistors are efficient structures that may experience reduced SCEs and enhanced carrier mobility relative to other types of transistors.

DETAILED DESCRIPTION

In some cases, reducing geometric and dimensional properties of a fin field-effect transistor (finFET) may decrease a performance of the finFET. As an example, a likelihood of short channel effects such as drain-induced barrier lowering in a finFET may increase as finFET technology processing nodes decrease. Additionally or alternatively, a likelihood of electron tunneling and leakage in a finFET may increase as a gate length of the finFET decreases.

Nanostructure transistors (e.g., nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and/or other types of nanostructure transistors) may overcome one or more of the above-described drawbacks of finFETs. However, nanostructure transistors face fabrication challenges that can cause performance issues and/or device failures. For example, a cladding sidewall layer may be formed in a nanostructure transistor as a temporary structure to enable the formation of a metal gate (MG) that surrounds the nanostructure channels of the nanostructure transistor. Methods of forming the cladding sidewall layer may result in protrusions (e.g., an overhang of the cladding sidewall layer on a hard mask region of the nanostructure transistor and/or a footing of the cladding sidewall layer on a shallow trench isolation (STI) region of the nanostructure transistor under an adjacent hybrid fin structure, among other examples). As a result, when the cladding sidewall layer is removed so that the metal gate can be formed in the area that was occupied by the cladding sidewall layer, a footing of the metal gate also protrudes under the adjacent hybrid fin structure, which may cause electrical shorting between the metal gate and a source/drain contact (MD) of the nanostructure transistor. An electrical short between the metal gate and the source/drain contact may result in a failure of the nanostructure transistor and reduced yield of nanostructure transistors formed on a semiconductor substrate.

Some implementations described herein provide nanostructure transistors and methods of formation such that a cladding sidewall layer footing is removed prior to formation of a hybrid fin structure. Removal of the cladding sidewall layer footing prevents a metal gate footing from forming under the hybrid fin structure when the cladding sidewall layer is removed to enable the metal gate to be formed around the nanostructure channels of a nanostructure transistor. As described herein, cladding sidewall layers can be formed in an asymmetric manner to include different lengths and/or angles, among other examples. The asymmetric cladding sidewall layers enable metal gate structures to be formed for p-type and n-type nanostructure transistors while preventing metal gate footings from forming under hybrid fin structures for p-type and n-type nanostructure transistors. This may reduce a likelihood of short channel effects and leakage within the nanostructure transistors yield of nanostructure transistors formed on a semiconductor substrate.

FIG.1is a diagram of an example environment100in which systems and/or methods described herein may be implemented. As shown inFIG.1, environment100may include a plurality of semiconductor processing tools102-112and a wafer/die transport tool114. The plurality of semiconductor processing tools102-112may include a deposition tool102, an exposure tool104, a developer tool106, an etch tool108, a planarization tool110, a plating tool112, and/or another type of semiconductor processing tool. The tools included in example environment100may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and/or manufacturing facility, among other examples.

The deposition tool102is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some implementations, the deposition tool102includes a spin coating tool that is capable of depositing a photoresist layer on a substrate such as a wafer. In some implementations, the deposition tool102includes a chemical vapor deposition (CVD) tool such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some implementations, the deposition tool102includes a physical vapor deposition (PVD) tool, such as a sputtering tool or another type of PVD tool. In some implementations, the deposition tool102includes an epitaxial tool that is configured to form layers and/or regions of a device by epitaxial growth. In some implementations, the example environment100includes a plurality of types of deposition tools102.

The developer tool106is a semiconductor processing tool that is capable of developing a photoresist layer that has been exposed to a radiation source to develop a pattern transferred to the photoresist layer from the exposure tool104. In some implementations, the developer tool106develops a pattern by removing unexposed portions of a photoresist layer. In some implementations, the developer tool106develops a pattern by removing exposed portions of a photoresist layer. In some implementations, the developer tool106develops a pattern by dissolving exposed or unexposed portions of a photoresist layer through the use of a chemical developer.

The etch tool108is a semiconductor processing tool that is capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etch tool108may include a wet etch tool, a dry etch tool, and/or the like. In some implementations, the etch tool108includes a chamber that is filled with an etchant, and the substrate is placed in the chamber for a particular time period to remove particular amounts of one or more portions of the substrate. In some implementations, the etch tool108may etch one or more portions of the substrate using a plasma etch or a plasma-assisted etch, which may involve using an ionized gas to isotropically or directionally etch the one or more portions.

The planarization tool110is a semiconductor processing tool that is capable of polishing or planarizing various layers of a wafer or semiconductor device. For example, a planarization tool110may include a chemical mechanical planarization (CMP) tool and/or another type of planarization tool that polishes or planarizes a layer or surface of deposited or plated material. The planarization tool110may polish or planarize a surface of a semiconductor device with a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing). The planarization tool110may utilize an abrasive and corrosive chemical slurry in conjunction with a polishing pad and retaining ring (e.g., typically of a greater diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by the retaining ring. The dynamic polishing head may rotate with different axes of rotation to remove material and even out any irregular topography of the semiconductor device, making the semiconductor device flat or planar.

The plating tool112is a semiconductor processing tool that is capable of plating a substrate (e.g., a wafer, a semiconductor device, and/or the like) or a portion thereof with one or more metals. For example, the plating tool112may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver, tin-lead, and/or the like) electroplating device, and/or an electroplating device for one or more other types of conductive materials, metals, and/or similar types of materials.

Wafer/die transport tool114includes a mobile robot, a robot arm, a tram or rail car, an overhead hoist transport (OHT) system, an automated materially handling system (AMHS), and/or another type of device that is configured to transport substrates and/or semiconductor devices between semiconductor processing tools102-112, that is configured to transport substrates and/or semiconductor devices between processing chambers of the same semiconductor processing tool, and/or that is configured to transport substrates and/or semiconductor devices to and from other locations such as a wafer rack, a storage room, and/or the like. In some implementations, wafer/die transport tool114may be a programmed device that is configured to travel a particular path and/or may operate semi-autonomously or autonomously. In some implementations, the environment100includes a plurality of wafer/die transport tools114.

For example, the wafer/die transport tool114may be included in a cluster tool or another type of tool that includes a plurality of processing chambers, and may be configured to transport substrates and/or semiconductor devices between the plurality of processing chambers, to transport substrates and/or semiconductor devices between a processing chamber and a buffer area, to transport substrates and/or semiconductor devices between a processing chamber and an interface tool such as an equipment front end module (EFEM), and/or to transport substrates and/or semiconductor devices between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), among other examples. In some implementations, a wafer/die transport tool114may be included in a multi-chamber (or cluster) deposition tool102, which may include a pre-clean processing chamber (e.g., for cleaning or removing oxides, oxidation, and/or other types of contamination or byproducts from a substrate and/or semiconductor device) and a plurality of types of deposition processing chambers (e.g., processing chambers for depositing different types of materials, processing chambers for performing different types of deposition operations). In these implementations, the wafer/die transport tool114is configured to transport substrates and/or semiconductor devices between the processing chambers of the deposition tool102without breaking or removing a vacuum (or an at least partial vacuum) between the processing chambers and/or between processing operations in the deposition tool102, as described herein.

The number and arrangement of devices shown inFIG.1are provided as one or more examples. In practice, there may be additional devices, fewer devices, different devices, or differently arranged devices than those shown inFIG.1. Furthermore, two or more devices shown inFIG.1may be implemented within a single device, or a single device shown inFIG.1may be implemented as multiple, distributed devices. Additionally, or alternatively, a set of devices (e.g., one or more devices) of environment100may perform one or more functions described as being performed by another set of devices of environment100.

FIG.2is a diagram of an example semiconductor device200described herein. The semiconductor device200includes one or more transistors. The one or more transistors may include nanostructure transistor(s) such as nanowire transistors, nanosheet transistors, gate-all-around (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and/or other types of nanostructure transistors. The semiconductor device200may include one or more additional devices, structures, and/or layers not shown inFIG.2. For example, the semiconductor device200may include additional layers and/or dies formed on layers above and/or below the portion of the semiconductor device200shown inFIG.2. Additionally, or alternatively, one or more additional semiconductor structures and/or semiconductor devices may be formed in a same layer of an electronic device or integrated circuit (IC) that includes the semiconductor device, with a lateral displacement, as the semiconductor device200shown inFIG.2.FIGS.3A-3Uare schematic cross-sectional views of various portions of the semiconductor device200illustrated inFIG.2, and correspond to various processing stages of forming nanostructure transistors of the semiconductor device200.

The semiconductor device200includes a semiconductor substrate202. The semiconductor substrate202includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon on insulator (SOI) substrate, a germanium substrate (Ge), a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate. The semiconductor substrate202may include various layers, including conductive or insulating layers formed on a semiconductor substrate. The semiconductor substrate202may include a compound semiconductor and/or an alloy semiconductor. The semiconductor substrate202may include various doping configurations to satisfy one or more design parameters. For example, different doping profiles (e.g., n-wells, p-wells) may be formed on the semiconductor substrate202in regions designed for different device types (e.g., p-type metal-oxide semiconductor (PMOS) nanostructure transistors, n-type metal-oxide semiconductor (NMOS) nanostructure transistors). The suitable doping may include ion implantation of dopants and/or diffusion processes. Further, the semiconductor substrate202may include an epitaxial layer (epi-layer), may be strained for performance enhancement, and/or may have other suitable enhancement features. The semiconductor substrate202may include a portion of a semiconductor wafer on which other semiconductor devices are formed.

Fin structures204are included above (and/or extend above) the semiconductor substrate202. A fin structure204provides a structure on which layers and/or other structures of the semiconductor device200are formed, such as epitaxial regions and/or gate structures, among other examples. In some implementations, the fin structures204include the same material as the semiconductor substrate202and are formed from the semiconductor substrate202. In some implementations, the fin structures204include silicon (Si) materials or another elementary semiconductor material such as germanium (Ge). In some implementations, the fin structures204include an alloy semiconductor material such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), or a combination thereof.

The fin structures204are fabricated by suitable semiconductor process techniques, such as masking, photolithography, and/or etch processes, among other examples. As an example, the fin structures204may be formed by etching a portion of the semiconductor substrate202away to form recesses in the semiconductor substrate202. The recesses may then be filled with isolating material that is recessed or etched back to form shallow trench isolation (STI) regions206above the semiconductor substrate202and between the fin structures204. Other fabrication techniques for the STI regions206and/or for the fin structures204may be used. The STI regions206may electrically isolate adjacent fin structures204and may provide a layer on which other layers and/or structures of the semiconductor device200are formed. The STI regions206may include a dielectric material such as a silicon oxide (SiOx), a silicon nitride (SixNy), a silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or another suitable insulating material. The STI regions206may include a multi-layer structure, for example, having one or more liner layers.

The semiconductor device200includes a plurality of channels208that extend between, and are electrically coupled with, source/drain regions210. The channels208include silicon-based nanostructures (e.g., nanosheets or nanowires, among other examples) that function as the semiconductive channels of the nanostructure transistor(s) of the semiconductor device200. The channels208may include silicon germanium (SiGe) or another silicon-based material. The source/drain regions210include silicon (Si) with one or more dopants, such as a p-type material (e.g., boron (B) or germanium (Ge), among other examples), an n-type material (e.g., phosphorous (P) or arsenic (As), among other examples), and/or another type of dopant. Accordingly, the semiconductor device200may include p-type metal-oxide semiconductor (PMOS) nanostructure transistors that include p-type source/drain regions210, n-type metal-oxide semiconductor (NMOS) nanostructure transistors that include n-type source/drain regions210, and/or other types of nanostructure transistors.

In some implementations, the semiconductor device200includes a plurality of types of fin structures. For example, the fin structures204may be referred to as active fins in that the channels208and source/drain regions210are formed and included over the fin structures204. Another type of fin structure includes hybrid fin structures. The hybrid fin structures may also be referred to as dummy fins, H-fins, or non-active fins, among other examples. Hybrid fin structures may be included between adjacent fin structures204(e.g., between adjacent active fin structures). The hybrid fins extend in a direction that is approximately parallel to the fin structures204.

Hybrid fin structures are configured to provide electrical isolation between two or more structures and/or components included in the semiconductor device200. In some implementations, a hybrid fin structure is configured to provide electrical isolation between two or more fin structures204(e.g., two or more active fin structures). In some implementations, a hybrid fin structure is configured to provide electrical isolation between two or more source/drain regions210. In some implementations, a hybrid fin structure is configured to provide electrical isolation between two or more gates structures or two or more portions of a gate structure. In some implementations, a hybrid fin structure is configured to provide electrical isolation between a source/drain region210and a gate structure.

A hybrid fin structure may include a plurality of types of dielectric materials. A hybrid fin structure may include a combination of one or more low dielectric constant (low-k) dielectric materials (e.g., a silicon oxide (SiOx) and/or a silicon nitride (SixNy), among other examples) and one or more high dielectric constant (high-k) dielectric materials (e.g., a hafnium oxide (HfOx) and/or other high-k dielectric material).

At least a subset of the channels208extend through one or more gate structures212. The gate structures212may be formed of one or more metal materials, one or more high dielectric constant (high-k) materials, and/or one or more other types of materials. In some implementations, dummy gate structures (e.g., polysilicon (PO) gate structures or another type of gate structures) are formed in the place of (e.g., prior to formation of) the gate structures212so that one or more other layers and/or structures of the semiconductor device200may be formed prior to formation of the gate structures212. This reduces and/or prevents damage to the gate structures212that would otherwise be caused by the formation of the one or more layers and/or structures. A replacement gate process (RGP) is then performed to remove the dummy gate structures and replace the dummy gate structures with the gate structures212(e.g., replacement gate structures).

As further shown inFIG.2, portions of a gate structure212are formed in between pairs of channels208in an alternating vertical arrangement. In other words, the semiconductor device200includes one or more vertical stacks of alternating channels208and portions of a gate structure212, as shown inFIG.2. In this way, a gate structure212wraps around an associated channel208on all sides of the channel208which increases control of the channel208, increases drive current for the nanostructure transistor(s) of the semiconductor device200, and reduces short channel effects (SCEs) for the nanostructure transistor(s) of the semiconductor device200.

Some source/drain regions210and gate structures212may be shared between two or more nanoscale transistors of the semiconductor device200. In these implementations, one or more source/drain regions210and a gate structure212may be connected or coupled to a plurality of channels208, as shown in the example inFIG.2. This enables the plurality of channels208to be controlled by a single gate structure212and a pair of source/drain regions210.

The semiconductor device200may also include an inter-layer dielectric (ILD) layer214above the STI regions206. The ILD layer214may be referred to as an ILD0 layer. The ILD layer214surrounds the gate structures212to provide electrical isolation and/or insulation between the gate structures212and/or the source/drain regions210, among other examples. Conductive structures such as contacts and/or interconnects may be formed through the ILD layer214to the source/drain regions210and the gate structures212to provide control of the source/drain regions210and the gate structures212.

FIGS.3A-3Uare diagrams of an example implementation300described herein. Operations shown in the example implementation300may be performed in a different order than shown inFIGS.3A-3U. The example implementation300includes an example of forming the semiconductor device200or a portion thereof (e.g., an example of forming nanostructure transistor(s) of the semiconductor device200). The semiconductor device200may include one or more additional devices, structures, and/or layers not shown inFIGS.3A-3U. The semiconductor device200may include additional layers and/or dies formed on layers above and/or below the portion of the semiconductor device200shown inFIGS.3A-3U. Additionally, or alternatively, one or more additional semiconductor structures and/or semiconductor devices may be formed in a same layer of an electronic device that includes the semiconductor device200.

Furthermore, the operations may encompass parameters described in connection withFIGS.6,7A,7B, and8, and elsewhere herein. In some implementations, the operations include forming a dielectric layer between a first fin structure (e.g., a first fin structure204) that is above the semiconductor substrate202and a second fin structure (e.g., a second fin structure204) that is above the semiconductor substrate202and is adjacent to the first fin structure. The operations may include removing portions of the dielectric layer to form the STI region206between the first fin structure and the second fin structure and to form a recess above the STI region206. The operations may include forming, in the recess, a cladding layer over a first sidewall of the first fin structure, over a second sidewall of the second fin structure, and over a top surface of the STI region206. The operations may include removing the cladding layer from the top surface of the STI region206to leave a first cladding sidewall layer along the first sidewall and a second cladding sidewall layer along the second sidewall. In some implementations, the first cladding sidewall layer and the second cladding sidewall layer include respective lengths that are asymmetric. The asymmetric lengths may provide sufficient electrical isolation for different types of fin structures (e.g., fin structures for p-type nanostructure transistors and fin structures for n-type nanostructure transistors) while reducing and/or minimizing footing of the first and second cladding sidewall layers on the STI region206. The reduced and/or minimized footing may reduce the likelihood of electrical shorting in the semiconductor device200.

FIGS.3A and3Brespectively illustrate a perspective view of the semiconductor device200and a cross-sectional view along the line A-A inFIG.3A. As shown inFIGS.3A and3B, processing of the semiconductor device200is performed in connection with the semiconductor substrate202. A layer stack302is formed on the semiconductor substrate202. The layer stack302may be referred to as a superlattice. In some implementations, one or more operations are performed in connection with the semiconductor substrate202prior to formation of the layer stack302. For example, an anti-punch through (APT) implant operation may be performed. The APT implant operation may be performed in one or more regions of the semiconductor substrate202above which channels208are to be formed. The APT implant operation is performed, for example, to reduce and/or prevent punch-through or unwanted diffusion into the semiconductor substrate202.

The layer stack302includes a plurality of alternating layers. The alternating layers include a plurality of first layers304and a plurality of second layers306. The quantity of the first layers304and the quantity of the second layers306illustrated inFIGS.3A and3Bare examples, and other quantities of the first layers304and the second layers306are within the scope of the present disclosure. In some implementations, the first layers304and the second layers306are formed to different thicknesses. For example, the second layers306may be formed to a thickness that is greater relative to a thickness of the first layers304. In some implementations, the first layers304(or a subset thereof) are formed to a thickness in a range of approximately 4 nanometers to approximately 7 nanometers. In some implementations, the second layers306(or a subset thereof) are formed to a thickness in a range of approximately 8 nanometers to approximately 12 nanometers. However, other values for the thickness of the first layers304and for the thickness of the second layers306are within the scope of the present disclosure.

The first layers304include a first material composition, and the second layers306include a second material composition. In some implementations, the first material composition and the second material composition are the same material composition. In some implementations, the first material composition and the second material composition are different material compositions. As an example, the first layers304may include silicon germanium (SiGe) and the second layers306may include silicon (Si). In some implementations, the first material composition and the second material composition have different oxidation rates and/or etch selectivity.

As described herein, the second layers306may be processed to form the channel208for subsequently-formed nanostructure transistors of the semiconductor device200. The first layers304are eventually removed and serve to define a vertical distance between an adjacent channel208for subsequently-formed nanostructure transistors of the semiconductor device200. Accordingly, the first layers304may also be referred to as sacrificial layers, and the second layers306may be referred to as channel layers.

The deposition tool102deposits and/or grows the alternating layers to include nanostructures (e.g., nanosheets) on the semiconductor substrate202. For example, the deposition tool102grows the alternating layers by epitaxial growth. However, other processes may be used to form the alternating layers of the layer stack302. Epitaxial growth of the alternating layers of the layer stack302may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or another suitable epitaxial growth process. In some implementations, the epitaxially grown layers such as the second layers306include the same material as the material of the semiconductor substrate202. In some implementations, the first layers304and/or the second layers306include a material that is different from the material of the semiconductor substrate202. As described above, in some implementations, the first layers304include epitaxially grown silicon germanium (SiGe) layers and the second layers306include epitaxially grown silicon (Si) layers. Alternatively, the first layers304and/or the second layers306may include other materials such as germanium (Ge), a compound semiconductor material such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), indium antimonide (InSb), an alloy semiconductor such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), indium gallium arsenide (InGaAs), gallium indium phosphide (GaInP), gallium indium arsenide phosphide (GaInAsP), and/or a combination thereof. The material(s) of the first layers304and/or the material(s) of the second layers306may be chosen based on providing different oxidation properties, different etching selectivity properties, and/or other different properties.

As further shown inFIGS.3A and3B, the deposition tool102may form one or more additional layers over and/or on the layer stack302. For example, a hard mask (HM) layer308may be formed over and/or on the layer stack302(e.g., on the top-most second layer306of the layer stack302). As another example, a capping layer310may be formed over and/or on the hard mask layer308. As another example, another hard mask layer including an oxide layer312and a nitride layer314may be formed over and/or on the capping layer310. The one or more hard mask (HM) layers308,312, and314may be used to form one or more structures of the semiconductor device200. The oxide layer312may function as an adhesion layer between the layer stack302and the nitride layer314, and may act as an etch stop layer for etching the nitride layer314. The one or more hard mask layers308,312, and314may include silicon germanium (SiGe), a silicon nitride (SixNy), a silicon oxide (SiOx), and/or another material. The capping layer310may include silicon (Si) and/or another material. In some implementations, the capping layer310is formed of the same material as the semiconductor substrate202. In some implementations, the one or more additional layers are thermally grown, deposited by CVD, PVD, ALD, and/or are formed using another deposition technique.

FIGS.3C and3Drespectively illustrate a perspective view of the semiconductor device200and a cross-sectional view along the line A-A inFIG.3C. As shown inFIGS.3C and3D, fin structures204are formed above the semiconductor substrate202of the semiconductor device200. A fin structure204includes a portion316of the layer stack302over and/or on a portion318formed in and/or above the semiconductor substrate202. The portion318of the fin structure204may be referred to as a mesa region (e.g., a silicon mesa) of the fin structure204on which the portion316of the layer stack302is included. The fin structures204may be formed by any suitable semiconductor processing technique. For example, the fin structures204may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, a sacrificial layer may be formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fin structures.

The fin structures204may subsequently be fabricated using suitable processes including photolithography and etch processes. In some implementations, the deposition tool102forms a photoresist layer over and/or on the hard mask layer including the oxide layer312and the nitride layer314, the exposure tool104exposes the photoresist layer to radiation (e.g., deep ultraviolet (UV) radiation, extreme UV (EUV) radiation), a post-exposure bake process is performed (e.g., to remove residual solvents from the photoresist layer), and the developer tool106develops the photoresist layer to form a masking element (or pattern) in the photoresist layer. In some implementations, patterning the photoresist layer to form the masking element is performed using an electron beam (e-beam) lithography process. The masking element may then be used to protect portions of the semiconductor substrate202and portions the layer stack302in an etch operation such that the portions of the semiconductor substrate202and portions the layer stack302remain non-etched to form the fin structures204. Unprotected portions of the substrate and unprotected portions of the layer stack302are etched (e.g., by the etch tool108) to form trenches in the semiconductor substrate202. The etch tool may etch the unprotected portions of the substrate and unprotected portions of the layer stack302using a dry etch technique (e.g., reactive ion etching), a wet etch technique, and/or a combination thereof.

In some implementations, another fin formation technique is used to form the fin structures204. For example, a fin region may be defined (e.g., by mask or isolation regions), and the portions316may be epitaxially grown in the form of the fin structure204. In some implementations, forming the fin structures204includes a trim process to decrease the width of the fin structures204. The trim process may include wet and/or dry etching processes, among other examples.

As further shown inFIG.3D, fin structures204may be formed for different types of nanostructure transistors for the semiconductor device200. In particular, a first subset of fin structures204amay be formed for p-type nanostructure transistors (e.g., p-type metal oxide semiconductor (PMOS) nanostructure transistors), and a second subset of fin structures204bmay be formed for n-type nanostructure transistors (e.g., n-type metal oxide semiconductor (NMOS) nanostructure transistors). The second subset of fin structures204bmay be doped with a p-type dopant (e.g., boron (B) and/or germanium (Ge), among other examples) and the first subset of fin structures204amay be doped with an n-type dopant (e.g., phosphorous (P) and/or arsenic (As), among other examples). Additionally or alternatively, p-type source/drain regions210may be subsequently formed for the p-type nanostructure transistors that include the first subset of fin structures204a, and n-type source/drain regions210may be subsequently formed for the n-type nanostructure transistors that include the second subset of fin structures204b.

The first subset of fin structures204a(e.g., PMOS fin structures) and the second subset of fin structures204b(e.g., NMOS fin structures) may be formed to include similar properties and/or different properties. For example, the first subset of fin structures204amay be formed to a first height and the second subset of fin structures204bmay be formed to a second height, where the first height and the second height are different heights. As another example, the first subset of fin structures204amay be formed to a first width and the second subset of fin structures204bmay be formed to a second width, where the first width and the second width are different widths. In the example shown inFIG.3D, the second width of the second subset of fin structures204b(e.g., for the NMOS nanostructure transistors) is greater relative to the first width of the first subset of fin structures204b(e.g., for the PMOS nanostructure transistors). However, other examples are within the scope of the present disclosure.

FIGS.3E and3Frespectively illustrate a perspective view of the semiconductor device200and a cross-sectional view along the line A-A inFIG.3E. As shown inFIGS.3E and3F, a liner320and a dielectric layer322are formed above the semiconductor substrate202and interposing (e.g., in between) the fin structures204. The deposition tool102may deposit the liner320and the dielectric layer322over the semiconductor substrate202and in the trenches between the fin structures204. The deposition tool102may form the dielectric layer322such that a height of a top surface of the dielectric layer322and a height of a top surface of the nitride layer314are approximately a same height.

Alternatively, the deposition tool102may form the dielectric layer322such that the height of the top surface of the dielectric layer322is greater relative to the height of the top surface of the nitride layer314, as shown inFIGS.3E and3F. In this way, the trenches between the fin structures204are overfilled with the dielectric layer322to ensure the trenches are fully filled with the dielectric layer322. Subsequently, the planarization tool110may perform a planarization or polishing operation (e.g., a CMP operation) to planarize the dielectric layer322. The nitride layer314of the hard mask layer may function as a CMP stop layer in the operation. In other words, the planarization tool110planarizes the dielectric layer322until reaching the nitride layer314of the hard mask layer. Accordingly, a height of top surfaces of the dielectric layer322and a height of top surfaces of the nitride layer314are approximately equal after the operation.

The deposition tool102may deposit the liner320using a conformal deposition technique. The deposition tool102may deposit the dielectric layer using a CVD technique (e.g., a flowable CVD (FCVD) technique or another CVD technique), a PVD technique, an ALD technique, and/or another deposition technique. In some implementations, after deposition of the dielectric layer322, the semiconductor device200is annealed, for example, to increase the quality of the dielectric layer322.

The liner320and the dielectric layer322each includes a dielectric material such as a silicon oxide (SiOx), a silicon nitride (SixNy), a silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or another suitable insulating material. In some implementations, the dielectric layer322may include a multi-layer structure, for example, having one or more liner layers.

FIGS.3G and3Hrespectively illustrate a perspective view of the semiconductor device200and a cross-sectional view along the line A-A inFIG.3G. As shown inFIGS.3G and3H, an etch back operation is performed to remove portions of the liner320and portions of the dielectric layer322to form the STI regions206. The etch tool108may etch the liner320and the dielectric layer322in the etch back operation to form the STI regions206. The etch tool108etches the liner320and the dielectric layer322based on the hard mask layer (e.g., the hard mask layer including the oxide layer312and the nitride layer314). The etch tool108etches the liner320and the dielectric layer322such that the height of the STI regions206are less than or approximately a same height as the bottom of the portions316of the layer stack302. Accordingly, the portions316of the layer stack302extend above the STI regions206. In some implementations, the liner320and the dielectric layer322are etched such that the heights of the STI regions206are less than heights of top surfaces of the portions318.

In some implementations, the etch tool108uses a plasma-based dry etch technique to etch the liner320and the dielectric layer322. Ammonia (NH3), hydrofluoric acid (HF), and/or another etchant may be used. The plasma-based dry etch technique may result in a reaction between the etchant(s) and the material of the liner320and the dielectric layer322, including:
SiO2+4HF→SiF4+2H2O
where silicon dioxide (SiO2) of the liner320and the dielectric layer322react with hydrofluoric acid to form byproducts including silicon tetrafluoride (SiF4) and water (H2O). The silicon tetrafluoride is further broken down by the hydrofluoric acid and ammonia to form an ammonium fluorosilicate ((NH4)2SiF6) byproduct:
SiF4+2HF+2NH3→(NH4)2SiF6
The ammonium fluorosilicate byproduct is removed from a processing chamber of the etch tool108. After removal of the ammonium fluorosilicate, a post-process temperature in a range of approximately 200 degrees Celsius to approximately 250 degrees Celsius is used to sublimate the ammonium fluorosilicate into constituents of silicon tetrafluoride, ammonia, and hydrofluoric acid.

As further shown inFIG.3H, the etch tool108may etch the liner320and the dielectric layer322such that a height323aof the STI regions206between the first subset of fin structures204a(e.g., for the PMOS nanostructure transistors) is greater relative to a height323bof the STI regions206between the second subset of fin structures204b(e.g., for the NMOS nanostructure transistors). This may occur due to the greater width the fin structures204brelative to the width of the fin structures204a, due to the different fin spacing between NMOS fin structures and PMOS fin structures, or a combination thereof. For example, the fin spacing (S1) between PMOS fin structures (P-P spacing) may be lesser relative to the fin spacing (S2) between a PMOS fin structure and an NMOS fin structure (P-N spacing or N-P spacing), and the fin spacing (S2) may be lesser relative to the fin spacing (S3) between NMOS fin structures (N-N spacing). In some implementations, the fin spacing (S1—P-P spacing) may be in a range of approximately 15 nanometers to approximately 20 nanometers, the fin spacing (S2—P-N spacing or N-P spacing) may be in a range of approximately 20 nanometers to approximately 25 nanometers, and the fin spacing (S3—N-N spacing) may be in a range of approximately 20 nanometers to approximately 30 nanometers. However, other values for these ranges are within the scope of the present disclosure.

Moreover, this results in a top surface of an STI region206between a fin structure204aand a fin structure204bbeing sloped or slanted (e.g., downward sloped from the fin structure204ato the fin structure204b, as shown in the example inFIG.3H). The etchants used to etch the liner320and the dielectric layer322first experience physisorption (e.g., a physical bonding to the liner320and the dielectric layer322) as a result of a Van der Waals force between the etchants and the surfaces of the liner320and the dielectric layer322. The etchants become trapped by dipole movement force. The etchants then attach to dangling bonds of the liner320and the dielectric layer322, and chemisorption begins. Here, the chemisorption of the etchant on the surface of the liner320and the dielectric layer322results in etching of the liner320and the dielectric layer322. The greater width of the trenches between the second subset of fin structures204bprovides a greater surface area for chemisorption to occur, which results in a greater etch rate between the second subset of fin structures204b. The greater etch rate results in the height of the STI regions206between the second subset of fin structures204bbeing lesser relative to the height of the STI regions206between the first subset of fin structures204a.

FIGS.3I and3Jrespectively illustrate a perspective view of the semiconductor device200and a cross-sectional view along the line A-A inFIG.3I. As shown inFIGS.3I and3J, a cladding layer324is formed over the fin structures204(e.g., over the top surfaces and over the sidewalls of the fin structures204) and over the STI regions206between the fin structures204. The cladding layer324includes silicon germanium (SiGe) or another material. The cladding layer324may be formed of the same material as the first layers304to enable the cladding sidewall layers (that are to be formed from the cladding layer324) and the first layers304to be removed in the same etch operation (a nanostructure release operation) so that a replacement gate (e.g., a gate structure212) may be formed in the areas occupied by the cladding sidewall layers and the first layers304. This enables the replacement gate to fully surround the nanostructure channels of the nanostructure transistors of the semiconductor device200.

The deposition tool102may deposit the cladding layer324. In some implementations, the deposition tool102deposits a seed layer (e.g., a silicon (Si) seed layer or another type of seed layer) over the fin structures204(e.g., over the top surfaces and over the sidewalls of the fin structures204) and over the STI regions206between the fin structures204. Then, the deposition tool102deposits silicon germanium on the seed layer to form the cladding layer324. The seed layer promotes growth and adhesion of the cladding layer324.

Deposition of the seed layer may include providing a silicon precursor to a processing chamber of the deposition tool102using a carrier gas such as nitrogen (N2) or hydrogen (H2), among other examples. In some implementations, a pre-clean operation is performed prior to deposition of the seed layer to reduce the formation of germanium oxide (GeOx). The silicon precursor may include disilane (Si2H6) or another silicon precursor. The use of disilane may enable formation of a seed layer to a thickness that is in a range of approximately 0.5 nanometers to approximately 1.5 nanometers. If the thickness is less than this range, a rate of formation of the cladding layer324may be reduced, resulting in a thickness of cladding layer324that is insufficient. If the thickness is greater than this range, a rate of formation of the cladding layer324may be increased to an uncontrollable amount, which may result in a wide dispersion of the thickness of the cladding layer324. However, other ranges and values for the thickness of the seed layer are within the scope of the present disclosure.

Deposition of the seed layer may be performed at a temperature in a range of approximately 450 degrees Celsius to approximately 500 degrees Celsius (or at a temperature in another range), at a pressure in a range of approximately 30 torr to approximately 100 torr (or at a pressure in another range), and/or for a time duration in a range of approximately 100 seconds to approximately 300 seconds (or for a time duration in another range), among other examples.

Deposition of the silicon germanium of the cladding layer324may include forming the cladding layer324to include an amorphous texture to promote conformal deposition of the cladding layer324. The silicon germanium may include a germanium content in a range of approximately 15% germanium to approximately 25% germanium. However, other values for the germanium content are within the scope of the present disclosure. Deposition of the cladding layer324may include providing a silicon precursor (e.g., disilane (Si2H6) or silicon tetrahydride (SiH4), among other examples) and a germanium precursor (e.g., germanium tetrahydride (GeH4) or another germanium precursor) to a processing chamber of the deposition tool102using a carrier gas such as nitrogen (N2) or hydrogen (H2), among other examples. Deposition of the cladding layer324may be performed at a temperature in a range of approximately 500 degrees Celsius to approximately 550 degrees Celsius (or at a temperature in another range) and/or at a pressure in a range of approximately 5 torr to approximately 20 torr (or at a pressure in another range).

As described in greater detail in connection withFIG.8and elsewhere herein, parameters associated with deposition of the seed layer and the cladding layer324may reduce overhang and/or protrusions of the silicon germanium from the hard mask layer (e.g., the hard mask layer including the oxide layer312and the nitride layer314). The parameters associated with the deposition of the seed layer and the cladding layer324may also enable selective etching of the cladding layer324to remove a footing formed near or above the STI region206.

FIGS.3K and3Lrespectively illustrate a perspective view of the semiconductor device200and a cross-sectional view along the line A-A inFIG.3K. As shown inFIGS.3K and3L, an etch back operation is performed to etch the cladding layer324to form cladding sidewall layers326. The etch tool108may etch the cladding layer324using a plasma-based dry etch technique or another etch technique. The etch tool108may perform the etch back operation to remove portions of the cladding layer324from the tops of the fin structures204and from the tops of the STI regions206. Removal of the cladding layer324from the tops of the STI regions206between the fin structures204ensures that the cladding sidewall layers326do not include a footing on the STI regions206between the fin structures204. This ensures that the cladding sidewall layers326do not include a footing under the hybrid fin structures that are to be formed over the STI regions206between the fin structures204.

In some implementations, the etch tool108uses a fluorine-based etchant to etch the cladding layer324. The fluorine-based etchant may include sulfur hexafluoride (SF6), fluoromethane (CH3F3), and/or another fluorine-based etchant. Other reactants and/or carriers such as methane (CH4), hydrogen (H2), argon (Ar), and/or helium (He) may be used in the etch back operation. In some implementations, the etch back operation is performed using a plasma bias in a range of approximately 500 volts to approximately 2000 volts. However, other values for the plasma bias are within the scope of the present disclosure. In some implementations, removing portions of the cladding layer324from the tops of the STI regions206includes performing a highly direction (e.g., anisotropic) etch to selectively remove (e.g., selectively etch) the cladding layer324on the tops of the STI regions206between the fin structures204, as described above.

As described in greater detail and in connection withFIGS.6,7A, and7B, and elsewhere herein, the cladding sidewall layers326may include asymmetric properties (e.g., different lengths, depths, and/or angles) relative to the STI region206, the fin structures204a, and/or the fin structures204b. The asymmetric properties provide sufficient depth of the metal gates for different types of fin structures (e.g., fin structures for p-type nanostructure transistors and fin structures for n-type nanostructure transistors) while reducing and/or minimizing footing of the cladding sidewall layers326(and thus, reducing and/or minimizing footing of the gate structures212that are formed in the areas that are occupied by the cladding sidewall layers326after removal of the cladding sidewall layers326) on the STI region206under hybrid fin structures of the nanostructure transistors of the semiconductor device200. The reduced and/or minimized footing further reduces a likelihood of electrical shorting. The asymmetric properties may result from forming the STI regions206to different heights, may result from forming sloped or asymmetric STI regions206, may result from forming the fin structures204to different widths for PMOS nanostructure transistors and NMOS nanostructures, and/or may result from forming the fin structures204to different fin spacings between the fin structures204, as described above.

FIGS.3M and3Nrespectively illustrate a perspective view of the semiconductor device200and a cross-sectional view along the line A-A inFIG.3M. As shown inFIGS.3M and3N, the hard mask layer (including the oxide layer312and the nitride layer314) and the capping layer310are removed to expose the hard mask layer308. In some implementations, the capping layer310, the oxide layer312, and the nitride layer314are removed using an etch operation (e.g., performed by the etch tool108), a planarization technique (e.g., performed by the planarization tool110), and/or another semiconductor processing technique.

FIGS.3O and3Prespectively illustrate a perspective view of the semiconductor device200and a cross-sectional view along the line A-A inFIG.3O. As shown inFIGS.3O and3P, a liner328and a dielectric layer330are formed above the semiconductor substrate202and interposing (e.g., in between) the fin structures204. The deposition tool102may deposit the liner328and the dielectric layer330over the semiconductor substrate202and between the cladding sidewall layers326in the trenches between the fin structures204. The deposition tool102may form the dielectric layer330such that a height of a top surface of the dielectric layer330and a height of a top surface of the hard mask layer308are approximately a same height.

Alternatively, the deposition tool102may form the dielectric layer330such that the height of the top surface of the dielectric layer330is greater relative to the height of the top surface of the hard mask layer308, as shown inFIGS.3O and3P. In this way, the trenches between the fin structures204are overfilled with the dielectric layer330to ensure the trenches are fully filled with the dielectric layer330. Subsequently, the planarization tool110may perform a planarization or polishing operation (e.g., a CMP operation) to planarize the dielectric layer330.

The deposition tool102may deposit the liner328using a conformal deposition technique. The deposition tool102may deposit the dielectric layer330using a CVD technique (e.g., a flowable CVD (FCVD) technique or another CVD technique), a PVD technique, an ALD technique, and/or another deposition technique. In some implementations, after deposition of the dielectric layer330, the semiconductor device200is annealed, for example, to increase the quality of the dielectric layer330.

The liner328and the dielectric layer330each includes a dielectric material such as a silicon oxide (SiOx), a silicon nitride (SixNy), a silicon oxynitride (SiON), a silicon carbon nitride (SiCN), fluoride-doped silicate glass (FSG), a low-k dielectric material, and/or another suitable insulating material. In some implementations, the dielectric layer330may include a multi-layer structure, for example, having one or more liner layers.

FIGS.3Q and3Rrespectively illustrate a perspective view of the semiconductor device200and a cross-sectional view along the line A-A inFIG.3Q. As shown inFIGS.3Q and3R, an etch back operation is performed to remove portions of the dielectric layer330. The etch tool108may etch the dielectric layer330in the etch back operation to reduce a height of a top surface of the dielectric layer330. In particular, the etch tool108etches the dielectric layer330such that the height of portions of the dielectric layer330between the fin structures204is less than the height of the top surface of the hard mask layer308. In some implementations, the etch tool108etches the dielectric layer330such that the height of portions of the dielectric layer330between the fin structures204is approximately equal to a height of top surfaces of the top-most of the second layers306of the portions316.

FIGS.3S and3Trespectively illustrate a perspective view of the semiconductor device200and a cross-sectional view along the line A-A inFIG.3S. As shown inFIGS.3S and3T, a high dielectric constant (high-k) layer332is deposited over the portions of the dielectric layer330between the fin structures204. The deposition tool102may deposit a high-k material such as a hafnium oxide (HfOx) and/or another high-k dielectric material to form the high-k layer332using a CVD technique, a PVD technique, an ALD technique, and/or another deposition technique. The combination of the portions of the dielectric layer330between the fin structures204and the high-k layer332between the fin structures204is referred to as a hybrid fin structure334(or dummy fin structure). The hybrid fin structure334, which may be located between the second layers306(e.g., nanostructutures) and the first layers304(e.g., sacrificial nanostructures) of the fin structures204, may comprise the dielectric layer330and the high-k dielectric layer332over the dielectric layer330. In some implementations, the planarization tool110may perform a planarization operation to planarize the high-k layer332such that a height of a top surface of the high-k layer332and the height of the hard mask layer308are approximately equal.

Subsequently, and as shown inFIGS.3S and3T, the hard mask layer308is removed. Removal of the hard mask layer308may include using an etch technique (e.g., a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique) or another removal technique.

FIG.3Uillustrates a perspective view of the semiconductor device200. As shown inFIG.3U, dummy gate structures336(also referred to as dummy gate stacks) are formed over the fin structures204and over the hybrid fin structures334. The dummy gate structures336are sacrificial structures that are to be replaced by replacement gate structures (or replacement gate stacks) at a subsequent processing stage for the semiconductor device200. Portions of the fin structures204underlying the dummy gate structures336may be referred to as channel regions. The dummy gate structures336may also define source/drain (S/D) regions of the fin structures204, such as the regions of the fin structures204adjacent and on opposing sides of the channel regions.

A dummy gate structure336may include a gate electrode layer338, a hard mask layer340over and/or on the gate electrode layer338, and spacer layers342on opposing sides of the gate electrode layer338and on opposing sides of the hard mask layer340. The dummy gate structures336may be formed on a gate dielectric layer344between the fin structures204and the dummy gate structures336, and between the hybrid fin structures334and the dummy gate structures336. The gate electrode layer338includes polycrystalline silicon (polysilicon or PO) or another material. The hard mask layer340includes one or more layers such as an oxide layer (e.g., a pad oxide layer that may include silicon dioxide (SiO2) or another material) and a nitride layer (e.g., a pad nitride layer that may include a silicon nitride such as Si3N4or another material) formed over the oxide layer. The spacer layers342include a silicon oxycarbide (SiOC), a nitrogen free SiOC, or another suitable material. The gate dielectric layer344may include a silicon oxide (e.g., SiOxsuch as SiO2), a silicon nitride (e.g., SixNysuch as Si3N4), a high-K dielectric material and/or another suitable material.

In some implementations, the gate dielectric layer344is conformally deposited on the semiconductor device200and then selectively removed from portions of the semiconductor device200(e.g., the source/drain areas). The gate electrode layer338is then deposited onto the remaining portions of the gate dielectric layer344. The hard mask layers340are then deposited onto the gate electrode layers338. The spacer layers342may be conformally deposited in a similar manner as the gate dielectric layer344. In some implementations, the spacer layers342include a plurality of types of spacer layers. For example, the spacer layers342may include a seal spacer layer that is formed on the sidewalls of the dummy gate structures336and a bulk spacer layer that is formed on the seal spacer layer. The seal spacer layer and the bulk spacer layer may be formed of similar materials or different materials. In some implementations, the bulk spacer layer is formed without plasma surface treatment that is used for the seal spacer layer. In some implementations, the bulk spacer layer is formed to a greater thickness relative to the thickness of the seal spacer layer.

FIG.3Ufurther illustrates reference cross-sections that are used in later figures, includingFIGS.4A-4D. Cross-section A-A is in an x-z plane (referred to as a y-cut) across the fin structures204and the hybrid fin structures334in source/drain areas of the semiconductor device200. Cross-section B-B is in a y-z plane (referred to as an x-cut) perpendicular to the cross-section A-A, and is across the dummy gate structures336in the source/drain areas of the semiconductor device200. Cross-section C-C is in the x-z plane parallel to the cross-section A-A and perpendicular to the cross-section B-B, and is along a dummy gate structures336. Subsequent figures refer to these reference cross-sections for clarity. In some figures, some reference numbers of components or features illustrated therein may be omitted to avoid obscuring other components or features for ease of depicting the figures.

As indicated above, the number and arrangement of operations and devices shown inFIGS.3A-3Uare provided as one or more examples. In practice, there may be additional operations and devices, fewer operations and devices, different operations and devices, or differently arranged operations and devices than those shown inFIGS.3A-3U.

FIGS.4A-4Dare diagrams of an example implementation400described herein. The example implementation400includes an example of forming source/drain regions in the source/drain areas of the semiconductor device200.FIGS.4A-4Dare illustrated from a plurality of perspectives illustrated inFIG.3U, including the perspective of the cross-sectional plane A-A inFIG.3U, the perspective of the cross-sectional plane B-B inFIG.3U, and the perspective of the cross-sectional plane C-C inFIG.3U. In some implementations, the operations described in connection with the example implementation400are performed after the operations described in connection withFIGS.3A-3U.

As shown inFIG.4A, the dummy gate structures336are formed above the fin structures204. As shown in the cross-sectional plane C-C inFIG.4A, portions of the gate dielectric layer344and portions of the gate electrode layers338are formed in recesses above the fin structures204that are formed as a result of the removal of the hard mask layer308. The formation of the dummy gate structures336is described in connection withFIG.3U.

As shown in the cross-sectional plane A-A and cross-sectional plane B-B inFIG.4B, source/drain recesses402are formed in the portions316of the fin structure204in an etch operation. The source/drain recesses402are formed to provide spaces in which source/drain regions210are to be formed on opposing sides of the dummy gate structures336. The etch operation may be performed by the etch tool108and may be referred to a strained source/drain (SSD) etch operation. In some implementations, the etch operation includes a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique.

As further shown in the cross-sectional plane A-A and cross-sectional plane B-B inFIG.4B, the source/drain recesses402may further be formed into the portions318of the fin structure204(e.g., into the mesa region of the fin structures204). In these implementations, the source/drain recesses402penetrate into a well portion (e.g., a p-well, an n-well) of the fin structure204. In implementations in which the semiconductor substrate202includes a silicon (Si) material having a (100) orientation, (111) faces are formed at bottoms of the source/drain recesses402, resulting in formation of a V-shape or a triangular shape cross section at the bottoms of the source/drain recesses402. In some implementations, a wet etching using tetramethylammonium hydroxide (TMAH) and/or a chemical dry etching using hydrochloric acid (HCl) are employed to form the V-shape profile.

As shown in the cross-sectional plane B-B and the cross-sectional plane C-C inFIG.4B, portions of the first layers304and portions of the second layers306of the layer stack302remain under the dummy gate structures336after the etch operation to form the source/drain recesses402. The portions of the second layers306under the dummy gate structures336form the channels208of the nanostructure transistors of the semiconductor device200.

As further shown in the cross-sectional plane B-B inFIG.4C, the deposition tool102forms inner spacer (InSP) layers404in cavities between the channels208prior to formation of the source/drain regions210in the source/drain recesses402. The inner spacer layers404are included to provide increased isolation between the gate structures212(e.g., the replacement gate structures) and the source/drain regions210that are to be formed in the source/drain recesses402for reduced parasitic capacitance. The inner spacer layers404include a silicon nitride (SixNy), a silicon oxide (SiOx), a silicon oxynitride (SiON), a silicon oxycarbide (SiOC), a silicon carbon nitride (SiCN), a silicon oxycarbonnitride (SiOCN), and/or another dielectric material. The inner spacer layers404and the spacer layers342may be formed of the same material or of different materials.

The inner spacer layers404may be formed by etching (e.g., by the etch tool108) the ends of the first layers304to form cavities between adjacent nanostructure channels208. The etching also results in removal of the remaining portions of the cladding sidewall layers326in the source/drain recesses402(e.g., because the cladding sidewall layers326and the first layers304are formed of the same material). The etch tool108may laterally etch (e.g., in a direction that is approximately parallel to a length of the first layers304) the first layers304in an etch operation, thereby forming the cavities (or recesses) between portions of the channels208. In implementations where the first layers304are silicon germanium (SiGe) and the second layers306are silicon (Si), the etch tool108may selectively etch the first layers304using a wet etchant such as, a mixed solution including hydrogen peroxide (H2O2), acetic acid (CH3COOH), and/or hydrogen fluoride (HF), followed by a cleaning with water (H2O). The mixed solution and the wafer may be provided into the source/drain recesses402to etch the first layers304from the source/drain recesses402. In some implementations, the etching by the mixed solution and cleaning by water is repeated approximately 10 times to approximately 20 times. The etching time by the mixed solution is in a range from about 1 minute to about 2 minutes in some implementations. The mixed solution may be used at a temperature in a range of approximately 60° Celsius to approximately 90° Celsius. However, other values for the parameters of the etch operation are within the scope of the present disclosure. The inner spacers layers404are then formed on the ends of the first layers304in the cavities. In some implementations, a conformal layer is deposited (e.g., by the deposition tool102) in the source/drain recesses402, and the etch tool108removes excess material of the conformal layer to form the inner spacer layers404.

As shown in the cross-sectional plane A-A and the cross-sectional plane B-B inFIG.4D, the source/drain recesses402are filled with one or more layers to form the source/drain regions210in the source/drain recesses402. For example, the deposition tool102may deposit a buffer layer406at the bottom of the source/drain recesses402, the deposition tool102may deposit the source/drain regions210on the buffer layer406, and the deposition tool102may deposit a capping layer408on the source/drain regions210. The buffer layer406may include silicon (Si), silicon doped with boron (SiB) or another dopant, and/or another material. The buffer layer406may be included to control the proximity and/or shape of the source/drain regions210.

The source/drain regions210may include one or more layers of epitaxially grown material. For example, the deposition tool102may epitaxially grow a first layer of the source/drain regions210(referred to as an L1) over the buffer layer406, and may epitaxially grow a second layer of the source/drain regions210(referred to as an L2, an L2-1, and/or an L2-2) over the first layer. The first layer may include a lightly doped silicon (e.g., doped with boron (B), phosphorous (P), and/or another dopant), and may be included as shielding layer to reduce short channel effects in the semiconductor device200and to reduce dopant extrusion into the channels208. The second layer may include a highly doped silicon or highly doped silicon germanium. The second layer may be included to provide a compressive stress in the source/drain regions210to reduce boron loss.

The capping layer408may include silicon, silicon germanium, doped silicon, doped silicon germanium, and/or another material. The capping layer408may be included to reduce dopant diffusion and to protect the source/drain regions210in subsequent semiconductor processing operations for the semiconductor device200prior to contact formation.

As indicated above, the number and arrangement of operations and devices shown inFIGS.4A-4Dare provided as one or more examples. In practice, there may be additional operations and devices, fewer operations and devices, different operations and devices, or differently arranged operations and devices than those shown inFIGS.4A-4D.

FIGS.5A-5Dare diagrams of an example implementation500described herein. The example implementation500includes an example of a replacement gate process (RPG) for replacing the dummy gate structures336with the gate structures212(e.g., the replacement gate structures) of the semiconductor device200.FIGS.5A-5Dare illustrated from a plurality of perspectives illustrated inFIG.3U, including the perspective of the cross-sectional plane A-A inFIG.3U, the perspective of the cross-sectional plane B-B inFIG.3U, and the perspective of the cross-sectional plane C-C inFIG.3U. In some implementations, the operations described in connection with the example implementation500are performed after the operations described in connection withFIGS.3A-3Uand/or after the operations described in connection withFIGS.4A-4D.

As shown in the cross-sectional plane A-A and the cross-sectional plane B-B inFIG.5A, the dielectric layer214is formed over the source/drain regions210. The dielectric layer214fills in areas between the dummy gate structures336, between the hybrid fin structures334, and over the source/drain regions210. The dielectric layer214is formed to reduce the likelihood of and/or prevent damage to the source/drain regions210during the replacement gate process. The dielectric layer214may be referred to as an interlayer dielectric (ILD) zero (ILD0) layer or another ILD layer.

In some implementations, a contact etch stop layer (CESL) is conformally deposited (e.g., by the deposition tool102) over the source/drain regions210, over the dummy gate structures336, and on the spacer layers342prior to formation of the dielectric layer214. The dielectric layer214is then formed on the CESL. The CESL may provide a mechanism to stop an etch process when forming contacts or vias for the source/drain regions210. The CESL may be formed of a dielectric material having a different etch selectivity from adjacent layers or components. The CESL may include or may be a nitrogen containing material, a silicon containing material, and/or a carbon containing material. Furthermore, the CESL may include or may be silicon nitride (SixNy), silicon carbon nitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon carbon oxide (SiCO), or a combination thereof, among other examples. The CESL may be deposited using a deposition process, such as ALD, CVD, or another deposition technique.

As shown in the cross-sectional plane B-B and the cross-sectional plane C-C inFIG.5B, the replacement gate operation is performed (e.g., by one or more of the semiconductor processing tools102-112) to remove the dummy gate structures336from the semiconductor device200. The removal of the dummy gate structures336leaves behind openings (or recesses) between the dielectric layer214over the source/drain regions210, and between the hybrid fin structures334over the fin structures204. The dummy gate structures336may be removed in one or more etch operations. Such etch operations may include a plasma etch technique, a wet chemical etch technique, and/or another type of etch technique.

As shown in the cross-sectional plane B-B and the cross-sectional plane C-C inFIG.5C, a nanostructure release operation is performed to remove the first layers304(e.g., the silicon germanium layers). This results in openings502between the channels208(e.g., the areas around the channels208). The nanostructure release operation may include the etch tool108performing an etch operation to remove the first layer304based on a difference in etch selectivity between the material of the first layers304and the material of the channels208, and between the material of the first layers304and the material of the inner spacer layers404. The inner spacer layers404may function as etch stop layers in the etch operation to protect the source/drain regions210from being etched. As further shown inFIG.5C, the cladding layers326are removed in the nanostructure release operation. This provides access to the areas around the nanostructure channels208, which enable replacement gate structures (e.g., the gate structures212) to be formed fully around the nanostructure channels208.

As shown in the cross-sectional plan B-B and the cross-sectional plane C-C inFIG.5D, the replacement gate operation continues where deposition tool102and/or the plating tool112forms the gate structures (e.g., replacement gate structures)212in the openings502between the source/drain regions210and between the hybrid fin structures334. In particular, the gate structures212fill the areas between and around the channels208that were previously occupied by the first layers304and the cladding sidewall layers326such that the gate structures212surround the channels208. The gate structures212may include metal gate structures. A conformal high-k dielectric liner504may be deposited onto the channels208and on sidewalls prior to formation of the gate structures212. The gate structures212may include additional layers such as an interfacial layer, a work function tuning layer, and/or a metal electrode structure, among other examples.

As further shown in the cross-sectional plane C-C inFIG.5D, the removal of the cladding layer324from the tops of the STI regions206to prevent the cladding sidewall layers326from including footings under the hybrid fin structure334between adjacent fin structures204enables the gate structures212to be formed such that the gate structure212does not include a footing under the hybrid fin structure334. In other words, since the gate structures212are formed in the areas that were previously occupied by the cladding sidewall layers326, the absence of a footing under the hybrid fin structure334for the cladding sidewall layers326also results in an absence of a footing under the hybrid fin structure334for the gate structures212. This reduces and/or prevents shorting between the gate structures212and the source/drain regions210under the hybrid fin structures212. Furthermore, and as shown in the cross-sectional plane C-C inFIG.5D, the hybrid fin structure334is between nanostructures (e.g., channels208) of adjacent structures204.

As indicated above, the number and arrangement of operations and devices shown inFIGS.5A-5Dare provided as one or more examples. In practice, there may be additional operations and devices, fewer operations and devices, different operations and devices, or differently arranged operations and devices than those shown inFIGS.5A-5D.

FIG.6is a diagram of an example implementation600described herein. The example implementation600includes a cladding sidewall layer configuration for the fin structure204a(e.g., a PMOS fin structure) and the fin structure204b(e.g., an NMOS fin structure). The fin structure204aand the fin structure204bcan be formed using a combination of one or more operations described in connection withFIGS.3A-3Uand/or elsewhere herein.

The example implementation600is illustrated from the perspective of the cross-sectional plane C-C inFIG.3U. As shown in the cross-sectional plane C-C inFIG.6, the fin structure204aand the fin structure204bare over the semiconductor substrate202. Furthermore, the fin structure204bis adjacent to the fin structure204a. The STI region206is between the fin structure204aand the fin structure204b.

The fin structure204aincludes the cladding sidewall layer326aalong a sidewall of the fin structure204a. The cladding sidewall layer326aincludes a bottom edge602aand faces the second fin structure204b.

The fin structure204bincludes the cladding sidewall layer326balong a sidewall of the fin structure204b. The cladding sidewall layer326bincludes the bottom edge602band faces the fin structure204a.

Note that the example implementation600illustrated inFIG.6an intermediate structure in the formation of the semiconductor device200. The cladding sidewall layers326aand326bare replaced with the gate structures212of the semiconductor device200in the final structure of the semiconductor device200. Accordingly, while the example implementation600is illustrated and described in connection with the cladding sidewall layers326aand326b, the dimensions and other properties described for the cladding sidewall layers326aand326bare the same or similar for the gate structures212that replace the cladding sidewall layers326aand326b. In other words, the dimensions and other properties of the sidewalls of the gate structures212can be considered to be the same or similar as the dimensions and other properties described for the cladding sidewall layers326aand326binFIG.6.

In some implementations, lengths associated with the cladding sidewall layer326band the cladding sidewall layer326aare asymmetric. For example, and as shown inFIG.6, the bottom edge602bis lower relative to the bottom edge602a. In combination with chemisorption and/or physisorption described in connection withFIG.3H, one or more processes described in connection withFIGS.3A-3J(e.g., etching of the dielectric layer322, deposition of the cladding sidewall layers326, or etching of the cladding sidewall layers326, among other examples) may be performed specifically to cause the bottom edge602bto be lower than the bottom edge602a.

In some implementations, a depth d of the bottom edge602bof the cladding sidewall layer326bis in a range of approximately 8 nanometers to approximately 15 nanometers below a top surface614of a mesa region of the semiconductor substrate202(e.g., top surfaces of the portions318of the fin structures204aand204b). Furthermore, the bottom edges602aand602bare located below the top surface614. If the depth610is less than this range, the cladding sidewall layer326bmay be over-etched and cause a length of the cladding sidewall layer326bto be shortened, which can result in insufficient coverage of the lower nanostructure channels of the semiconductor device200by a gate structure212that replaces the cladding sidewall layer326b. If the depth610is greater than this range, the cladding sidewall layer326bmay be under-etched and cause a footing to form over the STI region206, which increases a likelihood of electrical shorting because a gate structure212that replaces the cladding sidewall layer326bmay also have a footing under the hybrid fin structure334. However, other ranges and values for the depth610are within the scope of the present disclosure.

In some implementations, depth612of the bottom edge602aof the cladding sidewall layer326ais in a range of approximately 4 nanometers to approximately 6 nanometers below the top surface614of the region of the semiconductor substrate202. If the depth612is less than this range, the cladding sidewall layer326amay be over-etched and cause a length of the cladding sidewall layer326ato be shortened, which can result in insufficient coverage of the lower nanostructure channels of the semiconductor device200by a gate structure212that replaces the cladding sidewall layer326a. If the depth612is greater than this range, the cladding sidewall layer326amay be under-etched and cause a footing to form over the STI region206, which increases a likelihood of electrical shorting because a gate structure212that replaces the cladding sidewall layer326bmay also have a footing under the hybrid fin structure334. However, other ranges and values for the depth612are within the scope of the present disclosure.

In some implementations, a ratio of the depth610of the bottom edge602bto the depth612of the bottom edge602ais in a range of approximately 4:3 to approximately 4:1. If the ratio is less than this range, one or more of the cladding sidewall layers326aor326bmay be over-etched. If the ratio is greater than this range, one or more of the cladding sidewall layers326aor326bmay be under-etched and cause a footing to form over the STI region206. However, other ranges and values for the ratio are within the scope of the present disclosure.

In some implementations, and as shown, the fin structure204aincludes a portion316aof a layer stack (e.g., the layer stack302). In some implementations, and as shown, the fin structure204bincludes the portion316bof the layer stack. The portion316aof the layer stack includes a plurality of alternating layers (e.g., the plurality of the first layers304alternating with the plurality of the second layers306). The portion316bof the layer stack also includes the plurality of alternating layers (e.g., the plurality of the first layers304alternating with the plurality of the second layers306). As indicated above,FIG.6is provided as an example. Other examples may differ from what is described with regard toFIG.6.

FIGS.7A and7Bare diagrams of an example implementation700described herein. The example implementation700includes a plurality of examples of different cladding sidewall layer configurations (e.g., different lengths, different angles, different bottom edge depths) for different configurations of fin structures204. The example implementation700is illustrated from the perspective of the cross-sectional plane C-C ofFIG.3U. The example implementation700includes the fin structure204a1, the fin structure204a2, the fin structure204b1, and the fin structure204b2. The fin structure204a1, the fin structure204a2, the fin structure204b1, and the fin structure204b2may be formed over the semiconductor substrate202using a combination of one or more operations described in connection withFIGS.3A-3Uand elsewhere herein.

Turning toFIG.7A, in some implementations, the fin structure204a1includes a PMOS fin structure. The fin structure204a1includes the cladding sidewall layer326calong a sidewall of the fin structure204a1. The cladding sidewall layer326cfaces the dielectric layer330abetween the fin structure204a1and the fin structure204a2(e.g., another PMOS fin structure). The cladding sidewall layer326cincludes the bottom edge604c.

The fin structure204a1also includes the cladding sidewall layer326dalong an opposing sidewall. The cladding sidewall layer326dfaces the dielectric layer330bbetween the fin structure204a1and the fin structure204b1(e.g., an NMOS fin structure). The cladding sidewall layer326dincludes the bottom edge604d. As shown inFIG.7A, a vertical location of the bottom edge604dis lower than a vertical location of the bottom edge604c.

In some implementations, lengths and/or angles associated with the cladding sidewall layer326cand the cladding sidewall layer326dare asymmetric. For example, a length702of the cladding sidewall layer326cmay be less relative to a length704of the cladding sidewall layer326din a range from approximately 2 nanometers to approximately 5 nanometers. If the difference between the lengths702and704is less than this range, the cladding sidewall layer326may be over-etched. If the difference between the lengths702and704is greater than this range, a footing may remain over the STI region206aand/or the STI region206b. However, other ranges and values for the difference between the length702and the length704are within the scope of the present disclosure.

As another example, an angle706between a sidewall of the cladding sidewall layer326cand the bottom edge604cof the cladding sidewall layer326cmay be greater relative to an angle708between a sidewall of the cladding sidewall layer326dand the bottom edge604dof the cladding sidewall layer326d. The angle706may be greater than the angle708in a range from approximately 6 degrees to 15 degrees. If the difference between the angles706and708is less than this range, the STI region206aand/or the STI region206bmay be under-etched. If difference between the angles706and708is greater than this range, STI region206aand/or STI region206bmay be over-etched. However, other ranges and values for the difference between the angles706and708are within the scope of the present disclosure.

Note that the example illustrated inFIG.7Ais an intermediate structure in the formation of the semiconductor device200. The cladding sidewall layers326cand326dare replaced with the gate structures212of the semiconductor device200in the final structure of the semiconductor device200. Accordingly, while the example inFIG.7Ais illustrated and described in connection with the cladding sidewall layers326cand326d, the dimensions and other properties described for the cladding sidewall layers326cand326care the same or similar for the gate structures212(e.g., the sidewalls of the gate structures212) that replace the cladding sidewall layers326cand326d. In other words, the dimensions and other properties of the sidewalls of the gate structures212can be considered to be the same or similar as the dimensions and other properties described for the cladding sidewall layers326cand326dinFIG.7A.

Turning toFIG.7B, in some implementations, the fin structure204b1includes an NMOS fin structure. The fin structure204b1includes the cladding sidewall layer326ealong a sidewall of the fin structure204b1. The cladding sidewall layer326ealso includes the bottom edge604e.

The fin structure204b1also includes the cladding sidewall layer326falong an opposing sidewall. The cladding sidewall layer326ffaces the dielectric layer330bbetween the fin structure204b1and the fin structure204a1(e.g., a PMOS fin). The cladding sidewall layer326falso includes the bottom edge604f. A vertical location of the bottom edge604fis lower than a vertical location of the bottom edge604e.

In some implementations, lengths and/or angles associated with the cladding sidewall layer326eand the cladding sidewall layer326fare asymmetric. For example, a length710of the cladding sidewall layer326emay be less relative to a length712of the cladding sidewall layer326fin a range from approximately 2 nanometers to approximately 5 nanometers. If the difference between the lengths710and712is less than this range, the cladding sidewall layer326may be over-etched to cause a length of the cladding sidewall layer326eand/or the cladding sidewall layer326fto be shortened. If the difference between the lengths710and712is greater than this range, the cladding sidewall layer326may be under-etched. However, other ranges and values for difference between the length710and the length712are within the scope of the present disclosure.

Note that the example illustrated inFIG.7Bis an intermediate structure in the formation of the semiconductor device200. The cladding sidewall layers326eand326fare replaced with the gate structures212of the semiconductor device200in the final structure of the semiconductor device200. Accordingly, while the example inFIG.7Bis illustrated and described in connection with the cladding sidewall layers326eand326f, the dimensions and other properties described for the cladding sidewall layers326eand326fare the same or similar for the gate structures212(e.g., the sidewalls of the gate structures212) that replace the cladding sidewall layers326eand326f. In other words, the dimensions and other properties of the sidewalls of the gate structures212can be considered to be the same or similar as the dimensions and other properties described for the cladding sidewall layers326eand326finFIG.7B.

As indicated above,FIGS.7A and7Bare provided as examples. Other examples may differ from what is described with regard toFIGS.7A and7B.

FIG.8is a diagram of an example implementation800described herein. The example implementation800is illustrated from the perspective of the cross-sectional plane A-A ofFIG.3J. In the implementation800, the fin structure204includes the cladding layer324. The fin structure204includes the plurality of first layers304, the plurality of channels208, and the hard mask layer308. The fin structure204also includes a base region804(e.g., region at a base of the fin structure204that is near or over the STI region206). The fin structure204is shown after deposition of the cladding layer324and prior to etching the cladding layer324to form the cladding sidewall layers326. The fin structure204also includes an oxide layer806and a seed layer808between sidewalls of the fin structure204and the cladding layer324. In some implementations, the oxide layer806includes a native oxide growth that is approximately 1 nanometer thick. However, the oxide layer806may include a native oxide growth of another thickness.

As shown in the magnified view of example810, the seed layer808may have a thickness812. The seed layer808may be deposited using one or more operations or parameters as described in connection withFIGS.3I and3J. For example, operations may include depositing the seed layer808using a nitrogen (N2) carrier gas. Additionally, or alternatively, operations may include using disilane (Si2H6) as a silicon precursor. Using a disilane silicon precursor may cause the thickness812of the seed layer808on sides of the plurality second layers306(e.g., S1 layers) to be thinner relative to the thickness812on the sides of the plurality of first layers304(e.g., SiGe layers). As described in connection withFIGS.3I and3J, the thickness812may range from approximately 0.5 nanometers to approximately 1.5 nanometers. This may, as shown in example802, cause a “wavy” profile of the cladding layer324.

In some implementations, and as described in connection withFIGS.3I and3J, the seed layer808is deposited at a first pressure (e.g., approximately 30 torr to approximately 100 torr) and the cladding layer324is deposited at a second pressure (e.g., approximately 5 torr to approximately 20 torr) that is lesser relative to the first pressure. However, the cladding layer324may include other combinations of materials and/or thicknesses. This difference in pressure may reduce a likelihood of forming protrusions of the cladding layer324(e.g., an overhang protruding from the hard mask layer308or a footing protruding from the base region804, among other examples). In some implementations, the cladding layer324may include an amorphous silicon germanium (a-SiGe) material that is approximately 10 nanometers thick.

FIG.9a diagram of an example implementation900described herein. The example implementation900shows the semiconductor device200after the replacement gate operation as described in connection withFIG.5Dand elsewhere herein. The example implementation900is illustrated from the perspective of the cross-sectional plane C-C inFIG.3U.

As shown in the cross-sectional plane C-C inFIG.9, The semiconductor device200may include a plurality of nanostructures (e.g., a plurality of the channels208) arranged along a direction perpendicular to a substrate. The semiconductor device200includes the gate structure212wrapping around each of the plurality of nanostructures.

As shown, the gate structure212includes a first sidewall902aalong a first side of the plurality of nanostructures. In some implementations, the first sidewall902aincludes a first bottom edge a first vertical location (e.g., a first bottom edge at a first depth904). The gate structure further includes a second sidewall902balong a second side of the plurality of nanostructures opposing the first side. In some implementations, the second sidewall902bincludes a second bottom edge at a second vertical location (e.g., a second bottom edge at a second depth906). In some implementations, and as shown inFIG.9, the second vertical location is lower relative to the first vertical location of the first bottom edge.

In some implementations, sidewalls of the gate structure212(e.g., the first sidewall902aand/or the second sidewall902b) may include one or more dimensional properties corresponding to values and ranges of a previously formed cladding sidewall layer (e.g., one or more of the cladding sidewall layers326a-326f). As an example, bottom edges of sidewalls902aand/or902bmay include depths corresponding to values and ranges for the depths610and/or612. Additionally, or alternatively, lengths of the sidewalls902aand/or902bmay be asymmetric and include lengths corresponding to values and ranges for the lengths702,704,710, or712as described herein. Additionally, or alternatively, bottom edges of the sidewalls902aand/or902bmay include angles corresponding to values and ranges for the angles706and/or708as described herein.

FIG.10is a diagram of example components of a device1000. In some implementations, one or more of the semiconductor processing devices102-112and/or the wafer/die transport tool114may include one or more devices1000and/or one or more components of device1000. As shown inFIG.10, device1000may include a bus1010, a processor1020, a memory1030, an input component1040, an output component1050, and a communication component1060.

Bus1010includes one or more components that enable wired and/or wireless communication among the components of device1000. Bus1010may couple together two or more components ofFIG.10, such as via operative coupling, communicative coupling, electronic coupling, and/or electric coupling. Processor1020includes a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field-programmable gate array, an application-specific integrated circuit, and/or another type of processing component. Processor1020is implemented in hardware, firmware, or a combination of hardware and software. In some implementations, processor1020includes one or more processors capable of being programmed to perform one or more operations or processes described elsewhere herein.

Memory1030includes volatile and/or nonvolatile memory. For example, memory1030may include random access memory (RAM), read only memory (ROM), a hard disk drive, and/or another type of memory (e.g., a flash memory, a magnetic memory, and/or an optical memory). Memory1030may include internal memory (e.g., RAM, ROM, or a hard disk drive) and/or removable memory (e.g., removable via a universal serial bus connection). Memory1030may be a non-transitory computer-readable medium. Memory1030stores information, instructions, and/or software (e.g., one or more software applications) related to the operation of device1000. In some implementations, memory1030includes one or more memories that are coupled to one or more processors (e.g., processor1020), such as via bus1010.

Input component1040enables device1000to receive input, such as user input and/or sensed input. For example, input component1040may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, an accelerometer, a gyroscope, and/or an actuator. Output component1050enables device1000to provide output, such as via a display, a speaker, and/or a light-emitting diode. Communication component1060enables device1000to communicate with other devices via a wired connection and/or a wireless connection. For example, communication component1060may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and/or an antenna.

Device1000may perform one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory1030) may store a set of instructions (e.g., one or more instructions or code) for execution by processor1020. Processor1020may execute the set of instructions to perform one or more operations or processes described herein. In some implementations, execution of the set of instructions, by one or more processors1020, causes the one or more processors1020and/or the device1000to perform one or more operations or processes described herein. In some implementations, hardwired circuitry is used instead of or in combination with the instructions to perform one or more operations or processes described herein. Additionally, or alternatively, processor1020may be configured to perform one or more operations or processes described herein. Thus, implementations described herein are not limited to any specific combination of hardware circuitry and software.

The number and arrangement of components shown inFIG.1000are provided as an example. Device1000may include additional components, fewer components, different components, or differently arranged components than those shown inFIG.10. Additionally, or alternatively, a set of components (e.g., one or more components) of device1000may perform one or more functions described as being performed by another set of components of device1000.

FIG.11is a flowchart of an example process1100associated with forming a semiconductor device. In some implementations, one or more process blocks ofFIG.11are performed by one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tools102-112). Additionally, or alternatively, one or more process blocks ofFIG.11may be performed by one or more components of device1000, such as processor1020, memory1030, input component1040, output component1050, and/or communication component1060.

As shown inFIG.11, process1100may include forming a dielectric layer between a first fin structure that is above a semiconductor substrate and a second fin structure that is above the semiconductor substrate and is adjacent to the first fin structure (block1110). For example, one or more of the semiconductor processing tools102-112may form a dielectric layer322between a first fin structure204athat is above a semiconductor substrate and a second fin structure204bthat is above the semiconductor substrate and is adjacent to the first fin structure, as described above.

As further shown inFIG.11, process1100may include removing portions of the dielectric layer to form an STI region between the first fin structure and the second fin structure and to form a recess above the STI region (block1120). For example, one or more of the semiconductor processing tools102-112may remove portions of the dielectric layer322to form an STI region206between the first fin structure and the second fin structure and to form a recess above the STI region, as described above.

As further shown inFIG.11, process1100may include forming, in the recess, a cladding layer over a first sidewall of the first fin structure, over a second sidewall of the second fin structure, and over a top surface of the STI region (block1130). For example, one or more of the semiconductor processing tools102-112may form, in the recess, a cladding layer324over a first sidewall of the first fin structure, over a second sidewall of the second fin structure, and over a top surface of the STI region206, as described above.

As further shown inFIG.11, process1100may include removing the cladding layer from the top surface of the STI region to leave a first cladding sidewall layer along the first sidewall and a second cladding sidewall layer along the second sidewall (block1140). For example, one or more of the semiconductor processing tools102-112may remove the cladding layer324from the top surface of the STI region206to leave a first cladding sidewall layer326aalong the first sidewall and a second cladding sidewall layer326balong the second sidewall, as described above. In some implementations, the first cladding sidewall layer and the second cladding sidewall layer include respective lengths that are asymmetric.

In a first implementation, process1100includes forming a seed layer808over the first sidewall and over the second sidewall prior to forming the cladding layer, and forming the cladding layer324on the seed layer808.

In a second implementation, alone or in combination with the first implementation, forming the seed layer808includes forming the seed layer808using a chemical vapor deposition process in which a vapor mixture, including disilane (Si2H6), is used to deposit the seed layer808.

In a third implementation, alone or in combination with one or more of the first and second implementations, forming the seed layer808includes forming the seed layer808at a first pressure, and forming the cladding layer at a second pressure. In some implementations, the second pressure is lesser relative to the first pressure.

In a fourth implementation, alone or in combination with one or more of the first through third implementations, forming the seed layer808includes forming the seed layer808to a thickness812in a range from approximately 0.5 nanometers to approximately 1.5 nanometers.

In a fifth implementation, alone or in combination with one or more of the first through fourth implementations, forming the seed layer808includes forming the seed layer808to a first thickness812on sides of a plurality of first layers304included in the first fin structure204aand the second fin structure204b, and forming the seed layer808to a second thickness812on sides of a plurality of second layers306included in the first fin structure204aand the second fin structure204b. In some implementations, the second thickness812is lesser relative to the first thickness812.

In a sixth implementation, alone or in combination with one or more of the first through fifth implementations, process1100includes forming a plurality of nanostructures (e.g., the second layers306) and a plurality of sacrificial nanostructures (e.g., the first layers304) between the plurality of nanostructures, removing the plurality of sacrificial nanostructures, the first cladding sidewall layer326a, and the second cladding sidewall layer326b, and forming, after removing the plurality of sacrificial nanostructures, the first cladding sidewall layer326a, and the second cladding sidewall layer326b, a gate structure212that wraps around each of the plurality of nanostructures.

AlthoughFIG.11shows example blocks of process1100, in some implementations, process1100includes additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted inFIG.11. Additionally, or alternatively, two or more of the blocks of process1100may be performed in parallel.

In this way, a cladding sidewall layer footing is removed prior to formation of a hybrid fin structure. Removal of the cladding sidewall layer footing prevents a metal gate footing from forming under the hybrid fin structure when the cladding sidewall layer is removed to enable the metal gate to be formed around the nanostructure channels of a nanostructure transistor. As described herein, cladding sidewall layers can be formed in an asymmetric manner to include different lengths and/or angles, among other examples. The asymmetric cladding sidewall layers enable metal gate structures to be formed for p-type and n-type nanostructure transistors while preventing metal gate footings from forming under hybrid fin structures for p-type and n-type nanostructure transistors. This may reduce a likelihood of short channel effects and leakage within the nanostructure transistors yield of nanostructure transistors formed on a semiconductor substrate.

As described in greater detail above, some implementations described herein provide a method. The method includes forming a dielectric layer between a first fin structure that is above a semiconductor substrate and a second fin structure that is above the semiconductor substrate and is adjacent to the first fin structure. The method includes removing portions of the dielectric layer to form an STI region between the first fin structure and the second fin structure and to form a recess above the STI region. The method includes forming, in the recess, a cladding layer over a first sidewall of the first fin structure, over a second sidewall of the second fin structure, and over a top surface of the STI region. The method includes removing the cladding layer from the top surface of the STI region to leave a first cladding sidewall layer along the first sidewall and a second cladding sidewall layer along the second sidewall. In some implementations, the first cladding sidewall layer and the second cladding sidewall layer include respective lengths that are asymmetric.

As described in greater detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a first plurality of nanostructures over a semiconductor substrate. The semiconductor device includes a second plurality of nanostructures over the semiconductor substrate. In some implementations, the first and second plurality of nanostructures are arranged along a direction perpendicular to the semiconductor substrate. The semiconductor device includes a first gate structure wrapping around each of the first plurality of nanostructures, including a first sidewall along the direction. The semiconductor device includes a second gate structure wrapping around each of the second plurality of nanostructures, including a second sidewall along the direction. In some implementations, a first bottom edge of the first sidewall is lower relative to a second bottom edge of the second sidewall.

As described in greater detail above, some implementations described herein provide a semiconductor device. The semiconductor device includes a plurality of nanostructures over a semiconductor substrate. In some implementations, the plurality of nanostructures are arranged along a direction perpendicular to the semiconductor substrate. The semiconductor device includes a gate structure wrapping around each of the plurality of nano structures. The gate structure includes a first sidewall along a first side of the plurality of nanostructures. In some implementations, the first sidewall includes a first bottom edge at a first vertical location. The semiconductor device includes a second sidewall along a second side of the plurality of nanostructures opposing the first side. In some implementations, the second sidewall includes a second bottom edge at a second vertical location that is lower relative to the first vertical location of the first bottom edge.