Semiconductor device

A semiconductor device includes a first power supply which is disposed in a first direction, a first pad array which is disposed in the first direction, adjacent to the first power supply line, a second power supply line extending in the first direction, a first buffer circuit which is disposed between pads included in the first pad array, a second pad array which is disposed in the first direction, a third power supply line extending along the second pad array such that the second pad array is interposed between the second power supply line and the third power supply line, and a second buffer circuit which is disposed between pads included in the second pad array, and which is operated by a voltage between the second and third power supply lines.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and relates, for example, to layouts of pads, power supply lines and buffer circuits in a semiconductor chip.

2. Description of the Related Art

Normally, a semiconductor chip is provided with pads for input/output of signals. In a conventionally widely adopted pad layout, pad arrays are disposed along mutually opposed two sides (or four sides) of the semiconductor chip. However, for example, in a case where a memory cell array and a peripheral circuit thereof are formed on a semiconductor chip, the length of signal wiring lines for connecting a pad array, which is disposed adjacent to the memory cell array, and the peripheral circuit increases. As a result, a problem arises that the wiring resistance and wiring capacitance increase and a signal delay occurs.

Buffer circuits, such as input buffers and output buffers, are provided adjacent to the respective pad arrays. Power supply lines for supplying power to the buffer circuits are needed, leading to an increase in pattern occupation area. In particular, with recent increases in integration density and enhancement in function of semiconductor devices, there is a tendency that the area of an external connection region (pad arrays, power supply lines and buffer circuits), which occupies the surface of the semiconductor chip, increases.

In order to cope with an increase in number of pads, Patent Document 1, for instance, discloses an example of a pad layout and a lead layout, which is adaptive to reduction in size of the semiconductor chip and an increase in number of pins and a decrease in pitch of a package. However, no consideration is given to the length of signal wiring lines and the layout of power supply lines and buffer circuits. The prior art is not satisfactory from the standpoint of suppression of signal delay and reduction in pattern occupation area of the external connection region.

BRIEF SUMMARY OF THE INVENTION

The present invention provides a semiconductor device which can decrease the length of signal wiring to reduce signal delay, and can decrease the pattern occupation area of an external connection region.

According to an aspect of the present invention, there is provided a semiconductor device comprising: a first power supply line extending in one direction along one side of a semiconductor chip; a first pad array which is disposed in the first direction, adjacent to the first power supply line; a second power supply line extending in the first direction along the first pad array such that the first pad array is interposed between the first power supply line and the second power supply line; a first buffer circuit which is disposed between pads included in the first pad array, and which is operated by a voltage between the first and second power supply lines; a second pad array which is disposed in the first direction, adjacent to the second power supply line; a third power supply line extending along the second pad array such that the second pad array is interposed between the second power supply line and the third power supply line; and a second buffer circuit which is disposed between pads included in the second pad array, and which is operated by a voltage between the second and third power supply lines.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a first power supply line extending in one direction along one side of a semiconductor chip; a first pad array which is disposed in the first direction, adjacent to the first power supply line; a second power supply line extending in the first direction along the first pad array such that the first pad array is interposed between the first power supply line and the second power supply line; first buffer circuits which are disposed between a pad included in the first pad array and the first power supply line and between the pad included in the first pad array and the second power supply line, and which are operated by a voltage between the first and second power supply lines; a second pad array which is disposed in the first direction, adjacent to the second power supply line; a third power supply line extending along the second pad array such that the second pad array is interposed between the second power supply line and the third power supply line; and second buffer circuits which are disposed between a pad included in the second pad array and the second power supply line and between the pad included in the second pad array and the third power supply line, and which are operated by a voltage between the second and third power supply lines.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention will now be described with reference to the accompanying drawings. In the description below, common parts are designated by like reference numerals throughout the drawings.

First Embodiment

To begin with, a semiconductor device according to a first embodiment of the invention is described with reference toFIG. 1andFIG. 2.FIG. 1is a plan view that schematically shows the layout of a semiconductor memory chip.

As shown in the Figures, a semiconductor chip11includes cell arrays12-1and12-2, a peripheral circuit13and an external connection region14.

The external connection region14is disposed in the vicinity of the peripheral circuit13along one side of the chip11. In the external connection region14, there are arranged first to third power supply lines23,22,21which extend in a first direction along one side of the chip11, first and second pad arrays26and25, and first and second buffer circuits. A power supply voltage VCC (or power supply voltage VCCQ) is applied to the power supply lines23and21, and a power supply voltage VSS is applied to the power supply line22. The pad array26is disposed between the power supply lines23and22, and the pad array25is disposed between the power supply lines22and21. The pad array26comprises a plurality of pads26-1to26-7(seven pads in this example). Buffer circuits are provided in non-occupied regions between the pads26-1to26-7, or in regions between the pads26-1to26-7and the power supply lines23and22. The pad array26is used for input, output or input/output of data.

The pad array25comprises a plurality of pads25-1to25-6(six pads in this example). Buffer circuits are provided in non-occupied regions between the pads25-1to25-6, or in regions between the pads25-1to25-6and the power supply lines22and21. The pad array25is used for input, output or input/output of control signals. The pads25-1to25-6of the pad array25are arranged in the first direction with a displacement of about ½ pitch, relative to the pads26-1to26-7of the pad array26. Thus, the pads26-1to26-7and the pads25-1to25-6of the pad arrays26and25are arranged in a staggered fashion.

FIG. 2is a view for describing in detail an example of the pattern layout of the external connection region14(pads, power supply lines and buffer circuits).FIG. 2is a plan view showing, in enlarged scale, a part boxed by a broken line28inFIG. 1.

As shown inFIG. 2, buffer circuits are provided in non-occupied regions between the pads of the pad arrays26and25and in regions between the pads and the power supply lines. In this example, input buffers and output buffers are connected to the associated pads.

An input buffer32-1is disposed between the pads26-1and26-2, and is operated by a voltage between the power supply lines23and22. The input buffer32-1is composed of an NMOS transistor N3and a PMOS transistor P3. These transistors N3and P3have gates connected to the pad25-1and drains connected to the peripheral circuit13. A signal that is input to the pad25-1is supplied to the peripheral circuit13via the input buffer32-1.

The pad25-1is used, for example, for input of a control signal. The input control signal is supplied to the peripheral circuit13via the input buffer32-1.

An output buffer31-1is composed of a PMOS transistor P2, which is disposed between the pad26-1and the power supply line23, and an NMOS transistor N2which is disposed between the pad26-1and the power supply line22. The transistors P2and N2are disposed to be opposed to each other so as to sandwich the pad25-1in a second direction (crossing the first direction). The transistors P2and N2have gates connected to the peripheral circuit13and drains commonly connected to the pad25-1.

An input buffer32-2is disposed on a non-occupied region on the left side of the pad25-1, and is operated by a voltage between the power supply lines21and22. The input buffer32-2is composed of an NMOS transistor N1and a PMOS transistor P1. These transistors N1and P1have gates connected to the pad26-1and drains commonly connected to the peripheral circuit13. A signal that is input to the pad26-1is supplied to the peripheral circuit13via the input buffer32-2.

An output buffer31-2is composed of a PMOS transistor P2, which is disposed between the pad26-1and the power supply line23, and an NMOS transistor N2which is disposed between the pad26-1and the power supply line22. The transistors P2and N2are disposed to be opposed to each other so as to sandwich the pad26-1in the second direction. The transistors P2and N2have gates connected to the peripheral circuit13and drains commonly connected to the pad26-1.

The pad26-1is used, for example, for input/output of data. The input data is supplied to the peripheral circuit13via the input buffer32-2. Data, which is transferred from the peripheral circuit13, is output from the pad26-1via the output buffer31-2.

Similarly, an input buffer32-3is disposed on a non-occupied region on the right side of the pad25-1, and is operated by a voltage between the power supply lines21and22. The input buffer32-3is composed of an NMOS transistor N4and a PMOS transistor P4. These transistors N4and P4have gates connected to the pad26-2and drains commonly connected to the peripheral circuit13. A signal that is input to the pad26-2is supplied to the peripheral circuit13via the input buffer32-3.

An output buffer31-2is composed of a PMOS transistor P5, which is disposed between the pad26-2and the power supply line23, and an NMOS transistor N5which is disposed between the pad26-2and the power supply line22. The transistors P5and N5are disposed to be opposed to each other so as to sandwich the pad26-2in the second direction. The transistors P5and N5have gates connected to the peripheral circuit13and drains commonly connected to the pad26-2.

The pad26-2is used, for example, for input/output of data. The input data is supplied to the peripheral circuit13via the input buffer32-3. Data, which is transferred from the peripheral circuit13, is output from the pad26-2via the output buffer31-3.

It is possible that the gates of the transistors N2, N4, N6, P2, P4and P6may be individually supplied with voltages and be independently controlled.

As has been described above, in the semiconductor device according to the present embodiment, the pad arrays26and25are provided in two rows in the same direction in the vicinity of the peripheral circuit13. Thus, wiring lengths L1and L2between the pads of the pad arrays26and25and the peripheral circuit13can be reduced. Therefore, the wiring resistance and wiring capacitance can be reduced, and the signal delay can be decreased. This is advantageous for high-speed operations. In particular, in many cases, signals with relatively unstable voltages are used in a first-stage input circuit. Therefore, the instability in potential due to an increase in wiring length can be reduced, and the reliability can be enhanced.

In addition, the two-row pad arrays are arranged in the first direction along one side of the chip, and the power supply line22, which is disposed between the pad arrays, is shared by the input buffers32-1to32-3and the output buffers31-1and31-2. Therefore, compared to the case in which pad arrays are provided along two sides of the chip, the area in the second direction can be reduced, and the pattern occupation area of the external connection region can be decreased.

Further, the source regions of the transistors N1and N2and the source regions of the transistors N4and N5are shared, respectively, by the paired two transistors, and are commonly connected to the power supply line22. Thus, the area in the second direction can be reduced, and microfabrication can be achieved.

The PMOS transistors P2and P5and the NMOS transistors N2and N5, which constitute the output buffers31-1and31-2, are arranged to be opposed in the second direction so as to sandwich the pads26-1and26-2. Thus, a distance can be secured between the transistor P2, P5and the transistor N2, N5. Therefore, switching of parasitic thyristors, which are formed of parasitic PNP and NPN bipolar transistors, can be prevented, and so-called latch-up can be prevented. Hence, the reliability can be enhanced. The PMOS transistors P1, P3and P4and the NMOS transistors N1, N3and N4, which constitute the input buffers32-1to32-3, are arranged to be opposed in the second direction on the non-occupied regions of the pads25-1,26-1and26-2. Thus, in the non-occupied regions, a distance can be secured between the transistor P1, P3, P4and the transistor N1, N3and N4. Therefore, latch-up can similarly be prevented, and the reliability can be enhanced. Moreover, since the non-occupied regions can be utilized, the area in the first direction can be reduced.

In the case where the power supply voltages VCC and VCCQ are equal (e.g. 3.3 V), the voltage VCCQ is, for example, a power supply voltage for I/O pads. In this case, the voltage VCCQ tends to be easily mixed with external noise and is unstable. Thus, the voltage VCCQ may be used separately from the power supply voltage VCC. Besides, in the case where the voltages VCC and VCCQ are different (e.g. voltage VCC=about 3.3 V; the voltage VCCQ=about 1.8 V), the voltages may be used in order to distinguish their values.

Next, a semiconductor device according to Modification 1 of the invention is described with reference toFIG. 3. In the description below, a description of parts common to those of the first embodiment is omitted.FIG. 3is a view for describing the semiconductor device according to Modification 1.FIG. 3is a plan view that schematically shows the part boxed by the broken line28inFIG. 1. In this Modification, compared to the semiconductor device according to the first embodiment, the polarities of the transistors N1to N5and P1to P5, which constitute the input and output buffers, are reversed.

As shown inFIG. 3, a power supply voltage VSS is applied to the power supply lines21and23, and a power supply voltage VCC or VCCQ is applied to the power supply line22. Further, compared to the semiconductor device according to the first embodiment, the transistors N1to N5and P1to P5are reversely positioned in the second direction.

The sources of the PMOS transistors P1to P5are commonly connected to the power supply line22(VCC or VCCQ).

According to the above-described structure, the same advantages as with the first embodiment can be obtained.

Further, where necessary, the polarities of the transistors N1to N5and P1to P5, which constitute the input and output buffers, and the polarities of the power supply voltages, which are applied to the power supply lines21,22and23, may be reversed.

Next, a semiconductor device according to Modification 1 of the invention is described with reference toFIG. 4. In the description below, a description of parts common to those of the first embodiment is omitted.FIG. 4is a view for describing the semiconductor device according to Modification 2.FIG. 4is a plan view that schematically shows the part boxed by the broken line28inFIG. 1.

As shown inFIG. 4, a power supply voltage VCC is applied to the power supply line21, a power supply voltage VSS is applied to the power supply line22, and a power supply voltage VCCQ is applied to the power supply line23.

The output buffer31-1is disposed on a non-occupied region between the pads26-1and26-2. The output buffer31-2is disposed on a non-occupied region on the left side of the pad25-1. The output buffer31-3is disposed on a non-occupied region on the right side of the pad25-1.

In the semiconductor device according to this Modification, no input buffer is provided.

According to the above-described structure, the same advantages as with the first embodiment can be obtained. Further, the power supply voltage VCC is applied to the power supply line21, the power supply voltage VSS is applied to the power supply line22, and the power supply voltage VCCQ is applied to the power supply line23.

Thus, the power supply voltages can distinctively be applied to the power supply lines21,22and23, and it is possible to minimize the effect that is caused on the peripheral part by the power supply voltage VCCQ with a relatively large voltage variation. Therefore, the reliability can be enhanced.

Second Embodiment

Next, a semiconductor device according to a second embodiment of the invention is described with reference toFIG. 5. In the description below, a description of parts common to those of the first embodiment is omitted.FIG. 5is a view for describing the semiconductor device according to the second embodiment.FIG. 5is a plan view that schematically shows a part of the external connection region14. In the description of the semiconductor device according to this embodiment, depiction of detailed connections of the transistors, which constitute the output buffers31and input buffers32, is omitted.

As shown in the Figure, output pads31-1to31-4and input pads32-1to32-4are provided in the second direction so as to sandwich pads25-1,25-2,26-1and26-2.

The output buffers31-1to31-4include PMOS transistors P1, P3, P5and P7and NMOS transistors N1, N3, N5and N7, which are disposed to be opposed in the second direction so as to sandwich the pads25-1,25-2,26-1and26-2.

The input buffers32-1to32-4include PMOS transistors P2, P4, P6and P8and NMOS transistors N2, N4, N6and N8, which are disposed to be opposed in the second direction so as to sandwich the pads25-1,25-2,26-1and26-2.

None of the pads of the pad arrays25and26is disposed with a displaced pitch in the first direction.

The sources of the NMOS transistors N1to N6are commonly connected to the power supply line22. In the other respects, the structure of the second embodiment is the same as that of the first embodiment.

According to the above-described structure, the same advantages as with the first embodiment can be obtained. Further, the arrangement of the pads and output/input buffers may be altered, where necessary, as shown in the Figure.

Besides, the sources of the NMOS transistors N1to N6are commonly connected to the power supply line22. Therefore, the area in the second direction can be reduced.

Next, a semiconductor device according to Modification 3 of the invention is described with reference toFIG. 6. In the description below, a description of parts common to those of the second embodiment is omitted.FIG. 5is a view for describing the semiconductor device according to Modification 2.FIG. 6is a plan view that schematically shows a part of the external connection region14. In this Modification, compared to the semiconductor device according to the second embodiment, the polarities of the transistors N1to N8and P1to P8, which constitute the input and output buffers, are reversed.

As shown inFIG. 6, a power supply voltage VSS is applied to the power supply lines21and23, and a power supply voltage VCC or VCCQ is applied to the power supply line22. The sources of the PMOS transistors P1to P8are commonly connected to the power supply line22. In the other respects, the structure of Modification 3 is the same as that of the second embodiment.

According to the above-described structure, the same advantages as with the second embodiment can be obtained. Further, where necessary, the polarities of the power supply voltages, which are applied to the power supply lines21,22and23, and the polarities of the transistors N1to N8and P1to P8may be altered.

Third Embodiment

Next, a semiconductor device according to a third embodiment of the invention is described with reference toFIG. 7. In the description below, a description of parts common to those of the first embodiment is omitted.FIG. 7is a view for describing the semiconductor device according to the third embodiment.FIG. 7is a plan view that schematically shows a part of the external connection region14.

As shown in the Figure, output buffers31-1to31-4and input buffers32-1to32-4are provided in the first direction so as to sandwich pads25-1,25-2,26-1and26-2of the pad arrays25and26.

The output buffers31-1to31-4include PMOS transistors P1, P3, P5and P7and NMOS transistors N1, N3, N5and N7, which are disposed to be opposed in the first direction so as to sandwich the pads25-1,25-2,26-1and26-2.

The input buffers32-1to32-4include PMOS transistors P2, P4, P6and P8and NMOS transistors N2, N4, N6and N8, which are disposed to be opposed in the first direction so as to sandwich the pads25-1,25-2,26-1and26-2. In the other respects, the structure of the third embodiment is the same as that of the first embodiment.

According to the above-described structure, the same advantages as with the first embodiment can be obtained. Further, the PMOS transistors P1to P8and the NMOS transistors N1to N8are disposed to be opposed in the first direction so as to sandwich the pads25-1and26-1.

Thus, the arrangement of the transistors P1to P8and N1to N8can be altered, where necessary.

Next, a semiconductor device according to Modification 4 of the invention is described with reference toFIG. 8. In the description below, a description of parts common to those of the third embodiment is omitted.FIG. 8is a view for describing the semiconductor device according to Modification 4.FIG. 8is a plan view that schematically shows a part of the external connection region14. In this Modification, compared to the semiconductor device according to the third embodiment, the polarities of the transistors N1to N8and P1to P8, which constitute the input and output buffers, are reversed.

As shown inFIG. 8, a power supply voltage VSS is applied to the power supply lines21and23, and a power supply voltage VCC or VCCQ is applied to the power supply line22. In the other respects, the structure of Modification 4 is the same as that of the third embodiment.

According to the above-described structure, the same advantages as with the third embodiment can be obtained. Further, the power supply voltage VSS is applied to the power supply lines21and23, and the power supply voltage VCC or VCCQ is applied to the power supply line22.

Thus, where necessary, the polarities of the power supply voltages, which are applied to the power supply lines21,22and23, and the polarities of the transistors may be altered.

Fourth Embodiment

Next, a semiconductor device according to a fourth embodiment of the invention is described with reference toFIG. 9. In the description below, a description of parts common to those of the third embodiment is omitted.FIG. 9is a view for describing the semiconductor device according to the fourth embodiment.FIG. 9is a plan view that schematically shows a part of the external connection region14.

As shown in the Figure, the pad array26is provided with a displacement of about ½ pitch in the first direction, relative to the pads25-1to25-3of the pad array25. Thus, the pad arrays25and26are arranged in a so-called staggered fashion. The sources of the NMOS transistors N1to N8are commonly connected to the power supply line22. In the other respects, the structure of the fourth embodiment is the same as that of the third embodiment.

According to the above-described structure, the same advantages as with the first embodiment can be obtained.

Needless to say, as in the above-described Modifications, the polarities of the transistors N1to N8and P1to P8, which constitute the input and output buffers of the semiconductor device of this embodiment, and the polarities of the power supply voltages, which are applied to the power supply lines21,22and23, may be reversed.

Fifth Embodiment

Next, a semiconductor device according to a fourth embodiment of the invention is described with reference toFIG. 9. In the description below, a description of parts common to those of the fourth embodiment is omitted.FIG. 9is a view for describing the semiconductor device according to Modification 4, and is a plan view that schematically shows a part of the external connection region14. In this modification, output buffers31and input buffers32are disposed in the second direction in the pad array25, and are disposed in the first direction in the pad array26;

As shown in the Figure, PMOS transistors P1and P3and NMOS transistors N1and N3, which constitute the output buffers31-1and31-2in the pad array25, are disposed to be opposed in the second direction so as to sandwich the pads25-1and25-2. PMOS transistors P2and P4and NMOS transistors N2and N4, which constitute the input buffers32-1and32-2in the pad array25, are disposed to be opposed in the second direction so as to sandwich the pads25-1and25-2.

PMOS transistors P5and P7and NMOS transistors N5and N7, which constitute the output buffers31-3and31-4in the pad array26, are disposed to be opposed in the first direction so as to sandwich the pads26-1and26-2. PMOS transistors P6and P8and NMOS transistors N6and N8, which constitute the input buffers32-3and32-4in the pad array26, are disposed to be opposed in the first direction so as to sandwich the pads26-1and26-2. In the other respects, the structure of the fifth embodiment is the same as that of the fourth embodiment.

According to the above-described structure, the same advantages as with the fourth embodiment can be obtained. Further, the output buffers31and input buffers32are disposed in the second direction in the pad array25, and are disposed in the first direction in the pad array26.

Thus, the arrangement of the transistors P1to P8and N1to N8, which constitute the output buffers31and input buffers32, can be altered, where necessary.

Sixth Embodiment

Next, a semiconductor device according to a sixth embodiment of the invention is described with reference toFIG. 11. In the description below, a description of parts common to those of the fifth embodiment is omitted.FIG. 11is a view for describing the semiconductor device according to the fifth embodiment.FIG. 11is a plan view that schematically shows a part of the external connection region14.

As shown inFIG. 11, a transistor N1and a transistor P3, which have different polarities, are disposed adjacent to each other in the first direction. A distance (space) W1in the first direction is provided between the sources of the neighboring transistors N1and N2and the sources of neighboring transistors P1and P2. The distance W1is, e.g. about 100 μm.

Transistor P2and N5, which have different polarities, and transistors N2and P5, which have different polarities, are disposed adjacent to each other in the second direction. Further, a distance W2in the second direction is provided between the sources of the neighboring transistors P2, P5and the sources of the neighboring transistors N2, N5.

According to the above-described structure, the same advantages as with the fourth embodiment can be obtained. Further, the distance W1in the first direction is provided between the sources of the neighboring transistors N1and N2and the sources of neighboring transistors P1and P2.

Thus, the distance W1is provided between the sources of the transistors with different polarities, thereby to prevent switching of parasitic thyristors, which are formed of parasitic PNP and NPN bipolar transistors. Therefore, so-called latch-up can be prevented, and the reliability can be enhanced.

The distance W2in the second direction is provided between the sources of the neighboring transistors P2, P5and the sources of the neighboring transistors N2, N5.

Thus, by virtue of the same function as described above, latch-up can be prevented and the reliability can be enhanced.

Since the transistors with different polarities can be arranged adjacent to each other in the first and second directions, PMOS transistors or NMOS transistors may be arranged, where necessary, while latch-up can be prevented.

The present invention has been described by referring to the first to sixth embodiments and Modifications 1 to 4. The present invention is not limited to the above-described embodiments and Modifications. Various modifications can be made in practice without departing from the spirit of the invention. The embodiments and Modifications include various inventions, and various inventions can be derived from proper combinations of structural elements disclosed herein. For example, in the case where at least one of the problems described in the specification can be solved and at least one of the advantageous effects described in the specification can be achieved, even if some structural elements are omitted from all the structural elements disclosed in the embodiments and Modifications, the structure without such structural elements can be derived as an invention.