Amplifiers with improved linearity and noise performance

Amplifiers with improved linearity and noise performance are described. In an exemplary design, an apparatus includes first through sixth transistors. The first transistor receives an input signal and provides an amplified signal. The second transistor receives the amplified signal and provides signal drive for an output signal. The third transistor receives the input signal and provides an intermediate signal. The fourth transistor provides bias for the third transistor in a high linearity mode. The fifth transistor receives the intermediate signal and provides signal drive for the output signal in a low linearity mode. The third and fourth transistors form a deboost path that is enabled in the high linearity mode to improve linearity. The third and fifth transistors form a cascode path that is enabled in the low linearity mode to improve gain and noise performance. The sixth transistor generates distortion component used to cancel distortion component from the first transistor.

BACKGROUND

The present disclosure relates generally to electronics, and more specifically to amplifiers.

Amplifiers are commonly used in various electronics devices to provide signal amplification. Different types of amplifiers are available for different uses. For example, a wireless communication device such as a cellular phone may include a transmitter and a receiver for bi-directional communication. The receiver may utilize a low noise amplifier (LNA), the transmitter may utilize a power amplifier (PA), and the receiver and transmitter may utilize variable gain amplifiers (VGAs).

An LNA is commonly used in a receiver to amplify a low-amplitude signal received via a communication channel. The LNA is often the first active circuit encountered by the received signal and hence has a large impact on the performance of the receiver in several key areas. First, the LNA has a large influence on the overall noise figure of the receiver since the noise of the LNA is injected directly into the received signal and the noise of subsequent circuits is effectively reduced by the gain of the LNA. Second, the linearity of the LNA has a large influence on both the design of subsequent circuits in the receiver and the receiver performance. The LNA input signal typically includes various undesired signal components that may come from external interfering sources and leakage from a co-located transmitter. Nonlinearity of the LNA causes the undesired signal components to mix and generate cross modulation distortion components that may fall within the desired signal bandwidth. The amplitude of the distortion components is determined by the amount of nonlinearity of the LNA. Distortion components that fall within the desired signal bandwidth act as noise that may degrade the signal-to-noise ratio (SNR) of the desired signal, which may in turn degrade performance. Therefore, an LNA having good linearity and low noise figure may be highly desirable.

DETAILED DESCRIPTION

Amplifiers with improved linearity and noise performance are described herein. These amplifiers may be used for various electronics devices such as wireless and wireline communication devices, cellular phones, personal digital assistants (PDAs), handheld devices, wireless modems, laptop computers, cordless phones, Bluetooth devices, broadcast receivers, etc. These amplifiers may also be used for various applications such as communication, networking, computing, consumer electronics, etc. For example, the amplifiers may be used in wireless communication systems such as Code Division Multiple Access (CDMA) systems, Time Division Multiple Access (TDMA) systems, Frequency Division Multiple Access (FDMA) systems, Orthogonal FDMA (OFDMA) systems, Single-Carrier FDMA (SC-FDMA) systems, wireless local area network (WLAN) systems, etc. The amplifiers may also be used for various radio technologies such as Global System for Mobile Communications (GSM) used in TDMA systems, CDMA 1X and Wideband CDMA (WCDMA) used in CDMA systems, Long Term Evolution (LTE) and LTE-Advanced (LTE-A) used in OFDMA and SC-FDMA systems, Global Positioning System (GPS), etc. For clarity, the use of the amplifiers in a wireless communication device is described below.

FIG. 1shows a block diagram of an exemplary design of a wireless communication device100, which may be a cellular phone or some other device. In the exemplary design shown inFIG. 1, wireless device100includes a transceiver120having a receiver130and a transmitter150that support bi-directional communication. In general, wireless device100may include any number of receivers and any number of transmitters for any number of communication systems and any number of frequency bands.

In the receive path, an antenna110receives signals transmitted by base stations and other transmitter stations and provides a received RF signal, which is routed through a duplexer/switch112and provided to receiver130. Within receiver130, the received RF signal is amplified by an LNA132and demodulated by a receive demodulator (RX Demod)134to obtain a downconverted signal. The downconverted signal is amplified by an amplifier (Amp)136, filtered by a lowpass filter138, and further amplified by an amplifier140to obtain an input baseband signal, which is provided to a data processor170

In the transmit path, data processor170processes data to be transmitted and provides an output baseband signal to transmitter150. Within transmitter150, the output baseband signal is amplified by an amplifier152, filtered by a lowpass filter154, amplified by an amplifier156, and modulated by a transmit (TX) modulator158to obtain a modulated signal. A power amplifier (PA)160amplifies the modulated signal to obtain a desired output power level and provides a transmit RF signal. The transmit RF signal is routed through duplexer/switch112and transmitted via antenna110. A local oscillator (LO) signal generator162generates downconversion LO signals for demodulator134and upconversion LO signals for modulator158.

A jammer detector142detects for jammers in the received RF signal based on the downconverted signal from demodulator134(or some other signal in the receive path) and provides a jammer indicator. A jammer is an undesired signal that may be much larger in amplitude than a desired signal and may be located close in frequency to the desired signal. Jammer detector142may detect for close-in jammers and farther-out jammers, e.g., using filters with different bandwidths. Jammer detection may also be performed based on digital samples obtained by digitizing the input baseband signal from amplifier140. The operation of LNA132and/or other amplifiers may be controlled based on detected jammers. For example, an LNA control may be generated based on detected jammers and used to control the operation of LNA132.

FIG. 1shows an exemplary design of transceiver120. In general, the conditioning of the signals in receiver130and transmitter150may be performed by one or more stages of amplifier, filter, upconverter, downconverter, etc. The circuit blocks may be arranged differently from the configuration shown inFIG. 1. Furthermore, other circuit blocks not shown inFIG. 1may also be used to condition the signals in the transmitter and receiver. Some circuit blocks inFIG. 1may also be omitted. All or a portion of transceiver120may be implemented on an analog integrated circuit (IC), an RF IC (RFIC), a mixed-signal IC, etc.

Data processor170may perform various functions for wireless device100, e.g., processing for transmitted and received data. Data processor170may also generate controls (e.g., LNA control) for various circuit blocks in transceiver120. A memory172may store program codes and data for data processor170. Data processor170and memory172may be implemented on one or more application specific integrated circuits (ASICs) and other ICs.

FIG. 2Ashows the received RF signal from antenna110. The received RF signal may include a desired signal210and a jammer220. Jammer220is an undesired signal and may correspond to, for example, a signal transmitted by a nearby base station in an Advanced Mobile Phone System (AMPS) system.

FIG. 2Bshows the input RF signal at the input of LNA132. The input RF signal may include desired signal210and jammer220in the received RF signal as well as a TX leakage signal230from the transmit path. The TX leakage signal may be large relative to the desired signal, especially if wireless device100is far from a serving base station and needs to transmit at a high power level in order to reach the serving base station.

FIG. 2Cshows the output RF signal at the output of LNA132. Nonlinearity of LNA132may cause TX leakage signal230to interact with narrowband jammer220and generate cross modulation distortion components240around the jammer. A portion250of the cross modulation distortion, which is shown with shading, may fall within the desired signal band. Portion250would act as additional noise that may degrade the performance of the receiver. This noise may also degrade receiver sensitivity so that the smallest desired signal that can be reliably detected by the receiver needs to have a larger amplitude.

In an aspect, an amplifier capable of achieving high linearity and low noise figure may be used for LNA132. The amplifier may support multiple operating modes, which may include a high linearity mode, a low linearity mode, and possibly other modes. The high linearity mode may be used to obtain high linearity for the amplifier and may be selected when strong jammers are detected. The low linearity mode may be used to obtain low noise figure (i.e., improved noise performance) for the amplifier and may be selected when strong jammers are not detected.

FIG. 3shows a schematic diagram of an exemplary design of an amplifier300, which is capable of achieving high linearity and low noise figure. Amplifier300may be used for LNA132inFIG. 1and possibly other amplifiers in receiver130and transmitter150. In the exemplary design shown inFIG. 3, amplifier300includes a main signal path302, an auxiliary signal path304, and a distortion generation path306. Main signal path302includes N-channel metal oxide semiconductor (NMOS) transistors320and360that provide signal amplification for an input RF signal (RFin) and provide signal drive for an output RF signal (RFout). Auxiliary signal path304includes NMOS transistors310,340and350that may be operated to improve the linearity or noise figure of amplifier300. Distortion generation path306includes an NMOS transistor330that generates distortion components used to cancel distortion components from main signal path302and hence improve the linearity of amplifier300.

NMOS transistors310and320are coupled in parallel and have their gates coupled together and their sources coupled together. The input RF signal is provided to the gates of NMOS transistors310and320. An inductor322is coupled between the sources of NMOS transistors310and320and circuit ground and provides source degeneration for these NMOS transistors. NMOS transistor330has its gate coupled to one end of a capacitor334, its drain coupled to the drain of NMOS transistor320, and its source coupled to one end of an inductor332. Capacitor334provides AC coupling and has its other end receiving the input RF signal. Inductor332provides source degeneration for NMOS transistor330and has its other end coupled to circuit ground.

NMOS transistor340has its gate receiving a high linearity (HL) control signal, its source coupled to the drain of NMOS transistor310, and its drain coupled to a power supply, Vdd. NMOS transistor350has its gate receiving a low linearity (LL) control signal, its source coupled to the drain of NMOS transistor310, and its drain coupled to an output node X. NMOS transistor360has its gate receiving a Vb1 bias voltage, its source coupled to the drains of NMOS transistors320and330, and its drain coupled to output node X.

A load370includes an inductor372and a variable capacitor374coupled in parallel and between the power supply and output node X. Inductor372and capacitor374form a resonator circuit having a resonant frequency that may be adjusted by varying the capacitance of capacitor374. The resonant frequency may be set to a frequency channel or band of interest. Output node X provides the output RF signal.

NMOS transistors320and360form a first cascode pair used for signal amplification. NMOS transistor320provides signal amplification. NMOS transistor360provides load isolation for NMOS transistor320and also provides signal drive for the output RF signal. NMOS transistors310and340form a deboost path that may be enabled to improve the linearity of amplifier300, as described below. NMOS transistors310and350form a second cascode pair that may be enabled to provide additional signal amplification and improve gain and noise performance. NMOS transistor310provides signal amplification. NMOS transistor350provides load isolation for NMOS transistor310and also provides signal drive for the output RF signal. NMOS transistor330generates cross modulation distortion components used for distortion cancellation based on a modified derivative superposition (MDS) method. NMOS transistor330may be enabled to improve the linearity of amplifier300.

Inductor322provides source degeneration for NMOS transistors310and320and may further provide input impedance matching looking into the gates of NMOS transistors310and320. Inductor332provides source degeneration for NMOS transistor330and is also used to generate the proper distortion components for distortion cancellation.

FIG. 3shows an exemplary design of amplifier300capable of achieving high linearity and low noise figure. Amplifier300may also be implemented in other manners. For example, the source of NMOS transistor330may be coupled to a center tap of inductor322instead of separate inductor332. The drain of NMOS transistor330may be coupled to a cascode NMOS transistor, which may be coupled to output node X, e.g., similar to NMOS transistor350or360. The gate of NMOS transistor330may be coupled to the drain (instead of the gate) of NMOS transistor320via AC coupling capacitor334. Load370may be replaced with a transformer having a primary coil and a secondary coil. The primary coil may be coupled between the Vdd power supply and output node X, and the secondary coil may be coupled to a subsequent circuit, e.g., downconverter134inFIG. 1. Load370may also be replaced with an active load, which may be implemented with P-channel metal oxide semiconductor (PMOS) transistors or some other type of transistors.

In an exemplary design, amplifier300may operate in a high linearity mode or a low linearity mode. The high linearity mode may be used to obtain high linearity for amplifier300and may be selected when greater linearity is desired to reduce cross modulation distortion. The low linearity mode may be used to obtain lower noise figure for amplifier300and may be selected when high linearity is not required and better noise performance is desired. In an exemplary design, the high or low linearity mode may be selected based on jammer level. The high linearity mode may be selected if the jammer level exceeds a TH1 threshold, and the low linearity mode may be selected if the jammer level falls below a TH2 threshold. TH1 may be higher than TH2 to provide hysteresis and avoid continually toggling between the high and low linearity modes when the jammer level fluctuates near the TH1 or TH2 threshold. The high or low linearity mode may also be selected based on other factors.

In general, any number of operating modes may be supported by amplifier300. Each operating mode may be associated with certain transistors within amplifier300being enabled to provide the desired performance (e.g., higher linearity or lower noise figure) for that operating mode. Different operating modes may also be associated with different amounts of bias current for the transistors within amplifier300. For example, more bias current may be used for operating modes requiring higher linearity. The different operating modes for amplifier300may be selected based on jammer level and/or other factors. For clarity, much of the description below assumes two operating modes, the high and low linearity modes, for amplifier300.

FIG. 4shows operation of amplifier300in the high linearity mode. In this exemplary design of the high linearity mode, NMOS transistors310and340in the deboost path are enabled by a high voltage on the HL control signal. NMOS transistors320and360in the main signal path are enabled by the Vg1 and Vb1 bias voltages, respectively. NMOS transistor330in the distortion generation path is enabled by a Vg2 bias voltage. NMOS transistor350(not shown inFIG. 4) is disabled by a low voltage on the LL control signal.

NMOS transistor320provides signal amplification for the input RF signal and has nonlinearity. NMOS transistors310and340in the deboost path improve the linearity of NMOS transistor320. When the deboost path is enabled as shown inFIG. 4, NMOS transistor310provides a source current of is1, which is summed with a source current of is2from NMOS transistor320. The summed current of is1+is2is passed through inductor322. The source current of NMOS transistor310thus increases the current through inductor322, which increases the effective inductance of inductor322. The higher inductance results in more source degeneration for NMOS transistor320, which improves the linearity of NMOS transistor320. The gain of NMOS transistor320may be minimally impacted by NMOS transistor310being turned on. There may thus be negligible gain loss in the main signal path due to the deboost path being enabled.

NMOS transistor330generates third-order distortion component used to cancel third-order distortion component from NMOS transistor320and hence improve linearity. NMOS transistor320has a small-signal transconductance of g1, which is determined by various factors such as the size (e.g., length and width) of NMOS transistor320, the bias current for NMOS transistor320, the gate-to-source voltage νgsof NMOS transistor320, etc. NMOS transistor360has a small-signal transconductance of g1/α, where α is the ratio of the transconductance of NMOS transistor320to the transconductance of NMOS transistor360. The factor α is typically determined by the ratio of the width of NMOS transistor320to the width of NMOS transistor360. NMOS transistor330has a small-signal transconductance of g1/β, where β is the ratio of the transconductance of NMOS transistor320to the transconductance of NMOS transistor330. The factor β is typically determined by the ratio of the width of NMOS transistor320to the width of NMOS transistor330. The factors α and β may be selected as described below.

Linearization of amplifier300using the MDS method may be achieved at low frequency as follows. At low frequency, inductor322is effectively shorted and does not come into play, and the vgsvoltage of NMOS transistor320is equal to the input RF signal voltage. The drain current idof NMOS transistor320may be represented by a power series as follows:
id(vgs)=g1·vgs+g2·vgs2+g3·vgs3+  Eq (1)
where

g2is a coefficient that defines the strength of second-order nonlinearity,

g3is a coefficient that defines the strength of third-order nonlinearity, and

id(vgs) is the drain current of NMOS transistor320as a function of νgs.

For simplicity, nonlinearities higher than third order are ignored in equation (1). Coefficients g1, g2and g3are determined by the device size and the bias current for NMOS transistor320. The Vg1 bias voltage may be set to obtain a desired bias current for NMOS transistor320. Coefficient g3controls the third-order intermodulation distortion (IMD3) at low signal level and hence determines the third-order input intercept point (IIP3), which is a metric commonly used to specify the linearity of an amplifier.

Similarly, the drain current of NMOS transistor330is a function of the input RF signal voltage and may be represented by the power series shown in equation (1). For the MDS method, a positive g3coefficient with a particular g3curvature for NMOS transistor320may be canceled with a negative g3coefficient with a mirrored g3curvature for NMOS transistor330. The Vg2 bias voltage for NMOS transistor330may be set to obtain the desired g3coefficient and curvature for NMOS transistor330. Inductor332allows for adjustment of the magnitude and phase of the third-order distortion component from NMOS transistor330to match the magnitude and phase of the third-order distortion component from NMOS transistor320.

At high frequency, the drain current of NMOS transistor320may be represented by a Volterra series, which is often used for nonlinear analysis. The Volterra series includes a Volterra kernel for each order of nonlinearity. The third-order Volterra kernel determines third-order nonlinearity at high frequency, which is of interest. The Volterra series may be evaluated to determine distortion components of interest, which are those that affect IIP3. NMOS transistor330may be used to generate distortion components used to cancel distortion components generated by third-order nonlinearity of NMOS transistor320.

FIG. 5shows operation of amplifier300in the low linearity mode. In this exemplary design of the low linearity mode, NMOS transistors310and350in the cascode path are enabled by a high voltage on the LL control signal. NMOS transistors320and360in the main signal path are enabled by the Vg1 and Vb1 bias voltages, respectively. NMOS transistor340(not shown inFIG. 5) is disabled by a low voltage on the HL control signal. NMOS transistor330(also not shown inFIG. 5) is disabled by a low Vg2 bias voltage. NMOS transistor330is not needed in the low linearity mode and may degrade noise figure if enabled. Turning off NMOS transistor330in the low linearity mode may improve the noise figure of amplifier300in this mode.

NMOS transistor320provides signal amplification for the input RF signal and is buffered by NMOS transistor360. NMOS transistor310provides additional signal amplification for the input RF signal and is buffered by NMOS transistor350. NMOS transistors310and350and NMOS transistors320and360form two signal paths or branches that are coupled in parallel. NMOS transistors310and350increase the signal gain and improve the noise performance of amplifier300in the low linearity mode.

As shown inFIGS. 4 and 5, NMOS transistor310is a common source (CS) transistor that is shared by both the high and low linearity modes. In the high linearity mode, NMOS transistor350is disabled, and NMOS transistors310and340form the deboost path that improves the linearity of amplifier300. In the low linearity mode, NMOS transistor340is disabled, and NMOS transistors310and350form the cascode path that improves the gain and noise figure of amplifier300. NMOS transistor310is thus enabled in both the high and low linearity modes but is used in different manners in the two modes.

Sharing NMOS transistor310for both the high and low linearity modes may provide various advantages. First, if NMOS transistor350is omitted (i.e., not included in amplifier300), then NMOS transistor310would be turned off in the low linearity mode when NMOS transistor340is disabled. The turned off NMOS transistor310would then act as a parasitic capacitance that would degrade the noise figure of amplifier300in the low linearity mode. Higher power consumption may then be required to obtain a given noise figure. The parasitic capacitance and degradation in noise figure are avoided by reusing NMOS transistor310in the low linearity mode. Second, amplifier300has similar input impedance, Zin, in both the high and low linearity modes due to NMOS transistor310being enabled in both modes. The constant Zin may simplify input impedance matching for amplifier300in the high and low linearity modes.

FIG. 6shows a schematic diagram of an exemplary design of a differential amplifier600, which is capable of achieving high linearity and low noise figure. Amplifier600may also be used for LNA132inFIG. 1and possibly other amplifiers in receiver130and transmitter150. In the exemplary design shown inFIG. 6, amplifier600includes NMOS transistors610a,620a,630a,640a,650aand660a, inductors622aand632a, and a capacitor634a, which are coupled in similar manner as NMOS transistors310,320,330,340,350and360, inductors322and332, and capacitor334, respectively, inFIG. 3. Amplifier600further includes NMOS transistors610b,620b,630b,640b,650band660b, inductors622band632b, and a capacitor634b, which are coupled in similar manner as NMOS transistors610a,620a,630a,640a,650aand660a, inductors622aand632a, and capacitor634a, respectively. A non-inverting input RF signal (RFinp) is provided directly or indirectly to the gates of NMOS transistors610a,620aand630a. An inverting input RF signal (RFinn) is provided directly or indirectly to the gates of NMOS transistors610b,620band630b. An inverting output RF signal (RFoutn) is provided by the drains of NMOS transistors650aand660a. A non-inverting output RF signal (RFoutp) is provided by the drains of NMOS transistors650band660b. A load670is coupled to the drains of NMOS transistors650a,660a,650band660b.

FIGS. 3 and 6show exemplary designs in which an amplifier includes one main signal path and one auxiliary signal path, with the auxiliary signal path being operated to improve the linearity or noise performance of the amplifier. An amplifier may also include multiple main signal paths that may be operated to provide different gains for the amplifier. For example, more main signal paths may be selected when the input RF signal level is low in order to improve the gain and noise performance of the amplifier. An amplifier may also include multiple auxiliary signal paths that may be operated to provide different amounts of improvement in linearity or noise performance of the amplifier.

FIG. 7shows a schematic diagram of an exemplary design of an amplifier700with multiple auxiliary signal paths. Amplifier700is also capable of achieving high linearity and low noise figure and may be used for LNA132inFIG. 1and possibly other amplifiers in receiver130and transmitter150. In the exemplary design shown inFIG. 7, amplifier700includes a main signal path702, N auxiliary signal paths704athrough704n, a distortion generation path706, and a load770.

Main signal path702includes NMOS transistor720and760and an inductor722, which are coupled in similar manner as NMOS transistors320and360and inductor322inFIG. 3. Distortion generation path706includes an NMOS transistor730, an inductor732, and an AC coupling capacitor734, which are coupled in similar manner as NMOS transistors330, inductor332, and capacitor334inFIG. 3. Each auxiliary signal path704includes NMOS transistors710,740and750, which are coupled in similar manner as NMOS transistors310,340and350inFIG. 3. Auxiliary signal paths704aand704nreceive HL1through HLN control signals, respectively, for NMOS transistors740and also receive LL1through LLN control signals, respectively, for NMOS transistors750. NMOS transistors710,740and750in the N auxiliary signal paths704athrough704nmay have the same sizes or different sizes.

Each auxiliary signal path704includes a deboost path formed by NMOS transistors710and740and a cascode path formed by NMOS transistors710and750. Each auxiliary signal path704may have its deboost path enabled with a high voltage on the HL control signal or its cascode path enabled with a high voltage on the LL control signal. The number of deboost paths to enable may be dependent on the desired linearity, and progressively more deboost paths may be enabled to obtain progressively better linearity. The number of cascode paths to enable may be dependent on the desired noise and gain performance, and progressively more cascode paths may be enabled to obtain progressively better noise and gain performance.

FIG. 8shows a schematic diagram of an exemplary design of multiple (M) amplifiers800athrough800mcoupled in parallel. In this exemplary design, each amplifier800includes NMOS transistors810,820,830,840,850and860, inductors822and832, and a capacitor834, which are coupled in similar manner as NMOS transistors310,320,330,340,350and360, inductors322and332, and capacitor334, respectively, inFIG. 3. A load is formed by a transformer870having a primary coil872and a secondary coil874. Primary coil872has one end coupled to the Vdd power supply and the other end coupled to the drains of NMOS transistors850and860in the M amplifiers800athrough800m. Secondary coil874provides a differential output RF signal, RFoutp and RFoutn, and is coupled to a subsequent circuit, e.g., demodulator134inFIG. 1.

Amplifiers800athrough800mmay be designed for different frequency bands (e.g., cellular band and PCS band) and/or different radio technologies (e.g., GSM, CDMA 1X, WCDMA, etc.). Each amplifier800may receive a respective input RF signal and provide a respective output RF signal for its frequency band and/or radio technology. Amplifiers800athrough800mmay also be designed for different operating modes, e.g., high and low linearity modes, high and low power modes, etc. In any case, one or more of the M amplifiers800athrough800mmay be enabled to amplify the input RF signal(s), and remaining amplifiers may be disabled.

The amplifiers described herein may provide various advantages. First, the amplifiers may provide high linearity when the deboost path is enabled. Linearity may also be improved by the use of the distortion generation path, which may implement the MDS method or some other distortion cancellation method. Second, the amplifiers may support high frequency operation with low power consumption, which may be desirable for many wireless systems. Third, the input impedance of the amplifiers may be similar for both the high and low linearity modes, which may simplify input impedance matching for the amplifiers. Fourth, low noise figure may be obtained in the low linearity mode and high linearity may be obtained in the high linearity mode by sharing a common-source transistor for both modes. Fifth, the outputs of multiple amplifiers may be combined with one transformer, e.g., as shown inFIG. 8.

The amplifiers described herein may be able to meet or exceed stringent requirements for CDMA 1X. For example, the amplifiers may achieve an IIP3 of 6 dBm or better, a triple beat (TB) of 69 decibel (dB) or better, and a noise figure of 5 dB or lower in the high linearity mode. The amplifiers may achieve an IIP3 of −10 dBm or better, a triple beat of 49 dB or better, and a noise figure of 3 dB or lower in the low linearity mode. Computer simulation indicates that the amplifiers described herein can meet requirements of CDMA1X in PCS band with about one third to one half of the power consumption normally needed by conventional amplifiers to meet the same requirements. The amplifiers described herein may also be able to meet or exceed requirements for other systems and radio technologies.

In an exemplary design, an apparatus may comprise first through fifth transistors. The first transistor (e.g., NMOS transistor320inFIG. 3) may receive an input signal and provide an amplified signal. The second transistor (e.g., NMOS transistor360) may be coupled to the first transistor and may receive the amplified signal and provide signal drive for an output signal. The third transistor (e.g., NMOS transistor310) may be coupled to the first transistor and may receive the input signal and provide an intermediate signal. The fourth transistor (e.g., NMOS transistor340) may be coupled to the third transistor and may provide bias for the third transistor in a high linearity mode. The fifth transistor (e.g., NMOS transistor350) may also be coupled to the third transistor and may receive the intermediate signal and provide signal drive for the output signal in a low linearity mode. The fourth transistor may be enabled in the high linearity mode and disabled in the low linearity mode. The fifth transistor may be enabled in the low linearity mode and disabled in the high linearity mode. The input signal may observe similar input impedance in the high and low linearity modes.

The apparatus may further include a sixth transistor (e.g., NMOS transistor330) coupled to the first transistor. The sixth transistor may generate distortion component used to cancel distortion component generated by the first transistor. The sixth transistor may have its gate receiving the input signal and its drain coupled to the drain of the first transistor, e.g., as shown inFIG. 3. The sixth transistor may also generate the distortion component based on some other input signal and may have its drain coupled to some other transistor. The sixth transistor may be enabled in the high linearity mode and disabled in the low linearity mode.

The apparatus may further include an inductor coupled to the source of the first transistor and providing source degeneration for the first transistor. The third transistor may provide more current through the inductor to increase the inductance of the inductor and improve the linearity of the first transistor in the high linearity mode. The apparatus may further include a second inductor coupled to the source of the sixth transistor and providing source degeneration for the sixth transistor.

The apparatus may include a load coupled to the second and fifth transistors. In an exemplary design, the load may comprise an inductor and a capacitor coupled in parallel, e.g., as shown inFIG. 3. In another exemplary design, the load may comprise a transformer having a primary coil and a secondary coil. The primary coil may be coupled to the second and fifth transistors (e.g., as shown inFIG. 8), and the secondary coil may be coupled to a subsequent circuit (e.g., demodulator134inFIG. 1).

The apparatus may comprise additional transistors for a differential design, e.g., as shown inFIG. 6. The apparatus may also include a jammer detector to detect for jammers in the input signal. The high and low linearity modes may be determined based on detected jammers in the input signal.

In another exemplary design, an apparatus may comprise an amplifier (e.g., an LNA) to receive an input signal and provide an output signal. The amplifier may comprise a main signal path and an auxiliary signal path coupled in parallel, e.g., as shown inFIG. 3. The main signal path may receive and amplify the input signal and provide the output signal. The auxiliary signal path may comprise a first path (e.g., a deboost path) and a second path (e.g., a cascode path). The first path may be enabled to improve the linearity of the amplifier. The second path may be enabled to improve the gain and noise performance of the amplifier. The first and second paths may share a common source transistor, e.g., NMOS transistor310. The amplifier may further comprise a distortion generation path coupled in parallel with the main signal path. The distortion generation path may generate distortion component used to cancel distortion component generated by the main signal path.

The amplifier may further comprise a second auxiliary signal path coupled in parallel with the main signal path and comprising third and fourth paths, e.g., as shown inFIG. 7. The third path (e.g., another deboost path) may be enabled to improve the linearity of the amplifier. The fourth path (e.g., another cascode path) may be enabled to improve the gain and noise performance of the amplifier. The third and fourth paths may share a second common source transistor.

The apparatus may further comprise a second amplifier to receive a second input signal and provide a second output signal, e.g., as shown inFIG. 8. The two amplifiers may have their outputs coupled together and to a primary coil of a transformer, e.g., as shown inFIG. 8. The amplifiers may also provide their outputs separately.

In another exemplary design, a wireless communication device may comprise an antenna providing an input RF signal and an LNA amplifying the input RF signal and providing an output RF signal. The LNA may comprise first through fifth transistors. The first transistor (e.g., NMOS transistor320) may receive the input RF signal and provide an amplified signal. The second transistor (e.g., NMOS transistor360) may receive the amplified signal and provide signal drive for the output RF signal. The third transistor (e.g., NMOS transistor310) may receive the input RF signal and provide an intermediate signal. The fourth transistor (e.g., NMOS transistor340) may provide bias for the third transistor in a high linearity mode. The fifth transistor (e.g., NMOS transistor350) may receive the intermediate signal and provide signal drive for the output RF signal in a low linearity mode. The LNA may further comprise a sixth transistor (e.g., NMOS transistor330) that may generate distortion component used to cancel distortion component generated by the first transistor in the high linearity mode.

FIG. 9shows an exemplary design of a process900for performing signal amplification. An input signal may be amplified with a first transistor to obtain an amplified signal (block912). The amplified signal may be buffered with a second transistor to obtain an output signal (block914). The input signal may also be amplified with a third transistor to obtain an intermediate signal (block916). Bias for the third transistor may be provided with a fourth transistor in a high linearity mode (block918). The intermediate signal may be buffered, and signal drive may be provided for the output signal with a fifth transistor in a low linearity mode (block920). Distortion component may be generated with a sixth transistor in the high linearity mode (block922). Distortion component generated by the first transistor may be canceled with the distortion component generated by the sixth transistor in the high linearity mode (block924).

The amplifiers described herein may be implemented on an IC, an analog IC, an RFIC, a mixed-signal IC, an ASIC, a printed circuit board (PCB), an electronics device, etc. The amplifiers may also be fabricated with various IC process technologies such as complementary metal oxide semiconductor (CMOS), NMOS, PMOS, bipolar junction transistor (BJT), bipolar-CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

An apparatus implementing the amplifiers described herein may be a stand-alone device or may be part of a larger device. A device may be (i) a stand-alone IC, (ii) a set of one or more ICs that may include memory ICs for storing data and/or instructions, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter/receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that may be embedded within other devices, (vi) a receiver, cellular phone, wireless device, handset, or mobile unit, (vii) etc.