Memory and logic with shared cryogenic implants

An integrated circuit includes logic circuits of NMOS and PMOS transistors, and memory cells with NMOS and PMOS transistors. A common NSD implant mask exposes source and drain regions of a logic NMOS transistor and a memory NMOS transistor. The source and drain regions of the logic NMOS transistor and the memory NMOS transistor are concurrently implanted at a cryogenic temperature with an amorphizing species followed by arsenic. Phosphorus is concurrently implanted in the source and drain regions of the logic NMOS transistor and the memory NMOS transistor. The source and drain regions of the logic NMOS transistor are further implanted with phosphorus at a non-cryogenic temperature while the memory NMOS transistor is covered by a mask which blocks the phosphorus.

FIELD OF THE INVENTION

This invention relates to the field of integrated circuits. More particularly, this invention relates to MOS transistors in integrated circuits.

BACKGROUND OF THE INVENTION

An integrated circuit may include logic circuits of n-channel metal oxide semiconductor (NMOS) transistors and p-channel metal oxide semiconductor (PMOS) transistors, and it may be desirable to form the logic circuits to operate at a high speed. The integrated circuit may also include memory cells which have NMOS transistors in each cell, and it may be desirable to form the memory cells so as to reduce leakage current. It may further be desirable to maintain fabrication costs of the integrated circuit below a desired limit.

SUMMARY OF THE INVENTION

An integrated circuit includes logic circuits of NMOS and PMOS transistors, and memory cells with NMOS transistors. Source and drain regions of a logic NMOS transistor and a memory NMOS transistor are concurrently implanted at a cryogenic temperature with an amorphizing species followed by arsenic. Phosphorus is concurrently implanted in the source and drain regions of the logic NMOS transistor and the memory NMOS transistor. The source and drain regions of the logic NMOS transistor are further implanted with phosphorus at a non-cryogenic temperature while the memory NMOS transistor is covered by a mask which blocks the phosphorus.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

An integrated circuit includes logic circuits of NMOS and PMOS transistors, and memory cells with NMOS transistors. The logic circuits may include, for example, inverters, NAND gates, NOR gates, flip-flops, adders, multiplexers, and/or shift registers. The memory cells may be, for example, static random access memory (SRAM) cells, dynamic random access memory (DRAM) cells, flash memory cells, and/or ferroelectric random access memory (FRAM) cells.

A common n-channel source/drain (NSD) implant mask is formed which exposes a logic NMOS transistor and a memory NMOS transistor. Source and drain regions of the logic NMOS transistor and the memory NMOS transistor are concurrently implanted at a cryogenic temperature with an amorphizing species followed by arsenic. While the common NSD implant mask is in place, phosphorus is concurrently implanted in the source and drain regions of the logic NMOS transistor and the memory NMOS transistor, possibly at a cryogenic temperature or possibly at a non-cryogenic temperature.

A logic NSD implant mask is formed which exposes the logic NMOS transistor and covers the memory NMOS transistor. The source and drain regions of the logic NMOS transistor are implanted with phosphorus, and possibly also with arsenic, at a non-cryogenic temperature while the logic NSD implant mask is in place and blocks the phosphorus from the memory NMOS transistor.

In one example, the cryogenic implant of the amorphizing species and the arsenic into the logic and memory NMOS transistors may be done before the non-cryogenic implant of the phosphorus into the logic NMOS transistors. In another example, the non-cryogenic implant of the phosphorus may precede the cryogenic implant of the amorphizing species and the arsenic. An optional flash and/or laser anneal operation may be performed between the implants through the common NSD implant mask and the implants through the logic NSD implant mask. A laser anneal and possibly optional flash anneal is performed after the implants through the common NSD implant mask and the implants through the logic NSD implant mask are completed.

FIG. 1AthroughFIG. 1Kare cross sections of an integrated circuit containing logic circuits and memory cells, formed according to an exemplary process sequence, depicted in successive stages of fabrication. Referring toFIG. 1A, the integrated circuit100is formed in and on a substrate102which may be, for example, a silicon wafer, a silicon-on-insulator (SOI) wafer, a hybrid orientation technology (HOT) wafer with different crystal orientations for various transistors, or other substrate suitable for forming the integrated circuit100. The integrated circuit100includes a logic NMOS transistor104, a memory NMOS transistor106and a PMOS transistor108. It will be understood that reference to the integrated circuit100in this disclosure includes the integrated circuit100in successive stages of fabrication, as well as the completed integrated circuit100, and similarly for reference to the logic NMOS transistor104, the memory NMOS transistor106and the PMOS transistor108.

The logic NMOS transistor104includes a gate110, formed on a gate dielectric layer112on the substrate102. The gate110may include primarily polycrystalline silicon, commonly referred to as polysilicon. The logic NMOS transistor104further includes n-channel lightly doped drain (NLDD) regions114formed in the substrate102adjacent to and extending under the gate dielectric layer112. The logic NMOS transistor104also includes gate sidewall spacers116which include one or more dielectric layers on lateral surfaces of the gate110. In one version of the instant example, the logic NMOS transistor104may include optional epitaxial source and drain regions118formed in the substrate102adjacent to the gate110. The epitaxial source and drain regions118may include, for example, silicon with carbon to provide tensile stress to a channel region of the logic NMOS transistor104.

The memory NMOS transistor106includes a gate120, formed on a gate dielectric layer122on the substrate102. The memory NMOS transistor106further includes NLDD regions124formed in the substrate102adjacent to and extending under the gate dielectric layer122. The memory NMOS transistor106also includes gate sidewall spacers126similar to, and possibly formed concurrently with, the gate sidewall spacers116of the logic NMOS transistor104. In one version of the instant example, the memory NMOS transistor106may include optional epitaxial source and drain regions128formed in the substrate102adjacent to the gate120, similar to, and possibly formed concurrently with, the epitaxial source and drain regions118of the logic NMOS transistor104. The epitaxial source and drain regions128of the memory NMOS transistor106may be formed even if no epitaxial source and drain regions are formed in the logic NMOS transistor104. Conversely, the epitaxial source and drain regions118of the logic NMOS transistor104may be formed even if no epitaxial source and drain regions are formed in the memory NMOS transistor106.

The PMOS transistor108includes a gate130, formed on a gate dielectric layer132on the substrate102. The PMOS transistor108further includes p-channel lightly doped drain (PLDD) regions134formed in the substrate102adjacent to and extending under the gate dielectric layer132. The PMOS transistor108also includes gate sidewall spacers136formed on lateral surfaces of the gate130; some sublayers of the gate sidewall spacers136of the PMOS transistor108may be formed concurrently with sublayers of the gate sidewall spacers116of the logic NMOS transistor104and the gate sidewall spacers126of the memory NMOS transistor106. The PMOS transistor108may optionally include epitaxial source and drain regions, not shown, for example silicon germanium epitaxial source and drain regions to provide compressive stress in a channel region of the PMOS transistor108.

A common NSD implant mask138is formed over the integrated circuit100so as to expose the logic NMOS transistor104and the memory NMOS transistor106, and cover the PMOS transistor108. The common NSD implant mask138may include, for example, photoresist and possibly an antireflection layer.

The integrated circuit100is disposed on a first cryogenic substrate holder140, which cools the substrate102. The first cryogenic substrate holder140may be cooled by flowing a cryogenic fluid142such as liquid nitrogen or a halogenated hydrocarbon through the first cryogenic substrate holder140, as depicted schematically inFIG. 1A.

While the substrate102is cooled by the first cryogenic substrate holder140, an amorphizing species144, for example germanium, silicon, or argon, is implanted into the logic NMOS transistor104and the memory NMOS transistor106, while the common NSD implant mask138blocks the amorphizing species144from the PMOS transistor108. Implantation of the amorphizing species144forms amorphous layers146in the substrate102adjacent to the gate sidewall spacers116of the logic NMOS transistor104, and may form an amorphous layer148in the gate110. Similarly, implantation of the amorphizing species144forms amorphous layers150in the substrate102adjacent to the gate sidewall spacers126of the memory NMOS transistor106, and may form an amorphous layer152in the gate120. An exemplary dose range and energy range for the amorphizing species144may be 1×1014cm−2to 2×1015cm−2at 10 keV to 20 keV. While the amorphizing species144is implanted, the first cryogenic substrate holder140is maintained at a cryogenic temperature which is not higher than a maximum effective cryogenic temperature; the maximum effective cryogenic temperature is determined by the implant beam current density of the amophizing species implant process.

Referring toFIG. 1B, the integrated circuit100is disposed on a second cryogenic substrate holder154, which cools the substrate102, possibly using a cryogenic fluid156. While the substrate102is cooled by the second cryogenic substrate holder154, arsenic158is implanted into the logic NMOS transistor104and the memory NMOS transistor106, while the common NSD implant mask138blocks the arsenic158from the PMOS transistor108. Implantation of the arsenic158forms arsenic-doped layers160in the substrate102adjacent to the gate sidewall spacers116of the logic NMOS transistor104and within the amorphous layers146, and may form an arsenic-doped layer162in the gate110. Similarly, implantation of the arsenic158forms arsenic-doped layers164in the substrate102adjacent to the gate sidewall spacers126of the memory NMOS transistor106and within the amorphous layers150, and may form an arsenic-doped layer166in the gate120. An exemplary dose range and energy range for the arsenic158may be 5×1014cm−2to 1×1016cm−2at 10 keV to 20 keV. While the arsenic158is implanted, the second cryogenic substrate holder154is maintained at a cryogenic temperature which is equal to or colder than a maximum effective cryogenic temperature; the maximum effective cryogenic temperature is determined by the implant beam current density of the arsenic implant process. It will be recognized that the second cryogenic substrate holder154used for implanting the arsenic158may be the first cryogenic substrate holder140used for implanting the amorphizing species144.

Implanting the amorphizing species144and the arsenic158while cooling the substrate102on the first cryogenic substrate holder140and the second cryogenic substrate holder154, respectively, may desirably result in dislocation loops produced by the implant process being formed in the within the amorphous layers146and150, which may advantageously provide reduced crystal defects after a subsequent anneal, compared to process sequences which implant amorphizing species and arsenic at non-cryogenic temperatures and produce dislocation loops outside of amorphous layers. The maximum effective cryogenic temperatures of the first cryogenic substrate holder140and the second cryogenic substrate holder154are determined by a selected value of an implant beam current density of the amorphizing species144and an implant beam current density of the arsenic158; the relationship between a maximum effective cryogenic temperature Tmaxin degrees C. and a corresponding implant beam current density Jbeamin milliamps/sq.cm may be expressed by an Arrhenius equation:
log(Jbeam)=−(1020/(Tmax+273))+4.898

where log(Jbeam) is the base 10 logarithm of Jbeam

For an implant beam current density of 0.1 milliamps/cm2, the maximum effective cryogenic temperature is −100° C. (173° K). For an implant beam current density of 0.2 milliamps/cm2, the maximum effective cryogenic temperature is −90° C. (183° K). For an implant beam current density of 0.5 milliamps/cm2, the maximum effective cryogenic temperature is −77° C. (196° K). For an implant beam current density of 1 milliamp/cm2, the maximum effective cryogenic temperature is −65° C. (208° K). For an implant beam current density of 2 milliamps/cm2, the maximum effective cryogenic temperature is −51° C. (222° K). For an implant beam current density of 5 milliamps/cm2, the maximum effective cryogenic temperature is −30° C. (243° K). A chart of the maximum effective cryogenic temperature as a function of the implant beam current density is shown inFIG. 2.

Referring toFIG. 1C, phosphorus172is implanted into the logic NMOS transistor104and the memory NMOS transistor106, while the common NSD implant mask138blocks the phosphorus172from the PMOS transistor108. In the instant example, the phosphorus172is implanted while the substrate102is cooled by a third cryogenic substrate holder168, possibly cooled by a cryogenic fluid170. The third cryogenic substrate holder168is at a cryogenic temperature of −25° C. (248° K) or colder. It will be recognized that the third cryogenic substrate holder168used for implanting the phosphorus172may be the second cryogenic substrate holder154used for implanting the arsenic158and/or the first cryogenic substrate holder140used for implanting the amorphizing species144. Implantation of the phosphorus172forms phosphorus-doped layers174in the substrate102adjacent to the gate sidewall spacers116of the logic NMOS transistor104and overlapping the amorphous layers146, and may form a phosphorus-doped layer176in the gate110. Similarly, implantation of the phosphorus172forms phosphorus-doped layers178in the substrate102adjacent to the gate sidewall spacers126of the memory NMOS transistor106and overlapping the amorphous layers150, and may form a phosphorus-doped layer180in the gate120. An exemplary dose range and energy range for the phosphorus172may be 5×1014cm−2to 1×1016cm−2at 1 keV to 5 keV. Implanting the phosphorus172using the third cryogenic substrate holder168may accrue similar benefits as described for implanting the amorphizing species144and the arsenic158while cooling the substrate102. The common NSD implant mask138is subsequently removed, for example by ashing followed by a wet clean in an aqueous mixture of sulfuric acid and hydrogen peroxide.

Referring toFIG. 1D, an optional first intermediate laser anneal process182recrystallizes the amorphous layers146in the logic NMOS transistor104and the amorphous layers150in the memory NMOS transistor106, activates the arsenic in the arsenic-doped layers160in the logic NMOS transistor104and the arsenic-doped layers160in the memory NMOS transistor106, and activates the phosphorus in the phosphorus-doped layers174in the logic NMOS transistor104and the phosphorus-doped layers174in the memory NMOS transistor106, so as to form source and drain regions184in the substrate102adjacent to and extending under the gate dielectric layer112of the logic NMOS transistor104and to form source and drain regions186in the substrate102adjacent to and extending under the gate dielectric layer122of the memory NMOS transistor106. The first intermediate laser anneal process182recrystallizes the gate110and activates the arsenic and phosphorus implanted in the gate110of the logic NMOS transistor104, and recrystallizes the gate120and activates the arsenic and phosphorus implanted in the gate120of the memory NMOS transistor106. The first intermediate laser anneal process182may, for example, have a concentrated beam which is moved across the integrated circuit100as depicted schematically inFIG. 1Dto heat a top surface188of the substrate102to 1225° C. to 1275° C. for 100 nanoseconds to 100 microseconds.

Referring toFIG. 1E, an optional subsequent intermediate spike anneal process190further activates the arsenic and the phosphorus in the source and drain regions184of the logic NMOS transistor104and the source and drain regions186of the memory NMOS transistor106. The intermediate spike anneal process190may, for example, heat the substrate102to 950° C. to 1050° C. for 100 milliseconds to 2 seconds. In versions of the instant example in which the epitaxial source and drain regions118of the logic NMOS transistor104and/or the epitaxial source and drain regions128of the memory NMOS transistor106are present, the intermediate spike anneal process190may be advantageously limited to heating the substrate102to no more than 1000° C. so as to reduce carbon coming out of substitutional positions and reducing desired the tensile stress. The intermediate spike anneal process190may be performed in a rapid thermal processor (RTP).

Referring toFIG. 1F, an optional subsequent second intermediate laser anneal process192further activates the arsenic and the phosphorus in the source and drain regions184of the logic NMOS transistor104and the source and drain regions186of the memory NMOS transistor106. The second intermediate laser anneal process192may be similar to the first intermediate laser anneal process182. Performing the first intermediate laser anneal process182, the subsequent intermediate spike anneal process190and the subsequent second intermediate laser anneal process192may advantageously reduce crystal defects and provide a higher degree of activation of the arsenic and phosphorus compared to a process sequence having only one laser anneal or only one laser anneal and a spike anneal.

Referring toFIG. 1G, a logic NSD implant mask194is formed over the integrated circuit100so as to expose the logic NMOS transistor104and cover the memory NMOS transistor106and the PMOS transistor108. The logic NSD implant mask194may include, for example, photoresist and possibly an antireflection layer, and may be formed similarly to the common NSD implant mask138ofFIG. 1A. The integrated circuit100is disposed on a first non-cryogenic substrate holder196, which is at a non-cryogenic temperature above −25° C. (248° K). In one version of the instant example, the first non-cryogenic substrate holder196may be cooled with chilled water to a non-cryogenic temperature of 0° C. (273° K) to 20° C. (293° K). It will be recognized that the first non-cryogenic substrate holder196may be one of the cryogenic substrate holders140,154and/or168, which is not cooled for the instant step.

While the integrated circuit100is disposed on the first non-cryogenic substrate holder196, phosphorus198is implanted into the logic NMOS transistor104, while the logic NSD implant mask194blocks the phosphorus198from the memory NMOS transistor106and the PMOS transistor108. Implantation of the phosphorus198forms phosphorus-doped layers200in the substrate102adjacent to the gate sidewall spacers116of the logic NMOS transistor104, overlapping the source and drain regions184of the logic NMOS transistor104. A dose range and an energy range of the phosphorus198is 10 percent to 50 percent of the dose of the phosphorus172implanted at cryogenic temperature, at 1 keV to 5 keV.

Referring toFIG. 1H, the integrated circuit100may be disposed on a second non-cryogenic substrate holder202, and while the logic NSD implant mask194is in place, arsenic204may optionally be implanted into the logic NMOS transistor104, while the logic NSD implant mask194blocks the arsenic204from the memory NMOS transistor106and the PMOS transistor108. Implantation of the arsenic204forms arsenic-doped layers206in the substrate102adjacent to the gate sidewall spacers116of the logic NMOS transistor104, overlapping the source and drain regions184of the logic NMOS transistor104. A dose range and an energy range of the arsenic204is 10 percent to 30 percent of the dose of the arsenic158implanted at cryogenic temperature, at, for example, 10 keV to 20 keV. It will be recognized that the second non-cryogenic substrate holder202used for implanting the arsenic204may be the first non-cryogenic substrate holder196used for implanting the phosphorus198. The logic NSD implant mask194is subsequently removed, for example as described with respect to the common NSD implant mask138in reference toFIG. 1C.

Referring toFIG. 1I, a first final laser anneal process208activates the phosphorus in the phosphorus-doped layers200, and activates the arsenic in the arsenic-doped layers206, if present, to increase a total activated dopant amount in the source and drain regions184of the logic NMOS transistor104. The first final laser anneal process208may be similar to the first intermediate laser anneal process182described in reference toFIG. 1D.

Referring toFIG. 1J, an optional subsequent final spike anneal process210further activates the phosphorus and arsenic in the source and drain regions184of the logic NMOS transistor104. The final spike anneal process210may be similar to the intermediate spike anneal process190described in reference toFIG. 1E.

Referring toFIG. 1K, an optional subsequent second final laser anneal process212further activates the phosphorus and the arsenic in the source and drain regions184of the logic NMOS transistor104. The second final laser anneal process212may be similar to the first final laser anneal process208. Performing the first final laser anneal process208, the subsequent final spike anneal process210and the subsequent second final laser anneal process212may advantageously reduce crystal defects and provide a higher degree of activation of the arsenic and phosphorus compared to a process sequence having only one laser anneal or only a laser anneal and a spike anneal.

The integrated circuit100may be formed by an alternate process sequence, in which the common phosphorus172implant step described in reference toFIG. 1Cis performed using a third non-cryogenic substrate holder214.FIG. 3depicts the integrated circuit100in such an alternate process sequence at the common phosphorus implant step described in reference toFIG. 1C. The phosphorus172is implanted into the logic NMOS transistor104and the memory NMOS transistor106, while the common NSD implant mask138blocks the phosphorus172from the PMOS transistor108. In the instant example, the phosphorus172is implanted while the substrate102is disposed on the third non-cryogenic substrate holder214. It will be recognized that the third non-cryogenic substrate holder214used for implanting the phosphorus172may be the first non-cryogenic substrate holder196and/or the second non-cryogenic substrate holder202used for implanting the phosphorus198and the arsenic204, respectively, described in reference toFIG. 1GandFIG. 1H. Implantation of the phosphorus172forms the phosphorus-doped layers174in the substrate102adjacent to the gate sidewall spacers116of the logic NMOS transistor104as described in reference toFIG. 1C. Implanting the phosphorus172using the third non-cryogenic substrate holder214may advantageously reduce a fabrication cost of the integrated circuit100.

FIG. 4AthroughFIG. 4Dare cross sections of the integrated circuit100formed according to an alternate process sequence, in which the non-cryogenic implants precede the cryogenic implants, depicted in successive stages of fabrication. Referring toFIG. 4A, the logic NSD implant mask194is formed over the integrated circuit100so as to expose the logic NMOS transistor104and cover the memory NMOS transistor106and the PMOS transistor108. The integrated circuit100is disposed on the first non-cryogenic substrate holder196, which is at a non-cryogenic temperature above −25° C. (248° K). In the instant example, the optional epitaxial source and drain regions118of the logic NMOS transistor104and the optional epitaxial source and drain regions128of the memory NMOS transistor106are omitted.

The phosphorus198is implanted into the logic NMOS transistor104, while the logic NSD implant mask194blocks the phosphorus198from the memory NMOS transistor106and the PMOS transistor108. Implantation of the phosphorus198forms the phosphorus-doped layers200, described in reference toFIG. 1G, in the substrate102adjacent to the gate sidewall spacers116of the logic NMOS transistor104. A dose range of the phosphorus198is 10 percent to 50 percent of the dose of the yet-to-be implanted phosphorus172which will be implanted at cryogenic temperature. An energy range of the phosphorus198is 1 keV to 5 keV.

The integrated circuit100may be disposed on the second non-cryogenic substrate holder202, which is at a non-cryogenic temperature, and arsenic204may optionally be implanted into the logic NMOS transistor104, while the logic NSD implant mask194blocks the arsenic204from the memory NMOS transistor106and the PMOS transistor108. Implantation of the arsenic204forms the arsenic-doped layers206, described in reference toFIG. 1H, in the substrate102adjacent to the gate sidewall spacers116of the logic NMOS transistor104. A dose range of the arsenic204is 10 percent to 30 percent of the dose of the yet-to-be implanted arsenic158, which will be implanted at cryogenic temperature. An energy range of the arsenic204may be, for example, 10 keV to 20 keV. The logic NSD implant mask194is subsequently removed, for example as described with respect to the common NSD implant mask138in reference toFIG. 1C.

Referring toFIG. 4B, an optional first intermediate laser anneal process182activates the phosphorus in the phosphorus-doped layers200, and activates the arsenic in the arsenic-doped layers206, if present, to form the source and drain regions184in the substrate102adjacent to and extending under the gate dielectric layer112of the logic NMOS transistor104. An optional subsequent intermediate spike anneal process190further activates the arsenic and the phosphorus in the source and drain regions184of the logic NMOS transistor104. An optional subsequent second intermediate laser anneal process192further activates the arsenic and the phosphorus in the source and drain regions184of the logic NMOS transistor104. Performing the first intermediate laser anneal process182, the subsequent intermediate spike anneal process190and the subsequent second intermediate laser anneal process192may advantageously reduce crystal defects and provide a higher degree of activation of the arsenic and phosphorus compared to a process sequence having only one laser anneal or only one laser anneal and a spike anneal.

Referring toFIG. 4C, the common NSD implant mask138is formed over the integrated circuit100so as to expose the logic NMOS transistor104and the memory NMOS transistor106, and cover the PMOS transistor108. The integrated circuit100is disposed on the first cryogenic substrate holder140, which cools the substrate102as described in reference toFIG. 1AandFIG. 1B. The amorphizing species144is implanted into the logic NMOS transistor104and the memory NMOS transistor106, while the common NSD implant mask138blocks the amorphizing species144from the PMOS transistor108. Implantation of the amorphizing species144forms the amorphous layers146in the substrate102adjacent to the gate sidewall spacers116of the logic NMOS transistor104. Similarly, implantation of the amorphizing species144forms amorphous layers150in the substrate102adjacent to the gate sidewall spacers126of the memory NMOS transistor106. An exemplary dose range and energy range for the amorphizing species144may be 1×1014cm−2to 2×1015cm−2at 10 keV to 20 keV.

The integrated circuit100is disposed on the second cryogenic substrate holder154, which cools the substrate102as described in reference toFIG. 1AandFIG. 1B. The arsenic158is implanted into the logic NMOS transistor104and the memory NMOS transistor106, while the common NSD implant mask138blocks the arsenic158from the PMOS transistor108. Implantation of the arsenic158forms the arsenic-doped layers160in the substrate102adjacent to the gate sidewall spacers116of the logic NMOS transistor104. Similarly, implantation of the arsenic158forms the arsenic-doped layers164in the substrate102adjacent to the gate sidewall spacers126of the memory NMOS transistor106. An exemplary dose range and energy range for the arsenic158may be 5×1014cm−2to 1×1016cm−2at 10 keV to 20 keV.

The phosphorus172is implanted into the logic NMOS transistor104and the memory NMOS transistor106, while the common NSD implant mask138blocks the phosphorus172from the PMOS transistor108. In the instant example, the phosphorus172is implanted while the substrate102is cooled by the third cryogenic substrate holder168. Implantation of the phosphorus172forms phosphorus-doped layers174in the substrate102adjacent to the gate sidewall spacers116of the logic NMOS transistor104. Similarly, implantation of the phosphorus172forms phosphorus-doped layers178in the substrate102adjacent to the gate sidewall spacers126of the memory NMOS transistor106. An exemplary dose range and energy range for the phosphorus172may be 5×1014cm−2to 1×1016cm−2at 1 keV to 5 keV. Implanting the phosphorus172using the third cryogenic substrate holder168may accrue similar benefits as described for implanting the amorphizing species144and the arsenic158while cooling the substrate102. The common NSD implant mask138is subsequently removed, for example as described in reference toFIG. 1C.

Referring toFIG. 4D, the first final laser anneal process208recrystallizes the amorphous layers146in the logic NMOS transistor104and the amorphous layers150in the memory NMOS transistor106, activates the arsenic in the arsenic-doped layers160in the logic NMOS transistor104and the arsenic-doped layers160in the memory NMOS transistor106, and activates the phosphorus in the phosphorus-doped layers174in the logic NMOS transistor104and the phosphorus-doped layers174in the memory NMOS transistor106, so as to increase a total activated dopant amount in the source and drain regions184of the logic NMOS transistor104and to form source and drain regions186in the substrate102adjacent to and extending under the gate dielectric layer122of the memory NMOS transistor106. The first final laser anneal process208may be similar to the first intermediate laser anneal process182described in reference toFIG. 1D.

The optional subsequent final spike anneal process210further activates the phosphorus and arsenic in the source and drain regions184of the logic NMOS transistor104and the source and drain regions186of the memory NMOS transistor106. The final spike anneal process210may be similar to the intermediate spike anneal process190described in reference toFIG. 1E. The optional subsequent second final laser anneal process212further activates the phosphorus and the arsenic in the source and drain regions184of the logic NMOS transistor104and the source and drain regions186of the memory NMOS transistor106. The second final laser anneal process212may be similar to the first final laser anneal process208. Performing the first final laser anneal process208, the subsequent final spike anneal process210and the subsequent second final laser anneal process212may advantageously reduce crystal defects and provide a higher degree of activation of the arsenic and phosphorus compared to a process sequence having only one laser anneal or only a laser anneal and a spike anneal.

The integrated circuit100may be formed by an alternate process sequence, in which the common phosphorus implant step described in reference toFIG. 4Cis performed using a non-cryogenic substrate holder.FIG. 5depicts the integrated circuit100in such an alternate process sequence at the common phosphorus implant step described in reference toFIG. 4C. The phosphorus172is implanted into the logic NMOS transistor104and the memory NMOS transistor106, while the common NSD implant mask138blocks the phosphorus172from the PMOS transistor108. In the instant example, the phosphorus172is implanted while the substrate102is disposed on the third non-cryogenic substrate holder214. Implantation of the phosphorus172forms the phosphorus-doped layers174in the substrate102adjacent to the gate sidewall spacers116of the logic NMOS transistor104and forms the phosphorus-doped layers178in the substrate102adjacent to the gate sidewall spacers126of the memory NMOS transistor106, as described in reference toFIG. 4C. Implanting the phosphorus172using the third non-cryogenic substrate holder214may advantageously reduce a fabrication cost of the integrated circuit100.