Semiconductor memory device and fabrication method thereof using damascene bitline process

A semiconductor memory device includes a silicon substrate with a gate and contact pads at both sides of the gate, an inter-insulation layer formed on the substrate, including a storage node contact and a bit-line contact exposing a corresponding contact pad, and including a groove-shaped bit-line pattern, a storage node contact plug formed in the storage node contact, and a damascene bit line formed within the bit-line pattern and connected with the exposed corresponding contact pad through the bit-line contact.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device and a fabrication method that includes forming a bit-line with a damascene process after a storage node contact formation. This prevents bridge failures caused by voids and reduces a leakage current.

2. Description of the Related Art

Generally, as the size of a semiconductor memory device decreases, the cell pitch is correspondingly reduced. The reduction in pitch causes problems such as voids due to gap-fill failures in an inter-insulation layer, bridge failures between the storage node contacts due to the voids, and leakage current between the bit-line and the storage node contact due to scaling down the size of the bit-line spacer.

FIGS. 1A,2A,3A, and4A are cross-sectional views andFIGS. 1B,2B,3B, andFIG. 4Bare corresponding plan views illustrating a fabrication method of a conventional semiconductor memory device.FIGS. 1A and 2Aare cross-sectional views taken along the line IA—IA ofFIG. 4B, andFIGS. 3A and 4Aare cross-sectional views illustrating the relation between a bit-line and a storage node contact of the prior semiconductor memory device having a plan structure of FIG.4B.

Referring toFIGS. 1A and 1B, a silicon substrate100includes a field region101and an active region105, and a conventional shallow trench isolation STI process is performed to form a field isolation region110in the field region101of the silicon substrate100. Gates120crossing the active region105are formed on the silicon substrate100. In other words, on the silicon substrate100, a gate insulation layer121, a polysilicon layer123, a tungsten (W) layer125, and a cap nitride layer127are deposited sequentially and patterned using a gate mask (not shown) to form the gates120. Furthermore, a gate spacer130, such as a nitride layer, is formed on the sidewall of each gate120.

Referring toFIGS. 2A and 2B, a first inter-insulation layer140on the silicon substrate100and a conventional self-aligned contact process is performed to form self-aligned contacts (SACs)150. A conductive layer for a SAC contact pad, for example a polysilicon layer, is deposited, and a chemical mechanical polishing (CMP) process or an etch-back process is performed to form SAC contact pads160in the SACs150, respectively. Sequentially, a second inter-insulation layer170is deposited on the silicon substrate100and patterned to form a bit-line contact175to expose the corresponding contact pad of the SAC contact pads160which is to be connected with a bit-line in the following process.

Referring toFIGS. 3A and 3B, a conductive layer for a bit line and a capping insulation layer, such as a nitride layer, are deposited on the silicon substrate100. The conduction layer and the capping insulation layer are patterned to form a bit-line180that includes a capping layer185. The bit-line180is connected with the corresponding SAC contact pad160through the bit-line contact175.

Referring toFIGS. 4A and 4B, a third inter-insulation layer190is deposited on the substrate100and the third inter-insulation layer190and the second inter-insulation layer170are patterned to form a storage node contact195. The storage node contact195exposes the corresponding contact pad of the SAC contacts pads. Even though not shown in the drawings, a conventional capacitor fabrication process is performed to form a capacitor connected with the corresponding SAC contact pad160through the storage node contact195, thereby fabricating a conventional dynamic random access memory (DRAM) device.

However, the conventional DRAM device fabrication method has the problems of reduction in a thickness of the bit-line spacer due to reduction in a cell pitch, and a leakage current between the bit-line180and the storage node contact195due to the thickness reduction of the bit-line spacer. In more, the conventional DRAM device fabrication method also has the problems of a void due to a gap-fill fail in the third inter-insulation layer190, a bridge fail between the storage node contacts195due to the void, and a reduction of the overlay margin of the storage node contact195.

Embodiments of the invention address these and other problems in the prior art.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings.

FIGS. 5Ato13A andFIGS. 10Cto13C are cross-sectional views taken along the line IIA—IIA and the line IIC—IIC, respectively, ofFIG. 13B, illustrating a fabrication method of a semiconductor memory device according to an embodiment of the invention.FIGS. 5Bto13B are plan views illustrating a fabrication method of the semiconductor memory device of an embodiment of the invention.

Referring toFIGS. 5A and 5B, a silicon substrate200includes a field region201and an active region205. A conventional shallow trench isolation STI process is performed to form an STI field isolation210. The field isolation210isolates the active region205from the adjacent active region205.

Referring toFIGS. 6A and 6B, an oxide layer is formed on the substrate200through a sacrifice oxidation process and a nitride layer is deposited on the oxide layer. Using a gate mask (not shown), the nitride layer and the oxide layer are patterned to form sacrifice gates220including a sacrifice gate insulation layer (not shown). The sacrifice gates220cross the active region205, and they have the same shape as gates formed in a subsequent process. With the sacrifice gate formation, openings225are formed to expose portions of the active region205where contact pads will be located.

Referring toFIGS. 7A and 7B, on the exposed portions of the active regions205a silicon layer is grown through an anisotropic selective epitaxial process to form contact pads230within the openings225. Instead of a selective epitaxial growth, a polysilicon layer is deposited on the substrate200and then etched through a CMP process or an etch-back process to form the contact pads230. Then, a first inter-insulation layer240is deposited on the silicon substrate200and the CMP process is performed to planarize the silicon substrate200.

The first inter-insulation layer240is formed after contact pad formation to prevent a bridge fail between the pads230due to a void of the first inter-insulation layer. Furthermore, an open fail due to a reduction of the contact open area is prevented and a contact resistance is decreased due to a reduction of the contact area between the active region and the contact pad and surface treatment.

Referring toFIGS. 8A and 8B, by removing the sacrifice gates220including a sacrifice gate insulation layer, openings245are formed. An oxide layer250is grown on the substrate200through a thermal oxidation process and a gate electrode material is deposited on the oxide layer250. The gate electrode material and the oxide layer are etched through a CMP process to form damascene gates260within the openings245which are formed by removing the sacrifice gates220. A portion of the oxide layer250formed on the bottom of the gate260is a gate insulation layer251, and a portion of the oxide layer250formed on the sidewall of the gate260is a gate space253r. The gate260can have various structures such as a stack of a polysilicon layer and a metal layer of tungsten, a single metal layer of tungsten, or a stack of a polysilicon layer and a silicide layer. Instead of the thermal oxide layer250, an oxide layer or a high dielectric layer, such as aluminum oxide Al2O3, hafnium oxide HfO2, Zirconium oxide ZrO2, or tantalum oxide Ta2O5may alternatively be deposited through a deposition process.

In the embodiment, the gate insulation layer and the gate spacer including the oxide layer250are formed simultaneously through a thermal oxidation process or a deposition process. Therefore, because the gate spacer is a thermal oxide layer or a high dielectric layer with excellent dielectric characteristics, a leakage current between the gate and the contact pad230can be prevented. At this time, the oxide layer250has a thickness of 10 to 200 Å. Of the oxide layer250, the gate insulation layer251and the gate spacer253have almost the same thickness, in other words, they are within a thickness difference of 7 nm. The thickness difference is caused by the oxidation rate due to the difference of the doping concentration between the contact pad230and the silicon substrate200exposed by the opening245in the thermal oxidation process. In other words, the thickness difference is caused by the step coverage between the contact pad230and the silicon substrate200in a deposition process.

Referring toFIGS. 9A and 9B, a portion of the gate260is etched-back and an insulation layer, such as an oxide layer or a nitride layer, is deposited. Sequentially, a CMP process is performed to form a capping layer265on the top of the gate260within the opening245. A second inter-insulation layer270is deposited on the silicon substrate200and patterned to form a storage node contact275exposing the corresponding contact pad of the contact pads which is to be connected with a capacitor in a subsequent process. Sequentially, a storage node contact plug280is formed by selectively growing a silicon layer in the storage node contact275through an anisotropic epitaxial growth as the SAC contact pad230. Otherwise, the storage node contact plug280may be formed by depositing a polysilicon layer on the substrate and then etching it through a CMP process or an etch back process.

In this embodiment of the invention, only the portion of the second inter-insulation layer270where the storage node contact275is to be formed is etched and then the contact plug280is formed. Therefore, the storage node contact is formed with a size larger than that of the prior art, and the overlay margin of the storage node contact is sufficiently ensured.

The cross-sectional length in the bottom of the storage node contact plug280is longer than that of the contact pad230. That is, the cross-sectional length of the storage node contact plug280in the bit-line direction of the line IIA—IIA of FIG.13B and the cross sectional length in the gate direction of the line IIC—IIC ofFIG. 13Bare longer than those of the contact pad230.

Referring toFIGS. 10Ato10C, a portion of the second inter-insulation layer270where a bit-line is to be formed in a subsequent process is etched to form a bit-line pattern290that has a grooved shape. In other words, the second inter-insulation layer270is etched through a SAC process to form a bit-line pattern290that has a grooved shape and crosses the gate260.

Referring toFIGS. 11Ato11C, an insulation layer300for a bit-line spacer is formed on the substrate200. An oxide layer is formed by a thermal oxidation process or a deposition process or a high dielectric layer is deposited by a deposition process to form the insulation layer300. Sequentially, the second inter-insulation layer270is etched through a SAC process to form a bit-line contact310. The bit line contact310exposes the corresponding contact pad of the contact pads230that are connected to a bit line in a subsequent process.

Referring toFIGS. 12Ato12C, a conductive material for a bit-line is deposited on the silicon substrate and etched through a CMP process to form the bit-line320within the groove-shaped bit-line pattern290. The bit-line320crosses the gate260and connects with the corresponding contact pad230through the bit-line contact310.

Referring toFIGS. 13Ato13C, the bit line320is etched back by a predetermined thickness. An insulation layer such as a nitride layer is deposited on the silicon substrate and etched through a CMP process to form a bit-line capping layer330on the etched portion of the bit-line320with the bit-line pattern290. The cross sectional length of the bit-line capping layer330in the gate line direction is longer than that of the bit-line320in the gate line direction as shown in FIG.13C.

Although not shown in the drawings, a capacitor is then formed to connect with the storage node contact plug280, thereby fabricating a DRAM device according to this embodiment of the invention.

FIGS. 14Ato14C illustrate a fabrication method of a semiconductor memory device according to another embodiment of the invention, whereinFIG. 14Ais a cross sectional view taken along the line IIIA—IIIA of FIG.14B andFIG. 14Cis a cross sectional view taken along the line IIIC—IIIC of FIG.14B.

In this embodiment of the invention, the fabrication process up until the contact pad formation process is the same as the SAC contact pad formation process of the conventional DRAM fabrication process, and the bit-line formation process and the storage node contact pad formation process are the same as the process of the earlier-described embodiment of the invention.

With reference toFIGS. 14A,14B, and14C, on a silicon substrate400including a STI field isolation401and an active region405, gates420having a stack structure that includes a gate insulation layer421, a gate electrode material423, and a gate gapping layer427are formed. A gate spacer430of a nitride layer is in the sidewall of the gate420is formed.

A first inter-insulation layer440is deposited on the substrate400and a CMP process is performed to planarize the silicon substrate400. The first inter-insulation layer440is etched through a SAC process to form SAC contacts450and SAC contact pads460are formed in the SAC contacts450. A second inter-insulation layer470is deposited on the substrate400and etched to form a storage node contact475exposing the corresponding contact pad of the SAC contact pads460which is connected with a storage node in ta subsequent process. A storage node contact plug480is formed in the storage node contact475.

A portion of the second inter-insulation layer470where a bit line is to be formed is etched to form a groove-shaped bit-line pattern490. An insulation layer500for a bit-line spacer is formed on the substrate. The insulation layer500is an oxide layer or a high dielectric layer is formed by a thermal oxidation process or by a deposition process. The second inter-insulation layer470is etched to form a bit-line contact510to expose the corresponding contact pad of the SAC contact pads460that is to be connected with a bit-line. A damascene bit-line520is formed within the bit-line pattern490through a damascene bit-line process, and is connected with the contact pad460for a bit-line through the bit-line contact510. Sequentially, a portion of the bit-line520is etched and a bit-line capping layer530is formed at the etched portion of the bit-line520. Although not shown in the drawings, a subsequent storage node fabrication process is performed to fabricate a capacitor, thereby forming a semiconductor memory device according to another embodiment of the present invention.

As described above, according to embodiments of the invention, it is possible to prevent a void and a bridge fail due to a gap-fill fail in an inter-insulation layer by the size reduction of the DRAM device. Furthermore, a leakage current between the storage node contact and the bit-line, and between the gate and the contact pad, can be prevented. A sufficient overlay margin in the storage node contact and the bit-line contact can be ensured, an open fail is prevented, and a contact resistance is reduced.

Embodiments of the invention will now be described in a non-limiting way. Embodiments of the present invention provide a semiconductor memory device and a fabrication method thereof forming a storage node contact before a bit-line contact formation to increase the size of a storage node contact, thereby reducing a contact resistance and increasing an overlay margin.

Embodiments of the invention provide a semiconductor memory device and a fabrication method thereof forming a damascene bit-line to prevent a bridge fail by a void in an inter-insulation layer.

Embodiments of the invention provide a semiconductor memory device and a fabrication method thereof having a bit-line spacer with a high dielectric material to prevent a leakage current between a bit-line and a storage node contact.

Embodiments of the invention provide a semiconductor memory device and a fabrication method thereof using a damascene gate process and a silicon epitaxial process to prevent a bridge between pads due to a void in an inter-insulation layer.

Embodiments of the invention provide a semiconductor memory device and a fabrication method thereof forming a gate spacer with a high dielectric material to prevent a leakage current between a gate and an SAC contact pad.

Embodiments of the invention provide a semiconductor memory device and a fabrication method thereof preventing an increase of a contact resistance due to reduction of an open area and surface treatment, and preventing a contact open fail.

Embodiments of the invention provide a semiconductor memory device and a fabrication method thereof for ensuring a sufficient overlay margin of a bit-line contact.

Some embodiments of the invention provide a semiconductor memory device that includes a silicon substrate including a gate and contact pads at the both sides of the gate; a second inter-insulation layer formed on the substrate, including a storage node contact and a bit-line contact, the second inter-layer insulation layer exposing a corresponding contact pad, and including a groove-shaped bit-line pattern; a storage node contact plug formed in the storage node contact; and a damascene bit line, formed with the bit-line pattern, connected with the exposed corresponding contact pad through the bit-line contact.

Preferably, both the contact pad and the storage node contact plug are either an epitaxial silicon layer or a polysilicon layer. The gate is extended in a first direction, and the bit-line is extended in a second direction crossing the gate; and the cross sectional lengths of the bottom of the storage node contact plug in the first direction and the second direction are longer than the cross sectional lengths of the contact pad in the first direction and in the second direction.

The bit-line includes an insulation layer formed within the bit-line pattern, a bit-line material filling within the bit-line pattern including the insulation layer; and a capping layer formed on the top of the bit-line material within the bit-line pattern. The insulation layer functions as a bit-line spacer for insulating the bit-line and the storage node contact plug. The material of the insulation layer is different from the material of the capping layer, and the cross sectional length of the capping layer in the first direction is longer than the cross sectional length of the bit-line in the first direction. The insulation layer is a thermal oxide layer or high dielectric layer and the capping layer is a nitride layer.

The substrate includes a gate, the gate having a stack structure that includes a gate insulation layer, a gate material, and a capping layer, and a spacer in the sidewall thereof. The substrate also includes a first inter-insulation layer including self-aligned contacts exposing the silicon substrate at both sides of the gate and contact pads formed in the self-aligned contacts, respectively.

The substrate includes: the contact pads formed on the silicon substrate; the damascene type gate having a capping layer thereon, formed between the contact pads; an insulation layer formed on the bottom and the sidewall of the damascene gate; and a first inter-insulation layer formed on the silicon substrate to expose the contact pads and the capping layer. The thickness difference between portions of the insulation layer at the bottom and at the sidewall of the gate is within 7 nm; the portion of the insulation layer formed at the bottom of the gate functions as a gate insulation layer; and the portion of the insulation layer formed at the sidewall of the gate functions as a gate spacer.

Another embodiment of the invention provides a fabrication method of a semiconductor memory device including the processes of providing a silicon substrate including a gate and contact pads, forming a second inter-insulation layer on the silicon substrate, etching the second inter-insulation layer to form a storage node contact exposing a corresponding contact pad of the contact pads, forming a contact plug in the storage node contact, etching the second inter-insulation layer to form a groove-shaped bit-line pattern, etching the second inter-insulation layer to form a bit-line contact exposing a corresponding contact pad of the contact pads, and forming a damascene bit-line within the bit-line pattern that is connected with the corresponding contact pad through the bit-line contact.

The capping layer formation method includes the processes of etching back a portion of the insulation layer and the bit-line material within the bit-line pattern, depositing a nitride layer on the silicon substrate, and etching the nitride layer through a chemical mechanical polishing (CMP) process to form the capping layer.

The process of providing the substrate including the gate and the contact pads includes forming a gate having a stack structure that includes a gate insulation layer, a gate insulation material and a capping layer on a silicon substrate and a spacer at the sidewall of the gate. The process also includes forming a first inter-insulation layer on the silicon substrate, etching the first insulation layer to form SAC contacts exposing the silicon substrate at the both sides of the gate, and forming contact pads in the SAC contacts.

The process of providing the substrate including the gate and the contact pads includes forming a sacrifice gate including a sacrifice gate insulation layer on a silicon substrate, forming contact pads on the silicon substrate at both sides of the gate, forming a first inter-insulation layer on substrate to expose the contact pads and the sacrifice gate, removing the exposed sacrifice gate to form an opening exposing the silicon substrate, and forming a gate including an insulation layer in a bottom and a sidewall of the opening and a capping layer on the top thereof.