CHIP PACKAGE AND METHOD FOR FORMING THE SAME

A chip package is provided. The chip package includes a first semiconductor chip, a second semiconductor chip, a first encapsulating layer, a second encapsulating layer, a first through-via, and a second through-via. The second semiconductor chip is stacked on the first semiconductor chip, and the first encapsulating layer and the second encapsulating layer surround the first semiconductor chip and the second semiconductor chip, respectively. In addition, the first through-via and the second through-via penetrate the first encapsulating layer and the second encapsulating layer, respectively, and the second through-via is electrically connected between the second semiconductor chip and the first through-via. A method for forming the chip package are also provided.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to package technology, and in particular to a chip package and a method for forming the same.

Description of the Related Art

Optoelectronic devices (e.g., image-sensing devices) play an important role in capturing images and have been widely used in electronic products such as digital cameras, digital video recorders, and mobile phones. The chip packaging process is an important step in the fabrication of an electronic product. Chip packages not only protect sensing chips from outside environmental contaminants, but they also provide electrical connection paths between the electronic elements inside and those outside of the chip packages.

With the increase of functions and reduction of size of electronic products, system-in-package (SiP) technology has become an important technology to integrate different types of electronic devices (e.g., logic chips, sensing chips, memory chips, etc.) into a single package. Moreover, due to the rapid development of artificial intelligence (AI), heterogeneous integration has become an important trend in AI chips. SiP technology for heterogeneous integration can improve system performance while reducing chip size, power consumption, and manufacturing costs.

BRIEF SUMMARY OF THE INVENTION

An embodiment of the invention provides a chip package that includes: a first semiconductor chip having a first surface and a second surface opposite the first surface; a second semiconductor chip stacked on the second surface and having a third surface facing the second surface and a fourth surface opposite the third surface; a first encapsulating layer surrounding the first semiconductor chip; a second encapsulating layer surrounding the second semiconductor chip; a first through-via penetrating through the first encapsulating layer; and a second through-via, penetrating through the second encapsulating layer and electrically connected between the second semiconductor chip and the first through-via.

An embodiment of the invention provides a chip package that includes: a first semiconductor chip having a first surface and a second surface opposite the first surface; a second semiconductor chip stacked on the second surface and having a third surface facing the second surface and a fourth surface opposite the third surface; a first encapsulating layer surrounding the first semiconductor chip, wherein a portion of the first encapsulating layer extends over the first surface; a second encapsulating layer surrounding the second semiconductor chip, wherein a portion of the second encapsulating layer extends between the second surface and the third surface; a first through-via penetrating through the first encapsulating layer; a second through-via penetrating through the second semiconductor chip; and a third through-via penetrating through the portion of the second encapsulating layer, and electrically connected between the first through-via and the second through-via.

An embodiment of the invention provides a method for forming a chip package that includes: forming a first redistribution layer and a conductive bump on a transparent substrate, wherein the conductive bump is formed on the first redistribution layer; bonding a first semiconductor chip to the first redistribution layer via the conductive bump; forming a first encapsulating layer on the transparent substrate and covering the first semiconductor chip; forming a second redistribution layer on the first encapsulating layer, and forming a first through-via penetrating through the first encapsulating layer and electrically connected between the first redistribution layer and the second redistribution layer; stacking a second semiconductor chip on the first encapsulating layer on the first semiconductor chip; forming a second encapsulating layer on the first encapsulating layer and covering the second semiconductor chip; and forming a third redistribution layer on the second encapsulating layer, and forming a second through-via to penetrate through the entire second encapsulating layer and electrically connected to the second redistribution layer.

An embodiment of the invention provides a method for forming a chip package that includes: forming an insulating dam structure on a transparent substrate; bonding a first semiconductor chip to the transparent substrate via the insulating dam structure, wherein the first semiconductor chip has a first through-via corresponding to the dam structure and wherein a first redistribution layer is on the first semiconductor chip and electrically connected to the first through-via; forming a first encapsulating layer on the transparent substrate and covering the first semiconductor chip; forming a second redistribution layer on the first encapsulating layer, and forming a second through-via through a portion of the first encapsulating layer and electrically connected between the first redistribution layer and the second redistribution layer; stacking a second semiconductor chip on the first encapsulating layer above the first semiconductor chip; forming a second encapsulating layer on the first encapsulating layer and covering the second semiconductor chip; and forming a third redistribution layer on the second encapsulating layer, and forming a third through-via penetrating through the entire second encapsulating layer and electrically connected between the third redistribution layer and the second redistribution layer.

An embodiment of the invention provides a method for forming a chip package that includes: bonding a first semiconductor chip to a carrier substrate, wherein the first semiconductor chip has a first through-via and a first redistribution layer extending over the first semiconductor chip and electrically connected to the first through-via; forming a first encapsulating layer on the carrier substrate and covering the first semiconductor chip; forming a second redistribution layer on the first encapsulating layer, and forming a second through-via through a portion of the first encapsulating layer and electrically connected between the first redistribution layer and the second redistribution layer; stacking a second semiconductor chip on the first encapsulating layer on the first semiconductor chip; forming a second encapsulating layer on the first encapsulating layer and covering the second semiconductor chip; forming a third redistribution layer on the second encapsulating layer, and forming a third through-via penetrating through the entire second encapsulating layer and electrically connected between the third redistribution layer and the second redistribution layer; and removing the carrier substrate.

DETAILED DESCRIPTION OF THE INVENTION

The making and using of the embodiments of the present disclosure are discussed in detail below. However, it should be noted that the embodiments provide many applicable inventive concepts that can be embodied in a variety of specific methods. The specific embodiments discussed are merely illustrative of specific methods to make and use the embodiments, and do not limit the scope of the disclosure. In addition, the present disclosure may repeat reference numbers and/or letters in the various embodiments. This repetition is for the purpose of simplicity and clarity, and does not imply any relationship between the different embodiments and/or configurations discussed. Moreover, when a first material layer is referred to as being on or overlying a second material layer, the first material layer may be in direct contact with the second material layer, or separated from the second material layer by one or more material layers.

A chip package according to some embodiments of the present disclosure may be used to package micro-electro-mechanical system chips. However, embodiments of the invention are not limited thereto. For example, the chip package of the embodiments of the invention may be implemented to package active or passive devices or electronic components of integrated circuits, such as digital or analog circuits. For example, the chip package is related to optoelectronic devices, micro-electro-mechanical systems (MEMS), biometric devices, micro fluidic systems, and physical sensors measuring changes to physical quantities such as heat, light, capacitance, pressure, and so on. In particular, a wafer-level package (WSP) process may optionally be used to package semiconductor chips, such as image-sensor elements, light-emitting diodes (LEDs), solar cells, RF circuits, accelerators, gyroscopes, fingerprint recognition devices, micro actuators, surface acoustic wave devices, pressure sensors, ink printer heads, and so on.

The above-mentioned wafer-level package process mainly means that after the packaging step is accomplished during the wafer stage, the wafer with chips is cut to obtain individual packages. However, in a specific embodiment, separated semiconductor chips may be redistributed on a carrier wafer and then packaged, which may also be referred to as a wafer-level package process. In addition, the above-mentioned wafer-level package process may also be adapted to form a chip package having multi-layer integrated circuit devices by a stack of a plurality of wafers having integrated circuits.

Referring toFIG.2, which illustrates a cross-sectional of a chip package10in accordance with some embodiments of the present disclosure. The chip package10has a heterogeneous integrated structure and includes semiconductor chips200and300, encapsulating layers110and120, through-vias112a,122a,and122c.In some embodiments, the semiconductor chip200is an image-sensing chip, such as a CMOS image sensor (CIS) chip. The semiconductor chip200has two opposing surfaces200aand200b.The surface200a(e.g., the upper surface) is an active surface of the semiconductor chip200and the surface200b(e.g., the lower surface) is a non-active surface of the semiconductor chip200. The semiconductor chip200includes a sensing area (not shown). The sensing area may be adjacent to the surface200aof semiconductor chip200, and the sensing area includes a sensing device (not shown). For example, the sensing area has an image sensing device therein. In other some embodiments, the sensing area of semiconductor chip200includes a device for sensing biological features (e.g., a fingerprint recognition device), a device for sensing environmental features (e.g., a temperature sensing device, a humidity sensing device, a pressure sensing device, a capacitive sensing device), or other suitable sensing devices.

The semiconductor chip200includes an insulating layer201(as shown inFIG.1B) that has an upper surface defining as the surface200aof the semiconductor chip200. In some embodiments, the insulating layer201includes an interlayer dielectric (ILD) layer, an inter-metal dielectric (IMD) layer, a passivation layer, or a combination of thereof. In some embodiments, the insulating layer201includes an inorganic material, such as silicon oxide, silicon nitride, silicon nitride, metal oxide or a combination of thereof or other suitable insulating material.

In some embodiments, the insulating layer201has one or more conductive pads202therein (as shown inFIG.1B). In some embodiments, the conductive pad202is a single conductive layer or a multi-layer conductive structure. To simplify the diagram, only two conductive pads202with a single conductive layer are shown herein as an example. In some embodiments, the insulating layer201includes openings that expose the corresponding conductive pad202. In some embodiments, the sensing device in the sensing area is electrically connected to the conductive pads202through the interconnect structure (not shown) within the substrate of the semiconductor chip200and the insulating layer201.

In some embodiments, the semiconductor chip200further comprises an optical component203(as shown inFIG.1B) disposed on the insulating layer201and corresponding to the sensing area. In some embodiments, the optical component203includes a microlens array, a filter layer, a combination thereof, or another suitable optical component.

In some embodiments, the semiconductor chip300in the chip package10has two opposing surfaces300aand300b.The surface300a(e.g., the lower surface) is an active surface of the semiconductor chip300and the surface300b(e.g., the upper surface) is a non-active surface of the semiconductor chip300. Moreover, the semiconductor chip200is stacked on the surface300bof semiconductor chip300, and the surface200aof the semiconductor chip200faces the surface300bof semiconductor chip300. In some embodiments, the semiconductor chip300is an artificial intelligence (AI) chip. In those cases, when the semiconductor chip200is a CMOS image sensor (CIS) chip, the semiconductor chip300has a size larger than the size of semiconductor chip200. For example, the areas of surfaces300aand300bof semiconductor chip300are larger than the areas of surfaces200aand200bof semiconductor chip200.

Similarly, semiconductor chip300includes an insulating layer302(as shown inFIG.1D) having an upper surface that defines as a surface300aof semiconductor chip300. In some embodiments, the insulating layer302has the same or similar structure and material as those of the insulating layer201of semiconductor chip200. Moreover, the insulating layer302has one or more conductive pads301(as shown inFIG.1D) formed in the insulating layer302. In some embodiments, the conductive pad301is a single conductive layer or a multi-layer conductive structure. To simplify the diagram, only two conductive pads301with a single conductive layer are shown herein as an example. In some embodiments, the insulating layer302includes openings that expose the corresponding conductive pads301. In some embodiments, the conductive pads301can be electrically connected to the integrated circuit of the semiconductor chip300through the interconnect structure (not shown) within the substrate of the semiconductor chip300and the insulating layer302.

In some embodiments, the encapsulating layer110and120in chip package10surround corresponding semiconductor chips, respectively. For example, the encapsulating layer110surrounds the corresponding semiconductor chip200, and the encapsulating layer120surrounds the corresponding semiconductor chip300. In some embodiments, a portion of the encapsulating layer120extends over the active surface (e.g., surface300a) of semiconductor chip300. Similarly, a portion of the encapsulating layer110extends between the non-active surface (e.g., surface300b) of the semiconductor chip300and the non-active surface (e.g., surface200a) of the semiconductor chip200. In some embodiments, the encapsulating layers110and120include a molding compound material, which is made of epoxide, resin, or plasticizable polymer.

In some embodiments, the encapsulating layer120has openings121and123(as shown inFIG.1E) formed in the encapsulating layer120. The openings121penetrate through the entire encapsulating layer120and the openings123penetrate through the portion of the encapsulating layer120extending over the surface300aof the semiconductor chip300. Moreover, the through-vias122aand122cin the chip package10are formed in the openings121and123, respectively, and conformally extend on the sidewalls and bottom of the corresponding openings. The through-via122cis in direct contact with the corresponding conductive pad301, so as to be electrically connected to the semiconductor chip300. Similarly, the encapsulating layer110has openings111therein (as shown inFIG.1D). The opening111penetrates through the entire encapsulating layer110. Moreover, the through-via112ain the chip package10is formed in the opening111, and conformally extends on the sidewalls and bottom of the opening111.

In some embodiments, the chip package10further includes redistribution layers (RDLs)102,112b,and122beach having a fan-out structure. The redistribution layer102is formed on the encapsulating layer110and is electrically connected to the through-via122aand the conductive pad202of the semiconductor chip200via the conductive bumps104(e.g., micro bumps). The redistribution layer112bis formed between the encapsulating layer110and the encapsulating layer120and is electrically connected between the through-via112aand the through-via122a.The redistribution layer122bis formed below the encapsulating layer120. The redistribution layer122bis electrically connected between through-vias122aand122c.In some embodiments, the redistribution layer112bis formed from the same material layer as that of the through-via112a,and the redistribution layer122bis formed from the same material layer as those of the through-vias122aand122c.For example, the redistribution layers conformally extend to the sidewalls and bottom of the corresponding openings. Thereof, the redistribution layer formed within the opening is also referred to as the through-via. In some embodiments, the redistribution layers102,112b,and122binclude aluminum, titanium, tungsten, copper, or combinations thereof.

In some embodiments, the chip package10further includes a cover plate100disposed above the semiconductor chip200and covering the encapsulating layer110and the redistribution layers102to protect the optical components203. In some embodiments, the cover plate100may include glass, quartz, transparent polymer material or another suitable transparent material. Moreover, a portion of the encapsulating layer110extends between the semiconductor chip200and the cover plate100to cover the surface200bof the semiconductor chip200and expose the optical component203. As a result, the cover plate100, the encapsulating layer110and the semiconductor chip200together enclose a cavity above the sensing area, so that the optical component203is formed in the cavity.

In some embodiments, the chip package10further includes an adhesive layer116in direct contact with the non-active surface (e.g., surface300b) of the semiconductor chip300and the portion of the encapsulating layer110that extends over the surface200aof the semiconductor chip200, such that the semiconductor chip300is attached below the encapsulating layer110.

In some embodiments, the chip package10further includes a passivation layer130disposed on the active surface (e.g., surface300a) of the semiconductor chip300and filling openings121and123(indicated inFIG.1E). In some embodiments, the passivation layer130includes an epoxy resin, a solder mask, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, metal oxide, or a combination of thereof), an organic polymer material (such as polyimide, butylcyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons, or acrylates), or another suitable insulating material. In some embodiments, the passivation layer130does not fully fill the opening121, such that a hole131is formed under the passivation layer130in the opening121. During the thermal treatment in the manufacturing process, the hole131can be a buffer between the passivation layer130and through-via122a.Unwanted stress, which is induced between the passivation layer130and through-via122aas a result of mismatch of thermal expansion coefficients, is reduced. In one embodiment, the interface between the hole131and the passivation layer146has an arcuate contour.

In some embodiments, the passivation layer130has openings to expose portions of the redistribution layer122b.Moreover, the conductive structures134(e.g., solder balls, bumps, or conductive posts) are disposed on the active surface (e.g., surface300a) of the semiconductor chip300and electrically connected to the exposed redistribution layer122bthrough the openings in the passivation layer130. As a result, the conductive structures134are electrically connected to the through-vias122aand122c.In some embodiments, the conductive structures134include tin, lead, copper, gold, nickel, or a combination of thereof.

FIGS.1A to1Fare cross-sectional view of a method for forming a chip package10in accordance with some embodiments of the present disclosure. Elements inFIGS.1A to1Fthat are the same as those inFIG.2are labeled with the same reference numbers as inFIG.2and are not described again for brevity. Referring toFIG.1A, a substrate100W is provided. The substrate100W has chip regions and a scribe-line region surrounding these chip regions and separating adjacent chip regions. To simplify the diagram, only two complete chip regions D and a scribe-line region SL separating these chip regions D are depicted herein. In some embodiments, the substrate100W is a glass wafer to facilitate the wafer-level package process and serves as the cover plate100in the chip package10. Next, redistribution layers102and conductive bumps104are formed on the substrate100W, where the conductive bumps104are formed on the redistribution layers102.

Referring toFIG.1B, the semiconductor chip200is bonded onto the redistribution layers102of the corresponding chip region D via the conductive bumps104. In some embodiments, the semiconductor chip200includes an insulating layer201. The insulating layer201has one or more conductive pads202therein. In some embodiments, the semiconductor chip200further includes an optical component203disposed on the insulating layer201.

Referring toFIG.1C, an encapsulating layer110is formed on the substrate100W and covers the surface200aand sidewalls of the semiconductor chip200in each chip region D. Afterwards, openings111that penetrate through the encapsulating layer110are formed by an etching process or laser drilling process, to expose the redistribution layers102in each chip region D. In some embodiments, after forming the openings111, redistribution layers112bare formed on the encapsulating layer110in each chip region D, and through-vias112aare formed in the openings111in each chip region D. The through-via112ais electrically connected between the redistribution layer102and redistribution layer112b.In some embodiments, the redistribution layer112band the through-via112aare formed by depositing and patterning the same conformal metal layer.

Referring toFIG.1D, the semiconductor chip300is stacked on the semiconductor chip200in the corresponding chip region D by the adhesive layer116. For example, the adhesive layer116is attached to the non-active surface (e.g., surface300b) of the corresponding semiconductor chip300, and then is in directly contact with the portion of the encapsulating layer110extending over the surface200aof the semiconductor chip200, so that the semiconductor chip300is stacked on the corresponding semiconductor chip200. In some embodiments, the semiconductor chip300includes an insulating layer302having an upper surface that defines as the surface300aof semiconductor chip300. The insulating layer302has one or more conductive pads301therein.

Referring toFIG.1E, an encapsulating layer120is formed on the encapsulating layer110and in the openings111and covers the surface300aand sidewalls of the semiconductor chip300in each chip region D. Afterwards, openings121and123are formed in the encapsulating layer120by an etching process or laser drilling process, forming. The openings121penetrate through the entire encapsulating layer120, and the openings123penetrate through the portion of the encapsulating layer120extending over the surface300aof the semiconductor chip300. The openings121expose the redistribution layer112bon the encapsulating layer110in each chip region D, and the openings123exposes the conductive pads301of the semiconductor chip300in each chip region D.

In some embodiments, after forming openings121and123, the redistribution layer122bis formed on encapsulating layer120in each chip region D, and through-vias122aand122care respectively formed in openings121and123in each chip region D. The through-via122ais electrically connected to the exposed redistribution layer112b,and through-via122cis electrically connected to the conductive pad301of the semiconductor chip300. In some embodiments, the redistribution layer122band the through-vias122aand122care formed by depositing and patterning the same conformal metal layer.

Referring toFIG.1F, a passivation layer130is formed on the encapsulating layer120by a deposition process and fills the openings121and123of each chip region D (as shown inFIG.1F) to cover the redistribution layer122band through-vias122aand122c.In some embodiments, the passivation layer130fully fills the opening123and only partially fills the opening121, so that a hole131is formed in the opening121. Next, one or more openings can be formed in the passivation layer130in each chip region D by lithography and etching processes to expose portions of the redistribution layer122b.In some embodiments, a conductive structure134(e.g., a solder ball, a bump, or a conductive post) fills each of the openings in the passivation layer130by an electroplating process, a screen printing process, or another suitable process, to be electrically connected to the exposed portions of the redistribution layer122b.In some embodiments, the conductive structure134includes tin, lead, copper, gold, nickel, or a combination of thereof.

After forming the conductive structure134, the encapsulating layer120, the encapsulating layer110, and the substrate100W are successively diced along the scribe-line region SL. For example, a dicing process can be performed using a dicing saw or laser process. After performing the dicing process, an individual chip package10is formed, as shown inFIG.2.

Referring toFIG.4, which illustrates a cross-sectional view of the chip package10ain accordance with some embodiments of the present disclosure. Elements inFIG.4that are the same as those inFIG.2are labeled with the same reference numbers as inFIG.2and are not described again for brevity. In some embodiments, the structure of chip package10ais similar to the structure of chip package10inFIG.2. The difference is that the active surface (e.g., surface300a) of semiconductor chip300in chip package10afaces the non-active surface (e.g., surface200a) of semiconductor chip200. In those cases, the chip package10afurther includes one or more conductive structures305(e.g., bumps or conductive posts) disposed on the active surface of semiconductor chip300and electrically connected to the through-via112b.Moreover, the chip package10afurther includes an underfill layer306disposed between the encapsulating layer110and the semiconductor chip300. The underfill layer306surrounds the conductive structure305and is surrounded by the encapsulating layer120. In addition, since the active surface of semiconductor chip300is opposite to the conductive structure305, the chip package10adoes not have the through-vias122cas those in the chip package10.

FIGS.3A to3Dare cross-sectional view of a method for forming a chip package10ain accordance with some embodiments of the present disclosure. Elements inFIGS.3A to3Dthat are the same as those inFIGS.1A to1F and4are labeled with the same reference numbers as inFIGS.1A to1F and4and are not described again for brevity. Referring toFIG.3A, the structure as shown inFIG.1Bis provided. Next, an encapsulating layer110is formed on the substrate100W and covers the surface200aand sidewalls of the semiconductor chip200in each chip region D. Afterwards, openings111are formed to penetrate through the encapsulating layer110by an etching process or a laser drilling process, to expose the redistribution layers102in each chip region D. In some embodiments, after forming the opening111, redistribution layers112bare formed on the encapsulating layer110in each chip region D, and through-vias112aare formed in the openings111in each chip region D. The through-via112ais electrically connected between the redistribution layer102and redistribution layer112b.In some embodiments, the redistribution layer112band through-via112aare formed by depositing and patterning the same conformal metal layer. In other some embodiments, the pattern of the redistribution layers112bis the same as the pattern of the redistribution layers112bin chip package10. It is understood that the design of the pattern of the redistribution layers112bin chip package10adepends on the arrangement of the conductive structures305and is not limited to the embodiment shown inFIG.3A.

Referring toFIG.3B, the semiconductor chip300is stacked on the semiconductor chip200in the corresponding chip region D by the underfill layer306and the conductive structure305formed on each of the conductive pads301. For example, the conductive structures305are electrically connected to the corresponding redistribution layers112b,and the underfill layer306is in direct contact with the portion of the encapsulating layer110extending over the surface200aof the semiconductor chip200, so that the semiconductor chip300stacked on the corresponding semiconductor chip200. As a result, the active surface (e.g., surface300a) of semiconductor chip300faces the non-active surface (e.g., surface200a) of semiconductor chip200, and the conductive structures305are electrically connected between semiconductor chip300and redistribution layers112b.

Referring toFIG.3C, an encapsulating layer120is formed to cover the surface300band the sidewalls of the semiconductor chip300in each chip region D according to the method illustrated inFIG.1E, and openings121are formed in the encapsulating layer120. Moreover, according to the method illustrated inFIG.1E, redistribution layers122bare formed on the encapsulating layer120and through-vias122aare formed in the openings121.

Referring toFIG.3D, according to the method illustrated inFIG.1F, a passivation layer130is formed on the encapsulating layer120and fills the openings121in each chip region D. Moreover, according to the method illustrated inFIG.1F, a conductive structure134fills each opening in the passivation layer130to be electrically connected to the exposed portions of the redistribution layers122b.Afterwards, the encapsulating layer120, the encapsulating layer110and the substrate100W are successively diced according to the method described inFIG.1F. For example, a dicing process can be performed using a dicing saw or laser process. After performing the dicing process, an individual chip package10ais formed, as shown inFIG.4.

Referring toFIG.6, which illustrates a cross-sectional view of a chip package20in accordance with some embodiments of the present disclosure. Elements inFIG.6that are the same as those inFIG.2are labeled with the same reference numbers as inFIG.2and are not described again for brevity. In some embodiments, the structure of the chip package20is similar to the structure of the chip package10inFIG.2. The difference is that the chip package20has through-vias210apenetrating through the semiconductor chip200, and has through-vias112cpenetrating through the encapsulating layer110extending over the surface200aof the semiconductor wafer200. Unlike chip package10(which is electrically connected between semiconductor chip200and through-vias122aby using the through-vias112a), the chip package20is electrically connected between the semiconductor chip200and the through-vias122aby using the through-vias210aand112c.

FIGS.5A to5Fare cross-sectional view of a method for forming a chip package20in accordance with some embodiments of the present disclosure. Elements inFIGS.5A to5Fthat are the same as those inFIGS.1A to1F and6are labeled with the same reference numbers as inFIGS.1A to1F and6and are not described again for brevity. Referring toFIG.5A, a substrate100W is provided. The substrate W has two complete chip regions D and a scribe-line region SL separating these chip regions D. Next, a spacer layer (or is referred to as a dam)150is formed on the substrate100W in each chip region D. In some embodiments, the spacer layer150include an epoxy resin, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, metal oxide, or a combination thereof), an organic polymer material (such as polyimide, butylcyclobutene (BCB), parylene, polynaphthalenes, fluorocarbons, or acrylates), a photoresist material, or another suitable insulating materials.

Referring toFIG.5B, the semiconductor chip200is bonded to the spacer layer150in the corresponding chip region D. In some embodiments, the semiconductor chip200has openings211in the semiconductor chip200to expose conductive pads202disposed in the insulating layer201. Moreover, each through-via210ain the semiconductor wafer200is formed in each opening211and conformally extends to the sidewalls and bottom of the opening211to be electrically connected to the conductive pad202. Similarly, redistribution layers210bhave a fan-out structure and are formed on the surface200aof semiconductor chip200. In some embodiments, the redistribution layers210band the through-vias210aare made of the same material layer. For example, each redistribution layer conformally extends over the sidewalls and bottom of each opening211. Thereof, the portion of the redistribution layer formed in the opening211is also referred to as the through-via.

Referring toFIG.5C, an encapsulating layer110and openings113are formed according to the method illustrated inFIG.1C. The openings113expose the redistribution layers210bin the corresponding semiconductor chip200. According to the method illustrated inFIG.1C, redistribution layers112bare formed on the encapsulating layer110in each chip region D, and through-vias112care formed in the openings113in each chip region D, after forming the openings113. The through-vias112care electrically connected to the redistribution layers210b.In some embodiments, the redistribution layers112band the through-vias112care formed by depositing and patterning the same conformal metal layer.

Referring toFIG.5D, according to the method illustrated inFIG.1D, the semiconductor chip300is stacked on the semiconductor chip200in the corresponding chip region D via the adhesive layer116. For example, the adhesive layer116is attached to the non-active surface (e.g., surface300b) of the corresponding semiconductor chip300. The adhesive layer116is then in direct contact with the portion of the encapsulating layer110extending over the surface200aof the semiconductor chip200and fills in the openings113(indicated inFIG.5C), so that the semiconductor chip300is stacked on the corresponding semiconductor chip200.

Referring toFIG.5E, the encapsulating layer120and the openings121and123in the encapsulating layer120are formed according to the method illustrated inFIG.1E. The openings121expose the redistribution layers112band the openings123expose the conductive pads301of the corresponding semiconductor chip300. Moreover, according to the method illustrated inFIG.1E, redistribution layers122bare formed on the encapsulating layer120in each chip region D, and through-vias122aand122care respectively formed in the openings121and123in each chip region D.

Referring toFIG.5F, according to the method illustrated inFIG.1F, a passivation layer130is formed on the encapsulating layer120, a hole131is formed in each opening121, and conductive structures134are formed in the passivation layer130. Next, according to the method illustrated inFIG.1F, the encapsulating layer120, the encapsulating layer110, and the substrate100W are successively diced along the scribe-line region SL to form an individual chip package20, as shown inFIG.6.

Referring toFIG.8, which illustrates a cross-sectional view of a chip package20ain accordance with some embodiments of the present disclosure. Elements inFIG.8that are the same as those inFIGS.4and6are labeled with the same reference numbers as inFIGS.4and6and are not described again for brevity. In some embodiments, the structure of chip package20ais similar to the structure of chip package20inFIG.6. The difference is that the active surface (e.g., surface300a) of semiconductor chip300in chip package20afaces the non-active surface (e.g., surface200a) of semiconductor chip200. In those cases, the chip package20afurther includes one or more conductive structures305disposed on the active surface of semiconductor chip300and electrically connected to the through-vias112b.Moreover, the chip package20afurther includes an underfill layer306disposed between the encapsulating layer110and the semiconductor chip300. The underfill layer306surrounds the conductive structures305and is surrounded by the encapsulating layer120. In addition, since the active surface of the semiconductor chip300is opposite to the conductive structure305, the chip package20adoes not have the through-vias122cas those in the chip package20.

FIGS.7A to7Dare cross-sectional view of a method for forming a chip package20ain accordance with some embodiments of the present disclosure. Elements inFIGS.7A to7Dthat are the same as those inFIGS.5A to5F and6are labeled with the same reference numbers as inFIGS.5A to5F and6and are not described again for brevity. Referring toFIG.7A, the structure as shown inFIG.5Bis provided. Next, an encapsulating layer110is formed on the substrate100W and covers the surface200aand sidewalls of the semiconductor chip200in each chip region D. Afterwards, openings113are formed to penetrate through the portion of the encapsulating layer110extending over the surface200aof the semiconductor chip200by an etching process or a laser drilling process, to expose the redistribution layers210bin each chip region D. In some embodiments, after the openings113are formed, redistribution layers112bare formed on the encapsulating layer110in each chip region D, and through-vias112care formed in the openings113in each chip region D. The through-vias112care electrically connected to the redistribution layers210b.In some embodiments, the redistribution layers112band the through-vias112care formed by depositing and patterning the same conformal metal layer. In other some embodiments, the pattern of redistribution layers112bare the same as the pattern of redistribution layers112bin chip package20. It is understood that the design of the pattern of the redistribution layers112bin chip package20adepends on the arrangement of the conductive structures305and is not limited to the embodiment shown inFIG.7A.

Referring toFIG.7B, the semiconductor chip300is stacked on the semiconductor chip200in the corresponding chip region D by an underfill layer306and the conductive structure305formed on each of the conductive pads301. For example, the conductive structures305are electrically connected to the corresponding redistribution layers112b,and the underfill layer306is in direct contact with the portion of the encapsulating layer110extending over the surface200aof the semiconductor chip200, so that the semiconductor chip300is stacked on the corresponding semiconductor chip200. As a result, the active surface (e.g., surface300a) of semiconductor chip300faces the non-active surface (e.g., surface200a) of semiconductor chip200, and the conductive structures305are electrically connected between the semiconductor chip300and the redistribution layers112b.

Referring toFIG.7C, the encapsulating layer120and the openings121in the encapsulating layer120, the redistribution layers122bon the encapsulating layer120, and the through-vias122ain the openings121are formed according to the method illustrated inFIG.5E.

Referring toFIG.7D, a passivation layer130is formed on the encapsulating layer120and in the openings121, a conductive structure134is formed in each opening of the passivation layer130and electrically connected to the exposed redistribution layer122b, and the encapsulating layer120, the encapsulating layer110and substrate100W are successively diced according to the method illustrated inFIG.5F. After performing the dicing process, an individual chip package20ais formed, as shown inFIG.8.

Referring toFIG.10, which illustrates a cross-sectional view of the chip package30in accordance with some embodiments of the present disclosure. Elements inFIG.10that are the same as those inFIG.6are labeled with the same reference numbers as inFIG.6and are not described again for brevity. In some embodiments, the structure of the chip package30is similar to the structure of the chip package20inFIG.6. The difference is that the chip package30does not have a cover plate100disposed above the semiconductor chip200. Unlike the chip package20, the active surface (e.g., surface200b) of semiconductor chip200in chip package30is exposed to the external environment.

FIGS.9A to9Eare cross-sectional view of a method for forming a chip package30in accordance with some embodiments of the present disclosure. Elements inFIGS.9A to9Ethat are the same as those inFIGS.5A to5F and6are labeled with the same reference numbers as inFIGS.5A to5F and6and are not described again for brevity. Referring toFIG.9A, a carrier substrate400is provided. The carrier substrate400has chip regions and a scribe-line region surrounding these chip regions and separating adjacent chip regions. To simplify the diagram, only two complete chip regions D and a scribe-line region SL separating these chip regions D are depicted herein. In some embodiments, the carrier substrate400is made of silicon, glass, ceramic, or another suitable substrate material, and has a wafer shape to facilitate a wafer-level package process. For example, the carrier substrate400is a glass wafer and serves as a temporary support structure in the manufacture of the chip package30. Next, an adhesive layer160is formed on the carrier substrate400. In some embodiments, the adhesive layer160is made of a light-to-heat conversion (LTHC) material or another suitable material. Afterwards, a semiconductor chip200as shown inFIG.5Bis provided. The semiconductor chip200is bonded to the carrier substrate400in the corresponding chip region D by the adhesive layer160.

Referring toFIG.9B, an encapsulating layer110and openings113are formed according to the method illustrated inFIG.5C. The openings113expose the redistribution layers210bon the corresponding semiconductor chip200. According to the method illustrated inFIG.5C, redistribution layers112bare formed on the encapsulating layer110in each chip region D, and through-vias112care formed in the openings113in each chip region D. The through-vias112care electrically connected to the redistribution layers210b.

Referring toFIG.9C, a semiconductor chip300is stacked on a semiconductor chip200in the corresponding chip region D via an adhesive layer116according to the method illustrated inFIG.5D. For example, the adhesive layer116is attached onto the non-active surface (e.g., surface300b) of the corresponding semiconductor chip300, and then is in direct contact with the portion of the encapsulating layer110extending over the surface200aof the semiconductor chip200and fills in the openings113(indicated inFIG.9C), so that the semiconductor chip300is stacked on the corresponding semiconductor chip200.

Referring toFIG.9D, an encapsulating layer120and openings121and123in the encapsulating layer120are formed according to the method illustrated inFIG.5E. The openings121expose the redistribution layers112band the openings123expose the corresponding conductive pads301of the semiconductor chip300. Afterwards, according to the method illustrated inFIG.5E, redistribution layers122bare formed on the encapsulating layer120in each chip region D and through-vias122aand122care respectively formed in openings121and123in each chip region D.

Referring toFIG.9E, a passivation layer130is formed on the encapsulating layer120, a hole131is formed in each opening121, and conductive structures134are formed in the passivation layer130according to the method illustrated inFIG.5F. Afterwards, the semiconductor chips200and300surrounded by the encapsulating layers110and120are de-bonded from the carrier substrate400. In some embodiments, when the adhesive layer160is made of an LTHC material, the de-bonding process is performed by irradiating the adhesive layer160with laser light or UV light. Due to the heat generated by the laser or UV light, the LTHC material decomposes, and therefore the carrier substrate400is removed from the structure including the semiconductor chip200and300. Next, according to the method illustrated inFIG.5F, the encapsulating layer120and the encapsulating layer110are successively diced along the scribe-line region SL to form an individual chip package30, as shown inFIG.10.

Referring toFIG.12, which illustrates a cross-sectional view of the chip package30ain accordance with some embodiments of the present disclosure. Elements inFIG.12that are the same as those inFIG.8are labeled with the same reference numbers as inFIG.8and are not described again for brevity. In some embodiments, the structure of chip package30ais similar to the structure of chip package20ainFIG.8. The difference is that the chip package30adoes not have a cover plate100disposed above the semiconductor chip200. Unlike the chip package20a,the active surface (e.g., surface200b) of semiconductor chip200in chip package30ais exposed to the external environment.

FIGS.11A to11Dare cross-sectional view of a method for forming a chip package30ain accordance with some embodiments of the present disclosure. Elements inFIGS.11A to11Dthat are the same as those inFIGS.7A to7D and8are labeled with the same reference numbers as inFIGS.7A to7D and8and are not described again for brevity. Referring toFIG.11A, a carrier substrate400as shown inFIG.9Ais provided. The carrier substrate400has an adhesive layer160formed thereon. In some embodiments, the adhesive layer160is made of an LTHC material or another suitable material. Afterwards, a semiconductor chip200as shown inFIG.7Ais provided, and the semiconductor chip200is bonded to the carrier substrate400in the corresponding chip region D by the adhesive layer160. An encapsulating layer110and openings113are formed according to the method illustrated inFIG.7A. The openings113expose the redistribution layers210bon the corresponding semiconductor chip200. Afterwards, according to the method illustrated inFIG.7A, redistribution layers112bare formed on the encapsulating layer110in each chip region D, and through-vias112care formed in the openings113in each chip region D. The through-vias112care electrically connected to the redistribution layers210b.

Referring toFIG.11B, a semiconductor chip300is stacked on a semiconductor chip200in the corresponding chip region D by an underfill layer306and a conductive structure305formed on each conductive pad301, as described in the method ofFIG.7B.

Referring toFIG.11C, an encapsulating layer120and openings121in the encapsulating layer120, the redistribution layers122bon the encapsulating layer120, and the through-vias122bin the openings121are formed according to the method illustrated inFIG.7C.

Referring toFIG.11D, according to the method illustrated inFIG.7D, a passivation layer130is formed on the encapsulating layer120and in the opening121, and a conductive structure134is formed in each opening in the passivation layer130and electrically connected to the exposed redistribution layer122b.Afterwards, the semiconductor chips200and300surrounded by encapsulating layers110and120are de-bonded from the carrier substrate400. In some embodiments, when the adhesive layer160is made of an LTHC material, the de-bonding process is performed by irradiating the adhesive layer160with laser light or UV light to remove the carrier substrate400from the structure including the semiconductor chips200and300. Next, according to the method illustrated inFIG.7D, the encapsulating layer120and the encapsulating layer110are successively diced along the scribe-line region SL. After the dicing process, an individual chip package30ais formed, as shown inFIG.12.

According to the foregoing embodiments, since a portion of the encapsulating layer is employed to separate the top semiconductor chip from the bottom semiconductor chip, the distance between two such semiconductor chips can be increased, thereby reducing the parasitic capacitance between the semiconductor chips. Similarly, since a portion of the encapsulating layer is employed to separate the bottom semiconductor chip from the external conductive structures of the chip package (e.g., solder balls, bumps, or conductive posts), the distance between the semiconductor chip and the external conductive structures can be increased, thereby improving the electrical isolation between the semiconductor chip and the external conductive structures to reduce the leakage current of the chip package. As a result, the reliability of the chip package can be increased.

According to the foregoing embodiments, the semiconductor chips in the chip package with the heterogeneous integrated structure are arranged in a vertical stacking manner. Therefore, such a chip package can effectively reduce the form factor of the package as compared to the case where the semiconductor chips in the chip package are arranged in a side-by-side manner.

According to the foregoing embodiments, the through-vias formed in the encapsulating layer are employed to be electrically connected to the vertically stacked semiconductor chips in the chip package. Therefore, such a chip package can effectively reduce the manufacturing cost compared to the case where through-vias (e.g., through substrate vias or through silicon vias) formed in the semiconductor chip are employed to be electrically connected to the vertically stacked semiconductor chips.

While the invention has been disclosed in terms of the preferred embodiments, it is not limited. The various embodiments may be modified and combined by those skilled in the art without departing from the concept and scope of the invention.