Super halo implant combined with offset spacer process

A method for forming a semiconductor structure by using super halo implant combined with offset spacer process is disclosed. This invention comprises providing a substrate with a gate electrode formed thereon and a halo implant region formed therein. Then, a dielectric layer is deposited on the substrate and the gate electrode. Next, the semiconductor structure is annealed, and the dielectric layer is anisotropically etched to form an offset spacer.

BACKGROUND OF THE INVENTION
 1. Field of the Invention
 The present invention generally relates to a method for forming integrated
 circuits, and more particularly to a method for forming semiconductor
 device by using super halo implant combined with offset spacer process.
 2. Description of the Prior Art
 As MOS (Metal-Oxide-Semiconductor) device scaled down to sub-0.25 .mu.m, in
 order to maintain enough short channel margin, tilt angle halo implant is
 necessary. Unfortunately, the poly spacing is also shrunk, it dose
 strictly limit halo tilt angle. Thus, super halo process has been
 proposed. Super halo process uses zero angle halo implant after poly has
 been defined, then lateral diffusion is performed by using thermal anneal.
 Following description will set forth an exemplary process of super halo
 process with the aid of FIG. 1A to FIG. 1D.
 Referring to FIG. 1A, a substrate 100 is provided with gate oxide layer 120
 and poly gate 130 formed thereon. Thus, two gate electrodes formed in an
 active area defined in between the isolation regions (not shown in the
 FIGURE). The gate oxide layer 120 is a layer of insulation to separate
 poly gate 130 and substrate 100. Source and drain regions will be formed
 in the substrate 100 at opposite ends of the gate 130. A channel region
 under the gate electrode 130 is located between the source and drain
 regions in the substrate 100. Then, super halo implant is preformed to
 form implant regions 112, as shown in FIG. 1B. The implant regions 112 in
 the substrate 100 are placed to completely separate the source and drain
 regions from the channel regions for improving short channel effect. The
 implant step needs to be performed twice, one for NMOS and the other for
 PMOS, and then two masks and lithography processes are applied. After the
 super halo implant steps, such as anneals, cause the halo dopant diffuse
 toward the channel region.
 Subsequently, as shown in FIG. 1C, another implant occurs. This implant
 step is to form source/drain extension regions 114. The amount of dopant
 is controlled so that the dopant concentration is relatively low to source
 and drain regions, and the junction depth is controlled relative shallow
 to source/drain regions. Then, a thermal anneal is performed so that the
 dopant diffuses toward the area under gate electrode 130 and the gate to
 drain overlap will increase. Then, spacer 122 is formed on the sidewall of
 the gate 130, and again another implant is performed to form source/drain
 regions 116, as shown in FIG. 1D. The processes which follow are salicide
 process and backend process.
 By the way, the formulation of source/drain extension region and super halo
 implant must be separated because of shallow junction issue. It means that
 the super halo process needs to increase two mask steps (one for NMOS and
 the other for PMOS).
 SUMMARY OF THE INVENTION
 In accordance with the present invention, a method is provided for forming
 semiconductor devices that substantially combines super halo implant and
 offset spacer process. The super halo process in the present invention
 provides more lateral diffusion by combining offset spacer and can obtain
 better device performance for shorter channel margin.
 It is another object of this invention that super halo anneal can be
 replaced by offset spacer deposition temperature. Thus, the thermal cycle
 can be reduced.
 It is a further object of this invention to reduce the gate to drain
 overlap region to improve device performance in offset spacer process.
 In one embodiment, a method for forming a metal-oxide-semiconductor device
 by using super halo combined with offset spacer process is disclosed. The
 method includes first providing a substrate having a gate electrode formed
 thereon and a halo implant region formed therein. Secondly, a dielectric
 layer is deposited on the substrate and the gate electrode. Thirdly,
 anneal is performed so that dopant of halo implant will diffuse. Fourth,
 the dielectric layer is anisotropically etched to form an offset spacer.
 Fifth, source/drain extension regions are formed. Finally, a spacer is
 formed on the sidewall of the offset spacer beside the gate electrode, and
 source/drain regions are formed in the substrate.

DESCRIPTION OF THE PREFERRED EMBODIMENT
 Some sample embodiments of the present invention will now be described in
 greater detail. Nevertheless, it should be recognized that the present
 invention can be practiced in a wide range of other embodiments besides
 those explicitly described, and the scope of the present invention is
 expressly not limited except as specified in the accompanying claims.
 The semiconductor devices of the present invention are applicable to a
 broad range of semiconductor devices and can be fabricated from a variety
 of semiconductor materials. The following description discusses several
 presently preferred embodiments of the semiconductor devices of the
 present invention as implemented in silicon substrates, since the majority
 of currently available semiconductor devices are fabricated in silicon
 substrates and the most commonly encountered applications of the present
 invention will involve silicon substrates. Nevertheless, the present
 invention may also be advantageously employed in gallium arsenide,
 germanium, and other semiconductor materials. Accordingly, application of
 the present invention is not intended to be limited to those devices
 fabricated in silicon semiconductor materials, but will include those
 devices fabricated in one or more of the available semiconductor
 materials.
 Moreover, while the present invention is illustrated by a number of
 preferred embodiments directed to silicon semiconductor devices, it is not
 intended that these illustrations be a limitation on the scope or
 applicability of the present invention. Further, while the illustrative
 examples use insulated gate control structures, it should be recognized
 that the insulated gate portions may be replaced with light activated or
 current activated structure(s). Thus, it is not intended that the
 semiconductor devices of the present invention be limited to the
 structures illustrated. These devices are included to demonstrate the
 utility and application of the present invention to presently preferred
 embodiments.
 Further, various parts of the semiconductor elements have not been drawn to
 scale. Certain dimensions have been exaggerated in relation to other
 dimensions in order to provide a clearer illustration and understanding of
 the present invention. For the purposes of illustration the preferred
 embodiment of the semiconductor devices of the present invention have been
 shown to include specific P and N type regions, but it should be clearly
 understood that the teachings herein are equally applicable to
 semiconductor devices in which the conductivities of the various regions
 have been reversed, for example, to provide the dual of the illustrated
 device. Enhancement and depletion mode structures may be similarly
 interchanged.
 Further, although the embodiments illustrated herein are shown in two
 dimensional views with various regions having width and depth, it should
 be clearly understood that these regions are illustrations of only a
 portion of a single cell of a device, which may include a plurality of
 such cells arranged in a three-dimensional structure. Accordingly, these
 regions will have three dimensions, including length, width and depth,
 when fabricated in an actual device.
 In this invention, a method for forming semiconductor device comprises
 super halo implant combined with offset spacer process. By using this
 invention, on 0.18 .mu.m generation, the poly CD (critical dimension) can
 be reduced to 0.15 pim, and super halo implant can be adopted, too. Thus,
 we can obtain more lateral halo profile and larger poly spacing. Then,
 followed by offset spacer formation and source/drain extension
 implantation. The following will set forth the present invention with a
 preferred embodiment and the FIGS. 2A to 2E.
 Referring to FIG. 2A, a substrate 10 of a first conductivity type is
 provided with two gate electrodes formed thereon. The gate electrodes
 comprises a gate oxide layer 20 and a poly gate layer 30, in which gate
 oxide layer 20 is silicon oxide and poly gate 30 is polysilicon. The gate
 oxide layer is the layer of insulation to separate the substrate 10 and
 the poly gate 30. The method of forming the gate structure is to form a
 silicon oxide layer and a polysilicon layer sequentially and then to etch
 a portion of the polysilicon layer and the silicon oxide layer.
 The two gate electrodes formed here are in an active area defined in
 between the isolation regions (not shown in the FIGURE), and the CD can be
 0.15 .mu.m generation. Source and drain regions will be formed in the
 substrate 10 at opposite ends of the gate 30. A channel region under the
 gate electrode 30 is located between the source and drain regions in the
 substrate 10.
 Subsequently, as shown in FIG. 2B, an implant follows. This implant is halo
 implant. The implant regions 12 in the substrate 10 are placed to
 completely separate the source and drain regions from the channel regions
 for improving short channel effect. The dopant is a first conductivity
 type that is implanted to produce an intermediate concentration level. The
 dopant material for the halo implant is selected to be more diffusive than
 the dopant material of second conductivity type residing in the
 source/drain regions.
 Then, a blanket dielectric layer 22 is deposited on the substrate 10 and
 the gate structure 30 by using any conventional method, as shown in FIG.
 2C. The dielectric layer 22 is used to form offset spacer and has a
 thickness between about 100 to 500 angstroms. The material of this
 dielectric layer 22 is usually silicon oxide, and can be silicon nitride.
 Next, a thermal anneal is performed to make the halo dopant diffuse toward
 the channel region.
 Referring to FIG. 2D, an anisotropically etching is performed to form the
 offset spacer 22, and an implant then follows to form source/drain
 extension regions 14 by using the gate electrode 30 with the offset spacer
 22 as a mask. The anisotropically etching is any conventional method, such
 as RIE (Reactive Ion Etching), and this implant is of second conductivity
 type. The amount of dopant is controlled so that the dopant concentration
 is relatively low to source and drain regions, and the junction depth is
 controlled relative shallow to source/drain regions.
 Next, a spacer 24 is formed on the sidewall of the gate structure 30 with
 the offset spacer 22 by using the same method of forming offset spacer 22,
 and again another implant is performed to form source/drain regions 16, as
 shown in FIG. 2E. The source/drain regions 16 are of second conductivity
 type and the amount of dopant is controlled so that the dopant
 concentration is relatively high in respect to source/drain extension
 regions 14. The following processes are salicide process and backend
 process.
 In accordance with the present invention, the super halo implant provides
 more lateral diffusion by combining offset spacer and can obtain better
 device performance for shorter channel margin. Moreover, the super halo
 anneal can be replaced by offset spacer deposition temperature in this
 invention, and the thermal cycle can be reduced. Further, this invention
 reduces the gate to drain overlap region to improve device performance in
 offset spacer process.
 Although specific embodiments have been illustrated and described, it will
 be obvious to those skilled in the art that various modifications may be
 made without departing from what is intended to be limited solely by the
 appended claims.