Timing signal generator

A timing signal generator which can operate stably even when, or directly after, a power supply is switched on. The generator is of the type having a first dynamic delay circuit for generating a first timing signal in response to said input control signal and a second dynamic delay circuit for generating a second timing signal in response to the first timing signal, and is featured by a first transistor connected between the output of the first dynamic delay circuit and a voltage terminal with a gate connected to the input of the first dynamic delay circuit and a second transistor connected to the output of the second dynamic delay circuit and the voltage terminal with a gate connected to receive the first timing signal.

BACKGROUND OF THE INVENTION 
The present invention relates to a timing signal generator and more 
particularly to one suitable for a dynamic memory (DRAM). 
Dynamic memories have been utilized in various fields due to their large 
memory capacities. Dynamic memories operate under control of a basic, 
externally generated control signal. One of the important functions of the 
basic control signal is to control memory reset operations. 
In dynamic logic circuits, prior to any logic operation, circuit nodes are 
reset to establish the standby mode. In the standby mode, the circuit is 
made ready for the subsequent logic operation. In dynamic memories, a 
plurality of dynamic type functional blocks such as address buffers and 
address decoders are subjected to reset operations in predetermined timing 
sequences. For example, the address buffers are reset first to set the 
outputs therefrom at a low level and then NOR output nodes of the address 
decoders are reset to a high precharged level. By keeping the sequence of 
resets of the respective functional blocks in a predetermined order, the 
respective functional blocks can operate adequately, without malfunction, 
and at maximum speed when the memory is shifted to a read-out or write 
operation. In order to achieve the above sequence of reset operations for 
the functional blocks, a timing signal generator is employed in the 
memory. The timing signal generator generates a sequence of timing signals 
which control the reset operations of the respective blocks in response to 
a basic signal. However, the above sequence of reset operations is not 
maintained when, or directly after, a power supply to a memory is switched 
on, to shift the memory from a non-powered state to a powered state. In 
this instance, potential states of circuit nodes in the respective 
functional blocks are likely to be indefinite and unstable. Therefore, 
such circuit nodes are subjected to an initializing operation in order to 
set the circuit nodes at predetermined states. Namely, circuit conditions 
of the functional blocks must be set at predetermined initial states 
directly after the power voltage is turned on. Otherwise, the circuit 
operation will become incomplete and an abnormally large current is 
generated in the circuit. Such abnormal current sometimes causes the 
circuit to break down or do harm to other elements of the system or 
circuit board. 
In the initializing operation, a plurality of timing signals generated from 
a timing signal generator employed in a memory are also required to occur 
in a predetermined order. 
However, it has been difficult to achieve proper initializing operations 
when circuit node potentials are in the unstable state for the 
conventional timing signal generators may cause a timing abnormality in 
signal timing when, or immediately after, the power is switched on. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to present a timing signal 
generator which can generate a plurality of timing signals in a desired 
order even when power supply is switched on. 
It is another object of the present invention to provide a timing signal 
generator suitable for dynamic memories. 
The timing signal generator according to the present invention is of the 
type comprising a first delay circuit adapted to generate a first timing 
signal in response to an input control signal and a second delay circuit 
for generating a second timing signal in response to the first timing 
signal. The timing signal generator of the invention further comprises a 
first field effect transistor connected to the output terminal of the 
first delay circuit so as to supply it with a power voltage when the input 
control signal becomes high and a second field effect transistor connected 
to the output terminal of the second delay circuit so as to supply it with 
the power voltage when the first timing signal becomes high. 
According to the present invention, when the power supply is switched on, 
the first transistor becomes conducting first in response to the input 
control signal so that the first timing signal is generated. Then, in 
response to the generation of the first timing signal, the second 
transistor becomes conducting so that the second timing signal is 
generated. Thus, the first and second timing signals are generated in a 
desired order even when the power supply is switched on. 
The timing signal generator of the invention is useful not only for dynamic 
memories but also for dynamic logic circuits.

DETAILED DESCRIPTION OF THE INVENTION 
In the following explanation, N-channel MOS transistors are employed as 
transistors, and a power voltage V.sub.cc serves as a high level while 
ground potential serves as a low level. 
With reference to FIG. 1, the general structure of a dynamic memory will be 
briefly explained. 
The memory is the so-called multi-strobe type in which row address signals 
and column address signals are incorporated through the same set of 
address input terminals Ta to An in response to a row strobe signal RAS 
and a column strobe signal CAS in a time divisional way. A buffer 23 
receives RAS and generates an internal signal RASA. In response to RASA, a 
timing signal generator 20 generates timing signals .phi..sub.1 and 
.phi..sub.2 in a predetermined sequence. Namely, in response to a high 
level of RASA, the generator 20 produces the signal .phi..sub.1 first 
which controls a reset operation of the address buffer 11, and then 
produces the signal .phi..sub.2 for precharging the decoder 12 which is 
connected to word lines WL of a memory cell array 13. The array includes a 
plurality of memory cells MC at intersections of the word lines WL and 
digit lines DL in a known manner. A column timing signal generator 21 
receives CAS and an output signal of the timing signal generator 20 and 
generates timing signals .phi..sub.3 and .phi..sub.4 for controlling reset 
operations of a column address buffer 16 and a column decoder 15, 
respectively, and also generates a signal .phi..sub.c for controlling a 
read-write control signal generator 22. The generator 22 controls a switch 
circuit 17 which selectively connects a data output circuit 18 and a data 
input circuit 19 to a column selection circuit 14. 
In this memory, the signal RASA serves as a basic timing signal to control 
the whole memory directly and indirectly. The operations based on RASA 
will be explained hereinbelow. 
FIG. 2 shows a one bit structure of the buffer 11. A flip-flop F/F receives 
the address input Ao and generates its true signal ao and complementary 
signal ao. Here, transistors Q.sub.1 and Q.sub.2 are connected between the 
outputs ao, ao and a ground potential, respectively. The transistors 
Q.sub.1 and Q.sub.2 operatively clamp the outputs ao and ao to the ground 
potential in response to the timing signal .phi..sub.1 for resetting. 
FIG. 3 shows a one bit structure of the decoder 12. The decoder is 
basically composed of a NOR circuit including transistors Q.sub.4, 
Q.sub.5, Q.sub.6 receiving the outputs from the buffer 11 in a 
predetermined combination, a precharge transistor Q.sub.3 and a word line 
drive transistor Q.sub.7. Here, the time relation between the signal 
.phi..sub.1 and the signal .phi..sub.2 is determined such that the signal 
.phi..sub.2 will be at the high potential level after the reset signal 
.phi..sub.1 is at the high potential. If the signal .phi..sub.2 is at the 
high potential when the reset signal .phi..sub.1 is at the low potential, 
at least one of the OR transistors Q.sub.4, Q.sub.5, Q.sub.6 conducts 
because one of the outputs a.sub.i or a.sub.i is necessarily at the high 
potential. In this circumstance, it sometimes happens that when the signal 
.phi..sub.2 is produced, a large quantity of current flows through the 
address decoder so that a protection circuit of the power source is 
switched and the operation of the DRAM is stopped. 
FIG. 4 is a block diagram of a part of the conventional timing signal 
generator 20 in the DRAM. Delay circuits 31 and 32 are composed of dynamic 
logic circuits. The delay circuit 31 generates the signal .phi..sub.1 with 
a time lag of T.sub.1 with respect to the input signal RASA, and the delay 
circuit 32 generates the signal .phi..sub.2 with a time lag of T.sub.2 
with respect to the signal .phi..sub.1. Transistors Q.sub.10 and Q.sub.11 
are pull-up transistors for initializing the states of .phi..sub.1 and 
.phi..sub.2. 
The current capacity of transistors Q.sub.8 and Q.sub.9 is made about 100 
times that of the Q.sub.13. In the quiescent state, signals P.sub.1 and 
P.sub.2 are complementary to each other so that one of the transistors 
Q.sub.8 and Q.sub.9 conducts while the other is cut off. Therefore, in the 
quiescent state the level of the signal .phi..sub.2 is dependent on the 
signals P.sub.1 and P.sub.2, which are, in turn, determined solely by the 
signal .phi..sub.1. 
At the time of turning on the power voltage, however, the level of the 
signal RASA is uncertain and may be either high or low level and the 
levels of the signals P.sub.1 and P.sub.2 are indefinite. Therefore, the 
signals .phi..sub.1 and .phi..sub.2 are set comparatively slowly to a high 
level by the pull-up transistors Q.sub.10 and Q.sub.13. Since the gates of 
the pull-up transistors Q.sub.10 and Q.sub.13 are conncted to the 
terminals of the power source, the characteristics of the transistors 
Q.sub.10 and Q.sub.13 and their loads determine which one of the signals 
.phi..sub.1 and .phi..sub.2 will rise first in potential when the power 
voltage is switched on. However, to accurately obtain the necessary 
manufacturing characteristics relative to the pull-up transistors Q.sub.10 
and Q.sub.13, particularly current capacity, and to conveniently determine 
the load, are extremely difficult if not impossible. Therefore, an 
abnormality in timing between the signals may occur with the effect that 
the signal .phi..sub.2 may become high earlier than the signal 
.phi..sub.1. As described above, this timing abnormality disadvantageously 
leads to excessive current supply. 
An embodiment of the invention will now be described with reference to FIG. 
5. According to the invention, the gate of the transistor Q.sub.10', which 
is analogous to transistor Q.sub.10 of FIG. 4, is connected to receive the 
signal RASA and the gate of the transistor Q.sub.13', which is analogous 
to the transistor Q.sub.13 of FIG. 4, is connected to the output 
(.phi..sub.1) of the delay circuit 31. Here, RASA is the signal which 
takes a high level during at least a part of the stand-by period after the 
power is switched on. 
Therefore, the signal .phi..sub.1 rises in potential first in response to a 
high level of RASA applied to the delay circuit 31 and gate of transistor 
Q.sub.10'. Then, in response to the rise of .phi..sub.1, the transistor 
Q.sub.13' becomes conducting to raise .phi..sub.2 to a high level directly 
after the power is switched on. In this instance, the states of the delay 
circuits 31 and 32 are unstable and cannot properly drive their outputs. 
Accordingly, the transistor Q.sub.13, never conducts unless the reset 
signal .phi..sub.1 assumes the high level. Consequently, when initializing 
immediately after turning on the power, the order of the generation of 
signals, in which after the signal .phi..sub.1 becomes high level, the 
signal .phi..sub.2 should become high level, is steadily preserved. 
With reference to FIG. 6, a detailed example of the timing signal generator 
of the invention will be explained with a detailed example of the buffer 
23 of FIG. 1. 
The buffer 23 is composed of three stages of inverters 23-1 to 23-3 
connected in cascade. The inverter stage 23-1 generates RAS and RASO 
having the opposite phase to RAS. The stage 23-2 generates PXO of the 
opposite phase to RASO in response to RASO and the stage 23-3 generates 
RASA. 
The delay circuit 31 is made of transistors Q.sub.53 through Q.sub.60, 
Q.sub.8 and Q.sub.9 in which Q.sub.8 and Q.sub.9 form a push-pull type 
output section. The delay circuit 32 has a structure similar to that of 
the circuit 31. 
Next, operations of the circuit of FIG. 6 will be explained with reference 
to FIGS. 7A and 7B for the cases where RAS is at a high level and a low 
level when the power voltage is switched on, respectively. 
With reference to FIG. 7A, the operation when RAS is at a high level will 
be explained. 
The power voltage is switched on at Ton. RAS and RASO generated from the 
stage 23-1 are at a low level because the transistors Q.sub.34 and 
Q.sub.36 are conducting, and hence PXO and RASA rise in potential in 
proportion of the rise of the power voltage V.sub.cc through the pull-up 
transistors Q.sub.44 and Q.sub.52. Since RASA is high and RAS is low, the 
gas of the transistor Q'.sub.8 of the delay circuit 31 becomes low. 
Although RASA is at a high level, a boot capacitor C.sub.1 does not store 
any charge in this instance, and therefore, the gate potential of Q'.sub.8 
is at a low level. Accordingly, the transistors Q'.sub.8 and Q'.sub.9 are 
non-conducting so that the output of the delay circuit 31 is in a floating 
state unless the transistor Q'.sub.11 is present. But, in this instance, 
the transistor Q'.sub.11 is conducting in response to a high level of RASA 
applied to its gate so that the signal .phi..sub.1 gradually rises along 
with RASA. 
In the delay circuit 32, the gate potentials of the transistors Q.sub.8 and 
Q.sub.9 are at a low level. After .phi..sub.1 becomes high, .phi..sub.2 
rises gradually through the transistor Q.sub.13'. Thus, the order in which 
.phi..sub.1 and .phi..sub.2 rise is established. 
With reference to FIG. 7B, the operation when RAS is at a low level when 
the power is switched on will be explained. After the power voltage is 
switched on at a time point Ton, RAS and RASO rise in proportion to the 
rise of V.sub.cc while PXO and RASA becomes low because the transistors 
Q.sub.40, Q.sub.43, Q.sub.44, Q.sub.49 and Q.sub.51 become conducting. 
Here, the drivability of the pull-up transistors Q.sub.44 and Q.sub.52 are 
very small as compared to those of Q.sub.40, Q.sub.50 and Q.sub.51. In 
this instance, the transistor Q.sub.55 is conducting in response to a high 
level of RAS and the transistors Q.sub.60 and Q.sub.9 become conducting so 
that the .phi..sub.1 is kept at a low level irrespective of Q'.sub.11. 
Also, in the delay circuit 32, the transistors Q.sub.63, Q.sub.68 and 
Q.sub.9 become conducting so that .phi..sub.2 is set low. 
As long as RAS is at a high level, the memory cannot introduce the access 
operation. Therefore, RAS is changed from a low level to a high level at a 
time point T.sub.2. Then, RAS and RASO become low while PXO and RASA 
become high. With RASA high, the transistors Q.sub.53 and Q.sub.50 conduct 
so that the gate protentials of Q.sub.60 and Q'.sub.9 are kept at a low 
level and also the gate potential of Q.sub.58 is kept at a low level. 
Consequently, the transistors Q'.sub.8 and Q'.sub.9 become non-conducting 
so that .phi..sub.1 starts to rise through the transistor Q'.sub.11. 
While the delay circuit 32, after .phi..sub.1 becomes high, the gate 
potentials of Q.sub.66, Q.sub.68 and Q.sub.9 are at a low level because 
the transistor Q.sub.64 is conducting. Consequently, the transistors 
Q.sub.67, Q.sub.68, Q.sub.8 and Q.sub.9 become non-conducting and the 
delay circuit 32 itself does not drive the signal .phi..sub.2. In response 
to the rise of .phi..sub.1, the transistor Q'.sub.13 becomes conducting so 
that .phi..sub.2 starts to rise in potential. 
As described above, the timing signal generator of the invention can 
generate a plurality of timing signal in a desired order when the power 
voltage is switched on. 
While the invention has been described in detail and with reference to 
specific embodiments thereof, it will be apparent to one skilled in the 
art that various changes and modifications can be made therein without 
departing from the spirit and scope thereof.