Wide voltage range level shifter circuit

A level shifter circuit shifts a digital signal between first and second voltage levels. For a LOW to HIGH transition, an output PMOS transistor is switched on using a first NMOS transistor activated by the digital signal at the first voltage level while a second NMOS transistor is switched off to uncouple the output PMOS transistor from ground, and a third NMOS transistor is switched off to uncouple a current mirror circuit from ground. For a HIGH to LOW transition, the output PMOS transistor is switched off and a fourth NMOS transistor is switched on using an output of the current mirror circuit. The second NMOS transistor is switched on using an inverted version of the digital signal, and the current in the current mirror circuit is turned off with a fifth NMOS transistor when the drain of the output PMOS transistor approaches the voltage level of ground.

FIELD OF THE INVENTION

The disclosure relates to level shifter circuitry for integrated circuits, and particularly to wide range level shifter circuitry.

BACKGROUND

Level shifters are important interface circuits between voltage domains on an integrated circuit (IC). A digital signal flowing from a low-voltage domain such as a processor core domain to a high-voltage domain such as an input/output domain requires a shift up in voltage by a level shifter, while digital signals flowing in the other direction require a shift down in voltage. Commonly used level shifters are limited in their input to output voltage range and typically require large transistor devices on the lower voltage domain. This requirement negatively impacts both the semiconductor circuit area and power consumption of the level shifter. The speed of operation is also negatively impacted, especially when the input voltage is low and a shift is made to a high output voltage.

Some known approaches to solving these problems use a two or more voltage levels and two or more level shifting stages to shift voltages. However, such approaches require extra supply voltages to be generated, and use a much larger area than single-stage level shifters.

The use of the same reference symbols in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

FIG.1illustrates in circuit diagram form a level shifter circuit100according to some embodiments. Level shifter circuit100is generally embodied on an integrated circuit and operates to level-shift an incoming digital signal “A” on an input terminal101in a first voltage supply domain to the voltage level of a second voltage domain as output signal Y at the level shifter output terminal103.

Level shifter circuit100includes an inverter102, number of n-type metal oxide semiconductor (NMOS) transistors M0-M4, a number p-type metal oxide semiconductor (PMOS) transistors M5-M7, wherein an output voltage supply for the second voltage domain is provided between a supply rail104and a ground106, and is also generally referred to as “output voltage supply104”, an input terminal101receiving a digital signal A to be level shifted, and a second input labelled “na” receiving an inverted version of the digital signal to be level-shifted, and output terminal103. The voltage supply for the first voltage domain is not separately shown.

Inverter102has an input receiving the digital signal A at input terminal101, and an inverter output connected to the second input na. Inverter102is supplied in the first voltage domain.

PMOS transistors M5and M6form a current mirror circuit. PMOS transistor M5has a source connected to output voltage supply104, a drain, and a gate connected to the drain at a node labelled “vp”. PMOS transistor M6has a source connected to output voltage supply104, a drain, and a gate. PMOS transistor M7has a source connected to the output voltage supply104, a drain connected to the level shifter output terminal103, and a gate connected to the drain of the PMOS transistor M6at a node labelled “ny”.

NMOS transistors M3and M0are connected in series between the drain of PMOS transistor M5and ground. NMOS transistor has a gate connected to second input na, and NMOS transistor M0has a gate connected to a level shifter output terminal103. NMOS transistor M1has a source connected to ground106, a gate connected to input terminal101and a drain connected to node ny. NMOS transistors M4and M2are connected in series between the drain of PMOS transistor M7and ground. NMOS transistor M4has a gate connected to the second input na. NMOS transistor M2has a gate connected to the drain of the NMOS transistor M1.

In operation, for a LOW to HIGH transition of the digital signal at input terminal101, PMOS transistor M7is switched on using NMOS transistor M1, which activated by the digital signal A at the first voltage level. NMOS transistor M4is switched off by the signal at second input na, uncoupling PMOS transistor M7from ground. NMOS transistor M3is switched off, uncoupling the current mirror circuit of M5and M6from ground.

For a HIGH to LOW transition of the digital signal, PMOS transistor M7is switched off, and NMOS transistor M2is switched on, both using a voltage generated at the output of the current mirror circuit at node ny. NMOS transistor M4is switched on using an inverted version of the digital signal at node na. Current in the current mirror circuit of M5and M6is turned off using NMOS transistor M0when the drain of the PMOS transistor M7approaches the voltage level of ground. The current mirror formed by PMOS transistors M5and M6is sized such that the leakage currents ensure that node ny stays high and does not turn-on M7. To provide this effect of the leakage currents, PMOS transistor M5has a gate length longer than that of PMOS transistor M6. PMOS transistor M2ensures a proper operation when the input voltage is higher than the output voltage, preventing the current mirror from turning off to early, that is, before “ny” has reached the high state.

Level shifter circuit100provides a simple wide-range level shifter which does not require an intermediate voltage like that required by 2-stage level shifters (which are often used for low input voltages). Level shifter circuit100also has numerous advantages, including very fast operation for wide input and output voltage ranges, low power consumption for both static and dynamic power, and minimal area. In fact, the area for all devices except PMOS transistor M5(as discussed above) can employ the minimum width and length for the technology node employed, such as 55 nanometer (nm) or 22 nm technology nodes. Importantly, level shifter circuit100is capable of sub-threshold operation, and does not suffer from excessive delays when the input voltage is near the voltage threshold of the transistors. For example, an embodiment using a 55 nm process node is able to operate with an input voltage as low as 0.55V, and an embodiment using a 22 nm process node is able to operate with an input voltage as low as 0.45V. Also, level shifter circuit100is able to be modified for functional extensions of a retention mode and a set-reset mode with little added complexity and few additional transistors, as shown below with respect toFIG.2.

FIG.2illustrates in circuit diagram form a level shifter circuit200including a retention mode and a set-reset function according to some embodiments. Level shifter circuit200includes has a first input terminal101receiving the digital signal A to be shifted, a retain input terminal labelled “RET”, a set input terminal labelled “SET”, a reset input terminal labelled “RES”, and an output terminal203providing a level-shifted outputs signal “Y”. The level-shifting portion of the circuit is constructed like that ofFIG.1, including transistors M0-M7. Level shifter circuit200also includes two NOR gates208and210, and a set-reset latch212.

NOR gate208has a first input connected to input terminal201receiving the digital signal to be shifted, and a second input receiving the retain signal RET, and an output connected to level shifter na. NOR gate210has a first input connected to the output of NOR gate208, a second input receiving the retain signal RET, and an output connected to an input of the level shifter portion of the circuit labelled “nna”.

Set-reset latch212includes an input coupled to the output terminal203of the level shifter, and five NMOS transistors labelled M8-M12. NMOS transistor M8has a drain connected to the level shifter output terminal203, a source, and a gate. NMOS transistor M9has a drain coupled to the gate to NMOS transistor M8, a source, and a gate connected to the level shifter output terminal Y. NMOS transistor M10has a drain connected to the level shifter output, a source connected to ground, and a gate receiving a reset signal labelled “RESET”. NMOS transistor M11has a drain connected to the drain of NMOS transistor M9, a source connected to ground, and a gate receiving a set signal labelled “SET”. NMOS transistor M12has a drain connected to the sources of NMOS transistors M8and M9, a source connected to ground, and a gate receiving the retain signal RET.

In operation, the retention mode ensures that the level shifter state is retained in absence of an input signal input terminal A. In normal operation, with the RET signal LOW, an inverted version of the digital signal A at input terminal201is provided in normal operation at the output of NOR gate208, and the digital signal A to be level shifted is provided to the level shifter portion of the circuit at node nna by inverting the signal at node na again with NOR gate210. When the retain mode is activated by the RET signal going HIGH, nodes na and nna are held low. In parallel to this, NMOS transistors M8and M9are enabled by feeding the RET signal to NMOS transistor M12, latching the current state of the level shifter output203. The set and reset functionality is also provided by NMOS transistors M10and M11when the retain mode is active. The level shifter output at output terminal203is set by the SET signal going HIGH (RES must LOW) and reset by the RES signal going HIGH (SET must be LOW). The SET and RES signals are on the domain of output voltage supply104.

FIG.3shows a graph300illustrating power consumption of level shifter circuit100as compared to a variety of other level shifter architectures. The input voltage level in volts is shown on the horizontal axis, and the power in watts (W) per megahertz (MHz) is shown logarithmically on the vertical axis. Graph300shows waveforms for power consumption of a typical two-stage level shifter labelled “P 2-stage”, power consumption of a typical one-stage level shifter labelled “P 1-stage”, power consumption of a crossed current mirror level shifter labelled “P XCM”, power consumption of a modified Wilson level shifter labelled “P MW”, and power consumption of level shifter circuit100ofFIG.1labelled “P SECC”. The power consumption is shown for a 3.6V level-shifted output voltage.

As can be seen in graph300, the power consumption of level shifter100is almost constant with respect to the input voltage. Also, the power consumption of level shifter100is consistently around 50% lower than other depicted architectures, at around 0.16 microwatts (μW), as compared to the other architectures which consume over 1 μW at the lower input voltage, while at higher input voltages still consumes over 0.32 μW.

FIG.4shows a graph400illustrating a delay of level shifter circuit100as compared to a variety of other level shifter architectures. The input voltage level in volts is shown on the horizontal axis, and signal delay through the level shifter is shown on the vertical axis in seconds (s). Graph400shows waveforms of delay for a typical two-stage level shifter labelled “Tpd 2-stage”, delay of a typical one-stage level shifter labelled “Tpd 1-stage”, delay of a crossed current mirror level shifter labelled “Tpd XCM”, delay of a modified Wilson level shifter labelled “Tpd MW”, and power consumption of level shifter circuit100ofFIG.1labelled “Tpd SECC”. The delay is shown for a 3.6V level-shifted output voltage.

As can be seen, level shifter100exhibits superior delay performance for almost the full input voltage range, and only the two-stage level shifter has superior performance toward the low end of input voltages at 0.6V. Furthermore, performance at the low end range of 0.65V input to 1V input is significantly better than most of the other architectures. Importantly, this performance advantage is achieved with a low transistor count as compared to most other architectures.

Thus, various embodiments of level shifter circuits, an integrated circuit including such level shifter circuits, and corresponding methods have been described. The driver circuits, associated logic, and receiver circuits described herein provide numerous advantages for level shifting across a wide range of voltages and speeds, and are suitable for use with a variety of technology nodes.

The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments that fall within the true scope of the claims. For example, particular technology node employed may vary. As another example, the digital logic employed to control the level shifter circuits herein, of course, vary while providing the same functionality.

Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted by the forgoing detailed description.