Substrate, method of sawing substrate, and semiconductor device

A method of dividing a substrate includes preparing a substrate including a crystalline semiconductor layer having a scribe lane region and device regions, a dielectric layer on the crystalline semiconductor layer, and a partition structure in physical contact with the dielectric layer and provided on the scribe lane region of the crystalline semiconductor layer, forming an amorphous region in the crystalline semiconductor layer, and performing a grinding process on the crystalline semiconductor layer after the forming of the amorphous region. The amorphous region is formed in the scribe lane region of the crystalline semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2017-0030840, filed on Mar. 10, 2017, in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

TECHNICAL FIELD

This disclosure generally relates to a substrate, a method of dividing the substrate, and a semiconductor device.

BACKGROUND

Light, small, high-speed, high-performance and low-cost electronic products may be provided with the development of an electronic industry. A wafer-level substrate may be used in manufacture of a semiconductor device. The substrate may include a plurality of device regions, and the substrate may be sawed to separate semiconductor devices from each other. The semiconductor devices should be prevented from becoming damaged in the process of sawing the substrate. In addition, when the sawing of the substrate is poor, a manufacture yield of the semiconductor devices may be reduced.

SUMMARY

Embodiments of the inventive concepts may provide a substrate capable of separating semiconductor devices well, a method of sawing the substrate, and a semiconductor device.

In one embodiment, a method of dividing a substrate may include preparing a substrate by providing a crystalline semiconductor layer having a scribe lane region and device regions, forming a dielectric layer on the crystalline semiconductor layer, and forming a partition structure in physical contact with the dielectric layer. The partition structure may be provided on the scribe lane region of the crystalline semiconductor layer. An amorphous region may be formed in the crystalline semiconductor layer and a grinding process may be performed on the crystalline semiconductor layer after the amorphous region is formed. The amorphous region may be formed in the scribe lane region of the crystalline semiconductor layer.

In another embodiment, a semiconductor device may include a crystalline semiconductor substrate, a dielectric layer on the crystalline semiconductor substrate, a partition structure provided in the dielectric layer and having a different strength from the dielectric layer, and a protective layer provided on the dielectric layer. The dielectric layer may expose at least a portion of a sidewall of the partition structure.

In another embodiment, a substrate may include a semiconductor layer including device regions and a scribe lane region, a dielectric layer on the semiconductor layer, a protective layer on the dielectric layer, and a partition structure provided in the dielectric layer and being in physical contact with the protective layer. The partition structure may have a different strength from the dielectric layer. The scribe lane region of the semiconductor layer may include a first region overlapped by the partition structure, when viewed in a plan view, and having a width of 5 μm to 20 μm, and second regions spaced apart from the partition structure, when viewed in the plan view. The second regions may be disposed between the first region and respective ones of the device regions.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Substrates, methods of dividing or singulating (e.g., sawing) the same, and semiconductor devices according to embodiments of the inventive concepts will be described hereinafter.

FIG. 1Ais a plan view illustrating a substrate according to some embodiments of the inventive concepts.FIG. 1Bis an enlarged view of region T shown inFIG. 1A.FIG. 2Ais a cross-sectional view taken along line II-II′ shown inFIG. 1B.FIG. 2Bis an enlarged view of region ‘III’ shown inFIG. 2A.

Referring toFIGS. 1A, 1B, 2A, and 2B, a substrate1may be provided as a wafer-level substrate. The substrate1may include a semiconductor layer100, a dielectric layer200, a protective layer300, and partition structures500. The semiconductor layer100may include device regions DR and a scribe lane region SLR, as exemplarily illustrated inFIG. 1A. Each of the device regions DR of the semiconductor layer100may be surrounded by the scribe lane region SLR, when viewed in a plan view. Thus, the device regions DR of the semiconductor layer100may be spaced apart from each other by the scribe lane region SLR. The semiconductor layer100may have a first surface100aand a second surface100bopposite to the first surface100a. The semiconductor layer100may include a crystalline semiconductor layer. The semiconductor layer100may be a crystalline semiconductor substrate. In some embodiments, the semiconductor layer100may be a single-crystalline semiconductor layer. As illustrated inFIG. 2B, integrated circuits400may be disposed on the device regions DR of the semiconductor layer100. The integrated circuits400may include a logic circuit, a memory circuit, or a combination thereof.

The dielectric layer200may be disposed on the first surface100aof the semiconductor layer100. The dielectric layer200may include an insulating material. The dielectric layer200may include a low-k dielectric material. The dielectric layer200may have a dielectric constant lower than that of silicon oxide (SiO2). For example, the dielectric layer200may have a dielectric constant lower than 3.9. In particular, the dielectric layer200may have a dielectric constant of 1.0 (or about 1.0) to 3.0 (or about 3.0). For example, the dielectric layer200may include at least one of an oxide-based material doped with impurities, porous silicon oxide, or an organic polymer. The oxide-based material doped with impurities may, for example, include fluorine-doped oxide (or fluorosilicate glass (FSG)), a carbon-doped oxide, silicon oxide, hydrogen silsesquioxane (SiO:H; HSQ), methyl silsesquioxane (SiO:CH3; MSQ), or a-SiOC (SiOC:H). The organic polymer may include a polyallylether-based resin, a cyclic fluorine resin, a siloxane copolymer, a polyallylether fluoride-based resin, a polypentafluorostylene-based resin, a polytetrafluorostylene-based resin, a polyimide fluoride resin, polynaphthalene fluoride, a polycide resin, or the like or any combination thereof.

The protective layer300may be disposed on the dielectric layer200. The protective layer300may include a material of which a strength is different from that of the dielectric layer200. In some embodiments, the strength of protective layer300and the strength of the dielectric layer200may include shear strengths. For example, the strength of the protective layer300may be greater than the strength of the dielectric layer200. Even though not shown in the drawings, the protective layer300may include a plurality of stacked layers. The protective layer300may include an insulating material. For example, the protective layer300may include at least one of tetraethyl orthosilicate (TEOS), silicon nitride, a high-density plasma (HDP) oxide, or the like. In certain embodiments, the protection layer300may include at least one of a polymer or a resin.

Connection terminals450may be provided on the protective layer300. The connection terminals450may be provided on the device regions DR of the semiconductor layer100. The connection terminals450may include a conductive material. The connection terminals450may have solder ball shapes, bump shapes, pillar shapes, or the like or any combinations thereof. As illustrated inFIG. 2B, each of the connection terminals450may be electrically connected to at least one of the integrated circuits400through an interconnection structure430. The interconnection structure430may be provided in the dielectric layer200and the protective layer300.

The partition structures500may be disposed in the dielectric layer200. The partition structures500may be in physical contact with the semiconductor layer100and the protective layer300. Even though not shown in the drawings, the arrangement of the partition structures500may be variously modified. For example, in some embodiments, the partition structures500may be spaced apart from the semiconductor layer100, the protective layer300or both the semiconductor layer100and the protective layer300. In certain embodiments, the partition structures500may further extend into the protective layer300, into the semiconductor layer100, or into both the semiconductor layer100and the protective layer300. A strength of the partition structures500may be different from that of the dielectric layer200. In some embodiments, the strength of the partition structures500and the strength of the dielectric layer200may include shear strengths. For example, the strength of the partition structures500may be greater or less than the strength of the dielectric layer200. The partition structures500may include a different material from the dielectric layer200. In some embodiments, the partition structures500may include a metal such as copper, aluminum, tungsten, titanium, tantalum, or the like or any combination thereof. In certain embodiments, the partition structures500may include an insulating material such as tetraethyl orthosilicate (TEOS), silicon nitride, a high-density plasma (HDP) oxide, a polymer, a resin, or the like or any combination thereof. As illustrated inFIG. 1B, the partition structures500may be provided on the scribe lane region SLR of the semiconductor layer100. The partition structures500may be spaced apart from the device regions DR of the semiconductor layer100and, when viewed in plan view, may surround each of the device regions DR. At least two partition structures500may be disposed between adjacent two device regions DR of the semiconductor layer100, when viewed in a plan view. Further, distances between adjacent ones of the partition structures500disposed between two adjacent device regions DR of the semiconductor layer100may be substantially equal to each other. The partition structures500may have bar shapes when viewed in a plan view, but may have any other suitable or desired shape.

The scribe lane region SLR of the semiconductor layer100may include a first region R1and multiple second regions R2. The partition structures500may be disposed on the first region R1of the scribe lane region SLR, but may not be disposed on the second regions R2of the scribe lane region SLR. A separation line (or saw line) SL (not shown in the FIGS.) may be provided on the first region R1of the scribe lane region SLR. Here, the separation line SL may be an imaginary line. For example, the separation line SL may be provided between two adjacent partition structures500. The partition structures500may have long axes extending in a direction parallel to the separation line SL adjacent thereto. The scribe lane region SLR of the semiconductor layer100may have a width W1of 60 nm (or about 60 nm) to 80 nm (or about 80 nm). The first region R1of the scribe lane region SLR of the semiconductor layer100may have a width W2of 5 nm (or about 5 μm) to 20 nm (or about 20 nm). The second regions R2of the scribe lane region SLR of the semiconductor layer100may be disposed between the first region R1of the scribe lane region SLR and respective device regions DR of the semiconductor layer100.

FIGS. 3A, 4A, and 5Aare cross-sectional views taken along line II-II′ ofFIG. 1Bto illustrate a method of dividing a substrate, according to some embodiments of the inventive concepts.FIGS. 3B, 4B, and 5Bare enlarged views of regions ‘III’ ofFIGS. 3A, 4A, and 5A, respectively. Hereinafter, the same technical features as described above will not be mentioned, or will be mentioned only briefly, for the purpose of ease and convenience in explanation.

Referring toFIGS. 1A, 1B, 3A, and 3B, a substrate1may be prepared. The substrate1may be substantially the same as described with reference toFIGS. 1A, 1B, 2A, and 2B. The semiconductor layer100of the substrate1may include a crystalline semiconductor material. A laser apparatus900may be disposed on the second surface100bof the semiconductor layer100. A laser may be irradiated from the laser apparatus900to the semiconductor layer100to locally heat the semiconductor layer100. A crystal structure of the heated region of the semiconductor layer100may be changed. Thus, amorphous regions150may be formed in the semiconductor layer100. The laser may be irradiated along the separation line SL (seeFIG. 1B) of the semiconductor layer100and, when viewed in plan view, the amorphous regions150may thus overlap with the separation line SL. The amorphous regions150may be formed in the first region R1of the scribe lane region SLR of the semiconductor layer100. The amorphous regions150may be provided between the partition structures500, when viewed in a plan view. Alternatively, the amorphous regions150may be overlapped by the partition structures500, when viewed in a plan view. The amorphous regions150may be formed at different depths in the semiconductor layer100. For example, the amorphous regions150may be provided at different distances from the second surface100bof the semiconductor layer100.

Referring toFIGS. 1A, 1B, 4A, and 4B, a grinding process may be performed on the second surface100bof the semiconductor layer100to remove a portion of the semiconductor layer100, as shown by a dotted line inFIG. 4A. In other words, the substrate1may be thinned by the grinding process. The grinding process of the semiconductor layer100may include a back-lap process, a chemical mechanical polishing (CMP) process, or the like or any combination thereof. The amorphous regions150of the semiconductor layer100may act as crack seeds during the grinding process of the semiconductor layer100. For example, a crack C may be formed from the amorphous regions150of the semiconductor layer100, and may propagate from the second surface100bto the first surface100aof the semiconductor layer100. The crack C may propagate along a crystal plane of the semiconductor layer100. The dielectric layer200may have different characteristics from the semiconductor layer100. For example, the dielectric layer200may not have a crystal structure. The partition structures500may function as mediums for assisting the propagation of the crack C. For example, the crack C may easily propagate into the dielectric layer200due to the difference in strength between the dielectric layer200and the partition structures500. The dielectric layer200may have different characteristics from the protective layer300. For example, the strength of the protective layer300may be greater than that of the dielectric layer200. The partition structures500may be in physical contact with the protective layer300. In this case, the crack C may easily propagate into the protective layer300by the partition structures500. As illustrated inFIG. 4B, the partition structures500may prevent the crack C from propagating into portions of the dielectric layer200which, when viewed in plan view, overlap with the device regions DR of the semiconductor layer100. Thus, it is possible to prevent the integrated circuits400and the interconnection structure430of the device regions DR from being damaged during a grinding process. The crack C may propagate from the semiconductor layer100into the dielectric layer200and the protective layer300to divide the substrate1. According to some embodiments of the inventive concepts, the process of dividing the substrate1may include the process of forming the amorphous regions150and the process of grinding the semiconductor layer100. A mechanical apparatus such as a blade may not used in the process of dividing the substrate1. According to some embodiments, a kerf width of the substrate1may be reduced. Thus, the first region R1of the scribe lane region SLR of the semiconductor layer100may have the width W2of 5 nm (or about 5 μm) to 20 nm (or about 20 nm). As a result, the number of the device regions DR in the semiconductor layer100of the substrate1may be increased.

If the crack C propagates along an interface between the dielectric layer200and the protective layer300, it may be difficult to divide the substrate1. However, according to some embodiments, the partition structures500may prevent and/or inhibit the crack C from propagating into the dielectric layer200overlapping with the device regions DR. Thus, the substrate1may be easily divided.

Referring toFIGS. 1A, 1B, 5A, and 5B, the device regions DR of the semiconductor layer100may be separated from each other along the separation line SL upon separating the substrate1. As a result, semiconductor devices1000may be separated from each other. A tensile force may further be applied to the substrate1in the process of separating the semiconductor devices1000from each other. Each of the semiconductor devices1000may include a device region DR of the semiconductor layer100, a portion of the dielectric layer200, and a portion of the protective layer300. Here, the portion of the dielectric layer200and the portion of the protective layer300may correspond to a respective device region DR. In addition, each of the semiconductor devices1000may further include a scribe lane region SLR′, and the dielectric layer200and the protective layer300disposed on the scribe lane region SLR′. Here, the scribe lane region SLR′ may include a portion of the first region R1of the scribe lane region SLR of the semiconductor layer100and the second region R2of the scribe lane region SLR. Each of the semiconductor devices1000may include the partition structures500. The partition structures500may be adjacent to sidewalls1000cof the semiconductor devices1000. In some embodiments, some of the partition structures500may be exposed at the sidewalls1000cof the semiconductor devices1000. Here, the sidewalls1000cof the semiconductor devices1000may be cut surfaces. The dielectric layer200may expose at least a portion of one of the partition structures500of a semiconductor device1000. The dielectric layer200may cover a first sidewall500dof the exposed partition structure500but may expose a second sidewall500cof the exposed partition structure500. The first and second sidewalls500dand500cof the exposed partition structure500may be opposite to each other. The partition structures500may surround the dielectric layer200of a semiconductor device1000, when viewed in plan view.

The amorphous regions150may remain in the semiconductor layer100of the semiconductor device1000. The amorphous regions150may be exposed at a sidewall100cof the semiconductor layer100. Alternatively, the amorphous regions150may be removed during the grinding process of the semiconductor layer100. Since the substrate1is divided by the propagation of the crack C, the sidewalls100cof the semiconductor layer100and sidewalls of the protective layer300may be smooth. A semiconductor device1000may include one or more memory devices such as dynamic random access memory (DRAM) devices, NAND flash memory devices, NOR flash memory devices, one-NAND memory devices, phase change random access memory (PRAM) devices, resistance random access memory (ReRAM) devices, magnetic random access memory (MRAM) devices, or the like or any combination thereof. In certain embodiments, a semiconductor device1000may include one or more logic devices such as digital signal processors or controllers.

Partition structures according to some embodiments of the inventive concepts will be described hereinafter. The descriptions to the same technical features as in the above embodiments will be omitted, or mentioned only briefly, for the purpose of ease and convenience in explanation. In descriptions to embodiments ofFIGS. 6, 7A, 7B, 7C, and 8, a single partition structure will be described for the purpose of ease and convenience in explanation.

FIG. 6is an enlarged view corresponding to region ‘III’ shown inFIG. 2A, and illustrates a partition structure according to some embodiments of the inventive concepts.

Referring toFIG. 6, a dielectric layer200may include a first dielectric layer210, a second dielectric layer220, and a third dielectric layer230. However, the dielectric layer200may include more or fewer dielectric layers than illustrated inFIG. 6. The partition structure500may penetrate the dielectric layer200and may be in physical contact with the semiconductor layer100and the protective layer300. The partition structure500may include a plurality of partition patterns510and a plurality of partition vias520. The partition patterns510may be provided within the first, second and third dielectric layers210,220, and230, respectively. The partition vias520may penetrate at least one of the first dielectric layer210, the second dielectric layer220, or the third dielectric layer230. The partition vias520may be in physical contact with respective ones of the partition patterns510.

The partition structure500may have a strength greater than that of the dielectric layer200. The partition patterns510and the partition vias520may include a conductive material, e.g., a metal. The partition patterns510and the partition vias520may be electrically insulated from the integrated circuits400. The interconnection structure430may include a plurality of conductive patterns431and a plurality of conductive vias432. The conductive patterns431may be provided within the first, second and third dielectric layers210,220, and230, respectively. The conductive vias432may penetrate at least one of the first dielectric layer210, the second dielectric layer220, or the third dielectric layer230. The partition vias520and the conductive vias432may be formed by a common process. Formation of the partition vias520and the conductive vias432may include forming trenches in the third dielectric layer230and filling the conductive material in the trenches. The trenches may expose the partition patterns510and the conductive patterns431, respectively. The partition patterns510and the conductive patterns431may be formed by a common process. For example, a conductive layer may be formed on the second dielectric layer220, and pattering process may be performed on the conductive layer to form the partition patterns510and the conductive patterns431. The pattering process may include etching process. However, embodiments of the inventive concepts are not limited thereto. For example, the partition vias520may be formed in a process that is different from that in which the conductive vias432are formed. Likewise, in other embodiments, the partition patterns510may be formed in a process that is different from that in which the conductive patterns431are formed.

A protective ring600may be provided in the dielectric layer200. The protective ring600may surround each of the device regions DR of the semiconductor layer100, when viewed in a plan view. The protective ring600may include a metal, an insulating material, a doped semiconductor material, or the like or any combination thereof. When the semiconductor devices1000are separated from each other as described with reference toFIGS. 5A and 5B, the protective ring600may protect each of the semiconductor devices1000from external contamination.

Unlike the processes described above used to form the partition patterns510and partition vias520, the partition pattern510and the partition via520may be formed by a damascene process. Thus, the shape and arrangement of the partition structure500shown inFIG. 6may be variously modified, depending upon how the partition structure500is formed. Modified examples of the shape and arrangement of the partition structure500will be described hereinafter.

FIGS. 7A to 7Care enlarged views corresponding to region ‘IV’ shown inFIG. 6, and illustrate partition structures according to some embodiments of the inventive concepts. The descriptions to the same technical features as in the above embodiments will be omitted, or mentioned only briefly, for the purpose of ease and convenience in explanation.

As illustrated inFIG. 7A, the partition structure500may be provided as partition structure501, and may penetrate a portion of the dielectric layer200. For example, the partition structure501may be provided in the third dielectric layer230but may not be provided in the first dielectric layer210or the second dielectric layer220. Although the partition structure501is illustrated as not extending into the second dielectric layer220, the partition structure501may, in another embodiment, extend partially or completely into the second dielectric layer220, but not into the first dielectric layer210.

As illustrated inFIG. 7B, the partition structure500may be provided as partition structure502, and may extend into the protective layer300. For example, the partition structure502may protrude from the dielectric layer200into the protective layer300. The partition structure502may be in contact with the semiconductor layer100. Although the partition structure502is illustrated as physically contacting the semiconductor layer100, the partition structure502may, in another embodiment, be spaced apart from the semiconductor layer100.

As illustrated inFIG. 7C, the partition structure500may be provided as partition structure503, and may be provided only in the protective layer300. Thus, the partition structure503may be disposed on the third dielectric layer230and not extend into the third dielectric layer230.

FIG. 8is an enlarged view corresponding to region ‘III’ shown inFIG. 2A, and illustrates a partition structure according to some embodiments of the inventive concepts. Hereinafter, a single partition structure will be described for the purpose of ease and convenience in explanation.

Referring toFIGS. 8, 9, and 10, a trench250may be provided in the dielectric layer200. The trench250may extend from a top surface of the dielectric layer200toward a bottom surface of the dielectric layer200. A partition structure500may fill the trench250. The partition structure500may include a different material from the dielectric layer200. A protective layer300may include a first protective layer310, a second protective layer320, and a third protective layer330, which are sequentially stacked. However, the protective layer300may include more or fewer protective layers than illustrated inFIGS. 8, 9, and 10. As illustrated inFIG. 8, the partition structure500and the first protective layer310may constitute a single unit body. In other words, the partition structure500may be connected to the first protective layer310without an interface interposed therebetween and may include the same material as the first protective layer310. For example, the partition structure500may include a material such as tetraethyl orthosilicate (TEOS), a high-density plasma (HDP) oxide, or the like or any combination thereof. In one embodiment, the partition structure500and the first protective layer310may be formed by a common process. AlthoughFIG. 8illustrates an embodiment in which the partition structure500and the first protective layer310constitute a single unit body, it will be appreciated that, in other embodiments, as illustrated inFIG. 9, the partition structure500and the second protective layer320may constitute a single unit body or as illustrated inFIG. 10, the partition structure500and the third protective layer330may constitute a single unit body. In certain embodiments, the partition structure500may include a different material from the first to third protective layers310,320, and330.

The partition structure500may penetrate the dielectric layer200and may be in contact with the semiconductor layer100. In the illustrated embodiment, the partition structure500may extend into the semiconductor layer100. In this case, a bottom surface500bof the partition structure500may be provided in the semiconductor layer100. In another embodiment, however, the bottom surface500bof the partition structure500may be disposed in the dielectric layer200and may be spaced apart from the semiconductor layer100.

According to some embodiments of the inventive concepts, the partition structures may be disposed in the dielectric layer. The substrate may be easily divided due to the presence of the partition structures. In the process of dividing the substrate, the partition structures may prevent damage of the integrated circuits and the interconnection structures disposed on the device regions of the semiconductor layer.