Semiconductor device

A semiconductor device includes a plurality of first conductive lines in a first wiring layer, a plurality of second conductive lines in a second wiring layer, and a plurality of memory cells between the first and second conductive lines in a first direction in a first region. A plurality of third conductive lines in the first wiring layer, a plurality of fourth conductive lines in the second wiring, and a plurality of first memory lines are in a second region. The third conductive lines extends in a second direction and are spaced from each other in a third direction. The fourth conductive lines extend in the second direction and are spaced in the third direction. The first memory lines are between the third conductive lines and the fourth conductive lines in the first direction. The first memory lines comprise the same materials as the memory cells.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-174252, filed Sep. 18, 2018, the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

A capacitive circuit may be mounted in a semiconductor device. When doing so, it is desired to reduce a circuit area of the capacitive circuit.

DETAILED DESCRIPTION

In general, according to one embodiment, a semiconductor device comprises a first and second region on a substrate. A first wiring layer is on the substrate in both the first region and the second region. A second wiring layer is on the substrate in both the first region and the second region. A first memory cell layer is between the first and second wiring layers in a first direction orthogonal to the substrate. A plurality of first conductive lines is in the first wiring layer in the first region. The first conductive lines extend in a second direction that is parallel to the substrate. The first conductive lines are spaced from each other in a third direction crossing the second direction and parallel to the substrate. A plurality of second conductive lines is in the second wiring layer in the first region. The second conductive lines extend in the third direction. The second conductive lines are spaced from each other in the second direction. A first plurality of memory cells is in the first memory cell layer in the first region. These memory cells are respectively between a first conductive line and a second conductive line at a crossing point of the first conductive line and the second conductive line. A plurality of third conductive lines is in the first wiring layer in the second region. The third conductive lines extend in the second direction and are spaced from each other in the third direction. A plurality of fourth conductive lines is in the second wiring layer in the second region. The fourth conductive lines extend in the second direction and are spaced from each other in the third direction. A first plurality of memory lines is in the first memory cell layer in the second region. These memory lines are respectively between a third conductive line and a fourth conductive line. These memory lines extend coextensively in the second direction with the third and fourth conductive lines. The memory cells and the memory lines in the first memory cell layer are comprised of same materials. A capacitor element is formed in the second region by the plurality of third conductive lines, the plurality of fourth conductive lines, and the first plurality of memory lines.

Hereinafter, details of a semiconductor device according to certain example embodiments will be described with reference to the accompanying drawings. The scope of the present disclosure is not limited to these example embodiments.

First Embodiment

A semiconductor device according to a first embodiment may include one or more semiconductor chips. A capacitive circuit may be mounted in the semiconductor device. For example, a capacitive circuit that performs decoupling for removing noise received from a power source is incorporated. A capacitive circuit having a metal-oxide-metal (MOM) structure may be utilized. The MOM structure is formed by arranging two sets of wiring patterns in a comb shape, so that the teeth of one comb interdigitates with the teeth of the other comb though the combs remain spaced from each other. It is desirable to reduce the chip area (wafer die size) of the semiconductor device.

A cross-point type memory cell array may be mounted in the semiconductor device. In a cross-point type memory cell array, bit lines having a narrow line width are arranged at a fine pitch, and word lines having a narrow line width are also arranged at a fine pitch. Therefore, if a microfabrication process for forming a bit lines and word lines is applied, it is possible to form a capacitive circuit having high capacitance per unit area and to enable one process to be used for both fabrication of the memory cell array and the capacitive circuit. Thus, it would be possible to increase memory density and the capacitance of a capacitive circuit (having a MOM structure) at low cost and to reduce circuit area of the capacitive circuit having the required capacitance.

The cross-point type memory cell array has a structure in which the direction of the bit lines and the word lines intersect with each other and a memory cell (memory cell layer) is formed at the points of intersection. It is thus difficult to achieve a capacitive circuit having a MOM structure while leaving the standard structure of the cross-point type memory cell array unchanged.

In the first embodiment, a capacitive circuit is configured such that a bit line, a memory cell layer, and a word line overlap each other along a length direction, and is laid out in accordance with a MOM structure. Thus, density and capacitance of the capacitive circuit are increased, and the circuit area of the capacitive circuit is reduced.

Specifically, when the capacitive circuit is formed, the structure thereof is a modification of the configuration the structure of the memory cell array. The layout is changed such that rather than intersect at single crossing point, a word line and a bit line completely overlap each other when viewed from a direction perpendicular to a substrate (e.g., Z-direction). The memory cell layer is formed between the word line and the bit line in a line shape so as to match with the shape of the word line and the bit line. A stacked structure in which the word line, the memory cell layer, and the bit line are stacked in the direction perpendicular to the substrate serves as a portion of an electrode in the MOM structure. That is, in the capacitive circuit, a plurality of stacked structures which are configured with word lines, memory cell layers, and bit lines are arranged on the surface of the substrate as the interdigitated combs. A first electrode is obtained by electrically connecting the stacked structures having even numbers among the plurality of stacked structures. A second electrode is obtained by electrically connecting the stacked structures having odd numbers among the plurality of stacked structures. Thus, with the first electrode and the second electrode, it is possible to achieve a capacitive circuit having a MOM structure (in which two sets of patterns are arranged in interdigitated comb shapes).

More specifically, a semiconductor device1may be configured as illustrated inFIG. 1.FIG. 1is a block diagram illustrating a configuration of the semiconductor device1. The semiconductor device1includes a memory cell array region2and a peripheral region3.

A memory cell array4is disposed in the memory cell array region2. The memory cell array4is a cross-point type memory cell array. A plurality of memory cells is disposed between a plurality of bit lines and a plurality of word lines. A capacitive circuit5, a write circuit6, a test circuit7, a power source circuit8, and a control circuit9are disposed in the peripheral region3. The write circuit6performs a write operation on the capacitive circuit5. The test circuit7performs a test on the capacitive circuit5. The power source circuit8supplies power to the components of the semiconductor device1. The control circuit9performs a write operation and/or a read operation on the memory cell in the memory cell array4.

For example, the capacitive circuit5may be electrically inserted in the middle of wirings from the power source circuit8to the components of the semiconductor device1, and thus can perform decoupling for removing noise from power supplied to the components of the semiconductor device1. In addition, for example, the capacitive circuit5may be electrically inserted in the middle of wirings from the control circuit9to the components of the semiconductor device1, and thus can perform decoupling for removing noise from a control signal supplied to the components of the semiconductor device1.

The memory cell array4illustrated inFIG. 1may be configured as illustrated inFIG. 2A, for example.FIG. 2Ais a circuit diagram illustrating a configuration of the memory cell array4. In the following descriptions, a direction perpendicular to the surface of a substrate is set as a Z-direction, and two directions which are orthogonal to each other in a plane orthogonal to the Z-direction are set as an X-direction and a Y-direction. The memory cell array4includes bit lines BL-1, BL-2, and BL-3, memory cells MC(1,1), MC(1,2) . . . MC(3,3), and word lines WL-1, WL-2, and WL-3.

The bit lines BL-1to BL-3(indicated by dot-dash lines inFIG. 2A) intersect with the word lines WL-1to WL-3(indicated by solid lines inFIG. 2A). The bit lines BL-1to BL-3are arranged in an interlayer insulating film21(seeFIG. 5A). The bit lines BL are at a predetermined pitch in the Y-direction and to extend in the X-direction.FIG. 2Aillustrates a case where three bit lines BL are disposed. However, the number of bit lines BL is not limited to that depicted inFIG. 2A.

The word lines WL-1to WL-3intersect with the bit lines BL-1to BL-3. The word lines WL-1to WL-3are arranged in the interlayer insulating film21(seeFIG. 5A), but at a level above the bit lines BL-1to BL-3. The word lines WL are at a predetermined pitch in the X-direction and to extend in the Y-direction.FIG. 2Aillustrates a case where three word lines WL are disposed. However, the number of word lines WL is not limited to that depicted inFIG. 2A.

The plurality of memory cells MC(1,1) to MC(3,3) (indicated by dotted lines inFIG. 2A) is arranged at positions of intersection for bit lines BL-1to BL-3and the word lines WL-1to WL-3. The plurality of memory cells MC(1,1) to MC(3,3) is thus arranged in a matrix in a plane formed in the X-direction and the Y-direction.FIG. 2Aillustrates a case where the memory cells MC are arranged in 3 rows and 3 columns (a 3×3 matrix). However, the arrangement of the memory cell MC is not limited to that depicted inFIG. 2A.

Although not specifically illustrated, a variable resistance element and a diode (rectifying element) are connected to each other in series in each of the memory cells MC. The resistance state of the variable resistance element is electrically variable and functions to store data in a non-volatile manner based on a resistance value. The diode is disposed to perform an electrical access (forming/writing/erasing/reading) to a selected cell and is disposed to prevent flowing of a leak current in the access operations.

The variable resistance element is an element transitioning between at least two resistance values, for example, a low resistance state and a high resistance state. If a predetermined set voltage is applied between both ends of the memory cell MC, for example, such that the diode is biased in a forward direction, the variable resistance element transitions from the high resistance state to the low resistance state (write, set). If a predetermined reset voltage is applied across the memory cell MC such that the diode is biased in the forward direction, the variable resistance element transitions from the low resistance state to the high resistance state (erase, reset). The variable resistance element comprises an insulating material. Thus, a step, referred to as “forming,” is performed in which a set operation or a reset operation is performed to change of the electrical resistance value of the variable resistance element. Forming is performed by applying a voltage pulse having a predetermined magnitude and a predetermined pulse width to the element.

A circuit configuration illustrated inFIG. 2Amay be structured in the manner as illustrated inFIG. 3, for example.FIG. 3is a perspective view illustrating a configuration of the memory cell array4.

In the memory cell array4, a first conductive layer11, a memory layer12, and a second conductive layer13are stacked in this order from the lower layer to the upper layer. The first conductive layer11includes the plurality of bit lines BL-1to BL-3. The memory layer12includes the plurality of memory cells MC(1,1) to MC(3,3). The second conductive layer13includes the plurality of word lines WL-1to WL-3. The cross-point type memory cell array4is configured such that each of the bit lines BL extends in the X-direction, each of the word lines WL extends in the Y-direction, and each of the memory cells MC is disposed between a corresponding bit line BL and a corresponding word line WL in the Z-direction.

FIG. 5Ais a cross-sectional view illustrating the layer configuration of the memory cell array4.

The first conductive layer11includes a conductive film11afunctioning as the bit line BL. The conductive film11ais disposed on a substrate10. The substrate10may be formed of a material containing a semiconductor such as silicon, as the main component. Another film (for example, an insulating film) may be disposed between the substrate10and the conductive film11a. The conductive film11amay be formed of a material containing tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), cobalt (Co), and nitrides thereof, as the main component.

The memory layer12includes a diode layer12a, a first electrode layer12b, a variable resistance layer12c, and a second electrode layer12dfrom the lower layer to the upper layer.

The diode layer12ais formed on the upper surface of the conductive film11a. The diode layer12afunctions as a diode. The diode layer12ahas a metal-insulator-metal (MIM) structure or a P+ poly-silicon-intrinsic-N+ poly-silicon (PIN) structure, for example. In a case of the PIN structure, the diode layer12ahas a configuration in which an N-type layer, an I-type layer, and a P-type layer are stacked. The N-type layer is formed of a semiconductor (for example, silicon) containing N-type impurities such as arsenic and phosphorus. The I-type layer does not contain impurities and is formed of so-called an intrinsic semiconductor (for example, silicon). The P-type layer is formed of a semiconductor (for example, silicon) containing P-type impurities such as boron.

The first electrode layer12bis formed on the upper surface of the diode layer12a. The first electrode layer12bmay be formed of a material containing titanium nitride (TiN) or tantalum nitride (TaN) as the main component, or may be formed of a material containing titanium dioxide (TiO2) as the main component and doped with platinum (Pt), tungsten (W), tungsten nitride (WN), or niobium (Nb).

The variable resistance layer12cis formed on the upper surface of the first electrode layer12b. The variable resistance layer12cfunctions as a variable resistance element. The variable resistance layer12cmay comprise a material selected from a group consisting of ZnMn2O4, NiO, HfO, TiO2, SrZrO3, Pr0.7Ca0.3MnO3, SrTi1-xNbxO3, Sm0.7Ca0.3MnO3, GdOx, Fe3O4, γ-Fe2O3, GeSe, and Cu2S, as the main component. For example, a hafnium oxide (HfOx) is used in the variable resistance layer12c.

The second electrode layer12dis formed on the upper surface of the variable resistance layer12c. The second electrode layer12dmay be formed of a material containing TiN or TaN as the main component, or may be formed of a material containing TiO2as the main component and doped with Pt, W, WN, or Nb.

The second conductive layer13includes a conductive film13afunctioning as the word line WL. The conductive film13ais disposed on the second electrode layer12d. The conductive film13amay be formed of a material containing tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), cobalt (Co), and nitrides thereof, as the main component.

The memory layer12may comprise an insulating material in the variable resistance layer12cand the like. However, for example, forming is performed, and thereby the resistivity of the memory layer12can be set to be lower than the resistivity of the interlayer insulating film21(seeFIG. 5A) in the memory cell array4.

The capacitive circuit5illustrated inFIG. 1may be configured as illustrated inFIG. 2B, for example.FIG. 2Bis a circuit diagram illustrating the configuration of the capacitive circuit5. The capacitive circuit5includes bit lines BLa-1to BLa-5, memory lines ML-1to ML-5, word lines WLa-1to WLa-5, and connection lines CL-1and CL-2.

Each bit line BLa (indicated by a dot-dash line inFIG. 2B) extends in parallel with a word line WLa (indicated by a solid line illustrated inFIG. 2B). When viewed from the Z-direction, each bit line BLa overlaps a word line WLa. The plurality of bit lines BLa-1to BLa-5is arranged in the interlayer insulating film21(seeFIG. 5A). The bit lines BLa are at a predetermined pitch in the Y-direction and extend in the X-direction (row direction).FIG. 2Billustrates a case where five bit lines BLa are disposed. However, the number of bit lines BLa is not limited to that depicted inFIG. 2B.

Each word line WLa extends in parallel with a bit line BLa. When viewed from the Z-direction, each word line WLa overlaps a bit line BLa. The plurality of word lines WLa-1to WLa-5is arranged in the interlayer insulating film21(seeFIG. 5A) above the bit lines BLa-1to BLa-5. The word lines WLa are at a predetermined pitch in the Y-direction and extend in the X-direction (row direction).FIG. 2Billustrates a case where five word lines WLa are disposed. However, the number of word lines WLa is not limited to that depicted inFIG. 2B.

Each memory line ML (indicated by a dotted line inFIG. 2B) is interposed between a bit line BLa and a word line WLa. The memory line ML is in contact with the bit line BLa on a −Z-side and is in contact with the word line WLa on a +Z-side. Each memory line ML extends in parallel with a bit line BLa and a word line WLa. When viewed from the Z-direction, each memory line ML overlaps a bit line BLa and is overlapped by a word line WLa. The memory lines ML are at a predetermined pitch in the Y-direction and extend in the X-direction (row direction).FIG. 2Billustrates a case where five memory lines ML are disposed. However, the number of memory lines ML is not limited to that depicted inFIG. 2B.

The connection lines CL-1and CL-2(indicated by solid lines inFIG. 2B) are disposed in an XY plane and extend in a direction (Y-direction) intersecting with the primary extension direction of the word lines WLa and the bit lines BLa.

The connection line CL-1is disposed on a +X-side of the plurality of word lines WLa-1to WLa-5and connects the word lines WLa-2and WLa-4having even numbers to each other from among the plurality of word lines WLa-1to WLa-5. Thus, an electrode EL-1is formed. The word line WLa-2and the bit line BLa-2are electrically connected to each other via the memory line ML-2, and thus the bit line BLa-2, the memory line ML-2, and the word line WLa-2form a portion (e.g., a comb tooth) of the electrode EL-1. The word line WLa-4and the bit line BLa-4are connected to each other via the memory line ML-4, and thus the bit line BLa-4, the memory line ML-4, and the word line WLa-4form a portion (e.g., a comb tooth) of the electrode EL-1. The connection line CL-1forms a portion of the electrode EL-1connecting the comb teeth portions to each other.

Here, the connection line CL-1specifically connects the word lines WLa-2and WLa-4to each other. Alternatively, the connection line CL-1could connect the word lines WLa-2and WLa-4to each other and also connect the bit lines BLa-2and BLa-4to each other from among the plurality of bit lines BLa-1to BLa-5.

The connection line CL-2is disposed on a −X-side of the plurality of word lines WLa-1to WLa-5and connects the word lines WLa-1, WLa-3, and WLa-5having odd numbers to each other from among the plurality of word lines WLa-1to WLa-5. Thus, an electrode EL-2is formed. The word line WLa-1and the bit line BLa-1are electrically connected to each other via the memory line ML-1, and thus the bit line BLa-1, the memory line ML-1, and the word line WLa-1form a portion (e.g., a comb tooth) of the electrode EL-2. The word line WLa-3and the bit line BLa-3are electrically connected to each other via the memory line ML-3, and thus the bit line BLa-3, the memory line ML-3, and the word line WLa-3form a portion (e.g., a comb tooth) of the electrode EL-2. The word line WLa-5and the bit line BLa-5are electrically connected to each other via the memory line ML-5, and thus the bit line BLa-5the memory line ML-5, and the word line WLa-5form a portion (e.g., a comb tooth) of the electrode EL-2. The connection line CL-2forms a portion of the electrode EL-2connecting the comb teeth portions to each other.

The connection line CL-2connects the word lines WLa-1, WLa-3, and WLa-5having odd numbers to each other. Alternatively, the connection line CL-2may connect the word lines WLa-1, WLa-3, and WLa-5to each other and connect the bit lines BLa-1, BLa-3, and BLa-5to each other from among the plurality of bit lines BLa-1to BLa-5.

In the capacitive circuit5illustrated inFIG. 2B, the comb tooth-like electrode EL-1and the comb tooth-like electrode EL-2are respectively formed, and the electrode EL-1and the electrode EL-2are disposed so that the teeth of one comb are between the teeth of the other via the interlayer insulating film21(seeFIG. 5A) in the XY directions. That is, the electrode EL-1and the electrode EL-2constitute a MOM structure in which two sets of comb-shaped wiring patterns are formed in an interlocking manner.

A circuit configuration illustrated inFIG. 2Bmay be formed in a manner as illustrated inFIG. 4, for example.FIG. 4is a perspective view illustrating a configuration of a capacitive circuit5.

In the capacitive circuit5, a first conductive layer11, a memory layer12, and a second conductive layer13are stacked in this order from the lower layer to the upper layer. The first conductive layer11, the memory layer12, and the second conductive layer13are layers which match the first conductive layer11, the memory layer12, and the second conductive layer13in the memory cell array4, respectively.

The first conductive layer11includes bit lines BLa-1to BLa-5. The memory layer12includes memory lines ML-1to ML-5. The second conductive layer13includes word lines WLa-1to WLa-5and connection lines CL-1and CL-2. Each bit line BLa, each memory line ML, and each word line WLa extend in the X-direction. The connection line CL-1connects the even-numbered word lines WLa-2and WLa-4to each other on the +X-side. The connection line CL-2connects the odd-numbered word lines WLa-1, WLa-3, and WLa-5to each other on the −X-side. In this manner, a MOM structure type capacitive circuit5is formed.

FIG. 5Bis a cross-sectional view illustrating the layer configuration of the capacitive circuit5.

The first conductive layer11includes a conductive film11a1functioning as a bit line BLa. The conductive film11a1is disposed on a substrate10. The substrate10may be formed of a material containing a semiconductor such as silicon, as the main component. Another film (for example, an interlayer insulating film) may be disposed between the substrate10and the conductive film11a1. The conductive film11a1may be formed of a material containing tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), cobalt (Co), and nitrides thereof, as the main component. The conductive film11a1corresponds to the conductive film11a(seeFIG. 5A) in the memory cell array4.

The memory layer12includes a diode layer12a1, a first electrode layer12b1, a variable resistance layer12c1, and a second electrode layer12d1from the lower layer to the upper layer.

The diode layer12a1is formed on the upper surface of the conductive film11a1. The diode layer12a1is formed to have a metal-insulator-metal (MIM) structure or a P+ poly-silicon-intrinsic-N+ poly-silicon (PIN) structure, for example. In a case of a PIN structure, the diode layer12a1has a configuration, for example, in which an N-type layer, an I-type layer, and a P-type layer are stacked. The N-type layer is formed of a semiconductor (for example, silicon) containing N-type impurities such as arsenic and phosphorus. The I-type layer does not contain impurities and is formed of so-called an intrinsic semiconductor (for example, silicon). The P-type layer is formed of a semiconductor (for example, silicon) containing P-type impurities such as boron. The diode layer12a1corresponds to the diode layer12a(seeFIG. 5A) in the memory cell array4.

The first electrode layer12b1is formed on the upper surface of the diode layer12a1. The first electrode layer12b1may be formed of a material containing TiN or TaN as the main component, or may be formed of a material containing TiO2as the main component and doped with Pt, W, WN, or Nb. The first electrode layer12b1corresponds to the first electrode layer12b(seeFIG. 5A) in the memory cell array4.

The variable resistance layer12c1is formed on the upper surface of the first electrode layer12b1. The variable resistance layer12c1may be formed of a material comprises a material selected from the group consisting of ZnMn2O4, NiO, HfO, TiO2, SrZrO3, Pr0.7Ca0.3MnO3, SrTi1-xNbxO3, Sm0.7Ca0.3MnO3, GdOx, Fe3O4, γ-Fe2O3, GeSe, and Cu2S, as the main component. The variable resistance layer12c1may, for example, comprise a hafnium oxide (HfOx). The variable resistance layer12c1corresponds to the variable resistance layer12c(seeFIG. 5A) in the memory cell array4.

The second electrode layer12d1is formed on the upper surface of the variable resistance layer12c1. The second electrode layer12d1may be formed of a material containing TiN or TaN as the main component, or may be formed of a material containing TiO2as the main component and doped with Pt, W, WN, or Nb. The second electrode layer12d1corresponds to the second electrode layer12d(seeFIG. 5A) in the memory cell array4.

The second conductive layer13includes a conductive film13a1functioning as a word line WLa and a conductive film13a2functioning as a connection line CL. The conductive film13a1is disposed on the second electrode layer12d1. The conductive films13a1and13a2may be formed of a material containing tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), cobalt (Co), and nitrides thereof, as the main component. The conductive film13a1corresponds to the conductive film13a(seeFIG. 5A) in the memory cell array4.

The memory layer12may comprise an insulating substance in the variable resistance layer12c1and the like. However, for example, forming is performed, and thereby the resistivity of the memory layer12can be controlled to be lower than the resistivity of the interlayer insulating film21in the capacitive circuit5.

As described above, in the first embodiment, the capacitive circuit5in the semiconductor device1is configured such that a bit line BLa, a memory line ML, and a word line WLa parallel each other are laid out in accordance with a MOM structure. With such a configuration, it is possible to form the capacitive circuit5having high capacitance per unit area using substantially the same microfabrication process used in forming the plurality of bit lines and the plurality of word lines for the cross-point memory cell array4. Thus, it is possible to increase the capacitance of the capacitive circuit5and to reduce the circuit area of the capacitive circuit5.

In the first embodiment, the memory cell array4and the capacitive circuit5face each other. Thus, it is possible to form the memory cell array4and the capacitive circuit5with the same fabrication steps. Accordingly, it is possible to achieve both reduction in the cost of the semiconductor device1and an increase in the density of the capacitive circuit5.

The memory cell array4may be a cross-point type memory cell array, but embodiments of the present disclosure are not limited to a memory cell array4for a resistive switching memory (ReRAM) type. For example, the memory cell array4may be for a phase-change memory (PCM) type, and a phase-change layer may be provided in the layer configurations illustrated inFIGS. 5A and 5B, instead of the variable resistance layers12cand12c1. The phase-change layer may be formed of a chalcogenide-based material, such as one of germanium (Ge), antimony (Sb), or tellurium (Te), for example. Alternatively, the memory cell array4is a magnetoresistive memory (MRAM) type and a magnetic layer may be provided in the layer configurations illustrated inFIGS. 5A and 5Binstead of the variable resistance layers12cand12c1. Alternatively, the memory cell array4is a ferroelectric memory (FeRAM) type, and a ferroelectric layer may be provided in the layer configurations illustrated inFIGS. 5A and 5Binstead of the variable resistance layers12cand12c1.

In the layer configuration of the capacitive circuit5, a portion of the layer configuration of the memory cell array4can be omitted or changed. For example, when the diode layer12ain the memory cell array4has a P+poly-silicon-intrinsic-N+poly-silicon (PIN) structure, the diode layer12a1in the capacitive circuit5may have a configuration in which the I-type layer is omitted, and only the N-type layer and the P-type layer are stacked. Likewise, the thickness of the variable resistance layer12c1in the capacitive circuit5may be thinner than the thickness of the variable resistance layer12cin the memory cell array4.

The rectifying element used for a memory cell structure may be, for example, a switching element between two terminals, instead of the rectifying element such as a diode. When a voltage applied between two terminals is equal to or higher than a threshold voltage, the switching element is in a “high resistance” state, for example, in an electrically non-conductive state. When the voltage applied between the two terminals is lower than the threshold voltage, the switching element changes to “a low resistance state”, for example, an electrically conductive state. The switching element may have such a function regardless of the polarity of the voltage. The switching element contains one or more chalcogen elements selected from the group consisting of tellurium (Te), selenium (Se), and sulfur (S). The switching element may contain a chalcogenide which is a compound containing a chalcogen element. In addition, the switching element may contain one or more elements selected from the group consisting of B, Al, Ga, In, C, Si, Ge, Sn, As, P, and Sb.

Second Embodiment

A semiconductor device1iaccording to a second embodiment will be described. Descriptions will be made below focusing on differences from the first embodiment.

In the first embodiment, a case where the memory cells were arranged in two dimensions was described as an example. In the second embodiment, a case where the memory cells are arranged in three dimensions will be described.

Specifically, the semiconductor device1iincludes a memory cell array4iand a capacitive circuit5iinstead of the memory cell array4and the capacitive circuit5.

The memory cell array4imay be configured as illustrated inFIG. 6A, for example.FIG. 6Ais a circuit diagram illustrating a configuration of the memory cell array4i. The memory cell array4iincludes memory cells MC′ (1,1) . . . MC′ (3,3) and bit lines BL′-1to BL′-3.

The bit lines BL′-1to BL′-3(indicated by dot-dash lines inFIG. 6A) intersect with the word lines WL-1to WL-3(indicated by solid lines inFIG. 6A). The bit lines BL′-1to BL′-3are arranged in an interlayer insulating film22(seeFIG. 9A), above the word lines WL-1to WL-3. The bit lines BL′ are at a predetermined pitch in the Y-direction and to extend in the X-direction.FIG. 6Aillustrates a case where three bit lines BL′ are disposed. However, the number of bit lines BL′ is not limited to that depicted inFIG. 6A.

The plurality of memory cells MC′ (1,1) to MC′ (3,3) (indicated by dotted lines inFIG. 6A) are the intersection positions of the bit lines BL′-1to BL′-3and the word lines WL-1to WL-3. The plurality of memory cells MC′ (1,1) to MC′ (3,3) is arranged in a matrix in a plane formed in the X-direction and the Y-direction.FIG. 6Aillustrates a case where the memory cells MC′ are arranged in 3 rows and 3 columns. However, the arrangement of the memory cell MC′ is not limited to that depicted inFIG. 6A.

The plurality of memory cells MC′ (1,1) to MC′(3,3) corresponds to the plurality of memory cells MC(1,1) to MC(3,3) described in conjunction with the first embodiment. Each memory cell MC′ shares a word line WL with a corresponding memory cell MC.

A circuit configuration illustrated inFIG. 6Amay be provided as illustrated inFIG. 7, for example.FIG. 7is a perspective view illustrating a configuration of the memory cell array4i.

In the memory cell array4i, a second memory layer14and a third conductive layer15are further stacked on the layers depicted inFIG. 3. The second memory layer14includes the memory cells MC′ (1,1) to MC′ (3,3). The third conductive layer15includes the bit lines BL′-1to BL′-3. The three-dimensional cross-point type memory cell array4iis configured in a manner that each of the bit lines BL and BL′ extends in the X-direction, each of the word lines WL extends in the Y-direction, each of the memory cells MC is disposed between the corresponding bit line BL and the corresponding word line WL in the Z-direction, and each of the memory cells MC′ is disposed between the corresponding bit line BL′ and the corresponding word line WL in the Z-direction.

FIG. 9Ais a cross-sectional view illustrating the layer configuration of the memory cell array4i.

The second memory layer14includes a diode layer14a, a first electrode layer14b, a variable resistance layer14c, and a second electrode layer14dfrom the lower layer to the upper layer.

The diode layer14ais formed on the upper surface of the conductive film11a. The diode layer14afunctions as a diode. The diode layer14ais formed to have a metal-insulator-metal (MIM) structure or a P+ poly-silicon-intrinsic-N+ poly-silicon (PIN) structure, for example. In a case of the PIN structure, the diode layer14ahas a configuration, for example, in which an N-type layer, an I-type layer, and a P-type layer are stacked. The N-type layer is formed of a semiconductor (for example, silicon) containing N-type impurities such as arsenic and phosphorus. The I-type layer does not contain impurities and is formed of so-called an intrinsic semiconductor (for example, silicon). The P-type layer is formed of a semiconductor (for example, silicon) containing P-type impurities such as boron.

The first electrode layer14bis formed on the upper surface of the diode layer14a. The first electrode layer14bmay be formed of a material containing TiN or TaN as the main component, or may be formed of a material containing TiO2as the main component and doped with Pt, W, WN, or Nb.

The variable resistance layer14cis formed on the upper surface of the first electrode layer14b. The variable resistance layer14cfunctions as a variable resistance element. The variable resistance layer14cmay be formed of a material comprising material selected from the group consisting of ZnMn2O4, NiO, HfO, TiO2, SrZrO3, Pr0.7Ca0.3MnO3, SrTi1-xNbxO3, Sm0.7Ca0.3MnO3, GdOx, Fe3O4, γ-Fe2O3, GeSe, and Cu2S, as the main component. For example, a hafnium oxide (HfOx) is used in the variable resistance layer14c.

The second electrode layer14dis formed on the upper surface of the variable resistance layer14c. The second electrode layer14dmay be formed of a material containing TiN or TaN as the main component, or may be formed of a material containing TiO2as the main component and doped with Pt, W, WN, or Nb.

The third conductive layer15includes a conductive film15afunctioning as the bit line BL′. The conductive film15ais disposed on the second electrode layer14d. The conductive film15amay be formed of a material containing tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), cobalt (Co), and nitrides thereof, as the main component.

The second memory layer14may comprise an insulating substance in the variable resistance layer14cand the like. However, for example, forming is performed, and thereby the resistivity of the second memory layer14can be controlled to be lower than the resistivity of the interlayer insulating film22(seeFIG. 9A) in the memory cell array4i.

The capacitive circuit5imay be configured as illustrated inFIG. 6B, for example.FIG. 6Bis a circuit diagram illustrating a configuration of the capacitive circuit5i. The capacitive circuit5iincludes connection lines CL′-1and CL′-2instead of the connection lines CL-1and CL-2(seeFIG. 2B) and further includes memory lines ML′-1to ML′-5and bit lines BLa′-1to BLa′-5.

Each bit line BLa′ (indicated by a dot-dash line inFIG. 6B) extends in parallel with a word line WLa (indicated by a solid line illustrated inFIG. 6B). When viewed from the Z-direction, each bit line BLa′ overlaps a word line WLa. The bit lines BLa′-1to BLa′-5are arranged in the interlayer insulating film22(seeFIG. 9A). The bit lines BLa′ are at a predetermined pitch in the Y-direction and extend in the X-direction (row direction).FIG. 6Billustrates a case where five bit lines BLa′ are disposed. However, the number of bit lines BLa′ is not limited to that depicted inFIG. 6B.

Each memory line ML′ (indicated by a dotted line inFIG. 6B) is interposed between a word line WLa and a bit line BLa′. The memory line ML′ is in contact with the word line WLa on the −Z-side and is in contact with the bit line BLa′ on the +Z-side. Each memory line ML′ extends in parallel with a bit line BLa′ and a word line WLa. When viewed from the Z-direction, each memory line ML′ overlaps a bit line BLa′ and a word line WLa overlaps the memory line ML′. The memory lines ML′ are at a predetermined pitch in the Y-direction and extend in the X-direction (row direction).FIG. 6Billustrates a case where five memory lines ML′ are disposed. However, the number of memory lines ML′ is not limited to that depicted inFIG. 6B.

The connection lines CL′-1and CL′-2(indicated by solid lines inFIG. 6B) are disposed along the XY plane and extend in a direction (Y-direction) intersecting with the word line WLa and the bit lines BLa and BLa′.

The connection line CL′-1is disposed on the +X-side of the plurality of bit lines BLa′-1to BLa′-5and connects the even-numbered bit lines BLa′-2and BLa′-4to each other from among the plurality of bit lines BLa′-1to BLa′-5. Thus, an electrode ELi-1may be formed. That is, the bit line BLa-2, the memory line ML-2, the word line WLa-2, the memory line ML′-2, and the bit line BLa′-2form a portion of an electrode ELi-1. The bit line BLa-4, the memory line ML-4, the word line WLa-4, the memory line ML′-4, and the bit line BLa′-4form another portion of the electrode ELi-1. The connection line CL′-1forms a portion of the electrode ELi-1connecting the other portions.

The connection line CL′-1connects the even-numbered bit lines BLa′-2and BLa′-4to each other. Alternatively, the connection line CL′-1may connect the even number word lines WLa-2and WLa-4to each other.

The connection line CL′-2is disposed on the −X-side of the plurality of bit lines BLa′-1to BLa′-5and connects the bit lines BLa′-1, BLa′-3, and BLa′-5each other from among the plurality of bit lines BLa′-1to BLa′-5. Thus, an electrode ELi-2may be formed. That is, the bit line BLa-1, the memory line ML-1, the word line WLa-1, the memory line ML′-1, and the bit line BLa′-1form a portion of the electrode ELi-2. The bit line BLa-3, the memory line ML-3, the word line WLa-3, the memory line ML′-3, and the bit line BLa′-3from another portion of the electrode ELi-2. The bit line BLa-5, the memory line ML-5, the word line WLa-5, the memory line ML′-5, and the bit line BLa′-5form another portion of the electrode ELi-2. The connection line CL′-2forms a portion of the electrode ELi-2connecting the other portions.

The connection line CL′-2connects the odd-numbered bit lines BLa′-1, BLa′-3, and BLa′-5to each other. Alternatively, the connection line CL′-2may the odd-numbered word lines WLa-1, WLa-3, and WLa-5to each other.

In the capacitive circuit5iillustrated inFIG. 6B, the comb tooth-like electrode ELi-1and the comb tooth-like electrode ELi-2are respectively formed, and the electrode ELi-1and the electrode ELi-2are disposed so that the teeth of one comb interdigitate with the teeth of the other while being spaced from each other via the interlayer insulating film21and the interlayer insulating film22(seeFIG. 9A) in the XY directions. That is, the electrode ELi-1and the electrode ELi-2form a MOM structure.

A circuit configuration illustrated inFIG. 6Bmay be formed as illustrated inFIG. 8, for example.FIG. 8is a perspective view illustrating a configuration of mounting the capacitive circuit5i.

In the capacitive circuit5i, a second memory layer14and a third conductive layer15are further stacked. The second memory layer14and the third conductive layer15are layers which are also used as the second memory layer14and the third conductive layer15in the memory cell array4i, respectively.

The second memory layer14includes memory lines ML′-1to ML′-5. A third conductive layer15includes bit lines BLa′-1to BLa′-5and connection lines CL′-1and CL′-2. Each of the bit lines BLa and BLa′, each of the memory lines ML and ML′, and each of the word lines WLa extend in the X-direction. The connection line CL′-1connects the bit lines BLa′-2and BLa′-4to each other on the +X-side. The connection line CL′-2connects the bit lines BLa′-1, BLa′-3, and BLa′-5to each other on the −X-side. In this manner, the MOM structure type capacitive circuit5iis formed.

FIG. 9Bis a cross-sectional view illustrating the layer configuration of the capacitive circuit5i.

The second memory layer14includes a diode layer14a1, a first electrode layer14b1, a variable resistance layer14c1, and a second electrode layer14d1from the lower layer to the upper layer.

The diode layer14a1is formed on the upper surface of the conductive film13a1. The diode layer14a1functions as a diode. The diode layer14a1is formed to have a metal-insulator-metal (MIM) structure or a P+ poly-silicon-intrinsic-N+ poly-silicon (PIN) structure, for example. In a case of the PIN structure, the diode layer14a1has a configuration, for example, in which an N-type layer, an I-type layer, and a P-type layer are stacked. The N-type layer is formed of a semiconductor (for example, silicon) containing N-type impurities such as arsenic and phosphorus. The I-type layer does not contain impurities and is formed of so-called an intrinsic semiconductor (for example, silicon). The P-type layer is formed of a semiconductor (for example, silicon) containing P-type impurities such as boron. The diode layer14a1corresponds to the diode layer14a(seeFIG. 9A) in the memory cell array4i.

The first electrode layer14b1is formed on the upper surface of the diode layer14a1. The first electrode layer14b1may be formed of a material containing TiN or TaN as the main component, or may be formed of a material containing TiO2as the main component and doped with Pt, W, WN, or Nb. The first electrode layer14b1corresponds to the first electrode layer14b(seeFIG. 9A) in the memory cell array4i.

The variable resistance layer14c1is formed on the upper surface of the first electrode layer14b1. The variable resistance layer14c1functions as a variable resistance element. The variable resistance layer14c1may be formed of a material comprising a material selected from the group consisting of ZnMn2O4, NiO, HfO, TiO2, SrZrO3, Pr0.7Ca0.3MnO3, SrTi1-xNbxO3, Sm0.7Ca0.3MnO3, GdOx, Fe3O4, γ-Fe2O3, GeSe, and Cu2S, as the main component. For example, a hafnium oxide (HfOx) may be used in the variable resistance layer14c1. The variable resistance layer14c1corresponds to the variable resistance layer14c(seeFIG. 9A) in the memory cell array4i.

The second electrode layer14d1is formed on the upper surface of the variable resistance layer14c1. The second electrode layer14d1may be formed of a material containing TiN or TaN as the main component, or may be formed of a material containing TiO2as the main component and doped with Pt, W, WN, or Nb. The second electrode layer14d1corresponds to the second electrode layer14d(seeFIG. 9A) in the memory cell array4i.

The third conductive layer15includes a conductive film15a1functioning as the bit line BL′ and a conductive film15a2functioning as the connection line CL′. The conductive film15a1is disposed on the second electrode layer14d1. The conductive films15a1and15a2may be formed of a material containing tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), cobalt (Co), and nitrides thereof, as the main component. The conductive film15a1corresponds to the conductive film15a(seeFIG. 9A) in the memory cell array4i.

The second memory layer14may contain an insulating substance in the variable resistance layer14c1. However, for example, forming is performed, and thereby the resistivity of the second memory layer14can be varied to be lower than the resistivity of the interlayer insulating film22(seeFIG. 9A) in the memory cell array4i.

As described above, in the second embodiment, the capacitive circuit5iin the semiconductor device1iis configured such that the bit line BLa, the memory line ML, the word line WLa, the memory line ML′, and the bit line BLa′ overlap each other, and is laid out in accordance with a MOM structure. With such a configuration, it is also possible to form the capacitive circuit5ihaving high capacitance per unit area using the same microfabrication processes for forming the plurality of bit lines and the plurality of word lines used in fabricating the memory cell array4i. Thus, it is also possible to increase the density and the capacitance of the capacitive circuit5iand to reduce the circuit area of the capacitive circuit5ihaving required capacitance.

In the second embodiment, the memory cell array4iand the capacitive circuit5iface each other. Thus, it is possible to form the memory cell array4iand the capacitive circuit5iwith the same manufacturing process steps. Accordingly, it is possible to achieve both reduction of the cost of the semiconductor device1iand an increase of the density of the capacitive circuit5i.

Third Embodiment

A semiconductor device1jaccording to a third embodiment will be described. Descriptions will be made below focusing on differences from the first embodiment and the second embodiment.

The case where the memory cells are arranged in two dimensions was described as an example in the first embodiment. A case in which an upper and a lower layer of memory cells share word lines was described as an example in the second embodiment. In the third embodiment, a case in which the upper layer and lower layer of memory cells do not share word lines (in contrast to the second embodiment) is described as an example.

Specifically, a semiconductor device1jincludes a memory cell array4jand a capacitive circuit5jinstead of the memory cell array4and the capacitive circuit5(seeFIG. 1) or the memory cell array4ior the capacitive circuit5i(seeFIGS. 6A and 6B).

The memory cell array4jmay be configured as illustrated inFIG. 10A, for example.FIG. 10Ais a circuit diagram illustrating a configuration of the memory cell array4j. The memory cell array4jfurther includes bit lines BL″-1to BL″-3, memory cells MC″(1,1) . . . MC″(3,3), and word lines WL″-1to WL″-3.

The bit lines BL″-1to BL″-3(indicated by dot-dash lines inFIG. 10A) intersect with the f word lines WL″-1to WL″-3(indicated by solid lines inFIG. 10A). The bit lines BL″-1to BL″-3are arranged on an interlayer insulating film23(seeFIG. 13A) above the word lines WL-1to WL-3. The bit lines BL″-1to BL″-3is arranged in an interlayer insulating film22(seeFIG. 13A). The bit lines BL″ are at a predetermined pitch in the Y-direction and extend in the X-direction.FIG. 10Aillustrates a case where the three bit lines BL″ are disposed. However, the number of bit lines BL″ is not limited to that depicted inFIG. 13A.

The word lines WL″-1to WL″-3intersect the bit lines BL″-1to BL″-3. The word lines WL″-1to WL″-3are arranged in the interlayer insulating film22(seeFIG. 13A) above the plurality of bit lines BL″-1to BL″-3. The word lines WL″ are at a predetermined pitch in the X-direction and extend in the Y-direction.FIG. 10Aillustrates a case where the three word lines WL″ are disposed. However, the number of word lines WL″ is not limited to that depicted inFIG. 10A.

The memory cells MC″ (1,1) to MC″ (3,3) (indicated by dotted lines inFIG. 10A) are at positions of intersection of bit lines BL″-1to BL″-3and the word lines WL″-1to WL″-3. The plurality of memory cells MC″ (1,1) to MC″ (3,3) is arranged in a plane.FIG. 10Aillustrates a case where the memory cells MC″ are arranged in 3 rows and 3 columns. However, the arrangement of the memory cell MC″ is not limited to that in depictedFIG. 10A.

The plurality of memory cells MC″ (1,1) to MC″ (3,3) corresponds to the plurality of memory cells MC(1,1) to MC(3,3); however, the word line WL″ of each memory cell MC″ is separate from the word line WL of the corresponding memory cell MC. Thus, each memory cell MC″ is formed to be accessible with the corresponding memory cell MC while being independent from the corresponding memory cell MC.

A circuit configuration illustrated inFIG. 10Amay be formed in a manner as illustrated inFIG. 11, for example.FIG. 11is a perspective view illustrating a configuration of mounting the memory cell array4j.

In the memory cell array4j, a third conductive layer16, a second memory layer17, and a fourth conductive layer18are further stacked. The third conductive layer16includes bit lines BL″-1to BL″-3. The second memory layer17includes memory cells MC″ (1,1) to MC″ (3,3). The fourth conductive layer18includes word lines WL″-1to WL″-3. A three-dimensional cross-point type memory cell array4jis configured in a manner such that each of the bit lines BL and BL′ extends in the X-direction, each of the word lines WL and WL″ extends in the Y-direction, each of the memory cells MC is disposed between the corresponding bit line BL and the corresponding word line WL in the Z-direction, and each of the memory cells MC″ is disposed between the corresponding bit line BL″ and the corresponding word line WL″ in the Z-direction.

FIG. 13Ais a cross-sectional view illustrating the layer configuration of the memory cell array4j.

The third conductive layer16includes a conductive film16afunctioning as the bit line BL″. The conductive film16ais disposed on the substrate10. The substrate10may be formed of a material containing a semiconductor such as silicon, as the main component. The conductive film16amay be formed of a material containing tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), cobalt (Co), and nitrides thereof, as the main component.

The second memory layer17includes a diode layer17a, a first electrode layer17b, a variable resistance layer17c, and a second electrode layer17dfrom the lower layer to the upper layer.

The diode layer17ais formed on the upper surface of the conductive film11a. The diode layer17afunctions as a diode. The diode layer17ais formed to have a metal-insulator-metal (MIM) structure or a P+ poly-silicon-intrinsic-N+ poly-silicon (PIN) structure, for example. In a case of the PIN structure, the diode layer17ahas a configuration, for example, in which an N-type layer, an I-type layer, and a P-type layer are stacked. The N-type layer is formed of a semiconductor (for example, silicon) containing N-type impurities such as arsenic and phosphorus. The I-type layer does not contain impurities and is formed of so-called an intrinsic semiconductor (for example, silicon). The P-type layer is formed of a semiconductor (for example, silicon) containing P-type impurities such as boron.

The first electrode layer17bis formed on the upper surface of the diode layer17a. The first electrode layer17bmay be formed of a material containing TiN or TaN as the main component, or may be formed of a material containing TiO2as the main component and doped with Pt, W, WN, or Nb.

The variable resistance layer17cis formed on the upper surface of the first electrode layer17b. The variable resistance layer17cfunctions as a variable resistance element. The variable resistance layer17cmay be formed of a material comprising a material selected from the group consisting of ZnMn2O4, NiO, HfO, TiO2, SrZrO3, Pr0.7Ca0.3MnO3, SrTi1-xNbxO3, Sm0.7Ca0.3MnO3, GdOx, Fe3O4, γ-Fe2O3, GeSe, and Cu2S, as the main component. For example, a hafnium oxide (HfOx) may be utilized in variable resistance layer17c.

The second electrode layer17dis formed on the upper surface of the variable resistance layer17c. The second electrode layer17dmay be formed of a material containing TiN or TaN as the main component, or may be formed of a material containing TiO2as the main component and doped with Pt, W, WN, or Nb.

The fourth conductive layer18includes a conductive film18afunctioning as the bit line BL″. The conductive film18ais disposed on the second electrode layer17d. The conductive film18amay be formed of a material containing tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), cobalt (Co), and nitrides thereof, as the main component.

The second memory layer17may comprise an insulating substance in the variable resistance layer17c. However, for example, forming is performed, and thereby the resistivity of the second memory layer17can be altered to be lower than the resistivity of the interlayer insulating film22(seeFIG. 13A) in the memory cell array4j.

The capacitive circuit5jmay be configured as illustrated inFIG. 10B, for example.FIG. 10Bis a circuit diagram illustrating a configuration of the capacitive circuit5j. The capacitive circuit5jincludes connection lines CL′-1and CL′-2and connection lines CL″-1and CL″-2and connection plugs CP-1to CP-2instead of the plurality of connection lines CL-1and CL-2(compareFIG. 2B) and further includes bit lines BLa″-1to BLa″-5, a memory lines ML″-1to ML″-5, and word lines WLa″-1to WLa″-5.

Each bit line BLa″ (indicated by a dot-dash line inFIG. 10B) extends in parallel with a word line WLa″ (indicated by a solid line illustrated inFIG. 10B). When viewed from the Z-direction, each bit line BLa″ overlaps the word line WLa″. The bit lines BLa″-1to BLa″-5is arranged in an interlayer insulating film22(seeFIG. 13A). The bit lines BLa″ are at a predetermined pitch in the Y-direction and extend in the X-direction.FIG. 10Billustrates a case where the five bit lines BLa″ are disposed. However, the number of bit lines BLa″ is not limited to that depicted inFIG. 10B.

Each of the word lines WLa″ extends in parallel with a bit line BLa″. When viewed from the Z-direction, each word line WLa″ overlaps a bit line BLa″. The plurality of word lines WLa″-1to WLa″-5is in the interlayer insulating film22(seeFIG. 13A) above the bit lines BLa″-1to BLa″-5. The word lines WLa″ are at a predetermined pitch in the Y-direction and extend in the X-direction.FIG. 10Billustrates a case where the five word lines WLa″ are disposed. However, the number of word lines WLa″ is not limited to that depicted inFIG. 10B.

Each memory line ML″ (indicated by a dotted line inFIG. 10B) is interposed between the corresponding word line WLa″ and the corresponding bit line BLa″. The memory line ML″ is in contact with the bit line BLa″ on the −Z-side and is in contact with the word line WLa″ on the +Z-side. Each of the memory lines ML″ extends in parallel with a bit line BLa″ and a word line WLa″. When viewed from the Z-direction, each memory line ML″ overlaps a bit line BLa″ and a word line WLa″ overlaps each memory line ML″. The memory lines ML″ are at a predetermined pitch in the Y-direction and extend in the X-direction.FIG. 10Billustrates a case where the five memory lines ML″ are disposed. However, the number of memory lines ML″ is not limited to that depicted inFIG. 10B.

The connection lines CL″-1and CL″-2(indicated by solid lines inFIG. 10B) are disposed along an XY plane and extend in a direction (Y-direction) intersecting with the word lines WLa″ and the bit lines BLa″. The connection plugs CP-1and CP-2(indicated by dotted lines inFIG. 10B) are between the connection lines CL-1and CL-2and the connection lines CL″-1and CL″-2, respectively. The connection plugs CP-1and CP-2extend in the Z-direction. As depicted inFIG. 10B, connection plug CP-1connects connection line CL-1to connection line CL″-1, and connection plug CP-2connects connection line CL-2to connection line CL″-2.

The connection line CL″-1is disposed on the +X-side of the plurality of word lines WLa″-1to WLa″-5and connects the odd-numbered word lines WLa″-1, WLa″-3, and WLa″-5to each other from among the plurality of word lines WLa″-1to WLa″-5. The connection plug CP-1connects the connection line CL″-1and the connection line CL-1to each other. Thus, an electrode ELj-1may be formed. That is, the bit line BLa″-1, the memory line ML″-1, and the word line WLa″-1forms a portion of the electrode ELj-1. The bit line BLa″-3, the memory line ML″-3, and the word line WLa″-3form another portion of the electrode ELj-1. The bit line BLa″-5, the memory line ML″-5, and the word line WLa″-5form another portion of the electrode ELj-1. The connection line CL″-1and the connection plug CP-1form a portion connecting the other portions of the electrode ELj-1. The electrode EL-1(seeFIG. 2B) in the first embodiment may be a portion of the electrode ELj-1.

The connection line CL″-1connects the word lines WLa″-1, WLa″-3, and WLa″-5to each other. Alternatively, the connection line CL″-1may connect the bit lines BLa″-1, BLa″-3, and BLa″-5to each other.

The connection line CL″-2is disposed on the −X-side of the plurality of word lines WLa″-1to WLa″-5and connects the word lines WLa″-2and WLa″-4to each other from among the plurality of word lines WLa″-1to WLa″-5. The connection plug CP-2connects the connection line CL″-2and the connection line CL-2to each other. Thus, an electrode ELj-2may be formed. That is, the bit line BLa″-2, the memory line ML″-2, and the word line WLa″-2form a portion of the electrode ELj-2. The bit line BLa″-4, the memory line ML″-4, and the word line WLa″-4form another portion of the electrode ELj-2. The connection line CL″-2and the connection plug CP-2form a portion connection other portions of the electrode ELj-2. The electrode EL-2(seeFIG. 2B) in the first embodiment may be a portion of the electrode ELj-2.

The connection line CL″-2connects the word lines WLa″-2and WLa″-4to each other. Alternatively, the connection line CL″-2may connect the bit lines BLa″-2and BLa″-4to each other.

In the capacitive circuit5jillustrated inFIG. 10B, the comb tooth-like electrodes ELj-1and the comb tooth-like electrodes ELj-2are respectively formed. Portions of the electrode ELj-1on the −Z-side and portions of the electrode ELj-2on the −Z-side are arranged so that the teeth of one comb come between the teeth of the other via the interlayer insulating film21(seeFIG. 13A) while being spaced from each other in the XY directions, respectively. Portions of the electrode ELj-1on the +Z-side and portions of the electrode ELj-2on the +Z-side are arranged so that the teeth of one comb come between the teeth of the other via the interlayer insulating film22(seeFIG. 13A) while being spaced from each other in the XY directions, respectively. Portions of the electrode ELj-1on the −Z-side and portions of the electrode ELj-2on the +Z-side are arranged to be spaced from each other via the interlayer insulating film23(seeFIG. 13A) in the Z-direction, respectively. Portions of the electrode ELj-1on the +Z-side and portions of the electrode ELj-2on the −Z-side are arranged to be spaced from each other via the interlayer insulating film23(seeFIG. 13A) in the Z-direction, respectively. That is, the electrode ELj-1and the electrode ELj-2may constitute a MIM structure in which capacitance is formed of a conductive layer, an insulating layer, and a conductive layer including two sets of MOM structures.

A circuit configuration illustrated inFIG. 10Bmay be formed in a manner as illustrated inFIG. 12, for example.FIG. 12is a perspective view illustrating a configuration of mounting the capacitive circuit5j.

In the capacitive circuit5j, a third conductive layer16, a second memory layer17, and a fourth conductive layer18are further stacked. A plug layer19is disposed between the second conductive layer13and the fourth conductive layer18. The third conductive layer16, the second memory layer17, and the fourth conductive layer18are layers which are commonly used as the third conductive layer16, the second memory layer17, and the fourth conductive layer18in the memory cell array4j, respectively.

The third conductive layer16includes bit lines BLa″-1to BLa″-5. The second memory layer17includes memory lines ML″-1to ML″-5. The fourth conductive layer18includes word lines WLa″-1to WLa″-5and connection lines CL″-1and CL″-2. The plug layer19includes connection plugs CP-1and connection plugs CP-2. Each of the bit lines BLa and BLa″, each of the memory lines ML and ML″, and each of the word lines WLa and WLa″ extend in the X-direction. The connection line CL-1connects the even numbered word lines WLa-2and WLa-4having to each other on the +X-side. The connection line CL-2connects the odd-numbered word lines WLa-1, WLa-3, and WLa′-5to each other on the −X-side. The connection line CL″-1connects the word lines WLa″-1, WLa″-3, and WLa″-5to each other on the +X-side. The connection line CL″-2connects the word lines WLa″-2and WLa″-4to each other on the −X-side. A connection plug CP-1connects the connection line CL-1and the connection line CL″-1to each other. A connection plug CP-2connects the connection line CL-2and the connection line CL″-2to each other. In this manner, the capacitive circuit5jof a MIM structure type including two sets of MOM structures is formed.

FIG. 13Bis a cross-sectional view illustrating the layer configuration of the capacitive circuit5j.

The third conductive layer16includes a conductive film16a1functioning as the bit line BLa″. The conductive film16a1is disposed on the substrate10. The substrate10may be formed of a material containing a semiconductor such as silicon, as the main component. The conductive film16a1may be formed of a material containing tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), cobalt (Co), and nitrides thereof, as the main component.

The second memory layer17includes a diode layer17a1, a first electrode layer17b1, a variable resistance layer17c1, and a second electrode layer17d1from the lower layer to the upper layer.

The diode layer17a1is formed on the upper surface of the conductive film13a1. The diode layer17a1functions as a diode. The diode layer17a1is formed to have a metal-insulator-metal (MIM) structure or a P+ poly-silicon-intrinsic-N+ poly-silicon (PIN) structure, for example. In a case of the PIN structure, the diode layer17a1has a configuration, for example, in which an N-type layer, an I-type layer, and a P-type layer are stacked. The N-type layer is formed of a semiconductor (for example, silicon) containing N-type impurities such as arsenic and phosphorus. The I-type layer does not contain impurities and is formed of so-called an intrinsic semiconductor (for example, silicon). The P-type layer is formed of a semiconductor (for example, silicon) containing P-type impurities such as boron. The diode layer17a1corresponds to the diode layer17a(seeFIG. 13A) in the memory cell array4j.

The first electrode layer17b1is formed on the upper surface of the diode layer17a1. The first electrode layer17b1may be formed of a material containing TiN or TaN as the main component, or may be formed of a material containing TiO2as the main component and doped with Pt, W, WN, or Nb. The first electrode layer17b1corresponds to the first electrode layer17b(seeFIG. 13A) in the memory cell array4j.

The variable resistance layer17c1is formed on the upper surface of the first electrode layer17b1. The variable resistance layer17c1functions as a variable resistance element. The variable resistance layer17c1may be formed of a material comprising a material selected from a group consisting of ZnMn2O4, NiO, HfO, TiO2, SrZrO3, Pr0.7Ca0.3MnO3, SrTi1-xNbxO3, Sm0.7Ca0.3MnO3, GdOx, Fe3O4, γ-Fe2O3, GeSe, and Cu2S, as the main component. The variable resistance layer17c1corresponds to the variable resistance layer17c(seeFIG. 13A) in the memory cell array4j.

The second electrode layer17d1is formed on the upper surface of the variable resistance layer17c1. The second electrode layer17d1may be formed of a material containing TiN or TaN as the main component, or may be formed of a material containing TiO2as the main component and doped with Pt, W, WN, or Nb. The second electrode layer17d1corresponds to the second electrode layer17d(seeFIG. 13A) in the memory cell array4j.

The fourth conductive layer18includes a conductive film18a1functioning as the bit line BL′ and a conductive film18a2functioning as the connection line CL′. The conductive film18a1is disposed on the second electrode layer17d1. The conductive films18a1and18a2may be formed of a material containing tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), ruthenium (Ru), cobalt (Co), and nitrides thereof, as the main component. The conductive film18a1corresponds to the conductive film18a(seeFIG. 13A) in the memory cell array4j.

The second memory layer17may contain an insulating substance in the variable resistance layer17c1and the like. However, for example, forming is performed, and thereby the resistivity of the second memory layer17can be set lower than the resistivity of the interlayer insulating film22(seeFIG. 13A) in the memory cell array4j.

As described above, in the third embodiment, in the capacitive circuit5jof the semiconductor device1j, a MOM structure is formed in a manner such that the bit line BLa, the memory line ML, and the word line WLa overlap each other in a line and a MOM structure is formed in a manner such that the bit line BLa″, the memory line ML″, and the word line WLa″ overlap each other in a line. Together the two MOM structures thus formed constitute a MIM structure. With such a configuration, it is also possible to form the capacitive circuit5jhaving high capacitance per unit area using the same microfabrication processes used for forming the plurality of bit lines and the plurality of word lines in the memory cell array4j. Thus, it is also possible to increase the density and the capacitance of the capacitive circuit5jand to reduce the circuit area of the capacitive circuit5jhaving required capacitance.

In the third embodiment, in the semiconductor device1j, the memory cell array4j, and the capacitive circuit5jface each other. Thus, it is possible to form the memory cell array4jand the capacitive circuit5jwith the same steps. Accordingly, it is possible to easily achieve both reduction of the cost of the semiconductor device1jand an increase of the density of the capacitive circuit5j.

In the first to third embodiments, a mechanism for causing layout density of the pattern in the memory cell array equal that in the capacitive circuit may be adopted by causing the shape of the pattern of the memory layer in the memory cell array area to differ from that in the capacitive circuit area.

For example, layout density may be equalized by modifying the arrangement pitch (layout gap) in the capacitive circuit area. That is, as illustrated inFIGS. 14A and 14B, when the line width L2of the memory lines ML in a capacitive circuit5kis equal to the width L1of the memory cells MC in a memory cell array4k, the arrangement pitch G2of the memory lines ML in the capacitive circuit5kmay be wider than the arrangement pitch G1of the memory cells MC in the memory cell array4k.FIGS. 14A and 14Bare plan views illustrating configurations of the memory cell array4kand the capacitive circuit5kaccording to a first modification example applicable to the first to third embodiments. As illustrated inFIGS. 14A and 14B, in the memory cell array4k, when the layout width of the memory cells MC in the X-direction and the layout width thereof in the Y-direction are each set as L1, and the layout gap in the X-direction and the layout gap in the Y-direction are each set as G1(≅L1), the layout density of the memory layer12in the memory cells MC is about 25%. In the capacitive circuit5k, when the layout width of the memory line ML in the Y-direction is set as L2(≅L1), if the layout gap thereof in the Y-direction is set as G2(≅L2×3), the layout density of the memory line ML in the memory layer12may be set to about 25%. That is, the layout density of the pattern of the memory layer12in the memory cell array4kcan be set to be equal to that in the capacitive circuit5k.

Alternatively, for example, the layout density may be set to be equal by adjusting the line widths (layout widths). That is, in the memory layer12, as illustrated inFIGS. 15A and 15B, when the arrangement pitch P2of the memory line ML in a capacitive circuit5nis equal to the arrangement pitch P1of the memory cell MC in a memory cell array4n, the line width L3of the memory line ML in the capacitive circuit5nmay be less than the width L1of the memory cell MC in the memory cell array4n.FIGS. 15A and 15Bare plan views illustrating configurations of the memory cell array4nand the capacitive circuit5naccording to a second modification example applicable to the first to the third embodiments. As illustrated inFIGS. 15A and 15B, in the memory cell array4n, when the layout width of the memory cell MC in the X-direction and the layout width in the Y-direction are set as L1(≅P1×½), and the layout gap in the X-direction and the layout gap in the Y-direction are set as G1(≅L1≅P1×½), the layout density of the memory cell MC in the memory layer12may be set to about 25%. In the capacitive circuit5n, when the layout width of the memory line ML in the Y-direction is set as L3(≅P2×¼<L1≅P1×½), if the layout gap thereof in the Y-direction is set as G3(≅L3×3≅P2×¾), the layout density of the memory line ML in the memory layer12may be set to about 25%. That is, the layout density of the pattern of the memory layer12in the memory cell array4ncan be set to be equal to that in the capacitive circuit5n.

In the first to third embodiments, the write circuit6(seeFIG. 1) may be used to write/set a low resistance state in each memory line ML of the capacitive circuit5. In such a case, as illustrated inFIG. 16, a switching circuit31may be provided between the capacitive circuit5and the write circuit6. FIG. is a circuit diagram illustrating a configuration for writing/setting a low resistance state in memory lines ML of the capacitive circuit5.

The switching circuit31is capable of switching an electrical connection configuration between the capacitive circuit5and the write circuit6, in accordance with a control signal supplied by the control circuit9(seeFIG. 1) or a control signal supplied externally. As depicted inFIG. 16, the write circuit6has a node6aand a node6b. The switching circuit31is capable of separately connecting each word line WLa and bit line BLa adjacent to each memory line ML via the node6aand the node6bto the write circuit6.

The switching circuit31includes switches SWw1, SWb1, SWw2, SWb2, SWw3, SWb3, SWw4, SWb4, SWw5, and SWb5. The switch SWw1is electrically connected between the word line WLa-1and the node6a. The switch SWb1is electrically connected between the bit line BLa-1and the node6b. The switch SWw2is electrically connected between the word line WLa-2and the node6a. The switch SWb2is electrically connected between the bit line BLa-2and the node6b. The switch SWw3is electrically connected between the word line WLa-3and the node6a. The switch SWb3is electrically connected between the bit line BLa-3and the node6b. The switch SWw4is electrically connected between the word line WLa-4and the node6a. The switch SWb4is electrically connected between the bit line BLa-4and the node6b. The switch SWw5is electrically connected between the word line WLa-5and the node6a. The switch SWb5is electrically connected between the bit line BLa-5and the node6b.

For example, when the switches SWw1and SWb1in the switching circuit31are turned ON, the write circuit6applies a predetermined reset voltage across the word line WLa-1and the bit line BLa-1, and thereby a low resistance state can be written in the memory line ML-1. When the switches SWw2and SWb2in the switching circuit31are turned ON, the write circuit6applies the predetermined reset voltage across the word line WLa-2and the bit line BLa-2, and thereby a low resistance state can be written in the memory line ML-2. When the switches SWw3and SWb3in the switching circuit31are turned ON, the write circuit6applies the predetermined reset voltage across the word line WLa-3and the bit line BLa-3, and thereby a low resistance state can be written in the memory line ML-3. When the switches SWw4and SWb4in the switching circuit31are turned ON, the write circuit6applies the predetermined reset voltage across the word line WLa-4and the bit line BLa-4, and thereby a low resistance state can be written in the memory line ML-4. When the switches SWw5and SWb5in the switching circuit31are turned ON, the write circuit6applies the predetermined reset voltage across the word line WLa-5and the bit line BLa-5, and thereby a low resistance state can be written in the memory line ML-5.

In the first to third embodiments, a test circuit7(seeFIG. 1) may perform a test as to whether an insulating property is maintained between the different electrodes EL of the capacitive circuit5(e.g., there is a test for a short-circuit failure). In this case, for example, as illustrated inFIG. 17, a switching circuit32may be provided between the capacitive circuit5and the test circuit7.FIG. 17is a circuit diagram illustrating a configuration for testing the capacitive circuit5.

The switching circuit32is capable of switching an electrical connection configuration between the capacitive circuit5and the test circuit7, for example, in accordance with a control signal from the control circuit9(seeFIG. 1) or a control signal supplied from the outside. The test circuit7has a node7aand a node7b. The switching circuit32is capable of connecting different portions of the electrodes EL-1and EL-2to the node7aand the node7bof the test circuit7.

The timing at which the test circuit7and the switching circuit32perform a test for the capacitive circuit5may be before the capacitive circuit5is used. For example, this testing may occur after the semiconductor device is manufactured, but before the semiconductor device is used in normal operations (post-shipment operations), or the timing may be each time power is supplied to the semiconductor device (e.g., startup/initialization).

The switching circuit32includes switches SWw1, SWb1, SWw2, SWb2, SWw3, SWb3, SWw4, SWb4, SWw5, SWb5, SWc1, and SWc2. The switch SWw1is electrically connected between the word line WLa-1and the node7b. The switch SWb1is electrically connected between the bit line BLa-1and the node7a. The switch SWw2is electrically connected between the word line WLa-2and the node7b. The switch SWb2is electrically connected between the bit line BLa-2and the node7a. The switch SWw3is electrically connected between the word line WLa-3and the node7b. The switch SWb3is electrically connected between the bit line BLa-3and the node7a. The switch SWw4is electrically connected between the word line WLa-4and the node7b. The switch SWb4is electrically connected between the bit line BLa-4and the node7a. The switch SWw5is electrically connected between the word line WLa-5and the node7b. The switch SWb5is electrically connected between the bit line BLa-5and the node7a. The switch SWc1is electrically connected between the connection line CL-1and the node7a. The switch SWc2is electrically connected between the connection line CL-2and the node7b.

For example, when at least one of the switches SWw2, SWb2, SWw4, SWb4, and SWc1and at least one of the switches SWw1, SWb1, SWw3, SWb3, SWw5, SWb5, and SWc2in the switching circuit31is turned ON, the test circuit7is capable of performing a test as to whether an electrical short circuit has formed between the electrode EL-1and the electrode EL-2. When resistivity between the electrode EL-1and the electrode EL-2is equal to or lower than some threshold resistivity, the test circuit7can output an error signal to the control circuit9or otherwise. The error signal indicates that a short-circuit failure has occurred.

For example, when near patterning resolution limit manufacturing conditions for the semiconductor device are adapted from the memory cell array fabrication to the fabrication of the capacitive circuit5, the manufacturing yield of the capacitive circuit5may not be high. For example, if a short-circuit failure occurs in any portion of the capacitive circuit5, it may not be possible to use a circuit connected to the capacitive circuit5, and thus there is a possibility that using the semiconductor device itself is not possible (faulty). In consideration of this point, the switching circuit32, as illustrated inFIG. 17, is provided between the capacitive circuit5and a circuit using the capacitive circuit5(for example, power source circuit8and/or control circuit9illustrated inFIG. 1). Thus, in a case where it is determined by a test that a short-circuit failure occurs in the capacitive circuit5, the switching circuit32can cut off an electrical connection between the capacitive circuit5and the circuit using the capacitive circuit5. As a result, it is possible to avoid an occurrence in which using the entirety of the semiconductor device itself is rendered faulty by a faulty capacitive circuit5.

As illustrated inFIG. 18, a capacitive circuit5-1and a capacitance use circuit35-1and a capacitive circuit5-2and a capacitance use circuit35-2may be prepared as different sets.FIG. 18is a circuit diagram illustrating a configuration including capacitive circuits5-1and5-2, capacitance use circuits35-1and35-2, and test circuit7according to a fifth modification example applicable to the first to the third embodiments. For example, the capacitance use circuits35-1and35-2correspond to the power source circuit8and/or the control circuit9illustrated inFIG. 1. The test circuit7illustrated inFIG. 18may test the capacitive circuit5-1and the capacitive circuit5-2. The test circuit7may operate to stop operation of a faulty capacitive circuit5and utilize a non-faulty capacitive circuit5. The test circuit7may supply a select signal to a selector34in accordance with a test result to select between the different capacitive circuits5(e.g.,5-1and5-2). The test circuit7may cause an output from the capacitance use circuit35connected to the non-faulty capacitive circuit5to be utilized.