Method of forming cobalt contact module and cobalt contact module formed thereby

The disclosure relates to a method of forming a Co contact module, the method including depositing a liner layer on a trench block, partially plating the lined trenches with Co as a first metal such that the resulting Co layer has a top surface below an opening top surface of a shallowest trench, depositing a second metal on the Co layer and exposed surfaces of the liner layer, planarizing the second metal layer, and etching the second metal layer and portions of the liner layer. The disclosure also relates to a Co contact module formed by the noted method.

TECHNICAL FIELD

The subject matter disclosed herein relates to cobalt contact modules of semiconductors. More specifically, various aspects described herein relate to a method of forming a cobalt contact module and the cobalt contact module formed thereby.

BACKGROUND

The semiconductor industry has experienced rapid growth. Technological advances in semiconductor materials and design have produced generations of semiconductors where each generation has smaller and more complex circuits than the previous generation. In the course of semiconductor evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling down process generally produces a relatively high rate of power loss, thus there has been a desire to use a high dielectric constant (high-k) gate dielectrics and metal gate electrodes to improve device performance as feature sizes continue to decrease. In some arrangements of metal integration, patterns etched into a dielectric are filled with metal layers by blanket deposition onto the wafer surface, for example by chemical vapor deposition (CVD).

Chemical mechanical polishing (CMP) has become a key technology driver to achieve local or global wafer planarization for submicron advanced semiconductors. The CMP process is used to planarize and remove excess metal, for example cobalt (Co), over the dielectric and to produce a planar semiconductor structure wherein metal lines or plugs, barrier metal, and exposed dielectric surfaces are coplanar. However, in instances where the semiconductor structure includes a step height between a trench silicide (TS) area and a non-TS area, and where Co is deposited as the metal layer, traditional CMP results in a Co residue remaining on the lower height non-TS area which in turn causes a zero yield in the non-TS area.

BRIEF SUMMARY

Methods of forming a Co contact module and the cobalt contact module formed thereby are disclosed. In a first aspect of the disclosure, a method of forming a Co contact module includes: depositing a liner layer on a trench block, such that the liner layer is deposited over a top surface of the trench block and on sidewalls and bottom portions of trenches of the trench block; partially plating the trenches with Co as a first metal, such that a Co layer is formed within the trenches and a top surface of the Co layer is below an opening top surface of a shallowest trench; depositing a second metal, such that a second metal layer is formed over the Co layer and exposed surfaces of the liner layer and a top surface of the second metal layer is above an opening top surface of a deepest trench; planarizing the second metal layer, such that the top surface of the second metal layer becomes approximately coplanar with the opening top surface of the deepest trench; and etching the second metal layer and portions of the liner layer, such that a top surface of the etched second metal layer is approximately coplanar with the opening top surface of the shallowest trench.

A second aspect of the disclosure includes a Co contact module including: a trench block having trenches; a liner layer on sidewalls and bottom portions of the trenches, the liner layer being present on the sidewalls no higher than an opening top surface of a shallowest trench; a Co layer within the lined trenches, the Co layer having a top surface below the opening top surface of the shallowest trench; and a second metal layer on the Co layer, the second metal layer having a top surface approximately coplanar with the opening top surface of the shallowest trench.

DETAILED DESCRIPTION

The subject matter disclosed herein relates to cobalt contact modules of semiconductors. More specifically, various aspects described herein relate to a method of forming a cobalt contact module and the cobalt contact module formed thereby.

As noted above, conventional CMP techniques used to planarize and remove excess metal, for example cobalt (Co), from semiconductor structures including a step height between gates, for example between a trench silicide (TS) area and a non-TS area, typically result in a Co residue remaining on the lower height non-TS area which in turn causes a detrimental zero yield in the non-TS area.

FIGS. 1A-1C(prior art) depict the conventional methods of forming a Co contact module100(FIG. 1C) of a semiconductor.FIG. 1Ashows a trench block110with an approximately 35 nm step height120between gates130/140.FIG. 1Bshows conventional Co plating150of trench block110.FIG. 1Cshows conventional planarizing of the Co plated trench block wherein there remains a Co residue160on top of the lower gates140having a thickness approximately equal to the 35 nm step height120.

In contrast to the conventional methods, various aspects of the disclosure include a method of forming a Co contact module, the method including depositing a liner layer on a trench block, partially plating the lined trenches of the trench block with Co as a first metal such that the Co layer has a top surface below an opening top surface of a shallowest trench, depositing a second metal on the Co layer and exposed surfaces of the liner layer, planarizing the second metal layer, and etching the second metal layer and portions of the liner layer.

The partial Co plating of the disclosure, as opposed to the conventional full Co plating, does not produce Co residue on top of the lower gates. When Co residue is present on top of the lower gates, the Co is not able to be adequately etched and results in a zero yield at the lower gates.

The second metal layer of the disclosure, for example tungsten (W) or copper (Cu), is deposited on the Co layer and is present on top of the lower gates before planarizing. When the second metal (e.g., W or Cu) is present on top of the lower gates, the second metal and portions of the liner layer are easily etched such that the top surface of the etched second metal layer is approximately coplanar with the opening top surface of the shallowest trench.

The partial Co plating and second metal deposition of the disclosure eliminates the stated problem of the prior art, namely zero yield at the lower gates. Furthermore, since Co, W and Cu have similar electrical conductivities and resistivities, the Co contact module produced according to the disclosure is stable and maintains satisfactory conductivity and resistivity levels.

FIGS. 2A-2Fillustrate steps of a process in forming a cobalt contact module according to various embodiments of the disclosure.FIG. 2Ashows a trench block210with a step height220between upper gates230in a trench silicide (TS) area and lower gates240in a non-TS area, the gates230/240being formed on substrate201with trenches202therebetween. It is understood that substrate201can include any conventional substrate materials, e.g., silicon, germanium, silicon germanium, silicon carbide, etc. Upper gates230and lower gates240can be any gate electrode, including high-k metal gates. Step height220can be 30 nanometers (nm) or more, or within the range of 30 nm to 40 nm, or approximately 35 nm.

FIG. 2Bshows the deposition of a liner layer245on trench block210. The liner layer245is deposited such that liner layer245forms over a top surface246and on sidewalls247and bottom portions248of trenches202of trench block210. Liner layer245may contain Co, Ta, TaN, Ti, TiN, Ru or combinations thereof. Liner layer245may be deposited via any now known or later developed techniques appropriate for the material to be deposited as noted below. Liner layer245is preferably deposited via chemical vapor deposition (CVD).

As used herein, “depositing” may include any now known or later developed techniques appropriate for the material to be deposited including but are not limited to, for example:

FIG. 2Cshows partial Co plating of trench block210to form Co layer250. Co layer250is formed within trenches202and has a top surface251below an opening top surface252of a shallowest trench202A. Due to the top surface251of Co layer250being below opening top surface252, Co residue is not substantially produced on top of lower gates240.FIG. 3shows a TEM image of the Co partial plating progression fromFIG. 2A(left) toFIG. 2C(right).

As can be seen fromFIG. 3, the partial Co plating fills the trenches from the bottom up. Such bottom-up growth is the result of the plating rate at the bottom on the trenches being higher than the plating rate above the opening top surfaces of the trenches, a chamfer area of the trenches and the trench sidewall area near the chamfer area. This difference in plating rates is due to the use of a cobalt plating bath containing, among other things, one or more suppressors. The suppressors are any long molecules suitable for the purpose of suppressing. An example suppressor is polyethylene glycol having a molecular weight of 3400 or more. Other components that may be present in the plating bath include CoSO4, boric acid and/or H2SO4.

The suppressors absorb on the top surfaces of the trench block as well as on the chamfer areas of the trenches and the trench sidewall areas near the chamfer area. Thus, the plating overpotential in these areas (top surfaces, chamfers, sidewalls near chamfers) increases and receives minimal plating as compared to the lower plating overpotential at the bottom of the trenches. Minimal plating refers to plating of approximately 2 to 6%. Such minimal plating does not interfere with the yield of the lower gates discussed above.

FIG. 2Dshows deposition of a second metal on trench block210. Second metal layer255is formed over the partially plated Co layer250and exposed portions of liner layer245. Second metal layer255has a top surface256above an opening top surface257of a deepest trench202B. The second metal is tungsten or copper. Second metal layer255may be deposited via any now known or later developed techniques appropriate for the material to be deposited as noted above. Second metal layer255is preferably deposited via physical vapor deposition (PVD).

FIG. 2Eshows planarizing of the second metal layer on trench block210. Planarized second metal layer260is formed and has a top surface261approximately coplanar with opening top surface257of deepest trench202B. The planarized second metal layer260may be planarized via any now known or later developed techniques appropriate for the material to be planarized as noted below. Planarized second metal layer260is preferably planarized via chemical mechanical planarizing (CMP).

Planarization refers to various processes that make a surface more planar (that is, more flat and/or smooth). Chemical-mechanical-polishing (CMP) is one currently conventional planarization process which planarizes surfaces with a combination of chemical reactions and mechanical forces. CMP uses slurry including abrasive and corrosive chemical components along with a polishing pad and retaining ring, typically of a greater diameter than a wafer. The pad and wafer are pressed together by a dynamic polishing head and held in place by a plastic retaining ring. The dynamic polishing head is rotated with different axes of rotation (that is, not concentric). This removes material and tends to even out any “topography,” making the wafer flat and planar. Other currently conventional planarization techniques may include: (i) oxidation; (ii) chemical etching; (iii) taper control by ion implant damage; (iv) deposition of films of low-melting point glass; (v) resputtering of deposited films to smooth them out; (vi) photosensitive polyimide (PSPI) films; (vii) new resins; (viii) low-viscosity liquid epoxies; (ix) spin-on glass (SOG) materials; and/or (x) sacrificial etch-back.

FIG. 2Fshows etching of the planarized second metal layer and exposed portions of the liner layer. Etched second metal layer270is formed and has a top surface271approximately coplanar with opening top surface252of shallowest trench202A. The etched second metal layer270may be etched via any now known or later developed techniques appropriate for the material to be etched. Etched second metal layer270is preferably etched via non-selective reaction ion etching (RIE). The etching of the second metal layer and exposed portions of the liner layer is performed such that the portions of the liner layer245that are removed via the etching are portions located on the top surfaces of trench block210and on the sidewalls of trench portions located above top surface271of etched second metal layer270. The etching does not etch gates230/240due to masking of the gates.

Upon completion of the noted etching, there remains no Co residue, no second metal residue and no liner layer on top of lower gates240. Therefore, as noted above, the Co contact module produced according to the disclosure eliminates the stated problem of the prior art, namely zero yield at the lower gates, and does so while still maintaining stability of the Co/second metal composition and satisfactory conductivity and resistivity levels.

In addition to the method steps discussed above, the method of the disclosure can also include, before the depositing of liner layer245, deposition of titanium or titanium nitride410, followed by dynamic surface anneal (DSA)420(seeFIG. 4). The titanium and titanium nitride may be deposited via any now known or later developed techniques appropriate for the material to be deposited as noted above. Titanium is preferably deposited via radio frequency physical vapor deposition (RFPVD). Titanium nitride is preferably deposited via atom layer deposition (ALD).

Also, the method of the disclosure can further include, between the depositing of the second metal and the planarizing of second metal layer255, back-side and bevel cleaning510(seeFIG. 5).

Additionally, the method of the disclosure can further include, after the etching of the second metal layer and portions of the liner layer, formation of a cap layer610over the second metal layer270and exposed surfaces of gates230/240(seeFIG. 6). The cap layer can contain SiN, SiC, SiCN or combinations thereof.

While the aspects of the disclosure described above relate to a method of forming a cobalt contact module, the below discussed aspects relate to a cobalt contact module formed thereby.

The second metal of the Co contact module of the disclosure can be tungsten or copper. The liner layer of the Co contact module of the disclosure can contain Co, Ta, TaN, Ti, TiN, Ru or combinations thereof.

The trench block of the Co contact module of the disclosure has step height220between upper gates230in a trench silicide (TS) area and lower gates240in a non-TS area. Step height220can be approximately 30 nm or more, or within the range of 30 nm to 40 nm, or approximately 35 nm.

The Co contact module200of the disclosure can further include a cap layer610on the second metal layer270and exposed surfaces of gates230/240(seeFIG. 6). The cap layer can contain SiN, SiC, SiCN or combinations thereof.

As noted above, the Co contact module of the disclosure includes no Co residue, no second metal residue and no liner layer on top of the lower gates, thus eliminating the stated problem of the prior art, namely zero yield at the lower gates. In addition, the Co contact module of the disclosure eliminates the stated problem of the art while still maintaining stability of the Co/second metal composition and satisfactory conductivity and resistivity levels.