Rectifier capable of adjusting gate voltage of transistor and alternator including rectifier

An alternator and a rectifier are provided. The rectifier includes a gate driving circuit, a logic circuit, and a comparison circuit. The gate driving circuit generates a gate voltage, and a control terminal of a transistor receives the gate voltage. The gate driving circuit receives a control signal, and adjusts the gate voltage according to the control signal, so as to control a conductivity degree of the transistor. The logic circuit generates the control signal and a switch signal according to a comparison result and selects a selected voltage according to the switch signal. The comparison result is generated by comparing a sensing voltage of a first terminal of the transistor with the selected voltage.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 108133129, filed on Sep. 12, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Technical Field

The disclosure relates to an alternator and a rectifier, and particularly relates to a rectifier capable of adjusting a gate voltage of a rectifier transistor.

Description of Related Art

In an alternator, a rectifier is often used to rectify an alternating current (AC) input voltage and generate a rectified voltage that may be regarded as a direct current (DC) voltage. According to the related art, the input voltage is often rectified by switching on or off a diode or a transistor. However, when the alternator does not generate electricity, a leakage current of the transistor may consume energy of a battery. Moreover, since noise affects a drain and a source of the transistor, a drain-source voltage is oscillated. When the drain-source voltage is oscillated around a conductive voltage of the rectifier, the transistor may be switched on or off by mistake.

SUMMARY

The disclosure is directed to an alternator and a rectifier, which are adapted to avoid switching on/off a transistor by mistake.

The disclosure provides a rectifier adapted to a transistor. The rectifier includes a gate driving circuit, a logic circuit, and a comparison circuit. The gate driving circuit is coupled to a control terminal of the transistor, and is configured to generate a gate voltage, and the control terminal of the transistor receives the gate voltage. The gate driving circuit receives a control signal, and adjusts the gate voltage according to the control signal, so as to control a conductivity degree of the transistor. The logic circuit is coupled to the gate driving circuit, and generates the control signal and a switch signal according to a comparison result, and selects a selected voltage according to the switch signal. The comparison result is generated by the comparison circuit by comparing a sensing voltage of a first terminal of the transistor with the selected voltage.

The disclosure provides an alternator including a rotor, a stator and a plurality of the aforementioned rectifiers. Each of the rectifiers receives a corresponding AC input voltage as an input voltage, and the rectifiers collectively generate a rectified voltage.

Based on the above description, the rectifier of the disclosure detects a drain voltage of the rectifier transistor to adjust the gate voltage of the rectifier transistor, and switches a comparison reference of the comparison circuit to avoid switching on/off the transistor by mistake, so as to improve a working performance.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1is a schematic diagram of a rectifier according to an embodiment of the disclosure. Referring toFIG. 1, the rectifier100is adapted to a transistor110, and the rectifier100includes a gate driving circuit120, a logic circuit130and a comparison circuit140. The gate driving circuit120is coupled to a control terminal of the transistor110, and the gate driving circuit120provides a gate voltage VG to the control terminal of the transistor110to control a conductivity degree of the transistor110. The logic circuit130is coupled to the gate driving circuit120, and is configured to provide control signals to the gate driving circuit120, and the gate driving circuit120adjusts the conductivity degree of the transistor110according to one of the control signals. The comparison circuit140is coupled to the logic circuit130, the comparison circuit140may compare one of a plurality of selection voltages with a drain voltage VD of the transistor110, and the logic circuit130generates the control signal according to a comparison result.

In the embodiment, the logic circuit130may provide a control signal ENON1, a control signal ENON2and a control signal ENOFF. The gate driving circuit120may adjust the output gate voltage VG according to the control signal ENON1, the control signal ENON2and the control signal ENOFF. For example, when the control signal ENON1has a high logic level, and the control signal ENON2and the control signal ENOFF all have a low logic level, the gate driving circuit120adjusts the gate voltage VG according to the control signal ENON1, such that the transistor110is switched on and has a first conductive impedance. When the control signal ENON2has the high logic level, and the control signal ENON1and the control signal ENOFF all have the low logic level, the gate driving circuit120adjusts the gate voltage VG according to the control signal ENON2, such that the transistor110is switched on and has a second conductive impedance. When the control signal ENOFF has the high logic level, and the control signal ENON1and the control signal ENON2all have the low logic level, the gate driving circuit120adjusts the gate voltage VG according to the control signal ENOFF, so as to switch off the transistor110, where the first conductive impedance is smaller than the second conductive impedance.

In the embodiment, the logic circuit130provides 3 control signals to the gate driving circuit120, which is only an example, and is not used for limiting an implementation scope of the disclosure. In other embodiments, the number of the control signals may be greater than or equal to 2, which is not particularly specified.

The logic circuit130may generate the control signals according to the comparison result of the comparison circuit140, and generates a switch signal CS according to the comparison result. The comparison circuit140may compare one of a plurality of selection voltages with a sensing voltage VD_S, where the sensing voltage VD_S may be a sensing value of the drain voltage VD. Moreover, the comparison circuit140may switch a plurality of the selection voltages according to the switch signal CS. To be specific, a negative input terminal of the comparison circuit140receives the sensing voltage VD_S, and a positive input terminal of the comparison circuit140receives one of the plurality of selection voltages. The comparison circuit140may switch one of the selection voltages to another one of the selection voltages according to the switch signal CS.

FIG. 2is a schematic diagram of a state machine according to an embodiment of the disclosure. Referring toFIG. 1andFIG. 2, in the embodiment, the transistor110may be an N-type transistor, and the selection voltages are respectively a selection voltage VD_ON, a selection voltage VD_OCPand a selection voltage VD_OFF, where the selection voltage VD_ONis an initial selection voltage. The drain voltage VD decreases continuously after entering a negative half cycle. The comparison circuit140compares the sensing voltage VD_S with the selection voltage VD_ON, and when the sensing voltage VD_S is smaller than the selection voltage VD_ON, the logic circuit130generates the control signal ENON1with the high logic level according to the comparison result. Now, the other control signals ENON2and ENOFF may have the low logic level. The gate driving circuit120generates the gate voltage VG according to the control signal ENON1, and the transistor110is switched on and has the first conductive impedance. In this case, the transistor110may be completely switched on, so that the first conductive impedance of the transistor110is very tiny, and the drain voltage VD may be maintained be equal to or close to a voltage value of 0 volt. Now, the state machine is changed from a start state S1to a first stage conductive state S2. Moreover, when the sensing voltage VD_S is smaller than the selection voltage VD_ON, the logic circuit130adjusts the switch signal CS. Moreover, the comparison circuit140selects the selection voltage VD_OCPas a comparison reference according to the adjusted switch signal CS.

When the sensing voltage VD_S is smaller than or equal to the selection voltage VD_OCP, the state machine is maintained to the first stage conductive (rectifying) state S2. When the sensing voltage VD_S is greater than the selection voltage VD_OCP, the logic circuit130generates the control signal ENOFF with the high logic level according to the comparison result. Now, the other control signals ENON1and ENON2may have the low logic level. The gate driving circuit120generates the gate voltage VG according to the control signal ENOFF, so as to switch off the transistor110. Now, the state machine is changed from the first stage conductive (rectifying) state S2to the start state S1. Moreover, when the sensing voltage VD_S is greater than the selection voltage VD_OCP, the logic circuit130adjusts the switch signal CS. Moreover, the comparison circuit140selects the selection voltage VD_ONas a comparison reference according to the adjusted switch signal CS.

In an actual operation, various circuit anomalies may probably result in the sensing voltage VD_S larger than the selection voltage VD_OCP. Now, the gate driving circuit120may switch off the transistor110, and maintain the off state of the transistor110until the next negative half cycle of the drain voltage VD, so as to avoid oscillation of the sensing voltage VD_S near a conductive voltage of the transistor110to cause the transistor to switch on/off by mistake.

Comparatively, after the logic circuit130generates the control signal ENON1for a time interval TR, the logic circuit130generates the control signal ENON2with the high logic level. Now, the other control signals ENON1and ENOFF may have the low logic level. A time counting circuit can be set in the logic circuit130, and the time counting circuit may be implemented by a resistor-capacitor circuit or a timing circuit, so as to generate a value corresponding to a length of the time interval TR. The gate driving circuit120generates the gate voltage VG according to the control signal ENON2, so that the transistor110is partially switched on to have a second conductive impedance, where the second conductive impedance is greater than the first conductive impedance. Now, the state machine is changed from the first stage conductive (rectifying) state S2to a second stage conductive (rectifying) state S3. Moreover, when the logic circuit130generates the control signal ENON1, and maintains for the time interval TR, the logic circuit130adjusts the switch signal CS. The comparison circuit140selects the selection voltage VD_OFFas the comparison reference according to the adjusted switch signal CS.

When the sensing voltage VD_S is smaller than or equal to the selection voltage VD_OFF, the state machine is maintained to the second stage conductive (rectifying) state S3, and now the sensing voltage VD_S is equal to a regulation voltage VD_REG. When the sensing voltage VD_S is greater than the selection voltage VD_OFF, the logic circuit130generates the control signal ENOFF with the high logic level according to the comparison result. Now, the other control signals ENON1and ENON2may have the low logic level. The gate driving circuit120generates the gate voltage VG according to the control signal ENOFF, so as to switch off the transistor110. Now, the state machine is changed from the second stage conductive (rectifying) state S3to the start state S1. Moreover, when the sensing voltage VD_S is greater than the selection voltage VD_OFF, the logic circuit130adjusts the switch signal CS. Moreover, the comparison circuit140selects the selection voltage VD_ONas a comparison reference according to the adjusted switch signal CS.

Moreover, in case a drain and a source of the transistor110are short-circuited, a large current flows through the transistor110, and now a voltage value of the sensing voltage VD_S is rather high. Therefore, when the sensing voltage VD_S is equal to the regulation voltage VD_REG, the state machine is maintained to the second stage conductive (rectifying) state S3. When the sensing voltage VD_S is instantaneously larger than the selection voltage VDD_OCP, the state machine is quickly changed from the second stage conductive (rectifying) state S3to the start state S1. Through such mechanism, the transistor110may be quickly switched off, so as to avoid damage of the transistor110due to the large current.

In the embodiment, one of a plurality of control signals may be enabled, and has a first logic level. The gate driving circuit120may generate the gate voltage VG according to the control signal of the first logic level, and control the conductivity degree of the corresponding transistor through the gate voltage VG. In the embodiment, the first logic level may be the high logic level. Alternatively, in other embodiments of the disclosure, the first logic level may be the low logic level.

In this way, the rectifier100of the disclosure may adjust the gate voltage VG of the transistor110according to the drain voltage VD of the transistor110, so as to implement multi-stage control on the conductivity degree of the transistor110to achieve the rectifying effect. Implementation details of the gate driving circuit120, the logic circuit130and the comparison circuit140are described below.

The logic circuit130is configured to generate the control signal ENON1, the control signal ENON2and the control signal ENOFF according to the comparison result of the comparison circuit140. For example, when the sensing signal VD_S is smaller than the selection voltage VD_ON, the logic circuit130outputs the control signal ENON1of the high logic level, and now the control signal ENON2and the control signal ENOFF all have the low logic level.

The comparison circuit140is configured to compare the sensing signal VD_S with one selection voltage. Moreover, the comparison circuit140may select one of the selection voltage VD_ON, the selection voltage VD_OCPand the selection voltage VD_OFFas the comparison reference according to the switch signal CS.

FIG. 3is a schematic diagram of a comparison circuit according to an embodiment of the disclosure. Referring toFIG. 3, the comparison circuit140includes a voltage generating circuit142, a multiplexer141and an operational amplifier OP. The voltage generating circuit142is coupled to the multiplexer141, and the voltage generating circuit142receives the drain voltage VD, a source voltage VS, an operation power AVDD and a reference ground voltage GND.

The voltage generating circuit142includes a voltage source V1, a voltage source V2and a voltage source V3connected in series with each other. A first end of the voltage source V3may be coupled to the operation power AVDD through a resistor R1. A first end of the voltage source V2is coupled to a second end of the voltage source V3. A first end of the voltage source V1is coupled to a second end of the voltage source V2, and a second end of the voltage source V1may be coupled to the reference ground voltage GND through a resistor R2. The sensing voltage VD_S is provided to the first end of the voltage source V1, and the sensing voltage VD_S is generated by the drain voltage VD through a resistor R3. The source voltage VS is provided to one terminal of the resistor R2adjacent to the reference ground voltage GND. In the embodiment, the source voltage VS may be equal to the reference ground voltage GND.

A first input terminal of the multiplexer141receives a voltage of the first end of the voltage source V3, and a voltage of the first input terminal of the multiplexer141is equal to a sum of the sensing voltage VD_S and voltage values of the the voltage source V2and the voltage source V3. A second input terminal of the multiplexer141receives a voltage of the first end of the voltage source V2, and a voltage of the second input terminal of the multiplexer141is equal to a sum of the sensing voltage VD_S and the voltage source V2. A third input terminal of the multiplexer141receives a voltage of the second end of the voltage source V1, and a voltage of the third input terminal of the multiplexer141is equal to the sensing voltage VD_S minus the voltage source V1. The multiplexer141may output the voltage of the first input terminal of the multiplexer141, the voltage of the second input terminal of the multiplexer141, or the voltage of the third input terminal of the multiplexer141according to the switch signal CS.

The operational amplifier OP receives the operation voltage AVDD, the output voltage of the multiplexer141and a voltage source V0. The operational amplifier OP subtracts the output voltage of the multiplexer141from the voltage source V0to generate the comparison result.

In the embodiment, the voltage source V0may provide a voltage of 20 mV, the voltage source V1may provide a voltage of 10 mV, the voltage source V2may provide a voltage of 50 mV, and the voltage source V3may provide a voltage of 270 mV. In this way, the voltage of the first input terminal of the multiplexer141is the sensing voltage VD_S plus the voltage of 320 mV, the voltage of the second input terminal of the multiplexer141is the sensing voltage VD_S plus the voltage of 50 mV, and the voltage of the third input terminal of the multiplexer141is the sensing voltage VD_S minus the voltage of 10 mV. The operational amplifier OP subtracts the output voltage of the multiplexer141from the voltage source V0as the comparison result. When the output voltage of the multiplexer141is the sensing voltage VD_S plus the voltage of 320 mV, the comparison result is equivalent to a difference between the sensing voltage VD_S and a voltage of −300 mV. When the output voltage of the multiplexer141is the sensing voltage VD_S plus the voltage of 50 mV, the comparison result is equivalent to a difference between the sensing voltage VD_S and a voltage of −30 mV. When the output voltage of the multiplexer141is the sensing voltage VD_S minus the voltage of 10 mV, the comparison result is equivalent to a difference between the sensing voltage VD_S and a voltage of 30 mV.

Referring toFIG. 1, the rectifier100may further include a start circuit150. The start circuit150is configured to provide the operation power AVDD of the comparison circuit140and a plurality of reference voltages Vref, where the reference voltages Vref may serve as the voltage sources V0-V3.FIG. 4is a schematic diagram of a part of a rectifier according to an embodiment of the disclosure. Referring toFIG. 4, the start circuit150may include an operation power generator151and a reference voltage generator152. A first terminal of the operation power generator151is coupled to a voltage VH, a second terminal of the operation power generator151is coupled to the reference ground voltage GND, and a third terminal of the operation power generator151provides the operation power AVDD. The reference voltage generator152receives the operation power AVDD, and provides the voltage source V0-V3according to an enabling signal EN.

An enabling signal generating circuit160is configured to provide the enabling signal EN according to the sensing signal VD_S. InFIG. 4, the enabling signal generating circuit160includes a voltage shifter161, a transistor T1, a diode D1, a diode D2, a switch SW1, an inverter N1and a resistor R3. The diodes D1and D2may be diodes in the form of transistors. A first terminal of the resistor R4is coupled to the operation power AVDD, and a second terminal of the resistor R4provides the enabling signal EN. An input terminal of the inverter N1is coupled to the second terminal of the resistor R4to receive the enabling signal EN, and an output terminal of the inverter N1outputs an inverted enabling signal ENB. A first terminal of the transistor T1is coupled to a second terminal of the resistor R4, a second terminal of the transistor T1is coupled to an anode of the diode D1, and the transistor T1is controlled by an output voltage of the voltage shifter161. An anode of the diode D2is coupled to a cathode of the diode D1, and a cathode of the diode D2is coupled to the reference ground voltage. A first terminal of the switch SW1is coupled to the anode of the diode D2, a second terminal of the switch SW1is coupled to the cathode of the diode D2, and the switch SW1is controlled by the inverted enabling signal ENB. When the inverted enabling signal ENB has the high logic level, the switch SW1is switched on, and is configured to bypass the diode D2.

In another embodiment, the switch SW1may bypass the diode D1. In this case, the first terminal and the second terminal of the switch SW1may be respectively coupled to the anode and the cathode of the diode D1. In another embodiment, the number of the diodes may be greater than 2, and the switch SW1may be configured to bypass a plurality of diodes (for example, the diode D1and the diode D2).

The voltage shifter161is configured to shift a voltage of the sensing signal VD_S, so as to provide the proper voltage to the transistor T1. Referring toFIG. 1andFIG. 4, the rectifier100may further include a resistor R5, a resistor R6, a diode D3and a capacitor C1. A first terminal of the resistor R6is coupled to the drain voltage VD, and a second terminal of the resistor R6provides the sensing signal VD_S. A first terminal of the resistor R5is coupled to the drain voltage VD. An anode of the diode D3is coupled to a second terminal of the resistor R5, and a cathode of the diode D3is coupled to the voltage VH. The capacitor C1is coupled between the voltage VH and the reference ground voltage GND.

Referring toFIG. 2andFIG. 4, when the drain voltage VD is greater than or equal to a sum of the conductive voltage of the transistor T1, a conductive voltage of the diode D1and a conductive voltage of the diode D2, the transistor T1is switched on to form a path P1. Now, the enabling signal EN is pulled down to the low logic level, and the inverted enabling signal ENB has the high logic level, the path P1is cut off, the path P2is formed, and the state machine is in a standby state S0. Namely, a start condition of the enabling signal generating circuit160is that the drain voltage VD is smaller than N×VT1, where VT1represents the conductive voltage of the transistor, and N is a positive integer. In the embodiment, N is equal to 2, and N×VT1may be provided by the transistor T1and the diode D1. When the drain voltage VD is smaller than N×VT1, the transistor T1provides an impedance, and the voltage of the enabling signal EN is pulled up and transited to the high logic level based on a voltage divider rule, and the inverted enabling signal ENB is transited to the low logic level, the path P2is cut off, and the path P1is formed. Now, the state machine is changed from the standby state S0to the start state S1.

Comparatively, when the drain voltage VD is greater than a voltage of (N+M)×VT1, the transistor T1is switched on, and the enabling signal EN is transited to the low logic level, and the inverted enabling signal ENB is transited to the high logic level. Now, the state machine is changed from the start state S1to the standby state S0. Where, M is a positive integer, and the voltage of M×VT1may be provided by the diode D2. In the embodiment, M is equal to 1.

FIG. 5is a schematic diagram of a part of a rectifier according to an embodiment of the disclosure. A difference betweenFIG. 5andFIG. 4lies in an enabling signal generating circuit160′, and descriptions of other components ofFIG. 5may refer to related description of the embodiment ofFIG. 4, which are not repeated. Referring toFIG. 5, the enabling signal generating circuit160′ includes resistors R7-R9, a transistor T2, an inverter N2, a switch SW2and a voltage shifter161′. A first terminal of the resistor R7is coupled to the operation power AVDD, and a second terminal of the resistor R7provides the enabling signal EN. An input terminal of the inverter N2is coupled to the second terminal of the resistor R7to receive the enabling signal EN, and an output terminal of the inverter N2outputs the inverted enabling signal ENB. A first terminal of the transistor T2is coupled to the second terminal of the resistor R7, and a second terminal of the transistor T2is coupled to the reference ground voltage GND. A first terminal of the resistor R8is coupled to the first terminal of the transistor T2, a first terminal of the resistor R9is coupled to a second terminal of the resistor R8, and a second terminal of the resistor R9is coupled to the reference ground voltage GND. To be specific, the switch SW2and the resistor R9may form a variable resistor, the first terminal of the resistor R9is coupled to the first terminal of the switch SW2, the second terminal of the resistor R9is coupled to the reference ground voltage GND, and a third terminal of the resistor R9is coupled to the second terminal of the switch SW2. The switch SW2is constructed by a transistor, and is controlled by the enabling signal EN. In the embodiment, when the enabling signal EN has the high logic level, the switch SW2is switched on to decrease a resistance between the control terminal of the transistor T2and the reference ground voltage GND (which is smaller than a resistance R9′ of the resistor R9). Now, when the drain voltage is raised to [(R9′+R8)/R9′]×VT2from a low level, the transistor T2is switched on, and the enabling signal EN is changed from the high logic level to the low logic level. Comparatively, when the enabling signal EN has the low logic level, the switch SW2is switched off to increase the resistance between the control terminal of the transistor T2and the reference ground voltage GND (which is equal to the resistance of the resistor R9). When the drain voltage is dropped to [(R9+R8)/R9]×VT2from a high level, the transistor T2is switched off, and the enabling signal EN is changed from the low logic level to the high logic level.

According to the above description, it is learned that through the variable resistor formed by the switch SW2and the resistor R9, the conductivity degree of the transistor T2may be adjusted according to the enabling signal EN. Moreover, description of the voltage shifter161′ is the same with that of the voltage shifter161of the embodiment ofFIG. 4, and detail thereof is not repeated.

In the embodiment ofFIG. 5, the resistor R8and the resistor R9are configured to provide N×VT1and (N+M)×VT1mentioned in the embodiment ofFIG. 4. Referring both ofFIG. 2andFIG. 5, when the drain voltage VD is greater than or equal to (N+M)×VT1, a path P3is formed, and the transistor T2is controlled by the voltage of the first terminal of the resistor R9and is at least partially switched on, so that the enabling signal EN is pulled down to the low logic level. Now, the state machine is in the standby state S0. When the drain voltage VD is smaller than NXVT1, the voltage of the first terminal of the resistor R9is decreased, causing the transistor T2to be switched off and a path P4to be cut off. Now, the voltage of the enabling signal EN becomes higher based on the voltage divider rule, the enabling signal EN is accordingly transited to the high logic level, the inverted enabling signal ENB is transited to the low logic level, and a part of the resistor R9is bypassed by the switch SW2. Now, the sate machine is changed from the standby state S0to the start state S1.

Comparatively, when the drain voltage VD is greater than (N+M)×VT1, the transistor T2is switched on, and the enabling signal EN is transited to the low logic level, and the inverted enabling signal ENB is transited to the high logic level. Now, the state machine is changed from the start state S1to the standby state S0, where M×VT1may be provided by the transistor T2. In the embodiment, if R9=2×R9′=2×R8, N is equal to 1.5 and M is equal to 0.5.

In the above embodiment, voltage values of the selection voltage VD_ON, the selection voltage VD_OCPand the selection voltage VD_OFFare respectively equal to −300 mV, 30 mV and −30 mV. In another embodiment, the voltage values of the selection voltage VD_ON, the selection voltage VD_OCPand the selection voltage VD_OFFmay be directly provided to the positive input terminal of the operational amplifier OP.FIG. 6is a schematic diagram of a comparison circuit according to an embodiment of the disclosure. Referring toFIG. 6, the comparison circuit140′ only includes the operational amplifier OP and the multiplexer141. In the embodiment, a reference voltage generator152′ is configured to receive an operation power VHH and the drain voltage VD, and generates the operation power AVDD of the operational amplifier OP, the selection voltage VD_ON, the selection voltage VD_OCPand the selection voltage VD_OFFaccording to the enabling signal EN. The multiplexer141selects the selection voltage VD_ON, the selection voltage VD_OCPor the selection voltage VD_OFFaccording to the switch signal CS. The operational amplifier OP receives the operation power AVDD, the positive input terminal of the operational amplifier OP receives the output voltage of the multiplexer141, the negative input terminal of the operational amplifier OP is coupled to the sensing voltage VD_S, and the operational amplifier OP outputs a voltage difference between the positive input terminal and the negative input terminal. A generation detail of the enabling signal EN of the embodiment may refer to the related descriptions of the embodiments ofFIG. 4andFIG. 5, which is not repeated.

FIG. 7is a waveform schematic diagram according to an embodiment of the disclosure. InFIG. 7, variations of a drain current IDS, the drain voltage VD, the enabling signal EN and the gate voltage VG are drawn. Referring toFIG. 2andFIG. 7, at a time point t1, the enabling signal EN is transited from the low logic level to the high logic level, and now the start circuit generates a plurality of reference voltages Vref. The drain voltage VD decreases continuously after entering a negative half cycle. When the drain voltage VD is greater than or equal to N×VT1, the state machine is maintained to the standby state S0. When the drain voltage VD is smaller than N×VT1(corresponding to the time point t1), the state machine is changed from the standby state S0to the start state S1. When the drain voltage VD is smaller than the selection voltage VD_ON(corresponding to a time point t2), the state machine is changed from the start state S1to the first stage conductive (rectifying) state S2, until a time point t3. Then, at the time point t3after the time interval TR, the state machine is changed to the second stage conductive (rectifying) state S3. Under the second stage conductive (rectifying) state S3, the drain voltage VD is decreased, and is maintained to the regulation voltage VD=VD_REG. When the drain voltage VD is raised and greater than the selection voltage VD_OFF(corresponding to a time point t4), the state machine is changed to the start state S1. Now, the gate voltage VG is decreased, and the transistor executing the rectifying operation is switched off. When the drain voltage VD is greater than the selection voltage (N+M)×VT1(corresponding to a time point t5), the state machine is changed to the standby state S0.

Moreover, in the disclosure, the enabling signal of the control circuit may also be switched off when power is not generated, so that the current consumption can be controlled to the minimum to reduce a leakage current of the transistor.

In summary, in the disclosure, the gate voltage may be adjusted by detecting the drain voltage. Through the configuration of the disclosure, the leakage current of the transistor may be reduced, so as to avoid excessive energy consumption. Moreover, during the rectification of the transistor, the selection voltage is switched to avoid switching on/off the transistor by mistake.