Methods of fabricating semiconductor devices

Methods of fabricating a semiconductor device include forming a gate pattern on a substrate, forming spacers to cover both sidewalls of the gate pattern, forming an interlayer insulating layer to cover the gate pattern and the spacers, and forming contact holes to penetrate the interlayer insulating layer and expose sidewalls of the spacers. The forming of the spacers includes forming a spacer layer to cover the gate pattern and injecting silicon ions into the spacer layer. The spacer layer is a nitride-based low-k insulating layer, whose dielectric constant is lower than that of silicon oxide.

CROSS-REFERENCE TO RELATED APPLICATIONS

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2015-0084318, filed on Jun. 15, 2015, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND OF THE INVENTION

Example embodiments of the inventive concept relate to a semiconductor device and methods of fabricating the same, and in particular, to a semiconductor device with field effect transistors and methods of fabricating the same.

Due to their small-sized, multifunctional, and/or low-cost characteristics, semiconductor devices are being esteemed as important elements in the electronic industry. The semiconductor devices may be classified into a memory device for storing data, a logic device for processing data, and a hybrid device including both of memory and logic elements. To meet the increased demand for electronic devices with fast speed and/or low power consumption, semiconductor devices with high reliability, high performance, and/or multiple functions may be realized. To satisfy these technical requirements, complexity and/or integration density of semiconductor devices may be increased.

SUMMARY

Example embodiments of the inventive concept provide a semiconductor device, in which field effect transistors with improved electric characteristics are provided.

Some example embodiments of the inventive concept provide methods of fabricating a semiconductor device in which field effect transistors with improved electric characteristics are provided.

According to example embodiments of the inventive concept, methods of fabricating a semiconductor device may include forming a gate pattern on a substrate, forming spacers to cover both sidewalls of the gate pattern, forming an interlayer insulating layer to cover the gate pattern and the spacers, and forming contact holes to penetrate the interlayer insulating layer and expose sidewalls of the spacers. The forming of the spacers may include forming a spacer layer to cover the gate pattern and injecting silicon ions into the spacer layer. The spacer layer may be a nitride-based low-k insulating layer, whose dielectric constant may be lower than that of silicon oxide.

In some embodiments, the injecting of the silicon ions may be performed such that the spacer layer has a silicon concentration ranging from 30 at % to 40 at %.

In some embodiments, the injecting of the silicon ions may be performed at a dose ranging from 1.0E14/cm2to 1.0E16/cm2.

In some embodiments, the injecting of the silicon ions may be performed to form a first portion and a second portion in at least one of the spacers, the first portion may be positioned adjacent to the gate pattern, and the second portion may be spaced apart from the gate pattern with the first portion interposed therebetween. At least one of the contact holes may be formed to expose the second portion, and the second portion may have a silicon concentration higher than that of the first portion.

In some embodiments, an etch selectivity of the second portion with respect to the interlayer insulating layer may be higher than that of the first portion with respect to the interlayer insulating layer.

In some embodiments, the second portion may serve as an upper region of the spacer, and the second portion may be formed to have a top surface higher than that of the first portion.

In some embodiments, the second portion may be formed to have a thickness ranging from 2 nm to 20 nm.

In some embodiments, methods may further include forming source/drain regions at both sides of the gate pattern. The contact holes may be formed to be overlapped with the source/drain regions, when viewed in plan view.

In some embodiments, the forming of the spacers may further include forming an etch stop layer on the substrate to cover the spacer layer, and the injecting of the silicon ions may be performed after the forming of the etch stop layer.

In some embodiments, methods may further include forming trenches in the substrate to define active patterns and forming device isolation layers to fill the trenches. The active patterns may be formed to protrude between the device isolation layers, and the gate pattern may be formed to cross the active patterns.

In some embodiments, the gate pattern may be used as a sacrificial gate pattern. In this case, the method may further include a gate last process of replacing the gate pattern with a gate electrode.

According to example embodiments of the inventive concept, methods of fabricating a semiconductor device may include forming a pattern on a substrate and forming spacers to cover both sidewalls of the pattern. The forming of the spacers may include forming a spacer layer to cover the pattern and injecting silicon ions into the spacer layer. The injecting of the silicon ions may be performed to form a first portion and a second portion in at least one of the spacers, the first portion may be positioned adjacent to the pattern, and the second portion may be spaced apart from the pattern with the first portion interposed therebetween. The second portion may have a silicon concentration higher than that of the first portion.

In some embodiments, the spacer layer may be a nitride-based low-k insulating layer, whose dielectric constant is lower than that of silicon oxide. Here, an etch selectivity of the second portion with respect to an oxide-based insulating layer may be higher than that of the first portion with respect to the oxide-based insulating layer.

In some embodiments, the pattern may be used as a sacrificial gate pattern, and the method further include replacing the sacrificial gate pattern with a gate electrode, after the formation of the spacers.

In some embodiments, methods may further include forming source/drain regions at both sides of the sacrificial gate pattern, forming an interlayer insulating layer to cover the gate electrode, the spacers, and the source/drain regions, and forming contact holes to penetrate the interlayer insulating layer and expose the source/drain regions. At least one of the contact holes may be formed to expose the second portion.

Some embodiments of the present inventive concept include methods of fabricating a semiconductor device that include forming a gate pattern on a substrate, forming a spacer layer on sidewalls of the gate pattern that has a nitride-based low-k insulating layer that includes a dielectric constant that is lower than a dielectric constant of silicon oxide, injecting silicon ions into the spacer layer, forming an interlayer insulating layer on the gate pattern and the spacer layer and forming contact holes that penetrate the interlayer insulating layer and expose sidewalls of the spacer layer.

In some embodiments, injecting of the silicon ions is performed to provide that the spacer layer has a silicon concentration ranging from 30 at % to 40 at %. Some embodiments may further include forming spacers on the gate pattern by performing an anisotropic etching process on the spacer layer, the injecting of the silicon ions is performed to form a first portion and a second portion in at least one of the spacers, the first portion is positioned adjacent the gate pattern and the second portion is spaced apart from the gate pattern with the first portion interposed therebetween, at least one of the contact holes exposes the second portion, and the second portion has a silicon concentration that is higher than a silicon concentration of the first portion.

In some embodiments, a portion of the second portion serves as an upper region of the spacer, and the second portion has a top surface that is higher than a top surface of the first portion.

Some embodiments include forming source/drain regions at both sides of the gate pattern, wherein the contact holes overlap with the source/drain regions, when viewed in plan view; forming trenches in the substrate, the trenches defining active patterns; and forming device isolation layers that fill the trenches. In some embodiments, the active patterns protrude between the device isolation layers and the gate pattern crosses the active patterns.

It is noted that aspects of the inventive concept described with respect to one embodiment, may be incorporated in a different embodiment although not specifically described relative thereto. That is, all embodiments and/or features of any embodiment can be combined in any way and/or combination. These and other objects and/or aspects of the present inventive concept are explained in detail in the specification set forth below.

DETAILED DESCRIPTION

Accordingly, the cross-sectional view(s) illustrated herein provide support for a plurality of devices according to various embodiments described herein that extend along two different directions in a plan view and/or in three different directions in a perspective view. For example, when a single active region is illustrated in a cross-sectional view of a device/structure, the device/structure may include a plurality of active regions and transistor structures (or memory cell structures, gate structures, etc., as appropriate to the case) thereon, as would be illustrated by a plan view of the device/structure.

FIG. 1is a plan view illustrating a semiconductor device according to example embodiments of the inventive concept.FIG. 2Ais a sectional view taken along line I-I′ ofFIG. 1to illustrate a semiconductor device according to example embodiments of the inventive concept.

Referring toFIGS. 1 and 2A, a device isolation layer104may be provided on a substrate100to define an active pattern AP. The substrate100may be a semiconductor substrate (e.g., of silicon, germanium, or silicon-germanium) or a compound semiconductor substrate. In some embodiments, the device isolation layer104may include an insulating material, such as silicon oxide. The active pattern AP may correspond to a portion of the substrate100surrounded by the device isolation layer104. The active pattern AP may be a line- or bar-shaped structure extending in a second direction D2parallel to a top surface of the substrate100. Although one active pattern AP is illustrated inFIGS. 1 and 2A, the substrate100may have a plurality of the active patterns AP. In this case, the active patterns AP may be arranged along a first direction D1crossing the second direction D2. The active pattern AP may have a first conductivity type.

Gate electrodes135may be provided on the substrate100. Each of the gate electrodes135may be a line- or bar-shaped structure crossing the active pattern AP and extending parallel to the first direction D1. In some embodiments, the gate electrodes135may be formed of or include at least one of doped semiconductors, conductive metal nitrides (e.g., titanium nitride and/or tantalum nitride), and/or metals (e.g., titanium, tantalum, tungsten, copper, and/or aluminum).

A plurality of gate electrodes135may be provided to cross at least one of the active patterns AP. For example, as illustrated inFIGS. 1 and 2A, a pair of gate electrodes135may be provided on each of the active patterns AP to extend in the first direction D1. Here, the pair of the gate electrodes135may be spaced apart from each other in the second direction D2. For the sake of simplicity, a pair of the gate electrodes135will be described as an example.

Spacers125may be provided on both sidewalls of each of the gate electrodes135. The spacers125may extend along the gate electrodes135or parallel to the first direction D1. Each of the spacers125may have a top surface that is positioned at a higher level than those of the gate electrodes135. Furthermore, the top surface of each of the spacers125may be coplanar with top surfaces of a first interlayer dielectric (ILD) layer150and/or each of gate capping layers145, which will be described below. The spacers125may be formed of a nitride-based low-k insulating layer. The low-k insulating layer may have a dielectric constant lower than that of silicon oxide (SiO2). In some embodiments, the spacers125may have a dielectric constant lower than those of first and second interlayer insulating layers150and155, which will be described below. The spacers125may be formed of or include at least one of SiON, SiCON, and/or SiN. In the case where the spacers125include silicon nitride (SiN), the spacers125may be formed to have a porous structure and thereby to have a reduced dielectric constant. In the case where a low-k insulating layer is used as the spacer125, it is possible to reduce parasitic capacitance between the gate electrode135and a contact165.

Each of the spacers125may include a first portion127adjacent the gate electrode135and a second portion126adjacent the contact165. The second portion126may be spaced apart from the gate electrode135with the first portion127interposed therebetween. The second portion126may be a doped region, which is formed by an ion implantation process IIP of injecting and diffusing silicon ions into the spacer125. In some embodiments, a top surface126T of the second portion126may be coplanar with a top surface127T of the first portion127. A bottom surface126B of the second portion126may be higher than a bottom surface127B of the first portion127. The second portion126may have a thickness ranging from 2 nm to 20 nm. The second portion126may include the same material as the first portion127. However, the second portion126may have a silicon concentration that is higher than that of the first portion127. This is because, as will be described in more detail below, the silicon concentration of the second portion126is increased by an ion implantation process IIP. In detail, the second portion126may have a silicon concentration ranging from 30 at % to 40 at %. In more detail, the second portion126may have a silicon concentration ranging from about 33 at % to about 35 at %.

In some embodiments, an interface between the first portion127and the second portion126may be unclear. Here, when measured from a center of the spacer125, the first portion127may be positioned adjacent the gate electrode135, compared with the second portion126, and the second portion126may be positioned adjacent to the contact165, compared with the first portion127.

In general, if a material (e.g., a low-k dielectric layer) has a low dielectric constant, it may exhibit a relatively bad etch-resistant property, when a specific etchant is used. In the case where, to reduce parasitic capacitance of a semiconductor device, a low-k dielectric material is used for the spacers125, the spacers125may be easily removed, when the contacts165are formed. Accordingly, it may be difficult to use the spacers125to protect the gate electrodes135, and thus, an electric short circuit may be formed between the contacts165and the gate electrodes135. By contrast, according to example embodiments of the inventive concept, as a result of the silicon ion implantation process, the second portions126may have a silicon concentration higher than that of the first portions127. This may make it possible for the second portions126doped with silicon ions to have a good etch resistant property in a subsequent etching process. For example, the second portions126may have a high etch selectivity with respect to the first and second interlayer insulating layers150and155(e.g., of an oxide-based material). Since the second portions126are formed of a material with a low dielectric constant, it is possible to improve an RC-delay property of the device, and moreover, the use of the second portions126may make it possible to protect the gate electrodes135from etch damage.

Gate dielectric layers134may be provided between the gate electrodes135and the substrate100and between the gate electrodes135and the spacers125. The gate dielectric layers134may be formed of or include a high-k dielectric material. For example, the gate dielectric layers134may be formed of or include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and/or lead zinc niobate.

The gate capping layers145may be provided on the gate electrodes135, respectively. The gate capping layers145may extend along the gate electrodes135or parallel to the first direction D1. The gate capping layers145may be formed of or include a material having an etch selectivity with respect to first and second interlayer insulating layers150and155, which will be described below. For example, the gate capping layers145may be formed of or include at least one of SiON, SiCN, SiCON, and/or SiN. Furthermore, the gate capping layers145may include a material, whose dielectric constant is greater than that of the spacers125. In a usual etching process, as a dielectric constant of a material increases, an etch rate thereof may decrease. Thus, in a subsequent etching process for forming the contacts165, the gate capping layers145may make it possible to effectively protect the top portions of the gate electrodes135.

Source/drain regions114may be provided in the active pattern AP positioned between the pair of gate electrodes135and at both sides of the pair of gate electrodes135. The source/drain regions114may be epitaxial patterns formed by a selective epitaxial growth process. The source/drain regions114may have top surfaces, which are positioned at the same level as or at a higher level than the top surface of the active pattern AP. The source/drain region114is illustrated to have a flat top surface, but in certain embodiments, the source/drain region114may have a curved top surface with non-vanishing curvature. As an example, the source/drain regions114may upward convex top surfaces. Although not shown, bottom surfaces of the source/drain regions114may be positioned above the bottom surface of the device isolation layer104.

The source/drain regions114may include a semiconductor element different from those of the substrate100. For example, the source/drain regions114may be formed of or include a semiconductor material having a lattice constant different from (for example, greater or smaller than) the substrate100. This may make it possible to exert a compressive stress or a tensile stress to a channel region defined in the active pattern AP and below the gate electrode135. In the case where the substrate100is a silicon wafer, the source/drain regions114may be formed of or include a silicon-germanium (e.g., e-SiGe) and/or germanium layer. In this case, the source/drain regions114may exert a compressive stress on the channel regions (preferably, of PMOS field effect transistors). In the case where the substrate100is a silicon wafer, the source/drain regions114may be formed of or include a silicon carbide (SiC) layer. In this case, the source/drain regions114may exert a tensile stress on the channel regions (preferably, of NMOS field effect transistors). The compressive or tensile stress to be exerted on the channel region by the source/drains SD may make it possible for carriers in the channel regions to have an increased mobility, when the field effect transistors are operated. The source/drain regions114may have a second conductivity type that is different from that of the active pattern AP.

Although not shown, semiconductor capping patterns may be provided on the source/drain regions114. The semiconductor capping patterns may include the same semiconductor element as the substrate100or the source/drain regions114. As an example, the semiconductor capping patterns may be formed of or include silicon or silicon germanium. As another example, each of the semiconductor capping patterns may be a double-layered structure including a silicon layer and a silicon-germanium layer. In example embodiments, the semiconductor capping patterns may be doped with elements different from dopants contained in the source/drain regions114. For example, in the case where the source/drain regions114include an e-SiGe layer, the semiconductor capping patterns may be formed of or include a lightly Ge-doped layer and/or a highly B-doped layer. This makes it possible to reduce contact resistance between the semiconductor capping patterns and the source/drain regions114.

In some embodiments, metal silicide layers116may be respectively interposed between the source/drain regions114and the contacts165. In other words, the contacts165may be electrically connected to the source/drain regions114via the metal silicide layers116. The metal silicide layers116may be formed of or include at least one of metal-silicide materials (e.g., titanium silicide, tantalum silicide, and/or tungsten silicide). The metal-silicide materials may be formed through a chemical reaction between semiconductor elements contained in the source/drain regions114and metallic elements.

A first interlayer insulating layer150may be provided on the substrate100. The first interlayer insulating layer150may have a top surface that is substantially coplanar with those of the spacers125and the gate capping layers145. The first interlayer insulating layer150may be formed of or include a silicon oxide layer. A second interlayer insulating layer155may be formed on the first interlayer insulating layer150to cover the gate capping layers145. The second interlayer insulating layer155may be formed of or include a silicon oxide layer and/or a low-k oxide layer. The low-k oxide layer may include, for example, a carbon-doped silicon oxide layer (e.g., SiCOH). Although not shown, a pad oxide (e.g., of silicon oxide) (not shown) may be further provided between the substrate100and the first interlayer insulating layer150.

The contacts165may be provided on the substrate100to penetrate the second interlayer insulating layer155and the first interlayer insulating layer150and to be in contact with the metal silicide layers116. At least one of the contacts165may be in direct contact with at least one of the spacers125. The contacts165may be spaced apart from the gate electrodes135by the gate capping layers145and the spacers125and may be electrically connected to the source/drain regions114. The contacts165may be formed of or include a metallic material (e.g., tungsten). In some embodiments, the contacts165may include a stack of a barrier metal layer (e.g., of metal nitride) and a metal layer (e.g., of tungsten).

Referring back toFIG. 1, when viewed in a plan view, the contacts165may be aligned with the source/drain regions114. Each of the contacts165may include a portion that is not overlapped with the source/drain region114, in the plan view. Accordingly, at least one of the contacts165may be partially overlapped with the second portion126, in the plan view.

According to example embodiments of the inventive concept, a field effect transistor of a semiconductor device may include the gate capping layers145, which are disposed to protect top portions of the gate electrodes135, and the second portions126of the spacers125, which are disposed to protect sidewalls of the gate electrodes135. The gate capping layers145and the second portions126may have a high etch selectivity with respect to the first and second interlayer insulating layers150and155, and thus, it is possible to effectively protect the gate electrodes135from an etch damage. This makes it possible to enlarge a process margin in a contact-hole etching process to be described below. Furthermore, by virtue of the gate capping layers145and the second portions126, it is possible to form the contacts165in a self-aligned and effective manner, without a short between the contacts165and the gate electrodes135, and to improve operation speed and characteristics of the semiconductor device. As a result, it is possible to provide a semiconductor device with improved performance and a fabrication process with an increased process margin.

FIG. 2Bis a sectional view illustrating a portion, corresponding to the region M ofFIG. 2A, of a semiconductor device, according to other example embodiments of the inventive concept. In the following description, for concise description, an element previously described with reference toFIGS. 1 and 2Amay be identified by a similar or identical reference number without repeating an overlapping description thereof.

Referring toFIG. 2B, each of the spacers125may include the first portion127and the second portion126. Here, the second portion126may extend onto the first portion127and may serve as side and top regions of the spacer125. For example, the top surface126T of the second portion126may be higher than the top surface127T of the first portion127. Since the second portion126serves as the top region of the spacer125adjacent the gate capping layer145, it is possible to effectively protect the gate electrode135, when the contact165is formed.

FIGS. 3A through 3Hare sectional views illustrating methods of fabricating a semiconductor device, according to example embodiments of the inventive concept.FIGS. 3A through 3Hare sectional views corresponding to the line I-I′ ofFIG. 1.

Referring toFIGS. 1 and 3A, sacrificial gate patterns106and gate mask patterns108, which are sequentially stacked, may be formed on the substrate100. The substrate100may be a semiconductor substrate (e.g., of silicon, germanium, and/or silicon-germanium) and/or a compound semiconductor substrate. The device isolation layer104may be formed on or in the substrate100to define the active pattern AP. The device isolation layer104may be formed using a shallow trench isolation (STI) method. For example, the formation of the device isolation layer104may include patterning the substrate100to form a trench (not shown) and filling the trench with an insulating layer (e.g., of silicon oxide).

The active pattern AP may correspond to a portion of the substrate100surrounded by the device isolation layer104. The active pattern AP may be a line- or bar-shaped structure extending in a second direction D2parallel to a top surface of the substrate100. Although one active pattern AP is illustrated, the substrate100may have a plurality of the active patterns AP. In this case, the active patterns AP may be arranged along the first direction D1crossing the second direction D2. The active pattern AP may be doped to have a first conductivity type.

Each of the sacrificial gate patterns106and the gate mask patterns108may be a line- or bar-shaped structure crossing the active pattern AP and extending parallel to the first direction D1. For example, the sacrificial gate patterns106and the gate mask patterns108may be formed by sequentially forming a sacrificial gate layer (not shown) and a gate mask layer (not shown) on the substrate100and patterning the sacrificial gate layer and the gate mask layer.

A plurality of the sacrificial gate patterns106may be formed to cross at least one of the active patterns AP. As an example, a pair of the sacrificial gate patterns106may be formed spaced apart from each other in the second direction D2and may extend parallel to the first direction D1on the active pattern AP. The sacrificial gate layer may be formed of or include a poly-silicon layer. The gate mask layer may be formed of or include a silicon nitride layer or a silicon oxynitride layer.

Although not shown, before the formation of the sacrificial gate layer, a pad oxide (not shown) may be formed on the substrate100. The pad oxide may be formed by a dry oxidation process, a wet oxidation process, and/or a radical oxidation process. For the sake of simplicity, the description that follows will refer to an example of the present embodiment in which a pair of the sacrificial gate patterns106are spaced apart from each other in the second direction D2and are formed to cross one of the active patterns AP.

Referring toFIGS. 1 and 3B, a spacer layer120may be formed to cover the sacrificial gate patterns106. For example, the spacer layer120may be conformally formed on the resulting structure provided with the sacrificial gate patterns106. The spacer layer120may be formed of or include a nitride-based low-k insulating layer. As an example, the spacer layer120may be formed of or include at least one of SiON, SiCON, and/or SiN. In the case where the spacer layer120includes silicon nitride (SiN), the spacer layer120may be formed to have a porous structure and thereby to have a reduced dielectric constant.

The spacer layer120may be doped with silicon ions. For example, an ion implantation process IIP may be performed to inject silicon ions into the spacer layer120, and thus, a doped region121may be formed in an upper region of the spacer layer120. The ion implantation process IIP may be performed at a dose ranging from 1.0E14/cm2to 1.0E16/cm2. Accordingly, the doped region121may have a silicon concentration ranging from 30 at % to 40 at %. In more detail, the doped region121may have a silicon concentration ranging from about 33 at % to about 35 at %. As shown inFIG. 3B, the doped region121may have a uniform thickness.

As an example, a portion of the doped region121, which is positioned adjacent the sidewalls of the sacrificial gate patterns106, may have a thickness ranging from 2 nm to 20 nm. As another example, the doped region121may have a non-uniform thickness. For example, a thickness of a portion of the doped region121, which is positioned adjacent the gate mask patterns108, may be greater than that of the portion of the doped region121, which is positioned adjacent the sidewalls of the sacrificial gate patterns106. A thickness profile of the doped region121may be changed by controlling the ion implantation process IIP, but example embodiments of the inventive concept are not limited thereto.

Referring toFIGS. 1 and 3C, the spacer layer120may be anisotropically etched to form the spacers125covering the sidewalls of the sacrificial gate patterns106. For example, the spacers125may be formed by performing an anisotropic etching process on the spacer layer120. Each of the spacers125may include the first portion127, which is disposed adjacent the sacrificial gate pattern106, and the second portion126, which are spaced apart from the sacrificial gate pattern106with the first portion127interposed therebetween. Here, the second portion126may be a portion of the doped region121, which remain after the anisotropic etching process. A bottom surface of the second portion126may be positioned at a higher level than a bottom surface of the first portion127.

Next, recess regions112may be formed in the active pattern AP. The recess regions112may be formed by selectively etching the active pattern AP using the gate mask patterns108and the spacers125as an etch mask. As a result, the recess regions112may be formed between a pair of the sacrificial gate patterns106and in the active pattern AP positioned at both sides of the sacrificial gate patterns106. Although not shown, the bottom surfaces of the recess regions112may be positioned at a higher level than the bottom surface of the device isolation layer104. As an example, the etching process for forming the recess regions112may include an anisotropic etching process. As another example, the etching process for forming the recess regions112may include an isotropic etching process (e.g., a wet etching process). In this case, unlike that illustrated inFIG. 3C, the recess regions112may extend below the sacrificial gate patterns106.

Referring toFIGS. 1 and 3D, the source/drain regions114may be formed in the recess regions112, respectively. The source/drain regions114may serve as source/drain electrodes of a field effect transistor according to example embodiments of the inventive concept.

For example, the source/drain regions114may be formed by a selective epitaxial growth process using the substrate100as a seed layer. As an example, the selective epitaxial growth process may include a chemical vapor deposition (CVD) process and/or a molecular beam epitaxy (MBE) process. Each of the source/drain regions114may be formed to wholly fill a corresponding one of the recess regions112. Although the source/drain regions114are illustrated to have the top surfaces coplanar with that of the active pattern AP, the top surfaces of the source/drain regions114may be positioned at a higher level than that of the active pattern AP. In addition, although not illustrated, the source/drain regions114may have a curved top surface with non-vanishing curvature. As an example, the source/drain regions114may upward convex top surfaces.

The source/drain regions114may include a semiconductor element different from those of the substrate100. For example, the source/drain regions114may be formed of or include a semiconductor material having a lattice constant different from (for example, greater or smaller than) the substrate100. This may make it possible to exert a compressive stress or a tensile stress to a channel region defined in the active pattern AP and below the sacrificial gate patterns106. In the case where the substrate100is a silicon wafer, the source/drain regions114may be formed of or include a silicon-germanium (e.g., e-SiGe) and/or germanium layer. In this case, the source/drain regions114may exert a compressive stress on the channel regions (preferably, of PMOS field effect transistors). In the case where the substrate100is a silicon wafer, the source/drain regions114may be formed of or include a silicon carbide (SiC) layer. In this case, the source/drain regions114may exert a tensile stress on the channel regions (preferably, of NMOS field effect transistors). The compressive or tensile stress to be exerted on the channel region by the source/drain regions114may make it possible for carriers in the channel regions to have an increased mobility, when the field effect transistors are operated.

The source/drain regions114may be doped to have the second conductivity type different from the conductivity type of the active pattern AP. In some embodiments, the source/drain regions114may be formed using an in-situ doping process. In some embodiments, an ion implantation process may be performed to realize the second conductivity type of the source/drain regions114, after the formation of the source/drain regions114.

The first interlayer insulating layer150may be formed on the resulting structure provided with the source/drain regions114. The first interlayer insulating layer150may be formed of an oxide-based insulating layer and may be formed to cover the sacrificial gate patterns106and the gate mask patterns108. As an example, the first interlayer insulating layer150may include a silicon oxide layer and may be formed by a flowable chemical vapor deposition (FCVD) process.

Referring toFIGS. 1 and 3E, the first interlayer insulating layer150may be planarized to expose the top surfaces of the sacrificial gate patterns106. The planarization of the first interlayer insulating layer150may be performed using an etch-back process or a chemical-mechanical polishing (CMP) process. The planarization of the first interlayer insulating layer150may be performed to remove the gate mask patterns108and thereby to expose the top surfaces of the sacrificial gate patterns106. The planarization of the first interlayer insulating layer150may be performed to remove top portions of the spacers125. As a result, the top surface of the first interlayer insulating layer150may be coplanar with top surfaces of the sacrificial gate patterns106and the spacers125.

Referring toFIGS. 1 and 3F, the sacrificial gate patterns106may be removed to form gate trenches130. The gate trenches130may be formed by an etching process of selectively removing the sacrificial gate patterns106. The gate trenches130may be formed to expose the top surface of the substrate100and extend in the first direction D1.

The gate dielectric layer134and the gate electrode135may be formed in each of the gate trenches130. The gate dielectric layer134may be formed on the resulting structure provided with the gate trenches130. The gate dielectric layer134may be conformally formed to have a thickness that is too small to completely fill the gate trenches130. For example, the gate dielectric layer134may be formed to cover bottom surfaces of the gate trenches130and cover sidewalls of the spacers125, which are exposed by the gate trenches130, and the top surface of the first interlayer insulating layer150. The gate dielectric layer134may be formed by an atomic layer deposition (ALD) process and/or a chemical oxidation process. As an example, the gate dielectric layer134may be formed of or include a high-k dielectric material. For example, the gate dielectric layer134may be formed of or include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and/or lead zinc niobate.

Thereafter, a gate electrode layer may be formed on the gate dielectric layer134to fill the gate trenches130, and the gate electrode layer and the gate dielectric layer134may be planarized to expose the top surface of the first interlayer insulating layer150. As a result, the gate dielectric layer134and the gate electrode135may be locally formed in each of the gate trenches130. The gate dielectric layer134and the gate electrode135may extend in the first direction D1. In some embodiments, the gate electrode layer may be formed of or include at least one of conductive metal nitrides (e.g., titanium nitride and/or tantalum nitride) and/or metals (e.g., titanium, tantalum, tungsten, copper, and/or aluminum). The gate electrode layer may be formed by a deposition process (e.g., a CVD or sputtering process). The planarization of the gate electrode layer and the gate dielectric layer134may include a CMP process. As a result of the planarization process, the first interlayer insulating layer150may have the top surface coplanar with the top surfaces of the gate electrodes135and the spacers125.

Referring toFIGS. 1 and 3G, upper portions of the gate electrodes135may be recessed, and the gate capping layers145may be formed on the gate electrodes135, respectively.

In detail, a selective etching process may be performed to remove the upper portions of the gate electrodes135. As a result of the etching process, the top surfaces of the gate electrodes135may be lower than the top surface of the first interlayer insulating layer150. In some embodiments, portions of the gate dielectric layer134positioned above the gate electrodes135may be removed, after the recessing of the upper portions of the gate electrodes135. As a result, the gate dielectric layer134may be provided between the gate electrode135and the substrate100and between the gate electrode135and the spacers125.

Thereafter, the gate capping layers145may be formed to cover the recessed top surfaces of the gate electrodes135, respectively. The gate capping layers145may be formed to fill the empty regions, which are formed by recessing the upper portions of the gate electrodes135. The gate capping layers145may be formed of a material having an etch selectivity with respect to the first and second interlayer insulating layers150and155. As an example, the gate capping layers145may be formed of or include at least one of SiON, SiCN, SiCON, and/or SiN. The gate capping layers145may be formed by an atomic layer deposition (ALD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, and/or a high-density plasma chemical vapor deposition (HDPCVD) process.

Referring toFIGS. 1 and 3H, the second interlayer insulating layer155may be formed. The second interlayer insulating layer155may be formed of or include a silicon oxide layer or a low-k oxide layer. The low-k oxide layer may include, for example, a carbon-doped silicon oxide layer (e.g., SiCOH). The second interlayer insulating layer155may be formed by a CVD process.

Next, contact holes160may be formed to penetrate the second interlayer insulating layer155and the first interlayer insulating layer150and to expose the top surfaces of the source/drain regions114. At least one of the contact holes160may expose the sidewall of the spacer125(e.g., the second portion126). The contact holes160may be formed in a self-aligned manner by the spacers125. For example, the formation of the contact holes160may include forming a photoresist pattern (not shown) on the second interlayer insulating layer155to define positions and dispositions of the contact holes160and performing an anisotropic etching process using the photoresist pattern as an etch mask. The photoresist pattern (not shown) may be formed to have openings (not shown), whose planar shapes are substantially equal or similar to those of the contact holes160.

The gate capping layers145and the second portions126of the spacers125may have a high etch selectivity with respect to the first and second interlayer insulating layers150and155. In particular, since, as described above, the second portions126are additionally doped with silicon ions through the ion implantation process IIP, the second portions126may have a relatively higher etch resistant property, compared with that of the first portions127. Accordingly, it is possible to prevent the spacers125exposed by the contact holes160from being etched in the etching process for forming the contact holes160. In other words, by providing the second portions126according to example embodiments of the inventive concept, it is possible to increase a process margin in the etching process for forming the contact holes160and to effectively protect the sidewalls of the gate electrodes135. In other words, it is possible to form the contacts165in a self-aligned and effective manner.

The metal silicide layers116may be formed on the source/drain regions114exposed by the contact holes160. The formation of the metal silicide layers116may include forming a metal layer on the source/drain regions114and performing a thermal treatment process on the metal layer to form a metal-silicide layer. The metal silicide layers116may include at least one of, for example, titanium silicide, tantalum silicide, and/or tungsten silicide.

Referring back toFIGS. 1 and 2A, the contacts165may be formed to be in contact with the metal silicide layers116in the contact holes160. At least one of the contacts165may be in partial contact with the second portion126. In other words, the contacts165may be self-aligned contacts that are formed in a self-aligned manner by the spacers125. For example, the formation of the contacts165may include forming a conductive layer on the resulting structure provided with the contact holes160to fill the contact holes160and performing a planarization process to expose the top surface of the second interlayer insulating layer155. Here, the conductive layer may be formed of or include a metallic material (e.g., tungsten). In some embodiments, the formation of the conductive layer may include sequentially depositing a barrier metal layer (e.g., metal nitride) and a metal layer (e.g., tungsten).

FIG. 4is a sectional view illustrating methods of fabricating a semiconductor device, according to some other example embodiments of the inventive concept.FIG. 4is a sectional view corresponding to the line I-I′ ofFIG. 1. In the following description, for concise description, an element previously described with reference toFIG. 1andFIGS. 3A through 3Hmay be identified by a similar or identical reference number without repeating an overlapping description thereof.

Unlike that previously described with reference toFIGS. 1 and 3B, the spacer layer120may be formed to cover the sacrificial gate patterns106, but the ion implantation process IIP on the spacer layer120may be omitted.

Thereafter, as described with reference toFIGS. 1 and 3C, the spacer layer120may be anisotropically etched to form the spacers125, and the recess regions112may be formed in the active pattern AP. Next, as described with reference toFIGS. 1 and 3D, the source/drain regions114may be formed in the recess regions112, respectively.

However, as shown inFIGS. 1 and 4, before the formation of the first interlayer insulating layer150, the ion implantation process IIP may be performed on the spacers125. As a result, the second portions126doped with silicon ions may be formed in the spacers125. The first portions127may be interposed between the second portions126and the sacrificial gate patterns106. The second portions126may have a silicon concentration higher than that of the first portions127; for example, the silicon concentration of the second portions126may ranging from 30 at % to 40 at %. In particular, the second portions126may have a silicon concentration ranging from about 33 at % to about 35 at %. The second portion126may have a bottom surface coplanar with that of the first portion127. Except for these features, the ion implantation process IIP may be performed in the same manner as that previously described with reference toFIG. 3B.

Furthermore, aside from those described with reference toFIGS. 3B and 4, the ion implantation process IIP may be performed at any time between the formation of the spacer layer120and the formation of the first interlayer insulating layer150, although not shown.

FIG. 5is a plan view illustrating a semiconductor device, according to other example embodiments of the inventive concept.

Referring toFIG. 5, a semiconductor device according to example embodiments of the inventive concept may include a plurality of logic cells C1, C2, C3, and C4provided on a substrate. Each of the logic cells C1, C2, C3, and C4may include a plurality of transistors. As an example, the semiconductor device may include a first logic cell C1, a second logic cell C2spaced apart from the first logic cell C1in a first direction D1, a third logic cell C3spaced apart from the first logic cell C1in a second direction D2crossing the first direction D1, and a fourth logic cell C4spaced apart from the second logic cell C2in the second direction D2. Each of the logic cells C1, C2, C3, and C4may include active regions spaced apart from each other by device isolation layers104. Each of the logic cells C1, C2, C3, and C4may include a PMOSFET region PR and an NMOSFET region NR which are spaced apart from each other by the device isolation layers104.

As an example, the PMOSFET and NMOSFET regions PR and NR may be spaced apart from each other in the first direction D1. The PMOSFET region PR of the first logic cell C1may be disposed adjacent the PMOSFET region PR of the second logic cell C2in the first direction D1. In the following description, a term “logic cell” may refer to a unit circuit configured to perform a single logical operation. Further, the number of the logic cells may be variously changed from that illustrated in the drawing.

FIG. 6is a plan view illustrating a portion of a semiconductor device, according to some other example embodiments of the inventive concept. For example,FIG. 6is a plan view illustrating the first logic cell C1ofFIG. 5. Hereinafter, various embodiments of the inventive concept will be described with reference to the first logic cell C1ofFIG. 5, but the others of the logic cells may have substantially the same or similar structure as that of the first logic cell C1.FIG. 7is a perspective view illustrating the region N ofFIG. 6.FIG. 8is a sectional view taken along lines I-I′ and II-II′ ofFIG. 7. In the following description, for concise description, an element previously described with reference toFIGS. 1 and 2Amay be identified by a similar or identical reference number without repeating an overlapping description thereof.

Referring toFIGS. 6, 7, and 8, the device isolation layers104may be provided in the substrate100to define the PMOSFET and NMOSFET regions PR and NR. The device isolation layers104may be formed in a top portion of the substrate100. In example embodiments, the device isolation layers104may include an insulating material, such as silicon oxide.

The PMOSFET and NMOSFET regions PR and NR may be spaced apart from each other, in the first direction D1parallel to a top surface of the substrate100, by the device isolation layers104interposed therebetween. Although each of the PMOSFET and NMOSFET regions PR and NR is illustrated to be a single region, it may include a plurality of regions spaced apart from each other by the device isolation layers104.

A plurality of active patterns AP may be provided on the PMOSFET and NMOSFET regions PR and NR to extend in the second direction D2crossing the first direction D1. The active patterns AP may be arranged along the first direction D1. The device isolation layers104may be provided at both sides of each of the active patterns AP to define the active patterns AP. Although the number of the active patterns AP provided on each of the PMOSFET and NMOSFET regions PR and NR is shown to be two, example embodiments of the inventive concept may not be limited thereto.

Each of the active patterns AP may include active fins AF protruding between the device isolation layers104. For example, each of the active fins AF may have a structure protruding from the active pattern AP in a third direction D3perpendicular to the top surface of the substrate100. Each of the active fins AF may include the source/drain regions114and a channel region CHR interposed between the source/drain regions114.

In some embodiments, the gate electrodes135may be provided on the substrate100to cross the active patterns AP. The source/drain regions114may be provided at both sides of each of the gate electrodes135. In addition, the contacts165may be provided at both sides of each of the gate electrodes135and may be electrically connected to the source/drain regions114. Each of the contacts165may be connected to a corresponding one or some of the source/drain region114, but example embodiments of the inventive concept may not be limited thereto.

A gate contact CB and a conductive line CBL may be provided on one of the gate electrodes135. A first via V1may be disposed between the gate contact CB and the conductive line CBL. The conductive line CBL may be electrically connected to the one of the gate electrodes135through the first via V1and the gate contact CB to serve as a current path for applying signals to the one of the gate electrodes135.

The first logic cell C1may include a first wire PW1provided near an outer edge of the PMOSFET region PR and a second wire PW2provided near an outer edge of the NMOSFET region NR. As an example, the first wire PW1on the PMOSFET region PR may serve as a current path for transmitting a drain voltage Vdd (e.g., a power voltage). The second wire PW2on the NMOSFET region NR may serve as a current path for transmitting a source voltage Vss (e.g., a ground voltage).

The first and second wires PW1and PW2may extend in the second direction D2and may be shared by a plurality of logic cells, which are disposed adjacent one another in the second direction D2. As an example, the first wire PW1may be shared by the first logic cell C1and the third logic cell C3. Furthermore, the first wire PW1may be shared by the PMOSFET regions PR of the first and second logic cells C1and C2.

In some embodiments, a second via V2may be provided on one of the contact165. Accordingly, the source/drain region114connected to the one of the contacts165may be electrically connected to the first wire PW1through the one of the contacts165and the second via V2. Similarly, the source/drain region114on the NMOSFET region NR may also be electrically connected to the second wire PW2through the one of the contacts165and a third via V3.

Hereinafter, the region N of the PMOSFET region PR shown inFIG. 6will be described as an example, for the sake of simplicity.

The gate electrode135may be provided on the substrate100to cross the active patterns AP. The gate electrode135may be overlapped with the channel regions CHR of the active fins AF, when viewed in a plan view. In other words, the gate electrode135may be a line-shaped structure crossing the active fins AF and extending in the first direction D1.

The source/drain regions114may be provided on the active fins AF and at both sides of the gate electrode135. The source/drain regions114may be epitaxial patterns, which are epitaxially grown from the active patterns AP. In some embodiments, when viewed in a vertical section, top surfaces of the channel regions CHR may be positioned at a higher level than bottom surfaces of the source/drain regions114. The top surfaces of the source/drain regions114may be positioned at the same level as, or a higher level than, the top surfaces of the channel regions CHR.

The metal silicide layers116may be respectively interposed between the source/drain regions114and the contacts165. In other words, the contacts165may be electrically connected to the source/drain regions114via the metal silicide layers116.

The spacers125may be provided on both sidewalls of the gate electrode135. The spacers125may extend along the gate electrode135or parallel to the first direction D1. Each of the spacers125may include the first portion127adjacent the gate electrode135and the second portion126adjacent the contact165. The first and second portions126and127may be configured to have substantially the same features as those described with reference toFIGS. 2A and 2B.

The gate dielectric layer134may be provided between the gate electrode135and the active fins AF and between the gate electrode135and the spacers125. The gate dielectric layer134may extend along the bottom surface of the gate electrode135. For example, the gate dielectric layer134may cover top and side surfaces of the channel regions CHR. The gate dielectric layer134may extend horizontally from the active fins AF to partially cover a top surface of the device isolation layer104. In some embodiments, the gate dielectric layer134may be provided to expose at least a portion of the top surface of the device isolation layer104. The exposed portion of the device isolation layer104, which is not covered with the gate dielectric layer134, may be covered by the first interlayer insulating layer150.

The gate capping layer145may be provided on the gate electrode135. The gate capping layer145may extend along the gate electrode135or parallel to the first direction D1. The gate capping layer145may be formed to have substantially the same features as that described with reference toFIGS. 1 and 2A.

A first interlayer insulating layer150may be provided on the substrate100. The first interlayer insulating layer150may cover the spacers125and the source/drain regions114. The first interlayer insulating layer150may have a top surface that is substantially coplanar with that of the gate capping layer145. The second interlayer insulating layer155may be formed on the first interlayer insulating layer150to cover the gate capping layer145.

The contacts165may be provided on the substrate100to penetrate the second interlayer insulating layer155and the first interlayer insulating layer150and to be in contact with the metal silicide layers116. In some embodiments, an etch stop layer129may be interposed between the contacts165and the spacers125. Accordingly, at least one of the contacts165may be in direct contact with the etch stop layer129. In addition, at least one of the contacts165may be in direct contact with the top surface of the second portion126. In certain embodiments, the etch stop layer129may be omitted, and in this case, at least one of the contacts165may be in direct contact with the second portion126of the spacer125. Due to the gate capping layer145and the spacers125, the contacts165may be spaced apart from the gate electrode135. Interconnection lines190may be provided on the second interlayer insulating layer155to be connected to the contacts165.

FIGS. 9A through 9Dare sectional views illustrating methods of fabricating a semiconductor device, according to some other example embodiments of the inventive concept.FIGS. 9A through 9Dare sectional views taken along lines I-I′ and II-II′ ofFIG. 7. In the following description, for concise description, an element or operation previously described with reference toFIGS. 3A through 311may be identified by a similar or identical reference number without repeating an overlapping description thereof.

Referring toFIG. 9A, the substrate100may be patterned to form device isolation trenches105defining the active patterns AP. The substrate100may be a semiconductor substrate (e.g., of silicon, germanium, or silicon-germanium) or a compound semiconductor substrate.

The formation of the device isolation trenches105may include forming mask patterns on the substrate100and anisotropically etching the substrate100using the mask patterns an etch mask. Each of the mask patterns may include a first mask pattern110and a second mask pattern115, which are sequentially stacked on the substrate100and are formed to have an etch selectivity with respect to each other. Each of the device isolation trenches105may be formed to have an aspect ratio of at least 5. In some embodiments, each of the device isolation trenches105may be formed to have a downward tapered shape. Accordingly, each of the active patterns AP may be formed to have an upward tapered shape.

Referring toFIG. 9B, the device isolation layer104may be formed to fill the device isolation trenches105. The formation of the device isolation layer104may include forming an insulating layer to fill the device isolation trenches105and planarizing the insulating layer to expose the top surface of the first mask pattern110. As a result of the planarization process, the device isolation layer104may be locally formed in the device isolation trenches105.

Referring toFIG. 9C, top portions (hereinafter, active fins AF) of the active patterns AP may be exposed. The exposing of the active fins AF may include recessing top portions of the device isolation layer104using, for example, a wet etching process. The recessing of the device isolation layer104may be performed using an etch recipe having an etch selectivity with respect to the active patterns AP. The recessing of the device isolation layer104may be performed to remove the first mask pattern110and thereby to expose top surfaces of the active fins AF.

A sacrificial gate pattern106and a gate mask pattern (not shown), which are sequentially stacked, may be formed on the active fins AF. The sacrificial gate pattern106and the gate mask pattern (not shown) may be formed by sequentially forming a sacrificial gate layer (not shown) and a gate mask layer (not shown) on the active fins AF and the device isolation layer104and patterning the sacrificial gate layer and the gate mask layer (e.g., seeFIG. 3A). The sacrificial gate pattern106may be formed to cross the active fins AF.

The spacers125may be formed on both sidewalls of the sacrificial gate pattern106. The formation of the spacers125may include conformally forming a spacer layer on the resulting structure provided with the sacrificial gate pattern106and performing an anisotropic etching process on the spacer layer. Here, an ion implantation process may be performed to inject silicon ions into the spacer layer or the spacers125(e.g., seeFIGS. 3B and 4). As a result of the ion implantation process, each of the spacers125may include the first portion127, which is disposed adjacent the sacrificial gate pattern106, and the second portion126, which are spaced apart from the sacrificial gate pattern106with the first portion127interposed therebetween. The second portion126may have a silicon concentration higher than that of the first portion127.

The source/drain regions114may be formed at both sides of the sacrificial gate pattern106(e.g., seeFIGS. 3C and 3D). The source/drain regions114may serve as source/drain electrodes of a field effect transistor according to example embodiments of the inventive concept. The active fins AF may include the channel regions CHR positioned below the sacrificial gate pattern106. Each of the channel regions CHR may be interposed between the source/drain regions114.

The etch stop layer129may be formed on the resulting structure provided with the source/drain regions114. The etch stop layer129may cover the sacrificial gate patterns106. The etch stop layer129may protect the source/drain regions114against etch damage caused by a subsequent etching process. For example, the etch stop layer129may be formed of or include silicon nitride (SiN). In some embodiments, the silicon ion implantation process may be performed on the spacers125, after the formation of the etch stop layer129.

Thereafter, the first interlayer insulating layer150may be formed. The formation of the first interlayer insulating layer150may include forming an insulating layer to cover the sacrificial gate patterns106and planarizing the insulating layer to expose the top surfaces of the sacrificial gate patterns106(e.g., seeFIG. 3E).

Referring toFIG. 9D, the sacrificial gate pattern106may be removed to form a gate trench (not shown) (e.g., seeFIG. 3F). The gate trench may be formed to expose the active fins AF.

The gate dielectric layer134and the gate electrode135may be formed in the gate trench (not shown). The gate dielectric layer134may be formed to conformally cover the gate trench. Thereafter, a gate electrode layer (not shown) may be formed on the gate dielectric layer134to fill the gate trench, and the gate electrode layer and the gate dielectric layer134may be planarized to expose the top surface of the first interlayer insulating layer150.

Referring back toFIGS. 7 and 8, the top portion of the gate electrode135may be recessed, and the gate capping layer145may be formed on the gate electrode135(e.g., seeFIG. 3G).

The second interlayer insulating layer155may be formed on the first interlayer insulating layer150and the gate capping layer145. Next, contact holes (not shown) may be formed to penetrate the second interlayer insulating layer155and the first interlayer insulating layer150and to expose the top surfaces of the source/drain regions114(e.g., seeFIG. 3H). The formation of the contact holes may be performed to partially remove the etch stop layer129on the source/drain regions114. The remaining portion of the etch stop layer129may remain on the spacers125and the device isolation layer104. Accordingly, at least one of the contact holes may be formed to expose the etch stop layer129on the sidewall of the spacer125and/or the top surface of the second portion126.

Thereafter, the metal silicide layers116may be formed on the source/drain regions114exposed by the contact holes. The formation of the metal silicide layers116may include forming a metal layer on the source/drain regions114and performing a thermal treatment process on the metal layer to form a metal-silicide layer.

The contacts165may be formed in the contact holes to be in contact with the metal silicide layers116. The contacts165may be formed in a self-aligned manner by the spacers125. The interconnection lines190may be formed on the second interlayer insulating layer155and may be electrically connected to the contacts165.

FIG. 10is a block diagram illustrating an example of an electronic system including a semiconductor device according to example embodiments of the inventive concept.

Referring toFIG. 10, an electronic system1100according to example embodiments of the inventive concept may include a controller1110, an input-output (I/O) unit1120, a memory device1130, an interface unit1140, and a data bus1150. At least two of the controller1110, the I/O unit1120, the memory device1130and the interface unit1140may communicate with each other through the data bus1150. The data bus1150may correspond to a path through which electrical signals are transmitted.

The controller1110may include at least one of a microprocessor, a digital signal processor, a microcontroller, and/or another logic device, which is configured to have a similar function to them. The I/O unit1120may include a keypad, a keyboard, and/or a display unit. The memory device1130may store data and/or commands. The memory device1130may include a nonvolatile memory device (e.g., a FLASH memory device, a phase-change memory device, a magnetic memory device, and so forth). Furthermore, the memory device1130may further include a volatile memory device. For example, the memory device1130may include a static random access memory (SRAM) device with the semiconductor device according to example embodiments of the inventive concept. It may be possible to omit the memory device1130, depending on the purpose of the electronic system1100or a type of an electronic product, for which the electronic system1100is used. The interface unit1140may transmit electrical data to a communication network or may receive electrical data from a communication network. The interface unit1140may operate in a wireless or wired manner. For example, the interface unit1140may include an antenna for the wireless communication or a transceiver for the wired and/or wireless communication. A semiconductor device according to example embodiments of the inventive concept may be provided as a part of the controller1110or the I/O unit1120. Although not shown in the drawings, the electronic system1100may further include a fast DRAM device and/or a fast SRAM device that acts as a cache memory for improving an operation of the controller1110.

FIG. 11is a block diagram illustrating an example of an electronic device including a semiconductor device according to example embodiments of the inventive concept.

Referring toFIG. 11, an electronic device1200may include a semiconductor chip1210. The semiconductor chip1210may include a processor1211, an embedded memory1213, and a cache memory1215.

The processor1211may include one or more processor cores C1-Cn. The one or more processor cores C1-Cn may be configured to process data and signals. The processor cores C1-Cn may be configured to include the semiconductor device according to example embodiments of the inventive concept (for example, the plurality of logic cells described with reference toFIG. 5).

The electronic device1200may be configured to perform its own functions using the processed data and signals. As an example, the processor1211may be an application processor.

The embedded memory1213may exchange a first data DAT1with the processor1211. The first data DAT1may be data processed, or to be processed, by the one or more processor cores C1-Cn. The embedded memory1213may manage the first data DAT1. For example, the embedded memory1213may be used for a buffering operation on first data DAT1. In other words, the embedded memory1213may be operated as a buffer memory or a working memory for the processor1211.

In example embodiments, the electronic device1200may be used to realize a wearable electronic device. In general, the wearable electronic device may be configured to perform an operation of calculating a small amount of data, rather than calculating a large amount of data. In this sense, in the case where the electronic device1200is used for a wearable electronic device, the embedded memory1213may be configured to have a relatively small buffer capacity.

The embedded memory1213may be a static random access memory (SRAM) device. The SRAM device may have a faster operating speed than that of a dynamic random access memory (DRAM) device. Accordingly, in the case where the SRAM is embedded in the semiconductor chip1210, it is possible for the electronic device1200to have a small size and a fast operating speed. Furthermore, in the case where the SRAM is embedded in the semiconductor chip1210, it is possible to reduce an active power of the electronic device1200. As an example, the SRAM may include at least one of the semiconductor devices according to example embodiments of the inventive concept.

The cache memory1215may be mounted on the semiconductor chip1210, along with the one or more processor cores C1-Cn. The cache memory1215may be configured to store cache data DATc that will be used or directly accessed by the one or more processor cores C1-Cn. The cache memory1215may be configured to have a relatively small capacity and a very fast operating speed. In example embodiments, the cache memory1215may include an SRAM device including the semiconductor device according to example embodiments of the inventive concept. In the case where the cache memory1215is used, it is possible to reduce an access frequency or an access time to the embedded memory1213performed by the processor1211. In other words, the use of the cache memory1215may allow the electronic device1200to have a fast operating speed.

To provide better understanding of example embodiments of the inventive concept, the cache memory1215is illustrated inFIG. 11to be a component separated from the processor1211. However, the cache memory1215may be configured to be included in the processor1211. In addition, example embodiments of the inventive concept are not limited to the example illustrated byFIG. 11.

The processor1211, the embedded memory1213, and the cache memory1215may be configured to exchange and/or transmit data, based on at least one of various interface protocols. For example, the processor1211, the embedded memory1213, and the cache memory1215may be configured to exchange or transmit data, based on at least one of Universal Serial Bus (USB), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI) Express, Advanced Technology Attachment (ATA), Parallel ATA (PATA), Serial ATA (SATA), Serial Attached SCSI (SAS), Integrated Drive Electronics (IDE), and/or Universal Flash Storage (UFS).

FIG. 12is an equivalent circuit diagram illustrating an SRAM cell according to example embodiments of the inventive concept. The SRAM cell may be realized by at least one of the semiconductor devices according to example embodiments of the inventive concept. The SRAM cell may be used for the embedded memory1213and/or the cache memory1215ofFIG. 11.

Referring toFIG. 12, the SRAM cell may include a first pull-up transistor TU1, a first pull-down transistor TD1, a second pull-up transistor TU2, a second pull-down transistor TD2, a first access transistor TA1, and a second access transistor TA2. The first and second pull-up transistors TU1and TU2may be PMOS transistors, whereas the first and second pull-down transistors TD1and TD2and the first and second access transistors TA1and TA2may be NMOS transistors.

A first source/drain of the first pull-up transistor TU1and a first source/drain of the first pull-down transistor TD1may be connected to a first node N1. A second source/drain of the first pull-up transistor TU1may be connected to a power line Vcc, and a second source/drain of the first pull-down transistor TD1may be connected to a ground line Vss. A gate of the first pull-up transistor TU1and a gate of the first pull-down transistor TD1may be electrically connected to each other. Accordingly, the first pull-up transistor TU1and the first pull-down transistor TD1may constitute a first inverter. The mutually-connected gates of the first pull-up transistor TU1and the first pull-down transistor TD1may serve as an input terminal of the first inverter, and the first node N1may serve as an output terminal of the first inverter.

A first source/drain of the second pull-up transistor TU2and a first source/drain of the second pull-down transistor TD2may be connected to a second node N2. A second source/drain of the second pull-up transistor TU2may be connected to the power line Vcc, and a second source/drain of the second pull-down transistor TD2may be connected to the ground line Vss. A gate of the second pull-up transistor TU2and a gate of the second pull-down transistor TD2may be electrically connected to each other. Accordingly, the second pull-up transistor TU2and the second pull-down transistor TD2may constitute a second inverter. The mutually-connected gates of the second pull-up transistor TU2and the second pull-down transistor TD2may serve as an input terminal of the second inverter, the second node N2may serve as an output terminal of the second inverter.

The first and second inverters may be coupled with each other to form a latch structure. In other words, the gates of the first pull-up transistor TU1and the first pull-down transistor TD1may be electrically connected to the second node N2, and the gates of the second pull-up and second pull-down transistors TU2and TD2may be electrically connected to the first node N1. The first source/drain of the first access transistor TA1may be connected to the first node N1, and the second source/drain of the first access transistor TA1may be connected to a first bit line BL1. The first source/drain of the second access transistor TA2may be connected to the second node N2, and the second source/drain of the second access transistor TA2may be connected to a second bit line BL2. The gates of the first and second access transistors TA1and TA2may be electrically coupled to a word line WL. The SRAM cell according to example embodiments of the inventive concept may have the afore-described structure, but example embodiments of the inventive concept are not limited thereto.

FIGS. 13 through 15are diagrams illustrating some examples of a multimedia device including a semiconductor device according to example embodiments of the inventive concept. The electronic system1100ofFIG. 10and/or the electronic device1200ofFIG. 11may be applied to a mobile or smart phone2000shown inFIG. 13, to a tablet and/or smart tablet PC3000shown inFIG. 14, and/or to a laptop computer4000shown inFIG. 15.

According to example embodiments of the inventive concept, methods of fabricating a semiconductor device may include an ion implantation process of injecting silicon ions into spacers disposed on both sidewalls of a pattern, and thus, the spacers can have an increased etch resistant property to a specific etchant. Accordingly, the spacers may be formed of a low-k material, and this makes it possible to improve an RC delay property of the semiconductor device. Furthermore, it is possible to form contacts on both sides of the pattern (e.g., a gate electrode), in a self-aligned manner.