Data processing system for securing atomicity of transactions without generating separate commit command, and operating method thereof

A data processing system includes a host suitable for generating a plurality of write data grouped into transactions and a plurality of write commands including transaction information of each of the write data; and a memory system suitable for storing the write data in a normal region of a memory device in response to the write commands received from the host, and storing the transaction information included in each of the write commands in a spare region, which corresponds to the normal region, of the memory device.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2017-0139422 filed on Oct. 25, 2017, the disclosure of which is incorporated herein by reference in its entirety.

BACKGROUND

The present invention relates generally to a data processing system. Particularly, various embodiments of the invention relate to a data processing system capable of storing write data grouped as a transaction in a memory system, and an operating method thereof.

2. Description of the Related Art

The paradigm for computing environments is shifting toward ubiquitous computing which allows users to use computer systems anytime and anywhere. For this reason, the demand for portable electronic devices, such as mobile phones, digital cameras and laptop computers is soaring. Those electronic devices generally include a memory system using a memory device as a data storage device. The data storage device may be a main memory or an auxiliary memory of a portable electronic device.

Since a data storage device using a memory device does not have a mechanical driving device, it may have excellent stability and durability. Also, a data storage device has a quick data access rate with low power consumption. Non-limiting examples of a data storage device having such advantages include Universal Serial Bus (USB) memory devices, memory cards of diverse interfaces, Solid-State Drives (SSD) and the like.

SUMMARY

Various embodiments of the present invention are directed to a data processing system capable of storing write data grouped as a transaction, and an operating method thereof.

In accordance with an embodiment of the present invention, a data processing system includes: a host suitable for generating a plurality of write data grouped into transactions and a plurality of write commands including transaction information of each of the write data; and a memory system suitable for storing the write data in a normal region of a memory device in response to the write commands received from the host, and storing the transaction information included in each of the write commands in a spare region, which corresponds to the normal region, of the memory device.

The transaction information may include transaction ID information, commit information, and abort information.

The host may generate transaction information of each of first write data grouped into a first transaction including first ID information and commit information, and as a result of checking the transaction information of each of the write commands received from the host, the memory system identifies the write commands including the first ID information as first write commands, and identifies the write data corresponding to the first write commands as the first write data, and when the first write data are stored in a first normal region in response to the first write commands, the memory system loads and stores transaction information included in the first write commands in a first spare region corresponding to the first normal region.

The host may generate transaction information of each of second write data grouped into a second transaction including second ID information and commit information, and as a result of checking the transaction information of each of the write commands received from the host, the memory system identifies the write commands including the second ID information as second write commands, and identifies the write data corresponding to the second write commands as the second write data, and when the second write data are stored in a second normal region in response to the second write commands, the memory system loads and stores transaction information included in the second write commands in a second spare region corresponding to the second normal region.

The memory device may include a plurality of pages, the first normal region includes a first data section of a first page among the pages, the second normal region includes a second data section of the first page, the first spare region includes a first spare section of the first page, and the second spare region includes a second spare section of the first page.

The memory device may include a plurality of pages, the first normal region includes a data section of a first page among the pages, the second normal region includes a data section of a second page among the pages, the first spare region includes a spare section of the first page, and the second spare region includes a spare section of the second page.

The memory device may include a plurality of pages, the first normal region includes a data section of a first page group including at least two pages among the pages, the second normal region includes a data section of a second page group including at least two pages among the pages, the first spare region includes a spare section of the first page group, and the second spare region includes a spare section of the second page group.

The host may generate transaction information of last data among the write data including activated commit information and deactivated abort information for validating the write data, the host may generate the transaction information of the last data including deactivated commit information and activated abort information for invalidating the write data, and the host may generate transaction information of each of remaining intermediate data except for the last data among the write data including deactivated commit information and deactivated abort information.

As a result of reading and checking the transaction information of reading and checking the transaction information of the write data stored in the spare region when rebuilding the write data during a booting period where a power source is supplied again after sudden power-off (SPO) occurs while storing the write data in the memory device, when transaction information including activated commit information is retrieved, the memory system determines the write data stored in the normal region as being in a normal state and rebuilds the write data, and when transaction information including activated commit information is not retrieved or transaction information including activated abort information is retrieved, the memory system determines the write data stored in the normal region as being in an abnormal state and does not rebuild the write data.

The transaction information of each of the write data may further include start information, and the host may generate transaction information of start data among the intermediate data including deactivated commit information, deactivated abort information and activated start information.

As a result of reading and checking the transaction information of the write data stored in the spare region when rebuilding the write data during a booting period where a power source is supplied again after sudden power-off (SPO) occurs while storing the write data in the memory device, when transaction information including activated commit information and transaction information including activated start information are retrieved, the memory system determines the write data stored in the normal region as being in a normal state and rebuilds the write data, and when either transaction information including activated start information or transaction information including activated commit information is not retrieved, the memory system determines the write data stored in the normal region as being in an abnormal state and does not rebuild the write data.

In accordance with an embodiment of the present invention, an operating method of a data processing system including a host suitable for generating a plurality of write data grouped into transactions and a plurality of write commands, and a memory system suitable for storing the write data in a memory device in response to the write commands received from the host, may include generating, by the host, the write commands including transaction information of each of the write data; and storing, by the memory system, the write data in a normal region of the memory device and the transaction information included in each of the write commands in a spare region, which corresponds to the normal region, of the memory device.

The transaction information may include transaction ID information, commit information, and abort information.

First ID information, commit information and abort information may be included in transaction information of each of first write data grouped into a first transaction, and the storing of the write data in the normal region and the transaction information in the spare region of the memory device may include: identifying the write commands including the first ID information as first write commands and the write data corresponding to the first write commands as the first write data as a result of checking the transaction information of each of the write commands received from the host; and loading and storing transaction information included in the first write commands in a first spare region corresponding to a first normal region when the first write data are stored in the first normal region in response to the first write commands.

Second ID information, start information and commit information may be included in transaction information of each of second write data grouped into a second transaction, and the storing of the write data in the normal region and the transaction information in the spare region of the memory device may further include: identifying the write commands including the second ID information as second write commands and the write data corresponding to the second write commands as the second write data as a result of checking the transaction information of each of the write commands received from the host; and loading and storing transaction information included in the second write commands in a second spare region corresponding to a second normal region when the second write data are stored in the second normal region in response to the second write commands.

The memory device may include a plurality of pages, the first normal region includes a first data section of a first page among the pages, the second normal region includes a second data section of the first page, the first spare region includes a first spare section of the first page, and the second spare region includes a second spare section of the first page.

The memory device may include a plurality of pages, the first normal region may be a plurality of pages, the first normal region includes a data section of a first page among the pages, the second normal region includes a data section of a second page among the pages, the first spare region includes a spare section of the first page, and the second spare region includes a spare section of the second page.

The memory device may include a plurality of pages, the first normal region includes a data section of a first page group including two or more pages among the pages, the second normal region includes a data section of a second page group including two or more pages among the pages, the first spare region includes a spare section of the first page group, and the second spare region includes a spare section of the second page group.

The generating of the write commands of the transaction information of each of the write data may include: generating transaction information of last data among the write data including activated commit information and deactivated abort information into transaction information of last data among the write data for validating the write data, generating the transaction information of the last data including deactivated commit information and activated abort information for invalidating the write data, and generating transaction information of each of remaining intermediate data except for the last data among the write data including deactivated commit information and deactivated abort information.

The operating method may further include reading and checking the transaction information of the write data stored in the spare region when rebuilding the write data during a booting period where a power source is supplied again after sudden power-off (SPO) occurs while the memory system stores the write data in the memory device; determining the write data stored in the normal region as being in a normal state and rebuilding the write data when transaction information including activated commit information is retrieved as a result of the reading and checking of the transaction information; and determining the write data stored in the normal region as being in an abnormal state and not rebuilding the write data when transaction information including activated commit information is not retrieved or transaction information including activated abort information is retrieved as a result of the reading and checking of the transaction information.

In accordance with an embodiment of the present invention, a memory system may include: a memory device including a first region and a second region corresponding to the first region; and a controller suitable for: receiving a plurality of write data grouped into transactions and a plurality of write commands including transaction information of each of the write data; storing the write data in the first region in response to the write commands; and storing the transaction information included in each of the write commands in the second region.

The including and generating of the transaction information of each of the write data into the write commands may include: including and generating activated commit information and deactivated abort information into transaction information of last data among the write data in order to validate the write data, including and generating deactivated commit information and activated abort information into the transaction information of the last data in order to invalidate the write data, and including and generating deactivated commit information and deactivated abort information into transaction information of each of remaining intermediate data except for the last data among the write data. The operating method may further include: reading and checking the transaction information of the write data stored in the spare region when rebuilding the write data during a booting period where a power source is supplied again after sudden power-off (SPO) occurs while the memory system stores the write data in the memory device; determining the write data stored in the normal region as being in a normal state and rebuilding the write data when transaction information including activated commit information is retrieved as a result of the reading and checking of the transaction information; and determining the write data stored in the normal region as being in an abnormal state and not rebuilding the write data when transaction information including activated commit information is not retrieved or transaction information including activated abort information is retrieved as a result of the reading and checking of the transaction information.

These and other features and advantages of the present invention will become apparent to those with ordinary skill in the art to which the present invention belongs from the following description in conjunction with the accompanying drawings.

DETAILED DESCRIPTION

Various embodiments of the present invention are described below in more detail with reference to the accompanying drawings. We note, however, that the present invention may be embodied in different other embodiments, forms and variations thereof and should not be construed as being limited to the embodiments set forth herein. Rather, the described embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the present invention to those skilled in the art to which this invention pertains. Throughout the disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the present invention.

The drawings are not necessarily to scale and, in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiments. When an element is referred to as being connected or coupled to another element, it should be understood that the former can be directly connected or coupled to the latter, or electrically connected or coupled to the latter via an intervening element therebetween.

As used herein, singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise.

FIG. 1is a block diagram illustrating a data processing system100in accordance with an embodiment of the present invention.

Referring toFIG. 1, the data processing system100may include a host102operatively coupled to a memory system110.

The host102may include, for example, a portable electronic device such as a mobile phone, an MP3 player and a laptop computer or an electronic device such as a desktop computer, a game player, a TV, a projector and the like.

The memory system110may operate in response to a request from the host102, and in particular, store data to be accessed by the host102. The memory system110may be used as a main memory system or an auxiliary memory system of the host102. The memory system110may be implemented with any one of various types of storage devices, which may be electrically coupled with the host102, according to a protocol of a host interface. Examples of suitable storage devices include a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC) and a micro-MMC, a secure digital (SD) card, a mini-SD and a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick, and the like.

The storage devices for the memory system110may be implemented with a volatile memory device such as a dynamic random access memory (DRAM) and a static RAM (SRAM) and nonvolatile memory device such as a read only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase-change RAM (PRAM), a magneto-resistive RAM (MRAM), resistive RAM (RRAM) and a flash memory.

The memory system110may include a memory device150which stores data to be accessed by the host102, and a controller130which may control storage of data in the memory device150.

The controller130and the memory device150may be integrated into a single semiconductor device, which may be included in the various types of memory systems as exemplified above.

The memory system110may be configured as part of a computer, an ultra-mobile PC (UMPC), a workstation, a net-book, a personal digital assistant (PDA), a portable computer, a web tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game player, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a 3D television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage configuring a data center, a device capable of transmitting and receiving information under a wireless environment, one of various electronic devices configuring a home network, one of various electronic devices configuring a computer network, one of various electronic devices configuring a telematics network, a radio frequency identification (RFID) device, or one of various component elements configuring a computing system.

The memory device150may be a nonvolatile memory device and may retain data stored therein even though power is not supplied. The memory device150may store data provided from the host102through a write operation, and provide data stored therein to the host102through a read operation. The memory device150may include a plurality of memory blocks152to156, each of the memory blocks152to156may include a plurality of pages. Each of the pages may include a plurality of memory cells to which a plurality of word lines (WL) are electrically coupled.

The controller130may control overall operations of the memory device150, such as read, write, program and erase operations. For example, the controller130of the memory system110may control the memory device150in response to a request from the host102. The controller130may provide the data read from the memory device150, to the host102, and/or may store the data provided from the host102into the memory device150.

The controller130may include a host interface (I/F)132, a processor134, an error correction code (ECC) circuit138, a power management circuit (PMC)140, a memory device controller such as a memory interface (I/F)142and a memory144all operatively coupled via an internal bus.

The host interface132may process commands and data provided from the host102, and may communicate with the host102through at least one of various interface protocols such as universal serial bus (USB), multimedia card (MMC), peripheral component interconnect-express (PCI-E), small computer system interface (SCSI), serial-attached SCSI (SAS), serial advanced technology attachment (SATA), parallel advanced technology attachment (DATA), small computer system interface (SCSI), enhanced small disk interface (ESDI) and integrated drive electronics (IDE).

The ECC circuit138may detect and correct errors in the data read from the memory device150during the read operation. The ECC circuit138may not correct error bits when the number of the error bits is greater than or equal to a threshold number of correctable error bits, and may output an error correction fail signal indicating failure in correcting the error bits.

The ECC circuit138may perform an error correction operation based on a coded modulation such as a low density parity check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon (RS) code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), a Block coded modulation (BCM), and so on. The ECC circuit138may include all circuits, modules, systems or devices for the error correction operation.

The PMU140may provide and manage powerof the controller130.

The memory interface142may serve as a memory/storage interface between the controller130and the memory device150to allow the controller130to control the memory device150in response to a request from the host102. The memory interface142may generate a control signal for the memory device150and process data to be provided to the memory device150under the control of the processor134when the memory device150is a flash memory and, in particular, when the memory device150is a NAND flash memory.

The memory144may serve as a working memory of the memory system110and the controller130, and store data for driving the memory system110and the controller130. The controller130may control the memory device150in response to a request from the host102. The controller130may provide data read from the memory device150to the host102, may store data provided from the host102into the memory device150. The memory144may store data required for the controller130and the memory device150to perform these operations.

The memory144may be implemented with a volatile memory. The memory144may be implemented with a static random access memory (SRAM) or a dynamic random access memory (DRAM). AlthoughFIG. 1exemplifies the memory144disposed within the controller130, the present disclosure is not limited thereto. That is, the memory144may be disposed within or out of the controller130. For instance, in an embodiment, the memory144may be embodied by an external volatile memory having a memory interface transferring data between the memory144and the controller130.

The processor134may control the overall operations of the memory system110. The processor134may drive firmware to control the overall operations of the memory system110. The firmware may be referred to as flash translation layer (FTL).

A FTL may perform an operation as an interface between the host102and the memory device150. The host102may request the memory device150to perform write and read operations through the FTL.

The FTL may manage operations of address mapping, garbage collection, wear-leveling and so forth. Particularly, the FTL may store map data. Therefore, the controller130may map a logical address, which is provided from the host102, to a physical address of the memory device150through the map data. The memory device150may perform an operation like a general device because of the address mapping operation. Also, through the address mapping operation based on the map data, when the controller130updates data of a particular page, the controller130may program new data into another empty page and may invalidate old data of the particular page due to a characteristic of a flash memory device. Further, the controller130may store map data of the new data into the FTL.

The processor134may be implemented with a microprocessor or a central processing unit (CPU). The memory system110may include one or more processors134.

A management circuit (not shown) may be included in the processor134, and may perform bad block management of the memory device150. The management circuit may find bad memory blocks included in the memory device150, which are in unsatisfactory condition for further use, and perform bad block management on the bad memory blocks. When the memory device150is a flash memory, for example, a NAND flash memory, a program failure may occur during the write operation, for example, during the program operation, due to characteristics of a NAND logic function. During the bad block management, the data of the program-failed memory block or the bad memory block may be programmed into a new memory block. Also, the bad blocks seriously deteriorate the utilization efficiency of the memory device150having a 3D stack structure and the reliability of the memory system100, and thus reliable bad block management is required.

FIG. 2is a schematic diagram illustrating the memory device150.

Referring toFIG. 2, the memory device150may include the plurality of memory blocks BLOCK0to BLOCKN−1, and each of the blocks BLOCK0to BLOCKN−1 may include a plurality of pages, for example, 2Mpages, the number of which may vary according to circuit design. The memory device150may include a plurality of memory blocks, such as single level cell (SLC) memory blocks and multi-level cell (MLC) memory blocks, according to the number of bits which may be stored or expressed in each memory cell. The SLC memory block may include a plurality of pages which are implemented with memory cells each capable of storing 1-bit data. The MLC memory block may include a plurality of pages which are implemented with memory cells each capable of storing multi-bit data, for example, two or more-bit data. An MLC memory block including a plurality of pages which are implemented with memory cells that are each capable of storing 3-bit data may be defined as a triple level cell (TLC) memory block.

FIG. 3is a circuit diagram illustrating a memory block330in the memory device150.

Referring toFIG. 3, the memory block330corresponds to any of the plurality of memory blocks152to156.

Referring toFIG. 3, the memory block152of the memory device150may include a plurality of cell strings340which are electrically coupled to bit lines BL0to BLm−1, respectively. The cell string340of each column may include at least one drain select transistor DST and at least one source select transistor SST. A plurality of memory cells or a plurality of memory cell transistors MC0to MCn−1 may be electrically coupled in series between the select transistors DST and SST. The respective memory cells MC0to MCn−1 may be configured by single level cells (SLC) each of which may store 1 bit of information, or by multi-level cells (MLC) each of which may store data information of a plurality of bits. The strings340may be electrically coupled to the corresponding bit lines BL0to BLm−1, respectively. For reference, inFIG. 3, ‘DSL’ denotes a drain select line, ‘SSL’ denotes a source select line, and ‘CSL’ denotes a common source line.

WhileFIG. 3only shows, as an example, the memory block152which is configured by NAND flash memory cells, it is to be noted that the memory block152of the memory device150according to the embodiment is not limited to NAND flash memory and may be realized by NOR flash memory, hybrid flash memory in which at least two kinds of memory cells are combined, or one-NAND flash memory in which a controller is built in a memory chip. The operational characteristics of a semiconductor device may be applied to not only a flash memory device in which a charge storing layer is configured by conductive floating gates but also a charge trap flash (CTF) in which a charge storing layer is configured by a dielectric layer.

A power supply circuit310of the memory device150may provide word line voltages, for example, a program voltage, a read voltage and a pass voltage, to be supplied to respective word lines according to an operation mode and voltages to be supplied to bulks, for example, well regions in which the memory cells are formed. The power supply circuit310may perform a voltage generating operation under the control of a control circuit (not shown). The power supply circuit310may generate a plurality of variable read voltages to generate a plurality of read data, select one of the memory blocks or sectors of a memory cell array under the control of the control circuit, select one of the word lines of the selected memory block, and provide the word line voltages to the selected word line and unselected word lines.

A read/write circuit320of the memory device150may be controlled by the control circuit, and may serve as a sense amplifier or a write driver according to an operation mode. During a verification/normal read operation, the read/write circuit320may operate as a sense amplifier for reading data from the memory cell array. During a program operation, the read/write circuit320may operate as a write driver for driving bit lines according to data to be stored in the memory cell array. During a program operation, the read/write circuit320may receive from a buffer (not illustrated) data to be stored into the memory cell array, and drive bit lines according to the received data. The read/write circuit320may include a plurality of page buffers322to326respectively corresponding to columns (or bit lines or column pairs (or bit line pairs), and each of the page buffers322to326may include a plurality of latches (not illustrated).

FIG. 4is a schematic diagram illustrating a 3D structure of the memory device150.

The memory device150may be embodied by a 2D or 3D memory device. Specifically, as illustrated inFIG. 4, the memory device150may be embodied by a nonvolatile memory device having a 3D stack structure. When the memory device150has a 3D structure, the memory device150may include a plurality of memory blocks BLK0to BLKN−1 each having a 3D structure (or vertical structure).

FIG. 5is a diagram illustrating an operation of processing a plurality of write data grouped into transactions in a data processing system in accordance with an embodiment of the present invention.

Referring toFIG. 5, the data processing system100may include the host102and the memory system110. The data processing system100may have the configuration shown inFIG. 1.

The memory system110may include the controller130and the memory device150as described above with reference toFIG. 1.

The memory device150may include the plurality of memory blocks152and154as described above with reference toFIG. 1. Each of the memory blocks152and154may include a plurality of pages, e.g., 2MPAGES as described above with reference toFIG. 2.

AlthoughFIG. 5shows just a single non-volatile memory device150included in the memory system110, we note that a plurality of non-volatile memory devices may be included in the memory system110. Also, for the sake of convenience in description, only five pages P10to P15are shown in memory block152and only five pages are shown in memory block154. It is noted that the number of pages in each block may be different.

Although it is illustrated that the host interface (I/F)132, the processor134, the error correction code (ECC) circuit138, the power management circuit (PMC)140, the NAND flash controller142and the memory144included in the controller130ofFIG. 1are not included in the controller130ofFIG. 5, they are omitted in the drawing for the sake of convenience in description. In actuality, they may be included in the controller130.

Referring toFIG. 5, the host102may generate a plurality of write data WTDT<1:N+M> grouped into transactions and a plurality of write commands WCMD<1:N+M> for controlling an operation of storing the write data WTDT<1:N+M> in the memory system110, and transmit the generated write data WTDT<1:N+M> and write commands WCMD<1:N+M> to the memory system110.

The memory system110may store the write data WTDT<1:N+M> in the memory device150in response to the write commands WCMD<1:N+M> received from the host102.

According to the present invention, the write data WTDT<1:N+M> are grouped into a plurality of transactions, hence, the write operation performed in the data processing system100of the present invention is different from a conventional write operation performed in a conventional data processing system.

According to the present invention, grouping the write data WTDT<1:N+M> into a plurality of transactions means that a plurality of write data, which are used for the same purpose are grouped into a single transaction. For example, first write data 1st_WTDT<1:N> and second write data 2nd_WTDT<1:M> among the write data WTDT<1:N+M>, which are used for the same purpose, are grouped into a single transaction.

Examples of various data purposes may be modification, addition, or update of data. Hence, in an embodiment, write data used for modification of data may be grouped into one transaction, write data used for addition of data may be grouped into another transaction, and write data used for the purpose of update of data may be grouped into yet another transaction. In sum, write data may be grouped into a plurality of transactions depending on the purpose of the write data. In another embodiment, data for the purpose of modification of the database may be grouped into one transaction group, and data for the purpose of addition to the database may be grouped into another transaction group.

When the host102transmits the write data grouped into one transaction, e.g., the first write data 1st_WTDT<1:N> or the second write data 2nd_WTDT<1:M>, to the memory system110, all the data which are grouped into one transaction should be transmitted from the host102and stored in the memory system110so that the data of the transaction can be designated as being in a valid commit state. If at least one of the data of a transaction is not transmitted and stored then none of the data of the transaction can be placed in a valid commit state. Also, all the data of a transaction may be placed in an invalid abort state according to an abort request received from the host102.

That is, the write data grouped into one transaction, e.g., the first write data 1st_WTDT<1:N> or the second write data 2nd_WTDT<1:M>, may be valid only when they are all transmitted and stored so as to be all in the valid commit state.

For example, for the first write data 1st_WTDT<1:N> which are grouped into a first transaction to be placed in the valid commit state in the memory system110, all of the “N” first write data 1st_WTDT<1:N> should be transmitted and stored from the host102into the memory system110, and simultaneously there has to be no abort request received from the host102. When even one of the “N” first write data 1st_WTDT<1:N> is not transmitted and stored, or when the abort request from the host102is received before the completion of the transmission and storage of all of the first write data 1st_WTDT<1:N>, then all the first write data 1st_WTDT<1:N> are placed in the abort state in the memory system110.

The described operation of dividing and managing the write data WTDT<1:N+M> grouped into transactions into the commit state or the abort state is generally referred to herein as an operation for securing the atomicity of the transactions.

When the write data WTDT<1:N+M> are transmitted from the host102to the memory system110, the write data grouped into a plurality of transactions, e.g., the first write data 1st_WTDT<1:N> or the second write data 2nd_WTDT<1:M>, may be transmitted in a randomly mixed state to the memory system110. For example, when the first write data 1st_WTDT<1:N> grouped into the first transaction and the second write data 2nd_WTDT<1:M> grouped into a second transaction are transmitted from the host102to the memory system110, the first write data 1st_WTDT<1:N> and the second write data 2nd_WTDT<1:M> may be distinguished by an identifying transaction ID, and may be transmitted as the write data WTDT<1:N+M> in the randomly mixed state.

In an embodiment, the write data WTDT<1:N+M> may be grouped into a plurality of transactions generated from the host102and may then be transmitted in a randomly mixed state to the memory system110according to an exemplary method illustrated inFIG. 6A.

Referring toFIG. 6A, the host102may generate first write data 1st_WTDT<1:2> grouped into the first transaction and first write commands 1st_WCMD<1:2> including first transaction ID TID1to control an operation of storing the first write data 1st_WTDT<1:2> in the memory system110, and may transmit the first write data 1st_WTDT<1:2> and the first write commands 1st_WCMD<1:2> to the memory system110.

Also, the host102may generate second write data 2nd_WTDT<1:3> grouped into the second transaction and second write commands 2nd_WCMD<1:3> including second transaction ID TID2to control an operation of storing the second write data 2nd_WTDT<1:3> in the memory system110, and may transmit the second write data 2nd_WTDT<1:3> and the second write commands 2nd_WCMD<1:3> to the memory system110.

At this time, each of the first write commands 1st_WCMD<1:2> and each of the first write data 1st_WTDT<1:2> may be transmitted at a time point T1and a time point T3which are discontinuous with each other. Each of the second write commands 2nd_WCMD<1:3> and each of the second write data 2nd_WTDT<1:3> may be transmitted at a time point T2, a time point T5and a time point T6which are discontinuous with each other.

In this manner, the first write commands 1st_WCMD<1:2> and first write data 1st_WTDT<1:2> and the second write commands WCMD<1:3> and second write data 2nd_WTDT<1:3> may be transmitted in a randomly mixed state from the host102to the memory system110.

As a result of checking that the write commands WCMD<1:2+3> transmitted from the host102at the time points T1and T3include the first transaction ID TID1, the memory system110may identify the write commands WCMD<1:2+3> transmitted from the host102at the time points T1and T3as the first write commands 1st_WCMD<1:2> and the write data WTDT<1:2+3> transmitted from the host102at the time points T1and T3as the first write data 1st_WTDT<1:2> grouped into the first transaction.

Accordingly, the memory system110may store the first write data 1st_WTDT<1:2> in the memory device150in response to the first write commands 1st_WCMD<1:2>. The memory system110may manage first map information TID1_MAP for indicating that the first write data 1st_WTDT<1:2> stored in the memory device150at the time points T1and T3are included in a first transaction group. That is, the memory system110may use a way of including information indicating that the first write data 1st_WTDT<1:2> are grouped into the first transaction in the first map information TID1_MAP that manages a mapping relationship between a physical address and a logical address for the first write data 1st_WTDT<1:2>. The first map information TID1_MAP may be managed in the memory144having volatile characteristics in the memory system110before it is identified that the first write data 1st_WTDT<1:2> are in the commit state, and then may be stored in the memory device150having non-volatile characteristics when it is identified that the first write data 1st_WTDT<1:2> are in the commit state.

In this case, the host102may recognize that the first write data 1st_WTDT<1:2> include two data, but the memory system110may not. Accordingly, after the first write data 1st_WTDT<1:2> are transmitted from the host102to the memory system110, the host102may generate a first commit command 1st_COMMIT for indicating that transmission of the first write data 1st_WTDT<1:2> is completed, and transmit the first commit command 1st_COMMIT to the memory system110. That is, as illustrated in the drawing, the host102may generate and transmit the first commit command 1st_COMMIT to the memory system110at a time point T4subsequent to the time point T3where the transmission of the first write data 1st_WTDT<1:2> is completed. Accordingly, the memory system110may check the first write data 1st_WTDT<1:2> being in the commit state, and store the first map information TID1_MAP managed in the memory144in the memory device150.

Similarly, as a result of checking that the write commands WCMD<1:2+3> transmitted from the host102at the time points T2, T5and T6include the second transaction ID TID2, the memory system110may identify the write commands WCMD<1:2+3> transmitted from the host102at the time points T2, T5and T6as the second write commands 2nd_WCMD<1:3> and the write data WTDT<1:2+3> transmitted from the host102at the time points T2, T5and T6as the second write data 2nd_WTDT<1:3> grouped into the second transaction.

Accordingly, the memory system110may store the second write data 2nd_WTDT<1:3> in the memory device150in response to the second write commands 2nd_WCMD<1:3>. The memory system110may manage second map information TID2_MAP for indicating that the second write data 2nd_WTDT<1:3> stored in the memory device150at the T2, T5and T6time points are included in a second transaction group. That is, the memory system110may use a way of including information indicating that the second write data 2nd_WTDT<1:3> are grouped into the second transaction in the second map information TID2_MAP that manages a mapping relationship between a physical address and a logical address for the second write data 2nd_WTDT<1:3>. The second map information TID2_MAP may be managed in the memory144of the memory system110before it is identified that the second write data 2nd_WTDT<1:3> are in the commit state, and then may be stored in the memory device150having non-volatile characteristics when it is identified that the second write data 2nd_WTDT<1:3> are in the commit state.

In This case, the host102may recognize that the second write data 2nd_WTDT<1:3> include three data, but the memory system110may not. Accordingly, after the second write data 2nd_WTDT<1:3> are transmitted from the host102to the memory system110, the host102may generate a second commit command 2nd_COMMIT for indicating that transmission of the second write data 2nd_WTDT<1:3> is completed, and transmit the second commit command 2nd_COMMIT to the memory system110. That is, as illustrated in the drawing, the host102may generate and transmit the second commit command 2nd_COMMIT to the memory system110at a time point T7subsequent to the time point T6where the transmission of the second write data 2nd_WTDT<1:3> is completed. Accordingly, the memory system110may check the second write data 2nd_WTDT<1:3> being in the commit state, and store the second map information TID2_MAP managed in the memory144in the memory device150.

A case where it is checked that the first write data 1st_WTDT<1:2> and the second write data 2nd_WTDT<1:3> are in the commit state is exemplified in the aforementioned description. When the state of the first write data 1st_WTDT<1:2> or second write data 2nd_WTDT<1:3> is transitioned into the abort state according to the abort request of the host102, an abort command (not illustrated) may be transmitted from the host102to the memory system110regardless of a time point. For example, when the state of the first write data 1st_WTDT<1:2> is transitioned into the abort state, the host102may transmit the abort command (not illustrated) instead of the first write commands 1st_WCMD<2> and the first write data 1st_WTDT<2> to the memory system110at the time point T3. For another example, when the state of the first write data 1st_WTDT<1:2> is transitioned into the abort state, the host102may transmit the abort command (not illustrated) instead of the first commit command 1st_COMMIT to the memory system110at the time point T4.

As described above with reference toFIG. 6A, it may be seen that the host102generates and transmits the commit commands 1st_COMMIT and 2nd_COMMIT to secure atomicity of the transactions while generating and transmitting the write data WTDT<1:2+3> grouped into the plurality of transactions to the memory system110. Also, the memory system110may manage the map information TID1_MAP and TID2_MAP for the write data WTDT<1:2+3> grouped into the transactions just in the memory144before the commit commands 1st_COMMIT and 2nd_COMMIT are transmitted from the host102, and then may store the map information TID1_MAP and TID2_MAP in the memory device150after the commit commands 1st_COMMIT and 2nd_COMMIT are transmitted from the host102, thereby supporting an operation of securing the atomicity of the transactions.

However, in the operation as shown inFIG. 6A, there is a burden on the host102to generate the separate commit commands 1st_COMMIT and 2nd_COMMIT in order to support the operation of securing the atomicity of the transactions, and there is a burden on the memory system110to store the map information TID1_MAP and TID2_MAP in the memory device150whenever commits of the transactions are checked.

Another method illustrated inFIGS. 5, 6B and 6Cmay be applied to the data processing system100in accordance with an embodiment of the present invention. The method addresses the aforementioned limitations of the method described with reference toFIGS. 5 and 6A.

Referring again toFIG. 5, the host102may generate the write data WTDT<1:N+M> grouped into a plurality of transactions and the write commands WCMD<1:N+M> including transaction information TRINFO<1:N+M> of the write data WTDT<1:N+M>. For example, the host102may generate the first write data 1st_WTDT<1:N> corresponding to the first transaction and the first write commands 1st_WCMD<1:N> for controlling an operation of storing the first write data 1st_WTDT<1:N> in the memory system110in operation1021. In this case, the host102may include transaction information TRINFO<1:N> of the first write data 1st_WTDT<1:N> in the first write commands 1st_WCMD<1:N>, respectively, in operation1023. Also, the host102may generate the second write data 2nd_WTDT<1:M> corresponding to the second transaction and the second write commands 2nd_WCMD<1:M> for controlling an operation of storing the second write data 2nd_WTDT<1:M> in the memory system110in operation1022. In this case, the host102may include transaction information TRINFO<N+1:N+M> of the second write data 2nd_WTDT<1:M> in the second write commands 2nd_WCMD<1:M>, respectively, in operation1024.

In various embodiments, the transaction information TRINFO<1:N+M> of the write data WTDT<1:N+M> generated from the host102, as illustrated inFIG. 7A, may include transaction ID information TX ID, commit information Commit, and abort information Abort.

In some embodiments, the transaction ID information may indicate which transaction each of the write data WTDT<1:N+M> is grouped into. For example, it may be assumed that the host102generates the first write data 1st_WTDT<1:N> grouped into the first transaction and the second write data 2nd_WTDT<1:M> grouped into the second transaction. In this state, the transaction information TRINFO<1:N> corresponding to the first write data 1st_WTDT<1:N> may include the first transaction ID TID1indicating that the first write data 1st_WTDT<1:N> are grouped into the first transaction as the transaction ID information. Similarly, the transaction information TRINFO<N+1:N+M> corresponding to the second write data 2nd_WTDT<1:M> may include the second transaction ID TID2indicating that the second write data 2nd_WTDT<1:M> are grouped into the second transaction as the transaction ID information.

In some embodiments, the commit information and the abort information may indicate whether all the write data WTDT<1:N+M> are placed in the valid commit state or in the invalid abort state, respectively.

For example, as shown inFIG. 7A, when the commit information is included in the Nth first write data 1st_WTDT<N> which is last data among the first write data 1st_WTDT<1:N>, all the first write data 1st_WTDT<1:N> may be placed in the valid commit state. On the contrary, when the abort information is included in the Nth first write data 1st_WTDT<N>, all the first write data 1st_WTDT<1:N> may be placed in the invalid abort state.

Similarly, when the commit information is included in the Mth second write data 2nd_WTDT<M> which is last data among the second write data 2nd_WTDT<1:M>, all the second write data 2nd_WTDT<1:M> may be placed in the valid commit state. On the contrary, when the abort information is included in the Mth second write data 2nd_WTDT<M>, all the second write data 2nd_WTDT<1:M> may be placed in the invalid abort state.

Since each of the commit information and the abort information determines the write data 1st_WTDT<1:N> or 2nd_WTDT<1:M> as the respective commit state and abort state, the commit information and the abort information may be included in the last data 1st_WTDT<N> or 2nd_WTDT<M> among the write data 1st_WTDT<1:N> or 2nd_WTDT<1:M>, respectively.

Therefore, as shown inFIG. 6B, the transaction information TRINFO<1:N−1> corresponding to the first to (N−1)th first write data 1st_WTDT<1:N−1> may include deactivated commit information CM_NO and deactivated abort information AB_NO. The transaction information TRINFO<N> corresponding to the Nth first write data 1st_WTDT<N> may include activated commit information CM_YES and deactivated abort information AB_NO or deactivated commit information CM_NO and activated abort information AB_YES.

Similarly, as shown inFIG. 6B, the transaction information TRINFO<N+1:N+M−1> corresponding to the first to (M−1)th second write data 2nd_WTDT<1:M−1> may include deactivated commit information CM_NO and deactivated abort information AB_NO. The transaction information TRINFO<N+M> corresponding to the Mth second write data 2nd_WTDT<M> may include activated commit information CM_YES and deactivated abort information AB_NO. Alternatively, the transaction information TRINFO<N+M> corresponding to the Mth second write data 2nd_WTDT<M> may include deactivated commit information CM_NO and activated abort information AB_YES.

Herein, an example of the transaction information TRINFO<1:N+M> may refer to a format of the transaction information TRINFO<1:N+M> shown inFIG. 7A. For example, when it is assumed that each of the transaction information TRINFO<1:N+M> has a 1 byte, five bits (0thbit to 4thbit) may be allocated as the transaction ID information, one bit (5thbit) may be allocated as the commit information, one bit (6thbit) may be allocated as the abort information, and remaining one bit (7thbit) may be allocated as a reserved information.

In various embodiments, the transaction information TRINFO<1:N+M> of the write data WTDT<1:N+M> generated from the host102, as illustrated inFIG. 7B, may include transaction ID information TX ID, commit information Commit, abort information Abort, and start information Start.

In some embodiments, the transaction ID information may indicate which transaction each of the write data WTDT<1:N+M> is grouped into. For example, it may be assumed that the host102generates the first write data 1st_WTDT<1:N> grouped into the first transaction and the second write data 2nd_WTDT<1:M> grouped into the second transaction. In this stage, the transaction information TRINFO<1:N> corresponding to the first write data 1st_WTDT<1:N> may include the first transaction ID TID1indicating that the first write data 1st_WTDT<1:N> are grouped into the first transaction as the transaction ID information. Similarly, the transaction information TRINFO<N+1:N+M> corresponding to the second write data 2nd_WTDT<1:M> may include the second transaction ID TID2indicating that the second write data 2nd_WTDT<1:M> are grouped into the second transaction as the transaction ID information.

In some embodiments, the commit information and the abort information may indicate whether all the write data WTDT<1:N+M> are placed in the valid commit state or in the invalid abort state, respectively.

For example, as shown inFIG. 7B, when the commit information is included in the Nth first write data 1st_WTDT<N> which is last data among the first write data 1st_WTDT<1:N>, all the first write data 1st_WTDT<1:N> may be placed in the valid commit state. On the contrary, when the abort information is included in the Nth first write data 1st_WTDT<N>, all the first write data 1st_WTDT<1:N> may be placed in the invalid abort state.

Similarly, when the commit information is included in the Mth second write data 2nd_WTDT<M> which is last data among the second write data 2nd_WTDT<1:M>, all the second write data 2nd_WTDT<1:M> may be placed in the valid commit state. On the contrary, when the abort information is included in the Mth second write data 2nd_WTDT<M>, all the second write data 2nd_WTDT<1:M> may be placed in the invalid abort state.

Since each of the commit information and the abort information determines the write data 1st_WTDT<1:N> or 2nd_WTDT<1:M> as the respective commit state and abort state, the commit information and the abort information may be included in the last data 1st_WTDT<N> or 2nd_WTDT<M> among the write data 1st_WTDT<1:N> or 2nd_WTDT<1:M>, respectively.

In some embodiments, the start information may indicate start data 1st_WTDT<1> or 2nd_WTDT<1> of the write data 1st_WTDT<1:N> or 2nd_WTDT<1:M>.

Therefore, as shown inFIG. 6C, the transaction information TRINFO<1> corresponding to the first write data 1st_WTDT<1> may include activated start information ST_YES, deactivated commit information CM_NO and deactivated abort information AB_NO, and the transaction information TRINFO<2:N−1> corresponding to the second to (N−1)th first write data 1st_WTDT<2:N−1> may include deactivated start information ST_NO, deactivate commit information CM_NO and deactivated abort information AB_NO. The transaction information TRINFO<N> corresponding to the Nth first write data 1st_WTDT<N> may include deactivated start information ST_NO, activated commit information CM_YES and deactivate abort information AB_NO or deactivated start information ST_NO, deactivated commit information CM_NO and activated abort information CM_YES.

Similarly, as shown inFIG. 6C, the transaction information TRINFO<N+1> corresponding to the second write data 2nd_WTDT<1> may include activated start information ST_YES, deactivated commit information CM_NO and deactivated abort information AB_NO. The transaction information TRINFO<N+2:N+M−1> corresponding to the second to (M−1)th second write data 2nd_WTDT<2:M−1> may include deactivated start information ST_NO, deactivated commit information CM_NO and deactivated abort information AB_NO. The transaction information TRINFO<N+M> corresponding to the Mth second write data 2nd_WTDT<M> may include deactivated start information ST_NO, activated commit information CM_YES and deactivated abort information CM_NO. Alternatively, the transaction information TRINFO<N+M> corresponding to the Mth second write data 2nd_WTDT<M> may include deactivated start information ST_NO, deactivated commit information CM_NO and activated abort information AB_YES.

Herein, an example of the transaction information TRINFO<1:N+M> may refer to a format of the transaction information TRINFO<1:N+M> shown inFIG. 7B. For example, when it is assumed that each of the transaction information TRINFO<1:N+M> has a 1 byte, five bits (0thbit to 4thbit) may be allocated as the transaction ID information, one bit (5thbit) may be allocated as the commit information, one bit (6thbit) may be allocated as the abort information, and remaining one bit (7thbit) may be allocated as the start information.

Referring again toFIG. 5, The memory system110may include the controller130for controlling an operation of storing the write data WTDT<1:N+M> in the memory device150in response to the write commands WCMD<1:N+M> received from the host102, and the memory device150for storing the write data WTDT<1:N+M> according to the control of the controller130.

Herein, the memory device150may include the memory blocks152and154, the memory blocks152and154may include pages P1<0:5> and P2<0:5>, respectively. Each of the pages P1<0:5> and P2<0:5> may include normal regions N1, N2, N3and N4and spare regions S1, S2, S3and S4.

The controller130may store the write data WTDT<1:N+M> in the normal regions N1, N2, N3and N4of the memory device150in response to the write commands WCMD<1:N+M> received from the host102. Also, the controller130may store the transaction information TRINFO<1:N+M> included in the write commands WCMD<1:N+M> in the spare regions S1, S2, S3and S4corresponding to the normal regions N1, N2, N3and N4.

Specifically, the controller130may check the transaction information TRINFO<1:N+M> of the write commands WCMD<1:N+M> received from the host102in operation1301.

As a result of check in operation1301, the write commands WCMD<1:N> including the first transaction ID TID1as the transaction ID information among the transaction information TRINFO<1:N+M> may be qualified as the first write commands 1st_WCMD<1:N> in operation1302. Besides, as the result of check in operation1301, the write commands WCMD<N+1:N+M> including the second transaction ID TID2as the transaction ID information among the transaction information TRINFO<1:N+M> may be qualified as the second write commands 2nd_WCMD<1:M> in operation1302.

As a result of operation1302, the write data WTDT<1:N> corresponding to the first write commands 1st_WCMD<1:N> may be qualified as the first write data 1st_WTDT<1:N> in operation1303. Besides, as the result of operation1302, the write data WTDT<N+1:N+M> corresponding to the second write commands 2nd_WCMD<1:M> may be qualified as the second write data 2nd_WTDT<1:M> in operation1303.

After operation1302and operation1303, when the first write data 1st_WTDT<1:N> are stored in a first normal region of the memory device150in response to the first write commands 1st_WCMD<1:N>, the transaction information TRINFO<1:N> included in the first write commands 1st_WCMD<1:N> may be loaded and stored in a first spare region corresponding to the first normal region in operation1304. Besides, after operation1302and operation1303, when the second write data 2nd_WTDT<1:M> are stored in a second normal region of the memory device150in response to the second write commands 2nd_WCMD<1:M>, the transaction information TRINFO<N+1:N+M> included in the second write commands 2nd_WCMD<1:M> may be loaded and stored in a second spare region corresponding to the second normal region in operation1304.

The first normal region where the first write data 1st_WTDT<1:N> are stored, the first spare region where the transaction information TRINFO<1:N> corresponding to the first write data 1st_WTDT<1:N> are stored, the second normal region where the second write data 2nd_WTDT<1:M> are stored, and the second spare region where the transaction information TRINFO<N+1:N+M> corresponding to the second write data 2nd_WTDT<1:M> are stored may be defined according to various embodiments as follows.

According to a first embodiment, a first data section N1of any one, for example, a first page P10of the first memory block152, of the pages P1<0:5> and P2<0:5> included in the memory device150may be set to the first normal region. A first spare section S1corresponding to the first data section N1of the first page P10may be set to the first spare region. A second data section N2of the first page P10may be set to the second normal region. A second spare section S2corresponding to the second data section N2of the first page P10may be set to the second spare region.

According to another first embodiment, first and second data sections N1and N2of any one, for example, the first page P10of the first memory block152, of the pages P1<0:5> and P2<0:5> included in the memory device150may be set to the first normal region. First and second spare sections S1and S2corresponding to the first and second data sections N1and N2of the first page P10may be set to the first spare region. Third and fourth data sections N3and N4of the first page P10may be set to the second normal region. Third and fourth spare sections S3and S4corresponding to the third and fourth data sections N3and N4of the first page P10may be set to the second spare region.

That is, according to the first embodiments, all of the first normal region, the second normal region, the first spare region and the second spare region may be included in any one of the pages P1<0:5> and P2<0:5> included in the memory device150.

According to a second embodiment, data sections N1, N2, N3and N4of any one, for example, a first page P10of the first memory block152, of the pages P1<0:5> and P2<0:5> included in the memory device150may be set to the first normal region. Spare sections S1, S2, S3and S4of the first page P10of the first memory block152may be set to the first spare region. Data sections N1, N2, N3and N4of a second page P11of the first memory block152may be set to the second normal region. Spare sections S1, S2, S3and S4of the second page P11of the first memory block152may be set to the second spare region.

According to another second embodiment, data sections N1, N2, N3and N4of any one, for example, the first page P10of the first memory block152, of the pages P1<0:5> and P2<0:5> included in the memory device150may be set to the first normal region. Spare sections S1, S2, S3and S4of the first page P10of the first memory block152may be set to the first spare region. Data sections N1,N2, N3and N4of a first page P20of the second memory block154may be set to the second normal region. Spare sections S1, S2, S3and S4of the first page P20of the second memory block154may be set to the second spare region.

That is, according to the second embodiments, when the first normal region and the first spare region are included in any one of the pages P1<0:5> and P2<0:5> included in the memory device150, the second normal region and the second spare region may be included in another page.

According to a third embodiment, data sections N1, N2, N3and N4of two or more pages, for example, first and second pages P10and P11of the first memory block152, of the pages P1<0:5> and P2<0:5> included in the memory device150may be set to the first normal region. Spare sections S1, S2, S3and S4of the first and second pages P10and P11of the first memory block152may be set to the first spare region. Data sections N1, N2, N3and N4of third and fourth pages P12and P13of the first memory block152may be set to the second normal region. Spare sections S1, S2, S3and S4of the third and fourth pages P12and P13of the first memory block152may be set to the second spare region.

According to another third embodiment, data sections N1, N2, N3and N4of two or more pages, for example, the first and second pages P10and P11of the first memory block152, of the pages P1<0:5> and P2<0:5> included in the memory device150may be set to the first normal region. Spare sections S1, S2, S3and S4of the first and second pages P10and P11of the first memory block152may be set to the first spare region. Data sections N1, N2, N3and N4of first and second pages P20and P21of the second memory block154may be set to the second normal region. Spare sections S1, S2, S3and S4of the first and second pages P20and P21of the second memory block154may be set to the second spare region.

That is, according to the third embodiments, when the first normal region and the first spare region are included in two or more pages of the pages P1<0:5> and P2<0:5> included in the memory device150, the second normal region and the second spare region may be included in another two or more pages.

In the first to third embodiments, it is described that the first normal region and the second normal region have the same size all the time, and thus the first spare region and the second spare region also have the same size all the time. However, this is merely an example. For example, the first embodiments may be applied to the first normal region and the first spare region, the second embodiments may be applied to the second normal region and the second spare region.

Referring again toFIGS. 6B and 6C, the host102may generate the first write data 1st_WTDT<1:2> grouped into the first transaction and the first write commands 1st_WCMD<1:2> including the transaction information TRINFO<1:2> including the first transaction ID TID1to control an operation of storing the first write data 1st_WTDT<1:2> in the memory system110, and transmit the first write data 1st_WTDT<1:2> and the first write commands 1st_WCMD<1:2> to the memory system110.

In addition, the host102may generate the second write data 2nd_WTDT<1:3> grouped into the second transaction and the second write commands 2nd_WCMD<1:3> including transaction information TRINFO<3:5> including the second transaction ID TID2to control an operation of storing the second write data 2nd_WTDT<1:3> in the memory system110, and transmit the second write data 2nd_WTDT<1:3> and the second write commands 2nd_WCMD<1:3> to the memory system110.

At this time, the first write commands 1st_WCMD<1:2> and the first write data 1st_WTDT<1:2> may be transmitted at a time point T1and a time point T3which are discontinuous with each other. The second write commands 2nd_WCMD<1:3> and the second write data 2nd_WTDT<1:3> may be transmitted at a time point T2, a time point T4and a time point T5which are discontinuous with each other.

In this manner, it may be seen that the first write commands 1st_WCMD<1:2> and first write data 1st_WTDT<1:2> and the second write commands 2nd_WCMD<1:3> and second write data 2nd_WTDT<1:3> are transmitted in the randomly mixed state from the host102to the memory system110.

As a result of checkig that the transaction information TRINFO<1:2+3> included in the write commands WCMD<1:2+3> received from the host102at the time points T1and T3include the first transaction ID TID1, the memory system110may identify the write commands WCMD<1:2+3> received from the host102at the time points T1and T3as the first write commands 1st_WCMD<1:2> and the write data WTDT<1:2+3> received from the host102at the time points T1and T3as the first write data 1st_WTDT<1:2> grouped into the first transaction.

Accordingly, the memory system110may store the first write data 1st_WTDT<1:2> in the first normal region included in the memory device150in response to the first write commands 1st_WCMD<1:2>, and may load the transaction information TRINFO<1:2> corresponding to the first write data 1st_WTDT<1:2> included in the first write commands 1st_WCMD<1:2> and store the transaction information TRINFO<1:2> in the first spare region included in the memory device150. That is, the memory system110may store the first write data 1st_WTDT<1:2> in the first normal region, and then store the transaction information TRINFO<1:2> of the first write data 1st_WTDT<1:2> in the first spare region corresponding to the first normal region.

In addition, as a result of checking that the transaction information TRINFO<1:2+3> included in the write commands WCMD<1:2+3> received from the host102at the time points T2, T4and T5include the second transaction ID TID2, the memory system110may identify the write commands WCMD<1:2+3> received from the host102at the time points T2, T4and T5as the second write commands 2nd_WCMD<1:3> and the write data WTDT<1:2+3> received from the host102at the time points T2, T4and T5as the second write data 2nd_WTDT<1:3> grouped into the second transaction.

Accordingly, the memory system110may store the second write data 2nd_WTDT<1:3> in the second normal region included in the memory device150in response to the second write commands 2nd_WCMD<1:3>. Also, the memory system110may load the transaction information TRINFO<3:5> corresponding to the second write data 2nd_WTDT<1:3> included in the second write commands 2nd_WCMD<1:3> and store the transaction information TRINFO<3:5> in the second spare region included in the memory device150. That is, the memory system110may store the second write data 2nd_WTDT<1:3> in the second normal region, and then store the transaction information TRINFO<3:5> of the second write data 2nd_WTDT<1:3> in the second spare region corresponding to the second normal region.

Herein, referring again toFIG. 6B, it may be seen that not only the first transaction ID TID1as the transaction ID information but also the commit information CM and the abort information AB are included in the transaction information TRINFO<1:2> of the first write data 1st_WTDT<1:2>.

Accordingly, it may be seen whether the first write data 1st_WTDT<1:2> stored in the first normal region are in the commit state or in the abort state, through an operation of checking the transaction information TRINFO<1:2> of the first write data 1st_WTDT<1:2> stored in the first spare region.

For example, it may be seen that the first transaction ID TID1, the deactivated commit information CM_NO and the deactivated abort information AB_NO are included in the transaction information TRINFO<1> of the first write data 1st_WTDT<1> stored in the first spare region of the memory device150, which is generated and transmitted from the host102at the time point T1. Also, it may be seen that the first transaction ID TID1, the activated commit information CM_YES and the deactivated abort information AB_NO are included in the transaction information TRINFO<1> of the first write data 1st_WTDT<2> stored in the first spare region of the memory device150, which is generated and transmitted from the host102at the time point T3.

Accordingly, through the operation of checking the transaction information TRINFO<1:2> of the first write data 1st_WTDT<1:2> stored in the first spare region of the memory device150, data stored in the first normal region may be identified as the first write data 1st_WTDT<1:2>, and simultaneously, it may be seen that the first write data 1st_WTDT<1:2> are placed in the commit state.

To sum up, since the host102includes not only the transaction ID information which is the first transaction ID TID1but also the commit information and the abort information into the transaction information TRINFO<1:2> of the first write data 1st_WTDT<1:2>, and the memory system110stores the transaction information TRINFO<1:2> of the first write data 1st_WTDT<1:2> in the first spare region, it may be checked that the data stored in the first normal region are the first write data 1st_WTDT<1:2>. Simultaneously, it may be determined whether the first write data 1st_WTDT<1:2> are in the commit state or in the abort state, just through the operation of checking the first spare region.

It may be seen that not only the second transaction ID TID2as the transaction ID information but also the commit information and the abort information are included in the transaction information TRINFO<3:5> of the second write data 2nd_WTDT<1:3>.

Accordingly, it may be seen whether the second write data 2nd_WTDT<1:3> stored in the second normal region are in the commit state or in the abort state, through an operation of checking the transaction information TRINFO<3:5> of the second write data 2nd_WTDT<1:3> stored in the second spare region.

For example, it may be seen that the second transaction ID TID2, the deactivated commit information CM_NO and the deactivated abort information AB_NO are included in the transaction information TRINFO<3> of the second write data 2nd_WTDT<1> stored in the second spare region of the memory device150, which is generated and received from the host102at the time point T2. Also, it may be seen that the second transaction ID TID2, the deactivated commit information CM_NO and the deactivated abort information AB_NO are included in the transaction information TRINFO<4> of the second write data 2nd_WTDT<2> stored in the second spare region of the memory device150, which is generated and received from the host102at the time point T4. Also, it may be seen that the second transaction ID TID2, the activated commit information CM_YES and the deactivated abort information AB_NO are included in the transaction information TRINFO<5> of the second write data 2nd_WTDT<3> stored in the second spare region of the memory device150, which is generated and received from the host102at the time point T5.

Accordingly, through the operation of checking the transaction information TRINFO<3:5> of the second write data 2nd_WTDT<1:3> stored in the second spare region of the memory device150, data stored in the second normal region may be identified as the second write data 2nd_WTDT<1:3>. Simultaneously, it may be seen that the second write data 2nd_WTDT<1:3> are placed in the commit state.

To sum up, since the host102includes not only the transaction ID information which is the second transaction ID TID2but also the commit information and the abort information into the transaction information TRINFO<3:5> of the second write data 2nd_WTDT<1:3>, and the memory system110stores the transaction information TRINFO<3:5> of the second write data 2nd_WTDT<1:3> in the second spare region, it may be checked that the data stored in the second normal region are the second write data 2nd_WTDT<1:3>. Simultaneously, it may be determined whether the second write data 2nd_WTDT<1:3> are in the commit state or in the abort state, just through the operation of checking the second spare region.

Since the memory system110described with reference toFIG. 6Bmay determine whether or not the first write data 1st_WTDT<1:2> stored in the first normal region are in the commit state through the operation of checking the first spare region and determine whether or not the second write data 2nd_WTDT<1:3> stored in the second normal region are in the commit state through the operation of checking the second spare region, the host102, as described earlier with reference toFIG. 6A, may not need to generate and transmit the first commit command 1st_COMMIT and the second commit command 2nd_COMMIT for indicating that the transmission of first write data 1st_WTDT<1:2> is completed to the memory system110.

Referring again toFIG. 6C, it may be seen that not only the first transaction ID TID1as the transaction ID information but also the start information ST, the commit information CM and the abort information AB are included in the transaction information TRINFO<1:2> of the first write data 1st_WTDT<1:2>.

Accordingly, it may be seen whether or not start data of the transaction is included in the first write data 1st_WTDT<1:2> stored in the first normal region and simultaneously whether or not the first write data 1st_WTDT<1:2> are in the commit state or in the abort state, through an operation of checking the transaction information TRINFO<1:2> of the first write data 1st_WTDT<1:2> stored in the first spare region.

For example, it may be seen that the first transaction ID TID1, the activated start information ST_YES, the deactivated commit information CM_NO and the deactivated abort information AB_NO are included in the transaction information TRINFO<1> of the first write data 1st_WTDT<1> stored in the first spare region of the memory device150, which is generated and received from the host102at a time point T1. Also, it may be seen that the first transaction ID TID1, the deactivated start information ST_NO, the activated commit information CM_YES and the deactivated abort information AB_NO are included in the transaction information TRINFO<2> of the first write data 1st_WTDT<2> stored in the first spare region of the memory device150, which is generated and received from the host102at a time point T3.

Accordingly, through the operation of checking the transaction information TRINFO<1:2> of the first write data 1st_WTDT<1:2> stored in the first spare region of the memory device150, data stored in the first normal region may be identified as the first write data 1st_WTDT<1:2>. Simultaneously, it may be seen that the first write data 1st_WTDT<1> is the start data and the first write data 1st_WTDT<1:2> are placed in the commit state.

To sum up, the host102may include not only the transaction ID information which is the first transaction ID TID1but also the start information ST, the commit information CM and the abort information AB into the transaction information TRINFO<1:2> of the first write data 1st_WTDT<1:2>, and the memory system110may store the transaction information TRINFO<1:2> of the first write data 1st_WTDT<1:2> in the first spare region. Thus, it may be checked that the data stored in the first normal region are the first write data 1st_WTDT<1:2>, and it may be determined whether or not the start data of the transaction is included in the first write data 1st_WTDT<1:2>, and simultaneously whether the first write data 1st_WTDT<1:2> are in the commit state or in the abort state, just through the operation of checking the first spare region.

An advantage of the operation of checking whether or not the start data is included in the first write data 1st_WTDT<1:2> is that a start moment of the first transaction may be clearly distinguished. That is, if the start data of each transaction is clearly distinguished when a plurality of transactions are transmitted in a mixed state from the host102to the memory system110, an operation of distinguishing each of the plurality of transactions in the memory system110may be more simple.

In addition, it may be seen that not only the second transaction ID TID2as the transaction ID information but also the start information, the commit information and the abort information are included in the transaction information TRINFO<3:5> of the second write data 2nd_WTDT<1:3>.

Accordingly, it may be seen whether or not start data of the transaction is included in the second write data 2nd_WTDT<1:3> stored in the second normal region and simultaneously whether or not the second write data 2nd_WTDT<1:3> are in the commit state or in the abort state, through an operation of checking the transaction information TRINFO<3:5> of the second write data 2nd_WTDT<1:3> stored in the second spare region.

For example, it may be seen that the second transaction ID TID2, the activated start information ST_YES, the deactivated commit information CM_NO and the deactivated abort information AB_NO are included in the transaction information TRINFO<3> of the second write data 2nd_WTDT<1> stored in the second spare region of the memory device150, which is generated and received from the host102at a time point T2. Also, it may be seen that the second transaction ID TID2, the deactivated start information ST_NO, the activated commit information CM_YES and the deactivated abort information AB_NO are included in the transaction information TRINFO<4> of the second write data 2nd_WTDT<2> stored in the second spare region of the memory device150, which is generated and received from the host102at a time point T4. Besides, it may be seen that the second transaction ID TID2, the deactivated start information ST_NO, the activated commit information CM_YES and the deactivated abort information AB_NO are included in the transaction information TRINFO<5> of the second write data 2nd_WTDT<3> stored in the second spare region of the memory device150, which is generated and received from the host102at a time point T5.

Accordingly, through the operation of checking the transaction information TRINFO<3:5> of the second write data 2nd_WTDT<1:3> stored in the second spare region of the memory device150, data stored in the second normal region may be identified as the second write data 2nd_WTDT<1:3>. Simultaneously, it may be seen that the second write data 2nd_WTDT<1> is the start data and the second write data 2nd_WTDT<1:3> are placed in the commit state.

To sum up, the host102may include not only the transaction ID information which is the second transaction ID TID2but also the start information, the commit information and the abort information into the transaction information TRINFO<3:5> of the second write data 2nd_WTDT<1:3>, and the memory system110may store the transaction information TRINFO<3:5> of the second write data 2nd_WTDT<1:3> in the second spare region. Thus, it may be checked that the data stored in the second normal region are the second write data 2nd_WTDT<1:3>, and it may be determined whether or not the start data of the transaction is included in the second write data 2nd_WTDT<1:3>, and simultaneously whether the second write data 2nd_WTDT<1:3> are in the commit state or in the abort state, just through the operation of checking the second spare region.

An advantage of the operation of checking whether or not the start data is included in the second write data 2nd_WTDT<1:3> is that a start time point of the second transaction may be clearly distinguished. That is, if the start data of each transaction is clearly distinguished when a plurality of transactions are transmitted in a mixed state from the host102to the memory system110, an operation of distinguishing each of the plurality of transactions in the memory system110may be more simple.

Since the memory system110described with reference toFIG. 6Cmay determine whether or not the first write data 1st_WTDT<1:2> stored in the first normal region are in the commit state through the operation of checking the first spare region and determine whether or not the second write data 2nd_WTDT<1:3> stored in the second normal region are in the commit state through the operation of checking the second spare region, the host102, as described earlier with reference toFIG. 6A, may not need to generate and transmit the first commit command 1st_COMMIT and the second commit command 2nd_COMMIT for indicating that the transmission of first write data 1st_WTDT<1:2> is completed to the memory system110.

FIG. 8is a diagram illustrating an operation of rebuilding a plurality of write data grouped into transactions after sudden power-off (SPO) occurs in a data processing system shown inFIG. 5.

FIG. 8does not illustrate the normal regions N1, N2, N3and N4of the first memory block152of the memory device150of the memory system110included in the data processing system100shown inFIG. 5but illustrates just the spare regions S1, S2, S3and S4. In addition,FIG. 8shows that an operation of rebuilding the write data grouped into transactions after sudden power-off (SPO) occurs is included in the data processing system100.

Referring toFIG. 8, when rebuilding the write data WTDT<1:N+M> during a booting period where a power source is supplied again after the SPO occurs while the write data WTDT<1:N+M> are stored in the memory device150, the memory system110may read and check the transaction information TRINFO<1:N+M> of the write data WTDT<1:N+M> stored in the spare regions S1, S2, S3and S4of the memory device150.

As described above with reference toFIGS. 6B and 7A, it is assumed that the transaction ID information, the commit information and the abort information are included in the transaction information TRINFO<1:N+M> as a result of the check. When transaction information TR_INFO1<1:N> and TR_INFO2<1:M> including the activated commit information CM_YES are retrieved, the write data 1st_WTDT<1:N> and 2nd_WTDT<1:M> stored in the normal regions N1, N2, N3and N4, which correspond to the transaction information TR_INFO1<1:N> and TR_INFO2<1:M>, may be determined as a normal state and rebuilt.

As described above with reference toFIGS. 6B and 7A, it is assumed that the transaction ID information, the commit information and the abort information are included in the transaction information TRINFO<1:N+M> as the result of the check. When the transaction information TR_INFO1<1:N> and TR_INFO2<1:M> including the activated commit information CM_YES are not retrieved or the transaction information TR_INFO1<1:N> and TR_INFO2<1:M> including the activated abort information AB_YES are retrieved, the write data 1st_WTDT<1:N> and 2nd_WTDT<1:M> stored in the normal regions N1, N2, N3and N4, which correspond to the transaction information TR_INFO1<1:N> and TR_INFO2<1:M>, may be determined as an abnormal state and may not be rebuilt.

As described above with reference toFIGS. 6C and 7B, it is assumed that the transaction ID information, the start information, the commit information and the abort information are included in the transaction information TRINFO<1:N+M> as the result of the check. When the transaction information TR_INFO1<1:N> and TR_INFO2<1:M> including the activated commit information CM_YES and the transaction information TR_INFO1<1:N> and TR_INFO2<1:M> including the activated start information SY_YES are retrieved, the write data 1st_WTDT<1:N> and 2nd_WTDT<1:M> stored in the normal regions N1, N2, N3and N4, which correspond to the transaction information TR_INFO1<1:N> and TR_INFO2<1:M>, may be determined as a normal state and rebuilt.

As described above with reference toFIGS. 6C and 7B, it is assumed that the transaction ID information, the start information, the commit information and the abort information are included in the transaction information TRINFO<1:N+M> as the result of the check. When any one transaction information TR_INFO1<1:N> and TR_INFO2<1:M> of the transaction information TR_INFO1<1:N> and TR_INFO2<1:M> including the activated start information ST_YES and the transaction information TR_INFO1<1:N> and TR_INFO2<1:M> including the activated commit information CM_YES are not retrieved, the write data 1st_WTDT<1:N> and 2nd_WTDT<1:M> stored in the normal regions N1, N2, N3and N4, which correspond to the transaction information TR_INFO1<1:N> and TR_INFO2<1:M>, may be determined as an abnormal state and may not be rebuilt.

Referring again toFIG. 8in order to describe as an example, various pieces of transaction information T2, T2C, T1, T1, T2, T3, T2, T1C, T2, T3C may be stored in the spare regions S1, S2, S3and S4of the first memory block152of the memory device150.

“Tx” of the transaction information T2, T2C, T1, T1, T2, T3, T2, T1C, T2, T3C represents the transaction ID information. In other words, T2represents a second transaction ID, T1represents a first transaction ID, and T3represents a third transaction ID. “C” following “Tx” represents that the commit information is included in the transaction information on “Tx” in an activated state (CM_YES). Although not directly illustrated, “A” instead of “C” may be followed by “Tx”, which represents that the abort information is included in the transaction information on “Tx” in an activated state (AB_YES). Accordingly, a case where both “C” and “A” are not followed by “Tx” represents that the commit information and the abort information are included in the transaction information on “Tx” in a deactivated state (CM_NO, AB_NO).

Specifically, “T2” may be stored in the first spare section S1of the first page P10of the first memory block152of the memory device150, “T2C” may be stored in the second spare section S2, “T1” may be stored in the third spare section S3, and “T1” may be stored in the fourth spare section S4.

Also, “T2” may be stored in the first spare section S1of the second page P11of the first memory block152of the memory device150, “T3” may be stored in the second spare section S2, “T2” may be stored in the third spare section S3, and “T1C” may be stored in the fourth spare section S4.

Also, “T2” may be stored in the first spare section S1of the third page P12of the first memory block152of the memory device150, “T3C” may be stored in the second spare section S2, and it may be assumed that the SPO occurs in a process of storing the transaction information in the third spare section S3.

The memory system110may sequentially read and check the spare regions S1, S2, S3and S4of the first memory block152of the memory device150during a rebuilding operation after the SPO occurs.

According to a read order of the spare regions S1, S2, S3and S4of the first memory block152, the memory system110may sequentially check the transaction information “T2, T2C, T1, T1” stored in the spare regions S1, S2, S3and S4of the first page P10. Subsequently, the memory system110may sequentially check the transaction information “T2, T3, T2, T1C” stored in the spare regions S1, S2, S3and S4of the second page P11. Subsequently, the memory system110may sequentially check the transaction information “T2, T3C” stored until the SPO occurs in the spare regions S1, S2, S3and S4of the third page P12.

The memory system110may identify the transaction information “T2” and “T2C” stored respectively in the first spare section S1and second spare section S2of the first page P10as the transaction information corresponding to the second transaction in order. Since both of “T2” and “T2C” exist, the memory system110may determine that the activated commit information CM_YES is retrieved for the second transaction. Therefore, the memory system110may determine that all data (not illustrated) grouped into the second transaction, which are stored in the first normal section N1and second normal section N2of the first page P10corresponding to the first spare section S1and second spare section S2of the first page P10, respectively, are in the normal state, and may rebuild the data.

Subsequently, the memory system110may identify the transaction information “T1”, “T1” and “T1C” stored respectively in the third spare section S3and fourth spare section S4of the first page P10and in the fourth spare section S4of the second page P11as the transaction information corresponding to the first transaction in order. Since both of “T1” and “T1C” exist, the memory system110may determine that the activated commit information CM_YES is retrieved for the first transaction. Therefore, the memory system110may determine that all data (not illustrated) grouped into the first transaction, which are stored in the third normal section N3and fourth normal section N4of the first page P10and in the fourth normal section N4of the second page P11corresponding to the third spare section S3and fourth spare section S4of the first page P10and the fourth spare section S4of the second page P11, are in the normal state, and may rebuild the data.

Subsequently, the memory system110may identify the transaction information “T3” and “T3C” stored respectively in the second spare section S2of the second page P11and in the second spare section S2of the third page P12as the transaction information corresponding to the third transaction in order. Since both of “T3” and “T3C” exist, the memory system110may determine that the activated commit information CM_YES is retrieved for the third transaction. Therefore, the memory system110may determine that all data (not illustrated) grouped into the third transaction, which are stored in the second normal section N2of the second page P11and the second normal section N2of the third page P12corresponding to the second spare section S2of the second page P11and the second spare section S2of the third page P12, are in the normal state, and may rebuild the data.

Subsequently, the memory system110may identify the transaction information “T2”, “T2” and “T2” stored respectively in the first spare section S1and third spare section S3of the second page P11and in the first spare section S1of the third page P12as the transaction information corresponding to the second transaction. Since only “T2” exists, and “T2C” does not exist, the memory system110may determine that the activated commit information CM_YES is not retrieved for the second transaction. Therefore, the memory system110may determine that all data (not illustrated) grouped into the second transaction, which are stored in the first normal section N1and third normal section N3of the second page P11and in the first normal section N1of the third page P12corresponding to the first spare section S1and third spare section S3of the second page P11and in the first spare section S1of the third page P12, are in the abnormal state, and may not rebuild the data.

FIGS. 9 to 17are diagrams schematically illustrating application examples of the data processing system ofFIGS. 1 to 8according to various embodiments.

FIG. 9is a diagram schematically illustrating an example of the data processing system including the memory system in accordance with an embodiment.FIG. 9schematically illustrates a memory card system to which the memory system in accordance with an embodiment is applied.

Referring toFIG. 9, the memory card system6100may include a memory controller6120, a memory device6130and a connector6110.

More specifically, the memory controller6120may be connected to the memory device6130embodied by a nonvolatile memory, and configured to access the memory device6130. For example, the memory controller6120may be configured to control read, write, erase and background operations of the memory device6130. The memory controller6120may be configured to provide an interface between the memory device6130and a host, and drive firmware for controlling the memory device6130. That is, the memory controller6120may correspond to the controller130of the memory system110described with reference toFIGS. 1 to 8, and the memory device6130may correspond to the memory device150of the memory system110described with reference toFIGS. 1 to 8.

Thus, the memory controller6120may include a RAM, a processing unit, a host interface, a memory interface and an error correction unit. The memory controller130may further include the elements described inFIG. 1.

The memory controller6120may communicate with an external device, for example, the host102ofFIG. 1through the connector6110. For example, as described with reference toFIG. 1, the memory controller6120may be configured to communicate with an external device through one or more of various communication protocols such as universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI express (PCIe), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, small computer system interface (SCSI), enhanced small disk interface (EDSI), Integrated Drive Electronics (IDE), Firewire, universal flash storage (UFS), WIFI and Bluetooth. Thus, the memory system and the data processing system in accordance with an embodiment may be applied to wired/wireless electronic devices or particularly mobile electronic devices.

The memory device6130may be implemented by a nonvolatile memory. For example, the memory device6130may be implemented by various nonvolatile memory devices such as an erasable and programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM) and a spin torque transfer magnetic RAM (STT-RAM). The memory device6130may include a plurality of dies as in the memory device150ofFIG. 1.

The memory controller6120and the memory device6130may be integrated into a single semiconductor device. For example, the memory controller6120and the memory device6130may construct a solid state driver (SSD) by being integrated into a single semiconductor device. Also, the memory controller6120and the memory device6130may construct a memory card such as a PC card (PCMCIA: Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media card (e.g., SM and SMC), a memory stick, a multimedia card (e.g., MMC, RS-MMC, MMCmicro and eMMC), an SD card (e.g., SD, miniSD, microSD and SDHC) and a universal flash storage (UFS).

FIG. 10is a diagram schematically illustrating another example of the data processing system including a memory system, in accordance with an embodiment.

Referring toFIG. 10, the data processing system6200may include a memory device6230having one or more nonvolatile memories and a memory controller6220for controlling the memory device6230. The data processing system6200illustrated inFIG. 10may serve as a storage medium such as a memory card (CF, SD, micro-SD or the like) or USB device, as described with reference toFIG. 1. The memory device6230may correspond to the memory device150in the memory system110described inFIGS. 1 to 8, and the memory controller6220may correspond to the controller130in the memory system110described inFIGS. 1 to 8.

The memory controller6220may control a read, write, or erase operation on the memory device6230in response to a request of the host6210, and the memory controller6220may include one or more CPUs6221, a buffer memory such as RAM6222, an ECC circuit6223, a host interface6224and a memory interface such as an NVM interface6225.

The CPU6221may control the operations for the memory device6230, for example, read, write, file system management and bad page management operations. The RAM6222may be operated according to control of the CPU6221, and used as a work memory, buffer memory or cache memory. When the RAM6222is used as a work memory, data processed by the CPU6221may be temporarily stored in the RAM6222. When the RAM6222is used as a buffer memory, the RAM6222may be used for buffering data transmitted to the memory device6230from the host6210or transmitted to the host6210from the memory device6230. When the RAM6222is used as a cache memory, the RAM6222may assist the low-speed memory device6230to operate at high speed.

The ECC circuit6223may correspond to the ECC unit138of the controller130illustrated inFIG. 1. As described with reference toFIG. 1, the ECC circuit6223may generate an ECC (Error Correction Code) for correcting a fail bit or error bit of data provided from the memory device6230. The ECC circuit6223may perform error correction encoding on data provided to the memory device6230, thereby forming data with a parity bit. The parity bit may be stored in the memory device6230. The ECC circuit6223may perform error correction decoding on data outputted from the memory device6230. In this case, the ECC circuit6223may correct an error using the parity bit. For example, as described with reference toFIG. 1, the ECC circuit6223may correct an error using the LDPC code, BCH code, turbo code, Reed-Solomon code, convolution code, RSC or coded modulation such as TCM or BCM.

The memory controller6220may transmit/receive data to/from the host6210through the host interface6224, and transmit/receive data to/from the memory device6230through the NVM interface6225. The host interface6224may be connected to the host6210through a PATA bus, SATA bus, SCSI, USB, PCIe, or NAND interface. The memory controller6220may have a wireless communication function with a mobile communication protocol such as WiFi or Long Term Evolution (LTE). The memory controller6220may be connected to an external device, for example, the host6210or another external device, and then transmit/receive data to/from the external device. In particular, as the memory controller6220is configured to communicate with the external device through one or more of various communication protocols, the memory system and the data processing system in accordance with an embodiment may be applied to wired/wireless electronic devices or particularly a mobile electronic device.

FIG. 11is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with an embodiment.FIG. 11schematically illustrates an SSD to which the memory system in accordance with an embodiment is applied.

Referring toFIG. 11, the SSD6300may include a controller6320and a memory device6340including a plurality of nonvolatile memories. The controller6320may correspond to the controller130in the memory system110ofFIG. 1, and the memory device6340may correspond to the memory device150in the memory system ofFIG. 1.

More specifically, the controller6320may be connected to the memory device6340through a plurality of channels CH1to CHi. The controller6320may include one or more processors6321, a buffer memory6325, an ECC circuit6322, a host interface6324and a memory interface, for example, a nonvolatile memory interface6326.

The buffer memory6325may temporarily store data provided from the host6310or data provided from a plurality of flash memories NVM included in the memory device6340, or temporarily store meta data of the plurality of flash memories NVM, for example, map data including a mapping table. The buffer memory6325may be embodied by volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM and GRAM or nonvolatile memories such as FRAM, ReRAM, STT-MRAM and PRAM. For convenience of description,FIG. 11illustrates that the buffer memory6325exists in the controller6320. However, the buffer memory6325may exist outside the controller6320.

The ECC circuit6322may calculate an ECC value of data to be programmed to the memory device6340during a program operation, perform an error correction operation on data read from the memory device6340based on the ECC value during a read operation, and perform an error correction operation on data recovered from the memory device6340during a failed data recovery operation.

The host interface6324may provide an interface function with an external device, for example, the host6310, and the nonvolatile memory interface6326may provide an interface function with the memory device6340connected through the plurality of channels.

Furthermore, a plurality of SSDs6300to which the memory system110ofFIG. 1is applied may be provided to embody a data processing system, for example, RAID (Redundant Array of Independent Disks) system. In this case, the RAID system may include the plurality of SSDs6300and a RAID controller for controlling the plurality of SSDs6300. When the RAID controller performs a program operation in response to a write command provided from the host6310, the RAID controller may select one or more memory systems or SSDs6300according to a plurality of RAID levels, that is, RAID level information of the write command provided from the host6310in the SSDs6300, and output data corresponding to the write command to the selected SSDs6300. Furthermore, when the RAID controller performs a read command in response to a read command provided from the host6310, the RAID controller may select one or more memory systems or SSDs6300according to a plurality of RAID levels, that is, RAID level information of the read command provided from the host6310in the SSDs6300, and provide data read from the selected SSDs6300to the host6310.

FIG. 12is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with an embodiment.FIG. 12schematically illustrates an embedded Multi-Media Card (eMMC) to which the memory system in accordance with an embodiment is applied.

Referring toFIG. 12, the eMMC6400may include a controller6430and a memory device6440embodied by one or more NAND flash memories. The controller6430may correspond to the controller130in the memory system110ofFIG. 1, and the memory device6440may correspond to the memory device150in the memory system110ofFIG. 1.

More specifically, the controller6430may be connected to the memory device6440through a plurality of channels. The controller6430may include one or more cores6432, a host interface6431and a memory interface, for example, a NAND interface6433.

The core6432may control the operations of the eMMC6400, the host interface6431may provide an interface function between the controller6430and the host6410, and the NAND interface6433may provide an interface function between the memory device6440and the controller6430. For example, the host interface6431may serve as a parallel interface, for example, MMC interface as described with reference toFIG. 1. Furthermore, the host interface6431may serve as a serial interface, for example, UHS ((Ultra High Speed)-I/UHS-II) interface.

FIGS. 13 to 16are diagrams schematically illustrating other examples of the data processing system including the memory system in accordance with an embodiment.FIGS. 13 to 16schematically illustrate UFS (Universal Flash Storage) systems to which the memory system in accordance with an embodiment is applied.

Referring toFIGS. 13 to 16, the UFS systems6500,6600,6700and6800may include hosts6510,6610,6710and6810, UFS devices6520,6620,6720and6820and UFS cards6530,6630,6730and6830, respectively. The hosts6510,6610,6710and6810may serve as application processors of wired/wireless electronic devices or particularly mobile electronic devices, the UFS devices6520,6620,6720and6820may serve as embedded UFS devices, and the UFS cards6530,6630,6730and6830may serve as external embedded UFS devices or removable UFS cards.

The hosts6510,6610,6710and6810, the UFS devices6520,6620,6720and6820and the UFS cards6530,6630,6730and6830in the respective UFS systems6500,6600,6700and6800may communicate with external devices, for example, wired/wireless electronic devices or particularly mobile electronic devices through UFS protocols, and the UFS devices6520,6620,6720and6820and the UFS cards6530,6630,6730and6830may be embodied by the memory system110illustrated inFIG. 1. For example, in the UFS systems6500,6600,6700and6800, the UFS devices6520,6620,6720and6820may be embodied in the form of the data processing system6200, the SSD6300or the eMMC6400described with reference toFIGS. 10 to 12, and the UFS cards6530,6630,6730and6830may be embodied in the form of the memory card system6100described with reference toFIG. 9.

Furthermore, in the UFS systems6500,6600,6700and6800, the hosts6510,6610,6710and6810, the UFS devices6520,6620,6720and6820and the UFS cards6530,6630,6730and6830may communicate with each other through an UFS interface, for example, MIPI M-PHY and MIPI UniPro (Unified Protocol) in MIPI (Mobile Industry Processor Interface). Furthermore, the UFS devices6520,6620,6720and6820and the UFS cards6530,6630,6730and6830may communicate with each other through various protocols other than the UFS protocol, for example, UFDs, MMC, SD, mini-SD, and micro-SD.

FIG. 17is a diagram schematically illustrating another example of the data processing system including the memory system in accordance with an embodiment.FIG. 17is a diagram schematically illustrating a user system to which the memory system in accordance with an embodiment is applied.

Referring toFIG. 17, the user system6900may include an application processor6930, a memory module6920, a network module6940, a storage module6950and a user interface6910.

More specifically, the application processor6930may drive components included in the user system6900, for example, an OS, and include controllers, interfaces and a graphic engine which control the components included in the user system6900. The application processor6930may be provided as a System-on-Chip (SoC).

The memory module6920may be used as a main memory, work memory, buffer memory or cache memory of the user system6900. The memory module6920may include a volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR3 SDRAM or LPDDR3 SDRAM or a nonvolatile RAM such as PRAM, ReRAM, MRAM or FRAM. For example, the application processor6930and the memory module6920may be packaged and mounted, based on POP (Package on Package).

The network module6940may communicate with external devices. For example, the network module6940may not only support wired communication, but may also support various wireless communication protocols such as code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution (LTE), worldwide interoperability for microwave access (Wimax), wireless local area network (WLAN), ultra-wideband (UWB), Bluetooth, wireless display (WI-DI), thereby communicating with wired/wireless electronic devices or particularly mobile electronic devices. Therefore, the memory system and the data processing system, in accordance with an embodiment of the present invention, can be applied to wired/wireless electronic devices. The network module6940may be included in the application processor6930.

The storage module6950may store data, for example, data received from the application processor6930, and then may transmit the stored data to the application processor6930. The storage module6950may be embodied by a nonvolatile semiconductor memory device such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (ReRAM), a NAND flash, NOR flash and 3D NAND flash, and provided as a removable storage medium such as a memory card or external drive of the user system6900. The storage module6950may correspond to the memory system110described with reference toFIG. 1. Furthermore, the storage module6950may be embodied as an SSD, eMMC and UFS as described above with reference toFIGS. 11 to 16.

Furthermore, when the memory system110ofFIG. 1is applied to a mobile electronic device of the user system6900, the application processor6930may control the operations of the mobile electronic device, and the network module6940may serve as a communication module for controlling wired/wireless communication with an external device. The user interface6910may display data processed by the processor6930on a display/touch module of the mobile electronic device, or support a function of receiving data from the touch panel.