Semiconductor package

A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. nonprovisional application claims priority under 35 U.S.C § 119 to Korean Patent Application No. 10-2020-0098717 filed on Aug. 6, 2020 in the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND

The present inventive concepts relate to a semiconductor package.

A semiconductor package is provided to implement an integrated circuit chip to qualify for use in electronic products. A semiconductor package is typically configured such that a semiconductor chip is mounted on a printed circuit board (PCB) and bonding wires or bumps are used to electrically connect the semiconductor chip to the printed circuit board. With the development of electronic industry, many studies have been conducted to improve reliability and durability of semiconductor packages.

SUMMARY

Some example embodiments of the present inventive concepts provide a semiconductor package with improved performance.

Some example embodiments of the present inventive concepts provide a wiring structure capable of providing enhanced thermal radiation.

An object of the present inventive concepts is not limited to the mentioned above, and other objects which have not been mentioned above will be clearly understood to those skilled in the art from the following description.

According to an embodiment of the present inventive concept, a semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device that are stacked on each other so that the interposer is configured to connect the first sub-semiconductor device and the second sub-semiconductor device with each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip that is stacked on the first substrate. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and a plurality of thermal conductive vias that penetrate the dielectric layer and connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer of the interposer without overlapping the first thermal conductive pad of the interposer. The heat sink further covers the first thermal conductive pad of the interposer to be connected thereto.

According to an example embodiment of the present inventive concept, a semiconductor package includes a first sub-semiconductor device, an interposer on the first sub-semiconductor device, a first thermal interface material layer between the first sub-semiconductor device and the interposer, a second sub-semiconductor device on the interposer, the second sub-semiconductor device exposing a portion of the interposer, a heat sink that covers a top surface of the second sub-semiconductor device, a sidewall of the second sub-semiconductor device and the portion of the interposer, and a second thermal interface material layer between the heat sink and the portion of the interposer. The first sub-semiconductor device includes a first substrate and a first semiconductor chip that is stacked on the first substrate. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a thermal conductive pad in contact with a top surface of the dielectric layer, and a plurality of thermal conductive vias that penetrate the dielectric layer and connect the thermal conductive layer to the thermal conductive pad. The second sub-semiconductor device exposes the thermal conductive pad of the interposer. The first thermal interface material layer is in contact with a bottom surface of the thermal conductive layer and a top surface of the first semiconductor chip. The second thermal interface material layer is in contact with a top surface of the thermal conductive pad and the bottommost surface of the heat sink. The thermal conductive pad has a width having a value from about 500 μm to about 7,000 μm.

According to an embodiment of the present inventive concept, a semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device that are stacked on each other so that the interposer is configured to connect the first sub-semiconductor device and the second sub-semiconductor device with each other. The interposer includes a dielectric layer, a thermal conductive layer and a plurality of lower conductive patterns that are in contact with a bottom surface of the dielectric layer and are spaced apart from each other, a bottom surface of the thermal conductive layer being adjacent to and connected to a top surface of the first sub-semiconductor device, a thermal conductive pad and a plurality of upper conductive patterns that are in contact with a top surface of the dielectric layer and are spaced apart from each other, a plurality of thermal conductive vias that penetrate the dielectric layer and connect the thermal conductive layer to the thermal conductive pad, and a plurality of circuit vias that penetrate the dielectric layer. Each of the plurality of circuit vias connects a corresponding one of the plurality of upper conductive patterns to a corresponding one of the plurality of lower conductive patterns. The second sub-semiconductor device is disposed on the dielectric layer of the interposer without overlapping the thermal conductive pad of the interposer. A first width, in a first direction parallel to the bottom surface of the dielectric layer, of each of the plurality of thermal conductive vias is greater than a second width, in the first direction, of each of the plurality of circuit vias.

According to an embodiment of the present inventive concept, an interposer includes a dielectric layer, a thermal conductive layer and a plurality of lower conductive patterns that are in contact with a bottom surface of the dielectric layer and are spaced apart from each other, a thermal conductive pad and a plurality of upper conductive patterns that are in contact with a top surface of the dielectric layer and are spaced apart from each other, a plurality of thermal conductive vias that penetrate the dielectric layer and connect the thermal conductive layer to the thermal conductive pad, and a plurality of circuit vias that penetrate the dielectric layer. Each of the plurality of circuit vias connects a corresponding one of the plurality of upper conductive patterns to a corresponding one of the plurality of lower conductive patterns. A first width, in a first direction parallel to the bottom surface of the dielectric layer, of each of the plurality of thermal conductive vias is greater than a second width, in the first direction, of each of the plurality of circuit vias.

DETAILED DESCRIPTION OF EMBODIMENTS

Some example embodiments of the present inventive concepts will now be described in detail with reference to the accompanying drawings to aid in clearly explaining the present inventive concepts.

FIG.1illustrates a plan view showing a semiconductor package according to some example embodiments of the present inventive concepts.FIG.2illustrates a cross-sectional view taken along line IA-IA′ ofFIG.1.

Referring toFIGS.1and2, a semiconductor package1000according to some example embodiments may include a first sub-semiconductor package500(i.e., a first sub-semiconductor device), a wiring structure600(i.e., an interposer), a second sub-semiconductor package700(i.e., a second sub-semiconductor device), and a thermal radiation member HS (i.e., a heat sink) that are sequentially stacked on each other. The first sub-semiconductor package500and the wiring structure600may have the same width in a first direction X. The first sub-semiconductor package500and the wiring structure600may have their sidewalls that are aligned with each other. The second sub-semiconductor package700may have a width less than that of the wiring structure600in the first direction X. The second sub-semiconductor package700may have a first sidewall SW1aligned with a first sidewall SW2of the wiring structure600. The second sub-semiconductor package700may have a second sidewall SW3spaced apart from a second sidewall SW4of the wiring structure600. The second sub-semiconductor package700may expose a portion of the wiring structure600. The first sidewall SW1of the second sub-semiconductor package700and the second sidewall SW3thereof may be opposite to each other in the first direction X. The first sidewall SW2of the wiring structure600and the second sidewall SW4thereof may be opposite to each other in the first direction X. Terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise. For example, items described as “substantially the same,” “substantially equal,” or “substantially planar,” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations that may occur, for example, due to manufacturing processes.

The thermal radiation member HS may include or may be formed of a material, such as metal (such as aluminum and copper) or graphene, whose thermal conductivity is high such that the thermal radiation member HS may serve as a heat sink of the semiconductor package1000. The thermal radiation member HS may include a first thermal radiation part HS1(i.e., a first heat sink part) that overlaps the second sub-semiconductor package700and a second thermal radiation part HS2(i.e., a second heat sink part) that extends toward the wiring structure600from a sidewall of the first thermal radiation part HS1. The first and second thermal radiation parts HS1and HS2may be integrally united with each other, and no boundary may be present therebetween. The second thermal radiation part HS2may be thicker than the first thermal radiation part HS1. In the present embodiment, the second thermal radiation part HS2may have an “L” shape when the semiconductor package1000is viewed in a plan view, as shown inFIG.1. The second thermal radiation part HS2may have a first width W1in the first direction X. The first width W1may have a value, for example, from about 500 μm to about 7,000 μm. Terms such as “about” or “approximately” may reflect amounts, sizes, orientations, or layouts that vary only in a small relative manner, and/or in a way that does not significantly alter the operation, functionality, or structure of certain elements. For example, a range from “about 0.1 to about 1” may encompass a range such as a 0%-5% deviation around 0.1 and a 0% to 5% deviation around 1, especially if such deviation maintains the same effect as the listed range.

The first sub-semiconductor package500may include a first substrate S1, a first semiconductor apparatus CH1(i.e., a first semiconductor chip) mounted on the first substrate S1, and a first mold layer MD1that covers a sidewall of the first semiconductor apparatus CH1. The first substrate S1may have a first thickness TH1. The wiring structure600may have a second thickness TH2. The second thickness TH2may be less than the first thickness TH1. The first substrate S1may be, for example, a multi-layered printed circuit board. The first substrate S1may include a first body layer C1, a second body layer C2, and a third body layer C3. Each of the first, second, and third body layers C1, C2, and C3may include or may be formed of a dielectric material. For example, each of the first, second, and third body layers C1, C2, and C3may be formed of a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which a thermosetting or thermoplastic resin is impregnated with (or mixed with) a reinforcement element which is formed of, for example, glass fiber and/or inorganic filler. In an embodiment, the resin mixed with the reinforcement element may include a prepreg, a fire resist-4 (FR4), or a photosensitive resin, but the present inventive concepts are not limited thereto.

The second body layer C2may be positioned above the first body layer C1, and the third body layer C3may be positioned below the first body layer C1. The first body layer C1may include first internal lines14on a top surface thereof, and may also include second internal lines12on a bottom surface thereof. First upper conductive patterns16may be disposed on the second body layer C2, and first lower conductive patterns18may be disposed on a bottom surface of the third body layer C3. A first upper passivation layer PS1may be disposed on the second body layer C2, and the first upper conductive patterns16may be exposed on the second body layer C2. A first lower passivation layer PS2may be disposed below the third body layer C3, and the first lower conductive patterns18may be exposed below the third body layer C3. First circuit vias10may be disposed in the first, second, and third body layers C1, C2, and C3, and the first and second internal lines14and12and the first upper and lower conductive patterns16and18may be electrically connected to each other through the first circuit vias10. The first upper and lower passivation layers PS1 and PS2may be a photosensitive solder resist (PSR) layer. External connection terminals300may be bonded to the first lower conductive patterns18. The external connection terminals300may include or may be formed of one or more of solder balls, conductive bumps, and conductive pillars. The external connection terminals300may include or may be formed of one or more of tin, lead, aluminum, gold, and nickel.

The first semiconductor apparatus CH1(i.e., a semiconductor chip) may be a single semiconductor die, or a semiconductor package that includes a single semiconductor die, or a plurality of semiconductor dies of the same type or different types. As used herein, the semiconductor device may refer, for example, to a device such as a semiconductor chip (e.g., memory chip and/or logic chip formed on a die), a stack of semiconductor chips, a semiconductor package including one or more semiconductor chips stacked on a package substrate, or a package-on-package device including a plurality of packages. These devices may be formed using ball grid arrays, wire bonding, through substrate vias, or other electrical connection elements, and may include memory devices such as volatile or non-volatile memory devices. Semiconductor packages may include at least one semiconductor chip, a redistribution layer which allows the input/output pads of an integrated circuit in other locations of the semiconductor chip, a package substrate, or an encapsulant formed on the package substrate and covering the semiconductor chip. The semiconductor device may be one selected from an image sensor chip such as CMOS image sensor (CIS), a microelectromechanical system (MEMS) device chip, an application specific integrated circuit (ASIC) chip, and a memory device chip such as Flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, ReRAM, HBM (high bandwidth memory), and HMC (hybrid memory cubic). The first semiconductor apparatus CH1may be flip-chip bonded through first internal connection members310to the first upper conductive patterns16of the first substrate S1. The first internal connection members310may include or may be formed of one or more of solder balls, conductive bumps, and conductive pillars. A first under-fill layer UF1may be interposed between the first semiconductor apparatus CH1and the first substrate S1. The first under-fill layer UF1may include or may be formed of a thermo-curable resin or a photo-curable resin. The first under-fill layer UF1may further include an organic filler or an inorganic filler.

The first mold layer MD1may cover the sidewall of the first semiconductor apparatus CH1and a top surface of the first substrate S1. The first mold layer MD1may include or may be formed of a dielectric resin, for example, an epoxy molding compound (EMC). The first mold layer MD1may further include fillers, and the fillers may be dispersed in the dielectric resin.

FIG.3Aillustrates a plan view showing a wiring structure according to some example embodiments of the present inventive concepts.FIG.3Billustrates a cross-sectional view taken along line IA-IA′ ofFIG.3A.

Referring toFIGS.1,2,3A, and3B, the wiring structure600may be a double-sided printed circuit board. For example, the wiring structure600may include a fourth body layer C4, second upper conductive patterns34on a top surface of the fourth body layer C4, and second lower conductive patterns32on a bottom surface of the fourth body layer C4. Second circuit vias30may penetrate the fourth body layer C4, and may electrically connect the second upper conductive patterns34to the second lower conductive patterns32. The fourth body layer C4may include or may be formed of, for example, a material which is the same as or similar to that of the first body layer C1. Alternatively, the fourth body layer C4may include or may be formed of silicon. In the present embodiment, the wiring structure600may be an interposer which is an electrical interface for spreading a connection to a wider pitch or for rerouting a connection to a different connection. In an embodiment, the wiring structure600may be a printed circuit board (PCB) interposer, and the body layer of the wiring structure600may be formed of a dielectric layer. The present invention is not limited thereto. For example, the wiring structure600may be a silicon interposer of which a body layer is formed of silicon.

The wiring structure600may further include a thermal conductive layer TL disposed on the bottom surface of the fourth body layer C4, a thermal conductive pad TP disposed on the top surface of the fourth body layer C4, and a thermal conductive via VT that penetrates the fourth body layer C4and connects the thermal conductive layer TL to the thermal conductive pad TP. A second upper passivation layer PS3may be disposed on the fourth body layer C4, exposing the thermal conductive pad TP and the second upper conductive patterns34which are disposed on the top surface of the fourth body layer C4. A second lower passivation layer PS4may be disposed on the bottom surface of the fourth body layer C4, exposing the thermal conductive layer TL and the second lower conductive patterns32which are disposed on the bottom surface of the fourth body layer C4. The second upper and lower passivation layers PS3and PS4may include or may be formed of the same material as that of the first upper and lower passivation layers PS1and PS2. The thermal conductive pad TP, the thermal conductive via VT, and the thermal conductive layer TL may constitute a thermal conductive structure through which heat generated from the first semiconductor apparatus CH1may be transferred to the thermal radiation member HS (i.e., a heat sink). With the thermal conductive structure and the thermal radiation member HS, heat generated from the first semiconductor apparatus CH1may be dissipated away to a fluid medium such as air or a liquid coolant, thereby allowing regulation of the temperature of the first semiconductor apparatus CH1.

The thermal conductive layer TL may vertically overlap the thermal conductive pad TP. The thermal conductive pad TP and the second thermal radiation part HS2may have their planar shapes that are the same as each other and vertically overlap each other. When the wiring structure600is viewed in a plan view, the thermal conductive pad TP may have an “L” shape. The thermal conductive pad TP may have a second width W2in the first direction X. The second width W2may have a value, for example, from about 500 μm to about 7,000 μm. When the wiring structure600is viewed in a plan view, the thermal conductive layer TL may have a flat rectangular shape.

The thermal conductive layer TL and the second lower conductive patterns32may be the same in terms of thickness and material (e.g., metal such as copper). The thermal conductive pad TP and the second upper conductive patterns34may be the same in terms of thickness and material (e.g., metal such as copper). The thermal conductive via VT and the second circuit vias30may be the same in terms of thickness and material (e.g., metal such as copper). Alternatively, the thermal conductive layer TL, the thermal conductive pad TP, and the thermal conductive via VT may have different material and thickness (e.g., greater thickness) from those of the second lower conductive patterns32, the second upper conductive patterns34, and the second circuit vias30, respectively. The thermal conductive layer TL, the thermal conductive pad TP, and the thermal conductive via VT may include or may be formed of a material (e.g., metal or graphene) whose thermal conductivity is greater than that of the second lower conductive patterns32, the second upper conductive patterns34, and the second circuit vias30, respectively. In an embodiment, when the semiconductor package1000is viewed in a plan view, an area of the thermal conductive layer TL may be greater than or the same as that of the first semiconductor apparatus CH1. For example, a width, in the first direction X, of the thermal conductive layer TL may be greater than or the same as that of the first semiconductor apparatus CH1, and a width, in the second direction Y, of the thermal conductive layer TL may be greater than or the same as that of the first semiconductor apparatus CH1. As the overlapping area between the thermal conductive layer TL and the first semiconductor apparatus CH1increases, heat generated from the first semiconductor apparatus CH1may be transferred to the thermal radiation member HS more efficiently.

FIGS.4A and4Billustrate enlarged views showing section P1ofFIG.2.FIG.4Cillustrates an enlarged view showing section P2ofFIG.2.

Referring toFIGS.4A and4C, the thermal conductive via VT may have a third width W3in the first direction X. The second circuit via30may have a fourth width W4in the first direction X. The third width W3may be greater than the fourth width W4. The third width W3may have a value from about 100 μm to about 250 μm, for example, the fourth width W4may have a value from about 1 μm to about 70 μm. The relatively large width of the thermal conductive via VT may facilitate thermal transfer from the thermal conductive layer TL to the thermal conductive pad TP. The present inventive concept is not limited thereto. For example, the third width W3of the thermal conductive via VT may be the same as the fourth width W4of the second circuit via30. When heat transfer from the thermal conductive layer TL to the thermal conductive pad TP is secured, the thermal conductive via VT and the second circuit via30may have the same width as each other. Such heat transfer may also be secured by increasing the number of the thermal conductive via VT.

Referring toFIGS.2,4A, and4B, a first thermal interface material layer550may be interposed between the wiring structure600and the first sub-semiconductor package500. The first thermal interface material layer550has a thickness having a value from 5 μm to 40 μm. The first thermal interface material layer550may be in contact with a bottom surface of the thermal conductive layer TL and a top surface of the first semiconductor apparatus CH1. The first thermal interface material layer550may include or may be formed of a grease layer or a thermo-curable resin layer. The first thermal interface material layer550may further include filler particles dispersed in the thermo-curable resin layer. The filler particles may include or may be formed of a graphene power or a metal power whose thermal conductivity is high. Alternatively, the filler particles may include or may be formed of one or more of silica, alumina, zinc oxide, and boron nitride. The first thermal interface material layer550may have a bottom surface lower than a top surface of the first mold layer MD1. The first mold layer MD1may cover a sidewall of the first thermal interface material layer550. The first thermal interface material layer550may penetrate the second lower passivation layer PS4and may contact the thermal conductive layer TL. As shown inFIG.4A, the sidewall of the first thermal interface material layer550may be aligned with that of the first semiconductor apparatus CH1. Alternatively, a portion of the first thermal interface material layer550may protrude toward the first mold layer MD1. Therefore, the first mold layer MD1may have a partially recessed region RC1on an upper sidewall thereof. It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact.

Second internal connection members20may penetrate the first mold layer MD1and may electrically connect the wiring structure600to the first substrate S1of the first sub-semiconductor package500. The second internal connection members20may connect the first upper conductive patterns16to the second lower conductive patterns32. The second internal connection members20may be one or more of solder balls, conductive bumps, and conductive pillars.

Referring toFIG.2, a second thermal interface material layer650may be interposed between the second thermal radiation part HS2and the wiring structure600. The second thermal interface material layer650may include or may be formed of a material which is the same as or similar to that of the first thermal interface material layer550. The second thermal interface material layer650may penetrate the second upper passivation layer PS3and may contact the thermal conductive pad TP.

Referring still toFIG.2, the second sub-semiconductor package700may include a second substrate S2, a plurality of second semiconductor chips CH2stacked on the second substrate S2, and a second mold layer MD2that covers the second semiconductor chips CH2. The second substrate S2may be a double-sided or multi-layered printed circuit board. The second substrate S2may include a fifth body layer C5, third upper conductive patterns54disposed on a top surface of the fifth body layer C5, and third lower conductive patterns S2disposed on a bottom surface of the fifth body layer C5. Third circuit vias50may penetrate the fifth body layer C5and may electrically connect the third upper conductive patterns54to the third lower conductive patterns S2. The fifth body layer C5may include or may be formed of a material which is the same as or similar to that of the first body layer C1. A third upper passivation layer PS5may be disposed on the top surface of the fifth body layer C5and may partially expose the third upper conductive patterns54. A third lower passivation layer PS6may be disposed on the bottom surface of the fifth body layer C5and may partially expose the third lower conductive patterns S2. The third upper and lower passivation layers PS5and PS6may include or may be formed of a material which is the same as or similar to that of the first upper and lower passivation layers PS1and PS2. The second semiconductor chips CH2may be of the same kind of a memory chip. The second semiconductor chips CH2may be offset from each other in the first direction X or in the first and second directions X and Y and may be stacked to constitute a stepwise structure. The second semiconductor chips CH2may be connected through wires60to the third upper conductive patterns54.

The second sub-semiconductor package700may be electrically connected through third internal connection members320to the wiring structure600. The third internal connection members320may connect the third lower conductive patterns S2to the second upper conductive patterns34. The third internal connection members320may be one or more of solder balls, conductive bumps, and conductive pillars.

A third thermal interface material layer750may be interposed between the second sub-semiconductor package700and the first thermal radiation part HS1. The third thermal interface material layer750may include or may be formed of a material which is the same as or similar to that of the first thermal interface material layer550. The third thermal interface material layer750may contact a top surface of the second mold layer MD2.

The semiconductor package1000according to some example embodiments of the present inventive concepts may be configured such that the wiring structure600includes the thermal conductive layer TL, the thermal conductive via VT, and the thermal conductive pad TP, which are arranged to transfer heat from the first semiconductor apparatus CH1to the thermal radiation member HS. Therefore, heat generated from the first semiconductor apparatus CH1may be immediately discharged outwards. Accordingly, it may be possible to minimize, reduce, or prevent an increase in temperature of the first semiconductor apparatus CH1. A reduction in speed of the first semiconductor apparatus CH1may be prevented to avoid operating failure of the semiconductor package1000, which may result in an improvement in overall performance of the semiconductor package1000. The first, second, and third circuit vias10,30, and50may transmit electrical signals. Although not shown, the third width W3of the thermal conductive via VT may be greater than a width of the first circuit via10. The third width W3of the thermal conductive via VT may be greater than a width of the third circuit via50. The width of the thermal conductive via VT may be relatively greater than those of the first, second, and third circuit vias10,30, and50to facilitate heat transfer from the first semiconductor apparatus CH1to the thermal radiation member HS.

FIGS.5A to5Eillustrate cross-sectional views showing a method of fabricating a semiconductor package ofFIG.2.

Referring toFIG.5A, a first substrate S1may be prepared. The first substrate S1may include chip regions R1and a separation region SR between the chip regions R1. The first substrate S1may have on each of the chip regions R1a structure which is the same as or similar to that discussed with reference toFIG.2. First internal connection members310may be used to flip-chip bond first semiconductor apparatuses CH1to corresponding chip regions R1of the first substrate S1. A first under-fill layer UF1may be interposed between each of the first semiconductor apparatuses CH1and the first substrate S1. First preliminary connection members20amay be bonded to first upper conductive patterns16of the first substrate S1beside the first semiconductor apparatuses CH1. The first preliminary connection members20amay be solder balls, conductive bumps, or conductive pillars.

Referring toFIG.5B, a first thermal interface material layer550may be formed on the first semiconductor apparatus CH1. A wiring structure600may be positioned on the first substrate S1. The wiring structure600may have structures which are the same as or similar to those discussed with reference toFIGS.3A and3B. The wiring structure600may be aligned to the chip regions R1. Second preliminary connection members20bmay be bonded to second lower conductive patterns32of the wiring structure600. The second preliminary connection members20bmay be, for example, solder balls, conductive bumps, or conductive pillars.

Referring toFIGS.5C and5D, a reflow process may be performed after a thermal conductive layer TL of the wiring structure600is allowed to contact the first thermal interface material layer550and the second preliminary connection member20bis allowed to contact the first preliminary connection member20a. In the reflow process, the first preliminary connection member20aand the second preliminary connection member20bmay be melted and connected to each other to form a second internal connection member20. A molding process may be performed to form a first mold layer MD1that fills a space between the wiring structure600and the first substrate S1. External connection terminals300may be bonded to first lower conductive patterns18of the first substrate S1.

Referring toFIGS.5D and5E, a sawing or singulation process may be performed to separate the wiring structure600, the first mold layer MD1, and the first substrate S1from the separation region SR into individual preliminary semiconductor packages PPKG. In each preliminary semiconductor package PPKG, the wiring structure600is stacked on a first sub-semiconductor package500. The preliminary semiconductor packages PPKG may be tested to select non-defective preliminary semiconductor packages PPKG.

Referring back toFIGS.2and5E, second sub-semiconductor packages700may be prepared. The second sub-semiconductor packages700may also be tested to select non-defective second sub-semiconductor packages700. The second sub-semiconductor package700may be flip-chip bonded to the preliminary semiconductor package PPKG. In this step, the second sub-semiconductor package700may be disposed to expose thermal conductive pads TP. For example, in the preliminary semiconductor package PPKG with the second sub-semiconductor package700flip-chip bonded thereto, the second sub-semiconductor package700does not cover the thermal conductive pads TP. A second thermal interface material layer650and a third thermal interface material layer750may be formed on the preliminary semiconductor package PPKG with the second sub-semiconductor package700flip-chip bonded thereto. For example, the second thermal interface material layer650may be formed on the thermal conductive pad TP, and the third thermal interface material layer750may be formed on the second sub-semiconductor package700. A thermal radiation member HS may be bonded to the second sub-semiconductor package700with the third thermal interface material layer750. A semiconductor package1000may thus be fabricated as shown inFIG.2.

FIG.6illustrates a cross-sectional view taken along line IA-IA′ ofFIG.1.FIG.7Aillustrates a plan view showing a wiring structure according to some example embodiments of the present inventive concepts.FIG.7Billustrates a cross-sectional view taken along line IA-IA′ ofFIG.7A.

Referring toFIGS.6,7A, and7B, a semiconductor package1001according to the present embodiment may include a first sub-semiconductor package500, a wiring structure601, a second sub-semiconductor package700, and a thermal radiation member HS that are sequentially stacked on each other. The first sub-semiconductor package500, the second sub-semiconductor package700, and the thermal radiation member HS may be the same as or similar to those discussed with reference toFIG.2. The wiring structure601may have a different structure from that of the wiring structure600shown inFIGS.3A and3B.

The wiring structure601may further include a dielectric support pattern SP bonded to a bottom surface of the second lower passivation layer PS4. The dielectric support pattern SP may include or may be formed of one or more of an epoxy resin, a die attach film (DAF), a non-conductive film (NCF), and a photosensitive solder resist (PSR) layer. The dielectric support pattern SP may be formed to have a plurality of island shapes that are spaced apart from each other in the first and second directions X and Y. The dielectric support pattern SP may maintain a certain distance between the wiring structure601and the first semiconductor apparatus CH1in the fabrication step ofFIG.5C. The dielectric support pattern SP may support the wiring structure601and may prevent warpage of the wiring structure601. The semiconductor package1001with the dielectric support pattern SP may increase reliability.

The thermal conductive layer TL of the wiring structure601may have a grid shape. When the wiring structure601is viewed in a plan view, the thermal conductive layer TL may have a plurality of openings H1that are shaped like islands spaced apart from each other. The openings H1may be filled with the second lower passivation layer PS4. The dielectric support patterns SP may overlap portions of the second lower passivation layer PS4filling the openings H1. The other configurations may be identical or similar to those discussed with reference toFIGS.3A and3B.

Referring toFIG.8A, the dielectric support pattern SP may contact the top surface of the first semiconductor apparatus CH1. The first thermal interface material layer550adjacent to an edge of the first semiconductor apparatus CH1may laterally protrude beyond the first semiconductor apparatus CH1to thereby contact an upper sidewall of the first semiconductor apparatus CH1. The first thermal interface material layer550may contact the bottom surface of the second lower passivation layer PS4. The first mold layer MD1may have, on its upper sidewall, a recessed region RC1in contact with the first thermal interface material layer550.

Alternatively, as shown inFIG.8B, the dielectric support pattern SP may be spaced apart from the top surface of the first semiconductor apparatus CH1. A portion of the first thermal interface material layer550may be interposed between the dielectric support pattern SP and the first semiconductor apparatus CH1. The other structural features may be identical or similar to those discussed with reference toFIG.8A.

FIG.9illustrates a cross-sectional view taken along line IA-IA′ ofFIG.1.

Referring toFIG.9, a semiconductor package1002according to the present embodiment may include a first sub-semiconductor package500, a wiring structure600, a second sub-semiconductor package700, and a thermal radiation member HS that are sequentially stacked on each other. The first sub-semiconductor package500, the wiring structure600, and the second sub-semiconductor package700may be the same as or similar to those discussed with reference toFIG.2. The thermal radiation member HS may have a structure different from that ofFIG.2. In the present embodiment, the thermal radiation member HS may have a uniform thickness as a whole. The second thermal radiation part HS2of the thermal radiation member HS may have an L-shaped cross-section. The second thermal interface material layer650may extend from a gap between the second thermal radiation part HS2and the wiring structure600into a gap between the second thermal radiation part HS2and a sidewall of the second sub-semiconductor package700. The second thermal interface material layer650may further extend into a gap between the first thermal radiation part HS1and a top surface of the second sub-semiconductor package700. The second under-fill layer UF2may fill a space between the second sub-semiconductor package700and the wiring structure600. The second under-fill layer UF2may include or may be formed of a material which is the same as or similar to that of the first under-fill layer UF1. The other configurations may be identical or similar to those discussed with reference toFIGS.1to4C.

FIG.10illustrates a cross-sectional view taken along line IA-IA′ ofFIG.1.

Referring toFIG.10, a semiconductor package1003according to the present embodiment may include a first sub-semiconductor package501, a wiring structure602, a second sub-semiconductor package700, and a thermal radiation member HS that are sequentially stacked on each other. The first sub-semiconductor package501may be shaped like a chip last-type fan-out wafer level package (FOWLP). The first sub-semiconductor package501may include a first redistribution substrate RD1, a first semiconductor apparatus CH1mounted on the first redistribution substrate RD1, and a first mold layer MD1that covers the first semiconductor apparatus CH1. The first semiconductor apparatus CH1may be flip-chip bonded through the first internal connection members310to the first redistribution substrate RD1.

The first redistribution substrate RD1may include first, second, third, and fourth redistribution dielectric layers IL1, IL2, IL3, and IL4that are sequentially stacked on each other. The first, second, third, and fourth redistribution dielectric layers IL1, IL2, IL3, and IL4may be photo-imagable dielectric (PID) layer. First, second, and third redistribution patterns342,344, and346may be disposed between the first, second, third, and fourth redistribution dielectric layers IL1, IL2, IL3, and IL4. The first, second, and third redistribution patterns342,344, and346may include or may be formed of a conductive material, such as metal. Each of the first, second, and third redistribution patterns342,344, and346may include a via part VP and a line part LP that are integrally united with each other. The via part VP may be disposed below the line part LP. A barrier/seed pattern SL may be interposed between the first redistribution pattern342and the first redistribution dielectric layer IL1, between the second redistribution pattern344and the second redistribution dielectric layer IL2, and between the third redistribution pattern346and the third redistribution dielectric layer IL3. The barrier/seed pattern SL may include a barrier layer and a seed layer that are sequentially stacked on each other. The barrier layer may include or may be formed of a metal nitride layer. The seed layer may include or may be formed of the same metal as that of the first, second, and third redistribution patterns342,344, and346.

A first redistribution bump340may be provided in the first redistribution dielectric layer IL1. A first redistribution pad348may be disposed in the fourth redistribution dielectric layer IL4. The external connection terminal300may be bonded to the first redistribution bump340. The first mold layer MD1may cover the sidewall of the first semiconductor apparatus CH1and a top surface of the first redistribution substrate RD1. A first mold via MV1may penetrate the first mold layer MD1and may contact the first redistribution pad348of the first redistribution substrate RD1. The first mold via MV1may include or may be formed of metal, such as copper. The first mold via MV1may electrically connect the wiring structure602to the first redistribution substrate RD1.

FIG.11an enlarged view showing section P4ofFIG.10.

Referring toFIGS.10and11, the wiring structure602may have a structure similar to that of the first redistribution substrate RD1. In the present embodiment, the wiring structure602may be called a second redistribution substrate. The wiring structure602may include fifth, sixth, and seventh redistribution dielectric layers IL5, IL6, and IL7, and may also include fourth and fifth redistribution patterns352and354interposed between the fifth, sixth, and seventh redistribution dielectric layers IL5, IL6, and IL7. A sixth redistribution pattern356may be disposed on the seventh redistribution dielectric layer IL7. Like the first, second, and third redistribution patterns342,344, and346, each of the fourth, fifth, sixth redistribution patterns352,354, and356may also include a via part VP and a line part LP. The via parts VP of the first, second, third, fourth, fifth, and sixth redistribution patterns342,344,346,352,354, and356may have their inclined sidewalls.

A barrier/seed pattern SL may be interposed between the fourth redistribution pattern352and the fifth redistribution dielectric layer IL5, between the fifth redistribution pattern354and the sixth redistribution dielectric layer IL6, and between the sixth redistribution pattern356and the seventh redistribution dielectric layer IL7. A second redistribution bump350may be disposed in the fifth redistribution dielectric layer IL5.

The first mold via MV1may connect the second redistribution bump350to the first redistribution pad348. The wiring structure602may include a thermal conductive layer TL, a thermal conductive pad TP, and a thermal conductive via structure VST that connects the thermal conductive layer TL to the thermal conductive pad TP. The thermal conductive via structure VST may include first, second, and third thermal conductive via parts VT1, VT2, and VT3that are stacked on each other. The term “thermal conductive via part” may be called “sub-via.”

The first, second, and third thermal conductive via parts VT1, VT2, and VT3may have their inclined sidewalls. The thermal conductive via structure VST may further include a barrier/seed pattern SL interposed between the first thermal conductive via part VT1and the fifth redistribution dielectric layer IL5, between the second thermal conductive via part VT2and the sixth redistribution dielectric layer IL6, and between the third thermal conductive via part VT3and the seventh redistribution dielectric layer IL7. The barrier/seed pattern SL may also be interposed between the thermal conductive pad TP and the seventh redistribution dielectric layer IL7.

The first, second, and third thermal conductive via parts VT1, VT2, and VT3may each have a fifth width W5greater than a sixth width W6of each of the via parts VP of the fourth, fifth, and sixth redistribution patterns352,354, and356. In an embodiment, the fifth width W5may be the minimum width of each of the first, second, and third thermal conductive via parts VT1, VT2, and VT3, and the sixth width W6may be the minimum width of each of the via parts VP. The first thermal conductive via part VT1may have an increasing width from the fifth width W5in a third direction Z. In an embodiment, the width of the first thermal conductive via part VT1may gradually increase from the fifth width W5in a third direction Z. This width increase of the first thermal conductive via part VT1may be applicable to the remaining thermal conductive via parts VT2and VT3. The width of each via part VP may increase from the sixth width W6in the third direction Z. The fifth width W5may have a value, for example, from about 100 μm to about 250 μm. The sixth width W6may have a value, for example, from about 1 μm to about 70 μm.

The thermal conductive layer TL may have the same material and thickness as those of the second redistribution bump350. The thermal conductive pad TP may be connected to the third thermal conductive via part VT3, and may have the same thickness and material as those of the line part LP of the sixth redistribution pattern356. The first, second, and third thermal conductive via parts VT1, VT2, and VT3may have the same thickness and material as those of the via parts VP of the fourth, fifth, and sixth redistribution patterns352,354, and356. Alternatively, the thermal conductive layer TL, the thermal conductive pad TP, and the first, second, and third thermal conductive via parts VT1, VT2, and VT3may have different material (e.g., a material whose thermal conductivity is higher) and thickness (e.g., greater thickness) from those of the fourth, fifth, and sixth redistribution patterns352,354, and356.

In the embodiment shown inFIGS.10and11, the semiconductor package1003may be implemented without including the first thermal interface material layer550ofFIG.2. In the present embodiment, the second thermal interface material layer650may cover a top surface and a sidewall of the thermal conductive pad TP and a sidewall of the barrier/seed pattern SL below the thermal conductive pad TP. The fifth redistribution dielectric layer IL5may have a bottom surface lower than that of the second redistribution bump350and that of the thermal conductive layer TL. The first mold layer MD1may surround a sidewall of the first mold via MV1and a sidewall of the first semiconductor apparatus CH1. In an embodiment, an upper surface of the first mold layer MD1may be uneven, and the first mold layer MD1may be interposed between an upper portion of the first mold via MV1and a lower portion of the fifth redistribution dielectric layer IL5which are adjacent to each other in the first direction X, and between an upper portion of the first semiconductor apparatus CH1and a lower portion of the first redistribution dielectric layer IL5which are adjacent to each other in the first direction X. The topmost upper surface of the first mold layer MD1may contact a bottom surface of the second redistribution bumps350, and a bottom surface of the thermal conductive layer TL. The other configurations may be identical or similar to those discussed with reference toFIGS.1to4C.

FIG.12illustrates a cross-sectional view taken along line IA-IA′ ofFIG.1.

Referring toFIG.12, a semiconductor package1004according to the present embodiment may include a first sub-semiconductor package502, a wiring structure602, a second sub-semiconductor package700, and a thermal radiation member HS that are sequentially stacked on each other. The first sub-semiconductor package502may be shaped like a chip first-type fan-out wafer level package (FOWLP). The first sub-semiconductor package502may include a first redistribution substrate RD1, a first semiconductor apparatus CH1mounted on the first redistribution substrate RD1, and a first mold layer MD1that covers the first semiconductor apparatus CH1. The first semiconductor apparatus CH1may contact the first redistribution substrate RD1. The first under-fill layer UF1and the first internal connection member310ofFIG.10are not present in the first sub-semiconductor package502.

Each of first, second, and third redistribution patterns342,344, and346included in the first redistribution substrate RD1may include a via part VP and a line part LP that are integrally united with each other. The via part VP may be positioned on the line part LP. A barrier/seed pattern SL may be interposed between the first redistribution pattern342and a second redistribution dielectric layer IL2, between the second redistribution pattern344and a third redistribution dielectric layer IL3, and between the third redistribution pattern346and a fourth redistribution dielectric layer IL4. The first redistribution dielectric layer IL1may have therein a first redistribution bump340in contact with the line part LP of the first redistribution pattern342. A first redistribution pad348may be positioned on the fourth redistribution dielectric layer IL4. The other configurations may be identical or similar to those discussed with reference toFIGS.10and11.

FIG.13illustrates a cross-sectional view taken along line IA-IA′ ofFIG.1.

Referring toFIG.13, a semiconductor package1005according to the present embodiment may include a first sub-semiconductor package503, a wiring structure602, a second sub-semiconductor package700, and a thermal radiation member HS that are sequentially stacked on each other. The first sub-semiconductor package503may be shaped like a chip last-type fan-out panel level package (FOPLP). The first sub-semiconductor package503may include a first redistribution substrate RD1, a connection substrate900disposed on the first redistribution substrate RD1, and a first semiconductor apparatus CH1mounted on the first redistribution substrate RD1.

The connection substrate900may include a cavity region CV at a center thereof. The first semiconductor apparatus CH1may be disposed in the cavity region CV. The connection substrate900may include a plurality of base layers910and a conductive structure920. The base layers910may include or may be formed of a dielectric material. For example, the base layers910may include or may be formed of a carbon-based material, a ceramic, or a polymer. The conductive structure920may include a connection pad921, a first connection via922, a connection line923, and a second connection via924. The connection substrate900may be connected through a fourth internal connection member305to the first redistribution substrate RD1. A second under-fill layer UF2may be interposed between the connection substrate900and the first redistribution substrate RD1. A first mold layer MD1may fill a space between the first semiconductor apparatus CH1and an inner wall of the cavity region CV of the connection substrate900. The second connection via924of the first sub-semiconductor package503may contact a second redistribution bump350of the wiring structure602. The other configurations may be identical or similar to those discussed with reference toFIGS.10and11.

FIG.14illustrates a plan view showing a semiconductor package according to some example embodiments of the present inventive concepts.FIG.15illustrates a cross-sectional view taken along line IA-IA′ ofFIG.14.

Referring toFIGS.14and15, a semiconductor package1006according to the present embodiment may include a first sub-semiconductor package500and a wiring structure603that are sequentially stacked on each other. A second sub-semiconductor package100and a third sub-semiconductor package200may be disposed on the wiring structure603, and may be spaced apart from each other in a first direction X. A thermal radiation member HS may cover the second sub-semiconductor package100and the third sub-semiconductor package200. The thermal radiation member HS may include a first thermal radiation part HS1that overlaps the second and third sub-semiconductor packages100and200, and may also include a second thermal radiation part HS2that extends toward the wiring structure603from a sidewall of the first thermal radiation part HS1. The second thermal radiation part HS2may have an “8” shape when the semiconductor package1006is viewed in a plan view. The second thermal radiation part HS2may also be interposed between the second sub-semiconductor package100and the third sub-semiconductor package200. In an embodiment, each of the second sub-semiconductor package100and the third sub-semiconductor package200may be surrounded by the second thermal radiation part HS2.

The wiring structure603may include a thermal conductive pad TP that overlaps the second thermal radiation part HS2. The thermal conductive pad TP may have an “8” shape when the semiconductor package1006is viewed in a plan view. A plurality of thermal conductive vias VT may vertically overlap the second thermal radiation part HS2between the second sub-semiconductor package100and the third sub-semiconductor package200.

The second sub-semiconductor package100may include a second substrate101, a second semiconductor chip102mounted on the second substrate101through a wire103, and a second mold layer104that covers the second semiconductor chip102. The third sub-semiconductor package200may include a plurality of second semiconductor chips202stacked on a first semiconductor chip201. Each of the first and second semiconductor chips201and202may include a through via203. Sidewalls of the second semiconductor chips202may be covered with a third mold layer204. The third sub-semiconductor package200may be a high bandwidth memory (HBM) chip in which the first semiconductor chip201may be a logic device, and the second semiconductor chips202may be memory devices. A third thermal interface material layer750may be interposed between the first thermal radiation part HS1and the second sub-semiconductor package100and between the first thermal radiation part HS1and the third sub-semiconductor package200. The other configurations may be identical or similar to those discussed with reference toFIGS.1to4C.

FIGS.16A to16Eillustrate plan views showing a semiconductor package according to some example embodiments of the present inventive concepts.

Referring toFIG.16A, a semiconductor package1007according to the present embodiment may be configured such that a second thermal radiation part HS2and a thermal conductive pad TP have a “C” shape when the semiconductor package1007is viewed in a plan view.

Referring toFIG.16B, a semiconductor package1008according to the present embodiment may be configured such that a second thermal radiation part HS2and a thermal conductive pad TP have an “I” shape when the semiconductor package1008is viewed in a plan view.

Referring toFIG.16C, a semiconductor package1009according to the present embodiment may be configured such that a second thermal radiation part HS2and a thermal conductive pad TP have an “O” shape when the semiconductor package1009is viewed in a plan view. The second thermal radiation part HS2may surround a second sub-semiconductor package700.

Referring toFIG.16D, a semiconductor package1010according to the present embodiment may be configured such that a second thermal radiation part HS2and a thermal conductive pad TP have a grid shape when the semiconductor package1010is viewed in a plan view. Second sub-semiconductor packages700a,700b,700c, and700dmay be two-dimensionally arranged along a first direction X and a second direction Y. The second thermal radiation part HS2may be interposed between the second sub-semiconductor packages700ato700d, while surrounding the second sub-semiconductor packages700ato700d.

Referring toFIG.16E, a semiconductor package1011according to the present embodiment may be configured such that a second thermal radiation part HS2and a thermal conductive pad TP have a grid shape or an “E” shape when the semiconductor package1011is viewed in a plan view. Second sub-semiconductor packages700aand700bmay be linearly arranged in a second direction Y different from the first direction X. The second sub-semiconductor packages700aand700bmay be spaced apart from each other in the second direction Y. The second thermal radiation part HS2may be interposed between the second sub-semiconductor packages700aand700b.

In the embodiments shown inFIGS.16A to16E, the other configurations except those discussed above may be identical or similar to those discussed with reference toFIGS.1to15.

FIGS.17A and17Billustrate plan views showing a wiring structure according to some example embodiments of the present inventive concepts.

Referring toFIG.17A, a wiring structure604according to the present embodiment may include thermal conductive layers TL having island shapes that are spaced apart from each other along a first direction X and a second direction Y. Thermal conductive vias VT may be arranged identically or similarly to the thermal conductive layers TL. A thermal conductive pad TP may include protrusions TPP that connect a plurality of thermal conductive vias VT. The other configurations may be identical or similar to those discussed with reference toFIGS.3A and3B.

Referring toFIG.17B, a wiring structure605according to the present embodiment may include a thermal conductive layer TL that has a grid shape when the wiring structure605is viewed in a plan view. Although not shown, the planar shape of the thermal conductive layer TL is not limited to those illustrated inFIGS.3A,17A, and17B, but may have a cross shape, a circular shape, a closed loop shape, or any other shape.

A semiconductor package according to the present inventive concepts may be configured such that a wiring structure includes a thermal conductive layer, a thermal conductive via, and a thermal conductive pad, and thus heat is discharged from a first semiconductor apparatus of a first sub-semiconductor package to a heat sink of the semiconductor package. Therefore, a reduction in speed of the first semiconductor apparatus may be prevented to avoid operating failure of the semiconductor package and thereby to increase an operating speed of the semiconductor package, which may result in an improvement in overall performance of the semiconductor package.

A wiring structure according to the present inventive concepts may include a thermal conductive via whose width is greater than those of circuit vias, which configuration may achieve an advantage of thermal radiation.

Although the present inventive concepts have been described in connection with some example embodiments of the present inventive concepts illustrated in the accompanying drawings, it will be understood to those skilled in the art that various changes and modifications may be made without departing from the technical spirit and essential feature of the present inventive concepts. It will be apparent to those skilled in the art that various substitution, modifications, and changes may be thereto without departing from the scope and spirit of the present inventive concepts. The embodiments ofFIGS.1to17Bmay be combined with each other.