ELECTRONIC DEVICE

The disclosure provides an electronic device. The electronic device includes a substrate, a transistor, and a first insulating layer. The transistor is disposed on the substrate and includes a source electrode, a drain electrode, and a gate electrode. The first insulating layer is disposed between the source electrode and the gate electrode and between the drain electrode and the gate electrode. The first insulating layer has a first portion and a second portion. The first portion is defined as a portion overlapped with the source electrode and the drain electrode. The second portion is defined as a portion not overlapped with the source electrode and the drain electrode. A thickness of the first portion is greater than a thickness of the second portion. The electronic device of an embodiment of the disclosure may reduce transistor characteristic shift or improve transistor performance.

BACKGROUND

Technical Field

The disclosure relates to an electronic device, and more particularly, to an electronic device that may reduce transistor characteristic shift or improve transistor performance.

Description of Related Art

Electronic devices or tiled electronic devices have been widely used in different fields such as communication, display, passenger transportation, and medical treatment. With the vigorous development of electronic devices, there are higher requirements for the reliability or quality of electronic devices.

SUMMARY

The disclosure is directed to an electronic device that may reduce transistor characteristic shift or improve transistor performance.

According to an embodiment of the disclosure, an electronic device includes a substrate, a transistor, and a first insulating layer. The transistor is disposed on the substrate and includes a source electrode, a drain electrode, and a gate electrode. The first insulating layer is disposed between the source electrode and the gate electrode and between the drain electrode and the gate electrode. The first insulating layer has a first portion and a second portion. The first portion is defined as a portion overlapped with the source electrode and the drain electrode. The second portion is defined as a portion not overlapped with the source electrode and the drain electrode. A thickness of the first portion is greater than a thickness of the second portion.

According to an embodiment of the disclosure, an electronic device includes a substrate, a circuit layer, and a light detection element. The circuit layer is disposed on the substrate and includes a transistor. The light detection element is disposed on the circuit layer and electrically connected to the transistor. The circuit layer includes a first insulating layer. The first insulating layer has different thicknesses.

DESCRIPTION OF THE EMBODIMENTS

The disclosure may be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that in order to facilitate understanding to the reader and to simplify the drawings, the multiple drawings in the disclosure depict a part of the electronic device, and certain elements in the drawings are not drawn to actual scale. In addition, the number and size of each element in the figures are for illustration, and are not intended to limit the scope of the disclosure.

In the following description and claims, the words “including” and “containing” and the like are open words, so they should be interpreted as meaning “including but not limited to . . . ”

It should be understood that when an element or film layer is referred to as “on” or “connected to” to another element or film layer, the element or film layer may be directly on the other element or film layer or directly connected to the other element or layer, or there is an inserted element or film layer between the two (indirect case). Conversely, when an element is referred to as “directly” on or “directly connected” to another element or film layer, there is no intervening element or film layer between the two.

Although the terms “first”, “second”, “third” . . . may be used to describe various constituent elements, the constituent elements are not limited to these terms. These terms are used to distinguish a single constituent element from other constituent elements in the specification. The same terms may not be used in the claims, and the elements in the claims may be replaced with first, second, third . . . according to the order declared by the elements in the claims. Therefore, in the following description, the first constituent element may be the second constituent element in the claims.

In the text, the terms “about”, “approximately”, “substantially”, “essentially” generally mean within 10%, or within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. Quantities given herein are approximate quantities, that is, in the absence of a specific description of “about”, “approximately”, “substantially”, “essentially”, the meanings of “about”, “approximately”, “substantially”, “essentially” may still be implied.

In some embodiments of the disclosure, terms such as “connection”, “interconnection”, etc. regarding bonding and connection, unless specifically defined, may mean that two structures are in direct contact, or that two structures are not in direct contact and there are other structures located between these two structures. Moreover, the terms of bonding and connecting may also include the case where both structures are movable or both structures are fixed. In addition, the term “coupled” includes any direct and indirect electrical connection means.

In some embodiments of the disclosure, optical microscopy (OM), scanning electron microscope (SEM), film thickness profile measuring instrument (α-step), ellipsometer, or other suitable methods may be used to measure the area, width, thickness, or height of each element, or the distance or spacing between elements. Specifically, according to some embodiments, a scanning electron microscope may be used to obtain a cross-sectional structure image including the element to be measured, and the area, width, thickness, or height of each element, or the distance or spacing between elements may be measured.

The electronic device of the disclosure may include a display device, an antenna device, a sensing device, or a tiling device, but the disclosure is not limited thereto. The electronic device may be a bendable or flexible electronic device. The electronic device may include, for example, a liquid-crystal light-emitting diode (LED); and the LED may include, for example, an organic light-emitting diode (OLED), mini LED, micro LED, or quantum dot (QD) LED (such as QLED), fluorescence, phosphor, or other suitable materials, and the materials thereof may be arranged and combined arbitrarily, but the disclosure is not limited thereto. The antenna device may be, for example, a liquid-crystal antenna, but the disclosure is not limited thereto. The tiling device may be, for example, a display tiling device or an antenna tiling device, but the disclosure is not limited thereto. It should be noted that the electronic device may be any combination of the above, but the disclosure is not limited thereto. Hereinafter, the disclosure will be described with an electronic device, but the disclosure is not limited thereto.

It should be noted that in the following embodiments, the features in several different embodiments may be replaced, recombined, and mixed to complete other embodiments without departing from the spirit of the disclosure. As long as the features between the embodiments do not violate the spirit of the disclosure or conflict with each other, they may be mixed and used arbitrarily.

Hereinafter, reference will be made in detail to exemplary embodiments of the disclosure, and examples of the exemplary embodiments are illustrated in the figures. Wherever possible, the same reference numerals are used in the figures and the descriptions to refer to the same or similar portions.

FIG.1is a schematic cross-sectional view of an electronic device of an embodiment of the disclosure. Referring toFIG.1, an electronic device100of the present embodiment includes a substrate110, a transistor120, and a first insulating layer130. In particular, the substrate110may include a rigid substrate, a flexible substrate, or a combination of the above. For example, the material of the substrate110may include glass, quartz, sapphire, ceramics, polycarbonate (PC), polyimide (PI), polyethylene terephthalate (PET), other suitable substrate materials, or a combination of the above, but the disclosure is not limited thereto.

In the present embodiment, the transistor120is disposed on the substrate110. The transistor120may be, for example, an amorphous silicon thin-film transistor (TFT), a polysilicon such as a low-temperature polysilicon (LTPS) TFT, indium gallium zinc oxide (IGZO) TFT, other suitable transistors, or a combination of the above, but the disclosure is not limited thereto. Moreover, the type of the transistor120may be, for example, a switch TFT, a driving TFT, a scan TFT, a reset TFT, or other suitable transistors, but the disclosure is not limited thereto.

Specifically, the transistor120includes a source electrode121, a drain electrode122, a gate electrode123, and a semiconductor layer124. The gate electrode123is disposed on the substrate110. The semiconductor layer124is disposed on the gate electrode123, and the semiconductor layer124may be overlapped with the gate electrode123in a normal direction Z of the substrate110. The source electrode121and the drain electrode122are disposed on the semiconductor layer124, and the semiconductor layer124may be disposed between the source electrode121and the gate electrode123and between the drain electrode122and the gate electrode123. In the present embodiment, the source electrode121and the drain electrode122may be in contact with a portion1241of the semiconductor layer124to be electrically connected to the semiconductor layer124, there is a gap G between the source electrode121and the drain electrode122, and the gap G may expose another portion1242of the semiconductor layer124. The other portion1242may at least be overlapped with the gate electrode123in the normal direction Z of the substrate110, and an upper surface1242aof the other portion1242(i.e., the surface of the other portion1242facing away from the gate electrode123) may have an arc edge, but the disclosure is not limited thereto.

In the present embodiment, the transistor120may be, for example, a top gate transistor, but the disclosure is not limited thereto, and in some embodiments, the transistor may also be a bottom gate transistor or a dual gate or double gate transistor. In the present embodiment, the material of the semiconductor layer124may include, but is not limited to, amorphous silicon, low-temperature polysilicon, metal oxide (e.g., indium gallium zinc oxide), other suitable materials, or a combination of the above, but the disclosure is not limited thereto.

In the present embodiment, the first insulating layer130is disposed on the gate electrode123. The first insulating layer130may cover the substrate110. The first insulating layer130is disposed between the source electrode121and the gate electrode123and between the drain electrode122and the gate electrode123. In the present embodiment, the first insulating layer130may be in contact with the semiconductor layer124, and the first insulating layer130may be in contact with the gate electrode123and/or the substrate110, but the disclosure is not limited thereto. In the present embodiment, the first insulating layer130may have a single-layer or multi-layer structure, and the material of the first insulating layer130may include an organic material, inorganic material, or a combination of the above, but the disclosure is not limited thereto.

Specifically, the first insulating layer130has a first portion131, a second portion132, and a second portion133. The first portion131may be defined as the portion of the first insulating layer130overlapped with the source electrode121and the drain electrode122in the normal direction Z of the substrate110, and the second portion132and the second portion133may be defined as the portion of the first insulating layer130not overlapped with the source electrode121and the drain electrode122in the normal direction Z of the substrate110. In particular, the second portion132may be not overlapped with the gate electrode123in the normal direction Z of the substrate110, for example, and the second portion133may be overlapped with the gate electrode123in the normal direction Z of the substrate110, for example. In some embodiments, the first portion131may, for example, be completely overlapped with the source electrode121and the drain electrode122in the normal direction Z of the substrate110.

In the present embodiment, the first portion131has a thickness T1, the second portion132has a thickness T2, and the second portion133has a thickness T2′. The thickness T1of the first portion131is greater than the thickness T2of the second portion132. The thickness T1of the first portion131is, for example, equal to the thickness T2′ of the second portion133. In particular, the thickness T1of the first portion131is, for example, the minimum thickness of the first portion131measured along the normal direction Z of the substrate110in a cross section, the thickness T2of the second portion132is, for example, the minimum thickness of the second portion132measured along the normal direction Z of the substrate110, and the thickness T2′ of the second portion133is, for example, the minimum thickness of the second portion133measured along the normal direction Z of the substrate110. In some embodiments, a difference D between the thickness T1of the first portion131and the thickness T2of the second portion132may be greater than or equal to 0.01 micrometers (μm) and less than the thickness T1of the first portion131(i.e., 0.01 μm≤difference<T1), but the disclosure is not limited thereto. In some embodiments, the second portion132may be regarded as a recess of the first insulating layer130, and the depth of the recess may be substantially equal to the difference D, but the disclosure is not limited thereto.

In the present embodiment, in a cross-section, an upper surface1321of the second portion132has an oblique edge1321aand a horizontal edge1321bconnected to each other. There may be an angle A between the oblique edge1321aand the horizontal edge1321b, and the angle A may be greater than or equal to 90° (degrees) and less than 180° (i.e., 90°≤SA<180°), but the disclosure is not limited thereto. In some embodiments, the angle A may also be greater than or equal to 95 degrees and less than or equal to 175 degrees, greater than or equal to 100 degrees and less than or equal to 170 degrees, or greater than or equal to 105 degrees and less than or equal to 165 degrees. In some embodiments, the oblique edge1321aof the second portion132and a side edge121S of the source electrode121or a side edge122S of the drain electrode122may be aligned or not aligned. When the oblique edge1321aof the second portion132is aligned with the side edge121S of the source electrode121or the side edge122S of the drain electrode122, the oblique edge1321aand the side edge121S or the side edge122S may be connected to each other, for example. When the oblique edge1321aof the second portion132is not aligned with the side edge121S of the source electrode121or the side edge122S of the drain electrode122, the oblique edge1321aand the side edge121S or the side edge122S may be not connected to each other, for example.

In the present embodiment, the method of thinning the second portion132of the first insulating layer130may include, but is not limited to, the following steps: first, the first insulating layer130is formed on the gate electrode123so that the first insulating layer130may cover the gate electrode123and the substrate110; then, the semiconductor layer124is formed on the first insulating layer130, so that the semiconductor layer124may be overlapped with the gate electrode123in the normal direction Z of the substrate110; next, an electrode material layer (not shown) is formed on the semiconductor layer124, so that the electrode material layer may cover the semiconductor layer124and the first insulating layer130; next, an etching process is performed on the electrode material layer to form the source electrode121and the drain electrode122, wherein the source electrode121and the drain electrode122are in contact with the portion1241of the semiconductor layer124and expose the other portion1242of the semiconductor layer124; then, the etching process further over-etches the second portion132of the first insulating layer130and the other portion1242of the semiconductor layer124exposed by the source electrode121and the drain electrode122, so that the thickness T2of the second portion132may be less than the thickness T1of the first portion131. In a cross-section, the upper surface1242aof the other portion1242may have an arc edge.

In some embodiments, the method of thinning the second portion132of the first insulating layer130may include, but is not limited to, the following steps: first, the first insulating layer130is formed on the gate electrode123so that the first insulating layer130may cover the gate electrode123and the substrate110; then, the semiconductor layer124is formed on the first insulating layer130, so that the semiconductor layer124may be overlapped with the gate electrode123in the normal direction Z of the substrate110; next, an electrode material layer (not shown) is formed on the semiconductor layer124, so that the electrode material layer may cover the semiconductor layer124and the first insulating layer130; next, an etching process is performed on the electrode material layer to form the source electrode121and the drain electrode122on the semiconductor layer124; then, an etching process is performed on the second portion132of the first insulating layer130and/or the other portion1242of the semiconductor layer124exposed by the source electrode121and the drain electrode122, so that the thickness T2of the second portion132may be less than the thickness T1of the first portion131, and the upper surface1242aof the other portion1242may have an arc edge. In some embodiments, the middle portion of the other portion1242has, for example, a recess, so that the upper surface1242aof the other portion1242has an arc edge. In some embodiments, the upper surface1242aof the other portion1242may include other irregular shapes.

In the present embodiment, by reducing the thickness T2of the second portion132of the first insulating layer130to make the thickness T2of the second portion132less than the thickness T1of the first portion131, the hydrogen content in the first insulating layer130may be reduced to reduce the issue of characteristic shift of the transistor120or improve the performance of the transistor120.

Other embodiments are listed below for description. It must be noted here that the following embodiments adopt the reference numerals and part of the content of the above embodiments, wherein the same reference numerals are used to represent the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted parts, reference may be made to the above embodiments, which is not repeated in the following embodiments.

FIG.2is a schematic cross-sectional view of an electronic device of another embodiment of the disclosure. Please refer toFIG.1andFIG.2at the same time. An electronic device100aof the present embodiment is similar to the electronic device100inFIG.1, but the differences between the two are: the electronic device100aof the present embodiment further includes a second insulating layer140.

Specifically, referring toFIG.2, in the present embodiment, the second insulating layer140is disposed on the semiconductor layer124and overlapped with the other portion1242of the semiconductor layer124. The second insulating layer140is disposed between the source electrode121, the drain electrode122, and the semiconductor layer124. In particular, the second insulating layer140may have a single-layer or multi-layer structure, and the material of the second insulating layer140may include an organic material, inorganic material, or a combination of the above, but the disclosure is not limited thereto.

In the present embodiment, since the second insulating layer140may cover the other portion1242of the semiconductor layer124, the upper surface1242aof the other portion1242may not have an arc edge, for example. Moreover, since the second insulating layer140may be exposed by the gap G between the source electrode121and the drain electrode122, the upper surface141of the second insulating layer140(i.e., the surface of the second insulating layer140facing away from the semiconductor layer124) may have an arc edge. In some embodiments, the middle portion of the second insulating layer140has, for example, a recess, so that the upper surface141of the second insulating layer140has an arc edge. In some embodiments, the upper surface141of the second insulating layer140may include other irregular shapes.

FIG.3is a schematic cross-sectional view of an electronic device of another embodiment of the disclosure. Please refer toFIG.1andFIG.3at the same time. An electronic device100bof the present embodiment is similar to the electronic device100inFIG.1, but the differences between the two are: in the electronic device100bof the present embodiment, a first insulating layer130bmay be disposed on the semiconductor layer124, and the electronic device100bfurther includes a second insulating layer140b.

Specifically, referring toFIG.3, in the present embodiment, the second insulating layer140bis disposed on the substrate110and between the semiconductor layer124and the gate electrode123. The second insulating layer140bmay be in contact with the semiconductor layer124, the gate electrode123, and the substrate110, but the disclosure is not limited thereto. The semiconductor layer124may be disposed on the second insulating layer140b.

The first insulating layer130bmay be disposed on the semiconductor layer124to cover the semiconductor layer124and the second insulating layer140b. The first insulating layer130bmay be disposed between the source electrode121, the drain electrode122, and the semiconductor layer124. The first insulating layer130bmay be disposed between the source electrode121, the drain electrode122, and the drain electrode123. The first insulating layer130bmay be in contact with the semiconductor layer124and not in contact with the gate electrode123and the substrate110. The thickness T1of a first portion131bof the first insulating layer130bmay be greater than the thickness T2of a second portion132bor the thickness T2′ of a second portion133b. The definitions of the thickness T1, the thickness T2, and the thickness T2′ are as provided above.

In the present embodiment, since the first insulating layer130bmay cover the other portion1242of the semiconductor layer124, the upper surface1242aof the other portion1242does not have an arc edge. Moreover, since the second portion133bof the first insulating layer130b(that is, the portion of the second portion133boverlapped with the gate electrode123in the normal direction Z of the substrate110) may be exposed by the gap G between the source electrode121and the drain electrode122, the upper surface133b1of the second portion133b(i.e., the surface of the second portion133bfacing away from the semiconductor layer124) may have an arc edge. In other words, in a cross-section, the upper surface133b1of the portion of the second portion133boverlapped with the gate electrode123has an arc edge. In some embodiments, the source electrode121and the drain electrode122are electrically connected to the semiconductor layer124via, for example, an opening O of the first insulating layer130b. In some embodiments, the thickness T2of the second portion132bmay be, for example, less than or equal to the thickness T2′ of the second portion133b. In some embodiments, the opening O of the first insulating layer130bmay be overlapped with the gate electrode123, but the disclosure is not limited thereto. In some embodiments, the cross-sectional structure of the second portion132bof the first insulating layer130bis, for example, stepped, but the disclosure is not limited thereto.

In the present embodiment, by reducing the thickness T2of the second portion132bof the first insulating layer130bto make the thickness T2of the second portion132bor the thickness T2′ of the second portion133bless than the thickness T1of the first portion131b, the hydrogen content in the first insulating layer130bmay be reduced to reduce the issue of characteristic shift of the transistor120or improve the performance of the transistor120.

In some embodiments not shown, the portion of the second insulating layer140bnot overlapped with the source electrode121and the drain electrode122in the normal direction Z of the substrate110may be selectively thinned to reduce the hydrogen content in the second insulating layer140b, in order to further reduce the issue of characteristic shift of the transistor120or further improve the performance of the transistor120.

FIG.4is a schematic cross-sectional view of an electronic device of another embodiment of the disclosure. Please refer toFIG.3andFIG.4at the same time. An electronic device100cof the present embodiment is similar to the electronic device100binFIG.3, but the differences between the two are: in the electronic device100cof the present embodiment, the transistor120cis a top-gate transistor.

Specifically, referring toFIG.4, a semiconductor layer124cis disposed between the second insulating layer140band the substrate110, and a gate electrode123cis disposed between the first insulating layer130band the second insulating layer140b. The second insulating layer140bis disposed between the semiconductor layer124cand the gate electrode123c. The gate electrode123cis disposed on the semiconductor layer124c, the first insulating layer130bis disposed on the gate electrode123c, and the first insulating layer130bis not in contact with the semiconductor layer124c. In the present embodiment, the width of the semiconductor layer124cmay be greater than the width of the gate electrode123cin a cross section, but the disclosure is not limited thereto.

In the present embodiment, for example, the source electrode121and the drain electrode122are separated from the semiconductor layer124cby the first insulating layer130band the second insulating layer140b, and the source electrode121and the drain electrode122are electrically connected to the semiconductor layer124cvia, for example, an opening O1of the first insulating layer130band the second insulating layer140b, respectively. In some embodiments, the thickness T2of the second portion132bof the first insulating layer130bor the thickness T2′ of the second portion133bmay be, for example, less than or equal to the thickness T1of the first portion131bof the first insulating layer130b. In some embodiments, the thickness T2of the second portion132bof the first insulating layer130bmay be, for example, less than or equal to the thickness T2′ of the second portion133bof the first insulating layer130b. In the present embodiment, the cross-sectional structure of the second portion132bof the first insulating layer130bis, for example, stepped, but the disclosure is not limited thereto.

In some embodiments not shown, the portion of the second insulating layer140bnot overlapped with the source electrode121and the drain electrode122in the normal direction Z of the substrate110may be further thinned to reduce the hydrogen content in the second insulating layer140b, in order to further reduce the issue of characteristic shift of the transistor120or further improve the performance of the transistor120.

FIG.5is a schematic cross-sectional view of an electronic device of another embodiment of the disclosure. Please refer toFIG.4andFIG.5at the same time. An electronic device100dof the present embodiment is similar to the electronic device100cinFIG.4, but the differences between the two are: in the electronic device100dof the present embodiment, the thickness of a portion of a second insulating layer140dmay be reduced.

Specifically, referring toFIG.5, in the present embodiment, the second insulating layer140dmay be disposed between the semiconductor layer124cand the gate electrode123c. The second insulating layer140dhas a third portion143and a fourth portion144. In particular, the third portion143may be defined as a portion of the second insulating layer140doverlapped with the gate electrode123cin the normal direction Z of the substrate110, and the fourth portion144may be defined as a portion of the second insulating layer140dnot overlapped with the gate electrode123cin the normal direction Z of the substrate110. In some embodiments, the third portion143may, for example, be completely overlapped with the gate electrode123cin the normal direction Z of the substrate110.

In the present embodiment, the third portion143has a thickness T3, the fourth portion144has a thickness T4, and the thickness T3of the third portion143is greater than the thickness T4of the fourth portion144. In particular, the thickness T3of the third portion143is, for example, the minimum thickness of the third portion143along the normal direction Z of the substrate110under a cross-sectional structure, and the thickness T4of the fourth portion144is, for example, the minimum thickness of the fourth portion144along the normal direction Z of the substrate110under a cross-sectional structure. In the present embodiment, the source electrode121and the drain electrode122are electrically connected to the semiconductor layer124cvia, for example, an opening O2of the first insulating layer130b(e.g., the first portion131b) and the second insulating layer140d(e.g., the fourth portion144). In the present embodiment, the thickness T2of the second portion132bmay be, for example, less than or equal to the thickness T1of the first portion131b, and the thickness T2of the second portion132bmay be, for example, less than or equal to the thickness T2′ of the second portion133b. In the present embodiment, the cross-sectional structure of the second portion132bof the first insulating layer130bis, for example, stepped, but the disclosure is not limited thereto.

In the present embodiment, by reducing the thickness T4of the fourth portion144of the second insulating layer140dto make the thickness T4of the fourth portion144less than the thickness T3of the third portion143, the hydrogen content in the second insulating layer140dmay be reduced to further reduce the issue of characteristic shift of the transistor120dor further improve the performance of the transistor120c.

FIG.6Ais a schematic top view of an electronic device of another embodiment of the disclosure.FIG.6Bis a schematic cross-sectional view of the electronic device ofFIG.6Aalong section line I-I′. For the clarity of the drawings and the convenience of description,FIG.6Aomits to show some elements in an electronic device100e.

Referring toFIG.6AandFIG.6B, the electronic device100eof the present embodiment includes the substrate110, a circuit layer CL, and a light detection element150. The circuit layer CL is disposed on the substrate110. The circuit layer CL is disposed on the substrate110and includes the transistor120as shown inFIG.1and the first insulating layer130as shown inFIG.1, and therefore details are not repeated herein. The circuit layer CL may be defined as all laminations between the uppermost conductive layer of the transistor120(i.e., the uppermost layer in the source electrode121, the drain electrode122, or the gate electrode123, but the disclosure is not limited thereto) and the surface of the substrate110.

In the present embodiment, the circuit layer CL includes the first insulating layer130. The first insulating layer130may have the first portion131, the second portion132, and the second portion133. The first portion131may be defined as the portion of the first insulating layer130overlapped with the source electrode121and the drain electrode122in the normal direction Z of the substrate110, and the second portion132and the second portion133may be defined as the portion of the first insulating layer130not overlapped with the source electrode121and the drain electrode122in the normal direction Z of the substrate110. In particular, the second portion132may not be overlapped with the gate electrode123in the normal direction Z of the substrate110, and the second portion133may be overlapped with the gate electrode123in the normal direction Z of the substrate110. In some embodiments, the first portion131may, for example, be completely overlapped with the source electrode121and the drain electrode122in the normal direction Z of the substrate110, but the disclosure is not limited thereto. The second portion133may be completely overlapped with the gate electrode123in the normal direction Z of the substrate110.

The first insulating layer130may have different thicknesses. Specifically, the first portion131of the first insulating layer130has the thickness T1, the second portion132of the first insulating layer130has the thickness T2, and the second portion133thereof has the thickness T2′. The thickness T1of the first portion131is greater than the thickness T2of the second portion132. The definitions of the thickness T1, the thickness T2, or the thickness T2′ are as previously described. In the present embodiment, since the first insulating layer130may have different thicknesses, the hydrogen content in the first insulating layer130may be reduced, so as to reduce the issue of characteristic shift of the transistor120or improve the performance of the transistor120.

In the present embodiment, the electronic device100efurther includes a scan line SL, a data line DL, an insulating layer160, an insulating layer162, a planarization layer164, a bias signal line BL, and/or a protective layer166. Specifically, as shown inFIG.6A, the scan line SL may be intersected with the data line DL, and the scan line SL may be intersected with the bias signal line BL, but the disclosure is not limited thereto. In some embodiments, the extending directions of the data line DL and the bias signal line BL may be substantially the same. In some embodiments, the data line DL and the bias signal line BL are not overlapped, for example, in the normal direction Z of the substrate110. The scan line SL may be electrically connected to the transistor120via the gate electrode123, and the data line DL may be electrically connected to the transistor120via the source electrode121.

Please continue to refer toFIG.6B, the insulating layer160may be disposed on the transistor120to cover the source electrode121, the semiconductor layer124, the drain electrode122, and the second portion132of the first insulating layer130. The insulating layer160may have a single-layer or multi-layer structure, and the material of the insulating layer160may include an organic material, inorganic material, or a combination of the above, but the disclosure is not limited thereto.

The light detection element150is disposed on the circuit layer CL and electrically connected to the transistor. Specifically, the light detection element150may include a lower electrode151, an active layer152, and an upper electrode153. The lower electrode151may be disposed on the insulating layer160, and the lower electrode151may be electrically connected to the drain electrode122via an opening O3of the insulating layer160, but the disclosure is not limited thereto. The active layer152may be disposed on the lower electrode151and located between the lower electrode151and the upper electrode153. The active layer152may be, for example, a stacked structure (e.g., a PIN photodiode) formed by a P-type semiconductor, an intrinsic semiconductor, and an N-type semiconductor, but the disclosure is not limited thereto.

In the normal direction Z of the substrate110, the area of the lower electrode151may be greater than or equal to the area of the active layer152. In the normal direction Z of the substrate110, the area of the active layer152may be greater than or equal to the area of the upper electrode153. In some embodiments, the thickness of the lower electrode151may be different from the thickness of the upper electrode153. In some embodiments, the material of the lower electrode151may be different from the material of the upper electrode153. In some embodiments, the lower electrode151may be a metal material, and the upper electrode153may be a transparent conductive material, but the disclosure is not limited thereto. In the normal direction Z of the substrate110, the lower electrode151may be not overlapped with the scan line SL and/or the data line DL, for example. In some embodiments, in the normal direction Z of the substrate110, the bias signal line BL is overlapped with the transistor120and/or the scan line SL, for example. In some embodiments, in the normal direction Z of the substrate110, the bias signal line BL is not overlapped with the data line DL, for example.

In some embodiments, the insulating layer162is disposed on the light detection element150to cover the light detection element150and the transistor120. The planarization layer164may be disposed on the insulating layer162. The bias signal line BL may be disposed on the planarization layer164, and the bias signal line BL may be electrically connected to the upper electrode153of the light detection element150via an opening O4penetrating the planarization layer164and the insulating layer162. The protective layer166may be disposed on the bias signal line BL to cover the bias signal line BL and the planarization layer164. In the present embodiment, the insulating layer162, the planarization layer164, and the protective layer166may be single-layer or multi-layer structures, and the material of the insulating layer162, the planarization layer164, and the protective layer166may include an organic material, an inorganic material, or a combination of the above, but the disclosure is not limited thereto.

Although the present embodiment applies the transistor120shown inFIG.1and the first insulating layer130shown inFIG.1in the electronic device100eincluding the light detection element150(e.g., a PIN photodiode), the disclosure is not limited thereto. In some embodiments, the transistor120shown inFIG.1and the first insulating layer130shown inFIG.1may also be applied to an electronic device (not shown) including a pixel unit. In some embodiments, the transistor and the first insulating layer shown inFIG.2,FIG.3,FIG.4, orFIG.5may also be applied to an electronic device including a light detection element (or pixel unit).

Based on the above, in the electronic device of an embodiment of the disclosure, by reducing the thickness of the second portion of the first insulating layer to make the thickness of the second portion less than the thickness of the first portion, the hydrogen content in the first insulating layer may be reduced to reduce the issue of characteristic shift of the transistor or improve the performance of the transistor. Moreover, by further reducing the thickness of the fourth portion of the second insulating layer to make the thickness of the fourth portion less than the thickness of the third portion, the hydrogen content in the second insulating layer may also be reduced to further reduce the issue of characteristic shift of the transistor or further improve the performance of the transistor.

Although the disclosure is disclosed as above by the embodiments, the embodiments are not intended to limit the disclosure. Any person of ordinary skill in the art may make some changes and modifications without departing from the spirit and scope of the disclosure. Therefore, the scope of the disclosure shall be subject to what is defined in the appending claims.