Oversized interposer formed from a multi-pattern region mask

An embodiment of an interposer is disclosed. In such an embodiment, there is a first printed circuit region and a second printed circuit region. The second printed circuit region is proximate to the first printed circuit region with a seam region between the first printed circuit region and the second printed circuit region. The seam region includes a first die seal and a second die seal spaced apart from one another with a scribe line located between the first die seal and the second die seal.

FIELD OF THE INVENTION

An embodiment relates to integrated circuit devices (“ICs”). More particularly, an embodiment relates to an oversized interposer for an IC.

BACKGROUND

Integrated circuits have become more “dense” over time, i.e., more logic features have been implemented in an IC. More recently, Stacked-Silicon Interconnect Technology (“SSIT”) allows for more than one semiconductor die to be placed in a single package. SSIT ICs may be used to address increased demand for having various ICs within a single package. However, even though ICs using SSIT have more than one die, such ICs still have significant restriction due to interposer size. Conventionally, an interposer has been limited due to maximum field size of a reticle of a lithographic scanner. Hence, it is desirable to provide a larger interposer that is not so restricted to a maximum scanner field size restriction.

SUMMARY

One or more embodiments generally relate to an oversized interposer.

An embodiment relates generally to an interposer. In such an embodiment, there are a first printed circuit region and a second printed circuit region. The second printed circuit region is proximate to the first printed circuit region with a first seam region between the first printed circuit region and the second printed circuit region. The first seam region includes a first die seal and a second die seal spaced apart from one another with a first scribe line located between the first die seal and the second die seal.

Another embodiment relates generally to a lithographic mask. In such an embodiment, an image region is divided into a first pattern region, a second pattern region, and a third pattern region. The first pattern region is for interconnecting a first portion of a first die to an interposer. The second pattern region is for interconnecting a second portion of the first die and a first portion of a second die to the interposer. The third pattern region is for interconnecting a second portion of the second die to the interposer. The second pattern region is repeatable for the interposer to have a length or a width greater than a maximum length or a maximum width, respectively, of a reticle field size of a lithographic scanner.

Yet another embodiment relates generally to a method for lithographically printing. A mask and a wafer with a resist layer are loaded in a lithographic scanner for creating an interposer. The mask has an image region divided into a first pattern region, a second pattern region, and a third pattern region. The third pattern region is shuttered off. The first pattern region and the second pattern region are imaged onto the resist layer to respectively print an instance of a first printed circuit region and a first instance of a second printed circuit region with an instance of a first seam region and a first instance of a second seam region respectively associated therewith. The first pattern region is shuttered off. The second pattern region and the third pattern region are imaged onto the resist layer to respectively print a second instance of the second printed circuit region with a second instance of the second seam region and an instance of a third printed circuit region. The second pattern region with the second seam region is repeatable for the interposer to have a length or width greater than a maximum length or a maximum width, respectively, of a reticle field size of the lithographic scanner.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth to provide a more thorough description of the specific embodiments. It should be apparent, however, to one skilled in the art, that one or more embodiments may be practiced without all the specific details given below. In other instances, well known features have not been described in detail so as not to obscure the one or more embodiments. For ease of illustration, the same number labels are used in different diagrams to refer to the same items; however, in alternative embodiments the items may be different.

Before describing exemplary embodiments illustratively depicted in the several figures, a general introduction is provided to further understanding.

A lithographic scanner has a reticle field size limitation. The limited size of the reticle field heretofore limited the size of an interposer that could be created. For example, a conventional scanner field size limit is 26 mm by 33 mm. However, larger interposers are needed in order to accommodate more and/or larger integrated circuit dies in order to improve performance and/or increase pin-count density. Larger scanner field sizes may be available, and thus it shall be assumed that a scanner field size limit is at least 26 mm by at least 33 mm.

With the above general understanding borne in mind, various embodiments for a larger interposer, as well as methodology for creating same, are generally described below. A larger interposer may be created using multistep imaging by effectively dividing interconnects of a modular die to be mounted onto an interposer into image slices (“slices”) and lithographically stitching the slices together. Such multistep imaging may use a multi-pattern region mask for creating an oversized interposer, namely an interposer having at least one dimension greater than a maximum reticle field size limit. By having double-seal seam regions, interconnect circuit slices of an interposer may be coupled to one another using die bridging. Along those lines, multiple slices may be imaged to create an interposer larger than at least one maximum dimension afforded by reticle field size of a lithographic scanner.

Because one or more of the above-described embodiments are exemplified using a particular type of IC, a detailed description of such an IC is provided below. However, it should be understood that other types of ICs may benefit from one or more of the embodiments described herein.

Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (“PIPs”). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.

Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (“I/O”) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (“PLAs”) and Programmable Array Logic (“PAL”) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration (programming) sequence.

As noted above, advanced FPGAs can include several different types of programmable logic blocks in the array. For example,FIG. 1illustrates an FPGA architecture100that includes a large number of different programmable tiles including multi-gigabit transceivers (“MGTs”)101, configurable logic blocks (“CLBs”)102, random access memory blocks (“BRAMs”)103, input/output blocks (“IOBs”)104, configuration and clocking logic (“CONFIG/CLOCKS”)105, digital signal processing blocks (“DSPs”)106, specialized input/output blocks (“I/O”)107(e.g., configuration ports and clock ports), and other programmable logic108such as digital clock managers, analog-to-digital converters, system monitoring logic, and so forth. Some FPGAs also include dedicated processor blocks (“PROC”)110.

Some FPGAs utilizing the architecture illustrated inFIG. 1include additional logic blocks that disrupt the regular columnar structure making up a large part of the FPGA. The additional logic blocks can be programmable blocks and/or dedicated logic. For example, processor block110spans several columns of CLBs and BRAMs. Note thatFIG. 1is intended to illustrate only an exemplary FPGA architecture. For example, the numbers of logic blocks in a row, the relative width of the rows, the number and order of rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect/logic implementations included at the top ofFIG. 1are purely exemplary. For example, in an actual FPGA more than one adjacent row of CLBs is typically included wherever the CLBs appear, to facilitate the efficient implementation of user logic, but the number of adjacent CLB rows varies with the overall size of the FPGA. An FPGA, such as FPGA100may be coupled to an interposer or carrier, as described below in additional detail. An aspect of such an interposer is that it may have 2 or more instances of the same die type. In an embodiment the repeated die are PLDs, such as FPGAs100for example, but the same techniques for multi-mask exposure and for signal bridging may be used for other die types, including without limitation DRAM, Flash Memory, image sensors, or high speed transceivers, among other types of die.

FIG. 2is a block diagram depicting an exemplary embodiment of a stacked die assembly200. Stacked die assembly200includes interposer205having coupled thereto IC die201and IC dies202-1through202-3. IC die201may be any type of IC die, including without limitation a memory die, a voltage regulator die, or a high-speed interface die, among other types of IC dies. For purposes of clarity by way of example and not limitation, it shall be assumed that IC die201is a high-speed serial I/O (“HSS I/O”) die; however, in other embodiments this or another type of IC die may be used. Furthermore, in other embodiments, more than one IC die201of same or differing type may be used. In yet other embodiments, different types of die may be used between one or more of IC dies202-1through202-3.

IC dies202-1through202-3may be any type of modularly architected repeatable die. For purposes of clarity by way of example not limitation, FPGA IC dies202-1through202-3are described; however, in other embodiments other types of modularly architected repeatable IC dies may be used.

FPGA IC dies202-1through202-3respectively bridge seam regions221,222-1, and222-2. Seam regions221,222-1, and222-2all have a “double seam” to take advantage of symmetry and of repeating nature of modular FPGA IC dies202-1through202-3. By a “double seal”, it is generally meant a seam region having two die seals, one on either side of the seam.

Interconnects between FPGA IC dies202-1through202-3, as well as between HSS I/O die201and one or more of FPGA IC dies202-1through202-3, may respectively be printed as separate circuit regions (“printed circuit regions”), namely with separate pattern regions as described below in additional detail. By repeated imaging of separate printed circuit regions, interposer205may have at least one dimension which is larger than a maximum dimension therefor allowed by a lithographic scanner reticle field size. In this embodiment, interposer205includes four printed circuit regions211,212-1,212-2, and213. In this exemplary embodiment, printed circuit region213includes seam region221, a slice231-1of interposer205-to-FPGA IC die202-1interconnects, interposer205-to-HSS I/O die201interconnects, and HSS I/O die201-to-FPGA IC die202-1interconnects, as well as interconnects for bridging seam region221and through substrate interconnects (not shown), among other interconnects. For purposes of clarity by way of example not limitation, it shall be assumed that interposer205is a silicon substrate based interposer, and thus through substrate interconnects are through substrate vias (“TSVs”). However, it should be understood that in other embodiments, interposer205may be a dielectric substrate based interposer or other semiconductor substrate based interposer.

Printed circuit regions212-1and212-2may be repeats of one another, namely printed circuit regions212. Each of printed circuit regions212includes interconnects for two FPGA die slices to be generally partially located in such regions when corresponding such FPGA dies are coupled to interposer205. In this exemplary embodiment, printed circuit region212-2includes seam region222-1, a slice231-2of interposer205-to-FPGA IC die202-2interconnects, a slice232-1of interposer205-to-FPGA IC die202-1interconnects, TSVs (not shown), and FPGA IC die202-1-to-FPGA IC die202-2interconnects, as well as any interconnects for bridging seam regions221and222-1, among other interconnects. In this exemplary embodiment, printed circuit region212-1includes seam region222-2, a slice231-3of interposer205-to-FPGA IC die202-3interconnects, a slice232-2of interposer205-to-FPGA IC die202-2interconnects, TSVs (not shown), and FPGA IC die202-2-to-FPGA IC die202-3interconnects, as well as any interconnects for bridging seam regions222-1and222-2, among other interconnects.

Printed circuit region211includes, a slice232-3of interposer205-to-FPGA IC die202-3interconnects, and TSVs (not shown), as well as any interconnects for bridging seam region222-2, among other interconnects.

For purposes of clarity by way of example and not limitation, presently conventionally a maximum lithographic reticle field size allows for an interposer to be formed with a width of 26 mm and a length of 33 mm. In an exemplary embodiment, interposer205is formed with a width of approximately 25 mm and a length of approximately 34.4 mm. However, in other embodiments, other dimensions may be used in accordance with the following description.

Either width215or length210may be formed to be larger than a conventional maximum lithographic reticle field size dimension associated therewith by multiple-step imaging as described below. Even though the following description is in terms of having length210larger than a conventional maximum lithographic reticle field size length dimension, in other embodiments width215may be larger than a conventional maximum lithographic reticle field size width dimension.

FIG. 3is a block diagram depicting an exemplary embodiment of a lithographic mask (“mask”)300. In this exemplary embodiment, mask300includes four pattern regions311through314of an image region310. Pattern regions312through313correspond to lithographically imaged (“printed”) circuit regions212and213, respectively, ofFIG. 2. Pattern region311corresponds to printed circuit region211ofFIG. 2. In this exemplary embodiment, pattern regions311and314are identical. However, in other embodiments, pattern regions311and314may be different.

Pattern region314includes an image pattern for interconnects of a slice of a die area302-3and for die seals and a scribe line of a seam region323. In one sense, such a scribe line is a dummy scribe line, as an interposer is not diced along such scribe line; however, for registration for lithographic imaging, such scribe line may be used. Pattern region313includes an image pattern for interconnects of a slice of die area302-1and die area301, as well as other interconnects as previously described herein with respect to printed circuit region213ofFIG. 2. Such image pattern for pattern region313further includes imaging for die seals and a scribe line for seam area322. Pattern region312includes an image pattern for interconnects of a slice of die area302-1and a slice of die area302-2, as well as other interconnects as previously described herein with respect to printed circuit region212ofFIG. 2. Such image pattern for pattern region312further includes imaging for die seals for seam area321. Lastly, pattern region311includes an image pattern for interconnects of a slice of die area302-2, as well as other interconnects as previously described herein with respect to printed circuit region211ofFIG. 2.

Seam areas, such as seam areas321through323, may be architected or otherwise designed for a minimum or no interposer traces crossing boundaries associated therewith. Making reliable connections across seam regions associated with seam areas321through323, namely at intersections of two shutter edges from two sequential mask exposures, may be problematic. Along those lines, a channel region may be defined or otherwise created without micro bumps and without traces to correspond to a shutter defined seam region on an interposer.

FIG. 11is a block/perspective diagram depicting an exemplary embodiment of a portion of stacked die assembly200. Stacked die assembly200in seam regions221,222-1, and222-2includes respective pairs of die seals with a scribe line disposed between such die seals. For example, with reference to seam region221, there are two spaced apart die seals1101with a scribe line1102located between such die seals1101. Seam region221may be devoid of any micro bumps and traces on an uppermost surface1150of interposer205.

Returning toFIG. 3, pattern region314includes seam area323, and pattern region311does not include a seam area. Likewise, printed circuit region211does not include a seam region. Because mask300may use multiple exposures of pattern regions of various sequences across a wafer, having both pattern regions311and314may be useful so as not having to perform extra exposure operations.

Region311has half of a “standard” scribe line325. Regions313and314are divided by a “standard” scribe line324. All regions have a “standard” scribe line326or327on the left and right edges, respectively. A “standard” scribe line is a designated line and associated line width used for cutting a wafer into individual die. All multiple exposure masks can end with a standard scribe on all four sides and not have a die seal on an outside edge.

FIG. 4is a block diagram depicting an exemplary embodiment of mask300ofFIG. 3with sections shuttered off, such as by a lithographic scanner in which mask300is loaded. For an operation400, pattern region311and pattern region314of mask300may be shuttered off to prevent lithographic imaging (“printing”) of those regions onto a resist layer on a wafer loaded in a lithographic scanner. Furthermore, for operation400, pattern regions313and312may be exposed to allow printing of those regions onto such a resist layer of such a wafer loaded in such a lithographic scanner. It should be understood that die areas are generally indicated for interconnects associated there with. In other words, such die areas generally indicate locations for interconnects for dies to be mounted to an interposer in such areas.

FIG. 5is a block diagram depicting an exemplary embodiment of mask300ofFIG. 3at a time later with respect toFIG. 4with sections shuttered off, such as the same lithographic scanner used for operation400. For an operation500, pattern regions313and314may be shuttered off to prevent printing of those regions onto such a resist layer on such wafer loaded in such a lithographic scanner, as previously described with reference toFIG. 4. Furthermore, for operation500, pattern regions311and312may be exposed to allow printing of those regions onto such a resist layer of such a wafer loaded in such lithographic scanner. Along those lines, it should be understood that printing of pattern region312is repeated in operation500with respect to such printing of such region in operation400. However, in operation500, such repeated printing of pattern region312is offset from printing of such region in operation400so as to form adjacent printings of pattern region312on a wafer.

Accordingly, by shuttering off one or more selected pattern regions of mask300, multiple configurations of interposers may be created. Furthermore, by shuttering off one or more selected pattern regions of mask300and performing multiple sequential exposures, multiple configurations of interposers having a dimension longer, or wider, than conventionally allowed by a lithographic scanner reticle field size may be created. Thus, the positioning of shutters and the number of mask exposures may be used to create one or more configurations of interposers.

For example, to create the exemplary embodiment of interposer205ofFIG. 2, shuttered mask300of operation400may be first exposed on a first row of a wafer in order to lithographically image (“print”) circuitry associated with pattern regions312and313without printing circuitry associated with pattern regions311and314. On a next row of such a wafer above such first row, operation500may be performed as a subsequent exposure to print circuitry on such wafer associated with pattern regions311and312without printing circuitry associated with pattern regions313and314. Along those lines, another row with pattern regions311and314shuttered may be exposed followed by yet another row with pattern regions313and314shuttered, and so on, to create multiple instances of interposer205on a wafer.

In this exemplary embodiment, pattern region314is not used to make interposer205, and thus pattern region314is optional. However, in an embodiment with a smaller version of interposer205, pattern region314may be used. For example, a subsequent operation400, namely an operation with pattern region311shuttered, may be performed to expose pattern region312to314onto a resist layer of a wafer, namely operation500with pattern region311shuttered and with pattern regions313and314exposed. In such an embodiment, pattern region312includes seam areas322and321. In some embodiments of a multiple die interposer configuration, an interposer height or length larger than a maximum dimension conventionally allowed by reticle field size of a lithographic scanner may be formed. However, not all embodiments of interposers made from mask300have to have a height or length larger than a maximum dimension conventionally allowed by reticle field size of a lithographic scanner. This facilitates use of a single mask300to accommodate a variety of configurations to accommodate various sales demands.

FIG. 6is a block diagram depicting an exemplary embodiment of an interposer600printed using mask300ofFIG. 3. In this exemplary embodiment, interposer600is created on a wafer601by sequential exposures with pattern regions313and314exposed with pattern regions311and312shuttered off. Interposer600may be a two IC die configuration as indicated in the shaded area thereof. Each interposer600may be imaged at this level using a single exposure. Interposer600may be suitable for high-volume production as cost may be reduced with reduce lithographic processing time.

FIG. 7is a block diagram depicting an exemplary embodiment of an interposer700printed using mask300ofFIG. 3. In this exemplary embodiment, interposer700is created on a wafer701by sequential exposures with pattern regions311through313exposed with pattern region314shuttered off. Interposer700may be a three IC die configuration as indicated in the shaded area thereof. Each interposer700may be imaged at this level using a single exposure. Interposer700may be suitable for high-volume production as cost may be reduced with reduce lithographic processing time.

FIG. 8is a block diagram depicting an exemplary embodiment of an interposer800printed using mask300ofFIG. 3. In this exemplary embodiment, interposer800is created on a wafer801by alternating sequential exposures with pattern regions312and313exposed with pattern regions311and314shuttered off for an exposure, followed by having pattern regions311and312expose with pattern regions313and314shuttered off for a subsequent exposure. Interposer800may be a four IC die configuration as indicated in the shaded area thereof.

Each interposer800may be imaged at this level using two exposures, namely one exposure with one shuttering configuration followed by another exposure with another shuttering configuration. Use of two exposures with two shuttering configurations, in contrast to a single exposure and a single shuttering configuration as described with reference to interposers600and700, increases processing time.

FIG. 9is a block diagram depicting an exemplary embodiment of an interposer900printed using mask300ofFIG. 3. In this exemplary embodiment, interposer900is created on a wafer901, which may be a silicon wafer or other semiconductor wafer. Creation of interposer900is an extension of interposer800as previously described with reference toFIG. 8, and thus is not described in unnecessary detail for purposes of clarity. Interposer900may be for a five IC die configuration as indicated in the shaded area thereof. Interposer900may be formed with three exposures thereof with two corresponding shutter settings.

FIG. 10is a block diagram depicting another exemplary embodiment of a stacked die assembly200having seam crossing interconnects1012-1and1012-2. Even though the number of signals crossing seam regions, such as seam regions221,222-1, and222-2, may involve a small number of traces as compared to all traces on an interposer205, such signals nevertheless may have to cross seam regions.

With respect to FPGA IC dies202-1,202-2, and202-3, such signals crossing seam regions may include configuration and/or JTAG signals. For purposes of clarity by way of example not limitation, it shall be assumed that signals crossing seam regions are configuration signals, even though these or other types of signals may cross seam regions.

For example, signals beginning from a configuration module1011-1of FPGA IC die202-1may travel via interconnect1012-1to a configuration module1011-2of FPGA IC die202-2and to a configuration module1011-3of FPGA IC die202-3. Such signals may travel across seam regions221and222-1. Accordingly, micro bumps may be place outside opposing sides of seam regions for interconnecting to passive traces in FPGA IC dies202-1,202-2and202-3for bridging such seam regions.

Returning toFIG. 11, where there is shown a block/perspective diagram depicting an exemplary embodiment of a portion of stacked die assembly200, FPGA IC dies201-1,202-2, and202-3include configuration modules1011-1,1011-2, and1011-3, respectively. Configuration modules1011-1,1011-2, and1011-3are interconnected to traces1103on an upper most surface of1150of interposer205with micro bumps1104and passive traces1111-1,1111-2, and1111-3, respectively, of FPGA IC dies202-1,202-2, and202-3. Such micro bumps, interposer traces and die traces may provide interconnects1012-1and1012-2ofFIG. 10. Micro bumps1104are disposed on opposing sides of seam regions221,222-1, and222-2. Accordingly, by routing signals up to passive traces1111-1,1111-2, and1111-3of FPGA IC dies201-1,202-2, and202-3, respectively, seam regions221,222-1, and222-2may respectively be bridged.

FIG. 12is a block/circuit diagram depicting an exemplary embodiment of a repeatable die1200. Repeatable die1200includes traces for die area interconnects1210. Die area interconnects1210includes interconnects1201, module interconnects1202, and interconnects1203. Module interconnects1202may be for a configuration module1011or other IC module. For purposes of clarity by way of example and not limitation, it shall be assumed that module interconnects1202are for a configuration module1011. A signal of configuration module1011may be a chip select signal (“CS”). Even though a chip select signal is illustratively depicted, any type of signal may be used. Furthermore, interconnects1203may be for passive traces in an FPGA IC die202for bridging a seam region, as described below in additional detail. Repeatable die1200may be a die that matches a pattern made by regions311and312of mask300on interposer1300ofFIG. 13.

FIG. 13is a block diagram/circuit depicting an exemplary embodiment of a multi-section interconnect mask1300. Multi-section interconnect mask1300includes pattern section1301through pattern section1304. Pattern section1301includes interconnects1311. Pattern section1302includes images for interconnects1312. Pattern section1303includes images for interconnects1313, and pattern section1304includes images for interconnects1314.

Assuming module interconnects1202are for an FPGA IC die, as previously described, an interposer may have interconnects for each FPGA IC die created using multi-step exposures of a single multi-section interconnect mask1300, as described below in additional detail.

FIG. 14is a block diagram depicting an exemplary embodiment of a stacked die assembly1400having an interposer205printed with multi-section interconnect mask1300ofFIG. 13and repeatable die1200. Stacked die assembly1400further includes FPGA IC dies202-1through202-5coupled to interposer205, where FPGA IC dies202-1through202-5respectively include configuration modules1011-1through1011-5. Traces in interconnects which may be under or within FPGA IC dies202-1through202-5, as well as configuration modules thereof, are illustratively depicted along with traces and interconnects of interposer205for purposes of clarity.

Repeated placement of repeatable die1200may be as previously described. In this embodiment, FPGA IC dies202-1through202-5respectively bridge seam regions221-1through222-5formed between interposer mask exposure regions1302through1304.

By use of pattern section1302, interconnects for FPGA IC die202-1on interposer205may be created, where a CS port associated with configuration module1011-1is tied to a logic high voltage to indicate such configuration module is a master module. Such interconnects for FPGA IC die202-1on interposer205may further be created by use of pattern section1302for initial routing of configuration signals to be passed to CS ports of configuration modules1011-2through1011-5.

By repeated use of pattern section1303, such configuration signals on interposer202may effectively be successively passed or bussed to configuration modules1011-2through1011-5. Additionally, by repeated use of pattern section1303, FPGA IC die-to-die interconnects may be formed. Furthermore, configuration modules1011-2through1011-5may be identified as slave modules with respect to configuration module1011-1having a CS port tied to a logic high supply level1410. Use of technology for forming a stacked die assembly1400allows all identical die202to have a unique hook-up using an interposer made from repeated exposure of the same mask region1303and resulting metallization patterns.

Along those lines, a pattern region of a mask, such as pattern region312of mask300ofFIG. 3for example, effectively may be amended by application of pattern section1303for example, to create various configurations of interposers. Again, even though a master-slave arrangement among FPGA IC dies is illustratively depicted, it should be understood that by using various configurations of mask interconnect sections, different associations may be obtained from a single mask. End connections of such configuration bus may be formed using pattern section1301or1304, where each such unused end1412may be coupled to ground1411so as not to be floating.

FIG. 15is a block diagram depicting an exemplary embodiment of a conventional lithographic scanner1500. Loaded into lithographic scanner1500are wafer1501and mask1502. Wafer1501may have a resist layer1503.

FIG. 16is a flow diagram depicting an exemplary embodiment of a lithographic imaging (“printing”) flow1600for printing onto a resist layer of a wafer used to provide at least one interposer. Printing flow1600is described with simultaneous reference toFIGS. 1 through 16.

At1601, a mask, such as mask300for example, and a wafer, such as wafer1501for example, is loaded into a lithographic scanner, such as lithographic scanner1500for example. Wafer1501may have a resist layer1503. Furthermore, such mask300may have an image region310divided into the plurality of pattern regions, such as pattern regions311through314for example. Such plurality of pattern regions may include a first pattern region, a second pattern region, and a third pattern region, such as previously described herein for example with reference to pattern regions311through313.

At1602, a third pattern region of such mask is shuttered off in the lithographic scanner. At1603, the first pattern region and the second pattern region may be imaged onto the resist layer to respectively print an instance of a first printed circuit region and a first instance of a second printed circuit region, respectively. With such printing of an instance of the first printed circuit region, an instance of a first seam region, such as seam region221, may be printed. Likewise, with such printing of a first instance of the second printed circuit region, a first instance of the second seam region, such as a seam region222, may be printed.

At1604, the first pattern region and the third pattern region may be shuttered off in the lithographic scanner. At1605, the second pattern region may be again imaged onto the resist layer, though at a different location, to print a second instance of the second printed circuit region with a second instance of the second seam region. Such printing may cause the first instance of the second printed circuit region to order the second instance of the second printed circuit region, where the first instance of the second seam region is generally located between the first and second instances of the second printed circuit region. Along those lines, multiple iterations of printing instances of the second printed circuit region may be repeated for a number of die slices.

Once a number of die slices have been printed, at1606the first pattern region may be shuttered off in the lithographic scanner. At1607, the second pattern region and the third pattern region may be imaged onto the resist layer to respectively print an nth instance of the second pattern circuit region with an nth instance of the second seam region and an instance of a third printed circuit region, respectively. Accordingly, formation of multiple interposers from a single mask set has been described. Such interposers may be formed with at least one dimension larger than available from a conventional maximum reticle field size limit of a lithographic scanner. By using one mask with multiple pattern regions or sections, more efficiency in fabricating interposers may be obtained than having multiple masks which have to be stored in and/or changed out. In other words, handling multiple masks for a product involves changing masks and realigning masks, which may be avoided by having a single mask with multiple pattern regions or sections.

In addition to having formed long interposers, various configurations of such interposers may be formed using a single mask having multiple pattern regions or sections. Even though the above description was in terms of height or length, again it should be understood that either or both height or width may exceed maximum dimensions associated with a conventional reticle field size limit. Furthermore, because various configurations may be formed using a single mask, interposer configurations which heretofore may have not been cost-effective to manufacture due to low volume, may now be manufactured by effectively leveraging volumes associated with other configurations formed using such a single mask. Moreover, such masks may have various interconnect structures for creating uniqueness or other form of differentiation among dies on an interposer, such as for master-slave, identification, or other form of differentiation.

While the foregoing describes exemplary embodiments, other and further embodiments in accordance with the one or more aspects may be devised without departing from the scope thereof, which is determined by the claims that follow and equivalents thereof. Claims listing steps do not imply any order of the steps. Trademarks are the property of their respective owners.