Voltage generator

According to one embodiment, a voltage generator includes a step-up circuit and a limiter circuit. The step-up circuit outputs a first voltage to a first node. The limiter circuit includes first and second resistive elements, first and second capacitive elements, a switch element, and a comparator. The first resistive element is between the first node and a second node. The second resistive element is connected to the second node. The first capacitive element is between the first and second nodes. The switch element connects the second capacitive element to the second node at the same time that the first node is connected to a load. The comparator compares the potential at the second node with a reference potential.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2012-016707, filed Jan. 30, 2012, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate generally to a voltage generator.

BACKGROUND

In a nonvolatile semiconductor memory, the stability of a stepped-up potential is important.

DETAILED DESCRIPTION

In general, according to one embodiment, a voltage generator includes: a step-up circuit; and a limiter circuit. The step-up circuit outputs a first voltage to a first node. The limiter circuit monitors a voltage at the first node and controls the step-up circuit. The limiter circuit includes: a first resistive element; a second resistive element; a first capacitive element; a second capacitive element; a first switch element; and a comparator. The first resistive element has one end connected to the first node and other end connected to a second node. The second resistive element has one end connected to the second node. The first capacitive element has one electrode connected to the first node and other electrode connected to the second node. The first switch element connects the second capacitive element to the second node at the same time that the first node is connected to a load. The comparator compares the potential at the second node with a reference potential and controls the step-up circuit according to the comparison result.

A voltage generator and a semiconductor memory device according to a first embodiment will be explained. Hereinafter, a semiconductor memory device will be explained, taking as an example a three-dimensional stacked NAND flash memory where memory cells are stacked above a semiconductor substrate.

1. Configuration of Semiconductor Memory Device

First, the configuration of a semiconductor memory device according to the first embodiment will be explained.

1.1 Overall Configuration of Semiconductor Memory Device

FIG. 1is a block diagram of a semiconductor memory device according to the first embodiment. As shown inFIG. 1, a NAND flash memory1includes a memory cell array10, a decode module11, a sense amplifier12, a voltage generator13, a control circuit14, and a clock generator15.

Memory cell array10includes a plurality of (four in the embodiment) blocks BLKs (BLK0to BLK3) each being a set of nonvolatile memory cells. Data in the same block BLK is erased simultaneously. Each of blocks BLKs includes a plurality of (four in the embodiment) memory groups GPs (GP0to GP3) each being a set of NAND strings16where memory cells are connected in series. Of course, the number of blocks in memory cell array10and the number of memory groups in each block BLK are both arbitrary.

Clock generator15generates a clock CLK.

Control circuit14, which operates in synchronism with clock CLK, controls the operation of the entire NAND flash memory.

Under the control of control circuit14, voltage generator13generates voltages necessary to write data, read data, and erase data.

Decode module11includes row decoders17(17-0to17-3) associated with blocks BLK0to BLK3, respectively. Each of row decoders17selects a row direction of the associated block BLK and applies a necessary voltage to a memory cell in writing, reading, or erasing data.

Sense amplifier12senses and amplifies data read from a memory cell in reading data. When writing data, sense amplifier12transfers write-data to a memory cell.

Next, a detailed configuration of memory cell array10will be explained.FIG. 2is a circuit diagram of block BLK0. Each of blocks BLK1to BLK3has the same configuration.

As shown inFIG. 2, block BLK0includes four memory groups GPs. Each of memory groups GPs includes n (n being a natural number) NAND strings16.

Each of NAND strings16includes, for example, eight memory cell transistors MTs (MT0to MT7), select transistors ST1and ST2, and a back-gate transistor BT. Each of memory cell transistors MTs, which includes a stacked gate including a control gate and a charge accumulation layer, holds data in a nonvolatile manner. The number of memory cell transistors MTs is not limited to eight and may be 16, 32, 64, or 128. That is, the number is nonrestrictive. Like memory cell transistor MT, back-gate transistor BT includes a stacked gate including a control gate and a charge accumulation layer. Back-gate transistor BT is not for holding data and functions as just a current path in writing or erasing data. Memory cell transistors MTs and back-gate transistor BT are arranged between select transistors ST1and ST2in such a manner that their current paths are connected in series. Back-gate transistor BT is provided between memory cell transistors MT3and MT4. The current path of memory cell transistor MT7at one end of the series connection is connected to one end of the current path of select transistor ST1. The current path of memory cell transistor MT0at the other end is connected to one end of the current path of select transistor ST2.

The gate of select transistor ST1of each of memory groups GP0to GP3is connected to the associated one of select gate lines SGD0to SGD3in a common connection manner. The gate of select transistor ST2of each of memory groups GP0to GP3is connected to the associated one of select gate lines SGS0to SGS3in a common connection manner. In contrast, the control gates of memory cell transistors MT0to MT7in the same block BLK0are connected to word lines WL0to WL7, respectively, in a common connection manner. The control gate of back-gate transistor BT is connected to a back-gate line BG in a common connection manner (that is, the control gates of back-gate transistors BT in blocks BLK0to BLK3are connected to BG0to BG3, respectively).

Specifically, word lines WL0to WL7and back-gate line BG are shared by memory groups GP0to GP3in a common connection manner in the same block BLK0, whereas select gate lines SGD, SGS are independent of those in each of memory groups GP0to GP3even in the same block BLK0.

Of the NAND strings16arranged in a matrix in the memory cell array10, the other ends of the current paths of select transistors ST1of NAND strings16in the same row are connected to any one of bit lines (BL0to BLn, n being a natural number) in a common connection manner. That is, a bit line BL connects NAND strings16between a plurality of blocks BLKs in a common connection manner. The other ends of the current paths of select transistors ST2are connected to a source line SL in a common connection manner. Source line SL connects NAND strings16between, for example, a plurality of blocks in a common connection manner.

As described above, data in memory cell transistors MTs in the same block BLK is erased en bloc. In contrast, data is read from or written into, en bloc, a plurality of memory cell transistors MTs connected to any one of word lines WLs in any one of memory groups GPs in any one of blocks BLKs. This unit is called a page.

Next, a three-dimensional stacked structure of memory cell array10will be explained with reference toFIGS. 3 and 4.FIG. 3is a perspective view of memory cell array10.FIG. 4is a sectional view of memory cell array10.

As shown inFIGS. 3 and 4, memory cell array10is provided above a semiconductor substrate20. Memory cell array10includes a back-gate transistor layer L1, a memory cell transistor layer L2, a select transistor layer L3, and an interconnect layer L4formed sequentially on the semiconductor substrate20.

Back-gate transistor layer L1functions as a back-gate transistor BT. Memory cell transistor layer L2functions as memory cell transistors MT0to MT7(NAND strings16). Select transistor layer L3functions as select transistors ST1and ST2. Interconnect layer L4functions as source lines SLs and bit lines BLs.

Back-gate transistor layer L1includes a back-gate conducting layer21. Back-gate conducting layer21is formed so as to expand in a row and a column direction parallel to semiconductor substrate20. Back-gate conducting layer21is segmented block BLK by block BLK. Back-gate conducting layer21is made of, for example, polysilicon. Back-gate conducting layer21functions as a back-gate line BG.

In addition, back-gate conducting layer21has a back-gate hole22in it as shown inFIG. 4. Back-gate hole22is made so as to recess back-gate conducting layer21. Back-gate hole22is made so as be almost rectangular in the column direction as a longitudinal direction when viewed from above.

Memory cell transistor layer L2is formed on back-gate conducting layer L1. Memory cell transistor layer L2includes word line conducting layers23ato23d. Word line conducting layers23ato23dare stacked one on top of another, with interlayer insulating layers (not shown) interposed therebetween. Word line conducting layers23ato23dare formed into stripes extending in the row direction with a specific pitch in the column direction. Word line conducting layers23ato23dare made of, for example, polysilicon. Word line conducting layer23afunctions as control gates (word lines WL3and WL4) of memory cell transistors MT3and MT4, word line conducting layer23bfunctions as control gates (word lines WL2and WL5) of memory cell transistors MT2and MT5, word line conducting layer23cfunctions as control gates (word lines WL1and WL6) of memory cell transistors MT1and MT6, and word line conducting layer23dfunctions as control gates (word lines WL0and WL7) of memory cell transistors MT0and MT7.

As shown inFIG. 4, memory cell transistor layer L2has a memory hole24in it. Memory hole24is made to extend through word line conducting layers23ato23d. Memory hole24is made to align with the end portion of back-gate hole22in the column direction.

Furthermore, as shown inFIG. 4, back-gate transistor layer L1and memory cell transistor layer L2include a block insulating layer25a, a charge accumulation layer25b, a tunnel insulating layer25c, and a semiconductor layer26. Semiconductor layer26functions as a body (or a back-gate of each transistor) of NAND string16.

As shown inFIG. 4, block insulating layer25ais formed to a specific thickness on the sidewall facing back-gate hole22and memory hole25. Charge accumulation layer25bis formed to a specific thickness on the side of block insulating layer25a. Tunnel insulating layer25cis formed to a specific thickness on the side of charge accumulation layer25b. Semiconductor layer26is formed so as to contact the sidewall of tunnel insulating layer25c. Semiconductor layer26is formed so as to fill back-gate hole22and memory hole24.

Semiconductor layer26is formed into a U-shape when viewed from the row direction. That is, semiconductor layer26includes a pair of columnar parts26aextending perpendicular to the surface of semiconductor substrate20and a connecting part26bthat connects the lower ends of the pair of columnar parts26a.

Block insulating layer25aand tunnel insulating layer25care made of, for example, silicon oxide (SiO2). Charge accumulation layer25bis made of, for example, silicon nitride (SiN). Semiconductor layer26is made of polysilicon. Block insulating layer25a, charge accumulation layer25b, tunnel insulating layer25c, and semiconductor layer26form a MONOS transistor that functions as a memory cell transistor MT.

In other words, back-gate transistor layer L1is so configured that tunnel insulating layer25cis formed so as to surround connecting part26band that back-gate conducting layer21is formed so as to surround connecting part26b.

Furthermore, memory cell transistor layer L2is so configured that tunnel insulating layer25cis formed so as to surround columnar part26a, charge accumulation layer25bis formed so as to surround tunnel insulating layer25c, block insulating layer25ais formed so as to surround charge accumulation layer25b, and word line conducting layers23ato23dare formed so as to surround block insulating layers25ato25cand columnar part26a.

As shown inFIGS. 3 and 4, select transistor layer L3includes conducting layers27aand27b. Conducting layers27aand27bare formed into stripes extending in the row direction with a specific pitch in the column direction. A pair of conducting layers27aand a pair of conducting layers27bare arranged alternately in the column direction. Conducting layer27ais formed on one columnar part26aand conducting layer27bis formed on the other columnar layer26a.

Conducting layers27aand27bare made of polysilicon. Conducting layer27afunctions as the gate (select gate line SGS) of select transistor ST2. Conducting layer27bfunctions as the gate (select gate line SGD) of select transistor ST1.

Select transistor layer L3has holes28aand28bin it as shown inFIG. 4. Holes28aand28brespectively extend through conducting layers27aand27b. Holes28aand28balign with memory hole24.

As shown inFIG. 4, select transistor layer L3includes gate insulating layers29aand29b, and semiconductor layers30aand30b. Gate insulating layers29aand29bare formed on the sidewalls facing holes28aand28b, respectively. Semiconductor layers30aand30bare formed into columnar shapes extending in a direction perpendicular to the surface of semiconductor substrate30so as to contact gate insulating layers29aand29b, respectively.

In other words, select transistor layer L3is so configured that gate insulating layer29ais formed so as to surround columnar semiconductor layer30a, conducting layer27ais formed so as to surround gate insulating layer29aand semiconductor layer30a, gate insulating layer29bis formed so as to surround columnar semiconductor layer30b, and conducting layer27bis formed so as to surround gate insulating layer29band semiconductor layer30b.

Interconnect layer L4is formed on select transistor layer L3as shown inFIGS. 3 and 4. Interconnect layer L4includes a source line layer31, a plug layer32, and a bit line layer33. Source line layer31is formed into a plate extending in the row direction. Source line layer31is formed in contact with the upper surfaces of a pair of semiconductor layers27aadjacent to each other in the column direction. Plug layer32is formed in contact with the upper surfaces of semiconductor layer27band extends in a direction perpendicular to the surface of semiconductor substrate20. Bit line layers33are formed into stripes extending in the column direction with a specific pitch in the row direction. Bit line layers33are formed so as to contact the top surface of plug layer32. Source line layer31, plug layer32, and bit line layers33are made of, for example, such metal as tungsten (W). Source line layer31functions as source line SL explained inFIGS. 1 and 2. Bit line layers33function as bit lines BLs.

FIG. 5shows an equivalent circuit of NAND string16shown inFIGS. 3 and 4. As shown inFIG. 5, NAND string16includes select transistors ST1and ST2, memory cell transistors MT0to MT7, and a back-gate transistor BT. As described above, memory cell transistors MTs are connected in series between select transistors ST1and ST2. Back-gate transistor BT is connected in series between memory cell transistors MT3and MT4. In writing or reading data, back-gate transistor BT is always kept on.

The control gate of memory cell transistor MT is connected to a word line WL. The control gate of back-gate transistor BT is connected to a back-gate line BG. A set of a plurality of NAND strings16arranged in the row direction inFIG. 3corresponds to a memory group GP explained inFIG. 2.

Next, a configuration of row decoder17will be explained. Row decoders17-0to17-3are provided and associated with blocks BLK0to BLK3respectively to select or unselect blocks BLK0to BLK3. Each of the row decoders17-0to17-3transfers a voltage generated by the voltage generator13to the word lines and select gate lines SGD, SGS in the associated block BLK.

FIG. 6is a circuit diagram of row decoder17associated with any one of blocks BLK and a voltage generation circuit included in voltage generator13. As shown inFIG. 6, row decoder17includes high-voltage n-channel MOS transistors40to42.

Transistors40are associated with word lines WL0to WL7respectively and transfer a voltage to the associated word lines WLs. That is, one end of the current path of each of transistors40is connected to one of word lines WL0to WL7in the associated block BLK. The other end of the current path is connected to the one of signal lines CG0to CG7. The gates of transistors40are connected to a signal line TG in a common connection manner.

Transistors41and42transfer voltages to select gate lines SGD and SGS, respectively. One end of the current path of transistor41is connected to select gate line SGD in the associated block BLK and the other end is connected to signal line SGDI. One end of the current path of transistor42is connected to select gate line SGS in the associated block BLK and the other end is connected to signal line SGSI. The gates of transistors41and42are connected to the signal line TG in a common connection manner.

In each row decoder17, transistors40are shared by a plurality of memory groups GPs in the associated block BLK. For example, in row decoder17-0, a transistor40associated with word line WL0is connected to word lines WL0in four memory groups GP0to GP3. On the other hand, transistors41and42are independent of those in another memory group from one memory group to another. That is, although only one transistor41and one transistor42are shown inFIG. 6, four transistors41and four transistors42are provided so as to be associated with memory groups GP0to GP3.

Row decoder17further includes a driver circuit (not shown). The driver circuit supplies voltages to signal lines SGDI, SGSI. In addition, row decoder17includes a switch (not shown). With this switch, a necessary voltage is applied to signal lines CG0to CG7. Just for reference,FIG. 6shows the way the same voltage is applied to signal lines CG0to CG7by means of a switch.

Furthermore, for example, signal WLCON_V is supplied from control circuit14to signal line TG. Signal WLCON_V is asserted, turning on transistors40to42. This causes a voltage generated by the voltage generator13to be transferred to a word line WL. A specific voltage is transferred to select gate lines SGD, SGS.

Next, a configuration of voltage generator13will be explained with reference toFIG. 6. Voltage generator13includes a plurality of voltage generation modules50. Each of modules50generates voltages necessary to write, read, or erase data, including VPGM, VPASS, VREAD, VCGR, and VERA.

Voltage VPGM is a voltage applied to the selected word line in writing data. Voltage VPASS is a voltage applied to the unselected word lines in the selected block in writing data. Voltage VPASS turns on a memory cell transistor MT, regardless of whether the memory cell transistor holds data. Voltage VCGR is a voltage applied to the selected word line in reading data. Voltage VERA is a voltage applied to a bit line and/or a source line in erasing data.

Hereinafter, where there is no need to distinguish between those voltages, they will be collectively called the output voltage VCP of a voltage generation module50. AlthoughFIG. 6shows only one voltage generation module50, voltage generator13includes a plurality of voltage generation modules50that generate the aforementioned individual voltages. The switch (not shown) in row decoder17connects the corresponding one of voltage generation modules50to one of signal lines CG0to CG7.

As shown inFIG. 6, each of voltage generation modules50includes a charge pump circuit60, a limiter circuit70, and a limiter controller80.

Charge pump circuit60receives signal HVENBV supplied from, for example, control circuit14, thereby being enabled. Then, having received a clock CLK, charge pump circuit60steps up a voltage. Charge pump circuit60then outputs the stepped-up voltage to a node CP_OUT. The voltage at node CP_OUT is output as a stepped-up voltage VCP (specifically, VPGM, VPASS, VREAD, or the like) from voltage generation module50.

Limiter circuit70monitors the potential at node CP_OUT to generate a flag FLAG and controls charge pump circuit60so that voltage VCP may reach a desired value. As shown inFIG. 6, limiter circuit70includes a comparator71, resistive elements72and73, capacitive elements74and75, and an n-channel MOS transistor76.

One end of resistive element72is connected to node CP_OUT and the other end of it is connected to node MON. One end of resistive element73is connected to node MON and the other end of it is grounded. One electrode of capacitive element74is connected to node CP_OUT and the other electrode of it is connected to node MON. Transistor76has its drain connected to node MON and its source connected to one electrode of capacitive element75. A signal CONNECTC is input to the gate of transistor76. Transistor76is a low-withstand-voltage MOS transistor. For example, the gate insulating film of transistor76is thinner than that of high-withstand-voltage MOS transistor40in the row decoder17. The other electrode of capacitive element75is grounded. Comparator71includes an inverting input terminal to which a voltage Vmon at node MON is input, a noninverting input terminal to which a reference voltage Vref is input, and an output terminal that outputs a flag FLAG according to the result of comparison between Vmon and Vref.

With the above configuration, limiter circuit70controls charge pump circuit60by flag FLAG. Specifically, when Vref is higher than Vmon, FLAG is set (FLAG=High), stepping up the voltage of charge pump circuit60. In contrast, when Vref is lower than Vmon, FLAG is cleared (FLAG=Low), stopping the step-up of the voltage of the charge pump circuit60.

Limiter controller80generates a signal CONNECTC according to clock CLK and signal WLCON_V. Limiter controller80turns on transistor76the instant transistor40of row decoder17connects voltage generation module50to a word line WL. As shown inFIG. 6, limiter controller80includes a controller81and an exclusive OR (XOR) gate82.

Controller81receives a clock CLK at a clock input terminal and a signal WLCON_V at an enable terminal ENB and outputs an output signal at output terminal OUT. XOR gate82executes XOR operation of signal WLCON_V and the output signal of the controller81, and outputs the result as signal CONNECTC.

FIG. 7is a circuit diagram of controller81. As shown inFIG. 7, controller81includes an AND gate83, NOR gates84and85, an inverter86, and flip-flops (D-F/Fs)87to89.

AND gate receives clock CLK at the clock terminal, signal WLCON_V at the enable terminal ENB, and an inversion signal of the output signal at the output terminal OUT, and executes AND operation of CLK, WLCON_V, and the inversion signal. In flip-flop87, a reset terminal is connected to enable terminal ENB. Flip-flop87receives the output signal of AND gate83as a clock. Inverting output terminal Qn of flip-flop87is connected to input terminal D of flip-flop87. In flip-flop88, a reset terminal is connected to enable terminal ENB. Flip-flop88receives the signal from terminal Qn of flip-flop87as a clock. Inverting output terminal Qn of flip-flop88is connected to input terminal D of flip-flop88. In flip-flop89, a reset terminal is connected to enable terminal ENB. Flip-flop89receives the signal from terminal Qn of flip-flop88as a clock. Inverting output terminal Qn of flip-flop89is connected to input terminal D of flip-flop89. NOR gate84executes NOR operation of the signal from output terminal Q of flip-flop89and the signal from output terminal OUT. Inverter86inverts signal WLCON_V. NOR gate85executes NOR operation of the operation result of NOR gate84and the operation result of inverter86. The operation result of NOR gate85is output at output terminal OUT.

An inverted clock CLKn is input to the gate of transistor94and a clock CLK is input to the gate of transistor98. One end of the current path of transistors94and98is connected to input terminal D. NAND gate90executes NAND operation of a signal at the other end of the current path of transistors94and98and the signal at terminal ENS. Inverter92inverts the operation result of NAND gate90. CLK is input to the gate of transistor95and CLKn is input to the gate of transistor59. One end of the current path of transistors95and99is connected to the other end of the current path of transistors94and98. CLK is input to the gate of transistor96and CLKn is input to the gate of transistor100. One end of the current path of transistors96and100is connected to the output of inverter92and to the other end of the current path of transistors95and99. NAND gate91executes NAND operation of a signal at the other end of the current path of transistors96and100and the signal at terminal ENB. Inverter93inverts the operation result of NAND gate91. CLKn is input to the gate of transistor97and CLK is input to the gate of transistor101. One end of the current path of transistors97and101is connected to the other end of the current path of transistors96and100.

With the above configuration, the output of inverter93makes terminal Q and the output terminal of NAND gate91makes terminal Qn.

FIG. 9is a timing chart to explain an operation of each of flip-flops87to89, showing signals at terminal ENB, terminal D (Qn), and terminal Q and a clock CLK. As described above, the signal at terminal ENB is WLCON_V. As shown inFIG. 9, each of flip-flops87to89detects a falling edge of clock CLK. A signal that rises or falls at the falling edge of the CLK is output at terminal Q or Qn.

Controller81is configured to have the aforementioned flip-flops connected in series, thereby functioning as a delay circuit. The length of delay time can be changed arbitrarily by changing the number of stages of flip-flops, the frequency of CLK, or flip-flops that input an output signal to the NOR gate84.

2. Operation of Semiconductor Memory Device1

Next, an operation of the NAND flash memory configured as described above will be explained. First, a write operation and a read operation will be explained briefly.

2.1 Write Operation

First, a write operation will be explained. In a write operation, voltage generation module50generates voltages VPGM and VPASS.

In row decoder17associated with the selected block, signal WLCON_V is asserted (made high). Then, signal line CG associated with the selected word line is connected to node CP_OUT of voltage generation module50that generates VPGM. Signal lines CGs associated with the unselected word lines are connected to node CP_OUT of voltage generation module50that generates VPASS. In addition, 0 V is transferred to select gate line SGS and voltage VSG is transferred to select gate line SGD.

Then, sense amplifier12applies a specific voltage to a bit line BL. In a column where data is to be programmed, select transistor ST1is turned on, causing program-data to be transferred to the selected memory cell transistor. As a result, charge is injected into the charge accumulation layer, thereby programming data. In contrast, in a column where data is not to be programmed, a high voltage is applied to bit line BL, cutting off select transistor ST1. This makes the channel potential of NAND string16in the column electrically floating, with the result that the potential rises by coupling with a word line WL. As a result, charge is not injected into the charge accumulation layer, preventing data from being programmed.

2.2 Read Operation

Next, a read operation will be explained. In a read operation, voltage generation module50generates voltages VCGR and VREAD.

In row decoder17associated with the selected block, signal WLCON_V is asserted (made high). Then, signal line CG associated with the selected word line is connected to node CP_OUT of voltage generation module50that generates VCGR. Signal lines CGs associated with the unselected word lines are connected to node CP_OUT of voltage generation module50that generates VREAD. In addition, voltage VH is transferred to select gate lines SGD and SGS. Voltage VH is a voltage that turns on select transistors ST1and ST2.

Then, sense amplifier12applies a specific voltage to a bit line BL. If the selected memory cell transistor MT goes on, current flows from bit line BL to source line SL. In contrast, if the selected memory cell transistor MT goes off, no current flows from bit line BL to source line SL. Sense amplifier12determines the read data by sensing the current.

2.3 Operation of Voltage Generation Module50

Next, an operation of voltage generation module50in the write operation or read operation (also or an erase operation) will be explained with reference toFIG. 10.FIG. 10is a timing chart for voltage VCP (VPASS in the embodiment), the potential of an unselected word line, signals HVENB_V, WLCON_V, and CONNECTC in a write operation.

As shown inFIG. 10, at time t20, for example, control circuit14asserts (or makes high) signal HVENB_V, starting up charge pump circuit60. The charge pump circuit60steps-up a voltage and outputs a voltage VCP to node CP_OUT.

After voltage VCP has risen gradually and reached voltage VPASS, control circuit14asserts (or makes high) signal WLCON_V at time t21. At the same time that signal WLCON_V is asserted, limiter controller80asserts (or makes high) signal CONNECTC. When signal WLCON_V has been asserted, this connects node CP_OUT of voltage generation module50that generates VPASS to the unselected word line WL. As a result, the potential of the unselected word line rises and reaches voltage VPASS. In addition, voltage VCP drops sharply from VPASS the instant node CP_OUT is connected to a word line WL. After that, the voltage rises again and reaches VPASS. The period during which signal CONNECTC is asserted is, for example, about 0.8 μs. Signal CONNECTC is negated (or made low) before VCP returns to VPASS after having dropped sharply at time t21.

When the writing of data has been completed (at time t22), signal WLCON_V is negated (or made low), setting the unselected word line WL to 0 V.

InFIG. 10, voltage VPASS has been taken as an example. The same holds true for other voltages, including VPGM and VREAD.

3. Effects of the First Embodiment

With the configuration of the first embodiment, a stepped-up voltage can be made more stable and therefore the operation reliability of the NAND flash memory can be improved. This effect will be explained below.

In a high-voltage analog system, a desired high voltage is generated using a regulator circuit. Generally, a regulator detects a set voltage and controls a clock of a step-up circuit according to the detection result. The regulator includes a resistive divider and a differential amplifier. A reference voltage and a bias voltage are generated by a low-voltage analog system.

Generally, a regulator circuit is so configured that capacitive elements74and75and transistor76are eliminated in the limiter circuit70ofFIG. 6. With this configuration, the following problem arises: a part Idc of the direct-current component of current lout output from the charge pump circuit60to node CP_OUT flows into resistive element72. Therefore, only amounts of (Iout-Idc) can be used to charge a word line WL. Accordingly, it is preferable to make Idc smaller. To achieve this, it is necessary to increase the resistances of resistive elements72and73.

Unfortunately, when the size of resistive element72is made larger to increase the resistance of resistive element72, the capacitance between resistive element72and the semiconductor substrate also increases, making an RC delay larger. As a result, the following response of Vmon to CPout deteriorates, decreasing the stability of CPout near a regulation level, which results in an increase in the ripple of the stepped-up potential.

Therefore, use of capacitive element74enables an AC delay to be made smaller, which makes it possible not only to decrease Idc but also to suppress the ripple. However, when capacitive element74is used, a decrease in the voltage Vmon the instant node CP_OUT is connected to a load (word line WL) is noticeable. Depending on circumstances, Vmon may fall to a negative value, causing a forward bias in a p-n junction, which contributes to a decrease in the operation reliability of the circuit.

This problem is overcome by providing capacitive element75and transistor76in the configuration of the first embodiment.FIG. 11is a timing chart for the voltage VCP, signal CONNECTC, voltages Vref, Vmon, and flag FLAG. As shown inFIG. 11, immediately after switch40of row decoder17has been turned on, the value of VCP falls sharply. However, with the configuration of the first embodiment, transistor76is turned on at the same time switch40goes on, causing capacitive element75to be connected to node MON. This makes larger a capacitive load of limiter circuit70. As a result, an excessive drop in Vmon can be suppressed.

Excluding the instance switch circuit40goes on, transistor76is off. Therefore, in the remaining period, capacitive element75has no effect on the operation of limiter70. Accordingly, a large drop in Vmon can be suppressed, while making Idc smaller and keeping the following response of Vmon to lout.

4. Modification of the First Embodiment

FIG. 12is a circuit diagram of a voltage generator according to a modification of the first embodiment. The configuration is such that an re-channel MOS transistor77is further added to the configuration explained inFIG. 6. Transistor77has its drain connected to one electrode of capacitive element75and its source grounded. A signal /CONNECTC is input to the gate of transistor77. Signal /CONNECTC is an inverted signal of signal CONNECTC.

With this configuration, transistor77is turned on during the period before time t21inFIG. 10. Therefore, the potential at one electrode of capacitive element75is prevented from becoming floating. Therefore, at the instant of turning on transistor40of row decoder17, a fluctuation in Vmon caused by charge sharing can be suppressed.

While in the example ofFIG. 12, an example of setting one electrode of capacitive element75at the ground potential has been explained, a reference voltage that has a certain positive value may be used.

Next, a voltage generator and a semiconductor memory device according to a second embodiment will be explained. The second embodiment is such that capacitive element74is disconnected from node CP_OUT at the same time that the voltage generation module50is connected to a word line WL in the first embodiment. Hereinafter, only what differs from the first embodiment will be explained.

1. Configuration of Voltage Generation Module50

FIG. 13is a circuit diagram of a voltage generation module50according to the second embodiment. As shown inFIG. 13, voltage generation module50of the second embodiment is such that voltage generation module50explained with reference toFIG. 6is modified as follows:

(2) An n-channel MOS transistor78is provided between capacitive element74and node CP_OUT. Transistor78has its drain connected to node CP_OUT and its source connected to one electrode of capacitive element74. A signal /CONNECTC is input to the gate of transistor78. Transistor78, which is a high-withstand-voltage transistor, includes a gate insulating film whose thickness is almost the same as that of transistor40.

2. Effects of the Second Embodiment

With the configuration of the second embodiment, the moment node CP_OUT is connected to a word line WL, signal /CONNECTC is made low, turning off transistor78. This disconnects capacitive element74from node CP_OUT. Therefore, a sharp drop in voltage Vmon the moment node CP_OUT is connected to a word line WL can be suppressed.

During the rest period, signal /CONNECTC is high and therefore capacitive element74is connected to node CP_OUT. Accordingly, capacitive element74enables an AC delay to be made smaller and the following response of Vmon to lout to be secured.

Next, a voltage generator and a semiconductor memory device according to a third embodiment will be explained. The third embodiment is such that transistor78is replaced with a transfer gate in the second embodiment. Hereinafter, only what differs from the second embodiment will be explained.

1. Configuration of Voltage Generation Module50

FIG. 14is a circuit diagram of a voltage generation module50according to the third embodiment. As shown inFIG. 14, voltage generation module50of the third embodiment is such that voltage generation module50explained with reference toFIG. 13is modified as follows:

(1) A transistor78is provided between the other electrode of capacitive element74and node MON.

(2) Transistor78is replaced with a pair of an re-channel MOS transistor78-1and a p-channel MOS transistor78-2. Transistors78-1and78-2have their drain connected to the other electrode of capacitive element74and their source connected to node MON. Signal /CONNECTC is input to the gate of transistor78-1and signal CONNECTC is input to the gate of transistor78-2. Transistors78-1and78-2, which are low-withstand-voltage transistors, include gate insulating films whose film thickness is smaller than that of a high-withstand-voltage transistor, such as transistor40.

2. Effects of the Third Embodiment

The configuration of the third embodiment produces not only the effect explained in the second embodiment but also the effect of preventing coupling noise from occurring in Vmon via the gate capacitance of the transistor in disconnecting capacitive element74.

Specifically, with the third embodiment, the moment node CP_OUT is connected to a word line WL, the gate of transistor78-1transits from a high level to a low level and the gate of transistor78-2transits from the low level to the high level. Therefore, switching noise of transistors78-1and78-2is offset by a component resulting from the transition from the high level to the low level and by a component resulting from the transition from the low level to the high level.

This makes it possible to reduce noise in the voltage Vmon.

3. Modification of the Third Embodiment

The third embodiment can be applied to the first embodiment. Such an example is shown inFIG. 15.FIG. 15is a circuit diagram of a voltage generation module50. As shown inFIG. 15, a transistor76may be replaced with a transfer gate including a low-withstand-voltage n-channel MOS transistor76-1and a low-withstand-voltage p-channel MOS transistor76-2. Even this configuration produces the same effects.

Next, a voltage generator and a semiconductor memory device according to a fourth embodiment will be explained. The fourth embodiment relates to a configuration of resistive element73in the first to third embodiments. Hereinafter, only resistive element73will be explained.

1. First Example

In a first example, a current-addition R-2R digital-to-analog converter is used as resistive element73.FIG. 16is a circuit diagram of the R-2R digital-to-analog converter.

As shown inFIG. 16, a plurality of first switch elements M1to Mn (n being a natural number not less than 2) have their one end connected to node MON in a common connection manner and are subjected to switching control so as to correspond to digital-input bit signals B1to Bn, respectively. A plurality of second switch elements M1′ to Mn′ have their one end connected to node N2in a common connection manner and are subjected to switching control so as to correspond to signals /B1to /Bn, respectively, obtained by inverting the digital-input bit signals B1to Bn with inverter circuits IVs.

The other ends of the first switch elements M1toMn and those of the second switch elements M1′ to Mn′ subjected to switching control complementarily are connected in such a manner that those corresponding to each other are connected in a common connection manner. Switch elements M1to Mn, M1′ to Mn′ form a switching network114that is subjected to switching control whereby either node MON or node N2is selected according to complementary bit signals B1to Bn, /B1to /Bn in the digital inputs.

A ladder resistance network115is so configured that a plurality of (n) first resistive elements R5to R7and a plurality of (n+1) second resistive elements R1to R4one end of each of which is connected to a common connection node of the corresponding switch elements are connected in a ladder structure. Assuming the resistance of each of second resistive elements R1to R4is expressed as R, the resistance of each of first resistive elements R5to R7is set to 2R.

A third resistive element R8is connected between one end of a second resistive element group (R1to R4) of the ladder resistance network115and a Vss node.

A reference voltage generator116, which is to apply a reference potential Vref to node N2, has a low impedance.

As described above, a current-addition R-2R digital-to-analog conversion circuit where the ladder resistance network115is connected to the switching network114can be used as resistive element73. Such a current-addition R-2R digital-to-analog conversion circuit has been written in U.S. Pat. No. 6,404,274 (application Ser. No. 09/289,413, Jpn. Pat. Appln. KOKAI Publication No. 11-353889) which is incorporated herein by reference. Such a circuit can be used as resistive element73.

2. Second Example

In a second example, a current-addition digital-to-analog converter using binary code and thermometer code is used as resistive element73.FIG. 17is a circuit diagram of current-addition digital-to-analog converter using binary code and thermometer code.

As shown inFIG. 17, resistive element73may be replaced with a digital-to-analog converter including a binary current-addition module120and a thermometer code current-addition module121.

In binary current-addition module120, resistive elements are arranged so that current may change (or step up) in a stepwise manner at regular intervals according to binary data. In binary current-addition module120, resistive elements are connected in parallel in such a manner that the resistance of a resistive element is half that of the preceding one, starting with a reference resistance, enabling binary current-addition module120to increase current as binary data is counted up. Therefore, when binary data is input to the gates of gate transistors S<0> to S<3>, thereby performing selection control, this enables voltage Vmon to be stepped up.

Thermometer code is data code whereby the number of “1” bits in a binary representation is used as a number represented. For example, when “0,” “1,” “2,” “3,” “4,”, “5,” “6,” “7” in decimal are represented as binary data, they are represented using three bits as follows: “000,” “001,” “010,” “011,” “100,” “101,” “111” in that order. When these are represented in thermometer code, they are represented using seven bits as follows: “0000000,” “0000001,” “0000011,” “0000111,” “0001111,” “0011111,” “0111111,” “1111111” in that order. Thermometer code current-addition module121is controlled using the thermometer code.

Binary code is used for lower bits not required to have so high accuracy (or less influenced even if resistance varies). Thermometer code is used for higher bits required to have high accuracy (or liable to be affected by a variation in resistance). This increases resistance to a variation in resistance.

As described above, a current-addition digital-to-analog converter with a combination of binary code and thermometer code may be used without requiring a pair of differential amplifiers. Then, binary code is used for lower bits in voltage setting data composed of a plurality of bits. Thermometer code is used for higher bits. Then, a method of adding the resistances of the corresponding resistive elements is caused to correspond to binary code control and thermometer code control. This enables the contribution of a variation in the resistance of each of the resistive elements to be minimized when the most significant bit (MSB) is changed.

Such a current-addition digital-to-analog conversion circuit using binary code and thermometer code has been written in U.S. Pat. No. 7,595,684 (application Ser. No. 11/685,382, Jpn. Pat. Appln. KOKAI Publication No. 2007-282473) which is incorporated herein by reference. Such a circuit can be used.

As described above, the voltage generator50according to the embodiments includes a step-up circuit (CP60inFIG. 6) and a limiter circuit (limiter70inFIG. 6). The step-up circuit (CP60inFIG. 6) outputs a first voltage (VCP inFIG. 6) to a first node (CP_OUT inFIG. 6). The limiter circuit (limiter70inFIG. 6) monitors the voltage at the first node, thereby controlling the step-up circuit. The limiter circuit (limiter70inFIG. 6) includes a first resistive element (R72inFIG. 6), a second resistive element (R73inFIG. 6), a first capacitive element (C74inFIG. 6), a second capacitive element (C75inFIG. 6), a switch element (Tr76inFIG. 6), and a comparator (CMP71inFIG. 6). The first resistive element (R72inFIG. 6) has one end connected to the first node (CP_OUT inFIG. 6) and the other end connected to a second node (MON inFIG. 6). The second resistive element (R73inFIG. 6) has one end connected to the second node (MON inFIG. 6). The first capacitive element (C74inFIG. 6) has one electrode connected to the first node (CP_OUT inFIG. 6) and the other electrode connected to the second node (MON inFIG. 6). At the same time that the first node (CP_OUT inFIG. 6) is connected to a load (WL inFIG. 6), the switch element (Tr76inFIG. 6) connects the second capacitive element (C75inFIG. 6) to the second node (MON inFIG. 6). The comparator (CMP71inFIG. 6) compares the potential at the second node (MON inFIG. 6) with the reference potential (Vref inFIG. 6) to control the step-up circuit according to the comparison result.

Alternatively, the capacitive element (C74inFIG. 13) is provided between the first node (CP_OUT inFIG. 13) and the second node (MON inFIG. 13). Then, at the same time that the first node (CP_OUT inFIG. 13) is connected to a load (WL inFIG. 13), the switch element (Tr78inFIG. 13) disconnects the capacitive element (C74inFIG. 13) from the first node (CP_OUT inFIG. 13) or the second node (MON inFIG. 13).

As described above, when output node CP_OUT of voltage generation module50is connected to a load (word line WL), load75is connected temporarily to detection node MON of the limiter circuit70. Alternatively, bypass capacitor74added to improve the stability and response of a stepped-up potential is disconnected by switch78. During the period excluding the time that a stable operation is expected, load75is disconnected from detection node MON and bypass capacitor74is connected to output node CP_OUT. This makes it possible to suppress a rapid drop in the potential of detection node MON to a negative value, while securing the stability and response of the stepped-up potential.

As switches76and78, an n-channel MOS transistor and a p-channel MOS transistor can be used. It is conceivable that these MOS transistors do not function sufficiently as switches, depending on the potential of the MON node. Therefore, it is preferable to use transfer gates as switches76and78. This enables at least either the n-channel MOS transistor or p-channel MOS transistor to function as a switch, even if the potential of MON node is zero or VDD (positive potential).

Embodiments are not limited to what has been explained above and may be modified variously. For example, in the described embodiments, the period during which signal CONNECTC is kept high is 0.8 μs, this is illustrative only. Charge sharing between the capacitance on the memory cell array side and the capacitance of the limiter circuit70takes place instantaneously. It is sufficient if signal CONNECTC is kept high only when the charge sharing is taking place. In the above embodiments, signal CONNECTC is made high at the same time that node CP_OUT is connected to a word line WL. However, they need not necessarily take place accurately at the same time. Signal CONNECTC may be made high earlier than node CP_OUT is connected to a word line WL. In other words, the expression “at the same time” in this specification allows a certain amount of error.

When signal CONNECTC is made high, capacitive element75has an effect on the operation of limiter circuit70. Therefore, when signal CONNECTC is made high before node CP_OUT is connected to a word line WL, it is preferable to set the timing in a range that prevents capacitive element75from having an adverse effect on the operation of limiter circuit70. The same holds true for the timing with which signal CONNECTC is changed from high to low.

InFIG. 13explained in the second embodiment, transistor78may be provided between capacitive element74and node MON. In this case, a low-withstand-voltage transistor may be used as transistor78. That is, the withstand voltage of transistor78(78-1and79-2) is, for example, lower than that of transistor40. Conversely, transistors78-1and78-2may be provided between capacitive element74and node CP_OUT inFIG. 14. In this case, high-withstand-voltage transistors are used as transistors78-1and78-2. That is, the withstand voltage of transistor78(78-1and78-2) is set to, for example, that of transistor40or higher.

Memory cell array ofFIG. 2may be configured as shown inFIG. 18.FIG. 18is a circuit diagram of block BLK0. The remaining blocks BLK1to BLK3may have the same configuration. As shown inFIG. 18, word lines WL0to WL3, back-gate line BG, even-numbered select gate lines SGD0and SGD2, and odd-numbered select gate lines SGS1and SGS3are drawn to one side of memory cell array10. In contrast, word lines WL4to WL7, even-numbered select gate lines SGS0and SGS2, and odd-numbered select gate lines SGD1and SGD3are drawn to the other side of the memory cell array, that is, to the opposite side of the one side. In this configuration, for example, row decoder11may be divided into two sub-row decoders. The sub-row decoders may be arranged so as to sandwich memory cell array10between them. One sub-row decoder may select select gate lines SGD0, SGD2, SGS1and SGS3, word lines WL0to WL3, and back-gate line BG and the other sub-row decoder may select select gate lines SGS0, SGS2, SGD1and SGD3, and word lines WL4to WL7. With this configuration, the congestion of interconnections, including the select gate lines and word lines, between the row decoder17and memory cell array10can be alleviated.

Furthermore, in the embodiments, a semiconductor memory device has been explained, taking a three-dimensional stacked NAND flash memory as an example. However, the three-dimensional stacked NAND flash memory is not restricted to the configurations shown inFIGS. 3 to 5. For example, semiconductor layer26may be of a single columnar shape instead of a horseshoe shape. In this case, transistor BT is unnecessary. The embodiments are not limited to the three-dimensional stack structure and may be applied to a conventional NAND flash memory or the like where memory cells are arranged two-dimensionally in a plane of a semiconductor substrate. However, the memory cell array of the three-dimensional stacked NAND flash memory has a very large capacity as compared with the conventional equivalent. Therefore, when the embodiments are applied the three-dimensional stack structure, their effects are remarkable. Especially, with a configuration where high-density implementation is performed, the reference voltage Vref tends to be made much lower, making Vmon more liable to take a negative value. Therefore, it is preferable to apply the above embodiments to such a configuration.

Of course, the above embodiments can be applied not only to a NAND flash memory but also memory devices with a step-up circuit in general. Moreover, the embodiments may be applied to not only memory devices but also voltage regulators in general.