Switched-capacitance amplifier, a switched-capacitance filter and a charge-transfer filter comprising an amplifier of this type

The switched-capacitance amplifier comprises n capacitors C.sub.11 to C.sub.1n which are periodically switched in parallel and in series, the n parallel-switched capacitors being charged simultaneously by the same voltage V.sub.E. An amplified voltage n.times.V.sub.E is obtained between the end terminals A and B of the n series-switched capacitors. Periodic switching of the n capacitors in parallel and in series is performed by means of MOS transistors T.sub.11 to T.sub.1(2n-1) and T.sub.21 to T.sub.2(n-1) which operate in the switching mode. The n capacitors and the MOS transistors are integrated on the same semiconductor substrate.

This invention relates to a switched-capacitance amplifier as well as to 
switched-capacitance filters and to charge-transfer filters which 
incorporate an amplifier of this type. 
Switched-capacitance filters have been described in particular in two 
articles published in the American review entitled "Proceedings of the 
Institute of Electrical and Electronics Engineers", volume SC 12--No 
6--December 1977--pages 592 to 608, and "International symposium on 
circuits and systems proceedings"--April 1977--pages 525 to 529. 
Switched-capacitance filters are essentially composed of a filter cell and 
of an amplifier. The filter cell which is integrated has the same 
properties as a conventional filter cell constituted by resistors and 
capacitors but consists only of capacitors and MOS transistors. The 
resistors are replaced by a combination of MOS transistors and of 
capacitors, thus making it possible in particular to reduce their 
dimensional requirements as well as to obtain higher temperature stability 
and better linearity. The amplifier which is associated with the filter 
cell must have a very stable and well-defined gain. An operational 
amplifier is usually employed. 
The disadvantage of this amplifier lies in the fact that it cannot readily 
be integrated on the same substrate as the filter cell and also in the 
fact that it has high power consumption. 
The switched-capacitance amplifier in accordance with the invention 
utilizes the same technology as the filter cell since it is composed 
solely of capacitors and of MOS transistors and can be readily integrated 
with this latter. Said amplifier has the further advantage of a very 
stable and well-defined gain as well as a low power consumption. 
The present invention relates to a switched-capacitance amplifier 
comprising n periodically switched capacitors in parallel and in series: a 
single voltage charges simultaneously the n capacitors which are switched 
in parallel; an amplified voltage is obtained between the end terminals A 
and B of the n capacitors which are switched in series. Periodic switching 
of the n capacitors in parallel and in series is carried out by MOS 
transistors operating in the switching mode, the n capacitors and the 
transistors being integrated on the same semiconductor substrate. 
This invention relates to a single-input switched-capacitance amplifier and 
to a switched-capacitance differential amplifier.

The same references designate the same elements in the different figures in 
which the dimensions and proportions of the different elements have not 
been complied with. 
FIG. 1 shows one embodiment of a switched-capacitance amplifier according 
to the invention. 
Let C.sub.11, C.sub.12 . . . C.sub.1n designate the n capacitors to be 
switched periodically from parallel to series and conversely. 
The drains and sources of (n-1) MOS transistors, also referred-to as TMOS 
transistors, T.sub.21 to T.sub.2(n-1) are connected between the terminals 
of two successive capacitors, only the two end terminals of which are left 
free, namely terminal A of capacitor C.sub.11 and terminal B of capacitor 
C.sub.1n. 
The drains and sources of n MOS transistors T.sub.11 to T.sub.1n are 
connected between one of the terminals of each capacitor including the end 
terminal A, and the input E to which is applied a voltage V.sub.E. 
The drains and sources of (n-1) MOS transistors T.sub.1(n+1) to 
T.sub.1(2n-1) are connected between the other terminal of each capacitor 
and ground except for the terminal B which is connected directly to 
ground. 
The MOS transistors are driven by two periodic signals .phi..sub.1 and 
.phi..sub.2 applied respectively to the gates of transistors T.sub.11 to 
T.sub.1(2n-1) forming part of a first group of transistors G.sub.1, and of 
transistors T.sub.21 to T.sub.2(n-1) forming part of a second group of 
transistors G.sub.2. 
FIGS. 2a and 2b are phase diagrams of the periodic signals .phi..sub.1 and 
.phi..sub.2. 
Said diagrams (a) and (b) represent the potentials .phi..sub.1 and 
.phi..sub.2 the amplitude of which is rising from 0 to V, in volts, with a 
period T; the potentials .phi..sub.1 and .phi..sub.2 are never at V 
simultaneously. 
The transition of .phi..sub.1 from V to 0 is separated from the transition 
of .phi..sub.2 from 0 to V by a non-zero time interval .tau.. 
The operation of the device described earlier, as designated by the 
reference 1 and shown in dashed outline in FIG. 1 is as follows: 
at the instant t.sub.1, the signal .phi..sub.1 assumes the value V which 
initiates conduction of the TMOS transistors T.sub.11 to T.sub.1(2n-1). 
The voltage V.sub.E then charges the n capacitors in parallel through the 
TMOS transistors T.sub.11 to T.sub.1n. One terminal of these capacitors is 
maintained at the reference potential by means of the TMOS transistors 
T.sub.1(n+1) to T.sub.1(2n-1) ; 
at the instant t.sub.2, the signal .phi..sub.1 assumes the value 0 which 
has the effect of turning-off the TMOS transistors of the first group, 
whereupon the n capacitors are charged at the voltage V.sub.E ; 
after a non-zero time interval .tau. and in order to ensure that the TMOS 
transistors of both groups are not caused to conduct simultaneously, the 
signal .phi..sub.2 changes to V and initiates conduction of the TMOS 
transistors T.sub.21 to T.sub.2(n-1). The n capacitors are then in series 
and the voltage between the node A and ground is n.times.V.sub.E. 
The first group of TMOS transistors therefore serves to switch the n 
capacitors in parallel and the second group of TMOS transistors serve to 
switch these latter in series. 
The drain and the source of a TMOS transistor T.sub.3 is connected between 
the end terminal A and a node F. A capacitor C.sub.20 is connected between 
the node F and the potential to which the node B is brought when the 
capacitors are in series, namely ground potential in this case. 
The TMOS transistor T.sub.3 is driven by a periodic signal .phi..sub.3 
applied to the gate of said transistor. The potential .phi..sub.3 shown in 
FIG. 2c raises from 0 to V in volts with a period T in the same manner as 
.phi..sub.1 and .phi..sub.2. The potential .phi..sub.3 changes to V during 
the time interval in which the potential .phi..sub.2 is at V. The 
potential .phi..sub.3 can coincide with .phi..sub.2. 
The device described in the foregoing is designated by the reference 
numeral 2 and shown in dashed outline in FIG. 1. 
At the instant t.sub.3, when the potential .phi..sub.3 changes to V, the 
TMOS transistor T.sub.3 is turned on and the voltage n.times.V.sub.E at 
the node A is transmitted to the node F. The capacitor C.sub.20 serves to 
adjust the gain of the amplifier and to hold the information. 
The voltage at F at the instant t.sub.3 is given by writing the charge 
storage in the capacitors between t.sub.2 +.tau. and t.sub.3 and, in the 
case in which the n capacitors have the same value C, by: 
##EQU1## 
An output stage which makes it possible to obtain the amplified voltage at 
a medium value of impedance is connected to the node F. In FIG. 1, said 
stage is designated by the reference numeral 3 and shown in dashed 
outline. 
In FIG. 1, the output stage is constituted, for example, by a follower 
stage comprising two series-connected TMOS transistors T.sub.4 and 
T.sub.5. The input to the follower stage is established through the gate 
of transistor T.sub.4, the drain of T.sub.4 being supplied with a voltage 
V.sub.DD and the output is established through the source of T.sub.4 to 
which are connected the gate and the drain of T.sub.5, the source of 
T.sub.5 being connected to ground. 
The gain of the follower stage is written: 
##EQU2## 
(W/L) 5,4 being the ratio of width to length of the MOS channel of the 
TMOS transistors T.sub.5 and T.sub.4. 
The net gain of the amplifier is therefore: 
##EQU3## 
This gain is therefore continuously adjustable by varying the capacitance 
C.sub.20 and is of maximum value when the capacitance C.sub.20 is reduced 
to the gate capacitance of the TMOS transistor T.sub.4. Said gain is 
dependent on the ratio of capacitances C.sub.20 /C, on the geometry of the 
TMOS transistors T.sub.4 and T.sub.5 and on the number of capacitors. 
The output stage can be connected directly at A. The TMOS transistor 
T.sub.3 is therefore dispensed with. In this case, the gain is of maximum 
value. However, the capacitor C.sub.20 can be maintained between node A 
and node B in order to adjust the gain. In this case the capacitors 
C.sub.11 and C.sub.20 are charged in parallel from t.sub.1 to t.sub.2 by 
the TMOS transistor T.sub.11. The expression of the voltage at A without 
the TMOS transistor T.sub.3 and with the capacitor C.sub.20 is written: 
##EQU4## 
FIG. 3 shows one embodiment of a switched-capacitance differential 
amplifier according to the invention. 
As in FIG. 1, the drains and the sources of (n-1) TMOS transistors T.sub.21 
to T.sub.2(n-1) are connected between the terminals of two successive 
capacitors except for the end terminals A and B. In this case, an n.sup.th 
TMOS transistor T.sub.2n is connected between the terminal B and a 
reference voltage V.sub.R which can be ground. 
As in FIG. 1, the drains and the sources of n TMOS transistors T.sub.11 to 
T.sub.1n are connected between one of the terminals of each capacitor 
including the end terminal A, and an input E.sub.1 to which is applied a 
voltage V.sub.E +. 
In this case, the drains and the sources of n TMOS transistors T.sub.1(N+1) 
to T.sub.1(2n) are connected between the other terminal of each capacitor 
including the end terminal B, and a second input E.sub.2 to which is 
applied a voltage V.sub.E -. 
The TMOS transistors T.sub.11 to T.sub.1(2n) and the TMOS transistors 
T.sub.21 to T.sub.2n are driven by periodic signals .phi..sub.1 and 
.phi..sub.2 which are identical with those shown in FIGS. 2a and 2b. 
The device described in the foregoing is designated by the reference 
numeral 4 and shown in dashed outline in FIG. 3. 
From t.sub.1 to t.sub.2, the n parallel-connected capacitors are no longer 
charged to the value V.sub.E but from V.sub.E +-V.sub.E -. 
At the instant t.sub.2 +.tau., the voltage at A is equal to n(V.sub.E+ 
-V.sub.E-)-V.sub.R since the TMOS transistor T.sub.2n connects the node B 
to a reference voltage V.sub.R. 
At the node A, it is possible to connect a unit which is identical with 
that shown in FIG. 1 and designated by the reference numeral 2. Said unit 
comprises a TMOS transistor T.sub.3 between A and F and a capacitor 
C.sub.20 between F and the voltage to which the node B is brought when the 
capacitors are in series, which is V.sub.R in this case. 
The voltage V.sub.F at F and at the instant t.sub.3 is given by writing the 
capacitor charge storage as follows: 
##EQU5## 
The first term of the expression of V.sub.F is therefore similar to the 
expression of V.sub.F in the case of the amplifier shown in FIG. 1. The 
second term makes it possible to adjust the offset voltage. 
An output stage for obtaining the amplified voltage at a medium value of 
impedance can be connected to the node F or directly to the node A. 
The output stage can be a follower stage which is similar to that shown in 
FIG. 1 but can also be a conventional unity-gain circuit as shown in FIG. 
3 comprising TMOS depletion transistors T.sub.40, T.sub.41, T.sub.42, 
T.sub.43 and TMOS enrichment transistors T.sub.44, T.sub.45, T.sub.46, 
T.sub.47. Temperature stability is further enhanced but there is an 
increase in dissipated power and surface area. 
Both in the case of FIG. 1 and in the case of FIG. 3, the inputs of the 
amplifier according to the invention are not strictly high-impedance 
inputs since it is necessary to charge the n capacitors in parallel from 
t.sub.1 to t.sub.2. As a general rule, the capacitors are of low value 
since they have to be integrated on the same substrate as the TMOS 
transistors. An input stage which can be a follower stage of a type 
similar to that shown in FIG. 1 and designated by the reference numeral 3 
can be placed upstream of each amplifier input in order to obtain a 
very-high-impedance input. These follower stages are represented 
schematically by rectangles in FIG. 3 and designated by the reference 
numeral 5. 
FIGS. 4a and 4b are sectional views of an integrated capacitor and the 
electrical diagram which is associated with this latter. 
The capacitor is fabricated in accordance with a technology involving the 
use of two levels N.sub.1 and N.sub.2 of polycrystalline silicon and an 
aluminum level divided into two portions n.sub.1 and n.sub.2 insulated by 
an oxide layer 10. 
One capacitor plate connected to terminal B.sub.1 is formed by the assembly 
consisting of silicon N.sub.1 and aluminum n.sub.1 whilst the other 
capacitor plate connected to terminal B.sub.2 is formed by the assembly 
consisting of silicon N.sub.2 and aluminum n.sub.2. 
The oxide layers which separate the different metal deposits are of small 
thickness compared with the oxide layer 10 which separates them from the 
substrate. The presence of the semiconductor substrate 11 which carries 
the oxide layer and which usually serves as a potential reference 
introduces not-negligible stray capacitances Cp.sub.1 and Cp.sub.2 on the 
terminals B.sub.1 and B.sub.2 of the capacitor C, said stray capacitances 
being shown in dashed lines in FIG. 4a. 
The values of Cp.sub.1 and Cp.sub.2 are different: the value of Cp.sub.1 is 
proportional to the value of the realized capacitance C whilst the value 
Cp.sub.2 is fixed and usually very much lower than Cp.sub.1. In FIG. 4b, 
the plate of the capacitor C which is connected to the terminal B.sub.1 is 
shown as a thick line and the plate of the capacitor C which is connected 
to the terminal B.sub.2 is shown as a thin line. 
The stray capacitances are particularly troublesome in switched-capacitance 
differential amplifiers since, in addition to a reduction in gain, they 
introduce a substantial increase in the common mode. 
There is shown in FIG. 5 one embodiment of a differential amplifier having 
two switched capacitances in which there is a decrease in the gain 
reduction and in which the common mode resulting from stray capacitances 
is suppressed. 
As was the case in FIG. 4b, the plates of each capacitor have been 
represented in this figure in one thick line and one thin line, and the 
stray capacitances associated with the two capacitances to be switched are 
shown in dashed lines; both capacitances have the same value C and their 
stray capacitances Cp.sub.1 and Cp.sub.2 are therefore the same. 
This embodiment differs from that shown in FIG. 3 since: 
the drain and the source of the TMOS transistor T.sub.21 of the second 
group are necessarily connected to two terminals having the same name 
B.sub.1 or B.sub.2 ; 
a TMOS transistor T.sub.50 is connected between the end terminal A and 
ground and driven by a periodic signal .phi..sub.4 applied to the 
transistor gate; 
the reference voltage V.sub.R is ground. 
The signal .phi..sub.4 shown in FIG. 2d, as .phi..sub.1, .phi..sub.2, 
.phi..sub.3, rises from 0 to V in volts with a period T. The signal 
.phi..sub.4 changes to the value V between t.sub.2 and t.sub.2 +.tau. 
whereas the two capacitors are isolated from each other. 
At the instant t.sub.1, the two capacitors C are charged to V.sub.E 
+-V.sub.E - whilst the stray capacitances Cp.sub.1 and Cp.sub.2 are 
charged to V.sub.E + or to V.sub.E - according as the terminal at which 
they appear is connected either to E.sub.1 or to E.sub.2. 
At the instant t.sub.4, the signal .phi..sub.4 changes to V and triggers 
the TMOS transistor T.sub.50 into conduction, the stray capacitance of the 
terminal of capacitor C.sub.1 connected at A is charged the signal 
.phi..sub.4 reverts to 0 before t.sub.2 +.tau.. 
At the instant t.sub.2 +.tau., the two capacitors are placed in series and 
the stray capacitance of the terminal of capacitor C which is connected to 
the node B is thus discharged by T.sub.22. 
In this embodiment, the voltage at A at the instant t.sub.3 is proportional 
to V.sub.E +-V.sub.E - 
EQU V.sub.A =K.multidot.[V.sub.E +-V.sub.E -] 
If the stray capacitance at A is of very small value compared with C as is 
generally the case with Cp.sub.2, then V.sub.A is written: 
##EQU6## 
C.sub.p is the stray capacitance of the capacitors C other than the stray 
capacitance at A. 
The stages connected to the node A and before the inputs E.sub.1 and 
E.sub.2 are the same as those employed in the case of a differential 
amplifier of the type shown in FIG. 3. 
FIGS. 6a and 6b illustrate a switched-capacitance filter comprising a 
switched-capacitance amplifier in accordance with the invention. 
In these figures, a filter of the low-pass type is taken as an example. 
In FIG. 6a, said filter is formed by connecting a switched-capacitance 
filter cell in series with a single-input switched-capacitance amplifier 
shown diagrammatically and designated by the reference numeral 7, the 
output of the amplifier being connected to the cell in a feedback loop. 
The gain of the amplifier must be between 1 and 2, thus limiting the 
number of capacitances to be switched to two. The filter cell comprises 
four series-connected TMOS transistors T.sub.60, T.sub.61, T.sub.62, 
T.sub.63, the input being established on the drain of T.sub.60 and the 
output being established on the source of T.sub.63. A capacitor is 
connected between the source of T.sub.60, T.sub.62, T.sub.63 and ground 
and between the source of T.sub.61 and the output of the amplifier. At 
least four periodic signals are necessary for operation, namely two 
signals for the filter cell .phi..sub.5 and .phi..sub.6 and two signals 
for the amplifier .phi..sub.1 and .phi..sub.2. 
In FIG. 6b, there is shown a diagram of the filter of FIG. 6a in which the 
last capacitor of the cell coincides with the two amplifier capacitors 
C.sub.1 and C.sub.2 to be switched. Only three periodic signals are then 
necessary. 
This filter of the second order which is entirely constituted by switched 
capacitances can be placed as a pre- and post-filtering cell of a 
charge-transfer transversal filter. The filter can then be controlled by 
the same periodic signals as the charge-transfer circuit. 
FIG. 7 shows a charge-transfer filter which makes use of a 
switched-capacitance amplifier according to the invention. 
A charge-transfer filter comprises: 
a semiconductor substrate; 
an insulating layer deposited on the substrate; 
electrodes deposited on the insulating layer and constituted alternately by 
electrodes E1.sub.1 which are cut into two portions and by uncut 
electrodes E1.sub.2 for effecting the transfer of charges in the 
semiconductor by applying given potentials; 
reading means M.sub.1 and M.sub.2 of quantities of charges which are 
present beneath the two portions of the cut electrodes, said means are 
known in the prior art; 
a differential amplifier formed on the same semiconductor substrate as the 
remainder of the filter, which receives on its two inputs E.sub.1 and 
E.sub.2 the voltages V.sub.E + and V.sub.E - which are delivered by the 
reading means and serve to produce the output voltage V.sub.s of the 
filter. 
In FIG. 7, the differential amplifier is a switched-capacitance 
differential amplifier. The periodic signals .phi..sub.1, .phi..sub.2, 
.phi..sub.3 can be identique with signals employed in the operation of the 
charge-transfer device. The switched-capacitance amplifier is well suited 
to this type of application since it processes sampled signals which are 
precisely the signals delivered by the reading means. Complete integration 
of a charge-transfer filter can thus be achieved.