Pixel circuit capable of determining displayed gray scale and method for driving the same

A pixel circuit is provided. The pixel circuit is electrically coupled to a data line, a first scan line, and a second scan line. The pixel circuit includes a first pixel unit, a second pixel unit, and a third pixel unit. The first pixel unit is electrically coupled to the data line and the second scan line, to determine a first displayed gray scale of the first pixel unit. The second pixel unit is electrically coupled to the data line and the first scan line, to determine a second displayed gray scale of the second pixel unit. The third pixel unit is electrically coupled to the data line, the first scan line, and the second scan line, to determine a third displayed gray scale of the third pixel unit.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 101108143, filed on Mar. 9, 2012. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

1. Field of the Invention

The invention generally relates to a pixel circuit and a method for driving the same. More particularly, the invention relates to a pixel circuit for displaying a two-dimensional (2D) image and a three-dimensional (3D) image and a method for driving the pixel circuit.

2. Description of Related Art

In recent years, as display technology continuously advances, users have become more and more demanding on display quality, e.g., image resolution, color saturation, and so forth. In process of purchasing a display, whether the display is able to display a 3D image or not is also taken into consideration in addition to high image resolution and high color saturation. Since the technology for rendering a 3D image has not yet been widely adopted, the 3D image is not as common as the 2D image; namely, most video and image sources are 2D. In order for a display not to be subject to different video and image sources, some manufacturers have developed a certain display that can switch between a 2D-image display mode and a 3D-image display mode.

To resolve a color washout issue of displayed images, one single pixel of a display panel may be divided into a plurality of display blocks, so as to compensate the color washout effect at different viewing angles. On the other hand, to display a 3D image without encountering a cross-talk problem, some of the display blocks in one single pixel may serve as shielding blocks. Thereby, when the 3D image is being displayed, the number of the display blocks in one single pixel for resolving the color washout issue may be reduced. That is to say, in the process of displaying the 3D image, the color washout issue and the cross-talk problem may not be effectively resolved at the same time.

SUMMARY

The invention provides a pixel circuit that is equipped with a plurality of pixel units. The pixel units are coupled to one single data line to determine a plurality of displayed gray scales for a plurality of display blocks, and thereby the color washout issue arising from displaying an image may be resolved.

According to an embodiment of the invention, a pixel circuit that is electrically coupled to a data line, a first scan line, and a second scan line is provided. The pixel circuit includes a first pixel unit, a second pixel unit, and a third pixel unit. The first pixel unit is electrically coupled to the data line and the second scan line, so as to determine a first displayed gray scale of the first pixel unit. The second pixel unit is electrically coupled to the data line and the first scan line, so as to determine a second displayed gray scale of the second pixel unit. The third pixel unit is electrically coupled to the data line, the first scan line, and the second scan line, so as to determine a third displayed gray scale of the third pixel unit.

A driving method applicable for the aforementioned pixel circuit is provided. The method comprises inputting a display signal to the data line, so as to provide a first displayed level to the second pixel unit and the third pixel unit within a first time period and provide the second displayed level to the first pixel unit within a second time period, wherein the second time period is following the first time period.

Another method for driving the aforementioned pixel circuit is also provided. The method comprises: inputting a first gate signal to the first scan line, so as to enable the second pixel unit and the third pixel unit within a first time period; inputting a second gate signal to the second scan line, so as to enable the first pixel unit within a second time period following the first time period; and inputting a display signal to the data line, so as to provide a first displayed level to the second pixel unit and the third pixel unit within the first time period and provide a second displayed level to the first pixel unit within the second time period.

DESCRIPTION OF EMBODIMENTS

FIG. 1Ais a schematic view illustrating a structure of a pixel circuit according to an embodiment of the invention. Please refer toFIG. 1A. In the present embodiment, it is assumed that each pixel circuit (e.g., a pixel circuit100) is electrically coupled to two scan lines (e.g., a first scan line LS1and a second scan line LS2) and one data line (e.g., a data line LD). In the present embodiment, the pixel circuit100includes a first pixel unit101, a second pixel unit103, and a third pixel unit105, configured to display a same color. The first pixel unit101at least includes a first active device (e.g., a transistor TR1) and a first pixel electrode PE1; the second pixel unit103at least includes a second active device (e.g., a transistor TR2) and a second pixel electrode PE2; the third pixel unit105at least includes a third active device (e.g., a transistor TR3), a fourth active device (e.g., a transistor TR4), a third pixel electrode PE3, and a capacitor CA.

FIG. 1Bis a schematic circuitry diagram illustrating the pixel circuit depicted inFIG. 1A. With reference toFIG. 1AandFIG. 1B, in the present embodiment, the first pixel unit101further includes a first storage capacitor Cst1formed by the first pixel electrode PE1and a common electrode line Lcom (corresponding to a common voltage Vcom) collectively. In the first pixel unit101, the transistor TR1is electrically coupled to the second scan line LS2, the data line LD, and the first pixel electrode PE1(equivalent to the first storage capacitor Cst1). That is to say, the drain of the transistor TR1(corresponding to the first end) is electrically coupled to the first pixel electrode PE1, the source of the transistor TR1(corresponding to the second end) is electrically coupled to the data line LD, and the gate of the transistor TR1(corresponding to the third end) is electrically coupled to the second scan line LS2.

Based on the above, the voltage on the second scan line LS2determines whether the transistor TR1is turned on or turned off. As the transistor TR1is turned on, a channel is formed in the transistor TR1, so as to provide the first pixel electrode PE1with a level (i.e., a displayed level) of a display signal transmitted via the data line LD. After the first pixel electrode PE1receives the displayed level, the displayed gray scale of the first block BK1is determined according to the displayed level received by the first pixel electrode PE1. Therefore, the first pixel unit101described in the present embodiment determines the value of the displayed gray scale (i.e., the first displayed gray scale) of the first block BK1.

According to the present embodiment, the second pixel unit103further includes a second storage capacitor Cst2formed by the second pixel electrode PE2and the common electrode line Lcom collectively. In the second pixel unit103, the transistor TR2is electrically coupled to the first scan line LS1, the data line LD, and the second pixel electrode PE2(equivalent to the second storage capacitor Cst2). That is to say, the drain of the transistor TR2(corresponding to the first end) is electrically coupled to the second pixel electrode PE2, the source of the transistor TR2(corresponding to the second end) is electrically coupled to the data line LD, and the gate of the transistor TR2(corresponding to the third end) is electrically coupled to the first scan line LS1.

Based on the above, the voltage on the first scan line LS1determines whether the transistor TR2is turned on or turned off. As the transistor TR2is turned on, a channel is formed in the transistor TR2, so as to provide the second pixel electrode PE2with a level (i.e., a displayed level) of a display signal transmitted via the data line LD. After the second pixel electrode PE2receives the displayed level of the display signal transmitted via the data line LD, the displayed gray scale of the second block BK2is determined according to the displayed level received by the second pixel electrode PE2. Therefore, the second pixel unit103described in the present embodiment determines the value of the displayed gray scale (i.e., the second displayed gray scale) of the second block BK2.

According to the present embodiment, the third pixel unit105further includes a third storage capacitor Cst3formed by the third pixel electrode PE3and the common electrode line Lcom collectively. In the third pixel unit105, the transistor TR3is electrically coupled to the first scan line LS1, the data line LD, and the third pixel electrode PE3(equivalent to the third storage capacitor Cst3). That is to say, the drain of the transistor TR3(corresponding to the first end) is electrically coupled to the third pixel electrode PE3, the source of the transistor TR3(corresponding to the second end) is electrically coupled to the data line LD, and the gate of the transistor TR3(corresponding to the third end) is electrically coupled to the first scan line LS1. The transistor TR4is electrically coupled to the second scan line LS2, the drain of the transistor TR3, and the capacitor CA. In other words, the drain of the transistor TR4is electrically coupled to the capacitor CA, the source of the transistor TR4is electrically coupled to the drain of the transistor TR3, and the gate of the transistor TR4is electrically coupled to second scan line LS2.

Based on the above, the voltage on the first scan line LS1determines whether the transistor TR3is turned on or turned off, and the voltage on the second scan line LS2determines whether the transistor TR4is turned on or turned off. As the transistor TR3is turned on, a channel is formed in the transistor TR3, so as to provide the third pixel electrode PE3with a level (i.e., a displayed level) of a display signal transmitted via the data line LD. As the transistor TR4is turned on, a channel is formed in the transistor TR4, such that the third pixel electrode PE3is electrically coupled to the capacitor CA for adjusting the displayed level received by the third pixel electrode PE3. After the adjustment of the displayed level of the third pixel electrode PE3, the displayed gray scale of the third block BK3is determined according to the adjusted displayed level received by the third pixel electrode PE3. Therefore, the third pixel unit105described in the present embodiment determines the value of the displayed gray scale (i.e., the third displayed gray scale) of the third block BK3.

FIG. 2Ais a schematic view illustrating a time sequence of a driving signal in the pixel circuit depicted inFIG. 1Bwhen a 2D image is being displayed.FIG. 2Bis a schematic view illustrating a time sequence of a driving signal in the pixel circuit depicted inFIG. 1Awhen a 2D image is being displayed. With reference toFIG. 1A,FIG. 1B,FIG. 2A, andFIG. 2B, within a first time period TP1, a first gate signal G1is input to the first scan line LS1. The transistors TR2and TR3are turned on according to the first gate signal G1, and the transistors TR1and TR4are turned off. At this time, the second pixel unit103and the third pixel unit105are enabled, and the level of the displayed signal SD1transmitted via the data line LD is the first displayed level VD1. The first displayed level VD1is respectively provided to the second pixel electrode PE2and the third pixel electrode PE3via the transistor TR2and the transistor TR3that are both turned on.

Within a second time period TP2following the first time period TP1, a second gate signal G2is input to the second scan line LS2. The transistors TR1and TR4are turned on according to the second gate signal G2, and the transistors TR2and TR3are turned off. At this time, the first pixel unit101is enabled, and the level of the displayed signal SD1transmitted via the data line LD is the second displayed level VD2higher than the first displayed level VD1. The second displayed level VD2is provided to the first pixel electrode PE1via the transistor TR1that is turned on. In addition, the third pixel electrode PE3is electrically coupled to the capacitor CA via the transistor TR4that is turned on. Due to electric charge sharing, the displayed level of the third pixel electrode PE3is lowered down. Herein, the sum of the first time period and the second time period is substantially equal to a time period for a horizontal line. The time period for a horizontal line is defined as the active time of one data enable (DE) signal of the source driver.

To sum up, in each pixel circuit (e.g., a red pixel circuit100R, a green pixel circuit100G, and a blue pixel circuit100B) described in the present embodiment, after the second time period TP2, the displayed level of the first pixel electrode PE1is higher than the displayed level of the second pixel electrode PE2, and the displayed level of the second pixel electrode PE2is higher than the displayed level of the third pixel electrode PE3. That is to say, the value of the displayed gray scale of the first block BK1is greater than the value of the displayed gray scale of the second block BK2, and the value of the displayed gray scale of the second block BK2is greater than the value of the displayed gray scale of the third block BK3. As such, the first block BK1, the second block BK2, and the third block BK3can have different values of displayed gray scales, so as to resolve the color washout issue arising from displaying a 2D image.

FIG. 3Ais a schematic view illustrating a time sequence of a driving signal in the pixel circuit depicted inFIG. 1Bwhen a 3D image is being displayed.FIG. 3Bis a schematic view illustrating a time sequence of a driving signal in the pixel circuit depicted inFIG. 1Awhen a 3D image is being displayed. With reference toFIG. 1A,FIG. 1B,FIG. 3A, andFIG. 3B, within a first time period TP1, a first gate signal G1is input to the first scan line LS1, so as to turn on the transistors TR2and TR3according to the first gate signal G1; here, the transistors TR1and TR4are turned off. At this time, the level of the displayed signal SD2transmitted via the data line LD is the first displayed level VD3. The first displayed level VD3is respectively provided to the second pixel electrode PE2and the third pixel electrode PE3via the transistor TR2and the transistor TR3that are both turned on.

Within a second time period TP2, a second gate signal G2is input to the second scan line LS2, so as to turn on the transistors TR1and TR4according to the second gate signal G2; here, the transistors TR2and TR3are turned off. At this time, the level of the displayed signal SD2transmitted via the data line LD is the second displayed level VD4lower than the first displayed level VD3, and the second displayed level VD4is provided to the first pixel electrode PE1via the transistor TR1that is turned on. The second displayed level VD4is zero, for instance. In addition, the third pixel electrode PE3is electrically coupled to the capacitor CA via the transistor TR4that is turned on. Due to electric charge sharing, the displayed level of the third pixel electrode PE3is lowered down.

To sum up, in each pixel circuit (e.g., a red pixel circuit100R, a green pixel circuit100G, and a blue pixel circuit100B) described in the present embodiment, after the second time period TP2, the displayed level of the first pixel electrode PE1is zero, and the displayed level of the second pixel electrode PE2is higher than the displayed level of the third pixel electrode PE3. The second pixel electrode PE2may be selectively placed on the edge of the pixel circuit100. The displayed level of the first pixel electrode PE1on the edge of the pixel circuit100is lower than the displayed level of the third pixel electrode PE3, and the displayed level of the first pixel electrode PE1located on the edge of the pixel circuit100is substantially zero. Namely, the value of the displayed gray scale of the first block BK1on the edge of the pixel circuit100is zero (i.e., the first block BK1is in black), and the value of the displayed gray scale of the second block BK2is greater than the value of the displayed gray scale of the third block BK3. As such, the second block BK2and the third block BK3can have different values of displayed gray scales, so as to resolve the color washout issue arising from displaying a 3D image. Besides, the displayed gray scale value of the first block BK1is zero (i.e., the first block BK1is in black), such that the first block BK1can serve as a shielding block for curing the cross-talk problem occurring in adjacent pixels when a 3D image is displayed.

In view of the above, a method for driving a pixel circuit deduced, and the method is suitable for driving the pixel circuit100shown inFIG. 1AandFIG. 1B.FIG. 4is a flowchart illustrating a method for driving a pixel circuit according to an embodiment of the invention. With reference toFIG. 1A,FIG. 1B,FIG. 2A,FIG. 2B,FIG. 3A,FIG. 3B, andFIG. 4, in step S401, the first gate signal G1is input to the first scan line LS1, so as to enable the second pixel unit103and the third pixel unit105within the first time period TP1. In step S403, the second gate signal G2is input to the second scan line LS2, so as to enable the first pixel unit101within the second time period TP2following the first time period TP1.

In step S405, the display signal SD is input to the data line LD, so as to provide the first displayed level (e.g., VD1or VD3) to the second pixel unit103and the third pixel unit105within the first time period TP1and provide the second displayed level (e.g., VD2or VD4) to the first pixel unit101within the second time period TP2. The order of said steps is merely exemplarily and should not be construed as a limitation to the invention. Besides, the detailed steps are already described in the embodiments shown inFIG. 1A,FIG. 1B,FIG. 2A,FIG. 2B,FIG. 3A, andFIG. 3C, and therefore no further description in this regard is provided hereinafter.

In light of the foregoing, a pixel circuit is provided herein. In the pixel circuit, a plurality of displayed levels are sequentially transmitted to the first pixel unit, the second pixel unit, and the third pixel unit via one single data line, and the first, second, and third pixel units respectively determine the displayed gray scales of the first, second, and third blocks. Thereby, no additional data line is required to resolve the color washout issue arising from displaying a 2D image, and the satisfactory aperture ratio (AR) of the pixel circuit can be guaranteed. Moreover, the displayed level of the first pixel electrode of the first pixel unit on the edge of the pixel circuit may be set to zero (i.e., black), and the difference in the displayed gray scales of the second and third blocks helps resolve the color washout issue arising from displaying a 3D image. Further, the first block can serve as a shielding block to overcome the cross-talk problem occurring in adjacent pixels when a 3D image is displayed.