Semiconductor device

A semiconductor device includes a multi-level wiring structure that includes a first wring layer, a plurality of first patterns, and a first mark. The first wring layer is disposed at a first wiring level of the multi-level wiring structure. The plurality of first patterns is disposed over the first wring layer. The plurality of first patterns is disposed at a second wiring level of the multi-level wiring structure. The second wiring level is above the first wiring level. The plurality of first patterns is disposed over the first wring layer. The plurality of first patterns is disposed at a second wiring level of the multi-level wiring structure. The second wiring level is above the first wiring level. The first mark is disposed over the first wring layer. The first mark is disposed at a third wiring level. The third wiring level is above the second wiring level.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a semiconductor device.

Priority is claimed on Japanese Patent Application No. 2011-086715, filed Apr. 8, 2011, the content of which is incorporated herein by reference.

2. Description of the Related Art

FIG. 20is a cross-sectional view illustrating a schematic configuration of a semiconductor device in the related art. A semiconductor device1pshown inFIG. 20is a stack-type semiconductor device of a chip-on-chip (CoC) type.

The semiconductor device1pincludes a wiring board2and a chip stacked body3pmounted on one surface of the wiring board2. The chip stacked body3pincludes a plurality of memory chips31pato31pdand an interface chip32p. Each of the memory chips31pato31pdand the interface chip32pincludes a surface bump electrode311and a rear bump pad312corresponding to the surface bump electrode311, and the surface bump electrode311and the rear bump electrode312are electrically connected by a through electrode4. The plurality of memory chips31pato31pdand the interface chip32pare electrically connected to each other via the surface bump electrode311, the rear bump electrode312, and the through electrode4.

In addition, the surface bump electrode311of one surface (a lower-side surface inFIG. 20) of the interface chip32pis connected to an electrode pad23of the wiring board2.

An assembly process of the semiconductor device1pshown inFIG. 20will be described.FIG. 21is a view for explaining an assembly process.

As shown inFIG. 21, the memory chip (a second-level semiconductor chip)31pbis stacked and mounted on the memory chip31paheld on a level99.

Each of the memory chips31pato31pdand the interface chip32pincludes a surface mark and a rear mark in a surface side and a rear surface side of the chip, respectively. The surface mark and the rear mark are used for alignment when semiconductor chips are stacked. Specifically, the surface mark of the memory chip31pais photographed by a board-side recognition camera of a flip chip bonder and a coordinate of the memory chip31paon the level is recognized. The rear mark of the memory chip31pbpicked up by a tool BT of the flip chip bonder is photographed by a part-side recognition camera of the flip chip bonder and a coordinate of the memory chip31pbon the tool is recognized. According to the obtained position information, a position of the tool is adjusted with respect to the level and the memory chip31pbis stacked and mounted on the memory chip31paso that the surface bump electrode311of the memory chip31paand the rear bump electrode312of the memory chip31pbaccurately overlap.

Similarly, the memory chips (third- and fourth-level semiconductor chips)31pcand31pdand the interface chip32p(fifth-level semiconductor chip) are stacked and mounted.

As described above, the surface mark and the rear mark are employed to perform accurate alignment between the semiconductor chips.

FIG. 22is a cross-sectional view of a mark portion of a memory chip31p.

As shown in the cross-sectional view ofFIG. 22, the memory chip31pincludes a multi-layer wiring structure including wiring tungsten WT and first to third aluminum wirings1ALp,2ALp, and3AL.

In addition, as shown inFIG. 22, a surface mark313including the third aluminum wiring3AL is formed in a surface side of the memory chip31pand the wiring tungsten WT connected to a through electrode TSV (through-silicon via) for a rear mark is formed below the surface mark313. A rear bump electrode312is further connected to the through electrode TSV for a rear mark, and the through electrode TSV for a rear mark and the rear bump electrode312form a rear mark314. The through electrode TSV for a rear mark penetrates a semiconductor substrate319.

In addition, a polyimide film PI is formed on the multi-layer wiring structure. The polyimide film PI has a PI opening PIO formed in an area including a portion on the surface mark313.

In a recent semiconductor process, chemical mechanical polishing (CMP) technology is used for planarization. In general, in order to correct a difference in polishing state between a pattern-dense portion and a pattern-sparse portion in the CMP process, a dummy pattern may be arranged in the sparse portion. The CMP dummy pattern includes a minute pattern such as the first and second aluminum wirings, the wiring tungsten, gates, and shallow trench isolations STI in either side of the PI opening.

In the related art, the dummy pattern is mostly prohibited from being arranged below the PI opening PIO due to the following two reasons. First, there is a case in which the minute dummy patterns of wiring layers of the first and second aluminum wirings become an obstacle in recognition of the surface mark313of the third aluminum wiring3AL. Second, when the minute pattern such as a gate is present below the surface mark, there is a case in which the gate of the minute pattern serves as a hard mask and causes occurrence of particles in a dry etching process of the through electrode TSV for a rear mark since the through electrode TSV for a rear mark is below the wiring tungsten pad WTP.

Therefore, a prohibition area PA is provided even in a portion of the surface mark described herein. In addition, inFIG. 22, the CMP dummy pattern prohibition area PA almost corresponds to the PI opening PIO (to be described in detail later).

It has become clear from the inventor's research that in the assembly process, contrast of the surface mark313is significantly degraded in recognition of the surface mark313through the recognition camera when the chip itself is embedded in the stack semiconductor device.

FIG. 23is a cross-sectional view illustrating a PI opening PIO in which incident light (a solid line) and reflected light (a dashed line) of lighting are indicated. Since only a dielectric material such as silicon oxide (SiO2) is present in the PI opening PIO over a pad of wiring tungsten WT, attenuation of visible light is very small. Thus, reflection from a wiring tungsten pad WTP, which is a background of a surface mark313, is large and contrast of the surface mark313is significantly degraded.

As a result, there is a problem that a recognition error of the surface mark313occurs in a TSV stacking process and a throughput of the above-described assembly process is considerably degraded.

Documents related to the above-described technical content include Japanese Patent Laid-open Publication No. 2006-140300 and Japanese Patent Laid-open Publication No. 2007-088124.

Japanese Patent Laid-open Publication No. 2006-140300 discloses that when a multilayered circuit pattern is formed on a semiconductor substrate, with respect to an accuracy measurement mark for inspecting whether a resist pattern formed by exposure accurately overlaps a circuit pattern of an underlying layer, a dummy pattern is formed in a mask formation area of an underlying wiring layer below the wiring layer in which a main scale pattern is formed, in order for the main scale pattern not to be affected by dishing during CMP.

Japanese Patent Laid-open Publication No. 2007-088124 describes an alignment mark of a mounting board.

Japanese Patent Laid-open Publication No. 2006-140300 thoroughly discloses only the accuracy measurement mark merely used for alignment of the resist pattern when forming a device forming layer. Therefore, Japanese Patent Laid-open Publication No. 2006-140300 does not describe recognition of an alignment mark after forming a semiconductor chip at all or a mark symmetrically arranged with respect to the accuracy measurement mark, and does not relate to a semiconductor chip of a stack semiconductor device.

Japanese Patent Laid-open Publication No. 2007-088124 discloses only the alignment mark when a device is mounted on a flexible board and does not relate to a semiconductor chip of a stack semiconductor device.

SUMMARY

In one embodiment, a semiconductor device may include, but is not limited to, a multi-level wiring structure that includes a first wring layer, a plurality of first patterns, and a first mark. The first wring layer is disposed at a first wiring level of the multi-level wiring structure. The plurality of first patterns is disposed over the first wring layer. The plurality of first patterns is disposed at a second wiring level of the multi-level wiring structure. The second wiring level is above the first wiring level. The plurality of first patterns is disposed over the first wring layer. The plurality of first patterns is disposed at a second wiring level of the multi-level wiring structure. The second wiring level is above the first wiring level. The first mark is disposed over the first wring layer. The first mark is disposed at a third wiring level. The third wiring level is above the second wiring level.

In another embodiment, a semiconductor device may include, but is not limited to, a multi-level wiring structure and a resin layer. The multi-level wiring structure may include, but is not limited to, a plurality of patterns disposed at a first wiring level of the multi-level wiring structure and a first mark disposed at a second wiring level of the multi level wiring structure. The second wiring level is above the first wiring level. The resin layer is disposed over the multi-level wiring structure. The resin layer has an opening that is positioned over the first mark and at least one the plurality of patterns.

In still another embodiment, a semiconductor device may include, but is not limited to, a multi-level wiring structure, an insulation layer, a plurality of bump electrodes, a plurality of first wirings, a second wiring, and a plurality of third wirings. The multi-level wiring structure includes a first level wiring layer and a second level wiring layer formed over the first level wiring layer. The insulation layer is formed over the multi-level wiring structure. The insulation layer has a plurality of first openings and a second opening. The plurality of bump electrodes is each disposed in an associated one of the first openings. The plurality of first wirings is produced as the second level wiring layer. Each of the first wirings is vertically arranged with an associated one of the first openings of the insulation layer. Each of the first wirings is coupled to an associated one of the bump electrodes. The second wiring is produced as the second level wiring layer. The second wiring is vertically arranged with the second opening of the insulation layer. The second wiring is free of a contact with any one of the bump electrodes. The plurality of third wirings is produced as the first wiring layer. The plurality of third wirings is disposed in a first region that is vertically arranged with the first opening of the insulation layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

In one embodiment, a semiconductor device may include, but is not limited to, a multi-level wiring structure that includes a first wring layer, a plurality of first patterns, and a first mark. The first wring layer is disposed at a first wiring level of the multi-level wiring structure. The plurality of first patterns is disposed over the first wring layer. The plurality of first patterns is disposed at a second wiring level of the multi-level wiring structure. The second wiring level is above the first wiring level. The plurality of first patterns is disposed over the first wring layer. The plurality of first patterns is disposed at a second wiring level of the multi-level wiring structure. The second wiring level is above the first wiring level. The first mark is disposed over the first wring layer. The first mark is disposed at a third wiring level. The third wiring level is above the second wiring level.

In some cases, the semiconductor device may further include, but is not limited to, a semiconductor substrate on which the multi-level wiring structure being disposed, and a first penetration electrode that penetrates the semiconductor substrate, and that is in contact with the first wiring layer at one end thereof.

In some cases, the semiconductor device may further include, but is not limited to, a second mark disposed at the other end of the first penetration electrode.

In some cases, the plurality of first patterns is electrically floated.

In some cases, the plurality of first patterns is positioned in a region that is vertically arranged with the first mark.

In some cases, the multi-level wiring structure further may include, but is not limited to, a plurality of second patterns disposed over the first wring layer. The plurality of second patterns is disposed at a fourth wiring level of the multi-level wiring structure. The fourth wiring level is between the second wiring level and the third wiring level.

In some cases, each of the plurality of second patterns is larger in size than each of the plurality of first patterns.

In some cases, the semiconductor device may further include, but is not limited to, a plurality of second penetration electrodes each penetrating through the second substrate; and a plurality of terminals, each of the terminals being formed over the multi-level wiring structure. Each of the terminals is coupled to an associated one of the plurality of second penetration electrodes. The first penetration electrode is free from being coupled to any one of the terminals.

In some cases, the semiconductor device may further include, but is not limited to, a plurality of third patterns. Each of the plurality of third patterns is disposed at the third level of the multi-level wiring structure. Each of the plurality of third patterns is coupled between an associated one of the second penetration electrodes and an associated one of the terminals. Each of the third patterns is different in shape from the first mark.

In another embodiment, a semiconductor device may include, but is not limited to, a multi-level wiring structure and a resin layer. The multi-level wiring structure may include, but is not limited to, a plurality of patterns disposed at a first wiring level of the multi-level wiring structure and a first mark disposed at a second wiring level of the multi-level wiring structure. The second wiring level is above the first wiring level. The resin layer is disposed over the multi-level wiring structure. The resin layer has an opening that is positioned over the first mark and at least one the plurality of patterns.

In some cases, the semiconductor device may further include, but is not limited to, a semiconductor substrate on which the multi-level wiring structure is disposed; a penetration electrode that penetrates the semiconductor substrate; and a second mark coupled to the penetration electrode.

In some cases, the multi-level wiring structure may further include, but is not limited to, a third wiring layer disposed under the first wiring layer. The third wiring layer is disposed at a third wiring level below the first wiring level. The penetration electrode extends to the third wiring layer.

In some cases, the plurality of patterns is electrically floated.

In still another embodiment, a semiconductor device may include, but is not limited to, a multi-level wiring structure, an insulation layer, a plurality of bump electrodes, a plurality of first wirings, a second wiring, and a plurality of third wirings. The multi-level wiring structure includes a first level wiring layer and a second level wiring layer formed over the first level wiring layer. The insulation layer is formed over the multi-level wiring structure. The insulation layer has a plurality of first openings and a second opening. The plurality of bump electrodes is each disposed in an associated one of the first openings. The plurality of first wirings is produced as the second level wiring layer. Each of the first wirings is vertically arranged with an associated one of the first openings of the insulation layer. Each of the first wirings is coupled to an associated one of the bump electrodes. The second wiring is produced as the second level wiring layer. The second wiring is vertically arranged with the second opening of the insulation layer. The second wiring is free of a contact with any one of the bump electrodes. The plurality of third wirings is produced as the first wiring layer. The plurality of third wirings is disposed in a first region that is vertically arranged with the first opening of the insulation layer.

In some cases, the multi-level wiring structure may further include, but is not limited to, a third level wiring layer. The first level wiring layer is formed over the third level wiring layer. The semiconductor device may further include, but is not limited to, a plurality of fourth wirings each produced as the third level wiring layer and vertically arranged with a corresponding one of the first wirings. The fifth wiring is produced as the third level wiring layer and vertically arranged with the second wiring.

In some cases, the semiconductor device may further include, but is not limited to, a semiconductor substrate on which the multi-level wiring structure is formed, a plurality of first penetrating electrode penetrating through the semiconductor substrate, each of the first penetrating electrodes extending to reach a corresponding one of the fourth wirings, and a second penetrating electrode penetrating through the semiconductor substrate and extending to reach the fifth wiring.

In some cases, the multi-level wiring structure may further include, but is not limited to, a fourth level wiring layer intervened between the first and the third level wiring layers. The device further may include, but is not limited to, a plurality of sixth wirings produced as the fourth level wiring layer and disposed in a second region that vertically arranged with the first region.

In some cases, each of the sixth wirings is smaller in size than each of the third wirings.

In some cases, each of the fourth wirings is electrically connected to the corresponding one of the first wirings. The fifth wiring is electrically disconnected from the second wiring.

In some cases, each of the third wirings is electrically floated.

According to the semiconductor device of the present invention, in particular, even when a plurality of first patterns are present below a first mark, degradation of contrast of the first mark is suppressed. Therefore, in a stacking process of a semiconductor chip itself, it is possible to avoid a mark recognition error and thus to improve a throughput.

First Embodiment

FIG. 1is a cross-sectional view illustrating a schematic configuration of a semiconductor device according to an embodiment of the present invention. A semiconductor device1shown inFIG. 1is a stack-type semiconductor device of a CoC type.

The semiconductor device1includes a substantially quadrangular wiring board2, in which predetermined wirings are formed. The wiring board2is, for example, a glass epoxy board having a thickness of 0.2 mm, the predetermined wirings are formed in either surface of an insulating base21, and the wirings are partially covered with an insulating layer22, for example, a solder resist. An opening is formed in a central area of one surface of the wiring board2, and a plurality of connection pads23are formed in a portion of one surface exposed from the opening of the insulating layer (solder resist)22. Meanwhile, a plurality of lands24are formed in a portion of the wiring of the other surface of the wiring board2exposed from the insulating layer22. Here, the connection pads23and the lands24corresponding thereto are electrically connected by the wiring of the wiring board2.

A chip stacked body3is mounted on one surface of the wiring board2. The chip stacked body3has a substantially quadrangular plate shape and includes a plurality of semiconductor chips which are stacked and in which predetermined circuits are formed on one surface thereof. In these conductor device shown inFIG. 1, for example, four memory chips31ato31din which memory circuits are formed and an interface chip32for interface between the memory chip31and the wiring board2are stacked in five levels. Each of semiconductor chips has, for example, a thickness of 50 μm. A plurality of surface bump electrodes311are formed in a central area of one surface of the semiconductor chip and a plurality of rear bump electrodes312are formed in a central area of the other surface side of the semiconductor chip. The surface bump electrodes311and the rear bump electrodes312corresponding thereto are electrically connected by through electrodes4.

A first encapsulating resin unit5, for example, including an underfill material is formed in the chip stacked body3. The encapsulating resin unit5is formed to fill gaps between the semiconductor chips.

The surface bump electrode311of one surface (a lower-side surface inFIG. 1) of the lowermost semiconductor chip of the chip stacked body3is connected to the connection pad23of the wiring board2via a wire bump25.

A non conductive paste (NCP)6is configured to be disposed around an electrical connection portion between the chip stacked body3and the wiring board2and to protect the electrical connection portion and bond and fix the chip stacked body3to the wiring board2. A second encapsulating resin unit7is formed on one surface of the wiring board2to cover the chip stacked body3.

Solder balls8which are external terminals of the semiconductor device1are mounted on the plurality of lands24of the other surface of the wiring board2, respectively, and the external terminals are arranged in a lattice form at predetermined intervals.

The memory chip31of a first embodiment of the present invention will be described.FIGS. 2A and 2Bare schematic plan views of a memory chip31.FIG. 2Ais a view when viewed from a circuit forming surface (a surface) andFIG. 2Bis a view when viewed from a semiconductor substrate side (a rear surface).

As shown inFIG. 2A, wiring through electrodes41are arranged along an x-direction in a central portion of the circuit forming surface of the memory chip31in a y-direction. A plurality of dummy bump through electrodes42are arranged along each of two lengthwise sides (sides extending in the x-direction ofFIG. 2A) of the circuit forming surface of the memory chip31. The dummy bump through electrodes42are provided to prevent the memory chip31from being damaged by stress. Further, surface marks313are arranged in a pair of corners which are located diagonally to each other so that the surface marks313are viewed from a side of the circuit forming surface of the memory chip. Preferably, the surface marks313are arranged within an area in which the plurality of dummy bump through electrodes42are arranged, that is, on a straight line passing through the plurality of dummy bump through electrodes42.

As shown inFIG. 2B, in the semiconductor substrate side of the memory chip31, the wiring through electrodes41are arranged along the x-direction in a central portion in the y-direction. The plurality of dummy bump through electrodes42are arranged along each of the two lengthwise sides (the sides extending in the x-direction ofFIG. 2B) of the semiconductor substrate side of the memory chip31. Further, rear marks314are arranged in a pair of corners which are located diagonally to each other so that the rear marks314are viewed from the semiconductor substrate side. The pair of surface marks313and the pair of rear marks314are provided in facing positions with the semiconductor substrate interposed therebetween.

Preferably, the rear marks314are arranged within an area in which the plurality of dummy bump through electrodes42are arranged, that is, on a straight line passing through the plurality of dummy bump through electrodes42.

FIGS. 3A and 3Bare cross-sectional views of a peripheral portion of the wiring through electrode41of the memory chip31(a through electrode portion for dummy bumps is also substantially the same) and a peripheral portion of the surface mark313and the rear mark314(hereinafter, may be simply referred to as a mark portion).

FIG. 3Aillustrates a cross-sectional view of a periphery of the wiring through electrode41andFIG. 3Billustrates a cross-sectional view of a mark portion. As shown inFIGS. 3A and 3B, the memory chip31includes a multi-layer wiring structure having a wiring tungsten layer WTL, and first to third aluminum wiring layers1AIL,2AIL, and3AIL. First to third interlayer insulating layers315,316, and317are formed betweens the wiring layers and a fourth interlayer insulating layer318is formed between the third aluminum wiring layer3AIL and a polyimide film PI. In addition, a through electrode TSV1or a through electrode for a mark penetrating a semiconductor substrate319is formed.

As shown inFIG. 3A, in a side of a circuit-forming surface (a surface) of a portion of the wiring through electrode41, a surface bump electrode311including a surface bump26and a copper pillar27is formed in an opening PIO formed in the polyimide film PI and is electrically connected to a wiring pad MWLP formed as the third aluminum wiring layer3AIL via a cover opening28.

Further, the wiring pad MWLP is connected to a second metal wiring MWL2formed as the second aluminum wiring layer2AIL via a third through hole TH3formed in the third interlayer insulating layer317and the second metal wiring MWL2is connected to a first metal wiring MWL1formed as the first aluminum wiring layer1AIL via a second through hole TH2formed in the second interlayer insulating layer316. The first metal wiring MWL1is connected to a wiring tungsten pad WTP1formed as the wiring tungsten layer WTL via a first through hole TH1formed in the first interlayer insulating layer315and the wiring tungsten pad WTP1is connected to the wiring through electrode TSV1. In addition, an insulating trench29is formed in a portion of the wiring through electrode41to surround the wiring through electrode TSV1in the semiconductor substrate319.

A rear insulating layer43and a rear bump44are formed in a surface (a rear surface) of the semiconductor substrate side of the wiring through electrode portion and the rear bump44is connected to the wiring through electrode TSV1.

As shown inFIG. 3A, a plurality of dummy wirings (dummy patterns) DWP, DP1and DP2, as well as substantial functional wiring (a wiring tungsten pad WTP1, and the first and second metal wirings MWL1and MWL2), are formed in the wiring through electrode portion as the respective wiring layers of the wiring tungsten layer WTL, and the first and second aluminum wiring layers1AIL and2AIL.

Here, the substantial functional wirings are wirings for propagating power potentials, signal levels, or the like and wirings to which desired potentials corresponding to the power levels or signal levels are applied.

On the other hand, since the dummy wirings (dummy patterns) DPW, DP1, and DP2are arranged to prevent “dishing” from being generated in an area in which the functional wirings are not present when the interlayer insulating layers are planarized by a CMP method, desired potentials corresponding to the power potentials, signal levels, or the like are not supplied thereto and the dummy patterns are wirings which are in a floating state.

AlthoughFIG. 3Ahas illustrated that the functional wirings are connected only to the wiring through electrode TSV1, they are not limited thereto. For example, the functional wirings may be arranged to be mixed with the plurality of dummy wirings (dummy patterns) DWP, DP1, and DP2shown inFIG. 3A.

Meanwhile, as shown inFIG. 3B, in a surface of the mark portion, the surface mark313is formed as the third aluminum wiring layer3AIL located below the opening PIO formed in the polyimide film PI, a wiring tungsten pad WTP2is formed as the wiring tungsten layer WTL located below the opening PIO, and the wiring tungsten pad WTP2is connected to the through electrode TSV2for a mark. In a rear side of the mark portion, a rear bump44in which a rear mark is formed is formed below the through electrode TSV2for a mark.

In the mark portion, a first dummy pattern (a lower dummy pattern) DP1is formed as the first aluminum wiring layer1AIL to be covered with the second interlayer insulating layer316(that is, not to penetrate the second interlayer insulating layer316), and a second dummy pattern (an upper dummy pattern) DP2is formed as the second aluminum wiring layer2AIL to be covered with the third interlayer insulating layer317(that is, not to penetrate the third interlayer insulating layer317).

The second dummy pattern has a width (a length in the x-direction ofFIG. 3B) larger than the first dummy pattern. Preferably, the functional wirings are not arranged in the first and second aluminum wiring layers1AIL and2AIL of an area on the wiring tungsten pad WTP2.

Here, the inventor inspected an image from a camera for recognizing a mark in a process of inspecting contrast of the mark, and thus found that, since the CMP dummy pattern is very small, the CMP pattern was not recognized at all in a resolution (about 1 μm) of the camera, and the CMP dummy pattern portion exposed from an edge portion of the opening POI was recognized to be darker than a background. That is, the inventor found that even when a minute pattern, which is smaller than the resolution of the camera, is arranged close to the mark, the pattern is not an obstacle but rather helps to improve the contrast.

FIG. 4Ais a schematic plan view of a case in which the polyimide film PI of a portion of the surface mark is removed when viewed from a side of the circuit forming surface (a surface) of a memory chip.FIG. 4Bis a schematic plan view including the polyimide film PI.FIG. 4Cis a schematic plan view of a portion of the rear mark when viewed from a semiconductor substrate side (a rear surface) of the memory chip.

As shown inFIG. 4A, the surface mark313is an L-shaped mark formed as the third aluminum wiring layer3AIL. As shown inFIG. 4B, the polyimide film PI corresponding to an area thereof is opened to expose the surface mark313. In addition, as shown inFIG. 4B, the wiring tungsten pad WTP2, which is connected to the through electrode TSV2for a mark formed as the wiring tungsten layer WTL, is formed below the surface mark313. The rear bump electrode312is connected to the through electrode TSV2for a mark. As shown inFIG. 4C, the rear mark314having an L shape including the through electrode TSV2for a mark and the rear bump electrode312is formed. The through electrode TSV2for a mark penetrates the semiconductor substrate319.

Here, in the chip of the semiconductor device according to the first embodiment of the present invention, as shown inFIGS. 3B,4A, and4B, even in an area below the opening POI (including a portion beneath the surface mark) formed in the polyimide film PI (that is, an area on the wiring tungsten pad WTP2formed as the wiring tungsten layer WTL), the first and second dummy wirings (dummy patterns) DP1and DP2are formed as the first and second aluminum wiring layers1AIL and2AIL, respectively. In addition, among an area below the opening PIO (including an area on the wiring tungsten pad WTP2) formed in the polyimide film PI, a wiring layer in which the dummy wirings (dummy patterns) DP1and DP2are formed includes a portion on the wiring tungsten layer WTL, that is, only the first and second aluminum wiring layers1AIL and21AI and the wiring tungsten layer WTL, the gate G, and the STI are excluded from the dummy patterns.

Here, the wiring tungsten layer WTL corresponds to a first wiring layer, the first aluminum wiring layer1AIL corresponds to a second wiring layer, and the third aluminum wiring layer3AIL corresponds to a third wiring layer. The surface mark313and the rear mark314correspond to a first mark and a second mark, respectively.

FIG. 5is a cross-sectional view illustrating incident light (a solid line) and reflected light (a dashed line) of lighting in the embodiment of the present invention. Externally illuminated light is transmitted through between the plurality of dummy patterns DP2as the second aluminum wiring layer2AIL and the light transmitted through between the plurality of dummy patterns DP2is divided into light scattered in the plurality of dummy patterns DP1as the first aluminum wiring layer1AIL and light transmitted through between the plurality of dummy patterns DP1as the first aluminum wiring layer1AIL. The light transmitted through between the plurality of dummy patterns DP1as the first aluminum wiring layer1AIL is reflected from the wiring tungsten pad WTP2including the wiring tungsten layer WTL or scattered in the plurality of dummy patterns DP1and DP2as the first aluminum wiring layer1AIL and the second aluminum wiring layer2AIL. Thus, reflectance when viewed from the outside is drastically reduced. Since the dummy patterns themselves form a kind of grating, intervals (pitches) between the plurality of dummy patterns DP1and DP2different between the first aluminum wiring layer1AIL and the second aluminum wiring layer2AIL are more effective in lowering the reflectance of the mark background.

FIGS. 4D to 4Fare plan views when viewed from a surface side and a rear surface side of a portion of the wiring through electrode42with comparison to a mark portion.FIG. 4Dis a schematic plan view of an underlying layer of the second aluminum wiring layer2AIL of the wiring through electrode42when viewed from the surface side.FIG. 4Eis a schematic plan view of an overlying layer of the second aluminum wiring layer2AIL.FIG. 4Fis a schematic plan view of the rear bump44when viewed from the rear surface.

When comparingFIGS. 4A and 4BwithFIGS. 4C and 4D,FIGS. 4A and 4Bshow that the wiring tungsten pad WTP2of the mark portion has a square shape, whileFIGS. 4C and 4Dshow that the wiring tungsten pad WTP1of the wiring through electrode portion has a circular shape.

As shown inFIGS. 3A and 3B, preferably, a size of the wiring tungsten pad WTP2of the mark portion may be larger than a size of wiring tungsten pad WTP1of the wiring through electrode portion. This is because it is necessary for a size of the through electrode TSV2for a mark shown inFIG. 4Cto be larger than that of the wiring through electrode TSV1to form the rear mark314having a significantly large size to be recognized by a camera, or the like.

A method of fabricating the memory chip31according to the first embodiment of the present invention will be described.FIGS. 6A to 14are views for sequentially explaining a method of fabricating the memory chip31.

First, a fabrication step shown inFIG. 6Ashows a state in which a first interlayer insulating layer315is formed to cover a wiring tungsten layer WTL (including a wiring tungsten pad WTP2) which is a portion of a multi-layer wiring structure, an active device, and a capacitor on one surface of a semiconductor substrate319in a state in which a process of forming the wiring tungsten layer WTL, the active device, and the capacitor on one surface (a surface, a circuit forming surface side) of the semiconductor substrate319is completed. Then, forming the multi-layer wiring structure is performed. A via of a first through hole (not shown inFIG. 6A) is formed.

FIG. 6Bis a schematic plan view when viewed from the surface ofFIG. 6A. The schematic plan views in the description of the fabrication method of this embodiment describe an area corresponding to a portion beneath the opening PIO formed in the polyimide PI shown inFIGS. 4A to 4C. In addition, in the schematic plan views in the description of the fabrication method of this embodiment, interlayer insulating layers will be omitted so that shapes of wiring layers can be easily seen.

A fabrication step shown inFIG. 6Cshows a growth process of a first aluminum wiring layer1AIL, and a stacked metal layer including a barrier metal, aluminum, an anti-reflection layer, and the like is grown on a first interlayer insulating layer315by a sputtering method, or the like.

In a fabrication step ofFIG. 7A, a photoresist PR is coated on the stacked metal layer by coating and a pattern is formed using a reticle, or the like. Next, in a fabrication step ofFIG. 7B, the stacked metal layer is dry-etched using the photoresist PR as a mask to form a first aluminum wiring layer1AIL. In this case, a first dummy pattern DP1is formed in an area including a portion beneath the area in which the surface mark313is formed (including an area on the wiring tungsten pad WTP2ofFIG. 7B). A second interlayer insulating layer316is formed on the first dummy pattern DP1to cover the first aluminum wiring layer1AIL including the first dummy pattern DP1. The insulating layer is an oxide layer such as SiO2. A via of a second through hole (not shown inFIG. 7B) is formed.

FIG. 7Cis a schematic plan view when viewed from the surface ofFIG. 7B. In the area including a portion on the wiring tungsten pad WTP2formed in the wiring tungsten layer WTL, a plurality of first dummy patterns DP1formed in the first aluminum wiring layer1AIL are formed.

In a fabrication step ofFIG. 8A, a pattern of a second aluminum wiring layer2AIL is formed and a third interlayer insulating layer317is formed. The process is the same as the process of forming the first aluminum wiring layer1AIL. A plurality of second dummy patterns DP2are formed in an area on the second interlayer insulating layer316including the portion beneath the area in which the surface mark313is formed. The insulating layer is an oxide layer such a SiO2. A third interlayer insulating layer317is formed to cover the second aluminum wiring layer2AIL including the plurality of second dummy patterns DP2. A via of a third through hole (not shown inFIG. 8A) is formed.

FIG. 8Bis a schematic plan view when viewed from the surface ofFIG. 8A. In an area including a portion on the wiring tungsten pad WTP2formed in the wiring tungsten layer WTL, the plurality of second dummy patterns DP2formed in the second aluminum wiring layer2AIL are formed.

In a fabrication step ofFIG. 8C, a third aluminum wiring layer3AIL including the surface mark313is formed on the third interlayer insulating layer317. A fourth interlayer insulating layer318is formed to cover the third aluminum wiring layer3AIL. The fourth interlayer insulating layer318is referred to as a passivation layer and includes a nitride layer such as dense Si3N4or an oxynitride layer such as SiON to prevent moisture to penetrate.

FIG. 8Dis a schematic plan view when viewed from the surface ofFIG. 8C. In the area including the portion on the wiring tungsten pad WTP2formed in the wiring tungsten layer WTL, the surface mark313having an L shape formed in the third aluminum wiring layer3AIL is formed. As shown inFIGS. 7C and 8A, in this embodiment, the first and second dummy patterns DP1and DP2are also formed below the surface mark313.

In a fabrication step ofFIG. 9A, a polyimide film PI, which is a resin layer, is formed on the fourth interlayer insulating layer318and an opening PIO is formed in the formed polyimide film PI to expose the surface mark313and a portion of the fourth interlayer insulating layer318covering the surface mark313.

FIG. 9Bis a schematic plan view when viewed from the surface ofFIG. 9A. The opening PIO formed in the polyimide film PI is formed in an upper area in which the surface mark313, portions of the plurality of second dummy patterns DP2, portions of the plurality of first dummy patterns DP1, and the wiring tungsten pad WTP2are formed.

In fabrication step ofFIG. 9C, a wafer support system (WSS)321formed of SiO2or the like is attached to a wafer surface in which a wiring process up to a process of forming the surface bump is completed by an adhesive320. An adhesive capable of being peeled off from the wafer by ultraviolet light or the like is used as the adhesive320.

In a fabrication step ofFIG. 10A, a rear surface of the wafer is ground to be thinned to about 50 to 20 μm. An insulating layer322including a nitride layer such as Si3N4is formed on the rear surface to prevent the rear surface from being polluted with metal. For clarity, tops and bottoms of the wafers are upside down fromFIG. 10Ato process the rear surface from this step.

In a fabrication step ofFIG. 10B, to form a through electrode TSV2for a mark, a photoresist PR is coated to form an opening pattern330.

In a fabrication step ofFIG. 11A, a dry etching process is performed using the photoresist PR as a mask to form an opening331of the through electrode TSV2for a mark up to the wiring tungsten pad WTP2.

FIG. 11Bis a schematic plan view when viewed from the rear surface side ofFIG. 11A, and square-shaped openings331aand331bare formed by the dry etching process.

In a fabrication step ofFIG. 11C, after removing the photoresist PR, a seed layer323such as Ti/Cu is formed using a sputter on the entire rear surface of the wafer including a sidewall of the opening331(331a,331b) and a portion on the wiring tungsten pad WTP2of a bottom of the through electrode TSV2for a mark.

In a fabrication step ofFIG. 12A, to form a rear bump electrode312including the rear mark314, the photoresist PR is coated to form an opening pattern332.

In a fabrication step ofFIG. 12B, a Cu plating324is grown using a seed layer323as an electrode to fill a via of the through electrode TSV2for a mark and form a pillar of the rear bump electrode312.

In a fabrication step ofFIG. 13A, SnAg is formed as the rear bump electrode312including the rear bump44by plating.

In a fabrication step ofFIG. 13B, the photoresist PR is removed and the seed layer323is further removed by a wet etching method, or the like.

FIG. 13Cis a schematic plan view when viewed from the rear surface side ofFIG. 13B. The rear mark314having an L shape is formed. Next, in a fabrication step ofFIG. 14, the wafer is demounted from the support system321by ultraviolet light.

Next, an assembly process of the semiconductor device1shown inFIG. 1will be described.FIG. 15AtoFIG. 15Care views for explaining the assembly process.

As shown inFIG. 15A, a recess unit991is formed in an adsorption level99and a memory chip (a first-level semiconductor chip)31ais placed within the recess unit991to face a circuit-forming surface upward. The memory chip31aplaced on the adsorption level99is held and fixed through vacuum suction by a vacuum apparatus (not (shown).

As shown inFIG. 15B, a memory chip (a second-level semiconductor chip)31bis stacked and mounted on the memory chip31aheld on the adsorption level99as described above through a bonding tool BT by applying weight at a high temperature, for example, about 300° C.

In this case, to align stack positions of the memory chips31aand31b, the surface mark313of the memory chip31adisposed on the adsorption level99is photographed by a substrate-side recognition camera of a flip chip bonder and a coordinate of the memory chip31aon the level is recognized. The rear mark314of the memory chip31bpicked up by a tool of the flip chip bonder is photographed by a part-side recognition camera of the flip chip bonder and a coordinate of the memory chip31bon the tool is recognized. According to the obtained position information, a position of the tool is adjusted with respect to the level and the memory chip31bis stacked and mounted so that the surface bump electrode311of the memory chip31aand the rear bump electrode312of the memory chip31baccurately overlap.

The memory chip31bhas the same type as the memory chip31aand the surface bump electrode311of one surface of the memory chip31aand the corresponding rear bump electrode312of the other surface of the memory chip31bare electrically connected by thermo-composition so that the memory chip31bis stacked and mounted on one surface side of the memory chip31a. As described above, the memory chips are connected by the bump electrodes and thus a gap is formed between the memory chips.

Similarly, memory chips (third- and fourth-level semiconductor chips)31cand31d, and an interface chip (a fifth-level semiconductor chip)32are stacked and mounted and as shown inFIG. 15C, for example, a chip stacked body3, in which the four memory chips31ato31dand the interface chip32are stacked, is formed.

In the interface chip the rear bump electrode312of the other surface side is arranged to correspond to the surface bump electrode311of the memory chip31dand the surface bump electrode311of the surface side is arranged in a wide pitch of about 60 to 200 μm to be mounted on the connection pad23of the wiring board2.

Then, an underfill is inserted and formed between the chips, and the chip stacked body3is mounted on the wiring board2and the solder ball8is attached in an assembly process, resulting in the semiconductor device1shown inFIG. 1.

In the semiconductor device of the present invention, as described above, since the first aluminum wiring layer1AIL and the second aluminum wiring layer2AIL located below the surface mark313of the memory chip31(31ato31d) form the dummy patterns DP1and DP2having sizes smaller than resolution of the recognition camera, that is, sizes which are not recognized by the recognition camera, it is possible to recognize the surface mark313with high contrast in the assembly process as compared to the related art. Here, in particular, the semiconductor device is noticeably characterized in that degradation in the contrast of the surface mark313is suppressed without adding a new process.

As described above, when the degradation in the contrast of the surface mark313is suppressed and the surface mark is easily recognized, the chips are easily aligned in the assembly process shown inFIGS. 15A to 15C.

In particular, like a chip for TSV stack, it is effective when it is necessary to arrange the wiring tungsten pad WTP below the surface mark313.

Second Embodiment

A memory chip of a second embodiment of the present invention will be described.

The configurations of the semiconductor device is the same as that of the semiconductor device1shown inFIG. 1.

The second embodiment is different from the first embodiment in that the CMP dummy patterns DP1and DP2are employed in the first embodiment shown inFIG. 4B, while stripe-shaped patterns DP21and DP22are arranged as shown inFIG. 16in the second embodiment in place of the CMP dummy patterns.

The second embodiment is the same as the first embodiment in that pitches of the stripe-shaped dummy patterns DP21and DP22are made to be different in each wiring layer.

Third Embodiment

A third embodiment of the semiconductor device of the present invention will be described.

The entire configuration of the semiconductor device is the same as that of the semiconductor device1shown inFIG. 1.

The third embodiment is different from the first embodiment in that the CMP dummy patterns DP1and DP2are employed in the first embodiment shown inFIG. 4B, while stripe-shaped patterns DP31and dummy patterns of dot patterns DP32are mixed and arranged as shown inFIG. 17in the third embodiment in place of the CMP dummy patterns.

Modifications

In the first to third embodiments described above, patterns are arranged just below the surface mark313of the prohibition area PA, but as shown inFIG. 18, the patterns may be removed from just below the surface mark313.

In the first to third embodiments described above, the surface mark313and the rear mark314have an L shape, but they are not limited thereto.FIGS. 19A to 19Dare views illustrating other examples of mark shapes. As shown inFIGS. 19A to 19D, the mark may have a cross shape313a, a square shape313b, a circular shape313c, and a right-angled triangular shape313d, respectively, or have other various shapes.

As used herein, the following directional terms “forward, rearward, above, downward, vertical, horizontal, below, and transverse” as well as any other similar directional terms refer to those directions of an apparatus equipped with the present invention. Accordingly, these terms, as utilized to describe the present invention should be interpreted relative to an apparatus equipped with the present invention.

Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.