Integrated circuity, DRAM circuitry, methods used in forming integrated circuitry, and methods used in forming DRAM circuitry

A method used in forming integrated circuitry comprises forming a plurality of conductive vias comprising conductive material. The conductive vias are spaced relative one another by intermediate material. A discontinuous material is formed atop the conductive material of the vias and atop the intermediate material that is between the vias. Metal material is formed atop, directly against, and between the discontinuous material and atop and directly against the conductive material of the vias. The metal material is of different composition from that of the discontinuous material and is above the intermediate material that is between the vias. The metal material with discontinuous material there-below is formed to comprise a conductive line that is atop the intermediate material that is between the vias and is directly against individual of the vias. Structures independent of method are disclosed.

TECHNICAL FIELD

Embodiments disclosed herein pertain to integrated circuitry, to DRAM circuitry, to methods used in forming integrated circuitry, and to methods used in forming DRAM circuitry.

BACKGROUND

Memory cells may be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods of time in the absence of power. Non-volatile memory is conventionally specified to be memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed/rewritten to maintain data storage. Volatile memory may have a retention time of milliseconds or less. Regardless, memory cells are configured to retain or store memory in at least two different selectable states. In a binary system, the states are considered as either a “0” or a “1. In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

A capacitor is one type of electronic component that may be used in a memory cell. A capacitor has two electrical conductors separated by electrically insulating material. Energy as an electric field may be electrostatically stored within such material. Depending on composition of the insulator material, that stored field will be volatile or non-volatile. For example, a capacitor insulator material including only SiO2will be volatile. One type of non-volatile capacitor is a ferroelectric capacitor which has ferroelectric material as at least part of the insulating material. Ferroelectric materials are characterized by having two stable polarized states and thereby can comprise programmable material of a capacitor and/or memory cell. The polarization state of the ferroelectric material can be changed by application of suitable programming voltages and remains after removal of the programming voltage (at least for a time). Each polarization state has a different charge-stored capacitance from the other, and which ideally can be used to write (i.e., store) and read a memory state without reversing the polarization state until such is desired to be reversed. Less desirable, in some memory having ferroelectric capacitors the act of reading the memory state can reverse the polarization. Accordingly, upon determining the polarization state, a re-write of the memory cell is conducted to put the memory cell into the pre-read state immediately after its determination. Regardless, a memory cell incorporating a ferroelectric capacitor ideally is non-volatile due to the bi-stable characteristics of the ferroelectric material that forms a part of the capacitor. Other programmable materials may be used as a capacitor insulator to render capacitors non-volatile.

A field effect transistor is another type of electronic component that may be used in a memory cell. These transistors comprise a pair of conductive source/drain regions having a semiconductive channel region there-between. A conductive gate is adjacent the channel region and separated there-from by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source/drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structure, for example a reversibly programmable charge-storage region as part of the gate construction between the gate insulator and the conductive gate. Regardless, the gate insulator may be programmable, for example being ferroelectric.

NAND may be a basic architecture of integrated flash memory. A NAND cell unit comprises at least one selecting device coupled in series to a serial combination of memory cells (with the serial combination commonly being referred to as a NAND string). NAND architecture may be configured in a three-dimensional arrangement comprising vertically-stacked memory cells individually comprising a reversibly programmable vertical transistor. Control or other circuitry may be formed below the vertically-stacked memory cells. Other volatile or non-volatile memory array architectures may also comprise vertically-stacked memory cells that individually comprise a transistor.

Capacitors and transistors may of course be used in integrated circuitry other than memory circuitry. Regardless, conductive interconnect lines are used to connect various components of integrated circuitry.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

Embodiments of the invention encompass integrated circuitry constructions, such as DRAM constructions, and methods used in forming an integrated circuitry construction, such as a DRAM circuitry construction. First example embodiments comprising a DRAM construction are described with reference toFIGS. 1-8showing an example fragment of a substrate construction8comprising an array or array area10that has been fabricated relative to a base substrate11. Substrate construction11may comprise any one or more of conductive/conductor/conducting, semiconductive/semiconductor/semiconducting, and insulative/insulator/insulating (i.e., electrically herein) materials. Various materials are above base substrate11. Materials may be aside, elevationally inward, or elevationally outward of theFIGS. 1-8—depicted materials. For example, other partially or wholly fabricated components of integrated circuitry may be provided somewhere above, about, or within base substrate11. Control and/or other peripheral circuitry for operating components within a memory array may also be fabricated and may or may not be wholly or partially within a memory array or sub-array. Further, multiple sub-arrays may also be fabricated and operated independently, in tandem, or otherwise relative one another. As used in this document, a “sub-array” may also be considered as an array.

Base substrate11comprises semiconductive material12(e.g., appropriately and variously doped monocrystalline and/or polycrystalline silicon, Ge, SiGe, GaAs, and/or other existing or future-developed semiconductive material), trench isolation regions14(e.g., silicon nitride and/or silicon dioxide), and active area regions16comprising suitably and variously-doped semiconductive material12. In one embodiment, construction8comprises memory cells75(FIGS. 4, 5, and 8, and with only four outlines75shown inFIGS. 4 and 5and only two outlines75inFIG. 8for clarity in such figures), for example DRAM memory cells individually comprising a field effect transistor device25(FIG. 3) and a storage element (e.g., a capacitor85;FIGS. 1 and 8). However, embodiments of the invention encompass other memory cells and other constructions of integrated circuitry independent of whether containing memory cells.

Example transistor devices25individually comprise a pair of source/drain regions, a channel region between the pair of source/drain regions, a conductive gate operatively proximate the channel region, and a gate insulator between the conductive gate and the channel region. Devices25are shown as being recessed access devices, with example construction8showing such recessed access devices grouped in individual pairs of such devices. Individual recessed access devices25include a buried access line construction18, for example that is within a trench19in semiconductive material12. Constructions18comprise conductive gate material22(e.g., conductively-doped semiconductor material and/or metal material, including for example elemental W, Ru, and/or Mo) that functions as a conductive gate of individual devices25. A gate insulator20(e.g., silicon dioxide and/or silicon nitride) is along sidewalls21and a base23of individual trenches19between conductive gate material22and semiconductive material12. Insulator material37(e.g., silicon dioxide and/or silicon nitride) is within trenches19above materials20and22. Individual devices25comprise a pair of source/drain regions24,26in upper portions of semiconductive material12on opposing sides of individual trenches19(e.g., regions24,26being laterally outward of and higher than access line constructions18). Each of source/drain regions24,26has at least a part thereof having a conductivity-increasing dopant therein that is of maximum concentration of such conductivity-increasing dopant within the respective source/drain region24,26, for example to render such part to be conductive (e.g., having a maximum dopant concentration of at least 1019atoms/cm3). Accordingly, all or only a part of each source/drain region24,26may have such maximum concentration of conductivity-increasing dopant. Source/drain regions24and/or26may include other doped regions (not shown), for example halo regions, LDD regions, etc.

One of the source/drain regions (e.g., region26) of the pair of source/drain regions in individual of the pairs of recessed access devices25is laterally between conductive gate material22and is shared by the pair of devices25. Others of the source/drain regions (e.g., regions24) of the pair of source/drain regions are not shared by the pair of devices25. Thus, in the example embodiment, each active area region16comprises two devices25(e.g., one pair of devices25), with each sharing a central source/drain region26.

An example channel region27(FIGS. 1, 3, 7, and 8) is in semiconductive material12below pair of source/drain regions24,26along trench sidewalls21(FIGS. 7 and 8) and around trench base23. Channel region27may be undoped or may be suitably doped with a conductivity-increasing dopant likely of the opposite conductivity-type of the dopant in source/drain regions24,26, and for example that is at a maximum concentration in the channel of no greater than 1×1017atoms/cm3. When suitable voltage is applied to gate material22of an access line construction18, a conductive channel forms (e.g., along a channel current-flow line/path29[FIG. 8]) within channel region27proximate gate insulator20such that current is capable of flowing between a pair of source/drain regions24and26under the access line construction18within an individual active area region16. Stippling is diagrammatically shown to indicate primary conductivity-modifying dopant concentration (regardless of type), with denser stippling indicating greater dopant concentration and lighter stippling indicating lower dopant concentration. Conductivity-modifying dopant may be, and would likely be, in other portions of material12as shown. Only two different stippling densities are shown in material12for convenience, and additional dopant concentrations may be used, and constant dopant concentration is not required in any region.

First conductive/conductor vias36are individually directly electrically coupled to one of the source/drain regions (e.g.,24) of the pair of source/drain regions. A storage element (e.g., capacitor85) is directly electrically coupled to individual first conductive/conductor vias36.

Second conductive vias33are individually directly electrically coupled to the other of the source/drain regions (e.g.,26) of the pairs of source/drain regions. Second vias33are spaced relative one another (e.g., longitudinally relative to a digitline39there-above as described below) by intermediate material (e.g., one of more of materials32,37,14,38,48, and/or46when present, with materials32,38,48, and46being described below) and comprise conductive material (e.g.,34and35). In one embodiment, conductive material34/35of second vias33comprises lower conductively-doped semiconductive material34(e.g., conductively-doped polysilicon) below upper conductive material35(e.g., metal material) that is of different composition from that of conductively-doped semiconductive material34. Additional example conductive materials for materials34and35, and by way of example only, comprise metal nitrides (e.g., TiN, TaN, WN, MoN), metal carbo-nitrides (e.g., TiCN, TaCN, WCN, MoCN), and elemental-form metals (e.g., Ti, Ta, W, Mo, Co, Cu, Ru, Be) including combinations, compounds, and alloys thereof.

A digitline39is atop intermediate material32,37,14,38,48,46that is between second vias33and is directly electrically coupled to individual second vias33of multiple of transistors25. Digitline39comprises metal material42(e.g., elemental W, Ru, and/or Mo) that is directly against conductive material34/35of second vias33. Example digitlines39comprise part of digitline structures30that comprises opposing longitudinal insulative sides38(e.g., silicon dioxide and/or silicon nitride) and an insulative cap50(e.g., silicon nitride and/or silicon dioxide). Example material46is below digitlines39between immediately-longitudinally-adjacent second vias33. Lower insulative material48(e.g., one or more of silicon dioxide, silicon nitride, aluminum dioxide, hafnium oxide, etc.; e.g., thickness of 50 to 200 Angstroms) is below material46between immediately-longitudinally-adjacent second vias33. Material46may be insulative, semiconductive (i.e., material that is not sufficiently doped to be conductive), or conductive or be eliminated, with metal material42extending inwardly to lower insulative material48(not shown).

In one embodiment, an uppermost portion of the intermediate material (e.g., the uppermost portion of one or both of material32and46) comprises insulative material, in one embodiment comprises conductive material, and in one embodiment comprises semiconductive material (i.e., that is not sufficiently doped to be conductive). In one embodiment if conductive, the uppermost portion of the intermediate material comprises conductively-doped semiconductive material. In one embodiment, an uppermost portion of the intermediate material comprises insulative material and conductive material. By ways of example only, example insulative materials include silicon dioxide, silicon nitride, aluminum oxide, high k materials, low k materials, hafnium oxide, zirconium oxide, and insulative metal oxides that comprise a combination of two or more elemental metals. Example conductive materials include conductively-doped polysilicon as an example conductively-doped semiconductive material, and as well metal materials. An example semiconductive material is undoped or lightly-doped polysilicon.

A discontinuous material55is vertically between digitline39and conductive material34/35of second vias33and is vertically between digitline39and intermediate material32,46that is between second vias33. Discontinuous material55is of different composition from that of metal material42of digitline39. In one embodiment and as shown, discontinuous material55comprises void space there-through (i.e., void space that is laterally between and among spaced portions of material55), with the void space having greater total horizontal area than total horizontal area of the material of discontinuous material55. In one embodiment, the discontinuous material is insulative, in one embodiment is conductive, in one embodiment is semiconductive, and in one embodiment comprises elemental-form silicon. In one embodiment, discontinuous material55comprises elemental-form metal (e.g., Ti, Ta, W, Mo, Co, Cu, Ru, Be), and in one embodiment is of different composition from that of conductive material34/35.

Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

Embodiments of the invention encompass an integrated circuitry construction (e.g.,8) independent of whether comprising DRAM or other memory circuitry. Such a construction comprises a plurality of conductive vias (e.g.,33) that are spaced relative one another by intermediate material (one of more of materials32,37,14,38,48, and/or46when present). A conductive line (e.g.,39) is atop the intermediate material that is between the vias and directly electrically couples to individual of the vias. The conductive line comprises metal material (e.g.,42) directly against conductive material (e.g.,34/35) of the vias. A discontinuous material (e.g.,55) is vertically between the conductive line and the conductive material of the vias and is vertically between the conductive line and the intermediate material that is between the vias. The discontinuous material is of different composition from that of the metal material. In one embodiment, the conductive line is part of memory circuitry comprising NAND architecture (e.g., a digitline). Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

Embodiments of the invention encompass methods used in forming an integrated circuitry construction, for example comprising DRAM, other memory, and/or non-memory circuitry. Regardless, method aspects of the invention may use or have any of the attributes as described herein in structure and/or device embodiments. Likewise, the above-described structure embodiments may incorporate any of the attributes described with respect to method embodiment aspects.

An example method embodiment, and an example such embodiment for producing construction8ofFIGS. 1-8, is described initially with reference toFIGS. 9-29. Referring toFIGS. 9 and 10, such show a predecessor construction to that ofFIGS. 1 and 7wherein construction8has been fabricated to a point of comprising materials46and48within array10.FIGS. 11-13show openings56as having been formed there-thorough to source/drain regions26and, in one embodiment as shown, to an elevation that is below the bottom of material48.

Referring toFIGS. 14-16, openings56have been lined with insulative material32, followed by example anisotropic etching thereof to remove material32from being centrally over source/drain regions26. Conductive material34/35has subsequently been formed and planarized back at least to the elevationally-outermost surfaces of materials46and32. Such comprises but one example of forming conductive vias33that are individually directly electrically coupled to one of the source/drain regions (e.g.,26) of the pair of source/drain regions. Conductive vias33are spaced relative one another by intermediate material (e.g., one of more of materials32,37,14,48, and/or46when present) and comprise conductive material34/35. In one such embodiment, the method sequentially comprises forming lower conductively-doped semiconductive material (e.g.,34) within openings56in the intermediate material. For example, such may be formed to completely fill remaining volume of openings56and then planarized back at least to elevationally outermost surfaces of materials32and46. Conductively-doped semiconductive material34is then vertically recessed within openings56(e.g., by etching). Conductor material35is thereafter formed within openings56atop the vertically-recessed conductively-doped semiconductive material34, for example to overfill remaining volume of openings56and then planarized back at least to elevationally outermost surfaces of materials32and46.

Referring toFIGS. 20-22, metal material42has been formed atop, directly against, and between discontinuous material55and atop and directly against conductive material34/35of conductive vias33and above intermediate material32and46that is between conductive vias33. Discontinuous material55may function as a crystalline-growth seed material to facilitate growth of metal material42such that metal material42is formed in a desired crystalline orientation/phase. Example insulative material50has been formed there-atop.

Referring toFIGS. 23-25, metal material42with discontinuous material55there-below has been formed (e.g., by subtractive etching) to comprise a digitline39that is atop intermediate material32and46that is between conductive vias33and is directly against individual conductive vias33of multiple transistors25. For example, and in one embodiment, multiple digitlines39have been formed by subtractive patterning and etching, with in one example the etching removing discontinuous material55from being laterally between lines39.

Referring toFIGS. 26-28, insulative spacers38have been formed resulting in formation of digitline structures30and dielectric material40has been deposited there-between.FIG. 29shows forming of openings41there-through to source/drain regions24. Subsequent processing would occur to produce the construction as shown inFIGS. 1-8. For example, conductor vias36would be formed in openings41to be individually directly electrically coupled to other source/drain regions24of the pairs of source drain regions. A storage element, such as a capacitor85, would be formed to be directly electrically coupled to individual of conductor vias36.

Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

The above-described example processing and depicted construction shows the forming of multiple digitlines39that are laterally spaced relative one another, with the discontinuous material not being laterally between such multiple digitlines39. For example,FIGS. 23-25show removal of discontinuous material55from between digitlines39. Alternately, the discontinuous material may be laterally between the multiple digitlines, for example as shown and described relative to an alternate embodiment method and an alternate embodiment structure embodiment nFIGS. 30-32with respect to a construction8a. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences being indicated with the suffix “a”.

Referring toFIGS. 30 and 31, the patterning of metal material42to form digitlines39has left discontinuous material55laterally there-between.FIG. 32shows subsequent processing whereby discontinuous material55so-remains horizontally outside of conductive/conductor vias36. In one embodiment, discontinuous material55is not insulative (e.g., elemental silicon) and the method further comprises transforming (e.g., by anneal in an oxygen-containing ambient) discontinuous material55that is not insulative to be insulative laterally between said multiple conductive lines. For example, and by way of examples only, elemental silicon as material55could be annealed in an oxygen-containing ambient to form silicon dioxide material55or a conductive material55could be coated with a non-conductive material. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

Embodiments of the invention encompass methods used in forming integrated circuitry independent of whether such circuitry is DRAM or other memory circuitry. Such a method comprises forming a plurality of conductive vias (e.g.,33) comprising conductive material (e.g.,34/35). The conductive vias are spaced relative one another by intermediate material (e.g., one of more of materials32,37,14,38,48, and/or46when present). A discontinuous material (e.g.,55) is formed atop the conductive material of the vias and atop the intermediate material that is between the vias. Metal material (e.g.,42) is formed atop, directly against, and between the discontinuous material and atop and directly against the conductive material of the vias. The metal material is of different composition from that of the discontinuous material and is above the intermediate material that is between the vias. The metal material with discontinuous material there-below is formed to comprise a conductive line (e.g.,39) that is atop the intermediate material that is between the vias and is directly against individual of the vias. Any other attribute(s) or aspect(s) as shown and/or described herein with respect to other embodiments may be used.

The above processing(s) or construction(s) may be considered as being relative to an array of components formed as or within a single stack or single deck of such components above or as part of an underlying base substrate (albeit, the single stack/deck may have multiple tiers). Control and/or other peripheral circuitry for operating or accessing such components within an array may also be formed anywhere as part of the finished construction, and in some embodiments may be under the array (e.g., CMOS under-array). Regardless, one or more additional such stack(s)/deck(s) may be provided or fabricated above and/or below that shown in the figures or described above. Further, the array(s) of components may be the same or different relative one another in different stacks/decks. Intervening structure may be provided between immediately-vertically-adjacent stacks/decks (e.g., additional circuitry and/or dielectric layers). Also, different stacks/decks may be electrically coupled relative one another. The multiple stacks/decks may be fabricated separately and sequentially (e.g., one atop another), or two or more stacks/decks may be fabricated at essentially the same time.

The assemblies and structures discussed above may be used in integrated circuits/circuitry and may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

Further, “directly above”, “directly below”, and “directly under” require at least some lateral overlap (i.e., horizontally) of two stated regions/materials/components relative one another. Also, use of “above” not preceded by “directly” only requires that some portion of the stated region/material/component that is above the other be elevationally outward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components). Analogously, use of “below” and “under” not preceded by “directly” only requires that some portion of the stated region/material/component that is below/under the other be elevationally inward of the other (i.e., independent of whether there is any lateral overlap of the two stated regions/materials/components).

Any of the materials, regions, and structures described herein may be homogenous or non-homogenous, and regardless may be continuous or discontinuous over any material which such overlie. Where one or more example composition(s) is/are provided for any material, that material may comprise, consist essentially of, or consist of such one or more composition(s). Further, unless otherwise stated, each material may be formed using any suitable existing or future-developed technique, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implanting being examples.

The composition of any of the conductive/conductor/conducting materials herein may be metal material and/or conductively-doped semiconductive/semiconductor/semiconducting material. “Metal material” is any one or combination of an elemental metal, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compound(s).

Herein, “selective” as to etch, etching, removing, removal, depositing, forming, and/or formation is such an act of one stated material relative to another stated material(s) so acted upon at a rate of at least 2:1 by volume. Further, selectively depositing, selectively growing, or selectively forming is depositing, growing, or forming one material relative to another stated material or materials at a rate of at least 2:1 by volume for at least the first 75 Angstroms of depositing, growing, or forming.

Unless otherwise indicated, use of “or” herein encompasses either and both.

CONCLUSION

In some embodiments, a method used in forming integrated circuitry comprises forming a plurality of conductive vias comprising conductive material. The conductive vias are spaced relative one another by intermediate material. A discontinuous material is formed atop the conductive material of the vias and atop the intermediate material that is between the vias. Metal material is formed atop, directly against, and between the discontinuous material and atop and directly against the conductive material of the vias. The metal material is of different composition from that of the discontinuous material and is above the intermediate material that is between the vias. The metal material with discontinuous material there-below is formed to comprise a conductive line that is atop the intermediate material that is between the vias and is directly against individual of the vias.

In some embodiments, a method used in forming DRAM circuitry comprises forming transistors individually comprising a pair of source/drain regions, a channel region between the pair of source/drain regions, a conductive gate operatively proximate the channel region; and a gate insulator between the conductive gate and the channel region. Conductive vias are formed that individually directly electrically couple to one of the source/drain regions of the pairs. The conductive vias are spaced relative one another by intermediate material and comprise conductive material. A discontinuous material is formed atop the conductive material of the conductive vias and atop the intermediate material that is between the conductive vias. Metal material is formed atop, directly against, and between the discontinuous material and atop and directly against the conductive material of the conductive vias. The metal material is of different composition from that of the discontinuous material and is above the intermediate material that is between the conductive vias. The metal material is formed with discontinuous material there-below to comprise a digitline that is atop the intermediate material that is between the conductive vias and is directly against individual of the conductive vias of multiple of the transistors. Conductor vias are formed that individually directly electrically couple to the other source/drain regions of the pairs. A storage element is formed directly electrically coupled to individual of the conductor vias.

In some embodiments, integrated circuitry comprises a plurality of conductive vias comprising conductive material. The conductive vias are spaced relative one another by intermediate material. A conductive line is atop the intermediate material that is between the vias and directly electrically couples to individual of the vias. The conductive line comprises metal material directly against the conductive material of the vias. A discontinuous material is vertically between the conductive line and the conductive material of the vias and is vertically between the conductive line and the intermediate material that is between the vias. The discontinuous material is of different composition from that of the metal material.

In some embodiments, DRAM circuitry comprises transistors individually comprising a pair of source/drain regions, a channel region between the pair of source/drain regions, a conductive gate operatively proximate the channel region, and a gate insulator between the conductive gate and the channel region. First conductive vias individually directly electrically couple to one of the source/drain regions of the pairs. A storage element directly electrically couples to individual of the first conductive vias, and second conductive vias individually directly electrically couple to the other of the source/drain regions of the pairs. The second conductive vias are spaced relative one another by intermediate material and comprise conductive material. A digitline is atop the intermediate material that is between the second vias and directly electrically couple to individual of the second vias of multiple of the transistors. The digitline comprises metal material directly against the conductive material of the second vias. A discontinuous material is vertically between the digitline and the conductive material of the second vias and is vertically between the digitline and the intermediate material that is between the second vias. The discontinuous material is of different composition from that of the metal material.