Die-to-die power consumption optimization

Power consumption of electronic components is reduced, particularly in a multi-chip package. Embodiments reduce parasitic capacitance of a semiconductor chip by reducing ESD protection circuitry that is not needed during operation of the package. ESD protection circuitry would be operational during production and/or testing of the chip, but some circuitry would be disabled or removed prior to normal operation of the multi-chip package.

TECHNICAL FIELD

This application is related in general to multi-chip packages, and in specific to systems and methods of reducing and/or optimizing power consumption in multi-chip packages.

BACKGROUND

Many systems now use device packages that comprise multiple chips or dies mounted in a single package. Such packages are referred to as system-in-package (SiP) devices.FIG. 1depicts a conventional arrangement of a SiP package14. The package14comprises two chips10and11. Each die10,11may comprise one or more contacts16that connect the die10,11to contacts17on the package14, and then the exterior of the package14. Each die10,11may comprise one or more die-to-die (D2D) connections15that connect the two die10and11with each other. Each die may have one or more contacts12and13for the D2D connections15.

In general, chips are very susceptible to damage or destruction from electrostatic discharge (ESD). ESD occurs when there is a voltage difference between the chip and another object that is brought into contact with the chip. The voltage difference results in a high voltage discharge that damages the circuits on the chip. Since a layer of glass conventionally covers the active areas of the chip, the discharge conventionally enters the chip through the contacts12,13,16.

Consequently, each of the contacts12,13,16is conventionally protected with one or more ESD protection circuits. Examples of such circuits are shown inFIGS. 2A and 2B.

FIG. 2Adepicts a conventional output contact12and its related circuitry. Both the contact and its circuitry are located on the die10. The contact pad12is connected to driver20that provides the signal that is to be sent out over the contact12. Paired diodes21comprise the ESD circuit that is used to shunt a voltage discharge. For example, the diodes21may protect against human body model (HBM) type discharges. HBM type discharges are discharges caused by contact with a human.

FIG. 2Bdepicts a conventional input contact13and its related circuitry. Both the contact13and its circuitry are located on the die11. The contact pad13is connected to input receiver20that provides the signal that is to be used inside of die11. Paired diodes21and23comprise the primary ESD circuits that are used to shunt a voltage discharge. For example, diodes21may protect against primary discharge events, such as human body model (HBM) type discharges. Furthermore, diodes23serve as secondary protection circuitry, and may protect against secondary discharge events, such as charge device model (CDM) type discharges. CDM type discharges result from contact with another electronic device. Note that the resistor22is part of the secondary protection circuitry and limits current.

BRIEF SUMMARY

Various embodiments as described herein may be used to improve the operations of electronic devices. Devices, systems, and methods described herein may lead to improved power consumption of electronic devices.

One example embodiment is a semiconductor wafer that comprises at least one chip; and at least one electrostatic discharge (ESD) circuit associated with the chip. The ESD circuit is operable to protect the chip from an ESD event only during fabrication, and/or testing of the chip.

In another embodiment, a semiconductor wafer includes at least one chip, and at least one electrostatic discharge (ESD) circuit located on the chip. The ESD circuit is operable to protect the chip from an ESD event only during fabrication and/or testing of the chip. The wafer also includes at least one switch that disables the ESD circuit subsequent to fabrication of the chip.

Another example embodiment is a multi-chip package having a chip with a first port for handling an electrical signal, and an electrical path that is associated with the first port; and a second chip having a second port for handling the electrical signal. The first port and the second port are connected to each other to form a die-to-die connection within the package. The electrical path was connected to an ESD circuit such that the ESD circuit was operable to protect the first chip only during fabrication, and/or testing of the first chip and is not operable with the first chip residing in the package.

A further example embodiment is a process for forming an electronic device that comprises forming a chip on a wafer; forming an ESD circuit on the wafer that is electrically connected to a portion of the chip; maintaining the electrical connection between the chip and the ESD circuit for a portion of the process; and cutting the electrical connection prior to placing the chip in a package to form the electronic device.

DETAILED DESCRIPTION

Embodiments described herein involve reducing and/or optimizing power consumption in multi-chip packages, e.g., system in package (SiP) packages. The multi-chip packages may include through-silicon-stacked (TSS) packages and stacked die. The multi-chip package may include all analog/RF chips, all digital chips, and/or a combination of one or more analog/RF chips and one or more digital chips.

Embodiments described herein note that the ESD protection circuitry can consume significant amounts of power because of the parasitic capacitance imposed on the SiP package from the ESD protection circuitry. The power consumed by parasitic capacitance of ESD protection circuitry may be approximated by P˜fCV2, where f is the frequency or clock rate, C is the parasitic capacitance, and V is the voltage. Thus, reducing the capacitance will reduce the power consumption.

Embodiments described herein may be used in any electronic device, but are particularly useful in portable devices that use a battery for power. A reduction in power consumption will increase the operational time of the device before a recharge or battery replacement is needed. Such portable devices may include telephones, music/video players, portable computers, personal data assistant devices, hand-held diagnostic equipment, e-mail receivers, data recorders, game devices, or cameras.

Embodiments described herein note that some contacts, for example, die-to-die (D2D) contacts, will likely not be touched by humans, and thus do not use HBM type ESD protection when in a completed package. In other words, because the D2D contacts are not exposed to the outside world after packaging, HBM and/or CDM ESD will likely not occur on the D2D contacts. Embodiments described herein note that some contacts, for example D2D contacts, do not use ESD protection beyond intermediate device production/testing. In other words, some contacts do not use any ESD protection, either HBM or CDM types, during normal operation of the SiP package, but would only use CDM type ESD protection during production, e.g. wafer test or other testing procedures.

Embodiments described herein may not use HBM type ESD protection for one or more D2D contacts. Other embodiments may use minimal HBM type ESD protection for one or more D2D contacts, e.g. by reducing the size of the HBM diodes that would be conventionally used.

Embodiments described herein provide certain types of ESD protection until singulation of the die, at which time the ESD protection changes. One embodiment uses gates or switches to control the availability of ESD protection. During some production or fabrication steps, e.g. wafer testing or other times when the contact is exposed, the ESD protection may be connected to a test pad via one or more switches. During normal operation of the completed package, the one or more gates may switch the ESD protection out of connection with the test pad. One arrangement is to have multiple contact pads, with one pad being used for probing and having associated ESD protection, and another pad being used for SiP package operation. The switches would control which pad is connected to the die, and thus operational. Another arrangement is to have the switches located between the ESD diodes and the contact. During production, the switches would connect the ESD diodes with the contact. During operation, the switches would disconnect the ESD diodes from the contact.

Note that some embodiments use a larger driver in the production contact pad path, and a smaller driver in the operations contact pad path. During testing, when an ESD event is most likely and the primary diodes are connected (primary diodes are larger than the secondary diodes), large drivers operate. After testing, and when the circuitry is not exposed, the switches are switched so that small drivers operate, and the primary diodes are off. Thus, less drive voltage is needed saving power. Note that the secondary diodes and the resistor, if present, are on the same path. Only the primary diodes should be switched on or off.

Other embodiments provide ESD protection during production of the package while placing some or all of the ESD protection on a portion of the wafer that will be separated from the chip during production. For example, the ESD protection may be placed in the scribe lane or saw street of the wafer. Thus, the ESD protection is available during production of the chip while the chip is a part of the wafer. One of the last production steps is to cut the chip from the wafer, at which time the ESD protection is cut away from the chip.

Other embodiments may use combinations of all or some of the embodiments described herein to reduce the power consumption of the SiP package. Embodiments described herein recognize that it may be beneficial to maintain some ESD protection, even for D2D contacts. Thus, some embodiments may be used to reduce the ESD protection during operation of the SiP, rather than completely remove it. For example, the switch may switch from larger ESD protection during production to a lesser amount during operation. Similarly, some ESD protection may be located in the scribe lane, while other ESD protection remains on chip. Thus, this will reduce power consumption without affecting device yield, and therefore optimize power consumption.

FIG. 3depicts an arrangement of chips that reduces power consumption during operation of the chips. In this arrangement, each chip30,31has one or more D2D contacts comprising two contact pads, one pad12,13used during production/probing of the chip, and the second pad32,33used during operation of the chip.

In the chip30, switches36aand36bare used to connect the proper contact to the remainder of the chip. As shown, the remainder of the chip is an IN port that either sends or receives a signal, either power or data, to or from the chip30. Note that the switches may comprise active elements (e.g. logic gates or transistors), or passive elements (e.g. connections configured to break). Similarly, the chip31includes switches36aand36bto connect the proper contact to the remainder of the chip.

Note that in this arrangement, the chip30also includes a second driver37. The second driver may use less power and/or may have less capacitance than the driver20. In some instances, a smaller driver may be needed for operation, while a larger driver may be needed for production/probing (e.g., testing). Note that this is by way of example only, as the chip30may have only a single driver. For such an arrangement, the switches36a,36bwould be located between the driver20and the contacts32and12, similar to what is shown in the chip31.

Also note that in this arrangement, the chip31has some ESD protection during operation for illustrative purposes. Thus, during production/probing (or testing), the chip31would have ESD protection from both the primary circuit21and secondary protection23, as well as the resistor22. During operation, the primary circuit21is effectively switched off by opening the switch36dand closing the switch36c, leaving the secondary circuit23and resistor22to provide ESD protection for the chip31. Consequently, during operation a lesser amount of ESD protection is required, and thus by using a lesser amount of ESD protection, the capacitance of the die31is reduced. Similarly, during operation of the chip30, the circuit21and the large driver20are effectively switched off by opening the switch36band closing the switch36a, reducing capacitance and power drain of the die30.

Note that in this arrangement, all of the primary (e.g., HBM) ESD protection may have been removed from the D2D connections. Thus, the circuit23may be of the secondary (e.g., CDM) ESD type.

FIGS. 4A and 4Bdepict other arrangements for chips that reduce power consumption during operation of the chips. InFIG. 4A, the chip40has one or more contacts12that includes ESD protection circuitry21that is located in the scribe lane or saw street42of the wafer upon which the chip40is formed. During production/probing of the chip40, while still a part of the wafer, the ESD protection circuitry is operable to protect the chip40from an ESD event. Thus, the chip may be processed, handled, and/or tested with the chip40being protected against ESD discharges from entering through the contact12. When the chip40has been separated from the wafer, connection with the ESD protection circuitry21will have been cut, and thus during operation, the chip40will not suffer the capacitance and associated power drain of the circuitry21. The design/layout should account for imprecise cutting that may short signals during cutting.

InFIG. 4B, the chip41has one or more contacts13that includes the ESD protection circuitry21located in the scribe lane or saw street43of the wafer upon which the chip41is formed. Also note that in this arrangement, the chip41has some ESD protection22,23during operation for illustrative purposes. Thus, during production/probing (or testing), the chip41would have ESD protection from the circuits21,22, and23. During operation, the circuit21is cut away, leaving the circuits22and23to provide ESD protection for the chip41. Consequently, during operation a lesser amount of ESD protection is used, and thus the capacitance of the chip is reduced.

Note that in this arrangement, all of the primary (HBM) ESD protection may have been removed from the D2D connections. Thus, the circuit23may be of the secondary (CDM) ESD type. Other embodiments may use a reduced amount of primary (HBM) type ESD protection.

Another embodiment may have ESD circuitry located in one or more waste portions of the wafer. Thus, while not located in the scribe lane, the ESD circuitry will still be separated from the chip during the die cut portion of the production process.

Note that the embodiments have been depicted using paired diodes as the ESD circuit, however the embodiments described herein will operate with any type of ESD circuit, including those types that have a parasitic capacitance.

Further note that the embodiments have been described being associated with ESD circuits having a parasitic capacitance, however, the embodiments described herein will operate for any type of power draining ESD circuit.

The embodiments have been described being associated with ESD circuits, however, the embodiments described herein will operate for any type of power draining circuit, or other circuit that is needed for a portion of the fabrication process, but is not needed for normal operations of a packaged device.