Power factor correction autodetect

A power supply system includes an Offline Total Power Management Integrated Circuit (OTPMIC). The OTPMIC controls a Power Factor Correction (PFC) converter, a main AC/DC converter, and a standby AC/DC converter. A PFC Autodetect circuit in the OTPMIC monitors current flow in the PFC converter. If a high power condition is detected, then the PFC Autodetect circuit enables the PFC converter. The high power condition may be a voltage drop across a current sense resistor of a predetermined voltage for a predetermined time, within one half period of the incoming AC supply voltage. If a low power condition is detected, then the PFC Autodetect circuit disables the PFC converter. The PFC Autodetect circuit stores an IMON value that determines the predetermined voltage, and a TMON value that determines the predetermined time. The IMON and TMON values are loaded into the Autodetect circuit across an optocoupler link of the standby converter.

TECHNICAL FIELD

The described embodiments relate generally to power factor correction in power supply circuits.

BACKGROUND INFORMATION

In some applications, an AC-to-DC power supply is required that receives a single AC (Alternative Current) supply voltage and outputs multiple DC (Direct Current) supply voltages. Some of the DC supply voltages are to be supplied from the power supply at relatively high powers, whereas others may not need to be supplied at such high powers. In some instances, power factor correction is required such that the waveform of the current drawn by the power supply is made to be in phase with the phase of the waveform of the voltage received by the power supply. Improvements in such power supply circuits are desired.

SUMMARY

A power supply system includes an input electromagnetic interference (EMI) filter, a bridge rectifier, and an input smoothing capacitor, and a novel Offline Total Power Management Integrated Circuit (OTPMIC). The OTPMIC includes a Power Factor Correction (PFC) control circuit portion that controls an external PFC boost converter circuit. The OTPMIC also includes a main AC/DC control circuit portion that controls an external main AC/DC converter circuit. The OTPMIC also includes a standby AC/DC control circuit portion that controls an external standby AC/DC converter circuit.

The EMI filter, the bridge rectifier, the input smoothing capacitor, the PFC control circuit portion and the external PFC circuit together form a PFC boost converter AC/DC converter. When enabled, the PFC boost converter receives an input AC supply voltage (for example, 110 volts AC RMS 60 Hertz wall power) and outputs a 400 volt DC supply voltage. When disabled, the PFC boost converter receives the input AC supply voltage but only performs peak rectification, and outputs a peak rectified DC supply voltage. If, for example, the input AC supply voltage is a 110 volt AC signal, then the peak rectified output DC supply voltage is about 156 volts.

The EMI filter, the bridge rectifier, the input smoothing capacitor, the PFC AC/DC converter, the main AC/DC control circuit portion and the external main AC/DC converter circuit together form a main AC/DC converter. The main AC/DC control portion and external main AC/DC converter circuitry of the AC/DC converter receives the DC supply voltage from the output of the PFC boost converter (either 400 volts DC if PFC is on or 156 volts DC if PFC is off). The main AC/DC control portion and external main AC/DC converter circuitry of the AC/DC converter then outputs a first DC supply voltage at a relatively high power. The main AC/DC converter can be turned on and turned off.

The EMI filter, the bridge rectifier, the input smoothing capacitor, the PFC AC/DC converter, the standby AC/DC control portion and the external standby AC/DC converter circuit together form a standby AC/DC converter. The standby AC/DC control portion and external standby AC/DC circuitry of the standby AC/DC converter receives the DC supply voltage from the output of the PFC boost converter (either 400 volts DC or 156 volts DC). The standby AC/DC control portion and external standby AC/DC circuitry of the standby AC/DC converter then outputs a second DC supply voltage at a relatively low power. Typically the standby AC/DC converter is not turned off if the power supply system is operating. The main AC/DC converter, however, may be turned off if it is not required.

In one novel aspect, the PFC control circuit portion of the OTPMIC includes a current sense amplifier circuit, a PFC Pulse Width Modulator (PWM), and a novel PFC Autodetect circuit. The novel PFC Autodetect circuit supplies an enable/disable signal EN/DISB to the PFC PWM. If the EN/DISB signal has a first digital logic value, then the PFC PWM operates to control a switch of the external PFC circuit so that the switch is pulse width modulated and so that the external PFC circuit operates as a boost AC/DC converter having a PFC functionality. If the EN/DISB signal has a second digital logic value, then the PFC pulse width modulator is disabled and does not control the switch to switch. The switch remains off. Rather than operating as a boost converter, the external PFC circuit operates as a peak rectifier.

The PFC Autodetect circuit is operable in a PFC Autodetect mode. In the PFC autodetect mode, if the PFC Autodetect circuit is initially in an autodetect state in which it is disabling the PFC PWM, then the PFC Autodetect circuit monitors current flow in the external PFC circuit. Current flow may be monitored by monitoring a voltage drop across a current sense resistor RSENSE in the main current path within the external PFC circuit. If a high power condition is detected, then the PFC Autodetect circuit switches autodetect state so that the PFC Autodetect circuit asserts the EN/DISB signal high and enables the PFC PWM. In one example, the high power condition is detected as follows. If, in a half period of the incoming AC supply voltage the voltage drop across the sense resistor RSENSE is detected to exceed a first predetermined voltage continuously for a predetermined amount of time, then the PFC Autodetect circuit determines that the high power condition has been detected.

In the PFC autodetect mode, if the PFC Autodetect circuit is in the autodetect state in which the PFC PWM is enabled, then the PFC Autodetect circuit monitors the current flow in the external PFC circuit. If a low power condition is detected, then the PFC Autodetect circuit switches the autodetect state so that the PFC Autodetect circuit asserts the EN/DISB to a low digital logic level and disables the PFC pulse width modulator. One example of detecting such a low power condition is as follows. If the voltage drop across the sense resistor RSENSE is detected to remain below a second predetermined voltage throughout each half period of six consecutive half periods of the incoming AC supply voltage, then the PFC Autodetect circuit determines that the low power condition is detected.

In one example, the novel PFC Autodetect circuit has a PFC ON bit and a PFC OFF bit. If the PFC OFF bit is set, then the PFC Autodetect circuit outputs the EN/DISB signal to disable the PFC pulse width modulator regardless of the value of the PFC ON bit. If the PFC ON bit is set and the PFC OFF bit is cleared, then the PFC Autodetect circuit outputs the EN/DISB signal to enable the PFC pulse width modulator. If the PFC ON bit is cleared and the PFC OFF bit is cleared, then the PFC Autodetect circuit operates in the PFC autodetect mode described above.

In one example, the PFC Autodetect circuit stores a multi-bit digital value IMON. The IMON value determines the first predetermined voltage. The first predetermined voltage may, for example, be a voltage proportional to the digital value of IMON. The second predetermined voltage may be fixed fraction (for example, one sixth) of the first predetermined voltage. The PFC Autodetect also stores a multi-bit digital value TMON. The TMON value determines the predetermined about of time. The predetermined amount of time may, for example, be the period of an 8 kHz clock signal multiplied by the digital value of TMON.

In one example, the standby AC/DC converter has an optocoupler link between the secondary side of the standby AC/DC converter and the primary side of the AC/DC converter. Digital information is sent by a processor powered from the standby power supply voltage, and is communicated across this optocoupler link along with analog feedback information, to the OPTMIC. On the OPTMIC the analog feedback information is used by the standby AC/DC control circuit portion for voltage regulation purposes in the standby AC/DC converter. On the OPTMIC the digital information is communicated to the PFC control circuit portion. In one example the digital information includes the IMON value, the TMON value, the PFC ON bit value and the PFC OFF bit value. Once received, these digital values are then stored in appropriate registers and flip-flops in the PFC control circuit portion. The processor that is powered from the standby supply voltage can therefore configure and control the PFC Autodetect circuit even if the main AC/DC converter is turned off.

Further details and embodiments and techniques are described in the detailed description below. This summary does not purport to define the invention. The invention is defined by the claims.

DETAILED DESCRIPTION

FIG. 1is a simplified diagram of a power supply system1. System1includes AC supply voltage input terminals2and3, a first voltage output terminal4and ground terminal5, a second voltage output terminal6and ground terminal7, a digital input terminal8, an Offline Total Power Management Integrated Circuit (OTPMIC)9, an EMI filter10, a full bridge rectifier11, an input smoothing capacitor12, an external Power Factor Correction (PFC) circuit13, an external main AC/DC converter circuit14, and an external standby AC/DC converter circuit15. The circuits13,14and15are “external” in the sense that they are external to the OTPMIC9.

OTPMIC9includes a PFC control circuit portion16, a main AC/DC control circuit portion17, and a standby AC/DC control circuit portion18. The PFC control circuit portion16controls the external PFC circuit13so that together the circuits10,11,12,16and13form a boost AC/DC converter. External AC/DC circuit106is the external portion of this boost AC/DC converter. The phase of the waveform of the current that the boost AC/DC converter draws from input terminals2and3substantially matches the phase of the sinusoidal 110 volt RMS AC supply voltage waveform on terminals2and3. If the external PFC circuit13is enabled, then the external PFC circuit13outputs a rough 400 volt DC supply voltage VBUS19onto output node and conductor20. If, however, the external PFC circuit13is disabled when the power supply1is powered, then the external PFC circuit13outputs a peak rectified version of the AC input supply voltage onto conductor20. Where the AC input supply voltage is a 60 Hertz, 110 volt AC RMS signal, the voltage output onto conductor20is a 156 volt DC signal. When the external PFC circuit13is disabled, it is not performing power factor correction control of the phase of the current being drawn from the 110 VAC input terminals2and3.

The main AC/DC control circuit portion17controls the external main AC/DC converter circuit14so that together the circuits10,11,12,16,13,17and14form what is referred to here as the main AC/DC converter. If enabled, the external main AC/DC converter circuit14receives power (either 400 volts DC or 156 volts DC) from conductor20and outputs the supply voltage VOUT24onto VOUT terminal4. The main AC/DC converter circuit14here actually receives a rough DC voltage and outputs a DC voltage and in that sense is a DC/DC converter circuit, but circuit14is nonetheless referred to here as an AC/DC converter circuit because it is part of the overall main AC/DC converter. VOUT in this case is 24 volts DC. The vertical dashed line21inFIG. 1indicates the secondary side of the main AC/DC converter that is isolated from the primary side of the main AC/DC converter. An optocoupler link22between the secondary side and the primary side provides feedback back to the main AC/DC control circuit portion17. The main AC/DC control circuit portion17uses the feedback signal for output voltage regulation purposes.

The standby AC/DC control circuit portion18controls the external standby AC/DC converter circuit15so that together circuits10,11,12,16,13,18and15form a standby AC/DC converter. The standby AC/DC converter circuit is a “standby” converter in the sense that it continues to output a VISO voltage supply signal23(for example, 5 volts DC) throughout the time that the system1is powered, regardless of whether the main AC/DC converter circuit is disabled or is not disabled. If the main AC/DC converter is enabled, then the main AC/DC converter outputs the VOUT voltage supply signal24(for example, 12 volts DC). If disabled, then main AC/DC converter circuit does not output the VOUT voltage supply signal24. The standby AC/DC converter has a smaller output power capability as compared to the larger output power capability of the main AC/DC converter. The standby AC/DC converter may for example be rated to output ten watt maximum, whereas the main AC/DC converter may be rated to output five hundred watts maximum. The external standby AC/DC converter circuit15receives power (either 400 volts DC or 156 volts DC) from conductor20and outputs the supply voltage signal VISO23onto terminal6. As in the case of the main AC/DC converter circuit discussed above, the standby AC/DC converter circuit15here actually receives a rough DC voltage and outputs a DC voltage and in that sense is a DC/DC converter circuit, but circuit15is nonetheless referred to here as an AC/DC converter circuit because it is part of the overall standby AC/DC converter. InFIG. 1, the vertical dashed line21indicates the secondary side of the standby AC/DC converter that is isolated from the primary side. Note that the ground symbols used on the right side of line21are different from the ground symbols used on the left side of line21. An optocoupler link25extends between the secondary side and the primary side and provides analog feedback back to the standby AC/DC control circuit portion18. The standby AC/DC control circuit portion18uses the analog feedback signal for output voltage regulation purposes. In addition, as set forth in more detail below, a digital signal DS is communicated across the optocoupler link and is used to setup and control a novel PFC Autodetect circuit107located within the PFC control portion16of OTPMIC9.

FIG. 2is a more detailed diagram of the system1ofFIG. 1. In the particular example illustrated, the main AC/DC converter has an LLC resonant converter topology. In the particular example illustrated, the standby AC/DC converter has a flyback converter topology.

FIG. 3is a more detailed diagram of the power factor correction boost converter ofFIGS. 1 and 2. The PFC control circuit portion16of the offline total power management IC9includes a current sense amplifier circuit26, a PFC Pulse Width Modulator (PWM)27, and the novel PFC Autodetect circuit107. The 110 volt AC supply voltage59received via terminals2and3is filtered by EMI filter10and is full wave rectified by bridge rectifier11to generate a full wave and peak rectified signal VHV58on input node and conductor28. When switch29is turned on, an increasing current is made to flow from the conductor28, through inductor30, through the switch29, and through a sense resistor RSENSE31. As this current increases, energy is stored in the inductor. The switch29is then turned off. Continued current flow through inductor30now flows through the inductor30, through the rectifying diode32, thereby charging capacitors33and34. The switch29is then turned on again, and the cycle repeats. As is known in the art, the duty cycle of the turning on and off of the switch29is controlled so that the overall phase of the current waveform of the current being drawn through terminals2and3is in phase with the voltage waveform of the 110 VAC supply voltage59present on terminals2and3. The PFC control circuit portion16controls the switch29.

The PFC control circuit portion16monitors VHV58present on input node and conductor28through a resistor voltage divider circuit involving resistors35and36and capacitor37. The ACS signal104received onto the integrated circuit9via ACS terminal38is therefore a fixed fraction of the voltage of signal VHV58. The PFC control circuit portion16also monitors VBUS19present on output node and conductor20through a resistor voltage divider circuit involving resistors39and40. The voltage received onto the integrated circuit9via FBC terminal41is therefore a fixed fraction of the voltage of signal VBUS19on conductor20. The PFC control circuit portion16also monitors the voltage VSENSE60dropped across sense resistor RSENSE31via terminal GND43, terminal CSL42, and current sense amplifier circuit26. The PFC control circuit portion16controls the switch29of the external PFC circuit13by driving a control signal44out of terminal DRC45. Terminal COMPC46is a terminal for coupling an external compensation circuit47,48and49to circuitry inside the integrated circuit.

The power factor control circuitry may be realized in numerous different ways that are known in the art. In the illustrated example, current sense amplifier circuit26outputs a current sense signal CS50. The magnitude of current sense signal CS50is a scaled version of the voltage drop across current sense resistor RSENSE31. This voltage CS50is multiplied by analog multiplier circuit51with the voltage divided version of signal VHV58. Error amplifier52compares the voltage divided version of signal VBUS19received via terminal41with a 2.5 volt voltage reference signal and outputs an error signal ERR. An analog divider circuit53divides the signal output by the multiplier51by the error signal ERR output by the error amplifier52to generate a control signal54. The level of the control signal54controls the pulse width of the drive signal44output by the pulse width modulator PFC PWM27. If PFC PWM27is enabled, then switch29is pulse width modulated on and off as described above to make sure that the phase of the current drawn through terminals2and3substantially matches the phase of the voltage VAC received on terminals2and3.

The PFC PWM27, however, has an input control lead55that receives a digital enable/disable56signal EN/DISB56from the novel PFC Autodetect circuit107. If the EN/DISB signal has a high digital logic value, then the PFC PWM27is enabled and operates as set forth above to carry out power factor correction. If the EN/DISB signal has a low digital logic value, then the PFC PWM27is disabled such that switch29is off and remains off.

In the example illustrated, the PFC Autodetect circuit107stores a PFC ON bit value61, a PFC OFF bit value62, a 4-bit IMON value63, and a 5-bit TMON value64. These bits can be stored in a single register, or may be stored in multiple registers and/or flip-flops and/or other sequential logic elements. If the PFC OFF bit is set, then the PFC Autodetect circuit107is disabled regardless of the values of the PFC ON bit, the value of IMON, and the value of TMON. When the PFC Autodetect circuit107is disabled, the EN/DISB signal56supplied to PFC PWM27is a low digital logic level and the PFC PWM27is disabled.

If the PFC OFF bit value is cleared, then the PFC Autodetect circuit107may be set always to drive the EN/DISB signal56to a high digital logic value, or the PFC Autodetect circuit107may be set to operate in its autodetect mode. If the PFC ON bit is set when the PFC OFF bit is cleared, then the PFC Autodetect circuit is set always to drive the EN/DISB signal56to the high digital logic value. If, however, the PFC ON bit is cleared when the PFC OFF bit is cleared, then the PFC Autodetect circuit is set to operate in the autodetect mode.

In the autodetect mode, the PFC Autodetect circuit107may be in an autodetect state in which the EN/DISB signal56is at a high digital logic level, or the PFC Autodetect circuit107may be in an autodetect state in which the EN/DISB signal56is at a high digital logic level. If the PFC Autodetect circuit107is in the state in which the EN/DISB signal56is at the high digital logic level, then the PFC Autodetect circuit107monitors the voltage drop across the current sense resistor RSENSE31and if a high power condition is detected, then the PFC Autodetect circuit107switches the autodetect state to the state that asserts the EN/DISB signal, thereby enabling the PFC PWM27. One example of detecting such a high power condition is as follows. If, in a half period of the incoming AC supply voltage signal59on terminals2and3, the voltage drop across RSENSE31is detected to exceed a first predetermined voltage for a predetermined amount of time, then the autodetect state of the PFC Autodetect circuit107is switched so that the PFC Autodetect circuit107then asserts the EN/DISB signal56to a high digital logic level. If, in a half period of the incoming AC supply signal59on terminals2and3, the voltage drop across RSENSE31is not detected to exceed the first predetermined voltage for the predetermined amount of time, then the autodetect state of the PFC Autodetect circuit107is not switched and EN/DISB signal56continues to be output from the PFC Autodetect circuit107at a low digital logic level.

If the PFC Autodetect circuit107is in the autodetect state in which the EN/DISB signal56is at the high digital logic level, then the PFC Autodetect circuit107monitors the voltage drop across the current sense resistor RSENSE31. If a low power condition is detected then the PFC Autodetect circuit107switches the autodetect state so that the EN/DISB signal56is a digital low logic level, thereby disabling the PFC PWM27. One example of detecting such a low power condition is as follows. If the voltage drop across RSENSE is detected to be below a second predetermined voltage throughout one entire half period, of each of six consecutive half periods of the incoming VAC signal on terminals2and3, then the low power condition is detected. If the low power condition is detected, then state of the PFC Autodetect circuit107is switched so that the PFC Autodetect circuit107then asserts the EN/DISB signal56to a low logic level. If, on the other hand, the low power condition is not detected, then the PFC Autodetect circuit107does not switch states and continues to output the EN/DISB signal56at the high digital logic state.

In one example, the 4-bit value IMON sets the first predetermined voltage. The first predetermined may, for example, be a voltage proportional to the digital number IMON. The second predetermined voltage is a fixed fraction of the first predetermined voltage. The second predetermined voltage may, for example, be one sixth of the first predetermined voltage. The 5-bit value TMON sets the predetermined amount of time. The predetermined amount of time may, for example, be the product of the period of a clock signal multiplied by the digital number TMON.

In the illustrated example, the PFC Autodetect circuit107receives a digital signal57that is communicated across the optocoupler link25from the secondary side of the standby AC/DC converter and into the OTPMIC integrated circuit9via a feedback terminal FB. The actual signal communicated across the optocoupler link25is a signal IFB67that includes a low frequency analog signal (AS)68with the higher frequency digital signal (DS)57modulated onto the analog signal AS68. The digital signal DS57received in this manner is used to setup and control the PFC Autodetect circuit107by loading register and flip-flops in the PFC Autodetect circuit107that store the PFC ON, PFC OFF, IMON and TMON values. The low frequency analog signal AS68is used by the standby AC/DC controller circuit portion18for feedback voltage regulation purposes. The digital signal DS57as described above is supplied to the PFC control circuit portion16and is used to setup the PFC Autodetect circuit107.

FIG. 4is a waveform diagram that illustrates how the PFC Autodetect circuit107detects the high power condition in the autodetect mode, in one example. When the PFC Autodetect circuit107is in the state in which the EN/DISB signal56is at a digital logic low level, then the PFC function is disabled and the external PFC circuit13operates as a diode peak rectifier. Because the incoming AC supply voltage signal59on terminals2and3is a 110 volt RMS signal, the peak voltage is approximately 156 volts. The waveform labeled VBUS19inFIG. 4represents the peak rectified signal VBUS on conductor20. The full bridge rectifier11rectifies the incoming sinusoidal 110V RMS voltage59to generate the full wave and peak rectified signal VHV58on conductor28. The waveform labeled VHV inFIG. 4represents the full wave and peak rectified signal VHV58. A surge of current flows through the rectifying diode32once every half period of the incoming sinusoidal signal. The surge of current flows back to the rectifier11through RSENSE31. The waveform labeled VSENSE60inFIG. 4represents the voltage drop across the current sense resistor RENSE31. In the high power condition illustrated, during each half period of the incoming 110 volt AC signal59the peak magnitude of VSENSE60exceeds the first predetermined voltage by the amount of time TMON64. In the diagram, the first predetermined voltage is represented as VIMON, and the predetermined amount of time is represented as TMON. VIMON is a voltage proportional to the digital value IMON. TMON is equal to the digital value TMON multiplied by the period of the 8 kHz clock signal65. In the example of the diagram ofFIG. 4, the PFC Autodetect circuit107detects this high power condition in the second half period. In response, the PFC Autodetect circuit107asserts the EN/DISB signal56to a digital logic high value. Asserting EN/DISB high causes the PFC PWM27to operate and to carry out its power factor correction function.

As a result of power factor correction being enabled, the VBUS supply voltage output from the external PFC circuit13increases from the 156 volt peak rectified value to a rough 400 volt DC level. Also, the voltage dropped across the sense resistor RSENSE is proportional to the current drawn from the AC voltage source. As a result of power factor correction being enabled, the shape of VSENSE60changes from being surges of current as seen in the first two half periods to being a smooth wave shape whose phase is in phase with the phase of the incoming AC supply voltage VAC59.

FIG. 5is an expanded view of the second half period ofFIG. 4.

FIG. 6is a waveform diagram that illustrates one example of how the PFC Autodetect circuit107can detect the low power condition in the PFC Autodetect mode. The PFC Autodetect circuit107starts off in the autodetect state in which the EN/DISB signal56is at the digital logic high level. The PFC PWM27is therefore enabled and the external PFC circuit13is controlled to operate as a boost converter with power factor correction. The waveform labeled VSENSE60represents the waveform of the voltage drop across sense resistor RSENSE31. Each voltage surge is due to a surge of current flowing through the rectifying diode32. The PFC Autodetect circuit107detects that the magnitude of the signal VSENSE60does not rise above the second predetermined voltage (VIMON/6in this example) at any time during each half period of six consecutive half periods of the VAC input signal59. At the end of the sixth half period, the PFC Autodetect circuit107determines that the low power condition has been detected and in response switches state to assert the EN/DISB signal56high. Asserting EN/DISB high turns off the PFC PWM27. As a result of power factor correction being disabled, the magnitude of supply voltage VBUS19as output by the external PFC circuit13decreases in magnitude from its 400 volt DC value down to its full wave rectified value of about 156 volts DC.

FIG. 7is a circuit diagram of one example of the novel PFC Autodetect circuit107. The novel PFC Autodetect circuit can be realized in many different ways and may incorporate many different features. The circuit ofFIG. 7is but one specific example of a circuit that performs the PFC Autodetect function. It is not a large digital processor-based circuit that involves the execution of instructions, but rather is a robust, hardwired, and dedicated circuit that is programmable but that does not execute instructions. As shown inFIG. 2, a circuit70such as microcontroller MCU is located on the secondary side of the isolation line21. The circuit70is powered from the standby AC/DC converter supply voltage VISO23. The circuit70supplies serial digital data signal DS71via connector72, digital input terminal8, 1 nF capacitor73and 5 kΩ resistor74so as to modulate the digital signal onto analog signal AS68. The analog signal AS68is a current flowing through the LED75of the optocoupler. This current has a magnitude that is directly proportional to the magnitude of the voltage VISO23. The analog signal with the digital signal DS modulated on it passes over optocoupler link25as signal IFB67. A photodetector portion76of the optocoupler converts the light signal into a current again. The current signal IFB67flows from the photodetector portion76and into FB terminal66of the OTPMIC9.

As shown inFIG. 7, signal IFB67is received into an analog signal recovery circuit77of the standby AC/DC control portion18. Analog signal recovery circuit77includes a low pass filter that filters out the relatively high frequency digital signal DS, and buffers and amplifies the resulting analog signal AS, and outputs the lower frequency analog signal AS68. The lower frequency analog signal AS68is used for voltage regulation purposes in the controller for the standby AC/DC converter. The analog signal recovery circuit77also supplies the analog component of signal IFB to an edge detector circuit78of PFC Autodetect circuit107via conductor79. Signal IFB67is also supplied to the edge detector circuit78via conductor80. Edge detector circuit78uses the signals on conductors79and80to detect rising falling edges of the digital signal that was modulated onto the analog signal. The rising edges are used to set a latch and falling edges are used to reset the latch so that the output of the latch is the recovered digital bit stream of the original digital DS signal57as output by the microcontroller70. Digital signal DS57is supplied to UART (Universal Asynchronous Receiver Transmitter) logic of a digital signal recovery circuit79. The microcontroller70sends frames of digital data across the optocoupler communication link and into the UART logic. The UART logic receives the frames, and extracts the digital data payloads. The payloads are used to control the writing of digital data into registers in the digital signal recovery circuit79. For example, PFC ON bit61, PFC OFF bit62, and IMON63may be stored in a first such register, and TMON64may be stored in a second such register. By using UART communication to write appropriate values into these registers, the microcontroller70sets up the PFC Autodetect circuit107for subsequent operation.

The autodetect state of the PFC Autodetect circuit107is stored in an SR latch80. If SR latch80is set, then the EN/DISB signal56is a digital logic high level. If SR latch80is cleared, then the EN/DISB signal56is a digital logic low level.

Assume for explanation purposes here that the PFC Autodetect circuit is in the state in which EN/DISB signal56is at a digital logic level low. SR latch is therefore cleared. Further assume that neither the PFC ON bit nor the PFC OFF bit is set. In such a state, the PFC Autodetect circuit107monitors the VSENSE voltage to detect a high power condition. A signal CYCLE_SIG82that defines each half period of the incoming VAC signal59is generated by a cycle detect circuit83. There are multiple ways of realizing cycle detect circuit83. In one non-limiting example, a scaled version of the incoming sinusoidal AC signal is full wave rectified and compared to a reference voltage to generate the CYCLE_SIG signal. The signal CYCLE_SIG82in one example pulses low between each successive half period of the incoming VAC signal59, but otherwise is a digital logic level high. This signal CYCLE_SIG is used to asynchronously clear a counter CNTRA83at the beginning of each half period. The VSENSE voltage signal60between terminals42and43is amplified by the current sense amplifier circuit26to generate signal CS50that is proportional to VSENSE60. This signal CS50is supplied onto the non-inverter input lead of a comparator84. The 4-bit IMON value is converted into a voltage by DAC (Digital to Analog Converter)85. The resulting signal86is a voltage that has a magnitude equal to IMON multiplied by 45 mV. This signal86is supplied onto the inverting input lead of comparator84. If the current sense voltage signal CS50is higher than the voltage of signal86, then comparator84asserts signal87to be a digital logic high. If the current sense voltage signal CS50is lower than the voltage of signal86, then comparator84asserts signal87to be a digital logic low. The digital signal87is supplied onto a count enable CEN input of the counter CNTRA83. After the counter CNTRA83has been asynchronously cleared at the beginning of a half period, if the signal87is a digital logic high then the counter CNTRA83is enabled to count. The counter increments on each rising edge of the 8 kHz signal65. Accordingly, if the voltage drop across the sense resistor RSENSE31increases in the middle of a half period high enough that CS50exceeds the voltage of signal86for an amount of time during the peak of diode current flow, then the counter CNTRA83will be enabled to count. Digital comparator88compares the count output of counter CNTRA83with the 5-bit value TMON64. If the count becomes equal to TMON, then the A≧B signal89as output by the digital comparator88transitions from a digital low to a digital high. Because PFC ON is a digital low, the OR gate90passes the rising transition to the set input of SR latch80. The SR latch80is therefore set, and the EN/DISB signal56is made to transition from its digital logic low level to its digital logic high level. The PFC Autodetect circuit107therefore has transitioned state from outputting EN/DISB of a digital logic low level to outputting EN/DISB of a digital logic high level. If, however, during the half period the count output by CNTRA83did not reach the TMON value, then at the end of the half period the signal CYCLE_SIG82will pulse low and will asynchronously reset the counter CNTRA83without any set pulse having been sent to the SR latch80.

Next, assume that the PFC Autodetect circuit107is in the autodetect state in which the SR latch80is outputting a digital logic high level signal56. Further assume as above that neither the PFC ON bit nor the PFC OFF bit is set. In this state, the PFC Autodetect circuit107monitors VSENSE60to detect a low power condition. Resistors91and92form a resistor voltage divider that outputs onto the inverting input lead of comparator93a voltage signal that has one sixth the magnitude of voltage signal VIMON86. The current sense signal CS50is supplied onto the non-inverting input lead of comparator93. The signal94output by comparator93will therefore be at the high digital logic level if the current sense signal is higher than the voltage of signal86divided by six. If CYCLE_SIG82is low such as it is between half periods, then AND gate95cannot output a digital high signal to SR latch96. But if CYCLE_SIG82is at a digital high level as it is during the center portion of each half period, then AND gate95will output a high level if the current sense signal CS50is higher than the voltage of signal86divided by six. If the voltage of the CS signal is ever higher than the voltage of signal86divided by six (during the center portion of a half period), then the AND gate95will supply a high signal onto the set input of SR latch96, thereby causing the SR latch96to be set. As a result, a high signal is supplied onto the synchronous load enable SLED input lead of counter CNTAB97. Once set, the SR latch96will remain latched until the end of the half cycle when CYCLE_SIG going low will cause a high signal to be supplied via inverter98onto the reset input of SR latch96. Because the digital high is maintained on the SLED input lead until CYCLE_SIG goes low, the counter CNTRB97will be clocked when its SLED input lead is receiving a digital logic high signal. The counter CNTRB97will therefore parallel load in the “0000” value on its parallel input leads99on the falling edge of CYCLE_SIG82at the end of the half period. In this way, if the current sense VSENSE ever pulses high enough such that signal CS50exceeds the voltage of signal86divided by six, then at the end of the half cycle the counter CNTRB97will be parallel loaded with “0000”, thereby effectively clearing the 4-bit counter.

If, on the other hand, VSENSE does not pulse high enough such that signal CS50exceeds the voltage of signal86divided by six (during the center portion of a half period), then the SR latch96will not be set. At the end of the half period when CYCLE_SIG pulses low, the synchronous load input lead SLED is receiving a digital logic low value and the synchronous count enable SCEN input lead is receiving a digital logic high value. Accordingly, on the falling edge of signal CYCLE_SIG82at the end of the half period, the counter CNTRB97increments. CNTRB97is clocked on the falling edges of CYCL_SIG due to inverter105. If there are six consecutive half periods in which the voltage drop across sense resistor RSENSE31never got high enough to set the SR latch96, then the CNTRB=6 signal100as output by counter CNTRB97will be asserted high. The high signal will pass through OR gate101and will cause the SR latch80to reset. Resetting the SR latch80causes the EN/DISB signal56to be asserted to a digital logic low level. Accordingly, if a low power condition is detected, then the PFC PWM27is disabled.

A power on reset circuit102outputs an active high power on reset POR signal103. POR103is a high digital logic high level initially during power on of the integrated circuit. Under such circumstances, the high POR signal103overrides all other signals and resets the SR latch80, thereby forcing EN/DISB56low and disabling the PFC PWM27. When the power on reset condition has passed, then the POR signal103transitions to a low digital logic level and the POR circuit102has no effect on the PFC Autodetect circuit107. If the PFC OFF bit is set, then the SR latch80is also forced to reset and is held in that condition. Therefore setting the PFC OFF bit causes the PFC PWM27to be disabled as long as PFC OFF is set. If the PFC OFF bit is not set and POR103is not high but if the PFC ON bit is set, then the SR latch80will be set and will be held in that condition. The signal EN/DISB56is therefore forced to a digital logic high level, and the PFC PWM27is held in the enabled condition.

FIG. 8is a flowchart of a method200in accordance with one novel aspect. In this simplified method, both the PFC ON bit and the PFC off bet are cleared. The PFC converter can therefore operate in the autodetect mode. Process flow starts (201) in the PFC Autodetect state (202) in which power factor correction is off. In the circuit ofFIG. 7, power on reset POR signal103is a digital logic high and SR latch80is reset. Process flow stays in this PFC Autodetect state with the PFC PWM being turned off as long as POR signal103is asserted to a high digital logic level. When the power on reset condition has passed and the power on reset signal POR103transitions to a low digital low level, then the PFC Autodetect circuit107determines (203) whether a high power condition exists. In the circuit ofFIG. 7, the PFC Autodetect circuit107monitors VSENSE and determines whether VSENSE is greater (in any one half period of the incoming VAC signal59) than a first predetermined voltage for longer than a predetermined amount of time. The first predetermined voltage can set by setting the 4-bit value IMON, and the predetermined amount of time can be set by setting the 5-bit value TMON. If the high power condition is not detected, then the PFC Autodetect circuit107continues operating in this PFC Autodetect state and continues monitoring VSENSE and checking for a high power condition. Power factor correction remains off.

If the high power condition is detected, then the PFC Autodetect circuit107transitions to the PFC Autodetect state (204) in which power factor correction is turned on. In the example of the circuit ofFIG. 7, SR latch80is set and signal EN/DISB56is asserted to be a high digital logic level. Power factor correction is therefore on. The PFC Autodetect circuit107operates in the PFC Autodetect state in which power factor correct is enabled, and determines (205) whether a low power condition exists. In the circuit ofFIG. 7, the PFC Autodetect circuit107monitors VSENSE and determines whether VSENSE remains below a second predetermined voltage throughout each half period of six consecutive half periods of the incoming AC input supply voltage59. In the circuit ofFIG. 7, the second predetermined voltage is a fixed one sixth of the first predetermined voltage. If the low power condition is not detected, then the PFC Autodetect circuit107continues operating in this PFC Autodetect state and continues monitoring VSENSE and checking for a low power condition. If the low power condition is detected, then the PFC Autodetect circuit107transitions to the PFC Autodetect state (202) in which power factor correction is turned off. In the example of the circuit ofFIG. 7, SR latch80is reset and signal EN/DISB56is asserted to be a low digital logic level. Power factor correction is therefore off. Due to this operation, power factor correction is automatically turned off under low power conditions when power factor correction is not needed. Turning off the power factor correction circuitry in this condition reduces power consumption as compared to unnecessarily leaving the power factor correction circuit on.

FIG. 9is a flowchart of a method300in accordance with another novel aspect. An Offline Total Power Management Integrated Circuit (OTPMIC) has: 1) a PFC control portion, 2) a main AC/DC control portion, and 3) a standby AC/DC control portion (301). The standby AC/DC control portion is part of a standby power supply. The standby power supply has an optocoupler link that extends from the secondary side of the power supply to an FB terminal of the standby AC/DC control portion of the OTPMIC. Digital information is modulated (302) onto an analog signal. The resulting signal is sent from the secondary side of the standby power supply across the optocoupler link to the FB terminal. Once on the OTPMIC, the digital information is supplied (303) to the PFC control portion. The digital information is used to control a PFC Autodetect circuit in the PFC control portion. A main AC/DC power supply (that is controlled by the main AC/DC control portion of the OTPMIC) can be disabled so that it is not outputting its output supply voltage), but yet the standby power supply continues to operate so the optocoupler link used to communicate the digital information remains operating and available for controlling the PFC Autodetect circuit.

Although certain specific embodiments are described above for instructional purposes, the teachings of this patent document have general applicability and are not limited to the specific embodiments described above. The example of the high power condition set forth above is but one example. A PFC Autodetect circuit in other examples can use different input parameters and a different rule to determine that a high power condition has been detected. Likewise, the example of the low power condition set forth above is but one example. A PFC Autodetect circuit in other examples can use different input parameters and a different rule to determine that a low power condition has been detected. Accordingly, various modifications, adaptations, and combinations of various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the claims.