Incremental encoder for measuring positions of objects such as rotating shafts

A circuit for determining each level transition of first and second two logic level input signals and their leading or lagging phase relationship at each level transition and comprising first and second signal level storage means each having first input means responsive to the first and second input signals, respectively, first output means, and clock input means and responsive to a clock signal supplied to the clock input means to cause the logic level on its output means to become equal to the logic level on its first input means. First and second Exclusive OR gates each have a first input means connected respectively to said first input means of said first and second signal level storage means, and a second input means connected respectively to said first output means of said first and second signal level storage means. A third Exclusive OR gate responds to equal or non-equal logic levels on said first output terminal of said first Exclusive OR gate and said second input signal to produce first and second logic level, respectively. Additional means respond to the outputs of said first, second, and third Exclusive OR gates to determine the relationship of said first and second input signals at each level transition thereof and to supply a clock signal to the clock input means of said first and second signal level storage means after said additional means determines the phase relationship between said first and second input signals.

This invention related generally to incremental encoders of the type 
employed to track the position of a moving object such as a 
bi-directionally rotatable disc and more particularly to a circuit for 
determining the phase relationship of a pair of two-level signals of equal 
frequency produced by said moving object upon the occurrence of each level 
transition of both of said signals. 
Prior art systems have been devised which detect the leading or lagging 
phase relationship of the two signals at the time of each level transition 
of both of the two signals. These prior art devices accomplish their 
result by, in effect, dividing the two signals into four quadrants for 
each complete cycle of operation. More specifically, the logic level of 
the two signals will have four relationships, e.g. when they are both 
high, when they are both low, and when one is high and the other is low. 
Such prior art devices further contain logic which remembers at least the 
two immediately prior permutations of logic levels in addition to the one 
in which a determination of the phase relationship of the two signals at a 
level transition is to be made. These prior art devices are complex and 
require a relatively large amount of logic in order to remember the two 
prior level states as well as the one in which the decision is made, and 
then to decide from such information the proper interpretation of the 
level transition in the state being considered. Such complex logic is 
expensive and therefore prohibitive in many applications. Further, because 
of the complexity, the time required for the circuit to make a decision is 
longer than would be required for a system having fewer components, and 
therefore functions more slowly to further limit the number of feasible 
applications. 
The present invention provides an improved and simplified circuit wherein 
every positive-going and negative-going level transitions of both 
two-level signals produce incrementing or decrementing pulses in 
accordance with the phase relation of the two signals at the time of 
occurrence of each level transition. 
In accordance with a preferred form of the invention, there is provided 
first and second signal level storage means each having a data input 
terminal, a clock input terminal, and an output terminal, and constructed 
to store a signal logic level supplied to its data input terminal and 
further constructed to cause the signal logic level of its output terminal 
to become equal to the signal logic level of its data input terminal in 
response to a clock signal supplied to its clock input terminal. Further 
provided are first and second voltage comparator means each having a first 
input terminal means for receiving first and second input signals, 
respectively, a second input terminal means connected respectively to said 
output terminals of said first and second signal level storage means and 
responsive to equal and non-equal signal levels supplied to said first and 
second input terminal means to produce first and second output signal 
logic levels, respectively. A third voltage comparator means is responsive 
to equal and non-equal signal logic levels on said output terminal of said 
first signal level storage means and said second input signal to produce 
first and second output signal logic levels, respectively. Other means are 
responsive to the output signal levels on said first, second and third 
voltage comparator means to determine the leading or lagging phase 
relation of said first and second input signals at each level transition 
thereof, and further to supply a clock pulse to said clock input terminals 
of said first and second signal level storage means a predetermined time 
interval after the determination of said leading or lagging phase relation 
of said first and second input signals at each logic level transition.

Referring now to FIG. 1 there is shown a prior art means for generating a 
pair of two-level signals which have either a leading or lagging phase 
relationship. The disc 10 has a circular row of apertures 17 formed around 
the perimeter thereof, such as the individual apertures 11, 12, 13, and 
14. A pair of light sources 15 and 16 are positioned adjacent the 
apertures to project a beam of light through said apertures to 
photo-electric devices (not shown) as the disc 10 is rotated. The two 
lights source 15 and 16 are positioned in such a manner that one of the 
lights sources 15 will be centered in an aperture, such as aperture 11, at 
the time the other light source 16 is just crossing the edge of another 
aperture 12 and into said aperture 12. Thus, if the disc 10 is rotating in 
the counter-clockwise direction, as indicated by arrow 20, the signal 
.phi..sub.2 produced by light source 15 will lead the phase of the signal 
.phi..sub.1 produced by light source 16 to produce the signals .phi..sub.1 
and .phi..sub.2 shown in waveforms A and C of FIG. 5. 
Specifically, waveform A of FIG. 5, designated as signal .phi..sub.1, is 
generated by light source 16 of FIG. 1 and signal .phi..sub.2, shown in 
waveform B of FIG. 5, is generated by light source 15 of FIG. 1. It is to 
be noted that while signals .phi..sub.1 and .phi..sub.2 are shown as being 
in phase quadrature it is not necessary that they be so. It is only 
necessary that there be a leading and lagging phase relationship. 
When the rotation of disc 10 is reversed to rotate in the direction of 
arrow 21 (clockwise), the phase of the signal .phi..sub.1 produced by 
light source 16 will lead the phase of the signal .phi..sub.2 produced by 
light source 15, as shown in waveforms A and C of FIG. 6. 
Referring now to FIG. 2 the two received input signals .phi..sub.1 and 
.phi..sub.2 are supplied to first input terminals 64 and 70 of Exclusive 
OR gates 51 and 54. The Q.sub.1 and Q.sub.2 output terminals of 
conventional D type flip-flops 52 and 55 are supplied to the second input 
terminals of Exclusive OR gates 51 and 54. As will be discussed in detail 
later, Exclusive OR gates 51 and 54 produce output pulses defined herein 
as strobe pulses (shown in waveforms F of FIGS. 5 and 6) upon each 
transition of input signals .phi..sub.1 and .phi..sub.2, respectively. 
Such strobe signals are supplied through OR gate 58 to decoding means 75, 
the operation of which will be discussed in detail later herein but which 
in effect records such level transitions. Exclusive OR gate 56 responds to 
the input signals supplied to its two input terminals to supply a 
direction or phase relation indicating signal to decoding means 75 which 
responds thereto to determine the phase relationship between input signals 
.phi..sub.1 and .phi..sub.2 at the occurrence of each level transition 
thereof. A signal acknowledging each strobe pulse is supplied from 
decoding means 75 back to the clock inputs 68 and 66 of flip-flops 52 and 
55 to prepare the circuit for the occurrence of the next level transition 
as will be discussed in detail later herein. 
Consider next the operation of the circuit of FIG. 2 with respect to the 
waveforms of FIG. 5 wherein the input signal .phi..sub.1 lags the input 
signal .phi..sub.2 as shown in waveforms A and C of FIG. 5 and the disc 10 
of FIG. 1 is rotating in a counter-clockwise direction. 
In the discussion of the operation of the circuit of FIG. 2 with the 
waveforms of both FIGS. 5 and 6, the waveforms will be identified by the 
figure number plus the letter to the left of the waveform. Thus, waveform 
A in FIG. 5 will be designated as waveform 5A. Further, each of the 
waveforms has a voltage notation at the left side thereof. Thus, waveform 
5A has the voltage notation e.sub.50 at the left thereof which indicates 
that waveform 5A is the voltage signal appearing on input lead 50 of the 
logic diagram of FIG. 2. Similarly, in waveform 5B, the voltage e.sub.60 
is the voltage appearing on the Q.sub.1 output 60 of flip-flop 52 of FIG. 
2. 
Assume further the initial conditions existing at time t.sub.0 in FIG. 5, 
at which time .phi..sub.1 and Q.sub.1 are at their low levels and 
.phi..sub.2 and Q.sub.2 are at their high levels. Q.sub.1 and Q.sub.2 
represent the outputs of flip-flops 52 and 55, respectively, of FIG. 2 and 
are further identified as signal levels e.sub.60 and e.sub.61, 
respectively. 
The direction indicating signal e.sub.65 is high at time t.sub.0 and there 
is not strobe pulse e.sub.63 on lead 63 present at time t.sub.0. 
At time t.sub.1, .phi..sub.1 (waveform 5A) goes from its low to its high 
level to produce an output pulse at the output terminal 71 of Exclusive OR 
gate 51 (FIG. 2) since the voltage levels supplied to the two inputs 
thereof are now non-equal, i.e. of different signal logic levels since 
Q.sub.1 is low. The positive-going voltage change on output terminal 71 of 
Exclusive OR gate 51 is supplied through OR gate 58 to first inputs of AND 
gates 76 and 77 as a strobe or clock signal represented by pulse 86 of 
waveform 5F. Further, at time t.sub.1, the output signal of Exclusive OR 
gate 56, which is the direction indicating signal e.sub.65 of waveform 5E, 
is at its high level since the signal level e.sub.60 supplied to one of 
its input terminals is at a low level and the input signal .phi..sub.2 
supplied to its other input terminal is at a high level. Thus, AND gate 77 
is primed to permit the strobe signal 86 of waveform 5F to pass 
therethrough, through OR gate 78, delay means 79, and then back to the 
clock input terminal 66 of the conventional D-type flip-flop means 52 to 
cause the signal level on the Q.sub.1 output of flip-flop 52 to become 
equal to the signal level (.phi..sub.1) supplied to the D input thereof on 
input lead 50. 
Thus, at time t.sub.2, Q.sub.1 goes from its low to its high level, as 
shown in waveform 5B, which will cause the output of Exclusive OR gate 56 
to go from its high to its low level since the signal level on both inputs 
thereof are now at high levels. 
It will be noted from the foregoing discussion that when the level of 
.phi..sub.1 changed from its low to its high level at time t.sub.1 two 
subsequent changes in the circuit occurred. The first change was that the 
signals levels to the Exclusive OR gate 51 became unequal to produce a 
strobe signal which was supplied through OR gate 58 to the decoding means 
75. Then an acknowledgment pulse but, generated in decoding means 75, was 
supplied back to the clock input 68 of flip-flop 52 to change the signal 
on its Q.sub.1 output from its low to its high level, thereby causing the 
two input signals to Exclusive OR gate 56 to become equal and thereby 
change the output signal e.sub.65 of Exclusive OR gate 56 from its high to 
its low level at time t.sub.2. 
The direction indicating signal e.sub.65 is now at its low level, which is 
the wrong level to properly indicate the counter clockwise direction of 
motion of the disc 10 (FIG. 1) at the next transition of an input signal, 
which occurs in input signal .phi..sub.2 at time t.sub.3. Therefore, it is 
necessary that the level of the direction indicating signal e.sub.65 be 
changed back to its high level before the strobe pulse generated by the 
level transition of .phi..sub.2 at time t.sub.3 occurs. 
To effect the foregoing, the strobe pulse 87, which ultimately appears at 
the output of OR gate 58 due to the level transition of .phi..sub.2 at 
time t.sub.3 is delayed until after the direction indicating signal 
e.sub.65 is changed to its high level, as shown in waveform 5E at time 
t.sub.3. More specifically, at time t.sub.3, when .phi..sub.2 changes from 
its high to its low level, the direction indicating output signal e.sub.65 
from Exclusive OR gate 56 will change from its low to its high level since 
the signal levels supplied to the two inputs thereof are unequal. 
At the same time t.sub.3, the output of Exclusive OR gate 54 will change 
from its low to its high level since the signal levels supplied to the two 
inputs thereto are also unequal. Specifically, the signal level on lead 70 
has changed from a high to a low level whereas the output signal level of 
Q.sub.2 remains at a high level as shown at time t.sub.3 in waveform 5D. 
However, due to the delay means 57, the strobe signal 87 generated at the 
output of Exclusive OR gate 54 is delayed until time t.sub.4 as indicated 
in waveform 5F. 
Thus, it can be seen that the strobe signal 87 generated as a result of a 
level transition of .phi..sub.2 at time t.sub.3 is delayed until after the 
direction indicating signal has changed whereas in the case of a level 
transition of input signal .phi..sub.1 the strobe signal generated thereby 
precedes a change in the direction indicating signal produced by such 
level change. 
The foregoing order of events is necessary since the change in level of 
direction indicating signal e.sub.65 produced by a level change of 
.phi..sub.1 indicates a direction of rotation of the disc 10 (FIG. 1) 
opposite to that which is actually occurring. Therefore, it is necessary 
that the direction indicating signal e.sub.65 be changed back to its high 
level prior to the occurrence of the strobe pulse produced by a level 
transition of input signal .phi..sub.2. 
The strobe pulse 87 of waveform 5F is supplied from the output of OR gate 
58 (FIG. 2) through AND gate 77, primed by the positive level of the 
direction indicating signal e.sub.65, OR gate 78, delay means 79, and the 
back to the clock input terminal 66 of flip-flop 55 to cause the signal 
level of Q.sub.2 to become equal to the signal level to the D.sub.2 input 
53. Such D.sub.2 input signal level is the same level as the input signal 
.phi..sub.2 at time t.sub.5, which is a low level signal. The change in 
level of the Q.sub.2 output voltage e.sub.61 results in a change from a 
high to a low level of the output signal of Exclusive OR gate 54 which 
produces no effect on either AND gate 76 or AND gate 77 in decoding means 
75 since it is a negative-going signal. 
The next level transition occurs when .phi..sub.1 goes from its high to its 
low level at time t.sub.6 to produce a strobe output signal 88 of waveform 
5E at the output of Exclusive OR gate 51. As discussed above such strobe 
pulse 88 is produced as a result of the input signal e.sub.64 to Exclusive 
OR gate 51 changing levels while the Q.sub.1 output of flip-flop 52 does 
not change levels until the acknowledgment pulse is supplied back to clock 
input terminal 68 thereof from decoding means 75. 
Such acknowledgment signal is received back at time t.sub.7 to change the 
signal on the Q.sub.1 output of flip-flop 52 to that of data input 
D.sub.1. Thus, the output of Exclusive OR gate 51 goes from its high to 
its low level at time t.sub.7 and the direction indicating output voltage 
e.sub.65 of Exclusive OR gate 56 goes from its high to its low level since 
the levels of the signals supplied to the two inputs thereof are now 
equal. Specifically, the signal level on lead 60 goes to its low level and 
.phi..sub.2 supplied to lead 69 is also at a low level. 
Then, at time t.sub.10, the next level transition occurs when .phi..sub.2 
goes from its low to its high level as shown in waveform 5C. At the same 
time t.sub.10 the direction indicating signal e.sub.65 of waveform 6E is 
caused to go from its low to its high level since the level of the two 
signals supplied to the two inputs of Exclusive OR gate 56 are now 
unequal. A short time later at time t.sub.11, determined by delay means 
57, a strobe signal 89 is generated at the output of OR gate 58 due to the 
change of level on input terminal 70 of Exclusive OR gate 54. Next, at 
time t.sub.12 an acknowledgment signal (not specifically shown) is 
supplied from decoding means 75 back to the clock input terminal 66 of 
flip-flop 55 via lead 62 to cause the level of signal e.sub.61 on Q.sub.2 
output 61 thereof to become equal to the level signal .phi..sub.2 on the 
D.sub.2 input 53, which is then at a high level signal as shown in 
waveform 5C. 
The cycle of operation is completed at the next level transition at time 
t.sub.14 when .phi..sub.1 goes from its low to it high level. Such level 
transition is followed by a strobe signal 95 generated at the output of 
Exclusive OR gate 51 and which is supplied to decoding means 75 through OR 
gate 58. An acknowledgment pulse (not specifically shown) is then 
generated in decoding means 75 and supplied back to clock input 68 of 
flip-flop 52. Such acknowledgment signal functions to cause the voltage 
level e.sub.60 of Q.sub.1 to be equal to that of D.sub.1 input terminal 50 
at time t.sub.15, as shown in waveform 5B. 
Assume now that the disc 10 of FIG. 1 has moved to a position corresponding 
to time t.sub.16 in FIG. 5 and further that the disc 10 (FIG. 1) has 
stopped at time t.sub.16 but then begins to oscillate back and forth 
across the transition of .phi..sub.1 occurring at time t.sub.14. To 
accurately track the position of the disc 10, it is necessary that the 
motion of the disc in the reverse (clockwise) direction be recorded as 
crossing a level transition in said reverse direction. 
The foregoing occurs as follows. As the disc 10 of FIG. 1 begins to rotate 
in the reverse (clockwise) direction at time t.sub.16, the direction 
indicating signal e.sub.65 is at its low level. As the disc 10 (FIG. 1) 
continues to rotate in said reverse direction, nothing will occur to 
change the direction indicating signal e.sub.65 until after the level 
transition 91 of .phi..sub.1 (waveform 5A) occurs. At such level 
transition 91 at time t.sub.14, a strobe pulse 94 of waveform 5F is 
generated at the output of Exclusive OR gate 51 and supplied through OR 
gate 58 to decoding means 75. Since the direction indicating signal 
e.sub.65 is at its low level at this time t.sub.14, AND gate 76 will be 
enabled and AND gate 77 will be disabled so that strobe pulse 94 will 
appear on the output terminal 80 of AND gate 76 indicating that 
.phi..sub.1 leads .phi..sub.2, the criteria-defining motion of disc 10 in 
said reverse (clockwise) direction. 
The strobe pulse 94 will be supplied from AND gate 76 through OR gate 78, 
delay means 79, and then back to the clock input terminal 68 of flip-flop 
52 to cause the voltage level of Q.sub.1 to become equal to the low level 
of input D.sub.1 at time t.sub.13, as is shown in waveform 5B. Since 
.phi..sub.2 is a high level signal at time t.sub.13 the output of 
Exclusive OR gate 56 in FIG. 2 will also be a high level signal, thereby 
preparing the system to record a motion in the counterclockwise direction 
if the disc should then oscillate back again across the transition 91 of 
.phi..sub.1 in a counterclockwise direction, i.e. going to the right in 
the waveforms of FIG. 5. 
Should, however, the disc continue moving clockwise it will cross the 
transition 92 of .phi..sub.2 at time t.sub.10, as shown in waveform 5C. As 
discussed above, however, the strobe signal 93 generated as a result of a 
level transition of .phi..sub.2 at time t.sub.10 would be delayed until 
after the direction indicating signal e.sub.65 (waveform 5E) has changed 
levels. Thus, the direction indicating signal of waveform 5E would change 
to its low level at time t.sub.10 coincident with the level change of 
.phi..sub.2, said direction indicating signal appearing at the output of 
Exclusive OR gate 56 as discussed hereinbefore. 
However, the strobe pulse 93 generated at the output of Exclusive OR gate 
54 due to the level change of .phi..sub.2 at time t.sub.10 is delayed by 
delay means 57. Thus, when the strobe pulse 93 is supplied to decoding 
means 75 at time t9, the direction indicating signal e.sub.65 is at its 
low level so that strobe pulse 93 is interpreted in decoding means 75 as 
representing an increment of motion in the clockwise direction of the 
disc, i.e. when .phi..sub.1 leads .phi..sub.2 in phase. 
A complete set of waveforms illustrating the signals at various points in 
the circuit of FIG. 2 when the disc is rotating in a clockwise direction, 
e.i. when .phi..sub.1 leads .phi..sub.2 is show in the waveforms of FIG. 
6. 
In the operation of the circuit as represented by the waveforms of FIG. 6 
assume that the initial conditions are as shown at time t.sub.0 when 
.phi..sub.1, .phi..sub.2, Q.sub.1, Q.sub.2, and also the direction 
indicating signal e.sub.65 (waveform 6E) are all at their low levels. A 
low level of e.sub.65 indicates clockwise rotation. 
Thus, at time t.sub.1 when Q.sub.1 changes from its low to its high level, 
a strobe pulse 96 is generated at the output of Exclusive OR gate 51 which 
is supplied through OR gate 58 and then through primed AND gate 76 of 
decoding means 75. AND gate 76 is primed since the output of Exclusive OR 
gate 56 is at a low level which is inverted at the input 90 of AND gate 
76. 
An acknowledgment pulse is then supplied through OR gate 78, delay means 
79, and back to the clock input terminal 68 of flip-flop 52 to cause the 
voltage level of Q.sub.1 to become equal to that of D.sub.1 which is now a 
high level signal as indicated at time t.sub.1 of waveform 6A. 
The change of Q.sub.1 to a high level at time t.sub.2 results in the signal 
level to both inputs of Exclusive OR gate 51 becoming equal so that the 
output of Exclusive OR gate 51 is at a low level, thus terminating the 
strobe pulse 96 of waveform 6F. 
At time t.sub.3, .phi..sub.2 changes from its low to its high level to 
change the level of the direction indicating signal e.sub.65 from its high 
to its low level since the signal levels supplied to the two inputs of 
Exclusive OR gate 56 become equal at time t.sub.3. However, the strobe 
pulse 97 generated at the output of Exclusive OR gate 54 is delayed by 
delay means 57 until time t.sub.4 so that such strobe pulse 97 occurs 
after the direction indicating signal e.sub.65 has changed to its low 
level, thereby indicating a clockwise rotation of the disc 10 of FIG. 1. 
At time t.sub.5, the acknowledgment pulse from decoding means 75 is 
supplied back to the clock input terminal 66 of flip-flop 55, thereby 
causing the voltage level of Q.sub.2 to become equal to that of the 
D.sub.2 input terminal 53. Thus, the output of Exclusive OR gate 54 goes 
to its low level to terminate the strobe pulse 97 at time t.sub.5. 
The next voltage level transition occurs at time t.sub.6 when .phi..sub.1 
changes from its high to its low level, thereby producing and supplying a 
strobe pulse 98 from the output of Exclusive OR gate 51 through OR gate 58 
to decoding means 75. Since the direction indicating signal e.sub.65 is 
low at time t.sub.6, such strobe pulse 98 indicates rotation in the 
clockwise direction. The acknowledgment pulse (not shown) is supplied at 
time t.sub.7 from decoding means 75 back to the clock input terminal 68 of 
flip-flop 52 to cause the voltage level of Q.sub.1 to become equal to that 
of input terminal D.sub.1 and thereby cause the voltage level at the 
output of Exclusive OR gate 51 to go to its low level, thus terminating 
the strobe pulse 98 at time t.sub.7. 
At time t.sub.8, .phi..sub.2 changes from its high to its low level to 
cause an immediate change of the direction indicating signal e.sub.65 from 
its high to its low level in the manner discussed above. Subsequently, at 
time t.sub.9, strobe pulse 99 is supplied from the output of Exclusive OR 
gate 54, through delay means 57 and OR gate 58 and then through primed AND 
gate 76 of decoding means 75. Next, at time t.sub.10, an acknowledgment 
pulse (not shown) is supplied back from the output of delay means 79 to 
the clock input pulse terminal 66 of flip-flop 55 to cause the voltage 
level of Q.sub.2 to become equal to that of D.sub.2, thereby causing the 
output of Exclusive OR gate 54 to go to its low level and terminate the 
strobe pulse 99. 
The cycle of operation is completed at time t.sub.11 when .phi..sub.1 again 
changes from its low to its high level. Since the direction indicating 
signal e.sub.65 is at its low level at time t.sub.11, the strobe pulse 100 
will indicate rotation of disc 10 of FIG. 1 in the clockwise direction. 
Subsequently, at time t.sub.12, an acknowledgment signal is supplied back 
from decoding means 75 to the clock input terminal 68 of flip-flop 52 to 
cause the voltage level of Q.sub.1 to become equal to that of D.sub.1. 
Thus, the output of Exclusive OR gate 56 goes to its high value at time 
t.sub.12, as indicated in waveform 6E. Also, the strobe pulse 100 is 
terminated at time t.sub.12 as shown in waveform 6F. 
The flip-flop circuits 52 and 55 of FIG. 2 need not be flip-flop circuits. 
The requirements of the logic blocks 52 and 55 are that they are able to 
receive and store a signal level supplied to a first (data) input terminal 
and then to transfer said signal level to an output terminal (Q) upon the 
reception of a clock pulse at a clock input terminal. Logic means other 
than conventional D-type flip-flops are available to perform this function 
or, alternatively, can be designed by one skilled in the art. 
The decoding means 75 and the storage and utilization means 101 can be 
performed by a means other than that shown in FIG. 2. For example, the 
microprocessor 85 shown in FIG. 3 can be employed to perform the decoding, 
storage and utilization functions in response to the direction indicating 
signal e.sub.65 and the strobe signal e.sub.63 on leads 63, and also to 
generate acknowledgment signals on lead 62. 
In another alternate form of decoding means shown in FIG. 4, a 
bi-directional counter 105 can be employed to decode the direction 
indicating signal e.sub.65 and the strobe signal e.sub.63 and to count 
upwardly or downwardly in response to each strobe signal in accordance 
with the polarity of the direction indicating signal e.sub.65. The 
acknowledgment signal (not specifically shown) can be generated from the 
least significant bit position of the bi-directional counter output 
terminals 110 by various means such as that shown within the dotted block 
106. Within dotted block 106, there is a pulse generating circuit 
comprised of resistor 108, capacitor 109, and Exclusive OR gate 107. Each 
time the output of the least significant bit position 111 changes 
polarity, resistor 109 will require some time to charge to the new 
polarity, whereas the change of signal level will be supplied directly to 
the other terminal 112 of the Exclusive OR gate 107. Thus, during the 
interval of time required for capacitor 109 to charge, the voltage level 
supplied to the two input terminals of Exclusive OR gate 107 will be 
different so that a positive pulse will appear on the output thereof. This 
positive pulse is the acknowledgment signal and occurs with each change of 
the contents of the least significant bit position 111 of bi-directional 
counter 105.