Semiconductor Device and Method of Forming Stress Relief Vias in Multi-Layer RDL

A semiconductor device has a substrate and a first RDL formed over the substrate. A second RDL is formed over the first RDL with a first conductive via electrically connecting the first RDL and second RDL and a first opening formed in the second RDL around the first conductive via for stress relief. The first opening formed in the second RDL can have a semi-circle shape or a plurality of semi-circles or segments. A third RDL is formed over the second RDL with a second conductive via electrically connecting the second RDL and third RDL and a second opening formed in the third RDL around the second conductive via for stress relief. The first opening is offset from the second opening. A plurality of first openings can be formed around the first conductive via for stress relief, each offset from one another.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming vias to reduce stress, delamination, and warpage in multi-layer RDL.

BACKGROUND OF THE INVENTION

Semiconductor devices are commonly found in modern electrical products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed calculations, transmitting and receiving electromagnetic signals, controlling electrical devices, photo-electric, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networks, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automotive, industrial controllers, and office equipment.

Semiconductor devices often contain a semiconductor die or substrate with electrical interconnect structures, e.g., redistribution layers (RDL) formed over one or more surfaces of the semiconductor die or substrate to perform necessary electrical functions. The semiconductor devices are formed wafer or panels during the manufacturing process. The wafer and panels are subject to cracking due to the propagation of thermal stress, delamination, and warping displacement contributed by one or more expansive metal layers during formation of the RDL. Larger fan-out devices have a higher risk of cracking and consequently, lower yield leading to higher manufacturing costs.

DETAILED DESCRIPTION OF THE DRAWINGS

The present invention is described in one or more embodiments in the following description with reference to the figures, in which like numerals represent the same or similar elements. While the invention is described in terms of the best mode for achieving the invention's objectives, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents as supported by the following disclosure and drawings. The features shown in the figures are not necessarily drawn to scale. Elements having a similar function are assigned the same reference number in the figures. The term “semiconductor die” as used herein refers to both the singular and plural form of the words, and accordingly, can refer to both a single semiconductor device and multiple semiconductor devices.

Back-end manufacturing refers to cutting or singulating the finished wafer into the individual semiconductor die and packaging the semiconductor die for structural support, electrical interconnect, and environmental isolation. To singulate the semiconductor die, the wafer is scored and broken along non-functional regions of the wafer called saw streets or scribes. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor die are disposed on a package substrate that includes pins or contact pads for interconnection with other system components. Contact pads formed over the semiconductor die are then connected to contact pads within the package. The electrical connections can be made with conductive layers, bumps, stud bumps, conductive paste, or wirebonds. An encapsulant or other molding material is deposited over the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system and the functionality of the semiconductor device is made available to the other system components.

FIG.1ashows a semiconductor wafer100with a base substrate material102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor die or electrical components104is formed on wafer100separated by a non-active, inter-die wafer area or saw street106. Saw street106provides cutting areas to singulate semiconductor wafer100into individual semiconductor die104. In one embodiment, semiconductor wafer100has a width or diameter of 100-450 millimeters (mm).

FIG.1bshows a cross-sectional view of a portion of semiconductor wafer100. Each semiconductor die104has a back or non-active surface108and an active surface110containing analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within active surface110to implement analog circuits or digital circuits, such as digital signal processor (DSP), application specific integrated circuits (ASIC), memory, or other signal processing circuit. Semiconductor die104may also contain IPDs, such as inductors, capacitors, and resistors, for RF signal processing.

An electrically conductive layer112is formed over active surface110using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer112can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable electrically conductive material. Conductive layer112operates as contact pads electrically connected to the circuits on active surface110.

InFIG.1c, semiconductor wafer100is singulated through saw street106using a saw blade or laser cutting tool118into individual semiconductor die104. The individual semiconductor die104can be inspected and electrically tested for identification of known good die or known good unit (KGD/KGU) post singulation.

FIG.2ashows a temporary substrate or carrier120sacrificial base material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost, rigid material for structural support. Substrate120has major surfaces122and124. In one embodiment, carrier120is a support structure with a temporary bonding layer126.

Electrical components130a-130bare positioned over substrate120using a pick and place operation. Electrical components130a-130bare brought into contact with bonding layer126.FIG.2billustrates electrical components130a-130bbonded to substrate120, as a reconstituted wafer level package (WLP).

InFIG.2c, encapsulant or molding compound134is deposited over and around electrical components130a-130band substrate120using a paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable applicator. Encapsulant134can be liquid or granular polymer composite material, such as epoxy resin with filler, epoxy acrylate with filler, or polymer with proper filler. Encapsulant134is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants.

InFIG.2d, carrier120and bonding layer126are removed by chemical etching, chemical mechanical polishing (CMP), mechanical peel-off, mechanical grinding, thermal bake, ultra-violet (UV) light, or wet stripping to expose surface110and conductive layer112. Semiconductor assembly136is ready for a multi-layer RDL buildup structure on surface135of encapsulant134and conductive layer112of semiconductor die104to provide electrical interconnect for the semiconductor die, as well as external electrical components. Semiconductor assembly136operates as a substrate to form the multi-layer RDL buildup structure.

An insulating or passivation layer142is formed over insulating layer140using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. Insulating layer142contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other material having similar insulating and structural properties. Portions of insulating layers140and142are removed using an etching process or laser direct ablation (LDA) using laser143to form openings or vias144extending to conductive layer112for further electrical interconnect, such as multi-layer RDL buildup structures.

InFIG.3b, conductive layer146is formed over surface147of insulating layer142and into vias144using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer146can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer146is an RDL as it redistributes the electrical signal across and over semiconductor die104and encapsulant134. Portions of conductive layer146can be electrically common or electrically isolated depending on the design and function of semiconductor die104and other electrical components attached thereto.

An insulating or passivation layer148is formed over insulating layer142and conductive layer146using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. Insulating layer148contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other material having similar insulating and structural properties. Portions of insulating layer148are removed using an etching process or LDA using laser149to form openings or vias150extending to conductive layer146for further electrical interconnect, such as multi-layer RDL buildup structures. Insulating layers142and148provide isolation around conductive layer146.FIG.3cis a top view of vias150extending through insulating layer148to conductive layer146.

InFIG.3d, conductive layer152is formed over surface153of insulating layer148and into vias150using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer152can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer152is an RDL as it redistributes the electrical signal across and over semiconductor die104, encapsulant134, and conductive layer146. Portions of conductive layer152can be electrically common or electrically isolated depending on the design and function of semiconductor die104and other electrical components attached thereto. Portions of conductive layer152are removed using an etching process or LDA using laser155to form stress relief openings or vias or slots154extending at least partially around that portion of conductive layer152within via150and further extending to insulating layer148. Vias154reduce or eliminate cracking of conductive layer152due to stress, delamination, and warpage.

FIG.4ais a top view of a first embodiment of vias154formed at least partially around that portion of conductive layer152within via150. In the first embodiment, vias154are partial arcs or segments on opposite sides of vias150.FIG.4bis a top view of a second embodiment of vias154formed at least partially around that portion of conductive layer152within via150. In the second embodiment, via154is a partial circle around via150.FIG.4cis a top view of a third embodiment of vias154formed at least partially around that portion of conductive layer152within via150. In the third embodiment, vias154are partial arcs or segments on four sides of via150.FIG.4dis a top view of a fourth embodiment of vias154formed at least partially around that portion of conductive layer152within via150. In the fourth embodiment, vias154are partial segments around vias150.

Returning toFIG.3e, insulating or passivation layer160is formed over surface153of insulating layer148and conductive layer152using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. Insulating layer160contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other material having similar insulating and structural properties. Portions of insulating layer148are removed using an etching process or LDA, similar toFIG.3b, to form openings or vias162extending to conductive layer152for further electrical interconnect, such as multi-layer RDL buildup structures. Insulating layers148and160provide isolation around conductive layer152.

InFIG.3f, conductive layer166is formed over surface167of insulating layer160and into vias162using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer166can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer166is an RDL as it redistributes the electrical signal across and over semiconductor die104, encapsulant134, and conductive layer152. Portions of conductive layer166can be electrically common or electrically isolated depending on the design and function of semiconductor die104and other electrical components attached thereto. Portions of conductive layer162are removed using an etching process or LDA, similar toFIG.3d, to form stress relief openings or vias or slots168extending at least partially around that portion of conductive layer166within via162and further extending to insulating layer160. Vias168reduce or eliminate cracking of conductive layer166due to stress, delamination, and warpage. A top view of vias168is similar toFIGS.4a-4d.

An insulating or passivation layer170is formed over surface167of insulating layer160and conductive layer166using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. Insulating layer170contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other material having similar insulating and structural properties. Portions of insulating layer170are removed using an etching process or LDA, similar toFIG.3b, to form openings or vias171extending to conductive layer166for further electrical interconnect, such as multi-layer RDL buildup structures. Insulating layers160and170provide isolation around conductive layer166.

A conductive layer172is formed over surface173of insulating layer170and into vias171using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer172can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer172is an RDL as it redistributes the electrical signal across and over semiconductor die104, encapsulant134, and conductive layer166. Portions of conductive layer172can be electrically common or electrically isolated depending on the design and function of semiconductor die104and other electrical components attached thereto. Portions of conductive layer172are removed using an etching process or LDA, similar toFIG.3d, to form stress relief openings or vias or slots174extending at least partially around that portion of conductive layer172within via171and further extending to insulating layer170. Vias174reduce or eliminate cracking of conductive layer172due to stress, delamination, and warpage. A top view of vias174is similar toFIGS.4a-4d.

WLP178has multiple conductive layers152,166, and172constituting a multi-layer RDL structure. The stress relief vias154,168, and174reduce or eliminate cracking in the multi-layer RDL caused by stress, delamination, and warpage. The stress relief vias154,168, and174are formed around the conductive vias between each RDL layer. The inter-RDL connecting vias, such as vias144,150,162, and171, are likely points of cracking due to stress, delamination, and warpage. Vias154,168, and174result in less metal coverage and more points of stress relief for WLP178. The multi-circular design inFIGS.4a-4dprovide more cutouts compared to single circular design, hence reduced metal density further to improve the stress, delamination and warpage issues.

In another embodiment, continuing fromFIG.3e, conductive layer180is formed over surface167of insulating layer160and into vias162using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process, as shown inFIG.5. Conductive layer180can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer180is an RDL as it redistributes the electrical signal across and over semiconductor die104, encapsulant134, and conductive layer152. Portions of conductive layer180can be electrically common or electrically isolated depending on the design and function of semiconductor die104and other electrical components attached thereto. Portions of conductive layer180are removed using an etching process or LDA, similar toFIG.3d, to form stress relief openings or vias or slots182extending at least partially around that portion of conductive layer180within via162and further extending to insulating layer160. Notably, vias182in conductive layer180are offset or spaced apart from vias154in that vias154are formed closer to vias150and vias182are formed farther away from the center of vias150, as compared to vias154. Vias182reduce or eliminate cracking of conductive layer180due to stress, delamination, and warpage.

FIG.6ais a top view of a first embodiment of vias182formed at least partially around and offset or spaced away from vias154. In the first embodiment, vias182are partial arcs or segments on opposite sides of and offset or spaced away from vias154.FIG.6bis a top view of a second embodiment of vias182formed at least partially around and offset or spaced away from vias154. In the second embodiment, via182is a partial circle around and offset or spaced away from via154.FIG.6cis a top view of a third embodiment of vias182formed at least partially around and offset or spaced away from via154. In the third embodiment, vias182are partial arcs or segments on four sides of and offset or spaced away from vias154.FIG.6dis a top view of a fourth embodiment of vias182formed in between vias154. In the fourth embodiment, vias154are partial segments in between vias154.FIG.6eis a top view of a fifth embodiment of vias182formed in between vias154. In the fifth embodiment, vias154are partial segments in between vias154.

Returning toFIG.5, insulating or passivation layer184is formed over surface167of insulating layer160and conductive layer180using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation. Insulating layer184contains one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, polyimide, BCB, PBO, and other material having similar insulating and structural properties. Portions of insulating layer184are removed using an etching process or LDA, similar toFIG.3b, to form openings or vias186extending to conductive layer180for further electrical interconnect, such as multi-layer RDL buildup structures. Insulating layers160and184provide isolation around conductive layer180.

A conductive layer190is formed over surface185of insulating layer184and into vias186using PVD, CVD, electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer190can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable electrically conductive material. Conductive layer190is an RDL as it redistributes the electrical signal across and over semiconductor die104, encapsulant134, and conductive layer180. Portions of conductive layer190can be electrically common or electrically isolated depending on the design and function of semiconductor die104and other electrical components attached thereto. Portions of conductive layer190are removed using an etching process or LDA, similar toFIG.3d, to form stress relief openings or vias or slots194extending at least partially around that portion of conductive layer190within via186and further extending to insulating layer184. Vias194reduce or eliminate cracking of conductive layer190due to stress, delamination, and warpage. A top view of vias194is similar toFIGS.4a-4d.

WLP200has multiple conductive layers152,180, and190constituting a multi-layer RDL structure. The stress relief vias154,182, and194reduce or eliminate cracking in the multi-layer RDL caused by stress, delamination, and warpage. The stress relief vias154,182, and194are formed around the conductive vias between each RDL layer. The inter-RDL connecting vias, such as144,150,162, and186, are likely points of cracking due to stress, delamination, and warpage. Vias154,182, and194result in less metal coverage and more points of stress relief for WLP200. The multi-circular design inFIGS.4a-4dprovide more cutouts compared to single circular design, hence reduced metal density further to improve the stress, delamination and warpage issues. Stress relief vias154and194are vertically aligned in conductive layers152and190, while stress relief vias182in conductive layer180are offset or spaced apart from vias154and194. Likewise, the multi-circular design has more Cu cutouts compared to single circular design, hence reduced Cu density further to improve the stress, delamination and warpage issues.

In another embodiment,FIG.7illustrates multiple stress relief vias for each conductive via.FIG.7is formed similar toFIGS.3a-3fwith stress relief vias154aand154b,168aand168b, and174aand174b. For example, vias154bin conductive layer152are offset or spaced apart from vias154ain that vias154aare formed closer to vias150and vias154bare formed farther away from the center of vias150, as compared to vias154a. In a similar manner, vias168bin conductive layer166are offset or spaced apart from vias168ain that vias168aare formed closer to vias162and vias168bare formed farther away from the center of vias162, as compared to vias168a. Vias174bin conductive layer172are offset or spaced apart from vias174ain that vias174aare formed closer to vias171and vias174bare formed farther away from the center of vias171, as compared to vias174a.

FIG.8ais a top view of a first embodiment of vias154aand154bformed at least partially around that portion of conductive layer152within via150. In the first embodiment, vias154aand154bare partial arcs or segments on opposite sides of via150. Via154bis offset or spaced apart from via154a.FIG.8bis a top view of a second embodiment of vias154aand154bformed at least partially around that portion of conductive layer152within via150. In the second embodiment, via154aand154bare a partial circle around via150. Via154bis offset or spaced apart from via154a.FIG.8cis a top view of a third embodiment of vias154aand154bformed at least partially around that portion of conductive layer152within via150. In the third embodiment, vias154aand154bare partial arcs or segments on four sides of via150. Via154bis offset or spaced apart from via154a.FIG.8dis a top view of a fourth embodiment of vias154aand154bformed at least partially around that portion of conductive layer152within via150. In the fourth embodiment, vias154aand154bare partial segments around via150. Via154bis offset or spaced apart from via154a. The top views ofFIGS.8a-8dare applicable to stress relief vias168aand168band174aand174b.

In another embodiment,FIG.9illustrates multiple stress relief vias for each conductive via. The multiple stress relief vias are offset or spaced apart from one another.FIG.9is formed similar toFIG.5with additional stress relief vias154aand154b,182aand182b, and194aand194b. For example, vias154bin conductive layer152are offset or spaced apart from vias154ain that vias154aare formed closer to vias150and vias154bare formed farther away from the center of vias150, as compared to vias154a. Vias182bin conductive layer180are offset or spaced apart from vias182in that vias182aare formed closer to vias162and vias182bare formed farther away from the center of vias162, as compared to vias18sa. In addition, vias182aand182bare offset or spaced apart from vias154aand154b. Vias194bin conductive layer190are offset or spaced apart from vias194ain that vias194aare formed closer to vias186and vias194bare formed farther away from the center of vias186, as compared to vias194a. In addition, vias194aand184bare offset or spaced apart from vias182aand182b.

FIG.10ais a top view of a first embodiment of vias154aand154band vias182aand182bformed at least partially around that portion of conductive layer152within via150. In the first embodiment, vias154aand154band vias182aand182bare partial arcs or segments on opposite sides of via150. Vias154aand154band vias182aand182bare offset or spaced apart from one another.FIG.10bis a top view of a second embodiment of vias154aand154band vias182aand182bformed at least partially around that portion of conductive layer152within via150. In the second embodiment, via154aand154band vias182aand182bare a partial circle around via150. Vias154aand154band vias182aand182bare offset or spaced apart from one another.FIG.10cis a top view of a third embodiment of vias154aand154band vias182aand182bformed at least partially around that portion of conductive layer152within via150. In the third embodiment, vias154aand154band vias182aand182bare partial arcs or segments on four sides of via150. Vias154aand154band vias182aand182bare offset or spaced apart from one another.FIG.10dis a top view of a fourth embodiment of vias154aand154band vias182aand182bformed at least partially around that portion of conductive layer152within via150. In the fourth embodiment, vias154aand154band vias182aand182bare partial segments around via150. Vias154aand154band vias182aand182bare offset or spaced apart from one another.

WLP210has multiple conductive layers152,180, and192constituting a multi-layer RDL structure. The stress relief vias154,182, and194reduce or eliminate cracking in the multi-layer RDL caused by stress, delamination, and warpage. The stress relief vias154a-154b,182a-182b, and194a-194bare formed around the conductive vias between each RDL layer, e.g., vias150,162, and186. The stress relief vias154a-154b,182a-182b, and194a-194bcan single circular or multi-circular around each inter-RDL via, and by the locations inline or offset in multi-layer RDLs. The offset slots could provide the advantage over the in-line slots for the topology effect to allow more evenness of RDL and PSV layer formations. The inter-layer connecting vias, such as150,162, and186, are likely points of cracking due to stress, delamination, and warpage. Vias154a-154b,182a-182b, and194a-194bresult in less metal coverage and more points of stress relief for WLP210.

FIG.11illustrates electrical device400having a chip carrier substrate or PCB402with a plurality of semiconductor packages disposed on a surface of PCB402, including WLP178,200, and210. Electrical device400can have one type of semiconductor package, or multiple types of semiconductor packages, depending on the application. Electrical device400can be a stand-alone system that uses the semiconductor packages to perform one or more electrical functions. Alternatively, electrical device400can be a subcomponent of a larger system. For example, electrical device400can be part of a tablet, cellular phone, digital camera, communication system, or other electrical device. Alternatively, electrical device400can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can include microprocessors, memories, ASIC, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the products to be accepted by the market. The distance between semiconductor devices may be decreased to achieve higher density.

InFIG.11, PCB402provides a general substrate for structural support and electrical interconnect of the semiconductor packages disposed on the PCB. Conductive signal traces404are formed over a surface or within layers of PCB402using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition process. Signal traces404provide for electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces404also provide power and ground connections to each of the semiconductor packages.

In some embodiments, a semiconductor device has two packaging levels. First level packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. Second level packaging involves mechanically and electrically attaching the intermediate substrate to the PCB. In other embodiments, a semiconductor device may have the first level packaging where the die is mechanically and electrically disposed directly on the PCB. For the purpose of illustration, several types of first level packaging, including bond wire package406and flipchip408, are shown on PCB402. Additionally, several types of second level packaging, including ball grid array (BGA)410, bump chip carrier (BCC)412, land grid array (LGA)416, multi-chip module (MCM) or SIP module418, quad flat non-leaded package (QFN)420, quad flat package422, embedded wafer level ball grid array (eWLB)424, and wafer level chip scale package (WLCSP)426are shown disposed on PCB402. In one embodiment, eWLB424is a fan-out wafer level package (Fo-WLP) and WLCSP426is a fan-in wafer level package (Fi-WLP). Depending upon the system requirements, any combination of semiconductor packages, configured with any combination of first and second level packaging styles, as well as other electrical components, can be connected to PCB402. In some embodiments, electrical device400includes a single attached semiconductor package, while other embodiments call for multiple interconnected packages. By combining one or more semiconductor packages over a single substrate, manufacturers can incorporate pre-made components into electrical devices and systems. Because the semiconductor packages include sophisticated functionality, electrical devices can be manufactured using less expensive components and a streamlined manufacturing process. The resulting devices are less likely to fail and less expensive to manufacture resulting in a lower cost for consumers.