Process for fabricating three dimensional non-volatile memory system

A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells. In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface. A process for manufacturing the memory is also disclosed.

BACKGROUND

Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, and non-mobile computing devices. Semiconductor memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery).

One example of non-volatile memory uses reversible resistance-switching memory elements that may be set to either low or high resistance states. Upon application of sufficient voltage, current, or other stimulus, the reversible resistance-switching memory element switches to a stable low-resistance state, which is sometimes referred to as SETTING the device. This resistance-switching is reversible such that subsequent application of an appropriate voltage, current, or other stimulus can serve to return the reversible resistance-switching material to a stable high-resistance state, which is sometimes referred to as RESETTING the device. This conversion can be repeated many times.

Three dimensional (“3D”) memory arrays having reversible resistance-switching memory elements have been proposed. In one possible architecture, word lines extend horizontally and bit lines extend vertically. There a multiple levels of the word lines, hence multiple levels of memory elements. Each memory element is located between one of the vertical bit lines and one of the horizontal word lines. During operation, some of the memory cells are selected for the SET or RESET, while others are unselected.

As some memory systems are used in portable electronic devices that utilize batteries, conserving power is a goal.

DETAILED DESCRIPTION

A non-volatile storage apparatus is proposed that includes a plurality of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells of the plurality is connected to a different word line, a bit line connected to a first end of the serially connected memory cells and a switch connected to a second end of the serially connected memory cells.

In one embodiment, the memory cells include a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material, a channel, and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface.

With the above described structure, memory cells that are not intended to be subjected to a memory operation (e.g., programming or reading) can be completely unselected so that they do not leak (causing loss of power) and do not otherwise materially alter the memory operation (e.g., programming or reading).

FIG. 1is a functional block diagram of an example memory system100that can implement the proposed technology. The components depicted inFIG. 1are electrical circuits. Memory system100includes one or more memory die108. Each memory die108includes a three dimensional memory structure126of memory cells (such as, for example, a 3D array of memory cells), control circuitry110, and read/write circuits128. In other embodiments, the three dimensional memory array can be fabricated on top of CMOS circuits or a two dimensional array of memory cells can be used. Memory structure126is addressable by word lines via a row decoder124and by bit lines via a column decoder132. The read/write circuits128include multiple sense blocks150including SB1, SB2, . . . , SBp (sensing circuitry) and allow a page of memory cells to be read or programmed in parallel. Each of the sense blocks150include a sense amplifier connected to one or more respective bit lines. In some systems, a controller122is included in the same memory system100(e.g., a removable storage card) as the one or more memory die108. However, in other systems, the controller can be separated from the memory die108. In some embodiments the controller will be on a different die than the memory die. In some embodiments, one controller122will communicate with multiple memory die108. In other embodiments, each memory die108has its own controller. Commands and data are transferred between a host and Controller122via a data bus, and between controller122and the one or more memory die108via signal lines118(e.g., a Toggle Mode interface). In one embodiment, memory die108includes a set of input and/or output (I/O) pins that connect to lines118.

Memory structure126may comprise one or more arrays of memory cells including a 3D memory array, as discussed below. The memory structure may comprise a monolithic three dimensional memory structure in which multiple memory levels are formed above (and not in) a single substrate, such as a wafer, with no intervening substrates.

Control circuitry110cooperates with the read/write circuits128to perform memory operations on memory structure126, and includes a state machine112, an on-chip address decoder114, and a power control module116. The state machine112provides chip-level control of memory operations. Code and parameter storage113may be provided for storing operational parameters and software. In one embodiment, state machine112is programmable by the software stored in code and parameter storage113. In other embodiments, state machine112does not use software and is completely implemented in hardware (e.g., electrical circuits). On set of examples of memory operations includes programming and reading. Programming can include SETTING and RESETTING, as discussed above. Other types of programming can also be implemented.

The on-chip address decoder114provides an address interface between addresses used by the host or memory controller122to the hardware address used by the decoders124and132. Power control module116controls the power and voltages supplied to the word lines and bit lines during memory operations. It can include drivers for word line layers in a 3D configuration, select transistors (switches) and source lines. Power control module116may include charge pumps for creating voltages. The sense blocks include bit line drivers (e.g., as part of the sense amplifiers).

Any one or any combination of control circuitry110, state machine112, decoders114/124/132, code and parameter storage113, power control module116, sense blocks150, read/write circuits128, and Controller122can be considered one or more control circuits that performs the functions described herein.

In one set of embodiments, the memory cells comprising memory structure126are Barrier Modulated Memory Cells, in which the resistance of the memory cell is modulated by separation or recombination of oxygen vacancies and interstitial oxygen ions at a reversible resistance-switching interface between two materials. When the interstitial oxygen ions combine with the oxygen vacancies, a zone with a low density of charge carriers is formed at the interface due to reduction in oxygen vacancies, thereby increasing the resistance of the memory cell. This operation is herein referred to as a “RESETTING” operation. When the interstitial oxygen ion and oxygen vacancy pairs are created due to the separation of the interstitial oxygen ion from the vacancy lattice site, a zone with a high density of charge carriers is formed due to creation of oxygen vacancies, thereby decreasing the resistance of the memory element. This operation is herein referred to as a “SETTING” operation. Some example structures include an active layer and a barrier layer in contact with each other at the interface. The active layer includes a material that provides different resistance depending on the state of oxygen vacancies therein. Specifically, when oxygen vacancies are depleted at the interface with the barrier layer, the active layer at the interface of the active layer and the barrier layer is in a high resistance state, or a “reset” state. When oxygen vacancies are repopulated at the interface with the barrier layer, the active layer (at the interface) is in a low resistance state at the interface, or a “set” state. For example, the active layer can include titanium oxide (e.g., sub-stoichiometric titanium oxide having less than two oxygen atoms for each one titanium atom) or tantalum oxide (TaOx). Other materials can also be used. The barrier layer includes a material that provides a suitable band gap in a range from 0.6 eV to 7.6 eV in order to provide a suitable level of electrical isolation. For example, the barrier layer can include a material that provides a suitable electronic barrier to limit current through the active layer. In one embodiment, the barrier layer can include a material such as amorphous silicon (a semiconductor material) or aluminum oxide. More details of such memory cells can be found in U.S. Pat. No. 9,613,689, incorporated herein by reference. This particular memory system is used here for illustration only. The skilled in the art will realize other material systems can also be used.

FIG. 2depicts a cross section of an example monolithic three dimensional memory structure that includes serially connected non-volatile reversible resistance-switching Barrier Modulated Memory Cells. The memory structure depicted inFIG. 2is one example of memory structure126ofFIG. 1.

The memory structure includes a selection layer200positioned on top of metal line204and a memory layer202positioned on top of selection layer200. In one embodiment, metal line204is a source line that can be connected to a voltage source (e.g., a charge pump) or to ground. Selection layer200includes a plurality of vertically oriented transistors serving as switches. For example,FIG. 2shows a subset of those switches including switches212,214,216and218. Each of the switches is an NPN transistor that includes a vertical stack of a lower n+ layer, a p− layer above the lower n+ layer, and an upper n+ layer above the p− layer. On both sides of the NPN stack is dielectric material220(e.g., SiO2). Outside of the dielectric layer220are gate layers222(e.g., Si), in the shape of fins. Between gates222is dielectric material224(e.g., SiO2).

Memory layer202includes pluralities of serially connected non-volatile reversible resistance-switching memory cells, a plurality of word lines such that each of the memory cells of a plurality of serially connected memory cells are connected to a different word line of the plurality of word lines, bit lines connected to a first end of each of the sets of serially connected non-volatile reversible resistance-switching memory cells and selection switches (in the selection layer200) are connected to a second end of the pluralities of serially connected non-volatile reversible resistance switching memory cells.

Above each of the switches212,214,216,218are columns that include three pillars. The middle pillar is a plugging dielectric (e.g., SiO2). For example,FIG. 2shows plugging dielectric regions240,242,244and246. Each of the columns further includes barrier layers on different sides of each of the plugging dielectrics. On the left side of dielectric240is barrier layer250and one the right side is barrier layer251. On the left side of plugging dielectric242is barrier layer252and on the right side is barrier layer253. On the left side of plugging dielectric244is barrier layer254and on the right side is barrier layer255. On the left side of plugging dielectric246is barrier layer256and on the right side is barrier layer257. In one embodiment, the barrier layers are made up of amorphous silicon, and represent the barrier layers of the barrier modulated memory cells discussed above. Adjacent each of the barrier layers are active layers that are also part of the barrier modulated memory cells discussed above. For example, adjacent barrier layer251are active layer260and active layer262. Adjacent barrier layer252are active layer264and active layer266. Adjacent barrier layer253are active layer268and active layer270. Adjacent barrier layer254are active layer272and active layer274. Adjacent barrier layer255are active layer276and active layer278. Adjacent barrier256are active layer280and active layer282.FIG. 2shows only a portion of the memory structure. Therefore, there are active layers that are also adjacent barrier layers250and257. Furthermore, the memory structure continues in both directions (left of page and right of page). Furthermore,FIG. 2shows that the active layers are vertically displaced. That is, the active layers are positioned above consecutive or adjacent active layers.FIG. 2only shows two rows of active layers. However, it is contemplated that some embodiments of the memory structure will include more than two rows of active layers. In some examples, there can be 4 rows of active layers, 8 rows of active layers, 16 rows of active layers, 32 rows of active layers, 64 rows of active layers, etc. In one embodiment, the active layers are made of Tantalum Oxide (TaOx).

Adjacent to barrier layers and surrounding the active layers on three sides of the active layers are channel layers (e.g., Silicon). For example,FIG. 2shows channel layer290adjacent barrier251and surrounding active layers260and262on three sides of each active layer. Channel layer290is an electrical contact with switch212and bit line BL1. Channel292is adjacent barrier level252, surrounding active layers264and266on at least three sides of each active layer and in electrical contact with bit line BL2and switch214. Channel294is adjacent barrier layer253, surrounding active layers268and270on three sides of each active layer, in electrical contact with switch214and in electrical contact with bit line BL2. Channel296is adjacent barrier layer254, surrounds active layers272and274on three sides of each active layer, in electrical contact with switch216and in electrical contact with bit line BL3. Channel layer298is adjacent barrier layer255, surrounds active layers276and278on three sides of each active layer, in electrical contact with switch216and in electrical contact with bit line BL3. Channel layer300is adjacent barrier layer256, surrounds active layers280and282on three sides of each active layer, is in electrical contact with switch218and is in electrical contact with bit line BL4. As depicted inFIG. 2, each of the channel layers290,292,294,296,298and300are vertically elongated and directly connect to a bit line, where the bit line connects to a corresponding sense amplifier.

Each of the active layers and the associated adjacent portions of the barrier layers form the non-volatile reversible resistance-switching memory cells, which are vertically displaced as depicted inFIG. 2. Active layers260and262are part of one plurality of serially connected non-volatile reversible resistance-switching memory cells. Active layers264and266, and their associated adjacent portions of the barrier layers, are part of another plurality of serially connected non-volatile reversible-resistance switching memory cells. Active layers268and270, and their associated adjacent portions of the barrier layers, are part of another plurality of serially connected non-volatile reversible resistance-switching memory cells. Active layers272and274, and their associated adjacent portions of the barrier layers, are part of another plurality of serially connected non-volatile reversible resistance-switching memory cells. Active layers276and278, and their associated adjacent portions of the barrier layers, are part of another plurality of serially connected non-volatile reversible resistance-switching memory cells. Active layers280and282, and their associated adjacent portions of the barrier layers, are part of another plurality of serially connected non-volatile reversible resistance-switching memory cells.

The structure ofFIG. 2also includes dielectric regions301,313and325. In one example embodiment, these dielectric regions are made of SiO2. As can be seen fromFIG. 2, the dielectric regions301,313and325form pockets. For example one of those pockets is labeled with reference number350inFIG. 2. A portion of channel region290is positioned in pocket350. Additionally, a portion of active layer260is positioned in pocket350. A portion of each of the active layers is positioned in one of the pockets of the dielectric regions.

Within dielectric regions301,313and325are a plurality of vertically displaced control line layers. Each control line layer is positioned between two consecutive reversible resistance-switching elements (e.g., active layers+adjacent portion of barrier layers). Each control line comprises an offset layer and associated word line layer. Examples of control line layers depicted inFIG. 2include word line layer302and adjacent offset layer304directly below word line layer302, word line306and adjacent offset layer308directly below word line layer306, word line310and adjacent offset layer312directly below word line layer310, word line314and adjacent offset layer316directly below word line layer314, word line layer318and offset layer320directly below word line layer318, word line layer322and adjacent offset layer324directly below word line layer322, word line326and adjacent offset layer328directly below word line326, word line330and adjacent offset layer332directly below word line layer330, and word line layer334and adjacent offset layer336directly below word line layer334. In other embodiments, there can be more than three rows of control line layers. No specific number of rows is required. In one embodiment, the word line layers are made of p doped silicon and the offset layers are made of Si3N4. Other materials can also be used. Each of the word line layers can control the active layers immediately above the word line layer. The offset layers, in contact with and just below the associated word line layer, serve to shield the associated word line layers from controlling the active layers directly below the offset layer. Therefore, while a word line is vertically displaced between two consecutive active layers the word line can only control the top active layer because the associated offset layer shields the word line layer from controlling the other active layer below the offset layer. For example, word line layer306can control active layer260; however, offset308shields word line306from controlling active layer262.

FIG. 2only depicts a portion of the memory structure. In one embodiment, the memory structure will continue to the left and to the right of the cross section depicted inFIG. 2. Furthermore,FIG. 2is a cross section. In another embodiment, the memory structure will extend with more layers and cells vertically. Therefore, the structure continues into and out of the page for multiple horizontal layers. That is each of the word line layers are in a direction in and out of the page. Behind the columns and active layers depicted inFIG. 2will be additional sets of active layers in corresponding locations to create additional sets of serially connected memory cells.

FIG. 3depicts a circuit diagram of a portion of the memory structure ofFIG. 2that includes serially connected non-volatile reversible resistance-switching memory cells.FIG. 3shows a plurality of serially connected non-volatile reversible resistance-switching memory cells400connected to switch420and bit line contact412, plurality of serially connected non-volatile reversible resistance-switching memory cells402also connected to switch420and bit line contact412, plurality of serially connected non-volatile reversible resistance-switching memory cells404connected to bit line contact414and switch420, plurality of serially connected non-volatile reversible resistance-switching memory cells406connected to bit line contact414and switch420, plurality of serially connected non-volatile reversible resistance-switching memory cells408connected to bit line contact416and switch420, and plurality of serially connected non-volatile reversible resistance-switching memory cells410connected to bit line contact416and switch420. Ellipses are used inFIG. 3to indicate that the structure will continue. Each of the memory cells (MC) is serially connected to neighboring memory cells within the same plurality of memory cells (also referred to as a string). Each string or plurality of serially connected memory cells are connected on one end to switch420and at another end to a respective bit line contact BLC (and respective bit line). Switch420connects the memory cells to source line204(see alsoFIG. 2).FIG. 3shows three pairs of connected memory cells. A second pair (404and406) can be located behind the first pair (400and402) and the third pair (408and410) can be located behind the second pair (404and406) when looking at the structure ofFIG. 2. The skilled in the art will recognize that other electrical arrangement of wordlines (WLs), bitlines (BLCs) and selecting transistors (420) are possible without departing from the spirit of the technology proposed herein.

FIGS. 4A and 4Bdepict operation of example memory cells that is part of a plurality of serially connected non-volatile reversible resistance-switching memory cells. The structure ofFIG. 4Aincludes four memory cells. One of those memory cells450is indicated by the dashed line forming a box. Memory cell450includes active layer264, a portion of barrier layer292, word line layer306and offset layer308. Below offset308is another active layer266which is shielded from word line layer306by offset layer308. That structure including active layers264and266represents a first reversible resistance-switching structure, a second reversible resistance-switching structure, a control region comprising a word line layer306and an offset layer308adjacent to the word line layer. The word line layer306is on a first side of the control region facing the first reversible resistance-switching structure. The offset layer308is on the second side of the control region facing the second reversible resistance switching structure (e.g.,266). The offset layer308shields word line layer306from controlling active layer266.FIG. 4Ashows a situation when memory cell450is not selected for a memory operation. For example, word line306is at ground or a very low voltage. In this case, memory cell450is unselected so that current flows through channel292for the memory cell and bypasses the reversible resistance-switching interface458between active layer264and barrier layer292, as depicted by arrow452.

InFIG. 4B, memory cell450is selected for a memory operation. For example, memory cell450is to be programmed or read. The memory cell is selected so that current now flows through the reversible resistance-switching interface458between active layer264and barrier292and bypasses at least a portion of channel292. In this situation a larger voltage (e.g., proximately 5 volts) is applied to word line306. This voltage creates a depletion region454in channel292. Current from channel region292is forced into active layer264, through interface258and into barrier layer292(bypassing a portion of channel292because the current avoids the depletion region454), as depicted by arrow456.FIG. 4going through the interface between active layer264and barrier region292. Therefore, using gate306to turn on or off the depletion region switches the flow of current between the channel292or the interface458and, therefore. is one example of a means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface458.

The memory cells ofFIGS. 4A and 4Bcomprises a first current path and a second current path, where the first current path is reversible resistance-switching (e.g., through interface458as per arrow456) and the second current path (e.g., channel292) bypasses the first current path (as per arrow452).

FIG. 5is a flow chart describing one embodiment of a process for SETTING the memory cells. During the process ofFIG. 5, the memory cells being SET will experience the situation depicted graphically inFIG. 4B. The process ofFIG. 5is performed using the control circuitry discussed above inFIG. 1in order to control the memory cells of memory structure126(depicted inFIGS. 2 and 4A/B). In step502ofFIG. 5, the one or more control circuits apply a programming voltage to a selected bit line. As discussed above, each bit line is connected to a sense amplifier. Therefore, the sense amplifier (see corresponding Sense Block SBp) provides a programming voltage (e.g., 5 volts) to the selected bit line. In step504, the source line (e.g., line204) is connected to ground (or another small voltage). In step506, one or more unselected signals are applied to unselected word lines to cause the unselected serially connected reversible resistance-switching memory cells connected to the unselected word lines to be bypassed by current in associated channels. That is, memory cells not to be SET will be bypassed by applying an unselect signal (e.g., 0 volts) to the corresponding word lines so that the memory cells operates according toFIG. 4A. In step508, the one or more control circuits will apply a select signal to a selected word line to cause current from the selected channel to be diverted from the selected channel into and through a reversible resistance-switching interface of a selected reversible resistance-switching memory cell and subsequently back into the selected channel. That is, selected memory cells will have their corresponding word lines receive a select signal (e.g., 5 volts) in order to create a depletion region in the corresponding channels so that the memory cell operates according toFIG. 4B. As a result, the memory cell will be SET.

FIG. 6is a flow chart describing one embodiment of a process for RESETTING memory cells. In step540, bit lines are set to ground. For example, the connected sense amplifier can ground the bit line. Instead of ground, a small voltage can be used. In step542, the source line (e.g., line204ofFIG. 2) is connected to a programming voltage (e.g., 5 volts). In step544, one or more unselect signals are applied to the set of unselected word lines to cause unselected serially connected reversible resistance-switching elements connected to the unselected word lines to be bypassed by current in the associate channel. Therefore, the unselected memory cells will operate according toFIG. 4A. In step546, the one or more control circuits apply a select signal to the selected word line to cause current from the selected channel to be diverted from the selected channel into and through a reversible resistance-switching interface of a selected reversible resistance-switching element and subsequently back into the selected channel. Therefore, selected memory cells will operate based onFIG. 4B. As a result, the selected memory cells will be reset.

FIG. 7is a flow chart describing one embodiment of a process for reading memory cells. The process ofFIG. 7is performed by the one or more control circuits ofFIG. 1. In one embodiment, each sense amplifier that is connected to a bit line will include a capacitor. This capacitor is charged up. Then during the reading process it is attempted to discharge the capacitor through a bit line connected to the memory cell being read. Based on how much charge the capacitor discharges it can be determined whether the memory cell being read was in a high resistance state or a low resistance state. Other forms of sense amplifiers can also be used. In step570, the bit line is pre-charged to a pre-charge voltage. One example of a pre-charge voltage is 0.5 volts. In step572, the source line is connected to ground. For example, metal line204is connected to ground. Additionally, the appropriate select devices (e.g.,212,214,216,218) are turned on to connect the source line to the plurality of serially connected memory cells. In step574, the one or more control circuits apply one or more unselect signals to a set of unselected word lines that cause unselected serially connected reversible resistance-switching elements connected to the unselected word lines to be bypassed by current through associated channel. Therefore, the unselected memory cells will operate as depicted inFIG. 4A. In step576, the one or more control circuits apply a select signal to a selected word line to cause current from the selected channel to be diverted from the selected channel into and through a reversible resistance-switching interface of a selected reversible resistance-switching element and subsequently back into the selected channel. Therefore, selected memory cells will operate as depicted inFIG. 4B. As described, those memory cells that are not selected to be read will be bypassed while the memory cells selected to be read will have current (discharge from the capacitor) passing through the memory cells being read. In step578, the system will allow the capacitor in the sense amplifier to discharge through the bit line for a predefined period of time. In step580, the system measures the voltage across the capacitor in the sense amplifier. If the voltage is below a threshold then the resistance of the memory cell being read is a low resistance. If the voltage is not below the threshold then the resistance of the memory cell being read is high resistance.

FIG. 8is a flow chart describing one embodiment of a process for fabricating an example memory structure, such as the memory structure ofFIG. 2. In step602ofFIG. 8, selection layer200is fabricated. In step604, memory layer202is fabricated. In step606, the selection devices (e.g., switches212,214,216and218) of selection layer200are connected to memory layer202(e.g., are connected to the pluralities of serially connected non-volatile reversible resistance-switching memory cells). In step608, the bit lines are connected to the memory layer. For example, but lines (BL1-BL4) are connected to the top of the channels of the plurality of serially connected non-volatile reversible resistance-switching memory cells.

FIG. 9is a flow chart describing one embodiment of a process for fabricating an example selection layer200. Thus, the process ofFIG. 9is one example implementation of step602ofFIG. 8. In step650, an n+ layer will be deposited. For example, this can be accomplished using Chemical Vapor Deposition (“CVD”) or Atomic Layer Deposition (“ALD”). In step652, a p− layer will be deposited on top of the n+ layer. The p− layer is deposited using CVD or ALD. In step654, an n+ layer will be deposited on top of the p− layer of step652using CVD or ALD.FIG. 10Adepicts the state of the structure after step654. As can be seen, the structure includes n+ layer702(from step650), p− layer704(from step652), and n+ layer706(from step654). N+ layer702is positioned on top of metal line204(seeFIG. 2).

In step652ofFIG. 9, trenches will be etched through the three layers using a reactive ion etch.FIG. 10Bshows the structure with trenches710,712and714.FIG. 10Bonly shows a portion of the complete structure; therefore, only three trenches are depicted. In the actual structure, there will be many more than three trenches. As a result of the etching, NPN stacks are formed corresponding to switches212,214,216and218(seeFIG. 2).

In step658ofFIG. 9, an oxide will be grown on the side walls of each of the NPN stacks. In one embodiment, SiO2if thermally grown on the side of each of the NPN stacks.FIG. 10Cshows oxide220on the side of NPN stacks corresponding to switches212,214,216and218.

In step660ofFIG. 9, gate material will be deposited between the stacks. For example, Silicon will be deposited using CVD or ALD. In step662, the gate materials will be etched using a reactive ion etch.FIG. 10Dshows the structure after step652, including gates222in the shape of fins as a result of the reactive ion etch.

In step664ofFIG. 9, the trenches will be filled in with a dielectric (e.g., SiO2) using CVD or ALD. The dielectric is filled above the top of the NPN stacks corresponding to switches212-218. These stacks are also referred to as rails. In step666, the process will etch the dielectric part way down to expose the top of the rails/switches. In step668, the process will etch in a cross direction to separate the rails into posts for connection to the strings of serially connected memory cells. The result of step668is depicted at the bottom ofFIG. 2.

FIG. 11is a flow chart describing one embodiment of a process of fabricating an example memory layer (e.g., memory layer202ofFIG. 2). Therefore, the process ofFIG. 11is one example implementation of step604ofFIG. 8. In step750ofFIG. 11, the fabrication process includes depositing repeating groups of three layers (or at least three layers—as additional layers can be included with the three layers). Each group comprise a word layer (e.g., p-Si), an offset layer (e.g., Si3N4) and a dielectric layer (e.g., SiO2).FIG. 12Adepicts the results of step750. For example,FIG. 12Ashows a first group802of three layers and a second group804of three layers. Three layers of group802include word line layer810, offset layer812and dielectric layer814. The three layers of group804include word line layer816, offset layer818and dielectric layer820. In some embodiments, the structure includes more than two groups of three layers. In addition, additional layers outside any of the groups can be included. For example,FIG. 12Ashows word line822, offset layer824and dielectric layer826, as well as dielectric layer828.

In step752, trenches are etched through the layers. The result of step752is depicted inFIG. 12B, which shows trenches829and830etched into the layers. Step752results in the creation of a set of stacks832,834and836. Stack832includes dielectric layer840, word line layer302, offset layer304, dielectric layer842, word line layer306, offset layer308, dielectric layer844, word line layer310, offset layer312, and dielectric layer846. Stack834includes dielectric layer850, word line layer314, offset layer316, dielectric layer852, word line layer319, offset layer320, dielectric layer854, word line layer322, offset layer324, and dielectric layer856. Stack836includes dielectric layer858, word line layer336, offset layer328, dielectric layer860, word line layer330, offset layer332, dielectric layer862, word line layer334, offset layer336, and dielectric layer864.

In step754, selective etching is performed on the dielectric areas in the trenches to create pockets. With selective etching, SiO2etches faster. For example, a wet etching process can be used. In step756, oxide is added to the sidewalls of the trenches. For example, conformal oxide deposition or ALD can be used. The result of the steps754and756is depicted inFIG. 12C. As can be seen, a set of pockets870have been selectively etched into the dielectric regions301,313and325. Note that one of the pockets is also labeled with reference on the350to showFIG. 12Ccorrelating toFIG. 2. As discussed above, portions of the channels and the active layers will later be positioned inside pockets870.

In step758, channel material (e.g., Si) is deposited in the trenches so that at least a portion of that channel material is positioned in the pockets870. In one example, CVD or ALD is used to deposit the channel material.FIG. 12Ddepicts the result of step758. As can be seen, channels290,292,294,296,298and300have been added such that a portion of those channels are inside the pocket870.

In step760ofFIG. 11, active layer material (e.g., TaOx) is deposited in the trenches so that a portion of the activate layer material is positioned in the pockets and the channel surrounds the active layer on at least portions of three sides. In one embodiment, the active layer material is deposited using CVD or ALD. The result of step760is depicted inFIG. 12Ewhich shows the additional of active material900,902,904,906,908, and910.

In step762, the active layer material is etched to expose the channel material. For example, a reactive ion etching can be used, where the Silicon becomes a stopper for the etching. The results of step762are depicted inFIG. 12Fwhich shows portions of active layer material missing such that the result is the active layers260,262,264,266,268,270,272,274,276,278,280and282. Additionally, vertically elongated channels290,292,294,296,298and300are now exposed.

In step764, the barrier layer is deposited. In one embodiment, the barrier layer is Amorphous Silicon. The barrier layer can be deposited using CVD, ALD or low pressure channel vapor deposition (“LPCVD”). The result of step764is depicted inFIG. 12G, which shows barrier layers250,251,252,253,254,255,256and257.

In step766, plugging dielectric is deposited. For example, the dielectric can include SiO2. The plugging dielectric can be deposited using CVD or ALD. The result of step766is depicted inFIG. 12H, which shows the addition of plugging dielectrics240,242,244, and246.

The embodiment ofFIG. 2is a three dimensional structure which includes vertical sets of serially connected reversible resistance-switching memory cells. In other embodiments, memory structure126ofFIG. 1can be two dimensional memory array which include sets of serially connected reversible resistance-switching memory cells.FIG. 13depicts one example of a set of serially connected reversible resistance-switching cells appropriate for a two dimensional memory array. In such a memory array, there will be multiple sets of connected memory cells as depicted inFIG. 13. The structure ofFIG. 13includes a channel layer1002(e.g., Si). Below the channel layer is barrier layer1004, barrier layer1008, and barrier layer1012. Between barrier layer1004and barrier layer1008is active layer1006. Between barrier layer1008and barrier layer1012is active layer1010.FIG. 13shows reversible resistance-switching interface1014between active layer1006and barrier layer1004, reversible resistance-switching interface1016between active layer1006and barrier layer1008, reversible resistance-switching interface1018between barrier layer1008and active layer1010, and reversible resistance-switching interface1020between active layer1010and barrier layer1012. These interfaces are used as discussed above to implement barrier modulated memory cells

Each reversible resistance-switching interface (1014,1016,1018and1020) implements a memory cell of the serially connected reversible resistance-switching memory cells. Thus,FIG. 13shows four serially connected reversible resistance-switching memory cells. Above each reversible resistance-switching interface is a gate. For example, above interface1014(and above channel1002) is Gate1, above interface1016(and above channel1002) is Gate2, above interface1018(and above channel1002) is Gate3, and above interface1020(and above channel1002) is Gate4. At one end of channel1002is source line connection (SLC). At the other end of channel1002is a bit line connection (BLC). Each of the gates depicted inFIG. 13include three layers. The first layer of each gate (1030,1040,1050and1060) comprises a dielectric layer (e.g., SiO2). The middle layer (1032,1042,1052,1062) comprises a semiconductor layer (e.g., Si). The top layer (1034,1044,1054and1064) comprise a metal contact. With respect to the structure ofFIG. 13, the plurality of serially connected non-volatile reversible resistance-switching memory cells include a common horizontal channel1002and the plurality of serially connected non-volatile reversible resistance-switching memory cells are horizontally displaced. Additionally, the gates overlap the barrier layer, the active layer and the reversible resistance-switching interface.

When a large enough voltage (e.g., 5 volts) is applied to a gate, that gate causes a depletion region to exist in channel1002to divert current from channel1002into the appropriate active layer or barrier layer, through the interface to the adjoining barrier or active layer and then back to the channel. Therefore, only memory cells with the gate voltage high enough are selected for a memory operation. Memory cells with a low gate voltage (e.g., 0 volts) will have no depletion region and the current will bypass those memory cells (e.g., current flows in channel). Thus, the memory cells ofFIG. 13will operate as discussed above with respect toFIGS. 4A, 4B, 5, 6 and 7.

The embodiment ofFIG. 2, as fabricated by the process ofFIG. 11utilizes a trench based fabrication process that creates a set of vertically elongated rails. In another embodiment, after creating the various layers depicted inFIG. 12A, holes can be drilled, these holes are referred to as memory holes. A structure somewhat similar toFIG. 2can be fabricated inside the memory holes. However, the various layers inserted in the memory holes will be circular such as structure depicted byFIGS. 14 and 15. The top ofFIGS. 14 and 15show a portion of the memory structure. The same portion is depicted in bothFIGS. 14 and 15. The bottom ofFIG. 14shows a top down cross section, where the cross section is taking along line AA ofFIG. 14.FIG. 15shows a top down cross section where the cross section is taking along line BB. As can be seen from the structures ofFIGS. 14 and 15, the memory system includes dielectric material1102. Positioned inside dielectric material1102is gate layer1120and offset layer1122. The center of the memory hole includes a core including plugging dielectric1130surrounded by barrier layer1132. Channel1134surrounds barrier layer1132and also surrounds (on three sides) active layer1106and active layer1108. Cut AA ofFIG. 14is a cross section through active layer1108. Cut BB ofFIG. 15is a cross section through word line layer1120.

The proposed memory structures described above provides for a non-volatile memory where unselected memory cells are transparent to the current used to perform programming and/or reading. Thus, these unselected memory cells do not leak current and do not cause unnecessary use of power.

One embodiment includes a non-volatile storage apparatus, comprising: a first plurality of serially connected non-volatile reversible resistance-switching memory cells; a first plurality of word lines, each of the memory cells of the plurality are connected to a different word line of the first plurality of word lines; a first bit line connected to a first end of the first plurality of serially connected non-volatile reversible resistance-switching memory cells; and a first switch connected to a second end of the first plurality of serially connected non-volatile reversible resistance-switching memory cells.

In one example, the apparatus further comprises additional pluralities of serially connected non-volatile reversible resistance-switching memory cells, for each plurality of serially connected non-volatile reversible resistance-switching memory cells each of the memory cells is connected to a different word line of the first plurality of word lines; additional bit lines connected to the additional pluralities of serially connected non-volatile reversible resistance-switching memory cells, different bit lines are connected to different pluralities of serially connected non-volatile reversible resistance-switching memory cells; and additional switches connected to the additional pluralities of serially connected non-volatile reversible resistance-switching memory cells, different switches are connected to different pluralities of serially connected non-volatile reversible resistance-switching memory cells.

One embodiment includes a non-volatile storage apparatus, comprising: a plurality of vertically displaced reversible resistance-switching elements; a plurality of vertically displaced control line layers, each control line layer positioned between two consecutive reversible resistance-switching elements, each control line layer comprising an offset layer and an associated word line layer, the offset layer shields the associated word line layer form controlling one of the two consecutive reversible resistance-switching elements; a vertical channel layer positioned between the vertically displaced reversible resistance-switching elements and the vertically displaced control line layers; and a bit line connected to a first end of the channel layer.

One embodiment includes a non-volatile storage apparatus, comprising: a switch; a core comprising two vertical pillars of barrier layers separated by dielectric material positioned above the switch; a first plurality of vertically displaced active layers positioned on a first side of the core in contact with one of the vertical pillars of barrier layers; a second plurality of vertically displaced active layers positioned on a second side of the core in contact with one of the vertical pillars of barrier layers; a first vertical channel connected to the switch and positioned along a portion of the first side of the core and at least partially surrounding each of the first plurality of vertically displaced active layers on three sides; and a second vertical channel connected to the switch and positioned along a portion of the second side of the core and at least partially surrounding each of the second plurality of vertically displaced active layers on three sides.

One embodiment includes a method of operating non-volatile storage, comprising: applying one or more unselect signals to a set of unselected word lines to cause unselected serially connected reversible resistance-switching elements connected to the unselected word lines to be bypassed by current in an associated channel; and applying a select signal to a selected word line to cause current from the selected channel to be diverted from the selected channel into and through a reversible resistance-switching interface of a selected reversible resistance-switching element and subsequently back into the selected channel.

One embodiment includes a non-volatile storage apparatus, comprising: a first a reversible resistance-switching structure; a second a reversible resistance-switching structure; and a control region comprising a word line layer and an offset layer adjacent to the word line layer, the word line layer on a first side of the control region facing the first a reversible resistance-switching structure, the offset layer on a second side of the control region facing the second reversible resistance-switching structure, the offset layer shielding the word line layer from controlling the second reversible resistance-switching structure.

One embodiment includes a non-volatile storage apparatus, comprising: a dielectric region having a pocket; a word line layer inside and surrounded by the dielectric region, the word line layer positioned below the pocket; a reversible resistance-switching structure at least partially positioned in the pocket; and a channel layer positioned between the word line layer and the reversible resistance-switching structure, the channel layer at least partially positioned in the pocket.

One embodiment includes a non-volatile storage apparatus, comprising: a barrier layer; an active layer in contact with the barrier layer forming a reversible resistance-switching interface between the active layer and the barrier layer a gate layer that is in proximity to the reversible resistance-switching interface; and a channel region between the gate layer and the reversible resistance-switching interface.

One embodiment includes a non-volatile storage apparatus, comprising a reversible resistance-switching structure comprising a first material, a second material and a reversible resistance-switching interface between the first material and the second material; a channel; and means for switching current between current flowing through the channel and current flowing through the reversible resistance-switching interface in order to program and read the reversible resistance-switching interface.

One embodiment includes a method of operating non-volatile storage, comprising: unselecting a non-volatile memory cell so that current flows through a channel for the memory cell and bypasses a reversible resistance-switching interface between a first material and a second material; and selecting the non-volatile memory cell so that current flows through the reversible resistance-switching interface and bypasses at least a portion of the channel.

One embodiment includes a method for fabricating non-volatile memory, comprising: depositing multiple word line layers and multiple dielectric layers; creating trenches in the multiple word line layers and multiple dielectric layers; etching the multiple dielectric layers in the trenches to create pockets in the dielectric layers; adding channel material to the trenches; and adding active layers to the trenches so that a portion of each of the active layers is positioned in one of the pockets.

One embodiment includes a method for fabricating non-volatile memory, comprising: depositing repeating groups of at least three layers, each group of three layers comprising a word line layer, an offset layer adjacent the word line layer and a dielectric layer; creating trenches in the repeating groups of three layers; adding channel material to the trenches; and adding active layers vertically displaced in the trenches such that one of the word line layers and one of the offset layers are vertically positioned between neighboring active layers.

One embodiment includes a method for fabricating non-volatile memory, comprising: depositing multiple word line layers and multiple dielectric layers; creating trenches in the multiple word line layers and multiple dielectric layers; adding channel material to the trenches; and adding active layers to the trenches so that channel material at least partially surrounds each active layer on three sides.

One embodiment includes a method for fabricating non-volatile memory, comprising: creating multiple pluralities of serially connected non-volatile reversible resistance-switching memory cells including creating a plurality of word lines, each of the memory cells is connected to a different word line of the plurality of word lines; connecting bit lines to the pluralities of serially connected non-volatile reversible resistance-switching memory cells; and connecting selection switches to the pluralities of serially connected non-volatile reversible resistance-switching memory cells.