SEMICONDUCTOR DEVICES HAVING VERTICAL CHANNEL TRANSISTOR STRUCTURES AND METHODS OF FABRICATING THE SAME

A semiconductor device includes: a conductive line that extends in a first direction on a substrate; an insulating pattern layer on the substrate and having a trench that extends in a second direction, the trench having an extension portion that extends into the conductive line; a channel layer on opposite sidewalls of the trench and connected to a region, exposed by the trench, of the conductive line; first and second gate electrodes on the channel layer, and respectively along the opposite sidewalls of the trench; a gate insulating layer between the channel layer and the first and second gate electrodes; a buried insulating layer between the first and second gate electrodes within the trench; and a first contact and a second contact, respectively buried in the insulating pattern layer, and respectively connected to upper regions of the channel layer.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims the benefit of priority to Korean Patent Application No. 10-2021-0066831, filed on May 25, 2021, in the Korean Intellectual Property Office, and the entire contents of the above-identified application are incorporated by reference herein.

TECHNICAL FIELD

The present disclosure relates to semiconductor devices and to methods of fabricating the same.

BACKGROUND

Semiconductor devices have become increasingly highly integrated for a variety of reasons, including to satisfy requirements for higher levels of performance desired by customers.

Integration of typical two-dimensional or planar semiconductor devices is primarily determined by the area occupied by a unit memory cell. Reducing an area occupied by a unit memory cell requires an ability to form fine patterns (e.g., via semiconductor lithography), and as such, the integration of planar semiconductor devices is significantly affected by the level of technology for forming fine patterns. However, as significantly expensive process equipment is typically required to generate increasingly fine patterns, a practical limitation exists with respect to increasing the integration density of two-dimensional semiconductor devices. Therefore, three-dimensional semiconductor memory devices including three-dimensionally-arranged memory cells have been proposed.

SUMMARY

Aspects of the present disclosure provide semiconductor devices having vertical channel transistor (VCT) structures with improved electrical characteristics.

Aspects of the present disclosure provide methods of fabricating semiconductor devices having VCT structures with improved electrical characteristics.

According to some embodiments of the present disclosure, a semiconductor device may include: a substrate; a conductive line on the substrate and extending in a first direction; and an insulating pattern layer on the substrate and having a trench that extends in a second direction that intersects the first direction. The trench may have an extension portion that extends inwardly of the conductive line. The semiconductor device may include a channel layer on opposite sidewalls of the trench and connected to a region of the conductive line that is exposed by the extension portion of the trench. The semiconductor device may include a first gate electrode and a second gate electrode on the channel layer, and respectively along the opposite sidewalls of the trench; a gate insulating layer between the channel layer and the first and second gate electrodes; a buried insulating layer between the first and second gate electrodes within the trench; and a first contact and a second contact respectively buried in regions adjacent to the opposite sidewalls of the trench in the insulating pattern layer, and respectively connected to upper regions of the channel layer.

According to some example embodiments, a semiconductor device may include: a substrate; a plurality of conductive lines extending in a first direction on the substrate, and spaced apart from each other in a second direction that intersects the first direction; an insulating pattern layer that extends in the second direction on the substrate, and having a plurality of trenches spaced apart from each other in the first direction, each trench of the plurality of trenches having an extension portion that extends into the plurality of conductive lines; a plurality of channel layers on opposite sidewalls of each of the plurality of trenches and arranged in the second direction, the channel layers connected to regions exposed in the plurality of conductive lines exposed by the extension portions of the plurality of trenches; a plurality of first gate electrodes and a plurality of second gate electrodes on the plurality of channel layers in each of the plurality of trenches, and respectively extending on the opposite sidewalls of each of the plurality of trenches; a plurality of gate insulating layers between the plurality of channel layers and the plurality of first and second gate electrodes in each of the plurality of trenches; a plurality of buried insulating portions, respectively within the plurality of trenches, and between the plurality of first and second gate electrodes; and a plurality of first contacts and a plurality of second contacts buried in the insulating pattern layer and connected to upper regions of the plurality of channel layers adjacent to the opposite sidewalls of each of the plurality of trenches.

According to an example embodiment, a semiconductor device includes: a substrate; a conductive line extending in a first direction on the substrate; an insulating pattern layer on the substrate and having a trench that extends in a second direction that intersects the first direction; a channel layer arranged on opposite sidewalls of the trench and electrically connected to the conductive line at a bottom of the trench, the channel layer including an oxide semiconductor; a first gate electrode and a second gate electrode respectively on the opposite sidewalls of the trench on the channel layer; a gate insulating layer between the channel layer and the first and second gate electrodes and having a U-shape in a cross-section taken in the second direction; a buried insulating portion between the first and second gate electrodes within the trench and including a material that is different from a material of the insulating pattern layer; and a first contact and a second contact, electrically connected with respective upper regions of the channel layer.

According to some example embodiments, a method of fabricating a semiconductor device includes: forming a conductive line that extends in a first direction on a substrate; forming an oxide insulating layer on the substrate that covers the conductive line; forming a trench that extends in a second direction in the oxide insulating layer and has a bottom that exposes a region of the conductive line, the second direction intersecting the first direction; forming a channel layer including an oxide semiconductor on opposite sidewalls of the trench and connected to the exposed region of the conductive line; forming a gate insulating layer on an internal sidewall of the trench that covers the channel layer; forming a first gate electrode and a second gate electrode on each of the opposite sidewalls of the trench on the channel layer; forming a buried insulating portion between the first and second gate electrodes within the trench, the buried insulating portion comprising a material that is different from a material of the oxide insulating layer; forming a first contact and a second contact connected to respective upper regions of the channel layer; and annealing the channel layer in an oxygen-containing atmosphere.

DETAILED DESCRIPTION

Hereinafter, some example embodiments will be described with reference to the accompanying drawings.

FIG.1is a plan view of a semiconductor device according to some example embodiments, andFIGS.2A and2Bare cross-sectional views taken along lines I-I′ and II-II′ of the semiconductor device ofFIG.1, respectively.

Referring toFIGS.1,2A, and2B, a semiconductor device100according to some example embodiments may include a cell array implemented using a semiconductor memory device. As illustrated inFIG.1, the cell array may include a plurality of bitlines BL that extend in length in a first direction D1and a plurality of wordlines WL that extend in length in a second direction D2that intersects the first direction D1. The cell array may include a plurality of memory cell transistors MCT, with each memory cell transistor MCT arranged at a respective intersection between a wordline WL of the plurality of wordlines WL and a bitline BL of the plurality of bitlines BL. At least one of a plurality of data storage elements DS may be arranged in each of the plurality of cell transistors MCT.

The substrate101may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. An insulating layer105may be on the substrate101. The semiconductor device100may have a structure in which a plurality of bitlines BL or110, a plurality of memory cell transistors MCT, a plurality of wordlines WL or150, and a plurality of data storage elements DS are sequentially stacked on the substrate101in a third direction D3, perpendicular to an upper surface of the substrate101.

The plurality of bitlines BL may include a plurality of conductive lines110arranged side by side in the second direction D2on the substrate101. Each of the plurality of conductive lines110may have a width in the second direction D2. The plurality of conductive lines110may be electrically separated from the substrate101by the insulating layer105. The plurality of conductive lines110may be separated from each other by a first insulating pattern layer108. The first insulating pattern layer108may have an upper surface that is substantially planar with an upper surface of the plurality of first conductive lines110. Each of the plurality of conductive lines110may include a single conductive layer or a plurality of conductive layers. For example, the bitlines BL may include at least one of a doped semiconductor material (doped silicon, doped germanium, or the like), a conductive metal nitride (titanium nitride, tantalum nitride, or the like), a metal (tungsten, titanium, tantalum, or the like), and a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, or the like). In some example embodiments, the plurality of conductive lines110may each include a first conductive layer112such as tungsten (W) and a second conductive layer115, such as titanium nitride (TiN), arranged on the first conductive layer112. In some example embodiments, the first insulating pattern layer108may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

The wordlines WL may be connected with and/or include first and second gate electrodes150A and150B of the memory cell transistors MCT on the substrate101. In the cell array (seeFIG.1), the wordlines WL may be spaced apart from each other in a first direction D1.FIG.3is a plan view of a memory cell transistor (MCT) array in the region “A” of the semiconductor device ofFIG.1. Referring toFIG.3together withFIG.1, each of the first and second gate electrodes150A and150B may extend in length in the second direction D2and may be provided as gate electrodes of the plurality of memory cell transistors MCT arranged in the second direction D2. In some example embodiments, the wordlines WL may be provided as separate conductive lines connected to the first and second gate electrodes150A and150B. For example, such wordlines (not illustrated) may include a conductive material similar to that of the bitlines BL, and may be on a first insulating layer181and connected with upper ends of the first and second gate electrodes150A and150B.

As described above, a gate of the memory cell transistor MCT may be connected to a wordline WL, and a source of the memory cell transistor MCT may be connected to a bitline BL.

The memory cell transistor MCT of the semiconductor device100according to some example embodiments may include a vertical channel transistor VCT. Such a vertical channel transistor may include a channel layer130having a length of a channel that extends in the third direction D3, perpendicular to an upper surface of the substrate101.

A second insulating pattern layer120may be on the first insulating pattern layer108and the plurality of conductive lines110. The second insulating pattern layer120may include a trench T that defines a vertical channel transistor region. The trench T may extend in the second direction D2, and a partial region of the conductive line110may be exposed through a bottom surface of the trench T (seeFIGS.12A and12B). In some example embodiments, the trench T may have an extension portion Te that extends inwardly of the conductive line110. Stated differently, the extending or extension portion Te of the trench T may extend into the conductive line110or a portion thereof. As illustrated inFIG.2A, the extension portion Te of the trench T may be arranged in the second conductive layer115of the conductive lines. The second insulating pattern layer120may include a material that is similar to that of the first insulating pattern layer108. For example, the second insulating pattern layer120may include at least one of a silicon oxide layer and a silicon oxynitride layer.

A plurality of channel layers130may be on opposite sidewalls of the trench T and may be connected to a region of the conductive line110that is exposed by the extension portion Te of the trench T. Stated differently, the plurality of channel layers130may be within the trench T. The plurality of channel layers130may be arranged in a matrix form in the first direction D1and the second direction D2to be respectively disposed on regions, exposed by the trench T, of the conductive line110.

In some example embodiments, and as seen inFIG.2A, the channel layer130may have a U-shape in a cross-section in the first direction D1. Specifically, as illustrated inFIG.2A, the channel layers130may have first and second vertical channel elements130A and130B that extend in the third direction D3along respective and opposite sidewalls of the trench T of the second insulating pattern layer120, and a horizontal connection portion130C that connects the first and second vertical channel elements130A and130B and extends along a bottom of the trench T. The channel layer130may have a width defined in the first direction D1and a height (Lc ofFIG.4) in the third direction D3. The height (Lc inFIG.4) of the channel layer130may be larger than the width of the channel layer130. For example, the height may be about 2 to 10 times the first width, but the present disclosure and the example embodiments thereof are not limited thereto.

Each of the first and second vertical channel elements130A and130B may have a lower region that overlaps the conductive line110(or a portion thereof) in a horizontal direction (for example, the first direction D1). An upper surface of the conductive line110(for example, a region in which the trench T is not formed) may be higher than a lowermost level of the first and second vertical channel elements130A and130B. The horizontal connection portion130C may be connected to the conductive line110. An upper surface of the horizontal connection portion130C may be below an upper surface of the conductive line110. In some embodiments, the horizontal connection portion130C may be buried within the conductive line110.

In some embodiments, first and second contacts170A and170B may be buried in the second insulating layer120in respective regions thereof that are adjacent to the opposite sidewalls of the trench T. The first and second contacts170A and170B may be connected to upper regions of the channel layers130. The first contact170A may be connected to the first vertical channel element130A, and the second contact170B may be connected to the second vertical channel element130B. The first and second contacts170A and170B may be in partial contact with the channel layer130in a horizontal direction (for example, the first direction D1).

As described above, the lower region or the bottom portion (for example, the horizontal connection portion130C) of the channel layer130may be connected to the conductive line110and may provide a first source/drain region, and the upper region of the channel layer130may be connected to the first and second contacts170A and170B and may provide a second source/drain region. A region of the channel layer130between the first and second source/drain regions, for example, a partial region of the first and second horizontal channel elements130A and130B, may serve as a channel region.

In some example embodiments, as illustrated inFIGS.2A,2B, and3, a portion of the upper surface of the second insulating pattern layer120may be provided as an upper surface of the memory cell transistor MCT in a region between the first and second contacts170A and170B. Such an opened upper region of the second insulating pattern layer120may be provided as a path to the channel layer130, because oxygen may be introduced thereinto when an annealing process is applied in an oxygen atmosphere to improve characteristics of the channel layer130(for example, an oxide semiconductor). This will be described in detail later with reference toFIG.4.

In some example embodiments, the channel layer130may have low leakage current characteristics and may include a stackable oxide semiconductor. For example, the channel layer130may include an oxide semiconductor containing indium (In). The oxide semiconductor may be one of indium-gallium-zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium tin gallium oxide (ITGO), indium tungsten oxide (IWO), indium tin oxide (ITO), ZnO, and Cu2O. In some example embodiments, the channel layer130may have a multilayer structure. For example, the channel layer130may include a combination of amorphous indium-gallium-zinc oxide (a-IGZO) and c-axis aligned crystalline indium-gallium-zinc oxide (CAAC-IGZO), a combination of a-IGZO and Spinel IGZO, or a combination of IGZO and other oxide semiconductors. The channel layer130is not limited thereto. In some embodiments, the channel layer130may have a bandgap energy greater than a bandgap energy of silicon. For example, the channel layer130may be a polycrystalline or amorphous layer having a bandgap energy of about 1.5 eV to 5.6 eV or about 2.0 eV to 4.0 eV. The channel layer130may include MoS2, WS2, graphene, or hexagonal boron nitride (h-BN).

The gate insulating layer140may surround a sidewall of the channel layer130. In some example embodiments, the gate insulating layer140may extend in the first direction D1to cover the plurality of channel layers130arranged along a single trench T (seeFIG.3). The gate insulating layer140may have a U-shape in a cross-section (seeFIG.2A) in the first direction D1that is similar to the U-shape cross-section of the channel layer130. In some example embodiments, as illustrated inFIG.2A, the gate insulating layer140may include a first gate insulating element140A on the first vertical channel element130A, a second gate insulating element140B on the second vertical channel element130B, and a bottom insulting portion140C that connects the first and second gate insulating elements140A and140B to each other. The gate insulating layer140may include a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer having a higher dielectric constant than the silicon oxide layer, and/or combinations thereof, with the present disclosure not limited thereto. The high-k dielectric layer may include, but is not limited to, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or combinations thereof.

The first and second gate electrodes150A and150B may be on respective and opposite sidewalls of the channel layer130, with the gate insulating layer140interposed therebetween. As illustrated inFIG.3, the first and second gate electrodes150A and150B may be divided into a plurality of gate electrodes, respectively arranged to correspond to the first and second vertical channel elements130A and130B of the channel layer130in a single trench T. The first and second gate electrodes150A and150B may include doped polysilicon, a metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, and/or combinations thereof. For example, the first and second gate electrodes150A and150B may include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, and/or combinations thereof.

As illustrated inFIGS.2A and3, each channel layer130in a single trench T and first and second gate electrodes150A and150B facing each other in the channel layer130may constitute a dual transistor structure DT. That is, each of the dual transistor structures TC may include two unit transistor cells UC having a bilateral symmetrical structure. The first vertical channel element130A, the first gate electrode150A, and a portion of the gate insulating film140therebetween may constitute one unit transistor cell UC. Similarly, the second vertical channel element130B, the second gate electrode150B, and a portion of the gate insulating layer140therebetween may constitute another unit transistor cell UC.

A buried insulating part160may be in the first direction D1along a facing unit transistor cell UC in a single trench T. The buried insulating part160may extend in the first direction D1to fill some or all of a remaining space in the trench T along the space between the first and second gate electrodes150A and150B (FIG. see3). The buried insulating part160may have an upper surface that is substantially planar with an upper end of the channel layer130. In addition, the upper surface of the buried insulating part160may be substantially planar with an upper surface of the gate insulating layer140and upper ends of the first and second gate electrodes150A and150B.

A plurality of interconnection portions190may connect the first and second contacts170A and170B to the first insulating layer181on the upper surface of the memory cell transistor MCT. The plurality of interconnection portions190may extend to overlap a partial region of the channel layer130in the third direction D3. As illustrated inFIG.1, the plurality of interconnection portions190may be arranged in a matrix to be spaced apart from each other in the first direction D1and the second direction D2. For example, the interconnect portions190may include, but is not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or combinations thereof.

A second insulating layer183may be on the first insulating layer181, and data storage elements DS may be in or on the second insulating layer183. The data storage elements DS may be arranged in a matrix form to respectively correspond to the interconnection portions190(seeFIG.1). The data storage elements DS may be memory elements which may store data. Each of the data storage elements DS may be a memory element that uses a capacitor, a memory element that uses a magnetic tunnel junction pattern, or a memory element that uses a variable resistor including a phase change material. As an example, each of the data storage elements DS may be a capacitor. Each of the memory cell transistors MCT may be configured to be connected to a respective data storage element DS. In some embodiments, the data storage element DS may be a capacitor and a drain of the memory cell transistor MCT may be connected to the capacitor.

Specifically, each of the data storage elements DS may include a first electrode EL1, a dielectric layer DL, and a second electrode EL2connected to each of the interconnections190. In some example embodiments, the data storage elements DS may share a single dielectric layer DL and a single second electrode EL2. In other words, a plurality of first electrodes EL1may be provided, and a single dielectric layer DL may cover surfaces of the first electrodes EL1. A single second electrode EL2may be provided on a single dielectric layer DL. Each of the first electrodes EL1may be in the form of a cylinder having one end open. The second electrode EL2may fill the inside of the cylinder of the first electrode EL1. The present disclosure and the second electrode EL2thereof are not limited to such a structure. For example, the second electrode may be provided in a pillar structure.

In some example embodiments, as described above, the channel layer130, and in particular the first and second vertical channel elements130A and130B thereof, may contact each other while partially overlapping the conductive line110and the first and second contacts170A and170B. Thus, the channel layer130may be formed to have an effective channel length that is lower than a physically vertical length Lc of the channel layer130. As a result, ON-current characteristics (that is, Ion) of the channel layer130may be improved. Hereinafter, this will be described in greater detail with reference toFIG.4.

FIG.4is a cross-sectional view taken along line II-II′ of the MCT array ofFIG.3.

Referring toFIG.4, a vertical length Lc of the channel layer130, or in other words, heights of the first and second vertical channel elements130A and130B may be defined as a depth of the trench T. In some example embodiments, the vertical length Lc may be represented as the sum of a height of the second insulating pattern layer120and a depth of an extension portion Te of the trench T formed in the conductive line110.

A lower region of each of the first and second vertical channel elements130A and130B may overlap the conductive line110in a horizontal direction (for example, the first direction D1) by a width corresponding to a depth Da of the extension portion Te of the trench. In an upper surface of the conductive line110, a region in which the trench T is not formed may be higher than a lowermost level of the first and second gate electrodes150A and150B by a height denoted by Da′. An upper region of each of the first and second vertical channel elements130A and130B may partially overlap the first and second contacts170A and170B in the horizontal direction (for example, D1) by a depth Db at which the first and second contacts170A and170B are buried.

The effective channel length of the channel layer130may be defined as a value Le obtained by excluding a total length of overlapping portions Da+Db from the physically vertical length Lc of the channel layer130(e.g., Le=Lc−Da−Db). As described above, the arrangement of elements corresponding to a source/drain electrode may be structurally adjusted to reduce the effective channel length Le of the channel layer130, and thus, ON-current characteristics (that is, Ion) of the channel layer130may be improved. For example, the effective channel length Le of the channel layer130may range from 10 nm to 200 nm. Each of the widths Da and Db of the overlapping portions may range from 2 nm to 50 nm.

A channel layer material such as an oxide semiconductor (for example, IGZO) may be problematic in current characteristics due to relatively low carrier mobility while being stackable and having low leakage current characteristics. However, the channel layer may be changed to have a structure that overlaps the first and second contacts170A and170B and/or the conductive lines110, so that current characteristics may be significantly improved. For example, when the channel layer is IGZO, an ON-current (Ion) characteristic may be increased by 10 to 20 times by employing a structure similar to that ofFIG.2A. In some example embodiments, only a contact structure of one side of the first and second contacts170A and170B and the conductive lines110may overlap the channel layer130(seeFIGS.8and9).

In addition, an annealing process may be applied to the plurality of channel layers130to improve electrical characteristics (for example, channel leakage current characteristics when turned off). For example, when the plurality of channel layers130include an oxide semiconductor, an annealing process may be applied in an oxygen atmosphere.

In some example embodiments, a path through which oxygen is introduced through a region of the second insulating pattern layer120between the first and second contacts170A and170B to permeate into the channel layer130, as indicated by {circle around (1)} ofFIG.3, during an annealing process in an oxygen atmosphere, may be formed. The second insulating pattern layer120may be an oxygen-containing insulating material. For example, the second insulating pattern layer120may include silicon oxide (SiO2) or silicon oxynitride (SiON).

In addition, the present disclosure provides several methods of protecting a specific region from oxygen permeation during an oxygen annealing process.

To protect the first and second gate electrodes150A and150B from oxygen permeation (see {circle around (2)}), the buried insulating portion160may be provided as a material that is different from the second insulating pattern layer120. For example, the buried insulating portion160may be provided as an oxygen blocking layer. In some example embodiments, the buried insulating portion160may include an insulating material that has an oxygen diffusivity that is lower than oxygen diffusivity in the material of the second insulating pattern layer120under the same or equal conditions (for example, annealing conditions). For example, the buried insulating portion160may include silicon nitride (SiNx), silicon oxynitride (SiON), or aluminum oxide (AlOx).

In the channel layer130, a region corresponding to a source/drain may be protected from the oxygen permeation by the first and second contacts170A and170B. The first and second contacts170A and170B may include a conductive material having an oxygen diffusivity that is lower than oxygen diffusivity in the material of the second insulating pattern layer120under the same or equal conditions (for example, annealing conditions). For example, the first and second contacts170A and170B may include at least one of TiN, W, Cu, Ti, Ta, TaN, and Mo.

FIGS.5to9are cross-sectional views of semiconductor devices according to some example embodiments.

Referring toFIG.5, a semiconductor device100A according to some example embodiments may be understood to be similar to the semiconductor device100illustrated inFIGS.1to4, except that a buried insulating portion160′ may be formed of the same material as a second insulating pattern layer120. In addition, elements of some example embodiments in accordance withFIG.5may be understood with reference to the descriptions of the same or similar elements of the semiconductor device100illustrated inFIGS.1to4, unless otherwise specified.

The semiconductor device100A according to some example embodiments may include a buried insulating portion160′ having the same insulating material as the second insulating pattern layer120. For example, the buried insulating portion160′ and the second insulating pattern layer120may include at least one of a silicon oxide layer and a silicon oxynitride layer. In some example embodiments, an annealing process may be performed in an oxygen atmosphere after a channel layer130is formed and before the buried insulating portion160′ is formed (for example, seeFIGS.13A and13B). In this case, even when the buried insulating portion160′ is formed of an oxygen-containing insulating material such as silicon oxide, characteristics of the first and second gate electrodes150A and150B may be prevented from being adversely affected by annealing.

Referring toFIG.6, a semiconductor device100B according to some example embodiments may be understood to be similar to the semiconductor device100illustrated inFIGS.1to4, except that a channel layer130does not overlap a conductive line110and first and second contacts170A and170B in a horizontal direction (for example, the first direction D1). In addition, elements of some example embodiments in accordance withFIG.6may be understood with reference to the descriptions of the same or similar elements of the semiconductor device100illustrated inFIGS.1to4, unless otherwise specified.

The semiconductor device100B according to some example embodiments may introduce a configuration for improving characteristics of a channel layer130and protecting gate electrodes150A and150B by an annealing process as illustrated inFIG.2A, rather than a configuration in which the channel layer130does not overlap the conductive line110and the first and second contacts170A and170B in the horizontal direction (for example, the first direction D1). Specifically, a portion of an upper surface region of the second insulating pattern layer120may be exposed between adjacent trenches, in particular, between the first and second contacts170A and170B, so that the channel layer130may be cured by oxygen introduced through the exposed region of the second insulating pattern layer120during an annealing process to significantly improve leakage current characteristic of the channel layer130. Unlike the second insulating pattern layer120, a buried insulating portion160may be formed of an insulating material which does not contain oxygen. Thus, the first and second gate electrodes150A and150B may be protected from oxygen permeation which may occur in an annealing process after a memory cell transistor MCT is formed.

Referring toFIG.7, a semiconductor device100C according to some example embodiments may be understood to be similar to the semiconductor device100illustrated inFIG.4, except that a channel layer130′ may be provided after being separated into first and second horizontal channel elements130A and130B. In addition, elements of some example embodiments in accordance withFIG.7may be understood with reference to the descriptions of the same or similar elements of the semiconductor device100illustrated inFIGS.1to4, unless otherwise specified.

The semiconductor device100C according to some example embodiments may be configured such that the first and second horizontal channel elements130A and130B, respectively provided as channels of a unit transistor cell, may be separated from each other. Although a single channel layer130is shared in a dual transistor structure DT in the example embodiments discussed with reference toFIG.2A, the first and second horizontal channel elements130A and130B may not be connected to each other on a bottom of a trench, in a similar manner to first and second gate electrodes150A and150B. Lower regions of the first and second horizontal channel elements130A and130B may each be connected to a conductive line110. In some example embodiments, since bottoms as well as side surfaces of the lower regions of the first and second horizontal channel elements130A and130B are connected to the conductive line110, a sufficient contact area may be provided.

Referring toFIG.8, the semiconductor device100D according to some example embodiments may be understood to be similar to the semiconductor device100illustrated inFIGS.1to4, except that a trench (or a channel layer130) does not extend inwardly of a conductive line110. In addition, elements of some example embodiments in accordance withFIG.8may be understood with reference to the descriptions of the same or similar elements of the semiconductor device100illustrated inFIGS.1to4, unless otherwise specified.

In some example embodiments, first and second contacts170A and170B as drain contacts may overlap the channel layer130in a horizontal direction (for example, the first direction D1), whereas a conductive line110′ as a source contact may not overlap the channel layer130in the horizontal direction (for example, the first direction D1). Accordingly, a channel length may be reduced only by burying the first and second contacts170A and170B.

Specifically, similarly to the example embodiments discussed with reference toFIG.2A, the first and second contacts170A and170B may be buried in regions adjacent to opposite sidewalls of a trench in a second insulating pattern layer120and may connected to side surfaces of upper regions of the channel layer130and first and second horizontal channel elements130A and130B, respectively. On the other hand, the trench may be formed to extend only to an upper surface of a conductive line110′ and may not extend inwardly of the conductive line110′, and the channel layer130formed along the trench may be on an upper surface of the conductive line110′.

Referring toFIG.9, the semiconductor device100E according to some example embodiments may be understood to be similar to the semiconductor device100illustrated inFIGS.1to4, except that first and second contacts170A and170B are not buried in a second insulating pattern layer120. In addition, elements of some example embodiments in accordance withFIG.9may be understood with reference to the descriptions of the same or similar elements of the semiconductor device100illustrated inFIGS.1to4, unless otherwise specified.

In some example embodiments, a conductive line110as a source contact may overlap a channel layer130in a horizontal direction (for example, the first direction D1), whereas first and second contacts170A and170B as the drain contact may not overlap a channel layer130in the horizontal direction (for example, the first direction D1). Accordingly, unlike the example embodiment illustrated inFIG.8, a channel length may be reduced by positioning a portion of the channel layer inside (in a recessed region) of the conductive line110.

Specifically, similarly to the example embodiment illustrated inFIG.2, a trench may have an extension portion that extends inwardly of the inductive line110(also referred to as a “recess” of the conductive line110), and the channel layer130formed along the trench may be disposed in the recess of the conductive line110. The channel layer130may overlap the conductive line110in the horizontal direction (for example, the first direction D1) by a depth of the recess. On the other hand, the first and second contacts170A′ and170B′ may be arranged on (rather than within) the second insulating pattern layer120, and may be connected to upper surfaces of upper regions of the first and second horizontal channel elements130A and130B without an overlapping portion in the horizontal direction (for example, the first direction D1).

FIGS.10A to17Aare flow cross-sectional views illustrating operations of a method of fabricating a semiconductor device according to some example embodiments, andFIGS.10B to17Bare plan views of cross-sectional structures illustrated inFIGS.10A to17A, respectively.

A fabrication process according to some example embodiments may be understood to be a process of fabricating the memory cell transistor of the semiconductor device illustrated inFIG.2A, and each process cross-sectional view and each plan view illustrate regions corresponding toFIGS.4and3.

Referring toFIGS.10A and10B, a first insulating pattern layer108having a plurality of trenches that extend in a first direction D1may be formed on a substrate101, and a plurality of conductive lines110may be respectively arranged in the plurality of trenches.

The plurality of conductive lines110may extend in the first direction D1and may be arranged side by side in a second direction D2. The first insulating pattern layer108may have upper surface that is substantially coplanar with upper surfaces of the plurality of first conductive lines110. The plurality of conductive lines110may be electrically separated from the substrate101by an insulating layer105. Each of the plurality of conductive lines110may include a single conductive layer or a plurality of conductive layers. For example, in some example embodiments, the conductive lines may have a double-layer structure that includes first and second conductive layers112and115. The first conductive layer112may include tungsten (W), and the second conductive layer115may include titanium nitride (TiN). The first insulating pattern layer108may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

Referring toFIGS.11A and11B, an insulating layer120′ and a contact layer170L may be sequentially formed on the plurality of conductive lines110and the first insulating pattern layer108.

In the present process, before the trench is formed, a contact layer170L may be formed together with an insulating layer120′ for the second insulating pattern layer to provide an arrangement in which first and second contacts and a channel layer overlap each other. The insulating layer120′ may be provided as a second insulating pattern layer in a final structure. The insulating layer120′ may include an oxygen-containing insulating material to smoothly introduce oxygen for curing a channel layer (for example, an oxide semiconductor) in an annealing process. For example, the insulating layer120′ may include silicon oxide (SiO2) or silicon oxynitride (SiON).

The contact layer170L may include a conductive material having oxygen diffusivity lower than oxygen diffusivity in a material of the insulating layer120′ under the same or equal conditions (for example, annealing conditions) to prevent oxygen permeation into a contact region (for example, a drain region) of a channel layer to be formed in a subsequent process. For example, the contact layer170L may include at least one of TiN, W, Cu, Ti, Ta, TaN, and Mo. A thickness of the contact layer170L may be set to correspond to a thickness of a region in which a channel layer and a source contact (first and second contacts) overlap in the horizontal direction, or may be set to be slightly larger than the thickness of the region (in consideration of a polishing process ofFIG.15A).

Referring toFIGS.12A and12B, a plurality of trenches T may be formed in the insulating layer120′ and the contact layer170L to extend in a second direction, intersecting the first direction.

In the present process, the trench T may be formed to extend to a partial region Te of the conductive lines110. Each of the conductive lines110may have a region exposed by the trench T. A recess, corresponding to the extension portion Te of the trench T, may be formed in the exposed region of the conductive line110. As illustrated inFIG.12A, the extension portion Te of the trench T may be in the second conductive layer115of the conductive line110. Such a trench depth DT may be determined in consideration of a height of a channel layer (particularly, a horizontal channel element) to be formed in a subsequent process. For example, the trench depth DT may correspond to the height of the channel layer or may be set to be slightly larger than the height of the channel layer (in consideration of the polishing process ofFIG.15A). A depth Da of the extension portion Te of the trench T may determine a length of a portion of the conductive lines110in a horizontal direction that overlaps the channel layer (130LFIG.13A).

Referring toFIGS.13A and13B, the channel layer130L may be formed along opposite sidewalls of the trench T to be connected to the exposed region of the conductive lines110.

In some example embodiments, as illustrated inFIG.13B, the channel layer130L may be formed along adjacent cells (trenches) in a first direction and formed to be separated in units of cells in a second direction. The channel layer130L may be in the region exposed by the extension portion Te of the trench T and on opposite sidewalls of the trench T, and may extend to an upper surface of the contact layer170.

Due to the extension portion Te of the trench T, the overlapping portion of the conductive lines110and the channel layer130L may have a predetermined length Db. Similarly, the overlapping portion of the conductive lines110and the channel layer130L may have a predetermined length Da by forming a contact layer170L in advance before forming the trench T. In the final structure, the length of the overlapping portion of the contact layer170L and the channel layer130L may be slightly reduced by a polishing process.

The channel layer130L in some example embodiments may include an oxide semiconductor which may be stackable and which may have low leakage current characteristics. For example, the channel layer130L may include one of IGZO, ITZO, ITGO, IWO, ITO, ZnO, and Cu2O. In some example embodiments, the channel layer130L may include MoS2, WS2, graphene, or h-BN.

In some example embodiments, an annealing process may be performed after the formation of the channel layer. For example, the annealing process may be performed in an oxygen atmosphere and may be performed in the range of 250° C. to 400° C. (for example, 300° C. to 350° C.) for 30 minutes to 12 hours (for example, 1 hour to 3 hours), with the present disclosure not limited thereto.

Referring toFIGS.14A and14B, a gate insulating layer140L and a gate electrode layer150L may be sequentially formed on internal sidewalls of the trench to cover the channel layer130L.

In the present process, the gate insulating layer140L and the gate electrode layer150L may be formed conformally in sequence. After the gate insulating layer140may be formed in the trench along the channel layer130, the gate electrode layer150L may also be formed in the trench along the gate insulating layer140. For example, the gate insulating layer140L may include a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer having a higher dielectric constant than the silicon oxide layer, or combinations thereof. The high-k film may include, but is not limited to, HfO2, HfSiO, HfSiON, HfTaO, HfSiO, HfZrO, ZrO2, Al2O3, or combinations thereof. The gate electrode layer150L may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, and/or a combination thereof. For example, the gate electrode layer150L may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN., TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, and/or a combination thereof, but the present disclosure and example embodiments thereof are not limited thereto.

Referring toFIGS.15A and15B, a portion of the gate electrode layer150L may be removed to form first and second gate electrodes150A and150B, and a buried insulating layer160L may be formed in the trench T.

The first and second gate electrodes150A and150B may be formed by performing a selective anisotropic etching process on the gate electrode layer150L. The selective etching of the gate electrode layer150L may be anisotropically performed to remove the other portions while allowing a portion on the internal sidewall of the trench T, to remain. Thus, the first and second gate electrodes150A and150B may be formed.

Next, a buried insulating portion160L may be formed to fill a space between the first and second gate electrodes150A and150B in the trench T. In some example embodiments, the buried insulating layer160L may be formed of a material that is different from the material of the second insulating pattern layer120′, provided as an oxygen permeation path, to protect the first and second gate electrodes150A and150B from oxygen permeation. In some example embodiments, the buried insulating layer160L may include an insulating material having an oxygen diffusivity that is lower than an oxygen diffusivity in the material of the second insulating pattern layer120′ under the same or equal conditions (for example, annealing conditions). For example, the buried insulating layer160L may include silicon nitride (SiNx), silicon oxynitride (SiON), or aluminum oxide (AlOx).

Referring toFIGS.16A and16B, a planarization process may be performed to expose an upper surface of the contact layer170L.

Through the planarization process, a structure having two unit transistor cells facing each other may be formed in the trench T. The buried insulating portion160may extend in a first direction D1to fill all or a portion of a remaining space in the trench T along a space between the first and second gate electrodes150A and150B (FIG. see3). Due to the planarization process, the buried insulating portion160may have an upper surface that is substantially coplanar with an upper end of the channel layer130, and the upper surface of the buried insulating portion160may be substantially coplanar with upper ends of the gate insulating layer140and the first and second gate electrodes150A and150B.

Referring toFIGS.17A and17B, the contact layer170L may be patterned to form first and second contacts170A and170B, and the insulating portion120F may fill a region in which the contact layer170L is removed.

A portion of the contact layer170L between the trenches T, may be removed to form the first and second contacts170A and170B in the same pattern as illustrated inFIG.17B. In some example embodiments, the first and second contacts170A and170B may be patterned to have substantially the same width as the channel layer130in a width direction.

In the present process, a partial region of the second insulating pattern layer120′ may be exposed through the region in which the contact layer170L is removed, for example, through a space between the first and second contacts170A and170B or a space between contacts170A and170B adjacent to each other in the first direction. Additionally, the region in which the contact layer170L is removed may be filled with an insulating portion120F to be planarized, so that a final second insulating pattern layer120may be completed. The insulating portion120F for filling may include the same material as the second insulating pattern layer120′.

As described above, after the memory cell transistor MCT is formed, an annealing process for the channel layer may be performed. The annealing process may be performed in combination with or instead of the previous annealing process, and may be performed under conditions similar to the above-described annealing conditions.

In such an annealing process, an exposed upper surface region of the second insulating pattern layer120(for example, the insulating portion120F for filling) may be provided as a path through which oxygen is introduced and then reaches the channel layer130to improve characteristics of the channel layer130. Such an annealing process may be performed alone or additionally after forming the data storage element DS as illustrated inFIGS.2A and2B.

FIG.18is a cross-sectional view of a semiconductor device according to some example embodiments, andFIG.19is a cross-sectional view illustrating a process of forming the semiconductor device ofFIG.18.

Referring toFIG.18, a semiconductor device100F according to some example embodiments may be understood to be similar to the semiconductor device100illustrated inFIGS.1to4, except that a buried insulating layer160has a void V therein. In addition, elements of some example embodiments in accordance withFIG.18may be understood with reference to the descriptions of the same or similar elements of the semiconductor device100illustrated inFIGS.1to4, unless otherwise specified.

The semiconductor device100F according to some exemplary embodiments may include a buried insulating portion having a void therein. The buried insulating portion160may include an insulating material having a relatively low oxygen diffusivity to protect first and second gate electrodes150A and150B from oxygen permeation. For example, the buried insulating portion160may include silicon nitride (SiNx), silicon oxynitride (SiON), or aluminum oxide (AlOx). In some example embodiments, a void V may be formed in the buried insulating portion160to prevent oxidation of the first and second gate electrodes150A and150B and to reduce coupling between the first and second gate electrodes150A and150B.

The void V may be formed during formation of an insulating material for the buried insulating portion160. As illustrated inFIG.19, a desired void V may be formed by performing a deposition process of an insulating material under a condition in which a space between the first and second gate electrodes150A and150B is insufficiently filled, that is, to rapidly merge an insulating material deposited in an entrance portion of the space.

As described above, some example embodiments provide semiconductor devices having components, such as vertical channel transistors (VCT), which may secure ON-current characteristics even a channel layer having relatively low mobility is employed.