Nonvolatile memory device having stacked transistor configuration

A nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks, an address decoder that selects one of the memory blocks in response to an input address and generates a first control signal and a second control signal, a plurality of metal lines connected with the memory blocks and extending along a first direction, a plurality of pass transistors that connect the address decoder with a first subset of the metal lines connected with the selected memory block in response to the first control signal, and a plurality of ground transistors that supply a low voltage to a second subset of the metal lines connected with unselected memory blocks in response to the second control signal. The ground transistors have channels that extend along a second direction perpendicular to the first direction.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C §119 to Korean Patent Application No. 10-2010-0123794 filed on Dec. 6, 2010, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

Embodiments of the inventive concept relate generally to electronic memory technologies. More particularly, embodiments of the inventive concept relate to nonvolatile memory devices and related transistor configurations.

Semiconductor memory devices are fabricated using semiconductor materials such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Semiconductor memory devices can be roughly divided into two categories according to whether they retain stored data when disconnected from power. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory devices, which retain stored data when disconnected from power. Examples of volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM), and examples of nonvolatile memory devices include read only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable and programmable ROM (EEPROM), a flash memory device, a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), and a ferroelectric RAM (FRAM).

In an effort to improve the integration density of nonvolatile memory devices, researchers have recently developed nonvolatile memory devices in which memory cells are arranged in a three-dimensional array. One challenge in developing these devices is to ensure their structural integrity. For example, where features are stacked on top of each other in a three-dimensional array, some of the features may be formed on air gaps or spaces, which can weaken their structure.

SUMMARY OF THE INVENTION

According to one embodiment of the inventive concept, a nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks, an address decoder configured to select one of the memory blocks in response to an input address and to generate a first control signal and a second control signal, a plurality of metal lines connected with the memory blocks and extending along a first direction, a plurality of pass transistors configured to connect the address decoder with a first subset of the metal lines connected with the selected memory block in response to the first control signal, and a plurality of ground transistors configured to supply a low voltage to a second subset of the metal lines connected with unselected memory blocks in response to the second control signal. The ground transistors have channels that extend along a second direction perpendicular to the first direction.

According to another embodiment of the inventive concept, a nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks, an address decoder configured to select one of the plurality of memory blocks in response to an input address and to generate a first control signal and a second control signal, a plurality of first metal lines connected with a plurality of string selection transistors corresponding to the plurality of memory blocks and extending along a first direction, a plurality of second metal lines connected with a plurality of memory cell transistors of each of the plurality of memory blocks, a plurality of pass transistors configured to connect the address decoder with a subset of the first and second metal lines corresponding to the selected memory block in response to the first control signal, and a plurality of ground transistors configured to connect a low voltage node with a subset of the first metal lines connected to unselected memory blocks. The ground transistors have channels that extend along a second direction perpendicular to the first direction.

According to another embodiment of the inventive concept, a nonvolatile memory device comprises a memory cell array comprising a plurality of memory blocks, a plurality of metal lines connected with the memory blocks and extending along a first direction, a plurality of pass transistors configured to supply a first voltage to a first subset of the metal lines connected with a selected memory block in response to a first control signal, and a plurality of ground transistors configured to supply a second voltage to a second subset of the metal lines connected with unselected memory blocks in response to a second control signal. The ground transistors have channels that extend along a second direction perpendicular to the first direction.

These and other embodiments of the inventive concept can improve the structural integrity of ground transistors in stacked nonvolatile memory devices. This in turn can improve the reliability of the stacked nonvolatile memory devices.

DETAILED DESCRIPTION

Embodiments of the inventive concept are described below with reference to the accompanying drawings. These embodiments are presented as teaching examples and should not be construed to limit the scope of the inventive concept.

In the description that follows, the terms first, second, third, etc., are used to describe various features, but these features should not be limited by these terms. Rather, these terms are used merely to distinguish between different features. Accordingly, a first feature discussed below could be termed a second feature without changing the meaning of the described features.

Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper”, are used herein for ease of description to indicate one feature's relationship to another feature as illustrated in the drawings. These spatially relative terms are intended to encompass different orientations of the described features in use or operation in addition to the orientation depicted in the figures. For example, if a device shown in one of the figures is turned over, features described as “below” or “beneath” or “under” other features would then be oriented “above” the other elements or features. Thus, the terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. In addition, where a feature is referred to as being “between” two features, it can be the only feature between the two features, or one or more intervening features may also be present.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the inventive concept. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises” and/or “comprising,” when used in this specification, indicate the presence of stated features, but they do not preclude the presence or addition of one or more other features. As used herein, the term “and/or” indicates any and all combinations of one or more of the associated listed items.

Where a feature is referred to as being “on”, “connected to”, “coupled to”, or “adjacent to” another feature, it can be directly on, connected, coupled, or adjacent to the other feature, or intervening features may be present. In contrast, where a feature is referred to as being “directly on,” “directly connected to”, “directly coupled to”, or “immediately adjacent to” another feature, there are no intervening features present.

FIG. 1is a block diagram of a nonvolatile memory device100according to an embodiment of the inventive concept.

Referring toFIG. 1, nonvolatile memory device100comprises a memory cell array110, a block gating unit120, an address decoder130, a read/write circuit140, and control logic150.

Memory cell array110comprises a plurality of memory blocks each having a plurality of memory cells arranged along row and column directions on a substrate. The memory cells are arranged in cell strings, where each cell string comprises multiple memory cells stacked along a direction perpendicular to the substrate. In other words, the memory cells are arranged on the substrate along rows and columns, and they are stacked along a direction perpendicular to the substrate to form a three-dimensional structure. The memory cells of memory cell array110can be configured to store one or more bits of data per memory cell.

Block gating unit120is coupled to memory cell array110via string selection lines SSL, word lines WL, and ground selection lines GSL. Block gating unit120is coupled to address decoder130via string lines SS, selection lines S, and ground lines GS.

Block gating unit120receives a block selection signal BSS from address decoder130and selects a memory block of memory cell array110in response to block selection signal BSS. Block gating unit120connects string selection lines SSL, word lines WL, and ground selection lines GSL of the selected memory block with string lines SS, selection lines S, and ground lines GS.

Address decoder130is coupled with block gating unit120via string lines SS, selection lines S, and ground lines GS. Address decoder130operates under the control of control logic150. Address decoder130receives an address ADDR from an external device, decodes a row address from address ADDR, and outputs block selection signal BSS based on the decoded row address. Address decoder130selects one of selection lines S corresponding to the decoded row address and selects a string line and a ground line corresponding to the decoded row address. The selected string line and the selected ground line are selected from among string lines SS and ground lines GS.

Address decoder130decodes a column address of address ADDR to produce a decoded column address DCA, and it transmits decoded column address DCA to read/write circuit140. Address decoder130typically comprises a row decoder configured to decode a row address, a column decoder configured to decode a column address, and an address buffer configured to store address ADDR.

Read/write circuit140is connected to memory cell array110via bit lines BL. Read/write circuit140is configured to exchange data with an external device, and it operates under the control of control logic150. Read/write circuit140receives decoded column address DCA from address decoder120, and it selects bit lines in response to the decoded column address DCA.

Read/write circuit140can perform various types of memory access operations. For example, it can perform a write operation to write data received from an external device in memory cell array110, perform a read operation to read data from memory cell array110and output it to an external device, or perform a copy-back operation to read data from a first storage region of the memory cell array and write it in a second storage region.

Read/write circuit140typically comprises features such as a page buffer (or, a page register), a column selector circuit, or a data buffer. Read/write circuit140can also comprise other features, such as a sense amplifier, a write driver, a column selector circuit, or a data buffer.

Control logic150is coupled with address decoder130and read/write circuit140, and it controls overall operations of nonvolatile memory device100.

FIG. 2is a block diagram illustrating memory cell array110and block gating unit120ofFIG. 1according to an embodiment of the inventive concept.

Referring toFIG. 2, memory cell array110comprises a plurality of memory blocks BLK1through BLKz each connected with block gating unit120via one of string selection lines SSL, one of word lines WL, and one of ground selection lines GSL.

Block gating unit120comprises a plurality of gating circuits121through12zeach corresponding to one of memory blocks BLK1through BLKz. Each of gating circuits121through12zcomprises a ground circuit GCi (i=1 through z) and a pass circuit PCi.

A pass circuit PCi corresponding to the selected memory block responds to block selection signal BSS to connect a selected string selection line SSL, a selected word line WL, and a selected ground selection line GSL with a corresponding string line SS, selection line S, and ground line GS, respectively. A ground circuit GCi supplies a low voltage (e.g., a ground voltage VSS) to string selection lines SSL and ground selection lines of unselected memory blocks.

FIG. 3is a perspective view of memory cell array110and block gating unit120ofFIG. 1according to an embodiment of the inventive concept.

Referring toFIG. 3, memory cell array110has a three-dimensional structure, also referred to as a vertical structure. In this structure memory blocks BLK1through BLKz are stacked along a second direction and are formed in a plane extending along first and third directions. Block gating unit120has a plane structure and is formed in a plane extending in the first and third directions.

Memory cell array110and block gating unit120are interconnected via a metal layer ML formed over memory cell array110and block gating unit120. Memory cell array110is connected with metal layer ML via contact plugs CP, and block gating unit120is connected with metal layer ML via contact plugs CP. In various alternative embodiments, the locations of contact plugs CP can be changed from those shown inFIG. 3.

FIG. 4is a plane view of one of memory blocks BLK1through BLKz ofFIGS. 2 and 3according to an embodiment of the inventive concept. In particular,FIG. 4shows a plane view of conductive layers of a memory block BLKa.FIG. 5is a perspective view taken along a line I-I′ inFIG. 4, andFIG. 6is a cross-sectional view taken along a line I-I′ inFIG. 4.

Referring toFIGS. 4 through 6, memory block BLKa comprises three-dimensional structures extending along the first through third directions and formed on a substrate111. Substrate111forms a well having a first conductivity type, such as a p-well doped with a Group III element such as boron. Substrate111can be a pocket p-well provided within an n-well. Below, it is assumed that substrate111is a p-well (or, a pocket p-well). However, substrate111is not limited to p-type.

Substrate111further comprises a plurality of doping regions311through313extending along the first direction. Doping regions311through313are spaced apart from one another along the third direction. These doping regions are referred to as first doping region311, second doping region312, and third doping region313.

First through third doping regions311through313have a second conductivity type that differs from the conductivity type of substrate111. For example, first through third doping region311through313can be n-type conductivity regions. First through third doping region311through313are n-type conductivity regions. However, first through third doping regions311through313are not limited to n-type.

A plurality of insulation materials112and112aare provided sequentially on substrate111along the second direction between adjacent regions of first through third doping region311through313. Insulation materials112and112aare spaced apart along the second direction, and they extend along the first direction. Insulation materials112and112aare typically formed of an insulation material such as a semiconductor oxide film. A portion of insulation material112acontacting substrate111is thinner than other portions of insulation materials112.

Between two adjacent regions of first through third doping region311through313, a plurality of pillars PL11, PL12, PL21, and PL22are arranged sequentially along the first direction to penetrate insulation materials112and112aalong the second direction. Pillars PL11, PL12, PL21, and PL22contact substrate111through insulation materials112and112a. Pillars PL11, PL12, PL21, and PL22are formed with a multi-layer structure comprising a channel film114and an inner material115within channel film114.

Channel films114comprise a semiconductor material (e.g., silicon) having a first conductivity type. For example, channel films114can comprise a semiconductor material of the same type as substrate111. In the description that follows, it is assumed that channel films114comprise p-type silicon. However, channel films114are not limited to p-type silicon, and they could be formed of other materials, such as a nonconductive intrinsic semiconductor. Inner materials115are formed of an insulating material such as silicon oxide or an air gap.

Between two adjacent regions of first through third doping region311through313, information storage films116are provided on exposed surfaces of insulation materials112and112aand pillars PL11, PL12, PL21, and PL22. A thickness of information storage films116is less than a distance between insulation films112and112a.

Conductive materials CM1through CM8are provided on exposed surfaces of information storage films116between two adjacent regions of first through third doping region311through313. Conductive materials CM1through CM8extend along the first direction, and they can be provided between information storage film provided at a lower surface of an upper-layer insulation material and an information storage film provided at an upper surface of a lower-layer insulation material.

Conductive materials CM1through CM8and insulation materials112and112aon first through third doping region311through313are separated by word line cuts (labeled “WL Cut”). Conductive materials CM1through CM8can comprise a metallic conductive material or a nonmetallic conductive material such as polysilicon.

Information storage films116formed on an upper surface of an insulation material placed at the uppermost layer among insulation materials112and112acan be removed. For example, information storage films provided at sides opposite to pillars PL11, PL12, PL21, and PL22among sides of insulation materials112and112acan be removed.

A plurality of drains320are formed on pillars PL11, PL12, PL21, and PL22. Drains320are typically formed of a semiconductor material (e.g., silicon) having the second conductivity type. For example, drains320can be formed of an n-type semiconductor material, such as n-type silicon. In the description that follows, it is assumed that drains320are formed of n-type silicon. However, they can be extended to the upside of channel films114of pillars PL11, PL12, PL21, and PL22.

Bit lines BL extending in the third direction are provided on drains320. These bit lines BL are spaced apart in the first direction, and they are coupled with drains320. In addition, drains320and bit lines BL can be connected via contact plugs (not shown). Bit lines BL can be formed of a metallic conductive material or a nonmetallic conductive material such as polysilicon.

Rows and columns of pillars PL11, PL12, PL21, and PL22can be defined by the separation of conductive materials CM1through CM8. InFIGS. 4 through 6, conductive materials CM1through CM8are separated by second doping region312.

Pillars PL11and PL12, which are coupled with conductive materials CM1through CM8between first and second doping regions311and312information storage films116, are defined as a first row of pillars, and pillars PL21and PL22, which are coupled with conductive materials CM1through CM8between the second and third doping regions312and313via information storage films116, are defined as a second row of pillars.

Columns of pillars PL11, PL12, PL21, and PL22are defined according to bit lines BL1and BL2. Pillars PL11and PL21connected with first bit line BL1via drains320are be defined as a first column. Pillars PL12and PL22connected with second bit line BL1via drains320may be defined as a second column.

Conductive materials CM1through CM8have first through eighth heights according to their distances from substrate111. First conductive material CM1closest to substrate111has the first height, and eighth conductive material CM8closest to a bit line has the eighth height.

Pillars PL11, PL12, PL21, and PL22form a plurality of cell strings together with information storage films116and conductive materials CM1through CM8. That is, each of pillars PL11, PL12, PL21, and PL22forms a cell string with one of information storage films116and an adjacent one of conductive materials CM1through CM8. Each cell string comprises a plurality of cell transistors CT stacked in a direction perpendicular to substrate111. Examples of cell transistors CT are more fully described with reference toFIG. 7.

FIG. 7is a diagram illustrating one of cell transistors CT inFIG. 6according to an embodiment of the inventive concept. In the embodiment ofFIG. 7, the cell transistor has the fifth height corresponding to pillar PL11of the first row and the first column.

Referring toFIGS. 4 through 7, cell transistors CT are formed of fifth conductive material CM5, a portion of a pillar PL11adjacent to fifth conductive material CM5, and information storage films116between fifth conductive material CM5and pillar PL11.

Information storage films116extend to upper surfaces and lower surfaces of conductive materials CM1through CM8from regions between conductive materials CM1through CM8and pillars PL11, PL12, PL21, and PL22. Each of information storage films116comprises first through third sub insulation films117,118, and119.

In cell transistors CT, channel films114of pillars PL11, PL12, PL21, and PL22are formed of the same type of p-type silicon as substrate111. Channel films114act as bodies of cell transistors CT. Channel films114are formed in a direction perpendicular to substrate111. Channel films114of pillars PL11, PL12, PL21, and PL22act as a vertical body. Vertical channels are formed in channel films114.

First sub insulation films117adjacent to pillars PL11, PL12, PL21, and PL22act as tunneling insulation films of cell transistors CT. For example, first sub insulation films117adjacent to pillars PL11, PL12, PL21, and PL22can comprise a thermal oxide film, such as a silicon oxide film.

Second sub insulation films118function as charge storage films of cell transistors CT. For example, second sub insulation films118can function as charge trap films formed of a nitride film or a metal oxide film such as an aluminum oxide film or a hafnium oxide film. Second sub insulation films118are formed of a silicon nitride film.

Third sub insulation films119adjacent to conductive materials CM1through CM8act as blocking insulation films of cell transistors CT. Moreover, third sub insulation films119can be formed of a single layer or multiple layers. Third sub insulation films119typically comprise high dielectric films (e.g., aluminum oxide films or hafnium oxide films) having a dielectric constant larger than first and second sub insulation films117and118. For example, third sub insulation films119can comprise silicon oxide films. Moreover, in some embodiments, first through third sub insulation films117through119can form an oxide-nitride-oxide (ONO) structure.

Conductive materials CM1through CM8act as gates, such as control gates, third sub insulation films119act as block insulation films, second sub insulation films118act as charge storage films, first sub insulation films117act as tunneling insulation films, and channel films114act as vertical bodies. Collectively, these features operate as cell transistors CT stacked in a direction perpendicular to substrate111. In this example, cell transistors CT are charge trap type cell transistors.

Cell transistors CT can be used for different purposes according to their respective heights. For example, among cell transistors CT, at least one cell transistor placed at an upper portion can be used as a string selection transistor, and at least one cell transistor placed at a lower portion is used as a ground selection transistor. Remaining cell transistors between cell transistors used as string and ground selection transistors can be used as memory cells and dummy memory cells.

Conductive materials CM1through CM8extend along a row direction (or, the first direction) to be connected with pillars PL11and PL12or PL21and PL22. Conductive materials CM1through CM8constitute conductive lines interconnecting cell transistors CT of the same row of pillars PL11and PL12or PL21and PL22. Conductive materials CM1through CM8can also be used as string selection lines SSL, ground selection lines GSL, word lines WL, and dummy words line DWL according to their respective heights.

FIG. 8is a circuit diagram of a memory block according to an embodiment of the inventive concept.

Referring toFIGS. 4 through 8, cell strings CS11and CS21are connected between first bit line BL1and a common source line CSL, and cell strings CS12and CS22are connected between second bit line BL2and common source line CSL. Cell strings CS11, CS21, CS12, and CS22correspond to pillars PL11, PL21, PL12, and PL22, respectively.

Pillar PL11of the first row and the first column constitutes a cell string CS11of the first row and the first column with conductive materials CM1and CM8and information storage films116. Pillar PL12of the first row and the second column constitutes a cell string CS12of the first row and the second column with conductive materials CM1and CM8and information storage films116. Pillar PL21of the second row and the first column constitutes a cell string CS21of the second row and the first column with conductive materials CM1and CM8and information storage films116. Pillar PL21of the second row and the second column constitutes a cell string CS22of the second row and the second column with conductive materials CM1and CM8and information storage films116.

In cell strings CS11, CS21, CS12, and CS22, cell transistors having the first height act as ground selection transistors GST. Cell strings of the same row can share a ground selection line GSL, and cell strings in different rows can share ground selection line GSL. Ground selection line GSL can be formed by interconnecting first conductive materials CM1.

In cell strings CS11, CS21, CS12, and CS22, cell transistors having the second through sixth heights act as first through sixth memory cells MC1through MC6. First through sixth memory cells MC1through MC6are connected with first through sixth word lines WL1through WL6, respectively. Memory cells having the same height share a word line, whether they are in the same row or different rows.

First word line WL1is formed by connecting second conductive materials CM2in common, second word line WL2is formed by connecting the third conductive materials CM3in common, third word line WL3is formed by connecting fourth conductive materials CM4in common, fourth word line WL4is formed by connecting fifth conductive materials CM5in common, fifth word line WL5is formed by connecting sixth conductive materials CM6in common, and sixth word line WL6is formed by connecting seventh conductive materials CM7in common.

In cell strings CS11, CS21, CS12, and CS22, cell transistors having the eighth height act as string selection transistors SST. String selection transistors SST are connected with first and second string selection lines SSL1and SSL2, respectively. Cell strings in the same row share a string selection line, and cell strings in different rows are connected with different selection lines SSL1and SSL2. Pillars PL11, PL12, PL21, and PL22, which correspond to rows of cell strings CS11, CS12, CS21, and CS22, are defined by first and second string selection lines SSL1and SSL2.

Common source line CSL is connected in common with cell strings CS11, CS12, CS21, and CS22. For example, common source line CSL is formed by interconnecting first through third doping regions311through313(SeeFIGS. 4 through 6).

As described above, string selection lines SSL1and SSL2, word lines WL1through WL6, and ground selection line GSL in a selected memory block are connected with address decoder130via a pass circuit of block gating unit120corresponding to the selected memory block. Address decoder130selects string selection lines SSL1and SSL2, word lines WL1through WL6, and ground selection line GSL of the selected memory block.

Memory cells at the same height are connected in common with one word line. Accordingly, where a word line at a specific height is selected, all cell strings CS11, CS12, CS21, and CS22connected with the selected word line are selected.

Cell strings in different rows are connected with different string selection lines. Cell strings CS11and CS12or CS21and CS22in an unselected row among cell strings CS11, CS12, CS21, and CS22connected with the same word line may be separated from bit lines BL1and BL2by selecting and unselecting the first and second string selection lines SSL1and SSL2. Cell strings CS21and CS22or CS11and CS12in a selected row are electrically connected with bit lines BL1and BL2.

That is, rows of cell strings CS11, CS12, CS21, and CS22are selected by selecting and unselecting first and second string selection lines SSL1and SSL2. Columns of cell strings in a selected row can be selected by selecting the bit lines BL1and BL2.

String selection lines SSL1and SSL2, word lines WL1through WL6, and ground selection line GSL in unselected memory blocks are electrically separated from address decoder130via pass circuits of block gating unit120corresponding to the unselected memory blocks. Ground circuits of block gating unit120corresponding to the unselected memory blocks supply a low voltage (e.g., ground voltage VSS) to string selection lines SSL1and SSL2and ground selection line GSL in each of the unselected memory blocks. With these bias conditions, string and ground selection transistors SST and GST in the unselected memory blocks are turned off so as to be electrically separated from bit lines BL1and BL2and common source line CSL.

InFIGS. 4 through 8, memory blocks BLKa and BLKa1comprise 2×2 cell strings each having first through eighth heights. However, the heights of these strings can be made proportional to the number of cell strings. Moreover, in some embodiments, memory block BLKa and BLKa1are designed with first through eighth heights, where each of them comprises 8×8 cell strings. In such embodiments, these memory blocks can be connected with eight string selection lines and one ground selection line. Similarly, in some embodiments, memory block BLKa and BLKa1are designed with first through sixteenth heights, where each of them comprises 8×8 cell strings. In such embodiments, these memory blocks can be connected with sixteen string selection lines and one ground selection line.

In the description that follows, it will be assumed that memory block BLKa or BLKa1is connected with “n” string selection lines and one ground selection line. Further, it is assumed that memory block BLKa or BLKa1is connected with “m” word lines.

FIG. 9is a circuit diagram illustrating one of gating circuits121through12zshown inFIG. 2according to an embodiment of the inventive concept.

Referring toFIG. 9, a gating circuit12kcomprises a pass circuit PCk and a ground circuit GCk. Pass circuit PCk comprises a plurality of pass transistors. In response to a first block selection line BSS1, the pass transistors connect string selection lines SSL1through SSLn, word lines WL1through WLm, and a ground selection line GSL with string lines SS1through SSn, selection lines S1through Sm, and a ground line GS, respectively. The pass transistors can be formed of high-voltage transistors, for example.

Ground circuit GCk comprises a plurality of ground transistors that supply a low voltage to string selection lines SSL1through SSLn and ground line GSL in response to second block selection signal BSS2. The low voltage supplied by the ground transistors can be ground voltage VSS, for example.

The activated first block selection signal BSS1is supplied to a pass circuit corresponding to a selected one of memory blocks BLK1through BLKz. The activated second block selection signal BSS2is supplied to ground circuits each corresponding to unselected ones of memory blocks BLK1through BLKz. Under these bias conditions, string selection lines SSL1through SSLn, word line WL1through WLm, and ground selection line GSL of the selected block are coupled with address decoder130, while string selection lines SSL1through SSLn and ground selection line GSL of unselected memory blocks are grounded. At this time, word lines WL1through WLm of the unselected memory blocks are floated. The unselected memory blocks are separated from bit lines BL and a common source line CSL.

FIG. 10is a plane view of ground transistors in ground circuit GCk according to an embodiment of the inventive concept, andFIG. 11is a cross-sectional view taken along a line II-II′ inFIG. 10.

Referring toFIGS. 9 through 11, a plurality of ground transistor pairs GTP each comprise first and second gate patterns G1and G2, first and second active regions A1and A2each formed beside one of first and second gate patterns G1and G2, and a common active region CA formed between first and second gate patterns G1and G2.

First active region A1, common active region CA, and first gate pattern G1form one ground transistor of a ground transistor pair GTP, and second active region A2, common active region CA, and second gate pattern G2form another ground transistor of the ground transistor pair GTP.

First active region A1is connected with one of first metal lines S1M0through S8M0via a contact plug CP, and second active region A2is connected with another one of first metal lines S1M0through S8M0via a contact plug CP. First metal lines S1M0through S8M0are formed from metal layer ML described inFIG. 3. First metal lines S1M0through S8M0extend in the first direction on a memory block BLKk. As illustrated inFIG. 3, first metal lines S1M0through S8M0are connected with conductive materials CM1through CM8of memory block BLKk via contact plugs CP, respectively. That is, ground transistor pairs GTP are connected with memory block BLKk via first metal lines S1M0through S8M0. First metal lines S1M0through S8M0form string selection lines SSL1through SSLn and ground selection line GSL.

Common active region CA is connected with one of second metal lines G1M1and G2M1via a contact plug CP. Second metal lines G1M1and G2M1are formed from metal layer ML described inFIG. 3. Second metal lines G1M1and G2M1are formed over first metal lines S1M0through S8M0. Second metal lines G1M1and G2M1are interconnected, and a ground voltage is applied to second metal lines G1M1and G2M1.

The ground transistors ofFIG. 10comprise channels formed in a direction parallel with first metal lines S1M0through S8M0constituting string selection lines SSL1through SSLn and ground selection line GSL. Second metal lines G1M1and G2M1are disposed over ground transistor pairs GTP. First metal lines S1M0through S8M0are disposed among ground transistor pairs GTP.

In some embodiments, four ground transistor pairs GTP for supplying a ground voltage to eight first metal lines S1M0through S8M0occupy an area defined by a first length L1in the first direction and a second length L2in the third direction.

FIG. 12is a plane view of ground transistors according to an embodiment of the inventive concept.

Referring toFIGS. 9 and 12, first metal lines S1M0through S8M0are formed along the first direction. First metal lines S1M0through S8M0are formed of metal layer ML. First metal lines S1M0through S8M0form string selection lines SSL1and SSL2and a ground selection line GSL of memory block BLKk.

Second metal lines G1M1and G2M1are formed along the first direction. Second metal lines G1M1and G2M1are formed of metal layer ML. Second metal lines G1M1and G2M1are formed over first metal lines S1M0through S8M0. A ground voltage is applied to second metal lines G1M1and G2M1.

Ground transistor pairs GTP comprise channels that extend along a direction perpendicular to first and second metal lines S1M0through S8M0and G1M1and G2M1. Where the channels of ground transistor pairs GTP are perpendicular to first metal lines S1M0through S8M0, first metal lines S1M0through S8M0are disposed over ground transistor pairs GTP. Because a space is not required to dispose first metal lines S1M0through S8M0, the integrity of the ground transistors is improved.

In some embodiments, four ground transistor pairs GTP for supplying a ground voltage to eight first metal lines S1M0through S8M0occupy an area defined by third length L3in the first direction and first length L1in the third direction. Third length L3is shorter than second length L2described inFIGS. 10 and 11.

FIG. 13is a plane view of ground transistors according to an embodiment of the inventive concept. This embodiment differs from the embodiment ofFIG. 12in that first and second gate patterns G1and G2extend along the first direction and are interconnected.

A plurality of first active regions A1are formed at one end of first and second gate patterns G1and G2, a plurality of second active regions A2are formed at other ends thereof, and common active regions CA are formed between first gate patterns G1and G2. First and second gate patterns G1and G2, first and second active regions CA, and common active regions CA form a plurality of ground transistors. In these ground transistors, a space is not required to separate gate patterns G1and G2. Accordingly, the integrity of the ground transistors is improved.

In some embodiments, four ground transistor pairs GTP for supplying a ground voltage to eight first metal lines S1M0through S8M0occupy an area defined by a fourth length L4in the first direction and first length L1in the third direction. Fourth length L4is shorter than third length L3described inFIG. 12.

FIG. 14is a block diagram of memory cell array110and block gating unit120ofFIG. 1according to an embodiment of the inventive concept. InFIG. 14, memory cell array110is labeled110a, and block gating unit120is labeled120a.

Referring toFIG. 14, memory cell array110acomprises a plurality of memory blocks BLK1through BLKz each connected with a plurality of string selection lines SSL, a plurality of word lines WL, and a plurality of ground selection lines GSL.

Block gating unit120acomprises ground circuits GC1through GCz and pass circuits PC1through PCz. Ground circuits GC1through GCz correspond to memory blocks BLK1through BLKz, respectively, and pass circuits PC1through PCz correspond to memory blocks BLK1through BLKz, respectively. Each of pass circuits PC1through PCz is connected with a corresponding memory block via string selection lines SSL, word lines WL, and ground selection lines GSL. Each of ground circuits GC1through GCz is connected with a corresponding memory block via string selection lines SSL and ground selection lines GSL.

FIG. 15is a circuit diagram of a memory block according to an embodiment of the inventive concept. The memory block ofFIG. 15is similar to that ofFIG. 8except that it further comprises a plurality of ground selection lines GSL.

FIG. 16is a circuit diagram of one of gating circuits121and12zshown inFIG. 14according to an embodiment of the inventive concept.

Referring toFIG. 16, a gating circuit12kcomprises a pass circuit PCk′ and a ground circuit GCk′. Pass circuit PCk′ comprises a plurality of pass transistors. The pass transistors connect string selection lines SSL1through SSLn, word lines WL1through WLm, and ground selection lines GSL1through GSLn with address decoder130in response to first block selection signal BSS1.

Ground circuit GCk′ comprises a plurality of ground transistors. The ground transistors supply ground voltage VSS to string selection lines SSL1through SSLn and ground selection lines GSL1through GSLn in response to second block selection signal BSS2. The ground transistors can be formed as described in any ofFIGS. 10 through 13.

FIG. 17is a block diagram of memory cell array110and block gating unit120ofFIG. 1according to an embodiment of the inventive concept. InFIG. 17, memory cell array110is labeled110b, and block gating unit120is labeled120b.

Referring toFIG. 17, memory cell array110bcomprises a plurality of memory blocks BLK1through BLKz arranged in two groups. In alternative embodiments, they can be arranged in different numbers of groups.

Block gating unit120bcomprises a plurality of gating circuits121and122. In some embodiments, the number of gating circuits is identical to the number of groups of memory blocks. Gating circuits121and122are used to select or unselect the groups of memory blocks.

Gating circuits121and122connect string selection lines SSL, word lines WL, and ground selection lines GSL of a selected memory block group with address decoder130in response to block selection signal BSS. Gating circuits121and122supply ground voltage VSS to string selection lines SSL and ground selection lines GSL of an unselected memory block group.

FIG. 18is a plane view of a block gating unit according to an embodiment of the inventive concept.

Referring toFIG. 18, the block gating unit comprises a p-type substrate PSUB, an n-type well NW, and a p-type pocket well PPW.

A first transistor T1and a pass transistors PT are formed on pocket p-well PPW, and second transistors T2and ground transistors GT are formed on substrate PSUB. First and second transistors T1and T2are elements constituting block gating unit120. For example, first and second transistors T1and T2can constitute logic gates of block gating unit120.

Substrate PSUB and the pocket p-well PPW can be biased differently. For example, substrate PSUB can be biased by ground voltage VSS, and pocket p-well PPW can be biased by a negative voltage.

In some embodiments, first metal lines S1M0through S8M0(seeFIG. 13) forming string selection lines SSL and ground selection lines GSL extend along the first direction to be connected with pass transistors PT. First metal lines S1M0through S8M0further extend along the first direction to be connected with ground transistors GT.

FIG. 19is a plane view of a block gating unit according to an embodiment of the inventive concept.

Referring toFIG. 19, the block gating unit comprises second transistor T2formed on a substrate PSUB. First transistors T1, pass transistors PT, and ground transistors GC are formed on pocket p-well PPW.

Substrate PSUB and pocket p-well PPW are biased differently. For example, substrate PSUB is biased by ground voltage VSS, and pocket p-well PPW is biased by a negative voltage.

In some embodiments, first metal lines S1M0through S8M0(refer toFIG. 13) forming string selection lines SSL and ground selection lines GSL extend along the first direction to be connected with pass transistors PT. First metal lines S1M0through S8M0further extend along the first direction to be connected with ground transistors GT.

Compared with block gating unit ofFIG. 18, the block gating unit ofFIG. 19omits transistors between ground transistors GT and pass transistors PT. Accordingly, bussing of first metal lines S1M0through S8M0and structural integrity may be improved.

FIG. 20is a block diagram of a memory system1000according to an embodiment of the inventive concept.

Referring toFIG. 20, a memory system1000comprises a nonvolatile memory device1100and a controller1200. Nonvolatile memory device1100has substantially the same structure and functionality as a nonvolatile memory device100. Controller1200is coupled with a host and nonvolatile memory device1100. Controller1200is configured to access nonvolatile memory device1100in response to a request from the host. Controller1200is configured to control read, program, erase, and background operations of nonvolatile memory device1100, for example. Controller1200is configured to provide an interface between nonvolatile memory device1100and the host. Controller1200is configured to drive firmware for controlling the nonvolatile memory device1100.

Controller1200is configured to provide a control signal CTRL and an address ADDR to nonvolatile memory device1100. Nonvolatile memory device1100is configured to perform read, program, and erase operations according to control signal CTRL and address ADDR provided from controller1200.

In some embodiments, controller1200further comprises a RAM, a processing unit, a host interface, and a memory interface. The RAM is used as at least one of a working memory of the processing unit, a cache memory between the nonvolatile memory device1100and the host or a buffer memory between the nonvolatile memory device1100and the host. The processing unit controls overall operation of controller1200.

The host interface implements a protocol for data exchange between host and controller1200. For example, the host interface can communicate with an external device (e.g., the host) using a standard protocol such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnection (PCI) protocol, a PCI-express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial-ATA protocol, a parallel-ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, and an integrated drive electronics (IDE) protocol. The memory interface interfaces with nonvolatile memory device1100. The memory interface can comprise, for instance, a NAND flash interface or a NOR flash interface.

Memory system1000can further comprise an ECC block configured to detect and correct errors in data read from nonvolatile memory device1100. The ECC block can be provided as an element of controller1200or as an element of nonvolatile memory device1100.

Controller1200and nonvolatile memory device1100can be integrated in a single semiconductor device. For example, controller1200and nonvolatile memory device1100can be integrated to form a memory card such as a PC or PCMCIA card, a CF card, an SM or SMC card, a memory stick, a multimedia card such as an MMC, RS-MMC, or MMCmicro card, a security card such as an SD card, a miniSD card, a microSD card, or an SDHC card, or a universal flash storage (UFS) device.

Controller1200and nonvolatile memory device1100can also be integrated in a single semiconductor device to form a solid state drive (SSD). Where memory system1000is used in an SSD, it can improve the operating speed of a host coupled with memory system1000.

Memory system1000can also be used in a computer, portable computer, ultra mobile PC (UMPC), workstation, net-book, PDA, web tablet, wireless phone, mobile phone, smart phone, e-book, PMP (portable multimedia player), digital camera, digital audio recorder/player, digital picture/video recorder/player, portable game machine, navigation system, black box, 3-dimensional television, a device capable of transmitting and receiving information at a wireless circumstance, one of various electronic devices constituting home network, one of various electronic devices constituting computer network, one of various electronic devices constituting telematics network, RFID, and many other types of devices.

Nonvolatile memory device1100and/or memory system1000can be packaged in various types of packages or package configurations, such as package on package (PoP), ball grid arrays (BGAs), chip scale packages (CSPs), plastic leaded chip carrier (PLCC), plastic dual in-line package (PDI2P), die in waffle pack, die in wafer form, chip on board(COB), ceramic dual in-line package (CERDIP), plastic metric quad flat pack (MQFP), small outline integrated circuit (SOIC), shrink small outline package (SSOP), thin small outline (TSOP), thin quad flatpack (TQFP), system in package (SIP), multi chip package (MCP), wafer-level fabricated package (WFP), and wafer-level processed stack package (WSP).

FIG. 21is a block diagram of a memory system2000according to an embodiment of the inventive concept. This embodiment is a variation of the memory system illustrated inFIG. 20.

Referring toFIG. 21, a memory system2000comprises a nonvolatile memory device2100and a controller2200. Nonvolatile memory device2100comprises a plurality of nonvolatile memory chips divided into a plurality of groups. Nonvolatile memory chips in each group communicate with controller2200via a common channel. InFIG. 21, a plurality of memory chips communicate with controller2200via K channels CH1through CHk. Each of the nonvolatile memory chips can be formed with substantially the same structure and functionality as nonvolatile memory device100or nonvolatile memory1100ofFIG. 19.

As illustrated inFIG. 21, one channel may be connected with a plurality of nonvolatile memory chips. However, memory system2000may be modified such that one channel is connected with one nonvolatile memory chip.

FIG. 22is a block diagram of a computing system3000comprising memory system2000ofFIG. 21.

Referring toFIG. 22, computing system3000comprises a CPU3100, a RAM3200, a user interface3300, a power supply3400, and a memory system2000.

Memory system2000is electrically connected with CPU3100, RAM3200, user interface3300, and power supply3400. Data provided via user interface3300or processed by CPU3100is stored in memory system2000. In the embodiment ofFIG. 22, nonvolatile memory device2100is connected with a system bus3500via controller2200. However, in other embodiments, nonvolatile memory device2100can be connected directly with system bus3500.

As an alternative to incorporating memory system2000ofFIG. 21, computing system3000can incorporate memory system1000ofFIG. 20. As another alternative, computing system3000can incorporate both of memory systems1000and2000described inFIGS. 20 and 21.