Display pipe line buffer sharing

An apparatus for processing graphics data may include a plurality of processing pipelines, each pipeline configured to receive and process pixel data. A functional unit may combine the outputs of each processing pipeline. A buffer included in a given processing pipeline may be configured to store data from the functional unit in response to a determination that the given processing pipeline is inactive. The buffer may then send the stored data to a memory.

BACKGROUND

1. Technical Field

This disclosure relates generally to processing video input for display, and more specifically to methods for sharing hardware resources between different display pipelines.

2. Description of the Related Art

Part of the operation of many computer systems, including portable digital devices such as mobile phones, notebook computers and the like, is the use of some type of display device, such as a liquid crystal display (LCD), to display images, video information/streams, and data. Accordingly, these systems typically incorporate functionality for generating images and data, including video information, which are subsequently output to the display device. Such devices typically include video graphics circuitry to process images and video information for subsequent display.

In digital imaging, the smallest item of information in an image is called a “picture element”, more generally referred to as a “pixel.” For convenience, pixels are generally arranged in a regular two-dimensional grid. By using this arrangement, many common operations can be implemented by uniformly applying the same operation to each pixel independently. Since each pixel is an elemental part of a digital image, a greater number of pixels can provide a more accurate representation of the digital image. To represent a specific color on an electronic display, each pixel may have three values, one each for the amounts of red, green, and blue present in the desired color. Some formats for electronic displays may also include a fourth value, called alpha, which represents the transparency of the pixel. This format is commonly referred to as ARGB or RGBA. Another format for representing pixel color is YCbCr, where Y corresponds to the luma, or brightness, of a pixel and Cb and Cr correspond to two color-difference chrominance components, representing the blue-difference (Cb) and red-difference (Cr).

Most images and video information displayed on display devices such as LCD screens are interpreted as a succession of image frames, or frames for short. While generally a frame is one of the many still images that make up a complete moving picture or video stream, a frame can also be interpreted more broadly as simply a still image displayed on a digital (discrete, or progressive scan) display. A frame typically consists of a specified number of pixels according to the resolution of the image/video frame. Most graphics systems use frame buffers to store the pixels for image and video frame information. The term “frame buffer” often denotes the actual memory used to hold picture/video frames. The information in a frame buffer typically consists of color values for every pixel to be displayed on the screen. Color values are commonly stored in 1-bit monochrome, 4-bit palletized, 8-bit palletized, 16-bit high color and 24-bit true color formats. An additional alpha channel is oftentimes used to retain information about pixel transparency. The total amount of the memory required for frame buffers to store image/video information depends on the resolution of the output signal, and on the color depth and palette size. The High-Definition Television (HDTV) format, for example, is composed of up to 1080 rows of 1920 pixels per row, or almost 2.1M pixels per frame.

Various display formats are in common use today for computing devices to connect to electronic displays, including, but not limited to, older standards such as VGA and DVI, and more modern standards such as HDMI and DisplayPort. In addition, new standards are being developed such as, for example, HDBaseT. These various formats have various data resolution requirements, resulting in some formats using more data bits per pixel than others. In order to provide a high quality picture to all formats, an apparatus as discussed above may process all graphical data with enough data bits for the supported display format requiring the highest resolution. This leaves the apparatus responsible for removing data bits in order to support the other formats, which use lower resolutions.

SUMMARY OF EMBODIMENTS

Various embodiments of methods and devices for processing pixel data are disclosed. Broadly speaking an apparatus and method are contemplated in which the apparatus includes a plurality of processing pipelines, each of which may configured to process received pixel data and generate respective formatted data. A functional unit may combine the formatted data from each processing pipeline to generate display data. A first buffer included in a first processing pipeline of the plurality of processing pipelines may be configured to receive and store the display data in response to a determination that the first processing pipeline is inactive. The first buffer may be further configured to send the stored display data to a memory.

In another embodiment, circuitry may be configured to disable a first clock signal coupled to at least one processing pipeline of the plurality of processing pipelines. The circuitry may disabled the first clock in response to a determination that an amount of data stored in the first buffer is greater than or equal to a first buffer threshold value, and that an amount of data stored in the memory is greater than or equal to a first memory threshold value.

In other embodiments, the circuitry may be further configured to enable a second clock signal coupled to the first buffer. The circuitry may enable the second clock signal in response to a determination that the amount of data stored in the memory is less than a second memory threshold value.

DETAILED DESCRIPTION OF EMBODIMENTS

In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, one having ordinary skill in the art should recognize that the invention might be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the present invention.

Typically, raw video is received by an apparatus (e.g., an integrated circuit (IC), such as a system-on-a-chip (SOC), or a package such as a multi-chip module (MCM)) of a computer system in a format that is not directly compatible with the electronic display to which a display controller of the apparatus outputs frames to be displayed. In addition, the display controller may not accept the raw video format as input. Thus, at least some processing of input video may be performed by the apparatus to convert the video input into a display-compatible format before outputting the video frames to the electronic display for viewing. For example, the apparatus may be used to convert the video input from a raw video format (e.g., YUV420/1080p) to electronic display (e.g., ARGB) format frames of an appropriate size for viewing prior to feeding the video frames to the display controller. The display controller may perform additional rendering of the frames prior to feeding the frames to the electronic display.

In addition, there may be other graphical content, for example user interface graphics or objects, that may be input to the apparatus for processing and displaying to the electronic display. One or more video input streams and one or more of these other graphical input sources may be input for display concurrently. For example, a user may be watching a video on the computer system, and the operating system (OS) of the computer system or an application on the device may, during the video generate a notification or other user interface element that needs to be presented on the electronic display. Thus, in addition to video processing, another function that may be performed by the apparatus is combining these different graphical inputs such as, e.g., a video stream and one or more Graphical User-Interface (GUI) elements, into output frames to be presented on the electronic display simultaneously. This function may be referred to as window compositing.

During the processing of a frame of data, only portions of a display processor may be active. For example, only one generic pipeline may be used to downscale a user interface frame for display. Alternatively, a single generic pipeline may be operating in a no-scale mode to display a frame. In such cases, other generic pipelines may be active. While the other generic pipelines may be clock gated (i.e., a clock signal coupled to the pipeline may be stopped) to save dynamic power, the other generic pipelines may not be power gated which may be an inefficient use of power resources. The embodiments illustrated in the drawings and described below may provide techniques for using hardware resources of inactive generic pipelines to increase the effective capacity of storage circuits within the active portion of the display processor to improve power efficiency.

A block diagram of an embodiment of a computing system is illustrated inFIG. 1. In different embodiments, computer system100may be any of various types of devices, including, but not limited to, a desktop computer, laptop, tablet or pad device, mainframe computer system, workstation, a camera, a set top box, a mobile device, a mobile phone, a consumer device, video game console, handheld video game device, or any general type of computing or electronic device.

In the illustrated embodiment, computer system100includes one or more processors110coupled to system memory120via input/output (I/O) interface130. Computer system100further includes network interface140coupled to I/O interface130, and one or more input/output devices150, such as cursor control device160, keyboard170, and display(s)180. Computer system100may also include one or more cameras190, which may also be coupled to I/O interface130. At least one of cameras190may be operable to capture video sequences.

Although computer system100depicts a multiple processors (commonly referred to as a “multiprocessor system”), in other embodiments, a single processor may be employed. Processors110may be any suitable processor capable of executing instructions. For example, in various embodiments processors110may be general-purpose or embedded processors implementing any of a variety of Instruction Set Architectures (ISAs), such as the x86, PowerPC, SPARC, or MIPS ISAs, or any other suitable ISA. In multiprocessor systems, each of processors110may commonly, but not necessarily, implement the same ISA.

System memory120may be configured to store program instructions122and/or data132accessible by processor110. In various embodiments, system memory120may be implemented using a variety of memory technologies, such as, e.g., Static Random Access Memory (SRAM), Synchronous Dynamic Random Access Memory (SDRAM), non-volatile memory, or any other suitable type of memory. In the illustrated embodiment, program instructions122may be configured to implement various interfaces, methods and/or data, such, e.g., drivers, for controlling operations of an apparatus implementing embodiments of multiple video processing modes and embodiments of image compression techniques. Although only a single memory is illustrated in computing system100, in some embodiments, different numbers and different configurations of memories may be employed.

In one embodiment, I/O interface130may be configured to coordinate I/O traffic between processor110, system memory120, and any peripheral devices in the device, including network interface140or other peripheral interfaces, such as input/output devices150. In some embodiments, I/O interface130may perform any necessary protocol, timing or other data transformations to convert data signals from one component such as, e.g., system memory120, into a format suitable for use by another component such as, processor110, for example. In some embodiments, I/O interface130may include support for devices attached through various types of peripheral buses, such as a variant of the Peripheral Component Interconnect (PCI) bus standard or the Universal Serial Bus (USB) standard, for example. In some embodiments, the function of I/O interface130may be split into two or more separate components, such as a north bridge and a south bridge, for example. Also, in some embodiments some or all of the functionality of I/O interface130, such as an interface to system memory120, may be incorporated directly into processor110.

Network interface140may be configured to allow data to be exchanged between computer system100and other devices attached to a network185(e.g., carrier or agent devices) or between nodes of computer system100. Network185may in various embodiments include one or more networks including but not limited to Local Area Networks (LANs) (e.g., an Ethernet or corporate network), Wide Area Networks (WANs) (e.g., the Internet), wireless data networks, some other electronic data network, or some combination thereof. In various embodiments, network interface140may support communication via wired or wireless general data networks, such as, e.g., any suitable type of Ethernet network, via telecommunications/telephony networks such as analog voice networks or digital fiber communications networks; via storage area networks such as Fiber Channel SANs, or via any other suitable type of network and/or protocol.

Input/output devices150may, in some embodiments, include one or more display terminals, keyboards, keypads, touchpads, scanning devices, voice or optical recognition devices, or any other devices suitable for entering or accessing data by computer system100. Multiple input/output devices150may be present in computer system100or may be distributed on various nodes of computer system100. In some embodiments, similar input/output devices may be separate from computer system100and may interact with one or more nodes of computer system100through a wired or wireless connection, such as over network interface140.

As shown inFIG. 1, system memory120may include program instructions122, which may be processor-executable to implement any element or action to support operations of circuit blocks implementing embodiments of multiple video processing modes and embodiments of image compression techniques. In at least some embodiments, images or video captured by a camera190may be stored to system memory120. In addition, metadata for images or video captured by a camera190may be stored to system memory120. Video streams stored to system memory120may, for example, be processed by embodiments of an apparatus implementing embodiments of multiple video processing modes and embodiments of image compression techniques.

It is noted that the embodiment illustrated inFIG. 1is merely an example. In particular, the computer system and devices may include any combination of hardware or software that can perform the indicated functions, including computers, network devices, Internet appliances, PDAs, wireless phones, pagers, video or still cameras, etc. Computer system100may also be connected to other devices that are not illustrated, or instead may operate as a stand-alone system. In addition, the functionality provided by the illustrated components may, in some embodiments, be combined in fewer components or distributed in additional components. Similarly, in other embodiments, the functionality of some of the illustrated components may not be provided and/or other additional functionality may be available.

It is further noted that, while various items are illustrated as being stored in memory or on storage while being used, these items or portions of them may be transferred between memory and other storage devices for purposes of memory management and data integrity. Alternatively, in other embodiments some or all of the software components may execute in memory on another device and communicate with the illustrated computer system100via inter-computer communication. Some or all of the system components or data structures may also be stored (e.g., as instructions or structured data) on a computer-accessible medium or a portable article to be read by an appropriate drive, various examples of which are described above. In some embodiments, instructions stored on a computer-accessible medium separate from computer system100may be transmitted to computer system100via transmission media or signals such as electrical, electromagnetic, or digital signals, conveyed via a communication medium such as a network and/or a wireless link. Various embodiments may further include receiving, sending or storing instructions and/or data implemented in accordance with the foregoing description upon a computer-accessible medium. Generally speaking, a computer-accessible medium may include a non-transitory, computer-readable storage medium or memory medium such as magnetic or optical media, e.g., disk or DVD/CD-ROM (Read-Only Memory), volatile or non-volatile media such as Random Access Memory (RAM), such as, e.g., Synchronous Dynamic RAM (SDRAM), Double Data Rate SDRAM (DDR), Static RAM (SRAM), etc.), ROM, flash, etc. In some embodiments, a computer-accessible medium may include transmission media or signals such as electrical, electromagnetic, or digital signals, conveyed via a communication medium such as network and/or a wireless link.

Turning toFIG. 2, an embodiment of a display processor is illustrated. In the illustrated embodiment, display processor200may be coupled to a system bus220and to a display back end230. Display processor200may include functional sub-blocks such as one or more generic pipelines (also referred to herein as “processing pipelines” or “processing pipes”)201a-b, coupled to system bus220, blending unit202, coupled to generic pipelines201, gamut adjustment block203, coupled to blending unit202, color space converter204, coupled to gamut adjustment block203, multiplex circuit240coupled to generic pipe210band coupled to display back end230. Display processor200may also include control registers205, coupled to the various sub-blocks in display controller200, and a parameter First-In First-Out buffer (FIFO)206, coupled to system bus220and control registers205. Display processor200may also include control unit207.

System bus220, in some embodiments, may correspond to I/O interface130fromFIG. 1. System bus220couples various functional blocks such that the functional blocks may pass data between one another. Display controller200may be coupled to system bus220in order to receive video frame data for processing. In some embodiments, display processor200may also send processed video frames to other functional blocks and or memory that may also be coupled to system bus220.

Display back end230may receive processed image data as each pixel is processed by display processor200. Display back end230includes FIFO231, and may provide final processing to the image data before each video frame is displayed. In some embodiments, display back end may include ambient-adaptive pixel (AAP) modification, dynamic backlight control (DPB), display panel gamma correction, and dithering specific to an electronic display coupled to display back end230.

The display processor200may include one or more generic pipelines201a-b. Each generic pipeline201may fetch a video frame from a buffer coupled to system bus220. The buffered video frame may reside in a system memory such as, for example, system memory120fromFIG. 1. Each generic pipeline201may fetch a distinct image and may process its image in various ways to create formatted data. The processing to create the formatted data may include format conversion, such as, for example, YCbCr to ARGB, image scaling, dithering, and the like. In some embodiments, each generic pipeline may process one pixel at a time, in a specific order from the video frame, outputting a stream of formatted pixel data, maintaining the same order as pixel data passes through.

As described below in more detail, each of generic pipelines201a-bincludes a line buffer. In some embodiments, a line buffer from an inactive generic pipeline may be coupled to a line buffer of an active generic pipeline to increase the effective storage capacity of the line buffer of the active generic pipeline. For example, in cases when generic pipeline201bis not processing data associated with a particular frame, data to be stored in line buffer290of generic pipeline201amay be stored in either line buffer290of line buffer250. By using line buffer250to increase the effective storage capacity of line buffer290, more than one line of the particular frame may be stored, thereby reducing the frequency of fetch requests sent via bus220.

Multiplex circuit240may be configured to select one of color space converter output270or line buffer output280in response to control signal260. In some embodiments, when generic pipe201bis not being used to process a given frame, line buffer250of generic pipe201bmay be used as additional storage in the output path. Color space converter output270may be routed to line buffer250for storage. Line buffer output280may then be selected by multiplex circuit240to send to display back end230. By routing data from the color space converter204through line buffer250, the effective storage capacity of output FIFO231may, in various embodiments, be increased. As described below in more detail, line buffer250and output FIFO231may be coupled to different clock signals, allowing separate clock gating for each of the storage circuits.

Control unit207may, in various embodiments, be configured to arbitrate read requests to fetch data from memory from the generic pipeline201aand generic pipeline201b. In some embodiments, generic pipeline201aand generic pipeline201bmay each generate two read requests, resulting in four read requests competing for access to memory. Generic pipelines201aand201bmay, in other embodiments, assign an initial priority to each of the generated read requests. Control unit207may, in some embodiments, assign a priority to each request and dependent upon a display coordinate (where on a display the data to be fetch is to be shown). In various embodiments, control unit207may assign priorities to the read requests dependent upon any assigned initial priorities. The assigned priorities may then be used by control unit207to determine an order in which requests may be sent via bus220to memory. In some embodiments, the read requests may point to a virtual address. A memory management unit (not shown) may convert the virtual address to a physical address in memory prior to the requests being presented to the memory. In some embodiments, control unit207may generate control signal260to control multiplex circuit240. Control unit207may detect that for a given frame may be processed by a single generic pipe, and an input buffer of an unused generic pipe, such as input buffer250, may be used as another FIFO in output path (also referred to herein as a “post-blend” FIFO).

In some embodiments, control unit207may include a dedicated state machine or sequential logic circuit. A general purpose processor executing program instructions stored in memory may, in other embodiments, be employed to perform the functions of control unit207.

The output from generic pipelines201may be passed on to blending unit202. Blending unit202may receive a pixel stream from one or more generic pipelines. If only one pixel stream is received, blending unit202may simply pass the stream through to the next sub-block. However, if more than one pixel stream is received, blending unit202may blend the pixel colors together to create an image to be displayed. In various embodiments, blending unit202may be used to transition from one image to another or to display a notification window on top of an active application window. For example, a top layer video frame for a notification, such as, for a calendar reminder, may need to appear on top of, i.e., as a primary element in the display, despite a different application, an internet browser window for example. The calendar reminder may comprise some transparent or semi-transparent elements in which the browser window may be at least partially visible, which may require blending unit202to adjust the appearance of the browser window based on the color and transparency of the calendar reminder. The output of blending unit202may be a single pixel stream composite of the one or more input pixel streams.

The output of blending unit202may be sent to gamut adjustment unit203. Gamut adjustment203may adjust the color mapping of the output of blending unit202to better match the available color of the intended target display.

The output of gamut adjustment unit203may be sent to color space converter204. Color space converter204may take the pixel stream output from gamut adjustment unit203and convert it to a new color space. Color space converter204may then send the pixel stream to display back end230or back onto system bus220. In other embodiments, the pixel stream may be sent to other target destinations. For example, the pixel stream may be sent to a network interface, such as network interface140fromFIG. 1, for example. In some embodiments, new color space may be chosen based on the mix of colors after blending and gamut corrections have been applied. In further embodiments, the color space may be changed based on the intended target display.

The parameters that display processor200may use to control how the various sub-blocks manipulate the video frame may be stored in control registers205. These registers may include, but not limited to, setting input and output frame sizes, setting input and output pixel formats, location of the source frames, and destination of the output (display back end230or system bus220). Control registers205may be loaded by parameter FIFO206.

Parameter FIFO206may be loaded by a host processor, a direct memory access unit, a graphics processing unit, or any other suitable processor within the computing system. In other embodiments, parameter FIFO206may directly fetch values from a system memory, such as, for example, system memory120inFIG. 1. Parameter FIFO206may be configured to update control registers205of display processor200before each video frame is fetched. In some embodiments, parameter FIFO may update all control registers205for each frame. In other embodiments, parameter FIFO may be configured to update subsets of control registers205including all or none for each frame.

A FIFO as used and described herein, may refer to a memory storage buffer in which data stored in the buffer is read in the same order it was written. A FIFO may be comprised of RAM or registers and may utilize pointers to the first and last entries in the FIFO.

It is noted that the display processor illustrated inFIG. 2is merely an example. In other embodiments, different functional blocks and different configurations of functional blocks may be possible dependent upon the specific application for which the display processor is intended. For example, more than two generic pipelines may be included.

Turning toFIG. 3, an embodiment of a generic pipeline is illustrated. In some embodiments, generic pipeline300may correspond to generic pipelines201aand201bof display processor200as illustrated inFIG. 2, and may include multiple functional sub-units. In the illustrated embodiment, generic pipeline300includes fetch unit301, pre-fetch unit302, structure noise unit303, multiplex circuit312, line buffer304, vertical scaler305, horizontal scaler306, color space converter307, and gamut adjust unit308. In general, generic pipeline300may be responsible for fetching pixel data for source frames stored in a memory, and then processing the fetched data before sending the processed data to a blend unit, such as, blend unit202of display processor200as illustrated inFIG. 2.

Fetch unit301and pre-fetch unit302may, in some embodiments, be configured to generate read requests for source pixel data needed by generic pipeline300. In some embodiments, the order in which read request are sent to memory (also referred to as a “source buffer”) may be dependent upon a number of source buffer lines needed to generate an output line of a destination frame. Request the source lines, i.e., fetching the source lines from the source buffer, is commonly referred to as a “pass” of the source buffer.

In some embodiments, only data contained in one line of a source buffer may be needed when processing the beginning of a frame. An initial pass of the source buffer may, in various embodiments, include a fetch of as many as nine lines from the source buffer. In other embodiments, subsequent passes through of the source buffer may fetch may require less lines. During each pass of the source buffer, required portions or blocks of data may be fetched from top to bottom, then from left to right, where “top,” “bottom,” “left,” and “right” are in reference to a display.

Each read request may include one or more addresses indicating where the portion of data is stored in memory, i.e., a source buffer. In some embodiments, address information included in the read requests may be directed towards a virtual (also referred to herein as “logical”) address space, i.e., an addresses scheme that does not directly point to physical locations within a memory device, but rather is a simplified address space unique to a given processing process, such as, display processing, for example. In such cases, the virtual addresses may be mapped to physical addresses before the read requests are sent to the source buffer. A memory management unit may, in some embodiments, be used to map the virtual addresses to physical addresses. In some embodiments, the memory management unit may be included within the display processor, while in other embodiments, the memory management unit may be located elsewhere within a computing system.

Structured noise unit303may, in various embodiments, provide structured noise dithering on the Luma channel of YCbCr formatted data. Other channels, such as, e.g., the chroma channels of YCbCr, and other formats, such as, e.g., ARGB may not be dithered. In various embodiments, structured noise unit303may apply a two-dimensional array of Gaussian noise (i.e., statistical noise that is normally distributed) to blocks of the source frame data. A block of source frame data may, in some embodiments, include one or more source pixels. The noise may be applied to raw source data fetched from memory prior to scaling.

Multiplex circuit312may be configured to select one of the structured noise unit303or input data309for input to line buffer304responsive to control signal310. By allowing for two different data sources to be used as input to line buffer304, the storage capacity of line buffer304may be made available to other storage units within a display processor, such as display processor200, for example. In some embodiments, the storage capacity of line buffer304may be used to effectively increase the size of a line buffer in another generic pipeline, function as a standalone FIFO memory, or another suitable use.

Multiplex circuit312may be designed in accordance with numerous design styles. For example, multiplex circuit312may include one or more pass gates controlled by control signal310. The output of each pass gate may be coupled together in a wired-OR fashion. It is noted that a pass gate (also referred to as a “transmission gate”) may include an n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) and a p-channel MOSFET connected in parallel. In other embodiments, a single n-channel MOSFET or a single p-channel MOSFET may be used as a pass gate. It is further noted that, in various embodiments, a “transistor” may correspond to one or more transconductance elements such as a junction field-effect transistor (JFET), for example.

Line buffer304may be configured to store a line of a source frame. The line may include data indicative of luminance and chrominance of individual pixels included within the line. Line buffer304may be designed in accordance with one of various design styles. For example, line buffer304may be a SRAM, DRAM, or any other suitable memory type. In some embodiments, line buffer304may include a single input/output port, while, in other embodiments, line buffer304may have multiple data input/output ports. The output of line buffer304may be coupled to the input of vertical scaler305in addition to output data311. As described above, by providing for the output of line buffer304to exit generic pipeline300in conjunction with multiplex circuit312, the storage capacity of line buffer304may be used to increase an effective storage capacity of another storage circuit, or be used as a standalone memory within a display processor.

In some embodiments, scaling of source pixels may be performed in two steps. The first step may perform a vertical scaling, and the second step may perform a horizontal scaling. In the illustrated embodiment, vertical scaler305and horizontal scaler306may perform the vertical and horizontal scaling, respectively. Vertical scaler305and horizontal scaler306may be designed according to one of varying design styles. In some embodiments, vertical scaler305and horizontal scaler306may be implemented as a 9-tap 32-phase filters. Such a multi-phase filter may, in various embodiments, multiply each pixel retrieved by fetch unit302by a weighting factor. The results pixel values may then be added, and then rounded to form a scaled pixel. The selection of pixels to be used in the scaling process may be a function of a portion of a scale position value. In some embodiments, the weighting factors may be stored in a programmable table, and the selection of the weighting factors to use in the scaling may be a function of a different portion of the scale position value.

In some embodiments, the scale position value (also referred to herein as the “display position value”), may included multiple portions. For example, the scale position value may include an integer portion and a fractional portion. In some embodiments, the determination of which pixels to scale may depend on the integer portion of the scale position value, and the selecting of weighting factors may depend on the fractional portion of the scale position value. A Digital Differential Analyzer, as described below in more detail in regards toFIG. 4, may, in various embodiments, be used to determine the scale position value.

Color management within generic pipeline300may be performed by color space converter307and gamut adjust unit308. In some embodiments, color space converter307may be configured YCbCr source data to the RGB format. Alternatively, color space converter may be configured to remove offsets from source data in the RGB format. Color space converter307may, in various embodiments, include a variety of functional blocks, such as, e.g., an input offset unit, a matrix multiplier, and an output offset unit (all not shown). The use of such blocks may allow the conversion from YCbCr format to RGB format and vice-versa.

Gamut adjust unit308may, in various embodiments, be configured to convert pixels from a non-linear color space to a linear color space, and vice-versa. In some embodiments, gamut adjust unit308may include a Look Up Table (LUT) and an interpolation unit. The LUT may, in some embodiments, be programmable and be designed according to one of various design styles. For example, the LUT may include a SRAM or DRAM, or any other suitable memory circuit. In some embodiments, multiple LUTs may be employed. For example, separate LUTs may be used for Gamma and De-Gamma calculations.

It is noted that the embodiment illustrated inFIG. 3is merely an example. In other embodiments, different functional blocks and different configurations of functional blocks are possible and contemplated.

A block diagram illustrating clock domains in a display processor is depicted inFIG. 4. The illustrated embodiment includes fetch unit401, generic pipe402, blend unit403, post-blend FIFO404, and output FIFO405. In various embodiments, fetch unit401may correspond to fetch unit301and pre-fetch unit302as illustrated inFIG. 3, and generic pipe402may correspond to the remaining blocks of generic pipeline300as illustrated inFIG. 3. Each of fetch unit401, generic pipe402, and blend unit403is included in clock domain408, while post-blend FIFO404may be included in clock domain407. Output FIFO405may in a third (not shown) clock domain. Functional units within a given clock domain, such as, e.g., clock domain408, may be coupled to a common clock that may be disabled (also referred to herein as “gated”) to reduce power consumption. In various embodiments, a clock signal included each of clock domains407and408may transition at different frequencies, while, in other embodiments, the clock signals in the different clock domains may transition at the same frequency.

Post-blend FIFO404may, in some embodiments, correspond to a line buffer included in an inactive generic pipeline, such as, line buffer250ofFIG. 2, for example. In various embodiments, output FIFO405may correspond to a display back end FIFO, such as, e.g., output FIFO231.

During operation, clock domains408and407are both active and clock gating may not be enabled in either domain. As frame data is fetched by fetch unit401, and processed by generic pipe402and blend unit403, processed data flows through post-blend FIFO404and is stored in output FIFO405. As output FIFO405fills with data, processed data will also be stored in post-blend FIFO404.

When an amount of data stored in output FIFO405is greater than a high memory threshold, and an amount of data stored in post-blend FIFO404is greater than a high buffer threshold, clock gating may be enabled in both clock domain407and clock domain408, thereby allowing power to be conserved in the functional units included in those clock domains. While clock gating is enabled in both clock domains407and408, data is still being removed from output FIFO405.

When an amount of data stored in output FIFO405falls below a predetermined threshold value, clock gating may be disabled in clock domain407. With clock gating disabled in clock domain407, post-blend FIFO404may operate continuously, i.e., without inactive periods due to clock gating, sending data to output FIFO405.

When an amount of data stored in post-blend FIFO404falls below another predetermined threshold value, clock gating may then be disabled for clock domain407, allowing fetch unit401, generic pipe402, and blend unit403to operate without interruption. With the aforementioned units running, the aforementioned operations will repeat until both output FIFO405and post-blend FIFO404are both full, at which point, clock gating will be enabled for clock domains407and408. The procedure may then repeat until a complete frame has been processed. Once the complete frame has been processed, the line buffer being used as post-blend FIFO404may be re-mapped to be included in its corresponding generic pipeline.

It is noted that the embodiment illustrated inFIG. 4is merely an example. In other embodiments, different numbers of clocks domains, with different numbers number of functional units within each of the clock domains may be employed.

Turning toFIG. 5, a flow diagram depicting a method for operating a display processor, such as, e.g., display processor200, is illustrated. The method begins in block501. Pixel data for a new frame may then be received (block702). In various embodiments, the display processor may send a request for data via a communication bus, such as, bus220, for example. In response to the request, a memory, such as, e.g., memory120, may send the pixel data to the display processor via the same communication bus.

The method may then depend on a number of generic pipelines to be used in processing the frame data (block503). If more than one generic pipeline is required to process the frame data, then the method may conclude in block506.

If only a single generic pipeline is to be used in processing the frame data, then line buffers from unused generic pipelines may then be used to increase an effective size of an output buffer (block504). In some embodiments, a multiplex circuit, such as, e.g., multiplex circuit312may route data from outside of an inactive generic pipeline to the input of a line buffer of the inactive generic pipeline. For example, the output of color space converter204may be sent to the input of line buffer250of generic pipe201bof display processor200as illustrated inFIG. 2.

The output from the line buffer of an inactive generic pipeline may be routed to an output of a display processor. A multiplex circuit, such as, e.g., multiplex circuit240may then select, depending on an operating mode, between the output of a functional unit, such as, e.g., color space converter204, and the line buffer of the inactive generic pipeline (e.g., line buffer250). When the output of the line buffer of the inactive generic pipeline is selected for output from the display processor, the line buffer provides additional storage capacity for an output FIFO in a display back end unit, such as, display back end230, for example.

As described above in more detail in regard toFIG. 4, the line buffer of the inactive generic pipeline may be included in a different clock domain than the output FIFO of the display back end or the active generic pipeline. By including each of the aforementioned entities in different clock domains, the active generic pipeline may be clock gated while data is transferred from the line buffer to the output FIFO. With the active generic pipeline clock gated, request and response traffic on a communication bus, such as, bus220, may be reduced, thereby reducing system power consumption.

It is noted that the used of an input buffer of an inactive generic pipeline may be dependent on an operating mode of a display processor. In some embodiments, the line buffer of an inactive generic pipeline may be used during a downscaling mode.

Once the multiplex circuits have been set to allow for the use of the line buffer of an inactive generic pipeline at the output of the display processor, the frame data may then be processed (block505). In some embodiments, processing the frame data may include color space conversion, gamut adjust, and the like. The method may then conclude in block506. The control signals operating multiplex circuits, such as, e.g., multiple circuit240, that allow the use of the line buffer of an inactive generic pipeline external to the inactive generic pipeline may be reset following completion of processing the current frame, thereby allowing the inactive generic pipeline to be used in processing a subsequent frame.

It is noted that the embodiment illustrated inFIG. 5is merely an example. In other embodiments, different operations and different orders of operations are possible and contemplated.

An embodiment of a method for performing clock gating is illustrated in the flow diagram depicted inFIG. 6. Referring collectively to the block diagram ofFIG. 4and the flow diagram ofFIG. 6, the method begins in block601. Received pixel data may then be processed (block602). In various embodiments, the processing performed may include scaling, color correction, color conversion, and the like. The method may then depend on if the end of a frame has been reached (block603). Once the end of the frame has been reached, the method may conclude in block612.

If, however, there are still lines of the frame left to process, the method may then depend on if an amount of data stored in post-blend FIFO404is greater than or equal to a gate threshold (block604). The amount of data stored in post-blend FIFO404may be determined in various ways. For example, in some embodiments, a counter may be incremented responsive to a write to the FIFO and decremented responsive to a read from the FIFO. The gate threshold may, in some embodiments, be a predetermined value, while, in other embodiments, the gate threshold may be programmable or under other software control.

If the amount of data stored in post-blend FIFO404is less than the gate threshold, then the method may proceed from block602as described above. If, however, the amount of data stored in post-blend FIFO404is greater than or equal the gate threshold, then clock gating for clock domain408may be enabled. In various embodiments, a clock signal coupled to each of fetch unit401, generic pipe402, and blend unit403may be selective disabled (i.e., “gated”). The gating of the aforementioned clock signal may, in some embodiments, depend upon work load, power consumption, or any other suitable metric.

The method may then depend upon if the amount of data stored in the post-blend FIFO is less than a ungate threshold (block606). The ungate threshold may, in some embodiments, be a predetermined value, while, in other embodiments, the ungate threshold may be programmable or be under software control. If the amount of data stored in post-blend FIFO is greater than or equal to the ungate threshold, then clock gating for clock domain408may be disable (block611). In various embodiments, the clock signal coupled to each of fetch unit401, generic pipe402, and blend unit403, may be allowed to run without interruption (i.e., “ungated”). Once clock gating for clock domain408has been disabled, then method may continue from block602as described above.

If the amount of data stored in post-blend FIFO is less than the ungate threshold, then the method may depend on if an amount of data stored in output FIFO405is greater than or equal to another gate threshold (block607). The amount of data stored in output FIFO607may, in various embodiments, be determined using a counter or any other suitable method. If the amount of data stored in output FIFO405is less than the another gate threshold, then the method may proceed from block606as described above. It is noted that the another gate threshold may be programmable, in various embodiments.

If, however, the amount of data stored in output FIFO405is greater than or equal to the another gate threshold, the clock gating may be enabled for clock domain407(block608). In various embodiments, a clock signal coupled to post-blend FIFO404, or other functional units within clock domain407(not shown) may be gated.

Once clock gating for clock domain407is enabled, the method may then depend on if the amount of data stored in output FIFO405is less than another ungate threshold value (block609). As with the another gate threshold, the another ungate threshold value may be a predetermined value, or, in various embodiments, be programmable. If the amount of data stored in output FIFO405is greater than or equal to the another ungate threshold, then the method may proceed from block608as described above.

If the amount of data stored in output FIFO405is, however, less than the another ungate threshold, then clock gating for clock domain407may be disabled (block610). In various embodiments, the clock signal coupled to post-blend FIFO404and any other functional units within clock domain407may be ungated. Once clock gating has been disabled for clock domain407, then the method may proceed from block606as described above.

Although the operations of the method illustrated inFIG. 6are depicted as being performed in a serial fashion, in other embodiments, one or more of the operations may be performed in parallel.

Turning toFIG. 7, a flow diagram depicting a method for operating a display processor, such as, e.g., display processor200, is illustrated. The method begins in block701. Pixel data for a new frame may then be received (block702). In various embodiments, the display processor may send a request for data via a communication bus, such as, bus220, for example. In response to the request, a memory, such as, e.g., memory120, may send the pixel data to the display processor via the same communication bus.

The method may then depend on a number of generic pipelines (also referred to herein as “processing pipelines”) are to be employed to process the newly received frame data (block703). When more than one generic pipeline is to be employed to process the received frame data, the method may conclude in block706.

If, however, a single generic pipeline is to be employed to process the received frame data, then a size of a line buffer of the active generic pipeline may be increased (block704). In some embodiments, a multiplex circuit, such as, e.g., multiplex circuit312, may be employed to allow a line buffer (e.g., line buffer304) of an inactive generic pipeline to receive information from a source outside the generic pipeline (e.g., input data309). For example, line buffer250of generic pipe201bas illustrated inFIG. 2, may receive data from a structured noise unit, or other suitable functional unit within generic pipe201a. Data stored in line buffer250of generic pipe201bmay then be routed back to a line buffer within generic pipe201a. By establishing the connection between the line buffers, an effective size, i.e., capacity to store data bits, of the line buffer of generic pipe201amay be increase by the size of line buffer250of generic pipe201b. In some embodiments, a line buffer with an increased storage capacity may allow for the storage of more than one of a frame, thereby reducing a number of fetches that may be performed by a given generic pipeline.

It is noted that the use of input buffers from inactive generic pipelines may also depend on a mode of operation of the active generic pipeline. For example, in some embodiments, increasing the size of the input buffer of the active generic pipeline may be in response to the active generic pipeline operating in a mode where scaling is not being performed (also referred to herein as a “no-scale mode”).

Once the size of the line buffer of the active generic pipeline has been increase, the received frame data may be processed (block705). In some embodiments, processing the frame data may include color space conversion, gamut adjust, and the like. The method may then conclude in block706. Changes to line buffer sizes may, in various embodiments, be reset at the end of processing data for a given frame, thereby allowing an inactive generic pipeline to be employed to process frame data for a subsequent frame.

It is noted that embodiment depicted inFIG. 7is merely an example. In other embodiments, different operations and different orders of operations are possible and contemplated.