Formation of nitrogen containing dielectric layers having an improved nitrogen distribution

Provided is a method for manufacturing a gate dielectric. This method, without limitation, includes subjecting a silicon substrate to a first plasma nitridation process to incorporate a nitrogen region therein. This method further includes growing a dielectric material layer over the nitrogen region using a nitrogen containing oxidizer gas, and subjecting the dielectric material layer to a second plasma nitridation process, thereby forming a nitrided dielectric material layer over the nitrogen region.

TECHNICAL FIELD

The present disclosure is directed, in general, to a method for manufacturing gate dielectric layers and, more specifically, to the formation of nitrided gate dielectric layers having an improved nitrogen distribution.

BACKGROUND

In certain semiconductor applications it is necessary to integrate dual gate oxide (DGO) thicknesses for associated transistor devices onto a single integrated circuit device. One motivation for performing DGO processing is that high performance transistors typically operate at lower voltages (e.g., 1.5 volts and below), and thus require thinner gate dielectric regions. Alternatively, devices that interface with most conventional external peripherals typically require higher operating voltages (e.g., 1.6 volts and above), and thus require thicker gate dielectric regions. When interfacing lower voltage high performance metal-oxide-semiconductor field-effect-transistors (MOSFETs) within a core of an integrated circuit, to higher voltage peripheral devices, input and output (I/O) buffers of the integrated circuit (IC) are typically designed to contain thicker gate dielectric regions that are compatible with the higher external peripheral device voltages.

For example, current microcontroller units (MCUs) and digital signal processors (DSPs) are integrating several different types of technology onto a single IC, such as high speed logic, power logic, static random access memory (SRAM), nonvolatile memory (NVM), embedded dynamic random access memory (DRAM), analog circuitry, and other devices and technologies. Many of these devices require different gate dielectric processing and different gate dielectric thicknesses to provide both lower voltage devices within the core of the device and higher voltage devices to interface with external peripheral devices.

As stated above, a DGO thickness structure generally includes thin gate dielectrics for high performance low voltage operation core devices, and thick gate dielectrics for low leakage high voltage operation I/O devices. As devices shrink, and to meet device requirements, even the thick gate dielectrics are getting thinner. This can cause increased leakage current for the devices, especially the high voltage devices having the thick gate dielectrics.

It has generally been accepted that the leakage current can be mitigated by introducing nitrogen atoms into the gate dielectrics to suppress leakage currents for both the thin and thick gates. One method of nitrogen atom introduction includes performing non-thermal nitridation (e.g., plasma or radical nitridation) on the gate dielectrics. Unfortunately, this and other methods of introducing the nitrogen atoms into the gate dielectrics tend to provide a non-uniform nitrogen profile in the gate dielectric, which results in reduced reliability. The non-uniformity, and thus reduced reliability, is particularly significant in thicker gate dielectrics, such as those used in the aforementioned high voltage devices.

FIG. 1depicts a graph100illustrating the nitrogen profile110and oxygen profile120in a gate dielectric manufactured using one of the aforementioned nitrogen inclusion techniques. In observing the nitrogen profile110in the gate dielectric layer, those skilled in the art understand focus should be made on the bulk region of the dielectric layer, wherein the nitrogen profile is a true representation of the dielectric layer. Accordingly, the bulk region of the dielectric layer is generally defined to exclude, on the lower limit, the first 0.3 nm of the dielectric layer, represented by the line130, and exclude, on the upper limit, anything past where the oxygen profile120decreases to about 50% of an average oxygen concentration within the bulk region, as represented by a line140.

A non-uniformity (N.U.) of the nitrogen concentration in the bulk region may be defined to quantify differences between films. The definition applied in the context of the present disclosure is

%⁢⁢N.U.=[N]max-[N]min[N]avg*100(1)
Using this equation, the non-uniformity of the nitrogen within the dielectric layer represented in the graph100is at least 135 percent if not 140 percent or more. As indicated above, this non-uniformity introduces reliability issues. The graph100thereby illustrates that conventional manufacturing techniques are generally unable to obtain nitrogen non-uniformity values in the bulk of the dielectric layers less than about 100 percent.

Accordingly, what is needed in the art is a method for improving the nitrogen distribution within a dielectric layer.

SUMMARY

To address the above-discussed deficiencies, provided is a method for manufacturing a gate dielectric. This method, without limitation, includes subjecting a silicon substrate to a first plasma nitridation process to incorporate a nitrogen region therein. This method further includes growing a dielectric material layer over the nitrogen region using a nitrogen and oxygen containing fluid, and subjecting the dielectric material layer to a second plasma nitridation process, thereby forming a nitrided dielectric material layer over the nitrogen region.

Also provided is a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, in one embodiment, includes: 1) providing a substrate having a high voltage device region and a lower voltage device region, 2) subjecting the high voltage device region to a first plasma nitridation process to incorporate a nitrogen region within the substrate, at least a portion of the low voltage device region being protected from the first plasma nitridation process using a protective layer, 3) forming a first dielectric material layer over the nitrogen region using a nitrogen and oxygen containing fluid, 4) forming a second dielectric material layer over the substrate in the lower voltage device region after removing the protective layer, 5) subjecting the first dielectric material layer and the second dielectric material layer to a second plasma nitridation process, thereby forming a first nitrided dielectric material layer in the high voltage device region and a second nitrided dielectric material layer in the lower voltage device region, 6) forming a gate electrode material layer over the first nitrided dielectric material layer and the second nitrided dielectric material layer, and 7) patterning the gate electrode material layer, first nitrided dielectric material layer and the second nitrided dielectric material layer into a first gate structure in the high voltage device region and a second gate structure in the lower voltage device region.

Additionally provided is a semiconductor device. The semiconductor device may include a substrate having a high voltage device region and a lower voltage device region. The semiconductor device may additionally include a first gate structure located over the high voltage device region, the first gate structure including a nitrogen region located within the substrate, a first nitrided gate dielectric layer, and a first gate electrode layer. In this embodiment a bulk portion of the first nitrided gate dielectric layer has a uniform nitrogen concentration above about 9 atomic percent. The semiconductor device may also include a second gate structure located over the lower voltage device region, the second gate structure including a second nitrided gate dielectric layer and a second gate electrode layer.

DETAILED DESCRIPTION

FIG. 2illustrates a semiconductor device200manufactured in accordance with the disclosure. The device200initially includes a semiconductor substrate210. The substrate210, in the embodiment ofFIG. 2, has isolation structures215located therein. The structures215may be any isolation structures used in semiconductor devices, including shallow trench isolation structures, field oxide isolation structures, etc.

As is illustrated inFIG. 2, the structures215divide the device200into first and second transistor device regions. More particularly in the embodiment ofFIG. 2, the structures215divide the device200into a high voltage device region220and a lower voltage device region250. The term “high voltage device region”, as defined herein, means a device operating at voltages of about 1.6 volts and above. Additionally, the term “lower voltage device region”, as defined herein, means a device operating at voltages of about 1.5 volts and below. Accordingly, the high voltage device region220might be configured to provide a low leakage input/output (I/O) device, wherein the lower voltage device region250might be configured to provide a high performance core device. It is to be appreciated that the single high and lower voltage device regions220,250, are provided for illustrative purposes, and that the device200may include a plurality of the high voltage device regions220and lower voltage device regions250without departing from the disclosure.

The high voltage device region220illustrated inFIG. 2initially includes a gate structure230. The gate structure230includes a thin nitrogen region231located within the substrate210. The gate structure230additionally includes the nitrided gate dielectric layer233. Because the gate structure230forms a part of what will ultimately be a high voltage structure, the gate dielectric layer233tends to comprise a thick gate dielectric. For example, the gate dielectric layer233in the high voltage device region220might have a thickness ranging from about 1.5 nm to about 3.5 nm, or greater. Nevertheless, other thicknesses outside this range could be used.

The nitrided gate dielectric layer233can be an oxide (e.g., silicon dioxide (SiO2)) or a dielectric material suitable for operating as a gate dielectric structure of a transistor device. Since the nitrided gate dielectric layer233is relatively thin in comparison to conventional thick gate dielectric layers, nitrogen atoms have been introduced into the gate dielectric layer233, for example to suppress leakage currents associated with the operation of the gate structure230. The nitrogen atoms can be introduced into the nitrided gate dielectric layer233using a number of different processes. However, in the embodiment ofFIG. 2the nitrogen atoms are introduced into the nitrided gate dielectric layer233using a plasma (e.g., radical) nitridation process. A nitrided gate dielectric, such as silicon oxynitride, may result after introducing the nitrogen atoms into the nitrided gate dielectric layer233.

Turning for a moment toFIG. 3, shown is a graph300illustrating the nitrogen concentration and oxygen concentration in a gate dielectric manufactured in accordance with the principles of the disclosure. The gate dielectric is representative of the nitrided gate dielectric layer233, and will be referred to as such in the discussion of the graph300. A nitrogen profile310, portrayed as circles, shows the measured concentration of nitrogen, [N], with increasing depth in the gate dielectric layer233. An oxygen profile320, portrayed as triangles, shows the measured concentration of oxygen, [O], with increasing depth in the gate dielectric layer233. Both the nitrogen profile310and oxygen profile320were, in this embodiment, determined by time-of-flight secondary ion mass spectrometry (ToF-SIMS).

For purposes of this discussion, the nitrided gate dielectric layer233may be characterized as having a surface region and a bulk region. Each of the surface region and the bulk region may be defined in relation to the surface of the gate dielectric layer233and the oxygen profile320. The surface region is defined to begin at the surface of the gate dielectric233, and extend to a depth of about 0.3 nm, as indicated by a line330. The bulk region extends from about 0.3 nm until the oxygen profile320decreases to about 50% of an average oxygen concentration within the bulk region, as indicated by a line340. The depth corresponding to the intersection of the oxygen profile320and the line340, as indicated by a line350, is the lower extent of the bulk region, or about 2.5 nm in the graph300. Those skilled in the art will appreciate that the thickness of the bulk region will depend on the total thickness of the gate dielectric layer233.

A non-uniformity (N.U.) of the nitrogen concentration in the bulk region may be defined to quantify differences between films. The definition applied in the context of the present disclosure is

%⁢⁢N.U.=[N]max-[N]min[N]avg*100(2)
For the purposes of the disclosure, a non-uniformity less than about 35 percent is considered to be substantially uniform. Many of the conventional techniques for manufacturing the gate dielectrics provide a nitrogen non-uniformity of 100 percent or greater. Thus defined, the non-uniformity of the nitrogen concentration of the bulk region of the gate dielectric233in the graph300is computed to be less than about 20%, which is significantly below that which is generally attainable using conventional methods, and substantially below the upper level of what is considered uniform (e.g., 35 percent and above). Accordingly, the inventive methodology of the present disclosure is capable of providing gate dielectrics having substantially uniform nitrogen concentrations therein.

Not only does the gate dielectric layer233have a uniform nitrogen concentration, as defined above, the average uniform nitrogen concentration in certain embodiments is at or above about 9 atomic percent. For example, in the graph300ofFIG. 3, the average uniform nitrogen concentration is at least about 12 atomic percent. This is in direct contrast to previous gate dielectrics, including some previous gate dielectrics that might have had a uniform nitrogen concentration, which would have had nitrogen concentrations of about 8 atomic percent or below. It is believed that this feature (e.g., the average uniform nitrogen concentration at or above 9 atomic percent) is unique to the method for manufacturing the gate dielectric disclosed herein.

Returning toFIG. 2, the gate structure230also includes a gate electrode layer235disposed over the nitrided gate dielectric layer233. The gate electrode layer235may comprise, without limitation, polysilicon, amorphous silicon, germanium, silicon-germanium, or metal. Sidewall spacers238of a suitable insulating material may be disposed adjacent to the sidewalls of the nitrided gate dielectric layer233and gate electrode layer235. Source/drain regions240, which in one embodiment are conventional, may be formed within the substrate210proximate the gate structure230.

The lower voltage device region250may include a second gate structure260. As is illustrated inFIG. 2, the gate structure260may include a second nitrided gate dielectric layer263located over the substrate210. Because the gate dielectric layer263forms a part of what will ultimately be a high performance lower voltage structure, the gate dielectric layer263tends to comprise a thinner gate dielectric. For example, the gate dielectric layer263in the lower voltage device region250could have a thickness ranging from about 0.8 nm to about 1.4 nm. Nevertheless, other thicknesses outside this range could be used.

The second gate dielectric layer263may also be an oxide (e.g., silicon dioxide (SiO2)) or a dielectric material suitable for operating as a gate dielectric structure of a transistor device. In the embodiment ofFIG. 2, nitrogen atoms have also been introduced into the gate dielectric layer263to suppress leakage currents associated with the operation of the gate structure260. The nitrogen atoms can be introduced into gate dielectric263using a similar process as used to introduce the nitrogen atoms into the gate dielectric layer233. A nitrided gate dielectric, such as silicon oxynitride, may also result after introducing the nitrogen atoms into the gate dielectric layer263. As leakage is often more problematic for high voltage devices, certain embodiments of the present disclosure may exist wherein the gate dielectric layer263does not contain the nitrogen therein.

The gate structure260also includes a second gate electrode layer265disposed over the gate dielectric layer263. The gate electrode265may comprise, without limitation, polysilicon, amorphous silicon, germanium, silicon-germanium or metal. Sidewall spacers268of a suitable insulating material may be disposed adjacent to the sidewalls of the gate dielectric layer263and gate electrode layer265. Source/drain regions270, in certain embodiments conventional, may also be formed within the substrate210proximate the gate structure260.

While not illustrated, the source/drain regions240and270can also include source/drain extensions that are generally aligned with and partially beneath the respective edges of the gate electrode layers235and265. Those skilled in the art will understand and appreciate that the high and lower voltage device regions220,250can include either P type or N type transistors. The source/drain regions240and270can be formed as N or P type regions by doping with boron, arsenic or other appropriate doping materials, as known in the art.

FIGS. 4-11illustrate how one skilled in the art might manufacture a semiconductor device in accordance with this disclosure. WhileFIGS. 4-11are specifically directed to the manufacture of a semiconductor device,FIGS. 4-11also illustrate, in a broad sense, how one skilled in the art might manufacture a gate dielectric with improved nitrogen uniformity in accordance with the disclosure. Thus, a method for manufacturing a gate dielectric is discussed within the confines of discussing how one skilled in the art might manufacture a semiconductor device with respect toFIGS. 4-11. Nevertheless, while each of these ideas is discussed and illustrated using a single set of drawings, neither should be limiting on the other.

FIG. 4illustrates a semiconductor device400at an initial stage of formation. The device400illustrated inFIG. 4initially includes a substrate410. The substrate410may, in an embodiment, be any layer located in the device400, including a wafer itself or a layer located above the wafer (e.g., epitaxial layer). Moreover, the substrate410is generally formed from a semiconductor material, such as silicon or polysilicon. However, the substrate410may also be formed from other materials such as gallium arsenide, germanium, silicon-germanium, epitaxial formations, silicon carbide, indium phosphide, silicon-on-insulator substrates (SOI), strained silicon substrates, and/or other semiconductor substrate materials. Nevertheless, in the illustrative embodiment shown, the substrate410comprises an epitaxial silicon layer.

Formed within the substrate410and separating the device400into a high voltage device region420and a lower voltage device region460are isolation structures415. The structures415illustrated inFIG. 4happen to be shallow trench isolation structures; nevertheless, other embodiments exist wherein the isolation structures differ from those shown. For example, other known embodiments use field oxide isolation structures in place of the shallow trench isolation structures shown.

As just mentioned, the structures415in the embodiment ofFIG. 4separate the devices. The high voltage device region420might include transistor devices configured to operate at high voltages (e.g., about 1.6 volts and above) and the lower voltage device region460might include transistor devices configured to operate at lower voltages (e.g., about 1.5 volts and below).

The device400additionally includes a protective layer470exposing the high voltage device region420and protecting the lower voltage device region460. The protective layer470, in the embodiment shown, comprises an oxide. For example, an oxide having a thickness of at least about 10 nm may be formed (e.g., grown in one embodiment) on the substrate410and subsequently patterned to result in the protective layer470. While an oxide is used in the embodiment ofFIG. 4, other materials might also be used. Those skilled in the art understand the myriad of processes that might be used to form the protective layer470, including the growth of the layer.

FIG. 5illustrates the device400ofFIG. 4after subjecting it to a plasma (e.g., radical) nitridation process510. As the protective layer470protects the lower voltage device region460, the plasma nitridation process510forms a nitrogen region520within the substrate410in the high voltage device region420. As one might expect, a small amount of nitrogen may reside in the upper surface of the layer470after conducting the process510.

The specific conditions of the plasma nitridation process510may vary. However, one embodiment might use an effective RF power ranging from about 500 watts to about 1500 watts, a pressure ranging from about 10 mTorr to about 100 mTorr, a temperature ranging from about room temperature to about 200° C., a gas flow of nitrogen ranging from about 50 sccm to about 500 sccm, and for a period of about 30 seconds to about 90 seconds. However, another embodiment might use an effective microwave plasma power ranging from about 1000 watts to about 2000 watts, a pressure ranging from about 50 mTorr to about 200 mTorr, a temperature ranging from about 200° C. to about 500° C., a gas flow of nitrogen ranging from about 10 sccm to about 100 sccm, a gas flow of argon ranging from about 500 sccm to about 1500 sccm, and for a period of about 30 seconds to about 90 seconds. Nevertheless, other processing conditions could also be used.

What results is the nitrogen region520. The nitrogen region520, in one embodiment, has an average nitrogen concentration of at least about 1×1016 atoms/cm3, and in another embodiment from about 2×1016 atoms/cm3 to about 5×1016 atoms/cm3. As indicated above, the high nitrogen concentration of the nitrogen region520can be instrumental to the uniform nitrogen concentration that will ultimately result in the first nitrided gate dielectric layer1115(FIG. 11). For example, the nitrogen concentration of the nitrogen region520helps define the final nitrogen concentration in the first nitrided gate dielectric layer1115. Nevertheless, other nitrogen concentrations outside of the above-disclosed ranges could also be used.

FIG. 6illustrates the device400ofFIG. 5after forming a first dielectric material layer610over the nitrogen region520in the high voltage device region420. In the embodiment ofFIG. 6, the layer610does not form within the lower voltage device region460because the lower voltage device region460is being protected by the protective layer470. The layer610may have a thickness ranging from about 1.5 nm to about 3.5 nm, among others, while remaining within the purview of the disclosure.

The layer610may be formed in many different ways; however, in the embodiment ofFIG. 6, it is formed using a nitrogen containing oxidizer gas. For instance, in one embodiment the layer610might be grown using nitrous oxide (N2O) gas. In an alternative embodiment, the layer610might be grown using nitric oxide (NO) gas, or a mixture of the above gases with an inert gas. The inclusion of the nitrogen helps reduce the removal of any nitrogen from the interface of the layer610and the nitrogen region520. In one example embodiment, the layer610is grown in the N2O ambient using the following processing conditions: a pressure ranging from about 5 Torr to about 500 Torr, a temperature ranging from about 1050° C. to about 1150° C., and for a period of about 30 seconds to about 90 seconds. Nevertheless, other formation techniques and processing conditions might be used to form the layer610.

FIG. 7illustrates the device400ofFIG. 6after removing the protective layer470to expose the lower voltage device region460. In the example embodiment ofFIG. 7, the protective layer470is removed by patterning photoresist over the high voltage device region420and then etching the protective layer470from the substrate410in the lower voltage device region460. The photoresist would then be removed from the high voltage device region420. Nevertheless, those skilled in the etching art would understand the specifics needed to appropriately remove the protective layer470.

FIG. 8illustrates the device400ofFIG. 7after forming a second dielectric material layer820over the substrate410in the lower voltage device region460. In one embodiment, a wet chemical cleanup is performed on the substrate410prior to forming the layer820. The wet chemical cleanup can include a silicon surface cleaning process, such as an RCA (Radio Corporation of America) clean and/or a SPM (sulfuric acid-hydrogen peroxide-water solution) clean. The RCA clean is the industry standard for removing contaminants from wafers. The RCA cleaning procedure generally has three major steps (e.g., organic clean, oxide strip and ionic clean) used sequentially. However, those skilled in the art would be familiar with a variety of different wet chemical cleanup procedures that could be employed to clean the substrate410prior to the formation of the layer820.

The layer820may be formed using a variety of different processes. However, in the embodiment ofFIG. 8the layer820is formed using an oxidation process. The layer820may, in one embodiment, have a thickness of about 0.8 nm to about 1.4 nm, and be formed by a wet and/or dry thermal oxidation processing. It is to be appreciated that alternate methodologies can be employed to form the layer820. For example, any technique suitably used to form the layer610might be used to form the layer820.

In the example embodiment ofFIG. 8, the high voltage device region420is subjected to the same oxidation process as the lower voltage device region460. In this embodiment, a thickness of the layer610increases, ultimately becoming layer810. As one would expect, the layer810is formed in part by the oxidation process associated withFIG. 6and in part by the oxidation process associated withFIG. 8.

FIG. 9illustrates the device400ofFIG. 8after subjecting the layer810and the layer820to a second plasma nitridation process910. The process conditions for the second plasma nitridation process910may vary depending on a number of different criteria. However, in one example embodiment, the second plasma nitridation process910might use an effective RF power ranging from about 700 watts to about 1500 watts, a pressure ranging from about 10 mTorr to about 20 mTorr, a temperature ranging from about room temperature to about 400° C., and a gas flow of nitrogen ranging from about 100 sccm to about 500 sccm, for a period of about 10 seconds to about 60 seconds. Nevertheless, other processing conditions could also be used.

What results are a first nitrided dielectric material layer920in the high voltage device region420and a second nitrided dielectric material layer930in the lower voltage device region460. Since the second nitridation process910is a relatively gentle plasma condition, it tends to incorporate nitrogen on the top surface of the first nitrided dielectric material layer920. Nevertheless, it generally extends into a portion of the previous layer520.

Accordingly, after the completion of the second nitrided dielectric material layer930(e.g., oxidation, radical nitridation, and post-radical treatment anneal thereof) the nitrogen concentration in the layer520approaches the nitrogen concentration in the layer920. In the embodiment ofFIG. 9the first and second layers920,930are silicon oxynitride dielectric layer. This, however, obviously depends on the material that the previous layers810,820comprised prior to the second plasma nitridation process910. As the layers810,820may comprise different materials, the resulting layers920,930may also.

FIG. 10illustrates the device400ofFIG. 9after forming a conformal (e.g., blanket) layer of gate electrode material1010over the first and second nitrided dielectric material layers920,930. The layer1010may, depending on its composition, be formed using any suitable technique. For example, among others, the layer1010may be formed using chemical vapor deposition (CVD) techniques, such as low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD). In those embodiments wherein the layer1010comprises amorphous silicon, germanium, or silicon-germanium, standard deposition techniques may be employed. In those embodiments wherein the layer1010comprises a metal, standard sputtering techniques may be employed. The layer1010, in one example embodiment, has a thickness ranging from about 80 nm to about 120 nm, but should not be limited to this thickness.

FIG. 11illustrates the device400ofFIG. 10after patterning the layer of gate electrode material1010and first and second nitrided dielectric material layers920,930, resulting in a first gate structure1110located within the high voltage device region420and a second gate structure1120located within the lower voltage device region460. As one would expect, the first gate structure1110includes a nitrogen region1113, a first nitrided gate dielectric layer1115and a first gate electrode layer1118. Additionally, the second gate structure1120includes a second nitrided gate dielectric layer1123and a second gate electrode layer1128.

As is clearly illustrated, the first nitrided gate dielectric layer1115is thicker than the second nitrided gate dielectric layer1123. Both the first and second nitrided gate dielectric layers1115,1123may have improved nitrogen uniformities therein. Additionally, the average nitrogen concentrations in the first and second nitrided gate dielectric layers1115,1123may vary from each other. After completing the device shown inFIG. 11, the manufacturing of the semiconductor device400would tend to continue in a standard manner, ultimately resulting in a device similar to that illustrated inFIG. 2.

FIG. 12illustrates an integrated circuit (IC)1200incorporating a high voltage device region1210and a lower voltage device region1220formed according to the disclosure. The IC1200may include MOS, BiCMOS or bipolar components, and may further include passive components, such as capacitors, inductors or resistors. It may also include optical components or optoelectronic components. Those skilled in the art are familiar with these various types of components and their manufacture. The IC1200may also be a dual-voltage IC, comprising transistors operating with difference threshold voltages. The particular embodiment illustrated inFIG. 12is a dual-voltage IC, as reflected by the high voltage device region1210and lower voltage device region1220.

Dielectric layers1230may be fabricated over the high voltage device region1210and lower voltage device region1220using standard means. Additionally, interconnect structures1240are located within the dielectric layers1230to interconnect various components, thus forming the operational integrated circuit1200. It will be apparent to one skilled in the art that several variations of the exemplary interconnect architecture may exist.

Those skilled in the art to which the disclosure relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described embodiments without departing from the scope of the disclosure.