Multi-output voltage converter with switching arrangement and method for voltage conversion

A voltage converter (10) comprises an input (11) for receiving an input voltage (VIN), a first output (12) for providing a first output voltage (VPOS) and a second output (13) for providing a second output voltage (VNEG). The first output voltage (VPOS) and the second output voltage (VNEG) have opposite polarities. A switching arrangement (14) of the voltage converter (10) is designed to provide energy to an inductor (15) in a charging phase (A) of operation and to provide energy from the inductor (15) to the first output (12) and, via a flying capacitor (16), to the second output (13) in a discharging phase of operation. The first duration (t1) of the charging phase (A) of operation is controlled such that the difference between a first predetermined value and the sum of the absolute value of the first output voltage (VPOS) and of the second output voltage (VNEG) is minimized.

RELATED APPLICATIONS

This application claims the priority of European application no. 10015856.7 filed Dec. 20, 2010, the entire content of which is hereby incorporated by reference.

BACKGROUND OF THE INVENTION

A dual output converter generates a first and a second output voltage. A boost converter provides output voltages which have a higher value than an input voltage. Contrary to that a buck converter generates output voltages with values which are lower than the value of the input voltage.

Document DE 10206032418 A1 refers to a voltage converter comprising an inductor and four switches. The voltage converter generates a first and a second output voltage.

Document US 2009/0167264 A1 is related to a converter usable for dual voltage supply. The converter comprises an inductor, a first and a second rectifier element as well as a positive and a negative supply output.

Document “Single Boost Converter Builds Dual Polarity Supply”, Y. Sharma, Power Electronics Technology, September 2006, pp 42-46 describes a boost converter generating a positive and a negative voltage by means of an inductor and a charge-pump capacitor. During one phase of operation energy is stored in the inductor. The duration of this phase of operation only depends on a comparison of the first output voltage and a reference voltage.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a voltage converter and a method for voltage conversion with a high efficiency.

In one embodiment, a voltage converter comprises an input, a first and a second output as well as a switching arrangement.

The input of the voltage converter is designed for receiving an input voltage and providing the input voltage to the switching arrangement. The first output of the voltage converter is designed for providing a first output voltage. Moreover, the second output of the voltage converter is designed for providing a second output voltage. The first and the second output voltage have opposite polarities. The switching arrangement is designed to provide energy to an inductor in a charging phase of operation and to provide energy from the inductor to the first output and, via a flying capacitor, to the second output in a discharging phase of operation. The first duration of the charging phase of operation is controlled such that the difference between a first predetermined value and the sum of the absolute value of the first output voltage and of the absolute value of the second output voltage is minimized.

During the charging phase of operation, energy is advantageously provided to the inductor through the input of the voltage converter. The switching arrangement receives the input voltage and converts the input voltage into the first and the second output voltage. The switching arrangement provides the first output voltage to the first output of the voltage converter and the second output voltage to the second output of the voltage converter. The first duration is controlled such that the energy provided to the voltage converter is sufficient to generate the first and the second output voltage with their predetermined values. Thus, by the exact calculation of the first duration, it is avoided that the energy that is provided to the voltage converter is too high. This increases the efficiency of the voltage conversion.

In an embodiment, the first and the second output voltage have opposite polarities with respect to a ground potential that can be tapped at a reference potential terminal. The first output voltage is provided between the first output and the reference potential terminal. The second output voltage is provided between the second output and the reference potential terminal.

In an embodiment, the first output voltage has a positive polarity with respect to the ground potential at the reference potential terminal. The second output voltage has a negative polarity with respect to the ground potential at the reference potential terminal.

In an embodiment, in the discharging phase of operation, energy is provided from the inductor via the first output to a first storage capacitor and a first load. The first storage capacitor is arranged between the first output and the reference potential terminal. Moreover, in the discharging phase of operation, energy is provided from the inductor to a second storage capacitor and a second load via the flying capacitor and the second output. The second storage capacitor is arranged between the second output and the reference potential terminal.

In an embodiment, the discharging phase of operation of the switching arrangement comprises a positive and a negative discharging phase. The positive and the negative discharging phase are designed for distributing the energy that is provided to the voltage converter to the first and to the second output. The second duration of the positive discharging phase is controlled such that a difference between the first output voltage and a predetermined value of the first output voltage is minimized. The third duration of the negative discharging phase is controlled such that the difference between the second output voltage and the predetermined value of the second output voltage is minimized.

In an embodiment, the inductor and the flying capacitor are connected in series. The input of the voltage converter is coupled to a first terminal of the inductor. A second terminal of the inductor is connected to a first electrode of the flying capacitor. The first electrode of the flying capacitor is coupled via a first switch of the switching arrangement to the reference potential terminal. A third switch of the switching arrangement couples a second terminal of the flying capacitor to the reference potential terminal. The first and the third switch can be implemented as transistors, such as field-effect transistors.

In an embodiment, a second switch of the switching arrangement couples the second terminal of the inductor to the first output. A fourth switch of the switching arrangement couples the second electrode of the flying capacitor to the second output terminal. The second and the fourth switch can be implemented as transistors, preferably as field-effect transistors, or as rectifiers, such as diodes.

In an embodiment, the maximum voltage which is applied to one of the switches is equal to the absolute value of the first output voltage or to the absolute value of the second output voltage. Thus, for the generation for example of +5 V and

−5 V output voltages, transistors which provide an isolation of 5 V are suitable. This leads to a low cost for production. Resulting from the low voltage stress, a reduced size of the power transistor respectively power transistors can be used. These margins of the maximum voltages improve efficiency, since the voltage swings are limited.

The voltage converter can be designed such that the inductor current which flows through the inductor is reduced. Thus, the voltage is converted with a high efficiency. In addition, the high efficiency leads to the capacity to drive large output currents which supply the load. The inductor preferably is designed as a coil.

In an embodiment, a semiconductor body comprises the voltage converter, wherein the inductor and the flying capacitor are external devices that are coupled to the semiconductor body. Thus, the voltage converter besides the inductor and the flying capacitor is arranged on a first area of the semiconductor body. A single semiconductor body can comprise the voltage converter with the exception of the inductor and the flying capacitor.

In an embodiment, a method for voltage conversion comprises converting an input voltage into a first and a second output voltage. The first output voltage and the second output voltage have opposite polarities. The conversion is performed by providing energy to an inductor in a charging phase of operation and providing energy from the inductor to the first output at which the first output voltage is provided and, via a flying capacitor, to the second output at which the second output voltage is provided in a discharging phase of operation. The first duration of the charging phase of operation is controlled such that the difference between a first predetermined value and the sum of the absolute value of the first output voltage and of the absolute value of the second output voltage is minimized.

In an embodiment, the low peak-to-peak inductor current ripple requires only a low inductivity value of the inductor. The small average inductor current makes it possible to use a small inductor. The method of zero voltage switching can be applied for further improvement of the efficiency.

DETAILED DESCRIPTION OF THE DRAWINGS

FIG. 1Ashows an exemplary embodiment of a voltage converter according to the principle presented. The voltage converter10comprises an input11and a first and a second output12,13. A switching arrangement14couples the input11to the first and the second output12,13. The switching arrangement14comprises an inductor15and a flying capacitor16. The inductor15and the flying capacitor16are connected in series. The input11is coupled to a first terminal of the inductor15. A second terminal of the inductor15is coupled via a first switch17of the switching arrangement14to a reference potential terminal18. A second switch19of the switching arrangement14couples the second terminal of the inductor15to the first output12. A first electrode of the flying capacitor16is permanently connected to the second terminal of the inductor15. A third switch20of the switching arrangement14couples a second terminal of the flying capacitor16to the reference potential terminal18. A fourth switch21of the switching arrangement14couples the second electrode of the flying capacitor16to the second output terminal13.

A first storage capacitor22is arranged between the first output12and the reference potential terminal18. Correspondingly, a second storage capacitor23is arranged between the second output13and the reference potential terminal18. A first load resistor24couples the first output12to the reference potential terminal18and a second load resistor25couples the second output13to the reference potential terminal18. The first and the second load resistor24,25simulate a load which is connected to the first and to the second output12,13.

Moreover, the voltage converter10comprises a feedback unit26. The feedback unit26comprises a first and a second controlling amplifier27,28. A first input of the first controlling amplifier27is coupled to the first output12. A second input of the first controlling amplifier27is coupled via a first reference voltage source29to the reference potential terminal18. The second controlling amplifier28has a first input which is coupled to the second output13. A second input of the second controlling amplifier28is coupled via a second reference voltage source30to the reference potential terminal18. The first and the second controlling amplifier27,28can be realized as operational transconductance amplifiers, abbreviated OTA.

Further on, the voltage converter10uses a voltage divider31between the first output12and the second output13. The feedback unit26comprises the voltage divider31. The voltage divider31couples the first and the second output12,13to the first input of the first controlling amplifier27and to the first input of the second controlling amplifier28. The voltage divider31comprises a first, a second and a third resistor32to34. The first, second and third resistor32,33,34are connected in series. The first resistor32is arranged between the first output12and the first input of the first controlling amplifier27. Similarly, the third resistor34is arranged between the second output13and the first input of the second controlling amplifier28. The second resistor32couples the first resistor32to the third resistor34.

Further on, the feedback unit26comprises an adding unit35with two input terminals which are connected to an output of the first controlling amplifier27and to an output of the second controlling amplifier28. In addition, a subtracting unit36has two inputs. A first input of the subtracting unit36is connected to the output of the first controlling amplifier27and a second input of the subtracting unit36is connected to the output of the second controlling amplifier28. The first input of the subtracting unit36is the positive input and the second input of the subtracting unit36is the negative input. Thus, the adding unit35has one output and the subtracting unit36has also one output which form the two outputs of the feedback unit26.

Furthermore, the voltage converter10comprises a control circuit37. Two inputs of the control circuit37are connected to the two outputs of the feedback unit26. A first output of the control circuit37is connected to a control terminal of the first switch17. Correspondingly, a second, a third and a fourth output of the control circuit37are connected to the control terminals of the second, third and fourth switch19,20,21. The control circuit37comprises a first sub-circuit38having an input that is connected to the output of the subtracting unit36. Furthermore, the control circuit37comprises a second sub-circuit39having an input that is connected to the output of the adding unit35. A controller40of the control circuit37is connected on its input side to the first and to the second sub-circuit38,39. The output side of the controller40is connected to the first, second, third and fourth output of the control circuit37.

Moreover, the control circuit37comprises a clock input terminal. An oscillator41of the voltage converter10is connected to the clock input terminal of the control circuit37. A current sensor42is arranged such that the current sensor42measures the inductor current ILC flowing through the inductor15. An output of the current sensor42is connected to a sensing input of the control circuit37. The current sensor42is arranged between the input11and the first terminal of the inductor15.

An input voltage VIN is provided to the input11. The input voltage VIN is applied between the input11and the reference potential terminal18. A ground potential is tapped at the reference potential terminal18. A first output voltage VPOS can be tapped-off at the first output12. Thus, the first output voltage VPOS is provided between the first output12and the reference potential terminal18. The first output voltage VPOS has a positive polarity with respect to the ground potential at the reference potential terminal18. A second output voltage VNEG is tapped-off at the second output13. Similarly, the second output voltage VNEG is applied between the second output13and the reference potential terminal18. The second output voltage VNEG has a negative polarity with respect to the ground potential at the reference potential terminal18. A first, a second, a third and a fourth control signal S1, S2, S3, S4is generated by the control circuit37by means of the controller40and is provided to the control terminals of the first, second, third and fourth switch17,19,20,21, respectively. The voltage converter10comprises a charging phase A and a discharging phase of operation. The discharging phase is divided into a positive and a negative discharging phase of operation B, C. In the charging phase A of operation, energy is stored in the inductor15. In the positive discharging phase B, the energy that is stored in the inductor15is partially transferred to the first storage capacitor22. Thus, the first output voltage VPOS is increased in the positive discharging phase of operation B. The negative discharging phase C is used to provide energy to the second output13. In the negative discharging phase of operation C, energy is transferred from the inductor15to the flying capacitor16. During the charging phase A of operation, energy stored in the flying capacitor16is transferred to the second storage capacitor23.

In the charging phase A of operation, the first and the fourth switch17,21are closed and the second and the third switch19,20are open. In the positive discharging phase B of operation, the second switch19is closed and the first, the third and the fourth switch17,20,21are open. In the negative discharging phase C of operation, the third switch20is closed and the first, the second and the fourth switch17,19,21are open. The charging phase A of operation has the first duration t1. Similarly, the positive and the negative discharging phase B, C have the second and the third duration t2, t3. The oscillator41generates a clock signal SCL which is provided to the control circuit37. The clock signal SCL has a cycle time T. The cycle time T is constant. The cycle time T is equal to the sum of the durations of the charging phase A, the positive and the negative discharging phase B, C according to the following equation:
T=t1+t2+t3

The equation above is valid in a continuous conduction mode, wherein the inductor current ILC is continuous. In this mode, the inductor current ILC does for example not obtain the value zero.

The voltage divider31generates a first and a second divider voltage VB1, VB2. The first divider voltage VB1is generated at a node between the first and the second resistor32,33. Correspondingly, the second divider voltage VB2is provided at a node between the second and the third resistor33,34. The first divider voltage VB1is provided to the first input of the first controlling amplifier27. A first reference voltage VREF1is provided to the second input of the first controlling amplifier27. Similarly, the second divider voltage VB2is applied to the first input of the second controlling amplifier28. Further on, a second reference voltage VREF2is applied to the second input of the second controlling amplifier28. The first and the second reference voltage VREF1, VREF2are generated by the first and the second reference voltage source29,30, respectively.

The first inputs of the first and the second controlling amplifier27,28are inverting inputs. Thus, the second inputs of the first and the second controlling amplifier27,28are non-inverting inputs. A first voltage signal VC1at the output of the first controlling amplifier27depends on the difference between the first divider voltage VB1and the first reference voltage VREF1. Also a second voltage signal VC2at the output of the second controlling amplifier28depends on a difference of the second divider voltage VB2and second reference voltage VREF2. By the adding unit35the output signals VC1, VC2of the first and the second controlling amplifier27,28are added and a resulting second feedback signal V2is provided to the second sub-circuit39. The second sub-circuit39is designed for the control of the ratio of the second to the third duration t2:t3. The second feedback signal V2of the adding unit35is a function of the difference between the absolute value of the first output voltage VPOS and the absolute value of the second output voltage VNEG.

The subtracting unit36generates a first feedback signal V1which depends on the difference between the output signal of the first controlling amplifier27and the second controlling amplifier28. The first feedback signal V1of the subtracting unit36is provided to the first sub-circuit38. The first sub-circuit38is designed for the control of the first duration t1. The first feedback signal V1of the subtracting unit36is a function of the sum of the absolute value |VPOS| of the first output voltage VPOS and the absolute value |VNEG| of the second output voltage VNEG.

The sum of the voltages of the absolute value of the first output voltage VPOS and the absolute value of the second output voltage VNEG is regulated with the first duration t1. The difference between the absolute value of the first output voltage VPOS and the absolute value of the second output voltage VNEG is regulated with the ratio of the second duration divided by the third duration t2:t3. The first duration t1is increased by the control circuit37if the sum of the absolute value of the first output voltage VPOS and the absolute value of the second output voltage VNEG is smaller than the steady state value and vice versa. The ratio t2:t3decreases if the difference between the absolute value of the first output voltage VPOS and the absolute value of the second output voltage VNEG is more than the steady state value and vice versa. The first duration t1refers to the amount of time during the first switch17is on that means in a conducting state. During the first duration t1, also the fourth switch is on. The ripple of a power ground current may be equal to two times of the inductor current. The power ground current is the current with flows through a first and a second storage capacitor as well as a first and a second load resistor. The first, second and third durations t1, t2, t3are actively regulated by the control circuit37.

In an alternative embodiment, the fourth switch21is switched on for a shorter or longer duration than the first duration t1. If the fourth switch21is on before the first switch17and turned off after the first switch17turned off, then the first switch17is advantageously switched at a zero voltage across the first switch17.

In an alternative, not shown embodiment, the switching arrangement14comprises a fourth phase D with a fourth duration t4. Thus, the cycle time T can be calculated according to the following equation:
T=t1+t2+t3+t4,

wherein t4is the duration of the time for which the inductor current ILC remains zero. This mode of operation is a discontinuous conduction mode.

In an alternative embodiment, the voltage converter10does not comprise the current sensor42. Only a voltage mode control is used for the regulation of the first and the second output voltages VPOS, VNEG. In this case the inductor current ILC is not sensed.

In an alternative embodiment, the voltage converter10is operated in such a way that only the first output voltage VPOS is generated. In this case, the third duration t3is zero. Alternatively, only the second output voltage VNEG is generated. In that case, the second duration t2equals zero.

In an alternative, not shown embodiment, the voltage converter10uses the charging phase A as well as the positive and the negative discharging phase B, C, in the sequence A, C, B and not in the sequence A, B, C as shown in FIG.1Aa.

In an alternative embodiment, the first, second, third and fourth switch17,19,20,21are switched off for a predetermined duration before and after the switching cycle.

In an alternative, not shown embodiment, the inverting input and the non-inverting input of the first controlling amplifier27can be interchanged. Also the inverting input and the non-inverting input of the second controlling amplifier28can be interchanged.

In an alternative, not shown embodiment, the second and/or the fourth switch19,21are realized as rectifiers, such as diodes.

FIG. 1Bshows an alternative exemplary embodiment of a voltage converter according to the principle presented. The voltage converter according toFIG. 1Bis a further development of the voltage converter shown inFIG. 1A. The feedback unit26comprises a first and a second voltage divider50,51. The first voltage divider50comprises a series circuit of a fourth and a fifth resistor52,53. The series circuit of the fourth and the fifth resistor52,53couples the first output12to the reference potential terminal18. A node between the fourth and the fifth resistor52,53is connected to the first input of the first controlling amplifier27. The second voltage divider51comprises a series circuit of a sixth and a seventh resistor54,55. The series circuit of the sixth and the seventh resistor54,55is arranged between the second output13and the reference potential terminal18. A node between the sixth and the seventh resistor54,55is connected to the first input of the second controlling amplifier28.

The first voltage divider50generates the first divider voltage VB1and the second voltage divider51generates the second divider voltage VB2. Thus, the first divider voltage VB1and the second divider voltage VB2which are supplied to the first input of the first and the second controlling amplifier27,28can be calculated according to the following equations:
VB1=K1·|VPOS|andVB2=K2·|VNEG|,

wherein K1and K2are constant, |VPOS| is the absolute value of the first output voltage and |VNEG| is the absolute value of the second output voltage. Thus, the first and the second divider voltages VB1, VB2are independently generated for the first inputs of the first and the second controlling amplifier27,28. The voltage divider31ofFIG. 1Ais omitted. The voltage converter10according toFIG. 1Bshows the method of an independent feedback.

In an alternative, not shown embodiment, the first voltage divider50couples the first output12to a further reference potential terminal. Thus, the fifth resistor53is connected to the further reference potential terminal. A potential of the further reference potential terminal is different from the ground potential at the reference potential terminal18.

In an alternative, not shown embodiment, the second voltage divider51is arranged between the second output13and the further reference potential terminal or an additional reference potential terminal. Thus, the seventh resistor55is connected to the further reference potential terminal or the additional reference potential terminal. A potential at the additional reference potential terminal is different from the ground potential at the reference potential terminal18.

FIG. 1Cshows another exemplary embodiment of a voltage converter according to the principle presented. The voltage converter10according toFIG. 1Cis a further development of the voltage converters ofFIGS. 1A and 1B. The voltage converter10additionally comprises a first current source60which is arranged between the first output12and the reference potential terminal18. A first amplifier61has an output which is connected to a control input of the first current source60. A first input of the first amplifier61is coupled to the first output12. A second input of the first amplifier61is coupled via the first reference voltage source29to the reference potential terminal18.

Moreover, the current converter10comprises a second current source62. The second current source62is arranged between the second output13and the reference potential terminal18. A second amplifier63of the voltage converter10has an output which is connected to a control input of the second current source62. A first input of the second amplifier63is coupled to the second output13. A second input of the second amplifier63is coupled via the second reference voltage source30to the reference potential terminal18. Moreover, the voltage converter10comprises the first and the second voltage divider50,51as shown inFIG. 1B. The first and the second voltage divider50,51are coupled to the first inputs of the first and the second amplifier61,63.

A first input of the first controlling amplifier27is coupled to the first and the second output12,13. The voltage converter10comprises an additional voltage divider56having a first and a second divider resistor57,58. The additional voltage divider56is arranged between the first output12and the second output13. A node between the first and the second divider resistor57,58is connected to the first input of the first controlling amplifier27. The second input of the first controlling amplifier27is coupled via a third reference voltage source64to the second output13. Furthermore, the voltage converter10comprises a positive current sensor65. The positive current sensor65is designed to measure the first current IPC which flows through the first current source60. The positive current sensor65is arranged between the first current source60and the reference potential terminal18. An output of the positive current sensor65is coupled to the first input terminal of the second controlling amplifier28. A current reference source66couples the second input of the second controlling amplifier28to the reference potential terminal18. The first controlling amplifier27is connected to the first sub-circuit38. Similarly, the second controlling amplifier28is coupled to the input of the second sub-circuit39.

Moreover, the control circuit37comprises a third sub-circuit67and a change-over switch68. The output of the second sub-circuit39is connected to a first input of the change-over switch68. An output of the third sub-circuit67is connected to a second input of the change-over switch68. An output of the change-over switch68is connected to the controller40.

The first current source60is controlled such that a difference between the first divider voltage VB1and the first reference voltage VREF1is minimized. Similarly, the second current source62is controlled such that a difference between the second divider voltage VB2and the second reference voltage VREF2is minimized. A first amplifier signal SL1of the first amplifier61having a first amplification factor KA1and a second amplifier voltage SL2of the second amplifier63having a second amplification factor KA2can be calculated according to the following equations:
SL1=KA1·(VREF1−K1·|VPOS|) and
SL2=KA2·(K2·|VNEG|−VREF2)

The third reference voltage source64generates a third reference voltage VREF3. The first feedback signal V1which is applied to the first sub-circuit38can be calculated according to the following equation:
V1=K4·(VREF3−K3·(|VPOS|+|VNEG|)),

wherein K4is an amplification factor of the first controlling amplifier27. The positive current sensor65provides a positive current signal IPCS. The second feedback signal V2which is applied to the second sub-circuit39is calculated according to the following equation:
V2=K5·(IREF4−IPCS),
wherein K5the amplification factor of the second controlling amplifier28.

The sum of the absolute value of the first output voltage VPOS and of the absolute value of the second output voltage VNEG is regulated with the first controlling amplifier27. The first output voltage VPOS is regulated with the first current source60and the first amplifier61. The second output voltage VNEG is regulated by means of the second current source62and the second amplifier63.

A first current IPC flows through the first current source60. Similarly, a second current INC flows through the second current source62. If the first current IPC is not equal to the second current INC, then one current source of a group comprising the first and the second current source60,62is activated to balance the load which is connected to the first and to the second terminal12,13. A ground current IG flows from the first and the second load resistor24,25as well as the first and the second current source60,62to the reference potential terminal18. By means of the first and the second current source60,62a fine tuning of the values of the first and the second output voltage VPOS, VNEG can be achieved. The balancing results in a ground current IG with zero value.

If the controller40is connected via the change-over switch68to the third sub-circuit67, a fixed ratio t2:t3of the second duration t2to the third duration t3is used. In that case the first or the second current IPC, INC are in steady state and may be large resulting in a non-optimal efficiency. The first current IPC or the second current INC can be minimized by the second controlling amplifier28and the second sub-circuit39. By this regulation, the positive current signal IPCS of the first current sensor65is regulated to the current reference value IREF4which is provided by the current reference source66. The voltage converter10according toFIG. 1Cshows the method of load balancing.

In an alternative, not shown embodiment, the voltage converter10comprises a negative current sensor that measures the second current INC.

FIG. 1Dshows an exemplary embodiment of a voltage converter according to the principle presented. The voltage converter according toFIG. 1Dis a further development of the voltage converter shown inFIG. 1A to 1C. The voltage converter10comprises the first controlling amplifier27. The first input of the voltage controlling amplifier27is coupled to the first and to the second output12,13. The second input of the first controlling amplifier27is coupled via the third reference source64to the second output13. Moreover, the voltage converter10comprises the first and the second amplifier61,63. The inputs of the first and the second amplifier61,63are connected to the reference voltage sources29,30and are coupled to the first and to the second output12,13as shown inFIG. 1C.

The first controlling amplifier27is connected to the first sub-circuit38. A first and a second output of the first sub-circuit38are connected to the control terminal of the first and the fourth switch17,21. The control circuit37comprises a first and a second control switch70,71. The first control switch70couples the output of the first amplifier61to the second output of the control circuit37which is connected to the control terminal of the second switch19. Furthermore, the second control switch71couples the output of the second amplifier63to the third output of the control circuit37which is connected to the control terminal of the third switch20. A further output of the first sub-circuit38is connected to an input of the second sub-circuit39. The second sub-circuit is connected to the control terminals of the first and the second control switch70,71via two outputs of the second sub-circuit39. A first analog controller72comprises the first control switch70and the first amplifier61. A second analog controller73comprises the second control switch71and the second amplifier63.

The mode of operation of the voltage converter10according toFIG. 1Dcomprises the maximum of two phases. In the charging phase A, energy is provided to the inductor15, whereas in the discharging phase B′ the energy is provided both to the first and the second output12,13. The first and the fourth switch17,21are on in the charging phase A. The second and third switch19,20are open in the charging phase A. Thus, the charging phase A ofFIG. 1Dis equal to the charging phase A of theFIGS. 1A to 1C. In the discharging phase B′, the second and the third switch19,20are closed, whereas the first and the fourth switch17,21are open. The cycle time T is the sum of the first duration t1of the charging phase A and of the second duration t2of the discharging phase B′.

The first amplifier61provides the second control signal S2with an analog value. Similarly, the second amplifier63generates the third control signal S3with an analog value. Therefore, the second and the third switch19,20are regulated such that they obtain an open state, an closed state closed and states with a resistance value between open and closed. The second and the third switch19,20are controlled in an analog manner such that they obtain more than one resistance value between the resistance value at the open state and the resistance value at the closed state.

The sum of the absolute value of the first output signal VPOS and the absolute value of the second output voltage VNEG is regulated with the first controlling amplifier27and the first sub-circuit38by controlling the first duration t1. The first output voltage VPOS is regulated by operating the second switch19by means of the second control signal S2in the linear region of the second switch19. The second control signal S2has a voltage which is regulated during the discharging phase B′ with the first analog controller72comprising the first amplifier61and the first controller switch70. Similarly, the third control signal S3has the form of a voltage and is regulated during the positive discharging phase B′ with the second analog controller73comprising the second amplifier63and the second switch71. The voltage converter10according toFIG. 1Dshows the method of a linear switch operation.

In an alternative embodiment, the second control signal S2and/or the third control signal S3are applied for a smaller duration than the second duration t2. Thus, the second and/or the third control signal S2, S3are generated in the first part of the discharging phase B′ such that the second and the third switch19,20show a resistance between the open and the closed state of the switches, whereas in a second part of the discharging phase B′ the second and/or the third switch19,20are in an open state.

In an alternative embodiment, the first duration t1is fixed to some predetermined value. Thus, the first duration t1is not controlled by the first controlling amplifier27.

In an alternative embodiment, the fourth switch21is closed during a fourth duration t4which is longer than the first duration t1. Thus, the fourth switch21is closed before the first switch17is closed and the fourth switch21is opened after the first switch17is opened. The fourth duration t4is indicated in theFIG. 1D.

In an alternative, not shown embodiment, the second analog controller73generates the fourth control signal S4which is an analog signal instead of the third control signal S3during the fourth duration T4. The third control signal S3is a digital signal and is generated out of the first sub-circuit38.

In an alternative embodiment, only one of the first and the second analog controller72,73is active. Alternatively, none of the two analog controllers72,73is active.

In an alternative embodiment, the first duration t1is smaller than the fourth duration t4.

FIG. 1Eshows a further exemplary embodiment of a voltage converter according to the principle presented. The voltage converter according toFIG. 1Eis a further development of the voltage converter shown inFIG. 1A to 1B. The switching arrangement14comprises a series circuit of a first and a second additional switch80,81. The series circuit of the first and the second additional switch80,81is arranged in parallel to the second switch19. A node between the first and the second additional switch80,81is connected to a substrate of the second switch19. Moreover, the switching arrangement14comprises a series circuit of a first and a second further switch82,83. The series circuit of the first and the second further switch82,83is connected in parallel to the third switch20. Correspondingly, a node between the first and the second further switch82,83is connected to a substrate of the third switch20.

InFIG. 1E, a first diode84connects one terminal of the second switch19with the substrate of the second switch19. A second diode85connects a second terminal of the second switch19to the substrate of the second switch19. The first and the second diode84,85only represent the diodes between the source and the substrate and the drain and substrate respectively and are not realized as discrete and separate diodes. In case the first output voltage VPOS has a higher value in comparison to the voltage of the substrate of the second switch19, a current flows from the first output12to the substrate of the second switch19. In addition a third and a fourth diode86and87are shown inFIG. 1Ewhich represent the source to substrate diode and the drain to substrate diode of the third switch20.

The first, second, third and fourth switch17,19,20,21are realized as field-effect transistors. Preferably, the four switches are implemented as metal-oxide-semiconductor field-effect transistors, abbreviated MOSFET. The first and the fourth switch17,21can be realized as n-channel MOSFET. The second and the third switch19,20can be fabricated as p-channel MOSFET. The control circuit37that is not shown inFIG. 1Eis coupled on its output side to the control terminals of the first and second additional switch80,81and to the first and the second further switch82,83.

The two different cycles shown inFIG. 1Eare chosen if the first output voltage VPOS is larger than the absolute value of the second output voltage VNEG. In the upper embodiment of the cycle, the cycle comprises the charging phase A, the positive and the negative discharging phase B, C in such a sequence that the positive discharging phase B follows the charging phase A and the negative discharging phase C follows the positive discharging phase B. In that case a seventh signal X1is provided to the second additional switch81by the control circuit37such that the second additional switch is in an open state. An inverted seventh signal X1B which is provided to the first additional switch80is the inverse signal to the seventh signal X1. Thus, the inverted seventh signal X1B is provided to the first additional switch80with a value which sets the first additional switch80in a closed state during all phases of the cycle.

An eights signal X2is provided to the first further switch86which sets the first further switch82in an open state during the positive discharging phase B and in a closed state during the charging phase A and the negative discharging phase C. An inverted eights signal X2B is the inverted signal to the eights signal X2. The signal X2B is provided to the control terminal of the second further switch83. Thus, the second further switch83is in a closed state during the positive discharging phase B and in an open state during the charging phase A and the negative discharging phase C. The cycle comprises three intermediate phases D, E, F between the charging phase A and the positive discharging phase B. Furthermore, the cycle comprises two intermediate phases G, H between the positive and the negative discharging phase B, C. Additionally, the cycle comprises two further intermediate phases I, J between the negative charging phase C and the charging phase A. The values of the first, the second, the third, the fourth, the seventh and the eights control signal S1, S2, S3, S4, X1, X2are shown inFIG. 1E.

At the end of one phase, only one switch changes its state. This is not only valid for the charging phase A and the positive and the negative discharging phase B, C, but also for the intermediate phases.

In the lower embodiment, the cycle comprises the first, the second and the negative discharging phase A, B, C in such an order that the negative discharging phase C follows the charging phase A and the positive discharging phase B follows the negative discharging phase C. In this case also the seventh signal X1has a value which sets the second additional switch81in an open state and the first additional switch80in a closed state in all phases of the cycle.

The eights control signal X2is generated by the control circuit37in such a way that the first further switch82is in a closed state during the charging phase A and the negative discharging phase C and in an open state during the positive discharging phase B. The second further switch83is in an open state during the charging phase A and the negative discharging phase C and in a closed state during the positive discharging phase B. The cycle not only comprises the first, the second and the negative discharging phase A, B, C but also two intermediate phases between the charging phase A and the negative discharging phase C, two intermediate phases between the negative discharging phase C and the positive discharging phase B and three intermediate phases between the positive discharging phase B and the charging phase A.

According to the shown sequence of the first, second, third, fourth, the seventh and the eights control signal S1, S2, S3, S4, X1, X2, three of the four switches comprising the first, the second, the third and the fourth switch17,19,20,21have a zero voltage switching that means that these switches are switched at a point of time whereas approximately zero voltage is applied between the two terminals of the switches. The method of serial voltage switching will reduce the switching losses.

The control circuit37is designed such that it selects the cycle according to the two versions of the cycle according toFIG. 1Eor the two versions of the cycle ofFIG. 1Fdepending on a comparison of the absolute value of the first output signal VPOS and the absolute value of the second output signal VNEG. This leads to an improved efficiency of the voltage conversion.

FIG. 1Fshows a further exemplary embodiment of a voltage converter according to the principle presented. The voltage converter according toFIG. 1Fis a further development of the voltage converters shown inFIG. 1A to 1E. The two different cycles shown inFIG. 1Fare chosen if the first output voltage VPOS is smaller than the second output voltage VNEG. The operation is similar to the operation of the voltage converter10shown inFIG. 1E.

FIG. 1Gshows a further exemplary embodiment of a voltage converter according to the principle presented. The voltage converter according toFIG. 1Gis a further development of the voltage converters shown inFIG. 1A to 1F. The voltage converter10comprises a third output90and a fifth switch91which couples the second terminal of the inductor15to the third output90. A third storage capacitor92connects the third output90to the reference potential terminal18. A third load resistor93is arranged between the third output90and the reference potential terminal18and represents a load. Furthermore, the voltage converter10comprises a fourth output94and a second flying capacitor95. A first electrode of the second flying capacitor95is connected to the second terminal of the inductor15. Furthermore, the voltage converter10comprises a sixth and a seventh switch96,97which are connected in series. The series connection of the sixth and the seventh switch96,97couples the fourth output94to the reference potential terminal18. A second electrode of the second flying capacitor95is coupled to a node between the sixth and the seventh switch96,97. A fourth storage capacitor98is arranged between the fourth output94and the reference potential terminal18. A fourth load resistor99couples the fourth output94to the reference potential terminal18. The fourth load resistor99represents a further load.

By means of the fifth switch91, a third output voltage VPOS2is applied to the third output90. The third output voltage VPOS2has an opposite polarity to the second output voltage VNEG. By means of the second capacitor95and the series circuit of the sixth and seventh switch96,97, a fourth output voltage VNEG2is generated and applied to the fourth output94. The voltage converter10ofFIG. 1Gis a multi-output converter and generates more than two output voltages. The first duration t1of the charging phase A controls the sum of the absolute values of the four output voltages namely the first output voltage VPOS, the second output voltage VNEG, the third output voltage VPOS2and the fourth output voltage VNEG2. The individual output voltages VPOS, VNEG, VPOS2, VNEG2can be regulated by additional phases like the positive and the negative discharging phase B, C depending upon which output voltage of the first, the second, the third and the fourth output voltage VPOS, VNEG, VPOS2, VNEG2is required to be regulated respectively.

FIG. 1Hshows a further exemplary embodiment of a voltage converter according to the principle presented. The voltage converter according toFIG. 1His a further development of the voltage converters shown inFIG. 1A to 1G. The switching arrangement14comprises a first and a second input switch100,101. The first and the second input switch100,101form a series circuit which couples the input11to the reference potential terminal18. A node between the first and the second input switch100,101is connected to the first terminal of the inductor15. Thus, the voltage converter10is designed also for a buck-boost operation. If the first input switch100is continuously in a closed state and the second input switch101is continuously in an open state, the operation of the voltage converter10is similar to the operations shown inFIG. 1A to 1G. However, if the absolute value of the first output voltage VPOS is smaller than the absolute value of the input voltage VIN and/or the absolute value of the second output voltage VNEG is smaller than the absolute value of the input voltage VIN, then the first and the second input switch100,101are switched according to one of the four cycles shown inFIG. 1H.

The control strategy of the voltage converter10shown in this figure can use any of the control strategies from the previous figures. The first and the second input switch100,101can be operated like a switch having an open state and a closed state.

The voltage VLP at the node between the first and the second input switch100,101experiences either the input voltage VIN or the ground potential at the reference potential terminal18. The first, the second, the third and the fourth control signal S1, S2, S3, S4are equal in the four exemplary cycles. However, the signals SB1, SB2which are provided to the first and the second input switch100,101are different for the four exemplary cycles. The signal SB2which is provided to the second input switch101is an inverted signal in comparison to the signal SB1that is provided to the first input switch100in the first, second and fourth embodiment of a cycle. The voltage converter10in theFIGS. 1A to 1Gshows a buck-boost operation. By the additional switches, namely the first and the second input switch100,101, the flexibility for operation is increased so that a high efficiency can be achieved.

In an alternative embodiment, the first and the second input switch100,101can be operated in a linear mode. Thus, the first and the second input switch100,101not only have an open and a closed state but also at least one state with a resistance in between the open and the closed state.

In an alternative, not shown embodiment, the sequence of the phases is A, C, B instead of A, B, C as shown inFIG. 1H.

FIG. 2shows an exemplary control circuit37that can be inserted in the voltage converter ofFIGS. 1A to 1H. The first sub-circuit38comprises a first comparator110. The first feedback signal V1and the current sensor signal SIL are provided to the two inputs of the first comparator110. An output of the first comparator110is connected to the controller40. The second sub-circuit39comprises a second comparator111and a ramp generator112. The second feedback signal V2is provided to a first input of the second comparator111. The ramp generator112couples a second input of the second comparator111to the reference potential terminal18. An output of the second comparator111is connected to the controller40. Both comparators110,111provide digital signals at their outputs. The controller40is a microcontroller or a microprocessor.

FIG. 3shows an exemplary arrangement comprising the voltage converter10according to one of the previous figures. The arrangement further comprises a light source120. The light source120is connected to the first output12of the voltage converter13and to the second output13of the voltage converter10. The light source120is additionally connected to the reference potential terminal18. The light source120comprises a light emitting diode. The light emitting diode is realized as an organic light emitting diode, abbreviated OLED. The light source120is realized as a matrix. The light source120is implemented as an active-matrix organic light-emitting diode, abbreviated AMOLED. The voltage converter10provides a positive and a negative supply to the light source120. The voltage converter10additionally drives a logic circuit121which is comprised by the light source120. The light source120requires both the first output voltage VPOS with a positive polarity with respect to the reference potential terminal18and the second output voltage VNEG with a negative polarity with respect to the reference potential terminal18. The voltage converter10advantageously provides a very small imbalance of the first output voltage VPOS and of the second output voltage VNEG.

FIG. 4shows exemplary characteristics of a voltage converter according to the principle presented.FIG. 4shows the load current IL, the inductor current ILC, the voltage VGN at the node between the third and the fourth switch20,21, the voltage VLN at the second terminal of the inductor15, the second output voltage VNEG and the first output voltage VPOS as a function of the time t. The characteristics were received by a simulation in an open loop condition. The following values were assumed: the input voltage VIN equals 3.7 V, the bonding resistance is 25 mOhm, the resistance of the first, the second, the third and the fourth switch,17,19,20,21is 100 mOhm, the inductivity of the inductor15equals 4.7 m Henry with an equivalent series resistance, abbreviated ESR, of 10 mOhm, the value of first and second storage capacitor22,23has 4.7 micro F and an ESR of 5 mOhm, the capacitance of the flying capacitor16has a value of 2.2 micro F and an ESR of 5 mOhm, the frequency of the clock signal is 2 MHz and a zero switching time was assumed.