Control circuit with chopping amplifier for switching converter

A control circuit for switching converter has a chopping amplifier, a sample-hold circuit, a first comparator, an oscillator and a logic circuit. The chopping amplifier generates an amplified error signal based on a reference signal and a feedback signal. The sample-hold circuit generates a sample-hold signal based on the amplified error signal. The first comparator generates a first logic signal based on a comparison result between the sample-hold signal and a current sensing signal representing a current flowing through a power switch in the switching converter. The oscillator generates a clock signal. The logic circuit generates a control signal based on the first logic signal and the clock signal, the control signal is used to control the power switch.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application claims priority to and the benefit of Chinese Patent Application No. 201410330826.4, filed on Jul. 11, 2014, which is incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present invention generally relates to electronic apparatuses, and more particularly but not exclusively to control circuits with chopping amplifier for switching converter.

BACKGROUND

Switching converters are widely used due to their high efficiency and simple internal structure.FIG. 1schematically illustrates a prior art switching converter10. The switching converter10comprises a control circuit100and a switching circuit110. The switching circuit110comprises at least a power switch M1. The power switch M1has a first terminal, a second terminal and a control terminal. The switching circuit110converts an input voltage VIN to an output voltage VOUT according to a control signal CTRL. The switching circuit110may apply different types of topology, such as buck converter, boost converter, buck-boost converter, fly-back converter, and other switching converters.

The control circuit100comprises an error amplifier101, a comparator102, a logic circuit103, a current sensing circuit104and an oscillator105.

The error amplifier101has a first input terminal, a second input terminal and an output terminal. Based on a reference signal VREF received at the first input terminal and the output voltage VOUT received at the second input terminal, the error amplifier101is operable to generate an amplified error signal VEAO at the output terminal. In another embodiment, the error amplifier101generates the error signal VEAO based on the reference signal VREF and a feedback signal indicating a load current IOUT of the switching converter10.

The comparator102has a first input terminal, a second input terminal and an output terminal. The comparator102generates a first logic signal VL1at the output terminal based on a comparison result between the error signal VEAO received at the first input terminal and a current sensing signal RFLTI received at the second input terminal. The current sensing signal RFLTI could reflect a current flowing through the power switch M1or the inductor L. In the illustrated embodiment inFIG. 1, the current sensing signal RFLTI is generated by a current sensing circuit104that is configured to detect the current flowing through the power switch M1.

The logic circuit103has a first input terminal, a second input terminal and an output terminal. The logic circuit103generates a switching signal CTRL at the output terminal based on the first logic signal VL1received at the first input terminal and the second logic signal VL2received at the second input terminal. In the illustrated embodiment inFIG. 1, the second logic signal VL2is a clock signal provided by the oscillator105.

DC-DC converter10could provide a stable output voltage since the error amplifier101regulates the output voltage VOUT to a value substantially equal to the value of the reference signal VREF. In some applications, the value of the reference signal VREF may be relatively low (e.g. 200 mV) while an offset voltage (OFFSET) of the error amplifier101could be dozens of mill volts (e.g. 50 mV). So, the error of the output voltage VOUT or load current IOUT may be up to 25%. In addition, the noise of the input transistor of the error amplifier101would be amplified and reflected on the output voltage VOUT or load current IOUT. Reducing the error of the output voltage caused by the offset voltage or noise of the error amplifier101becomes a big challenge.

SUMMARY

Embodiments of the present invention are directed to a control circuit for a switching converter with at least a power switch, comprising: a chopping amplifier having a first input terminal, a second input terminal, a control terminal and an output terminal, wherein the first input terminal is configured to receive a reference signal, and wherein the second input terminal is configured to receive a feedback signal representing an output voltage or a load current of the switching converter, and wherein the control terminal is configured to receive a chopping control signal, and wherein based on the reference signal and the feedback signal, the chopping amplifier is operable to generate an amplified error signal at the output terminal; a sample-hold circuit having an input terminal, an output terminal and a control terminal, wherein the input terminal is coupled to the output terminal of the chopping amplifier, and wherein the control terminal is configured to receive a sample-hold control signal, and wherein the sample-hold circuit generates a sample-hold signal at the output terminal; a first comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the sample-hold circuit, and wherein the second input terminal is configured to receive a current sensing signal representing a current flowing through the power switch, and wherein based on a comparison result between the sample-hold signal and the current sensing signal, the first comparator generates a first logic signal at the output terminal; an oscillator, generating a clock signal; and a logic circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is configured to receive the first logic signal, and wherein the second input terminal is configured to receive the clock signal, and wherein based on the first logic signal and the clock signal, the logic circuit generates a switching signal at the output terminal, and wherein the switching signal is configured to control the power switch.

Furthermore, there has been provided, in accordance with an embodiment of the present invention, a control circuit for a switching converter with at least a power switch, comprising: a chopping amplifier having a first input terminal, a second input terminal, a control terminal and an output terminal, wherein the first input terminal is configured to receive a reference signal, and wherein the second input terminal is configured to receive a feedback signal representing an output voltage or a load current of the switching converter, and wherein the control terminal is configured to receive a chopping control signal, and wherein based on the reference signal and the feedback signal, the chopping amplifier is operable to generate an amplified error signal at the output terminal; a sample-hold circuit having an input terminal, an output terminal and a control terminal, wherein the input terminal is coupled to the output terminal of the chopping amplifier, and wherein the control terminal is configured to receive a sample-hold control signal, and wherein the sample-hold circuit generates a sample-hold signal at the output terminal; a first comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the sample-hold circuit, and wherein the second input terminal is configured to receive the feedback signal, and wherein based on a comparison result between the sample-hold signal and the feedback signal, the first comparator generates an ON signal at the output terminal; an OFF signal generating circuit, generating an OFF signal at the output terminal; and a logic circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is configured to receive the ON signal, and wherein the second input terminal is configured to receive the OFF signal, and wherein based on the ON signal and the OFF signal, the logic circuit provides a switching signal at the output terminal, and wherein the switching signal is configured to control the power switch.

Furthermore, there has been provided, in accordance with an embodiment of the present invention, a control circuit for a switching converter with at least a power switch, comprising: a chopping amplifier having a first input terminal, a second input terminal, a control terminal and an output terminal, wherein the first input terminal is configured to receive a reference signal, and wherein the second input terminal is configured to receive a feedback signal representing an output voltage or a load current of the switching converter, and wherein the control terminal is configured to receive a chopping control signal, and wherein based on the reference signal and the feedback signal, the chopping amplifier is operable to generate an amplified error signal at the output terminal; a first comparator having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the chopping amplifier, and wherein the second input terminal is configured to receive a current sensing signal representing a current flowing through the power switch, and wherein based on a comparison result between the amplified error signal and the current sensing signal, the first comparator generates a first logic signal at the output terminal; an oscillator, generating a clock signal; and a logic circuit having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is configured to receive the first logic signal, and wherein the second input terminal is configured to receive the clock signal, and wherein based on the first logic signal and the clock signal, the logic circuit generates a switching signal at the output terminal, and wherein the switching signal is configured to control the power switch, and wherein the frequency of the chopping control signal is N times of the frequency of the switching signal, and wherein N is an integer greater than 0.

DETAILED DESCRIPTION

FIG. 2schematically illustrates a switching converter20in accordance with an embodiment of the present invention. The switching converter20comprises a control circuit200and a switching circuit110. The control circuit200comprises a chopping amplifier201, a comparator102, a logic circuit103, a current sensing circuit104and an oscillator105.

The chopping amplifier201has a first input terminal, a second input terminal, a control terminal and an output terminal. Based on the reference signal VREF received at the first input terminal and the output voltage VOUT received at the second input terminal, the chopping amplifier201is operable to generate the error signal VEAO at the output terminal. As chopping technique is utilized, the chopping amplifier201comprises a first chopper2011, an input stage2012, a second chopper2013and an output stage2014. The first chopper2011is configured to receive the reference signal VREF and the output voltage VOUT, the input stage2012is coupled between the first chopper2011and the second chopper2013, the output stage2014is configured to generate the amplified error signal VEAO. A chopping control signal received on the control terminal of the chopping amplifier is used to control the first chopper2011and the second chopper2013.

FIG. 3schematically illustrates a chopping amplifier300in accordance with an embodiment of the present invention. The chopping amplifier300comprises a first chopper301, an input stage302, a second chopper303and an output stage304. In theFIG. 3, a differential signal VDIF is used to express a difference between the reference signal VREF and the output voltage VOUT, wherein VOS is an offset voltage of the input stage302, and wherein VO1 is an output voltage of the input stage302, and further wherein VO2 is an output voltage of the second chopper303. The output stage304could be regarded as a low pass filter to filter out the high frequency components of VO2. The output signal of the output stage304is configured to be the amplified error signal VEAO.

Referring toFIG. 3, the differential signal VDIF is modulated to a chopping frequency (up to several hundred kHz) by the first chopper301, and then amplified by the input stage302and modulated back to the baseband by the second chopper303. The offset voltage VOS is only modulated by the second chopper303and would be filter out by the output stage304. It means that the offset voltage VOS could be nearly removed by the chopping amplifier300.

FIG. 4illustrates operational waveforms of the chopping amplifier300in accordance with an embodiment of the present invention. Referring toFIG. 4, a chopping control signal FCHP with 50% duty cycle is used to control the first chopper301and the second chopper303. In the first half cycle of the control single FCHP, switches K1and K3are turned on, and switches K2and K4are turned off. the output voltage VO1 and VO2 could be expressed as
VO1=A×(VDIF+VOS)
VO2=A×(VDIF+VOS)

Wherein A is the amplification factor of the input stage301. In the second half cycle of the control single FCHP, switches K2and K4are turned on, switches K1and K3are turned off, the output voltage VO1 and VO2 could be expressed as
VO1=A×(VOS−VDIF)
VO2=A×(VDIF−VOS)

The average value of VO2 in one cycle could be expressed as
VEAO=0.5×A×(VOS+VDIF)+0.5×A×(VDIF−VOS)=A×VDIF

The chopping techniques successfully reduce the error caused by the offset voltage VOS. Similarly, chopping technique also could successfully reduce noise caused by the noise of the input transistor of an amplifier.

In some embodiments, because of limitations of process, such as inability to provide a large resistor or capacitor, the output stage2014generally cannot provide a very low cutoff frequency. In some embodiments, an amplifier may be unable to provide a very low cut-off frequency due to the requirement of the loop stability of a switching converter. These limitations make the error signal VEAO be a varying triangular signal or a fluctuating signal. In some embodiments, the amplified error signal VEAO is configured to decide on-time or off-time of power switch M1. A varying signal may cause inconsistent on-time or off-time, leading to a varying duty cycle. For constant ON time (COT) or constant off time mode voltage converter, the variation of the error signal VEAO can also lead to a varying switching frequency.

One way to solve above issues is to set the frequency of the chopping control signal FCHP to be N times of the switching frequency of the converter20, wherein N is an integer greater than 0.FIG. 5illustrates an operational waveforms when the chopping frequency FCHP is substantial equal to the switching frequency of the switching converter20in accordance with an embodiment of the present invention. When the frequency of error amplifier signal VEAO and current feedback signal RFLTI are similar to each other, the current feedback signal RFLTI and the amplified error signal VEAO always “encounter” at the same voltage value, which makes the duty cycle of the switch signal CTRL consistent. However, since an optimal selection of the chopping control signal FCHP is a square wave signal with 50% duty cycle, a clock signal having a frequency of 2 times of the frequency of chopping control signal FCHP should be provided for frequency dividing. In some embodiments, an oscillator needs to provide a triangular wave having the same frequency as switching signal CTRL, which makes it unable to provide a clock signal having a frequency of 2 times of the frequency of switching signal CTRL. Also, in other embodiments, voltage converters may not have an oscillator.

To solve above issues, sample-hold technique could be used in an amplifier.FIG. 6schematically illustrates a switching converter60in accordance with an embodiment of the present invention. The switching converter60comprises a control circuit600and a switching circuit110. The control circuit600comprises the chopping amplifier201, a sample-hold circuit601, the comparator102, the logic circuit103, the current sensing circuit104, the oscillator105, a frequency divider602and a pulse generating circuit603.

The sample-hold circuit601has an input terminal, an output terminal and a control terminal, wherein the input terminal is coupled to the output terminal of the chopping amplifier201, and wherein the control terminal is configured to receive a sample-hold control signal VSH, and wherein the sample-hold circuit601generates a sample-hold signal VHOD at the output terminal. The sample-hold circuit601samples the amplified error signal VEAO and provides a signal at the output terminal as the sample-hold signal VHOD. The sample-hold circuit601refreshes the sample-hold signal VHOD when the sample-hold control signal VSH is enabled.

In one embodiment, the second logic signal VL2can be used to obtain the chopping control signal FCHP. As shown inFIG. 6, control circuit600further comprises the frequency divider602having an input terminal and an output terminal, and wherein the input terminal is configured to receive the second logic signal VL2, and wherein the frequency divider602is configured to generate the chopping control signal FCHP. After frequency dividing, the period of the chopping control signal FCHP is usually several times of it of the second logic signal VL2, such as 2 times, 4 times or 6 times. In one embodiment, the chopping control signal FCHP could be served as the sample-hold control signal VSH directly. In another embodiment, the control circuit600further comprises the pulse generating circuit603having an input terminal and an output terminal, and wherein the input terminal is configured to receive the chopping control signal FCHP, and wherein the pulse generating circuit603is configured to generate the sample-hold control signal VSH having the same frequency as it of the chopping control signal FCHP.

In another embodiment, the input terminal of the frequency divider602could be couple to the output terminal of the logic circuit103, configured to generate the chopping control signal FCHP based on the switching signal CTRL.

FIG. 8schematically illustrates a switching mode power converter80in accordance with an embodiment of the present invention. The switching mode power converter80comprises a control circuit800and a switching circuit810. The switching circuit810adopts a synchronous buck topology, comprising a power switch M1, a low side switch M2, an inductor L and an output capacitor C. The power switch M1has a first terminal configured to receive an input voltage VIN, a control terminal configured to receive the switching signal CTRL, and a second terminal. The low side switch has a first terminal coupled to the second terminal of the power switch M1, a control terminal and a second terminal connected to ground. The inductor L has a first terminal connected to the second terminal of the power switch M1and a second terminal configured to provide the output voltage VOUT. The switching circuit810converts the input voltage VIN to the output voltage VOUT according to a control signal CTRL.

The control circuit800comprises the chopping amplifier201, the sample-hold circuit601, the frequency divider602, the pulse generating circuit603, a comparator801, an OFF signal generating circuit802, a logic circuit803, a current sensing circuit804and an OFF threshold generating circuit805.

The chopping amplifier201has a first input terminal, a second input terminal, a control terminal and an output terminal, wherein the first input terminal is configured to receive a reference signal VREF, and wherein the second input terminal is configured to receive a feedback signal VFB, and wherein the control terminal is configured to receive a chopping control signal FCHP, and wherein based on the reference signal and the feedback signal, the chopping amplifier is operable to generate the amplified error signal VEAO at the output terminal;

The sample-hold circuit601has an input terminal, an output terminal and a control terminal, wherein the input terminal is coupled to the output terminal of the chopping amplifier201, and wherein the control terminal is configured to receive a sample-hold control signal VSH, and wherein the sample-hold circuit generates a sample-hold signal VHOD at the output terminal.

The comparator801has a first input terminal, a second input terminal and an output terminal. Based on a comparison result between the sample-hold signal VHOD received at the first input terminal and the feedback voltage VFB received at the second input terminal, the comparator801provides the ON signal ONSET at the output terminal. In the embodiment shown inFIG. 8, a first resister RF1and a second resister RF2are connected in series to sense the output voltage VOUT and provide the feedback voltage VFB. In another embodiment, the feedback voltage VFB may express a load current of the switching converter80.

The OFF signal generating circuit802provides an OFF signal OFFSET at the output terminal. In one embodiment, the OFF signal OFFSET could be a clock signal with a constant pulse width. In another embodiment, the OFF signal generating circuit802has a first input terminal, a second input terminal and an output terminal, based on a comparison result between a reference voltage signal received at the first input terminal and a triangular wave signal received at the second input terminal, the OFF signal generating circuit102provides the OFF signal OFFSET. In one embodiment, the OFF signal generating circuit802comprises a second comparator COM2. The second comparator COM2has a first input terminal, a second input terminal and an output terminal. The second comparator COM2provides the OFF signal OFFSET at the output terminal based on a comparison result between an OFF threshold signal OFFTH provided by the current seeing circuit804and a current sensing signal RFLTI provided by the OFF threshold generating circuit805.

The logic circuit803has a first input terminal, a second input terminal and an output terminal. The logic circuit803provides a switching signal CTRL at the output terminal based on the ON signal ONSET received at the first input terminal and the OFF signal OFFSET received at the second input terminal. In an embodiment, the logic circuit803is a RS flip-flop.

The current sensing circuit804has an input terminal and an output terminal. The current sensing circuit804provides the current sensing signal RFLTI based on a current flowing through the power switch M1. In one embodiment, the current sensing circuit104is configured to detect the current flowing through the power switch M1directly. In another embodiment, the current sensing circuit804comprises a current simulating circuit configured to simulate the current flowing through the power switch M1by detecting the voltage on the second terminal of the power switch M1or the voltage difference between the first terminal and the second terminal of the power switch M1.

The OFF threshold generating circuit805has an input terminal and an output terminal. The OFF threshold generating circuit805provides the OFF threshold signal OFFTH based on the difference between a frequency of the switching signal CTRL and a preset frequency FQREF, so as to make the frequency of the switching signal CTRL substantially equal to the preset frequency FQREF. In one embodiment, The OFF threshold generating circuit805comprises a phase lock (PLL) circuit. The PLL circuit is configured to receive a reference clock signal CLK and the switching signal CTRL, and provides the OFF threshold signal OFFTH based on the frequency difference between the reference clock signal CLK and the switching signal CTRL.

FIG. 9illustrates operational waveforms of the switching converter80in accordance with an embodiment of the present invention. When the feedback voltage VFB becomes is smaller than the reference signal VREF, the ON signal ONSET jumps from logic low to logic high, the switching signal CTRL is turned to logical high to turn on the power switch M1. The current sensing signal RFLTI and the current flowing through the power switch M1(IM1) are increased since the power switch M1is turned on. When the current sensing signal RFLTI reaches the OFF threshold OFFTH provided by the OFF threshold generating circuit805, the switching signal CTRL is turned to logical low, and the power switch M1is turned off. The OFF threshold generating circuit805adjusts the OFF threshold signal OFFTH based on the difference between a frequency of the switching signal CTRL and a preset frequency FQREF, so as to make the frequency of the switching signal CTRL substantially equal to the preset frequency FQREF. In one embodiment, when the power switch M1is tuned off, the current sensing signal RFLTI could fall slowly as dashed line inFIG. 9. In another embodiment, when the power switch M1is tuned off, the current sensing signal RFLTI could fall to a low value sharply.

FIG. 10schematically illustrates the OFF threshold generating circuit805in accordance with an embodiment of the present invention. The OFF threshold generating circuit805comprises a first current source I1, a second current source I2, a third current source I3, a first capacitor C1, a second capacitor C2, a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a third comparator COM3and a second logic circuit8051.

The first capacitor C1has a first terminal and a second terminal, wherein the second terminal is connected to ground. The first switch S1has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to a first voltage V1via the first current source I1, and wherein the second terminal is coupled to the first terminal of the first capacitor C1. The second switch S2has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the first terminal of the first capacitor C1, and wherein the second terminal is connected to ground. The second capacitor C2has a first terminal and a second terminal, wherein the second terminal is connected to ground. The third switch S3has a first terminal, a second terminal and a control terminal, wherein the first terminal receives a second voltage V2via the second current source I2, and wherein the second terminal is coupled to the first terminal of the second capacitor C2. The fourth switch S4has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the first terminal of the first capacitor C1, and wherein the second terminal is coupled to ground via third current source I3. The third comparator COM3has a first input terminal, a second input terminal and an output terminal, and wherein the first input terminal is coupled to the first terminal of the first capacitor C1, and wherein the second input terminal is configured to receive a second reference signal VREF2. The second logic circuit8051has a first input terminal, a second input terminal, a first output terminal and a second output terminal, wherein the first input terminal is coupled to the output of the third comparator COM3, and wherein the second input terminal is configured to receive the switching signal CTRL, and wherein the second logic circuit is configured to provide a plurality of control signals to control the first switch S1, the second switch S2, the third switch S3and the fourth switch S4.

In one embodiment, the second logic circuit8051comprises a RS flip-flop having a first input terminal R, a second input terminal S and an output terminal O. In another embodiment, the second logic circuit8051further comprises a pulse generating circuit8052having an input terminal and an output terminal. The pulse generating circuit8052is configured to generate a pulse signal PULSE having same frequency as the switching signal CTRL.

In some embodiments, the OFF threshold generating circuit805further comprises a clamping circuit CLAMP. The clamping circuit CLAMP is configured to set a maximum value of the VC2to a clamped voltage VCLAP. When the switching converter80in a light load, the OFF threshold signal OFFTH is smaller than the maximum value and the frequency of the switching signal CTRL is equal to the preset frequency FQREF. When the switching converter80in a heavy load, the OFF threshold signal OFFTH is clamped to the maximum value by the clamping circuit CLAMP and the frequency of the switching signal CTRL is larger than the preset frequency FQREF

Control circuits with chopping amplifier for switching converter have been disclosed. While specific embodiments of the present invention have been provided in the above description, it should be understood that these embodiments are for illustration purposes and not intend to limit the present invention. Many additional embodiments will be apparent to persons of ordinary skill in the art under the spirit of the present invention.