STAIRCASE FORMATION IN A MEMORY ARRAY

Methods, systems, and devices for staircase formation in a memory array are described. A liner composed of a first liner material may be deposited on a tread and a first portion of the liner may be doped. After doping the first portion of the liner, a second portion of the liner may be converted into a second liner material using a chemical process. After converting the second portion of the liner into the second liner material, the first portion of the liner material may be removed so that a subsequent removal process can expose a first sub-tread. After exposing the first sub-tread, the second portion of the liner may be removed so that a second sub-tread is exposed.

FIELD OF TECHNOLOGY

The following relates to one or more systems for memory, including staircase formation in a memory array.

BACKGROUND

Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device to various states. For example, binary memory cells may be programmed to one of two supported states, often corresponding to a logic 1 or a logic 0. In some examples, a single memory cell may support more than two possible states, any one of which may be stored by the memory cell. To access information stored by a memory device, a component may read (e.g., sense, detect, retrieve, identify, determine, evaluate) the state of one or more memory cells within the memory device. To store information, a component may write (e.g., program, set, assign) one or more memory cells within the memory device to corresponding states.

DETAILED DESCRIPTION

In some memory systems, word line contacts may be used to couple the word lines of memory cells with supporting components. For example, a word line that is coupled with a memory cell may also be coupled with a word line contact that allows the memory system to apply electrical signals to the word line. If the word lines are stacked layers of metal material (e.g., tungsten) in the x-y plane, the word line contacts may be conductive pillars that couple with contact surfaces of the word lines and extend in the z-direction. To prevent shorts between word lines, the contact surfaces may form a staircase pattern where each landing surface is offset from the other and is referred to as a “tread” of the staircase. For example, if the treads (contact surfaces) are in the x-y plane, the staircase may extend widthwise in the x-direction, may extend lengthwise in the y-direction, and may extend height-wise in the z-direction.

As components of memory arrays scale and get smaller to include more memory cells and word lines, the quantity of word line contacts in a memory array may also increase. Instead of adding additional treads for the new word line contacts (which may increase the total area consumed by the word line contacts), it may be desirable to form lateral sub-treads on the treads of a staircase. For example, it may be desirable to form two lateral sub-treads on the treads of the staircase, permitting two times (2x) more word line contacts per unit area relative to other designs. But the manufacturing process used to form the treads may be inadequate to form the sub-treads in the sizes used to increase the quantity of word line contacts and reduce the area used by each word line contact. A lateral sub-tread may also be referred to herein as a contact surface, lateral fold, or other suitable terminology.

The techniques described herein allow for formation of two or more lateral sub-treads (contact surfaces) in a staircase architecture for word line contacts, thus reducing the area consumed by the word line contacts. A staircase with lateral sub-treads (contact surfaces) may also be referred to herein as a folded staircase.

To form multiple lateral sub-treads (contact surfaces), a liner composed of a first liner material (e.g., polysilicon) may be deposited on a tread and a first portion of the liner may be doped (e.g., with boron). After doping the first portion of the liner, a second portion of the liner (which may overlay an area of the tread that will become the second sub-tread) may be converted into a second liner material (e.g., tungsten) using a chemical process. The second liner material may more robustly withstand a removal process (e.g., dry etching) relative to the first liner material. After converting the second portion of the liner into the second liner material, the first portion of the liner material may be removed so that a subsequent removal process (e.g., dry etching) can expose the first sub-tread. After exposing the first sub-tread, the second portion of the liner may be removed (e.g., via wet etching) so that the second sub-tread is exposed.

Thus, two lateral sub-treads (contact surfaces) may be formed on a tread in a staircase architecture for word line contacts. Compared to other techniques, conversion of the first liner material to the second liner material may allow for a thinner liner (which may be referred to as an etch-stop layer) and may negate the use for additional process steps such as gap filling, among other advantages.

Features of the disclosure are initially described in the context of systems, devices, and circuits with reference toFIG.1. Features of the disclosure are described in the context of a material structure with reference toFIGS.2A through2K. These and other features of the disclosure are further illustrated by and described in the context of flowcharts that relate to staircase formation in a memory array with reference toFIGS.3through4.

FIG.1illustrates an example of a memory device100that supports staircase formation in a memory array in accordance with examples as disclosed herein.FIG.1is an illustrative representation of various components and features of the memory device100. As such, the components and features of the memory device100are shown to illustrate functional interrelationships, and not necessarily physical positions within the memory device100. Further, although some elements included inFIG.1are labeled with a numeric indicator, some other corresponding elements are not labeled, even though they are the same or would be understood to be similar, in an effort to increase visibility and clarity of the depicted features.

The memory device100may include one or more memory cells105, such as memory cell105-aand memory cell105-b. In some examples, a memory cell105may be a NAND memory cell, such as in the blow-up diagram of memory cell105-a. Each memory cell105may be programmed to store a logic value representing one or more bits of information. In some examples, a single memory cell105—such as a memory cell105configured as a single-level cell (SLC)—may be programmed to one of two supported states and thus may store one bit of information at a time (e.g., a logic 0 or a logic 1). In some other examples, a single memory cell105—such a memory cell105configured as a multi-level cell (MLC), a ti-level cell (TLC), a quad-level cell (QLC), or other type of multiple-level memory cell105—may be programmed to one state of more than two supported states and thus may store more than one bit of information at a time. In some cases, a multiple-level memory cell105(e.g., an MLC memory cell, a TLC memory cell, a QLC memory cell) may be physically different than an SLC cell. For example, a multiple-level memory cell105may use a different cell geometry or may be fabricated using different materials. In some examples, a multiple-level memory cell105may be physically the same or similar to an SLC cell, and other circuitry in a memory block (e.g., a controller, sense amplifiers, drivers) may be configured to operate (e.g., read and program) the memory cell as an SLC cell, or as an MLC cell, or as a TLC cell, etc.

In some NAND memory arrays, each memory cell105may be illustrated as a transistor that includes a charge trapping structure (e.g., a floating gate, a replacement gate, a dielectric material) for storing an amount of charge representative of a logic value. For example, the blow-up inFIG.1illustrates a NAND memory cell105-athat includes a transistor110(e.g., a metal-oxide-semiconductor (MOS) transistor) that may be used to store a logic value. The transistor110may include a control gate115and a charge trapping structure120(e.g., a floating gate, a replacement gate), where the charge trapping structure120may, in some examples, be between two portions of dielectric material125. The transistor110also may include a first node130(e.g., a source or drain) and a second node135(e.g., a drain or source). A logic value may be stored in transistor110by storing (e.g., writing) a quantity of electrons (e.g., an amount of charge) on the charge trapping structure120. An amount of charge to be stored on the charge trapping structure120may depend on the logic value to be stored. The charge stored on the charge trapping structure120may affect the threshold voltage of the transistor110, thereby affecting the amount of current that flows through the transistor110when the transistor110is activated (e.g., when a voltage is applied to the control gate115, when the memory cell105-ais read). In some examples, the charge trapping structure120may be an example of a floating gate or a replacement gate that may be part of a 2D NAND structure. For example, a 2D NAND array may include multiple control gates115and charge trapping structures120arranged around a single channel (e.g., a horizontal channel, a vertical channel, a columnar channel, a pillar channel).

A logic value stored in the transistor110may be sensed (e.g., as part of a read operation) by applying a voltage to the control gate115(e.g., to control node140, via a word line165) to activate the transistor110and measuring (e.g., detecting, sensing) an amount of current that flows through the first node130or the second node135(e.g., via a bit line155). For example, a sense component170may determine whether an SLC memory cell105stores a logic 0 or a logic 1 in a binary manner (e.g., based on a presence or absence of a current through the memory cell105when a read voltage is applied to the control gate115, based on whether the current is above or below a threshold current). For a multiple-level memory cell105, a sense component170may determine a logic value stored in the memory cell105based on various intermediate threshold levels of current when a read voltage is applied to the control gate115, or by applying different read voltages to the control gate and evaluating different resulting levels of current through the transistor110, or various combinations thereof. In one example of a multiple-level architecture, a sense component170may determine the logic value of a TLC memory cell105based on eight different levels of current, or ranges of current, that define the eight potential logic values that could be stored by the TLC memory cell105.

An SLC memory cell105may be written by applying one of two voltages (e.g., a voltage above a threshold or a voltage below a threshold) to memory cell105to store, or not store, an electric charge on the charge trapping structure120and thereby cause the memory cell105store one of two possible logic values. For example, when a first voltage is applied to the control node140(e.g., via a word line165) relative to a bulk node145(e.g., a body node) for the transistor110(e.g., when the control node140is at a higher voltage than the bulk), electrons may tunnel into the charge trapping structure120. Injection of electrons into the charge trapping structure120may be referred to as programming the memory cell105and may occur as part of a write operation. A programmed memory cell may, in some cases, be considered as storing a logic 0. When a second voltage is applied to the control node140(e.g., via the word line165) relative to the bulk node145for the transistor110(e.g., when the control node140is at a lower voltage than the bulk node145), electrons may leave the charge trapping structure120. Removal of electrons from the charge trapping structure120may be referred to as erasing the memory cell105and may occur as part of an erase operation. An erased memory cell may, in some cases, be considered as storing a logic 1. In some cases, memory cells105may be programmed at a page level of granularity due to memory cells105of a page sharing a common word line165, and memory cells105may be erased at a block level of granularity due to memory cells105of a block sharing commonly biased bulk nodes145.

In contrast to writing an SLC memory cell105, writing a multiple-level (e.g., MLC, TLC, or QLC) memory cell105may involve applying different voltages to the memory cell105(e.g., to the control node140or bulk node145thereof) at a finer level of granularity to more finely control the amount of charge stored on the charge trapping structure120, thereby enabling a larger set of logic values to be represented. Thus, multiple-level memory cells105may provide greater density of storage relative to SLC memory cells105but may, in some cases, involve narrower read or write margins or greater complexities for supporting circuitry.

A charge-trapping NAND memory cell105may operate similarly to a floating-gate NAND memory cell105but, instead of or in addition to storing a charge on a charge trapping structure120, a charge-trapping NAND memory cell105may store a charge representing a logic state in a dielectric material between the control gate115and a channel (e.g., a channel between a first node130and a second node135). Thus, a charge-trapping NAND memory cell105may include a charge trapping structure120, or may implement charge trapping functionality in one or more portions of dielectric material125, among other configurations.

In some examples, each page of memory cells105may be connected to a corresponding word line165, and each column of memory cells105may be connected to a corresponding bit line155(e.g., digit line). Thus, one memory cell105may be located at the intersection of a word line165and a bit line155. This intersection may be referred to as an address of a memory cell105. In some cases, word lines165and bit lines155may be substantially perpendicular to one another, and may be generically referred to as access lines or select lines.

In some cases, a memory device100may include a three-dimensional (3D) memory array, where multiple two-dimensional (2D) memory arrays may be formed on top of one another. In some examples, such an arrangement may increase the quantity of memory cells105that may be fabricated on a single die or substrate as compared with 1D arrays, which, in turn, may reduce production costs, or increase the performance of the memory array, or both. In the example ofFIG.1, memory device100includes multiple levels (e.g., decks, layers, planes, tiers) of memory cells105. The levels may, in some examples, be separated by an electrically insulating material. Each level may be aligned or positioned so that memory cells105may be aligned (e.g., exactly aligned, overlapping, or approximately aligned) with one another across each level, forming a memory cell stack175. In some cases, memory cells aligned along a memory cell stack175may be referred to as a string of memory cells105(e.g., as described with reference toFIG.2).

Accessing memory cells105may be controlled through a row decoder160and a column decoder150. For example, the row decoder160may receive a row address from the memory controller180and activate an appropriate word line165based on the received row address. Similarly, the column decoder150may receive a column address from the memory controller180and activate an appropriate bit line155. Thus, by activating one word line165and one bit line155, one memory cell105may be accessed. As part of such accessing, a memory cell105may be read (e.g., sensed) by sense component170. For example, the sense component170may be configured to determine the stored logic value of a memory cell105based on a signal generated by accessing the memory cell105. The signal may include a current, a voltage, or both a current and a voltage on the bit line155for the memory cell105and may depend on the logic value stored by the memory cell105. The sense component170may include various circuitry (e.g., transistors, amplifiers) configured to detect and amplify a signal (e.g., a current or voltage) on a bit line155. The logic value of memory cell105as detected by the sense component170may be output via input/output component190. In some cases, a sense component170may be a part of a column decoder150or a row decoder160, or a sense component170may otherwise be connected to or in electronic communication with a column decoder150or a row decoder160.

A memory cell105may be programmed or written by activating the relevant word line165and bit line155to enable a logic value (e.g., representing one or more bits of information) to be stored in the memory cell105. A column decoder150or a row decoder160may accept data (e.g., from the input/output component190) to be written to the memory cells105. In the case of NAND memory, a memory cell105may be written by storing electrons in a charge trapping structure or an insulating layer.

A memory controller180may control the operation (e.g., read, write, re-write, refresh) of memory cells105through the various components (e.g., row decoder160, column decoder150, sense component170). In some cases, one or more of a row decoder160, a column decoder150, and a sense component170may be co-located with a memory controller180. A memory controller180may generate row and column address signals in order to activate a desired word line165and bit line155. In some examples, a memory controller180may generate and control various voltages or currents used during the operation of memory device100.

The word lines165may be coupled with various components (e.g., word line drivers238) via word line contacts. For example, if the word lines165are stacked metal layers in the x-y plane, word line contacts that extend in the z-direction may couple the word lines165to word line drivers238. The contact surfaces (treads) of the word lines165may form a rising staircase (e.g., with each tread higher in the z-direction than the previous tread). To reduce the area consumed by the word line contacts, lateral sub-treads (also referred to as contact surfaces) may be formed in the treads according to the techniques described herein. Specifically, the lateral contact surfaces may be formed by using a liner material and converting a portion of the liner material into a different material.

FIGS.2A through2Killustrate examples of a material structure200at different stages of a process that forms multiple lateral contact surfaces in a word line staircase.FIGS.2A through2Kshow a cross-section of the material structure200. Aspects of the material structure200may be described with reference to an x-direction, a y-direction, and a z-direction of the illustrated coordinate system. Although described with reference to two contact surfaces, the techniques described herein can be extended to any quantity of contact surfaces.

FIG.2Aillustrates an example of a material structure200after a cavity202is formed in a set of stacked materials212. The stacked materials212may include alternating materials or layers. For examples, the stacked materials212may include a dielectric material (e.g., oxide) formed as dielectric layers206and may include a sacrificial material (e.g., nitride) formed as sacrificial layers204. In some examples, the stacked materials212may be formed by depositing the dielectric material and the sacrificial material layer-by-layer. The cavity202may be formed by removing sections of the dielectric layers206and the sacrificial layers204. A dry-etch process may be used to form the cavity202.

The bottom or floor of the cavity202may be in the x-y plane and may form a tread208of a word line staircase as described herein. For example, the staircase may extend lengthwise in the y-direction (e.g., into the page) and may extend height-wise in the z-direction.

The cavity202may be defined by a first sidewall210-aof the stacked materials212and a second sidewall210-bof the stacked materials212, each of which may be perpendicular to the tread208. The sacrificial material may be a placeholder material that is replaced with a metal material (e.g., that makes up the word lines) after the contact surfaces have been formed on the tread208. A sacrificial material may also be referred to as a placeholder material, a temporary material, or other suitable terminology.

FIG.2Billustrates an example of the material structure200after a liner214is deposited in the cavity202. In some examples, the liner214may comprise a first liner material, such as a polysilicon material. The liner214may overlay the tread208, the first sidewall210-a, and the second sidewall210-b. Thus, the liner214may overlay the first sacrificial layer204-a. The liner214may allow for formation of a protective barrier (e.g., etch stop) that helps protect the second contact surface218of the second sacrificial layer204-bduring a subsequent removal processes that exposes the first contact surface216of the first sacrificial layer204-a.

FIG.2Cillustrates an example of the material structure200after selectively doping a portion of the liner214to form a doped portion (e.g., first portion220). In some examples, doping the portion of the liner214may include doping the liner214with boron. In some examples, a resist material219may shield some of the liner214from the doping. Thus, use of a resist material219may allow for the selective doping where a first portion220of the liner214is doped and the rest of the liner214(e.g., including the second portion222) remains undoped. The first portion220may be above the first contact surface216of the first sacrificial layer204-a. The second portion222may overlay the second contact surface218of the second sacrificial layer204-b. Doping the first portion220of the liner214may change the properties of the first portion220so that the first portion220is resistant to a subsequent chemical conversion process that is used to convert the material of the second portion222.

FIG.2Dillustrates an example of the material structure200after converting the second portion222of the liner214from a first material to a second material. For example, a chemical process may be used to convert the second portion222from polysilicon to tungsten. Compared to the polysilicon, the tungsten may provide a more robust etch-stop than the polysilicon (which may be beneficial during later etching steps), which in turn may allow the tungsten to be thinner (which may provide cost-savings). Due to the doping, the first portion220of the liner214may resist the chemical process used to convert second portion222and thus may remain as doped polysilicon. Relative to other techniques, conversion of the first liner material to the second liner material may allow for use of a thinner liner214(which may reduce manufacturing costs) and may negate the use for additional process steps such as gap filling, among other advantages.

FIG.2Eillustrates an example of the material structure200after removing the first portion220of the liner214and leaving the second portion222. In some examples, the removal process (to which the second portion222is impervious) may use Tetramethylammonium Hydroxide (TMAH) to remove the first portion220from the material structure200. Removing the first portion220may expose the second sacrificial layer204-bfor a subsequent removal process that is used to expose the first contact surface216. Retaining the second portion222may protect the second contact surface218from the removal process used to expose the first contact surface216.

In some examples (e.g., as shown in the bottom figure), additional second liner material223(e.g., additional tungsten) may be deposited on the second portion222to increase the thickness of the second portion222(and thus improve the resiliency of the second portion222with respect to one or more subsequent removal processes).

FIG.2Fillustrates an example of the material structure200after removing a section (e.g., section221) of the second sacrificial layer204-band a section (e.g., section225) of the dielectric layer206-athat is above (e.g., in the z-direction) the first sacrificial layer204-aand below (e.g., in the z-direction) the second sacrificial layer204-b. In some examples, a wet-etching process may be used to remove the sections of second sacrificial layer204-band the dielectric layer206-a. Removing the sections of second sacrificial layer204-band the dielectric layer206-amay expose the first contact surface216of the first sacrificial layer204-a.

FIG.2Gillustrates an example of the material structure200after removing the second portion222of the liner214. In some examples, a wet-etching process may be used to remove the second portion222of the liner214. The wet-etching process may use a sulfuric peroxide mixture (SPM), ammonia peroxide mixture (APM), or other suitable chemical solutions. Removing the second portion222may expose the second contact surface218of the second sacrificial layer204-b. Thus, the material structure200may include multiple lateral sub-treads (e.g., first contact surface216and second contact surface218). Removing the second portion222may expose a shelf224of the second sidewall210-b. Removing the second portion222may form a first sidewall225-aextending from the first contact surface216to the second contact surface218and a second sidewall225-bextending from the first contact surface216to the shelf224. The size of the shelf224(e.g., from the second sidewall210-bto the second sidewall225-b) may be based on a thickness of the second portion222.

FIG.2Hillustrates an example of the material structure200after depositing a non-conductive material, such as the oxide material226, within the cavity202. The oxide material226may be deposited so that the oxide material226at least partially fills the cavity202and overlays the first sidewall210-a, the second sidewall210-b, the first contact surface216, and the second contact surface218. Depositing the oxide material226may allow for conductive pillars (e.g., word line contacts) to be formed within the material structure200, among other purposes.

FIG.2Iillustrates an example of the material structure200after replacing the sacrificial material with a metal material. For example, the first sacrificial layer204-amay be replaced by a first metal layer228-athat forms a first word line coupled with a first memory cell. Similarly, the second sacrificial layer204-bmay be replaced by a second metal layer228-bthat forms a second word line coupled with a second memory cell. Thus, the material structure200may include a first contact surface230-aof the first metal layer228-aand a second contact surface230-bof the second metal layer228-b. In some examples, the replacement process may be referred to as a replacement gate (RG) process.

FIG.2Jillustrates an example of the material structure200after forming elongated cavities, such as cavity232-aand cavity232-b, in the material structure200. In some examples, a dry-etching process may be used to form the cavities. The cavities232may be formed through the oxide material226. The metal layers228may serve as etch stops so that the cavities stop at the metal layers228. So, forming the cavities232may expose the first contact surface230-aand the second contact surface230-b.

FIG.2Killustrates an example of the material structure200after forming conductive (e.g., metal) pillars, such as pillar234-aand pillar234-b, within the elongated cavities232. For example, pillar234-amay be formed within cavity232-a, and pillar234-bmay be formed within the cavity232-b.

The material structure200may include a shelf236, similar to the shelf224. The shelf236may include at least a portion of the second metal layer228-b, which may extend around the front and/or back of the pillar234-b. For instance, as can be seen from the planar top view of the material structure200, the second metal layer228-bmay surround the oxide material226and the pillar234-b. So, the shelf236may extend from the second sidewall at the same height (e.g., in the z-direction) as the second contact surface230-b. The cross-sectional view in the top figure is relative to the line A-A of the top view.

The width of the shelf236in the x-direction may be equal to the thickness (e.g., in the x-direction) of the liner214. The height of the shelf236(in the z-direction and relative to the first contact surface230-amay be equal to the sum of A) the height of the second metal layer228-band B) the dielectric layer below the second metal layer228-b. As can be seen inFIG.2K, the shelf236may form a horizontal surface that is parallel with the contact surfaces and that is perpendicular to the sidewalls. The shelf236may be separated from the conductive pillar234-bby the oxide material226.

The pillar234-bmay be between a first sidewall240-aextending from the first contact surface230-ato the second contact surface230-band a second sidewall240-bextending from the first contact surface230-ato the shelf236. The size of the shelf236(e.g., from the second sidewall210-bto the second sidewall240-b) may be based on a thickness of the liner214.

Thus, the material structure200may include two word line contact surfaces230(lateral sub-treads), which may reduce the area consumed by the word line contacts (pillars234).

FIG.3shows a flowchart illustrating a method300that supports staircase formation in a memory array in accordance with examples as disclosed herein. The operations of method300may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally, or alternatively, one or more controllers may perform aspects of the described functions using special-purpose hardware.

At305, the method may include depositing a liner within a cavity of a set of stacked materials including alternating dielectric material and sacrificial material, the liner including a first liner material. The operations of305may be performed in accordance with examples as disclosed herein.

At310, the method may include doping a first portion of the liner. The operations of310may be performed in accordance with examples as disclosed herein.

At315, the method may include converting a second portion of the liner into a second liner material based at least in part on doping the first portion. The operations of315may be performed in accordance with examples as disclosed herein.

At320, the method may include removing the first portion of the liner based at least in part on converting the second portion of the liner into the second liner material. The operations of320may be performed in accordance with examples as disclosed herein.

At325, the method may include exposing a first contact surface of a first sacrificial layer of the sacrificial material based at least in part on removing the first portion of the liner. The operations of325may be performed in accordance with examples as disclosed herein.

At330, the method may include removing the second portion of the liner based at least in part on exposing the first contact surface, where removing the second portion exposes a second contact surface of a second sacrificial layer of the sacrificial material above the first sacrificial layer. The operations of330may be performed in accordance with examples as disclosed herein.

At335, the method may include replacing the sacrificial material with metal material. The operations of335may be performed in accordance with examples as disclosed herein.

At340, the method may include forming a first conductive pillar above a first contact surface of a first metal layer that replaced the first sacrificial layer, and a second conductive pillar above a second contact surface of a second metal layer that replaced the second sacrificial layer. The operations of340may be performed in accordance with examples as disclosed herein.

In some examples, an apparatus (e.g., a manufacturing system) as described herein may perform a method or methods, such as the method300. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of the manufacturing system), or any combination thereof for performing the following aspects of the present disclosure:Aspect 1: A method or apparatus including operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing a liner within a cavity of a set of stacked materials including alternating dielectric material and sacrificial material, the liner including a first liner material; doping a first portion of the liner; converting a second portion of the liner into a second liner material based at least in part on doping the first portion; removing the first portion of the liner based at least in part on converting the second portion of the liner into the second liner material; exposing a first contact surface of a first sacrificial layer of the sacrificial material based at least in part on removing the first portion of the liner; removing the second portion of the liner based at least in part on exposing the first contact surface, where removing the second portion exposes a second contact surface of a second sacrificial layer of the sacrificial material above the first sacrificial layer; replacing the sacrificial material with metal material; and forming a first conductive pillar above a first contact surface of a first metal layer that replaced the first sacrificial layer, and a second conductive pillar above a second contact surface of a second metal layer that replaced the second sacrificial layer.Aspect 2: The method or apparatus of aspect 1, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for forming the cavity in the set of stacked materials before depositing the liner.Aspect 3: The method or apparatus of any of aspects 1 through 2, where the first liner material includes polysilicon and the first portion of the first liner material is doped with boron.Aspect 4: The method or apparatus of aspect 3, where the second liner material includes tungsten.Aspect 5: The method or apparatus of any of aspects 1 through 4, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing, after removing the first portion of the liner, additional second liner material over the second liner material to increase a thickness of the second liner material.Aspect 6: The method or apparatus of any of aspects 1 through 5, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for removing a section of the second sacrificial layer based at least in part on removing the first portion of the liner, where the first contact surface is exposed based at least in part on removing the section of the second sacrificial layer.Aspect 7: The method or apparatus of any of aspects 1 through 6, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for removing, based at least in part on removing the first portion of the liner, a section of a dielectric layer that is below the second sacrificial layer and above the first sacrificial layer, where the first contact surface is exposed based at least in part on removing the section of the second sacrificial layer.Aspect 8: The method or apparatus of any of aspects 1 through 7, where the set of stacked materials includes a sidewall and, where removing the second portion of the liner exposes a shelf of the sidewall.Aspect 9: The method or apparatus of any of aspects 1 through 8, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing oxide material within the cavity based at least in part on exposing the second contact surface of the second sacrificial layer, where the sacrificial material is replaced with the metal material after depositing the oxide material.Aspect 10: The method or apparatus of aspect 9, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for forming elongated cavities through the oxide material, where the first conductive pillar and the second conductive pillar are each formed within a respective elongated cavity of the elongated cavities.

FIG.4shows a flowchart illustrating a method400that supports staircase formation in a memory array in accordance with examples as disclosed herein. The operations of method400may be implemented by a manufacturing system or one or more controllers associated with a manufacturing system. In some examples, one or more controllers may execute a set of instructions to control one or more functional elements of the manufacturing system to perform the described functions. Additionally, or alternatively, one or more controllers may perform aspects of the described functions using special-purpose hardware.

At405, the method may include forming a cavity within a set of stacked materials including alternating dielectric material and sacrificial material. The operations of405may be performed in accordance with examples as disclosed herein.

At410, the method may include depositing a liner within the cavity. The operations of410may be performed in accordance with examples as disclosed herein.

At415, the method may include doping a first portion of the liner that overlays a first contact surface of a first sacrificial layer of the sacrificial material. The operations of415may be performed in accordance with examples as disclosed herein.

At420, the method may include removing the first portion of the liner and leaving a second portion of the liner based at least in part on doping the first portion. The operations of420may be performed in accordance with examples as disclosed herein.

At425, the method may include exposing the first contact surface of the first sacrificial layer based at least in part on removing the first portion of the liner. The operations of425may be performed in accordance with examples as disclosed herein.

At430, the method may include removing the second portion of the liner to expose a second contact surface of a second sacrificial layer of the sacrificial material. The operations of430may be performed in accordance with examples as disclosed herein.

At435, the method may include replacing the first sacrificial layer with a first metal layer and the second sacrificial layer with a second metal layer. The operations of435may be performed in accordance with examples as disclosed herein.

At440, the method may include forming a first conductive pillar above a first contact surface of the first metal layer and a second conductive pillar above a second contact surface of the second metal layer. The operations of440may be performed in accordance with examples as disclosed herein.

In some examples, an apparatus (e.g., a manufacturing system) as described herein may perform a method or methods, such as the method400. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by one or more controllers to control one or more functional elements of the manufacturing system), or any combination thereof for performing the following aspects of the present disclosure:Aspect 11: A method or apparatus including operations, features, circuitry, logic, means, or instructions, or any combination thereof for forming a cavity within a set of stacked materials including alternating dielectric material and sacrificial material; depositing a liner within the cavity; doping a first portion of the liner that overlays a first contact surface of a first sacrificial layer of the sacrificial material; removing the first portion of the liner and leaving a second portion of the liner based at least in part on doping the first portion; exposing the first contact surface of the first sacrificial layer based at least in part on removing the first portion of the liner; removing the second portion of the liner to expose a second contact surface of a second sacrificial layer of the sacrificial material; replacing the first sacrificial layer with a first metal layer and the second sacrificial layer with a second metal layer; and forming a first conductive pillar above a first contact surface of the first metal layer and a second conductive pillar above a second contact surface of the second metal layer.Aspect 12: The method or apparatus of aspect 11, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for converting the second portion of the liner from a first material to a second material based at least in part on doping the first portion.Aspect 13: The method or apparatus of any of aspects 11 through 12, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing, after removing the first portion of the liner, additional material over the second portion to increase a thickness of the second portion.Aspect 14: The method or apparatus of any of aspects 11 through 13, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for removing a section of the second sacrificial layer based at least in part on removing the first portion of the liner, where the first contact surface is exposed based at least in part on removing the section of the second sacrificial layer.Aspect 15: The method or apparatus of any of aspects 11 through 14, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for removing, based at least in part on removing the first portion of the liner, a section of a dielectric layer that is below the second sacrificial layer and above the first sacrificial layer, where the first contact surface is exposed based at least in part on removing the section of the second sacrificial layer.Aspect 16: The method or apparatus of any of aspects 11 through 15, where the set of stacked materials includes a sidewall and, where and removing the second portion of the liner exposes a shelf of the sidewall.Aspect 17: The method or apparatus of aspects 11 through 16, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for depositing oxide material within the cavity based at least in part on exposing the second contact surface of the second sacrificial layer, where the first sacrificial layer is replaced with the first metal layer after depositing the oxide material, and where the second sacrificial layer is replaced with the second metal layer after depositing the oxide material.Aspect 18: The method or apparatus of aspect 17, further including operations, features, circuitry, logic, means, or instructions, or any combination thereof for forming elongated cavities through the oxide material, where the first conductive pillar and the second conductive pillar are each formed within a respective elongated cavity of the elongated cavities.

An apparatus is described. The following provides an overview of aspects of the apparatus as described herein:Aspect 19: An apparatus, including: a set of stacked materials including alternating dielectric material and metal material; a first word line contact including a first conductive pillar coupled with a first contact surface of a first word line that includes a first metal layer of the metal material; a second word line contact including a second conductive pillar coupled with a second contact surface of a second word line that includes a second metal layer of the metal material that is above the first metal layer; and a sidewall of the set of stacked materials including a shelf at a same height as the first contact surface of the first word line.Aspect 20: The apparatus of aspect 19, including: a word line driver coupled with the second word line contact.Aspect 21: The apparatus of any of aspects 19 through 20, including: an oxide material at least partially surrounding the first conductive pillar and the second conductive pillar.Aspect 22: The apparatus of aspect 21, where the oxide material separates the second conductive pillar from the sidewall and the shelf.Aspect 23: The apparatus of any of aspects 19 through 22, including: a dielectric layer between the first metal layer and the second metal layer.Aspect 24: The apparatus of any of aspects 19 through 23, where the shelf includes a section of the first metal layer.

The term “layer” or “level” used herein refers to a stratum or sheet of a geometrical structure (e.g., relative to a substrate). Each layer or level may have three dimensions (e.g., height, width, and depth) and may cover at least a portion of a surface. For example, a layer or level may be a three dimensional structure where two dimensions are greater than a third, e.g., a thin-film. Layers or levels may include different elements, components, or materials, or combinations thereof. In some examples, one layer or level may be composed of two or more sublayers or sublevels.