Storage device, access method and system utilizing the same

A storage device including a memory array and a peripheral logic circuit is provided. The memory array includes a plurality of banks and a data path. The peripheral logic circuit operates in a copy mode or a normal mode according to a mode-switch command. In the copy mode, the peripheral logic circuit directs a first bank to provide specific data to the data path and directs a second bank to receive specific data from the data path.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority of Taiwan Patent Application No. 108129079, filed on Aug. 15, 2019, the entirety of which is incorporated by reference herein.

BACKGROUND OF THE INVENTION

Field of the Invention

The invention relates to a storage device, and more particularly to a storage device that is capable of copying data from a bank to another bank.

Description of the Related Art

In a conventional access operation, if a memory controller intends to copy data from a first address of a memory to a second address of the memory, the memory controller assigns the first address and then sends a read command to retrieve data of the first address. After the data of the first address has been retrieved by the memory controller, the memory controller assigns the second address and then sends a write command to write the data of the first address to the second address. The conventional access operation however is time consuming.

BRIEF SUMMARY OF THE INVENTION

In accordance with an embodiment, a storage device comprises a memory array and a peripheral logic circuit. The memory array comprises a plurality of banks and a data path. The peripheral logic circuit operates in a copy mode or a normal mode according to a mode-switch command. In the copy mode, the peripheral logic circuit directs a first bank of the plurality of banks to provide specific data to the data path and directs a second bank of the plurality of banks to receive the specific data from the data path.

An exemplary embodiment of an access method for a storage device comprising a plurality of banks is described in the following paragraph. A mode-switch command is received to enter a copy mode or a normal mode. In the copy mode, a first bank of the plurality of banks is directed to provide specific data to a data path and a second bank of the plurality of banks is directed to store the specific data from the data path. In the normal mode, external data is provided to the data path according to a write command, the second bank is directed to store the external data, the first bank is directed to provide the specific data to the data path and the specific data from the data path is output to an external interface.

In one aspect of one implementation of the invention, an access system comprises a controller and a storage device. The controller is configured to generate a mode-switch command. After the controller sends the mode-switch command, the controller generates an activation command and a copy command. The storage device operates according to the mode-switch command, the activation command and the copy command. The storage device comprises a memory array and a peripheral logic circuit. The memory array comprises a plurality of banks and a data path. The data path is coupled to the plurality of banks. The peripheral logic circuit operates in a copy mode or a normal mode according to the mode-switch command. In the copy mode, the peripheral logic circuit directs a first bank of the plurality of banks to provide specific data to the data path and directs a second bank of the plurality of banks to store the specific data from the data path.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1is a schematic diagram of an exemplary embodiment of an access system according to various aspects of the present disclosure. As shown inFIG. 1, the access system100comprises a controller110and a storage device120. The controller110sends different commands to access the storage device120. For example, assuming the controller110intends to read data stored in the storage device120. In such case, the controller110sends a read command CMDRT. If the controller10intends to write data into the storage device120, the controller110sends a write command CMDWR. If the controller110intends to change the operation mode of the storage device120, the controller110sends a mode-switch command CMDMS. In this case, the storage device120operates in a normal mode or in a copy mode according to the mode-switch command CMDMS.

In the normal mode, when the controller110sends the read command CMDRT, the storage device120performs a read operation and provides specific data stored in the storage device120to the controller110. In this mode, when the controller110sends the write command CMDWR, the storage device120performs a write operation to store external data. In the copy mode, the storage device120selects a plurality of addresses according to an activation command CMDATand then copies data from a specific address to another specific address according to a copy command CMDCPsent from the controller110. The type of copy command CMDCPis not limited in the present disclosure. The copy command CMDCPmay be a write command or a read command. In this case, the controller110only sends a command (e.g., a write command or a read command) to direct the storage device120perform a copy operation.

The kind of storage device120is not limited in the present disclosure. In one embodiment, the storage device120is a DRAM. In this embodiment, the storage device120comprises a peripheral logic circuit121and a memory array122. The peripheral logic circuit121decodes the command sent from the controller110to generate a decoded result and accesses the memory array122according to the decoded result.

The memory array122comprises banks B0˜B7and a data path DL. The banks B0˜B7are coupled to the data path DL. The banks B0˜B7may output specific data to the data path DL or receive and store the specific data from the data path DL. In one embodiment, the data path DL is a data bus. Additionally, the number of banks is not limited in the present disclosure. In other embodiments, the memory array122may comprise more banks or fewer banks.

In the normal mode, the peripheral logic circuit121decodes the commands sent from the controller110to determine the type of commands and performs different operations according to the different commands. For example, when the controller110sends the read command CMDRT, the peripheral logic circuit121performs a read operation for the memory array122. The peripheral logic circuit may direct a specific bank of the memory array122to output specific data to the data path DL according to address information of the read command CMDRT. Then, the peripheral logic circuit121reads the specific data from the data path DL and outputs the specific data to the controller110.

In the normal mode, when the controller110sends the write command CMDWR, the peripheral logic circuit121performs a write operation for the memory array122. In this case, the peripheral logic circuit may transmit external data provided by the controller110to the data path DL. The peripheral logic circuit121directs a specific bank of the memory array122to receive and store the specific data from the data path DL according to a write address of the write command CMDWR.

In the copy mode, the peripheral logic circuit performs a copy operation for the memory array122to copy all or a portion of data stored in a specific bank of the memory array122to one or more banks of the memory array122. For example, when the controller110intends to copy data of a first bank of the memory array122to a second bank of the memory array122, the controller110sends the mode-switch command CMDMSto direct the peripheral logic circuit121enters the copy mode.

In the copy mode, the peripheral logic circuit121actives a plurality of banks and serves an active bank as a source bank. Briefly put, assuming the peripheral logic circuit121actives the banks B0and B7and serves the bank B0as a source bank. In such cases, the peripheral logic circuit121directs the bank B0to output specific data to the data path DL. Additionally, the peripheral logic circuit121serves the bank B7as a target bank and directs the bank B7to store the specific data from the data path DL. Since the peripheral logic circuit121does not receive the specific data from the data path DL and does not provide external data to the data path DL, the access time is reduced.

The invention is not limited with regard to the number of target bank. In one embodiment, the peripheral logic circuit121may direct many target banks (e.g., the banks B1and B7) to store the specific data from the data path DL. Since the peripheral logic circuit121can write the specific data into many banks simultaneously, the write time is reduced.

The invention does not limit how the peripheral logic circuit121assigns the source bank and the target bank. In one embodiment, the controller110sends an activation command CMDATto assign which banks to perform a copy operation. In this case, the peripheral logic circuit121decodes the activation command CMDATto generate activation information BNK<7:0> and activates many banks of the memory array122according to the activation information BNK<7:0>.

In one embodiment, the activation information BNK<7:0> has a plurality of bits, each corresponding to a bank. For example, when the value of the activation information BNK<7:0> is 1000 0001, it means that the controller110selects the banks B7and B0. Therefore, the peripheral logic circuit121activates the banks B7and B0. In other embodiments, when the value of the activation information BNK<7:0> is 1000 0011, it means that the controller110selects the banks B7, B1and B0. Therefore, the peripheral logic circuit121activates the banks B7, B1and B0.

Next, the peripheral logic circuit121decodes a copy command CMDCPsent from the controller110to generate source information RCBS<7:0>. The source information RCBS<7:0> is provided to assign one bank among the activated banks as a source bank. In one embodiment, the source information RCBS<7:0> has a plurality of bits, each corresponding to a bank. For example, when the value of the source information RCBS<7:0> is 0000 0001, it means that the controller110intends to copy the data stored in the bank B0. Therefore, the peripheral logic circuit121assigns the bank B0to serve as a source bank according to the source information RCBS<7:0>. In this case, the peripheral logic circuit121directs the bank B0to output specific data to the data path DL. In other embodiments, the peripheral logic circuit121obtains address information according to the copy command CMDCPand enables a portion of bit lines of the bank B0according to the address information to direct the enabled bit lines to output data referred to as the specific data.

Then, the peripheral logic circuit121performs a specific operation for the activation information BNK<7:0> and the source information RCBS<7:0> to obtain at least one target bank among the activated banks. The type of specific operation is not limited in the present disclosure. In one embodiment, any operation can serve as the specific operation, as long as the operation is capable of identifying a source bank and at least one target bank. In this embodiment, the peripheral logic circuit121performs an XOR operation for the activation information BNK<7:0> and the source information RCBS<7:0> to generate write information WCBS<7:0>. In one embodiment, the write information WCBS<7:0> has a plurality of bits each corresponding to a bank.

For example, assuming the value of the write information WCBS<7:0> is 1000 0000 corresponding to the banks B7˜B0respectively. In this case, the bank B7is assigned to serve a target bank. Therefore, the peripheral logic circuit121directs the bank B7to receive the specific data from the data path DL. In some embodiments, when the value of the write information WCBS<7:0> is 1111 1110, it means that the banks B7˜B1serve as target banks. Therefore, the peripheral logic circuit121directs the banks B7˜B1to receive and store the specific data from the data path DL. Since the data stored in a specific bank can be copied to many banks, the data-access efficiency is increased.

FIG. 2is a schematic diagram of an exemplary embodiment of the memory array122according to various aspects of the present disclosure. Briefly put, only banks B1˜B4are shown inFIG. 2, but the disclosure is not limited thereto. Additionally, the structure of the banks B1˜B4are the same. The bank B1is used as an example to describe structure and operation. In this embodiment, the bank B1comprises a row selector211, cells C11˜Cpqand an access circuit231.

The row selector211is coupled to the word lines WL1˜WLpand selects one of the word lines WL1˜WLpaccording to a row enable signal SRE1. In one embodiment, the row enable signal SRE1relates to the activation information BNK<7:0>. For example, when the value of the first specific bit of the activation information BNK<7:0> is 1, it means that the bank B1needs to be activated. Therefore, the peripheral logic circuit121enables a specific word line of the bank B1according to the row enable signal SRE1. In other embodiments, when the values of a first specific bit and a second specific bit of the activation information BNK<7:0> are 1, it means that the banks B1and B2need to be activated. Therefore, the peripheral logic circuit121selects a specific word line (e.g., the word line WL1) coupled to the banks B1and B2via the row enable signals SRE1and SRE2.

In this embodiment, the cells C11˜Cpqare arranged into an array and each cell is coupled to a corresponding word line and a corresponding bit line. For example, the cell C11is coupled to the word line WL1and the bit line BL1to receive and store the data from the bit line BL1according to a turn-on signal from the word line WL1or output data to the bit line BL1according to the turn-on signal from the word line WL1. Since the structures of the cells C11˜Cpqare the same,FIG. 2only shows the structure of the cell C11.

As shown inFIG. 2, the cell C11comprises a storage capacitor221and an access circuit222. The access circuit222comprises an amplifier circuit (not shown). The amplifier circuit amplifies data stored in the storage capacitor221according to a column enable signal RCSL to generate amplified data to the corresponding bit line. In some embodiments, the amplifier circuit in the access circuit222is referred to as a first sense amplifier. In other embodiments, the cells (e.g., C11˜Cp1) coupled to the same bit line (e.g., BL1) shares the same amplifier circuit. Therefore, the cells C11˜Cpqdo not occupy large space in the bank B1.

In one embodiment, the column enable signal RCSL relates to the copy command CMDCP. For example, after the peripheral logic circuit121decodes the copy command CMDCP, the peripheral logic circuit121obtains the source information RCBS<7:0> and address information (i.e., the column enable signal RCSL). The address information is utilized to assign the bit line which is coupled to a bank to be read.

The access circuit231is coupled to the bit lines BL1˜BLqand receives the control signals SSC1and SWC1. In this embodiment, the access circuit231comprises an amplifier circuit240and a write driver250. The amplifier circuit240amplifies the data from the bit lines BL1˜BLqaccording to the control signal SSC1and provides the amplified data to the data path DL. In one embodiment, the amplifier circuit240is referred to as a second sense amplifier (SSA). The write driver250transmits the data from the data path DL to at least one of the bit lines BL1˜BLqaccording to the control signal SWC1.

In one embodiment, the control signal SSC1relates to the source information RCBS<7:0>. For example, assuming the value of a specific bit of the source information RCBS<7:0> is 1 and the specific bit corresponds to the bank B1. In this case, the peripheral logic circuit121enables the control signal SSC1. Therefore, the amplifier circuit240amplifies the data from the bit lines BL1˜BLqand outputs the amplified data to the data path DL.

In other embodiments, the control signal SWC1is related to the write information WCBS<7:0>. For example, assuming that the value of a specific bit of the write information WCBS<7:0> is 1 and the specific bit corresponds to the bank B1, the peripheral logic circuit121enables the control signal SWC1. Therefore, the write driver250transmits the data on the data path DL to the bank B1.

The data path DL comprises paths DL1˜DLqconfigured to receive data from the access circuits231˜234. In one embodiment, the number of paths of the data path DL is the same as the number of bit lines of each bank. In this case, the bit lines BL1˜BLqof the banks B1˜B4are coupled to path DL1˜DLqvia the access circuits231˜234respectively. For example, the bit lines BL1of the banks B1˜B4are coupled to the path DL1, and the bit lines BLqof the banks B1˜B4are coupled to the path DLq.

Assuming that the bank B1is assigned to be a source bank, and the bank B4is assigned to be a target bank. In this case, the row selector221selects one of the word lines WL1˜WLpof the bank B1according to the row enable signal SRE1. Assuming the word line WL1is selected. In this case, when the column enable signal RCSL enables the bit lines BL1˜BLq, the cells C11˜C1qof the bank B1, arranged in a first row (horizontally) are turned on. Therefore, each of the access circuits222in the cells C11˜C1qof the bank B1amplifies data stored in the corresponding storage capacitor221to generate amplified data to the corresponding bit line among the bit lines BL1˜BLq. When the control signal SSC1is enabled, the amplifier circuit240of the bank B1amplifies the amplified data of the bit lines BL1˜BLqto generate specific data to the data path DL. When the control signal SWC4is enabled, the access circuit234of the bank B4transmits data on the data path DL to the bit lines BL1˜BLqof the bank B4.

FIG. 3is a schematic diagram of an exemplary embodiment of the peripheral logic circuit121according to various aspects of the present disclosure. In this embodiment, the peripheral logic circuit121comprises a determining circuit310, a write circuit320and a read circuit330. The determining circuit310controls the write circuit320and the read circuit330according to the kind of the command sent from the controller110. For example, when the controller110intends to copy data from a bank of the memory array122to another bank of the memory array122, the controller110sends the mode-switch command CMDMSto require the write circuit320to enter a copy mode.

In the copy mode, the determining circuit310provides a copy command CMDCPsent from the controller110to the write circuit320or the read circuit330according to the kind of copy command CMDCP. For example, when the copy command CMDCPis a write command, the determining circuit310requires the write circuit320to enter a copy mode and provides the copy command CMDCPto the write circuit320. However, when the copy command CMDCPis a read command, the determining circuit310requires the read circuit330to enter a copy mode and provides the copy command CMDCPto the read circuit330.

In other embodiments, the determining circuit310decodes the activation command CMDATto generate and output the activation information BNK<7:0>. In this case, the activation information BNK<7:0> is utilized to activate a plurality of banks. In some embodiments, the determining circuit310outputs the activation command CMDATto the write circuit320or the read circuit330. In this case, the write circuit320or the read circuit330decodes the activation command CMDATto generate and output the activation information BNK<7:0>.

In one embodiment, the write circuit320comprises a command decoder circuit321and a counter322. In the copy mode, the command decoder circuit321decodes the copy command CMDCPto generate source information RCBS<7:0> and the column enable signal RCSL. The source information RCBS<7:0> is utilized to assign a source bank among the activated banks. The column enable signal RCSL is address information to select at least one of the word lines and at least one of the bit lines of the source bank.

The counter322is configured to provide the control signals SSC1˜SSC4and SWC1˜SWC4. In the copy mode, after receiving the column enable signal RCSL, the counter322starts counting. When a first count value of the counter322reaches a first predetermined value, the counter322enables one of the control signals SSC1˜SSC4to turn on the amplifier function of the corresponding access circuit. TakingFIG. 2as an example, when the counter322enables the control signal SSC1, the amplifier circuit240of the access circuit231amplifies the data stored in the bank B1to generate amplified data and output the amplified data to the data path DL.

When a second count value of the counter322reaches a second predetermined value, the counter322enables one of the control signals SWC1˜SWC4to turn on the write function of the corresponding access circuit. TakingFIG. 2as an example, when the counter322enables the control signal SWC4, the write driver (not shown) of the access circuit234transmits the specific data on the data path DL to the bank B4.

In other embodiments, the read circuit330comprises a command decoder circuit331and delay circuits332and333. In the copy mode, the command decoder circuit331decodes the copy command CMDCPto generate the source information RCBS<7:0> and the column enable signal RCSL. Since the operation of the command decoder circuit331is the same as the operation of the command decoder circuit321, the description of the operation of the command decoder circuit331is omitted.

The delay circuit332delays the column enable signal RCSL to enable one of the control signals SSC1˜SSC4. The control signals SSC1˜SSC4are utilized to turn on the amplifier function of the access circuit of the source bank. The delay circuit333delays the control signals SSC1˜SSC4to generate the control signals SWC1˜SWC4. The control signals SWC1˜SWC4are utilized to turn on the write function of the access circuit of the target bank.

In other embodiments, the determining circuit310may operate in a normal mode according to the mode-switch command CMDMS. In the normal mode, the determining circuit310enables the write circuit320or the read circuit330. For example, when the determining circuit310receives the write command CMDWR, the determining circuit310enables the write circuit320and requires the write circuit320to operate in a normal mode. In the normal mode, the command decoder circuit321decodes the write command CMDWRto generate address information ADD. The address information ADD is utilized to assign a specific address. When the counter322receives the address information ADD, the counter322starts counting. When the count value of the counter322reaches a predetermined value, the counter322outputs the control signals SWC1˜SWC4to turn on the write function of the access circuits231˜234shown inFIG. 2. Taking the bank B1ofFIG. 2as an example, when the write function of the access circuit231is turned on, the write driver250writes the data (referred to as external data) on the data path DL into the bank B1.

In the normal mode, if the determining circuit310receives the read command CMDRT, the determining circuit310enables the read circuit330and requires the read circuit330to operate in a normal mode. In the normal mode, the command decoder circuit331decodes the read command CMDRTto generate address information ADD. The address information ADD is utilized to assign a specific address. The delay circuit332delays the address information ADD to generate the control signals SSC1˜SSC4to turn on the amplifier functions of the access circuits231˜234shown inFIG. 2. Taking the bank B1ofFIG. 2as an example, when the amplifier function of the access circuit231is turned on, the amplifier circuit240amplifies the data of the specific address and transmits the amplified result to the data path DL.

FIG. 4is a flowchart of an exemplary embodiment of an access method according to various aspects of the present disclosure. The access method is applied to a storage device. In one embodiment, the storage device comprises a plurality of banks. The banks are coupled to a data path.

First, an external command is received and decoded (step S411). In one embodiment, the storage device comprises a peripheral logic circuit configured to decode the external command. The external command may be provided by a controller. In this case, the controller is disposed out of the storage device.

A determination is made as to whether the external command requires the storage device to enter a copy mode (step S412). When the external command does not require the storage device to enter the copy mode, the peripheral logic circuit determines whether the external command is a read command (step S413). When the external command is not a read command, it means that the external command is a write command. Therefore, the peripheral logic circuit performs a write operation to write external data into the corresponding banks (step S414). In one embodiment, the peripheral logic circuit transmits external data provided by an external controller to the data path and directs the corresponding bank to store the external data from the data path.

When the external command is a read command, the peripheral logic circuit performs a read operation to retrieve data stored in a specific bank and outputs the data to an external controller (step S415). In one embodiment, the peripheral logic circuit directs the specific bank to output specific data to the data path. In this case, the peripheral logic circuit retrieves the specific data from the data path and provides the specific data to an external controller.

When the external command directs the storage device to enter a copy mode, a first bank among the banks provides specific data to the data path (step S416). In one embodiment, the external controller sends an activation command. In such cases, the peripheral logic circuit decodes the activation command to generate activation information (step S417). In one embodiment, the activation information has a plurality of bits. Each of the bits of the activation information corresponds to a bank.

Many banks are activated according to the activation information (step S418). For example, when the value of a specific bit of the activation information is 1, it means that the corresponding bank needs to be activated. Therefore, the peripheral logic circuit activates the corresponding bank corresponding to the specific bit. Briefly put, assuming the peripheral logic circuit activates a first bank and a second bank. Additionally, the external controller sends a copy command. In this case, the peripheral logic circuit decodes the copy command to generate source information (step S419).

One of the activated banks outputs specific data to the data path according to the source information (Step S420). In one embodiment, the source information has many bits. Each of the bits of the source information corresponds to a bank. For example, when the value of a specific bit of the source information is 1, it means that the bank corresponding to the specific bit of the source information is a source bank. Therefore, the peripheral logic circuit directs the source bank to output specific data according to the source information. In one embodiment, the peripheral logic circuit further generates address information according to the copy command and enables many bit lines coupled to the source bank according to the address information. In this case, a first sense amplifier coupled to the bit lines amplifies the data stored in the cells coupled to the bit lines to generate amplified data. Next, a second sense amplifier amplifies the amplified data to generate the specific data.

The second bank of the banks is directed to receive the specific data from the data path (step S421). In one embodiment, the peripheral logic circuit assigns at least one of the banks among the activated banks to serve as a target bank according to the activation information and the source information (step S422). In this embodiment, the peripheral logic circuit performs an XOR operation for the activation information and the source information to generate write information.

The peripheral logic circuit directs the target bank to store specific data from the data path according to the write information (step S423). In one embodiment, after the second sense amplifier provides the specific data to the data path, the peripheral logic circuit directs the target bank to store specific data from the data path.

In other embodiments, the peripheral logic circuit may direct many activated banks to simultaneously store the specific data from the data path according to the write information. Therefore, the access time of the storage device can be reduced. Furthermore, since the peripheral logic circuit does not receive external data to be stored in the target bank from an external interface, the process of writing data to the storage device is simplified.