Alignment mark design for packages

A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.

BACKGROUND

The fabrication of modern circuits typically involves several steps. Integrated circuits are first fabricated on a semiconductor wafer, which contains multiple duplicated semiconductor chips, each comprising integrated circuits. The semiconductor chips are then sawed from the wafer and packaged. The packaging processes have two main purposes: to protect delicate semiconductor chips and connect interior integrated circuits to exterior pins.

With the increasing demand for more functions, Package-on-Package (PoP) technology, in which two or more packages are bonded to expand the integration ability of the packages, was developed. With a high degree of integration, the electrical performance of the resulting PoP package is improved due to the shortened connecting paths between components. By using PoP technology, package design becomes more flexible and less complex. Time-to-market is also reduced.

BRIEF SUMMARY OF THE INVENTION

In accordance with some aspect of the present disclosure, a package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.

Other embodiments are also disclosed.

The advantageous features of the present disclosure include improved accuracy in alignment without incurring additional manufacturing cost.

DETAILED DESCRIPTION

FIGS. 1 through 14illustrate the cross-sectional views and top views of intermediate stages in the manufacturing of a package in accordance with embodiments. The steps shown inFIG. 1 through 14are also illustrated schematically in the process flow300shown inFIG. 20. In the subsequent discussion, the process steps shown inFIGS. 1 through 14are discussed, referring to the process steps inFIG. 20.

FIG. 1illustrates carrier20and release layer22formed on carrier20. Carrier20may be a glass carrier, a ceramic carrier, or the like. Carrier20may have a round top-view shape and may be a size of a silicon wafer. For example, carrier20may have an 8-inch diameter, a 12-inch diameter, or the like. Release layer22may be formed of a polymer-based material (such as a Light To Heat Conversion (LTHC) material), which may be removed along with carrier20from the overlying structures that will be formed in subsequent steps. In some embodiments, release layer22is formed of an epoxy-based thermal-release material. In other embodiments, release layer22is formed of an ultra-violet (UV) glue. Release layer22may be dispensed as a liquid and cured. In alternative embodiments, release layer22is a laminate film and is laminated onto carrier20. The top surface of release layer22is leveled and has a high degree of co-planarity.

Dielectric layer24is formed on release layer22. In some embodiments, dielectric layer24is formed of a polymer, which may also be a photo-sensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like, that may be easily patterned using a photo lithography process. In alternative embodiments, dielectric layer24is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PhosphoSilicate Glass (PSG), BoroSilicate Glass (BSG), Boron-doped PhosphoSilicate Glass (BPSG), or the like.

Referring toFIG. 2, Redistribution Lines (RDLs)26are formed over dielectric layer24. RDLs26are also referred to as backside RDLs since they are located on the backside of device die36(FIG. 5A). RDLs26may include RDLs26B and may or may not include RDL(s)26A, which, if formed, will be electrically coupled to the subsequently formed alignment marks. The formation of RDLs26may include forming a seed layer (not shown) over dielectric layer24, forming a patterned mask (not shown) such as photo resist over the seed layer, and then performing a metal plating on the exposed seed layer. The patterned mask and the portions of the seed layer covered by the patterned mask are then removed, leaving RDLs26as inFIG. 2. In some embodiments, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed using, for example, Physical Vapor Deposition (PVD). The plating may be performed using, for example, electroless plating.

Referring toFIG. 3, dielectric layer28is formed on RDLs26. The bottom surface of dielectric layer28may be in contact with the top surfaces of RDLs26and dielectric layer24. In some embodiments, dielectric layer28is formed of a polymer, which may be a photo-sensitive material such as PBO, polyimide, BCB, or the like. In alternative embodiments, dielectric layer28is formed of a nitride such as silicon nitride, an oxide such as silicon oxide, PSG, BSG, BPSG, or the like. Dielectric layer28is then patterned to form openings30therein. Hence, RDLs26are exposed through the openings30in dielectric layer28. Openings30include30B and may or may not include30A. For example, if RDLs26A are not formed, opening30A is also not formed.

Referring toFIG. 4A, metal posts32(including32A and32B) are formed. Throughout the description, metal posts32are alternatively referred to as through-vias32since metal posts32penetrate through the subsequently formed molding material. In accordance with some embodiments of the present disclosure, through-vias32are formed by plating. The plating of through-vias32may include forming a blanket seed layer (schematically illustrated as31) over layer28and extending into openings30, forming and patterning photo resist33, and plating through-vias32on the portions of seed layer that are exposed through the openings in photo resist33. Photo resist33and the portions of seed layer31that were covered by photo resist33are then removed, and hence are shown using dashed lines. The material of through-vias32may include copper, aluminum, or the like. Through-vias32have the shape of rods. The top-view shapes of through-vias32may be circles, rectangles, squares, hexagons, or the like.

Through-vias32includes32A and32B.FIG. 4Billustrates a top view of through-vias32A and32B. In some embodiments, through-vias32B are arranged as rows and columns. The outer boundaries of the outmost through-vias32B may define region34, which will be referred to as design area34hereinafter. No through-via32B and RDL will be formed outside of design area34, and no device die will be placed outside of design area34. Through-vias32B are used for electrically inter-coupling features on the opposite ends of through-vias32B. Through-vias32A, on the other hand, are used as alignment marks and hence are sometimes referred to as alignment marks32A. Through-vias32A may not be used for electrical coupling of devices and features.

In accordance with some embodiments of the present disclosure, through-vias32A are placed outside design area34. In accordance with alternative embodiments, through-vias32A may also be placed inside design area34. In some embodiments, through-vias32A may have a different top-view shape and/or size from through-vias32B for easy identification. For example, as shown inFIG. 4B, through-vias32A have a rectangular or a square top-view shape, while through-vias32B have a round top-view shape.

FIG. 5Aillustrates the placement of device dies36. Device die36is adhered to dielectric layer28through Die-Attach Film (DAF)45, which may be an adhesive film. Device die36may be a logic device die including logic transistors therein. In some exemplary embodiments, device die36is a die designed for mobile applications and may be a Power Management Integrated Circuit (PMIC) die, a Transceiver (TRX) die, or the like. Although one device die36is illustrated, more device dies may be placed over dielectric layer28.

In some exemplary embodiments, metal pillar(s)38(such as a copper post) are pre-formed as the topmost portion of device die36, wherein metal pillar38is electrically coupled to the integrated circuit devices such as transistors in device die36. In some embodiments, a polymer fills the gaps between neighboring metal pillars38to form top dielectric layer40, wherein top dielectric layer40may also be on top of and contact passivation layer42. Polymer layer40may be formed of PBO in some embodiments. In some embodiments, passivation layer42comprises silicon nitride, silicon oxynitride, silicon oxide, or multi-layers thereof.

Next, molding material44is molded on device die36. Molding material44fills the gaps between neighboring through-vias32and the gaps between through-vias32and device die36. Molding material44may include a molding compound, a molding underfill, an epoxy, or a resin. The top surface of molding material44is higher than the top ends of metal pillar38.

Next, a planarization such as a Chemical Mechanical Polish (CMP) step or a grinding step is performed to thin molding material44until through-vias32and metal pillar38are exposed. Due to the grinding, the top ends of through-vias32are substantially level (coplanar) with the top surfaces of metal pillars38, and are substantially coplanar with the top surface of molding material44.

FIG. 5Bschematically illustrates a top view of the structure inFIG. 5A. In the placement of device die36, alignment marks32A are used to align the position of device die36to ensure device die36is placed at the desirable location and that device die36does not shift or rotate from its intended position and direction. The alignment is performed by determining the relative position of device die36relative to the positions of alignment marks32A.

FIG. 5Cillustrates a top view including more device die36and through-vias32placed on carrier20, which has a round shape in the top view. Similar to the formation of device dies, the structure that is formed in accordance with the embodiments of the present disclosure is to be sawed as a plurality of packages, each including a device die36and its surrounding through-vias32. The placement of each of the device dies36may be aligned through aligning to the corresponding alignment marks32A in the same package.

Referring toFIG. 6, dielectric layer46is formed. In some embodiments, dielectric layer46is formed of a polymer such as PBO, polyimide, or the like. In alternative embodiments, dielectric layer46is formed of silicon nitride, silicon oxide, or the like. Openings48are formed in dielectric layer46to expose through-vias32B and metal pillars38. The formation of openings48may be performed through a photo lithography process. In accordance with some embodiments of the present disclosure, no openings are formed over through-vias32A, and hence through-vias32A are not exposed. In alternative embodiments, through-vias32A may be exposed through some openings48.

In accordance with some embodiments, the formation of openings48is also performed using alignment marks32A as alignment marks so that openings48may be accurately aligned to the respective through-vias32and metal pillar38.

Next, referring toFIG. 7, Redistribution Lines (RDLs)50are formed to connect to metal pillar38and through-vias32B. RDLs50may also interconnect metal pillar38and through-vias32B. RDLs50include metal traces (metal lines) over dielectric layer46as well as vias extending into openings48to electrically connect to through-vias32B and metal pillar38. In some embodiments, RDLs50are formed in a plating process, wherein each of RDLs50includes a seed layer (not shown) and a plated metallic material over the seed layer. The seed layer and the plated material may be formed of the same material or different materials. RDLs50may comprise a metal or a metal alloy including aluminum, copper, tungsten, and alloys thereof.

Referring toFIG. 8, dielectric layer52is formed over RDLs50and dielectric layer46. Dielectric layer52may be formed using a polymer, which may be selected from the same candidate materials as those of dielectric layer46. For example, dielectric layers52may comprise PBO, polyimide, BCB, or the like. Alternatively, dielectric layer52may include non-organic dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or the like. Opening(s)54are also formed in dielectric layer52to expose RDLs50. The formation of openings54may be performed through a photo lithography process.

FIG. 9illustrates the formation of RDLs56, which are electrically connected to RDLs50through opening(s)54(FIG. 8). The formation of RDLs56may adopt similar methods and materials to those for forming RDLs50. RDLs50and56are also referred to as front-side RDLs since they are located on the front side of device die36.

As shown inFIG. 10, an additional dielectric layer57, which may be polymer, is formed to cover RDLs56and dielectric layer52. Dielectric layer57may also be a polymer, which is selected from the same candidate polymers used for forming dielectric layers46and52. Opening(s)57are then formed in dielectric layer57to expose the metal pad portions of RDLs56.

FIG. 11illustrates the formation of Under-Bump Metallurgies (UBMs)60and electrical connectors62in accordance with some exemplary embodiments. The formation of UBMs60may include deposition and patterning. The formation of electrical connectors62may include placing solder balls on the exposed portions of UBMs60and then reflowing the solder balls. In alternative embodiments, the formation of electrical connectors62includes performing a plating step to form solder regions over RDLs56and then reflowing the solder regions. Electrical connectors62may also include metal pillars or metal pillars and solder caps, which may also be formed through plating. Throughout the description, the combined structure, including device die36, through-vias32, molding material44, and the corresponding RDLs and dielectric layers on the opposite sides of molding material44, will be referred to as package100, which may be a composite wafer with a round top-view shape.

Next, package100is de-bonded from carrier20. Adhesive layer22is also cleaned from package100. The resulting structure is shown inFIG. 12. The de-bonding may be performed by projecting a light such as UV light or laser on adhesive layer22to decompose adhesive layer22. In some embodiments, package100is further adhered to carrier64through adhesive66, wherein electrical connectors62face, and may contact, adhesive66.

Tape68is then adhered onto dielectric layer24, which is exposed. Laser marking is then performed on tape68to form identification marks70. Identification marks70are hence the recesses in tape68and may carry the identification information of the respective package. Identification marks70may include letters, number, or other identifiable patterns. The formation of identification marks70may be performed through laser drilling.

Referring toFIG. 13, openings72are formed in tape68and dielectric layer24, and hence the metal pad portions of RDLs56are exposed to openings72. The formation of openings72may be performed through laser drilling or photo lithography processes.

In subsequent steps, carrier64and adhesive66are removed from package100. A die saw step is performed to saw package100into a plurality of packages102, each including device die36, through-vias32B, and alignment marks32A. In the die-saw step in accordance with some embodiments, kerves74are kept away from alignment marks32A. Accordingly, the resulting package102includes both alignment marks32A and through-vias32B.

FIG. 14illustrates the bonding of package102with another package200. In accordance with some embodiments, the bonding is performed through solder regions76, which join the metal pads in RDLs26B to the metal pads in the overlying package200. In some embodiments, package200includes device dies202, which may be memory dies such as Static Random Access Memory (SRAM) dies, Dynamic Random Access Memory (DRAM) dies, or the like. The memory dies may also be bonded to package substrate204in some exemplary embodiments.

In the package102as shown inFIG. 13 or 14, alignment marks32A may be electrically insulated from the integrated circuit devices in package102and200. Alignment marks32A may be electrically floating in some embodiments. In accordance with some embodiments, as shown inFIG. 14, through-via(s)32A may be physically connected to some metal features, such as RDL(s)26A. In alternative embodiments, the metal features in the dashed region78are not formed. This may be achieved by not forming RDL26A inFIG. 2and opening30A inFIG. 3. When the metal features RDLs26A are not formed, the entireties of the opposite surfaces (the illustrated top surface and bottom surface) of alignment mark32A are not in contact with any conductive feature. Furthermore, each of alignment mark32A and all of the conductive features (such as RDL26A, if any) that are electrically connected to the alignment mark32A as a whole may be fully insulated inside package102by dielectric layers and molding material44.

FIG. 15schematically illustrates a top view of package100(FIG. 13), and the packages102in package100. The relative sizes of packages102(relative to the size of package100) are exaggerated in order to show the details of through-vias32B and alignment marks32A. As shown inFIG. 15, packages102are separated from each other by scribe lines104, which are the regions in which the sawing kerves must pass through. The actual kerves are illustrated as106and are narrower than scribe lines104. The widths of kerves106and scribe lines104are designed so that, with the variation in the sawing of package100, kerves106are still within scribe lines104.

Alignment marks32A are outside of scribe lines104and hence will not be sawed. This is advantageous since alignment marks32A have a height equal to the thickness of device die36(FIG. 13) and have large volumes, and hence alignment marks32A may adversely affect the sawing process. On the other hand, alignment marks32A are outside of design area34and hence can be easily identified during the alignment process.

In accordance with some embodiments, diameter D1(or the length and the width of through-vias32B) is in the range between about 150 μm and about 300 μm. The length L1and width W1of alignment marks32A are in the range between about 100 μm and about 300 μm. Distance D2and D3between alignment marks32A and scribe lines104are equal to or greater than the respective length L1and width W1of alignment marks32A. It is appreciated, however, that the values recited throughout the description are merely examples and may be changed to different values.

In the embodiments shown inFIG. 15, in each of packages102, there are two alignment marks32A placed diagonally, wherein the alignment marks32A are adjacent to opposite corners of package102.FIG. 16illustrates the top view of package102in accordance with alternative embodiments, wherein two alignment marks32A are formed adjacent to two corners of package102, wherein the two corners are neighboring corners formed by a same edge of package102. In the embodiments inFIG. 17, alignment marks32A are formed adjacent to each of the four corners of package102.

FIG. 18illustrates the top view of package102in accordance with yet alternative embodiments, in which package102includes two or more device dies. For example, in the illustrated exemplary package102, there are two device dies36, each encircled by a plurality of through-vias32B that form a ring. A joined design area34includes both device dies36and the respective surrounding through-vias32B therein. Alignment marks32A are again placed outside of the joined design area34.

InFIG. 18, two device dies36are aligned with a straight line parallel to an edge of the respective package102.FIG. 19illustrates the top view of package102, wherein device dies36are misaligned. In these embodiments, design area34is not a simple rectangular region. Rather, design area34includes two rectangular regions joined to each other.

In each ofFIGS. 15 through 19, alignment marks32A are also used for the alignment in the formation of the respective packages102. The alignment process may be found referring toFIGS. 6 and 7.

FIG. 20schematically illustrates the process flow300for the processes inFIGS. 1 through 14. The process flow is briefly discussed herein. The details of the process flow may be found in the discussion ofFIGS. 1 through 14. In step302, backside RDLs26are formed on a carrier, as shown inFIGS. 1 through 3. In step304of the process flow inFIG. 20, through-vias32B and alignment marks32A are formed to connect to the backside RDLs26, and the respective formation process is illustrated inFIGS. 4A and 4B. In step306of the process flow inFIG. 20, device die36is placed, and the respective formation process is illustrated inFIGS. 5A, 5B, and 5C. The placement of device die36is performed using alignment marks32A for alignment. In step308and310of the process flow inFIG. 20, front-side RDLs50and56are formed, and the respective formation process is illustrated inFIGS. 6 through 9. The formation of openings in the bottom dielectric layer may also be performed using alignment marks32A for alignment. In step312of the process flow inFIG. 20, UBMs60and solder regions62are formed, and the respective formation process is illustrated inFIGS. 10 and 11. In step314of the process flow inFIG. 20, tape68is adhered to the backside of the respective package, and the respective formation process is illustrated inFIG. 12. In step316of the process flow inFIG. 20, openings are formed, with UBMs and solder regions formed. The packages are sawed, and a further bonding process is performed. The respective formation process is illustrated inFIGS. 13 and 14.

The embodiments of the present disclosure have some advantageous features. By forming the alignment marks for each of the plurality of packages, the device dies may be accurately placed. The shifting and the rotation of the device dies relative to the through-vias are thus substantially eliminated or at least reduced. Furthermore, the alignment marks are formed at the same time the through-vias (for electrical connections) are formed, and hence no extra manufacturing cost is incurred.

In accordance with some embodiments of the present disclosure, a package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.

In accordance with alternative embodiments of the present disclosure, a package includes a device die including a metal pillar at a surface of the device die, a plurality of through-vias surrounding the device die, and an alignment mark. The alignment mark is electrically floating. A molding material molds the device die, the alignment mark, and the plurality of through-vias therein. A first plurality of redistribution lines is on a first side of the molding material. A second plurality of redistribution lines is on a second side of the molding material, with the second side being opposite to the first side. The first plurality of redistribution lines is electrically coupled to the second plurality of redistribution lines through the plurality of through-vias.

In accordance with yet alternative embodiments of the present disclosure, a method includes forming a through-via and an alignment mark simultaneously as well as placing a device die adjacent to the through-via and the alignment mark. The step of placing is performed using the alignment mark for alignment. The method further includes molding the through-via, the alignment mark, and the device die in a molding material and performing a planarization to expose the through-via, the alignment mark, and a metal pillar of the device die. A plurality of redistribution lines is formed to electrically connect to the through-via and the metal pillar of the device die.