Systems and methods for multi-pass alternate decoding

Various embodiments of the present invention provide systems and methods for data processing. For example, data decoding systems are disclosed that include a data decoder circuit and a decode value modification circuit.

BACKGROUND OF THE INVENTION

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data decoding.

Various storage systems include data processing circuitry implemented with a data decoding circuit. In some cases, a belief propagation based decoder circuit is used. In such cases where high rate low density parity check codes are used, an error floor is more severe because short cycles are unavoidable. Such short cycles make the messages in the belief propagation decoder correlate quickly and degrade the performance. In contrast, a maximum likelihood decoder may be used as it does not exhibit the same limitations. However, such maximum likelihood decoders are typically too complex for practical implementation.

Hence, for at least the aforementioned reasons, there exists a need in the art for advanced systems and methods for data processing.

BRIEF SUMMARY OF THE INVENTION

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data decoding.

Various embodiments of the present invention provide data decoding systems that include: a data decoder circuit and a decode value modification circuit. The data decoder circuit is operable to: apply a data decode algorithm to a decoder input to yield a first decoded output and an indication of at least one point of failure of the first decoded output, apply the data decode algorithm to the decoder input guided by a first modified decode output to yield a second decoded output and an indication of at least one point of failure of the second decoded output, and apply the data decode algorithm to the decoder input guided by a second modified decode output to yield a third decoded output and an indication of at least one point of failure of the third decoded output. The decode value modification circuit is operable to: identify a first symbol of the first decoded output associated with the point of failure of the first decoded output, and to modify a subset of values associated with the identified symbol to yield the first modified decode output; and identify a second symbol of the second decoded output associated with the point of failure of the second decoded output, and to modify a subset of values associated with the identified first symbol and the identified second symbol to yield the second modified decode output. In some instances of the aforementioned embodiments, the data decoding system is implemented as part of a storage device or a receiving device. In various instances of the aforementioned embodiments, the data decoding system is implemented as part of an integrated circuit.

In some instances of the aforementioned embodiments, the data decode algorithm is a low density parity check algorithm, and the point of failure of the first decoded output is a failure of a parity check equation implemented as part of the low density parity check algorithm. In some such instances, the low density parity check algorithm is a non-binary low density parity check algorithm, and in other such instances the low density parity check algorithm is a binary low density parity check algorithm. In particular cases, the low density parity check algorithm is implemented as a belief propagation data decode algorithm.

In various instances of the aforementioned embodiments, the decode value modification circuit includes a partial maximum likelihood decode algorithm to identify the first symbol and the second symbol. In some such instances, the decode value modification circuit includes: a syndrome calculation circuit operable to calculate a syndrome based upon a number of symbols associated with the point of failure of the first decoded output; an array calculator circuit operable to calculate an array of possible hard decision values across the contributors to the point of failure of the first decoded output; and an index identifier circuit operable to determine a candidate from the array as the identified symbol. In particular cases, the decode value modification circuit includes further includes: a likely symbol value selector circuit operable to determine whether the subset of values associated with the identified symbol includes one log likelihood ratio value or two log likelihood ratio values.

In one or more instances of the aforementioned embodiments, the data decoder circuit further includes a multi-pass controller circuit operable to selectively control generation of the first modified decode output and the second modified decode output. In particular cases, the controller circuit enables generation of the first modified decode output when: a number of iterations of the data decoder circuit applying the data decode algorithm to the decoder input is greater than a first threshold value; a number of points of failure corresponding to the first decoded output is less than a second threshold value; and the number of points of failure corresponding to the first decoded output is the same as the number of points of failure corresponding to a previous decoded output.

Other embodiments of the present invention provide methods for data decoding that include: applying a data decode algorithm by a data decoder circuit to a decoder input to yield a first decoded output and an indication of at least one point of failure of the first decoded output; identifying at least a first symbol and a second symbol associated with the point of failure of the first decoded output; modifying at least one of the first symbol and the second symbol to yield a first modification; modifying the first decoded output to incorporate the first modification to yield a first modified decode output; applying the data decode algorithm to the decoder input guided by the first modified decode output to yield a second decoded output; identifying at least a third symbol and a fourth symbol associated with the point of failure of the second decoded output; modifying at least one of the third symbol and the fourth symbol to yield a second modification; and modifying the second decoded output to incorporate the first modification and the second modification to yield a second modified decode output. In some cases, the methods further include applying the data decode algorithm to the decoder input guided by the first modified decode output to yield a third decoded output.

In various instances, modifying at least one of the first symbol and the second symbol to yield the first modification includes: calculating a syndrome including the first symbol and the second symbol; calculating an array of possible hard decision values across the contributors to the point of failure of the first decoded output; determining an index corresponding to a candidate from the array as an identified symbol; determining a subset values associated with the identified symbol to be modified; modifying the subset of values to yield a modified decoded output; and applying the data decode algorithm by the data decoder circuit to the decoder input guided by the modified decoded output to yield a second decoded output.

This summary provides only a general outline of some embodiments of the invention. Many other objects, features, advantages and other embodiments of the invention will become more fully apparent from the following detailed description, the appended claims and the accompanying drawings.

DETAILED DESCRIPTION OF THE INVENTION

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data decoding.

Various embodiments of the present invention provide data processing systems that include a data decoder circuit having a low complexity decoder circuit and a partial maximum likelihood decode value modification circuit that is selectively used to modify an output of the belief propagation decoder circuit across multiple passes when a potential trapping set is detected. As just one of many advantages, the aforementioned approach allows for using data decoder circuits that exhibit relatively low complexity such as, for example, a belief propagation decoder circuit, while using another decoder algorithm to correct errors that are not correctable by the low complexity decoder algorithm. As the errors to be corrected are localized by the belief propagation decoder circuit, the complexity of the other decoder circuit may be very low.

In some cases, selective modification of an output of the low density parity check decoder circuit is done based upon some conclusions about a subset of uncorrectable errors. In particular, it has been determined that: every unsatisfied checks is connected by one error symbol, the error symbol has the most significant ambiguity among all variable nodes associated with an unsatisfied checks, and the second most likely symbol associated with the error symbol is almost always the correct symbol. Based upon this, some embodiments of the present invention identify uncorrectable errors that seem to correspond to the above criteria, and modify the error symbol to use the second most likely value on a first pass. In some cases, the uncorrectable error condition is referred to as a potential trapping set condition. Subsequent to the modification, the belief propagation decoding is performed anew using the modified symbol to yield another output, and the output generated by the belief propagation decoding are used to determine another set of symbols to be modified on a second pass. Then, the belief propagation decoding is performed on the data set including modified symbols that were identified on both the first pass and the second pass.

Turning toFIG. 1a, a data processing circuit100is shown that includes a data decoding circuit170including a combination of a low complexity decoder circuit166and a multi-pass partial maximum likelihood decode value modification circuit168in accordance with one or more embodiments of the present invention. Low complexity decoder circuit166may be any decoder circuit known in the art that is less complex to implement than a maximum likelihood decoder circuit. In some cases, low complexity decoder circuit166is a belief propagation decoder circuit as are known in the art. Such a belief propagation data decoder circuit may be implemented similar to that discussed in Pearl, Judea, “REVEREND BAYES ON INFERENCE ENGINES: A DISTRIBUTED HIERARCHAL APPROACH”, AAAI-82 Proceedings, 1982. The entirety of the aforementioned reference is incorporated herein by reference for all purposes. Data processing circuit100includes an analog front end circuit110that receives an analog signal105. Analog front end circuit110processes analog signal105and provides a processed analog signal112to an analog to digital converter circuit114. Analog front end circuit110may include, but is not limited to, an analog filter and an amplifier circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of circuitry that may be included as part of analog front end circuit110. In some cases, analog signal105is derived from a read/write head assembly (not shown) that is disposed in relation to a storage medium (not shown). In other cases, analog signal105is derived from a receiver circuit (not shown) that is operable to receive a signal from a transmission medium (not shown). The transmission medium may be wired or wireless. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of source from which analog input105may be derived.

Analog to digital converter circuit114converts processed analog signal112into a corresponding series of digital samples116. Analog to digital converter circuit114may be any circuit known in the art that is capable of producing digital samples corresponding to an analog input signal. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of analog to digital converter circuits that may be used in relation to different embodiments of the present invention. Digital samples116are provided to an equalizer circuit120. Equalizer circuit120applies an equalization algorithm to digital samples116to yield an equalized output125. In some embodiments of the present invention, equalizer circuit120is a digital finite impulse response filter circuit as are known in the art. In some cases, equalizer120includes sufficient memory to maintain one or more codewords until a data detector circuit130is available for processing, and for multiple processes through data detector circuit130.

Data detector circuit130is operable to apply a data detection algorithm to a received codeword or data set, and in some cases data detector circuit130can process two or more codewords in parallel. In some embodiments of the present invention, data detector circuit130is a Viterbi algorithm data detector circuit as are known in the art. In other embodiments of the present invention, data detector circuit130is a maximum a posteriori data detector circuit as are known in the art. Of note, the general phrases “Viterbi data detection algorithm” or “Viterbi algorithm data detector circuit” are used in their broadest sense to mean any Viterbi detection algorithm or Viterbi algorithm detector circuit or variations thereof including, but not limited to, bi-direction Viterbi detection algorithm or bi-direction Viterbi algorithm detector circuit. Also, the general phrases “maximum a posteriori data detection algorithm” or “maximum a posteriori data detector circuit” are used in their broadest sense to mean any maximum a posteriori detection algorithm or detector circuit or variations thereof including, but not limited to, simplified maximum a posteriori data detection algorithm and a max-log maximum a posteriori data detection algorithm, or corresponding detector circuits. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of data detector circuits that may be used in relation to different embodiments of the present invention. Data detector circuit130is started based upon availability of a data set from equalizer circuit120or from a central memory circuit150.

Upon completion, data detector circuit130provides a detector output196. Detector output196includes soft data. As used herein, the phrase “soft data” is used in its broadest sense to mean reliability data with each instance of the reliability data indicating a likelihood that a corresponding bit position or group of bit positions has been correctly detected. In some embodiments of the present invention, the soft data or reliability data is log likelihood ratio data as is known in the art. Detected output196is provided to a local interleaver circuit142. Local interleaver circuit142is operable to shuffle sub-portions (i.e., local chunks) of the data set included as detected output and provides an interleaved codeword146that is stored to central memory circuit150. Interleaver circuit142may be any circuit known in the art that is capable of shuffling data sets to yield a re-arranged data set. Interleaved codeword146is stored to central memory circuit150. Interleaved codeword146is comprised of a number of encoded sub-codewords designed to reduce the complexity of a downstream data decoder circuit while maintaining reasonable processing ability.

Once a data decoding circuit170is available, a previously stored interleaved codeword146is accessed from central memory circuit150as a stored codeword186and globally interleaved by a global interleaver/de-interleaver circuit184. Global interleaver/De-interleaver circuit184may be any circuit known in the art that is capable of globally rearranging codewords. Global interleaver/De-interleaver circuit184provides a decoder input152as an input to low data decoding circuit170.

Data decoding circuit170includes low complexity decoder circuit166, multi-pass partial maximum likelihood decode value modification circuit168, and a multi-pass controller circuit175. Low complexity decoder circuit166receives decoder input152and applies a decoder algorithm thereto to yield a decoder output167. In addition, checksum indices169(i.e., an identification of a particular parity check equation) of any unsatisfied parity checks are generated. Decoder output167and checksum indices169are provided to multi-pass controller circuit175. In addition, decoder output167is fed back to low complexity decoder circuit166where it can be used to guide subsequent application of the decoder algorithm to decoder input152.

Multi-pass controller circuit175utilizes decoder output167and checksum indices169to determine if a potential trapping set condition has occurred. Where a potential trapping set condition has occurred, a log likelihood ratio (LLR) subset output177(a portion of decoder output167) and corresponding index outputs176(i.e., a portion of checksum indices169corresponding to LLR subset output177) are provided by multi-pass controller circuit175to multi-pass partial maximum likelihood decode value modification circuit168. Multi-pass partial maximum likelihood decode value modification circuit168determines which symbols are associated with an unsatisfied check. Each unsatisfied check is indicated by index outputs176. A total syndrome (s) is calculated for each of the unsatisfied checks in accordance with the following equation:

s=∑i=0M⁢vi×ei,
where vicorresponds to hard decision values of the variable nodes feeding a check node associated with the unsatisfied check, M is the number of variable nodes corresponding to the check node, and eicorresponds to the edge values connecting the variable nodes to the check node.FIG. 1bshows a portion of a decoder algorithm graph131showing M variable nodes (vi)132connected to a check node133where the checksum is unsatisfied via a M edges134that each have an edge value.

Multi-pass partial maximum likelihood decode value modification circuit168calculates an array of possible hard decision values across the contributors to the unsatisfied check in accordance with the following equation:
HDi,j′=(j×ei−1)−HDi, foriε{1,2, . . .M},jε{1,2,3},
where j represents the contribution from the previously calculated total syndrome, HDirepresents the most likely hard decision for the particular instance i, and ei−1corresponds to the inverse edge value for the particular instance i. In this case, j is a value of 1 to 3 as the decoder is a non-binary decoder using two bit symbols with three non-zero LLR values for each symbol. Where a binary decoder is being used, jε{1}. Where three bit symbols are used, jε{1, 2, 3,4, 5, 6, 7}. Thus, while the rest of this embodiment is discussed in relation to a two-bit symbol situation, one of ordinary skill in the art will recognize a variety of other binary and non-binary decoders to which the inventions may be applied.

Using the aforementioned array, multi-pass partial maximum likelihood decode value modification circuit168determines the most likely candidate from the array for modification. The most likely candidate is selected as the instance i in each row of the array (i.e., jε{1, 2, 3}) that has the lowest LLR value. This determination may be done in accordance with the following equation:
ij*=arg mini(LLRHDiXOR HD′i,j), forjε{1,2,3}.
This determination results in three index values i1, i2, i3where jε{1, 2, 3}. Again, where a different number of bits per symbol are being used, the number of index values will be correspondingly different.

The LLR values associated with the index value ij* are used by multi-pass partial maximum likelihood decode value modification circuit168to determine whether one or two LLR values are to be modified. In particular, multi-pass partial maximum likelihood decode value modification circuit168determines whether modifying one LLR value associated with the symbol indicated by index value ij* results in a greater change than modifying two LLR values associated with the symbol indicated by index value ij*. The determination may be made based upon the following comparison:

LLRHDi⁢XOR⁢⁢HDi,s′≥∑j=03⁢LLRHDi⁢XORHDi,j′-LLRHDi⁢XORHDi,s′
Where the comparison indicates that modifying a single LLR value yields a greater change than modifying two LLR values of the symbol indicated by index value ij*, the following symbol modification is performed:
HDi*s=HDi*j.
Otherwise, where the comparison indicates that modifying a single LLR value does not yield a greater change than modifying two LLR values of the symbol indicated by index value ij*, the following symbol modifications are:
HDi*j=HDi*j,j, forj≠s.
The modified symbol (with one or two values modified) are provided as a replacement symbol output179to low complexity decoder circuit166that inserts the modified symbol into decoder output167prior to a subsequent application of the data decoder algorithm to decoder input152.

In one particular embodiment of the present invention, a potential trapping set condition is considered to have occurred where the number of remaining unsatisfied checks after application of the decoder algorithm to decoder input152is less than ten, and the indexes corresponding to the remaining unsatisfied checks have not changed for at least two local iterations (i.e., passes through low complexity decoder circuit166). In addition, in some cases, multi-pass controller circuit175is not enabled to indicate a potential trapping set condition until at least four local iterations of decoder algorithm to decoder input152have completed. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other indicia that may be used to define the occurrence of a potential trapping set condition and/or to trigger operation of multi-pass partial maximum likelihood decode value modification circuit168.

In addition, multi-pass controller circuit175determines whether the data decoding algorithm converged. Where the data decoding algorithm failed to converge and no more local iterations (iterations through low complexity decoder circuit166), multi-pass controller circuit175provides a decoder output154(i.e., decoder output167) back to central memory circuit150via global interleaver/de-interleaver circuit184. Prior to storage of decoded output154to central memory circuit150, decoded output154is globally de-interleaved to yield a globally de-interleaved output188that is stored to central memory circuit150. The global de-interleaving reverses the global interleaving earlier applied to stored codeword186to yield decoder input152. Once data detector circuit130is available, a previously stored de-interleaved output188is accessed from central memory circuit150and locally de-interleaved by a de-interleaver circuit144. De-interleaver circuit144re-arranges decoder output148to reverse the shuffling originally performed by interleaver circuit142. A resulting de-interleaved output197is provided to data detector circuit130where it is used to guide subsequent detection of a corresponding data set receive as equalized output125.

Alternatively, where the data decoding algorithm converged, multi-pass controller circuit175provides an output codeword172to a de-interleaver circuit180. De-interleaver circuit180rearranges the data to reverse both the global and local interleaving applied to the data to yield a de-interleaved output182. De-interleaved output182is provided to a hard decision output circuit190. Hard decision output circuit190is operable to re-order data sets that may complete out of order back into their original order. The originally ordered data sets are then provided as a hard decision output192.

As another alternative, where multi-pass controller circuit175determines that a potential trapping set has been found and additional local iterations (iterations through low complexity decoder circuit166) are allowed, multi-pass controller circuit175causes a series of actions. First, multi-pass controller circuit175provides log likelihood ratio (LLR) subset output177(a portion of decoder output167) and corresponding index outputs176that are used by multi-pass partial maximum likelihood decode value modification circuit168to determine the modified symbol (with one or two values modified) and provide it as a replacement symbol output179to low complexity decoder circuit166that inserts the modified symbol into decoder output167prior to a subsequent application of the data decoder algorithm to decoder input152. Second, the replacement symbol output179is saved as a saved replacement symbol output181. Third, low complexity decoder circuit166applies the decode algorithm to the modified symbol set formed by incorporating replacement symbol output179into decoder output167to yield an updated decoder output167. Fourth, multi-pass controller circuit175provides log likelihood ratio (LLR) subset output177(a portion of decoder output167) and corresponding index outputs176that are used by multi-pass partial maximum likelihood decode value modification circuit168to determine the modified symbol (with one or two values modified) and provide it as a replacement symbol output179to low complexity decoder circuit166. Fifth, low complexity decoder circuit166applies the decode algorithm to the modified symbol set formed by incorporating both the replacement symbol output179and saved replacement symbol output181into decoder output167to yield an updated decoder output167.

An example of operation of data decoding circuit170is provided in the following pseudo-code:

perform data decode of decoder input 152 by belief propagation decoder circuit 166;If (number of unsatisfied checks == 0){provide decoder output 167 as output codeword 172}Else if (number of unsatisfied checks > 0 && number of local iterations == maximum){provide decoder output 167 as decoded output 154}Else if (number of unsatisfied checks > 0 &&[number of unsatisfied checks >= M ORnumber of local iterations is < N ORindexes 169 change from one local iteration to the next]){provide decoder output 167 as an input to low complexity decoder circuit 166}Else if (number of unsatisfied checks > 0 &&[number of unsatisfied checks < M ANDnumber of local iterations is >= N ORindexes 169 do not change from one local iteration to the next]){provide LLR subset output 177 and index output 176 to partial maximum likelihooddecoder circuit 168 to generate replacement symbol output 179;modify decoder output 167 to incorporate replacement symbol output 179;store replacement symbol output 179 as saved replacement symbol output 181;perform decoding by low complexity decoder circuit 166 on the modified decoder outputto yield an updated decoder output 167;provide LLR subset output 177 and index output 176 to partial maximum likelihooddecoder circuit 168 to generate replacement symbol output 179;modify decoder output 167 to incorporate replacement symbol output 179 and savedreplacement symbol output 181;perform decoding by low complexity decoder circuit 166 on the modified decoder outputto yield an updated decoder output 167;}

Turning toFIG. 1c, a controller circuit101that may be used as part of multi-pass controller circuit175ofFIG. 1in accordance with various embodiments of the present invention. Controller circuit101includes an LLR subset register102that stores each element of decoder output167that corresponds to a non-zero value of a checksum identified as one of checksum indices169. An LLR subset register output103is provided by LLR subset register102. In addition, controller circuit101includes an unsatisfied check index register106that stores each index for which one or more instances of decoder output167stored to LLR subset register102. Controller circuit101also includes a codeword completion circuit113that counts decoder outputs167to determine whether all instances of a codeword have been received. Where a completed codeword is received, a codeword complete output117is asserted high.

An unsatisfied check counter circuit127counts the number of non-zero parity check equation results (i.e., unsatisfied checks) indicated by checksum indices to yield an unsatisfied check count value128. Unsatisfied check counter circuit127is reset whenever codeword complete output117is asserted such that a completed codeword is indicated. Hence, unsatisfied check count value128indicates the number of unsatisfied checks that occur for a given codeword. A count output equals zero circuit131indicates whether unsatisfied check count value128is equal to zero. Where unsatisfied check count value128is determined to be equal to zero, count output equals zero circuit131asserts a zero count output133. Where zero count output133is asserted indicating that unsatisfied check count value128is zero, an output codeword generator circuit134provides decoder output167as output codeword172.

In addition, a count output less than M circuit129determines whether unsatisfied check count value128is greater than zero and less than a value M. In some cases, M is ten. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other values of M that may be used in relation to different embodiments of the present invention. Where count output less than M circuit129determines that the value of unsatisfied check count value128is greater than zero and less than M, count output less than M circuit129asserts an M count output132.

A local iteration counter circuit118receives codeword complete output117and counts the number of local iterations that have been applied to the particular codeword (received as decoder output167). The number of local iterations is provided as a local iteration count value119. A count output greater than N circuit receives local iteration count value119and asserts a count value greater than N output126whenever local iteration count value119is greater than N. In some cases, N is three. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other values of N that may be used in relation to different embodiments of the present invention. A count output equals maximum local iterations circuit121receives local iteration count value119and asserts a count value equals maximum local iterations output122whenever local iteration count value119equals the defined maximum number of local iterations. is greater than N. In some cases, N is three. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other values of N that may be used in relation to different embodiments of the present invention. Where M count output132indicates that the number of unsatisfied checks is not zero and count value equals maximum local iterations output122indicates the maximum number of local iterations have been performed, a decoded output generator circuit123provides a derivative of decoder output167as decoded output154.

An index buffer108receives index values107from unsatisfied check index register106and stores them upon completion of a codeword (e.g., codeword complete output117is asserted). Index values109from index buffer108are compared with index values107by a same indexes circuit111to determine whether there has been a change over the last two local iterations to determine if the same parity check equations remain unsatisfied. Where the same parity check equations remain unsatisfied, same indexes circuit111asserts an unchanged output112. In addition, index values107are provided as an index output176. LLR subset output generator circuit104provides LLR subset register output103as LLR subset output177whenever same indexes output112is asserted, count value greater than N output126is asserted, and M count output132are all asserted.

Turning toFIG. 1d, a simplified maximum likelihood decode value modification circuit800is shown that may be used in relation to the decoder system ofFIG. 1in accordance with various embodiments of the present invention. Simplified maximum likelihood decode value modification circuit800includes a syndrome calculation circuit810that receives log likelihood ratio output177and index output176, and based thereon determines which symbols are associated with a given unsatisfied check, and calculates a total syndrome for each of the unsatisfied checks in accordance with the following equation:

s=∑i=0M⁢vi×ei,
where vicorresponds to hard decision values of the variable nodes feeding a check node associated with the unsatisfied check, M is the number of variable nodes corresponding to the check node, and eicorresponds to the edge values connecting the variable nodes to the check node. Referring toFIG. 1b, a portion of a decoder algorithm graph131showing M variable nodes (vi)132connected to a check node133where the checksum is unsatisfied via a M edges134that each have an edge value. Syndrome calculation circuit810provides a syndrome output812.

In addition, simplified maximum likelihood decode value modification circuit800includes an unsatisfied check array calculator circuit820that receives log likelihood ratio output177and index output176, and based thereon determines which symbols are associated with a given unsatisfied check and calculates an calculates an array of possible hard decision values across the contributors to the unsatisfied check in accordance with the following equation:
HDi,j′=(j×ei−1)−HDi, foriε{1,2, . . .M},jε{1,2,3},
where j represents the contribution from the previously calculated total syndrome, HDirepresents the most likely hard decision for the particular instance i, and ei−1corresponds to the inverse edge value for the particular instance i. In this case, j is a value of 1 to 3 as the decoder is a non-binary decoder using two bit symbols with three non-zero LLR values for each symbol. Where a binary decoder is being used, jε{1}. Where three bit symbols are used, jε{1, 2, 3,4, 5, 6, 7}. Thus, while the rest of this embodiment is discussed in relation to a two-bit symbol situation, one of ordinary skill in the art will recognize a variety of other binary and non-binary decoders to which the inventions may be applied. Unsatisfied check array calculator circuit820provides the calculated array as a vector output822to an index identifier circuit832.

Index identifier circuit830uses vector output822representing the array of possible hard decision values to determine the most likely candidate from the array for modification. The most likely candidate is selected as the instance i in each row of the array (i.e., jε{1, 2, 3}) that has the lowest LLR value. This determination may be done in accordance with the following equation:
ij*=arg mini(LLRHDiXOR HD′i,j), forjε{1,2,3}.
This determination results in three index values i1, i2, i3where jε{1, 2, 3}. Again, where a different number of bits per symbol are being used, the number of index values will be correspondingly different. This identified set of index values is provided as an index output832to a likely symbol value selector and modification circuit830.

Likely symbol value selector and modification circuit830uses the LLR values indicated by index output to determine whether one or two LLR values are to be modified. In particular, likely symbol value selector and modification circuit830determines whether modifying one LLR value associated with the symbol indicated by index value ij* results in a greater change than modifying two LLR values associated with the symbol indicated by index value ij*. The determination may be made based upon the following comparison:

LLRHDi⁢XORHDi,s′≥∑j=13⁢LLRHDi⁢XORHDi,j′-LLRHDi⁢XORHDi,s′
Where the comparison indicates that modifying a single LLR value yields a greater change than modifying two LLR values of the symbol indicated by index value ij*, the following symbol modification is performed:
HDi*s=HDi*j.
Otherwise, where the comparison indicates that modifying a single LLR value does not yield a greater change than modifying two LLR values of the symbol indicated by index value ij*, the following symbol modifications are:
HDi*j=HDi*j,j, forj≠s.
The modified symbol (with one or two values modified) are provided as a replacement symbol output179. In addition, replacement symbol output179is stored to a replacement symbol storage circuit850. Replacement symbol storage circuit850provides the stored data as a saved replacement symbol output181.

Turning toFIG. 2a, a flow diagram200shows a method for multi-pass alternate decoding in accordance with various embodiments of the present invention. Following flow diagram200, an analog input is received (block205). The analog input may be derived from, for example, a storage medium or a data transmission channel. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of sources of the analog input. The analog input is converted to a series of digital samples (block210). This conversion may be done using an analog to digital converter circuit or system as are known in the art. Of note, any circuit known in the art that is capable of converting an analog signal into a series of digital values representing the received analog signal may be used. The resulting digital samples are equalized to yield an equalized output (block215). In some embodiments of the present invention, the equalization is done using a digital finite impulse response circuit as are known in the art. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of equalizer circuits that may be used in place of such a digital finite impulse response circuit to perform equalization in accordance with different embodiments of the present invention.

It is determined whether a data detector circuit is available (block220). Where a data detector circuit is available (block220), a data detection algorithm is applied to the equalized output guided by a data set derived from a decoded output where available (e.g., the second and later iterations through the data detector circuit and the data decoder circuit) from a central memory circuit to yield a detected output (block225). In some embodiments of the present invention, data detection algorithm is a Viterbi algorithm as are known in the art. In other embodiments of the present invention, the data detection algorithm is a maximum a posteriori data detection algorithm as are known in the art. The data set derived from the decoded output may be a de-interleaved version of the decoded data set. A signal derived from the detected output (e.g., a locally interleaved version of the detected output) is stored to the central memory to await processing by a data decoder circuit (block230).

In parallel to the previously discussed data detection processing, it is determined whether a data decoder circuit is available (block240). Where the data decoder circuit is available (block240), a previously stored derivative of a detected output is accessed from the central memory (block245). A low complexity data decode algorithm is applied to the derivative of the detected output to yield a decoded output (block250). In some embodiments of the present invention, the low complexity data decode algorithm is a belief propagation data decode algorithm as are known in the art. Such a belief propagation data decode algorithm may be implemented similar to that discussed in Pearl, Judea, “REVEREND BAYES ON INFERENCE ENGINES: A DISTRIBUTED HIERARCHAL APPROACH”, AAAI-82 Proceedings, 1982. It should be noted that other embodiments of the present may use different decode algorithms.

It is determined whether the decoded output converged (i.e., the original data set is recovered) (block255). In some cases, such convergence is found where all of the checksum equations utilized as part of the low complexity decode algorithm are correct (i.e., there are no unsatisfied checks). Where the decode algorithm converged (block255), the decoded output is provided as a hard decision output (block260). Otherwise, where the decode algorithm failed to converge (block255), it is determined whether the number of local iterations of the data decode algorithm on the current data set exceeded a threshold value N (block265). In some cases, N is four. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other values of N that may be used in relation to different embodiments of the present invention. Where the number of local iterations has not exceeded the threshold value N (block265), the processes of blocks250-265are repeated for the same data set using the previous decoded output as a guide.

Otherwise, where the number of local iterations has exceeded the threshold value N (block265), it is determined whether another local iteration is to be performed (block270). In some cases, this is determined by comparing the number of local iterations that have been completed to a defined threshold number. Where another local iteration is not called for (e.g., the number of local iterations equals a maximum number of local iterations) (block270), the decoded output is stored to the central memory circuit where it awaits processing by the data detector circuit (i.e., another global iteration) (block275). Otherwise, where it is determined that another local iteration is called for (e.g., the number of local iterations is not equal to a maximum number of local iterations) (block270), it is determined whether the number of remaining unsatisfied checks is less than a threshold value M (block280). In some cases, M is ten. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize other values of M that may be used in relation to different embodiments of the present invention. Where the number of unsatisfied checks is not less than the threshold value M (block280), the processes of blocks250-280are repeated for the same data set using the previous decoded output as a guide.

Otherwise, where the number of unsatisfied checks is less than the threshold value M (block280), a multi-pass alternating decoding with symbol modification is performed (block201). Multi-pass alternating decoding with symbol modification includes performing a partial maximum likelihood decode process on a subset of the decoded output (i.e., portions of the decoded output corresponding to unsatisfied checks). The partial maximum likelihood decode process identifies one or more likely symbol errors. These likely symbol errors are saved as saved symbol errors for use in a subsequent pass. The decoded output is modified to change the values of the likely symbol errors, and the belief propagation algorithm is re-applied to the derivative of the detected output guided by the modified decoded output to yield an updated decoded output. The partial maximum likelihood decode process is applied to a subset of the updated decoded output (i.e., portions of the decoded output corresponding to unsatisfied checks). Again, the partial maximum likelihood decode process identifies one or more likely symbol errors. These likely symbol errors and the previously saved likely symbol errors are used to guide bit modification in the updated decoded output. Subsequently, the belief propagation algorithm is re-applied to the derivative of the detected output guided by the newly formed modified decoded output to yield an updated decoded output. The updated decoded output is then used to guide re-application of the low density parity check decoding algorithm to the derivative of the detected output (block250), and the processes of blocks255-292are repeated.

Turning toFIG. 2b, a flow diagram271shows an implementation of the multi-pass alternate decoding with symbol modification ofFIG. 2ain accordance with some embodiments of the present invention. Following flow diagram271, an alternate decode algorithm is applied to a portion of the decoded output corresponding to unsatisfied checks to yield a data subset (block211). A symbol modification is then performed (block251) based upon the data subset. The symbol modification (block251) includes identifying the most likely symbol corresponding to each unsatisfied check for modification (block253). The identified symbol is stored as a first modification (block257). The first modification is then applied to the decoder output to yield a modified decode output (block259). Application of the first modification to yield the modified decode output includes modifying the bits of the overall decode output in accordance with the first modification. Thus, the modified decode output is the original decode output (from block250) having one or more symbols modified in accordance with the first modification.

Next, apply the belief propagation data decode algorithm to the derivative of the detected output guided by the modified decode output to yield a decoded output (block217). This is the same process as block250. It is determined whether the decoded output converged (i.e., the original data set is recovered) (block219). Where the decoded output converged (block219), the decoded output is provided to block260ofFIG. 2a. Alternatively, where the decoded output failed to converge (block219), the alternate decode algorithm is applied to a portion of the decoded output from block217corresponding to unsatisfied checks to yield a data subset (block221). A symbol modification is then performed (block261) based upon the data subset. The symbol modification (block261) includes identifying the most likely symbol corresponding to each unsatisfied check for modification which is a second modification (block263). A combination of the first modification and the second modification is then applied to the decoder output to yield a modified decode output (block269). Application of the combination of the first modification and the second modification to yield the modified decode output includes modifying the bits of the overall decode output in accordance with the combination of the first modification and the second modification. Thus, the modified decode output is the original decode output (from block217) having one or more symbols modified in accordance with the combination of the first modification and the second modification. The modified decode output is then provided to block250ofFIG. 2a.

Turning toFIG. 2c, a flow diagram299shows a method for performing the function of block251ofFIG. 2bin relation to symbol modification in accordance with some embodiments of the present invention. In this example, each symbol is two bits representing four potential symbol values (i.e., ‘00’, ‘01’, ‘10’, ‘11). Following flow diagram299, a first unsatisfied check is selected (block272). In some cases, such an unsatisfied check is a parity check equation that did not yield a zero output after application of the data decode algorithm. Each unsatisfied check has a number of symbol values from which the unsatisfied check is calculated. A syndrome for all of the values associated with the selected unsatisfied check is calculated (block274). In some cases, the syndrome is calculated in accordance with the following equation:

s=∑i=0M⁢vi×ei,
where vicorresponds to hard decision values of the variable nodes feeding a check node associated with the unsatisfied check, M is the number of variable nodes corresponding to the check node, and eicorresponds to the edge values connecting the variable nodes to the check node. Referring toFIG. 1b, a portion of a decoder algorithm graph131showing M variable nodes (vi)132connected to a check node133where the checksum is unsatisfied via a M edges134that each have an edge value.

An array of possible hard decision values are calculated (block276) across the contributors to the unsatisfied check in accordance with the following equation:
HDi,j′=(j×ei−1)−HDi, foriε{1,2, . . .M},jε{1,2,3},
where j represents the contribution from the previously calculated total syndrome, HDirepresents the most likely hard decision for the particular instance i, and ei−1corresponds to the inverse edge value for the particular instance i. In this case, j is a value of 1 to 3 as the decoder is a non-binary decoder using two bit symbols with three non-zero LLR values for each symbol. Where a binary decoder is being used, jε{1}. Where three bit symbols are used, jε{1, 2, 3, 4, 5, 6, 7}. Thus, while the rest of this embodiment is discussed in relation to a two-bit symbol situation, one of ordinary skill in the art will recognize a variety of other binary and non-binary decoders to which the inventions may be applied.

An index identifying the most likely candidate from the aforementioned array is selected (block278). The most likely candidate is selected as the instance i in each row of the array (i.e., jε{1, 2, 3}) that has the lowest LLR value. The index may be calculated in accordance with the following equation:
ij*=arg mini(LLRHDiXOR HD′i,j), forjε{1,2,3}.
This determination results in three index values i1, i2, i3where jε{1, 2, 3}. Again, where a different number of bits per symbol are being used, the number of index values will be correspondingly different.

It is then determined whether one or two LLR values of the symbol identified by the aforementioned index are to be modified (block282). In particular, it is determined whether modifying one LLR value associated with the symbol indicated by index value ij* results in a greater change than modifying two LLR values associated with the symbol indicated by index value ij*. The determination may be made based upon the following comparison:

Where the comparison indicates that modifying a single LLR value yields a greater change than modifying two LLR values of the symbol indicated by index value ij* (block282), the determined flip value (i.e., a new value for one LLR value of the identified most likely candidate) is stored as a first modification (block273), and the LLR value of the symbol identified by the index is modified (block284). The modification may be made in accordance with the following equation:
HDi*s=HDi*j.
Otherwise, where the comparison indicates that modifying a single LLR value does not yield a greater change than modifying two LLR values of the symbol indicated by index value ij* (block282), the determined flip values (i.e., new values for two LLR values of the identified most likely candidate) is stored as the first modification (block277), then the two LLR values of the symbol identified by the index are modified (block286). The modification may be made in accordance with the following equation:
HDi*j=HDi*j,j, forj≠s.

It is then determined whether another unsatisfied check remains (block288). Where another unsatisfied check remains (block288), the next unsatisfied check is selected (block294), and the processes of blocks272-288are repeated to further modify the decoded output. Alternatively, where no additional unsatisfied checks remain (block288), the process is returned to that discussed in relation toFIG. 2bwhere the modified decoded output is used to guide re-application of the belief propagation decoding algorithm to the derivative of the detected output (block217).

Turning toFIG. 2d, a flow diagram999shows a method for performing the function of block261ofFIG. 2bin relation to symbol modification in accordance with various embodiments of the present invention. In this example, each symbol is two bits representing four potential symbol values (i.e., ‘00’, ‘01’, ‘10’, ‘11). Following flow diagram299, a first unsatisfied check is selected (block972). In some cases, such an unsatisfied check is a parity check equation that did not yield a zero output after application of the data decode algorithm. Each unsatisfied check has a number of symbol values from which the unsatisfied check is calculated. A syndrome for all of the values associated with the selected unsatisfied check is calculated (block974). In some cases, the syndrome is calculated in accordance with the following equation:

s=∑i=0M⁢vi×ei,
where vicorresponds to hard decision values of the variable nodes feeding a check node associated with the unsatisfied check, M is the number of variable nodes corresponding to the check node, and eicorresponds to the edge values connecting the variable nodes to the check node. Referring toFIG. 1b, a portion of a decoder algorithm graph131showing M variable nodes (vi)132connected to a check node133where the checksum is unsatisfied via a M edges134that each have an edge value.

An array of possible hard decision values are calculated (block976) across the contributors to the unsatisfied check in accordance with the following equation:
HDi,j′=(j×ei−1)−HDi, foriε{1,2, . . .M},jε{1,2,3},
where j represents the contribution from the previously calculated total syndrome, HDirepresents the most likely hard decision for the particular instance i, and ei−1corresponds to the inverse edge value for the particular instance i. In this case, j is a value of 1 to 3 as the decoder is a non-binary decoder using two bit symbols with three non-zero LLR values for each symbol. Where a binary decoder is being used, jε{1}. Where three bit symbols are used, jε{1, 2, 3,4, 5, 6, 7}. Thus, while the rest of this embodiment is discussed in relation to a two-bit symbol situation, one of ordinary skill in the art will recognize a variety of other binary and non-binary decoders to which the inventions may be applied.

An index identifying the most likely candidate from the aforementioned array is selected (block978). The most likely candidate is selected as the instance i in each row of the array (i.e., jε{1, 2, 3}) that has the lowest LLR value. The index may be calculated in accordance with the following equation:
ij*=arg mini(LLRHDiXOR HD′i,j), forjε{1,2,3}.
This determination results in three index values i1, i2, i3where jε{1, 2, 3}. Again, where a different number of bits per symbol are being used, the number of index values will be correspondingly different.

It is then determined whether one or two LLR values of the symbol identified by the aforementioned index are to be modified (block982). In particular, it is determined whether modifying one LLR value associated with the symbol indicated by index value ij* results in a greater change than modifying two LLR values associated with the symbol indicated by index value ij*. The determination may be made based upon the following comparison:

Where the comparison indicates that modifying a single LLR value yields a greater change than modifying two LLR values of the symbol indicated by index value ij* (block982), one LLR value of the symbol identified by the index is modified (block984). The modification may be made in accordance with the following equation:
HDi*s=HDi*j.
Otherwise, where the comparison indicates that modifying a single LLR value does not yield a greater change than modifying two LLR values of the symbol indicated by index value ij* (block982), two LLR values of the symbol identified by the index are modified (block986). The modification may be made in accordance with the following equation:
HDi*j=HDi*j,j, forj≠s.

It is then determined whether another unsatisfied check remains (block988). Where another unsatisfied check remains (block988), the next unsatisfied check is selected (block994), and the processes of blocks972-988are repeated to further modify the decoded output. Alternatively, where no additional unsatisfied checks remain (block988), the process is returned to that discussed in relation toFIG. 2awhere the modified decoded output is used to guide re-application of the low density parity check decoding algorithm to the derivative of the detected output (block250).

Turning toFIG. 3, a storage device300is shown including simplified maximum likelihood value modification circuitry in accordance with one or more embodiments of the present invention. Storage device300may be, for example, a hard disk drive. Storage device300also includes a preamplifier370, an interface controller320, a hard disk controller366, a motor controller368, a spindle motor372, a disk platter378, and a read/write head assembly376. Interface controller320controls addressing and timing of data to/from disk platter378. The data on disk platter378consists of groups of magnetic signals that may be detected by read/write head assembly376when the assembly is properly positioned over disk platter378. In one embodiment, disk platter378includes magnetic signals recorded in accordance with either a longitudinal or a perpendicular recording scheme.

In a typical read operation, read/write head assembly376is accurately positioned by motor controller368over a desired data track on disk platter378. Motor controller368both positions read/write head assembly376in relation to disk platter378and drives spindle motor372by moving read/write head assembly to the proper data track on disk platter378under the direction of hard disk controller366. Spindle motor372spins disk platter378at a determined spin rate (RPMs). Once read/write head assembly378is positioned adjacent the proper data track, magnetic signals representing data on disk platter378are sensed by read/write head assembly376as disk platter378is rotated by spindle motor372. The sensed magnetic signals are provided as a continuous, minute analog signal representative of the magnetic data on disk platter378. This minute analog signal is transferred from read/write head assembly376to read channel circuit310via preamplifier370. Preamplifier370is operable to amplify the minute analog signals accessed from disk platter378. In turn, read channel circuit310decodes and digitizes the received analog signal to recreate the information originally written to disk platter378. This data is provided as read data303to a receiving circuit. A write operation is substantially the opposite of the preceding read operation with write data301being provided to read channel circuit310. This data is then encoded and written to disk platter378.

During operation, data decoding applied to the information received from disk platter378may not converge. Where it is determined that there is a potential trapping set or other impediment to convergence, a partial maximum likelihood value modification circuit identifies a symbol associated with an unsatisfied check that exhibits the most significant ambiguity. This symbol is then modified and used to replace a corresponding symbol in a previously generated decoded output prior to a subsequent application of a data decode algorithm to a decoder input. The process of modification is then repeated a second time after which all symbols identified in both passes are modified prior to subsequent application of a data decode algorithm. Such symbol modification circuitry may be implemented similar to that discussed above in relation toFIGS. 1a-1d, and/or may be done using a process similar to that discussed above in relation toFIGS. 2a-2d.

It should be noted that storage system may utilize SATA, SAS or other storage technologies known in the art. Also, it should be noted that storage system300may be integrated into a larger storage system such as, for example, a RAID (redundant array of inexpensive disks or redundant array of independent disks) based storage system. Such a RAID storage system increases stability and reliability through redundancy, combining multiple disks as a logical unit. Data may be spread across a number of disks included in the RAID storage system according to a variety of algorithms and accessed by an operating system as if it were a single disk. For example, data may be mirrored to multiple disks in the RAID storage system, or may be sliced and distributed across multiple disks in a number of techniques. If a small number of disks in the RAID storage system fail or become unavailable, error correction techniques may be used to recreate the missing data based on the remaining portions of the data from the other disks in the RAID storage system. The disks in the RAID storage system may be, but are not limited to, individual storage systems such as storage system300, and may be located in close proximity to each other or distributed more widely for increased security. In a write operation, write data is provided to a controller, which stores the write data across the disks, for example by mirroring or by striping the write data. In a read operation, the controller retrieves the data from the disks. The controller then yields the resulting read data as if the RAID storage system were a single disk. It should also be noted that various functions or blocks of storage system300may be implemented in either software or firmware, while other functions or blocks are implemented in hardware.

Turning toFIG. 4, a data transmission system400including simplified maximum likelihood value modification circuitry in accordance with various embodiments of the present invention. Data transmission system400includes a transmitter410that is operable to transmit encoded information via a transfer medium430as is known in the art. The encoded data is received from transfer medium430by receiver420. Transceiver420incorporates data decoder circuitry. While processing received data, received data is converted from an analog signal to a series of corresponding digital samples, and the digital samples are equalized to yield an equalized output. The equalized output is then provided to a data processing circuit including both a data detector circuit and a data decoder circuit. Data is passed between the data decoder and data detector circuit via a central memory allowing for variation between the number of processing iterations that are applied to different data sets. It should be noted that transfer medium430may be any transfer medium known in the art including, but not limited to, a wireless medium, an optical medium, or a wired medium. Based upon the disclosure provided herein, one of ordinary skill in the art will recognize a variety of transfer mediums that may be used in relation to different embodiments of the present invention.

During operation, data decoding applied to the information received via transfer medium430may not converge. Where it is determined that there is a potential trapping set or other impediment to convergence, a partial maximum likelihood value modification circuit identifies a symbol associated with an unsatisfied check that exhibits the most significant ambiguity. This symbol is then modified and used to replace a corresponding symbol in a previously generated decoded output prior to a subsequent application of a data decode algorithm to a decoder input. The process of modification is then repeated a second time after which all symbols identified in both passes are modified prior to subsequent application of a data decode algorithm. Such symbol modification circuitry may be implemented similar to that discussed above in relation toFIGS. 1a-1d, and/or may be done using a process similar to that discussed above in relation toFIGS. 2a-2d.