Semiconductor device manufacturing method

A semiconductor manufacturing method includes exposing on a photoresist film a first partial pattern of a contact hole, overlapping a part of a gate interconnection in alignment with an alignment mark formed simultaneously with forming the gate interconnection, exposing on the photoresist film a second partial pattern, overlapping a part of an active region in alignment with an alignment mark formed simultaneously with forming the active region, developing the photoresist film to form an opening at the portion where the first partial pattern and the second partial pattern have been exposed, and etching an insulation film to form a contact hole down to the gate interconnection and the source/drain diffused layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2011-42675, filed on Feb. 28, 2011, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to a semiconductor device manufacturing method.

BACKGROUND

Static Random Access Memory (SRAM) is a semiconductor device having the memory cells formed of flip-flop circuits and is operative at high speed.

In semiconductor devices, such as SRAM, etc., gate interconnections, conductor plugs, etc. are laid out in the memory cell parts in very high densities. The gate interconnections, the conductor plugs, etc. are laid out in very high density, whereby the size of the memory cells can be reduced, and the memory capacity can be increased.

Recently, to realize lower costs and larger capacities, the memory cells are required to be more micronized and integrated.

It is required to manufacture SRAM of high reliability at higher yields.

Related reference is as follows:

SUMMARY

According to one aspect of an embodiment, a semiconductor device manufacturing method comprising: forming a device isolation region for defining a plurality of active regions in a semiconductor substrate and forming a first alignment mark in the semiconductor substrate; forming a first gate interconnection which is formed, crossing over one of said plurality of active regions and which is linear and includes the gate electrode of a first transistor, and a second gate interconnection which is formed, crossing over the other of said plurality of active regions and which is linear and in parallel with the first gate interconnection over the semiconductor substrate with a gate insulation film formed therebetween, and forming a second alignment mark over the semiconductor substrate; forming source/drain diffused layers respectively in the active regions; forming an insulation film over the semiconductor substrate and over the first gate interconnection and the second gate interconnection; forming a photoresist film over the insulation film; making alignment by using the second alignment mark and exposing on the photoresist film a first partial pattern for forming a first contact hole in the insulation film, overlapping at least a part of the first gate interconnection; making alignment by using the first alignment mark and exposing on the photoresist film a second partial pattern for forming the first contact hole in the insulation film, overlapping at least a part of the source/drain diffused layer of the second transistor; developing the photoresist film to form a first opening in the photoresist film at the portion where the first partial pattern and the second partial pattern have been exposed; etching the insulation film with the photoresist film as the mask to form in the insulation film the first contact hole down to the first gate interconnection and the source/drain diffused layer of the second transistor; and burying the first contact layer in the first contact hole.

According to another aspect of the embodiment, a semiconductor device manufacturing method comprising: forming a device isolation region for defining a plurality of active regions in a semiconductor substrate and forming a first alignment mark in the semiconductor substrate; forming a first gate interconnection which is formed, crossing over one of said plurality of active regions and which is linear and includes the gate electrode of a first transistor, and a second gate interconnection which is formed, crossing over the other of said plurality of active regions and which is linear and in parallel with the first gate interconnection over the semiconductor substrate with a gate insulation film formed therebetween, and forming a second alignment mark over the semiconductor substrate; forming source/drain diffused layers respectively in the active regions on both sides of the gate electrodes; forming the first insulation film over the semiconductor substrate, the first gate interconnection and the second gate interconnection; forming over the first insulation film the second insulation film which is different from the first insulation film in the etching characteristics; forming the first photoresist film over the second insulation film; making alignment by using the second alignment mark and exposing on the first photoresist film a first partial pattern for a first contact hole in the first insulation film, overlapping at least a part of the first gate interconnection; developing the first photoresist film to form a first opening in the first photoresist film at the portion where the first partial pattern has been exposed; etching the second insulation film by using as the mask the first photoresist film with the first opening formed in; forming a second photoresist film over the second insulation film; making alignment by using the first alignment mark to expose on the second photoresist film a second partial pattern for forming the first contact hole in the first insulation film, overlapping at least a part of the source/drain diffused layer of the second transistor; developing the second photoresist film to form a second opening in the second photoresist film at the portion where the second partial pattern has been exposed; etching the second insulation film by using as the mask the second photoresist film with the second opening formed in; etching the first insulation film with the second insulation film as the mask to form in the first insulation film the first contact hole down to the first gate interconnection and the source/drain diffused layer of the second transistor; and burying the first contact layer in the first contact hole.

DESCRIPTION OF EMBODIMENTS

The proposed semiconductor device manufacturing method has not been always able to provide sufficiently high reliability and yields.

The semiconductor device manufacturing method according to the reference example will be described with reference toFIGS. 49A to 52B.FIGS. 49A to 52Bare plan views of the semiconductor device in the steps of the semiconductor device manufacturing method, which illustrate the method.

As illustrated inFIGS. 49A and 49B, active regions111a-111ddefined by a device isolation region (not illustrated) is formed in a part of a semiconductor substrate (not illustrated) a memory cell158is to be formed. Simultaneously with forming the active regions111a-111d, alignment mark111eis also formed. The alignment mark111eis formed of the same film of the device isolation region defining the active regions111a-111e.

Next, gate interconnections116a-116dare formed, crossing the active regions111a-111d. When the patterns of the gate interconnections116a-116dare transferred, the mask (reticle) is aligned with the alignment mark111e. Simultaneously with forming the gate interconnections116a-116d, the alignment marks116e,116fare formed. The alignment marks116e,116fare formed of the same film as the gate interconnections116a-116d.

Then, in the active regions111a-111don both sides of the gate interconnections116a-116d, source/drain diffused layers120,122,124,126,128,130,132,134,136,138are formed.

Next, an inter-layer insulation film (not illustrated) is formed on the semiconductor substrate.

Then, contact holes146a-146lare transferred on the inter-layer insulation film. When the contact holes146a-146lare transferred, the mask is aligned with the alignment mark116f. Simultaneously with forming the contact holes146a-146l, an opening146mof the pattern of the alignment mark for the mask is formed.

Next, contact layers148a-148lare buried in the contact holes148a-148l. At this time, the alignment mark148mis buried in the opening146m(seeFIGS. 50A and 50B).

However, in aligning the mask, disalignments often take place.

FIGS. 51A and 51Billustrate a case that a large disalignment has taken place in the Y direction in transferring the patterns of the gate interconnections116a-116d.

FIGS. 52A and 52billustrate a case that a large disalignment has further taken place in the X direction in transferring the pattern of the contact holes246a.

When such disalignments take place, defective connections often take place between the contact layers148a,148band the gate interconnections116a,116bin the encircled parts inFIG. 52A. Between the contact layers148a,148band the source/drain diffused layers120,122, defective connections often take place.

The inventors of the present application have made earnest studies and got an idea that a semiconductor device of high reliability can be manufactured in the following way with high yields.

[a] First Embodiment

The semiconductor device according to a first embodiment and its manufacturing method will be described with reference toFIGS. 1A to 33B.

First, the semiconductor device according to the present embodiment will be described with reference toFIGS. 1A to 4.FIGS. 1A and 1Bare plan views of the semiconductor device according to the present embodiment (Part1).FIG. 1Aillustrates one of plural memory cells formed in the memory cell region.FIG. 1Billustrates the alignment marks provided in the peripheral part of a semiconductor chip.FIGS. 2A and 2Bare sectional views of the semiconductor device according to the present embodument. The leftmost view ofFIG. 2Ais the A-A′ line sectional view ofFIG. 1A. The second view ofFIG. 2Afrom the left is the B-B′ line sectional view ofFIG. 1A. The third view ofFIG. 2Afrom the left is the C-C′ line sectional view ofFIG. 1A. The fourth view ofFIG. 2Afrom the left is the D-D′ line sectional view ofFIG. 1A.FIG. 2Bis the E-E′ line sectional view ofFIG. 1B.FIG. 3is a plan view (Part2) of the semiconductor device according to the present embodiment.FIGS. 1A and 1Billustrate the configuration of the design pattern, andFIG. 3illustrates an example of the configuration of the pattern to be actually formed.FIG. 3corresponds toFIG. 1A, andFIG. 4is a circuit view of the semiconductor device according to the present embodiment.

In a semiconductor substrate10, a device isolation region12adefining the device regions11a-11dis formed. The device isolation region12ais buried in a trench13aformed in the semiconductor substrate10. The semiconductor substrate10is, e.g., a silicon substrate. As the device isolation region12a, silicon oxide film, for example, is used.

In the semiconductor substrate10, alignment marks11e,11fare formed. The alignment marks11e,11fare provided, e.g., in the peripheral part of the semiconductor substrate (semiconductor chip)10. The alignment marks11e,11fare defined by the same insulation film12bas the device isolation region12a. The insulation film12bdefining the alignment marks11e,11fis buried in the trench13bformed in the semiconductor substrate10.

The plane shape of the alignment marks11e,11fis, e.g., a rectangle.

The plane shape of the alignment marks11e,11fis not limited to rectangle. The plane shapes of the alignment marks11e,11fcan be, e.g., a frame shape or others.

On the semiconductor substrate10, gate interconnections16a-16dare formed with a gate insulation film14formed therebetween. On the semiconductor substrate10, alignment marks16e,16fare formed with the insulation film14formed therebetween. The alignment marks16e,16fare formed of the same film as the gate interconnections16a-16d. That is, the gate interconnections16a-16dand the alignment marks16e,16fare formed by patterning the same film.

The plane shape of the alignment mark16eis, e.g., a frame-shape.

The plane shape of the alignment mark16eis not limited to a frame-shape. The plane shape of the alignment mark16ecan be a rectangle or others.

The plane shape of the alignment mark16fis, e.g., a rectangle.

The plane shape of the alignment mark16fis not limited to a rectangle. The plane shape of the alignment mark16fcan be, e.g., a frame shape or others.

A sidewall insulation film18is formed on the respective side walls of the gate interconnections16a-16dand the alignment marks16e,16f.

The gate interconnection16ais formed, crossing the device regions11a,11c. The gate interconnection16aincludes the gate electrode of a load transistor L1, the gate electrode of a driver transistor D1and commonly connects the gate electrode of the load transistor L1and the gate electrode of the driver transistor D1. The gate interconnection16ais extended to the vicinity of the source/drain diffusion layers20of the load transistor L2formed in the device region11b.

In the device region11aon both sides of the gate interconnection16a, source/drain regions22,24are formed. The gate electrode16aand the source/drain diffused layers22,24form the load transistor L1.

In the device region11con both sides of the gate interconnection16a, source/drain diffused layers26, are formed. The gate electrode16aand the source/drain diffused layer26,28form the driver transistor D1.

The gate interconnection16bis formed, crossing the device regions11b,11d. The gate interconnection16bincludes the gate electrode of the load transistor L2and the gate electrode of the driver transistor D2and commonly connects the gate electrode of the load transistor L2and the gate electrode of the driver transistor D2. The gate interconnection16bis extended to the vicinity of the source/drain diffused layer22of the load transistor L1formed in the device region11a. The longitudinal direction of the gate interconnection16aand the longitudinal direction of the gate interconnection16bare the same. The gate interconnections16aand the gate interconnection16bare opposed to each other in a partial region.

In the device region11bon both sides of the gate interconnection16b, source/drain diffused layers20,30are formed. The gate electrode16band the source/drain diffused layer20,30form the load transistor L2.

In the device region11don both sides of the gate interconnection16b, source/drain diffused layers32,34are formed. The gate electrode16band the source/drain diffused layers32,34form the driver transistor D2.

The gate interconnection16cis formed, crossing the device region11c. The gate interconnection16cis positioned on the extended line of the gate interconnection16b. The gate interconnection16cincludes the gate electrode of a transfer transistor T1. Source/drain diffused layers26,36are formed in the device region11con both sides of the gate interconnection16c. The gate electrode16cand the source/drain diffused layers26,36form the transfer transistor T1. One of the source/drain diffused layers26of the transfer transistor T1and one of the source/drain diffused layers26of the driver transistor D1are formed of the common source/drain diffused layer26.

The gate interconnection16dis formed, crossing the device region11d. The gate interconnection16dis positioned on the extended line of the gate interconnection16a. The gate interconnection16dincludes the gate electrode of a transfer transistor T2. Source/drain diffused layers32,38are formed in the device region11don both sides of the gate electrode16d. The gate electrode16dand the source/drain diffused layers32,38form the transfer transistor T2. One of the source/drain diffused layers32of the transfer transistor T2and one of the source/drain diffused layers32of the driver transistor D2is formed of the common source/drain diffused layer32.

The width of the gate interconnections16a-16d, e.g., the gate length is, e.g., about 35-60 nm. The height of the gate interconnections16a-16dis, e.g., about 70-100 nm. The interval between the gate interconnections16a,16dand the gate interconnections16b,16c, i.e., the pitch of the gate interconnections is, e.g., about 0.16-0.2 μm.

On the source/drain diffused layers20,22,24,26,28,30,32,34,36,38, a silicide film52of, e.g., nickel silicide is formed. The silicide film52on the source/drain diffused layers20,22,24,26,28,30,32,34,36,38functions as the source/drain electrodes. On the gate interconnections16a-16d, the silicide film52of, e.g., nickel silicide is formed.

On the semiconductor substrate10with these transistors L1, L2, D1, D2, T1, T2formed on, an insulation film40of, e.g., silicon nitride is formed. The insulation film40is formed, filling the gaps between the gate electrodes16a-16d.

On the semiconductor substrate10with the insulation film40formed on, an insulation film42of, e.g., silicon dioxide is formed. The surface of the insulation film42is planarized by polishing. The insulation film40and the insulation film42form an inter-layer insulation film44.

In the inter-layer insulation film44, a contact hole (opening)46afor exposing the end of the gate interconnection16aand the source/drain diffused layer20of the load transistor L2is formed. The shape of the section of the opening46ain the direction parallel with the surface of the semiconductor substrate10is, e.g., substantially elliptical (seeFIG. 3). In the opening46a, a contact layer (conductor plug)48aof, e.g., tungsten is buried.

In the inter-layer insulation film44, an opening46bfor integrally exposing the end of the gate interconnection16band the source/drain diffused layer22of the load transistor L1is formed. The shape of the section of the opening46bin the direction parallel with the surface of the semiconductor substrate10is, e.g., substantially elliptical (seeFIG. 3). In the opening46b, a contact layer48bof, e.g., tungsten is buried.

The contact layers48a,48bare called shared contacts.

In the inter-layer insulation film44, an opening46cfor exposing the source/drain diffused layer24of the load transistor L1and an opening46dfor exposing the source/drain diffused layer30of the load transistor L2are formed. In the inter-layer insulation film44, an opening46efor exposing the source/drain diffused layer28of the driver transistor D1and an opening46ffor exposing the common source/drain diffused layer26of the driver transistor D1and the transfer transistor T1are formed. In the inter-layer insulation film44, an opening46gfor exposing the source/drain diffused layer36of the driver transistor T1and an opening46hfor exposing the source/drain diffused layer34of the driver transistor D2are formed. In the inter-layer insulation film44, an opening46ifor exposing the common source/drain diffused layer32of the driver transistor D2and the transfer transistor T2and an opening46jfor exposing the source/drain diffused layer38of the driver transistor T2are formed. In the inter-layer insulation film44, an opening46kfor exposing the gate interconnection16cand an opening46lfor exposing the gate interconnection16dare formed.

The shape of the section of the openings46c-46lin the direction parallel with the surface of the semiconductor substrate10is, e.g., substantially circular (seeFIG. 3). The diameter of the openings46c-46lis, e.g., 50-80 nm. In the openings46c-46l, contact layers48c-48lof, e.g., tungsten are buried.

In the inter-layer insulation film44, openings46m,46nare formed down to the insulation film12b. In the openings46m,46n, alignment marks48m,48nare buried.

The plane shape of the alignment marks48m,48nis, e.g., a frame shape.

The plane shape of the alignment marks48m,48nare not especially limited to the frame shape. The plane shapes of the alignment marks48m,48ncan be, e.g., a rectangle or others.

On the inter-layer insulation film44, interconnections50(seeFIGS. 2A and 2B) connected respectively to the contact layers48a-48lare formed.

The contact layer48aand the contact layer48iare electrically connected by the interconnection50. The contact layer48band the contact layer48fare electrically connected by the interconnection50.

The interconnection50connected to the contact layers48c,48dare electrically connected to a source voltage Vdd (seeFIG. 4). The interconnection50connected to the contact layers48e,48hare electrically connected to a source voltage Vss (seeFIG. 4).

The interconnections50connected to the contact layers46g,46jare electrically connected to the bit lines BL (seeFIG. 4). The gate interconnections16a,16bare electrically connected to the word line WL (seeFIG. 4) via contact layers not illustrated and the interconnections50.

FIG. 4is a circuit diagram of the memory cell of the semiconductor device according to the present embodiment.

As illustrated inFIG. 4, the load transistor L1and the driver transistor D1form an inverter54a. The load transistor L2and a driver transistor D2form an inverter54b. The inverter54aand the inverter54bform a flip-flop circuit56. The flip-flop circuit56is controlled by the transfer transistors T1, T2connected to the bit lines BL and the word line WL. The load transistors L1, L2, the driver transistors D1, D2and the transfer transistors T1, T2form the memory cell58.

[The Method for Manufacturing the Semiconductor Device]

Next, the method for manufacturing the semiconductor device according to the present embodiment will be described with reference toFIGS. 5A to 29B.FIGS. 5A to 29Bare views of the semiconductor device according to the present embodiment in the steps of the method for manufacturing the semiconductor device.FIGS. 5A to 10Bare sectional views.FIGS. 11A and 11Bare plan views corresponding to the views ofFIGS. 10A and 10B.FIGS. 12A and 12Bare sectional views.FIGS. 13A and 13Bare plan views corresponding to the views ofFIGS. 12A and 12B.FIGS. 14A to 19Bare sectional views.FIGS. 20A and 20Bare plan views corresponding to the views ofFIGS. 19A and 19B.FIGS. 21A and 21Bare sectional views.FIGS. 22A and 22Bare plan views corresponding to the views ofFIGS. 21A and 21B.FIGS. 23A and 23Bare sectional views.FIGS. 24A and 24Bare plan views corresponding to the views ofFIGS. 23A and 23B.FIGS. 25A and 25Bare sectional views.FIGS. 26A and 26Bare plan views corresponding to the views ofFIGS. 25A and 25B.FIGS. 27A and 27Bare sectional views.FIGS. 28A and 28Bare plan views corresponding to the views ofFIGS. 27A and 27B.FIGS. 29A and 29Bare sectional views.

First, as illustrated inFIGS. 5A and 5B, the semiconductor substrate (semiconductor wafer)10is prepared. As the semiconductor substrate10, a silicon wafer, for example, is used.

Next, a silicon oxide film53of an about 10 nm-film thickness is formed on the semiconductor substrate10by, e.g., thermal oxidation.

Next, a silicon nitride film55of an about 100 nm-film thickness is formed on the entire surface by, e.g., CVD (Chemical Vapor Deposition).

Next, a photoresist film57is formed on the entire surface by, e.g., spin coating.

Then, by using a reticle having the patterns of the active regions (device regions)11a-11dand the patterns of the alignment marks11e,11fformed on, these patterns are exposed on the photoresist film57.

Thus, the patterns of the active regions11a-11dand the patterns of the alignment marks11e,11fare transferred on the photoresist film57(seeFIGS. 6A and 6B). Specifically, the openings59afor forming the device isolation regions12a, and the openings59bfor forming the alignment marks11e,11fare formed in the photoresist film57.

Next, as illustrated inFIGS. 7A and 7B, the silicon nitride film55and the silicon oxide film53are etched with the photoresist film57as the mask.

Next, as illustrated inFIGS. 8A and 8B, with the photoresist film57as the mask, the semiconductor wafer10is etched to the trench13afor the device isolation region12ato be buried in and the trench13bfor the insulation film12bto be buried in are formed in the semiconductor wafer10.

Next, as illustrated inFIGS. 9A and 9B, an insulation film12of, e.g., a 500 nm-film thickness is formed in the trenches13a,13band on the semiconductor wafer10.

Then, the insulation film12is polished by, e.g., CMP (Chemical Mechanical Polishing). Then, the silicon nitride film55and the silicon oxide film53are etched off. Thus, the device isolation region12aand the insulation film12bare buried respectively in the trench13aand the trench13b. The alignment marks11e,11fare respectively defined by the insulation film12bburied in the trench13b(seeFIGS. 10A to 11B). The alignment marks11e,11fare formed respectively at plural parts of the periphery of the semiconductor chip.

The plane shape of the alignment marks11e,11fis, e.g., rectangle.

The plane shape of the alignment marks11e,11fis not limited to a rectangle. The plane shapes of the alignment marks11e,11fcan be, e.g., a frame-shape or others.

Thus, the active regions11a-11dare defined by the device isolation regions12a, and the alignment marks11e,11fare formed, defined by the insulation film12b.

Next, although not illustrated, ion implantation for forming wells (not illustrated) and ion implantation for forming the channel doped layers (not illustrated) are made in the active regions11a-11d, and then activation anneal is made.

Then, the gate insulation film14of silicon dioxide of, e.g., a physical film thickness 0.6-2 nm thickness is formed on the entire surface by, e.g., thermal oxidation.

Then, a polysilicon film of, e.g., a 70-120 nm-film thickness is formed on the entire surface by CVD (Chemical Vapor Deposition).

Then, a photoresist film (not illustrated) is formed on the entire surface by, e.g., spin coating.

Next, by using a reticle having the patterns of the gate interconnections16a-16dand the patterns of the alignment marks16e,16fformed on, these patterns are exposed on the photoresist film.

To align the reticle, the alignment mark11edefined by the isolation film12bis used.

Next, the photoresist film is developed.

Thus, the patterns of the gate interconnections16a-16dand the patterns of the alignment marks16e,16fare transferred on the photoresist film.

Then, with the photoresist film as the mask the polysilicon film is etched. Thus, the gate interconnections16a-16dof polysilicon and the alignment marks16e,16fof polysilicon are formed (seeFIGS. 12A to 13B).

The gate interconnection16ais formed linear, crossing the device regions11a,11c. The gate interconnection16bis formed linear, crossing the device regions11b,11d. The gate interconnection16cis formed linear, crossing the device region11d. The longitudinal directions of the gate interconnections16a-16dare in the same direction. The gate interconnections16aand the gate interconnection16bare formed, neighboring each other in parts of the regions. The gate interconnection16cis formed, positioned on the line extended from the gate interconnection16b. The gate interconnection16dis formed, positioned on the line extended from the gate interconnection16a. The width of the gate interconnections16a-16d, i.e., the gate length is, e.g., about 35-60 nm. The interval between the gate interconnections16a,16dand the gate interconnections16b,16c, i.e., the pitch of the gate interconnections is, e.g., about 0.16-0.2 μm. The alignment marks16e,16fare formed respectively at plural parts of the periphery of the semiconductor chip.

The plane shape of the alignment marks16eis, e.g., a frame-shape.

The plane shape of the alignment marks16eis not limited to the frame shape. The plane shape of the alignment mark16ecan be, e.g., a rectangle or others.

The plane shape of the alignment mark16fis, e.g., a rectangle.

The plane shape of the alignment mark16fis not limited to a rectangle. The plane shape of the alignment mark16fcan be a frame shape or others.

Thus, the gate interconnections16a-16dare formed while the alignment marks16e-16fare formed.

Then, a dopant impurity is implanted by ion implantation to form the extension regions (not illustrated) which form the shallow regions of the extension source/drain structure respectively in the semiconductor substrate10on both sides of the gate interconnections16a-16d.

Next, a silicon oxide film of, e.g., an about 30-60 nm is formed on the entire surface by, e.g., CVD.

Next, the silicon oxide film is etched by, e.g., anisotropic etching. Thus, the sidewall insulation film18of silicon dioxide is formed on the side walls of the gate interconnections16a-16d(seeFIGS. 14A and 14B).

A dopant impurity is implanted by ion implantation to form impurity diffused regions which form the deep regions of the extension source/drain structure in the semiconductor substrate10on both sides of the gate interconnections16a-16d. Thus, the source/drain diffused layers20,22,24,26,28,30,32,34,36,38(seeFIGS. 1A and 1B) having the extension regions and the deep impurity diffused regions are formed.

Then, heat processing (anneal) for activating the dopant impurity implanted in the source/drain diffused layers20,22,24,26,28,30,32,34,36,38is made. The heat processing temperature is, e.g., about 800-1200° C.

Then, a refractory metal film of a 5-30 nm-film thickness is formed on the entire surface by, e.g., sputtering. As the refractory metal film, nickel film, for example, is used.

Next, heat processing is made to react the surface of the semiconductor substrate10and the refractory metal film with each other while reacting the upper surfaces of the gate interconnections16a-16dand the refractory metal film with each other. Then, the unreacted refractory metal film is etched off. Thus, on the source/drain diffused layers20,22,24,26,28,30,32,34,36,38, the silicide film52of, e.g., nickel silicide is formed. The silicide film52on the source/drain diffused layers20,22,24,26,28,30,32,34,36,38function as the source/drain electrodes. On the gate interconnections16a-16d, the silicide film52of, e.g., nickel silicide is formed. On the alignment marks11e,11f,16e,16f, the silicide film52of, e.g., nickel silicide is formed (seeFIGS. 15A and 15B).

Next, the insulation film40of silicon nitride of, e.g., a 30-80 nm-film thickness is formed on the entire surface by, e.g., plasma CVD. The film forming conditions for the insulation film40are as exemplified below. That is, the frequency of high-frequency power to be applied is, e.g., 13.56 MHz. The gas to be fed into the film forming chamber is, e.g., a mixed gas containing SiH4gas, NH3gas and N2gas. The internal temperature of the film forming chamber is, e.g., 350-450° C. The insulation film40is formed, filling the intervals between the gate interconnections16a-16d(seeFIGS. 16A and 16B).

Then, the insulation film42of silicon dioxide of, e.g., an about 400-700 nm-film thickness is formed on the entire surface by, e.g., plasma CVD. The film forming conditions for the insulation film42are as exemplified below. That is, the frequency of the high frequency power to be applied is, e.g., 13.56 MHz. The gas to be fed into the film forming chamber is the mixed gas containing SiH4gas and N2O gas. The internal temperature of the film forming chamber is, e.g., about 350-450° C.

Next, the surface of the insulation film42is planarizsed by, e.g., CMP. The insulation film40and the insulation film42form the inter-layer insulation film44(seeFIGS. 17A and 17B).

Next, as illustrated inFIGS. 18A and 18B, a photoresist film60is formed on the entire surface by, e.g., spin coating.

Then, by photolithography, partial patterns61a1,61b1and the patterns61c-61lare exposed on the photoresist film60(seeFIGS. 19A to 20B). The partial patterns61a1,61b1are for forming the contact holes46a,46b. The patterns61c-61lare for forming the contact holes46c-46l. The partial patterns61a1,61b1are laid out, sufficiently overlapping parts of the gate interconnections16a,16b. The partial patterns61a1,61b1are laid out, sufficiently overlapping parts of partial patterns61a2,61b2(seeFIGS. 21A to 22B) which will be mentioned below. In aligning the first mask (the first reticle) (not illustrated) for exposing the partial patterns61a1,61b1and the patters61c-61l, the alignment is made by using the alignment mark16f.

The pattern of the alignment mark16fand patterns of the gate interconnections16a-16dwere transferred by using the same mask. Accordingly, no disalignment takes place between the alignment mark16f, and the gate interconnections16a,16b. The alignment mark16fis used in aligning the first mask, whereby the disalignment between the partial patterns61a1,61b1, and the gate interconnections16a,16bcan be made extremely small. Accordingly, the partial patterns61a1,61b1, and parts of the gate interconnections16a,16bcan be sufficiently overlapped.

Thus, the partial patterns61a1,61b1for forming the contact holes46a,46b, and the patterns61c-61lfor forming the contact holes46c-46lare exposed on the photoresist film60. At this time, the pattern61mof the alignment mark (not illustrated) of the first mask (not illustrated) is also exposed on the photoresist film60.

Then, by photolithography, partial patterns61a2,61b2are exposed on the photoresist film60(seeFIGS. 21A to 22B). The partial patterns61a2,61b2are for forming the contact holes46a,46btogether with the partial patterns61a1,61b1. The partial patterns61a2,61b2are laid out, sufficiently overlapping parts of the active regions11b,11a. The partial patterns61a2,61b2are laid out, sufficiently overlapping parts of the partial patterns61a2,61b2. In aligning the second mask (the second reticle) for exposing the partial patterns61a2,61b2, the alignment is made by using an alignment mark11f.

The pattern of the alignment mark11fand the patterns of the active regions11a-11dwere transferred by using the same mask. Accordingly, no disalignment takes place between the alignment mark11fand the active regions11a-11d. The alignment mark11fis used in aligning the second mask, whereby the disalignment between the partial patterns61a2,61b2and the active regions11b,11acan be made extremely small. Accordingly, parts of the partial patterns61a2,61b2and parts of the active regions11b,11acan be sufficiently overlapped.

Thus, the partial patterns61a2,61b2of the contact holes46a,46bare exposed on the photoresist film60. At this time, the pattern61nof the alignment mark (not illustrated) of the second mask is also exposed on the photoresist film60.

The partial patterns61a1,61b1and partial patterns61a2,61b2are thus exposed, whereby the parts of the partial patterns61a1,61b1and the parts of the partial patterns61a2,61b2are surely overlapped even when disalignments take place.

Next, the photoresist film60is developed. Thus, the openings70a-70lfor forming the contact holes46a-46l, the opening70mof the pattern of the alignment mark of the first mask, and the opening70nof the pattern of the alignment mark of the second mask are formed in the photoresist film60(seeFIGS. 23A to 24B).

As described above, according to the present embodiment, parts of the partial patterns61a1,61b1and parts of the gate interconnections16a,16bcan be sufficiently overlapped. According to the present embodiment, parts of the partial patterns61a1,61b1and parts of the active regions11b,11acan be sufficiently overlapped. Parts of the partial patterns61a1,61b1and parts of the partial pattern61a2,61b2are laid out, sufficiently overlapping each other. Accordingly, the opening70aof the photoresist film60is formed, sufficiently overlapping the end of the gate interconnection16aand the part of the source/drain diffused layer20of the load transistor L2. The opening70bof the photoresist film60is formed, sufficiently overlapping the end of the gate interconnection16band the part of the source/drain diffused layer22of the load transistor L1.

Then, with the photoresist film60as the mask, the inter-layer insulation film44is etched. Thus, the contact holes46a-46land the openings46m,46nare formed in the inter-layer insulation film44(seeFIGS. 25A to 26B).

As described above, the opening70aof the photoresist film60sufficiently overlaps the end of the gate interconnection16aand the part of the source/drain diffused layer20of the load transistor L2. Accordingly, the contact hole46asurely exposes integrally the end of the gate interconnection16aand the source/drain diffused layer20of the load transistor L2even when a disalignment takes place.

As described above, the opening70bof the photoresist film60sufficiently overlaps the end of the gate interconnection16band the part of the source/drain diffused layer22of the load transistor L1. Accordingly, the contact hole46bsurely exposes integrally the end of the gate interconnection16band the source/drain diffused layer22of the load transistor L1even when a disalignment takes place. The shape of the section of the contact holes46a,46bin the direction parallel with the surface of the semiconductor substrate10is, e.g., substantially elliptical (seeFIG. 3).

The contact hole46cis formed, exposing the source/drain diffused layer24of the load transistor L1. The contact hole46dis formed, exposing the source/drain diffused layer30of the load transistor L2. The contact hole46eis formed, exposing the source/drain diffused layer28of the driver transistor D1. The contact hole46fis formed, exposing the source/drain diffused layer26which is common between the driver transistor D1and the transfer transistor T1. The contact hole46gis formed, exposing the source/drain diffused layer36of the driver transistor T1. The contact holes46his formed, exposing the source/drain diffused layer34of the driver transistor D2. The contact hole46iis formed, exposing the source/drain diffused layer32which is common between the driver transistor D2and the transfer transistor T2. The contact hole46jis formed, exposing the source/drain diffused layer38of the driver transistor T2. The shape of the section of the contact holes46c-46jin the direction parallel with the surface of the semiconductor substrate10is, e.g., substantially circular (seeFIG. 3). The diameter of the contact holes46c-46lis, e.g., about 50-80 nm.

The openings46m,46nare formed down to the insulation film12b. The shape of the section of he openings46m,46nin the direction parallel with the surface of the semiconductor substrate10is, e.g., the frame shape.

Next, a Ti film of, e.g., a 2-10 nm-film thickness and a TiN film of, e.g., a 2-10 nm-film thickness are sequentially formed on the entire surface by, e.g., sputtering or CVD to form a glue layer.

Then, a tungsten film of, e g., a 70-100 nm-film thickness is formed on the entire surface by, e.g., sputtering.

Then, the tungsten film is polished by, e.g., CMP until the surface of the inter-layer insulation film44is exposed. Thus, the contact layers48a-48jof tungsten are buried in the contact holes46a-46l. In the openings46m,46b, the alignment marks48m,48nof tungsten are respectively buried (seeFIGS. 27A to 28B).

As described above, the contact hole46asurely exposes integrally the end of the gate interconnection16aand the part of the source/drain diffused layer20of the load transistor L2. Accordingly, the contact layer48asurely connects integrally the end of the gate interconnection16aand the source/drain diffused layer20of the load transistor L2.

As described above, the contact hole46bsurely exposes integrally the end of the gate interconnection16band the source/drain diffused layer22of the load transistor L1. Accordingly, the contact layer48bsurely connects integrally the end of the gate interconnection16band the part of the source/drain diffused layer of the load transistor L1.

Next, a conduction film is formed on the entire surface by, e.g., sputtering.

Then, the conduction film is patterned by photolithography to form the interconnections50respectively connected to the contact layers48a-48l(seeFIGS. 29A and 29B).

Thus, the semiconductor device according to the present embodiment is manufactured.

When a disalignment takes place in the method for manufacturing the semiconductor device according to the present embodiment, what is described below follows. The case of a disalingment will be described with reference toFIGS. 30A to 33B.FIGS. 30A to 33Bare plan views of the semiconductor device according to the present embodiment in the steps of the method for manufacturing the semiconductor device, which illustrate the case of a disalignment.

FIGS. 30A and 30Billustrate the case that a large disalingment takes place in the Y direction in transferring the patterns of the gate interconnections16a-16d. The patterns of the alignment marks16e,16f, which are also transferred simultaneously with transferring the patterns of the gate interconnections16a-16d, are disaligned largely with respect to the alignment marks11e,11f.

The alignment mark (not illustrated) of the first mask (not illustrated) is aligned with the alignment mark16f, whereby, as illustrated inFIGS. 31A and 31B, the ends of the gate interconnections16a,16band parts of the partial patterns61a1,16b1can be sufficiently overlapped.

The alignment mark (not illustrated) of the second mask (not illustrated) is aligned with the alignment mark11f, whereby as illustrated inFIGS. 32A and 32B, a part of the source/drain diffused layer20of the load transistor L2and the partial pattern61a2can be sufficiently overlapped. A part of the source/drain diffused layer22of the load transistor L1and a part of the partial pattern61b2can be sufficiently overlapped.

The contact hole46asufficiently exposes integrally the end of the gate interconnection16aand a part of the source/drain diffused layer20of the load transistor L2. The contact hole46bsufficiently exposes integrally the end of the gate interconnection16band a part of the source/drain diffused layer22of the load transistor L1.

As described above, according to the present embodiment, even when a large disalignment takes place, the contact hole46awhich surely exposes integrally the end of the gate interconnection16aand a part of the source/drain diffused layer20of the load transistor L2can be formed. According to the present embodiment, even when a large disalingment takes place, the contact hole46bwhich surely exposes integrally the end of the gate interconnection16band a part of the source/drain diffused layer22of the load transistor L1can be formed.

In the present embodiment, the partial patterns61a1,61b1for forming parts of the contact holes46a,46bare exposed on the photoresist film60in alignment with the alignment mark16ftransferred simultaneously with transferring the patterns of the gate interconnections16a,16b. Accordingly, parts of the partial patterns61a1,61b1and parts of the gate interconnections16a,16bcan be sufficiently overlapped. The partial patterns61a2,61b2for forming parts of the contact holes46a,46bare exposed on the photoresist film60in alignment with the alignment mark11ftransferred simultaneously with transferring the patterns of the active regions11a,11b. Accordingly, parts of the partial patterns61a2,61b2and parts of the active regions11b,11acan be sufficiently overlapped. Parts of the partial patterns61a1,61b1and parts of the partial patterns61a2,61b2are laid out, sufficiently overlapping each other. Thus, according to the present embodiment, the contact hole46asurely exposing integrally the end of the gate interconnection16aand a part of the source/drain diffused layer20of the load transistor L2can be formed. The contact hole46bsurely exposing integrally the end of the gate interconnection16band a part of the source/drain diffused layer22of the load transistor L1can be formed. Thus, according to the present embodiment, the contact layer48surely connecting integrally the end of the gate interconnection16aand the source/drain diffused layer20of the load transistor L2can be formed. The contact layer48bsurely connecting integrally the end of the gate interconnection16band a part of the source/drain diffused layer22of the load transistor L1can be formed. Thus, according to the present embodiment, the semiconductor device of high reliability can be manufactured with high yields.

[b] Second Embodiment

The semiconductor device manufacturing method according to a second embodiment will be described with reference toFIGS. 34A to 48B.FIGS. 34A to 48Bare sectional views of the semiconductor device in the steps of the semiconductor device manufacturing method according to the present embodiment, which illustrate the method.FIGS. 34A to 35are sectional views.FIGS. 36A and 36Bare plan views corresponding toFIG. 35.FIG. 37is a sectional view.FIGS. 38A and 39Bare plan views corresponding toFIG. 37.FIGS. 39A to 41are sectional views.FIGS. 42A and 42Bare plan views corresponding toFIG. 41.FIG. 43is a sectional view.FIGS. 44A and 44Bare plan views corresponding toFIG. 43.FIGS. 45A and 45Bare sectional views.FIGS. 46A and 46Bare plan views corresponding toFIGS. 45A and 45B.FIGS. 47A and 47Bare sectional views.FIGS. 48A and 48Bare plan views corresponding toFIGS. 47A and 47B. The same members of the present embodiment as those of the semiconductor device according to the first embodiment and its manufacturing method illustrated inFIGS. 1A to 33Bare represented by the same reference numbers not to repeat or to simplify their description.

The semiconductor device manufacturing method according to the present embodiment forms the contact holes46a-46lby using a hard mask.

First, the step of forming the silicon oxide film53on the semiconductor substrate10to the step of forming the inter-layer insulation film44are the same as those of the method for manufacturing the semiconductor device according to the first embodiment described above with reference toFIG. 5A to 17B, and their description will not be repeated.

Next, as illustrated inFIG. 34A, a silicon nitride film72of an about 30 nm-film thickness is formed by, e.g., plasma CVD. The silicon nitride film72is to be a hard mask.

Next, a photoresist film74is formed on the entire surface by, e.g., spin coating.

Then, in the same way as in the method for manufacturing the semiconductor device according to the first embodiment described above with reference toFIGS. 19A and 19B, the partial patterns61a1and61b1and the patterns61c-61l(seeFIGS. 19A to 20B) are exposed on the photoresist film74by photolithography (seeFIG. 34B).

As described above, the partial patterns61a1,61b1are for forming the contact holes46a,46b. As described above, the patterns61c,61lare for forming the contact holes46c-46l. The partial patterns61a1,61b1are laid out, sufficiently overlapping parts of the gate interconnections16a,16b. The partial patterns61a1,61b1are laid out, sufficiently overlapping parts of the partial patterns61a2,61b2to be described later (seeFIG. 40). In aligning the first mask (the first reticle) (not illustrated) for exposing the partial patterns61a1,61b1and the patterns61c-61l, the alignment is made by using the alignment mark16f(seeFIGS. 20A and 20B).

The pattern of the alignment mark16fand the patterns of the gate interconnections16a-16dwere transferred by using the same mask. Accordingly no disalignment takes place between the alignment mark16fand the gate interconnections16a,16b. The alignment mark16fis used in aligning the first mask, whereby the disalignment between the partial patterns61a1,61b1and the gate interconnections16a,16bcan be made extremely small. Accordingly, the partial patterns61a1,61b1and parts of the gate interconnections16a,16bcan be sufficiently overlap.

Thus, the partial patterns61a1,16b1for forming the contact holes46a,46band the patterns61c-61lfor forming the contact holes46c-46l(seeFIGS. 20A and 20B) are exposed on the photoresist film60. At this time, the pattern61m(seeFIGS. 19A to 20B) of the alignment mark (not illustrated) for the first mask is also exposed on the photoresist film74.

Then, the photoresist film74is developed. Thus, the openings76a,76bof the partial patterns61a1,61b1of the contact holes46a,46band the openings76c-76lfor forming the contact holes46c-46lare formed in the photoresist film74. The opening76mof the pattern of the alignment mark (not illustrated) of the first mask (not illustrated) is formed in the photoresist film74(seeFIGS. 35 to 36B).

As described above, parts of the partial patterns61a1,61b1and parts of the gate interconnections16a,16bare sufficiently overlapped. Accordingly, the openings76a,76band parts of the gate interconnections16a,16bare sufficiently overlapped.

Then, the silicon nitride film72is etched with the photoresist film74as the mask. Thus, a hard mask72with the openings78a1,78b1of the partial patterns of the contact holes46a,46band the openings78c-78lfor forming the contact holes46c-46lformed in is formed. In the hard mask72, an opening78mof the pattern of the alignment mark (not illustrated) of the first mask (not illustrated) is formed (seeFIGS. 37 to 38B).

As described above, the openings76a,76band parts of the gate interconnections16a,16bare sufficiently overlapped. Thus, the openings78a1,78b1and the parts of the gate interconnections16a,16bare sufficiently overlapped.

Next, as illustrated inFIG. 39A, the photoresist film74is removed by wet processing and asking.

Next, as illustrated inFIG. 39B, a photoresist film80is formed on the entire surface by, e.g., spin coating.

Then, the partial patterns61a2,61b2are exposed on the photoresist film80by photolithography (seeFIG. 40). The partial patterns61a2,61b2are laid out, sufficiently overlapping parts of the active regions11b,11a. The partial patterns61a2,61b2are laid out, sufficiently overlapping parts of the openings78a1,78b1. In aligning the second mask (not illustrated) for exposing the partial patterns61a2,61b2, the alignment is made by using the alignment mark11f.

The pattern of the alignment mark11fand the patterns of the active regions11a-11dwere transferred by using the same mask. Accordingly, no disalignment takes place between the alignment mark11fand the active regions11a-11d. The alignment mark11fis used in aligning the second mask, whereby the alignment between the partial patterns61a2,61b2and the active regions11b,11acan be made extremely small. Accordingly, parts of the partial patterns61a2,61b2and parts of the active regions can be sufficiently overlapped.

Thus, the partial patterns61a2,61b2of the contact holes46a,46bare exposed on the photoresist film80. At this time, the pattern61n(seeFIGS. 42A and 42B) of the alignment mark (not illustrated) for the second mask is also exposed on the photoresist film80.

The partial patterns61a2,61b2are thus exposed, whereby parts of the openings78a1,78b1and parts of the partial patterns61a2,61b2can be surely overlapped even when a disalignment takes place.

Then, the photoresist film80is developed. Thus, the openings82a,82bfor forming the partial patterns61a2,61b2of the contact holes46a,46band the opening82cof the pattern of the alignment mark are formed in the photoresist film80. Parts of the openings82a,82band parts of the active regions11b,11aare sufficiently overlapped (seeFIGS. 41 to 42B).

The hard mask72is etched with the photoresist film80as the mask. Thus, the partial patterns61a2,61b2of the contact holes46a,46bare transferred to the hard mask72. Thus, the openings78a,78bfor forming the contact holes46a,46bare formed in the hard mask72. The opening78nof the pattern of the alignment mark (not illustrated) of the second mask (not illustrated) is also formed in the hard mask72(seeFIGS. 43 to 44B).

As described above, parts of the openings82a,82band parts of the active regions11b,11aare sufficiently overlapped. Accordingly the parts of the openings78a,78band the parts of the active regions11b,11aare sufficiently overlapped. As described above, the openings78a1,78b1(seeFIG. 41) and parts of the gate interconnections16a,16bare sufficiently overlapped. Accordingly, the parts of the openings78a,78band the parts of the gate interconnections16a,16bare sufficiently overlapped.

Next, as illustrated inFIG. 45A, the photoresist film80is removed by wet processing and asking.

Next, the inter-layer insulation film44is etched with the hard mask72as the mask. Thus, the contact holes46a-46land the openings46m,46nare formed in the inter-layer insulation film44(seeFIGS. 45B to 46B).

As described above, parts of the openings78a,78band parts of the active regions11b,11aare sufficiently overlapped. Accordingly, parts of the contact holes46a,46band the parts of the active regions11b,11aare sufficiently overlapped. As described above, the parts of the openings78a,78band parts of the gate interconnections16a,16bare sufficiently overlapped. Accordingly, the parts of the contact holes46a,46band the parts of the gate interconnections16a,16bare sufficiently overlapped.

Thus, even when a disalingment takes place, the contact holes46acan surely expose integrally the end of the gate interconnection16aand the source/drain diffused layer20of the load transistor L2. Even when a disalignment takes place, the contact hole46bsurely exposes integrally the end of the gate interconnection16band the source/drain diffused layer22of the load transistor L1.

The semiconductor device manufacturing method following the above-described steps is the same as the method for manufacturing the semiconductor device according to the first embodiment described above with reference toFIGS. 27A to 29B, and its description will not be repeated.

Thus, the semiconductor device is manufactured by the semiconductor device manufacturing method according to the present embodiment (seeFIGS. 47A to 48B).

As described above, the inter-layer insulation film44may be etched by using the hard mask72. In the present embodiment, the partial patterns61a1,61b1for forming parts of the contact holes46a,46bare transferred to the hard mask72in alignment with the alignment mark16ftransferred simultaneously with transferring the patterns of the gate interconnections16a,16b. The partial patterns61a2,61b2for forming parts of the contact holes46a,46bare transferred to the hard mask72in alignment with the alignment mark11ftransferred simultaneously with transferring patterns of the active regions11a,11b. Parts of the partial patterns61a1,61b1and parts of the partial patterns61a2,61b2are laid out, sufficiently overlapped. Thus, according to the present embodiment as well, the contact hole46awhich can surely expose integrally the end of the gate interconnection16aand a part of the source/drain diffused layer20of the load transistor L2can be formed. The contact hole46bwhich can surely expose integrally the end of the gate interconnection16band the end of the source/drain diffused layer22of the load transistor L1can be formed. Thus, according to the present embodiment as well, the contact layer48awhich can surely connect integrally the end of the gate interconnection16aand the source/drain diffused layer20of the load transistor L2can be formed. The contact layer48bwhich can surely connect integrally the end of the gate interconnection16band a part of the source/drain diffused layer22of the load transistor L1can be formed. Thus, according to the present embodiment as well, the semiconductor device of high reliability can be manufactured with high yields.

The present invention is not limited to the above-described embodiments and can cover other various modifications.

For example, in the above-described embodiments, in the first exposure, the partial patterns61a1,61b1and the patterns61c-61mare exposed, and the partial patterns61a2,61b2,61nare exposed in the second exposure. However, this is not essential. For example, it is possible that in the first exposure, the partial patterns61a1,61b1and the pattern61mare exposed, and in the second exposure, the partial patterns61a2,61b2and the patterns61c-61l,61nare exposed in the second exposure.

In the above-described embodiments, the first exposure was made with the first mask aligned with the alignment mark16ftransferred simultaneously with transferring the patters of the gate interconnections16a,16b. The second exposure was made with the second mask aligned with the alignment mark11ftransferred simultaneously with transferring the patterns of the active regions11a,11b. However, the sequence of the exposures is not limited to this. For example, it is possible that the first exposure may be made with the second mask aligned with the alignment mark11ftransferred simultaneously with transferring the patterns of the active regions11a,11b, and the second exposure is made with the first mask aligned with the alignment mark16ftransferred simultaneously with transferring the patterns of the gate interconnections16a,16b.