Clocked based method and devices for measuring voltage-variable capacitances and other on-chip parameters

A characterization method for a device under test includes applying a bias voltage to a test circuit. The test circuit includes a first transistor coupled to the device under test, a second transistor coupled to the device under test and to the first transistor. A third transistor is coupled to a dummy device, a fourth transistor is coupled to the dummy device and to the third transistor. The transistors are of a common type. The characterization method further includes applying non-overlapping clocking signals to transistors of the test circuit to produce test signals for application to the device under test and detecting a current in one or more transistors from the device under test. The bias voltage is further varied to characterize the device under test.

BACKGROUND

The present invention is related generally to test methods and structures for integrated circuits. In particular, the present invention is related to clocked based methods and devices for measuring voltage-variable capacitances and other on-chip parameters.

Integrated circuits and their constituent components are tested for a variety of reasons. Completed circuits are tested for functionality and satisfaction of performance parameters. Such performance parameters include circuit speed or frequency of operation and power dissipation. Test cells on a circuit are tested for characterization of device parameters. Such device parameters include insulator dielectric capacitances, junction capacitances and threshold voltages in metal-oxide-semiconductor (MOS) integrated circuits, diode reverse bias leakage currents, dielectric tunneling currents, and, in non-volatile memory devices and standard MOS transistors, the location and density of trapped charges in gate dielectrics. Other circuit parameters are measured as well, such as metal interconnect resistance and interlayer capacitances. In particular, capacitance versus voltage characteristics, C-V curves, are among the most fundamental and popular analysis methods used in the semiconductor industry. These tests are performed during initial process design and characterization and for parametric data gathering even in mature semiconductor manufacturing processes.

Many of these tests require measurement of on-chip capacitances and similar values. Such measurements have grown increasingly unreliable and difficult to make as integrated circuit dimensions have decreased. A capacitance meter has been used, both manually and under automatic control. However, such a meter can be cumbersome, inaccurate and unreliable. For example, current capacitance meters have a resolution of approximately 1 pF. However, many device and interconnect capacitances of interest are in the range of 0.0-100 fF.

Although most on-chip capacitances of interest could be represented in test chip test structures, the large sizes of such structures often prevent their use. Achieving capacitance measurement structures that have enough capacitance to make accurate measurements possible requires that the structures be very large. These large structures consume inordinate amounts of valuable test chip space.

The maximum sizes of test chips are limited by the sizes of the stepping fields of the “wafer steppers” on which the test chips are manufactured. Wafer steppers are the lithographic systems that are currently used in most semiconductor manufacturing facilities for optically patterning the various layers of semiconductor products and of technology development test chips. Steppers use reticules (advanced photolithographic masks) to selectively expose specific areas of photographic emulsions on each wafer during wafer processing. This selective exposure determines the shapes and locations of the polygons that make up the structure of each layer on a semiconductor product or test chip.

Due to each stepper's optical constraints, the area of a wafer or exposure field that a stepper can pattern in a single exposure is limited. Normally, one exposure transfers the pattern from a complete reticule to the photographic emulsion on a wafer. A typical area of a single exposure is 2.5 cm by 2.5 cm. Typically, a single stepper will use a single reticule for patterning a given layer on all of the wafers in a manufacturing wafer lot. Each lot typically consists of 25 or 50 wafers. The stepper starts at one point on each wafer, exposes that location and then steps to the next location and exposes that location. The stepper repeats this process until it has stepped to and exposed all of the assigned locations on a wafer. Hence the term “stepper.”

Different reticules with different patterns are used for different layers. Normally however, only one reticule is used to pattern a single given layer on all of the wafers in a manufacturing wafer lot. Steppers are generally not interrupted in the midst of stepping a wafer lot for the sake of changing to a second reticule. Changing reticules requires that a stepper be disabled for a significant period of time. Any such stepper “down time” is prohibitively costly. The cost of a new semiconductor manufacturing facility's steppers are a major fraction of the cost of the entire facility (on the order of $100 million out of the typical $1 billion that is spent in building and equipping a facility). It would be very impractical, for example, to use one reticule to pattern a layer on a portion of the wafers in a wafer lot and to then to switch to a different reticule to pattern that same layer on the wafers in the remainder of the wafer lot.

Thus the sizes and numbers of test structures that can be placed into a process development test chip are strictly limited to the structures that will fit together into the limited wafer area that is afforded by a single stepper exposure field. While designing the test structures for a test chip, it is common for engineers to make very difficult decisions as to which test structures they will include in the test chip and which test structures they will not include. Omitting structures can often lead to an engineering group later painfully realizing that it does not have the test structures needed answering critical technology development questions. In short, test chip area is extremely costly and reducing the sizes of test structures while maintaining the efficacy of the structures is desirable.

A technique has been developed for measuring on-chip voltage independent capacitance. In “A Simple Method for On-Chip, Sub-Femto Farad Interconnect Capacitance Measurement,” McGaughy et al., IEEE Electron Device Letters, Vol. 18, No. 1, January 1997, a technique and circuit are disclosed which permit measuring on-chip capacitances with high resolution. The test structures that the technique uses consume significantly less test chip area than do previous techniques. An on-chip test circuit uses four transistors in addition to the unknown capacitance to be characterized. No reference capacitor is required and resolution down to 0.03 fF is provided. Measurement may be conducted automatically or manually.

While the disclosed technique is useful for measuring voltage independent capacitance, a large class of device and circuit characteristics are voltage dependent or voltage variable. That is, the capacitance of a device or interconnect or other structure varies with applied voltage. Examples include gate capacitance of a MOS transistor or the capacitance of a reverse biased diode. Further, parameters other than capacitance vary with applied voltage and are not measurable with the disclosed technique. These include leakage current in a reverse biased diode and dielectric tunneling currents. All of these voltage variable parameters are key to device characterization and modeling and essential to process control. However, none of these parameters is available using the technique as disclosed in the above-identified reference.

Accordingly, there is a need for an improved method and apparatus for characterizing on-chip devices, currents and capacitances that are variable with applied voltage. Ideally the method will have enough measurement resolution and precision to allow the accurate characterization of capacitors that are small enough to be economically included in technology development test chips.

SUMMARY

By way of introduction only, the embodiments illustrated herein disclose methods and apparatus for measuring device parameters such as capacitances including voltage variable capacitances. A test circuit allows the current and voltage characteristics of the device parameter to be measured while excluding parasitic effects. A bias voltage is varied while clocked test signals are applied to the test circuit. In one embodiment, the transistors of the test circuit are fabricated in a well to isolate them from the substrate potential of the semiconductor substrate. This permits application of both positive and negative voltages for complete characterization of device and circuit parameters.

The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation on the following claims, which define the scope of the invention.

BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS

FIG. 1is a schematic diagram of a test circuit for measuring integrated circuit parameters;

FIG. 2illustrates exemplary waveforms for activating the test circuit ofFIG. 1;

FIG. 3is an exemplary curve illustrating capacitance as a function of average effective DC voltage resulting from the test circuit ofFIG. 1;

FIG. 4is a schematic diagram of a test circuit to be used in conjunction with the test circuit inFIG. 1;

FIG. 5is a block diagram of a circuit for providing the clocking signals ofFIG. 2;

FIG. 6is a circuit in partial-block, partial schematic form for multiplexing signals to test circuits of an integrated circuit;

FIG. 7is an alternative embodiment of the circuit ofFIG. 6;

FIG. 8is a schematic diagram of exemplary device layouts of on-chip capacitors for measuring device parameters in conjunction with the test circuit ofFIG. 1;

FIG. 9is a schematic diagram of an exemplary on-chip circuit which uses the test circuit ofFIG. 1for measuring the gate capacitance and other device parameters of a common MOSFET transistor.

FIG. 10is a schematic diagram of a second exemplary on-chip circuit which uses the test circuit ofFIG. 1for measuring the gate capacitance and other device parameters of two different geometries of common MOSFET transistors;

FIG. 11is a schematic diagram of a second exemplary on-chip circuit which uses the test circuit ofFIG. 1for measuring the drain to gate capacitances, drain to substrate capacitances, source to gate capacitances, source to substrate capacitances, and other device parameters of two different geometries of common MOSFET transistors;

FIG. 12is a schematic diagram of an exemplary on-chip circuit which uses the test circuit ofFIG. 1for measuring the drain to gate capacitance, drain to substrate capacitance, the source to gate capacitance, source to substrate capacitance, and other device parameters of a common MOSFET transistor;

FIG. 13illustrates the various combinations of measurement arrangements for measuring and isolating the individual node to node capacitances associated with a three or more electrode capacitance structure;

FIG. 14is a schematic diagram of an exemplary on-chip circuit which uses the test circuit ofFIG. 1for measuring device parameters of a floating gate flash EPROM (erasable programmable read only memory) memory core cell transistor;

FIG. 15is a schematic diagram of a second exemplary on-chip circuit which uses the test circuit ofFIG. 1for measuring device parameters of two different geometries of floating gate flash EPROM memory core cell transistors;

FIG. 16is a schematic diagram of an exemplary on-chip circuit which uses the test circuit ofFIG. 1for measuring device parameters of a flash EPROM memory core cell transistor;

FIG. 17is a schematic diagram of a second exemplary on-chip circuit which uses the test circuit ofFIG. 1for measuring device parameters of one geometry of flash EPROM memory core cell transistor;

FIG. 18is a schematic diagram of an exemplary on-chip circuit which uses the test circuit ofFIG. 1for measuring device parameters of a flash EPROM memory core cell transistor with a connection being provided for separately biasing the transistor's floating gate node;

FIG. 19is a schematic diagram of a second exemplary on-chip circuit which uses the test circuit ofFIG. 1for measuring device parameters of a second geometry of flash EPROM memory core cell transistor to the second transistor's other nodes, with connections being provided for separately biasing each of the transistors' floating gate nodes;

FIG. 20is a schematic diagram of an exemplary on-chip circuit which uses the test circuit ofFIG. 1for measuring device parameters of a flash EPROM memory core cell transistor, with a connection being provided for separately biasing the transistor's control gate node;

FIG. 21is a schematic diagram of a second exemplary on-chip circuit which uses the test circuit ofFIG. 1for measuring device parameters of a flash EPROM memory core cell transistor, with connections being provided for separately biasing each of the transistors' control gate nodes;

FIG. 22illustrates a cross sectional view of a MOSFET transistor, a cross sectional view an NROM memory core cell transistor, and a schematic symbol for an NROM memory core cell transistor;

FIG. 23illustrates the gate capacitance as a function of applied DC gate voltage of an uncharged (erased) NROM memory core cell transistor;

FIG. 24illustrates the gate capacitance as a function of applied DC gate voltage;

FIG. 25illustrates the superimposed gate capacitances as functions of applied DC gate voltage of an uncharged (erased) NROM memory core cell transistor and of a charged NROM memory core cell transistor;

FIG. 26illustrates the superimposed gate capacitances as functions of applied DC gate voltage of an NROM memory core cell transistor under various operating conditions;

FIG. 27is a schematic diagram of an exemplary on-chip circuit which uses the test circuit ofFIG. 1for measuring device parameters;

FIG. 28is an exemplary on-chip circuit in partial-block, partial schematic form which uses the test circuit ofFIG. 1for measuring device parameters;

FIG. 29is an illustration of an exemplary on-chip circuit in partial schematic, partial layout form which uses two copies of the test circuit ofFIG. 1for measuring device parameters;

FIG. 30is an illustration of an exemplary on-chip circuit in partial schematic, partial layout form which uses two copies of the test circuit ofFIG. 1for measuring device parameters;

FIG. 31is an illustration of an exemplary on-chip circuit in partial schematic, partial layout form which uses two copies of the test circuit ofFIG. 1for measuring device parameters;

FIG. 32is an illustration of an exemplary on-chip circuit in partial schematic, partial layout form which uses two copies of the test circuit ofFIG. 1for measuring device parameters;

FIG. 33is an illustration of an exemplary on-chip circuit in partial schematic, partial layout form which uses two copies of the test circuit ofFIG. 1for measuring device parameters;

FIG. 34is an illustration of an exemplary on-chip circuit in partial schematic, partial layout form which uses two copies of the test circuit ofFIG. 1for measuring device parameters;

FIG. 35is a schematic diagram of a test circuit for measuring reverse biased diode leakage currents which uses capacitances previously characterized with the test circuit ofFIG. 1;

FIG. 36is an exemplary waveform for activating the test circuit ofFIG. 35 and aresultant waveform;

FIG. 37is a schematic diagram of a test circuit for measuring tunnel currents through a dielectric which uses capacitances previously characterized with the test circuit ofFIG. 1; and

FIG. 38is a schematic diagram of a circuit for multiplexing signals to multiple test circuits which are similar to the test circuits shown in FIG.35and in FIG.37.

DETAILED DESCRIPTION OF PRESENTLY PREFERRED EMBODIMENTS

Referring now toFIG. 1, it shows a schematic diagram of a test circuit100used for measurement of integrated circuit parameters. The test circuit100includes a first transistor102, a second transistor104, a third transistor106and a fourth transistor108. The third transistor is substantially the same in all regards as the first transistor. The fourth transistor is substantially the same in all regards to the second transistor. The test circuit100is connected to a device under test110, in this case a capacitance labeled CDUT(Device Under Test Capacitance). In addition, the test circuit100includes a dummy capacitance112, labeled CDUMMY. The device under test110is positioned between an output105of the test circuit100and the substrate114. Similarly, the dummy capacitance112is electrically located between a node107and the substrate114. Note that the device under test capacitance and the dummy capacitance are connected to the substrate114in this embodiment. Alternatively, in other embodiments, they could instead be connected to an independently biased node (for example they could be connected to a doped well in the substrate, or to a plate of metal interconnect or poly silicon interconnect residing over the substrate).

It is envisioned that the test circuit100will be manufactured on a semiconductor substrate114along with other devices forming an integrated circuit or a wafer of integrated circuits. By appropriate application of control signals, to be described herein, a wide variety of circuit and device parameters may be characterized, automatically or manually, using one or more test circuits, such as the test circuit100.

Each of the transistors102,104,106,108is preferably of the same doping type. InFIG. 1, each transistor is a p-channel transistor. More specifically, each of the transistors102,104,106,108is formed by defining P+ diffusion areas in an n-well defined in the p-type substrate114. Preferably, standard semiconductor processing techniques are used to manufacture the test circuit100along with the conventional devices which form an integrated circuit or a wafer of integrated circuits. Thus, the test circuit100may be included as a component of a test circuit or test chip on the wafer, or may be included as a test circuit within an individual integrated circuit of the wafer. Alternatively, the test circuit and other test devices may be included in the scribe grid of the wafer so as not to take up any active space of the wafer of integrated circuits.

The test circuit100is suitable for testing a device under test110. The device under test may be a device such as a transistor or a diode, a portion or parasitic component of a device such as the gate oxide capacitance, or tunnel oxide capacitance of a non-volatile memory cell transistor, or a portion or parasitic of another component of an integrated circuit such as the capacitance associated with interconnect metal.

A dummy device or capacitance112is typically also included. Preferably, the dummy capacitance contains all of the parts of the device under test capacitance110that are not portions of the capacitance of interest. Specifically, in most embodiments, the dummy capacitance and node107contain a copy of the parasitic (undesired) capacitances that are associated with the device under test capacitance and node105. The purpose here is for duplicates of all of the parasitic capacitances associated with node105to be associated with node107. In this way, the measurement structure ofFIG. 1can be used to measure both the device under test capacitance and the dummy capacitance and the difference between the two resultant capacitance values will be the capacitance of interest. Normally, many of the parts of the device under test capacitance are duplicated in the dummy capacitance. These duplicated parts are the portions of the structure of the device under test for which capacitance is not desired to be measured (it is desired that these portions of the capacitance be excluded from the final capacitance result).

The first transistor102has a source connected to a bias node116labeled VHigh2 in FIG.1. The first transistor102has a drain connected to an output105of the test circuit100. The first transistor102has a gate connected to a first clocked node122, labeled Clock Up. The second transistor104has a source connected to the output105, a drain connected to a second bias node118, labeled VLow inFIG. 1, and a gate connected to a second clocked node124, labeled Clock Down. Similarly, the third transistor has a source connected to a third bias node120, labeled VHigh1, a drain connected to the output107, and a gate connected to the first clocked node122. Still further, the fourth transistor108has a source connected to the output107, a drain connected to the second bias node118, and a gate connected to the second clocked node124.

Thus, the test circuit100includes a first transistor pair130including first transistor102and second transistor104connected with the device under test110. The test circuit100further includes a second transistor pair132including the third transistor106and the fourth transistor108. The third transistor106and the first transistor102have a common gate connection134configured to be driven by a first variable voltage at the first clocked node122. The third transistor and the first transistor receive a first variable bias voltage at the nodes116,120. The fourth transistor108and the second transistor104have a common gate connection136configured to be driven by a second variable voltage at the second clocked node124. The fourth transistor108and the second transistor104receive a second variable bias voltage at the second bias node118. In the preferred embodiment, bias voltage VHIGHis applied to node116and the current flowing into node116is measured in order to determine the combined capacitance of the device under test capacitor CDUT110and the parasitic capacitance associated with node105(CPARASITIC-105). Subsequently, the bias voltage VHIGHis applied to node120and the current flowing into node120is measured in order to determine the combined capacitance of the dummy capacitor CDummy112and the parasitic capacitance associated with node107, (CPARASITIC-107).

FIG. 2illustrates exemplary waveforms for activating the test circuit100of FIG.1. InFIG. 1, a first clocking signal202labeled Clock Up, is applied to the first clocked node122of the test circuit100in FIG.1. Similarly, a second clock signal204labeled Clock Down, is applied to the second clocked node124of FIG.1. The first clock signal202and the second clock signal204are preferably non-overlapping clock signals. That is, the high and low states of the two clock signals202,204are arranged so that the two transistors of the first transistor pair130are not conducting simultaneously. Similarly, the high and low states of the two clock signals202,204are arranged so that the two transistors of the second transistor pair132are not conducting simultaneously.

Thus, in the exemplary embodiment ofFIG. 2, at the time t0, the first clock signal202has a value VCLOCK-UP-LOWand the second clock at204has a value VCLOCK-DOWN-HIGH. In this state, the first transistor102is turned on and is conducting current. The second transistor104, also a p-channel transistor, is turned off and not conducting. After time t1, the first clock signal202transitions from VCLOCK-UP-LOWto VCLOCK-UP-HIGH, turning off the first transistor102. After time t2, the second clock signal204transitions from VCLOCK-DOWN-HIGHto VCLOCK-DOWN-LOWturning on the second transistor104.

From time t3to time t4, the second transistor104is turned on and conducting. Meanwhile, the first transistor102is turned off. From time t4to time t5, the second clock signal204transitions from a voltage VCLOCK-DOWN-LOWto a voltage VCLOCK-DOWN-HIGHturning off the second transistor104. From time t5until time t6, the first clock signal202transitions from voltage VCLOCK-UP-HIGHto a voltage VCLOCK-UP-LOW, turning on the first transistor102. Subsequently, after time t6, the first transistor102is turned on and conducting. The cycle repeats again starting at time t7. This repetition occurs with a frequency f, typically 500,000 Hz. Depending upon the application, the clocking frequency can be very slow, such as 5,000 Hz or less, or fairly fast, such as 2,000,000 Hz or greater.

During times such as t0to t1, with the first transistor102turned on and conducting, the device under test110is charged from a voltage VLOWto a voltage equal to VHIGH. During a subsequent time period from t3to t4, the device under test110is discharged through the second transistor104from a voltage VHIGHto a voltage equal to VLOW. During each of these charging and discharging cycles all of the capacitances associated with node105are charged and discharged. These capacitances include the device under test capacitance and all of the parasitic capacitances associated with node105, including CPARASITIC-105; the diode capacitances associated with the drain of transistor102and the source of transistor104, the gate to drain capacitance of transistor102, the gate to source capacitance of transistor104, the interconnect capacitances connected to node105, etc. The amount of charge transferred from node116to node118via node105during each cycle is equal to the product of the total capacitance associated with node105(device under test and parasitic) and the difference in the charging voltage VHIGHand the discharging voltage VLOW. This transferred charge results in an average current flowing from node116to node118which is equal to the product of the transferred charge per cycle and the cycling frequency f. By measuring the average current via node116into transistor102, the sum of the device under test capacitance and the parasitic capacitance associated with node105can be determined.

Normally, so that the same current measurement device can be used to measure the current associated with the dummy capacitance and the device under test capacitance, the two capacitances are measured at different times. It is desirable to use the same current measurement device for measuring both capacitances so that the two measurements will be equally affected by any errors in calibration of the current measurement device.

Measurement of the dummy capacitance,112, is normally conducted in the same fashion as the measurement of the device under test capacitance. During the dummy capacitance measurement, transistors106and108respectively inFIG. 1are treated in the same fashion as transistors102and104were during the device under test capacitance measurement. As with transistors102and104, transistors106and108are normally p-channel transistors. Node120is treated in the same fashion as was node116. Node107is treated in the same fashion as was node105.

Thus, in the exemplary embodiment ofFIG. 2, at the time t0, the first clock signal202has a value VCLOCK-UP-LOWand the second clock at204has a value VCLOCK-DOWN-HIGH. In this state, the third transistor106is turned on and able to conduct current. The fourth transistor108is turned off and not conducting. After time t1, the first clock signal202transitions from VCLOCK-UP-LOWto VCLOCK-UP-HIGH, turning off the third transistor106. After time t2, the second clock signal204transitions from VCLOCK-DOWN-HIGHto VCLOCK-DOWN-LOWturning on the fourth transistor108. From time t3to time t4, the fourth transistor108is turned on and conducting. Meanwhile, the third transistor106is turned off. From time t4to time t5, the second clock signal204transitions from a voltage VCLOCK-DOWN-LOWto a voltage VCLOCK-DOWN-HIGHturning off the fourth transistor108. From time t5until time t6, the first clock signal202transitions from voltage VCLOCK-UP-HIGHto a voltage VCLOCK-UP-LOW, turning on the third transistor106. Subsequently, after time t6, the third transistor106is turned on and conducting. The cycle repeats again starting at time t7. As with the measurement of the device under test capacitance, this repetition occurs with a frequency f, typically 500,000 Hz.

During times such as t0to t1, with the third transistor106turned on and conducting, the dummy capacitance112is charged from a voltage VLOWto a voltage equal to VHIGH. During a subsequent time period from t3to t4, the dummy capacitance112is discharged through the fourth transistor108from a voltage VHIGHto a voltage equal to VLOW. During each of these charging and discharging cycles, all of the capacitances associated with node107are charged and discharged. These capacitances include the dummy capacitance and all of the parasitic capacitances associated with node107(CPARASITIC-107; the diode capacitances associated with the drain of transistor106and the source of transistor108, the gate to drain capacitance of transistor106, the gate to source capacitance of transistor108, the interconnect capacitances connected to node107, etc.). The amount of charge transferred from node120to node118via node107during each cycle is equal to the product of the total capacitance associated with node107(dummy capacitance and parasitic) and the difference in the charging voltage VHIGHand the discharging voltage VLOW. This transferred charge results in an average current flowing from node120to node118which is equal to the product of the transferred charge per cycle and the cycling frequency f. By measuring the average current via node120into transistor106, the sum of the dummy capacitance and the parasitic capacitance associated with node107can be determined.

In turn, the above procedures apply effective average DC biases of (VHIGH+VLOW)/2 to the device under test110and to the dummy capacitor112. In the illustrated embodiment, referring to the measurement of the device under test capacitor as an example, the voltage VHIGHon node116is varied along with VLOWon node118to characterize the voltage dependence of the capacitance of the device under test110and the accompanying parasitic capacitances associated with node105. The values of VLOWand VHIGHare preferably kept close to one another so that measured capacitances will be accurate for the effective DC bias in the vicinity of VLOWand VHIGH. Moreover, the difference between the values of VLOWand VHIGHis maintained constant as VLOWand VHIGHare varied together. In one typical embodiment, the difference between the voltage values VLOWand VHIGHwill be on the order of 0.2 volts. Other values can also be used for this difference. Note that the values of voltages VLOWand VHIGHapplied to nodes118and116respectively when measuring the device under test capacitance are normally the same as the values of the voltages VLOWand VHIGHapplied to nodes118and120respectively when measuring the dummy capacitance.

The DC voltage that results from the average of VLOWand VHIGHcan be varied over a wide range of voltage, from negative to positive voltage. For example, at one data point, the value of VHIGHis set at 3.1 volts and the value of VLOWis set at 2.9 volts. In the case when VHIGHis applied to116, the average of VHIGHand VLOW, 3.0 volts, is the effective DC voltage applied to the device under test10(assuming that the substrate114is grounded). For device under test capacitors that have their non-switched common nodes connected to a node other than the substrate (114), the overall average voltage applied across the device under test capacitor is the difference in voltage between the average effective DC voltage applied to node105(3.0 volts in this example) and the voltage applied to the non-switched common node. All of the above procedures and analysis can also be analogously applied to the measurement of the dummy capacitance and the parasitic capacitance associated with node107.

With the values of the bias voltages VHIGH(on node116) and VLOW(on node118) set as described above, the clock nodes122,124are supplied with the clock signals202and204as shown in FIG.2. Preferably, this measurement technique is repeated across a wide range of voltages VHIGHand VLOW. VHIGHand VLOWare varied together across the measurement range, for example, from +3 to −3 volts, keeping the same difference, such as 0.2 volts, between the two bias voltages. Thus, at one data point, VHIGHis set at +0.1 volts and VLOWis set at −0.1 volts, producing an effective average DC voltage applied to the device under test110of 0 volts. At a subsequent data point, VHIGH2is set to a value of −0.9 volts and VLOWis set to a value of −1.1 volts, producing an effective average DC value of −1.0 volts across the device under test110.

As the values of VHIGHand VLOWare varied, the high and low voltage values of the clock signals202and204(VClockupHigh, VClockupLow, VClockDownHigh, and VClockDownLow) are normally also varied to maintain the clock signals' abilities to turn on and turn off the transistors102,104,106and108. Again, the above procedures and analysis can also be analogously applied to the measurement of the dummy capacitance and the parasitic capacitance associated with node107.

Equations 1 and 2 yield the sum of the device under test capacitance and the parasitic capacitance associated with node105(CDUT+CParasitic-105), and the sum of the dummy capacitance and the parasitic capacitance associated with node107(CDUMMY+CParasitic-107)CDUT+CParasitic⁢-⁢105=I(Average⁢⁢Into⁢⁢Node⁢⁢116)(VHIGH⁢⁢Applied⁢⁢To⁢⁢Node⁢⁢116-VLOW)·fEquation⁢⁢1CDummy+CParasitic⁢-⁢107=I(Average⁢⁢Into⁢⁢Node⁢⁢120)(VHIGH⁢⁢Applied⁢⁢To⁢⁢Node⁢⁢120-VLOW)·fEquation⁢⁢2
In these two equations, “f” is the cycling frequency of the clocking signals202and204.

In the preferred embodiment, the parasitic capacitances associated with nodes105and107(CParasitic-105, and CParasitic-107) are made to be equal. This is normally accomplished in semiconductor test chips by making the physical layouts of the various portions of nodes105and107be geometrically and structurally the same in each node. Often this equivalence is achieved by constructing the physical structures of nodes105and107as geometric mirror images of one another. In this way the parasitic capacitances associated with node105and with node107can be regarded as being equivalent to one another.
CParasitic-105=CParasitic-107Equation 3

In equation 4, the dummy capacitance and the parasitic capacitance associated with node107are subtracted from the device under test capacitance and the parasitic capacitance associated with node105. The parasitic capacitances associated with node107in equation 4 cancel the parasitic capacitances associated with node105. This cancellation occurs because all of the portions of nodes105and107except for the device under test capacitor and the dummy capacitor are normally constructed identically or in mirror image to their counterparts in the other node. Accordingly, equation 4 yields the desired difference in the values of the device under test capacitor and the dummy capacitor. A primary goal in the development of the device under test capacitor and the dummy capacitor is to construct the two capacitors in such a way that their difference is a structure which has a capacitance of interest, namely the desired capacitance.
CDesired=CDUT+CParasitic-105−CDummy−Parasitic-107Equation 4

Ultimately, by separating the values of VHIGH2and VLOWby a small voltage (for example 0.2 volts) and then sweeping the values of VHIGH2and VLOWtogether across a range of voltages (for example from −3 volts to +3 volts), and applying the above described methods at each voltage in the voltage range, a C-V curve (a capacitance versus voltage curve) that is characteristic of the device under test capacitance can be created. Similarly a C-V curve that is characteristic of the dummy capacitance can also be created. Subtracting the dummy capacitance curve from the device under test capacitance curve yields a C-V curve that is characteristic of the capacitance of interest over the voltage range. This capacitance is characteristic of the desired capacitance.FIG. 3shows an exemplary C-V curve302for a voltage variable capacitance that could result from the above outlined devices and procedures.

The test circuit100ofFIG. 1, operated in conjunction with the test signals202,204ofFIG. 2, provides unique advantages over the measurement technique disclosed in “A Simple Method For On-Chip Sub Femto Farad Interconnect Capacitance Measurement” of McGaughy, et al. In that disclosure, transistors analogous to the second transistor104and the fourth transistor108are n-channel transistors formed in the p-type substrate114. Further, to prevent the n-channel transistors' n-type source diffusions from forward biasing their diodes with the p-type substrate, the voltage applied to the sources (analogous to VLOWinFIG. 1) must be constrained to voltage levels above the substrate potential (often the ground potential). Furthermore, McGaughy, et al. connect the sources of their n-channel transistors to the substrate, further constraining the voltage on their node analogous to VLOWinFIG. 1to the substrate's ground potential (0 volts).

Thus, the test circuit ofFIG. 1allows the application of voltages to the nodes VLOWand VHIGHthat are independent of the substrate voltage and all other node voltages. The second bias node118is independent of the substrate and all other nodes. Also, the test circuit100employs switching devices that are capable of applying VLOWand VHIGHvoltages that can be both negative as well as positive with respect to the non-clocked electrode or terminal of the capacitor or other device under test. This non-clocked node is shown as P-substrate in the example of FIG.1. The circuit ofFIG. 1enables the measurement of capacitances over a range of average effective DC voltages (positive to negative). In short, the circuit ofFIG. 1enables the measurement of common capacitance versus voltage characteristics, C-V curves. The ability to measure C-V curves is of fundamental value to the practice of developing and manufacturing integrated circuits.

The use of p-channel transistors in n-wells formed in the p-substrate is particularly suitable for an n-well CMOS technology. In other processes, any transistor that can be biased independently from the substrate node would likely be suitable for switching. Examples include n-channel transistors and p-channel transistors in a twin tub process or n-channel transistors in a p-well formed in an n-substrate process. Further, other waveforms besides the waveforms of the test signals202,204may be substituted. For example, sinusoids, triangle waves and other variations in the high and low voltage values may be advantageous for measurement accuracy, stability, repeatability and reproducibility. For example, sinusoids, having fewer harmonics than the square waves illustrated inFIG. 2, helped to reduce signal noise and reflections in a test setup. The peak to peak voltages and the average voltages of the clock signals can also be varied in order to optimize capacitance measurement accuracy. Some of this optimization can be guided through circuit simulation of the measurement circuit (FIG.1and its variations) and the applied input signals.

FIG. 4is a schematic diagram of a circuit that can be used in conjunction with the test circuit100ofFIG. 1. Aportion of the test circuit100ofFIG. 1is repeated in FIG.4. The circuit ofFIG. 4can be useful in diagnosing problems in the test circuit of FIG.1. The circuit ofFIG. 4can be used for measuring the voltages on the internal node105of a copy of the test circuit ofFIG. 1(also shown as node105in FIG.4). InFIG. 4, additional transistors402,404have been added to the test circuit of FIG.1. Preferably, the transistor404is electrically identical to the transistor402. For example, the transistor404normally has an identical geometrical structure to that of the transistor402and is normally in close proximity to the transistor402so that the two transistors402,404experience similar fabrication, temperature, and other processing and environmental effects. As indicated inFIG. 4, the source of the transistor402is electrically connected to a probe pad406and the drain of the transistor402is electrically connected to a probe pad408. Similarly, the source of the transistor404is electrically connected to a probe pad410, the gate of the transistor404is electrically connected to a probe pad412and the drain of the transistor404is electrically connected to a probe pad414.

The circuit ofFIG. 4permits determination of the voltage on the internal node105of a copy of the test circuit100(FIG.1). The voltage at node105can be determined by setting the drain and source voltages of transistors402,404equal to each other. That is, the voltage applied to probe pad408is set the same as the voltage applied to probe pad414while the voltage applied to probe pad406is set the same as the voltage applied to probe pad410. These voltages may be established using automatic test equipment, for example, during final wafer test, or can otherwise be applied during bench testing. Further, the voltage on the gate of the transistor404is varied until the current through transistor404matches the current through transistor402. Once equivalent currents are achieved, since the transistors402and404and their biasing are substantially identical, then the voltage on the gate of transistor402is the same as the voltage applied to the gate of the transistor404. The voltage on the gate of transistor404can be varied, for example, using automatic test equipment, by binary searching the voltage applied at the probe pad412until the currents in the transistors402and404are substantially equal.

In the preferred embodiment, the sense circuit which detects the voltage at node105is implemented using on chip devices. If the gate of transistor M1inFIG. 4is connected to node107in a copy of circuit100instead of to node105, then the resultant circuit can be used to measure the voltage on node107.

Having knowledge of the voltages on nodes105and107can be important. For example, when the voltage on the second clocked node124is raised to shut off the transistor108, some of the rise in voltage on node124may be connected to node107via the gate to source capacitance of transistor108. The portion of the voltage on node124that occurs after transistor108is shut off could perhaps in some cases contribute to a perturbation in the voltage on node107. Due to this perturbation, node107may no longer be at a voltage VLOW. This deviation from VLOWmay perhaps cause errors in the capacitance measured using the techniques described herein. Having knowledge of whether or not the perturbation occurs and knowing the exact amount of perturbation, if any, could lead to ways for counteracting the perturbation.

FIG. 5is a block diagram of a circuit500for providing the clocking signals of FIG.2. This circuit would be used as an alternative to having an automated parametric test system provide the clocking signals required for driving the test circuit ofFIG. 1(on nodes122and124). The circuit500includes a control circuit502, a voltage controlled oscillator (VCO)504, gating circuitry506and a frequency divider508. Circuit500is preferably fabricated on the same semiconductor substrate as the test circuit100of FIG.1.

The control circuitry502includes an interface510and digital to analog converters (DACs)512,514,516. The interface510includes a plurality of probe pads520for exchanging signals with an automated parametric test system, external to the semiconductor substrate that includes circuit500. It is envisioned that, in measurements, probes will contact the probe pads520to permit exchange of electrical signals between the external parametric test system and the circuit500. In the preferred embodiment, interface510receives digital signals from the parametric test system and provides digital signals to the parametric test system. In alternative embodiments, analog signals or a combination of analog and digital signals could be used instead of digital signals. The digital signals received from the parametric test system define, for example, the clock high voltage, the clock low voltage, and the period of the clocked signals to be applied to the test circuit100.

The DACs512,514,516of the control circuit502convert received digital data from the parametric test system interface510to analog on-chip levels for use by test circuit100. DAC512converts digital data to a voltage corresponding to VHIGH. The DAC514converts digital data to a voltage corresponding to VLOW. The DAC516converts digital data from the parametric test system interface510to an analog voltage for controlling the voltage controlled oscillator504. The voltages Vhighand VLOWare provided from the DAC512and the DAC514, respectively, to the gating circuitry506. The voltage controlled oscillator504, in response to the voltage received from the DAC516, produces an oscillating signal. This oscillating signal is provided to the gating circuitry506. The gating circuitry506responds to the high voltage DC level and the low voltage DC level received from the DACs512,514, respectively and to the oscillating signal received from the voltage controlled oscillator by providing the clocking signals required by the test circuit100. The outputs of the gating circuitry506are the clock signal labeled CLOCK UP (202) and the clock signal labeled CLOCK DOWN (204) in FIG.2.

For monitoring the clock frequency of the circuit500, a feedback path is provided to the frequency counter508. The counter508receives the CLOCK DOWN signal from the gating circuitry506. The counter508divides the frequency of the CLOCK DOWN signal down to a lower value. The divided signal is provided to the control circuitry502and in turn provided to one of the probe pads520.

The frequency division counter508divides the on-chip frequency of the CLOCK DOWN signal down to a frequency that the parametric test system can monitor with standard measurement hardware. Since typical parametric test systems are designed to operate at dc or at low frequencies, dividing the frequency of the on-chip signal down to a lower value allows the clock frequency of the circuit500to be monitored by the parametric test system. The divider508provides a means for the parametric test system to monitor the clock frequency of circuit500without substantial modification to the parametric test system's hardware or software. Alternatively, a circuit for dividing the on chip frequency down to a more manageable level may be located off chip from the circuit500. A range of frequency division that is suitable for most applications is division by 10 to 10,000,000.

Often multiple test circuits100and their associated devices under test110and dummy capacitors112can be constructed in smaller spaces on a test wafer than can the probe pads that are required for connecting such circuits to parametric test systems. Accordingly, using just a few probe pads to control many such circuits100can be very advantageous from the standpoint of saving space on test wafers and test chips. Moreover, using just a few probe pads to control many test circuits100is a likely requirement for economically placing large numbers of capacitance measurement circuits100and their associated devices under test and dummy capacitors into product wafer scribe lines (scribe grids). The circuits in FIG.6and inFIG. 7provide methods for controlling large numbers of test circuits100with a relatively small number of probe pads.

FIG.6andFIG. 7illustrate circuits in partial block, partial schematic form for multiplexing signals to multiple copies of test circuit100. Each test circuit100ofFIG. 1is generally suitable for testing a single device under test110. However, for characterizing a semiconductor fabrication process or an individual wafer or substrate, many device and circuit parameters should be characterized. These include voltage variable capacitances such as metal-oxide-semiconductor capacitances and reverse biased junction capacitances, as well as voltage invariant capacitances such as interconnect capacitances. For each such capacitance, it may be desirable to characterize different sized devices or different geometries and configurations of interconnect layers. This allows, for example, characterization of capacitance due to device area as well as perimeter. Use of an automatic parametric test system allows application of control signals and collection of large amounts of data for a variety of device parameters through software control of the parametric test system. By having the parametric test system interrogate a large number of test circuits of the form100, the device and circuit parameters associated with each such test circuit can be characterized. Doing this permits substantially complete characterization of a given technology's device capacitances and a large number of its other device and process parameters.

The embodiments of FIG.6andFIG. 7are two examples of various possible ways for using relatively small numbers of probe pads to control a large number of test circuits100. Using fewer probe pads saves substantial test chip space. Both FIG.6andFIG. 7illustrate the circuitry and method that allow the sharing of individual test structure probe pads by numerous device test structures, that is multiplexing of test structure probe pads.

InFIG. 6, the multiplexing technique is implemented by connecting numerous copies of test circuit100to the same probe pad in a parallel-connected configuration. In the exemplary embodiment ofFIG. 6, the test circuits100are all substantially identical. Each test circuit100is connected to a device under test labeled CDUTA1, CDUTB1, etc. Each test circuit100is substantially implemented and operated as illustrated above in FIG.1. The test circuits are arranged generally in an array of rows and columns. Each row of test circuits shares a common node for the CLOCK UP signal and a separate common node for the CLOCK DOWN signal. Along columns, each test circuit of a column shares a common node for the bias voltage VHIGH1, and a separate common node for the bias voltage VHIGH2. In this embodiment, all test circuits100share a single separate common node for the bias voltage VLOW.

Thus, to activate an individual test circuit merely requires providing appropriate bias voltages at the bias probe pads and providing appropriate clocking signals at the appropriate clocking probe pads. For example, to activate the test circuit602and device under test CDUTA1at the top left ofFIG. 6, an appropriate bias voltage is applied to the probe pad604labeled VHIGH1and another appropriate bias voltage is applied to the probe pad608labeled VLOW. Similarly, test circuit602's dummy capacitance CDUMA2can be accessed by applying an appropriate bias voltage to probe pad606(labeled VHIGH2). In the preferred embodiment CDUTA1and CDUMA2would normally be accessed at separate times. However, with very extensive, extremely accurate and well calibrated measurement equipment, CDUTA1and CDUMA2could be measured simultaneously. With such equipment, all of the devices in a single row could be simultaneously measured; CDUTA1, CDUMA2, CDUTA3, CDUMA4, etc.

Continuing with the example of measuring the capacitance Of CDUTA1, appropriate clock signals are provided to the clock up probe pad610and to the clock down probe pad612. Appropriate deselect voltages are provided to the circuit's other clocking probe pads, including probe pad618labeled Clock Up B and probe pad620labeled Clock Down B; and probe pad622labeled Clock Up C and probe pad624labeled Clock Down C. In the preferred embodiment, the clocking transistors in the test circuit100ofFIG. 1, transistors102,104,106, and108are all p-channel MOSFET's in n-doped wells in a p-doped substrate. Thus, shutting off these transistors and deselecting their circuits100inFIG. 6merely requires setting the transistors' clock probe pads (their gates), Clock Up B, Clock Down B, Clock Up C, and Clock Down C to a positive voltage which is higher in potential than the values of the voltages on the VHIGH1probe pad604and the VHIGH2probe pad606.

In this manner, each test circuit can be uniquely selected to permit characterization of an individual device under test. By identifying the device under test associated with each probe pad combination, a software program routine can be written for a parametric test system to apply the proper voltages to the proper probe pads in the proper sequence with the proper timing to fully characterize each device under test.

The circuit600further includes isolation resistors630connected between each of the clock probe pads610,612,618,620,622,624, and a clock off probe pad632. By biasing the common clock off probe pad632to a voltage that will deselect the respective test circuits, all of the nodes that control the test circuits may be biased to voltages that will deselect the test circuits. InFIG. 6, the resistors630have an exemplary value of 10 KΩ. However, any suitable value may be used.

The measurement structure or test circuit to be selected is selected by biasing two of the common switch nodes so that the switches that they control are turned on and turned off at the appropriate times during measurements. For example, Clock Up B probe pad618and Clock Down B probe pad620can be selected to activate one of the test circuits100in the second row of the circuit600of FIG.6. The Clock Off probe pad632is biased to a voltage that is appropriate to shut off all of the deselected test circuits100that do not have their Clock Up and Clock Down nodes biased otherwise. In this example it is assumed that the switch transistors102,104,106, and108of circuit600's copies of circuit100are all p-channel enhancement transistors. As such, a sufficient positive voltage applied to the Clock Off probe pad will deselect all of the test circuits100except for the one that is selected. The Clock Off probe pad is connected through resistors632to the gates of transistors102,104,106, and108in circuit600's copies of circuit100. This deselect voltage applied to the Clock Off probe pad must be more positive than the voltages applied to the various VHigh1, VHigh2, etc probe pads. The clocking voltages applied directly to the Clock Up B probe pad618and to the Clock Down B probe pad620overcome the deselect voltage that would otherwise be applied to the two probe pads by the resistors630connected to Clock Off probe pad632.

In this manner, test circuits using multiplexed VHIGHand VLOWprobe pads can be clocked with just five probes. A first probe is placed on the Clock Off probe pad632. A second and a third probe are placed on the Clock Up and Clock Down probe pads of the test circuit to be interrogated. Two probes are used to bias the VLOWprobe pad, the appropriate VHIGHprobe pad, and to measure the current into the VHIGHprobe pad. This method is very helpful when bench testing is accomplished with a limited number of individual probes, i.e., without a probe card or without an automated parametric test system. Alternatively, of course, any suitable method of electrically stimulating and sensing the circuit600, such as by bonding out the probe pads to a ceramic or plastic package containing the integrated circuit, may be used.

In an alternative embodiment, the resistors630ofFIG. 6may be implemented as transistors. In one embodiment, p-channel transistors with long narrow channels are employed with the transistor gates connected to their respective Clock Up and Clock Down nodes. These p-channel transistors are fabricated in n-doped wells in the semiconductor substrate. Similarly, a p-well technology could just as well use n-channel transistors in p-wells. Still further, a test circuit100to be interrogated could be selected by turning on and turning off appropriate isolation transistors that are implemented in series with the test structures. The isolation transistors could be controlled by on chip circuitry, off chip circuitry or a combination of the two. For example, each test circuit100may have a set of logic signals corresponding to an address which is unique among the addresses of all the test circuits in the circuit600. By providing the appropriate logic signals to be decoded as the address of a unique test circuit100, that test circuit may be activated or interrogated.

In another alternative embodiment, the circuit ofFIG. 6could be altered to eliminate additional probe pads. Specifically all but one of the clock down probe pads can be eliminated. Clock Down A pad612, Clock Down B pad620, Clock Down C pad624, etc. could all be connected to one common probe pad. Individual rows of circuits100could be deselected by setting the Clock Up probe pad for each deselected row to a voltage that would turn off the transistors102and106in the deselected test circuits100(seeFIG. 1for transistor designations). In this example, as in that above, the transistors102and106are p-channel transistors and shutting them off in deselected circuits would require a positive voltage applied to their Clock Up probe pads. This voltage would be high and positive relative to the voltage applied to the VHIGH1probe pad of the selected circuit100and the VHIGH2probe pad of the selected circuit100. As with the circuit shown inFIG. 6, the particular device under test capacitor or dummy capacitor (CDUTor CDUM) to be chosen from among the capacitors on a selected row of circuits100, is selected by merely applying voltage VHIGHto the appropriate VHIGH1, VHIGH2, or VHIGH3, etc. probe pad and then measuring the current into that probe pad.

FIG. 7is an example of a circuit that can be used similarly to the circuit inFIG. 6to employ a relatively small number of probe pads to provide a method for characterizing a large number of device under test capacitors and dummy capacitors. The circuit700ofFIG. 7, however, is applied specifically to the characterization of capacitances which are portions of various transistors (in this example MOSFET's such as those used in CMOS products). In addition to some of the ways that the circuit inFIG. 6can alleviate space consuming probe pads, the circuit ofFIG. 7minimizes the number of drain and source probe pads that are necessary for correctly biasing the MOSFET's that form the device under test capacitors and the dummy capacitors. A circuit that is used for measuring the gate capacitances of MOSFET's must provide for the DC biasing to various choices of voltages of the transistor gates, drains, and sources while gate capacitance is being measured. Further, the circuit must provide for the DC biasing of each transistor's gate, the biasing of each transistor's drain, the biasing of each transistor's source, and the measurement of the drain current into each transistor with biases applied. The circuit700ofFIG. 7fulfills these requirements while also reducing the number of probe pads that the circuit requires.

As inFIG. 6, the test circuits100ofFIG. 7are arranged generally in an array or matrix of rows and columns. Each test circuit100is associated with a device under test730,734,738,742,746,750, etc. and with a dummy device732,736,740,744,748,752, etc. Selecting a specific device to characterize can be accomplished by applying appropriate clocking signals to the clock up and clock down nodes associated with the row of test circuits in which the selected device resides, applying appropriate inhibiting voltages to the clock up and clock down nodes associated with the rows of the other test circuits, applying appropriate voltages to the VLow and VHigh nodes, such as nodes708,710, etc. associated with the column of devices under test or dummy devices that the selected device resides in, applying inhibit voltages to the VLow and VHigh nodes of the other columns of devices and then applying voltages to the drain and source nodes of the row of devices that the device resides in.

These concepts can best be understood through two general examples. The first example will be of an embodiment of a method for measuring the DC drain current through n-channel MOSFET746(a device under test transistor) inFIG. 7while the transistor is undergoing DC biasing. The second example will illustrate a method for measuring the capacitance of the gate of the same transistor while the transistor is undergoing an effective average DC gate bias, a drain bias and a source bias. In these embodiments, all of the device under test transistors and dummy transistors ofFIG. 7are assumed to be fabricated in the technology's p-doped substrate. Transistors in doped wells and in other types of substrates could also be characterized in this same general fashion. Further the examples assume that the transistors102,104,106, and108in the test circuits100(ofFIG. 1) shown in the circuit700ofFIG. 7are all p-channel MOSFET transistors in n-doped wells in a p-doped substrate technology.

For example, the DC drain current characteristics of transistor746can be measured through applying the following biases to the circuit700of FIG.7. An appropriately large negative voltage is applied to the Clock Up B probe pad (node702) and the voltage that is desired to be applied to the gate node of transistor746is applied to the VHigh3 probe pad (node710). This combination of biases will cause the transistor106of the circuit100associated with transistor746to turn on and pass the chosen gate voltage to the gate of transistor746. Alternatively, an appropriately large negative voltage could be applied to the Clock Down B probe pad (node704) and the voltage that is desired to be applied to the gate node of transistor746would be applied to the VLow3 probe pad (node708). This combination would pass the chosen gate voltage through the108transistor of the same test circuit100. Continuing with the first example, an appropriately large negative voltage would be applied to the other VHigh probe pads (VHigh1, VHigh2, VHigh4, etc.) in order to turn off unselected transistors734,736,748, etc. Then the desired drain and source voltages would be applied to the drain and source probe pads VDrain-B(node713) and VSource-B(node720), respectively. Finally the drain current of transistor746would be measured as the current flowing into the drain probe pad VDrain-B(node713). The current flowing into VDrain-B(node713) can only pass from the drain to the source of transistor746because the VHigh or VLow biasing associated with the other transistors on transistor746's row has turned off all of the transistors on that row except for transistor746.

In a second example, the gate capacitance of device under test transistor746and the parasitic capacitances associated with that gate node can be measured through applying the following biases and signals to the circuit700of FIG.7. Signals as described in the discussion of FIG.1andFIG. 2are applied to the Clock Up B probe pad (node702) and to the Clock Down B probe pad (node704). Appropriate high positive voltages are applied to the non-selected row Clock Up and Down nodes (Clock Up A, Clock Down A, Clock Up C, Clock Down C, etc.) in order to turn off transistors102,104,106, and108of circuits100on the unselected rows. In this way, the only current path that current traveling into the VHigh3 node (710) can travel is through transistors106and108of the test circuit100associated with the gate of transistor746. As described in the discussions of FIG.1andFIG. 2, appropriate voltages are applied to the VHigh3 node and the VLow3 node and the current flowing into the VHigh3 node is measured in order to determine the sum of the gate capacitance of transistor746and the parasitic capacitance associated with the rest of transistor746's gate node. Equating this result with similar results from transistors having other channel widths and channel lengths provides a way to determine, for example, the capacitance per unit area of the gate of a typical transistor. More examples extracting various transistor parameters will be discussed below in conjunction with discussions of specific transistor related device structures.

It is important to note thatFIG. 7is only one possible embodiment of ways to reduce the number of probe pads required for test structures that are designed for measuring transistor gate capacitances. As with the circuit ofFIG. 6, the number of probe pads used by circuit700(FIG. 7) can be further reduced by connecting all of the circuit's Clock Down nodes together to one common clock down node probe pad.

Consider again the example of measuring DC drain current. In this case however, the clock down nodes of circuit700would be linked to a single common probe pad. In this arrangement, the various Clock Up nodes would be used to gate appropriately large negative DC voltages from the unselected column VHigh nodes into the gates of the unselected transistors730,734,736,738,740,742,744,746,748,750,752in order to turn off the unselected transistors. With the clock down nodes linked together the DC current into the drain of transistor746could, for example, be measured through the second row's drain node (VDrain-B,713) by biasing the common clock down node to an appropriately high positive voltage (turning off transistors108and104on all test circuits100of FIG.7), biasing all clock up nodes to an appropriately large negative voltage (and turning on all transistors106and102), applying an appropriate large negative voltage to the unselected column VHigh nodes (turning off all unselected transistors730through752), and applying the desired voltage to the gate of transistor746via the VHigh3 node and transistor746's associated transistor106.

In the common clock down node scheme, the gate capacitance of transistor746can be measured by blocking current from passing through transistors106of the test circuits associated with transistors742, and750, etc. This current blocking is brought on by applying appropriately large positive voltages to nodes Clock Up A, and Clock Up C, etc. In this way, current from the node VHigh3 can only pass through transistor106of the test circuit100associated with transistor746.

FIG. 8illustrates one example of a set of test capacitors800that can be used for characterizing the gate capacitance of a given type of metal oxide semiconductor field effect transistor (MOSFET). The test capacitors800include a first capacitor802, a second capacitor822and a third capacitor832. In this embodiment, capacitor802is substituted for the CDUTcapacitor110in a first copy of test circuit100. Capacitor822is substituted for the CDummycapacitor112in the first copy of test circuit100. Capacitor832is substituted for the CDUTcapacitor110in a second copy of test circuit100. In all cases, the gate nodes814,824, and842of the capacitors shown inFIG. 8would be connected to the appropriate choices of nodes105for capacitor802and capacitor832or node107for capacitor822. In this example, the N+ source/drain node of each capacitor is connected to a probe pad or other electrical connection not shown in FIG.8.

In this example, the capacitors802,822, and832are formed as n-channel capacitors in the p-doped substrate of an N-well in p-substrate CMOS process technology. Capacitor802has source/drain diffusion808connected to metal (not shown) via contacts810and also has the substrate node. Capacitor802has gate poly silicon806connected to metal via contacts812. The capacitor's poly silicon gate and source/drain are separated by one of the technology's various gate dielectrics such as a thin layer of silicon dioxide. Similarly, capacitor822has source/drain diffusion804connected to metal (not shown) via contacts828and also has the substrate node. Capacitor822has gate poly silicon820connected to metal via contacts826. The capacitor's poly silicon gate and source/drain are separated by one of the technology's various gate dielectrics such as a thin layer of silicon dioxide. Capacitor832has source/drain diffusion834connected to metal (not shown) via contacts838and also has the substrate node. Capacitor832has gate poly silicon830connected to metal via contacts844. The capacitor's poly silicon gate and source/drain are separated by one of the technology's various gate dielectrics such as a thin layer of silicon dioxide.

In the simplest embodiment, all of these source/drain connections are connected to probe pads to allow connection to the probes associated with an automated parametric test system. The substrate is also connected to a probe pad. The switching portion of test circuit800is identical to the switching portion of test circuit100ofFIG. 1(the VHigh1 node120, VHigh2 node116, Clock Up node122, Clock Down node124, the VLow node118, and transistors102,104,106, and108). The biasing and capacitance measurement procedure for test circuit800largely parallels that described above in conjunction with test circuit100of FIG.1.

Test circuit800ofFIG. 8allows the source/drains808,804and834of capacitors802,822and832to be biased during gate capacitance measurement. As pointed out in the discussion of test circuit100ofFIG. 1, appropriately biasing the VHigh2 node and the VLow node allows an effective average DC bias to be applied to node105during capacitance measurement. In this case, node105of the first copy of test circuit100is the gate electrode of MOS capacitor802. Similarly, the gate of MOS capacitor822can be biased during capacitance measurement via appropriate biasing of VHigh1 and VLow of the first copy of the test circuit100. Similarly, the gate of MOS capacitor832can be biased during capacitance measurement via appropriate biasing of VHigh2 and VLow of the second copy of the test circuit100.

In this way, during gate capacitance measurement, the source/drain, gate, and substrate of each MOS capacitor802,822and832can be separately biased to any level that would normally be appropriate for such capacitors and the MOSFET's that they are associated with in the given technology. For example, MOS capacitor802's gate capacitance can be measured with the capacitor's semiconductor surface operating in an accumulated mode (VGS<0), in depletion (VFlatBand<VGS<VThreshold), or in inversion (VThreshold<VGS).

By appropriately choosing the geometries of capacitors802,822, and832, test capacitors800can be developed which can lead to the determination of various MOS capacitor capacitance parameters, transistor capacitance parameters, and various general transistor parameters. In the example shown inFIG. 8, the main rectangular portion of capacitor802is 32 micrometers (um) by 32 um with an area of 1024 um2and a perimeter of 128 um. The main rectangular portion of capacitor822is 60 um by 4 um with an area of 240 um2and a perimeter of 128 um. The main rectangular portion of capacitor832is 256 um by 4 um with an area of 1024 um2and a perimeter of 520 um. Capacitors802,822and832are normally created using the same gate insulator thickness and gate dielectric material. Using dimensions such as these brings about cancellations of the area components of gate capacitance and of the perimeter components of gate capacitance when measured capacitances from the various capacitors in800are subtracted from one another. The gate areas of capacitors802and822are different by 784 um2but their gate perimeter lengths are equal at 128 um. When the result of measuring the gate capacitance of capacitor822is subtracted from the result of measuring the gate capacitance of capacitor802, the resultant difference is the gate to channel region capacitance due to substantially 784 um2of pure gate to channel region (without any perimeter component or gate to source/drain overlap or fringing fields involved). It is important to note that the specific shapes of capacitor802and capacitor822are constructed so that non-ideal effects will cancel when the capacitances are subtracted. Both capacitors have three gate corners over their respective source/drain regions. Both capacitors have gate to metal connections which are identical in shape. The same cancellations hold true for the capacitor832. When the capacitance of capacitor832is subtracted from the capacitance of capacitor802, the capacitance due to substantially 392 um of perimeter results. MOSFET's having the same gate, source, and drain processing as these capacitors will have gate to source and gate to drain capacitances per micrometer of source and drain width that will be the same as this perimeter capacitance.

It is important to note that many critical process parameters and device parameters can be derived from the capacitance versus voltage characteristics that these structures can provide. Among these parameters are threshold voltages versus source to substrate or source to well bias, flat band voltages, information on charge trapping, gate oxide capacitance, information on gate oxide purity, depletion region capacitance and thickness, information on transistor channel doping density, transistor gate to drain and gate to source fringing field capacitances, etc.

FIG. 9illustrates one example of an application of the test circuit100ofFIG. 1in which the device under test capacitance110is replaced in a test circuit900with MOSFET transistor910(Metal Oxide Semiconductor Field Effect Transistor). In this configuration the gate906of transistor910is connected to node105and will allow the test circuit900to measure the sum of the gate capacitance of transistor910, the parasitic capacitance associated with the interconnect to the gate of910and the other parasitic capacitances associated with node105. The drain of transistor910is connected to probe pad902and the source of the transistor is connected to probe pad904. For this example, the transistor is an n-channel enhancement transistor that resides in the p-doped substrate114.

In test circuit900, the dummy capacitance112of the test circuit100is replaced with a copy,912, of the interconnect to the gate906of transistor910. In the various embodiments of this circuit, this copy of transistor910's gate connection can be made to contain more or less parts of the interconnect to910and more or less parts of the gate of transistor910. These choices depend upon which parts of the gate capacitance of transistor910are desired to be measured. In one embodiment, for example, the dummy capacitor912contains only a copy of the metal line to the gate of910. In another,912contains a copy of the metal line to the gate of910, a copy of the small portion of the gate poly silicon that the metal line is connected to, and copies of the contacts that connect the metal line to the gate. In these example embodiments, the contacts to the poly silicon gate do not reside over the channel of the transistor but instead make contact to a portion of the poly silicon gate which is fabricated over thick oxide, for example the field oxide over the substrate adjacent to the transistor, normally much thicker than the transistor's gate oxide.

Following procedures described in conjunction with the discussion of FIG.1andFIG. 2, the gate capacitance of the transistor910can be characterized over a range of effective average DC gate voltages. The capacitance of interconnect912is also characterized and transistor912's measured capacitance is subtracted from the capacitance deriving from the measurement of transistor910's gate capacitance. In this way, the capacitance of transistor910's gate can be separated from the capacitance of910's gate interconnect and from the parasitic capacitances associated with node105. The pure gate capacitance of transistor910can be determined. Further, using this method, the gate capacitance characteristic of transistor910can be determined for a range of gate voltages (negative to positive) and under various conditions of drain bias and source bias.

FIG. 10is an illustration of a circuit1000for measuring various aspects of gate capacitance of a MOSFET. The circuit1000ofFIG. 10is very similar to the circuit900of FIG.9. The device under test capacitance of circuit1000, transistor1010is very similar (perhaps the same as) transistor910in the circuit900of FIG.9.FIG. 10continues the concept of adding more portions of the device under test transistor to the dummy capacitor. In the case of test circuit1000, the dummy capacitor is a complete transistor. In this embodiment, the dummy transistor1012has a channel length or a channel width which differs from the dimensions of the device under test transistor1010. In the case of test circuit1000, there are not strong reasons for referring to either device1012or1010as dummy or device under test. Devices1010and1012are each full transistors. Normally, transistor1010and transistor1012have different channel lengths or different channel widths.

A number of versions of the circuit1000ofFIG. 10can be used in order to provide for the comparison of the capacitances of a number of devices. Purposely forming each device with a different geometry can lead to the determination of various device parameters. Comparing the capacitances of devices having varying channel lengths, L (for example, a set of devices with width to length ratios of 20 um/10 um, 20 um/5 um, 20 um/2 um, and 20 um/1 um), can lead to the determination of gate to channel capacitance per unit length of channel for a given channel width (20 um in this case). Comparing this information with that garnered from another set of devices having the same channel lengths as the first set, L, but having a different channel width, W, (for example, a set of devices with width to length ratios of 5 um/10 um, 5 um/5 um, 5 um/2 um, and 5 um/1 um), can lead to a determination of gate to channel capacitance per unit area. Such analysis can also lead to a determination of the capacitances associated with the edges of transistor channels (the edges parallel to the flow of current). Other combinations of geometries can also lead to the determination of the capacitances from the gates to the drains and gates to the sources of the transistors.

For example, the gate capacitances of transistors of various channel widths but having the same channel length can be compared to determine the combined gate to channel, gate to source, and gate to drain capacitances of a strip of transistor stretching from the drain to the source. This strip does not include the effects of the field edges of the channel. The field edges are the edges of the channel parallel to current flow. Having several groups of transistors of this sort, each group with its own common channel length, can lead to a determination of the gate to source and gate to drain capacitance of a given type of transistor. Part of this determination involves measuring the gate capacitances of the various transistors under several bias conditions. These conditions include channel in accumulation, in depletion, and in inversion.

As with transistor910of the circuit900, transistors1010and1012each have drains and sources connected to probe pads. These probe pads enable the biasing of the transistors into their various operating modes (for n-channel transistors; accumulation with the gate to source voltage well below threshold voltage and the transistor turned off; depletion with the gate to source voltage somewhat below threshold voltage and the transistor turned off but near turn on; inversion in saturation with the gate to source voltage above threshold voltage and the transistor turned on but with the gate voltage below the drain voltage; and inversion in linear with the gate to source voltage above threshold voltage and the transistor turned on with the gate voltage above the drain voltage).

Using appropriate combinations of the circuits800,900and1000(having appropriate choices of capacitor and transistor geometries) can lead to the full characterization of gate to accumulated channel capacitance, gate to inversion layer capacitance, gate to channel depletion region capacitance, gate to source capacitance, and gate to drain capacitance. The circuits800,900, and1000can be applied to all types of MOSFET transistors (residing in various substrates, doped wells, and having various types of source and drain doping and channel doping), MESFET transistors (Metal Semiconductor Field Effect Transistors), JFET transistors (Junction Field Effect Transistors), bipolar junction transistors (in which the base is used as the node whose primary capacitance is to be measured, and in which the transistor is biased so that the device will remain turned off), and any other types of devices in which the devices' switch control nodes (gates, bases, etc.) are maintained in a largely insulating mode.

It is important to note that all of the features and advantages of the circuits900and1000can also, if desired, be incorporated into the multiplexing circuit700of FIG.7. The features of test circuit800can also be incorporated into the multiplexing circuit of FIG.6.

Further, the circuits900and1000of FIG.9andFIG. 10could be expanded to use numbers of identical transistors in parallel with one another for the circuit's device under test transistor, and for the circuit's dummy transistor. For example, device910in circuit900could be replaced with a number of devices identical to device910connected to one another in an electrically parallel arrangement. These parallel devices would have their common gate connected to node105. The devices would share a common drain probe pad, a common source probe pad, and a common substrate probe pad the common substrate probe pad is normal for most test structures. The advantage of this common transistor arrangement is that it increases the amount of capacitance that each circuit is to measure and thus increases the accuracy of each measurement.

FIG. 11illustrates one example of an application of the test circuit100ofFIG. 1in which the device under test capacitance110is replaced with MOSFET transistor1110(Metal Oxide Semiconductor Field Effect Transistor) and the dummy capacitance112is replaced with MOSFET transistor1112. In this configuration, the drain and source of transistor1110are connected to node105and allow the test circuit1100to measure the sum of the drain capacitance of transistor1110, the source capacitance of transistor1110, the parasitic capacitance associated with the interconnect to the drain and source of1110and the other parasitic capacitances associated with node105. The gate of transistor1110is connected to probe pad1105. In this embodiment, the transistor is an n-channel enhancement transistor that resides in the p-doped substrate114. The drain and source of transistor1112are connected to node107and allow the test circuit1100to measure the sum of the drain capacitance of transistor1112, the source capacitance of transistor1112, the parasitic capacitance associated with the interconnect to the drain and source of1112, and the other parasitic capacitances associated with node107. The gate of transistor112is connected to probe pad1109. The transistor is also an n-channel enhancement transistor that resides in the p-doped substrate114.

Additionally, in analogy to circuit900ofFIG. 9, transistor1112in circuit1100can be removed and replaced with a copy of the interconnect from node105to the source and drain of transistor1110. Doing this creates the circuit1200shown in FIG.12. For this example, transistor1210in circuit1200is similar in type and function to transistor1110in circuit1100. Again in analogy to circuit900, circuit1200ofFIG. 12provides a way to separate the value of transistor1210's source and drain capacitance from the parasitic capacitances associated with node105and from the parasitic capacitance associated with the interconnect leading to the source and drain of transistor1210.

In analogy to the example procedures discussed in conjunction with circuits900and1000, various transistor geometries can be used in conjunction with circuits1200and1100to provide ways to determine numerous important device parameters. Being able to measure the capacitances associated with the sources and drains of these transistors (1210,1110, and1112) while simultaneously being able to apply bias voltages to the transistors' drains and sources, and to their gates allows the determination of the effects on source capacitance, drain capacitance, inversion layer to gate capacitance, and inversion layer to substrate capacitance of various modes of transistor bias. Among the possible biasing modes for the transistors of circuits1200and1100are: accumulation with the gate to source voltage well below threshold voltage and the transistor turned off; depletion with the gate to source voltage somewhat below threshold voltage and the transistor turned off but near turn on; and inversion in linear with the gate to source voltage above threshold voltage and the transistor turned on.

Also in analogy to the methods employed with circuits900and1000, multiple copies of circuits1200and1100can be used to determine numerous device parameters. Each copy would employ unique geometries of transistors to be characterized. The various transistor geometries allow the determination of device capacitances as functions of transistor widths and lengths. Moreover, characterizing numerous device sizes allows the determination of the capacitances associated with each of the various portions of a device.

For example, the gate of transistor1210is biased so that the transistor is in accumulation. Then the capacitances connected to node107and to node105are each measured. Subtracting the two capacitances yields the capacitance from the source1204and the drain1202of transistor1210to the transistor's gate1205and to the substrate114. Doing this same measurement, but with the gate of1210biased so that1210is in inversion, yields the combined capacitance of the source and drain to the gate and to the substrate along with the capacitance from the inversion layer to the gate and the inversion layer to the substrate. Doing this procedure for various sizes of transistors and comparing the results leads to the combined capacitance from the inversion layer to the gate and to the substrate. Knowing the gate to inversion layer capacitance from using the circuits900and1000as described above, allows through subtraction the determination of the capacitance between the inversion layer and the substrate.

It is important to note that the above is merely one example of how this concept can be used. The circuits1200and1100can be used in conjunction with most any type of transistor including a bipolar junction transistor by connecting the emitter and collector together and connecting them to nodes105or107, a metal-semiconductor field effect transistor (MESFET), floating gate flash EPROM memory transistors, floating gate standard EPROM memory transistors, etc.

Circuit1400of FIG.14and circuit1500ofFIG. 15function similarly to circuits900and1000. These two circuits can be used to measure the overall gate capacitance of various forms of floating gate non-volatile memory transistors. The two circuits are part of a group of circuits that can be used to characterize the various gate related capacitances of floating gate flash EPROM memory core cell transistors and floating gate EPROM memory core cell transistors. It is important to note however that because floating gate memory transistors have floating gates1403in addition to their control gates1413, floating gate transistors require special treatment. Having two electrodes such as the floating gate and the control gate and a ground plane such as the drain, source, substrate and any inversion layer requires that floating gate transistors be treated as multiple electrode capacitors, multiple meaning more than two electrodes.

FIG. 13shows the general forms of the various measurement structures that are required for correctly measuring the capacitances of and characterizing three electrode capacitors. The method illustrated inFIG. 13can be extended to multiple electrode capacitors with more than three electrodes. Specifically, the circuits1382,1383and1384are required for measurements in three electrode situations. Circuit1382shows how electrodes A1322and B1324are connected together. Their combined capacitance to electrode C1326is measured. Circuit1383shows how electrodes B1344and C1346are connected together. The capacitance from electrode A1342to the connected combination of electrode B1344and electrode C1346is measured. Circuit1384shows how electrode A1362and electrode C1366) are connected together. The capacitance from electrode B1364to the connected combination of electrode A1362and electrode C1366is measured. The measurement of these three capacitances renders information which can be used to determine the values of capacitors CAB (all the same value and labeled1308,1328,1348, and1368in1381,1382,1383, and1384), CAC(all the same value and labeled1310,1330,1350, and1370in1381,1382,1383, and1384), and CBC(all the same value and labeled1312,1332,1352, and1372in1381,1382,1383, and1384).

Measurements very similar to those employed in conjunction with the circuits900and1000are likewise conducted using circuits1600and1700. In the embodiments of circuit1600, all of the capacitances connected to node105are compared with the capacitances connected to node107. Interconnect1612is connected to node107and is a copy of the interconnect from node105to the control gate and floating gate of flash EPROM transistor1610. Subtracting the value of the total of the capacitances connected to node107from the value of the total connected to node105yields the capacitance from the control gate and floating gate of flash EPROM transistor1610to the rest of the transistor. This capacitance includes both the control gate and floating gate fringe capacitances to the transistor source, drain, and adjacent substrate regions. The capacitance also includes the capacitances from the floating gate to the channel, and to the source and drain overlap regions. As explained in the discussion of circuits900and1000, various widths and lengths of transistor1610can be measured in order to isolate the values of the capacitances associated with the various parts of the flash EPROM transistor. Similarly, circuit1700is use in much the same way that circuit1000is used. Again, various widths and lengths of transistors1710and1712can be measured in order to isolate the values of the capacitances associated with the various parts of the flash EPROM transistor.

Device sizes are varied in circuits1800and1900(FIG.18andFIG. 19, respectively) just as they are in circuits1600and1700in order to determine capacitances for the various parts of the flash EPROM transistor. In circuits1800and1900however, the floating gate of the transistors1810,1910, and1912are connected to probe pads so that they can be biased to desired voltages. Biasing is normally to ground in order to have the same potential as the substrate. The various portions of the devices in these two circuits serve the same role as the electrodes in circuit1383. The control gates act as electrode A1342in1383. The floating gates act as electrode B1344in circuit1383, while the drains, sources and substrates in1810,1912and1910serve the same role as electrode C in1383.

In a very similar sense, device sizes are varied in circuits2000and2100(FIG.20andFIG. 21, respectively) just as they are in circuits1600,1700,1800and1900in order to determine capacitances for the various parts of the flash EPROM transistor. In circuits2000and2100however, the control gate of the transistors2010,2110, and2112are connected to probe pads so that they can be biased to desired voltages (normally to ground in order to have the same potential as the substrate). The various portions of the devices in these two circuits serve the same role as the electrodes in circuit1384. The floating gates act as electrode A (1362) in1384. The control gates act as electrode B (1364) in circuit1384, while the drains, sources and substrates in2010,2112and2110serve the same role as electrode C in1384.

Once the devices in the three forms of circuits (the forms analogous to circuits1382,1383, and1384) have all been characterized, capacitances analogous to CAB, CAC, and CBCcan be calculated for each specific type of device capacitance as desired. For example, the capacitances from the floating gate and the from floating gate edges to the control gate, to the transistor source, to the transistor drain, and to the substrate regions adjacent to the transistor's channel can be determined.

It is important to note that any or all of flash EPROM core cell transistors1410,1510,1512,1610,1710,1712,1810,1910,1912,2010,2110, and2112can be replaced with multiple flash EPROM core cell transistors of the same sizes in parallel with one another. This is often done in order to increase the values of the capacitances being measured and bring about more measurement accuracy. Further, this method of making measurements on three electrode flash EPROM core cell transistors can be generalized to other types of three electrode devices.

FIG. 22illustrates two examples of the various types of MOSFET transistors that can trap charges in their gate dielectrics. Transistor2200is an example of a standard n-channel enhancement transistor with charge trapped in its gate dielectric near its drain. Trapping charge in the gate dielectric of such a standard MOSFET is almost always a very undesirable event. It is useful to be able to characterize the concentration and location of trapped charge when trapping occurs in such transistors.

In contrast, when done correctly, trapping charge is a useful thing to have happen in the gate dielectrics of NROM memory core cell transistors, device2201. The NROM memory transistor is described in U.S. Pat. No. 6,011,725; issued Jan. 4, 2000 to Boaz Eitan and titled Two Bit Non-Volatile Electrically Erasable And Programmable Semiconductor Memory Cell Utilizing Asymmetrical Charge Trapping. This particular example of the transistor uses a “sandwich” structure of silicon dioxide, silicon nitride, and silicon dioxide as its gate dielectric. Trapping charge in its gate dielectric is how such a transistor is programmed. Normally charge is trapped at the lower interface between the silicon nitride and the lower layer of silicon dioxide. Device2202is a schematic symbol used to represent the NROM memory core cell transistor2201.

For numerous reasons, it is extremely valuable to have knowledge of the concentration of trapped dielectric charge at each location with respect to the drain and source (with respect to the channel length). Knowledge of gate dielectric charge concentrations and charge locations in standard MOSFET's can help to diagnose the cause of charge trapping and aid in assessing the risks to product reliability associated with trapped dielectric charge.

Knowledge of gate dielectric charge concentrations and charge locations in NROM memory core cell transistors is extremely helpful in determining the best methods for programming, erasing, and reading the memory transistors. Charge concentration and location are also critical issues in developing and improving methods for program and erase cycling of these memory transistors.

Gate capacitance versus gate voltage characteristics of transistors can lead to information on the position and concentration of trapped dielectric charge in standard MOSFET transistors, in floating gate flash EPROM memory core cell transistors, in thick oxide field transistors, and NROM memory core cell transistors.

The example of trapped charge in the gate dielectric of an NROM memory transistor will be used to illustrate a method for profiling the concentration and location of the trapped dielectric charge. The illustrated method can also be applied to the characterization of trapped charge in the gate dielectric of a standard MOSFET transistor.

FIG. 23illustrates an example C-V characteristic for an NROM memory core cell transistor that has no trapped charge in its gate dielectric. Refer toFIG. 22for an idealized cross section2201and a schematic symbol for this transistor. A low gate to source voltage (e.g., less than zero volts) yields a portion of a C-V characteristic2302for an accumulated surface as a large density of holes is drawn to the silicon dioxide to silicon interface. Raising the gate voltage to above zero volts but keeping the gate voltage below the transistor's threshold voltage causes the transistor to go into the depletion condition. When a transistor is in depletion, the silicon at the transistor's silicon to silicon dioxide interface, the transistor's “surface”, is depleted of mobile charge carriers. As such, the gate capacitance of the transistor is reduced (C-V curve portion2303).

For gate voltages greater than the transistor's threshold voltage, the transistor's surface becomes inverted (C-V curve portions2304,2305). The curve ofFIG. 23is for a transistor with a low drain to source voltage VDS. The gate capacitance of the inverted transistor is dominated by the capacitance from the gate of the transistor to the inversion layer at the surface of the transistor. Here, the term surface means the silicon at the interface between the transistor's gate dielectric the silicon just beneath the gate dielectric. This is the region in which the transistor's inversion layer is formed.

FIG. 24shows the effects (exaggerated and not to scale) of increasing the transistor's drain to source voltage and saturating the transistor. The saturation of the transistor is increased by raising its drain to source voltage successively further beyond the drain to source voltage that brings about the onset of saturation. The depletion region that forms between the drain end of the transistor's inversion layer and the drain of the transistor increases in width (in the drain to source direction). (This depletion region is often referred to as the saturation “pinch off region.”) This increase in the depletion region width decreases the length of the channel inversion layer. The capacitance from the gate of the transistor to this pinch off depletion region is less per unit area than the capacitance from the gate to the inversion layer per unit area. Thus as the drain voltage is increased to bias the transistor further into saturation, the gate capacitance of the device is reduced. Note that if the gate voltage of the transistor increases the transistor becomes less saturated. This is because increasing the gate voltage of a transistor raises the drain voltage that is needed to bring on the onset of saturation. FIG.24's curves2402,2403,2404,2405, and2406are for successively greater amounts of drain voltage and wider saturation pinch off depletion regions.

FIG. 25shows the effects of trapped gate dielectric charge on the C-V characteristics. A shift in a curve's position to a higher gate voltage (from point2502to point2504, for example) indicates an increase in threshold voltage in a portion of the channel. Trapped gate dielectric charge causes increases in transistor threshold voltage, corresponding to movement toward higher gate voltages of portions of the C-V curves. A threshold voltage shift for part of the transistor channel is shown as the shift from FIG.25's2502curve to the figure's2504curve (shown not to scale). This shift is caused by trapped charge in the transistor's gate dielectric. The magnitude of the shift indicates the concentration of the trapped charge.

The vertical fraction of the curve that shifted to the greater threshold voltage indicates the area of the transistor's channel that is charged. The vertical fraction in this example is the difference in capacitance levels2505and2503divided by the difference in capacitance levels2505and2507. Capacitance level2507is the gate capacitance of the transistor with the transistor biased in depletion. The area of the transistor channel that is charged is proportional to the above described vertical fraction. Again, the concentration of the charge in this area is commensurate with a shift in threshold voltage from2502to2504.

This idealized curve would indicate that roughly one third of the area of the transistor's gate dielectric is uniformly charged to a concentration that would bring about a threshold voltage shift from curve2502to curve2504. In practice, the trapped charge concentration usually is not normally distributed uniformly over the area of the transistor gate dielectric. As such, the resultant shift in the C-V curves is more spread out over the range of threshold voltage shift. In other words, the shape of the curve2503will have more of a gradual shift. Some portions of the gate area will have small threshold shifts resulting in a gradual shifting of curve2502toward higher gate voltages, although (perhaps not as abrupt as the sudden shift seen in curve2503.

FIG. 26shows C-V curves resulting from trapped charge and from applied drain voltages that cause the transistor to saturate for some gate voltages. The curves ofFIG. 26are less idealized than the curves in FIG.24and FIG.25. They are more exemplary of the curves seen in practice (the curves are still somewhat exaggerated). Example curve2602is for an uncharged gate dielectric with no voltage applied from drain to source. Example curve2603is for trapped charge of varying concentration somewhere in the gate dielectric. Example curve2604shows the effects of applying a large drain to source voltage to the device in the case when the trapped charge indicated by curve2603is near the drain of the transistor. In this situation, the elevated drain to source voltage would tend to deplete (through its drain voltage induced saturation pinch off depletion region) the portion of the transistor channel that is also already depleted by the trapped charge. In this situation, the saturation pinch off depletion region has less influence in depleting the transistor channel region than it would normally have. On the other hand, curve2605is an example of having charge in the gate dielectric in a region that is away from the drain of the transistor and of having a large drain voltage drive the transistor into saturation. Both the charge induced depletion region and the drain voltage induced pinch off region reduce the capacitance of the gate. To a major extent, the two effects add.

Commonly, a very effective alternate method can be used to determine NROM memory transistor charge density and charge location. As with the first method outlined above, this method is based upon analysis of capacitance versus voltage curves. Often, the charge in the gate dielectric above the channel of an NROM transistor extends across the entire transistor channel in a direction perpendicular to the flow of current. At low gate voltages, this sort of charge distribution has the effect of isolating the drain of the transistor from the source of the transistor. This type of charge distribution is referred to as a “full channel blocking charge distribution.”

Consider the situation with drain and source voltages set equal to one another and a gate voltage that is just large enough to invert the portions of the channel that do not have charge in the gate dielectric above them. The gate voltage in this situation is low enough that the channel regions beneath the dielectric charge are not inverted but instead are depleted. The capacitance voltage characteristics (C-V curve) measured under this bias condition gives a strong indication of the total area of the channel that has charge in the dielectric above it. The C-V curves also indicate the concentration of the charge. The area that is charged is determined, as shown inFIG. 25, from the vertical shift in C-V characteristics from the curve labeled2503to the flat portion of the curve labeled2502(the highest portion of2502). The lateral shift from the curve labeled2502to the portion of the curve labeled2504indicates charge concentration. As noted previously, the curve labeled2503and2504is idealized. An actual curve would not have capacitances as constant in the region labeled2503and would not have such an abrupt change in capacitance in the region labeled2504. These curves have been simplified for the sake of illustration. Nonetheless, the described analysis could be applied to more complex actual curves in order to obtain charged area and charge concentration.

The theory needed for understanding how to locate the dielectric charge in the above example of a full-channel blocking charge distribution is akin to understanding the theory that explains saturation mode operation in MOSFET's. Raising the source to bulk voltage of a MOSFET transistor raises the transistor's threshold voltage. This is a fairly strong effect in NROM memory transistors due to the n-channel transistors' relatively high concentration of p-type channel dopant. Moreover, raising the voltage of any portion of a transistor's inversion layer raises the threshold voltage for that portion of the transistor's channel. Raising the drain voltage of an inverted transistor raises the voltage on the drain end of the transistor's inversion layer. This in turn increases the gate to channel threshold voltage local to the drain end of the inversion layer. Moreover, raising the voltage on the inversion layer near the drain causes the voltage from the gate of the transistor to the drain end of the inversion layer to become smaller. With enough drain voltage, this combination of increased local threshold voltage and reduced voltage from the gate to the local inversion layer can prohibit the existence of an inversion layer at the drain end of the channel. Thus a saturation pinch-off region forms near the drain end of the MOSFET channel. The above outlines the standard theory for MOSFET saturation.

Understanding the case of an NROM transistor with a full channel blocking charge distribution draws upon theory similar to that outlined above for MOSFET transistors in saturation. Consider the case of an NROM transistor having channel blocking charge fully crossing the center of the transistor's channel. The example further assumes that the charge covers 20 percent of the transistor's channel length (and thus 20 percent of the channel area). This leaves a region of channel near the source of the transistor having an uncharged gate dielectric and a similar region near the drain. Each of these uncharged regions would have areas equal to 40 percent of the channel area

As explained above, holding the drain and the source of the transistor at the same voltage will yield a C-V curve indicating that 20 percent of the channel is charged. The capacitance curve will indicate that the transistor is fully depleted for gate voltages just below the threshold voltage of the uncharged regions. As the gate voltage is increased, the two uncharged regions (each having 40 percent of the channel area) will invert and the C-V curve will attain 80 percent of its fully inverted capacitance level. As the gate voltage increases further, the remaining 20 percent of the channel will invert and the C-V curve will reach its full inversion capacitance level. Of course, the various portions of this remaining 20 percent of the channel will their own threshold voltage. The level of each area's threshold is dependent upon the dielectric charge concentration overlying the area.

Under some bias conditions, raising the drain voltage of the full-channel charge blocked NROM transistor can isolate large portions of the transistor channel and can prevent these regions from being inverted. These portions of the channel would invert if not for the presence of the charge fully blocking the channel of the transistor. Consider a gate voltage that is just high enough to invert the uncharged portions of the transistor channel (80 percent of the channel area) but which is not high enough to invert the charged portion of the transistor channel (the 20 percent of the channel midway between source and drain). Under this condition, the dielectric charge in the middle of the channel effectively isolates the uncharged portions of the channel from one another. Again, these uncharged portions of the channel are the 40 percent of the channel near the drain and the 40 percent of the channel near the source. The inversion layer of the portion of the channel near the source takes on the same voltage as the source. The inversion layer of the portion of the channel near the drain takes on the same voltage as the drain. These two inversion layers are isolated from one another. The drain actually acts as a “pseudo source” for inversion layer electrons. As such, this inverted region near the drain is termed the “drain-sourced inversion layer.”

Under this condition, raising the voltage on the drain of the transistor increases the voltage of the drain-sourced inversion layer. With enough increase in drain voltage, the voltage from the gate to the drain-sourced inversion layer is be too small to support an inversion layer. This portion of the channel is isolated for two reasons. First, the region cannot gain electrons from the source due to the full channel blocking charge. Second, the region cannot gain electrons from the drain. This is because the drain is at a higher voltage than the highest voltage that could exist in such a transistor's inversion layer. Simply, the transistor's gate voltage is too low to support inversion with such a high inversion layer voltage (such a high drain voltage). There would be too little voltage difference from the gate voltage to the inversion layer voltage. Note again that the transistor's drain is acting as the source for this isolated portion of the channel.

This is very similar in concept to the theory for saturation pinch-off in a normal uncharged transistor. Instead of gaining electrons from the drain, any drain-sourced inversion layer would lose its electrons to the higher voltage drain. This causes the 40 percent of the channel nearest to the drain to become depleted.

With the above in mind, it is fairly easy to determine how much channel area without overlying dielectric charge exists between the drain and the channel blocking charge. Two C-V curves are required. One C-V curve would be measured with the drain voltage low enough to allow inversion in the drain-sourced portion of the channel. A second C-V curve would be measured with the drain voltage raised enough to cause the drain-sourced channel region to deplete. The difference between the two C-V curves gives a clear indication of how much of the channel lies between the drain and the full channel blocking charge. Thus the method can determine the distance between the channel blocking charge and the drain.

Similarly, the roles of the source and drain can be reversed so that the distance from the source to the channel blocking charge can be determined. Knowing these two distances and knowing the amount of channel area “covered” by the dielectric charge yields a full understanding of the location of the charge with respect to the transistor's drain and source.

FIG. 27is a schematic diagram of an exemplary circuit,2700, for measuring the capacitances needed for creating capacitance versus voltage characteristics similar to those shown inFIG. 23,FIG. 24,FIG. 25, and FIG.26. In the example ofFIG. 27, the circuit is configured for measuring the capacitance versus gate voltage characteristics of NROM memory core cell transistors. Among other measurements and analysis that this circuit enables, the circuit provides for the determination of the location and concentration of trapped charges in the gate dielectrics of MOSFET transistors. Here, location means position with respect to the channel length (with respect to the source and the drain). The methods for determining charge location and concentration from capacitance and voltage characteristics were explained in the discussions ofFIG. 23,FIG. 24,FIG. 25, and FIG.26.

The gates2703of multiple parallel NROM memory core cell transistors2202are connected via interconnect network2707to node105of a test circuit similar to test circuit100discussed in conjunction with FIG.1. The gate capacitances associated with these transistors form the device under test capacitances of this test circuit. The drains of the NROM transistors are connected in common to probe pad and node2702. The sources of the NROM transistors are connected in common to probe pad and node2704.

As shown in this example, these transistors can be fabricated in the doped substrate114of a semiconductor wafer. Alternatively, they can be fabricated in a doped well resident in the substrate of a semiconductor wafer. The transistors in this example happen to be n-channel NROM core cell memory transistors. Any type of transistor having an insulating gate could just as well be analyzed by a form of this circuit.

An interconnect network2717identical to network2707is connected to test circuit node107and forms the dummy capacitance of the test circuit. All of the capacitances associated with node105and107are measured in accordance with the method described in the discussion of FIG.1. The gate capacitances of gates2703are the result of subtracting the node107capacitances from the node105capacitances at the various operating conditions.

Test circuit2700provides for the programming and erasure of NROM memory core cell transistors2202. NROM memory transistor programming, erasure and reading occur via the application of appropriate voltages to drain connection2702, source connection2704, and gate node105,2707, and2703(105,2707, and2703are all portions of the same node). Similar to methods outlined herein for other test circuits, a DC voltage can be applied to node105merely by taking Clock Up node122negative in voltage in order to turn on transistor102, taking Clock Down node124to a large positive voltage in order to turn off transistor104, and then applying to node116the gate voltage that is desired for gate nodes2703.

Circuit2700employs multiple parallel connected copies of NROM memory core cell transistor2202in order to increase the overall capacitance to be measured. Measuring a large number of transistor gate capacitances enables more precise capacitance measurements. Under ideal conditions, a single transistor2202could be used in the circuit. Although this example describes the charge profiling method in conjunction with NROM cells, the method can be applied in the same fashion to the analysis of standard MOSFET transistors.

Test circuit2800ofFIG. 28is an example of another embodiment of a test circuit for measuring the gate capacitances of NROM memory core cell transistors. Alternatively, the circuit can be used to measure the gate capacitances of other types of transistors.

Test circuit2800improves on test circuit2700in that2800provides for the programming, and reading of individual NROM memory core cell transistors. Transistors can be programmed and read individually as is normally done in some phases of these types of transistors' operation in products. It is very desirable to have a method for determining the gate dielectric charge distributions in transistors that result from many cycles of transistor program and erase cycling. Charge distribution refers here to the location and concentration of charge in the gate dielectric. Test circuit2800provides an improved means for determining the concentration and location of trapped charge in the gate dielectric of NROM memory transistors.

Test circuit2800contains an array of NROM memory core cell transistors arranged in the same fashion that transistors in a product array would be arranged in. Having an array of transistors is advantageous in that the transistors of interest are subjected to the same processing anomalies to which the transistors in a product memory are subjected, such as transistor to transistor proximity effects, plasma etcher loading, etc. Moreover, simultaneously measuring the gate capacitance of many parallel transistors increases the overall capacitance being measured and hence increases capacitance measurement accuracy.

Transistors2807,2821and the other transistors in the same row of transistors as transistors2807and2821are the devices whose gate capacitances can be measured in this example circuit (the transistors of interest). The gates of all of the transistors on this array row are connected to interconnect2820and are eventually connected to node105of a copy of test circuit100. The common gate connecting all of the transistors in the row containing transistors2807and2821is normally referred to as the “word line” for that row of transistors. The term “word line” normally refers to the portion of this node that is transiting the array of memory transistors itself. The other word lines in the array of circuit2800are connected to a common probe pad and to node2812. The circuit's bit-lines2813,2814,2815,2816,2817,28182819are the lines connecting the drains and sources of the transistors in the array. In the preferred embodiment, the word lines are poly crystalline silicon and the bit lines are n-doped regions in the semiconductor substrate.

In this example embodiment, each bit line can act as the source line for all of the transistors connected to it and, in other operating modes, as the drain line for all of the transistors connected to it. In this example, the NROM memory core cell transistors are bi-directional devices. Each NROM transistor is reversible with its two ends (drain and source diffusions) acting as drain and source in one mode and then acting respectively as source and drain in another. Whether a bit line is acting as a drain or as a source at a particular moment merely depends upon the bias condition of the array's various bit lines at that time. If a first bit line is biased to a relatively high positive voltage and a second adjacent bit line is biased to a lower voltage then the first bit line acts as a drain and while the second acts as a source. In this example, bit lines are numbered from left to right. Bit lines2813,2815,2816, and2818are odd bit lines and connect to the odd bit line select circuitry2827. Bit lines2814,2817, and2819are even bit lines and connect to the even bit line select circuitry2826. Note that although bit lines2815and2816are shown adjacent to one another in the figure, they are actually separated by perhaps a very large number of even and odd bit lines that were omitted from the figure for the sake of brevity. This circuit often contains thousands of bit lines with thousands of NROM transistors having their gates connected to the word line that also connects to transistors2807and2821.

The even bit line select circuitry,2826, serves to electrically connect a single selected even bit line to the even selected bit line probe pad2808. The select circuitry also connects all lower numbered even bit lines to the lower numbered even bit line probe pad2837and all higher numbered even bit lines to the higher numbered even bit line probe pad2809. Similarly, the odd bit line select circuitry,2827, serves to electrically connect a single selected odd bit line to the odd selected bit line probe pad2824. The select circuitry also connects all lower numbered odd bit lines to the lower numbered odd bit line probe pad2823and all higher numbered odd bit lines to the higher numbered odd bit line probe pad2825. The even selected bit line and the odd selected bit line are adjacent to one another in this example. In other embodiments, select circuitry2826and2827could be constructed such that all of the bit lines could be selected and connected in different fashions as desired.

In this embodiment, the bit line select circuits,2826and2827, accept signals from the address lines coming from address bus2810and from those signals determine the even bit line and the odd bit line to be selected. Address probe pads2811are used for connecting the address bus nodes to the automated parametric test system normally used for reading, programming, erasing, and program and erase cycling NROM transistor test arrays. Lower numbered even bit line probe pad2837, even selected bit line probe pad2808, higher numbered even bit line probe pad2809, lower numbered odd bit line probe pad2823, odd selected bit line probe pad2824, and higher numbered odd bit line probe pad2825are also used for connecting their respective nodes to appropriate nodes in the parametric test system. These bit line probe pads are used for applying appropriate voltages and measuring bit line currents and voltages. Unselected word line probe pad2812is used for connecting the parametric test system node which will be used to apply voltages to the other (unselected) word lines in the test circuit memory transistor array.

The bit line select circuits2826and2827can be formed from the high voltage and negative voltage transistors that are parts of typical non-volatile memory technologies. The construction of the select circuits is very similar to the construction of the circuits that are used as “y decoders” in memory products. Decoding addresses, selecting bit-lines and electrically connecting bit lines and groups of bit lines to nodes used for biasing those bit lines is a very common practice in memory technologies. As previously mentioned, circuit2800uses a copy of test circuit100and has circuit100connected to interconnect2820and the selected word line.

As with other previously described test circuits (for example900,1400,1600,1800and2000), a copy,2822, of interconnect2820is connected to test circuit node107and acts as the dummy capacitance. Measuring the capacitances associated with node107results in the dummy capacitance. Measuring the capacitances associated with node105results in the device under test capacitance. Subtracting the dummy capacitance from the device under test capacitance results in the capacitance from the word line and the gates of the transistors on the array row containing transistors2807and2821to the rest of the structure. These capacitances include the gate to channel, gate to source, and gate to drain capacitances of the transistors of interest. The capacitances also include the word line to bit line capacitances and the capacitances between the word line and the adjacent word lines. Commonly, the parametric test system used for biasing circuit2800's address probe pads also provides the signals used to drive circuit2800's copy of circuit100. The parametric test system also measures the currents into the two VHIGH nodes of the copy of circuit100(116, and120).

Generally, all of the NROM transistors in a single test circuit array are of the same size. Having a number of test circuits2800, with each having its own unique size of transistors, can allow for the isolation of the capacitances of specific portions of the transistors. This is similar in nature to the methods employed in conjunction with the test circuits of FIG.9and FIG.10.

Test circuit2800provides a means for developing NROM memory core cell transistor capacitance versus voltage characteristics similar to those inFIGS. 23,24,25, and26. Thus is provides a means for characterizing the location and concentration of charge trapped in NROM transistor gate dielectrics. It also allows the NROM transistors of interest to be individually programmed, erased and read.

In another embodiment, the word line of interest is merely chosen from among the word lines of an existing test chip memory array. These memory test arrays are a common feature of memory technology development test chips and commonly contain, for example, 4,194,304 NROM transistors (4 Mega-cells). In this situation, interconnect2827would connect test circuit100's node105to an existing test array word line. Interconnect2822would be connected to test circuit node107and would be a copy of the interconnect2820connecting node105with the test array word line to be monitored. In short, the lower portion of the circuit inFIG. 28would be replaced with the circuitry in the existing test chip memory array. In this embodiment, one of the test chip memory array's word lines would be dedicated to the measurement of word line capacitance and the measurement of NROM gate capacitance, and to the characterization of trapped dielectric charge.

FIG. 29,FIG. 30, andFIG. 31illustrate exemplary circuits2900,3000, and3100which are used in conjunction with one another for determining the various electrode to electrode capacitances and the electrode to underlying ground plane capacitances of an exemplary three electrode capacitive system. In this example, two of the three electrodes are metal interconnect lines on two different metal layers of a semiconductor process. The third electrode is the semiconductor substrate. In other embodiments, a conducting plate connected to a probe pad could be substituted for the third electrode (substituted for the substrate). Secondly, although circuits2900,3000,3100in this example measure the capacitances associated with metal lines on two separate layers, the method can also be applied to conductive lines of materials other than metal. Further, the method can be applied to lines formed in separate layers or to lines formed in the same layer.

In a similar fashion to the general circuits described inFIG. 13, circuits2900,3000, and3100are used in determining the interelectrode capacitances of a line to line and line to ground plane (substrate in this example) three electrode capacitance system. Circuit2900takes the role of circuit1382inFIG. 13while circuits3000and3100take the roles of circuits1383and1384.

Circuit2900ofFIG. 29employs a first copy,2999, and a second copy,2922, of the circuit100for measuring device parameters. This first copy has its nodes105and107connected, respectively, to nodes2902and2912of the device under test capacitance and the dummy capacitance of circuit2900. Circuit2900has first device under test metal lines2904and second device under test metal lines2906.

For this example, lines2904and2906are formed on two separate metal layers of the semiconductor process. Lines2904are formed in a layer that is further from the substrate than the layer in which lines2906are formed.

The circuit also has first dummy device metal lines2914and second dummy device metal lines2916. For this example, lines2914and2916are also formed on two separate metal layers of the semiconductor process. Lines2914are formed in a layer that is further from the substrate than the layer that lines2916are formed in. Lines2904and2914are formed in the same layer and lines2906and2916are formed in the same layer. Lines2914and lines2904have the same widths and same spacings. Lines2914are shorter than lines2904by an amount LDUT. Lines2916and lines2906also have the same widths as one another and the same spacings as one another. Lines2916are also shorter than lines2906by the amount LDUT. As shown inFIG. 2900, lines2904run parallel to lines2906and are interdigitated (interleaved) between lines2906. Lines2904and2906are spaced evenly so that the spaces between individual lines are all the same as one another. Lines2914also run parallel to lines2916and are also interdigitated (interleaved) between lines2916. Lines2914and2916are also spaced evenly so that the spaces between individual lines are all the same as one another.

The connections to lines2914are either identical to the connections to lines2904or else are mirror images of the connections to lines2904. Also, the connections to lines2916are either identical to the connections to lines2906or else are mirror images of the connections to lines2906. Similar correspondences between the device under test structures and the dummy device structures apply to all of the interconnects that link various lines of each group lines to each other. For example, the interconnects that link the individual lines of2914to one another are mirror images of the interconnects that link the individual lines of2904to one another. Also, the interconnects that link the individual lines of2916to one another are mirror images of the interconnects that link the individual lines of2906to one another.

In the case of circuit2900, lines2904are connected to lines2906by interconnect2933and lines2914are connected to lines2916by interconnect2943. Interconnects2933and2943are either identical to one another or else are mirror images of one another. Having lines2906connected to lines2904and having lines2916connected to lines2906makes circuit2900be a specific form of the general circuit1382for measuring the capacitances of and characterizing three electrode capacitors. The device under test capacitors and the dummy capacitors in circuits3000and3100do not have connections2933and2943. Instead,3000's and3100's device under test capacitors and dummy capacitors are configured and connected in ways to make circuits3000and3100be specific forms of the general circuits1383and1384for measuring the capacitances of and characterizing three electrode capacitors.

As described herein in the above discussions of circuit100, the first copy,2999, of the test circuit100is used to measure the value of the sum of the capacitances connected to node105(including the parasitic capacitance associated with node105, the capacitances associated with interconnect2902, and the capacitances associated with device under test metal lines2904and2906). Node105of the first copy of circuit100connects to device under test metal lines2904,2906and connection2933via interconnect2902.

The first copy,2999, of the test circuit100is also used to measure the value of the sum of the capacitances connected to node107(including the parasitic capacitance associated with node107, the capacitances associated with interconnect2912, and the capacitances associated with dummy device metal lines2914and2916). Node107of the first copy of circuit100connects to dummy device metal lines2914,2916and connection2943via interconnect2912.

The circuit2900's second copy,2922, of the circuit100is used to develop time varying electric fields in portions of the device under test capacitor and the dummy device capacitor of circuit2900. All of the voltage signals applied to circuit2922(the second copy of100in the lower part ofFIG. 29) are identical in timing and voltage levels to those applied to the various input nodes of2900's first copy of100. In practice,2922's nodes122,124and118are connected to their counterparts in2900's first copy of circuit100. When2900's first copy,2999, of circuit100is being used to measure the capacitances connected to node105, a separate power supply is used to apply the same voltage to2922's node2924as the voltage that is being applied to node116of2900's first copy,2999, of circuit100. In this way, at each moment in time, electric field continuation lines2908and2910have the same voltages on them as do the lines in2904and2906.

When2900's first copy,2999, of circuit100is being used to measure the capacitances connected to node107,2922′ node2924is also biased. Circuit130of2922is used for both the device under test capacitance measurements and for the dummy device capacitance measurements. Circuit132in2922is not used for field continuation purposes and can be used, as desired, for the measurement of other capacitances.

Line2908is formed from the same material and on the same layer as lines2906. It has the same line width as lines2906and has the same line spacing from itself to lines2904as lines2906have from lines2904. Line2910is formed from the same material and on the same layer as lines2904. It has the same line width as lines2904and has the same line spacing from itself to lines2906as lines2904have from lines2906.

Lines2908,2910and the voltages applied to them are needed in order to make the strengths and distributions of the electric fields at locations between lines2904and2908and between lines2906and2910be the same as the strengths and distributions at similar locations between the various lines2906and2904. Lines2908and2910continue the periodic distribution (in the y-axis or up and down the page direction with respect to the orientation ofFIG. 29) of the electric fields generated by the voltages on lines2904and2906to beyond the edges of2904and2906. In this way, the structure formed by2904and2906has the same capacitances (or very nearly the same capacitances) per line and per line pair as would a similar structure with an infinite number of interdigitated lines (alternating between lines as in2904and2906). Being able to accurately characterize structures that have periodic electric fields and periodic capacitances of this nature is important because the resultant capacitances are often used to “calibrate” the inputs to electric field simulation programs. These field simulation programs normally assume “periodic boundary conditions”, boundary conditions that render the results of the simulations valid for structures that repeat to infinity in either one or two dimensions. The structures in2900are designed to characterize the capacitances of portions of structures that would repeat to infinity.

Lines2918and2920adjacent to lines2914and2916provide the same sort of field continuation for lines2914and lines2916as lines2908and2910do for lines2904and lines2906.

The region delineated by the rectangle2909encloses circuit2900's device under test. If the structures inside of rectangle2909were removed and the rectangle were compressed laterally, the result would look like a mirror image of circuit2900's dummy device. Rectangle2909would compress to look like line2919in the dummy capacitance structure.

The sum of the capacitances connected to circuit2999's node107are subtracted from the sum of the capacitances connected to circuit2999's node105. This yields the capacitance from the portions of lines2904and2906inside of rectangle2909to the portion of the substrate contained inside the rectangle. It is important to note that this capacitance is that which would result from a portion of a capacitor that would be infinite in expanse in both the “x direction” (left and right on the page; and the “y direction” (up and down on the page). In the example of circuit2900, the portion would consist of three lines similar to2904and three lines similar to lines2906. The length of these lines is the same as the width in the “y direction” (left and right on the page) of the rectangle2909. This length is the same as LDUT, the difference in lengths of the device under test and dummy device metal lines.

Circuit2900's device under test layout and dummy device layout eliminate from the three dimensional capacitance calculations and simulations the need for considering the fringe fields that would otherwise be associated with the ends of lines. The circuit's field continuation structures also largely eliminate the inaccuracies associated with missing nearest neighbor lines in the regions adjacent to the lines whose capacitances are being measured.

It should be further noted that other embodiments of this circuit can eliminate the effects of missing second and third nearest neighbor lines by also including those lines in the device under test and the dummy device. These second and third nearest neighbor lines would (in the case of circuit2900) be connected in common with field continuation lines2908,2910,2918and2920.

As noted above, circuit3000inFIG. 30is used in conjunction with circuit2900in FIG.29and circuit3100inFIG. 31in order to determine the various electrode to electrode capacitances and the electrode to underlying ground plane capacitances of an exemplary three electrode capacitive system. Circuit3000is to circuit2900as circuit1383is to circuit1382.FIG. 30continues FIG.29's example of two types of metal lines over a grounded substrate. Circuit3000has first device under test metal lines3004which are on the same layer, and have the same widths and spacings as circuit2900's first device under test metal lines2904. Circuit3000has second device under test metal lines3006which are on the same layer and have the same widths and spacings as circuit2900's first device under test metal lines2906.

The circuit also has first dummy device metal lines3014which are on the same layer and have the same widths and spacings as circuit2900's first dummy device metal lines2914. Circuit30also has second dummy device metal lines3016which are on the same layer, and have the same widths and spacings as circuit2900's second dummy device metal lines2916. As with circuit2900's lines, circuit3000's dummy device metal lines3014are shorter than the circuit's device under test metal lines3004by an amount LDUT. Circuit3000's dummy device metal lines3016are also shorter than the circuit's device under test metal lines3006by an amount LDUT.

Circuit3000is very similar in structure and operation to circuit2900. Circuit3000only differs from circuit2900in the way that circuit3000's device under test structure and dummy device structure are configured. Circuit3000's line structures3004,3006,3014,3016, and field continuation structures3008,3010,3018, and3020are of the same materials, on the same layers, and are of the same dimensions and spacings as their circuit2900counterparts,2904,2906,2914,2916,2908,2910,2918, and2920, respectively.

Circuit3000is used to measure the capacitance from lines such as3004to lines such as3006and to the substrate when the lines3006and the substrate are at the same potential (the normal case). Lines3004are connected to node105of3000's first copy,3099, of circuit100. Similarly, lines3014are connected to node107of3000's first copy,3099, of circuit100. Lines3006and lines3016are both connected to a probe pad3033for biasing (usually to the same potential as the substrate). As in2900, lines3010and3020are connected to the field continuation circuit3022. These two lines are analogous to lines2910and2920. Lines3008and3018also provide field continuation and are connected to probe pad3033. Lines3008and3018are biased to the same potential as lines3006and lines3016because lines3008and3018act toward lines3004and3014in the same fashions as lines3006and lines3016do.

The voltages on lines3004and3014oscillate when the capacitances of these lines are being measured. To continue the periodic electric field patterns caused by lines3004and3014, field continuation generation circuit3022causes the voltages on lines3010and3020to also oscillate with the same voltage signals as those on lines3004and3014. The voltages on lines3006and3016are held constant (normally to the same ground potential as that on the substrate). In order to continue the periodic electric field pattern caused by the voltages on lines3006and3016being held constant, the voltages on field continuation lines3008and3018are also held constant (with the same voltages as the voltages on lines3006and3016). In short, lines3008,3010,3018and3020continue the electric field patterns set up by lines3004,3006,3014, and3016during the respective times when measurements are being performed on lines3004and lines3014.

In analogy to rectangle2909inFIG. 29, rectangle3009inFIG. 30encloses the device whose capacitance is being measured in circuit3000. Circuit3000provides a means for measuring the capacitance from the portions of lines3004inside of rectangle3009to the structure comprising the portions of lines3006in rectangle3009, the portions of line3008in rectangle3009, and the portion of the substrate in rectangle3009. As in circuit2900, the lengths of the portions of the lines3004and3006which contribute to the measured capacitance are the same as LDUT, the difference in lengths of the device under test and dummy device metal lines.

As with the capacitance measured by circuit2900, this capacitance is the capacitance that would result from a portion of a capacitor that would be infinite in expanse in both the “x direction” (left and right on the page) and the “y direction” (up and down the page). As with circuit2900's capacitances, circuit3000's device under test layout and dummy device layout eliminate from the three dimensional capacitance calculations and simulations, the need for considering the fringe fields that would otherwise be associated with the ends of lines. The circuit's field continuation structures also largely eliminate the inaccuracies associated with missing nearest neighbor lines in the regions adjacent to the lines whose capacitances are being measured.

It should be further noted that other embodiments of this circuit can also eliminate the effects of missing second and third nearest neighbor lines by including those lines in the device under test and the dummy device. Among these added second to nearest neighbor and third to nearest neighbor field continuation lines, lines similar to lines3008and3018(of the same material on the same layer, with the same dimensions and spacings) would be connected in common with lines3008and3018. Added second to nearest neighbor and third to nearest neighbor field continuation lines similar to3010and3020would be connected in common with lines3010and3020.

Circuit3000serves the same role as circuit1383with the portion of lines3004in rectangle3009serving the same role as electrode1342(“Electrode A”) in circuit1383.

As noted above, circuit3100inFIG. 31is used in conjunction with circuit2900in FIG.29and circuit3000inFIG. 30in order to determine the various electrode to electrode capacitances and the electrode to underlying ground plane capacitances of an exemplary three electrode capacitive system. Circuit3100is to circuits2900and3000as circuit1384is to circuits1382and1383.FIG. 31continues FIG.29's example of two types of metal lines over a grounded substrate. Circuit3100has first device under test metal lines3104which are on the same layer and have the same widths and spacings as circuit2900's first device under test metal lines2904. Circuit3100has second device under test metal lines3106which are on the same layer and have the same widths and spacings as circuit2900's first device under test metal lines2906.

The circuit also has first dummy device metal lines3114which are on the same layer and have the same widths and spacings as circuit2900's first dummy device metal lines2914. Circuit31also has second dummy device metal lines3116which are on the same layer and have the same widths and spacings as circuit2900's second dummy device metal lines2916. As with circuit2900's lines, circuit3100's dummy device metal lines3114are shorter than the circuit's device under test metal lines3104by an amount LDUT. Circuit3100's dummy device metal lines3116are also shorter than the circuit's device under test metal lines3106by an amount LDUT.

Circuit3100is very similar in structure and operation to circuit2900. Circuit3100only differs from circuit2900in the way that circuit3100's device under test structure and dummy device structure are configured. Circuit3100's line structures3104,3106,3114,3116, and field continuation structures3108,3110,3118, and3120are of the same materials, on the same layers, and are of the same dimensions and spacings as their circuit2900counterparts,2904,2906,2914,2916,2910,2908,2920, and2918, respectively.

Very similar to circuits2900and3000, circuit3100uses device under test capacitance and dummy device capacitance cancellations to provide a means for measuring interconnect line capacitances. In particular, circuit3100provides a means for measuring the capacitance from the portions of lines3106inside of rectangle3109to the structure comprising the portions of lines3104in rectangle3109, the portions of line3108in rectangle3109, and the portion of the substrate in rectangle3109. As with the capacitance measured by circuit2900, this capacitance is the capacitance that would result from a portion of a capacitor that would be infinite in expanse in both the “x direction” (left and right on the page) and the “y direction” (up and down the page). As with circuit2900's capacitances, circuit3100's device under test layout and dummy device layout eliminate from the three dimensional capacitance calculations and simulations the need for considering the fringe fields that would otherwise be associated with the ends of lines. The circuit field continuation structures also largely eliminate the inaccuracies associated with the missing nearest neighbor lines in the regions adjacent to the lines whose capacitances are being measured.

As with circuits2900and3000, it should be further noted that other embodiments of this circuit can also eliminate the effects of missing second and third nearest neighbor lines by including those lines in the device under test and the dummy device. Among these added second to nearest neighbor and third to nearest neighbor field continuation lines, lines similar to line3108and3118(of the same material on the same layer, with the same dimensions and spacings) would be connected in common with lines3108and3118. Added second to nearest neighbor and third to nearest neighbor field continuation lines similar to3110and3120would be connected in common with lines3110and3120.

Circuit3100serves the same role as circuit1384with the portion of lines3106in rectangle3109serving the same role as electrode1364(“Electrode B”) in circuit1384.

With circuits2900,3000and3100acting in concert with one another, the various interelectrode capacitances (analogous to those shown inFIG. 13) from the first type of interconnect line to the second type of interconnect line, from the first type of interconnect line to the substrate, and from the second type of interconnect line to the substrate can be measured.

It is important to note that capacitance circuits for determining the capacitances of non-periodic structures can also be created from reductions of circuits2900,3000, and3100. A simple example is that of having a single line of a first type of interconnect run parallel for a distance with a single line of a second type of interconnect. The first interconnect would be substituted for one of the lines of2904,3004and3104in circuits2900,3000,3100while the second interconnect would be substituted for one of the adjacent lines of2906,3006and3106. Analogous substitutions would be made for the dummy devices' lines2914,3014,3114,2916,3016, and3116. In all cases the lengths of the dummy device interconnect lines would be shorter than the device under test lines by an amount LDUT. The portions of the dummy device lines running parallel to one another would be shorter than the parallel portions of the devices under test's lines by an amount LDUT. All electric field continuation structures would be removed. The three resulting circuits would be suitable for measuring the capacitances from line to line and the capacitances from each line to the substrate or ground plane. The capacitances would be the capacitances corresponding to a length LDUTof two isolated parallel lines of the first and second types of interconnect.

All of these circuits2900,3000,3100, and their three single lines in parallel analogies, can be copied and their line widths and line spacings modified to create circuits which can be used to determine the values of various components of the overall capacitances. Further, these circuits can be modified to consider four and more electrode capacitance systems.

The circuits3200,3300, and3400(FIG. 32,FIG. 33, andFIG. 34) are further examples of how circuits2900,3000and3100can be used. The three circuits illustrate an exemplary embodiment of circuits for determining the capacitance from a first set of interconnect lines, to a second set of interconnect lines, with the first set of lines crossing the second set of lines. The first set of interconnect lines are comprised of a first type of interconnect having first line widths and first line spacings. The second set of interconnect lines are comprised of a second type of interconnect having second line widths and second line spacings. The first and second types of interconnects are formed on separate non-intersecting layers of the semiconductor test chip.

Of the three circuits,3200,3300, and3400, circuit3200is analogous to circuits1382and2900. Circuit3300is analogous to circuits1383and3000. And circuit3400is analogous to circuits1384and3100. Circuits3200,3300, and3400are also used for determining the interelectrode capacitances of a three electrode capacitance system. In this case the three electrodes are the first set of interconnect lines, the second set of interconnect lines, and an underlying ground plane (normally the underlying semiconductor substrate).

Circuit3200considers the case in which the first and second set of interconnect lines are connected together and the capacitance from them to the ground plane is measured. Circuit3200has device under test interconnect lines3204and3206, and dummy device interconnect lines3214and3216. The circuit also has field continuation interconnect lines3208,3219,3220, and3218connected to the circuit's second copy,3222, of circuit100. Circuit3200's first copy,3299, of circuit100is shown at the top of FIG.32. Lines3219and3221in the dummy device provide capacitances from themselves to lines3216and3214. These components of the dummy device capacitances are equal to the device under test capacitances from lines3204to lines3210and from lines3206to lines3208. These dummy and device under test capacitances are designed to cancel one another.

Lines3204,3208,3219,3214, and3218running in the vertical direction (y direction) with respect toFIG. 32are composed of the first type of interconnect, while lines3206,3210,3216,3220, and3221running in the horizontal direction (x direction) with, respect toFIG. 32are composed of the first type of interconnect. Rectangle3235has a horizontal width LDUTand a vertical height HDUT.

Device under test capacitor lines3206are longer than dummy capacitor lines3216by an amount equal to LDUT. Device under test capacitor lines3204are longer than dummy capacitor lines3214by an amount equal to HDUT. As shown inFIG. 32, interconnects3202and3212will have the same capacitances to the substrate as each other. The two interconnects are equivalent to one another in their total lengths and, from a capacitance standpoint, have equivalent shapes. The two lines have the same number of corners in them and have the same lengths in their line segments.

The capacitances connected to node107of the first copy,3299, of circuit100are subtracted from the capacitances connected to node105of the first copy,3299, of circuit100. The result is the capacitance from the portions of lines3204and3206contained in rectangle3235to the portion of the substrate contained in3235. This capacitance can be interpreted as the capacitance of a portion of a periodic capacitance structure (periodic in x and y directions) that extends to infinity in vertical as well as horizontal expanse. The portion of the infinite capacitor that this circuit considers is a portion like that contained in rectangle3235.

Similarly, circuit3300ofFIG. 33measures the capacitance from the portion of first lines3304contained in rectangle3335to the portions of second lines3306and the underlying ground plane (normally the substrate) contained in rectangle3335. Again rectangle3335has height HDUTand width LDUT. HDUTcorresponds to the difference in lengths of the device under test lines3304and the dummy device lines3314. The dimensions of rectangle3335are identical to the dimensions of rectangle3235in circuit3200. Moreover, the two rectangles contain identical structures.

Finally, circuit3400ofFIG. 34measures the capacitance from the portion of second lines3406contained in rectangle3435to the portions of first lines3404and the underlying ground plane (normally the substrate) contained in rectangle3435. Again rectangle3435has height HDUTand width LDUT. LDUTcorresponds to the difference in lengths of the device under test lines3406and the dummy device lines3416. The dimensions of rectangle3435are identical to the dimensions of rectangles3235, and3335in circuits3200and3300.

Circuit3200serves the same role as circuit1382with the portion of lines3204and3206in rectangle3235serving the same roles as electrodes1322and1324(“Electrodes A and B”) in circuit1382. Circuit3300serves the same role as circuit1383with the portion of lines3304contained in rectangle3335serving the same role as electrode1342(“Electrode A”) in circuit1383. The portion of lines3306contained in circuit3300's rectangle3335serve the same role as electrode1344(“Electrode B”) in circuit1383. Circuit3400serves the same role as circuit1384with the portion of lines3406contained in rectangle3435serving the same role as electrode1364(“Electrode B”) in circuit1384. The portion of lines3404contained in circuit3400's rectangle3435serve the same role as electrode1362(“Electrode A”) in circuit1384.

With circuits3200,3300and3400acting in concert, the various interelectrode capacitances analogous to those shown inFIG. 13can be measured. For circuits3200,3300and3400, these interelectrode capacitances are the capacitances from the first set of interconnect lines to the second set of interconnect lines, from the first set of interconnect lines to the underlying ground plane (normally the substrate), and from the second set of interconnect lines to the underlying ground plane.

As with circuits2900,3000and3100, it is important to note that circuits for determining the capacitances of non-periodic structures can also be created from reductions of circuits3200,3300, and3400. A simple example is that of having a first interconnect, comprised of a single line of a first interconnect type cross a second interconnect, comprised of a single line of a second interconnect type. The first interconnect is substituted for one of the lines of each of3204,3304and3404in circuits3200,3300,3400while the second interconnect is substituted for one of the lines of3206,3306and3406. The dummy devices are versions of the device under test first and second interconnect lines that are shortened by a uniform amount so as not to include the crossings of conductors.

These dummy device lines are most easily made from copies of the device under test lines. The dummy device lines are uniformly shortened as appropriate by an amount equal to the portion of the device under test lines that were considered to be part of the device under test line crossing. All the dummy capacitances are capacitances to the underlying ground plane. Electric field continuation and generation structures3221,3220,3208,3210,3320,3310,3418, and3408are removed. The three resulting circuits are suitable for measuring the line to line and line to underlying ground plane capacitances.

All of these circuits (3200,3300,3400, and their three single lines crossing other lines embodiments) can be copied and their line widths and line spacings modified to create circuits which can be used to determine the values of various components of the overall capacitances. Further, these circuits can also be modified to consider four and more electrode capacitance systems.

FIG. 35is a schematic diagram of a test circuit3500for characterizing device parameters. Among these parameters, the circuit is well suited for measuring very small DC currents through various devices.

Circuit3500employs capacitive devices which have had their capacitance versus voltage characteristics previously characterized using various of the embodiments of circuit100for characterizing device parameters. These capacitive devices are either insulators to DC currents or else pass very small amounts of DC currents (for example 10 femto Amps, 10−14Amps).

The circuit ofFIG. 35includes a voltage sense transistor3508, which is an n-channel MOSFET in the preferred embodiment, and a duplicate transistor3512, along with a pull-up capacitor3503and a pull-down capacitive device3505. In the preferred embodiment, all of these devices are fabricated on the semiconductor substrate of a process development test chip or a production process control monitor test structure. The gate capacitance of the voltage sense transistor has also had its capacitance versus voltage characteristics previously characterized using various of the embodiments of circuit100for characterizing device parameters.

In this example, pull down device3505is a semiconductor p-n junction diode. The diode will be reversed biased and has a well characterized reverse biased capacitance. In this embodiment, circuit3500provides a means for measuring the reverse biased leakage current of diode3505. The voltage sense transistor3508has a drain connected to a probe pad3507and a source connected to a probe pad3509for applying bias voltages to the drain and to the source of transistor3508and for detecting currents into the drain of transistor3508.

One terminal of capacitor3503is connected to probe pad3502for applying voltages to the capacitor. The other terminal of capacitor3503is connected to node3504. One terminal of diode3505is connected to probe pad3506for applying voltages to the device. The other terminal of diode3505is connected to node3504. In the preferred embodiment, the p-doped end of diode3505is connected to probe pad3506and the diode's n-doped end is connected to node3504. The gate of the voltage sense transistor3508, is connected to node3504and provides a means for sensing the voltage at node3504.

The duplicate transistor3512is preferably substantially identical to the voltage sense transistor3508so that the operational characteristics of the duplicate transistor3512substantially match those of the voltage sense transistor3508. The duplicate transistor3512has a drain connected to a probe pad3510, a source connected to a probe pad3513, and a gate connected to a probe pad3511. The probe pads permit application and sensing of voltages and currents at each of the terminals of the transistor3512.

To first order, devices3503,3505and3508form a capacitive voltage divider from node3502to node3506with node3502intended to be the more positive voltage going of the several nodes. During voltage division, with the voltage on node3502being increased in the positive sense and the voltages applied to nodes3506,3507and3509being held constant, the increase in voltage on node3502tends to couple positive voltage onto node3504via the capacitance of device3503. At the same time, the capacitances of devices3505and3508tend to retard the increase in voltage on node3504. The capacitances associated with device3508which tend to retard the rise in voltage on node3504are the transistor's gate to drain, gate to source, gate to inversion layer and gate to body capacitances.

The voltage sense transistor3508, with its gate connected to the common node3504, provides an indication of the voltage at the common node3504. Preferably, the pull-up capacitor3503is a known value capacitor such as a voltage invariant metal-to-metal capacitor characterized using the techniques described herein, or a well characterized voltage variable gate oxide capacitor characterized using the techniques described herein. When3503is a gate oxide capacitor, it is normally implemented as a p-channel transistor with its gate connected to node3504and its source and drain connected to node3502. In the preferred embodiment, the transistor is formed in an n-doped well in the semiconductor's p-doped substrate. Similarly, the pull down device3505has a capacitance-voltage behavior characterized using the techniques described herein. Any type of capacitive device may be suitably used.

During voltage division, the voltage on node3504is determined via voltage sense transistor3508. Before a voltage is applied to node3502, a drain voltage is applied to node3507(for example 5 volts), and a source voltage is applied to node3509(for this example 0 volts with the substrate grounded). From this point until the end of the test, the drain current into node3507is monitored and values are periodically recorded. Voltages are applied to node3506(usually 0 volts in this embodiment) and to node3502. Representative voltage versus time characteristics are shown in FIG.36. An example voltage signal to be applied to node3502is marked3602in FIG.36. When a positive voltage is applied to node3502, capacitor3503couples a positive voltage onto node3504raising the voltage on the node. The voltage on node3504must attain a voltage large enough to turn on transistor3508. The magnitude of the voltage on node3504is determined by the value of the voltage applied to node3502and by the capacitances of devices3503,3505and3508. The sizes of these devices' capacitances can be suitably chosen during test circuit construction. With the voltage on node3504large enough to exceed the gate to source threshold voltage of transistor3508, the transistor turns on and conducts current.

The amount of current flowing into the drain of transistor3508is a strong function of the voltage on the transistor's gate, the voltage on node3504. This is particularly the case when the voltage on node3507, the transistor's drain, is chosen to be substantially greater than the voltage that will appear on node3504(transistor in saturation).

The precise voltage, normally within ±0.005 volts, on node3504can be determined by also applying the same drain and source voltages to duplicate transistor3512that are applied to transistor3508. The same voltage as that which is applied to probe pad3507is applied to probe pad3510and the same voltage as that which is applied to probe pad3509is applied to probe pad3513. A voltage is applied to the duplicate transistor's gate probe pad3511. The current into the duplicate transistor's drain3510is also monitored and the voltage applied to the duplicate transistor's gate,3511, is modified until the current into the drain3510of the duplicate transistor is the same as the current into the drain3507of the voltage sense transistor. Typically the voltage on the gate of transistor3512is binary searched by the automatic test system that is conducting the tests. Once equivalent drain currents are achieved in the two transistors, the voltage on the gate3511of the duplicate transistor3512is the same as the voltage on node3504, the gate of the voltage sense transistor.

It is important to note that the periodic recording of the currents through sense transistor3508and the determination of the matching gate voltages on node3511of duplicate transistor3512need not occur simultaneously. A series of currents into node3507can be measured over time and later these currents can be used to determine what the voltage on node3504was at the time of each measurement. As long as the temperatures of transistors3508and3512are the same during the measurements of currents into nodes3507and3510, and as long as the parameters of the two devices are stable over time, the measurement of currents into node3507and the determination of the corresponding voltages on node3504can take place at widely separate times.

As the voltage on node3502is raised from ground potential to a fixed voltage, the voltage on node3504will increase to a specific voltage due to the coupling of voltage through capacitor3503.FIG. 36illustrates exemplary voltage versus time signals for the voltage applied to node3502(curve3602) and for the resultant voltage on node3504(curve3606). At time t1, the voltage applied to node3502has reached its peak value and is then held constant. In response, the voltage on node3504rises to its peak voltage shown as point3604. Due to the positive voltage on node3504, device3505, which is in this case a reverse biased diode, will begin to pass current. This current will slowly reduce the positive charge on the node3504connected terminals of the various capacitive devices connected to node3504. Over time, this charge loss will lower the voltage on node3504. The sizes of the capacitances of devices3503,3505and transistor3508can be chosen during test circuit design to adjust the expected fall rate of the voltage on node3504. This is an important test equipment issue. The fall rate must be slow enough to allow the test equipment enough time to measure the currents into node3507several times during the fall time. Very slow voltage decay times require larger capacitors and can lengthen test times. Very fast voltage decay times can be too fast for some parametric test systems to accurately measure.

Having a thorough understanding of the capacitance versus voltage characteristics of the devices in circuit3500, and having an accurate method for monitoring the time dependence of the voltage on node3504, provide a means for determining the amount of current flowing through device3505. The leakage current through the diode is equal to the time derivative of the voltage on node3504(dV/dt) multiplied by the sum of the capacitances connected to node3504. This assumes that the voltages on all other nodes of circuit3500are constant. This derivative is shown inFIG. 36as the slope of the tangent3608to the voltage versus time curve for the voltage on node3504. This tangent occurs at time t2in FIG.36. The diode current calculated from the time derivative would be valid for the voltages at time t2. If necessary, a circuit simulator can also be used as an aid in determining the current through device3505from the change in node3504's voltage over time. Careful choice of the types and capacitances of the devices used in circuit3500enables a wide range of voltages to be induced on node3504. This in turn allows the current through device3505to be characterized over a wide range of DC voltage conditions.

Because the reverse biased leakage current of each diode can vary greatly with variations in temperature, several circuits with several sets of device capacitance sizes may be necessary for characterizing the leakage currents of each diode over a range of temperatures. Copies of all of the capacitors connected to node3504can be thoroughly characterized via the various embodiments of the capacitance measurement methods provided by circuit100.

The implementation illustrated inFIG. 35is particularly suitable for measuring reverse bias currents in the diode forming the pull down capacitor3505. The pull-up capacitor3503is preferably a capacitor that allows passage of little or no DC current while the reverse biased diode3505allows passage of some level of DC current. Further, the gate of the voltage sensing transistor3508allows passage of little or no DC current.

In this embodiment, the device which has its current characterized and which acts as the voltage divider pull down device3505is a diode. In alternative embodiments, small currents can be measured through any device with a capacitance. The device to be measured is placed in the position occupied by device3505in circuit3500.

It is to be noted that the techniques for characterizing the reverse bias diode forming the pull down capacitor3505may be extended to a characterization of any suitable device. This includes any of the p-n junctions formed in the semiconductor substrate, including well-substrate junctions, active area-substrate junctions, active area-well junctions, etc. Further, the currents through other types of devices such as the gate leakage currents of metal semiconductor field effect transistors (MESFET's) may be characterized in this manner.

When it is desired to measure the current through a device that has a relatively small capacitance, a non-conductive device (non-conductive in the DC sense) with a large capacitance can be placed in the position occupied by device3505in circuit3500. The low capacitance device with the current to be measured is placed in parallel with the larger capacitance device occupying the place of3505. The current through the low capacitance device is measured in the same fashion as described herein with the only difference being that the calculation of the current must also account for the capacitance of the added large capacitance device.

FIG. 37illustrates an extension of this general technique. Circuit3700provides a means for measuring tunnel currents through a dielectric such as a gate oxide layer. Circuit3700includes a voltage sense transistor3708having a drain connected to a probe pad3707, a source connected to a probe pad3709and a gate connected to node3704. In the preferred embodiment, the sense transistor is an n-channel enhancement transistor formed in a p-doped well3721in an n-doped well3720formed in the semiconductor substrate. In this way positive or negative voltages can be applied to p-well3721. With negative voltages applied to p-well3721, sense transistor3708can be operated with negative voltages present on its drain3707, source3709and gate3704nodes.

Circuit3700further includes a duplicate transistor3712having its drain, gate and source electrically connected to probe pads3710,3711and3713, respectively. Duplicate transistor3712also resides in a p-doped well in an n-doped well in the p-doped semiconductor substrate. In the preferred embodiment, the sense device and the duplicate sense device share the same p-well3721and the same n-well3720. In addition, in the circuit3700, a capacitor voltage divider is formed using a pull-up capacitor3703and a pull down capacitor3716. In the implementation ofFIG. 37, the pull down capacitor3716is formed using the floating gate of a floating gate transistor. Floating gate transistors are typically used in non-volatile memory devices such as in Flash EPROM memories. The floating gate device has source and drain regions diffused in a substrate or a well area. Above the source, drain and transistor channel are two gates made of poly silicon. The first gate is a floating gate, meaning that it is not normally electrically connected and is isolated by a gate dielectric and an inter-poly dielectric. The second gate is a control gate and is electrically connected to other portions of the circuit. In the circuit3700, the source of the floating gate transistor is connected to a probe pad3714and the drain of the transistor is connected to a probe pad3717. The floating gate is electrically connected to node3704. The control gate of the floating gate transistor is electrically connected to a probe pad3706.

The pull-up capacitor3703is preferably a previously characterized voltage-dependent or voltage-independent capacitor. In one embodiment, capacitor3703is a p-channel MOSFET transistor gate oxide capacitor formed in an n-well formed in the p-type substrate. The transistor capacitor uses thick gate oxide as opposed to tunnel oxide. The voltage divider upper node at the probe pad3702is formed from the source/drain diffusion of gate oxide capacitor3703. The gate of gate oxide capacitor3703is connected to node3704. Alternatively, the capacitor3703may be formed using a metal-to-metal capacitor.

Copies of all of the capacitances in the circuit3700are previously characterized via the use various embodiments of circuit100. For example, the tunnel oxide capacitance between the floating gate and the source and drain of the transistor forming the pull down capacitor has been previously characterized for voltage dependence.

Using methods very similar in concept to those described in conjunction with circuit3500, the tunneling current from the floating gate3715to the channel and source and drain of floating gate transistor3716can be characterized over a range of voltages. In addition to providing for the inducement of and sensing of positive voltages on node3704, circuit3700provides for the inducement and sensing of negative voltages on node3704. The tunneling of electrons from the floating gate3715, to the channel, to the source3714or to the drain3717of transistor3716can be characterized when node3704has a sufficient negative voltage on it. Negative voltages are coupled into node3704via the application of negative voltages to nodes3702and3706. In addition to the rest of the capacitances in circuit3700, the tunneling current calculations must take into account the effects of the capacitance from transistor3716's floating gate3715to the transistor's control gate3705.

Along with allowing the measurement of tunneling currents through the tunneling dielectric between the channel of transistor3716and floating gate3715, circuit3700also allows the programming and erasure of floating gate transistor3716. Normal memory transistor source and drain voltages suitable for transistor programming and erasure can be applied to the source3714and drain3717of floating gate transistor3716while normal programming and erase voltages can be connected onto the floating gate via the application of appropriate voltages to probe pads3702and3706.

Through its ability to provide a method for measuring the amount of charge on node3704, circuit3700provides a way to measure the amount of charging current flowing through the channel to floating gate dielectric during the programming of transistor3716. As already noted above, the circuit provides for the measurement of tunneling current through this same dielectric. This tunneling current is the current that is normally used to erase the transistor.

As with test circuit100and its devices under test, multiple copies of test circuits3500and3700and their associated devices under test,3505and3705, and their duplicate sense transistors,3512and3712, can be constructed in smaller spaces on test wafers than can the probe pads that are required for connecting such circuits to parametric test systems. Using just a few probe pads to control many such circuits3500and3700can be very advantageous from the standpoint of saving space on test wafers and test chips. Moreover, using just a few probe pads to control many test circuits3500and3700is a likely requirement for economically placing large numbers of current measurement circuits3500and3700into product wafer scribe lines scribe grids.

FIG. 38illustrates an exemplary embodiment of a test circuit3800that uses a relatively small number of probe pads to control a large number of individual test circuits. Test circuit3800controls multiple copies of test circuit3500. A very similar method can be used to control multiple copies of test circuit3700. Test circuit3800allows the sharing of individual test structure probe pads by numerous device test structures, that is, multiplexing of test structure probe pads.

InFIG. 38, the multiplexing technique is implemented by connecting numerous copies of a test circuit such as test circuit3500to the same probe pad, pad3807. The copies of circuit3500are connected in a parallel configuration. The connections to probe pad3807are made through select transistors3817,3827,3837. In this embodiment, these select transistors are p-channel MOSFET transistors fabricated in an n-doped well in the semiconductor technology's p-doped substrate. Although only three measurement circuits,3871,3872,3873, are shown inFIG. 38connected to probe pad3807, the circuit3800can accommodate many copies of such circuits. Many circuits such as circuit3871can be connected to a single probe pad such as pad3807. Each circuit like3871can be linked to the probe pad with a select transistor identical to transistors3817,3827,3837.

Furthermore,FIG. 38shows the circuitry associated with only one multiplexed probe pad3807. Normally, multiple copies of the circuit shown inFIG. 38are fabricated in close proximity to one another. These multiple copies share common signal lines.

Along with controlling select transistors3817,3827,3837, probe pads3802,3812,3822also control the select transistors connecting other probe pads similar to pad3807with other measurement circuits similar to circuits3871,3872,3873. Probe pads3832,3806,3809,3819each also carry common signals to these other measurement circuits connected to other probe pads similar to probe pad3807.

Circuit3800functions in a very similar fashion to how circuit3500functions. Reverse biased leakage currents are measured through diodes3805,3815,3825in largely the same manner as currents are measured through diode3505of circuit3500. Pull up capacitors3803,3813,3823have the same role as pull up capacitor3503in circuit3500. Voltage sense transistors3808,3818and3828have the same role as voltage sense transistor3508of circuit3500. Duplicate sense transistor3852is substantially identical to voltage sense transistors3808,3818,3828. Duplicate sense transistor select device3855is substantially identical to select transistors3817,3827,3837. This embodiment also includes auxiliary pull down capacitors3804,3814and3824. These capacitors are added to circuit3800as an example of how additional capacitance can be added in parallel with diodes3805,3815,3825. This is sometimes done in order to augment the natural capacitances of the diodes3805,3815,3825. These auxiliary capacitors are typically included in circuits such as circuit3800and circuit3500when the capacitances of diodes3805,3815,3825and3505are small compared with the capacitances of the other devices in the circuits. Auxiliary pull down capacitors3804,3814,3824are often not necessary and are not specifically needed for the multiplexing accomplished by circuit3800.

A single current measurement circuit such as circuit3871can be selected from among the various current measurement circuits by turning on the selected circuit's select transistor. For example, individual current measurement circuit3871can be used to measure the current through diode3805by applying an appropriately large negative voltage to probe pad3822which is electrically coupled with the gate of select transistor3817. Meanwhile, measurement circuits3872,3873and all other measurement circuits connected to node3807are deselected by applying appropriately large positive voltages to their select transistors3827,3837and the select transistors for any other measurement circuits connected to probe pad3807.

In this way, applying a positive voltage to probe pad3807allows current to enter the drain of transistor3808. This current is analogous to the current running into the drain of transistor3508when circuit3500is sensing the voltage on node3504. With a sufficiently large negative voltage on the gate3822, of p-channel select transistor3817, almost all of the voltage from pad3807to sense transistor source pad3809is present as drain to source voltage on transistor3808. In other words, transistor3817is operated in its linear mode with very little voltage drop from its source to its drain. Further, select transistors3817,3827,3837and3855are normally designed with short channel lengths and wide channel widths. In this way, when the transistors are turned on, their drain to source voltages will be small even with relatively large source to drain currents running through them.

As with circuit3500, the voltages on nodes3881,3882,3883are determined from the amounts of currents passing through transistors3808,3818,3828. Again, note that only one of these transistors will be passing current during a given measurement. The other two circuits' select transistors are turned off. As with circuit3500, the voltage on the gate3851of the duplicate sense transistor3852is varied until the current through the duplicate sense transistor matches the current through the selected sense transistor one of either3808,3818or3828.

To some extent, the presence of the select transistors in circuit3800will influence the drain to source current passing through the selected sense transistor. This influence is duplicated by the duplicate select transistor3855in the duplicate sense circuit. This duplicate sense circuit is shown inFIG. 38connected to probe pads3850,3853,3854,3851. For example, assume that transistors3827and3837and other select transistors not shown inFIG. 38are unselected (turned off). With equal voltages applied to probe pads3807,3850, equal voltages applied to probe pads3809,3853, and equal voltages applied to probe pads3822,3854, equal currents will flow through transistors3808and3852once the voltage on node3851attains the same level as the voltage on node3881.

The currents through diodes3804,3814and3824are determined as explained in the previous discussions of circuit3500in FIG.35. Multiple copies of circuit3800connected to multiplexed pads like3807and sharing common nodes3802,3812,3822,3832,3806,3809and3819can be used to accurately measure very small currents through devices such as the diodes in the example of FIG.38. Moreover, this method can measure the small currents through a large number of devices while using a minimum number of probe pads.

For example, if the devices in circuit3800could be made sufficiently small, a 46 pad test tile could accommodate nearly 400 separate test diodes of various types and sizes. Common probe pads3832,3806,3809,3819, an n-well probe pad, and a substrate probe pad would consume six probe pads. Nineteen probe pads would be used for select gate bias pads. These pads would be similar to probe pads3802,3812and3822. Twenty probe pads would be used in the same fashion as probe pad3807as sense transistor drain bias probe pads. Each of the twenty drain bias probe pads, similar to probe pad3807, would be connected to the sources of 19 select transistors. Each of those select transistors would be connected to a separate current measurement circuit like circuits3871,3872and3873. Each of the gates of the 19 select transistors connected to a single drain bias probe pad would be connected to a separate select gate bias probe pad. In this way, each of the select transistors connected to a single drain bias probe pad can be individually controlled either selected or unselected. During measurements involving a particular drain bias probe pad like pad3807, the 19 select gate bias probe pads would be used to select one of the 19 select transistors connected to the drain bias probe pad and to deselect the other 18 select transistors also connected to that drain bias probe pad.

The duplicate sense transistor circuit can also be integrated with the measurement circuits in this 46 probe pad test tile. Duplicate drain node3850is connected to one of the 20 drain bias probe pads and probe pad3850is omitted. Transistor3855is substituted for one of the 19 select transistors connected to that drain bias probe pad. The duplicate select transistor's gate bias node is controlled by the select gate bias probe pad that the replaced select transistor was connected to. Probe pad3854is thus omitted. Node3853is connected to the common source probe pad3809and probe pad3853is omitted. Duplicate sense transistor gate node3851requires its own dedicated probe pad.

In this way the reverse bias leakage currents of 379 separate diodes can be measured using only 46 pads. This number of diodes comes from having 20 drain bias probe pads with 19 measurement circuits connected to each drain bias probe pad. One of the 19 circuits on one of the pads is replaced with a duplicate sense circuit. In practice, the devices in circuit3800are not usually small enough to allow this level of test wafer packing efficiency. However, it is extremely useful to even use probe pad multiplexing just to double the number of devices that can be tested using a given number of probe pads.

It is important to note thatFIG. 38is only one possible embodiment of ways to reduce the number of probe pads required for test structures that are designed for measuring small device currents.

From the foregoing, it can be seen that the illustrated embodiments provide an improved method and apparatus for characterizing on-chip devices, currents and capacitances, in particular those which are variable with applied voltage. A novel circuit allows application of voltages to bias nodes that are not the same as the substrate voltage or any other voltage in the circuit. This allows complete characterization across all applied voltages. Switching devices are employed that are capable of applying bias voltages that can be both negative as well as positive with respect to the non-clocked electrode of the device under test.

While a particular embodiment of the present invention has been shown and described, modifications may be made. It is therefore intended in the appended claims to cover all such changes and modifications which fall within the true spirit and scope of the invention.