Outputting of codeword bits for transmission prior to loading all input bits

Methods, systems, and devices for outputting of codeword bits for transmission prior to loading all input bits. An example encoder may have multiple encoding branches. The encoder may divide the encoding branches into first and second encoding branch subsets, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset. The encoder may generate first and second subsets of output bits of a codeword in first and second encoding operations, the generating comprising inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset. The encoder may output the first subset of output bits prior to outputting the second subset of output bits.

INTRODUCTION

The following relates generally to wireless communication, and more specifically to outputting of codeword bits for transmission prior to loading all input bits.

Code blocks may be encoded by a transmitting device (e.g., a base station or UE) using an encoding algorithm. Error correcting codes may be used to introduce redundancy in a code block so that transmission errors may be detected and corrected. Some examples of encoding algorithms with error correcting codes include convolutional codes (CCs), low-density parity-check (LDPC) codes, and polar codes. A polar code is an example of a linear block error correcting code and is the first coding technique to provably achieve channel capacity. Encoding algorithms require implementation, and existing implementations may have system constraints such as input and output bus widths or finite processing speed. System performance for implementations may be determined by factors such as overhead, coding gain, transmission pipelining, and decoding delay. Existing implementations do not provide satisfactory results for one or more of these factors.

SUMMARY

A method for encoding by an encoder comprising a plurality of encoding branches is described. The method may include dividing the plurality of encoding branches into at least a first encoding branch subset and a second encoding branch subset, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset, generating first and second subsets of output bits of a codeword in first and second encoding operations, the generating comprising inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset, and outputting, from the encoder, the first subset of output bits prior to outputting the second subset of output bits.

An apparatus for encoding is described. The apparatus may include means for dividing a plurality of encoding branches into at least a first encoding branch subset and a second encoding branch subset, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset, means for generating first and second subsets of output bits of a codeword in first and second encoding operations, the generating comprising inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset, and means for outputting the first subset of output bits prior to outputting the second subset of output bits.

Another apparatus for encoding is described. The apparatus may include a processor, memory in electronic communication with the processor, and instructions stored in the memory. The instructions may be operable to cause the processor to divide a plurality of encoding branches into at least a first encoding branch subset and a second encoding branch subset, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset, generate first and second subsets of output bits of a codeword in first and second encoding operations, the generating comprising inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset, and output the first subset of output bits prior to outputting the second subset of output bits.

A non-transitory computer readable medium for encoding is described. The non-transitory computer-readable medium may include instructions operable to cause a processor to divide the plurality of encoding branches into at least a first encoding branch subset and a second encoding branch subset, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset, generate first and second subsets of output bits of a codeword in first and second encoding operations, the generating comprising inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset, and output the first subset of output bits prior to outputting the second subset of output bits.

Some examples of the method, apparatus, and non-transitory computer-readable medium described above may further include processes, features, means, or instructions for receiving a first of a plurality of subsets of the information bits of the information bit-vector prior to receiving a last of the plurality of subsets of the information bits of the information bit-vector.

In some examples of the method, apparatus, and non-transitory computer-readable medium described above, the outputting of the first subset of output bits may be performed prior to the receiving of the last of the plurality of subsets of the information bits of the information bit-vector.

Some examples of the method, apparatus, and non-transitory computer-readable medium described above may further include processes, features, means, or instructions for receiving the information bits of the information bit-vector for generating the codeword at a constant rate. Some examples of the method, apparatus, and non-transitory computer-readable medium described above may further include processes, features, means, or instructions for receiving the information bits of the information bit-vector for generating the codeword at a variable rate.

In some examples of the method, apparatus, and non-transitory computer-readable medium described above, generating at least one of a plurality of subsets of output bits using one of a plurality of encoding branch subsets comprises: inputting at least one frozen bit into the one of the plurality of encoding branch subsets.

In some cases, each of the subsets of output bits, including the first and second subsets, have a same number of bits. In some cases, the first subset of output bits has a different number of bits than the second subset of output bits.

Some examples of the method, apparatus, and non-transitory computer-readable medium described above may further include processes, features, means, or instructions for determining a code rate for the encoding by selecting a number of frozen bits for input to the plurality of encoding branches.

Some examples of the method, apparatus, and non-transitory computer-readable medium described above may further include processes, features, means, or instructions for performing bit-reversal on input indices of the plurality of encoding branches relative to corresponding output indices of the plurality of encoding branches prior to the dividing of the plurality of encoding branches.

In some examples of the method, apparatus, and non-transitory computer-readable medium described above, each of the plurality of subsets of output bits may have a same number of bits.

In some examples of the method, apparatus, and non-transitory computer-readable medium described above, the first of the plurality of subsets of output bits may have a different number of bits than the second of the plurality of subsets of output bits.

In some examples of the method, apparatus, and non-transitory computer-readable medium described above, a first subset of the bit-reversed indices correspond to the first encoding branch subset and a second subset of the bit-reversed indices correspond to the second encoding branch subset, and wherein each bit-reversed index in the first subset of the bit-reversed indices may have a higher number than each bit-reversed index in the second subset of the bit-reversed indices.

In some examples of the method, apparatus, and non-transitory computer-readable medium described above, the first subset of output bits correspond to a first subset of the output indices of the plurality of encoding branches and the second subset of output bits correspond to a second subset of the output indices of the plurality of encoding branches, and wherein the first subset of the output indices and the second subset of the output indices may be interleaved with each other.

In some examples of the method, apparatus, and non-transitory computer-readable medium described above, the second subset of output bits may be dependent on the first subset of output bits and bits input to the second encoding branch subset. In some examples of the method, apparatus, and non-transitory computer-readable medium described above, the first subset of output bits may be transmitted prior to transmission of the second subset of output bits.

In some examples of the method, apparatus, and non-transitory computer-readable medium described above, the encoder may be a linear block encoder. In some examples of the method, apparatus, and non-transitory computer-readable medium described above, the linear block encoder may be a polar code encoder, a Reed-Muller (RM) encoder, a polar RM encoder, a systematic encoder, or a bit-reversed encoder.

In some examples of the method, apparatus, and non-transitory computer-readable medium described above, generating the first and second subsets of output bits of the codeword in first and second encoding operations comprises: inputting a first subset of the information bits of the information bit-vector and a first error detecting code generated from the first subset of the information bits to encoding branches of the first encoding branch subset for generating the first subset of output bits. Some examples of the method, apparatus, and non-transitory computer-readable medium described above may further include processes, features, means, or instructions for inputting a second subset of the information bits of the information bit-vector and a second error detecting code generated from the first subset of the information bits, the second subset of the information bits, or both the first and second subsets of the information bits, to encoding branches of the second encoding branch subset for generating the second subset of output bits.

DETAILED DESCRIPTION

Techniques are described for outputting codeword bits for transmission prior to loading all input bits. An encoder may include multiple encoding branches that are each loaded with a bit to be encoded. The encoding branches may have different levels of dependency, where the encoding branch dependency may be associated with a number of encoding branches on which the codeword bit associated with the encoding branch depends. Conventional encoding techniques result in undesirable encoder latency as such techniques do not consider dependencies between encoding branches and delay outputting bits of a codeword until a most dependent bit of the codeword is calculated. The most dependent bit of the codeword may be the bit that depends on the highest number of other encoding branches in a set of encoding branches. The encoder examples described herein decrease encoder latency by dividing encoding branches into at least two subsets based at least in part on inter-branch dependencies. The encoder may process encoding branches subset by subset in order of increasing inter-branch dependency. An encoder may first encode bits using an encoding branch subset that is independent of other encoding branches and output those encoded bits for transmission prior to outputting bits encoded by branches that depend on other encoding branches. By encoding and outputting encoded bits in such a manner, the encoder as described herein may have less latency as compared to conventional encoders that do not consider branch inter-dependency. The encoder may also output codeword bits in sets that provide for simplified memory access by a decoder.

Aspects of the disclosure are initially described in the context of a wireless communications system. Devices of the wireless communications system, such as user equipment and base stations, may decrease encoder latency by utilizing encoders that output codeword bits for transmission prior to loading all input bits. Aspects of the disclosure are further illustrated by and described with reference to apparatus diagrams, system diagrams, and flowcharts that relate to outputting of codeword bits for transmission prior to loading all input bits.

FIG. 1illustrates an example of a wireless communications system100in accordance with one or more aspects of the present disclosure. The wireless communications system100includes base stations105, UEs115, and a core network130. In some examples, the wireless communications system100may be an LTE, LTE-Advanced, new radio (NR), or 5G network. In NR or 5G networks, the base stations105may include access nodes (ANs), central units (CUs), and/or distributed units (DUs). An AN may be an example of a new radio base station (NR BS), a new radio Node-B (NR NB), a network node (NN), or the like. A CU may be an example of a central node (CN), an access node controller (ANC), or the like. Each of the DUs may be an example of an edge node (EN), an edge unit (EU), a radio head (RH), a smart radio head (SRH), a transmission and reception point (TRP), or the like. The UEs115, base stations105, and other devices of wireless communications system100may have low-latency encoders that output codeword bits for transmission prior to loading all input bits. A UE115, a base station105, or both, may include, an encoding component1315as described below in further detail.

Base stations105may communicate with the core network130and with one another. For example, base stations105may interface with the core network130through backhaul links132(e.g., S1, etc.). Base stations105may communicate with one another over backhaul links134(e.g., X2, etc.) either directly or indirectly (e.g., through core network130). Base stations105may perform radio configuration and scheduling for communication with UEs115, or may operate under the control of a base station controller (not shown). In some examples, base stations105may be macro cells, small cells, hot spots, or the like. Base stations105may also be referred to as eNodeBs (eNBs)105. Wireless communications systems are widely deployed to provide various types of communication content such as voice, video, packet data, messaging, broadcast, and so on. These systems may be capable of supporting communication with multiple users by sharing the available system resources (e.g., time, frequency, and power). Examples of such multiple-access systems include CDMA systems, TDMA systems, FDMA systems, and OFDMA systems. A wireless multiple-access communications system may include a number of base stations, each simultaneously supporting communication for one or more multiple communication devices, which may be otherwise known as a UE.

In some cases, a base station105and a user equipment (UE)115may communicate using carrier frequencies at 6 GHz or less (sub-6), or higher such as 28 GHz, 60 GHz, etc. which is also known as millimeter wave communications. Each component can have a bandwidth of, e.g., 1.4, 3, 5, 10, 15, 20 MHz, etc. In some cases, a base station105and a UE115may communicate using more than one carrier in a carrier aggregation (CA) configuration. Each aggregated carrier is referred to as a component carrier (CC). In some cases, the number of CCs can be limited to, e.g., a maximum of five 20 MHz carriers, giving maximum aggregated bandwidth of 100 MHz. In frequency division duplexing (FDD), the number of aggregated carriers can be different in downlink (DL) and uplink (UL). The number of UL component carriers may be equal to or lower than the number of DL component carriers. The individual component carriers can also be of different bandwidths. For time division duplexing (TDD), the number of CCs as well as the bandwidths of each CC will normally be the same for DL and UL. Component carriers may be arranged in a number of ways. For example, a carrier aggregation (CA) configuration may be based at least in part on contiguous component carriers within the same operating frequency band, i.e., called intra-band contiguous CA. Non-contiguous allocations can also be used, where the component carriers may be either be intra-band, or inter-band.

Within a CA configuration, certain CCs may be configured differently from other CCs of the CA configuration. For example, the CA configuration may include a primary CC (PCC or PCell) and one or several secondary CCs (SCC or SCell). The PCell may be configured to carry uplink and downlink control information on PUCCH and PDCCH/ePDCCH, respectively. PDCCH on a PCell may include scheduling information for resources of the PCell or for resources of one or more SCells, or both. An SCell may include PDCCH, which may include scheduling information for resources of that SCell or for one or more other SCells. Some SCells may be configured for downlink communications and may not be configured for uplink communications, while a PCell may be configured for both uplink and downlink communications. Various carriers of the CA may be TDD or FDD configured. A CA configuration may include both TDD and FDD configured carriers.

In some cases, wireless communications system100may utilize enhanced component carriers (eCCs). In some examples, NR or 5G networks may utilize eCCs, and the use of eCCs over a shared spectrum may be referred to as New Radio for Shared Spectrum (NR-SS). An SCell may, for instance, be an eCC. An eCC may be characterized by one or more features including: wider bandwidth, shorter symbol duration, shorter TTIs, and modified control channel configuration. In some cases, an eCC may be associated with a carrier aggregation configuration or a dual connectivity configuration (e.g., when multiple serving cells have a suboptimal or non-ideal backhaul link). An eCC may also be configured for use in unlicensed spectrum or shared spectrum (where more than one operator is allowed to use the spectrum). An eCC characterized by wide bandwidth may include one or more segments that may be utilized by UEs115that are not capable of monitoring the whole bandwidth or prefer to use a limited bandwidth (e.g., to conserve power). In some cases, an eCC may utilize a different symbol duration than other CCs, which may include use of a reduced symbol duration as compared with symbol durations of the other CCs. A shorter symbol duration is associated with increased subcarrier spacing. A device, such as a UE115or base station105, utilizing eCCs may transmit wideband signals (e.g., 20, 40, 60, 80 MHz, etc.) at reduced symbol durations (e.g., 16.67 microseconds). A TTI in eCC may consist of one or multiple symbols. In some cases, the TTI duration (that is, the number of symbols in a TTI) may be variable.

In some environments, reducing or minimizing system latency may be an important system performance factor. However, an encoder may have a finite input bus width or input bits of a single input vector may become available at different times. For example, an input vector may include information bits and check bits, where some or all information bits may be generated by or received from different sources. In addition, the check bits may not be available until sometime after all of the information bits are available. The input vector may be, for example, a physical channel message (e.g., control channel message) or a data packet. Additionally or alternatively, a codeword corresponding to a single input vector may not be transmitted in a single transmission time interval (e.g., one symbol period, multiple symbol periods, etc.). For example, transmissions associated with a physical channel message or packet may span multiple transmission time intervals.

System performance of transmission of information bits in low-latency environments may be determined by factors such as overhead, coding gain, transmission pipelining, and decoding delay. Some processing techniques may emphasize improving transmission pipelining and decoding delay at the expense of higher overhead and lower coding gain. Generally, use of a larger code length (e.g., larger codeword) reduces overhead and provides higher coding gain. However, a larger code length may result in a larger decoding delay and overall system latency. In contrast, smaller code length reduces latency or decoding delay but results in an increase in overhead and lower coding gain.

Components of the wireless communications system100including the base stations105or UEs115may implement encoding techniques that output codeword bits for transmission prior to loading all input bits. A base station105or a UE115may include an encoder having multiple encoding branches that are each loaded with a bit to be encoded. The encoder examples described herein may decrease encoder latency by dividing encoding branches into subsets based at least in part on inter-branch dependencies. The encoder may process encoding branches subset by subset in order of increasing inter-branch dependency. In an example, the encoder may first encode bits using an encoding branch subset that is independent of other encoding branches and output those encoded bits for transmission prior to outputting bits encoded by branches that depend on other encoding branches. By encoding and outputting encoded bits in such a manner, an encoder as described herein may have less latency as compared to conventional encoders that do not consider branch inter-dependency.

FIG. 2illustrates an example of a device200for outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. The device200may be any device within wireless communications system100that performs an encoding algorithm. The device200may be, for example, a UE115or base station105as described inFIG. 1. The following refers to device200as a UE115.

In many instances, a UE200may have data stored in memory205to be transmitted to another device, such as base station105. To initiate the transmission process, the UE200may retrieve from memory205the data for transmission, encode the data by an encoder210, and transmit the encoded data by a transmitter215. In one example, a bus220may connect the memory205and encoder210, and a bus225may connect encoder210and transmitter215. Bus220may provide N bits at a time to encoder210, and bus225may provide M bits at a time to transmitter215. N and M may be positive integers, may be the same number, or may be different numbers. Encoder210may use a number of encoding techniques to encode the data for transmission. For example, error correcting codes may be used to introduce redundancy in a code block so that transmission errors may be detected and corrected. Example encoding techniques include linear block encoding, polar encoding, Reed-Muller encoding, polar RM encoding, and the like. The following initially describes an example of encoder210being a polar encoder with 8 encoding branches, and later extends the principles herein to an encoder having any number of encoding branches.

FIG. 3illustrates an example of an encoder300in accordance with one or more aspects of the present disclosure. Encoder300is an example of encoder210ofFIG. 2. The following describes encoder300as being a polar encoder, and the principles described herein may be extended to other types of linear block encoders such as, for example, a Reed-Muller (RM) encoder, a polar RM encoder, a systematic encoder, a bit-reversed encoder, and the like.

In an example, polar encoder300may encode an input vector of N bits to generate a codeword X of the same number of bits. The depicted polar encoder300is an 8-bit encoder, and thus encodes an 8-bit input vector I=[i0, i1, . . . , i7] and generates an 8-bit codeword X=[x0, x1, . . . , x7]. Polar encoders of other bit-sizes may also be used. Generally, the length N of a polar encoder may follow the relationship that log2(N) is an integer. Polar encoder300includes multiple encoding branches U0to U7, where each encoding branch may be loaded with a corresponding bit from the input vector, perform one or more encoding operations on the input bit based on one or more other input bits, and output a bit x of codeword X. In branch U0, for example, bit i0is received at input310, three Boolean exclusive or (XOR) operations are performed (see “+” symbol at element320), and bit x0of codeword X is output at output315.

As depicted, each encoding branch U0to U7of polar encoder300may perform zero or more encoding operations on the input bits. Each encoding operation may be a parity check operation (e.g., XOR) or a repetition operation (repetition of a bit for use in a parity check operation for a different branch). Encoding a bit in one encoding branch may depend on bits input to one or more other encoding branches. For example, branch U6performs a parity check operation by XOR'ing bits i6and i7(e.g., x6=i6XOR i7). As seen, bit i6is loaded at input325of encoding branch U6and bit i7is loaded at input330of branch U7. At335, encoding branch U6XORs i6and i7and provides x6at output340. The remaining encoding branches U0to U7perform similar operations to encode corresponding bits of the input vector. In conventional techniques, bits of the input vector are loaded to encoding branches U0to U7from top to bottom, represented by arrow305. Thus, input i0is first loaded into encoding branch U0, input i1is next loaded into encoding branch U1, and so forth. The resulting codeword X is similarly output from polar encoder300to a transmitter (e.g., transmitter215ofFIG. 2) for transmission in top to bottom order. Thus, codeword bit x0is transmitted first, codeword bit x1is transmitted next, and so forth. Loading bits of input vector and outputting bits of codeword X from top to bottom results in undue encoding latency.

FIG. 4illustrates an example of an encoder400in accordance with one or more aspects of the present disclosure. This figure illustrates how conventional techniques of loading and outputting from a polar encoder cause encoding latency. Polar encoder300-ais an example of polar encoder210,300ofFIGS. 2-3. Certain lines of the polar encoder300-ahave been darkened to show inter-branch dependency. The encoding branch dependency for each of the codeword bits x0to x7is associated with a number of encoding branches (e.g., U-bits) on which the codeword bit associated with the encoding branch depends. The most dependent bit of the codeword depends on the highest number of other encoding branches in the polar encoder300-a. As illustrated, codeword bit x0depends on bits input to all of the encoding branches U0to U7. Thus, codeword bit x0is the most dependent as its output depends on all of the other encoding branches. While not darkened, it can be seen that codeword bit x1depends on bits input to encoding branches U1and U3to U7, codeword bit x2depends on bits input to encoding branches U2, U3, U6and U7, and so forth. Thus, from top to bottom, a bit input to a particular encoding branch of polar encoder300-agenerally depends on bits encoded by one or more higher-indexed encoding branches, but is generally independent of bit(s) input to any lower-indexed encoding branch.

Conventional techniques load bits into the polar encoder300-afrom top to bottom (see arrow420), and similarly output codeword bits x from top to bottom (see arrow425). Loading and outputting encoded bits from top to bottom results in excessive encoder latency because transmission cannot begin until the codeword bit x0, having the highest inter-branch dependency, is ready for transmission. Moreover, polar encoders300and300-acannot generate codeword X until all inputs are available at each encoding branch U. The examples described herein reduce encoder latency by changing the order in which bits are loaded into and outputted from a polar encoder.

FIG. 5illustrates an example of a polar encoder500for outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. Polar encoder500is an example of polar encoder210,300,300-aofFIGS. 2-4. To reduce encoder latency, polar encoder500reverses the order in which bits of an input vector are loaded and codeword bits are output. By doing so, the polar encoder500can output at least some codeword bits of codeword X to transmitter215for transmission prior to loading all bits of input vector and prior to generating an entire codeword X. In some instances, the polar encoder500can output codeword bits for transmission by transmitter215prior to when all bits of input vector are available. In some examples, the input vector includes information bits of an information bit-vector I, frozen bits, and/or parity bits, and thus the frozen bits may be known while the information bits and parity bits (if present) may not be available all at the same time. In other examples, encoding branches corresponding to the frozen bits may be hardcoded, and, in some examples, the input vector may be the information bit-vector I and/or parity bits. An information bit-vector may also be referred to as an information block.

In an example, polar encoder500may determine which codeword bits have the fewest dependencies on other encoding branches, and load bits into encoding branches for encoding based at least in part on the inter-branch dependency. Arrow520reflects the generally bottom to top order in which bits of an input vector are loaded into polar encoder500, and arrow525reflects the generally bottom to top order in which bits of a codeword are output for transmission.

Below is a generalized algorithm for loading, encoding, and outputting using polar encoder500of an N-bit codeword length, where N is a positive integer.

1. Place a first subset of bits from the input vector in a first subset of encoding branches [uj→uN-1] having the fewest dependencies.

2. Calculate and output for transmission codeword bits [xj→xN-1] from the first subset of encoding branches.

3. Place a second subset of bits from the input vector in a second subset of encoding branches [ui→uj-1] having the next fewest dependencies.

4. Calculate and output for transmission codeword bits [xi→xj-1] from the second subset of encoding branches.

The algorithm may continue loading subsets of bits from the input vector into subsequent subsets of encoding branches having increasing amounts of inter-branch dependences until all bits of the input vector have been encoded and output. Thus, the encoder500may output one or more subsets of the codeword bits to a transmitter (e.g., transmitter215) prior to encoder500generating the entire codeword X. In some cases, encoder500may output one or more subsets of the codeword bits to the transmitter prior to receiving all bits of the input vector. Transmitter215may begin and/or complete transmitting the one or more codeword bits before a final subset of the codeword bits has been output by the polar encoder500.

Below inFIGS. 6-7are two examples of this generalized algorithm for an 8-bit polar encoder.FIG. 6describes a polar encoder that receives information bits of an information bit-vector at a constant rate and outputs bits at a variable rate, andFIG. 7describes a polar encoder that receives information bits of an information bit-vector at a variable rate and outputs codeword bits at a constant rate.

FIG. 6illustrates an example of a constant input rate polar encoder600for outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. Polar encoder600is an example of polar encoder210,300,300-a,500ofFIGS. 2-5.

Polar encoder600generally loads bits for encoding from bottom to top (see arrow620) and also generally outputs codeword bits from bottom to top (see arrow625). To do so, polar encoder600divides encoding branches into three subsets based at least in part on inter-branch encoding dependencies. The first encoding branch subset605has the fewest dependencies as encoding its input bits is independent of the bits for loading on any other encoding branch subset. The second encoding branch subset610has the next fewest dependencies as encoding its input bits only depends on the input bits themselves and the input bits to the first encoding branch subset605. The third encoding branch subset615has the most dependencies as encoding its input bits depends on the input bits themselves and both the input bits to the first and second encoding branch subsets. As can be seen, outputs for each respective encoding branch subset are independent of inputs to encoding branches of encoding branch subsets having a higher order. In an example, encoding branch subset605is independent of inputs to higher order subsets610,615, and encoding branch subset610is independent of inputs to higher order subset615.

In the depicted example, the input vector may include frozen bits and information bits of an information bit-vector. Frozen bits may be set to a defined value and may be used to define a transmission rate. For example, encoder600may determine which of the encoding branches receive the frozen bits for a given rate. Based at least in part on which encoding branches are loaded with the frozen bits, a decoder may be able to determine the transmission rate. For a polar encoder having N encoding branches, K information bits may be respectively input into K of the N branches and N-K frozen bits may be respectively input to K-N of the N branches, where K and N are integers and K is less than N. In the depicted example, frozen bits are set to 0 and input to encoding branches U0, U1, U2, U4. In other examples, a frozen bit may be set to a different value (e.g., 1), and frozen bits may be input to a different combination of encoding branches (e.g., for a different transmission rate). In some examples, frozen bits may be included in input vector. In other examples, the input vector may be an information bit-vector that includes information bits, but does not include any frozen bits. In some examples, the input vector is received and information bits of the information bit-vector are mapped to the locations of encoding branches U designated for information bits while frozen bits are mapped to the remaining encoding branches U.

Information bits carry information to be encoded. In the depicted example, information bits i0, i1, i2, and i3are input to encoding branches U3, U5, U6, U7. Below is a description of an encoding algorithm applied by polar encoder600that receives information bits of an information bit-vector at a constant rate for encoding. In this example, information bits of an information bit-vector I=[i0, i1, i2, and i3] may be made available to the encoder at a rate of two (2) bits of each of multiple time intervals. That is, i0and i1may be available (e.g., generated by a prior processing block) prior information bits i2and i3being made available.

In a first encoding operation, polar encoder600loads a first subset of bits of the input vector into the first encoding branch subset605. In particular, bit i0of information bit-vector I is loaded into branch U6and bit i1of information bit-vector I is loaded into branch U7.

In a second encoding operation, the polar encoder600calculates and outputs codeword bits from the first encoding branch subset605. In particular, encoding branch U6outputs codeword bit x6and encoding branch U7outputs codeword bit x7. In a third encoding operation, the polar encoder600loads a second subset of bits of the input vector into the second encoding branch subset610. For example, bit i2of information bit-vector I is loaded into branch U3, a frozen bit is loaded into branch U4, and bit i3of information bit-vector I is loaded into branch U5. Polar encoder600may thus output codeword bits x6and x7for transmission by a transmitter215prior to outputting other bits (e.g., x5, x4, and x3) of codeword X. Polar encoder600can do so because codeword bits x6and x7are independent of inputs to encoding branches of encoding branch subsets610,615that have a higher order. In some cases, the second and third encoding operations may be done concurrently (e.g., in a pipelined encoder where registers may capture the inputs/outputs of the encoder).

In a fourth encoding operation, polar encoder600calculates and outputs codeword bits from the second encoding branch subset610. In particular, branch U3outputs codeword bit x3, branch U4outputs codeword bit x4, branch U5outputs codeword bit x5. In a fifth encoding operation, polar encoder600loads a third subset of bits of the input vector into the third encoding branch subset615. In this case, the information bit-vector I does not have any further information bits and frozen bits are loaded into branches U0, U1, and U2. Polar encoder600may output codeword bit x3, x4and x5for transmission by a transmitter215prior to outputting x0, x1and x2of codeword X. Again, polar encoder600can do so because codeword bits x3, x4and x5only depend on bits loaded onto encoding branch subsets605and610, and are independent of inputs to encoding branches of encoding branch subset615that has a higher order. In some cases (e.g., piplelining), the fourth and fifth encoding operations are performed concurrently.

In a sixth encoding operation, the polar encoder600calculates and outputs codeword bits from the third encoding branch subset615. In particular, branch U0outputs codeword bit x0, branch U1outputs codeword bit x1, branch U2outputs codeword bit x2. Polar encoder600may output codeword bits x0, x1and x2.

The polar encoder600may thus be considered as having a constant input rate as two information bits from information bit-vector I may be received at a time during a particular operation in the encoding algorithm. The polar encoder600may be considered as having a variable output rate as two or three codeword bits may be output per operation. An operation as described herein designates an order in which operations are performed. An operation of an encoding algorithm may correspond to a particular cycle or set of cycles of a computer processor. In other examples, multiple operations of the encoding algorithm may be completed within a single cycle. As may be seen, the polar encoder600may output bits of codeword X at least at the same time as, and in some instances prior to, receiving a last of the subsets of the information bits from the information bit-vector. For example, if input vector includes frozen and information bits of an information bit-vector I, the polar encoder600encodes and outputs the information bits i0and i1prior to frozen bits being loaded into branches U0, U1, and U2.

By loading polar encoder600in such a manner, the polar encoder600may output a subset of bits from codeword X for transmission prior to loading all information bits of an input vector and prior to generating the entire codeword X. Thus, the encoder600may output the subset of codeword bits to a transmitter for transmitting the subset of codeword bits earlier than conventional techniques. For example, transmitter215may begin and/or complete transmitting a subset of one or more codeword bits before another subset of one or more codeword bits has been output by the polar encoder600. For example, transmitter215may transmit codeword bits x6and x7in a first symbol period, codeword bits x3, x4, and x5in a second symbol period, and codeword bits x0, x1, and x2in a third symbol period, where codeword bits x0, x1, and x2are not output by the encoder until at least after the first symbol period.

A polar encoder may configured to output bits at a constant rate.FIG. 7illustrates an example of a constant output rate polar encoder700for outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. Polar encoder700is an example of polar encoder210,300,300-a,500,600ofFIGS. 2-6.

Similar to the description provided above inFIG. 6, the information bit-vector I only includes the information bits (e.g., I=[i0, ii, i2, and i3]) to be encoded and does not include any frozen bits. In the depicted example, polar encoder700divides the encoding branches into four subsets based at least in part on encoding branch inter-dependencies. The first encoding branch subset705has the fewest inter-branch dependencies as encoding its input bits is independent of any other encoding branch subsets. The second encoding branch subset710has the next fewest inter-branch dependencies as encoding its input bits only depends on its input bits and the input bits to the first encoding branch subset705. The third encoding branch subset715has the next fewest inter-branch dependencies as encoding its input bits depends on its input bits and the inputs bits to both the first and second encoding branch subsets. The fourth encoding branch subset720has the most inter-branch dependencies as encoding its input bits depends on its input bits and the input bits to the first, second, and third encoding branch subsets.

As can be seen, outputs for each respective encoding branch subset are independent of inputs to encoding branches of encoding branch subsets having a higher order. In an example, encoding branch subset705is independent of inputs to higher order subsets710,715,720, and encoding branch subset710is independent of inputs to higher order subsets715,720. Below is a description of an encoding algorithm applied by constant output rate polar encoder700.

In a first encoding operation, the polar encoder700loads a first subset of bits of the input vector into the first encoding branch subset705. In particular, bit i0of information bit-vector I is loaded into branch U6and bit i1of information bit-vector I is loaded into branch U7.

In a second encoding operation, the polar encoder700calculates and outputs codeword bits from the first encoding branch subset705. In particular, branch U6outputs codeword bit x6, and branch U7outputs codeword bit x7. In a third encoding operation, the polar encoder700loads a second subset of bits of the input vector into the second encoding branch subset710. In particular, a frozen bit is loaded into branch U4, and bit i3of information bit-vector I is loaded into branch U5. In this example, polar encoder700may output codeword bits x6and x7prior to outputting other bits of codeword X. Polar encoder700can do so because codeword bits x6and x7do not depend on bits loaded to any of the other encoding branch subsets710,715,720having a higher order. In some cases, the second and third encoding operations may be done concurrently (e.g., in a pipelined encoder where registers may capture the inputs/outputs of the encoder).

In a fourth encoding operation, the polar encoder700calculates and outputs codeword bits from the second encoding branch subset710. In particular, branch U4outputs codeword bit x4and branch U5outputs codeword bit x5. In a fifth encoding option, the polar encoder700loads a third subset of bits of the input vector into the third encoding branch subset715. In particular, a frozen bit is loaded into branch U2, and information bit i2of information bit-vector I is loaded into branch U3. In this example, polar encoder700may output codeword bit x4and x5prior to outputting bits x2and x3of codeword X. Polar encoder700can do so because codeword bits x4and x5only depend on bits loaded into the first and second encoding branch subsets705and710, but do not depend on bits input to the third or fourth encoding branch subsets715,720having a higher order. In some cases, the fourth and fifth encoding operations may be done concurrently (e.g., a pipelined encoder).

In a sixth encoding operation, the polar encoder700calculates and outputs codeword bits from the third encoding branch subset715. In particular, branch U2outputs codeword bit x2and branch U3outputs codeword bit x3. In a seventh encoding operation, the polar encoder700loads a fourth subset of bits of the input vector into the fourth encoding branch subset720. In particular, frozen bits are loaded into branches U0and U1. In this example, polar encoder700may output codeword bits x2and x3prior to outputting bits x0and x1of codeword X. Polar encoder700can do so because codeword bits x2and x3only depend on bits loaded into the first, second, and third encoding branch subsets, but do not depend on bits input to the fourth encoding branch subset720having a higher order. In some cases, the sixth and seventh encoding operations may be done concurrently (e.g., a pipelined encoder).

In an eighth encoding operation, the polar encoder700calculates and outputs codeword bits from the fourth encoding branch subset720. In particular, branch U0outputs codeword bit x0and branch U1outputs codeword bit x1.

The polar encoder700performing the above algorithm is considered to provide a constant output rate as encoder700outputs two bits at each operation of the algorithm. The polar encoder700may be considered as having a variable input rate as differing numbers of information bits of an information bit-vector I may be input per operation. An operation of this encoding algorithm may be defined similarly as an operation of polar encoder600as described above. By loading polar encoder700using this encoding algorithm, the polar encoder700may output a subset of bits from codeword X for transmission prior to loading all input bits of information bit-vector I and prior to generating the entire codeword X. Thus, a transmitter215may receive from the encoder700and begin transmitting the subset of codeword bits earlier than conventional techniques. For example, transmitter215may transmit codeword bits x6and x7in a first symbol period, codeword bits x4and x5in a second symbol period, codeword bits x3and x2in a third symbol period, and codeword bits x0and x1in a fourth symbol period, where codeword bits x0and x1are not output by the encoder until at least after the first symbol period.

The principles described herein may be extended to encoders having any number of encoding branches. Similar to the discussion of an 8-bit encoder described above, an n-bit encoder may output bits of a codeword for transmission prior to loading all input bits of an input vector and prior to generating the entire codeword. In such an example, n may be a positive integer. The following description provides an example of when bits can be output for transmission from a 128-bit encoder.

FIG. 8illustrates an example of a table800for outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. Table800depicts the number of information bits required to transmit each corresponding block of 8 bits of data for a 128-bit codeword. A 128 branch polar encoder (e.g., U0to U127) may be used to generate a 128-bit codeword X (e.g., x0to x127). The table800indicates how many input information bits are required to output a particular 8-bit segment of the 128-bit code word, and table800may be read from left to right. The leftmost column of table800lists different code rates and the remaining columns list the number of input information bits required for a polar encoder to output a particular 8-bit segment of the 128-bit code word. For instance, the 128 branch polar encoder first calculates and outputs a first bit subset [x120, x127] of codeword X, then calculates and outputs a second bit subset [x112, x119] of codeword X bits, and so forth until a final bit subset [x0, x7] of codeword X is calculated and output.

Referring to the row of table800for the ⅙ code rate, the 128 branch polar encoder can output a first 8-bit segment that includes bits [x120, x127] of the 128-bit codeword as soon as the first 7 information bits are available and encoded by encoding branches U120to U127. The 128 branch polar encoder can output a second 8-bit segment that includes bits [x112, x119] of the 128-bit codeword as soon as 4 more additional information bits become available (e.g., a total of 11 information bits (7+4) have been received) and encoded by encoding branches U112to U119. The remainder of this row, as well the other rows, may be read in the same manner. Similar to the description provided above, a polar encoder may divide its encoding branches into ordered subsets where each subset is independent of inputs to encoding branches of encoding branch subsets having a higher order, encode bits on a subset by subset basis based at least in part on the order, and output codeword bits from encoding branch subset prior to outputting bits from another encoding branch subsets having a higher order.

The techniques described herein are applicable to bit-reversed polar encoders.FIG. 9illustrates an example of a bit-reversed polar encoder900for outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. Polar encoder900has encoding branches with bit-reversed indices, which may be compared to encoding branches of the polar encoders shown inFIGS. 3-7that are in a natural index order. An index refers to the number assigned to a particular encoding branch. An index progressing in sequential order from top to bottom is referred to as a natural index. The polar encoders shown inFIGS. 3-7are considered to be in a natural index order as the index of each encoding branch increases sequentially starting with U0at the top, and increasing by 1 until bottom branch U7is reached.

Bit-reversal refers to the process of reordering encoding branches of an encoder. Instead of proceeding in sequential order from top to bottom, the indices are rearranged and operations are performed in a bit-reversed order. To give an example, the indices are considered to be a p-digit binary code where p is a positive integer. For an 8 bit encoder (e.g., 23), p is 3 where 0 in decimal is represented a 000 in binary, and 7 in decimal is represented by 111 in binary. Bit-reversal means that the bits in a binary representation of an index are reversed. For example, performing bit-reversal on binary number 011 (3 in decimal) is 110 (6 in decimal).

As depicted, encoding branches U of bit-reversed polar encoder900are arranged using bit-reversed indices and are in the following order from top to bottom: U0, U4, U2, U6, U1, U5, U3, and U7. In other words, binary number 000 of the top branch is bit-reversed to yield 000 (0 in decimal) after bit-reversal, binary number 001 of the branch second from the top is bit-reversed to yield 100 (4 in decimal), and so forth. Similar to the description ofFIG. 6, bits of input bit-vector I may be loaded into bit-reversed polar encoder900in generally bottom to top order (see arrow920), and bit-reversed polar encoder900may output bits of codeword C in bottom to top order (see arrow925).

Bit-reversal may have multiple advantages. In one example, bit-reversal may lead to simpler memory access in a decoder. Bit-reversal may also enable a decoder to start a decoding algorithm as soon as the decoder receives two log likelihood ratio (LLR) values.

A polar encoder in accordance with the examples described herein having bit-reversed indices also has improved encoder latency as compared to conventional techniques.FIG. 10illustrates an example of a bit-reversed encoder1000for outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. In this example, information bits of an information bit-vector may be input at a constant rate, similar to the description above ofFIG. 6. The principles may also applied a polar encoder having a constant output rate as described inFIG. 7. In theFIG. 6example, an input vector may include frozen bits, information bits, or both, as described above. Similar to the description ofFIG. 6, bits of an input vector may be loaded into bit-reversed polar encoder1000in generally bottom to top order (see arrow1020), and bit-reversed polar encoder1000may output bits of codeword C in bottom to top order (see arrow1025). In the depicted example, the input vector may include an information bit-vector I, which may include one or more information bits (e.g., I=[i0, i1, i2, and i3]). As shown, information bits i0, i1, i2, and i3are input to encoding branches U3, U5, U6, U7.

Bit-reversed polar encoder1000divides encoding branches into three subsets based at least in part on inter-branch encoding dependencies. The first encoding branch subset1005has the fewest inter-branch dependencies as encoding its input bits is independent of any other encoding branch subsets. The second encoding branch subset1010has the next fewest inter-branch dependencies as encoding its input bits only depends on the input bits to the first and second encoding branch subsets1005and1010. The third encoding branch subset1015has the most inter-branch dependencies as encoding its input bits depends on input bits to the first, second, and third encoding branch subsets. As can be seen, outputs for each encoding branch subset are independent of inputs to encoding branches of encoding branch subsets having a higher order. In an example, encoding branch subset1005is independent of inputs to higher order subsets1010,1015, and encoding branch subset1010is independent of inputs to higher order subset1015. Below is a description of an encoding algorithm applied by bit-reversed polar encoder1000.

In a first encoding operation, polar encoder1000loads a first subset of bits of the input vector into the first encoding branch subset1005. In particular, bit i0of information bit-vector I is loaded into branch U3and bit i1of information bit-vector I is loaded into branch U7.

In a second encoding operation, the polar encoder1000calculates and outputs codeword bits from the first encoding branch subset1005. In particular, branch U3outputs codeword bit c6and branch U7outputs codeword bit c7. In a third decoding operation, the polar encoder loads a second subset of bits of the input vector into the second encoding branch subset1010. In particular, bit i2of information bit-vector I is loaded into branch U6, a frozen bit is loaded into branch U1, and bit i3of information bit-vector I is loaded into branch U5. Polar encoder1000may output codeword bits c6and c7prior to outputting other bits of codeword C. Polar encoder1000can do so because codeword bits c6and c7do not depend on bits loaded to any of the other encoding branch subsets having a higher order. In some cases, the second and third encoding operations may be done concurrently (e.g., a pipelined encoder).

In a fourth encoding operation, the polar encoder1000calculates and outputs codeword bits from the second encoding branch subset1010. In particular, branch U6outputs codeword bit c3, branch U1outputs codeword bit c4, and branch U5outputs codeword bit c5. In a fifth encoding operation, the polar encoder1000loads a third subset of bits of the input vector into the third encoding branch subset1015. In particular, frozen bits are loaded into branches U0, U4, and U2. Polar encoder1000may output codeword bit c3, c4and c5prior to outputting c0, c1and c2of codeword C. Polar encoder1000can do so because codeword bits c3, c4and c5only depend on bits loaded into the first and second encoding branch subsets1005and1010, but do not depend on bits input to the third encoding branch subset1015of higher order. In some cases, the fourth and fifth encoding operations may be done concurrently (e.g., a pipelined encoder).

In a sixth encoding operation, the polar encoder1000calculates and outputs codeword bits from the third encoding branch subset1015. In particular, branch U0outputs codeword bit c0, branch U4outputs codeword bit c1, and branch U2outputs codeword bit c2.

The polar encoder1000may thus be considered as having a constant input rate as two information bits of an information bit-vector may be received at a time during a particular operation in the encoding algorithm. An operation of an encoding algorithm may correspond to one or more cycles of a computer processor as described above inFIG. 6. By loading polar encoder1000in such a manner, the polar encoder1000may output a subset of bits from codeword X for transmission prior to all information bits of an information bit-vector I being available and prior to generating the entire codeword X. Thus, the encoder1000may output a subset of bits from a codeword X to a transmitter215earlier than conventional techniques. Transmitter215may begin and/or complete transmitting the subset of bits of the codeword before a second or final subset of bits of the codeword has been output by the polar encoder1000.

FIG. 11illustrates an example of a table1100for outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. The encoding algorithm using bit-reversed indexing, as described herein, is not limited to providing early transmission of 8-bit codewords. Table1100indicates the number of information bits required to transmit each corresponding block of 8 bits of data for a 128-bit codeword.FIG. 11is similar to the table shown inFIG. 8and is set up in the same manner. As can be seen, bit-reversed encoding may provide a more balanced distribution of information bits across the columns of the table1100. In comparing table800and table1100, more information bits in table800are encoded in the higher bits of the 128-bit code word (e.g., bit x64and above) than in the lower bits. Table1100, by comparison, distributes more information bits into the lower bits of the 128-bit code word (e.g., bit x63and below).

Advantageously, the examples described herein provide for a linear block encoder that outputs a subset of bits of a codeword for transmission prior to all input bits being available and prior to generating the entire codeword, thus resulting in reduced encoder latency. Further advantageously, a transmitter may receive the codeword bit subsets from the encoder and begin transmitting codeword bits before an entire codeword is generated. Thus, the examples described herein permit a transmitter to begin transmitting bits of a codeword sooner than in conventional techniques. Also beneficially, information and frozen bits are introduced sequentially to be encoded causally before an entire information bit-vector is processed (e.g., the information bit-vector could be available but prior to a first decoding operation, but decoding operations may be processed in a causal manner that allows earlier transmission of at least some codeword bits). For example, codeword bits may be split across two or more symbols, where a first subset of codeword bits are transmitted prior to the encoder completing processing for all bits of the codeword.

The bit-reversed polar encoder may also output codeword bits in sets that provide for simplified memory access by a decoder.FIG. 12illustrates an example of a bit-reversed polar encoder1200for outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. The bit-reversed polar encoder1200may encode output codeword bits in a manner that simplifies decoding by a decoder. In this example, input indices of the encoding branches may be bit-reversed and output indices of codeword bits output from the encoding branches may be in a sequential order. For comparison,FIG. 5depicts a non-bit-reversed encoder having input and output indices in sequential order with lower index values depicted at the top encoding branch and sequentially increasing toward the bottom encoding branch. As seen inFIG. 12, the input indices of the encoding branches are bit-reversed (e.g., 000 is bit-reversed to 000, 001 is bit-reversed to 100, 010 is bit-reversed to 010, 011 is bit-reversed to 110, and so forth) whereas the output indices of the codeword bits are in sequential order that increase from top to bottom.

The bit-reversed polar encoder1200may output sets of codeword bits c from subsets of encoding branches U corresponding to values of bit-reversed indices of the encoding branches U. In an example, codeword bits c generated by encoding branches U having higher index values are output prior to codeword bits c generated by encoding branches U having lower index values. Reliability metrics may be calculated for the encoding branches, and the encoding branches may be ordered by the calculated reliability metrics. A reliability metric may represent a likelihood of a decoder encountering a decoding error when decoding a codeword bit encoded by a particular encoding branch. The reliability metric may be used for selecting in which encoding branch to input a bit for encoding. The reliability metric may be calculated based on, for example, a polarization weight or density evolution function. In some examples, the frozen bits may be input into the encoding branches having lower reliability while the information bits are input into the encoding branches having higher reliability. In the example shown inFIG. 12, frozen bits are loaded into encoding branches U0, U1, U2, and U4, and information bits i0, i1, i2, and i3are loaded into encoding branches U3, U5, U6, and U7for encoding.

In the depicted example, encoding branches of the bit-reversed polar encoder1200are divided into two subsets, as seen by a first type of dashed line1205defining a first subset having encoding branches U0to U3and a second type of dashed line1210defining a second subset having encoding branches U4to U7. Each bit-reversed index value of the encoding branches of the second subset has a higher number than any bit-reversed index value of the encoding branches of the first subset. For example, the bit-reversed index values for the encoding branches of the second subset range from 4 to 7, and the bit-reversed index values for the encoding branches of the first subset range from 0 to 3. The codeword bits c1, c3, c5, and c7are generated by encoding branches U4to U7, and the codeword bits c0, c2, c4, and c6are generated by encoding branches U0to U3. The bit-reversed polar encoder1200may output codeword bits c1, c3, c5, and c7generated by encoding branches U4to U7of the first subset prior to outputting codeword bits c0, c2, c4, and c6generated by encoding branches U0to U3of the second subset. As can been seen inFIG. 12, codeword bits c0, c2, c4, and c6are dependent on codeword bits c1, c3, c5, and c7and input bits to encoding branches U0to U3, and codeword bits c1, c3, c5, and c7are independent of codeword bits c0, c2, c4, and c6and bits input to encoding branches U0to U3. As depicted inFIG. 12, codeword bits of the first subset of encoding branches are interleaved with codeword bits output by the second subset of encoding branches.

Outputting codeword bits, for a bit-reversed polar encoder1200having input and output bit locations bit-reversed from each other, in subsets that correspond to the order of the input bits may simplify decoding of the codeword bits by a decoder. The decoder performs the reverse operation as polar encoder1200and decodes received codeword bits c in the order of the index values of the encoding branches U. The decoder may look like the polar encoder1200with all of the arrows pointed in the opposite direction. During decoding, the codeword bits may be input on the right and the decoded codeword bits may be output at locations U0to U7. Thus, a bit at location U0may be decoded first because it relies on the other codeword bits, followed by a bit at location U1, then bit location U2, and so forth in sequential order to bit location U7

Decoding is simplified as the decoder may decode received codeword bits in subsets that correspond to the sequential, bit-reversed index order of the encoding branches U. In an example, the polar encoder1200may generate a subset of codeword bits c1, c3, c5, and c7corresponding to outputs from encoding branches U4to U7and output the subset of codeword bits c1, c3, c5, and c7(e.g., transmit the codeword bits c1, c3, c5, and c7via a wireless communication channel). Subsequently, the polar encoder1200may generate a subset of codeword bits c0, c2, c4, and c6corresponding to outputs from encoding branches U0to U3and output the subset of codeword bits c0, c2, c4, and c6(e.g., transmit the codeword bits c0, c2, c4, and c6via a wireless communication channel). A decoder may first receive the subset of codeword bits c1, c3, c5, and c7and then receive the subset of codeword bits c0, c2, c4, and c6. The decoder may decode the received codeword bits in an order that corresponds to sequential, increasing index values of the encoding branches U. Specifically, the received codeword bits c may be decoded in the following order: c0, c4, c2, c6, c1, c5, c3, and c7, which respectively correspond to encoding branches U0, U1, U2, U3, U4, U5, U6, and U7. Other than having to store a first subset of codeword bits c1, c3, c5, and c7while waiting for receipt of a second subset of codeword bits c0, c2, c4, and c6, this decoding process simplifies memory access by storing codeword bits in a subsets where the decoder does not have to jump back and forth between the subsets of codeword bits during the decoding process. For instance, the subset of codeword bits c0, c2, c4, and c6corresponds to encoding branches U0to U3and may be decoded prior to decoding any of the codeword bits c1, c3, c5, and c7in the other subset. In contrast, if, for instance, the first subset included codeword bit c1that corresponds to encoding branch U4and the second subset included codeword bit c6that corresponds to encoding branch U3, the decoder would have to decode codeword bit c6before decoding codeword bit c1, which results in more complicated memory access.

In some examples, error detecting codes may be used to protect bits input to respective subsets of the encoding branches U of the polar encoder1200. The error detecting codes may be independent of one another thereby simplifying decoding, as described below. In an example, a bit-reversed polar encoder may have a bit length N, and the N encoding branches (having bit reversed indexes) may be divided into M branch subsets, each branch subset having N/M encoding branches. In an example, a first subset of information bits of an information bit-vector and a first error detecting code (e.g., a cyclic redundancy check) generated from the first subset of information bits may be loaded into information bit locations of the encoding branches of a first branch subset, which may be selected as the highest M bit-reversed indexes. The output bits from the M encoding branches of the first branch subset may be generated and transmitted in a first transmission interval. Subsequently, a second subset of information bits of the information bit-vector and a second error detecting code (e.g., a cyclic redundancy check) generated from the first subset of the information bits, the second subset of the information bits, or both the first and second subsets of the information bits, may be loaded into information bit locations of the encoding branches of a second branch subset, which may be selected as the next-highest M bit-reversed indexes. The second error detecting code may be based on multiple subsets of information bits and may operate as a further check that both the first and second subsets are properly decoded. The output bits from the M encoding branches of the second branch subset may be generated and transmitted in a second transmission interval. The process may be repeated N/M times until all N bits of the codeword have been generated and transmitted.

The decoder may first receive potentially corrupted versions of the subsets of codeword bits associated with each branch subset. The decoder may decode the N bits of the codeword to recover the input bits (e.g., including information bits and error detecting code bits). As described above, the decoder may perform the decoding operation starting at the lowest bit-reversed index and proceeding generally (e.g., some bits may be decoded in parallel if not dependent on each other) in order of increasing bit-reversed index. As the input bits for each branch subset are decoded, the decoder may apply an error detecting algorithm to the decoded subsets of bits associated with each branch subset. If the calculated and received error detecting codes match for a given set of recovered input bits, the decoder determines that the decoding operation was successful and continues decoding further sets of bits. If they don't match, the decoder can indicate a decoding error for the given set of recovered input bits.

Advantageously, the decoder can process a first subset of information bits of an information bit-vector encoded by a first subset of encoding branches that have an error detecting code that is independent of an error detecting code generated for a second (or subsequent) subset of received information bits of the information bit-vector encoded by a second (or subsequent) subset of encoding branches. The error detecting codes do not depend on one another, and a decoding error identified by one error detecting code is independent of a decoding error identified by another error detecting code. Thus, each subset of information bits of the information bit-vector is protected by a separate error detecting code. Decoding each subset of bits independently with its own error detecting code reduces coding gain of the codeword, but allows independent decoding of subsets of bits of the codewords that may be transmitted in different transmission intervals (e.g., symbol periods, etc.).

The techniques for using separate error detecting codes for subsets of encoding branches described with reference to the bit-reversed polar encoder1200may also be applied to a non-bit-reversed polar encoder. For example, a non-bit-reversed polar encoder (or other device) may group, into subsets, codeword bits generated by encoding branches with indices having adjacent numbers, without any gaps between the adjacent numbers within a particular subset, and may communicate each of the subsets (e.g., via a wireless communication channel) to a decoder. Because the codeword bits in each subset are generated by encoding branches with indices having adjacent numbers, the decoder can decode codeword bits in a current subset without having to jump back and forth to decode codeword bits from a one or more different subsets before completing decoding bits of a current subset.

FIG. 13shows a block diagram1300of a wireless device1305that supports outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. Wireless device1305may be an example of aspects of a user equipment (UE)115or base station105as described with reference toFIG. 1. Wireless device1305may include receiver1310, encoding component1315, and transmitter1320. Wireless device1305may also include a processor. Each of these components may be in communication with one another (e.g., via one or more buses).

Receiver1310may receive a signal including information such as packets, user data, or control information associated with various information channels (e.g., control channels, data channels, etc.). The receiver1310may process (e.g., downconvert, filter, perform analog-to-digital conversion, etc.) and pass information on to other components of the device. The receiver1310may be an example of aspects of the transceiver1635described with reference toFIG. 16.

Encoding component1315may be an example of aspects of the encoding component1515described with reference toFIG. 15.

Encoding component1315may divide a plurality of encoding branches into at least a first encoding branch subset and a second encoding branch subset, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset. Encoding component1315may generate first and second subsets of output bits of a codeword in first and second encoding operations. In some cases, the generating may include inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset. Encoding component1315may output the first subset of output bits prior to outputting the second subset of output bits.

Transmitter1320may transmit signals generated by other components of the device. In some cases, the transmitter1420may transmit the first subset of output bits prior to transmitting the second subset of output bits. In some cases, the transmitter1320may transmit at least some, or all, of the first subset of output bits prior to transmitting any of, some of, or all of the second subset of output bits. In some examples, the transmitter1320may be collocated with a receiver1310in a transceiver module. For example, the transmitter1320may be an example of aspects of the transceiver1635described with reference toFIG. 16. The transmitter1320may include a single antenna, or it may include a set of antennas.

FIG. 14shows a block diagram1400of a wireless device1405that supports outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. Wireless device1405may be an example of aspects of a wireless device1305or a UE115or base station105as described with reference toFIGS. 1 and 12. Wireless device1405may include receiver1410, encoding component1415, and transmitter1420. Wireless device1405may also include a processor. Each of these components may be in communication with one another (e.g., via one or more buses).

Receiver1410may receive a signal including information such as packets, user data, or control information associated with various information channels (e.g., control channels, data channels, etc.). The receiver1410may process (e.g., downconvert, filter, perform analog-to-digital conversion, etc.) and pass information on to other components of the device. The receiver1410may be an example of aspects of the transceiver1635described with reference toFIG. 16.

Encoding component1415may be an example of aspects of the encoding component1515described with reference toFIG. 15. Encoding component1415may also include Divider Component1425and Branch Subset Encoder1430.

Divider Component1425may divide a plurality of encoding branches into at least a first encoding branch subset and a second encoding branch subset, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset.

Branch Subset Encoder1430may generate first and second subsets of output bits of a codeword in first and second encoding operations. In some cases, the generating may include inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset. Branch Subset Encoder1430may output the first subset of output bits prior to outputting the second subset of output bits.

Transmitter1420may transmit signals generated by other components of the device. In some cases, the transmitter1420may transmit the first subset of output bits prior to transmitting the second subset of output bits. In some cases, the transmitter1320may transmit at least some, or all, of the first subset of output bits prior to transmitting any of, some of, or all of the second subset of output bits. In some examples, the transmitter1420may be collocated with a receiver1410in a transceiver module. For example, the transmitter1420may be an example of aspects of the transceiver1635described with reference toFIG. 16. The transmitter1420may include a single antenna, or it may include a set of antennas.

FIG. 15shows a block diagram1500of an encoding component1515that supports outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. The encoding component1515may be an example of aspects of an encoding component1315or an encoding component1415described with reference toFIGS. 13, and 14. The encoding component1515may include Divider Component1520, Branch Subset Encoder1525, Bit Loader Component1530, Code Rate Determiner1535, and Bit Reverser Component1540. Each of these modules may communicate, directly or indirectly, with one another (e.g., via one or more buses).

Divider Component1520may divide the plurality of encoding branches into at least a first encoding branch subset and a second encoding branch subset, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset.

Branch Subset Encoder1525may generate first and second subsets of output bits of a codeword in first and second encoding operations, the generating comprising inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset. Branch Subset Encoder1525may output the first subset of output bits prior to outputting the second subset of output bits.

In some cases, generating the first and second subsets of output bits of the codeword in first and second encoding operations includes: inputting a first subset of the information bits of the information bit-vector and a first error detecting code generated from the first subset of the information bits to encoding branches of the first encoding branch subset for generating the first subset of output bits, and inputting a second subset of the information bits of the information bit-vector and a second error detecting code generated from the first subset of the information bits, the second subset of the information bits, or both the first and second subsets of the information bits, to encoding branches of the second encoding branch subset for generating the second subset of output bits. In some cases, each of the subsets, including the first and second subsets, of output bits have a same number of bits. In some cases, the first subset of output bits has a different number of bits than the second subset of output bits. In some cases, the information bits of the information bit-vector for generating the codeword may be received at a constant rate or a variable rate. In some cases, the encoder is a linear block encoder. In some cases, the linear block encoder is one of a polar code encoder, a Reed-Muller (RM) encoder, a polar RM encoder, a systematic encoder, and a bit-reversed encoder.

Bit Loader Component1530may receive a first of a plurality of subsets of bits from an information bit-vector prior to receiving a last of the plurality of subsets of the bits from the input vector. In some cases, the outputting of the first subset of output bits is performed prior to receiving of the last of the plurality of subsets of the information bits from the information bit-vector.

Code Rate Determiner1535may determine a code rate for encoding by selecting a number of frozen bits for input to the set of encoding branches.

Bit Reverser Component1540may perform bit-reversal on input indices of the plurality of encoding branches relative to corresponding output indices of the plurality of encoding branches prior to the dividing of the plurality of encoding branches. In some cases, a first subset of the bit-reversed indices correspond to the first encoding branch subset and a second subset of the bit-reversed indices correspond to the second encoding branch subset, and where each bit-reversed index in the first subset of the bit-reversed indices has a higher number than each bit-reversed index in the second subset of the bit-reversed indices. In some cases, the first subset of output bits correspond to a first subset of the output indices of the set of encoding branches and the second subset of output bits correspond to a second subset of the output indices of the set of encoding branches, and where the first subset of the output indices and the second subset of the output indices are interleaved with each other. In some cases, the second subset of output bits is dependent on the first subset of output bits and bits input to the second encoding branch subset.

FIG. 16shows a diagram of a system1600including a device1605that supports outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. Device1605may be an example of or include the components of wireless device1305, wireless device1405, or a UE115as described above, e.g., with reference toFIGS. 1, 12 and 13. Device1605may include components for bi-directional voice and data communications including components for transmitting and receiving communications, including UE encoding component1615, processor1620, memory1625, software1630, transceiver1635, antenna1640, and I/O controller1645. These components may be in electronic communication via one or more busses (e.g., bus1610). Device1605may communicate wirelessly with one or more base stations105.

Processor1620may include an intelligent hardware device, (e.g., a general-purpose processor, a digital signal processor (DSP), a central processing unit (CPU), a microcontroller, an application-specific integrated circuit (ASIC), an field-programmable gate array (FPGA), a programmable logic device, a discrete gate or transistor logic component, a discrete hardware component, or any combination thereof). In some cases, processor1620may be configured to operate a memory array using a memory controller. In other cases, a memory controller may be integrated into processor1620. Processor1620may be configured to execute computer-readable instructions stored in a memory to perform various functions (e.g., functions or tasks supporting outputting of codeword bits for transmission prior to loading all input bits).

Memory1625may include random access memory (RAM) and read only memory (ROM). The memory1625may store computer-readable, computer-executable software1630including instructions that, when executed, cause the processor to perform various functions described herein. In some cases, the memory1625may contain, among other things, a basic input/output system (BIOS) which may control basic hardware and/or software operation such as the interaction with peripheral components or devices.

Software1630may include code to implement aspects of the present disclosure, including code to support outputting of codeword bits for transmission prior to loading all input bits. Software1630may be stored in a non-transitory computer-readable medium such as system memory or other memory. In some cases, the software1630may not be directly executable by the processor but may cause a computer (e.g., when compiled and executed) to perform functions described herein.

In some cases, the wireless device may include a single antenna1640. However, in some cases the device may have more than one antenna1640, which may be capable of concurrently transmitting or receiving multiple wireless transmissions.

I/O controller1645may manage input and output signals for device1605. I/O controller1645may also manage peripherals not integrated into device1605. In some cases, I/O controller1645may represent a physical connection or port to an external peripheral. In some cases, I/O controller1645may utilize an operating system such as iOS®, ANDROID®, MS-DOS®, MS-WINDOWS®, OS/2®, UNIX®, LINUX®, or another known operating system.

FIG. 17shows a diagram of a system1700including a device1705that supports outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. Device1705may be an example of or include the components of wireless device1305, wireless device1405, or a base station105as described above, e.g., with reference toFIGS. 1, 13 and 14. Device1705may include components for bi-directional voice and data communications including components for transmitting and receiving communications, including base station encoding component1715, processor1720, memory1725, software1730, transceiver1735, antenna1740, network communications manager1745, and base station communications manager1750. These components may be in electronic communication via one or more busses (e.g., bus1710). Device1705may communicate wirelessly with one or more UEs115.

Base station encoding component1715may divide the plurality of encoding branches into at least a first encoding branch subset and a second encoding branch subset, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset. Base station encoding component1715may generate first and second subsets of output bits of a codeword in first and second encoding operations, the generating comprising inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset. Base station encoding component1715may output the first subset of output bits prior to outputting the second subset of output bits.

Memory1725may include RAM and ROM. The memory1725may store computer-readable, computer-executable software1630including instructions that, when executed, cause the processor to perform various functions described herein. In some cases, the memory1725may contain, among other things, a BIOS which may control basic hardware and/or software operation such as the interaction with peripheral components or devices.

Software1730may include code to implement aspects of the present disclosure, including code to support outputting of codeword bits for transmission prior to loading all input bits. Software1730may be stored in a non-transitory computer-readable medium such as system memory or other memory. In some cases, the software1730may not be directly executable by the processor but may cause a computer (e.g., when compiled and executed) to perform functions described herein.

In some cases, the wireless device may include a single antenna1740. However, in some cases the device may have more than one antenna1740, which may be capable of concurrently transmitting or receiving multiple wireless transmissions.

Network communications manager1745may manage communications with the core network (e.g., via one or more wired backhaul links). For example, the network communications manager1745may manage the transfer of data communications for client devices, such as one or more UEs115.

FIG. 18shows a flowchart illustrating a method1800for outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. The operations of method1800may be implemented by a UE115or base station105or its components as described herein. For example, the operations of method1800may be performed by an encoding component as described with reference toFIGS. 13 through 15. In some examples, a UE115or base station105may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the UE115or base station105may perform aspects the functions described below using special-purpose hardware.

At block1805the UE115or base station105may divide a plurality of encoding branches into at least a first encoding branch subset and a second encoding branch subset, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset. The operations of block1805may be performed according to the methods described with reference toFIGS. 1 through 12. In certain examples, aspects of the operations of block1805may be performed by a Divider Component as described with reference toFIGS. 13 through 15.

At block1810the UE115or base station105may generate first and second subsets of output bits of a codeword in first and second encoding operations, the generating comprising inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset. The operations of block1810may be performed according to the methods described with reference toFIGS. 1 through 12. In certain examples, aspects of the operations of block1810may be performed by a Branch Subset Encoder as described with reference toFIGS. 13 through 15.

At block1815the UE115or base station105may output the first subset of output bits prior to outputting the second subset of output bits. The operations of block1815may be performed according to the methods described with reference toFIGS. 1 through 12. In certain examples, aspects of the operations of block1815may be performed by a Branch Subset Encoder as described with reference toFIGS. 13 through 15.

FIG. 19shows a flowchart illustrating a method1900for outputting of codeword bits for transmission prior to loading all input bits in accordance with one or more aspects of the present disclosure. The operations of method1900may be implemented by a UE115or base station105or its components as described herein. For example, the operations of method1900may be performed by an encoding component as described with reference toFIGS. 13 through 15. In some examples, a UE115or base station105may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the UE115or base station105may perform aspects the functions described below using special-purpose hardware.

At block1905the UE115or base station105may perform bit-reversal on input indices of a plurality of encoding branches relative to corresponding output indices of the plurality of encoding branches prior to dividing of the plurality of encoding branches. The operations of block1905may be performed according to the methods described with reference toFIGS. 1 through 12. Block1905is shown using a dashed line as it is optional and may be skipped. In certain examples, aspects of the operations of block1905may be performed by a Bit Reverser Component as described with reference toFIGS. 13 through 15.

At block1910the UE115or base station105may divide the plurality of encoding branches into at least a first encoding branch subset and a second encoding branch subset, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset. The operations of block1910may be performed according to the methods described with reference toFIGS. 1 through 12. In certain examples, aspects of the operations of block1910may be performed by a Divider Component as described with reference toFIGS. 13 through 15.

At block1915the UE115or base station105may generate first and second subsets of output bits of a codeword in first and second encoding operations, the generating comprising inputting information bits of an information bit-vector and at least one frozen bit into respective encoding branches of the plurality of encoding branches and generating the first subset of output bits using the first encoding branch subset prior to generating the second subset of output bits using the second encoding branch subset. The operations of block1915may be performed according to the methods described with reference toFIGS. 1 through 12. In certain examples, aspects of the operations of block1915may be performed by a Branch Subset Encoder as described with reference toFIGS. 13 through 15.

At block1920the UE115or base station105may output the first subset of output bits prior to outputting the second subset of output bits. The operations of block1920may be performed according to the methods described with reference toFIGS. 1 through 12. In certain examples, aspects of the operations of block1920may be performed by a Branch Subset Encoder as described with reference toFIGS. 13 through 15.

FIG. 20shows a flowchart illustrating a method2000for outputting of codeword bits for transmission prior to generating entire codeword in accordance with various aspects of the present disclosure. The operations of method2000may be implemented by a UE115or base station105or its components as described herein. For example, the operations of method2000may be performed by a communications manager as described with reference toFIGS. 13 through 15. In some examples, a UE115or base station105may execute a set of codes to control the functional elements of the device to perform the functions described below. Additionally or alternatively, the UE115or base station105may perform aspects of the functions described below using special-purpose hardware.

At block2005the UE115or base station105may perform bit-reversal on input indices of a plurality of encoding branches relative to corresponding output indices of the plurality of encoding branches prior to dividing of the plurality of encoding branches. The operations of block2005may be performed according to the methods described with reference toFIGS. 1 through 12. Block2005is shown using a dashed line as it is optional and may be skipped. In certain examples, aspects of the operations of block2005may be performed by a Bit Reverser Component as described with reference toFIG. 15.

At block2010the UE115or base station105may divide the plurality of encoding branches into at least a first encoding branch subset and a second encoding branch subset, outputs of the first encoding branch subset being independent of inputs to the second encoding branch subset. The operations of block2010may be performed according to the methods described with reference toFIGS. 1 through 12. In certain examples, aspects of the operations of block2010may be performed by a Divider Component as described with reference toFIGS. 13 through 15.

At block2015the UE115or base station105may input a first subset of information bits of an information bit-vector and a first error detecting code generated from the first subset of the information bits to encoding branches of the first encoding branch subset for generating a first subset of output bits, and input a second subset of the information bits of the information bit-vector and a second error detecting code generated from the first subset of the information bits, the second subset of the information bits, or both the first and second subsets of the information bits, to encoding branches of the second encoding branch subset for generating a second subset of output bits. The operations of block2015may be performed according to the methods described with reference toFIGS. 1 through 12. In certain examples, aspects of the operations of block2015may be performed by a Branch Subset Encoder as described with reference toFIGS. 13 through 15.

At block2020the UE115or base station105may output the first subset of output bits prior to outputting the second subset of output bits. The operations of block2015may be performed according to the methods described with reference toFIGS. 1 through 12. In certain examples, aspects of the operations of block2020may be performed by a Bit Reverser Component as described with reference toFIGS. 13 through 15.

It should be noted that the methods described above describe possible implementations, and that the operations may be rearranged or otherwise modified and that other implementations are possible. Furthermore, aspects from two or more of the methods may be combined.