Wiring board, semiconductor apparatus and method of manufacturing them

There are provided steps of providing a dielectric layer and a wiring layer on a surface of a support to form an intermediate body, removing the support from the intermediate body to obtain a wiring board, and carrying out a roughening treatment over a surface of the support before the intermediate body forming step.

TECHNICAL FIELD

The present disclosure relates to a wiring board to be used in a semiconductor apparatus or a semiconductor package and a method of manufacturing the wiring board. More particularly, the present disclosure relates to a wiring board formed by using a support for a reinforcement in a manufacturing process to provide an insulating layer and a wiring layer on the support through a build-up method and then removing the support and a method of manufacturing the wiring board. Furthermore, the present disclosure relates to a semiconductor apparatus formed by using a wiring board formed through the same method and a method of manufacturing the semiconductor apparatus.

RELATED ART

A support is used for a reinforcement in a manufacture of a wiring board. As the related art of the case in which the wiring board is thus manufactured by using the support, there has been known a method of manufacturing a wiring board in which a dielectric layer (an insulating layer or a solder resist layer) and a wiring layer are provided on a surface of the support to form an intermediate body and the support is removed from the intermediate body to obtain the wiring board.

FIGS. 1 and 2show an example in which a semiconductor device is provided on the wiring board obtained by the manufacturing method and a semiconductor apparatus is thus obtained. InFIG. 1, a wiring board (a multilayer wiring board or a semiconductor package)10is formed by alternately providing a wiring layer10band an insulating layer10cto be a dielectric layer through a build-up method and a solder resist layer11is formed on an uppermost layer and a lowermost layer, for example. An electrical connection of the wiring layers10bbetween the respective layers is carried out through a via portion penetrating the insulating layer10c.

FIG. 2shows a semiconductor device mounting portion in the semiconductor apparatus ofFIG. 1in detail. The solder resist layer11is provided on the uppermost layer of the wiring board10and an opening portion is formed in a predetermined position of the solder resist layer11, and a connecting pad17to be electrically connected to the wiring layer10bof the wiring board10through a via is formed on the opening portion.

A semiconductor device13is provided on the wiring board10through a flip-chip bonding. In this case, a solder is provided on the connecting pad17of the wiring board through an application of a solder paste, for example. Subsequently, a semiconductor device13having a bump14formed on a terminal is positioned on the connecting pad17, and the solder16and the bump14are molten to electrically connect the semiconductor device13to the connecting pad17. Then, a liquid underfill resin12is filled and cured between the semiconductor device13and the solder resist layer11of the wiring board10.

For the related art related to the invention, the following documents have been known. The wiring board (the semiconductor apparatus) shown as the related-art examples inFIGS. 1 and 2has been described in the following Patent Document 1 and Patent Document 2, and particularly, corresponds to a multilayer wiring board according to embodiments inFIG. 1(a first embodiment) andFIG. 9(a ninth embodiment) in the Patent Document 2.

According to the Patent Document 1 (Japanese Patent Unexamined Application Publication No. 2000-323613), it has been disclosed that a via for electrically connecting a conductor wiring and/or a pad which is formed on both sides of an insulating layer is formed to penetrate an insulator and is formed as a recess portion taking a shape of a truncated cone and having an opening area opened on an external connecting terminal side which is larger than a bottom area on a semiconductor device mounting surface side in order to form a mounting surface on which the semiconductor device is to be mounted as flatly as possible and to reduce a thickness as greatly as possible in a multilayer board for a semiconductor apparatus. Moreover, it has been disclosed that a seed layer is formed between a metal plate and a pad for a semiconductor device in order to enhance an adhesion between the pad for the semiconductor device and a metal plate.

In the Patent Document 2 (Japanese Patent Unexamined Application Publication No. 2007-13092), moreover, it has been disclosed that a first solder resist layer is formed on a support substrate, a first opening portion is formed on the first solder resist layer, a semiconductor device mounting electrode is formed on the first opening portion, an insulating layer is formed on the electrode, and a wiring portion to be connected to the electrode is formed on the insulating layer, and subsequently, a second solder resist layer is formed in a wiring portion and a second opening portion is formed on the second solder resist layer in order to obtain a wiring board in which a thickness can be reduced and which can correspond to a high density wiring. It has been disclosed that a support is removed to obtain a wiring board.

As described above, for example, according to the semiconductor apparatus in accordance with the related art shown inFIGS. 1 and 2, in some cases in which a surface of the solder resist layer11on a surface of the wiring board10which is provided in contact with the support is set to be a mounting surface27of the semiconductor device13, the surface of the solder resist layer11is excessively flattened and a wettability of the solder resist layer11is insufficient. In this case, there is a possibility that a void15might be generated in the underfill resin12as shown inFIG. 2and peeling might be caused between the underfill resin12and the solder resist layer11to be a dielectric layer. To the contrary, in the case in which the wettability of the solder resist layer11is excessively sufficient, the underfill resin12excessively flows over the wiring board10. Consequently, a defective appearance of a finished semiconductor package is generated.

As described above, in the wiring board (the semiconductor apparatus) shown in the related art ofFIGS. 1 and 2, the dielectric layer (the insulating layer and the solder resist layer) and the wiring layer are simply provided on the support to form an intermediate body and the support is removed from the intermediate body to obtain the wiring board. In general, a surface of a metal plate or a metal foil which is not subjected to any processing is very flat. In some cases in which the metal plate or the metal foil is used as the support and a surface of the wiring board from which the support is removed is set to be the semiconductor device mounting surface, therefore, the surface of the solder resist layer is excessively flat. Accordingly, the wettability of the solder resist layer and the underfill resin is insufficient so that the void is generated in the underfill resin.

The related art described in the Patent Documents 1 and 2 is the same as the related-art examples shown inFIGS. 1 and 2as described above. Also in the wiring board (the semiconductor apparatuses) described in the Patent Documents 1 and 2, accordingly, the same problem as that in the related-art examples shown inFIGS. 1 and 2is caused.

SUMMARY

Exemplary embodiments of the present invention provide a method of manufacturing the wiring board and a semiconductor apparatus which can adjust a wettability between an underfill resin and an insulating layer or a solder resist layer which serves as a semiconductor device mounting surface by setting the semiconductor device mounting surface as a roughened surface, and particularly, can control a flowability of the underfill resin when filling the underfill resin, thereby forming the underfill resin well so as to prevent a void from being generated, and the wiring board and the semiconductor apparatus which are manufactured by the method.

Moreover, exemplary embodiments of the present invention a method of manufacturing a wiring board and a semiconductor apparatus which can enhance an adhesion between a support and an insulating layer or a solder resist layer in a manufacture and can prevent a generation of a defect such as sudden peeling of the support and the wiring board during the manufacture by setting, as a roughened surface, a surface of a support on which the wiring board (an intermediate body) is to be formed in the case in which the insulating layer and a wiring layer are provided on the support to form the wiring board, and the wiring board and the semiconductor apparatus which are manufactured by the method.

A method of manufacturing a wiring board according to the invention includes steps of carrying out a roughening treatment over a surface of a support; providing a dielectric layer and a wiring layer on the surface of the support subjected to the roughening treatment to form an intermediate body, and removing the support from the intermediate body to obtain the wiring board.

In the specification of the application, an insulating layer or a solder resist layer, or a layer obtained by adding the insulating layer and the solder resist layer will be referred to as a “dielectric layer”. Moreover, the dielectric layer (the insulating layer and the solder resist layer) and the wiring layer which are provided on the support immediately before the removal of the support will be referred to as an “intermediate body”.

Moreover, the method of manufacturing a semiconductor apparatus according to the invention includes steps of carrying out a roughening treatment over a surface of a support; providing a dielectric layer and a wiring layer on the surface of the support subjected to the roughening treatment to form an intermediate body, removing the support from the intermediate body to obtain the wiring board, and mounting a semiconductor device on a surface of the wiring board from which the support is removed.

Furthermore, the method of manufacturing a semiconductor apparatus according to the invention includes steps of carrying out a roughening treatment over a surface of a support; providing a dielectric layer and a wiring layer on the surface of the support subjected to the roughening treatment to form an intermediate body, removing the support from the intermediate body to obtain the wiring board, and mounting a semiconductor device on an opposed surface to a surface of the wiring board from which the support is removed.

Moreover, the method of manufacturing a semiconductor apparatus according to the invention includes steps of carrying out a roughening treatment over a surface of a support, providing a dielectric layer and a wiring layer on the surface of the support subjected to the roughening treatment to form an intermediate body, mounting a semiconductor device on a surface of the intermediate body which is opposed to a contact surface with the support, and removing the support from the intermediate body to obtain the semiconductor apparatus.

In the method of manufacturing a wiring board or a semiconductor apparatus according to the invention, furthermore, the support is formed of a metal and the roughening treatment is carried out over the surface of the support by etching, thereby forming a roughened surface. Alternatively, the support is formed of a metal and an oxide film is provided by an oxidizing treatment to carry out the roughening treatment over the surface of the support, thereby forming a roughened surface.

Further, in the method of manufacturing a wiring board or a semiconductor apparatus according to the invention, before or after carrying out the roughening treatment over the surface of the support, a connecting pad is formed on the surface of the support, and then the intermediate body is formed on the surface of the support provided with the connecting pad.

The invention provides a wiring board comprising a dielectric layer and a wiring layer, wherein one surface of the wiring board serves as a semiconductor device mounting surface and the other surface which is opposed to the surface of the wiring board serves as an external connecting terminal surface, and wherein a surface of the dielectric layer of the semiconductor device mounting surface or the external connecting terminal surface is formed as a roughened surface.

Moreover, the invention provides a semiconductor apparatus comprising:

a wiring board having a dielectric layer and a wiring layer, wherein one surface of the wiring board serves as a semiconductor device mounting surface and the other surface which is opposed to the surface of the wiring board serves as an external connecting terminal surface, and wherein a surface of the dielectric layer of the semiconductor device mounting surface is formed as a roughened surface;

a semiconductor device mounted on the semiconductor device mounting surface through a flip-chip bonding; and

an underfill resin filled between the semiconductor device and the semiconductor device mounting surface.

Furthermore, the invention provides a semiconductor apparatus comprising:

a wiring board having a dielectric layer and a wiring layer, wherein one surface of the wiring board serves as a semiconductor device mounting surface and the other surface which is opposed to the surface of the wiring board serves as an external connecting terminal surface, and wherein a surface of the dielectric layer of the external connecting terminal surface is formed as a roughened surface; and

a semiconductor device mounted on the semiconductor device mounting surface.

As described above, according to the invention, the roughening treatment is carried out before the dielectric layer or the wiring layer is formed on the surface of the support. Therefore, it is possible to adjust the wettability between the underfill resin and the insulating layer or the solder resist layer (that is, the dielectric layer). In particular, the flowability of the liquid underfill resin in filling of the underfill resin is controlled so that a void can be prevented from being generated in the underfill resin. Accordingly, it is possible to fill the underfill resin well between the semiconductor device and the wiring board.

By setting the surface of the support to be the roughened surface, moreover, it is possible to enhance an adhesion of the support and the insulating layer or the solder resist layer (the dielectric layer) during the manufacture. Consequently, it is possible to prevent the support and the wiring board from being suddenly peeled in the manufacture. Accordingly, it is possible to prevent a manufacturing defect of the wiring board or the semiconductor apparatus from being generated.

According to the related art shown inFIG. 2, particularly, prior to the mounting of the semiconductor device, it is necessary to roughen the surface of the solder resist layer11through etching such as a plasma processing or a desmear processing after removing the support in order to prevent the void15from being generated in the underfill resin12. On the other hand, according to the invention, it is possible to transfer the surface shape of the roughened surface of the support onto the surface of the solder resist layer by roughening the surface of the support. Accordingly, it is not necessary to carry out a special roughening treatment for the solder resist layer in order to prevent the void from being generated in the underfill resin.

Other features and advantages may be apparent from the following detailed description, the accompanying drawings and the claims.

DETAILED DESCRIPTION

Embodiments according to the invention will be described below in detail with reference to the accompanying drawings.

FIGS. 3A to 4Dshow a method of manufacturing a wiring board according to a first embodiment of the invention in order of steps. InFIG. 3A, a support20is prepared. For the support20, a metal plate formed of Cu or a metal foil formed of Cu in the same manner is generally used, for example. In case of a copper foil formed of Cu, a rolled copper foil or an electrolytic copper foil is suitably used.

A surface treatment for roughening a surface of the support20forming an insulating layer23is carried out at a subsequent step. Examples of a surface treatment include etching, oxidation, plating and blasting. As will be described below, in the examples according to the invention, there is carried out a so-called roughening treatment for carrying out soft etching (wet etching) by spraying an ammonium persulfate solution onto the surface of the support20.FIG. 3Bshows a surface20aof the support20which is changed into a very small concavo-convex surface through the execution of the roughening treatment.

Next, electrolytic plating is carried out. More specifically, inFIG. 3C, a plated resist layer21is formed on a surface of a support20and is subjected to patterning by an ordinary method. Examples of a patterning method include a pattern forming method using screen printing and a pattern forming method using a photolithographic process. In case of the photolithographic process, a mask (not shown) having a plurality of openings in a predetermined position is utilized to carry out exposure and development, thereby removing the plated resist layer21in the exposed portion to form a large number of opening portions21a.

As shown inFIG. 3D, next, electrolytic plating is carried out by setting the support20itself as one of electrodes. For the electrolytic plating in this case, an Au plated layer22aand an Ni plated layer22bare formed on the opening portion21aof the plated resist21to obtain a plated layer22. In the case in which a semiconductor device is provided by a flip-chip method at a subsequent step, the plated layer22is used as a connecting pad to be connected to an electrode terminal of the semiconductor device or is used as a connecting pad of an external connecting terminal. For the plated layer, however, it is possible to provide layers in a combination of /Ni/Cu, Au/Pd/Ni/Cu, and Ni/Cu in order from the support20side. InFIG. 3E, next, the plated resist layer21is removed.

As shown inFIG. 3F, then, a resin film constituted by an epoxy resin or a polyimide resin is provided on a whole surface of the support20on which the plated layer22constituted by the Au plated layer22aand the Ni plated layer22bis formed. Thus, an insulating layer23is formed as a dielectric layer. In this case, the roughening treatment is previously carried out over the surface20aof the support20. Therefore, an adhesion between the support20and the insulating layer23is maintained to be high and a reinforcing function in a process for manufacturing the wiring board is sufficiently fulfilled, and furthermore, troubles are not made in the case in which the support20is removed at a subsequent step.

InFIG. 4A, thereafter, a via hole24to be an opening portion is formed to penetrate the insulating layer23through a laser processing to aim at the plated layer22provided on the support20. The via hole24takes a shape of an inverted truncated cone having a larger area on the opening portion side than an area on a bottom side. Consequently, the plated layer22is exposed to a bottom surface of the via hole24. InFIG. 4B, next, a wiring layer25constituted by a via and a pattern is formed as a metal layer covering a region including the bottom surface and wall surface of the via hole24through a semiadditive method. Consequently, the wiring layer25is electrically connected to the plated layer22provided in contact with the support20through the via portion.

As shown inFIG. 4C, similarly, the respective steps of forming the insulating layer23(FIG. 3E), forming the via hole24(FIG. 4A) and forming the wiring layer25(FIG. 4B) are repeated at a necessary number of times for forming a predetermined multilayer wiring board. Then, the insulating layer23and the wiring layer25which are uppermost layers are covered to form a solder resist26serving as a dielectric layer and patterning is thus carried out. As a patterning method, in the same manner as described above, a mask (not shown) having an opening in a corresponding position to a conductor pad25afor an external connecting terminal is utilized to carry out exposure and development, thereby removing the solder resist26in the exposed portion and forming an opening portion26ato expose the conductor pad25afor an external connecting terminal of the wiring layer25to be the uppermost layer. Thus, a wiring board (a multilayer wiring board or a semiconductor package) is formed on the support20and the wiring board set into a state in which the support20is not removed is referred to as an “intermediate body”40in this specification.

As shown inFIG. 4D, next, the support20is removed by etching. Consequently, a surface of the multilayer wiring board from which the support20is removed serves as a semiconductor device mounting surface27for mounting a semiconductor device. On the other hand, as described above, a surface of the multilayer wiring board from which the conductor pad25afor an external connecting terminal of the wiring layer25to be the uppermost layer serves as an external connecting terminal surface28. Thus, there is finished a wiring board (a multilayer wiring board or a semiconductor package)42having the semiconductor device mounting surface on one surface and the external connecting terminal surface on the other surface.

In this case, a surface shape of a roughened surface20aof the support20is transferred onto the insulating layer23of the semiconductor device mounting surface27so that the semiconductor device mounting surface27serves as a roughened surface23a.

FIG. 5shows a state in which a semiconductor device30is mounted on the semiconductor device mounting surface27of the wiring board42which is finished through the steps shown inFIGS. 3A to 4D. InFIG. 5, the finished wiring board42shown inFIG. 4Dis vertically inverted and the semiconductor device mounting surface27is set to be an upper side. In order to mount the semiconductor device30on the wiring board42, an electrode of the semiconductor device30and the connecting pad17on the wiring board side are electrically connected to each other through a flip-chip method and an underfill resin31is filled between the semiconductor device30and the wiring board. In the case in which the semiconductor device30is mounted on the wiring board (semiconductor package)42through a flip-chip bonding, for example, a solder is provided on the connecting pad17of the wiring board42through an application of the solder paste16, and subsequently, the semiconductor device30having the bump14formed on a terminal is positioned on the connecting pad17, and the solder16and the bump14are molten to electrically connect the semiconductor device30to the connecting pad17. Then, an underfill resin31is filled and cured between the semiconductor device30and the wiring board (the insulating layer or the solder resist layer)42.

In this case, a flow of the underfill resin31can be controlled by the roughened surface23a. Accordingly, the underfill resin31can be filled well so as not to generate a void.

Next, a method of manufacturing a wiring board according to a second embodiment of the invention will be described in order of steps with reference toFIGS. 6 to 7B. In the second embodiment, the steps described with reference toFIGS. 3A to 3Fin the first embodiment are exactly executed and the steps shown inFIGS. 4A and 4Bare executed. More specifically, inFIG. 6, a via hole24is formed on an insulating layer23through a laser processing to aim at a plated layer22provided on a support20, the plated layer22is exposed to a bottom surface of the via hole24, and furthermore, a wiring layer25constituted by a via and a pattern is formed by a semiadditive method, for example, in the same manner as in the step ofFIG. 4A. Consequently, the wiring layer25is electrically connected to the plated layer22provided in contact with the support20through the via portion.

Subsequently, a solder resist26is formed on the insulating layer23and the wiring layer25and is subjected to patterning. As a patterning method, for example, a mask (not shown) having an opening in a corresponding position to a conductor pad25aof the wiring layer25is utilized to carry out exposure and development, thereby removing the solder resist26in the exposed portion and forming an opening portion26ato expose the conductor pad25aof the wiring layer25. A plated layer33constituted by Au plating and Ni plating is formed on the conductor pad25athrough nonelectrolytic plating. A composition of the plated layer22in this case can also be obtained in another combination in the same manner as in the case shown inFIG. 3C.

As shown inFIG. 7A, next, the support20is removed by etching. Consequently, a surface of the wiring board from which the support20is removed serves as an external connecting terminal surface28, for example. In this case, a surface23aof an insulating layer forming the external connecting terminal surface28is a roughened surface. On the other hand, as described above, a side on which the connecting pad33formed by the plated layer is provided on the conductor pad25aof the wiring layer25serves as a semiconductor device mounting surface27. Thus, there is finished a wiring board having the semiconductor device mounting surface27on one surface and the external connecting terminal surface28on the other surface. As a typical example of the case in which a surface of the wiring board from which the support20is removed is set to be the external connecting terminal surface28, for instance, it is possible to propose the case in which the wiring board is used as an interposer. In this case, an underfill resin (not shown) is filled between the external connecting terminal surface28of the wiring board serving as the interposer and a mounting substrate (not shown).

InFIG. 7B, a semiconductor device30is mounted on the semiconductor device mounting surface27of the wiring board and an electrode terminal of an upper surface of the semiconductor device30and the connecting pad33of the wiring board are connected to each other through a bonding wire34, and a region including the semiconductor device30and the bonding wire34is sealed with a resin35.

As shown inFIGS. 8A and 8B, alternatively, the semiconductor device30is mounted on the semiconductor device mounting surface27of the wiring board to which the support20is attached and the electrode terminal of the upper surface of the semiconductor device30and the connecting pad33of the wiring board are connected to each other through the bonding wire34, and the region including the semiconductor device30and the bonding wire34is sealed with the resin35in a state in which the support20has not been removed, that is, as shown inFIG. 6. After the resin sealing is carried out, the support20is removed by etching so that a semiconductor apparatus provided with the semiconductor device30is finished. In this case, in the same manner as inFIG. 7A, the surface23aof the insulating layer forming the external connecting terminal surface28is roughened.

FIGS. 9A to 10Dshow a method of manufacturing a wiring board according to a third embodiment of the invention in order of steps. Description will be given to only different portions from the first embodiment shown inFIGS. 3A to 4D. Steps shown inFIGS. 9A to 9Care the same as the steps shown inFIGS. 3A to 3C.

The third embodiment (FIGS. 9A to 11) is characterized in that a solder resist is first formed on a support20. Accordingly, a manufacturing process according to the third embodiment is different from that in the first embodiment. More specifically, a support20is prepared inFIG. 9A, a roughened surface20ais formed inFIG. 9Band a solder resist layer29is formed inFIG. 9C.

Subsequently, a plated layer22constituted by an Au plated layer22aand an Ni plated layer22bis formed on an opening portion29aof the solder resist layer29as shown inFIG. 9D, and an insulating layer23is formed on the solder resist layer29and the plated layer22as shown inFIG. 9E.

InFIG. 10A, thereafter, a via hole24to be an opening portion is formed to penetrate the insulating layer23through a laser processing to aim at the plated layer22provided on the support20. The via hole24takes a shape of an inverted truncated cone having a larger area on the opening portion side than an area on a bottom side. Consequently, the plated layer22is exposed to a bottom surface of the via hole24. InFIG. 10B, next, a wiring layer25constituted by a via and a pattern is formed as a metal layer covering a region including the bottom surface and wall surface of the via hole24by a semiadditive method, for example. Consequently, the wiring layer25is electrically connected to the plated layer22provided in contact with the support20through the via portion.

As shown inFIG. 10C, similarly, the respective steps of forming the insulating layer23, forming the via hole24and forming the wiring layer25are repeated at a necessary number of times for forming a predetermined multilayer wiring board. Then, the insulating layer23and the wiring layer25which are uppermost layers are covered to form a solder resist26serving as a dielectric layer and patterning is carried out. Thus, there is formed an “intermediate body”40in which a wiring board (a multilayer wiring board or a semiconductor package) is provided on the support20.

As shown inFIG. 10D, next, the support20is removed by etching. Consequently, a surface of the multilayer wiring board from which the support20is removed serves as a semiconductor device mounting surface27for mounting a semiconductor device. On the other hand, as described above, a surface of the multilayer wiring board from which the conductor pad25afor an external connecting terminal of the wiring layer25to be the uppermost layer serves as an external connecting terminal surface28. Thus, there is finished a wiring board (a multilayer wiring board or a semiconductor package)42having the semiconductor device mounting surface27on one surface and the external connecting terminal surface28on the other surface.

In this case, a surface shape of a roughened surface20aof the support20is transferred onto the solder resist layer29of the semiconductor device mounting surface27so that the semiconductor device mounting surface27serves as a roughened surface29a.

FIG. 11shows a state in which a semiconductor device30is mounted on the semiconductor device mounting surface27of the wiring board42which is finished at the steps shown inFIGS. 9A to 10D. InFIG. 11, the wiring board42finished inFIG. 10Dis vertically inverted and the semiconductor device mounting surface27is shown as an upper side. A method of mounting the semiconductor device30on the wiring board42through a flip-chip bonding is the same as that in the first embodiment.

In the first and second embodiments, after the support20is subjected to the roughening treatment, the plated layer22(connecting pad) is formed. Therefore, the plated resist layer21is buried in the roughened surface of the support20, so that an adhesion between the plated resist layer21and the support20is improved. Further, the plating solution for the plated layer22does not flow into portions placed below the plated resist layer21, and thus, the plated layer22with a stable shape can be formed.

In the third embodiment, after the support20is subjected to the roughening treatment, the solder resist layer29is formed. Therefore, the solder resist layer29is buried in the roughened surface of the support20, so that an adhesion between the solder resist layer29and the support20is improved. Further, the plating solution for the plated layer22does not flow into portions placed below the solder resist layer29, and thus, the plated layer22with a stable shape can be formed. Further, since the adhesion between the solder resist layer29and the support20is improved, it is possible to prevent the intermediate body40and the support20from being peeled in the manufacturing process.

Further, in the first to third embodiments, after the roughened surface is formed on the support20, the plated layer22(connecting pad) is formed. Therefore, it is possible to prevent the plated layer22from being damaged by etching, etc, due to the roughening treatment of the support20. Therefore, the roughness degree of the support20can be adjusted while only considering the filling property of the underfill resin.

In order to perform the roughening treatment or removing treatment easily, the copper foil or copper plate is preferably used as the support20. The plated layer22(connecting pad) may be constituted by layers including a layer made of the same material as the support20, for example, by the combination of Au/Ni/Cu, Au/Pd/Ni/Cu, or Ni/Cu. In this case, it is preferable that the plated layer22is formed after the support20is subjected to the roughening treatment because the plated layer is not damaged by etching, etc. duce to the roughening treatment.

In a case where the surface of the plated layer22(connecting pad) is formed to be roughened surface, when the semiconductor chip is connected to the connecting pad by flip-chip bonding, the solder ball is mounted on the connecting pad, or the lead pin is soldered to the connecting pad, the gas vaporized from solder flux is discharged via a concave-convex portion of the roughened surface as a gas discharging path. Therefore, it is possible to prevent void by the gas from being generated within the solder. Thus, the solder bonding property is improved.

In the first to third embodiments, in order to improve an adhesion between the plated layer22and the insulating layer23, it is preferable that in the process betweenFIG. 3EandFIG. 3For the process betweenFIG. 9DandFIG. 9E, the surface of the plated layer22is subjected to the roughening treatment. For example, in the first embodiment, after the plated layer22is formed on the roughened surface of the support20(FIG. 3E,FIG. 17A), a roughening treatment is carried out over the surface of the plated layer22(FIG. 17B) so that the surface of the Ni plated layer22bbecomes a roughened surface122b. InFIG. 17B, an etching liquid which roughens only the Ni Plated layer22bis used in the roughening treatment. Next, the insulating layer23is formed on the whole surface of the support20on which the plated layer22is formed (FIG. 17C). After the insulating layer23is formed, the steps shown inFIGS. 4A to 5are executed. By this treatment, the insulating layer23is buried into the roughened surface of the plated layer22and thus, the adhesion between the plated layer22and the insulating layer23is improved. Herein, the same method as the roughening treatment of the support20is used for this roughening treatment of the plated layer22. In the first and second embodiments, if the plated layer22is subjected to the roughening treatment, the surface of the support20may be further subjected to the roughening treatment. Particularly, this becomes notably when the plated layer22(connecting pad) preferably includes a uppermost layer made of the same material as the support20, for example, the plated layer22is constituted by the combination of Au/Ni/Cu, Au/Pd/Ni/Cu, or Ni/Cu. In this case, by considering the increase of the roughness degrees by the roughening treatment of the plated layer22, the roughening treatment is carried out over the surface of the support20.

FIGS. 12A to 13Bshow a method of manufacturing a wiring board according to a fourth embodiment of the invention in order of steps. Description will be given to only different portions from the first embodiment shown inFIGS. 3A to 4D. In the fourth embodiment, before a roughening treatment is carried out over a surface of a support20, a plated resist layer21is formed on a surface of the support20and is subjected to patterning by an ordinary method as shown inFIG. 12B. Examples of a patterning method include a pattern forming method using screen printing and a pattern forming method using a photolithographic process. In case of the photolithographic process, a mask (not shown) having a plurality of openings in a predetermined position is utilized to carry out exposure and development, thereby removing the plated resist layer21in the exposed portion to form a large number of opening portions21a.

As shown inFIG. 12C, next, electrolytic plating is carried out by setting the support20itself as one of electrodes. For the electrolytic plating in this case, an Au plated layer22aand an Ni plated layer22bare formed on the opening portion21aof the plated resist21to obtain a plated layer22. Subsequently, the plated resist layer21is removed inFIG. 12D.

As shown inFIG. 12E, next, a surface treatment for roughening the surface of the support20is carried out. A surface treating method includes etching, oxidation, plating and blasting. As will be described below, in the example according to the invention, there is carried out a so-called roughening treatment for performing soft etching by spraying an ammonium persulfate solution onto the surface of the support20. The plated layer22formed on the surface of the support20before the roughening is not influenced by the roughening treatment. Accordingly, the plated layer22is maintained to be formed on a flat surface at the surface of the support20. More specifically, only the support20formed of copper is etched and a portion of the plated layer22formed of gold and nickel is not etched.

As shown inFIG. 13A, then, a resin film formed by an epoxy resin or a polyimide resin is provided over a whole surface of the support20having the plated layer22formed thereon. Consequently, an insulating layer23is formed. In this case, the roughening treatment is previously carried out over the surface20aof the support20. Therefore, an adhesion between the support20and the insulating layer23is maintained to be high and a reinforcing function in a process for manufacturing the wiring board is sufficiently fulfilled, and furthermore, troubles are not made in the case in which the support20is removed at a subsequent step. A via hole24to be an opening portion is formed to penetrate the insulating layer23through a laser processing to aim at the plated layer22provided on the support20. The via hole24takes a shape of an inverted truncated cone having a larger area on the opening portion side than an area on a bottom side. Consequently, the plated layer22is exposed to a bottom surface of the via hole24.

In the same manner as in the first embodiment, the respective steps of forming the insulating layer23, forming the via hole24and forming the wiring layer25are repeated at a necessary number of times for forming a predetermined multilayer wiring board. Then, the insulating layer23and the wiring layer25which are uppermost layers are covered to form a solder resist26and patterning is carried out. Thus, there is formed an “intermediate body”40in which a wiring board (a multilayer wiring board or a semiconductor package) is provided on the support20.

As shown inFIG. 13B, next, the support20is removed by etching. Consequently, a surface of the multilayer wiring board from which the support20is removed serves as a semiconductor device mounting surface27for mounting a semiconductor device. On the other hand, as described above, a surface of the multilayer wiring board from which the conductor pad25afor an external connecting terminal of the wiring layer25to be the uppermost layer serves as an external connecting terminal surface28. Thus, there is finished a wiring board (a multilayer wiring board or a semiconductor package)42having the semiconductor device mounting surface on one surface and the external connecting terminal surface on the other surface.

In this case, a surface shape of a roughened surface20aof the support20is transferred onto the insulating layer23of the semiconductor device mounting surface27so that the semiconductor device mounting surface27serves as a roughened surface23a.

FIG. 14shows a state in which a semiconductor device30is mounted on the semiconductor device mounting surface27of the wiring board42which is finished at the steps shown inFIGS. 12A to 13B. InFIG. 14, the wiring board42finished inFIG. 13Bis vertically inverted and the semiconductor device mounting surface27is shown as an upper side. The semiconductor device30is mounted on the wiring board42through a flip-chip bonding in the same manner as in the first embodiment.

As described above, in the fourth embodiment (FIGS. 12A to 14), the plated layer22serving as the connecting pad17is formed on the support20and the roughening treatment is then carried out over the support20. More specifically, the plated layer22is formed on the flat support20. For this reason, a back surface of the connecting pad17(an exposed surface from the insulating layer23) is not influenced by the roughening treatment. Accordingly, a surface of the connecting pad17is formed as a flat surface. Therefore, the roughening treatment can solder bond the semiconductor device in the same manner as the related-art art without influencing a solder bonding property of the connecting pad17when mounting the semiconductor device through the flip-chip bonding. More specifically, in the fourth embodiment, a degree of flatness of the surface of the connecting pad17mounting the semiconductor device is higher than that of the surface of the dielectric layer formed on the roughened surface as in the embodiment.

Table 1 shows a relationship between a wettability and a surface roughness over the surface of the wiring board according to the invention. Moreover,FIGS. 15 and 16show the relationship between a wettability and a surface roughness in charts. In the process for manufacturing the wiring board according to the invention, a wettability to the insulating layer23is regulated due to a roughness caused by roughening the surface of the support20. InFIGS. 15 and 16, “A” indicates the related-art example (1) “B” indicates the related-art example (2), “C” indicates the embodiment (1), “D” indicates the embodiment (2), “E” indicates the embodiment (3) and “F” indicates the embodiment (4). In the right upper corner ofFIGS. 15 and 16, “y” indicates a formula of an approximate straight line in the graph and “R2” indicates a matching degree between the appropriate straight line and measured values.

The related-art example (1) indicates the case in which any roughening treatment is not carried out over the surface of the solder resist layer11in the related-art example shown inFIG. 2. The related-art example (2) indicates the case in which a so-called desmear treatment is carried out as the roughening treatment over the surface of the solder resist layer11.

Moreover, the embodiment (1) indicates the case in which rolled copper foil is used as a material of the support20to obtain a wiring board by the support20subjected to the following blackening treatment (an oxidation treatment) for immersing a material into a blackening treatment solution (a mixed solution of sodium chlorite, sodium hydrate and sodium phosphate). Furthermore, the embodiments (2) and (3) and the comparative example indicate the cases in which electrolytic copper foil is used as the material of the support20to obtain the wiring board by the support20subjected to the following same roughening treatment.

Referring to the “roughening treatment”, a surface of the electrolytic copper foil to be the support20was subjected to etching (in this case, so-called soft etching) by spraying an ammonium persulfate solution so that a surface roughness shown in the Table 1 was obtained.

In the case in which the “roughening treatment” is carried out by a chemical method, it is possible to propose etching (soft etching) with a sulfuric acid-hydrogen peroxide based etchant, etching to be carried out by spraying the formic roughening treatment solution, etc., in addition to the etching to be carried out by spraying the ammonium persulfate solution. Moreover, the roughening method includes a method which is referred to as a blackening treatment (an oxidation treatment) for immersing a material into a blackening treatment solution (for example, a mixed solution of sodium chlorite, sodium hydrate and sodium phosphate). By the method, an oxide film (an oxide film formed of a metal to be a support) is formed on the surface of the support and is thus changed into a roughened surface. Alternatively, examples of a physical roughening treatment method include a sand blasting method. In addition, it is also possible to propose a method of carrying out nickel plating for forming a plated surface like a needle or copper plating to form recesses and projections.

As described above, various roughening treatments could be carried out. Herein, in the embodiments (2) and (3) and the comparative example, there was carried out only the “roughening treatment” for etching (soft etching) the surface of the electrolytic copper by spraying the ammonium persulfate solution. The roughness degrees for the embodiments (2) and (3) and the comparative example were changed respectively by changing the time of splaying the ammonium persulfate solution.

As shown in the Table 1 orFIGS. 15 and 16, in the related-art example, Ra (nm) and Rz (μm) are greater, a contact angle of the surface of the solder resist layer is smaller, and a wettability is more enhanced in the case in which the roughening treatment is carried out over the surface of the solder resist layer, that is, the related-art example (2) than those in the case in which the roughening treatment is not carried out, that is, the related-art example (1). In the embodiments (1) to (3) according to the invention and the comparative example, it is apparent that Ra (nm) and Rz (μm) are greater, the contact angle of the semiconductor device mounting surface (the roughened surface) is considerably reduced, a surface roughness of the wiring board is brought into a “rough” state and the wettability is regulated as compared with the related-art examples (1) and (2).

Further, as a result of various examinations, the inventors found that the wettablity of the insulating layer is insufficient if the contact angle is more than 100° and the wettablity of the insulating layer is excessively sufficient if the contact angle is equal to or less than 87.5°. Therefore, as shown in the Table 1 orFIGS. 15 and 16, the roughness degree of the roughened surface is preferably in a range of 300 nm≦Ra≦800 nm and 3.5 μm≦Rz≦7 μm.

The wettability is obtained by dripping a waterdrop onto a surface of a sample and measuring a contact angle of water.

As in the related-art example (2), thus, the roughening treatment has been carried out by a desmear for the solder resist layer in the related art. In the treatment, however, it is found that only an insufficient roughened surface is obtained. In the case in which the insulating layer serves as the semiconductor device mounting surface as in the embodiments shown inFIGS. 3 to 5, the roughening treatment using the desmear is harder than the treatment for the solder resist. In addition, in the case in which the desmear treatment is carried out, only the insufficient roughened surface is obtained. On the other hand, in the embodiment according to the invention, the support formed of a metal which can easily be subjected to the roughening treatment is used to carry out the roughening treatment over the support and to then transfer the surface shape of the roughened surface of the support onto the insulating layer and the solder resist layer. Irrespective of a material by which the semiconductor device mounting surface is formed, accordingly, the roughening can be performed well.

A general line for manufacturing the wiring board is provided with an etching device, an oxidizing (blackening) device and a plating device. In the invention, it is possible to carry out the roughening treatment for the support by utilizing the existing devices. Therefore, a new capital investment is not required so that a transition to execution is easy.

While the embodiments according to the invention have been described above with reference to the accompanying drawings, the invention is not restricted to the embodiments but various configurations, changes and modifications can be made without departing from the spirit or scope of the invention.

For example, in the embodiments according to the invention, there has been described only a wiring board (a semiconductor package) of an LGA (Land Grid Array) type in which a connecting pad itself exposed to an external connecting terminal surface serves as an external connecting terminal. It is a matter of course that the invention can also be applied to a wiring board (a semiconductor package) of a BGA (Ball Grid Array) type in which a solder ball is bonded to a connecting pad exposed to an external connecting terminal surface or a PGA (Pin Grid Array) type in which a pin is bonded to a connecting pad exposed to an external connecting terminal surface.

For example, the wiring board according to the second embodiment shown inFIGS. 6 to 8B, it is a matter of course that an insulating layer and a wiring layer may be formed as a multilayer to obtain a multilayer wiring board. In the semiconductor apparatus according to the second embodiment, moreover, the semiconductor device may be provided on the wiring board through the flip-chip bonding. In the second embodiment, particularly, it is also possible to employ a structure including the step inFIG. 9Eand a structure in which the roughening treatment for the support is carried out after the formation of the connecting pad as shown inFIG. 12Eas described in the third or fourth embodiment.

Although the copper foil or the copper plate is used as the support in the embodiments, moreover, it is also possible to use a stainless or aluminum foil or plate in addition to the materials.

As described above, according to the invention, there is included the step of carrying out the roughening treatment over the surface of the support. Therefore, the surface of the support subjected to the roughening treatment is transferred onto the insulating layer or the solder resist layer which serves as the semiconductor device mounting surface. Accordingly, there is carried out a regulation into a state in which a high wettability is obtained together with the underfill resin in the process for manufacturing a semiconductor apparatus. Consequently, it is possible to control a flowability of the underfill resin when filling the underfill resin, thereby preventing a void from being generated. Moreover, an adhesion between the support and the insulating layer or the solder resist during the manufacture can be enhanced. Consequently, it is possible to prevent the generation of a drawback that the support and the wiring board are suddenly peeled in the manufacture. Accordingly, quality can be enhanced and the invention can be widely applied as a wiring board or a semiconductor apparatus having the feature, for example, a semiconductor package including an MPU, a chip set and a memory or a coreless package such as a DLL3.