TRANSISTOR, MEMORY DEVICE AND MANUFACTURING METHOD OF MEMORY DEVICE

A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.

BACKGROUND

As the size of the integrated circuit keeps decreasing, the integration density of the component or device gradually increases. Semiconductor memory devices include volatile memories and non-volatile memories. For semiconductor memory devices, the increased memory cell density leads to compact structure designs with reduced sizes but maintaining the performance of the semiconductor memory devices.

DETAILED DESCRIPTION

FIG.1illustrates a cross-sectional view of a semiconductor device10in accordance with some embodiments. In some embodiments, the semiconductor device10is formed with integrated memory devices120and130. The semiconductor device10may include active devices110and memory devices120,130. The active devices110may be field effect transistor (FET) devices. In one embodiment, the active devices110are formed through the front-end-of-line (FEOL) manufacturing processes and include fin field effect transistors (FinFETs). The at least one of the memory devices120,130may include ferroelectric random access memory (FeRAM) devices formed through the back-end-of-line (BEOL) manufacturing processes. It is understood that FinFETs are used as examples, and other kinds of FEOL devices such as planar transistors or gate-all-around (GAA) transistors may be used herein and included within the scope of the present disclosure. That is, the memory devices120,130may be integrated with or in any suitable semiconductor devices. InFIG.1, the details of the memory devices120,130are not shown and further details will be described later in subsequent figures.

As illustrated inFIG.1, the semiconductor device10includes different regions for forming different types of circuits. For example, the semiconductor device10includes a first region102for forming logic circuits and a second region104for forming peripheral circuits, input/output (I/O) circuits, electrostatic discharge (ESD) circuits, and/or analog circuits. The semiconductor device10may also include other regions for forming other types of circuits which are fully intended to be included within the scope of the present disclosure. The semiconductor device10includes a substrate101. In some embodiments, the substrate101is a bulk substrate, such as a silicon substrate, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. In some embodiments, the substrate101includes other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. For example, additional electrical components, such as resistors, capacitors, inductors, diodes, or the like, is formed in or on the substrate101during the FEOL manufacturing processes.

As seen inFIG.1, the active devices110are formed on the substrate101, and isolation regions103, such as shallow trench isolation (STI) regions, are formed between or around the active devices110. In some embodiments, the active device110includes a gate electrode107and source and drain regions105and106. The gate electrode107may be formed over the substrate101with gate spacers108along sidewalls of the gate electrode107. The source and drain regions105and106such as doped or epitaxial source and drain regions are formed on opposing sides of the gate electrode107. In some embodiments, conductive contacts109, such as gate contacts and source/drain contacts, are formed over and electrically coupled to respective underlying electrically conductive features (e.g., gate electrodes107or source and drain regions105and106). In some embodiments, a dielectric layer116, such as an inter-layer dielectric (ILD) layer, is formed over the substrate101and covering the source and drain regions105and106, the gate electrode107and the contacts109, and other electrically conductive features, such as conductive interconnect structures including conductive vias112and conductive lines114, are embedded in the dielectric layer116. It is understood that the dielectric layer116may include more than one dielectric layers of the same or different dielectric materials. Collectively, the substrate101, the active devices110, the contacts109, conductive features112/114, and the dielectric layers116shown inFIG.1may be referred to as the front-end level12L.

Referring toFIG.1, dielectric layers118and dielectric layers122are formed over the dielectric layer116in alternation. In one embodiment, at least one of the dielectric layers118includes an etch stop layer (ESL). In some embodiments, the materials of the dielectric layers118is different from the materials of the dielectric layers116and122. In some embodiments, the material of the dielectric layer(s)118includes silicon nitride or carbide formed by plasma-enhanced physical vapor deposition (PECVD). In some embodiments, one or more of the dielectric layers118is omitted. In some embodiments, the dielectric layers116and122is formed of any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or low-k materials, formed by a suitable method, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or the like. InFIG.1, memory devices120and130, each of which may include a plurality of memory cells, are formed in the dielectric layer122and coupled to electrically conductive features (e.g., conductive vias124and conductive lines125) in the dielectric layer122.

InFIG.1, the memory devices120and130are formed at different layers of the dielectric layers122. The memory device120is formed at the lower layer, and the memory device130is formed at the upper layer. In some embodiments, the memory devices120and130have the same or similar structure. In some embodiments, the memory devices120and130have different structure designs. Although two layers of memory devices are depicted inFIG.1, other numbers of layers of memory devices, such as one layer, three layers, or more, are also possible and are encompassed within the scope of the present disclosure. Collectively, the layers of memory device120and130are referred to as the memory device level14L or a memory region of the semiconductor device10. The memory device level14L may be formed in the BEOL processes of semiconductor manufacturing. The memory devices120and130may be formed in the BEOL processes at any suitable locations within the semiconductor device10, such as over the first region102, over the second region104, or over a plurality of regions.

After the memory device level14L is formed, an interconnect level16L including electrically conductive interconnecting features (e.g., conductive vias126and conductive lines127) embedded in the dielectric layer(s)122is formed over the memory device level14L. Any suitable methods may be employed to form the interconnect level16L, and the details are not described herein. In some embodiments, the interconnect level16L is electrically connect the electrical components formed in/on the substrate101to form functional circuits. In some embodiments, the interconnect structure16L is also electrically coupled the memory devices120,130to the active devices110and/or the components in/on the substrate101. In addition, the memory devices120and130may be electrically coupled to an external circuit or an external device through the structure of the interconnect level16L. In some embodiments, the memory devices120and130are electrically coupled to the active devices110of the front-end level12L and/or other electrical components formed in the substrate101, and are controlled or accessed (e.g., written to or read from) by functional circuits of the semiconductor device10. Alternatively, the memory devices120,130are electrically coupled to (e.g., controlled or accessed) an external circuit of another semiconductor device through the structure of the interconnect level16L.

FIG.2AtoFIG.2Iare three dimensional views illustrating various stages of a manufacturing method of a memory device.FIG.3AtoFIG.3Iare cross-sectional views taken along cross section line I-I′ inFIG.2AtoFIG.2I.FIG.4Ais a perspective three dimensional view of a portion ofFIG.2H, andFIG.4Bis a cross-sectional view taken along cross section line II-II′ inFIG.4A. According to some embodiments, the memory device may be a three-dimensional (3D) memory device with a ferroelectric material. The memory devices depicted in the following paragraphs may be used as the memory devices120and130inFIG.1.

Referring toFIG.2AandFIG.3A, a semiconductor material202is formed on a dielectric layer200. In some embodiments, the dielectric layer200is the dielectric layer(s)122in the memory device level14L ofFIG.1, so the detailed description thereof is omitted herein. The dielectric layer200is formed over the front-end level12L. The dielectric layer200may be a single layer or multiple layers. In some embodiments, the dielectric layer200is also referred to as a buffer layer. A material of the dielectric layer200is not particularly limited, as long as said material renders good etching selectivity between the semiconductor material202and the dielectric layer200and between a semiconductor material208(described below) and the dielectric layer200. For example, the dielectric layer200is made of polyimide, epoxy resin, acrylic resin, phenol resin, BCB, PBO, silicon oxide, silicon nitride, or any other suitable polymer-based dielectric material.

In some embodiments, the semiconductor material202is made of a first conductive type oxide semiconductor material. The first conductive type is n-type or p-type. In some embodiments, the semiconductor material202includes n-type amorphous oxide semiconductor such as amorphous indium tungsten oxide (a-IWO), amorphous indium zinc oxide (a-IZO), amorphous indium-tungsten-zinc oxide (a-IWZO), amorphous indium-tin-zinc oxide (a-ITZO), amorphous indium tin oxide (a-ITO), amorphous indium oxide (a-InO) material, the like, or a combination thereof. In alternative embodiments, the semiconductor material202includes p-type oxide based material such as SnOx, CuxO (e.g., Cu2O, CuFeO2, Cu15Fe3O2), NiOx, Ni(Sn)O, the like, or a combination thereof. In some embodiments, the semiconductor material202is doped with a first conductive type dopant. For example, the semiconductor material202is doped with p-type dopants, such as boron, BF2, the like, or a combination thereof, or doped with n-type dopants, such as phosphorus, arsenic, the like, or a combination thereof. In some embodiments, the semiconductor material202includes IV element such as Ge, Si—Ge, Ge—Si, SiC or Ge—Sn, a compound such as GaN, GaAs, GaP, GaSb, InN, InAs, InSb, BN, BP, AlN, AlP, AlAs, AlSb, CdSe, CdS, CdTe, ZnS or ZnTe, 2D material such as graphene, MoS2, MoTe, MoSe, WSe2, WS2, h-BN or PbI2, the like, or a combination thereof. In some embodiments, an etching selectivity between the semiconductor material202and the dielectric layer200is high. For example, the etching selectivity between the semiconductor material202and the dielectric layer200ranges between 1:10 and 1:10000. Herein, the etching selectivity is denoted by a ratio between an etch rate of the semiconductor material202and the dielectric layer200. In some embodiments, the semiconductor material202is made of a single layer having one of the foregoing materials. However, the disclosure is not limited thereto. In some alternative embodiments, the semiconductor material202is made of a laminate structure of at least two of the foregoing materials. In some embodiments, the semiconductor material202is deposited on the dielectric layer200through ALD, CVD, PVD, or the like. In some embodiments, a thickness of the semiconductor material202is in a range of 0.5 nm to 10 nm.

Then, a conductive material204is formed on the semiconductor material202over the dielectric layer200. In some embodiments, the conductive material204includes cobalt, tungsten, copper, titanium, tantalum, aluminum, zirconium, hafnium, the like, a combination thereof, or other suitable conductive materials. In some embodiments, the conductive material204is formed through CVD, ALD, plating, or other suitable deposition techniques. In some embodiments, a barrier layer (not shown) is optionally formed between the conductive material204and the semiconductor material202, so as to avoid diffusion of atoms between elements. The barrier layer includes, for example, TiN, TaN, TiSiN, TaSiN, WSiN, TiC, TaC, TiAlC, TaAlC, TiAlN, TaAlN, or a combination thereof.

Referring toFIG.2BandFIG.3B, the conductive material204is patterned, to form a plurality of source and drain electrodes206A and206B. For example, portions of conductive material204are removed to expose the underlying semiconductor material202. In some embodiments, the conductive material204is patterned through a lithography process and an etching process by using a mask. The lithography process includes, for example, photoresist coating, soft baking, exposing, post-exposure baking (PEB), developing, and hard baking. The etching process includes, for example, an anisotropic etching process such as dry etch or an isotropic etching process such as wet etch.

One of the source and drain electrodes206A and206B is a source electrode (e.g., source electrode206A), and the other of the source and drain electrodes206A and206B is a drain electrode (e.g., drain electrode206B), and vice versa. In some embodiments, the source and drain electrodes206A and206B are physically separated from each other. In some embodiments, the adjacent source and drain electrodes206A and206B arranged along a direction D1are paired, and thus are also referred to as a pair of source and drain electrodes206A and206B. In some embodiments, plural pairs of source and drain electrodes206A and206B are arranged in an array having a plurality of rows R arranged along the direction D1and a plurality of columns C arranged along a direction D2substantially perpendicular to the direction D1. For example, each row R of the array has plural pairs of source and drain electrodes206A and206B arranged along the direction D2, and each column of the array has plural pairs of source and drain electrodes206A and206B arranged along the direction D1. The direction D1and the direction D2are, for example, substantially perpendicular to a stacking direction D3of the dielectric layer200, the semiconductor material202and the source and drain electrodes206A and206B. For example, the direction D1is x-direction, the direction D2is y-direction, and the direction D3is z-direction. The source and drain electrodes206A and206B cover portions of the semiconductor material202while portions of the semiconductor material202between the source and drain electrodes206A and206B are exposed. In some embodiments, the source electrodes206A are also referred to as source lines, and the drain electrodes206B are also referred to as bit lines.

Referring toFIG.2CandFIG.3C, a semiconductor material208is formed over the semiconductor material202, to cover the source and drain electrodes206A and206B and the exposed semiconductor material202. In some embodiments, the semiconductor material208has the same material of the semiconductor material202. In alternative embodiments, the semiconductor material208has different material from the semiconductor material202as long as they have the same conductive type. In some embodiments, the semiconductor material208is made of a first conductive type oxide semiconductor material. The first conductive type is n-type or p-type. In some embodiments, the semiconductor material208includes n-type amorphous oxide semiconductor such as amorphous indium tungsten oxide (a-IWO), amorphous indium zinc oxide (a-IZO), amorphous indium-tungsten-zinc oxide (a-IWZO), amorphous indium-tin-zinc oxide (a-ITZO), amorphous indium tin oxide (a-ITO), amorphous indium oxide (a-InO) material, the like, or a combination thereof. In alternative embodiments, the semiconductor material208includes p-type oxide based material such as SnOx, CuxO (e.g., Cu2O, CuFeO2, Cu15Fe3O2), NiOx, Ni(Sn)O, the like, or a combination thereof. In some embodiments, the semiconductor material208is doped with a first conductive type dopant. For example, the semiconductor material208is doped with p-type dopants, such as boron, BF2, the like, or a combination thereof, or doped with n-type dopants, such as phosphorus, arsenic, the like, or a combination thereof. In some embodiments, the semiconductor material208includes IV element such as Ge, Si—Ge, Ge—Si, SiC or Ge—Sn, a compound such as GaN, GaAs, GaP, GaSb, InN, InAs, InSb, BN, BP, AlN, AlP, AlAs, AlSb, CdSe, CdS, CdTe, ZnS or ZnTe, 2D material such as graphene, MoS2, MoTe, MoSe, WSe2, WS2, h-BN or PbI2, the like, or a combination thereof. In some embodiments, an etching selectivity between the semiconductor material208and the dielectric layer200is high. For example, the etching selectivity between the semiconductor material208and the dielectric layer200ranges between 1:10 and 1:10000. Herein, the etching selectivity is denoted by a ratio between an etch rate of the semiconductor material202and the dielectric layer200. In some embodiments, the semiconductor material208is made of a single layer having one of the foregoing materials. However, the disclosure is not limited thereto. In some alternative embodiments, the semiconductor material208is made of a laminate structure of at least two of the foregoing materials. In some embodiments, the semiconductor material208is deposited on the dielectric layer200through ALD, CVD, PVD, or the like. In some embodiments, a thickness of the semiconductor material208is in a range of 0.5 nm to 10 nm.

In some embodiments, the semiconductor material208is conformally formed on the source and drain electrodes206A and206B and the exposed semiconductor material202. For example, the semiconductor material208is continuously disposed on and in direct contact with all exposed surfaces of the source and drain electrodes206A and206B and the semiconductor material202. In some embodiments, the semiconductor material208surrounds the source and drain electrodes206A and206B.

Referring toFIG.2D,FIG.2E,FIG.3DandFIG.3E, portions of the semiconductor materials202and208between the source and drain electrodes206A and206B are removed. In some embodiments, the semiconductor materials202and208are partially removed through an etching process by using a patterned photoresist layer210. In some embodiments, as shown inFIG.2DandFIG.3D, the patterned photoresist layer210is formed on the semiconductor material208, to cover the source and drain electrodes206A and206B and regions respectively between a pair of source and drain electrodes206A and206B. As shown inFIG.2D, the patterned photoresist layer210may cover plural pairs of source and drain electrodes206A and206B in the same row R, and expose the semiconductor material208between adjacent rows R. For example, as shown inFIG.3D, sidewalls211sof the patterned photoresist layer210are substantially flush with sidewalls209sof the semiconductor material208.

Then, as shown inFIG.2EandFIG.3E, by using the patterned photoresist layer210as a mask, portions of the semiconductor materials202and208are removed, to form a semiconductor layer212A, a semiconductor layers212B and a semiconductor nanosheet214. In some embodiments, the semiconductor layer212A surrounds one of a pair of source and drain electrodes206A and206B, the semiconductor layers212B surrounds the other of a pair of source and drain electrodes206A and206B and the semiconductor nanosheet214is disposed between a pair of source and drain electrodes206A and206B. For example, the semiconductor layer212A surrounds the source electrode206A while the semiconductor layer212B surrounds the drain electrode, and vice versa. In some embodiments, the semiconductor materials202and208are removed through an etching process. The etching process includes, for example, an isotropic etching process such as wet etch or an anisotropic etching process such as dry etch. In some embodiments, an etchant for the wet etch includes a combination of hydrogen fluoride (HF) and ammonia (NH3), a combination of HF and tetramethylammonium hydroxide (TMAH), or the like. On the other hand, the dry etch process includes, for example, reactive ion etch (RIE), inductively coupled plasma (ICP) etch, electron cyclotron resonance (ECR) etch, neutral beam etch (NBE), and/or the like.

In some embodiments, the semiconductor layer212A, the semiconductor layer212B and the semiconductor nanosheet214are respectively include a semiconductor layer202aand a semiconductor layer208a. For example, the semiconductor layer202aof the semiconductor layer212A is disposed at a first surface (e.g., bottom surface)207aof one (e.g., the source electrode206A) of a pair of source and drain electrodes206A and206B, and the semiconductor layer208aof the semiconductor layer212A is disposed at a second surface (e.g., top surface)207bopposite to the first surface of the one (e.g., source electrode206A) of the pair of source and drain electrodes206A and206B and on sidewalls between the first and second surfaces207aand207b. Similarly, the semiconductor layer202aof the semiconductor layer212B is disposed at a first surface (e.g., bottom surface)207aof the other (e.g., drain electrode206B) of the pair of source and drain electrodes206A and206B, and the semiconductor layer208aof the semiconductor layer212B is disposed at a second surface (e.g., top surface)207bopposite to the first surface of the other (e.g., drain electrode206B) of the pair of source and drain electrodes206A and206B and on sidewalls between the first and second surfaces207aand207b. In other words, one of a pair of source and drain electrodes206A and206B is surrounded by the semiconductor layer212A, and the other of the pair of source and drain electrodes206A and206B is surrounded by the semiconductor layer212B. The semiconductor nanosheet214includes the semiconductor layer202aand the semiconductor layer208aon the semiconductor layer202a, for example.

In some embodiments, the semiconductor layer202ais continuously formed on a pair of source and drain electrodes206A and206B and the region between the pair of source and drain electrodes206A and206B, and the semiconductor layer208ais also continuously formed below a pair of source and drain electrodes206A and206B and the region between the pair of source and drain electrodes206A and206B. In some embodiments, the semiconductor layer212A and the semiconductor layer212B are physically connected by the semiconductor nanosheet214therebetween. In some embodiments, the semiconductor layer212A, the semiconductor nanosheet214and the semiconductor layer212B are continuous and thus may be referred to as a semiconductor structure (or a channel structure), and the source and drain electrodes206A and206B are embedded in the semiconductor structure. In an embodiment in which the semiconductor layer202aand the semiconductor layer208ahave the same material, an interface does not exist between the semiconductor layer202aand the semiconductor layer208a. For example, the semiconductor layer202aand the semiconductor layer208aare integrally formed. On contrary, in an embodiment in which the semiconductor layer202aand the semiconductor layer208ahave different materials, an interface may exist between the semiconductor layer202aand the semiconductor layer208a.

Referring toFIG.2FandFIG.3F, portions of the dielectric layer200are removed, to form trenches216A,216B and216C. In some embodiments, with the patterned photoresist layer210, the dielectric layer200is partially removed through an etching process. The etching process includes, for example, an isotropic etching process such as wet etch or an anisotropic etching process such as dry etch. In some embodiments, an etchant for the wet etch includes a combination of hydrogen fluoride (HF) and ammonia (NH3), a combination of HF and tetramethylammonium hydroxide (TMAH), or the like. On the other hand, the dry etch process includes, for example, reactive ion etch (RIE), inductively coupled plasma (ICP) etch, electron cyclotron resonance (ECR) etch, neutral beam etch (NBE), and/or the like. As mentioned above, the etching selectivity between the semiconductor layer202aand the dielectric layer200and between the semiconductor layer208aand the dielectric layer200is high. Therefore, during the etching process, the etchant may selectively remove the dielectric layer200without damaging the exposed semiconductor layer212A, semiconductor layer212B and semiconductor nanosheet214. Then, the patterned photoresist layer210is removed by a removal process such as an ashing process.

In some embodiments, the trench216A is formed between the source electrodes206A and the drain electrodes206B which are paired in the same row R, the trench216B is formed between different rows R (e.g., between different pairs of source and drain electrodes206A and206B in different rows R), and the trench216C is formed between the columns C (e.g., between different pairs of source and drain electrodes206A and206B in the same row R). The trench216A is disposed below the semiconductor nanosheets214. For example, as shown inFIG.3F, sidewalls217sof the trench216A are substantially flush with adjacent sidewalls207sof a pair of the source and drain electrodes206A and206B. Accordingly, the semiconductor nanosheet214may be suspended over the dielectric layer200between a pair of source and drain electrodes206A and206B. In some embodiments, the trenches216A and the trenches216B are extended along the direction D2, and the trenches216A and the trenches216B are alternately arranged along the direction D1. The trenches216C may be extended along the direction D1and arranged along the direction D2. The trenches216C cross over the trenches216A and the trenches216B, and the trenches216A,216B and216C are connected to form a net-shaped trench, for example. In some embodiments, a depth of the trenches216A,216B and216C is substantially the same. For example, the depth of the trenches216A,216B and216C is in a range of 10 nm to 100 nm.

Referring toFIG.2GandFIG.3G, a memory material218and a conductive material220may be sequentially formed. For example, the memory material218is formed on the exposed surfaces of the semiconductor nanosheet214and the trenches216A to216C. The memory material218may be deposited conformally on the exposed surfaces of the semiconductor nanosheet214and bottom and sidewall surfaces of the trenches216A to216C. In some embodiments, the memory material218includes materials that are capable of switching between two different polarization directions by applying an appropriate voltage differential across the memory material218. For example, the memory material218includes ferroelectric material or the like.

In some embodiments, the memory material218has a thickness of about 1-20 nm, such as 5-10 nm. Other thickness ranges (e.g., more than 20 nm or 5-15 nm) may be applicable. In some embodiments, the memory material218is formed in a fully amorphous state. In alternative embodiments, the memory material218is formed in a partially crystalline state; that is, the memory material218is formed in a mixed crystalline-amorphous state and having some degree of structural order. In alternative embodiments, the memory material218is formed in a fully crystalline state. In some embodiments, the memory material218is a single layer. In alternative embodiments, the memory material218is a multi-layer structure. After the memory material218is deposited, an annealing step may be performed, so as to achieve a desired crystalline lattice structure for the memory material218. In some embodiments, upon the annealing process, the memory material218is transformed from an amorphous state to a partially or fully crystalline state. In alternative embodiments, upon the annealing, the memory material218is transformed from a partially crystalline state to a fully crystalline state.

In alternative embodiments, the memory material218is replaced with a gate dielectric material. In such embodiments, the gate dielectric material includes silicon oxide, silicon nitride, silicon oxynitride, high-k dielectrics, or a combination thereof. It should be noted that the high-k dielectric materials are generally dielectric materials having a dielectric constant higher than 4, greater than about 12, greater than about 16, or even greater than about 20. The gate dielectric material may include metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, or combinations thereof.

After forming the memory material218, the conductive material220may be formed to wrap the semiconductor nanosheets214and fills space above the semiconductor nanosheets214between the source and drain electrodes206A and206B and the trenches216A to216C. In some embodiments, the conductive material220includes Mo, Ti, Pd, W, Co, Cr, Cu, Ni, Ta, Pt, Au, Al, TiW, TiN, TaN, WN, WCN, any other suitable metal-containing material, or a combination thereof. The conductive material220may be formed by a deposition process such as ALD, CVD, PVD, or the like. In some embodiments, a barrier layer (not shown) is optionally formed between the conductive material220and the memory material218, so as to avoid diffusion of atoms between elements. In some embodiments, the barrier material includes TiN, TaN, TiSiN, TaSiN, WSiN, TiC, TaC, TiAlC, TaAlC, TiAlN, TaAlN, or a combination thereof.

The memory material218and the conductive material220may further formed outside the trenches216A to216C such as formed on the semiconductor layers212A and212B. Thus, after forming the memory material218and the conductive material220, a planarization process (e.g., a CMP, etch back, or the like) may be performed to remove excess portions of the memory material218and the conductive material220. For example, by using the semiconductor layers212A and212B as polish stop layers or etch stop layers, the memory material218and the conductive material220higher than surfaces (e.g., top surfaces) of the semiconductor layers212A and212B are removed. Thus, as shown inFIG.2GandFIG.3G, after removal, surfaces (e.g., top surfaces) of the memory material218and the conductive material220are substantially coplanar with surfaces (e.g., top surfaces) of the semiconductor layers212A and212B. In some embodiments, as shown inFIG.2G, the conductive material220is net-shaped.

Referring toFIG.2HandFIG.3H, portions of the conductive material220in the trenches216B are replaced with dielectric layers226. In some embodiments, portions of the conductive material220in the trenches216B are removed through an etching process by using a mask (not shown). For example, the conductive material220in the trenches216B is exposed by the mask, and then the exposed conductive material220is removed by an anisotropic etching process such as dry etch or an isotropic etching process such as wet etch. After the removal, the dielectric layers226are formed to fill the trenches216B respectively, for example. In some embodiments, the dielectric layer226is in direct contact with the memory layer222and is surrounded by the memory layer222. In some embodiments, as shown inFIG.2H, the dielectric layer226has an inverted T shape. For example, a first portion of the dielectric layer226surrounded by the dielectric layer200has a first width, and a second portion of the dielectric layer226between the source and drain electrodes206A and206B has a second width smaller than the first width. In some embodiments, the dielectric layer226continuously extends between the adjacent source and drain electrodes206A and206B in different rows R. For example, the dielectric layer226continuously extends between the source electrodes206A in the first row R and the drain electrode206B in the second row R which are immediately adjacent to each other. The dielectric layer226may extend in the direction D2substantially parallel to the extending direction (e.g., the direction D2) of the gate electrode224. The dielectric layers226and the gate electrodes224are alternately arranged along the direction D1, for example. The dielectric layers226may include silicon oxide, silicon nitride, silicon oxynitride, the like or a combination thereof, and dielectric layers226may be deposited by CVD, PVD, ALD, PECVD, the like or a combination thereof. Optionally, after deposition, a planarization process (e.g., a CMP, etch back, or the like) may be performed to remove excess portions of the dielectric materials. In some embodiments, the material of the dielectric layers226is substantially the same as the dielectric layer200. In such embodiments, an interface may not exist between the dielectric layer200and the dielectric layers226, and the dielectric layer200and the dielectric layers226are integrally formed. However, the disclosure is not limited thereto. The material of the dielectric layers226may be different from the dielectric layer200. In some embodiments, from a top view, the dielectric layer226is a straight line.

After forming the dielectric layers226, the remained memory material218in the trenches216A,216B and216C and the remained conductive material220in the trenches216A and216C are referred to as a memory layer222and a gate electrode224, respectively. As shown inFIG.3HandFIG.4A, the gate electrode224wraps around the semiconductor nanosheet214and is disposed between the source and drain electrodes206A and206B, for example. In some embodiments, as shown inFIG.2H, the gate electrode224has an inverted T shape. For example, a first portion of the gate electrode224(e.g., below the semiconductor nanosheet214) surrounded by the dielectric layer200has a first width, and a second portion of the gate electrode224(e.g., above the semiconductor nanosheet214) between the source and drain electrodes206A and206B has a second width smaller than the first width. In some embodiments, the gate electrode224continuously extends between the source and drain electrodes206A and206B of plural pairs in the same row R. For example, the gate electrode224is disposed between the source electrodes206A and the drain electrodes206B which are paired in the same row R. In addition, the gate electrode224may further extend between the source electrodes206A and/or between the drain electrodes206B in the same row R. In such embodiments, the gate electrode224is shaped as a net and has a cross shape at an intersection228A of the source and drain electrodes206A and206B in the same row R. In some embodiments, as shown inFIG.2H, an outer sidewall of the gate electrode224is substantially flush with an inner sidewall of the memory layer222surrounding the dielectric layer226. In some embodiments, the dielectric layer226is electrically isolated the gate electrodes224in different rows R. The dielectric layer226is in direct contact with the gate electrode224, for example.

In some embodiments, the memory layer222is continuously disposed along with the gate electrode224. The memory layer222is disposed between the gate electrode224and the semiconductor nanosheet214, between the gate electrode224and the semiconductor layer212A, between the gate electrode224and the semiconductor layer212B and between the gate electrode224and the dielectric layer200, for example. In some embodiments, the memory layer222is in direct contact with the gate electrode224, the semiconductor nanosheet214, the semiconductor layer212A, the semiconductor layer212B and the dielectric layer200. In some embodiments, the memory layer222is further disposed between and in direct contact with the dielectric layer200and the dielectric layer226. For example, the memory layer222surrounds the dielectric layer226. In some embodiments, the memory layer222is also referred to as a gate dielectric layer.

In the resulting structure, first surfaces (e.g., top surfaces)223a,225a,213a,227aof the memory layer222, the gate electrode224, the semiconductor layers212A,212B (i.e., the semiconductor layers208aof the semiconductor layers212A,212B) and the dielectric layer226may be substantially coplanar (e.g., within process variations). Second surfaces (e.g., bottom surfaces)223b,225b,213b,227bof the memory layer222, the gate electrode224, the semiconductor layers212A,212B (i.e., the semiconductor layers202aof the semiconductor layers212A,212B) and the dielectric layer226are disposed opposite to the first surfaces223a,225a,213a,227a. The second surface225bof the gate electrode224is substantially coplanar with the second surface227bof the dielectric layer226, and the second surface223bof the memory layer222below the gate electrode224is substantially coplanar with the second surface223bof the memory layer222below the dielectric layer226, for example. The second surfaces213bof the semiconductor layers212A,212B (i.e., the semiconductor layers202aof the semiconductor layers212A,212B) may be substantially coplanar with a surface215a(e.g., bottom surface) of the semiconductor nanosheet214, and may be disposed between the first and second surfaces223aand223bof the memory layer222and between the first and second surfaces225aand225bof the gate electrode224.

In some embodiments, the cross-sectional view of the semiconductor nanosheet214(i.e., channel layer) is circular (as shown inFIG.4B). However, the disclosure is not limited thereto. The semiconductor nanosheet214may have any suitable cross-sectional view such as oval (as shown inFIG.5A), square (as shown inFIG.5B) and rectangular (as shown inFIG.5C). In some embodiments, the memory layer222is illustrated as a single layer as shown inFIG.4BtoFIG.5C. However, the disclosure is not limited thereto. In alternative embodiments, as shown inFIG.5DandFIG.5E, the memory layer222is a multi-layer structure. For example, the memory layer222includes a plurality of sublayers222a,222b,222cbetween the semiconductor nanosheet214and the gate electrode224. The materials of the sublayers222a,222b,222cmay be selected based on the interfacial property to the semiconductor nanosheet214or the gate electrode224. For example, the sublayer222ais in direct contact with the semiconductor nanosheet214, and thus it is suitable for the sublayer222ato be electrically compatible with the semiconductor nanosheet214. Similarly, the outermost sublayer (e.g., sublayer222bor sublayer222c) is in direct contact with the gate electrode224, and thus it is suitable for the outermost sublayer (e.g., sublayer222bor sublayer222c) to be electrically compatible with the gate electrode224. The sublayers222a,222b,222cmay have different materials or the same material with different dopants or different dopant concentration. For example, the sublayers222a,222b,222cinclude Hf1-xZrxO2(HZO)-based material, and rations of Hf and Zr of the sublayers222a,222b,222care different from each other.

In some embodiments, after formation of the dielectric layer226, a memory device is formed. The memory device includes a memory array including a plurality of memory cells MC arranged in a plurality of rows R and a plurality of columns C. As shown inFIG.2HandFIG.3H, it is seen that each memory cell MC includes a GAA transistor (e.g., a GAA ferroelectric TFT) T with the memory layer222. In alternative embodiments, the memory layer222is replaced with a gate dielectric layer including a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, and high-k dielectrics. In some embodiments, each GAA transistor T of the memory cell MC includes the gate electrode224(e.g., electrically connected to a word line), the source and drain electrodes206A and206B (e.g., electrically connected to a source line and a bit line) and the semiconductor nanosheet214functioning as the channel layer. The dielectric layers200and226are used for isolating memory cells MC. In some embodiments, the memory cells MC are disposed on the dielectric layer200and surrounded by the dielectric layer226. The dielectric layers200and226may be collectively referred to as a dielectric structure, and thus as shown inFIG.2HandFIG.3H, the memory cells MC are embedded in the dielectric structure.

In some embodiments, the memory layer222is used to store the digital information (e.g., a bit “1” or “0”) stored in the memory cell MC. In some embodiments, the GAA ferroelectric TFT is integrated into CMOS BEOL process for computing-in-memory application due to its low-temperature process. Furthermore, the GAA ferroelectric TFT may show improved electrical properties such as gate control ability, low leakage current, low resistance and high on/off current ratio.

Referring toFIG.2IandFIG.3I, conductive lines230A and conductive lines230B are formed to electrically connect the source electrodes206A and the drain electrodes206B, respectively. In some embodiments, the conductive lines230A are formed above the source electrodes206A, and the conductive lines230A are electrically connected to the source electrodes206A through a plurality of conductive contacts232A therebetween. The conductive lines230B are formed above the drain electrodes206B, and the conductive lines230B are electrically connected to the drain electrodes206B through a plurality of conductive contacts232B therebetween. For example, the conductive contacts232A penetrate the semiconductor layer212A to electrically connect to the source electrodes206A, and similarly, the conductive contacts232B penetrate the semiconductor layer212B to electrically connect to the drain electrodes206B. In some embodiments, the conductive lines230A,230B are formed using a combination of photolithography and etching techniques. The conductive lines230A,230B may include copper, silver, gold, tungsten, aluminum, combinations thereof, or the like. In addition, the conductive lines230A,230B may have other configurations.

The conductive lines230A and the conductive lines230B may each extend in the direction D2perpendicular to the extending direction (e.g., the direction D1) of the gate electrodes224. The conductive lines230A and the conductive lines230B may be parallel to each other and alternately arranged over the dielectric layer200along the direction D1. In some embodiments, the conductive lines230A,230B and the gate electrodes224connect the memory device to an underlying/overlying circuitry (e.g., control circuitry) and/or signal, power, and ground lines, respectively. Other conductive contacts or vias may be formed to electrically connect the conductive lines230A,230B and the gate electrodes224to the underlying active devices of the substrate. In alternative embodiments, routing and/or power lines to and from the memory device are provided by an interconnect structure formed over the memory device.

In some embodiments, as shown inFIG.2H, the dielectric layers226are merely formed in the trenches216B. However, the disclosure is not limited thereto. In alternative embodiments, the dielectric layers226further extend into the trenches216C. In such embodiments, during the step of removal of the conductive material220in the trenches216B, the conductive material220in portions of the trenches216C are also removed. Thus, as shown inFIG.6, the dielectric layer226has a cross shape at an intersection228B of the source and drain electrodes206A and206B in different rows R. The dielectric layer226may further extend between the adjacent source and electrodes206A and206B in different rows R. In some embodiments, as shown inFIG.6, both outer sidewalls of the dielectric layer226at the intersection228B extend beyond the memory layer222. In such embodiments, the dielectric layer226and the gate electrode224are both shaped as a net. However, the disclosure is not limited thereto. In alternative embodiments, only a first outer sidewall of the dielectric layer226extends beyond the memory layer222while a second outer sidewall opposite to the first outer sidewall of the dielectric layer226remains being substantially flush with the memory layer222. In an embodiment (not shown), the dielectric layer226fills the trench216C entirely, and thus the dielectric layer226has a net shape while the gate electrode224is a straight line.

In some embodiments, as mentioned before with reference toFIG.2GandFIG.3G, since the semiconductor layers212A and212B is used as polish stop layers or etch stop layers, surfaces (e.g., top surfaces) of the memory material218and the conductive material220are substantially coplanar with surfaces (e.g., top surfaces) of the semiconductor layers212A and212B. Accordingly, the formed memory layer222and gate electrode224also have the surfaces (e.g., top surfaces)223a,225asubstantially coplanar with surfaces (e.g., top surfaces)213aof the semiconductor layers212A and212B as shown inFIG.2HandFIG.3H. However, the disclosure is not limited thereto. In alternative embodiments, during the partial removal of the conductive material220, the memory material218may serve as a polish stop layer or an etch stop layer, and thus the memory material218remains on the semiconductor layers212A and212B without removing. Accordingly, as shown inFIG.7AandFIG.7B, the formed memory layer222further extends onto the surfaces213a(e.g., top surfaces) of the semiconductor layers212A and212B. In such embodiments, the memory layer222surrounds the dielectric layer226, extends on the semiconductor layers212A and212B and wraps the semiconductor nanosheet214continuously. The surface223aof the memory layer222is substantially flush with the surfaces227a,225aof the dielectric layer226and the gate electrode224, for example. Furthermore, in such embodiments, as shown inFIG.7AandFIG.7B, the conductive contacts232A and232B penetrates the memory layer222and the semiconductor layer212A to electrically connect to the source and drain electrodes206A and206B respectively.

At act S300, a first semiconductor material is formed over a first dielectric layer.FIG.2AandFIG.3Aillustrate views corresponding to some embodiments of act S300.

At act S302, a first conductive material on the first semiconductor material.FIG.2AandFIG.3Aillustrate views corresponding to some embodiments of act S302.

At act S304, the first conductive material is patterned to form plural pairs of source and drain electrodes separated from each other.FIG.2BandFIG.3Billustrate views corresponding to some embodiments of act S304.

At act S306, a second semiconductor material is formed on the plural pairs of source and drain electrodes and the first semiconductor material.FIG.2CandFIG.3Cillustrate views corresponding to some embodiments of act S306.

At act S308, portions of the first semiconductor material, the second semiconductor material and the first dielectric layer respectively between each pair of source and drain electrodes are removed, to form a plurality of semiconductor nanosheets respectively between each pair of source and drain electrodes and a plurality of first trenches respectively below the semiconductor nanosheets.FIG.2DtoFIG.2FandFIG.3DtoFIG.3Fillustrate views corresponding to some embodiments of act S306.

At act S310, a memory layer and a gate electrode are formed to wrap around the semiconductor nanosheets.FIG.2G,FIG.2H,FIG.3G,FIG.3H,FIG.6,FIG.7AandFIG.7Billustrate views corresponding to some embodiments of act S310.

In accordance with some embodiments of the disclosure, a transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.

In accordance with some embodiments of the disclosure, a memory device includes a plurality of memory cells. The memory cells include plural pairs of source and drain electrodes, a plurality of semiconductor nanosheets, a gate electrode and a memory layer. The source and drain electrodes are separated from each other. Each semiconductor nanosheet is disposed between each pair of source and drain electrodes. The gate electrode continuously wraps around the semiconductor nanosheets, wherein the gate electrode is continuously disposed between the plural pairs of source and drain electrodes. The memory layer is disposed between the gate electrode and the semiconductor nanosheets.

In accordance with some embodiments of the disclosure, a manufacturing method of a memory device includes at least the following steps. A first semiconductor material is formed over a first dielectric layer. A first conductive material is formed on the first semiconductor material. The first conductive material is patterned to form plural pairs of source and drain electrodes separated from each other. A second semiconductor material is formed on the plural pairs of source and drain electrodes and the first semiconductor material. Portions of the first semiconductor material, the second semiconductor material and the first dielectric layer respectively between each pair of source and drain electrodes are removed, to form a plurality of semiconductor nanosheets respectively between each pair of source and drain electrodes and a plurality of first trenches respectively below the semiconductor nanosheets. A memory layer and a gate electrode are formed to wrap around the semiconductor nanosheets.