Processor performance state optimization

A processor performance state optimization includes a system to change a performance state of a processor. In an embodiment, the system to change a performance state of the processor includes a processor and a step logic sub-system operatively coupled with the processor and is operable to communicate a performance state change request to the processor. A core voltage regulator is operatively coupled with the step logic sub-system. An end performance state sub-system to determine a desired end performance state is coupled with the step logic sub-system. And, an enable sub-state transition sub-system to enable sub-state transitions is coupled with the step logic sub-system.

BACKGROUND

The present disclosure relates generally to information handling systems (IHSs), and more particularly to IHS processor performance state optimization.

IHSs are generally understood in the art to operate using a processor to process information. Current processor control algorithms have been found through experimentation when running bursty applications to give higher performance and lower power consumption when using minimum and maximum performance states and transitioning between the two. A processor may process information by running as fast as possible to get a piece of work done and then sleeping the system until the next processing information arrives. Traditionally, processors begin running at a lowest performance state and let the voltage continue to slew to a voltage required by the intended performance state and then transition the operating frequency once this occurs. However, with a processor having many performance states, the processor spends a large amount of time at the lowest speed with much higher voltages than required for the given operating frequency. This results in a power penalty for the performance of the processor obtained at the low operating frequency.

Accordingly, it would be desirable to provide improved processor performance state optimization absent the deficiencies described above.

SUMMARY

According to one embodiment, a system to change a performance state of a processor includes a processor and a step logic sub-system operatively coupled with the processor and is operable to communicate a performance state change request to the processor. A core voltage regulator is operatively coupled with the step logic sub-system. An end performance state sub-system to determine a desired end performance state is coupled with the step logic sub-system. And, an enable sub-state transition sub-system to enable sub-state transitions is coupled with the step logic sub-system.

DETAILED DESCRIPTION

For purposes of this disclosure, an IHS100includes any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, or other purposes. For example, an IHS100may be a personal computer, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The IHS100may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, read only memory (ROM), and/or other types of nonvolatile memory. Additional components of the IHS100may include one or more disk drives, one or more network ports for communicating with external devices as well as various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. The IHS100may also include one or more buses operable to transmit communications between the various hardware components.

FIG. 1is a block diagram of one IHS100. The IHS100includes a processor102such as an Intel Pentium™ series processor or any other processor available. A memory I/O hub chipset104(comprising one or more integrated circuits) connects to processor102over a front-side bus106. Memory I/O hub104provides the processor102with access to a variety of resources. Main memory108connects to memory I/O hub104over a memory or data bus. A graphics processor110also connects to memory I/O hub104, allowing the graphics processor to communicate, e.g., with processor102and main memory108. Graphics processor110, in turn, provides display signals to a display device112.

Other resources can also be coupled to the system through the memory I/O hub104using a data bus, including an optical drive114or other removable-media drive, one or more hard disk drives116, one or more network interfaces118, one or more Universal Serial Bus (USB) ports120, and a super I/O controller122to provide access to user input devices124, etc. The IHS100may also include a solid state drive (SSDs)126in place of, or in addition to main memory108, the optical drive114, and/or a hard disk drive116. It is understood that any or all of the drive devices114,116, and126may be located locally with the IHS100, located remotely from the IHS100, and/or they may be virtual with respect to the IHS100.

Not all IHSs100include each of the components shown inFIG. 1, and other components not shown may exist. Furthermore, some components shown as separate may exist in an integrated package or be integrated in a common integrated circuit with other components, for example, the processor102and the memory I/O hub104can be combined together. As can be appreciated, many systems are expandable, and include or can include a variety of components, including redundant or parallel resources.

The advanced configuration and power interface (ACPI) performance states are commonly used as processor102and other device performance standards and are commonly understood by those having ordinary skill in the art. ACPI specification is an open industry standard that defines common interfaces for hardware recognition, motherboard and device configuration and power management. Using ACPI, an operating system (OS) for an IHS is generally in control of the power management of the IHS. As is also commonly understood by those having ordinary skill in the art, processor102power states are generally know as C0(operating state), C1(halt), C2(stop-clock), and C3(sleep). Performance states for the processor102and other devices are generally implementation-dependent, where P0is the highest performance state, with P1to Pn being successively lower-performance states. Power consumption in semiconductor type devices equals a switching function (Voltage2·frequency·capacitance·constant) plus a leakage function (Voltage2/Resistance). Therefore, it follows that changing both voltage and frequency of operation for the processor yields exponential changes in power consumption for the device (e.g., a processor102). It is generally understood that there is a minimum operating frequency for the semiconductor device for a given voltage.

FIG. 2illustrates a prior art embodiment of a processor102performance state change method130. The method130begins at block132where the processor is presently in one of several available performance states. The method130proceeds to decision block132where the method130determines whether a time since the last processor102calculation equals a pre-determined time delay. If no, the time since the last processor102calculation does not equal a pre-determined time delay, the method130returns to block132. If yes, the time since the last processor102calculation does equal a pre-determined time delay, the method130proceeds to block136where the method130collects data and calculates processor business for the interval time since the last calculation. The method130then proceeds to decision block138where the method130determines whether a performance state change is required. If no, no performance state change is required, the method130returns to block132. If yes, a performance state change is required, the method130proceeds to block140where the method130changes the performance state of the processor102. The method130then returns to block132and starts over.

FIG. 3illustrates an embodiment of an optimized processor performance state change method144. The method144begins at block146where the processor102is presently in one of several available performance states. The method144proceeds to decision block148where the method144determines whether a time since the last processor102calculation equals a pre-determined time delay. If no, the time since the last processor102calculation does not equal a pre-determined time delay, the method144returns to block146. If yes, the time since the last processor102calculation does equal a pre-determined time delay, the method144proceeds to block150where the method144collects data and calculates processor business for the interval time since the last calculation. The method144then proceeds to decision block152where the method144determines whether a performance state change is required. If no, no performance state change is required, the method144returns to block146. If yes, a performance state change is required, the method144proceeds to block154where the method144changes the performance state of the processor102. The method144then proceeds to decision block156where the method144determines whether intermediate stepping of voltage and/or frequency between pre-determined performance states levels is required. If no, the method144returns to block146. If yes, intermediate stepping is required, the method144proceeds to block158where the method144sets a sub-step timer. The method144then proceeds to decision block160where the method144determines whether the sub-step timer has expired. If no, the method144returns to decision block160. If yes, the sub-step timer has expired, the method144proceeds to block162where the method144sends a processor state change request. The method144then proceeds to decision block164where the method144determines whether the desired performance state has been achieved. If no, the method144returns to block158. If yes, the desired performance state has been achieved, the method returns to block146and starts over.

FIG. 4illustrates a logic block diagram for an embodiment of a sub state change system170internal to the processor102. In this system170, the processor102includes a step logic system172for reviewing a pre-loaded performance ramp table and determining when performance state changes and performance sub-state changes are desirable and initiating such changes. The step logic system172communicates a voltage identification174to a core voltage regulator176. Therefore, the step logic system172informs the core voltage regulator176of the desired voltage for the processor102core. When informed of the desired voltage level for the processor102core, the core voltage regulator176may regulate the processor102core operating voltage. It is generally understood that changing the core voltage level requires a slew time for the voltage to change to a new desired level. Therefore, changing a voltage level may be performed before changing a frequency level when changing performance states allowing the voltage to sloop to the desired level before the frequency is changed. This keeps the processor102operating above a minimum core voltage operating level.

FIG. 5illustrates a logic block diagram for an embodiment of a sub state change system180external to processor102. In this system180, the processor102couples with an external step logic system182for reviewing a pre-loaded performance ramp table and determining when performance state changes and performance sub-state changes are desirable and initiating such changes. The step logic system182receives a voltage identification184from the processor. The step logic system182communicates a voltage identification186to a core voltage regulator188. Therefore, the step logic system182informs the core voltage regulator188of the desired voltage for the processor102core. When informed of the desired voltage level for the processor102core, the core voltage regulator188may regulate the processor102core operating voltage. The step logic182receives a desired end performance state input190informing the step logic182of a desired end performance state for the processor102. The step logic182may use the desired end performance state input190to determine how to perform intermediate steps for voltage and/or frequency between defined performance states. The step logic182also receives an enable sub state transition input informing the step logic182if sub state transitions are available for the processor102. The step logic182uses the voltage identification input184, the desired end performance state input190, and/or the enable sub state transitions input192to determine if and how intermediate steps should be taken in voltage and/or frequency between the performance states and communicates outputs of a voltage identification186and a performance state change request194to the core voltage regulator188and the processor102respectively.

FIG. 6illustrates an embodiment of a transition diagram200showing work potential between performance states along a processor102core operating level202. An existing performance state Pn204is shown. A desired or target performance state P0206is also shown. This diagram200shows that one or more work potential states Pn-1208, Pn-2210exist between the performance states204,206along the operating level202.

Referring toFIGS. 4,5, and6, both of the systems170,180should be initialized with a set of voltages for supported performance states. During transition from one performance state to another performance state, the systems170,180would know a desired final performance state. Combining this knowledge with a preloaded supported performance state table would allow the systems170,180to initiate sub-state changes along the ramp202.

In an embodiment, when transitioning up in voltage, the system170,180would compare a present voltage to a voltage required for all supported performance states with higher voltage requirements than the present performance state. Then, the system170,180would initiate a processor performance state change when the present voltage is greater than or equal to the next supported performance state voltage as defined on performance state table.

In an embodiment, when transitioning down in voltage, the system170,180may transition by determining when present voltage is substantially equal to a present performance state minimum voltage plus a preset offset voltage and when so, initiating a transition to a next lower voltage performance state. The offset assures that transition occurs before voltage gets below a minimum for the present performance state. As such, this allows a voltage reduction to be continuous.

In an embodiment, when transitioning down in voltage, the system170,180may transition by reducing voltage to a minimum for the present performance state and pause the voltage reduction. Then, the system170,180may initiate a performance state change, wait for it to complete and reduce voltage to the minimum for the new performance state.

In an embodiment, a hardware change from present processor architecture supports transitions to intermediate performance states during ramping of voltage between performance states that have intermediate states. This allows the processor performance to adjust as the voltage slews and gains more performance relative to the higher power dissipation due to the higher voltage. A similar situation exists on transitions from higher performance states to lower ones.

In IHS operating systems software drivers generally perform performance state changes for the processors102. However, most operating systems do not change faster than about every 50 msec. A slow part of the performance state transition is the voltage slew from one value to another value. To the contrary, frequency changes may take place in a few micro seconds to a few clock cycles. Therefore, it is generally desirable to slew the voltage first and then tell the controller to change the frequency. This can be performed in reverse when transitioning to a lower performance state. In an embodiment, the transition to intermediate performance states is performed by hardware, such as shown inFIG. 5, because the hardware can react faster than software initiated state changes and thus, improves IHS100performance. It is a benefit in both desktop and mobile devices to transition to low power as soon as possible to save power. In an embodiment, an operating point may be controlled by the operating system, but during slew times, hardware may be used to ramp the system using intermediate steps following the slew/frequency level at allowable operating points.