Optimizing the utilization of metrology tools

Methods and corresponding metrology modules and systems, which measure metrology parameter(s) of a previous layer of a metrology target and/or an alignment mark, prior to producing a current layer of the metrology target, derive merit figure(s) from the measured metrology parameter(s) to indicate an inaccuracy, and compensate for the inaccuracy to enhance subsequent overlay measurements of the metrology target. In an example embodiment, methods and corresponding metrology modules and systems use stand-alone metrology tool(s) and track-integrated metrology tool(s) at distinct measurement patterns to address separately different aspects of variation among wafers.

TECHNICAL FIELD

The present disclosure relates to the field of metrology, and more particularly, to utilizing metrology tools in more efficient ways.

BACKGROUND

Current lithography process control evaluates critical dimensions (CDs), overlay, side wall angles (SWA), focus and dose etc. and is carried out after the lithography process is completed, i.e., after the process on the track, the application of the lithography tool (e.g., scanner, stepper) and additional and track processes (e.g., develop) have taken place. The associated metrology processes are used to detect need for rework and scanner correction terms, e.g., in a feedback mode. Current process control is carried out by stand-alone tools or by track-integrated tools, which are operated in similar manners.

Advanced nodes technology has very limited overlay budgets that dictate narrow process windows of 4 nm and below. Currently the overlay (OVL) is measured after the process in the lithography cell, and the data is used for calculating rework disposition and scanner correction terms. The alignment of the current exposure to previous exposure is being done using alignment marks that are printed on the wafer in a previous exposure. The overlay is measured on a different target, that includes at least two features, one is printed in the previous layer and one in the current.

Before and during the wafer exposure the scanner is looking for the alignment marks and calculates their location, by doing that the scanner aligns the previous layer pattern with new layer pattern it is about to be printed. The method of measurement and the algorithm that is being used to calculate the location of the target might be sensitive to process induced errors. Stated differently, the asymmetry of the features profile in the alignment mark might create a systematic error in the alignment of the wafer. If this process-induced asymmetry is changing along the wafer, it may induce a within-wafer (and even within-field) overlay variation. Currently those errors are being detected by carrying out overlay measurements after the development process in the lithography cell. If the wafers fail specific criteria, they go through a rework process in which the resist and other layers on the wafer (e.g., BARC—the bottom anti-reflective coating layer) are stripped and cleaned and the wafers are returned for subsequent lithographic processing. The rework process is time consuming, reduces the die yield, and may have other costs.

SUMMARY

The following is a simplified summary providing an initial understanding of the invention. The summary does not necessarily identify key elements nor limits the scope of the invention, but merely serves as an introduction to the following description.

One aspect of the present invention provides a method comprising measuring at least one metrology parameter of at least one of a previous layer of a metrology target and an alignment mark, prior to producing a current layer of the metrology target, deriving at least one merit figure from the at least one measured metrology parameter to indicate an inaccuracy, and compensating for the inaccuracy to enhance subsequent overlay measurements of the metrology target.

DETAILED DESCRIPTION

Methods and corresponding metrology modules and systems are provided, which measure metrology parameter(s) of a previous layer of a metrology target and/or an alignment mark, prior to producing a current layer of the metrology target, derive merit figure(s) from the measured metrology parameter(s) to indicate an inaccuracy, and compensate for the inaccuracy to enhance subsequent overlay measurements of the metrology target.

Certain embodiments provide measurements, e.g., by stand-alone, track-integrated, etch-integrated or any other in-situ optical metrology tool, of optical and/or structural characteristics, such as critical dimensions (e.g., height, side wall angle, pitch, line width), film thickness, refractive indices and overlay before and after the track process, of device or test features during semiconductor manufacture. The measurements may be carried out after resist strip process (AEI—After Etch Inspection). For lithography multiple patterning, the measurements may be carried out between exposures within a single layer.

For example, the wafers may be measured by an optical tool before processing in the lithography cell. In the measurement, the alignment marks may be measured in addition to part of the overlay target, both generally printed during a previous lithographic step and prior to subsequent processing (e.g., polishing, etching etc.). The measured data may be used to generate merit figure(s) that correlate with systematic errors in the consecutive overlay measurement (after production of the current layer of the targets by lithographic exposure). The overlay error that is measured after the lithographic process may be due to e.g., alignment measurement error due to optical bias associated with process induced alignment target asymmetry and/or random or systematic contributions related to the mechanics and control loops of the wafers and reticle stages.

An example for process induced alignment target asymmetry is illustrated inFIGS. 1A and 1B, schematically illustrating cross section views of lines that construct alignment marks, without and with process-induced alignment target asymmetry, respectively, according to some embodiments of the invention. The alignment target on a wafer60should have no side wall angle, as illustrated in elements62A ofFIG. 1A, while one form of process-induced alignment target asymmetry may result in a side wall angle (SWA) on one side or both sides of the alignment target elements, the former case illustrated in elements62B ofFIG. 1B. This error in turn may induce systematic error in the scanner alignment system (e.g., contribute to the wafer stage location error in the scanner). It is noted the previous layer(s) of metrology target(s) may be used to derive similar process-induced asymmetry measures as the alignment target(s) andFIG. 1A, 1Bmay be understood as representing an example of target element asymmetry in a previous layer of a metrology target as well.

One or more merit figure(s) may be calculated based on an image (e.g., in the field plane, in the pupil plane, or any combination thereof) of the alignment mark or of a previous layer in an overlay mark. The merit figure(s) may comprise mathematical manipulation(s) on the image of one of these features and/or combine measurement data from multiple alignment marks and/or metrology target(s) previous layer structures. The merit figure(s), when correlated with the post lithographic process measured overlay error, may be used to correct alignment systematic errors, e.g., by automatic process control (APC) of the lithography cell.

FIG. 2is a high level flowchart illustrating the use of pre-lithographic-process measurements100, according to some embodiments of the invention. While post-lithographic measurements81are carried out after the lithographic process, e.g., by an overlay tool80after production of the respective metrology targets50, certain embodiments comprise measurements100which are carried out prior to the completion of the metrology targets and/or on alignment mark(s)58and are thus pre-lithographic-process measurements. Alignment mark(s)58and or previous layer(s) of metrology target(s)56(prior to complete production of the metrology targets, e.g., prior to production of the current layer) may be measured by an optical tool110, and corresponding merit figures may be calculated by a merit computer120(which may be part of a metrology tool). Correction factors130may be derived from the merit figures and used by APC95to correct the production process e.g., of the current layer of devices and/or metrology targets by a scanner90or any other lithographic tool. The disclosed method may be regarded as a feed forward to APC95which improves the scanner alignment performance and reduce the rework rate. Alternatively or complementarily, when based on measurements of previous layer(s) of metrology target(s)56, the derived merit figure(s) may be used to select metrology target(s) for metrology measurements and/or to choose or adapt (i.e., select parameters of) a metrology recipe, based e.g., on relations between target asymmetry and accuracy of recipe parameters.

FIG. 3is an exemplary illustration of a correlation between the overlay and one of the suggested merit figures, according to some embodiments of the invention. The illustrated merit represents inaccuracy and is unit-less. The merit is calculated on the basis of previous layer measurements while the overlay is measured after the full production of the metrology target. It is noted that various merits may be used, such as merits comprising various mathematical manipulations on the image of any of the marks or targets and/or various measurement data from multiple alignment marks and/or metrology target(s) previous layer structures. Image manipulation data and measurement data may be combined to for merit(s). It is noted that the correlation is due to similar effects on the layers by the production tool (e.g., scanner90), which are manifested in measurements100and81, such as optical aberrations of scanner90. The data is shown for the x direction, and the correlation indicates the possibility to apply correction factor(s)130even before the production of the metrology target is completed. For example, the slope or other parameters of the correlation may be used to calculate correction factor(s)130, possibly further dependent on the location on the wafer of the specific measurement, which may then be used to correct current production of the same wafer and/or of wafers in the same lot (typically a group of 25 wafers) by APC95. Clearly, correlations between the merit figure(s) and the metrology results (such as overlay) may be found to be more complex and correction factor(s)130may be calculated accordingly. It is noted that different layers may be used as previous layer, depending on the advance of the lithographic process and the specific metrology targets and alignment marks which are used. It is further noted that the derivation of the empirical correlations between measurements81,100may be carried out by using the same measurement tool for the pre- and post-lithographic process metrology100,81(respectively) to avoid tool-related errors. The measurement tool may be integrated or stand-alone.

In some cases the same phenomena in the pre lithographic process can create the same merit that triggers the correction terms feed forward. In such cases the post lithographic process overlay measurement are larger and the lot is being reworked without the contribution of the feed forward method. In certain embodiments, when the feed forward correction parameters are too high (above a given threshold), the algorithm may disregard them and not use the feedforward data in order to prevent too high corrections.

In certain embodiments, measurements100and/or the merit figure(s) may be used to select wafer locations, alignment marks and/or metrology targets which have expected small errors and remove wafer locations, alignment marks and/or metrology targets having large expected errors from use by APC95. For example, marks or targets expected to have large side wall angles may be removed from consideration and use.

FIG. 4is a high level flowchart illustrating a method200, according to some embodiments of the invention. Method200may be at least partially implemented by at least one computer processor, e.g., in a metrology module. Certain embodiments comprise computer program products comprising a computer readable storage medium having computer readable program embodied therewith and configured to carry out of the relevant stages of method200. Certain embodiments comprise metrology measurements resulting from method200.

Method200may comprise measuring at least one metrology parameter of at least one of a previous layer of a metrology target and an alignment mark, prior to producing a current layer of the metrology target (stage210), deriving at least one merit figure from the at least one measured metrology parameter to indicate an inaccuracy (stage220), and compensating for the inaccuracy to enhance subsequent overlay measurements of the metrology target (stage230). Measuring the metrology target may be carried out with a same tool as the tool used for the measuring of the at least one metrology parameter (stage250).

Method200may further comprise correlating the derived at least one merit figure with random or systematic inaccuracies of mechanics and control loops of production stages (stage222).

In certain embodiments, the at least one metrology parameter may be measured on the alignment mark and method200may further comprise correlating the derived merit figure with an optical bias associated with process-induced alignment target asymmetry (stage224) and optionally selecting at least one alignment mark for aligning a lithography tool according to the derived merit figure (stage240).

In certain embodiments, the at least one metrology parameter may be measured on the previous layer and method200may further comprise selecting at least one metrology target for metrology measurements according to the derived merit figure (stage245) and/or choosing or adapting a metrology recipe according to the derived merit figure (stage247). Certain embodiments comprise combinations of stages224and240.

Methods and corresponding metrology modules and systems may further use stand-alone metrology tool(s) and track-integrated metrology tool(s) at distinct measurement patterns to address separately different aspects of variation among wafers.

FIG. 5is a high level schematic illustration of a metrology system101, according to some embodiments of the invention. Metrology system101may comprise at least one stand-alone metrology tool160and at least one track-integrated metrology tool150, operated according to embodiments that are described below and/or according to a method300illustrated inFIG. 6below, e.g., via a control unit140configured to manage distinct measurement patterns159,161of tools150,160, respectively. Control unit140may be configured to control a wafer tray66to provide wafers60from a wafer lot65to tools150,160.

Currently, stand-alone tools and track-integrated tools are used interchangeably and in a similar way. Stand-alone tools and track-integrated tools operate according to similar principle, yet differ in that track-integrated tools, being integrated in the track of the lithography unit, are critically limited in the measurement time available to them. The available time for metrology measurements by track-integrated tools is limited to a specified time derived from lithography unit flow in order to avoid reduction in the throughput of the lithography unit (scanner and track) due to longer measurement time. In certain embodiments, track-integrated tools150and stand-alone tools160may be used in combination to improve the process control. In advanced nodes, the wafer-to-wafer variation becomes a major contributor to the overlay error and presents the following challenges related to rework detection and correction terms validity to all wafers. In case the wafer-to-wafer variation is systematic, e.g., variation due to lens and mask heating, a compensation factor may be calculated and used to compensate for the variation. In case the variation is random and changes rapidly from lot to lot, a larger number of measurements is required to improve the detection of the variation and faster feedback is required for tool correction to compensate for the variation.

Certain embodiments comprise using track-integrated metrology tool(s)150and stand-alone metrology tool(s)160at different and distinct measurement patterns159,161to address separately different aspects of variation among wafers. Measurement patterns159,161may comprise sparse sampling of many wafers69per lot65by track-integrated tools150to yield global measurement patterns159and dense sampling of fewer wafers61per lot65by stand-alone tools160yield local measurement patterns161. It is noted that the terms global and local are used here to relate to the characterization of wafers60in wafer lot65, i.e., to lot-level variation, and to the characterization of fields in wafers60, i.e., to wafer-level variation, respectively.

For example, sparse sampling on track-integrated metrology tools150may be aimed to yield measurements of wafer characteristics152that are used to detect rework need and to select the best wafer(s) to be measured in more detail, e.g., by stand-alone metrology tool(s)160to yield metrology results162. As the number of wafers that can be measured as well as the density of measurements of each wafers are limited, the suggested embodiments provide an advantage over the current practice of measuring wafers60from specific locations in lot65. Measuring selected wafers may improve the correction terms and represent better the typical wafers and the current lithography tool conditions rather than other problems which are not related to the lithography process step. Disclosed embodiments provide improved detection (e.g., for rework) of excessive variation as it is characterized by a faster response time due to the sparse sampling of more wafers60per lot65. A non-limiting numerical example for sampling patterns may include, as global measurement pattern159, 30-50 points per wafer on 15-25 wafers measured by track-integrated tool150and, as local measurement pattern161, 600 points per wafer measured on 2 wafers by stand-alone tool160.

In another example, sparse sampling on track-integrated metrology tools150may be aimed to yield a linear or a low order correction terms154to the lithography tool as a quick correction, while dense sampling on stand-alone tools160may be aimed to yield high order correction terms164as a more exact but slower correction. A non-limiting numerical example for sampling patterns may include, as global measurement pattern159, 100-200 points per wafer on 5-10 wafers measured by track-integrated tool150and, as local measurement pattern161, 600 points per wafer measured on 2 wafers by stand-alone tool160. Due to the limited allowed time for integrated metrology tool, less dense sampling is being expected like in pattern159, and the practically possible contribution for the control or correction model is likewise limited in track-integrated metrology.

In yet another example, sparse sampling on track-integrated metrology tools150may be aimed to yield wafer correction terms156, while dense sampling on stand-alone tools160may be aimed to yield field correction terms166. The wafer correction terms and field correction terms which are thus calculated may be used in different modules to correct the lithography tool. High order wafer and field correction terms may be achieved by sampling patterns that include, as global measurement pattern159, 100-200 points per wafer on 5-10 wafers measured by track-integrated tool150and, as local measurement pattern161, 600 points per wafer measured on 2 wafers by stand-alone tool160. Advantageously, wafer and field correction terms are derived faster and more accurately than in current methods. Wafer for measurement by stand-alone tool160may be selected according to wafer measurements by track-integrated tool150.

The producer may collect all the correction terms from the different sources and then calculate a statistical aggregation in order to have controlled process over time. The corresponding correction terms may be derived adaptively over time to compensate for errors related to the source of the corrections and to control unit140.

FIG. 6is a high level flowchart illustrating a method300, according to some embodiments of the invention. Method300may be at least partially implemented by at least one computer processor, e.g., in a metrology system. Certain embodiments comprise computer program products comprising a computer readable storage medium having computer readable program embodied therewith and configured to carry out of the relevant stages of method300.

Method300may comprise using at least one stand-alone metrology tool and at least one track-integrated metrology tool at distinct measurement patterns to address separately different aspects of variation among wafers (stage310).

In certain embodiments, the distinct measurement patterns may comprise sparse sampling of wafers by the at least one track-integrated metrology tool to identify characteristics of the sparsely-sampled wafers, wherein the sparsely-sampled wafers comprise at least a half (e.g., 12 wafers or more) of the wafers in a lot (stage320), and dense sampling of wafers by the at least one stand-alone metrology tool to yield metrology results within the densely-sampled wafers, wherein the densely-sampled wafers comprise at most a tenth (e.g., 1-3 wafers) of the wafers in the lot (stage325). For example, the sparsely-sampled wafers may comprise between 15 and 25 wafers per lot, which are sampled at between 30 and 50 locations per wafer, and the densely-sampled wafers may comprise between 1 and 3 wafers per lot, which are sampled at between 400 and 800 locations per wafer.

In certain embodiments, the distinct measurement patterns may comprise sparse sampling of wafers by the at least one track-integrated metrology tool to yield low order correction terms, wherein the sparsely sampled wafers comprise at least a fifth (e.g., 5 wafers or more) of the wafers in a lot (stage330), and dense sampling of wafers by the at least one stand-alone metrology tool to yield low order correction terms, wherein the densely sampled wafers comprise at most a tenth (e.g., 2-3 wafers) of the wafers in the lot (stage335). For example, the sparsely-sampled wafers may comprise between 5 and 10 wafers per lot, which are sampled at between 100 and 200 locations per wafer, and the densely-sampled wafers may comprise between 1 and 3 wafers per lot, which are sampled at between 400 and 800 locations per wafer.

In certain embodiments, the distinct measurement patterns may comprise sparse sampling of wafers by the at least one track-integrated metrology tool to measure wafer correction terms (stage340), wherein the sparsely sampled wafers may comprise at least a fifth (e.g., 5 wafers in a lot) of the wafers in a lot, and dense sampling of wafers by the at least one stand-alone metrology tool to measure field correction terms (stage345), wherein the densely sampled wafers may comprise at most a tenth (e.g., 2-3 wafers) of the wafers in the lot.

In certain embodiments, method300may further comprise selecting the (fewer) densely-sampled wafers according to measurements of the (more) sparsely-sampled wafers (stage350).

Advantageously, the disclosed measurements prior to the completion of metrology target production may improve the scanner alignment and may enable scanner adaptation to wafer-to-wafer variation. Additionally, the disclosed procedures may reduce the rework rate and the yield loss related to overlay errors.

In the above description, an embodiment is an example or implementation of the invention. The various appearances of “one embodiment”, “an embodiment”, “certain embodiments” or “some embodiments” do not necessarily all refer to the same embodiments.

Certain embodiments of the invention may include features from different embodiments disclosed above, and certain embodiments may incorporate elements from other embodiments disclosed above. The disclosure of elements of the invention in the context of a specific embodiment is not to be taken as limiting their use in the specific embodiment alone.

Furthermore, it is to be understood that the invention can be carried out or practiced in various ways and that the invention can be implemented in certain embodiments other than the ones outlined in the description above.

The invention is not limited to those diagrams or to the corresponding descriptions. For example, flow need not move through each illustrated box or state, or in exactly the same order as illustrated and described.