Delay locked loop including a delay code generator

A delay locked loop includes a delay line, a delay circuit, a phase detector, a delay code generator, and a delay controller. The delay line may delay an input clock signal in units of unit delay in response to a delay control code to generate an output clock signal. The delay circuit may delay the output clock signal to generate a delay clock signal. The phase detector may compare the input clock signal and the delay clock signal to generate a phase detection signal. The delay code generator may compare the input clock signal and the delay clock signal to detect a phase difference therebetween, and generate a delay code using the phase difference. The delay controller may generate the delay control code using the delay code and the phase detection signal.

CROSS-REFERENCE TO RELATED APPLICATION

This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2016-0062897, filed on May 23, 2016 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated by reference herein in its entirety.

TECHNICAL FIELD

Exemplary embodiments of the inventive concept relate to delay locked loops, and more particularly, to a delay locked loop including a delay code generator.

DISCUSSION OF RELATED ART

A delay locked loop (DLL) is used to provide an internal clock having a phase which is ahead of a certain period of time of an input clock. In a semiconductor memory device having a relatively high degree of integration such as a dynamic random access memory (DRAM), an internal clock is generated to operate in synchronization with an external clock.

To provide a stable internal clock, the delay locked loop determines a delay time through a loop to generate a clock and locks the determined delay time to generate the internal clock. This process is called a lock process. A DRAM device uses the delay locked loop to complete the lock process within a reference time.

The delay locked loop in a DRAM may be used together with a duty cycle correction circuit to generate a high quality internal clock. In this case, by having the delay locked loop with a shorter lock time characteristic, the lock process of the delay locked loop and a duty cycle correction operation of the duty cycle correction circuit may be completed within a predetermined reference time.

SUMMARY

According to an exemplary embodiment of the inventive concept, a delay locked loop includes a delay line, a delay circuit, a phase detector, a delay code generator, and a delay controller. The delay line may delay an input clock signal in units of unit delay in response to a delay control code to generate an output clock signal. The delay circuit may delay the output clock signal to generate a delay clock signal. The phase detector may compare the input clock signal and the delay clock signal to generate a phase detection signal. The delay code generator may compare the input clock signal and the delay clock signal to detect a phase difference therebetween and to generate a delay code using the phase difference. The delay controller may generate the delay control code using the delay code and the phase detection signal.

According to an exemplary embodiment of the inventive concept, a delay locked loop includes a delay line, a delay circuit, a phase detector, a delay code generator, and a delay controller. The delay line may delay an input clock signal to generate an output clock signal in response to a delay control code. The delay circuit may delay the output clock signal to generate a delay clock signal. The phase detector may compare the input clock signal and the delay clock signal to detect a phase difference therebetween and generate a phase detection signal and an error pulse, having a pulse width which is proportional to the phase difference, using the phase difference. The delay code generator may generate a delay code using the error pulse. The delay controller may generate the delay control code using the delay code and the phase detection signal.

According to an exemplary embodiment of the inventive concept, in a method of performing a coarse lock process using a delay locked loop, an input clock signal and a delay clock signal are received at a phase detector. The delay clock signal is an output clock signal of the delay locked loop that is delayed for a predetermined amount of time. A phase difference between the input clock signal and the delay clock signal is determined by the phase detector to generate a phase detection signal. The input clock signal and the delay clock signal are received at a delay code generator. A delay code is generated by the delay code generator using the input clock signal and the delay clock signal. The phase detection signal and the delay code are received at a delay controller. A delay control code is generated by the delay controller using the phase detection code and the delay code. The input clock signal and the delay control code are received at a delay line to generate the output clock signal.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Exemplary embodiments of the inventive concept will be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout this application.

FIG. 1is a block diagram illustrating a delay locked loop according to an exemplary embodiment of the inventive concept. Referring toFIG. 1, the delay locked loop100may include a delay line110, a replica of internal delay120, a phase detector130, a delay code generator140, and a delay controller150.

The delay locked loop100receives an input clock signal CLK_i and delays the received input clock signal CLK_i for a certain time to generate an output clock signal CLK_o. Since a delay time must be locked in order to generate a stable output clock signal CLK_o, the delay locked loop100performs a process of locking a clock signal generation loop. The lock operation or process may be defined as an operation where the delay locked loop100determines a delay time to maintain it. For example, when a phase difference between the input clock signal CLK_i and a delay clock signal CLK_d enters a specific range, the phase detector130may generate a lock completion signal and a lock process may be completed by the lock completion signal. Generally, the lock process may include a coarse lock process that performs a lock in units of relatively large unit delays and a fine lock process that performs a lock in units of relatively small unit delays. For example, the coarse lock process and the fine lock process may be performed at substantially the same time. Alternatively, after the coarse lock process is completed, the fine lock process may be performed. It is assumed that the delay locked loop100performs the fine lock process after the coarse lock process is completed.

The delay locked loop100of the present inventive concept may reduce the time taken to perform the coarse lock process. Since the fine lock process and the method of generating the lock completion signal have little relation to the present inventive concept, a description thereof is omitted. However, an additional circuit for the fine lock process and the method of generating the lock completion signal may be added to the delay locked loop100.

The delay line110is connected to the replica of internal delay120and the delay controller150. The delay line110receives the input clock signal CLK_i, and delays the received input clock signal CLK_i for a predetermined delay according to a delay control code (Code_d[0:n]) to generate the output clock signal CLK_o. The delay control code (Code_d[0:n]) may be provided from the delay controller150. The delay line110may include a plurality of delay stages for delaying the input clock signal CLK_i in units of unit delays. A single delay stage, among the plurality of delay stages, may include a plurality of logic circuits. A configuration and operation of the delay line110will be described below with reference toFIGS. 3 to 6.

The replica of internal delay120is connected to the delay line110, the phase detector130, and the delay code generator140. The replica of internal delay120delays the output clock signal CLK_o for a delay time for which the delay locked loop100desires to compensate and generates the delay clock signal CLK_d. For example, the delay locked loop100may be used in a DRAM device and in this case, the replica of internal delay120may be designed to compensate for a delay time caused by delay components that exist on a transmission path of the input clock signal CLK_i inside the DRAM device.

The phase detector130is connected to the delay line110, the replica of internal delay120, the delay code generator140, and the delay controller150. The phase detector130receives the input clock signal CLK_i and the delay clock signal CLK_d, and determines a phase difference between them to generate a phase detection signal. For example, the phase detection signal may include a code rising signal (Code_up) and a code falling signal (Code_down). The code rising signal (Code_up) is a signal for increasing a delay time of the delay clock signal CLK_d in units of unit delays and the code falling signal (Code_down) is a signal for reducing a delay time in units of unit delays.

In the case where the delay clock signal CLK_d is ahead of the input clock signal CLK_i, the phase detector130generates the code rising signal (Code_up) to increase a delay time for the output clock signal CLK_o. In contrast, in the case where the delay clock signal CLK_d falls behind the input clock signal CLK_i, the phase detector130generates the code falling signal (Code_down) to reduce a delay time for the output clock signal CLK_o. In other words, the phase detector130performs a comparison operation and a phase detection signal generating operation to reduce the phase difference described above.

The delay code generator140is connected to the replica of internal delay120, the phase detector130, and the delay controller150. The delay code generator140receives the input clock signal CLK_i and the delay clock signal CLK_d, and determines a phase difference between them to generate a delay code (Code_c[0:m]) with respect to a time that is proportional to the phase difference. For example, when the phase difference increases, the delay code generator140increases a code value of the delay code (Code_c[0:m]), and when the phase difference decreases, the delay code generator140reduces a code value of the delay code (Code_c[0:m]).

The delay code (Code_c[0:m]) is provided to the delay controller150and includes an initial delay control code (Code_d[0:n]) of the delay line110with respect to the phase difference. Thereafter, the delay code (Code_c[0:m]) combines with the phase detection signal to generate an updated delay control code (Code_d[0:n]). For example, the number (m+1) of bits of the delay code (Code_c[0:m]) may be the same as the number (n+1) of bits of the delay control code (Code_d[0:n]). Alternatively, the number (m+1) of bits of the delay code (Code_c[0:m]) may be less than the number (n+1) of bits of the delay control code (Code_d[0:n]). This will be described below with reference toFIG. 10. A configuration and operation of the delay code generator140will be described below with reference toFIGS. 7 to 13.

The delay controller150may be connected to the delay line110, the phase detector130, and the delay code generator140. The delay controller150generates the delay control code (Code_d[0:n]) for controlling a delay time of the delay line110using the delay code (Code_c[0:m]) and the phase detection signal. For example, the number of bits of the delay control code (Code_d[0:n]) may be decided in proportion to the number of delay stages included in the delay line110. In other words, each bit of the delay control code (Code_d[0:n]) may determine whether to use a corresponding one of the delay stages of the delay line110. For example, the delay controller150may include shift registers. In this case, the delay controller150may increase or decrease the delay control code (Code_d[0:n]) by one bit. Accordingly, a delay time of the delay line110may increase or decrease by one unit delay.

The delay controller150of the present inventive concept generates the initial delay control code (Code_d[0:n]) using the delay code (Code_c[0:m]). InFIG. 1, this process is illustrated as a first loop (Loop1). After that, in the case where the delay locked loop100is coarse-locked by the initial delay control code (Code_d[0:n]), the coarse lock process is finished. In the case where the delay locked loop100is not coarse-locked by the initial delay control code (Code_d[0:n]), the delay controller150shifts the initial delay control code (Code_d[0:n]) to perform the coarse lock. InFIG. 1, this process is illustrated as a second loop (Loop2). The delay code (Code_c[0:m]) and the delay control code (Code_d[0:n]) generated by the delay code generator140and the delay controller150, respectively, may be reset by a reset signal (Reset). This will be described below with reference toFIG. 2.

The delay controller150of the present inventive concept performs a coarse lock process beginning with the delay control code (Code_d[0:n]) generated based on a code value of the initial delay code (Code_c[0:m]). As described above, the initial delay code (Code_c[0:m]) is a code value with respect to a phase difference at a first cycle of the input clock signal CLK_i and the output clock signal CLK_o. Since the delay locked loop100of the present inventive concept does not compare a phase difference with respect to all values of the delay control code (Code_d[0:n]), operation time of the coarse lock process may be reduced.

FIG. 2is a flowchart illustrating an operation of the delay locked loop ofFIG. 1according to an exemplary embodiment of the inventive concept.FIG. 2will be described with reference toFIG. 1. Referring toFIG. 2, the delay locked loop100may perform the coarse lock process.

In an operation S110, the delay locked loop100performs the first and second loop (Loop1, Loop2) operations with respect to the first cycle of the input clock signal CLK_i and the delay clock signal CLK_d. In an operation S120, the delay code generator140receives the input clock signal CLK_i and the delay clock signal CLK_d to generate the initial delay code (Code_c[0:m]) through the second loop (Loop2). After that, the delay code generator140maintains the initial delay code (Code_c[0:m]) after the first cycle.

In an operation S130, the delay controller150receives the phase detection signal and the delay code (Code_c[0:m]) to generate the delay control code (Code_d[0:n]) through the first loop (Loop1). In the first cycle, the delay controller150does not respond to the phase detection signal and generate the delay control code (Code_d[0:n]) based on the delay code (Code_c[0:m]).

In an operation S140, the phase detector130compares the input clock signal CLK_i and the delay clock signal CLK_d to determine whether the delay locked loop100is coarse-locked. In the case where the delay locked loop100is not coarse-locked (operation S140:No), the delay locked loop100performs an operation S150. In the case where the delay locked loop100is coarse-locked (operation S140:Yes), the delay locked loop100generates a coarse lock signal and the coarse lock process is finished.

In the operation S150, the phase detector130generates a phase detection signal for adjusting the delay control code (Code_d[0:n]) with respect to a second cycle. As described above, the phase detector130generates the code rising signal (Code_up) or the code falling signal (Code_down) according to a phase of the delay clock signal CLK_d with respect to an input/output signal, and provides the generated code rising signal Code_up or the generated code falling signal Code_down to the delay controller150. The delay controller150generates an updated delay control code (Code_d[0:n]) with respect to the second cycle and provides the updated delay control code (Code_d[0:n]) to the delay line (operation S130).

In the present exemplary embodiment ofFIG. 2, after generating the initial delay code Code_c[0:m] with respect to the first cycle, the delay code generator140does not perform a phase comparison operation and a delay code update operation, and maintains the initial delay code (Code_c[0:m]). This is to minimize power consumption by preventing an unnecessary operation of the delay code generator140. The operation in which the delay code generator140maintains the initial delay code (Code_c[0:m]) will be described below with reference toFIGS. 10 to 12.

After the first cycle, the delay code generator140may perform the phase comparison operation and code update operation at every cycle until the coarse lock is completed without stopping an operation. In this case, after the coarse lock is completed, the delay code generator140may operate to maintain the delay code (Code_c[m:0]) before a subsequent coarse lock is performed. In other words, after the operation S140:Yes, the delay locked loop100may perform the operation S120of generating the delay code (Code_c[0:m]) again.

After the operations S110to S150are completed, the delay locked loop100may complete a lock process by performing a fine lock process. For example, thereafter, the delay locked loop100may perform a lock process with respect to a new frequency or a new environment again. In this case, the delay locked loop100may initialize the delay code (Code_c[m:0]) and the delay control code (Code_d[0:n]) by the reset signal (Reset) to perform a new lock process.

FIG. 3is a circuit diagram illustrating the delay line110ofFIG. 1. Referring toFIG. 3, the delay line110may include first through n+1th input NAND logics (NI1to NIn+1), first through n+1th feedback NAND logics (NF1to NFn+1), first through n+1th output NAND logics (NO1to NOn+1), and first through n+1th inverters (I1to In+1). The delay line110may be turned on or off by a control signal (On). When the control signal (On) is logic ‘1’, the delay line110operates and when the control signal (On) is logic ‘0’, the delay line110does not operate and does not pass the input clock signal CLK_i. It is assumed below that the control signal (On) is logic ‘1’.

The first input NAND logic NI1, the first feedback NAND logic NF1, and the first output NAND logic NO1may constitute a first delay stage. The first delay stage generates a first delay TD1. The first and second input NAND logics NI1and NI2, the second feedback NAND logic NF2, and the first and second output NAND logics NO1and NO2may constitute a second delay stage. The second delay stage generates a second delay TD2. The first through third input NAND logics NI1to NI3, the third feedback NAND logic NF3, and the first through third output NAND logics NO1to NO3may constitute a third delay stage. The third delay stage generates a third delay TD3. Similarly, the first through n+1th input NAND logics NI1to NIn+1, the n+1th feedback NAND logic NFn+1, and the first through n+1th output NAND logics NO1to NOn+1 may constitute an n+1th delay stage. The n+1th delay stage generates an n+1th delay TDn+1.

A delay time difference between adjacent delays is substantially the same. For example, the delay time difference between the first delay TD1and the second delay TD2constitutes the unit delay described above with reference toFIG. 1. When comparing a delay time of a signal passing through the first delay stage and a delay time of a signal passing through the second delay stage, the delay difference, or the delay unit of the delay line110ofFIG. 3, may have a delay as much as a transmission time of a signal by two NAND logics, the second input NAND logic NI2and the second output NAND logic NO2.

The above-described first through n+1th delay stages may be selected by delay control codes (Code_d[0:n]). The first through n+1th inverters (I1to In+1) invert the delay control codes (Code_d[0:n]), respectively, to provide inverted delay control codes to the first through n+1th feedback NAND logics (NF1to NFn+1), respectively. The second through n+1th input NAND logics (NI2to Nin+1) directly receive the delay control codes (Code_d[0:n−1]), respectively. A method of selecting the first through n+1th delay stages will be described below with reference toFIG. 4.

FIG. 4is a drawing illustrating an operation of a NAND logic ofFIG. 3according to an exemplary embodiment of the inventive concept. Referring toFIG. 4, the first input NAND logic NI1is illustrated as merely an example. An operation of the first input NAND logic NI1may be applied to the first through n+1th input NAND logics (NI1to Nin+1), the first through n+1th feedback NAND logics (NF1to NFn+1), and the first through n+1th output NAND logics (NO1to NOn+1), illustrated inFIG. 3.

The first input NAND logic NI1receives the input clock signal CLK_i and the control signal (On) to output a signal to a node (n0). According to the control signal (On), the first input NAND logic NI1inverts the input clock signal CLK_i to transmit the inverted input clock signal CLK_i to the node (n0) or to output logic ‘1’. Referring to a table illustrated inFIG. 4, in the case that the control signal (On) is logic ‘0’, the first input NAND logic NI1outputs only logic ‘1’ regardless of a logic value of the input clock signal CLK_i. In the case that the control signal (On) is logic ‘1’, the first input NAND logic NI1inverts the input clock signal CLK_i to output the inverted input clock signal CLK_i to the node (n0).

Referring toFIG. 3again, a method of selecting the first through n+1th delay stages by the delay control code (Code_d[0:n]) will be described. Hereinafter, it is assumed that n is 5. For example, in the case where a delay control code Code_d[0:5] is ‘000000’, by a code value (logic ‘0’) of a Code_d[0] which is a most significant bit (MSB) of the delay control code Code_d[0:5], the second input NAND logic NI2ignores the input clock signal CLK_i transmitted through the node (n0) and outputs logic ‘1’ to a node (n1). The first feedback NAND logic NF1receives logic ‘1’ inverted by the first inverter I1to pass the input clock signal CLK_i transmitted through the node (n0). The passed input clock signal CLK_i is output as the output clock signal CLK_o by the first output NAND logic NO1.

As an example, it is assumed that the delay control code (Code_d[0:5]) is ‘110000’. In this case, the first and second feedback NAND logics NF1and NF2receive logic ‘0’ inverted by the first and second inverters I1and12and do not pass the input clock signal CLK_i transmitted through the node (n0) and the node (n1) to the next stage. The second and third input NAND logics NI2and NI3, which receive logic ‘1’, pass the input clock signal CLK_i. A clock signal transmitted through a node (n2) is not transmitted to the next stage by the fourth input NAND logic NI4that received logic ‘0’, but is transmitted to the third output NAND logic NO3by the third feedback NAND logic NF3that received logic ‘1’. As a result, the third delay stage is selected by the delay control code (Code_d[0:5]). The input clock signal CLK_i is output as the output clock signal CLK_o after the third delay TD3. Selection of the first through n+1th delay stages may be performed using substantially the same method as that described above.

FIGS. 5 and 6are timing diagrams illustrating an output clock signal according to an operation of a delay line ofFIG. 3according to an exemplary embodiment of the inventive concept.

Referring to the timing diagram ofFIG. 5, a change of the output clock signal CLK_o according to the value of the delay control code (Code_d[0:5]) is illustrated. For example, in the case where the delay control code (Code_d[0:5]) is ‘000000’, the input clock signal CLK_i is output as the output clock signal CLK_o after a delay time of the first delay TD1. In the case where the delay control code (Code_d[0:5]) is ‘100000’, the input clock signal CLK_i is output as the output clock signal CLK_o after a delay time of the second delay TD2. In the case where the delay control code (Code_d[0:5]) is ‘110000’, the input clock signal CLK_i is output as the output clock signal CLK_o after a delay time of the third delay TD3.

Referring to the timing diagram ofFIG. 6, a change of the output clock signal CLK_o according to the delay code Code_c[0:m] and the delay control code (Code_d[0:n]) is illustrated.FIG. 6will be described with reference toFIG. 1. Here, a time section (t0˜t1) is defined as a first cycle of the input clock signal CLK_i and a time section (t1˜t2) is defined as a second cycle of the input clock signal CLK_i.

In the time section (t0˜t1), the delay code generator140generates the delay code (Code_c[05]) with respect to the first cycle. For example, it is assumed that a phase of the delay clock signal CLK_d is ahead of that of the input clock signal CLK_i by a required delay (TD_required). The corresponding delay code (Code_c[0:1]) is adjusted to compensate the required delay (TD_required). For example, the corresponding delay code (Code_c[0:1]) may have a code value of ‘111000’. ‘111000’ may become an initial value of the delay code (Code_c[0:1]) by the delay controller150and be input to the delay line110. The delay line110delays the input clock signal CLK_i for the fourth delay TD4to generate the output clock signal CLK_o. As described above, ‘111000’, which is the code value of the initial delay code (Code_c[0:1]), may be maintained until the delay locked loop100is reset.

At t1, the phase detector130can still detect a phase difference between the delay clock signal CLK_d and the input clock signal CLK_i. In this case, the phase detector130adjusts a delay time of the delay line110in the second cycle in units of unit delays. When the phase detection signal by the phase detector130is the code falling signal (Code_down) (case1), the delay controller150outputs a code ‘110000’ as the delay control code (Code_d[0:1]). When the phase detection signal by the phase detector130is the code rising signal (Code_up) (case2), the delay controller150outputs a code ‘111100’ as the delay control code (Code_d[0:1]). In the example ofFIG. 6, it is assumed that the phase detector130outputs the code falling signal (Code_down).

At t2, the phase detector130detects that a phase difference between the delay clock signal CLK_d and the input clock signal CLK_i is within a certain range and then completes a coarse lock. Subsequently, the delay locked loop100may perform a fine lock process.

InFIG. 6, it is illustrated that the delay locked loop100completes a coarse lock at t2after the second cycle. However, the delay locked loop100may complete a coarse lock at t1after the first cycle or may complete the coarse lock after the second cycle. As described above, since the delay locked loop100scans the delay control code (Code_d[0:1]) not from ‘000000’ but from the initial code value ‘111000’ using the delay code (Code_c[0:1]), a time taken for the coarse lock process may be reduced.

FIG. 7is a block diagram illustrating a delay code generator ofFIG. 1according to an exemplary embodiment of the inventive concept. Referring toFIG. 7, the delay code generator140may include an error pulse generator141, a delay measuring circuit142, and a code generator143.

The error pulse generator141receives the input clock signal CLK_i and the delay clock signal CLK_d to detect a phase difference between them. Subsequently, the error pulse generator141generates an error pulse P_err having a pulse width which is in proportion to the phase difference. A configuration and operation of the error pulse generator141will be described below with reference toFIGS. 8 and 9.

The delay measuring circuit142receives the error pulse P_err from the error pulse generator141and generates measuring pulses whose number is proportional to the pulse width of the error pulse P_err. The delay measuring circuit142generates m number of measuring signals (Delay[0:m]) based on the measuring pulse and provides the generated m number of measuring signals (Delay[0:m]) to the code generator143. A configuration and operation of the delay measuring circuit142will be described below with reference toFIGS. 10 to 12.

The code generator143receives the measuring signals (Delay[0:m]) from the delay measuring circuit142to generate the delay code (Code_c[m:0]) having m+1 bits. A configuration and operation of the code generator143will be described below with reference toFIG. 13.

FIG. 8is a block diagram illustrating an error pulse generator ofFIG. 7according to an exemplary embodiment of the inventive concept. Referring toFIG. 8, the error pulse generator141may include first and second flip-flops FF1and FF2, a logical AND, and a logical OR.

The first flip-flop FF1receives a data signal DI as an input signal and discriminates data of the data signal DI by a rising edge of the input clock signal CLK_i to generate a first discriminating signal Q1. The second flip-flop FF2receives the data signal DI as an input signal and discriminates data of the data signal DI by a rising edge of the delay clock signal CLK_d to generate a second discriminating signal Q2.

The logical AND performs an AND operation on the first and second discriminating signals Q1and Q2to generate a pulse reset signal RST. The first and second flip-flops FF1and FF2receive the pulse reset signal RST to reset the first and second discriminating signals (Q1, Q2). The logical OR performs an OR operation on the first and second discriminating signals (Q1, Q2) to generate an error pulse P_err. Discriminating signals (Q1, Q2) of the first and second flop-flops FF1and FF2which are reset may have logic ‘0’. An operation of the error pulse generator141will be described below with reference toFIG. 9.

The first and second flop-flops FF1and FF2may discriminate the data signal DI based on a falling edge. For example, the error pulse generator141may stop an operation after the first cycle of the input clock signal CLK_i. As described above, this is to prevent an update of the delay code (Code_c[d:m]) by preventing generation of the error pulse P_err with respect to the second cycle and to maintain, by the delay code generator140, the initial delay code (Code_c[0:m]). To this end, the data signal DI may be controlled to maintain logic ‘1’ during the first cycle and to maintain logic ‘0’ after the first cycle.

FIG. 9is a timing diagram illustrating an error pulse according to an operation of the error pulse generator ofFIG. 8according to an exemplary embodiment of the inventive concept. Referring toFIG. 9, the error pulse generator141generates the error pulse P_err having a pulse width which is in proportion to a phase difference between the input clock signal CLK_i and the delay clock signal CLK_d.

At t0, the first flip-flop FF1discriminates the data signal DI of logic ‘1’ by the rising edge of the input clock signal CLK_i to generate the first discriminating signal Q1. The discriminating signal Q1has logic ‘1’. The second flip-flop FF2outputs logic ‘0’ which is an initial value as the second discriminating signal Q2.

At t1, the second flip-flop FF2discriminates the data signal DI of logic ‘1’ by the rising edge of the delay clock signal CLK_d to generate the second discriminating signal Q2. The second discriminating signal Q2has logic ‘1’.

At t1˜t2, the first and second discriminating signals (Q1, Q2) have logic ‘1’ and the logical AND receives the first and second discriminating signals (Q1, Q2) to generate the pulse reset signal RST of logic ‘1’. Accordingly, the first and second flip-flops FF1and FF2are reset and thus, the first and second discriminating signals (Q1, Q2) are reset to logic ‘0’. Consequently, the error pulse P_err is a pulse signal that maintains logic ‘1’ during a time section t0˜t1, which is a phase difference between the input clock signal CLK_i and the delay clock signal CLK_d.

For example, the time section t0˜t1may become the first cycle. As described above, the data signal DI may have logic ‘0’. Thus, at t2and t3, the first and second flip-flops (FF1, FF2) output logic ‘0’.

FIG. 10is a circuit diagram illustrating a delay measuring circuit ofFIG. 7according to an exemplary embodiment of the inventive concept. The delay measuring circuit142may include first through m+1th input NAND logics (NI1to NIm+1), first through m+1th feedback NAND logics (NF1to NFm+1), and first through m+1th output NAND logics (NO1to NOm+1).

The delay measuring circuit142does not include the first through n+1th inverters (N1to Nn+1) as compared with the delay line110ofFIG. 3. Accordingly, each of the second through m+1th input NAND logics (NI2to NIm+1) receives a driving voltage VDD as a control input signal.

The delay measuring circuit142may be designed to have substantially the same unit delay as the delay line110by modeling the delay line110. In other words, a configuration of a logical circuit constituting a delay stage of the delay measuring circuit142and first through m+1th delays (TD1to TDm+1) are substantially the same as a delay of the delay line110. Thus, a description thereof will be omitted. Herein, delay values obtained by subtracting a delay of one output NAND logic from the first through m+1th delay (TD1to TDm+1) are defined as first through m+1th error delays (TDD1to TDDm+1), respectively.

The delay measuring circuit142receives the error pulse P_err and generates first through m+1th error signals (Err_d1to Err_dm+1) which are output after the first through m+1th error delays (TDD1to TDDm+1). The delay measuring circuit142compares the first through m+1th error signals (Err_d1to Err_dm+1), which are output after being delayed for different delay times, with the error pulse P_err to generate a measuring pulse. Since the measuring pulse is generated only when the first through m+1th error signals (Err_d1to Err_dm+1) and the error pulse P_err output logic ‘1’, an output NAND that receives an error signal having a delay greater than the pulse width of the error pulse P_err cannot generate a measuring pulse. A method of generating a measuring pulse will be described in detail with reference toFIG. 11.

The delay measuring circuit142may be designed to have a delay k, or 1/k times as long as a unit delay, by modeling a size of the delay line1101/k or k times. The delay measuring circuit142may include a smaller number of delay stages as compared with the delay line110. In this case, as described with reference toFIG. 1, ‘m+1’, which is the number of bits of the measuring signal (Delay[0:m]) and the delay code (Code_c[0:m]), becomes smaller than ‘n+1’, which is the number of bits of the delay control code (Code_d[0:n]).

For example, since the error pulse P_err drives a plurality of output NANDs, the delay measuring circuit142may further comprise a buffer for reducing a drive loading of the error pulse P_err. The buffer may include a plurality of inverters.

FIG. 11is a timing diagram illustrating an operation of the delay measuring circuit ofFIG. 10according to an exemplary embodiment of the inventive concept.FIG. 11will be described with reference toFIGS. 7 through 10. Referring toFIG. 11, the delay measuring circuit142may generate measuring pulses whose number is proportional to the pulse width of the error pulse P_err.

The first feedback NAND logic NF1generates a first error signal Err_d1being delayed for a first error delay TDD1from the error pulse P_err. The first output NAND logic NO1performs an AND operation of the error pulse P_err and the first error signal Err_d1to generate a measuring pulse and outputs the generated measuring pulse as a measuring signal (Delay[0]). After that, the code generator143ofFIG. 7receives the measuring signal (Delay[0]) to generate a delay code (Code_c[0]) having logic ‘1’.

The second feedback NAND logic NF2generates a second error signal Err_d2being delayed for a second error delay TDD2from the error pulse P_err. The second output NAND logic NO2performs an AND operation of the error pulse P_err and the second error signal Err_d2to generate a measuring pulse and outputs the generated measuring pulse as a measuring signal (Delay[1]). After that, the code generator143receives the measuring signal (Delay[1]) to generate a delay code (Code_c[1]) having logic ‘1’.

In the case where the first through m+1th feedback NAND logic (NF1to NFm+1) are general NAND logics, the measuring signal Delay[0,1] may be output as a pulse signal whose value returns to an original value after a specific period of time. The first through m+1th feedback NAND logic (NF1to NFm+1) may be designed such that they charge a voltage level of logic ‘1’ as an initial value to maintain the voltage level, and voltage levels of their internal nodes are discharged according to an input signal to output logic ‘0’. This will be described below with reference toFIG. 12. Herein, the ‘measuring pulse’ is not a general pulse signal that outputs a logic level which is changed only during a certain time section, but is a signal of which a level is changed from logic ‘1’ to logic ‘0’ or from logic ‘0’ to logic ‘1’ to maintain the changed level. This is to distinguish between a measuring signal (Delay[0:m]) of which a level is changed and a measuring signal (Delay[0:m]) of which a level is not changed.

The third feedback NAND logic NF3generates a third error signal Err_d3being delayed for a third error delay TDD3from the error pulse P_err. The third output NAND logic NO3performs an AND operation of the error pulse P_err and the third error signal Err_d3to generate a measuring pulse and outputs the generated measuring pulse as a measuring signal (Delay[2]). Since the measuring signal (Delay[2]) maintains logic ‘0’, the code generator143receives the measuring signal (Delay[2]) to generate a delay code (Code_c[1]) having logic ‘0’.

Similarly, the third through m+1th feedback NAND logics (NF3to NFm+1) do not generate a measuring pulse. Thus, the delay measuring circuit142outputs each bit of measuring signals Delay[3:m] as logic ‘1’ and the code generator143outputs each bit of the delay codes (Code_c[3:m]) as logic ‘0’. Consequently, in the case where m is 5, the delay code (Code_c[0:1]) becomes a code ‘110000’.

FIG. 12is a circuit diagram illustrating an output NAND logic ofFIG. 10according to an exemplary embodiment of the inventive concept. Referring toFIG. 12, the delay measuring circuit142can maintain the initial delay code (Code_c[0:m]) after the first cycle of the input clock signal CLK_i.

Referring toFIG. 12, the first output NAND logic NO1is illustrated. An operation of the first output NAND logic NO1may be applied to the first through m+1th output NAND logics (NO1to Nom+1) illustrated inFIG. 11.

As illustrated above, the delay locked loop100may perform a new lock process by initializing, by a reset signal, the delay code (Code_c[0:m]) and the delay control signal (Code_d[0:n]). Here, a reset bar signal RSTb is a signal obtained by inverting the reset signal. The reset signal is a different signal from the pulse reset signal RST illustrated inFIG. 8.

The reset bar signal RSTb may maintain a level of logic ‘0’ before an operation of the delay locked loop100and maintain a level of logic ‘1’ after the operation of the delay locked loop100. Thus, a first PMOS transistor MP1is turned on by the reset bar signal RSTb before the operation of the delay locked loop100and a node (n1) is charged to a level of drive voltage VDD. After that, since the reset bar signal RSTb becomes logic ‘0’, the first PMOS transistor MP1and a second PMOS transistor MP2are turned off and the node (n1) maintains the level of the drive voltage VDD before first and second NMOS transistors MN1and MN2are turned on.

The first output NAND logic NO1may receive the error pulse P_err and the first error signal Err_d1by an operation of the delay measuring circuit142. The first and second NMOS transistors (MN1, MN2) are turned on by the error pulse P_err and the first error signal Err_d1, and then a node (n0) is discharged to a ground node GND, thus outputting a measuring signal Delay[0] of logic ‘0’.

As described above, when the error pulse generator141does not generate the error pulse P_err again after the first cycle, the first output NAND logic NO1does not receive a new error pulse P_err and the first error signal Err_d1. Thus, the measuring signal (Delay[0]) of the first output NAND logic NO1maintains logic ‘0’. The code generator143may make the delay code (Code_c[0]) to maintain logic ‘0’. The first through m+1th output NAND logics (NO1to Nom+1) perform substantially the same operation. Consequently, the delay code generator140may maintain the initial delay code (Code_c[0:m]) even after the first cycle.

FIG. 13is a circuit diagram illustrating a code generator ofFIG. 7according to an exemplary embodiment of the inventive concept. The code generator143may include first through m+1th latches (L1to Lm+1). Each of the first through m+1th latches (L1to Lm+1) may include a pair of inverters. Input and output nodes of one of the pair of inverters are connected to output and input nodes of the other of the pair of inverters, respectively. The code generator143receives measuring signals (Delay[0:m]), amplifies a signal level of each of the measuring signals (Delay[0:m]), and generates the delay code (Code_d[0:m]). The code generator143maintains the generated delay code (Code_d[0:m]).

FIG. 14is a block diagram illustrating a delay locked loop according to an exemplary embodiment of the inventive concept. A delay locked loop200may include a delay line210, a replica of internal delay220, a phase detector230, a delay code generator240, and a delay controller250. The delay code generator240may include a delay measuring circuit242and a code generator243. A configuration and operation of the delay locked loop200are substantially the same as those of the delay locked loop100ofFIG. 1, except for the phase detector230.

The phase detector230ofFIG. 14is connected to the replica of internal delay220, the delay code generator240, and the delay controller250. As compared with the phase detector130ofFIG. 1, the phase detector230receives the input clock signal CLK_i and the delay clock signal CLK_d to generate the phase detection signal and the error pulse P_err at substantially the same time. Since the phase detection signal and the error pulse P_err are generated based on the phase difference, they both can be generated by the phase detector230. A configuration and operation of the phase detector230will be described below with reference toFIGS. 15 and 16.

FIG. 15is a circuit diagram illustrating a phase detector ofFIG. 14according to an exemplary embodiment of the inventive concept. The phase detector230may include first and second flip-flops (FF1, FF2), a first logical AND (AND1), and a pulse generating circuit231. The pulse generating circuit231may include a logical NOR and a second logical AND (AND2). A configuration and operation of the first and second flip-flops (FF1, FF2) and the first logical AND (AND1) are substantially the same as those of the error pulse generator141ofFIG. 8. Thus, a description thereof is omitted.

The first and second flip-flops (FF1, FF2) do not receive the data signal DI but receive the drive signal VDD (as compared with the error pulse generator141ofFIG. 8). This is because the phase detector230may operate to perform a fine lock even after the first cycle or a coarse lock. Thus, the data signal DI is applied to the pulse generating circuit231.

As described above, the data signal DI may be controlled to maintain logic ‘1’ during the first cycle and maintain logic ‘1’ after the first cycle. Thus, while the data signal DI maintains logic ‘1’, the pulse generating circuit231operates as a general logical OR. While the data signal DI maintains logic ‘0’, the pulse generating circuit231outputs logic ‘0’ regardless of a change of an input signal. Thus, the phase detector230generates the same error pulse P_err as the error pulse generator141ofFIG. 8.

A process of generating the phase detection signal of the phase detector230is described below with reference toFIG. 16. As described above, the phase detection signal may include the code rising signal (Code_up) and the code falling signal (Code_down).

FIG. 16is a timing diagram illustrating a phase detection signal generating operation of the phase detector ofFIG. 15according to an exemplary embodiment of the inventive concept.FIG. 16will be described with reference toFIG. 15. Referring toFIG. 16, the phase detector230compares the input clock signal CLK_i and the delay clock signal CLK_d to generate the code rising signal (Code_up) or the code falling signal (Code_down). An operation of the phase detector230is substantially the same as the operation of the error pulse generator141ofFIG. 8. Thus, a detailed description thereof is omitted.

In a time section t0˜t1, the delay clock signal CLK_d is delayed compared to the input clock signal CLK_i to be input to the phase detector230. In this case, the first flip-flop FF1generates a pulse signal that maintains logic ‘1’ during the time section t0˜t1, which is a phase difference between the input clock signal CLK_i and the delay clock signal CLK_d. In this case, the second flip-flop FF2is reset by the pulse reset signal RST to output logic ‘0’.

In a time section t2˜t3, the input clock signal CLK_i is delayed compared to the delay clock signal CLK_d to be input to the phase detector230. In this case, the second flip-flop FF2generates a pulse signal that maintains logic ‘1’ during the time section t2˜t3, which is a phase difference between the input clock signal CLK_i and the delay clock signal CLK_d. In this case, the first flip-flop FF1is reset by the pulse reset signal RST to output logic ‘0’.

Consequently, the first discriminating signal Q1includes information that the delay clock signal CLK_d is delayed compared to the input clock signal CLK_i. The first discriminating signal Q1is output as the code falling signal (Code_down). The second discriminating signal Q2includes information that the delay clock signal CLK_d is delayed compared to the input clock signal CLK_i. The second discriminating signal Q2is output as the code rising signal (Code_up). The delay locked loop200adjusts a phase of the delay clock signal CLK_d according to the code falling signal (Code_down) or the code rising signal (Code_up).

FIG. 17is a block diagram illustrating a memory device including a delay locked loop according to an exemplary embodiment of the inventive concept. Referring toFIG. 17, a memory device1000may include a clock buffer1100, a delay locked loop1200, a duty cycle correction1300, a command decoder1400, an address latch1500, a memory cell array1600, a sense amplifier1610, a row decoder1620, a column decoder1630, a data input driver1700, and a data output driver1800.

For example, the memory device1000may be a volatile memory such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a thyristor RAM (TRAM), a zero capacitor RAM (Z-RAM), a twin transistor RAM (TTRAM), a MRMA, etc.

The clock buffer1100may receive a clock signal from a pad (CK_t, CK_c) to generate the input clock signal CLK_i. The delay locked loop1200may be designed to compensate a delay time that occurs due to the clock buffer1100and the data output driver1800that exist on a transmission path of the input clock signal CLK_i inside the DRAM device. The duty cycle correction1300receives the output clock signal CLK_o from the delay locked loop1200and then corrects a duty of the output clock signal CLK_o to provide the corrected output clock signal CLK_o to the data output driver1800.

The delay locked loop1200may correspond to the delay locked loop100or200described with reference toFIGS. 1 to 16. Thus, the delay locked loop1200may have a fast locking characteristic and thus, an operation time of the duty cycle correction1300is easily secured. Accordingly, an operation characteristic of the duty cycle correction1300may be guaranteed.

The command decoder1400receives various commands through a command pad CMD. The command decoder1400provides commands to circuit blocks such as the row decoder1620and the column decoder1630.

The address latch1500receives an address of a memory cell accessed through an address pad ADDR. In the case where data is stored in a memory cell or data is read out from a memory cell, an address ADDR that selects a memory cell may be provided through the address latch1500, the row decoder1620, and the column decoder1630.

The memory cell array1600may provide stored data to the data output driver1800through a sense amplifier1610. The memory cell array1600may store data received from the data input driver1700in a predetermined address through the sense amplifier1610. In this case, the row decoder1620and the column decoder1630may provide the address ADDR of a memory cell with respect to data to be inputted and outputted to the memory cell array1600.

The data output driver1800may output data stored in the memory cell array1600through a data pad DQ. When outputting data, the data output driver1800may output a data strobe signal through a strobe pad DQS.

The data input driver1700may receive data provided through the data pad DQ to provide the received data to the sense amplifier1610. When receiving data, the input driver1700may receive the data strobe signal through the strobe pad DQS.

FIG. 18is a block diagram of a user system including a volatile memory device according to an exemplary embodiment of the inventive concept. A user system2000includes an image processing unit2100, a wireless transmit/receive unit2200, an audio processing unit2300, an image file generating unit2400, a memory2500, a user interface2600, and a controller2700.

The image processing unit2100includes a lens2110, an image sensor2120, an image processor2130, and a display unit2140. The wireless transmit/receive unit2200includes an antenna2210, a transceiver2220, and a modem2230. The audio processing unit2300includes an audio processor2310, a mike2320, and a speaker2330.

The memory2500may be a memory module DIMM, a memory card (Multimedia Card (MMC), embedded MMC (eMMC), Secured Digital (SD), micro SD), etc. In addition, the controller2700may be provided as a system on chip that drives an application program, an operating system, etc. The controller2700may include the image processor2130or the modem2230.

The memory2500may be provided as a memory device including the delay locked loop100or200as described with reference toFIGS. 1 to 16. The memory2500may also be provided as a memory module including the memory device1000described with reference toFIGS. 1 to 17. The memory2500may perform a rapid lock even in an external variable environment to provide a stable clock inside the memory device and guarantee quality of output data.

As described above, according to exemplary embodiments of the inventive concept, a delay locked loop can complete a coarse lock in a relatively short amount of time. Thus, the delay locked loop can guarantee an operation time taken to perform a fine lock and a duty correction after the coarse lock and thus, a clock signal of high quality may be generated.