Methods of forming memory and methods of forming vertically-stacked structures

Some embodiments include constructions having electrically conductive bitlines within a stack of alternating electrically conductive wordline levels and electrically insulative levels. Cavities extend into the electrically conductive wordline levels, and phase change material is within the cavities. Some embodiments include methods of forming memory. An opening is formed through a stack of alternating electrically conductive levels and electrically insulative levels. Cavities are extended into the electrically conductive levels along the opening. Phase change material is formed within the cavities, and incorporated into vertically-stacked memory cells. An electrically conductive interconnect is formed within the opening, and is electrically coupled with a plurality of the vertically-stacked memory cells.

TECHNICAL FIELD

Semiconductor constructions, methods of forming memory, and methods of forming vertically-stacked structures.

BACKGROUND

Memory is one type of integrated circuitry, and is used in computer systems for storing data. Memory cells may be configured to retain or store memory in at least two different selectable states. In some memory cells, the different memory states may correspond to different physical states of a programmable material. For instance, phase change memory (PCM) may utilize ovonic memory materials (e.g., various chalcogenides) as programmable materials in memory cells; with the phase change materials being transformed from one phase to another through application of appropriate electrical stimulus.

The ovonic memory materials may be utilized in combination with selection devices, such as diodes or ovonic threshold switches.

A continuing goal with memory, including PCM, is to increase packing density of the memory across a semiconductor substrate. Accordingly, it is desired to develop new memory architectures, and new methods of forming memory architectures.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

In some embodiments, new processing is utilized to form vertically-stacked structures, such as, for example, vertically-stacked PCM cells. Some example embodiments are described with reference toFIGS. 1-35.

Referring toFIGS. 1-3, a semiconductor construction10includes an etchstop material14supported by a base12. A break is provided between the etchstop material14and the base12to indicate that there may be additional materials and/or integrated circuit structures between the base and the etchstop material in some embodiments.

The base12may comprise semiconductor material, and in some embodiments may comprise, consist essentially of, or consist of monocrystalline silicon. In some embodiments, base12may be considered to comprise a semiconductor substrate. The term “semiconductor substrate” means any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductor substrates described above. In some embodiments, base12may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit fabrication. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

The etchstop material14may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of aluminum oxide or tungsten silicide.

The electrically conductive levels18may comprise any suitable electrically conductive material; and in some embodiments may comprise, consist essentially of, or consist of one or more of various metals (for example, tungsten, titanium, etc.), metal-containing compositions (for example, metal nitride, metal carbide, metal silicide, etc.), and conductively-doped semiconductor materials (for example, conductively-doped silicon, conductively-doped germanium, etc.). For instance, in some embodiments the electrically conductive levels18may comprise, consist essentially of, or consist of tungsten.

In some embodiments, the electrically conductive levels18may be patterned into wordlines of a memory array. Such example processing may form vertically-stacked memory, with the number of memory cells in each vertical stack being determined by the number of wordline levels. A break is provided within the stack16to indicate that there may be more levels in the stack than are shown. The stack may have any number of wordline levels suitable to form a desired structure. For instance, in some embodiments the stack may have 8 wordline levels, 16 wordline levels, 32 wordline levels, 36 wordline levels, 64 wordline levels, 72 wordline levels, etc.

The electrically insulative levels20may comprise any suitable composition; and in some embodiments may comprise, consist essentially of or consist of silicon dioxide.

The electrically conductive levels18may be of any suitable thickness (T1), and in some embodiments may have a thickness within a range of from about 5 nm to about 300 nm; such as, for example, a thickness of about 30 nm. The electrically insulative levels20may be of any suitable thickness (T2), and in some embodiments may have a thickness within a range of from about 5 nm to about 200 nm; such as, for example, a thickness of about 20 nm.

In the shown embodiment, the base12has a substantially horizontal primary surface13. Some embodiments form vertically-extending structures. The vertically-extending structures may be considered to extend along a vertical direction; or, in other words, to extend along a direction which is substantially orthogonal to the horizontal primary surface13.

A hardmask material22is formed over stack16. The hardmask material22may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of silicon nitride.

Referring toFIGS. 4-6, trenches24-27are formed to extend through the stack16to the etchstop material14. The trenches may be formed with any suitable processing. For instance, in some embodiments a patterned masking material (not shown) may be formed over the hardmask material22to define locations of the trenches24-27, a pattern from the masking material may be transferred into hardmask material22with one or more suitable etches, and then the pattern may be transferred from the hardmask material into stack16with one or more suitable etches. The patterned masking material may be removed at some point subsequent to the patterning of hardmask material22. The masking material may comprise any suitable composition, and in some embodiments may comprise a photolithographically-patterned photoresist mask and/or a mask formed utilizing pitch-multiplication methodologies. In some embodiments, other materials (not shown) may be provided between a patterned masking material and the hardmask material22. For instance, if the masking material comprises photolithographically-patterned photoresist, an antireflective material (not shown) and a carbon-containing material (not shown) may be provided between the hardmask material22and the photoresist. Such materials may be removed during or after formation of the trenches within stack16to leave the construction shown inFIGS. 4-6.

In the shown embodiment ofFIGS. 4-6, trenches24-27are linear trenches which are substantially parallel to one another. The term “substantially parallel” means that the trenches are parallel to within reasonable tolerances of fabrication and measurement. Although the linear trenches ofFIGS. 4-6are shown to be separate from one another, in other embodiments (such as, for example, an embodiment described below with reference toFIGS. 32-35) a single serpentining trench may be formed which encompasses linear regions at the locations of trenches24-27.

Referring toFIGS. 7-9, electrically insulative fill material28is provided within trenches24-27(FIGS. 4-6) to form electrically insulative panels30-33within such trenches. The fill material may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of an electrical insulative oxide, such as, for example, silicon dioxide. The fill material may be formed by any suitable processing, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or physical vapor deposition (PVD). In the shown embodiment, a planarized surface35extends across fill material28and hardmask22. Such planarized surface may be formed by any suitable processing. For instance, in some embodiments the fill material28may be formed to overfill the trenches24-27(FIGS. 4-6), and subsequently chemical-mechanical polishing (CMP) may be utilized to form the planarized surface35.

In the shown embodiment, the panels30-33are rectangularly-shaped. Each panel has a pair of opposing sides37and39(shown relative to panel31) which are adjacent to stack16. The illustrated panels also have a pair of opposing ends41and43(shown relative to panel31) which are also adjacent to the stack16.

The panels30-33ofFIGS. 7-9are linear structures which are substantially parallel to one another. Although the panels ofFIGS. 7-9are shown to be separate from one another, in other embodiments (such as, for example, an embodiment described below with reference toFIGS. 32-35) a single serpentining panel may be formed which encompasses linear regions at the locations of panels30-33.

Referring toFIGS. 10-12, openings50-55are formed through panels30-33. The openings may be formed utilizing any suitable processing. For instance, in some embodiments a patterned masking material (not shown) may be formed over the material28to define locations of the openings50-55, and then a pattern may be transferred from the masking material into material28with one or more suitable etches. The patterned masking material may then be removed to leave the construction ofFIGS. 10-12. The masking material may comprise any suitable composition, and in some embodiments may comprise a photolithographically-patterned photoresist mask and/or a mask formed utilizing pitch-multiplication methodologies. In some embodiments, other materials (not shown) may be provided between a patterned masking material and the material28. For instance, if the masking material comprises photolithographically-patterned photoresist, an antireflective material (not shown) and a carbon-containing material (not shown) may be provided between the photoresist and the material28. Such antireflective material and/or carbon-containing material may be removed during or after formation of the openings50-55to leave the construction shown inFIGS. 10-12.

The formation of openings50-55may be considered to result from the removal of some sections of panels30-33. Other sections of the panels remain. For example, panel31is shown to comprise sections56and57remaining on opposing sides of opening52. In some embodiments, each of the openings50-55may be considered to have a first pair of opposing sides along stack16, and a second pair of opposing sides along remaining sections of the panels30-33. For instance, opening52is shown to comprise a first pair of opposing sides59and61along stack16, and to comprise a second pair of opposing sides63and65along the remaining sections56and57of panel31.

The openings50-55may have any suitable shape. Although the openings are square in the top view ofFIG. 10, in other embodiments the openings may have other shapes. For instance, in some embodiments the openings may be circular or elliptical when viewed in a top view analogous to that ofFIG. 10.

In the shown embodiment, the sidewalls of openings50-55are substantially vertical. In actual processing, such sidewalls may be tapered.

The openings may be formed to extend to the etch stop material14(as shown), or may be formed to extend through such etch stop material in other embodiments.

Referring toFIGS. 13-15, the electrically conductive levels18are etched along sidewalls of openings50-55to form cavities60(only some of which are labeled) extending into the conductive levels.

In some embodiments, the electrically conductive levels18comprise metal (for instance, tungsten), the electrically insulative levels20and electrically insulative material28comprise silicon dioxide, and the formation of cavities60utilizes isotropic etching which is substantially selective for the metal relative to the silicon dioxide.

The electrically conductive levels18have exposed edges62(only some of which are labeled) within the cavities60.

Referring toFIGS. 16-18, electrically conductive electrode material64is formed across upper surfaces of materials22and28, and within cavities60. The electrode material64may comprise any suitable composition; and in some embodiments may comprise, consist essentially of or consist of one or more of various metals (for example, tungsten, titanium, etc.), metal-containing compositions (for example, metal nitride, metal carbide, metal silicide, etc.), and conductively-doped semiconductor materials (for example, conductively-doped silicon, conductively-doped germanium, etc.). For instance, in some embodiments the electrode material64may comprise, consist essentially of, or consist of one or more of TiSiN, TiAlN, TiN, WN, Ti, C and W; where the formulas indicate the components within the listed compounds, rather than designating specific stoichiometries of such components.

The electrode material64may be referred to as first electrode material, or as bottom electrode material, in some embodiments.

Referring toFIGS. 19-21, the electrode material64is etched back to remove all of the material64except for that which is within cavities60(only some of which are labeled) and along surfaces of conductive levels18. The etching of material64may utilize any suitable processing, such as, for example, a timed isotropic etch. Such etching forms material64into a plurality of electrodes66. The electrodes66may be referred to as either first electrodes or bottom electrodes in some embodiments.

Referring toFIGS. 22-24, dielectric material67(only some of which is labeled) is formed within cavities60(only some of which are labeled). The material67lines the cavities, and thus forms electrically insulative liners within the cavities. Such liners may prevent shorting between electrodes66and other electrodes of PCM cells, as described below with reference toFIG. 31. The dielectric material may comprise any suitable material; such as, for example, silicon dioxide, aluminum oxide, silicon nitride, silicon oxynitride, hafnium oxide, etc. In some embodiments, the dielectric material67may be thin enough to avoid problematically interfering with cell performance, and yet thick enough to prevent undesired shorting between electrodes; and may, for example, have a thickness of from greater than 0 angstroms to less than or equal to about 20 angstroms; from greater than 0 angstroms to less than or equal to about 10 angstroms, etc. In some embodiments, the dielectric material67may be of appropriate composition to be incorporated into a cell select device (for instance, on ovonic threshold switch), or to be incorporated into phase change material; and in such embodiments the dielectric material may comprise, for example, oxide-containing ovonic material.

Referring toFIGS. 25-27, similar deposition and etchback methodologies to those described above relative to material64(i.e., the methodologies described above with reference toFIGS. 16-21) are utilized to deposit and pattern cell select device material68(only some of which is labeled), electrode material72(only some of which is labeled), phase change material76(only some of which is labeled), and electrode material80(only some of which is labeled).

The electrode materials72and80are patterned into electrodes74and82, respectively within the cavities60(some of which are labeled in, for example,FIG. 20). The electrode74may be referred to as a middle electrode, and thus the electrode material72may be referred to as middle electrode material. The electrode82may be referred to as a second electrode in some embodiments, or as a top electrode; and thus the electrode material80may be referred to as second electrode material, or as top electrode material. The electrode materials64,72and80may be the same composition as one another in some embodiments. In other embodiments, at least one of the electrode materials64,72and80may be a different composition relative to at least one other of the electrode materials64,72and80. In some embodiments, all of the electrode materials64,72and80comprise, consist essentially of, or consist of one or more of TiSiN, TiAIN, TiN, WN, Ti, C and W; where the formulas indicate the components within the listed compounds, rather than designating specific stoichiometries of such components.

The phase change material76is patterned into programmable units78(only some of which are labeled) within the cavities60(some of which are labeled in, for example,FIG. 20). The phase change material76may comprise any suitable composition or combination of compositions; and in some embodiments may be a chalcogenide. For instance, in some embodiments the phase change material may comprise one or more of germanium, antimony, tellurium and indium. The phase change material may, for example, comprise, consist essentially of or consist of GeSbTe or InGeTe; where the formulas indicate the components within the listed compounds, rather than designating specific stoichiometries of such components.

The cell select device material68is patterned cell select devices70(only some of which are labeled) within the cavities60(some of which are labeled in, for example,FIG. 20). The cell select devices70may correspond to ovonic threshold switches in some embodiments. In such embodiments, the cell select device material68may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of, or consist of one or more of germanium, arsenic, selenium, tellurium and silicon. The material68may, for example, comprise, consist essentially of, or consist of AsSe, AsSeGe, AsSeGeTe or AsGeTeSi; where the formulas indicate the components within the listed compounds, rather than designating specific stoichiometries of such components.

The relative thicknesses of materials64,68,72,76and80may be tailored for specific applications. For instance, all of the electrode materials64,72and80may be about the same thicknesses as one another (as shown), or in other embodiments at least one of the electrode materials may be thicker than at least one other of the electrode materials. Also, the phase change material76may be thicker than the cell select device material68(as shown), in other embodiments may be about the same thickness as the cell select device material, and in other embodiments may be thinner than the cell select device material.

Referring toFIGS. 28-30, electrically conductive interconnect material84is formed within openings50-55and along the electrode material82. In the shown embodiment, the material84entirely fills the openings50-55. In other embodiments, the material84may line the openings or otherwise not entirely fill the openings

The electrically conductive interconnect material84may comprise any suitable composition or combination of compositions; and in some embodiments may comprise, consist essentially of or consist of one or more of various metals (for example, tungsten, titanium, etc.), metal-containing compositions (for example, metal nitride, metal carbide, metal silicide, etc.), and conductively-doped semiconductor materials (for example, conductively-doped silicon, conductively-doped germanium, etc.). For instance, in some embodiments, the interconnect material may comprise, consist essentially of, or consist of tungsten.

In some embodiments, the interconnect material84may be patterned into bitlines86of a memory array, and in such embodiments the material84may be referred to as bitline material. In some embodiments, material84may be formed to overfill the openings50-55, and the patterning of material84may comprise removal of excess material (for example, utilizing chemical-mechanical polishing) to leave the shown construction.

FIG. 29shows that the electrodes66,74and82, together with the programmable units78and cell select devices70form a plurality of PCM cells88(only some of which are labeled inFIG. 29). The cells88may be considered to form a three-dimensional memory array; with rows of the array extending horizontally along the wordline levels18, and with columns of the array comprising vertically-stacked cells along bitlines86. In operation, each cell88may be uniquely addressed through the combination of a wordline and a bitline. In some embodiments, the interconnect material84within each of the openings50-55may be considered to form a bitline or other electrically conductive interconnect which electrically couples pluralities of the vertically-stacked memory cells88to one another.

The illustrated memory cells88are example memory cells, and in other embodiments other PCM cells may be formed. For instance, in some embodiments, one or both of the electrodes66and82may be omitted. As another example, in some embodiments the relative order of the programmable units78and cell select devices70may be reversed so that the cell select devices are formed after the programmable units, and thus are closer to the bitlines86than the programmable units. As another example, in some embodiments, the cell select devices70and middle electrodes74may be omitted.

In some embodiments, the first and second electrodes66and82within each memory cell88may be considered to be formed on opposing sides of the phase change material76within the memory cells. In the shown embodiment, the cell select devices70and middle electrodes74are also between the first and second electrodes, and the phase change material76is spaced from the cell select devices70by the middle electrodes74.

In some embodiments, the construction10ofFIGS. 28-30may be considered to be a memory array having material28configured as electrically insulative pillars90extending through the stack16. The construction further comprises bitlines86configured as conductive structures (e.g., wires) extending vertically through the stack16, with the bitline structures being between the electrically insulative pillars90. Each of the bitline structures may be considered to comprise a first pair of opposing sides87and89(shown relative to a bitline structure within opening52), and a second pair of opposing sides91and93(also shown relative to the bitline structure within opening52). In some embodiments, the bitline structures may be considered to be representative of electrically conductive interconnect structures that may be formed to extend vertically through the stack16.

The individual sides of the first pair of opposing sides are spaced from adjacent pillars90by intervening regions of stack16(shown inFIG. 29, where intervening regions of the stack are labeled as a region95between side87and one of the pillars90, and a region97between side89and another of the pillars90).

Each of the second pair of opposing sides91and93does not have any of the materials of stack16between it and the adjacent pillars90, as can be seen inFIG. 30.

The wordline levels18of the memory array ofFIGS. 28-30would be connected to other circuitry external of the memory array. Such connections may utilize any suitable landing pad structures, including, for example, so-called “shark-jaw” structures, “staircase” structures, etc. In some embodiments, (discussed below with reference toFIGS. 32-35), an elongated trench may be utilized to sub-divide the stack16and thereby simplify routing to landing pads and/or other circuitry.

In some embodiments, an electrode directly against the phase change material76(for instance, the electrode74in the shown embodiment) may correspond to a “heater” utilized to thermally induce a phase change within the programmable material. Such heater may consist essentially of, or consist of, TiSiN (where the formula indicates the components within the listed compound, rather than designating a specific stoichiometry of such components), in some embodiments.

FIG. 31shows an enlarged view of a fragment of the construction ofFIGS. 28-30(specifically, shows a view of the fragment along the line A-A ofFIGS. 29 and 30), and shows two memory cells88on opposing sides of a bitline86relative to one another. The dielectric material67surrounds a lateral periphery of a region of the memory cell, and prevents shorting between wordline levels18and electrode materials72and80.

FIG. 32shows a construction10aat a processing stage analogous to that ofFIG. 4. The construction comprises a single long trench120having linear regions24a-27ain locations analogous to the locations of trenches24-27ofFIG. 4. The trench120serpentines across construction10a, with the linear regions24a-27abeing joined to one another through curved regions121-123. In the shown embodiment, the linear regions24a-27aare substantially parallel to one another.

Referring toFIG. 33, the electrically insulative material28is formed within trench120with processing analogous to that described above with reference toFIG. 7. The electrically insulative material28forms a single long panel124within the trench120. Such panel comprises linear regions134-137within the linear regions24a-27aof trench120. The linear regions134-137are joined to one another by curved regions141-143of the panel.

Referring toFIG. 34, the openings50-55are formed to extend through the panel124with processing analogous to that described above with reference toFIG. 10. In the shown embodiment, the openings are only formed within the linear regions134-137of the panel, and not within the curved regions141-143.

An advantage of the embodiment ofFIG. 35is that the serpentining structure147can subdivide the wordline levels18(FIG. 29) into two separate groups. A first group is on a side150of the serpentining structure, and another group is on an opposing side152of the serpentining structure. The wordlines on side150may be considered to be a first set of wordlines, and those on side152may be considered to be a second set of wordlines. All of the wordlines within the first set that are at a common vertical level may be electrically coupled to one another, and electrically coupled to a common landing pad and/or to other common circuitry; and all of the wordlines within the second set that are at a common vertical level may be electrically coupled to one another, and electrically coupled to a common landing pad and/or to other common circuitry.

The serpentining structure147ofFIG. 35may be one of many substantially identical serpentining structures formed across a semiconductor construction during fabrication of a memory array.

Although the illustrated serpentining structure147has a single electrically insulative material28extending between the bitlines86and along the curved regions141-143, in other embodiments two or more electrically insulative materials may be utilized instead of the single electrically insulative material28. For instance, a different electrically insulative material may be utilized within the curved regions141-143than within linear regions between the bitlines86.

The structures and memory arrays discussed above may be incorporated into electronic systems. Such electronic systems may be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multilayer, multichip modules. The electronic systems may be any of a broad range of systems, such as, for example, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

The terms “dielectric” and “electrically insulative” are both utilized to describe materials having insulative electrical properties. Both terms are considered synonymous in this disclosure. The utilization of the term “dielectric” in some instances, and the term “electrically insulative” in other instances, is to provide language variation within this disclosure to simplify antecedent basis within the claims that follow, and is not utilized to indicate any significant chemical or electrical differences.

The cross-sectional views of the accompanying illustrations only show features within the planes of the cross-sections, and do not show materials behind the planes of the cross-sections in order to simplify the drawings.

When a structure is referred to above as being “on” or “against” another structure, it can be directly on the other structure or intervening structures may also be present. In contrast, when a structure is referred to as being “directly on” or “directly against” another structure, there are no intervening structures present. When a structure is referred to as being “connected” or “coupled” to another structure, it can be directly connected or coupled to the other structure, or intervening structures may be present. In contrast, when a structure is referred to as being “directly connected” or “directly coupled” to another structure, there are no intervening structures present.

Some embodiments include a method of forming memory. An opening is formed through a stack of alternating electrically conductive levels and electrically insulative levels. Cavities are formed to extend into the electrically conductive levels along the opening. Phase change material is formed within the cavities, and is incorporated into vertically-stacked memory cells. An electrically conductive interconnect is formed within the opening and is electrically coupled with a plurality of the vertically-stacked memory cells.

Some embodiments include a method of forming vertically-stacked structures. A stack of alternating electrically conductive levels and electrically insulative levels is formed. An electrically insulative panel is formed to extend through the stack. Some sections of the panel are removed while other sections are left remaining. Openings are formed where sections of the panel were removed. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive levels along the first pair of opposing sides of the openings. Phase change material is formed within the cavities.

Some embodiments include a method of forming memory. A stack of alternating electrically conductive wordline levels and electrically insulative levels is formed. A trench is formed to extend through the stack. An electrically insulative panel is formed within the trench. Some sections of the panel are removed while other sections are left remaining. Openings are formed where sections of the panel were removed. Each opening has a first pair of opposing sides along the stack, and has a second pair of opposing sides along remaining sections of the panel. Cavities are formed to extend into the electrically conductive wordline levels along the first pair of opposing sides of the openings. First electrode material is formed along exposed edges of the electrically conductive wordline levels within the cavities. After the first electrode material is formed, phase change material is formed within the cavities; and then second electrode material is formed within the cavities. Electrically conductive bitline material is formed within the openings and is spaced from the phase change material by at least the second electrode material.

Some embodiments include a semiconductor construction. A stack of alternating electrically wordline conductive levels and electrically insulative levels is over a semiconductor base. Bitlines extend into the stack. Cavities extend into the electrically conductive levels along the bitlines. Phase change material is within the cavities.

Some embodiments include a semiconductor construction. A stack of alternating electrically conductive levels and electrically insulative levels is over a semiconductor base. Electrically insulative pillars extend through the stack. Interconnect material structures are between the pillars. The interconnect material structures have a first pair of opposing sides and a second pair of opposing sides. The first pair of opposing sides are spaced from adjacent pillars by intervening regions of the stack. None of the stack is between each of the sides of the second pair of opposing sides and pillars adjacent such sides of the second pair. Cavities extend into the electrically conductive levels along the first pair of opposing sides of the interconnect material structures. Phase change material is within the cavities.