Method of making reinforced semiconductor package

A method of making a reinforced semiconductor package includes forming a semiconductor interconnect tablet (24). Formation of the tablet includes providing a plurality of conductive metal tabs (10), positioning a first end (12) of the tabs (10) in a first section of a mold chase (14), positioning a second section of the mold chase (16) over a second end (18) of the tabs (10), such that the tabs (10) are anchored between the first and second sections (14, 16) of the mold chase, loading the first and second sections (14, 16) of the mold chase into a molding system (20) and performing a molding operation such that a plastic mold compound (22) is formed around the metal tabs (10) and an interconnect tablet (24) is formed. Then the first and second sections (14, 16) of the mold chase are removed from the molding system (20) and the interconnect tablet (24) is removed from the first and second sections (14, 16) of the mold chase.

BACKGROUND OF THE INVENTION

The present invention relates to packaging of semiconductor devices in general and more specifically to a method of packaging a semiconductor device using a lead reinforced plastic tablet.

Small packages having high pin counts are in demand. There is pressure on the IC packing industry to provide ways to interconnect smaller circuits with more Inputs and Outputs (IOs). That is, very high density interconnects at die level must be translated to the much coarser pitch of printed circuit boards. Lead frames and interconnecting substrates are used to provide this IO pitch translation function. For example, a ball grid array (BGA) package uses an interposer substrate to convert the peripheral bonding sites of the die to an array configuration. Such interposers generally are made from ceramic materials having vias formed by drilling, punching, etching or laser that are metallized or filled with conductive metal. The processes for making interposers are difficult and expensive. Thus, a need exists for a method of making a high density package with fine pitch and high IO count interconnections at low cost.

Accordingly, it is an object of the present invention to provide a method of fabricating a low cost, high IO semiconductor package.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The detailed description set forth below in connection with the appended drawings is intended as a description of the presently preferred embodiments of the invention, and is not intended to represent the only form in which the present invention may be practiced. It is to be understood that the same or equivalent functions may be accomplished by different embodiments that are intended to be encompassed within the spirit and scope of the invention.

To achieve the objects and advantages discussed above and others, the present invention provides a method of forming a semiconductor interconnect tablet. The method includes the steps of providing a plurality of conductive metal tabs; positioning a first end of the tabs in a first section of a mold chase; and positioning a second section of the mold chase over a second end of the tabs, wherein the tabs are anchored between the first and second mold chases. The first and second sections of the mold chase are loaded into a molding system and a molding operation is performed, wherein a plastic mold compound is formed around the metal tabs, thereby forming an interconnect tablet. The first and second sections of the mold chase are removed from the molding system and the interconnect tablet is removed from the first and second mold sections of the mold chase.

The present invention also provides a method of forming a semiconductor device, which includes the steps outlined above for forming an interconnect tablet; performing a surface finishing operation on the interconnect tablet such that the first and second tab ends are generally coplanar with the plastic mold compound on top and bottom surfaces of the interconnect tablet; attaching an integrated circuit (IC) to the top surface of the interconnect tablet and electrically coupling the IC to the metal tabs of the interconnect tablet. Finally, the IC, electrical connections, and at least the top surface of the interconnect tablet are covered with an encapsulant.

FIGS. 1–8illustrate a method of making an interconnect tablet in accordance with an embodiment of the present invention.

Referring now toFIG. 1, a plurality of conductive metal tabs10are shown. The metal tabs10in this particular example are generally cylindrical in shape and have a length of about 1.0 to 2.0 millimeters (mm) and a diameter of about 0.2 mm to 1.2 mm. However, it should be understood that metal tabs of other shapes and dimensions may be employed as well, depending on the desired thickness of the interconnect tablet. The metal tabs10are formed of an electrically conductive material such as copper and may be plated with tin/gold.

Referring now toFIG. 2, first ends12of the tabs10are positioned in a first section of a mold chase14as shown. The first ends12of the metal tabs10may be positioned in the first section of the mold chase14via a shaking operation. Such shaking operations are known in the art. In this particular example, about 0.5 mm of the first ends12of the metal tabs10extend into the first section of the mold chase14. However, it should be understood that the present invention is not limited by the length of the metal tabs extending into the mold chase.

Referring now toFIG. 3, a second section of the mold chase16is positioned over a second end18of the tabs10such that the tabs10are anchored between the first and second sections14and16of the mold chase. The holes sizes are substantially the same as for the first section of the mold chase, where the metal tabs are smaller than the holes so that alignment between the two mold chases is easily carried out.

FIG. 4shows the first and second sections14and16of the mold chase loaded into a molding system20.FIG. 5illustrates a molding operation. Specifically, a plastic mold compound22is formed around the metal tabs10so as to form an interconnect tablet24. The metal tabs10serve as communication ports and also to reinforce the interconnect tablet24.FIG. 6shows the first14and second16sections of the mold chase removed from the molding system20.

Referring now toFIG. 7, the interconnect tablet24next is removed from the first14and second16sections of the mold chase as shown. As can be seen, the first and second ends12and18of the metal tabs10extend beyond the plastic mold compound22.FIG. 8shows the interconnect tablet24after a surface finishing operation has been performed such that the first and second tab ends12and18are generally coplanar with the plastic mold compound22on top and bottom surfaces of the interconnect tablet24. The surface finishing operation may include chemical wet etching, chemical dry etching, or surface grinding, as is known by those of skill in the art.

FIG. 9is a perspective view of an interconnect tablet30in accordance with an embodiment of the present invention. The interconnect tablet30comprises a plurality of conductive metal tabs32distributed within a plastic mold compound34. In the embodiment shown, the tabs32are arranged in a 4×7 matrix. However, those of skill in the art will understand that the pattern as well as the number of metal tabs32may vary depending on the application of the tablet34. The spacing between the tabs32may also vary depending on application. The metal tabs32serve as communication ports and also as reinforcement for the interconnect tablet30. Although the metal tabs32in this particular example are illustrated as having a cylindrical shape, it should be understood that the present invention is not limited by the shape of the metal tabs.

The interconnect tablet30illustrated inFIG. 9may be used to form a semiconductor device by attaching an integrated circuit (IC) to the top surface of the interconnect tablet30, electrically coupling the IC to the metal tabs32of the interconnect tablet30, and encapsulating the IC, electrical connections, and at least the top surface of the interconnect tablet30with an encapsulant.

FIG. 10is a cross-sectional view of an interconnect tablet40and an integrated circuit (IC)42attached thereto in accordance with an embodiment of the present invention. In the embodiment shown, the IC42may comprise any type of IC, such as a controller, a DSP, etc. The IC42is attached to the interconnect tablet40as a flip-chip. Specifically, the IC42is attached to the tablet40and electrically coupled to respective ones of a plurality of metal tabs44with a plurality of conductive balls46. Although not shown, the IC42and at least the top surface of the tablet52may be covered with a plastic encapsulant.

FIG. 11is a perspective view of an IC50attached to a surface of an interconnect tablet52in accordance with another embodiment of the present invention. The IC50may be attached to the interconnect tablet52with an adhesive. The IC50is electrically coupled to the interconnect tablet52by wire bonding a plurality of wires54between die bonding pads of the IC50and the metal tabs56of the interconnect tablet52. The wires54may be coated or insulated wires or bare wires.

FIG. 12Ais a cross-sectional view of a packaged semiconductor device60in accordance with an embodiment of the present invention. An IC62is electrically coupled to an interconnect tablet64by wire bonding a plurality of wires66between die bonding pads of the IC62and the metal tabs68of the interconnect tablet64. A glob top encapsulating process is then performed to encapsulate the IC62, electrical connections66, and at least a top surface of the interconnect tablet64with an encapsulant70.

FIG. 12Bis a cross-sectional view of a packaged semiconductor device80in accordance with another embodiment of the present invention. An IC82is electrically coupled to an interconnect tablet84by wire bonding a plurality of wires86between die bonding pads of the IC82and the metal tabs88of the interconnect tablet84. A molding process is then performed to encapsulate the IC82, electrical connections86, and at least a top surface of the interconnect tablet84with an encapsulant90.

As is evident from the foregoing discussion, the present invention provides a method of forming an interconnect tablet and a semiconductor device, which have benefits over existing processes. As an example, fine pitch packaging can be achieved with the present invention by employing finer metal tabs or reducing the spacing between metal tabs. In addition, the present invention provides a method of making a high density package with improved reliability at low cost by doing away with the need for intermediate substrates, thereby eliminating substrate processing costs and silicon to printed circuit board (PCB) thermal mismatch. Further, assembly and testing of semiconductor devices made in accordance with the present invention can be done in array (MAP) format, thereby achieving high throughput.

Thus it is apparent that there has been provided, in accordance with the invention, a method of forming a semiconductor device and a semiconductor device formed in accordance with such a method that fully meets the advantages set forth previously. Although the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these illustrative embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. For example, the metal tabs are not limited to copper, but may be any conductive material used in the art to form interconnections. As addressed earlier, the present invention is not limited by the shape of the metal tabs. Nor is the device configuration limited to flip chip and wire bond applications. It should be understood that the present invention may be implemented with multiple functional silicon die in stacked form by mixing flip chip and wire bond technologies on the same interconnect tablet. Furthermore, the present invention is not limited to those types of semiconductor die described or illustrated herein. Therefore, it is intended that this invention encompass all such variations and modifications as fall within the scope of the appended claims.