Multi-level signal receivers and memory systems including the same

A multi-level signal receiver includes a data sampler having (M−1) sense amplifiers therein, which are configured to compare a multi-level signal having one of M voltage levels with (M−1) reference voltages, to thereby generate (M−1) comparison signals. The data sampler is further configured to generate a target data signal including N bits, where M is an integer greater than two and N is an integer greater than one. An equalization controller is provided, which is configured to train the (M−1) sense amplifiers by: (i) adjusting at least one of (M−1) voltage intervals during a first training mode, and (ii) adjusting levels of the (M−1) reference voltages during a second training mode, based on equalized values of the (M−1) comparison signals, where each of the (M−1) voltage intervals represents a difference between two adjacent voltage levels from among the M voltage levels.

REFERENCE TO PRIORITY APPLICATION

This application claims priority under 35 USC § 119 to Korean Patent Application No. 10-2020-0111665, filed Sep. 2, 2020, the disclosure of which is hereby incorporated herein by reference.

BACKGROUND

1. Technical Field

Example embodiments relate generally to semiconductor integrated circuits and, more particularly, to signal transmitters and receivers and memory systems including the same.

2. Description of the Related Art

Semiconductor memory devices can generally be divided into two categories depending upon whether or not they retain stored data when disconnected from a power supply. These categories include: (i) volatile memory devices, which lose stored data when disconnected from a power supply, and (ii) nonvolatile memory devices, which retain stored data when disconnected from a power supply. Volatile memory devices may perform read and write operations at a relatively high speed, while contents stored therein may be lost when powered off. In contrast, nonvolatile memory devices may retain contents stored therein even when powered off, which means they may be used to store data that must be retained regardless of whether they are powered.

Recently, as the performance of semiconductor memory device has improved, a high communication speed (or interface speed) is required between a memory controller and the semiconductor memory device. To support these higher communication speeds, multi-level signaling, in which a plurality of bits are transmitted during one unit interval (UI), has been researched.

SUMMARY

At least one example embodiment of the present disclosure provides a multi-level signal receiver capable of training sense amplifiers based on multi-level signaling.

At least one example embodiment of the present disclosure provides a memory system including a multi-level signal receiver capable of training sense amplifiers based on multi-level signaling.

According to some example embodiments, a multi-level signal receiver includes a data sampler having (M−1) sense amplifiers therein, which are configured to compare a multi-level signal having one of M voltage levels with (M−1) reference voltages, to thereby generate (M−1) comparison signals. The data sampler is further configured to generate a target data signal including N bits, where M is an integer greater than two and N is an integer greater than one. An equalization controller is provided, which is configured to train the (M−1) sense amplifiers by: (i) adjusting at least one of (M−1) voltage intervals during a first training mode, and (ii) adjusting levels of the (M−1) reference voltages during a second training mode, based on equalized values of the (M−1) comparison signals, where each of the (M−1) voltage intervals represents a difference between two adjacent voltage levels from among the M voltage levels.

In some of these embodiments, the M voltage levels include a first voltage level, a second voltage level (greater than the first voltage level), a third voltage level (greater than the second voltage level), and a fourth voltage level (greater than the third voltage level). In addition, the (M−1) reference voltages include a first reference voltage, a second reference voltage greater than the first reference voltage, and a third reference voltage greater than the second reference voltage. In addition, the M−1 sense amplifiers can include a first sense amplifier, which is configured to: (i) compare the multi-level signal received at a first input terminal with the first reference voltage received at a second input terminal, and (ii) output a first comparison signal at an output terminal, responsive to a clock signal. A second sense amplifier is also provided, which is configured to: (i) compare the multi-level signal received at a first input terminal with the second reference voltage received at a second input terminal, and (ii) output a second comparison signal at an output terminal, responsive to the clock signal. A third sense amplifier is provided, which is configured to: (i) compare the multi-level signal received at a first input terminal with the third reference voltage received at a second input terminal, and (ii) output a third comparison signal at an output terminal, responsive to the clock signal. The data sampler further includes a clock generator configured to generate the clock signal, and an output decoder, which is configured to decode the first comparison signal, the second comparison signal and the third comparison signal, and to output the target data signal.

According to these embodiments, a first equalizer is also provided, which has an input responsive to an inverted version of the first comparison signal and an output electrically coupled to the first input terminal of the first sense amplifier. A second equalizer is provided, which has an input responsive to the first comparison signal and an output electrically coupled to the second input terminal of the first sense amplifier. In addition, the equalization controller is configured to enable the first equalizer during the first training mode, and the first equalizer is configured to provide the first input terminal of the first sense amplifier with an equalized version of the first comparison signal. The equalization controller is further configured to adjust a first control equalization coefficient, which is provided as an input to the first equalizer during the first training mode.

According to additional embodiments, a multi-level signal receiver includes a data sampler, a reference voltage generator and an equalization controller. The data sampler includes (M−1) sense amplifiers to compare a multi-level signal having one of M voltage levels different from each other, received from a channel with (M−1) reference voltages, and to generate (M−1) comparison signals. The data sampler generates a target data signal including N bits based on the (M−1) comparison signals. Here, M is an integer greater than two and N is an integer greater than one. The reference voltage generator generates the (M−1) reference voltages. The equalization controller advantageously trains the (M−1) sense amplifiers by adjusting at least one of (M−1) voltage intervals during a first training mode and by adjusting levels of the (M−1) reference voltages during a second training mode, based on equalized values of the (M−1) comparison signals. Each of the (M−1) voltage intervals represents a difference between two adjacent voltage levels from among the M voltage levels.

According to other example embodiments, a memory system to transmit data based on a multi-level signal having one of M (M being an integer greater than two) voltage levels different from each other, includes a memory controller and a memory device. The memory controller includes a transmitter to generate the multi-level signal based on the input data. The memory device, which is connected to the memory controller through a channel, includes at least one multi-level signal receiver to receive the multi-level signal from the channel and compares the multi-level signal with (M−1) reference voltages to generate a target data signal including N bits, where N is an integer greater than one. The at least one multi-level signal receiver includes a data sampler, a reference voltage generator and an equalization controller. The data sampler includes (M−1) sense amplifiers to compare the multi-level signal with the (M−1) reference voltages to generate (M−1) comparison signals. The reference voltage generator generates the (M−1) reference voltages. The equalization controller trains the (M−1) sense amplifiers by adjusting at least one of (M−1) voltage intervals in a first training mode, and by adjusting levels of the (M−1) reference voltages in second training mode, based on equalized values of the (M−1) comparison signals. Each of the (M−1) voltage intervals represents a difference between two adjacent voltage levels from among the M voltage levels.

According to further embodiments, a multi-level signal receiver includes a data sampler, a reference voltage generator and an equalization controller. The data sampler includes first through third sense amplifiers, which compare a multi-level signal having one of first through fourth voltage levels different from each other with respective first through third reference voltages to generate corresponding first through third comparison signals. The data sampler generates a target data signal including two bits based on the first through third comparison signals. A reference voltage generator is provided, which is configured to generate the first through third reference voltages. The equalization controller trains the (M−1) sense amplifiers by adjusting at least one of first through third voltage intervals in a first training mode and by adjusting levels of the first through third reference voltages in second training mode, based on equalized values of the first through third comparison signals. Each of the first through voltage intervals represents a difference between two adjacent voltage levels from among the first through fourth voltage levels. The first sense amplifier compares the multi-level signal with the first reference voltage to output the first comparison signal based on a clock signal. The second sense amplifier compares the multi-level signal with the second reference voltage to output the second comparison signal based on the clock signal. The third sense amplifier compares the multi-level signal with the third reference voltage to output the third comparison signal based on the clock signal. The second reference voltage has a level greater than a level of the first reference voltage and the third reference voltage has a level greater the level of the second reference voltage.

Accordingly, the multi-level signal receiver may use (M−1) sense amplifiers to compare a multi-level signal having one of M voltage levels different from each other with (M−1) reference voltages, and may train the (M−1) sense amplifiers by adjusting voltage intervals of the M voltage levels or levels of the (M−1) reference voltages by using equalizers. Therefore, the multi-level signal receiver may enhance performance.

DETAILED DESCRIPTION OF THE EMBODIMENTS

Various example embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are shown. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals refer to like elements throughout this application.

The multi-level signaling scheme may be used as a means of compressing the bandwidth required to transmit data at a given bit rate. In a simple binary scheme, two single symbols, usually two voltage levels, may be used to represent ‘1’ and ‘0,’ and thus the symbol rate may be equal to the bit rate. In contrast, the principle of the multi-level signaling scheme may be to use a larger alphabet of m symbols to represent data, so that each symbol may represent more than one bit of data. As a result, the number of symbols that needs to be transmitted may be less than the number of bits (e.g., the symbol rate may be less than the bit rate), and thus the bandwidth may be compressed. The alphabet of symbols may be constructed from a number of different voltage levels. For example, in a four-level scheme, groups of two data bits may be mapped to one of four symbols. Only one symbol need be transmitted for each pair of data bits, so the symbol rate may be a half of the bit rate.

In other words, the multi-level signaling scheme may be used to increase a data transmission (or transfer) rate without increasing the frequency of data transmission and/or a transmission power of the communicated data. An example of one type of the multi-level signaling scheme may be a pulse amplitude modulation (PAM) scheme, where a unique symbol of a multi-level signal may represent a plurality of bits of data. The number of possible pulse amplitudes in a digital PAM scheme may be some power of two. For example, there may be 22possible discrete pulse amplitudes in a 4-level PAM (e.g., in PAM4), there may be 23possible discrete pulse amplitudes in an 8-level PAM (e.g., in PAM8), and there may be 24possible discrete pulse amplitudes in a 16-level PAM (e.g., in PAM16). However, example embodiments are not limited thereto, and example embodiments may be applied or employed to a K-level PAM (e.g., PAM(K)) having K possible pulse amplitudes, where K is a natural number greater than or equal to three.

FIG.1is a block diagram illustrating a memory system according to example embodiments. Referring toFIG.1, a memory system10includes a memory controller100and a semiconductor memory device200. The memory system10may further include a plurality of signal lines30that electrically connect the memory controller100with the semiconductor memory device200. The semiconductor memory device200is at least partially controlled by the memory controller100. For example, based on requests from a host (not illustrated), the memory controller100may store (e.g., write or program) data into the semiconductor memory device200, or may retrieve (e.g., read or sense) data from the semiconductor memory device200.

The plurality of signal lines30may include control lines, command lines, address lines, data input/output (I/O) lines and power lines. The memory controller100may transmit a command CMD, an address ADDR and a control signal CTRL to the memory device40via the command lines, the address lines and the control lines, and may exchange a data signal MLDAT with the semiconductor memory device200via the data I/O lines, and may transmit a power supply voltage PWR to the semiconductor memory device200via the power lines. For example, the data signal MLDAT may be the multi-level signal that is generated and transmitted according to example embodiments. Although not illustrated inFIG.1, the plurality of signal lines30may further include data strobe signal (DQS) lines for transmitting a DQS signal.

In some example embodiments, at least a part or all of the signal lines30may be referred to as a channel. The term “channel” as used herein may represent signal lines that include the data I/O lines for transmitting the data signal MLDAT. However, example embodiments are not limited thereto, and the channel may further include the command lines for transmitting the command CMD and/or the address lines for transmitting the address ADDR.

FIGS.2and3are block diagrams illustrating an example of a memory system ofFIG.1. Referring toFIGS.2and3, a memory system11includes a memory controller101, a semiconductor memory device201and a plurality of channels31a,31band31c. The memory controller101may include a plurality of transmitters25a,25band25c, a plurality of receivers27a,27band27c, and a plurality of data I/O pads29a,29band29c. The semiconductor memory device201may include a plurality of transmitters45a,45band45c, a plurality of receivers47a,47band47c, and a plurality of data I/O pads49a,49band49c.

Advantageously, each of the plurality of transmitters25a,25b,25c,45a,45band45cmay generate a multi-level signal, and may perform the method of generating multi-level signal. Each of the plurality of receivers27a,27b,27c,47a,47band47cmay receive the multi-level signal. The plurality of transmitters25a,25b,25c,45a,45band45cand the plurality of receivers27a,27b,27c,47a,47band47cmay transmit and receive multi-level signal through the plurality of channels31a,31band31c. As shown, each of the plurality of data I/O pads29a,29b,29c,49a,49band49cmay be connected to a respective one of the plurality of transmitters25a,25b,25c,45a,45band45cand a respective one of the plurality of receivers27a,27b,27c,47a,47band47c. The plurality of channels31a,31band31cmay connect the memory controller201with the semiconductor memory device201. Each of the plurality of channels31a,31band31cmay be connected to a respective one of the plurality of transmitters25a,25band25cand a respective one of the plurality of receivers27a,27band27cthrough a respective one of the plurality of data I/O pads29a,29band29c. In addition, each of the plurality of channels31a,31band31cmay be connected to a respective one of the plurality of transmitters45a,45band45cand a respective one of the plurality of receivers47a,47band47cthrough a respective one of the plurality of data I/O pads49a,49band49c. The multi-level signal may be transmitted through each of the plurality of channels31a,31band31c.

FIG.2illustrates an operation of transferring data from the memory controller101to the semiconductor memory device201. For example, the transmitter25amay generate an output data signal DS11, which is the multi-level signal, based on input data DAT11, the output data signal DS11may be transmitted from the memory controller21to the memory device41through the channel31a, and the receiver47amay receive the output data signal DS11to obtain data ODAT11corresponding to the input data DAT11. Similarly, the transmitter25bmay generate an output data signal DS21, which is the multi-level signal, based on input data DAT21, the output data signal DS21may be transmitted to the memory device41through the channel31b, and the receiver47bmay receive the output data signal DS21to obtain data ODAT21corresponding to the input data DAT21. The transmitter25cmay generate an output data signal DSN1, which is the multi-level signal, based on input data DATN1, the output data signal DSN1may be transmitted to the semiconductor memory device201through the channel31c, and the receiver47cmay receive the output data signal DSN1to obtain data ODATN1corresponding to the input data DATN1. For example, the input data DAT11, DAT21and DATN1may be write data to be written into the semiconductor memory device201.

Alternatively,FIG.3illustrates an operation of transferring data from the semiconductor memory device201to the memory controller101. For example, the transmitter45amay generate an output data signal DS12, which is the multi-level signal, based on input data DAT12, and the output data signal DS12may be transmitted from the memory device41to the memory controller21through the channel31a, and the receiver27amay receive the output data signal DS12to obtain data ODAT12corresponding to the input data DAT12. Similarly, the transmitter45bmay generate an output data signal DS22, which is the multi-level signal, based on input data DAT22, and the output data signal DS22may be transmitted to the memory controller21through the channel31b, and the receiver27bmay receive the output data signal DS22to obtain data ODAT22corresponding to the input data DAT22. The transmitter45cmay generate an output data signal DSN2, which is the multi-level signal, based on input data DATN2, and the output data signal DSN2may be transmitted to the memory controller101through the channel31c, and the receiver27cmay receive the output data signal DSN2to obtain data ODATN2corresponding to the input data DATN2. For example, the input data DAT12, DAT22and DATN2may be read data retrieved from the semiconductor memory device201in response to a READ command issued by the memory controller101.

FIG.4is a block diagram illustrating an example of a memory controller included in a memory system according to example embodiments. Referring toFIG.4, a memory controller100may include at least one processor110, a buffer memory120, a host interface130, an error correction code (ECC) engine140and a memory interface150. The processor110may control an operation of the memory controller100in response to a command and/or request received via the host interface130from an external host (not illustrated). For example, the processor110may control respective components by employing firmware for operating a memory device (e.g., the semiconductor memory device200inFIG.1).

The buffer memory120may store instructions and data executed and processed by the processor110. For example, the buffer memory120may be implemented with a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), a cache memory, or the like. The host interface130may provide physical connections between the host and the memory controller100. The host interface130may provide an interface corresponding to a bus format of the host for communication between the host and the memory controller100.

The ECC engine140, which is provided for error correction, may perform coded modulation using a Bose-Chaudhuri-Hocquenghem (BCH) code, a low density parity check (LDPC) code, a turbo code, a Reed-Solomon code, a convolution code, a recursive systematic code (RSC), a trellis-coded modulation (TCM), a block coded modulation (BCM), etc., or may perform ECC encoding and ECC decoding using above-described codes or other error correction codes.

The memory interface150may exchange data with the semiconductor memory device200. The memory interface150may transmit a command and an address to the semiconductor memory device200, and may transmit data to the semiconductor memory device200or receive data read from the semiconductor memory device200. Although not illustrated inFIG.4, a transmitter (e.g., the transmitter25ainFIG.2), which generates the multi-level signal according to example embodiments, and a receiver (e.g., the receiver27ainFIG.2), which receives the multi-level signal, may be included in the memory interface150(see, e.g., memory controller101ofFIG.3).

FIG.5is a block diagram illustrating an example of the semiconductor memory device included in the memory system ofFIG.1, according to additional embodiments. Referring toFIG.5, the semiconductor memory device200aincludes the control logic circuit210, an address register220, a bank control logic230, a refresh counter245, a row address multiplexer240, a column address latch250, a row decoder260, a column decoder270, the memory cell array300, a sense amplifier unit285, an I/O gating circuit290, an error correction code (ECC) engine390, an on-die termination (ODT) circuit297and a data I/O buffer295. In some embodiments, the semiconductor memory device200amay be a volatile memory device and may include a dynamic random access memory (DRAM) device.

The memory cell array300includes first through eighth bank arrays310˜380. The row decoder260includes first through eighth bank row decoders260a˜260hrespectively coupled to the first through eighth bank arrays310˜380, the column decoder270includes first through eighth bank column decoders270a˜270hrespectively coupled to the first through eighth bank arrays310˜380, and the sense amplifier unit285includes first through eighth bank sense amplifiers285a˜285hrespectively coupled to the first through eighth bank arrays310˜380. The first through eighth bank arrays310˜380, the first through eighth bank row decoders260a˜260h, the first through eighth bank column decoders270a˜270hand first through eighth bank sense amplifiers285a˜285hmay form first through eighth banks. Each of the first through eighth bank arrays310˜380includes a plurality of memory cells MC formed at intersections of a plurality of word-lines WL and a plurality of bit-line BTL. The address register220receives the address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR and a column address COL_ADDR from the memory controller100. The address register220provides the received bank address BANK_ADDR to the bank control logic230, provides the received row address ROW_ADDR to the row address multiplexer240, and provides the received column address COL_ADDR to the column address latch250. The bank control logic230generates bank control signals in response to the bank address BANK_ADDR. One of the first through eighth bank row decoders260a˜260hcorresponding to the bank address BANK_ADDR is activated in response to the bank control signals, and one of the first through eighth bank column decoders270a˜270hcorresponding to the bank address BANK_ADDR is activated in response to the bank control signals.

The row address multiplexer240receives the row address ROW_ADDR from the address register220, and receives a refresh row address REF_ADDR from the refresh counter245. The row address multiplexer240selectively outputs the row address ROW_ADDR or the refresh row address REF_ADDR as a row address RA. The row address RA that is output from the row address multiplexer240is applied to the first through eighth bank row decoders260a˜260h. The refresh counter245may sequentially output the refresh row address REF_ADDR under control of the control logic circuit210. The activated one of the first through eighth bank row decoders260a˜260h, by the bank control logic230, decodes the row address RA that is output from the row address multiplexer240, and activates a word-line corresponding to the row address RA. For example, the activated bank row decoder applies a word-line driving voltage to the word-line corresponding to the row address.

The column address latch250receives the column address COL_ADDR from the address register220, and temporarily stores the received column address COL_ADDR. In some embodiments, in a burst mode, the column address latch250generates column addresses that increment from the received column address COL_ADDR. The column address latch250applies the temporarily stored or generated column address to the first through eighth bank column decoders270a˜270h. The activated one of the first through eighth bank column decoders270a˜270hactivates a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I/O gating circuit290. The I/O gating circuit290includes a circuitry for gating input/output data, and further includes input data mask logic, read data latches for storing data that is output from the first through eighth bank arrays310˜380, and write drivers for writing data to the first through eighth bank arrays310˜380.

Codeword CW read from one bank array of the first through eighth bank arrays310˜380is sensed by a sense amplifier coupled to the one bank array from which the data is to be read, and is stored in the read data latches. The codeword CW stored in the read data latches may be provided to the memory controller100via the data I/O buffer295after ECC decoding is performed on the codeword CW by the ECC engine390. The data DQ to be written in one bank array of the first through eighth bank arrays310˜380may be provided to the data I/O buffer295from the memory controller100, and may be provided to the ECC engine390from the data I/O buffer295. And, the ECC engine390may perform an ECC encoding on the data DQ to generate parity bits, and may provide the data DQ and the parity bits to the I/O gating circuit290, which may write the data DQ and the parity bits in a sub-page in one bank array through the write drivers.

The data I/O buffer295may provide the target data signal DQ100to the ECC engine390in a write operation of the semiconductor memory device200a, and may provide the data signal DQ from the ECC engine390to the memory controller100in a read operation of the semiconductor memory device200a. The data I/O buffer295may include a multi-level signal receiver according to example embodiments, may decode the multi-level data MLDAT into a target data signal, and may provide the target data signal to the ECC engine390in a write operation. The ECC engine390may perform ECC encoding and ECC decoding on the target data signal DQ according to a control of the control logic circuit210.

The control logic circuit210may control operations of the semiconductor memory device200a. For example, the control logic circuit210may generate control signals for the semiconductor memory device200ain order to perform a write operation or a read operation. The control logic circuit210includes a command decoder211that decodes the command CMD received from the memory controller100and a mode register212that sets an operation mode of the semiconductor memory device200a. For example, the command decoder211may generate the control signals corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, and a chip select signal, etc.

The ODT circuit297may be connected to a data I/O pad299and the data I/O buffer295. When the ODT circuit297is enabled, the ODT circuit297may perform an ODT operation. When the ODT operation is performed, signal integrity of the transmitted/received signal may be enhanced by preventing signal reflection due to impedance matching.

Although the memory device included in the memory system according to example embodiments is described based on a DRAM, the memory device according to example embodiments may be any volatile memory device (e.g., SRAM), and/or any nonvolatile memory device, e.g., a flash memory, a phase random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), a thyristor random access memory (TRAM), etc.

Hereinafter, example embodiments will be described in detail based on various examples of the multi-level signaling scheme (e.g., the PAM scheme) and various examples of the transmitter according thereto. In particular,FIGS.6and7are diagrams for describing a data signal generated by a method of generating a multi-level signal according to example embodiments. For example,FIG.6illustrates an ideal eye diagram of a data signal (e.g., a PAM4 signal) generated based on the 4-level scheme (e.g., the PAM4 scheme), whereasFIG.7is a simplified diagram illustrating the eye diagram ofFIG.6. Referring toFIG.6, an eye diagram may be used to indicate the quality of signals in high-speed transmissions. For example, the eye diagram may represent four symbols of a signal (e.g., ‘00,’ ‘01,’ ‘10’ and ‘11’), and each of the four symbols may be represented by a respective one of different voltage levels (e.g., voltage amplitudes) VL11, VL21, VL31and VL41. The eye diagram may be used to provide a visual indication of the health of the signal integrity, and may indicate noise margins of the data signal.

To generate the eye diagram, an oscilloscope or other computing device may sample a digital signal according to a sample period SP (e.g., a unit interval or a bit period). The sample period SP may be defined by a clock associated with the transmission of the measured signal. The oscilloscope or other computing device may measure the voltage level of the signal during the sample period SP to form the plurality of traces TRC. Various characteristics associated with the measured signal may be determined by overlaying the plurality of traces TRC.

As will be understood by those skilled in the art, an eye diagram may be used to identify a number of characteristics of a communication signal such as jitter, crosstalk, electromagnetic interference (EMI), signal loss, signal-to-noise ratio (SNR), other characteristics, or combinations thereof. For example, a width W of an eye in the eye diagram may be used to indicate a timing synchronization of the measured signal or jitter effects of the measured signal. For example, the eye diagram may indicate an eye opening OP, which represents a peak-to-peak voltage difference between the various voltage levels VL11, VL21, VL31and VL41. The eye opening OP may be related to a voltage margin for discriminating between different voltage levels VL11, VL21, VL31and VL41of the measured signal. The eye opening OP may correspond to the voltage interval described with reference toFIG.1. For example, the eye diagram may be used to identify a rise time RT and/or a fall time FT for transitions from a first amplitude to a second amplitude. The rise time RT or the fall time FT may indicate a time required for transitioning from one voltage level to another voltage level, and may be related to or associated with a rising edge and a falling edge, respectively. The jitter JT may refer to a timing error which results from a misalignment of rise and fall times. The jitter JT may occur when the rising edge or the falling edge occurs at a time that is different from an ideal time defined by the data clock.

Referring toFIG.7, different first, second, third and fourth voltage levels VL11, VL21, VL31and VL41of the data signal that is the PAM4 signal are illustrated, different first, second and third voltage intervals VOH11, VOH21and VOH31of the data signal are illustrated, and a voltage swing width VSW1of the data signal is illustrated. The first voltage level VL11that is the lowest voltage level may be lower than the second voltage level VL21, the second voltage level VL21may be lower than the third voltage level VL31, and the third voltage level VL31may be lower than the fourth voltage level VL41, which is the highest voltage level. In addition, the first voltage interval VOH11may represent a difference between the first and second voltage levels VL11and VL21, the second voltage interval VOH21may represent a difference between the second and third voltage levels VL21and VL31, the third voltage interval VOH31may represent a difference between the third and fourth voltage levels VL31and VL41, and the voltage swing width VSW1may represent a difference between the first and fourth voltage levels VL11and VL41.

FIG.8is a block diagram illustrating a transmitter according to example embodiments. Referring toFIG.8, a transmitter400includes a pull-up/pull-down control circuit420, a voltage setting circuit430and a driver circuit440. The transmitter400may further include a multiplexer410and a data I/O pad450. The multiplexer410may receive input data DAT1including two or more bits D0and D1, and may divide the input data DAT1into the two or more bits D0and D1. The pull-up/pull-down control circuit420generates two or more pull-up control signals PUS1and PUS2and two or more pull-down control signals PDS1and PDS2based on the input data DAT1(e.g., the two or more bits D0and D1) and voltage setting control signals VSU1and VSD1. The voltage setting circuit430performs a voltage setting operation for voltage intervals of a multi-level signal and generates the voltage setting control signals VSU1and VSD1that represent a result of the voltage setting operation. The driver circuit440generates an output data signal DS1that is the multi-level signal based on the two or more pull-up control signals PUS1and PUS2and the two or more pull-down control signals PDS1and PDS2. The data I/O pad450may output the output data signal DS1. The multi-level signal has one of M voltage levels. When the voltage setting operation is performed, M−1 voltage intervals each of which represents a difference between two adjacent voltage levels are different from each other.

Based on a characteristic data CDAT, the voltage setting circuit430may select at least one voltage level to be adjusted and may generate the voltage setting control signals VSU1and VSD1. The characteristic data CDAT may represent a characteristic of a channel that transmits the output data signal DS1. The characteristic data CDAT may be generated based on a training operation on a multi-level signal receiver in the semiconductor memory device200and the semiconductor memory device200may transmit the characteristic data CDAT to the voltage setting circuit430. In example embodiments, an eye monitor circuit (such as an eye monitor circuit51a) in the semiconductor memory device200may transmit the characteristic data CDAT to the voltage setting circuit430based on the training result.

In an example ofFIG.8, the input data DAT1may include a first bit D0and a second bit D1that are different from each other, and the multiplexer410may divide the input data DAT1into the first bit D0and the second bit D1based on a four-phase clock signal CK_4P. In some example embodiments, the first bit D0may be a least significant bit (LSB) of the input data DAT1, and the second bit D1may be a most significant bit (MSB) of the input data DAT1.

FIGS.9and10are diagrams illustrating examples of a driver circuit included in a transmitter ofFIG.8. Referring toFIG.9, the driver circuit440may include a first pull-up circuit441, a second pull-up circuit443, a first pull-down circuit445and a second pull-down circuit447. The first pull-up circuit441may pull up the data I/O pad450based on the first pull-up control signal PUS1. The second pull-up circuit443may pull up the data I/O pad450based on the second pull-up control signal PUS2. The first pull-down circuit445may pull down the data I/O pad450based on the first pull-down control signal PDS1. The second pull-down circuit447may pull down the data I/O pad450based on the second pull-down control signal PDS2.

And, as shown byFIG.10, a driver circuit440amay include a first pull-up circuit441a, a second pull-up circuit443a, a first pull-down circuit445aand a second pull-down circuit447a. The first pull-up circuit441amay include a plurality of first pull-up transistors T11, . . . , T1X that are connected in parallel between a power supply voltage and the data I/O pad450. The plurality of first pull-up transistors T11, . . . , T1X may be selectively turned on based on the first pull-up control signal PUS1. The second pull-up circuit443amay include a plurality of second pull-up transistors T21, T22, . . . , T2Y that are connected in parallel between the power supply voltage and the data I/O pad450. The plurality of second pull-up transistors T21, T22, . . . , T2Y may be selectively turned on based on the second pull-up control signal PUS2.

Thus, when it is required to pull up the output data signal DS1to the second voltage level VL21, the first pull-up circuit441amay be enabled or activated by turning on at least some of the plurality of first pull-up transistors T11, . . . , T1X based on the first pull-up control signal PUS1. In this case, the second voltage level VL21may be adjusted by controlling the number (or quantity) of the plurality of first pull-up transistors T11, . . . , T1X that are turned on. For example, the second voltage level VL21may increase as the number of the plurality of first pull-up transistors T11, . . . , T1X that are turned on increases. Similarly, when it is required to pull up the output data signal DS1to the third voltage level VL31, the second pull-up circuit443amay be enabled based on the second pull-up control signal PUS2, and the third voltage level VL31may be adjusted by controlling the number of the plurality of second pull-up transistors T21, T22, . . . , T2Y that are turned on. And, when it is required to pull up the output data signal DS1to the fourth voltage level VL41, both the first and second pull-up circuits441aand443amay be simultaneously enabled based on the first and second pull-up control signals PUS1and PUS2, and the fourth voltage level VL41may be adjusted by controlling the number of the plurality of first pull-up transistors T11, . . . , T1X and the plurality of second pull-up transistors T21, T22, . . . , T2Y that are turned on. When at least one of the second, third and fourth voltage levels VL21, VL31and VL41are adjusted as described above, the voltage intervals and the voltage swing width may be adjusted.

The first pull-down circuit44amay include a plurality of first pull-down transistors T31, . . . , T3X that are connected in parallel between the data I/O pad450and a ground voltage. The plurality of first pull-down transistors T31, . . . , T3X may be selectively turned on based on the first pull-down control signal PDS1. The second pull-down circuit447amay include a plurality of second pull-down transistors T41, T42, . . . , T4Y that are connected in parallel between the data I/O pad450and the ground voltage. The plurality of second pull-down transistors T41, T42, . . . , T4Y may be selectively turned on based on the second pull-down control signal PDS2. Operations of the first and second pull-down circuits445aand447amay be similar to the operations of the first and second pull-up circuits441aand443a.

FIGS.11A and11Bare diagrams for describing operations performed by a method of generating a multi-level signal and a transmitter according to example embodiments. Referring toFIG.11A, as the voltage interval adjustment and the voltage swing width adjustment are performed on the output data signal, voltage levels VL11a, VL21a, VL31aand VL41amay be adjusted, and voltage intervals VOH11a, VOH21aand VOH31aand a voltage swing width VSW1amay be changed. As compared with the example ofFIG.6B, the first and second voltage intervals VOH11aand VOH21aand the voltage swing width VSW1amay increase in an example ofFIG.11A, and the third voltage interval VOH31amay decrease in the example ofFIG.11A. In addition, in the example ofFIG.9A, the first, second and third voltage intervals VOH11a, VOH21aand VOH31amay be different from each other, and the first voltage interval VOH11amay be less than the second voltage interval VOH21aand may be larger than the third voltage interval VOH31a.

Referring toFIG.11B, as the voltage interval adjustment and the voltage swing width adjustment are performed on the output data signal, voltage levels VL11b, VL21b, VL31band VL41bmay be adjusted, and voltage intervals VOH11b, VOH21band VOH31band a voltage swing width VSW1bmay be changed. As compared with the example ofFIG.7, the first voltage interval VOH11band the voltage swing width VSW1bmay increase in an example ofFIG.11B, and the second and third voltage intervals VOH21band VOH31bmay decrease in the example ofFIG.11B. In addition, in the example ofFIG.9B, the first voltage interval VOH11bmay be larger than the second and third voltage intervals VOH21band VOH31b, and the second and third voltage intervals VOH21band VOH31bmay be equal to each other.

FIG.12is a diagram for describing a data signal generated by a method of generating a multi-level signal according to example embodiments. The descriptions repeated withFIG.7will be omitted. Referring toFIG.12: (i) different first, second, third, fourth, fifth, sixth, seventh and eighth voltage levels VL12, VL22, VL32, VL42, VL52, VL62, VL72and VL82of a data signal (e.g., a PAM8 signal) that is generated based on the 8-level scheme (e.g., the PAM8 scheme) are illustrated, (ii) different first, second, third, fourth, fifth, sixth and seventh voltage intervals VOH12, VOH22, VOH32, VOH42, VOH52, VOH62and VOH72of the data signal are illustrated, and (iii) a voltage swing width VSW2of the data signal is illustrated. As described above, the selective level change for adjusting the voltage intervals and/or the voltage swing width may be performed.

FIG.13is a block diagram illustrating a transmitter according to example embodiments. The descriptions repeated withFIG.8will be omitted. Referring toFIG.13, a transmitter460includes a pull-up/pull-down control circuit470, a voltage setting circuit475and a driver circuit480. The transmitter460may further include a multiplexer465and a data I/O pad490, as shown.

In an example ofFIG.13, input data DAT2may include a first bit D0, a second bit D1and a third bit D2that are different from each other, and the multiplexer465may divide the input data DAT2into the first, second and third bits D0, D1and D2based on an eight-phase clock signal CK_8P. An output data signal DS2may correspond to the data signal illustrated inFIG.12, and may have one of the first, second, third, fourth, fifth, sixth, seventh and eighth voltage levels VL12, VL22, VL32, VL42, VL52, VL62, VL72and VL82, that are different from each other, during one unit interval. The voltage setting operation may be performed by adjusting at least one of the voltage levels VL12, VL22, VL32, VL42, VL52, VL62, VL72and VL82.

In some example embodiments, the first bit D0may be a LSB of the input data DAT2, the second bit D1may be a central significant bit (CSB) of the input data DAT2, and the third bit D2may be an MSB of the input data DAT2. Based on the characteristic data CDAT, the voltage setting circuit475may generate the voltage setting control signals VSU2and VSD2. The pull-up/pull-down control circuit470may generate pull-up control signals PUS1, PSU2, PUS3and pull-down control signals PDS1, PDS2, PDS3and may provide the pull-up control signals PUS1, PSU2, PUS3and pull-down control signals PDS1, PDS2, PDS3to the driver circuit480.

FIG.14is a block diagram illustrating a multi-level signal receiver according to example embodiments. Referring toFIG.14, a multi-level signal receiver500may include a data sampler505, a reference voltage generator600, and an equalization controller650. InFIG.14, a storage device670, which may be external to the multi-level signal receiver500, is illustrated for convenience of explanation.

The data sampler505(i) receives a multi-level (data) signal MLDAT having one of M voltage levels different from each other, (ii) compares the multi-level signal MLDAT with (M−1) reference voltages VREF1˜VREF (M−1), (iii) generates (M−1) comparison signals CS1˜CS (M−1), and (iv) generates target data signal DQ including N bits based on the (M−1) comparison signals CS1˜CS (M−1). Here, M is an integer greater than two and N is an integer greater than one. The data sampler505may include (M−1) sense amplifiers

As shown, the reference voltage generator600may generate the (M−1) reference voltages VREF1˜VREF (M−1) and may provide the (M−1) reference voltages VREF1˜VREF (M−1) to the data sampler505. In addition, the equalization controller650may train the (M−1) sense amplifiers by adjusting at least one of (M−1) voltage intervals when operating in a first training mode, and by adjusting levels of the (M−1) reference voltages VREF1˜VREF (M−1) when operating in a second training mode, based on equalized values of the (M−1) comparison signals CS1˜CS (M−1). Here, each of the (M−1) voltage intervals represents a difference between two adjacent voltage levels from among the M voltage levels. The equalization controller650may perform the training by providing control equalization coefficients CWs to equalizers within the data sampler505. In addition, the equalization controller650may store control code set CDST associated with equalization coefficients of equalizers associated with the (M−1) sense amplifiers in the storage device670based on the training. The equalization controller650may also provide the reference voltage generator600with a reference switch control signal RSC to adjust levels of the (M−1) reference voltages VREF1˜VREF (M−1).

FIG.15Ais a block diagram illustrating an example of the data sampler in the multi-level signal receiver ofFIG.14, according to example embodiments. InFIG.15A, it is assumed that the value of M is four and the value of N is two. Referring toFIG.15A, a data sampler505amay include first through sense amplifiers510,520and530, a clock generator540and an output decoder550. The data sampler505amay further include first equalizers EQ11, EQ21and EQ31, second equalizers EQ12, EQ22and EQ32and inverters INV1, INV2and INV3.

The clock generator540generates the clock signal CK and provides the clock signal CK to the first through sense amplifiers510,520and530. In an embodiment, the clock generator540may generate the clock signal CK as a double data rate (DDR) clock signal, a four-phase clock signal, or an eight-phase clock signal.

The first sense amplifier510may compare the multi-level signal MLDAT received at a first input terminal with a first reference voltage VREF1received at a second input terminal based on the clock signal CK, and output a first comparison signal CS1to the output decoder550. Similarly, the second sense amplifier520may compare the multi-level signal MLDAT received at a first input terminal with a second reference voltage VREF2received at a second input terminal based on the clock signal CK, and output a second comparison signal CS2to the output decoder550. The third sense amplifier530may compare the multi-level signal MLDAT received at a first input terminal with a third reference voltage VREF3received at a second input terminal based on the clock signal CK, and output a third comparison signal CS3to the output decoder550.

As shown byFIG.15A, each of the first equalizers EQ11, EQ21and EQ31receive corresponding signals (i.e., “inverted” comparison signals) from the output terminals of respective inverters INV1, INV2and INV3, and are also responsive to respective first enable signals EN11, EN21and EN31, which operate to enable/disable the respective equalizer. Furthermore, each of the first equalizers EQ11, EQ21and EQ31generate respective first equalized values (at outputs thereof) by equalizing respective ones of the “inverted” comparison signals (i.e., /CS1, /CS2and /CS3) generated by the inverters INV1, INV2and INV3. In addition, each of the adders551,553and555may pass a corresponding output from the first equalizers EQ11, EQ21and EQ31to a corresponding first input terminal of the first through third sense amplifiers510,520and530(i.e., SA1, SA2, SA3).

Moreover, each of the second equalizers EQ12, EQ22and EQ32receive corresponding comparison signals (i.e., CS1, CS2and CS3), and are also responsive to respective second enable signals EN12, EN22and EN32, which operate to enable/disable the respective equalizer. Furthermore, each of the second equalizers EQ12, EQ22and EQ32generate respective second equalized values (at outputs thereof) by equalizing respective ones of the comparison signals (i.e., CS1, CS2and CS3) and passing these equalized values to the adders552,554and556, which pass these signals to a corresponding second input terminal of the first through third sense amplifiers510,520and530.

The equalization controller650may provide the first enable signals EN11, EN21and EN31to the first equalizers EQ11, EQ21and EQ31, may provide the second enable signals EN12, EN22and EN32to the second equalizers EQ12, EQ22and EQ32, and may provide the first equalizers EQ11, EQ21and EQ31and the second equalizers EQ12, EQ22and EQ32with the control equalization coefficients CWs to control the first equalizers EQ11, EQ21and EQ31and the second equalizers EQ12, EQ22and EQ32. Advantageously, the equalization controller650may adjust the control equalization coefficients CWs until the first through third comparison signals CS1, CS2and CS3match expected values, and may store control equalization coefficients CWs, in the storage670, in case when the first through third comparison signals CS1, CS2and CS3match the expected values. The equalization controller650may store the expected values therein.

As described herein, when M corresponds to four, the multi-level signal MLDAT may have one of the first through fourth voltage levels VL11, VL21, VL31and VL41, the first reference voltage VREF1may be set to have a level between the first voltage level VL11and the second voltage level VL21, the second reference voltage VREF2may be set to have a level between the second voltage level VL21and the third voltage level VL31, and the third reference voltage VREF3may be set to have a level between the third voltage level VL31and the fourth voltage level VL41. Accordingly, the second reference voltage VREF2may have a voltage level greater than a voltage level of the first reference voltage VREF1and the third reference voltage VREF3may have a voltage level greater than the voltage level of the second reference voltage VREF2.

The output decoder550ofFIG.15Amay decode the first comparison signal CS1, the second comparison signal CS2, and the third comparison signal CS3, and may determine data bits corresponding to the multi-level signal MLDAT based on levels of the first comparison signal CS1, the second comparison signal CS2, and the third comparison signal CS3, and may output the target data signal DQ indicating the determined data bits. For example, when the first comparison signal CS1, the second comparison signal CS2and the third comparison signal CS3indicate that a voltage level of the multi-level signal MLDAT is greater than the third reference voltage VREF3, the output decoder550may output the target data signal DQ corresponding ‘11’. Alternatively, when the first comparison signal CS1, the second comparison signal CS2and the third comparison signal CS3indicate that the voltage level of the multi-level signal MLDAT is smaller than the third reference voltage VREF3and greater than the second reference voltage VREF2, the output decoder550may output the target data signal DQ corresponding to ‘10’.

And, when the first comparison signal CS1, the second comparison signal CS2and the third comparison signal CS3indicate that the voltage level of the multi-level signal MLDAT is smaller than the second reference voltage VREF2yet greater than the first reference voltage VREF1, the output decoder550may output the target data signal DQ corresponding to ‘01’. Finally, when the first comparison signal CS1, the second comparison signal CS2and the third comparison signal CS3indicate that the voltage level of the multi-level signal MLDAT is smaller than the first reference voltage VREF1, the output decoder550may output the target data signal DQ corresponding to ‘00’.

FIG.15Bis a block diagram illustrating another example of the data sampler in the multi-level signal receiver ofFIG.14according to example embodiments. InFIG.15B, it is assumed that M is four (4) and N is two (2). Referring toFIG.15B, a data sampler505bmay include first through third sense amplifiers570,573and575, a clock generator540a, a latch circuit577and an output decoder579. The clock generator540amay generate a four-phase clock signal CK_4P and provide the clock signal CK_4P to the first through third sense amplifiers570,573, and575and the latch circuit577.

The first sense amplifier570may include first through fourth sub sense amplifier SSA11˜SSA14, the second sense amplifier573may include first through fourth sub sense amplifier SSA21˜SSA24, and the third sense amplifier575may include first through fourth sub sense amplifier SSA31˜SSA34. The latch circuit577may include latches LAT11˜LAT14corresponding to the first through fourth sub sense amplifiers SSA11˜SSA14, latches LAT21˜LAT24corresponding to the first through fourth sub sense amplifiers SSA21˜SSA24, and latches LAT31˜LAT34corresponding to the first through fourth sub sense amplifiers SSA31˜SSA34.

Each of the first through fourth sub sense amplifiers SSA11˜SSA14may compare the multi-level signal MLDAT with the first reference voltage VREF1at every phase of the four-phase clock signal CK_4P and may provide respective one of the latches LAT11˜LAT14with respective one of first comparison signals CS11˜CS14and respective one of first inverted comparison signals CS11B˜CS14B based on a result of the comparison. Each of the latches LAT11˜LAT14may latch respective one of the first comparison signals CS11˜CS14and respective one of the first inverted comparison signals CS11B˜CS14B to output respective one of latch signals LS11˜LS14. Internal signals of the latches LAT11˜LAT14may correspond to a differential type and may fed-back to the first through fourth sub sense amplifiers SSA11˜SSA14.

Similarly, each of the first through fourth sub sense amplifiers SSA21˜SSA24may compare the multi-level signal MLDAT with the second reference voltage VREF2at every phase of the four-phase clock signal CK_4P and may provide respective one of the latches LAT21˜LAT24with respective one of second comparison signals CS21˜CS24and respective one of second inverted comparison signals CS21B˜CS24B based on a result of the comparison. Each of the latches LAT21˜LAT24may latch respective one of the second comparison signals CS21˜CS24and respective one of the second inverted comparison signals CS21B˜CS24B to output respective one of latch signals LS21˜LS24. Internal signals of the latches LAT21˜LAT24may correspond to a differential type and may fed-back to the first through fourth sub sense amplifiers SSA21˜SSA24.

Next, each of the first through fourth sub sense amplifiers SSA31˜SSA34may compare the multi-level signal MLDAT with the third reference voltage VREF3at every phase of the four-phase clock signal CK_4P and may provide respective one of the latches LAT31˜LAT34with respective one of third comparison signals CS31˜CS34and respective one of third inverted comparison signals CS31B˜CS34B based on a result of the comparison. Each of the latches LAT31˜LAT34may latch respective one of the third comparison signals CS31˜CS34and respective one of the third inverted comparison signals CS31B˜CS34B to output respective one of latch signals LS31˜LS34. Internal signals of the latches LAT31˜LAT34may correspond to a differential type and may fed-back to the first through fourth sub sense amplifiers SSA31˜SSA34. The output decoder595may decode the latch signals LS11˜LS14, the latch signals LS21˜LS24, and the latch signals LS31˜LS34to output the target data signal DQ indicating the determined data bits.

FIG.16is a circuit diagram illustrating one of equalizers inFIG.14(andFIG.15A) according to example embodiments. Referring toFIG.16, an equalizer EQ may be implemented with a decision feedback equalizer (DEF) and the equalizer EQ may include delay elements583a˜583s, multipliers591˜59n, an adder SUM, a subtractor581and a decision logic582. Here, s is an integer greater than two and n is an integer greater than two. The delay elements583a˜583s, the multipliers591˜59n, and the adder SUM may constitute a feedback filter FF.

The delay elements583a˜583smay sequentially delay a decision bit Dk, the multipliers591˜59nmultiply outputs of the delay elements583a˜583sby the control equalization coefficients CW1˜CWs, respectively, the adder SUM adds outputs of the multipliers591˜59nand the subtractor581subtracts an output of the adder SUM from an input bit Xk to provide an output bit Yk. The decision logic582may determines a logic level of the output bit Yk based on the clock signal CLK to provide a decision bit Dk. InFIG.16, the input bit Xk may one of the first through third comparison signals CS1, CS2and CS3, or may be one of the inverted versions of the first through third comparison signals CS1, CS2and CS3, and the decision bit Dk may correspond to one of an output of the first equalizers EQ11, EQ21and EQ31, or an output of the second equalizers EQ12, EQ22and EQ32.

FIG.17is a circuit diagram illustrating an example of the first sense amplifier according to example embodiments. InFIG.17, the first equalizer EQ11and the second equalizer EQ12are illustrated for convenience of explanation. Referring toFIG.17, the first sense amplifier510may include first through third p-channel metal-oxide semiconductor (PMOS) transistors511,512and513, a CMOS transmission gate516and first and second n-channel metal-oxide semiconductor (NMOS) transistors514and515.

As shown, the first PMOS transistor511is connected between the power supply voltage VDDQ and a first node N11and has a gate receiving the clock signal CK. The second default PMOS transistor512is connected between the first node N11and a second node N12and has a gate receiving the multi-level signal MLDAT. The third default PMOS transistor513is connected between the first node N11and a third node N13and has a gate receiving the first reference voltage VREF1.

The CMOS transmission gate516is connected between the second node N12and the third node N13, and has gate terminals connected to the ground voltage VSS and the power supply voltage VDDQ, as shown, to thereby act as a normally-on transmission gate (having a predetermined channel resistance therein). The first default NMOS transistor514is connected between the second node N12and the ground voltage VSS and has a gate receiving the clock signal CK. The second default NMOS transistor515is connected between the third node N13and the ground voltage VDDQ and has a gate receiving the clock signal CK.

When the first PMOS transistor511is turned-on in response to the clock signal CK (i.e., CK=low), the first NMOS transistor514and the second NMOS transistor515are turned-off. Therefore, currents corresponding to voltage difference between the multi-level signal MLDAT and the first reference voltage VREF1are provided to the second node N12and the third node N13, respectively. The transmission gate516is turned-on, the first sense amplifier510may provide the first comparison single CS1based on potential difference between the second node N12and the third node N13. In contrast, when the first NMOS transistor514and the second NMOS transistor515are turned-on in response to the clock signal CK (i.e., CK=high), the second node N12and the third node N13are discharged to the ground voltage VSS. Therefore, the first sense amplifier510may compare the multi-level signal MLDAT and the first reference voltage VREF1, may output the first comparison single CS1at the third node N13and may output a first inverted comparison single CS1B at the second node N12.

The first equalizer EQ11may include PMOS transistor pairs (517a1,517b1)˜(517am,517bm) connected in parallel with the second PMOS transistor512between the first node N11and the second node N12. Each pair of the PMOS transistor pairs (517a1,517b1)˜(517am,517bm) may be connected in series between the first node N11and the second node N12. Each gate of the PMOS transistors517a1˜517amreceives respective one of first enable signals EN11a˜EN11m, and each gate of the PMOS transistors517b1˜517bmreceives inverted version CS1B of the first comparison signal CS1. At least some of the PMOS transistors517a1˜517ammay have different channel width over channel length and at least some of the PMOS transistors517b1˜517bmmay have different channel width over channel length.

Likewise, the second equalizer EQ12may include PMOS transistor pairs (518a1,518b1)˜(518am,518bm) connected in parallel with the third PMOS transistor513between the first node N11and the third node N13. Each pair of the PMOS transistor pairs (518a1,518b1)˜(518am,518bm) may be selectively connected in series between the first node N11and the third node N13. Each gate of the PMOS transistors518a1˜518amreceives a respective one of second enable signals EN12a˜EN12m, and each gate of the PMOS transistors518b1˜518bmreceives the first comparison signal CS1. At least some of the PMOS transistors518a1˜518ammay have different channel width over channel length and at least some of the PMOS transistors518b1˜518bmmay have different channel width over channel length.

FIG.18is a circuit diagram illustrating an example of the third sense amplifier according to example embodiments. Referring toFIG.18, a third sense amplifier530amay include first through third PMOS transistors531,532and534, a “normally-on” CMOS transmission gate539having a predetermined channel resistance (Rchan) and first and second NMOS transistors537and538. The first PMOS transistor531is connected between the power supply voltage VDDQ and a first node N21, and has a gate receiving the clock signal CK. The second PMOS transistor532is connected between the first node N21and a second node N22and has a gate receiving the multi-level signal MLDAT. The third PMOS transistor534is connected between the first node N21and a third node N23and has a gate receiving the third reference voltage VREF3.

The transmission gate539is connected between the second node N22and the third node N23, and is connected to the ground voltage VSS and the power supply voltage VDDQ. The first NMOS transistor537is connected between the second node N22and the ground voltage VSS and has a gate receiving the clock signal CK. The second NMOS transistor538is connected between the third node N23and the ground voltage VDDQ and has a gate receiving the clock signal CK. Therefore, the third sense amplifier530amay compare the multi-level signal MLDAT and the third reference voltage VREF3, may output the third comparison single CS3at the third node N23and may output a third inverted comparison single CS3B at the second node N22.

As described with reference toFIG.17, a first equalizer may be connected between the first node N21and the second node N22and a second equalizer may be connected between the first node N21and the third node N23. In the embodiments, each threshold voltage of the second PMOS transistor532and the third PMOS transistor534is smaller than each threshold voltage of the second PMOS transistor512and the third PMOS transistor513. Therefore, the first sense amplifier510and the third sense amplifier530amay have a first sensing characteristic and the second sensing characteristic with respect to the first reference voltage VREF1and the third reference voltage VREF3, respectively, based on a difference of the threshold voltages.

The third reference voltage VREF3is applied to the gate of the third PMOS transistor534, and the first reference voltage VREF1whose level is smaller than a level of the third reference voltage VREF3is applied to the gate of the third PMOS transistor513. If the threshold voltages of the third PMOS transistor534and the third PMOS transistor513are the same, the second sensing characteristic of the third sense amplifier530amay be worse than the first sensing characteristic of the first sense amplifier510. But, because the threshold voltage of the third PMOS transistor534is smaller than the threshold voltage of the third PMOS transistor513, the third PMOS transistor534is turned-on in response to a voltage level which is greater than a voltage level which turns-on the third PMOS transistor513, so that the second sensing characteristic of the third sense amplifier530amay be enhanced.

FIG.19is a circuit diagram illustrating an example of the third sense amplifier according to example embodiments. Referring toFIG.19, a third sense amplifier530bmay include first through fifth PMOS transistors531,532b,533band534b,535b, a transmission gate539, and first and second NMOS transistors537and538. The first PMOS transistor531is connected between the power supply voltage VDDQ and a first node N21and has a gate receiving the clock signal CK. The second and third PMOS transistors532band533bare connected in parallel between the first node N21and a second node N22and have gates receiving the multi-level signal MLDAT. The fourth and fifths PMOS transistors534band535bare connected in parallel between the first node N21and a third node N23and have gates receiving the third reference voltage VREF3.

The CMOS transmission gate539(having a predetermined channel resistance Rchan) is connected between the second node N22and the third node N23and is connected to the ground voltage VSS and the power supply voltage VDDQ. The first NMOS transistor537is connected between the second node N22and the ground voltage VSS and has a gate receiving the clock signal CK. The second NMOS transistor538is connected between the third node N23and the ground voltage VSS and has a gate receiving the clock signal CK. Therefore, the third sense amplifier530bmay compare the multi-level signal MLDAT and the third reference voltage VREF3, may output the third comparison single CS3at the third node N23, and may output the third inverted comparison single CS3B at the second node N22.

As described with reference toFIG.17, a first equalizer may be connected between the first node N21and the second node N22, and a second equalizer may be connected between the first node N21and the third node N23. In the embodiments, each threshold voltage of the second through fifth PMOS transistors531,532b,533band534b,535bis smaller than each threshold voltage of the second PMOS transistor512and the third default PMOS transistor513. Therefore, the first sense amplifier510and the third sense amplifier530bhave a first sensing characteristic and a second sensing characteristic with respect to the first reference voltage VREF1and the third reference voltage VREF3, respectively, based on the differences of the threshold voltages.

InFIG.19, the second and third PMOS transistors532band533breceiving the multi-level signal MLDAT are disposed in parallel between the first node N21and a second node N22and the fourth and fifths PMOS transistors534band535breceiving the third reference voltage VREF3are disposed in parallel between the first node N21and the third node N23. Therefore, a channel width over a channel length of a PMOS transistor receiving the third reference voltage VREF3is increased.

FIG.20is a block diagram illustrating an example of the reference voltage generator according to example embodiments. Referring toFIG.20, the reference voltage generator600may include a voltage division circuit610and a reference switch circuit620. The voltage division circuit610may include a plurality of resistors R connected in series between the power supply voltage VDDQ and the ground voltage VSS. The reference switch circuit620may switch between the plurality of resistors R in response to the reference switch control signal RCS to output the (M−1) reference voltages VREF1˜VREF (M−1). The reference switch circuit620may include a plurality of switches connected between the plurality of resistors R.

The reference switch control signal RCS may be provided from the equalization controller650inFIG.14. Therefore, the equalization controller650may control the reference voltage generator600such that the levels of the (M−1) reference voltages are adjusted until the (M−1) comparison signals CS1˜CS (M−1) match expected values, and may store control equalization coefficients CWs in the storage670when the (M−1) comparison signals CS1˜CS (M−1) match the expected values. The equalization controller650may store the expected values therein.

FIG.21Aillustrates the multi-level signal and the reference voltages when the multi-level signal is not affected by the channel. Referring toFIG.21A, the multi-level signal MLDAT denoted by PAM-4 may have one of the first through fourth voltage levels VL11, VL21, VL31and VL41, the first reference voltage VREF1may be set to have a level between the first voltage level VL11and the second voltage level VL21, the second reference voltage VREF2may be set to have a level between the second voltage level VL21and the third voltage level VL31, and the third reference voltage VREF3may be set to have a level between the third voltage level VL31and the fourth voltage level VL41.

FIG.21Billustrates the multi-level signal and the reference voltages when the multi-level signal is affected by the channel. Referring toFIG.21B, the multi-level signal MLDAT denoted by PAM-4′ may have one of the first through fourth voltage levels VL11c, VL21c, VL31cand VL41cdifferent from each other, and the first, second and third voltage intervals VOH11c, VOH21cand VOH31cmay be varied. By advantageously performing training according to example embodiments, the first through third reference voltages VREF1, VREF2and VREF3may be adjusted to first through third reference voltages VREF1c, VREF2cand VREF3c, and the first through third sense amplifiers510,520and530may perform normal comparison operations responsive to the training.

FIG.22is a block diagram illustrating an example of a memory system ofFIG.1according to example embodiments. The overlapping descriptions associated withFIGS.2and3will be omitted. Referring toFIG.22, a memory system11includes a memory controller101, a memory device201and a plurality of channels31a,31band31c. The memory system11may be substantially the same as the memory system11ofFIG.2, except that the memory device201further includes an eye monitor circuit51a. The eye monitor circuit51amay be coupled to the plurality of channels31a,31band31c, and may generate characteristic data CDAT1that represents characteristics of the channels31a,31band31cbased on the received output data signals DS11, DS21and DS31. The control code set CDST stored in the storage690through the training may be provided to the equalizers in the receivers47a,47band47cas control codes CCDa, CCDb, . . . , CCDc.

A voltage setting circuit (e.g., the voltage setting circuit430inFIG.8) is included in each of the transmitters25a,25band25cmay generate voltage setting control signals based on the characteristic data CDAT1. Training including the voltage setting operation to adjust at least one of the voltage intervals based on the characteristics of the channels31a,31band31c. The eye monitor circuit51amay be included with respect to each of the channels31a,31band31cor may be disposed at outside of the memory controller101and the memory device201.

The training operation associated withFIGS.21A-21Bwill be described in detail as follows. Before the training operation, all transmitters connected to each data I/O pad (or pin) may receive the same code for generating output signals to have the same voltage interval. After that, a command for starting the training operation may be received, and different random patterns may be output for each pin based on the “training” command. After that, “eyes” may be checked for each pin, and different codes may be provided for each pin and each voltage level. As the training operation is performed, output signals may be generated to have different voltage intervals for each pin. For example, a ZQ code may be changed in a case of on-resistance (or on-die) training, or an additional change circuit may be used to change the codes or voltage intervals. When the training operation is completed for each pin and for each level, signals received by the receivers may have optimal voltage intervals for each pin and for each level. In some example embodiments, the above-described training operation may be sequentially performed for each pin, or may be simultaneously (e.g., globally) performed for all pins.

FIG.23is a flow chart illustrating a method of receiving a multi-level signal in the semiconductor memory device according to example embodiments. Referring toFIGS.1through23, in a method of receiving a multi-level signal in the semiconductor memory device, the multi-level signal receiver500in the semiconductor memory device200receives the multi-level signal MLDAT having one of M different voltage levels through a channel (operation S100). Here, M is an integer greater than two. Each of the (M−1) sense amplifiers in the multi-level signal receiver500compares a multi-level signal MLDAT with one of the (M−1) reference voltages to generate respective one of (M−1) comparison signals (operation S200). The equalization controller650in the receiver500determines whether a training mode corresponds to either a first training mode or a second training mode (operation S300).

When the training mode corresponds to the first training mode (TRM1in S300), the equalization controller650may adjust at least one of (M−1) voltage intervals representing a difference between two adjacent voltage levels from among the M voltage levels based on equalized values of the (M−1) comparison signals CS1˜CS (M−1) (operation S400). However, when the training mode corresponds to the second training mode (TRM2in S300), the equalization controller650may adjust levels of the (M−1) reference voltages VREF1˜VREF (M−1) based on the equalized values of the (M−1) comparison signals CS1˜CS (M−1) (operation S500)

FIG.24is a block diagram illustrating a communication system according to example embodiments. Referring toFIG.24, a communication system800includes a first communication device810, a second communication device830and a channel850therebetween. The first communication device810includes a first transmitter811and a first receiver812. The second communication device830includes a second transmitter831and a second receiver832. The first transmitter811and the first receiver812are connected to the second transmitter831and the second receiver832through the channel850. In some example embodiments, each of the first and second communication devices810and830may include a plurality of transmitters and a plurality of receivers, and the communication system800may include a plurality of channels for connecting the plurality of transmitters and a plurality of receivers.

In addition, the receivers812and832may be the multi-level signal receivers described herein with respect to example embodiments, may receive a multi-level signal having one of M voltage levels different from each other, may determine a voltage level of the multi-level signal by using M−1 sense amplifiers, and may perform training on the M−1 sense amplifiers per data I/O pad, as described hereinabove.

The inventive concept may be applied to various devices and systems that include the memory devices and the memory systems. For example, the inventive concept may be applied to systems such as a personal computer (PC), a server computer, a data center, a workstation, a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camcorder, a video player, a navigation device, a wearable device, an internet of things (IoT) device, an internet of everything (IoE) device, an e-book reader, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, a drone, etc.