NAND flash memory with reduced planar size

A NAND flash memory capable of reducing the planar size of a memory cell is provided. The three-dimensional NAND flash memory includes a substrate, an insulating layer, a lower conductive layer (a source), a three-dimensional memory cell structure, and a bit line. The memory cell structure includes a plurality of strip-shaped gate stacks including stacks of insulators and conductors stacked along a vertical direction from the substrate; and a plurality of channel stacks separately arranged along one side of the gate stack. An upper end of the channel stack is electrically connected to the orthogonal bit line, and a lower end of the channel stack is electrically connected to the lower conductive layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a NAND flash memory, and in particular, to a three-dimensional NAND flash memory and a manufacturing method thereof.

2. Description of Related Art

In recent years, in order to improve the integration of a memory cell, a three-dimensional NAND flash memory of the memory cell that is stacked in a vertical direction is put into practical use. For example, the memory cell is formed by using semiconductor pillars extending in the vertical direction from a substrate (Patent Document 1).

In addition, in Non-Patent Document 1, as shown inFIG.1, a plurality of rectangular gates are stacked on the substrate, and an insulator including a charge storage layer (for example, a nitride silicon layer) and a channel film are formed in the vertical direction along an end of the gate. The channel film includes polysilicon and is U-shaped. A NAND string includes a U-shaped channel film, an insulator including a charge storage layer, and a gate. One upper end of the channel film is connected to a local source line via a plug, and the other upper end is connected to a bit line via a plug.FIG.2Ais a cross-sectional view when a channel film of a flash memory ofFIG.1is cut off in a horizontal direction, andFIG.2Bis a cross-sectional view when a channel film is cut off in a vertical direction. A black elliptical part shown inFIG.2Ais a hole formed through etching, and the hole is an insulating region that insulates the channel film formed along a multi-gate. An interval is 100 nm. In addition, an interval between adjacent multi-gates is 220 nm.

RELATED ART

Patent Document

[Patent Document 1] Japanese Patent Application Laid-Open No. 2015-176870[Non-Patent Document 1] A Novel Double-density, Single-Gate Vertical Channel (SGVC) 3D NAND Flash That Is Tolerant to Deep Vertical Etching CD Variation and Process Robust Read-disturb Immunity, Hang-Ting Lue et al, IEEE International Electron Devices Meeting (IEDM) 15-44, P321-324.

SUMMARY OF THE INVENTION

An objective of the invention is to provide a NAND flash memory capable of reducing the planar size of a memory cell and a manufacturing method thereof compared to the prior art.

The three-dimensional NAND flash memory of the invention includes: a substrate; a lower conductive layer formed in or on the substrate; a plurality of stacks extending in a first direction on the lower conductive layer, and each including stacks of insulators and conductors stacked in a vertical direction from the substrate; a plurality of channel stacks separately arranged along one side of the plurality of stacks and each including an insulating layer including a charge storage layer and a channel film, the insulating layer and the channel film extending in a vertical direction from the substrate, and a lower end of the channel film being electrically connected to the lower conductive layer; and a plurality of strip-shaped upper conductive layers extending in a second direction orthogonal to the first direction, respectively arranged on the plurality of channel stacks, and electrically connected to an upper end of the crossed channel film.

A manufacturing method of a three-dimensional NAND flash memory of the invention includes the following steps. A step of forming a lower conductive layer in or on a substrate. A step of forming a stack by alternately stacking insulators and conductors on the lower conductive layer. A step of etching the stack at a depth reaching the lower conductive layer to form a plurality of stacks extending in a first direction; a step of forming channel stacks on an entire surface of the substrate including the plurality of stacks. A step of etching the channel stacks to separately arrange the channel stacks along one side of each of the plurality of stacks. A step of forming a plurality of strip-shaped upper conductive layers extending in a second direction orthogonal to the first direction on the channel stacks. A step of electrically connecting the plurality of upper conductive layers to an upper end of the crossed channel stack, respectively.

According to the invention, in comparison to the prior art, channel stacks are separately arranged along one side of a stack, and the upper conductive layer is electrically connected to the crossed channel stacks, so that the planar size of a memory cell may be reduced. Therefore, a NAND flash memory with high integration may be obtained.

DESCRIPTION OF THE EMBODIMENTS

A three-dimensional NAND flash memory of the invention is used as a memory medium for various semiconductor devices (for example, a microcontroller, a microprocessor, and a logic processor embedded in such a flash memory).

Embodiment

Then, the following describes the embodiments of the invention with reference to the accompanying drawings. It should be noted that the proportions in the drawings are exaggerated for ease of understanding and do not necessarily represent actual product proportions.

A NAND flash memory100of the present embodiment includes: a substrate1, an insulating layer2formed on the substrate1, a lower conductive layer3formed on the insulating layer2, a memory cell structure MC stacked on the lower conductive layer3in a vertical direction, and a bit line8formed on the memory cell structure MC.

The substrate1is not particularly limited, and includes, for example, a silicon substrate. The silicon substrate may include any of intrinsic type, n-type, and p-type. In addition, when a peripheral circuit (for example, a column selection drive circuit or an integrated circuit such as a page buffer/readout circuit) is formed on a surface of the silicon substrate, the silicon substrate may include n-type or p-type. In the following description, a case that a silicon substrate is used as a substrate1is exemplified.

The insulating layer2formed on the silicon substrate1includes, for example, a silicon oxide film, a silicon nitride film, or the like. The lower conductive layer3includes, for example, n-type polysilicon, or a stack of a metal material and n-type polysilicon. The lower conductive layer3functions as a common source SL of a NAND string.

The memory cell structure MC includes a plurality of NAND strings formed on the lower conductive layer3in the vertical direction or the longitudinal direction. As is well known, a NAND string includes a plurality of memory cells connected in series, a selection transistor on the bit line side connected to one end of the plurality of memory cells, and a selection transistor on the source line side connected to the other end. Furthermore, the NAND string may also include a virtual memory cell between the selection transistor on the bit line side and the memory cell or between the selection transistor on the source line side and the memory cell.

Gate stacks110are formed by alternately stacking insulators4and conductors5on the lower conductive layer3. As shown inFIG.3AandFIG.3B, the gate stacks110are processed to be strip-shaped (rectangular in shape) when viewed from a plane, and extend in a stripe shape in a row direction. An uppermost layer of the gate stacks110is an insulator6connected to a bit line8via an insulator7, and a lowermost layer is an insulator4connected to the lower conductive layer3. The insulator4and the insulator6include, for example, a silicon oxide film, a silicon nitride film, or the like. A conductor5A directly below the insulator6constitutes a gate of the selection transistor on the bit line side, and a conductor5B directly above the insulator4at the lowermost layer constitutes a gate of the selection transistor on the source line side. A plurality of conductors5between the conductor5A and the conductor5B respectively constitute gates of the memory cell. The conductor5, the conductor5A, and the conductor5B include, for example, n-type polycrystalline silicon. The conductor5A that constitutes the gate of the selection transistor on the bit line side is connected to one or more selection gate lines SGD generated by a column selection drive circuit or the like not shown. The conductor5B constituting the gate of the selection transistor on the source line side is connected to one or more selection gate lines SGS generated by the same column selection drive circuit or the like, and the plurality of conductors5are connected to corresponding word lines WL.

The memory cell structure MC further includes channel stacks9. As shown inFIG.3B,FIG.4, andFIG.6, the channel stacks9are formed separately in the row direction in such a manner as to follow one side of the gate stacks110. A channel stack9extends from the lower conductive layer3to the bit line8in the vertical direction. An upper end9A of the channel stack9is connected to crossed bit lines8, and a lower end9B is connected to the lower conductive layer3. In this example, the upper end9A of the channel stack9is formed to cover a part of the insulator6of the gate stacks110. In this way, a contact area between the channel stack9and the bit line8may be increased. However, such composition is an example and is not limited thereto.

One NAND string includes one channel stack9extending in the vertical direction. The channel stack9includes a channel film constituting a channel and a gate insulator formed between the channel film and the gate5. The channel film includes polysilicon, for example. The gate insulator includes a charge storage layer that stores charges and a plurality of insulating layers sandwiching the charge storage layer. The gate insulator may be, for example, an ONO structure of silicon oxide film (O)/silicon nitride film (N)/silicon oxide film (O). Other semiconductor materials with a high dielectric constant may be used instead of the silicon oxide film. In addition, details of the channel stack9are to be described later.

As described above, on one side of the gate stacks110, the plurality of channel stacks9are formed separately, and the insulator7is formed between the channel stacks9. Furthermore, an insulator7is also formed on the other side of the gate stacks110. In other words, space between two adjacent gate stacks is filled with the insulator7.

As shown inFIG.3A, on the top of the memory cell structure MC, a plurality of bit lines8processed to be strip-shaped (rectangular in shape) when viewed from a plane extend in a stripe shape in the column direction. The plurality of bit lines8are respectively electrically connected to the upper end9A of the channel stack9corresponding to a position crossing the gate stack110. The bit line8includes, for example, a metal material such as polysilicon, aluminium (Al), or the like.

Next, the manufacturing method of the NAND flash memory of the present embodiment is described with reference toFIG.7toFIG.18. First, as shown inFIG.7, an insulating layer2is formed on a substrate1, and a lower conductive layer3is formed on the insulating layer2. Next, a stack110A including a stack of an insulator4, an insulator6, and a conductor5is formed on the lower conductive layer3. The stack110A is a precursor of the gate stack110. A number of conductors5stacked by the stack110A is determined according to a number (for example, 32 or 64) of memory cells of a NAND string.

Next, a patterned etching mask (not shown) is formed on the insulator6through photolithography, and the insulator4, the insulator6, and the conductor5of the stack110A are simultaneously anisotropically etched by using the etching mask. The etching is performed until reaching the lower conductive layer3. The etching is performed by, for example, anisotropic etching or a combination of anisotropic etching and isotropic etching. On the surface of the lower conductive layer3, micro steps or recesses removed by etching may be formed. It is desirable that the lower conductive layer3has a sufficiently large film thickness for such steps or recesses. In this way, as shown inFIG.8, a strip-shaped gate stack110extending in the row direction is formed on the lower conductive layer3. An interval between the gate stacks110is, for example, 180 nm.FIG.9is a cross-sectional view taken along line A-A (line A-A is the same position as line A-A inFIG.3A).

Next, as shown inFIG.10, the channel stack9is formed on an entire surface of the substrate to cover the gate stack110. The structure of the channel stack9is described with reference toFIG.10AtoFIG.10D. The enlarged cross-sectional views ofFIG.10BtoFIG.10Dcorrespond to the regions Q1and Q2shown inFIG.10A, respectively.

As shown inFIG.10B, an insulating layer10, a charge storage layer11, an insulating layer12, and a polysilicon layer13are sequentially stacked on the entire surface of the substrate to cover the gate stack110. The method for forming these films is not particularly limited, and for example, chemical vapor deposition (CVD) or sputtering may be used. The insulating layer12includes silicon dioxide (SiO2), or a stack of silicon dioxide (SiO2) and silicon nitride (SiN). The charge storage layer11includes several insulators, for example, a stack including silicon nitride (SiN) or silicon dioxide (SiO2) capable of storing charges. The insulating layer10includes several insulators such as a high dielectric constant (High K, Hi K) material with a high dielectric constant. The polysilicon layer13is not doped, and therefore includes intrinsic silicon.

Next, as shown inFIG.10C, bottoms of the insulating layer10, the charge storage layer11, the insulating layer12, and the polysilicon layer13are etched by using an etching mask not shown herein. The etching is performed by, for example, anisotropic etching or a combination of anisotropic etching and isotropic etching until the surface of the lower conductive layer3is exposed. On the surface of the lower conductive layer3, micro steps or recesses removed by etching may be formed. It is desirable that the lower conductive layer3has a sufficiently large film thickness for such steps or recesses. Next, as shown inFIG.10D, a polysilicon layer14is stored on the entire surface of the substrate. The polysilicon layer14is not doped either and therefore is intrinsic silicon. The two polysilicon layers13and14are electrically connected to each other, and the lower end of the polysilicon layer14is electrically connected to the lower conductive layer3. In this way, channel stacks9are formed to cover two sides of the gate stacks110.FIG.11is a cross-sectional view taken along line C-C the same position as line C-C inFIG.3A.

Next, as shown inFIG.12, the channel stacks9are processed into a plurality of stripes by etching to form a plurality of channel stacks9insulated from each other. As shown inFIG.13, one channel stack9extends in a direction orthogonal to a direction in which a gate insulator110extends, and the plurality of channel stacks9are separately arranged at a certain interval in the direction in which the gate insulator110extends.

Next, the channel stack9is further processed along one side of the gate insulator110. The processing flow is shown inFIG.14toFIG.16. Moreover,FIG.14toFIG.16are each a schematic cross-sectional view along a line A-A ofFIG.13. As shown inFIG.14, a patterned etching mask15is formed through photolithography to cover a part of side and upper surfaces of the channel stack9.

Next, as shown inFIG.15, the channel stack9is partially removed for etching via the etching mask15. The etching is performed by, for example, anisotropic etching or a combination of anisotropic etching and isotropic etching until the surface of the lower conductive layer3is exposed. On the surface of the lower conductive layer3, micro steps or recesses removed by etching may be formed. It is desirable that the lower conductive layer3has a sufficiently large film thickness for such steps or recesses. Through the etching, the channel stack9remains on one side of the gate insulator110and covers a part of the insulator6of the gate stack110. In order to increase the contact area between the channel stack with the bit line8or the area for forming a contact hole connected to the bit line, the channel stack9is formed to cover the insulator6. In addition, the bottom of the channel stack9is separated from the bottom of the channel stack9of the adjacent gate stacks110, so that the lower conductive layer3is exposed.

Next, as shown inFIG.16, the etching mask15is removed. After the etching mask15is removed, an intermediate insulator7is stored on an entire surface of the substrate to cover the channel stack9and the gate stack110. Accordingly, space between adjacent gate stacks110is filled with the intermediate insulator7.

Next, as shown inFIG.17, chemical mechanical planarization (CMP) or the like is performed on the intermediate insulator7. Through the planarization process, the top of the channel stack9is exposed.

Next, as shown inFIG.18, materials of bit lines are stored on the entire surface of the substrate, and then the bit line8is patterned into a strip shape. The bit line8is electrically connected to a polysilicon layer13and a polysilicon layer14of the channel stack9that are crossed directly below the bit line. For example herein, the bit line8is in direct contact with the upper end9A of the channel stack9, but an interlayer insulating film may be formed after planarization processing, and a contact hole may be formed in the interlayer insulating film to expose the upper end9A of the channel stack9, so that the bit line8is electrically connected to the channel stack9via the contact hole.

In this way, a NAND string connected between the bit line8and the lower conductive layer (source)3is formed to obtain a three-dimensional memory cell array.

Next, the cell size of the three-dimensional NAND flash memory of the present embodiment is compared with the cell size of existing products.FIG.19Bis a schematic top view of a flash memory of the present embodiment, andFIG.19Ais a schematic top view showing no bit line8and bit line (BL) contact16between the bit line8and a channel film19. In these figures,18represents a gate insulating film (an insulator10, an insulator11, and an insulator12shown inFIG.10B), and19represents a channel film (polysilicon13and polysilicon14shown inFIG.10D). In addition, a rectangular region R shown by the dashed lines represents the planar size of one memory cell. When an interval of the gate electrode5is 180 nm and an interval of the channel film19is 50 nm, the planar size R is 50×180 nm2.

In addition,FIG.20Bis a schematic top view of an existing memory cell of the non-patent document 1, andFIG.20Ais a schematic top view showing no bit line8and plug17for contact between the bit line8and a channel film19. The rectangular region R1represents the planar size of one memory cell, which is represented by the same scale as that inFIG.20A.

In the existing memory cell structure, two memory cells are formed on both sides of the gate5, and the bit lines8is connected to the two memory cells facing each other in a shared manner. For example, the two memory cells MC1and MC2are connected to the bit lines8via the plug17. In order to cause the two memory cells to operate individually, the bit lines8connected to the two memory cells are required to be separated from each other. On the contrary, in the memory cell structure of the present embodiment, the memory cell is only arranged on one side of the gate5. Therefore, the bit lines8connected to the two memory cells may be shared. According to such differences, the interval between the bit lines8in the present embodiment is about half of the interval between the existing bit lines8, so that the planar size R of the memory cell in the present embodiment is less than the planar size R1of the existing memory cell. Specifically, it may be learned that the planar size R1of the existing memory cell is about 160×100 nm2, and the planar size R of the memory cell of the present embodiment is less than that of the existing memory cell.

In the embodiment, for example, the lower conductive layer (source)3including n-type polysilicon is formed on the substrate1via the insulating layer2, which is not limited thereto. The lower conductive layer (source) may also be a highly doped n-type well region formed in a P-type silicon substrate, for example.

The NAND flash memory includes a plurality of blocks, each of the blocks including a three-dimensional NAND string as described above. The memory cell may be a single level cell (SLC) type with a one-bit (binary data) memory or with a multi-bit memory. In the NAND flash memory, readout or programming is performed in units of pages, and erased in units of blocks. Since these operations are well known, the descriptions thereof are omitted herein.

The preferred embodiments of the invention are described in detail, but the invention is not limited to the specific embodiments. Various modifications and variations can be made within the scope of the spirit of the invention in the claims.