Transistor device with improved source/drain junction architecture and methods of making such a device

One illustrative device disclosed herein includes a plurality of source/drain regions positioned in an active region on opposite sides of a gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor and a plurality of halo regions, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions. A method disclosed herein includes forming a plurality of halo implant regions in an active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of an isolation region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the present disclosure relates to the manufacture of semiconductor devices, and, more specifically, to a transistor device with improved source/drain junction architecture and various methods of making such a device.

2. Description of the Related Art

The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit element that substantially determines performance of the integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NMOS transistors and/or PMOS transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped channel region disposed between the highly doped source/drain regions. Device designers are under constant pressure to improve the electrical performance characteristics of semiconductor devices, such as transistors, and the overall performance capabilities of integrated circuit devices that incorporate such devices.

Ion implantation is a technique that is employed in many technical fields to implant dopant ions into a substrate so as to alter the characteristics of the substrate or of a specified portion thereof. For example, the rapid development of advanced devices in the semiconductor industry is based on, among other things, the ability to generate highly complex dopant profiles within tiny regions of a semiconducting substrate by performing advanced implantation techniques through a masking. In implanting specified ions into a substrate, the desired lateral implant profile may be readily obtained by providing correspondingly adapted implantation masks. A desired vertical implant profile may be achieved by, among other things, controlling the acceleration energy of the ions during the implantation process such that the majority of the ions are positioned at a desired depth in the substrate. Moreover, by appropriately selecting the dopant dose, i.e., the number of ions per unit area of the ion beam impinging on a substrate, comparably high concentrations of atoms may be incorporated into a substrate as compared to other doping techniques, such as diffusion. In the case of an illustrative transistor, ion implantation may be used to form various doped regions, such as halo implant regions, extension implant regions and deep source/drain implant regions, etc.

An illustrative ion implantation sequence employed in forming an illustrative transistor30will now be discussed with reference toFIGS. 1A-1D.FIG. 1Adepicts the transistor30at an early stage of fabrication, wherein a gate structure14has been formed above a semiconductor substrate10in an active region that is defined by a shallow trench isolation structure12. The gate structure14typically includes a gate insulation layer14A and a conductive gate electrode14B. As shown inFIG. 1A, an implantation mask17is formed above the substrate so as to expose the transistor. The ion implantation mask17is typically a patterned layer of photoresist material and it may be formed using traditional photolithography tools and techniques. In one illustrative embodiment, a plurality of angled ion implantation processes are performed to form the schematically depicted so-called halo implant regions15in the substrate10. The halo implant regions15are typically formed by performing a series of two or four angled implant processes, during which the substrate10is rotated 180° or 90° after each of the angled implantation processes is performed. The halo implant regions15are doped with the same type of dopant material as is the active region of the substrate10. For example, for an NMOS device, the halo implant regions15may be P-doped regions so as to reinforce the dopants in the P-doped active region. In the case of a PMOS device, the halo implant regions15would be N-doped regions. The dopant concentration of the halo implant regions15may vary depending upon the particular application. The implant angle used in forming the halo implant regions15may also vary depending upon the particular application. Among other things, the purpose of the halo implant regions15is to reduce so-called short channel effects on minimum channel length devices, i.e., the proximity from the left and the right halo implant regions will help to avoid premature punch-through and keep the threshold voltage of the transistor device high enough for proper functionality.

As indicated inFIG. 1B, after the halo implant regions15are formed, a so-called extension ion implantation process is typically performed to form so-called extension implant regions16in the substrate10. The extension implant process is typically performed through the same masking layer17that was used when forming the halo implant regions15. In the case of an NMOS device, the extension implant regions will be N-doped regions. The concentration of dopant materials in the extension implant regions16may vary depending upon the particular application. In some embodiments, the extension implant regions16may be self-aligned relative to the sidewalls of the gate structure14. In other applications, a small sidewall spacer (not shown) may be formed adjacent to the gate structure14prior to forming the extension implant regions16. The extension implant regions16typically have a lower dopant concentration and a shallower depth than that of so-called deep source/drain implant regions that, as discussed more fully below, will be formed in the substrate10.

FIG. 1Cdepicts the device30after several process operations have been performed. First, the patterned implant mask17used when performing the process operations described above in connection withFIGS. 1A-1Bis removed. Then, one or more sidewall spacers18are formed proximate the gate structure14. The spacers18may be formed by depositing a layer of spacer material and thereafter performing an anisotropic etching process. Next, a so-called source/drain doping process is performed on the transistor30by means of an epitaxy and/or ion implantation process to form so-called deep source/drain implant regions20in the substrate10. As noted above, the source/drain ion implantation process is typically performed using a higher dopant dose and at a higher implant energy than the ion implantation process that was performed to form the extension implant regions16. The halo implant regions15have a sufficient concentration of counter-dopant materials so as to effectively overwhelm the dopants implanted during the source/drain implantation process. As a result, the source/drain implant regions20effectively stop on the halo implant regions15.

Thereafter, as shown inFIG. 1D, a heating or anneal process is performed to form the final source/drain regions22for the transistor30. This heating process repairs the damage to the lattice structure of the substrate material as a result of the implantation processes and it activates the implanted dopant materials, i.e., the implanted dopant materials are incorporated into the silicon lattice. As depicted, the halo regions15limit the depth of the final source/drain regions22. As device dimensions are continually being reduced, it is very important that the depth of the source/drain regions22for a transistor be very shallow, e.g., approximately 15 nm or less in current-day technologies, and that the implanted dopants are, to the extent possible, fully activated. Thus, heating processes such as a flash anneal or a laser anneal are performed for a very short duration, e.g., 1250° C. for a duration of 2-10 milliseconds, and are performed to limit the diffusion of the implanted ions, so as to maintain the desired shallow dopant profile, while at the same time trying to maximize dopant activation. In general, the higher the annealing temperature, the greater the extent of dopant activation. For previous device generations, a typical anneal process might be a rapid thermal anneal process performed at a temperature of about 1080° C. for a much longer duration of about 1-2 seconds. However, the very short millisecond anneal times performed to activate very shallow source/drain regions are insufficient to cure all of the damages to the substrate resulting from the ion implantation processes. After a flash or laser anneal process is performed, the source/drain regions22of the transistor30will have an amorphous region (where there is a sufficient concentration of ions to enable the region to conduct current) and a semi-amorphous region (where implanted ions are not of sufficient concentration or not activated). The depth of the amorphous regions may be approximately 3-7 nm and 40-50 nm, for the extension implant regions16and the deep source/drain implant regions20, respectively, of the source/drain region22of the transistor30. As a result, the depth of the semi-amorphous region would tend to overlap with the PN junction in the source/drain region of the device, which may result in higher leakage currents, which tend to reduce the electrical performance of the resulting device and an integrated circuit device incorporating such transistors.

The present disclosure is directed to a transistor device with improved source/drain architecture and various methods of making such a device that may solve or reduce one or more of the problems identified above.

SUMMARY OF THE INVENTION

Generally, the present disclosure is directed to a transistor device with improved source/drain junction architecture and various methods of making such a device. In one example, a method disclosed herein includes forming an isolation region in the substrate so as to define an active region in the substrate, forming a gate structure above the active region and, after forming the gate structure, forming a plurality of halo implant regions in the active region, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of the isolation region.

Another illustrative method involves forming the isolation region in a substrate so as to define an active region in the substrate, forming a gate structure above the active region, after forming the gate structure, forming a patterned halo implantation mask that has an opening that exposes the gate structure and a portion, but not all, of the active region positioned between the gate structure and the isolation region, and performing a plurality of angled ion implantation processes through the patterned halo implantation mask to form a plurality of halo implant regions in the substrate.

Yet another illustrative method disclosed herein includes the steps of forming the isolation region in a substrate so as to define an active region in the substrate, forming the gate structure above the active region, after forming the gate structure, forming a patterned halo implantation mask that has an opening that exposes the gate structure and a portion, but not all, of the active region positioned between the gate structure and the isolation region, and performing a plurality of angled ion implantation processes through the patterned halo implantation mask to form a plurality of halo implant regions in the substrate, wherein an outer edge of each of the halo implant regions is laterally spaced apart from an adjacent inner edge of the isolation region. In this example, the method further includes performing an extension ion implantation process through the patterned halo implantation mask so as to form a plurality of extension implant regions in the substrate, wherein an outer edge of each of the extension implant regions is laterally spaced apart from an adjacent inner edge of the isolation region.

One illustrative device disclosed herein includes an isolation region positioned in the substrate so as to define an active region in the substrate, a gate structure positioned above the substrate, a plurality of source/drain regions positioned in the active region on opposite sides of the gate structure, each of the source/drain regions having a lateral width in a gate length direction of the transistor, and a plurality of halo regions positioned in the active region, wherein each of the halo regions is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions.

Another illustrative device disclosed herein includes an isolation region positioned in the substrate that defines an active region in the substrate, a gate structure positioned above the substrate, a plurality of source/drain regions positioned in the active region on opposite sides of the gate structure, wherein each of the source/drain regions extends to and contacts the isolation region, and a plurality of halo regions positioned in the active region, wherein each of the halo regions has an outer edge that does not extend to and contact the isolation region.

DETAILED DESCRIPTION

The present disclosure is directed to a transistor device with improved source/drain junction architecture and various methods of making such a device. As will be readily apparent to those skilled in the art upon a complete reading of the present application, the present methods and systems are applicable to a variety of technologies, e.g., NMOS, PMOS, CMOS, etc., and they are readily applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc. With reference to the attached drawings, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.

FIG. 2Adepicts an illustrative transistor device100disclosed herein at an early stage of fabrication, wherein a gate structure106has been formed above a semiconductor substrate102in an active region that is defined by a shallow trench isolation structure104. The gate structure106typically includes a gate insulation layer106A and a conductive gate electrode106B. The substrate102may have a variety of configurations, such as the depicted bulk silicon configuration. The substrate102may also have a silicon-on-insulator (SOI) configuration that includes a bulk silicon layer, a buried insulation layer and an active layer, wherein semiconductor devices are formed in and above the active layer. Thus, the terms substrate or semiconductor substrate should be understood to cover all forms of semiconductor structures. The substrate102may also be made of materials other than silicon. As will be recognized by those skilled in the art after a complete reading of the present application, the gate structure106may be of any desired construction and comprised of any of a variety of different materials, such as one or more conductive layers made of polysilicon or a metal, etc., and one or more layers of insulating material, such as silicon dioxide, a high-k material, etc. Additionally, the gate structure106for an NMOS transistor may have different material combinations as compared to a gate structure106for a PMOS transistor. Thus, the particular details of construction of gate structure106, and the manner in which the gate structure106is formed, should not be considered a limitation of the present invention. For example, the gate structure106may be made using so-called “gate-first” or “gate-last” techniques.

The drawings below depict one illustrative process flow sequence in which halo implant regions, extension implant regions and deep source/drain regions are formed in that order using the novel methods disclosed herein. However, as will be appreciated by those skilled in the art after a complete reading of the present application, the halo and extension implantation processes may be performed in any desired order. Thus, the inventions disclosed herein should not be considered to be limited to any particular sequence of process operations unless such a sequence is expressly recited in the attached claims.

Next, as shown inFIG. 2B, a patterned halo ion implantation mask108is formed above the substrate102. The halo ion implantation mask108is typically a patterned layer of photoresist material and it may be formed using traditional photolithography tools and techniques. Using the methods disclosed herein, the halo ion implantation mask108is formed such that it has an opening108A that exposes a portion, but not all, of the active region between the gate structure106and the inner edges104E of the isolation region104. The height or thickness108H of the halo ion implantation mask108may vary depending upon the particular application and the desired final width of the halo regions to be formed in the substrate102, as discussed more fully below. In general, all other things being equal, as the height of the halo ion implantation mask108is increased, the width of the halo implant regions may be reduced. In one illustrative embodiment, the halo ion implantation mask108may have an overall height108H that falls within the range of about 100-200 nm. Stated another way, the overall height of the halo ion implantation mask108may be about 80-180 nm taller than the height of the gate structure106. The size of the space108W between the inside edge108E of the opening108A in the halo ion implantation mask108and the corresponding edge106E of the gate structure106may vary depending upon the particular application. In one illustrative embodiment, the size of the space108W may be about 2-3 times the height of the gate structure106. In absolute terms, the size of the space108W may fall within the range of about 50-150 nm, depending upon the overall lateral width of the source/drain regions. Stated another way, the inner edge108E of the opening108A may be positioned inward of the inner edge104E of the isolation region104by a distance108R that falls within the range of about 20-4000 nm.

FIG. 2Cdepicts the device100after a plurality of angled halo ion implantation processes110are performed through the halo ion implantation mask108to form the schematically depicted halo implant regions110A in the substrate102. The halo implant regions110A are typically formed by performing a series of two or four angled implant processes during which the substrate102is rotated 180° or 90°, respectively, after each of the angled implantation processes is performed. The halo implant regions110A are doped with the same type of dopant material as is the active region of the substrate102. For example, for an NMOS device, the halo implant regions110A may be P-doped regions so as to reinforce the dopants in the P-doped active region. In the case of a PMOS device, the halo implant regions110A would be N-doped regions. Stated another way, the halo implant regions110A are doped with a dopant material that is opposite to the type of dopant material that is used to form the doped source/drain regions. The dopant dose used during the angled halo ion implantation processes110may vary depending upon the particular application, e.g., the dopant dose may fall within the range of about 5e12-5e14atoms/cm2. The implant angle110B used during the angled halo ion implantation processes110may also vary depending upon the particular application, i.e., the angle110B may fall within the range of about 10-30 degrees. In one particular embodiment, the halo implant regions110A may be formed by performing the angled halo ion implant processes110using a dopant dose of 5e12-5e14atoms/cm2and at an energy level of about 10-30 keV. In this illustrative example, the halo implant regions110A may have at peak-concentration a target depth of about 7-30 nm.

FIG. 2Ddepicts the device100after, in the illustrative processing sequence depicted herein, a substantially vertical, extension ion implantation process114is performed through the same halo implant mask108to form reduced-width extension implant regions114A in the substrate102. The extension implant regions114A have a reduced width in the sense that the outer edge114E of the extension implant regions114A do not extend all of the way to the isolation region104as is common when performing extension implantation processes using prior art techniques. The reduced-width extension implant regions114A are formed with a type of dopant that is opposite to the type of dopant used to form the halo implant regions110A. For example, for an NMOS device, the extension implant regions114A are N-doped regions. Conversely, for a PMOS device, the extension implant regions114A would be P-doped regions. In this illustrative example, the extension ion implantation process114was performed using a dopant dose of 1-2e15ions/cm2and at an energy level of about 2-5 keV. In this illustrative example, the extension implant regions114may have at peak-concentration a target depth of about 4-20 nm.

FIG. 2Edepicts the device100after several process operations were performed. First, the halo ion implantation mask108was removed by performing, for example, an ashing process. Then, one or more sidewall spacers116were formed proximate the gate structure106. The spacers116may be formed by depositing a layer(s) of spacer material and thereafter performing an anisotropic etching process. Thereafter, a patterned source/drain implantation mask118was formed above the device100.

Next, as shown inFIG. 2F, a so-called source/drain ion implantation process120was performed on the device100to form so-called deep source/drain implant regions120A in the substrate102. As noted previously, the source/drain ion implantation process120is typically performed using a higher dopant dose and at a higher implant energy than the extension ion implantation process110. The halo implant regions110A have a sufficient concentration of counter-dopant materials so as to effectively overwhelm the dopants implanted during the source/drain implantation process120. As a result, the source/drain implant regions120A effectively stop on the halo implant regions110A. However, as depicted inFIG. 2F, the portions of the source/drain implant regions120A that are not located above the halo implant regions110A effectively penetrate to a greater depth into the substrate102. That is, the source/drain implant regions120A positioned between the outermost edge110E of the halo implant regions110A and the inner edges104E of the isolation region104has a greater depth than does the portions of the source/drain regions120A that are positioned above the halo implant regions110A, i.e., the junction depth is deeper where the halo implant regions110A are absent. In this illustrative example, the deep source/drain ion implantation process120was performed using a dopant dose of 3-4 e15atoms/cm2and at an energy level of about 10-25 keV. In this illustrative example, the deep source/drain implant regions120A may have at peak-concentration a target depth of about 50-60 nm.

FIG. 2Gdepicts the device100after several process operations have been performed. First, the patterned source/drain implantation mask118was removed by performing another ashing process. Then, a heating or anneal process is performed to repair the damage to the lattice structure of the substrate102as a result of the various implantation processes and it activates the implanted dopant materials. During the heating process, the implanted dopant materials tend to migrate or move to at least some degree so as to merge together to at least some extent. In the depicted example, the extension implant regions114A and the deep source/drain implant regions120A merge together to form final source/drain regions122for the device100. The dopants implanted to form the halo implant regions110A have migrated to form final halo regions110X. The parameters of the heating process may vary depending on the particular application. In general, the heating process may be performed at a temperature in the range of about 800-1200° C. for a few milliseconds to a few seconds.

As will be appreciated by those skilled in the art after a complete reading of the present application, the device100depicted inFIG. 2Gpresents a novel source/drain junction architecture as compared to prior art devices. More specifically, in the device100depicted herein, the outer edge110E of the halo implant regions110A and the final halo regions110X do not extend all the way to the inner edge104E of the isolation region104. That is, there is a space or region125(in the gate length direction) between the inner edge104E of the isolation structure104and the outer edge110E of the halo implant regions110A and the final halo regions110X. As a result, the junction depth122X of the source/drain regions122that are positioned above this region125where the halo regions110X are not present is greater than it would have been if the halo regions110X extended all of the way to the inner edge104E of the isolation region104. Stated another way, the portions of the source/drain regions120positioned above the halo regions110X have a shallower junction depth than the junction depth122X of the portions of the source/drain regions122that are positioned above the region125where the halo regions110X are not present. In one illustrative embodiment, the portions of the source/drain regions122positioned above the region125may have a junction depth that is about 10-25 nm greater than the junction depth of the portions of the source/drain regions120positioned above the halo regions110X. The novel device disclosed herein may prove useful in many applications. For example, in the case where the device100has source/drain regions122that are very wide (in the channel length direction), e.g., a lateral width of about 200-4000 nm, the novel source/drain junction architecture disclosed herein permits the formation of source/drain regions122with deeper junction depths at distances that are spaced laterally far enough from the gate structure106while still providing the desired shallower junction depths for the source/drain regions122in areas that are closer to the gate structure106, i.e., closer to the actual channel region of the device100. Using the novel source/drain junction architecture disclosed herein, some of the leakage currents that would occur if the source/drain regions122had a substantially uniform shallow junction depth from the gate structure106to the isolation region104may be avoided by increasing the depth of the portion of the source/drain region122at the region125where the halo regions110X are not present.

As will be appreciated by those skilled in the art after a complete reading of the present application, various novel methods and devices are disclosed herein. One illustrative method disclosed herein involves forming an isolation region104in the substrate102so as to define an active region in the substrate102, forming a gate structure106above the active region and, after forming the gate structure106, forming a plurality of halo implant regions110A in the active region, wherein an outer edge110E of each of the halo implant regions110A is laterally spaced apart from an adjacent inner edge104E of the isolation region104.

Another illustrative method involves forming the isolation region104in the substrate102so as to define an active region in the substrate102, forming a gate structure106above the active region, after forming the gate structure106, forming a patterned halo implantation mask108that has an opening108A that exposes the gate structure106and a portion, but not all, of the active region positioned between the gate structure106and the isolation region104, and performing a plurality of angled ion implantation processes110through the patterned halo implantation mask108to form a plurality of halo implant regions110A in the substrate102.

Yet another illustrative method disclosed herein includes the steps of forming the isolation region104in a substrate102so as to define an active region in the substrate102, forming the gate structure106above the active region, after forming the gate structure106, forming a patterned halo implantation mask108that has an opening108A that exposes the gate structure106and a portion, but not all, of the active region positioned between the gate structure106and the isolation region104, and performing a plurality of angled ion implantation processes110through the patterned halo implantation mask108to form a plurality of halo implant regions110A in the substrate102, wherein an outer edge110E of each of the halo implant regions110is laterally spaced apart from an adjacent inner edge104E of the isolation region104. In this example, the method further includes performing an extension ion implantation process114through the patterned halo implantation mask108so as to form a plurality of extension implant regions114A in the substrate102, wherein an outer edge114E of each of the extension implant regions is laterally spaced apart from an adjacent inner edge104E of the isolation region104. Stated another way, each of the extension implant regions114A has first and second portions, and wherein the first portion is positioned above a corresponding halo implant region110A and the second portion is positioned adjacent the isolation region104and above a portion of the active region where the corresponding halo implant region110A is absent.

The subject matter disclosed herein is also directed to various embodiments of a transistor device. In one example, such a device includes an isolation region104positioned in the substrate102so as to define an active region in the substrate102, a gate structure106positioned above the substrate102, a plurality of source/drain regions122positioned in the active region on opposite sides of the gate structure106, each of the source/drain regions having a lateral width in a gate length direction of the transistor, and a plurality of halo regions110X positioned in the active region, wherein each of the halo regions110X is positioned under a portion, but not all, of the lateral width of one of the plurality of source/drain regions122.

Another illustrative device disclosed herein includes an isolation region104positioned in the substrate that defines an active region in the substrate, a gate structure106positioned above the substrate102, a plurality of source/drain regions122positioned in the active region on opposite sides of the gate structure122, wherein each of the source/drain regions extends to and contacts the isolation region104, and a plurality of halo regions110X positioned in the active region, wherein each of the halo regions110X has an outer edge110E that does not extend to and contact the isolation region104.