Semiconductor device and method of forming vertical structure

According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.

BACKGROUND

Vertical semiconductor devices, such as vertical gate-all-around transistors, are an emerging research area in the semiconductor industry. However, the process integration for the device is always a challenge because essentials of the device are vulnerable to oxidation. Therefore, there is a need to improve the above deficiency.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and the second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and the second features, such that the first and the second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

This disclosure provides a novel vertical structure having multiple barrier layers, which can be applied to vertical gate-all-around (VGAA) devices. The material of the barrier layers can be SiN, SiCN, or SiCON. The barrier layers isolate a source, a drain, a gate including high-K layer and a metal gate from oxidation by other processes. Therefore, the vertical structure having the barrier layers may decrease: nanowire oxidation caused by changing critical dimension of the nanowire; source/drain oxidation; high-K dielectrics oxidation caused by changing equivalent oxide thickness (EOT); and metal gate oxidation, due to annealing processes. Additionally, the barrier layers can be used as a hard mask during contact etching processes to form self-aligned contacts.

The vertical structure may be configured as follows: the substrate material may be Si, SiGe, Ge, or III/V Epi (InP, GaAs, AlAs, InAs, InAlAs, InGaAs, InSb, GaSb, InAlSb, InGaSb); the nanowire material may be Si, SiGe, Ge, or III/V Epi (InP, GaAs, AlAs, InAs, InAlAs, InGaAs, InSb, GaSb, InAlSb, InGaSb); the substrate material can be same or different with the nanowire material; the high-K dielectrics may be a single layer or multiple layers structure with HfO2, ZrO2, HfZrO2, Ga2O3, Gd2O3, TaSiO2, Al2O3, or TiO2; the work function metal (WFM) for PMOS vertical structures may be TiN, W, WN, Mo, or MoN; the WFM for NMOS vertical structures may be TiAl, TiAlC, or TaAlC; the metal gate (MG) material may be Al, W, Co, or Cu; the barrier layer material may be SiN, SiON, SiC, SiCN, SiCO, or SiCON; SAC metal material may be Al, W, Co, or Cu; Back-end-of-line (BEOL) metal material may be Al, W, Co, or Cu.

Additionally, the drain may refer to a region that has been treated as a drain, or a region that has not been treated but to be treated as a drain. The source may refer to a region that has been treated as a source, or a region that has not been treated but to be treated as a source. The channel may refer to a region that has been treated as a channel, or a region that has not been treated but to be treated as a channel.

FIG. 1is a sectional view illustrating an exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 1, a semiconductor device100is provided. In the semiconductor device100, a first vertical structure110, and a second vertical structure120are provided over a substrate101. The first vertical structure110and the second vertical structure120may be vertical-gate-all-around devices electrically isolated by shallow trench isolation102. The first vertical structure110may be a PMOS, and may include an n-well111, a first source112, a first channel113, and a first drain114. The second vertical structure120may be an NMOS, and may include a p-well121, a second source122, a second channel123, and a second drain124. Silicides116,126are used to reduce contact resistance.

The first source112is disposed over the n-well111. The first channel113is disposed over the first source112. The first drain114is disposed over the first channel113. The second source122is disposed over the p-well121. The second channel123is disposed over the second source122. The second drain124is disposed over the second channel123. The following procedures may be performed on the first vertical structure110and the second vertical structure120, so will only be discussed below with respect to the first vertical structure110.

In one embodiment, the substrate101includes a crystalline silicon substrate. In some alternative embodiments, the substrate101may be made of some other suitable elemental semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Further, the substrate101may include an epitaxial layer (epi-layer), may be strained for performance enhancement, and/or may include a silicon-on-insulator (SOI) structure.

FIG. 2is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 2, a first barrier layer202is formed over the source112, the channel113, and the drain114of the first vertical structure110to protect them from oxidation. The first barrier layer202may be formed of SiN, SiON, SiC, SiCN, SiCO, or SiCON. The first barrier layer202may have a thickness of, for example, about 30 to about 60 angstroms. In the embodiment, the first barrier layer202is formed in contact with the source112, the channel113, and the drain114; in some embodiment, there are other layers therebetween so that the first barrier layer202is formed not in contact with but adjacent to them.

A first interlayer dielectric204(e.g., an oxide layer) is formed over the first barrier layer202. To enhance quality of the first interlayer dielectric204, oxidation processes may be applied to the first interlayer dielectric204. In some embodiments, the enhancement is included in the formation of the first interlayer dielectric204. The source112, the channel113, and the drain114of the first vertical structure110are covered by the first barrier layer202, so that the oxidation processes for the enhancement does not damage or oxidize the first vertical structure110. A chemical mechanical polishing is performed on the first interlayer dielectric204and stops on the first barrier layer202. The protection that the first barrier layer202provides is not limited to the above oxidation and can be any that is likely to oxidize the first vertical structure110.

FIG. 3is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 3, the first interlayer dielectric204is etched back to form a bottom isolation layer302corresponding to the source112of the first vertical structure110by using wet etching or plasma etching. In the embodiment, the bottom isolation layer302is aligned with a top surface of the source112in conjunction with the channel113.

FIG. 4is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 4, the first barrier layer202is etched back, by using wet etching or plasma etching, and corresponds to the source112. In details, the first barrier layer202is aligned with the top surface of the source112in conjunction with the channel113.

FIG. 4ais a sectional view illustrating a detailed diagram of the left portion of the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 4a, the first interlayer dielectric204and the first layer202are well-controlled to etched back by using wet etching or plasma etching. In the embodiment, the first interlayer dielectric204is higher than a top surface of the source112about 0 to about 10 nanometers. The method will provide a device operating in an accumulation mode.

FIG. 4bis a sectional view illustrating another detailed diagram of the left portion of the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 4b, the first interlayer dielectric204and the first layer202are well-controlled to etched back by using wet etching or plasma etching. In the embodiment, the first interlayer dielectric204is lower than a top surface of the source112about 0 to about 10 nanometers. The method will provide a device operating in an inversion mode.

FIG. 5is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. Continuing fromFIG. 4, as shown inFIG. 5, a high-k dielectric layer502, work function metal (WFM) layers504,506, and a metal gate508are formed over the first vertical structure110. The high-K dielectric material may be a single layer or multiple layers structure with HfO2, ZrO2, HfZrO2, Ga2O3, Gd2O3, TaSiO2, Al2O3, or TiO2. The work function metal (WFM) may be TiN, W, WN, Mo, MoN, TiAl, TiAlC, or TaAlC. The metal gate material may be Al, W, Co, or Cu.

FIG. 6is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 6, the high-k dielectric layer502, the work function metal (WFM) layers504,506, and the metal gate508are etched back to expose the drain114.

FIG. 7is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 7, a portion of the high-k dielectric layer502, the work function metal (WFM) layers504,506, and the metal gate508above the STI102between the first vertical structure110and the second vertical structure120are etched back, and the etch-back stops on the bottom isolation layer302. A gate702is formed and includes the high-k dielectric layer502, the work function metal (WFM) layers504,506, and the metal gate508.

FIG. 8is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 8, a second barrier layer802is formed over the gate702and the drain114of the first vertical structure110, and the bottom isolation layer302so as to protect the gate702and the drain114from oxidation. In details, the second barrier layer802is formed in contact with a top and a sidewall of the gate702, and a top and a sidewall the drain114as well.

The second barrier layer802may be formed of SiN, SiON, SiC, SiCN, SiCO, or SiCON. The second barrier layer802may have a thickness of, for example, about 30 to about 60 angstroms. In the embodiment, the second barrier layer802is formed in contact with the gate702and the drain114; in some embodiment, there are other layers therebetween so that the second barrier layer802is formed not in contact with but adjacent to them.

FIG. 9is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 9, a second interlayer dielectric902(e.g., an oxide layer) is formed over the second barrier layer802. In some embodiments, the enhancement is included in the formation of the second interlayer dielectric902. To enhance quality of the second interlayer dielectric902, oxidation processes may be applied to the second interlayer dielectric902. The gate702and the drain114of the first vertical structure110are covered by the second barrier layer802so that the oxidation processes for the enhancement does not damage or oxidize the first vertical structure110. Furthermore, a chemical mechanical polishing is performed on the second interlayer dielectric902and stops on the second barrier layer802. The protection that the second barrier layer802provides is not limited to the above oxidation and can be any that is likely to oxidize the first vertical structure110.

FIG. 10is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 10, the second interlayer dielectric902and the second barrier layer802are etched back to expose a top of the drain114of the first vertical structure110by using wet etching or plasma etching.

FIG. 11is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 11, a metal is deposited on the drain114, and annealing is performed on the metal to form a silicide1102.

FIG. 11ais a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. Continuing fromFIG. 9, as shown inFIG. 11athe second interlayer dielectric902and the second barrier layer802are etched back to expose not only a top of the drain114but also a portion of a sidewall of the drain114by using wet etching or plasma etching. Moreover, a metal is deposited the top and the sidewall of the drain114, and annealing is performed on the metal to form a silicide1102ahaving a greater width than the silicide1102inFIG. 11.

FIG. 12is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. Continuing fromFIG. 11, as shown inFIG. 12, a pad1202is formed on the silicide1102. A third interlayer dielectric1204(e.g., an oxide layer) is formed over the second interlayer dielectric902and the pad1202.

FIG. 13is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 13, an opening1302is formed through the first barrier layer202, the first interlayer dielectric204, the second barrier layer802, the second interlayer dielectric902, and the third interlayer dielectric1204. The formation of the opening1302may include: to etch the third interlayer dielectric1204and the second interlayer dielectric902; to etch the second barrier layer802; to etch the first interlayer dielectric204; to etch the first barrier layer202. The second barrier layers802can be used a hard mask during such formation of the opening1302to protect the gate702from unexpected damage.

FIG. 14is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 14, a contact metal1402is formed in the opening1302. A chemical mechanical polishing is performed on the contact metal1402and stops on the third interlayer dielectric1204.

In the abovementioned processes, the first barrier layer202protects the source112, the channel113, and the drain114of the first vertical structure110from the formation of the bottom isolation layer302which may damage or oxidize the first vertical structure110. The second barrier layer802protects the gate702and the drain114from the formation of the second interlayer dielectric902which may damage or oxidize the first vertical structure110.

The abovementioned disclosure shows one embodiment, and the following description disclosure will introduce another embodiment with other types of barrier layers.

FIG. 15is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. Continuing fromFIG. 4, as shown inFIG. 15, a high-k dielectric layer1502, a work function metal (WFM) layers1504, and a metal gate1508are formed over the first vertical structure110. Compared toFIG. 5, the formation does not fill the recess between the first vertical structure110and the second vertical structure120with the metal gate1508but as a thin layer inFIG. 15.

FIG. 16is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 16, a portion of the high-k dielectric layer1502, the work function metal (WFM) layer1504, and the metal gate1508above the STI102between the first vertical structure110and the second vertical structure120are etched back, and the etch-back stops on the bottom isolation layer302.

FIG. 17is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 17, a second barrier layer1702is formed over the high-k dielectric layer1502, the work function metal layer1504, and the metal gate1508so as to protect them from oxidation. The second barrier layer1702may be formed of SiN, SiON, SiC, SiCN, SiCO, or SiCON. The second barrier layer1702may have a thickness of, for example, about 30 to about 60 angstroms. In the embodiment, the second barrier layer1702is formed in contact with the high-k dielectric layer1502, the work function metal layer1504, the metal gate1508and the bottom isolation layer302; in some embodiment, there are other layers therebetween so that the second barrier layer1702is formed not in contact with but adjacent to them.

A second interlayer dielectric1704(e.g., an oxide layer) is formed over the second barrier layer1702. To enhance quality of the second interlayer dielectric1704, oxidation processes may be applied to the second interlayer dielectric1704. In some embodiments, the enhancement is included in the formation of the second interlayer dielectric1704. The high-k dielectric layer1502, the work function metal layer1504, and the metal gate1508are covered by the second barrier layer1702so that the oxidation processes for the enhancement does not damage or oxidize the first vertical structure110. The protection that the second barrier layer1702provides is not limited to the above oxidation and can be any that is likely to oxidize the first vertical structure110.

FIG. 18is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 18, a chemical mechanical polishing is performed on the second interlayer dielectric1704and stops on the second barrier layer1702. Moreover, the second interlayer dielectric1704is etched back as a middle isolation layer1802to be aligned with a top of the channel113in conjunction with the drain114.

FIG. 19is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 19, the second barrier layer1702, the high-k dielectric layer1502, the work function metal layer1504, and the metal gate1508are etched back to disconnect from the drain114.

FIG. 20is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 20, a third barrier layer2002is formed over the high-k dielectric layer1502, the work function metal layer1504, the metal gate1508, and a sidewall of the drain114so as to protect them from oxidation. The third barrier layer2002may be formed of SiN, SiON, SiC, SiCN, SiCO, or SiCON. The formation of the third barrier layer2002may include: to conformally form the third barrier layer2002; and to perform dry etching on the third barrier layer2002to expose the drain114. In the embodiment, the third barrier layer2002is formed in contact with the high-k dielectric layer1502, the work function metal layer1504, the metal gate1508, and a sidewall of the drain114; in some embodiment, there are other layers therebetween so that the third barrier layer2002is formed not in contact with but adjacent to them.

FIG. 21is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 21, a metal is deposited on the drain114, and annealing is performed on the metal to form a silicide2102.

FIG. 22is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 22, a pad2202is formed on the silicide2102. A third interlayer dielectric2204(e.g., an oxide layer) is formed over the middle isolation layer1802and the pad2202as a top isolation layer.

FIG. 23is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 23, an opening2302is formed through the first barrier layer202, the first interlayer dielectric204, the second barrier layer1702, the second interlayer dielectric1802, and the third interlayer dielectric2204. The formation of the opening1302may include: to etch the third interlayer dielectric2204and the second interlayer dielectric1802; to etch the second barrier layer1702; to etch the first interlayer dielectric204; to etch the first barrier layer202. In some embodiments, when the metal gate1508is closer to the opening2302, the second barrier layers1702can be used a hard mask during such formation of the opening2302to protect the metal gate1508from unexpected damage.

FIG. 24is a sectional view illustrating the exemplary semiconductor device in accordance with some embodiments. As shown inFIG. 24, a contact metal2402is formed in the opening2302. A chemical mechanical polishing is performed on the contact metal2402and stops on the third interlayer dielectric2204.

In the abovementioned processes, the first barrier layer202protects the source112, the channel113, and the drain114of the first vertical structure110from the formation of the bottom isolation layer302which may damage or oxidize the first vertical structure110. The second barrier layer1702protects the high-k dielectric layer1502, the work function metal layer1504, and the metal gate1508from the formation of the middle isolation layer1802which may damage or oxidize the first vertical structure110. The third barrier layer2002protects the high-k dielectric layer1502, the work function metal layer1504, the metal gate1508, and the drain114from the formation of the top isolation layer2204which may damage or oxidize the first vertical structure110. Each of the formation of the bottom isolation layer302, the middle isolation layer1802, and the top isolation layer2204respectively corresponds to the source112, the gate in contact with the channel113, and the drain114.

FIG. 25is a flow chart for a method of forming a vertical structure with at least two barrier layers. As shown inFIG. 25, a method2500is provided. The method2500includes the following operations: providing a substrate (2502); providing a vertical structure over the substrate (2504); providing a first barrier layer over a source, a channel, and a drain of the vertical structure (2506); and providing a second barrier layer over a gate and the drain of the vertical structure (2508).

The method2500may further include forming a first interlayer dielectric over the first barrier layer corresponding to the source of the vertical structure. The method2500may further include forming the gate over the channel of the vertical structure. The method2500may further include forming a second interlayer dielectric over the second barrier layer corresponding to the gate and the drain of the vertical structure. The method2500may further include: performing chemical mechanical polishing on the second interlayer dielectric and stopping on the second barrier layer; etching the second interlayer dielectric and the second barrier layer to expose a top of the drain; and forming silicide on the drain.

The method2500may further include: forming an opening through the first barrier layer, the first interlayer dielectric, the second barrier layer, and the second interlayer dielectric; and forming contact metal in the opening. The method2500may further include etching the second barrier layer to expose the drain and a top of the gate; and forming a third barrier layer as a spacer over the top of the gate and a sidewall of the drain. The operation2508may further include providing the second barrier layer in contact with a sidewall of the drain of the vertical structure. The operation2508may further include providing the second barrier layer in contact with a sidewall of the drain and a top and a sidewall of the gate of the vertical structure.

FIG. 26is a flow chart for a method of forming a vertical structure. As shown inFIG. 26, a method2600is provided. The method2600includes the following operations: providing a substrate (2602); providing a vertical structure over the substrate (2604); and providing a barrier layer over the vertical structure to protect the vertical structure from oxidation (2606).

The operation2606may further include providing the barrier layer over the vertical structure to protect the vertical structure from oxidation during formation of an oxide layer. The operation2606may further include providing the barrier layer over a source of the vertical structure to protect the source during formation of the oxide layer corresponding to the source. The operation2606may further include providing the barrier layer over a gate of the vertical structure to protect the gate during formation of the oxide layer corresponding to the gate. The operation2606may further include providing the barrier layer over a drain of the vertical structure to protect the drain during formation of the oxide layer corresponding to the drain.

According to an exemplary embodiment, a method of forming a vertical structure with at least two barrier layers is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; providing a first barrier layer over a source, a channel, and a drain of the vertical structure; and providing a second barrier layer over a gate and the drain of the vertical structure.

According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing a vertical structure over the substrate; and providing a barrier layer over the vertical structure to protect the vertical structure from oxidation.

According to an exemplary embodiment, a semiconductor device is provided. The device includes: a substrate; a vertical device over the substrate and having a source, a gate and a drain; and a barrier layer over the gate and the drain of the vertical structure.