Digital PLL device

An input clock dividing unit frequency-divides an input clock, and an input clock multiplying unit frequency-multiplies the input clock. An operation clock selecting unit selects the frequency-divided clock when the input clock is fast and selects the frequency-multiplied clock when the input clock is slow, based on the frequency detection result of frequency detecting unit. The operation clock selecting unit then outputs the selected clock to a phase comparing unit as an operation clock. The phase comparing unit operates according to the frequency-divided or frequency-multiplied clock, and controls an oscillating unit so that the phase difference between a reference signal and a comparison signal becomes zero. The phase of an output clock is thus caused to track the phase of the reference signal.

RELATED APPLICATIONS

This application is the U.S. National Phase under 35 U.S.C. §371 of International Application No. PCT/JP2008/001827, filed on Jul. 8, 2008, which in turn claims the benefit of Japanese Application No. 2007-190405, filed on Jul. 23, 2007, the disclosures of which Applications are incorporated by reference herein.

TECHNICAL FIELD

The present invention generally relates to a digital PLL device. More particularly, the present invention relates to a digital PLL device that is used for, for example, regeneration of an audio clock from a clock transmitted through a digital interface such as IEEE 1394 and HDMI (High-Definition Multimedia Interface) used in a digital television and an AV amplifier.

BACKGROUND ART

Many digital interfaces employ a system in which a parameter is created by a transmitting party according to a predetermined formula and a required audio clock is regenerated from a transmitted clock by using the parameter. As a typical structure of this system, a digital PLL is used by itself or in combination with an analog PLL.

It has been common in the art to use a transmitted clock as an operation clock of a digital PLL for regenerating a clock (e.g., see Non-patent document 1).

FIG. 7is a block diagram showing a structure of a conventional digital PLL device.

The conventional digital PLL device ofFIG. 7includes an n dividing unit1, a phase comparing unit2, an oscillating unit3, and an m dividing unit4.

As shown inFIG. 7, the n dividing unit1frequency-divides a clock transmitted through a digital interface by n to produce a digital PLL reference signal. The phase comparing unit2operates by using the transmitted clock as an operation clock. The phase comparing unit2obtains the phase difference between the reference signal generated by the n dividing unit1and a comparison signal generated by dividing an output clock by m in the m dividing unit4, and outputs a control signal so as to reduce the phase difference. The oscillating unit3changes the output clock by the control signal received from the phase comparing unit2. This operation is repeated as a feedback loop, whereby the phase of the output clock is caused to track (lock to) the phase of the reference signal.

For example, in an HDMI specification, parameters N and CTS are prepared as parameters for regenerating an audio clock. These parameters are defined by the following formula:
CTS=(transmitted clock×N)/(128×Fs)
where Fs (Sampling Frequency) indicates an audio clock.

A source device as a transmitter determines the value of CTS by counting the number of transmitted clocks in each of the (128×Fs/N) clocks. A sink device as a receiver frequency-divides the transmitted clock by CTS to generate a digital PLL reference signal. By repeating an operation of comparing the phase of a comparison signal generated by frequency-dividing an output signal by N with the phase of the generated reference signal and controlling the output clock so that the phase difference becomes zero, the phase of the comparison signal is caused to track the phase of the reference signal. By thus locking the output clock to (128×Fs), Fs can be regenerated by the sink device.

DISCLOSURE OF THE INVENTION

Problems to be Solved by the Invention

When a transmitted clock is fast in the above conventional digital PLL device, an operation clock is fast, causing increase in circuit scale and significant increase in power consumption. When the transmitted clock is slow, on the other hand, the operation clock is slow, causing increase in jitter and increase in tracking time.

The transmitted clock has been increasingly becoming faster especially due to Deep Color defined in the HDMI specification, recent higher definition of image, and the like. Under such circumstances, conventional digital PLL devices have been increasingly suffering from problems such as increased circuit scale and significantly increased power consumption.

The conventional PLL devices thus have problems such as increased circuit scale, increased power consumption, increased jitter, and increased tracking time depending on the transmitted clock rate.

In view of the above problems, it is an object of the present invention to provide a digital PLL device having a structure capable of suppressing increase in circuit scale and increase in power consumption when a transmitted clock is fast, and to provide a digital PLL device having a structure capable of suppressing increase in jitter and increase in tracking time when a transmitted clock is slow.

Means for Solving the Problems

In order to achieve the above object, a digital PLL device according to one aspect of the present invention includes: an operation clock generating unit configured to output a frequency-divided or frequency-multiplied input clock as an operation clock; an n dividing unit configured to frequency-divide an input clock by n to output a reference signal; a phase comparing unit configured to compare the reference signal with a comparison signal and output a control signal; an oscillating unit configured to change an oscillation frequency of an output clock according to the control signal; and an m dividing unit configured to frequency-divide the output clock by m to output the comparison signal.

In the digital PLL device according to the above aspect of the present invention, the operation clock generating unit is an output clock dividing unit configured to frequency-divide the input clock and output the resultant clock as the operation clock.

In this case, the n dividing unit frequency-divides the operation clock instead of the input clock by n to output the reference signal, and the digital PLL device further includes an input clock multiplying unit configured to frequency-multiply an output of the oscillating unit and output the resultant clock.

In the digital PLL device according to the above aspect of the present invention, the operation clock generating unit is an input clock multiplying unit configured to frequency-multiply the input clock and output the resultant clock as the operation clock.

In this case, the n dividing unit frequency-divides the operation clock instead of the input clock by n to output the reference signal, and the digital PLL device further includes an output clock dividing unit configured to frequency-divide an output of the oscillating unit and output the resultant clock.

In the digital PLL device according to the above aspect of the present invention, the operation clock generating unit further includes an input clock dividing unit configured to frequency-divide the input clock and output the resultant clock, an input clock multiplying unit configured to frequency-multiply the input clock and output the resultant clock, and an operation clock selecting unit configured to select the output of the input clock dividing unit or the output of the input clock multiplying unit and output the selected output as the operation clock.

In this case, the digital PLL device further includes a frequency detecting unit configured to detect a frequency of the input clock and output a frequency detection result, wherein the operation clock selecting unit selects the output of the input clock dividing unit or the output of the input clock multiplying unit based on the frequency detection result.

In the digital PLL device according to the above aspect of the present invention, the n dividing unit frequency-divides the operation clock from the operation clock selecting unit instead of the input clock by n to output the reference signal, and the digital PLL device further includes: an output clock multiplying unit configured to frequency-multiply an output of the oscillating unit and output the resultant clock; an output clock dividing unit configured to frequency-divide the output of the oscillating unit and output the resultant clock; and an output clock selecting unit configured to select the output of the output clock multiplying unit or the output of the output clock dividing unit and output the selected output.

In this case, the digital PLL device further includes a frequency detecting unit configured to detect a frequency of the input clock and output a frequency detection result, the operation clock selecting unit selects the output of the input clock dividing unit or the output of the input clock multiplying unit based on the frequency detection result, and the output clock selecting unit selects the output of the output clock multiplying unit or the output of the output clock dividing unit based on the frequency detection result.

In the digital PLL device according to the above aspect of the present invention, the phase comparing unit operates according to the operation clock.

In the digital PLL device according to the above aspect of the present invention, the input clock is transmitted through a digital interface.

In the digital PLL device according to the above aspect of the present invention, the digital interface is IEEE 1394 or HDMI.

Effects of the Invention

As has been described above, the digital PLL device according to one aspect of the present invention can reduce the circuit scale, power consumption, jitter, and tracking time regardless of the transmitted clock rate, as compared to conventional digital PLL devices.

The transmitted clock rate has been rapidly increased due to, for example, an improved resolution resulting from Deep Color defined by the HDMI specification or recent increase in screen size of display devices. Accordingly, increase in circuit scale and increase in power consumption due to the high-speed operation, for example, can be suppressed by operating the digital PLL device based on a frequency-divided fast transmitted clock. In the case where the high-speed operation of the transmitted clock is not required such as in low-end devices, increase in jitter and increase in tracking time due to the low-speed operation, for example, can be suppressed by operating the digital PLL device based on a frequency-multiplied transmitted clock.

DESCRIPTION OF THE REFERENCE NUMERALS

2phase comparing unit

5input clock dividing unit

6input clock multiplying unit

7operation clock selecting unit

9output clock multiplying unit

10output clock dividing unit

11output clock selecting unit

BEST MODE FOR CARRYING OUT THE INVENTION

First Embodiment

FIG. 1is a block diagram showing a structure of a digital PLL device according to a first embodiment of the present invention.

The digital PLL device according to the first embodiment of the present invention shown inFIG. 1includes an n dividing unit1, a phase comparing unit2, an oscillating unit3, an m dividing unit4, and an input clock dividing unit5.

Operation of the digital PLL device of the present embodiment having the above structure will now be described.

As shown inFIG. 1, the n dividing unit1frequency-divides an input clock transmitted through a digital interface by n (n is a natural number) to generate a digital PLL reference signal. The input clock dividing unit5frequency-divides the input clock and outputs the resultant clock to the phase comparing unit2as an operation clock. The phase comparing unit2operates according to the operation clock received from the input clock dividing unit5. The phase comparing unit2obtains the phase difference between the reference signal generated by the n dividing unit1and a comparison signal generated by frequency-dividing an output clock by m (m is a natural number) in the m dividing unit4, and outputs a control signal so that the phase difference becomes zero. The oscillating unit3changes the output clock by the control signal received from the phase comparing unit2.

Provided that the input clock frequency is x hertz and the output clock frequency is y hertz, the reference signal frequency is x/n hertz. Since the phase of the comparison signal tracks the phase of the reference signal, the comparison signal frequency is also x/n hertz. The output clock frequency is therefore y=(x×m)/n hertz. A desired output clock is thus obtained.

As has been described above, according to the digital PLL device of the first embodiment of the present invention, the phase comparing unit2can be operated by using a frequency-divided input clock as an operation clock. This structure suppresses increase in circuit scale and increase in power consumption caused by high-speed operation due to a high-speed transmitted clock, as compared to conventional digital PLL devices in which the phase comparing unit2is operated by using an input clock directly as an operation clock.

Note that the input clock and the frequency dividing parameters m and n may be transmitted through a digital interface. This structure is effective in the case where a clock cannot be transmitted directly but a clock synchronized with a transmitting party needs to be generated. Examples of such a digital interface include audio transmission of IEEE 1394 or HDMI.

Second Embodiment

FIG. 2is a block diagram showing a structure of a digital PLL device according to a second embodiment of the present invention.

The digital PLL device according to the second embodiment of the present invention shown inFIG. 2includes an n dividing unit1, a phase comparing unit2, an oscillating unit3, an m dividing unit4, and an input clock multiplying unit6. Note that, as compared to the structure of the digital PLL device of the first embodiment shown inFIG. 1, the structure of the digital PLL device of the present embodiment is characterized by including the input clock multiplying unit6configured to frequency-multiply an input clock instead of the input clock dividing unit5of the first embodiment configured to frequency-divide an input clock.

Operation of the digital PLL device of the present embodiment having the above structure will now be described.

As shown inFIG. 2, the n dividing unit1frequency-divides an input clock transmitted through a digital interface by n to generate a digital PLL reference signal. The input clock multiplying unit6frequency-multiplies the input clock and outputs the resultant clock to the phase comparing unit2as an operation clock. The phase comparing unit2operates according to the operation clock received from the input clock multiplying unit6. The phase comparing unit2obtains the phase difference between the reference signal generated by the n dividing unit1and a comparison signal generated by frequency-dividing an output clock by m in the m dividing unit4, and outputs a control signal so that the phase difference becomes zero. The oscillating unit3changes the output clock by the control signal received from the phase comparing unit2.

Provided that the input clock frequency is x hertz and the output clock frequency is y hertz, the reference signal frequency is x/n hertz. Since the phase of the comparison signal tracks the phase of the reference signal, the comparison signal frequency is also x/n hertz. The output clock frequency is therefore y=(x×m)/n hertz. A desired output clock is thus obtained.

As has been described above, according to the digital PLL device of the second embodiment of the present invention, the phase comparing unit2can be operated by using a frequency-multiplied input clock as an operation clock. This structure suppresses increase in jitter and increase in tracking time caused by low-speed operation due to a low-speed transmitted clock, as compared to conventional digital PLL devices in which the phase comparing unit2is operated by using an input clock directly as an operation clock.

Note that the input clock and the frequency dividing parameters m and n may be transmitted through a digital interface. This structure is effective in the case where a clock cannot be transmitted directly but a clock synchronized with a transmitting party needs to be generated. Examples of such a digital interface include audio transmission of IEEE 1394 or HDMI.

Third Embodiment

FIG. 3is a block diagram showing a structure of a digital PLL device according to a third embodiment of the present invention.

The digital PLL device according to the third embodiment of the present invention shown inFIG. 3includes an n dividing unit1, a phase comparing unit2, an oscillating unit3, an m dividing unit4, an input clock dividing unit5, an input clock multiplying unit6, an operation clock selecting unit7, and a frequency detecting unit8.

As compared to the structures of the digital PLL devices of the first and second embodiments shown inFIGS. 1 and 2, the structure of the digital PLL device of the present embodiment is characterized by including the input clock dividing unit5of the first embodiment configured to frequency-divide an input clock and the input clock multiplying unit6of the second embodiment configured to frequency-multiply an input clock, and characterized by further including the operation clock selecting unit7configured to select the clock frequency-divided by the input clock dividing unit5or the clock frequency-multiplied by the input clock multiplying unit6and output the selected clock as an operation clock. The digital PLL device of the third embodiment may further include the frequency detecting unit8configured to detect an input clock frequency and output the detection result to the operation clock selecting unit7so that the operation clock selecting unit7can select an optimal operation clock.

The digital PLL device of the third embodiment of the present invention therefore has the effects of both the first and second embodiments described above. More specifically, as compared to conventional digital PLL devices in which the phase comparing unit2is operated by using an input clock directly as an operation clock, the digital PLL device of the third embodiment suppresses increase in circuit scale and increase in power consumption caused by high-speed operation due to a high-speed transmitted clock and also suppresses increase in jitter and increase in tracking time caused by low-speed operation due to a low-speed transmitted clock. Moreover, since the digital PLL device of the third embodiment includes the frequency detecting unit8, an optimal operation clock can be selected according to the operation speed, based on the input clock frequency. The digital PLL device of the third embodiment can therefore operate rationally.

Note that the input clock and the frequency dividing parameters m and n may be transmitted through a digital interface. This structure is effective in the case where a clock cannot be transmitted directly but a clock synchronized with a transmitting party needs to be generated. Examples of such a digital interface include audio transmission of IEEE 1394 or HDMI.

Fourth Embodiment

FIG. 4is a block diagram showing a structure of a digital PLL device according to a fourth embodiment of the present invention.

The digital PLL device according to the fourth embodiment of the present invention shown inFIG. 4includes an n dividing unit1, a phase comparing unit2, an oscillating unit3, an m dividing unit4, an input clock dividing unit5, and an output clock multiplying unit9.

Operation of the digital PLL device of the present embodiment having the above structure will now be described.

As shown inFIG. 4, the input clock dividing unit5frequency-divides an input clock transmitted through a digital interface and outputs the resultant clock to the phase comparing unit2and also to the n dividing unit1as an operation clock. The n dividing unit1frequency-divides the clock received from the input clock dividing unit5by n to generate a digital PLL reference signal. The phase comparing unit2operates according to the operation clock received from the input clock dividing unit5. The phase comparing unit2obtains the phase difference between the reference signal generated by the n dividing unit1and a comparison signal generated by frequency-dividing an output clock by m in the m dividing unit4, and outputs a control signal so that the phase difference becomes zero. The oscillating unit3changes the output clock by the control signal received from the phase comparing unit2. The output clock multiplying unit9frequency-multiplies the clock received from the oscillating unit3and outputs the resultant clock.

Provided that the input clock frequency is x hertz, the output clock frequency is y hertz, and the frequency-dividing factor of the input clock dividing unit5is a, the reference signal frequency is x/(a×n) hertz. Since the phase of the comparison signal tracks the phase of the reference signal, the comparison signal frequency is also x/(a×n) hertz. The output clock frequency of the oscillating unit3is therefore y′=(x×m)/(a×n) hertz. A desired output clock is thus obtained by using the value a as a frequency-multiplying factor of the output clock multiplying unit9.

As has been described above, according to the digital PLL device of the fourth embodiment of the present invention, the phase comparing unit2can be operated by using a frequency-divided input clock as an operation clock. This structure suppresses increase in circuit scale and increase in power consumption caused by high-speed operation due to a high-speed transmitted clock, as compared to conventional digital PLL devices in which the phase comparing unit2is operated by using an input clock directly as an operation clock.

Note that the input clock and the frequency dividing parameters m and n may be transmitted through a digital interface. This structure is effective in the case where a clock cannot be transmitted directly but a clock synchronized with a transmitting party needs to be generated. Examples of such a digital interface include audio transmission of IEEE 1394 or HDMI.

Fifth Embodiment

FIG. 5is a block diagram showing a structure of a digital PLL device according to a fifth embodiment of the present invention.

The digital PLL device according to the fifth embodiment of the present invention shown inFIG. 5includes an n dividing unit1, a phase comparing unit2, an oscillating unit3, an m dividing unit4, an input clock multiplying unit6, and an output clock dividing unit10. Note that, as compared to the structure of the digital PLL device of the fourth embodiment shown inFIG. 4, the structure of the digital PLL device of the present embodiment is characterized by including the input clock multiplying unit6configured to frequency-multiply an input clock instead of the input clock dividing unit5configured to frequency-divide an input clock in the fourth embodiment, and by including the output clock dividing unit10configured to frequency-divide a clock received from the oscillating unit3and output the resultant clock instead of the output clock multiplying unit9configured to frequency-multiply a clock received from the oscillating unit3in the fourth embodiment.

Operation of the digital PLL device of the present embodiment having the above structure will now be described.

As shown inFIG. 5, the input clock multiplying unit6frequency-multiplies an input clock transmitted through a digital interface and outputs the resultant clock to the phase comparing unit2and also to the n dividing unit1as an operation clock. The n dividing unit1frequency-divides the clock received from the input clock multiplying unit6by n to generate a digital PLL reference signal. The phase comparing unit2operates according to the operation clock received from the input clock multiplying unit6. The phase comparing unit2obtains the phase difference between the reference signal generated by the n dividing unit1and a comparison signal generated by frequency-dividing an output clock by m in the m dividing unit4, and outputs a control signal so that the phase difference becomes zero. The oscillating unit3changes the output clock by the control signal received from the phase comparing unit2. The output clock dividing unit10frequency-divides the clock received from the oscillating unit3and outputs the resultant clock.

Provided that the input clock frequency is x hertz, the output clock frequency is y hertz, and the frequency-multiplying factor of the input clock multiplying unit6is b, the reference signal frequency is (x×b)/n hertz. Since the phase of the comparison signal tracks the phase of the reference signal, the comparison signal frequency is also (x×b)/n hertz. The output clock frequency of the oscillating unit3is therefore y′=(x×b×m)/n hertz. A desired output clock is thus obtained by using a frequency-dividing factor b in the output clock dividing unit10.

As has been described above, according to the digital PLL device of the fifth embodiment of the present invention, the phase comparing unit2can be operated by using a frequency-multiplied input clock as an operation clock. This structure suppresses increase in jitter and increase in tracking time caused by low-speed operation due to a low-speed transmitted clock, as compared to conventional digital PLL devices in which the phase comparing unit2is operated by using an input clock directly as an operation clock.

Note that the input clock and the frequency dividing parameters m and n may be transmitted through a digital interface. This structure is effective in the case where a clock cannot be transmitted directly but a clock synchronized with a transmitting party needs to be generated. Examples of such a digital interface include audio transmission of IEEE 1394 or HDMI.

Sixth Embodiment

FIG. 6is a block diagram showing a structure of a digital PLL device according to a sixth embodiment of the present invention.

The digital PLL device according to the sixth embodiment of the present invention shown inFIG. 6includes an n dividing unit1, a phase comparing unit2, an oscillating unit3, an m dividing unit4, an input clock dividing unit5, an input clock multiplying unit6, an operation clock selecting unit7, a frequency detecting unit8, an output clock multiplying unit9, an output clock dividing unit10, and an output clock selecting unit11.

As compared to the structures of the digital PLL devices of the fourth and fifth embodiments shown inFIGS. 4 and 5, the structure of the digital PLL device of the present embodiment is characterized by including the input clock dividing unit5configured to frequency-divide an input clock in the fourth embodiment and the input clock multiplying unit6configured to frequency-multiply an input clock in the fifth embodiment, and by including the operation clock selecting unit7configured to select the clock frequency-divided by the input clock dividing unit5or the clock frequency-multiplied by the input clock multiplying unit6and output the selected clock to the n dividing unit1and the phase comparing unit2. The structure of the digital PLL device of the present embodiment is also characterized by including the output clock multiplying unit9configured to multiply a clock received from the oscillating unit3and output the resultant clock and the output clock dividing unit10configured to frequency-divide a clock received from the oscillating unit3and output the resultant clock, and by including the output clock selecting unit11configured to select the clock frequency-multiplied by the output clock multiplying unit9or the clock frequency-divided by the output clock dividing unit10and output the selected clock. The digital PLL device of the present embodiment may further include the frequency detecting unit8configured to detect an input clock frequency and output the detection result to the operation clock selecting unit7and the output clock selecting unit11, so that the operation clock selecting unit7and the output clock selecting unit11can select an optimal operation clock.

The digital PLL device of the sixth embodiment of the present invention therefore has the effects of both the fourth and fifth embodiments described above. More specifically, as compared to conventional digital PLL devices in which the phase comparing unit2is operated by using an input clock directly as an operation clock, the digital PLL device of the sixth embodiment suppresses increase in circuit scale and increase in power consumption caused by high-speed operation due to a high-speed transmitted clock and also suppresses increase in jitter and increase in tracking time caused by low-speed operation due to a low-speed transmitted clock. Moreover, since the digital PLL device of the sixth embodiment includes the frequency detecting unit8, an optimal operation clock can be selected according to the operation speed, based on the input clock frequency. The digital PLL device of the sixth embodiment can therefore operate rationally.

Note that the input clock and the frequency dividing parameters m and n may be transmitted through a digital interface. This structure is effective in the case where a clock cannot be transmitted directly but a clock synchronized with a transmitting party needs to be generated. Examples of such a digital interface include audio transmission of IEEE 1394 or HDMI.

Industrial Applicability

The digital PLL device of the present invention is useful in the case where a clock cannot be transmitted directly but a clock synchronized with a transmitting party needs to be generated, such as when audio data is transmitted through a digital interface.

The digital PLL device of the present invention is particularly useful in the case where the transmitted clock rate is increased due to, for example, an improved resolution resulting from Deep Color defined by the HDMI specification or recent increase in size of display devices.