Vertical stacking of graphene in a field-effect transistor

A graphene field-effect transistor is disclosed. The graphene field-effect transistor includes a first graphene sheet, a first gate layer coupled to the first graphene sheet and a second graphene sheet coupled to the first gate layer opposite the first gate layer. The first gate layer is configured to influence an electric field within the first graphene sheet as well as to influence an electric field of the second graphene sheet.

BACKGROUND

The present invention relates to semiconductor electronics, and more specifically, to graphene field-effect transistors.

Graphene exhibits exceptional electronic properties such as a relative high carrier mobility and transconductance. These exceptional properties enable graphene to be used to form graphene field-effect transistors (GFETs), which may be useful in applications up to the terahertz frequency region. A typical GFET includes a source contact and a drain contact with a graphene sheet extending between them to form a gated channel. The GFET operates, in part, by modulating the conductance of the graphene sheet, usually via a gate contact metal proximate the graphene sheet. One of the leading challenges in GFET technology is that the intrinsic properties of the graphene are substantially compromised at the interfaces of the GFET, i.e., metal source/drain contacts, gate dielectrics, supporting substrates, etc. These interfaces produce sizable contact resistance, reduced carrier mobility due to scattering centers, and many other hindrances.

SUMMARY

According to one embodiment of the present invention, a graphene field-effect transistor includes: a first graphene sheet; a first gate layer coupled to the first graphene sheet configured to influence an electric field within the first graphene sheet; and a second graphene sheet coupled to the first gate layer opposite the first gate layer, wherein the first gate layer is configured to influence an electric field of the second graphene sheet.

According to another embodiment of the present invention, a gate region of a transistor includes: a plurality of alternating layers of gate layers and graphene sheets; and an electrical coupling between the gate layers.

According to another embodiment of the present invention, a transistor includes: a plurality of alternating layers of gate layers and graphene sheets; an electrical coupling device configured to couple the gate layers to each other; and at least one of a source contact and a drain contact, wherein the graphene sheets are configured to couple to the at least one of the source contact and the drain contact.

DETAILED DESCRIPTION

FIG. 1shows an exemplary single layer of a gate region of an exemplary graphene transistor100disclosed herein. The gate region is formed on a substrate102. Substrate102has a first gate contact metal104aformed in a recess of the substrate102to form a substantially co-planar surface with the substrate102. In exemplary embodiments, the substrate102is a silicon substrate. The gate contact metal104amay be palladium or other suitable contact metal in exemplary embodiments. A dielectric layer106ais formed on the surface of the substrate102and covers at least a portion of the gate contact metal104a. The dielectric layer106amay include hafnium oxide (HfO2), Al2O3or other suitable dielectric material. A graphene sheet108is disposed on the dielectric layer106. The graphene sheet108extends between regions of the substrate102that are on opposite sides of the gate contact metal104a. A second dielectric layer106bis formed on top of the graphene sheet108and a second gate contact metal104bis formed on top of the second dielectric layer106b. Therefore, the exemplary single layer100includes a graphene sheet108surrounds to gate contact metals104aand104bat opposing surfaces of the graphene sheet108and separated from the gate contact metals104aand104bvia dielectric layers106aand106b, respectively. The gate contact metals104aand104bmay be electrically coupled via electrical wires or other suitable electrical coupling device or method. These gate contact metals104aand104bare therefore responsive to a same applied voltage, and the conductance of the graphene sheet108may be modulated via a voltage applied at both surfaces (i.e., top and bottom surfaces) of the graphene sheet108.

FIG. 2shows an exemplary GFET200that includes multiple stacked graphene sheets206a,206band206c. The exemplary GFET200includes a plurality of graphene sheets206a,206band206cstacked on top of each other with interleaving gate layers202aand202bon a substrate102to form a gate region. The height of the gate region is related to the number of graphene sheets206a,206band206c. The graphene sheets206a,206band206cextend between a source contact210and a drain contact212and provide multiple parallel gate channels between the source contact210and drain contact212. Three graphene sheets206a,206band206care shown inFIG. 2for illustrative purposes. However, it is understood that a GFET formed using the methods disclosed herein may have any number of graphene sheets. The number of graphene sheets may affect various transistor parameters, such as drain current and/or transconductance, for example. Thus, the number of graphene sheets may be selected to form a GFET having a parameter that is within a selected criterion. It is also understood that the number of gate layers may be increased without increasing the footprint of the transistor, i.e., the surface area of the substrate taken up by the transistor.

In the exemplary multiple-gate GFET200, the plurality of graphene sheets206a,206band206cmay be separated by interleaved gate layers such as exemplary gate layers202aand202b. Gate layer202aincludes a gate contact metal204athat is sandwiched between a dielectric material208aon one side of the gate contact metal204band a dielectric material208bon an opposing side of the gate contact metal204b. In exemplary embodiments, the dielectric materials208aand208bare the same material. Similarly, gate layer202bincludes gate contact metal204bsandwiched between dielectric material208cand dielectric material208d. Top graphene sheet206cis covered by dielectric layer208eand gate contact metal204c. Thus, each graphene sheet is surrounded by gate contact metal at each surface. In exemplary embodiments, the gate layers202aand202bmay be electrically coupled to each other. In particular, the gate contact metals240a,204band204cmay be electrically coupled to each other. The coupled gate contact metals204a,204band204cmay thus be coupled to a same voltage source. Thus, a uniform voltage may be applied through each of the gate contact metals240a,204band204c. A voltage applied to a gate contact metal such as gate contact metal204balters an electric field in its adjacent graphene sheets, i.e., graphene sheets206band206c. Additionally, a selected graphene sheet such as graphene sheet206bmay have its internal electric field affected by voltage applied at its adjacent gate contact metals, i.e., gate contact metals204aand204b.

FIGS. 3-8show exemplary stages for manufacturing the multi-layer graphene field-effect transistor200shown inFIG. 2.FIG. 3shows a first manufacturing stage of the GFET200in which a sheet of graphene304is disposed on a substrate302, such as a silicon dioxide substrate. The substrate is typically 1 micrometer (μm) in thickness. The graphene sheet304may be grown independently using, for example, chemical vapor deposition (CVD) of the graphene on a copper foil and then transferred onto the silicon substrate302. A resist (not shown) may then be formed on the graphene sheet304and the silicon substrate102to protect a segment of the initial graphene sheet from lithographic process that patterns the graphene sheet for the active transistor device. In an exemplary embodiment, the resist may include a bilayer resist of hydrogen silsesquioxiane (HSQ 2%) on poly(methylmethacrylate) (PMMA). Electron beam lithography (EBL) may then be used to pattern the bilayer resist to form a mask. A reactive ion etch may be used to remove graphene in the exposed region. The etching process leaves the graphene sheet304as shown in theFIG. 3.

FIG. 4shows a second stage of the manufacturing process in which source and drain contacts are formed. Source306aand drain306bmay be formed by forming a resist layer on the substrate, using electron beam lithography on the resist layer to expose a region. A metal is then deposited in the exposed region to form the source306aand the drain306busing, for example, atomic layer deposition. The source306aand drain306bare formed so as to be electrically coupled to the graphene sheet304. In an exemplary embodiment, the metal used in the source306aand drain306bis palladium (Pd), although any suitable metal may be used. In an exemplary embodiment, the thickness of the source306aand drain306bis about 30 nanometers (nm), although any suitable thickness may be used. After the atomic layer deposition of the source306aand drain306b, the resist layer is lifted off of the substrate using, for example, hot acetone.

FIG. 5shows a third stage of the manufacturing process in which a dielectric layer502ais formed on the graphene sheet304. The dielectric layer502amay be formed by a method of resist deposition, lithography, atomic layer deposition of a dielectric material and resist take off. In an exemplary embodiment, electron beam lithography is used to pattern a region of the exposed graphene304. After the region is exposed, trimethylaluminum (TMA) and water precursors in NO2may be deposited on the graphene sheet to form a seed layer. In an exemplary embodiment, the TMA and water precursor in NO2are deposited over a 10 cycle deposition process. Once the seed layer is formed, atomic layer deposition may be used to form a dielectric layer of hafnium oxide (HfO2), Al2O3or other suitable high-k dielectric material. In an exemplary embodiment, the dielectric layer has a thickness of about 10 nm.

FIG. 6shows a fourth stage of the manufacturing process in which gate contact metal502bis formed on the dielectric layer502aofFIG. 5. The gate layer502bmay be formed by resist deposition, lithography, atomic layer deposition of the gate contact metal and resist take-off using hot acetone. In an exemplary embodiment, the metal of the gate contact metal502bmay be palladium or other suitable contact material. In an exemplary embodiment, the gate contact metal502bhas a thickness of about 10 nm. The transistor that is formed after this fourth stage is equivalent to a top-gated graphene FET. This top-gated graphene FET may be tested after the fourth stage and before continuing the manufacturing process.

FIG. 7shows a fifth stage of the manufacturing process in which a second dielectric layer502cis deposited on the gate contact metal502bofFIG. 6. Deposition of the second dielectric layer502ccompletes formation of a gate layer of the multi-level graphene FET, such as exemplary gate layer102a. The process for forming the second dielectric layer is similar to the process of forming the first dielectric layer shown inFIG. 5. The second dielectric layer may include hafnium oxide or other suitable dielectric material. In an exemplary embodiment, the second dielectric layer502chas a thickness of about 10 nm.

The gate layer102athus comprises first dielectric layer502ahaving a thickness of 10 nm, gate contact metal502bhaving a thickness of 10 nm and second dielectric layer502chaving a thickness of 10 nm. Therefore, the thickness of the gate layer102is approximately 30 nm and is the same thickness as the source402aand drain402b. The top surfaces of the gate layer102a, the source402aand the drain402btherefore form substantially coplanar surfaces that may be used for further graphene sheet deposition and transistor growth.

FIG. 8shows a sixth stage of the manufacturing process in which a second graphene sheet804of the GFET200is formed. The second graphene sheet804may be formed using the same process as the first graphene sheet ofFIG. 1. In other words, a CVD-grown graphene material is deposited on the surfaces provided by the gate layer102, the source402aand drain402band etched to a selected dimension to provide the second graphene sheet804. The second graphene sheet804is formed so as to be electrically coupled to the source306aand the drain306b. At the end of the sixth stage, there are two independent, vertically stacked graphene sheets304and804that are gated by the same gate contact metal503band in contact with the same source402aand same drain404b. The presence of the second graphene sheet804enhances a performance characteristic of the GFET while maintaining a footprint of the GFET at the substrate, i.e., without increasing the surface area required by the GFET at the substrate102.

FIG. 9shows a flowchart900illustrating an exemplary method of forming the graphene FET of the present invention. In block902, a graphene sheet is transferred to a substrate and patterned and etched to form a first graphene sheet of the GFET that provide a gate channel of the GFET. In block904, source and drain contacts are formed on the first graphene sheet. In an exemplary embodiment, a resist is deposited and patterned. Metals are then deposited in the patterned area of the resist to form the source and drain contacts and the resist is lifted off. In block906, the first dielectric layer is formed on the first graphene sheet. In an exemplary embodiment, a resist is deposited and patterned to expose and area of the first graphene sheet. A dielectric material is deposited in the patterned area of the resist to form the first dielectric layer and the resist is lifted off. In block908, a gate contact metal is deposited on the first dielectric layer. In an exemplary embodiment, a resist is deposited and patterned to expose the first dielectric layer. The gate contact metal is then deposited on the exposed first dielectric layer and the resist is lifted off. In block910, a second dielectric layer is deposited on the gate contact metal formed in block908. In an exemplary embodiment, a resist is deposited and patterned to expose at least a portion of the gate contact metal. A dielectric material is deposited on the exposed portion of the gate contact metal to form the second dielectric layer and the resist is lifted off. At this point an operable gate channel has been completed. Therefore, in block912, an operator determines whether the most recently completed gate channel is the last gate channel of the GFET to be formed. This decision is generally based on a design specification selected by the operator. If this is the final gate channel, the process proceeds to block914where it ends. Otherwise, a second graphene sheet is transferred to the substrate to lie on top of the gate channel formed in blocks906,908and910as well as on top of the source and drain contacts formed in block904. This second graphene sheet forms a second gate channel of the GFET parallel to the first gate channel. From block916, the process returns to block904and more layers are deposited to form the next layer of gate channels. This process may be continued to form any number of gate channels. Once the final gate channel is completed, the gate contact metals may be electrically coupled using, for example, a wire connection or bonding method.

FIG. 10shows an exemplary graph illustrating the effect of multiple graphene sheets on various parameters of the exemplary GFET of the present invention. The gate-source voltage is shown along the x-axis in volts. Drain current (Id) is shown along the left-side y-axis as measured in microamps per micrometer. Transconductance is shown along the right-side y-axis as measured in microsiemens per micrometer. Drain current1002arepresents the drain current for an exemplary single-layer GFET of the present invention. Drain current1002brepresents the drain current for an exemplary double-layer GFET of the present invention. Clearly, the drain current1002bof the double-layer GFET is increased over the drain current1002aof the single-layer GFET. Transconductance1004arepresents the transconductance for the exemplary single-layer GFET. Transconductance1004brepresents the transconductance for the exemplary double-layer GFET. The transconductance1004bof the double-layer GFET is increased over the transconductance1004aof the single-layer GFET.