INTEGRATION OF ADVANCED PHOTONIC MATERIALS IN SILICON PHOTONIC PLATFORM

Embodiments herein describe a photonic platform having a chiplet with a Pockels effect electro-optic layer made of LN or BTO and a substrate. The chiplet is bonded to a photonic wafer which includes a waveguide. In this manner, a ridge waveguide formed by the Pockels effect electro-optic layer and the waveguide utilizes electro-optic effects to tune a signal.

TECHNICAL FIELD

Embodiments presented in this disclosure generally relate to silicon photonics. More specifically, embodiments disclosed herein relate to middle-end-of-line (MEOL) integration of Lithium niobate and Barium titanate thin films in silicon photonic waveguides.

BACKGROUND

As the growth in the volume of communication network traffic continually increases, the need for development of network components to support the increased traffic also increases. Network connectivity speeds continue to increase to facilitate this growth in traffic as networks transition from 10G to 100G to 800G and beyond. Current Silicon photonic technologies based on P-type, intrinsic, and N-type (PIN) or silicon-insulator-silicon capacitor (SISCAP) based modulators n support 224G serializer/deserializer (SERDES) speeds. However, material, structural, and other limitations of the current silicon photonic platforms present a challenge to future implementations of higher network traffic speeds. A silicon photonic platform that includes electro-optic materials could overcome many of the limitations of photonic platforms that rely solely on silicon materials. An additional benefit would be the integration of electro-optic materials during middle-end of line (MEOL) processes.

For example, silicon is self-limiting as a medium for optical modulation. Silicon exhibits two-photon absorption effects that result in free carrier absorption. Two photon absorption is a non-linear effect occurring within an optical waveguide that increase optical loss within the optical waveguide. Silicon modulators also have low energy efficiency due to permanent injection currents. Furthermore, silicon modulators employing a reverse biased p-n junction require a long phase modulation length in excess of 1 mm. The large footprint required by these devices is not suitable for high density optical circuits. Finally, forward biased PIN diodes suffer from low modulation speeds. The effect of these limitations is that silicon optical modulators suffer from poor function in high-speed modulation and non-linear modulation.

DESCRIPTION OF EXAMPLE EMBODIMENTS

Overview

One embodiment presented in this disclosure includes a method of manufacturing a photonic platform. The method includes providing a chiplet that includes a Pockels effect electro-optic layer and a substrate, bonding the chiplet to a photonic wafer such that the Pockels effect electro-optic layer is optically coupled to a waveguide disposed within the photonic wafer, and removing the substrate after bonding the chiplet to the photonic wafer.

Another embodiment presented in this disclosure is silicon photonic platform that includes a semiconductor wafer comprising a waveguide, a Pockels effect electro-optic layer disposed over, and optically coupled to, the waveguide, a first electrode electrically coupled to a first end of the Pockels effect electro-optic layer, and a second electrode electrically coupled to a second end of the Pockels effect electro-optic layer where a wafer bondline is disposed between the Pockels effect electro-optic layer and the waveguide.

EXAMPLE EMBODIMENTS

As described above silicon-based modulators are commonly integrated into photonic devices. The silicon platform combines photonic and electronic elements on the same chip while capitalizing on a mature silicon wafer industry. The combination of developed silicon wafer manufacturing techniques and the well-known qualities of silicon semiconductors allows for low-cost production. However, silicon based optical modulators suffer from poor function in high-speed modulation and non-linear modulation.

As the growth in the volume of communication network traffic continually increases, the need for development of network components to support the increased traffic also increases. Network connectivity speeds continue to increase to facilitate this growth in traffic. However, material, structural, and other limitations of the current silicon photonic platforms present a challenge to future implementations of higher network traffic speeds. The limitations of silicon photonic platforms are inherent to silicon. Silicon photonic platforms suffer from poor performance where high-speed modulation or non-linear modulation is useful.

The examples and embodiments that follow include Pockels effects based devices permit high-speed, low-power electro-optical modulation and are effective non-linear modulators. Materials such as LN and BTO exhibit Pockels Effects. The application of LN or BTO within photonic platforms offers several advantages. One such advantage is that LN or BTO modulates optical signals through an electro-optic effect. The electro-optic effect permits modulation of a signal through change in phase shift due to an alteration of the refractive index of a crystal by an applied electric field. The electro-optic effects of the crystal can be broadly classified as either longitudinal electro-optic effects or transverse electro-optic effects. Longitudinal electro-optic effects describe changes to the crystal when an electric field is applied along the propagation direction of light. Transverse electro-optic effects describe changes to the crystal when an electric field is applied perpendicular to the direction of propagation of the light. Electro-optic effects have very short response times, on the order of 1010 Hz. This very fast response time permit high-speed modulation of a propagating signal. Electro-optic materials exhibit modification of the refractive index of the material by the application of a direct current (DC) or low frequency electric field. The applied low frequency electric field is much lower than the optical frequency.

Generally, for electro-optic materials a modification of the refractive index may occur through polarization. The magnitude of material polarization is proportional to the strength of an applied electric field. The magnitude of the material polarization as a function of the applied external electric field is: |{right arrow over (P)}|=ϵ0χe|{right arrow over (E)}|+ϵ0χ(2)|{right arrow over (E)}|2+ϵ0χ(3)|{right arrow over (E)}|3+ . . . . The effect due to the ϵ0χ(2)|{right arrow over (E)}|2term is the Pockels effect. Pockels effect exhibits material polarization as a function of the square of the external field. The Pockels effect or Pockels electro-optic effects materializes as a change in birefringence induced by the electric field. An electric field causes electron or crystal lattice displacements which result in changes in the refractive index. The index of refraction (neo) attributed to the Pockels effect is estimated by:

Where nxis the index of refraction, γ is the Pockels coefficient having units m/V, E is the applied electric field, and s is the Kerr coefficient having units m2/V2. From this equation the change in the applied electric field alters the index of refraction by the Pockels effect term: ½γnx2|E|. By altering the index of refraction, Pockels effect materials like LN or BTO can alter the phase, frequency, amplitude, and/or polarization of the effected signal.

The embodiments described herein include a silicon photonic platform that includes a waveguide. The waveguide includes a LN or BTO layer for modulation of an optical signal carried by a silicon waveguide. Together the LN or BTO layer and the silicon nitride layer form a ridge waveguide that modulates optical signals more efficiently, is easier to construction, and utilizes MEOL processes to improve manufacturing.

FIG.1illustrates a wafer100that has a substrate101and an electro-optical layer105. The substrate101can have silicon substrate with option of having additional dielectric layer103(e.g., silicon dioxide) and an optional silicon layer104. The electro-optical layer105can be LN or BTO. An optional dielectric layer106can be also deposited or formed on layer105to improve bonding properties of the final surface. For example, the dielectric layer106can be used to bond the structure to another wafer. As discussed in more detail below, multiple chiplets can be cut from the wafer100and be placed (bonded) on a larger photonic platform in a manner where the LN or BTO layer105becomes part of a ridge waveguide.

LN and BTO are electro-optic materials and the placement of the chiplet on a larger photonic platform is more simple, efficient, and effective than growing a LN or BTO layer directly on the larger photonic platform. Unlike silicon-based waveguides that rely on dopants to provide charges facilitating their functionality, LN or BTO waveguides use an applied electric field. Both LN and BTO exhibit electro-optic effects due to Pockels Effect. The ability of LN and BTO materials to change their bifringence through the application of an electric field creates efficient electro-optic modulators. Some benefits of this approach are that a LN or BTO electro-optic layer is not grown on the photonic platform and avoids typical semiconductor manufacturing steps such as deposition, photoresist, lithography etching, and ionization.

Additional qualities of LN that make it an attractive material are LN has a melting point of 1250° C., a trigonal crystal system, a no refractive index of 2.30, and a ne refractive index of 2.21. In addition to electro-optic modulators, other applications for LN include high-performance acoustic wave filters. For electro-optical modular applications, thin film LN on insulator wafers (e.g., where the structure includes a silicon substrate/dielectric/LN layer) offer small size, stability, large bandwidth, high transmission rate, low power consumption, compatibility with CMOS driving voltage, and enabling optical integration. Thin film LN wafers can be fabricated using a smart cut process by transferring a thin film of LN layer on a silicon wafer with insulator (typically oxide).

In another embodiment, BTO is used as the electro-optical material to make high-speed electro-optic modulators. BTO is a ferroelectric, pyroelectric, and piezoelectric ceramic material that has a melting point of 1,625° C., a tetragonal crystal system, a no refractive index of 2.412, and a ne refractive index of 2.360. BTO enables Pockels-effect-based devices on silicon. Some of the benefits of applying BTO is its large Pockels coefficients, BTO can be grown on silicon substrates with large wafer sizes, and BTO exhibits excellent crystal quality. BTO is also a chemically and thermally stable material. BTO can be grown on wafers having a range of wafer diameters from 50 mm to 300 mm independent of the diameter of the photonic platform wafer. BTO can be grown on silicon or insulator surface with good crystal quality.

FIG.2illustrates a photonic platform silicon on insulator (SOI) wafer201of a device200constructed by a front end of line (FEOL) process. The wafer201includes a photodiode202(e.g., a germanium photodiode) and a plurality of waveguides203,204,205,206, a buried oxide layer207and a silicon substrate208. The waveguide204can be a silicon nitride waveguide or silicon waveguide. The waveguide205is an optional second silicon nitride waveguide. The waveguide203is a multi-level silicon waveguide and can be used to form grating couplers or wave-guiding structures. In one embodiment, the silicon waveguide203has a thickness less than 400 nm. Photodiode202can also be integrated in the photonics platform wafer.

Integration of thin film LN or BTO as part of a Middle End of Line (MEOL) process flow includes bonding LN or BTO chiplets after the FEOL which includes the formation of the Si and nitride waveguides203,204,205,206, germanium photodiode epitaxial and implants/anneals and prior to BEOL (Back End of Line) processing which includes metallization, Interlayer dielectric (ILD) formation and in some cases, wafer-to-wafer bonding.

FIG.3illustrates one embodiment of MEOL attachment of a LN or BTO chiplet301to the photonic platform silicon wafer201to form a device300. It should be noted here that other MEOL implementation of integration of LN or BTO chiplets on210are also possible. The chiplet301is bonded at a bond line at a top surface of the wafer201.

As depicted inFIG.1, from the LN or BTO wafer100, a plurality of smaller LN or BTO chiplets301are manufactured. A single LN or BTO chiplet301die can be cut from the larger LN or BTO wafer100. Each LN or BTO chiplet301has the same layers of the LN or BTO wafer100. However, as described earlier, the layers104and106can be optional. The layers103and106can be made of silicon oxide or silicon nitride or any other integrated circuit fabrication compatible dielectric layers. The dimensions of the LN or BTO chiplets301is sized to match the required optic-electric signals carried by the waveguide. In this example, each chiplet301is bonded to the photonic wafer201in a MEOL process to form an electro-optic connection with waveguide204. The union of the LN or BTO layer105with waveguide204forms a ridge waveguide structure capable of modulating the phase of the waveguide signal.

FIG.4Aillustrates the MEOL step of removing the first layer102(e.g., the substrate) of a device400. After attachment of the LN or BTO chiplet401to the photonic wafer201, the first layer102is removed. The final configuration of is a chiplet401electro-optically connected to the first nitride waveguide204forming a ridge waveguide402. The ridge waveguide402, at a minimum, the LN or BTO layer105, and nitride waveguide204. Much like the device depicted inFIG.1, the layers104and106may be omitted.

FIG.4Billustrates attaching a laser chiplet403(e.g., an III-V laser epi chiplet) to the photonic wafer201, in addition to the BTO or LN chiplet401. The position of the laser chiplet403is such that it will form ridge waveguide with the waveguide204. The laser chiplet403can have Multiple Quantum Well (MQW) or Multiple Quantum Dot (MQD) structure407. After bonding, a substrate406of the laser chiplet403is removed as shown inFIG.4C. This can be followed by additional MEOL and BEOL processing steps similar to shown inFIGS.6-8to convert the structure407into a laser structure.

FIG.5illustrates an additional embodiment of the device depicted inFIG.1. In the device500, a silicon nitride layer501is added during MEOL processing to the chiplet401. For simplicity, the process steps to form silicon nitride layer501are not described and can include conventional IC fabrication process steps such as deposition, photolithography, etch, and chemical mechanical processing. The addition of the silicon nitride layer501improves phase efficiency and facilitates mode engineering.

FIG.6illustrates additional MEOL elements added to the device ofFIG.4Ato form device600. Electrodes602,603are added to connect the LN or BTO layer to an electric field. Electrode602is located distal from the midline of the LN or BTO layer. Electrode603is located distal from both electrode602and the midline of the LN or BTO layer. An electric charge applied to electrodes602and603induces an electric field in the ridge waveguide402. The applied electric fields allow birefringence and phase adjusting. Additional elements include electrodes604,605, and606, first level metal (M1-A) connection607, a second first level metal connection (M1-B)608, and nitride layers609,610, and614. The nitride layers609,610, and614can be nitride caps to provide an upper diffusion barrier for the metal underneath.

In one embodiment, the layers609,610, and614are formed by a single layer deposition and etching using photolithography process. Although not shown inFIG.6, a waveguide (e.g., a nitride waveguide) can also be formed using the same deposition and etching photo lithography process and at the same time the layers609,610, and614are formed but without having metal layer beneath it. That is, nitride waveguides may be disposed in the same layer of the device600as the layers609,610, and614. Electrodes602,603,604,605, and606can be made using tungsten (W) or any other appropriate metals. Inter-metal dielectric layer (IDL)601may be formed using multiple deposition, etching, and polishing steps as part of the integration scheme to create metal separating dielectric. The IDL601can be tetraethyl orthosilicate (TEOS), silicon, silicon dioxide, or other suitable material, or a combination thereof. Further, the laser structure407ofFIG.4Ccan be added to the structure inFIG.6, in which case additional steps can be performed to create metal contacts to the laser layer.

Layers611,612, and617are diffusion barrier layers and are formed using a single deposition and etching using photolithography process. The choice of diffusion barrier layer is dependent on the choice of metal system used for the metal connections607,608, and616.

The M1-A connection608may also have a nitride layer610located on the proximal side of M1-A connection608. Nitride layer610extends over both sides of M1-A connection608. M1-A connection608forms an electrical connection with the LN or BTO layer105through electrode603. M1-A connection608is connected to photodiode202through electrode606. M1-A connection608is connected to waveguide206through electrode605.

A second first level metal connection607also has a nitride layer609located on the proximal side of M1-B607. The connection607is connected to the LN or BTO layer105by way of electrode602. An additional electrode604connects the connection607with waveguide203.

Connection613is a connection between M1 layers and second metal layer M2 above it (not shown in the figure). While not shown, addition BEOL processes can be performed on the device600to form a large number of additional metal layers (for example two to fifteen layers) with electrical connections between them.

FIG.7illustrates another embodiment in which a Through Silicon Via (TSV)705is also implemented prior to formation of M1 layer in a device700. The TSV705extends from a metal connection616(which is part of the first metal layer) deep inside the Si substrate208and provides electrical connection to the back side of the wafer when wafer is thinned to reveal the TSV705from back side. Layer710is a dielectric that provides electrical isolation between the TSV705and substrate208. Typical thickness of the silicon substrate208after thinning (not shown in the figure) may be in the range of 50-125 ums and additional processing steps can be performed to create additional layers on the back side of the wafer.

In another embodiment, a wafer-to-wafer bonding based BEOL flow is described inFIG.8A through8D. It is to be noted that a large number of BEOL options are available and the process flow described here is not limiting.

FIG.8Ashows a silicon photonic wafer800with BTO or LN integration and two layers of metals (rather than just one metal layer as shown inFIG.6). That is, the wafer800illustrates a metal layer801being added above, and connected to, the IDL601to form two metal layers. It is to be noted that the wafer800can include any number of metal layers (e.g., only one metal layer or more than two metal layers).

FIG.8Bshows a separate handle wafer850that has two metal layers860disposed on silicon substrate208. However, in other embodiments, the wafer850may not include any metal layer (and can simply include a dielectric layer on top of the substrate208). Or the wafer850can include only one metal layer, or more than two metal layers. In this example, the wafer850also includes an optional TSV865that is isolated by a dielectric870from the substrate208.

As shown inFIG.8C, the two wafers800and850fromFIGS.8A and8Bare bonded at a bonding interface875to form a combined wafer880.FIG.8Dillustrates, after wafer bonding inFIG.8C, the substrate of the wafer800(e.g., a photonic wafer) is removed and a contact885(e.g., a via) is formed to at least one metal layer in the wafer800. Further, in this example, an optional contact886(e.g., a via) is also formed to connect to at least one metal layer of the wafer850(assuming this handle wafer has a metal layer). After forming the contacts885and886, additional metal layers can be formed that includes the metal routes887and888and additional contacts such as the contact889.

FIG.9illustrates a method900of manufacture of the photonic platform. Method900can refer to the elements inFIGS.1-8. At block901a chiplet301that includes a Pockels effect electro-optic layer (e.g., a BTO or LN layer) and a substrate (e.g., the substrate101inFIG.1) is provided. The chiplet301may include any of the optional other layers illustrated inFIG.1.

At block902, the chiplet is bonded during a MEOL process to a photonic wafer (e.g., wafer201inFIG.2) such that the Pockels effect electro-optic layer is optical coupled to a waveguide (e.g., waveguide204inFIG.2) disposed within the wafer.

At block903, the substrate of the chiplet is removed. Moreover, in addition to bonding the chiplet to the wafer, the method900can include bonding the laser structure (e.g., the laser chiplet403) to the wafer and removing its substrate406.

At block904, metal layers (e.g., metal connections607and608), electrical connections (e.g., connection613), and additional waveguides are formed on the combined chiplet and photonic wafer structure.

At block905, a handle wafer (e.g., wafer850inFIG.8C) is attached to the combined chiplet and photonic wafer structure. After attaching the handle wafer, backside metals can (optionally) be formed on the structure, such as the metal routes888and887shown inFIG.8Das part of a back end of line (BEOL) process. Note that this block is applicable toFIGS.8A-8Dand may not be used when forming the structures illustrated inFIGS.6and7.