Reducing the load on the bitlines of a ROM bitcell array

Systems, apparatuses, and methods for reducing the load on the bitlines of a ROM bitcell array are described. The connections between nets of a ROM bitcell array may be assigned based on their programmed values using a traditional approach. Then, a plurality of optimizations may be performed on the assignment of nets to reduce the load on the bitlines of the array. A first optimization may swap the connections between ground and bitline for the nets of a given column responsive to detecting that the number of connections to the corresponding bitline is greater than the number of connections to ground for the given column. A second optimization may remove the connection of a net to a bitline if three consecutive nets of a given column are connected to the bitline.

BACKGROUND

Technical Field

Embodiments described herein relate to the field of integrated circuit design and more particularly, to methods for reducing the load on the bitlines of a ROM bitcell array.

Description of the Related Art

The semiconductor industry aims to manufacture integrated circuits with higher and higher densities of semiconductor devices on a smaller chip area to achieve greater functionality and to reduce manufacturing costs. This desire for large scale integration has led to a continued shrinking of circuit dimensions and device features. However, as technological advances enable smaller integrated circuit features, spacing between devices and layers is reduced, thereby increasing capacitance. The increased capacitance results in degraded performance, increased current leakage, and decreased reliability. The impact will be more significant if there is a large load on a long running wire.

In view of the above, methods and mechanisms for reducing the load on integrated circuit wires are desired.

SUMMARY

Systems, apparatuses, and methods for reducing the load on bitlines in memory cell array are contemplated.

Embodiments of an apparatus configured to perform optimizations of memory cell arrays are contemplated. In various embodiments, the array is a Read Only Memory (ROM) bitcell array. In one embodiment, the apparatus corresponds to a tool that is configured to analyze the initial layout of a ROM bitcell array to detect one or more conditions for optimizing the layout of the array. Such a tool may be, for example, a design tool or ROM bitcell programming tool. If a first condition is detected, a first optimization step may be performed to reduce the load on the bitlines of the ROM bitcell array. In one embodiment, first condition may comprise determining that the number of nets connected to a bitline is greater than the number of nets connected to ground for a given column of the ROM bitcell array. In such an embodiment, the design tool may analyze each column of the ROM bitcell array to determine if the first condition is detected for the column. In various embodiments, the first optimization step may comprise swapping connections between the bitline and ground for the given column. The first optimization may be performed for each column of the ROM bitcell array for which the first condition is detected.

In various embodiments, the design tool may also determine if a second condition is detected for the initial layout of the ROM bitcell array. In one embodiment, the second condition may comprise detecting three consecutive nets of a given column connected to a corresponding bitline. In another embodiment, the second condition may comprise detecting that two nets at a start or an end of a given column are connected to a corresponding bitline. In these embodiments, the design tool may analyze each column of the ROM bitcell array to determine if the second condition is detected for any of the columns of the array.

If the second condition is detected for any of the columns of the ROM bitcell array, then the design tool may perform a second optimization step. In one embodiment, the second optimization step may comprise removing at least one connection to the bitline for the three consecutive nets of the given column. In another embodiment, the second optimization step may comprise removing a connection to the bitline for a net at the start or end of the given column. When the connection to the bitline is removed for a given net, the given net may be left floating or shorted with the other leg of the same bitcell if the other leg is also floating. In further embodiments, other optimization steps may also be performed on the initial layout of the ROM bitcell array. The layout of the ROM bitcell array may then be finalized using the one or more optimization steps applied to the initial layout.

These and other features and advantages will become apparent to those of ordinary skill in the art in view of the following detailed descriptions of the approaches presented herein.

DETAILED DESCRIPTION OF EMBODIMENTS

Referring now toFIG. 1, a diagram of one embodiment of a base read-only memory (ROM) bitcell100is shown. It is noted that while the following uses a ROM type memory cell for purposes of discussion, those skilled in the art will appreciate that the methods and mechanisms described herein may be applied to other memory cells and circuit types. In the example shown, bitcell100may be configured to store a single bit. In one embodiment, bitcell100may be a single n-channel Mosfet (NMOS) transistor. The gate110of bitcell100may be connected to a wordline (e.g., corresponding to a row in an array of cells). The two terminals (drain106and source108) are shown as floating but can be connected to bitline102(e.g., corresponding to a column in an array of cells) or VSS104(ground), depending on the data value (0 or 1) which is programmed to bitcell100. It is noted that bitcell100is intended to represent a bitcell in accordance with one embodiment. Other types of bitcells and transistor technologies may be utilized in other embodiments.

Turning now toFIG. 2, two diagrams illustrating bitcells programmed with a value of ‘0’ are shown. In the top diagram200, the drain is connected to the bitline while the source is connected to VSS. In the bottom diagram205, the drain is connected to VSS while the source is connected to the bitline. Either approach may be used to program the bitcell to a value of ‘0’.

Referring now toFIG. 3, diagrams illustrating bitcells programmed with a value of ‘1’ are shown. Various connections may be utilized to program a bitcell with a value of ‘1’. For example, both terminals (drain and source) may be connected to VSS to program the bitcell with a value of ‘1’ as shown in diagram300. Also, both the drain and the source may be connected to the bitline as shown in diagram305to program the bitcell with a value of ‘1’. Alternatively, one terminal (drain or source) may be connected to the bitline and the other may be floating to program the bitcell with a value of ‘1’ as shown in diagram310. Still further, one terminal may be connected to VSS and the other may be floating to program the bitcell with a value of ‘1’ as shown in diagram315. Additionally, both terminals may be floating as shown in diagram320to program the bitcell with a value of ‘1’. Still further, the drain and source may be connected together as shown in diagram325to program the bitcell with a value of ‘1’. Additional ways of connecting a bitcell in order to program the bitcell with a value of ‘1’ may also be utilized.

It should be understood that the value designations shown inFIGS. 2 and 3may be reversed in another embodiment. For example, in another embodiment, the value of ‘1’ may be programmed using the connections shown inFIG. 2while the value of ‘0’ may be programmed using the connections shown inFIG. 3. Generally speaking, the diagrams shown inFIG. 2may be utilized to store a first type of information (e.g., a binary value of ‘0’) and the diagrams shown inFIG. 3may be utilized to store a second type of information (e.g., a binary value of ‘1’).

Turning now toFIG. 4, a diagram of one embodiment of programming a ROM bitcell array400is shown. The values used for programming the ROM bitcell array400are shown at the bottom ofFIG. 4. Accordingly, the first (leftmost) column405of ROM bitcell array400may be programmed to store “0111001”, the second column410may be programmed to store “0101111”, the third column415may be programmed to store “1101100”, the fourth column420may be programmed to store “1111011”, and the fifth column425may be programmed to store “1111111”. These values are merely intended to represent one possible set of values which may be used to program a ROM bitcell array400. ROM bitcell array400is one example of how the nets (i.e., drains and sources) of individual bitcells may be connected in one embodiment using a traditional programming approach.

Referring now toFIG. 5, one embodiment of a prior art method500for determining how to program a bitcell array is shown. For purposes of discussion, the steps in this embodiment are shown in sequential order. It should be noted that in various embodiments of the method described below, one or more of the elements described may be performed concurrently, in a different order than shown, or may be omitted entirely. Other additional elements may also be performed as desired. Any of the various devices, apparatuses, and/or systems described herein may be configured to implement method500.

Method500may start by determining if the current net being processed is the first net of the bitcell array column (conditional block505). If the current net is not the first net of the bitcell array column (conditional block505, “no” leg), then the tool may determine if the bitcell is assigned to be programmed as a ‘0’ (conditional block510). If the bitcell is assigned to be programmed as a ‘1’ (conditional block510, “no” leg), then the tool may determine if the previous net is connected to the bitline (BL) (conditional block515). If the previous net is not connected to the bitline (conditional block515, “no” leg), then the tool may connect the next net to VSS (block520). If the previous net is connected to the bitline (conditional block515, “yes” leg), then the tool may connect the next net to the bitline (block525).

If the bitcell is assigned to be programmed as a ‘0’ (conditional block510, “yes” leg), then the tool may determine if the previous net is connected to the bitline (conditional block530). If the previous net is connected to the bitline (conditional block530, “yes” leg), then the tool may connect the next net to VSS (block535). If the previous net is not connected to the bitline (conditional block530, “no” leg), then the tool may connect the next net to the bitline (block540).

If this net is the first net of the bitcell array column (conditional block505, “yes” leg), then the tool may connect the net to the bitline (block545). Next, the tool may determine if the bitcell is assigned to be programmed as a ‘0’ (conditional block550). If the bitcell is assigned to be programmed as a ‘0’ (conditional block550, “yes” leg), then the tool may connect the next net to VSS (block555). If the bitcell is assigned to be programmed as a ‘1’ (conditional block550, “no” leg), then the tool may connect the next net to the bitline (block560). It is noted that method500may be repeated for each net of the ROM bitcell array. It is also noted that method500may be utilized to connect the nets of ROM bitcell array400ofFIG. 4according to the programmed values shown at the bottom ofFIG. 4. It should be understood that there are many other different prior art approaches to programming a bitcell array, and that method500is merely one example of an approach to programming a bitcell array.

Referring now toFIG. 6, one embodiment of a method600for performing a first optimization to reduce the load on the bitlines of a ROM bitcell array is shown. For purposes of discussion, the steps in this embodiment are shown in sequential order. It should be noted that in various embodiments of the method described below, one or more of the elements described may be performed concurrently, in a different order than shown, or may be omitted entirely. Other additional elements may also be performed as desired. Any of the various apparatuses and/or systems described herein may be configured to implement method600.

In various embodiments, the number of nets connected to the bitline (BL) and the number of nets connected to VSS for each column of the ROM bitcell array (block605). For example, an apparatus such as a design tool, or ROM programming tool, may be used to count the number of nets. In one embodiment, the design tool may be a software tool executing on a computer system such as a desktop computer, workstation, cloud, or other computing device. Other design tools may have hardware specifically designed for performing design tasks. Any of a variety of hardware and/or software components are possible and are contemplated. The computer system may include one or more processors, memory devices, input/output devices, internal buses, communication interfaces, display devices, and/or other devices. If the number of nets connected to the bitline is greater than the number of nets connected to VSS for a given column (conditional block610, “yes” leg), then the design tool may swap the connections between the bitline and VSS for the given column (block615). If the number of nets connected to the bitline is less than or equal to the number of nets connected to VSS for a given column (conditional block610, “no” leg), then no change may be made for the given column (block620).

Referring now toFIG. 7, one embodiment of a method700for performing a second optimization to reduce the load on the bitlines of a ROM bitcell array is shown. For purposes of discussion, the steps in this embodiment are shown in sequential order. It should be noted that in various embodiments of the method described below, one or more of the elements described may be performed concurrently, in a different order than shown, or may be omitted entirely. Other additional elements may also be performed as desired. Any of the various apparatuses and/or systems described herein may be configured to implement method700.

Method700may start with a design tool, for example, determining if the net is connected to the bitline (BL) (conditional block705). If the net is connected to the bitline (conditional block705, “yes” leg), then the design tool may determine if this is the first net of a given column of the ROM bitcell array (conditional block710). If the net is not connected to the bitline (conditional block705, “no” leg), then the design tool may determine if all nets of the array have been considered for optimization (conditional block745). If all nets have been considered for optimization (conditional block745, “yes” leg), then the optimization may be done (block755). If there are one or more nets of the array that have not yet been considered for optimization (conditional block745, “no” leg), then another net may be selected for optimization (block750). In block750, the design tool may select the next net in the same column of the ROM bitcell array, or the design tool may select a net in another column of the array. After block750, method700may return to block705to determine if the selected net is connected to the bitline.

If this is the first net (conditional block710, “yes” leg), then the design tool may determine if the next net is connected to the bitline according to the original assignment of nets (conditional block715). If the next net is connected to the bitline (conditional block715, “yes” leg), then the design tool may remove the connection from the bitline (block720). If the next net is not connected to the bitline (conditional block715, “no” leg), then the design tool may determine if all nets of the array have been considered for optimization (conditional block745).

If this is not the first net (conditional block710, “no” leg), then the design tool may determine if the previous net is connected to the bitline according to the original assignment of nets (conditional block725). If the previous net is connected to the bitline (conditional block725, “yes” leg), then the design tool may determine if the next net is connected to the bitline according to the original assignment of nets (conditional block735). If the previous net is not connected to the bitline (conditional block725, “no” leg), then the design tool may determine if the previous net is connected to VSS according to the original assignment of nets (conditional block730). If the previous net is connected to VSS (conditional block730, “yes” leg), then the design tool may determine if all nets of the array have been considered for optimization (conditional block745). If the previous net is not connected to VSS (conditional block730, “no” leg), then the design tool may determine if the next net is connected to the bitline according to the original assignment of nets (conditional block735). If the next net is connected to the bitline (conditional block735, “yes” leg), then the design tool may remove the connection from the bitline (block720). If the next net is not connected to the bitline (conditional block735, “no” leg), then the design tool may determine if this is the last net of the given column of the ROM bitcell array (conditional block740).

If this is the last net (conditional block740, “yes” leg), then the design tool may remove the connection from the bitline (block720). If this is not the last net (conditional block740, “no” leg), then the design tool may determine if all nets of the array have been considered for optimization (conditional block745). In one embodiment, method700may be performed by a design tool after method600(ofFIG. 6) has been performed. Alternatively, method700may be performed by the design tool without method600being performed. In some embodiments, multiple instances of method700may be performed in parallel for a plurality of nets. For example, a software program may execute a plurality of threads simultaneously, and each thread of the plurality of threads may execute method700for a different net of the bitcell array.

Turning now toFIG. 8, a diagram of one embodiment of a ROM bitcell array800is shown. ROM bitcell array800illustrates an example of the current approach to connecting nets of the individual bitcells based on the values assigned to the bitcells as shown at the bottom of each column of ROM bitcell array800. A design tool may make an initial pass through ROM bitcell array800and connect the nets as shown inFIG. 8according to the values assigned to the bitcells.

ROM bitcell array800is identical to ROM bitcell array400ofFIG. 4. However, there is additional information shown at the bottom ofFIG. 8to illustrate the optimization techniques which may be utilized to reduce the load on the bitlines of ROM bitcell array800. At the bottom of each column, the number of nets connected to bitline and VSS is shown next to the corresponding bitline and VSS.

For example, column805has two nets connected to the bitline and six nets connected to VSS, column810has six nets connected to the bitline and two nets connected to VSS, column815has four nets connected to the bitline and four nets connected to VSS, column820has five nets connected to the bitline and three nets connected to VSS, and column825has eight nets connected to the bitline and zero nets connected to VSS.

ROM bitcell array800will be used as an example for illustrating how the optimizations described inFIGS. 6 and 7may be utilized to reduce the load on the bitlines of array800.

Referring now toFIG. 9, a diagram of one embodiment of a ROM bitcell array900is shown. ROM bitcell array900is meant to represent ROM bitcell array800(ofFIG. 8) after the optimization described inFIG. 6has been performed to reduce the number of connections to the bitlines of the array. The boxes930,935, and940at the bottom of columns910,920, and925, respectively, illustrate the reduction of the number of connections to the bitlines that was achieved in response to using method600ofFIG. 6.

In one embodiment, method600may be utilized to determine if reductions in the number of connections to the bitlines of ROM bitcell array900may be achieved. For columns905and915, the number of nets connected to VSS is greater than or equal to the number of nets connected to the bitline, so no changes have been made to these columns. However, for columns910,920, and925, the number of nets connected to the bitline is greater than the number of nets connected to VSS, and so the connections have been swapped for the nets of these columns. In other words, swapping the connections comprises reassigning a net to the bitline if it was previously assigned to VSS and reassigning a net to VSS if it was previously assigned to the bitline. The changes in the number of nets connected to the bitline and VSS are illustrated in boxes930,935, and940for columns910,920, and925, respectively.

For example, by swapping the connections to the bitline with the connections to VSS for column910, the connections to the bitline were reduced from six to two. For column920, the connections to the bitline were reduced from five to three by swapping the connections to the bitline with the connections to VSS. For column925, the connections to the bitline were reduced from eight to zero, as all previous connections from sources and drains to the bitline were replaced with connections to VSS. This is possible for column925because all of the bitcells are programmed with a value of ‘1’, and this can be achieved by connecting both the source and drain of each bitcell to VSS.

Turning now toFIG. 10, a diagram of one embodiment of a ROM bitcell array1000is shown. ROM bitcell array1000is meant to represent ROM bitcell array900(ofFIG. 9) after the optimization described inFIG. 7has been utilized to reduce the number of connections to the bitlines of the array. The boxes1030and1035at the bottom of columns1015and1020, respectively, illustrate the reduction of the number of bitline connections that was achieved using method700ofFIG. 7.

As shown inFIG. 10, the number of nets connected to the bitline in column1015was reduced from four to two using the optimization techniques described in method700ofFIG. 7. It is noted that this reduction was achieved while still maintaining the same programmed values on each of the bitcells of column1015of ROM bitcell array1000. Whereas the previous assignment of net connections had three consecutive nets connected to the bitline at the top of column1015, after the reassignment, the top two nets of column1015are left floating (i.e., unconnected or open). Alternatively, in another embodiment, the top two nets of column1015may be shorted together after the reassignment. Also, the number of nets connected to the bitline in column1020was reduced from three to one using the optimization techniques described in method700ofFIG. 7. The previous assignment of nets had three consecutive nets connected to the bitline at the bottom of column1020, but after the optimization, the bottom two nets of column1020are left floating.

Referring now toFIG. 11, one embodiment of a method1100for reducing the load on the bitlines of a ROM bitcell array is shown. For purposes of discussion, the steps in this embodiment are shown in sequential order. It should be noted that in various embodiments of the method described below, one or more of the elements described may be performed concurrently, in a different order than shown, or may be omitted entirely. Other additional elements may also be performed as desired. Any of the apparatuses and/or systems described herein may be configured to implement method1100.

A design tool may receive an initial layout of a ROM bitcell array (block1105). In one embodiment, the design tool may be software and/or hardware executing on an apparatus. The apparatus may include at least one or more processors coupled to one or more memory devices. In another embodiment, the design tool may be software and/or hardware executing on a system. The system may include at least one or more processors coupled to one or more memory devices. In one embodiment, the ROM bitcell array may be part of an integrated circuit design, wherein the integrated circuit includes a plurality of other components. When fabricated, the integrated circuit may be included in any of various types of devices (e.g., computing devices), apparatuses, and systems (e.g., computing systems, computers, servers, smartphones, tablets, watches).

The design tool may analyze the initial layout of the ROM bitcell array to determine if a first condition is detected for the ROM bitcell array (conditional block1110). In one embodiment, the first condition may comprise determining the number of nets connected to the bitline is greater than the number of nets connected to ground for a given column of the ROM bitcell array. In this embodiment, the design tool may analyze each column of the ROM bitcell array to determine if the first condition is detected for any of the columns of the ROM bitcell array. In other embodiments, the first condition may comprise other factors.

If the first condition is detected for the ROM bitcell array (conditional block1110, “yes” leg), then the design tool may perform a first optimization (block1115). In one embodiment, the first optimization may comprise swapping connections between bitline and ground for the given column. Swapping connections between bitline and ground for the given column may comprise moving connections from a bitline to ground, and moving connections from ground to the bitline. It is noted that the first optimization may be performed for each column of the ROM bitcell array for which the first condition was detected. In other embodiments, the first optimization may comprise one or more other steps.

If the first condition is not detected for the ROM bitcell array (conditional block1110, “no” leg), then the design tool may proceed to determine if a second condition is detected for the ROM bitcell array (conditional block1120). In one embodiment, the second condition may comprise detecting three consecutive nets of a given column are connected to the bitline. In another embodiment, the second condition may comprise detecting that two nets at an end of a given column are connected to the bitline. In these embodiments, the design tool may analyze each column of the ROM bitcell array to determine if the second condition is detected for any of the columns of the ROM bitcell array. In other embodiments, the second condition may comprise other factors.

If the second condition is detected for the ROM bitcell array (conditional block1120, “yes” leg), then the design tool may perform a second optimization (block1125). In one embodiment, the second optimization may comprise removing at least one connection to the bitline for the three consecutive nets connected to the bitline of the given column. In another embodiment, the second optimization may comprise removing a connection to the bitline for a net at the end of the given column. In other embodiments, the second optimization may comprise one or more other steps. If the second condition is not detected for the ROM bitcell array (conditional block1120, “no” leg), then method1100may end.

Turning now toFIG. 12, one embodiment of a method1200for programming a ROM bitcell array is shown. For purposes of discussion, the steps in this embodiment are shown in sequential order. It should be noted that in various embodiments of the method described below, one or more of the elements described may be performed concurrently, in a different order than shown, or may be omitted entirely. Other additional elements may also be performed as desired. Any of the apparatuses and/or systems described herein may be configured to implement method1200.

A design tool may receive data which is intended to be stored on a ROM bitcell array (block1205). Any amount of data may be received, depending on the embodiment. Next, the design tool may program the array with the received data using a current approach (e.g., the approach of method500ofFIG. 5) (block1210). In other embodiments, other current approaches (e.g., the approach of method1500ofFIG. 15) may be utilized to program the array in block1210. Next, the design tool may perform a first optimization (block1215). In one embodiment, the first optimization may be based on method600ofFIG. 6. Next, the design tool may perform a second optimization on the programmed array (block1220). In one embodiment, the second optimization may be based on method700ofFIG. 7. After block1220, method1200may end.

Referring now toFIG. 13, another embodiment of a method1300for designing a ROM bitcell array is shown. For purposes of discussion, the steps in this embodiment are shown in sequential order. It should be noted that in various embodiments of the method described below, one or more of the elements described may be performed concurrently, in a different order than shown, or may be omitted entirely. Other additional elements may also be performed as desired. Any of the apparatuses and/or systems described herein may be configured to implement method1300.

A design tool may receive data which is intended to be stored in a ROM bitcell array (block1305). Next the design tool may design the array with the received data using an integrated approach that combines the current approach with one or more optimization steps to reduce the load on the bitlines of the array (block1310). For example, in one embodiment, the design tool may combine the current approach with a first optimization step (e.g., method600ofFIG. 6) and a second optimization step (e.g., method700ofFIG. 7) in a single design stage for programming the array with the received data. After block1310, method1300may end.

Turning now toFIG. 14, one embodiment of a method1400for programming the first net of a bitcell array is shown. For purposes of discussion, the steps in this embodiment are shown in sequential order. It should be noted that in various embodiments of the method described below, one or more of the elements described may be performed concurrently, in a different order than shown, or may be omitted entirely. Other additional elements may also be performed as desired. Any of the apparatuses and/or systems described herein may be configured to implement method1400.

A design tool may connect the first net (either the source or the drain) of the first transistor to the bitline or VSS (block1405). Depending on the embodiment, the design tool may choose to connect the first net to either of the bitline or VSS. For example, in one embodiment, the design tool may be configured to connect the first net to the bitline. In another embodiment, the design tool may be configured to connect the first net to VSS.

Next, the design tool may determine the data for programming the first transistor (conditional block1410). If the data for programming the first transistor is a ‘0’ (conditional block1410, “yes” leg), then the design tool may connect the other end of the first transistor to the other wire (block1415). Accordingly, if the first net of the first transistor was connected to the bitline in block1405, then the other end of the first transistor may be connected to VSS in block1415. If the first net of the first transistor was connected to VSS in block1405, then the other end of the first transistor may be connected to the bitline in block1415.

If the data for programming the first transistor is a ‘1’ (conditional block1410, “no” leg), then the design tool may connect the other end of the first transistor to the same wire (block1420). Accordingly, if the first net of the first transistor was connected to the bitline in block1405, then the other end of the first transistor may be connected to the bitline in block1420. If the first net of the first transistor was connected to VSS in block1405, then the other end of the first transistor may be connected to VSS in block1420.

It is noted that method1400shows a variation on the current approach shown in method500ofFIG. 5. The first net may be connected to the bitline or VSS, and then subsequent blocks may be altered depending on which choice was made for the first net. This is a different approach from block545of method500where the first net was connected to the bitline. It should be understood that different types of current approaches may be utilized with the optimizations described herein.

Referring now toFIG. 15, another embodiment of a method1500for determining how to program a bitcell array is shown. For purposes of discussion, the steps in this embodiment are shown in sequential order. It should be noted that in various embodiments of the method described below, one or more of the elements described may be performed concurrently, in a different order than shown, or may be omitted entirely. Other additional elements may also be performed as desired. Any of the various devices, apparatuses, and/or systems described herein may be configured to implement method1500.

Method1500is intended to represent a variation on the method500(ofFIG. 5) for programming a bitcell array. The blocks of method1500that are different from method500are shown with a dashed border. These blocks are blocks1545,1555, and1560. The other blocks of method1500may be performed in the same manner as their respective blocks in method500. Accordingly, blocks1505,1510,1515,1520,1525,1530,1535,1540, and1550may be performed in the same manner as blocks505,510,515,520,525,530,535,540, and550, respectively, of method500.

In block1545, the design tool may connect the net to VSS responsive to determining the net is the first net of the column in conditional block1505. This is a different approach from method500, wherein in block545, the design tool connected the net to the bitline responsive to determining the net is the first net of the column in conditional block505. In block1555, the design tool may connect the next net to the bitline responsive to determining the bitcell is being programmed with a ‘0’ in conditional block1550. In block1560, the design tool may connect the next net to VSS responsive to determining the bitcell is being programmed with a ‘1’ in conditional block1550.

It is noted that in some embodiments, methods1200(ofFIG. 12) and1300(ofFIG. 13) may utilize method1500as the current approach for programming the bitcell array in blocks1210and1310, respectively. Then, after performing method1500, one or more optimization steps may be performed to reduce the load on the bitlines of the bitcell array.

Turning now toFIG. 16, diagrams of four columns storing the same data are shown. After the second optimization has been performed, any of the bitcell connections shown in diagrams of200and205ofFIG. 2may be utilized to program a bitcell with a value of ‘0’ to change one or more existing connections. Additionally, after the second optimization has been performed, any of the bitcell connections shown in diagrams of300-325ofFIG. 3may be utilized to program a bitcell with a value of ‘1’ to change one or more existing connections. It should be understood that these value designations may be reversed in another embodiment, such that the bitcell connections of diagrams200-205may be utilized to program a bitcell with a value of ‘1’ and the bitcell connections of diagrams300-305may be utilized to program a bitcell with a value of ‘0’.

Examples of different ways of programming a column of bitcells with the same data values using different connections are shown inFIG. 16. In column1605, there is one net connected to the bitline and five nets connected to VSS to program the column with the values “1111011” as shown at the bottom of the column. Column1610illustrates a second way of programming a column with the values “1111011”, with column1610having one net connected to the bitline and two nets connected to VSS. Column1615also has one net connected to the bitline and two nets connected to VSS, with the final two nets shorted to each other rather than left floating as in column1610. The fifth bitcell of column1620has the VSS and the bitline connections reversed as compared to the fifth bitcell of column1610. Otherwise, the other nets of column1620are connected in the same manner as the corresponding nets of column1610.

In various embodiments, program instructions of a software application may be used to implement the methods and/or mechanisms previously described. The program instructions may describe the behavior of hardware in a high-level programming language, such as C. Alternatively, a hardware design language (HDL) may be used, such as Verilog. The program instructions may be stored on a non-transitory computer readable storage medium. Numerous types of storage media are available. The storage medium may be accessible by a computer during use to provide the program instructions and accompanying data to the computer for program execution. In some embodiments, a synthesis tool reads the program instructions in order to produce a netlist comprising a list of gates from a synthesis library.