Using split word lines and switches for reducing capacitive loading on a memory system

Systems and methods disclosed herein are related to a memory system. In one aspect, the memory system includes a first set of memory cells including a first string of memory cells and a second string of memory cells; and a first switch including: a first electrode connected to first electrodes of the first string of memory cells and first electrodes of the second string of memory cells, and a second electrode connected to a first global bit line, wherein gate electrodes of the first string of memory cells are connected to a first word line and gate electrodes of the second string of memory cells are connected to a second word line.

TECHNICAL FIELD

The disclosure relates generally to high density memory devices, and more particularly, to memory devices in which multiple planes of memory cells are arranged to provide a three-dimensional (3D) array including split word lines (WL) and/or switches to reduce bit line (BL) capacitance.

BACKGROUND

Developments in electronic devices, such as computers, portable devices, smart phones, internet of thing (IoT) devices, etc., have prompted increased demands for memory devices. In general, memory devices may be volatile memory devices and non-volatile memory devices. Volatile memory devices can store data while power is provided but may lose the stored data once the power is shut off. Unlike volatile memory devices, non-volatile memory devices may retain data even after the power is shut off but may be slower than the volatile memory devices.

SUMMARY

DETAILED DESCRIPTION

In accordance with some embodiments, a memory system includes one or more switches (sometimes referred to as, “select gates”) to couple or decouple local lines to a global line. A local line may be a metal rail, to which two or more memory cells are connected. For example, a local line may be a local select line (e.g., LSL[00] or LSL[10] inFIG. 3A), to which first electrodes (e.g., drain (or source) electrodes) of memory cells are connected. For example, a local line may be a local bit line (e.g., LBL[00] or LBL[10] inFIG. 3A), to which second electrodes (e.g., source (or drain) electrodes) of the memory cells are connected. A global line may be a metal rail, to which one or more of selected local lines can be electrically coupled through switches. For example, a global line may be a global select line (e.g., GSL[0] inFIG. 3A), to which two or more local select lines can be electrically coupled through switches. For example, a global line may be a global bit line (e.g., GBL[0] inFIG. 3A), to which two or more local bit lines can be electrically coupled through switches.

Advantageously, the memory system employing the disclosed switches can achieve several benefits. In one aspect, switches between a global line and local lines can be individually configured or operated to electrically couple or decouple respective local lines to the global line. By coupling a selected local line to a global line, a subset of a set of memory cells connected to the selected local line can be electrically coupled to the global line while the other subset of the set of memory cells connected to unselected local lines can be electrically decoupled from the global line. Hence, the global line may have a capacitive loading corresponding to the selected subset of the set of memory cells instead of a capacitive loading corresponding to the entire set of memory cells. Accordingly, the set of memory cells having many memory cells can be configured or operated through a global line with a low capacitive loading corresponding to the subset of the set of memory cells.

In another aspect, each word line in a memory array may be split into two word lines (e.g., a first word line and a second word line) to further reduce the capacitive loading on a controller during read and/or write operations. By splitting a word line, half of the memory cells in a subset of memory cells (e.g., subset310inFIG. 3A) are coupled to the first word line, while the other half is coupled to second word line.

By reducing the capacitive loading, operating speed of the memory system can be improved, which in turn, reduces the power consumption of the memory system. Moreover, the techniques and/or features of the present disclosure may also improve routing and shielding.

1. Memory Architecture

FIG. 1is a diagram of a memory system100, in accordance with an embodiment of the present disclosure. In some embodiments, the memory system100is implemented as an integrated circuit. In some embodiments, the memory system100includes a memory controller105and a memory array120. The memory array120may include a plurality of storage circuits or memory cells125arranged in two- or three-dimensional arrays. Each memory cell125may be connected to a corresponding gate line GL and a corresponding bit line BL. Each gate line GL may include any conductive material. The memory controller105may write data to or read data from the memory array120according to electrical signals through gate lines GL and bit lines BL. In other embodiments, the memory system100includes more, fewer, or different components than shown inFIG. 1.

The memory array120is a hardware component that stores data. In one aspect, the memory array120is embodied as a semiconductor memory device. The memory array120includes a plurality of storage circuits or memory cells125. In some embodiments, the memory array120includes gate lines GL0, GL1. . . GLJ, each extending in a first direction and bit lines BL0, BL1. . . BLK, each extending in a second direction. The gate lines GL and the bit lines BL may be conductive metals or conductive rails. Each gate line GL may include a word line and control lines. In one aspect, each memory cell125is connected to a corresponding gate line GL and a corresponding bit line BL, and can be operated according to voltages or currents through the corresponding gate line GL and the corresponding bit line BL. In one aspect, each memory cell125may be a non-volatile memory cell. In some embodiments, the memory array120includes additional lines (e.g., sense lines, reference lines, reference control lines, power rails, etc.).

The memory controller105is a hardware component that controls operations of the memory array120. In some embodiments, the memory controller105includes a bit line controller112, a gate line controller114, and a timing controller110. In one configuration, the gate line controller114is a circuit that provides a voltage or a current through one or more gate lines GL of the memory array120. In one aspect, the bit line controller112is a circuit that provides a voltage or current through one or more bit lines BL of the memory array120and senses a voltage or current from the memory array120through one or more sense lines. In one configuration, the timing controller110is a circuit that provides control signals or clock signals to the gate line controller114and the bit line controller112to synchronize operations of the bit line controller112and the gate line controller114. The bit line controller112may be connected to bit lines BL and sense lines of the memory array120, and the gate line controller114may be connected to gate lines GL of the memory array120. In one example, to write data to a memory cell125, the gate line controller114applies a voltage or current to the memory cell125through a gate line GL connected to the memory cell125, and the bit line controller112applies a voltage or current corresponding to data to be stored to the memory cell125through a bit line BL connected to the memory cell125. In one example, to read data from a memory cell125, the gate line controller114applies a voltage or a current to the memory cell125through a gate line GL connected to the memory cell125, and the bit line controller112senses a voltage or current corresponding to data stored by the memory cell125through a sense line or a bit line connected to the memory cell125. In some embodiments, the memory controller105includes more, fewer, or different components than shown inFIG. 1.

FIG. 2is a diagram showing three-dimensional memory arrays210A . . .210N, in accordance with one embodiment. In some embodiments, the memory array120includes the memory arrays210A . . .210N. Each memory array210includes a plurality of memory cells125arranged in a three-dimensional array. In some embodiments, each memory array210may include a same number of memory cells125. In some embodiments, two or more memory arrays210may include different numbers of memory cells125. In one configuration, the memory arrays210A . . .210N are stacked along a Z-direction. Each memory array210may have bit lines BL on one side of the memory array210and have select lines SL on an opposite side of the memory array210. In some embodiments, two adjacent memory arrays210may share select lines SL. In some embodiments, two adjacent memory arrays210may share bit lines BL. For example, memory arrays210N-1,210N share or are electrically coupled to a set of select lines SL. For example, memory arrays210N-2,210N-1share or are electrically coupled to a set of bit line BL. By sharing select lines SL and/or bit lines BL, a number of drivers of the memory controller105to apply signals through the select lines SL and/or bit lines BL can be reduced to achieve area efficiency. In some embodiments, the memory array120includes additional memory arrays that may have separate select lines SL and/or bit lines BL than shown inFIG. 2.

2. Memory System(s) with Switches and/or Split Word Lines

FIG. 3Ais a diagram showing a portion of a three-dimensional memory array210including switches SS, SB arranged on the bottom-side and split word lines for reducing capacitive loading, in accordance with one embodiment. InFIG. 3A, the memory array210includes a first set of memory cells and a second set of memory cells. In one configuration, the first set of memory cells includes subsets310[00] . . .310[03] of memory cells that may be electrically coupled to a global bit line GBL[0] and a global select line GSL[0] extending along a Y-direction. In one configuration, the second set of memory cells includes subsets310[10] . . .310[13] of memory cells that may be electrically coupled to a global bit line GBL[1] and a global select line GSL[1] extending along the Y-direction. Each subset310of memory cells may include F number of memory cells M (memory cell125) disposed along a Z-direction, where F also corresponds to a total number of floors or layers in the memory array210. Each set of memory cells may include a larger number of subsets310of memory cells than shown inFIG. 3Aalong the Y-direction. The memory array210may include a larger number of sets of memory cells than shown inFIG. 3Astacked along the X-direction. By arranging memory cells as shown inFIG. 3A, a storage density of the memory array210can be increased.

In one configuration, one or more memory cells of a subset310may be positioned on the left side of the subset310and the other memory cells of the subset310may be positioned on the right side of the subset310. In one configuration, a subset310may include a first vertical string of memory cells disposed along a Z-direction and a second vertical string of memory cells disposed along the Z-direction, where the first vertical string and the second vertical string are in parallel with one another. Each memory cell may be identified (e.g., indexed, referenced, labeled, etc.) according to its position in a subset310and its X-Y-Z position in the memory array210. For example, as shown inFIG. 3A, subset310[00] includes M [0][0][0]_L, M [0][0][0]_R, M [0][0][1]_L, M [0][0][1]_R, M [0][0][F-2]_L, M [0][0][F-2]_R, M [0][0][F]_L, and M [0][0][F]_R; and subset310[10] includes M [1][0][0]_L, M [1][0][0]_R, M [1][0][1]_L, M [1][0][1]_R, M [1][0][F-2]_L, M [1][0][F-2]_R, M [1][0][F]_L, and M [1][0][F]_R.

Each memory cell M may be a volatile memory cell, a non-volatile memory cell, or any memory cell that can store data. Each memory cell M may be embodied as a transistor, such as a metal-oxide-semiconductor field effect transistor (MOSFET), a gate-all-around FET (GAAFET), or a fin field-effect transistor (FinFET). Each memory cell M may include a first electrode (e.g., drain electrode) coupled to a local select line LSL[X][Y], a second electrode (e.g., source electrode) coupled to a local bit line LBL[X][Y], and a third electrode (e.g., gate electrode) coupled to a corresponding split word line (e.g., WL[X][Z]_L or word line WL[X][Z]_R). Each memory cell M may store data or conduct current according to a voltage applied to a gate electrode of the memory cell M.

In one configuration, a subset310of memory cells M are connected in parallel between a local select line LSL and a local bit line LBL. A local select line LSL may be a metal rail, at which first electrodes (e.g., drain electrodes) of a subset310memory cells are connected. A local bit line LBL may be a metal rail, at which second electrodes (e.g., source electrodes) of a subset310memory cells are connected. The local select line LSL may extend along the Z-direction and connect to a corresponding switch SS. Similarly, the local bit line LBL may extend along the Z-direction in parallel with the local bit line LBL and connect to a corresponding switch SB.

A word line WL[X][Y] may be split (e.g., divided, partitioned, separated, etc.) into a WL[X][Y]_L (left) and a WL[X][Y]_R (right) and extended along the X-direction to connect gate electrodes of corresponding memory cells M in different sets to the memory controller (e.g., gate line controller114). In one configuration, a WL[X][Y]_L connects to the gate electrodes of memory cells M that are positioned on the left side of a subset310and a WL[X][Y]_R connects to the gate electrodes of memory cells M that are positioned on the right side of a subset310. In one configuration, a WL[X][Y]_L connects to the gate electrodes of memory cells M that are positioned on the left side of a plurality of subsets (e.g., subset310[00],310[10]), and a WL[X][Y]_R connects to the gate electrodes of memory cells M that are positioned on the right side of a plurality of subsets (e.g., subset310[00],310[10]). In one configuration, a word line WL[X][Y] is split into two words lines (e.g., WL[X][Y]_L and WL[X][Y]_R) that are respectively dedicated to a memory cell M (left or right) from each subset310along the X-direction of the memory array210.

For example, as shown inFIG. 3A, WL[0][0]_L connects to the gate electrode of M[0][0][0]_L (e.g., an M cell that is positioned on the left side of subset310[00]) and the gate electrode of M[1][0][0]_L (e.g., an M cell that is positioned on the left side of subset310[10]); WL[0][0]_R connects to the gate electrode of M[0][0][0]_R (e.g., an M cell that is positioned on the right side of subset310[00]) and the gate electrode of M[1][0][0]_R (e.g., an M cell that is positioned on the right side of subset310[10]); WL[0][1]_L connects to the gate electrode of M[0][0][1]_L and the gate electrode of M[1][0][1]_L; WL[0][1]_R connects to the gate electrode of M[0][0][1]_R and the gate electrode of M[1][0][1]_R; WL[0][F-2]_L connects to the gate electrode of M[0][0][F-2]_L and the gate electrode of M[1][0][F-2]_L; WL[0][F-2]_R connects to the gate electrode of M[0][0][F-2]_R and the gate electrode of M[1][0][F-2]_R; WL[0][F-1]_L connects to the gate electrode of M[0][0][F-1]_L and the gate electrode of M[1][0][F-1]_L; WL[0][F-1]_R connects to the gate electrode of M[0][0][F-1]_R and the gate electrode of M[1][0][F-1]_R.

In one configuration, although not shown inFIG. 3A, the connections of WL[X][Y]_L and WL[X][Y]_R may be reversed in that a WL[X][Y]_L connects to the gate electrodes of memory cells M that are positioned on the right side of a plurality of subsets (e.g., subset310[00],310[10]), and a WL[X][Y]_R connects to the gate electrodes of memory cells M that are positioned on the left side of a plurality of subsets (e.g., subset310[00],310[10]). For example, WL[0][0]_L connects to the gate electrode of M[0][0][0]_R (e.g., an M cell that is positioned on the right side of subset310[00]) and the gate electrode of M[1][0][0]_R (e.g., an M cell that is positioned on the right side of subset310[10]); WL[0][0]_R connects to the gate electrode of M[0][0][0]_L (e.g., an M cell that is positioned on the left side of subset310[00]) and the gate electrode of M[1][0][0]_L (e.g., an M cell that is positioned on the left side of subset310[10]), etc.

Splitting a word line WL[X][Y] into two words lines (e.g., WL[X][Y]_L and WL[X][Y]_R) may reduce the capacitive loading on a bit line (e.g., LBL[X][Y] or GBL[X][Y]), thereby allowing a memory array210to maintain the large cell bit count that may be needed for various memory applications (e.g., storage) and without additional processing cost.

Each switch SB may be embodied as a transistor (e.g., MOSFET, GAAFET, FinFET, etc.). Each switch SB may include a first electrode (e.g., drain electrode) connected to the local bit line LBL, a second electrode (e.g., source electrode) connected to a corresponding global bit line GBL, and a third electrode (e.g., gate electrode) connected to a corresponding switch control line SBL (sometimes referred to as, “select gate left” or “SG[X]_L”). The switch control line SBL may be a metal rail extending along the X-direction to connect the memory controller105(e.g., gate line controller114) to the gate electrodes of switches SB. According to a voltage or a signal applied through the switch control line SBL, one or more switches SB connected to the switch control line SBL may be toggled (e.g., enabled or disabled). For example, in response to a voltage corresponding to logic state ‘1’ provided through the switch control line SBL, a switch SB may be enabled to electrically couple (e.g., connect, engage, etc.) second electrodes (e.g., source electrodes) of the subset310of memory cells to the global bit line GBL. For example, in response to a voltage corresponding to logic state ‘0’ provided through the switch control line SBL, the switch SB may be disabled to electrically decouple (e.g., disconnect, disengage, etc.) second electrodes (e.g., source electrodes) of the subset310of memory cells from the global bit line GBL.

Each switch SS may be embodied as a transistor (e.g., MOSFET, GAAFET, FinFET, etc.). The switch SS may include a first electrode (e.g., source electrode) connected to the local select line LSL, a second electrode (e.g., drain electrode) connected to a corresponding global select line GSL, and a third electrode (e.g., gate electrode) connected to a corresponding switch control line SSL (sometimes referred to as, “select gate right” or “SG[X]_R”). The switch control line SSL may be a metal rail extending along the X-direction to connect the memory controller105(e.g., gate line controller114) to the gate electrodes of switches SS. According to a voltage or a signal applied through the switch control line SSL, one or more switches SS connected to the switch control line SSL may be enabled or disabled. For example, in response to a voltage corresponding to logic state ‘1’ provided through a switch control line SSL, the switch SS may be enabled to electrically couple first electrodes (e.g., drain electrodes) of the subset310of memory cells to the global select line GSL. For example, in response to a voltage corresponding to logic state ‘0’ provided through the switch control line SSL, the switch SS may be disabled to electrically decouple first electrodes (e.g., drain electrodes) of the subset310of memory cells from the global select line GSL.

In one configuration, the global select line GSL is a metal rail, at which corresponding switches SS are connected. The global select line GSL may extend along the Y-direction. In one implementation, the global select line GSL may be connected to a memory controller105(e.g., bit line controller112). The global bit line GBL may be a metal rail, at which corresponding switches SB are connected. The global bit line GBL may extend along the Y-direction in parallel with the global select line GSL. In one implementation, the global bit line GBL may be connected to the memory controller105(e.g., bit line controller112).

Switches SB, SS are positioned on the same side of the memory array210to reduce processing cost and/or processing complexity. For example, as shown inFIG. 3A, switches SB, SS are positioned and/or arranged on the bottom-side of memory array210. In one configuration, switches SB, SS may be positioned on the top-side of memory array210. For example,FIG. 3Bis a diagram showing a portion of a three-dimensional memory array210including switches SS, SB arranged on the top-side and split word lines for reducing capacitive loading, in accordance with one embodiment.

Referring back toFIG. 3A, in one configuration, the switches SB, SS can be operated or configured according to a voltage or signal from the memory controller105(e.g., gate line controller114) to electrically couple (sometimes referred to as a, “coupling method”) a subset310of memory cells to corresponding global lines BL, SL selectively. For example, from a set310[X0] . . .310[X3] of memory cells connected to local select lines LSL[X0] . . . LSL[X3] and local bit lines LBL[X0] . . . LBL[X3], a subset310[XY] of memory cells connected to a local select line LSL[XY] and a local bit line LBL[XY] can be electrically coupled to the global bit line GBL[X] and the global select line GSL[X] through selected switches SB, SS. Meanwhile, other subsets310of memory cells connected to other local select lines LSL and local bit lines LBL can be electrically decoupled (sometimes referred to as a, “decoupling method”) from the global bit line GBL[X] and the global select line GSL[X]. By electrically coupling a selected subset310[XY] of memory cells to the global bit line GBL[X] and the global select line GSL[X] through the switches SB, SS, the global bit line GBL[X] and the global select line GSL[X] may have a capacitive loading corresponding to the selected subset310[XY] of memory cells instead of the set310[X1] . . .310[X3] (e.g., a plurality or all) of memory cells. Accordingly, the global bit lines GBL[X] and the global select lines GSL[X] may be implemented to provide voltages or current, without increased capacitive loading.

A split word line allows the controller105to access (e.g., read, write, program) a single vertical string of a memory cells in subset310without having to access all the vertical strings of memory cells in the subset310. For example, subset310[00] may include a first vertical string of memory cells (e.g., M[0][0][0]_L, M[0][1][0]_L, M[0][F-2][0]_L, M[0][F-1][0]_L) that are disposed along the Z-direction, where each memory cell M of the first vertical string has its gate electrode coupled to a corresponding word line WL[X][Z]_L (left); and a second vertical string of memory cells (e.g., M[0][0][0]_R, M[0][1][0]_R, M[0][F-2][0]_R, M[0][F-1][0]_R) disposed along the Z-direction, where each memory cell M of the second vertical string has its gate electrode coupled to a corresponding word line WL[X][Z]_R (right). In this configuration, the memory controller105can (1) select the subset310[00] of memory cells via the switches SB, SS using the “coupling” method as discussed herein, and (2) deselect the other subsets310of memory cells via switches SB, SS using the “decoupling method” as discussed herein. In response to selecting/deselecting the subsets310of memory cells, the controller105can access the first vertical string of memory cells using via word lines WL[X][Y]_L (left) without having to also access the second vertical string of memory cells in the subset310. Accordingly, splitting a word line WL[X][Y] into two words lines (e.g., WL[X][Y]_L and WL[X][Y]_R) may further help to reduce the capacitive loading on a word line WL[X][Y], thereby allowing the controller105and/or memory cells M to be operated or configured with improved speed and/or lower power consumption.

In some embodiments, the memory array210includes either one of the switches SB, SS, but may lack the other of the switches SB, SS. For example, the memory array210includes the switches SB as shown inFIG. 3A, where the switches SS are omitted and local select lines LSL [X0], [X1], [X2], [X3] are connected to corresponding global select lines SL[X]. For example, the memory array210includes the switches SS as shown inFIG. 3A, where the switches SB are omitted and local bit lines LBL [X0], [X1], [X2], [X3] are connected to corresponding global bit lines GBL[X]. The switches SS or SB can be configured or operated to electrically couple or decouple the subset310of memory cells to a corresponding global line selectively. In some embodiments, the memory array210may include split word lines WL and either one of the switches SB, SS, but may lack the other of the switches SB, SS.

In one configuration, the gate electrode of a switch SB of a subset310of memory cells may be electrically coupled to the gate electrode of the corresponding switch SS. In other words, the switch SB and/or its respective functionality may be merged with the switch SS and/or its respective functionality. For example,FIG. 4Ais a diagram showing a portion of a three-dimensional memory array210including switches SS, SB arranged on the bottom-side, split word lines, and merged switches SB, SS for reducing capacitive loading, in accordance with one embodiment. As another example,FIG. 4Bis a diagram showing a portion of a three-dimensional memory array210including switches SS, SB arranged on the top-side, split word lines, and merged switches SB, SS for reducing capacitive loading, in accordance with one embodiment. As shown inFIGS. 4A and 4B, when the gate electrodes of the switches SB, SS are electrically coupled together (merged), then the corresponding switch control lines SSL[Y], SBL[Y] may be merged into a single control line (shown inFIG. 4Bas, switch merged control line or SML[0]) that is connected to a single driver. Accordingly, the switches SB, SS connected to the SML[0] can be simultaneously (or nearly simultaneously) enabled or disabled according to a voltage, current, or pulse from the driver. By implementing the same (single) driver to configure or operate the switches SB, SS, several drivers can be reduced to achieve area efficiency.

In some embodiments, the M cells and switches SB,SS in the memory array210depicted in any ofFIG. 3A,FIG. 3B,FIG. 4A,FIG. 4Bmay be embodied as P-type metal-oxide-semiconductor field effect transistors (PMOS). In some embodiments, the M cells and switches SB,SS in the memory array210depicted in any ofFIG. 3A,FIG. 3B,FIG. 4A,FIG. 4Bmay be embodied as N-type metal-oxide-semiconductor field effect transistors (NMOS).

FIG. 5is a diagram showing drivers to drive one or more switches, in accordance with an embodiment of the present disclosure. The diagram500includes drivers DS[0], DB[0], DS[1], DB[1], DW[0]_L . . . DW[F-1]_L, and DW[0]_R . . . DW[F-1]_R. The drivers DS[0], DB[0], DS[1], DB[1], DW[0]_L . . . DW[F-1]_L, and DW[0]_R . . . DW[F-1]_R may be part of the gate line controller114. In one aspect, the drivers DS[0], DB[0], DS[1], DB[1], DW[0]_L . . . DW[F-1]_L, and/or DW[0]_R . . . DW[F-1]_R are connected to two or more switches or two or more memory cells to achieve area efficiency.

In one configuration, the gate electrode of the switch SS connected to a subset310[01] of memory cells is connected to an output of a driver DS[1] through switch control line SSL[1]. In one configuration, the gate electrode of the switch SS connected to a subset310[00] of memory cells is connected to an output of a driver DS[0] through switch control lines SSL[0]. In one configuration, the gate electrode of the switch SB connected to a subset310[01] of memory cells is connected to an output of a driver DB[1] through switch control line SBL[1]. In one configuration, the gate electrode of the switch SB connected to a subset310[00] of memory cells is connected to an output of a driver DB[0] through switch control lines SBL[0].

In one configuration, a gate electrode of each memory cell in the subset310[00] of memory cells and a gate electrode of a corresponding memory cell in the subset310[01] of memory cells are connected to an output of a driver DW[X]_L or DW[X]_R through word lines WL. For example, a gate electrode of a first memory cell that is positioned on the left side in the subset310[00] of memory cells and a gate electrode of a first memory cell that is positioned on the left side in the subset310[01] of memory cells are connected to an output of the driver DW[0]_L through word lines WL[0][0]_L, WL[1][0]_L. As another example, a gate electrode of a first memory cell that is positioned on the right side in the subset310[00] of memory cells and a gate electrode of a first memory cell that is positioned on the right side in the subset310[01] of memory cells are connected to an output of the driver DW[0]_R through word lines WL[0][0]_R, WL[1][0]_R. As another example, a gate electrode of a Fth memory cell that is positioned on the left side in the subset310[00] of memory cells and a gate electrode of a Fth memory cell that is positioned on the left side in the subset310[01] of memory cells are connected to an output of the driver DW[F-1]_L through word lines WL[0][F-1]_L, WL[1][F-1]_L. As another example, a gate electrode of a Fth memory cell that is positioned on the right side in the subset310[00] of memory cells and a gate electrode of a Fth memory cell that is positioned on the right side in the subset310[01] of memory cells are connected to an output of the driver DW[F-1]_R through word lines WL[0][F-1]_R, WL[1][F-1]_R. Although two subsets310[01],310[00] of memory cells are shown inFIG. 5, the output of each driver (e.g., DW_L and/or DW_R) may be connected to additional memory cells in other subsets (e.g.,310[02],310[03]) through word lines.

Without implementing the disclosed switches SS, SB and sharing drivers (e.g., DS, DB, DW_L, and/or DW_R), a number of drivers may correspond to a number of total memory cells in a set of memory cells. By sharing a driver (e.g., DS, DB, DW_L, and/or DW_R) to drive multiple memory cells in different subsets310of memory cells, several drivers can be reduced to achieve area efficiency. Hence, 68% of area reduction can be achieved by sharing drivers.

FIG. 6is a timing diagram600showing pulses P1, P2, P3, P4for operating the memory array120, in accordance with one embodiment. In some embodiments, the pulses P1, P2, P3, P4are generated by the memory controller105(e.g., gate line controller114).

In one approach, the pulse P1is applied to gate electrodes of switches SS, SB connected to a selected subset310of memory cells, and the pulse P3is applied to gate electrodes of switches SS, SB connected to unselected subsets310of memory cells. By applying the pulse P1having a high voltage610, the switches SS, SB connected to the selected subset310of memory cells can be enabled to electrically couple the selected subset310of memory cells to the global select line GSL and the global bit line GBL. Meanwhile, by applying the pulse P3having a low voltage630, the switches SS, SB connected to the unselected subsets310of memory cells can be disabled to electrically decouple the unselected subset310of memory cells from the global select line GSL and the global bit line GBL. Accordingly, the global select line GSL and the global bit line GBL may have a capacitive loading corresponding to the selected subset of memory cells, rather than the entire set of memory cells.

In one approach, the pulse P2is applied to a gate electrode or a word line WL of a selected memory cell, and the pulse P4is applied to gate electrodes or word lines WL of unselected memory cells. For example, P2may be applied to WL[X][Z]_L when a first vertical string (e.g., leftmost) of a subset310is selected and P4may be applied to WL[X][Z]_R when a second vertical string (e.g., rightmost) of a subset310is deselected. As another example, P2may be applied to WL[X][Z]_R when a second vertical string (e.g., rightmost) of a subset310is selected and P4may be applied to WL[X][Z]_L when a first vertical string (e.g., leftmost) of a subset310is deselected.

In some embodiments, P1may have a pulse-width (e.g., an elapsed time between the rising edge and falling edge of a pulse) that is wider than the pulse-width of P2. In some embodiments, P1may have a pulse-width (e.g., an elapsed time between the rising edge and falling edge of P1) that is shorter than the pulse-width of P2. In one embodiment, P1may have a pulse-width (e.g., an elapsed time between the rising edge and falling edge of P1) that is the same as the pulse-width of P2.

In some embodiments, the rising edge and/or falling edge of P1may be coincident with the rising edge and/or falling edge of P2. In some embodiments, the rising edge and/or falling edge of P1may be delayed with respect to the corresponding rising edge and/or corresponding falling edge of P2. In some embodiments, the rising edge and/or falling edge of P1may be advanced with respect to the corresponding rising edge and/or corresponding falling edge of P2.

By applying the pulse P2having a high voltage620, the selected memory cell may be programmed or conduct current corresponding to programmed data. Meanwhile, by applying the pulse P4having a low voltage640, the unselected memory cells can be disabled from being programmed or conducting current. Accordingly, the selected memory cell from a subset310of memory cells can be individually programmed or operated.

FIG. 7is a graph700showing effects of reduced capacitive loading due to switches SS, SB, in accordance with one embodiment. F may indicate several memory cells in a subset of memory cells along the Z-direction. S may indicate several sets of memory cells along the X-direction (or a number of global select lines GSL). In one aspect, without implementing the disclosed switches SS, SB and/or split word lines, capacitive loading at global lines may increase according to a number of subsets of memory cells, as shown in cases710. For example, without the disclosed switches SS, SB and/or split word lines, the global lines may have a high capacitance loading, if a memory array210includes 64 number of subsets of memory cells. By implementing the switches SW (e.g., SS, SB) and/or split word lines, capacitive loadings at global lines may not increase despite the increased number of subsets of memory cells, as shown in cases720. For example, a global line may have a capacitive loading corresponding to a selected subset310of memory cells by enabling switches SS, SB connected to the selected subset310of memory cells and disabling switches SS, SB connected to the unselected subsets310of memory cells. Accordingly, the increased number of subsets of memory cells may not affect the capacitive loading at the global lines.

FIG. 8Ais a diagram showing an example implementation of a memory array having GSL/GBL connections and single-side switches SS, SB, in accordance with one embodiment. As shown inFIG. 8A, a memory array800A includes a structure802A (e.g., S/BL connect) implemented for a global bit line GBL connection. The memory array800A includes a structure804A (e.g., S/BL connect) implemented for a global select line GSL connection. The memory array800A may also include a structure806A (e.g., SL/BL) implemented for a switch (SS, SB), such as a transistor channel. As shown, the switches are positioned on the bottom-side of the memory array800A. The memory array800A may also include a structure808A (e.g., inter connect) implemented for a non-split word line. The memory array800A may also include a structure810A (e.g., WL) implemented for a bit cell, such as a transistor. The memory array800A may also include a structure820A corresponding to a ferroelectric (FE) film. The memory array800A may also include a structure822A corresponding to oxide (e.g., SiO2). The memory array800A may also include a structure824A implemented for a channel. In this configuration, the memory array800A may have a cell count corresponding to the following equation:
Cell count=Row Count*1/2*Column Count*Floor Count  (1)

; where a Row Count corresponds to the number of rows (y-direction) in the memory array, a Column Count corresponds to the number of columns (x-direction) in the memory array, and a Floor Count corresponds to the number of floors (z-direction) in the memory array.

In some embodiments, WL is defined as a word-line for Vg. In some embodiments, the size of a WL in the z-direction may be 20 nanometers to 120 nanometers. In some embodiments, S/BL is defined as a source-line/bit-line for a first power rail (e.g., VDD) and a second power rail (e.g., ground). In some embodiments, OX is defined as oxide for isolation. In some embodiments, FE is defined as ferroelectric film of memory. In some embodiments, an FE has a thickness of 5 nanometers to 30 nanometers. In some embodiments, a channel corresponds to a channel film of memory. In some embodiments, a channel may have a thickness of 5 nanometers to 30 nanometers. In some embodiments, S/BL corresponds to an interconnect.

FIG. 8Bis a diagram showing an example implementation of a memory array having GSL/GBL connections and single-side switches SS, SB, in accordance with one embodiment. As shown inFIG. 8B, a memory array800B includes a structure802B implemented for a global bit line GBL connection. The memory array800B includes a structure804B implemented for a global select line GSL connection. The memory array800B may also include a structure806B implemented for a switch (SS, SB), such as a transistor channel. As shown, the switches are positioned on the bottom-side of the memory array800B. The memory array800B may also include a structure808B (e.g., inter connect) implemented for a split word line (e.g., a word line that is split into a first word line and a second word line). The memory array800B may also include a structure810B (e.g., WL) implemented for a bit cell, such as a transistor. The memory array800B may also include a structure820B corresponding to iron (FE). The memory array800B may also include a structure822B corresponding to oxide (e.g., SiO2). The memory array800B may also include a structure824B implemented for a channel. In this configuration, the memory array800B may have a cell count corresponding to the following equation:
Cell count=Row Count*Column Count*Floor Count  (2)

FIGS. 8C-8Dare diagrams showing example implementations of memory arrays, in accordance with some embodiments. The memory arrays800C and800D include a structure811that may include iron (FE). The memory arrays800C and800D include a structure813that may correspond to a channel. The memory arrays800C and800D include a structure815that may correspond to a select line SL (or global select line GSL) and/or a bit line BL (or global bit line GBL). The memory arrays800C and800D include a structure817that may include oxide. The memory arrays800C and800D include a structure819that may correspond to a word line WL.

In one embodiment, a process flow for building a memory array having GSL/GBL connections and single-side switches SS, SB may include the following operations: stacking, cell area dry etching, replacement silicon nitride (SiN), word line WL metal filling, iron (FE)/channel/oxide deposition, formation of global select line GSL and global bit line GNL, and contact/via. In one embodiment, a process flow may include the following operations: stacking, cell area dry etching, replacement SiN, oxide filling (for split word lines WL), word line WL metal filling, FE/channel/oxide deposition, formation of global select line GSL and global bit line GBL, and contact/via. In one embodiment, a process flow may include the following operations: stacking, cell area dry etching, replacement SiN with less length, word line WL metal filling, FE/channel/oxide deposition, formation of global select line GSL and global bit line GNL, and contact/via. In one embodiment, a process flow may be modified and/or adjusted to include additional oxide filling before word line WL metal to split the word line WL. In one embodiment, a process flow may be modified and/or adjusted to include a replacement SiN removal with less length.

FIG. 8Eis a diagram showing an example implementation of a memory array having GSL/GBL connections and single-side switches SS, SB positioned on the top-side of the memory array, in accordance with one embodiment. The memory array800E includes a structure802E (e.g., S/BL connect) implemented for a global bit line GBL connection. The memory array800E includes a structure804E (e.g., S/BL connect) implemented for a global select line GSL connection. The memory array800E may include a structure806E (e.g., SL/BL) implemented for a switch (SS, SB), such as a transistor channel. As shown, the switches are positioned on the top-side of the memory array800E. The memory array800E may also include a structure808E implemented for a split word line (e.g., a word line that is split into two word lines). The memory array800E may also include a structure810E implemented for a bit cell, such as a transistor. The memory array800E may also include a structure820E corresponding to iron (FE). The memory array800E may also include a structure822E corresponding to oxide (e.g., SiO2). The memory array800E may also include a structure824E implemented for a channel. The memory array800E includes a selection region830E and a memory cell region832E.

FIGS. 8F-8Gare diagrams showing example implementations of memory arrays having different size switches (SB, SS) in relation to the bit cell for different applications, in accordance with some embodiments. The memory arrays800F and800G include structures806F (e.g., a SG WL) and806G, respectively, implemented for a select gate (e.g., switches SS, SB). The memory arrays800F and800G may also include structures810F (e.g., Cell WL) and810G, respectively implemented for a bit cell.

As shown inFIG. 8F, the size of the structure806F of the select gate (e.g., switch SB, SS) in the vertical dimension (e.g., z-dimension) is larger than the size of the structure810F of the bit cell in the vertical dimension, in accordance with one embodiment. For example, the size of the structure806F of the select gate (e.g., switch SB, SS) in the vertical dimension (e.g., z-dimension) may be 1.5 to 3 times larger than the size of the structure810F of the bit cell in the vertical dimension. In this configuration, the select gate may have a thinner oxide (e.g., SiO2) for HP application and/or be changed to LK oxide. In some embodiments, an HP application is defined as an HPC product, which require high bandwidth, high capacity for data storage, such as AI computing device.

As shown inFIG. 8G, the size of the structure806G of the select gate (e.g., switch SB, SS) in the vertical dimension (e.g., z-dimension) is smaller than the size of the structure810G of the bit cell in the vertical dimension, in accordance with one embodiment. For example, the size of the structure806G of the select gate in the vertical dimension may be 0.5× to 0.2× of the size of the structure810G of the bitcell in the vertical dimension. In this configuration, the select gate may have a thicker oxide (e.g., SiO2) for HV application and/or the select gate material may be changed to any other material. In some embodiments, an HV application is defined as power supplier, motor controller. In some embodiment, the select gate (e.g., switch SB, SS) maybe the same size as the bit cell. In some embodiments, the oxide of an HP and/or an HV device may identify as gate oxide. In some embodiments, an HP device will use thinner gate oxide and an HV device will use a thicker gate oxide. In some embodiments, an HP device may change the oxide to LK oxide, which may also improve the performance.

FIG. 8His a table showing example embodiments of an HP application, an LP application, and an HV application. In one embodiment, an HP product may be an HPC or artificial intelligence (AI) computing device. In one embodiment, the size of the structure806F (e.g., a SG WL) of the select gate (e.g., switch SB, SS) in the vertical dimension (e.g., z-dimension) is larger than the size of the structure810F (e.g., Cell WL) of the bit cell in the vertical dimension. In one embodiment, an SG device may have a thinner gate oxide. In one embodiment, an SG device can adapt LK as isolation OX.

In one embodiment, an LP product may be one or more smart phone chips. In one embodiment, the size of the structure806F (e.g., a SG WL) of the select gate (e.g., switch SB, SS) in the vertical dimension (e.g., z-dimension) is smaller than the size of the structure810F (e.g., Cell WL) of the bit cell in the vertical dimension.

In one embodiment, an HV product may be an HPC or artificial intelligence (AI) computing device. In one embodiment, an SG device may have thicker gate oxide.

FIG. 8Iis a diagram showing an example implementation of a memory array having GSL/GBL connections and single-side switches SS, SB positioned on the top-side of the memory array, in accordance with one embodiment. The memory array800I includes a structure802I (e.g., S/BL connect) implemented for a global bit line GBL connection. The memory array800I includes a structure804I (e.g., S/BL connect) implemented for a global select line GSL connection. The memory array800I may include a structure806I implemented for a switch (SS, SB), such as a transistor channel. The memory array800I may include a structure808I implemented for a non-split word line. The memory array800I may also include a structure810I (e.g., WL) implemented for a bit cell, such as a transistor. In some embodiments, the word line WL (e.g., structure810I) is split or not by word line WL thickness. In some embodiments, a different layer (e.g., a floor in the z-direction) of the memory array800I may be a different effective word line WL (e.g., structure810I). In some embodiments, large effective width may be for strong Ion bit cell. In some embodiments, small effective width may be for low Ion bit cell. In some embodiments, non-split WL (e.g., structure810I) may be for a special bit cell or select gate SG (e.g., switches SS, SB) with strong Ion.

FIGS. 8J-8Kare diagrams showing example implementations of memory arrays having GSL/GBL connections and merged select gates, in accordance with one embodiment. The memory array800J includes a structure806J implemented for a merged select gate (e.g., switches SS, SB) on the bottom-side of memory array800J. The memory array800K includes a structure806K implemented for a merged select gate (e.g., switches SS, SB) on the top side of memory array800K. A merged select SG may be configured for strong Ion cell to perform the bit cell selection.

FIG. 8Lis a diagram showing an example implementation of a memory array from four different perspectives, in accordance with one embodiment. As shown inFIG. 8L, a memory array800L includes a structure802L (e.g., S/BL connect) implemented for a global bit line GBL connection. The memory array800L may also include a structure806L (e.g., SL/BL) implemented for a switch (SS, SB), such as a transistor channel. The memory array800L may also include a structure810L (e.g., WL) implemented for a bit cell, such as a transistor. The memory array800L may also include a structure824L implemented for a channel. The memory array800L may also include a structure830L implemented for a via (sometimes referred to as a, “staircase via”).

The memory array800L may include a two-side word line WL (e.g., structure810L) contact to relax (e.g., loosen) the routing pitch. The memory array800L may include one or more structures and/or layers of a first type that include polysilicon, TiN, W, Cu or any conductive material. In one example, the memory array800L may include one or more structures and/or layers of a second type that include polysilicon, LTPS, a-Si TFT, IGZO, or any semiconductor characteristic material. In one example, the memory array800L may include one or more structures and/or layers of a third type that include Perovskite, SBT, PZT, HfZrO, HfO and any ferroelectric characteristic material. Between the structures and/or layers, the memory cell800L may include a structure for isolation. For example, a structure may electrically isolate or decouple between other structures.

3. Method(s) for Implementing the Illustrative Embodiments

FIG. 9is a flowchart showing a method900of accessing and/or operating a memory cell (e.g., memory cell125) and/or a memory array (e.g., memory array210), in accordance with some embodiments. The method900may be performed by the memory controller105ofFIG. 1. In some embodiments, the method900is performed by other entities. In some embodiments, the method900includes more, fewer, or different operations than shown inFIG. 9.

In an operation902, the memory controller105enables (e.g., selects), during a first time period, a first switch (e.g., SB, SS) connected to a first subset (e.g.,310[00]) of a set (e.g.,310[00] . . .310[03]) of memory cells, wherein the first subset includes a first string of memory cells and a second string of memory cells. By enabling the first switch, the first subset of memory cells (including its respective first and second string of memory cells) may be electrically coupled to one or more global lines. For example, switches SB, SS connected to the subset310[00] of memory cells may be enabled, such that the subset310[00] of memory cells can be electrically coupled to the global bit line GBL[0] and the global select line GSL[0] during the first time period.

In an operation904, the memory controller105disables (e.g., deselects), during the first time period, a second switch (e.g., SB, SS) connected to a second subset (e.g.,310[01]) of the set (e.g.,310[00] . . .310[03]) of memory cells, wherein the second subset includes a third string of memory cells and a fourth string of memory cells. By disabling the second switch, the second subset of memory cells (including its respective third and fourth string of memory cells) may be electrically decoupled from the one or more global lines. For example, switches SB, SS connected to the subset310[01] of memory cells may be disabled, such that the subset310[01] of memory cells can be electrically decoupled from the global bit line GBL[0] and the global select line GSL[0] during the first time period. In one approach, the memory controller105may disable switches (e.g., SB, SS) connected to other subsets (e.g.,310[02],310[03]) of the set (e.g.,310[00] . . .310[03]) of memory cells, such that the global line (e.g., GBL[0], GSL[0]) has a capacitive loading corresponding to the first subset (e.g.,310[00]) of memory cells instead of the entire set (e.g.,310[00] . . .310[03]) of memory cells.

In an operation906, the memory controller105accesses (e.g., configures, programs, reads, writes), during the first time period, one or more memory cells of the first subset (e.g.,310[00]) of memory cells. For example, the memory controller105may apply a voltage, current, or pulse to a string of memory cells through its respective split word line (e.g., WL[X][Y]_L or WL[X][Y]_R) to program the string of memory cells or cause the string of memory cells to conduct current according to the programmed data. For example, a first string of memory cells that are positioned on the left side of selected subset310[00] may be coupled to WL[0][0]_L and a second string of memory cells that are positioned on the right side of selected subset310[00] may be coupled to WL[0][0]_R. The memory controller105may access the first string of memory cells by applying a voltage, current, or pulse to WL[0][0]_L. Since the second string of memory cells are not coupled to WL[0][0]_L, but rather coupled to WL[0][0]_R, the memory controller105may access the first string of memory cells without being loaded by the capacitance of the second string of memory cells.

In one approach, the memory controller105may apply the voltage, current, or pulse to other strings of memory cells in unselected subsets (e.g.,310[01] . . .310[03]) of memory cells. However, because the switches SB, SS connected to the unselected subsets of memory cells are electrically decoupled from the global lines GBL, GSL, the memory cells in the unselected subsets may not be programmed or may not conduct current despite the voltage, current, or pulses applied. Hence, the memory controller105may access a string of memory cells in a selected subset (e.g.,310[00]) of memory cells without being loaded by the capacitance of other strings of memory cells in unselected subsets.

In one approach, the memory controller105may enable, during the first time period, a third switch (e.g., SB, SS) connected to a third subset (e.g.,310[10]) of a set (e.g.,310[10] . . .310[13]) of memory cells, wherein the third subset includes a fifth string of memory cells and a sixth string of memory cells. The memory controller105may disable, during the first time period, a fourth switch (e.g., SB, SS) connected to a fourth subset (e.g.,310[11]) of the set (e.g.,310[10] . . . [13]) of memory cells, wherein the fourth subset includes a seventh string of memory cells and a eighth string of memory cells. During the first time period, the memory controller105may disable other switches (e.g., SB, SS) connected other subsets (e.g.,310[12],310[13]) of the set of memory cells. By enabling the third switch connected to the third subset (e.g.,310[10]) of memory cells (including its respective fifth and sixth string of memory cells) and disabling other switches connected to other subsets (e.g.,310[11] . . .310[13]) of the set of memory cells (e.g.,310[10] . . .310[13]), the global line (e.g., GBL[1], GSL[1]) may have a capacitive loading corresponding to the third subset (e.g.,310[10]) of memory cells instead of the entire set (e.g.,310[10] . . .310[13]) of memory cells. Moreover, a string of memory cells of the third subset (e.g.,310[10]) of memory cells can be accessed via its respective split word line (e.g., WL[X][Y]_L), while a string of memory cells of the first subset (e.g.,310[00]) of memory cells can be accessed through the same (shared) word line during the first time period. For example, a fifth string of memory cells that are positioned on the left side of subset310[10] and a first string of memory cells that are positioned on the left side of subset310[00] can each be accessed via WL[0][0]_L. As another example, a sixth string of memory cells that are positioned on the right side of subset310[10] and a second string of memory cells that are positioned on the right side of subset310[00] can each be accessed via WL[0][0]_R.

In an operation908, the memory controller105enables, during a second time period, the second switch (e.g., SB, SS) connected to the second subset (e.g.,310[01]) of the set (e.g.,310[00] . . .310[03]) of memory cells. By enabling the second switch, the second subset (e.g.,310[01]) of memory cells (including its respective third and fourth string of memory cells) may be electrically coupled to the global line. For example, switches SB, SS connected to the subset310[01] of memory cells may be enabled, such that the subset310[01] of memory cells can be electrically coupled to the global bit line GBL[0] and the global select line GSL[0] during the second time period.

In an operation910, the memory controller105disables, during the second time period, the first switch (e.g., SB, SS) connected to the first subset (e.g.,310[00]) of the set (e.g.,310[00] . . .310[03]) of memory cells. By disabling the first switch, the first subset (e.g.,310[00]) of memory cells may be electrically decoupled from the global line. For example, switches SB, SS connected to the subset310[00] of memory cells may be disabled, such that the subset310[00] of memory cells (including its respective first and second string of memory cells) can be electrically decoupled from the global bit line GBL[0] and the global select line GSL[0]. In one approach, the memory controller105may disable switches (e.g., SB, SS) connected to other subsets (e.g.,310[02],310[03]) of the set (e.g.,310[00] . . .310[03]) of memory cells, such that the global line (e.g., GBL[0], GSL[0]) has a capacitive loading corresponding to the second subset (e.g.,310[01]) of memory cells instead of the entire set (e.g.,310[00] . . .310[03]) of memory cells.

In an operation912, the memory controller105accesses (e.g., configures, programs, reads, writes), during the second time period, one or more memory cells of the second subset (e.g.,310[01]) of memory cells. For example, the memory controller105may apply a voltage, current, or pulse to a string of memory cells through its respective split word line (e.g., WL[X][Y]_L or WL[X][Y]_R) to program the string of memory cells or cause the string of memory cells to conduct current according to the programmed data.

In one approach, the memory controller105may apply the voltage, current, or pulse to other strings of memory cells in unselected subsets (e.g.,310[00],310[02] . . .310[03]) of memory cells. However, because the switches SB, SS connected to the unselected subsets of memory cells are electrically decoupled from the global lines GBL, GSL, the memory cells in the unselected subsets may not be programmed or may not conduct current despite the voltage, current, or pulses applied through word lines. Hence, the memory controller105may access a string of memory cells in a selected subset (e.g.,310[01]) of memory cells without being loaded by the capacitance of other strings of memory cells in unselected subsets.

In one approach, the memory controller105may enable, during the second time period, the fourth switch (e.g., SB, SS) connected to the fourth subset (e.g.,310[11]) of the set (e.g.,310[10] . . .310[13]) of memory cells, wherein the third subset includes a fifth string of memory cells and a sixth string of memory cells. The memory controller105may disable, during the second time period, the third switch (e.g., SB, SS) connected to the third subset (e.g.,310[10]) of the set (e.g.,310[10] . . . [13]) of memory cells, wherein the third subset includes a third string of memory cells and a fourth string of memory cells. During the second time period, the memory controller105may disable other switches (e.g., SB, SS) connected other subsets (e.g.,310[12],310[13]) of the set of memory cells. By enabling the fourth switch connected to the fourth subset (e.g.,310[11]) of memory cells (including its respective seventh and eighth string of memory cells) and disabling other switches connected to other subsets (e.g.,310[10],310[12] . . .310[13]) of the set of memory cells (e.g.,310[10] . . .310[13]), the global line (e.g., GBL[1], GSL[1]) may have a capacitive loading corresponding to the fourth subset (e.g.,310[11]) of memory cells instead of the entire set (e.g.,310[10] . . .310[13]) of memory cells. Moreover, a string of memory cells of the fourth subset (e.g.,310[11]) of memory cells can be accessed, while a string of memory cells of the second subset (e.g.,310[01]) of memory cells are accessed through the same (e.g., shared, common, coupled) word line during the second time period.

4. Computing System for Implementing the Illustrative Embodiments

FIG. 10is an example block diagram of a computing system1000, in accordance with some embodiments of the disclosure. The computing system1000may be used by a circuit or layout designer for integrated circuit design. A “circuit” as used herein is an interconnection of electrical components such as resistors, transistors, switches, batteries, inductors, or other types of semiconductor devices configured for implementing a desired functionality. The computing system1000includes a host device1005associated with a memory device1010. The host device1005may be configured to receive input from one or more input devices1015and provide output to one or more output devices1020. The host device1005may be configured to communicate with the memory device1010, the input devices1015, and the output devices1020via appropriate interfaces1025A,1025B, and1025C, respectively. The computing system1000may be implemented in a variety of computing devices such as computers (e.g., desktop, laptop, servers, data centers, etc.), tablets, personal digital assistants, mobile devices, other handheld or portable devices, or any other computing unit suitable for performing schematic design and/or layout design using the host device1005.

The input devices1015may include any of a variety of input technologies such as a keyboard, stylus, touch screen, mouse, track ball, keypad, microphone, voice recognition, motion recognition, remote controllers, input ports, one or more buttons, dials, joysticks, and any other input peripheral that is associated with the host device1105and that allows an external source, such as a user (e.g., a circuit or layout designer), to enter information (e.g., data) into the host device and send instructions to the host device. Similarly, the output devices1020may include a variety of output technologies such as external memories, printers, speakers, displays, microphones, light emitting diodes, headphones, video devices, and any other output peripherals that are configured to receive information (e.g., data) from the host device1005. The “data” that is either input into the host device1005and/or output from the host device may include any of a variety of textual data, circuit data, signal data, semiconductor device data, graphical data, combinations thereof, or other types of analog and/or digital data that is suitable for processing using the computing system1000.

The host device1005includes or is associated with one or more processing units/processors, such as Central Processing Unit (“CPU”) cores1030A-1030N. The CPU cores1030A-1030N may be implemented as an Application Specific Integrated Circuit (“ASIC”), Field Programmable Gate Array (“FPGA”), or any other type of processing unit. Each of the CPU cores1030A-1030N may be configured to execute instructions for running one or more applications of the host device1005. In some embodiments, the instructions and data to run the one or more applications may be stored within the memory device1010. The host device1005may also be configured to store the results of running the one or more applications within the memory device1010. Thus, the host device1005may be configured to request the memory device1010to perform a variety of operations. For example, the host device1005may request the memory device1010to read data, write data, update or delete data, and/or perform management or other operations. One such application that the host device1005may be configured to run may be a standard cell application1035. The standard cell application1035may be part of a computer aided design or electronic design automation software suite that may be used by a user of the host device1005to use, create, or modify a standard cell of a circuit. In some embodiments, the instructions to execute or run the standard cell application1035may be stored within the memory device1010. The standard cell application1035may be executed by one or more of the CPU cores1030A-1030N using the instructions associated with the standard cell application from the memory device1010. In one example, the standard cell application1035allows a user to utilize pre-generated schematic and/or layout designs of the memory system100or a portion of the memory system100to aid integrated circuit design. After the layout design of the integrated circuit is complete, multiples of the integrated circuit, for example, including the memory system100or a portion of the memory system100can be fabricated according to the layout design by a fabrication facility.

Referring still toFIG. 10, the memory device1010includes a memory controller1040that is configured to read data from or write data to a memory array1045. The memory array1045may include a variety of volatile and/or non-volatile memories. For example, in some embodiments, the memory array1045may include NAND flash memory cores. In other embodiments, the memory array1045may include NOR flash memory cores, Static Random Access Memory (SRAM) cores, Dynamic Random Access Memory (DRAM) cores, Magnetoresistive Random Access Memory (MRAM) cores, Phase Change Memory (PCM) cores, Resistive Random Access Memory (ReRAM) cores, 3D XPoint memory cores, ferroelectric random-access memory (FeRAM) cores, and other types of memory cores that are suitable for use within the memory array. The memories within the memory array1045may be individually and independently controlled by the memory controller1040. In other words, the memory controller1040may be configured to communicate with each memory within the memory array1045individually and independently. By communicating with the memory array1045, the memory controller1040may be configured to read data from or write data to the memory array in response to instructions received from the host device1005. Although shown as being part of the memory device1010, in some embodiments, the memory controller1040may be part of the host device1005or part of another component of the computing system1000and associated with the memory device. The memory controller1040may be implemented as a logic circuit in either software, hardware, firmware, or combination thereof to perform the functions described herein. For example, in some embodiments, the memory controller1040may be configured to retrieve the instructions associated with the standard cell application1035stored in the memory array1045of the memory device1010upon receiving a request from the host device1005.

It is to be understood that only some components of the computing system1000are shown and described inFIG. 10. However, the computing system1000may include other components such as various batteries and power sources, networking interfaces, routers, switches, external memory systems, controllers, etc. Generally speaking, the computing system1000may include any of a variety of hardware, software, and/or firmware components that are needed or considered desirable in performing the functions described herein. Similarly, the host device1005, the input devices1015, the output devices1020, and the memory device1010including the memory controller1040and the memory array1045may include other hardware, software, and/or firmware components that are considered necessary or desirable in performing the functions described herein.

One aspect of this description relates to a memory array. In some embodiments, the memory array includes a first set of memory cells including a first subset of memory cells and a second subset of memory cells. In some embodiments, the memory array includes a first switch including a first electrode connected to first electrodes of the first subset of memory cells, and a second electrode connected to a first global line. In some embodiments, the memory array includes a second switch including a first electrode connected to first electrodes of the second subset of memory cells, and a second electrode connected to the first global line.

One aspect of this description relates to a memory system. In some embodiments, the memory system includes a memory array and a controller. In some embodiments, the memory array includes a first set of memory cells, a second set of memory cells, a first switch connected to the first set of memory cells, and a second switch connected to the second set of memory cells. In some embodiments, the controller is connected to the memory array. In some embodiments, the controller is to enable, during a first time period, the first switch while disabling the second switch to electrically couple the first set of memory cells to a first global select line and electrically decouple the second set of memory cells from the first global select line. In some embodiments, the controller is to enable, during a second time period, the second switch while disabling the first switch to electrically couple the second set of memory cells to the first global select line and electrically decouple the first set of memory cells from the first global select line.

One aspect of this description relates to a method of operating a memory system. In some embodiments, the method includes enabling, during a first time period, a first switch connected to first electrodes of a first set of memory cells to electrically couple the first electrodes of the first set of memory cells to a first global select line. In some embodiments, the method includes disabling, during the first time period, a second switch connected to first electrodes of a second set of memory cells to electrically decouple the first electrodes of the second set of memory cells from the first global select line. In some embodiments, the method includes enabling, during the first time period, a third switch connected to second electrodes of the first set of memory cells to electrically couple the second electrodes of the first set of memory cells to a first global bit line. In some embodiments, the method includes disabling, during the first time period, a fourth switch connected to second electrodes of the second set of memory cells to electrically decouple the second electrodes of the second set of memory cells from the first global bit line. In some embodiments, the method includes configuring, during the first time period, one or more memory cells of the first set of memory cells.