Host computer virtual memory within a network interface adapter

A system and method of mapping a host computer address space into a network interface adapter (NIA) address space. A network interface processor within the NIA requests a memory allocation from the host computer. The host computer responds with an assigned base address in the host computer address space, and a length defining the contiguous addresses within the host computer address space equal to the allocation requested by the NIA processor. A hardware trap is set such that an interrupt to the NIA processor is generated when the host computer attempts to access data at an address within the allocated address range of host computer contiguous addresses. The network interface processor translates the received host address to a physical address within the NIA address space, reads the data at the respective NIA physical address, and transfers the data to the host computer.

BACKGROUND OF THE INVENTION

The present application relates generally to computer software boot techniques, and more particularly to the execution of computer boot techniques within a network interface adapter.

In a typical computer system interconnected to a network, a network interface adapter (NIA) acts as an interface between the host computer and a computer network. The NIA performs the necessary interface functions for transmitting and receiving data over the computer network. The NIA includes a memory for storing data or software program code images that the host computer utilizes in communicating over the computer network. As such, the data and software program code images must be accessible to the host computer in order to be accessed and utilized by the host computer. In order for these resources to be accessible to the host computer, they must be included in the host computer address space. To be included within the host computer address space, these resources need to have memory addresses assigned to them that are accessible by the host computer.

Prior art systems have stored such data and software program code images in serial EEPROMs. However, a bottleneck may exist in the transfer of a data image or a code image from the NIA to the host computer due to the serial nature and speed of such EEPROMs.

It would therefore be desirable to have an NIA that is capable of storing data and software program code images having a non-static host address, and of transferring the data and software program code images stored at an NIA address, which is specifiable and is independent of the host computer address, to the host computer more efficiently.

BRIEF SUMMARY OF THE INVENTION

Consistent with the present invention, a system and method are disclosed for accessing a data image stored within a network interface adapter (NIA) by a host computer. Upon boot up, the NIA requests an allocation of memory space from the host computer that may be accessed by the host computer. The host computer responds with an individual base address and memory allocation. Each of the base addresses supplied is within the host computer address space. When the host computer attempts to read data contained within the address space assigned to the NIA, the address is trapped on the NIA, and the NIA processor is notified. The NIA processor reads the address requested by the host computer, and translates the address in the host computer address space into a physical address in the NIA address space. Upon locating the data at the applicable physical address, the NIA processor transfers the data to the host computer.

Other features, functions, and aspects of the invention will be evident from the Detailed Description of the Invention that follows.

DETAILED DESCRIPTION OF THE INVENTION

U.S. patent application Ser. No. 09/590,892 filed Jun. 9, 2000 entitled HOST COMPUTER VIRTUAL MEMORY WITHIN A NETWORK INTERFACE ADAPTER is hereby incorporated herein by reference.

Consistent with the present invention, a system and method of performing a virtual boot of data in a network interface adapter (NIA) is disclosed. The host computer reads a PCI configuration register that has been loaded with a predetermined request for the memory needed for the BIOS ROM. The host computer responds with an assigned base address in the host computer address space, and an allocation of a range of contiguous addresses within the host computer address space equal to the amount of memory requested by the NIA processor. A hardware trap within the NIA is set to occur on the base address and the range of contiguous addresses assigned to the NIA by the host computer such that, when the host computer attempts to access an address within the range of contiguous addresses, the network interface processor is notified. In response to notification of the receipt of an address within the specified range, the network interface processor translates the address within the host computer address space to a physical address within the NIA address space. The network interface processor then locates and transfers the contents of the address(es) to the host computer. As used herein, “data” may include software program code, or any other information used by a software program during execution.

FIG. 1depicts a system10including a NIA14that is capable of performing a virtual boot of a data image or a software program code image under the control of a NIA processor24within the NIA14, according to the present invention. The processor may comprise an Advanced Reduced Instruction Set Computer (RISC) Machine (ARM) processor integrated on an application specific integrated circuit (ASIC)44with other components, as discussed later in greater detail. The NIA14includes a PCI interface40that couples the network interface processor24to a PCI bus13via a plurality of registers. These registers can include PCI configuration registers36, address registers38, data transfer registers37, and status registers39. In the presently disclosed embodiment, the PCI configuration registers36comprise a plurality of registers that are used to pass configuration requests from the NIA14to the host computer12, configuration responses from a host computer12to the NIA14, and configuration data between both the NIA14and the host computer12. The address registers38comprise a plurality of registers, and are used to pass an address or addresses to the NIA containing data or software program code required by the host computer. The addresses passed to the NIA from the host computer will be located within the host computer address space. The data transfer registers37are employed in the transmission of data, software program code, or other information between the NIA14and the host computer12. The status registers39may be used to provide a status indicator of whether the host computer is reading or writing data to a memory location in the NIA memory.

A ROM26, External RAM34, Instruction RAM28, Data RAM30, and Flash RAM32are coupled to the NIA processor24to enable the processor24to read and write instructions and data from and to the respective memories, as applicable. A cryptographic processor34, may be coupled to the NIA processor24. The cryptographic processor34is employed to accelerate cryptographic functions within the NIA14. The NIA processor24is also coupled to a NIA network interface42, which is coupled to a network to permit reception and transmission of information over the network. A hardware logic or state machine35is coupled to the PCI Bus Interface40and to the ARM processor24. The hardware logic or state machine35traps on an address on the PCI bus interface40that is within a predetermined address range, and notifies the ARM processor24thereof.

In the presently disclosed embodiment, the NIA is coupled to the host computer12via a host PCI interface20. The host computer12includes a host processor16, a host memory18, and control logic19. The host processor16is communicably coupled to the host memory18and the host PCI interface20.

The NIA14may be fabricated integrally on a motherboard with host computer electronics or alternatively as a separate network interface adapter card.

As indicated above, the NIA processor24may comprise an ARM processor. The ARM processor may be integrated on the ASIC44along with the ROM26, IRAM28, DRAM30, the PCI configuration registers36, the address registers38, the data transfer registers37, and the hardware logic or state machine35.

More specifically, the NIA14provides a request for configuration data from the host computer12via the PCI configuration data registers36, the PCI bus interface40, the PCI bus13, and the host PCI interface20. Such configuration data can include a request for address assignments within the host computer address space from the host computer for resources within the NIA. Such a request can be made, for example, for address assignments associated with the input/output (I/O) of the NIA14, the RAM or ROM memory contained within the NIA14, and BIOS ROM used by the NIA14. Memory addresses for data images and software program code images are contained within the Flash RAM32. In a preferred embodiment, the NIA14requests a BIOS ROM address for netboot code contained within the Flash RAM32.

Additionally, the host computer12can request to read data assigned within in its own memory space that is physically located within the NIA14by providing an address to the NIA processor via the address registers38. As will be explained in more detail below, the physical memory contained within the NIA14has a different physical address than that assigned by the host computer12in the configuration response. Accordingly, when the NIA processor24is notified that the host computer12is requesting to read data from an address within the host computer address space assigned to the NIA14, the NIA processor24translates that address to a physical address contained within the NIA address space. As discussed in more detail below, in one embodiment, in which the data being retrieved by the host computer12resides within the Flash RAM32, the NIA processor locates the physical address of data being retrieved within the Flash RAM32. As will be discussed below, the Flash RAM32includes a section containing section headers that include a pointer to the beginning of each section. Using the address from the host computer, the NIA processor computes an offset from the assigned base address, and uses this offset to locate the physical address of the data within the particular section of the Flash RAM32. The NIA processor24then transfers the data associated with the address to the host computer. Thus, the operation of translating from a virtual boot memory address to a physical address is completely transparent to the host computer12.

A technique for translating between the host address space and the NIA address space to facilitate reading from and writing to the NIA address space is described below. In the case of a read operation, the NIA processor translates the host address as described herein, retrieves the data from an NIA memory such as the Flash RAM at the location(s) specified by the translated address(es), and writes the data into the data transfer registers for transmittal to the host computer. In the case of a write operation, the NIA processor translates the host address as described herein, retrieves the data from the data transfer registers37, and writes the data into the desired physical memory location in the NIA memory.

The hardware logic or state machine35is responsible for monitoring the PCI bus interface40and notifying the NIA processor24when one or more predetermined conditions occur. The hardware logic or state machine35may be either a combinatorial logic or a state machine that is operative to monitor certain bus, address, or data lines for an occurrence of these certain conditions. These predetermined conditions may include particular addresses that are being accessed by the host computer12, predetermined data, or commands. More specifically, the hardware logic or state machine determines whether the respective host operation is a read or a write operation, and sets the appropriate status bit in the status register to identify the operation, as applicable. The hardware logic or state machine35also monitors the PCI bus interface40for an address within the host computer address space that has been assigned to the NIA14. The hardware logic or state machine35is further operative to notify the NIA processor24upon the occurrence of one of the predetermined conditions. This notification may be in the form of an interrupt to the NIA processor24or via a status bit accessible to the NIA processor24.

The organization of the Flash RAM32in the presently disclosed system is illustrated in FIG.2. In a preferred embodiment, the Flash RAM32comprises a serial device that is organized as a paginated memory and contains 512 pages. The Flash Ram contains 264 bytes per page.

The first entry in the Flash RAM32is a unique ASCII string202that may be verified by the processor to indicate that the Flash RAM32has been loaded with the appropriate code image. The next entries in the Flash RAM32include section headers204. The section headers may include two entries. The first entry is a section identifier206that identifiers the code within the respective section. The second entry in the section headers204is a section pointer208that provides a software pointer to the address of the first location within the section corresponding to the section identifier. In a preferred embodiment, there are a maximum of 16 sections stored within the Flash RAM32.

A static data section210may contain static configuration data such as the PCI device identifier, MAC address, and serial numbers and other manufacturing parameters of the NIA. In one embodiment, the NIA includes a PCI device ID that signifies the type of cryptographic processor expected to be populated on the NIA. The static data section210also includes a header portion located at the beginning of the section. The header portion contains a section length parameter212, a load address214, and a checksum216derived from the data stored within static section210. Although the header portion associated with the static data section210contains a load address, it is not used in the presently illustrated embodiment.

Variable data section218may contain variable configuration data, which is typically the configuration data for the NIA. This variable data may include the factory default configuration data and in one embodiment, may be modified by a user. The variable data section218also includes a header portion located at the beginning of the variable data section218containing a section length parameter220that defines the length of the respective section, a load address222that specifies the memory location in NIA memory at which to store the variable data and a checksum224derived from the data stored within the variable section218. Although the section header associated with the variable data section218contains a load address, this load address is not used.

Variable prime data section226may contain factory default configuration settings for the NIA that are used as a data backup for the variable data stored in variable data section218. In one embodiment, to ensure the integrity of the data stored in this page, the user is unable to over-write that data stored in this section. The variable prime data stored in variable prime data section226of the Flash RAM32may be used by the host processor to rewrite certain invalid data values stored in other pages and sections within the Flash RAM32. Variable prime data section226includes a header portion located at the beginning of the section containing a section length parameter228defining the length of the respective section, a load address230that specifies the NIA memory address, and a checksum232derived from the data stored within variable prime section226. Although the header portion contains a load address, this load address is not used.

A boot image section234contains the boot software for the NIA. This boot software code includes self diagnostic software code herein discussed. Preferably the boot image code is stored in contiguous pages of memory within the boot image section234or may be stored in contiguously linked pages. The boot image section234also includes a header portion located at the beginning of the boot image section234. The header portion contains a section length parameter236that defines the length of the boot image section234, a load address238that provides the address where the boot software code is to be loaded in NIA memory, and a checksum240derived from the data stored within the boot image section234.

The sleep image code may be divided into a number of sections, depending on the system requirements. The sleep code may be divided into a plurality of sections, each being loaded into a different RAM module in the NIA. The Sleep image-1section242contains the first section of the sleep software code. The Sleep image-1section242includes a header portion located at the beginning of the section. The header portion contains a section length parameter244defining the length of the sleep image section, a load address246that defines the memory and address where the first section of the sleep software code is to be loaded, a checksum248derived from the software code stored within the sleep image-1section242, and a next-section-pointer250. The next section pointer250provides a software pointer link to the location in the Flash RAM32where the subsequent section of sleep software code is stored.

In the embodiment illustrated inFIG. 2, a second sleep image section, i.e., sleep image-2section252, is provided. Sleep image-2section252provides a second section of sleep software code that will be loaded into a different RAM module than the sleep image-1software code. A header portion is located at the beginning of the section. The header portion contains a section length parameter254that defines the length of the sleep image-2section, a load address256identifying the memory and address into which the sleep image-2section is to be loaded, a checksum258derived from the software code stored within the sleep image-1section242, and a next-section-pointer260. The next section pointer260provides a software pointer link to the location in the Flash RAM32where the subsequent section of sleep software code is stored, if a sequential section is present. It should be understood that there may be as many sections of sleep software code as needed for a given system.

The netboot image section262contains the Net boot software code and contains the code for establishing the communication parameters between the NIA and the network. The Net boot image section includes a header portion located at the beginning of the section. The header portion includes a section length parameter264, a load address266providing an address where the Net boot software code could be loaded, and a checksum268derived from the data stored within the Net boot image section262. Although the header portion associated with the netboot image section262contains a load address, it is not used in the presently illustrated embodiment.

During the boot up process, the NIA14requests memory allocations from the host processor24, for a certain amount of memory sufficient to accommodate information to be transferred from the NIA to the host. The host processor assigns for each such allocation a base address within the host address space, and a length defining contiguous memory addresses within the host address space. This allocation establishes a range of addresses within the host computer address space that will accommodate the information to be transferred from the NIA14. This allows the host processor to access the NIA memory by reading data contained at a memory address within the host address space. Hardware logic or state machine35monitors the interface between the NIA14and the host computer12and traps on an address that is within the range of memory addresses assigned by the host computer to the NIA. The NIA processor24is notified (preferably by an interrupt) when the host computer is attempting to access one or more addresses within the range of addresses assigned to the NIA14. The NIA processor24reads the address(es) written to the address registers38by the host computer and translates the host computer address(es) into a physical address contained within the NIA address space. The NIA processor24then transfers the requested data from the respective physical NIA memory address to the host computer using the data registers37.

The method of translating from a host address space to an NIA address space is further described in the flow diagram of FIG.3. The NIA processor24requests a memory allocation within the address space of the host computer12, as depicted in step302. The NIA processor24may request memory allocations for various functions such as the I/O of the NIA14, the memory space contained within the NIA14, and the ROM BIOS of the NIA14. The host computer12responds to the NIA with a base address within the host address space for each memory allocation requested by the NIA14, and a length that defines the allocated size of the contiguous address space within the host computer12, as depicted in step304. Each function therefore receives a base address and a contiguous range of memory addresses extending from the assigned host computer base address. Each NIA memory allocation request, however, does not have to be contiguous in the host computer address space or with any other host computer allocation.

The host computer requests data contained within an NIA memory, and provides to the NIA a host computer address within the range of memory addresses assigned by the host computer to the NIA, as depicted in step306. The host address is checked to verify that it is within the address space assigned by the host computer12to the NIA14, as depicted in step308. A high speed processor, combinatorial logic, or a state machine may be used to trap the incoming address within the specified range. If the address received from the host computer is within the range of host computer addresses allocated to the NIA14, then the NIA processor24is notified that the host computer12is requesting data from the NIA14, as depicted in step310. The NIA processor24reads the address or addresses in the address register38, as depicted in step312.

The NIA processor24translates the received host address into a physical address contained within the NIA address space, as depicted in step314. For example, if the NIA14requested a memory allocation for the BIOS ROM to be assigned to the netboot code, then as described above, the netboot code would receive a particular base address and a contiguous range of memory addresses within the host computer address space having a length equal to the netboot code length. Accordingly, for the host computer to access a memory address that is within the Bios ROM address range, the NIA processor will locate the netboot code section within the NIA address space. The data may be contained within the Flash RAM32, and the NIA processor24can utilize the section header section204of the Flash RAM32to locate the particular section within it.

The NIA processor24accesses the contents of the physical address within the NIA address space that corresponds to the host computer address, as depicted in step316. The NIA processor may determine the offset of the host computer address from the host computer assigned base address. Using this offset, the NIA processor locates the desired data within the physical memory of the NIA address space by accessing the contents that are offset from the beginning address of the physical memory section within the NIA address space in which the data resides. In one embodiment, in which the Flash RAM32contains the data, the NIA processor24locates the address of the desired data as the offset distance from the beginning of the above-identified section.

The NIA processor24transfers the desired data to the host computer12, as depicted in step318. The NIA processor reads the desired data, and transfers the desired data to the host computer via the data transfer registers37, the PCI bus interface40, the PCI bus, and the host PCI interface20.

Those of ordinary skill in the art should further appreciate that variations to and modifications of the above-described method and system may be made without departing from the inventive concept disclosed herein. Accordingly, the invention should be viewed as limited solely by the scope and spirit of the appended claims.