Method for prevention of latch-up of CMOS devices

A MOSFET integrated circuit device comprises a lightly doping a semiconductor substrate, with wells formed within the substrate doped with an opposite value dopant, forming a plurality of doped regions within the surface of the substrate and within the surface of the wells, the improvement comprising opening a trench about the periphery of the wells, and filling the trench with a relatively highly conductive material as a guard structure.

BACKGROUND OF THE INVENTION 
1. Field of the Invention 
This invention relates to MOSFET devices and more particularly to 
prevention of latchup problems therein. 
2. Description of Related Art 
U.S. Pat. No. 4,927,777 of Hsu et al "Method of Making a MOS Transistor" 
shows forming trenches about wells of oppositely doped material with 
insulating material. 
U.S. Pat. No. 4,960,726 of Lechaton et al "BICMOS Process" describes deep 
trenches which are lined with an insulating material such as silicon 
dioxide and filled with a "filler material" such as polysilicon or an 
insulator. There are shallow trench structures comprising an insulating 
material such as silicon dioxide or intrinsic polysilicon. 
U.S. Pat. No. 5,071,777 of Gahle "Method of Fabricating Implanted Wells and 
Islands of CMOS Circuits" protection against latch-up is provided by edge 
regions which are thermally oxidized to form a field oxide layer. 
U.S. Pat. No. 5,096,843 of Kodaira "Method of Manufacturing a Bipolar CMOS 
Device" employs a trench filled with material formed on the side wall of 
the trench serving as a barrier against impurities. 
U.S. Pat. No. 5,137,837 of Chang et al "Radiation-Hard High-Voltage 
Semiconductive Device Structure Fabricated on SOI Substrate" and U.S. Pat. 
No. 5,158,900 of Lau et al "Method of Separately Fabricating a 
Base/Emitter Structure of a BiCMOS Device" show methods/structures for 
isolating bipolar, NMOS and PMOS devices within an integrated circuit 
structure. 
Latch-up is a malfunction of MOSFET devices which presents a problem in the 
design of CMOS integrated circuits. Several solutions have been 
recommended in the past. One is the use of epitaxial wafers which is not 
cost effective. Another solution is enlargement of N+ device and P+ device 
spacing, which will enlarge the die size which is undesirable where 
smaller size is more desirable. The minority carrier should be recombined 
in the enlarged spacing, the substrate current I.sub.b (FIG. 1) could be 
reduced. 
An object of the instant invention is to reduce the die size, enhance the 
immunity to latchup, and provide greater cost effectiveness. 
Latchup Mechanism 
FIG. 1 shows a physics and lumped circuit model illustrating problem of the 
latchup mechanism of a CMOS device. The schematic and equivalent circuits 
of parasitic resistors R.sub.S 35 and R.sub.W 36 and parasitic NPN and PNP 
bipolar transistors 27 and 31 in the CMOS are drawn as equivalent discrete 
devices. The CMOS device is formed on a P- doped substrate 10. The bias 
V.sub.SS is connected by line 25 to lines 8 and 9 which are connected to 
P+ region 11 and N+ region 12. N+ region 12 is the source of an FET device 
5 comprising gate 14 (connected by line 17 to V.sub.IN, and completed by 
the drain in the form of an N+ region 13 connected by line 16 to 
V.sub.OUT, The emitter of NPN equivalent transistor 27 is connected to 
source region 12 from internally of the substrate 10. The collector of 
transistor 27 is connected by line 28 to the base of PNP transistor 31 
which is shown within the n-well tub 30 in which the other, adjacent FET 
device 6 is located. The base of transistor 27 is connected to line 38 
which connects to one end of equivalent R.sub.S resistor 36, the other end 
of which is connected to the P+ region 11. Line 38 is also connected via 
line 34 in well 30 to the collector of transistor 31, the emitter of which 
is connected via line 33 to P+ region 20 which is the drain of the FET 6, 
which is biased by V.sub.DD source 22 through line 22. V.sub.DD is 
connected via line 7 to N+ region 23 as well, which is connected to one 
end of R.sub.W which is connected to the base of PNP transistor 31. 
A mathematical analysis of the relationships shown by the lumped circuit 
model of FIG. 1 is set forth below: 
EQU .beta..sub.npn, .beta..sub.pnp : common-emitter current gain 
positive feedback condition: 
EQU (I.sub.b .beta..sub.npn IRw).beta..sub.pnp -I.sub.RS &gt;I.sub.b 
R.sub.S =shunting resistance 
.beta.=device transconductance parameter 
I.sub.RS =current through shunting resistance 
I.sub.b =current to base of a "parasitic" npn bipolar transistor 
EQU I.sub.b (.beta..sub.npn .beta..sub.pnp -1)&gt;I.sub.RS +I.sub.RW .beta..sub.pn 
p 
R.sub.W =Well Resistance 
I.sub.b can be expressed in terms of total supply current I.sub.DD 
I.sub.DD =I.sub.RS +I.sub.b (.beta..sub.npn +1) 
##EQU1## 
Known methods of avoiding latchup: 
1. Reducing the bipolar gain (.beta..sub.npn .beta..sub.pnp) 
2. Lowering the shunting resistances (R.sub.S and R.sub.W) Additional 
relevant factors are as follows: 
1. Reduction of the bipolar gain degrades the performance of the FET 
device. 
2. Lowering the R.sub.S (shunting resistance) by using an epitaxial wafer 
leads to high cost. 
3. Lowering the R.sub.W shunting resistance is a good approach. 
FIG. 2 shows a partially three dimensional layout of an MOSFET device to 
illustrate a potential latchup path typical of prior art devices. 
In a semiconductor substrate 40 which is doped with P dopant, an N- well 41 
contains an N+ structure 42 comprising an N+ well pick-up. Parallel to 
structure 42 is a P+ structure 43. The structures 42 and 43 are connected 
to voltage source V.sub.CC. Adjacent to well 41 extending transversely 
with respect to the direction of structures 42 and 43 is a structure 44 
composed of N+ dopant. Structure 44 is connected to bias source V.sub.SS. 
A V.sub.CC to V.sub.SS path is formed by P+ structure 43, an N- well 41, a 
P- sub 40, and N+ structure 44, referred to hereinafter as an "SCR" path. 
To the right side of FIG. 2, a two dimensional view of an N+ region 47 
another N- well 50 is shown with a P+ region 48 connected via line 46 to 
V.sub.I/O and a N+ region 49 connected to V.sub.CC. A number of electrons 
are shown in the bulk of the substrate 40 adjacent to N+ region 47. 
Negative charge 52 is referred to as a minority carrier injection into N- 
well 50 which has the effect when the V.sub.I/O undershooting below the P- 
(V.sub.SS, the minority carrier (electron) injected from the N+ to the P- 
(substrate.) An electron 51 is shown approaching the N- well 41 and it 
indicates the need to insert a conductive guard structure in accordance 
with this invention. The electrons form the substrate current. The 
conductive guard ring structure must be inserted between the N+ region 47 
and the N- well 41 to collect the electrons. 
FIG. 3A shows a prior art P- semiconductor substrate 55 with a conventional 
approach to the problem of latchup wherein a space of 100 .mu.m is 
provided between the N+ region 60 and the N-well 56 to the right. N+ 
regions 60 and 61 are shown in the P- substrate connected to I/O and 
V.sub.DD respectively. In the N- well 56 the N+ regions 62, 64 and P+ 
region 63 are connected respectively to V.sub.dd. The N+ region 66 and the 
P+ region 68 are both connected by line 69 to V.sub.SS. The N+ region 61 
which is connected to source V.sub.DD is the guard ring structure to 
collect the electrons to avoid going through the resistor 58 and the 
resistor 59. The voltage drop in the resistor will turn on the P+/N- well 
to form the P+ region 63, N- well 56, P- substrate 55, N+ region 66 SCR 
path. The guard ring structure efficiency is poor which cannot collect 
most of the electron path where the resistor 58 and resistor 59 are shown 
in the possible electron paths. 
FIG. 3B shows a prior art P- semiconductor substrate 75 with an N-well 
guard ring structure approach to the problem of latchup. The N+ region 80 
is shown in the P- substrate connected to I/O, but unlike FIG. 3A, the N+ 
region 81 is in a new N- well 77 of its own connected to V.sub.DD. In the 
N- well 76 the N+ regions 82, 84 and P+ region 83 are connected. The guard 
ring structure efficiency for the N+ region 81 in an N- well 77 is better 
than when it is N+ only. The resistor 79 is the possible electron path 
which decreases the conductivity provided by the resistors 58 and 59 which 
are shown in FIG. 3A. 
SUMMARY OF THE INVENTION 
Applicants have discovered that lowering the R.sub.W shunting resistance is 
an excellent new approach to improving the relevant parameters. A 
conductor, having a relatively high conductivity (low resistance) is 
placed about the periphery of wells or tubs in the substrate to prevent 
parasitic transistors from causing latchup. 
A MOSFET integrated circuit device comprises a lightly doping a 
semiconductor substrate, with wells formed within the substrate doped with 
an opposite value dopant, forming a plurality of doped regions within the 
surface of the substrate and within the surface of the wells, the 
improvement comprising opening a trench about the periphery of the wells, 
and filling the trench with a relatively highly conductive material. 
In accordance with this invention, a MOSFET integrated circuit device is 
made by the process of fabrication of the MOSFET integrated circuit 
devices, comprising 
a) lightly doping a semiconductor substrate, 
b) forming wells within the substrate doped with an opposite value dopant, 
c) forming a plurality of doped regions within the surface of the substrate 
and within the surface of the wells, 
d) opening trenches along the periphery of the wells, and 
e) filling the trenches with a relatively highly conductive material. 
Preferably, the highly conductive material in the trench is selected from 
polysilicon material and metallic materials. 
Preferably, the dopant is implanted with a dose of more than about E16 
atoms/cm.sup.2, preferably, within the range between about E16 
atoms/cm.sup.2 and about E18 atoms/cm.sup.2. 
Preferably, the dopant is implanted with an energy of greater than about 50 
keV in a high current implanter type of tool. 
Preferably, the trench is etched to a depth on the order of 2-3 .mu.m deep 
and no more than the well depth. 
Preferably, the highly conductive material in the trench comprises a 
polysilicon material or a metallic material, the dopant is implanted with 
a dose of more than about E16 atoms/cm.sup.2, the dopant is implanted with 
an energy of greater than about 50 keV in a high current implanter type of 
tool, and the trench is etched to a depth on the order of 2-3 .mu.m deep 
and no more than the well depth. 
Preferably, the highly conductive material in the trench comprises a 
polysilicon material or a metallic material, the dopant is implanted with 
a dose of between about E16 atoms/cm.sup.2 and about E18 atoms/cm.sup.2, 
the dopant is implanted with an energy of between about 50 keV and about 
100 keV in a high current implanter type of tool, and the trench is etched 
to a depth on the order of 2-3 .mu.m deep and no more than the well depth.

DESCRIPTION OF THE PREFERRED EMBODIMENT 
The instant invention enhances the immunity to latchup thereby achieving a 
major objective of this invention while at the same time reducing the die 
size, and providing greater cost effectiveness than in the prior art. 
FIG. 4 shows an embodiment of the present invention in which the type of 
structure shown in FIG. 3B has been modified by the introduction of 
conductive guard structures 100, 101, 102 and 103 into trenches 95, 96, 98 
and 99 juxtaposed with the interfaces between the bulk of the P- 
semiconductor substrate 85 and the wells 96 and 98 which are connected to 
V.sub.SS by line 89. The trenches are no deeper than the N wells and P 
wells with which they are associated and preferably between about 2 .mu.m 
and about 3 .mu.m deep when the wells are between about 3 .mu.m and about 
4 .mu.m deep. Alternatively, the trenches are between about 1.5 .mu.m and 
about 2.5 .mu.m deep when the wells are between about 2 .mu.m and about 3 
.mu.m deep. The conductive guard structures in the trenches are metal or 
preferably highly doped polysilicon. Within the guard structures 100 and 
101, the N-well 87 protects the N+ region 91. The N+ region 90 is shown in 
the P- substrate connected to I/O, but unlike FIG. 3B, the well 87 is 
improved by rings 100 and 101. In the N- well 86, the N+ regions 92, 94, 
and P+ region 93 are connected respectively to V.sub.dd. The periphery of 
well 86 is improved by the guard structures 102 and 103. 
The guard structures 100 and 101 improve the guard structure efficiency 
which provides a deeper substrate current collector than the N+ region. 
The guard structure 100 and guard structure 101 are filled with highly 
conductive (low resistance) conductor material to reduce the well 
resistance and improve the guard structure efficiency. The guard 
structures 102 and 103 make the N- well resistance lower than the 
conventional value, which improves the latchup immunity. Most of the 
electrons can be collected by the improved well 87 with guard structures 
100 and 101 which reduce the substrate current. 
FIG. 5 is a plan view of the structure shown in FIG. 4 showing the 
configuration of the conductive guard structures 100-103 and the regions 
91, 92, 93, and 94, etc. In this structure, the values are as follows: 
R.sub.S =20-50 ohms/square. 
R.sub.S well.gtoreq.1000 ohms/square 
For an N- substrate, with a minority carrier guard structure, the N and P 
doping values are reversed. In addition, the N+ well, V.sub.DD and P- 
well, V.sub.SS are also reversed. In the case of an N- substrate, the N+ 
is converted to P+, the P+ is converted N+, and N- well is converted to P- 
well, V.sub.DD is converted to V.sub.SS and V.sub.SS is converted to 
V.sub.DD. 
The process of manufacture of a device in accordance with this invention 
comprises the conventional process of forming a MOSFET device modified by 
digging a trench and filling the trench with a conductor composed of metal 
or doped polysilicon comprising conductive guard structures 100-103. 
First, a mask is applied to the surface of the substrate. The mask 
comprises photoresist which is to be patterned to define the trench areas 
in the wells. The photoresist is exposed and developed and then openings 
are etched for the purpose of forming the trenches into which conductive 
guard structures 100-103 are deposited. Next N+ ions are implanted into 
the conductive guard structures 100-103 in the trenches. The chemical 
species of the dopant implanted is selected from the group of dopants 
consisting of phosphorous P31 or Arsenic As75 with a dose of between about 
1E16 atoms/cm.sup.2 about 1E18 atoms/cm.sup.2, at an energy of between 
about 50 keV and about 100 keV. At the end of the etching process, the 
resist is removed by a conventional process. 
In the case of heavily doped polysilicon in the trench, the polysilicon is 
preferably applied by the process of thermal reaction of a liquid source 
of phosphorous dopant POCl.sub.3 or the process of N+ ion implantation. 
The P+ dopant is applied to the P- well and N- sub. 
FIGS. 6A and 6 B illustrate the process required to form the conductive 
guard structures 100-103. 
Referring to FIG. 6A, in the first stage, N-wells 86 and 87 are formed in 
the P- substrate 85. Substrate 85 doped P- is coated with field oxidation 
(FOX) structures 37 over the junctions of the N- wells 86, 87 with the 
remainder of the P- substrate 85 and spaced otherwise along the surface of 
the substrate and N-well 86. A blanket APCVD oxide layer 39 is deposited 
over the FOX structures 37 and the exposed surfaces of the P- substrate 85 
and the exposed surfaces of the N-wells 86 and 87. Next, the structure is 
coated with a layer of photoresist 88. Next trench masking is provided as 
the photoresist is patterned using conventional photolithography to 
develop the photoresist, forming mask openings 95, 96, 98 and 99 in the 
photoresist layer 88. Next an oxide etch of layer 39 and FOX 37, and 
silicon 85 is etched next through the mask openings 95, 96, 98 and 99 down 
into the outer walls of wells 86 and 87 (to form trenches for guard 
structures 100-103 along the borders at the periphery of said N-wells 86 
and 87 as seen in FIG. 6B). 
Referring to FIG. 6B, the photoresist layer 88 has been removed. Metal or 
polysilicon layer 110 is deposited next upon the exposed surface of oxide 
layer 39 and down through the mask openings into the trenches 95, 96, 98 
and 99 to form the guard structures 100-103. Next, as an optional step, 
the polysilicon layer 110 is doped or implanted in a conventional way. 
Next, the polysilicon layer 110 is etched to remove surplus material in a 
conventional way. The subsequent step is that APCVD oxide layer 39 is 
etched. 
A sacrificial oxide step follows. Next a conventional threshold voltage 
(V.sub.T) implantation is performed. A cleaning step is performed followed 
by a gate oxidation step. Next, a conventional polysilicon gate deposition 
is performed. The value of R.sub.W is preferably about three orders of 
magnitude lower in ohms/square than a conventional well R.sub.W with the 
trenches filled with a guard conductor structure of highly conductive 
material. 
The minority carrier guard structure is improved by providing a deeper 
current collector as compared with the N+ or P+ junctions or with a well. 
The improved structure makes R.sub.W lower than the conventional value 
which improves the efficiency of the minority carrier guard structure. 
While this invention has been described in terms of the above specific 
embodiment(s), those skilled in the art will recognize that the invention 
can be practiced with modifications within the spirit and scope of the 
appended claims, i.e. that changes can be made in form and detail, without 
departing from the spirit and scope of the invention. Accordingly all such 
changes come within the purview of the present invention and the invention 
encompasses the subject matter of the claims which follow.