Devices for detecting and/or imaging single photoelectron

A wafer of neutron transmutation doped silicon having a p-n junction between extended opposite surfaces is formed with bevelled edges. A single or plurality of reverse biased signal contacts is disposed on one surface to provide a single or integrated array of avalanche photodiodes. In addition, an avalanche photodetector (APD) capable of detecting a single photoelectron or imaging multiple photoelectrons comprises a light sensitive photocathode, similar to that in a photomultiplier tube, acting as a converter to produce photoelectrons, which are then accelerated to an anode. The anode comprises a single avalanche photodiode (AP) for detecting or an array (APA) for imaging photoelectrons. The energetic photoelectrons striking the AP or the APA serve as the AP or APA's input signal, respectively.

DETAILED DESCRIPTION 
FIG. 1 illustrates a single photoelectron detection device providing with 
an avalanche photodiode formed of a wafer 12 of NTD n-type silicon, about 
7-10 centimeters in diameter. The process for providing NTD silicon is 
well-established. See in this regard the "Special Issue on High-Power 
Semiconductor Devices", i.e., Trans. Electron Devices, ED 23 (1976), in 
particular the article therein by E. W. Haas and M. S. Schnoller, 
"Phosphorus Doping of Silicon by Means of Neutron Irradiation", at 803 
(1976), incorporated herein by reference. A silicon slice having high 
resistivity is irradiated with thermal neutrons. The process gives rise to 
fractional transmutation of silicon into phosphorus and dopes the silicon 
n-type as follows: 
EQU Si.sup.3.sub.1.sup.0.sub.5 +neutron.fwdarw.Si.sup.3.sub.1.sup.1.sub.4 
+.gamma.ray+p.sup.3.sub.1.sup.1.sub.5 +.beta. ray 
with a half life of 2.6 hours. Since the penetration range of neutrons in 
silicon is about a meter, doping is very uniform throughout the slice. For 
example, resistivity variations are about plus or minus 15% for 
conventionally doped silicon and about plus or minus 0.5% for NTD silicon. 
As a result of the neutron transmutation doping process, the silicon wafer 
12 has phosphorous impurities very uniformly distributed throughout its 
bulk. Typically, there are 10.sup.14 to 10.sup.15 phosphorous 
atoms/cm.sup.3 forming an n-type silicon having a resistivity of about 
30-50 ohm-cm. The lower region of the wafer is formed with a p+ layer 14 
defining a p-n junction 16 coplanar with the parallel surfaces of the 
wafer 12. For example, the p+ region can be made by diffusing boron or 
gallium from a gas into the lower surface of the wafer 12 by techniques 
which are well known. The p-type impurities are deep-diffused into the 
surface and a portion is removed from the deeply diffused region in 
accordance with the teachings of Huth et al. U.S. Pat. No. 3,449,177. For 
example, by diffusing boron into the crystal to form a gradient 75 microns 
deep, and then lapping 20-30 microns, and etching 1-0.5 micron, a flat, 
polished, major entrance surface 18 is produced in which the p+ region is 
about 100 microns deep and the p-n junction 16 is about 25 microns thick. 
A non-injecting contact 20 is formed by diffusion of additional n-type 
impurity, such as antimony, into the top major surface 22 of the wafer, 
for example, by use of the well-known planar process or by well known ion 
implantation processes. The element 20 constitutes a circular region of 
n+type silicon. In similar manner, a guard electrode 24 of n++type silicon 
can be formed by diffusion of an impurity such as phosphorus in a ring 
around the element 20. The provision of the guard electrode 24 is of 
course a well known expedient. It is deeper than element 20 and can be 
formed prior to and/or during formation of the guard element 24. 
In the embodiment of FIG. 1, electrical lead wire 23 is connected to 
element 20, for example by thermal compression bonding with a gold silicon 
alloy, or with pure gold wire. Alternatively, the contacts can themselves 
form the element 20 by using a gold-antimony alloy, for example with about 
0.1% antimony, to simultaneously form the heavily doped n+ type region. 
All of these techniques are well known to the art and do not themselves 
form a part of the invention. 
The photodiode of FIG. 1, (as with all the embodiments) is reverse biased 
to provide an avalanche photodiode. The breakdown voltage of such an 
avalanche device is determined by a number of factors, including the depth 
of the p-n junction, and the resistivity of the material. In a typical 
embodiment, the bulk breakdown voltage is in the range from about 1500 to 
200 volts. Premature breakdown along the edge surfaces of the device is 
eliminated by using surface contouring, a technique described in Huth et 
al. U.S. Pat. No. 3,491,272. Such surface contouring is effected in the 
embodiment of FIG. 1 by bevelling the edges of the wafer 12 using simple 
cutting and lapping techniques (See, for example, Huth et al. U.S. Pat. 
No. 3,491,272.) so as to form a positive bevelled structure, i.e., one in 
which the cross-sectional area of the wafer 10 decreases from the heavily 
doped side of the p-n junction 16 (p+region 14) to the more lightly doped 
side (n-type region). In particular, the edge surfaces 26 are bevelled so 
that the angle 28 formed with the plane of the p-n junction 16 and the 
major faces 18 and 22 of the wafer 10, is about 10 degrees. A range from 
about 5 degrees to about 40 degrees is generally useful. The drawing of 
FIG. 1 is, of course, not to scale. 
The positive bevelled contour 26 is illustrative of bevels that may be 
used. The straight bevel shown is a practical contour and can be readily 
obtained by simple cutting and lapping techniques. However, more complex 
contour surfaces related to the shape of the electric field are within the 
scope of construction of the device of FIG. 1. By providing a contoured 
surface 26, the device is made bulk limited rather than surface limited. 
In other words, the peak reverse voltage is limited by the voltage at 
which avalanche breakdown occurs in the interior of the semiconductor 
wafer body, rather than being limited by the peak surface electric field. 
The entrance surface 18 of the wafer can further include a thin, (0.1-0.3 
micron deep) p++ blue enhanced photosensitizing layer diffused into the p+ 
layer 14. This minimizes any "dead layer" to increase UV response to the 
200-300 nm level. Technology for producing even thinner dead layers on 
silicon for far UV detection are known. For example a technique known as 
the "Flash Gate" method comprises applying an extremely thin silicon layer 
covered with a 10 angstrom thick metallic platinum layer to produce 
response in the 100 nm region. Such a technique has been applied to 
charge-coupled 2-dimensional imaging devices for broad wavelength response 
application. With the avalanche techniques of the present invention, 
response is possible for even single photons at energies approaching 100 
eV, or into the "vacuum UV" region. An additional antireflective coating, 
for example formed of silicon oxide, is applied to the p++ layer. 
A front contact ring 34, formed of gold or even conductive epoxy resin, is 
bonded to the lower surface 18 of the device and acts in conjunction with 
the lead 23 from the non-injecting contacts 20 and an applied potential of 
1500-2300 volts, having positive and negative polarities 36 and 38, 
respectively, to create a reverse bias voltage high enough for avalanche 
multiplication to take place. The result is a deep diffused avalanche 
junction and a depletion region, i.e., an avalanche space charge region, 
that spans the p-n junction 16, extending from the avalanche junction to 
the top surface 22 of the wafer 12. A carrier drift region, about 10-25 
microns deep, extends from the photosensitizing layer to the avalanche 
junction and constitutes a pixel plane. The space charge, or avalanche, 
region therefore constitutes a gain plane immediately adjacent the pixel 
plane. 
As indicated in FIG. 1 by the dashed lines 46, the regions of the wafer 12 
below the bevelled edge 26 are inactive, the active portion of the device 
being confined to those regions in line with the element 20. 
Referring to FIG. 1, in essence, the single electron detection device 
utilizes "hybrid" photomultiplication, that is, a "Digicon" type image 
tube in which an avalanche photodiode replaces the no-gain diode normally 
used in such devices. Photodetectors of the Digicon type are fabricated 
using a traditional vacuum/photocathode assembly. High voltage accelerates 
generated photoelectrons into a silicon diode. Essentially the device is 
analogous to an imaging photomultiplier tube using an ordinary 
photocathode as a photon/electron converter on one end and a silicon 
semiconductor photodiode on the other end. The device provides for single 
photoelectron counting capability by applying a voltage of 15-30 kilovolts 
between the photocathode and the silicon diode, achieving an electron gain 
of from 5.times.10.sup.3 to 10.sup.4. Dynamic range is a serious 
limitation in Digicon type devices with limits set by the noise background 
(i.e., counts detected by the diode with no optical signal incident) of 
about 10 counts per second to a maximum count rate of about 10.sup.4 
counts per second. The upper limit is set by the slow collection time of 
the diode used thus far, which is an ordinary, non-amplifying silicon 
photodiode, and the necessarily slow, charge sensitive electronic 
preamplification that must therefore be used. Radiation damage in the 
silicon diode caused by the interaction of the electrons accelerated by 
these very high voltages is a serious problem and one which limits the 
life of the detector, currently to only about 10.sup.12 counts per diode 
image element. 
For example, with a Digicon, in order to generate a measurable signal from 
an initial single photoelectron (from an optical photon interaction), the 
detector employs an acceleration voltage of 20-30 kilovolts within its 
enclosed vacuum. The signal generated is calculated in electron-hole pairs 
by dividing the voltage by approximately 3 eV/electron-hole pair. 
Therefore, under an acceleration of say 20 kilovolts, about 5500 
electron-hole pairs are generated. Such a signal level is at just about 
the noise limit of a room temperature operated diode with associated 
charge sensitive preamplification electronics. Voltages greater than 20 
kilovolts are often employed to get useful signal levels from the 
detector. While the Digicon is an extraordinary device, with a tremendous 
optical detection capability, elaborate components are needed to provide 
magnetic focusing and deflection and it has all the limitations that have 
been previously referred to herein, attributable to the requirement that 
very high voltage levels be used. 
Because of the multiplication obtained by the avalanche photodiode of the 
present invention, a hybrid, Digicon-type device can be constructed which 
obtains an equivalent generation of electron-hole pairs but at only a 
fraction of the voltage, i.e., about 3-5 kilovolts. Alternatively, the 
hybrid device can maintain the detector voltage at the 20 kilovolt level 
with the resultant signal level being as high as 5.5.times.10.sup.6 
electron-hole pairs. Such a large output signal can have many 
ramifications, among which are a general simplification of associated 
electronics. Noise in the low level output of non-gain diodes effectively 
"smears out" resolution between diode elements and is a limiting factor. 
For example, at the 20-kilovolt range, the magnitude of the scattering 
distance of electrons in a silicon diode becomes about 25-50 micrometers, 
which is close to the measured resolving power of the Digicon detector. 
Since the signal level determines the ultimate spatial resolving power in 
high density arrays, the spatial resolving power of the device can be 
raised by this invention to a few micrometers from the current 20-100 
micrometer level. 
Referring more specifically to FIG. 1, the hybrid, Digicon-type device of 
this invention includes on the "Digicon side" a flat, optical glass face 
plate 102, carrying on its top surface a photocathode layer 104, 
separated, but closely spaced from, the entrance surface 18 of the 
avalanche photodiode by means of a ceramic insulator ring 106. High 
voltage electrode rings 108 and 110 are disposed respectively between the 
photocathode surface 104 and insulator ring 106 and between the insulator 
ring 106 and entrance surface 18 of the avalanche photodiode array wafer 
12. The distance obtained between the photocathode surface 104 and the 
entrance surface 18 of the avalanche wafer 12, for example, about a 
millimeter is sufficiently small to enable simple proximity focussing. 
A third high voltage electrode ring 114 is disposed to contact the top 
surface 22 of the avalanche photodiode wafer 12 and is supported on and 
spaced from the middle high voltage electrode 110 by means of a ceramic 
insulator ring 116. Leads 23 from element 20 is connected at the center B 
to pulse detection electronics 120 which includes amplifiers, 
discriminators, counters, etc., all as known in the Digicon art. The 
nature of the optical glass 102 and associated photocathode surface 104, 
method of association, and the photodetection electronics, are well known 
to the art and do not themselves form a part of the invention. 
The composite, hybrid structure is clamped or otherwise secured and, during 
construction, a vacuum is applied so that there is a vacuum between the 
photocathode surface 104 and avalanche wafer entrance surface 18. 
"Dead layer" considerations at the front surface of the avalanche 
photodiode require that the input electron be accelerated so as to have a 
range in silicon of about 1 micrometer, requiring a voltage range of about 
3-5 kilovolts. In this regard, as previously indicated, "Flash Gate" 
technology has been developed to provide high quantum efficiencies in the 
visible and extended blue regions of the optical spectrum wherein 
photoabsorption is of the same depth of a micrometer, or less. 
As indicated in FIG. 1, in an exemplary embodiment, a voltage of 5 KV is 
applied across the lower high voltage electrode rings 108 and 110 to 
accelerate electrons from the photocathode surface 104, providing as a 
result of that acceleration, about 1.4.times.10.sup.3 electron-hole pairs. 
A voltage of 6.5 KV is applied to the top high voltage electrode 114 with 
respect to the bottommost electrode 10B, resulting in an internal 
avalanche gain of about 10.sup.3, for a total gain of approximately 
1.4.times.10.sup.6. 
FIGS. 2a-c summarize the response of a discrete avalanche hybrid single 
electron device at 5, 7.5 and 10 kV electron acceleration voltages, 
respectively. The responses are measured with a discrete silicon avalanche 
photodetector. Photoelectrons are accelerated onto the discrete avalanche 
detector using proximity focusing at the acceleration voltages. Upon 
impact, electron-hole pairs are generated, one electron-hole pair is 
produced for each 3.6 eV of energy lost by the photoelectron in the diode. 
Each current pulse generated by a photoelectron is amplified by a 
charge-sensitive preamplifier and is counted in a digital sense or a 
photoelectron event if it exceeds a preset discriminator threshold level. 
A "pulse-height distribution" is formed by converting the photoelectron 
pulse after amplification into an analog voltage by an analog-to-digital 
converter (ADC). The output of the ADC provides a numerical representation 
of the height (or magnitude) of the photoelectron pulse. The digital 
pulse-height representations of all the pulses are then sorted by 
magnitude into different channels and the number of counts 
(photoelectrons) is then plotted as a function of channel number. 
As shown in FIGS. 2a-c, the pulse-height distribution for the discrete 
silicon avalanche photodetector at various photoelectron acceleration 
voltages are characterized by three major regions, viz. the single 
electron peak 1, the low energy electronic noise portion 2 and the valley 
3 therebetween where the discriminator level is set. 
The single electron peak 1, which represents incident electrons that 
release their full energy within the avalanche photodiode, is shifted 
towards higher channel numbers in FIGS. 2a-c as the photoelectron 
acceleration voltage increases from 5 to 10kV. Counts occurring between 
the electronic noise distribution and the single electron peak caused by 
incident electrons falling on the avalanche photodiode peripheries and by 
electron back scatter from the avalanche photodiode also increase as the 
photoelectron acceleration voltage increases from 5 to 10 kV. In both 
situations, only a portion of the incident electron's energy is collected 
by the avalanche photodiode and is manifested as a lower-magnitude 
pulse-peak value. 
Referring to FIG. 3, a device utilizing hybrid photomultiplication, in 
essence a "Digicon" type image tube, in which an avalanche photodiode 
array 10 (APA) is used to replace the no-gain diode array normally used in 
such devices. The APA is similar to the discrete avalanche photodiode 
except with a plurality of non-injecting contacts 20 on the top region 
surface 22 of the wafer. The photolithographic technique used with such 
processes permit a very large number of signal contacts 20 to be arranged 
as an array on the top surface 20 of the wafer, each signal contact 
defining an array element and electrical lead wires 23 and connected to 
each individual array element 20. 
The result is an array with the capability of massive parallel readout. In 
this regard, reference can be made to the article "Digicons in Space" in 
the Sept., 1980 issue of Electro-Optical Systems Design, pp. 29-37, 
incorporated herein by reference, where there is described an image tube, 
referred to as a Digicon using a diode array of 512 elements. The 
embodiment of FIG. 3, in which 512 array elements are formed through the 
top surface of the wafer 12, can readily substitute for that diode array, 
as will be described in more detail below. 
The simple nature of the wafer structure used in the embodiment of FIG. 3 
and the extremely high uniformity obtained by the NTD process, permits the 
formation of a diode array that is limited only by photolithographic 
techniques and the ability to physically arrange for the parallel 
disposition of individual output contact wires 23. 
Similar to the discrete device, a carrier drift region about 10-25 microns 
deep extends from the photosensitizing layer to the avalanche junction 
constitutes a pixel plane. The size of the pixels in the pixel plane is 
defined by the minimum distance 48 between the array elements, which, in 
turn, is determined by the resolution obtained by the diffusion or ion 
implantation step used to form the elements 20 as well as the avalanche 
spreading factor. As a result, devices can be constructed having pixel 
dimensions smaller than the 100 .mu.m value which is about the practical 
limit of charge coupled device technology. 
The angular spatial resolution is a function of a number of factors such as 
the number and spacing of the silicon diodes (currently the smallest 
spacing being on 100 micrometer centers) and the high voltage applied to 
accelerate the photoelectrons into the silicon array. 
Furthermore, the APA wafer 12 is as described similar to FIG. 1. The 
avalanche photodiode array wafer 12 is as described with respect to FIG. 
1, except that a plurality of p++regions 112 may be formed, e.g., by 
diffusion or ion implantation of boron, into the p+ region 14. The p++ 
regions 112 serve as "acceptors" for electrons accelerated from the 
photocathode layer. The p++regions 112 can be as numerous as the n+ array 
element 20 to maintain spatial resolution, but mutual alignment between 
the p++ regions 112 and array elements 20 is not required. Leads 23 from 
the array elements 20 are connected to a bus 118 which, in turn, is 
connected to pulse detection electronics 120. 
Referring to FIG. 4, a particular application of a coarse array structure 
is illustrated, obtained by separating four of the isolated coarse array 
diodes 33 integrally disposed in quadrature array. Here also, a wafer 12 
of NTD n-type silicon is the starting material in which there is provided 
a p+region 14 by techniques identical to that referred to above with 
respect to the embodiment of FIGS. 1 and 3. Other aspects of the 
embodiments of FIGS. 1 and 3 are applicable here, for example, the 
provision of a photosensitizing layer 30 and antireflective coating, but 
which for simplicity are not illustrated. The major difference between the 
coarse array of FIG. 4 and the denser array of FIGS. 1 and 3 is the 
isolation of individual photodiodes 33 by the application of a gridwork of 
bevelled edges 26' which are similar to the outer edge bevel 26 and in 
which the angle formed with p-n junction 16 is also the same. In 
particular, array elements 20 along with associated leads 23 are formed in 
the manner referred to with respect to FIG. 3, but they are less closely 
packed. The wafer is cut through in a gridded pattern by means of a 
diamond wheel, or other cutting device, to form the positive bevels 26'. 
The bevelling of the wafer 12 is conducted so as to just cut through the 
p-n junction 16, thereby isolating each of the photodiodes 33 defined by 
the contacts 20. A plurality of junctures 52 are formed criss-crossing the 
wafer, isolating the individual diodes 33. With each photodiode 33, there 
is an active region 54 directly beneath the contact 20, delineated in the 
drawing of FIG. 3 by the dashed lines 46 adjacent the outer edge and 
internally by the dashed lines 56. Details of the entrance surface 18 of 
the coarse array device of FIG. 4 are the same as depicted in FIG. 3. The 
electrical leads 23 from each n+ region 20 are connected to a feedback 
mechanism 121 which in turn is connected to an imaging system including a 
lens or semiconductor laser 122. The feedback mechanism and method of 
connection, and the imaging system and lens or laser 122 are all in 
accordance with techniques that are well known to the art and do not 
themselves form a part of the invention. 
Analogous to the hybrid part solid state Digicon device in FIG. 3, the 
quadrature device uses an ordinary photocathode as a photon/electron 
connecter in one end and a silicon semiconductor photodiode array on the 
other end. 
Referring more specifically to FIG. 4, in operation, a light beam 124 from 
the lens or suitably disposed laser 122, is centered at the juncture 126 
common to the four photodiodes 33. As the beam moves off center, it 
generates a signal to the leads 23 which is fed back to the controlling 
mechanism for an adjustment in the appropriate direction to recenter the 
beam 124. 
Referring to FIG. 5, a quadrature array is shown which functions in the 
same manner as the device of FIG. 1, but in which the array elements 20 
are obtained from the avalanche photodiode array wafer 12 of FIG. 3. Four 
such elements 20 disposed in quadrature array are isolated and cut from 
the wafer 12 so as to be provided with bevelled surfaces 26'. Here, too, 
the device includes a p+region 14, but a common p-n junction 16. Analogous 
to the hybrid part solid state Digicon device in FIG. 3, the quadrature 
device uses an ordinary photocathode as a photon/electron connector on one 
end and a silicon avalanche photodiode array on the other end. In 
operation, analogous to the quadrature coarse array structure, a light 
beam 124 from a lens or semiconductor laser 122 is applied to the junction 
126' centrally disposed between the four array elements 20. Signals 
obtained from the leads 23 are applied to the feedback mechanism 121 in 
the manner described with respect to the coarse quadrature array of FIG. 
4. 
It will be appreciated that the foregoing embodiments illustrate various 
applications of the silicon avalanche photodiode and photodiode array 
structure and that other applications and combinations are possible. It is 
understood that changes and variations can be made therein without 
departing from the scope of the invention or defined in the following 
claims.