MOS transistor process

A MOS transistor process includes the following steps. A gate structure is formed on a substrate. A source/drain is formed in the substrate beside the gate structure. After the source/drain is formed, (1) at least a recess is formed in the substrate beside the gate structure. An epitaxial structure is formed in the recess. (2) A cleaning process may be performed to clean the surface of the substrate beside the gate structure. An epitaxial structure is formed in the substrate beside the gate structure.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a MOS transistor process, and more specifically to a MOS transistor process, that forms a recess and/or performs a cleaning process after a source/drain is formed and before an epitaxial structure is formed.

2. Description of the Prior Art

For decades, chip manufacturers have made metal-oxide-semiconductor (MOS) transistors faster by making them smaller. As the semiconductor processes advance to very deep sub micron era such as 65-nm node or beyond, how to increase the driving current of MOS transistors has become a critical issue. In order to improve device performances, crystal strain technology has been developed. Crystal strain technology is becoming more and more attractive as a mean for reaching better performances in the field of CMOS transistor fabrication. Putting a strain on a semiconductor crystal alters the speed at which charges move through that crystal. Strain makes CMOS transistors work better by enabling electrical charges, such as electrons, to pass more easily through the silicon lattice of the gate channel.

In the known arts, attempts have been made to use a strained silicon layer, which has been grown epitaxially on a silicon substrate with an epitaxial structure such as a silicon germanium (SiGe) structure or a silicon carbide (SiC) structure disposed in between. In this type of MOS transistor, a biaxial compressive or tensile strain occurs in the epitaxial structure due to the silicon germanium or the silicon carbide which has a less or larger lattice constant than silicon, and, as a result, the band structure is altered, and the carrier mobility increases. This enhances the speed performance of the MOS transistors.

However, ingredients in the epitaxial structure such as germanium or carbon etc would diffuse outwards when induced by high temperature or ion implantation etc, thereby decreasing the concentration of the ingredients in the epitaxial structure, and degrading the performance of the epitaxial structure. Moreover, the qualities of the surface of a substrate having the epitaxial structure formed thereon will also affect the shape or the cross-sectional profile etc. of the epitaxial structure, which would affect the performances of formed semiconductor component.

SUMMARY OF THE INVENTION

The present invention provides a MOS transistor process, which forms epitaxial structures after source/drains are formed, and forms recesses or performs a cleaning process after the source/drains are formed and before the epitaxial structures are formed, so that the performances of the epitaxial structures can be improved.

The present invention provides a MOS transistor process including the following steps. A gate structure is formed on a substrate. A source/drain is formed in the substrate beside the gate structure. At least a recess is formed in the substrate beside the gate structure after the source/drain is formed. An epitaxial structure is formed in the recess.

The present invention provides a MOS transistor process including the following steps. A gate structure is formed on a substrate. A source/drain is formed in the substrate beside the gate structure. A cleaning process is performed to clean the surface of the substrate beside the gate structure after the source/drain is formed. An epitaxial structure is formed in the substrate beside the gate structure.

According to the above, the present invention provides a MOS transistor process, which forms source/drains, forms recesses and/or performs a cleaning process, and then forms epitaxial structures. This way, outward diffusion of the ingredients in the epitaxial structures caused by a source/drain ion implantation process and a source/drain annealing process for forming the source/drains can be avoided, that would decrease stresses forcing gate channels from the epitaxial structures and lead to circuit leakages in the gate channels. Moreover, the recesses are formed, or the cleaning process is performed, after the source/drains are formed, so that the substrate damaged during processes such as processes for forming source/drains, or impurities on the substrate can be removed, thereby improving the performances of the epitaxial structure formed on the substrate.

DETAILED DESCRIPTION

The MOS transistor process of the present invention can be applied in a gate-first process, a gate-last for high-k first process or a gate-last for high-k last process etc. Moreover, planar MOS transistors are used as an example in the following, but the present invention can also be applied to non-planar MOS transistors such as Multi-gate MOSFETs like fin-shaped field effect transistors (FinFET) or tri-gate MOSFETs. One embodiment is presented later, wherein planar MOS transistors use a gate-last for high-k first process, but it is not limited thereto.

FIGS. 1-8schematically depict cross-sectional views of a MOS transistor process according to an embodiment of the present invention. As shown inFIG. 1, a substrate110is provided. The substrate110may be a semiconductor substrate such as a silicon substrate, a silicon containing substrate, a III-V group-on-silicon (such as GaN-on-silicon) substrate, a graphene-on-silicon substrate or a silicon-on-insulator (SOI) substrate. An isolation structure10is formed in the substrate110to electrically isolate transistors in each area. The isolation structure10may be a shallow trench isolation (STI) structure formed by methods such as a shallow trench isolation (STI) process. The details of the methods for forming the shallow trench isolation (STI) structure are known in the art, and won't be described herein. In this embodiment, two transistors M1 and M2 having a common source or a common drain are formed in an area A, but it is not limited thereto. In another embodiment, a single transistor or a plurality of transistors with no common sources or common drains may be formed in the area A.

In aforesaid embodiment, the buffer layer122is an oxide layer, which may be formed by a thermal oxide process or a chemical oxide process, but it is not limited thereto. The buffer layer122is located between the dielectric layer124and the substrate110to buffer the dielectric layer124and the substrate110. The buffer layer122may be selectively formed depending upon the materials of the dielectric layer124and the substrate110, and the electrical performances of formed semiconductor components. For example, a gate-last for high-k first process is used in this embodiment, the dielectric layer124is therefore a dielectric layer having a high dielectric constant, such as the group selected from hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalite (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT) and barium strontium titanate (BaxSr1-xTiO3, BST), but it is not limited thereto. The material difference between the dielectric layer124and the substrate110can therefore be buffered by the buffer layer122. In another embodiment, if a gate-last for high-k last process is applied, the dielectric layer124may be directly formed on the substrate110, wherein the dielectric layer124may be an oxide layer, which will be removed in a later process, and then the buffer layer122is formed on the substrate110after the dielectric layer124is removed during a metal gate replacement process. The buffer layer122may be formed on the substrate110before the dielectric layer124is formed, so that only the dielectric layer124needs to be removed during the metal gate replacement process, without removing the buffer layer122. In another way, when a polysilicon transistor is formed, the dielectric layer124can be an oxide layer, so that the buffer layer122and the barrier layer126may not need to be formed.

The barrier layer126is located on the dielectric layer124to be an etching stop layer for protecting the dielectric layer124from being damaged while the electrode layer128is removed, and to prevent metals formed on the barrier layer126from diffusing downwards and pollute the dielectric layer124. The barrier layer126maybe a single layer structure or a multi-layer structure composed of materials such as tantalum nitride (TaN) or titanium nitride (TiN) etc. The electrode layer128may be a sacrificial electrode layer composed of materials such as polysilicon, which may be replaced by a metal gate in later processes, but it is not limited thereto. The cap layer129may be a single layer or a stacked structure composed of layers such as a nitride layer or an oxide layer etc. The cap layer129can prevent layers beneath such as the electrode layer128from being damaged in later etching processes, so the materials of the cap layer129may depend upon the parameters of the etching processes such as the etchant of the etching processes. The main spacer130may be a single layer or a multilayer structure composed of layers such as a nitride layer, an oxide layer or the combination of both, but it is not limited thereto.

As shown inFIGS. 2-3, a source/drain140is formed in the substrate110beside each of the gate structures G1and G2. In details, as shown inFIG. 2, a source/drain ion implantation process P1is performed to automatically align and form an implanted region140′ in the substrate110beside each of the gate structures G1and G2by the main spacers130. As shown inFIG. 3, a source/drain annealing process P2is performed to activate the implanted regions140′, so that the source/drain140can be formed in the substrate110beside each of the main spacers130. Furthermore, a liner spacer (not shown) may be selectively formed on the substrate110beside each of the gate structures G1and G2before the main spacers130s are formed, and then a lightly doped source/drain (not shown) is automatically aligned and formed in the substrate110beside each of the liner spacers (not shown).

The main spacer130is removed, so that the sidewalls of the gate structures G1and G2are exposed as shown inFIG. 4. Due to the source/drains140being automatically aligned and formed by the main spacers130, a distance d1between the source/drain140and each of the gate structures G1and G2is equal to the width w1of the main spacer130as shown in aforementioned figures. That means the distance d1van be controlled by adjusting the width w1of the main spacer130. In this embodiment, the main spacer130is entirely removed; but in another embodiment, the main spacer130may be partially removed or not removed. Then, an epitaxial spacer may be formed later on the substrate110beside the remaining main spacer130.

As shown inFIGS. 5-6, an epitaxial spacer150is formed on the substrate110beside each of the gate structures G1and G2. In details, as shown inFIG. 5, an epitaxial spacer material150′ may be formed to cover the gate structures G1and G2and the substrate110. As shown inFIG. 6, an etching process P3is performed to etch the epitaxial spacer material150′ and an epitaxial spacer150is therefore formed on the substrate110beside each of the gate structures G1and G2. In this embodiment, not only the epitaxial spacer material150′ is etched during the etching process P3, but also recesses R are formed in the substrate110beside the epitaxial spacers150. Thus, part of the substrate110being crystalline damaged can be removed in said processes, especially in the source/drain ion implantation process P1, as the recesses R are formed. For instance, as the depth of the implanted region140′ formed by performing the source/drain ion implantation process P1is 50 Å (angstroms), the depth of the recesses R is preferred to be 50˜65 Å (angstroms). Therefore, the damage part of the substrate110can be removed, enabling epitaxial structures being formed in the recesses R having an undamaged surface and the epitaxial structures will have better shapes and better cross-sectional profiles. In another embodiment, the recesses R and the epitaxial spacers150maybe formed by different etching processes, and the depth of the recesses R depends upon the needs such as the materials or the characteristics of the formed epitaxial structures. For instance, as the epitaxial structures are carbon containing silicon phosphorus (SiCP) epitaxial structures, the depth of the recesses R is preferred to be 400˜500 Å (angstrom). Moreover, a width w2of the epitaxial spacers150will determine the distance between the epitaxial structures formed in the substrate110beside the epitaxial spacer150and the gate structures G1and G2in later processes. In this embodiment, the width w2of the epitaxial spacers150is narrower than the width w1of the main spacers130as shown in previous figures, so that the epitaxial structures formed in later processes can be closer to the gate channels C1and C2. This way, stresses forcing the gate channels C1and C2from the epitaxial structures can be increased, while the source/drains140are prevented from being too close to the gate channels C1and C2, which would cause an electron tunnel effect and induce circuit leakages.

In another embodiment, the distance between the epitaxial structures and the gate channels C1and C2and the distance between the source/drains140and the gate channels C1and C2can be adjusted according to the needs. The adjusting methods may include the following steps. The distance between the source/drain140and the gate channels C1and C2can be decided by the width w1of the mainspacers130. Then, the main spacers130are removed partially or entirely, or the main spacer130may not be removed, and then the epitaxial spacers150can be formed on the substrate110at the original position of the main spacers130and/or beside the main spacers130. So, the distance between the epitaxial structures and the gate channels C1and C2can be controlled by the remaining main spacers130and the width w2of the epitaxial spacers150.

As shown inFIG. 7, a cleaning process P4is performed to clean the surface S of the recesses R, to remove impurities such as residues or native oxides etc, so that the epitaxial structures formed in the recesses R can have better shapes and cross-sectional profiles, and the formed semiconductor component can achieve better performances. The cleaning process P4may include a Standard Clean1(SC1) process and/or a dilute hydrofluoric acid containing cleaning process. In an embodiment, a Standard Clean1(SC1) process is performed to oxidize the surface S of part of the recesses R, and then a dilute hydrofluoric acid containing cleaning process is performed to remove oxide and other impurities on the surface S and repair the surface S of the recesses R, but it is not limited thereto. In this embodiment, a first Standard Clean1(SC1) process, a dilute hydrofluoric acid containing cleaning process and a second Standard Clean1(SC1) process are sequentially performed. Specifically, the first Standard Clean1(SC1) process is firstly performed, wherein the first Standard Clean1(SC1) process is a “multi-wafer at once” cleaning process, and the processing temperature of the first Standard Clean1(SC1) process is 70° C. and the processing time is 60 seconds; then, the dilute hydrofluoric acid containing cleaning process and the second Standard Clean1(SC1) process are sequentially performed, wherein the dilute hydrofluoric acid containing cleaning process and the second Standard Clean1(SC1) process are “one wafer at once” cleaning processes, and the processing time of the dilute hydrofluoric acid containing cleaning process is 15 seconds, and the processing temperature of the second Standard Clean1is 60° C. and the processing time is 90 seconds.

As shown inFIG. 8, an epitaxial process P5is performed to form an epitaxial structure160in each of the recesses R. The epitaxial structure160may be a silicon phosphorus (SiP) epitaxial structure, a silicon germanium (SiGe) epitaxial structure or a carbon containing silicon phosphorus (SiCP) epitaxial structure, but it is not limited thereto. The structure depends upon the types of formed transistors. In this embodiment, the epitaxial structure160is a silicon phosphorus (SiP) epitaxial structure of an NMOS transistor. The ingredients in the epitaxial structure160, such as phosphorus, is eager to diffuse outwards, which means that the ingredients in the epitaxial structure160, such as phosphorus, have high sensitivities with ion implantations or high temperatures. The epitaxial structure160are formed after the source/drains140are formed, so that the epitaxial structures160will not suffer the affection of the source/drain ion implantation process P1and the source/drain annealing process P2. Therefore, the ingredients in the epitaxial structures160can be prevented from diffusing outwards, which would reduce the stresses applied on the gate channels C1and C2from the epitaxial structures160, and lead to circuit leakages. Moreover, there may be dopants doped into the epitaxial structures160to induce the epitaxial structures160to be conductive, wherein the dopants may be boron or phosphorus etc, depending upon the electrical types. The dopants may be in-situ doped into the epitaxial structures160during the epitaxial process P5. The dopants may diffuse into the epitaxial structures160from the source/drains140; or they may be ion implanted into the epitaxial structures160after the epitaxial structures160are formed.

Above all, in the present invention, the recesses R are formed in the substrate110beside the gate structures G1and G2after the source/drains140, the cleaning process P4is performed to clean the surface S of the recesses R, and then the epitaxial structures160are formed. By doing this, the epitaxial structures160suffering from the damages of the ion implantation process of the source/drains140and form the high temperature of the annealing process of the source/drains140can be avoided. Moreover, the recesses R formed after the source/drains140can remove the damaged substrate110during the processes such as processes for forming the source/drains140, thereby improving the performances of the epitaxial structures160formed in the recesses R. Furthermore, the cleaning process P4is performed after the recesses R are formed, so that the surface S of the recesses R can be cleaned, and the performances of the epitaxial structures160formed in the recesses R can be improved.

However, the steps of forming the source/drains140, forming the recesses R, performing the cleaning process P4, and forming the epitaxial structures160are just one embodiment of the present invention. Since forming the recesses R and performing the cleaning process P4can improve the surface quality of the substrate110, thereby improving the performances of the epitaxial structures160, the recesses R formation only or the cleaning process P4only may be carried out after the source/drains140are formed and before the epitaxial structures160are formed, in order to achieve the purposes of the present invention. However, it is preferred to form the recesses R and then perform the cleaning process P4to obtain better performances of the epitaxial structures160.

To summarize, the present invention provides a MOS transistor process, which forms source/drains, forms recesses and/or performs a cleaning process, and then forms epitaxial structures. This way, outward diffusion of the ingredients in the epitaxial structures caused by a source/drain ion implantation process and a source/drain annealing process for forming the source/drains can be avoided, which would decrease the stresses forcing gate channels from the epitaxial structures and lead to circuit leakages in the gate channels. Moreover, the recesses may be formed after the source/drains are formed, so that the substrate damaged during processes, such as processes for forming source/drains, are removed, thereby improving the performances of the epitaxial structures formed in the recess. A cleaning process may be performed after the source/drain are formed, so that impurities on the surface of the substrate can be removed, thereby improving the performances of the epitaxial structure formed on the substrate. Preferably, the recess is formed and then the cleaning process is performed, after the source/drains are formed and before the epitaxial structures are formed.