Low-power approximate DPD actuator for 5G-new radio

Systems and methods are disclosed herein for providing efficient Digital Predistortion (DPD). In some embodiments, a system comprises a DPD system comprising a DPD actuator. The DPD actuator comprises a Look-Up Table (LUT), selection circuitry, and an approximate multiplication function. Each LUT entry comprises information that represents a first set of values {p1, p2, . . . , pk} and a second set of values {s1, s2, . . . , sk} that represent a LUT value of s1·2p+s2·2p+ . . . +sk·2pwhere each value si∈{+1,−1} where k≥2. The selection circuitry is operable to, for each input sample of an input signal, select a LUT entry based on a value derived from the input sample that is indicative of a power of the input signal. The approximate multiplication function comprises shifting and combining circuitry that operates to, for each input sample, shift and combine bits that form a binary representation of the input sample in accordance with {p1, p2, . . . , pk} and {s1, s2, . . . , sk} to provide an output sample.

TECHNICAL FIELD

The present disclosure relates to Digital Predistortion (DPD) to compensate for power amplifier non-linearities in a radio device.

BACKGROUND

Power Amplifiers (PAs) are the most dominant source of distortion in a radio system (Morgan et al., “A Generalized Memory Polynomial Model for Digital Predistortion of RF Power Amplifiers,” IEEE Transactions on Signal Processing, Vol. 54, No. 10, pages 3852-3860, October 2006). Digital Predistortion (DPD) is a frequently used technique to compensate the power consumption of a PA. The DPD reduces the power/energy footprint by reducing nonlinear distortion introduced by PAs and enhances the power efficiency of the PA by allowing the PA to operate in its non-linear region. However, the digital pre-distorter itself consumes a major portion of power for the digital part. A typical digital pre-distorter is composed of a forward path and an adaptation path. In Third Generation Partnership (3GPP) Fifth Generation (5G) radios containing tens of PAs, the forward path is the main source of power since, firstly, the forward path has to be replicated for all PAs and, secondly, the forward path is always active. As such, there is a need for systems and methods for providing DPD in a manner that reduces power consumption.

SUMMARY

Systems and methods are disclosed herein for providing efficient Digital Predistortion (DPD). In some embodiments, a system comprises a DPD system for digitally predistorting an input signal to provide a predistorted output signal. The DPD system comprises a DPD actuator, where the DPD actuator comprises a Look-Up Table (LUT), selection circuitry, and an approximate multiplication function. The LUT comprises a plurality of LUT entries, where each LUT entry comprises information that represents a first set of values {p1, p2, . . . pk} and a second set of values {s1, s2, . . . , sk} that together represent a LUT value of s1·2p1+s2·2p2+ . . . +sk·2pkwhere each value si∈{+1, −1} for all i=1, 2, . . . , k and k≥2. The selection circuitry is operable to, for each input sample of a plurality of input samples of the input signal, select a LUT entry from among the plurality of LUT entries comprised in the LUT based on a value derived from the input sample that is indicative of a power of the input signal. The approximate multiplication function comprises shifting and combining circuitry that operates to, for each input sample of the plurality of input samples of the input signal: for each value piin the first set of values {p1, p2, . . . , pk} for the selected LUT entry, shift a plurality of bits that form a binary representation of the input sample by pibit positions to provide a respective shifted value; and combine the shifted values using additions and subtractions in accordance with signs defined by the second set of values {s1, s2, . . . , sk} to thereby provide a binary representation of an output sample. In this manner, an efficient DPD actuator is provided.

In some embodiments, the DPD system further comprises an adaptor that operates to update the plurality of LUT entries in the LUT.

In some embodiments, the adaptor comprises a modification function and a LUT conversion function operable to generate a plurality of initial LUT values to be approximated by the information stored in the plurality of LUT entries, wherein the modification function is operable to approximate each of at least some input values of the LUT conversion function as either a power of 2 value or a combination of two or more power of 2 values.

In some embodiments, k≥2. In some other embodiments, k=3.

In some embodiments, the input signal is a complex signal having a real component and an imaginary component, and the plurality of input samples of the input signal is a plurality of input samples of the real component of the input signal or a plurality of input samples of the imaginary component of the input signal.

In some embodiments, the system further comprises transmitter circuitry operable to upconvert, filter, and amplify the output signal prior to transmission, wherein the DPD system operates to compensate for a non-linear characteristic of a Power Amplifier (PA) comprised in the transmitter circuitry.

In some embodiments, the adaptor comprises an adaptation function, a LUT conversion function, and an approximation function. The adaptation function is operable to compute a desired DPD characteristic based on a comparison of the input signal and a feedback signal, the feedback signal being from an output of a respective PA. The LUT conversion function is operable to, for each LUT entry, compute an initial LUT value for the LUT entry based on the desired DPD characteristic. The approximation function is operable to, for each LUT entry, compute the first set of values {p1, p2, . . . , pk} and the second set of values {s1, s2, . . . , sk} for the LUT entry such that s1·2p1+s2·2p2+ . . . +sk·2pkis an approximation of the initial LUT value for the LUT entry.

In some embodiments, the DPD actuator comprises a plurality of memory tap branches each comprising a separate LUT, a separate select circuitry, and a separate approximate multiplication function. Each output sample of the output signal is provided as a sum of output samples from the plurality of memory tap branches for a respective input sample of the input signal.

In some embodiments, the approximate multiplication function comprises a shifter, an adder/subtractor, and an accumulation register. The shifter, the adder/subtractor, and the accumulation register are controlled to generate and combine the shifted values in a serial manner in accordance with the first set of values {p1, p2, . . . , pk} and the second set of values {s1, s2, . . . , sk} for the selected LUT entry.

In some embodiments, the system is a transmitter of a radio node in a cellular communications network.

Embodiments of a method for digitally predistorting an input signal to provide a predistorted output signal are also disclosed. In some embodiments, a method for digitally predistorting an input signal to provide a predistorted output signal using a DPD actuator comprising a LUT comprising a plurality of LUT entries, wherein each LUT entry comprises information that represents a first set of values {p1, p2, . . . , pk} and a second set of values {s1, s2, . . . , sk} that together represent a LUT value of s1·2p1+s2·2p2+ . . . +sk·2pkwhere each value si∈{+1, −1} for all i=1, 2, . . . , k and k≥2, is provided. The method comprises, for each input sample of a plurality of input samples of the input signal: selecting a LUT entry from among the plurality of LUT entries comprised in the LUT based on a value derived from the input sample that is indicative of a power of the input signal; for each value piin the first set of values {p1, p2, . . . , pk} for the selected LUT entry, shifting a plurality of bits that form a binary representation of the input sample by pibit positions to provide a respective shifted value; and combining the shifted values using additions and subtractions in accordance with signs defined by the second set of values {si, s2, . . . , sk} to thereby provide a binary representation of an output sample that is an approximation of a multiplication of the input sample and a desired DPD value represented by the LUT entry.

In some embodiments, the method further comprises adapting the plurality of LUT entries in the LUT.

In some embodiments, adapting the plurality of LUT entries in the LUT comprises generating input values based on a feedback signal, approximating each of at least some of the input values as either a power of 2 value or a combination of two or more power of 2 values, and generating a plurality of initial LUT values to be approximated by the information stored in the plurality of LUT entries based on the at least some input values.

In some embodiments, k≥2. In some other embodiments, k=3.

In some embodiments, the input signal is a complex signal having a real component and an imaginary component, and the plurality of input samples of the input signal is a plurality of input samples of the real component of the input signal or a plurality of input samples of the imaginary component of the input signal.

In some embodiments, the method further comprises, in transmitter circuitry, upconverting, filtering, and amplifying the output signal prior to transmission, wherein the DPD actuator applies a predistortion that compensates for a non-linear characteristic of a PA comprised in transmitter circuitry.

In some embodiments, adapting the plurality of LUT entries in the LUT comprises computing a desired DPD characteristic based on a comparison of the input signal and a feedback signal, the feedback signal being from an output of a respective PA. Adapting the plurality of LUT entries in the LUT further comprises, for each LUT entry, computing an initial LUT value for the LUT entry based on the desired DPD characteristic and computing the first set of values {p1, p2, . . . , pk} and the second set of values {s1, s2, . . . , sk} for the LUT entry such that s1·2p1+s2·2p2+ . . . +sk·2pkis an approximation of the initial LUT value for the LUT entry.

DETAILED DESCRIPTION

Present day Digital Predistortion (DPD) systems use Look-Up Tables (LUTs) in the forward path to linearize a Power Amplifier (PA) to thereby reduce the Adjacent Channel Leakage Ratio (ACLR). This enables the PA to be operated in its non-linear region, which in turn enhances the efficiency of the PA.FIG. 1illustrates one example of a present day DPD system100. This DPD system100includes a forward path including a LUT102and a multiplier104, and an adaptation path that includes an adaptation function106and a LUT conversion function108. In operation, an input signal is received by the DPD system100. For each sample of the input signal, a value derived from the sample of the input signal that is indicative of the power of the input signal (e.g., a magnitude squared of the sample of the input signal) is used as an address of the LUT102. The addressed value in the LUT102is output to the multiplier104where it is multiplied together with the sample of the input signal to provide a respective sample of the output signal. This process is repeated for each sample of the input signal. The resulting output signal is a predistorted version of the input signal. Note that, while not shown, the output signal of the DPD system100is fed to a respective PA. Also, to cater memory effects, a pre-distorter commonly has three to twenty taps, as will be appreciated by one of skill in the art. However, multiple taps are not shown inFIG. 1for clarity and ease of discussion.

When the adaptation path is active, the adaptation function106and the LUT conversion function108operate together to populate the values in the LUT102to achieve the desired performance. More specifically, the adaptation function106compares the input signal and a feedback signal (e.g., an amplified version of the output signal from the output of a respective PA) and, based on this comparison, generates a desired predistortion characteristic. As an example, the adaptation function106may train the coefficients of an N-th order (e.g., third order, fourth order, fifth order, etc.) polynomial that defines the desired predistortion. The LUT conversion function108converts the output of the adaptation function106(e.g., the N-th order polynomial) into respective LUT values and stores those LUT values in the LUT102. In this manner, the adaptation path populates the LUT102.

In existing DPD systems, the multiplier104is a conventional multiplier (e.g., Booth Wallace multiplier). It is well known that these multipliers consume a significant amount of power and area. As a result of these multipliers, the conventional DPD system consumes a large amount of power. Due to the high power consumption, the conventional DPD system cannot be placed on the same chip with the PA due to excessive heating; instead, the DPD system is conventionally placed in the baseband processing unit with cooling. In general filter design domain, there are numerous works that reduce the power consumption by converting multiplications to shift and accumulate operations provided that one of the operands is a constant. However, they are not applicable to DPD since those techniques require that at least one of the operands is a constant.

Recently, 3GPP specification for NR has lowered the ACLR requirements. The proposed architecture exploits the lower ACLR requirements to save power in a DPD actuator (also called the forward path). In particular, a system and methods are disclosed herein that provide a solution for approximating multiplications using shift and accumulate operations in a DPD system (i.e., when neither of the operands is a constant). Simulations have shown that, theoretically, the solution presented herein saves 72% energy, saves 86% area, and has no additional memory costs. All this achieved at the cost of 2 decibels relative to the carrier (dBc) loss in ACLR, which is well within the range of the 5G 3GPP specification.

Systems and methods disclosed herein leverage the reduced ACLR requirements of 3GPP NR to reduce power consumption due to multipliers in the DPD system by replacing the conventional multipliers with circuitry that approximates multiplication using bit shifting operations. In particular, each LUT entry is represented by summation or subtraction of multiple powers of 2. The multiplier is then implemented by performing multiple bit shifting operations on a binary representation of the sample of the input signal and combining (e.g., adding and/or subtracting) the resulting bit-shifted versions of the sample of the input signal. In this manner, conventional multipliers are completely eliminated. Simulations have shown that, theoretically, a 72% reduction in dynamic energy can be achieved while maintaining the ACLR requirements of 3GPP. This reduction in power will allow, for example, the DPD system to be integrated with the radio on the same chip.

In this regard,FIG. 2illustrates a DPD system200according to embodiments of the present disclosure. Note that, for clarity and ease of discussion, the DPD system200is shown as a single tap system. However, as will be appreciated by one of ordinary skill in the art, the DPD system200may have multiple taps in order to compensate for memory effects. The DPD system200includes a forward path202including a select function203(also referred to herein as “selection circuitry”), a LUT204, and an approximate multiplication function206. The DPD system200also includes an adaptation path208that includes an adaptation function210, a LUT conversion function212, and an approximation function214. Note that the select function203, the LUT204, and the approximate multiplication function206are also referred to herein as a “DPD actuator” or a “LUT-based DPD actuator.” Similarly, the adaptation function210, the LUT conversion function212, and the approximation function214are also referred to herein as an “adaptor” or “DPD adaptor.” As discussed below in detail, the approximate multiplication function206implements an approximation of a multiplication of a sample of the input signal and a desired predistortion value using k bit shift operations, where k≥2 and, more preferably, k≥3. In some preferred embodiments, k=3. Note that the approximate multiplication function206performs an actual multiplication of the sample of the input signal and an approximation of the desired predistortion value (represented by values stored in the indexed LUT entry) using k bit shift operations. As such, the approximate multiplication function206is said to perform an “approximate multiplication” of the desired predistortion value and the sample of the input signal. The LUT204has multiple LUT entries, each storing information that defines the k bit shift operations and the combinations (i.e., additions or subtractions) of the resulting bit-shifted values needed to approximate multiplication of the input signal by a desired predistortion value for a respective input signal power level. The select function203selects the LUT entry to be output by the LUT204to the approximate multiplication function206based on the input signal. More specifically, the LUT entries are preferably indexed by a value derived from the input sample that is indicative of a power of the input signal (e.g., a magnitude squared of sample of the input signal.

Note that the input signal and the output signal of the DPD system200are typically complex signals, where each sample of these signals includes a real component (I) and an imaginary component or quadrature component (Q). As such, each LUT entry preferably includes separate information for I and Q. In other words, in order to approximate a multiplication of two complex values (i.e., a complex value sample of the input signal and a complex value of the desired predistortion), each LUT entry in the LUT204may include: (a) first information that defines the bit-shifting operations and combinations of the resulting bit-shifted values needed to approximate a multiplication of either the real component or the imaginary component of the sample of the input signal and the real component of the desired predistortion and (b) second information that defines the bit-shifting operations and combinations of the resulting bit-shifted values needed to approximate a multiplication of either the real component or the imaginary component of the sample of the input signal and the imaginary component of the desired predistortion. In other words, the multiplication of a complex input sample (Iin, Qin) and a respective complex DPD value (IDPD, QDPD) can be expressed as:
(Iin+iQin)·(IDPD+iQDPD)=IinIDPD−QinQDPD+iIinQDPD+iIDPDQin.

Thus, in some embodiments, to approximate complex multiplication, each DPD actuator202includes four approximate multiplication functions206to generate the terms IinIDPD, QinQDPD, IinQDPD, and IDPDQinusing respective combinations of bit shifting operations in accordance with respective information stored in applicable LUT entry (i.e., a first set of power values and sign values for IDPDand a second set of power values and sign values for QDPDin a manner similar to that described herein). For a particular complex input sample, the outputs of the four approximate multiplication functions206are combined in accordance with the equation above to provide the real and imaginary components of the output sample.

In the adaptation path208, when activated, the adaptation function210performs any suitable adaptation scheme based on the input signal and a respective feedback signal from the output of a respective PA to compute a desired predistortion characteristic. As an example, the adaptation function210may train coefficients of an N-th order (e.g., third order, fourth order, fifth order, etc.) polynomial that defines the desired predistortion. The LUT conversion function212converts the output of the adaptation function210(e.g., the N-th order polynomial) into respective initial LUT values. Rather than storing these LUT values in the LUT204, the approximation function214approximates each initial LUT value (LUTINT) as:
LUTINT≅s1·2p1+s2·2p2+ . . . +sk·2pk
where each value si∈{+1, −1} for all i=1, 2, . . . , k. The values siare sign values that define whether the k values of 2 are to be added or subtracted. For each initial LUT value, the approximation function214then stores, in a respective entry in the LUT204, information that represents a first set of values {p1, p2, . . . , pk} and a second set of values {s1, s2, . . . , sk} that together represent the approximation of the initial LUT value as s1·2p1+s2·2p2+ . . . +sk·2pk. For example, the information in the LUT entry may include k variables that represent the first set of values {p1, p2, . . . , pk} and k bits that represent the second set of values {s1, s2, . . . , sk} (i.e., bit value of 1 represents si=1 and bit value of 0 represents si=−1).

In operation, the input signal is received by the DPD system200. For each sample of the input signal, the select function203derives a value from the sample of the input signal that is indicative of the power of the input signal (e.g., a magnitude squared of the sample of the input signal). The value is used by the select function203to provide an address or index to the LUT204such that information from a corresponding entry of the LUT204is output to the approximate multiplication function206. This information is used at the approximate multiplication function206to generate an approximation of a multiplication of the sample of the input signal and a desired predistortion value using bit-shifting operations. This process is repeated for each sample of the input signal. The resulting output signal is a predistorted version of the input signal. Note that, while not shown, the output signal of the DPD system200is fed to a respective PA.

When the adaptation path208is active, the adaptation function210, the LUT conversion function212, and the approximation function214operate together to populate the LUT entries in the LUT204to achieve the desired performance. More specifically, the adaptation function210compares the input signal and a feedback signal (e.g., an amplified version of the output signal from the output of a respective PA) and, based on this comparison, generates a desired predistortion characteristic. Again, as an example, the adaptation function210may train the coefficients of an N-th order (e.g., third order, fourth order, fifth order, etc.) polynomial that defines the desired predistortion. The LUT conversion function212converts the output of the adaptation function210(e.g., the N-th order polynomial) into respective initial LUT values. Again, the approximation function214then approximates each of the initial LUT values as a combination of k powers of 2 and stores the information that represents the resulting power values {p1, p2, . . . pk} and sign values {s1, s2, . . . , sk} in the respective LUT entry.

A more detailed description of the operation of the approximate multiplication function206will now be provided. In general, assume that the sample of the input signal is X and the desired predistortion value is Y. This value of Y corresponds to the initial LUT value for the respective LUT entry. At the approximation function214, Y is approximated as:
Y≅s1·2p1+s2·2p2+ . . . +sk·2pk.

Assuming a binary representation of X, a multiplication of X and Y can then be computed using k bit shifting operations on the binary representation of Y and combining the results. Specifically, the multiplication of X and Y can be computed as follows:Shift bits of X by p1bit positions to get first bit-shifted value,Shift bits of X by p2bit positions to get second bit-shifted value,. . . ,Shift bits of X by pkbit positions to get k-th bit-shifted value, andCombine (i.e., add or subtract) the bit-shifted values in accordance with the respective sign values s1, s2, . . . , sk, where si=1 indicates addition and si=−1 indicates subtraction.

This processing may be performed serially (i.e., using a single bit shifter circuit to perform the bit-shifting operations serially) where accumulation is used to combine the bit-shifted values or performed in parallel (i.e., using k bit shifter circuits to perform the k bit-shifting operations in parallel) where addition/subtraction circuitry is then used to combine the bit-shifted values.

In this regard,FIG. 3illustrates one example embodiment of the approximate multiplication function206for k=3 in which the bit-shifted values are computed serially and accumulated. For clarity and ease of discussion, this example focuses on a scenario in which the input signal is a real signal.

As illustrated, the information from the appropriate LUT entry includes three variables, namely, a first variable that is a binary representation of p1, a second variable that is a binary representation of p2, and a third variable that is a binary representation of p3. In addition, the information from the LUT entry includes a first bit that represents the value s1, a second bit that represents the value s2, and a third bit that represents the value s3. The three variables representing the power values p1, p2, and p3are input to a first multiplexer300, and the three bits representing the sign values s1, s2, and s3are input to a second multiplexer302. A sample of the input signal (referred to herein as an input sample) is input to a shifter304. The output of the shifter304is provided to an adder/subtractor306that either adds or subtracts the output of the shifter304to/from a current value in an accumulation register308in accordance with the output of the second multiplexer302. A mod3 counter310controls outputs of the multiplexers300and302.

In operation, a new input sample and the information from the respective LUT entry are provided to the approximate multiplication function206. The accumulation register308is initialized to zero. In the first iteration, the first multiplexer300outputs the binary representation of p1, and the second multiplexer302outputs the bit that represents s1. The shifter304shifts the bits forming the binary representation of the input sample by p1bit positions to get a first bit-shifted value. If s1=1 as represented by the corresponding bit in the LUT entry, the adder/subtractor306adds the first bit-shifted value to the current value in the accumulation register308and stores the result in the accumulation register308. Conversely, if s1=−1 as represented by the corresponding bit in the LUT entry, the adder/subtractor306subtracts the first bit-shifted value from the current value in the accumulation register308and stores the result in the accumulation register308.

The mod3 counter310is incremented to then start the second iteration. In the second iteration, the first multiplexer300outputs the binary representation of p2, and the second multiplexer302outputs the bit that represents s2. The shifter304shifts the bits forming the binary representation of the input sample by p2bit positions to get a second bit-shifted value. If s2=1 as represented by the corresponding bit in the LUT entry, the adder/subtractor306adds the second bit-shifted value to the current value in the accumulation register308and stores the result in the accumulation register308. Conversely, if s2=−1 as represented by the corresponding bit in the LUT entry, the adder/subtractor306subtracts the second bit-shifted value from the current value in the accumulation register308and stores the result in the accumulation register308.

The mod3 counter310is again incremented to then start the third iteration. In the third iteration, the first multiplexer300outputs the binary representation of p3, and the second multiplexer302outputs the bit that represents s3. The shifter304shifts the bits forming the binary representation of the input sample by p3bit positions to get a third bit-shifted value. If s3=1 as represented by the corresponding bit in the LUT entry, the adder/subtractor306adds the third bit-shifted value to the current value in the accumulation register308and stores the result in the accumulation register308. Conversely, if s3=−1 as represented by the corresponding bit in the LUT entry, the adder/subtractor306subtracts the third bit-shifted value from the current value in the accumulation register308and stores the result in the accumulation register308. At that point, the process is complete, and the value stored in the accumulation register308is output as an output sample.

Note that the whileFIG. 3illustrates a serial implementation of the shifting operations, the approximate multiplication function206may alternatively use multiple shifters304in parallel to perform the bit-shifting operations in parallel.

In order to perform the approximate multiplication, the approximation function214needs to compute the first set of values {p1, p2, . . . , pk} (i.e., the power values) and the second set of values {s1, s2, . . . , sk} (i.e., the sign values) for each LUT entry by approximating the corresponding initial LUT value as:
LUTINT≅s1·2p1+s2·2p2+ . . . +sk·2pk,
as discussed above. One process for performing this approximation is outlined in by the pseudo-code below. This process transforms the initial LUT values output by the LUT conversion function212to a power of two representation. To understand how this process works, consider for example an initial LUT value of 45. The process will approximate the value of 45 as 25+24−21=46. The new LUT entry stored in the LUT204will store information that represents the powers (i.e., 5, 4, and 1) and signs (i.e., 1, 1, and −1). As an example, four bits may be used to store each power and one bit may be used to store its sign. Therefore, for, e.g., three variables, only 15 bits are needed. As discussed below, in one embodiment, the number of variables is three because experiments (explained later) reveal that three variables are sufficient to achieve the ACLR levels needed for NR 3GPP specification.

variables=3;%number of variables that represent a numberpowers_matrix=zeros(1,variables,numel(LUT)); %p1,p2,...,pk for each LUT indexsigns_matrix=ones(1,variables, numel(LUT)); %s1,s2,...,sk for each LUT indexfor input_iter=1:numel(LUT) %this loop runs iterates through entire LUTinput=LUT(input_iter);%get each lut element 1 by 1for iter=1:variables %loop to compute p1,p2,...,pk and s1,s2,...,sk for currentLUT entryn=0;target=0; %target value for 2{circumflex over ( )}powers_matrix(1,iter,input_iter)sum=0;if (iter==1) %for p1 the target is always the input valuetarget=input;else %e.g,. for p2, the target is abs(input−2{circumflex over ( )}p1)for j=1:(iter−1) %det sum of product of 2's based on current powers andsignsif (signs_matrix(1,j,input_iter)==1)sum=sum + 2{circumflex over ( )}powers_matrix(1,j,input_iter);elsesum=sum−2{circumflex over ( )}powers_matrix(1,j,input_iter);endendtarget=abs(input−sum);endif (target == 0) %need this or else can get negative value of n−1 if target ==0n=1;power_after=n;elsewhile ((2{circumflex over ( )}n)<=target) %find 2{circumflex over ( )}n representation>targetn=n+1;power_after=n; %this is the next power of 2>targetendendpower_before=(n−1);%this is the power of 2 <targetif(abs((2{circumflex over ( )}power_after)−target)<abs((2{circumflex over ( )}power_before)−target)) %Findcloseset numberchosen_power=power_after;elsechosen_power=power_before;endpowers_matrix(1,iter,input_iter)=chosen_power; %element inside powersmatrixnew_sum=0;for j=1:iter %determine new sum of product of 2's after adding new valueif (signs_matrix(1,j,input_iter)==1)new_sum=new_sum + 2{circumflex over ( )}powers_matrix(1,j,input_iter);elsenew_sum=new_sum−2{circumflex over ( )}powers_matrix(1,j,input_iter);endendif (new_sum>input) %choose the correct sign for next variableif ((iter+1)<=variables)signs_matrix(1,iter+1,input_iter)= −1;endelseif ((iter+1)<=variables)signs_matrix(1,iter+1,input_iter)=1;endendendend

The process above is outlined by the flowchart ofFIG. 4. As illustrated inFIG. 4, the approximation function214initializes a LUT index to 1 (step400). In the pseudocode above, the LUT index is referred to as “input_inter.” The approximation function214sets an input parameter equal to the initial LUT value corresponding to the LUT index, which is denoted here as LUT(input_inter), (step402). The approximation function214also initializes a variable index i to 1 (step404). In the pseudocode above, the variable index is referred to as “inter.”

The approximation function214sets a target parameter equal to the input, where the input is LUT(input_inter) (step406) and finds a value of pithat gives a power of 2 (i.e., 2pi) that is closest to the target (step408). Based on the chosen value of piand LUT(input_inter), the approximation function214determines the sign value si+1for the next iteration (step410). Specifically, if Σj=1isj2pjis less than the input, then the sign value si+1is set to +1; otherwise, the sign value si+1is set to −1. Note that step410does not need to be performed for the last iteration (i.e., where i=k where k is the number of variables as described above). The approximation function214determines whether i<k (step412). If so, the variable index i is incremented (step414), and the approximation function214updates the target (step416). Specifically, the updated target is computed as:

The process returns to step408and is repeated for the next power of 2. Once i=k, all of the set of power of 2 values {p1, p2, . . . , pk} and the second set of sign values {s1, s2, . . . , sk} that define the combination of k power of 2 values that approximate the initial LUT value for the current LUT index have been computed and can be stored in the LUT204.

The approximation function214determines whether the initial LUT value for the last LUT index has been approximated (step418). If not, the LUT index is incremented (step420) and the process returns to step402and is repeated for the next LUT value. Once all of the LUT table values have been approximated, the process ends.

The following example illustrates the process ofFIG. 4(and also the process outlined in the pseudocode above).Assume an initial LUT value of 91 and k=3.The input value is set to 91.The target is initially set to the input value (i.e., target=91).For the first iteration where i=1p1is computed as the value that gives a value of 2p1that is closest to the target (i.e., the closest to 91). Thus, pi=6.s1is always +1The value of s2is set to +1. In particular, since 26is less than the input value of 91, s2is set to +1. Note that if 2p1had been greater than the input value, then s2is would have then been set to −1.For the second iteration where i=2The target is updated as:

target=abs⁢⁢(input-∑j=1i-1⁢sj⁢2pj)Thus, for this second iteration the target is set to abs(91−26)=27.p2is computed as the value that gives a value of 2p2that is closest to the new target (i.e., the closest to 27). Thus, p2=5.The value of s3is set to −1. In particular, since 26+25=96 is greater than the input value of 91, s3is set to −1.For the third iteration where i=3The target is updated as:

target=abs⁢⁢(input-∑j=1i-1⁢sj⁢2pj)Thus, for this second iteration the target is set to abs(91−26−25)=5.p3is computed as the value that gives a value of 2p3that is closest to the new target (i.e., the closest to 5). Thus, p3=2.As a result, the initial LUT value of 91 is approximated as 26+25−22=92, where the set of power of 2 values {6,5,2} and the second set of sign values {1,1,−1}. Information that represents the set of power of 2 values {6,5,2} and the second set of sign values {1,1,−1} is stored in the corresponding entry in the LUT204and is used by the approximate multiplication function206to perform multiplication using, in this example, three bit shift operations and combining the results in accordance with the sign values {1,1,−1}.

Simulations were run using a PA model. The signal used was a 400 megahertz (MHz) wide LTE signal with sampling rate fs=2.212 gigahertz (GHz). The simulations used an implementation of the DPD system200based on a memory polynomial model with nonlinear order of 5 and memory length of 3, which results in three LUTs per DPD actuator. Simulations were run using three different coefficients per LUT: 64, 32, and 16.

The performance is measured in terms of time-domain Error Vector Magnitude (EVM) and ACLR. Based on the 3GPP specification for NR, the ACLR requirements per transmit (TX) branch is <−28 dBc. Usually telecom vendors have internal requirements of higher ACLR to ensure that the noise margins also meet operator/region requirements. Therefore, a conservative adjusted ACLR of −35 dBc is used.

FIG. 5shows the ACLR results obtained using three implementations of the proposed DPD system using 64, 32, and 16 coefficients per LUT. For comparison purposes, the ACLR results obtained using a conventional DPD system, i.e., one that does not use approximate multiplications, are also included. It can be seen that for all the proposed actuators, only three variables (i.e., 15 bits) were necessary to achieve the required ACLR level. Compared to a conventional DPD actuator, the proposed actuators obtain slightly higher ACLR values, which was caused by the use of approximate multiplications. It is important to highlight that despite that, the results are still within the ACLR budget for NR.

Similarly,FIG. 6shows that three variables are sufficient to reach required EVM levels. The EVM requirement specified by 3GPP NR is 8%. However, we have adjusted it conservatively to 4% since crest factor reduction induces a loss in EVM.

Finally, the energy and area saving potential of the proposed DPD system200will be discussed. Intuitively, a 16-bit multiplier requires 16 half adders and 240 full adders. To meet the high clock speeds, the multiplier is commonly pipelined in 2-3 stages. The proposed architecture of the DPD system200ofFIG. 3requires only 2 additions (using 30 full adders and 2 half adders) for accumulation. It requires two additional full adders for the mod3 counter310. The shifter overhead is negligible. Therefore, in terms of area, the proposed architecture requires 34 adders compared to 256 needed for a conventional DPD actuator. In terms of energy, the proposed architecture requires only 70 additions compared to 256 needed for the conventional multiplier. Hence the proposed architecture saves 86% area and 72% power.

As described herein, a DPD system is disclosed that exploits the lower ACLR requirements specified by 3GPP specifications. The embodiments described herein promise massive reduction in energy and area compared to conventional DPD systems by transforming all the multiplications to shift accumulate operations. As described herein, the DPD system operates as follows. During the adaptation phase of DPD, the LUT values are represented as combinations of k powers of 2. Experiments revealed that the required ACLR can be achieved using only three variables. For each LUT entry, the desired LUT value is approximated as the combination of k powers of 2 that is closest to the desired LUT entry. This step has low overall cost since table conversion occurs infrequently. Once the LUT entries are stored as power of 2 representations, the DPD actuator uses the LUT to perform shift and combine operations to approximate multiplication of input samples and the appropriate values to provide a predistorted output signal.

As discussed above, the DPD system200is illustrated inFIG. 2and described above as a single tap system. However, in many implementations, a multi-tap DPD system is needed to compensate for memory effects. In this regard,FIG. 7illustrates another example of the DPD system200in which the DPD actuator202includes M memory taps, each having its own 2 selection function203, LUT204, and approximate multiplication function206, which are denoted inFIG. 7as memory tap branches2700-1through2700-M. The DPD actuator2202ofFIG. 7also includes a number of delays7701-1through7701-(M−1) and a number of adders702-1through702-(M−1). As illustrated, the memory tap branch2700-1digitally predistorts the input signal to provide a first output signal as described above. In a similar manner, the memory tap branch2700-2digitally predistorts a first delayed version of the input signal output by the delay7701-1to provide a second output signal. Likewise, the memory tap branch2701-M digitally predistorts a (M−1)-th delayed version of the input signal output by the delay7701-(M−1) to provide a Mth output signal. The M output signals of the M memory tap branches2700-1through2700-M are added by the adders702-1through702-(M−1) to provide the output signal of the DPD actuator2202.

Notably, each memory tap branch2700-m(for m=1, 2, . . . , M) has its own LUT204-m. The DPD adaptor208generates and updates the LUT entries of the LUTs204-1through204-M in the manner described above. However, as will be appreciated by one of ordinary skill in the art upon reading this disclosure, the DPD adaptor208generates the initial LUT values for the LUTs204-1through204-M using an appropriate adaptation scheme that takes memory effects into account. Then, as described above, for each LUT entry in each LUT204-m, the DPD adaptor208approximates the initial LUT value for that LUT entry of that LUT204-mas a combination of k powers of 2, as described above, and stores the respective set of power values {p1, p2, . . . , pk} and the respective set of sign values {s1, s2, . . . , sk} in the LUT entry.

FIG. 8illustrates one example of the DPD adaptor208in accordance with some embodiments of the present disclosure. As illustrated, the DPD adaptor208includes the adaptation function210, the LUT conversion function212, and the approximation function214, as described above. The adaptation function210and the LUT conversion function212operate to generate the desired DPD values for the LUTs204based on some optimization algorithm, as will be understood by those of skill in the art of LUT-based DPD systems. In this example, the adaptation function210includes an H-matrix calculation function800and a θ calculation function802. In addition, the adaptation function210includes an optional H-matrix analysis and modification function804. The H-matrix calculation function800calculates an H-matrix based on a feedback signal (e.g., from the output of the PA). Optionally, for each complex value in the H-matrix, the H-matrix analysis and modification function804determines whether the real and imaginary components of the complex value can be approximated as a power of 2 value, within some predefined or preconfigured degree of accuracy (e.g., as configured by configurable H-matrix parameters). Real and imaginary component values in the H-matrix that can be approximated as power of 2 values within the predefined or preconfigured degree of accuracy are replaced with corresponding power of 2 values. The modified H-matrix is provided to the θ calculation function802and used, together with the feedback signal, to compute θ. The LUT conversion function212then computes desired (complex) DPD values based on the (modified) H-matrix and θ.

Note that the predefined or preconfigured degree of accuracy is, in this example, defined by a number of configurable parameters. Specifically, these parameters include: εrwhich defines a range of real values centered at a value of 0 within which a real value can be approximated as 0, εiwhich defines a range of imaginary values centered at a value of 0 within which an imaginary value can be approximated as 0, εr,1/2which defines a range of real values centered at a value of ½ within which a real value can be approximated as ½ (i.e., 2−1), εi,1/2which defines a range of imaginary values centered at a value of ½ within which an imaginary value can be approximated as ½ (i.e., 2−1), εr,1/4which defines a range of real values centered at a value of ¼ within which a real value can be approximated as ¼ (i.e., 2−2), εi,1/4which defines a range of imaginary values centered at a value of ¼ within which an imaginary value can be approximated as ¼ (i.e., 2−2), εr,1/8which defines a range of real values centered at a value of ⅛ within which a real value can be approximated as ⅛ (i.e., 2−8), εi,1/8which defines a range of imaginary values centered at a value of ⅛ within which an imaginary value can be approximated as ⅛ (i.e., 2−8), etc. In this regard,FIG. 9illustrates several examples of the approximation of the real and/or imaginary components of a complex value as 0 based on εrand εi.FIG. 10is a visual representation of the value ranges defined by the aforementioned parameters within which the real and/or imaginary components of a complex value can be approximated as a power of 2 value. Note that parameters discussed above assume approximation of the real and imaginary components of the complex DPD values as a single power of 2 value. However, in some other embodiments, approximation of the real and imaginary components of the complex DPD values as a combination of two or more power of 2 values, in which case the parameters would include some parameter(s) that defines an acceptable range of values around a particular value represented as a combination of two or more power of 2 values in which a real/imaginary component of a DPD value can be approximated as the combination of two or more power of 2 values.

Also note that, in the case of complex DPD values and a complex input signal, each LUT entry preferably includes separate information for I and Q, as discussed above. In other words, in order to approximate a multiplication of two complex values (i.e., a complex value sample of the input signal and a complex value of the desired predistortion), each LUT entry in the LUT204may include: (a) first information that defines the bit-shifting operations and combinations of the resulting bit-shifted values needed to approximate a multiplication of either the real component or the imaginary component of the sample of the input signal and the real component of the desired predistortion and (b) second information that defines the bit-shifting operations and combinations of the resulting bit-shifted values needed to approximate a multiplication of either the real component or the imaginary component of the sample of the input signal and the imaginary component of the desired predistortion. In other words, the multiplication of a complex input sample (Iin, Qin) and a respective complex DPD value (IDPD, QDPD) can be expressed as:
(Iin+iQin)·(IDPD+iQDPD)=IinIDPD−QinQDPD+iIinQDPD+iIDPDQin.

Thus, in some embodiments, to approximate complex multiplication, each DPD actuator202includes four approximate multiplication functions206to generate the terms IinIDPD, QinQDPD, IinQDPD, and IDPDQinusing respective combinations of bit shifting operations in accordance with respective information stored in applicable LUT entry (i.e., a first set of power values and sign values for IDPDand a second set of power values and sign values for QDPDin a manner similar to that described herein). For a particular complex input sample, the outputs of the four approximate multiplication functions206are combined in accordance with the equation above to provide the real and imaginary components of the output sample.

Thus, returning toFIG. 8, for each complex desired DPD value, the approximation function214approximates each of the real and imaginary components of the desired complex DPD value as a combination of k power of 2 values, as described above, and provides the resulting sets of power and sign values to the LUT204for storage in the appropriate LUT entry.

Note that the H-matrix calculation function800and the θ calculation function802ofFIG. 8are only examples. The main aspect to be illustrated by the adaptation function210ofFIG. 8is that there may be an approximation within the adaptation function210before the generation of the desired DPD values. Such an approximation can be used for any LUT creation based adaptation algorithm and for any data input to the LUT conversion function212. Such approximations may simplify the LUT value generation algorithm calculations and may, therefore, lower overall total power consumption.

While the disclosed DPD system200can be used in any type of wireless transmitter, in some embodiments the DPD system200is implemented in a radio node (e.g., a base station or wireless device (e.g., a UE)) in a cellular communications network. In this regard,FIG. 11illustrates one example of a cellular communications network1100in which one or more radio nodes include the DPD system200according to some embodiments of the present disclosure. In the embodiments described herein, the cellular communications network1100is a 3GPP 5G NR network. In this example, the cellular communications network1100includes base stations1102-1and1102-2, which in 5G NR are referred to as gNBs, controlling corresponding macro cells1104-1and1104-2. The base stations1102-1and1102-2are generally referred to herein collectively as base stations1102and individually as base station1102. Likewise, the macro cells1104-1and1104-2are generally referred to herein collectively as macro cells1104and individually as macro cell1104. The cellular communications network1100may also include a number of low power nodes1106-1through1106-4controlling corresponding small cells1108-1through1108-4. The low power nodes1106-1through1106-4can be small base stations (such as pico or femto base stations) or Remote Radio Heads (RRHs), or the like. Notably, while not illustrated, one or more of the small cells1108-1through1108-4may alternatively be provided by the base stations1102. The low power nodes1106-1through1106-4are generally referred to herein collectively as low power nodes1106and individually as low power node1106. Likewise, the small cells1108-1through1108-4are generally referred to herein collectively as small cells1108and individually as small cell1108. The base stations1102(and optionally the low power nodes1106) are connected to a core network1110.

The base stations1102and the low power nodes1106provide service to wireless devices1112-1through1112-5in the corresponding cells1104and1108. The wireless devices1112-1through1112-5are generally referred to herein collectively as wireless devices1112and individually as wireless device1112. The wireless devices1112are also sometimes referred to herein as UEs.

FIG. 12is a schematic block diagram of a radio access node1200according to some embodiments of the present disclosure. The radio access node1200may be, for example, a base station1102or1106. As illustrated, the radio access node1200includes a control system1202that includes one or more processors1204(e.g., Central Processing Units (CPUs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs), and/or the like), memory1206, and a network interface1208. The one or more processors1204are also referred to herein as processing circuitry. In addition, the radio access node1200includes one or more radio units1210that each includes one or more transmitters1212and one or more receivers1214coupled to one or more antennas1216. The radio units1210may be referred to or be part of radio interface circuitry. In some embodiments, the radio unit(s)1210is external to the control system1202and connected to the control system1202via, e.g., a wired connection (e.g., an optical cable). However, in some other embodiments, the radio unit(s)1210and potentially the antenna(s)1216are integrated together with the control system1202. In some embodiments, the DPD system200is implemented in the transmitter(s)1212.

FIG. 13is a schematic block diagram of the radio access node1200according to some other embodiments of the present disclosure. The radio access node1200includes one or more modules1300, each of which is implemented in software. The module(s)1300provide the functionality of the radio access node1200described herein. For example, at least some of the functionality of the DPD system200may be implemented by the module(s)1300.

FIG. 14is a schematic block diagram of a UE1400according to some embodiments of the present disclosure. As illustrated, the UE1400includes one or more processors1402(e.g., CPUs, ASICs, FPGAs, and/or the like), memory1404, and one or more transceivers1406each including one or more transmitters1408and one or more receivers1410coupled to one or more antennas1412. The processors1402are also referred to herein as processing circuitry. The transceivers1406are also referred to herein as radio circuitry. In some embodiments, the DPD system200is implemented in the transmitter(s)1408. Note that the UE1400may include additional components not illustrated inFIG. 14such as, e.g., one or more user interface components (e.g., a display, buttons, a touch screen, a microphone, a speaker(s), and/or the like), a power supply (e.g., a battery and associated power circuitry), etc.

FIG. 15is a schematic block diagram of the UE1400according to some other embodiments of the present disclosure. The UE1400includes one or more modules1500, each of which is implemented in software. The module(s)1500provide the functionality of the UE1400described herein. For example, at least some of the functionality of the DPD system200may be implemented by the module(s)1500.

At least some of the following abbreviations may be used in this disclosure. If there is an inconsistency between abbreviations, preference should be given to how it is used above. If listed multiple times below, the first listing should be preferred over any subsequent listing(s).3GPP Third Generation Partnership Project5G Fifth GenerationACLR Adjacent Channel Leakage RatioASIC Application Specific Integrated CircuitCPU Central Processing UnitdBc Decibels Relative to the CarrierDPD Digital PredistortionDSP Digital Signal ProcessoreNB Enhanced or Evolved Node BEVM Error Vector MagnitudeFPGA Field Programmable Gate ArrayGHz GigahertzgNB New Radio Base StationLTE Long Term EvolutionLUT Look-Up TableMHz MegahertzMME Mobility Management EntityMTC Machine Type CommunicationNR New RadioPA Power AmplifierP-GW Packet Data Network GatewayRAM Random Access MemoryROM Read Only MemoryRRH Remote Radio HeadSCEF Service Capability Exposure FunctionTX TransmitUE User Equipment