Semiconductor memory device for controlling write recovery time

A semiconductor memory device includes a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.

FIELD OF INVENTION

The present invention relates to a semiconductor memory device; and, more particularly, to a semiconductor memory device having ability of controlling timing of an auto-precharge operation depending on a column address strobe (CAS) latency mode.

DESCRIPTION OF PRIOR ART

An operational speed of a semiconductor memory device is an important factor to evaluate performance of the semiconductor memory device. Particularly, a write recovery time is one of factors which have influence on the operational speed of the semiconductor memory device.

After a data is stored into a unit cell included in the semiconductor memory device, a precharge operation is performed. Herein, there exists a time period before performing the precharge operation for the data to be stably stored into the unit cell not being prevented by the precharge operation.

The time period is called the write recovery time. That is, the write recovery time is a minimum time required for stably storing the data into the unit cell not being prevented by the precharge operation.

There have been introduced various ways for controlling the write recovery time. For instance, the write recovery time can be controlled using a clock signal. That is, in case that a mode register set (MRS) is set for a burst length to be 2, the write recovery time is a duration from a rising edge of the clock signal which a second data is inputted synchronizing with to a rising edge of the clock signal which a precharge command signal is inputted synchronizing with.

Generally, there are three ways for controlling the write recovery time, i.e., a synchronous method, an asynchronous method and admixed method.

In case of the synchronous method, the write recovery time is controlled using the clock signal as described above. That is, the precharge operation is performed synchronizing with the clock signal after the burst length and predetermined cycles of the clock signal. In case of the asynchronous method, the precharge operation is performed after the burst length and a predetermined delay time. The mixed method uses both of the synchronous method and the asynchronous method.

Those methods for controlling the write recover time are selected depending on various factors such as an operating frequency, a manufacturing process, an operating voltage and a temperature of the semiconductor memory device.

Generally, the synchronous method is adopted if there exist many variations on the manufacturing process; and the asynchronous method is adopted if the operating frequency is broad-banded.

FIG. 1is a block diagram showing a conventional semiconductor memory device.

As shown, the conventional semiconductor memory device includes an auto-precharge control unit10, a control unit20and a memory cell block30.

The auto-precharge control unit10generates a precharge control signal pc to control the control unit20. The control unit20controls the memory cell block30in response to the precharge control signal pc so that the memory cell block30performs an auto-precharge operation and a data access operation. The memory cell block30is provided with a plurality of unit cells.

To perform the data access operation, the conventional semiconductor memory device amplifies a data included in a selected unit cell, and the amplified data is latched by a sense-amplifier.

Thereafter, in case that the data access operation is performed for reading data from the conventional semiconductor memory device, the data latched by the sense-amplifier is outputted to the outside of the conventional semiconductor memory device. In case that the data access operation is performed for writing data to the conventional semiconductor memory device, an inputted data to be written is latched by the sense-amplifier. Herein, if the inputted data to be written is equal to the data latched by the sense-amplifier, the sense-amplifier keeps its data. On the other hand, if the inputted data to be written is different from the data latched by the sense-amplifier, the sense-amplifier inverts its data. Then, the data latched by the sense-amplifier is stored into the selected unit cell.

Thereafter, the sense-amplifier is precharged. This operation, i.e., the precharge operation was performed by an external precharge command signal when the operational speed of a semiconductor memory device was slow. However, at present, as a semiconductor memory device operates at a high speed, an internal prechrage command signal is generated and the precharge operation is performed automatically. That is, after completing an operation corresponding to an inputted command signal, the precharge operation is performed automatically after a predetermined time is passed. This automatically performed precharge operation is called an auto-precharge operation.

FIG. 2is a block diagram showing the auto-precharge control unit10.

As shown, the auto-precharge control unit10includes a timing control unit11, an auto-precharge timing decoder12and an auto-precharge timing control unit13.

The timing control unit11generates a first auto-precharge control signal apcg1and a second auto-precharge control signal apcg2to control timing of the auto-precharge operation after comparing timing of the auto-precharge operation expected when the conventional semiconductor memory device is designed with timing of the auto-precharge operation when the conventional semiconductor memory device is manufactured. The auto-precharge timing decoder12decodes the first and the second auto-precharge control signals apcg1and apcg2in order to output a plurality of decoded signals A, B and C. The auto-precharge timing control unit13receives an auto-precharge performing signal apcgpb for outputting the auto-precharge performing signal apcgpb as the precharge signal pc after adjusting output timing of the auto-precharge performing signal apcgpb in response to the plurality of decoded signals A, B and C.

Herein, as described above, the first auto-precharge control signal apcg1and the second auto-precharge control signal apcg2are used for compensating time difference between timing of the auto-precharge operation expected when the conventional semiconductor memory device is designed with timing of the auto-precharge operation when the conventional semiconductor memory device is manufactured. The first auto-precharge control signal apcg1and the second auto-precharge control signal apcg2are also used for arbitrarily control timing of the auto-precharge operation.

FIG. 3is a schematic circuit diagram showing the timing control unit11.

As shown, the timing control unit11includes a first and a second unit timing control units11A and11B.

The first unit timing control unit11A includes a first fuse F1, a first capacitor C1, a first metal oxide semiconductor (MOS) transistor MN1and a plurality of inverters I1, I2and I3.

One side of the first fuse F1is connected to a power supply voltage VDD and the other side is connected to the first capacitor C1, the first MOS transistor MN1and the inverter I1. A gate of the MOS transistor MN1is connected to an output of the inverter I1. One side of the first capacitor C1is connected to the first fuse F1, the MOS transistor MN1and the inverter I1and the other side is connected to a ground voltage VSS. The inverters I2and I3serve to buffer an output signal from the inverter I1for outputting the first auto-precharge control signal apcg1.

The second unit timing control unit11B includes a second fuse F2, a second capacitor C2, a second MOS transistor MN2and a plurality of inverters I4, I5and I6.

The timing control unit11controls the first and the second precharge control signals apcg1and apcg2by selectively blowing the first and the second fuse F1and F2.

For instance, at a wafer-level test, if the first fuse F1is blown by a laser, the first precharge control signal apcg1is activated as a logic high level because charge stored in the first capacitor C1is discharged and a voltage level of an input of the inverter I1becomes a voltage level of the ground voltage VDD. In case that the first fuse F1is not blown, the first precharge control signal apcg1is outputted as a logic low level.

Herein, the timing control unit11includes two unit timing control units, i.e., the first and the second unit timing control units11A and11B. However, the timing control unit11can includes more unit timing control units.

The auto-precharge timing decoder12decodes the first and the second precharge control signals apcg1and apcg2for selectively activating and outputting the plurality of decoded signals A, B and C.

Thereafter, the auto-precharge timing control unit13delays the auto-precharge performing signal apcgpb for a predetermined time and outputs the delayed auto-precharge performing signal apcgpb in response to the plurality of decoded signals A, B and C.

Meanwhile, timing of the auto-precharge operation is determined by the write recovery time as described above. The write recovery time is variable depending on a column address strobe (CAS) latency. The CAS latency (CL) is the ratio between column access time and a clock cycle time. That is, the CL shows how many cycles of the clock signal are spent while performing a read operation of a semiconductor memory device.

However, if the write recovery time keeps its value regardless of the CL, a semiconductor memory device can operate abnormally when the CL changes.

Generally, a semiconductor memory device changes value of the CL depending on a frequency change of the clock signal to be operated stably. The conventional semiconductor memory device can not control the auto-precharge operation depending on the CL. Therefore, there occur some errors when a value of the CL is changed due to the frequency change of the clock signal.

SUMMARY OF INVENTION

It is, therefore, an object of the present invention to provide a semiconductor memory device having ability of controlling a write recovery time depending on a frequency of a clock signal.

In accordance with an aspect of the present invention, there is provided a semiconductor memory device including a CAS latency mode detecting means for outputting a CAS latency control signal in response to a CAS latency mode; and an auto-precharge control means for controlling timing of an auto-precharge operation in response to the CAS latency control signal.

DETAILED DESCRIPTION OF INVENTION

Hereinafter, a semiconductor memory device in accordance with the present invention will be described in detail referring to the accompanying drawings.

FIG. 5is a block diagram showing a semiconductor memory device in accordance with a preferred embodiment of the present invention.

As shown, the semiconductor memory device includes an auto-precharge control unit1000and a column address strobe (CAS) latency mode detecting unit100.

The CAS latency mode detecting unit100generates a first and a second CAS latency control signals CL_S1and CL_S2in response to a CAS latency mode. The auto-prechrage control unit1000controls timing of an auto-precharge operation in response to the first and the second CAS latency control signals CL_S1and CL_S2.

The auto-precharge control unit1000includes a timing control unit200, an auto-precharge timing decoder300and an auto-precharge timing control unit400.

The timing control unit11generates a first and a second precharge control signals apcg1and apcg2. The auto-precharge timing decoder300decodes the first and the second precharge control signals apcg1and apcg2and the first and the second CAS latency control signals CL_SL and CL_S2for generating and outputting a plurality of decoded signals A, B, C and D. Herein, the auto-precharge timing decoder300activates one of the plurality of decoded signals A, B, C and D.

The auto-precharge timing control unit400delays an auto-precharge performing signal apcgpb in response to the plurality of decoded signals A, B, C and D for outputting the delayed auto-precharge performing signal apcgpb. Herein, how long the auto-precharge performing signal apcgpb is delayed is determined by the plurality of decoded signals A, B, C and D.

The timing control unit11includes a plurality of fuses for outputting the first and the second precharge control signals apcg1and apcg2. The structure of the timing control unit11is the same as that of the timing control unit included in the conventional semiconductor memory device.

FIG. 6is a schematic circuit diagram showing the CAS latency mode detecting-unit100shown inFIG. 5.

As shown, the CAS latency mode detecting unit100includes a first unit CAS latency mode detector110and a second unit CAS latency mode detector120.

In detail, each of the first and the second unit CAS latency mode detector110and120receives two CAS latency mode signals for generating a CAS latency control signal. That is, the second unit CAS latency mode detector120receives a first and a second CAS latency mode signals CL2and CL3to output the first CAS latency control signal CL_S1. Likewise, the first unit CAS latency mode detector110receives a third and a fourth CAS latency mode signals CL4and CL5.

The first CAS latency mode detector110includes two inverters I11and I12and a NAND gate ND5. The two inverters I11and I12receive the third and the fourth CAS latency mode signals CL4and CL5respectively. The NAND gate ND5performs a logic operation to outputted signals from the two inverters I11and I12to output the second CAS latency control signal CL_S2.

The structure and the operation of the second CAS latency mode detector120are the same as those of the first CAS latency mode detector110.

If a CAS latency is 2 or 3, the CAS latency mode detecting unit100activates and outputs the first CAS latency control signal CL_S1. On the other hand, if the CAS latency is 4 or 5, the CAS latency mode detecting unit100activates and outputs the second CAS latency control signal CL_S2.

Herein, the CAS latency mode detecting unit100includes two unit CAS latency mode detectors. However, the CAS latency mode detecting unit100can include more unit CAS latency mode detectors if there are more CAS latency mode signals besides the first to the fourth CAS latency mode signals CL2to CL5. In addition, it is also possible to arrange the unit CAS latency mode signals differently.

As shown, the auto-precharge timing decoder300includes an internal decoder310and a signal mixing unit320.

The internal decoder310including a plurality of inverters and NAND gates to receive and decode the first and the second precharge control signals apcg1and apcg2; and, thus, to output the decoded signals to the signal mixing unit320.

The signal mixing unit320also includes a plurality of NAND gates and inverters. The signal mixing unit320receives the first and the second CAS latency control signals CL_SL and CL_S2, and also receives the decoded signals outputted from the internal decoder310. The signal mixing unit320performs a logic operation on the decoded signals from the internal decoder310and the first and the second CAS latency control signals CL_S1and CL_S2in order to output the plurality of decoded signals A, B, C and D.

FIG. 8is a schematic circuit diagram showing the auto-precharge timing control unit400.

As shown, the auto-precharge timing control unit400includes a delay unit410and a signal output unit420.

The delay unit410serves to delay the auto-precharge performing signal apcgpb in response to the decoded signals A, B, C and D, and serves to output the delayed auto-precharge performing signal apcgpb to the signal output unit420. The signal output unit420receives the decoded signals A, B, C and D, the auto-precharge performing signal apcgpb and the delayed auto-precharge performing signal apcgpb from the delay unit410.

If all of the decoded signals A, B, C and D are inactivated, the signal output unit420outputs the auto-precharge performing signal apcgpb. On the other hand, if one of the decoded signals A, B, C and D is activated, the signal output unit420outputs the delayed auto-precharge performing signal apcgpb.

The delay unit410includes first to fourth unit delays411to414, first to fourth transfer gate T1to T4and a plurality of inverters I27to I33.

The first unit delay411receives the auto-precharge performing signal apcgpb to delay it. The first transfer gate T1is turned on by the decoded signal A in order to transfer an output signal from the first unit delay411to a latch formed by the 132 and the 133. The second unit delay412delays an output signal from the first unit delay411. The second transfer gate T2is turned on by the decoded signal B in order to transfer an output signal from the second unit delay412to the latch.

Likewise, the third unit delay413delays an output signal from the second unit delay412. The third transfer gate T3is turned on by the decoded signal C in order to transfer an output signal from the third unit delay413to the latch. The fourth unit delay414delays an output signal from the third unit delay413. The fourth transfer gate T4is turned on by the decoded signal D in order to transfer an output signal from the fourth unit delay414to the latch.

The latch formed by the inverters I32and I33serves to store a signal outputted from the plurality of decoded signals A, B, C and D.

The signal output unit420includes a NOR gate NOR1, a fifth transfer gate T5, a sixth transfer gate T6and two inverters I34and I35. The NOR gate NOR1receives the plurality of decoded signals A, B, C and D to perform a logic NOR operation to the plurality of decoded signals A, B, C and D, and outputs the result to the I35.

If an output signal from the inverter I35is in a logic low level, the sixth transfer gate is turned on and transfers the auto-precharge performing signal apcgpb as an output of the signal output unit420. On the other hand, if the output signal from the inverter I35is in a logic high level, the fifth transfer gate T5is turned on and transfers the delayed auto-precharge performing signal apcgpb outputted from the delay unit410as the output of the signal output unit420.

An operation of the semiconductor memory device in accordance with the preferred embodiment of the present invention is described below referring toFIGS. 5 to 8.

The CAS latency mode detecting unit100selectively activates and outputs the first and the second CAS latency control signals CL_S1and CL_S2in response to the first to the fourth CAS latency mode signals CL2to CL5. For instance, if the CAS latency is 3, the CAS latency mode detecting unit100activates the first CAS latency control signal CL_SL and outputs the activated first CAS latency control signal CL_SL to the auto-precharge timing decoder300.

Meanwhile, the timing control unit11generates the first and the second precharge control signals apcg1and apcg2by selectively blowing fuses included in the timing control unit11.

Thereafter, the internal decoder310decodes the first and the second precharge control signals apcg1and apcg2, and outputs the decoded signals to the signal mixing unit320. The signal mixing unit320performs a logic operation to outputted signals from the internal decoder310and the first and the second CAS latency control signals CL_S1and CL_S2in order to activate and output one of the plurality of decoded signals A, B, C and D.

Thereafter, the auto-precharge timing control unit400delays the auto-precharge performing signal apcgpb in response to the plurality of decoded signals A, B, C and D. An activated signal among the plurality of decoded signals A, B, C and D determines delay amount of the auto-precharge performing signal apcgpb.

For instance, if the decoded signal C is activated, the third and the fifth transfer gates T3and T5are turned on and the other transfer gates, i.e., T1, T2, T4and T6, are turned off. Therefore, the auto-precharge performing signal apcgpb is delayed passing through the first to the third unit delays411to413and outputted through the fifth transfer gate T5.

If all of the plurality of decoded signals A, B, C and D are inactivated, the sixth transfer gate T6is turned on and the other transferring gates, i.e., T1to T5, are turned off. Therefore, the auto-precharge performing signal apcgpb is not delayed and outputted from the auto-precharge timing control unit400.

Thereafter, in response to an output signal of the auto-precharge timing control unit400, the auto-precharge operation is performed.

As described above, the semiconductor memory device in accordance with the present invention can control timing of the auto-precharge operation according to a CAS latency. Therefore, the semiconductor memory device can perform the auto-precharge operation at proper time even if the CAS latency is changed.

Controlling timing of the auto-precharge operation according to the CAS latency means that the write recovery time is controlled according to the CAS latency. That is, the semiconductor memory device in accordance with the present invention can change the write recovery time when the write recovery time is required to be changed due to the change of the CAS latency.

A major cause of the change of the CAS latency is a change of a clock frequency. Therefore, the semiconductor memory device in accordance with the present invention can operate stably and reliably even if the clock frequency and the CAS latency are changed.

The present application contains subject matter related to Korean patent application No. 2003-76796, filed in the Korean Patent Office on Oct. 31, 2003, the entire contents of which being incorporated herein by reference.