Image processing apparatus, image forming apparatus and image processing method

An image processing apparatus has a line memory for writing and reading image data of one line. A write/read controller controls writing and reading the image data of one line in and from the line memory. A white line determiner determines whether an image corresponding to image data of one line being written in the line memory is a white line. An image processor performs specified image processing on the image data of one line read from the line memory by the write/read controller. An image processing controller generates an operation clock used in the image processor and causes the image processor to perform the specified image processing for the image data of one line determined not to be a white line and stops generating the operation clock and reads white data from a white data storage for the image data of one line determined to be a white line.

BACKGROUND OF THE DISCLOSURE

1. Field of the Invention

The present disclosure relates to an image processing apparatus with a line memory, an image forming apparatus with such an image processing apparatus and an image processing method.

2. Description of the Related Art

A line sensor is provided in an image processing apparatus such as a digital complex machine and generates image data of one page by repeatedly reading one page line by line in a main scanning direction. A line memory is a memory for storing image data of one line.

There has been proposed an image processing apparatus which determines whether or not image data of one page is white image data band by band, compresses the bands determined not to be the white image data, does not compress the bands determined to be the white image data and reads compressed white image data stored beforehand in a storage. According to this image processing apparatus, image processing can be speeded up since the bands determined to be the white image data are not compressed.

Properties required for image processing apparatuses include low power consumption besides high-speed processing. Accordingly, when white image data are not compressed as in the above image processing apparatus, it is preferable if power consumption can be reduced utilizing this.

SUMMARY OF THE DISCLOSURE

An object of the present disclosure is to provide an image processing apparatus capable of reducing power consumption, an image forming apparatus including such an image processing apparatus and an image processing method.

In order to achieve this object, one aspect of the present disclosure is directed to an image processing apparatus, comprising a line memory capable of writing and reading image data of one line; a write/read controller for controlling writing and reading of the image data of one line in and from the line memory; a white line determiner for determining whether or not an image corresponding to the image data of one line being written in the line memory by the write/read controller is a white line, an image processor capable of performing a specified image processing on the image data of one line read from the line memory by the write/read controller, a white data storage storing white data, and an image processing controller for controlling to generate an operation clock used in the image processor and cause the image processor to perform the specified image processing for the image data of one line determined not to be a white line by the white line determiner and controlling to stop generating the operation clock and read the white data from the white data storage for the image data of one line determined to be a white line by the white line determiner.

In order to achieve the above object, another aspect of the present disclosure is directed to an image forming apparatus, comprising an image processing apparatus according to the one aspect of the disclosure, and an image forming unit for forming an image on a sheet using image data of one page which is a collection of image data of a plurality of lines processed in the image processing apparatus.

In order to achieve the above object, still another aspect of the present disclosure is directed to an image processing method, comprising a first step of determining whether or not an image corresponding to image data of one line being written in a line memory is a white line, a second step of writing the image data of one line in the line memory, a third step of reading the image data of one line written in the line memory in the second step and performing a specified image processing on the read image data of one line using an operation clock when the image is judged not to be a white line in the first step, and a fourth step of causing the specified image processing not to be performed on the image data of one line written in the line memory in the second step by stopping the generation of the operation clock and, instead, reading white data as the image data of one line when the image is judged to be a white line in the first step.

Objects, features and advantages of the present disclosure will become more apparent upon reading the following detailed description along with the accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, an embodiment of the present disclosure is described in detail with reference to the drawings.FIG. 1is a diagram schematically showing the internal structure of an image forming apparatus1including an image processing apparatus according to one embodiment of the present disclosure. The image forming apparatus1can be applied, for example, to a digital complex machine having copy, printer, scanner and facsimile functions. The image forming apparatus1includes an apparatus main body100, a document reader200arranged on the apparatus main body100, a document feeder300arranged on the document reader200and an operation unit400arranged on the front surface of an upper part of the apparatus main body100.

The document feeder300functions as an automatic document feeder and can successively feed a plurality of documents placed on a document placing portion301to the document reader200.

The document reader200includes a carriage201carrying an exposure lamp and the like, a document table203made of a transparent member such as glass, an unillustrated CCD (Charge Coupled Device) sensor and a document reading slit205. The document reader200divides a document into a plurality of lines along a main scanning direction, reads the document while relatively moving the document in the sub scanning direction, and successively outputs image data of one line to a line memory51to be described later. In the case of reading a document placed on the document table203, the document is read by the CCD sensor by moving the carriage201in a longitudinal direction of the document table203. On the contrary, in the case of reading a document fed from the document feeder300, the document fed from the document feeder300is read through the document reading slit205by the CCD sensor by moving the carriage201to a position facing the document reading slit205. The CCD sensor outputs the read document as image data.

The apparatus main body100includes a sheet storage unit101, an image forming unit103and a fixing unit105. The sheet storage unit101is arranged in a bottommost part of the apparatus main body100and includes sheet trays107capable of storing stacks of sheets. The uppermost sheet in the sheet stack stored in each sheet tray107is fed to a sheet conveyance path111by driving a pickup roller109. The sheet is conveyed to the image forming unit103via the sheet conveyance path111.

The image forming unit103forms a toner image on a sheet conveyed thereto. The image forming unit103includes a photoconductive drum113, an exposure unit115, a developing unit117and a transfer unit119. The exposure unit115generates light modulated in correspondence with image data (image data output from the document reader200, image data transmitted from a personal computer, facsimile-received image data or the like) and irradiates the light to the uniformly charged circumferential surface of the photoconductive drum113. In this way, an electrostatic latent image corresponding to the image data is formed on the circumferential surface of the photoconductive drum113. By supplying toner from the developing unit117to the circumferential surface of the photoconductive drum113in this state, a toner image corresponding to the image data is formed on the circumferential surface. This toner image is transferred to a sheet conveyed from the sheet storage unit101described above by the transfer unit119.

The sheet having the toner image transferred thereto is fed to the fixing unit105. In the fixing unit105, heat and pressure are applied to the toner image and the sheet, whereby the toner image is fixed to the sheet. The sheet is discharged to a stack tray121or a discharge tray123.

The operation unit400includes an operation key unit401and a display unit403. The display unit403has a touch panel function and a screen with soft keys is displayed thereon. A user does setting necessary to perform the copy function or the like by operating the soft keys while viewing the screen.

The operation key unit401includes operation keys which are hard keys. Specifically, the operation key unit401includes a start key405, a numerical pad407, a stop key409, a reset key411, function switching keys413for switching the function among the copy, printer, scanner and facsimile functions, and the like.

The start key405is a key for starting an operation such as a copy operation or facsimile transmission. The numerical pad407is an assembly of keys used to input numbers such as the number of copies to be made, facsimile numbers and the like. The stop key409is a key for stopping the copy operation or the like halfway. The reset key411is a key for returning a set content to an initially set state.

The function switching keys413include a copy key, a transmit key and the like and are used to switch the function among the copy function, the transmit function and the like. If the copy key is operated, an initial screen for the copy operation is displayed on the display unit403. If the transmit key is operated, an initial screen for facsimile transmission and mail transmission is displayed on the display unit403.

FIG. 2is a block diagram showing the construction of the image forming apparatus1shown inFIG. 1. The image forming apparatus1includes the apparatus main body100, the document reader200, the document feeder300, the operation unit400, a control unit500, a communication unit600and an image processing apparatus700which are connected to each other via a bus. The apparatus main body100, the document reader200, the document feeder300and the operation unit400are not described here since they are already described.

The control unit500includes a CPU (Central Processing Unit), a ROM (Read Only Memory), a RAM (Random Access Memory), an image memory and the like. The CPU executes a control necessary to operate the image forming apparatus1on the above hardware constituting the image forming apparatus1. The ROM stores software necessary to control the operation of the image forming apparatus1. The RAM is used to temporarily store data generated at the time of executing the software and store application software and the like. The image memory is for temporarily storing image data (image data output from the document reader200, image data transmitted from a personal computer, facsimile-received image data or the like).

The communication unit600includes a facsimile communication unit601and a network I/F unit603. The facsimile communication unit601includes an NCU (Network Control Unit) for controlling connection of a telephone line to a destination facsimile machine and a modulation/demodulation circuit for modulating and demodulating a signal for facsimile communication. The facsimile communication unit601is connected to a telephone line605.

The network I/F unit603is connected to a LAN (Local Area Network)607. The network I/F unit603is a communication interface circuit for carrying out communication with terminal units such personal computers connected to the LAN607.

The image processing apparatus700is described.FIG. 3is a block diagram showing the construction of the image processing apparatus700according to this embodiment. The image processing apparatus700includes an ASIC (Application Specific Integrated Circuit)11and a DRAM (Dynamic Random Access Memory)13. Image data ImD of one page generated by a CCD sensor15is written in the DRAM13after specified image processings are performed thereon in the ASIC11. The CCD sensor15is provided in the document reader200shown inFIG. 2.

The ASIC11includes an internal clock generator21, an image processing controller23, a line processor25, an image processor27, an input device29, a white line determiner31, a white data storage33, a DMA (Direct Memory Access) controller35and an output device37.

The internal clock generator21generates an internal clock CLK2. The image processing controller23generates a read clock CLK3and an operation clock CLK4based on the internal clock CLK2. The read clock CLK3is fed to the line processor25and used in the case of reading image data of one line written in the line memory. The operation clock CLK4is fed to the image processor27and serves as a reference clock for image processing. The internal clock CLK2serves as an operation clock of the DMA controller35.

In an analog front end39, various processings are performed on analog image data of one page generated by the CCD sensor15and digital image data ImD of one page is input to the input device29. A sub scanning synchronization signal SG1and a main scanning synchronization signal SG2generated in the document reader200and an external clock CLK1and an image valid section signal SG3generated in the image processing apparatus700are input to the input device29. The input device29is an input interface between the ASIC11and the outside.

The image data ImD of one page is input to the input device29in the order of image data of the first line, that of the second line, that of the third line, . . . , that of the last line in synchronization with the main scanning synchronization signal SG2. The image data ImD of one page is a collection of image data of a plurality of lines.

One line is composed of a plurality of pixels. Accordingly, the image data of one line is a collection of a plurality of pixel data, i.e. first pixel data, second pixel data, third pixel data, . . . , last pixel data.

The image valid section signal SG3is generated in synchronization with the main scanning synchronization signal SG2in the image processing apparatus700and indicates a section of one main scanning line where an image is valid. The image is valid when the image valid section signal SG3is in an assert state (i.e. in an active state), whereas the image is invalid when the image valid section signal SG3is in a negate state (i.e. in an inactive state). The image valid section signal SG3is also called a MRE (Memory Read Enable) signal.

The sub scanning synchronization signal SG1is a signal indicating a section in the sub scanning direction where the image is valid. The image is valid when the sub scanning synchronization signal SG1is in an assert state while being invalid when it is in a negate state.

The image data ImD of one page, the sub scanning synchronization signal SG1, the main scanning synchronization signal SG2, the external clock CLK1and the image valid section signal SG3input to the input device29are fed to the line processor25. Since the image processings are performed on the image data line by line in the image processor27, the line processor25reads and writes the image data ImD of one page line by line.

The line processor25includes a first line memory51a, a second line memory51b, a write/read controller53, a write address counter55and a read address counter57.

The first and second line memories51a,51bare realized, for example, by SRAMs (Static Random Access Memories). Image data of one line is read from and written in the first and second line memories51a,51b. If the first line memory51ais readable, the second line memory51bis writable. Conversely, if the first line memory51ais writable, the second line memory51bis readable. Reading of image data of one line and writing of image data of line are performed in parallel. Unless it is necessary to distinguish the first and second line memories51a,51b, they are written as line memories51.

The write/read controller53switches the readable line memory51and the writable line memory51line by line out of the two line memories every time the main scanning synchronization signal SG2is input to the line processor25. The write/read controller53controls to read the image data of one line written in the readable line memory51and transfer it to the image processor27. The write/read controller53controls to write image data of the next line in the writable line memory51.

The external clock CLK1is input to a clock terminal of the write address counter55. Every time the external clock CLK1is input to the clock terminal, the write address counter55counts up and generates an address. This address is an address of an area where one pixel data is written (i.e. memory cell) in the writable line memory51.

The read clock CLK3is used for a control to read the image data of one line written in the readable line memory51. The read clock CLK3is input to a clock terminal of the read address counter57. Every time the read clock CLK3is input to the clock terminal, the read address counter57counts up and generates an address. This address is an address of an area where one pixel data is read (i.e. memory cell) in the readable line memory51.

The image data of one line read from the line processor25is transferred to the image processor27and stored in a line memory61of the image processor27. In the image processor27, specified image processings are performed on the image data of one line. The image processings here are, for example, color correction, chromatic aberration correction, MTF (Modulation Transfer Function) correction and line correction.

The image data ImD of one page, the sub scanning synchronization signal SG1, the main scanning synchronization signal SG2, the external clock CLK1and the image valid section signal SG3input to the input device29are fed to the white line determiner31. Using these, the white line determiner31determines whether or not an image corresponding to the image data of one line being written in the line memory51is a white line.

The white line determiner31counts white pixels out of the pixels constituting one line and determines that this line is a white line if the count value exceeds a predetermined threshold value. The definition of a white pixel may be such that a pixel is a white pixel if a pixel value is 255 or equal to or larger than a predetermined threshold value (e.g. 250), for example, in the case of representing the pixel in 256 gradations.

If the white line determiner31determines the line to be a white line, an output OP1of the white line determiner31is H level. If the white line determiner31determines the line not to be a white line, the output OP1of the white line determiner31is L level.

The output OP1is fed to the image processing controller23. The image processing controller23controls to generate the operation clock CLK4used in the image processor27and cause the image processor27to perform the specified image processings for the image data of one line determined not to be a white line by the white line determiner31. The image processing controller23controls to stop the generation of the operation clock CLK4used in the image processor27and read the white data from the white data storage33for the image data of one line determined to be a white line by the white line determiner31. The image processing controller23includes a signal output device71, OR gates73,72band a multiplexer77. In the image processing controller23, levels of outputs OP2, OP3and OP4are switched in accordance with the output OP1. The output OP2of H level is an example of a first mask signal, and the output OP3of H level is an example of a second mask signal.FIGS. 4 and 5are timing charts showing the operation of the image processing apparatus700. The output OP1and the like are described with reference toFIGS. 3 to 5.

When the sub scanning synchronization signal SG1input to the white line determiner31is switched from L level to H level (time t1), i.e. the image processing for the image data of one page starts in the image processing apparatus700, the level of the output OP1is switched to H level.

The image data of one line are successively fed to the line processor25, the image processor27, the multiplexer77and the DMA controller35after it is determined in the white line determiner31whether or not each of these image data is a white line. For the image data of one line determined not to be a white line in the white line determiner31, the values of the outputs OP2, OP3and OP4are adjusted (times t11, t13and t15inFIG. 5) in accordance with processing timings in the above respective devices.

The output OP2and the internal clock CLK2are input to the OR gate73. If the output OP2is H level (white line), the output of the OR gate73is H level. If the output OP2is L level (not a white line), the read clock CLK3is output from the OR gate (time t11). That is, the OR gate73functions as a first OR gate, outputs the internal clock CLK2as the read clock CLK3unless the first mask signal is input (i.e. if the output OP2of L level is input) and does not output the read clock CLK3if the first mask signal is input (i.e. the output OP2of H level is input).

The output OP3and the internal clock CLK2are input to the OR gate75. If the output OP3is H level (white line), the output of the OR gate75is H level. If the output OP3is L level (not a white line), the operation clock CLK4is output from the OR gate75(time t13). That is, the OR gate75functions as a second OR gate, outputs the internal clock CLK2as the operation clock CLK4unless the second mask signal is input (i.e. if the output OP3of L level is input) and does not output the operation clock CLK4if the second mask signal is input (i.e. the output OP3of H level is input).

The output OP4serves as a signal for switching the output of the multiplexer77. If the output OP4is H level (white line), the multiplexer77outputs the white data read from the white data storage33. For the case where the image corresponding to the image data of one line is a white line, the white data having the image processings performed thereon in the image processor27is stored in the white data storage33beforehand. If the white line determiner31determines the image corresponding to the image data of one line to be a white line, the read clock CLK3and the operation clock CLK4are not generated. Thus, the image processings are not performed on this image data in the image processor27, wherefore the white data is output instead.

If the output OP4is L level (not a white line) (time t15), the multiplexer77outputs the image data of one line having the image processings performed thereon in the image processor27.

The data output from the multiplexer77is transferred to the DRAM13via the output device37and written in the DRAM13by the DMA controller35. The output device37is an output interface between the ASIC11and the outside.

The signal output device71is described.FIG. 6is a circuit diagram of the signal output device71. The signal output device71is a shift register including three D flip-flops72a,72band72c. The image valid section signal SG3is input to clock terminals of the D flip-flops72a,72band72c. The output OP1is input to an input terminal of the D flip-flop72a. The sub scanning synchronization signal SG1is input to set terminals of the D flip-flops72a,72band72c.

An output from the D flip-flop72ain the first stage becomes the output OP2, that from the D flip-flop72bin the second stage becomes the output OP3and that from the D flip-flop72cin the third stage becomes the output OP4.

Next, the operation of the image processing apparatus700is described mainly usingFIGS. 4 and 5. There is described an exemplary case where image data of the first to (N−1)th lines out of image data ImD of one page correspond to a leading margin of a document of one page.

If the sub scanning synchronization signal SG1is in L level (negate state), a L-level signal is input to the set terminals of the D flip-flops72a,72band72cshown inFIG. 6. Accordingly, the D flip-flops72a,72band72care set, wherefore the output OP2from the D flip-flop72a, the output OP3from the D flip-flop72band the output OP4from the D flip-flop72crespectively become H level. If the output OP2is H level, the image processing controller23stops generating the read clock CLK3. If the output OP3is H level, the image processing controller23stops generating the operation clock CLK4.

At time t1, the sub scanning synchronization signal SG1is switched from L level to H level (assert state). This causes the output OP1of the white line determiner31to be switched from L level to the H level.

Further, at time t1, the main scanning synchronization signal SG2of L level corresponding to the image data of the first line is input to the line processor25. The write/read controller53sets the first line memory51ato be writable and the second line memory51bto be readable.

The image valid section signal SG3is switched to H level. The write/read controller53controls to write the image data of the first line in the first line memory51a. The write/read controller53continuously controls to write in the first line memory51auntil the image valid section signal SG2is switched to L level. Writing means overwriting. Data stored in the second line memory51bis indefinite. Since the read clock CLK3is not generated, no data is read from the second line memory51b.

The image valid section signal SG3is switched to L level. The write/read controller53finishes the control to write the image data of the first line in the first line memory51a. The white line determiner31determines the image corresponding to the image data of the first line to be a white line. Thus, the white line determiner31keeps the output OP1of H level, wherefore the image processing controller23continues not to generate the read clock CLK3and the operation clock CLK4.

The main scanning synchronization signal SG2of L level corresponding to the image data of the second line is input to the line processor25. The write/read controller53sets the first line memory51ato be readable and the second line memory51bto be writable.

Since the image valid section signal SG3is switched to H level, the write/read controller53controls to write the image data of the second line in the second line memory51b. Since the read clock CLK3is not generated in the image processing controller23, the image data of the first line is not read from the first line memory51a.

The image valid section signal SG3is switched to L level. The write/read controller53finishes the control to write the image data of the second line in the second line memory51b. Since the white line determiner31determines the image corresponding to the image data of the second line to be a white line, the white line determiner31keeps the output OP1of H level. Thus, the image processing controller23continues not to generate the read clock CLK3and the operation clock CLK4.

The image valid section signal SG3is switched to H level. The write/read controller53controls to write the image data of the third line in the first line memory51a. Since the read clock CLK3is not generated, the image data of the second line is not read from the second line memory51b. Further, since the operation clock CLK4is not generated, the image processor27does not operate.

The image valid section signal SG3is switched to L level. The write/read controller53finishes the control to write the image data of the third line in the first line memory51a. The white line determiner31determines the image corresponding to the image data of the third line to be a white line. Thus, it is continued not to generate the read clock CLK3and the operation clock CLK4.

The image valid section signal SG3is switched to H level. The write/read controller53controls to write the image data of the fourth line in the second line memory51b. Since the read clock CLK3is not generated, the image data of the third line is not read from the first line memory51a. Further, since the operation clock CLK4is not generated, the image processor27does not operate.

Since the output OP4is H level, the multiplexer77selects the white data storage33. Accordingly, the white data stored beforehand in the white data storage33is output as the image data of the first line from the multiplexer77. Then, by the DMA controller35, the white data is written in the memory cells allotted to the image data of the first line out of the memory cells of the DRAM13. Thereafter, the white data stored beforehand in the white data storage33is output from the multiplexer77also for image data of the second to (N−1)thlines and written in the memory cells allotted to the image data of these lines out of the memory cells of the DRAM13.

The image valid section signal SG3is switched to L level. The write/read controller53finishes the control to write the image data of the Nthline in the first line memory51a. The white line determiner31determines the Nthline not to be a white line. This causes the white line determiner31to switch the output OP1to L level, wherefore an L-level signal is input to the input terminal of the D flip-flop72ashown inFIG. 6. On the other hand, since the outputs OP2, OP3continue to be H level, the image processing controller23continues not to generate the read clock CLK3and the operation clock CLK4.

The image valid section signal SG3is switched to H level. The write/read controller53controls to write the image data of the (N+1)thline in the second line memory51b. Since the output OP1is L level, the output OP2is switched to L level in synchronization with the switch of the image valid section signal SG3to H level. Since this causes the read clock CLK3to be generated, the write/read controller53controls to read the image data of the Nthline from the first line memory51a. Note that since the operation clock CLK4is not generated, the image processor27does not operate. Since the output OP4is H level, the multiplexer77selects the white data storage33. Accordingly, the white data is output as the image data of the (N−2)thline from the multiplexer77.

The image valid section signal SG3is switched to L level. The write/read controller53finishes the control to write the image data of the (N+1)thline in the second line memory51b. Since determining the (N+1)thline not to be a white line, the white line determiner31keeps the output OP1of L level.

The image valid section signal SG3is switched to H level. The write/read controller53controls to write the image data of the (N+2)th line in the first line memory51aand to read the image data of the (N+1)th from the second line memory51b.

Since the output OP1is L level, the output OP3is switched to L level in synchronization with the switch of the image valid section signal SG3to H level. Since the operation clock CLK4is generated, the specified image processings are performed on the image data of the Nthline read from the first line memory51ain the image processor27.

The image valid section signal SG3is switched to L level. The write/read controller53finishes the control to write the image data of the (N+2)thline in the first line memory51a. Since determining the (N+2)thline not to be a white line, the white line determiner31keeps the output OP1of L level.

The image valid section signal SG3is switched to H level. The write/read controller53controls to write the image data of the (N+3)thline in the second line memory51band to read the image data of the (N+2)thfrom the first line memory51a.

Since the output OP1is L level, the output OP4is switched to L level in synchronization with the switch of the image valid section signal SG3to H level. Since the output OP4is L level, the multiplexer77selects the image processor27. Accordingly, the image data of the Nth line having the image processings performed thereon in the image processor27is output from the multiplexer77.

Thereafter, unless the image of one line is a white line, the image data of this line having the image processings performed thereon in the image processor27is output from the multiplexer77. If the image of one line is a white line, the white data stored in the white data storage33is output from the multiplexer77. Accordingly, if a document is a character document, no image processings are performed on image data of one line corresponding to line spaces and a trailing end margin in the image processor27and white data is output.

As described above, the image processing controller23generates the read clock CLK3for the image data of one line determined not to be a white line by the white line determiner31, and stops generating the read clock CLK3for the image data of one line determined to be a white line by the white line determiner31. The write/read controller53controls to read the image data of one line determined not to be a white line by the white line determiner31from the line memory51using the read clock CLK3, and does not control to read the image data of one line determined to be a white line by the white line determiner31from the line memory51.

Main effects of this embodiment are described. According to this embodiment, if the image corresponding to the image data of one line is determined to be a while line in the white line determiner31, the generation of the operation clock CLK4used in the image processor27is stopped. In this way, the image data of this line is neither written in nor read from the line memory61and no image processings are performed thereon in the image processor27. Thus, the white data is read from the white data storage33instead. In this way, if the image corresponding to the image data of one line is determined to be a white line, the generation of the operation clock CLK4used in the image processor27is stopped for the image data of this line. Therefore, lower power consumption of the image processing apparatus700can be realized. Particularly, since writing and reading are stopped in the line memory61by stopping the operation clock CLK4, power consumption can be reduced.

According to this embodiment, if the image corresponding to the image data of one line is determined to be a white line, no image processings are performed on the image data of this line. Thus, reading of the image data of this line is prevented by stopping the generation of the read clock CLK3. Since the generation of the read clock CLK3is stopped, lower power consumption of the image processing apparatus700can be realized.

Further, according to this embodiment, as shown inFIGS. 4 and 5, the generation of the read clock CLK3and the operation clock CLK4is stopped if the sub scanning synchronization signal SG1is in the negate state (before time t1) and it is possible to generate the read clock CLK3and the operation clock CLK4if the sub scanning synchronization signal SG1is in the assert state (after time t1). Since no image data is input to the image processing apparatus700if the sub scanning synchronization signal SG1is in the negate state, lower power consumption of the image processing apparatus700can be realized by stopping the generation of the read clock CLK3and the operation clock CLK4. Thus, the read clock CLK3and the operation clock CLK4can be stopped before the image data of the first line is written in the line memory51, wherefore lower power consumption of the image processing apparatus700can be realized.

According to this embodiment, a clock as a basis of the read clock CLK3and that as a basis of the operation clock CLK4are common (internal clock CLK2), the generation and non-generation of the read clock CLK3are switched by the OR gate73(first OR gate) and the first mask signal, and the generation and non-generation of the operation clock CLK4are switched by the OR gate75(second OR gate) and the second mask signal. Therefore, the generation and non-generation of the read clock CLK3and the generation and non-generation of the operation clock CLK4can be realized by a simple construction.

According to this embodiment, as shown inFIG. 4, the image data ImD is not input to the image processing apparatus700if the sub scanning synchronization signal SG1is in the negate state (before time t1). Thus, the signal output device71outputs the first and second mask signals. Since this causes the generation of the operation clock CLK4and the read clock CLK3to be stopped, lower power consumption of the image processing apparatus700can be realized.

In this embodiment, as shown inFIGS. 4 and 5, the image data of one line determined to be a white line is not read from the line memory51. However, it is also possible to read the image data of one line determined to be a white line from the line memory51. In this mode, the image data of one line determined to be a white line is read from the line memory51and fed to the image processor27. However, since the operation clock CLK4is not generated, no image processings are performed on the image data of one line determined to be a white line in the image processor27and the white data is read from the white data storage33as in this embodiment. In this mode, the OR gate73shown inFIG. 3and the generation of the output OP2become unnecessary, and the internal clock CLK2is input as the read clock CLK3to the line processor25.

Although the image data processed in the ASIC11is written in the DRAM13in this embodiment, it may be transferred to an ASIC in a subsequent stage.

This application is based on Japanese Patent application No. 2010-262316 filed in Japan Patent Office on Nov. 25, 2010, the contents of which are hereby incorporated by reference.