Double patterning process for integrated circuit device manufacturing

A method of forming an integrated circuit (IC) device feature includes forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned; forming a first photoresist layer over the hardmask layer; patterning a first set of semiconductor device features in the first photoresist layer; registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the first photoresist layer; forming a second photoresist layer over the substantially planar hardmask layer; patterning a second set of semiconductor device features in the second photoresist layer; registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the second photoresist layer; and creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor device features.

BACKGROUND

The present invention relates generally to semiconductor device manufacturing techniques and, more particularly, to an improved double patterning process for integrated circuit (IC) device manufacturing.

Double exposure, double etch patterning has been adopted in 32 nanometer (nm) node to improve pattern density at critical levels. Double patterning is a process for obtaining designed layout patterns, by distributing layout patterns into a plurality of masks and performing a plurality of exposure processes, etching processes and the like. When the distance between two layout patterns is small, if the two layout patterns are formed on an identical mask, the two layout patterns cannot separately be formed on a wafer. Double patterning is therefore used to avoid such a problem.

More specifically, a first exposure of photoresist is used to transfer a first pattern to an underlying hardmask layer by etching. After the photoresist is removed following the hardmask pattern transfer, a second layer of photoresist is then coated onto the once-etched hardmask layer. This second photoresist layer undergoes a second exposure, imaging additional features (by etching) in between the features already patterned in the hardmask layer. The resulting surface pattern of first and second features in the patterned hardmask can then be transferred into a layer beneath the hardmask, such as a dielectric layer or a gate electrode layer, for example. This effectively allows for a doubling of feature density.

However, there are issues related to the double patterning technique. In particular, one obstacle relates to the topography formed in a layer (e.g., a hardmask) as a result of the first patterning and etch process. The resulting topography from a first patterning process reduces the lithography process window for the second patterning process. This is especially a problem for high numerical aperture (NA) lithography due to its extremely shallow depth of focus.

SUMMARY

In an exemplary embodiment, a method of forming an integrated circuit (IC) device feature includes forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned; forming a first photoresist layer over the initially substantially planar hardmask layer, and patterning a first set of semiconductor device features in the first photoresist layer; registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the first photoresist layer; forming a second photoresist layer over the substantially planar hardmask layer, and patterning a second set of semiconductor device features in the second photoresist layer; registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the second photoresist layer; and creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor device features.

In another embodiment, a method of forming an integrated circuit (IC) device feature includes forming an initially substantially planar hardmask layer over a semiconductor device layer to be patterned; forming a first photoresist layer over the initially substantially planar hardmask layer, and patterning a first set of semiconductor device features in the first photoresist layer; registering the first set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the first photoresist layer; forming a second photoresist layer over the substantially planar hardmask layer, and patterning a second set of semiconductor device features in the second photoresist layer; registering the second set of semiconductor device features in the hardmask layer in a manner that maintains the hardmask layer substantially planar; removing the second photoresist layer; creating topography within the hardmask layer by removing portions thereof corresponding to both the first and second sets of semiconductor device features; and transferring a resulting combined pattern formed in the hardmask layer into the semiconductor device layer therebeneath.

DETAILED DESCRIPTION

Disclosed herein an improved double patterning process for integrated circuit (IC) device manufacturing that avoids creating topography in a hardmask after a first patterning operation. In so doing, the lithographic process window of the second patterning process is improved. Once both lithography patterns are defined, the resulting final double density pattern is then actually transferred into the hardmask layer through a single etch. In an exemplary embodiment, the first and second (or more) patterns are “registered” or recorded in the hardmask layer in a non-topographic fashion by implantation of a dopant species (such as germanium, for example), which creates an etch selectivity in the hardmask layer (e.g., a nitride material). In this manner, the hardmask layer is not etched to create topography therein until multiple lithographic patterns have been defined therein through dopant implantation.

Referring initially toFIGS. 1 through 5, there is shown are a series of top and cross sectional views illustrating an existing method of double patterning in semiconductor device manufacturing. In the Figures, the “(a)” suffix generally denotes a top view, while the “(b)” and “(c)” suffixes generally denote cross sectional views taken along lines of the top view. Beginning withFIG. 1,FIG. 1(a) is a top view of a semiconductor device100that is being patterned for transistor gate formation, whileFIG. 1(b) is a cross sectional view taken along the lines B-B ofFIG. 1(a). As is particularly shown inFIG. 1(b), a semiconductor substrate102(e.g., silicon, silicon-on-insulator, etc.) has a gate dielectric layer104(e.g., oxide, nitride, oxynitride, etc.) formed thereon, followed by a gate conductor layer106(e.g., polysilicon). A hardmask layer108(e.g., silicon nitride) is patterned in accordance with a first lithographic process as known in the art to define a first pattern that, in this example, is a plurality of gate conductors.

As then shown inFIGS. 2(a) and2(b), a second lithographic process is used to create a second pattern, wherein a (second) photoresist layer110is formed over the device (including the topographic, once patterned hardmask layer108) and patterned so as to form an opening112therein. The opening112in the resist layer110defines a location in which a pair of the subsequently formed gate lines are to be broken. As shown inFIGS. 3(a) and3(b), the exposed portions of the nitride hardmask layer108are then removed, such as by reactive ion etching (RIE). Then, the resist layer110is removed as shown inFIGS. 4(a) and4(b), thereby revealing the completed double patterned hardmask layer108. Finally, inFIGS. 5(a),5(b) and5(c), the double pattern of the hardmask layer108is transferred into the gate conductor layer106through another etch process, stopping on the gate dielectric layer104. From this point, standard CMOS device process may continue.

As mentioned above, however, during the second patterning of the hardmask layer108, the formation of the resist layer110on the topographic features of the once patterned hardmask layer108(FIG. 2) creates problems in terms of the diminished process window. That is, patterning a resist layer with features at or below the critical dimension on a topographic surface is problematic given a smaller depth of focus and the potential for scumming (resist residue left on the wafer).

Accordingly,FIGS. 6 through 12are a series of various top and cross sectional views illustrating a method of double patterning in semiconductor device manufacturing, in accordance with an embodiment of the invention. The technique of this embodiment is again presented in the context of gate conductor formation, but as will be shown later, it is equally applicable to formation of other device features in semiconductor manufacturing. Beginning withFIGS. 6(a) and6(b), a semiconductor device600includes a semiconductor substrate602, a gate dielectric layer604formed on the substrate602, a gate conductor layer606formed on the gate dielectric layer604, and a hardmask layer608formed on the gate conductor layer606. As also shown, a first photoresist layer610formed on the hardmask layer608is patterned with a first set of features.

In a conventional double patterning process, the resist pattern would, at this point, be etched into the hardmask layer608before a second patterning process takes place. However, as shown inFIGS. 7(a) and7(b), the device is instead subjected to a dopant implant (e.g., a neutral species such as germanium) so as to create doped regions612within the hardmask layer608(e.g., nitride) that are etch selective with respect to undoped portions thereof. In addition to germanium, other dopant materials may also be used, including but not limited to, silicon, argon, xenon, and arsenic. In this manner, the first pattern is effectively registered or stored within the hardmask layer608in a manner that does not create topography prior to completion of all desired patterns. Once the first pattern is registered, the first resist layer610is then removed.

As shown inFIGS. 8(a) and8(b), a second photoresist layer614is then formed over the substantially planar, non-topographic hardmask layer608with doped regions612. The resist layer614is then patterned and opened to form an opening616(similar to that inFIG. 2(a)) for the purpose of creating a break in the subsequently gate lines, and the dimensions of which are difficult to create in a single pattern process. Then, a second dopant implant is performed so as register this second pattern within the newly exposed portions of the planar hardmask layer608, as shown inFIGS. 9(a) and9(b). In other words, the entire portion of the hardmask layer exposed by opening616is now a doped region612.

InFIGS. 10(a) and10(b), the resulting double pattern is revealed in the planar hardmask layer upon removal of the second photoresist layer, specifically depicting the doped regions612in the hardmask layer608resulting from a double exposure, double dopant process. At this point, the hardmask layer608may now be patterned topographically with the desired gate pattern through a selective etch process that removes the doped regions612, as shown inFIGS. 11(a) and11(b). In one embodiment, the hardmask layer608comprises silicon nitride while the dopant species is germanium. The selective etch process for removing the doped regions612includes performing an etch process in a solution comprising hydrofluoric (HF) acid. Thereafter, the pattern of the hardmask layer608is then transferred into the gate conductor606, through another etch process, stopping on the gate dielectric layer604as shown inFIGS. 12(a),12(b) and12(c). From this point, standard CMOS device processing may continue.

FIGS. 13 through 18are a series of various top and cross sectional views illustrating a method of double patterning in semiconductor device manufacturing, in accordance with another embodiment of the invention. In this example, the non-topographic double patterning technique is applied in the formation of dense contacts, such as conductively filled vias within an interlevel dielectric (ILD) layer, used for making contact between transistor devices and a first wiring level, or between wiring levels in the back end of line (BEOL) regions of a semiconductor device, for example.

Beginning withFIGS. 13(a) and13(b), a semiconductor device1300includes a semiconductor substrate1302, a self aligned silicide (salicide) layer1304formed on the substrate1302, an ILD layer1306formed on the salicide layer604, and a hardmask layer1308formed on the ILD layer1306. As also shown, a first photoresist layer1310formed on the hardmask layer1308is patterned with a first set of contact hole features or vias1312a,1312b. Conventionally, to pattern one or more additional vias between vias1312a,1312b, the resist pattern would first be etched into the hardmask layer1308, followed by deposition of a second photoresist layer and a second patterning step to define subsequent contact holes. Instead, the device is subjected to a dopant implant (e.g., a neutral species such as germanium) as shown inFIGS. 14(a) and14(b) so as to create doped regions1314within the hardmask layer1308that are etch selective with respect to undoped portions thereof. In this manner, the first pattern of contact holes is effectively registered or stored within the hardmask layer1308in a manner that does not create topography prior to completion of all desired contact holes. Once the first pattern is registered, the first resist layer1310is then removed.

As shown inFIGS. 15(a) and15(b), a second photoresist layer1316is then formed over the substantially planar, non-topographic hardmask layer1308with doped regions1314. The resist layer1316is then patterned and opened to form another via opening1312c, disposed between previously formed openings1312a,1312b, in order to increase the density of the vias. Then, a second dopant implant is performed so as register this second via pattern within the newly exposed portions of the planar hardmask layer1308, as shown inFIGS. 16(a) and16(b). Thereafter, the second photoresist layer1316is removed, followed by a selective etch process that removes the doped regions1314, as shown inFIGS. 17(a) and17(b). The combined via pattern etched into the hardmask layer1308is then transferred into the ILD layer1306, through another etch process, stopping on the salicide layer1304as shown inFIGS. 18(a) and18(b). From this point, standard damascene processing (e.g., liner, metal fill, chemical mechanical polishing, etc.) may continue.

Finally,FIGS. 19(a) and19(b) are, respectively, top and cross sectional views illustrating another example of a semiconductor structure that may be formed using the above described double patterning technique, in accordance with another embodiment of the invention. As the double pattern/double dopant implant/single etch sequence is adequately described above, the detailed sequence is omitted. Rather,FIGS. 19(a) and19(b) depict still another example of a semiconductor device structure that may be formed through such a technique. Here, the example depicts the formation of double density shallow trench isolation (STI) structures that (as known in the art) are used to electrically isolate neighboring transistor devices and the like from one another. As is shown, a substrate1902has a pad oxide layer1904and a pad nitride layer1906formed thereon. A plurality of trench patterns1908a,1908b,1908care defined (through the above described technique) in the pad nitride and oxide layers1906,1904to be transferred into the substrate1902and subsequently filled with an STI fill material, such as an oxide.