Method and apparatus for charge transfer

A circuit comprises: a first capacitor; a second capacitor; a MOS (metal oxide semiconductor) transistor; and an operational amplifier, wherein the first capacitor is configured to couple to the second capacitor via the MOS transistor; the operational amplifier is configured to receive a voltage at the first capacitor and output a control voltage; and the MOS transistor is configured to be controlled by the control voltage.

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention generally relates to charge transfer.

Description of Related Art

Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “voltage,” “signal,” “logical signal,” “clock,” “phase,” “capacitor,” “charge,” “current,” “transistor,” “MOS (metal-oxide semiconductor),” “PMOS (p-channel metal oxide semiconductor),” “NMOS (n-channel metal oxide semiconductor),” “source,” “gate,” “drain,” “threshold voltage,” “circuit node,” “ground node,” “operational amplifier,” “virtual ground,” “electrical potential,” “switch,” “open circuit,” “short circuit” “single-ended circuit,” and “differential circuit.” Terms and basic concepts like these are apparent to those of ordinary skill in the art and thus will not be explained in detail here.

Through this disclosure, a logical signal is a signal of two states: “high” and “low,” which can also be re-phrased as “1” and “0.” For brevity, a logical signal in the “high” (“low”) state is simply stated as the logical signal is “high” (“low”), or alternatively, the logical signal is “1” (“0”). Also, for brevity, quotation marks may be omitted and the immediately above is simply stated as the logical signal is high (low), or alternatively, the logical signal is 1 (0), with the understanding that the statement is made in the context of describing a state of the logical signal.

A logical signal is said to be asserted when it is high. A logical signal is said to be de-asserted when it is low.

A clock signal is a cyclic logical signal. For brevity, hereafter, “clock signal” may be simply referred to as “clock.”

FIG. 1shows a schematic diagram of a prior art charge transfer circuit100, which comprises: a first capacitor CI, a second capacitor CF, and an operational amplifier110. The operational amplifier110imposes a virtual ground condition on a circuit node101, thus causing a charge stored on the first capacitor CIto transfer to the second capacitor CF. The principle of the prior art charge transfer circuit100is well known to those of ordinary skill in the art and thus not explained in detail here. An issue with the prior art charge transfer circuit100is: the operational amplifier110needs to provide an output current IOinjected to the circuit node101via the second capacitor CFto impose the virtual ground condition on the circuit node101and thus fulfill the charge transfer. To enable a fast charge transfer, the operational amplifier110should have a high driving capability, which enables a large output current IO. An operational amplifier of a high driving capability is power hungry. Therefore, the prior art charge transfer circuit100is power hungry if a fast charge transfer is sought.

What is desired is a charge transfer circuit that is more power efficient.

BRIEF SUMMARY OF THE INVENTION

Certain embodiments of the present invention involve a transfer of charge stored on a first capacitor to a second capacitor via a MOS (metal oxide semiconductor) transistor, wherein a voltage of a gate terminal of the MOS transistor is controlled by an amplification of a voltage of the first capacitor.

In an embodiment, a circuit comprises: a first capacitor; a second capacitor; a MOS (metal oxide semiconductor) transistor; and an operational amplifier, wherein: the first capacitor is configured to couple to the second capacitor via the MOS transistor; the operational amplifier is configured to receive a voltage at the first capacitor and output a control voltage; and the MOS transistor is configured to be controlled by the control voltage. In an embodiment, the MOS transistor is a PMOS transistor (p-channel metal oxide semiconductor). In another embodiment, the MOS transistor is a NMOS transistor (n-channel metal oxide semiconductor).

In an embodiment, a circuit comprises: a first capacitor; a second capacitor; a MOS (metal oxide semiconductor) transistor; an operational amplifier; a first switch controlled by a first clock signal; a second switch controlled by a second clock signal; and a third switch controlled by a third clock signal, wherein: the first capacitor is configured to receive a charge via the first switch when the first clock signal is asserted, the second capacitor is configured to be reset via the second switch when the second clock signal is asserted, the first capacitor is configured to couple to the second capacitor via the MOS transistor and the third switch when the third clock signal is asserted, the operational amplifier is configured to receive a voltage at the first capacitor and output a control voltage, and the MOS transistor is configured to be controlled by the control voltage. In an embodiment, the MOS transistor is a PMOS transistor (p-channel metal oxide semiconductor). In another embodiment, the MOS transistor is a NMOS transistor (n-channel metal oxide semiconductor). In an embodiment, the first clock signal and the third clock signal are non-overlapping, and also the second clock signal and the third clock signal are non-overlapping.

In an embodiment, a method comprises: storing a voltage at a first capacitor; resetting a voltage at a second capacitor; coupling the first capacitor to the second capacitor via a MOS transistor; generating a control voltage by amplifying a voltage of the first capacitor; and controlling a gate terminal of the MOS (metal oxide semiconductor) transistor using the control voltage. In an embodiment, the MOS transistor is a PMOS transistor (p-channel metal oxide semiconductor). In another embodiment, the MOS transistor is a NMOS transistor (n-channel metal oxide semiconductor). In an embodiment, the storing comprises coupling the first capacitor to an input voltage via a switch controlled by a clock signal that is asserted during the storing. In an embodiment, the resetting comprises coupling the second capacitor to ground node via a switch controlled by a clock signal that is asserted during the resetting. In an embodiment, the coupling comprises coupling the first capacitor to the second capacitor via a serial connection of the MOS transistor and a switch controlled by a clock signal that is asserted during the coupling. In an embodiment, the generating comprises using an operational amplifier.

DETAILED DESCRIPTION OF THE INVENTION

The present invention relates to charge transfer. While the specification describes several example embodiments of the invention considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention.

FIG. 2Ashows a schematic diagram of a charge transfer circuit200A in accordance with an embodiment of the present invention. The charge transfer circuit200A comprises: a source capacitor CS, a destination capacitor CD, a PMOS (p-channel metal oxide semiconductor) transistor220, and an operational amplifier210. Throughout this disclosure, a ground symbol (such as211,212, and213) denotes a ground node, at which an electrical potential is substantially fixed. However, an electrical potential of a first ground node may not be necessarily equal to an electrical potential of a second ground node. For instance, the ground node211may not have the same electrical potential as the ground node212. The operational amplifier210imposes a virtual ground condition on the circuit node201via the PMOS transistor220, thus causing a charge stored on the source capacitor CSto transfer to the destination capacitor CD. A major difference between the charge transfer circuit200A ofFIG. 2Aand the prior art charge transfer circuit100ofFIG. 1is: the operational amplifier110imposes the virtual ground condition on the circuit node101by directly injecting current IOinto the circuit node101, while the operational amplifier210imposes the virtual ground condition on the circuit node201by providing a sufficiently low gate voltage for the PMOS transistor220(e.g., so that its source-to-gate voltage is greater than its threshold voltage) and letting the PMOS transistor220handle the charge transfer. For the charge transfer circuit200A ofFIG. 2Ato have a fast charge transfer, the PMOS transistor220must have a sufficiently large width-to-length ratio and also must be quickly turned on upon a start of the charge transfer. In modern CMOS (complementary metal oxide semiconductor) technologies, a MOS (metal oxide semiconductor) transistor can have a very low threshold voltage (e.g., 300 mV) and also a very small length (e.g. 30 nm), and therefore can have a large width-to-length ratio without exhibiting a large gate capacitance, which is proportional to a product of the width and the length of the MOS transistor. As long as the PMOS transistor220has sufficiently large width-to-length ratio but does not have a large gate capacitance (seen at the circuit node202), the operational amplifier210does not need to have a high driving capability but still can quickly drive the gate voltage of the PMOS transistor220sufficiently low to turn on the PMOS transistor220to enable fast charge transfer. The needed width-to-length ratio of the PMOS transistor220depends on the values of the source capacitor CSand the destination capacitor CD. By way of example: CS=800 fF, CD=400 fF, the width/length of the PMOS transistor220is 16 μm/30 nm, and the gate capacitance of the PMOS transistor220is approximately 20 fF. Therefore, the operational amplifier210ofFIG. 2Aonly needs to drive a 20 fF load. In contrast, if CI=800 fF and CF=400 fF, the operational amplifier110ofFIG. 1needs to drive a 266.7 fF load (i.e., 800 fF in series with 400 fF). The charge transfer circuit200A ofFIG. 2A, therefore, can have a superior power efficiency compared to the prior art charge transfer circuit100ofFIG. 1, since the capacitive load for the operational amplifier is much smaller (more than ten times smaller in the above example). As noted above, the various values detailed above (e.g., threshold voltage, width, length, capacitance) are for illustrative purposes, and that other values may be used depending on the implementation. Details ofFIG. 2Aare self-explanatory (e.g., the source, the gate, and the drain terminals of the PMOS transistor220are connected to circuit nodes201,202, and203, respectively) and apparent to those of ordinary skill in the art and thus not explained in detail here.

Note that what is shown inFIG. 2Ais a simplified schematic diagram that does not show every detail of the charge transfer circuit200A. In particular, a charge must be stored onto the source capacitor CSin the first place, before the charge can be transferred to the destination capacitor CD. In practice, the charge transfer circuit200A is a discrete-time circuit that has multiple phases including a sampling phase and a transfer phase, wherein: a charge is stored onto the source capacitor CSin the sampling phase, and the charge stored onto the source capacitor CSin the sampling phase is transferred to the destination capacitor CDin the transfer phase. In a multiple-phase discrete-time circuit, a plurality of switches controlled by a plurality of clock signals, respectively, are needed, wherein a state of said plurality of clock signals defines a phase of the multiple-phase discrete-time circuit. Since the present invention is primarily concerned with improving power efficiency of charge transfer in the transfer phase,FIG. 2Aonly shows a simplified, equivalent circuit of the charge transfer circuit200A in the transfer phase, wherein: each switch (of said plurality of switches) that is turned on is equivalent to and thus replaced by a short circuit, each switch (of said plurality of switches) that is turned off is equivalent to and thus replaced by an open circuit, and as a result there are no switches explicitly shown inFIG. 2A. There are numerous workable embodiments for actual implementation of the charge transfer circuit200A that can embody the multiple phase operation.FIG. 2Bshows a schematic diagram of an exemplary charge transfer circuit200B that is an embodiment of an actual implementation of the charge transfer circuit200A ofFIG. 2Athat enables a multiple-phase operation. Besides what is shown in the charge transfer circuit200A ofFIG. 2A, the charge transfer circuit200B ofFIG. 2Bfurther comprises a first switch221, a second switch222, and a third switch223controlled by a first clock signal CK1, a second clock signal CK2, and a third clock signal CK3, respectively. Besides, an additional ground node214is shown, and an internal circuit node203′ is labeled. The first clock signal CK1and the third clock signal CK3are non-overlapping; that is, they will not be asserted at the same time. The second clock signal CK2and the third clock signal CK3are also non-overlapping. The first clock signal CK1and the second clock signal CK2, however, can be overlapping. When the first clock signal CK1is asserted, the charge transfer circuit200B is in the sampling phase, wherein an input voltage signal VIis stored onto the source capacitor CSvia the first switch221. When the second clock signal CK2is asserted, the charge transfer circuit200B is in a reset phase, wherein the circuit node203is shorted to the ground node214via the second switch222to reset a charge stored on the destination capacitor CD. When the third clock signal CK3is asserted, the charge transfer circuit200B is in the transfer phase, wherein the first switch221and the second switch222are opened, the third switch223is closed, and the charge transfer circuit200B ofFIG. 2Bis thus equivalent to the charge transfer circuit200A ofFIG. 2A, as mentioned earlier.FIG. 2Bis self-explanatory and details (e.g., the source, the gate, and the drain terminals of the PMOS transistor220are connected to the circuit nodes201,202, and203′, respectively) are apparent to those of ordinary skill in the art and thus not explained in detail here.

Now refer back toFIG. 2A. There is a restriction on the usage of the charge transfer circuit200A ofFIG. 2A. The PMOS transistor220must have a positive source-to-drain voltage, therefore the voltage at the circuit node201must be higher than the voltage at the circuit node203. Circuit designers and/or users need to ensure that this condition holds throughout the charge transfer in an actual application, otherwise the charge transfer circuit200A may not work properly. This condition can be ensured, for instance, if the input voltage VIis sufficiently high when the charge transfer circuit200B ofFIG. 2Bis used for the actual implementation of the transfer circuit200A ofFIG. 2A. If the voltage at the circuit node201is too low for the charge transfer circuit200A ofFIG. 2Ato be workable, an alternative charge transfer circuit200C shown inFIG. 2Ccan be used. The charge transfer circuit200C ofFIG. 2Cis the same as the charge transfer circuit200A ofFIG. 2Aexcept that the PMOS transistor220inFIG. 2Ais replaced by a NMOS (n-channel metal oxide semiconductor) transistor220′ inFIG. 2C. Due to using the NMOS transistor220′, the charge transfer circuit200C can be workable when the voltage at the circuit node201is lower than the voltage at the circuit node203. Those of ordinary skill in the art can add circuitry to the charge transfer circuit200C ofFIG. 2Cso as to enable a multiple phase operation, in a similar way that circuitry is added to the charge transfer circuit200A ofFIG. 2A, resulting in the charge transfer circuit200B ofFIG. 2Bthat enables a multiple phase operation.

The charge transfer circuits200A,200B, and200C shown inFIG. 2A,FIG. 2B, andFIG. 2C, respectively, are embodied in a single-ended circuit topology for purpose of simplicity and ease of illustration of a principle of the present invention. In practice, however, embodiments in form of differential circuit topology are often preferred due to better signal-to-noise ratio, as is understood and appreciated by those of ordinary skill in the art.FIG. 3shows a charge transfer circuit300that embodies the charge transfer circuit200A ofFIG. 2Ain a differential circuit topology. The following highlights differences between the charge transfer circuit300ofFIG. 3and the charge transfer circuit200A ofFIG. 2A: the ground node211inFIG. 2Ais replaced by a ground node311inFIG. 3; the ground node213inFIG. 2Ais replaced by a ground node313inFIG. 3; the circuit node201inFIG. 2Ais replaced by two circuit nodes301P and301M inFIG. 3; the circuit node202inFIG. 2Ais replaced by two circuit nodes302P and302M inFIG. 3; the circuit node203inFIG. 2Ais replaced by two circuit nodes303P and303M inFIG. 3; the operational amplifier210inFIG. 2Ais replaced by a differential operational amplifier310inFIG. 3; the source capacitor CSinFIG. 2Ais replaced by two source capacitors CSPand CSMinFIG. 3; the destination capacitor CDinFIG. 2Ais replaced by two destination capacitors CDPand CDMinFIG. 3; and the PMOS transistor220inFIG. 2Ais replaced by two PMOS transistors320P and320M inFIG. 3. That the charge transfer circuit300ofFIG. 3is a differential circuit embodiment of the charge transfer circuit200A ofFIG. 2Ais clear to those of ordinary skill in the art and thus not explained in detail here. The charge transfer circuit200B ofFIG. 2Band the charge transfer circuit200C ofFIG. 2Ccan be modified into a respective differential circuit embodiment in a similar manner that can be easily worked out by those of ordinary skill. Besides, those of ordinary skill in the art can add circuitry to the charge transfer circuit300ofFIG. 3so as to enable a multiple phase operation, in a similar way that circuitry is added to the charge transfer circuit200A ofFIG. 2A, resulting in the charge transfer circuit200B ofFIG. 2Bthat enables a multiple phase operation.

FIG. 4shows a flow diagram of a method400for charge transfer in accordance with an embodiment of the present invention. The method400comprises: upon start (step401), storing a voltage at a first capacitor (step402); resetting a voltage at a second capacitor (step403); coupling the first capacitor to a second capacitor via a MOS transistor (step404); generating a control voltage by amplifying a voltage of the first capacitor (step405); and controlling a gate terminal of the MOS transistor using the control voltage (step406); this concludes a charge transfer (step407).

Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. For instance, the type of MOS transistors (e.g., p-type or n-type) depicted inFIGS. 2A-3may be interchanged (e.g., to n-type or p-type, respectively) in some embodiments. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.