Memory device and driving circuit adopted by the memory device

A memory device and a driving circuit adopted by the memory device are disclosed. The driving circuit includes a power line, a ground line, and first and second data lines coupled between the power line and the ground line. Each data line comprises 4 driver groups. For the first data line, the first driver group contains an even-stage inverter driver, the second driver group contains the even-stage inverter driver, the third driver group contains an odd-stage inverter driver, and the fourth driver group contains the odd-stage inverter driver. For the second data line, the first driver group contains the odd-stage inverter driver, the second driver group contains the even-stage inverter driver, the third driver group contains the even-stage inverter driver, and the fourth driver group contains the odd-stage inverter driver. The even-stage inverter driver comprises an even number of inverters. The odd-stage inverter driver comprises an odd number of inverters.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to semiconductor circuits, and in particular relates to a memory device and a driving circuit adopted by the memory device.

2. Description of the Related Art

As semiconductor technology advances, transistors sizes of semiconductor circuits are shrunk and a power supply voltage supplied to a semiconductor circuit is decreased. In semiconductor memories, large amounts of memory data are read and written frequently and in high speed, resulting in an escalated scale of power noises in power signals. Noises in a power supply to a semiconductor memory circuit will lead to decreased signal-to-noise ratio (SNR) and increased bit error rate (BER), both cause damages to circuit performance.

Therefore, a memory device and a driving circuit adopted by the memory device for reducing power noise in the power supply are required.

BRIEF SUMMARY OF THE INVENTION

A driving circuit is disclosed, comprising a power line, a ground line, and first and second data lines. The first and second data lines are coupled between the power line and the ground line. Each data line comprises 4 driver groups. For the first data line, the first driver group contains an even-stage inverter driver, the second driver group contains the even-stage inverter driver, the third driver group contains an odd-stage inverter driver, and the fourth driver group contains the odd-stage inverter driver. For the second data line, the first driver group contains the odd-stage inverter driver, the second driver group contains the even-stage inverter driver, the third driver group contains the even-stage inverter driver, and the fourth driver group contains the odd-stage inverter driver. The even-stage inverter driver comprises an even number of inverters. The odd-stage inverter driver comprises an odd number of inverters.

Another embodiment of a memory device is provided, comprising a power line, a ground line, and a memory circuit. The memory circuit, coupled between the power line and the ground line, comprises a driving circuit and a memory cell array. The diving circuit comprises first and second data lines, coupled between the power line and the ground line, driving memory data to and from the memory cell array, each data line comprises 4 driver groups. For the first data line, the first driver group contains an even-stage inverter driver, the second driver group contains the even-stage inverter driver, the third driver group contains an odd-stage inverter driver, and the fourth driver group contains the odd-stage inverter driver. For the second data line, the first driver group contains the odd-stage inverter driver, the second driver group contains the even-stage inverter driver, the third driver group contains the even-stage inverter driver, and the fourth driver group contains the odd-stage inverter driver. The even-stage inverter driver comprises an even number of inverters. The odd-stage inverter driver comprises an odd number of inverters.

DETAILED DESCRIPTION OF THE INVENTION

As disclosed herein, memory devices may refer to Dynamic Random Access Memory (DRAM), Static DRAM (SDRAM), Electrically Erasable and Programmable ROM (EEPROM), NAND flash memory, NOR flash memory, Phase-change RAM (PRAM), Magnetic RAM (MRAM), and Ferroelectric RAM (FRAM), and resistive memory devices (ReRAMs).

FIG. 1is a block diagram of a memory device1according to an embodiment of the invention, comprising an address buffer (ADB)10, a data buffer (DATAB)12, a word-line decoder14, a bit-line decoder, sense amplifier, and write driver16, and a memory cell array18. The memory device1is formed on a silicon substrate, for example, using a complementary metal oxide semiconductor (CMOS) process. The memory device1may be a semiconductor memory housed in a package, and may be a memory macro (an intellectual property core (IP)) that is embedded in a system large scale integrated circuit (system LSI) or the like. The memory device1may be a non-clock-synchronized-type semiconductor memory or a clock-synchronized-type semiconductor memory.

In some embodiments, all circuits or all analog circuits of the memory device1are connected to a common external power source via common power and ground rails. For example, all circuits in the data buffer DATAB12and the address buffer ADB10are connected to a common power source Vext via a common power line vdd and ground line vss which can be modeled as inductors connected in series, as depicted inFIG. 2. As a consequence, when the circuits including active loads draw currents from the power source, the time varying currents create a power noise across the inductors.

Turning back toFIG. 1, the data buffer DATAB12drives data signals DATA[0. . .127] via a data bus and outputs the received data signals DATA[0. . .127] to and from the bit-line decoder, sense amplifier, and write driver16, where the received data signals DATA[0. . .127] for reading and writing into a memory cell MC of the memory cell array18. The address buffer ADB10receives address signals AD via an address bus, and outputs high order bits of the address signals AD, for example, a row address RAD to the word-line decoder14and high order bits of the address signals AD, for example, a column address CAD to the bit-line decoder, sense amplifier, and write driver16. The word-line decoder14decodes the row address RAD and selects one of the word drivers to activate a corresponding word line WL from a low level, for example, a ground potential VSS, to a high level, for example, a power supply voltage VDD for a given period. The bit-line decoder, sense amplifier, and write driver16decodes the column address CAD and selects one of the write drivers to activate a corresponding bit line BL from a low level, for example, a ground potential VSS, to a high level, for example, a power supply voltage VDD for a given period.

Accordingly, the data buffer DATAB12contains 128-bit data lines and the address buffer ADB10contains 32-bit data lines. In order to reduce the power noise induced on the power and ground lines vdd and vss by 50 percent, data buffer circuits containing two or multiples of two data lines can adopt a specific order of driver types as shown inFIG. 3. That is, each data line of the data buffer DATAB12and the address buffer ADB10includes 4 driver groups with the specific order of the driver types inFIG. 3. The 4 driver groups are a driver group1, a driver group2, a driver group3, and a driver group4. Take the data buffer DATAB12as an example, each data line contains 4 driver groups formed by even-stage inverter drivers A or odd-stage inverter drivers B, where the even-stage inverter drivers A contains an even-number of inverters and the odd-stage inverter drivers B contains an odd-number of inverters. For example, the even-stage inverter driver A is formed by 2 inverters, and the odd-stage inverter driver A is formed by 3 inverters. An inverter is not limited to an inverter logic gate, but can be any type of inverting logic gate. The 128-bit data are divided into 4 data groups, namely Data[0. . .31], Data[32. . .63], Data[64. . .95], and Data[96. . .127] respectively. Each data group are coupled between the power and ground lines vdd and vss (not shown), and transmits data signals DATA via the data bus from 4 places of a memory chip.

The data group Data[0. . .31] contains 32 data lines, each data line contains 4 drivers arranged in an order of an even-stage inverter driver D00, an even-stage inverter driver D01, an odd-stage inverter driver D02, and an odd-stage inverter driver D03. The data group Data[32. . .63] contains 32 data lines, each data line contains 4 drivers arranged in an order of an odd-stage inverter driver D10, an even-stage inverter driver D11, an even-stage inverter driver D12, and an odd-stage inverter driver D13. The data group Data[64. . .95] contains 32 data lines, each data line contains 4 drivers arranged in the same order as in the data group Data[0. . .31], including an even-stage inverter driver D20, an even-stage inverter driver D21, an odd-stage inverter driver D22, and an odd-stage inverter driver D23. The data group Data[96. . .127] contains 32 data lines, each data line contains 4 drivers arranged in the same order as in the data group Data[32. . .63], including an odd-stage inverter driver D30, an even-stage inverter driver D31, an even-stage inverter driver D32, and an odd-stage inverter driver D33.

With the circuit arrangement inFIG. 3, the data buffer DATAB12can deliver data Data[0. . .127] between the data bus and the memory cell array while reducing the power noise on the power and ground lines.FIGS. 4 through 7illustrate four embodiments in which the data buffer DATAB12reduces the power noise by 50% during data delivery.

Referring toFIG. 3and Table 1 below, Table 1 shows output transients of inverter drivers D00through D33in a first embodiment, where a symbol (r) indicates that the output exhibits a rising transient and a symbol (f) indicates that the output exhibits a falling transient. For the data group Data[0. . .31], the even-stage inverter driver D00receives rising transients and outputs rising transients, the even-stage inverter driver D01receives rising transients and outputs rising transients, the odd-stage inverter driver D02receives rising transients and outputs falling transients, and the odd-stage inverter driver D03receives falling transients and outputs rising transients. For the data group Data[32. . .63], the odd-stage inverter driver D10receives rising transients and outputs falling transients, the even-stage inverter driver D11receives falling transients and outputs falling transients, the even-stage inverter driver D12receives falling transients and outputs falling transients, and the odd-stage inverter driver D13receives falling transients and outputs rising transients. For data group Data[64. . .95], the even-stage inverter driver D20receives rising transients and outputs rising transients, the even-stage inverter driver D21receives rising transients and outputs rising transients, the odd-stage inverter driver D22receives rising transients and outputs falling transients, and the odd-stage inverter driver D23receives falling transients and outputs rising transients. For the data group Data[96. . .127], the odd-stage inverter driver D30receives rising transients and outputs falling transients, the even-stage inverter driver D31receives falling transients and outputs falling transients, the even-stage inverter driver D32receives falling transients and outputs falling transients, and the odd-stage inverter driver D33receives falling transients and outputs rising transients.

Turning toFIG. 4, since the 4 data groups are connected to the power and ground lines, the net power noises on the power line vdd and the ground line vss are the combinations of all rising and falling transients of the 4 data groups Data[0. . .31], Data[32. . .63], Data[64. . .95], and Data[96. . .127] of the data buffer DATAB12. As a result, for the driver group1, the rising and the falling transients will be cancelled out, resulting in substantially no power noise on the power line vdd and the ground line vss; for the driver group2, the rising and the falling transients will be cancelled out, resulting in substantially no power noise on the power line vdd and the ground line vss; for the driver group3, all falling transients will be added up, inducing a net power noise with a positive voltage on the power line vdd and the ground line vss; for the driver group4, all rising transients will be added up, inducing a net power noise with a negative voltage on the power line vdd and the ground line vss. In other words, with the circuit configuration inFIG. 3and the embodiment inFIG. 4, when the data buffer DATAB12is in operation, the power noise only occurs at 50% of the time. In comparison to the conventional buffer circuit, the circuit arrangement inFIG. 3results in a 50% power noise reduction.

Referring toFIG. 3and Table 2 below, Table 2 shows output transients of inverter drivers D00through D33in a second embodiment, where a symbol (r) indicates that the output exhibits a rising transient and a symbol (f) indicates that the output exhibits a falling transient. For the data group Data[0. . .31], the even-stage inverter driver D00receives falling transients and outputs falling transients, the even-stage inverter driver D01receives falling transients and outputs falling transients, the odd-stage inverter driver D02receives falling transients and outputs rising transients, and the odd-stage inverter driver D03receives rising transients and outputs falling transients. For the data group Data[32. . .63], the odd-stage inverter driver D10receives falling transients and outputs rising transients, the even-stage inverter driver D11receives rising transients and outputs rising transients, the even-stage inverter driver D12receives rising transients and outputs rising transients, and the odd-stage inverter driver D13receives rising transients and outputs falling transients. For data group Data[64. . .95], the even-stage inverter driver D20receives falling transients and outputs falling transients, the even-stage inverter driver D21receives falling transients and outputs falling transients, the odd-stage inverter driver D22receives falling transients and outputs rising transients, and the odd-stage inverter driver D23receives rising transients and outputs falling transients. For the data group Data[96. . .127], the odd-stage inverter driver D30receives falling transients and outputs rising transients, the even-stage inverter driver D31receives rising transients and outputs rising transients, the even-stage inverter driver D32receives rising transients and outputs rising transients, and the odd-stage inverter driver D33receives rising transients and outputs falling transients.

Turning toFIG. 5, since the 4 data groups are connected to the power and ground lines, the net power noises on the power line vdd and the ground line vss are the combinations of all rising and falling transients of the 4 data groups Data[0. . .31], Data[32. . .63], Data[64. . .95], and Data[96. . .127] of the data buffer DATAB12. As a result, for the driver group1, the rising and the falling transients will be cancelled out, resulting in substantially no power noise on the power line vdd and the ground line vss; for the driver group2, the rising and the falling transients will be cancelled out, resulting in substantially no power noise on the power line vdd and the ground line vss; for the driver group3, all rising transients will be added up, inducing a net power noise with a negative voltage on the power line vdd and the ground line vss; for the driver group4, all falling transients will be added up, inducing a net power noise with a positive voltage on the power line vdd and the ground line vss. In other words, with the circuit configuration inFIG. 3and the embodiment inFIG. 5, when the data buffer DATAB12is in operation, the power noise only occurs at 50% of the time. In comparison to the conventional buffer circuit, the circuit arrangement inFIG. 3results in a 50% power noise reduction.

Referring toFIG. 3and Table 3 below, Table 3 shows output transients of inverter drivers D00through D33in a third embodiment, where a symbol (r) indicates that the output exhibits a rising transient and a symbol (f) indicates that the output exhibits a falling transient. For the data group Data[0. . .31], the even-stage inverter driver D00receives rising transients and outputs rising transients, the even-stage inverter driver D01receives rising transients and outputs rising transients, the odd-stage inverter driver D02receives rising transients and outputs falling transients, and the odd-stage inverter driver D03receives falling transients and outputs rising transients. For the data group Data[32. . .63], the odd-stage inverter driver D10receives falling transients and outputs rising transients, the even-stage inverter driver D11receives rising transients and outputs rising transients, the even-stage inverter driver D12receives rising transients and outputs rising transients, and the odd-stage inverter driver D13receives rising transients and outputs falling transients. For data group Data[64. . .95], the even-stage inverter driver D20receives rising transients and outputs rising transients, the even-stage inverter driver D21receives rising transients and outputs rising transients, the odd-stage inverter driver D22receives rising transients and outputs falling transients, and the odd-stage inverter driver D23receives falling transients and outputs rising transients. For the data group Data[96. . .127], the odd-stage inverter driver D30receives falling transients and outputs rising transients, the even-stage inverter driver D31receives rising transients and outputs rising transients, the even-stage inverter driver D32receives rising transients and outputs rising transients, and the odd-stage inverter driver D33receives rising transients and outputs falling transients.

Turning toFIG. 6, since the 4 data groups are connected to the power and ground lines, the net power noises on the power line vdd and the ground line vss are the combinations of all rising and falling transients of the 4 data groups Data[0. . .31], Data[32. . .63], Data[64. . .95], and Data[96. . .127] of the data buffer DATAB12. As a result, for the driver group1, all rising transients will be added up, inducing a net power noise with a negative voltage on the power line vdd and the ground line vss; for the driver group2, all rising transients will be added up, inducing a net power noise with a negative voltage on the power line vdd and the ground line vss; for the driver group3, the rising and the falling transients will be cancelled out, resulting in substantially no power noise on the power line vdd and the ground line vss; for the driver group4, the rising and the falling transients will be cancelled out, resulting in substantially no power noise on the power line vdd and the ground line vss. In other words, with the circuit configuration inFIG. 3and the embodiment inFIG. 6, when the data buffer DATAB12is in operation, the power noise only occurs only at 50% of the time. In comparison to the conventional buffer circuit, the circuit arrangement inFIG. 3results in a 50% power noise reduction.

Referring toFIG. 3and Table 4 below, Table 4 shows output transients of inverter drivers D00through D33in a fourth embodiment, where a symbol (r) indicates that the output exhibits a rising transient and a symbol (f) indicates that the output exhibits a falling transient. For the data group Data[0. . .31], the even-stage inverter driver D00receives falling transients and outputs falling transients, the even-stage inverter driver D01receives falling transients and outputs falling transients, the odd-stage inverter driver D02receives falling transients and outputs rising transients, and the odd-stage inverter driver D03receives rising transients and outputs falling transients. For the data group Data[32. . .63], the odd-stage inverter driver D10receives rising transients and outputs falling transients, the even-stage inverter driver D11receives falling transients and outputs falling transients, the even-stage inverter driver D12receives falling transients and outputs falling transients, and the odd-stage inverter driver D13receives falling transients and outputs rising transients. For data group Data[64. . .95], the even-stage inverter driver D20receives falling transients and outputs falling transients, the even-stage inverter driver D21receives falling transients and outputs falling transients, the odd-stage inverter driver D22receives falling transients and outputs rising transients, and the odd-stage inverter driver D23receives rising transients and outputs falling transients. For the data group Data[96. . .127], the odd-stage inverter driver D30receives rising transients and outputs falling transients, the even-stage inverter driver D31receives falling transients and outputs falling transients, the even-stage inverter driver D32receives falling transients and outputs falling transients, and the odd-stage inverter driver D33receives falling transients and outputs rising transients.

Turning toFIG. 7, since the 4 data groups are connected to the power and ground lines, the net power noises on the power line vdd and the ground line vss are the combinations of all rising and falling transients of the 4 data groups Data[0. . .31], Data[32. . .63], Data[64. . .95], and Data[96. . .127] of the data buffer DATAB12. As a result, for the driver group1, all falling transients will be added up, inducing a net power noise with a positive voltage on the power line vdd and the ground line vss; for the driver group2, all falling transients will be added up, inducing a net power noise with a positive voltage on the power line vdd and the ground line vss; for the driver group3, the rising and the falling transients will be cancelled out, resulting in substantially no power noise on the power line vdd and the ground line vss; for the driver group4, the rising and the falling transients will be cancelled out, resulting in substantially no power noise on the power line vdd and the ground line vss. In other words, with the circuit configuration inFIG. 3and the embodiment inFIG. 6, when the data buffer DATAB12is in operation, the power noise only occurs only at 50% of the time. In comparison to the conventional buffer circuit, the circuit arrangement inFIG. 3results in a 50% power noise reduction.

As used herein, the term “determining” encompasses calculating, computing, processing, deriving, investigating, looking up (e.g., looking up in a table, a database or another data structure), ascertaining and the like. Also, “determining” may include resolving, selecting, choosing, establishing and the like.

The term “or” used herein is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from the context, the phrase “X employs A or B” is intended to mean any of the natural inclusive permutations. In addition, the articles “a” and “an” as used in this application and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from the context to be directed to a singular form.

The various illustrative logical blocks, modules and circuits described in connection with the present disclosure may be implemented or performed with a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array signal (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any commercially available processor, controller, microcontroller or state machine.

The operations and functions of the various logical blocks, modules, and circuits described herein may be implemented in circuit hardware or embedded software codes that can be accessed and executed by a processor.