Chip package structure and process for fabricating the same

A chip package structure comprises a carrier, a chip and an underfill. The chip has an active surface on which a plurality of bumps are formed. The chip is flip-chip bonded onto the carrier with the active surface facing the carrier, and is electrically connected to the carrier through the bumps. The underfill is filled between the chip and the carrier. A portion of the underfill near the chip serves as a first underfill portion. The portion of the underfill near the carrier serves as a second underfill portion. The Young's modulus of the first underfill portion is smaller than the Young's modulus of the second underfill portion. The second underfill portion can be optionally replaced with a selected encapsulation. The selected encapsulation covers the chip and the carrier around the chip.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application serial no. 93109438, filed on Apr. 6, 2004. All disclosure of the Taiwan application is incorporated herein by reference.

BACKGROUND OF THE IVENTION

1. Field of the Invention

This invention relates to a chip package structure and a process of fabricating the same. More particularly, this invention relates to a chip package structure formed by flip chip bonding and a process of fabricating the same.

2. Brief Description of Related Art

Electronic devices have been increasingly developed to meet demands of digitalization, network, LAN connection and humanization in use. Therefore, high operation speed, multifunctions, integration, compactness and competitive prices are the key features for commercial success. The Chip package technology must catch up the development trend of the electronic devices with high density and compactness. A flip chip technology uses bumps as the connection intermedium to a carrier, which shortens wire length compared to a conventional wire bonding. Short wire length facilitates increase in signal transmission between the chip and the carrier. Therefore, the flip chip technology has become the main stream in the high-pin-count packaging field.

FIG. 1is a cross-sectional view of a conventional chip package structure formed by a flip chip technology. Referring toFIG. 1, a chip50of a chip package structure40has an active surface52on which a plurality of bumps60are respectively mounted. A plurality of bonding pads54are formed on the active surface52. A plurality of contacts84are formed on a carrier80. The chip50electrically connects to the carrier80via the bonding pads54, the bumps60and the contacts84.

Furthermore, in order to protect the chip50from being damaged due to the moisture and protect the bumps60connecting the chip50and the carrier80from being damaged due to the mechanical stress, an underfill70is filled between the chip50and the carrier80. However, since there is a mismatch in coefficient of thermal expansion (CTE) between the chip50, the bumps60, the underfill70and the carrier80, the chip package structure40tends to fail due to the thermal stress resulting from temperature difference during thermal cycles.

Upper layers of the chip are called as interconnection that consists of a plurality of conductive layers and dielectric layers sandwiched by the conductive layers. When the Young's modulus of the underfill is high, delamination between the conductive layers and the dielectric layers occurs due to the thermal stress, which deteriorates the interconnections and leads to chip failure. Complying with the appearance of the copper process applied in the semiconductor manufacturing technology, the material constituent of the conductive layers and the dielectric layers are from the set of aluminum and silicon dioxide to the set of copper and organic materials. The adhesion between copper and low-k dielectrics is lower than that between aluminum and silicon dioxide. Therefore, delamination between the copper layer and the low-k dielectrics occurs more often.

Furthermore, when the Young's modulus of the underfill is low, the thermal stress tends to cause cracking of bumps near the carrier, and thereby significantly decreasing the reliability of electric connection between the chip and the carrier. Therefore, how to avoid the damage of interconnection of the chip and the bump due to the CTEs mismatch between the chip, the bumps, the underfill and the carrier is an important issue in this field.

SUMMARY OF THE INVENTION

Therefore, the invention is directed to a chip package structure and a process of fabricating the same capable of reducing the problems caused by coefficient of thermal expansion mismatch between the chip, the bumps, the underfill and the carrier to reduce damage to the interconnection of the chip and the bumps.

According to a first embodiment of the invention, a chip package structure of the invention includes a carrier, a chip and an underfill. The carrier has a first surface and a second surface opposite to the first surface. The chip has an active surface on which a plurality of bumps are formed. The chip is bonded to the first surface of the carrier with the active surface of the chip facing thereto, and electrically connects to the carrier via the bumps. The underfill fills between the chip and the carrier. The portion of the underfill near the chip serves as a first underfill portion. The portion of the underfill near the carrier serves as a second underfill portion. The Young's modulus of the first underfill portion is smaller than the Young's modulus of the second underfill portion.

In the present embodiment of the present invention, the Young's modulus of the first underfill portion is smaller than 7E9 Pa, for example, and the glass transition temperature (Tg) thereof is smaller than 100° C., for example. The Young's modulus of the second underfill portion is in a range of 7E9 to 20E9 Pa, for example, and the glass transition temperature (Tg) thereof is larger than 140° C., for example.

Furthermore, chip package structure of this embodiment may further include an encapsulation covering the chip and the carrier around the chip. The carrier can be a package substrate, for example.

According to a second embodiment of the invention, a chip package structure of the invention includes a carrier, a chip, an underfill and an encapsulation. The chip has an active surface on which a plurality of bumps are formed. The carrier has a first surface and a second surface opposite to the first surface. The chip is bonded to the first surface of the carrier with the active surface of the chip facing thereto, and electrically connects to the carrier via the bumps. The underfill fills the part near the chip that between the chip and the carrier. The encapsulation fills between the underfill and the carrier and covers the chip and the carrier around the chip.

In the second embodiment of the present invention, the Young's modulus of the underfill is smaller than 7E9 Pa, for example, and the glass transition temperature (Tg) thereof is smaller than 100° C., for example. The carrier can be a package substrate, for example.

According to a third embodiment of the present invention, a chip packaging process is provided. First, a carrier and a chip are provided. The carrier has a first surface and a second surface opposite to the first surface. The chip has an active surface on which a plurality of bumps are formed. Than, a first underfill is formed on the active surface of the chip. The first underfill is located between the bumps but does not cover the bumps. The height of the bumps is larger than the thickness of the first underfill. After, the chip is flip-chip bonded onto the first surface of the carrier and electrically connected to the carrier via the bumps. Finally, a second underfill is filled between the first underfill and the carrier. The Young's modulus of the first underfill is smaller than that of the second underfill.

In the third embodiment of the present invention, after the second underfill has been formed, an encapsulation may further applied over the chip and the carrier around the chip.

According to a fourth embodiment of the present invention, a chip packaging process is provided. First, a carrier and a chip are provided. The chip has an active surface on which a plurality of first bumps are formed. The carrier has a first surface and a second surface opposite to the first surface. Than, a first underfill is formed on the active surface of the chip and the first bumps are exposed. After, a plurality of second bumps are correspondingly formed on the first bumps. Thereafter, the chip is flip-chip bonded onto the first surface of the carrier and is electrically connected to the carrier via the first and second bumps. Finally, a second underfill is filled between the first underfill and the carrier. The Young's modulus of the first underfill is smaller than the Young's modulus of the second underfill.

In this embodiment of the present invention, the step of exposing the first bumps includes, for example, grinding the first underfill until the first bumps are exposed. Furthermore, after the second underfill has been formed, an encapsulation may further applied over the chip and the carrier around the chip.

According to a fifth embodiment of the present invention, a chip packaging process is provided. First, a carrier and a chip are provided. The carrier has a first surface and a second surface opposite to the first surface. The chip has an active surface on which a plurality of bumps are formed. Then, an underfill is formed on the active surface of the chip and is located between the bumps without covering the bumps. The height of the bumps is larger than the thickness of the underfill. After, the chip is flip-chip bonded onto the first surface of the carrier and is electrically connected to the carrier via the bumps. Finally, an encapsulation is applied over the chip and the carrier around the chip. The encapsulation fills up between the underfill and the carrier.

According to a sixth embodiment of the present invention, a chip packaging process is provided. First, a carrier and a chip are provided. The carrier has a first surface and a second surface opposite to the first surface. The chip has an active surface on which a plurality of first bumps are formed. Than, an underfill is formed on the active surface of the chip and the first bumps are exposed. After, a plurality of second bumps are correspondingly formed on the first bumps. Next, the chip is flip-chip bonded on the first surface of the carrier and is electrically connected to the carrier via the first and second bumps. Finally, an encapsulation is applied over the chip and the carrier around the chip. The encapsulation fills up between the underfill and the carrier.

In this embodiment of the present invention, the step of exposing the first bumps includes, for example, grinding the first underfill until the first bumps are exposed.

Since the Young's modulus of the first underfill near the chip is smaller than that of the second underfill near the carrier, or the second underfill is replaced with the encapsulation having Young's modulus larger than that of the first underfill, the chip package structure is capable of not only reducing damage to the chip but also avoiding crack of the bumps due to the CTEs mismatch between the chip, the bumps, the carrier and the underfill.

DETAILED DESCRIPTION OF EMBODIMENTS

First Embodiment

FIGS. 2A–2Eare cross-sectional views showing a process of fabricating a chip package structure according to a first embodiment of the invention. Referring toFIGS. 2A–2E, A carrier110and a chip120are provided first. The carrier110is illustrated inFIG. 2C. The carrier can be, for example, an organic package substrate. The carrier110has a first surface S1and a second surface S2opposite to the first surface S1. The first surface S1and the second surface S2respectively have a plurality of contacts112aand112bformed thereon. Furthermore, a plurality of solder balls114are mounted on contacts112bin array to facilitate the electric connection to a printed circuit board (PCB) (not shown) in a subsequent Ball Grid Array (BGA) packaging.

The chip120has an active surface122on which a plurality of bumps124are formed thereon. The active surface122further has a plurality of bonding pads126and a passivation layer128thereon. The passivation layer128exposes the bonding pads126and is used to protect the chip120. An under bump metallurgy (UBM)132forming from a patterned metallic layer may further dispose on each bonding pad126. The bumps124are mounted on the UBMs132.

Referring toFIG. 2B, a first underfill142is formed on the active surface122of the chip120between the bumps124, without covering the bumps124. The height of the bumps124is larger than the thickness of the first underfill142. That is, the bumps124protrude over the first underfill142.

Referring toFIG. 2C, the chip120is flip-chip bonded onto the first surface S1of the carrier110and is electrically connected to the carrier110via the bumps124.

Referring toFIG. 2D, a second underfill144is filled between the first underfill142and the carrier110. The Young's modulus of the first underfill142is smaller than that of the second underfill144.

Referring toFIG. 2E, an encapsulation160is further applied over the chip120and the carrier110around the chip120after the second underfill144has been formed to protect the chip120from being damaged during marking and moving.

Referring toFIG. 2E, a chip package structure100according to a first embodiment of the invention includes the carrier110, the chip120and an underfill140. The chip120has an active surface122on which a plurality of bumps124are formed thereon. The chip120is flip-chip bonded to a first surface S1of the carrier110with the active surface122of the chip120facing thereto and is electrically connected to the carrier110via the bumps124. The underfill140is filled between the chip120and the carrier110. The portion of the underfill140near the chip120serves as a first underfill portion142. The portion of the underfill140near the carrier110serves as a second underfill portion144. The Young's modulus of the first underfill portion142is smaller than the Young's modulus of the second underfill portion144.

In this embodiment, the Young's modulus of the first underfill portion142is smaller than 7E9 Pa, for example, and the glass transition temperature (Tg) thereof is smaller than 100° C., for example. The Young's modulus of the second underfill portion144is in a range of about 7E9 to 20E9 Pa, for example, and the glass transition temperature (Tg) thereof is larger than 140° C., for example. Furthermore, chip package structure100may further include an encapsulation160covering the chip120and the carrier110around the chip120.

Second Embodiment

FIGS. 3A–3Gare cross-sectional views showing a process of fabricating a chip package structure according to a second embodiment of the invention. Referring toFIGS. 3A–3G, a carrier210and a chip220are provided first. The carrier210and the chip220are similar to the carrier110and the chip120in the first embodiment and thus the description thereof is omitted herein.

Referring toFIG. 3B, a first underfill242is formed on an active surface222of the chip220. The first underfill242covers the first bumps224athat are formed on the active surface222of the chip220. The method of forming the first underfill242includes dispensing the first underfill material over the active surface222of the chip220and curing the first underfill material to form the first underfill242.

Referring toFIG. 3C, a part of the first underfill242is removed by grinding or other methods to expose the first bumps224a.

Referring toFIG. 3D, a second bump224bis formed on each of the first bumps224a.

Referring toFIG. 3E, the chip220is flip-chip bonded on the carrier210and is electrically connected to the carrier210via the first and second bumps224a,224b.

Referring toFIG. 3F, a second underfill244is filled between the first underfill242and the carrier210. The Young's modulus of the first underfill242is smaller than that of the second underfill244. The preferred Young's modulus and glass transition temperature of the first and second underfill242,244are identical to those in the first embodiment.

Referring toFIG. 3G, an encapsulation260may further applied over the chip220and the carrier210around the chip220after the second underfill244has been formed. A chip package structure200of this embodiment has the same features as the chip package structure100in the first embodiment.

FIGS. 4A–4Dare cross-sectional views showing a process of fabricating the second bumps in the chip package structure according to a second embodiment of the invention. The step of forming the second bumps is not limited to the process illustrated below. A photoresist270is formed on the chip220to cover the first underfill242and the first bumps224afirst. Then, a plurality of openings272are formed in the photoresist270to expose the first bumps224a. Next, a solder material is filled in the openings272to form a plurality of solder bumps234. Thereafter, the photoresist270is removed. Final, the solder bumps234are reflowed to form a plurality of bumps224bon the first bumps224a, as shown inFIG. 3D. The photoresist270can be, for example, a dry film or liquid photoresist. The step of filling the solder material includes, for example, stencil printing.

Third Embodiment

FIG. 5is a cross-sectional view of a chip package structure according to a third embodiment of the invention. The process of forming the package structure before applying the encapsulation is similar to the process described with reference toFIGS. 2A–2C. Thereafter, an encapsulation162is applied over the chip120and the carrier110around the chip120. The encapsulation162fills up between the underfill142and the carrier110.

A chip package structure102of this embodiment includes the carrier110, the chip120, the first underfill142and the encapsulation160. The chip120has an active surface122on which the bumps124are formed thereon. The chip120is flip-chip bonded on the first surface S1of the carrier110, with the active surface122facing the carrier thereto, and is electrically connected to the carrier via the bumps124. The first underfill142is filled between the chip120and the carrier110near the chip120. The encapsulation160is filled between the first underfill142and the carrier110to cover the chip120and the carrier110around chip120.

In this embodiment, the Young's modulus of the first underfill142is smaller than, for example, 7E9 Pa. The glass transition temperature of the first underfill142is smaller than 100° C.

Fourth Embodiment

FIG. 6is a cross-sectional view of a chip package structure according to a fourth embodiment of the invention. The process of forming the package structure before applying the molding material is similar to the process described with reference toFIGS. 3A–3E. Thereafter, an encapsulation262is applied over the chip220and the carrier210around the chip220. The encapsulation262fills up between the underfill242and the carrier210. The chip package structure202of this embodiment has the same features as the chip package structure102of the third embodiment.

As described above, in the chip package structure of the invention, the Young's modulus of the first underfill near the chip is smaller than that of the second underfill near the carrier. Alternatively, the second underfill can be replaced with an encapsulation having a Young's modulus larger than the Young's modulus of the first underfill. Therefore, the chip package structure of the invention is not only capable of reducing damage to the chip due to the high Young's modulus underfill, but also cracking of the bump due to the low Young's modulus underfill is effectively reduced. Furthermore, a part of the underfill is formed on the chip during the bump formation process. Therefore, the need of filling the encapsulation between the chip and the carrier by capillarity method is greatly reduced, thereby increasing the efficiency of the chip packaging process.

Realizations in accordance with the present invention therefore have been described in the context of particular embodiments. These embodiments are meant to be illustrative and not limiting. Many variations, modifications, additions, and improvements are possible. Accordingly, plural instances may be provided for components described herein as a single instance. Additionally, structures and functionality presented as discrete components in the exemplary configurations may be implemented as a combined structure or component. These and other variations, modifications, additions, and improvements may fall within the scope of the invention as defined in the claims that follow.