Fast and accurate capacitance checker

Switching cells and decoupling capacitors in an integrated circuit design may be assessed to ensure voltage stability during high-speed switching events. Assessment of the switching cells and decoupling capacitors may include identifying the locations of the switching cells and the decoupling capacitors and dividing the integrated circuit design into a number of equally sized bins. Selected bins for each switching cell may be identified. The selected bin for each switching cell may be assessed, along with one or more bins neighboring the selected bin, to determine if a sufficient number of decoupling capacitors are available in these bins to provide voltage stability for each switching cell in the integrated circuit design.

BACKGROUND

1. Technical Field

Embodiments described herein relate to integrated circuit layouts and designs. More particularly, the embodiments described herein relate to analyzing integrated circuit designs and modifying the integrated circuit design based on the design analysis.

2. Description of Related Art

For deep sub-micron technologies, IR drop (voltage drop across the device) in the power grid of an integrated circuit due to switching activity (e.g., high-speed switching activity) may have performance implications, especially for high-speed integrated circuits. Typically, in order to ensure voltage stability (and minimize IR drop) during high-speed switching events, an integrated circuit design may be analyzed to make sure there is a sufficient number of decoupling capacitors (dcaps) placed locally around each high-speed switching cell (e.g., clock buffers) in the design so that there is enough charge available for each high-speed switching cell. The design may also be analyzed to make sure that the dcaps associated with a high-speed switching cell are located within a certain distance from the cell. Having the dcaps closer to the high-speed switching cell increases effectiveness of the dcaps.

For a typical integrated circuit design, the number of high-speed switching cells (e.g., clock buffers) may be in the thousands while the number of dcaps, or dcap cells, may be in the millions. A conventional approach to analyzing the integrated circuit design is to check the location of each high-speed switching cell against the location of all the dcaps in the design using a computer processor. Such an approach may, however, be time consuming and cumbersome as it would require on the order of 1 billion checks between switching cells and dcaps in a typical integrated circuit design. For example, an integrated circuit design with 15,000 high-speed switching cells (clock buffers) and 5 million dcaps may take around 11 hours to check using the computer processor. Additionally, it may be difficult using this approach to ensure accuracy in associating dcaps with individual switching cells if neighboring switching cells are relatively close together (e.g., the neighboring switching cells are a distance apart that is less than the allowable distance between a switching cell and a dcap).

SUMMARY

In certain embodiments, a process is used to assess switching cells and decoupling capacitors in an integrated circuit design. The switching cells and decoupling capacitors may be assessed to determine if each switching cell in the design has a sufficient number of decoupling capacitors available to it in order to provide voltage stability in the switching cell. Assessment of the switching cells and decoupling capacitors may include identifying x- and y-coordinates of each switching cell and each decoupling capacitor in the design. The design may be divided into a grid having a desired number of equally sized bins. In certain embodiments, the bins are square bins of equal size and the design is divided into a grid with an equal number of columns and rows.

Each decoupling capacitor may be associated with a bin in the grid that contains the x- and y-coordinates of the decoupling capacitor. A selected bin may be identified for each switching cell in the grid (e.g., the design). For each selected bin, bins that neighbor the selected bin are identified. The neighboring bins may be adjacent a side or a corner of the selected bin.

In certain embodiments, each selected bin and one or more of its neighboring bins are assessed to determine if there is a sufficient number of decoupling capacitors in these bins that are available to each switching cell in the selected bin. The sufficient number of available decoupling capacitors may be a number of decoupling capacitors needed to provide voltage stability in each switching cell. In some embodiments, each decoupling capacitor in the grid is associated with, or assigned to, only one switching cell to avoid overlapping usage of decoupling capacitors. In certain embodiments, the decoupling capacitors available to a switching cell are within a selected distance form the switching cell.

While the embodiments described in this disclosure may be susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. The drawings may not be to scale. It should be understood that the drawings and detailed description thereto are not intended to limit the embodiments to the particular form disclosed, but to the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the appended claims.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1depicts a plan view of an embodiment of a portion of an integrated circuit design. Integrated circuit design100may include switching cells102(circles) and decoupling capacitors104(diamonds) at various locations in the design. In certain embodiments, switching cells102are high-speed switching cells such as clock buffers. For simplicity in the drawings,FIG. 1depicts only a portion of a complete integrated circuit design. Thus,FIG. 1shows only a limited number of switching cells102and decoupling capacitors104in design100. It is to be understood that design100may include a significant number of switching cells102and decoupling capacitors104. For example, a typical integrated circuit design may include between about 3,000 and about 15,000 switching cells and between about 1 million to about 5 million decoupling capacitors whileFIG. 1shows smaller amounts of switching cells102and decoupling capacitors104.

FIG. 2depicts a flowchart of an embodiment of a process for assessing switching cells102and decoupling capacitors104in design100. Process200may begin with “Identify coordinates202”. In202, the x- and y-coordinates of switching cells102and decoupling capacitors104are identified in design100. It is to be understood that the x- and y-coordinates, as used in embodiments herein, describe the orthogonal coordinates of a component in a plane (e.g., the x- and y-coordinates are orthogonal coordinates along the x-axis and y-axis shown inFIG. 1). Identifying the x- and y-coordinates for switching cells102and decoupling capacitors104provides an (x,y) location for each switching cell and each decoupling capacitor).

In certain embodiments, process200continues with “Create bins204”. In204, design100may be divided into a selected number of bins of selected x- and y-dimensions.FIG. 3depicts a plan view of an embodiment of a portion of design100divided into bins302. It is to be understood that the switching cells102and decoupling capacitors104in design100shown inFIG. 3would be in similar locations and in similar numbers to the switching cells and decoupling capacitors inFIG. 1. For simplicity in the drawing, however, a majority of switching cells102and decoupling capacitors104are not shown inFIG. 3.

As shown inFIG. 3, design100may be divided into the selected number of bins by dividing the design into grid304. Grid304may include a matrix of bins with a selected number of bin columns (e.g., columns 1 through A for a total number of A columns, as shown inFIG. 3) and a selected number of bin rows (e.g., rows 1 through B for a total number of B rows, as shown inFIG. 3). Thus, design100may have A×B number of bins302. The total number of bins302in grid304may be selected based on factors such as, but not limited to, size or area of design100, number of switching cells102and/or decoupling capacitors104, and properties (e.g., size and/or speed) of the switching cells and/or the decoupling capacitors.

In certain embodiments, bins302are substantially equally sized (e.g., each bin is the same size as every other bin). In certain embodiments, bins302are square bins (e.g., the bins have the same x- and y-dimensions). Thus, grid304may be a square grid including an equal number of bin columns (A) and bin rows (B), and the total number of bins may be A2or B2(given A=B and the total number of bins is A×B).

In certain embodiments, the dimensions of bins302(e.g., the x- and y-dimensions of the bins) are related to a maximum desired distance (e.g., a selected distance) between each switching cell102and the decoupling capacitors104that are available for assignment with each switching cell. For example, the dimensions of bins302may be on the order of the maximum desired distance (e.g., the selected distance) between each switching cell102and its available decoupling capacitors104. In certain embodiments, the dimensions of bins302are substantially the same as the maximum desired distance (e.g., the selected distance) between each switching cell102and its available decoupling capacitors104. The maximum desired distance may be, for example, a distance selected based on factors such as, but not limited to, the number of switching cells102and/or decoupling capacitors104and the properties (e.g., size and/or speed) of the switching cells and/or decoupling capacitors. In certain embodiments, the maximum desired distance is selected to allow decoupling capacitors104to affectively operate in conjunction with their associate (assigned) switching cell102.

While process200, shown inFIG. 2, shows “Create bins204” following “Identify coordinates202”, it is to be understood that the order of these 2 steps may be exchanged. Thus, bins302may be created in grid304in204before the coordinates of switching cells102and decoupling capacitors104are identified in202.

After202and204, process200continues with “Associate capacitors206”, as shown inFIG. 2. In206, each decoupling capacitor104, shown inFIG. 3, is associated with its respective bin302(e.g., the bin containing the decoupling capacitor). Association of each decoupling capacitor104with its respective bin302may be achieved by assigning each decoupling capacitor to the bin that includes (contains) the x- and y-coordinates of the decoupling capacitor. For example, decoupling capacitor104′, shown inFIG. 3, has x- and y-coordinates that put the decoupling capacitor in bin302(5,5) and thus, decoupling capacitor104′ may be associated with (assigned to) bin302(5,5).

Following206, process200may continue with “Select bins208”, as shown inFIG. 2. In208, a bin (e.g., bin302shown inFIG. 3) may be selected for each switching cell102in design100(e.g., grid304). Thus, each switching cell102in design100is now associated with a selected bin for that switching cell. In some embodiments, more than one switching cell102may be in the same selected bin. Association of switching cells102and bins302may be achieved by assigning each switching cell to the bin that includes (contains) the x- and y-coordinates of the switching cell. For example, switching cell102′, shown inFIG. 3, has x- and y-coordinates that put the switching cell in bin302(5,5) and thus, bin302(5,5) may be selected bin302′ for switching cell102′.

After selecting the bin for each switching cell, process200may include “Identify neighbor bins210”, as shown inFIG. 2. In210, bins302that neighbor each selected bin are identified. Neighboring bins may include bins that are adjacent the selected bin. In certain embodiments, the neighboring bins include bins that share a side and/or bins that share a corner with the selected bin. Thus, each selected bin may have 8 neighboring bins for a square grid pattern of bins. For example, if bin302(5,5), shown inFIG. 3, is the selected bin, then the 8 neighboring bins may include bins302(4,5),302(6,5),302(5,4),302(5,6) that share a side with the selected bin and bins302(4,4),302(4,6),302(6,4),302(6,6) that share a corner with the selected bin.

After the neighboring bins have been identifed, process200may proceed with “Identify available dcaps212”. In212, decoupling capacitors104that are available for each switching cell (e.g., switching cell102′) in a selected bin (e.g., selected bin302′) are identified in the selected bin and its neighboring bins. In212, the search and identification of available decoupling capacitors is limited to the selected bin and its neighboring bins. Searching only in the selected bin and the neighboring bins significantly reduces the search area for identifying available decoupling capacitors. For example, if n is the total number of switching cells and decoupling capacitors, a typical search (checking each switching cell against every decoupling capacitor in the design) would involve n2searches. In212, however, only 9 bins (e.g., the selected bin and its 8 neighboring bins) may be searched. Thus, in a design divided into 10000 bins (e.g., A×B=100×100), the search space is reduced by a factor of 9/10000 (e.g., there may now be only n2×9/10000 searches). Reducing the number of bins for identification in212may reduce the computational capacity needed to perform the search and significantly increase the speed for the process of ensuring there is a sufficient number of decoupling capacitors placed locally around each switching cell in the design.

In certain embodiments, available decoupling capacitors include decoupling capacitors104that are in either selected bin302′ or its neighboring bins and that are within a selected distance from switching cell102′ in the selected bin. The selected distance, as described above, may be the maximum desired distance between each switching cell102and its available decoupling capacitors104. The selected distance may be selected based on factors such as, but not limited to, the number of switching cells102and/or decoupling capacitors104and the properties (e.g., size and/or speed) of the switching cells and/or decoupling capacitors.

In certain embodiments, the selected distance is less than the distance from the switching cell (e.g., switching cell102′) to a furthest point in the bins neighboring the selected bin (e.g., selected bin302′). Having distance from the switching cell to a furthest point in the neighboring bins be greater than the selected distance may ensure that any available decoupling capacitors for the switching cell are not located beyond the neighboring bins.

In some embodiments, a distance of a decoupling capacitor to a switching cell is calculated by a Pythagorean Theorem calculation using each component's x- and y-coordinates found in202. The calculated distance may then be compared to the selected distance to see if the decoupling capacitor is within the selected distance and thus, “available” to the switching cell.

In certain embodiments, available decoupling capacitors include decoupling capacitors that are not used for another switching cell (e.g., decoupling capacitors that have not been assigned to or associated with another switching cell as described herein). For example, once decoupling capacitors are assigned to or associated with a switching cell, as described in step216below, these decoupling capacitors are removed from being available for association with any other switching cell in the design (e.g., the coordinates of these decoupling capacitors may be removed from any further searches for decoupling capacitors). Marking decoupling capacitors as “assigned” and removing them from availability for another switching cell may inhibit overlapping usage of decoupling capacitors between relatively close switching cells (e.g., switching cells that are within the selected distance from each other). Additionally, not allowing decoupling capacitors to be available to more than one switching cell may provide more accurate assignment and mapping of switching cells and their associated decoupling capacitors.

In some embodiments, in212, the process of identifying decoupling capacitors104that are available for each switching cell begins with identifying decoupling capacitors that are available in the selected bin and its neighboring bins that share a wall in one direction (e.g., the x-direction) before looking at decoupling capacitors in other neighboring bins. For example, for switching cell102′ in bin302′ (e.g., bin302(5,5), available decoupling capacitors may be identified in the selected in (bin302(5,5)), bin302(4,5), and bin302(6,5) before decoupling capacitors in any other neighboring bins are assessed. Thus, if the sufficient number of available decoupling capacitors (as described in step214below) is found in only the selected bin and its neighboring bins that share the wall in one direction, no further assessment of available decoupling capacitors is needed in the other neighboring bins. Checking only these bins may save time, increase the speed of process200, and reduce the computational capacity needed for the process. If the sufficient number of available decoupling capacitors is not found in only the selected bin and its neighboring bins that share the wall in one direction, the other neighboring bins may be assessed for available decoupling capacitors.

After available decoupling capacitors are identified in212, process200may proceed, in some embodiments, with “Assess sufficient number214” or, in some embodiments, with “Assign selected number216”. In some embodiments, steps214and216are performed in combination in process200with one step following the other step. Steps214and216may be performed in combination with either step being the first step.

In214, the available decoupling capacitors identified in212are assessed to determine if there are a sufficient number of the available decoupling capacitors in the selected bin and its neighboring bins for each switching cell in the selected bin. The sufficient number of the available decoupling capacitors may be a number of decoupling capacitors needed to provide voltage stability in each switching cell during, for example, switching events (such as high-speed switching events). The sufficient number of available decoupling capacitors104needed for each switching cell102in design100, shown inFIG. 3, may depend on a number of factors including, but not limited to, the properties (e.g., size and/or speed) of each switching cell and/or the distance between each switching cell and each of the available decoupling capacitors. Thus, the sufficient number of available decoupling capacitors104needed for each switching cell102in design100may vary between switching cells. In some embodiments, if one or more switching cells in design100do not have the sufficient number of available decoupling capacitors, the design is modified in222, which is described below.

In216, shown inFIG. 2, a selected number of the available decoupling capacitors identified in212are assigned to each switching cell in the selected bin (e.g., switching cell102′ in selected bin302′ shown inFIG. 3). In certain embodiments, the selected number of the available decoupling capacitors assigned to each switching cell is the number of decoupling capacitors needed to provide voltage stability in the switching cell during, for example, switching events (e.g., the selected number is the sufficient number of available capacitors needed as described above). In some embodiments, the selected number of the available decoupling capacitors assigned to each switching cell is provided to214to assess if the selected number of assigned decoupling capacitors is a sufficient number to provide voltage stability in the switching cell.

In some embodiments, the selected number of the available decoupling capacitors assigned to each switching cell includes the available decoupling capacitors identified in212that are closest to the switching cell. For example, if 20 decoupling capacitors are identified in212as being available to a switching cell but only 15 decoupling capacitors are needed for the switching cell (e.g., to provide voltage stability in the switching cell), then the 15 decoupling capacitors assigned to the switching cell may be the 15 decoupling capacitors of the 20 identified decoupling capacitors that closest to the switching cell.

In certain embodiments, after214and/or216, a map of each of the switching cells and their assigned decoupling capacitors is created in “Create map218”. The created map may be, for example, a plan view or layout view of design100(e.g., a plan view similar toFIG. 3) showing all the switching cells and decoupling capacitors in the design with indicators or other markings differentially identifying the decoupling capacitors assigned to each switching cell.

In certain embodiments, after the map is created in218, the integrated circuit design (e.g., design100) is output (e.g., provided as a final design) in “Output design220”. In some embodiments, the integrated circuit design is output without creating the map of switching cells and decoupling capacitors (e.g., step218is skipped after either214or216).

In certain embodiments, if one or more switching cells in design100do not have the sufficient number of available decoupling capacitors after either214,216, and/or218, the design is modified in “Modify design222”. Modifying design100may include adding additional decoupling capacitors to the design in selected locations. The locations may be selected to provide the one or more switching cells that do not have the sufficient number of available decoupling capacitors with the sufficient number of available decoupling capacitors. Thus, design100may be modified by adding decoupling capacitors where needed until each switching cell in the design has its sufficient number of decoupling capacitors. In some embodiments, the locations are identified using the map created in218. In certain embodiments, after design100is modified in222, process200may be repeated starting in202, as shown inFIG. 2, to ensure that the additional decoupling capacitors added to the design provide the sufficient number for each switching cell in the design.

In certain embodiments, one or more process steps described herein are operated using software executable by a processor (e.g., a computer processor). For example, process200, shown inFIG. 2may have one or more steps controlled or operated using software executable by the processor. In some embodiments, the process steps are stored as program instructions in a computer readable storage medium (e.g., a non-transitory computer readable storage medium) and the program instructions are executable by the processor.

FIG. 4depicts a block diagram of one embodiment of exemplary computer system410. Exemplary computer system410may be used to implement one or more embodiments described herein. In some embodiments, computer system410is operable by a user to implement one or more embodiments described herein such as process200, shown inFIG. 2. In the embodiment ofFIG. 4, computer system410includes processor412, memory414, and various peripheral devices416. Processor412is coupled to memory414and peripheral devices416. Processor412is configured to execute instructions, including the instructions for process200, which may be in software. In various embodiments, processor412may implement any desired instruction set (e.g. Intel Architecture-32 (IA-32, also known as x86), IA-32 with 64 bit extensions, x86-64, PowerPC, Sparc, MIPS, ARM, IA-64, etc.). In some embodiments, computer system410may include more than one processor.

Processor412may be coupled to memory414and peripheral devices416in any desired fashion. For example, in some embodiments, processor412may be coupled to memory414and/or peripheral devices416via various interconnect. Alternatively or in addition, one or more bridge chips may be used to coupled processor412, memory414, and peripheral devices416.

Memory414may comprise any type of memory system. For example, memory414may comprise DRAM, and more particularly double data rate (DDR) SDRAM, RDRAM, etc. A memory controller may be included to interface to memory414, and/or processor412may include a memory controller. Memory414may store the instructions to be executed by processor412during use, data to be operated upon by the processor during use, etc.

Peripheral devices416may represent any sort of hardware devices that may be included in computer system410or coupled thereto (e.g. storage devices, optionally including computer accessible storage medium500, shown inFIG. 5, other input/output (I/O) devices such as video hardware, audio hardware, user interface devices, networking hardware, etc.).

Turning now toFIG. 5, a block diagram of one embodiment of computer accessible storage medium500including one or more data structures representative of switching cells and decoupling capacitors included in design100(depicted inFIGS. 1 and 3) and one or more code sequences representative of process200(depicted inFIG. 2) is shown. Each code sequence may include one or more instructions, which when executed by a processor in a computer, implement the operations described for the corresponding code sequence. Generally speaking, a computer accessible storage medium may include any storage media accessible by a computer during use to provide instructions and/or data to the computer. For example, a computer accessible storage medium may include non-transitory storage media such as magnetic or optical media, e.g., disk (fixed or removable), tape, CD-ROM, DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, or Blu-Ray. Storage media may further include volatile or non-volatile memory media such as RAM (e.g. synchronous dynamic RAM (SDRAM), Rambus DRAM (RDRAM), static RAM (SRAM), etc.), ROM, or Flash memory. The storage media may be physically included within the computer to which the storage media provides instructions/data. Alternatively, the storage media may be connected to the computer. For example, the storage media may be connected to the computer over a network or wireless link, such as network attached storage. The storage media may be connected through a peripheral interface such as the Universal Serial Bus (USB). Generally, computer accessible storage medium500may store data in a non-transitory manner, where non-transitory in this context may refer to not transmitting the instructions/data on a signal. For example, non-transitory storage may be volatile (and may lose the stored instructions/data in response to a power down) or non-volatile.

Further modifications and alternative embodiments of various aspects of the embodiments described in this disclosure will be apparent to those skilled in the art in view of this description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the embodiments. It is to be understood that the forms of the embodiments shown and described herein are to be taken as the presently preferred embodiments. Elements and materials may be substituted for those illustrated and described herein, parts and processes may be reversed, and certain features of the embodiments may be utilized independently, all as would be apparent to one skilled in the art after having the benefit of this description. Changes may be made in the elements described herein without departing from the spirit and scope of the following claims.