Method and a decoder for decoding MPEG video

A decoded picture and parameters of a sequence layer, a GOP layer and a picture layer respectively for displaying the decoded picture are stored as a set in each of picture banks and parameter banks of a frame memory. Parameters of each layer stored as a set with a picture decoded immediately before are read out. Parameters attached to a picture to be decoded are decoded overwritten. Thus, the parameters of each layer stored as a set with the picture to be decoded are generated.

FIELD OF THE INVENTION

The present invention relates in general to a method and a decoder for decoding bit stream data of a dynamic image that has been decoded according to the MPEG (Moving Picture Experts Group) standard.

BACKGROUND OF THE INVENTION

The MPEG standard is an international standard relating to an image compression. A dynamic image coding technique and a dynamic image decoding technique based on the MPEG standard are the techniques that are unavoidable in the recent multimedia environment. Thus, there have been developed many dynamic image coding apparatuses and dynamic image decoding apparatuses that employ the MPEG standard.

In the MPEG standard, three types of pictures are used for achieving high-efficiency coding. These three types are, intra-coded picture (hereinafter to be referred to as an I picture), a predictive-coded picture (hereinafter to be referred to as P picture), and a bidirectionally predictive-coded picture (hereinafter to be referred to as B picture).

The I picture is coded based on only the picture information of its own, that is, without using other picture information. As the I picture can be coded independent of other pictures, the I picture is used as an access point at the time of a random access. Therefore, other picture information is not necessary for decoding the I picture.

The P picture is coded by using a past I picture or a past P picture as a reference picture. Therefore, the information of a past I picture is necessary for decoding the P picture.

The B picture is coded by using past and future I pictures or past and future P pictures as reference pictures. Therefore, the information of past and future I pictures or P pictures are necessary for decoding the B picture.

A hierarchical coding system is employed in the MPEG standard. In other words, a video sequence consists of six hierarchical layers in total. They are a sequence layer, a group-of-picture layer (hereinafter to be referred to as GOP layer), a picture layer, a slice layer, a macro block layer (hereinafter to be referred to as MB layer), and a block layer, in the order starting from a highest-order layer. The four high-order layers starting from the sequence layer to the slice layer are added with a start code respectively to show the start of each layer.

Following each start code, parameters are coded for each layer. For example, the sequence layer has a sequence header code (SHC) at the beginning, and then has, as parameters, a horizontal size value, a vertical size value, aspect ratio information, etc. which are superimposed in this order.

The table inFIG. 1shows a part of parameters for each layer of the MPEG standard. In the case of the sequence layer, the horizontal size value and the vertical size value are parameters that express the sizes of an image in the horizontal direction and the vertical direction respectively. In other words, they are the parameters that express numbers of pixels in the horizontal direction and the vertical direction respectively. The aspect ratio information is a parameter that expresses the aspect ratio of the pixels. In addition to these parameters, the sequence layer also has other parameters, such as a display horizontal size and display vertical size that express the display sizes of a decoded image in the horizontal direction and in the vertical direction respectively.

The GOP layer has two parameters. They are, a closed group of picture (closed gop) that expresses that it is possible to display a B picture at the head of the GOP, and a broken link that expresses that it is not possible to display a B picture at the head of the GOP.

The picture layer has four parameters. First two parameters are a top field first that expresses that a display is made starting from a picture of a first field, and a repeat first field that expresses that a picture in the first field is displayed repeatedly. Other two parameters are a frame center horizontal offset and a frame center vertical offset that are pan-scan parameters.

A conventional MPEG video decoder generally stores these parameters of each layer into a register inside the decoder, and refers to these parameters at the time of making a display. The structure of the conventional MPEG video decoder will be explained below.

FIG. 2is a block diagram that shows a structure of the conventional MPEG video decoder. This MPEG video decoder consists of a buffer memory11, an image decoding section12, a frame buffer13, a decode control section14, and a display control section15. The buffer memory11stores an MPEG bit stream that has been transmitted from a transmission path or a storing medium. The image decoding section12decodes a bit stream that has been transmitted from the buffer memory11, and generates a picture.

The frame buffer13stores a picture generated by the image decoding section12. The frame buffer13has a capacity for storing three pictures. The frame buffer13is divided into three areas which respectively store one picture. Each area is called a bank. In other words, the frame buffer13has three banks, a first bank13a,a second bank13band a third bank13c.Each of the banks13a,13band13chas its own address (i.e., bank address).

The decode control section14incorporates a vertical synchronization signal generator16that generates a vertical synchronization signal (V-Sync)21. The decode control section14issues a slice layer decode starting instruction22to the image decoding section12and the display control section15. The slice layer decode starting instruction22is synchronous with the vertical synchronization signal (V-Sync)21. The cycle of issuing the slice layer decode starting instruction22is basically once per every two field time, that is, once per one frame time. This cycle is for matching the decoding speed with the display speed, as the display speed is at the rate of displaying one picture during one frame time. When the capacity of the buffer memory11has satisfied a predetermined condition at the time of a cold starting, the decode control section14issues an initial decode starting instruction23. The timing of issuing the initial decode starting instruction23is not related to the vertical synchronization signal (V-Sync)21.

The display control section15incorporates registers for storing parameters24of each layer decoded by the image decoding section12and a bank address25. These registers include a reorder register15a,a current register15b,a field delay register15c,and a display register15d.The bank address25is the address of the bank in the frame buffer13in which a decoded picture is stored.

The display control section15receives a sequence layer decode completion notice26and a GOP layer decode completion notice27from the image decoding section12. The sequence layer decode completion notice26is issued at a point of time when the decoding of the parameters of the sequence layer has been finished. The GOP decode completion notice27is issued at a point of time when the decoding of the parameters of the GOP layer has been finished.

The display control section15is supplied with the vertical synchronization signal (V-Sync)21from the vertical synchronization signal generator16. The display control section15outputs a display starting instruction28to the frame buffer13at a timing synchronous with the vertical synchronization signal (V-Sync)21. Based on this display starting instruction28, the frame buffer13transfers a predetermined picture to a display unit not shown, and the display unit displays the image.

As explained above, the MPEG video decoder starts the decoding of a bit stream for one picture at a timing synchronous with the vertical synchronization signal (V-Sync)21, and transfers the picture to the display unit at a timing synchronous with the vertical synchronization signal (V-Sync)21. Thus, the image displayed by the display unit is updated at the timing synchronous with the vertical synchronization signal (V-Sync)21, and the display unit displays a dynamic image.

FIG. 3is a diagram that shows a structure of the registers within the display control section15. The display control section15is provided with a sequence layer parameter register15e,a GOP layer parameter register15f,and picture layer parameter registers15g.When the sequence layer parameter register15ehas received the sequence layer decode completion notice26, the sequence layer parameter register15estores the parameters of the horizontal size value and the vertical size value of the sequence layer out of the parameters24of each layer.

Parameters that are stored in the picture layer parameter register group15ginclude a temporal reference, a picture coding type, and a picture structure of the picture layer respectively, out of the parameters24of each layer. The picture layer parameter register group15gstores the bank address25.

The reason why there are four registers15a,15b,15cand15dfor storing the picture layer display parameters and the bank address25is that, according to the MPEG standard, it is necessary to reorder the I picture, the P picture and the B picture. In other words, as mentioned above for decoding the B picture, the past and future pictures are referred. Therefore, it is necessary to reorder the pictures in order to process the future picture first.

The reorder register15astores the picture layer parameters and the bank address25of the I picture and the P picture respectively. The I picture and the P picture are not displayed straight when the decoding of these pictures has been completed. It is necessary to reorder these pictures with the B picture. Therefore, the parameters and the bank address25of the I picture and the P picture respectively are once saved in the reorder register15a.

The current register15bstores the picture layer display parameter of the picture to be displayed and the bank address25. As the B picture is displayed immediately after the completion of the decoding, the parameters and the bank address25of the B picture are not stored in the reorder register15abut are stored directly in the current register15b.

The field delay register15cdelays the bank address25transferred from the current register15bby one field time in order to set the decoding time to one frame time, and then transfers the delayed result to the next display register15d.If it is assumed that the field delay register15cis not present, then the field slot of the display timing becomes the field slot immediately after the field slot of the decoding timing. As a result, it is not possible to perform the display at the right timing. The data that is stored in the field delay register15cis only the bank address25.

The display register15dstores the bank address25of the picture currently being displayed. In other words, the display control section15issues the display starting instruction28so that a picture indicated by the bank address25stored in the display register15dis displayed. The data stored in the display register15dis only the bank address25, and the display register15dtakes in the content of the display register15cas it is. The display control section15executes the display of the picture by comprehensively analyzing the display parameter of the picture layer stored in this register and the parameters of the sequence layer and the parameters of the GOP layer.

These four registers15ato15dhave a shift register structure as shown inFIG. 3. The shift pulse of the reorder register15aand the current register15bis the slice layer decode starting instruction22, and the shift pulse of the field delay register15cand the display register15dis the vertical synchronization signal (V-Sync)21. The bank address25shifts to all the registers from the reorder register15ato the display register15d,but the display parameter of the picture layer shifts only up to the current register15b.

The operation of the MPEG video decoder having the above-described conventional structure will be explained next. The time chart shown inFIG. 4explains the operation of the conventional MPEG video decoder. In the example shown inFIG. 4, it is assumed that a bit stream is input in the order of an I picture I2, a B picture B0, a B picture B1, a P picture P5, a B picture B3, a B picture B4, and so on, and that the pictures are displayed in the order of the picture B0, the picture B1the picture I2, the picture B3, and so on.

The MPEG bit stream obtained through the transmission path or the storing medium is first stored in the buffer memory11. When a certain amount of data (for example, data for one picture) has accumulated in the buffer memory11, the decode control section14issues the initial decode starting instruction23(at time t0). When the image decoding section12has received the initial decode starting instruction23, the image decoding section12starts the decoding of the bit stream, and first carries out the decoding of a first picture. When the image decoding section12has finished the decoding of all the parameters of the sequence layer, the image decoding section12issues the sequence layer decode completion notice26. When the display control section15has received the sequence layer decode completion notice26, the display control section15stores the parameters of the sequence layer in the sequence layer parameter register15e(at time t1).

Next, the image decoding section12carries out the decoding of the parameters of the GOP layer. When the image decoding section12has finished the decoding of the parameters of the GOP layer, the image decoding section12issues the GOP layer decode completion notice27. When the display control section15has received the GOP layer decode completion notice27, the display control section15stores the parameters of the GOP layer in the GOP layer parameter register15f(at time t2). Further, the image decoding section12decodes the parameters of the picture layer of the picture I2and reads the decoded parameters, and then halts temporarily (at time t3).

Thereafter, in synchronism with the pulse of the vertical synchronization signal (V-Sync), the decode control section14issues the slice layer decode starting instruction22(at time t4). When the image decoding section12has received the slice layer decode starting instruction22, the image decoding section12decodes the slice layer and the MB (macro block) layer of the picture I2. When the decoding of the MB layer has been completed, the image decoding section12decodes the picture layer of the next picture B0. When the decoding of the picture layer of the picture B0has been completed, the image decoding section12halts temporarily again (at time t5).

In the mean time, at time t4, the display control section15receives the picture parameter of the picture I2from the image decoding section12, and stores the picture parameter in the reorder register15a.In this case, the reorder register15astores the parameters of the picture I2at a timing synchronous with the slice layer decode starting instruction22using the slice layer decode starting instruction22as a latch pulse.

At time t6, the decode control section14issues the slice layer decode starting instruction22again in synchronism with the vertical synchronization signal (V-Sync)21. When the image decoding section12has received this slice layer decode starting instruction22, the image decoding section12starts the decoding of the slice layer and the MB layer of the picture B0. At the same time, the image decoding section12stores the picture parameter of the picture B0into the current register15b.

The picture parameter of the picture B0is shifted to the field delay register15cin synchronism with the vertical synchronization signal (V-Sync)21, and is further stored in the display register15din synchronism with the next vertical synchronization signal (V-Sync)21(at time t7). Thus, the data of the pictures to be displayed have been arranged, and the pictures are ready for display. Then, the display control section15comprehensively analyzes the display layer parameters, the sequence layer parameters, and the GOP layer parameters, and determines how to display this B0.

Assume, for example, that the horizontal size value is “720”, the vertical size value is “480”, the value of the closed group of picture is “1”, the value of the broken link is “0 (zero)”, the value of the top field first is “1”, the value of the repeat first field is “0 (zero)”, and the values of the frame center horizontal offset and the frame center vertical offset are both “0 (zero)”. In this case, the display control section15makes a decision that as the picture B0is effective, this picture is displayed, and that the display is carried out in an ordinary manner instead of carrying out a pan-scan display in the pixel size of “720×480”.

Thereafter, the display control section15issues the display starting instruction28to the frame buffer13, and makes the picture displayed in the region shown by the horizontal size value and the vertical size value.

Thereafter, the image decoding section12carries out the decoding sequentially in a similar manner. For making a display of the B picture, the display control section15progresses the display by referring to the display parameter of the picture layer stored in the current register15band the display parameters of the sequence layer and the GOP layer. Further, for making a display of the I picture or the P picture, the display control section15progresses the display by referring to the display parameter of the picture layer stored in the display register15dand the display parameters of the sequence layer and the GOP layer.

In the television image according to the NTSC (National Television System Committee) system, one frame is divided into two fields (a top field and a bottom field). Therefore, inFIG. 4(as well as inFIG. 5,FIG. 7andFIG. 8), each picture is shown by being divided into the top field (a field indicated by “T” in the drawing) and the bottom field (a field indicated by “B” in the drawing).

However, according to the above-described conventional MPEG video decoder, when a bit stream has only one picture in one sequence and also when the bit stream having a plurality of these sequences connected together (generally called a slide show) is to be decoded and displayed, the following two problems arise. These problems will be explained next.

The time chart shown inFIG. 5explains the operation in a slide show of the conventional MPEG video decoder. A case where three sequences are connected together, each sequence having one picture, will be explained as an example. The three sequences will be called SEQ1, SEQ2and SEQ3. In this case, as one sequence has one picture, a display parameter of the sequence layer exists in each of the three pictures.

Assume that the first sequence SQ1has a value of “720” for the horizontal size value and a value of “480” for the vertical size value, the second sequence SQ2has a value of “360” for the horizontal size value and a value of “240” for the vertical size value, and the third sequence SQ3has a value of “360” for the horizontal size value and a value of “480” for the vertical size value.

In this case, as shown inFIG. 5, the operation from time t0to t3is the same as the operation of the normal display shown inFIG. 4. However, as shown inFIG. 5, the first sequence SEQ1changes to the second sequence SEQ2at time t4. Therefore, the sequence layer display parameter is updated from the parameter of the first sequence SEQ1to the parameter of the second sequence SEQ2. In other words, the horizontal size of the image is updated from 720 pixels to 360 pixels, and the vertical size of the image is updated from 480 pixels to 240 pixels. Further, the second sequence SEQ2is updated to the third sequence SEQ3at time t5. At this point of time, the display parameter of the second sequence SEQ2is updated to the display parameter of the third sequence SEQ3. Therefore, the vertical size of the image is updated from 240 pixels to 480 pixels. As a result, the sizes of the image are changed to “360×480” pixels.

In the case of displaying the I2picture of the first sequence SEQ1at time t6, the picture must be displayed in the sizes of “720×480” in principle. However, as the display parameter has been updated to the parameter of the third sequence at time t6, the I2picture of the first sequence SEQ1is displayed by the pixel sizes of “360×480”. In other words, as the combination of the picture parameters and the sequence layers of the three sequences are not managed completely, the decoded images are not displayed correctly. Same thing can be said about the display parameter of the GOP layer though its explanation has been omitted. This is a first problem. This problem also occurs when a pause, a quick winding or a rewinding operation has been carried out for the MPEG bit stream that has been sent from the storing medium.

This problem occurs because only one register is provided for the sequence layer parameter register15eand the GOP layer parameter register15frespectively in the display control section15. Therefore, only one set of the sequence parameters and the GOP parameters can be held in these registers15eand15frespectively. As a result, when different sequences continue like the slide show, the sequence parameters and the GOP parameters are overwritten and updated sequentially.

The second problem is that as there is no fourth sequence after the third sequence SEQ3, which is the last sequence of this slide show, the third sequence SEQ3cannot be displayed. This is because when the slice layer decode starting instruction to the fourth sequence is not issued from the decode control section14, the picture parameters of the third sequence SEQ3stored in the reorder register15acannot be shifted to the current register15bat time t6. When the picture parameters of the third sequence SEQ3are not shifted to the current register15b,the parameters are not shifted to the field delay register15cand the display register15deither. As a result, the third sequence SEQ3is not displayed at all.

In order to decode and display the slide show by the MPEG video decoder having the above-described conventions structure, it is necessary to add in advance an additional sequence to the end of the last sequence, and to take a sufficiently long time between the sequences in order to avoid the overwriting of the parameters stored in the sequence layer parameter register15eand the GOP layer parameter register15frespectively. However, based on this arrangement, it is not possible to completely achieve the display of the slide show.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide an MPEG video decoder and an MPEG video decoding method capable of making a correct display in the MPEG bit stream such as a slide show even if there is no continuing pictures (or sequences).

It is another object of the present invention to provide an MPEG video decoder and an MPEG video decoding method capable of making a display of pictures in an optional order regardless of the original display order.

According to one aspect of the present invention, a decoded picture and parameters of a sequence layer, a GOP layer and a picture layer respectively for displaying the decoded picture are stored as a set in each bank of a frame memory. The parameters of each layer that are stored as a set with a picture to be decoded are generated by decoding the parameters attached to the picture to be decoded and by updating the parameters of each layer stored as a set with the picture that has been decoded immediately before.

However, for carrying out the decoding of a first picture, parameters are read from a memory area that stores parameters of the sequence layer, the GOP layer and the picture area respectively that are attached to the picture to be decoded. The parameters and the picture are decoded regardless of the vertical synchronization signal. On the other hand, the decoded picture is displayed in synchronism with the vertical synchronization signal.

The parameters of each layer decoded by the image decoding section are once stored in an internal buffer of the image decoding section in a macro block unit, and are then written into the frame memory. Similarly, pictures that have been decoded by the image decoding section are once stored in the internal buffer of the image decoding section in a macro block unit, and are then written into the frame memory. In this case, the decoded parameters of each layer and the decoded pictures are transferred between the internal buffer and the frame memory via the same data transfer path.

According to the present invention, each bank of the frame memory stores a set of the decoded picture and the parameters of the sequence layer, the GOP layer and the picture layer respectively for storing the picture. Therefore, it is possible to continuously decode the bit stream like the slide show. Further, it is possible to display the pictures in an optional order.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

One preferred embodiment of an MPEG video decoder relating to the present invention will be explained next with reference to the drawings.FIG. 6is a block diagram that shows one example of a structure of the MPEG video decoder relating to the present invention. This MPEG video decoder includes a buffer memory51, an image decoding section52, a frame memory53, a decode control section54, a display control section55, a vertical synchronization signal generator56, and a status register57.

The buffer memory51stores a bit stream of the MPEG obtained through a transmission path or from a storing medium. The image decoding section52decodes a bit stream transmitted from the buffer memory51, and generates a picture and parameters of each layer. The image decoding section52has a macro-block buffer (hereinafter to be referred to as MB buffer)58as an internal buffer. The MB buffer58temporarily stores a decoded picture in a macro-block unit (8×8 pixels). Further, the MB buffer58temporarily stores decoded parameters.

The frame memory53stores a picture and parameters of each layer transferred from the MB buffer58. In other words, the frame memory53is provided with a picture storing area53din which a decoded picture is stored and a parameter storing area53ein which parameters of each layer are stored. The picture storing area53dis divided into, for example, three picture banks53a,53band53c,although the number of the picture banks is not particularly limited. Similarly, the parameter storing area53eis divided into, for example, three parameter banks53f,53gand53h,although the number of the parameter banks is not particularly limited. The storage format of each of the parameter banks53f,53gand53his the same as that of the macro block (MB).

A decoded picture is stored in any one of the picture banks. Parameters attached to the stored picture are stored into a parameter bank corresponding to the storing bank of the picture among the three parameter banks53f,53gand53h.For example, assume that the first parameter bank53fcorresponds to the first picture bank53a.When a decoded picture of a picture I2has been stored into the first picture bank53a,all the parameters of the picture I2are stored into the first parameter bank53f.For example, the parameter banks53f,53gand53hare provided in empty areas of the picture banks53a,53band53crespectively.

A data transfer path71between the MB buffer58and the frame memory53is a path for transferring a decoded picture from the MB buffer58to the frame memory53. At the same time, the data transfer path71also works as a path for transferring parameters in two directions between the MB buffer58and the frame memory53. In other words, parameters that have been stored in the MB buffer58are transferred to the parameter storing area53eof the frame memory53via the data transfer path71. Similarly, parameters that have been stored in the parameter storing area53eare transferred to the MB buffer58via the data transfer path71.

The status register57stores values corresponding to a data storage state of each bank of the frame memory53. Three banks each are provided for pictures and for parameters in the frame memory53, however, the number of banks is not particularly limited. In other words, as the frame memory53can store three sets of pictures and parameters, the status register57has three bits.

When a certain bank in the frame memory53stores a decoded picture and parameters corresponding to this picture, the value of the corresponding bit of the status register57becomes “1”. On the other hand, the value of the bit of the status register57corresponding to an empty bank becomes “0”. When a bank stores a picture of which display has already been finished, and also when this picture is not a reference picture of other picture, that is, when this picture is already unnecessary and this picture can be overwritten, the value of the bit of the status register corresponding to this bank becomes “0”.

The bits of the status register57correspond to the third banks53cand53h,the second banks53band53g,and the first banks53aand53f,in this order starting from the highest-order bit (MSB), for example. More specifically, when data are stored in all of the three banks53a,53band53c,the value of the status register is “111”, and when all of these three banks are empty, the value of the status register57is “000”.

The status register57plays the role of an arbitration function for arbitrating between the decode control section54and the display control section55. In other word, the decode control section54and the display control section55observe the status register57, and carry out decoding or display according to the value of the status register57.

The decode control section54issues a slice layer decode starting instruction62to the image decoding section52and the display control section55. The issue timing of the slice layer decode starting instruction62is not related to a vertical synchronization signal (V-Sync)61. When the capacity of the buffer memory51has satisfied a predetermined condition at the time of a cold starting, the decode control section54issues an initial decode starting instruction63to the decode control section52. The timing of issuing the initial decode starting instruction63is not related to the vertical synchronization signal (V-Sync)61. When the decoding of all the macro blocks of a picture under decoding has been finished, the decode control section54issues a decode completion notice72to the status register57.

The display control section55is supplied with the vertical synchronization signal (V-Sync)61from the vertical synchronization signal generator56. The display control section55reads all the parameters of a picture to be displayed from the corresponding parameter bank via a parameter transfer path73. The timing of reading the parameters is related to the vertical synchronization signal (V-Sync)61. Further, the display control section55issues a display starting instruction to the frame memory53. Based on this display starting instruction68, a desired picture is transferred to a display unit not shown inFIG. 6from the frame memory53, and the picture is displayed in the display unit. After the completion of the display, the display control section55issues a display completion notice74to the status register57.

A decode processing of the MPEG video decoder relating to the present invention will be explained next.FIG. 7is a flowchart that shows one example of a decode processing of the MPEG video decoder relating to the present invention.

An MPEG bit stream obtained through a transmission path or from a storing medium is stored into the buffer memory51. In starting a decoding, when a predetermined amount of MPEG bit stream (for example one picture component) has been stored into the buffer memory51(step S1), the decode control section54first observes the status register57(step S2). Then, the decode control section54makes a decision as to whether there is an empty bank in the frame memory53or not (step S3). When there is no empty bank, the decode control section54does not start the decoding, and waits until there is an empty bank.

When there is an empty bank, the decoding is started. The decode control section54reads out parameters relating to a picture (or a sequence) that has been decoded immediately before from the parameter bank that stores these parameters, and then the decode control section54stores the read-out parameters into the MB buffer58(step S4). However, when decoding a first picture of a series of MPEG bit stream, there is no picture that has been decoded immediately before. In other words, there is no parameter bank that stores parameters relating to a picture (or a sequence) that has been decoded immediately before.

Therefore, when decoding a first picture, parameters are read from a bank that is scheduled to store the parameters relating to this picture when the decoding of this picture has been finished in future. At a first decoding time, the bank that is scheduled to store the parameters in future is in the initial state, that is, in the state that nothing has been written in this bank. Therefore, “0” is written into all the banks of the MB buffer58.

Then, the image decoding section52decodes the sequence layer, the GOP layer and the picture layer relating to the picture to be decoded (step S5). When there is no data in the sequence layer and the GOP layer, only the picture layer is decoded. Parameters of each layer that have been generated as a result of the decoding are overwritten into the parameters stored in the MB buffer58(step S6). Then, the parameters are transferred from the MB buffer to the parameter bank, and are written into this parameter bank.

When the parameters relating to the picture to be decoding have been written into the parameter bank, the decode control section54issues the slice layer decode starting instruction62(step S7). After the slice layer decode starting instruction62has been issued, the decoding of the slice layer and the MB layer of the picture to be decoded is started. The decoded data are once stored into the MB buffer58, and then written into the picture bank of the frame memory53in the macro-block unit.

When the decoding of all the macro-blocks relating to the picture under decoding has been finished (step S8), the decode control section54issues the decode completion notice72to the status register57(step S9). Based on this decode completion notice72, the value of the bit of the status register57corresponding to the bank of the frame memory53in which the decoded picture and parameters are stored is changed from “0” to “1” (step S10). Thereafter, the process returns to the first step, and the processing at step S1to step S10is repeated.

A display processing of the MPEG video decoder relating to the present invention will be explained next. The flowchart inFIG. 8shows one example of the display processing of the MPEG video decoder relating to the present invention.

In synchronism with the fall of the vertical synchronization signal (V-Sync)61(step S11), the display control section55observes the status register57(step S12). The status register57makes a decision as to whether there is a picture that can be displayed within the frame memory53or not (step S13). When the value of any one of the bits of the status register57is “1”, this means that there is a picture that can be displayed within the frame memory53.

When there is a picture that can be displayed, the display control section55reads out all the parameters of the picture to be displayed from the corresponding parameter bank (step S14). The display control section55analyzes the content of the parameters that have read, and determines how to display this picture (step S15). Then, the display control section55issues a display starting instruction68(step S16). Based on this display starting instruction68, a desired picture is transferred from the frame memory53to a display unit not shown, and this picture is displayed in the display unit.

When the display of all the lines of the picture has been finished (step S17), the display control section55issues a display completion notice74to the status register57(step S18). Based on the issuing of this display completion notice74, when the displayed picture is not a reference frame, the value of the corresponding bit of the status register57is written from “1” to “0” (step S19). However, when the displayed picture is a reference frame, the value of the corresponding bit is kept at “1”. Thereafter, the process returns to the first step, and the processing from step S11to S19is repeated.

Next, normal operation of the MPEG video decoder relating to the present invention will be explained. The time chart inFIG. 9shows operation timings during a normal operation of the MPEG video decoder relating to the present invention. The normal operation in this case refers to the operation of decoding a series of MPEG bit stream in the original order. Therefore, such operations as a slide show, a quick winding or rewinding, and an inverse reproduction are not included.

When the initial decode starting instruction63has been issued at time t0, the decode control section54first observes the status register57. As the status register57is at the initial state, the value of the status register57is “000”. Therefore, the picture I2is decoded using, for example, the first banks53aand53fof the frame memory53.

As the picture I2is the first picture, there is no picture that has been decoded in this straight line. Therefore, at time t0, all the parameters are read from the first parameter bank53f(legend101inFIG. 9), and these parameters are written into the MB buffer58(legend102inFIG. 9). In this case, as nothing has yet been written into the first parameter bank53f,“0” is written into all the parameters of the MB buffer58. The reason why the parameters are read from the first parameter bank53fat the beginning is as explained previously.

At time t2, the writing of the content of the first parameter bank53finto the MB buffer58has been finished. At the same time, the decoding of the bit stream is started, and the sequence layer and the GOP layer are decoded (legend103inFIG. 9). Subsequently, the picture layer of the picture I2is decoded (legend104inFIG. 9). The parameters obtained as a result of the decoding are sequentially written into the MB buffer58while forming the parameters into a format that can be stored into the MB buffer58(legend105inFIG. 9). When the decoding of the picture layer has been finished at time t3, the decoding is halted temporarily.

After the writing of the parameters into the MB buffer58has been finished, the parameters are read out from the MB buffer58at times t4to t5(legend106inFIG. 9). Then, the read-out parameters are written into the first parameter bank53f(legend107inFIG. 9). All the parameters of the picture I2have been stored into the first parameter bank53fby this time.

At time t6, the decode control section54issues the slice layer decode starting instruction62. Then, the image decoding section52decodes the slice layer and the MB layer of the picture I2at times t6and t7(legend108inFIG. 9) In this case, decoding is carried out for each one macro-block. Coefficient data generated as a result of the decoding are accumulated into the MB buffer58(legend109inFIG. 9). Then, the slices are sequentially written into the first picture bank53ain the macro-block unit (legend110inFIG. 9).

When all the slices have been written into the first picture bank53aat time t7, “1” is written into the lowest-order bit (LSB) of the status register57. Therefore, the value of the status register57becomes “001”. The decoding of the picture I2has been completed by this time.

Thereafter, at time t8, the decode control section54observes the value of the status register57again. As the value of the status register57is “001”, the picture B0is decoded using, for example, the second banks53band53gof the frame memory53. Therefore, all the parameters of the picture I2that has been decoded immediately before are read from the first parameter bank53f(legend111inFIG. 9). The read-out parameters are then written into the MB buffer58(legend112inFIG. 9).

As the picture I2and the picture B0are the pictures that are included in the same sequence, only the parameters of the picture layer exist in the picture B0. In other words, the parameters of the sequence layer and the GOP layer do not exist in the picture B0. Therefore, in order to obtain parameters corresponding to the parameters of the sequence layer and the GOP layer of the picture B0, the parameters of the sequence layer and the GOP layer of the picture included in the same sequence are necessary. For this purpose, the parameters of the picture (the picture I2in this case) decoded immediately before are read out in the present embodiment.

When all the parameters of the picture I2have been written into the MB buffer58at time t9, the decoding of the picture B0is started (legend113inFIG. 9). As the picture B0starts with the data of the picture layer, the parameters of the sequence layer and the GOP layer stored in the MB buffer58are left as they are, and only the decoded picture layer parameters are overwritten into the MB buffer58(legend114inFIG. 9).

When the writing of the parameters into the MB buffer58has been finished at time t10, the parameters are read out from the MB buffer58(legend115inFIG. 9). The read-out parameters are written into the second parameter bank53g(legend116inFIG. 9). All the parameters of the picture B0have been stored into the second parameter bank53gby this time.

At time t11, the decode control section54issues the slice layer decode starting instruction62. Thus, the image decoding section52decodes the slice layer and the MB layer of the picture B0at times t11to t12(legend117inFIG. 9). The image decoding section52then accumulates the coefficient data into the MB buffer58(legend118inFIG. 9), and sequentially writes the coefficient data into the second picture bank53b(legend119inFIG. 9).

When the writing of all the slices into the second picture bank53bhas been finished at time t12, “1” is written into the center bit of the status register57. Therefore, the value of the status register57becomes “011”. The decoding of the picture B0has been completed by this time.

The picture B1is also decoded in a similar manner. As the value of the status register57at time t15is “011”, the decoding of the picture B1is carried out using the third banks53cand53hof the frame memory53. All the parameters of the picture B0decoded immediately before are read out (legend120inFIG. 9), and the parameters are written into the MB buffer58(legend121inFIG. 9). The picture layer of the picture B1is decoded (legend122inFIG. 9), and the picture layer parameters of the picture B1are overwritten into the MB buffer58(legend123inFIG. 9). The parameters are read from the MB buffer58(legend124inFIG. 9), and the parameters are written into the third parameter bank53h(legend125inFIG. 9). Through the above series of operation, all the parameters of the picture B1are stored into the third parameter bank53h.

When the slice layer decode starting instruction62has been issued at time t17, the slice layer and the MB layer of the picture B1are decoded (legend126inFIG. 9), the coefficient data are accumulated into the MB buffer58(legend127inFIG. 9), and the coefficient data are transferred from the MB buffer58into the third picture bank53c(legend128inFIG. 9). Through the series of the above operation, all the slices of the picture B1are written into the third picture bank53c.Thereafter, “1” is written into the highest-order bit (MSB) of the status register57. The decoding of the picture P5afterward is carried out in a similar manner.

In the mean time, the display control section55observes the status register57at the fall of the vertical synchronization signal (V-Sync)61. The value of the status register57at time t13is “011”. Thus, as the value of the center bit corresponding to the second banks53band53gis “1”, it can be understood that the picture B0to be displayed first is stored in the second banks53band53d,and the picture B0can be displayed.

Therefore, at time t13, the display control section55reads out the parameters of the picture B0from the second parameter bank53g(legend201inFIG. 9). Then, the display control section55analyzes the read-out parameters, and determines how to display the picture. During the period from time t14to t16, the display control section55reads out the decoded picture of the picture B0from the second picture bank53b(legends202and203inFIG. 9), and makes the picture to be displayed in the display unit (legends204and205inFIG. 9). Thereafter, the display control section55writes “0” into the center bit of the status register57. InFIG. 9, the legends204and205denote a top field and a bottom field of the picture B0respectively.

The picture B1is also displayed in a similar manner. At the fall timing of the vertical synchronization signal (V-Sync)61at time t19, the value of the status register57is “101”. Therefore, it can be understood that the third banks53cand53hstore the picture B1that is to be displayed at a second time, and the picture B1can be displayed.

Therefore, the display control section55reads out the parameters of the picture B1at time t19(legend206inFIG. 9), and makes a decision as to how to display the picture. During the period from time t2to t22, the display control section55reads out the decoded picture of the picture B1(legends209and210inFIG. 9), and makes the picture displayed in the display unit (legends209and210inFIG. 9). Thereafter, “0” is written into the highest-order bit (MSB) of the status register57. The decoding and the display of the picture in the normal operation are proceeded in the above-described manner.

Next, the operation in the slide show of the MPEG video decoder relating to the present invention will be explained. The operation in the slide show is basically the same as that in the above-described normal operation, except that the parameters of the sequence layer and the GOP layer attached to each one picture are written into the MB buffer58. The time chart inFIG. 10shows operation timings in a slide show of the MPEG video decoder relating to the present invention.

When the initial decode starting instruction63has been issued at time t0, the decode control section54first observes the status register57. As the status register57is at the initial state, the value of the status register57is “000”. Therefore, the first sequence SEQ1is decoded using, for example, the first banks53aand53fof the frame memory53.

At time t0, all the parameters are read from the first parameter bank53f(legend301inFIG. 10), and these parameters are written into the MB buffer58(legend302inFIG. 10). In the slide show, the sequence layer and the GOP layer are attached to each one picture. Therefore, a series of the read operation for reading these parameters and the write operation for writing these parameters into the MB buffer58are not necessary in principle. However, as the slide show is executed by the operation similar to that in the normal operation, the series of operations are also executed in the slide show.

At time t2, the writing of the content of the first parameter bank53finto the MB buffer58has been finished. At the same time, the decoding of the bit stream is started, and the sequence layer and the GOP layer of the first sequence SEQ1are decoded (legend303inFIG. 10). Subsequently, the picture layer of the first sequence SEQ1is decoded (legend304inFIG. 10). The parameters obtained as a result of the decoding are sequentially written into the MB buffer58while forming the parameters into a format that can be stored into the MB buffer58(legend305inFIG. 10). When the decoding of the picture layer has been finished at time t3, the decoding is halted temporarily.

After the writing of the parameters into the MB buffer58has been finished, the parameters are read out from the MB buffer58at times t4to t5(legend306inFIG. 10). Then, the read-out parameters are written into the first parameter bank53f(legend307inFIG. 10). All the parameters of the first sequence SEQ1have been stored into the first parameter bank53fby this time.

At time t6, the decode control section54issues the slice layer decode starting instruction62. Then, the image decoding section52decodes the slice layer and the MB layer of the first sequence SEQ1for each one macro-block at times t6and t7(legend308inFIG. 10). Coefficient data generated as a result of the decoding are accumulated into the MB buffer58(legend309inFIG. 10). Then, the slices are sequentially written into the first picture bank53ain the macro-block unit (legend310inFIG. 10).

When all the slices have been written into the first picture bank53aat time t7, “1” is written into the lowest-order bit (LSB) of the status register57. Therefore, the value of the status register57becomes “001”. The decoding of the first sequence SEQ1has been completed by this time.

Thereafter, at time t8, the decode control section54observes the value of the status register57again. As the value of the status register57is “001”, the second sequence SEQ2is decoded using, for example, the second banks53band53gof the frame memory53. Therefore, the parameters of the first sequence decoded immediately before are read from the first parameter bank53f(legend311inFIG. 10). The read-out parameters are then written into the MB buffer58(legend312inFIG. 10).

When all the parameters have been written into the MB buffer58at time t9, the decoding of the second sequence SEQ2is started, and the sequence layer and the GOP layer are decoded (legend313inFIG. 10). Subsequently, the picture layer of the second sequence SEQ2is (legend314inFIG. 10). The parameters of the decoded layers are overwritten into the MB buffer (legend315inFIG. 10).

When the writing of the parameters into the MB buffer58has been finished at time t10, the parameters are read out from the MB buffer58(legend316inFIG. 10). The read-out parameters are written into the second parameter bank53g(legend317inFIG. 10). All the parameters of the second sequence SEQ2have been stored into the second parameter bank53gby this time.

At time t11, the decode control section54issues the slice layer decode starting instruction62. Thus, the image decoding section52decodes the slice layer and the MB layer of the second sequence SEQ2at times t11to t12(legend318inFIG. 10). The image decoding section52then accumulates the coefficient data into the MB buffer58(legend319inFIG. 10), and sequentially writes the coefficient data into the second picture bank53b(legend320inFIG. 10).

When the writing of all the slices into the second picture bank53bhas been finished at time t12, “1” is written into the center bit of the status register57. Therefore, the value of the status register57becomes “011”. The decoding of the second sequence SEQ2has been completed by this time.

The third sequence SEQ3is also decoded in a similar manner. As the value of the status register57at time t15is “011”, the decoding of the third sequence SEQ3is carried out using the third banks53cand53hof the frame memory53.

All the parameters stored immediately before are read out (legend321inFIG. 10), and the parameters are written into the MB buffer58(legend322inFIG. 10). The sequence layer and the GOP layer of the third sequence SEQ3are decoded (legend323inFIG. 10). The picture layer of the third sequence SEQ3is decoded (legend324inFIG. 10). The parameters of each layer of the third sequence SEQ3are overwritten into the MB buffer58(legend325inFIG. 10), and the parameters are read from the MB buffer58(legend326inFIG. 10). The parameters are written into the third parameter bank53h(legend327inFIG. 10). Through the above series of operation, all the parameters of the third sequence SEQ3are stored into the third parameter bank53h.

When the slice layer decode starting instruction62has been issued at time t17, the slice layer and the MB layer of the third sequence SEQ3are decoded (legend328inFIG. 10), the coefficient data are accumulated into the MB buffer58(legend329inFIG. 10), and the coefficient data are transferred from the MB buffer58into the third picture bank53c(legend320inFIG. 10). Through the series of the above operation, all the slices of the third sequence SEQ3are written into the third picture bank53c.Thereafter, “1” is written into the highest-order bit (MSB) of the status register57. When there are continuing sequences, the decoding of these sequences is carried out in a similar manner.

In the mean time, the display control section55observes the status register57at the fall of the vertical synchronization signal (V-Sync)61. The value of the status register57at time t13is “011”. Therefore, it is determined that the picture of the first sequence SEQ1is displayed. In the case of the slide show, all the pictures are intra-pictures. Therefore, they can be displayed anytime when their decoding has been completed. At time t13, it is possible to display the first sequence SEQ1and the second sequence SEQ2.

At time t13, the display control section55reads out the parameters of the first sequence SEQ1from the first parameter bank53f(legend401inFIG. 10). As the first parameter bank53fstores the sequence parameters and the GOP parameters of the first sequence SEQ1, it is possible to read out the value of the horizontal size value (for example, “720”) and the value of the vertical size value (for example, “480”).

The display control section55reads out the decoded pictures of the first sequence SEQ1from the first picture bank53a(legend402and403inFIG. 10), and makes the pictures to be displayed in the display unit (legend404and405inFIG. 10). Therefore, at times t14to t16, the pictures of the first sequence SEQ1can be displayed correctly as the parameters and the pictures are combined together correctly. Thereafter, the display control section55writes “0” into the lowest-order bit (LSB) of the status register57.

The pictures of the second sequence SEQ2are also displayed in a similar manner. At the fall timing of the vertical synchronization signal (V-Sync)61at time t19, the value of the status register57is “101”. Therefore, it is determined that the pictures of the second sequence SEQ2are displayed. The display control section55then reads out the parameters of the second sequence SEQ2(legend406inFIG. 10). Then, the display control section55reads out the decoded pictures of the second sequence SEQ2(legend407and408inFIG. 10), and makes the pictures displayed in the display unit (legend409and410inFIG. 10). Thereafter, “0” is written into the center bit of the status register57. The decoding and the display of the pictures in the slide show are proceeded in the above-described manner.

According to the present embodiment, the picture banks53a,53band53cand the parameter banks53f,53gand53hof the frame memory53store the decoded pictures and the parameters of the sequence layer, the GOP layer and the picture layer for displaying the pictures as a set respectively. Therefore, it is possible to continuously decode the pictures of the bit stream like the slide show. Further, as it is possible to display the pictures in a desired order, it is easily possible to reproduce the pictures in the opposite order. Further, it becomes easy to manage the pictures and display parameters in the frame memory53.

The above description assumes MPEG2 as an example. However, it is also possible to apply the present invention to both the MPEG1 and the MPEG2.

In the present embodiment, the frame memory53has banks for three pictures. However, the number of banks is not limited to three, and it is also possible to provide banks for two picture or four pictures or above. Further, it is needless to mention that the MPEG video decoder relating to the present invention is not limited to the above-described embodiment, and the MPEG video decoder can be designed to have various modifications.

As explained above, according to the present invention, each bank of the frame memory stores a decoded picture and the parameters of the sequence layer, the GOP layer and the picture layer respectively for displaying this picture, as a set. Therefore, it is possible to continuously decode pictures of a bit stream like a slide show. Further, it is also possible to display the pictures in an optional order.