Semiconductor device

A semiconductor device includes a semiconductor substrate, an emitter region, a base region and multiple accumulation areas, and an upper accumulation area in the multiple accumulation areas is in direct contact with a gate trench section and a dummy trench section, in an arrangement direction that is orthogonal to a depth direction and an extending direction, a lower accumulation area furthest from the upper surface of the semiconductor substrate in the multiple accumulation areas has: a gate vicinity area closer to the gate trench section than the dummy trench section in the arrangement direction; and a dummy vicinity area closer to the dummy trench section than the gate trench section in the arrangement direction, and having a doping concentration of the first conductivity type lower than that of the gate vicinity area.

NO. 2017-006175 filed in JP on Jan. 17, 2017, and

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor device.

2. Related Art

Conventionally, an insulated gate type bipolar transistor (IGBT) with a charge stored layer has been known (see Patent document 1, for example).

PRIOR ART DOCUMENT

Patent Document

Patent document 1: Japanese Patent Application Publication No. 2007-311627

The larger a displacement current that flows in a gate electrode of the IGBT during a low-current turn-on, the shorter a turn-on time of the IGBT. In a semiconductor device with the IGBT, the shorter the turn-on time, the larger a voltage reduction rate in a voltage between collector and emitter (hereinafter, referred to as ‘dV/dt’). As dV/dt is larger, an electromagnetic noise becomes larger.

SUMMARY

In a first aspect of the present invention, a semiconductor device is provided. The semiconductor device may comprise a semiconductor substrate, an emitter region, a base region, a gate trench section and a dummy trench section, and multiple accumulation areas. The semiconductor substrate may have a drift region of a first conductivity type. The emitter region may be provided over the drift region inside the semiconductor substrate. The emitter region may have a doping concentration of the first conductivity type higher than a doping concentration of the first conductivity type of the drift region. The base region may be provided between the emitter region and the drift region inside the semiconductor substrate. The base region may be of a second conductivity type. The gate trench section and the dummy trench section may be provided to extend from an upper surface of the semiconductor substrate to the drift region by passing through the emitter region and the base region. The gate trench section and the dummy trench section each may have a conductive section in the interior. The multiple accumulation areas may be provided side by side in a depth direction from the upper surface of the semiconductor substrate toward the lower surface thereof, under the base region and between the gate trench section and the dummy trench section. The multiple accumulation areas each may include a region having a doping concentration of the first conductivity type higher than the doping concentration of the first conductivity type of the drift region. The upper accumulation area closest to the upper surface of the semiconductor substrate in the multiple accumulation areas may be in direct contact with the gate trench section and the dummy trench section, in an arrangement direction of the gate trench section and the dummy trench section orthogonal to an extending direction thereof and the depth direction. In a top view of the semiconductor substrate, the extending direction may be the direction in which the longitudinal portions of the gate trench section and the dummy trench section extend. The lower accumulation area may have a gate vicinity area and a dummy vicinity area. The lower accumulation area may be the furthest one from the upper surface of the semiconductor substrate in the multiple accumulation areas. The gate vicinity area may be closer to the gate trench section than the dummy trench section in the arrangement direction. The dummy vicinity area may be closer to the dummy trench section than the gate trench section in the arrangement direction. The dummy vicinity area may have a doping concentration of the first conductivity type lower than that of the gate vicinity area.

The dummy vicinity area may have a doping concentration of the first conductivity type that is the same as the doping concentration of the first conductivity type in the drift region.

The dummy vicinity area may have a doping concentration of the first conductivity type that is higher than the doping concentration of the first conductivity type in the drift region, and that is lower than a peak concentration in the doping concentration of the first conductivity type of the gate vicinity area in the depth direction.

The multiple accumulation areas may have an intermediate accumulation area located between the upper accumulation area and the lower accumulation area. The intermediate accumulation area may have the gate vicinity area and the dummy vicinity area. The gate vicinity area may be closer to the gate trench section than the dummy trench section in the arrangement direction. The dummy vicinity area may be closer to the dummy trench section than the gate trench section in the arrangement direction. In the intermediate accumulation area, the doping concentration of the first conductivity type in the gate vicinity area may be higher than the doping concentration of the first conductivity type in the dummy vicinity area. In the intermediate accumulation area, the length of the gate vicinity area in the arrangement direction area may be shorter than the length of the gate vicinity area in the lower accumulation area in the arrangement direction.

The multiple accumulation areas may have an intermediate accumulation area located between the upper accumulation area and the lower accumulation area. The intermediate accumulation area may have the gate vicinity area and the dummy vicinity area. The gate vicinity area may be closer to the gate trench section than the dummy trench section in the arrangement direction. The dummy vicinity area may be closer to the dummy trench section than the gate trench section in the arrangement direction. The doping concentration of the first conductivity type of the gate vicinity area in the intermediate accumulation area may be higher than the doping concentration of the first conductivity type of the gate vicinity area in the lower accumulation area.

When the length between the gate trench section and the dummy trench section in the arrangement direction is defined as Wm, and the length of the gate vicinity area in the intermediate accumulation area in the arrangement direction is defined as Wa, Wm and Wa may satisfy an expression: 0.55≤Wa/Wm≤0.95.

The lower accumulation area may be located in the lower end vicinity of the gate trench section in the depth direction.

In a second aspect of the present invention, a manufacturing method of a semiconductor device is provided. A manufacturing method of the semiconductor device may comprise: forming a trench section; ion implanting impurities of the first conductivity type on the whole transistor section from the upper surface of the semiconductor substrate; and ion implanting the impurities of the first conductivity type in the state where a mask material is provided over the dummy trench section in the transistor section. The semiconductor substrate may include a drift region of the first conductivity type. The trench section may have the gate trench section and the dummy trench section. In the ion implanting the impurities of the first conductivity type on the whole transistor section from the upper surface of the semiconductor substrate, the upper accumulation area may be formed. The upper accumulation area may be closest to the upper surface of the semiconductor substrate. The transistor section may include the gate trench section and the dummy trench section. In the ion implanting the impurities of the first conductivity type in the state where the mask material is provided over the dummy trench section in the transistor section, at least the lower accumulation area may be formed. The lower accumulation area may be furthest from the upper surface of the semiconductor substrate. In the arrangement direction of the gate trench section and the dummy trench section, the upper accumulation area may be in direct contact with the gate trench section and the dummy trench section. The arrangement direction may be the direction orthogonal to the extending direction and the depth direction. In a top view of the semiconductor substrate, the extending direction may be the direction in which the longitudinal portions of the gate trench section and the dummy trench section extend. The depth direction may be the direction from the upper surface of the semiconductor substrate toward the lower surface. The lower accumulation area may have the gate vicinity area and the dummy vicinity area. The gate vicinity area may be closer to the gate trench section than the dummy trench section in the arrangement direction. The dummy vicinity area may be closer to the dummy trench section than the gate trench section in the arrangement direction. The dummy vicinity area may have a doping concentration of the first conductivity type lower than that of the gate vicinity area.

In the ion implanting the impurities of the first conductivity type in the state where the mask material is provided over the dummy trench section in the transistor section, forming the intermediate accumulation area may be included. The intermediate accumulation area may be located between the upper accumulation area and the lower accumulation area.

The impurities of the first conductivity type may be phosphorus or protons.

DESCRIPTION OF EXEMPLARY EMBODIMENTS

FIG. 1is a view showing a part of an upper surface of a semiconductor device100according to an embodiment in the present invention. The semiconductor device100of the present example is a semiconductor chip that has a transistor section70including a transistor such as IGBT and a diode section80including a diode such as FWD. The diode section80is provided adjacent to the transistor section70in the upper surface of a semiconductor substrate. InFIG. 1, a part of the upper surface of the chip around the chip end portion is shown, and other regions are omitted.

Also, althoughFIG. 1shows an active region of the semiconductor substrate in the semiconductor device100, the semiconductor device100may have an edge termination portion surrounding the active region. The active region refers to a region through which an electric current flows when the semiconductor device100is controlled to be in an on-state. The edge termination portion has a functionality that mitigates an electric field crowding in an upper surface vicinity of the semiconductor substrate. The edge termination portion has more than one structure of, for example, a guard ring, a field plate, a RESURF and a combination thereof.

The semiconductor device100of the present example comprises a well region11, an emitter region12, a base region14, a contact region15, a dummy trench section30and a gate trench section40, each of which is provided to a predetermined depth from the upper surface of the semiconductor substrate. Also, the semiconductor device100of the present example comprises a gate metal layer50and an emitter electrode52provided over the upper surface of the semiconductor substrate. The gate metal layer50and the emitter electrode52are provided with separated from each other.

Note that as used herein, in some cases the dummy trench section30and the gate trench section40are generically referred to as ‘trench section.’ In the present example, the direction in which the dummy trench section30and the gate trench section40are arranged at a predetermined interval is referred to as ‘arrangement direction.’ Also, in the present example, the arrangement direction of the trench section is a direction in parallel to X-axis.

In the present example, the extending direction of the trench section is a direction in parallel to Y-axis. The X-axis and the Y-axis are axes orthogonal to each other in a plane parallel to the upper surface of the semiconductor substrate. Also, the axis orthogonal to the X-axis and the Y-axis is defined as the Z-axis. Note that as used herein, in some cases, a direction in parallel to Z-axis is referred to as ‘depth direction of the semiconductor substrate.’

Note that as used herein, the terms “upper,” “lower,” “over,” and “under” are not limited to a vertical direction in the gravitational direction. These terms merely refer to a relative direction to a predetermined axis.

Although an interlayer dielectric film is provided between the emitter electrode52and the gate metal layer50, and the upper surface of the semiconductor substrate, it is omitted inFIG. 1. The interlayer dielectric film of the present example has contact holes49,54,56and58. The contact holes49,54,56and58of the present example are provided by passing through the interlayer dielectric film.

The emitter electrode52is in contact with the emitter region12and the contact region15on the upper surface of the semiconductor substrate through the contact hole54. Also, the emitter electrode52is electrically connected to the base region14through the contact region15via the contact hole54. Also, the emitter electrode52is connected to a dummy conductive section within the dummy trench section30through the contact hole56and the contact hole58. A connecting portion21or a connecting portion25may be provided between the emitter electrode52and the dummy conductive section, which is formed of a conductive material such as polysilicon doped with impurities. The connecting portion21and the connecting portion25each are provided on the upper surface of the semiconductor substrate through the insulating film.

The gate metal layer50is contact with a gate metal runner48via the contact hole49. The gate metal runner48may be formed of polysilicon doped with impurities, or the like. The gate metal runner48is connected to a gate conductive section within the gate trench section40on the upper surface of the semiconductor substrate. The gate metal runner48is not electrically connected to the dummy conductive section and the emitter electrode52within the dummy trench section30. The gate metal runner48may be electrically separated from the emitter electrode52by the interlayer dielectric film. The gate metal runner48of the present example is provided from a portion under the contact hole49to a tip portion of the gate trench section40. At the tip portion of the gate trench section40, the gate conductive section is exposed to the upper surface of the semiconductor substrate, and is in contact with the gate metal runner48.

The emitter electrode52and the gate metal layer50are formed of a material containing a metal. For example, at least some regions of each electrode are formed of aluminum or an aluminum-silicon alloy or the like. Each electrode may have a barrier metal formed of titanium, a titanium compound or the like in an under layer of a region formed of aluminum or the like, and may have a plug formed of tungsten or the like within the contact hole. The plug may have the barrier metal on the side that is in contact with the semiconductor substrate, tungsten is embedded to be in contact with the barrier metal, so that the tungsten may be in contact with the region formed of aluminum or the like through the barrier metal.

One or more gate trench sections40and one or more dummy trench sections30are arranged at a predetermined interval along a predetermined arrangement direction in a region of the transistor section70. In the transistor section70, one or more gate trench sections40and one or more dummy trench sections30may be provided alternately along the arrangement direction.

The gate trench section40of the present example may have two longitudinal portions which extend along the extending direction, and have a connecting portion which connects between the two longitudinal portions. At least part of the connecting portion is preferably provided in a curved shape. When the end portions of the two longitudinal portions in the gate trench section40are connected, the electric field concentration at the end portions of the longitudinal portions can be mitigated. The gate metal runner48may be connected to the gate conductive section at the connecting portion of the gate trench section40.

In the transistor section70of the present example, the dummy trench section30is provided between the longitudinal portions of the gate trench section40. These dummy trench sections30have a straight shape to extend in the extending direction.

Note that in the transistor section70, a plurality of dummy trench sections30may be arranged at a boundary with the diode section80. At the boundary portion in the transistor section70of the present example, the two dummy trench sections30adjacent in the arrangement direction are provided without the gate trench section40sandwiched therebetween. The dummy trench section30provided at the boundary portion may also include the longitudinal portion and the connecting portion. Note that in the present example, the number of trench sections refers to the number of longitudinal portions of the trench sections arranged in the arrangement direction. The dummy trench section30having the connecting portion and the dummy trench section30having a straight shape may have the same length in the extending direction.

The number of dummy trench sections30arranged serially at the boundary with the diode section80may be greater than the number of dummy trench sections30arranged serially inside the transistor section70away from the diode section80.

In the example ofFIG. 1, in the transistor section70at the boundary with the diode section80, two dummy trench sections30are arranged adjacently. In contrast, inside the transistor section70, the gate trench sections40and the dummy trench sections30are arranged alternately one by one.

The emitter electrode52is provided over the well region11, the emitter region12, base region14, the contact region15, the dummy trench section30and the gate trench section40. The well region11is provided within a predetermined range from the end portion of the active region in the vicinity of the gate metal layer50. The diffusion depth of the well region11may be greater than each depth of the dummy trench sections30and the gate trench sections40. Some regions close to the gate metal layer50of the dummy trench section30and the gate trench section40are provided in the well region11. A bottom of an end of the dummy trench section30in the extending direction may be covered by the well region11.

In the present example, the portion sandwiched by the individual trench sections is referred to as ‘mesa portion.’ The mesa portion has a base region14. The base region14is of the second conductivity type and has a lower doping concentration than that of the well region11. The base region14of the present example is of P-type. Note that in the present example, the first conductivity type is defined as N type, and the second conductivity type is defined as P type. Note that in another example, the first conductivity type may be defined as P type, and the second conductivity type may be defined as N type.

The mesa portion has the contact region15of the second conductivity type having a doping concentration higher than that of the base region14on the upper surface of the base region14. The contact region15of the present example is of P+ type. Also, in the transistor section70, the emitter region12is selectively provided in direct contact with the contact region15on the upper surface of the base region14. The emitter region12has a doping concentration of the first conductivity type higher than a doping concentration of the first conductivity type of the drift region in the semiconductor substrate. The emitter region12of the present example is of N+ type.

Each of the contact region15and the emitter region12is provided from one of the adjacent trench sections to the other. One or more contact regions15and one or more emitter regions12of the transistor section70are provided to be exposed to the uppermost surface of the mesa portion alternately along the extending direction of the trench section.

In another example, the mesa portion in the transistor section70may have the contact region15and the emitter region12with a stripe pattern in parallel to the extending direction. For example, the emitter region12is provided in a region in direct contact with the trench section, and the contact region15is provided in a region sandwiched between the emitter regions12.

The emitter region12may not be provided in the mesa portion of the diode section80. In the present example, in the mesa portion of the diode section80, the contact region15is provided in a region opposed to at least one contact region15in the transistor section70. The diode section80of the present example has an N+ type cathode region82that is exposed to the lower surface of the semiconductor substrate. InFIG. 1, the range in which the cathode region82is provided is shown partially by a dashed line. The cathode region82may be provided in the range of the same depth as that of a P+ type collector region described later (that is, a range in the Z-axis direction). Although the collector region is omitted inFIG. 1, the collector region may be provided in a portion other than the portion in which the cathode region82is provided in an X-Y plane.

In the present example, the collector region is also provided in the region under the mesa portion in direct contact with the transistor section70, in the mesa portion of the diode section80. That is, the collector region extends to the region under that mesa portion in the X-axis direction, and the cathode region82is not provided in the region under that mesa portion in the X-axis direction. Thereby, as compared to the case where the cathode region82is provided on the whole diode section80in the X-axis direction, a distance between the emitter region12, which is provided in the mesa portion in direct contact with the diode section80in the mesa portion of the transistor section70, and the cathode region82of the diode section80can be ensured. Therefore, the electrons injected into the transistor section70from the gate structure section to the drift layer can be prevented from being flown out to the cathode region82of the diode section80.

In the transistor section70, the contact hole54is provided over each region of the contact region15and the emitter region12. The contact hole54is not provided in a region which corresponds to the base region14or the well region11.

In the diode section80, the contact hole54is provided over the contact region15and the base region14. The contact hole54of the present example is not provided over the base region14closest to the gate metal layer50, among the plurality of base regions14in the mesa portion of the diode section80. In the present example, the contact hole54of the transistor section70and the contact hole54of the diode section80have the same length in the extending direction.

FIG. 2is a view showing one example in a section a-a′ inFIG. 1. InFIG. 2, a semiconductor substrate10, an interlayer dielectric film38, an emitter electrode52and a collector electrode24are additionally shown. The emitter electrode52is located on the upper surface92of the semiconductor substrate10and the interlayer dielectric film38. Note that the aforementioned depth direction may be the direction from the upper surface92of the semiconductor substrate10toward the lower surface94.

The collector electrode24is in direct contact with the lower surface94of the semiconductor substrate10. The collector electrode24and the emitter electrode52are formed of a conductive material such as a metal. The semiconductor substrate10may be a silicon substrate, may be a silicon carbide substrate, may be a gallium oxide substrate or may be a nitride semiconductor substrate such as gallium nitride or the like. The semiconductor substrate10of the present example is a silicon substrate.

In the section ofFIG. 2, the mesa portion of the transistor section70has an N+ type emitter region12, a P-type base region14and multiple accumulation areas60in turn from the upper surface92toward the lower surface94. The transistor section70of the emitter region12is provided from the interior of the semiconductor substrate10to the upper surface92. The transistor section70has a drift region18of the first conductivity type under the mesa portion. The drift region18of the present example is of N-type.

The multiple accumulation areas60are provided under the base region14, and side by side in the depth direction between the gate trench section40and the dummy trench section30. In this manner, the base region14of the transistor section70is located between the emitter region12and the multiple accumulation areas60located over the drift region18, in the interior of the semiconductor substrate10.

The multiple accumulation areas60each include a region having a doping concentration of the first conductivity type higher than the doping concentration of the first conductivity type in the drift region18. The multiple accumulation areas60of the present example each are of N+ type. When the multiple accumulation areas60each having a higher concentration than that in the drift region18are provided between the drift region18and the base region14, a carrier injection enhancement effect (Injection Enhanced Effect: IE effect) is increased, which can reduce the on-voltage.

In the present example, the multiple accumulation areas60includes the upper accumulation area62, the intermediate accumulation area64and the lower accumulation area66in turn from the upper surface92toward the lower surface94. The upper accumulation area62is the accumulation area closest to the upper surface92of the semiconductor substrate10in the multiple accumulation areas60. In contrast, the lower accumulation area66is the accumulation area furthest from the upper surface92of the semiconductor substrate10in the multiple accumulation areas60. Also, the intermediate accumulation area64is the accumulation area located between the upper accumulation area62and the lower accumulation area66in the depth direction.

Note that in another example, the multiple accumulation areas60may have two or more intermediate accumulation areas64between the upper accumulation area62and the lower accumulation area66. Further, in still another example, the multiple accumulation areas60may have only the upper accumulation area62and the lower accumulation area66without having the intermediate accumulation area64.

The mesa portion of the transistor section70adjacent to the diode section80has the N+ type emitter region12, the P-type base region14and the N+ type upper accumulation area62in turn from the upper surface92toward the lower surface94. However, in another example, the mesa portion of the transistor section70adjacent to the diode section80may not have the upper accumulation area62. Also, that mesa portion in still another example may include the upper accumulation area62, the intermediate accumulation area64and the lower accumulation area66.

The mesa portion of the diode section80has the P-type base region14that is exposed to the upper surface92. However, the mesa portion of the diode section80adjacent to the transistor section70has the contact region15on the base region14. That contact region15is exposed to the upper surface92. Note that the diode section80does not have the multiple accumulation areas60. Additionally, as not shown, a P type high concentration area shallower than the contact region15may be formed on the upper surface of the base region14. That P type high concentration area reduces the contact resistance between the base region14and the emitter electrode52. In particular, when the plug is formed, the reduction effect of the contact resistance is greater.

In both of the transistor section70and the diode section80, an N+ type buffer region20is provided on a lower surface of the drift region18. The doping concentration of the buffer region20may be higher than the doping concentration of the drift region18. The buffer region20of the present example includes an N+ type impurity region having a plurality of peaks of the doping concentration in the depth direction. The buffer region20may serve as a field stop layer that prevents a depletion layer that expands from the lower surface of the base region14, from reaching the P+ type collector region22and the N+ type cathode region82.

The transistor section70has the P+ type collector region22on a lower surface of the buffer region20. Also, the diode section80has an N+ type cathode region82on the lower surface of the buffer region20. In the present example, the transistor section70is defined as a region such that a predetermined unit structure including the emitter region12and the contact region15is regularly arranged, in a virtual projection region where within the active region, the collector region22is projected from the lower surface94to the upper surface92in a direction perpendicular to the lower surface94. Also, in the present example, the diode section80is defined as a region such that a predetermined unit structure including the emitter region12and the contact region15are not regularly arranged, in a virtual projection region where within the active region, the collector region22and the cathode region82are projected from the lower surface94to the upper surface92in the direction perpendicular to the lower surface94.

One or more dummy trench sections30and one or more gate trench sections40pass through the base region14from the upper surface92of the semiconductor substrate10, and reach the drift region18. For regions provided with at least either of the emitter region12, the contact region15and the upper accumulation area62, the dummy trench section30also passes through these regions and reaches the drift region18. Similarly, for regions provided with at least either of the emitter region12, the contact region15, the upper accumulation area62, the intermediate accumulation area64and the lower accumulation area66, the gate trench section40also passes through these regions and reaches the drift region18. Note that the configuration in which the trench section passes through impurity regions is not limited to the one manufactured by a sequence of forming the trench section after forming the impurity regions. It is assumed that the configuration by forming the impurity region between the trench sections after forming the trench sections also falls within the one in which the trench section passes through the impurity region.

The gate trench section40includes a gate trench43, a gate insulating film42and a gate conductive section44provided in the semiconductor substrate10. The gate insulating film42is provided to cover the inner wall of the gate trench43. The gate insulating film42may be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench43. The gate conductive section44is provided inside the gate trench43at a more inner side than the gate insulating film42. That is, the gate insulating film42insulates the gate conductive section44from the semiconductor substrate10. The gate conductive section44is formed of a conductive material such as polysilicon.

A part of the gate conductive section44faces the base region14in the arrangement direction. The portion facing the gate conductive section44in the base region14may serve as a channel formation region. When a predetermined voltage is applied to the gate conductive section44, a channel is formed in the surface layer of the interface that is in contact with the gate trench43in the base regions14. Note that the gate trench section40inFIG. 2is covered with the interlayer dielectric film38on the upper surface92of the semiconductor substrate10.

The dummy trench section30inFIG. 2may have a structure similar to that of the gate trench section40. The dummy trench section30includes a dummy trench33, a dummy trench insulating film32and a dummy conductive section34provided in the semiconductor substrate10. The dummy trench insulating film32is provided to cover an inner wall of the dummy trench33. The dummy conductive section34is provided inside the dummy trench33and provided at a more inner side than the dummy trench insulating film32. The dummy trench insulating film32insulates the dummy conductive section34from the semiconductor substrate10. The dummy conductive section34may be formed of the same material as the gate conductive section44. For example, the dummy conductive section34is formed of a conductive material such as polysilicon. The dummy conductive section34may have the same length as the gate conductive section44in the depth direction. The dummy trench section30inFIG. 2is also covered with the interlayer dielectric film38on the upper surface92of the semiconductor substrate10.

The upper accumulation area62of the present example is in direct contact with the gate trench section40and the dummy trench section30in the arrangement direction (X-axis direction). That is, the upper accumulation area62covers the whole lower surface of the base region14in each mesa portion.

The lower accumulation area66of the present example has a gate vicinity area66gand a dummy vicinity area66d. The gate vicinity area66gis the region closer to the gate trench section40than the dummy trench section30in the arrangement direction. That is, the gate vicinity area66gextends from the gate trench section40in the arrangement direction, but does not reach the dummy trench section30. In contrast, the dummy vicinity area66dis the region closer to the dummy trench section30than the gate trench section40in the arrangement direction. The dummy vicinity area66dof the present example has a length, in the arrangement direction, from the end portion closest to the dummy trench section30of the gate vicinity area66gto the sidewall closest to the gate trench section40in the dummy trench section30.

The gate vicinity area66gmay have an N type doping concentration not less than the N type doping concentration of the upper accumulation area62. In contrast, the dummy vicinity area66dmay have an N type doping concentration lower than that of the gate vicinity area66g. The dummy vicinity area66dof the present example may have an N type doping concentration that is higher than the N type doping concentration of the drift region18, and that is lower than the N type doping concentration of the upper accumulation area62. Instead of this, as described later, the doping concentration of the dummy vicinity area66dmay be the same as the N type doping concentration of the drift region18. In the lower accumulation area66, the gate vicinity area66gmay contribute mainly to the IE effect.

The intermediate accumulation area64is located between the upper accumulation area62and the lower accumulation area66in the depth direction. Similarly to the lower accumulation area66, the intermediate accumulation area64also has the gate vicinity area64gand the dummy vicinity area64d. In the present example, the N type doping concentration of the gate vicinity area64gis greater than the N type doping concentration in the dummy vicinity area64d. In the present example, one layer of the upper accumulation area62, one layer of the intermediate accumulation area64and one layer of the lower accumulation area66are provided, but the number of layers of each accumulation area is not limited to the above. For example, the accumulation areas by two layers composed of either of the intermediate accumulation area64and the lower accumulation area66, and the upper accumulation area62may be provided. Also, at least one accumulation area of the upper accumulation area62, the intermediate accumulation area64and the lower accumulation area66may be provided by multiple layers.

Although the details will be described later, due to the configuration of the multiple accumulation areas60in the present example, the displacement current can be suppressed that flows from the dummy trench section30to the gate trench section40during a low-current turn-on of an IGBT.

FIG. 3is a view showing one example of doping concentration distributions in a section b-b′ inFIG. 2. The section b-b′ is the section that passes through the upper accumulation area62, the gate vicinity area64gand the gate vicinity area66gto be in parallel to the depth direction. InFIG. 3, there is shown a doping concentration distribution from the emitter region12in the transistor section70to the lower end vicinity of the gate trench section40.

InFIG. 3, the vertical axis indicates a concentration of impurities. Note that the vertical axis is a logarithmic axis, and the concentration is ten times higher by an increase of one graduation thereof. As used herein, a doping concentration refers to a concentration of impurities transformed to donors or acceptors. That is, the doping concentration as used herein corresponds to a difference of concentration of the donors and acceptors (that is, meaning a net doping concentration).

Each of the doping concentration distribution of the upper accumulation area62, the gate vicinity area64gand the gate vicinity area66ghas a peak in the depth direction. In the present example, it is assumed that the number of the accumulation areas including multiple accumulation areas60is the number of the peaks of the doping concentrations. In the present example, the multiple accumulation areas60have three peaks.

As one example, a peak value D62of the doping concentration in the upper accumulation area62is the same as a peak value D64gof the doping concentration in the gate vicinity area64g. The peak value D64gof the doping concentration in the gate vicinity area64gis lower than a peak value D66gin the gate vicinity area66g. In the present example, each doping concentration of the peak values D62and D64gis 1E+17 [cm−3], and the doping concentration of the peak value D66gis 3E+17 [cm−3]. Note that these peak values may have errors of ±10% or so. Note that the letter ‘E’ means powers of 10. For example, 1E+17 means 1.0×1017.

The peak position P62of the doping concentration in the upper accumulation area62, the peak position P64gof the doping concentration in the gate vicinity area64gand the peak position P66gof the doping concentration distribution in the gate vicinity area66gmay be arranged at equal intervals in the depth direction. Note that these peak positions may have errors of ±10% or so. In the present example, the upper surface92is defined as 0 [μm] in depth. In this case, the peak positions P62, P64gand P66gare respectively 2.1 [μm], 3.2 [μm] and 4.3 [μm].

Each peak position P can be determined by an acceleration energy when N type impurities are ion implanted. The tail region of the doping concentration distribution that extends gently from each peak position in the depth direction may be formed by an annealing after the ion implantation.

It is desirable that in the multiple accumulation areas60, the gate vicinity area66gis provided in the lower end vicinity of the gate trench section40in the depth direction. In the present example, the configuration in which the gate vicinity area66gis provided in the lower end vicinity of the gate trench section40means the one in which the peak position of the doping concentration of the gate vicinity area66gis closer to the upper surface92by a predetermined length between 1 [μm] and 1.5 [μm] from the lower end of the gate trench section40in the depth direction. In the present example, P66gis closer to the upper surface92by 1.2 [μm] from the lower end of the gate trench section40.

When the lower accumulation area66is provided in the lower end vicinity of the gate trench section40, the degradation in breakdown voltage of the semiconductor device100can be suppressed, as compared to the case where the lower accumulation area66is provided closer to the lower surface94than the lower end vicinity of the gate trench section40. For example, in the present example, the breakdown voltage can be improved, as compared to the case where the gate vicinity areas64gand66gare closer to the upper accumulation area62than those in the example ofFIG. 3. Also, for example, in the present example, the breakdown voltage can be improved, as compared to the case where only the upper accumulation area62and the gate vicinity areas64gare provided. Note that in addition to the case where the upper accumulation area62and the gate vicinity areas64gand66gare provided, the effect by the improvement of the breakdown voltage can also be obtained in the case where the upper accumulation area62and the gate vicinity area66gare provided.

The doping concentration in the region between the upper accumulation area62and the gate vicinity area64g, and the doping concentration in the region between the gate vicinity area64gand the gate vicinity area66geach may be higher than the doping concentration Ddof the drift region18. That is, a local minimum value Dmlof the doping concentration distribution at the boundary between the upper accumulation area62and the gate vicinity area64gmay be the same as the doping concentration Ddof the drift region18or larger than the Dd. Similarly, a local minimum value Dm2of the doping concentration distribution at the boundary between the gate vicinity area64gand the gate vicinity area66gmay also be the same as the doping concentration Ddof the drift region18or larger than the Dd. Each of the peak values D62, D64gand D66gmay be ten times or more the local minimum value Dmlor Dm2, and may be one hundred times or more thereof.

FIG. 4is a view showing one example of doping concentration distributions in a section c-c′ inFIG. 2. The section c-c′ is the section that passes through the upper accumulation area62, the dummy vicinity area64dand the dummy vicinity area66dto be in parallel to the depth direction. InFIG. 4, there is shown a doping concentration distribution from the emitter region12in the transistor section70to the lower end vicinity of the gate trench section40. Since the vertical axis and the horizontal axis are the same as those ofFIG. 3, these descriptions will be omitted. The doping concentration distribution in the section c-c′ is shown by a solid line. Note that the doping concentration distribution in the section b-b′ ofFIG. 3is shown by a dashed line for reference.

In the present example, a difference from the example ofFIG. 3is that each of the dummy vicinity areas64dand66dhas an N type doping concentration lower than the peak value D62. Each of the dummy vicinity areas64dand66dmay have an N type doping concentration higher than the N type doping concentration Ddin the drift region18. Also, each of the dummy vicinity areas64dand66dmay have an N type doping concentration lower than each of the peak concentrations D64gand D66gof the N type doping concentration of the gate vicinity areas64gand66gin the depth direction. In the present example, the peak concentrations D64dand D66dof the dummy vicinity areas64dand66din the depth direction each have an N type doping concentration lower than each of the local minimum values Dmland Dm2. The respective positions of the peak concentrations D64dand D66dmay be the same as those of P64gand P66g.

The peak concentrations D64dand D66dof the dummy vicinity areas64dand66deach may have an N type doping concentration that is 1.2 times or more, 1.3 times or more, 1.4 times or more, or 1.5 times or more of the doping concentration Ddof the drift region18. The dummy vicinity areas64dand66dof the present example may also contribute to the IE effect, although the effect is smaller than that by the gate vicinity areas64gand66g.

Note that the doping concentration Ddof the drift region18may be the doping concentration between the lower end of the gate trench section40and the buffer region20in the depth direction. The doping concentration Ddof the drift region18is, for example, a net doping concentration at the intermediate position between the lower end of the gate trench section40and the buffer region20in the depth direction. The doping concentration Ddof the drift region18may be an average value of the doping concentration in a predetermined depth range. In one example, the doping concentration Ddof the drift region18may be an average value of the doping concentration from the position that is lowered by 1 μm from the lower end of the gate trench section40to the position that is raised by 1 μm from the boundary between the drift region18and the buffer region20.

Instead of this, in another example, the dummy vicinity areas64dand66deach may have an N type doping concentration that is the same as the N type doping concentration in the drift region18. In this case, the doping concentration distribution of the dummy vicinity areas64dand66dis shown by an alternate long and short dash line. In this case, the intermediate accumulation area64and the lower accumulation area66may be configured by the gate vicinity areas64gand66g.

FIG. 5is an enlarged view in the vicinity of the gate trench section40inFIG. 2. In the present example, the length Wa of the gate vicinity area64gin the arrangement direction is shorter than the length Wb of the gate vicinity area66gin the arrangement direction (Wa<Wb). However, in another example, Wb<Wa may be allowed. Also, the length Wb is shorter than the shortest distance Wm between the gate trench section40and the dummy trench section30in the arrangement direction (Wb<Wm). Wa and Wm may satisfy an expression: 0.55≤Wa/Wm≤0.95. Also, Wb and Wm may satisfy an expression: 0.7<Wb/Wm<1. The gate vicinity areas64gand66gmay be separated from the dummy trench section30. Note that Wm may be provided between 0.4 [μm] and 1.8 [μm].

FIG. 6Ais a view showing an electron current and a displacement current during the low-current turn-on in Comparative Example 1 having only the upper accumulation area62. InFIG. 6A, in consideration of viewability of the drawing, only the vicinity of one pair of trench sections inFIG. 5is shown. During the low-current turn-on, the voltage of the gate conductive section44is gradually raised from 0[V]. Thereby, a negative charge is induced in the vicinity of the gate trench section40in the base region14, so that a channel is formed.

The majority of the current at an early stage during the low-current turn-on is not a hole current, but the electron current. The early stage refers to a period from a time immediately before the gate voltage Vge reaches a threshold voltage to a time that enters a mirror period at which Vge becomes constant at the value of almost the threshold voltage. As the Vge comes closer to the threshold voltage, opening of the channel is started, and injection of electrons into the drift region is started. In Comparative Example 1 ofFIG. 6A, there is a possibility that the electrons that travel downward from the channel is liable to travel once in the arrangement direction (X direction) in the upper accumulation area62. Note that in the drift region18under the upper accumulation area62, the accumulation layer of the electrons has been already formed in the vicinity of the gate trench section40(the threshold voltage in which the accumulation layer of the electrons is formed in the N type region is by far smaller than the threshold voltage of an inversion layer in the P type region), thus having a lower impedance than that of the drift region18. Therefore, the electron current flows mainly in the vicinity of the gate trench section40.

When the electrons reach the collector region on the backside, injection of holes is started from the collector region to the buffer region and the drift region. In Comparative Example 1 ofFIG. 6A, the inventor in the present case confirmed by simulation that the holes exist on the order of 1E+16 [cm−3] from the lower end vicinity of the gate trench section40to the side portion of the dummy trench section30located under the upper accumulation area62. The holes are concentrated at the respective lower ends of the gate trench section40and the dummy trench section30. Since in particular, the dummy conductive section34has the same potential as that of the emitter electrode52, the inversion layer of the holes is formed at the sidewall of the dummy trench section30. The holes injected from the collector region are concentrated on the vicinity of the inversion layer of the holes. The holes are accumulated from the dummy trench section30to the lower end of the gate trench section40. Due to this hole distribution, a larger displacement current as compared to the example inFIG. 6Bdescribed later flows to the lower end vicinity of the gate trench section40during the low-current turn-on.

The displacement current due to the accumulation of the holes causes the chargings of the gate conductive sections44facing each other across the gate insulating film. The chargings of the gate conductive sections44causes a momentary increase of a gate electrode Vge. As that displacement current is larger, the gate conductive section44is charged faster, so that the potential of the gate conductive section44is raised more quickly. As a result, the potential of the gate conductive section44will exceed momentarily a gate threshold. Thereby, a large amount of injection of the electrons and the holes is started, so that a current between collector and emitter is increased. The voltage reduction rate (dV/dt) of the voltage between collector and emitter is increased according to the current change rate by the increase of the current between collector and emitter. As the displacement current is larger, the dV/dt becomes larger. In particular, as the accumulated holes flow less in the emitter electrode, the displacement current becomes larger, so that the momentary increase in potential of the gate conductive section44becomes larger. Therefore, in Comparative Example 1 inFIG. 6A, the dV/dt becomes relatively larger, and the electromagnetic noise also becomes relatively larger.

FIG. 6Bis a view showing the electron current and the displacement current during the low-current turn-on in the present example. Also inFIG. 6B, only the vicinity of only the one pair of trench sections inFIG. 5is shown. Also in the present example, the electrons are liable to travel in the arrangement direction (X direction) in the upper accumulation area62. However, in the present example, the intermediate accumulation area64and the lower accumulation area66are provided under the upper accumulation area62. In the present example, the impedance for the electron current is lower in the case where it travels from the upper accumulation area62to the intermediate accumulation area64and the lower accumulation area66, than the case where it returns to the vicinity of the gate trench section40again. Therefore, the electron current of the present example does not return to the vicinity of the gate trench section40, but travels downward in the central vicinity of the mesa sandwiched between the gate trench section40and the dummy trench section30. That is, the electron current of the present example flows in the central vicinity of the mesa, not in the vicinity of the gate trench section40. An effect where this electron current flows in the central vicinity of the mesa cannot be produced by an accumulation area with only a single layer, which cannot be predicted. That is, the effect is the one to be obtained for the first time in the case where the multiple accumulation areas60of the present example are involved.

When the electron current flows in the central vicinity of the mesa, the holes are divided into parts at the central vicinity of the mesa, and forced to flow toward either of the gate trench section40side or the dummy trench section30side. This division of the holes at the mesa central portion suppresses the accumulation of the holes at the lower end of the gate trench section40. As a result, the displacement current can be made smaller as compared to the example ofFIG. 6A. Since the displacement current can be made smaller, the charging of the gate conductive section44becomes smaller, so that a momentary increase of the gate electrode Vge can also be suppressed. Thereby, the voltage reduction rate (dV/dt) in the voltage between collector and emitter can also be suppressed.

The inventor in the present case confirmed by simulation that the holes are mainly distributed at the lower end of the gate trench section40, and at the lower end and the side portion of the dummy trench section30, but hardly distributed at the mesa central portion. The holes exist on the order of 1E+13 [cm−3] in the lower end vicinity of the gate trench section40and the lower end vicinity of the dummy trench section30, so that it is sufficiently lower than 1E+16 [cm−3] in Comparative Example 1 ofFIG. 6A. Although it is not limited to the following reason, it is considered that the hole distribution in the present example ofFIG. 6Bis due to a fact in which the holes between the gate trench section40and the dummy trench section30are divided into parts by the electron current. Also, due to that hole distribution, during the low-current turn-on, the displacement current smaller than that of Comparative Example 1 inFIG. 6Aflows from the lower end vicinity of the dummy trench section30to the lower end vicinity of the gate trench section40.

Therefore, since in the present example, the displacement current is smaller than that of Comparative Example 1 inFIG. 6A, dV/dt becomes smaller than that of Comparative Example 1 inFIG. 6A, and the electromagnetic noise can also be made smaller. Also, in the present example, for the purpose of suppression of a quick increase in the potential of the gate conductive section44, an additional gate resistance Rg may not be provided in the gate conductive section44, or may be a sufficiently small Rg. Therefore, it is also advantageous that the electric power loss during the turn-on can be reduced as compared to Comparative Example 1 ofFIG. 6A.

In addition, in the present example, the gate vicinity areas64gand66gare not in direct contact with the dummy trench section30. Therefore, the holes can exist from the lower end of the dummy trench section30to the portion immediately under the upper accumulation area62at the side portion of the dummy trench section30. Thereby, the holes can be pulled in to the vicinity of the upper surface92, as compared to the case where the gate vicinity areas64gand66gare in direct contact with the dummy trench section30. Therefore, during a turn-off, the holes accumulating in the vicinity of the dummy trench section30can be pulled out more from the P+ type contact region15.

That is, in the present example, as compared to the case where the gate vicinity areas64gand66gare in direct contact with the dummy trench section30, the holes accumulating in the vicinity of the dummy trench section30associated with the turn-on and turn-off can be reduced. Thereby, the division of the holes at the mesa central portion can be facilitated, and a momentary increase of the gate voltage Vge can be further suppressed. Also, a trade-off characteristic between the on-voltage and the turn-off loss of the IGBT can be improved.

FIG. 6Cis a view showing Comparative Example 2 having multiple accumulation areas60. InFIG. 6C, only the structure in the vicinity of only the one pair of trench sections inFIG. 5is shown. Similarly to the example ofFIG. 6B, Comparative Example 2 inFIG. 6Chas the upper accumulation area62, the intermediate accumulation area64and the lower accumulation area66. Note that both the intermediate accumulation area64and the lower accumulation area66of Comparative Example 2 extend from the gate trench section40to the dummy trench section30. That is, the intermediate accumulation area64and the lower accumulation area66in Comparative Example 2 do not have the dummy vicinity areas64dand66d.

FIG. 7is a view showing simulations of Vge and Vce during the low-current turn-on. Vge is a potential difference between the gate metal layer50and the emitter electrode52, and Vce is a potential difference between the collector electrode24and the emitter electrode52. Vge and Vce in Comparative Example 1 ofFIG. 6Ais shown by dashed lines, and Vge and Vce in the present example ofFIG. 6Bis shown by a solid line. Further, Comparative Example 2 ofFIG. 6C(an example in which high concentration areas at multiple stages are connected to the dummy trench section30) is shown by a dashed line. The left side of the vertical axis indicates Vce [V], and the right side of the vertical axis indicates Vge [V]. The horizontal axis indicates time [s].

As shown inFIG. 7, in Comparative Example 1 ofFIG. 6Aand the present example ofFIG. 6B, a positive potential was applied to the gate metal layer50at a time 1E−5 [s]. The Vge in Comparative Example 1 ofFIG. 6Awas raised to around 8.6 [V] once, and then settled to about 7 [V] by a time 1.03E−5 [s]. Hereinafter, a matter that the Vge is momentarily increased in this manner will be referred to as ‘momentary increase (rapid spike).’ On the other hand, the magnitude (absolute value) of the voltage reduction rate (dV/dt) of Vce was about 14000 [V/μs], and almost maintained to about 14000 [V/μs] up to the time when the voltage is below 40 [V]. Thereafter, the Vge in Comparative Example 1 ofFIG. 6Awas maintained at 7 [V] to a time 1.04E−5 [s], and the potential was gradually raised after the time 1.04E−5 [s]. Note that a period at which Vge was the constant value at about 7 [V] is referred to as ‘mirror period.’

The Vge in the present example ofFIG. 6Bwas once raised to around 8.1 [V] lower by 0.5 [V] than that of Comparative Example 1, and then settled to about 7 [V] by the time 1.03E−5 [s]. On the other hand, the dV/dt of the Vce was about 5800 [V/μs] around from about 1.028E−5 [s] at which the voltage starts falling down at the maximum reduction rate. Further subsequently, the magnitude of the dV/dt was reduced, and reduced to about 1200 [V/μs] at the time of 200 [V] or less in the voltage. This value was one-tenth or less that of Comparative Example 1.

With respect to Comparative Example 2 ofFIG. 6C, similarly to the present example ofFIG. 6B, main differences were as follows: the Vge peak value of the gate voltage during the rapid spike was 7.8 [V] lower by 0.3 [V] than that in the present example ofFIG. 6B; and the dV/dt of 200 [V] or less in the voltage was about 1600 [V/μs].

After a positive potential was applied to the gate metal layer50, a conductivity modulation was generated in the drift region18, so that the Vce was gradually dropped. In the Vce in Comparative Example 1 ofFIG. 6A, the potential was dropped rapidly from a time 1.01E−5 [s] to a time 1.015E−5 [s]. In contrast, in the present example ofFIG. 6B, the potential was dropped from the time 1.015E−5 [s] to a time 1.045E−5 [s]. That is, in the present example ofFIG. 6B, the potential was dropped slowly by taking three times the time as compared toFIG. 6A. In this manner, in the present example, the dV/dt during the low-current turn-on could be suppressed.

Note that the mirror periods in the present example and Comparative Example 2 each were longer than that of Comparative Example 1 by two times or more. However, this is adjustable by a gate resistance. That is, in the present example and Comparative Example 2, the dV/dt was lowered to be one-tenth or near that of Comparative Example 1; thus, when the gate resistance is made smaller by that amount, the mirror period becomes shorter.

In the present example inFIG. 6B, it is advantageous that the trade-off between the on-voltage and the turn-off loss is better than that of Comparative Example 2 ofFIG. 6C. In Comparative Example 2 ofFIG. 6C, the on-voltage is made lower than that in the present example ofFIG. 6B, but the turn-off loss is made higher than that in the present example ofFIG. 6B. When the on-voltage and the turn-off loss are considered in a comprehensive manner, the present example ofFIG. 6Bis superior to that in Comparative Example 2 ofFIG. 6C.

FIG. 8is a flowchart showing one example of a manufacturing method of the semiconductor device100. In the present example, individual steps are carried out in the order from step S100to step S160(that is, in ascending order of the number).

FIG. 9includes views showing step S100to step S106. (a) inFIG. 9shows step S100that forms the trenches having the dummy trench33and the gate trench43in the semiconductor substrate10. The semiconductor substrate10may be the substrate having an N-type drift region18as an impurity region. In step S100, the trenches may be formed by selectively etching the upper surface92of the semiconductor substrate10by use of a mask material (not shown). Note that a line segment a-a′ in the figure means that (a) inFIG. 9shows the same section as that ofFIG. 2. Also, wave lines in the figure mean that the length between the upper surface92and the lower surface94is omitted.

(b) inFIG. 9shows step S102that thermally oxidizes the semiconductor substrate10. The thermally oxidized film102may be formed on the whole surface of the semiconductor substrate10. In step S102, it may be formed at least on the upper surface92and inside the trenches. Since the semiconductor substrate10of the present example is a silicon substrate, the thermally oxidized film102is a silicon oxide film. The silicon oxide film to be formed in contact with the gate trench43may be considered as the gate insulating film42, and the silicon oxide film to be formed in contact with the dummy trench33may be considered as the dummy trench insulating film32.

(c) inFIG. 9shows step S104that forms a conductive layer104on the semiconductor substrate10. The conductive layer104may be formed to be in contact with the upper surface92and the thermally oxidized film102inside the trench. The conductive layer104may be formed by chemical vapor deposition (CVD). The conductive layer104of the present example is a polysilicon layer doped with impurities.

(d) inFIG. 9shows step S106that etches the conductive layer104. In the etching of step S106, the thermally oxidized film102may serve as an etching stopper. By that etching, the conductive layer104located on the upper surface92may be removed. Note that the upper portion of the conductive layer104located inside the trench section may be recessed through the etching of step S106. In the present example, each upper portion of the dummy conductive section34and the gate conductive section44has a V-shape in a sectional view of (d) inFIG. 9. Thereby, the gate trench section40and the dummy trench section30are formed.

FIG. 10includes views showing step S110to step S116. (a) inFIG. 10shows step S110that forms the base region14. In step S110, after P type impurities are ion implanted on the whole upper surface92, the semiconductor substrate10is subjected to an annealing. The ion implanted P type impurities are diffused and activated by the annealing. Also, the crystallinity of the semiconductor substrate10destructed by the ion implantation may be recovered to some extent by the annealing. The annealing may be performed for about three hours at about 1150 degrees C.

(b) inFIG. 10shows step S112that forms the upper accumulation area62. In the present example, the upper accumulation area62is not provided in the diode section80. Then, a mask material112is provided over the diode section80. In contrast, the mask material112is not provided over the transistor section70. In this manner, when the mask material112is selectively provided, and N type impurities are ion implanted from the upper surface92, the N type impurities can be ion implanted over a predetermined depth range in the transistor section70. At step S112, protons or phosphorus may be ion implanted. Since protons are ion implanted in the present example, hydrogen may exist as the N type impurities in the upper accumulation area62. The mask material112may be formed of a photoresist.

(c) inFIG. 10shows step S114that forms the intermediate accumulation area64and the lower accumulation area66in sequence. Note that either of the intermediate accumulation area64and the lower accumulation area66may be formed in advance. In one example, the N type impurities may be ion implanted at the depth position corresponding to the intermediate accumulation area64, and then the N type impurities may be ion implanted at the depth position corresponding to the lower accumulation area66. Also, in another example, the N type impurities may be ion implanted at the depth position corresponding to the lower accumulation area66, and then the N type impurities may be ion implanted at the depth position corresponding to the intermediate accumulation area64.

At step S114, in addition to the upper portion of the diode section80, the mask material114is provided in the upper portion of the dummy trench section30in the transistor section70. In this manner, in the state where the mask material114is selectively provided, the N type impurities are ion implanted. The mask material114may also be formed by the photoresist.

At step S114, the ion implantations may be performed by a plurality of times at different ranges for the impurities to be ion implanted. In the present example, protons are ion implanted at different depths of the semiconductor substrate10. Protons can be implanted to a deeper position as compared to phosphorus ions or the like, and also has a small variation at the implanted position. When the intermediate accumulation area64and the lower accumulation area66located at a position deeper than that of the upper accumulation area62are formed of protons, the intermediate accumulation area64and the lower accumulation area66can be formed more readily, as compared to the case formed by phosphorus. In addition, in the case where protons are used as compared to the case where phosphorus is used, it is advantageous in that since the peak of the doping concentration distribution in the multiple accumulation areas60can be steeply formed, the multiple accumulation areas60having a narrow depth range can be readily formed.

(d) inFIG. 10shows step S116that forms the emitter region12and the contact region15. In the present example, in the state where a mask material (not shown) having an opening at a position corresponding to the emitter region12is provided, the N type impurities are ion implanted from the upper surface92. The N type impurities may be phosphorus. Also, in the state where a mask material (not shown) having an opening at a position corresponding to the contact region15is provided, P type impurities are ion implanted from the upper surface92. The P type impurities may be boron or aluminum. Note that either of the ion implantation of the N type impurities for formation of the emitter region12and the ion implantation of the P type impurities for formation of the contact region15may be performed in advance. After that N type and P type impurities are ion implanted, the semiconductor substrate10may be subjected to the annealing. The annealing at step S116may be the annealing at a lower temperature and for a shorter time as compared to the annealing in the formation of the base region14(step S110). For example, the annealing at step S116is performed at about 1000 degrees C. for about 30 minutes.

FIG. 11includes views showing step S120to step S140. (a) inFIG. 11shows step S120that forms the interlayer dielectric film38and the contact hole54. The interlayer dielectric film38may be formed of BPSG, PSG or BSG. The contact hole54may be formed by selectively removing the interlayer dielectric film38. Note that the thermally oxidized film102immediately under the contact hole54may be removed at step S120. Also, the contact hole49,56and58may be formed at step S120.

(b) inFIG. 11shows Step S130that forms a plug53and the emitter electrode52. The plug53and the emitter electrode52may be formed by sputtering. The plug53may be embedded in the contact hole54to be defined at the side portion of the interlayer dielectric film38and the upper surface92. Note that as described inFIG. 2, the plug53may be lacking. The plug53may be a lamination structure composed of a barrier metal such as tungsten that is thinner than a thickness of the interlayer dielectric film38that is formed on the upper surface92of the semiconductor substrate10and on the sidewall of the interlayer dielectric film38, and of a tungsten that is formed substantially flush with the upper surface of the interlayer dielectric film38when a concave portion defined by that barrier metal is embedded. The emitter electrode52may be provided uniformly on the plug53and the interlayer dielectric film38. The emitter electrode52may be formed of aluminum or an alloy of aluminum-silicon.

(c) inFIG. 11shows step S140that thins the semiconductor substrate10. At step S140, the lower surface94of the semiconductor substrate10is grinded to adjust the thickness of the semiconductor substrate10. The thickness of the semiconductor substrate10may be set according to a breakdown voltage to be involved by the semiconductor device100.

FIG. 12includes views showing step S150and step S160. (a) inFIG. 12shows step S150that forms the P+ type collector region22, the N+ type cathode region82and the collector electrode24. The collector region22and the cathode region82may be formed by ion implantation. Also, the collector electrode24may have a lamination structure formed by sputtering. The collector electrode24may be formed by the following manner: a titanium layer is formed in direct contact with the lower surface94; a nickel layer is formed in direct contact with that titanium layer; and a gold layer is formed in direct contact with that nickel layer.

(b) inFIG. 12shows step S160that forms the buffer region20. At step S160, protons may be implanted from the lower surface94. Protons may be implanted in the buffer region20by a plurality of times at different depth positions. Also, after the implantation of protons, the semiconductor substrate10may be subjected to an annealing to activate the protons implanted in the buffer region20. For example, the annealing is performed at a temperature from about 350 degrees C. to about 450 degrees C. in order to activate the ion implanted protons. Thereby, a plurality of peaks may be formed in the doping concentration distribution of the buffer region20in the depth direction. Note that the formation of the collector electrode24may be performed after the formation of the buffer region20. Thus, the semiconductor device100can be manufactured.

FIG. 13is an enlarged view in the vicinity of a gate trench section40in a first modification example. The upper accumulation area62of the present example is the same as that in the example ofFIG. 2. However, the semiconductor substrate10of the present example does not have an intermediate accumulation area64. Also, in the present example, the upper accumulation area62and the lower accumulation area66are provided step-wise in the depth direction. Such a point is different from the example ofFIG. 2.

The lower accumulation area66of the present example may have the gate vicinity area66gand the dummy vicinity area66d. The gate vicinity area66gmay have a peak of the doping concentration as shown in the example ofFIG. 3, and may have a uniform doping concentration without peaks. The dummy vicinity area66dmay have a doping concentration lower than the peak concentration of the gate vicinity area66g, and may have the same doping concentration as that of the drift region18. Also in the present example, the advantageous effect in the example ofFIG. 6Bcan be acquired.

FIG. 14is an enlarged view in the vicinity of a gate trench section40in a second modification example. In the lower accumulation area66of the present example, the length of the gate vicinity area66gin the arrangement direction (X-axis direction) is gradually shortened across from the lower end of the upper accumulation area62to the lower end of the gate trench section40. That is, the outer shape of the gate vicinity area66gis provided in a curved shape. Such a point is different from the example ofFIG. 13.

In the present example, corresponding to the length of the gate vicinity area66gin the arrangement direction, the length of the dummy vicinity area66din the arrangement direction is gradually lengthened as going downward. Such a point is different from the first modification example ofFIG. 13. Also in the present example, the advantageous effect in the example ofFIG. 6Bcan be acquired.

FIG. 15is a view showing doping concentration distributions in sections A-A inFIG. 13andFIG. 14. The vertical axis indicates a doping concentration NDcorresponding to a logarithmic display. The multiple accumulation areas60may be completely separated from the dummy trench section30. The complete separation may comprise, for example, a region having a doping concentration N0in the drift region18between the multiple accumulation areas60and the dummy trench section30. Also in the present example, the advantageous effect in the example ofFIG. 6Bcan be acquired.

On the other hand,FIG. 16is a view showing another example of the doping concentration distributions in the sections A-A ofFIG. 13andFIG. 14. As shown inFIG. 16, the multiple accumulation areas may be in contact with the dummy trench section30as reducing the concentration toward the dummy trench section30, and may be separated from the dummy trench section30. Also in the present example, the advantageous effect in the example ofFIG. 6Bcan be acquired.

EXPLANATION OF REFERENCES