Semiconductor device and method for manufacturing the same

A method for manufacturing a semiconductor device is provided. The method includes forming multiple conductive patterns 13a, forming an intermediate insulating film 16 on all of device isolation insulating films 6 and the conductive patterns 13a, forming a second conductive film 17 on the intermediate insulating film 16, patterning the second conductive film 17, the intermediate insulating film 16, and the multiple conductive patterns 13a, individually, to make the conductive patterns 13a into floating gates 13c and to make the second conductive film 17 into multiple strip-like control gates 17a. In the method, an edge, in a plan layout, of at least one of each of the conductive patterns 13a and each of the device isolation insulating films 6 is bent in a region between the control gates 17a adjacent in a row direction.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon prior International Patent Application No. PCT/JP2007/55666, filed on Mar. 20, 2007, the entire contents of which are incorporated herein by reference.

FIELD

It is related to a semiconductor device and a method for manufacturing the semiconductor device.

BACKGROUND

There are various types of nonvolatile memories formed on semiconductor substrates. Among those, a flash memory, which stores information by accumulating electrons in a floating gate, is generally and widely used due to the merits that higher integration can be achieved.

Such flash memory includes an ONO film and a control gate which are formed on a floating gate. Of these films, unnecessary ONO film at portions between cells is desired to be removed by etching. In reality, however, some portions of the ONO film between the cells are not etched due to a step of an underlying layer, so that the etching residues of ONO film remain.

For example, in Japanese Laid-open Patent Publication No. 05-267683, in order to solve a problem that a residue of an ONO film causes an electric short-circuit between adjacent floating gates and thereby lowers a yield, the ONO film is formed after insulating side walls are formed on side surfaces of the floating gates. In this way, the etching residue of the ONO film is unlikely to be left.

However, when the insulating side walls are newly formed in this manner, the number of manufacturing processes is increased, which in turn increases the manufacturing cost of a semiconductor device.

SUMMARY

According to one aspect discussed herein, a semiconductor device includes a semiconductor substrate, device isolation insulating films formed in the semiconductor substrate, a tunnel insulating film formed over the semiconductor device between the device isolation insulating films, a plurality of floating gates formed in a matrix form over the tunnel insulating film, an intermediate insulating film formed over the floating gates, and a plurality of strip-shaped control gates that are respectively formed over the intermediate insulating films, the control gate collectively covering the plurality of the floating gates aligned in a single column, wherein a residue of the intermediate insulating film is formed to linearly extend over the device isolation insulating film or over the tunnel insulating film in a region between the control gates adjacent in a row direction, and a portion of the residue is located out of a slanting surface of the device isolation insulating film.

According to another aspect discussed herein, a method for manufacturing a semiconductor device includes forming device isolation insulating films in a semiconductor substrate, forming a tunnel insulating film over the semiconductor substrate between the device isolation insulating films, forming a first conductive film over the device isolation insulating films and the tunnel insulating film, patterning the first conductive film to make the first conductive film into a plurality of conductive patterns separated from one another over the device isolation insulating films, forming an intermediate insulating film over the device isolation insulating films and the conductive patterns, forming a second conductive film over the intermediate insulating film, patterning the second conductive film, the intermediate insulating film, and the plurality of conductive patterns to make the plurality of conductive patterns into a plurality of floating gates in a matrix form, and to make the second conductive films into a plurality of strip-shaped control gates each collectively covering the plurality of the floating gates aligned in a single column, wherein, in a region between the control gates adjacent in a row direction, an edge of a plan layout of either the conductive pattern or the device isolation insulating film is bent.

DESCRIPTION OF EMBODIMENT

FIGS. 1A to 1Pare cross-sectional views of a semiconductor device according to a preliminary explanation during the manufacturing thereof.FIGS. 2A to 2Gare plan views of this semiconductor. Note that the cross-sectional views inFIGS. 1A to 1Pcorrespond to the cross-sectional views taken along the lines X1-X1, X2-X2, and Y1-Y1ofFIGS. 2A to 2G.

This semiconductor device is a flash memory and is manufactured in the following manner.

Firstly, a thermal oxide film2is formed on a surface of a p type silicon substrate1. Thereafter, a silicon nitride film3is formed on the thermal oxide film2by a CVD (chemical vapor deposition) method. After that, a photoresist is applied on the silicon nitride film3. The photoresist is then exposed and developed, so as to form a first resist pattern4including windows4a.

FIG. 2Ais a plan view after this process is finished. As depicted inFIG. 2A, each window4aof the first resist pattern4has a strip-shaped planar shape extending in a row direction.

Subsequently, as depicted inFIG. 1B, the silicon nitride film3is dry-etched through the windows4aso as to form openings having shapes corresponding respectively to the windows4a, in the silicon nitride film3. Furthermore, the thermal oxide film2which is exposed through the openings is removed by dry etching, so that openings2aas depicted inFIG. 1Bare formed in the thermal oxide film2.

After that, the first resist pattern2is removed.

FIG. 2Bis a plan view after this process is finished. As depicted inFIG. 2B, the planar shape of each opening2ais strip-shaped, and extends in the row direction.

Next, as depicted inFIG. 1C, surfaces of the silicon substrate1, which are exposed respectively through the openings2a, are thermally oxidized to respectively form device isolation insulating films6each formed of a field oxide film. Such a device isolation structure is also referred to as LOCOS (local oxidation of silicon).

The plan view after this process is finished becomes likeFIG. 2C. As depicted inFIG. 2C, each device isolation insulating film6has a strip-shaped planar shape extending in the row direction.

Then, as depicted inFIG. 1D, after the silicon nitride film3is removed by dry etching, ions of p type impurities are ion-implanted to a predetermined depth into the silicon substrate1with the thermal oxide film2being used as a through film. Consequently, a p well10is formed.

Furthermore, the thermal oxide film2is wet-etched, so that a clean surface of the silicon substrate1between the adjacent device isolation insulating films6is exposed as depicted inFIG. 1E.

FIG. 2Dis a plan view after the processes up to this point are finished.

Subsequently, as depicted inFIG. 1F, the clean surface of the silicon substrate1which is exposed between the adjacent device isolation insulating films6is thermally oxidized to form a thermal oxide film with a thickness of approximately 9 nm. The resultant thermal oxide film serves as a tunnel insulating film11.

Next, as depicted inFIG. 1G, by a CVD method using a mixed gas of silane (SiH4) and phosphine (PH3), a polysilicon film is formed as a first conductive film13with a thickness of approximately 90 nm on the tunnel insulating films11. Here, the polysilicon film is caused to be an n type by doping phosphorus thereinto at the time of its film formation.

Note that, in place of such a polysilicon film, an amorphous silicon film into which an n type impurity is doped may be formed as the first conductive film13.

After that, as depicted inFIG. 1H, a photoresist is applied to the entire upper surface of the first conductive film13. The photoresist is then exposed and developed, so as to form a second resist pattern15including windows15aover the device isolation insulating films6.

FIG. 2Eis a plan view after the second resist pattern15is formed in this manner.

After that, as depicted inFIG. 1I, byusing the second resist pattern15as a mask, the first conductive film13is dry-etched. The first conductive film13thus dry-etched serves as multiple conductive patterns13a, which are separated from one another on the device isolation insulating films6.

This dry etching is performed by RIE (reactive ion etching) using a mixed gas of, for example, Cl2and O2as an etching gas.

Here, it is ideally preferable that side surfaces of the conductive pattern13abe positioned on top surfaces6aof the device isolation insulating films6. However, in reality, due to misalignment between the conducive pattern13aand the device isolation insulating film6, the side surface13xof the conductive pattern13amay be positioned, in some cases, on a slanting surface6bof the device isolation insulating film6as depicted in the dotted circle inFIG. 1I.

When the side surface13xis positioned on the slanting surface6bin this manner, the side surface13xat a portion in contact with the slanting surface6bextends in a trailing manner.

After the etching is finished, the second resist pattern15is removed.

FIG. 2Fis a plan view after this process is finished.

As depicted inFIG. 2F, each conductive pattern13ahas a strip-shaped planar shape extending in the row direction and is formed in such a manner that the side surfaces thereof overlap with the device isolation insulating films6.

Next, as depicted inFIG. 1J, an ONO film is formed, as an intermediate insulating film16, on each of the device isolation insulating films6and the conductive patterns13a.

The intermediate insulating film16is formed by forming a first thermal oxide film16x, a silicon nitride film16y, and a second thermal oxide film16zin this order.

Among these films, the first thermal oxide film16xis formed by thermally oxidizing the upper surface of the conductive pattern13aand has a thickness of approximately 8 nm. In addition, the silicon nitride film16yis formed by a CVD method with a thickness of approximately 10 nm on the first thermal oxide film16x. Then, the second thermal oxide film16zis formed by thermally oxidizing the silicon nitride film16yformed thereunder and has a thickness of approximately 4 nm.

Note that, in place of such an ONO film, an ONONO film which is formed by sequentially forming a silicon nitride film and a silicon oxide film further on the ONO film, or a single-layered silicon oxide film may be formed as the intermediate insulating film16. This is also the case for first to fourth embodiments to be described later.

Next, as depicted inFIG. 1K, a polysilicon film with a thickness of approximately 120 nm and a tungsten silicide (WSi) film with a thickness of approximately 150 nm are formed in this order on the intermediate insulating film16by a CVD method. These films serve a second conductive film17.

After that, as depicted inFIG. 1L, a photoresist is applied on the second conductive film17. The photoresist is then exposed and developed, so as to form a third resist pattern20. The third resist pattern20has a strip-shaped planar shape corresponding to control gates to be described later. Note that a silicon nitride film may be formed as an antireflection film on the second conductive film17before the third resist pattern20is formed.

Subsequently, as depicted inFIG. 1M, by using the third resist pattern20as a mask, the second conductive film17is dry-etched by RIE using a mixed gas of Cl2, O2, and HBr as an etching gas. The second conductive film17, which is not etched and thus is left, becomes control gates17a.

Furthermore, as depicted inFIG. 1N, the etching gas is changed in the etching chamber used in the above RIE, so that portions of the intermediate insulating film16which are not covered with the control gate17aare removed by etching. In this etching, a mixed gas of, for example, CF4and Ar is used as an etching gas.

Here, this etching is anisotropic etching in which the etching rate is greatest in a direction vertical to the upper surface of the silicon substrate1. Accordingly, the intermediate insulating film16formed on the upper surfaces of the conductive patterns13acan be completely removed by the etching. However, the intermediate insulating film16formed on the side surface13xof the conductive pattern13acannot be completely removed, because the film thickness thereof on the side surface13xin the vertical direction of the silicon substrate1is thicker than those in the other portions.

As a result, as depicted in the dotted circle inFIG. 1N, a residue16aof the intermediate insulating film16is left on the side surface13xof the conductive pattern13a.

Next, as depicted inFIG. 1O, while using the etching chamber again described above, and changing the etching gas to a mixed gas of Cl2, O2, and HBr, portions of the conductive pattern13awhich are not covered with the third resist pattern20are removed by the RIE. The conductive patterns13a, which are not etched and thus left, serves as floating gates13c.

As described above, the residues16aof the intermediate insulating film16are left on the device isolation insulating films6. Moreover, as described by referring toFIG. 1I, the side surface13xof the conductive pattern13is formed on the slanting surface6bof the device isolation insulating film6in the trailing manner. For this reason, when this etching is finished, as depicted in the dotted circle inFIG. 1O, the conductive pattern13ahidden by the trailing portion of the residue16ais left unetched. Accordingly, a stringer (a linear residue)13bof the conductive pattern13ais left beside the residue16a.

After that, the third resist pattern20is removed.

FIG. 2Gis a plan view after this process is finished.

As depicted inFIG. 2G, multiple floating gates13care formed in a matrix form. In addition, each control gate17ahas a strip-shaped planar shape, which collectively covers the multiple floating gates13caligned in a single column.

In addition, the residue16aextends from one floating gate13cto the other floating gate13c, where the floating gates13cbeing adjacent in the row direction. Accordingly, when the stringer13bof the conductive pattern13ais formed beside the residue16aas described above, the adjacent floating gates13care electrically short-circuited by the stringer13b.

Firstly, while using the control gates17aas masks, ions of n type impurities are ion-implanted into the silicon substrate1, so that n type source/drain extensions21are formed in the silicon substrate1beside the floating gates13c.

Subsequently, an insulating film is formed on the entire upper surface of the silicon substrate1. The insulating film is then etched back to be left beside each of the control gates17aas insulating side walls26. The insulating film is, for example, a silicon oxide film formed by a CVD method.

Thereafter, while using the insulating side walls26and the control gates17aas masks, ions of n type impurities are ion-implanted into the silicon substrate1. With this, as depicted inFIG. 1P, source lines24and drain regions23are formed in the silicon substrate1beside the floating gates13c.

Note that the source line24is formed in such a way as to extend in a strip-like shape in a direction same as that of the control gates17a. A portion of the device isolation insulating film6which intersects with the source line24is removed in advance before the source line24is formed.

Furthermore, by a sputtering method, a refractory metal film such as a titanium film is formed on each of the upper surfaces of the silicon substrate1and the control gates17a. Then, the refractory metal film is subjected to annealing to be reacted with silicon, so that a metal silicide layer25is formed. After that, the refractory metal film which is left unreacted on the insulating side walls26and the like is removed by wet etching.

With the processes described up to this point, formed in the silicon substrate1are flash memory cells FL each including the floating gate13c, the intermediate insulating film16, the control gate17a, the source line24, the drain region23, and the like.

Thus, the basic structure of the semiconductor device is completed.

In this semiconductor device, as described by referring toFIG. 1O, the side surface of the conductive pattern13ais formed on the slanting surface6bof the device isolation insulating film6in the trailing manner. As a result, the stringer13bof the conductive pattern13ais left beside the residue16aof the intermediate insulating film16.

FIG. 3is a view drawn based on an SEM (scanning electron microscope) image of this semiconductor device. In the portion A inFIG. 3, the trailing of the conductive pattern13aoccurs.

When such trailing generates in the stringer13b, floating gates13cof the flash memory cell FL, which are adjacent in the row direction, are electrically short-circuited. Accordingly, electrons accumulated in one of the floating gates13cmove to the other one of the floating gates13cthrough the stringer13b. Thus, an inversion of memory data or the like is caused, thereby deteriorating the retention characteristic of the flash memory.

In particular, such a problem becomes prominent when misalignment occurs between the device isolation insulating film6and the conductive pattern13a, so that the side surface of the conductive pattern13ais positioned on the slanting surface6bof the device isolation insulating film6.

FIG. 14is a graph obtained by examining a relationship between percentage defective of the semiconductor device and an amount of misalignment between the device isolation insulating film6and the conductive pattern13a.

Note that, inFIG. 14, it is assumed that the misalignment amount is set to be 0 when the device isolation insulating film6and the conductive pattern13aare positioned as designed, and that the misalignment amount indicates a plus value when the device isolation insulating film6is misaligned to the right or left side thereof, for example, to the right side.

As depicted in the graph, the percentage defective is suppressed to low levels when the absolute value of the misalignment amount is 0.04 μm or less. However, when the absolute value of the misalignment amount exceeds 0.04 μm, the increase of the percentage defective becomes prominent.

Thus, the semiconductor device including the flash memory cells is desired to have a structure in which the percentage defective is not increased even when the device isolation insulating film6and the conductive pattern13aare misaligned.

With this taken into consideration, the inventor of the present application has come up with embodiments as described below. Note that, in the figures to be referred to in each of the following embodiments, same reference numerals are given to denote components same as those described in the preliminary explanation, and the descriptions thereof are omitted.

First Embodiment

FIGS. 4A to 4Dare plan views of a semiconductor device according to a first embodiment during the manufacturing thereof. In addition,FIGS. 5A to 5Dare enlarged cross-sectional views taken along the line X3-X3ofFIGS. 4A to 4D. Furthermore,FIGS. 6A to 6Eare cross-sectional views taken along the lines X1-X1, X2-X2, and Y1-Y1ofFIGS. 4A to 4D.

In the present embodiment, while performing the same processes as those described in the preliminary explanation, the plan layout of the second resist pattern15is changed as described below, so that a semiconductor device in which the retention characteristic of a flash memory can be improved is manufactured.

To manufacture such a semiconductor device, as depicted inFIGS. 4A,5A, and6A, a second resist pattern15is firstly formed by performing the processes ofFIGS. 1A to 1Hdescribed in the preliminary explanation.

As depicted in the plan view ofFIG. 4A, according to the present embodiment, in a region B between the adjacent control gates17athat is formed later, a convex portion15xwhich protrudes toward the inner side of the device isolation insulating film6is provided in each edge of the second resist pattern15.

Subsequently, as depicted inFIGS. 4B,5B, and6B, by using the second resist pattern15as a mask, a first conductive film13is etched by the method described in the preliminary explanation, so as to form multiple conductive patterns13awhich are separated from one another on the device isolation insulating films6.

Note that, in the plan view ofFIG. 4B, the second resist pattern15is omitted for the plan layout of the conductive pattern13ato be easily seen.

As depicted inFIG. 4B, each conductive pattern13ahas a substantially strip-shaped planar shape extending in a row direction. Furthermore, convex portions13xwhich protrude, in a plan view, toward the inner sides of the respective device isolation insulating film6are formed in accordance with the convex portions15xin the second resist pattern15.

After that, the second resist pattern15is removed.

Next, the processes ofFIGS. 1J to 1Ndescribed in the preliminary explanation are performed to obtain the structure depicted inFIGS. 4C,5C, and6C.

As depicted inFIG. 4C, since the convex portions13xare provided in each edge of the conductive pattern13aas described above, residues16ain the region B between the control gates17aare caused to have linear planar shapes that follow the convex portions13xand bend toward the inner sides of the device isolation insulating film6.

Subsequently, the conductive patterns13aare etched according to the process ofFIG. 1Oin the preliminary explanation. Accordingly, as depicted inFIGS. 4D,5D, and6D, portions of the conductive patterns13awhich are not covered with the control gates17aare removed, thereby forming multiple floating gates13cin a matrix form.

Here, the residue16aextends from one of the each adjacent floating gate13cto the other floating gate13c.

After that, the process ofFIG. 1Pdescribed in the preliminary explanation is performed to complete the basic structure of the semiconductor device according to the present embodiment as depicted inFIG. 6E.

According to the present embodiment as described above, as depicted inFIG. 4D, the residues16aof the intermediate insulating film16are formed to bend toward the inner sides of the device isolation insulating films6, in the region B between the control gates17aadjacent in the row direction.

For this reason, when misalignment occurs between the device isolation insulating film6and the conductive pattern13a, a portion16dof the residue16ais positioned out of the slanting surface6bof the device isolation insulating film6but is positioned on the top surface6aas depicted in the dotted circle inFIG. 4D.

As depicted inFIG. 5B, the trailing of the side surface of the conductive pattern13adoes not occur on the top surface6a. Accordingly, a stringer13bof the conductive pattern13a(seeFIG. 4D) is not formed beside the residue16a. Therefore, as depicted in the dotted circle inFIG. 4D, the stringer13bformed on the slanting surface6bis divided by the top surface6a. Thus, the floating gates13cadjacent in the row direction are prevented from being electrically short-circuited by the stringer13b. Consequently, the retention characteristic of the semiconductor device including the flash memory is improved, and the yield of the semiconductor device is also improved.

Moreover, in the present embodiment, as compared with the case of the preliminary explanation, it is only needed to change the plan layouts of the conductive patterns13a. Accordingly, some new additional processes are not needed. Thus, an increase in manufacturing cost of the semiconductor device can be suppressed.

Second Embodiment

FIGS. 7A and 7Bare plan views of a semiconductor device according to a second embodiment during the manufacturing thereof.FIGS. 8A and 8Bare enlarged cross-sectional views taken along the line X3-X3of these plan views.

To manufacture this semiconductor device, the processes ofFIGS. 1A to 1Idescribed in the preliminary explanation are performed to form conductive patterns13aas depicted inFIGS. 7A and 8A.

In the present embodiment, however, as depicted inFIG. 7A, concave portions13yrecessed in a direction away from the device isolation insulating film6is provided in the edges of the conductive patterns13athat extend in a strip-like shape in a row direction.

After that, the processes ofFIGS. 1J to 1Oin the preliminary explanation are performed to obtain the structure depicted inFIGS. 7B and 8B.

As depicted inFIG. 7B, the concave portions13yare provided in the edge of the conductive pattern13a. Therefore, the planar shapes of residues16ain a region B between the control gates17aextend in such a way as to bend toward the outer sides of the device isolation insulating films6.

Accordingly, in the case where the device isolation insulating film6and the conductive pattern13aare misaligned, a portion16cof the residue16aof the intermediate insulating film16is formed on a tunnel insulating film11. Since the upper surface of the tunnel insulating film11is flat, the trailing of the conductive pattern13aas described in the preliminary explanation does not occur. Accordingly, a stringer13bof the conductive pattern13ais not left beside the portion16cof the residue16a. Thus, the floating gates13cadjacent in the row direction can be prevented from being electrically short-circuited by the stringer13b.

Third Embodiment

FIGS. 9A to 9Fare plan views of a semiconductor device according to a third embodiment during manufacturing process thereof. In addition,FIGS. 10A to 10Fare enlarged cross-sectional views taken along the line X3-X3ofFIGS. 9A to 9F. Furthermore,FIGS. 11A to 11Gare cross-sectional views taken along the lines X1-X1, X2-X2, and Y1-Y1ofFIGS. 9A to 9F.

In the above-described first and second embodiments, the convex portions13xor the concave portions13yare provided in the conductive pattern13a, so that the stringer13bis divided at the region between the floating gates13cthat are adjacent in the row direction.

In contrast, in the present embodiment, while performing the same processes as those in the preliminary explanation, the plan layout of the device isolation insulating film6is changed as follows to divide the stringer13b.

To manufacture the semiconductor device according to the present embodiment, as depicted inFIGS. 9A,10A, and11A, the first resist pattern4is firstly formed by performing the process ofFIG. 1Adescribed in the preliminary explanation.

As depicted in the plan view ofFIG. 9A, in the present embodiment, convex portions4xare provided in the window4aof the first resist pattern4.

Subsequently, as depicted inFIGS. 9B,10B, and11B, similar toFIG. 1Bin the preliminary explanation, by using the first resist pattern4as a mask, a thermal oxide film2and a silicon nitride film3are dry-etched to form openings2ain these films. Thereafter, the first resist pattern4is removed.

As depicted inFIG. 9B, convex portions2xreflecting the convex portions4xof the first resist pattern4are formed in the opening2a.

Subsequently, as depicted inFIGS. 9C,10C, and11C, by performing the process ofFIG. 1Cdescribed in the preliminary explanation, surfaces of a silicon substrate1which are exposed through the opening2aare thermally oxidized to form device isolation insulting films6formed of a thermal oxide film.

As depicted in the plan view ofFIG. 9C, reflecting the convex portions2xof the opening2a, concave portions6xare formed in the edge of the device isolation insulating film6in such a way as to be recessed in a direction toward the inner side of the device isolation insulating film6.

Thereafter, the thermal oxide film2and the silicon nitride film3are removed by wet etching so as to obtain the structure depicted inFIGS. 9D,10D, and11D.

Next, the processes ofFIGS. 1F to 1Idescribed in the preliminary explanation are performed to form strip-shaped conductive patterns13aextending in a row direction, as depicted inFIGS. 9E,10E, and11E.

Here, when the conductive pattern13aand the device isolation insulating film6are misaligned, a side surface13xof the conductive pattern13ais positioned out of a slanting surface6b, and the side surface13xis positioned on a tunnel insulating film11formed on the flat surface of the silicon substrate1, as depicted inFIG. 10E.

Furthermore, the processes ofFIGS. 1J to 1Oin the preliminary explanation are performed to pattern the conductive patterns13a, the intermediate insulating film16, and the second conductive film17, so that floating gates13cand control gates17aas depicted inFIGS. 9F,10F, and11F are formed.

Among these processes, the process of etching the intermediate insulating film16is performed as described inFIG. 1Nbefore the floating gates13care formed. In this process, the residue16aof the intermediate insulating film16is linearly formed along the edge of the conductive pattern13a.

Note that, in the present embodiment, unlike the first and second embodiments, the convex portions13xand the concave portions13yare not provided in the first conductive film13a. Instead, the edges of the first conductive film13aare linearly formed like the preliminary explanation. Accordingly, the planar shape of each residue16ais also linearly formed.

In addition, as depicted in the dotted circle inFIG. 9F, the concave portions6xare provided in the device isolation insulating film6. Accordingly, when the conductive pattern13aand the device isolation insulating film6are misaligned, a portion16eof the residue16ais positioned out of the slanting surface6bof the device isolation insulating film6, and the portion16eis formed on the tunnel insulating film11beside the concave portion6x.

In addition, another portion6fof the residue16ais positioned out of the slanting surface6b, and the portion16fis positioned on the top surface6a.

Furthermore, in the process of forming the control gates17a, the stringer13bof the conductive pattern13ais formed beside the residue16aformed on the slanting surface6b, due to the trailing of the conductive pattern13aas described in the preliminary explanation. However, since the tunnel insulating film11and the top surface6aare made flat, such trailing does not occur on these films and thus the stringer13bis not formed beside the portions6eand6fof the residue16a.

Thereafter, the process ofFIG. 1Pdescribed in the preliminary explanation is performed to complete the basic structure of the semiconductor device according to the present embodiment as depicted inFIG. 11G.

In the above-described present embodiment, in the process of forming the device isolation insulating films6(FIGS. 9A to 9D), in the region B between the control gates17aadjacent in the row direction, the concave portions6xrecessed toward the inner side of the device isolation insulating film6is provided in the plan layout of the device isolation insulating film6

With this configuration, as depicted in the dotted circle inFIG. 9F, the portions6eand6fof the residue16aof the intermediate insulating film16are formed to be located out of the slanting surfaces6bof the device isolation insulating film6. Therefore, the stringer13bof the first conductive film13ais not formed beside the portions6eand6f. Accordingly, the stringers13bin the region B are divided. Consequently, the floating gates13cadjacent in the row direction are prevented from being electrically short-circuited by the conductive stringers13b.

Fourth Embodiment

FIGS. 12A and 12Bare plan views of a semiconductor device according to a fourth embodiment during the manufacturing thereof.FIGS. 13A and 13Bare enlarged cross-sectional views taken along the line X3-X3in these plan views.

To manufacture this semiconductor device, the processes ofFIGS. 1A to 1Edescribed in the preliminary explanation are performed to form device isolation insulating films6as depicted inFIGS. 12A and 13A.

In the present embodiment, however, as depicted inFIG. 12A, in the processes ofFIGS. 1A to 1E, convex portions6yprotruding toward the outer side of the device isolation insulating film6are provided in the edges of the plan layout of the device isolation insulating film6in the plan view.

After that, the processes ofFIGS. 1F to 1Oin the preliminary explanation are performed to obtain the structure depicted inFIGS. 12B and 13B.

Note that, in the present embodiment, for the reason similar to the third embodiment, residues16aof the intermediate insulating film16are linearly formed.

According to the present embodiment, as depicted in theFIGS. 12B and 13B, the convex portions6yare provided in the device isolation insulating film6. Therefore, when the conductive pattern13aand the device isolation insulating film6are misaligned, a portion16cof the residue16aof the intermediate insulating film16is formed on a top surface6aof the device isolation insulating film6. Since the top surface6ais planar, the trailing of the conductive pattern13aas described in the preliminary explanation does not occur. Accordingly, a stringer13bof the conductive pattern13ais not left beside the portion16cof the residue16a. Thus, the floating gates13cadjacent in a row direction can be prevented from being electrically short-circuited by the stringer13b.

The embodiments are described thus far in detail. However, the present embodiments are not limited to the above-described embodiments.

For example, in the first and second embodiments, the convex portions13xand the concave portions13yare provided in the conductive pattern13a. However, as long as the edge of the conductive pattern13ais bent, the shape to be given to the conductive pattern13ais not limited to these shapes. Similarly, in the third and fourth embodiments as well, as long as the edge of the device isolation insulating film6is bent, the shape of the edge is not limited to the concave portions6xor the convex portions6y.

Furthermore, the first to fourth embodiments may be arbitrarily combined, as long as the edge of the plan layout of either of the conductive patterns13aand device isolation insulating films6is bent.