Method for forming passivation layer

A method for forming a passivation layer is disclosed. In the method, a substrate containing a top surface and a bottom surface opposite to the top surface is first provided, wherein a plurality of conductive pads are disposed on the top surface thereof. Thereafter, a first passivation layer is formed on the top surface of the substrate, wherein the first passivation layer has a characteristic of photoresist. A first exposure/develop step is then performed to form a plurality of first openings in the first passivation layer, wherein the conductive pads are exposed through the first openings. Then, a second passivation layer is formed on the first passivation layer, wherein the second passivation layer has a characteristic of photoresist. A second exposure/develop step is then performed to form a plurality of second openings in the second passivation layer, wherein the conductive pads are exposed through the second openings.

RELATED APPLICATIONS

The present application is based on, and claims priority from, Taiwan Application Serial Number 95111057, filed Mar. 29, 2006, the disclosure of which is hereby incorporated by reference herein in its entirety.

FIELD OF THE INVENTION

The present invention relates to a method for forming a passivation layer, and more particularly, to a method for forming a passivation layer with the capability of reducing voids.

BACKGROUND OF THE INVENTION

With the development of semiconductor technology, the requirements for packaging integrated circuits have becoming stricter. Currently, most of the high pin-count chips (such as graphic chips and chip sets, etc.) are packaged by a BGA (Ball Grid Array) technique, wherein the BGA technique can be divided into five categories including a PBGA (Plastic BGA) substrate, a CBGA (Ceramic BGA) substrate, a FCBGA (FlipChip BGA) substrate, a TBGA (Tape BGA) substrate, and a CDPBGA (Carity Down PBGA) substrate. The FCBGA technique is to dispose Au or solder bumps on an IC chip for soldering to a printed wiring board (PWB).

For example, referring toFIG. 1,FIG. 1is a schematic cross-sectional view showing the structure of a conventional solder bump prepared by a film electro-deposition process. Such as shown inFIG. 1, a silicon wafer100includes a conductive pad12, a passivation layer110, a conductive layer180and a solder ball190. The conductive pad102, such as an aluminum pad or a copper pad, is used for forming an electrical connection to an external circuit (not shown). The passivation layer110is used for providing a semiconductor structure with protection and a planarization surface, wherein the passivation layer110allows the surface102aof the conductive pad102to be exposed. The conductive layer10, such as a UBM (Under Bump Metallurgy Layer) layer formed by sputtering, covers a portion of the passivation layer110and the surface102aof the conductive pad102. The UBM layer is typically composed of an adhering/diffusion barrier layer160and a wetting layer170, for increasing the adhesion between the solder ball190and the conductive pad102.

Referring toFIG. 2AtoFIG. 2D,FIG. 2AtoFIG. 2Dare schematic cross-sectional views showing the process for making the passivation layer110shown inFIG. 1. At first, such as shown inFIG. 2A, a silicon wafer100is provided, wherein the silicon wafer110has a plurality of conductive pads102formed thereon. Then, such as shown inFIG. 2B, a passivation layer110is coated on the silicon wafer100so as to cover the conductive pads102, wherein the passivation layer110is made of polyimide, and the thickness thereof is about 10 μm. Thereafter, such as shown inFIG. 2C, an exposure/develop step is performed to form a plurality of openings112on the passivation layer110for exposing the conductive pads102. Then, such as shown inFIG. 2D, a baking step is performed for curing the passivation layer110. In the conventional skill, since the passivation layer110is formed by only one costing step and covers the entire surface of the silicon wafer100, a particle104(shown inFIG. 2A) if existing on the silicon wafer100will easily result in a void114(shown inFIG. 2D) formed on the surface of the final passivation layer110, wherein the existence of the void114will easily cause customer complaints and lower the product yield.

SUMMARY OF THE INVENTION

Therefore, an improved method for forming a passivation layer is desired to solve the problems of the voids caused by the particles formed on the passivation layer in the conventional process, thereby promoting the product quality and process yield.

One aspect of the present invention is to provide a method for filling up the voids formed on the passivation by applying the steps of passivation-layer coating and exposure/develop twice, thereby overcoming the problems of the voids caused by the particles remaining on the substrate.

According to a preferred embodiment of the present invention, the method for forming a passivation layer comprises providing a substrate, wherein the substrate has a top surface and a bottom surface opposite to the top surface, and the top surface has a plurality of conductive pads; forming a first passivation layer on the top surface; performing a first exposure/develop step to form a plurality of first openings in the first passivation layer, wherein the conductive pads are exposed through the first openings; forming a second passivation layer on the first passivation layer, the ratio of the thickness of the first passivation layer and the thickness of the second passivation layer is substantially at least two; and performing a second exposure/develop step to form a plurality of second openings in the second passivation layer, wherein the conductive pads are exposed through the second openings.

With the application of the aforementioned method for forming a passivation layer, two coating steps for forming the passivation layer are used to replace the original single coating step for forming the same, so that it can be assured that the passivation layer formed by the first coating step does not have any void existing after the second coating step is performed, thus avoiding customer complaints and lowered product yield caused by the overlarge voids remaining in the passivation layer. Therefore, with comparison to other conventional processes, the process disclosed in the present invention not only can resolve the problems of poor passivation layer quality and lowered product yield, but also can greatly save fabrication time and cost.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring toFIG. 3AtoFIG. 3F,FIG. 3AtoFIG. 3Fare schematic cross-sectional views showing the process for making a passivation layer according to a preferred embodiment of the present invention. At first, such as shown inFIG. 3A, a substrate300is provided. In the present embodiment, the substrate is a wafer having a top surface300aand a bottom surface300bopposite to the top surface300a, wherein there are a plurality of conductive pads302disposed on the top surface300a. At this point, since the substrate300has not been cleaned up, there is at least a particle304remaining on the top surface300a. Thereafter, such as shown inFIG. 3B, a first passivation layer310is formed on top of the top surface300ato cover the conductive pads302. In the present embodiment, the first passivation layer310is made of polyimide, which has a characteristic of negative photoresist, so that the unexposed portion of the first passivation layer310will be removed via a develop step, and the other exposed portion thereof will remain. However, the present invention is not limited thereto, and the material having a characteristic of positive photoresist also can be used to form the first passivation layer310. At this point, if there is a particle403remaining on the top surface300a, at least one void314(shown inFIG. 3C) will be formed in a portion of the first passivation layer310to expose the substrate300in the subsequent exposure/develop step. In the present embodiment, the thickness of the first passivation layer310is about 8 μm. Then, such as shown inFIG. 3C, a first exposure/develop step is performed to form a plurality of first openings312on the first passivation layer310for exposing the conductive pads302. Meanwhile, the remaining particle304results in the void314formed on the first passivation layer310. Thereafter, such as shown inFIG. 3D, a second passivation layer320is formed on top of the first passivation layer310to cover the conductive pads. In the present embodiment, the second passivation layer320is made of polyimide, which has a characteristic of negative photoresist, so that the unexposed portion of the second passivation layer320will be removed via a develop step, and the other exposed portion thereof will remain. However, the present invention is not limited thereto, and the material having a characteristic of positive photoresist also can be used to form the second passivation layer320. If there is a void314existing on the first passivation layer310, the void314is filled up with the second passivation layer320at this point. Further, in the present embodiment, the thickness of the second passivation layer320is about 2 μm. It is worthy to be noted that the ratio of the thickness of the first passivation layer310and the thickness of the second passivation layer320is substantially at least two. Such that, the void314formed on the first passivation layer310can be filled up with the second passivation layer310subsequently coated, and if there are still other particles remaining on the second passivation layer320, those particles will not result in large voids since the second passivation layer320is thinner. Thereafter, such as shown inFIG. 3E, a second exposure/develop step is performed to form a plurality of second openings322on the second passivation layer320for exposing the conductive pads302. Then, a baking step is performed for curing the first passivation layer310and the second passivation layer320.

In brief, the method of the present invention for forming a passivation layer is featured in dividing the single coating step for forming the original passivation layer into two coating steps for forming the novel passivation layer having the same thickness as the original passivation layer. The method of the present invention can assure that the passivation layer formed by the first coating step does not have any void existing after the second coating step is performed, thus avoiding customer complaints and lowered product yield caused by the overlarge voids remaining in the passivation layer. Therefore, with comparison to other conventional processes, the process disclosed in the present invention can substantially prevent voids from forming on the passivation layer, so that the product quality and process yield can be greatly promoted.

According to the aforementioned preferred embodiments of the present invention, one advantage of applying the method of the present invention for forming a passivation layer is that the original single coating step for forming the passivation layer is replaced with two coating steps by using the same process equipment, such that no voids or voids smaller than the client standard will be formed on the passivation layer of the same thickness, thus preventing the problem of lowering process yield from occurring. Hence, the present invention not only resolves the void problem occurring in the conventional process, but also greatly promotes the quality and process yield of the passivation layer, and further save fabrication time and cost.