Process for fabricating circuit substrate

A process for fabricating a circuit substrate is provided. A patterned conductive layer having an inner pad is provided on a base layer, a dielectric layer is disposed on the base layer and covers the patterned conductive layer, and a covering layer is disposed on the dielectric layer. A part of the covering layer is removed by dry etching to form a first opening. A part of the dielectric layer exposed by the first opening is removed to form a dielectric opening exposing a part of the inner pad. A patterned mask having a second opening to expose a part of the inner pad is formed on the covering layer. A conductive structure including a conductive block filling the dielectric opening, an outer pad filling the first opening and a surplus layer filling the second opening is formed. Finally, the patterned mask, surplus layer and covering layer are removed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a circuit substrate and fabricating method thereof. More particularly, the present invention relates to a circuit substrate with a pad and a conductive block formed in one piece with each other and the fabricating method thereof.

2. Description of Related Art

In current semiconductor package technology, a circuit substrate is one of the most frequently used components. A conventional circuit substrate is mainly composed of a plurality of patterned conductive layers and a plurality of dielectric layers alternately stacked to one another. In addition, the patterned conductive layers are electrically connected through a plurality of conductive vias. As the integration of traces in the circuit substrate increases, how to utilize the limited space of circuit substrate effectively in circuit layout has become an important subject.

SUMMARY OF THE INVENTION

The present invention provides a method comprising following steps for fabricating a circuit substrate. A base layer, a patterned conductive layer, a dielectric layer and a covering layer are provided, wherein the patterned conductive layer having an inner pad is disposed on the base layer, the dielectric layer is disposed on the base layer and covers the patterned conductive layer, and the covering layer is disposed on the dielectric layer. A part of the covering layer is removed by dry etching to form a first opening. A part of the dielectric layer exposed by the first opening is removed to form a dielectric opening exposing a part of the inner pad. A patterned mask having a second opening to expose a part of the inner pad is formed on the covering layer. A conductive structure including a conductive block filling the dielectric opening, an outer pad filling the first opening and a surplus layer filling the second layer is provided, wherein the conductive block, the outer pad and the surplus layer are formed in one piece together. Then, the patterned mask, the surplus layer and the covering layer are removed.

The present invention further provides a circuit substrate including a base layer, a patterned conductive layer, a dielectric layer and a conductive block. The patterned conductive layer having an inner pad is disposed on the base layer. The dielectric layer is disposed on the base layer and the dielectric layer covers the patterned conductive layer. The conductive block penetrates the dielectric layer, and the conductive block is substantially coplanar with the dielectric layer and connected the inner pad.

DESCRIPTION OF EMBODIMENTS

FIGS. 1A through 1Iare cross-sectional views showing a process of fabricating a circuit substrate according to an embodiment of the present invention. First, as shown inFIG. 1A, a base layer110, a patterned conductive layer120, a dielectric layer130and a covering layer150are provided. The base layer110may be a circuit layer of a chip, a circuit layer of a chip carrier, or a circuit layer of a printed circuit board. The patterned conductive layer120is disposed in the base layer110and the patterned conductive layer120has an inner pad122. The dielectric layer130is disposed on the base layer110and the dielectric layer130covers the patterned conductive layer120. The covering layer150is disposed on the dielectric layer130. The material of the covering layer150may be nonmetal such as organic material or may be metal used as a barrier. Particularly, in an embodiment, the covering layer150is made of the material capable of being peeled from the dielectric layer130.

In the present embodiment, the dielectric layer130can be made of resin, and the dielectric layer130and the covering layer150thereon are laminated with the base layer110and the patterned conductive layer120, such that the dielectric layer130is located between the base layer110and the covering layer150and covers the patterned conductive layer120. In other words, in the present embodiment, a double layered structure comprising the dielectric layer130and the covering layer150is provided and laminated with the base layer110and the patterned conductive layer120thereon. For the fabrication process of the present invention, the double layered structure including the dielectric layer130and the covering layer150facilitates simplifying the fabricating process. In another embodiment, the dielectric layer130and the covering layer150can be formed on the base layer110in sequence to cover the patterned conductive layer120.

Referring toFIG. 1B, a part of the covering layer150is removed by dry etching to form a first opening152. In the present embodiment, the material of the covering layer150is nonmetal, and the dry etching for removing the part of the covering layer150may be laser ablation or plasma etching. In another embodiment, if the material of the covering layer150is metal, patterning process including photolithography and etching is adopted to faun the first opening152rather than laser ablation. Comparing with the patterning process, the dry etching (especially laser ablation) requires less processing time in forming the first opening152.

Then, referring toFIG. 1Bagain, a part of the dielectric layer130exposed by the first opening152is removed to form a dielectric opening132, wherein the dielectric opening132exposes a part of the inner pad122.

In the present embodiment, if the material of the covering layer150is nonmetal, the part of the dielectric layer130exposed by the first opening152can be removed by dry etching. The dry etching used for removing a portion of the dielectric layer130is, for example, laser ablation or plasma etching.

Referring toFIG. 1C, a conductive seed layer140ais formed on the inner wall of the dielectric opening132, the inner wall of the first opening152, and the covering layer150. The material of the conductive seed layer140ais copper, for example.

Referring toFIG. 1D, a patterned mask160having a second opening162to expose the first opening152, the dielectric opening132and a part of the inner pad122is formed on a part of the conductive seed layer140alocated on the covering layer150.

Next, referring toFIG. 1E, a conductive structure140is formed by plating in using the conductive seed layer140afor transmitting current. The material of the conductive structure140is copper, for example. The conductive structure140includes a conductive block142filling the dielectric opening132and covering a part of the inner pad122, an outer pad144filling the first opening152, and a surplus layer146filling the second opening162. The conductive block142, the outer pad144and the surplus layer146are formed by plating to provide an integrative structure.

Referring toFIG. 1G, the surplus layer146and the part of the conductive seed layer140alocated on the covering layer150are removed. In the present embodiment, the surplus layer146and the part of the conductive seed layer140alocated on the covering layer150can be removed by grinding, polishing or etching.

Referring toFIG. 1H, the covering layer150is removed. In the present embodiment, the covering layer150can be peeled from the dielectric layer130after weakening the bonding between the covering layer150and the dielectric layer130. It is noted that the outer pad144is exposed after removing the covering layer150to be connected with a chip or a package. In addition, the thickness of the outer pad144is related to the covering layer150; namely, the thickness of the outer pad144can be controlled by adjusting the thickness of the covering layer150.

Referring toFIG. 1I, a surface passivation layer170may further be formed on the outer pad144and a part of the conductive seed layer140a. The material of the surface passivation layer170may comprises Ni/Au stacked layer, Ni/Pd/Au stacked layer, Ni/Sn stacked layer, Pd, Au or the alloy thereof, or the surface passivation layer170may be an organic solderability preservation (OSP).

FIG. 2is a perspective view showing the inner pad and the conductive block ofFIG. 1. Referring toFIGS. 1I and 2, the outer diameter of the inner pad122is greater than that of the conductive block142. In addition, the patterned conductive layer120further has an inner trace124, wherein the inner pad122is formed of an end portion of the inner trace124, and the outer diameter of the inner pad122is greater than a line width of the inner trace124. In the present embodiment, the inner trace124may be served as a signal trace, a grounding trace or a power trace.

FIG. 3is a cross-sectional view showing a final step of a process of fabricating a circuit substrate according to another embodiment of the present invention.FIG. 4is a perspective view showing the inner pad and the conductive block ofFIG. 3. Referring toFIGS. 3 and 4, the present embodiment is similar to the above embodiment shown inFIGS. 1A through 1Iexcept that an outer diameter of the inner pad122is smaller than an outer diameter of the conductive block142such that the conductive block142encompasses the inner pad122. In addition, the patterned conductive layer120further has an inner trace124, wherein the inner pad122is formed of an end portion of the inner trace124, and the outer diameter of the inner pad122is substantially equal to a line width of the inner trace124.

FIGS. 5A and 5Bare cross-sectional views showing final two steps of a process of fabricating a circuit substrate according to another embodiment of the present invention. Referring toFIG. 5A, following the steps as shown inFIGS. 1A through 1H, the outer pad144and a part of the conductive seed layer140aare removed such that the conductive block142is substantially coplanar with the dielectric layer130and connected with a part of the inner pad122via the conductive seed layer140a. Referring toFIG. 5B, finally, a surface passivation layer170may be formed on the outer pad142and a part of the conductive seed layer140a.

FIG. 6is a cross-sectional view showing a final step of a process of fabricating a circuit substrate according to another embodiment of the present invention. Referring toFIG. 6, the present embodiment is similar to the above embodiment shown inFIG. 5Bexcept that an outer diameter of the inner pad122is smaller than an outer diameter of the conductive block142such that the conductive block142encompasses the inner pad122.FIG. 4shows the same concept.

FIG. 7is a cross-sectional view showing a final step of a process of fabricating a circuit substrate according to another embodiment of the present invention. Being different from the aforementioned embodiment ofFIG. 1I, the present embodiment increases the inner diameter of the first opening152by performing another etching process to broaden the first opening152after forming the first opening152and the dielectric opening132inFIG. 1B, such that the outer diameter of the outer pad144later formed inFIGS. 1C through 1Eis greater than that of the conductive block142.

FIG. 8is a cross-sectional view showing a final step of a process of fabricating a circuit substrate according to another embodiment of the present invention. Referring toFIG. 8, the present embodiment is similar to the above embodiment shown inFIG. 7except that an outer diameter of the inner pad122is smaller than an outer diameter of the conductive block142such that the conductive block142encompasses the inner pad122.FIG. 4shows the same concept.

In summary, the present invention forms an opening in the covering layer by dry etching so as to reduce the processing time and facilitate the formation of the outer pad. In addition, the thickness of the outer pad can be precisely controlled through the covering layer. The conductive block and the outer pad are formed in one piece, such that misalignment between the outer pad and the conductive block during plural patterning steps of the conventional process can be prevented. Furthermore, the conductive block embedded in the dielectric layer can replace the outer pad to serve as an electrode of the circuit substrate.