Semiconductor memory device having auxiliary conduction region of reduced area

A semiconductor memory device includes a semiconductor substrate; a plurality of word lines provided on the semiconductor substrate and arranged in parallel to each other; a plurality of memory cells provided along each of the plurality of word lines; a plurality of sub bit lines provided on the semiconductor substrate and arranged in parallel to each other, each of the plurality of word line intersecting the plurality of sub bit lines; a plurality of main bit lines arranged in parallel to the plurality of sub bit lines; a plurality of bank select lines arranged in parallel to the plurality of word lines; a plurality of bank select transistors provided along each of the plurality of bank select lines and connected to the respective sub bit lines; and a plurality of auxiliary conduction regions provided for each of the plurality of the main bit lines, connecting each of the plurality of the main bit lines to a set of the plurality of bank select transistors of the plurality of sub bit lines. The shape of the plurality of bank select transistors is the same. Each of the plurality of auxiliary conduction regions has a modified-H shape including a central portion connected to each of the plurality of main bit lines and branch portions each connected to a corresponding one of the set of the plurality of bank select transistors of the plurality of sub bit lines.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with a hierarchical bit line architecture having main and sub bit lines.

2. Description of the Related Art

Mask Read Only Memory (MROM) is a conventional semiconductor memory device which adopts a hierarchical bit line architecture. MROM includes a memory cell structure having two transistors (MOSFET) with different level threshold levels so as to store a binary digit. One of the two transistors has a low threshold level, i.e., a low voltage applied to the gate electrode can cause a sufficient current to flow through the transistor. The other has a high threshold level such that only a sufficiently high voltage applied to the gate electrode allows the current flow. The use of two transistors having low and high threshold levels, respectively, can realize the binary memory. The hierarchical bit line architecture is used to read the value of the binary digit stored in the corresponding transistor, and to integrate the memory cells in high density.

FIG. 2 is a circuit diagram representing an MROM with a hierarchical bit line architecture. As shown in FIG. 2 , main bit lines MB 1 , MB 2 , . . . , etc. and sub bit lines SB 1 , SB 2 , . . . , etc. are arranged in a hierarchical structure. For example, the main bit line MB 1 is disposed between the odd-numbered sub bit line SB 1 and the even-numbered sub bit line SB 2 . One of memory cells M 1 , M 2 , . . . , etc., which includes a transistor, is disposed each between the adjacent two sub bit lines. The source of each of the memory cells M 1 , M 2 , . . . , etc. is connected to one of the adjacent two sub bit lines and the drain is connected to the other. The gates of the memory cells are connected to word lines WL 0 , . . . , WLn. The main bit lines MB 1 , MB 2 , . . . etc. are connected to sense circuits SA 1 , SA 2 , . . . , etc., respectively, and a charging circuit Ca, or are otherwise connected via transistors (MOSFET) Q 1 , Q 2 , . . . , etc. to GND. Each odd-numbered sub bit line is connected via a bank select transistor (MOSFET) BK 1 or BK 2 to a main bit line. The gates of the bank select transistors (MOSFET) BK 1 and BK 2 are connected to bank select lines BKL 1 and BKL 2 , respectively. Each even-numbered sub bit line is connected via a bank select transistor (MOSFET) BK 3 or BK 4 to a main bit line. The gates of the bank select transistors BK 3 and BK 4 are connected to bank select lines BKL 3 and BKL 4 , respectively.

In order to read the value of the memory cell M 4 , for example, the bank select line BKL 1 is activated so that the bank select transistor BK 1 is switched ON while the bank select line BKL 3 is activated so that the bank select transistor BK 3 is switched ON. This leads to formation of a current path from the charging circuit Ca to the main bit line MB 1 to the bank select transistor BK 1 to the sub bit line SB 3 . When the threshold of the memory cell M 4 is set to a low value, the activated word line WL 0 switches ON the memory cell M 4 . This allows a current to flow from the sub bit line SB 3 , to the memory cell M 4 , to the sub bit line SB 4 , to the bank select transistor BK 3 , to the main bit line MB 2 , to the transistor Q 1 , to GND. On the other hand, when the threshold of the memory cell M 4 is set to a high value, the activated word line WL 0 leaves the memory cell M 4 OFF. This does not allow a current to flow in the above-described path. The sense circuit SA 1 reads the binary digit stored in the memory cell M 4 by determining whether a current flows through the path or not.

FIG. 3 is a diagram illustrating a layout design of the semiconductor substrate on which the MROM shown in FIG. 2 is provided.

In FIG. 3 , a channel region Ch is provided in each of the bank select transistors BK 1 , BK 2 , . . . , etc. An auxiliary conduction region (diffusion region) H is connected via each of the bank select transistors BK 1 , BK 2 , . . . , etc. to each of the sub bit lines SB 1 , SB 2 , . . . , etc. Each of the bank select transistors BK 1 , BK 2 , . . . , etc. is connected via a contact hole CC of the corresponding auxiliary conduction region H to each of the main bit lines MB 1 , MB 2 , . . . , etc. The word lines WL 0 , . . . , WLn intersect the sub bit lines SB 1 , SB 2 , . . . , etc.

The main bit lines MB 1 , MB 2 , . . . , etc. are made of a low resistance material such as metal. The sub bit lines SB 1 , SB 2 , . . . , etc. are formed of a diffusion layer which enables formation of the source and drain of a transistor. Each memory cell uses two adjacent sub bit lines as a source electrode and a drain electrode, respectively, and one of the word lines WL 0 , . . . , WLn as a gate electrode in a way shown in FIG. 3 .

Here the bank select transistors BK 1 , BK 2 , etc. each have channel region Ch having a large width w 2 . The large-width channel regions Ch increase current flowing from the charging circuit to the memory cells M 1 , M 2 , . . . , etc. to GND, and the increased current can improve the performance of the bank select transistors BK 1 , BK 2 , . . . , etc. This leads to high-speed reading of data from the memory cells M 1 , M 2 , . . . , etc.

As shown in FIG. 3 , the channel regions Ch of two adjacent bank select line s BK 1 , BK 2 , . . . , etc. face each other. For example, the channel region Ch of the bank select line BK 1 faces the channel region Ch of the bank select line BK 2 . The channel region Ch of the bank select line BK 3 faces the channel region Ch of the bank select line BK 4 . The width b between the bank select transistors, e.g. , between BK 1 and BK 2 or between BK 3 and BK 4 , is required to sufficiently isolate the bank selects transistors. The sufficient width b leads to an increase in the width a of a memory array, resulting in a large-sized chip.

To solve such a problem, Japanese Laid-Open Publication No. 6-104406 discloses an MROM which has a circuit structure and layout design as shown in FIGS. 4 and 5 , respectively. Like numeral references refer to like parts in FIGS. 2 through 5 .

As is apparent from FIG. 4 , bank select transistors BK 2 - 1 and BK 2 - 2 are connected to each other in parallel and bank select transistors BK 3 - 1 and BK 3 - 2 are connected to each other in parallel. Each of the bank select transistors BK 2 - 1 and BK 2 - 2 has the same current supply performance (current amount per unit area) as that of the bank select transistor BK 2 shown in FIG. 2 . Each of the bank select transistors BK 3 - 1 and BK 3 - 2 has the same current supply performance as that of the bank select transistor BK 3 shown in FIG. 2 .

As is apparent from FIG. 5 , the auxiliary conduction regions H (diffusion region) each have an H-shape. A sub bit line SB 1 is connected to an auxiliary conduction region H via the bank select transistors BK 2 - 1 and BK 2 - 2 . Similarly, sub bit line SB 2 is connected to an auxiliary conduction region H via the bank select transistor BK 4 . Sub bit line SB 3 is connected to an auxiliary conduction region H via the bank select transistor BK 1 . Sub bit line SB 4 is connected to an auxiliary conduction region H via the bank select transistors BK 3 - 1 and BK 3 - 2 . The auxiliary conduction regions H each are connected via a contact hole CC of an insulating layer (not shown) to one of the main bit lines MB 1 , MB 2 , . . . , etc.

Here the width w 1 of the channel region Ch of each of the bank select transistors BK 2 - 1 and BK 2 - 2 and the bank select transistors BK 3 - 1 and BK 3 - 2 is smaller than the width w 2 of the channel region Ch of each of the bank select transistors BK 2 and BK 3 shown in FIG. 3 . This prevents an increase in chip size.

The width W 1 of the channel region Ch of each of the bank select transistors BK 2 - 1 and BK 2 - 2 may be small. However, when the sum of the widths w 1 of the channel regions Ch of the bank select transistors BK 2 - 1 and BK 2 - 2 (i.e., w 1 w 1 ) is equal to the width w 2 of the channel region Ch of the bank select transistor BK 2 shown in FIG. 3 (w 1 w 1 w 2 ), the bank select transistors BK 2 - 1 and BK 2 - 2 provide the same amount of current flow as that of the bank select transistor BK 2 shown in FIG. 3 . The same applies to the relationship between the bank select transistors BK 3 - 1 and BK 3 - 2 and the bank select transistor BK 3 shown in FIG. 3 .

Even when the relationship w 1 w 1 w 2 is satisfied in the layout design shown in FIG. 5 , the relationship does not hold in the actual LSI due to the microstructure. In this case, the bank select transistors BK 2 - 1 and BK 2 - 2 shown in FIG. 4 do not have the same current supply performance as that of the bank select transistor BK 2 shown in FIG. 3 . The bank select transistors BK 3 - 1 and BK 3 - 2 shown in FIG. 4 do not have the same current supply performance as that of the bank select transistor BK 3 shown in FIG. 2 . This is because the effective width of the channel region Ch of a bank select transistor is smaller in the actual LSI than in the layout design. In other words, the width of the channel region Ch of the bank select transistor in the layout design includes an ineffective width which does not function as the channel region Ch. This ineffective width does not depend on the gate width when the gate length is constant.

FIG. 6 shows a channel region Ch of a bank select transistor between two sub bit lines SB. FIG. 6 also shows the relationship between the width w 1 of the channel region Ch in a layout design and the effective and ineffective widths w 6 and w 4 of the channel region Ch in the actual LSI (w 6 w 1 2 w 4 ).

Taking the relationship into consideration, the sum W eff0 of the effective widths of the channel region ch of the bank select transistors BK 2 - 1 and BK 2 - 2 is represented by the following equation: W eff0 (w 1 2 w 4 ) (w 1 2 w 4 ) 2 w 1 4 w 4 . The effective width W eff0 of the channel region Ch of the bank select transistor BK 2 shown in FIG. 3 is represented by the following equation: W eff1 w 2 2 w 4 2 w 1 2 w 4 where w 2 is the width of the channel region Ch of the bank select transistor BK 2 in the layout design ( 2 w 1 ). Since the ineffective width w 4 is constant as described above, the sum W eff0 of the effective widths of the channel region oh of the bank select transistors BK 2 - 1 and BK 2 - 2 shown in FIG. 5 is smaller than the effective width W eff1 of the channel region Ch of the bank select transistor BK 2 shown in FIG. 3 . Moreover, the value (w 1 w 1 w 2 ) defined in the layout design often does not hold in the actual LSI due to variations in the width w 1 . For these reasons, the combinations of the bank transistors BK 2 - 1 and BK 2 - 2 as well as BK 3 - 1 and BK 3 - 2 have reduced current supply performance.

The width w 1 of the channel region Ch in the layout design can be defined to allow for the ineffective width w 4 . The ineffective width w 4 varies depending on the manufacturing conditions of the actual LSI, so that it is difficult to control the effective width w 6 . Variations in the bank select transistors cause the reading speed of the memory cell to vary among the bank select transistors through which the value in a memory cell is read out. For this reason, a stable and fast reading cannot be established.

Furthermore, the auxiliary conduction region H has a parasitic capacitance. As is apparent from the layout design shown in FIG. 5 , the auxiliary conduction region H is H-shaped. The large area of the auxiliary conduction region H leads to an increase in the parasitic capacitance of the main bit line. This results in the slow speed at which the memory cell value is read out.

SUMMARY OF THE INVENTION

According to one aspect of the present invention, a semiconductor memory device includes a semiconductor substrate; a plurality of word lines provided on the semiconductor substrate and arranged in parallel to each other; a plurality of memory cells provided along each of the plurality of word lines; a plurality of sub bit lines provided on the semiconductor substrate and arranged in parallel to each other, each of the plurality of word line intersecting the plurality of sub bit lines; a plurality of main bit lines arranged in parallel to the plurality of sub bit lines; a plurality of bank select lines arranged in parallel to the plurality of word lines; a plurality of bank select transistors provided along each of the plurality of bank select lines and connected to the respective sub bit lines; and a plurality of auxiliary conduction regions provided for each of the plurality of the main bit lines, connecting each of the plurality of the main bit lines to a set of the plurality of bank select transistors of the plurality of sub bit lines. The shape of the plurality of bank select transistors is the same. Each of the plurality of auxiliary conduction regions has a modified-H shape including a central portion connected to each of the plurality of main bit lines and branch portions each connected to a corresponding one of the set of the plurality of bank select transistors of the plurality of sub bit lines.

In one embodiment of this invention, each of the plurality of auxiliary conduction regions has four branch portions and has a modified-H shape.

In one embodiment of this invention, two of the four branch portions are smaller than the others.

In one embodiment of this invention, the semiconductor substrate is of a first conductivity type and the plurality of sub bit lines are a second conductivity type diffusion layer.

In one embodiment of this invention, each of the plurality of memory cells has one of the plurality of sub bit lines as a source and a drain and one of the plurality of word lines as a gate electrode.

In one embodiment of this invention, each of the plurality of main bit lines is made of a low resistance metal material.

According to another aspect of the present invention, a semiconductor memory device includes a semiconductor substrate; a plurality of word lines provided on the semiconductor substrate and arranged in parallel to each other; a plurality of memory cells provided along each of the plurality of word lines; a plurality of sub bit lines provided on the semiconductor substrate and arranged in parallel to each other, each of the plurality of word line intersecting the plurality of sub bit lines; a plurality of main bit lines arranged in parallel to the plurality of sub bit lines; a plurality of bank select lines arranged in parallel to the plurality of word lines; a plurality of bank select transistors provided along each of the plurality of bank select lines and connected to the respective sub bit lines; and a plurality of auxiliary conduction regions provided for each of the plurality of the main bit lines, connecting each of the plurality of the main bit lines to a set of the plurality of sub bit lines. The plurality of bank select transistors provided along one of the plurality of bank select lines and the plurality of bank select transistors provided along another of the plurality of bank select lines adjacent to the one of the plurality of bank select lines are alternately arranged and protrude inwardly between the one and another of the plurality of word lines.

In one embodiment of this invention, the semiconductor substrate is of a first conductivity type and the plurality of sub bit lines are a second conductivity type diffusion layer.

In one embodiment of this invention, each of the plurality of memory cells has one of the plurality of sub bit lines as a source and a drain and one of the plurality of word lines as a gate electrode.

In one embodiment of this invention, each of the plurality of main bit lines is made of a low resistance metal material.

Thus, the invention described herein makes possible the advantage of providing a semiconductor memory device providing stable high-speed reading without an increase in chip size.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a layout design of a semiconductor memory device according to an example of the present invention. The semiconductor memory device is an MROM having a hierarchical bit line architecture. FIG. 2 discussed above, also represents a circuit diagram of the semiconductor memory device according to the present invention.

An auxiliary conduction region (diffusion region) H is modified-H- shaped and has a central portion Ha which is connected via a contact hole CC to one of the main bit lines MB 1 , MB 2 , . . . , etc. and a branch portion Hb which is connected to one of the bank select transistors BK 1 , BK 2 , BK 3 , BK 4 , . . . , etc. Thus, the bank select transistors BK 1 , BK 2 , BK 3 , BK 4 , . . . , etc. are connected via the auxiliary conduction region (diffusion region H) to the corresponding main bit line.

A semiconductor substrate of the semiconductor memory device is of a first conductive type (e.g., p-type or p-well). The sub bit lines SB 1 , SB 2 , . . . , etc. are formed of a diffusion layer of a second conductivity type (e.g., n-type) which enables formation of the source and drain of a transistor. The memory cells M 1 , M 2 , . . . , etc. each use two adjacent sub bit lines SB 1 , SB 2 , . . . , etc. as a source and a drain, and one of the word lines WL 0 , . . . , WLn as a gate electrode. The main bit lines MB 1 , MB 2 , etc. are formed of a low resistance material such as metal.

The bank select transistor BK 1 of the bank select line BKL 1 and the bank select transistor BK 2 of the bank select line BKL 2 are alternately arranged in such a manner that the channel regions Ch of the bank select transistors BK 1 and BK 2 protrude inwardly between the bank select lines BKL 1 and BKL 2 . Similarly, the bank select transistor BK 3 of the bank select line BKL 3 and the bank select transistor BK 4 of the bank select line BKL 4 are alternately arranged in such a manner that the channel regions Ch of the bank select transistors BK 3 and BK 4 protrude inwardly between the bank select lines BKL 3 and BKL 4 .

In such a layout design, the width w 2 of the channel region Ch of each of the bank select transistors BK 1 , BK 2 , BK 3 , BK 4 , . . . , etc. is large while the bank select lines BKL 1 and BKL 2 are arranged close to each other and the bank select lines BKL 3 and BKL 4 are arranged close to each other. This arrangement prevents an increase in chip size while the current supply performance of the bank select transistors BK 1 , BK 2 , BK 3 , and BK 4 is not degraded and the speed of reading data from the memory cell is not lowered. Moreover, the bank select transistors BK 1 , BK 2 , BK 3 , BK 4 , . . . , etc. have the same shape and size. Therefore, the speed of reading data from the memory cell is the same regardless of through which bank select transistor the data is transferred. Stable high-speed reading can be obtained.

Each auxiliary conduction region H has four branch regions Hb, two of which are shorter than the others. Thus, the area of each auxiliary conduction region H is smaller compared with the auxiliary conduction region H of the conventional semiconductor memory device shown in FIG. 5 . The smaller area of the auxiliary conduction region H has a reduced parasitic capacitance for the corresponding main bit line, resulting in high-speed reading of data from the memory cell.

For instance, when the semiconductor memory device has a configuration such that data is read from four memory cells via one main bit line and one bank includes 32 memory cells, there are 64 modified-H-shaped auxiliary conduction regions H in the device. All the parasitic capacitances of these auxiliary conduction regions H add up as the capacitances of the main bit lines. The capacitances of the main bit lines have adverse influences on the speed of reading data from the memory cells. To avoid this, a small area and short circumference of auxiliary conduction region H is required. The modified-H-shaped auxiliary conduction region H has a small area and a short circumference compared with the auxiliary conduction region H of the conventional conduction region H shown in FIG. 5 , thereby reducing the total capacitance of the main bit lines and thus obtaining high speed reading.

As described above, in the semiconductor memory device of the present invention, an increase in chip size is prevented; the channel widths of the bank select transistors are broad and uniform; and the bank select transistors have large and constant current supply capacitances. Therefore, the semiconductor memory device provides stable high-speed reading.