Package, optical device, and manufacturing method of package

A package includes a photonic integrated circuit die, an electric integrated circuit die, and an encapsulant. The photonic integrated circuit die includes a semiconductor substrate, an insulation layer, and a waveguide. The semiconductor substrate has a notch. The insulation layer is disposed on the semiconductor substrate. The waveguide is disposed on the insulation layer. The notch of the semiconductor substrate is underneath at least a portion of the waveguide. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The encapsulant laterally encapsulates the electric integrated circuit die.

BACKGROUND

Currently, semiconductor structures including both photonic integrated circuit dies (known as P-dies) and electric integrated circuit dies (known as E-dies) are becoming increasingly popular for their compactness. In addition, due to the widely use of optical fiber-related applications for signal transmission, optical signaling and processing have been used in more applications. Although existing methods of fabricating the semiconductor structures have been generally adequate for their intended purposes, they have not been entirely satisfactory in all respects. For example, challenges rise to develop robust process for interconnecting among P-dies, E-dies, and optical fibers.

DETAILED DESCRIPTION

FIG. 1AtoFIG. 1Kare schematic cross-sectional views illustrating a manufacturing process of an optical device OP1in accordance with some embodiments of the disclosure. Referring toFIG. 1A, a semiconductor wafer SW is provided. In some embodiments, the semiconductor wafer SW may be referred to as a “photonic wafer.” For example, the semiconductor wafer SW may include photonic components to process, receive, and/or transmit optical signals. In some embodiments, the semiconductor wafer SW includes a semiconductor substrate110, an insulation layer120, a dielectric layer130, a plurality of waveguides140, an interconnection structure150, and a plurality of through vias160. In some embodiments, the semiconductor substrate110, the insulation layer120, the waveguides140, and the interconnection structure150are stacked in sequential order.

In some embodiments, the semiconductor substrate110has a first surface110aand a second surface110bopposite to the first surface110a. In some embodiments, the semiconductor substrate110may be made of elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenic, gallium phosphide, indium antimonide, indium arsenide, or indium phosphide; or alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. In some embodiments, the semiconductor substrate110may be a bulk semiconductor substrate, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. Alternatively, the semiconductor substrate110may be a multi-layered or gradient substrate. In some embodiments, the semiconductor substrate110has a plurality of semiconductor components (e.g., transistors, capacitors, photodiodes, combinations thereof, or the like) and/or a plurality of optical components (e.g. waveguides, filters, combinations thereof, or the like) formed therein.

In some embodiments, the insulation layer120is disposed on the first surface110aof the semiconductor substrate110. In some embodiments, the insulation layer120may be a buried oxide (BOX) layer, a silicon oxide layer, a silicon nitride layer, a titanium oxide layer, or the like. In some embodiments, the insulation layer120may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin-on process, the like, or a combination thereof. It should be noted that the insulation layer120may be optional. For example, the insulation layer120may be omitted in some embodiments.

As illustrated inFIG. 1A, the waveguides140are disposed on the insulation layer120. In some embodiments, the waveguides140may be formed by the following steps. First, a semiconductor layer (not shown) is disposed on the insulation layer120. In some embodiments, the semiconductor substrate110, the insulation layer120, and the semiconductor layer may be collectively referred to as a “semiconductor-on-insulator (SOI) substrate.” A material of the semiconductor layer and the material of the semiconductor substrate110may be the same or may be different from each other. For example, the semiconductor layer may be made of elemental semiconductor materials, such as crystalline silicon, diamond, or germanium; compound semiconductor materials, such as silicon carbide, gallium arsenic, gallium phosphide, indium antimonide, indium arsenide, or indium phosphide; or alloy semiconductor materials, such as silicon germanium, silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. Subsequently, the semiconductor layer may be doped with a p-type or an n-type dopant. Thereafter, the doped semiconductor layer is patterned to form waveguides140. In some embodiments, the waveguides140are able to transmit optical signals entering from a lateral side. For example, the waveguides140may be referred to as “edge couplers.” In some embodiments, the waveguides140have broad bandwidth with small polarization dependent loss. In some embodiments, a thickness t140of the waveguides140ranges from about 100 nm to about 150 nm.

In some embodiments, the dielectric layer130is disposed on the insulation layer120to laterally cover the waveguides140. For example, the waveguides140are embedded in the dielectric layer130. In some embodiments, the dielectric layer130is made of transparent dielectric material. For example, the dielectric layer130may be formed of silicon oxide, silicon nitride, titanium oxide, the like, or a combination thereof. In some embodiments, the dielectric layer130may be formed by a CVD process, a PVD process, an ALD process, a spin-on process, the like, or a combination thereof.

In some embodiments, the interconnection structure150is formed over the dielectric layer130and the waveguides140. The interconnection structure150includes an inter-dielectric layer152, a plurality of patterned conductive layers154, and a plurality of conductive vias156. For simplicity, the inter-dielectric layer152is illustrated as a bulky layer inFIG. 1A, but it should be understood that the inter-dielectric layer152may be constituted by multiple dielectric layers. The patterned conductive layers154and the dielectric layers of the inter-dielectric layer152are stacked alternately. In some embodiments, the conductive vias156are embedded in the dielectric layers of the inter-dielectric layer152. In some embodiments, two vertically adjacent patterned conductive layers154are electrically connected to each other through conductive vias156. In some embodiments, the interconnection structure150may be electrically connected to the waveguides140and/or the semiconductor substrate110through contact structures (not shown). For example, the interconnection structure150may be electrically connected to the semiconductor components and/or the optical components formed in the semiconductor substrate110.

In some embodiments, the inter-dielectric layer152may be formed of silicon oxide, silicon oxynitride, silicon nitride, or low-k dielectric materials having k values lower than about 3.0. The low-k dielectric materials may include Black Diamond (a registered trademark of Applied Materials), a carbon-containing low-k dielectric material, Hydrogen SilsesQuioxane (HSQ), MethylSilsesQuioxane (MSQ), or the like. Etch stop layers (not shown) may be formed to separate neighboring dielectric layers within the inter-dielectric layer152. In some embodiments, the etch stop layers are formed of a material having a high etching selectivity relative to the dielectric layers of the inter-dielectric layer152. For example, the etch stop layers may be formed of silicon carbide, silicon carbo-nitride, or the like. The inter-dielectric layer152may be formed by suitable fabrication techniques such as spin-on coating, CVD, plasma-enhanced chemical vapor deposition (PECVD), or the like. In some embodiments, a material of the patterned conductive layers154and a material of the conductive vias156include aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. The patterned conductive layers154and the conductive vias156may be formed by, for example, electroplating, deposition, and/or photolithography and etching. In some embodiments, the patterned conductive layers154and the underlying conductive vias156are simultaneously formed. For example, the patterned conductive layers154and the underlying conductive vias156may be formed by a dual-damascene process. It should be noted that the number of the dielectric layers in the inter-dielectric layer152, the number of the patterned conductive layers154, and the number of the conductive vias156shown inFIG. 1Aare merely exemplary illustrations, and the disclosure is not limited. In some alternative embodiments, the number of the dielectric layers in the inter-dielectric layer152, the number of the patterned conductive layers154, and the number of the conductive vias156may be adjusted depending on the routing requirements.

As illustrate inFIG. 1A, the semiconductor wafer SW further includes the through vias160embedded in the semiconductor substrate110, the insulation layer120, the dielectric layer130, and the inter-dielectric layer152of the interconnection structure150. It should be noted that the through vias160are illustrated by dotted line to denote that the through vias160are not located on the cross-sectional plane inFIG. 1A. The through vias160may be located on a plane in front of or behind the cross-sectional plane inFIG. 1A. That is, the through vias160are illustrated in a perspective manner. For example, the through vias160do not penetrate through the waveguides140. In some embodiments, the through vias160may be referred to as “through semiconductor vias.” As illustrated inFIG. 1A, the through vias160extend vertically from the interconnection structure150to the semiconductor substrate110. In some embodiments, the through vias160are formed of a conductive material. For example, the through vias160may include a metallic material, such as tungsten, copper, titanium, aluminum, nickel, alloys thereof, or the like. At this stage, the through vias116may not be accessibly exposed by the semiconductor substrate110.

At this stage, a top surface of the interconnection structure150and top surfaces of the through vias160are collectively referred to as a first surface SWa of the semiconductor wafer SW. On the other hand, the second surface110bof the semiconductor substrate110may be referred to as a second surface SWb of the semiconductor wafer SW. As illustrated inFIG. 1A, the second surface SWb of the semiconductor wafer SW is opposite to the first surface SWa of the semiconductor wafer SW. In some embodiments, the top surface of the interconnection structure150and the top surfaces of the through vias160are substantially levelled to provide an appropriate first surface SWa for bonding.

Referring toFIG. 1B, a plurality of electric integrated circuit dies200is bonded to the semiconductor wafer SW. In some embodiments, the electric integrated circuit dies200may be logic IC dies, memory dies, analog IC dies, application-specific IC (ASIC) dies, or the like. In some alternative embodiments, each of the electric integrated circuit dies200is a package structure of which a plurality of die components is encapsulated in a packaging encapsulation (e.g., molding compound; not shown). In some embodiments, each electric integrated circuit die200includes a semiconductor substrate210, a device layer200, and an interconnection structure230.

In some embodiments, the semiconductor substrate210of the electric integrated circuit die200is similar to the semiconductor substrate110of the semiconductor wafer SW, so the detailed description thereof is omitted herein. In some embodiments, the device layer220is formed over the semiconductor substrate210. In some embodiments, the device layer220includes a plurality of active devices and/or passive devices formed therein. Examples of the active devices include, but are not limited to, diodes, field effect transistors (FETs), metal-oxide-semiconductor FETs (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar transistors, or the like. On the other hand, examples of the passive devices include, but are not limited to, resistors, capacitors, inductors, or the like.

In some embodiments, the interconnection structure230is formed over the device layer220. In some embodiments, the interconnection structure230is electrically coupled to the active devices and/or the passive devices in the device layer220through contact structures (not shown). The interconnection structure230includes an inter-dielectric layer232, a patterned conductive layer234, a plurality of conductive vias236, and a plurality of bonding pads238. The inter-dielectric layer232, the patterned conductive layer234, and the conductive vias236in the interconnection structure230are respectively similar to the inter-dielectric layer152, the patterned conductive layers154, and the conductive vias156in the interconnection structure150, so the detailed descriptions thereof are omitted herein. It should be noted that the number of the dielectric layers in the inter-dielectric layer232, the number of the patterned conductive layer234, and the number of the conductive vias236shown inFIG. 1Bare merely exemplary illustrations, and the disclosure is not limited. In some alternative embodiments, the number of the dielectric layers in the inter-dielectric layer232, the number of the patterned conductive layer234, and the number of the conductive vias236may be adjusted depending on the routing requirements. For example, when more than one layer of the patterned conductive layer234are presented, these patterned conductive layers234may be electrically connected to each other through the conductive vias236located between the two. As illustrated inFIG. 1B, the bonding pads238are embedded in the inter-dielectric layer232. In some embodiments, the bonding pads238are connected to the patterned conductive layer234through the conductive vias236. That is, the bonding pads238are electrically coupled to the active devices and/or the passive devices in the device layer220through the conductive vias236and the patterned conductive layer234. In some embodiments, a material of the bonding pads238may be the same or may be different from the material of the patterned conductive layer234and the conductive vias236. For example, the material of the bonding pads238may include a metallic material, such as tungsten, copper, titanium, aluminum, nickel, alloys thereof, or the like.

In some embodiments, a bottom surface of the inter-dielectric layer232and bottom surfaces of the bonding pads238shown inFIG. 1Bare collectively referred to as a first surface200aof the electric integrated circuit die200. On the other hand, a top surface of the semiconductor substrate210shown inFIG. 1Bmay be referred to as a second surface200bof the electric integrated circuit die200. As illustrated inFIG. 1B, the second surface200bof the electric integrated circuit die200is opposite to the first surface200aof the electric integrated circuit die200. In some embodiments, the bottom surface of the inter-dielectric layer232and the bottom surfaces of the bonding pads238are substantially levelled to provide an appropriate first surface200afor bonding.

In some embodiments, the electric integrated circuit dies200are distributed in an array on the semiconductor wafer SW. As illustrated inFIG. 1B, the electric integrated circuit dies200are bonded to the semiconductor wafer SW in a face-to-face manner. For example, the electric integrated circuit dies200are picked-and-placed onto the semiconductor wafer SW in a face down manner. That is, the first surface200aof each electric integrated circuit die200is attached to the first surface SWa of the semiconductor wafer SW. The bonding between the electric integrated circuit dies200and the semiconductor wafer SW may include hybrid bonding, fusion bonding, direct bonding, dielectric bonding, metal bonding, solder joints (e.g., micro-bumps), or the like. In some embodiments, the interconnection structure230of the electric integrated circuit die200is bonded to the interconnection structure150of the semiconductor wafer SW. For example, the bonding pads238of the electric integrated circuit die200are bonded to the through vias160exposed by the interconnection structure150of the semiconductor wafer SW. As such, the through vias160of the semiconductor wafer SW are electrically connected to the electric integrated circuit dies200. Although not illustrated, the bonding pads238of the electric integrated circuit die200may also be bonded to the topmost patterned conductive layer154of the interconnection structure150of the semiconductor wafer SW. In some embodiments, the bottom surface of the inter-dielectric layer232of the electric integrated circuit die200may be bonded to the top surface of the inter-dielectric layer152of the semiconductor wafer SW through dielectric bonding.

As illustrated inFIG. 1B, each of the electric integrated circuit dies200may correspond to one of the waveguides140in the semiconductor wafer SW. For example, the bonding area of the respective electric integrated circuit die200overlaps with the area occupied by one of the waveguide140from a top view. However, the disclosure is not limited thereto. In some alternative embodiments, each of the electric integrated circuit dies200may correspond to multiple waveguides140.

In some embodiments, since the electric integrated circuit dies200are bonded to the semiconductor wafer SW to render electrical/optical connection with the semiconductor wafer SW, the electric integrated circuit dies200are able to process the electrical signals converted from optical signals generated by the optical components in the semiconductor wafer SW.

Referring toFIG. 1C, an encapsulant300is formed on the semiconductor wafer SW to laterally encapsulate the electric integrated circuit dies200. In some embodiments, the encapsulant300fills a gap between two adjacent electric integrated circuit dies200. In some embodiments, a material of the encapsulant300includes silicon oxide, silicon nitride, silicon carbide, fluoride-doped silicate glass (FSG), low-k dielectric, or the like. However, the disclosure is not limited thereto. In some alternative embodiments, the material of the encapsulant300includes a molding compound, a polymeric material, such as polyimide, epoxy resin, acrylic resin, phenol resin, BCB, PBO, a combination thereof, or other suitable polymer-based dielectric materials. In some embodiments, the encapsulant300further includes fillers. Alternatively, the encapsulant300may be free of fillers.

In some embodiments, the encapsulant300may be formed by the following steps. First, an encapsulation material (not shown) is formed over the semiconductor wafer SW to encapsulate the electric integrated circuit dies200. At this stage, the semiconductor substrates210of the electric integrated circuit dies200are not revealed and are well protected by the encapsulation material. In some embodiments, the encapsulation material may be formed by a molding process (such as a compression molding process), a spin-coating process, a CVD process, a PECVD process, an ALD process, or the like. After the encapsulation material is formed, the encapsulation material is thinned until the semiconductor substrates210of the electric integrated circuit dies200are exposed. For example, the encapsulation material is thinned until the second surfaces200bof the electric integrated circuit dies200are exposed. In some embodiments, the semiconductor substrates210and the encapsulation material are further thinned to reduce the overall thickness of the electric integrated circuit dies200. In some embodiments, the encapsulation material and the semiconductor substrates210may be thinned or planarized through a grinding process, such as a mechanical grinding process, a chemical mechanical polishing (CMP) process, or the like. After the thinning process, each electric integrated circuit die200has a thinned semiconductor substrate210and the encapsulant300is formed to expose the semiconductor substrate210. That is, the second surfaces200bof the electric integrated circuit dies200are substantially coplanar with a top surface300aof the encapsulant300. In some embodiments, the encapsulant300may be referred to as “gap fill oxide.” It should be noted that the foregoing process merely serves as an exemplary illustration, and the disclosure is not limited thereto. In some alternative embodiments, the encapsulant300may be formed after the semiconductor substrates210are thinned.

Referring toFIG. 1D, a bonding layer400and a supporting substrate500are formed over the second surface200bof the electric integrated circuit die200and the top surface300aof the encapsulant300. In some embodiments, the bonding layer400is a smooth layer having a continuous even surface and overlaid on the electric integrated circuit dies200and the encapsulant300. In some embodiments, a material of the bonding layer400may include silicon oxynitride (SiON), silicon oxide, silicon nitride or the like, and the bonding layer400may be formed by deposition or the like. In some embodiments, the bonding layer400has a substantially uniform and even thickness.

In some embodiments, the supporting substrate500is bonded to the bonding layer400. In some embodiments, the supporting substrate500includes semiconductor materials. For example, the supporting substrate500may be made of a suitable elemental semiconductor, such as crystalline silicon, diamond, or germanium; a suitable compound semiconductor, such as gallium arsenide, silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide. However, the disclosure is not limited thereto. In some alternative embodiments, the supporting substrate500may be a glass substrate. In some embodiments, the supporting substrate500is free of active components and passive components. In some embodiments, the supporting substrate500is also free of wire routings. For example, the supporting substrate500may be a blank substrate which purely functions as a supporting element without serving any signal transmission function.

In some embodiments, the supporting substrate500is bonded to the electric integrated circuit dies200and the encapsulant300through fusion bonding. The fusion bonding process may include a hydrophilic fusion bonding process, where a workable temperature is approximately greater than or substantially equal to about 100° C. and a workable pressure is approximately greater than or substantially equal to about 1 kg/cm2. In some embodiments, the fusion bonding process does not involve metal to metal bonding. In some embodiments, since the supporting substrate500is in wafer form, the process illustrated inFIG. 1Dmay be referred to as “wafer-to-wafer bonding.” It should be noted that in some embodiments, the bonding layer400and the supporting substrate500may be optional. In other words, the step illustrated inFIG. 1Dmay be skipped.

Referring toFIG. 1E, the structure illustrated inFIG. 1Dis flipped upside down. Thereafter, a thickness of the semiconductor substrate110is reduced until the through vias160are accessibly revealed by the thinned semiconductor substrate110for further electrical connection. In some embodiments, the thinning process includes a CMP process, a mechanical grinding process, or the like. As illustrated inFIG. 1E, the semiconductor substrate110is thinned from the second surface110buntil the through vias160are exposed. In some embodiments, after the through vias160are exposed, the semiconductor substrate110and the through vias160may be further thinned slightly to reduce the overall thickness of the semiconductor substrate110. In some embodiments, surfaces160aof the through vias160and the second surface110bof the thinned semiconductor substrate110are substantially leveled. At this stage, the surfaces160aof the through vias160and the second surface110bof the semiconductor substrate110may be collectively referred to as the second surface SWb of the semiconductor wafer SW. As illustrated inFIG. 1E, after the thinning process, the through vias160penetrate through the semiconductor substrate110.

Referring toFIG. 1F, a redistribution structure600is formed on the second surface SWb of the semiconductor wafer SW. For example, the redistribution structure600is formed over the semiconductor substrate110opposite to the insulation layer120. In some embodiments, the redistribution structure600includes a dielectric layer602, a plurality of redistribution conductive layers604, and a plurality of conductive vias606. For simplicity, the dielectric layer602is illustrated as a bulky layer inFIG. 1F, but it should be understood that the dielectric layer602may be constituted by multiple dielectric layers. The redistribution conductive layers604and the dielectric layers of the dielectric layer602are stacked alternately. The redistribution conductive layers604are interconnected with one another by conductive vias606embedded in the dielectric layers602. In some embodiments, a material of the redistribution conductive layers604and the conductive vias606includes aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. The redistribution conductive layers604may be formed by, for example, electroplating, deposition, and/or photolithography and etching. In some embodiments, a material of the dielectric layers602includes polyimide, epoxy resin, acrylic resin, phenol resin, benzocyclobutene (BCB), polybenzooxazole (PBO), or other suitable polymer-based dielectric materials. The dielectric layer602, for example, may be formed by suitable fabrication techniques such as spin-on coating, CVD, PECVD, or the like. In some embodiments, the redistribution structure600is formed such that the redistribution conductive layers604are electrically connected to the through vias160of the semiconductor wafer SW.

Referring toFIG. 1G, a portion of the redistribution structure600and a portion of the semiconductor substrate110are removed. In some embodiments, the portion of the redistribution structure600and the portion of the semiconductor substrate110are removed by two distinct steps. For example, the portion of the redistribution structure600is first removed to expose the underlying semiconductor substrate110. Thereafter, the semiconductor substrate110exposed by the redistribution structure600is removed. In some embodiments, the portion of the redistribution structure600and the exposed semiconductor substrate110are removed through two different etching processes. The etching processes include, for example, an anisotropic etching process such as dry etch or an isotropic etching process such as wet etch. In some embodiments, an etchant for the wet etch includes a combination of hydrogen fluoride (HF), copper (Cu), and ammonia (NH3), a combination of HF and TMAH, or the like. On the other hand, the dry etch process includes, for example, reactive ion etch (RIE), inductively coupled plasma (ICP) etch, transformer coupled plasma (TCP) etch, electron cyclotron resonance (ECR) etch, neutral beam etch (NBE), and/or the like. In some embodiments, the portion of the redistribution structure600being removed may be free of the redistribution conductive layers604and the conductive vias606. In other words, the portion of the redistribution structure600being removed only includes the dielectric layer602. However, the disclosure is not limited thereto. In some alternative embodiments, portions of the dielectric layer602, portions of the redistribution conductive layers604, and portions of the conductive vias606may be removed together. Although the portion of the redistribution structure600and the portion of the semiconductor substrate110may be removed by two different process, the disclosure is not limited thereto. In some alternative embodiments, the portion of the redistribution structure600and the portion of the semiconductor substrate110may be removed by one single step (i.e. one single process) depending on the selectivity of the etchant.

In some embodiments, the insulation layer120underneath the semiconductor substrate110may serve as an etch stop layer to prevent the etching process from damaging other components underneath the semiconductor substrate110and the insulation layer120. In some embodiments, the insulation layer120may be slightly etched. Upon removal of portions of the semiconductor substrate110, a plurality of notches N is formed in the semiconductor substrate110. In some embodiments, the notches N have straight sidewalls. However, the disclosure is not limited thereto. In some alternative embodiments, the notches N have curved sidewalls. As illustrated inFIG. 1G, heights HNof the notches N are substantially equal to a thickness t110of the semiconductor substrate110. In other words, the etching process etches through the semiconductor substrate110along a thickness direction, and the notches N penetrate through the semiconductor substrate110. The configurations of the notches N will be discussed below in conjunction withFIG. 2A.

FIG. 2Ais a schematic partial top view of the semiconductor substrate110and the waveguide140inFIG. 1Gin accordance with some embodiments of the disclosure. For simplicity, the redistribution structure600, the insulation layer120, and the through vias160inFIG. 1Gare omitted inFIG. 2A. Referring toFIG. 1GandFIG. 2A, the notch N of the semiconductor substrate110is formed corresponding to at least a portion of the waveguide140. For example, the notch N is formed directly above at least a portion of the waveguide140. In some embodiments, a location of the notch N corresponds to a tip140tof the waveguide140. That is, a projection of the notch N along a direction perpendicular to the first surface110aof the semiconductor substrate110is overlapped with the tip140tof the waveguide140. In some embodiments, from the top view, the tip140tof the waveguide140is located within the boundary of the notch N of the semiconductor substrate110.

As illustrated inFIG. 2A, the notch N exhibits a rectangular shape from the top view. For example, a width WNof the notch N is uniform. In some embodiments, the width WNof the notch N ranges from about 10 μm to about 20 μm. On the other hand, a length LNof the notch N may range from about 100 μm to about 300 μm. In some embodiments, a width of the waveguide140is not uniform. For example, the waveguide140has a smaller width W1401at the tip140t. In some embodiments, a minimum width W1401of the waveguide140at the tip140tis about 50 nm to about 100 nm, and a maximum width W1402of the waveguide140is about 130 nm to about 260 nm. In some embodiments, a length L140tof the tip140tof the waveguide140located within the boundary of the notch N ranges from about 100 μm to about 300 μm. On the other hand, a distance D between an end of the tip140tand a virtual line extending from an edge of the semiconductor substrate110shown inFIG. 2Aranges from about 10 μm to about 2 μm. Moreover, a spacing S between the tip140tof the waveguide140and a sidewall of the notch N ranges from about 5 μm to about 10 μm.

As mentioned above, the waveguides140are able to transmit optical signals entering from the lateral side. When the optical signal is transmitted to the waveguide140from the lateral side, the region above and/or below the tip140tof the waveguide140is preferably to be free of semiconductor material, so as to prevent the semiconductor material from generating optical absorption noise. For example, if semiconductor material exists in the region above and/or below the tip140tof the waveguide140, the semiconductor material would absorb some of the optical signals, thereby causing optical signal loss when entering or transmitting through the waveguide140. In some embodiments, the length LNof the notch N is inversely proportional to the cross-sectional area of the tip140tof the waveguide140. For example, when the cross-sectional area of the tip140tof the waveguide140is very small, it is difficult for the tip140tof the waveguide140to receive optical signals. As such, the length LNof the notch N is required to be longer (i.e. larger region is free of semiconductor material) to compensate for the small optical reception ability of the waveguide140. Referring toFIG. 1GandFIG. 2A, since the notch N is formed above the tip140tof the waveguide140, the region directly above the tip140tof the waveguide140is being occupied by air, and is free of semiconductor material. As such, the noise originated from the semiconductor material (i.e. the semiconductor substrate110) may be eliminated, thereby enhancing the signal accuracy of the optical signals received and transmitted by the waveguide140.

It should be noted that the shape and the dimension of the notch N illustrated inFIG. 2Amerely serve as exemplary illustrations, and the disclosure is not limited thereto. Other configurations of the notch N will be discussed below in conjunction withFIG. 2BandFIG. 2C.

FIG. 2Bis a schematic partial top view of the semiconductor substrate110and the waveguide140inFIG. 1Gin accordance with some alternative embodiments of the disclosure. For simplicity, the redistribution structure600, the insulation layer120, and the through vias160inFIG. 1Gare omitted inFIG. 2B. As illustrated inFIG. 2B, the notch N exhibits a trumpet-like shape from an interior toward an edge of the semiconductor substrate110in the top view. For example, a width of the notch N gradually decreases from an edge of the semiconductor substrate110toward an interior of the semiconductor substrate110. In some embodiments, the notch N has a maximum width WN1of about 15 μm to about 30 μm and a minimum width WN2of about 10 μm to about 20 μm. On the other hand, a length LNof the notch N may range from about 100 μm to about 300 μm. In some embodiments, a width of the waveguide140is not uniform. For example, the waveguide140has a smaller width W1401at the tip140t. In some embodiments, a minimum width W1401of the waveguide140at the tip140tis about 50 nm to about 100 nm, and a maximum width W1402of the waveguide140is about 130 nm to about 260 nm. In some embodiments, a length L140tof the tip140tof the waveguide140located within the boundary of the notch N ranges from about 100 μm to about 300 μm. On the other hand, a distance D between an end of the tip140tand a virtual line extending from an edge of the semiconductor substrate110shown inFIG. 2Branges from about 10 μm to about 2 μm. Moreover, a spacing S between the tip140tof the waveguide140and a sidewall of the notch N ranges from about 5 μm to about 10 μm.

As mentioned above, the waveguides140are able to transmit optical signals entering from the lateral side. When the optical signal is transmitted to the waveguide140from the lateral side, the region above and/or below the tip140tof the waveguide140is preferably to be free of semiconductor material, so as to prevent the semiconductor material from generating optical absorption noise. Referring toFIG. 1GandFIG. 2B, since the notch N is formed above the tip140tof the waveguide140, the region directly above the tip140tof the waveguide140is being occupied by air, and is free of semiconductor material. Moreover, the trumpet-like shape of the notch N shown inFIG. 2Bprovides extra margin to ensure more clearance of the semiconductor material above the tip140tof the waveguide140. As such, the noise originated from the semiconductor material (i.e. the semiconductor substrate110) may be eliminated, thereby enhancing the signal accuracy of the optical signals received and transmitted by the waveguide140.

FIG. 2Cis a schematic partial top view of the semiconductor substrate110and the waveguide140inFIG. 1Gin accordance with some alternative embodiments of the disclosure. For simplicity, the redistribution structure600, the insulation layer120, and the through vias160inFIG. 1Gare omitted inFIG. 2C. As illustrated inFIG. 2C, the notch N exhibits a trumpet-like shape from an edge toward an interior of the semiconductor substrate110in the top view. For example, a width of the notch N gradually increases from an edge of the semiconductor substrate110toward an interior of the semiconductor substrate110. In some embodiments, the notch N has a maximum width WN1of about 10 μm to about 20 μm and a minimum width WN2of about 9 μm to about 18 μm. On the other hand, a length LNof the notch N may range from about 100 μm to about 300 μm. In some embodiments, a width of the waveguide140is not uniform. For example, the waveguide140has a smaller width W1401at the tip140t. In some embodiments, a minimum width W1401of the waveguide140at the tip140tis about 50 nm to about 100 nm, and a maximum width W1402of the waveguide140is about 130 nm to about 260 nm. In some embodiments, a length L140tof the tip140tof the waveguide140located within the boundary of the notch N ranges from about 100 μm to about 300 μm. On the other hand, a distance D between an end of the tip140tand a virtual line extending from an edge of the semiconductor substrate110shown inFIG. 2Branges from about 10 μm to about 2 μm. Moreover, a spacing S between the tip140tof the waveguide140and a sidewall of the notch N ranges from about 5 μm to about 10 μm. As illustrated inFIG. 2C, a contour of the notch N may be conformal with a contour of the tip140tof the waveguide140. In some embodiments, the width of a portion of the notch N varies while the width of another portion of the notch remains constant. For example, the width of the notch N may gradually increase from an edge of the semiconductor substrate110toward an interior of the semiconductor substrate110until certain point. Thereafter, the width of the notch N remains constant, as shown inFIG. 2C.

As mentioned above, the waveguides140are able to transmit optical signals entering from the lateral side. When the optical signal is transmitted to the waveguide140from the lateral side, the region above and/or below the tip140tof the waveguide140is preferably to be free of semiconductor material, so as to prevent the semiconductor material from generating optical absorption noise. Referring toFIG. 1GandFIG. 2C, since the notch N is formed above the tip140tof the waveguide140, the region directly above the tip140tof the waveguide140is being occupied by air, and is free of semiconductor material. Moreover, since the trumpet-like shape shown inFIG. 2Cis conformal with the shape of the tip140tof the waveguide140, the area penalty may be minimized (i.e. the removal of the semiconductor substrate110may be kept at minimum). As such, the noise originated from the semiconductor material (i.e. the semiconductor substrate110) may be eliminated, thereby enhancing the signal accuracy of the optical signals received and transmitted by the waveguide140.

Referring toFIG. 1H, a plurality of conductive pads700is formed over the redistribution structure600. In some embodiments, the conductive pads700are partially embedded in the dielectric layer602of the redistribution structure600. For example, a plurality of openings is formed in the dielectric layer602to expose the topmost redistribution conductive layer604, and the conductive pads700extend into the openings of the dielectric layer602to render electrical connection with the redistribution conductive layer604. In some embodiments, a material of the conductive pads700includes aluminum, titanium, copper, nickel, tungsten, and/or alloys thereof. In some embodiments, the conductive pads700may be formed by electroplating, deposition, and/or photolithography and etching. In some embodiments, the conductive pads700may be referred to as “under-ball metallurgy (UBM) patterns.”

As illustrated inFIG. 1GandFIG. 1H, the conductive pads700are formed after the removal of the portion of the semiconductor substrate110. However, the disclosure is not limited thereto. In some alternative embodiments, the conductive pads700may be formed prior to the removal of the portion of the semiconductor substrate110. When the conductive pads700are formed prior to the removal of portions of the redistribution structure600and the semiconductor substrate110(shown inFIG. 1G), a photoresist layer (not shown) may be formed to cover the conductive pads700, so as to prevent the conductive pads700from being damaged by the etching process.

Referring toFIG. 1I, a plurality of conductive terminals800is formed over the conductive pads700. The conductive terminals800may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, a combination thereof, or the like. The conductive terminals800may be or may include controlled collapse chip connection (C4) bumps, metal pillars, micro-bumps, ball grid array (BGA), solder balls, electroless nickel-electroless palladium-immersion gold (ENEPIG) formed bumps, and/or the like. In some embodiments, the conductive terminals800are formed by forming a layer of solder through evaporation, plating, printing, ball placement, or the like. A reflow process is optionally performed to shape the layer of solder into the desired bump shapes. In some alternative embodiments, the conductive terminals800are metal pillars (e.g., a copper pillar) formed by sputtering, printing, plating, CVD, or the like. The conductive terminals800formed as metal pillars may be free of solder and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on the tops of the conductive terminals800. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof.

Referring toFIG. 1IandFIG. 1J, a singulation process is performed on the structure illustrated inFIG. 1Ito obtain a plurality of packages10. That is, the redistribution structure600, the semiconductor wafer SW, the encapsulant300, the bonding layer400, and the supporting substrate500are singulated. In some embodiments, the dicing process or the singulation process typically involves dicing with a rotating blade or a laser beam. In other words, the dicing or singulation process is, for example, a laser cutting process, a mechanical cutting process, or other suitable processes.

In some embodiments, during the singulation process, the semiconductor wafer SW is divided into a plurality of photonic integrated circuit dies100. As illustrated inFIG. 1J, each package10includes the photonic integrated circuit die100, the electric integrated circuit die200, the encapsulant300, the bonding layer400, the supporting substrate500, the redistribution structure600, the conductive pads700, and the conductive terminals800. The photonic integrated circuit die100includes the semiconductor substrate110, the insulation layer120, the dielectric layer130, the waveguide140, the interconnection structure150, and the through vias160. The semiconductor substrate110has the first surface110aand the second surface110bopposite to the first surface110a. The insulation layer120, the waveguide140, and the interconnection structure150are sequentially disposed on the first surface110aof the semiconductor substrate110. On the other hand, the dielectric layer130laterally wraps around the waveguide140. In some embodiments, the through vias160penetrate through the semiconductor substrate110, the insulation layer120, the dielectric layer130, and the interconnection structure150to electrically connect with the electric integrated circuit die200. The notch N is formed in the semiconductor substrate110. As illustrated inFIG. 1J, the notch N of the semiconductor substrate110is underneath at least a portion of the waveguide140. For example, a projection of the tip140tof the waveguide140along a direction perpendicular to the first surface110aof the semiconductor substrate110is overlapped with the notch N. In some embodiments, the electric integrated circuit die200is disposed over and electrically connected to the photonic integrated circuit die100. The encapsulant300laterally encapsulates the electric integrated circuit die200. In some embodiments, the bonding layer400and the supporting substrate500are sequentially stacked over the electric integrated circuit die200and the encapsulant300. On the other hand, the redistribution structure600, the conductive pads700, and the conductive terminals800are sequentially disposed over the second surface110bof the semiconductor substrate110.

Referring toFIG. 1K, the package10may be assembled with other components to form an optical device OP1. As illustrated inFIG. 1K, the optical device OP1includes the package10, a circuit substrate CS, a supporting structure SS, and an optical fiber F. In some embodiments, the package10is mounted onto the circuit substrate CS. In some embodiments, the circuit substrate CS includes a printed circuit board (PCB) or the like. In some embodiments, the package10is electrically connected to the circuit substrate CS through the conductive terminals800. For example, the conductive terminals800of the package10are directly in contact with the wiring of the circuit substrate1000to render electrical connection. In some embodiments, after the package10is attached to the circuit substrate CS, a reflow process is performed on the conductive terminals800to strengthen the attachment between the conductive terminals800and the circuit substrate CS.

In some embodiments, the supporting structure SS is disposed on the circuit substrate CS. For example, the supporting structure SS is disposed adjacent to the package10. In some embodiments, the optical fiber F is disposed on the supporting structure SS. That is, the supporting structure SS provides a platform to securely fix the optical fiber F in place. In some embodiments, the optical fiber F is disposed to be adjacent to the photonic integrated circuit die100of the package10. For example, the optical fiber F is disposed adjacent to the waveguide140of the photonic integrated circuit die100. In some embodiments, the optical fiber F is optically coupled to the waveguide140, so as to enable exchange of optical signals between the photonic integrated circuit die100and the optical fiber F. In some embodiments, the optical fiber F is aligned with the waveguide140to ensure minimum optical signal loss. As mentioned above, when the optical signals from the optical fiber F is transmitted to the waveguide140of the photonic integrated circuit die100, the region underneath the tip140tof the waveguide140is preferably to be free of semiconductor material, so as to reduce the noise originated from such material. As illustrated inFIG. 1K, since the notch N is formed directly below the tip140tof the waveguide140, the region directly underneath the tip140tof the waveguide140is being occupied by air, and is free of semiconductor material. As such, the noise originated from the semiconductor material (i.e. the semiconductor substrate110) may be eliminated, thereby enhancing the signal accuracy of the optical signals received and transmitted by the waveguide140. It should be noted that althoughFIG. 1Killustrated that the notch N is being occupied by air, the disclosure is not limited thereto. In some alternative embodiments, the notch N may be filled with a low optical absorption dielectric material, and the signal accuracy of the optical signals received and transmitted by the waveguide140may still be ensured.

FIG. 3is a schematic cross-sectional view illustrating an optical device OP2in accordance with some alternative embodiments of the disclosure. Referring toFIG. 3, the optical device OP2inFIG. 3is similar to the optical device OP1inFIG. 1K, so similar elements are denoted by the same reference numeral and the detailed descriptions thereof are omitted herein. The difference between the optical device OP2inFIG. 3and the optical device OP1inFIG. 1Klies in that the package10inFIG. 1Kis replaced by a package20inFIG. 3. The package20inFIG. 3is similar to the package10inFIG. 1Kexcept the photonic integrated circuit die100of the package20further includes an etch stop layer170. As illustrated inFIG. 3, the etch stop layer170is sandwiched between the semiconductor substrate110and the insulation layer120. In some embodiments, a material of the etch stop layer170includes silicon nitride or the like. As mentioned above, during the manufacturing process of the packages, a portion of the semiconductor substrate110is removed to form the notch N (shown inFIG. 1G). The etch stop layer170is able to prevent the etchant from damaging the underlying layer during removal of the semiconductor substrate110when forming the notch N. In some embodiments, during the etching process shown inFIG. 1G, the etch stop layer170may be slightly etched.

FIG. 4is a schematic cross-sectional view illustrating an optical device OP3in accordance with some alternative embodiments of the disclosure. Referring toFIG. 4, the optical device OP3inFIG. 4is similar to the optical device OP1inFIG. 1K, so similar elements are denoted by the same reference numeral and the detailed descriptions thereof are omitted herein. The difference between the optical device OP3inFIG. 4and the optical device OP1inFIG. 1Klies in that the package10inFIG. 1Kis replaced by a package30inFIG. 4. The package30inFIG. 4is similar to the package10inFIG. 1Kexcept the notch N does not penetrate through the semiconductor substrate110in the package30. For example, the notch N may be an undercut directly underneath the tip140tof the waveguide140. As illustrated inFIG. 4, the notch N has a curved sidewall. Since the notch N does not penetrate through the semiconductor substrate110, a height HNof the notch N is smaller than a thickness t110of the semiconductor substrate110. In some embodiments, the height HNof the notch N ranges from about 10 μm to about 50 μm. As illustrated inFIG. 4, since the notch N is formed below the tip140tof the waveguide140, the proximal region directly underneath the tip140tof the waveguide140is being occupied by air, and is free of semiconductor material. As such, the noise originated from the semiconductor material (i.e. the semiconductor substrate110) may be eliminated, thereby enhancing the signal accuracy of the optical signals received and transmitted by the waveguide140.

In accordance with some embodiments of the disclosure, a package includes a photonic integrated circuit die, an electric integrated circuit die, and an encapsulant. The photonic integrated circuit die includes a semiconductor substrate, an insulation layer, and a waveguide. The semiconductor substrate has a notch. The insulation layer is disposed on the semiconductor substrate. The waveguide is disposed on the insulation layer. The notch of the semiconductor substrate is underneath at least a portion of the waveguide. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The encapsulant laterally encapsulates the electric integrated circuit die.

In accordance with some embodiments of the disclosure, an optical device includes a circuit substrate and a package. The package is disposed on the circuit substrate. The package includes a photonic integrated circuit die and an electric integrated circuit die. The photonic integrated circuit die includes a semiconductor substrate, an insulation layer, and a waveguide. The semiconductor substrate has a first surface and a second surface opposite to the first surface. The semiconductor substrate includes a notch. The insulation layer is disposed on the first surface of the semiconductor substrate. The waveguide is disposed on the insulation layer. A projection of a tip of the waveguide along a direction perpendicular to the first surface of the semiconductor substrate is overlapped with the notch. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die.

In accordance with some embodiments of the disclosure, a manufacturing method of a package includes at least the following steps. A semiconductor wafer including a semiconductor substrate, an insulation layer, waveguides, and an interconnection structure stacked in sequential order is provided. An electric integrated circuit die is bonded to the semiconductor wafer. The electric integrated circuit die is laterally encapsulated by an encapsulant. A redistribution structure is formed over the semiconductor substrate opposite to the insulation layer. A portion of the semiconductor substrate is removed to form notches in the semiconductor substrate. Conductive pads are formed over the redistribution structure. Conductive terminals are formed over the conductive pads.