Chip capable of improving test coverage of pads and related method thereof

A method for improving test coverage of pads of a chip, where the chip includes a control unit, a plurality of pads, and a storage unit, and the storage unit includes a plurality of blocks, includes writing test data to a first predetermined block through a predetermined pad of the plurality of pads, controlling a first pad to read and store a predetermined datum of the test data from the first predetermined block, controlling the first pad to write the predetermined datum to a second predetermined block, reading the predetermined datum stored in the second predetermined block through the predetermined pad, and determining whether the first pad is passed.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates a chip capable of improving test coverage of chip pads and a method capable of improving test coverage of chip pads, and particularly to a chip and a method that can utilize a controller to control a pad not coupled to a probe to read/write a predetermined datum to improve test coverage of chip pads.

2. Description of the Prior Art

Please refer toFIG. 1andFIG. 2.FIG. 1is a diagram illustrating a probe100of a test machine utilizing a data compression method to write test data TD to a chip200according to the prior art, andFIG. 2is a diagram illustrating the probe100of the test machine utilizing the data compression method to read test data from the chip200according to the prior art. As shown inFIG. 1, the probe100writes the test data TD to a data path circuit206through a pad202and an off-chip unit204. Then, the data path circuit206writes the test data TD to a storage unit208of the chip200. As shown inFIG. 2, when the probe100utilizes the data compression method to read the test data from the chip200, the probe100can read the test data from a corresponding block of the storage unit208through an exclusive-OR gate210and the data path circuit206.

As shown inFIG. 1andFIG. 2, a chip probing test of the prior art can cover the data path circuit206, the storage unit208, the pad202, and the off-chip unit204. However, the chip probing test of the prior art can not cover other pads and other off-chip units of the chip200. That is to say, the chip probing test of the prior art can not determine whether other pads and other off-chip units of the chip200are passed.

SUMMARY OF THE INVENTION

An embodiment provides a chip capable of improving test coverage of chip pads. The chip includes a control unit, a plurality of pads, and a storage unit. A predetermined pad of the plurality of pads is used for coupling to a probe of a probe card, and the probe card is coupled to a test machine. The storage unit includes a plurality of blocks. The control unit controls a first pad of the plurality of pads to read and store a predetermined datum of test data from a first predetermined block, the control unit controls the first pad to write the predetermined datum to a second predetermined block of the plurality of blocks, the test machine controls the probe to read the predetermined datum stored in the second predetermined block through the predetermined pad, and the test machine determines whether the first pad is passed according to a read result.

Another embodiment provides a method capable of improving test coverage of chip pads. A chip includes a control unit, a plurality of pads, and a storage unit, where the storage unit includes a plurality of blocks. The method includes writing test data to a first predetermined block of the plurality of blocks through a predetermined pad of the plurality of pads; controlling a first pad of the plurality of pads to read and store a predetermined datum of the test data from the first predetermined block; controlling the first pad to write the predetermined datum to a second predetermined block of the plurality of blocks; reading the predetermined datum stored in the second predetermined block through the predetermined pad; and determining whether the first pad is passed according to a read result.

The present invention provides a chip capable of improving test coverage of chip pads and a method capable of improving test coverage of chip pads. The chip and the method utilize a controller to control a pad not coupled to a probe to read a predetermined datum, and utilize the controller to control the pad not coupled to the probe to write the predetermined datum to a predetermined block of a storage unit. Then, a test machine controls the probe to read the predetermined datum stored in the predetermined block through a predetermined pad, and records a read result corresponding to the pad not coupled to the probe. Therefore, the test machine can determine whether the pad not coupled to the probe is passed according to the read result. In addition, the test machine can also determine a leakage condition of the pad not coupled to the probe according to the read result corresponding to the pad not coupled to the probe.

DETAILED DESCRIPTION

Please refer toFIG. 3.FIG. 3is a diagram illustrating a chip300capable of improving test coverage of chip pads according to an embodiment. The chip300includes a control unit302, a plurality of pads3041-304N, a plurality of off-chip units3061-306N, a plurality of data path units3081-308N, and a storage unit310, where N is a positive integer. As shown inFIG. 3, a predetermined pad3041of the plurality of pads3041-304N is used for coupling to a probe314of a probe card312, and the probe card312is coupled to a test machine316. But, the present invention is not limited to the predetermined pad3041being coupled to the probe314. That is to say, other pads of the plurality of pads3041-304N can also be coupled to the probe314. Each off-chip unit of the plurality of off-chip units3061-306N is coupled between a data path unit and a pad. The storage unit310includes a plurality of blocks3101-310N, and the storage unit310can be a memory array.

As shown inFIG. 3, the test machine316controls the probe314to write test data to the first predetermined block3101through the off-chip unit3061and the data path unit3081coupled to the predetermined pad3041. For example, the test machine316controls the probe314to write logic “0” to all memory cells of the first predetermined block3101through the off-chip unit3061and the data path unit3081coupled to the predetermined pad3041. Then, the test machine316controls the probe314to write a predetermined datum (e.g. logic “1”) of test data to a memory cell31011of the first predetermined block3101. But, the present invention is not limited to the test machine316controlling the probe314to write the test data to the first predetermined block3101. That is to say, the test machine316can also control the probe314to write the test data to other blocks of the plurality of blocks3101-310N. In addition, the present invention is also not limited to the above mentioned test data pattern.

Then, the control unit302controls a first pad3042of the plurality of pads3041-304N to read and store the predetermined datum (the logic “1”) from the memory cell31011of the first predetermined block3101. That is to say, the first pad3042utilizes a parasitic capacitor PC thereof to store the predetermined datum (the logic “1”) . After the first pad3042utilizes the parasitic capacitor PC thereof to store the predetermined datum (the logic “1”), the control unit302controls the first pad3042to write the predetermined datum (the logic “1”) to all memory cells of a second predetermined block3102of the plurality of blocks3101-310N. But, the present invention is not limited to the control unit302controlling the first pad3042to write the predetermined datum (the logic “1”) to the memory cells of the second predetermined block3102in turn. That is to say, the control unit302can also control the first pad3042to write the predetermined datum (the logic “1”) to other blocks of the plurality of blocks3101-310N. Then, the test machine316can control the probe314to read the predetermined datum (the logic “1”) stored in the second predetermined block3102through the predetermined pad3041, and record a read result corresponding to the first pad3042.

Please refer toFIG. 4.FIG. 4is a diagram illustrating the read result corresponding to the predetermined datum (the logic “1”) stored in the first pad3042. As shown inFIG. 4, because the control unit302controls the first pad3042to write the predetermined datum (the logic “1”) to the memory cells of the second predetermined block3102in turn, the test machine316can record gradually decrease potential stored in the memory cells of the second predetermined block3102. That is to say, the first pad3042utilizes storing charges thereof corresponding to the predetermined datum (the logic “1”) charges the memory cells of the second predetermined block3102in turn, so potential of the first pad3042can be gradually decreased, resulting in the potential stored in the memory cells of the second predetermined block3102being also gradually decreased. As shown inFIG. 4, when potential stored in a memory cell is lower than a reference voltage VREF, the test machine316determines that the memory cell stores the logic “0”; when potential stored in the memory cell is higher than the reference voltage VREF, the test machine316determines that the memory cell stores the logic “1”. Therefore, the test machine316can determined whether the first pad3042is passed according to a read result shown inFIG. 4. That is to say, if the read result corresponding to the predetermined datum (the logic “1”) stored in the first pad3042is not similar to the read result shown inFIG. 4, the test machine316can determined that the first pad3042is not passed. In addition, the test machine316can determine a leakage condition of the first pad3042according to the read result corresponding to the predetermined datum (the logic “1”) stored in the first pad3042and equation (1):

As shown in equation (1), Ileakage is a leakage current of the first pad3042, Cm is a storage capacitance of each memory cell, V1is potential corresponding to the logic “1”, VREF is a reference voltage, TCK is time for writing data to each memory cell, and M is number of memory cells which stores the logic “1”.

In addition, if the test machine316controls the probe314to write the logic “1” to the memory cells of the first predetermined block3101through the off-chip unit3061and the data path unit3081coupled to the predetermined pad3041. Then, the test machine316controls the probe314to write a predetermined datum (e.g. the logic “0”) of the test data to the memory cell31011of the first predetermined block3101. But, the present invention is not limited to the above mentioned test data pattern. Then, the control unit302controls the first pad3042to read and store the predetermined datum (the logic “0”) from the memory cell31011. After the first pad3042utilizes the parasitic capacitor PC thereof to store the predetermined datum (the logic “0”), the control unit302controls the first pad3042to write the predetermined datum (the logic “0”) to the memory cells of the second predetermined block3102in turn. But, the present invention is not limited to the control unit302controlling the first pad3042to write the predetermined datum (the logic “0”) to the memory cells of the second predetermined block3102in turn. That is to say, the control unit302can also control the first pad3042to write the predetermined datum (the logic “0”) to other blocks of the plurality of blocks3101-310N. Then, the test machine316can control the probe314to read the predetermined datum (the logic “0”) stored in the second predetermined block3102through the predetermined pad3041, and record a read result corresponding to the first pad3042.

Please refer toFIG. 5.FIG. 5is a diagram illustrating the read result corresponding to the predetermined datum (the logic “0”) stored in the first pad3042. As shown inFIG. 5, because the control unit302controls the first pad3042to write the predetermined datum (the logic “0”) to the memory cells of the second predetermined block3102in turn, the test machine316can record gradually increase potential stored in the memory cells of the second predetermined block3102. Therefore, as shown inFIG. 5, the test machine316can determine whether the first pad3042is passed according to a read result shown inFIG. 5. That is to say, if the read result corresponding to the predetermined datum (the logic “0”) stored in the first pad3042is not similar to the read result shown inFIG. 5, the test machine316can determined that the first pad3042is not passed. In addition, the test machine316can further determine a leakage condition of the first pad3042according to the read result corresponding to the predetermined datum (the logic “0”) stored in the first pad3042and equation (1).

In addition, the present invention can also test other pads of the plurality of pads3041-304N according to the above mentioned method for testing the first pad3042. In addition, the present invention can also simultaneously test the plurality of pads3041-304N according to the above mentioned method for testing the first pad3042.

Please refer toFIG. 6.FIG. 6is a diagram illustrating a chip600capable of improving test coverage of chip pads according to another embodiment. A difference between the chip600and the chip300is that a storage unit610included in the chip600is a logic circuit, and a plurality of off-chip units6061-606N are coupled to each other. In addition, because the plurality of off-chip units6061-606N are coupled to each other, the test machine316controls the probe314to write test data to the plurality of off-chip units6061-606N through the predetermined pad3041according to a boundary scan method, where the boundary scan method is that the test data are written to the plurality of off-chip units6061-606N in turn through a shift registering method. Then, the control unit302controls the plurality of off-chip units6061-606N to write the test data to a first predetermined block6101of the storage unit610through the plurality of data path units3081-308N. In addition, those skilled in the scope of the present invention can easily know that subsequent operational principles of the chip600are the same as those of the chip300, so further description thereof is omitted for simplicity.

Please refer toFIG. 3,FIG. 4, heFIG. 5, andFIG. 7.FIG. 7is a method capable of improving test coverage of chip pads according to another embodiment. The method inFIG. 7is illustrated using the chip300inFIG. 3. Detailed steps are as follows:

Step701: The test machine316couples the probe314of the probe card312to the predetermined pad3041.

Step702: The probe314of the probe card312writes test data to the first predetermined block3101of the plurality of blocks3101-310N through the off-chip unit3061and the data path unit3081coupled to the predetermined pad3041.

Step704: The control unit302controls the first pad3042to read and store a predetermined datum of the test data from the first predetermined block3101.

Step706: The control unit302controls the first pad3042to write the predetermined datum to the second predetermined block3102of the plurality of blocks3101-310N.

Step708: The test machine316controls the probe314to read the predetermined datum stored in the second predetermined block3102through the predetermined pad3041.

Step710: The test machine316determines whether the first pad3042is passed and a leakage condition of the first pad3042according to a read result.

In Step702, as shown inFIG. 3, the test machine316controls the probe314of the probe card312to write the test data to the first predetermined block3101of the storage unit310through the off-chip unit3061and the data path unit3081coupled to the predetermined pad3041, where the storage unit310can be a memory array. For example, the test machine316controls the probe314to write logic “0” to the memory cells of the first predetermined block3101through the off-chip unit3061and the data path unit3081coupled to the predetermined pad3041. Then, the test machine316controls the probe314to write a predetermined datum (e.g. logic “1”) of the test data to the memory cell31011of the first predetermined block3101. But, the present invention is not limited to the test machine316controlling the probe314to write the test data to the first predetermined block3101. That is to say, the test machine316can also control the probe314to write the test data to other blocks of the plurality of blocks3101-310N. In addition, the present invention is also not limited to the above mentioned test data pattern.

In Step704, the control unit302controls the first pad3042to read and store the predetermined datum (the logic “1”) from the memory cell31011of the first predetermined block3101. That is to say, the first pad3042utilizes the parasitic capacitor PC thereof to store the predetermined datum (the logic “1”). In Step706, after the first pad3042utilizes the parasitic capacitor PC thereof to store the predetermined datum (the logic “1”), the control unit302controls the first pad3042to write the predetermined datum (the logic “1”) to the memory cells of the second predetermined block3102in turn. Then, in Step708, the test machine316controls the probe314to read the predetermined datum (the logic “1”) stored in the second predetermined block3102through the predetermined pad3041, and record the read result corresponding to the first pad3042.

In Step710, as shown inFIG. 4, because the control unit302controls the first pad3042to write the predetermined datum (the logic “1”) to the memory cells of the second predetermined block3102in turn, the test machine316can determined whether the first pad3042is passed according to the read result shown inFIG. 4. That is to say, if the read result corresponding to the predetermined datum (the logic “1”) stored in the first pad3042is not similar to the read result shown inFIG. 4, the test machine316can determined that the first pad3042is not passed. In addition, the test machine316can determine the leakage condition of the first pad3042according to the read result corresponding to the predetermined datum (the logic “1”) stored in the first pad3042and equation (1).

In Step710, because the control unit302controls the first pad3042to write the predetermined datum (the logic “0”) to the memory cells of the second predetermined block3102in turn, the test machine316can determine whether the first pad3042is passed according to the read result shown inFIG. 5. That is to say, if the read result corresponding to the predetermined datum (the logic “0”) stored in the first pad3042is not similar to the read result shown inFIG. 5, the test machine316can determined that the first pad3042is not passed. In addition, the test machine316can further determine the leakage condition of the first pad3042according to the read result corresponding to the predetermined datum (the logic “0”) stored in the first pad3042and equation (1).

Please refer toFIG. 6andFIG. 8.FIG. 8is a method capable of improving test coverage of chip pads according to another embodiment. The method inFIG. 8is illustrated using the chip600inFIG. 6. Detailed steps are as follows:

Step802: The test machine316couples the probe314of the probe card312to the predetermined pad3041.

Step804: The probe314of the probe card312writes test data to the plurality of off-chip units6061-606N through the predetermined pad3041according to the boundary scan method.

Step806: The control unit302controls the plurality of off-chip units6061-606N to write the test data to the first predetermined block6101of the plurality of blocks6101-610N through the data path units3081-308N.

Step808: The control unit302controls the first pad3042to read and store a predetermined datum of the test data from the first predetermined block6101.

Step810: The control unit302controls the first pad3042to write the predetermined datum to the second predetermined block3102of the plurality of blocks3101-310N.

Step812: The test machine316controls the probe314to read the predetermined datum stored in the second predetermined block3102through the predetermined pad3041.

Step814: The test machine316determines whether the first pad3042is passed and a leakage condition of the first pad3042according to a read result.

A difference between the embodiment inFIG. 8and the embodiment inFIG. 7is that in Step804, because the plurality of off-chip units6061-606N are coupled to each other, the test machine316controls the probe314to write the test data to the plurality of off-chip units6061-606N through the predetermined pad3041according to the boundary scan method, where the boundary scan method is that the test data are written to the plurality of off-chip units6061-606N in turn through the shift registering method. Then, in Step806, the control unit302controls the plurality of off-chip units6061-606N to write the test data to the first predetermined block6101of the storage unit610through the plurality of data path units3081-308N, where the storage unit610can be a logic circuit . In addition, those skilled in the scope of the present invention can easily know that subsequent operational principles of the embodiment inFIG. 8are the same as those of the embodiment inFIG. 7, so further description thereof is omitted for simplicity.

To sum up, the chip capable of improving test coverage of chip pads and the method capable of improving test coverage of chip pads utilize the controller to control a pad not coupled to the probe to read a predetermined datum, and utilize the controller to control the pad not coupled to the probe to write the predetermined datum to a predetermined block of the storage unit. Then, the test machine controls the probe to read the predetermined datum stored in the predetermined block through a predetermined pad, and records a read result corresponding to the pad not coupled to the probe. Therefore, the test machine can determine whether the pad not coupled to the probe is passed according to the read result. In addition, the test machine can also determine a leakage condition of the pad not coupled to the probe according to the read result corresponding to the pad not coupled to the probe.