Methods of forming electrical interconnects on integrated circuit substrates using selective slurries

Methods of forming electrical interconnects include the steps of forming a first electrically conductive layer on a semiconductor substrate and then forming a first electrically insulating layer on the first electrically conductive layer. A second electrically insulating layer is then formed on the first electrically insulating layer. The second electrically insulating layer is then etched to expose the first electrically insulating layer and then a third electrically insulating layer is formed on the first electrically insulating layer. The first and third electrically insulating layers are then etched to define a contact hole therein which exposes a portion of the first electrically conductive layer. A barrier metal layer is then formed. The barrier metal layer is preferably formed to extend on the third electrically insulating layer and on the exposed portion of the first electrically conductive layer. The second electrically conductive layer is then formed to extend on the barrier metal layer and into the contact hole. The second electrically conductive layer and barrier metal layer are then polished in sequence to expose the third electrically insulating layer. The step of polishing the second electrically conductive layer and the barrier metal layer preferably comprises the steps of polishing the second electrically conductive layer and the third electrically insulating layer simultaneously at a first rate and a second rate less than the first rate, respectively, using a first slurry, and then polishing the second electrically conductive layer and the third electrically insulating layer simultaneously at a third rate and a fourth rate greater than the third rate, respectively, using a second slurry.

FIELD OF THE INVENTION

The present invention relates to methods of forming integrated circuits and more particularly, to methods of forming electrical interconnects on integrated circuit substrates.

BACKGROUND OF THE INVENTION

A wiring layer in a semiconductor device functions to transmit signals and is typically connected to lower conduction layers via contact plugs. Contact plugs should typically be formed of low-resistivity metals in order to prevent signal delays.

FIGS. 1A-1Dare sectional views for illustrating a conventional method of forming a contact plug in a semiconductor device. InFIGS. 1A-1D, reference numeral1is a semiconductor substrate, reference numeral3is an inter-insulating layer, reference numeral5is a wiring layer, reference numerals7,7a and7b are insulating films, reference numeral8is a contact hole, reference numerals9and9a are barrier layers and reference numerals11and11a are material layers. Referring toFIG. 1A, a conductive material is deposited on a semiconductor substrate1on which an inter-insulating layer3is formed, and then patterned to form a wiring layer5. Next, an insulating material is deposited on the semiconductor substrate1on which the wiring layer5is formed, thereby forming the insulating film7. The wiring layer5may be formed of a metal, e.g., aluminum (Al). The insulating film7has depressed portions which conform to the structure of the wiring layer5.

Referring now toFIG. 1B, the insulating film7undergoes a chemical and mechanical polishing (CMP) process to form a planarized insulating film7a. At this time, the insulating film7a can be formed to a predetermined thickness by controlling the time required for the polishing process. Thereafter, a cleaning process such as a spin scrubbing method is performed to remove particles generated during the polishing process.

Referring now toFIG. 1C, the insulating film7a is etched using photolithography to expose the surface of the wiring layer5and form contact holes8. Titanium (Ti) and titanium nitride (TiN) are sequentially deposited in the contact holes8to form a barrier layer9having a titanium nitride (TiN)/titanium (Ti) structure. Then, tungsten (W) is deposited on the entire surface of the semiconductor substrate1on which the barrier layer9is formed, thereby forming the material layer11. The titanium reduces the contact resistance between the tungsten as the component material of the material layer11and the aluminum as that of the wiring layer5. The titanium nitride also improves adhesion of the tungsten.

Referring toFIG. 1D, the material layer11and the barrier layer9undergo a chemical and mechanical polishing (CMP) process until an insulating film7b is exposed. Accordingly, a plurality of contact plugs comprised of a material layer11a and a barrier layer9a are formed in the contact hole8. As described above, the CMP process is carried out two times, after the deposition of the insulating film7and after the deposition of the material layer11. Unfortunately, the use of two polishing steps complicates the process for forming contact plugs.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide improved methods of forming electrical interconnects on integrated circuit substrates.

These and other objects, advantages and features of the present invention are provided by methods of forming electrical interconnects which include the steps of forming a first electrically conductive layer on a semiconductor substrate and then forming a first electrically insulating layer on the first electrically conductive layer. A second electrically insulating layer is then formed on the first electrically insulating layer. The second electrically insulating layer is then etched to expose the first electrically insulating layer and then a third electrically insulating layer is formed on the first electrically insulating layer. The first and third electrically insulating layers are then etched to define a contact hole therein which exposes a portion of the first electrically conductive layer. A barrier metal layer is then formed. The barrier metal layer is preferably formed to extend on the third electrically insulating layer and on the exposed portion of the first electrically conductive layer. The second electrically conductive layer is then formed to extend on the barrier metal layer and into the contact hole. The second electrically conductive layer and barrier metal layer are then polished in sequence to expose the third electrically insulating layer.

According to a preferred aspect of the present invention, the step of polishing the second electrically conductive layer and the barrier metal layer comprises the steps of polishing the second electrically conductive layer and the third electrically insulating layer simultaneously at a first rate and a second rate less than the first rate, respectively, using a first slurry, and then polishing the second electrically conductive layer and the third electrically insulating layer simultaneously at a third rate and a fourth rate greater than the third rate, respectively, using a second slurry. These polishing steps are preferably performed in an apparatus containing first and second polishing plates with the first and second slurries, respectively. According to another preferred aspect of the present invention, the step of forming a third electrically insulating layer is followed by the step of forming a trench having a first width in the third electrically insulating layer. According to this aspect of the present invention, the step of patterning the first and third electrically insulating layers comprises patterning the first and third electrically insulating layers to define a contact hole having a second width less than the first width, extending between a bottom of the trench and the first electrically conductive layer.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring toFIGS. 2Ato2E, reference numeral21is a semiconductor substrate, reference numeral23is an inter-insulating layer, reference numeral25is a wiring layer, reference numerals27,27a and27b are first insulating films, reference numeral29is a second insulating film, reference numerals31,31a and31b are third insulating films, reference numeral32is a contact hole, reference numerals33,33a and33b are barrier layers, and reference numerals35,35a and35b are material layers.

Referring specifically toFIG. 2A, a conductive material is deposited on the semiconductor substrate21on which the inter-insulating layer23is formed, and then patterned to form the wiring layer25. An insulating material is deposited on the semiconductor substrate21on which the wiring layer25is formed, thereby forming the first insulating film27. Then, the second insulating film29is formed on the first insulating film27. The wiring layer25may be formed of a metal, e.g., aluminum (Al). The first insulating film27is formed by depositing an oxide material including silicon to a thickness of between 1000 and 100000 Å using a high density plasma method wherein deposition and etching are simultaneously performed. At this time, a step difference is generated due to the wiring layer25. SiO2, SiOF, boron phosphorus silicate glass (BPSG), etc. can be used as the oxide material including silicon. The second insulating film29may be formed by depositing silicon-on-glass (SOG) to a thickness of between 1000 and 100000 A. However, any one selected among a flowable oxide, a photoresist and an insulating polymer can be used instead of SOG. Alternatively, the second insulating film29can be formed by depositing any one of the above materials twice or more. At this time, a thermal treatment step is additionally performed after each of the depositing steps in order to improve the characteristics of the film material.

Referring toFIG. 2B, the second insulating film29is etched back until it is completely removed, and a third insulating film31is then formed on the first insulating film27. The etching-back process is performed under a condition where the ratio of the etching selectivity of the first insulating film27to the second insulating film29is between about 3 and 0.33. As a result of such an etching-back process, a planarized first insulating film27a is obtained. As compared to the conventional method wherein a spin scrubbing process is performed after a chemical and mechanical polishing (CMP) process, the etching-back process simplifies the process and reduces process costs. The third insulating film31is formed of either a single layer using any one selected among SiO2, undoped silicate glass (USG), boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), SiOF, SiN, SiON, spin-on-glass (SOG), a flowable oxide and an insulating polymer, or a multi-layer formed by combining the single layers. At this time, the thickness of the entire third insulating film31is set between 10 and 100000 Å.

Among the above materials forming the third insulating film31, SiO2, undoped silicate glass (USG), boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), SiOF, SiN and SiON are deposited according to either a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced CVD (PECVD) method, and spin-on-glass (SOG), flowable oxide and insulating polymer are coated according to a spin coating method.

Referring toFIG. 2C, the third insulating film31and the first insulating film27a are selectively etched using photolithography to expose the surface of the wiring layer25, thereby forming the contact hole32. Then, a barrier layer33is formed on the semiconductor substrate21on which the contact hole32is formed. Next, a low-resistance metal is deposited on the entire surface of the semiconductor substrate21on which the barrier layer33is formed, thereby forming the material layer35. The barrier layer33can be formed of a single layer of a refractory metal, e.g., titanium (Ti), titanium nitride (TiN) or tungsten nitride (WN) or a multi layer formed by combining the single layers, in addition to a titanium nitride (TiN)/titanium (Ti) structure. The low-resistance metal for the material layer35includes tungsten (W), aluminum (Al) and copper (Cu). In addition, the material layer35can be formed of any one material selected among low-resistance metal compounds such as polysilicon, tungsten silicon, an aluminum copper compound and an aluminum copper silicon compound.

Referring toFIG. 2D, the material layer35and the barrier layer33are polished using a CMP apparatus until the surface of the third insulating film31a is exposed. The polishing apparatus includes at least two polishing plates which can employ different slurries. The polishing process is performed by at least one polishing plate using a slurry that can polish the material layer35at a higher rate than the third insulating film31a, so that the material layer35and the barrier layer33on the third insulating film31a are selectively removed. As a result, a contact plug composed of the material layer35a and the barrier layer33a is formed in the contact hole32.

Referring toFIG. 2E, the CMP process is performed in situ to planarize the third insulating film31a. Here, the polishing process may be performed by at least the other polishing plate of the CMP apparatus using a slurry that can polish the third insulating film31a at a faster rate than the material layer35a, so that a portion of the third insulating film31a is removed.

Next, a cleaning process is performed on the semiconductor substrate21using DI (De-Ionized) water in order to eliminate particles generated during the polishing process. This cleaning process may be performed by a polishing plate, to which a polishing pad used only for cleansing is attached, or in a dedicated cleaning apparatus.

FIGS. 3Ato3C are sectional views for illustrating a second embodiment for forming a contact plug for a semiconductor device according to the present invention. Reference numeral51is a semiconductor substrate, reference numeral53is an inter-insulating layer, reference numeral55is a wiring layer, reference numerals57and57a are first insulating films, reference numeral58is a trench, reference numerals59and59a are third insulating films, reference numeral60is a contact hole, reference numerals61and61a are barrier layers, and reference numerals63and63a are material layers.

Referring toFIG. 3A, a conductive material is deposited on the semiconductor substrate51on which the inter-insulating layer53is formed, and then patterned to form the wiring layer55. An insulating material is deposited on the semiconductor substrate51on which the wiring layer55is formed, thereby forming the first insulating film57and a second insulating film (not shown) in a sequence. Then, the second insulating film is etched back until it is completely removed. A third insulating film (which will be patterned later to be reference numeral59) is formed on the first insulating film57. The third insulating film above the wiring layer55is removed partially or completely using photolithography, thereby forming the trench58in the third insulating film59. The wiring layer55may be formed of a metal such as aluminum (Al).

The first insulating film57is formed by depositing an oxide material including silicon to a thickness of between 1000 and 100000 Å using a high density plasma (HDP) method wherein deposition and etching are simultaneously performed. At this time, a step difference is generated due to the wiring layer55. SiO2, SiOF, boron phosphorus silicate glass (BPSG), etc. can be used as the oxide material including silicon. The second insulating film is formed by depositing silicon-on-glass (SOG) to a thickness of between 1000 and 100000 Å. However, any one selected among a flowable oxide, a photoresist and an insulating polymer can be used instead of SOG. Alternatively, the second insulating film can be formed by depositing any one of the above materials twice or more. At this time, a thermal treatment step is additionally performed after each of the depositing processes in order to improve the characteristics of the film material. The etching-back process is performed under a condition where the etching selectivity of the first insulating film57to the second insulating film is between 3 to 1 and 1 to 3. Consequently, the first insulating film57is planarized.

As compared to the conventional method wherein a spin scrubbing process is performed after a chemical and mechanical polishing (CMP) process, the planarizing method using the etching-back process is simple and reduces fabricating costs, as described more fully herein below. The third insulating film59is formed of either a single layer using any one selected among SiO2, undoped silicate glass (USG), boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), SiOF, SiN, SiON, spin-on-glass (SOG), a flowable oxide and an insulating polymer, or a multi layer formed by combining the single layers. At this time, the thickness of the entire third insulating film59is set between 10 and 100000 Å.

Among the above materials forming the third insulating film59, SiO2, undoped silicate glass (USG), boron phosphorus silicate glass (BPSG), phosphorus silicate glass (PSG), SiOF, SiN or SiON may be deposited according to either a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced CVD (PECVD) method, and spin-on-glass (SOG), flowable oxide and insulating polymer may be deposited according to a spin coating method.

The trench58is for forming another wiring layer which is connected to the wiring layer55. Referring toFIG. 3B, the third insulating film59and the first insulating film57are etched using photolithography to expose the surface of the wiring layer55, thereby forming the contact hole60. Then, the barrier layer61is formed on the semiconductor substrate51on which the contact hole60is formed. Next, a low-resistance metal is deposited on the entire surface of the semiconductor substrate51on which the barrier layer61is formed, thereby forming the material layer63.

The barrier layer61can be formed of a single layer of a refractory metal, e.g., titanium (Ti), titanium nitride (TiN) or tungsten nitride (WN) or a multi layer formed by combining the single layers, in addition to a titanium nitride (TiN)/titanium (Ti) structure. The low-resistance metal for the material layer63includes tungsten (W), aluminum (Al) and copper (Cu). In addition, the material layer63can be formed of any one material selected among low-resistance metal compounds such as polysilicon and tungsten silicon, aluminum copper compound and aluminum copper silicon compound.

Referring toFIG. 3C, the material layer63and the barrier layer61are polished until the surface of the third insulating film59a is exposed. A first polishing process is then performed using a slurry which is capable of polishing the material layer63at a faster rate than the third insulating film59a. Consequently, the contact hole60and the trench58are filled with the material layer63a and the barrier layer61a so that a contact plug is formed in the contact hole60and another wiring layer is formed in the trench58. Thus, a plug and additional wiring layer can be simultaneously formed in accordance with a second embodiment of the present invention.

Then, a second polishing process is performed using another slurry which is capable of polishing the third insulating film59a at a faster rate than the material layer63. The first and second polishing processes may be performed using respective first and second polishing plates in a polishing apparatus. At this time, the contact plug having a material layer63a/barrier layer61a structure can be formed to a certain thickness by controlling the polishing time. Next, a cleaning process is performed on the semiconductor substrate51using DI (De-Ionized) water in order to eliminate particles generated during the polishing process. This cleaning process may be performed by a polishing plate to which a polishing pad used only for cleansing is attached, or in a cleaning apparatus.

FIGS. 4Ato4D are sectional views for illustrating a third embodiment for forming contact plug for a semiconductor device according to the present invention. Reference numeral71is a semiconductor substrate, reference numeral73is an inter-insulating layer, reference numeral75is a wiring layer, reference numerals77,77a and77b are insulating films, reference numeral78is a contact hole, reference numerals79,79a and79b are barrier layers, and reference numerals81,81a and81b are material layers.

Referring toFIG. 4A, a conductive material is deposited on the semiconductor substrate71on which the inter-insulating layer73is formed, and then patterned to form the wiring layer75. An insulating material is deposited on the semiconductor substrate71on which the wiring layer75is formed, thereby forming the insulating film77. The wiring layer75may be formed of a metal such as aluminum (Al). The insulating film77may be formed by depositing an oxide material including silicon to a thickness of between 1000 and 100000 Å using a high density plasma (HDP) method wherein deposition and etching are simultaneously performed. At this time, a step difference is generated due to the wiring layer75. SiO2, SiOF, boron phosphorus silicate glass (BPSG), etc. can be used as the oxide material including silicon.

Referring toFIG. 4B, the insulating film77is etched using photolithography until the surface of the wiring layer75is exposed, thereby forming the contact hole78. Then, the barrier layer79is formed on the semiconductor substrate71on which the contact hole78is formed. Next, a low-resistance metal is deposited on the entire surface of the semiconductor substrate71on which the barrier layer79is formed, thereby forming the material layer81. The barrier layer79can be formed of a single layer of a refractory metal, e.g., titanium (Ti), titanium nitride (TiN) or tungsten nitride (WN) or a multi layer formed by combining the single layers, in addition to a titanium nitride (TiN)/titanium (Ti) structure. In addition, the material layer81can be formed of any one material selected among tungsten (W), aluminum (Al) and copper (Cu), polysilicon and a tungsten silicon compound, an aluminum copper compound, and a low-resistance metal compound such as an aluminum copper silicon compound.

Referring toFIG. 4C, the material layer81and the barrier layer79are polished until the surface of the insulating film77a is exposed. The polishing process is performed using a first slurry which can polish the material layer81faster than the insulating film77a. This polishing step can be performed using one polishing plate of a CMP apparatus including at least two polishing plates. Referring toFIG. 4D, the polishing process is again performed using a second slurry which can polish the material layer81at a slower rate than the insulating film77a. Consequently, a contact plug having the material layer81b/barrier layer79b structure, and the planarized insulating film77b, are formed in the contact hole78.

As described above, in the contact plug forming method for a semiconductor device according to the present invention, the insulating film is planarized using an etching-back method instead of a CMP process, and the material layer and the insulating film for forming a contact plug are consecutively polished using a CMP apparatus including at least two polishing plates. Therefore, the process is simplified, the planarization degree is improved, and a contact plug and another wiring layer can be simultaneously formed.