Quadrature-phase voltage controlled oscillator

A voltage controlled oscillator (VCO) is provided. The VCO may include a first ring oscillation circuit that may have a plurality of delay cells and may output first differential oscillation signals, and a second ring oscillation circuit that may have a plurality of delay cells and may output second differential oscillation signals. The delay cells of the first ring oscillation circuit may be respectively cross-coupled to the corresponding delay cells of the second ring oscillation circuit. Each of the delay cells may include a differential amplification circuit that may output a first differential signal based on a first control signal, and a negative resistance circuit that may be connected in parallel to a pair of output terminals of the differential amplification circuit, may receive a second differential signal, may adjust the phase of the first differential signal based on a second control signal, and may then output the first differential signal.

PRIORITY STATEMENT

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2007-0036166, filed on Apr. 12, 2007, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

BACKGROUND

Example embodiments may relate to a voltage controlled oscillator (VCO), and more particularly, to a VCO for generating quadrature-phase clock signals.

2. Description of Related Art

A voltage controlled oscillator (VCO) is a circuit that may output a signal having a frequency that may be proportional or disproportional to a voltage applied from the outside. The VCO may be used in analog circuits or digital circuits, and particularly, in a phase locked loop (PLL) circuit, which may be employed in a radio data communication.

Examples of the VCO may include a ring oscillator and a LC oscillator, which may be selectively used according to their circuit characteristics. Recently, a complementary metal oxide semiconductor (CMOS) ring oscillator, which may be a highly integrated and low-cost circuit, has been widely used.

The CMOS ring oscillator may include an odd number of delay cells, and may have a ring structure in which a signal output from a delay cell of a last stage may be fed back to a delay cell of a first stage.

The total number of the delay cells of the ring oscillator may be inversely proportional to an output oscillation frequency. Thus, a 3-stage ring oscillator with three delay cells may be used in order to establish a high-speed data communication.

Two signals from among signals output from the 3-stage ring oscillator may be respectively phase-shifted by 120 degrees and 240 degrees with respect to the other signal.

However, quadrature-phase (4-phase) clock signals may be needed in order to reproduce data received or transmitted during a high-speed data communication. The 4-phase clock signals may also be needed in order to serialize or parallelize a data signal received or transmitted in a data pipeline stage of a semiconductor memory device, such as a dynamic random access memory (DRAM).

Thus, the ring oscillator with three delay cells may be suitable for transmission of data at high speeds but may not be suitable for a data communication requiring the 4-phase signals.

Either a ring oscillator with four delay cells or an additional circuit may be needed in order to generate the 4-phase clock signals that are phase shifted by 90 degrees with respect to one another.

FIG. 1is a circuit diagram of a conventional PLL circuit10for generating 4-phase frequencies. Referring toFIG. 1, the PLL circuit10may have a phase/frequency detector11, a charge pump12, a loop filter13, a VCO14, a duty correction circuit15, and a frequency divider16. In the PLL circuit10, in order to generate 4-phase clock signals I, IB, Q, and QB having a desired frequency, e.g., 2.5 GHz, the VCO14may generate a clock signal having a frequency, e.g., 5.0 GHz, which may be twice the value of a desired frequency. The clock signal may pass through the frequency divider16, which may be embodied as a flip-flop, thus generating the 4-phase clock signals I, IB, Q, and QB having the desired frequency.

Therefore, in order to generate the 4-phase clock signals, an additional frequency divider may be needed, which may complicate the construction of a circuit.

SUMMARY

Example embodiments provide a voltage controlled oscillator (VCO) which may be used in a VCO circuit employing a ring oscillator, which may be capable of stably generating quadrature phase (4-phase) clock signals even during a high-speed data communication while reducing power consumption.

Example embodiments may provide a voltage controlled oscillator which may include a first ring oscillation circuit that may have a plurality of delay cells and may output first differential oscillation signals; and a second ring oscillation circuit that may have a plurality of delay cells and may output second differential oscillation signals, wherein the delay cells of the first ring oscillation circuit may be respectively cross-coupled to the corresponding delay cells of the second ring oscillation circuit.

Each of the delay cells may include a differential amplification circuit that may output a first differential signal based on a first control signal; and a negative resistance circuit that may be connected in parallel to a pair of output terminals of the differential amplification circuit, may receive a second differential signal, may adjust a phase of the first differential signal based on a second control signal, and may then, output the first differential signal.

The differential amplification circuit may include a first resistor that may be connected between a first power source and a first node, and a second resistor that may be connected between the first power source and a second node; a pair of input transistors that may receive a differential input signal, where one of the input transistors may be connected between the first node and a third node and the other input transistor may be connected between the second node and the third node; and a bias transistor that may be connected between the third node and a second power source and may be controlled by the first control signal.

The negative resistance circuit may include a pair of first transistors that may be cross-coupled to each other; a pair of second transistors that may be respectively connected in parallel to the first transistors and may receive the second differential signal; and a third transistor that may change a resistance of the corresponding delay cell in order to adjust a delay time of the delay cell, in response to the second control signal.

One of the first transistors may be connected between the first node and a fourth node, the other first transistor may be connected between the second node and the fourth node, and a gate terminal of each of the first transistors may be connected to a drain terminal of the other first transistor. One of the second transistors may be connected between the first node and the fourth node and the other second transistor may be connected between the second node and the fourth node. The third transistor may be connected between the fourth node and the second power source.

The second differential signal may be output from each of the delay cells of the second ring oscillation circuit that may be respectively cross-coupled to the delay cells of the first ring oscillation circuit, or each of the delay cells of the first ring oscillation circuit that may be respectively cross-coupled to the delay cells of the second ring oscillation circuit. A delay time of each of the delay cells may be changed based on a voltage of one of the first and second control signals.

Each of the first and second ring oscillation circuits may comprise three delay cells. The first differential oscillation signals and the second differential oscillation signals may be 4-phase clock signals that may be phase shifted by 90 degrees with respect to one another.

Example embodiments may provide a voltage controlled oscillator which may include a first ring oscillation circuit that may have first, second, and third delay cells; and a second ring oscillation circuit that may have fourth, fifth and sixth delay cells, wherein the first delay cell may be cross-coupled to the fourth delay cell, the second delay cell may be cross-coupled to the fifth delay cell, and the third delay cell may be cross-coupled to the sixth delay cell.

Each of the first through sixth delay cells may comprise a differential amplification circuit that may output a first differential signal based on a first control signal; and a negative resistance circuit that may be connected in parallel to a pair of output terminals of the differential amplification circuit, may receive a second differential signal, may adjust a phase of the first differential signal based on a second control signal, and may output the first differential signal.

The differential amplification circuit may include a first resistor that may be connected between a first power source and a first node, and a second resistor that may be connected between the first power source and a second node; a pair of input transistors that may receive a different input signal, where one of the input transistors may be connected between the first node and a third node and the other input transistor may be connected between the second node and the third node; and a bias transistor that may be connected between the third node and a second power source and may be controlled by the first control signal, wherein the first and second nodes may be the output terminals of the differential amplification circuit.

The negative resistance circuit may include a pair of first transistors that may be cross-coupled to each other; a pair of second transistors that may be respectively coupled in parallel to the first transistors and receive the second differential signal; and a third transistor that may change a resistance of the corresponding delay cell in order to adjust a delay time of the delay cell, in response to the second control signal.

One of the first transistors may be connected between the first node and a fourth node, the other first transistor may be connected between the second node and the fourth node, and a gate terminal of each of the first transistors may be connected to a drain terminal of the other first transistor. One of the second transistors may be connected between the first node and the fourth node, and the other second transistor may be connected between the second node and the fourth node. The third transistor may be connected between the fourth node and the second power source.

The second differential signal may be output from a corresponding one of the delay cells that may be respectively cross-coupled to the first through sixth delay cells.

The delay time of each of the first through sixth delay cell may be changed based on a voltage of one of the first and second control signals.

Signals output from the first and second ring oscillation circuits may be 4-phase clock signals that may be phase shifted by 90 degrees with respect to one another.

DESCRIPTION OF EXAMPLE EMBODIMENTS

FIG. 2is a schematic block diagram of a general 3-stage ring oscillator20according to a related art. Referring toFIG. 2, the ring oscillator20may include a first delay cell21, a second delay cell22, and a third delay cell23.

Signals Xq31and Yq31, which may be output from the first delay cell21, may be supplied to the second delay cell22, and signals Xq32and Yq32, which may be output from the second delay cell22, may be supplied to the third delay cell23. Signals Xq33and Yq33, which may be output from the third delay cell23, may be fed back to the first delay cell21.

The first through third delay cells21,22, and23may form a feedback loop together, and may output oscillation signals that oscillate at desired frequency.

Each of the delay cells21,22, and23may have an output terminal. Signals output from the delay cells21,22, and23may have the same frequency but may be 120 degrees out of phase with one another.

That is, the signals Xq32and Yq32, which may be output from the second delay cell22, and the signals Xq33and Yq33, which may be output from the third delay cell23, may be respectively phase delayed by 120 degrees and 240 degrees with respect to the signals Xq31and Yq31, which may be output from the first delay cell21.

The ring oscillator20, which may have the three delay cells21,22, and23, may perform a high-speed oscillation operation in a circuit that requires a high-speed operation but may not be used in a circuit that requires 4-phase clock signals in a data communication.

FIG. 3is a schematic block diagram of a VCO30according to example embodiments. Referring toFIG. 3, the VCO30may include a first ring oscillation circuit100and a second ring oscillation circuit200.

The first ring oscillation circuit100may include a plurality of delay cells110,120, and130and the second ring oscillation circuit200may include a plurality of delay cells210,220, and230. The delay cells110through130of the first ring oscillation circuit100may be respectively cross-coupled to the corresponding delay cells210through230of the second ring oscillation circuit200.

More specifically, referring toFIG. 3, the first ring oscillation circuit100may include first through third delay cells110,120, and130, and the second ring oscillation circuit200may include fourth through sixth delay cells210,220, and230.

The first delay cell110may be cross-coupled to the fourth delay cell210, the second delay cell120may be cross-coupled to the fifth delay cell220, and the third delay cell130may be cross-coupled to the sixth delay cell230.

The first oscillation circuit100and the second oscillation circuit200may individually form a feedback loop. The first oscillation circuit100may output first differential frequency signals Q and QB which may have a desired frequency, and the second oscillation circuit200may output second differential frequency signals I and IB which may have the desired frequency.

The first differential frequency signals Q and QB which may be output from the first oscillation circuit100and the second differential frequency signals I and IB which may be output from the second oscillation circuit200may be 4-phase (or orthogonal phase) signals that may be phase shifted by 90 degrees with respect to one another.

More specifically, the third delay cell130may output the first differential frequency signals Q and QB, and the sixth delay cell230may output the second differential frequency signals I and IB that may be respectively phase shifted by 90 degrees with respect to the first differential frequency signals Q and QB.

The first differential frequency signals Q and QB may have the same frequency as the second differential frequency signals I and IB.

The constructions of and the linking relationship between the delay cells110through230will be described later with reference toFIG. 4.

FIG. 4is a circuit diagram of the first and fourth delay cells110and210illustrated inFIG. 3. In detail,FIG. 4may illustrate the relationship between the first delay cell110and the fourth delay cell210that may be cross-coupled to each other.

The delay cells110through230may have the same construction and operation. Thus, the constructions of and the linking relationship between the delay cells110through230will be described based on the first and fourth delay cells110and210.

Referring toFIGS. 3 and 4, the first delay cell110may include a first differential amplification circuit111and a first negative resistance circuit112.

The first differential amplification circuit111may include a first resistor R1, a second resistor R2, and first through third NMOS transistors N1, N2, and N3. The first resistors R1may be connected between a power source terminal VDD and a first node Q1, and the second resistor R2may be connected between the power source terminal VDD and a second node Q2.

The first NMOS transistor N1may be connected between the first node Q1and a third node Q3. The second NMOS transistor N2may be connected between the second node Q2and the third node Q3. The third NMOS transistor N3may be connected between the third node Q3and a ground terminal GND.

The first differential amplification circuit111may receive differential input signals Vinm and Vinp, and may output differential output signals Voutm and Voutp in response to a first control signal Vbias1.

In detail, the first differential amplification circuit111may control the frequencies of the differential output signals Voutm and Voutp based on the voltage of the first control signal Vbias1which may be supplied to a gate terminal of the third NMOS transistor N3, and may then output the differential output signals Voutm and Voutp.

The third NMOS transistor N3may be a bias transistor controlled by the first control signal Vbias1.

The frequencies of the differential output signals Voutm and Voutp, which may be output from the first differential amplification circuit111, may increase to be proportional to the voltage of the first control signal Vbias1.

The first negative resistance circuit112may include fourth through eighth NMOS transistors N4, N5, N6, N7, and N8, and may be connected in parallel to the first and second nodes Q1and Q2that may be a pair of output terminals of the first differential amplification circuit111.

The resistance of the first negative resistance circuit112may change in response to a second control signal Vcont1, which may result in changing a delay time of the first delay cell110.

The fourth NMOS transistor N4may be connected between the first node Q1and a fourth node Q4, and the fifth NMOS transistor N5may be connected between the second node Q2and the fourth node Q4. The fourth NMOS transistor N4may be cross-coupled to the fifth NMOS transistor N5.

That is, a gate terminal of the fourth NMOS transistor N4may be connected to a drain terminal of the fifth NMOS transistor N5, and a gate terminal of the fifth NMOS transistor N5may be connected to a drain terminal of the fourth NMOS transistor N4.

The sixth NMOS transistor N6may be connected in parallel to the fourth NMOS transistor N4, the seventh NMOS transistor N7may be connected in parallel to the fifth NMOS transistor N5, and the eighth NMOS transistor N8may be connected between the fourth node Q4and the ground terminal GND.

The sixth NMOS transistor N6and the seventh NMOS transistor N7may be transistors for receiving differential signals output from the fourth delay cell210which may be cross-coupled to the first delay cell110.

According to example embodiments, a gate terminal of the sixth NMOS transistor N6may receive one of the differential signals output from the fourth-delay cell210, e.g., a signal which may be output from a fifth node Q5. A gate terminal of the seventh NMOS transistor N7may receive the other differential signal output from the fourth delay cell210, e.g., a signal which may be output from a sixth node Q6.

The delay time of the first delay cell110may be embodied to be changed based on the first control signal Vbias1and/or the second control signal Vcont1.

The fourth delay cell210may include a second differential amplification circuit211and a second negative resistance circuit212.

The second differential amplification circuit211may include a third resistor R3, a fourth resistor R4, and ninth through eleventh NMOS transistors N9, N10, and N11. The third resistor R3may be connected between the power source terminal VDD and the fifth node Q5, and the fourth resistor R4may be connected between the power source terminal VDD and the sixth node Q6.

The ninth NMOS transistor N9may be connected between the fifth node Q5and a seventh node Q7, and the tenth NMOS transistor N10may be connected between the sixth node Q6and the seventh node Q7. The eleventh NMOS transistor N11may be connected between the seventh node Q7and the ground terminal GND.

The second differential amplification circuit211may receive the differential input signals Vinm and Vinp, and may output the differential output signals Voutm and Voutp in response to a third control signal Vbias2.

More specifically, the second differential amplification circuit211may control the frequencies of the differential output signals Voutm and Voutp based on the voltage of the third control signal Vbias2, which may be supplied to a gate terminal of the eleventh NMOS transistor N11, and then may output the differential output signals Voutm and Voutp.

The eleventh NMOS transistor N11may be a bias transistor controlled by the third control signal Vbias2.

The second negative resistance circuit212may include twelfth through sixteenth NMOS transistors N12, N13, N14, N15, and N16, and may be connected in parallel to the fifth and sixth nodes Q5and Q6that may be a pair of output terminals of the second differential amplification circuit211.

The resistance of the second negative resistance circuit212may change in response to a fourth control signal Vcont2, which may result in changing a delay time of the fourth delay cell210.

The twelfth NMOS transistor N12may be connected between the fifth node Q5and an eighth node Q8, and the thirteenth NMOS transistor N13may be connected between the sixth node Q6and the eighth node Q8.

The twelfth NMOS transistor N12may be cross-coupled to the thirteenth NMOS transistor N13. According to example embodiments, a gate terminal of the twelfth NMOS transistor N12may be connected to a drain terminal of the thirteenth NMOS transistor N13, and a gate terminal of the thirteenth NMOS transistor N13may be connected to a drain terminal of the twelfth NMOS transistor N12.

The fourteenth NMOS transistor N14may be connected in parallel to the twelfth NMOS transistor N12, and the fifteenth NMOS transistor N15may be connected in parallel to the thirteenth NMOS transistor N13.

The sixteenth NMOS transistor N16may be connected between the eighth node Q8and the ground terminal GND.

The fourteenth NMOS transistor N14and the fifteenth NMOS transistor N15may be transistors for receiving differential output signals from the first delay cell110which may be cross-coupled to the fourth delay cell210.

That is, a gate terminal of the fourteenth NMOS transistor N14may receive one of the differential output signals from the first delay cell110, e.g., a signal which may be output from the second node Q2, and a gate terminal of the fifteenth NMOS transistor N15may receive the other differential output signal from the first delay cell110, e.g., a signal which may be output from the first node Q1.

The delay time of the fourth delay cell210may be embodied to be changed based on the third control signal Vbias2and/or the fourth control signal Vcont2.

The constructions of and the linking relationship between the second delay cell120and the fifth delay cell220and the constructions of and the linking relationship between the third delay cell130and the sixth delay cell230, may be identical to the constructions and the linking relationship between the first delay cell110and the fourth delay cell210, which have been described above with reference toFIG. 4.

FIGS. 5A through 5Care timing diagrams illustrating the result of a simulation performed on a VCO according to example embodiments. In detail,FIG. 5Ais a timing diagram of signals Q and QB output from the first ring oscillation circuit100illustrated inFIG. 3.FIG. 5Bis a timing diagram of signals I and IB output from the second ring oscillation circuit200illustrated inFIG. 3.FIG. 5Cis a timing diagram illustrating the relationship between the phases of the signals Q and QB output from the first ring oscillation circuit100and the signals I and IB output from the second ring oscillation circuit200.

Referring toFIGS. 3 through 5C, the VCO30illustrated inFIG. 3may accurately output 4-phase clock signals. According to example embodiments, the signals Q and QB, which may be output from the first ring oscillation circuit100, and the signals I and IB, which may be output from the second ring oscillation circuit200, may be respectively phase shifted by 90 degrees with respect to one another.

As described above, a VCO according to example embodiments may not only output a high-speed oscillation frequency suitable for high-speed transmission of data but may also generate 4-phase frequency signals.