Method of making self-aligned silicide CMOS transistors

The present invention includes forming gate structures having a nitride cap on the substrate. An ion implantation is used to dope ions into the substrate to form the lightly doped drain (LDD) structures. An oxide layer is formed on the gate structures. Subsequently, the oxide layer is etched back to form oxide spacers on the side walls of the gate structures. Next, an ion implantation with a high dose is carried out to dope nitrogen ions into the oxide spacers, the cap silicon nitride and the silicon substrate. The cap silicon nitride layer is then removed. Then, a refractory or noble metal layer is sputtered on the substrate, nitride doped oxide spacers and the gates. A first step thermal process is performed to form SALICIDE and polycide. Next, an ion implantation is utilized to dope ions into the SALICIDE and polycide films. A second step thermal process is employed to form shallow source and drain junction.

FIELD OF THE INVENTION 
The present invention relates to semiconductor devices, and more 
specifically, to complementary metal-oxide-semiconductor (CMOS) devices. 
BACKGROUND 
The semiconductor industry has been advanced to the field of Ultra Large 
Scale Integrated (ULSI) technologies. The fabrication of the 
metal-oxide-semiconductor transistor also follows the trend. As the size 
of the devices is scaled down, the fabrication meets more issues than ever 
for these recent years. For example, high performance CMOS technology has 
been developed for achieving high packing density wafer for ultra large 
scale integrated (ULSI) circuits. The cost of the scaled devices is the 
parasitic effect which will degrade the RC delay and source and drain 
series resistance. 
The use of a hot carrier is another important issue to degrade the 
performance of the devices, although the supply voltage is lowered to 2.5 
V for 0.25 micron MOS. In order to provide reliable MOSFETs, many 
structures of the MOSFET have been proposed. The prior art has reported 
that an ion implantation with high dose nitrogen for doping into the 
polysilicon gate and silicon substrate will improve the performance of the 
deep sub-micron devices. For example, one prior art approach to improve 
the hot carrier resistance is to use a NICE (nitrogen implantation into 
CMOS gate electrode and source and drain) structure. The NICE structure is 
proposed by T. Kuroi, et al., in IEDM Tech. Dig., p325, 1993, entitled 
"Novel NICE (Nitrogen Implantation into CMOS Gate Electrode and Source and 
Drain) Structure for High Reliability and High Performance 0.25 .mu.m Dual 
Gate CMOS". In the structure, the surface channel PMOS with the p+ poly 
gate has been investigated in place of the buried channel with n+ poly 
gate due to the superior short channel behavior. This NICE structure 
exhibits nitrogen implanted n+ and p+ gates and nitrogen implanted p+ 
source and drain. The hot carrier problem will be effectively improved by 
incorporating nitrogen into the gate oxide with nitrogen implantation on 
the polysilicon gate. 
However, the high dose (higher than 4E15 atom/cm.sup.2) nitrogen 
implantation will cause the drastic increase in sheet resistance of 
poly-Si gate, therefore the operation speed of devices will be degraded. 
Please refer to the article "Impact of Nitrogen Implantation on Highly 
Reliable Sub-Quarter-Micron Metal Oxide Field-Effect Transistors with 
Lightly Doped Drain Structure", S. Shimizu, et al., Jpn. J. Appel. Phys., 
vol. 35, p.802, 1996. The hot carrier degration in LDD n-MOS is caused by 
the generation of interface states or electron traps in the sidewall 
spacers. For the NICE structure, the nitride gate oxide under the gate 
electrode is not effective in suppressing the generation of interface 
state electron traps. Thus, S. Shimizu proposed a NISW (nitrogen 
implantation in the silicon oxide sidewall spacers) structure to solve the 
aforesaid issue. The issue can be suppressed due to the fact that the 
dangling bonds and weakened bonds formed at the interface between the 
sidewall spacers and the silicon substrate are occupied by the segregated 
nitrogen atoms. 
In order to increase the operation speed, the self-aligned metal silicided 
process has been developing for many years. The technology is used to 
achieve the purpose of reducing the resistance of the gate, the source and 
drain. The fast operation speed is a basic requirement for ultra-short 
channel MOSFET. M. T. Takagi, et al. provide a method of forming silicided 
process in IEDM, Tech. Dig., p.455, 1996. The self-aligned silicided 
contact technology is the popular method of reducing the resistance of the 
gate, drain and source electrode. For example, a metal layer, such as Ti, 
Pt, Co, W, Ni, Cr, etc. is sputtered on the substrate and the gate. Then, 
a rapid thermal annealing (RTA) at 350 to 700 degrees centigrade is 
performed to react the metal with the gate and the substrate. Then, a 
stripping step is used to remove the non-reactive metal on the sidewall 
spacers of the gate. Therefore, the silicide layers are self-aligned 
formed on gate, source and drain regions. 
Further, an article reported that the spacers having oxynitride can 
suppress the short channel effects or reverse short channel effect. Please 
refer to the article proposed by P. G. Y. Tsui, et al., in IEDM Tech. 
Dig., p.501, 1994, entitled "Suppression of MOSFET Reverse Short Channel 
Effect by N.sub.2 O Gate Poly Reoxidation Process". 
SUMMARY 
In accordance with the present invention, a sub-micron CMOS device with 
shallow source and drain junction is provided. In one embodiment, an 
N-well and a P-well are created in a substrate using suitable processes. 
Subsequently, a thin oxide layer is formed on the substrate to act as a 
gate oxide. An undoped polysilicon layer is deposited by chemical vapor 
deposition on the gate oxide layer. Next, a silicon nitride layer is 
successively formed on the polysilicon layer to act as an anti-reflective 
coating (ARC). Then, the undoped polysilicon layer, ARC layer, and the 
oxide layer are patterned to form ultra short channel polysilicon gates on 
the P-well and N-well, respectively. 
An ion implantation is used to dope ions into the substrate to form the 
lightly doped drain (LDD) structures. An oxide layer is formed on the gate 
structures. Subsequently, the oxide layer is etched back to form oxide 
spacers on the sidewalls of the gate structures. Next, an ion implantation 
with high dose is carried out to dope nitrogen ions into the oxide 
spacers, the cap silicon nitride and the silicon substrate. The nitride 
doped oxide spacers are used to suppress the reverse short channel effect 
or short channel effect. The cap silicon nitride layer is then removed to 
expose the gates. Then, a refractory or noble metal layer is sputtered on 
the substrate, nitride doped oxide spacers and the gates. 
A first step thermal process is performed at a lower temperature to react 
the metal with the polysilicon and the silicon to form silicide layers. 
Then, a strip step is used to remove the non-reactive metal on the oxide 
spacers. Next, an ion implantation is utilized to dope ions into the 
silicide layers. A second step thermal process is employed to form the 
ultra-shallow source and drain junctions by using the silicide layers as 
the diffusion source. Preferably, the thermal process having a high 
temperature is completed by using rapid thermal process.

DETAILED DESCRIPTION 
The present invention proposes a method to fabricate the CMOS transistors 
with a self-aligned silicide structure. The detailed description can be 
understood as follows and in conjunction with the accompanying drawings. 
Referring to FIG. 1, a single crystal substrate 2 with a &lt;100&gt; 
crystallographic orientation is used for the preferred embodiment. The 
substrate includes a plurality of field oxide regions 4 and twin wells 
(P-well and N-well) previously formed therein. In this embodiment, thick 
field oxide (FOX) regions 4 are created for the purposes of isolation. 
Typically, the FOX regions 4 are created via a first photoresist and dry 
etching to define a silicon nitride-silicon dioxide composite layer. After 
the photoresist is removed and wet cleaned, thermal oxidation in an oxygen 
ambient is performed to form the FOX regions 4, to a thickness of about 
3000-8000 angstroms. The silicon nitride layer is then typically removed 
using hot phosphoric acid solution while the silicon dioxide is removed by 
using diluted HF or BOE solution. 
A thin oxide layer 6 is formed on the substrate 2 to act as a gate oxide. 
In the preferred embodiment, the gate oxide layer 6 is composed of silicon 
oxide that is formed by using an oxygen-steam ambient, at a temperature 
between about 800 to 1100 degrees centigrade. The gate oxide layer 6 can 
also be the silicon dioxide formed using a chemical vapor deposition 
process, with a tetraethylorthosilicate (TEOS) source, at a temperature 
between about 600 to 800 degrees centigrade and a pressure of about 0.1 to 
10 torr. In the preferred embodiment, the thickness of the gate oxide 
layer 6 is about 15-200 angstroms. 
Referring to FIG. 2, after the silicon oxide layer 6 is formed, undoped 
polysilicon layers 8 are deposited by chemical vapor deposition on the 
gate oxide layer 6. Next, a silicon nitride layer 10 is successively 
formed on the polysilicon layer 8 to act as an anti-reflective coating 
(ARC). Then, the undoped polysilicon layer 8, ARC layer 10, and the oxide 
layer 6 are patterned to form ultra short channel polysilicon gate 
structures on the P-well and N-well, respectively. 
Now referring to FIG. 3, an ion implantation is used to dope ions into the 
substrate such that the lightly doped drain (LDD) structures 12 are formed 
adjacent to the gate structures. Preferably, the dopant of the LDD 
implantation can be selected from the group of arsenic, phosphorus and the 
combination thereof for the nMOS devices, and boron or BF.sub.2 and the 
combination thereof for the PMOS devices, respectively. The energy and 
dosage of the implantation are about 5 to 60 KeV, 5E12 to 1E14 
atoms/cm.sup.2, respectively. 
As shown in FIG. 4, an oxide layer 14 is formed on the gate structures 
consisting of the gate 8 and the gate oxide 6. Subsequently, the oxide 
layer 14 is etched back by using an anisotropical etching process. Thus, 
oxide spacers 14 are formed on the sidewalls of the gate structures. 
Next, an ion implantation with high dose is carried out to dope nitrogen 
ions into the oxide spacers 14, the cap silicon nitride 10 and the silicon 
substrate, as shown in FIG. 5. In this case, the energy of the ion 
implantation is about 0.5 to 100 KeV, and the dosage of the ion 
implantation is about 1E14 to 1E16 atoms/cm.sup.2. The nitride doped oxide 
spacers 14 are used to suppress the reverse short channel effect or short 
channel effect. Thus, the performance of the CMOS will be enhanced. 
Turning to FIG. 6, the cap silicon nitride layer 10 is removed to expose 
the gates 8. This can be completed by means of hot phosphorus acid 
solution. Then, self-aligned silicide (SALICIDE) technique is introduced 
to reduce the resistance of the gate 8 and source and drain. First, a 
refractory or noble metal layer 16, such as Ti, Pt, Co, W, Ni, Pd, Cr, 
etc. is sputtered on the substrate 2, nitride doped oxide spacers 14 and 
the gates 8. 
Referring to FIG. 7, a first step thermal process with lower temperature is 
performed at about 300 to 700 degrees centigrade in N.sub.2 ambient to 
react the metal with the silicon and the polysilicon to form silicide 
layers on the gate, source and drain. Then, a strip step is used to remove 
non-reactive metal on the nitride doped oxide spacers 14. Therefore, the 
silicide 18, and polycide 20 are self-aligned formed on the gates and the 
substrates, respectively. Next, an ion implantation is utilized to dope 
ions into the silicide 18 and polycide 20 in order to make the source and 
drain regions for subsequent steps. The dopant of the ion implantation 
includes arsenic, phosphorus or the combination thereof for the nMOS 
devices, and boron, BF.sub.2 or the combination thereof for the PMOS 
devices, respectively. In a preferred embodiment, the implantation is 
performed with an energy and dosage of about 0.5 to 120 KeV and 5E14 to 
5E16 atoms/cm.sup.2, respectively. 
The next step according to the present invention is, turning to FIG. 8, a 
second step thermal process for silicidation anneal is employed in N.sub.2 
ambient to form shallow source and drain junctions 22 adjacent to the LDD 
12. Preferably, the thermal process is completed by using rapid thermal 
process with relatively high temperature compared to the first step 
thermal process. The temperature of this step is about 750 to 1150 degrees 
centigrade. The silicide 18 and polycide 20 films are used as a diffusion 
source for forming the shallow source and drain junction 22. 
As can be appreciated from the above disclosure, the present invention 
provides the following advantages: (1) The device operation speed can be 
improved by using the self-aligned silicide technology; (2) short channel 
effect or reverse channel effect will be suppressed by the nitride doped 
oxide spacers; and (3) the sheet resistance of the gate can be sustained 
by using the cap nitride layer as a hard mask or barrier for nitrogen 
implant. 
As is understood by a person skilled in the art, the foregoing embodiments 
of the present invention are illustrative of the present invention rather 
than limiting of the present invention. The description is intended to 
cover various modifications and similar arrangements included within the 
spirit and scope of the appended claims, the scope of which should be 
accorded the broadest interpretation so as to encompass all such 
modifications and similar structure. Accordingly, while the preferred 
embodiment of the invention has been illustrated and described, it will be 
appreciated that various changes can be made therein without departing 
from the spirit and scope of the invention.