Methods and apparatus for resource sharing in a programmable interrupt controller

Efficient techniques are described for identifying active interrupt requests to improve performance and reduce power requirements in a processor system. A method to identify active sampled interrupt requests begins with scanning groups of the sampled interrupt requests one group at a time to identify an active interrupt request in any scanned group. A group of interrupt requests is an M/R priority of N sampled interrupt requests, M is the number of priority levels, and R is a resource sharing factor. A group selection circuit is updated to a new group in response to having identified an active interrupt request to improve the latency in processing high priority interrupt requests. Also, groups having active interrupt requests may be identified by early detection or look ahead circuitry. The scanning of groups of interrupt requests may be stopped until the next interrupt request sample point has been reached to reduce power utilization.

FIELD OF THE DISCLOSURE

The present disclosure relates generally to the field of programmable interrupt controllers and, in particular, to prioritized resource sharing interrupt selection logic in a programmable interrupt controller.

BACKGROUND

Many portable products, such as cell phones, laptop computers, personal data assistants (PDAs) and the like, utilize a processing system that executes programs, such as, communication and multimedia programs. A processing system for such portable products may include multiple processors, memory for storing instructions and data, controllers, peripheral devices, such as communication interfaces, and fixed function logic blocks configured, for example, on a single chip. Many of these peripheral devices utilize interrupts to notify an appropriate processor of an event that has occurred or that data is to be transferred between the peripheral device and memory. With processing systems having a large number of functions and associated system elements, a large number of interrupts have to be handled, many of which have to be processed to meet strict real time requirements. With such systems, it becomes increasingly important to efficiently service the large number of interrupts at low power drain to reduce overall energy consumption. Many personal computers are also being developed that utilize a large number of interrupts that must be efficiently serviced to support high performance operations.

In prior systems, relatively few interrupts and a small number of priority levels were generally supported by a programmable interrupt controller that interfaced to a single processor. However, current and planned future systems have grown in complexity causing an increase in the number of interrupts, priority levels, and interfacing processors required to meet product requirements. With this growth in system complexity, the number of interrupts having short or time critical, real time requirements, has also increased.

SUMMARY

Among its several aspects, the present disclosure recognizes that with the number of interrupts increasing, there is an advantage to provide more efficient methods and apparatus for identifying active interrupt requests may improve performance and reduce power requirements in a processor system. To such ends, one embodiment addresses a method to identify active interrupt requests. A group of interrupt requests selected by a group selection circuit is scanned to identify an active interrupt request in any scanned group. The group selection circuit is updated to a new group.

Another embodiment addresses an apparatus for selecting interrupt requests including a group selection circuit, a priority level to interrupt request mapping unit, and a priority level interrupt request selection unit. The group selection circuit generates a sequence of group selection outputs, wherein a group selection output identifies a group of interrupt requests. The priority level to interrupt request mapping unit generates enable signals for interrupt requests belonging to select groups of interrupt requests according to the interrupt requests' assigned interrupt priority levels and the sequence of group selection outputs. The priority level interrupt request selection unit selects one or more active interrupt requests for output in response to the enable signals.

Another embodiment addresses a method for selecting interrupt requests. A sequence of group selection outputs is generated, wherein a group selection output identifies a group of interrupt requests. Enable signals are generated for interrupt requests belonging to select groups of interrupt requests according to the sequence of group selection outputs. One or more active interrupt requests are selected for output in response to the enable signals.

Another embodiment addresses a method to identify an active interrupt request. A highest priority level group is identified as having an active interrupt request from among a plurality of priority level groups of interrupt requests to process the active interrupt request. Priority level groups that do not have an active interrupt request are skipped.

Another embodiment addresses a method for selecting interrupt requests. A group selection output is generated from a pattern generator to identify a group of interrupt requests. The method detects whether there is an active interrupt request in the identified group of interrupt requests. The pattern generator is set to operate in response to a first update clock having a first frequency upon detecting there is an active interrupt request. The pattern generator is set to operate in response to a second update clock having a second frequency upon detecting there is not an active interrupt request, wherein the second frequency is greater than the first frequency.

DETAILED DESCRIPTION

The detailed description set forth below in connection with the appended drawings is intended as a description of various exemplary embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In some instances, well known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present invention.

FIG. 1illustrates an exemplary wireless communication system100in which an embodiment of the invention may be advantageously employed. For purposes of illustration,FIG. 1shows three remote units120,130, and150and two base stations140. It will be recognized that common wireless communication systems may have many more remote units and base stations. Remote units120,130,150, and base stations140which include hardware components, software components, or both as represented by components125A,125C,125B, and125D, respectively, have been adapted to embody the invention as discussed further below.FIG. 1shows forward link signals180from the base stations140to the remote units120,130, and150and reverse link signals190from the remote units120,130, and150to the base stations140.

InFIG. 1, remote unit120is shown as a mobile telephone, remote unit130is shown as a portable computer, and remote unit150is shown as a fixed location remote unit in a wireless local loop system. By way of example, the remote units may alternatively be cell phones, pagers, walkie talkies, handheld personal communication system (PCS) units, portable data units such as personal data assistants, or fixed location data units such as meter reading equipment. AlthoughFIG. 1illustrates remote units according to the teachings of the disclosure, the disclosure is not limited to these exemplary illustrated units. Embodiments of the invention may be suitably employed in any device having a plurality of interrupts.

FIG. 2shows a processing system200with an exemplary programmable interrupt controller (PIC)204which may suitably be employed in components125A-125D ofFIG. 1. The processing system200also includes memory205, processor subsystem206, which may be one or more of a plurality of processors, and K bus devices2080-208K-1. Other system elements, such as peripheral devices, are not shown for reasons of clarity in showing aspects of the PIC204in accordance with the present invention. The actual number of processors and bus devices required for a particular application may vary depending upon processing requirements and design constraints.

The shared bus interconnect212manages bus traffic, provides connection paths between one or more processors, bus devices and their associated peripheral devices, and memory, and supplies control and data signals214to the PIC204. A bus device, such as a bus master or bus slave, may be a memory controller, a bridge device for interconnecting to another bus interconnect device, a peripheral device such as a hard disk controller, a universal serial bus (USB) controller, an interactive display device, a radio device coupling a controller to a transmitter and receiver, or the like. Bus devices may utilize direct memory access (DMA) techniques for reading or writing data to memory205. The processing system200may be implemented using application specific integrated circuit (ASIC) technology, field programmable gate array (FPGA) technology, or other programmable logic, discrete gate or transistor logic, or any other available technology suitable for an intended application.

The processor subsystem206, for example, may be configured to execute instructions under control of a program stored on a computer readable storage medium either directly associated locally with the processor, such as memory205, or accessible through the shared bus interconnect212from a bus device. The storage medium may include random access memory (RAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), flash memory, read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), compact disk (CD), digital video disk (DVD), other types of removable disks, or any other suitable storage medium.

The programmable interrupt controller (PIC)204comprises an interrupt controller and control register unit (ICCR)216, a winning interrupt searcher unit218, and an output selection unit220. The control and data signal214may be utilized to load configuration registers and parameters in the ICCR unit216that are required to operate the PIC204. The configuration registers are used, for example, to specify a priority level for each interrupt, as described in further detail below. The winning interrupt searcher218receives interrupt request input (IRQin(N-1:0)) signals222from various system components, including peripheral devices, bus devices, and processors. In the winning interrupt searcher218, the IRQin(N-1:0) signals222are sampled, prioritized according to priority levels as programmed in the configuration registers, and the highest priority received interrupt is identified, by an interrupt identification (id) output224. The interrupt id output224is coupled to the output selection unit220. The output selection unit220uses the interrupt id output224to identify the associated interrupt, from the IRQin(N-1:0) signals222. The identified interrupt is coupled to interrupt processing logic circuit226of the processor subsystem206, for example. Interface signals230and232may be coupled to other interrupt processing logic circuits in a multiprocessor system. For example, an identified interrupt may be broadcast to all processor subsystems or may be selectively distributed to one or more of the processor subsystems in a multiprocessor system.

FIG. 3illustrates a first exemplary N×M×R programmable interrupt controller (PIC) circuit300which may suitably be used for the programmable interrupt controller204shown inFIG. 2, with N interrupts, M priority levels, and a resource sharing factor R. The N×M×R PIC circuit300comprises an interrupt controller and control register (ICCR) unit304, a winning interrupt searcher306, and an output selection unit308. The ICCR unit304comprises a priority level to interrupt request mapping unit305having, for example, a configuration register (CR)310, decoders311, and a multiplexer (Mux) unit312, a group selection circuit314, and a resource sharing controller316. The winning interrupt searcher306comprises a sampler324, a priority level IRQ selection unit326, and a winner selection circuit328. The output selection unit308comprises a storage and control circuit334.

The N×M×R PIC circuit300may be programmed by loading the CR310with data values that assign each of the N interrupts, IRQin(N-1:0)222, with one of the priority levels M, with M=0 being the highest priority and M-1being the lowest priority. For example, interrupt0may be assigned to priority level0by programming a binary coded zero data value in the portion of the CR310associated with interrupt0. Interrupt set up software uses knowledge of the interrupt processing hardware and modes of operation to intelligently assign interrupt requests to specific groupings of interrupts at higher or lower priority levels by loading the CR310with such assignment based in part on interrupt response time requirements. For example, interrupt requests are assigned to a priority level based on an estimated average time to respond to a priority level interrupt request in a system operating environment. It is also appreciated that the priority levels may be organized in various ways, for example, in a reverse order with the M-1priority level being the highest priority level and M=0 being the lowest priority. The data values loaded in the CR310may also be encoded using different encoding formats, as may be appropriate for a particular implementation. Alternatively, a bit map per group may be loaded in the configuration registers310removing the need for decoders311. The resource sharing factor R may also be programmed into the resource sharing controller316or R may be fixed by design.

In operation, the IRQin(N-1:0) signals222are sampled at the beginning of every period of a sample clock (Sclock)323and stored in the sampler324as up to N pending interrupts. The sample clock323may be a gated clock or a controlled sampling signal. The sampler324outputs N sampled IRQ signals325which are coupled to the priority level IRQ selection unit326. The N sampled IRQ signals325are prioritized and scanned in the priority level IRQ selection unit326according to their preset priority levels stored in the configuration registers (CR)310. The encoded data values stored in the CR310are decoded by decoders311whose output signals are coupled to the Mux unit312. The Mux unit312produces N*(M/R) enable signals315that are used to control the priority level IRQ selection unit326to select interrupts, for example, in groups of one or more priority levels to produce prioritized and selected pending interrupts327. The Mux unit312selects output signals of the decoders311to produce N*(M/R) enable signals315in response to a group selection output317provided from the group selection circuit314, as described in further detail below.

In one embodiment, the group selection circuit314may be configured as a counter which generates count values. The count values may be used to represent one or more groups of priority levels that are to be scanned for pending interrupts. Also, the group selection circuit314group selection output317may be updated to the next count value every period of an update clock (Uclock)331, for example. The update clock331may be a gated clock or a controlled update signal. Generally, Uclock331has a frequency that is R*frequency of Sclock323, where R is the resource sharing factor. For example, with a resource sharing factor R of four, the M priority levels are split into M/R=M/4 groups of priority levels with a count value associated with each group of priority levels. In this fashion, the capability is provided to sequence through all of the M priority levels every period of the Sclock323by clocking the group selection circuit314in synchronism with the Uclock331. In another embodiment, the group selection circuit314may be a pattern generator which generates the group selection output317according to a predetermined pattern which may be selectable under program control. Alternatively, and as described in more detail below, the group selection circuit317may adaptively generate the group selection output317to select groups having one or more active interrupt requests and skip groups not having an active interrupt request.

Advantageously, multiple modes of operating the N×M×R PIC300are provided by the resource sharing controller316. In a first operating mode, N sampled interrupt requests are checked across all of the M priority levels to determine a highest priority interrupt. In a second operating mode, reduced latency is provided for processing high priority interrupts. In a third operating mode, the N×M×R PIC300may be operated with low power utilization. In a fourth mode of operation, an early detection circuit controls the group selection circuit314to adaptively generate the group selection output317to select groups having one or more active interrupt requests and skip groups not having an active interrupt request. In a fifth mode of operation, the sampled interrupt requests are examined and the group selection circuit314is loaded with the highest priority group having an active interrupt request thereby adaptively selecting groups based on the order interrupt requests are received. In a sixth mode of operation, the number of priority levels that are checked each Uclock331period may be varied. These modes of operations are described in further detail below.

Prioritized and selected pending interrupts327are coupled to the winner selection circuit328. The winner selection circuit328selects, among the prioritized and selected pending interrupts327, the highest priority selected pending interrupt and outputs an encoded interrupt request input (IRQin) identification number (Id) on interrupt Id output329to identify the highest priority interrupt. Additional information associated with the winning interrupt, such as, interrupt status or fast interrupt notification, is output on interrupt status330. The output selection unit308receives the interrupt Id output329and the interrupt status330and saves the state of these signals in the storage and control circuit334which may be configured with a first-in-first-out (FIFO) storage device. The storage and control circuit334provides a buffered interrupt Id output333and buffered interrupt status output337coupled to interrupt processing logic, such as the interrupt processing logic226ofFIG. 2. The interrupt processing logic226responds with an interrupt processed acknowledgement signal339which initiates clearing the stored state of the selected interrupt output329and interrupt status330. Signal339is also used in the resource sharing controller316to generate a clear signal335to the sampler324in the winning interrupt searcher306to clear the saved state of the processed interrupt request. Any further pending interrupts held in the sampler324may be then processed.

FIG. 4illustrates a first embodiment of a prioritized interrupt selection circuit400with R=M suitable for use in the N×M×R PIC ofFIG. 3. The prioritized interrupt selection circuit400comprises a winner selection unit401, a resource sharing circuit404, a resource sharing controller405, a group counter406, a configuration register408comprised of N priority level registers4080-408N-1, N priority level decoders4200-420N-1, and R-to-1 muxes4300-430N-1. The prioritized interrupt selection circuit400is shown with N sampled interrupt inputs IRQin(N-1:0)402received from a sampler, such as sampler324ofFIG. 3, and with one resource sharing circuit404. The N interrupts are assigned to priority levels through the use of the configuration register408. For example, in a system with N interrupts and M priority levels, where N and M are both a power of 2, the priority level may be encoded in log(M)-bits. For N interrupts there are N encoded priority levels that are loaded into the N priority level registers4080-408N-1to assign each of the N interrupts with a priority level. While the circuit400ofFIG. 4is based on N and M being a power of 2, the circuit400is not so limited and N and M need not be restricted to power of 2 values.

The priority level decoders4200-420N-1decode the priority levels stored in their associated priority level registers4080-408N-1producing M-1inactive outputs and one active output from each decoder. The one active output from each decoder indicates the priority level for the associated interrupt. The group counter406is a log(R)-bit counter that is clocked, for example, by Uclock423and controlled by the resource sharing controller405. The group counter406generates multiplexer select signals433that are used by the N muxes4300-430N-1to select an output from each of the decoders4200-420N-1to be used as enable signals436coupled to AND gates4040-404N-1of the resource sharing circuit404. The multiplexer select signals433correspond to count values of the group counter406with each count value, in this example, representing a priority level. A count value of zero would enable priority level L0and a count value of one would enable priority level L1. The group counter406counts through the priority levels until priority level LM-1is enabled. For example, by loading all zeros into the N priority level registers4080-408N-1, all N interrupts are assigned to priority level zero. The group counter406having a count value of zero, would generate multiplexer select signals433that cause the multiplexers4300-430N-1to select the priority level zero (L0) output of each of the decoder and, for this example, generate N active enable signals436. Generally, all N interrupts are not mapped to a single priority level, but rather distributed among the M priority levels according to a system priority specification. Other modes of operating the prioritized interrupt selection circuit400are described in further detail below. The output of the resource sharing circuit404is coupled to the winner selection unit401having one internal priority level winner selection circuit445and a final winner select circuit446. The final winner select circuit446outputs a highest priority interrupt Id signal447and an associated interrupt status signal448.

FIG. 5illustrates a second embodiment of a prioritized interrupt selection circuit500with R=M/2 suitable for use in the N×M×R PIC ofFIG. 3. The prioritized interrupt selection circuit500comprises a winner select unit501, resource sharing circuits503and504, a resource sharing controller505, a group counter506, a configuration register508comprised of N priority level registers5080-508N-1, N priority level decoders5200-520N-1, and R-to-1 muxes5300-530N-1and5310-531N-1. The prioritized interrupt selection circuit500is shown with N sampled interrupt inputs IRQin(N-1:0)502received from a sampler, such as sampler324ofFIG. 3, and with two resource sharing circuits503and504. The N interrupts are assigned to priority levels through the use of the configuration register508. For example, in a system with N interrupts and M priority levels, N and M both a power of 2, the priority level may be encoded in log(M)-bits. For N interrupts there are N encoded priority levels that are loaded into the N priority level registers5080-508N-1to assign each of the N interrupts with a priority level. While the circuit500ofFIG. 5is based on N and M being a power of 2, the circuit500is not so limited and N and M need not be restricted to power of 2 values.

The priority level decoders5200-520N-1decode the priority levels stored their associated priority level registers5080-508N-1producing M-1inactive outputs and one active output from each decoder. The one active output from each decoder indicates the priority level for the associated interrupt. The group counter506is a log(R)-bit counter that is clocked, for example, by Uclock523and controlled by the resource sharing controller505. The group counter506generates multiplexer select signals533that are used by the R-to-1 muxes5300-530N-1and5310-531N-1to select an output from each of the decoders5200-520N-1to be used as enable signals536coupled to AND gates5030-503N-1of the resource sharing circuit503and to AND gates5040-504N-1of the resource sharing circuit504. The multiplexer select signals533correspond to count values of the group counter506with each count value representing two priority levels. A count value of zero would enable priority levels L0and L1and a count value of one would enable priority levels L2and L3. The counter continues to count until priority levels LM-2and LM-1are enabled. For example, by loading either a zero value or a one value into each of the N priority level registers5080-508N-1, each of the N interrupts would be assigned to priority level zero or priority level one as loaded into the configuration register508. The group counter506having a count value of zero, would generate multiplexer select signals533that cause the multiplexers5300-530N-1to select the priority level zero (L0) output of the decoders5200-520N-1and cause multiplexers5310-531N-1to select the priority level one (L1) output of each of the decoders5200-520N-1and, for this example, generate 2*N active enable signals536. Generally, all N interrupts are not mapped to one or two priority levels, but rather distributed among the M priority levels according to a system priority specification. Other modes of operating the prioritized interrupt selection circuit500are described in further detail below. The outputs of the resource sharing circuits503and504are coupled to the winner selection unit501having two internal priority level winner selection circuits545and a final winner select circuit546. The final winner select circuit546outputs a highest priority interrupt Id signal547and an associated interrupt status signal548.

FIG. 6illustrates an exemplary first timing diagram600for a resource sharing interrupt controller using the prioritized interrupt selection circuit500ofFIG. 5. In this example, there are eight priority levels, M=8, and R is equal to M/2=4 with the N×8×4 interrupt controller operating in a first operating mode. Sclock604may suitably represent the timing of Sclock323ofFIG. 3. Uclock606may suitably represent the timing of Uclock523ofFIG. 5. Uclock606is shown operating at a frequency that is R=4 times the frequency of Sclock604. Counter output608may suitably represent the timing of group counter506multiplexer select signals533. Counter output608sequences through count values representing two priority levels at a time at the sample points indicated by sample point indication610. The counter output608, in this example, provides count values that are associated with priority levels, such as, (00=L0,L1), (01=L2,L3), (10=L4,L5), and (11=L6,L7). The sample point indication610represents the points in time the N interrupts, such as IRQin(N-1:0)222ofFIG. 3, are sampled in synch with the rising edge of Sclock604in a sampler, such as sampler324ofFIG. 3.

At the first sample point612, a priority level4(L4) interrupt and a priority level7(L7) interrupt are active and sampled. With the group counter506at a first count value (0,0)614, priority levels L0and L1inputs to the muxes5300-530N-1and5310-531N-1are selected. Any sampled active interrupt that was assigned to priority levels L0or L1would be enabled to pass through the resource sharing circuits503and504. Since in this example no active L0or L1interrupts were sampled, the group counter506is updated to a second count value (0,1)615. At the second count value (0,1)615, priority levels L2and L3inputs to the muxes5300-530N-1and5310-531N-1are selected. Any interrupt active that was assigned to priority levels L2or L3would be enabled to pass through the resource sharing circuits503and504. Since in this example no active L2or L3interrupts were sampled, the group counter506is updated to a third count (1,0) value616. At the third count value (1,0)616, priority levels L4and L5inputs to the muxes5300-530N-1and5310-531N-1are selected. Any active interrupt that was assigned to priority levels L4or L5would be enabled to pass through the resource sharing circuits503and504. Since in this example, there is an active L4interrupt that was sampled, that particular L4interrupt is passed through the resource sharing circuit503to one of the two internal priority level winner selection circuits545. Since the priority level L4interrupt is the highest priority level interrupt identified at this point in the count sequence, the final winner selection circuit546outputs a final winner620identifying, at this time, the highest priority interrupt as the L4interrupt.

In this first operating mode, the group counter506is updated to a fourth count (1,1) value617. At the fourth count value (1,1)617, priority levels L6and L7inputs to the muxes5300-530N-1and5310-531N-1are selected. Any active interrupt that was assigned to priority levels L6or L7would be enabled to pass through the resource sharing circuits503and504. Since in this example, there is an active L7interrupt that was sampled, that particular L7interrupt is passed through the resource sharing circuit504to one of the two internal priority level winner selection circuits545. Since the priority level L7interrupt is the highest priority level interrupt identified at this point in the count sequence, the final winner selection circuit546outputs a final winner620identifying, at this time, the highest priority interrupt as the L7interrupt. The group counter506then wraps back to the initial count value (0,0) and the process continues. In the first operating mode, N sampled interrupt requests are checked across all of the M priority levels to determine a highest priority interrupt

FIG. 7illustrates an exemplary timing diagram700for a reduced latency interrupt controller using the prioritized interrupt selection circuit500ofFIG. 5. In this example, there are eight priority levels, M=8, and R is equal to M/2=4 with the N×8×4 interrupt controller operating in a second operating mode to provide reduced latency sampling of the highest priority interrupts. Reference clock704is provided for timing reference purposes. Uclock706may suitably represent the timing of Uclock523ofFIG. 5. Uclock706is shown operating at a frequency that is R=4 times the frequency of the reference clock704. Counter output708may suitably represent the timing of group counter506multiplexer select signals533. Counter output708sequences through counts representing two priority levels at a time at the sample points indicated by sample point indication710. The counter output708, in this example, provides count values that are associated with priority levels, such as, (00=L0,L1), (01=L2,L3), (10=L4,L5), and (11=L6,L7). The sample point indication710represents the points in time the N interrupts, such as IRQin(N-1:0)222ofFIG. 3, are sampled dependent upon whether interrupts were previously detected and, for example, in synch with rising edges of Uclock706. To support a reduced latency interrupt controller, real-time event interrupts are assigned to the highest priority level, for example, interrupt priority levels zero and one. Less time-critical interrupts may be assigned to lower priority levels.

At the first sample point712, a priority level0(L0) interrupt is active and sampled. With the group counter506at a count value (0,0)714, priority levels L0and L1inputs to the muxes5300-530N-1and5310-531N-1are selected. Any sampled active interrupt that was assigned to priority levels L0or L1would be enabled to pass through the resource sharing circuits503and504. If a lower priority interrupt was also sampled at sample point712, it would be held in a pending state. Since in this example, there is an active L0interrupt that was sampled, that particular L0interrupt is passed through the resource sharing circuit503to one of the two internal priority level winner selection circuits545. Since the priority level L0interrupt is the highest priority level interrupt identified at this point in the count sequence, the final winner selection circuit546outputs a final winner620identifying, at this time, the highest priority interrupt as the L0interrupt.

In this second operating mode, the L0interrupt is received, for example, by interrupt processing logic226ofFIG. 2, for further processing and an acknowledgment is returned to the interrupt controller. In the second operating mode, the interrupt controller is reset to select the first group and new interrupts are sampled. At sample point715, a new priority level L0interrupt and a priority level L1interrupt are active and sampled. With the group counter506maintained at a count value (0,0)716, priority levels L0and L1inputs to the muxes5300-530N-1and5310-531N-1are selected. Since in this example, there are an active L0interrupt and an active L1interrupt, the identified L0interrupt is passed through the resource sharing circuit503and the identified L1interrupt is passed through the resource sharing circuit504to the two internal priority level winner selection circuits545. Since the priority level L0interrupt is the highest priority level interrupt identified at this point, the final winner selection circuit546outputs a final winner620identifying, at this time, the highest priority interrupt as the L0interrupt. After receiving an acknowledgement of the L0interrupt from the interrupt processing logic, the interrupt requests are sampled at sample point717with the group counter506being reset to or maintained at a count value (0,0)718. Since no new interrupts are active, the pending L1interrupt is selected for output.

After the high priority L1interrupt has been acknowledged, the interrupt controller samples the interrupts at sample point719, which samples an active L4interrupt. The group counter begins at a count value (0,0)720. Since at sample point719no active L0or L1interrupts were sampled, the resource sharing counter is updated to a new count value (0,1)721. At the new count value (0,1)721, priority levels L2and L3inputs to the muxes5300-530N-1and5310-531N-1are selected. Any interrupt active that was assigned to priority levels L2or L3would be enabled to pass through the resource sharing circuits503and504. Since in this example no active L2or L3interrupts were sampled, the group counter is updated to a new count (1,0) value722. At the new count value (1,0)722, priority levels L4and L5inputs to the muxes5300-530N-1and5310-531N-1are selected. Any active interrupt that was assigned to priority levels L4or L5would be enabled to pass through the resource sharing circuits503and504. Since at sample point719, there is an active L4interrupt that was sampled, that particular L4interrupt is passed through the resource sharing circuit503to one of the two internal priority level winner selection circuits545. Since the priority level L4interrupt is the highest priority level interrupt identified at this point in the count sequence, the final winner selection circuit546outputs a final winner726identifying, at this time, the highest priority interrupt as the L4interrupt. After receiving an acknowledgement for the L4interrupt, the interrupt requests are sampled at sample point723and the group counter506is reset to the beginning count value (0,0). The second operating mode allows a reduced latency for sampling and processing high priority interrupts.

FIG. 8illustrates an exemplary timing diagram800for power saving operations on the prioritized interrupt selection circuit500ofFIG. 5. In this example, there are eight priority levels, M=8, and R is equal to M/2=4 with the N×8×4 interrupt controller operating in a third operating mode to provide power saving operation of the interrupt controller. For the third operating mode, interrupts may be assigned such that high priority interrupts are assigned to priority level L0. The assigned high priority L0interrupts may be able to be sampled at a Sclock804rate and still meet system requirements. Further, the interrupt controller may be set inactive after sampling a high priority L0interrupt. When the interrupt controller is in an inactive state, the processing of any pending lower priority interrupts is delayed until the next Sclock period. If no active L0interrupt has been sampled, lower priority interrupts are processed as required to meet system requirements. In another embodiment, the interrupt controller may be set inactive after servicing any highest priority level interrupt holding processing of pending interrupt requests to the next clock period. Sclock804may suitably represent the timing of Sclock323ofFIG. 3. Uclock806may suitably represent the timing of Uclock523ofFIG. 5. Uclock806may be a gated clock that operates at a frequency that is R=4 times the frequency of Sclock804when Uclock806is not inactive for power saving reasons. Counter output808may suitably represent the timing of group counter506multiplexer select signals533. Counter output808sequences through count values representing two priority levels at a time at the sample points indicated by sample point indication810. The counter output808, in this example, provides count values that are associated with priority levels, such as, (00=L0,L1), (01=L2,L3), (10=L4,L5), and (11=L6,L7). The sample point indication810represents the points in time the N interrupts, such as IRQin(N-1:0)222ofFIG. 3, are sampled in a sampler, such as sampler324ofFIG. 3, dependent upon whether interrupts were previously detected and, for example, in synch with rising edges of Sclock804.

At the first sample point812, a priority level0(L0) interrupt is active and sampled. With the group counter506at a count value (0,0)814, priority levels L0and L1inputs to the muxes5300-530N-1and5310-531N-1are selected. Since in this example, there is an active L0interrupt that was sampled, that particular L0interrupt is passed through the resource sharing circuit503to one of the two internal priority level winner selection circuits545. Since the priority level L0interrupt is the highest priority level interrupt identified at this point in the count sequence, the final winner selection circuit546outputs a final winner820identifying, at this time, the highest priority interrupt as the L0interrupt. After receiving an acknowledgement for the L0interrupt, the interrupt controller is set inactive, which may include gating Uclock806off thereby stopping operation of the group counter506, the muxes5300-530N-1and5310-531N-1, the resource sharing circuits503and504, and the winner selection unit501.

At a second sample point815, a priority level2(L2) interrupt is active and sampled. Uclock806resumes clocking and the group counter506resumes operation. With the group counter506reset to a count value (0,0)816, priority levels L0and L1inputs to the muxes5300-530N-1and5310-531N-1are selected. Since there are no active L0or L1interrupts, the counter is updated to a new count value (0,1)817. Priority levels L2and L3inputs to the muxes5300-530N-1and5310-531N-1are selected. Since the priority level L2interrupt is the highest priority level interrupt identified at this point in the count sequence, the final winner selection circuit546outputs a final winner820identifying, at this time, the highest priority interrupt as the L2interrupt. After receiving an acknowledgement for the L2interrupt, the interrupt controller is set inactive, which includes gating Uclock806off thereby stopping operation of the group counter506, the muxes5300-530N-1and5310-531N-1, the resource sharing circuits503and504, and the winner selection unit501. The third operating mode provides power saving operations of the interrupt controller.

FIG. 9illustrates an exemplary first interrupt process900for a reduced latency interrupt controller. At block904, the interrupt controller is initialized, which may include, resetting a group counter, such as group counter506, to an initial count value representing the highest priority group of priority levels. The initialization may also include loading the configuration registers to map interrupts to priority levels. At block906, interrupt requests are sampled. At block908, a number of priority levels M divided by resource sharing factor R (M/R) priority level interrupts are scanned based on a group selection value, for example, from the group counter. At decision block910, a determination is made whether any active interrupts were found. If no active interrupts were identified in the M/R scanned group, the first interrupt process900proceeds to block912. At block912, the group counter is updated to the next count value and the first interrupt process900proceeds to block908to scan the next M/R group of priority level interrupts. If active interrupts were identified at decision block910, the first interrupt process900proceeds to block914. At block914, the highest priority interrupt is identified in the scanned group of M/R priority level interrupts. At block916, the highest priority identified interrupt is sent to interrupt processing logic, acknowledged, and the group selection circuit is reset. For example, the group counter506is reset to the initial count value. The first interrupt process900proceeds to block906to sample the incoming interrupt requests with any previously sampled lower priority interrupt requests kept pending. Further, a process to preclude interrupt starvation or loss of any pending interrupts may also be included in the first interrupt process900.

FIG. 10illustrates an exemplary second interrupt process1000for a power savings interrupt controller. At block1004, the interrupt controller is initialized, which may include, resetting a group selection circuit, such as group counter506, to an initial count value representing the highest priority group of priority levels. The initialization may also include loading the configuration registers to map interrupts to priority levels. Also, a parameter may be loaded to specify the count value of the group counter or priority level that may trigger placing the interrupt controller in an inactive state. At block1006, interrupt requests are sampled. At block1008, a total number of priority levels M divided by resource sharing factor R (M/R) priority level interrupts are scanned based on the count value from the group counter. At decision block1010, a determination is made whether any active interrupts were found. If no active interrupts were identified in the M/R scanned group, the second interrupt process1000proceeds to block1012. At block1012, the group counter count value is updated to the next count value and the second interrupt process1000proceeds to block1008to scan the next M/R group of priority level interrupts. If active interrupts were identified at decision block1010, the second interrupt process1000proceeds to block1014. At block1014, the highest priority interrupt is identified in the scanned group of M/R priority level interrupts. At block1016, the highest priority identified interrupt is sent to interrupt processing logic and the group selection circuit is rest after receiving an acknowledgement. At block1018, the interrupt controller may be set inactive to save power. At decision block1020, a determination is made as to whether the next sample point has been reached. If the next sample point has not been reached, the second interrupt process1000waits until the sample point has been reached. When the next sample point is reached, the second interrupt process1000proceeds to block1006. Further, a process to preclude interrupt starvation or loss of any pending interrupts may also be included in the second interrupt process1000.

FIG. 11illustrates a third embodiment of a prioritized interrupt selection circuit1100operating in a fourth operating mode. The prioritized interrupt selection circuit1100comprises a winner select unit1101, resource sharing circuits1103and1104, a resource sharing controller1105, a pattern generator or group counter1106, a configuration register1108, priority level decoder1120, multiplexer1130, and an early detection circuit logically shown as an OR gate1150. The prioritized interrupt selection circuit1100is shown with N sampled interrupt inputs IRQin(N-1:0)1102received from a sampler, such as sampler324ofFIG. 3, and with two resource sharing circuits1103and1104. The N interrupts are assigned to priority levels through the use of the configuration register1108.

The priority level decoder1120decode the priority levels stored their associated configuration register1108producing M-1inactive outputs and one active output from each internal decoder. The one active output from each of the internal decoders indicates the priority level for the associated interrupt. The group counter1106is a log(R)-bit counter that is clocked, for example, by a first update clock (Uclock1)1123and by a second update clock (Uclock2)1124, as described in more detail below. The group counter1106is controlled by the resource sharing controller1105. The group counter1106generates multiplexer select signals1133that are used by the multiplexer1130to select an output from each of the internal decoders to be used as enable signals1136coupled to AND gates11030-1103N-1of the resource sharing circuit1103and to AND gates11040-104N-1of the resource sharing circuit1104. The multiplexer select signals1133correspond to count values of the group counter1106with each count value, in this case, representing two priority levels. A count value of zero would enable priority levels L0and L1and a count value of one would enable priority levels L2and L3.

With an interrupt request detected in either priority levels L0or L1, the group counter1106may be updated by the Uclock11123or by the Uclock21124depending upon the operating mode. In one embodiment, Uclock21124operates at a higher frequency than Uclock11123. For example, in the first operating mode the group counter1106could be updated by Uclock11123providing similar timing to that shown in the timing diagram600ofFIG. 6. Alternatively, in the fourth mode of operation, the early detection circuit OR gate1150controls the group counter1106to adaptively generate the multiplexer select signals1133to select groups having one or more active interrupt requests and skip groups not having an active interrupt request. In the fourth operating mode, the group counter1106would be updated by Uclock21124in response to the early detection circuit OR gate1150indicating there are no active sampled interrupt request. With Uclock21124operating at a higher frequency than Uclock11123, the latency between processing active sampled interrupt requests is reduced.

The outputs of the resource sharing circuits1103and1104are coupled to the winner selection unit1101which outputs a highest priority interrupt Id signal1147and an associated interrupt status signal1148. When the early detection circuit OR gate1150indicates an active interrupt is present, the group counter1106updates the multiplexer select signals1133after a delay appropriate to process the active interrupt.

FIG. 12illustrates an exemplary third interrupt process1200for operating a programmable interrupt controller in a fourth operating mode for a reduced latency interrupt controller. At block1204, the interrupt controller is initialized, which may include, resetting a group counter, such as group counter1106, to an initial count value representing the highest priority group of priority levels. The initialization may also include loading the configuration registers to map interrupts to priority levels. At block1206, interrupt requests are sampled. At block1208, a number of priority levels M divided by resource sharing factor R (M/R) priority level interrupts are scanned based on a group selection value, for example, from the group counter. At decision block1210, a determination is made whether any active interrupts were found. If no active interrupts were identified in the M/R scanned group, the third interrupt process1200proceeds to block1212. At block1212, the group counter is updated to the next count value by use of high speed clock Uclock2to advantageously reduce the latency when no active interrupt requests have been sampled. The third interrupt process1200then proceeds to block1208to scan the next M/R group of priority level interrupts. If active interrupts were identified at decision block1210, the third interrupt process1200proceeds to block1214. At block1214, if the update clock was previously set to Uclock2at block1212, then the update clock is set back to Uclock1to provide sufficient time to process an identified interrupt. Also at block1214, the highest priority interrupt is identified in the scanned group of M/R priority level interrupts. At block1216, the highest priority identified interrupt is sent to interrupt processing logic, acknowledged, and the group selection circuit is reset. For example, the group counter1106is reset to the initial count value. The third interrupt process1200proceeds to block1206to sample the incoming interrupt requests with any previously sampled lower priority interrupt requests kept pending. Further, a process to preclude interrupt starvation or loss of any pending interrupts may also be included in the third interrupt process1200.

FIG. 13illustrates a second exemplary N×M×R programmable interrupt controller (PIC)1300with N interrupts, M priority levels, and a resource sharing factor R operating in a fourth operating mode for a reduced latency interrupt controller. The N×M×R PIC circuit1300comprises an interrupt controller and control register (ICCR) unit1304, a winning interrupt searcher1306, a priority level IRQ look ahead circuit1307, and an output selection unit1308. The ICCR unit1304comprises a priority level to interrupt request mapping unit1305having, for example, a configuration register (CR)1310, decoders1311, and a multiplexer (Mux) unit1312, a group selection circuit1314, and a resource sharing controller1316. The winning interrupt searcher1306comprises a sampler1324, a priority level IRQ selection unit1326, and a winner selection circuit1328. The output selection unit1308comprises a storage and control circuit1334. The N×M×R PIC circuit1300may be programmed by loading the CR1310with data values that assign each of the N interrupts, IRQin(N-1:0)222, with one of the priority levels M, with M=0 being the highest priority and M-1being the lowest priority.

In operation, the IRQin(N-1:0) signals222are adaptively sampled and stored in the sampler1324as up to N pending interrupts. The sample clock1323may be a gated clock or a controlled sampling signal as described in more detail below. The sampler1324outputs N sampled IRQ signals1325which are coupled to the priority level IRQ selection unit1326and to the look ahead circuit1307. Encoded data values stored in the CR310are decoded by decoders311whose output signals are coupled to the Mux unit312. The Mux unit312produces N*(M/R) enable signals315that are used to control the priority level IRQ selection unit326to select interrupts, for example, in groups of one or more priority levels to produce prioritized and selected pending interrupts327. The Mux unit312selects output signals of the decoders311to produce up to N*(M/R) enable signals315in response to a group selection output317provided from the group selection circuit314

The look ahead circuit1307examines the N sampled IRQ signals1325for active IRQs. If an active IRQ is detected, the look ahead circuit1307outputs an active prioritized group signal1309which identifies the highest priority group having the active interrupt request. The group selection circuit1314in response to the active prioritized group signal1309provides a group selection output1317to multiplexers in mux unit1312to provide enable signals315for at least the identified group having the active interrupt request. By use of the priority level IRQ look ahead circuit1307, the N sampled IRQ signals325are advantageously scanned within groups that have active interrupt requests thereby skipping scanning operations on groups without active interrupt requests.

FIG. 14illustrates an exemplary fourth interrupt process1400for operating a programmable interrupt controller in a fifth operating mode for a reduced latency interrupt controller. At block1404, the interrupt controller is initialized, which may include, resetting a group counter, such as group selection circuit1307, to an initial count value representing the highest priority group of priority levels. The initialization may also include loading the configuration registers to map interrupts to priority levels. At block1406, interrupt requests are sampled. At decision block1408, a determination is made whether any active interrupts were detected by the look ahead circuit, such as priority level IRQ look ahead circuit1307. If no active interrupts were identified, the fourth interrupt process1400proceeds to block1406where the interrupt requests are sampled. If one or more active interrupts were identified at decision block1408, the interrupt process1400proceeds to block1410. At block1410, the highest priority group having the one more active interrupts is identified. At block1412, a group selection circuit, such as the group selection circuit1314is updated with the identified highest priority group having the one or more active interrupt requests. At block1414, the highest priority identified interrupt in the identified highest priority group is sent to interrupt processing logic. With proper buffering, such as by using a first-in-first-out (FIFO) at the interface to the interrupt processing logic, multiple interrupt requests may be identified in priority order for presentation to the interrupt processing logic. The fourth interrupt process1400proceeds to block1406where the interrupt requests are sampled with any previously sampled lower priority interrupt requests kept pending. Further, a process to preclude interrupt starvation or loss of any pending interrupts may also be included in the fourth interrupt process1400.

By extension, large systems may be handled by the advantageous techniques of the present invention. For example, a system with N=1,024 interrupts, M=256 priority levels, and a resource sharing factor R of four may advantageously extend the techniques illustrated by the N×M×R programmable interrupt controller circuit300. By comparison, a programmable interrupt controller with no resource sharing would require M resource sharing circuits and M priority level winner selection circuits instead of M/R resource sharing circuits and M/R priority level winner selection circuits. Such savings provide an advantageous reduction in implementation area, even when considering the added cost for resource sharing circuitry. As shown with the prioritized interrupt selection circuit400, this added cost may be of minimum expense as long as system requirements may be met by such a design. With the techniques for reduced latency interrupt handling and reduced power utilization, considerable flexibility and system benefits may be obtained. It is further noted that the prioritized interrupt selection circuit500may be considered a superset of the prioritized interrupt selection circuit400. By appropriate mapping of interrupts or by redesign of muxes5300-530N-1and5310-531N-1, another embodiment of the prioritized interrupt selection circuit500may be utilized to emulate the operation of the prioritized interrupt selection circuit400. In this manner, larger resource sharing interrupt controllers may emulate smaller resource sharing interrupt controllers as a sixth mode of operation, providing another degree of flexibility and support for legacy design operations.

The methods described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in a computer readable medium, such as, RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. A storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. A software module residing in a computer readable medium when executed by a processor may, for example, program the operating mode of the N×M×R PIC300ofFIG. 3, the set of configuration registers310to assign sampled interrupt requests to priority levels, and the resource sharing factor R.

While the invention is disclosed in the context of illustrative embodiments, it will be recognized that a wide variety of implementations may be employed by persons of ordinary skill in the art consistent with the above discussion and the claims which follow below.