RAM TRUE RANDOM NUMBER GENERATOR

A system to generate true random numbers includes a RAM array, a null-read controller and a hash generator. The RAM array has memory cells and a sense amplifier. The memory cells store data therein, the cells are connected in rows to word lines and in columns to pairs of bit lines, and the sense amplifier senses a differential input signal. The null-read controller implements a null-read operation by the sense amplifier of a portion of the RAM array. The hash generator receives a null-read result from the null-read operation and outputs a partial true random number based on the null read result

FIELD OF THE INVENTION

The present invention relates to random number generators generally and to true random number hardware generators in particular.

BACKGROUND OF THE INVENTION

Random numbers are needed for many applications such as gambling, statistical sampling, computer simulation, and cryptography. Random number generation is a process by which a sequence of numbers, or any other symbols, that cannot be reasonably predicted is generated. A sequence that is produced by a random number generator (RNG) will contain some patterns that are discernable in hindsight, but are not predictable in foresight. A pseudorandom number generator (PRNG) generates numbers that appear random, but are in fact pre-determined, and may be reproduced by knowing the ‘seed’ value input to the PRNG, and the state of the PRNG. Most software implemented random number generators are PRNGs.

In contrast, the number sequence from a true random number generator (TRNG) is a function of a physical environment that is changing in a manner that cannot be modeled, such as measuring atmospheric noise, thermal noise, and radioactive decay of a material. Critical applications that require randomness, such as in security, generally use hardware random number generation.

SUMMARY OF THE PRESENT INVENTION

There is therefore provided, in accordance with a preferred embodiment of the present invention, a true random number generator system. The system includes a RAM array, a null-read controller and a hash generator. The RAM array has memory cells and a sense amplifier. The memory cells store data therein, the cells are connected in rows to word lines and in columns to pairs of bit lines, and the sense amplifier senses a differential input signal. The null-read controller implements a null-read operation by the sense amplifier of a portion of the RAM array. The hash generator receives a null-read result from the null-read operation and outputs a partial true random number based on the null read result.

Moreover, in accordance with a preferred embodiment of the present invention, the differential input signal is on pairs of bit lines when they are connected to the sense amplifier, or a pair of local data lines when they are connected to the sense amplifier.

Further, in accordance with a preferred embodiment of the present invention, the null-read controller includes a differential voltage conditioner (DVC) and a word line overrider (WLO). The DVC minimizes the sense amplifier offset voltage in the sense amplifier during the a null-read operation. The WLO stops a row controller activating connected word lines during a null read of the differential input signal on one of the pairs of bit lines, the connected word lines being connected to the rows of memory cells.

Still further, in accordance with a preferred embodiment of the present invention, the WLO outputs a word line address disable (WLAD) signal to disable all word line activations by the row decoder.

Additionally, in accordance with a preferred embodiment of the present invention, the WLO outputs an unconnected word line selection (UWLS) signal to enable the row controller to activate only unconnected word lines. The unconnected word lines are not connected to the rows of the memory cells.

Moreover, in accordance with a preferred embodiment of the present invention, prior to the null read operation, the DVC conditions the pair of bit lines by equalizing the number of stored 0s and 1s per the pair of bit lines, performing an additional RAM No-OP cycle, performing a valid-read operation, or performing a valid-write of 0 followed by a valid-read operation.

Alternatively, in accordance with a preferred embodiment of the present invention, the null-read controller includes a differential voltage conditioner (DVC) and a column controller. The DVC minimizes the sense amplifier offset voltage in the sense amplifier during a null-read operation. The column controller stops the column pass gates connecting the pair of bit lines to the pair of local data lines during a null read of the differential input signal on the pairs of local data lines.

Moreover, in accordance with a preferred embodiment of the present invention, prior to the null read operation, the DVC conditions the pair of local data lines by equalizing the number of stored 0s and is connected to the pair of local data lines, performing a additional RAM No-OP cycle, performing a valid-read operation, or performing a valid-write of 0 followed by a valid-read operation.

Further, in accordance with a preferred embodiment of the present invention, the RAM array is an SRAM (static random access memory) array.

Still further, in accordance with a preferred embodiment of the present invention, the RAM array is a DRAM (dynamic random access memory) array.

Additionally, in accordance with a preferred embodiment of the present invention, the null-read operation is a single null read, a multiplicity of sequential null reads, or a multiplicity of simultaneous null reads.

Moreover, in accordance with a preferred embodiment of the present invention, the RAM array stores the null-read result.

Alternatively, in accordance with a preferred embodiment of the present invention, the null read controller concatenates two null-read results to form a concatenated null-read result.

Further, in accordance with a preferred embodiment of the present invention, the RAM array stores a partial true random number.

Still further, in accordance with a preferred embodiment of the present invention, the hash generator concatenates two partial true random numbers to form a true random number.

Additionally, in accordance with a preferred embodiment of the present invention, the memory cells are 6T SRAM, 8T SRAM, dual-port SRAM or multi-port SRAM.

Additionally, in accordance with a preferred embodiment of the present invention, a multiplicity of the RAM arrays are arranged into a RAM bank.

There is provided in accordance, with a preferred embodiment of the present invention, a method for a RAM (random access memory) array. The method includes executing a null-read operation.

Moreover, in accordance with a preferred embodiment of the present invention, executing a null-read operation includes pre-charging a pair of differential lines in the RAM array to a predetermined voltage, and differentially reading a differential signal on the pair of differential lines by a sense amplifier, without receiving a second differential signal from a memory cell onto the pair of differential lines after the pre-charging.

Additionally, in accordance with a preferred embodiment of the present invention, the pair of differential lines is a pair of bit lines when they are attached to the sense amplifier, or a pair of local data lines when they are attached to the sense amplifier.

Moreover, in accordance with a preferred embodiment of the present invention, conditioning the pair of differential lines prior to the pre-charging is by equalizing the number of stored 0s and is per the pair of differential lines, performing an additional RAM No-OP cycle, second performing a valid-read operation, or third performing a valid-write of 0 followed by a valid-read operation.

Still further, in accordance with a preferred embodiment of the present invention, the differentially reading includes enabling a word line address disable (WLAD) signal to disable all word line activations by a row decoder, or enabling an unconnected word line selection (UWLS) signal such that the row controller activates only unconnected word lines which are the word lines that are not connected to rows of the memory cells.

Alternatively, in accordance with a preferred embodiment of the present invention, the differentially reading includes stopping column pass gates connecting the pairs of bit lines to the pair of local data lines, the pairs of bit lines also being connected to the columns of the memory cells.

There is therefore provided, in accordance with a preferred embodiment of the present invention, a method to generate a true random number. The method includes pre-charging a pair of differential lines in a portion of a RAM array to a predetermined voltage, null-reading a differential signal on the pair of differential lines, receiving a null-read result from the null-reading, and generating a partial true random number based on the a null-read result.

Moreover, in accordance with a preferred embodiment of the present invention, the pair of differential lines is a pair of bit lines when they are attached to a sense amplifier, or a pair of local data lines when they are attached to the sense amplifier.

Further, in accordance with a preferred embodiment of the present invention, the null-reading includes differentially reading the differential signal on the a pair of differential lines by a the sense amplifier, without receiving a second differential signal from a memory cell onto the pair of differential lines after the pre-charging.

Still further, in accordance with a preferred embodiment of the present invention, the differentially reading includes enabling a word line address disable (WLAD) signal to disable all word line activations by a row decoder, or enabling an unconnected word line selection (UWLS) signal such that the row controller activates only unconnected word lines which are the word lines that are not connected to rows of the memory cells.

Alternatively, in accordance with a preferred embodiment of the present invention, the differentially reading includes stopping column pass gates connecting the pairs of bit lines to the pair of local data lines, the pairs of bit lines also being connected to the columns of the memory cells.

Additionally, in accordance with a preferred embodiment of the present invention, the null-reading is a single null read, a multiplicity of sequential null reads, or a multiplicity of simultaneous null reads.

Moreover, in accordance with a preferred embodiment of the present invention, the method includes first storing the a null-read result in a RAM array.

Further, in accordance with a preferred embodiment of the present invention, the method includes first concatenating two null-read results to form a concatenated null-read result.

Still further, in accordance with a preferred embodiment of the present invention, the method includes second storing the partial true random number in the a RAM array.

Moreover, in accordance with a preferred embodiment of the present invention, the method includes second concatenating at least two the partial true random numbers to form a true random number.

Additionally, in accordance with a preferred embodiment of the present invention, the method includes conditioning the pair of differential lines prior to the pre-charging by equalizing the number of stored 0s and 1s per differential line pair, performing an additional RAM No-OP cycle, second performing a valid-read operation, or third performing a valid-write of 0 followed by a valid-read operation.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

Applicant has realized that elements in a standard 6T SRAM (static random access memory) array, may be used in a true random number generator (TRNG) system. In order to understand the operation of the TRNG system, the structure and operation of SRAM arrays will be presented.

SRAM Background

Reference is now made toFIG. 1, which illustrates a standard 6T SRAM memory cell100composed of six transistors, and toFIG. 2which illustrates an SRAM memory array200of multiple cells100.

Four transistors (not shown) of 6T SRAM cell100form a standard flip-flop element102that has two stable voltage states which define as the logical “0” and “1” states of cell100. Typically, a high voltage value defines the logical “1” and a low voltage value defines the logical “0”. The cell outputs its stored value via node Q and its complementary value via node Q′. Thus if cell100stores the value “1”, the voltage value at node Q reflects the value of “1” and the voltage value at complementary node Q′ reflects the value of “0”.

Two bit lines, BL and BL′, are used to transfer data from the cell for read operations. The bit lines BL and BL′ are connected to flip-flop102via two pass transistors N1and N2respectively, which control access to the cell.

As shown inFIG. 2, the cells in memory array200are arranged in a matrix. All the cells100in the same column are connected to the same bit line pair BL and BL′ via the access transistors N1and N2of each cell. All the cells in the same row are connected to the same word line WL. The column of cells is selected by charging bit lines BL and BL′ of the desired column with the appropriate voltage. Row decoder16controls the row selection by charging word line WL of the selected row to high.

When row decoder16selects a word line WL, according to ADD, the input row address, as the gates of transistors N1and N2are connected to word line WL then gate transistors N1and N2of all cells100in the selected row are activated. Then the contents of cells100may be accessed for read operations. Hence the selected cell100is the cell that resides at the intersection of word line WL and the bit line pair BL and BL′ for a column.

SRAM Read Operation

To read the state of 6T SRAM cell100, first, both bit lines BL and BL′ are pre-charged to a high voltage level by a pre-charge circuit300, which is connected to bit lines BL and BL′. Reference is now made toFIG. 3, which illustrates an exemplary implementation of a standard pre-charge circuit300. Pre-charge circuit300comprises three transistors N3thru N5. Transistor N3is a gating transistor that controls the connection of voltage source VDD to bit line BL. Transistor N4is a gating transistor that controls the connection of voltage source VDD to bit line BL′. Transistor N5is a gating transistor that controls the connection of bit line BL to bit line BL′. The gates of all transistors N3thru N5are controlled by a pre-charge enable signal, PCEN.

To pre-charge bit lines BL and BL′, signal PCEN may be enabled, which turns on all transistors N3thru N5. Bit lines BL and BL′ may both be charged toward VDD. After a predetermined time, Tpc, then the voltage levels on bit lines BL and BL′ may stabilize, signal PCEN may be disabled, leaving bit lines BL and BL′ floating high with a balanced voltage.

Then row decoder16activates word line WL which activates pass transistors N1and N2in cell100, connecting nodes Q and Q′ to bit lines BL and BL′ respectively. When connected, voltage levels of nodes Q and Q′ will affect the final voltage on bit lines BL and BL′, respectively. One of nodes Q and Q′ stores logical value “1”, or a voltage level at VDD, and the other of nodes Q and Q′ stores logical value “0”, or a voltage level at VSS. For example, as transistor N1and transistor N2are on, then if cell100stores a “1”, and node Q equals 1 and node Q′ equals 0, then the voltage level on bit line BL stays at voltage VDD and the voltage level on bit line BL′ starts to be pulled low by flip flop102through transistor N2. If cell100stores a “0”, then the voltage level on bit line BL′ stays at voltage level VDD and the voltage level on bit line BL starts to be pulled low. As explained hereinbelow, sense amplifier (SA)400measures the final voltage levels on bit lines BL and BL′ according to the content of cell100.

After a predetermined time, Tread, the signal or the delta voltages on bit lines BL and BL′ develops, then SA400may compare the voltage levels on bit lines BL and BL′. Reference is now made toFIG. 4, which illustrates an exemplary implementation of a standard SA circuit400. SA circuit400has four inverters I1thru I4, and five transistors: a cross connected pair N6and N7; a cross connected pair N9and N10; and, a gating transistor N8. Bit line BL is connected to the drain of transistor N6, the drain of transistor N9, the gate of transistor N10, the gate of transistor N7and the input of inverter I1. The output of inverter I1is connected to the input of inverter I2, and the output of inverter I2is the output of SA400, “SAOUT”. Bit line BL′ is connected to the drain of transistor N7, the drain of transistor N10, the gate of transistor N9, the gate of transistor N6and the input of inverter I3. The inverters I3and I4form a dummy device to provide a balanced capacitance to bit line BL′ to mimic the capacitance load of inverters I1and I2to bit line BL. The source of transistors N6and N7are connected to node D. Transistor N9is connected between voltage source VDD and bit line BL. Transistor N10is connected between voltage source VDD and bit line BL′. Transistor N8is connected between the sources of transistors N6and N7and ground. The gate of transistor N8is connected to sense amplifier enable signal (SAEN) which acts as an enable and disable for the entire sense amplifier.

Transistor N8is activated by signal SAEN, causing SA400to output a cell read value, equal to either a logical “1” or to a logical “0”. When SAEN is enabled, transistor N8is turned on and pulls node D low. If the voltage level on bit line BL is higher than the voltage level on bit line BL′, then transistor N7has more drive strength than transistor N6. Then bit line BL′ is pulled low and bit line BL is pulled back up high by transistor N9after an initial dip. Inverters I1and I2will then buffer the signal on bit line BL to a logic 1 as the output, SAOUT, of SA. Accordingly, SA400outputs a logical “1” indicating that cell100is storing the value “1.” The converse is true for a stored value of “0”.

The memory cell transistors in circuit100consist of minimum size transistors for small memory cell size. The transistor drive capability to pull down bit lines BL and BL′ during a read operation is weak. Bit lines BL and BL′ are high capacitance lines, with many connected cells100. Therefore, bit line BL and BL′ need time to discharge, and to develop the signal margin to overcome the inherent SA offset voltage.

The SA offset voltage comprises the sum of the following:

1. The mismatch of VT (Threshold Voltage) and GM (Transconductance) of NMOS cross coupled transistor pair, N6and N7in the SA400circuit.

2. The mismatch of VT (Threshold Voltage) and GM (Transconductance) of PMOS cross coupled transistor pair, N9and N10in the SA400circuit.

3. The capacitance mismatch of bit lines BL and BL′.

4. The leakage current mismatch of bit lines BL and BL′.

Applicant has realized that a sense amplifier may compare a differential voltage signal between bit lines BL and BL′ even when no cell has been read, during what may be defined as a “Null Read” operation.

As mentioned herein above, after pre-charging, the voltages on bit line BL and bit line BL′ may be equalized and stay at voltage level VDD. When word line WL is activated, either bit line BL or BL′ may be pulled low, as explained hereinabove. In the null read case, where no word line WL is activated, SA400may still perform sensing when SAEN is on and SAOUT flips to either 1 or 0 based on SA offset voltages discussed hereinabove.

Spatial Randomness

SA offset voltage is randomly distributed across the chip. The neighboring SA may have varied offset voltages, with some SA having an offset voltage favoring bit line BL, while another SA have an offset voltage favoring BL′. Therefore, the null read value on SAOUT may vary from location to location across the chip, and also vary from chip to chip in a giving location.

Temporal Randomness

Applicant has also realized that a number of sense amplifiers in a chip may have SA offset voltages so small that the null read value on SAOUT may vary between different null read cycles influenced by changing physical effects, such as electrical noises, temperature effects, etc. Since these effects change with time, the random SAOUT may be defined as “temporally random.”

True Random Number Generator System

Applicant has realized that, since SRAMs are ubiquitously embedded in the designs of processor, GPU, FPGA and microcontrollers, an SRAM memory array used for embedded memory storage under normal operation may also be used as the basis for a true random number generator system. Applicant has also realized that an output from an SRAM null-read may be used as an input to a hash encoder to output a true random number.

Applicant has realized that by keeping the output of the SRAM null read to the hash generator entirely within the domain of the claimed system, it cannot be altered by external entities, thus guaranteeing the integrity of the process.

Reference is made toFIG. 5Awhich is an illustration of an SRAM true random number generator (STRNG)500. STRNG500comprises a CPU51, an SRAM array53(similar to SRAM array200inFIG. 2), a hash generator56, and a null-read controller (NRC)58. NRC58comprises a differential voltage conditioner (DVC)54, and word line overrider (WLO)59.

CPU51may control the operation of row decoder16, pre-charge circuit300and SA400(as shown inFIG. 2) within SRAM array53. NRC58may supply techniques to CPU51to perform single or multiple null-read operations. WLO59may apply additional word line conditioning, as explained hereinbelow, such that SA400may make differential bit line measurements without cell100reads, during null-read operations. DVC54may apply conditioning techniques, as explained hereinbelow, such that bit lines BL and BL′ may become more precisely balanced during null-read operations.

SRAM array53may output a null-read result NR to hash generator56, or may store result NR in SRAM array53. Hash generator56may hash result NR to produce a random number, RN, such that RN=H(NR), where H is the hash function of hash generator56.

In an alternate embodiment, SRAM true random number generator may comprise a multiplicity of SRAM arrays organized into SRAM banks. Reference is briefly made toFIG. 5Bwhich illustrates an alternative STRNG, labeled500′. STRNG500′ is similar to STRNG500in that it comprises CPU51, hash generator56, and differential voltage conditioner (DVC)54. However, in this embodiment, STRNG500′ comprises a multiplicity of SRAM banks52each comprising a plurality of SRAM arrays53. CPU51may be connected to each SRAM array53, and to each SRAM bank52, to NRC58and to hash generator56.

As in STRNG500, CPU51may control the operation of all row decoders16, all pre-charge circuits300and all SAs400within any of the multiplicity of SRAM arrays53. STRNG500′ may perform a null-read operation on a multiplicity of SAs400that may be contiguous on a single SRAM array53, non-contiguous on a single SRAM array53, non-contiguous across a multiplicity of SRAM arrays53in a single SRAM bank52, or non-contiguous across a multiplicity of SRAM arrays53across a multiplicity of SRAM bank52. Likewise, output NR may be stored in a contiguous or non-contiguous fashion.

Applicant has realized that STRNG500or500′ may perform a null-read operation using a standard row decoder that accesses a word line not connected to a row cells100, in any SRAM array53. Reference is made toFIG. 6Awhich illustrates NRC59connected to a row decoder16′ and memory cells100of an SRAM array53′ (similar to that shown inFIG. 2). As explained hereinabove, row decoder16′ of SRAM array53′ may access one of its word lines W0thru W255.

Applicant has realized that, by having more word lines WL than the number of rows of memory cells100in memory array53′, then there may be a plurality of word lines WL that are not connected to any row of cells100, in any memory array53′. For example, if row decoder16′ receives address ADD, which may be an 8 bit address (with256possible addresses), ADD[0:7], then row controller16′ may control256word lines W0thru W255. If the number of rows in memory array53actually connected to memory cells100is less than 256, say 240, then row decoder16′ may use word line addresses ADD[0:7] from 0 to 239 to activate word lines WL0to WL239which are connected to memory cells100, and may use word line addresses ADD[0:7] from 240 to 255 to activate unconnected word lines WL240to WL255. Hence, WLO59, (via NRC59and via CPU51) may output an unconnected word line selection signal, UWLS, to row decoder16′, such that row decoder16′ may select a word line address between ADD[0:7] from 240 to 255, which may activate an unconnected word line WL240to WL255, in order that selected SAs400may perform a null-read.

Reference is briefly made toFIG. 6Bwhich illustrates an alternate embodiment of SRAM array53″, that comprises a row decoder16″ which receives a word line address disable signal WLAD from WLO59, (via NRC59and via CPU51). When activated, signal WLAD may disable all word line outputs W0thru W239from row decoder16″. Hence, when signal WLAD is enabled, selected SAs400may perform null-reads regardless of the value of word line address ADD.

Reference is made toFIGS. 7Athru7D which illustrate inputs and outputs of SAs400and hash generator56(similar to those shown inFIG. 6A). As shown inFIG. 7A, SRAM array53may perform a null-read utilizing a plurality R of SAs400at one time. After a null-read operation, SAs400may output the R bits of null-read result NR to hash generator56.

Hash generator56may require an input G of M bits, as shown inFIG. 7B.

As shown inFIG. 7C, if M is greater than R, then SRAM array53may make a plurality of null-reads, for example: NR1, NR2and NR3, and then may form a concatenated M bit output G, suitable for input to hash generator56.

It will be appreciated that STRNG500′, rather than making multiple null-reads, a single set of SAs400may make a plurality of simultaneous null-reads on a plurality of SAs400in different areas of SRAM array53and/or across multiple SRAM arrays53in either the same or different SRAM banks52.

A shown inFIG. 7D, if hash generator56requires an input G of M bits, and if M is less than R, then array53may output a subset of the R bits of result NR to hash generator56.

It should be noted that cryptographic hash functions, such as SHA-K, may take a variable length input of M bits and produce a fixed length output of K bits. For example, the input sequence M may be 32768 bits, and the output sequence K may be 256 bits, as for example in SHA-256.

Applicant has realized that if the number M of bits required as input G by hash generator56includes at least K random bits, then H(M) is a true random number of K bits.

Applicant has realized that, at any given time, about 5% of sense amplifiers may produce temporally random data. Therefore, as long as 5% of M is greater than K, then the hash of G, H(G), may be a true random number of K bits.

It should also be noted that if the required true random number (TRNG-N) has N bits, and the number of bits output from hash generator53is K bits, then if K is greater than N, hash generator56may output an N bit subset of the K bit hash generator output. However, if K is less than N, then system500may invoke several null-read and hash generations, which may then be concatenated to form a TRN of a full N bits.

Bit Line Differential Voltage Conditioning

During a normal read operation the pre-charge time, Tpc, may not be long enough to fully equalize bit lines BL and BL′ to voltage level VDD. This may be an acceptable design choice as it takes less time to develop the sense signal on bit lines BL and BL′ than to fully equalize the voltage levels on bit lines BL and BL′. However, for a null-read operation it is more critical to have bit lines BL and BL′ pre-charged and fully equalized to minimize the effects of any SA offset voltage due to insufficient time Tpc. Also, if bit lines BL and BL′ have an unbalanced number of memory cells100storing “1s” and memory cells100storing “0s”, then the offset voltage due to leakage may favor either bit lines BL or BL′ depending on the number of memory cells100storing “1s” and memory cells100storing “0s” connected to bit lines BL or BL′. In order to minimize the offset voltage on bit lines BL and BL′ before a null read, Applicant has realized that a number of different steps may be performed. Such steps may be performed by DVC54.

(i) To ensure proper pre-charging of bit lines BL and BL′, DVC54may add an extra SRAM No-OP cycles to ensure bit lines BL and BL′ may be fully equalized and precharged high. No-Op cycles are when there is no read from or write to cell100after pre-charging.

(ii) To avoid such impacts of leakage, DVC54may ensure equal numbers of stored 0s and 1s per bit line pair. For example, columns may be written with alternating stored 0s and stored 1s.

(iii) To ensure balanced bit lines BL and BL′, DVC54may make a valid-read prior to a null-read. A valid read is one where word line WL activates a cell100.

(iv) To ensure balanced bit lines BL and BL′, DVC54may make a valid-write of 0, followed by a valid-read, prior to a null-read. Similarly, a valid write is one where word line WL activates a cell100.

A null-read after valid-read or valid-write operation may have further unpredicted results pending on previous operation and data background.

Alternate Embodiments

The design of SA400as shown inFIG. 4is an example only, variations of sense amplifier designs known in the art, may also be used.

Although standard 6T SRAM is described inFIGS. 1 and 2, alternate embodiments may utilize 8T, dual-port and multi-port SRAM.

Reference is made toFIG. 8which illustrates an alternate embodiment of RAM array53′″ which also comprises a differential local data line pair LDL and LDL′, an LDL pre-charge circuit81, a column decoder82, column pass gates83and NRC58. Column pass gates83may be used to multiplex multiple column differential bit line pairs BL and BL′ to differential local data line pair LDL and LDL′ such that differential local data line pair LDL and LDL′ may be connected to SA400, rather than differential bit line pair BL and BL′ being connected directly to SA400, as described herein above. Column pass gate83may be decoded by column decoder82using a column line CL. After LDL pre-charge circuit81pre-charges and equalizes local data line pair LDL and LDL′, then NRC58may perform a null-read operation by disabling column decoder82(similar to the manner in which row decoder16may be disabled, as described hereinabove) such that LDL and LDL′ do not connect to BL and BL′ and there is no signal developed by memory cell100.

Alternate embodiments of a STRNG may implemented on DRAM (dynamic random access memory), since DRAM also has a similar differential sensing mechanism in its sense amplifiers.

Spatial Randomness

As mentioned hereinabove, an SA400with large offset voltages may produce the same and consistent logical output during a null-read operation and an SA400with very small offset voltage may produce random logic outputs from null-read cycle to null-read cycle.

Applicant has realized that the offset voltage distribution of sense amplifiers may vary from location to location on an SRAM chip, and may also vary from SRAM chip to SRAM chip. Therefore, the result of a null read made across multiple SRAM locations may be unpredictable and may be “spatially random”.

Likewise, bit lines BL and BL′ may have weak cells that leak more than an average cell. These weak cells may be spatially randomly distributed across SRAM locations and may also be used as the basis for random number generation.