DC AND SYNCHRONIZED ENERGY ASSISTED PERPENDICULAR MAGNETIC RECORDING (EPMR) DRIVER CIRCUIT FOR HARD DISK DRIVE (HDD)

Various illustrative aspects are directed to a data storage device comprising a storage medium and a head configured to access the storage medium. The head comprises a first write assist element and a second write assist element. Control circuitry for driving the head is configured to apply a first write assist current Im that is synchronized to a write data current Iw to the first write assist element; and to apply a second DC write assist current Imdc to the second write assist element.

BACKGROUND

Data storage devices such as hard disk drives (HDDs) comprise a disk and a head connected to a distal end of an actuator arm that is rotated about a pivot by a voice coil motor (VCM) to position the head radially over the disk. The disk comprises a plurality of radially spaced, concentric tracks for recording user data sectors and servo sectors. The servo sectors comprise head positioning information (e.g., a track address) that is read by the head and processed by a servo control system to control the actuator arm as it seeks from track to track.

Data is typically written to the disk by modulating a write current in an inductive coil (write coil) to record magnetic transitions onto the disk surface in a process referred to as saturation recording. During read-back, the magnetic transitions are sensed by a read element (e.g., a magneto-resistive element) and the resulting read signal is demodulated by a suitable read channel. In conventional perpendicular magnetic recording (PMR), an electrical current is passed through the write coil, which generates a magnetic field. This field magnetizes a write pole, which is in close proximity to the disk surface. The magnetic field from the write pole then aligns the magnetic grains in the disk media in a certain orientation, creating a stored bit.

Since data on an HDD is written on tracks, higher tracks per inch (TPI) and higher bits per inch (BPI) on those tracks result in higher areal density, which enables more data per disk. Energy assisted magnetic recording (EAMR), which involves focusing energy on the track being written to in order to make the disk media easier to write to, is one approach for increasing aerial density. One type of EAMR is heat assisted magnetic recording (HAMR), which heats the disk surface during write operations to decrease the coercivity of the magnetic medium, thereby enabling the magnetic field generated by the write coil to magnetize the disk surface more readily. Another type of EAMR is microwave assisted magnetic recording (MAMR), which uses a spin torque oscillator (STO) to apply a high frequency auxiliary magnetic field to the media close to the resonant frequency of the magnetic grains, thereby enabling the magnetic field generated by the write coil to magnetize the disk surface more readily.

SUMMARY

Various aspects of this disclosure provide a DC and synchronized energy assisted perpendicular magnetic recording (ePMR) driver circuit for a hard disk drive (HDD).

One aspect of this disclosure is directed to a data storage device comprising a storage medium; a head configured to access the storage medium, the head comprising a first write assist element and a second write assist element; and control circuitry for driving the head, the control circuitry configured to apply a first write assist current Im that is synchronized to a write data current Iw to the first write assist element; and apply a second DC write assist current Imdc to the second write assist element.

Another aspect of this disclosure is directed to control circuitry, which may comprise one or more processing devices, for driving a head of a data storage device that comprises an inductive write assist element and a resistive write assist element. The control circuitry comprises means for applying a first write assist current Im that is synchronized to a write data current Iw to the inductive write assist element; and means for applying a second DC write assist current Imdc to the resistive write assist element.

A further aspect of this disclosure is directed to a method for driving a head of a data storage device. The method comprises applying a write assist current Im that is synchronized to a write data current Iw to an FEePMR write assist element during a write operation; and applying a DC write assist current Imdc to an ePMR write assist element during the write operation.

In some implementations of the data storage device, control circuitry and/or the method described herein, the first write assist element is a field effect energy assisted perpendicular magnetic recording (FEePMR) write assist element; and the second write assist element is an energy assisted perpendicular magnetic recording (ePMR) write assist element.

In some implementations of the data storage device, control circuitry and/or the method described herein, the first write assist element has an inductance Lm and the second write assist element has a resistance Rm.

In some implementations of the data storage device, control circuitry and/or the method described herein, the control circuitry comprises first and second current sources that generate toggled currents I_p and I_n that are timed relative to the write data current Iw. The first and second current sources are coupled to the first write assist element to generate the first write assist current Im that is synchronized with the write data current Iw.

In some implementations of the data storage device, control circuitry and/or the method described herein, the control circuitry comprises a first voltage source Vm that is coupled to the second write assist element to generate the second DC write assist current Imdc.

In some implementations of the data storage device, control circuitry and/or the method described herein, the control circuitry comprises a dynamic wave shaping (DWS) element that programs an overshoot pulse amplitude and an overshoot pulse duration of the first write assist current Im.

In some implementations of the data storage device, control circuitry and/or the method described herein, the control circuitry comprises a variable delay element that programs a delay of the first write assist current Im relative to the write data current Iw.

In some implementations of the data storage device, control circuitry and/or the method described herein, the control circuitry comprises a variable capacitance Cx across the first write assist element that sets a rise/fall time of the first write assist current Im.

Additional aspects of this disclosure are depicted and described in the accompanying drawings and the following description.

DETAILED DESCRIPTION

FIG.1Ais a conceptual block diagram of a data storage device in the form of hard disk drive (HDD)100, in accordance with aspects of this disclosure. HDD100comprises a storage medium in the form of disk60and a magnetic read-write head50. Disk60comprises a plurality of radially spaced data tracks4that may be divided into a plurality of circumferentially spaced data sectors (not shown) for storing user data and/or other information. Disk60also comprises a plurality of angularly spaced servo wedges220-22Nthat include a servo sector for each data track4providing embedded servo information for the track. The servo information for each track4may include a pattern of alternating magnetic transitions (servo burst), which may be read from disk60by head50and processed by controller10to determine the position of head50relative to the corresponding track4.

Magnetic read-write head50is connected to the distal end of actuator arm25to access the surface of disk60. Head50includes a write element for writing data to disk60and a read element for reading data from disk60. Actuator arm25is rotated about a pivot by an actuator such as voice coil motor (VCM)20to position head50radially over disk60. To write data to disk60, control circuitry10controls VCM20to position head50over a desired track4. Control circuitry10processes data to be written to disk60into a data write current, which is outputted to head50. Head50converts the write signal into a magnetic field that magnetizes the surface of disk60, thereby magnetically writing the data onto disk60. To read data from disk60, control circuitry10controls VCM20to position head50over a desired track4. Head50generates a read signal based on the magnetization of the disk surface under head50. Control circuitry10receives and processes the read signal into data. HDD100also includes a spindle and a spindle motor (not shown) for rotating disk60at high speed during read/write operations such that an air bearing forms between head50and the surface of disk60.

Host30may be a computing device such as a desktop computer, a laptop, a server, a mobile computing device (e.g., smartphone, tablet, Netbook, to name a few non-limiting examples), or any other applicable computing device. Alternatively, host25may be a test computer that performs calibration and testing functions as part of the disk drive manufacturing processing.

Control circuitry10controls HDD100is configured to perform various operations described herein. In one aspect of this disclosure, control circuitry10is configured to execute the method80shown in the flow diagram ofFIG.1B. In particular, and as will be described in more detail herein, in step82, a synchronized write assist current Im is applied to a first (e.g., FEePMR) write assist element during a write operation. In step84, a DC write assist current Imdc is applied to a second (e.g., ePMR) write assist element during the write operation. In additional aspects of this disclosure, in connection with method80, control circuitry10may execute method750ofFIG.7for programming various parameters of the synchronized and DC write assist currents.

Energy assisted magnetic recording (EAMR), which involves focusing energy on the track being written to make the disk media easier to write to, is one approach for increasing aerial density. One type of EAMR is heat assisted magnetic recording (HAMR), which heats the disk surface during write operations to decrease the coercivity of the magnetic medium, thereby enabling the magnetic field generated by the write coil to magnetize the disk surface more readily. Another type of EAMR is microwave assisted magnetic recording (MAMR), which uses a spin torque oscillator (STO) to apply a high frequency auxiliary magnetic field to the media close to the resonant frequency of the magnetic grains, thereby enabling the magnetic field generated by the write coil to magnetize the disk surface more readily.

According to aspects of this disclosure, another type of energy assisted magnetic recording (EAMR) is energy assisted perpendicular magnetic recording (ePMR), which introduces an improvement in head transition consistency that reduces jitter and enables an increase in BPI. Jitter comes from the volatility of saturation at the recording head when flipping the write current from one direction to another and is a significant limiter for improving BPI. ePMR applies an electrical bias current to an assist element in the recording head (e.g., near the main pole of the write head) during at least a portion of the write operation. This current generates an additional magnetic field that creates a preferred path for the magnetization flip of media bits. By applying a preferred magnetic path, every pass of multiple data writes has a more consistent waveform. This, in turn, produces a more consistent write signal, significantly reducing jitter. When jitter is reduced, bits of data can be written closer together, which increases BPI and leads to higher aerial density. An example ePMR assist element and its related material stack and design is described in co-owned U.S. Pat. No. 10,891,974 granted Jan. 12, 2021, titled “Magnetic head with current assisted magnetic recording and method of making thereof” which is hereby incorporated by reference.

According to aspects of this disclosure, a driver for a write head utilizing ePMR is provided that enhances write-ability and reduces write jitter. The driver synchronizes the ePMR current with the head write current to properly drive the head.FIG.2is a conceptual block diagram of a head200utilizing ePMR write assist elements and control circuitry201to drive head200. Control circuitry201includes preamp220coupled to head200, and data channel240coupled to preamp200. Control circuitry201may be a part of control circuitry10ofFIG.1Aor may be separate from control circuitry10.

Head200comprises a first write assist element202coupled in series with a second write assist element204. In one implementation, first write assist element202is a field effect ePMR (FEePMR) element, having an inductance Lm, and second write assist element204is an ePMR element, having a resistance Rm. The FEePMR element is so-labeled field effect ePMR as it is an assist element that provides an assistive effect to the primary write field generated by the write pole or main pole driven by the write coil206. The FEePMR element implementation can include several options, including a conductive element or material stack near the write pole (e.g., between the write pole and a surrounding shield or structure), a magnetic assistive write element such as an assistive pole, etc. A first write assist current Im that is synchronized with the write data current Iw is driven in first write assist element202, and a second, DC write assist current Imdc is driven in second write assist element204. As will be described in more detail, the ePMR portion of head200is driven by signals on three terminals DC, M1and M2from preamp220. Head200further comprises write coil206, which is an inductive coil that writes data by selectively magnetizing portions of the magnetic material on the surface of disk60. Magnetic transitions representing bits are written into the magnetic material by reversing the current through write coil206. As implemented in a disk drive, head200may correspond to head50ofFIG.1A.

Preamp220comprises ePMR driver circuit222, which drives FEePMR write assist element202and ePMR write assist element204of head200via signals on terminals DC, M1and M2. Additional details of driver circuit222will be described with reference toFIGS.3and8. Preamp220further comprises write driver224, which generates an analog signal, current Iw, that is applied to the inductive write coil206of head200. Driver circuit222is driven by the write data output of write receiver230, as delayed by programmable delay element226. Write driver224is driven by the write data output of write receiver230, as delayed by delay element228. As will be described in more detail herein, programmable delay element226provides the ability to program and modify the timing of synchronized write assist current Im relative to the timing of write data current Iw.

In some embodiments, the head200includes one assist element. For example, an implementation of head200may only include the first assist element FEePMR202and not the second assist element ePMR204. Correspondingly, the ePMR driver circuit would not need to drive the DC write assist current and would provide the synchronized write assist current. In other embodiments, the head200can include other types of assist elements (other than FEePMR) that can be driven with the synchronized write assist current. Similarly, the head200can include other types of assist elements (other than ePMR) that can be driven with the DC write assist current. Thus preamp220can be generally used for driving various types of assist elements.

Preamp220further comprises dynamic wave shaping (DWS) element232, which provides a DWS trigger signal to driver circuit222. DWS element232can optionally modify parameters of the synchronized write assist current Im based on the shape and pattern of the write data current Iw. For example, and as will be described in more detail herein, DWS element232can provide synchronized write assist current Im with a programmable overshoot pulse (Imosa) and a programmable overshoot duration (Tosd) (FIG.5). In addition, DWS element232can boost the synchronized write assist current Im (FIG.6A) as well as the overshoot pulse Imosa (FIG.6B).

Preamp220is coupled to data channel240. Data channel240comprises DWS driver242, which drives DWS element232of preamp220with differential signals DWS_p and DWS_n. Data channel240further comprises write driver244, which drives write receiver230of preamp220with differential write data signals Wrt_p and Wrt_n. Data channel further comprises logic/SIO element246which is in communication with logic/SIO element236of preamp220.

FIG.3is a conceptual block diagram of head200and driver circuit222, in accordance with aspects of this disclosure. Voltage source210(Vm) of driver circuit222, which is coupled to the DC terminal of head200via termination resistance211(Rt) and transmission line205, programmably sets the DC write assist current Imdc applied to ePMR write assist element204(Rm) relative to the common mode voltage source212(Vwrt_cm). Termination resistance211(Rt) is matched with the impedance Zo of transmission line205to minimize voltage reflections. Common mode voltage source212(Vwrt_cm) is coupled to transmission lines203and201via termination resistances213and215(Rt), which are matched with the impedances of transmission lines203and201to minimize voltage reflections.

Current sources214and216of driver circuit222respectively generate pulsed or toggled currents I_p and I_n that are timed relative to the write data current Iw via application of the write data current Iw to driver circuit222(FIG.2). Pulsed or toggled currents I_p and I_n are coupled, respectively, to terminals M1and M2of head200via transmission lines203and201to produce a write assist current Im that is synchronized with the write data current Iw and that flows through FEePMR write assist element202(Lm). Thus, driver circuit222sets a programmable DC write assist current Imdc through write assist element204(Rm) and a programmable synchronized write assist current Im through write assist element202(Lm).

In head200, the capacitance Cm across Rm (across the DC and M1terminals) should be minimized to minimize current glitches through write assist element204(Rm). In addition, the capacitance Cx across FEePMR write assist element202(i.e., the capacitance across terminals M1and M2) can be set to a desirable rise/fall time Tmr (seeFIGS.4A-4B) of the synchronized write assist current Im. Resistance Rm1between terminal M1and write assist element202, and resistance Rm2between terminal M2and write assist element202, are head wiring resistances that should be minimized.

FIG.4Ais a timing diagram400showing the synchronized (ePMR) write assist current Im at402, the DC write assist current Imdc at404, and the write data current Iw at406, in accordance with aspects of this disclosure. Timing diagram400illustrates some of the programmable parameters of the synchronized write assist current402and the DC write assist current404.

In one aspect, the amplitude and polarity of synchronized write assist current402Im are programmable. In particular, the amplitude and polarity may be programmed via the pulsed or toggled current sources214(I_p) and216(I_n). In one aspect, these parameters may be set to track or mimic the amplitude and polarity of the write current Iw (406).

In another aspect, the amplitude and polarity of DC write assist current404Imdc are programmable. In particular, the amplitude and polarity may be programmed by voltage source210(Vm) of driver circuit222relative to common mode voltage source212(Vwrt_cm). In this regard, DC write assist current404may be set to have a positive polarity, as is shown inFIG.4A, or may be set to have a negative polarity, as is shown in timing diagram410ofFIG.4B.

In another aspect, the delay Td of synchronized write assist current402relative to the write data current406is programmable. In particular, the delay Td is set by programmable delay element226in preamp220(FIG.2). Delay Td may be set such that synchronized write assist current402follows write data current406(as shown inFIG.4A), or such synchronized write assist current402precedes write data current406(not shown).

In another aspect, the rise/fall time Tmr of synchronized write assist current402is programmable. In particular, the rise/fall time Tmr may be programmed by setting the rise/fall time of I_p and I_m current sources214and216(as shown inFIG.3). Capacitance Cx across FEePMR write assist element202(i.e., capacitance Cx between terminals M1and M2) can be adjusted for a fixed current rise/fall time.

FIG.5is a timing diagram500showing synchronized write assist current Im at502, with programmable overshoot pulse501having an amplitude Imosa and overshoot duration Tosd, the DC write assist current Imdc at504, and the write data current Iw at506.FIG.5illustrates additional programmable features of the Im current502.

In one aspect, synchronized write assist current502can be set to have an overshoot pulse501of programmable amplitude Imosa and programmable duration Tosd. Overshoot pulse501may mimic the overshoot pulse505of write data current506. The amplitude Imosa and duration Tosd of overshoot pulse501are programmed by dynamic wave shaping (DWS) element232based on the corresponding pattern in write data current506(i.e., overshoot pulse505of write data current506).

FIG.6Ais a timing diagram600showing the synchronized write assist current Im at602, the DC write assist current Imdc at604, and the write data current Iw at606.FIG.6Aalso shows DWS signal610(i.e., the signal output by DWS element232) having a boost portion612.FIG.6Aillustrates additional programmable features of synchronized write assist current602and write data current606.

In one aspect, the amplitude Iw of write data current606can be boosted by DWS signal610. As can be seen inFIG.6A, during boost portion612of DWS signal610, the amplitude of write data current606is boosted from an amplitude of Iw to an amplitude of dIw.

In another aspect, the amplitude OSA of the overshoot pulse605of write data current606can be boosted by DWS signal610. As can be seen inFIG.6A, during boost portion612of DWS signal610, the amplitude OSA of the overshoot pulse605is boosted to produce an overshoot pulse607having a boosted amplitude dOSA.

In another aspect, the amplitude Im of synchronized write assist current602can be boosted by DWS signal610. As can be seen inFIG.6A, during boost portion612of DWS signal610, the amplitude of synchronized write assist current602is boosted from an amplitude Im to an amplitude dim.

FIG.6Bis a timing diagram620showing the synchronized write assist current Im at602, the DC write assist current Imdc at604, and the write data current Iw at606.FIG.6Bfurther illustrates that the DWS signal610(i.e., the signal output by DWS element232) has a boost portion612.FIG.6Billustrates additional programmable features of synchronized write assist current602.

In one aspect, when synchronized write assist current602is programmed to have an overshoot pulse601of amplitude Imosa, during boost portion612of DWS signal610, the amplitude Imosa of overshoot pulse601is boosted to produce an overshoot pulse603have a boosted amplitude dImosa. This is in addition to the boosted amplitude dim also provided to synchronized write assist current602during boost portion612of DWS signal610.

FIG.7is a flowchart of a method750for programming various parameters of the synchronized and DC write assist currents, as discussed with reference to the timing diagrams ofFIGS.4A-6B, in accordance with aspects of this disclosure. In step752, the amplitude Im and polarity of the synchronized write assist current Im are programmed. Step752may be carried out, for example, based on signals received from DWS element232. In step754, the amplitude and polarity of the DC write assist current Imdc are programmed. Step754may be implemented, for example, by programming voltage source210(Vm). In step756, the delay Td of the synchronized write assist current Im relative to the write data current Iw is programmed. This may be implemented, for example, by programmable delay element226(FIG.2). In step758, the rise/fall time Tmr of the synchronized write assist current Im is programmed. This may be implemented, for example, by the setting of capacitor Cx across the FEePMR write assist element202. In step760, the amplitude Imosa and duration Tosd of the overshoot pulse for synchronized write assist current Im is programmed. Step760may be carried out, for example, based on signals received from DWS element232. In step762, the amplitude of the synchronized write assist current may be boosted by an amount dim, and the amplitude of the overshoot pulse may be boosted by an amount dImosa. Step762may be carried out, for example, based on signals received from DWS element232.

FIG.8is a circuit driver diagram700showing additional details of one possible implementation of driver circuit ofFIG.3, in accordance with aspects of this disclosure. Driver circuit700implements a classical H-driver bridge using transistor devices Q1, Q2, Q3and Q4, where devices Q1-Q4may be any state-of-the-art transistor device technology that meets speed requirements. Current flows through devices Q1and Q4when Q2and Q3are off, and vice-versa when the write data current Iw switches polarity. Terminal M1of head200is coupled to the emitter of transistor Q1and the collector of transistor Q3, and terminal M2is coupled to the emitter of transistor Q2and the collector of transistor Q4.

Voltage source710(Vm), which is coupled to the DC terminal of head200via termination resistance711(Rt), programmably sets the DC write assist current Imdc applied to the ePMR write assist element204(Rm) of head200relative to the common mode voltage source712(Vwrt_cm), which is coupled via termination resistances713and715(Rt) to terminals M1and M2of head200. As inFIG.3, termination resistances711,713and715may be matched with the impedances of their transmission lines to the head terminals to minimize voltage reflections.

Current sources714(Im+dIm) and715(Iosa+dIosa) are coupled to the emitters of transistors Q1and Q2, and together produce the positive current I_p (i.e., corresponding to current source214of driver circuit222ofFIG.3), which is toggled or pulsed with the negative current I_n (i.e., corresponding to current source216of driver circuit222) produced by current sources716(Im+dIm) and717(Iosa+dIsoa), which are coupled to the emitters of transistors Q3and Q4, to generate the synchronized write assist current Im that flows through FEePMR write assist element202of head200. Thus, the amplitude Im of the synchronized write assist current can be programmed and boosted by dim, and the amplitude OSA of the overshoot pulse can be programmed and boosted by dIosa. As previously described, the duration (Tosd) of the overshoot pulse can also be programmed. Whether and how much to program and boost the Im current and the overshoot pulse are based on decisions made by the DWS element232.

The write data current Iw is also provided to driver circuit700such that the synchronized write assist current Im can be synchronized or patterned after the write data current Iw. In particular, the positive Iw write data signal720is input to the bases of transistors Q1and Q3via programmable delay722, and the negative Iw write data signal730is input to the bases of transistors Q2and Q4via programmable delay732. The variable delays722and732synchronize the write assist current Im with the write coil current Iw as programmed by the delays.

In some aspects, it may be desirable to separate the DC write assist current from the synchronized write assist current.FIG.9Aillustrates a modified driver and head configuration for separating the DC write assist current from the synchronized write assist current. Another terminal is added to support the assist element portion of head800, such that head800how has four terminals for its assist elements: DC1, DC2, M1and M2. Voltage source810(Vm) of driver822, which is coupled to the DC1terminal of head800via a termination resistance, programmably sets the DC write assist current Imdc applied to ePMR write assist element804(Rm) relative to the common mode voltage source812(Vwrt_cm). The DC2terminal is added to head800and is grounded near either head800or driver822. In this configuration, a matched transmission line is not required between the termination resistance of voltage source810and the DC1terminal. By this configuration, the capacitance Cm across the DC terminal and the M1terminal (seeFIG.3) is eliminated since those terminals are now electrically separate.

In all other respects, the configurations of head800and driver822correspond to head200and driver circuit222ofFIG.2. That is, current sources814and816respectively generate pulsed or toggled currents I_p and I_n that are timed with the write data current Iw via application of the write data current to the driver (FIG.2). Pulsed or toggled currents I_p and I_n are coupled, respectively, to terminals M1and M2of head800via transmission lines203and201to produce a write assist current Im that is synchronized with the write data current Iw and that flows through FEePMR write assist element802(Lm). As in head200, the capacitance Cx across write assist element802can be set to a desirable rise/fall time Tmr (seeFIGS.4A-4B) of the synchronized write assist current Im. Current sources I_p (814) and I_n (816) can be programmed for a desirable rise/fall time Tmr (seeFIGS.4A-4B).

FIG.9Bis a circuit driver diagram850showing additional details of one possible implementation of the four terminal assist element driver circuit ofFIG.8A, in accordance with aspects of this disclosure. As with driver circuit700ofFIG.7, driver850implements a classical H-driver bridge using transistor devices Q1, Q2, Q3and Q4. Current flows through devices Q1and Q4when Q2and Q3are off, and vice-versa when the write data current Iw switches polarity. Voltage source860(Vm) is coupled to the DC1terminal of head800via termination resistance861(Rt) and programmably sets the DC write assist current Imdc applied to write assist element204(Rm) of head200relative to the common mode voltage source862(Vwrt_cm), which is coupled via termination resistances Rt to terminals M1and M2of head200. The DC2terminal is added to head800and is grounded near either head800or the driver circuit. In this configuration, a matched transmission line is not required between the termination resistance of voltage source860and the DC1terminal. In all other respects, the circuit driver ofFIG.8Bfunctions in the same manner as that ofFIG.7.

Any suitable control circuitry may be employed to implement the methods (e.g., methods80and750) described herein, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a data storage controller, or certain operations described above may be performed by a read channel and others by a data storage controller. In one example, the read channel and data storage controller are implemented as separate integrated circuits, and in another example, they are fabricated into a single integrated circuit or system on a chip (SoC). The control circuitry may also include a preamp circuit implemented as a separate integrated circuit, integrated into the read channel or data storage controller circuit, or integrated into an SoC.

The control circuitry (e.g., control circuitry10inFIG.1A) may comprise a microprocessor executing instructions operable to cause the microprocessor to perform the methods described herein. The instructions may be stored in any computer-readable medium. The instructions may be stored on a non-volatile semiconductor memory device, component, or system external to the microprocessor, or integrated with the microprocessor in an SoC. The instructions may be stored on a disk and read into a volatile semiconductor memory when the disk drive is powered on. The control circuitry may comprise suitable logic circuitry, such as state machine circuitry. The methods, such as, but not limited to, method80, described herein may be implemented using analog circuitry (e.g., analog comparators, timers, etc.), digital circuitry and/or a combination of analog and digital circuitry.

One or more processing devices may comprise the control circuitry10described herein and may perform one or more of the functions of the control circuitry10described herein. The control circuitry10may be abstracted away from being physically proximate to the disks and disk surfaces. The control circuitry10may be part of (or proximate to) a rack of or a unitary product comprising multiple data storage devices or may be part of (or proximate to) one or more physical or virtual servers or may be part of (or proximate to) to one or more local area or storage area networks or may be part of (or proximate to) a data center or may be hosted in one or more cloud services.

A disk drive or HDD as described herein may include a magnetic disk drive, an optical disk drive, a hybrid disk drive, or other types of disk drive. In addition, electronic devices such as computing devices, data server devices, media content storage devices, or other devices, components, or systems may comprise the storage media and/or control circuitry described herein.

The features and methods described herein may be used independently of one another or may be combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure. Certain method, event, or process blocks may be omitted in some implementations. The methods described herein are not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences. The systems and components described herein may be configured differently than described. Elements may be added to, removed from, or rearranged relative to this disclosure.

While this disclosure has been described with reference to various examples and particular implementations, these examples are illustrative, and the scope of this disclosure is not limited to them. Many variations, modifications, and additions are possible and are within the scope of this disclosure. Such variations, modifications and additions fall within the scope of the disclosure as defined in the claims that follow.