Method for fabricating semiconductor device

A method for fabricating a semiconductor device can prevent a leakage current and the decrease of threshold voltage by rounding corners of a trench. The method may include the steps of forming a pad insulating layer in a semiconductor substrate defined with an active region and a device isolation region, forming a first trench, forming polymer at inner sidewalls of the first trench, forming a second trench, removing the polymer, forming an oxide layer by thermally oxidizing the semiconductor substrate, and forming insulating layers for device isolation in the first and second trenches.

This application claims the benefit of Korean Patent Application No. 10-2005-0112998, filed on Nov. 24, 2005, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method for fabricating a semiconductor device. More particularly, the present invention relates to a method for fabricating a semiconductor device that can improve the efficiency of the device by rounding corners of a trench used in forming a Shallow Trench Isolation (STI).

2. Discussion of the Related Art

Generally, semiconductor devices such as memory devices and image sensors are fabricated by integrating a plurality of unit devices into a semiconductor substrate. To realize high-integration of a semiconductor device, a plurality of active regions are defined to correspond to a plurality of unit devices. Then, field regions are defined to form field oxide layers or device isolation layers.

To fabricate a semiconductor device, the field oxide layer may be formed in the field region. However, with the recent trend toward the high-integration of semiconductor devices, a trench may be formed in the field region. The trench is filled with an insulating layer, such as a TEOS layer, and then a CMP (Chemical Mechanical Polishing) process is performed so that the TEOS layer is left only inside the trench.

A method for forming the Shallow Trench Isolation according to the related art will be explained as follows.

FIGS. 1A to 1Eare cross sectional views of a device fabricated by a method for forming the Shallow Trench Isolation of a semiconductor device according to the related art.

As shown inFIG. 1A, a pad insulating layer2is formed on a semiconductor substrate1. Then, a photoresist3is formed on the pad insulating layer2. The pad insulating layer2may have a stacked structure of pad oxide, pad nitride and TEOS (Tetra Ethyl Ortho Silicate) oxide.

Referring toFIG. 1B, the photoresist3is selectively removed by exposure and development using a mask for defining active and field regions. Then, predetermined portions of the photoresist3corresponding to the field regions are removed.

As shown inFIG. 1C, regions in the pad insulating layer2and the semiconductor substrate1corresponding to the field regions are etched at a predetermined depth using the patterned photoresist3as a mask. Trenches4are thereby formed.

As shown inFIG. 1D, inside each of the trenches4, the semiconductor substrate1is thermally oxidized to round corners in each of the trenches4. Accordingly, a thermal oxide layer is formed in each of the trenches4.

As shown inFIG. 1E, the pad insulating layer2, the photoresist3and the thermal oxide layer are removed. Then, an O3TEOS layer is formed in an entire surface of the semiconductor substrate1, to fill the respective trenches4. Then, a CMP (Chemical Mechanical Polishing) process is applied to the formed O3TEOS layer. The O3TEOS layer is left only inside the trenches4, thereby forming the Shallow Trench Isolation6.

Unit devices may be subsequently formed in the respective active regions which are isolated from one another by the Shallow Trench Isolation6.

However, the method for fabricating the semiconductor device according to the related art has the following disadvantages.

In the method for fabricating the semiconductor device according to the related art, the thermal oxidation process is applied to round the corners of the trench formed in the field region. However, it is difficult to round the corners of the trench even though the thermal oxidation process is applied. Accordingly, a leakage current occurs in the corners of the trench, thereby causing deterioration in the semiconductor device.

SUMMARY OF THE INVENTION

An advantage of the present invention is to provide a method for fabricating a semiconductor device that prevents a leakage current and the decrease of threshold voltage by rounding corners of a trench.

To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described, a method for fabricating a semiconductor device includes steps of forming a pad insulating layer in a semiconductor substrate defined with an active region and a device isolation region, forming a first trench, by etching the pad insulating layer and the semiconductor substrate in an area corresponding to the device isolation region to a predetermined depth, forming polymer at inner sidewalls of the first trench, forming a second trench by etching the semiconductor substrate at a predetermined depth using the polymer and the pad insulating layer as a mask, removing the polymer, forming an oxide layer by thermally oxidizing the semiconductor substrate, and forming insulating layers for device isolation in the first trench and in the second trench.

DETAILED DESCRIPTION OF THE INVENTION

Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or similar parts.

A method for fabricating a semiconductor device according to an embodiment of the present invention will be described with reference to the accompanying drawings.

FIGS. 2A to 2Jare cross sectional views of a device fabricated by a method for forming the Shallow Trench Isolation of a semiconductor device according to an exemplary embodiment of the present invention.

As shown inFIG. 2A, a semiconductor substrate11is defined with a plurality of active regions and a plurality of field regions. On the semiconductor substrate11, there is a pad insulating layer12. The pad insulating layer12may have a stacked structured of pad oxide, pad nitride and TEOS (Tetra Ethyl Ortho Silicate) oxide.

Referring toFIG. 2B, a photoresist13is formed on the pad insulating layer12. Then, an exposure and development process is performed using a mask for defining the active and field regions. Predetermined portions of the photoresist13corresponding to the field regions are removed.

As shown inFIG. 2C, areas of the pad insulating layer12and the semiconductor substrate11corresponding to the field regions are etched to a predetermined depth using the patterned photoresist13as a mask. First trenches14are thereby formed.

As shown inFIG. 2D, polymer15is formed at both inner sidewalls in each of the first trenches14including the patterned photoresist13and the pad insulating layer12. The polymer15may be formed with plasma generated by fluorine gas including carbon such as CH2F2or C4F8/C5F8.

As shown inFIG. 2E, the semiconductor substrate11is etched to a predetermined depth using the photoresist13and the polymer15as a mask. Second trenches16are thereby formed.

Referring toFIG. 2HandFIG. 2I, the semiconductor substrate11including the first and second trenches is thermally oxidized so as to round the corners of the first and second trenches14and16. A thermal oxide layer17is formed on inner surfaces of the first and second trenches14and16and the surface of the semiconductor substrate11(seeFIG. 2H) or on inner surfaces of the first and second trenches14and16(seeFIG. 2I).

Referring toFIG. 2J, after removing the pad insulating layer12and the thermal oxide layer17, an O3TEOS layer or an HDP (High Density Plasma) oxide layer is formed on the entire surface of the semiconductor substrate11to fill the first and second trenches14and16. Then, the O3TEOS layer or the HDP (High Density Plasma) oxide layer is selectively removed by CMP (Chemical Mechanical Polishing), whereby the O3TEOS layer or the HDP (High Density Plasma) oxide layer remains only inside the first and second trenches14and16. A Shallow Trench Isolation18is thereby formed.

In another exemplary embodiment of the present invention, before removing the pad insulating layer12and the thermal oxide layer17, the O3TEOS layer or the HDP (High Density Plasma) oxide layer is formed on the entire surface of the semiconductor substrate11to fill the first and second trenches14and16. Then, the O3TEOS layer or the HDP (High Density Plasma) oxide layer, the pad insulating layer and the thermal oxide layer17are removed to expose the surface of the semiconductor substrate11corresponding to the active regions, thereby forming the Shallow Trench Isolation18.

Unit devices may be formed in respective active regions which are isolated from one another by the Shallow Trench Isolation18.

As mentioned above, the method for fabricating the semiconductor device has the following advantages.

In exemplary embodiments for fabricating the semiconductor device according to the present invention, the first trench is formed in the device isolation region, and the polymer is formed at the inner sidewall of the first trench. Then, the second trench is formed in the device isolation region using the polymer as a mask. That is, the corner of the trench is formed in the shape of a step. Then, after forming the corner in the shape of a step, the corner of the trench is rounded by thermally oxidizing the semiconductor substrate.

Accordingly, it is possible to prevent a leakage current and the decrease of threshold voltage in the corner of the trench in the active region. Thee efficiency of the semiconductor device is thereby improved.