Crystal laminate, semiconductor device and method for manufacturing the same

Provided is a crystal laminate including: a crystal substrate formed from a monocrystal of group III nitride expressed by a compositional formula InxAlyGa1-x-yN (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1), the crystal substrate containing at least any one of n-type impurity selected from the group consisting of Si, Ge, and O; and a crystal layer formed by a group III nitride crystal epitaxially grown on a main surface of the crystal substrate, at least any one of p-type impurity selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb being ion-implanted in the crystal layer. The crystal laminate is configured in a manner such that an absorption coefficient of the crystal substrate for light with a wavelength of 2000 nm when the crystal substrate is irradiated with the light falls within a range of 1.8 cm−1 or more and 4.6 cm−1 or less under a temperature condition of normal temperature.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority under 37 U.S.C. § 371 to International Patent Application No. PCT/JP2018/016093, filed Apr. 19, 2018, which claims priority to and the benefit of Japanese Patent Application No. 2017-105756, filed on May 29, 2017. The contents of these applications are hereby incorporated by reference in their entireties.

TECHNICAL FIELD

The present invention relates to a crystal laminate, semiconductor device, and semiconductor device manufacturing method.

BACKGROUND ART

In the production of a semiconductor device such as a light-emitting element or a high-speed transistor, a crystal laminate including a crystal substrate formed from a group III nitride monocrystal and a crystal layer formed as a result of a group III nitride crystal being epitaxially grown on a main surface of the substrate may be used in the process of the production. After an impurity such as Mg is ion-implanted in the crystal layer, annealing (activation annealing) may be carried out for the purpose of repairing crystal damage having occurred in the crystal layer or activating the ion-implanted impurity (see Patent Literature 1).

RELATED ART LITERATURE

Patent Literature

SUMMARY OF INVENTION

Problem to be Solved by Invention

The present invention aims at providing a technique whereby annealing after ion-implantation can be carried out in a short time and with accuracy.

Means for Solving Problem

In an aspect of the present invention, provided is a crystal laminate and related techniques,

the crystal laminate including:

a crystal substrate formed from a monocrystal of group III nitride expressed by a compositional formula InxAlyGa1-x-yN (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1), the crystal substrate containing at least any one of n-type impurity selected from the group consisting of Si, Ge, and O; and

a crystal layer formed by a group III nitride crystal epitaxially grown on a main surface of the crystal substrate, at least any one of p-type impurity selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb being ion-implanted in the crystal layer,

the crystal laminate being configured in a manner such that an absorption coefficient of the crystal substrate for light with a wavelength of 2000 nm when the crystal substrate is irradiated with the light falls within a range of 1.8 cm−1or more and 4.6 cm−1or less under a temperature condition of normal temperature.

Effect of Invention

According to the present invention, annealing after ion-implantation can be carried out in a short time and with accuracy, and an enhancement in the characteristics of a semiconductor device manufactured as a final product as well as an increase in semiconductor device manufacture yield can be achieved.

DETAILED DESCRIPTION OF INVENTION

Embodiment of Present Invention

1. Configuration of Crystal Laminate20

A crystal laminate (also referred to as “laminate”)20of this embodiment includes: a crystal substrate (also referred to as “substrate” or “wafer”)10formed from a monocrystal of GaN (also referred to as “GaN crystal” or “GaN monocrystal”) and having a disc shape; and a crystal layer (also referred to as “epi-layer”)11formed on a main surface of the substrate10.FIGS.1(a) and1(b)illustrate a plan view and a cross section view of the laminate20, respectively.

The substrate10may be used satisfactorily for purposes such as producing a semiconductor device such as a laser diode, LED, high-speed transistor, etc. In this regard, if the diameter D thereof is smaller than 25 mm, semiconductor device productivity is prone to decrease, so it is preferable to set the diameter to 25 mm or more. If the thickness T thereof is below 150 μm, the mechanical strength of the substrate10decreases, for example, which makes it difficult to maintain the free-standing state, so the thickness is to be 150 μm or more, preferably around 400 μm, for example. The dislocation density in the main surface of the substrate10may be 5×106/cm2or less, for example. Note, however, that the dimensions and the like presented herein are no more than examples, and this embodiment is not limited thereto. The substrate10may, for example, be obtained through a process in which hydride vapor phase epitaxy (“HVPE” hereinbelow) is used to epitaxially grow a GaN monocrystal on a seed crystal substrate formed from a GaN monocrystal, and the resulting crystal ingot that has been grown thickly is sliced so that the resultant is self-standing. Alternatively, the substrate10may be obtained through a process including: using a GaN layer provided on a different kind of substrate such as a sapphire substrate as a base layer; peeling from the different kind of substrate the crystal ingot obtained by thickly growing a GaN layer by means of a nano-mask, or the like; and removing a facet-grown crystal on the side of the different kind of substrate from the crystal ingot.

The epi-layer11may be formed by epitaxially growing a GaN monocrystal on the main surface of the substrate10. The thickness of the epi-layer11may be set to a predetermined thickness within a range of 3 μm or more and 30 μm or less, for example. The n-type impurity concentration in the epi-layer11may be lower than the n-type impurity concentration in the substrate10, for example, and may be set to a predetermined concentration within a range of 1.0×1015at·cm−3or more and 5.0×1016at·cm−3or less, for example. Note, however, that the dimensions and the like presented herein are no more than examples, and this embodiment is not limited thereto. The epi-layer11may be grown on the main surface of the substrate10by known vapor phase epitaxy such as metal-organic vapor phase epitaxy (hereinbelow, “MOVPE”) or HVPE, or known liquid phase epitaxy such as a Na flux method or an ammonothermal method, for example. As will be described later, at least a partial region of the epi-layer11is subject to ion-implantation of at least any one of p-type impurity selected from the group consisting of carbon (C), magnesium (Mg), iron (Fe), beryllium (Be), zinc (Zn), vanadium (V), and antimony (Sb). In this description, a planned region of the epi-layer11that may be subject to ion-implantation and a region thereof in which ion-implantation has already been performed are collectively referred to as an “ion-implantation region”. From the standpoint of controlling the shape of the ion-implantation region and controlling conductive characteristics, it is preferred that the p-type impurity be at least one of Mg and Zn.

The substrate10is configured such that the light absorption coefficient thereof when irradiated with light (infrared) with a wavelength of 2000 nm equivalent to the temperature of black body radiation when the temperature is about 1200° C. falls within a range of 1.8 cm−1or more and 4.6 cm−1or less, preferably 2.2 cm−1or more and 3.7 cm−1or less, for example, under a temperature condition of normal temperature, i.e. within a range of 20° C.-30° C. This is because of the substrate10containing at least any one of n-type impurity (dopant) selected from the group consisting of silicon (Si), germanium (Ge), and oxygen (O) in a concentration of 1×1018at·cm−3or more and 2.5×1018at·cm−3or less, preferably 1.2×1018at·cm−3or more and 2.0×1018at·cm−3or less, for example. The concentration of free electrons (free carriers) occurring in the substrate10as a result of adding the n-type impurity is equivalent to the concentration of the n-type impurity incorporated in the crystal lattice and activated as a donor under the temperature condition of normal temperature, and may be a concentration of 1×1018cm−3or more and 2.5×1018cm−3or less, preferably 1.2×1018cm−3or more and 2.0×1018cm−3or less, for example.

When the GaN crystal having free carriers is irradiated with infrared rays having a wavelength of 700-2500 nm, for example, absorption of the infrared rays by the free carriers (free carrier absorption) occurs, and a resulting increase in kinetic energy, and the like, causes heating of the GaN crystal. The inventors of the present invention produced samples 1-3 in the form of n-type GaN crystals in which Si concentration was adjusted such that the free carrier concentration of the samples under the temperature condition of normal temperature were 2.0×1018cm−3, 1.2×1018cm−3, and 1.0×1017cm−3, respectively, and measured the wavelength dependence of the absorption coefficient for each of the samples. Results thereof are presented inFIG.5. InFIG.5, the horizontal axis indicates the wavelength (nm) of irradiation light and the vertical axis indicates the absorption coefficient (cm−1) based on free carrier absorption. As can be seen fromFIG.5, it was confirmed that the absorption coefficients when the GaN crystals of samples 1-3 were irradiated with light with a wavelength of 2000 nm were 3.7 cm−1, 2.2 cm−1, and 0.2 cm−1, respectively.FIG.6presents the relations of the absorption coefficients at a wavelength of 2000 nm to the free electron concentration in samples 1-3. As can be seen fromFIG.6, it was confirmed that the absorption coefficients when the GaN crystals of samples 1-3 were irradiated with light with a wavelength of 2000 nm were proportional to the free carrier concentration. That is, it was confirmed that with a GaN crystal in which n-type impurity concentration (free carrier concentration) is adjusted as in samples 1 and 2, an absorption coefficient based on free carrier absorption falls within an appropriate range of 1.8 cm−1or more and 4.6 cm−1or less and the GaN crystal can be heated at a practical temperature rising rate through infrared irradiation. In contrast, it was confirmed that with a GaN crystal in which n-type impurity concentration (free carrier concentration) is adjusted as in sample 3, an absorption coefficient based on free carrier absorption is significantly lower than those of samples 1 and 2, and it is difficult to heat the GaN crystal at a practical temperature rising rate through infrared irradiation.

Even when no impurity is added (doped), intrinsic carriers, i.e. pairs of free electrons and holes, occur in a GaN crystal as an intrinsic semiconductor due to heating-based excitation. The inventors of the present invention also estimated, based on calculation, the density of intrinsic carriers occurring in a GaN crystal as an intrinsic semiconductor.FIG.7presents a result thereof. InFIG.7, the horizontal axis indicates GaN crystal temperature (° C.) and the vertical axis indicates intrinsic carrier density (cm−3). According toFIG.7, it can be confirmed that at least under a temperature condition of 1250° C. or lower, the density of intrinsic carriers occurring in the GaN crystal is lower than 1×1017cm−3, that is, lower than the n-type impurity-based free carrier concentration of the GaN crystal of sample3above.

From these measurement results, it can be confirmed that with regard to an infrared absorption coefficient of an n-type GaN crystal, at least under a temperature condition of normal temperature or higher and 1250° C. or lower, it is sufficient to take into consideration free carriers that occur due to the addition (doping) of an n-type impurity and there is no need to consider the influence of intrinsic carriers. That is, it was confirmed that the absorption coefficient of the substrate10in this embodiment is regulated almost entirely by the amount of n-type impurity added (doped) in the substrate10at least under the temperature condition of normal temperature or higher and 1250° C. or lower. In other words, it was confirmed that for keeping the absorption coefficient of the substrate10within the aforementioned range, it is crucially important to finely control the amount of n-type impurity added (doped) in the substrate10.

In order to respond to such requirements, in this embodiment, the concentration of O, which is one from among the n-type impurities that can be used herein (i.e. Si, Ge, and O) and the dosage of which is relatively difficult to control, is reduced to the possible extent, and the total concentration of Si and Ge, the dosage of which is relatively easy to control, is used to regulate the amount of n-type impurities added in the substrate10. Accordingly, the free carrier concentration in the substrate10is made equivalent to the total concentration of Si and Ge. Specifically, while the concentration of 0 added in the substrate10is reduced to a magnitude of lower than 1×1017at·cm−3, the total concentration of Si and Ge added in the substrate10is set to a magnitude of 1×1018at·cm−3or more and 2.5×1018at·cm−3or less. The inventors of the present invention already confirmed that employing the crystal growth technique described later is extremely useful for reducing the0concentration as described above. It was confirmed that, according to this technique, the concentration of each of O and carbon (C) added in the substrate10can be reduced to a magnitude of lower than 5×1015at·cm−3, and moreover, the concentration of each of boron (B) and iron (Fe) can be reduced to a magnitude of lower than 1×1015at·cm−3. Further, it was confirmed that, according to this method, the concentration of each of the other elements can also be reduced to a concentration that is below the lower limit of detection for SIMS. Besides, the actual concentration of other impurities than Si and Ge can also be considered to be below 1×1014at·cm−3in view of the fact that the free carrier concentration in the substrate10is equivalent to the total concentration of Si and Ge.

2. Semiconductor Device Manufacturing Method

Next, some processes that are carried out as part of the semiconductor device manufacturing process, i.e. processes for manufacturing the substrate10and the laminate20, ion-implantation process, annealing process, and so on, will be described in order.

Configuration of HVPE Apparatus

First, a configuration of an HVPE apparatus (vapor deposition apparatus)200used in the manufacture of the substrate10will be described in detail with reference toFIG.2.

The HVPE apparatus200includes a reaction vessel (airproof vessel)203, in the interior of which a deposition chamber (reaction chamber)201is formed. An inner cover204and a susceptor208are provided in the deposition chamber201. The susceptor208is positioned so as to be surrounded by the inner cover204and serves as a stand on which a seed crystal substrate (also referred to as a “seed substrate” below)5is to be disposed. The susceptor208is connected to a rotary shaft215of a rotary mechanism216and is configured to be capable of rotating in conformity with the driving of the rotary mechanism216.

One end of the reaction vessel203receives the connection of a gas supply pipe232afor supplying hydrogen chloride (HCl) gas in a gas generator233a, a gas supply pipe232bfor supplying ammonia (NH3) gas to the inner side of the inner cover204, a gas supply pipe232cfor supplying doping gas (described later) to the inner side of the inner cover204, a gas supply pipe232dfor supplying a gas mixture (N2/H2gas) of nitrogen (N2) gas and hydrogen gas (H2) as purge gas to the inner side of the inner cover204, and a gas supply pipe232efor supplying N2gas as purge gas in the deposition chamber201. Flow rate control devices241a-241eand valves243a-243eare provided on the gas supply pipes232a-232e, respectively, in the stated order from the upstream side. A gas generator233afor storing a Ga melt as a raw material is provided downstream of the gas supply pipe232a. The gas generator233ais provided with the nozzle249afor supplying gallium chloride (GaCl) gas, generated through a reaction between HCl gas and the Ga melt, toward, for example, the seed substrate5disposed on the susceptor208. Nozzles249b,249care connected to the downstream side of the gas supply pipes232b,232c, respectively, for supplying the various gases supplied from these gas supply pipes toward, for example, the seed substrate5disposed on the susceptor208. The nozzles249a-249care disposed so as to flow gas in a direction intersecting the surface of the susceptor208. The doping gas supplied from the nozzle249cis a gas mixture of doping raw material gas and a carrier gas such as N2/H2gas. For the doping gas, in order to limit thermal decomposition of halide gas of the doping raw material, HCl gas may be flown together. For the doping raw material gas included in the doping gas, there may be used, for example, dichlorosilane (SiH2Cl2) gas or silane (SiH4) gas in the case of silicone (Si) dope, or tetrachlorogermane (GeCl4) gas, dichlorogermane (GeH2Cl2) gas, or germane (GeH4) gas in the case of germanium (Ge) dope, but the doping raw material gas is not limited to these.

An evacuation pipe230for evacuating the inside of the deposition chamber201is provided on the other end of the reaction vessel203. The evacuation pipe230is provided with a pump (or blower)231. Zone heaters207a,207bare provided at the outer periphery of the reaction vessel203for heating the inside of the gas generator233a, the seed substrate5on the susceptor208, and the like, individually for each zone, to a desired temperature. A temperature sensor (not illustrated in the drawings) for measuring the temperature inside the deposition chamber201is provided in the reaction vessel203.

The aforementioned members constituting the HVPE apparatus200, in particular the members for forming the flow of the various gases, may be configured in the manner described below, for example, so as to enable low impurity concentration crystal growth (described later).

Specifically, as it is illustrated inFIG.2distinguishably according to hatching types, it is preferred that members formed from a material that does not contain quartz and boron be used for members that define a high-temperature region in the reaction vessel203, the high-temperature region being a region that is heated to a crystal growth temperature (e.g. 1000° C. or higher) by receiving heat radiation from the zone heaters207a,207band that comes into contact with gas being supplied onto the seed substrate5. Specifically, members formed from silicon carbide (SiC)-coated graphite, for example, may preferably be used for the members defining the high-temperature region. Meanwhile, in regions with relatively low temperatures, it is preferred to form members using high-purity quartz. In other words, in the high-temperature region in which temperature rises relatively high and which comes into contact with HCl gas, and the like, the various members may be formed using SiC-coated graphite without using high-purity quartz. More specifically, the inner cover204, susceptor208, rotary shaft215, gas generator233a, nozzles249a-249c, etc. may be formed from SiC-coated graphite. Note that there is no other choice than using quartz for a furnace core tube that is included in the reaction vessel203, and this is why the inner cover204for surrounding the susceptor208, gas generator233a, and the like is provided in the deposition chamber201. Walls of the reaction vessel203on both ends thereof, the evacuation pipe230, and the like may be formed using a metallic material such as stainless steel.

According to “Polyakov et al. J. Appl. Phys. 115, 183706 (2014)”, for example, it is disclosed that growth at 950° C. makes it possible to achieve growth of a GaN crystal having low impurity concentration. Such low-temperature growth, however, leads to deterioration in the quality of the obtained crystal, and a GaN crystal having satisfactory thermophysical properties, electrical characteristics, etc. cannot be obtained.

In contrast, in the aforementioned HVPE apparatus200in this embodiment, the members in the high-temperature region in which the temperature rises relatively high and which comes into contact with HCl gas, or the like, is formed using SiC-coated graphite; accordingly, even in a temperature range of 1050° C. or above that is suitable for GaN crystal growth, for example, supply of impurities such as Si, O, C, Fe, Cr, Ni, etc. due to quartz, stainless steel, etc. to the crystal growth site can be blocked. As a result, it is possible to achieve growth of a GaN crystal which has high purity and which demonstrates satisfactory characteristics in terms of thermophysical properties and electrical characteristics.

The members included in the HVPE apparatus200are connected to a controller280formed as a computer and are configured such that a processing procedure and processing conditions therefor (described later) are controlled by a program executed on the controller280.

Next, a series of processes in which the aforementioned HVPE apparatus200is used to epitaxially grow a GaN monocrystal on the seed substrate5and then the grown crystal is sliced so as to obtain the substrate10will be described in detail with reference toFIG.2. Operations of the units forming the HVPE apparatus200are controlled by the controller280in the description below.

The substrate10manufacturing process includes an loading step, a crystal growth step, a unloading step, and a slicing step.

Loading Step

Specifically, first, the throat of the reaction vessel203is opened and the seed substrate5is placed on the susceptor208. The seed substrate5placed on the susceptor208serves as a base (seed) for manufacturing the substrate10(described later) and is formed from a monocrystal of GaN, which is an example of a nitride semiconductor, while assuming the shape of a board.

The seed substrate5is placed on the susceptor208in such a way that the surface of the seed substrate5placed on the susceptor208, i.e. the main surface (crystal growth surface, base surface) thereof on the side facing the nozzles249a-249c, is the (0001) surface, i.e. +c face (Ga-polar surface), of the GaN crystal.

Crystal Growth Step

In this step, after introduction of the seed substrate5into the deposition chamber201is completed, the throat is closed, and while heating and evacuating the inside of the deposition chamber201, supply of either H2gas or H2gas plus N2gas into the deposition chamber201is started. Then, in a state in which a desired processing temperature and processing pressure have been reached in the deposition chamber201and the atmosphere in the deposition chamber201has been made into a desired atmosphere, the supply of HCl gas and NH3gas from the gas supply pipes232a,232bis started and GaCl gas and NH3gas are supplied onto the surface of the seed substrate5.

Accordingly, a GaN crystal is epitaxially grown in the c-axis direction on the surface of the seed substrate5and a Gan crystal6is formed, as the cross-sectional diagram thereof is illustrated inFIG.3(a). At this time, by supplying SiH2Cl2gas, Si as an n-type impurity can be added in the GaN crystal6.

In this step, it is preferred that, for the purpose of preventing thermal decomposition of the GaN crystal forming the seed substrate5, supply of NH3gas in the deposition chamber201be started at or before the time point at which the temperature of the seed substrate5reaches 500° C. Moreover, it is preferred that, for the purpose of enhancing uniformity of the GaN crystal6in-plane film thickness, or the like, this step be carried out while the susceptor208is kept being rotated.

In this step, with regard to the temperatures of the zone heaters207a,207b, it is preferred that the temperature of the heater207afor heating a section in the deposition chamber201on the upstream side, encompassing the gas generator233a, be set to a temperature of 700° C.-900° C., for example, and the temperature of the heater207bfor heating a section in the deposition chamber201on the downstream side, encompassing the susceptor208, be set to a temperature of 1000° C. or higher and 1200° C. or lower, for example. Accordingly, the temperature of the susceptor208is adjusted to a predetermined temperature within 1000° C.-1200° C. In this step, an internal heater (not illustrated in the drawings) may be used in an off state, but on condition that the temperature of the susceptor208is within the aforementioned range of 1000° C.-1200° C., temperature control using this internal heater may be carried out.

Examples of other processing conditions adopted in this step include the following.

When supplying GaCl gas and NH3gas onto the surface of the seed substrate5, N2gas serving as a carrier gas may be added from each of the gas supply pipes232a,232b. By adjusting the blow-out flow velocity of gas supplied from the nozzles249a,249bthrough the addition of N2gas, it is possible to appropriately control distribution of, for example, the amount of supply of raw material gas on the surface of the seed substrate5, and even growth speed distribution can be achieved across the entire surface. Instead of N2gas, a rare gas such as Ar gas or He gas may be added.

Unloading Step

Once the GaN crystal6having a desired thickness is grown on the seed substrate5, then in a state in which the inside of the deposition chamber201is evacuated and while NH3gas and N2gas are being supplied inside the deposition chamber201, each of the supply of HCl gas in the gas generator233a, the supply of H2gas in the deposition chamber201, and the heating by the zone heaters207a,207bis stopped. Then, when the temperature inside the deposition chamber201is lowered to or below 500° C., the supply of NH3gas is stopped, and the atmosphere in the deposition chamber201is substituted with N2gas to return the pressure to atmospheric pressure. Then, the temperature inside the deposition chamber201is lowered to a temperature of, for example, 200° C. or lower, i.e. a temperature at which the GaN crystal ingot (i.e. the seed substrate5with the GaN crystal6formed on the main surface thereof) can be unloaded from the reaction vessel203. Thereafter, the crystal ingot is unloaded from the deposition chamber201to the outside.

Slicing Step

Thereafter, by slicing the unloaded crystal ingot in a direction parallel to the GaN crystal6growth surface, for example, one or more substrates10can be obtained, as illustrated inFIG.3(b). The various constituents, properties, etc. of the substrate10are as described above, so description thereof will be skipped here. This slicing can be carried out using, for example, a wire saw or an electrical discharge machine. The thickness of the substrate10may be set to 250 μm or more, around 400 μm, for example. Thereafter, a predetermined polishing process is carried out on the surface (+c face) of the substrate10to make this surface into an epi-ready mirror surface. The reverse surface (−c face) of the substrate10is made into a lapped surface of a mirror surface.

After the substrate10is produced, then as illustrated inFIG.4(a), the epi-layer11is formed by epitaxially growing a monocrystal of GaN on the main surface of the substrate10, and the laminate20in which the substrate10and the epi-layer11are laminated is produced. As has been described above, the epi-layer11may be formed by known vapor phase epitaxy such as MOVPE or HVPE or known liquid phase epitaxy such as a Na flux method or an ammonothermal method. When HVPE is used, the HVPE apparatus200used for producing the substrate10may be used to form the epi-layer11using the aforementioned crystal growth technique. The thickness of the epi-layer11may be set to a thickness within a range of 3 μm or more and 20 μm or less, for example. The epi-layer in this embodiment is formed as a layer which, for example, does not contain n-type impurities such as Si, Ge, O, etc. and p-type impurities such as C, Mg, Fe, Be, Zn, V, Sb, etc., i.e. is formed as a non-doped GaN layer.

Once the laminate20is produced, then as illustrated inFIG.4(b), a known technique such as photolithography is used to form a mask pattern11mon the main surface of the epi-layer11. Then, at least any one of p-type impurity selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb is implanted in the exposed portion of the epi-layer11not being covered by the mask pattern11m, i.e. ion-implantation region11p. For the implantation of the p-type impurity, a known ion-implantation technique may be used, as appropriate. The shape and size of the mask pattern11m, the type, implantation depth, implantation amount, etc. of the p-type impurity and other relevant conditions may be selected, as appropriate, on the basis of the specification of the semiconductor device intended to be produced.

Protection Film12Formation Process

After the ion-implantation is completed, ashing or other known technique is used to remove the mask pattern11m. Then, chemical vapor deposition (CVD) or other known deposition technique is used to form the protective film12which covers in continuous fashion the entire main surface of the epi-layer11, as illustrated inFIG.4(c). The protective film12may be formed from a silicon nitride film (SiN film) or an aluminum nitride film (AlN film), and the thickness thereof may be a thickness within a range of 20-50 nm, for example.

Annealing Process

After the formation of the protective film12is completed, the laminate20is introduced into a heating furnace (not illustrated in the drawings) equipped with an infrared heater and an infrared lamp so as to irradiate the laminate20with infrared rays and cause the aforementioned free carrier absorption in the substrate10, thereby heating the laminate20.

The annealing may be carried out according to a processing procedure and under processing conditions such that, for example, a temperature increase from an initial temperature to an annealing temperature is performed for a period within a range from 3 to 30 seconds, then the annealing temperature is maintained for a period within a range from 20 seconds to 3 minutes, and thereafter a temperature reduction from the annealing temperature to a termination temperature is performed for a period within a range from 1 minute to 10 minutes. The termination temperature and the initial temperature may each be a temperature within a range of 500° C.-800° C., for example. The annealing temperature may be a temperature within a range of 1100° C. or higher and 1250° C. or lower, for example. The atmosphere for the annealing is set to be an inert gas atmosphere formed from N2gas, a rare gas, etc., and the pressure thereof may be set to be a pressure within a range of 100-250 kPa, for example.

By carrying out the annealing according to the aforementioned processing procedure and processing conditions, the crystal damage the epi-layer11has received due to the ion-implantation can be restored, and moreover, the p-type impurity ion-implanted can be incorporated in the crystal lattice of the epi-layer11to activate the impurity as an acceptor.

It is preferred that this annealing be performed in a state in which, as illustrated inFIG.4(d), protrusions300p, for example, a plurality (e.g. three) of which are provided on an upper surface of a retaining plate300are used to support a support-receiving surface of the laminate20(the surface thereof on the lower side in the drawing) such that the retaining plate300and the laminate20are separate from each other, i.e. the laminate20is uplifted floatingly. In contrast, the heating of the laminate20would mainly be the result of the infrared ray-based heat radiation, not the heat transfer from the retaining plate300. When the heating of the laminate20is carried out on the basis of the heat transfer from the retaining plate300(or in combination with the heat transfer), then, depending on the state of the rear surface of the laminate20and/or the state of the surface of the retaining plate300, it may be difficult to heat the laminate20uniformly over the entire surface thereof. In addition, the laminate20may warp as the annealing proceeds so that the state of contact between the laminate20and the retaining plate300gradually changes, and as a result, the laminate20heating condition may become non-uniform over the entire surface thereof. When the laminate20is heated mainly on the basis of heat radiation as in this embodiment, such problems can be eliminated. For the purpose of eliminating the influence of the heat transfer, it is preferred that the shape and/or the dimensions of the protrusions300pbe appropriately selected so that the contact area between the protrusions300pand the laminate20be a magnitude of 5% or less of the support-receiving surface of the laminate20, preferably 3% or less thereof.

Protective Film Removal Process

Once the annealing is completed, the protective film12is removed from the laminate20by etching or other such known technique, as illustrated inFIG.4(e). Thereafter, the laminate20undergoes various processing such as crystal growth, photolithography, heating, etching, etc., and the manufacture of the semiconductor device is completed.

3. Effects Obtained According to This Embodiment

One or more of the effects described hereinbelow can be obtained according to this embodiment.

a. Since the absorption coefficient of the substrate10with respect to light with a wavelength of 2000 nm under the temperature condition of normal temperature falls within the range of 1.8 cm−1or more and 4.6 cm−1or less, the annealing of the crystal using infrared rays can be carried out in a short time and with accuracy. For example, annealing that involves an increase and reduction in temperature of 500° C.->1250° C.->500° C. can be carried out within a short time of, for example, several tens of seconds to several minutes with accuracy and good reproducibility. As a result, the characteristics of the semiconductor device manufactured through the annealing after the ion-implantation can be enhanced, and manufacture yield of the semiconductor device can be made satisfactory.

When the absorption coefficient under normal temperature is smaller than 1.8 cm−1, it may be difficult to carry out the aforementioned increase and reduction in temperature in a short time and with accuracy, and the laminate20may be damaged during the annealing. For example, long-time exposure of the laminate20under a temperature condition of 1100° C. or higher may result in the elimination of the N (nitrogen) component from the substrate10and hence in the difficulty to maintain the conductive characteristics (n-type characteristics) of the substrate10. Moreover, a prolonged annealing processing duration may result in the migration of the p-type impurity ion-implanted in the epi-layer11and hence in the difficulty to control the shape of the ion-implantation region11p(p-type channel) and control the conductive characteristics. Further, the absorption coefficient under the temperature condition of normal temperature being smaller than 1.8 cm−1means that the amount of n-type impurity in the substrate10, i.e. the conductive characteristics of the substrate10, is excessively small, and it may be difficult to use the laminate20to produce a semiconductor device having a structure such that a current is applied in the thickness direction thereof, for example. Setting the absorption coefficient under normal temperature to a magnitude of 1.8 cm−1or more, as in this embodiment, makes it possible to solve the aforementioned problems.

The absorption coefficient under normal temperature exceeding 4.6 cm−1means that the amount of n-type impurity in the substrate10for achieving this absorption coefficient is larger than 2.5×1018at·cm−3and excessive, and may result in an adverse effect on the crystallinity of the substrate10, for example. For example, if the concentration of the n-type impurity added in the substrate10is excessive, the density of defects in the substrate10increases, and thus epitaxial growth on the substrate10may be difficult, characteristics of the semiconductor device produced using the laminate20may deteriorate, or the life thereof may be shortened. Setting the absorption coefficient of the substrate10to a magnitude of 4.6 cm−1or smaller, as in this embodiment, makes it possible to solve the aforementioned problems.

b. As has been described above, with regard to the efficiency of infrared absorption by the substrate10formed from the GaN crystal, at least under a temperature condition of normal temperature or higher and 1250° C. or lower, it is sufficient to take into consideration only the free carriers that occur due to the addition (doping) of the n-type impurity in the GaN crystal and there is no need to take the intrinsic carriers into consideration. In other words, the infrared absorption coefficient of the substrate10, at least under the aforementioned temperature condition, is regulated almost entirely by the amount of n-type impurity added (doped) in the GaN crystal. In this regard, according to this embodiment, processing conditions for carrying out the annealing can be easily designed, and the short annealing can be easily carried out with accuracy and good reproducibility.
c. When manufacturing the substrate10, the concentration of O, which is one from among the n-type impurities that can be used herein (i.e. Si, Ge, and O) and the dosage of which is relatively difficult to control, is reduced to the possible extent, and the total dosage of Si and Ge, the dosage of which is relatively easy to control, is mainly used to regulate the total amount of n-type impurities added in the substrate10. Accordingly, the infrared absorption coefficient of the substrate10can be kept within the aforementioned range with good reproducibility and accuracy.

Other Embodiments of Present Invention

Specific embodiments of the present invention have been described above, but the present invention is not limited the embodiments described above and may be modified in a variety of ways as long as the spirit of the invention is maintained.

To cite an example, the substrate10and the epi-layer11may be formed from, not limited to GaN but, aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium nitride (InN), indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), or other group III nitride crystal, i.e. a crystal expressed by a compositional formula InxAlyGa1-x-yN (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1). The crystal forming the substrate10and the crystal forming the epi-layer11may have the same or different compositions.

To cite another example, the n-type impurity added (doped) in the substrate10is not limited to Si. That is, the n-type impurity added in the substrate10may be Ge, or O, or any combination thereof.

<Preferable Modes of Present Invention>

Preferable modes of the present invention will be appended below.

In an aspect of the present invention, provided is

a crystal laminate including:

a crystal substrate formed from a monocrystal of group III nitride expressed by a compositional formula InxAlyGa1-x-yN (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1), the crystal substrate containing at least any one of n-type impurity selected from the group consisting of Si, Ge, and O; and

a crystal layer formed by a group III nitride crystal epitaxially grown on a main surface of the crystal substrate, the crystal layer containing at least any one of p-type impurity selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb,

the crystal laminate being configured in a manner such that an absorption coefficient of the crystal substrate for light with a wavelength of 2000 nm when the crystal substrate is irradiated with the light falls within a range of 1.8 cm−1or more and 4.6 cm−1or less under a temperature condition of normal temperature.

Preferably, in the crystal laminate of Appendix 1,

density of an intrinsic carrier within the crystal substrate is lower than 1×1017cm−3at least under a temperature condition of normal temperature or higher and 1250° C. or lower.

Preferably, in the crystal laminate of Appendix 1 or 2,

concentration of a free electron occurring within the crystal substrate due to addition of the n-type impurity is 1×1018cm−3or more and 2.5×1018cm−3or less under a temperature condition of normal temperature.

Preferably, in the crystal laminate of any one of Appendices 1 to 3,

concentration of the n-type impurity in the crystal substrate is 1×1018at·cm−3or more and 2.5×1018at·cm−3or less.

Preferably, in the crystal laminate of any one of appendices 1 to 4,

concentration of 0 in the crystal substrate is 1×1017at·cm−3or less (preferably 5×1015at·cm−3or less) and total concentration of Si and Ge in the crystal substrate is 1×1018at·cm−3or more and 2.5×1018at·cm−3or less.

In another aspect of the present invention, provided is a semiconductor device including:

a crystal substrate formed from a monocrystal of group III nitride expressed by a compositional formula InxAlyGa1-x-yN (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1), the crystal substrate containing at least any one of n-type impurity selected from the group consisting of Si, Ge, and O; and

a crystal layer formed by a group III nitride crystal epitaxially grown on a main surface of the crystal substrate, the crystal layer containing at least any one of p-type impurity selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb,

the semiconductor device being configured in a manner such that an absorption coefficient of the crystal substrate for light with a wavelength of 2000 nm when the crystal substrate is irradiated with the light falls within a range of 1.8 cm−1or more and 4.6 cm−1or less under a temperature condition of normal temperature.

In yet another aspect of the present invention, provided is

a semiconductor device manufacturing method including:

preparing a crystal laminate including a crystal substrate formed from a monocrystal of group III nitride expressed by a compositional formula InxAlyGa1-x-yN (where 0≤x≤1, 0≤y≤1, 0≤x+y≤1), the crystal substrate containing at least any one of n-type impurity selected from the group consisting of Si, Ge, and O, and a crystal layer formed by a group III nitride crystal epitaxially grown on a main surface of the crystal substrate, an absorption coefficient of the crystal substrate for light with a wavelength of 2000 nm when the crystal substrate is irradiated with the light being 1.8 cm−1or more and 4.6 cm−1or less under a temperature condition of normal temperature;

ion-implanting at least any one of p-type impurity selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb in a main surface of the crystal layer; and

heating the crystal laminate by irradiating the crystal laminate with an infrared ray.

The method of Appendix 7, wherein

the heating of the crystal laminate is performed in a condition in which a support-receiving surface of the crystal laminate is being supported at three or more locations and the crystal laminate and a retaining plate present on the support-receiving surface side of the crystal laminate are separate from each other.

The method of Appendix 7 or 8, wherein

the preparation of the crystal laminate includes a crystal growth process of loading a seed crystal substrate and a raw material including a group III element in a reaction vessel, and supplying a nitriding agent and a halide of the raw material onto the seed crystal substrate heated to a predetermined crystal growth temperature to grow a crystal of a nitride of the group III element on the seed crystal substrate, and

in the crystal growth process,

a member formed from a material in which at least a surface of the material does not contain quartz and boron is used as a member defining a high-temperature region, at least, of the reaction vessel, the high-temperature region being a region that is heated to the crystal growth temperature and that comes into contact with gas being supplied onto the seed crystal substrate.

The method of Appendix 9, wherein

preferably, a member formed from silicon carbide-coated graphite is used as the member defining the high-temperature region.

REFERENCE SIGNS LIST