Device testing method and architecture

The same testing equipment can be used to test devices operating under different protocols. Where the testing protocol is slower than the native serial protocol of the high-speed serial link connecting the device processor to the component to be tested, the link may be adapted to carry the lower speed testing protocol. This may be accomplished by adding low-speed buffers to the circuits of the serial link, or the serial link may have a native low-speed protocol in addition to its high-speed protocol connections may be made to the pathways for the native low-speed protocol, or the testing protocol may be impressed on top of native low-speed protocol. Where the driver of the device being tested has limited number of pins, the test mode can be controlled by applying power to different power supply input pins.

BACKGROUND OF THE INVENTION

This relates to testing of peripheral devices using different communications protocols.

Many kinds of portable electronic devices include processors or systems-on-a-chip (SOCs) that communicate with peripheral components such as memory, displays, or various transducers. Various different protocols are in use in such devices. For example, an older such protocol is the Serial Peripheral Interface (SPI) protocol, while a newer such protocol is the Mobile Industry Processor Interface (MIPI) protocol, which is a high-speed serial interface protocol.

In the assembly of electronic devices, the various components normally will have been tested individually in advance, but it is nevertheless important to test the communications between the components of the assembled devices. However, as new protocols for communications between components are developed, it becomes necessary to have testing equipment and methods for each protocol.

SUMMARY OF THE INVENTION

The present invention allows the same testing equipment to be used to test devices operating under different protocols. Aspects of the invention reside in testing methods, while other aspects of the invention reside in adaptations of the architecture of the devices to be tested, to allow testing and operation under different protocols.

In accordance with a first aspect of the invention, a driver circuit between a peripheral component of a device and the serial link to the processor of the device may have a limited number of signal pins. If the peripheral component were to be tested in its native protocol, this would not be an issue, because the test signals would simply be sent over the serial link in the native protocol. However, where the native protocol is not to be used, and instead a separate test circuit using a different protocol is to be connected to the processor end of the serial link in the place of the processor, then a method to control the driver circuit for testing is provided.

In accordance with this aspect of the invention, a driver circuit that has multiple different power supplies (for multiple different components with which it interfaces) may be placed into a test mode by asserting a test signal on a single pin, and then using different power supply pins to control the testing mode. Thus, there is provided a method of testing a peripheral component of an electronic device, where the peripheral component has a driver circuit with a single test input pin and a plurality of power supply input pins. The method includes asserting a test signal on the test input pin to enter a testing state, and controlling the testing state by applying power to selected one or more of the plurality of power supply input pins.

In accordance with a second aspect of the invention, where the testing protocol is slower than the native serial protocol of the high-speed serial link connecting the device processor to the component to be tested, the link may be adapted to carry the lower speed testing protocol. In a first variant, this may be accomplished by adding low-speed buffers to the circuits of the serial link. In a second variant, the serial link may have a native low-speed protocol in addition to its high-speed protocol and the adaptation of the link may be accomplished by facilitating connections to the pathways for the native low-speed protocol. In a third variant, the serial link may have a native low-speed protocol and the testing protocol may be impressed on top of that protocol. In such a case, the native low-speed protocol would operate over the link, but the data payload of the low-speed protocol signals would be signals according to the testing protocol. Thus, there is provided a method of testing a peripheral component of an electronic device, where the peripheral component has a driver circuit with an interface for receiving signals according to a first signalling protocol. The method includes applying testing signals to the interface according to a second signalling protocol.

In accordance with a third aspect of the invention, the link itself may be calibrated by sending an alternating pattern over the link. The driver circuit need detect only the alternating pattern, rather than having to recognize a random data pattern. This may be facilitated by the addition of hardware modules to both the test apparatus and the driver circuit to send and recognize, respectively, the alternating pattern. Thus, there is provided a method of testing a peripheral component of an electronic device, where the peripheral component has a driver circuit with an interface for receiving test signals. The method includes calibrating a link to the interface by applying to the link signals having a known characteristic, and measuring that characteristic in the driver circuit.

A system architecture, including both a testing apparatus and a peripheral component adapted to be tested, may incorporate one or more of the foregoing aspects of the invention.

DETAILED DESCRIPTION

In accordance with this invention, a peripheral component designed to communicate with its host processor using a first, serial protocol may be tested by a testing apparatus designed for a second serial protocol. In the embodiments described herein, MIPI and SPI are examples of two testing protocols. In those particular examples, one protocol (MIPI) is a higher-speed protocol, while the other protocol (SPI) is a lower-speed protocol. However, while certain aspects of the invention relate to the two protocols being of higher and lower speeds, other aspects of the invention may apply regardless of the relative speeds of the two protocols.

The invention may be described with reference toFIGS. 1-10, which describe, as an example, the testing, using the SPI protocol, of a display module (e.g., a liquid-crystal display (LCD) module) used in a portable device that operates under the MIPI protocol. It will be recognized, however, that references to an LCD module and to the SPI and MIPI protocols are exemplary only.

As seen inFIG. 1, a conventional testing system uses the components of device100itself to test display module101. Device100includes, in addition to display module101, a processor102and a high-speed serial interface (HSSI)104such as a MIPI interface, connecting processor102to display module101. Use of a serial interface allows, for example, the reduction of the number of wires/pins needed to transmit RGB video data to display101from 24 wires (eight bits for each of the three color signals) to six wires.

Within display module101is a display driver circuit103, which in addition to driver circuitry includes a host interface113that connects to HSSI104and a panel interface123that connects to the actual LCD panel111. Testing preferably should test not only display panel111itself, but also driver circuit103and HSSI104.

A test image or series of test images105may be input to processor102, and display panel111may be observed to see if the test image or images are faithfully reproduced. However, this testing system requires that device100already be assembled and therefore does not allow testing of display module101before assembly. If a problem is discovered in testing, device100would have to be disassembled or discarded.

Therefore, it is known to use a test system200as shown inFIG. 2, where display module101is connected, through HSSI104, to an application-specific integrated circuit (ASIC)201designed to test display module101. Testing ASIC201may operate according to a protocol other than the high-speed protocol of HSSI104, and therefore a bridge circuit202may be provided as an interface between testing ASIC201and HSSI104. A test image or series of test images105may be input to testing ASIC201, and display panel111may be observed to see if the test image or images are faithfully reproduced.

Use of the test system ofFIG. 2requires a fully functional bridge circuit202that can fully implement the serial protocol of HSSI104. This requires a complex bridge circuit202for each potential pair of protocols used in HSSI104and testing ASIC201. Moreover, as new high-speed serial protocols are developed, new bridge circuits202would have to be developed as quickly to be able to use testing ASIC201.

Therefore, in accordance with the present invention, as shown inFIG. 3, the requirements for testing ASIC201and bridge circuit202are reduced by moving more testing functionality into the component301to be tested, allowing the use of a simpler testing ASIC302, which includes a simplified high-speed interface to replace bridge circuit202.

Thus, one feature of the present invention is the incorporation in driver circuit303of some testing functionality previously provided in testing ASIC201. One such function is the ability to control the enabling of various test modes by direct inputs to driver circuit303. The number of pins available on driver circuit303is limited, and generally they are all assigned to various functions, with one pin STEST323provided for testing. However, driver circuit303may typically be an ASIC and as such, may include different components with varying power supply needs. Therefore, driver circuit303may have a plurality of power supply inputs313at, e.g., various different voltage levels. These inputs may be used normally to provide power to different components of driver circuit303, but when a test input STEST323is asserted, the application of one or more of power supply inputs313signals to driver circuit303causes driver circuit303to enter one of several different test modes.

As seen inFIG. 4, there may be n different power supply inputs313, labelled VDD1-VDDn. If STEST is not asserted (i.e., STEST=0), then power supply inputs VDD1-VDDn simply supply power to n different portions of driver circuit303. However, if STEST is asserted (i.e., STEST=1.8V, for example), then power supply inputs VDD1-VDDn may be used to determine which test mode is used to test component301including driver circuit303.

In the different power application modes shown inFIG. 4, there may be no power applied (region401), power applied only to VDD1(region402), power applied only to VDD1and VDD2(region403), power applied to VDD1through VDDn-1(region404) and power applied to all VDD1through VDDn (region405). In intermediate region406, there would be a similar progression of applying power to additional VDD inputs starting with VDD3and ending with VDDn-2.

In normal operation of driver circuit303, these different combinations of power supply inputs may invoke various operating modes as suggested by the exemplary labels (“shutdown”, “hibernation”, “standby”, “operate”) inFIG. 4. However, when STEST is asserted, each of these combinations of power supply inputs may invoke a different test mode. For example, the test modes may range from a most limited test under limited power supply through increasingly less-limited tests under increasingly greater power supply, to a full test under full power. For example, the simplest test, which may be invoked by VDD1, may be a static test in which various resistances are measured. For example, in the circuit ofFIG. 5, the VDD1power supply would be needed to turn on FET switches501so that resistances502,503could be measured using, e.g., voltmeter504.

It should be noted that although the tests are described above as increasing in degree of power and sophistication as the number of power supplies applied increases, the degree of sophistication may increase or decrease as one steps through the various test modes. Similarly, although the modes have been described as being invoked by sequentially applying additional power supply inputs without deactivating previously applied power supply inputs, the sequence of invoking different testing modes may include deactivating one or more previously applied power supplies as other power supplies are applied.

The test signals may be sent using a lower-speed protocol such as SPI. Accordingly, the invention may include adapting the SPI signalling onto HSSI104which may be configured for a higher-speed protocol such as MIPI. One embodiment600of such an adaptation according to the invention is shown inFIG. 6. In this embodiment, six-wire HSSI channel104is set up for three differential MIPI signals, CK_HS (high-speed clock), D0_HS (high-speed data0) and D1_HS (high-speed data1). In accordance with this embodiment, four of the six wires are used for four single-ended SPI signals CLK (clock), CSB (chip select), DI (input data) and DO (output data). As an example, in this particular embodiment, the SPI CLK signal is propagated on the negative leg CKN601of the MIPI CK_HS signal, the SPI CSB signal is propagated on the positive leg CKP602of the MIPI CK_HS signal, the SPI DO signal is propagated on the negative leg DON603of the MIPI D0_HS signal, and the SPI DI signal is propagated on the positive leg CKP604of the MIPI D0_HS signal.

In order to propagate the low-speed SPI signals on wires601-604, low-speed buffers605,606are added at the transmit and receive ends, respectively, of each wire601-604. For the CLK, CSB and DI signals, the transmit end is testing ASIC302, while for the DO signal, the transmit end is driver circuit303. Resistor/capacitor arrangement607is for prevention of reflection during high-speed (e.g., MIPI) operation, and therefore switches617are open during low-speed (e.g., SPI) operation. In addition, the output impedance of each differential high-speed transmitter (HS_TX)608and the input impedance of each differential receiver (HS_RX)609may be set very high (e.g., to theoretical infinity) during low-speed operation using known techniques so that they do not interfere with the low-speed signals.

Another embodiment700of an adaptation of HSSI104for low-speed operation according to the invention is shown inFIG. 7. In this embodiment, HSSI104has its own native low-speed protocol, including buffers605,606and drivers701,702. In this case, buffers605,606need not be added, but the native low-speed protocol drivers701,702should be bypassed using multiplexers705and demultiplexers706. In other respects, embodiment700may operate like embodiment600.

A third embodiment800of an adaptation of HSSI104for low-speed operation according to the invention is shown inFIG. 8. In this embodiment, HSSI104has its own native low-speed protocol, including buffers605,606and drivers801,802. In this case, unlike embodiment700, instead of bypassing drivers801,802and using buffers605,606directly, the low-speed (e.g., SPI) signals are transmitted as the data payload of the native low-speed protocol. Thus, driver801would encode the low-speed testing signals (e.g., SPI signals) from testing ASIC302into the data payload of the native low-speed protocol, and the low-speed testing signals would be extracted from the received native low-speed data by driver802. Driver802may also include Bus-Turn-Around handling to process the return DO data.

Regardless of which link adaptation600,700,800is used, link104would operate best if calibrated to match the terminal resistance of driver circuit303, which may be adjustable, to the link impedance. This may be accomplished by sending an alternating pattern (e.g., 101010 . . . ) on chip-select signal CSB with a fixed (i.e., source-synchronous) clock-data phase relationship (e.g., one bit on each rising and falling clock edge), adjusting the terminal resistance until the phase relationship is maintained. Alternatively, or additionally, the amplitude of the received signal can be measured as the terminal resistance is swept through its full range of values, and the terminal resistance can then be set to the value901at which the received amplitude900is greatest, as shown inFIG. 9.

An embodiment of a system architecture1000according to the invention is shown inFIG. 10, including an embodiment1001of driver circuit303, and an embodiment1002of testing ASIC302, connected by HSSI104. In this architecture1000, there is a respective physical layer interface1003,1004at the transmitter and receiver ends of HSSI104to handle the physical layer of the communications on HSSI104. For use during low-speed testing, e.g., under the SPI protocol, a respective low-speed interface (e.g., an SPI interface)1005,1006is provided at each end, connected to respective physical layer interface1003,1004.

In driver circuit1001, “Protocol0” interface1008is provided for operation of driver circuit1001during normal operations, under the native high-speed protocol of driver circuit1001(e.g., the MIPI protocol). Similarly, panel interface123is the same panel interface described above in connection withFIG. 1and is used for communicating between driver circuit1001and actual display panel111, whether in testing mode or normal operating mode. A “Protocol1” interface1010also is provided for use in one test mode as described below. Finally, a pattern generator1012is provided within driver circuit1001for use only in testing mode.

A controller1014in driver circuit1001uses multiplexer1016to select “Protocol0” interface1008, “Protocol1” interface1010, or a pattern generator1012as the input to panel interface123. Protocol0” interface1008would be selected during normal operation. In one testing mode, as determined, e.g., by SPI interface1007, controller1014would select Protocol1” interface1010. In that mode, test controller1009of testing ASIC1002similarly would use multiplexer1011to select a compatible Protocoll interface1013. Protocoll may be a simplified version, for testing purposes, of the native high-speed protocol (e.g., MIPI). For example, the simplified protocol might have no packet headers or footers, and the data payload might not be encoded, with the goal of simplifying the overhead, primarily in driver circuit1001, where the testing components are used essentially once and then rarely if ever used again. This simplified protocol can be used to send picture data1015from testing ASIC1002to display panel111, and the rendering of picture data1015on display panel111can be observed to evaluate the functioning of display module101, including not only display panel111but driver circuit1001itself.

One example of a simplified protocol1100which may be used as Protocoll is shown inFIG. 11. Protocol1100is a simplified version of a conventional 24-bit parallel RGB video interface protocol, which includes signals VS (vertical sync), HS (horizontal sync), DE (data enable), PCK (pixel clock), and the three 8-bit parallel color component data signals R, G and B.

The R, G and B data signals may be serialized using circuitry1200ofFIG. 12, in which the RGB data are pipelined in synchronization with the pixel clock PCK. Pixel clock PCK is synchronized by a high-speed clock1202generated using phase-locked loop1201and is used to clock serializer1203.

In the MIPI-SPI example discussed above, a MIPI receiver will be expecting high-speed differential signals at, e.g., 0.2V, and a low-power signal at, e.g., 1.2V, and is able to distinguish between them. However, in the serial interface of the invention, there are a limited number of wires available to transmit those signals. Therefore, in accordance with the invention, low-power signals such as the sync signals are embedded in the high-speed differential data signals as a form of added low-power (“LP”) signal. The first VS and first HS signals are blended with high-speed clock1202by LP blender circuit1212to produce a differential high-speed clock signal CKP/N in which peak1112represents the embedded low-power first sync signal. Similarly, the HS and DE signals are blended with serialized RGB signals1204by LP blender circuit1214to produce differential high-speed RGB data signals D0P/N, D1P/N and D2P/N, in which peaks1114represent the embedded low-power sync and enable signals.

In this arrangement, timing can be controlled as follows:(1) For high-speed clock initialization and transmission:first falling edge of VS starts state LP10the elapse of a certain number of high speed clock cycles (e.g., 64 clocks) starts state LP00a subsequent HS falling edge ends HS_prepare perioddifferential clock runs from that point onwardclock rises to LP11state by external reset(2) For high-speed data transmission:every DE falling edge starts state LP11a subsequent HS rising edge starts state LP10the elapse of a certain number of high speed clock cycles (e.g., 64 clocks) starts state LP00a subsequent DE rising edge ends HS prepare perioddifferential data runs from that point onwardresult=DE signal is embedded into high-speed RGB data in sync with the high-speed clock

In another testing mode according to the invention, controller1014can select pattern generator1012as the video source. Pattern generator1012can be small as about100logic gates and be able to generate the necessary test patterns to evaluate the functioning of at least display panel111. Providing pattern generator1012in driver circuit1001relieves the burden on link104from having to carry the test data, particularly when using a low-speed protocol. As a variant of this embodiment, pattern generator1017can be provided in testing ASIC1002. Although the test patterns would still have to be carried on link104, there would be no need to communicate the test data1015to testing ASIC1002(e.g., via a DVI, USB or RGB interface), so the burden on testing architecture1000is still reduced.

Finally, channel calibration module1018in driver circuit1001works with test controller1009of testing ASIC1002and system clock1019to calibrate the channel as described above. In particular, in actual use of component301, where the data received is always different, bit error rate testing would require transmission to component301of a pattern, recovery of the pattern by component301, loopback transmission of the recovered pattern, and comparison at the source of the looped-back data to the original pattern.

In accordance with the invention, as shown inFIG. 13, component301can include a reference pattern generator1301that generates a predetermined “known” test pattern1302, such as a simple alternating 1-0-1-0 pattern. In a test mode, that same predetermined pattern can be sent from the transmitter to component301where comparators1304can compare the recovered byte1303to pattern1302and generate an error if the patterns do not match. The number of received bits and the number of error bits can be recorded in registers. A bit error rate (BER) may be calculated as the ratio between them: BER=number of error bits/number of received bits.

As seen inFIG. 14, because the data are sent in the form of the delayed clock through the variable delay1305in the transmitter, the quality of reception can be tested by changing the delay. It may be preferable to delay the data by half a clock as in case A. If the rising and falling edges of clock move away from the middle of data bit, and closer to one end, as in case B, a certain probability of misalignment of clock and data may appears at the receiver end because of noise in the channel. Case C shows the accumulation of the edge uncertainty at the receiver end. Because the condition of the receiver may affect the number of errors caused by such delay of data against the clock edges, the quality of receiver can be measured against the amount of shift. As discussed above, the termination resistance can be varied to find the minimum phase error. If a large range of termination resistance provides the minimum phase error, the termination resistance may be set to any value in that range, but preferably may be set to the midpoint of the range.

Thus it is seen that apparatus and methods for testing a peripheral component of a device using a protocol other than the native protocol of the device, have been provided. It will be understood that the foregoing is only illustrative of the principles of the invention, and that various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention, and the present invention is limited only by the claims that follow.