Method of compensating for propagation delay of tri-state bidirectional bus in a semiconductor device

A semiconductor device for detecting and compensating for a propagation delay of a tri-state bidirectional bus connected between a master block and a plurality of slave blocks. The master block controls the slave blocks. A bidirectional bus connects the master block and each of the slave blocks and accommodates transmission of data therebetween. A unidirectional bus is connected between the master block and each of the slave blocks. The unidirectional bus accommodates the transmission of control signals generated in the master block to the slave blocks wherein the master block detects a propagation delay time between the master block and the slave blocks. The master block counts the number of clocks from a time when a selected slave block transmits an allocated symbol to a time when the allocated symbol reaches the master block such that a propagation delay time between the master block and the selected slave block is detected and stored.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims the benefit of Korean Patent Application No. 10-2007-0001691, filed on Jan. 5, 2007, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the invention relate to a semiconductor device. More particularly, embodiments of the invention relate to a method of detecting the propagation delay of a tri-state bidirectional bus connected between blocks in a semiconductor chip to compensate for detected propagation delays.

2. Discussion of Related Art

As more semiconductor devices operate at high speeds, synchronization between the semiconductor chip and external devices as well as synchronization between signal lines and blocks within the chip is increasingly important. In addition, routing and cross-talk associated with the number of signal lines in these chips becomes an issue as more and more devices are formed on such chips. Signal lines are used to connect blocks in a semiconductor chip. Buffering and trees are generally used to reduce propagation delays between blocks or to skew generations. A method of minimizing signal skews is disclosed in U.S. Pat. No. 5,987,576.

FIG. 1illustrates signal lines connected between blocks in a semiconductor device. In particular, signal lines LR1-LR4connect master block11with slave blocks12-15and are used for reading. Signal lines LW1-LW4also connect master block11with slave blocks12-15in a tree configuration and are used for writing. Buffers BR1-BR6and BW1-BW8are used to minimize propagation delay or skew associated with the signal lines. However, this method complicates chip layout and routing. Also, propagation delay or skew has a fixed time adapted to a clock period, but the clock period is adjustable. This method also limits the operating frequency and is less accommodating to changes in operating processes and environment.

When a tri-state bidirectional bus is used for connecting signal lines between blocks in a semiconductor device, these signal lines are commonly used for reading and writing. This use combination greatly reduces the number of signal lines. However, when using a tri-state bidirectional bus, signals cannot be amplified via buffering. Therefore, a tri-state bidirectional bus may be used between adjacent blocks, but propagation delays and increased transition times limit its use between distant blocks. In particular, when a unidirectional and a bidirectional bus are used together, synchronization becomes difficult between the corresponding signals.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention are directed to a semiconductor device utilizing a tri-state bidirectional bus capable of synchronizing signals of a unidirectional bus and a bidirectional bus. In an exemplary embodiment, the semiconductor device includes a plurality of slave blocks, a master block, a bidirectional bus and a unidirectional bus. The master block controls the slave blocks. The bidirectional bus is connected between the master block and each of the slave blocks to transmit data there between. The unidirectional bus is connected between the master block and each of the slave blocks and accommodates the transmission of control signals generated in the master block to the slave blocks where the master block detects a propagation delay time between the master block and the slave blocks.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 2is a schematic block diagram of a semiconductor device including a plurality of slave blocks22-25, a master block21for controlling the slave blocks22-25. The semiconductor device also includes tri-state bidirectional bus L1connected between master block21and slave blocks22-25, and unidirectional buses L2and L3connected between master block21and slave blocks22-25. Slave blocks22-25and master block21are synchronized to operate with a clock signal CLK. In particular, master block21detects a propagation delay time of tri-state bidirectional bus L1between the master block21and each of the slave blocks22-25. Bidirectional bus L1transmits data between master block21and slave blocks22-25. In this manner, data of master block21is transmitted to slave blocks22-25via bidirectional bus L1, and data of slave blocks22-25is also transmitted to master block21via bidirectional bus L1. Unidirectional buses L2and L3transmit control signals, such as enable signal EN, initial signal INIT, and acknowledge signal ACK, generated from master block21to slave blocks22-25. Initial signal INIT and acknowledge signal ACK are used for detecting a propagation delay time associated with tri-state bidirectional bus L1between master block21and each of the slave blocks22-25. Enable signal EN is used for enabling slave blocks22-25.

FIG. 3is a timing diagram showing a method and operation of detecting a propagation delay time by a master block in the semiconductor device illustrated inFIG. 2where SB represents the slave blocks and MB represents the master block. Master block21generates an initial signal INIT and transmits this signal to slave blocks22-25via unidirectional bus L3. One of the slave blocks22-25is selected based on initial signal INIT. When one of the slave blocks22-25is selected, the selected slave block SB transmits an allocated symbol SYM to master block21(MB) via bidirectional bus L1. Master block21counts the number of clock signals CLK from a time when the selected slave block SB transmits symbol SYM to a time when symbol SYM reaches master block MB so as to detect and store a propagation delay time between the master block MB and the selected slave block SB.

The detected propagation delay time is calculated as the number of clocks CLK and is represented as the minimum number of clocks which is greater than an actual propagation delay time. For example, the actual propagation delay time TPD is shown inFIG. 3which is defined by the number of clocks CLK (about 1.5) from the time when slave block SB transmits symbol signal SYM to a time when the symbol SYM reaches master block MB. A counter of master block MB counts the number of clocks as 2 which corresponds to the detected propagation delay time CNT. Next, master block MB recognizes received symbol SYM and generates acknowledge signal ACK transmitted to the selected slave block SB via unidirectional bus L3. The selected slave block SB maintains a hold state in response to acknowledge signal ACK. The propagation delay time between the master block MB and the selected slave block SB is detected and the detected propagation delay time CNT is stored in a register of master block MB.

FIG. 4is a timing diagram showing a method and operation of detecting propagation delays between master block21and slave blocks22-25. Slave block22(SB_1) illustrated inFIG. 2is selected by an initial signal INIT[1] generated by master block21(MB). The number of clocks (CNT=2) corresponding to a propagation delay time TPD1between master block MB and slave block SB1is counted. The number of clocks (CNT=2) is stored as a detected propagation delay time between master block MB and slave block SB_1in the master block MB register. Slave block23(SB_2) is selected by an initial signal INIT[2] generated in master block MB. Then, the number of clocks (CNT=3) corresponding to a propagation delay time TPD2between master block MB and slave block SB_2is counted and the number of clocks is stored in the master block register as a detected propagation delay time between master block MB and slave block SB_2. Slave block24(SB_3) illustrated inFIG. 2is selected by an initial signal INIT[3] generated in the master block MB. The number of clocks CNT=4 corresponding to a propagation delay time TPD3between the master block MB and the slave block SB_3is counted and stored as a detected propagation delay time in the register of the master block MB. Slave block25(SB_n) illustrated inFIG. 2is selected by an initial signal INIT[n] generated in the master block MB. Then, the number of clocks CNT=6 corresponding to a propagation delay time TPDn between the master block MB and the slave block SB_n is counted and stored as a detected propagation delay time in the register of the master block MB.

FIG. 5is a timing diagram illustrating a method and operation for compensating for the propagation delay time detected in the semiconductor device illustrated inFIG. 2. Master block21(MB) transmits data signal DATA1to a first selected slave block22(SB_1) via bidirectional bus L1. Data signal DATA1is delayed by the propagation delay time TPD1between the master block MB and slave block SB_1before reaching slave block SB_1. In order to compensate for the propagation delay time TPD1, master block MB generates an enable signal EN delayed by the detected number of clocks CNT=2 and stored in the register (from a time when the data signal DATA1is transmitted). Enable signal EN is transmitted to the first selected slave block SB_1via unidirectional bus L2. Here, it is presumed that there is little propagation delay time of unidirectional bus L2and the use of a buffer can further decrease the propagation delay time of the unidirectional bus. In this manner, data signal DATA1transmitted via bidirectional bus L1may be synchronized with enable signal EN transmitted via unidirectional bus L2. Enable signal EN is approximately located at the center of data signal DATA1reaching slave block SB_1. Accordingly, slave block SB_1may latch the data signal DATA1in response to enable signal EN in a stable manner.

Master block21(MB) transmits data DATA2to the second selected slave block23(SB_2) via bidirectional bus L1. Data signal DATA2is delayed by the propagation delay time TPD2between the master block MB and slave block SB_2, before reaching slave block SB_2. In order to compensate for the propagation delay time TPD2, master block MB generates an enable signal EN delayed by the number of clocks CNT=3 detected and stored in the register. The enable signal EN is transmitted to the second selected slave block SB_2via unidirectional bus L2. Data signal DATA2transmitted via bidirectional bus L1may be synchronized with enable signal EN transmitted via unidirectional bus L2. In this manner, enable signal EN is approximately located at the center of data DATA2when reaching slave block SB_2. Accordingly, slave block SB_2may latch data signal DATA2in response to the enable signal EN in a stable manner.

Master block21(MB) transmits data signal DATA3to the third selected slave block24(SB_3) via bidirectional bus L1. Data signal DATA3is delayed by the propagation delay time TPD3between master block MB and slave block SB_3before reaching slave block SB_3. In order to compensate for the propagation delay time TPD3, master block MB generates enable signal EN delayed by the number of clocks CNT=4 detected and stored in the register. The enable signal EN is transmitted to the third selected slave block SB_3via unidirectional bus L2. In this manner data DATA3transmitted via bidirectional bus L1may be synchronized with enable signal EN transmitted via unidirectional bus L2. The enable signal EN is approximately located at a center of data DATA3when reaching slave block SB_3. Accordingly, slave block SB_2may latch data signal DATA3in response to enable signal EN in a stable manner. Master block21(MB) transmits data DATAn to the fourth selected slave block25(SB_n) via bidirectional bus L1. Data signal DATAn is delayed by the propagation delay time TPDn between master block MB and slave block SB_n before reaching slave block SB_n. In order to compensate for propagation delay time TPDn, master block MB generates enable signal EN delayed by the number of clocks CNT=6 detected and stored in the register. Enable signal EN is transmitted to the final selected slave block SB_n via unidirectional bus L2. In this manner, data DATAn transmitted via bidirectional bus L1may be synchronized with enable signal EN transmitted via unidirectional bus L2. Enable signal EN is approximately located at the center of data DATAn when reaching slave block SB_n. Accordingly, slave block SB_n may latch data DATAn in response to enable signal EN in a stable manner.

FIG. 6is a block diagram illustrating a more detailed structure of the master block and the slave blocks illustrated inFIG. 2. Master block MB includes controller211, symbol detector212, counter213, register214, output buffer215, and input buffer216. Controller211generates initial signal INIT, acknowledge signal ACK, and enable signal EN. Symbol detector212receives and detects symbol SYM transmitted via bidirectional bus L1and input buffer216. Counter213counts the number of clocks N from a time when the selected slave block SB transmits an allocated symbol SYM to the time when allocated symbol SYM reaches master block MB in response to an output of symbol detector212. Register214stores the number of clocks N in response to a register enable signal REN generated by controller211and provides the stored number of clocks N to controller211. Output buffer215receives data DOUT generated in master block MB to output the data DOUT to bidirectional bus L1. Input buffer216receives symbol SYM or data DIN transmitted from slave block SB via bidirectional bus L1. Slave block SB includes symbol generator221, selector222, output buffer223, and input buffer224.

Symbol generator221is controlled by initial signal INIT, acknowledge signal ACK, and enable signal EN. Symbol generator generates allocated symbol SYM in response to initial signal INIT. Selector222selects one of the symbol SYM and data DOUT generated in slave block SB. Output buffer223receives the output from selector222supplies it to bidirectional bus L1. Input buffer224receives data transmitted from the master block MB via bidirectional bus L1. In this manner, when unidirectional and bidirectional buses are used together, a signal of the unidirectional bus can easily be synchronized with a bidirectional bus signal.