Binary logic unit and method to operate a binary logic unit

A binary logic unit to apply any Boolean operation on two input signals (va, vb) is described, wherein any Boolean operation to be applied on the input signals (va, vb) is defined by a particular combination of well defined control signals (ctl0, ctl1, ctl2, ctl3), wherein the input signals (va, vb) are used to select a control signal (ctl0, ctl1, ctl2, ctl3) as an output signal (vo) of the binary logic unit representing the result of a particular Boolean operation applied on the two input signals (va, vb). Furthermore a method to operate such a binary logic unit is described.

BACKGROUND OF THE INVENTION

The invention relates to a binary logic unit to apply any desired Boolean operation on two input signals plus a method to operate such a binary logic unit.

A binary logic unit used to apply logic Boolean operations on two input signals va, vbcomprises a plurality of basic logic gates like AND, OR, XOR and XNOR gates, each one consisting of one or more transistors. Table 1, shown inFIG. 8, gives an overlook over the Boolean operations that can be performed on two input signals va, vbby a binary logic unit.

A binary logic unit1according to the state of the art is shown inFIG. 1. It is a static CMOS realization of thirty-eight transistors that are arranged to different logic gates2. The logic gates2are a 4:1 multiplexer3, a 2:1 multiplexer4, two XOR-gates5,6, and two inverters7,8. The logic gates2are controlled by control signals ctl switching the transistors of the logic gates2in a way that an output signal voof the binary logic unit1is achieved equivalent to the result of a desired Boolean operation applied on the input signals va, vb.

The principle of such a binary logic unit is shown inFIG. 2. Thereby the two input signals va, vbare linked to a number of combinatory circuits11equal to the number of Boolean operations to be applied on the two input signals va, vb. The results of these Boolean operations are applied on the data inputs of a multiplexer12. A control signal ctl applied on the control input of the multiplexer12selects the result according to the desired Boolean operation.

RegardingFIG. 1, in order to implement this principle, the input signal vais applied on the XOR-gate5and the input signal vbis applied on the XOR-gate6and together with its inverse on two data inputs of the 4:1 multiplexer3. Two static signals marked with ‘1’ and ‘0’ are applied on the remaining two data inputs of the 4:1 multiplexer3. The 4:1 multiplexer3is controlled by a pair of control signals applied on the control inputs of the 4:1 multiplexer3. Each of the XOR-gates5,6is also controlled by a control signal respectively. The 2:1 multiplexer4is controlled by the output of the XOR-gate5wherein the outputs of the other XOR-gate5and of the 4:1 multiplexer3are fed in the data inputs of the 2:1 multiplexer4. The output signal voof the 2:1 multiplexer4is the result of a Boolean operation selected by the control signals and applied on the input signals va, vb.

It can be seen that the implementation of a binary logic unit according to the state of the art requires many transistors and in consequence of this also a large silicon area. Thereby in modern microprocessors power consumption particularly due to leakage power is a huge problem and is to be reduced. According to a rule of thumb, leakage power is a function of silicon area. The larger the silicon area required, the higher the leakage power suffered.

As a binary logic unit performs on each input bit in any logic unit within a microprocessor, like e.g., a vector unit such as VMX used in IBM PowerPC and POWER processors, a realization for a single bit with reduced power consumption and with a reduced requirement of silicon area would have a noticeable impact on the total power consumption and size of any chip.

SUMMARY OF THE INVENTION

It is therefore an object, of at least one embodiment, of the invention to provide a binary logic unit with reduced silicon area requirement consequence of which is a reduced power consumption and leakage power. It is also an object of the invention to provide a method to operate such a binary logic unit.

In an embodiment of the invention, the invention comprises a binary logic unit to apply any desired Boolean operation on input signals wherein any desired Boolean operation to be applied on the input signals of the binary logic unit is defined by a particular combination of well defined control signals that are fed into the binary logic unit, wherein the input signals are used to select a control signal as an output signal of the binary logic unit representing the result of a particular Boolean operation applied on the input signals.

In general, the binary logic unit according to the invention works according to a multiplexer principle, wherein data and control inputs of the multiplexer are interchanged in a way that the input signals are applied on the control inputs of the multiplexer and the control signals are applied on the data inputs of the multiplexer, and wherein depending on a desired Boolean operation defined by a particular combination of the control signals, the input signals are used to select a control signal as an output signal of the multiplexer representing the result of the particular Boolean operation applied on the input signals.

Applying the multiplexer principle on a binary logic unit, in combination with interchanging control and data inputs, allows to significantly reduce the number of transistors required to implement a binary logic unit. Thereby silicon area requirement of a binary logic according to the invention and in consequence of that power consumption and leakage power are reduced.

In a preferred embodiment of the invention, the binary logic unit is implemented with one 4:1 multiplexer, wherein four well defined control signals are used to specify any Boolean operation to be applied on two input signals, wherein each one of the four control signals is applied on one of the four data inputs of the multiplexer respectively and each one of the two input signals is applied on one of the two control inputs of the multiplexer respectively and wherein the input signals select one of the control signals applied on the data inputs as an output signal representing the result of a particular Boolean operation specified by the control signals.

In another embodiment of the invention, the binary logic unit is implemented with three 2:1 multiplexers, a first and a second one arranged in parallel to each other and a third one arranged in series to the first and second ones, wherein a first input signal and its inverse are applied on the control inputs of the first and second multiplexer arranged in parallel to each other, a first pair of control signals is applied on the signal inputs of the first of the two parallel multiplexers and a second pair of control signals is applied on the signal inputs of the second of the two parallel multiplexers, wherein a second input signal and its inverse are applied on the control inputs of the third multiplexer arranged in series to the first and second multiplexer, wherein the output signal of the first multiplexer is applied on a first data input of the third multiplexer, wherein the output signal of the second multiplexer is applied on a second data input of the third multiplexer, and wherein the output of the third multiplexer represents the result of a Boolean operation specified by the four control signals that is applied on the two input signals. Using three 2:1 multiplexers represents an implementation of the binary logic according to the invention that requires a very small number of transistors. Using a suitable selection of control signals for implementing the binary logic with three 2:1 multiplexers requires eighteen transistors only in order to generate an output signal representing the result of any Boolean operation applied on the two input signals. This is equivalent to a saving of 53% of transistors, silicon area and leakage power compared with the state of the art. Thereby it is important that a 4:1 multiplexer can be implemented with three 2:1 multiplexers as described above.

In an additional embodiment of the invention, the binary logic unit is implemented with three AND/OR-gates each one consisting of two AND-gates arranged parallel to each other and one OR-gate arranged in series to the AND-gates. A first and a second AND/OR-gate of the binary logic unit are arranged parallel to each other and a third one is arranged in series to the first and second one. A first control signal and a first input signal are applied on the inputs of a first AND-gate of the first AND/OR-gate. A second control signal and the inverse of the first input signal are applied on the inputs of a second AND-gate of the first AND/OR-gate. A third control signal and the first input signal are applied on the inputs of a first AND-gate of the second AND/OR-gate. A fourth control signal and the inverse of the first input signal are applied on the inputs of a second AND-gate of the second AND/OR-gate. The output of the first AND/OR-gate and a second input signal are applied on a first AND-gate of the third AND/OR-gate and the output of the second AND/OR-gate and the inverse of the second input signal are applied on a second AND-gate of the third AND/OR-gate. An output signal of the third AND/OR-gate represents the result of a Boolean operation specified by the four control signals that is applied on the two input signals. Implementing the binary logic unit according to the invention with AND/OR-gates allows reducing the number of transistors required to twenty-eight. This is equivalent to a saving of 26% of transistors, silicon area and power leakage compared with the state of the art.

In yet another embodiment of the invention, the binary logic unit is implemented with an evaluation network of a dynamic gate. In the case of complex gates like a 4:1 multiplexer dynamic gates have comparable smaller footprint. Furthermore dynamic gates allow reducing the number of transistors required to nineteen. This is equivalent to a saving of 50% of transistors, silicon area and power leakage compared with the state of the art.

According to another embodiment of the invention, the evaluation network of a dynamic gate consists of four parallel rows of three serial transistors respectively, wherein in each row a first transistor is switched by one of the control signals respectively, a second one by a first input signal or its inverse and a third one by a second input signal or its inverse. Implementing the binary logic unit according to the invention with such an evaluation network of a dynamic gate allows to reduce the number of transistors required to twenty-one. This is equivalent to a saving of 45% of transistors, silicon area and power leakage compared with the state of the art.

According to another embodiment of the invention, the evaluation network of a dynamic gate consists of four parallel rows of two serial transistors respectively, wherein in each row a first transistor is switched by one of the control signals respectively and a second transistor is switched by a first input signal or its inverse, wherein the four parallel rows are grouped to a first and a second pair, each one comprising one row with a transistor switched by the first input signal and one row with a transistor switched by the inverse of the first input signal respectively, wherein each pair is arranged in series to a third transistor respectively, wherein the third transistor arranged in series to the first pair is switched by a second input signal and the third transistor arranged in series to the second pair is switched by the inverse of the second input signal. Implementing the binary logic unit according to the invention with such an evaluation network of a dynamic gate allows reducing the number of transistors required to nineteen. This is equivalent to a saving of 50% of transistors, silicon area and power leakage compared with the state of the art.

In a second aspect, the invention provides a method to operate a binary logic unit mentioned above to apply any Boolean operation on two input signals, said method comprises the steps of:i) well defining any Boolean operation to be applied on two input signals by particular combinations of well defined control signals, andii) selecting a control signal as an output signal of the binary logic unit by the input signals, which control signal represents the result of a particular Boolean operation applied on the two input signals.

Thereby the control signals are well defined in a way, that a control signal selected as an output signal by any particular pair of input signals represents the result of a desired Boolean operation applied on the two input signals.

The method according to the invention allows a realization of a binary logic unit with less transistors, consequence of which the binary logic unit according to the invention has a reduced silicon area requirement, reduced cost and reduced power consumption.

According to a preferred embodiment of the method according to the invention, control and data inputs of a binary logic unit are interchanged in a way that the input signals are applied on the control inputs and control signals specifying a desired Boolean operation are applied on the data inputs, wherein the input signals select a particular control signal representing the result of the particular desired Boolean operation applied on the input signals.

According to another embodiment of the method according to the invention, the binary logic works according to a multiplexer principle, wherein four control signals of which particular combinations specify any Boolean operation to be applied on the input signals are applied on four data inputs of the multiplexer and the input signals are applied on two control inputs of the multiplexer in order to select a particular control signal representing the result of a particular desired Boolean operation applied on the input signals as an output signal of the multiplexer.

DETAILED DESCRIPTION

In a binary logic unit according to the invention, any desired Boolean operation to be applied on the input signals of the binary logic unit is defined by a particular combination of well defined control signals that are fed into the binary logic unit. The input signals are used to select one control signal of a particular combination of control signals that define a particular desired Boolean operation to be applied on the input signals as an output signal of the binary logic unit. The selected control signal that is the output signal represents the result of the particular Boolean operation applied on the two input signals. The binary logic unit according to the invention works according to a multiplexer principle. Thereby data and control inputs of the multiplexer are interchanged in a way that the input signals are applied on the control inputs of the multiplexer and the control signals are applied on the data inputs of the multiplexer. Depending on a desired Boolean operation defined by a particular combination of the control signals, the input signals are used to select a control signal as an output signal of the multiplexer representing the result of the particular Boolean operation applied on the two input signals.

A binary logic unit100shown inFIG. 3is implemented with one 4:1 multiplexer300. Four well defined control signals ctl are used to specify any Boolean operation to be applied on two input signals va, vb. Each one of the four control signals ctl is applied on one of the four data inputs301of the multiplexer300respectively and each one of the two input signals va, vbis applied on one of the two control inputs302of the multiplexer300respectively. Within the multiplexer300the input signals va, vbapplied on the control inputs302select one of the control signals ctl applied on the data inputs301as an output signal vorepresenting the result of a particular Boolean operation specified by the control signals ctl.

Table 2, depicted onFIG. 8, gives an overlook over the Boolean operations executable by a binary logic unit according to the invention plus an overlook over well-defined control signals ctl0, ctl1, ctl2, ctl3specifying the particular Boolean operations. The control signals ctl0, ctl1, ctl2, ctl3specify the Boolean operations in a way that when selecting a particular control signal ctl0, ctl1, ctl2, ctl3by a particular pair of input signals va, vbwithin the binary logic unit, the control signal ctl0, ctl1, ctl2, ctl3selected represents the result of a particular Boolean operation applied on said pair of input signals va, vb.

Applying the multiplexer principle on a binary logic unit in combination with interchanging control and data inputs allows significantly reducing the number of transistors required to implement a binary logic unit. Due to this silicon area requirement of a binary logic according to the invention and in consequence of that power consumption and leakage power are reduced.

A binary logic unit110shown inFIG. 4is implemented with three 2:1 multiplexers310,320,330. A first310and a second multiplexer320are arranged in parallel to each other and a third multiplexer330is arranged in series to the first310and second320ones. A first input signal vaand its inverse !vaare applied on the control inputs311,312of the first multiplexer310and on the control inputs321,322of the second multiplexer320. A first pair of control signals ctl0, ctl1is applied on the signal inputs313,314of the first multiplexer310and a second pair of control signals ctl2, ctl3is applied on the signal inputs323,324of the second multiplexer320. A second input signal vband its inverse !vbare applied on the control inputs331,332of the third multiplexer330arranged in series to the first310and second multiplexer320. The output signal vo1of the first multiplexer310is applied on a first data input333of the third multiplexer330. The output signal vo2of the second multiplexer320is applied on a second data input334of the third multiplexer330. The output voof the third multiplexer330represents the result of a Boolean operation specified by the four control signals ctl0, ctl1, ctl2, ctl3that is applied on the two input signals va, vb. Using three 2:1 multiplexers310,320,330represents an implementation of the binary logic110according to the invention that requires a very small number of transistors. Depending on a skilled selection of the control signals ctl0, ctl1, ctl2, ctl3implementing the binary logic with three 2:1 multiplexers310,320,330only requires eighteen transistors in order to generate an output signal vorepresenting the result of any Boolean operation applied on the two input signals va, vb. This is equivalent to a saving of 53% of transistors, silicon area and power leakage compared with the state of the art.

A binary logic unit140shown inFIG. 5is implemented with three AND/OR-gates340,350,360. Each AND/OR-gate340,350,360consists of two AND-gates341,342,351,352,361,362arranged parallel to each other and one OR-gate343,353,363arranged in series to the AND-gates341,342,351,352,361,362. A first340and a second AND/OR-gate350of the binary logic unit140are arranged parallel to each other. A third AND/OR-gate360of the binary logic unit140is arranged in series to the first340and second350AND/OR-gates. A first control signal ctl0and a first input signal vaare applied on the inputs344,345of a first AND-gate341of the first AND/OR-gate340. A second control signal ctl1and the inverse of the first input signal !vaare applied on the inputs346,347of a second AND-gate342of the first AND/OR-gate340. A third control signal ctl2and the first input signal vaare applied on the inputs354,355of a first AND-gate351of the second AND/OR-gate350. A fourth control signal ctl3and the inverse of the first input signal !vaare applied on the inputs356,357of a second AND-gate352of the second AND/OR-gate350. The output vo1of the first AND/OR-gate340and a second input signal vbare applied on the inputs364,365of a first AND-gate361of the third AND/OR-gate360. The output vo2of the second AND/OR-gate and the inverse !vbof the second input signal are applied on the inputs366,367of a second AND-gate363of the third AND/OR-gate360. The output signal voof the third AND/OR-gate360represents the result of a Boolean operation specified by the four control signals ctl0, ctl1, ctl2, ctl3that is applied on the two input signals va, vb. Implementing the binary logic unit140with AND/OR-gates340,350,360allows to reduce the number of transistors required to twenty-eight. This is equivalent to a saving of 26% of transistors, silicon area and power leakage compared with the state of the art.

It is also thinkable to implement the binary logic unit according to the invention with an evaluation network400,500of a dynamic gate as shown inFIGS. 6 and 7.

The binary logic unit170shown inFIG. 6shows a first implementation with an evaluation network400of a dynamic gate. The evaluation network400of a dynamic gate consists of four parallel rows410,420,430,440of three serial transistors411,412,413,421,422,423,431,432,433,441,442,443respectively. In each row410,420,430,440a first transistor411,421,431441is switched by one of the control signals ctl0, ctl1, ctl2, ctl3respectively. A second transistor413,423,433,443within each row410,420,430,440is switched by a first input signal vaor its inverse !va. Thereby the transistors413,433are switched by the first input signal vaand the transistors423,443by its inverse !va. A third transistor412,422,432,442within each row410,420,430,440is switched by a second input signal vbor its inverse !vb. Thereby the transistors412,422are switched by the second input signal vband the transistors423,424by its inverse !vb. Implementing the binary logic unit170according to the invention with such an evaluation network400of a dynamic gate allows to reduce the number of transistors required to twenty-one. This is equivalent to a saving of 45% of transistors, silicon area and power leakage compared with the state of the art.

The evaluation network500of a dynamic gate of the binary logic unit180shown inFIG. 7consists of four parallel rows510,520,530,540of two serial transistors respectively. In each row510,520,530,540a first transistor511,521,531,541is switched by one of the control signals ctl0, ctl1, ctl2, ctl3respectively and a second transistor512,522,532,542is switched by a first input signal vaor its inverse !va. The four parallel rows510,520,530,540are grouped to a first550and a second pair560, each one comprising one row510,530with a transistor512,532switched by the first input signal vaand one row520,540with a transistor522,542switched by the inverse !vaof the first input signal respectively. Each pair550,560is arranged in series to a third transistor551,561respectively, wherein the third transistor551arranged in series to the first pair550is switched by a second input signal vband the third transistor561arranged in series to the second pair560is switched by the inverse !vbof the second input signal. Implementing the binary logic unit180according to the invention with such an evaluation network500of a dynamic gate allows reducing the number of transistors required to nineteen. This is equivalent to a saving of 50% of transistors, silicon area and power leakage compared with the state of the art.

It is important to mention, that the invention allows realization of a binary logic unit with a very small number of transistors.

The implementations represent a new static CMOS realization of binary logic units. The implementations of the binary logic units according to the invention are based e.g. on AND-OR logic gates as opposed to XOR-gates in combination with multiplexers according to the state of the art.

When the circuit is mapped on a CMOS technology either an AOI-OAI logic gate will be most suited assuming a static circuit family. Compared to state of the art, using AOI-OAI (AND OR INVERT—OR AND INVERT) logic gates has the advantage of reducing the transistor count by 26% (FIG. 5). This can be directly translated to an approximately proportional decrease in area and power requirement. This reduction is achieved with an approximately equal loading of the input operands, a comparable propagation delay of the timing critical path and the same number of control signals, i.e., without any disadvantage compared to the state-of-the-art. However, regarding power and area requirement a benefit of 26% is approximated using total transistor count.

As additional advantage is the reduced delay of the input operand vbto the output as compared to the paths of vaor vbwithin a binary logic unit according to the state of the art.

It is important to mention, that the foregoing described above remains the same when applying the invention on situations where a Boolean operation is applied on three or more input signals. Thereby it is also advantageous to use well defined combinations of well defined control signals to define a particular Boolean operation to be applied on the input signals and to select one of the control signals by the input signals as an output signal representing the result of the particular Boolean operation applied on the input signals. Doing so also reduces cost, power consumption and requirement of silicon area in cases where an implementation for applying a Boolean operation on three or more input signals is required.