Semiconductor device and method fabricating the same

A semiconductor device is provided. The semiconductor device includes a substrate, a conductive pattern, a support structure, a first conductive layer, and a dielectric layer. The conductive pattern extends vertically from the substrate. The support structure extends from an outer sidewall of the conductive pattern. The first conductive layer covers the conductive pattern. The dielectric layer at least covers the first conductive layer and the support structure.

FIELD

The present disclosure relates to semiconductor fabrication and more specifically to a capacitor having a lower electrode with a multiple-layers structure and the fabricating method thereof.

BACKGROUND

As the size of memory devices continues to become smaller, the memory capacitance is restricted due to the structure of the capacitor. In a metal-insulator-metal (MIM) structure, the limited effective area of the lower electrode leads to reduced performance of memory device.

SUMMARY

The following presents a summary of examples of the present disclosure in order to provide a basic understanding of at least some of its examples. This summary is not an extensive overview of the present disclosure. It is not intended to identify key or critical elements of the present disclosure or to delineate the scope of the present disclosure. The following summary merely presents some concepts of the present disclosure in a general form as a prelude to the more detailed description provided below.

In one example, a semiconductor device is provided. The semiconductor device includes a substrate, a conductive pattern, a support structure, a first conductive layer, and a dielectric layer. The conductive pattern extends vertically from the substrate. The support structure extends from an outer sidewall of the conductive pattern. The first conductive layer covers the conductive pattern. The dielectric layer at least covers the first conductive layer and the support structure.

In another example, a method for fabricating a semiconductor device is provided. The method includes actions of: providing a substrate having an etch stop layer formed thereon; forming a preliminary stacked structure on the etch stop layer, the preliminary stacked structure including a lower sacrifice layer contacting the etch stop layer, a support layer, and an upper sacrifice layer; forming a hole penetrating the preliminary stacked structure and the etch stop layer; forming a conductive pattern in the hole; removing the upper sacrifice layer and a portion of the support layer; removing the lower sacrifice layer; forming a first conductive layer covering the conductive pattern; and forming a dielectric layer covering the first conductive layer, a remaining portion of the support layer, and the etch stop layer.

The details of one or more examples are set forth in the accompanying drawings and description below.

DETAILED DESCRIPTION

To facilitate an understanding of the principles and features of the various implementations of the present disclosure, various illustrative implementations are explained below. Although example implementations of the present disclosure are explained in detail, it is to be understood that other implementations are contemplated. Accordingly, it is not intended that the present disclosure is limited in its scope to the details of construction and arrangement of components set forth in the following description or illustrated in the drawings. The present disclosure is capable of other implementations and of being practiced or carried out in various ways.

FIGS. 1 to 5are cross-sectional views illustrating a method for fabricating a conductive pattern having a supporter in a semiconductor device100in accordance with various implementations of the present disclosure. As shown inFIG. 1, the semiconductor device100includes a substrate110, an etch stop layer120formed on the substrate110and a preliminary stacked pattern130formed on the etch stop layer120. The semiconductor device100may be a dynamic random access memory (DRAM) device. The substrate110includes a dielectric region111and a contact region112. The dielectric region111may be formed of a dielectric material, such as silicon nitride (SiN). The contact region112may be formed of a metal material, such as tungsten, titanium, or tantalum. In some implementations, the substrate110may be a silicon wafer.

The preliminary stacked pattern130includes a first sacrificial layer131, a support layer150formed on the first sacrificial layer131, a second sacrificial layer131formed on the support layer150, and mask patterns (not shown) formed over the second sacrificial layer131. For example, the preliminary stacked pattern130may be formed by sequentially stacking layers using a deposition technique, such as ALD process, a plasma assisted atomic layer deposition (PAALD), a CVD process, a plasma enhanced chemical vapor deposition (PECVD) process, a low pressure chemical vapor deposition (LPCVD) process, a high density plasma chemical vapor deposition (HDP-CVD) process, a spin coating process, a sputtering process, or the like.

In some implementations, the etch stop layer120may include a material selected from SiN, silicon boron nitride (SiBN), silicon carbon nitride (SiCN), silicon carbide (SiC), silicon oxynitride (SiON), silicon oxycarbide (SiOC), or the like. The first and second sacrificial layers131,132may be formed of a silicon oxide-based material, such as silicon oxide (SiOx), plasma enhanced oxide (PEOX), borosilicate glass (BSG), phosphosilicate glass (PSG), boro phospho silicate glass (BPSG), tetraethyl orthosilicate (TEOS), boro tetraethyl orthosilicate (BTEOS), phosphorous tetraethyl orthosilicate (PTEOS), or boro phospho tetraethyl orthosilicate (BPTEOS). The mask patterns may be made of a combination of SiN and polysilicon. Alternatively, the mask patterns may be made of a metal material.

As shown inFIG. 2, an etching process is performed to form a hole140penetrating the preliminary stacked pattern130and the etch stop layer120so that the substrate110is exposed. For example, a dry etching process such as a plasma etching process, an inductively coupled plasma (ICP) process, a transformer coupled plasma (TCP) process or a reactive ion etching (RIE) process may be used. Subsequently, a conductive pattern160is formed on the preliminary stacked pattern130by a deposition process such as a CVD process or ALD process. The conductive pattern160covers the surface of the hole140and the top of the preliminary stacked pattern130. The conductive pattern160may be formed of a metal including a material such as titanium nitride (TiN), titanium silicide nitride (TiSiN), tungsten nitride (WN), or a compound including a material selected from the group consisting essentially of titanium (Ti), tungsten (W), oxygen (O), nitrogen (N), and silicon (Si). Preferably, the conductive pattern160is electrically connected to the contact region112.

Referring toFIGS. 3 to 5, semiconductor fabricating processes are used to remove the first sacrificial layer131and the second sacrificial layer132. As shown inFIG. 3, a portion of the conductive pattern160is removed by a planarization process such as a etch-back process or a chemical mechanical polishing (CMP) process. Subsequent to the removal, a top surface of the second sacrificial layer132is exposed. As shown inFIG. 4, a first wet etch process is used to remove the second sacrificial layer132. Subsequently, a dry etch process is used to remove a portion of the support layer150so as to form a recess210to expose the first sacrificial layer131. As shown inFIG. 5, a second wet etch process is used to remove the first sacrificial layer131.

FIG. 6is a top view of the semiconductor device100with reference toFIG. 5in accordance with some implementations of the present disclosure. A predetermined area of the support layer150is chosen to form the recess210. The shape of the predetermined area may be a rectangle, a circle, or a triangle.FIG. 5is a cross-sectional view along the dash line A-A′.

FIGS. 7 to 8are cross-sectional views illustrating a method for fabricating a capacitor having a supporter in the semiconductor device100in accordance with some implementations of the present disclosure. As shown inFIG. 7, a first conductive layer161is formed to cover the conductive pattern160by a deposition process such as atomic layer deposition (ALD), chemical vapor deposition (CVD), or a sequential flow deposition (SFD). For example, the first conductive layer161is selectively deposited on an exposed surface of the conductive pattern160. In some implementations, the conductive pattern160has a hollow cylindrical structure extending vertically from the substrate110. The support layer150is formed on a predefined area of an outer sidewall of the hollow cylindrical structure, i.e. the support layer150extends horizontally from the outer sidewall. The first conductive layer161covers surfaces of the hollow cylindrical structure including the bottom area, the inner sidewall, the top area, and the exposed area of the outer sidewall. In some examples, the first conductive layer161may contact with the etch stop layer120. Preferably, the first conductive layer161includes W, WN, tungsten-containing material, or nitrogen-containing material.

As shown inFIG. 8, a dielectric layer162is formed to cover the first conductive layer161, the etch stop layer120, and the support layer150. Subsequently, a second conductive layer163is formed to cover the dielectric layer162. Preferably, the dielectric layer162includes ZrxOy, HfxOy, TaxOy, ZrHfSiOxTixOy, LaxOy, AlxOy, HfxSiyOz, or ZrxSiyOz. The second conductive layer163may be formed of a metal including a material such as TiN, TiSiN, WN, or a compound including a material selected from the group consisting essentially of Ti, W, O, N, and Si.

In some implementations, a thickness of the conductive pattern160is 150 angstrom (A) or less, and a thickness of the first conductive layer161is 50 A or less. A combination of the conductive pattern160and the first conductive layer161serves as a lower electrode for a capacitor in DRAM. A root mean square (RMS) of the lower electrode is up to 20 nanometer (nm). A resistivity of the lower electrode is up to 150 microohm centimeter (μΩ·cm).

Although specific implementations have been illustrated and described herein, those of ordinary skill in the art appreciate that any arrangement which is calculated to achieve the same purpose may be substituted for the specific implementations shown and that implementations of the present disclosure have other applications in other environments. This present disclosure is intended to cover any adaptations or variations of the present disclosure. The following claims are in no way intended to limit the scope of implementations of the present disclosure to the specific implementations described herein.