TRANSFER METHOD AND TRANSFER APPARATUS FOR SUBSTRATE PROCESSING SYSTEM

A semiconductor substrate is transferred accurately with respect to an edge ring. A transfer apparatus uses a transfer method for a substrate processing system, where the method includes tray loading, measuring, positioning, substrate placement, and tray removing. The tray loading includes loading a tray on which a semiconductor substrate and an edge ring are placeable into a mounting chamber including a support. The measurement includes measuring a position of the edge ring placed on the tray and obtaining position information about the edge ring. The positioning includes positioning the semiconductor substrate based on the position information. The substrate placement includes placing the positioned semiconductor substrate onto the tray. The tray removing includes removing the tray on which the semiconductor substrate and the edge ring are placed from the mounting chamber.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Japanese Patent Application No. 2019-148490 filed on Aug. 13, 2019, the entire disclosure of which is incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to a transfer method and transfer apparatus for a substrate processing system.

BACKGROUND

In plasma processing for semiconductor substrates, an edge ring (also called a focus ring) may be used along the periphery of a semiconductor substrate placed inside a process chamber (process module) having a predetermined degree of vacuum. With the edge ring controlling plasma around the substrate periphery, the semiconductor substrate can be processed uniformly across its peripheral and central portions. For this process, the semiconductor substrate and the edge ring are to be aligned properly with each other. The semiconductor substrate is thus to be transferred accurately with respect to the edge ring.

The edge ring can become worn through plasma processing and thus should be replaced regularly. In one approach to replacing the edge ring, the process chamber accommodating the edge ring is vented to the atmosphere. In another approach that does not require venting, an edge-ring storage space that is connected to a vacuum transfer chamber may be used for transferring the edge ring into the process chamber using a transfer mechanism included in the vacuum transfer chamber.

Yet, another method is to place a semiconductor substrate onto a tray and transfer the tray with the semiconductor substrate into the process chamber.

BRIEF SUMMARY

A semiconductor substrate typically passes through an atmospheric transfer chamber, a loadlock chamber, and a vacuum transfer chamber before being transferred into a process chamber. Although the transfer mechanism is controlled to transfer the semiconductor substrate accurately with respect to an edge ring placed inside the process chamber, the present inventors recognized a possible problem of the semiconductor substrate being initially improperly placed with respect to the transfer mechanism before being transferred into the process chamber, and so the semiconductor substrate may not to be transferred accurately. Further, the present inventors recognized that when the transfer mechanism in the vacuum transfer chamber is used to transfer an edge ring into the process chamber, the edge ring is also to be transferred and placed accurately onto a support for the edge ring.

The present disclosure is directed to a technique for placing a semiconductor substrate accurately with respect to an edge ring.

A transfer method for a substrate processing system according to one aspect of the present disclosure includes tray loading, measurement, positioning, substrate placement, and tray removing. The tray loading includes loading a tray on which a semiconductor substrate and an edge ring are placeable into a mounting chamber that includes a support. The measurement includes measuring a position of the edge ring placed on the tray and obtaining position information about the edge ring. The positioning includes positioning the semiconductor substrate based on the position information. The substrate placement includes placing the semiconductor substrate onto the tray, after the semiconductor substrate was positioned based on the position information. The tray removing includes removing the tray on which the semiconductor substrate and the edge ring are placed from the mounting chamber.

This exemplary technique according to the present disclosure allows accurate placement of a semiconductor substrate with respect to an edge ring.

DETAILED DESCRIPTION OF THE DRAWINGS

The description set forth below in connection with the appended drawings is intended as a description of various embodiments of the disclosed subject matter and is not necessarily intended to represent the only embodiment(s). In certain instances, the description includes specific details for the purpose of providing an understanding of the disclosed subject matter. However, it will be apparent to those skilled in the art that embodiments may be practiced without these specific details. In some instances, well-known structures and components may be shown in block diagram form in order to avoid obscuring the concepts of the disclosed subject matter.

Reference throughout the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, characteristic, operation, or function described in connection with an embodiment is included in at least one embodiment of the disclosed subject matter. Thus, any appearance of the phrases “in one embodiment” or “in an embodiment” in the specification is not necessarily referring to the same embodiment. Further, the particular features, structures, characteristics, operations, or functions may be combined in any suitable manner in one or more embodiments. Further, it is intended that embodiments of the disclosed subject matter can and do cover modifications and variations of the described embodiments.

It must be noted that, as used in the specification and the appended claims, the singular forms “a,” “an,” and “the” include plural referents unless the context clearly dictates otherwise. That is, unless clearly specified otherwise, as used herein the words “a” and “an” and the like carry the meaning of “one or more.” Additionally, it is to be understood that terms such as “left,” “right,” “top,” “bottom,” “front,” “rear,” “side,” “height,” “length,” “width,” “upper,” “lower,” “interior,” “exterior,” “inner,” “outer,” and the like that may be used herein, merely describe points of reference and do not necessarily limit embodiments of the disclosed subject matter to any particular orientation or configuration. Furthermore, terms such as “first,” “second,” “third,” etc., merely identify one of a number of portions, components, points of reference, operations and/or functions as described herein, and likewise do not necessarily limit embodiments of the disclosed subject matter to any particular configuration or orientation.

Embodiments of the present disclosure will now be described with reference to the drawings. In the embodiments described below, similar components are indicated by like reference numerals and will not be described repeatedly. The embodiments are illustrated by way of example and not by way of limitation in the accompanying drawings that are not to scale unless otherwise indicated.

Structure of Substrate Processing System

FIG. 1is a diagram of a substrate processing system showing its example structure. InFIG. 1, a substrate processing system100includes front-opening unified pods (FOUPs)14, an atmospheric transfer chamber11, an edge-ring storage facility2, a tray storage facility5, an aligner3, a loadlock chamber12, a vacuum transfer chamber13, process modules4, a first transfer mechanism15, and a second transfer mechanism16. While the term “mechanism” is used for convenience as a label, the transfer mechanisms are circuitry controlled assemblies that have controllable, movable arms, which are controlled to move items from one space to another. Thus, the transfer mechanism may also be referred to as transfer assembly/assemblies.

Each FOUP14is an enclosure for storing semiconductor substrates (hereinafter also referred to as wafers) and has a lid to open and close the enclosure. When a FOUP14that is storing wafers is attached to the atmospheric transfer chamber11, the lid of the FOUP14is engaged with a gate door GT of the atmospheric transfer chamber11and is unlatched. The lid of the FOUP14can be open in this state. When the gate door GT is open in this state, the lid of the FOUP14moves together with the gate door GT and is open, thus connecting the inside of the FOUP14with the inside of the atmospheric transfer chamber11.

The atmospheric transfer chamber11maintains an ambient atmosphere inside. The edge-ring storage facility2and the tray storage facility5are connected to the atmospheric transfer chamber11via shutters23, which can be open and closed. The edge-ring storage facility2stores multiple edge rings. The tray storage facility5stores multiple trays. The aligner3is also connected to the atmospheric transfer chamber11through an opening22. The atmospheric transfer chamber11accommodates the first transfer mechanism15, which transfers and receives wafers, edge rings, and trays to and from the FOUPs14, the edge-ring storage facility2, the tray storage facility5, the aligner3, and the loadlock chamber12. The first transfer mechanism15includes a base15a, an articulated arm15b, and a pick15c. The arm15bhas a basal end connected to the base15aand a distal end connected to the pick15c. The base15ais movable in directions indicated by the arrows (along the length of the atmospheric transfer chamber11) in the atmospheric transfer chamber11. The pick15cis U-shaped to support a wafer, an edge ring, and a tray. When the pick15cretrieves an edge ring from the edge-ring storage facility2, the shutter23between the edge-ring storage facility2and the atmospheric transfer chamber11is open. When the pick15cretrieves a tray from the tray storage facility5, the shutter23between the tray storage facility5and the atmospheric transfer chamber11is open.

The atmospheric transfer chamber11and the vacuum transfer chamber13are connected via the loadlock chamber12. The vacuum transfer chamber13maintains a vacuum atmosphere inside. The loadlock chamber12is separated from the atmospheric transfer chamber11and from the vacuum transfer chamber13by gate valves G. The gate valves G are normally closed. When the first transfer mechanism15transfers a wafer, an edge ring, or a tray from the atmospheric transfer chamber11into the loadlock chamber12, the gate valve G between the atmospheric transfer chamber11and the loadlock chamber12is open. When the second transfer mechanism16unloads a tray supporting an edge ring and a wafer from the loadlock chamber12and loads the tray into the vacuum transfer chamber13, the gate valve G between the loadlock chamber12and the vacuum transfer chamber13is open. The first transfer mechanism15is controlled with circuit logic which may be hardwired (e.g., application specific integrated circuit, ASIC) and/or a computer processor that is software programmable. The circuit logic controls the actuation of motors that control the movement of the transfer mechanism according to software routines that are either autonomous (e.g., recipe) and/or responsive to external input such as by an operator who inputs commands via a user interface to the transfer mechanism15. The circuit logic may use a computer, and/or microprocessor(s) as will be discussed later.

The loadlock chamber12is connected to a vacuum pump (not shown) serving as an exhaust mechanism and a leak valve (not shown) for restoring the atmospheric pressure in the chamber. The inside of the loadlock chamber12is thus switchable between the ambient atmosphere and the vacuum atmosphere. When the first transfer mechanism15transfers a wafer, an edge ring, or a tray from the atmospheric transfer chamber11into the loadlock chamber12, the inside of the loadlock chamber12is switched to the ambient atmosphere. When the second transfer mechanism16unloads a tray supporting a wafer and an edge ring from the loadlock chamber12and loads the tray into the vacuum transfer chamber13, the inside of the loadlock chamber12is switched to the vacuum atmosphere.

The second transfer mechanism16in the vacuum transfer chamber13transfers and receives a tray supporting a wafer and an edge ring between the loadlock chamber12and one of the process modules4. The second transfer mechanism16includes a base16a, an articulated arm16b, and a pick16c. The arm16bhas a basal end connected to the base16aand a distal end connected to the pick16c. The base16ais movable in directions indicated by the arrows (along the length of the vacuum transfer chamber13) in the vacuum transfer chamber13. The pick16cis U-shaped to support a tray supporting a wafer and an edge ring. The second transfer mechanism16has a similar circuit-based controller as discussed with respect to the first transfer mechanism15.

The vacuum transfer chamber13is separated from the process modules4with the gate valves G. The gate valves G are normally closed. When the second transfer mechanism16transfers a tray supporting a wafer and an edge ring from the vacuum transfer chamber13into one of the process modules4, the gate valve G between the vacuum transfer chamber13and the process module4is open.

The process modules4each process a wafer as a workpiece in the vacuum atmosphere. The process modules4perform processing such as etching or film deposition on a wafer placed on a tray.

Structure of Process Module

FIG. 2is a diagram of an exemplary process module4, which in this example is a capacitively coupled plasma apparatus. The process module4includes a process chamber10formed from a metal such as aluminum or stainless steel. The process chamber10is electrically grounded for protection.

The process chamber10accommodates a disk-shaped susceptor12that is generally horizontally oriented, such that a top surface is horizontal in the process chamber10. A tray TR1supporting a wafer W and an edge ring ER is placed onto the susceptor12. The susceptor12also serves as a lower electrode. The process chamber10has the gate valve G on the side wall for opening and closing the port to load and unload the tray TR1. The susceptor12is formed from, for example, a metal such as aluminum and is supported on an insulating cylindrical support14that extends vertically upward from the bottom of the process chamber10.

A conductive cylindrical support (inner wall)16, which surrounds the outer periphery of the cylindrical support14, extends vertically upward from the bottom of the process chamber10. The cylindrical support16and the side wall of the process chamber10together define an annular exhaust path18. The exhaust path18has an outlet22on its bottom.

The outlet22is connected to an exhaust device26through an exhaust pipe24. The exhaust device26includes a vacuum pump, such as a turbomolecular pump, to reduce the pressure in a process space PS in the process chamber10to an intended degree of vacuum. The process chamber10may maintain a pressure of, for example, 10 to 3,500 mTorr inside.

The wafer W as a processing target substrate is placed onto the tray TR1on the susceptor12, with the edge ring ER placed along the periphery of the wafer W. The edge ring ER is formed from either a conductive material such as Si or SiC or an insulating material such as SiO2. The edge ring ER is placed on the upper surface of the tray TR1.

An electrostatic chuck (ESC)40for attracting a wafer is located on the upper surface of the susceptor12. The ESC40includes a sheet or mesh conductor between dielectric films or plates. The conductor in the ESC40is coupled to a direct-current (DC) power supply42located outside the process chamber10via a switch44and a power supply line46. With the switch44turned on, the DC power supply42applies a DC voltage to the ESC40to generate a Coulomb force in the ESC40, causing the ESC40to electrostatically attract the wafer W through the tray TR1.

The susceptor12has an annular refrigerant compartment48extending circumferentially inside. The refrigerant compartment48contains a refrigerant (e.g., cooling water) with a predetermined temperature that is circulated from a chiller unit (not shown) through pipes50and52. The temperature of the refrigerant is controlled to control the temperature of the wafer W. To more precisely control the temperature of the wafer W, a heat-transfer gas supply unit (not shown) supplies a heat-transfer gas (e.g., He gas) between the tray TR1and the wafer W through a gas supply line51and a gas flow channel56in the susceptor12.

A disk-shaped upper electrode60is located on the ceiling of the process chamber10parallel to and facing (or opposite to) the susceptor12. The upper electrode60is attached to the ceiling of the process chamber10with a ring-shaped insulator98formed from, for example, ceramics.

The upper electrode60includes an electrode plate64directly facing the susceptor12and an electrode support66supporting the electrode plate64from behind (or from above) in a detachable manner. The electrode plate64may be formed from a conductive material, such as Si or Al. The electrode support66is formed from, for example, anodized aluminum. Moreover, the Si may be doped to enhance its conductivity, or formed as doped polysilicon. As described above, the process module4includes the disk-shaped susceptor12(lower electrode) and the disk-shaped upper electrode60located parallel to and facing each other.

A gas supply unit76supplies a process gas to the process chamber10. The upper electrode60also serves as a shower head electrode for supplying the process gas into the process space PS defined between the upper electrode60and the susceptor12. In more detail, the electrode support66includes a gas diffusing compartment72connected to many gas outlets74extending toward the susceptor12through the electrode support66and the electrode plate64. A gas inlet72alocated in an upper portion of the gas diffusing compartment72is connected to a gas supply line78extending from the gas supply unit76.

The upper electrode60is coupled to a first radio frequency (RF) power supply150via a first impedance matching circuit, or “matcher”152. The first matcher152performs impedance matching between the first RF power supply150and a load (mainly the electrode, plasma, and the process chamber). The first RF power supply150can apply an RF voltage for generating plasma with a frequency of 30 to 150 MHz to the upper electrode60. Once the upper electrode60receives such a high RF voltage, it can generate well-dissociated and high-density plasma in the process space PS, thus enabling plasma processing under lower pressure conditions. The first RF power supply150may output a voltage with a frequency of 50 to 80 MHz, and be typically adjusted to output a voltage with 60 MHz or similar frequencies.

The susceptor12as the lower electrode is coupled to a second RF power supply160with a connection rod36via a second matcher162. The second impedance matching circuit, or “matcher”162performs impedance matching between the second RF power supply160and a load (mainly the electrode, plasm, and the process chamber). The second RF power supply160can apply an RF voltage for biasing with a frequency of several hundred kilohertz to about ten to twenty megahertz to the susceptor12. The second RF power supply160is typically adjusted to output a voltage with a frequency of, for example, 2 MHz or 13.56 MHz. Shapes of Tray, Edge Ring, and Wafer

FIG. 3is a diagram of a tray showing its example shape.FIG. 4is a diagram of an edge ring placed on the tray, showing its example shape.FIG. 5is a diagram of an edge ring and a wafer placed on the tray, showing their example shapes.

As shown in the plan view ofFIG. 3, the tray TR1is disk-shaped and includes a conductive tray body101, a dielectric film102coating the tray body101, a lift pin contact103, and through-holes104,105, and106. Through-holes104allow supply of a heat-transfer gas between the tray TR1and the wafer W through the gas flow channel56(FIG. 2) in the process module4. Through-holes105receive a lift pin for raising and lowering the wafer W. Through-holes106receive a lift pin for raising and lowering the edge ring ER. The lift pin contact103is a part of the back surface of the tray body101without the dielectric film102and can be in contact with the lift pin raising the tray TR1. The lift pin contact103may be recess-shaped to receive the lift pin. The tray TR1includes a substrate support108on its upper surface for supporting the wafer W and an edge-ring support107for supporting the edge ring ER. The edge-ring support107surrounds the substrate support108. More specifically, the substrate support108and the edge-ring support107are parts of the conductive tray body101and include the dielectric film102coating the tray body101. The edge-ring support107is located lower than the substrate support108. The dielectric film102may be located on at least the upper surface of the tray body101.

As shown in the plan view portion ofFIG. 4, the edge ring ER is annular and has a circular outer peripheral portion and a partially flat inner peripheral portion with a flat FL. The edge ring ER is placed onto the edge-ring support107that is on the upper surface of the tray TR1. The edge ring ER has the inner peripheral portion thinner than the outer peripheral portion. More specifically, the edge ring ER placed on the edge-ring support107has the inner peripheral portion with the upper surface substantially flush with or lower than the upper surface of the substrate support108. The edge ring ER also has the outer peripheral portion with the upper surface substantially flush with or higher than the upper surface of the wafer W placed on the substrate support108that is on the upper surface of the tray TR1.

As shown in the plan view portion ofFIG. 5, the wafer W is disk-shaped and has a V-shaped notch NT on its outer periphery. The wafer W is placed onto the substrate support108that is on the upper surface of the tray TR1. The wafer W is placed onto the substrate support108to have the notch NT at the flat FL on the edge ring ER. As described above, the substrate support108has a support surface supporting the back surface of the wafer W and the through-holes104and105extending through the tray body101and the dielectric film102. The substrate support108has a smaller surface area than the wafer W. More specifically, the wafer W is placed onto the substrate support108to have the outer peripheral portion with the notch NT located outside the outer periphery of the substrate support108and on the inner peripheral portion of the edge ring ER.

As described above, the wafer W and the edge ring ER can be placed onto the tray TR1.

Structure of Mounting Apparatus

FIG. 6is a diagram of a structure of an exemplary mounting apparatus12A. In the present embodiment, the mounting apparatus12A shown inFIG. 6serves as the loadlock chamber12(seeFIG. 1). InFIG. 6, the mounting apparatus12A includes a chamber201, a rotation angle sensor202(e.g., an optical sensor), horizontal position sensors203(e.g., also an optical sensor), a support204, a first lift pin205, a second lift pin206, a third lift pin207, a DC power supply208, and a switch209. The rotation angle sensor202is located on (or through) the upper wall of the chamber201, and the horizontal position sensors203are located on (or through) the side walls of the chamber201. The conductive chamber201accommodates the support204. The mounting apparatus12A includes a first lift mechanism (not shown, but one example is computer controller servo motor(s)) for raising and lowering the first lift pin205, a second lift mechanism (not shown, but also one or more servo motors in this embodiment) for raising and lowering the second lift pin206independently of the first lift pin205, and a third lift mechanism (not shown, but also one or more servo motors in this embodiment) for raising and lowering the third lift pin207independently of the first lift pin205and the second lift pin206. Each lift mechanism may include an actuator, a motor, and/or another device that controllably urges the lift pin upward and downward. The first lift pin205, the second lift pin206, and the third lift pin207are formed from a conductive material (e.g., Ni or Al). The first lift pin205is coupled to the DC power supply208via the switch209. The second lift pin206and the third lift pin207are grounded. The mounting apparatus12A further includes a vacuum pump (not shown) serving as an exhaust mechanism that can reduce the pressure in the chamber201to a pressure lower than the atmospheric pressure, and a leak valve (not shown) for restoring the atmospheric pressure in the chamber201.

Transfer Method for Substrate Processing System

FIG. 7is a flowchart showing an example procedure of a transfer method according to an embodiment.FIGS. 8 to 11are diagrams of the mounting apparatus at various stages in the example transfer method.

In step S1, inFIG. 7, a tray TR1is loaded into the loadlock chamber12using the first transfer mechanism15. The tray TR1is stored in the tray storage facility5connected to the atmospheric transfer chamber11. The first transfer mechanism15unloads the tray TR1from the tray storage facility5and loads the tray TR1supported on the pick15cinto the loadlock chamber12(mounting apparatus12A, as shown inFIG. 6for example). The loadlock chamber12has an atmospheric pressure inside.

In step S2, the tray TR1is then placed onto the support204in the loadlock chamber12. As shown inFIG. 8, the first lift pin205is raised (in other words, the tray TR1is lifted up) to separate the tray TR1from the pick15c, while coming in contact with the lift pin contact103on the back surface of the tray body101.

With the first lift pin205held at the position shown inFIG. 8, the pick15cis retracted from the loadlock chamber12.

The first lift pin205is then lowered (in other words, the tray TR1is moved down) to place the tray TR1onto the support204.

In step S3, an edge ring ER is loaded into the loadlock chamber12using the first transfer mechanism15. The edge ring ER is stored in the edge-ring storage facility2connected to the atmospheric transfer chamber11. The first transfer mechanism15unloads the edge ring ER from the edge-ring storage facility2and loads the edge ring ER supported on the pick15cinto the loadlock chamber12.

In step S4, the edge ring ER is placed onto the tray TR1, which itself is placed on the support204in the loadlock chamber12. As shown inFIG. 9, the third lift pin207is raised (in other words, the edge ring ER is lifted up) to separate the edge ring ER from the pick15c, while coming in contact with the back surface (underneath) of the edge ring ER through the through-holes106in the tray TR1. The third lift pin207is grounded and thus eliminates static electricity from the edge ring ER when its distal ends come in contact with the back surface of the edge ring ER.

With the third lift pin207held at the position shown inFIG. 9, the pick15cis retracted from the loadlock chamber12.

The third lift pin207is then lowered (in other words, the edge ring ER is moved down) to place the edge ring ER onto the tray TR1.

In step S5, the position of the edge ring ER placed on the tray TR1is measured. As shown inFIG. 10, the position of the edge ring ER placed on the tray TR1is measured using the rotation angle sensor202and the horizontal position sensors203to obtain position information about the edge ring ER. A signal representing the obtained position information is then transmitted to the aligner3. The rotation angle sensor202includes, for example, a charge-coupled device (CCD) that optically detects the position of the ER. A rotation angle RA of the edge ring ER with respect to a predetermined reference position RP is measured using an image of the flat FL captured from above the edge ring ER. Rotation angle information RAI indicating the rotation angle RA is thus obtained as first position information about the edge ring ER. The horizontal position sensors203include, for example, lasers emitting light toward the edge ring ER from laterally outside the edge ring ER. A positional displacement HP of the edge ring ER in the horizontal direction with respect to the predetermined reference position RP is measured using a distance between each horizontal position sensor203and the outer periphery of the edge ring ER. Horizontal position information HPI indicating the positional displacement HP is thus obtained as second position information about the edge ring ER. The position information transmitted from the loadlock chamber12to the aligner3thus includes the rotation angle information RAI about the edge ring ER and the horizontal position information HPI about the edge ring ER.

In step S6, a wafer W is positioned using the aligner3. The wafer W is transferred from the FOUP14into the aligner3using the first transfer mechanism15. The aligner3positions the wafer W based on the position information transmitted from the loadlock chamber12. More specifically, the aligner3rotates the wafer W based on the rotation angle information RAI about the edge ring ER and horizontally positions the wafer W based on the horizontal position information HPI about the edge ring ER. Positioning the wafer W will be described in detail later.

In step S7, the wafer W is loaded into the loadlock chamber12using the first transfer mechanism15. The positioned wafer W is supported on the pick15cin the first transfer mechanism15, unloaded from the aligner3, and transferred to above the support204in the loadlock chamber12.

In step S8, the wafer W is then placed onto the tray TR1placed on the support204in the loadlock chamber12. As shown inFIG. 11, the second lift pin206is raised to separate the wafer W from the pick15c(in other words, the wafer W is lifted up), while coming in contact with the back surface of the wafer W through the through-holes105in the tray TR1. The second lift pin206is grounded and thus eliminates static electricity from the wafer W when its distal ends come in contact with the back surface of the wafer W.

With the second lift pin206held at the position shown inFIG. 11, the pick15cis retracted from the loadlock chamber12.

The second lift pin206is then lowered (in other words, the wafer W is moved down) to place the wafer W onto the tray TR1.

In step S9, a DC voltage is applied to the tray body101. The vacuum pump starts exhausting air from the chamber201to cause the first lift pin205to be in contact with the lift pin contact103. The switch209is turned on to couple the first lift pin205to the DC power supply208, allowing the DC power supply208to apply a positive DC voltage to the first lift pin205. The first lift pin205receives a positive DC voltage from the DC power supply208, which is then applied to the tray body101through the first lift pin205and the lift pin contact103. The DC voltage applied to the tray body101generates a Coulomb force in the tray TR1, which then electrostatically attracts the wafer W. The edge ring ER formed from, for example, a conductive material such as Si or SiC, is also electrostatically attracted to the tray TR1. Moreover, the Si or SiC may be doped to enhance its conductivity, or formed as doped polysilicon. As described above, the wafer W is electrostatically attracted to the tray TR1with the first lift pin205in contact with the back surface of the tray body101and with a DC voltage applied to the tray body101through the first lift pin205.

In step S10, the tray TR1supporting the edge ring ER and the wafer W is then loaded into the process module4. The switch209is turned off to stop the DC voltage applied to the tray body101, whereas the first lift pin205is raised with its distal ends remaining in contact with the back surface of the tray TR1. This allows the tray TR1to remain charged after the DC voltage applied to the tray body101is stopped, allowing the wafer W to remain attracted to the tray TR1.

The tray TR1is unloaded from the loadlock chamber12using the second transfer mechanism16in the vacuum transfer chamber13. The pick16cin the second transfer mechanism16is advanced into the loadlock chamber12and is located under the tray TR1, which is lifted by the first lift pin205.

The first lift pin205is then lowered to place the tray TR1onto the pick16c. After retracting the pick16cfrom the loadlock chamber12, the second transfer mechanism16transfers the tray TR1supporting the wafer W and the edge ring ER from the loadlock chamber12to the process module4.

While being transferred from the loadlock chamber12into the process module4, the tray TR1supporting the wafer W and the edge ring ER remains charged, allowing the positioned wafer W to remain attracted to the tray TR1. The positioned wafer W can avoid displacement while being transferred from the loadlock chamber12into the process module4.

The edge ring ER typically weighs more than the wafer W. The edge ring ER is thus less likely to be displaced than the wafer W when the tray TR1is transferred from the loadlock chamber12into the process module4. The edge ring ER is formed from an insulating material such as SiO2and is also effectively transferred using the tray TR1. The edge ring ER is formed from a conductive material such as Si or SiC and is attracted to the tray TR1together with the wafer W, and thus can be transferred more effectively.

The tray TR1transferred into the process module4is placed onto the susceptor12(ESC40) in the process module4. The susceptor12includes a lift pin (not shown). The tray TR1is placed onto the susceptor12(ESC40) in the same manner as in step S2. After the tray TR1is placed onto the ESC40, the switch44is turned on to cause the DC power supply42to apply a DC voltage to the ESC40. The wafer W is attracted to the ESC40through the tray TR1.

In step S11, plasma processing, such as etching, is performed.

When the plasma processing is complete, the tray TR1supporting the edge ring ER and the wafer W is unloaded from the process module4in step S12. The tray TR1unloaded from the process module4is placed onto the support204in the loadlock chamber12. After the atmospheric pressure in the loadlock chamber12is restored using the leak valve (not shown), the first transfer mechanism15unloads the wafer W from the loadlock chamber12. The unloaded wafer W is stored into the FOUP14.

The edge ring ER and the tray TR1may or may not be stored separately in the edge-ring storage facility2and the tray storage facility5. A new wafer W may be loaded into the loadlock chamber12while the edge ring ER and the tray TR1remain on the support204in the loadlock chamber12. In this case, the subsequent processing may be started from step S5or step S6. To replace the edge ring ER that has worn, the edge ring ER may be stored into the edge-ring storage facility2and a new edge ring ER may be loaded into the loadlock chamber12. In this case, the subsequent processing may be started from step S3.

Attractive Force in ESC

In step S10, the tray TR1loaded into the process module4is placed onto the ESC40. The wafer W is placed onto the tray TR1, instead of being placed directly onto the ESC40.FIG. 12is a graph showing the relationship between a capacitance per unit area and an attractive force per unit area generated in the ESC in the process module. For example, when a dielectric layer above an electrode incorporated in the ESC has a thickness of 0.3 mm, the dielectric films102on the upper and lower surfaces of the tray body101each have a thickness of 0.1 mm, and the dielectric materials have a relative dielectric constant of 8.5, the tray TR1has a capacitance of 0.124 g/m2. When the DC power supply42applies a DC voltage of 5 kV to the ESC40, the ESC40generates a Coulomb force with an attractive force of about 170 Torr per unit area. The attractive force is large enough to attract the wafer W without being separated from the tray TR1placed on the ESC40under the pressure applied from a heat-transfer gas supplied between the tray TR1and the wafer W in the process module4.

Positioning Wafer

FIG. 13is a diagram showing the arrangement of the rotation angle sensor and the horizontal position sensors. As shown inFIG. 13, the edge ring ER is placed onto the tray TR1with the flat FL located under the rotation angle sensor202in the mounting apparatus12A. The horizontal position sensors203are at three positions surrounding the edge ring ER placed on the tray TR1in the mounting apparatus12A.

FIG. 14is a diagram of the edge ring and the wafer that are accurately aligned with each other. As shown inFIG. 14, when the edge ring ER and the wafer W are accurately aligned with each other, the edge ring ER is concentric with the wafer W, with the apex of the notch NT in the middle of the flat FL on the edge ring ER. To align the edge ring ER and the wafer W accurately with each other, a straight reference line L1and a straight reference line L2are preset. The reference position RP is defined by the reference line L1in the lateral direction and the reference line L2in the vertical direction. The reference lines L1and L2intersect perpendicularly with each other. When the edge ring ER and the wafer W are accurately aligned with each other, the centers of the edge ring ER and the wafer W align with the intersection between the reference lines L1and L2and the middle of the flat FL and the apex of the notch NT align with the reference line L1.

FIGS. 15 to 18are diagrams each describing an example of positioning of the wafer.FIGS. 15 and 17each show the position of the edge ring ER placed on the tray TR1, andFIGS. 16 and 18each show the position of the positioned wafer W.

As shown inFIG. 15, a positional displacement HP of the edge ring ER placed on the tray TR1in the horizontal direction with respect to the reference position RP, which is defined by the reference lines L1and L2, is measured using the horizontal position sensors203. To measure the positional displacement HP, a straight line LA in the lateral direction and a straight line LB in the vertical direction are defined for the edge ring ER placed on the tray TR1, as shown inFIG. 15. The straight line LA and the straight line LB intersect perpendicularly with each other. The center of the edge ring ER aligns with the intersection between the straight lines LA and LB, and the middle of the flat FL aligns with the straight line LA. The horizontal position sensors203measure, as a positional displacement HP, the direction and the degree of displacement of the intersection between the straight lines LA and LB from the intersection between the reference lines L1and L2. To position the wafer W horizontally with the aligner3, the center position of the wafer W is moved from the intersection between the reference lines L1and L2by the positional displacement HP as shown inFIG. 16. The wafer W is concentric with the edge ring ER, which is placed on the tray TR1with the positional displacement HP. This provides a constant clearance between the inner periphery of the edge ring ER and the outer periphery of the wafer W inside the edge ring ER across the entire peripheries.

As shown inFIG. 17, a rotation angle RA of the edge ring ER placed on the tray TR1with respect to the reference position RP, which is defined by the reference lines L1and L2, is measured using the rotation angle sensor202. To measure the rotation angle RA, a straight line LC in the lateral direction and a straight line LD in the vertical direction are defined for the edge ring ER placed on the tray TR1, as shown inFIG. 17. The straight line LC and the straight line LD intersect perpendicularly with each other. The center of the edge ring ER and the intersection between the reference lines L1and L2align with the intersection between the straight lines LC and LD, and the middle of the flat FL aligns with the straight line LC. The rotation angle sensor202measures the rotation angle RA of the straight line LC with respect to the reference line L1. To rotate the wafer W with the aligner3, the wafer W is rotated from the reference position RP by the rotation angle RA. This allows the wafer W to be placed with the apex of the notch NT aligning with the middle of the flat FL on the edge ring ER placed on the tray TR1with its flat FL displaced by the rotation angle RA, as shown inFIG. 18.

In the present embodiment, the edge ring ER and the wafer W are placed onto the tray TR1in the loadlock chamber12, and the tray TR1is transferred into the process module4. The position of the edge ring ER is then measured in the loadlock chamber12, and the wafer W is positioned based on the measurement result and then is placed onto the tray TR1. The wafer W is thus transferred to the accurate position relative to the edge ring ER, although the edge ring ER is displaced. The tray TR1can electrostatically attract the wafer W and the edge ring ER. The edge ring ER and the wafer W placed on the tray TR1in the loadlock chamber12are thus transferred into the process module4without any displacement from each other. When a wafer W is transferred with respect to an edge ring ER located in the process module4, the wafer W may be displaced relative to the edge ring ER due to an error in transferring the wafer W from the loadlock chamber12into the process module4. However, in the present embodiment, the wafer W is transferred with respect to the edge ring ER located in the loadlock chamber12, eliminating such displacement of the wafer W relative to the edge ring ER due to an error in transferring the wafer W from the loadlock chamber12into the process module4. More specifically, in the present embodiment, the wafer W is transferred to the accurate position relative to the edge ring ER in the loadlock chamber12, and the wafer W and the edge ring ER are transferred from the loadlock chamber12into the process module4while being maintained at their relative positions. This enables uniform plasma processing of the wafer W in the process module4.

The embodiments disclosed herein are illustrative in all aspects and should not be construed to be restrictive. The above embodiments may be implemented in various forms. The components in the above embodiments may be eliminated, substituted, or modified in various forms without departing from the spirit and scope of the claims.

For example, the tray storage facility5is connected to the atmospheric transfer chamber11in the above embodiment. In some embodiments, the tray storage facility5may be connected to the vacuum transfer chamber13as shown inFIG. 19.FIG. 19is a diagram of a substrate processing system with the tray storage facility5connected to a vacuum transfer chamber, showing its example structure. The edge-ring storage facility2may also be connected to the vacuum transfer chamber13. In such cases, the second transfer mechanism16loads the edge ring and/or the tray into the loadlock chamber12.

In the above embodiment, the edge ring and the wafer are placed onto the tray in the loadlock chamber12. In some embodiments, the edge ring and the wafer may be placed onto the tray outside the loadlock chamber12. For example, a mounting apparatus12A separate from the loadlock chamber12may be connected to the atmospheric transfer chamber11. The edge ring and the wafer may be placed onto the tray in the mounting apparatus12A, and then the tray may be loaded into the loadlock chamber12.

In the above embodiment, the tray TR1is placed onto the support204in step S2. In some embodiments, the tray TR1may not be placed in this step. In step S3, the first lift pin205may be lowered to receive the edge ring ER, and the processing in step S3and subsequent steps may be performed with the tray TR1supported by the first lift pin205.

In the above embodiment, the tray is stored in the tray storage facility5and the edge ring is stored in the edge-ring storage facility2, and the tray and the edge ring are separately loaded into the loadlock chamber12. In some embodiments, a tray on which an edge ring is placed may be stored in the tray storage facility5. In this case, the processing in steps S3and S4may be eliminated. The edge-ring storage facility2, the third lift pin207for raising and lowering the edge ring in the mounting apparatus12A, and the through-holes106for receiving the third lift pin207in the tray TR1may also be eliminated.

In the above embodiment, the edge ring has its inner peripheral portion located lower than the outer peripheral portion of the wafer W. In some embodiments, the edge ring may have its inner peripheral portion not located lower than the outer peripheral portion of the wafer W. More specifically, the tray TR1has the edge-ring support107lower than the substrate support108. In some embodiments, the edge-ring support may be either higher than or flush with the substrate support.

FIG. 20is a diagram of an example tray having the edge-ring support flush with the substrate support. InFIG. 20, a tray TR2is disk-shaped and includes a conductive tray body251, a dielectric film252coating the tray body251, an annular groove253, a protective member254received in the groove253, a lift pin contact255, and through-holes256and257. The dielectric film252may be located on at least the upper surface of the tray body251. The through-holes256are used to supply a heat-transfer gas between the tray TR2and the wafer W through the gas flow channel56(FIG. 2) in the process module4. The through-holes257receive a lift pin for raising and lowering the wafer W. The tray TR2has no through-hole for receiving a lift pin for raising and lowering the edge ring ER. In some embodiments, the tray TR2may have such through-holes. The tray TR2includes, on its upper surface, a substrate support259on which the wafer W is to be placed and an edge-ring support258on which the edge ring ER is to be placed. The edge-ring support258surrounds the substrate support259. The substrate support259and the edge-ring support258are flush with each other.

On the tray TR2, the outer peripheral portion of the wafer W does not overlap the inner peripheral portion of the edge ring ER. This causes the dielectric film located between the wafer W and the edge ring ER to be exposed to plasma during the plasma processing. The wafer W may be contaminated by the dielectric film or by the underlying material of the tray body exposed after the dielectric film wears. The tray TR2thus includes the protective member254between the substrate support259and the edge-ring support258. The protective member254is received in the groove253between the substrate support259and the edge-ring support258. The protective member254may be formed from the same material as the edge ring ER. In this case, the tray TR2and the edge ring ER may have simpler shapes.

In the above embodiment, a DC voltage is applied to the tray body101using the first lift pin205coupled to the DC power supply208. In some embodiments, a DC voltage may be applied to the tray body101without using a lift pin.

FIG. 21is a diagram describing an example of application of a DC voltage to the tray body without using a lift pin. A mounting apparatus12B shown inFIG. 21serves as the loadlock chamber12. The same components as in the mounting apparatus12A shown inFIG. 6are not shown or described. InFIG. 21, the mounting apparatus12B includes a conductive support352, an insulating support351, a DC power supply353, and a conductive lift pin501. The lift pin501is grounded. A tray TR3is placed onto the support352. The edge ring ER and the wafer W are placed onto the tray TR3. The wafer W is raised or lowered using the lift pin501and placed onto the tray TR3. When the wafer W is raised and lowered using the lift pin501, static electricity is eliminated from the wafer W.

The tray TR3includes a conductive tray body362and a dielectric film361stacked on the tray body362. Unlike the tray TR1shown inFIG. 3, the tray TR3includes the tray body362with the upper surface alone coated by the dielectric film361and without the lower surface coated by any dielectric film. More specifically, the conductive tray body362is exposed on the lower surface of the tray TR3. The DC power supply353applies a DC voltage to the support352with the tray TR3supporting the edge ring ER and the wafer W placed on the support352, allowing the DC voltage to be applied to the tray body362. The tray TR3generates a Coulomb force to electrostatically attract the wafer W to the tray TR3.

FIG. 22is a diagram describing another example of application of a DC voltage to the tray body without using a lift pin. A mounting apparatus12C shown inFIG. 22serves as the loadlock chamber12. The same components as in the mounting apparatus12B shown inFIG. 21are not shown and/or described. Unlike the mounting apparatus12B shown inFIG. 21, the mounting apparatus12C includes a conducting terminal361located on the upper surface of the conductive support352. The conducting terminal361may be a protruding part of the conductive support352or may be a member separate from the support352. For example, the conducting terminal361may be a spring.

A tray TR4is placed onto the support352. The tray TR4includes a conductive tray body451, a dielectric film452coating the tray body451, and a DC power supply connector453. The DC power supply connector453is a part of the back surface of the tray body451without the dielectric film452and to be in contact with the conducting terminal361. The DC power supply connector453may be a recess shaped to receive the conducting terminal361. Unlike the tray TR1shown inFIG. 3, the tray TR4includes the DC power supply connector453. When the tray TR4supporting the edge ring ER and the wafer W is placed onto the support352, the conducting terminal361on the support352is coupled to the tray body451through the DC power supply connector453. The DC power supply353applies a DC voltage to the support352with the tray TR4supporting the edge ring ER and the wafer W placed on the support352, allowing the DC voltage to be applied to the tray body451. The tray TR4thus generates a Coulomb force to electrostatically attract the wafer W to the tray TR4.

FIG. 23is a diagram describing still another example of application of a DC voltage to the tray body without using a lift pin. A mounting apparatus12D shown inFIG. 23serves as the loadlock chamber12. The same components as in the mounting apparatus12C shown inFIG. 22are not shown and/or described. Unlike the mounting apparatus12C shown inFIG. 22, the mounting apparatus12D includes a support371that is an insulating member and a DC power supply355that is not coupled to the support371. The support371includes, on its upper surface, the conducting terminal361that is conductive and is directly coupled to the DC power supply355. A tray TR5is placed onto the support371.

The tray TR5includes, similarly to the tray TR4, a conductive tray body471, a dielectric film472coating the tray body471, and a DC power supply connector473. When the tray TR5supporting the edge ring ER and the wafer W is placed onto the support371, the conducting terminal361on the support371comes in contact with the tray body471via the DC power supply connector473. The DC power supply355thus applies a DC voltage to the tray body471with the tray TR5supporting the edge ring ER and the wafer W placed on the support371. The DC voltage applied to the tray body471generates a Coulomb force in the tray TR5, causing the tray TR5to electrostatically attract the wafer W.

In the above embodiment, the grounded conductive lift pin eliminates static electricity from the wafer W. However, static electricity in the wafer W may be eliminated without using a lift pin.

FIG. 24is a diagram describing an example of static electricity elimination from the wafer W without using a lift pin. A mounting apparatus12E shown inFIG. 24serves as the loadlock chamber12. The same components as in the mounting apparatus12B shown inFIG. 21are not shown and/or described. InFIG. 24, the mounting apparatus12E includes a grounded member354. Unlike the mounting apparatus12B, the mounting apparatus12E eliminates static electricity from the wafer W using the grounded member354, instead of the grounded lift pin501. The grounded member354is electrically coupled to the grounded chamber201. The grounded member354can be in contact with the wafer W placed on the tray TR6. The grounded member354may also be in contact with the edge ring ER, in addition to the wafer W.

As shown inFIG. 24, the grounded member354is placed in contact with the wafer W to ground the wafer W and eliminate static electricity from the wafer W. The DC power supply353applies a DC voltage to the support352with the tray TR6supporting the edge ring ER and the wafer W placed on the support352. The DC voltage applied to the support352generates a Coulomb force in the tray TR6, causing the tray TR6to electrostatically attract the wafer W.

FIG. 25is a diagram describing another example of static electricity elimination from the wafer W without using a lift pin. A mounting apparatus12F as shown inFIG. 25serves as the loadlock chamber12. The same components as in the mounting apparatus12C shown inFIG. 22are not shown and/or described. InFIG. 25, the mounting apparatus12F includes an RF power supply392coupled to a conductive support382.

When a tray TR7supporting the edge ring ER and the wafer W is placed onto the support382, a DC power supply391is coupled to a tray body481via a DC power supply connector483. The DC power supply391coupled to the tray body481applies a DC voltage to the tray body481. The RF power supply392applies an RF voltage for generating plasma with a frequency of 30 to 150 MHz to the support382. Such a high RF voltage applied to the support382can generate plasma PLS in the chamber201. The edge ring ER and the wafer W are grounded through the plasma PLS generated in the chamber201. The DC voltage applied to the tray body481generates a Coulomb force in the tray TR7, causing the tray TR7to electrostatically attract the wafer W.

In the above embodiment, the tray serves as a monopolar ESC. In some embodiments, the tray may serve as a bipolar ESC.

FIG. 26is a diagram of an example tray serving as a bipolar ESC. InFIG. 26, a tray TR8is disk-shaped and includes a conductive first tray body302, a conductive second tray body301, a dielectric film303coating the first tray body302and the second tray body301, an insulating layer304, lift pin contacts305and306, and through-holes307and308. Unlike the tray TR1, the tray TR8includes two bodies, or the first tray body302and the second tray body301, divided by the insulating layer304and each including a lift pin contact. The insulating layer304electrically divides the first tray body302and the second tray body301in the horizontal direction. The through-holes307are used to supply a heat-transfer gas between the tray TR8and the wafer W through the gas flow channel56(FIG. 2) in the process module4. The through-holes308receive a lift pin.

FIG. 27is a diagram of an example mounting apparatus for mounting a tray TR9. A mounting apparatus12G shown inFIG. 27serves as the loadlock chamber12. Unlike the mounting apparatus12A shown inFIG. 6, the mounting apparatus12G shown inFIG. 27includes a first lift pin401, an insulating second lift pin409, a first DC power supply407, a second DC power supply405, and switches406and408. The first lift pin401includes a conductive first pin404, a conductive second pin403, and an insulating support402that connects the first pin404and the second pin403. The mounting apparatus12G further includes a first lift mechanism (not shown) for raising and lowering the first lift pin401and a second lift mechanism (not shown) for raising and lowering the second lift pin409independently of the first lift pin401. The first pin404is coupled to the first DC power supply407via the switch408, and the second pin403is coupled to the second DC power supply405via the switch406.

As shown inFIG. 27, a tray TR9supporting the wafer W and the edge ring ER is placed onto the support204. The first pin404and the second pin403are in contact with lift pin contacts305and306. The switch408is turned on to couple the first pin404to the first DC power supply407, allowing the first DC power supply407to apply a positive DC voltage to the first pin404. The first pin404receives a positive DC voltage from the first DC power supply407, which is then applied to the first tray body302through the first pin404and the lift pin contact306. The switch406is turned on to couple the second pin403to the second DC power supply405, allowing the second DC power supply405to apply a negative DC voltage to the second pin403. The second pin403receives a negative DC voltage from the second DC power supply405, which is then applied to the second tray body301through the second pin403and the lift pin contact305. The DC voltage applied to the first tray body302and the second tray body301generates a Coulomb force in the tray TR9, causing the tray TR9to electrostatically attract the wafer W. The edge ring ER formed from, for example, a conductive material such as Si or SiC is also electrostatically attracted to the tray TR9.

In the above embodiment, the aligner3rotates and horizontally positions the wafer W in step S6. However, the first transfer mechanism15may be controlled to horizontally position the wafer W based on the horizontal position information HPI about the edge ring ER. More specifically, to horizontally position the wafer W, the first transfer mechanism15may transfer the wafer W to above the support204to allow the wafer W to be concentric with the edge ring ER based on the horizontal position information HPI about the edge ring ER.

The operations of the individual components in the substrate processing system100or200and the entire operation (sequence) of the substrate processing system100or200are controlled by a controller. The controller may be a microcomputer, or processing circuitry like that shown inFIG. 28.FIG. 28is a block diagram of processing circuitry for performing computer-based operations described herein.FIG. 28illustrates processing circuitry400that may be used to control any computer-based and cloud-based control processes, descriptions or blocks in flowcharts can be understood as representing modules, segments or portions of code which include one or more executable instructions for implementing specific logical functions or steps in the process, and alternate implementations are included within the scope of the exemplary embodiments of the present advancements in which functions can be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending upon the functionality involved, as would be understood by those skilled in the art. The various elements, features, and processes described herein may be used independently of one another or may be combined in various ways. All possible combinations and sub-combinations are intended to fall within the scope of this disclosure.

InFIG. 28, the processing circuitry400includes a CPU401which performs one or more of the control processes described above/below. The process data and instructions may be stored in memory402. These processes and instructions may also be stored on a storage medium disk404such as a hard drive (HDD) or portable storage medium or may be stored remotely. Further, the claimed advancements are not limited by the form of the computer-readable media on which the instructions of the inventive process are stored. For example, the instructions may be stored on CDs, DVDs, in FLASH memory, RAM, ROM, PROM, EPROM, EEPROM, hard disk or any other information processing device with which the processing circuitry400communicates, such as a server or computer. The processes may also be stored in network based storage, cloud-based storage or other remote accessible storage and executable by processing circuitry400.

The hardware elements in order to achieve the processing circuitry400may be realized by various circuitry elements. Further, each of the functions of the above described embodiments may be implemented by circuitry, which includes one or more processing circuits. A processing circuit includes a particularly programmed processor, for example, processor (CPU)401, as shown inFIG. 28. A processing circuit also includes devices such as an application specific integrated circuit (ASIC) and conventional circuit components arranged to perform the recited functions.

InFIG. 28, the processing circuitry400includes a CPU401which performs the processes described above. The processing circuitry400may be a general-purpose computer or a particular, special-purpose machine. In one embodiment, the processing circuitry400becomes a particular, special-purpose machine when the processor401is programmed to perform edge-ring, tray, and wafer transfer and placement by controlling the transfer mechanism and sensors as discussed above. The processing circuitry400may be in or locally communicable to substrate processing apparatus200. In some embodiments, processing circuitry400may be remote from substrate processing apparatus200, providing processing instructions to substrate processing apparatus200via network428.

Alternatively, or additionally, the CPU401may be implemented on an FPGA, ASIC, PLD or using discrete logic circuits, as one of ordinary skill in the art would recognize. Further, CPU401may be implemented as multiple processors cooperatively working in parallel to perform the instructions of the inventive processes described above.

The processing circuitry400inFIG. 28also includes a network controller406, such as an Intel Ethernet PRO network interface card from Intel Corporation of America, for interfacing with network428. As can be appreciated, the network428can be a public network, such as the Internet, or a private network such as an LAN or WAN network, or any combination thereof and can also include PSTN or ISDN sub-networks. The network428can also be wired, such as an Ethernet network, or can be wireless such as a cellular network including EDGE, 3G and 4G wireless cellular systems. The wireless network can also be Wi-Fi, Bluetooth, or any other wireless form of communication that is known.

The processing circuitry400further includes a display controller408, such as a graphics card or graphics adaptor for interfacing with display410, such as a monitor. A general purpose I/O interface412interfaces with a keyboard and/or mouse414as well as a touch screen panel416on or separate from display410. General purpose I/O interface also connects to a variety of peripherals418including printers and scanners.

The general-purpose storage controller424connects the storage medium disk404with communication bus426, which may be an ISA, EISA, VESA, PCI, or similar, for interconnecting all of the components of the processing circuitry400. A description of the general features and functionality of the display410, keyboard and/or mouse414, as well as the display controller408, storage controller424, network controller406, and general purpose I/O interface412is omitted herein for brevity as these features are known.

The embodiments disclosed herein are illustrative in all aspects and should not be construed to be restrictive. The above embodiments may be implemented in various forms. The components in the above embodiments may be eliminated, substituted, or modified in various forms without departing from the spirit and scope of the claims. For example, although etching is described as an example of substrate processing in the above embodiments, the substrate processing performed with the technique according to the present disclosure is not limited to etching. For example, the technique according to the present disclosure is applicable to film deposition as one example of substrate processing by modifying the degree of vacuum in the process space PS and selecting a process gas suitable for film deposition.

REFERENCE SIGNS LIST