Sub 60nm etchless MRAM devices by ion beam etching fabricated T-shaped bottom electrode

A first conductive layer is patterned and trimmed to form a sub 30 nm conductive via on a first bottom electrode. The conductive via is encapsulated with a first dielectric layer and planarized to expose a top surface of the conductive via. A second conductive layer is deposited over the first dielectric layer and the conductive via. The second conductive layer is patterned to form a sub 60 nm second conductive layer wherein the conductive via and second conductive layer together form a T-shaped second bottom electrode. MTJ stacks are deposited on the T-shaped second bottom electrode and on the first bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and planarized to expose a top surface of the MTJ stack on the T-shaped second bottom electrode. A top electrode contacts the MTJ stack on the T-shaped second bottom electrode plug.

TECHNICAL FIELD

This application relates to the general field of magnetic tunneling junctions (MTJ) and, more particularly, to etchless methods for forming sub 60 nm MTJ structures.

BACKGROUND

Fabrication of magnetoresistive random-access memory (MRAM) devices normally involves a sequence of processing steps during which many layers of metals and dielectrics are deposited and then patterned to form a magnetoresistive stack as well as electrodes for electrical connections. To define those millions of MTJ cells in each MRAM device and make them non-interacting to each other, precise patterning steps including reactive ion etching (RIE) are usually involved. During RIE, high energy ions remove materials vertically in those areas not masked by photoresist, separating one MTJ cell from another. However, the high energy ions can also react with the non-removed materials, oxygen, moisture and other chemicals laterally, causing sidewall damage and lowering device performance. To solve this issue, pure physical etching techniques such as ion beam etching (IBE) have been applied to etch the MTJ stack to avoid the damaged MTJ sidewall. However, due to their non-volatile nature, IBE etched conductive materials in the MTJ and bottom electrode can be re-deposited into the tunnel barrier, resulting in shorted devices. A new device structure and associated process flow which can form MTJ patterns with desired sizes without plasma etch is desired.

Several patents teach methods of forming an MTJ without etching, including U.S. Pat. No. 9,029,170 (Li et al) and Patent CN107342331 (Wang et al), but these methods are different from the present disclosure.

SUMMARY

It is an object of the present disclosure to provide a method of forming MTJ structures without chemical damage or re-deposition of metal materials on the MTJ sidewalls.

Another object of the present disclosure is to provide a method of electrically isolatedly forming MTJ patterns on top of a T-shaped bottom electrode without using a plasma etch.

Another object of the present disclosure is to provide a T-shaped bottom electrode and electrically isolatedly forming MTJ patterns on top of the bottom electrode without etching.

In accordance with the objectives of the present disclosure, a method for fabricating a magnetic tunneling junction (MTJ) structure is achieved. A first conductive layer is deposited on a first bottom electrode. The first conductive layer is patterned and trimmed to form a sub 30 nm conductive via on the first bottom electrode. The conductive via is encapsulated with a first dielectric layer. The first dielectric layer is planarized to expose a top surface of the conductive via. A second conductive layer is deposited over the first dielectric layer and the conductive via. The second conductive layer is patterned to form a sub 60 nm second conductive layer wherein the conductive via and second conductive layer together form a T-shaped second bottom electrode. MTJ stacks are deposited on the T-shaped second bottom electrode and on the first bottom electrode wherein the MTJ stacks are discontinuous. A second dielectric layer is deposited over the MTJ stacks and planarized to expose a top surface of the MTJ stack on the T-shaped second bottom electrode. A top electrode layer is deposited on the second dielectric layer and contacting the top surface of the MTJ stack on the T-shaped second bottom electrode plug to complete the MTJ structure.

Also in accordance with the objects of the present disclosure, an improved magnetic tunneling junction (MTJ) is achieved. The MTJ structure comprises a sub-60 nm MTJ device on a T-shaped second bottom electrode, a first bottom electrode underlying the T-shaped second bottom electrode, and a top electrode overlying and contacting the MTJ device.

DETAILED DESCRIPTION

In the present disclosure, it is demonstrated that by using a high angle ion beam etching, we can create a T shaped bottom electrode. Since the bottom portion is only sub 30 nm, much smaller than the top portion of sub 60 nm, the later MTJ deposition cannot form a continuous film along the electrode, but forms separate patterns on top. Using this etchless process, any chemical damage and/or conductive metal re-deposition on the MTJ sidewall are avoided, improving the MRAM device performance.

In a typical MTJ process, the MTJ stack is deposited onto a uniformly sized bottom electrode. Plasma etch is used to transfer the photolithography created photoresist pattern into the MTJ stack. A physical etch such as pure Ar RIE or IBE can avoid chemical damage, but the metal re-deposition in this type of etch can cause electrically shorted devices. However, in the process of the present disclosure, the MTJ stack is deposited onto a T-shaped electrode, so that the patterns are formed without using plasma etch, avoiding these issues.

The preferred embodiment of the present disclosure will be described in more detail with reference toFIGS. 1-9.FIG. 1illustrates a first bottom electrode layer12formed on a semiconductor substrate, not shown. The first bottom electrode12is preferably Ta, TaN, Ti or TiN. On top of first bottom electrode or circuit12, a conductive layer14such as Ta, TaN, Ti, TiN W, Cu, Mg, Ru, Cr, Co, Fe, Ni or their alloys is deposited to a thickness h1of 10-100 nm, and preferably ≥50 nm. A dielectric layer16such as SiO2, SiN, SiON, SiC, or SiCN is deposited using chemical vapor deposition (CVD) or spin-coating to a thickness h2of ≥90 nm.

Next, a photoresist is spin-coated and patterned by photolithography, such as 248 nm photolithography, forming photoresist patterns18with size d1of approximately 70-80 nm and height h3of ≥200 nm.

Now, the dielectric layer16and conductive layer14are etched by a fluorine carbon based plasma such as CF4or CHF3alone, or mixed with Ar and N2. O2can be added to reduce the pillar size further. They can alternatively be patterned by a physical etch such as IBE. Metal layer14can also be patterned by a physical etch such as IBE or RIE using pure Ar plasma. Dependent on the thickness of the conductive layer14, the dielectric layer16can be partially consumed. The conductive layer's remaining thickness is still h1(≥50 nm) with pattern size d2of 15-70 nm, as shown inFIG. 2.

Next, a high angle IBE trimming20is applied to the conductive layer14. The high angle ranges from 70-90° with respect to the surface's normal line. After IBE trimming, as shown inFIG. 3, the conductive layer pattern size decreases to d3, which can range from 10-30 nm, dependent on the IBE trimming conditions such as RF power (500-1000 W) and time (100-500 sec). Due to the protection of the remaining dielectric layer16on top of the conductive layer14(FIG. 2), and the extremely low vertical etch rate (≤5 A/sec) of IBE at such a large angle, the remaining conductive layer height h4is the same as h1, or decreases less than 5 nm after this step. Ex-situ IBE trimming is used when the conductive layer14is made of inert metals and in-situ IBE trimming is needed for metals that can be readily oxidized in air. Compared to the immersion 193 nm or EUV photolithography which is widely used to deliver similar results in the integrated circuit (IC) industry, this high angle IBE trimming is a much lower cost method. The remaining dielectric layer16and photoresist pattern18are consumed during the IBE trimming.

As illustrated inFIG. 4, a dielectric material22such as SiO2, SiN, SiON, SiC, SiCN, or amorphous carbon is deposited to a thickness of ≥100 nm to encapsulate the conductive via14. The dielectric material22may be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). Whether ex-situ or in-situ PVD/CVD/ALD encapsulation is used is dependent on how sensitive these vias are to the atmosphere. Spin-on or amorphous carbon can also be used if the bottom electrode is made of an inert metal.

Chemical mechanical polishing (CMP) is applied to smooth the surface as well as expose the conductive vias14underneath, with remaining via height h5of 45 nm, as shown inFIG. 5. Conductive via14forms the bottom pillar portion of the T-shaped bottom electrode. Now, the top portion of the T-shape will be formed.

A metal layer24such as Ta, TaN, Ti or TiN W, Cu, Mg, Ru, Cr, Co, Fe, Ni or their alloys is deposited with a thickness h6of 10-100 nm and preferably 50 nm over the via14and planarized dielectric layer22, as shown inFIG. 5. Dielectric layer26such as SiO2, SiN, SiON, SiC, or SiCN with thickness h7of ≥20 nm is deposited over metal layer24. Photoresist with a thickness h8of ≥200 nm is deposited and patterned by 248 nm photolithography to form photoresist mask28. The dielectric26and metal layer24are etched by RIE, IBE or their combination to form the pattern size d4of 50-60 nm, as shown inFIG. 6.

FIG. 6illustrates the T-shaped bottom electrode14/24of the present disclosure. The dielectric encapsulation22and remaining hard mask26are stripped off to expose the entire T-shaped electrode. A fluorine carbon plasma with high carbon/fluorine ratio such as C4F8or CH2F2can be used to strip off materials like SiO2, SiN, SiON, SiC, or SiCN, without etching the T-shaped bottom electrode. O2plasma can be used to strip off spin-on or CVD deposited carbon encapsulation. Ex-situ stripping is used when the metal vias are made of inert metals, but in-situ stripping is needed for metals that can be readily oxidized in air.

Now, as shown inFIG. 7, MTJ film layers are deposited, typically including a seed layer, a pinned layer, a barrier layer, a free layer, and a cap layer, for example. These layers form the MTJ film stack30. The MTJ stack30can be deposited ex-situ, but preferrably, the MTJ stack is deposited in-situ. After the MTJ stack is deposited, it only covers the top of the T-shaped bottom electrode14/24as well as the first bottom electrode12on the sides. It should be noted that the MTJ stack is discontinuous because of the undercut structure24/14.

As a result, the MTJ patterns with size d5(50-60 nm) are formed without plasma etch and thus, without plasma etch-induced chemical damage and/or conductive metal re-deposition on the MTJ sidewalls. Now, as shown inFIG. 8, dielectric layer32is deposited and flattened by CMP, for example, wherein the top MTJ surface is exposed. Finally, the top metal electrode34is deposited to form the whole device, also preferably in an in-situ method, as shown inFIG. 9.

In the process of the present disclosure, by decoupling the etch process, we can use a high angle ion beam etching to create a T-shaped bottom electrode to allow for etchless MTJ patterns. The top and pillar T-shaped electrode portions' sizes are sub 60 nm and 30 nm, respectively. After MTJ deposition, the same size of 60 nm MTJ patterns can be electrically isolatedly formed on top of the bottom electrode, without using an etching process. This approach avoids any chemical damage and/or conductive metal re-deposition on the MTJ sidewall, thus improving the MRAM device performance.

FIG. 9illustrates the completed MTJ structure of the present disclosure. We used high angle IBE trimming to fabricate the T-shaped bottom electrode14/24to create MTJ patterns30without using a plasma etch. This approach avoids any chemical damage and/or conductive metal re-deposition on the MTJ sidewall, improving the MRAM device performance. Dielectric layer32covers the MTJ structures. Top electrode34contacted the MTJ structure30.

The process of the present disclosure will be used for MRAM chips of size smaller than 60 nm as problems associated with chemically damaged sidewalls and re-deposition from the bottom electrode become very severe for these smaller sized MRAM chips.

Although the preferred embodiment of the present disclosure has been illustrated, and that form has been described in detail, it will be readily understood by those skilled in the art that various modifications may be made therein without departing from the spirit of the disclosure or from the scope of the appended claims.