The switching performance of a half-bridge arrangement particularly for a converter shall be improved. For this purpose, a half-bridge arrangement has a circuit board having at least four trace layers and two switching elements and a capacitor device arranged on opposite sides of the circuit board and interconnected so as to produce, during a commutation event of the half-bridge arrangement, at least two dipoles having opposite spatial directions.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims the priority of European Patent Application, Serial No. 17155207.8, filed Feb. 8, 2017, pursuant to 35 U.S.C. 119(a)-(d), the content of which is incorporated herein by reference in its entirety as if fully set forth herein.

BACKGROUND OF THE INVENTION

The present invention relates to a half-bridge arrangement for a converter, comprising two switching elements, a capacitor device and a circuit board to which the switching elements and the capacitor device are interconnected to form a half bridge. The present invention also relates to a converter having such a half-bridge arrangement.

A half bridge is a basic building block in power electronics. It is used, for example, in most step-up converter, step-down converter and current and voltage transformer topologies.FIG. 1shows a circuit diagram of a half-bridge arrangement with drive circuitry according to the prior art. The half-bridge arrangement comprises two switching elements T1and T2which can both be implemented as a MOSFET with parallel freewheel diode. The two switching elements are Interconnected at a node1at which the output voltage (generally an AC voltage) is usually present. In this example, the source S of the first switching element T1is connected to the drain D of the second switching element T2via the node1. The drain D of the first switching element T1is usually at the positive DC voltage potential DC+ and is connected to one terminal of a DC-link capacitor C1. Likewise in the example, the source S of the second switching element T2is at a negative DC voltage potential DC− and is connected to the other terminal of the DC-link capacitor C1.

The gate G of the first switching element T1is connected to the output of the first driver TR1. Connected to the supply terminals of the first driver TR1is a capacitor C2which provides a first supply voltage Vcc1. The first driver TR1derives its reference potential from the source S of T1.

The second switching element T2and a second driver TR2are in a similar configuration. The output of this driver is connected to the gate G of the transistor of the second switching element T2. The supply terminals of the driver TR2are connected to a capacitor C3which provides a supply voltage Vcc2. The reference potential for the second driver TR2is again the source S of the second switching element T2.

An important factor for the switching performance of the half bridge is the parasitic Inductance in the commutation circuit. The commutation circuit is the circuit in which the current changes during a switching operation. This commutation circuit KK is shown inFIG. 1and passes through the switching elements T1, T2and C1. Parasitic inductances are also produced by a first drive circuit AK1at the first driver TR1and a second drive circuit AK2at the second driver TR2. The respective drive circuits AK1and AK2pass via the source S and gate G to the outputs of the respective drivers TR1and TR2, via the respective supply terminal to the respective capacitors C2and C3and back to the source S.

In power electronics there is a trend toward higher switching frequencies. As a result, passive components (inductors and capacitors) may be made smaller in many circuits. However, this causes higher switching losses in the components (especially in the case of “hard” switching when the current or voltage are non-zero), as more switching operations take place as the frequency increases. The switching losses are proportional to the switching current, the switching voltage and the switching time. For the same requirement placed on the system (current and voltage are fixed), these can be reduced by faster switching edges. The faster rise or fall times of current and voltage cause overvoltages and put an additional load on the interference immunity in the circuit. The largest effect is produced here by the leakage or parasitic inductances in the commutation circuit KK and in the drive circuits AK1and AK2as shown inFIG. 1.

Particularly at higher powers (higher currents), so-called high-copper circuit boards are used in which the thickness of the copper layer is significantly increased compared to normal types. There, because of the large copper cross-sections and the usual ramps at the board edges, the distances between the components and therefore the Inductances of the current paths are greater. This gives rise to conflicting objectives in the case of high powers and high frequencies.

In addition, switching and on-state power losses in the form of heat are engendered in the power semiconductors. This heat has to be dissipated in order to cool the semiconductors and therefore to be able to use them more intensively.

The problems mentioned are minimized in different approaches. However, each problem is mainly approached individually, resulting in conflicts. For example, so-called modules as shown inFIGS. 2 and 3are used for heat dissipation. There, the power semiconductors, i.e. switching elements T1and T2, are mounted on a DCB substrate2(Direct Copper Bonding). The DCB substrate2is mostly fixed to an aluminum base plate3. A heat sink4is disposed on the opposite side of the aluminum base plate3. The switching elements T1and T2are encapsulated in an insulator5through which interconnects6project. A module7is therefore formed by the aluminum base plate3, the DCB substrate2and the insulator layer5with the encapsulated switching elements T1and T2and the interconnects6. The module7is attached to a circuit board8on the side opposite the heat sink4. The interconnects6constitute the electrical connections from the switching elements T1and T2to the circuit board8. The DC-link capacitor C1and the drivers TR1and TR2can be disposed on the opposite side of the circuit board8.

InFIG. 2it is indicated that the drive circuits AK1and AK2are basically created between internal interconnects6and the DCB substrate2and the circuit board8, whereas, as shown inFIG. 3, the commutation circuit KK is created between the external interconnects6and the DCB substrate2and circuit board8. It is not automatically possible to optimize the leakage inductances of the drive circuits AK1, AK2and of the commutation circuit KK, as the inductances are dominated by the module7. Because of this, these designs are generally unsuitable for higher switching frequencies.

Another approach is to design using discrete elements such as THT components (Through-Hole Technology) and SMD components (Surface Mounted Device). As in the case of module-type design, THT semiconductors offer only limited scope for low-inductance connection. Although this design also allows a connection to a heat sink to be provided, high frequencies are only rarely realized, and it will therefore not be discussed further here.

SMD circuit board design provides greater optimization potential here in respect of higher frequencies. Two frequently used designs will now be shown in connection withFIG. 4andFIG. 5, namely one-sided and two-sided component placement.FIG. 4shows the one-sided placement variant. Here all the components T1, T2, TR1, TR2, C1, C2and C3are disposed on one side of a board (not shown). The drive circuits AK1, AK2and the commutation circuit KK are located in one plane. Maximum optimization of the leakage inductance here resides in the size of the discrete elements. For this variant, heat dissipation is difficult to achieve for the power electronics.

The two-sided placement variant as shown inFIG. 5mainly uses the same drive circuitry as inFIG. 4and differs primarily in that one of the three main components T1, T2or C1is on the back of the board8. As can be seen fromFIG. 5, the commutation circuit KK is dependent on the thickness of the board8(e.g. 1.6 mm). However, heat dissipation from the high-side switch T1in particular is also difficult with this design, as most discrete power semiconductors refer their thermal pad for heat dissipation to source potential and this must be kept small for interference immunity reasons.

Any leakage inductances L can be estimated using the formulas below. This enables qualitative design improvements to be achieved. Formula [1] below relates, as shown inFIG. 6, to a conductor9and10which is in no or virtually no field of another conductor. Formula [2] relates, as shown inFIG. 7, to the case that two conductors with contrary flow directions are positioned opposite one another. The respective geometric dimensions t, w, l of the conductors9and10and, where applicable, their spacing h are marked inFIGS. 6 and 7and used in the respective formulas [1] and [2] below.

The effect of the commutation inductance on the losses in a half bridge can be observed inFIG. 8. This shows power loss Pvversus leakage inductance L. The power loss Pvincreases constantly toward higher leakage inductances. This effect is noticeable particularly at higher frequencies and currents as the main loss component in this half bridge configuration.

It would therefore be desirable and advantageous to obviate prior art shortcomings and to provide an improved half-bridge arrangement which is less sensitive to switching events.

SUMMARY OF THE INVENTION

According to the present invention, a half-bridge arrangement for a converter is provided, comprising two switching elements, a capacitor device and a circuit board to which the switching elements and the capacitor device are interconnected to form a half bridge. The half-bridge arrangement can in principle also be used for other purposes apart from converters. IGBTs, but also other power switches, can be used for the two switching elements. The capacitor device is used to store or buffer energy and is typically implemented as a DC-link capacitor. The switching elements are disposed in a usual manner on a circuit board and interconnected to form a half bridge which is connected to the capacitor device.

The circuit board has at least four trace layers. This makes it possible for current loops perpendicular to the main surface of the circuit board to be formed within the circuit board when there is a commutation event. During such an event when the switch state of one or both of the switching elements changes, at least one commutation circuit is created whose parasitic inductance is important for the switching performance of the half-bridge arrangement. Advantageously, the switching elements and the capacitor device are disposed on the circuit board and connected by means of the circuit trace layers such that, during a commutation event, at least two dipoles of opposite direction are produced in the circuit board. Two parallel commutation circuits are thus created whose respective currents produce dipoles of opposite direction. The fact that the dipoles are of opposite direction causes their effects to be mutually attenuated, resulting in an improvement in the switching performance of the half-bridge arrangement.

The half-bridge device advantageously has two capacitors or another even number of capacitors which are disposed symmetrically on the circuit board. A symmetrical arrangement of this kind enables identically dimensioned dipoles of opposite direction to be generated during a commutation event, i.e. in the event of a commutation.

In addition, the switching elements and the capacitors can be disposed on both sides of the circuit board. The advantage of this is that, for example, a point-symmetric arrangement of the components can be achieved. In such an arrangement, sufficient cooling surface area can be provided on both sides of the circuit board simultaneously.

The switching elements and the capacitor device can also be arranged and interconnected such that during a commutation event two dipoles of opposite direction are produced in two different spatial directions in each case. For the design of the half-bridge arrangement, not just one but at least two spatial directions that are different from one another and non-parallel are therefore used for the dipoles. For the respective opposing dipoles, one of the dipoles is then aligned with the spatial direction and the other dipole is oriented counter to this spatial direction. The same applies to the at least one other spatial direction.

In a specific embodiment, the circuit board can have four trace layers, and at least four parallel commutation circuits occur during a commutation event. The objective is to minimize the total parasitic inductance of the half-bridge arrangement. As the commutation circuits are connected in parallel with one another, it is advantageous if one of the commutation circuits has a very small inductance. The resulting total inductance is then smaller than the smallest individual inductance. The objective can be more easily met the more commutation circuits are available. Thus a half-bridge arrangement whose circuit board has more than four trace layers can also be implemented such that more than four commutation circuits can be created.

The commutation circuits are preferably disposed symmetrically with respect to one another. This means that the commutation currents cancel each other out, resulting in reduced noise emission.

In another embodiment, the half-bridge arrangement has a driver device which is disposed such that a driver current direction of a main current of the driver device is perpendicular to a commutation current direction of a main current in the commutation circuit during a commutation event. This can prevent the driver circuit or more specifically the driver device from being easily coupled into the commutation circuit or more specifically the switching elements of the commutation circuit and the switching performance of the half-bridge arrangement from being affected. Due to the perpendicular arrangement of the driver current direction and the commutation current direction, it can rather be achieved that the currents of the circuits in question have little effect on one another.

In another advantageous embodiment, a center tap of the half bridge is made as small as possible, in particular less than five percent of the circuit board. The center tap of the half bridge conventionally produces an AC voltage. If the center tap is therefore made as small as possible, the interference immunity of the entire half-bridge arrangement is increased, as there is less coupling to other components or devices.

In addition, the circuit trace layers can each have a copper fill factor that is as high as possible. This has advantages in respect of conducting heat away from the half-bridge arrangement. In fact, not only the circuit board substrate but in particular the copper is then used for heat dissipation, the latter possessing a very high coefficient of thermal conduction.

In a particular application, a converter is equipped with the above mentioned half-bridge arrangement. In the case of converters, the commutation events occur continuously, which means that it is particularly necessary for them that the switching performance is as far as possible not subject to parasitic inductances.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The examples described in more detail below are preferred embodiments of the present invention. It should be noted that the individual features can be implemented not only in the feature combinations described, but on a stand-alone basis or in other technically meaningful combinations.

The examples refer to a half-bridge arrangement that is preferably used in a converter. The individual devices and components are to be designed according to the required powers.

A particular focus of attention is the arrangement of the components and the design of the circuit board8. The components here include in particular those of the half bridge itself including the driver components and the component or components of the capacitor device.

FIG. 9shows four layers11,12,13and14of a typical circuit board. Each layer represents a corresponding conductor or copper layer. For example, the first layer11and the third layer13are at positive potential DC+ and the second layer12and fourth layer14at negative potential DC−. In addition to the circuit trace layers11to14, the components and via holes or interconnects6directly assigned to the circuit trace layers are also marked onFIG. 9. Vertical stacking of the individual layers11to14produces a circuit board or more specifically half-bridge arrangement having the cross-sections as shown inFIG. 10andFIG. 11.

Each of the four layers11to14has a main section15which is here rectangular and whose longitudinal direction16extends parallel with the orientation of the series arrangement of the switching elements T1and T2. It should be noted that the switching elements T1and T2are on different sides of the circuit board8. In this example, the DC-Ink capacitor is implemented by two capacitors C11and C12. These two capacitors are also on different sides of the circuit board8(cf.FIG. 11). In their arrangement, the two capacitors C11and C12are on the same line as the series arrangement of the switching elements T1and T2, i.e. parallel to the longitudinal direction16. The cross-section through the circuit board arrangement according toFIGS. 11 to 14runs parallel to the longitudinal direction16.

A driver section17is located on a long side of each main section15of each layer11to14. This driver section17is used for contacting the elements of the respective driver or drive circuits AK1and AK2(cf.FIG. 1). Thus the driver sections17of the first layer11and of the second layer12connect the driver TR1and the capacitor C2to the associated switching element T1. Similarly, the driver sections17of the third layer13and of the fourth layer14connect the second driver TR2and the capacitor C3to the second switching element T2. In addition, for the individual layers, the so-called “pads” for contacting the switching elements T1and T2can be seen. In particular, the pads for drain D, source S and gate G of the switching elements T1and T2are indicated.

Also marked in the third layer13is a commutation current direction18running parallel to the longitudinal direction16. The commutation current flows along this commutation current direction18through the components T1, T2, C11and C12. The double arrow of the commutation current direction18indicates that the commutation current can also run contrary to the longitudinal direction16.

A driver current direction19is produced perpendicular to the longitudinal direction16. A main flow direction of the driver current therefore corresponds to the driver current direction19. As the double arrow again indicates, the driver current can run in two opposite directions. The fact that the driver current direction19and the commutation current direction18run perpendicular to one another, i.e. the drive path is at right angles to the commutation path, is a particularly noteworthy aspect. As a result, the current flows and therefore also the H-fields thereof are oriented predominantly orthogonally with respect to one another, which means that they have little effect on each other. This increases the interference immunity of the half-bridge arrangement.

As mentioned above, one switching element T1with drive arrangement TR1and C2is on one side of the circuit board8, e.g. the top side, and the other switching element T2with drive arrangement TR2and C3is on the other side, e.g. the underside. As a result, the switching elements and associated drivers are thermally decoupled. Heat can be removed via the vacant surfaces20(cf.FIGS. 10 and 11). The spread of heat over the surface area can be increased by the thickness of the copper layer and the copper fill factor of the inner layers. Heat dissipation of this kind is generally more effective than heat dissipation via the substrate21of the circuit board8. It is preferable here to use a switching element having a “thermal pad” at the drain terminal. This thermal pad is made larger than the other terminals for gate G and source S. It is also preferable that the potentials of the individual layers11to14alternate, e.g. DC+, DC−, DC+, DC−.

FIG. 10shows a cross-section along the driver current direction19through the completely assembled circuit trace arrangement or more specifically half-bridge arrangement. The individual circuit trace layers11to14are stacked to form the (here) four-layer circuit board8, insulated by the circuit board substrate21. Directly mounted on the first circuit trace layer11are the components T1, TR1and C2and directly on the fourth circuit trace layer14the components T2, TR2and C3. A via hole or interconnect6connects the source S of switch element T1to the drain D of switching element T2. Other interconnects6are marked between the first circuit trace layer11and the second circuit trace layer12and between the third circuit trace layer13and the fourth circuit trace layer14.

FIG. 10shows the particular design on the drive circuitry for T1and T2. The gate G is connected on the respective outer layer and a layer below is connected back again on an unloaded source terminal of planar design of the respective switching element T1or T2. This not only reduces the drive inductance, but also increases the interference immunity.

FIGS. 11 to 14show, in schematic form, cross-sections through the circuit board arrangement or more specifically half-bridge arrangement parallel to the commutation current direction18i.e. the longitudinal direction16. Particularly noticeable here is the point symmetry of the arrangement of the components T1, T2, C11and C12. This symmetry gives rise to specific conditions with regard to the respective commutation circuits. Examples of these commutation circuits are shown inFIGS. 11 to 14. They are created simultaneously during a commutation event, i.e. a change of switch state of the switching elements T1and/or TR2.

InFIG. 11a first commutation circuit KK1is marked. It begins in the first circuit trace layer11at capacitor C11(part of the DC-link capacitor C1), runs via the second layer12and an interconnect to the source S of T2(fourth layer14), then to the drain D of T2, onward via an interconnect6to the source S and drain D of T1(first layer11), and back to the other terminal of capacitor C11. This creates two current meshes running contrary to one another. Thus, according to the “right-hand rule”, this results in a dipole δ+and an opposing dipole δ−. The effect of the two dipoles of the first commutation circuit KK1is therefore reduced because of their opposite directions.

In symmetry therewith, a similar commutation circuit KK2is created by the symmetrically arranged second switching element T2and the corresponding capacitor C12of the DC-link capacitor C1, as shown inFIG. 12. Once again the opposing dipoles δ+and δ−are produced in the same way.

A third commutation circuit KK3is created as shown inFIG. 13. The commutation circuit here runs from the drain D via the source S of the switching element T1(first layer11), on to the drain D and source S of the switching element T2(fourth layer14), then through the capacitor C12(fourth circuit trace layer14) and back via the second circuit trace layer12to the drain D of the switching element T1. The corresponding mesh loops again produce the two opposing dipoles δ+and δ−.

Similarly, because of the symmetrical arrangement, a fourth commutation circuit KK4as shown inFIG. 14from the source S via the drain D of T2is created, and so on.

Use of the inner layers means that the commutation paths are routed past one another in a planar manner, which minimizes their inductance. In addition, as shown inFIGS. 11 to 14, parallel commutation circuits KK1to KK4are formed, resulting in a paralleling of the respective inductances and thus achieving a further reduction in the total inductance. The concept can be extended as required by additional inner layers, result in further paralleling and thus ever lower inductances in the commutation path.

A particularly important feature in this arrangement is the symmetry of the commutation paths. The commutations currents are thereby additionally canceled out, resulting in low noise emission of the circuit as a whole.

Another aspect relates to the shielding of the center tap (denoted by “AC” in the third layer13inFIG. 9) of the half bridge. This center tap oscillates relative to the “fixed” DC-link potentials. This is therefore made as small as possible, resulting in a lower parasitic capacitance and therefore less interference. It should be emphasized that the complete connection is optimally shielded in this way from an EMC standpoint (cf. second layer12above it and fourth layer14below it).

Vertical mounting is to be recommended as a preferred arrangement for passive cooling of circuit. By this means, heat can be dissipated on both sides of the circuit board8.

The design shown in the exemplary embodiment can also be used for connecting a plurality of switches (particularly GaN-on-Si switches) in parallel with a driver, the thermal coupling between the switches being particularly important here. Thus, a symmetrical current distribution between the switches is achieved.

The particular advantage of the half-bridge arrangement described above is the specific geometric arrangement of the half-bridge components. Using a multi-layer board and taking the symmetry into account results in a very low-inductance design. A passive heat dissipation solution on the circuit board is also shown, which means that no additional cooling is required. Another positive aspect is the optimized EMC performance, which is of enormous importance particularly for fast-switching devices (GaN-on-Si or Si—C).

The low-inductance design therefore confers advantages due to the parallel commutation paths. The resulting switching overvoltages are smaller and the switching losses lower. In addition, higher switching frequencies are possible, and the inductances can be further reduced by additional inner layers.

In respect of interference immunity, a notable advantage is that less external circuitry is required, higher switching speeds and switching frequencies are possible, and the EMC load is reduced. The latter results in particular from the shielding of the center tap, field cancellation of commutation circuit and drive circuit (perpendicular arrangement) and the fact that the fields of the parallel commutation circuits cancel each other out (symmetrical design).

Another advantage is that the inductances are independent of the board thickness. In particular, low inductances are produced even in the case of high layer thicknesses when the components have to move further apart because of the ramp profile at the copper edges. Lastly, the above half-bridge arrangement also make it possible to optimize cooling. In particular, an improved heat spread over the circuit board as well as two-sided heat dissipation can be achieved.