Method for achieving smooth side walls after Bosch etch process

A method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.

BACKGROUND

Deep aspect ratio silicon etching is one of the principal technologies currently being used to fabricate microstructure devices, and is an enabling technology for many microelectromechanical systems (MEMS) applications. A conventionally used single-crystal silicon deep aspect ratio etch process is based upon a cyclic plasma etch/polymer deposition method, also known as Rapid Alternating Parameters (RAP) process, or a Bosch process.

FIGS. 1A-Fillustrate a conventional method of etching silicon in a Bosch process.

FIG. 1Aillustrates a first step in the conventional Bosch etching process.

As shown in the figure, a silicon layer100has a top surface102, upon which a photoresist mask104is disposed. Photoresist mask104includes a window106, wherein a portion of surface102is exposed.

Silicon layer100with photoresist mask104is placed in a standard silicon etching chamber to begin the etching process.

FIG. 1Billustrates a second step in the conventional Bosch etching process.

As shown in the figure, the portion of silicon layer100that is exposed through window106has been etched so as to create via108. Via108includes a side wall110and a bottom surface112.

Via108is created by generating an etching gas plasma in the etching chamber. An example gas used to etch silicon is SF6, however other gases may be used. The etch depth is controlled by introducing the gas into the chamber at a specific flow rate and pressure for a certain amount of time, with silicon layer100at a specific voltage, or bias, and RF power is provided to form an etch plasma. The gas removes the silicon in an isotropic manner. Isotropy is uniformity in all directions. As such, the etching process removes silicon in all directions equally. In three-dimensional space, the result of the isotropic removal is a spherical hole. This is indicated in the figure by the circular shape of side wall110and bottom surface112of via108in two-dimensional space.

FIG. 1Cillustrates a third step in the conventional Bosch etching process.

As shown in the figure, protective layer116is disposed upon both a top surface114of photoresist mask104, side wall110and bottom surface112of via108.

Protective layer116may include a polymer that decreases lateral etching as compared to vertical etching. Accordingly, the width of via108docs not increase throughout the process. While other materials may be used, one non-limiting example of a material used for a protective layer is C4F8.

FIG. 1Dillustrates a fourth step in the conventional Bosch etching process.

As shown in the figure, most of protective layer116has been removed to leave protective surface118disposed on side wall110of via108. Protective surface118docs not cover bottom surface112. As such, bottom surface112is exposed through a window120of protective surface118.

In order to continue vertical etching into silicon layer100, without lateral etching, it is necessary to clear protective layer116from bottom surface112, while maintaining protective surface118on side wall110. Without protective surface118, additional etching steps would increase the width of via108due to the isotropic nature of the etching process. Protective layer116may be removed from bottom surface112using known methods as part of a conventional Bosch process.

FIG. 1Eillustrates a fifth step in the conventional Bosch etching process. As shown in the figure, silicon layer100has been etched a second time to create via126, with side walls110and122and bottom surface124.

Due to the isotropic nature of the etching process, the second etch process removes protective layer118and also creates via126. Creating via126does not increase the size of side wall110as the etching gas does not contact side wall110due to protective layer118.

FIG. 1Fillustrates a final via produced by multiple cycles in the conventional Bosch etching process.

As shown in the figure, silicon layer100has been etched a plurality of times to create via128. The process of etching and deposition continues in an alternating fashion until a via of the desired depth is created.

The isotropic nature of the etching process tends to create vias that are essentially semi-spherical because the etching gas has no directional component and attacks all surfaces equally. The result is that each etch undercuts the previous etch such that the wall of the completed via has an undulating nature with peaks and troughs. The collection of peaks and troughs are called scallops. Depending on the processing parameters, the depth and width of the scallops can change. This will be described in greater detail with reference toFIGS. 2-3.

FIG. 2illustrates an enlarged view of side wall110and122ofFIG. 1E.

As shown inFIG. 2, side walls110and122form a scallop202, which includes peaks204and206. Scallop202has a width, W, measured as the longest horizontal distance between peak204or206and side wall110. Scallop202also has a depth, H, measured as the vertical distance between peaks204and206. Width, W, and depth, H, are variables that are controlled by the processing parameters under which the via is created. For example, one process incorporating certain parameters for a given amount of time will create scallops of a specific size. Increased exposure time, while maintaining all other parameters constant, would result in a large scallop.

If a less aggressive etching process is performed, the relative difference between the peaks and troughs of the scallops may be decreased. However, many more scallops will be formed to reach the same depth. An additional scallop is formed each time the etching process is repeated. This will be described with reference toFIG. 3.

FIG. 3illustrates another example of side walls created by etching a via with a conventional Bosch process using different etching parameters.

As shown in the figure, a side wall302includes a plurality of peaks, a sample indicated by peaks306and308. A scallop310has a width, w, measured as the longest horizontal distance between peak306or308and side wall302. Scallop310also has a depth, h, measured as the vertical distance between peaks306and308.

When performing a more aggressive etching process, a via of the desired depth can be created relatively quickly with a single etching step. A disadvantage of performing this aggressive etch is that, due to the isotropic nature of the etching process, the scallop created during this process would be very large.

In contrast, when performing a less aggressive etching process, creating a via of the desired depth will take more time. The increase in total processing time is a result of performing multiple etching steps for a short amount of time. The advantage of performing a less aggressive etch is that each scallop created is much smaller, however many more scallops are required to produce a via of the same depth.

For optimum semiconductor performance, the plurality of scallops created during the etching process would be completely removed, leaving a smooth-walled via. There are methods to reduce the profile of the scallops by modifying processing parameters, however there is no known method to completely eliminate scallops from the side wall of a via.

U.S. Pat. No. 6,846,746 (Ratner et al.) provides a method to reduce scallops, but not fully eliminate them, in etch applications. Scallop reduction is accomplished by oxidation of the scallop peaks, followed by an etch suitable for removal of silicon oxides. The primary gases disclosed are CF4and O2, though the patent also describes a non-oxidative process with SF6, and there is a brief mention of NF3. The parameters disclosed for processing with SF6and NF3differ greatly. The disclosed flow range for fluorine-containing gases: is 2-50 sccm in combination with a flow of He of 2-200 sccm, at a pressure of 1-30 mtorr. Further, the process described in Ratner et al. uses a bias of 10-40V in the processing chamber. This bias directs fluorine ions to chemically react with the scalloped side walls. The chemical reaction takes a large amount of time and creates unwanted undercutting within the trench.

Published US Patent application 2009/0272717 A1 (Pamarthy et al.) also provides a method to reduce scallops, but not fully eliminate them, in etch applications. Scallop reduction is accomplished by invoking fast gas switching in an attempt to overcome the formation of scallops, however the disclosed on/off times are greater than 1 second. Additionally, the unused gas is dumped into an exhaust stream, thereby wasting about half the gas, which is undesirable. Furthermore, the proposed method results in typical scallop measurements of 1.5 microns.

The scallops discussed above are undesirable, and no conventional etching process completely eliminates scallops.

What is needed is an improved etching process that does not produce a scalloped via. This processing method must maintain the integrity of the via, meaning the via dimensions must not be increased.

BRIEF SUMMARY

The present invention provides an improved method to eliminate scallops on the side wall of a via created using a conventional etching process, like the Bosch process.

In accordance with an aspect of the present invention, a method is provided for etching silicon in a plasma processing chamber, having an operating pressure and an operating bias. The method includes: performing a first vertical etch in the silicon to create a hole having a first depth and a sidewall; performing a deposition of a protective layer on the sidewall; performing a second vertical etch to deepen the hole to a second depth and to create a second sidewall, the second sidewall including a first trough, a second trough and a peak, the first trough corresponding to the first sidewall, the second trough corresponding to the second sidewall, the peak being disposed between the first trough and the second trough; and performing a third etch to reduce the peak.

DETAILED DESCRIPTION

As a result of the alternating processes of etching and deposition, the exposed surface of scallops is no longer pure silicon, but comprise a combination of silicon, fluorine, carbon and sulfur, which are byproducts of the etching process. This will be described in greater detail with reference toFIG. 4.

FIG. 4illustrates an enlarged view of side walls122and110ofFIG. 1E.

As shown inFIG. 4, material400is created during the conventional silicon etching process. Material400is thickest at peaks204and206and thinnest at the bases of troughs110and122.

FIG. 5illustrates a via created in silicon after a plurality of steps of a conventional silicon etching process.

As shown in the figure, material400is disposed between via128and silicon layer100. Material400is in contact with silicon layer100at boundary layer500.

For optimum semiconductor performance, material400, and with it, the plurality of scallops created during the etching process, would be completely removed, leaving a smooth wall of pure silicon at boundary layer500.

In accordance with aspects of the present invention, a post-processing step is used to remove scallops created during the etching process, thus leaving a smooth-walled via. This will be further described with reference toFIG. 6.

FIG. 6illustrates a via created in silicon after a plurality of steps of a conventional silicon etching process, followed by a post-processing step in accordance with aspects of the present invention.

As shown in the figure, via600has been created in silicon layer100. Via600includes a smooth side wall602and a bottom surface604.

Smooth side wall602is created after the conventional etching process by incorporating a post-processing step to eliminate the scallops created during the etching process.

In the post-processing step, another gas is introduced that has a chemistry to selectively remove the scallops from the side wall of the via while leaving the remaining silicon intact. As non-limiting examples, the gas may include NF3, CF4, SF6, Ar, He, O2, N2and combinations thereof. In a preferred embodiment, to remove scallops from a via that is from 3 to 10 microns in diameter and 40 to 150 microns deep, gas flows of 100 to 500 sccm CF4and 300 to 1000 sccm NF3are introduced into the chamber for 15 to 180 seconds.

The pressure at which the gas is introduced to the chamber should be balanced such that the scallops at the top of the via are removed at the same rate as those at the bottom of the via. The pressure range in which scallops can be removed with the disclosed postprocessing steps is 15-100 mtorr. In a preferred embodiment, to remove scallops from a via that is 5 microns in diameter and 60 microns deep, a pressures in the range of 40 to 80 mtorr was found to be most effective. Using pressures higher than 100 mtorr can result in deformation of via profile, which is undesirable.

The operating bias within the chamber serves to direct the gas ions to the peaks of the scallops to preferentially remove the peaks while leaving the troughs unmolested, and thus not increasing the diameter of the via. The operating bias under which the scallops can be removed most effectively is 200-1000V. In a preferred embodiment, to remove scallops from a via that is 5 microns in diameter and 60 microns deep, an operating bias of 700 Volts was found to be most effective. Using a bias higher than 1000V can result in rapid removal of the photoresist mask, which is undesirable because the top layer of silicon would be left unprotected and could be damaged.

In contrast with Ratner et al., discussed above, a method in accordance with aspects of the present invention uses a much higher bias. The 200-1000V bias of the plasma processing chamber in accordance with the present invention induces ion bombardment to remove the scallops. This ion bombardment removes the scallops in a much faster time period as compared to the chemical reaction used by Ratner et al. discussed above. Further, in contrast with the chemical reaction used by Ratner et al. discussed above, the ion bombardment of the present invention drastically reduces undercutting of the via.

In summary of a preferred embodiment, removal of scallops from a via that is 3 to 10 microns in diameter and 40 to 150 microns deep is accomplished using gas flows of 100 to 500 sccm CF4and 300 to 1000 sccm NF3for 70 seconds, at a pressure of 40 to 80 mtorr with a 200 to 1000V operating bias, and transformer coupled plasma (TCP power) at 1.0 3.5 kW.

In some cases, it may be necessary to employ an intermediate step after etching is complete, but before post-processing steps discussed above, to remove the scallops. The etching process typically leaves some deposition on the sidewalls, even after the final etch is complete. When the deposition covers the troughs and not the peaks of the scallops, an intermediate step is not required and the peaks can be removed by the post-processing steps discussed above. The remaining deposition can actually act as a protective layer during scallop removal to prevent damage to the protective films, such as oxides, low k oxides and nitrides, on top of the silicon.

If the deposition partially or completely covers the peaks of the scallops, an intermediate step may be required. The intermediate step may include using a plasma of O2or a combination of O2and CF4to remove the deposition. As a non-limiting example of the intermediate step, the pressure would be 5-100 mtorr, TCP power of 500-3000 W, operating bias of 50-300V, and gas flows of 200-1000 sccm of O2and 0-10% additional flow of CF4.

In other cases, there may not be enough deposition to prevent damage to the protective films on top of the silicon. In those instances, it may be necessary to add to the existing deposition layer to protect those films, as the fluorine in NF3and CF4can attack the films if they are not protected. The addition to the deposition layer may include a fluorocarbon layer that is concentrated at the top of the via. This can be achieved by using high operating pressures, non-limiting examples of which include 40-200 mtorr, and low operating biases, such as 0-100V, with TCP power in the range of 500-3000 W, and gas flows in the range of 100-1200 sccm. Non-limiting examples of gases used include polymerizing fluorocarbons, particularly C4F8and SF6, with flows of SF6from 0-15% of the fluorocarbon flow. In addition to C4F8, other polymerizing gases such as C4F6can be used.

In some cases, particularly after an oxidative deposition clearing step, the silicon will be oxidized such that alternative Silicon Oxide removal is necessary. This will require the addition of other fluorocarbons to the CF4or substitution of CF4with these fluorocarbons. Alternative fluorocarbons can be CHF3, CH2F2, C2F6, C2F4H2and combinations thereof. The flows of fluorocarbons will be similar to the flows of CF4100 to 500 sccm. In addition it may be of value to deliberately oxidize the scallop peaks, as indicated above with clearing or partial clearing of excess polymer. The removal of partially oxidized scallops is achieved more effectively using these fluorocarbons rather than CF4only.