Hybrid bond pad structure

The present disclosure relates to a multi-dimensional integrated chip having a redistribution layer vertically extending between integrated chip die, which is laterally offset from a back-side bond pad. The multi-dimensional integrated chip has a first integrated chip die with a first plurality of metal interconnect layers disposed within a first inter-level dielectric layer arranged onto a front-side of a first semiconductor substrate. The multi-dimensional integrated chip also has a second integrated chip die with a second plurality of metal interconnect layers disposed within a second inter-level dielectric layer abutting the first ILD layer. A bond pad is disposed within a recess extending through the second semiconductor substrate. A redistribution layer vertically extends between the first plurality of metal interconnect layers and the second plurality of metal interconnect layers at a position that is laterally offset from the bond pad.

BACKGROUND

A multi-dimensional integrated chip is an integrated circuit having multiple substrates or die which are vertically stacked onto and electrically interconnected to one another. By electrically interconnecting the stacked substrates or die, the multi-dimensional integrated chip acts as a single device, which provides improved performance, reduced power consumption, and a reduced footprint over convention integrated chips. Therefore, multi-dimensional integrated chips provide a path to continue to meet the performance/cost demands of next-generation integrated circuits without further lithographic scaling.

DETAILED DESCRIPTION

Three-dimensional integrated chips (3DIC) are manufactured by stacking a plurality of integrated chip die on top of one another. The plurality of integrated chip die are separately produced by forming one or more metallization layers within ILD layers overlying separate semiconductor substrates. One or more redistribution layers are then formed within the ILD layers over the metallization layers and a planarization process (e.g., a chemical mechanical polishing process) is performed to form a planar surface comprising the redistribution layers and the ILD layer. The planar surfaces of the separate integrated chip die are then brought together so that the redistribution layers of the separate integrated chip die abut. A bond pad is subsequently produced within a recess vertically extending through an upper substrate to an underlying metallization layer, so as to provide an electrical connection between the bond pad and the multi-dimensional integrated chip.

When the planarization process is performed on the separate integrated chip die, an upper surface of the redistribution layer may ‘dish’ to form a concave surface that drops below the surrounding ILD layer. When the planar surfaces of two integrated chip die are subsequently brought together, the concave surfaces come together to form one or more bubbles at the interface of the two integrated chip die. The bubbles structurally weaken a region below the bond pad, such that if a force used to form a bonding structure onto the bond pad is too large, the structure underlying the bond pad may crack and damage the multi-dimensional integrated chip.

The present disclosure relates to a multi-dimensional integrated chip having a redistribution layer vertically extending between integrated chip die, which is laterally offset from a back-side bond pad, and a corresponding method of formation. In some embodiments, the multi-dimensional integrated chip has a first integrated chip die with a first plurality of metal interconnect layers disposed within a first inter-level dielectric (ILD) layer arranged onto a front-side of a first semiconductor substrate. The multi-dimensional integrated chip also has a second integrated chip die with a second plurality of metal interconnect layers disposed within a second ILD layer abutting the first ILD layer. A bond pad is disposed within a recess extending through the second semiconductor substrate. A redistribution layer vertically extends between the first plurality of metal interconnect layers and the second plurality of metal interconnect layers at a position that is laterally offset from the bond pad. Since the redistribution layer is laterally offset from the bond pad, a region underlying the bond pad is devoid of bubbles along the interface between the first integrated chip die and the second integrated chip die. Without bubbles underlying the bond pad, the structural integrity of the bond pad is increased, thereby reducing cracking and damage to the multi-dimensional integrated chip.

FIG. 1illustrates some embodiments of a stacked integrated chip100having a back-side bond pad.

The stacked integrated chip100comprises a first integrated chip die102and a second integrated chip die110. The first integrated chip die102comprises a first back-end-of-the-line (BEOL) metallization stack108arranged onto a front-side104aof a first semiconductor substrate104. The first BEOL metallization stack108comprises one or more metal interconnect layers arranged within a first inter-layer dielectric (ILD) layer106comprising one or more ILD materials (e.g., a low-k dielectric material, silicon dioxide, etc.). In some embodiments, the first semiconductor substrate104may comprise a device region105having a plurality of semiconductor devices (e.g., transistor devices, capacitors, inductors, etc.) and/or MEMs devices.

The second integrated chip die110comprises a second back-end-of-the-line (BEOL) metallization stack116arranged onto a front-side112aof a second semiconductor substrate112. The second BEOL metallization stack116has one or more metal interconnect layers arranged within a second ILD layer114comprising one or more ILD materials. In some embodiments, the second semiconductor substrate112may comprise integrated chip devices, imaging devices, or MEMs devices, for example. The first integrated chip die102is vertically stacked onto the second integrated chip die110in a face-to-face (F2F) configuration, such that the first ILD layer106abuts the second ILD layer114.

A bond pad120, which is in electrical contact with the second BEOL metallization stack116, is arranged within a recess122that extends through a portion of the second semiconductor substrate112(e.g., from the front-side112aof the substrate to a back-side112bof the substrate). The bond pad120comprises a conductive material (e.g., a metal such as aluminum) and has an upper surface that is exposed by the recess122. The bond pad120is configured to provide an electrical connection between the stacked integrated chip100and an external device. For example, a solder bump (not shown) may be formed onto the bond pad120to connect the bond pad120to an external I/O pin of an integrated chip package. In some embodiments, the bond pad120may comprise a slotted bond pad. The slotted bond pad comprises protrusions120bextending vertically outward from a lower surface of a base region120ato an underlying metal interconnect layer within the second BEOL metallization stack116. In some embodiments, pad openings124are arranged within an upper surface of the base region120a. The pad openings124may vertically extend to within the protrusions120b.

A first metal routing layer109disposed within the first BEOL metallization stack108extends laterally outward from a bond pad area126underlying the bond pad120. In some embodiments, within the bond pad area126the first BEOL metallization stack108and/or the second BEOL metallization stack116may be a solid bond pad having metal vias arranged between one or more solid metal wire layers (e.g., a solid intermediate metal wire layer and/or a solid top metal wire layer). In other embodiments, within the bond pad area126the first BEOL metallization stack108and/or the second BEOL metallization stack116may be a slotted bond pad having metal vias arranged between one or more slotted metal wire layers (e.g., a slotted intermediate metal wire layer and/or a slotted top metal wire layer). In some embodiments, the first metal routing layer109laterally extends beyond an adjacent metal wire layer. Similarly, a second metal routing layer117disposed within the second BEOL metallization stack116laterally extends outward from the bond pad area126in a same direction as the first metal routing layer109.

The first metal routing layer109is electrically connected to the second metal routing layer117by way of a redistribution structure118that is laterally offset from the bond pad120. The redistribution structure118comprises a conductive material that vertically extends from within the first ILD layer106to within the second ILD layer114. In some embodiments, the redistribution structure118may comprise copper and/or aluminum, for example. Since the redistribution structure118is laterally offset from the bond pad120, the bond pad area126is devoid of routing between the first BEOL metallization stack108and the second BEOL metallization stack116.

In some embodiments, the redistribution structure118may comprise a bubble or void119arranged along an interface128between the first integrated chip die102and the second integrated chip die110. However, since the redistribution structure118is laterally offset from the bond pad area126, the bond pad area126is devoid of void along the interface between the first integrated chip die102and the second integrated chip die110. Without voids underlying the bond pad120, a bonding structure (e.g., a wirebond ball) can be formed onto the bond pad120without damaging the underlying structure of stacked integrated chip100.

FIG. 2Aillustrates a cross-sectional view of some additional embodiments of a stacked integrated chip200having a back-side bond pad.

The stacked integrated chip200comprises a first integrated chip die102, and a second integrated chip die201that is vertically stacked onto the first integrated chip die102in a F2F configuration. The first integrated chip die102comprises a first BEOL metallization stack204disposed within a first ILD layer202arranged onto a front-side of a first semiconductor substrate104. The first BEOL metallization stack204includes a first plurality of metal interconnect layers comprising alternating layers of metal wires206a(configured to provide lateral connections) and metal vias208a(configured to provide vertical connections). The first plurality of metal interconnect layers further include a first upper metal wire layer210(e.g., a top metal wire layer within the first BEOL metallization stack208) that laterally extends to a position outside of a bond pad area126(e.g., to a position that is laterally offset from slotted bond pad226).

The second integrated chip die201comprises a second BEOL metallization stack214disposed within a second ILD layer212arranged onto a front-side of a second semiconductor substrate224. The second BEOL metallization stack214includes a second plurality of metal interconnect layers comprising a bond pad layer216and a second upper metal wire layer218(e.g., a top metal wire layer within the second BEOL metallization stack214) vertically separated by one or more metal wires206band metal vias208b. In some embodiments, the bond pad layer216may comprise a first metal interconnect layer (e.g., a “lowest” metal wire layer within the second BEOL metallization stack214). The second upper metal wire layer218laterally extends to a position outside of a bond pad area126(e.g., to a position that is laterally offset from slotted bond pad226).

The first and second plurality of metal interconnect layers are stacked onto one another in a bond pad configuration, which has the metal wires206and metal vias208stacked vertically onto one another to provide structural stability for the overlying slotted bond pad226. The stacked metal vias208are laterally aligned between different metal vias layers. In some embodiments, the metal wires206and metal vias208may be arranged in a periodic pattern. In some embodiments, the first and/or second plurality of metal interconnect layers may have a slotted structure. In such embodiments, the metal wires206band metal vias208bwithin the second plurality of metal interconnect layers may have a plurality of column structures laterally separated from one another and vertically extending between the upper metal wire layer218and the bond pad layer216. In other embodiments, the first and/or second plurality of metal interconnect layers may have metal wires with a solid structure. In such embodiments, the metal wires206bbetween the upper metal wire layer218and the bond pad layer216may comprise a solid structure laterally extending between a plurality of metal vias208bon a same metal via layer. In some embodiments, the first upper metal wire layer210and the second upper metal wire layer218extend laterally past the other plurality of metal interconnect layers in the bond pad configuration.

In some embodiments, the first ILD layer202and the second ILD layer212may comprise one or more of a low-k dielectric (i.e., a dielectric with a dielectric constant less than about 3.9), an ultra low-k dielectric, or an oxide. In some embodiments, the first and second plurality of metal interconnect layers may comprise as aluminum, copper, tungsten, or some other metal.

A redistribution structure220configured to provide an electrical connection between the first BEOL metallization stack204and the second BEOL metallization stack214is located at a position that is laterally offset from the bond pad area126(e.g., a position that is laterally offset from slotted bond pad226). The redistribution structure220comprises a first redistribution layer220aand a second redistribution layer220b. The first redistribution layer220aabuts the first upper metal wire layer210at a position laterally outside of a bond pad area126. The second redistribution layer220babuts the second upper metal wire layer218at a position laterally outside of a bond pad area126. In some embodiments, the first redistribution layer220aand the second redistribution layer220bhave concave surfaces that meet to form a bubble222at an interface between the stacked integrated chip die.

A recess232is arranged in a back-side of the second semiconductor substrate224. A buffer layer228is disposed along interior surfaces of the recess232. In some embodiments, the buffer layer228is confined to the recess232. In other embodiments, the buffer layer228may extend outward from the recess232. In some embodiments, the buffer layer228may comprise a single or multi-layer dielectric film including an oxide (e.g., silicon dioxide), a nitride (e.g., silicon nitride), and/or a high k dielectric (i.e., having a dielectric constant greater than about 3.9).

A slotted bond pad226is disposed within the recess232at a position overlying the buffer layer228. The slotted bond pad226comprises protrusions226bvertically extending outward from a base region226a, through the buffer layer228, to the bond pad layer216. In various embodiments, the slotted bond pad226may comprise a conductive material, such as copper and/or aluminum, for example. A dielectric layer230is arranged within the recess232at a location over the slotted bond pad226. In some embodiments, the dielectric layer230may comprise an oxide, such as silicon dioxide. An opening234vertically extends through the dielectric layer230to expose an upper surface of the slotted bond pad226.

FIG. 2Billustrates a top-view236of some embodiments of the stacked integrated chip200shown along line A-A′ ofFIG. 2A.

As shown in top-view236, the second upper metal wire layer218may comprise a solid bond pad configuration having a metal plate218awithin the bond pad area126underlying the slotted bond pad (e.g., element226ofFIG. 2A). Extensions218bprotrude outward from the metal plate218ato a redistribution landing area218cconfigured to make contact with a plurality of redistribution structures220. In some embodiments, the metal plate218aand the redistribution landing area218ccontinuously extend in a first direction238along multiple extensions218bextending along a second direction240and separated from one another in the first direction238.

It will be appreciated that top-view236is a non-limiting example of the second upper metal wire layer218for a solid bond pad configuration. In other embodiments, the second upper metal wire layer218may have an alternative structure, such as for example a non-solid structure for a slotted bond pad configuration.

FIG. 3illustrates some alternative embodiments of a stacked integrated chip300having a back-side bond pad.

The stacked integrated chip300comprises a first integrated chip die102, and a second integrated chip die302vertically stacked onto the first integrated chip die102. The first integrated chip die102comprises a first BEOL metallization stack204having a first upper metal wire layer210that horizontally extends to a position that is laterally offset from a slotted bond pad226. The second integrated chip die302comprises a second BEOL metallization stack304comprising an intermediate metal interconnect layer306vertically arranged between a bond pad layer216(that abuts the slotted bond pad226) and a second upper metal wire layer218. The intermediate metal interconnect layer306horizontally extends to a position laterally offset from the slotted bond pad226.

A redistribution structure220forms an electrical connection extending between the first upper metal wire layer210and the intermediate metal interconnect layer306at a position that is laterally offset from the slotted bond pad226. The redistribution structure220comprises a first redistribution layer220aabutting the first upper metal wire layer210, and a second redistribution layer220bconnected to the intermediate metal interconnect layer306by way of one or more connecting metal interconnect layers308.

FIG. 4illustrates some alternative embodiments of a stacked integrated chip400having a back-side bond pad.

The stacked integrated chip400comprises a first integrated chip die402, and a second integrated chip die302vertically stacked onto the first integrated chip die402. The first integrated chip die402comprises a first BEOL metallization stack404having a first intermediate metal interconnect layer406vertically arranged between a first semiconductor substrate104and a first upper metal layer210. The first intermediate metal interconnect layer406horizontally extends to a position that is laterally offset from slotted bond pad226. The second integrated chip die302comprises a second BEOL metallization stack304comprising a second intermediate metal interconnect layer306vertically arranged between a bond pad layer216and a second upper metal wire layer218. The second intermediate metal interconnect layer306horizontally extends to a position that is laterally offset from the slotted bond pad226.

A redistribution structure220forms an electrical connection extending between first intermediate metal interconnect layer406and the second intermediate metal interconnect layer306at a position that is laterally offset from the slotted bond pad226. The redistribution structure220comprises a first redistribution layer220aconnected to the first intermediate metal interconnect layer406by way of one or more first connecting metal interconnect layers408, and a second redistribution layer220bconnected to the second intermediate metal interconnect layer306by way of one or more second connecting metal interconnect layers308.

FIG. 5illustrates some alternative embodiments of a stacked integrated chip500having a back-side bond pad.

The stacked integrated chip500comprises a first integrated chip die402, and a second integrated chip die502vertically stacked onto the first integrated chip die402. The second integrated chip die502has an upper metal wire layer504comprising a slotted structure. The slotted structure comprises a plurality of segments504a-504nthat are laterally separated from one another. The plurality of segments504a-504nare respectively connected to adjacent metal vias208, which couple one or more of the plurality of segments504a-504nto a second intermediate metal interconnect layer306coupled to a redistribution structure220.

FIG. 6illustrates a cross-sectional view of some alternative embodiments of a stacked integrated chip600having a back-side bond pad.

The stacked integrated chip600comprises a first integrated chip die602, and a second integrated chip die302vertically stacked onto the first integrated chip die602. The second integrated chip die302has a second plurality of metal interconnect layers stacked onto one another in a bond pad configuration (e.g., in a slotted or solid pad configuration), which has the metal wires and metal vias stacked vertically onto one another to provide structural stability for an overlying slotted bond pad226. The first integrated chip die602comprises a plurality of metal wire layers604and metal via layers606configured to provide routing for integrated circuit logic elements. The plurality of metal wire layers604and metal via layers606are not arranged in a bond pad configuration. For example, the metal via layers606(e.g., a first via layer and an overlying second via layer) are not aligned in a lateral direction within a bond pad area126underlying the slotted bond pad226.

FIG. 7illustrates some additional embodiments of a back side illumination (BSI) image sensor700having a back-side bond pad.

The BSI image sensor700comprises a first integrated chip die102and a second integrated chip die702, which is vertically stacked onto the first integrated chip die102. The second integrated chip die702comprises a second semiconductor substrate704and an isolation region716. The second semiconductor substrate704and the isolation region716both abut an upper surface of the second ILD layer212, and the isolation region716extends vertically therefrom into the second semiconductor substrate704. In some embodiments, the isolation region716may comprise an oxide or an implant isolation region.

A recess714is arranged within the second semiconductor substrate704. The recess714comprises substantially vertical sidewalls. A slotted bond pad226is arranged within the recess at a location overlying a buffer layer706. A dielectric layer may be disposed within the recess714over the slotted bond pad226, and a passivation layer710may be arranged over the dielectric layer708. The passivation layer710extends along an upper surface of the second semiconductor substrate704and the dielectric layer708. In various embodiments, the passivation layer710may comprise a single or multilayer dielectric film including one or more layers of oxide, nitride, and high-k dielectric. A metal connect layer712is arranged over the passivation layer710and extends into the recess714to a position in contact with a slotted bond pad226. In various embodiments, the metal connect layer712may comprise copper or aluminum.

FIG. 8illustrates a cross-sectional view of some embodiments of a back-side illuminated (BSI) image sensor800.

The BSI image sensor800includes a first integrated chip die102and a second integrated chip die802. The second integrated chip die802comprises a sensing region804and an interconnect region806. The sensing region804is configured to sense incident radiation (e.g., visible light). The interconnect region806laterally surrounds the sensing region804and comprises bond pads120that are configured to connect the BSI image sensor800to external devices. The second integrated chip die802comprises a second semiconductor substrate808having a front-side808aabutting a second ILD layer212. An array of pixel sensors818are arranged within the front-side808aof the second semiconductor substrate808in the sensing region804. The array of pixel sensors818comprises a plurality of pixel sensors820. In various embodiments, the plurality of pixel sensors820may comprise photodetectors and/or photodiodes.

A passivation layer710is arranged along a back-side808bof the second semiconductor substrate808. In some embodiments, a metal connect layer712is arranged over the passivation layer710. An array of color filters comprising a plurality of color filters810-814is buried in the passivation layer710, within the sensing region804. Typically, the plurality of color filters810-814have planar upper surfaces that are approximately co-planar with an upper surface of the passivation layer710. The plurality of color filters810-814are configured to transmit assigned colors or wavelengths of radiation to the corresponding pixel sensors820. In some embodiments, the plurality of color filters810-814include blue color filters810, red color filters812, and green color filters814. Micro-lenses816are arranged over the plurality of color filters810-814. The micro-lenses816may have centers aligned with centers of the plurality of color filters810-814. The micro-lenses816are configured to focus incident radiation towards the array of pixel sensors818and/or the plurality of color filters810-814. In some embodiments, the micro-lenses816have convex upper surfaces.

FIG. 9illustrates a flow diagram of some embodiments of a method900of a forming a stacked integrated chip having a back-side bond pad.

At902, a first integrated chip die is formed having a first back-end-of-the-line (BEOL) metallization stack arranged within a first ILD layer overlying a first semiconductor substrate. In some embodiments, the first integrated chip die may be formed according to acts904-910.

At904, a plurality of semiconductor devices are formed within the first semiconductor substrate.

At906, a first plurality of metal interconnect layers are formed within the first ILD layer disposed over the first semiconductor substrate. The first plurality of metal interconnect layers comprise a first metal routing layer extending laterally beyond a bond pad area in which a bond pad is subsequently formed.

At908, a first redistribution layer is formed in contact with the first metal routing layer at a position laterally offset from the bond pad area.

At910, a first planarization process is performed to form a first planar interface comprising the first ILD layer and the first redistribution layer.

At912, a second integrated chip die is formed having a second BEOL metallization stack arranged within a second ILD layer overlying a second semiconductor substrate. In some embodiments, the second integrated chip die may be formed according to acts914-920.

At914, an isolation region is formed within the second semiconductor substrate.

At916, a second first plurality of metal interconnect layers are formed within the second ILD layer disposed over the second semiconductor substrate. The second first plurality of metal interconnect layers comprise a bond pad layer and a second metal routing layer extending laterally beyond the bond pad area.

At918, a second redistribution layer is formed in contact with the second metal routing layer at a position laterally offset from the bond pad layer.

At920, a second planarization process is performed to form a second planar interface comprising the second ILD layer and the second redistribution layer.

At922, the first integrated chip die is bonded to the second integrated chip die in a face to face (F2F) configuration, so that the first and second redistribution layers abut one another at an interface comprising the first and second ILD layers.

At924, a recess is formed within the second semiconductor substrate. The recess extends through a portion of the second semiconductor substrate.

At926, a bond pad is formed within the recess. The bond pad vertically extends to the bond pad connection layer within the second BEOL metallization stack. In some embodiments, the bond pad may comprise a slotted bond pad.

At928, a dielectric layer is formed within the recess at a position overlying the slotted bond pad.

At930, a passivation layer is formed over the dielectric layer. The passivation layer has an opening that vertically extends through the passivation layer to the underlying bond pad.

At932, a metal connect layer is formed onto the passivation layer and within the opening.

FIGS. 10A-17illustrate some embodiments of cross-sectional views showing a method of a forming a stacked integrated chip having a back-side bond pad. AlthoughFIGS. 10A-17are described in relation to method900, it will be appreciated that the structures disclosed inFIGS. 10A-17are not limited to such a method, but instead may stand alone as structures independent of the method.

FIGS. 10A-10Cillustrate some embodiments of cross-sectional views,1000a-1000c, of an integrated chip corresponding to act902.

As shown in cross-sectional view1000a, a plurality of semiconductor devices are formed within a device region105of a first semiconductor substrate104. The first semiconductor substrate104may comprise any type of semiconductor body (e.g., silicon/CMOS bulk, SiGe, SOI, etc.) such as a semiconductor wafer or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers formed thereon and/or otherwise associated therewith. The semiconductor devices may comprise active (e.g., MOSFETs) and/or passive devices (e.g., capacitor, inductor, resistor, etc.)

As shown in cross-sectional view1000b, a first plurality of metal interconnect layers1002are formed within a first ILD layer202disposed over the first semiconductor substrate104. The first plurality of metal interconnect layers1002may be formed by etching the first ILD layer202to form openings. The openings are then filled with a conductive material (e.g., tungsten, copper, aluminum, etc.) to form a metal wire206and/or a metal via208. In some embodiments, the first plurality of metal interconnect layers1002may be disposed in a bond pad configuration.

As shown in cross-sectional view1000c, a first metal routing layer1004is formed extending outward from a first BEOL metallization stack204to a position laterally offset from a bonding area in which a bond pad is subsequently formed. The first metal routing layer1004may be formed by etching the first ILD layer202to form an opening, which is subsequently filled with a conductive material (e.g., copper, aluminum, etc.).

A first redistribution layer220ais formed over the first metal routing layer1004. The first redistribution layer220amay be formed by etching the first ILD layer202to form an opening that is laterally offset from a bond pad area in which a bond pad is subsequently formed. The opening is subsequently filled with a conductive material (e.g., copper, aluminum, etc.). A first planarization process is then performed to form a first planar interface1006comprising the first ILD layer202and the first redistribution layer220a. In some embodiments, the first planarization process may cause an upper surface of the first redistribution layer220ato dish, giving the upper surface a concave curvature.

FIGS. 11A-11Cillustrate some embodiments of cross-sectional views,1100a-1100c, of an integrated chip corresponding to act910.

As shown in cross-sectional view1100a, an isolation region1102is formed within a second semiconductor substrate224. The isolation region1102is arranged within a front-side224aof the second semiconductor substrate224. In some embodiments, the isolation region1102is formed by way of a thermal oxidation process. The second semiconductor substrate224may comprise any type of semiconductor body (e.g., silicon/CMOS bulk, SiGe, SOI, etc.) such as a semiconductor wafer or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers formed thereon and/or otherwise associated therewith.

As shown in cross-sectional view1100b, a second plurality of metal interconnect layers1104are formed within a second ILD layer212disposed over the first semiconductor substrate. The second plurality of metal interconnect layers1104may be formed by etching the second ILD layer212to form openings. The openings are then filled with a conductive material (e.g., tungsten, copper, aluminum, etc.) to form a metal wire206and/or a metal via208. In some embodiments, the second plurality of metal interconnect layers1104may be disposed in a bond pad configuration.

As shown in cross-sectional view1100c, a second metal routing layer1106is formed extending outward from the second BEOL metallization stack214to a position laterally offset from the bonding area in which a bond pad is subsequently formed. The second metal routing layer1106may be formed by etching the second ILD layer212to form an opening. The opening is then filled with a conductive material (e.g., copper, aluminum, etc).

A second redistribution layer220bis formed over the second metal routing layer1106. The second redistribution layer220bmay be formed by etching the second ILD layer212to form an opening that is laterally offset from the bond pad area. The opening is subsequently filled with a conductive material (e.g., copper, aluminum, etc.). A second planarization process is then performed to form a second planar interface1108comprising the second ILD layer212and the second redistribution layer220b. In some embodiments, the second planarization process may cause an upper surface of the second redistribution layer220bto dish, giving the upper surface a concave curvature.

FIG. 12illustrates some embodiments of a cross-sectional view1200of an integrated chip corresponding to act922.

As shown in cross-sectional view1200, the first integrated chip die102is bonded to the second integrated chip die201in a face-to-face (F2F) configuration. In some embodiments, the bonding may comprise bump-less copper to copper bonding at the redistribution layers,220aand220b. In other embodiments, the bonding may comprise fusion bonding. In some embodiments, a bubble222may form between the first redistribution layer220aand the second redistribution layer220bdue to dishing caused by the first and second planarization processes. The bubble222forms at a location that is laterally offset from a bond pad area in which a bond pad is subsequently formed. In some embodiments, the second semiconductor substrate224may be thinned after bonding.

FIG. 13illustrates some embodiments of a cross-sectional view1300of an integrated chip corresponding to act924.

As shown in cross-sectional view1300, a back-side224bof the second semiconductor substrate224is selectively exposed to a first etchant1302. The first etchant1302is configured to remove a portion of the second semiconductor substrate224. In some embodiments, due to over etching, the isolation region1102may be eroded by the first etchant1302. The first etchant1302forms a recess232in the second semiconductor substrate224overlying the bond pad layer216and vertically extending to the isolation region1102. In some embodiments, the recess232extends laterally around an array of pixel sensors (not shown). In some embodiments, the second semiconductor substrate224may be selectively masked prior to exposure to the first etchant1302by a masking layer1304(e.g., a photoresist layer). In various embodiments, the first etchant1302may comprise a dry etchant have an etching chemistry comprising a fluorine species (e.g., CF4, CHF3, C4F8, etc.) or a wet etchant (e.g., hydroflouric acid (HF)).

FIGS. 14A-14Billustrate some embodiments of cross-sectional views,1400aand1400b, of an integrated chip corresponding to act926.

As shown in cross-sectional view1400a, a buffer layer1402is formed over the second semiconductor substrate224and lining the recess232. The buffer layer1402may be formed using vapor deposition (e.g., chemical vapor deposition (CVD)), thermal oxidation, spin coating, or any other suitable deposition technique. In some embodiments, the buffer layer1402may comprise an oxide, such as silicon dioxide.

The workpiece is subsequently exposed to a second etchant1404. The second etchant1404removes portions of the buffer layer1402, the isolation region716, and the second ILD layer212, resulting in trenches1408overlying the bond pad layer216. In some embodiments, the workpiece may be selectively masked prior to exposure to the second etchant1404by a masking layer1406(e.g., a photoresist layer). In various embodiments, the second etchant1404may comprise a dry etchant have an etching chemistry comprising a fluorine species (e.g., CF4, CHF3, C4F8, etc.) or a wet etchant (e.g., hydroflouric acid (HF)).

As shown in cross-sectional view1400b, a slotted bond pad226is formed over the buffer layer1402. The slotted bond pad226comprises protrusions226bextending within the trenches1408to a position in electrical contact with the underlying bond pad layer216. In some embodiments, the slotted bond pad226may be formed by forming a pad layer over the buffer layer1402. The pad layer may comprise a metal, such as aluminum copper, copper, aluminum, or some other metal. The pad layer is subsequently etched to form the slotted bond pad226. The etchant may further form pad openings124extending vertically into an upper surface of the pad at a location overlying the protrusions226b.

FIG. 15illustrates some embodiments of a cross-sectional view1500of an integrated chip corresponding to act928.

As shown in cross-sectional view1500, a dielectric layer1502is formed within the recess232at a position overlying the slotted bond pad226and the buffer layer228. In various embodiments, the dielectric layer1502may be formed using vapor deposition, thermal oxidation, spin coating, or any other suitable deposition technique. In various embodiments, the dielectric layer1502may comprise an oxide, such as silicon dioxide, or some other dielectric. In some embodiments, a chemical mechanical polishing (CMP) process may be performed after deposition of the dielectric layer230.

FIG. 16illustrates some embodiments of a cross-sectional view1700of an integrated chip corresponding to act930.

As shown in cross-sectional view1600, a passivation layer710is formed over the second semiconductor substrate224and the dielectric layer230. The passivation layer710may comprise a single or multilayer dielectric film having one or more layers of oxide, nitride, and/or a high-k dielectric. The one or more layers may be formed by sequentially depositing the layers using vapor deposition, thermal oxidation, spin coating, or any other suitable deposition technique. After deposition, the passivation layer710and the dielectric layer230may be subsequently etched to form an opening1602that extends to the underlying slotted bond pad226.

FIG. 17illustrates some embodiments of a cross-sectional view1700of an integrated chip corresponding to act932.

As shown in cross-sectional view1700, a metal connect layer712is formed over the passivation layer710and within the opening1602. In various embodiments, the metal connect layer712may comprise a metal, such as copper or aluminum copper. In various embodiments, the metal connect layer712may be formed using, for example, vapor deposition, thermal oxidation, spin coating, or any other suitable deposition technique.

Therefore, the present disclosure relates to a multi-dimensional integrated chip having a redistribution layer vertically extending between integrated chip die, which is laterally offset from a back-side bond pad.

In some embodiments, the present disclosure relates to a multi-dimensional integrated chip. The multi-dimensional integrated chip comprises a first integrated chip die comprising a first plurality of metal interconnect layers arranged within a first inter-level dielectric (ILD) layer disposed onto a front-side of a first semiconductor substrate, and a second integrated chip die comprising a second plurality of metal interconnect layers arranged within a second ILD layer disposed onto a front-side of a second semiconductor substrate, wherein the first ILD layer abuts the second ILD layer. The multi-dimensional integrated chip further comprises a bond pad disposed within a recess extending through the second semiconductor substrate, and a redistribution structure vertically extending between one of the first plurality of metal interconnect layers and one of the second plurality of metal interconnect layers at a position that is laterally offset from the bond pad.

In other embodiments, the present disclosure relates to a multi-dimensional integrated chip. The multi-dimensional integrated chip comprises a first integrated chip die comprising a first inter-level dielectric (ILD) layer disposed onto a front-side of a first semiconductor substrate and surrounding a first plurality of metal interconnect layers comprising a first metal routing layer. The multi-dimensional integrated chip further comprises a second integrated chip die comprising a second ILD layer disposed onto a front-side of a second semiconductor substrate and surrounding a second plurality of metal interconnect layers comprising a bond pad layer vertically separated by one or more metal vias or metal wires from a second metal routing layer. The multi-dimensional integrated chip further comprises a slotted bond pad disposed within a recess extending through the second semiconductor substrate and having protrusions in contact with the bond pad layer. The multi-dimensional integrated chip further comprises a redistribution structure vertically extending between the first metal routing layer and the second metal routing layer at a position that is laterally offset from the slotted bond pad, wherein a bond pad area extending below the slotted bond pad is devoid of redistribution structures extending between the first metal routing layer and the second metal routing layer.

In yet other embodiments, the present disclosure relates to a method of forming a multi-dimensional integrated chip. The method comprises forming a first integrated chip die having a first plurality of metal interconnect layers arranged within a first inter-level dielectric (ILD) layer disposed on a front-side of a first semiconductor substrate, and forming a second integrated chip die having a second plurality of metal interconnect layers arranged within a second ILD layer disposed on a front-side of a second semiconductor substrate. The method further comprises bonding the first integrated chip die to the second integrated chip die so that a first redistribution layer coupled to the first plurality of metal interconnect layers abuts a second redistribution layer coupled to the second plurality of metal interconnect layers at an interface between the first ILD layer and the second ILD layer. The method further comprises forming a recess within a back-side of the second semiconductor substrate, and forming a slotted bond pad within the recess, wherein the slotted bond pad electrically contacts the second plurality of metal interconnect layers.