Transistor in a wiring interlayer insulating film

A semiconductor device includes a substrate; a first insulating layer provided on the substrate; a conductive layer buried in the first insulating layer; a semiconductor pillar including a lower diffusion layer provided immediately above the conductive layer, the lower diffusion layer being electrically connected to the conductive layer, a semiconductor layer on the lower diffusion layer, and an upper diffusion layer on the semiconductor layer; a gate insulating film provided on a peripheral side surface of the semiconductor layer; a gate electrode provided on the gate insulating film; and a second insulating layer provided such that the gate electrode and a circumference of the semiconductor pillar are buried in the second insulating layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device and a fabrication method of the same.

2. Description of Related Art

Various MOS transistors have been proposed for high performance MOS transistors, but the current mainstream is a so-called planar transistor including a gate electrode provided on a silicon substrate through a gate insulating film, a source diffusion layer and a drain diffusion layer provided on both sides thereof.

When such a planar transistor is used, an integration density thereof is restricted by the substrate area and the occupied area for element isolation. In addition, an increase in the packaging density of transistors causes an increase in the wiring complexity and the occupied area for wiring, and thus a further increase in the packaging density becomes more difficult. Moreover, for cost reduction, an increase in the substrate diameter is attempted to increase the number of chips to be obtained by one substrate, but further increase in the diameter of a silicon substrate becomes more difficult.

Further, the silicon substrate is of a circular planar shape in the nature of the fabrication method, which has a problem in that when an ordinary rectangular semiconductor chip is fabricated, the circular peripheral edge of the substrate remains unused.

In contrast to such a planar transistor, there is proposed a so-called vertical transistor without a need to use a silicon substrate. For example, Japanese Patent Laid-Open No. 7-297406 discloses a vertical thin film semiconductor device in which a drain electrode, a silicon layer, and a source electrode are laminated in a direction perpendicular to a substrate surface, wherein the drain electrode is formed in contact with the substrate surface, and the drain electrode occupies a wider area than the source electrode.

SUMMARY

In one embodiment, there is provided a semiconductor device including:

a substrate;

a first insulating layer provided on the substrate;

a conductive layer buried in the first insulating layer;

a semiconductor pillar including a lower diffusion layer provided immediately above the conductive layer, the lower diffusion layer being electrically connected to the conductive layer, a semiconductor layer on the lower diffusion layer, and an upper diffusion layer on the semiconductor layer;

a gate insulating film provided on a peripheral side surface of the semiconductor layer;

a gate electrode provided on the gate insulating film; and

a second insulating layer provided such that the gate electrode and a circumference of the semiconductor pillar are buried in the second insulating layer.

In another embodiment, there is provided the semiconductor device, wherein the gate electrode is provided on the gate insulating film such that the gate electrode surrounds a circumference of the semiconductor layer.

In another embodiment, there is provided any one of the semiconductor devices, wherein the lower diffusion layer is made of an impurity containing single crystal silicon layer on a polysilicon layer.

In another embodiment, there is provided any one of the semiconductor devices, further including a silicon nitride film covering an upper surface of the first insulating layer, wherein the gate electrode and the second insulating layer are provided on the silicon nitride film.

In another embodiment, there is provided any one of the semiconductor devices, wherein the substrate is an insulating substrate.

In another embodiment, there is provided any one of the semiconductor devices, wherein the gate electrode includes an extension portion extending in a substrate plane direction; and

the semiconductor device further includes:a third insulating layer provided on the second insulating layer;a first conductive plug passing through the third insulating layer, the first conductive plug being connected to the upper diffusion layer;a second conductive plug passing through the third insulating layer and the second insulating layer, the second conductive plug being connected to the extension portion of the gate electrode;a conductive layer provided on the third insulating layer, the conductive layer being connected to the first conductive plug; anda conductive layer provided on the third insulating layer, the conductive layer being connected to the second conductive plug.

In another embodiment, there is provided any one of the semiconductor devices further including:

a third insulating layer provided on the second insulating layer;

a fourth insulating layer provided on the third insulating layer;

a conductive layer buried in the fourth insulating layer;

a semiconductor pillar including a lower diffusion layer provided immediately above the conductive layer, the lower diffusion layer being electrically connected to the conductive layer, a semiconductor layer on the lower diffusion layer, and an upper diffusion layer on the semiconductor layer;

a gate insulating film provided on a peripheral side surface of the semiconductor layer;

a gate electrode provided on the gate insulating film; and

a fifth insulating layer provided such that the gate electrode and a circumference of the semiconductor pillar are buried in the fifth insulating layer.

In another embodiment, there is provided a method of fabricating a semiconductor device including:

forming a first insulating layer on a substrate such that a conductive layer is buried in the first insulating layer;

forming a sacrificial layer on the first insulating layer;

forming a hole reaching the conductive layer in the sacrificial layer;

forming a polysilicon film on a surface containing the inside of the hole;

forming a mask film such that the hole is filled with the mask film;

removing the mask film such that a part of the mask film remains in a bottom of the hole;

removing the polysilicon film using the remaining part of the mask film as a mask to leave a part of the polysilicon film on the hole bottom;

forming a first single crystal silicon layer by single crystallizing at least an upper layer portion of the remaining polysilicon film part after the remaining mask film part is removed;

forming a lower diffusion layer by injecting an impurity into the first single crystal silicon layer;

forming a second single crystal silicon layer on the lower diffusion layer inside the hole;

forming an upper diffusion layer by injecting an impurity into a surface layer portion of the second single crystal silicon layer;

exposing a semiconductor pillar including the lower diffusion layer formed inside the hole, the semiconductor layer on the lower diffusion layer, and the upper diffusion layer on the semiconductor layer by removing the sacrificial layer;

forming a gate insulating film on the peripheral side surface of the semiconductor layer;

forming a gate electrode on the gate insulating film; and

forming a second insulating layer on the gate electrode and the semiconductor pillar.

In another embodiment, there is provided the method of fabricating a semiconductor device, further including forming a etching protection film on the first insulating layer before forming the sacrificial layer,

wherein the sacrificial layer is removed by etching using the etching protection film for protecting the first insulating layer.

In another embodiment, there is provided any one of the methods of fabricating a semiconductor device, further including injecting a conductive type impurity opposite to a conductive type of the impurity of the lower diffusion layer into the second single crystal silicon layer,

wherein the upper diffusion layer is formed by injecting the same conductive type impurity as the conductive type of the impurity of the lower diffusion layer.

In another embodiment, there is provided any one of the methods of fabricating a semiconductor device, further including:

forming a etching protection film such that the hole is filled with the etching protection film, after forming the upper diffusion layer in the hole;

removing the etching protection film such that a part of the etching protection film remains in the hole;

forming an impurity containing polysilicon film over the semiconductor pillar, after forming the gate insulating film;

forming a side wall covering a peripheral side surface of the semiconductor pillar by performing an etch back using a remaining part of the etching protection film for protecting the semiconductor pillar;

forming a conductive film on the side wall; and

forming a conductive film pattern by patterning the conductive film;

wherein the gate electrode comprises the side wall and the conductive film pattern.

The present invention can provide a semiconductor device including a field-effect transistor capable of being formed with a high integration density, and the fabrication method of the same.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Since a conventional MOS transistor, which is provided on a flat surface of a substrate, is restricted by the substrate area, the transistor is difficult to be formed thereon in highly density. In recent years, as the process temperature is lowered with a trend of a metalized gate and a shallowed diffusion layer, the difference between the transistor forming process and the wiring forming process is reduced. In view of this, the present inventor has made zealous studies and has found a transistor structure which can be formed not on a substrate surface but in a wiring interlayer insulating film.

The present invention can be effectively applied to a semiconductor device provided with an MIS field effect transistor (hereinafter referred to as a “transistor”).

The transistor in accordance with an exemplary embodiment includes a semiconductor pillar including a lower diffusion layer electrically connected to a conductive layer buried in an insulating layer, the lower diffusion layer being provided immediately thereabove, a semiconductor layer on the lower diffusion layer, and an upper diffusion layer on the semiconductor layer; a gate insulating film provided on a peripheral side surface of the semiconductor layer; and a gate electrode provided on the gate insulating film. The gate electrode and the semiconductor pillar are buried in the insulating layer.

The present exemplary embodiment can form a plurality of transistors in a plurality of insulating layers between wiring layers respectively, and thus can increase the number of transistors per unit area.

Moreover, according to the present exemplary embodiment, since the transistor components such as a source, a channel forming region, and a drain are laminated in a direction perpendicular to the substrate surface, the occupied area can be reduced and the number of transistors formed per unit area can be increased in comparison with the conventional planar transistor. Further, a perfect depletion type transistor can be easily formed.

Moreover, according to the present exemplary embodiment, since a transistor can be formed between wiring layers, an inexpensive insulating substrate can be used in stead of a relatively expensive semiconductor single crystal substrate, thereby reducing the cost. Moreover, for example, when a quartz substrate is used, the substrate can be of 1 m or larger size and can be of a rectangular shape, thereby increasing the number of chips obtained and increasing the use efficiency of the entire substrate.

Moreover, according to the present exemplary embodiment, since transistors are separated by an interlayer insulating film, a conventional element isolation process is not required, thereby reducing the cost.

Moreover, according to the present exemplary embodiment, since the gate length control can be performed by the film thickness control based on a film forming technique in stead of a control based on a conventional lithographic technique and etching technique, the gate length controllability can be increased.

FIG. 1illustrates a schematic sectional structure of an exemplary embodiment, in which two MOS transistors are respectively formed in two layers sandwiched by wiring layers.

For example, a quartz substrate can be used as a substrate1without undue restriction as long as the substrate has enough flatness and thermal resistance.

On a surface of the substrate1, there is formed a wiring layer10with enough thermal resistance; and on the wiring layer10, there is formed a semiconductor pillar with a structure in which a lower diffusion layer (source)11, a semiconductor layer (channel region)12, and an upper diffusion layer (drain)13are laminated in the height direction (direction perpendicular to the substrate surface). In addition, a gate oxide film14and a gate electrode15are formed so as to surround the semiconductor pillar; and thus a MOS transistor (hereinafter referred to as a “first transistor”) is configured in an interlayer insulating film18.

The upper diffusion layer13of the semiconductor pillar of the first transistor is connected to a wiring layer20aon the interlayer insulating film18through a contact plug16; and the gate electrode15is connected to the wiring layer20bthrough a contact plug17. It should be noted that a via plug (not shown) for connecting the lower side wiring layer10to the upper side wiring layer is formed as needed.

On the wiring layer20b, there is provided a MOS transistor (hereinafter referred to as a “second transistor”) with the same structure as that of the first transistor located thereunder. There is formed a semiconductor pillar with a structure in which a lower diffusion layer (source)21, and a semiconductor layer (channel region)22, and an upper diffusion layer (drain)23are laminated. A gate oxide film24and a gate electrode25are formed so as to surround the semiconductor pillar; and thus the second transistor is configured in an interlayer insulating film28.

The upper diffusion layer23of the semiconductor pillar of the second transistor is connected to a wiring layer30aon the interlayer insulating film28through a contact plug26; and the gate electrode25is connected to a wiring layer30bthrough a contact plug27. It should be noted that a via plug (not shown) for connecting the lower side wiring layer20bto the upper side wiring layer is formed as needed.

On the wiring layers30aand30b, there is formed an insulating protection film40. It should be noted that above the wiring layers and the insulating protection film, there may be formed another MOS transistor and a wiring layer as needed.

FIG. 2illustrates a basic plan layout view of one MOS transistor in the present exemplary embodiment.

The semiconductor pillar (laminated layers of the source, the channel region, and the drain)2forming the MOS transistor has a long pattern in the lateral direction inFIG. 2. The short side length (vertical width) is set to, for example, 100 nm or less so as to completely deplete the channel region by an electric field applied from the gate electrode15surrounding the circumference thereof. The long side length (lateral width) is set to a length required and enough to flow current necessary for circuit operation.

The semiconductor pillar2is provided on the wiring layer10such that the lower diffusion layer (source)11is in contact with the wiring layer10. On the semiconductor pillar2, there is provided the contact plug16so as to connect the upper diffusion layer (drain)13to the wiring layer20a.

The gate electrode15is extended in one of the vertical direction in the figure (direction perpendicular to the extending direction of the semiconductor pillar). On the extending region adjacent to the semiconductor pillar2, there is provided the contact plug17so as to connect the gate electrode15to the wiring layer20b. The extending direction of the gate electrode and the shape and the area of the extending region can be set appropriately, and is not limited to this figure.

Hereinafter, an exemplary embodiment of the fabrication method of the semiconductor device in accordance with the present invention will be described with reference toFIGS. 3A to 3S.FIGS. 3A to 3Sillustrate sectional structures of the individual steps corresponding to a section along the A-B line inFIG. 2.

As shown inFIG. 3A, the insulating film3made of a silicon oxide film or the like is formed on the quartz substrate1as needed, and then, the wiring layer10is formed. The wiring layer10can be formed, for example, by laminating a tungsten film10a, a titanium nitride film10b, and a titanium film10cin that order, and patterning the films through a general method.

Next, a silicon oxide film18ais formed so as to bury the wiring layer. The silicon oxide film18ais planarized by the chemical mechanical polishing (CMP) or the like and the wiring layer10is exposed. Then, a silicon nitride film18band a silicon oxide film (sacrificial oxide film)18care formed. The total size of the film thickness of the silicon nitride film18band the film thickness of the silicon oxide film18cdetermines the gate length of a transistor to be formed later. In order to give priority to a performance such as a current drive capability, the gate length needs to be as short as possible. In this case, the total size can be set to, for example, 80 nm. In order to give priority to a stability of the characteristics, the gate length needs to be long. In this case, the total size can be set to, for example, 200 nm. When the total size of the film thickness is set in this manner, the silicon nitride film18bis set to a required minimum thickness (e.g., 10 nm) enough to withstand a subsequent hydrofluoric acid etching.

As shown inFIG. 3B, a hole2ain which the semiconductor pillar2will be formed later is formed so as to expose the wiring layer10in the bottom thereof using the lithographic technique and the dry etching technique. Next, a polysilicon film11ais formed on the entire surface containing the inside of the hole by the CVD method. The film thickness of the polysilicon film11ais set to a thickness (e.g., 15 nm) not to bury the hole2a.

Next, as shown inFIG. 3C, a resist film50is formed so as to bury the entire hole2a.

Next, the resist film50is removed such that a part of the resist film remains in the bottom of the hole2a. Then, as shown inFIG. 3D, the remaining resist film is used as a mask and the polysilicon film11ais removed, for example, by the isotropic dry etching such that the polysilicon film11aremains only in the bottom of the hole. The examples of the method of leaving a part of the resist film50in the hole bottom include a method of removing the resist up to a predetermined depth in the hole by controlling the amount of light exposure using a positive resist; and a method of leaving a predetermined thickness of resist film in the hole by controlling the amount of etching through etch back by an asher process using an O2/CF4 gas or the like.

Next, the remaining resist film50is removed, and then, the polysilicon film surface is locally single crystallized using laser annealing or the like. Then, for an n-channel transistor, arsenic or phosphorus is ion-implanted as an n-type impurity; and for a p-channel transistor, boron is ion-implanted as a p-type impurity, and then, heat treatment is performed. As shown inFIG. 3E, the above process forms a single crystal silicon diffusion layer11d, a polysilicon diffusion layer11c, and a titanium silicide layer11bformed by a reaction between polysilicon and underlayer Ti. With the formation, the surface crystallinity is recovered.

Next, as shown inFIG. 3F, a silicon crystal is selectively grown, for example, by the MOCVD epitaxial method using a single crystal silicon surface in the bottom of the hole2aas nuclei. At this time, for an n-channel transistor, boron is introduced as a p-type impurity, and for a p-channel transistor, phosphorus is introduced as an n-type impurity. The semiconductor layer (channel region)12of the MOS transistor is thus formed.

Next, as shown inFIG. 3G, the upper diffusion layer13is formed in the upper surface layer part of the semiconductor layer12as follows. For an n-channel transistor, arsenic or phosphorus is ion-implanted as an n-type impurity, and for a p-channel transistor, boron is ion implanted as a p-type impurity; and then, heat treatment is performed.

Next, as shown inFIG. 3H, a silicon nitride film18dis formed so as to completely bury the hole2a. Next, as shown inFIG. 3I, the silicon nitride film on the surface outside the hole is removed, for example, by the CMP method such that the silicon nitride film18dremains only inside the hole.

Next, as shown inFIG. 3J, the silicon oxide film18cis removed, for example, by wet etching using hydrofluoric acid solution. Next, the gate oxide film14is formed on the side surface of the semiconductor pillar including the semiconductor layer12, for example, by thermal oxidation method.

Next, as shown inFIG. 3K, the impurity containing polysilicon film15ais formed, for example, by the CVD method. Then, as shown inFIG. 3L, etch back is performed to remove the polysilicon film15asuch that the polysilicon film remains on the side surface of the semiconductor pillar. As a result, a polysilicon side wall made of the polysilicon film15aremaining on the side surface of the semiconductor pillar is formed. The side wall is later used as part of the gate electrode. The use of the side wall can increase the controllability of the threshold (Vth) and can maintain the reliability of the gate oxide film.

Next, as shown inFIG. 3M, the tungsten film15bis deposited, for example, by the CVD method. Then, as shown inFIG. 3N, the gate electrode15made of the tungsten film15band the polysilicon side wall15ais formed by patterning the tungsten film15busing the lithographic technique and the etching technique. In order to suppress the reaction between the tungsten film15band the polysilicon side wall15a, a tungsten nitride film may be provided therebetween.

Next, as shown inFIG. 3O, a silicon oxide film18eis formed, for example, by the CVD method so as to bury the gate electrode15.

Next, as shown inFIG. 3P, polishing by the CMP method is performed for planarization until the gate electrode15above the upper diffusion layer13is removed and the silicon nitride film18dis exposed.

Next, a silicon oxide film18fis formed on the silicon oxide film18e, for example, by the CVD method so as to cover the exposed gate electrode15and the silicon nitride film18d. Next, as shown inFIG. 3Q, a contact hole16areaching the upper diffusion layer13and a contact hole17areaching the gate electrode are formed by the lithographic technique and the dry etching technique. The silicon nitride film18dcan be used as the etching stopper for forming the contact hole16a.

Next, for example, a titanium film and a titanium nitride film are formed in that order on the surface including the inside of the holes, and then, a tungsten film is formed so as to bury the holes. Then, the conductive films on the surface outside the hole are removed by the CMP method. By doing so, as shown inFIG. 3R, the contact plug16connected to the upper diffusion layer13and the contact plug17connected to the gate electrode15are formed.

Next, as shown inFIG. 3S, a laminate film made of a titanium nitride film, an aluminum film and a titanium nitride film is formed, for example, by sputtering technique. Then, the wiring layers20aand20bare formed by patterning using the lithographic technique and the dry etching technique.

The above process forms a vertical MOS transistor in an interlayer film between the lower side wiring layer10and the upper side wiring layers20aand20b.

According to the present exemplary embodiment, another wiring layer is formed instead of the wiring layers20aand20bby the same method as the method of forming the wiring layer10; another vertical MOS transistor is formed on the upper layer portion thereof by the same method as the method of forming the above described vertical MOS transistor; and thereby a structure having a plurality of transistors formed in upper and lower different layers can be formed as shown inFIG. 1. Further, though not illustrated, repeating the same process can produce a structure having a three or more insulating layers between wiring layers, each of the insulating layers including a vertical MOS transistor.

According to the present exemplary embodiment, the foregoing description has been given to an example in which a semiconductor single crystal substrate is not used, but the semiconductor single crystal substrate may be used to form a general planar MOS transistor on the substrate and to form the above described vertical MOS transistor on the upper side of the planar MOS transistor.