Thin substrate PoP structure

A PoP (package-on-package) package includes a bottom package with a substrate encapsulated in an encapsulant with a die coupled to the top of the substrate. At least a portion of the die is exposed above the encapsulant on the bottom package substrate. A top package includes a substrate with encapsulant on both the frontside and the backside of the substrate. The backside of the top package substrate is coupled to the topside of the bottom package substrate with at least part of the die being located in a recess in the encapsulant on the backside of the top package substrate.

BACKGROUND

1. Field of the Invention

The present invention relates to semiconductor packaging and methods for packaging semiconductor devices. More particularly, the invention relates to a PoP (package-on-package) using thin or coreless substrates.

2. Description of Related Art

Package-on-package (“PoP”) technology has become increasingly popular as the demand for lower cost, higher performance, increased integrated circuit density, and increased package density continues in the semiconductor industry. As the push for smaller and smaller packages increases, the integration of die and package (e.g., “pre-stacking” or the integration of system on a chip (“SoC”) technology with memory technology) allows for thinner packages. Such pre-stacking has become a critical component for thin and fine pitch PoP packages.

A problem that arises with thin and fine pitch PoP packages is the potential for warping as the pitch is reduced between terminals (e.g., balls such as solder balls) on either the top package or the bottom package in the PoP package. Warping may be caused by the difference in thermal characteristics of materials used in the package (e.g., the substrate and an encapsulant applied to the substrate). The top package may especially have warping problems due to the top package not being attached to any external component that inhibits warping. For example, the bottom package may be attached to a printed circuit board that helps to inhibit warping in the bottom package.

The warping problem in the top package may be further increased with the use of a thin or coreless substrate in the top package. The thin or coreless substrate may have less mechanical strength to resist the effects caused by differences in thermal characteristics between the substrate and the applied encapsulant. The warping problem may lead to failure or reduced performance of the PoP package and/or problems in reliability of devices utilizing the PoP package.

SUMMARY

In certain embodiments, an assembly system for a PoP package includes a bottom package and a top package. The bottom package may include a substrate coupled to a die. The substrate and the die may be encapsulated in an encapsulant with at least part of the die being exposed above the encapsulant. At least a portion of the die is exposed above the encapsulant on the bottom package substrate. The top package may include a substrate with encapsulant on both the frontside (top) and the backside (bottom) of the substrate. Because of the encapsulant on both sides of the top package, thermal properties in the top package may be substantially balanced. Balancing the thermal properties may balance thermal stresses on the top package and reduce or inhibit warping in the top package.

In certain embodiments, the encapsulant on the backside of the top package substrate includes a recess. In some embodiments, at least part of the substrate is exposed in the recess. In other embodiments, the substrate is substantially covered in the recess. In certain embodiments, when the bottom package and the top package are coupled to form a PoP package, the recess in the top package accommodates the die coupled to the substrate in the bottom package (e.g., at least part of the die is located in the recess). In some embodiments, terminals (e.g., solder balls) on the top of the bottom package substrate are coupled to terminals on the bottom of the top package substrate when the bottom package is coupled to the top package.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1depicts a cross-sectional representation of an example of top and bottom packages for a PoP (“package-on-package”) package before assembly (e.g., a PoP package system). PoP package assembly system100includes bottom package102and top104. Bottom package102includes substrate106with encapsulant108at least partially covering the substrate. Die110may be coupled to substrate106using terminals112(e.g., solder balls) and be at least partially covered in encapsulant108. Terminals114(e.g., solder balls) may be coupled to an upper (top) surface of substrate106. Terminals115(e.g., solder balls) may be coupled to a lower (bottom) surface of substrate106.

Top package104includes substrate116with encapsulant118covering an upper (top) surface of the substrate. Terminals120(e.g., solder balls) are coupled to a lower (bottom) surface of substrate116. As shown inFIG. 1, top package104may undergo warping because of the different thermal characteristics (e.g., coefficient of thermal expansion (“CTE”) and/or shrinkage rate) between substrate116, encapsulant118, and terminals120. Warping may cause problems such as, but not limited to, loss of connection between terminals114in bottom package102and terminals120in top package104after assembly of the PoP package. The warping problem in top package104may be increased if substrate116is a relatively thin substrate (e.g., less than about 400 μm in thickness) and/or the substrate is a coreless substrate (e.g., a substrate made of only dielectric polymer and copper traces).

FIG. 2depicts a cross-sectional representation of an embodiment of PoP (“package-on-package”) package assembly system100′. System100′ includes bottom package102′ and top package104′. In certain embodiments, bottom package102′ includes substrate106. Substrate106may be, for example, a base substrate for a package or a package substrate. In certain embodiments, substrate106is a coreless substrate. In some embodiments, substrate106is a thin substrate with a core. Substrate106may have a thickness of less than about 400 μm. In some embodiments, the thickness of substrate106is less than about 200 μm or less than about 100 μm.

Die110may be coupled to an upper (top, topside, or frontside) surface of substrate106using terminals112and/or other mechanisms for coupling a die to a substrate. Die110may be, for example, a semiconductor chip, an integrated circuit die, or a flip chip die. In certain embodiments, die110is a system on a chip (“SoC”). In certain embodiments, terminals114are coupled to the top of substrate106. Terminals115may be coupled to a lower (bottom, bottomside, or backside) surface of substrate106. Terminals112,114, and/or115may include, but not be limited to, balls, pillars, or columns made from, for example, solder or copper.

After die110and terminals114are coupled to substrate106, the top (e.g., upper surface) of the substrate may be at least partially covered by encapsulant108. Encapsulant108may be, for example, a polymer or a mold compound. In certain embodiments, encapsulant108has selected properties (e.g., selected thermal properties). For example, in some embodiments, encapsulant108has a glass transition temperature (Tg) of between about 115° C. and about 190° C. In some embodiments, encapsulant108has a coefficient of thermal expansion (CTE) of between about 10 ppm/° C. and about 38 ppm/° C. below the glass transition temperature and between about 40 ppm/° C. and about 145 ppm/° C. above the glass transition temperature. In some embodiments, encapsulant108has a modulus between about 570 kgf/mm2and about 2400 kgf/mm2at 25° C. or between about 8 kgf/mm2and about 70 kgf/mm2at about 260° C. In certain embodiments, encapsulant108has thermal properties that are as close to the thermal properties of substrate106as possible.

In certain embodiments, die110is at least partially covered in encapsulant108and at least a portion of the die is exposed above the encapsulant, as shown inFIG. 2. In certain embodiments, a mold chase is used to form encapsulant108over substrate106.FIG. 3depicts a side-view representation of mold chase500being used during application of encapsulant108over substrate106. As shown inFIG. 3, mold chase500has a shape that, when the mold chase is placed against die110, inhibits encapsulant108from covering the top surface of the die. In some embodiments, a protective film is placed over the top surface of die110during the encapsulation process. The protective film may protect die110from damage when the die contacts mold chase500. The protective film may be, for example, a polymer film.

In certain embodiments, as shown inFIG. 2, terminals114are at least partially covered by encapsulant108. For example, at least a portion of terminals114is exposed above encapsulant108, as shown inFIG. 2. In some embodiments, terminals114are first covered by encapsulant108when the encapsulant is applied to substrate106and then a portion of the encapsulant is removed to expose portions of the terminals. For example, terminals114may be exposed in a cavity, as shown inFIG. 2, using techniques such as, but not limited to, laser drilling/ablation to expose portions of the terminals. In other embodiments, portions of terminals114are exposed using flat-type processing such as, but not limited to, mechanical grinding/cutting processing. In some embodiments, a film assistance mold (FAM) process is used to form encapsulant108in a mold shape that exposes portions of terminals114(e.g., the mold shape has cavities for the terminals as shown inFIG. 2).

In certain embodiments, terminals114have a height above substrate106, represented by dashed line122B, that is higher than a height of encapsulant108above the substrate, represented by dashed line122A. Terminals114may have a higher height than encapsulant108to ensure connection between the terminals in bottom package102′ and terminals (e.g., terminals120) in top package104′.

In certain embodiments, top package104′ includes substrate116. Substrate116may be, for example, a base substrate for a package or a package substrate. In certain embodiments, substrate116is a coreless substrate. In some embodiments, substrate116is a thin substrate with a core. Substrate116may have a thickness of less than about 400 μm. In some embodiments, the thickness of substrate116is less than about 200 μm or less than about 100 μm.

In certain embodiments, terminals120are coupled to a lower (bottom, bottomside, or backside) surface of substrate116. Terminals120may include, but not be limited to, balls, pillars, or columns made from, for example, solder or copper. Terminals120may be aligned to connect with terminals114in bottom package102′.

An upper (top, topside, or frontside) surface of substrate116may be at least partially covered by encapsulant118. Encapsulant118may be the same material as encapsulant108and/or have similar properties to encapsulant108. In some embodiments, encapsulant118substantially covers the entire top of substrate116, as shown inFIG. 2.

In certain embodiments, as shown inFIG. 2, the bottom of top package104′ is at least partially covered by encapsulant124. Encapsulant124may be the same material and/or have similar properties as encapsulant108and/or encapsulant118. In certain embodiments, recess126is formed in encapsulant124. In some embodiments, recess126is formed during the encapsulation/molding process (e.g., using a mold chase cavity designed with the recess). In other embodiments, recess126is formed after the encapsulation/molding process. For example, recess126may be formed using mechanical grinding/cutting processes or laser drilling/ablation processes.

In certain embodiments, as shown inFIG. 2, recess126is formed with at least some encapsulation124left in the recess (e.g., encapsulant124substantially covers or encloses substrate116in the recess and the substrate is not exposed in the recess). In some embodiments, the top package substrate is exposed in the recess.FIG. 4depicts a cross-sectional representation of an embodiment of PoP (“package-on-package”) package assembly system100″. As shown inFIG. 4, top package104″ includes encapsulant124with recess126′. Substrate116is at least partially exposed in recess126′. In certain embodiments, substrate116is substantially exposed in recess126′.FIG. 5depicts a bottom-view representation of top package104″ with substrate116exposed in recess126′.

In certain embodiments, recess126(or recess126′) is sized to accommodate the exposed portion of die110when top package104′ (or top package104″) is coupled to bottom package102′.FIG. 6depicts a cross-sectional representation of an embodiment of PoP package600formed when bottom package102′ is coupled to top package104′. As shown inFIG. 6, accommodating die110in recess126(or recess126′) reduces the overall thickness of PoP package600.

In certain embodiments, as shown inFIGS. 2 and 4, at least some parts of terminals120are exposed above encapsulant124. Terminals120may be exposed to allow interconnection between terminals120and terminals114when top package104′ (or top package104″) is coupled to the bottom package, as shown inFIG. 6.

In some embodiments, terminals120are first covered by encapsulant124when the encapsulant is applied to substrate116and then a portion of the encapsulant is removed to expose portions of the terminals. For example, terminals120may be exposed in a cavity using techniques such as, but not limited to, laser drilling/ablation to expose portions of the terminals. Terminal120A, shown inFIGS. 2 and 4, depicts an example of a terminal exposed by cavity-type processing. In some embodiments, portions of terminals120are exposed using flat-type processing such as, but not limited to, mechanical grinding/cutting processing. Terminal120B, shown inFIGS. 2 and 4, depicts an example of a terminal exposed by flat-type processing. In some embodiments, a film assistance mold (FAM) process is used to form encapsulant124in a mold shape that exposes portions of terminals120(e.g., the mold shape has cavities for the terminals or is flat but exposes portions of the terminals).

Terminals114may have a higher height than encapsulant108to ensure connection between the terminals in bottom package102′ and terminals (e.g., terminals120) in top package104′.

As described above for the embodiments shown inFIGS. 2-6, at least partially covering the bottom (backside) of top package104′ (or top package104″) with encapsulant124in addition to covering the top (frontside) of the top package with encapsulant118may create a top package structure with substantially balanced thermal properties (e.g., having encapsulant on the backside and the frontside of the top package balances thermal properties such as, but not limited to, CTE and shrinkage rate in the top package). Balancing of the thermal properties in the top package may balance thermal stresses on the top package and reduce or inhibit warping in the top package, especially for top packages with thin or coreless substrates. Reducing warping in the top package may improve pre-stacking and improve the reliability of a PoP package that has fine pitch (e.g., reduced pitch between terminals) and thin or coreless substrates. In addition, accommodating the die from the bottom package in recess126(or recess126′) in encapsulant124allows the PoP package to maintain a reduced (or thin) overall PoP package thickness.

Embodiments described herein describe a structure and a method for forming a PoP package with a top package having encapsulant on both sides of the top package. It would be apparent to those skilled in the art, however, that the embodiments described herein may be applied to the bottom package for use with surface mount technology (SMT) on a printed circuit board and/or in a module/system level assembly.