Method of fabricating a LDDFET with self-aligned silicide

A method of fabricating a lightly-doped drain field effect transistor (LDDFET) with or without self-aligned silicide (salicide) on a substrate is disclosed. The initial steps include either (1) anisotropic silicon nitride and polysilicon etching steps, an isotropic photoresist erosion step, and a second anisotropic etching of part of the silicon nitride to obtain a ladder-shaped polysilicon gate having a silicon nitride thereon; or (2) an anisotropic polysilicon etch step, an isotropic photoresist erosion step to expose part of the unetched polysilicon, and a second anisotropic polysilicon etch step to remove completely the unmasked polysilicon to obtain the ladder-shaped polysilicon gate. The LDD structure is formed by the implantation of ions to form a heavily-doped source and drain regions and lightly-doped regions under the step of the ladder-shaped polysilicon gate layer. Thereafter, the thin polysilicon step is oxidized completely. After the silicon nitride and silicon dioxide layers are removed, the self-aligned silicide may be applied to form the LDD with salicide.

BACKGROUND OF THE INVENTION 
In order to achieve high circuit performance and density, MOSFET 
(metal-oxide-semiconductor field effect transistor) devices in silicon 
integrated circuit technology are scaled down to submicrometer range. In 
scaling down MOSFETs, the reduction of device dimensions is not 
accompanied by a corresponding reduction in power requirements. As a 
result, NMOS (n-channel MOS) devices are susceptible to channel 
hot-electron (CHE) instability. See Chenming Hu et al., 
"Hot-Electron-Induced MOSFET Degradation--Model, Monitor and Improvement," 
IEEE Transactions on Electron Devices, Vol. ED-32, No. 2 (February 1985), 
pp. 375-385. The instability is caused by the very high electric field 
near the drain junction resulting from the short channel length and high 
supply voltage. 
Another difficulty caused by scaling down is the increase in the resistance 
of diffused layers. This results in increased signal delays along diffused 
interconnects and degrades circuit performance due to the large 
source/drain series resistance. 
To alleviate the high electric field at the reduced MOSFET channel length, 
lightly doped drain (LDD) devices have been proposed. See K. Saito et al, 
"A New Short Channel MOSFET with Lightly Doped Drain," Denshi Tsushin 
Rengo Taikai (in Japanese) (April 1978), p. 220. In the LDD structure, 
narrow, self-aligned, n.sup.- regions are introduced between the channel 
and the n.sup.+ source/drain regions. The n.sup.- region spreads the high 
electric field out near the drain junction, allowing the device to be 
operated at a higher supply voltage with fewer hot-electron problems. 
Several processes for fabricating lightly-doped drain field effect 
transistor (LDDFET) have been proposed. Spacer and overhang techniques are 
most commonly adopted. The spacer technique involves a reactive-ion 
etching (RIE) step after silicon dioxide is chemically vapor deposited to 
form side wall oxide spacers. Oxide spacers are used to mask the heavy and 
deep implant of the n.sup.+ drain/source regions after the formation of 
the shallow n.sup.- drain/source regions. See FIG. 2, p. 590, of Paul J. 
Tsang et al., "Fabrication of High-Performance LDDFET's with Oxide 
Sidewall-Spacer Technology," IEEE Transactions on Electron Devices, Vol. 
ED-29, No. 4 (April 1982). The overhang technique involves a polysilicon 
over-etching step after SiO.sub.2 /Si.sub.3 N.sub.4 /poly-Si/SiO.sub.2 
gate stack is patterned to form SiO.sub.2 /Si.sub.3 N.sub.4 overhangs. 
SiO.sub.2 /Si.sub.3 N.sub.4 overhangs are used to mask the heavy and deep 
implant of the n.sup.+ drain/source regions followed by the formation of 
the shallow n.sup.- drain/source regions. See FIG. 2, p. 1360, of Seiki 
Ogura et al., "Design and Characteristics of the Lightly Doped 
Drain-Source (LDD) Insulated Gate Field-Effect Transistor," IEEE 
Transactions on Electron Devices, Vol. ED-27, No. 8 (August 1980). 
Two alternative structures, buried LDD and graded/buried LDD structures, 
adopting sidewall oxide spacer technology, have also been demonstrated. 
See Ching-Yeu Wei et al., "Buried and Graded/Buried LDD Structures for 
Improved Hot-Electron Reliability," IEEE Electron Device Letters, Vol. 
EDL-7, No. 6 (June 1986), pp. 380-382. In the spacer technology, 
additional oxide deposition and oxide etch-back processes are needed. In 
the overhang technology, additional Si.sub.3 N.sub.4 /SiO.sub.2 deposition 
and polysilicon over-etching processes are required. In addition, two ion 
implantation steps are necessary and, therefore, these two processes are 
far too complicated for commercial application. 
Still another method described is the so-called self-defined polysilicon 
sidewall (SEPOS) technique which uses SiO.sub.2 at the vertical sides of 
the polysilicon to define the oxide-framed polysilicon sidewall. See FIG. 
1, p. 2463, of M. Saitoh, "Degradation Mechanism of Lightly Doped Drain 
(LDD) n-Channel MOSFET's Studied by Ultraviolet Light Irradiation," J. 
Electrochem. Soc.: Solid-State Science and Technology, Vol. 132, No. 10 
(October 1985), pp. 2463-2466. 
Also proposed has been the self-aligned polysilicon source/drain (SAPSD) 
technique which uses a n.sup.+ polysilicon source/drain layer to allow the 
dopants to diffuse into the substrate to form the n.sup.- region. See FIG. 
1, p. 314, of Tiao-Yuan Huang et al., "A MOS Transistor with Self-Aligned 
Polysilicon Source-Drain," IEEE Electron Device Letters, Vol. EDL-7, No. 5 
(May 1986), pp. 314-316. 
The inverse-T LDD (ITLDD) transistor has also been proposed. This 
transistor uses a sidewall oxide spacer to define the n.sup.- region. See 
FIG. 2, page 743, of Tiao-Yuan Huang et al., "A Novel Submicron LDD 
Transistor with Inverse-T Gate Structure," IEDM 86 (International Electron 
and Device Meeting 1986), Sec. 31.7, pp. 742-745. Unfortunately, all of 
these techniques are too difficult because of the complexity of the 
processes. 
In addition, a new LDD structure for NMOS FET has also been demonstrated. 
It may be made using a single ion implantation step to form n.sup.- 
regions due to the sloped sidewall of the structure. See FIG. 1, p. 28, of 
"A New Structure LDD for NMOSFET," Japan Semiconductor News, Vol. 3, No. 3 
(June 1984), pp. 27-28. Unfortunately, the gate of the FET is much higher 
than source/drain regions. 
To overcome the series resistance problem, self-aligned silicide (salicide) 
technology has been proposed. This approach reduces device series 
resistance and enhances interconnects. See C. M. Osburn et al., "High 
Conductivity Diffusions and Gate Regions using Self-Aligned Silicide 
Technology," Electrochemical Society Proceedings, First International 
Symposium VLSI Science and Technology, Vol. 82--7 (1982), pp. 213-223. In 
salicide technology, a gate sidewall oxide is formed which protects the 
gate sidewall from shorting to the source/drain regions after 
salicidation. 
Combining LDD with salicide technologies has been reported. See FIG. 6, p. 
347, of Fang-Shi J. Lai et al., "Design and Characteristics of a Lightly 
Doped Drain (LDD) Device Fabricated with Self-Aligned Titanium 
Disilicide," IEEE Transactions on Electron Devices, Vol. ED-33, No. 3 
(March 1986), pp. 345-353. However, the fabrication of the LDDFET requires 
additional depositing and etching of chemical vapor deposited films and 
two ion implantation steps. Accordingly, the process is far too 
complicated. 
SUMMARY OF THE PRESENT INVENTION 
The present invention relates to a technique of fabricating a lightly-doped 
drain field effect transistor (LDDFET) using a single ion-implantation 
with or without self-aligned silicide (salicide). 
A high quality silicon dioxide layer is thermally grown on a silicon wafer, 
and a polysilicon layer is then deposited over the thermal oxide layer. A 
n.sup.+ diffusion step is performed to dope the polysilicon layer and a 
silicon nitride layer is deposited thereon. The photoresist mask having a 
polysilicon gate pattern is then applied using conventional photoresist 
coating and optical lithography techniques. 
In a first technique of the invention, a first dry etching step is 
performed in which silicon nitride is removed completely and polysilicon 
is anisotropically etched to a proper thickness. Then the photoresist 
masking layer is isotropically etched (eroded) to expose part of the 
unetched silicon nitride layer; and a second dry etching step is performed 
to remove silicon nitride and polysilicon layers until all of the 
remaining polysilicon on source and drain regions are removed. 
In the second technique of the invention, a portion of the unmasked 
polysilicon is anisotropically etched to a predetermined thickness. Then 
the photoresist masking layer is isotropically etched to expose part of 
the unetched polysilicon, and a second partial etch of the newly unmasked 
polysilicon performed until all of the remaining polysilicon on the source 
and drain regions is removed. 
These steps complete the formation of the ladder polysilicon gate. When the 
first technique is used, the gate has silicon nitride on top of it. 
After the photoresist masking layer is stripped, a heavy n-type ion 
implantation process is performed to achieve source/drain regions and 
lightly-doped source/drain regions at the same time. An oxidation process 
is then followed to oxidize the thin polysilicon steps completely. The 
silicon nitride layer and silicon dioxide layers on the source/drain 
regions are removed, leaving the polysilicon dioxide around the sidewall 
of the polysilicon gate. Thereafter, a thin layer of metal is deposited to 
form metal silicide at both polysilicon gate and source/drain regions. A 
selective etchant is then used to remove the unreacted metal, but not the 
metal silicides, to form the LDDFET with salicide.

DETAILED DESCRIPTION OF THE INVENTION 
According to the present invention, an improved method is provided to 
fabricate the lightly doped drain field effect transistor (LDDFET) with or 
without self-aligned silicide (salicide). This technique finds particular 
application in the processing of silicon wafers for integrated circuit 
chips. Accordingly, the invention will be described for this particular 
application. 
Referring now to the drawings, FIG. 1 shows a section through the silicon 
wafer after the initial processing steps. The silicon wafer, designated by 
the reference character 10, has grown thereon a thin film of silicon 
dioxide (SiO.sub.2), 20. On top of the SiO.sub.2 is a layer of doped 
polysilicon, 30, which has been doped using in-situ chemical vapor 
deposition (CVD) or a diffusion process. On top of the polysilicon 30 is a 
layer of silicon nitride, 40, which is deposited using conventional low 
pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical 
vapor deposition (PECVD). On top of the silicon nitride 40 is a 
photoresist masking layer, 50, having a polysilicon gate pattern. This 
pattern is defined using standard photoresist coating, exposure and 
development processes. 
FIG. 2 shows the resulting structure after the unmasked portions of silicon 
nitride 40 and a part of polysilicon 30 are etched anisotropically. The 
anisotropic etching can be performed using the reactive-ion etching 
system, for example, AME-8110 system (trademark of Applied Material Co.). 
The silicon nitride etching is performed using 60 SCCM (standard cubic 
centimeters per minute) of CHF.sub.3 and 35 SCCM of O.sub.2 at a pressure 
of 40 milli-torr and a power of 600 watts. This gives an etch rate of 
about 630.+-.10 Angstroms/min. For polysilicon etching, 65 SCCM of Ar and 
20 SCCM of NF.sub.3, a pressure of 40 milli-torr and a D.C. bias of -230 V 
are preferred, with the etch rate being about 250.+-.15 Angstroms/min. The 
amount of the polysilicon layer removed is carefully determined, typically 
700 Angstroms. The remainder of the unmasked polysilicon layer, designated 
by the reference character 32, is left on the silicon dioxide and the 
remainder of the silicon nitride, designated by the reference character 
42, is left on the polysilicon. This layer 42 plays the role of an 
oxidation resistance layer during the subsequent polysilicon oxidation 
step. 
FIG. 3 shows the resulting structure after the photoresist masking layer is 
isotropically etched. This etch step exposes the desired portion of the 
etch-resistant silicon nitride layer 42. The isotropic etching can be 
performed using a dry etching process, for example, by introducing 50 SCCM 
of O.sub.2 gas into AME-8110 system, at a pressure of 100 milli-torr and 
a power of 300 watts to etch the photoresist at a lateral rate of about 
800.+-.30 Angstroms/min. The remaining portion of photoresist masking 
layer is designated by the reference character 52. The remaining portion 
of the unetched silicon nitride is designated by the reference character 
44. 
FIG. A-4 shows the resulting structure after the exposed silicon nitride 
layer and a portion of polysilicon layer 32 are removed completely by 
anisotropic etching using a AME-8110 system. As can be seen, there is 
formed a polysilicon "step," designated by the reference character 34, 
around the bottom of the polysilicon gate 30, the latter being under the 
eroded photoresist masking layer 52. The polysilicon step 34 is the 
remainder of the exposed unetched polysilicon 32 after the first 
polysilicon anisotropic etching. The length of this step corresponds to 
the length of lightly-doped regions and is designed to be in the range of 
0.25-0.30 micrometer for standard applications. The thickness of 
polysilicon step 34 is, making reference to FIG. 2, equal to the 
difference between the thickness of unetched polysilicon gate 30 and the 
thickness of the partially etched polysilicon 32, i.e., the thickness of 
the polysilicon removed in the first polysilicon etching procedure. As 
stated above, the thickness of polysilicon step 34 is, in this example, 
700 Angstroms. The remainder of silicon nitride 42, designated by the 
reference character 46, is left on top of the polysilicon gate 30 after 
etching. 
FIG. A-5 shows the resulting structure after the photoresist masking layer 
52 is removed using, for example, a sulfuric acid stripping solution. As 
can be seen, the polysilicon gate is ladder-shaped, i.e., has the step 34, 
with silicon nitride on top of it. This is an essential feature in the 
process for making an LDDFET with salicide. 
FIG. A-6 shows the resulting structure after the source/drain region is 
doped by ion implantation. The portions outside the ladder-shaped 
polysilicon gate regions are unmasked and therefore the implanting dopants 
penetrate far into the silicon to form the highly-doped source/drain 
regions 62. The portion of the silicon under the polysilicon step 34, 
being incompletely masked by the thin layer of polysilicon, are only 
partially penetrated by the dopant and form lightly-doped source/drain 
regions 64. The portion under the thick polysilicon gate region 30 and the 
silicon nitride layer 46 is completely masked and, therefore, the 
implanting dopants are prevented from reaching the silicon substrate in 
the gate region. 
The ladder-shaped polysilicon gate formed in accordance with the invention 
permits the simultaneous formation of the highly-doped source/drain 
regions and lightly-doped source/drain regions by means of a single heavy 
dose source/drain ion implantation process. Since the thickness or height 
of the polysilicon step 34 determines the degree of ion implantation in 
the lightly doped source/drain region, it must be carefully designed. For 
example, a 700 Angstrom polysilicon step is chosen for an arsenic dopant, 
6.times.10.sup.15 doses/cm.sup.2, 80 kilo electron volts energy, 
source/drain ion implantation process. The proper thickness of the step 
may be readily determined by those skilled in the art by considering the 
particular dopant to be used and the degree of ion implantation desired. 
After the LDDFET is fabricated, the salicide process is commenced. 
Referring now to FIG. A-7, the structure is subjected to oxidation so that 
the thin polysilicon step 34 is oxidized completely. The layer of the 
polysilicon dioxide 36 is about twice as thick as the thin polysilicon 
step 34 from which it was formed. In this example, a 1400 Angstrom 
polysilicon dioxide layer is obtained by oxidizing the 700 Angstrom 
polysilicon layer. The silicon dioxide layer, formed at the sidewall of 
the gate, protects the gate sidewall from shorting to source/drain regions 
during the salicidation process. In addition, the silicon nitride layer 46 
prevents the oxidation of the top of the polysilicon layer 30 because the 
former is highly oxidation-resistant. The polysilicon gate, after 
oxidation, is designated by the reference character 38. The silicon 
dioxide formed over the source/drain regions is designated by the 
reference character 22. The oxidation process can be performed by exposing 
the structure to oxygen for 5 min., to a mixture of oxygen and hydrogen 
chloride for 45 min., and to nitrogen for 15 min. in a furnace at 
920.degree. C. 
FIG. A-8 shows the resulting structure after the silicon nitride layer 46 
is removed. This is accomplished by using a dry etching process, as for 
example by introducing 60 SCCM of CHF.sub.3 and 35 SCCM of O.sub.2 into 
AME-8110 system at a pressure of 40 milli-torr and a power of 600 watts. 
Under these conditions an etch rate of about 630.+-.10 Angstroms/min. is 
achieved. 
FIG. A-9 shows the resulting structure after the silicon dioxide layers 22 
are removed by using, for example, a diluted HF solution. During this step 
a portion of polysilicon dioxide layer 36, corresponding in thickness with 
the silicon dioxide layer 22, is also removed. The remainder of the 
polysilicon dioxide layer is designated by the reference character 39. 
FIG. A-10 shows the resulting structure after self-aligned silicide layers 
are formed. The first step in this process is the deposition of a metal 
film over the wafer. The silicide is then formed by reacting the metal 
with the silicon in a selected atmosphere at a selected temperature to 
anneal the structure. Finally, the unreacted metal is removed by a 
selective wet etch process that etches metal without attacking silicide or 
polysilicon dioxide, thereby leaving silicides 72 on the gate, source and 
drain regions. As an example of the foregoing, TiSi.sub.2 (titanium 
disilicide) is formed at temperatures of about 600.degree.-700.degree. C. 
The selective etch is accomplished using a mixed solution of one part 
H.sub.2 O.sub.2, one part NH.sub.4 OH and five parts H.sub.2 O. A second 
anneal after etching is performed at 800.degree. C. See C. Y. Ting et al., 
"The Use of TiSi.sub.2 in a Self-Aligned Silicide Technology," 
Electrochemical Society, Proceedings of First International Symposium on 
VLSI Science and Technology (1982), pp. 224-231 and C. Y. Ting, "Silicide 
for Contacts and Interconnects," IEDM 84 (International Electron Device 
Meeting 1984), Sec. 5.1, pp. 110-113. 
The key features of the LDDFET with salicide are now achieved. By 
performing conventional low temperature oxidation, contact window opening, 
metallization and passivation processes, the LDDFET with salicide is ready 
for practical applications. 
As a further embodiment of the invention, the incompletely anisotropic 
polysilicon etching and the isotropic photoresist eroding steps of the 
process described above can be repeated several times to form a multi-step 
ladder-shaped polysilicon gate. The technique can be used to form a 
multi-region lightly-doped field effect transistor with salicide. The 
several polysilicon steps, each with different thicknesses, allow 
different amounts of dopants to penetrate, thereby forming lightly-doped 
regions with a gradation of doping concentrations under each polysilicon 
step after the ion implantation step is performed. Two-, three-, four- and 
multi-region, lightly-doped drain field effect transistors can all be 
readily fabricated by following the teaching of the invention. Such 
multi-region LDD reduce further the channel hot-electron instability, as 
has been described in connection with graded/buried LDD structures. 
The process for forming a ladder-shaped polysilicon gate having two steps 
may be readily understood by references to FIGS. 1 through 3 and B-4 
through B-12. The first three steps of the process described in FIGS. 1 to 
3 are identical to those described above and need not be repeated here. 
The structure, having been subjected to the first mask erosion step shown 
in FIG. 3, is, as shown in FIG. B-4, subjected to an anisotropic etching 
process which completely removes the unmasked silicon nitride film and the 
partially unmasked polysilicon film. As will be noted, this process 
results in the formation of a second step in the polysilicon layer. 
FIGS. B-5 and B-6 show the structure after the second mask erosion step and 
the second anisotropic etching step. In this latter step, the newly 
unmasked silicon nitride is removed and the partially etched polysilicon 
outside the gate region is completely removed so as to expose the gate 
SiO.sub.2 layer. FIG. B-7 shows the structure after the photoresist layer 
is removed in preparation for the ion-implantation step illustrated in 
FIG. B-8. As is shown in FIG. B-8, n.sup.+ source and drain regions are 
formed under the exposed silicon dioxide layer, wherein n.sup.- and 
n.sup.-- layers are formed beneath the steps of the polysilicon. It will 
be understood that, since the first polysilicon step is but a thin layer, 
it serves to only partially mask the ions from penetrating the 
semiconductor substrate. In contrast, the second step, representing a 
somewhat thicker layer, further reduces the ion-implantation in the area 
adjacent to the gate region. This gradation is particularly effective in 
minimizing the hot-electron effect. 
After the implantation step, as illustrated in FIG. B-9, the structure is 
subjected to an oxidative environment and the exposed surface of the 
polysilicon is converted to polysilicon dioxide spacers. Thereafter, as 
shown in FIGS. B-10 and B-11, the silicon nitride layer and the silicon 
dioxide layer over the source and drain regions are removed. The salicide 
layers are then formed over the gate and the source and drain regions as 
shown in FIG. B-12. 
It will be understood that the specific steps described in connection with 
the first embodiment of the invention may be readily applied to this 
second embodiment of the invention and, therefore, in order to avoid 
redundancy, such steps are not described in detail in connection with this 
embodiment. 
The third embodiment of the invention, steps of which are shown in FIGS. 
C-2 through C-5 of the attached drawings, shows a technique for forming 
the ladder polysilicon gate without the need of using the isotropic 
etching of the photoresist mask. This method is comparable to the first 
embodiment to the extent that the initial steps necessary to form FIG. 1 
are followed. However, as shown in FIG. C-2, the structure of FIG. 1 is 
successively subjected to an anisotropic etching step to remove the 
unmasked silicon nitride layer 40 and to partially remove the unmasked 
polysilicon layer 30. In this process, the photoresist layer 50 is then 
completely removed. 
As illustrated in FIG. C-3, the next step is to chemically vapor deposit a 
silicon oxide layer over the surface of the structure shown in FIG. C-2. 
Thereafter, using anisotropic etching, preferably reactive ion etching, 
spacers 82 are formed which cover the vertical surfaces of the silicon 
nitride and the thick central portion of the polysilicon layer as well as 
a defined portion of the horizontal surface of the thin polysilicon layer. 
The sequence of CVD deposition of silicon dioxide followed by reactive ion 
etching is referred to as spacer technology. This is described in IEEE, 
Vol. ED-29, No. 4, p. 590. 
The next step in the process is the removal of the entire unmasked 
polysilicon layer 31. The residual polysilicon is illustrated in FIG. C-4 
and comprises a thick central portion 30 and a thin step 34. This stage of 
the process is completed by etching the structure to completely remove the 
spacer 82, thereby forming the structure shown in FIG. C-5. It will be 
noted that the structure in FIG. C-5 is comparable to that shown in the 
first embodiment of the invention in FIG. A-6. From this point in the 
process, the fabrication of the LDDFET with self-aligned silicide is 
substantially the same as that shown for the first embodiment of the 
invention. 
The fourth embodiment of the invention is a variation on the technique for 
forming the two-step LDDFET with salicide. The initial steps in this 
embodiment are similar to the third embodiment of the invention down 
through the processing steps illustrated in FIG. C-3. 
After the silicon dioxide spacer is formed, a second anisotropic etching 
step is carried out to further reduce the thickness of the polysilicon 
layer. The resulting structure is illustrated in FIG. D-4. It will be 
noted that the silicon dioxide spacer and the silicon nitride layer act as 
a mask in this processing step. 
In the next step, a second chemical vapor deposition step takes place, 
followed by anisotropic etching to form the silicon dioxide spacer shown 
in FIG. D-5. This step in essence increases the thickness of the silicon 
dioxide spacer so that it now covers the thin polysilicon layer. Using the 
same techniques as previously described, the unmasked polysilicon layer is 
now completely removed, exposing the thin silicon dioxide layer on top of 
the silicon substrate to form the structure shown in FIG. D-6. 
FIG. D-7 shows the two-step ladder polysilicon gate structure after the 
silicon dioxide spacer and the unmasked thin silicon dioxide layer are 
removed. Thereafter, the salicide is formed, following substantially the 
steps set forth in FIGS. B-8 to B-12. The key advantage of the spacer 
technology described in the third and fourth embodiments of the invention 
is the controllability of the polysilicon etching. In the photoresist 
eroding process, shown in the first two embodiments of the invention 
described above, it is difficult to form a polysilicon step of the desired 
thickness without leaving a polysilicon residue outside of the gate 
region. In spacer technology, in contrast, the spacer is formed to mask 
the polysilicon step after the desired thickness has been achieved. 
Thereafter, the anisotropic etching can be used to remove the polysilicon 
outside of the gate region completely while the polysilicon step is 
protected. 
As a further embodiment of the invention, after the ion implantation step 
of the process (e.g., FIGS. A-6 and B-8) is performed, the silicon nitride 
layer may be removed. This results in a ladder-gate or a multi-region 
ladder-gate LDDFET without salicide. Such process can also be used to 
fabricate n-channel MOSFETs. 
In addition, the ion implantation step of the process may be omitted and 
the invention applied as a spacer formation process. Such process may be 
used to fabricate NMOS or PMOS with salicide. 
The second technique of the invention is shown in the four embodiments 
illustrated in FIGS. E-1 to H-7. FIG. E-1 shows a section through the 
silicon wafer after the initial processing steps. The silicon wafer, 
designated by the reference character 10, has grown thereon a thin film of 
silicon dioxide (SiO.sub.2), 20. On top of the SiO.sub.2 is a layer of 
doped polysilicon, 30, which has been doped using in-situ chemical vapor 
deposition (CVD) or a diffusion process. On top of the polysilicon 30 is a 
photoresist masking layer, 50, having a polysilicon gate pattern. This 
pattern is defined using standard photoresist coating, exposure and 
development processes. 
FIG. E-2 shows the resulting structure after the unmasked portions of 
polysilicon 30 are etched anisotropically. The anisotropic etching can be 
performed using the reactive-ion etching system as described above. The 
amount of the polysilicon layer removed is carefully determined, typically 
700 Angstroms. The remainder of the unmasked polysilicon layer, designated 
by the reference character 32, is left on the silicon dioxide. 
FIG. E-3 shows the resulting structure after the photoresist masking layer 
is isotropically etched. This etch step exposes the desired portion of the 
polysilicon layer 30. The remaining portion of photoresist masking layer 
is designated by the reference character 52. 
FIG. E-4 shows the resulting structure after the exposed portion of 
polysilicon layer 32 is removed completely by anisotropic etching. There 
is formed a polysilicon "step" 36 around the bottom of the polysilicon 
gate 30, the latter being under the eroded photoresist masking layer 52. 
The polysilicon step 36 is the remainder of the exposed unetched 
polysilicon 32 after the first polysilicon anisotropic etching. 
FIG. E-5 shows the resulting structure after the photoresist masking layer 
52 is removed. As can be seen, the polysilicon gate is ladder-shaped, 
i.e., has the step 36. 
FIG. E-6 shows the resulting structure after the source/drain region is 
doped by ion implantation. The portions outside the ladder-shaped 
polysilicon gate regions are unmasked and therefore the implanting dopants 
penetrate far into the silicon to form the highly-doped source/drain 
regions 62. The portion of the silicon under the polysilicon step 36, 
being incompletely masked by the thin layer of polysilicon, are only 
partially penetrated by the dopant and form lightly-doped source/drain 
regions 64. The portion under the thick polysilicon gate region 30 is 
completely masked and, therefore, the implanting dopants are prevented 
from reaching the silicon substrate in the gate region. 
The process for forming a ladder-shaped polysilicon gate having two steps 
according to the second technique of the invention is shown in FIGS. F-1 
through F-8. The first three steps of the process shown in FIGS. F-1 to 
F-3 are identical to those in FIGS. E-1 to E-3 and need not be repeated 
here. The structure, having been subjected to the first mask erosion step 
shown in FIG. E-3, is, as shown in FIG. F-4, subjected to an anisotropic 
etching process which removes the partially unmasked polysilicon film. As 
will be noted, this process results in the formation of a second step in 
the polysilicon layer. 
FIGS. F-5 and F-6 show the structure after the second mask erosion step and 
the second anisotropic etching step. In this latter step, the newly 
unmasked polysilicon is removed and the partially etched polysilicon 
outside the gate region is completely removed so as to expose the gate 
SiO.sub.2 layer. FIG. F-7 shows the structure after the photoresist layer 
is removed in preparation for the ion-implantation step illustrated in 
FIG. F-8. As is shown in FIG. B-8, n.sup.+ source and drain regions are 
formed under the exposed silicon dioxide layer, wherein n.sup.- and 
n.sup.-- layers are formed beneath the steps of the polysilicon. It will 
be understood that, since the first polysilicon step is but a thin layer, 
it serves to only partially mask the ions from penetrating the 
semiconductor substrate. In contrast, the second step, representing a 
somewhat thicker layer, further reduces the ion-implantation in the area 
adjacent to the gate region. This gradation is particularly effective in 
minimizing the hot-electron effect. 
The seventh embodiment of the invention, steps of which are shown in FIGS. 
G-1 through G-5 of the attached drawings, shows a technique for forming 
the ladder polysilicon gate without the need of using the isotropic 
etching of the photoresist mask. This method is comparable to the first 
embodiment to the extent that the initial steps necessary to form FIG. 1 
are followed, with the exception that a silicon dioxide layer 60 is formed 
between the polysilicon layer 30 and the photoresist 50. As shown in FIG. 
G-2 the structure of FIG. 1 is successively subjected to an anisotropic 
etching step to remove the unmasked silicon dioxide layer 60 and to 
partially remove the unmasked polysilicon layer 30. In this process, the 
photoresist layer 50 is then completely removed. 
As illustrated in FIG. G-3, the next step is to chemically vapor deposit a 
silicon oxide layer over the surface of the structure shown in FIG. G-2. 
Thereafter, using anisotropic etching, preferably reactive ion etching, 
spacers 82 are formed which cover the vertical surfaces of the silicon 
dioxide and the thick central portion of the polysilicon layer as well as 
a defined portion of the horizontal surface of the thin polysilicon layer. 
The next step in the process is the removal of the entire unmasked 
polysilicon layer 31. The residual polysilicon is illustrated in FIG. G-4 
and comprises a thick central portion 30 and a thin step 36. This stage of 
the process is completed by etching the structure to completely remove the 
spacer 82, thereby forming the structure shown in FIG. G-5. It will be 
noted that the structure in FIG. G-5 is comparable to that shown in the 
fifth embodiment of the invention in FIG. E-5. From this point in the 
process, the fabrication of the LDDFET is substantially the same as that 
shown for the fifth embodiment of the invention. 
The eighth embodiment of the invention is a variation on the technique for 
forming the two-step LDD. The initial steps in this embodiment, FIGS. H-1 
to H-3, are similar to the seventh embodiment of the invention down 
through the processing steps illustrated in FIG. G-3. 
After the silicon dioxide spacer is formed, a second anisotropic etching 
step is carried out to further reduce the thickness of the polysilicon 
layer. The resulting structure is illustrated in FIG. H-4. It will be 
noted that the silicon dioxide spacer and the silicon dioxide layer act as 
a mask in this processing step. 
In the next step, a second chemical vapor deposition step takes place, 
followed by anisotropic etching to form the silicon dioxide spacer shown 
in FIG. H-5. This step in essence increases the thickness of the silicon 
dioxide spacer so that it now covers the thin polysilicon layer. Using the 
same techniques as previously described, the unmasked polysilicon layer is 
now completely removed, exposing the thin silicon dioxide layer on top of 
the silicon substrate to form the structure shown in FIG. H-6. 
FIG. H-7 shows the two-step ladder polysilicon gate structure after the 
silicon dioxide spacer and the unmasked thin silicon dioxide layer are 
removed. Ion-implantation follows to form the LDDFET structure as 
described above. 
In scaling down MOSFETs, many problems arise. Hot-electron instability and 
series resistance are two of the main problems. The hot-electron 
instability problem is eliminated by using the LDD structure, while series 
resistance is reduced by using salicide interconnections. 
In addition to the steps recited above for fabricating the standard NMOS or 
PMOS, a series of additional process steps is employed. These include 
defining the isolation region, forming gate dielectrics, defining 
polysilicon gate regions, ion-implantation of the source and drain 
regions, low temperature oxide deposition, forming window openings for the 
contacts, metallization, and passivation. For CMOS integrated circuit 
fabrication, a well formation step must first be employed and the p.sup.+ 
and n.sup.+ source/drain regions formed individually. The foregoing 
additional steps are well known in the art. 
In the description of the embodiments of the invention set forth above, it 
is assumed that the isolation region (for NMOS and PMOS) or well and 
isolation regions (for CMOS) have already been formed in accordance with 
conventional procedures. 
It will be understood that only NMOS devices have the hot-electron 
instability problem; accordingly, the ladder-gate LDDFET with or without 
salicide would only be used to fabricate n-channel MOSFETs. On the other 
hand, both NMOS and PMOS devices have series resistance problems, thereby 
making the use of the spacer formation process with salicides particularly 
useful. 
The foregoing description is for purposes of illustration only. It will be 
readily understood that many variations thereof, which will not depart 
from the spirit of the invention, will be apparent to those skilled in the 
art.