Method and apparatus for reconfigurable memory

A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.

FIELD OF THE INVENTION

The invention relates generally to the field of memory. Particularly, the invention relates to reconfigurable memory.

BACKGROUND OF THE INVENTION

As integrated circuit devices have become more complex, their die sizes have increased even though transistor sizes have been decreasing. This is so because of the increased demand for performance, functionality and integration into today's integrated circuits. To accommodate the increased die sizes of integrated circuits, the actual sizes of wafers used in semiconductor manufacturing of integrated circuits has been increasing as well to manufacture a reasonable number of the large die sizes simultaneously. It is not uncommon to talk about integrated circuits being one inch by one inch and manufactured on a wafer having a diameter of twelve inches or more. While wafer sizes have increased, they have not kept up with the demand for die size increases of integrated circuits. As a result, the number of dies of an integrated circuit on one wafer (die per wafer) has been decreasing. Thus, the yield of each individual die of the integrated circuit across a wafer is important in order to lower costs and obtain higher profit margins. Yield is even more important when memory circuitry having memory cells is included. The memory cells tend to be more sensitive to certain types of defects in semiconductor manufacturing because of their dense transistor circuitry.

Memory integrated circuits, such as random access memory (RAM) integrated circuits and read only memory (ROM) integrated circuits, typically have a rated capacity such as thirty two megabytes or sixty-four megabytes. The entire rated capacity needs to be functional in order to sell the memory integrated circuit. Thus, manufacturers of memory integrated circuits usually provide redundant rows and/or redundant columns of memory cells to substitute in for a bad row or bad column of memory cells.

Bad rows or bad columns in a memory integrated circuit are typically discovered during wafer testing prior to packaging the memory integrated circuit. In this case, fuses or links in the memory integrated circuit can be cut by a laser to substitute in a redundant row or a redundant column of memory devices for a respective bad row or bad column.

Other types of integrated circuits which are not a memory integrated circuit may include some memory circuitry therein. Typically if any part of the memory circuitry therein was tested to be defective, the entire integrated circuit was marked as being defective and discarded.

Today some integrated circuits, including micro-processor integrated circuits, micro-computer integrated circuits, application specific integrated circuits, custom integrated circuits, digital signal processing integrated circuits, and application specific signal processing integrated circuits, commonly have large blocks of memory circuitry therein such as one to sixteen megabytes or more of memory. Because the memory circuitry has become much larger in these integrated circuits, it can cause a higher rate of failure.

Like reference numbers and designations in the drawings indicate like elements providing similar functionality.

DETAILED DESCRIPTION OF THE INVENTION

In the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, the invention may be practiced without these specific details. In other instances well known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the invention.

A reconfigurable memory in an integrated circuit includes memory cells and a memory controller. To support the reconfigurable memory, memory cells are tested to determine if there is a failure in the cell or a failure in accessing the cell during a read or write operation. After determining where any failure exists, the address locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. Memory blocks may also be referred to as memory banks. This allows the logical addressing to work around the unusable memory cells or memory blocks. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable at a reduced functional percentage.

Referring now toFIG. 1, an integrated circuit100including a reconfigurable memory102is illustrated. The reconfigurable memory102is reconfigurable in that it can map out bad or unusable memory cells. Memory blocks of the reconfigurable memory102having a bad memory cell therein can be mapped out so that they are not addressed. To further support the reconfigurable memory102, the integrated circuit100includes a test access port (TAP)104, a built in self-tester (BIST)106, a host port107, and a memory test register108. The reconfigurable memory102in one embodiment is a global memory such that data and code of programs can be shared by one or more execution units EU1112A through EUN112N. The integrated circuit in one embodiment is application specific signal processor and the one or more execution units EU1112A through EUN112N are digital signal processing units to process one or more communication channels.

The built-in-self-tester106within the integrated circuit100in one embodiment is a memory tester to test each and every memory block and memory cell of the reconfigurable memory102in order to determine or detect which memory blocks and memory cells are bad. After testing the reconfigurable memory102, the unusable or bad memory cells and memory blocks can be mapped out by reprogramming the relationship between the logical address space and the physical address space. The BIST106is a hardware BIST and includes one or more controllers, a state machine, a comparator, and other control logic. The one or more controllers controls the testing of memory blocks212in the reconfigurable memory102. To speed testing, the one or more controllers operate in parallel each testing a one or more memory blocks at a time. This reduces testing time and testing costs and the time for realignment of the logical addresses by a system. It is preferable to not test all memory blocks at the same time in order to avoid peak power consumption. In one embodiment, three controllers are provided each to test six memory blocks in a reconfigurable memory having eighteen memory blocks. The state machine under an algorithm is used to generate the addresses and the data of a test pattern to test the reconfigurable memory102. The comparator within the BIST106performs a comparison between the actual test results and the expected test results to determine if a memory block or memory cell within the reconfigurable memory passed or failed a test.

The test access port104is a Joint Test Action Group (JTAG) serial test port in one embodiment. Testing of the reconfigurable memory102can be initiated externally through the test access port104, the host port107or another access port that can communicate with the built-in-self-tester106and the test register108. In the case that the test access port104is a JTAG test port, testing can be initiated externally by data communication over the input and/or output pins of the test access port104. In the case that the host port107is used to initiate testing of the reconfigurable memory, the data communication to initiate the testing is performed externally in parallel over parallel input and/or output pins of the host port107. To initiate and perform testing of the reconfigurable memory, the host port107couples to the memory test register108and the BIST106. To initiate and perform testing of the reconfigurable memory, the test access port104couples to the memory test register108and the BIST106. The testing can be kicked off externally by a host controller by writing to the memory test register108and setting a BIST start indicator508(shown inFIG. 5) of the register108. Alternatively, it can be kicked off through the test access port104.

The reconfigurable memory102is sized accordingly (i.e., it has a maximum capacity) such that reductions in memory capacity can still provide a functional device. For example, the reconfigurable memory102may have eight (8) megabits of maximum memory capacity configured as sixteen (16) blocks of five-hundred-twelve (512) kilobits. If one or more memory cells in one memory block goes bad, it can be mapped out reducing the total memory capacity. In the case of the example where a whole memory block is mapped out, the total memory capacity is reduced by five-hundred-twelve (512) kilobits. If additional blocks of memory are mapped out, the total memory capacity is reduced in additional increments of five-hundred-twelve (512) kilobits. A minimum capacity of the reconfigurable memory102may be a single block of memory such that the integrated circuit100can remain functional. In the exemplary reconfigurable memory102, one memory block is five-hundred-twelve (512) kilobits of memory capacity.

The total memory capacity of the reconfigurable memory102can be binned out during testing at the factory similar to frequency binning of integrated circuits, such as microprocessors. For example with a maximum total capacity of eight (8) megabits, the reconfigurable memory can be binned out in increments of five-hundred-twelve (512) kilobits according to the total usable memory space therein. That is, the integrated circuit100having the reconfigurable memory102may be binned out into bins of 8 meg, 7.5 meg, 7 meg, 6.5 meg, 6 meg, 5.5 meg, 5 meg, 4.5 meg, 4 meg and so on and so forth. Other bin sizes and increments of mapping out memory capacity can be used.

Similar to price points for various frequency bins, price points can be established for various levels of memory capacity of the reconfigurable memory102. The price of the integrated circuit100can be adjusted at each bin for the reduction in capacity of the reconfigurable memory102. The price points can be established because of different device yields which is inversely proportional to the device manufacturing costs.

The binning of the integrated circuit100for different memory capacities of the reconfigurable memory allows for increased die yield over a silicon wafer. For example, assume that only 10% of the die on a wafer test out to have a reconfigurable memory102with a maximum capacity. Assuming the reconfigurable memory102is binned out at 7 megabits of capacity and has five-hundred-twelve kilobit (512 k bit) memory blocks, by allowing two memory blocks each of 512 k bits to be defective, the yield of die per wafer can increase to approximately 25% for example. A greater percentage yield can be achieved for the integrated circuit100using lower memory capacity binning for the reconfigurable memory102. Thus, manufacturing costs and price can be reduced for an integrated circuit100including a reconfigurable memory102when binning is used.

In the case that the executions units EU1112A–EUN112N are digital signal processing units and the reconfigurable memory102is a global memory supporting a number of communication channels, the reduction in total memory capacity reduces the number of communication channels supported. With binning of the memory capacity of the reconfigurable memory and the respective channel capacity, the price and cost of manufacture of the integrated circuit100can be reduced.

Referring now toFIG. 2, a block diagram of the reconfigurable memory102is illustrated. The reconfigurable memory102includes a memory array202and a reconfigurable memory controller204. The memory array202is organized into one or more clusters210AA–210NN. The one or more clusters210AA–210NN are generally referred to as clusters210. Each cluster210includes a memory block A212A, a memory block B212B, a memory block C212C, and a memory block D212D generally referred to as memory block212. Each of the memory blocks212is in and of itself a memory unit including row and column address decoders, sense amplifiers, and tri-state drivers. The sense amplifiers are used to determine the data stored into memory cells which are addressed by row and column address decoders during a read operation. The tri-state drivers can be used to drive data into the memory cells addressed by row and column address decoders during a memory write operation. Each cluster210in the memory array202includes four memory blocks212and signals for each. These signals received by each cluster210are generally four read/write strobes R/W215and four chip select signals CS216, one for each memory block; and an address bus ADD217, a data bus input DB IN218, and a data bus output DB OUT219for each memory block. Each instance of these signals for each cluster includes a two letter extension on its reference number associated with the respective cluster as illustrated inFIG. 2. For example, cluster210AA receives four read/write strobes R/W215AA, four chip select signals CS216AA, one for each memory block; an address bus ADD217AA, a data bus input DB IN218AA, and a data bus output DB OUT219AA. In one embodiment, each address bus ADD217is sixteen bits wide to address sixty-four (64 k) kilo-words in each memory block using eight (8) bit words, and each data bus input DB IN218and data bus output DB OUT219is sixty-four bits wide. Each of the memory blocks212A–212D in each cluster210receives one of the R/W strobes215and one of the chip select signals CS216. Each of the memory blocks212A–212D in each cluster210couple to its respective address bus ADD217, data bus input218and data bus output219for each respective cluster. The chip select signals CS216represent a decoding of the upper address bits of the address bus207while the signals on each respective address bus ADD217for each memory block are a function of the lower address bits of the address bus207.

The reconfigurable memory controller204receives a read/write strobe R/W205, an address bus207, a data input bus208and a data output bus209. Reconfigurable memory controller204receives the read/write strobe R/W205and the address bus207to address the memory blocks and clusters in the memory array202by generating the appropriate signals on each cluster's four read/write strobes R/W215, four chip select signals CS216, and address bus ADD217.

The reconfigurable memory controller204also maps out the addresses of bad memory cells and bad memory blocks and then re-align the logical addressing to the physical addressing so as to achieve a continuous logical address map. For example, if during testing it is determined that the memory block B212B inFIG. 2has a bad memory cell, it is mapped out from the address space by the reconfigurable memory controller204. The reconfigurable memory controller204transparently maps out addresses such that the address space remains linearly configured from an address of zero to the usable capacity of the memory array202. After selectively configuring the reconfigurable memory controller204, a user or programmer can write to or read from the reconfigurable memory in a contiguous manner. In the case that the memory block B212B having the failure is mapped out, the maximum logical address of the address space, representing the usable capacity that is addressable in the memory array202, is reduced from the maximum physical address.

The reconfigurable memory controller204includes configuration registers which can be externally programmed in order to realign the logical addressing and map out bad memory blocks. The registers in one embodiment are externally programmed when the reconfigurable memory102is embedded within a system. Upon initialization, the reconfigurable memory102is tested and the initialization software programs the configuration registers to map out and realign the logical addressing. In another embodiment, the configuration registers are non-volatile or have a fuse-link type of programmability and can be programmed at the factory. In this case, the integrated circuit is tested in wafer or packaged form at the factory and the configuration registers are programmed as well accordingly. In either embodiment, the testing and reconfiguration of the reconfigurable memory can be transparent to the system designer and user of the printed circuit board incorporating the integrated circuit102. The testing of the reconfigurable memory102can be done by the integrated circuit itself by using the BIST when in a system. Alternatively, the reconfigurable memory102can be externally tested by production test software through the pins of a packaged integrated circuit or the pads of a die of the integrated circuit in wafer form.

Referring now toFIG. 3, the basic addressing functionality of the reconfigurable memory controller204is illustrated. Reconfigurable memory controller204receives a logical address and generates a physical address output which is coupled into the memory array202. The reconfigurable memory controller204further maps out addresses of bad memory blocks and bad memory cells and includes the configuration registers to realign the logical address map. In programming, the logical address map can be flexibly realigned including a realignment into a continuous linear address range.

Referring now toFIG. 4, an exemplary address space of a reconfigurable memory illustrating how address mapping of logical addresses into physical addresses with mapping out of addresses of bad memory blocks and bad memory cells is provided. Each memory block is assumed to access eight (8) bits with each address. If each memory block has five-hundred twelve (512 k) kilo-bits, then each memory block will have sixty-four (64 k) kilo-words of address space with each word being 8 bits wide. In the example ofFIG. 4, the memory block D1can correspond to memory block D212D of the memory cluster210AA and has an unusable memory cell. It is desirable to reconfigure the reconfigurable memory102so that the memory block D1is mapped out and a linear logical address space is maintained. InFIG. 4, the logical addresses and the logical bit sequence accessed by the logical addresses of the reconfigurable memory are on the left. The physical addresses and the physical bit sequence accessed thereby of the reconfigurable memory are on the right. The physical address space varies from a zero k-word address (0 k) to a maximal address (MAX/8 word) corresponding to the maximum capacity (MAX bits) of the reconfigurable memory102. The logical address space varies from a zero k-word address (0 k) to the maximum addressable range less the number of mapped out addresses (MAX/8-MOA).

In the example ofFIG. 4, a single memory block D1212D having a physical bit sequence from 1536 k-bit to (2048 k−1)-bit is mapped out due to a bad memory cell. In this case, the logical address and the physical address for logical bit sequence from 0 k-bit to (1536 k−1)-bit in memory blocks A1212A, B1212B, and C1212C are equal. Thereafter the logical address and physical address are not equal. In order to map out the single memory block D1212D, the logical address for logical bit sequence from 1536 k-bit to (MAX-512 K)-bit is shifted by 512 k bits to obtain the physical address. For example, the logical address (192 k-word) for logical bit 1536 k is mapped to the physical address (256 k-word) for physical bit 2048 k. In this manner, the software can see a continuous contiguous memory space even though a block of memory has been removed.

Referring now toFIG. 5, an exemplary reconfigurable memory102′, the test access port104, the BIST controller106, and the memory test register108are illustrated. The reconfigurable memory102′ has four clusters, cluster210AA, cluster210AB, cluster210BA, and cluster210BB. Each of the memory clusters210includes memory block A, memory block B, memory block C, and memory block D. The reconfigurable memory102′ in one embodiment is organized into sixteen (16) memory blocks each having five-hundred-twelve (512) kilobits, containing a maximum capacity of eight (8) megabits. The reconfigurable memory102′ further includes the reconfigurable memory controller204.

The serial test access port104includes a TAP controller502coupled to the BIST controller106. The memory test register108includes a pass/fail indicator504A–504N for each memory block of each cluster within the reconfigurable memory102′. The pass/fail indicators504A–504N are labeled inFIG. 5as CL1MBA504A for cluster1, memory block A through CL4MBD504N for cluster4, memory block D. The memory test register108further includes a BIST (built-in self tester) done indicator506and a BIST start indicator508. The BIST done indicator506is generally a flag to indicate that the built-in self test of the reconfigurable memory102′ has been completed or not. The BIST start indicator508is used to kick off the memory test. Each pass/fail indicator504A–504N within the memory test register108is set to indicate whether the corresponding memory block has passed or failed testing. In one embodiment, each of the pass/failed indicators504A–504N, the BIST done indicator506, and the BIST start indicator508is represented using a 1-bit value.

In order to test the reconfigurable memory102′, the BIST controller106generates test signals. Test signals generated by the BIST controller106strobe the Read/Write signal line205, signal addresses on the address bus207, and writes test data on the data input bus208. The BIST controller106further reads out data from memory locations within the reconfigurable memory array102′ over the data output bus209. The BIST controller106compares expected data output from the reconfigurable memory with the actual data output on the data output bus209. The expected data output is predetermined from the type of memory test and the respective test signals which are provided to the reconfigurable memory. One or more known memory tests, such as a March test, can be used in testing the reconfigurable memory.

The BIST controller106sets the pass/fail indicators504A–504N within the memory test register108indicating either a pass or fail for each respective memory block based on the comparison between expected data output and the actual data output. The BIST controller106further indicates to the TAP controller502whether a memory block has passed or failed testing so that it can be externally signaled out through the serial test access port104as well. Upon completion of the testing of the reconfigurable memory, the BIST controller106sets the BIST done indicator506indicating that testing is completed.

The memory test register108is externally accessible by a host system through the host port107. The access to the memory test register108can be I/O mapped or memory mapped within the integrated circuit100. As further explained herein, a host system also has access to the reconfigurable memory controller204through the host port107to set registers therein for controlling the mapping out of memory blocks having bad memory cells. After completion of testing, the host system may desire to set registers within the reconfigurable memory controller204to control addressing of the reconfigurable memory102.

Referring now toFIG. 6, an instance of a memory block212is illustrated. Each memory block212includes an array of memory cells600, an address decoder602and a bus driver/receiver604. A word of memory cells can be accessed within the array of memory cells600of the memory block212. Each word of memory within the memory block212is W bits wide. In one embodiment, a word is 64-bit wide and can be obtained in one access.

There are “N” memory blocks212within the reconfigurable memory102while there are “M” clusters210. The use of “n” and “m” with a reference number represents an instance of each. Each memory block212in a cluster210receives a chip select signal CS216nof the chip select signals CS216and a read/write strobe R/W215nof the read write strobes R/W215. Each memory block212in a cluster210further couples to the address bus217m,the data in bus218mand the data out bus219mfor the respective cluster. That is, there are N chip select signals CS216and N read/write strobes R/W215respectively one for each CS216nand one for each R/W215n.There are M address buses217, M data in buses218, and M data out buses219respectively one for each address bus217m,data in bus218mand data out bus219m.

The array of memory cells600in the memory block212are organized into columns and rows. The address decoder602can include a row address decoder and a column address decoder in order to access the memory cells and read or write data therein. The bus driver/receiver604includes a sense amplifier array and latches in order to read data out from memory cells selected by the address decoders and store it into the latches. The bus driver/receiver604further includes a driver to drive data which is stored in the latches onto the data bus219. Another set of latches can also store data off of the data in bus218mthat is to be written into the memory block212.

Each chips select signal CS216nis an enable or activate signal that enables access to each respective memory block212and is derived from the upper bits of the address bus217n.The lower bits of the address bus217nfurther addresses a word or words within the array of memory cells600in the enabled memory block212of a respective memory cluster210. The read/write strobe R/W215nindicates whether data on the data in bus218mis to be written into the memory block212or if data is to be read out from the memory cells600onto the data out bus219m.

Referring now toFIG. 7, the reconfigurable memory controller204includes an array of configuration registers702A–702N. Each configuration register702A–702N includes an enable bit704and a chip select base address706and is associated with a respective memory block212in the reconfigurable memory102. The chip select base address706allows the addressing for a memory block212to be selectively offset in order to start addressing the memory block at a different address. This allows blocks with bad memory cells to be worked around. The value of the chip select base address706can be anything and need not be limited to establish a linear address space. A non-linear address space can be utilized for some reason. It should be noted that the chip set base address706can also be referred to as a memory block base address.

Each configuration register702A–702N can be loaded in parallel through the host port107. The information stored within the enable bit704in each configuration register702A–702N, is utilized by the address mapping logic within the reconfigurable memory controller to map out unusable blocks or unusable memory cells. The information stored within the chip select base address706in each configuration register702A–702N can be used to provide a continuous linear memory space of logical addressing. Alternatively, the information stored within the chip select base address706in each configuration register702A–704N can be used to provide a non-linear memory space of logical addressing. The configuration registers702A14702N are usually loaded after the reconfigurable memory102has been tested. During reset of the integrated circuit, such as during power on reset, the enable bit704in each configuration register is set so as to enable access to each memory block212for testing. The information stored within the chip select base address706of each configuration register is defaulted to provide access and test each memory cell within the reconfigurable memory102during reset of the integrated circuit. In one embodiment, the default information stored in the chip select base address706of each configuration register provides linear logical addressing and a one to one mapping to physical addressing. The linear logical addressing is provided at default by setting the value of the chip select base addresses706to start at zero for configuration register702A and increment thereon for each of the configuration registers702B to702N. In any case, the default information should allow the total capacity of the reconfigurable memory102to be tested in order to determine which memory cells and memory blocks are unusable.

To reprogram the reconfigurable memory102, software executing on an external host controller or within the integrated circuit100can read the pass/fail information within the test register108and set/clear the enable bit704and the values of the chip select base address706in each configuration register702accordingly for each memory block212. The values of the chip select base address706, the most significant address bits, set by the external host controller can linearize the logical addressing by setting a linear sequence of 0, 1, 2, 3 and so on, incrementing by one. Alternatively, a different logical addressing scheme can be utilized by prograimning the values of the chip select base address706differently.

Referring now toFIG. 8, a detailed block diagram of the reconfigurable memory controller204is illustrated for addressing each of the memory blocks within the reconfigurable memory102. For N memory blocks212, the reconfigurable memory controller204includes N address mappers802A–802N, generally each instance is referred to as address mapper802. The N address mappers802A–802N generate each chip select signal216nand address217nrespectively for each memory block. The bits of the address bus207are split into upper bits and lower bits of the address bus207within each address mapper802. The upper bits of the address bus207are used to generate the chip select or enable for each block of memory while the lower bits of the address bus207are used to generate the address for the memory locations within a memory block212selected by the chip select.

Each of the N address mappers802A–802N include a respective configuration register702A–702N as illustrated. The enable bit704of each configuration register702is coupled into an AND gate804. Each of the chip select base addresses706of each of the configuration registers702is coupled into a bit wise comparator806.

Each enable bit704in each configuration register702controls whether or not the respective memory block212is to be mapped out or not. If the enable bit704is set, the respective memory block212is not mapped out. If the enable bit704is not set, the respective memory block212is mapped out. The enable bit704gates the generation of the chip select signal216n.If the enable bit704is set, the chip select signal216ncan be generated through the AND gate804if the upper addresses match the chip select base address. In this case, the respective memory block212is not mapped out. If the enable bit704is not set, the chip select signal216ncan not be generated through the AND gate804regardless of any address value and the respective memory block212is mapped out.

The upper bits of the address data bus207are coupled into the bit wise comparator806to be compared with the chip select base address706. First, the bit wise comparator806essentially takes a logical exclusive NOR (XNOR) of each respective bit of the upper bits of the address data bus207and the chip select base address706. The comparator then logically ANDs together each of the XNOR results of this initial bit comparison to determine if all the upper bits of the address data bus207match all the bits of the chip select base address706to generate a match output807. If there is any difference in the bits, the match output807is not generated and the respective memory block212is not enabled. The match output807of the bit wise comparator806is coupled into the AND gate804. The output of the AND gate804in each of the address mappers802A–802N is the respective chip select signal216nfor each memory block212in each cluster210.

The lower bits of the address bus207are coupled into a bus multiplexer (MUX)808in each of the address mappers802A–802N. Each of the address mappers802A–802N further includes a register810to store a change in a bus state of each respective address bus217n.The bus multiplexer808and the register810form a bus state keeper812in each address mapper802.

In each address mapper802, the multiplexer808and register810are coupled together as shown in address mapper802A. The output from each respective register810is coupled into an input of each respective bus MUX808in the address mappers802A–802N. The other bus input into the bus multiplexer808is the lower bits of the address bus207. The chip select signal216nfor each respective address mapper802controls the selection made by each respective bus MUX808. In the case that the respective memory block212is to be addressed as signaled by the chip select signal CS216n,then a new address is selected from the lower bits of the address bus207. In the case that the respective memory block212is not to be addressed, then the state of the respective address bus217previously stored within the register801is selected to be output from the MUX808by the chip selected signal CS216n.In this manner, the multiplexer808and register810recycle the same lower bits of address until the respective memory block212is selected for access by the upper bits of the address bus207. Keeping the state of the bus216from changing, conserves power by avoiding a charging and discharging the capacitance of the address bus217nuntil necessary. The operation of each bus state keeper812is similar to that of the bus state keepers902further described below with reference toFIG. 9. The multiplexer808in each of the address mappers is typically controlled by the chip select signals to demultiplex the address bus207into one of the address buses217.

Referring now toFIG. 9, a block diagram of the data input/output control provided by the reconfigurable memory control204for the reconfigurable memory102is illustrated. The reconfigurable memory controller204receives the data bus input208and provides the data bus output209for the reconfigurable memory102. The reconfigurable memory controller204couples to the data input buses218and data output buses219of each memory cluster212to write and read data there between.

The reconfigurable memory controller204includes a bus state keeper902for each cluster212labeled bus state keepers902A–902D, a cluster address decoder904, and a bus multiplexer906. The bus multiplexer906receives as input each of the data out buses219AA–219NN of each cluster212in the reconfigurable memory. It is controlled by a cluster selection control signal from the cluster address decoder904. The output of the bus multiplexer906couples to and generates signals on the data output bus209of the reconfigurable memory102. The embodiment of the bus multiplexer906corresponding to exemplary embodiment ofFIG. 9is a four-to-one bus multiplexer and receives as input each of the data out buses219AA–219BB of each cluster212. InFIG. 9, the data out buses for the four cluster embodiment ofFIG. 5are CL1DBout219AA, CL2DBout219AB, CL3DBout219BA and CL4DBout219BB.

Each of the bus state keepers902includes a two-to-one bus multiplexer912and a register914coupled together as shown by bus state keeper902A inFIG. 9. The data input bus208is coupled into one bus input of each bus multiplexer912and the output of each respective register914is coupled into the other bus input of each respective bus multiplexer912. Each respective register914stores the state of each bit of the respective data input bus218when it changes state. The register914keeps the stored state on the bus218until the state of the respective bus218is to be updated. The state of a respective bus218is updated or changed when the bus multiplexer912is controlled to select the data bus input208as its output onto the bus218. Otherwise, with the bus multiplexer912selecting the output of the register914as its output, the state on the bus218is recirculated when the register914is clocked. In one embodiment, a system clock can be used to clock the register914.

The cluster address decoder904receives all of the chip select signals216for each memory block212of each cluster210and controls each bus multiplexer912in the bus state keepers902and the bus multiplexer906. The chip select signals216are responsive to the upper bits of the address bus and the chip select base address706of a respective configuration register. In response to a selected chip select signal216of a respective memory block, the cluster address decoder904enables data to flow into and out of the respective cluster where the respective memory block resides. In effect, the cluster address decoder904logically ORs the chip select signals216for memory blocks within each cluster together. If any memory block is selected within the cluster, the data paths into and out of that cluster through the reconfigurable memory controller204are enabled. The cluster address decoder904selectively controls the bus multiplexers912of the bus state keepers902to select the data input bus208as its output onto data bus218in response to the chip select signals216. The cluster address decoder904logically controls the bus multiplexers912in all the bus state keepers902as a bus demultiplexer. That is, the data input bus208is selected for output on one of the buses218in response to signals from the cluster address decoder904.

For example, assume that the upper address bits and the chip select base address generates cluster2chip select A to enable access to memory block A in cluster2. The cluster address decoder904generates a cluster2enable signal CL2EN which is coupled into the bus multiplexer912of the bus state keeper902B. This controls the bus multiplexer912in the bus state keeper902B to allow the information on the data input bus208to be transmitted to the cluster2bus data bus input CL2DBIN218AB.

Because the chip select base address706is programmable in each configuration register702, a memory block can be rearranged to be addressed with a different cluster of memory blocks. That is, the memory blocks212can be addressed across cluster boundaries due to the programmability of the chip select base address706and the bus multiplexers912in the bus state keepers902and the bus multiplexer906for the data input and output busses. This allows adaptive control of the addressing of the memory blocks within the reconfigurable memory to achieve any desirable logical address space.

The bus multiplexer906multiplexes the data output buses219from each cluster210into the data output bus209of the reconfigurable memory102. Each bus219of the clusters210is coupled to an input of the bus multiplexer906. The output of the bus multiplexer906is coupled to the data output bus209to generate data signals thereon. Control signals from the cluster address decoder904are coupled into the selection input of the bus multiplexer906to select which cluster data bus output219is multiplexed onto the data bus output209through the reconfigurable memory controller204. The control signals from the address decoder904can be the same or function similar to the cluster enable signals CL1LEN through CL4EN or they may be different in that they are for a read operation as opposed to a write operation. The control signals may also be encoded to control the bus multiplexer906. The control signals select the active cluster where a word of memory in a memory block therein was accessed. For example assume that a word of memory in memory block A of cluster3was accessed by the address during a read operation. The control signals from the cluster address decoder904set up the bus multiplexer906to select the cluster3data bus output as its output onto the data output bus209. In this manner the data read out from a selected memory block in a selected cluster is read out onto the data output bus209or the reconfigurable memory.

Avoiding changes of state in buses can conserve considerable power when the buses have significant capacitive loading. This is particularly true when there are many buses which have capacitive loading or a bus is wide having a high number of bit or signal lines. In the reconfigurable memory102′ for example, there are four input data buses218, four output data buses219, four address buses217, sixteen chip select lines216, and sixteen read/write strobes215between the reconfigurable memory controller204and all the memory blocks212of the memory array202. Each of the data buses218and219have sixty-four signal lines and each of the address buses217have sixteen signal lines in the reconfigurable memory102′. The length of the input data buses218, output data buses219, address buses217, chip select lines216, and read/write strobes215between the reconfigurable memory controller204and all the memory blocks212of the memory array202can also be rather long. The number of signal lines in each bus, the length of routing, and the frequency of changes of a signal on the signal lines affects the amount of power consumption in the reconfigurable memory. While the length of the signal lines is somewhat fixed by the design and layout of the reconfigurable memory, the number of signal lines changing state can functionally be less in order to conserve power. That is, if charges stored on the capacitance of all the signal lines are not constantly dissipated actively to ground or if charges are not constantly added actively to the dissipated capacitance of all the signal lines, power can be conserved within an integrated circuit.

The reconfigurable memory102is organized into memory clusters210and memory blocks212. As a result, not all bit lines within the memory blocks need to change state. Furthermore, only one address bus217and one data input bus218(write) or one data output bus219(read) typically needs to change state between one memory block212and the reconfigurable memory controller204at a time. All other address buses217and data buses218and219can remain in a stable state to conserve power. The address mappers802A–802N generating the chip select signals216, selectively control which input data bus and output data bus are active for one selected cluster. In this manner, power consumption can be reduced because not all bit lines of the data buses for all the clusters need to change state. Their states can be kept by the bus state keepers812and902. The use of the bus state keepers can be generalized to parallel buses between the same two functional blocks, each using a multiplexer and a register to maintain a stable stored state but for the one that is predetermined to change state as indicated by an address or a control signal.