Thin film transistor liquid crystal display structure

A process for manufacturing a thin film transistor liquid crystal display (TFT-LCD) is disclosed. The process can reduce the number of the mask used in the photolithography process to three masks, form a capacitor during the manufacturing process simultaneously, and enhance the transmission rate of the TFT-LCD. Because the pixel electrodes are formed directly on the substrate, without forming an insulator layer in the pixel area, the transmission can be enhanced. The manufacturing process also provides a protective circuit for avoiding electrostatic discharge damage, and a passivation layer to protect the capacitor, the gate line, and the signal line.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates in general to a manufacturing process of a thin film transistor liquid crystal display (TFT-LCD). In particular, the present invention relates to a TFT-LCD manufacturing process using three photolithography process masks.

2. Description of the Related Art

A liquid crystal display (LCD) employing a thin film transistor (TFT) as an active device provides advantages of low power consumption, thin profile, light weight and low driving voltage. However, the TFT process consists of multiple masks in multiple photolithography processes, usually more than seven masks, thereby encountering the problems of poor yield and high cost. In order to improve the problems, reducing the steps of the photolithography process becomes an important issue.

U.S. Pat. No. 5,478,766 discloses a process for forming of a TFT-LCD by multiple photolithography processes using three masks.FIGS. 1Ato1C show top views of the masks used in the TFT-LCD manufacturing process according to the prior art, andFIGS. 2Ato2E are cross-sectional views along the line A-A′ inFIGS. 1Ato1C of the prior art. First, as shown in FIG.1A andFIG. 2A, a first metal layer is deposited on a substrate21, and patterned by a first photolithography process to form a gate electrode22and a gate line (not shown) connected to the gate electrode22. Usually, the metal layer is further oxidized to form a protecting layer23covering the gate electrode22. Then, as shown inFIG. 2B, an insulating layer24, an amorphous silicon layer25and a doped silicon layer26are deposited on the substrate21. Next, as shown inFIGS. 1B and 2C, a second metal layer is deposited on the doped silicon layer26. The second metal layer is then patterned as a signal line27and a source/drain metal layer28by a second photolithography process. AS shown inFIGS. 1C and 2D, an indium tin oxide (ITO) layer is deposited on the substrate21. A photo resist layer (not shown) is then formed above the ITO layer, then the ITO layer is patterned to form a pixel electrode29by a third photolithography process. Finally, as shown inFIG. 2E, the same photo resist layer is used to define the patterns of the source/drain metal layer28and the doped silicon layer26. A source electrode31and a drain electrode32are finally formed.

According to the above process, the masks used in the photolithography process are reduced to three masks; however, an insulating layer24is formed between the pixel electrode29and the substrate21, and the transmission of the display is decreased. Further, the first metal layer and the second metal layer cannot electrically connect for avoiding the damage of electrostatic discharge (ESD) because the insulating layer24is remained on the substrate21. The reliability of the LCD may be poor because of the damage of electrostatic discharge (ESD).

SUMMARY OF THE INVENTION

An object of the present invention is to provide a process for manufacturing a thin film transistor liquid crystal display (TFT-LCD) by three masks, providing a protective circuit to avoid ESD effect, increasing the transmission of the TFT-LCD, and forming a capacitor in the TFT-LCD to solve the above problems.

Another object of the present invention is to provide a process for manufacturing a thin film transistor liquid crystal display (TFT-LCD) with a protective structure to avoid capacitor shorts and shorts between the gate line and the signal line.

In achieving the above objects, the process for manufacturing the thin film transistor liquid crystal display comprises the steps of:(a) providing a substrate having a transistor area, a capacitor area, a pixel area, and a gate pad area;(b) depositing and patterning a first metal layer on the substrate to form a gate electrode, a capacitor upper electrode, and a pad electrode respectively in the transistor area, the capacitor area, and the gate pad area;(c) depositing and patterning an insulating layer, a semiconductor layer, a doped silicon layer and a second metal layer to (1) form an TFT island structure in the transistor area and a capacitor in the capacitor area, and (2) remove the second metal layer, the doped silicon layer, the semiconductor layer and the insulating layer in the pixel area and the gate pad area to expose the substrate in the pixel area and expose the pad electrode in the gate pad area; and(d) depositing a transparent conducting layer, and (1) patterning the transparent conducting layer by defining a channel area in the transistor area, and removing the transparent conducting layer within the channel area, and (2) removing parts of the second metal layer and the doped silicon layer uncovered by the transparent conducting layer so as to define a source electrode and a drain electrode in the transistor area, therefore, the source electrode and the drain electrode being separated by the channel area to expose the semiconductor layer in the channel area.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Please refer toFIGS. 3Ato3C andFIGS. 4Ato4D.FIGS. 3Ato3C show top views of the first embodiment in the present invention.FIG. 3A,FIG. 3B, andFIG. 3Crespectively show the TFT-LCD in the first, second, and third photolithography processes, andFIGS. 4Ato4D are cross-sectional views ofFIGS. 3Ato3C along lines B-B′ and C-C′.

First, a substrate40is provided. The substrate40has a transistor area (area I), a signal line area (area II), a capacitor area (area III), a pixel area (area IV), and a gate pad area (area V). Then, as shown in FIG.3A andFIG. 4A, a first metal layer is deposited on the substrate40, and the first metal layer is patterned to form a gate line34including a gate electrode42, a capacitor bottom electrode44, and a pad electrode46.

As shown in FIG.3B andFIG. 4B, an insulating layer50, a semiconductor layer52, a doped silicon layer54and a second metal layer56are deposited on substrate40, respectively. The second photolithography process is used to pattern the second metal layer56, the doped silicon layer54, the semiconductor layer52, and the insulating layer50so as to define a TFT island structure and a capacitor on the transistor area I and the capacitor are III, respectively. At the same time, the second metal layer56, the doped silicon layer54, the semiconductor layer52, and the insulating layer50are removed from the pixel area IV and the gate pad area V, therefore, the substrate40is exposed in the pixel area IV and the pad electrode46is exposed in the gate pad area V. In the signal line area II, a signal line56is formed, and part of the signal line56overlaps the gate line34as shown in FIG.3B.

As shown in FIG.3C andFIG. 4C, a transparent conducting layer58is deposited on the substrate40. A patterned photo resist layer59is formed on the transparent conducting layer58as a mask. By using the mask, a third photolithography process is performed to pattern the transparent conducting layer58. In this step, a channel area64is first defined in the transistor area I. A part of the transparent conducting layer58is then removed from the channel area64, and the pixel electrodes58e,58d,58bare respectively formed above the TFT island structure and in the pixel area IV. The same photo resist layer59is used to pattern the second metal layer and the doped silicon layer by another etching process. In this step, parts of the second metal layer56and the doped silicon layer54uncovered by the photo resist layer59are removed, and a source electrode60and a drain electrode62are defined in the transistor area I. The source electrode60and the drain electrode62are separated by the channel area64, and the semiconductor layer52is exposed in the channel area64. In this etching process, a time control method is used to control the condition of etching, and therefore, an etching end point of the etching process is defined when the doped silicon layer54is completely removed in the channel area64. In other words, the etching condition of the whole process can be controlled by the etching time of the doped silicon layer54. Finally, photo resist layer59is removed and the manufacturing process is finished.

In order to avoid circuit shorts in the capacitor or between the gate line and signal line, parts of the signal line are wider at the positions361,362where the signal line56overlays the gate line34. Further, the photo resist layer59used to pattern the transparent conducting layer58is also used to pattern the second metal layer56and the doped silicon layer54as shown in FIG.4C. Thus, all of the transparent conducting layer58, the second metal layer56, and the doped silicon layer54have the same pattern. For example, in the capacitor area III, a sidewall581of the transparent conducting layer58is aligned to a sidewall561of the second metal layer56and a sidewall541of the doped silicon layer54, but the sidewall581of the transparent conducting layer58is not aligned to a sidewall521of the semiconductor layer52. Besides, in the signal line area II, the transparent conducting layer58is narrower than the semiconductor layer52and the insulating layer50as shown in FIG.4D. Therefore, if a particle (not shown) falls in the capacitor area III, the second metal layer56will not be electrically connected to the first metal layer44by the particle because the second metal layer56and the first metal layer44have different widths. The probability of the short circuit caused by dropped particles contacting the second metal layer and first metal layer at the same time is reduced.

According to the above description, the advantages of the manufacturing process in the invention include: (1) the number of the mask used in the photolithography process is reduced to three masks, (2) a capacitor can be formed in the manufacturing process simultaneously, and (3) the manufacturing steps of the process is reduced, so the manufacturing throughput is increased. Further, as shown inFIG. 4D, the pixel electrode58bin the pixel area V is formed on the substrate40directly. No insulating layer is formed between the pixel electrode58band the substrate40so the transmission of the TFT-LCD can be greatly enhanced.

In addition, an electrostatic discharge (ESD) protective circuit is also formed around the LCD panel. Please refer to FIG.5A toFIG. 5Cwhich are cross sectional views showing the process for forming the ESD protective circuit. First, as shown inFIG. 5A, a gate line72is formed around the LCD display and is electrically connected to the gate line34and the gate electrode42. A signal line74is further formed as shown in FIG.5B. The insulating layer50, the semiconductor layer52, and the doped silicon layer54are formed between the gate line72and the signal line74, respectively. Finally, a transparent conducting layer58is formed as shown in FIG.5C. The insulating layer50, the semiconductor layer52, and the doped silicon layer54just cover a part of the gate line72so the transparent conducting layer58can be formed above the signal line74and the gate line72at the same time. The gate line72(the first metal layer) and the signal line74(the second metal layer) can thus be electrically connected by the transparent conducting layer58so as to form the protective circuit for ESD protection. Thus, it is unnecessary to form a through hole by remove a part of the insulating layer above the gate line just for allowing the transparent conducting layer to be electrically connected with the gate line and the signal line.

Please refer toFIG. 6which shows a transistor structure of the second embodiment in the present invention. A passivation layer80is formed by a fourth photolithography process as shown in FIG.6. The passivation layer80is a planar layer and covers the pixel electrodes58d,58e, the source electrode60, the drain electrode62and the channel area64. Therefore, the passivation layer80can protect the channel area64, the reliability of channel area64is enhanced, and the whole TFT-LCD surface can be planarized by the passivation layer80.

In the above-mention process, the insulating layer50can be made by silicon nitride and the substrate40is made by silicon oxide, so the etching reactants in the second photolithography process has a high selective ratio for nitride and oxide in order to remove the insulating layer completely. In addition, the semiconductor layer52is an amorphous silicon layer, the doped silicon layer54is a n type amorphous silicon layer, and the transparent conducting layer58is made by indium Tin Oxide (ITO) layer.