Oscillation circuit, voltage controlled oscillator, and serial data receiver

An oscillation circuit includes: an oscillator configured to generate N phase clocks (where N is an integer of 2 or more) including a first phase clock to Nth phase clock whose phases are shifted by 360°/N at regular intervals; a pulse generating part configured to receive a plurality of the N phase clocks and generate a plurality of intermediate pulses each having a duty ratio of 25%; and a clock synthesizing part configured to synthesize the plurality of intermediate pulses to generate a single phase output clock or multi-phase output clocks, the single phase output clock and the multi-phase output clocks having a frequency that is twice an oscillation frequency of the oscillator.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-103094, filed on May 20, 2015, the entire contents of which are incorporated herein by reference.

TECHNICAL FIELD

The present disclosure relates to an oscillation circuit.

BACKGROUND

A great deal of digital circuits includes an oscillator for generating a clock. Recently, as an amount of data handled by digital circuits grows, an oscillation frequency of an oscillator has been on the increase. For example, since a data rate of a transmitter that transmits serially transmitted image data or a receiver that receives serially transmitted image data reaches even up to 5 Gbps, a frequency of a few GHz is required as a clock for sampling.

An LC oscillator or a ring oscillator has been used as an oscillator. The LC oscillator easily generates a clock of a few GHz. However, the integration of an inductor on a semiconductor substrate requires a high frequency process, increasing costs. Further, since inductance is fixed, it is difficult to vary an oscillation frequency.

Meanwhile, the ring oscillator is configured by arranging a delay circuit as a base in a ring shape and is configured through a CMOS process or BiCMOS process, which is thus advantageous in terms of costs. In addition, by changing the bias condition of the delay circuit, a delay time thereof can be changed to vary an oscillation frequency.

The ring oscillator is configured by using a plurality of delay circuits connected in multiple stages, and a clock frequency is increased as a delay amount of each of the delay circuits is reduced. However, there is a restriction in a delay amount of the delay circuits that can be configured through a general semiconductor manufacturing process and it is difficult to generate a clock of a few GHz.

SUMMARY

The present disclosure provides some embodiments of an oscillator capable of generating a high speed clock.

According to one embodiment of the present disclosure, there is provided an oscillation circuit. The oscillation circuit includes: an oscillator configured to generate N phase clocks (where N is an integer of 2 or more) including a first phase clock to Nth phase clock whose phases are shifted by 360°/N at regular intervals; a pulse generating part configured to receive a plurality of the N phase clocks and generate a plurality of intermediate pulses each having a duty ratio of 25%; and a clock synthesizing part configured to synthesize the plurality of intermediate pulses to generate a single phase output clock or multi-phase output clocks, the singles phase output clock and the multi-phase output clocks having a frequency that is twice an oscillation frequency of a ring oscillator.

According to this embodiment, it is possible to generate a high speed output clock having a frequency that is twice that of the original oscillator.

In some embodiments, the pulse generating part may be configured to generate one intermediate pulse from a pair of clocks that are 90° out of phase with each other.

In the pulse generating part, a positive edge and a negative edge of the intermediate pulse may be based on an edge having the same polarity of the pair of clocks as a basis of the intermediate pulse. Thus, even when a duty ratio of a multi-phase clock is changed or fluctuates, a duty ratio of an intermediate pulse is hardly affected.

In some embodiments, the pulse generating part may be configured to invert one of the pair of clocks and perform a logical product of an inverted clock and the other clock to generate one intermediate pulse. Alternatively, the pulse generating part may be configured to invert one of the pair of clocks and perform a negative logical sum of an inverted clock and the other clock to generate one intermediate pulse. Thus, a positive edge and a negative edge of the intermediate pulse can be defined by an edge having the same polarity of a pair of clocks.

In some embodiments, the clock synthesizing part may be configured to perform a logical sum of a pair of intermediate pulses that are 180° out of phase to generate one output clock.

In some embodiments, the ring oscillator may be configured to generate four phase clocks CLKA0to CLKA3whose phases are shifted by 90°. The pulse generating part may be configured to generate a first intermediate pulse CLKB0based on a first phase clock CLKA0and a second phase clock CLKA1of the four phase clocks, and a second intermediate pulse CLKB2based on a third phase clock CLKA2and a fourth phase clock CLK3of the four phase clocks. The clock synthesizing part may be configured to generate a first output clock CLKC0based on the first intermediate pulse CLKB0and the second intermediate pulse CLKB2.

In some embodiments, the pulse generating part may be configured to generate a third intermediate pulse CLKB1based on the second phase clock CLKA1and the third phase clock CLKA2of the four phase clocks, and a fourth intermediate pulse CLKB3based on the fourth phase clock CLKA3and the first phase clock CLKA0of the four phase clocks. The clock synthesizing part may be configured to generate a second output clock CLKC1based on the third intermediate pulse CLKB1and the fourth intermediate pulse CLKB3.

The oscillator may be configured to generate four phase clocks CLKA0to CLKA3whose phases are shifted by 90°. The pulse generating part may include: a first AND gate configured to generate a logical product of a first phase clock CLKA0of the four phase clocks and an inverted signal of a second phase clock CLKA1; and a second AND gate configured to generate a logical product of a third phase clock CLKA2of the four phase clocks and an inverted signal of a fourth phase clock CLKA3. The clock synthesizing part may include a first OR gate configured to generate a logical sum of an output of the first AND gate and an output of the second AND gate.

The pulse generating part may further include: a third AND gate configured to generate a logical product of the second phase clock CLKA1of the four phase clocks and an inverted signal of the third phase clock CLKA2; and a fourth AND gate configured to generate a logical product of the fourth phase clock CLKA3of the four phase clocks and an inverted signal of the first phase clock CLKA0. The clock synthesizing part may further include a second OR gate configured to generate a logical sum of an output of the third AND gate and an output of the fourth AND gate.

In some embodiments, the ring oscillator may be configured to generate eight phase clocks CLKA0to CLKA7whose phases are shifted by 45°. The pulse generating part may be configured to generate a first intermediate pulse CLKB0based on a first phase clock CLKA0and a third phase clock CLKA2of the eight phase clocks and a second intermediate pulse CLKB4based on a fifth phase clock CLKA4and a seventh phase clock CLKA6of the eight phase clocks, and the clock synthesizing part may be configured to generate a first output clock CLKC0based on the first intermediate pulse CLKB0and the second intermediate pulse CLKB4.

In some embodiments, the pulse generating part may be configured to generate a third intermediate pulse CLKB2based on the third phase clock CLKA2and the fifth phase clock CLKA4of the eight phase clocks and a fourth intermediate pulse CLKB6based on the seventh phase clock CLKA6and the first phase clock CLKA0of the eight phase clocks, and the clock synthesizing part may be configured to generate a second output clock CLKC2based on the third intermediate pulse CLKB2and the fourth intermediate pulse CLKB6.

In some embodiments, the pulse generating part may be configured to generate a fifth intermediate pulse CLKB1based on the second phase clock CLKA1and the fourth phase clock CLKA3of the eight phase clocks and a sixth intermediate pulse CLKB5based on the sixth phase clock CLKA5and the eighth phase clock CLKA7of the eight phase clocks, and the clock synthesizing part may be configured to generate a third output clock CLKC1based on the fifth intermediate pulse CLKB1and the sixth intermediate pulse CLKB5.

In some embodiments, the pulse generating part may be configured to generate a seventh intermediate pulse CLKB3based on the fourth phase clock CLKA3and the sixth phase clock CLKA5of the eight phase clocks and an eighth intermediate pulse CLKB7based on the eighth phase clock CLKA7and the second phase clock CLKA1of the eight phase clocks, and the clock synthesizing part may be configured to generate a fourth output clock CLKC3based on the seventh intermediate pulse CLKB3and the eighth intermediate pulse CLKB7.

In some embodiments, the ring oscillator may be configured to generate eight phase clocks CLKA0to CLKA7whose phases are shifted by 45°. The pulse generating part may include: a first AND gate configured to generate a logical product of a first phase clock CLKA0of the eight phase clocks and an inverted signal of a third phase clock CLKA2; a second AND gate configured to generate a logical product of the third phase clock CLKA2of the eight phase clocks and an inverted signal of a fifth phase clock CLKA4; a third AND gate configured to generate a logical product of the fifth phase clock CLKA4of the eight phase clocks and an inverted signal of a seventh phase clock CLKA6; and a fourth AND gate configured to generate a logical product of the seventh phase clock CLKA6of the eight phase clocks and an inverted signal of the first phase clock CLKA0. The clock synthesizing part may include: a first OR gate configured to generate a logical sum of an output of the first AND gate and an output of the third AND gate; and a second OR gate configured to generate a logical sum of an output of the second AND gate and an output of the fourth AND gate.

In some embodiments, the pulse generating part may include: a fifth AND gate configured to generate a logical product of a second phase clock CLKA1of the eight phase clocks and an inverted signal of a fourth phase clock CLKA3; a sixth AND gate configured to generate a logical product of the fourth phase clock CLKA3of the eight phase clocks and an inverted signal of a sixth phase clock CLKA5; a seventh AND gate configured to generate a logical product of the sixth phase clock CLKA5of the eight phase clocks and an inverted signal of an eighth phase clock CLKA7; and an eighth AND gate configured to generate a logical product of the eighth phase clock CLKA7of the eight phase clocks and an inverted signal of the second phase clock CLKA1. The clock synthesizing part may include: a third OR gate configured to generate a logical sum of an output of the fifth AND gate and an output of the seventh AND gate; and a fourth OR gate configured to generate a logical sum of an output of the sixth AND gate and an output of the eighth AND gate.

In some embodiments, the oscillator may include differential type even number stage delay circuits connected to form a ring shape.

According to another embodiment of the present disclosure, there is provided a voltage controlled oscillator (VCO) including any one of the oscillation circuits described above.

According to still another embodiment of the present disclosure, there is provided a serial data transmitter including any one of the oscillation circuits described above.

According to a further embodiment of the present disclosure, there is provided a serial data receiver including any one of the oscillation circuits described above.

Also, arbitrarily combining the foregoing components or converting the expression of the present disclosure among a method, an apparatus, and the like is also effective as an embodiment of the present disclosure.

DETAILED DESCRIPTION

Embodiments of the present disclosure will be now described in detail with reference to the drawings. Like or equivalent components, members, and processes illustrated in each drawing are given like reference numerals and a repeated description thereof will be properly omitted. Also, the embodiments are presented by way of example only, and are not intended to limit the present disclosure, and any feature or combination thereof described in the embodiments may not necessarily be essential to the present disclosure.

In the present disclosure, “a state where a member A is connected to a member B” includes a case where the member A and the member B are physically directly connected or even a case in which the member A and the member B are indirectly connected through any other member that does not affect an electrical connection state thereof. Similarly, “a state where a member C is installed between a member A and a member B” also includes a case where the member A and the member C or the member B and the member C are indirectly connected through any other member that does not affect an electrical connection state, in addition to a case in which the member A and the member C or the member B and the member C are directly connected.

FIG. 1is a block diagram of an oscillation circuit200according to an embodiment. The oscillation circuit200includes an oscillator210, a pulse generating part220, and a clock synthesizing part230.

The oscillator210generates N phase clocks (where N is an integer of 2 or more) including first phase clock CLKA0to Nth phase clock CLKA(N−1) whose phases are shifted by 360°/N at regular intervals.

The pulse generating part220receives a plurality of the N phase clocks CLKA0to CLKA(N−1) and generates a plurality of M intermediate pulses CLKB0to CLKB(M−1) each having a duty ratio of 25%. Here, M is an integer of 2 or more.

The pulse generating part220generates one intermediate pulse CLKBk based on a pair of clocks CLKAi and CLKAj that are 90° out of phase with each other, where i and j are integers (where 0≤i≤N−1 and 0≤j≤N−1). Also, k is an integer (where 0≤k≤M−1).

A positive edge and a negative edge of the intermediate pulse CLKBk may be defined according to an edge (here, a positive edge) having the same polarity of the pair of clocks CLKAi and CLKAj as a basis thereof.

The clock synthesizing part230synthesizes a plurality of intermediate pulses CLKB to generate a single phase output clock CLKC0having a frequency that is twice the oscillation frequency of the oscillator210or multi-phase (R phase) output clocks CLKC0to CLK(R−1). Here, R is an integer of 2 or more.

For example, the clock synthesizing part230performs a logical sum (OR) of a pair of intermediate pulses CLKBp and CLKBq that are 180° out of phase with each other to generate one output clock CLKCs. Here, p and q are integers (where 0≤i≤M−1 and 0≤j≤M−1). Also, s is an integer (where 0≤s≤R−1).

The basic configuration of the oscillation circuit200has been described above. Next, an operation thereof will be described. Here, the cases of N=4, M=4, and R=2 will be described to help in understanding and simplifying the description.

FIG. 2is an operational waveform view of the oscillation circuit200ofFIG. 1. The oscillator210generates four phase clocks CLKA0to CLKA3. Upon receipt of the four phase clocks CLKA0to CLKA3, the pulse generating part220generates a plurality of (here, four) intermediate pulses CLKB0to CLKB3.

The pulse generating part220generates a first intermediate pulse CLKB0based on a first phase clock CLKA0and a second phase clock CLKA1of the four phase clocks, and generates a second intermediate pulse CLKB2based on a third phase clock CLKA2and a fourth phase clock CLKA3of the four phase clocks. The clock synthesizing part230generates a first output clock CLKC0based on the first intermediate pulse CLKB0and the second intermediate pulse CLKB2.

Also, the pulse generating part220generates a third intermediate pulse CLKB1based on the second phase clock CLKA1and the third phase clock CLKA2of the four phase clocks, and generates a fourth intermediate pulse CLKB3based on the fourth phase clock CLKA3and the first phase clock CLKA0of the four phase clocks. The clock synthesizing part230generates a second output clock CLKC1based on the third intermediate pulse CLKB1and the fourth intermediate pulse CLKB3.

The operation of the oscillation circuit200has been described above. According to this oscillation circuit200, it is possible to generate the output clocks CLKC0and CLKC1having a period TCof half the oscillation period TAof the oscillator210, i.e., having a double frequency.

Further, the output clocks CLKC0and CLKC1may be recognized as 2-phase clocks whose phases are shifted by 180° (½ period). Only one of them may be required according to applications. In this case, the function of generating the CLKC0(or CLKC1) of the other side may be omitted.

The present disclosure is recognized by the block diagram and circuit diagram ofFIG. 1, and encompasses various devices and circuits derived from the above description and is not limited to a specific configuration. Hereinafter, a more specific configuration example will be described in order to facilitate and clarify understanding of the essence and circuitry operation of the disclosure, rather than to narrow the scope of the present disclosure.

First Embodiment

FIG. 3is a circuit diagram of the oscillation circuit200according to a first embodiment. The oscillator210generates four phase clocks CLKA0to CLKA3whose phase are shifted by 90°. The oscillator210has differential type even number four-stage delay circuits212_1to212_4connected to form a ring shape and comparators214_1and214_2.

The comparator214_1compares differential inputs of a delay circuit212_1at a first stage to output a first phase clock CLKA0representing a comparison result and a third phase clock CLKA2as a logical inversion thereof. The comparator214_2compares differential inputs of a delay circuit212_3at a third stage to output a second phase clock CLKA1representing a comparison result and a fourth phase clock CLKA3as a logical inversion thereof. When the differential inputs of the delay circuits212_1to212_4have steep edges and a driving capacity of the delay circuits212_1to212_4is sufficiently high (output impedance is low), the comparators214_1and214_2may be omitted.

The pulse generating part220includes first AND gate A1to fourth AND gate A4. The first AND gate A1performs a logical product (AND) of the first phase clock CLKA0of the four phase clocks and an inverted signal #CLKA1of the second phase clock CLKA1to generate a first intermediate pulse CLKB0. The second AND gate A2performs a logical product of the third phase clock CLKA2of the four phase clocks and an inverted signal #CLKA3of the fourth clock CLKA3to generate a third intermediate pulse CLKB2. The first intermediate pulse CLKB0and the third intermediate pulse CLKB2are 180° out of phase with each other.

The third AND gate A3performs a logical product of the second phase clock CLKA1of the four phase clocks and an inverted signal #CLKA2of the third phase clock CLKA2to generate a second intermediate pulse CLKB1. The fourth AND gate A4performs a logical product of the fourth phase clock CLKA3of the four phase clocks and an inverted signal #CLKA0of the first clock CLKA0to generate a fourth intermediate pulse CLKB3. The second intermediate pulse CLKB1and the fourth intermediate pulse CLKB3are 180° out of phase with each other.

The clock synthesizing part230includes a first OR gate O1and a second OR gate O2. The first OR gate O1performs a logical sum (OR) of an output CLKB0of the first AND gate A1and an output CLKB2of the second AND gate A2to generate a first output clock CLKC0. Also, the second OR gate O2performs a logical sum of an output CLKB1of the third AND gate A3and an output CLKB3of the fourth AND gate A4to generate a second output clock CLKB1.

According to the oscillation circuit200ofFIG. 3, the double frequency and the two phase output clocks CLKC0and CLKC1may be generated. When a single phase output clock is required, the set of the third AND gate A3, the fourth AND gate A4, and the second OR gate O2may be omitted.

In particular, according to the configuration of the pulse generating part220and/or a method of generating an intermediate pulse, both a positive edge and a negative edge of the intermediate pulse CLKB are defined by a positive edge of the multi-phase clock CLKA. Thus, the intermediate pulse CLKB is advantageous in that it is not affected by a variation in the duty ratio of the multi-phase clock CLKA.

Second Embodiment

Next, the generation of the double frequency and the four phase output clocks CLKC0to CLKC3will be described.FIG. 4is another operational waveform view of the oscillation circuit200ofFIG. 1.

The oscillator210generates eight phase clocks CLKA0to CLKA7whose phases are shifted by 45°. The pulse generating part220receives the eight phase clocks CLKA0to CLKA7and generates a plurality of (here, eight) intermediate pulses CLKB0to CLKB7.

The pulse generating part220generates a first intermediate pulse CLKB0based on the first phase clock CLKA0and the third phase clock CLKA2of the eight phase clocks, and generates a second intermediate pulse CLKB4based on a fifth phase clock CLKA4and a seventh phase clock CLKA6. The clock synthesizing part230generates a first output clock CLKC0based on the first intermediate pulse CLKB0and the second intermediate pulse CLKB4.

The pulse generating part220generates a third intermediate pulse CLKB2based on the third phase clock CLKA2and the fifth phase clock CLKA4, and generates a fourth intermediate pulse CLKB6based on the seventh phase clock CLKA6and the first phase clock CLKA0. The clock synthesizing part230generates a second output clock CLKC2based on the third intermediate pulse CLKB2and the fourth intermediate pulse CLKB6.

The pulse generating part220generates a fifth intermediate pulse CLKB1based on the second phase clock CLKA1and the fourth phase clock CLKA3, and generates a sixth intermediate pulse CLKB5based on a sixth phase clock CLKA5and an eighth phase clock CLKA7. The clock synthesizing part230generates a third output clock CLKC1based on the fifth intermediate pulse CLKB1and the sixth intermediate pulse CLKB5.

The pulse generating part220generates a seventh intermediate pulse CLKB3based on the fourth phase clock CLKA3and the sixth phase clock CLKA5of the eight phase clocks, and generates an eighth intermediate pulse CLKB7based on the eighth phase clock CLKA7and the second phase clock CLKA1of the eight phase clocks. The clock synthesizing part230generates a fourth output clock CLKC3based on the seventh intermediate pulse CLKB3and the eighth intermediate pulse CLKB7.

Another operation of the oscillation circuit200has been described above. According to this oscillation circuit200, it is possible to generate the four phase output clocks CLKC0to CLKC3having a period TCof half the oscillation period TAof the oscillator210, i.e., having a double frequency.

FIG. 5is a circuit diagram of an oscillation circuit200according to a second embodiment. The oscillator210generates eight phase clocks CLKA0to CLKA7whose phases are shifted by 45°. The oscillator210has differential type even number four-stage delay circuits212_1to212_4connected to form a ring shape and comparators214_1to214_4.

The pulse generating part220includes a set of first AND gate A1to fourth AND gate A4and a set of fifth AND gate A5to eighth AND gate A8.

Clocks CLKA0, CLKA2, CLKA4, and CLKA6according to the second embodiment correspond to the clocks CLKA0, CLKA1, CLKA2, and CLKA3of the first embodiment. Thus, the set of first AND gate A1to fourth AND gate A4ofFIG. 5corresponds to the first AND gate A1to fourth AND gate A4ofFIG. 3.

The fifth AND gate A5to eighth AND gate A8are configured in the same manner as the first AND gate A1to fourth AND gate A4to generate intermediate pulses CLKB1, CLKB3, CLKB5, and CLKB7based on clocks CLKA1, CLKA3, CLKA5, and CLKA7.

The clock synthesizing part230has a set of first OR gate O1and second OR gate O2and a set of third OR gate O3and fourth OR gate O4. The set of first OR gate O1and second OR gate O2corresponds to the first OR gate O1and the second OR gate O2ofFIG. 3. The output clocks CLKC0and CLKC2of the second embodiment correspond to the output clocks CLKC0and CLKC1of the first embodiment.

The third OR gate O3generates an output clock CLKC1and the fourth OR gate O4generates an output clock CLKC3.

According to the oscillation circuit200ofFIG. 5, it is possible to generate the double frequency and the four phase output clocks CLKC0to CLKC3ofFIG. 4.

LikeFIG. 3, according to the configuration of the pulse generating part220and/or the method of generating an intermediate pulse ofFIG. 5, both a positive edge and a negative edge of the intermediate pulse CLKB are defined by the positive edge of the multi-phase clock CLKA. Thus, the intermediate pulse CLKB is advantageous in that it is not affected by a variation in a duty ratio of the multi-phase clock CLKA.

Next, applications of the oscillation circuit200will be described. The oscillation circuit200may be used in a serial data receiver, specifically in a clock data recovery (CDR) circuit100.FIG. 6is a block diagram illustrating a configuration of the CDR circuit100according to an embodiment. The CDR circuit100includes a phase comparator10, a frequency comparator20, a selector30, a charge pump circuit40, a loop filter50, a voltage controlled oscillator (VCO)60, and a serial-parallel converter70.

The CDR circuit100receives serial type differential input data DIN+ and DIN− (hereinafter, generally referred to simply as input data DINas necessary). The input data DINincludes a clock signal. The CDR circuit100extracts and reproduces a clock signal from the input data DIN, and receives a value of the input data DINusing the reproduced clock signal.

The CDR circuit100reproduces four phase clock signals CK1to CK4of a ½ frequency of a data rate. Also, the four phase clock signals CK1to CK4are shifted by ¼ period (90°) in phase. The four phase clock signals CK1to CK4are generated by a so-called PLL circuit.

The phase comparator10uses the first clock signal CK1and the third clock signal CK3whose phases are shifted by 180°, among the four phase clock signals CK1to CK4, to obtain two data DOUT1and DOUT2at every period of the clock signals. Specifically, the phase comparator10latches a value of the input data DINat a timing of a positive edge of the first clock signal CK1and determines the value as data DOUT1, and latches the value of the input data DINat a timing of a positive edge of the third clock signal CK3and determines the value as data DOUT2. The data DOUT1and DOUT2are supplied to the serial-parallel converter70at the next stage.FIG. 7is a time chart illustrating the timing of each signal in the CDR circuit100ofFIG. 6.

The serial-parallel converter70receives the serial data DOUT1and DOUT2and the clock signals CK1and CK3synchronized therewith, and converts the same into output parallel data DOUTat the timing of the serial data DOUT1and DOUT2. The serial-parallel converter70outputs the output parallel data DOUTtogether with the clock signal CKOUTsynchronized therewith to a subsequent processing block.

Hereinafter, a configuration regarding the extraction and reproducing of the clock signals CK1to CK4of the CDR circuit100will be described.

The phase comparator10, the charge pump circuit40, the loop filter50, and the VCO60form a so-called phase locked loop (PLL) circuit. Through this PLL circuit, a frequency and a phase of the clock signals CK1to CK4are feedback-controlled such that a timing of an edge of the second clock signal CK2and a timing of an edge of the fourth clock signal CK4correspond to a change point of the input data DIN.

The VCO60oscillates at a frequency that is based on an input control voltage Vcnt2. The VCO60generates four phase clock signals CK1to CK4. For example, the VCO60is a ring oscillator to which four-stage delay elements are connected to form a ring shape. Each of the delay elements is biased by the control voltage Vcnt2, and a delay amount of each of the delay elements is controlled by the control voltage Vcnt2. As a result, the oscillation frequency of the ring oscillator is based on the control voltage Vcnt2. The four phase clock signals CK1to CK4correspond to input signals (or output signals) of the four delay elements.

The VCO60may be configured by using the oscillation circuit200according to the embodiment, specifically, by using the oscillation circuit200ofFIG. 5. That is, in the oscillator210of the oscillation circuit200, a delay amount of the delay circuit212is configured to be variable according to the control voltage Vcnt2. The output clocks CLKC0to CLKC3ofFIG. 5correspond to the four phase clocks CK1to CK4ofFIG. 6.

The phase comparator10receives the input data DINand the clock signals CK1to CK4. The phase comparator10compares a phase of the input data DINwith a phase of each of the clock signals CK1to CK4to generate an up signal UP_A and a down signal DN_A. The up signal UP_A and the down signal DN_A will also be generally referred to as a phase difference signal PD_A.

When a phase of the clock signal CK is behind with respect to the input data DIN, the up signal UP_A is asserted (high level), and when the phase of the clock signal CK is ahead with respect to the input data DIN, the down signal DN_A is asserted.

The phase difference signal PD_A is input to the charge pump circuit40through the selector30. The charge pump circuit40increases a control voltage Vcnt1when the up signal UP_A is asserted, and lowers the control voltage Vcnt1when the down signal DN_A is asserted. The loop filter50is a lag lead filter and adjusts a high frequency component of the control voltage Vcnt1to generate the control voltage Vcnt2. A low pass filter may be used as the loop filter50.

The configuration of the charge pump circuit40is not limited, but it includes, for example, a capacitor, a charge circuit for charging the capacitor according to the up signal UP_A, and a discharge circuit for discharging the capacitor according to the down signal DN_A. The control voltage Vcnt2is output to the VCO60.

When a phase of the clock signal CK is lagged and the up signal UP_A is asserted, a frequency of the clock signal CK is increased due to an increase in the control voltage Vcnt2, and thus, feedback is applied to advance the phase. Conversely, when the phase of the clock signal CK is advanced and the down signal DN_A is asserted, the frequency of the clock signal CK is lowered due to lowering of the control voltage Vcnt2, and thus, feedback is applied to make the phase lagged. As a result, the frequency and phase of the clock signal CK are optimized with respect to a change point (edge) of the input data DIN.

In addition to the PLL circuit described above, the CDR circuit100includes a frequency locked loop (FLL) circuit formed by the frequency comparator20, the charge pump circuit40, the loop filter50, and the VCO60.

The frequency and phase of the clock signals CK1to CK4are feedback-controlled by the FLL circuit such that the periods of the clock signals CK2and CK4correspond to a data period Td of the input data DIN. Also, the loop of the FLL circuit may be omitted.

The first comparator CMP1compares input data DIN+ and DIN− to generate a reference signal Ref. Also, the second comparator CMP2compares the clock signals CK2and CK4to generate a signal Vco. The frequency comparator20compares the reference signal Ref and the signal Vco to generate a phase frequency difference signal PFD corresponding to a phase difference therebetween. The phase frequency difference signal PH) indicates whether a phase of the signal Vco is advanced or lagged with respect to the phase of the reference signal Ref. Like the phase difference signal PD, the phase frequency difference signal PFD includes an up signal UP_B and a down signal DN_B. When the phase of the signal Vco is lagged, the up signal UP_B is asserted, and when the phase of the signal Vco is advanced, the down signal DN_B is asserted.

The phase frequency difference signal PFD is input to the charge pump circuit40through the selector30. The operations of the charge pump circuit40, the loop filter50, and the VCO60are the same as described above. Upon receipt of the phase difference signal PD and the phase frequency difference signal PFD, the selector30generates a control signal (UP/DN).

A frequency and a phase of the clock signals CK1to CK4are feedback-controlled by the FLL circuit such that an interval between a positive edge of the clock signal CK2and a positive edge of the clock signal CK4corresponds to a period of the input data DIN.

The overall configuration of the CDR circuit100has been described above. It is possible to reproduce high speed clock signals CK0to CK3synchronized with the serial data at a high speed of a few GHz by using the oscillation circuit200according to the embodiment in the CDR circuit100.

The present disclosure has been described above based on the embodiments. It is to be understood by those skilled in the art that the embodiments are merely illustrative and may be variously modified by any combination of the components or processes, and the modifications are also within the scope of the present disclosure. Hereinafter, these modifications will be described.

The configuration of the pulse generating part220is not limited to that ofFIG. 3.FIG. 8Ais a circuit diagram of a pulse generating part220aaccording to a first modification. The pulse generating part220aincludes NOR gates NOR1to NOR4instead of the first AND gate A1. Each of the NOR gates performs a negative logical sum (NOR) of an inverted signal of a multi-phase clock CLKA at one side and the multi-phase clock CLKA at the other side to generate an intermediate pulse CLKB. Also, according this modification, it is possible to obtain the same effects as those of the pulse generating parts220ofFIGS. 3 and 5.)

In the embodiment, both the positive edge and the negative edge of the intermediate pulse CLKB are defined by the positive edge of the multi-clock CLKA, but the present disclosure is not limited thereto. That is, the positive edge and the negative edge of the intermediate pulse CLKB may also be defined by the negative edge of the multi-phase clock CLKA. In other words, both the positive edge and the negative edge of the intermediate pulse CLKB may be defined by the common edge having the same polarity of the multi-phase clock.

In this case, the multi-phase pulse input to the AND gates ofFIGS. 3 and 5may be changed.FIG. 8Bis a circuit diagram of a pulse generating part220baccording to a second modification.FIG. 8Cis a circuit diagram of a pulse generating part220caccording to a third modification.

The configurations of the pulse generating part220and the clock synthesizing part230are not limited to those described in the embodiments or modifications, but it is understood by those skilled in the art that various modifications may be designed and those modifications are also included within the scope of the present disclosure.

FIG. 9is an operational waveform view of an oscillation circuit200according to a fourth modification. InFIG. 4, a duty ratio of the intermediate pulse generated by the pulse generating part220is equally 25%, but the present disclosure is not limited thereto. When the N phase clocks CLKA0to CLKA(N−1) are generated by the oscillator210, the pulse generating part220may generate an intermediate pulse having a duty ratio of (100/N) % using a pair of clocks CLKA that are (360/N)° out of phase with each other. In a configuration of the pulse generating part220, the inputs of respective logic gates may be properly changed, like those as described in the embodiments or the modifications.

Upon receipt of the intermediate pulse having a duty ratio of (100/N) %, the clock synthesizing part230generates a single phase or multi-phase output clocks having a 2K-times frequency (where K is a natural number) of the oscillation frequency of the oscillator210.

In the embodiment, the case in which two phase or four phase output clocks are generated has been described as an example, but the technical concept disclosed in the embodiment may also be applied to the cases of generating eight phase clocks, sixteen phase clocks, or any other output clocks, and it is understood by those skilled in the art that these cases are included within the scope of the present disclosure.

The applications of the oscillation circuit200are not limited to the CDR circuit, but it may be used for a serial data transmitter and a serial data receiver of the type in which a clock is transmitted via a clock line.

Although the present disclosure has been described using specific terms based on the embodiments, the embodiments are merely intended to illustrate the principle and applications of the present disclosure and the embodiments may be variously modified and arranged within a range that does not depart from the spirit of the present disclosure defined in the claims.

According to the present disclosure in some embodiments, it is possible to generate a high speed clock.