Method of electrodepositing gold on a copper seed layer to form a gold metallization structure

An electrically conductive barrier layer is formed on a semiconductor substrate such that the barrier layer covers a first device terminal. A seed layer is formed on the barrier layer. The seed includes a noble metal other than gold. The substrate is masked so that a first mask opening is laterally aligned with the first terminal. An unmasked portion of the seed layer is electroplated using a gold electrolyte solution so as to form a first gold metallization structure in the first mask opening. The mask, the masked portions of the seed layer, and the barrier layer are removed. The noble metal from the unmasked portion of the seed layer is diffused into the first gold metallization structure. The first gold metallization structure is electrically connected to the first terminal via the barrier layer.

TECHNICAL FIELD

The present invention generally relates to semiconductor devices and more particularly relates to techniques for forming gold metallization layers that may be connected to one or more semiconductor devices.

BACKGROUND

Metallization layers are commonality utilized in semiconductor applications for electrically connecting one or more semiconductor devices, such as MOSFETs, IGBTs, diodes, etc. For example, a metallization layer may be used in an integrated circuit to electrically connect power and ground potential to individual transistor devices. Further, metallization layers may be used in an integrated circuit as interconnects for the input and output terminals of the transistors. A variety of processing techniques are available for forming semiconductor metallization layers such as electroplating, chemical or physical vapor deposition, etc. Lithography techniques are commonly utilized to provide metallization lines with precisely controlled width and pitch.

In many cases, copper is a preferred material for semiconductor metallization layers. Copper offers low electrical resistance and is therefore conducive to high frequency switching operation of semiconductor devices. Further, copper is advantageous in high power applications because it provides low resistive losses and high thermal conductivity. However, copper metallization lines may be susceptible to reliability issues. Particularly in the case of high-temperature and high-humidity conditions, copper is prone to corrosion, oxidation, and/or electromigration. Unless proper mitigation steps are taken, the risk of electrical short in copper metallization lines (e.g., between a source and drain line) due to copper dendrites and/or cathodic-anodic filamentation (CAF) may be unacceptably high.

Known techniques for mitigating the risk of electrical short in copper metallization lines include forming protective layers that seal the copper and prevent electromigration and/or diffusion of the copper. For example, protective layers formed from materials such as nickel (Ni), palladium (Pd) and gold (Au) may be used to protect and seal copper metallization layers. However, these techniques introduce undesirable expense and complexity to the process.

SUMMARY

According to an embodiment, a method of forming a metallization for electrically connecting one or more semiconductor devices is disclosed. According to the method, an electrically conductive barrier layer is formed on a semiconductor substrate such that the barrier layer covers a first terminal of a device formed in the substrate. A seed layer is formed on the barrier layer. The seed layer extends over the first terminal and includes a noble metal other than gold. The substrate is masked with a mask having a first opening that is laterally aligned with the first terminal such that an unmasked portion of the seed layer is exposed by the first opening and such that a masked portion of the seed layer is covered by the mask. The unmasked portion of the seed layer is electroplated using a gold electrolyte solution so as to form a first gold metallization structure arranged in the first mask opening. The mask is removed and the masked portions of the seed layer and the barrier layer are removed. The noble metal from the unmasked portion of the seed layer is diffused into the first gold metallization structure. The first gold metallization structure is electrically connected to the first terminal via the barrier layer.

According to an embodiment, a method of forming a gold metallization structure by electrodeposition using a copper seed layer is disclosed. According to the method, an electrically conductive barrier layer covering a surface of a semiconductor substrate is formed. The substrate includes a source and drain terminal of a semiconductor device. A continuous portion of the barrier layer contacts the source and drain terminals. A copper seed layer is formed such that a continuous seed layer portion covers the continuous portion of the barrier layer. The seed layer is masked with a mask having first and second openings that are laterally aligned with the source and drain terminals. Unmasked portions of the seed layer are electroplated using a gold electrolyte solution so as to form first and second gold metallization structures arranged in the first and second mask openings. The mask is removed. The masked portions of the seed layer and the barrier layer are removed so as to electrically isolate the first and second gold metallization structures. Copper atoms from the seed layer are diffused into the first and second gold metallization structures such that respective interfaces between the barrier layer and the first and second gold metallization structures are substantially devoid of metallic copper. The first and second gold metallization structures are electrically connected to the first and second terminals, respectively.

According to an embodiment, a semiconductor device is disclosed. The semiconductor device includes a substrate having first and second terminals of one or more semiconductor devices. First and second barrier metal regions are electrically connected to the first and second terminals, respectively. First and second gold metallization structures are electrically connected to the first and second terminals via the first and second barrier metal regions, respectively. The first and second gold metallization structures include diffused copper atoms. Interfaces between the first and second barrier metals and the first and second gold metallization structures, respectively, are substantially devoid of metallic copper.

DETAILED DESCRIPTION

Embodiments disclosed herein include a method of forming a gold metallization structure, such as a power line or interconnect line that is electrically connected to one or more semiconductor devices. The gold metallization structure is formed by an electroplating using a photolithography mask to define the geometry of the metallization lines. The seed layer is formed from a noble metal other than gold, such as copper. After the electroplating process, portions of the seed layer are removed, e.g., by etching. The remaining metallic portion of the seed layer underneath the gold metallization structure is diffused into the gold structure. As a result, the device is substantially devoid of the seed layer in its metallic state.

Advantageously, the embodiments disclosed herein provide an electroplated gold metallization line that is resistant to electromigration and/or diffusion, while using a seed layer material other than gold (e.g., copper) that is easily and reliably etched away. Although gold seed layers may be used to form an electroplated gold metallization line, a drawback of this technique is that the removal of the seed layer (e.g., by etching with aqua regia) often leads to redeposition of metallic gold. This presents a high risk of electrical short. An alternative to electroplating is an evaporation and resist-lift-off technique. However, minimum structure widths and distances required for modern semiconductor device metallizations (e.g., below 30 μm) may be difficult or impossible to achieve using resist-lift-off techniques.

By using copper as a seed layer, most of the copper material can be easily removed from the device, e.g., by wet-chemical etch techniques, with a low likelihood of redeposition. The remaining copper in the device can be diffused into the gold structures. As a result, the gold structures include diffused copper atoms, but there is little to no metallic state bulk copper that is at risk of corrosion, oxidation or electromigration. That is, the processes described herein utilize copper as a seed layer, but the copper is rendered inert by a diffusion step. Further, by using an electroplating process with a copper seed layer, the embodiments described herein can be easily and cost-effectively implemented into existing copper electroplating process technologies, e.g., by selecting the appropriate electrolyte solution.

Referring toFIG. 1, a semiconductor substrate100is depicted. The semiconductor substrate100may be formed from any commonly known semiconductor material, such as silicon (Si), silicon carbide (SiC), germanium (Ge), a silicon germanium crystal (SiGe), gallium nitride (GaN), gallium arsenide (GaAs), and the like. The semiconductor substrate100may be a bulk substrate or alternatively may include one or more epitaxially grown layers102.

One or more semiconductor devices are formed in the substrate100. The semiconductor devices may be any device requiring electrical connection. Examples of such semiconductor devices MOSFETs, IGBTs, diodes, etc. Terminals of the semiconductor devices are exposed from the substrate. That is, the semiconductor substrate100ofFIG. 1is formed with at least one semiconductor device that is ready for electrical connection to a metallization layer. This may be done according to known techniques. The terminal may be an input terminal or output terminal of the device, such as a source region, a drain region, a gate electrode, an emitter region, a collector region, etc. The terminal may be a region of semiconductor material or an electrical conductor formed in the substrate.

According to an embodiment, the substrate100includes a power transistor (e.g., an IGBT) with first and second terminals104,106that are source and drain regions of the power transistor. According to an embodiment, contract trenches110extend from the main surface108of the substrate100to first and second terminals104,106so as to expose the first and second terminals104,106. The first and second terminals104,106are laterally separated from one another. As used herein, a lateral direction refers to a direction that is parallel to a main surface108of the semiconductor substrate100.

Referring toFIG. 2, a barrier layer112is formed on the substrate100. The barrier layer112is formed from an electrically conductive material that is configured to prevent electromigration of an adjoining metal conductor (e.g., copper). For example, the barrier layer112may be formed from tantalum (Ta), tantalum-nitride (TaN), titanium (Ti), titanium-nitride (TiN), titanium-tungsten (TiW), and the like. According to an embodiment, the barrier layer112is between 0.01-1 μm thick. The barrier layer112may be formed by a deposition technique (e.g., sputtering, evaporation-or chemical vapor deposition), for example.

The barrier layer112is formed along the surface108of the substrate100and covers at least one of the first and second terminals104,106. As shown inFIG. 2, the barrier layer112covers both the first and second terminals104,106. According to an embodiment, a continuous barrier layer112portion contacts both the first and second terminals104,106and extends along the surface108of the substrate100between the first and second terminals104,106. Alternatively, one or more intervening conductive layers (not shown) may be provided between the barrier layer112and the terminals104,106. Further, other barrier layers (not shown) may be formed on the substrate100, either above or below the depicted barrier layer112. The barrier layer112may be a complete layer that is formed along the entire surface of the substrate100or alternatively may cover only a portion of the substrate100that includes at least one of the terminals104,106.

Also referring toFIG. 2, a seed layer114is formed on the barrier layer112. The seed layer114extends over at least one of the first and second terminals104,106, and may be coextensive with the barrier layer112. That is, the seed layer114may have the same lateral boundaries as the barrier layer112, and may completely cover the substrate100. According to an embodiment, a continuous seed layer114portion covers the continuous barrier layer112portion. Thus, the continuous seed layer114portion is arranged over and extends between the first and second terminals104,106. Further, in embodiments that include the contact trenches110, the continuous portions of the seed layer114and the barrier layer112may extend into these contact trenches.

The seed layer114may be formed from any electrical conductor that is suitable as cathode electrode for an electroplating process. Examples of such conductors include noble metals other than gold such as silver (Ag), platinum (Pt) or palladium (Pd) and copper (Cu). As used herein, the term noble metal refers to a metal that is resistant to chemical action, does not corrode, and is not easily dissolved by acid (e.g., acids associated with an electroplating process). According to an embodiment, the seed layer114is a layer of copper (Cu). The seed layer114may have a thickness of between 0.1-3 μm. The seed layer114may be formed by a deposition technique (e.g., sputtering, evaporation or chemical vapor deposition), for example.

Referring toFIG. 3, the substrate100including the seed layer114and the barrier layer112is masked. According to an embodiment, a photoresist mask116having first and second openings118,120is formed on the substrate100. The photoresist mask116may be formed according to commonly known techniques. The first and second openings118,120are laterally aligned with the first and second terminals104,106, respectively As shown inFIG. 3, the mask116is configured such that unmasked portions of the seed layer114and the barrier layer112, which extend over the first and second terminals104,106, are exposed by the first and second openings118,120, respectively. Likewise, masked portions of the seed layer114are covered by the mask116. In the event that the substrate100includes contact trenches110, the unmasked portions of the seed layer114and barrier layer112are arranged in the contact trenches110.

The mask116may be patterned in any desired geometry. For example, if the substrate100includes a plurality of devices, the mask116may be pattered with openings corresponding to the input and/or output terminals of each device. Furthermore, the minimum geometric features of the photoresist mask116(e.g., minimum widths and pitch) may be adjusted, depending upon the configuration of the devices and the application requirements.

Referring toFIG. 4, an electroplating process is performed. As used herein, electroplating refers to an electrodeposition technique in which the device is submerged in an electrolyte solution and a DC circuit is formed with the device. The DC circuit includes an anode and a cathode placed in an electrolyte solution. Under a DC bias, dissolved metal cations in the electrolyte solution deposit on the cathode. As a result, an essentially pure metal structure develops on the seed cathode.

In the electroplating process of the presently disclosed embodiment, a gold electrolyte solution120, such as a cyanidic or sulfidic solution, is used. An anode122is placed in the gold electrolyte solution120and the seed layer114is used as a cathode of the DC circuit. As a result, essentially pure gold is electrodeposited on the seed layer114. The anode122may be formed from any conductive material that is resistant to corrosion (e.g., platinum). The thickness of the gold that is deposited on the seed layer114depends upon parameters of the electroplating process such as duration, concentration of cations in the electrolyte solution, current flow and geometric parameters, such as open area and arrangement of the semiconductor devices.

In the embodiment ofFIG. 4, the unmasked portions of the seed layer114are electroplated to form first and second gold metallization structures124,126arranged in the first and second mask openings118,120, respectively. Thus, the geometry of the photoresist mask116defines the geometry of gold metallization structures124,126. As shown inFIG. 5, the mask116is subsequently removed from the substrate100.

Referring toFIG. 6, the (previously) masked portions of the seed layer114and the barrier layer112are removed. According to an embodiment, etching techniques are utilized to remove material from the seed layer114and the barrier layer112and consequently remove the (previously) masked portions of the seed layer114and the barrier layer112. For example, both the seed layer114and the barrier layer112may be etched by a wet chemical etching process. Alternatively, the barrier layer112may be etched by a plasma etching process. The etching of the seed layer114and the barrier layer112is selective to gold so that the first and second gold metallization structures124,126remain substantially intact after etching. In the embodiment ofFIG. 6, lateral sections of the seed layer114and the barrier layer112between the first and second gold metallization structures124,126are completely etched away so that the first and second gold metallization structures124,126are electrically isolated from one another. In other words, there is no conductive path between the first and second gold metallization structures124,126through the seed layer114or barrier layer112.

According to an embodiment, the etching process is performed such that portions of the of the seed layer114underneath the first and second gold metallization structures124,126are also etched away. In other words, etching of the seed layer114and the barrier layer112includes etching both the unmasked portions and part of the masked portions. This under-etch at the foundation of the first and second gold metallization structures124,126may be a consequence of etching the seed layer114for a sufficient duration to ensure that all of the seed layer114material between the first and second gold metallization structures124,126is removed, and that the first and second gold metallization structures124,126are electrically isolated from one another.

Referring toFIG. 7, the remaining unmasked portions of the seed layer114are diffused into the first and second gold metallization structures124,126. As a result, the metallic state portions of the seed layer114are effectively eradicated. For example, in the event that the seed layer114is formed from copper, copper atoms disperse into the gold metallization structures124,126. Further, metallic state copper between the gold metallization structures124,126and the barrier layer112is diminished.

According to an embodiment, diffusing the noble metal from the unmasked portion of the seed layer114includes diffusing all of the noble metal between the barrier layer112and the gold metallization structures124,126into the gold metallization structures124,126to form an interface between the barrier layer112and the metallization structures124,126that is substantially devoid of the noble metal in its metallic state. In other words, the diffusion process is controlled so that the gold of the first and second gold metallization structures124,126directly contacts the barrier layer112. In the embodiments in which the seed layer114is formed from copper, this may be achieved by annealing the substrate100with the gold metallization structures124,126and the metallic state copper of the seed layer114at a temperature between 200° and 400° C. for a duration of 10 to 60 minutes so that the copper completely diffuses in to the gold metallization structures124,126.

In the above described methods, the first and second gold metallization structures124,126are electrically connected to the first and second terminals104,106, respectively, via the barrier layer112. That is, a first region of the barrier layer112arranged between the first gold metallization structure124and the first terminal104provides an electrically conductive path. Likewise, a second region of the barrier layer112arranged between the second gold metallization structure126and the second terminal106provides an electrically conductive path. This electrical connection between the terminals104,106and the gold metallization structures124,126is not necessarily exclusively to the barrier layer112, and may be completed through other regions and/or conductive materials

In the above depicted sequence, diffusing the noble metal of the seed layer114is performed after removing the masked portions of the seed layer114and the barrier layer112. As previously explained, all of the material of the seed layer114may be removed except for the portions of the seed layer114arranged underneath the gold metallization structures124,126. Subsequently, all of the remaining seed layer114material (e.g., copper) may be diffused into the gold metallization structures124,126by the diffusion process. In other words, the device may be substantially free of the seed layer114material in its metallic state after the diffusion process.

By diffusing the all of the metallic state copper (in the embodiments that utilize copper as the seed layer114material) into the gold metallization structures124,126, the resulting semiconductor device includes a high-performance metallization that is not susceptible to electrical short due to the effects of electromigration, diffusion, and/or oxidation. The diffusion technique produces gold metallization structures124,126with a percentage of copper. Depending upon the temperature and time conditions of the diffusion process, the copper may be concentrated towards the bottom of the structures124,126. However, this copper is in the form of diffused copper atoms (i.e., dispersed atoms) and not in the metallic state. Further, the interfaces between the first and second terminals104,106and the first and second gold metallization structures124,126, respectively, can be formed to be substantially devoid of metallic copper. In other words, the methods and devices described herein avoid the drawbacks associated with copper, by enveloping the copper from the seed layer114into the gold metallization structures124,126.

By utilizing a patterned electrodeposition technique, advantageous structure widths are possible in the presently disclosed methods. According to an embodiment, a width (W) of the first and second gold metallization structures124,126is less than 10 μm and a separation distance (D) between the first and second gold metallization structures124,126is less than 10 μm. A variety of different dimensions are possible, and the minimum spacing between the metallization structures is determined by the capabilities of the photolithography process.

The device ofFIG. 7may be subsequently processed according to commonly known techniques. For example, a dielectric layer (not shown) that electrically insulates the first and second gold metallization structures124,126from one another may be formed on the substrate100. Higher level metallization layers may be formed on the substrate100as well.

FIGS. 8-9depict an alternate embodiment in which the diffusing the noble metal of the seed layer114is performed prior to removing the masked portions of the seed layer114and the barrier layer112. In this embodiment, the device may be formed according to the process steps disclosed with reference toFIGS. 1-5. Subsequently, a diffusion process such as the process described with reference toFIG. 7is performed. If the seed layer114is formed from copper, the substrate100including the seed layer114and the first and second gold metallization structures124,126may be annealed at temperature between 200° and 400° C. so that all of the metallic state copper underneath the first and second gold metallization structures124,126diffuses away from the interface. Concurrently, gold material from the first and second gold metallization structures124,126laterally diffuses into the masked portions of the seed layer114.FIG. 8depicts an exemplary boundary of the laterally diffused gold. According to an embodiment, the gold diffuses into the seed layer114to a certain lateral distance, depending on temperature and diffusion duration. For example, the gold may be laterally diffused into the seed layer by a distance of 0.3-0.5 μm.

As shown inFIG. 9, the masked portions of the seed layer114and the barrier layer112are subsequently removed. The seed layer114may be removed by a wet chemical etch and the barrier layer112may be removed by a wet chemical etch or a plasma etch, for example. One advantage of the process sequence ofFIGS. 8-9is increased mechanical stability of the metallization structures124,126. This increased mechanical stability arises due to the laterally diffused gold, which expands the foundation of the metallization structures124,126.

The term “substantially” encompasses absolute conformity with a requirement as well as minor deviation from absolute conformity with the requirement due to manufacturing process variations, assembly, and other factors that may cause a deviation from the ideal. Provided that the deviation is within process tolerances so as to achieve practical conformity, the term “substantially” encompasses any of these deviations. For example, a “substantially” pure metal may include a very low percentage of alloy metal atoms, but nonetheless provides the desired qualities (e.g., electrical resistance, resistance to corrosion, etc.) of a pure metal in a semiconductor device. Likewise, an interface that is substantially devoid of the noble metal in its metallic state may have a small percentage of noble metal in the metallic state, so long as this amount is within acceptable process tolerances and the risk of electrical short attributable to the metallic state noble metal is negligible or non-existent.

Within this specification the terms “in electrical contact,” “electrically connected,” “in low resistive electric contact,” “electrically coupled,” “in low ohmic contact,” and “in low resistive electric connection” are used synonymously. Likewise, the terms “in resistive electric contact,” “in ohmic contact,” and “in resistive electric connection” are used synonymously within this specification.