Finite state machines

An example finite state machine may include a content-addressable memory. The content-addressable memory may include blocks that respectively store input-terms of the finite state machine. The finite state machine may be configured to, for each received input: select a subset of the blocks of the content addressable memory to enable for searching, the subset being selected based on a current state of the finite state machine, and determine a next state of the finite state machine by searching the currently enabled subset of blocks of the content addressable memory based on the input.

BACKGROUND

A finite-state machine (FSM) (also known as a finite-state automaton (FSA), finite automaton, or state machine) is a machine that can assume a finite set of states (one state at a time), and changes from one of these states to another in response to received inputs. The FSM may be defined, for example, by a list of its possible states, its initial state, and conditions for transitioning from one state to another. Some FSMs may make use of content addressable memory (CAM), which may include, in some examples, ternary content addressable memory (TCAM).

CAM is a type of memory that can perform a search operation in which a data string may be input as search content and the resulting output is an address or other content-associated data of a location in the memory that stores matching data (if there is any). This is in contrast to a read operation in which an address is input and the resulting output is the data stored in the memory location corresponding to the searched address. Certain CAMs may be able to perform both the aforementioned search operation and the aforementioned read operation, while non-CAM memories may be able to perform the read operation but not the search operation.

TCAM is a type of CAM in which the bit cells can store a wildcard data value in addition to two binary data values. When a bit cell that stores the wildcard value is searched, the result is a match regardless of what search criterion is used to search the bit cell. Certain TCAMs may also allow a search to be conducted on the basis of a wildcard search criterion. When a bit cell is searched based on the wildcard search criterion, the result is a match regardless of what value is stored in the bit cell.

DETAILED DESCRIPTION

1. Example Finite State Machines—Overview

Example FSMs described herein may include a CAM and another memory (such as a random access memory), which together may be used to determine state transitions of the FSM in response to received inputs. For example, the CAM may store terms that the FSM will recognize as valid inputs for each possible state of the FSM, and for each of these input terms the memory may store a corresponding state identifier. In such an example, when an input term is received, the FSM may determine what its next state should be by searching the CAM based on the input term and then reading the storage block of the memory that corresponds to the storage block of the CAM that matched the search. For example, when the CAM is searched, if the third storage block of the CAM matches the input term, then the third storage block of the memory may be read and the next state of the FSM may be the state identified in the third storage block of the memory.

In some examples, the storage blocks of the memory that store state identifiers may also store additional information associated with the state, such as an instruction. The instruction may cause the FSM to perform a particular action as a result of reaching the state. For example, if the fourth storage block of the memory stores the state identifier “3” and an instruction to clear a specified variable, then when the fourth storage block of the memory is read in response to an input term the FSM may transition to the state “3” and clear the specified variable.

In operation, the example FSM may receive a stream of multiple input terms, and may search the CAM and read the memory successively for each received input term, changing states along the way. Thus, the FSM may transition through a number of states until the input stream ends and/or the FSM reaches a terminal state. At termination, the state of the FSM may be indicative of something, such as whether the input stream was “accepted” or “rejected” by the FSM. For example, one application of such an FSM may be the parsing of a character stream to identify accepted words.

Furthermore, in example FSMs described herein, when the FSM searches the CAM based on a received input term, the FSM searches just those storage blocks of the CAM that are associated with the current state of the FSM, rather than searching the entire CAM. In particular, for each received input, the example FSM may enable a subset of the blocks of the CAM for searching and disable searching of the remaining blocks, with the blocks of the CAM that are enabled being selected based on the current state of the FSM. For example, the storage blocks of the CAM may be associated with particular FSM states, and the FSM may enable searching of only those storage blocks of the CAM that are associated with the current state of the FSM. For example, if the current state is “3” and blocks 16-28 of the CAM are associated with the state “3”, then blocks 16-28 are enabled for searching while the remaining blocks of the CAM are disabled for searching. In some examples, enabling searching of a CAM block may include precharging a matchline associated with the storage block (or enabling the precharging), while disabling searching of the CAM block may include not precharging the matchline.

Because the example FSMs described herein search just those CAM blocks associated with the current state of the FSM, these FSMs may avoid a potential problem that might otherwise occur in which a search of the CAM does not return a unique match. In particular, a given input term may be a valid input for multiple FSM states, and therefore the input term may be recorded in multiple CAM blocks—specifically, the term may be recorded in one CAM block of each of the FSM states for which the term is a valid input. Because the same term may be stored in multiple CAM blocks, if the entire CAM were searched for a given input term then it is possible for there to be multiple CAM blocks that match the search. This potential problem may be avoided, however, by searching just those CAM blocks associated with the current state of the FSM.

In addition, because the example FSMs described herein search just those CAM blocks associated with the current state of the FSM, the amount of power used by the FSM may be greatly reduced. For example, in FSM's whose CAMs use matchline precharging, the matchlines of storage blocks that are not associated with the current state are not precharged, which saves a significant amount of power.

As noted above, the storage blocks of the CAM may be associated with the states of the FSM, and the FSM may use these associations to determine which blocks of the CAM to enable for searching. In some examples, the associations between CAM storage blocks and FSM states may be fixed (e.g., the FSM is “hardwired” to treat certain CAM blocks as being associated with certain FSM states), while in other examples the associations between CAM storage blocks and FSM states may be dynamically changed (e.g., the FSM may allocate and reallocate CAM blocks to FSM states).

As an example of fixed associations between CAM blocks and FSM states, the FSM may include enablement circuits corresponding respectively to the FSM states, and each of these enablement circuits may be fixedly associated with a subset of the CAM blocks. In such examples, each enablement circuit may be configured to control whether its CAM blocks are enabled. For example, the enablement circuits may each be configured to determine whether the current state of the FSM matches the enablement circuit's corresponding state, and if so the enablement circuit may generate an enable signal that controls whether searching is enabled for its CAM blocks.

As an example of dynamically changeable associations between CAM blocks and FSM states, the FSM may include a look-up table (LUT) in which ranges of CAM block addresses may be dynamically allocated to FSM states. In such examples, the current state of the FSM may be input to the LUT, and the LUT may output an indication of the range of CAM block addresses that is currently associated with the current state of the FSM. The FSM may then determine which CAM blocks to enable based on whether the blocks are within the address range output by the LUT. For example, the FSM may include an enablement circuit for each individual CAM block, which may be configured to control enablement of its CAM block based on whether the address of its CAM block is within the range output by the LUT.

In an alternative approach to avoiding the problem of the CAM potentially returning multiple matches for a single search term, some FSMs may store state identifiers in the CAM together with the possible input terms, and search the CAM based on both the current state and the received input term. In other words, for each input term that is to be stored in the CAM, the state associated with the input term may be prepended or appended to the input term and the resulting word may be what is actually stored in the CAM block. Then, when the CAM is searched, the current state may be prepended or appended to the received input term to generate the search word that the CAM is searched for. In this approach, unique CAM search results may be ensured.

Although this alternative approach does avoid the problem of non-unique CAM results, the approach entails searching the entire CAM for each received input term. Therefore such an FSM will use much more power than the example FSMs described herein in which only a subset of the CAM is searched for each received input term. In addition, because each CAM storage block in this alternative approach stores a state identifier in addition to the input term, the word storage size (i.e., the number of bit cells per storage block) in the CAM of the alternative approach must be larger than the word storage size in the example CAMs described herein, which store just the input term but not the state identifier. A larger word storage size results in a larger overall size and increased cost for these FSMs of the alternative approach as compared to the example FSMs described herein.

FIGS. 1A and 1Billustrate an example FSM10. The FSM10includes a CAM100, a memory200, search enablement logic300, and state transition logic400. The CAM100may store input terms of the FSM10in storage blocks110, with each storage block110being associated with a state of the FSM10. The memory200may store identifiers of states of the FSM10in storage blocks210. In some examples, the memory200may also store additional information, such as instructions, in the storage blocks210. The search enablement logic300may select a subset of the storage blocks110of the CAM100to enable for searching based on the current state of the FSM10. The state transition logic400may receive an input stream comprising a series of input terms, and may control the state transitions of the FSM10based on the input stream.

In particular, for each input term of the input stream, the state transition logic400may provide the input term to the CAM100and cause the CAM100to be searched using the input term as a search word. Based on the current state of the FSM10, the search enablement logic300may select a subset of the storage blocks110of the CAM100to enable for searching—specifically, the search enablement logic300may select those storage blocks110that are associated with the current state. Thus, when the CAM100is searched based on the input term, only a subset of the storage blocks thereof is searched.

The CAM100then outputs an indication (called “match_addr” herein) of the storage block110that matches the input term (if any). The state transition logic400may then output to the memory200an indication (called “read_addr” herein) of a particular storage block210that is to be read, based on match_addr and a predefined correspondence between storage blocks110and storage blocks210.

One, both, or neither of match_addr and read_addr may be analog signals identifying the matching storage block110and/or the target storage block210, and one, both, or neither of match_addr and read_addr may be digital signals encoding addresses of the matching storage block110and/or the target storage block210. In some examples, the state transition logic400may translate match_addr into read_addr, while in other examples match_addr and read_addr may be identical, and match_addr may simply be passed straight through to the memory200as read_addr.

For example, as illustrated inFIG. 1B, each storage block110's matchline120may be connected directly to its corresponding storage block210of the memory200, such that the corresponding storage blocks210is automatically read when the matchline120of the corresponding storage block110indicates a match. This example may be beneficial in that encoding, decoding, translating, and/or other circuitry between the CAM100and the memory200may be omitted, thus simplifying the design and manufacture of the FSM10, reducing power consumption, and potentially increasing speed of operation. In this example, match_addr and read_addr are formed by a single analog signal (i.e., the high voltage of the matchline120of the matching storage block210).

As another example, as illustrated inFIG. 1A, match_addr and read_addr both are digital signals that encode addresses. More specifically, match_addr encodes the address of the matching block110, while read_addr encodes the address of the corresponding storage block210that is to be read. This example may be beneficial in that correspondence relationships between blocks110and blocks210may be changed post-manufacture, since they are not hard-wired into the FSM10. In some of these examples, match_addr and read_addr may be different, in which case the state transition logic400may translate match_addr and read_addr. In other examples, match_addr and read_addr may be identical, in which case match_addr may simply be input directly from the CAM100to the memory200.

Although not illustrated, other combinations of match_addr and read_addr may be used. For example, match_addr may be analog while read_addr is digital (e.g., the matchline120of each storage block110may be output directly from the CAM100to the state transition logic400, which outputs a digital read_addr based thereon). As another example, match_addr may be digital while read_addr is analog (e.h., each storage block210may have an associated read wiring (not illustrated) that is connected to the state transition logic400, such that the target storage block210is indicated by applying an active signal on its associated read wiring). In such an example, the active signal on the read wiring constitutes read_addr.

The memory200may output the state identifier stored in the read storage block210to the state transition logic400. The memory200may also generate additional output based on the contents of the read storage block210; for example, if the read storage block210stores an instruction in addition to the state identifier, then the memory200may output the instruction. The state transition logic400may then update the current state of the FSM10to match the state identifier that was output by the memory200.

Specific examples of the above-described components of the example FSM10will be described in greater detail below.

The example CAM100may include multiple storage blocks110(see, e.g.,FIG. 2). Each storage block110may include a number of bit cells112(see, e.g.,FIG. 5), which are capable of storing at least binary values (e.g., 1 or 0). Each storage block110corresponds to a data word, with each bit cell112of the storage block110corresponding to a bit-position of the data word. For example, if the first, second, and third, bit cells112of a storage block110store the value “1” and the fourth bit cell112of the storage block110stores the value “0”, then the storage block110stores the word “1110”.

In the FSM10, the storage blocks110may be used to store input terms of the FSM10. More specifically, groups115of storage blocks110may be respectively associated with states of the FSM10, and each group115of storage blocks110may store the input terms that are accepted by the FSM10for that state. For example, if state “3” of the FSM10accepts the terms “b”, “c”, and “d”, then the terms “b”, “c”, and “d” may be stored in a group115of storage blocks110that is associated with state “3”. Because multiple states of the FSM10may accept the same term, some input terms may be stored in multiple of the storage blocks110; however, in general each input term is stored just once within the same group115.

Each of the storage blocks110has a corresponding matchline120(see, e.g.,FIG. 2), which indicates during a search operation whether the word stored in the storage block110matches a search word. In particular, bit cells112that are part of the same storage block110are all connected to the same matchline120as one another, either in parallel or in series (see, e.g.,FIG. 5). In order to search the storage block110, the CAM100may apply voltages to the bit cells112based on a search word, such that the value stored in each bit cell112of the storage block110is compared to the bit of the search word in the same bit position. For example, during a search operation using the search word “1011”, the first, third, and fourth bit cells112of the storage block110may be compared to the value “1”, while the second bit cell112of the storage block110may be compared to the value “0”. If the word stored in a storage block110matches the search word, then the voltage of the matchline120associated with the storage block110will be at one level (e.g., high), while if any bit cell112of the storage block110stores a non-matching value, then voltage of the matchline120will be at an opposite level (e.g., low).

For example, in a NOR-type architecture, the bit cells112respectively include switches (not illustrated), such as transistors, that are connected in parallel to the corresponding matchline120. Each of the switches may be connected between a first voltage (e.g., a low voltage) and the matchline120, such that when the switch is ON (e.g., passing a signal) a current path is formed that connects the matchline120to the first voltage. In such an example, the CAM100searches a storage block110by first precharging the matchline120to a second voltage (e.g., a high voltage). Then any bit cell112whose stored value does not match the corresponding bit of the search word will turn ON its switch, thus forming a current path to connect the matchline120to the first voltage. Thus, if a single bit cell112does not store a matching value, then that bit cell112will pull the voltage of the matchline120to the first voltage (regardless of whether or not the other bit cells112match their respective search criteria). Accordingly, the matchline120remains at the second voltage only if all of the bit cells112store values that match their respective search criteria.

As another example, in a NAND-type architecture, the bit cells112may be serially connected to one another, with a last one of the bit cells112being connected to the corresponding matchline120. The bit cells112may be configured such that a given bit cell112passes an active signal (e.g., high voltage) to its next neighbor if the given bit cell112: (a) received an active signal either from the previous cell112or from a voltage source in the case of the first bit cell112, and (b) matches its own search criteria. Thus, the last bit cell112in the series will output a match signal to the corresponding matchline120only if all of the bit cells112matched their search criteria. For example, each bit cell112may include a switch (not illustrated), such as a transistor, that is turned ON (passes a signal) during a search if the bit cell112matches its search criterion. The switches of the bit cells112may be connected in series between the second voltage (e.g., a high voltage) and the corresponding matchline120, such that when all of the switches are ON they form a signal path between the matchline120and the second voltage (e.g., a high voltage). In such an example, if a single bit cell112does not store a matching value, then the switch of that bit cell112will prevent a signal from being passed on to the next bit cell112and ultimately to the matchline120. Accordingly, an active signal is applied to the matchline120by the last bit cell112only if all of the bit cells112store values that match their respective search criteria.

In some examples, the CAM100may also include an encoder130(not illustrated). The encoder130may detect any matchline120that indicates a match (e.g., has a high voltage after a search), determine an address of the corresponding storage block110, and output that address as a digital signal constituting match_addr.

In other examples, such as in the example ofFIG. 1B, the matchlines120may extend out of the CAM100without passing through an encoder, in which case an active signal on one of the matchlines120constitutes match_addr.

In some examples in which the CAM100is a TCAM, the bit cells112may also be capable of storing a wildcard value in addition to the binary values. The bit cells112are such that, if they store the wildcard value, then they always indicate a match regardless of the value they are compared to.

The memory200may be any non-transitory machine readable medium, which may include volatile storage media (e.g., DRAM, SRAM, etc.) and/or non-volatile storage media (e.g., PROM, EPROM, EEPROM, NVRAM, hard drives, optical disks, etc.). The memory200may include storage blocks210. Each storage block210of the memory200may correspond to a storage block110of the CAM100, and may be used to store a destination state identifier. The state identifier is referred to herein as a “destination” state identifier because it denotes the next state that the FSM10will assume if that storage block210is read. In particular, when a storage block110of the CAM100matches a search, then the corresponding storage block210of the memory200is read, and the state identifier that is stored therein becomes the next state of the FSM10. Thus, the destination state identifier that is read from the memory200becomes the “current state” for the next input term that is input to the FSM10.

As noted above, in addition to storing the destination state identifiers, the storage blocks210may also store additional information. For example, the storage blocks210may store instructions that may be output to a processor for execution.

As mentioned above, the search enablement logic300may be configured to select a subset of the storage blocks110of the CAM100to enable for searching. In particular, the search enablement logic300may select the subset based on a current state of the FSM10. More specifically, each storage block110is associated with one of the states of the FSM10, and the search enablement logic300may select those storage blocks110that are associated with the current state of the FSM10. Examples of how the search enablement logic300may be able to determine which storage blocks110are associated with the current state are described in greater detail in the following sections.

Once the search enablement logic300has identified which storage blocks110to enable, it may enable the searching of the selected storage blocks110by causing a necessary condition of searching to be satisfied for those selected storage blocks110. For example, the search enablement logic300and/or the CAM100may include circuitry that prevents any given storage block110from being searched if it does not have an active search enable signal (i.e., a storage block110having an active search enable signal is a necessary condition for it to be searched). In such examples, the search enablement logic300may enable searching of the selected storage blocks by generating active search enable signals for the selected storage blocks110.

For example, in some examples in which the CAM100has a NOR-based architecture, the searching of a storage block110requires precharging of its matchline120. In such examples, the search enablement logic300and/or the CAM100may include circuitry that prevents a precharging voltage from being generated for or applied to the matchline120of any storage block110that does not have an active search enable signal. In this way, a storage block110having the active search enable signal becomes a necessary condition for it to be searched.

As another example, in some examples in which the CAM100has a NAND-based architecture, the searching of a storage block110requires the first bit cell112in the series of bit cells112of the storage block110to be connected to the second voltage (e.g., high voltage). In such examples, the search enablement logic300and/or the CAM100may include circuitry (such as a switch) that prevents the second voltage from being connected to the first bit cell112of any storage block110that does not have an active search enable signal. In this way, a storage block110having the active search enable signal becomes a necessary condition for it to be searched.

The search enablement logic300may be any circuitry capable of performing the operations described herein in relation to the search enablement logic300. For example, the search enablement logic300may include dedicated hardware, such as in the detailed examples illustrated inFIGS. 4, 5, and8and described below.

As another example, the search enablement logic300could include general-purpose processing circuitry that is configured to perform the operations described herein by executing machine readable instructions. In such an example, the processing circuitry constituting the search enablement logic300may include any circuitry capable of executing machine-readable instructions, such as a central processing unit (CPU), a microprocessor, a microcontroller device, a digital signal processor (DSP), etc.

2.3.1. Example of Fixed State/Block Associations

FIG. 2illustrates a first example of the search enablement logic300in which the storage blocks110of the CAM100are fixedly associated with states of the FSM10. In this example, the search enablement logic300includes group enablement circuits310. Each of the group enablement circuits310is associated with a particular state of the FSM10; for example, inFIGS. 2 and 3, the state with which a group enablement circuit310is associated is indicated as a binary number within the box that represents the group enablement circuit310. In addition, each of the group enablement circuits310is to control search enablement for a corresponding group115of multiple storage blocks110of the CAM100; for example, inFIGS. 2 and 3each group enablement circuit310is associated with a group115comprising four storage blocks110. Specifically, a given group enablement circuit310is to control whether searching is enabled for its group115of storage blocks110based on whether the current state of the FSM10matches the state that is associated with the group enablement circuit115.

For example, a group enablement circuit310may control search enablement of its corresponding group115by outputting a search enable signal to corresponding wiring lines315. In the example of CAM100with a NOR-architecture, the wiring lines315may be connected to a precharging circuit (not illustrated) of each storage block110in its corresponding group115, which allows precharging for its storage block110only when the search enable signal is asserted on the wiring line315. In the example of CAM100with a NAND-architecture, the wiring lines315may be connected to a switch (not illustrated) of each storage block110in its corresponding group115, which connects the first bit cell112of the storage block to the second voltage only when the search enable signal is asserted on the wiring line315.

For example, inFIG. 3, an example is illustrated in which the current state of the FSM10is “0010”, various input terms are stored in the storage blocks110(indicated inFIG. 3by letters within the boxes representing the storage blocks110), and the input search term is “c”. In this example, each of the group enablement circuits310reads “0010” (i.e., the current state) from the digital bus301, and decides whether to output an active enable signal based on whether “0010” matches the state that is associated with the group enablement circuit310. InFIG. 3the group enablement circuit310whose associated state matches the current state is indicated by a thick lined rectangle, and this group enablement circuit310outputs a search enable signal for each storage block110in its associated group115, while the other group enablement circuits310do not output search enable signals. InFIG. 3, the wiring lines315carrying active search enable signals are indicated by thick lines, while the wiring lines315not carrying active search enable signals are indicated by dashed lines. The enabled storage blocks110are searched based on “c” (i.e., the input term), while the remaining blocks110of the CAM100are not searched. InFIG. 3, the storage blocks110that are searched are indicated by thick lined rectangles. The storage block110within the searched group115that stores the term “c” indicates a match on its matchline120. InFIG. 3, the matchline120indicating a match is indicated by a thick line, while the matchlines120that do not indicate a match are indicated by dashed lines. In the example illustrated inFIG. 3, the indication of the match on the matchline120is output directly from the CAM100as match_addr. In other examples (not illustrated), the indication of the match on the matchline120may be encoded into a digital value corresponding to the address of the matching storage block110(i.e., “00110”), which is then output from the CAM100.

AlthoughFIGS. 2 and 3illustrate examples in which there are fifteen group enablement circuits310and four storage blocks110per group115, these numbers are used merely for convenience of illustration and description. In practice, any number of group enablement circuits310may be included. In addition, any number of storage blocks110may be included in each group115, and the number of storage blocks110does not have to be the same from one group115to the next.

In some example FSMs10that use the example search enablement logic300ofFIGS. 2 and 3, the maximum number of states that the FSM10may have is equal to the number of group enablement circuits310. Accordingly, in some circumstances it may be desired to include at least as many group enablement circuits310as the anticipated number of FSM states. Similarly, in some example FSMs10that use the example search enablement logic300ofFIGS. 2 and 3, the maximum number of input terms that can be accepted by any given state of the FSM10may be equal to the number of storage blocks110in the group115associated with that state. Accordingly, in some circumstances it may be desired to include at least as many storage blocks110in each group115as are anticipated to be needed by the states of the FSM10. In examples in which the states and input terms of the FSM10are known and the FSM10is not intended to be reprogrammed, the numbers of group enablement circuits310and storage blocks110in each group115may be tailored specifically to match the states and input terms of the FSM10. In examples in which the FSM10is to be a general-purpose or reprogrammable FSM, then it may be desirable, in some circumstances, to include the same number of storage blocks110per group115, since it might not be known in advance how many search terms will need to be associated with each state.

FIG. 4illustrates one possible example of how a group enablement circuit310may be constituted. In the example ofFIG. 4, each group enablement circuit310comprises an AND gate311that has its inputs connected to a digital bus301that carries a digital value representing the current state, and whose output is a search enable signal for a group115of storage blocks110. Each of the AND gates311may have the same number of inputs as the word size of the digital bus301, which number is designated “N” herein. InFIG. 4, a four-bit example (i.e., N=4) is shown for simplicity, but in practice any word size that is sufficient to encode all of the states of the FSM10may be used. The inputs of each AND gate311may be connected to the bus301in such a manner as to cause the AND gate311to function as a digital comparator that compares the value of the digital bus to a specific number, which is the FSM state that the group enablement circuit310is associated with. In such an example, the AND gate311will output a logic 1 only when the current state is the same as the state that the group enablement circuit310is associated with. In particular, such a comparator may be formed by connecting each input of the AND gate311to either an inverted or non-inverted signal of a corresponding bit of the digital bus301based on the corresponding state number. Specifically, each AND gate311may be connected to the digital bus301based on its corresponding state number as follows: for each value of n={1, 2, . . . , N}, if the nthbit of the state number is “0” then connect the nthinput of the AND gate311to the inverted signal of the nthbit of the digital bus301, and if the nthbit of the state number is “1” then connect the nthinput of the AND gate311to the non-inverted signal of the nthbit of the digital bus301. Thus, for example, an AND gate311that is associated with the number “0001” may be formed by connecting its first three inputs to an inverted signal of the first three bits of the bus301, respectively, and connecting its fourth input to the non-inverted fourth bit of the bus301, as illustrated inFIG. 4.

The search enable signal that is output by a group enablement circuit310controls whether searching of the storage blocks110of its group115is enabled in the sense that none of the storage blocks110in its group115can be searched if the search enable signal is not active (e.g., logic 1). However, just because the search enable signal is active for a given group115, this does not necessarily mean that all (or any) of the enabled storage blocks110will actually be searched. For example, it is possible for searching of a storage block110to be contingent on both the search enable signal and additional conditions. For example, the search enable signal may be logically conjoined (AND-ed) with another signal, and the result may control search enablement of the entire group115or of individual storage blocks110therein, such that searching is enabled for the group115or individual blocks110only when both signals are active.

More specifically, references herein to something controlling whether searching is enabled should be understood to mean that the thing (e.g., the search enable signal) is at least a necessary condition for searching of the group115, but should not be misunderstood to mean that the thing is necessarily a sufficient condition of searching of the group115.

For example,FIG. 5illustrates additional enablement logic that may further control, in conjunction with the search enable signal, whether any or all of storage blocks110in a group115can be searched. In the example ofFIG. 5, each group115may have an associated precharge control circuit312and multiple individual enablement circuits313.

The precharge control circuit312may be constituted by an AND logic gate that performs logical conjunction on the search enable signal output by the group enablement circuit310and a precharge signal, and the output of the precharge control circuit312may control whether any of the matchlines120of the group115may be precharged. Thus, in this example, searching is enabled for storage blocks in the group115only if the search enable signal and the precharge signal are both active (logical 1) at the same time. The precharge control circuit312may be included to ensure that precharging of matchlines120occurs only at desired timings, such as immediately prior to a search operation.

The individual enablement circuits313may each be associated with one of the storage blocks110of the group115, and may control whether that individual storage block110is enabled for searching. In the example ofFIG. 5, each individual enablement circuit313controls whether its storage block110is enabled for searching based on (1) the output of the precharge control circuit312, and (2) whether a special bit111associated with the storage block110is set. In particular, if the special bit111is set (e.g., stores a “1”), then searching of the storage block110may be enabled (assuming other conditions, such as the search enable signal being on, are met), while if the special bit111is not set (e.g., stores a “0”), then searching of the storage block110may be disabled (regardless of whether the other conditions are met). For example, each individual enablement circuit313may be constituted by an AND logic gate with one input connected to a readout node of the special bit111of the corresponding storage block110and a second input connected to the output of the precharge control circuit312. The special bit111may be configured such that, at least during a search operation, its readout node outputs a logic 1 when the bit111is set and outputs a logic 0 when the bit111is not set.

The use of such individual enablement circuits313may allow more fine-grained control of which storage blocks110are enabled. For example, the FSM10and/or a user thereof may prevent individual storage blocks110from being searched by not setting its special bit111. For example, the FSM10may be configured to set the special bit111of any storage block110that stores an input term, but to not set the special bit111of any storage block110that is empty. This may be beneficial, for example, because it may save even more power by preventing the wasteful searching of storage blocks110that do not store any input terms. For example, in some example FSMs10, it may be possible for an FSM state to have more storage blocks110associated with it than are needed to store the valid inputs for that state, which means that there will be some unused storage blocks110for that state. For example, suppose that every state is allocated 64 storage blocks110and that a given FSM state has only 23 valid inputs, then in this example there will be 41 storage blocks in the group115associated with the given state that do not store anything.

AlthoughFIG. 5focuses on an example using a NOR-type CAM architecture, the same principles apply to a NAND-type architecture mutatis mutandis. For example, in a NAND-type architecture, instead of the outputs of the AND gates313being connected to the matchlines120, they each could be connected to the first bit cell112of their corresponding storage block110as the source of the second voltage. In such examples, the second voltage is applied to the first bit cell112when the corresponding AND gate313outputs logical 1. As another example, in a NAND-type architecture, instead of the outputs of the AND gates313being connected to the matchlines120, they each could be connected to a switch (e.g., transistor) that is interposed between a voltage source carrying the second voltage and the first bit cell112, such that the switch is turned ON (e.g., passes a signal) when the AND gate313outputs logical 1.

2.3.2. Example of Changeable State/Block Associations

In a second example of the search enablement logic300, the storage blocks110of the CAM are changeably associated with states of the FSM10. For example, the search enablement logic300may select a subset of storage blocks110to enable for searching by identifying a range of block-addresses that are associated with a current state of the FSM and enabling searching of only those blocks110of the CAM100whose respective block-addresses are within the identified range. The search enablement logic300may identify the range of block-addresses that are associated with the current FSM state by consulting a record that associates block-addresses with FSM states, such as a look up table (LUT). The association between block-addresses and FSM states may be changeable in the record, thus allowing the storage blocks110to be dynamically allocated and reallocated amongst FSM states.

For example, as illustrated inFIG. 6, the search enablement logic300may include individual enablement circuits320, with each being associated with one storage block110of the CAM100. Each of the individual enablement circuits320is to control search enablement for its corresponding storage block110. For example, an individual enablement circuit320may control search enablement of its corresponding storage block110by outputting a search enable signal to a corresponding wiring line326. The wiring line326may be connected to circuitry (not illustrated) (such as a precharge circuit or switch) associated with the corresponding storage block110that allows searching of its storage block110only when the search enable signal is asserted on the wiring line326.

The search enablement logic300may further include an LUT325, which associates ranges of block-addresses of storage blocks110with states of the FSM10. The current FSM state may be input to the LUT325, and in response the LUT325may look up the range of addresses that is associated with the current state and output an indication of the range, such as the first and last block-address of the range. The individual enablement circuits320may each determine whether or not to enable their storage block based on the range of block-addresses output by the LUT325. Specifically, an individual enablement circuit310may enable its storage block110if only its block-address is within the identified range.

For example, inFIG. 7, an example is illustrated in which the current state of the FSM10is “0010”, various input terms are stored in the storage blocks110(indicated inFIG. 7by letters within the boxes representing the storage blocks110), and the input search term is “b”. In this example, the LUT325looks up “0010” (i.e., the current state), and outputs “000011” and “000110” (i.e., the start and end block-addresses of the range that is associated with the state “0010” in the LUT325). Each of the individual enablement circuits320reads “000011” and “000110” (i.e., the start and end block addresses) from the digital bus302, and decides whether to output an enable signal based on whether the block address of its associated storage block110is within the range indicated by the read numbers. InFIG. 7the individual enablement circuits320whose associated block addresses are within the range output by the LUT325are indicated by a thick lined rectangle, and each of these individual enablement circuits320outputs a search enable signal for its corresponding storage block110, while the other individual enablement circuits320do not output any enable signals. InFIG. 7, the wiring lines326carrying active search enable signals are indicated by thick lines, while the wiring lines326not carrying active search enable signals are indicated by dashed lines. The enabled storage blocks110are searched based on “b” (i.e., the input term), while the remaining blocks110of the CAM100are not searched. InFIG. 7, the storage blocks110that are searched are indicated by the thick lined rectangles. The storage block110among the searched storage blocks110that stores the term “b” indicates a match on its matchline120. InFIG. 7, the matchline120indicating a match is indicated by a thick line, while the matchlines120that do not indicate a match are indicated by dashed lines. In the example illustrated inFIG. 7, the indication of the match on the matchline120is output directly from the CAM100as match_addr. In other examples (not illustrated), the indication of the match on the matchline120may be encoded into a digital value corresponding to the address of the matching storage block110(i.e., “000100”), which is then output from the CAM100.

AlthoughFIGS. 6 and 7illustrate examples in which there are 63 individual enablement circuits320and storage blocks110, these numbers are used merely for convenience of illustration and description. In practice, any number of individual enablement circuits320and storage blocks110may be included.

FIG. 8illustrates one example of how the individual enablement circuits320may be constituted. The individual enablement circuits320illustrated inFIG. 8are configured to output a search enable signal if any of the following conditions are satisfied: (A) their associated block address matches the start address carried on the digital bus302, (B) their associated block address matches the end address carried on the digital bus302, or (C) their associated block address is between the start and end addresses carried on the digital bus302. More specifically, each of the individual enablement circuits320, with a few exceptions, may include: (i) a start AND gate321whose inputs are connected to the bits of the digital bus302that carry the start block address, (ii) an end AND gate322whose inputs are connected to the bits of the digital bus302that carry the end block address, (iii) an AND gate324, and (iv) an OR gate323whose output is the wiring line326. The inputs of the AND gate324are connected to an inverted output of the end AND gate322and to the wiring line326. The output of the AND gate324is passed to a next individual enablement circuit320. The inputs of the OR gate323are connected to the output of the start AND gate321and the output of the AND gate324of the previous individual enablement circuit320. The first one of the individual enablement circuits320may omit the OR gate323, and the corresponding wiring line326may be connected to the output of the start AND gate321instead. The last one of the individual enablement circuits320may omit the AND gate324and the end AND gate322. Additional details pertaining to these elements are described in greater detail below.

For each individual enablement circuit320, the start and end AND gates321,322may have their inputs connected to the digital bus302so as to cause the AND gates321,322to act as digital comparators comparing the start and end addresses, respectively, to the individual enablement circuit320's block address. Thus, for example, the start AND gate321of the first individual enablement circuit320is connected to the start address bits of the bus302so as to cause the start AND gate321to compare the start address on the bus302to the block address associated with the first individual enablement circuit320(which is “0001” inFIG. 8). Thus, the start AND gate321outputs a logical 1 if and only if the start address carried on the bus302matches the block address associated with the individual enablement circuit320, while the end AND gate322outputs a logical 1 if and only if the end value carried on the bus302matches the block address associated with the individual enablement circuit320.

The start AND gates321described above ensure that the individual enablement circuit320that matches the start address will output a search enable signal. In particular, because the output of the start AND gate321is an input of the OR gate323, the individual enablement circuit320will output an active (e.g., logical 1) search enable signal if the start address on the digital bus302matches its block address.

As for individual enablement circuits320whose block addresses equal the end address or are between the start and end addresses, these individual enablement circuits320may be caused to output active search enable signals via the AND gates324. As noted above, the output of the AND gate324is passed down to the next individual enablement circuit320as an input of the OR gate323of the next circuit320. Thus, an individual enablement circuit320will output an active search enable signal if the AND gate324of the previous individual enablement circuit320is outputting an active search enable signal. Furthermore, the AND gate324of a given individual enablement circuit320is configured such that it will output a logical 1 if and only if (1) the given individual enablement circuit320is outputting an active search enable signal, and (2) the block address of the given individual enablement circuit320does not match the end address. Accordingly, any individual enablement circuit320will output an active search enable signal if the previous individual enablement circuit320is also outputting an active search enable signal, unless the block address of the previous individual enablement circuit320happens to match the end address. This results in all of the individual enablement circuits320whose block addresses are between the start and end addresses (inclusive of the end address) outputting active search enable signals, while any individual enablement circuit320whose block address is outside the range (i.e., prior to the start address or subsequent to the end address) does not output an active search enable signal.

To see how the above-described configuration results in the correct individual enablement circuits320outputting search enable signals, consider an example in which the start address output on the bus302is “0011” (i.e., 3) and the end address output on the bus302is “0101” (i.e., 5). In this example, the third individual enablement circuit320whose block address is “0011” will output a search enable signal because its block address matches the start address (i.e., its start AND circuit321outputs logical 1, causing its OR gate323to output logical 1). This is precisely the desired result, since the block address of the third circuit320(“0011”) is within the range [0011, 0101]. Furthermore, the AND gate324of the third individual enablement circuit320will output logical 1, since its OR gate323is outputting logical 1 and its end AND gate322is outputting logical 0.

To further the above example, the fourth individual enablement circuit320whose block address is “0100” will also output a search enable signal, even though its block address does not match the start address, because the AND gate324of the previous circuit320(i.e., the third circuit320) is outputting logical 1. This is precisely the desired result, since the block address of the fourth circuit320(“0100”) is within the range [0011, 0101]. Furthermore, the AND gate324of the fourth individual enablement circuit320will output logical 1, since its OR gate323is outputting logical 1 and its end AND gate322is outputting logical 0.

To further the above example, the fifth individual enablement circuit320whose block address is “0101” will also output a search enable signal because the OR gate323of the previous circuit320(i.e., the fourth circuit320) is outputting logical 1. This is precisely the desired result, since the block address of the fifth circuit320(“0101”) is within the range [0011, 0101]. However, unlike with the previous two circuits320, the AND gate324of the fifth individual enablement circuit320does not output a logical 1, because the block address of the fifth individual enablement circuit320matches the end address (i.e., its end AND gate322outputs logical 1).

To further the above example, the first, second, and sixth or greater individual enablement circuits320all will not output a search enable signal, because (A) their respective block addresses do not match the start address (i.e., their respective start AND gates321output logic 0), and (B) none of these individual enablement circuits320have a previous circuit320whose AND gate324is outputting logical 1. This is precisely the desired result, since none of the block addresses of the first circuit320(“0001”), second circuit (“0010”), and sixth or subsequent circuits320(“0110”, . . . ) are within the range [0011, 0101].

One benefit of example FSMs10that use changeable association between FSM states and CAM storage blocks110, such as the example illustrated inFIGS. 6 and 7, is that these FSMs10may have more efficient utilization of their CAM blocks110than example FSMs10that use fixed associations between CAM blocks110and FSM states. In particular, in some fixed association FSMs10, some FSM states may have reserved for them more storage blocks110than they need to store the valid inputs for that state, which can result in wasted storage blocks. In contrast, in example FSMs10that use changeable association between FSM states and CAM storage blocks110, such as the example illustrated inFIGS. 6 and 7, each state may be associated with exactly enough CAM blocks110to store its valid input terms and no empty storage blocks110are reserved for that state. Thus, in some circumstances, the FSM states may be more densely packed in the CAM100of a changeable-association FSM10, allowing the CAM100to be smaller overall than the CAM100of a fixed-association FSM10.

Another benefit of example FSMs10that use changeable association between FSM states and CAM storage blocks110is that they may be more easily able to accommodate states that have large numbers of valid inputs. In particular, in changeable-association FSMs10the number of inputs that can be included in a state is limited only by the overall number of storage blocks110in the CAM100. In contrast, in some fixed-association FSMs10, each state has the same number of storage blocks110associated with it, and therefore no state may have more valid inputs than this number. (In this discussion, it is assumed for convenience that a wildcard input term counts as a single input term, even though in practice it may “match” multiple distinct searches).

Another benefit of example FSMs10that use changeable association between FSM states and CAM storage blocks110is that they may be more easily reprogrammed to change the operation of the FSM10. Although fixed-association FSMs10may be reprogrammable—for example one can change the input terms stored in the CAM100—but the reprogrammability of such FSMs10may be limited in some circumstances by the fixed associations between state and the number of storage blocks110. For example, if the second state is fixedly associated with eight storage blocks110, then it might not be possible to reprogram the FSM10to include ten valid inputs for the second state; in contrast, in example FSMs10that use changeable association between FSM states and CAM storage blocks110, there is nothing in principle that would prevent such a reprogramming, since the storage blocks110can be reallocated.

However, one benefit of example FSMs10that use fixed associations between FSM states and CAM storage blocks110, such as the FSMs10illustrated inFIGS. 2 and 3, is that they may be simpler and cheaper to construct than example FSMs10that use changeable associations between FSM states and CAM storage blocks110. For example, the number of group enablement circuits310in the example ofFIG. 2is going to be less than the number of individual enablement circuits320included in the example ofFIG. 6, resulting in less complexity and lower cost for the fixed association FSM10. As another example, the group enablement circuit310in the example ofFIG. 4may be less complex than the example individual enablement circuit320inFIG. 8, resulting in less complexity and lower cost for the fixed association FSM10. As another example, the digital bus301of the example ofFIG. 2may have a smaller word-width than the digital bus302of the example ofFIG. 6, resulting in less complexity and lower cost for the fixed association FSM10. As another example, the search enablement circuit310ofFIG. 2does not need an LUT or other record, while the search enablement circuit310ofFIG. 6does, resulting in less complexity and lower cost for the fixed association FSM10.

In other words, the fixed-association FSMs10ofFIGS. 2-5may be less complex, while the changeable-association FSMs10ofFIGS. 6-8may be more flexibly reprogrammable and CAM-space-efficient.

2.4. Example State Transition Logic400

The state transition logic400may be configured to, for each received input: feed the received input to the CAM100as a search term, and determine a next state of the FSM10based on a destination-state identifier read from the memory200. After identifying the next state, the state transition logic400may update its current state output to be the destination-state identifier read from the memory200. The state transition logic400may also output the destination state identifier to a controller (not illustrated) of the FSM10, which may be part of the FSM10or external to the FSM10(such as, for example, the processing circuitry510illustrated inFIG. 12). In some examples, such as the example ofFIG. 1A, the state translation logic400may also generate the target read address (read_addr) for the memory200based on an output from the CAM100.

FIG. 9illustrates one example of how the state transition logic400may be constituted. The state transition logic400may include a first register401and a second register402. In some examples, such as the example ofFIG. 1A, the state transition logic400may also include a translator403. InFIG. 9, the translator403is illustrated with dotted lines to emphasize that it is not necessarily included in every example of the state transition logic400.

The first register401may have the input stream applied to its input terminals. The first register401may output input terms of the input stream, which are then fed to the CAM100as search terms. For example, each input term of the input stream may be successively output from the first register401based on a clock signal clk, with one input term being output per clock cycle. In some examples, one purpose of the first register401may be to ensure that the input terms are fed to the CAM100at desired timings, since the timings at which the input terms are received by the FSM10may not always align with desired timings. In some examples, the first register401may receive and/or store multiple input terms at a time, and then output the input terms one at a time.

In some examples in which the timings of input terms in the input stream already align with desired timings, the first register401may be omitted. In such examples, the input stream may be fed directly into the CAM100.

The second register402may receive the destination state identifier that is read from the memory200. Upon a next clock cycle beginning, the second register402may then output the received destination state identifier to the search enablement logic300as the current state.

In some examples, the translator403is to receive match_addr (the identification of the matching storage block110that is output from the CAM100) and, based thereon, output read_addr (the identification of the target storage block210that is to be read). InFIG. 9, an example is illustrated in which match_addr and read_addr are both digital signals that encode block addresses. However, as noted above, match_addr and read_addr may be any combination of digital and analog signals.

For example, if match_addr and read_addr are both digital signals that encode block addresses, the translator403may comprise circuitry that associates CAM100block addresses with corresponding memory200block addresses (or ranges of block addresses). For example, the translator403may comprise an LUT (not illustrated) that associates block addresses of the CAM100with block addresses of the memory200, and the LUT may be searched based on match_addr to determine read_addr.

As another example, if match_addr is an analog signal asserted on one of the matchlines120and read_addr is a digital signal that encodes a block address, then translator403may comprise circuitry that associates matchlines120with corresponding memory200block addresses (or ranges of block addresses), such as an encoder.

Furthermore, as noted above, in some examples match_addr and read_addr may be identical, in which case the translator403may be omitted, and match_addr may be passed directly to the memory200as read_addr. For example, as illustrated inFIG. 1B, each matchline120may be connected directly to the memory200and correspond to one of the storage blocks210such that a given storage block210is identified as the read target when its corresponding matchline120carries an active signal.

FIG. 10illustrates example operations of the example state transition logic400ofFIG. 9. InFIG. 10, the inputs and/or outputs of various structures are shown across time.FIG. 10is included to aid understanding, but is not intended to accurately represent the exact timings at which signals start and/or end relative to one another.

As illustrated inFIG. 10, the input terms I1, . . . , I4are serially input to the CAM100as search terms, one per clock cycle. After the clock cycle begins, the search enablement logic300enables a subset of storage blocks110based on the current state being output by the register402. Specifically, in the nthclock cycle the search enablement logic300enables the subset of blocks110at a timing tnabased on the current state Sn-1.

Subsequently, the enabled storage blocks110are searched based on the most recent input term input to the CAM100. Specifically, for the nthclock cycle, the CAM100is searched based on the input term Inat timing tnb. As a result of the searching of the CAM100, the CAM100outputs match_addr. The match_addr is then translated into a read_addr that is fed to the memory200(or match_addr is fed directly to the memory200as the read_addr).

Subsequently, the storage block210of the memory200whose block address matches read_address is read. Specifically, for the nthclock cycle, at timing tncthe storage block210that matches Addrnis read, where Addrnis the read_address that results from searching the CAM100based on the input term In. As a result of reading the memory200, a destination state identifier stored in the read storage block210is output to and stored in the second register402. Specifically, for the nthclock cycle, the destination state identifier Snis output to the second register402.

In some examples, the timing at which the memory200is read is coordinated such that the destination state is being asserted on the inputs of the second register402at least when the next clock cycle begins, so that the second register402will store the destination state. For example, inFIG. 10, the destination state identifier Snis asserted at the inputs of second register402from some timing after tncuntil at least tn+1. Thus, for the nthclock cycle, the current state that is output by the second register402is Sn-1(i.e., the destination state from the previous clock cycle).

In some examples, the destination state may be buffered before being input to the second register402at the start of the next clock cycle.

In some examples, the second register402may receive an enable signal that coincides with the outputting of the destination state from the memory200, rather than a clock signal clk.

In the example, described above, the dedicated hardware is used for the state transition logic400. However, in other examples, the state transition logic400could be formed by general purpose processing circuitry executing machine readable instructions.

3. Example Method

FIG. 11illustrates an example method. The method may be performed using one of the example FSMs10described above. For example, the method may be performed by any entity that controls the example FSM10, directly or indirectly, such as a person or another electronic device (such as processing circuitry executing machine readable instructions). The entity performing the method may be referred to hereinafter as the controller or as a processing circuit. The controller may be part of the FSM10or external to the FSM10(such as, for example, the processing circuitry510illustrated inFIG. 12).

In block4001, the controller may cause the search enablement logic300to select a subset of CAM storage blocks110to enable for searching based on a current state of the FSM10.

In block4002, the controller may cause the selected subset of blocks110of the CAM100that were enabled to be searched based on the current received input term.

In block4003, the controller may cause the storage block210of the memory200that is associated with the storage block110that matched the search to be read.

In block4004, the controller may cause a current state of the FSM10to be updated to equal the destination state identifier that was stored in the storage block210that was read in block4003.

4. Example Electronic Device

The example FSMs10described herein may be used in any electronic device, such as, for example, in a personal computer, server, smartphone, tablet, network device, etc.

FIG. 12illustrates an example device1000that includes an example FSM10. Moreover, some of the features described below could be omitted from the example device1000and others not described below could be added.

The device1000may include an FSM10, processing circuitry510(also referred to as a controller), and machine readable media530. The FSM10may be an instance of the example FSM10described above, and may include a CAM100, a memory200, search enablement logic300, and state transition logic400.

The processing circuitry510may supply the input stream to the FSM10, and may receive the outputs from the FSM10. The processing circuitry510may also control various operations of the FSM10, such as, for example, by providing signals to control operations of the CAM100and/or memory200. The processing circuitry510may be any circuitry capable of executing machine-readable instructions, such as a central processing unit (CPU), a microprocessor, a microcontroller device, a digital signal processor (DSP), etc. The processing circuitry510may also be an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), an application-specific instruction set processor (ASIP), or the like, that is configured to perform certain operations described herein.

In some examples, some or all of the search enablement logic300may be formed by processing circuitry executing machine readable instructions. In some such examples, the processing circuitry forming the search enablement logic300may be distinct from the processing circuitry510. In other such examples, the processing circuitry510may be the processing circuitry forming the search enablement logic300.

The machine readable media530may be any non-transitory machine readable medium, which may include volatile storage media (e.g., DRAM, SRAM, etc.) and/or non-volatile storage media (e.g., PROM, EPROM, EEPROM, NVRAM, hard drives, optical disks, etc.). The machine readable media530may store machine-readable instructions that, when executed by the processing circuitry510, cause the processing circuitry510to perform some or all of the operations described herein, such as the operations described above in relation toFIG. 11. In particular, the instructions may cause the processing circuitry510to send input terms to the FSM10, control searching of the CAM100, and control reading of the memory200. In some examples, the instructions may also include instructions to cause the processing circuitry510to perform operations of the search enablement logic300. In some examples, the machine readable media530and the memory200may be part of the same component. In other examples, the machine readable media530and the memory200may be distinct components.

The example FSMs are described herein and illustrated in the drawings in a conceptual or schematic manner to aid understanding. In particular, physical structures in the example FSMs are referred to and/or illustrated conceptually herein as circuit components, and the relationships between these circuit components are illustrated in circuit diagrams in accordance with the usual practice in the art. Circuit components are conceptual representations of classes of physical structures or devices that perform certain functions and/or have certain properties. Examples of such circuit components include passive devices such as resistors, capacitors, memristors, etc.; active devices such as transistors, diodes, etc.; constituent elements of the active/passive devices such as terminals, electrodes, gates, sources, drains, etc.; elements that connect devices such as wiring lines, nodes, etc.; and so on. It should be understood that a single physical structure (or set of physical structures) in an actual physical incarnation of an example FSM may serve multiple functions and/or have multiple properties, and thus a single physical structure (or set of physical structures) may be described and/or illustrated herein as multiple distinct circuit components. For example, a single piece of metal in a particular physical incarnation of an example FSMs may serve as both a gate electrode of a transistor and as a wiring line. Thus, the fact that two or more circuit components may be referred to or illustrated herein as distinct components should not be interpreted to mean that their corresponding physical structures in a physical incarnation of the example FSMs are distinct structures.

When reference is made herein or in the appended claims to a first circuit component being “connected to” a second circuit component, this means that: (1) the physical structures corresponding to the first and second components are so arranged that a current path exists there-between, and/or (2) a single physical structure that is electrically conductive serves as at least a part of both the first and second circuit components. Note that, in light of this definition, a reference herein to or illustration in the drawings of multiple circuit components being “connected to” one another does not imply that the circuit components are necessarily separate physical entities. For example, a reference to a first circuit component being “connected to” a second circuit component could encompass: (A) a scenario in which a physical structure that serves as a terminal of the first circuit component is in direct physical contact with a physical structure that serves as a terminal of the second circuit; (B) a scenario in which a physical structure that serves as a terminal of the first circuit component is in direct physical contact with an electrical conductor (e.g., a wiring line) that is itself in direct physical contact with a physical structure that serves as a terminal of the second circuit; (C) a scenario in which the same physical structure that serves as a terminal of the first circuit component also serves as a terminal of the second circuit component; etc.

When reference is made herein or in the appended claims to a first component being “connected between” second and third components, this means that two opposing terminals of the first component are connected to the second component and to the third component, respectively. In particular, when reference is made herein or in the appended claims to a transistor being “connected between” two elements, this means that a source terminal of the transistor (also referred to as a source electrode, source region, source, etc.) is connected to one of the two elements, and a drain terminal of the transistor (also referred to as a drain electrode, drain region, drain, etc.) is connected to the other one of the two elements.

When reference is made herein or in the appended claims to a number of circuit components being “connected in series between” a first element and a second element, this means that the number of circuit components are connected end-to-end in a series, in the same order that they are recited, and that the first circuit component of the series is connected to the first element and the last circuit component of the series is connected to the second element. For example, “A, B, and C are connected in series between D and E” means that D is connected to A, A is connected to B, B is connected to C, and C is connected to E, which may be graphically represented as D-{A-B-C}-E where the dashes (“-”) indicate connections and the braces (“{ }”) indicate the series.

As used herein, a “switch” is any device that can selectively connect or disconnect two terminals to/from each other. For example, the switch may be a transistor, a multiplexor, a demultiplexor, a mechanical switch, etc. References to a switch being “ON” mean that the two terminals are connected, allowing a signal to pass through the switch, while references to a switch being “OFF” mean that the two terminals are disconnected, preventing a signal from passing through the switch. For example, when a transistor is the switch, the switch is ON when the transistor is ohmic (i.e., a channel has formed), and the switch is OFF when the transistor is not ohmic (i.e., no channel has formed).

Throughout this disclosure and in the appended claims, occasionally reference may be made to “a number” of items. Such references to “a number” mean any integer greater than or equal to one. When “a number” is used in this way, the word describing the item(s) may be written with the pluralized “s” for grammatical consistency, but this does not necessarily mean that multiple items are being referred to. Thus, for example, “a number of comparators” could encompass both one comparator and multiple comparators.

While the above disclosure has been shown and described with reference to the foregoing examples, it should be understood that other forms, details, and implementations may be made without departing from the spirit and scope of this disclosure.