Metal line patterning

Disclosed are approaches for forming a semiconductor device. In some embodiments, a method may include a method may include providing a semiconductor device including plurality of patterning structures over a device stack, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface. The method may further include forming a seed layer along just the first sidewall and the upper surface of each of the plurality of patterning structures, forming a metal layer atop the seed layer, forming a fill material between each of the plurality of patterning structures, and removing the plurality of patterning structures.

FIELD OF THE DISCLOSURE

The present disclosure relates to semiconductor devices, and more particularly, to methods for metal line patterning.

BACKGROUND OF THE DISCLOSURE

Traditionally, metal lines in semiconductor devices have been formed by subtractive processes, as well as a damascene process. Metal line widths have been trending towards widths of less than 10 nm. However, as line widths decrease, the cross-sectional area also decreases, causing resistance to increase. Furthermore, metal lines having a seed layer further reduce metal volume and increase resistance. It is with respect to these and other deficiencies of the prior art that the present disclosure is provided.

SUMMARY OF THE DISCLOSURE

In one approach, a method may include providing a semiconductor device including plurality of patterning structures over a device stack, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface. The method may further include forming a seed layer along just the first sidewall and the upper surface of each of the plurality of patterning structures, forming a metal layer atop the seed layer, forming a fill material between each of the plurality of patterning structures, and removing the plurality of patterning structures.

In another approach, a method of forming a semiconductor device may include providing a plurality of patterning structures over a device stack, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface. The method may further include forming a seed layer along just the first sidewall and the upper surface of each of the plurality of patterning structures, forming a metal layer atop just the seed layer, and forming a fill material over the plurality of patterning structures and the device stack. The method may further include planarizing the fill material, the metal layer, and the seed layer to remove the metal layer and the seed layer from the upper surface of each of the plurality of patterning structures.

In another approach, a metal line patterning method may include providing a semiconductor device including a plurality of patterning structures over a device stack, each of the plurality of patterning structures including a first sidewall, a second sidewall, and an upper surface. The metal line patterning method may further include forming a metal layer and a seed layer over each of the plurality of patterning structures, planarizing a metal layer and a seed layer to remove the metal layer and the seed layer from the upper surface of each of the plurality of patterning structures, and removing the plurality of patterning structures to form a plurality of fill structures, wherein the metal layer and the seed layer are present along just one sidewall of each of the plurality of fill structures.

DETAILED DESCRIPTION

Methods and semiconductor devices in accordance with the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings, where embodiments of the methods are shown. The methods and semiconductor devices may be embodied in many different forms and are not to be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so the disclosure will be thorough and complete, and will fully convey the scope of the system and method to those skilled in the art.

FIG. 1depicts a side cross-sectional view of a semiconductor device (hereinafter “device”)100in accordance with embodiments of the present disclosure. The device100may include a device stack101and upper device layer102, which may be a dielectric layer. A plurality of masking or patterning structures105may be formed over the device layer102. As shown, each of the patterning structures105may include a first sidewall106, a second sidewall108, and an upper surface110connecting the first and second sidewalls106,108. In some embodiments, the patterning structures105may be formed by a relaxed lithography and etch process, wherein the patterning step may involve a self-aligned quadruple patterning (SAQP) process or a selective self-aligned double patterning (SADP) process or any lithography process that may be at a lower resolution than the desired final structure. Although non-limiting, the patterning structures105may be made from any known hardmask material, e.g., oxide, silicon, C, silicon nitride, and the like. In some embodiments, the patterning structures105may include a photoresist layer114atop a patterning film116.

As shown inFIGS. 2A-2B, the photoresist layer114is removed selective to an upper surface118of the patterning film116of each patterning structure105. A seed layer120may then be formed over the patterning structures105. In some embodiments, the seed layer120may be formed by a directional mask deposition process122, wherein a seed material (e.g., a metal layer, such as copper, cobalt, nickel, gold, silver, manganese, tin, aluminum, ruthenium, and alloys thereof) may be delivered to the device100at a non-zero angle of inclination ϕ relative to a perpendicular126to a top surface128of the device layer102. In some embodiments, the non-zero angle of inclination may be selected so that the seed material impacts just the first sidewall106and the upper surface118of each of the patterning structures105. The seed layer120generally does not form along the second sidewall108of each of the patterning structures105. As shown, the top surface128between each of the patterning structures105is generally unaffected by the directional mask deposition process122. Said another way, the seed material is prevented from forming along the top surface128of the device layer102in an area directly adjacent the second sidewall108of each of the patterning structures105.

As shown inFIGS. 3A-3B, a metal layer130may be formed along the first sidewall106and the upper surface118of each of the patterning structures105. More specifically, the metal layer130may be formed atop each of the seed layers120. As shown, the metal layer130may not be formed along the second sidewall108of each of the patterning structures105. In some embodiments, the metal layers130may be formed by a selective atomic layer deposition (ALD) process. In other embodiments, the metal layers130may be formed by a chemical vapor deposition (CVD) process or electrochemical deposition. As shown, each metal layer130generally extends down to the top surface128of the device layer102. Although non-limiting, the metal layer may be ruthenium (Ru), cobalt (Co), molybdenum (Mo), or tungsten (W).

Next, as shown inFIG. 4, a fill material140may be formed over the device100, including between each of the patterning structures105, and then planarized, as shown inFIG. 5. In some embodiments, the fill material140may be planarized selective to the upper surface118of the patterning structures105. As shown, the metal layer130and the seed layer120may also be removed from the upper surface118of each of the patterning structures105. In some embodiments, the metal layer130and the seed layer120remain only along the first sidewall106of each of the patterning structures105. In some embodiments, the planarization process may be a CMP and/or etch. Although non-limiting, the fill material140may be a gap fill oxide or nitride.

Next, as shown inFIGS. 6A-6B, the patterning structures105may be removed from the device100to form a set of trenches144and a plurality of fill structures146. In some embodiments, the patterning structures105may be removed selective to the top surface128of the device layer102of the patterning stack101using, e.g., a wet etch process. The metal layers130and the seed layers120may remain. As shown, the metal layers130and the seed layers120are present along just one sidewall148of each of the plurality of fill structures146.

Next, as shown inFIG. 7, a second fill material152may be formed over the device100, including over the plurality of fill structures146and within the set of trenches144. In some embodiments, the second fill material152may be gap fill oxide or nitride, which is planarized (not shown) to a same height or thickness as the metal layers130and the seed layers120.

FIG. 8shows a side view of another apparatus according to embodiments of the disclosure. As shown, an extraction assembly280may be coupled to the plasma chamber202, and include an extraction plate284and a beam blocker282. The extraction assembly280may further include a collimation plate286, disposed between the extraction plate284and device layer102. Extraction of an ion beam may be achieved by a bias voltage applied between the plasma chamber202and device layer102, depending upon the targeted ion energy. To generate an angled ion beam, the beam blocker282may be arranged to block a portion of the aperture290, formed with the extraction plate284, so that an ion beam288is extracted from the plasma chamber202along the edge of the aperture as shown.

Notably, ions may exit the plasma chamber202over a range of angles. To select for a given angle of incidence (or narrow range of angles of incidence) (θ), the collimation plate286may be provided with a collimation aperture292arranged at a specific offset O with respect to an edge of the aperture290.FIG. 8illustrates four possible placements for the collimation aperture292. Increasing the value of O will lead to a higher value of θ. InFIG. 8, for an offset O1, the corresponding q1 is 17-21 degrees. Larger offsets will produce larger angles of incidence. Thus, for a given placement of the collimation aperture292, ions exiting the plasma chamber202will be blocked from traversing to the device layer102, except those ions having the suitable angle of incidence to pass through the collimation aperture292and strike the device layer102. Thus, by switching between different collimation plates having different value of O, the apparatus ofFIG. 8presents a convenient means to vary the angle of incidence of ions of a reactive beam to be applied to a substrate to change the coverage of the selective seed layer120on the patterning structures105, as generally shown inFIGS. 1 and 3B.

It is to be understood that the various layers, structures, and regions shown in the accompanying drawings are schematic illustrations. For ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given drawing. This does not imply that any layers, structures, and/or regions not explicitly shown are omitted from the actual semiconductor structures.

In various embodiments, design tools can be provided and configured to create the datasets used to pattern the semiconductor layers of the device100, e.g., as described herein. For example, data sets can be created to generate photomasks used during lithography operations to pattern the layers for structures as described herein. Such design tools can include a collection of one or more modules and can also be comprised of hardware, software or a combination thereof. Thus, for example, a tool can be a collection of one or more software modules, hardware modules, software/hardware modules or any combination or permutation thereof. As another example, a tool can be a computing device or other appliance running software, or implemented in hardware.

As used herein, a module might be implemented utilizing any form of hardware, software, or a combination thereof. For example, one or more processors, controllers, ASICs, PLAs, logical components, software routines or other mechanisms might be implemented to make up a module. In implementation, the various modules described herein might be implemented as discrete modules or the functions and features described can be shared in part or in total among one or more modules. In other words, as would be apparent to one of ordinary skill in the art after reading the Detailed Description, the various features and functionality described herein may be implemented in any given application and can be implemented in one or more separate or shared modules in various combinations and permutations. Although various features or elements of functionality may be individually described or claimed as separate modules, one of ordinary skill in the art will understand these features and functionality can be shared among one or more common software and hardware elements.

For the sake of convenience and clarity, terms such as “top,” “bottom,” “upper,” “lower,” “vertical,” “horizontal,” “lateral,” and “longitudinal” will be understood as describing the relative placement and orientation of components and their constituent parts as appearing in the figures. The terminology will include the words specifically mentioned, derivatives thereof, and words of similar import.

As used herein, an element or operation recited in the singular and proceeded with the word “a” or “an” is to be understood as including plural elements or operations, until such exclusion is explicitly recited. Furthermore, references to “one embodiment” of the present disclosure are not intended as limiting. Additional embodiments may also incorporating the recited features.

Furthermore, the terms “substantial” or “substantially,” as well as the terms “approximate” or “approximately,” can be used interchangeably in some embodiments, and can be described using any relative measures acceptable by one of ordinary skill in the art. For example, these terms can serve as a comparison to a reference parameter, to indicate a deviation capable of providing the intended function. Although non-limiting, the deviation from the reference parameter can be, for example, in an amount of less than 1%, less than 3%, less than 5%, less than 10%, less than 15%, less than 20%, and so on.

Still furthermore, one of ordinary skill will understand when an element such as a layer, region, or substrate is referred to as being formed on, deposited on, or disposed “on,” “over” or “atop” another element, the element can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on,” “directly over” or “directly atop” another element, no intervening elements are present.

As used herein, “depositing” and/or “deposited” may include any now known or later developed techniques appropriate for the material to be deposited including yet not limited to, for example: chemical vapor deposition (CVD), low-pressure CVD (LPCVD), and plasma-enhanced CVD (PECVD). Additional techniques may include semi-atmosphere CVD (SACVD) and high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), limited reaction processing CVD (LRPCVD), metal-organic CVD (MOCVD), and sputtering deposition. Additional techniques may include ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitridation, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, evaporation.

While certain embodiments of the disclosure have been described herein, the disclosure is not limited thereto, as the disclosure is as broad in scope as the art will allow and the specification may be read likewise. Therefore, the above description is not to be construed as limiting. Instead, the above description is merely as exemplifications of particular embodiments. Those skilled in the art will envision other modifications within the scope and spirit of the claims appended hereto.