Magnetoresistance device

A magnetoresistance device has a channel extending between first and second ends in a first direction comprising non-ferromagnetic semiconducting material, such as silicon, a plurality of leads connected to and spaced apart along the channel, a gate structure for applying an electric field to the channel in a second direction which is substantially perpendicular to the first direction so as to form an inversion layer in the channel and a face which lies substantially in a plane defined by the first and second directions and which is configured such that an edge of the channel runs along the face.

FIELD OF THE INVENTION

The present invention relates to a magnetoresistance device particularly, but not exclusively, for use as a magnetic field sensor or a read head in a hard disk drive.

BACKGROUND

Hard disk drives (HDDs) are widely used for high-density information storage. HDDs are commonly found in computer systems traditionally associated with this type of storage, such as servers and desktop computers. However, HDDs having smaller form factors, such as one-inch drives, can also be found in hand-held electronic devices, such as music players and digital cameras.

Higher storage capacity in HDDs can be achieved by increasing storage density. Storage density is currently doubling roughly every year and the highest storage density presently achievable using conventional technology, such as by recording data in bit cells which are arranged longitudinally in the magnetic recording medium and reading data using so-called “spin value” read heads, is about 100 Gb/in2.

However, as storage density in HDDs continues to increase, then recording media and read heads encounter the problem of the superparamagnetic effect.

The superparamagnetic effect arises when the size of a ferromagnetic grain is sufficiently reduced that the energy required to change direction of magnetisation of the grain is comparable to the thermal energy. Thus, the magnetisation of the grain is liable to fluctuate and so lead to data corruption.

For recording media, a solution to the problem has been demonstrated which involves arranging bit cells perpendicularly (rather than longitudinally) to the surface of the recording medium which allows each bit cell to be large enough to avoid the superparamagnetic effect.

To address this problem in read heads, it been proposed to avoid using any ferromagnetic material and to take advantage of the so-called extraordinary magnetoresistance (EMR) effect.

A device exhibiting the EMR effect is described in “Enhanced Room-Temperature Geometric Magnetoresistance in Inhomogeneous Narrow-Gap Semiconductors”, by S. A. Solin, T. Thio, D. R. Hines and J. J. Heremans, Science volume 289, p. 1530 (2000). The device is arranged in a van der Pauw configuration and includes a highly conductive gold inhomogeneity concentrically embedded in a disk of non-magnetic indium antimonide (InSb). At zero applied magnetic field (H=0), current flows through the gold inhomogeneity. However, at non-zero applied magnetic field (H≠0), current is deflected perpendicularly to the field-line distribution, around the gold inhomogeneity and through the annulus. This gives rise to a drop in conductance.

Currently, high mobility narrow gap semiconductors with low carrier density, such as indium antimonide (μn=7×104cm2V−1s−1at 300° K), indium arsenide (μn=3×104cm2V−1s−1at 300° K) and gallium arsenide (μn=8.5×103cm2V−1s−1at 300° K), seem to be the best candidates for EMR-based read heads.

A drawback of this device is that it requires a thick (i.e. about 75 nm) passivation layer to protect and confine the active layer as well as an insulating coat in the form of a layer of silicon nitride. This increases the separation between the channel and magnetic media and so reduces magnetic field strength and, thus, the output signal.

Silicon does not require passivation and silicon-based magnetic field sensors exhibiting magnetoresistance are known.

For example, EP-A-1 868 254 describes a device exhibiting the extraordinary magnetoresistance effect having a channel formed of silicon. A conductor formed of titanium silicide or highly-doped silicon acts as a shunt and is connected to the channel along one side of the channel. Leads are connected to and spaced along the channel on the opposite side of the channel.

However, silicon has lower mobility and so device performance tends to be poorer.

The present invention seeks to provide an improved magnetoresistance device.

SUMMARY

According to a first aspect of certain embodiments of the present invention there is provided a magnetoresistance device having a channel extending between first and second ends in a first direction comprising non-ferromagnetic semiconducting material, a plurality of leads connected to and spaced apart along the channel, a gate structure for applying an electric field to the channel in a second direction which is substantially perpendicular to the first direction so as to form an inversion layer in the channel and a face which lies substantially in a plane defined by the first and second directions and which is configured such an edge of the channel runs along the side face. The face may be a side face. The gate structure may lie above or below the channel.

Thus, the face may be presented to the upper surface of a magnetic media which can have the advantage of allowing the channel to be brought close to the surface of a magnetic media. If the non-ferromagnetic semiconducting material is silicon or some other non-ferromagnetic semiconducting material which does not require passivation, then the separation between the channel and the surface of a magnetic media can very small (e.g. less than about 10 nm).

The plurality of leads may comprise two leads, three leads or four leads. The plurality of leads may comprise more than four leads.

The gate structure may comprise a gate electrode separated from the channel by a gate dielectric for applying an electric field to the channel.

The gate structure can be used to form an inversion layer in the channel in an undoped or lightly-doped semiconducting material which has a higher mobility than the same but heavily-doped semiconducting material which would otherwise be needed to reduce the resistance of the device and so improve device performance.

The gate structure may be a top gate structure wherein the gate dielectric is disposed on the channel and the gate electrode is disposed on the gate dielectric. The gate structure may be a bottom gate structure. The gate electrode may comprise semiconducting material and may comprise silicon, such as doped silicon. The gate electrode may comprise highly-doped silicon, e.g. doped with an impurity having a concentration of at least about 1×1019cm−3. The gate electrode may comprise n-type semiconducting material.

The channel may comprise silicon or silicon germanium. The channel may be undoped or doped with an impurity, e.g. a donor, having a concentration up to about 1×1016cm−3. The channel may be strained.

The layer structure may include a layer of the non-ferromagnetic semiconducting material disposed on the substrate and the channel may be formed in the layer of non-ferromagnetic semiconducting material. Additionally or alternatively, the substrate may include a region of the non-ferromagnetic semiconducting material and the channel is formed in the substrate.

The device may further comprise a conductive region comprising non-ferromagnetic material having a higher conductivity than the channel and connecting at least two sections of the channel. Thus, the conductive region may provide a shunt.

The conductive region may comprise semiconducting material, such as silicon. The conductive region may be doped with an impurity having a concentration of at least about 1×1019cm−3. The conductive region may lie under the channel. The conductive region may be formed in a region of the substrate.

The device may be a read head for a hard disk drive.

According to a second aspect of certain embodiments of the present invention there is provided apparatus comprising the magnetoresistance device and a magnetic field source, the magnetic field source and device arranged such that, when a magnetic field is applied to the device, the magnetic field passes substantially perpendicularly through the side face.

According to a third aspect of certain embodiments of the present invention there is provided a method of operating a magnetoresistance device having a channel extending between first and second ends in a first direction comprising non-ferromagnetic semiconducting material, a plurality of leads connected to and spaced apart along the channel in a second direction which is substantially perpendicular to the first direction, a gate structure for applying an electric field to the channel so as to form an inversion layer in the channel and a face which lies substantially in a plane defined by the first and second directions and which is configured such that an edge of the channel runs along the side face, the method comprising driving a current between two leads and measuring a voltage developed between two leads.

According to a fourth aspect of certain embodiments of the present invention there is provided a method of operating a magnetoresistance device having a channel extending between first and second ends in a first direction comprising non-ferromagnetic semiconducting material, a plurality of leads connected to and spaced apart along the channel, a gate structure for applying an electric field to the channel in a second direction which is substantially perpendicular to the first direction so as to form an inversion layer in the channel and a face which lies substantially in a plane defined by the first and second directions configured such that an edge of the channel runs along the face, the method comprising applying a bias of appropriate polarity and sufficient magnitude so as to form of an inversion layer in the channel.

According to a fifth aspect of certain embodiments of the present invention there is provided method of fabricating a magnetoresistance device, the method comprising providing a channel extending between first and second ends in a first direction comprising non-ferromagnetic semiconducting material, a plurality of leads connected to and spaced apart along a side of the channel and a gate structure for applying an electric field to the channel in a second direction which is substantially perpendicular to the first direction so as to form an inversion layer in the channel, and defining a face which lies substantially in a plane defined by the first and second directions and which is configured such that an edge of the channel runs along the face.

Removing the side of the layer structure and the substrate may comprise lapping the layer structure and the substrate.

According to a sixth aspect of certain embodiments of the present invention there is provided a magnetoresistance device having a channel arranged comprising non-ferromagnetic semiconducting material, a plurality of leads connected to and spaced apart along the channel, a gate structure for applying an electric field to the channel so as to form an inversion layer in the channel and a side face configured such that a side of the channel runs along the side face.

DETAILED DESCRIPTION OF CERTAIN EMBODIMENTS

First Embodiment

Referring toFIGS. 1 to 4, a first embodiment of a magnetoresistance device1according to the present invention is shown.

The device1includes a layer structure2disposed on an upper surface3of a substrate4. The substrate4comprises p-type single crystal silicon having a conductivity of about 10 Ωcm.

The device1has a side face5which is substantially flat and lies in a plane6which cuts through the layers of the layer structure2and the upper surface3of a substrate4. For example, as shown inFIG. 1, a growth axis corresponds to the z-axis, the upper surface3of the substrate4lies in an x-y plane and the side face5lies in an x-z plane. As will be explained in more detail later, the side face5is formed by lapping and the device1may be used as a read head in a hard disk drive with the side face5providing an air bearing surface (ABS). In certain embodiments, the side face5(or at least part of the side face5) is covered by a thin protective layer (not shown) of dielectric material, e.g. having a thickness of equal to or less than about 10 nm, equal to or less than about 5 nm, equal to or less than 2 nm or equal to or less than about 1 nm. The protective layer (not shown) may be formed of silicon dioxide (SiO2) and may form naturally. The protective layer (not shown) may be kept as thin as possible and/or be made of a material having a relative permeability, μr, so as to keep magnetic field strength high. The side face5is substantially flat across the whole side of the device1.

The device1includes a layer7of epitaxially-grown, undoped single crystal silicon (Si) having a thickness, t1, of about 30 nm. The silicon layer7provides a channel8and, when a large enough electric field is applied, an inversion layer (FIGS. 6a&6b) which is generally rectangular in plan view, which extends between first and second ends9,10and which has a first edge or side11which runs along the side face5.

The undoped silicon layer7includes first, second, third and fourth heavily-doped n-type implanted regions121,122,123,124(hereinafter referred to as “leads”) which provide electrical connections to and along the channel8. The leads121,122,123,124are doped with an n-type impurity in the form of arsenic (As) to a concentration of about 1×1020cm−3and have a thickness, t2, of about 20 nm.

The device1includes a top gate structure13. The gate structure13includes a gate electrode14formed of a patterned layer of heavily-doped n-type polycrystalline silicon (Si) having a thickness, t3, of about 100 nm and a gate dielectric15formed of a co-extensive (in plan view) patterned layer14of silicon dioxide (SiO2) having a thickness, t4, of about 5 nm. During fabrication, the gate electrode14provides a mask for implantation. The gate electrode13may be formed of one or more layers of metal or metal alloy, such as aluminium or gold. The gate structure13also has an edge or side which runs along the side face5.

As will be explained in more detail later, the gate structure13can be used to apply a sufficiently high electric field to the undoped silicon layer7to form an inversion layer25(FIGS. 6a&6b) and defines the extent of the channel8. Thus, the gate structure13is substantially co-extensive with the channel8and the inversion layer25(FIGS. 6a&6b). There may be small differences (e.g. a few nanometers) between the extent of the gate structure13and channel8, for example, due to undercut or overcut profile. The gate structure13also has an edge or side which runs along the side face5. The channel8extends at least a given (perpendicular) distance, W, away from the side face5and has a second, opposite side11′ which is lithographically defined (by virtue of the gate structure13) and which does not does not run along, nor is close (e.g. closer than about 50 nm) to any side faces of the device1.

Not all parts or regions of the channel8contribute equally to the behaviour or response of the device1. In particular, an effective channel8efflying near to the side face5provides the greatest contribution. The effective channel8efflies between first and second effective ends9eff,10effin a region between the first and fourth leads121,124(shown lightly shaded inFIG. 2) in which the leads121,122,123,124are most closely separated and, thus, has lowest resistance.

The gate structure13and undated epitaxial silicon layer7are covered by an insulating top layer16of silicon dioxide (SiO2) having a thickness, t5, of about 400 nm. Other insulating materials may be used instead of silicon dioxide, such as aluminium oxide (Al2O3).

The insulating top layer16includes contact holes171,172,173,174,175(or “vias”). The leads121,122,123,124and the gate electrode15are contacted by conductive tracks181,182,183,184,185formed of a layer of aluminium (Al) which run over an upper surface19of the insulating layer16and into the contact holes171,172,173,174,175. The gate structure13lies over the channel8such that the gate14lies in the x-y plane. As shown inFIG. 1, when a magnetic field B is applied (perpendicularly) to the side face5along the y-axis, the magnetic field passes in the plane of the gate14.

The substrate4includes a heavily-doped n-type region (or “well”)20which connects at least two sections of the channel8and is herein referred to as a “shunt”. The shunt20is generally rectangular in plan view. The shunt20is doped with an n-type impurity in the form of arsenic (As) to a concentration of about 1×1020cm−3and has a thickness, t6, of about 40 nm. As will be explained later, in some embodiments, the device need not include a shunt.

The channel8is generally rectangular in plan view and has a length, l1, of about 1 μm and a width, w1, of about 1 μm. The gate structure13is generally rectangular in plan view and has a length, l2, of about 1 μm and a width, w2, of about 1 μm. The channel8and gate13are co-extensive and so l1=l2and w1=w2.

The shunt20is elongated and rectangular in plan view having a length, l3, of about 300 nm and a width, w3, of about 40 nm. The leads121,122,123,124each have a width, l4, i.e. length along the channel2, of about 20 nm. The first and second leads121,122are spaced apart having spacing, s1, of about 100 nm. The second, third and fourth leads122,123,124are spaced apart having spacing, s2, of about 20 nm.

The effective channel8effhas a length, l1eff, of about 300 nm and a width, w1eff, of about 40 nm, i.e. approximately the width of shunt20. In embodiments in which the shunt is omitted, the effective width, w1eff, is larger.

The face5lies substantially in a plane6defined by the direction of the channel8, in this example along the x-axis, and the direction in which gate structure13applies electric field to the channel8, in this example the z-axis. Thus, the face5lies substantially in the x-z plane. For example, the face5lies in a plane which deviates (i.e. tilts) from the x-z plane preferably by no more than about 10°, more preferably by no more than about 5°, even more preferably by no more than about 2° or yet even more preferably by no more than about 1°.

In operation, the magnetoresistance device1can be used as a read head in a hard disk drive to detect a magnetic field B passing perpendicularly or nearly perpendicularly (i.e. a few degrees off perpendicular) to the side face5. As will be explained in more detail later, the device1exhibits a magnetoresistive effect in the thin inversion layer25and adjacent region of the channel8since the conductivity of the channel8varies greatly, e.g. exponentially, with distance from the gate13. The device1need not use a thick passivation layer and so the channel8can be brought as close as possible to a magnetic disk.

Referring toFIG. 5, a circuit configuration21for operating the magnetoresistance device1is shown. The circuit configuration21includes a current source22configured to drive current, I, through the channel8between the first lead121(FIG. 2) and the third lead123(FIG. 2) and a voltmeter23configured to measure voltage, V, developed across the second and fourth leads122,124(FIG. 2). This configuration can be referred to as an “IVIV” configuration, geometry or arrangement. A voltage source24is used to apply a bias, VG, to the gate electrode14.

Referring toFIGS. 6aand6b,an inversion layer25is formed in the undoped channel8adjacent to an interface26between the gate dielectric15and the silicon channel8when a sufficiently large voltage, VG, exceeding a threshold voltage, Vth, but not exceeding a gate dielectric breakdown voltage, Vb, is applied to the gate electrode14. Values for the threshold voltage Vthand the gate dielectric breakdown voltage, Vb, can be found by routine experiment. The values usually depend on the material chosen for the silicon layer7and the gate dielectric15and the thickness of the gate dielectric15.

Referring in particular toFIG. 6b,applying a voltage to the gate electrode14generates an electric field27at the interface26causing the conduction and valence bands28,29in the channel8to bend. If a sufficiently large voltage, VG, is applied to the gate electrode14, then the electric field26causes the conduction band28to bend below the Fermi level30and form a potential well31in which free electrons can accumulate, i.e. to form an inversion layer25. The thickness of the inversion layer25can be as small as 1 nm.

FIGS. 6aand6billustrate band bending resulting in accumulation of electrons. If a sufficiently large gate voltage of opposite polarity is applied, which exceeds another threshold voltage, then this can result in hole accumulation. However, the mobility of electrons is usually higher than the mobility of holes, i.e. μe>μh, and so device performance based on electron accumulation is used here.

The current flowing between the first and third electrodes121,123(FIG. 2) flows mainly in the inversion layer25. When a magnetic field B is applied perpendicularly to the side face5, a force acts on electrons causing them to bend perpendicularly to the plane of the inversion layer25(FIG. 6a). The direction in which the electrons bend depends on the direction of the applied magnetic fields. As the resistance of the channel varies with distance from the gate, this results in a magnetoresistance between second and fourth electrodes121,123(FIG. 2).

FIG. 7illustrates voltage-current characteristics321,322,323of the device1(FIG. 1) at a gate voltage of 3V and at three different magnetic fields, namely, B=0 mT, +50 mT and −50 mT, applied perpendicular to the side face5(FIG. 1). The measurement is taken using the same configuration and in which voltage, V, is sensed between the second and fourth leads122,124(FIG. 2) while sweeping current, I, driven through the channel8between the first and third leads121,123(FIG. 2).

FIG. 8illustrates a voltage-magnetic field characteristic33of the device1(FIG. 1) at a gate voltage of 3V and a current of 300 μA driven between the first and second leads121,123(FIG. 2) as magnetic applied perpendicular to the side face5(FIG. 1) is swept from −50 mT to +50 mT.

If (using another different measurement configuration) the third lead123is grounded and the first lead121(FIG. 2) is biased at 1V, then the current, I, flowing between the first and third leads121,123(FIG. 2) is around 330 μA, which means the resistance between the first and third leads121,123(FIG. 2) is about 3 kΩ.

The measured resistance (using yet another different configuration) between second and fourth electrodes122,124(FIG. 2) is almost half of the resistance between the first and third leads121,123(FIG. 2) for the same gate voltage, VG.

As shown inFIG. 7, the output voltage between the second and fourth electrodes122,124(FIG. 2) increases as the current between the first and second leads121,123(FIG. 2).

As shown inFIG. 8, if a current of 300 μA is applied between the first and second leads121,123(FIG. 2), then the change of output voltage (ΔV) measured between the second and fourth electrodes122,124(FIG. 2) is 5.9 mV when the change in applied magnetic field (ΔB) is 50 mT.

Referring toFIGS. 9 and 10, the device1is again measured under similar conditions but using gate bias of 5V, and another set of characteristics are obtained341,342,343,35. As shown inFIGS. 9 and 10, the output voltage is higher.

Referring in particular toFIG. 10, if a current of 300 μA is applied between the first and second leads121,123, then the change of output voltage (ΔV) measured between the second and fourth electrodes122,124(FIG. 2) is 6.5 mV when the change in applied magnetic field (ΔB) is 50 mT.

The output voltage scales with the size of the device and so becomes larger as the device becomes larger. The electrodes121,122,123,124and ion-implanted shunt20have negligible contact resistances.

The device1outputs a signal which is about three to four orders of magnitude greater than a device described in EP-A-1 868 254.

Referring toFIGS. 11ato11q,a method of fabricating the device1will now be described.

A p-type silicon wafer36(FIG. 11a) is cleaned using acetone and IPA. A layer (not shown) of optical resist is spun-on. The optical resist layer (not shown) is patterned using a mask (which is also referred to as a reticle) and a UV light source and developed using an optical resist developer.

Referring toFIG. 11a,optical lithography stage leaves a patterned optical resist layer37leaving an unexposed area38defining the shunt20(FIG. 1).

Referring toFIG. 11b,the wafer36is loaded into an ion implantation chamber (not shown). Arsenic (As) ions39at about 10 keV are implanted into the unmasked regions40of the wafer36. The resist37is removed and the wafer36is laser annealed to activate the implant.

Referring toFIG. 11c,implantation leaves an n+well20′ at the surface41of the implanted wafer42having a doping concentration of about 1×1020cm−3and unimplanted regions43.

The implanted wafer43is cleaned using a 3:1 H2SO4:H2O2(commonly known as a “Piranha etch”). Then, the surface oxide (not shown) is removed by a short dip in 2:5:3 NH2F:C2H4O2:H2O (also known as a “SILOX etch”) and loaded into a reactor chamber (not shown).

Referring toFIG. 11d,a layer44of undoped silicon (Si) having a thickness of 30 nm is grown epitaxially by chemical vapour deposition (CVD). A layer45of silicon dioxide (SiO2) having a thickness of 5 nm is grown by wet oxidation (i.e. oxidation in H2O) at about 800° C. followed by a layer46of n+polycrystalline silicon having a thickness of 100 nm by chemical vapour deposition (CVD).

At this stage the wafer47may be divided into chips. The wafer47(or a chip) may be processed further as follows:

The wafer is cleaned using a Piranha etch, followed by a dip in a SILOX etch. A layer (not shown) of PMMA is applied (e.g. spun-on) to an upper surface48of the wafer48and cured by baking.

The PMMA layer (not shown) is patterned using a scanning electron beam and developed using a mixture of IPA and water to leave a patterned PMMA layer (not shown). The chip is given a short, for example 3-minute, oxygen plasma ash, then a 30-nm thick layer of aluminium is thermally evaporated over the PMMA-patterned surface of the chip. The developed resist is “lifted-off” in acetone, then rinsed in IPA to leave an aluminium etch mask49(which provides a so-called “hard etch mask”) and unmasked areas50of the wafer48as shown inFIG. 11e.

Referring toFIG. 11f,in the unmasked areas50, regions51,52of the silicon and silicon dioxide layers45,46are etched by a reactive ion etch53using a mixture of carbon tetrafluoride and silicon tetrachloride (CF4:SiCl4) as a feed gas.

The aluminium etch mask49is removed using a base, such as (CH3)4NOH.

In some embodiments, a soft etch mask, such as an e-beam resist, may be used. A negative resist may be used instead of a positive resist.

Referring toFIG. 11g,the structure of the device at this stage in processing is shown. A patterned silicon layer53and a coextensive underlying silicon dioxide layer54lie on an upper surface55of the undoped epitaxial silicon layer44.

The patterned silicon and silicon dioxide layers53,54provide an implantation mask leaving areas of the wafer56unmasked.

Referring toFIG. 11h,the wafer56is cleaned and loaded into an ion implantation chamber (not shown). Arsenic (As) ions57at about 5 keV are implanted into the patterned silicon layer53(which is unmasked) and unmasked regions58of the undoped epitaxial silicon layer44. The wafer56is laser annealed to activate the implant.

Referring toFIG. 11f,implantation leaves a layer44′ of epitaxial silicon having doped well regions59and underlying and adjacent undoped regions60, and a patterned layer61of doped polycrystalline silicon. The undoped region60of the silicon44′ corresponds to the channel8.

The wafer62is cleaned using acetone and IPA.

Referring toFIG. 11j,a blanket layer63of silicon dioxide (SiO2) having a thickness of 400 nm is grown by chemical vapour deposition (CVD) over the upper surface63of the wafer62.

A layer (not shown) of PMMA is applied (e.g. spun-on) to an upper surface64of the layer63of silicon dioxide and cured by baking. The PMMA layer (not shown) is patterned using a scanning electron beam and developed using a mixture of IPA and water.

Referring toFIG. 11l,in the unmasked areas66, regions67of the silicon dioxide layer65are etched by a reactive ion etch68, for example using trifluoromethane (CHF3) as a feed gas, through to the doped well regions59.

Referring toFIG. 11m,reactive ion etching leaves vias17in a patterned layer of silicon dioxide63′.

Referring toFIG. 11n,a layer68of aluminium (Al) having a thickness of 400 nm is deposited using RF sputtering over an upper surface69of the patterned layer of silicon dioxide63′ and which covers side walls70and bottoms71of the vias17.

A layer (not shown) of PMMA is applied (e.g. spun-on) to an upper surface72of the metallisation72and cured by baking. The PMMA layer (not shown) is patterned using a scanning electron beam and developed using a mixture of IPA and water.

Referring toFIG. 11p,unwanted regions75of metallization68are etched by a reactive ion etch76, for example using a mixture of boron trichloride, trichloromethane and chlorine (BCl3:CHCl3:Cl2) as a feed gas.

Referring toFIG. 11q,etch stage leaves metallic leads12on the upper surface69of the patterned layer of silicon dioxide63′.

In some embodiments, a lift-off process can be used which involves defining a pattern in positive resist where the leads are to go, depositing

Referring toFIG. 11r,regions77,78,79,80,81,82,83of the patterned top layer63′ of silicon dioxide, patterned layer61of doped polycrystalline silicon, patterned layer54of silicon dioxide, doped well regions59, undoped epitaxial silicon layer60, substrate4and doped well regions20′ respectively are removed by lapping. A lapping process and lapping apparatus is described in U.S. Pat. No. 6,881,124. Other forms of removing the side of the device may be used.

Lapping results in the device1shown inFIGS. 1 to 4. However, as mentioned earlier, a thin (e.g. equal to or less than 2 nm) protective layer of silicon dioxide or other material may be deposited or grown so as to cover at least part of the side face5, e.g. corresponding to the channel8and/or gate14.

If not already divided into chips, the wafer is divided into chips at this stage and the chips are packaged. As will be described later, the device1can be used in a read head in a hard disk drive.

Second Embodiment

Referring toFIGS. 12 to 14, a second embodiment of a magnetoresistance device101according to the present invention is shown.

The second magnetoresistance device101is similar to the first magnetoresistance device1(FIGS. 1 to 4) hereinbefore described.

The device101includes a layer structure102formed on an upper surface103of a p-type substrate104and has a side face105. The device101includes a layer107of epitaxially-grown, undoped single crystal silicon (Si), which provides a channel region108between first and second ends109,110and which has a first side111which runs along the side face105. The undoped silicon layer107includes first, second, third and fourth leads1121,1122,1123,1124. The device101has a top gate113including a gate electrode114and a gate dielectric115for forming an inversion layer125in the undoped silicon layer107. The gate structure113is covered by an insulating top layer116having therein vias1171,1172,1173,1174,1175. The leads1121,1122,1123,1124and the gate electrode114are contacted by conductive tracks1181,1182,1183,1184,1185formed of aluminium.

Device geometry, materials and dimensions are substantially the same as those of the first device1(FIGS. 1 to 4) described earlier. For example, the channel108, leads1121,1122,1123,1124and gate electrode114, gate dielectric115have substantially the same dimensions and comprise the same materials as the channel8(FIGS. 1 to 4), leads121,122,123,124(FIGS. 1 to 4) and gate electrode14(FIGS. 2,3and4) and gate dielectric15(FIGS. 1 to 4) described earlier.

The second magnetoresistance device101differs from the first magnetoresistance device1(FIGS. 1 to 4) hereinbefore described in that it does not have a shunt.

The device101can be controlled using the same circuit configuration21shown inFIG. 5.

When a gate voltage of 5 V is applied, if a current of 120 μA is applied between the first and third leads1121,1123, then the change of output voltage (ΔV) measured between the second and fourth electrodes1122,1124is 25 mV when the change in applied magnetic field (ΔB) is 50 mT.

If the third lead1123is grounded and the first lead1121is biased at 1V, then the resistance between the first and third leads1121,1123is about 7.1 kΩ and the resistance between second and fourth electrodes1122,1124is about half the value between the first and third leads1121,1123.

The second device101can be simpler and cheaper to fabricate since fewer process steps are required and also exhibits a larger magnetoresistance compared with the first device1(FIG. 1).

Third Embodiment

Referring toFIGS. 15 to 17, a third embodiment of a magnetoresistance device201according to the present invention is shown.

The third magnetoresistance device201is similar to the first magnetoresistance device1(FIGS. 1 to 4) hereinbefore described.

The device201includes a layer structure202formed on an upper surface203of a p-type substrate204and has a side face205. The device201includes a layer207of epitaxially-grown, undoped single crystal silicon (Si), which provides a channel208between first and second ends209,210and which has a first side211which runs along the side face205. The undoped silicon layer207includes first, second and third leads1121,1122,1123. The device201has a top gate structure213including a gate electrode214and a gate dielectric215for forming an inversion layer225in the undoped silicon layer207. The gate structure213is covered by an insulating top layer216having therein vias2171,2172,2173,2175. The leads2121,2122,2123and the gate electrode215are contacted by conductive tracks2181,2182,2183,2185formed of aluminium. The substrate204includes a heavily-doped n-type well220which serves as a shunt. The shunt220may be omitted.

The third magnetoresistance device201differs from the first magnetoresistance device1(FIGS. 1 to 4) hereinbefore described in that it has only three leads2121,2122,2123. Furthermore, the lead width (i.e. l3) and lead spacings (i.e. s1and s2) are different from those of the first device1(FIG. 1). In particular, the leads2121,2122,2123each have a width of about 30 nm. The first and second leads2121,2122are spaced apart by about 150 nm. The second and third leads2122,2123are spaced apart by about 30 nm.

Otherwise, device geometry, materials and dimensions are substantially the same as those of the first device1(FIGS. 1 to 4) described earlier. For example, the channel208, leads2121,2122,2123, gate electrode214, gate dielectric215and shunt220have substantially the same dimensions (other than lead width and spacings) and comprise the same materials as the channel8(FIGS. 1 to 4), leads121,122,123(FIGS. 1 to 4) and gate electrode14(FIGS. 1 to 4), gate dielectric15(FIGS. 1 to 4) and shunt20(FIGS. 1 to 4) described earlier.

Referring toFIG. 18, a circuit configuration221for operating the third device201is shown. The circuit configuration221includes a current source222configured to drive current, I, through the channel208between the first lead2121(FIG. 15) and the third lead2123(FIG. 15) and a voltmeter223configured to measure voltage, V, developed across the second and third leads2122,2123(FIG. 15). A voltage source224is used to apply a bias, VG, to the gate electrode214.

FIG. 19illustrates voltage-current characteristics2341,2342,2343of the third device201(FIG. 15) at a gate voltage of 5V and at three different magnetic fields, namely, B=0 mT, +50 mT and −50 mT, applied perpendicular to the side face205(FIG. 15). The measurement is taken using a configuration in which voltage, V, is sensed between the second and third leads2122,2123(FIG. 15) while sweeping current, I, driven through the channel208between the first and third leads2121,2123(FIG. 15).

FIG. 20illustrates a voltage-magnetic field characteristic234of the device201(FIG. 15) at a gate voltage of 5V and a current of 250 μA driven between the first and third leads2121,2123(FIG. 15) as magnetic applied perpendicular to the side face205(FIG. 15) is swept from −50 mT to +50 mT.

As shown inFIG. 19, when a gate voltage of 5 V is applied, if a current of 260 μA is applied between the first and third leads2121,2123(FIG. 15), then the change of output voltage (ΔV) measured between the second and third electrodes2122,2123(FIG. 15) is 24 mV when the change in applied magnetic field (ΔB) is 50 mT. The output voltage between the second and third leads2122,2123(FIG. 15) increases with increasing current.

If the third lead2123(FIG. 15) is grounded and the first lead2121(FIG. 15) is biased at 1V, then the resistance between the first and third leads2121,2123(FIG. 15) is about 3.8 kΩ.

Fourth Embodiment

Referring toFIGS. 21 to 23, a fourth embodiment of a magnetoresistance device301according to the present invention is shown.

The fourth magnetoresistance device301is similar to the first magnetoresistance device1(FIGS. 1 to 4) hereinbefore described.

The device301includes a structure302formed on an upper surface303of a p-type substrate304and has a side face305. The device301includes a layer307of epitaxially-grown, undoped single crystal silicon (Si), which provides a channel308between first and second ends309,310and which has a first side311which runs along the side face305. The undoped silicon layer307includes two leads3122,3123. The device301has a top gate structure313including a gate electrode314and a gate dielectric315for forming an inversion layer325in the undoped silicon layer307. The gate structure313is covered by an insulating top layer316having therein vias3172,3173,3175. The leads3122,3123and the gate electrode315are contacted by conductive tracks3182,3183,3185formed of aluminium. The substrate304includes a heavily-doped n-type well320which serves as a shunt. The shunt320may be omitted.

The fourth magnetoresistance device301differs from the first magnetoresistance device1(FIGS. 1 to 4) hereinbefore described in that it has only two leads3122,3123. However, similar to first device1, the leads3121,3122,3123each have a width of about 20 nm. The leads3122,3123are spaced apart by about 20 nm.

Otherwise, device geometry, materials and dimensions are substantially the same as those of the first device1(FIGS. 1 to 4) described earlier. For example, the channel308, leads3122,3123, gate electrode314, gate dielectric315and shunt320have substantially the same dimensions (other than lead width and spacings) and comprise the same materials as the channel8(FIGS. 1 to 4), leads121,122,123(FIGS. 1 to 4) and gate electrode14(FIGS. 1 to 4), gate dielectric15(FIGS. 1 to 4) and shunt20(FIGS. 1 to 4) described earlier.

Referring toFIG. 24, a circuit configuration321for operating the fourth device301is shown. The circuit configuration321includes a current source322configured to drive current, I, through the channel308between the leads3122,3123(FIG. 21) and a voltmeter323configured to measure voltage, V, developed across the same leads3122,3123(FIG. 21). A voltage source324is used to apply a bias, VG, to the gate electrode314.

FIG. 25illustrates voltage-current characteristics3341,3342,3343of the fourth device301(FIG. 21) at a gate voltage of 5V and at three different magnetic fields, namely, B=0 mT, +50 mT and −50 mT, applied perpendicular to the side face305(FIG. 21). The measurement is taken using the configuration in which voltage, V, is sensed between the leads3122,3123(FIG. 21) while sweeping current, I, driven through the channel308between the leads3122,3123(FIG. 21).

As shown inFIG. 24, when a gate voltage of 5 V is applied, if a current of 390 μA is applied between the leads3122,3123(FIG. 21), then the change of output voltage (ΔV) measured between the electrodes3122,3123(FIG. 21) is 0.86 mV when the change in applied magnetic field (ΔB) is 50 mT. The output voltage between the second and third leads3122,3123(FIG. 21) increases with increasing current.

The resistance measured between the leads3122,3123(FIG. 21) is about 2.5 kΩ.

Fifth Embodiment

Referring toFIGS. 26 to 28, a fifth embodiment of a magnetoresistance device401according to the present invention is shown.

The device401includes a layer structure402formed on an upper surface403of a p-type substrate404and has a side face405. The device401includes a layer407of epitaxially-grown, undoped single crystal silicon (Si), which provides a channel408between first and second ends409,410and which has a first side411which runs along the side face405. The undoped silicon layer407includes two heavily-doped n-type wells4122,4123which provide leads. The device401has a top gate structure413including a gate electrode414and a gate dielectric415for forming an inversion layer425in the undoped silicon layer407. The gate structure413is covered by an insulating top layer416having therein vias4172,4173,4175. The leads4122,4123and the gate electrode415are contacted by conductive tracks4182,4183,4185formed of aluminium. The substrate404includes a heavily-doped n-type well420which serves as a shunt. The shunt420may be omitted.

The fifth magnetoresistance device401differs from the first magnetoresistance device1(FIGS. 1 to 4) hereinbefore described in that it has only two leads4122,4123, and that the gate structure is less extensive, namely that it is arranged just between the leads4122,4123. The leads4122,4123each have a width of about 20 nm. The leads4122,4123are spaced apart by about 20 nm.

Layer thicknesses and materials are substantially the same as those of the first device1(FIGS. 1 to 4) described earlier.

Referring toFIG. 29, a circuit configuration421for operating the fourth device401is shown. The circuit configuration421includes a current source422configured to drive current, I, through the channel408between the leads4122,4123and a voltmeter423configured to measure voltage, V, developed across the same leads4122,4123.A voltage source424is used to apply a bias, VG, to the gate electrode414.

FIG. 30illustrates voltage-current characteristics4341,4342,4343of the fifth device401(FIG. 26) at a gate voltage of 5V and at three different magnetic fields, namely, B=0 mT, +50 mT and −50 mT, applied perpendicular to the side face405(FIG. 24). The measurement is taken using the configuration in which voltage, V, is sensed between the leads4122,4123(FIG. 26) while sweeping current, I, driven through the channel408between the leads4122,4123(FIG. 26).

As shown inFIG. 30, when a gate voltage of 5 V is applied, if a current of 370 μA is applied between the leads4122,4123(FIG. 26), then the change of output voltage (ΔV) measured between the electrodes4122,4123(FIG. 26) is 2.2 mV when the change in applied magnetic field (ΔB) is 50 mT. The output voltage between the second and third leads4122,4123(FIG. 26) increases with increasing current.

The resistance measured between the leads4122,4123(FIG. 26) is about 2.7 kΩ.

Read Head

A slider593supports the read head591and a write head594over a rotatable platen595. The read head591measures magnetic field B produced by a perpendicularly-arranged bit cell596passing beneath it. The read head591may be used in a hard disk drive having longitudinally-arranged bit cells.

It will be appreciated that many modifications may be made to the embodiments hereinbefore described.

A bottom gate structure may be used in which the gate electrode lies under a gate dielectric and the gate dielectric lies under the channel.

A device may include a side gate structure rather than a top gate structure and have a top (or bottom) face instead of a side face such that the side of the channel runs along the top face. For example, a layer of non-ferromagnetic semiconductor material, such as silicon, may be etched to form a side wall and a gate structure comprising a layer of an insulating material and a layer of conductive material may be formed, e.g. grown and/or deposited, over the side wall. The top of the structure may be etched or lapped to define a top face.

The side face may be substantially flat across the whole side of the device. A substantially flat face across the whole side of the device can be conveniently formed by lapping. However, the face, e.g. side face, need not be substantially flat across the whole of the device, e.g. across the whole side of the device. Instead, the side of device may be substantially flat in the vicinity of the channel, gate structure and shunt and form a projection with respect to the rest of the side of the device.

The gate electrode may be doped with an impurity (n-type or p-type) having a concentration of at least about 1×1019cm−3, for example about 1×1021cm−3.

The gate electrode need not comprise silicon, but may be formed from a metal, such as aluminium (Al) or gold (Au), or metal alloy. The gate electrode may include one or more layers. For example, the gate electrode may be a bi-layer, e.g. titanium (Ti) and gold (Au).

The device may be a silicon-based device. For example the channel, shunt and/or the leads may comprise a silicon-containing material, such as silicon or silicon-germanium (e.g. Si0.9Ge0.1)). Different silicon-containing materials can be used in different parts of the device.

Other elemental semiconductors, such as germanium, can be used. Compound semiconductors may be used, such as gallium arsenide (GaAs), indium arsenide (InAs) and indium antimonide (InSb) and other binary semiconductors and tertiary and quaternary semiconductors may be used. Heterostructures, such as AlGaAs/GaAs, may be used.

The channel may be undoped or doped with an impurity (n-type or p-type) up to a concentration of about 1×1015cm−3, up to a concentration of about 1×1016cm−3or up to a concentration of about 1×1017cm−3.

The shunt (if present) and/or the leads may be doped with an impurity (n-type or p-type) having a concentration of at least about 1×1019cm−3, for example about 1×1021cm−3, and/or may comprise one or more δ-doped layers.

The channel and/or shunt and/or leads may have a thickness between about 5 to 50 nm or a thickness between about 50 nm to 100 nm. Furthermore, the channel, shunt and leads may have different thicknesses. Different thicknesses may be achieved by depositing layers of different thicknesses or by masked etching.

The shunt may extend along a portion of the channel, i.e. less than the full length of the channel. The shunt need not be rectangular.

The leads may each have a thickness less than 50 nm. The channel may have a width (i.e. w1) less than 100 nm and/or a length (i.e. l1) less than 10 μm. The shunt may have a width (i.e. w2) up to 500 nm and/or a length (i.e. l2) less than 10 μm which may or may not be the same as the length of the channel. The leads may each have a width (i.e. l3) up to 200 nm, the width being in a direction which corresponds to length for the channel. The leads need not be arranged perpendicularly with respect to the channel. End leads, for example first and sixth leads, may be arranged to approach the channel, e.g. channel, from the ends of the channel, rather than transversely. The leads need not be formed in plane with the channel. At least some of the leads can be arranged above and/or below the channel, i.e. underlie and/or overlie the channel. The device may include leads which are not used. For example, the device may comprise four or more leads, but fewer leads are used for driving and measuring signals through the channel.

An insulating layer which provides electrical insulation can be thicker or thinner than 150 nm.

Other concentrations and mixtures for etches and developers may be used. Other etches, resists and developers may be used. Etching, exposure and development times can be varied and can be found by routine experiment. The anneal temperature may also be found by routine experiment.