ESD-protecting circuit and LSI using the same

An ESD-protecting circuit is connected between a terminal pad and an internal circuit formed in an LSI. The ESD-protecting circuit includes a conductive line connected to the terminal pad; first and second protecting elements, connected to the conductive line; and first and second resistive elements formed on the. The conductive line has a slit that divides the conductive line so that the first and second resistive elements have equal resistive values.

TECHNICAL FIELD OF THE INVENTION

This invention relates generally to an ESD-protecting circuit for protecting an LSI from electrostatic discharge.

BACKGROUND OF THE INVENTION

Recently, an ESD-protecting circuit is used for protecting an internal circuit from electrostatic discharge in an LSI. A conventional ESD-protecting circuit includes a plurality of protecting elements, such as transistors, to draw surge current thereto. However, surge current tends to flow to the transistors unequally, and as a result, the ESD-protecting circuit and/or the internal circuit are damaged.

OBJECTS OF THE INVENTION

Accordingly, an object of the present invention is to provide an improved ESD-protecting circuit, all the protecting elements are used efficiently or in good balance.

SUMMARY OF THE INVENTION

According to a first aspect of the present invention, an ESD-protecting circuit is connected between a terminal pad and an internal circuit formed in an LSI. The ESD-protecting circuit includes first and second conductive lines, connected in parallel to the terminal pad; first and second protecting elements, connected to the first and second conductive lines, respectively; and first and second resistive elements formed on the first and second conductive lines, respectively.

According to a second aspect of the present invention, an LSI includes an I/O terminal pad connected to an external circuit; an internal circuit, comprising an I/O buffer; and an ESD-protecting circuit, connected between the I/O terminal pad and I/O buffer. The ESD-protecting circuit includes first and second conductive lines, connected in parallel to the terminal pad; first and second protecting elements, connected to the first and second conductive lines, respectively; and first and second resistive elements formed on the first and second conductive lines, respectively.

According to a third aspect of the present invention, an LSI includes a power-supply terminal; a ground terminal; a power-supply line connected between the power-supply terminal and ground terminal; an internal circuit, connected to the power-supply line; and an ESD-protecting circuit connected on the power-supply line. The ESD-protecting circuit includes first and second conductive lines, connected in parallel to the terminal pad; first and second protecting elements, connected to the first and second conductive lines, respectively; and first and second resistive elements formed on the first and second conductive lines, respectively.

According to a fourth aspect of the present invention is formed by combining the above described second and third aspects. Namely an LSI includes an I/O terminal pad connected to an external circuit; a power-supply terminal; a ground terminal; a power-supply line connected between the power-supply terminal and ground terminal; an internal circuit, which comprises an I/O buffer and is connected to the power-supply line; a first ESD-protecting circuit, connected between the I/O terminal pad and I/O buffer; and a second ESD-protecting circuit connected on the power-supply line. Each of the first and second ESD-protecting circuit includes first and second conductive lines, connected in parallel to the terminal pad; first and second protecting elements, connected to the first and second conductive lines, respectively; and first and second resistive elements formed on the first and second conductive lines, respectively.

DETAILED DISCLOSURE OF THE INVENTION

FIG. 1is a block diagram showing an LSI10according to the present invention. The LSI10includes an internal circuit12; an I/O terminal pads16and18; ESD protecting circuits20and22, which are connected to the I/O terminal pads16and18, respectively; and I/O buffer circuits24and26, which are arranged in the internal circuit12. The I/O buffer circuits24and26are connected to the ESD protecting circuit20and22, respectively.

FIG. 2is a circuit diagram showing an ESD protecting circuit according to a first preferred embodiment of the present invention.FIG. 3is a schematic diagram showing a layout of the ESD protecting circuit, according to the first preferred embodiment.FIG. 4is a cross sectional view taken on line A—A in FIG.3. The ESD-protecting circuits20and22have the same structure. The ESD-protecting circuit20(22) includes first and second conductive lines30aand30b, connected in parallel to the terminal pad16(18). The conductive lines30aand30bmay be formed as metal patterns. The ESD-protecting circuit20(22) further includes first and second protecting elements34aand34b, connected to the first and second conductive lines30aand30b, respectively. The ESD-protecting circuit20(22) also includes first and second resistive elements32aand32bformed on the first and second conductive lines30aand30b, respectively.

The protecting elements34aand34bare PMOS transistors. As shown inFIG. 3, the first and second conductive lines30aand30bare connected to the drain35aand35bof the PMOS transistors34aand34b, respectively. InFIG. 3, reference numerals36and38represent an active region and a common gate region, respectively. The first and second protecting elements34aand34bare formed on the same active region36. As shown inFIG. 4, the first and second conductive lines30aand30bare formed in the same metal layer39. In other words, the ESD-protecting circuit20(22) is of a single metal-layer type.

Resistance values of the first and second resistive elements32aand32bare adjusted by changing the lengths and thickness of the first and second conductive lines30aand30b. The resistive element32aforms a part of the conductive line30a, while the resistive element32bforms a part of the conductive line30b. The resistance values of the first and second resistive elements32aand32bare controlled so that impedance existing between the pad16and drain35aand impedance existing between the pad16and drain35bbecome equal to each other.

As described above, according to the first preferred embodiment, all the protecting elements34aand34bare used efficiently or in good balance. As a result, concentration of surge current can be prevented, and therefore, the internal circuit12is well protected from electrostatic discharge.

FIGS. 5 and 6are circuit diagrams showing other types of ESD protecting circuits according to the present invention. Referring toFIG. 5, the ESD-protecting circuit20(22) includes first and second conductive lines40aand40b, connected in parallel to the terminal pad16(18). The conductive lines40aand40bmay be formed as metal patterns. The ESD-protecting circuit20(22) further includes first and second protecting elements44aand44b, connected to the first and second conductive lines40aand40b, respectively. The ESD-protecting circuit20(22) also includes first and second resistive elements42aand42bconnected on the first and second conductive lines40aand40b, respectively. The protecting elements44aand44bare diodes. The first and second conductive lines40aand40bare formed in metal layers at a same level.

Referring toFIG. 6, the ESD-protecting circuit20(22) includes first and second conductive lines50aand50b, connected in parallel to the terminal pad16(18). The conductive lines50aand50bmay be formed as metal patterns. The ESD-protecting circuit20(22) further includes first and second protecting elements54aand54b, connected to the first and second conductive lines50aand50b, respectively. The ESD-protecting circuit20(22) also includes first and second resistive elements52aand52bconnected on the first and second conductive lines50aand50b, respectively. The protecting elements54aand54bare NMOS transistors. The first and second conductive lines50aand50bare formed in metal.

FIG. 7is a schematic diagram showing a layout of an ESD protecting circuit according to a second preferred embodiment of the present invention. InFIG. 7, the same or corresponding elements to those shown inFIG. 3are represented by the same reference numerals, and the same description is not repeated. In this embodiment, first and second conductive lines30aand30bare formed by splitting a single conductive line at a part connected to the terminal pad16(18).

In the same manner as the first preferred embodiment, resistance values of the first and second conductive lines30aand30bare adjusted by changing the lengths and thickness thereof so that impedance existing between the pad16and drain35aand impedance existing between the pad16and drain35bbecome equal to each other.

As described above, according to the second preferred embodiment, all the protecting elements34aand34bare used efficiently or in good balance. As a result, concentration of surge current can be prevented, and therefore, the internal circuit12is well protected from electrostatic discharge.

FIG. 8is a schematic diagram showing a layout of an ESD protecting circuit according to a third preferred embodiment of the present invention. InFIG. 8, the same or corresponding elements to those shown inFIGS. 3 and 7are represented by the same reference numerals, and the same description is not repeated. In this embodiment, a first conductive line30ais formed on a first conductive layer, and a second conductive line30bis formed on a second conductive layer, which is formed above the first conductive layer.

In the same manner as the first preferred embodiment, resistance values of the first and second conductive lines30aand30bare adjusted by changing the lengths and thickness thereof so that impedance existing between the pad16and drain35aand impedance existing between the pad16and drain35bbecome equal to each other.

As described above, according to the third preferred embodiment, all the protecting elements34aand34bare used efficiently or in good balance. As a result, concentration of surge current can be prevented, and therefore, the internal circuit12is well protected from electrostatic discharge. In addition, the ESD-protecting circuits20and22can be designed to be smaller in size, because the first and second conductive lines30aand30bare formed on the different layers.

FIG. 9is a circuit diagram showing an ESD protecting circuit according to a fourth preferred embodiment of the present invention.FIG. 10is a schematic diagram showing a layout of the ESD protecting circuit, shown in FIG.9. InFIGS. 9 and 10, the same or corresponding elements to those shown inFIGS. 1-8are represented by the same reference numerals, and the same description is not repeated. In this embodiment, a first conductive line130ais formed on a first conductive layer, and a second conductive line130bis formed on a second conductive layer, which is formed above the first conductive layer.

The ESD-protecting circuit20(22) further includes third and fourth conductive lines130cand130d, serially connected to the first and second conductive lines130aand130b, respectively; third and fourth protecting elements134cand134d, connected to the third and fourth conductive lines130cand130d, respectively; and third and fourth resistive elements132cand132dformed on the third and fourth conductive lines130cand130d, respectively.

The third and fourth conductive lines130cand130dare formed on the first and second conductive layers, respectively. In other words, the first and third conductive lines130aand130cform a first conductive pattern100aon the first metal layer, while the second and fourth conductive lines130band130dform a second conductive pattern100don the second metal layer, as shown in FIG.10.

In the same manner as the first preferred embodiment, resistance values of the first and second conductive patterns100aand100dare adjusted by changing the lengths and thickness thereof so that impedance existing between the pad16and the drains connected to protecting elements134aand134cand impedance existing between the pad16and the drains connected to protecting elements134band134dbecome equal to each other. As described above, according to the fourth preferred embodiment, concentration of surge current can be prevented, and therefore, the internal circuit12is well protected from electrostatic discharge. In addition, the ESD-protecting circuits20and22can be designed to be smaller in size, because the first and second conductive patterns100aand100bare formed on the different layers.

FIG. 11is a circuit diagram showing an ESD protecting circuit according to a fifth preferred embodiment of the present invention.FIG. 12is a schematic diagram showing a layout of the ESD protecting circuit, shown in FIG.11. InFIGS. 11 and 12, the same or corresponding elements to those shown inFIGS. 1-8are represented by the same reference numerals, and the same description is not repeated. In this embodiment, a first conductive line130ais formed on a first conductive layer, and a second conductive line130bis formed on a second conductive layer, which is formed above the first conductive layer.

The ESD-protecting circuit20(22) further includes third and fourth conductive lines130cand130d, connected in parallel to a terminal pad16(18); third and fourth protecting elements134cand134d, connected to the third and fourth conductive lines130cand130d, respectively; and third and fourth resistive elements132cand132dformed on the third and fourth conductive lines130cand130d, respectively. The third and fourth conductive lines130cand130dare formed on the first and second conductive layers, respectively.

In the same manner as the first preferred embodiment, resistance values of the first to fourth conductive lines130a,130b,130cand130dare adjusted by changing the lengths and thickness thereof so that impedance existing between the pad16and the drains of the protecting elements become equal to each other. As described above, according to the fifth preferred embodiment, all the protecting elements134a,134b,134cand134dare used efficiently or in good balance. As a result, concentration of surge current can be prevented, and therefore, the internal circuit12is well protected from electrostatic discharge. In addition, the ESD-protecting circuits20and22can be designed to be smaller in size.

FIG. 13is a block diagram showing another configuration of LSI200according to the present invention. InFIG. 13, the same or corresponding elements to those shown inFIGS. 1-12are represented by the same reference numerals, and the same description is not repeated. The LSI200includes a power-supply terminal206; a ground terminal208, which is grounded; a power-supply line204having supply lines respectively connected to the power-supply terminal206and ground terminal208; an internal circuit12, connected to the power-supply line204; and first to fourth ESD-protecting circuits210a,210b,210cand210dformed on and connected to the power-supply line204. For the first to fourth ESD-protecting circuits210a,210b,210cand210d, one of the ESD-protecting circuits described in the first to fifth preferred embodiments may be selectively used.

According to the LSI200, shown inFIG. 13, concentration of surge current flowing through the power-supply terminal206and/or ground terminal208can be prevented, and therefore, the internal circuit12is well protected from electrostatic discharge.

FIG. 14is a block diagram showing another configuration of LSI300according to the present invention. The LSI300can be fabricated by combining the LSIs shown inFIGS. 1 and 13. InFIG. 14, the same or corresponding elements to those shown inFIGS. 1-13are represented by the same reference numerals, and the same description is not repeated. The LSI300includes a power-supply terminal206; a ground terminal208, which is grounded; a power-supply line204having supply lines respectively connected to the power-supply terminal206and ground terminal208; an internal circuit12connected to the power-supply line204; and first to fourth ESD-protecting circuits210a,210b,210cand210dformed on and connected to the power-supply line204.

The LSI300further includes I/O terminal pads16and18connected to an external circuit. The internal circuit12includes I/O buffers24and26. The ESD-protecting circuit20is connected between the I/O terminal pad16and the I/O buffer24, while the ESD-protecting circuit22is connected between the I/O terminal pad18and the I/O buffer26.

For the ESD-protecting circuits20,22,210a,210b,210cand210d, one of the ESD-protecting circuits described in the first to fifth preferred embodiments may be selectively used.

According to the LSI300, shown inFIG. 14, concentration of surge current flowing through the terminal pads16,18,206and208can be prevented, and therefore, the internal circuit12is well protected from electrostatic discharge.