Data storage device and operating method thereof

A method for operating a data storage device, the method comprising: enqueuing requests for a nonvolatile memory device, received from a host device, in a first queue; determining whether a starvation time of a request which is not enqueued in a second queue and has a relatively low priority, among the requests queued in the first queue is reaching to a predetermined response time; and enqueuing, based on a determination result, any one between the request which has the low priority and a request which is not enqueued in the second queue and has a high priority among the requests queued in the first queue, in the second queue.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) to Korean application number 10-2017-0046530, filed on Apr. 11, 2017, which is herein incorporated by reference in its entirety.

BACKGROUND

1. Technical Field

Various embodiments generally relate to a data storage device which uses a nonvolatile memory device as a storage medium.

2. Related Art

Recently, the paradigm for the computer environment has been changed into ubiquitous computing so that computer systems can be used anytime and anywhere. Accordingly, the use of portable electronic devices such as mobile phones, digital cameras, and notebook computers has rapidly increased. In general, portable electronic devices use a data storage device which uses a memory device. A data storage device is used to store data to be used in a portable electronic device.

A data storage device using a memory device has excellent stability and durability since it does not include a mechanical driving unit. Also, a data storage device using a memory device is advantageous in that it may access data faster and consume less power. Non-limiting examples of a data storage device having such advantages include a universal serial bus (USB) memory device, memory cards having various interfaces, a universal flash storage (UFS) device, and a solid state drive (SSD).

SUMMARY

Various embodiments are directed to a data storage device which is capable of reordering a request from a host device in such a manner that the request may be processed efficiently, and an operating method thereof.

In an embodiment, a method for operating a data storage device, the method comprising: enqueuing requests for a nonvolatile memory device, received from a host device, in a first queue; determining whether a starvation time of a request which is not enqueued in a second queue and has a relatively low priority, among the requests queued in the first queue is reaching to a predetermined response time; and enqueuing based on a determination result, any one between the request which has the low priority and a request which is not enqueued in the second queue and has a high priority among the requests queued in the first queue, in the second queue.

In an embodiment, a data storage device may include: a first queue suitable for queuing requests received from a host device; a second queue suitable for queuing some of the requests queued in the first queue; and a host interface unit suitable for enqueuing the requests queued in the first queue, in the second queue such that the requests are reordered, wherein the host interface unit determines a degree to which a starvation time of a request which is not enqueued in a second queue and has a relatively low priority, among the requests queued in the first queue is reaching to a predetermined response time, and enqueues, based on a determination result, any one between the request which has the low priority and a request which is not enqueued in the second queue and has a high priority among the requests queued in the first queue, in the second queue.

According to the embodiments, a request from a host device may be processed efficiently.

DETAILED DESCRIPTION

In the present invention, advantages, features and methods for achieving them will become more apparent after a reading of the following exemplary embodiments taken in conjunction with the drawings. The present invention may, however, be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided to describe the present invention in detail to the extent that a person skilled in the art to which the invention pertains can easily enforce the technical concept of the present invention.

It is to be understood herein that embodiments of the present invention are not limited to the particulars shown in the drawings and that the drawings are not necessarily to scale and in some instances proportions may have been exaggerated in order to more clearly depict certain features of the invention. While particular terminology is used herein, it is to be appreciated that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the present invention.

As used herein, the term “and/or” includes any and ail combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being “on,” “connected to” or “coupled to” another element, it may be directly on, connected or coupled to the other element or intervening elements may be present. As used herein, a singular form is intended to include plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “includes” and/or “including,” when used in this specification, specify the presence of at least one stated feature, step, operation, and/or element, but do not preclude the presence or addition of one or more other features, steps, operations, and/or elements thereof.

Hereinafter, a data storage device and an operating method thereof will be described below with reference to the accompanying drawings through various examples of embodiments.

FIG. 1is a block diagram illustrating a data storage device100in accordance with an embodiment. Referring toFIG. 1, the data storage device100may store data to be accessed by a host device400such as a mobile phone, an MP3 player, a laptop computer, a desktop computer, a game player, a television (TV), an in-vehicle infotainment system, and so forth. The data storage device100may also be referred to as a memory system.

The data storage device100may be implemented with any one among various types of storage devices according to a host interface HIF meaning a transmission protocol with respect to the host device400. For example, the data storage device100may be implemented with any one of various types of storage devices such as a solid state drive (SSD), a multimedia card such as an MMC, an eMMC, an RS-MMC and a micro-MMC, a secure digital card such as SD, a mini-SD and a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnection (PCI) card type storage device, a PCI express (PCI-e) card type storage device, a compact flash (CF) card, a smart media card, a memory stick, and so forth.

The data storage device100may be implemented with any one among various types of package types. For example, the data storage device100may be manufactured as any one of various kinds of package types such as a package-on-package (POP), a system-in-package (SIP), a system-on-chip (SOC), a multi-chip package (MCP), a chip-on-board (COB), a wafer-level fabricated package (WFP) and a wafer-level stack package (WSP).

The data storage device100may include a nonvolatile memory device200and a controller300. The nonvolatile memory device200may be coupled with the controller300through a channel CH which includes at least one signal line capable of transmitting a command, an address, control signals and data. The nonvolatile memory device200may be used as the storage medium of the data storage device100.

The nonvolatile memory device200may be configured by any one of various types of nonvolatile memory devices such as a NAND flash memory device, a NOR flash memory device, a ferroelectric random access memory (FRAM) using a ferroelectric capacitor, a magnetic random access memory (MRAM) using tunneling magneto-resistive (TMR) layer, a phase change random access memory (PCRAM) using a chalcogenide alloy, and a resistive random access memory (RERAM) using a transition metal oxide. The ferroelectric random access memory (FRAM) the magnetic random access memory (MRAM), the phase change random access memory (PCRAM) and the resistive random access memory (RERAM) are a kind of nonvolatile random access memory devices capable of random access to memory cells. The nonvolatile memory device200may be configured by a combination of a NAND flash memory device and the above-described various types of nonvolatile random access memory devices.

The controller300may include a host interface unit310, a second queue320, a control unit330, a working memory340, and a memory control unit350. The host interface unit310may include a first queue311.

The host interface unit310may interface the host device400with the data storage device100. For example, the host interface unit310may communicate with the host device400by using the host interface HIF, that is, any one among standard transmission protocols such as universal serial bus (USB), universal flash storage (UFS), multimedia card (MMC), parallel advanced technology attachment (PATA), serial advanced technology attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI) and PCI express (PCI-e) protocols.

The host interface unit310may perform a request queuing operation or a command queuing operation. The host interface unit310may receive a request from the host device400, and enqueue the received request in the first queue311. The host interface unit310may enqueue some of requests queued in the first queue311, in the second queue320. The host interface unit310may enqueue the requests queued in the first queue311, in the second queue320, such that the requests queued in the first queue311may be reordered based on various references.

The host interface unit310may include a function block which is needed for a request queuing operation based on a starvation of a request, for example, a timer313.

The second queue320may be coupled between the host interface unit310and the control unit330. The second queue320may be used for request exchange between the host interface unit310and the control unit330. The second queue320may be configured in the type of a linked queue or a circular queue.

The control unit330may be implemented with a micro control unit (MCU) or a central processing unit (CPU). The control unit330may process a request queued in the second queue320. In order to process the request, the control unit330may drive an instruction or algorithm of a code type, that is, a software, loaded in the working memory340, and may control internal function blocks or the nonvolatile memory device200.

The control unit330may notify the host interface unit310that there is a processing-completed request. For example, as shown inFIG. 2, the control unit330may notify processing completion of a request in such a way as to record a completion flag CF in an area Q21of the second queue320in which processing-completed request is queued. On the other hand, the remaining areas Q22, Q23and Q24of the second queue320are areas corresponding to processing standby requests. For another example, as shown inFIG. 3, the control unit330may notify processing completion of a request in such a way as to transmit an interrupt ITR to the host interface unit310.

The working memory340may be implemented with a random access memory such as a dynamic random access memo (DRAM) or a static random access memory (SRAM). The working memory340may store a software to be driven by the control unit330. Also, the working memory340may store the data needed to drive the software.

The memory control unit350may control the nonvolatile memory device200according to control of the control unit330. The memory control unit350may also be referred to as a memory interface unit. The memory control unit350may provide control signals to the nonvolatile memory device200. The control signals may include a command, an address, a control signal and so forth for controlling the nonvolatile memory device200. The memory control unit350may provide data to the nonvolatile memory device200or may be provided with the data read out from the nonvolatile memory device200.

FIG. 4is a diagram illustrating a request queuing operation based on a reception order of a request in accordance with an embodiment. As an example, a state in which five requests RQ1to RQ5are received from the host device400is illustrated inFIG. 4. For example, the request queuing operation ofFIG. 4may be performed by the data storage device100ofFIG. 1.

Referring toFIG. 4, the host interface unit310may enqueue the requests RQ1to RQ5in the first queue311in a sequence in which they are received. For example, the host interface unit310may enqueue the requests RQ1to RQ5in areas Q11to Q15of the first queue311, respectively. The host interface unit310may queue the requests RQ1to RQ5queued in the first queue311, in the second queue320in the sequence in which they are received. For example, the host interface unit310may queue the requests RQ1to RQ4in the second queue320. That is, the host interface unit310may enqueue the requests RQ1to RQ4in areas Q21to Q24of the second queue320, respectively.

The control unit330may process the requests RQ1to RQ4which are queued in the second queue320, in a sequence in which they are queued. For example, the control unit330may process the requests RQ1to RQ4in the sequence of the first request RQ1to the fourth request RQ4. If processing of the first request RQ1is completed, the host interface unit310may queue the remaining request queued in the first queue311, that is, the fifth request RQ5, in the second queue320.

FIG. 5is a diagram illustrating a request queuing operation based on a priority of a request in accordance with an embodiment. For example, a state in which seven requests RQ1to RQ7are received from the host device400is illustrated inFIG. 5. For example, the request queuing operation ofFIG. 5may be performed by the data storage device100ofFIG. 1.

Referring toFIG. 5, the host interface unit310may enqueue the requests RQ1to RQ7in the first queue311in a sequence in which they are received. For example, the host interface unit310may enqueue the requests RQ1to RQ7in areas Q11to Q17of the first queue311, respectively. The requests RQ6and RQ7are requests having relatively high priorities, and the requests RQ1to RQ5are requests having low priorities. The host interface unit310may queue the requests RQ1to RQ7queued in the first queue311, in the second queue320, such that requests may be reordered based on priorities of the requests. For example, the host interface unit310may respectively queue the requests RQ6and RQ7having high priorities, in areas Q21and Q22of the second queue320. Then, the host interface unit310may respectively queue the requests RQ1and RQ2having low priorities, in areas Q23and Q24of the second queue320, in the sequence in which they are received.

The control unit330may process the requests RQ6, RQ7, RQ1and RQ2which are queued in the second queue320, in a sequence in which they are queued. For example the control unit330may process the requests RQ6, RQ7, RQ1and RQ2in the sequence of the sixth request RQ6, the seventh request RQ7, the first request RQ1and the second request RQ2. As processing of the requests RQ6, RQ7, RQ1and RQ2is completed, the host interface unit310may queue the remaining requests queued in the first queue311, that is, the requests RQ3to RQ5, in the second queue320, in the sequence in which they are received.

If requests are reordered based on priorities of the requests, the requests RQ6and RQ7having high priorities may be processed first, and the requests RQ1to RQ5having low priorities may be processed later.

FIG. 6is a diagram illustrating a request queuing operation based on a processing time of a request in accordance with an embodiment. For example, a state in which four requests RQ1to RQ4are received from the host device400is illustrated inFIG. 6, For example, the request queuing operation ofFIG. 6may be performed by the data storage device100shown inFIG. 1.

Referring toFIG. 6, the host interface unit310may enqueue the requests RQ1to RQ4in the first queue311in a sequence in which they are received. For example, the host interface unit310may enqueue the requests RQ1to RQ4in areas Q11to Q14of the first queue311, respectively. The requests RQ1, RQ3and RQ4are requests having relatively short processing time, and the request RQ2is a request having relatively long processing time. The host interface unit310may queue the requests RQ1to RQ4queued in the first queue311, in the second queue320, such that requests may be reordered based on processing times of the requests. For example, the host interface unit310may respectively queue the requests RQ1, RQ3and RQ4having short processing times, in areas Q21to Q23of the second queue320. Then, the host interface unit310may queue the request. RQ2having a long processing time, in area Q24of the second queue320.

The control unit330may process the requests RQ1to RQ4which are queued in the second queue320, in a sequence in which they are queued. For example, the control unit330may process the requests RQ1to RQ4in the sequence of the first request RQ1, the third request RQ3, the fourth request RQ4and the second request RQ2.

If requests are reordered based on processing times of the requests, the requests RQ1, RQ3and RQ4, for example, read requests, having short processing times may be processed first, and the request RQ2, for example, a write request, having a long processing time may be processed later.

FIGS. 7 to 10are diagrams illustrating examples of a request queuing operation based on a starvation of a request in accordance with an embodiment. For example, the request queuing operation ofFIGS. 7 to 10may be performed by the data storage device100shown inFIG. 1.

Referring toFIG. 7, as an example, a state n which five requests RQ1to RQ5having low priorities are respectively queued in areas Q11to Q15of the first queue311four requests RQ1to RQ4among them are respectively queued in areas Q21to Q24of the second queue320and then one request RQ6having a high priority is received from the host device400is illustrated. Moreover, a state in which the first request RQ1among the requests RQ1to RQ4queued in the second queue320is completely processed is illustrated.

According to these states, the host interface unit310should enqueue, in the second queue320, any one between the requests RQ5and RQ6which are not enqueued in the second queue320among the requests RQ1to RQ6queued in the first queue311. In this case, the host interface unit310may enqueue any one of the requests RQ5and RQ6, in the second queue320, based on priorities of the requests RQ5and RQ6. Alternatively, the host interface unit310may enqueue any one of the requests RQ5and RQ6, in the second queue320, such that the requests RQ5and RQ6are reordered based on a starvation of a request.

The host interface unit310may determine a degree to which the starvation time of the fifth request RQ5not enqueued in the second queue320and having a low priority among the requests RQ1to RQ6queued in the first queue311is imminent to a response time, and may enqueue, in the second queue320, any one of the fifth request RQ5having a low priority and the sixth request RQ6having a high priority, based on a determination result.

Referring toFIG. 8, the host interface unit310may determine starvation starvation time Tstrv_RQ5of the fifth request RQ5which is not enqueued in the second queue320and has a low priority. For example, the host interface unit310may count a time that is passed from a point of time at which the fifth request RQ5is received from the host device400, through the timer313. Therefore, the starvation time Tstrv_RQ5of the fifth request RQ5may mean a time by which processing of the fifth request RQ5is delayed.

While only the starvation time Tstrv_RQ5of the fifth request RQ5has been described, respective starvation times of all the requests received from the host device400may be managed by the host interface unit310.

The host interface unit310may determine a processing time Tprcs_RQ1of the first request RQ1which is completely processed among the requests RQ1to RQ4queued in the second queue320. For example, the host interface unit310may count a time that is passed from a point of time at which the first request. RQ1is queued in the second queue320to a point of time at which processing completion of the first request RQ1is notified from the control unit330, through the timer313. Thus, the processing time Tprcs_RQ1of the first request. RQ1may mean a time that is passed to process the first request RQ1.

The host interface unit310may compare the difference between the starvation time Tstrv_RQ5of the fifth request RQ5and the processing time Tprcs_RQ1of the first request RQ1with a reference time Tref. The host interface unit310may determine a degree to which the response time of the fifth request RQ5is imminent, based on a comparison result.

A response time may mean a time limit within which the data storage device100should send a response to a request after the request is transmitted from the host device400. The response time may be a time that is prescribed according to the transmission protocol between the host device400and the data storage device100.

The host interface unit310may set a time that is obtained by subtracting an average processing time of previously processing-completed requests from the response time, as the reference time Tref. Therefore, the reference time Tref may be a time shorter than the response time.

When the difference between the starvation time Tstrv_RQ5of the fifth request RQ5and the processing time Tprcs_RQ1of the first request RQ1is less than the reference time Tref, the host interface unit310may determine that the response time of the fifth request RQ5is imminent. Based on such a determination result, as shown inFIG. 9, the host interface unit310may enqueue the fifth request RQ5in the second queue320before the sixth request RQ6even though the priority of the fifth request RQ5is lower than the priority of the sixth request RQ6.

When the difference between the starvation time Tstrv_RQ5of the fifth request RQ5and the processing time Tprcs_RQ1of the first request RQ1is equal to or greater than the reference time Tref, the host interface unit310may determine that the response time of the fifth request RQ5is not imminent. Based on such a determination result, as shown inFIG. 10, the host interface unit310may enqueue the sixth request RQ6having a high priority in the second queue320based on priorities of the requests RQ5and RQ6.

FIG. 11is a diagram illustrating a data processing system1000including a solid state drive (SSD)1200in accordance with an embodiment. Referring toFIG. 11, the data processing system1000may include a host device1100and the SSD1200.

The SSD1200may include a controller1210, a buffer memory device1220, a plurality of nonvolatile memory devices1231to123n, a power supply1240, a signal connector1250, and a power connector1260.

The controller1210may control general operations of the SSD1200. The controller1210may include a host interface unit1211, a control unit1212, a random access memory1213, an error correction code (ECC) unit1214, and a memory interface unit1215.

The host interface unit1211may exchange a signal SGL with the host device1100through the signal connector1250. The signal SGL may include a command, an address, data, and so forth. The host interface unit1211may interface the host device1100and the SSD1200according to the protocol of the host device1100. For example, the host interface unit1211may communicate with the host device1100through any one of standard interface protocols such as secure digital, universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), personal computer memory card international association (PCMCIA), parallel advanced technology attachment (PITA), serial advanced technology attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI express (PCI-E) and universal flash storage (UFS).

The control unit1212may analyze and process the signal SGL received from the host device1100. The control unit1212may control operations of internal function blocks according to a firmware or a software for driving the SSD1200. The random access memory1213may be used as a working memory for driving such a firmware or software.

The ECC unit1214may generate the parity data of data to be transmitted to at least one of the nonvolatile memory devices1231to123n. The generated parity data may be stored together with the data in the nonvolatile memory devices1231to123n. The ECC unit1214may detect an error of the data read from at least one of the nonvolatile memory devices1231to123n, based on the parity data. If a detected error is within a correctable range, the ECC unit1214may correct the detected error.

The memory interface unit1215may provide control signals such as commands and addresses to at least one of the nonvolatile memory devices1231to123n, according to control of the control unit1212. Moreover, the memory interface unit1215may exchange data with at least one of the nonvolatile memory devices1231to123n, according to control of the control unit1212. For example, the memory interface unit1215may provide the data stored in the buffer memory device1220, to at least one of the nonvolatile memory devices1231to123nor provide the data read from at least one of the nonvolatile memory devices1231to123n, to the buffer memory device1220.

The buffer memory device1220may temporarily store data to be stored in at least one of the nonvolatile memory devices1231to123n. Further, the buffer memory device1220may temporarily store the data read from at least one of the nonvolatile memory devices1231to123n. The data temporarily stored in the buffer memory device1220may be transmitted to the host device1100or at least one of the nonvolatile memory devices1231to123naccording to control of the controller1210.

The nonvolatile memory devices1231to123nmay be used as storage media of the SSD1200. The nonvolatile memory devices1231to123nmay be coupled with the controller1210through a plurality of channels CH1to CHn, respectively. One or more nonvolatile memory devices may be coupled to one channel. The nonvolatile memory devices coupled to each channel may be coupled to the same signal bus and data bus.

The power supply1240may provide power PWR inputted through the power connector1260, to the inside of the SSD1200. The power supply1240may include an auxiliary power supply1241. The auxiliary power supply1241may supply power to allow the SSD1200to be normally terminated when a sudden power-off occurs. The auxiliary power supply1241may include large, capacity capacitors.

The signal connector1250may be configured by various types of connectors depending on an interface scheme between the host device1100and the SSD1200.

The power connector1260may be configured by various types of connectors depending on a power supply scheme of the host device1100.

FIG. 12is a diagram illustrating a data processing system2000including a data storage device2200in accordance with an embodiment. Referring toFIG. 12, the data processing system2000may include a host device2100and the data storage device2200.

The host device2100may be configured in the form of a board such as a printed circuit board. Although not shown, the host device2100may include internal function blocks for performing the function of a host device.

The host device2100may include a connection terminal2110such as a socket, a slot or a connector. The data storage device2200may be mounted to the connection terminal2110.

The data storage device2200may be configured in the form of a board such as a printed circuit board. The data storage device2200may be referred to as a memory module or a memory card. The data storage device2200may include a controller2210, a buffer memory device2220, nonvolatile memory devices2231and2232, a power management integrated circuit (PMIC)2240, and a connection terminal2250.

The controller2210may control general operations of the data storage device2200. The controller2210may be configured in the same manner as the controller1210shown inFIG. 11.

The buffer memory device2220may temporarily store data to be stored in the nonvolatile memory devices2231and2232. Further, the buffer memory device2220may temporarily store the data read from the nonvolatile memory devices2231and2232. The data temporarily stored in the buffer memory device2220may be transmitted to the host device2100or the nonvolatile memory devices2231and2232according to control of the controller2210.

The nonvolatile memory devices2231and2232may be used as storage media of the data storage device2200.

The PMIC2240may provide the power inputted through the connection terminal2250, to the inside of the data storage device2200. The PMIC2240may manage the power of the data storage device2200according to control of the controller2210.

The connection terminal2250may be coupled to the connection terminal2110of the host device2100. Through the connection terminal2250, signals such as commands, addresses, data and so forth and power may be transferred between the host device2100and the data storage device2200. The connection terminal2250may be configured into various types depending on an interface scheme between the host device2100and the data storage device2200. The connection terminal2250may be disposed on any one side of the data storage device2200.

FIG. 3is a diagram illustrating a data processing system3000including a data storage device3200in accordance with an embodiment. Referring toFIG. 13, the data processing system3000may include a host device3100and the data storage device3200.

The host device3100may be configured in the form of a board such as a printed circuit board. Although not shown, the host device3100may include internal function blocks for performing the function of a host device.

The data storage device3200may be configured in the form of a surface-mounting type package. The data storage device3200may be mounted to the host device3100through solder balls3250. The data storage device3200may include a controller3210, a buffer memory device3220, and a nonvolatile memory device3230.

The controller3210may control general operations of the data storage device3200. The controller3210may be configured in the same manner as the controller1210shown inFIG. 11.

The buffer memory device3220may temporarily store data to be stored in the nonvolatile memory device3230. Further, the buffer memory device3220may temporarily store the data read from the nonvolatile memory device3230. The data temporarily stored in the buffer memory device3220may be transmitted to the host device3100or the nonvolatile memory device3230according to control of the controller3210.

The nonvolatile memory device3230may be used as the storage medium of the data storage device3200.

FIG. 14is a diagram illustrating a network system4000including a data storage device4200in accordance with an embodiment. Referring toFIG. 14, the network system4000may include a server system4300and a plurality of client systems4410to4430which are coupled through a network4500.

The server system4300may service data in response to requests from the plurality of client systems4410to4430. For example, the server system4300may store the data provided from the plurality of client systems4410to4430. For another example, the server system4300may provide data to the plurality of client systems4410to4430.

The server system4300may include a host device4100and the data storage device4200. The data storage device4200may be configured by the data storage device100shown inFIG. 1, the data storage device1200shown inFIG. 11, the data storage device2200shown inFIG. 12or the data storage device3200shown inFIG. 13.

FIG. 15is a block diagram illustrating a nonvolatile memory device200included in a data storage device in accordance with an embodiment. Referring toFIG. 15, the nonvolatile memory device200may include a memory cell array210, a row decoder220, a data read/write block230, a column decoder240, a voltage generator250, and a control logic260.

The memory cell array210may include memory cells MC which are arranged at areas where word lines WL1to WLm and bit lines BL1to BLn intersect with each other.

The row decoder220may be coupled with the memory cell array210through the word lines WL1to WLm. The row decoder220may operate according to control of the control logic260. The row decoder220may decode an address provided from an external device (not shown). The row decoder220may select and drive the word lines WL1to WLm, based on a decoding result. For instance, the row decoder220may provide a word line voltage provided from the voltage generator250, to the word lines WL1to WLm.

The data read/write block230may be coupled with the memory cell array210through the bit lines BL1to BLn. The data read/write block230may include read/write circuits RW1to RWn respectively corresponding to the bit lines BL1to BLn. The data read/write block230may operate according to control of the control logic260. The data read/write block230may operate as a write driver or a sense amplifier according to an operation mode. For example, the data read/write block230may operate as a write driver which stores data provided from the external device, in the memory cell array210in a write operation. For another example, the data read/write block230may operate as a sense amplifier which reads out data from the memory cell array210in a read operation.

The column decoder240may operate according to control of the control logic260. The column decoder240may decode an address provided from the external device. The column decoder240may couple the read/write circuits RW1to RWn of the data read/write block330respectively corresponding to the bit lines BL1to BLn with data input/output lines or data input/output buffers, based on a decoding result.

The voltage generator250may generate voltages to be used in internal operations of the nonvolatile memory device200. The voltages generated by the voltage generator250may be applied to the memory cells of the memory cell array210. For example, a program voltage generated in a program operation may be applied to a word line of memory cells for which the program operation is to be performed. For another example, an erase voltage generated in an erase operation may be applied to a well area of memory cells for which the erase operation is to be performed. For still another example, a read voltage generated in a read operation may be applied to a word line of memory cells for which the read operation is to be performed.

The control logic260may control general operations of the nonvolatile memory device200, based on control signals provided from the external device. For example, the control logic260may control operations of the nonvolatile memory device200such as read, write and erase operations of the nonvolatile memory device200.

While various embodiments have been described above, it will be understood to those skilled in the art that the embodiments described are examples only. Accordingly, the data storage device and the operating method thereof described herein should not be limited based on the described embodiments.