Low voltage non-volatile memory cells using twin bit line current sensing

A non-volatile memory cell operating at low voltage by means of impact ionization for programming. Impact ionization arises from a charge injector, such as a diode, created in the substrate of a floating gate charge storage transistor. The charge supply is biased by push-pull voltages applied to the charge storage transistor, while another floating gate transistor assists in reading the charge state of the charge storage transistor. The other transistor switches current from a sense transistor associated with a sense line, the current switching between two bit lines depending on the charge state of the charge storage transistor. In other words, the switched current appears in one of two bit lines, one bit line indicating stored charge and the other indicating the absence of stored charge, i.e. digital zero and one, positively indicated in the two bit lines.

TECHNICAL FIELD

The invention relates to non-volatile memory transistors and, in particular, to non-volatile memory cells operating at low voltage.

BACKGROUND ART

Impact ionization has been known for several years. U.S. Pat. No. 4,432,075 to B. Eitan and U.S. Pat. No. 4,821,236 to Hayashi et al. describe an EEPROM transistor adjacent to a charge generator, creating a substrate current near the EEPROM, creating excess charge or holes, resembling space charge, near subsurface electrodes of the EEPROM. Assume that the holes are generated and accelerated toward one of the electrodes of the EEPROM. Resulting secondary electrons are sufficiently energetic to penetrate gate oxide over the substrate and become injected into a conductive floating gate. For EEPROMs, the floating gate becomes charged by band-to-band tunneling, a situation which eliminates the need for a control gate over the floating gate. It is known that EEPROMs using impact ionization require lower voltages for programming and erasing compared to conventional EEPROMs that can require 12 volts or more for programming.

U.S. Pat. No. 4,334,292 discloses a non-volatile memory cell employing at least two bit lines for programming and reading the cell. Charge injector regions are employed to reduce voltage supply levels for the memory cell.

U.S. Pat. No. 4,821,236 shows a subsurface injector region that generates charge for storage on a floating gate of a non-volatile memory cell. See also U.S. Pat. No. 6,125,053 regarding impact ionization.

One of the problems encountered in manufacturing EEPROMs is generating the high voltages required for programming. Where only low voltages are available, charge pumps, or the like, are typically employed to supply internal programming voltages. Charge pumps occupy valuable die area and require ancillary timing circuits for operating switches associated with the charge pumps. In turn, the timing circuits can require adjustment, needing other ancillary circuits. Similarly, circuits for reading EEPROMs require high voltages on control gates to drive charge from floating gates. Voltage must be high enough to obtain sufficient current flow that can be read. Once again, voltage increasing circuits must be used where only low voltage power supplies are employed.

An object of the invention was to devise an EEPROM architecture operating on very low voltages, yet not employing charge pumps or the like.

SUMMARY OF THE INVENTION

The above object has been achieved with an EEPROM transistor that can be programmed and read with very low voltages in metal-oxide-semiconductor (MOS) technology, the read operation using two parallel bit lines, one signalling digital one and the other signalling digital zero. Charge storage is stimulated in this environment by creating a virtual diode, formed by reverse biasing of a source or drain of a PMOS transistor, or an NMOS transistor in a P-well, establishing a polarity that allows electrons to emerge from the source or drain having a current flowing to the substrate and elsewhere. This reverse biasing is an effective p-n junction, similar to a virtual diode and a counterflow of holes that impinge upon the source or drain, giving rise to free electrons. Some of these electrons are pushed toward a control gate above a floating gate. At the same time, a charge attractive low voltage on the control gate pulls charge onto the floating gate where it is stored, indicative of a data state, such as a 1 or 0, providing a novel push-pull bias voltage arrangement.

To erase the charge storage transistor, an opposite voltage is applied to the control gate which drives charge from the floating gate into the grounded substrate. To read the charge storage transistor a second transistor is required, acting as a switch, and a third transistor that acts as a sense transistor. When the charge storage transistor is charged, the channel of the switch transistor will block conduction from the sense transistor and current flows through the switch transistor into a first bit line. When the charge storage transistor is not charged, the channel of the storage transistor is available for conduction and current from the select transistor flows through the charge storage transistor into a second bit line. Accordingly, a current pulse in the first bit line indicates that the storage transistor is charged, signalling a first data state, while a current pulse in the second bit line indicates no charge in the storage transistor, indicative of a second data state.

The charge storage and switch transistors are constructed similarly but only one transistor is charged because it has a subsurface p-n junction used for charging the cell. The switch transistor, while appearing to have a floating gate, uses the apparent floating gate to attenuate control gate voltage on the channel. There is enough voltage influence on the channel of the switch transistor to allow conduction when the channel of the charge storage transistor is blocked by charge on its floating gate. There is no charge storage on the floating gate of the switch transistor. Since the floating gate of the switch transistor is floating, it will communicate an electric field from the control gate to the channel to govern the switching characteristic of the transistor. With small geometries, all bias voltages are 3.0 volts or less and preferably below 2.5 volts and with ultra small geometries below 2.0 volts.

BEST MODE FOR CARRYING OUT THE INVENTION

With reference toFIG. 1, two CMOS floating gate transistors are shown, including a first floating gate transistor11and a second floating gate transistor13. Transistor11has a source21, a control gate23, a drain25, and a floating gate27. Transistor13has a source31, a control gate33, a drain35, and a floating gate37.

Drain25of first transistor11is electrically connected to bit line41that runs through all memory cells in a column of a memory array. Control gate23is connected to word line45and also to control gate33of second transistor13. Source21of first transistor11is connected to source31of second transistor13and to the source53of CMOS transistor51at node39. The control gate55of CMOS transistor51is a select line for the memory array. A drain57of CMOS transistor51is connected to a sense line59running through a memory array of cells of the kind shown inFIG. 1in a direction parallel to rows of the memory cells. An n-well in which the p-type transistors are built serves as a grounding point10with a ground terminal12.

Second floating gate transistor13has its drain electrode35connected to bit line43. The two bit lines41and43are parallel and are each connected to a drain electrode of one of the floating gate transistors11and13, respectively. In the program and erase modes of operation, the bit lines are used to apply bias. In the read mode of operation, the bit lines signal the presence and absence of charge on the charge storage floating gate transistor11.FIG. 1, showing the program mode of operation, has negative voltage, −V, on bit line41and positive voltage, +V, on word line45. Sense line59is floating. The only requirement on voltage V is that it exceed the threshold voltage of the CMOS transistors.

Both floating gate transistors11and13are manufactured similarly and simultaneously. Both employ a stripe of poly1for the floating gates. In insulated relation above the floating gate stripe is a stripe of poly2for the control gates. In use, floating gate transistor11is used for charge storage and floating gate transistor13is not. The charge storage aspect of floating gate transistor11arises from grounding the substrate of floating gate transistor11, or otherwise applying a VDDvoltage at node12to cause electron flow out of the drain. This electron flow simulates a diode, termed a virtual diode, that arises from the p-n junction stimulated by the negative voltage, −V, applied to the p-type drain25, sweeping electrons out of the drain region. The existence of such diodes in PMOS transistors biased by a negative drain voltage is known as PMOS enhancement transistor action. When transistor dimensions are reduced to micron size dimensions, electrons not only flow to ground but are influenced by a positive control gate voltage, +V, on control gate23.

InFIG. 2, the control gate23in PMOS transistor11has a positive voltage, +V, applied to word line45. A negative voltage, −V, is applied on bit line41to subsurface drain electrode25driving off electrodes, thereby making the region p+. A virtual diode30exists between ground40and drain25. Drain25is bounded by isolation region18and upper surface16of the n-well below where the drain25resides. Electrons are swept out of the n-well20and flow through the diode30toward ground40. Some electrons in n-well20, as well as drain25, experience an electric field from the positive voltage applied to word line45. This causes electron injection into the thin oxide insulation layer22, typically a very thin oxide layer resembling tunnel oxide, with electrons moving on to floating gate27, as indicated by arrows A.

Note that transistor13inFIG. 1has no similar negative voltage applied on bit line43and so drain35does not form a virtual diode. Returning toFIG. 2, the floating gate27is spaced from the control gate23by an insulative layer24. Control gate23is conductive, preferably made of poly, i.e. a poly2layer. The floating gate27is also made of poly, i.e. a poly1layer. Transistor13is fabricated similarly. In summary, when a negative voltage, −V, is applied to bit line41and a positive voltage, +V, is applied to word line45, charge flows across thin oxide layer22onto floating gate27. Charge on floating gate27indicates a logic state, such as a digital zero or a digital one. The charge flow mechanism can be hot electron transfer, Fowler-Nordheim tunneling, or band-to-band tunneling. Electrons are available as space charge generated as a result of impact ionization. Hot electrons may have enough kinetic energy to overcome the tunnel barrier and move onto the floating gate, accelerated by the positive voltage, +V, on control gate23such that penetration of oxide layer22occurs moving the electrons onto floating gate27. Other tunneling mechanisms can be simultaneously operative.

InFIG. 3, reading of the floating gate charge storage transistor is illustrated in the situation where there is charge stored on the floating gate charge storage transistor. A low positive voltage, approximately 1.8 volts, is applied to word line45and select line45. A positive voltage above threshold, +V, is applied momentarily to line59. This causes select transistor51to conduct current toward node39. Charge on the floating gate charge storage transistor draws holes into the channel of transistor11causing transistor11to conduct into bit line41, indicated by path B. Thus, current in bit line41occurring after pulsing sense line59with a positive voltage, indicates that floating gate charge storage transistor11is charged. Note that switching transistor13is a high resistance path to current flow compared to path B.

When the floating gate charge storage transistor is not charged and the same voltages are applied to lines45,55and59, then the floating gate charge storage transistor is essentially open because the channel does not permit conduction. Conduction by select transistor51causes the voltage at node39to be almost the same as the voltage on select line55. This voltage, say +1.8 V, is about the same as the voltage applied to word line45. Voltage on word line45induces a similar voltage on floating gate of switching transistor13, creating a conductive channel into the floating bit line43, with current flow indicated by the path C. Switching transistor13now provides a low resistance path for current while the current path through the floating gate charge storage transistor11is blocked. Current in bit line43occurring after sense line59is pulsed with a positive voltage indicates that the floating gate charge storage transistor11is not charged.

An erase operation is illustrated inFIG. 5where negative voltage, −V, is applied to word line45and positive voltage, +V, is applied to bit line41. Positive voltage on drain25, coupled with an equal negative voltage on control gate25pulls stored charge off of floating gate27. Select transistor51, together with select line55and sense line59are inactive and so is bit line43. Switching transistor13is off.

FIG. 6illustrates the bit line41with the voltage +V pulling electrons into drain25from a floating gate27with the voltage −V simultaneously pushing electrons away from control gate23toward drain25. This discharges the floating gate of transistor13, thereby erasing the cell in a push-pull manner.

InFIG. 7the solid rectangular lines102and104are subsurface active areas, on the order of a few microns in width, that are doped N-well regions in a P substrate. The P+ diffusions in the N-well regions are shown by numbers, i.e. sources and drains, but not lines. The dashed lines112,116are STI isolation regions.

The double hatched horizontal stripe45is the cell word line formed by a poly2stripe spaced apart by an insulative layer over a poly1stripe that is floating gates37and27inFIG. 1. The poly2stripe acts as control gates23and33inFIG. 1. The floating gate charge storage transistor11has a drain region25and a source region21. A via10extends from an upper metal layer1to contact a subsurface N-well for forming a p-n junction to establish impact ionization. Switching transistor13has a drain region35and a source region31. Contacts203and201form portions of bit lines43and41, respectively, inFIG. 1. A poly1conductive strap100ties together sources21and31.

A horizontal poly1stripe55is the select line for select transistor51having a source region53and a drain region57. A via205from metal layer1to the drain region57establishes sense line59inFIG. 1. A first metal layer1portion is represented by horizontal line301connecting vias211and213forming node39inFIG. 1, joining sources21and31. A second metal layer1portion, not connected to the previously mentioned first metal layer1portion, is represented by horizontal line303serving as sense line59inFIG. 1.

A first metal layer2portion is represented by vertical line401, making contact with via201to communicate bit line43. A second metal-layer2portion is represented by vertical line403, making contact with via203to communicate bit line41. A third metal layer2portion is represented by vertical line405, making contact with via10to establish p-n junctions for impact ionization. The first, second and third metal layer portions are not connected, but fabricated at the same time.

In the lower half ofFIG. 7, the memory cell503is a vertical mirror image of memory cell501in the upper half ofFIG. 7. The mirror image is formed across the shared sense line303with otherwise identical construction.

Mirror image memory cells501and503are shown inFIG. 8, adjacent to corresponding cells601and603and in an array with further corresponding cells901and903. The cells501,601and901share word lines701, select line703and sense line705. Cells503,603and903share word line711, select line713and sense line715. Memory cells501and503share bit lines541and543while memory cells601and603share bit lines641and643. The memory cells in the array are seen to employ three transistors, all fabricated at the same time using a stripe geometry.