AMPLIFIER WITH ADJUSTABLE INPUT AND FEEDBACK RESISTANCE

A programmable gain amplifier (PGA) circuit for adjusting a signal gain between a signal input and a signal output can include a differential-input amplifier which can include a first input node, a second input node, and a first output node, where the differential-input amplifier can be configured to amplify a difference in signal level between the first input node and the second input node for being provided on the first output node. The PGA circuit can also include a first configurable input impedance circuit, which can be arranged between a first signal input node and the first input node, which can be configured to provide a first specified input impedance value. The PGA circuit can also include a first configurable feedback impedance circuit, which can be arranged between a first signal output node and the first input node, which can be configured to provide a first specified feedback impedance value.

TECHNICAL FIELD

The present disclosure relates to amplifiers, and more particularly, but not by way of limitation, to a programmable gain amplifier with an adjustable input resistance string and an adjustable feedback resistance string.

BACKGROUND

Amplifier circuits are used in electronic systems for a variety of applications. For example, an analog amplifier circuit can be used in combination with other circuit types, such as co-integrated on a monolithic integrated circuit or in an integrated circuit package. An amplifier circuit can be configured to provide a fixed or adjustable gain. For example, gain programmability can include either amplification or attenuation, or both.

In analog signal processing applications, such as in automotive, wireless communication, or networking applications, it can be desirable to modify an amplitude range of an incoming analog signal, such as before downstream analog processing or digitization. A programmable-gain amplifier (PGA) circuit can provide gain adjustability, such as controlled by digital or analog signals provided by other elements in a signal processing system.

SUMMARY

In an example, a programmable gain amplifier (PGA) circuit for adjusting a signal gain between a signal input and a signal output can include a differential-input amplifier which can include a first input node, a second input node, and a first output node, where the differential-input amplifier can be configured to amplify a difference in signal level between the first input node and the second input node for being provided on the first output node. The PGA circuit can also include a first configurable input impedance circuit, arranged between a first signal input node and the first input node, where the first configurable input impedance circuit can be configured to provide a first specified input impedance value, where the first configurable input impedance circuit can include a first series arrangement of a first plurality of resistors, where a first end of the first series arrangement can be coupled to the first signal input node, where respective connection points between respective ones of the first plurality of resistors can define respective input impedance tap points, and a first plurality of switches, where a first end of respective ones of the first plurality of switches can be coupled to the first input node and a second end of the respective ones of the first plurality of switches can be coupled to corresponding ones of the input impedance tap points. The PGA circuit can also include a first configurable feedback impedance circuit, which can be arranged between a first signal output node and the first input node, where the first configurable feedback impedance circuit is configured to provide a first specified feedback impedance value, where the first configurable feedback impedance circuit can include a second series arrangement of a second plurality of resistors, where a first end of the second series arrangement can be coupled to the first signal output node, where respective connection points between respective ones of the second plurality of resistors can define respective feedback impedance tap points, and a second plurality of switches, where a first end of respective ones of the second plurality of switches can be coupled to the first input node and a second end of the respective ones of the second plurality of switches can be coupled to corresponding ones of the feedback impedance tap points.

DETAILED DESCRIPTION

The present inventors have recognized, among other things, that it can be desirable for a programmable gain amplifier (PGA) circuit to include adjustable gain steps that are at or below a specified gain step threshold. This can help to provide an output signal where artifacts are suppressed or below a threshold of perception by a user. For example, in audio applications, users of the system may perceive an audible artifact such as a pop or click corresponding to a gain value change. Providing gain steps at or below the specified gain step threshold can reduce or eliminate such artifacts. The present inventors have recognized, among other things, that implementation of such a specified gain step can be accomplished by using a circuit topology having a coarse gain control and a fine gain control. For example, the fine gain control can be stepped through fine gain increments, and once all available fine gain increments are used, a coarse gain control can be stepped through a coarse gain increment and the fine gain control can be reset, such as to produce a specified a step size corresponding to the fine gain increment. Such an approach can also be used for gain decrements.

The present inventors have recognized, among other things, that it can also be desirable to provide a stable input impedance to the PGA circuit across the adjustable gain range. For example, the approach described herein can be used to help limit a change in the input impedance of a PGA circuit across gain values, such as by limiting such an impedance change to a specified range or value. This can help provide one or more of more stable corner frequency or pole location for upstream filters (e.g., a filter formed by a resistor in series with a capacitor, such as can be affected by the input impedance of the PGA circuit), or a more linear effective gain, as compared to a PGA circuit having a larger variation in input impedance.

FIG.1shows an example of a portion of a PGA circuit100. The PGA circuit100can be configured to adjust a signal gain between a signal input and a signal output. The signal input can be received on the first signal input node111, and the signal output can be generated on the first signal output node114. The PGA circuit100can include a gain controller circuit110, a differential-input amplifier115, a first configurable input impedance circuit120, and a first configurable feedback impedance circuit140.

The gain controller circuit110can be configured to control one or more of the first configurable input impedance circuit120or the first configurable feedback impedance circuit140, which can include controlling the first configurable input impedance circuit120and the first configurable feedback impedance circuit140such that the PGA circuit100produces a specified value of the signal gain. The gain controller circuit110can control the first configurable input impedance circuit120such that it is configured to provide a first specified input impedance value. The gain controller circuit110can control the first configurable feedback impedance circuit140such that it is configured to provide a first specified feedback impedance value. The gain controller circuit110can be any circuit capable of controlling the first configurable input impedance circuit120or the first configurable feedback impedance circuit140. The gain controller circuit110can include or can be communicatively coupled with one or more of logic circuitry, a processor circuit capable of executing instructions, a memory circuit comprising instructions, or the like.

The differential-input amplifier115can be configured to amplify a difference between the signal received on the first input node112and the second input node113on the first output node116. The differential-input amplifier115can be an amplifier, such as an operational amplifier. The differential-input amplifier115can be configured to have one or more properties, such as a high input impedance, a low output impedance, or both. The differential-input amplifier115can function to reduce a voltage difference between the first input node112and the second input node113when a feedback connection from the first output node116is provided, such as the first configurable feedback impedance circuit140. In an example where the differential-input amplifier115is an operational amplifier (as shown inFIG.1), one or more of the first input node112can be an inverting input, the second input node113can be a non-inverting input, or the first output node116can be a non-inverting output. The first output node116can comprise the first signal output node114. The second input node113can be coupled to a reference voltage (e.g., a ground potential).

The first configurable input impedance circuit120can be configured to provide a first specified input impedance value, such as can one or more of determine the input impedance of the PGA circuit100(e.g., the effective impedance experienced by a circuit connected to the first signal input node111and looking toward the differential-input amplifier115) or affect a gain of the PGA circuit100. In an example, there can be a first input impedance element118arranged between the first signal input node111and the first configurable input impedance circuit120. In this example, the input impedance can be the sum of the impedance of the first input impedance element118and the first configurable input impedance circuit120. The first input impedance element118can have a specified input impedance element value.

The first configurable input impedance circuit120can include a first series arrangement of a first plurality of resistors, and a first plurality of switches. A first end of the first series arrangement can be coupled to the first signal input node111. Respective connection points between the respective ones of the first plurality of resistors can define respective input impedance tap points. The first series arrangement of the first plurality of resistors can include the first resistor121, the second resistor122, and the third resistor123. One or more of the first resistor121, the second resistor122, and the third resistor123can be arranged in series. There can be one or more additional resistors in the first series arrangement, which can include one or more additional resistors between the second resistor122and the third resistor123. There can be any number of resistors in the first plurality of resistors, such as can include two resistors, three or more resistors, five or more resistors, 10 or more resistors, 20 or more resistors, 31 resistors (e.g., as shown inFIG.1), or 40 or more resistors. In an example, all of the resistors in the first plurality of resistors are arranged in series. In an example, one or more of the resistors are arranged in parallel. In an example, the first configurable input impedance circuit120can include one or more additional circuit components (e.g., capacitors, inductors), such as can be arranged in series and/or parallel.

The individual ones of the first plurality of resistors can have any specified value. In an example, all of the resistors in the first plurality of resistors can have the same resistance value.

The first plurality of switches can be configured to adjust an impedance of the first configurable input impedance circuit120. A first end of respective ones of the first plurality of switches can be coupled to the first input node112and a second end of respective ones of the first plurality of switches can be coupled to corresponding ones of the input impedance tap points. The first plurality of switches can include a first switch131, a second switch132, an i-th switch133, a fourth switch134, and a fifth switch135. There can be one or more additional switches in the first plurality of switches, which can include one or more additional switches between the second switch132and the fourth switch134. In an example, the gain controller circuit110can be configured to control the first configurable input impedance circuit120by closing an individual one of the first plurality of switches, which can include closing the i-th switch133. For example, the i-th switch133can represent the individual one of the first plurality of switches that is closed, such as can include the first switch131, the second switch132, etc.

The second end of the first switch131can be coupled to the first input impedance tap point formed before the first resistor121. The second end of the second switch132can be coupled to the second input impedance tap point formed between the first resistor121and the second resistor122. The second end fifth switch135can be coupled to the last input impedance tap point formed after the third resistor123.

The first specified input impedance value can include the sum of the resistance values for all of the resistors between the second end of the first switch131and the i-th switch133(e.g., the resistance value of the first resistor121, when the second switch132is the selected i-th switch133). In an example, two or more of the first plurality of switches can be closed at the same time, which can provide a smaller resistance step than closing an individual one of the first plurality of switches at one time.

The first configurable feedback impedance circuit140can be configured to provide a first specified feedback impedance value, such as can affect a gain of the PGA circuit100. The first configurable feedback impedance circuit140can be configured similarly to the first configurable input impedance circuit120, or can differ in one or more ways. The first configurable feedback impedance circuit140can include a second series arrangement of a second plurality of resistors. A first end of the second series arrangement can be coupled to the first signal output node114. Respective connection points between the respective ones of the second plurality of resistors can define respective feedback impedance tap points. The second series arrangement can include the first resistor141, the second resistor142, the third resistor143, the fourth resistor144, and the fifth resistor145. One or more of the first resistor141, the second resistor142, the third resistor143, the fourth resistor144, or the fifth resistor145can be arranged in series. There can be one or more additional resistors in the second series arrangement, which can include one or more additional resistors between the third resistor143and the fourth resistor144. There can be any number of resistors in the second plurality of resistors, such as can include two resistors, three or more resistors, five or more resistors, 10 or more resistors, 20 or more resistors, 30 or more resistors, 40 or more resistors, 51 resistors (e.g., as shown inFIG.1), or 60 or more resistors. In an example, all of the resistors in the second plurality of resistors are arranged in series. In an example, one or more of the resistors are arranged in parallel. In an example, the first configurable feedback impedance circuit140can include one or more additional circuit components (e.g., capacitors, inductors), such as can be arranged in series and/or parallel.

The individual ones of the second plurality of resistors can have any specified value. In an example, all of the resistors in the second plurality of resistors can have the same resistance value. One or more of the values of the resistors in the second plurality of resistors can differ from or match one or more of the values of the resistors in the first plurality of resistors.

The second plurality of switches can be configured to adjust an impedance of the first configurable feedback impedance circuit140. A first end of respective ones of the second plurality of switches can be coupled to the first input node112and a second end of respective ones of the first plurality of switches can be coupled to corresponding ones of the feedback impedance tap points. The second plurality of switches can include a first switch151, a second switch152, a third switch153, a j-th switch154, a fifth switch155, and a sixth switch156. There can be one or more additional switches in the second plurality of switches, which can include one or more additional switches between the third switch153and the fifth switch155. In an example, the gain controller circuit110can be configured to control the first configurable feedback impedance circuit140by closing an individual one of the second plurality of switches, which can include closing the j-th switch154. For example, the j-th switch154can represent the individual one of the second plurality of switches that is closed, such as can include the first switch151, the second switch152, etc.

The second end of the first switch151can be coupled to the first feedback impedance tap point formed before the first resistor141. The second end of the second switch152can be coupled to the second feedback impedance tap point formed between the first resistor141and the second resistor142. The second end of the sixth switch156can be coupled to the last feedback impedance tap point formed between the fourth resistor144and the fifth resistor145.

The first specified feedback impedance value can include the sum of the resistance values for all of the resistors between the first signal output node114and the j-th switch154(e.g., the sum of the resistance values of the fifth resistor145, and the fourth resistor144, when the fifth switch155is the selected j-th switch154). In an example, two or more of the second plurality of switches can be closed at the same time, which can provide a smaller resistance step than closing an individual one of the second plurality of switches at one time.

In the example ofFIG.1, the PGA circuit100can include an inverting amplifier configuration. The signal gain of the PGA circuit100ofFIG.1can be shown by equation 1.

In equation 1, V114is the signal output on the first signal output node114, V111is the signal input on the first signal input node111, Rfeedbackis the feedback resistance value, Rinputis the input resistance value, R140is the first specified feedback impedance value of the first configurable feedback impedance circuit140, R118is the resistance value of the first input impedance element118, and R120is the first specified input impedance value of the first configurable input impedance circuit120. By controlling one or more of the first plurality of switches or the second plurality of switches, the gain controller circuit110can control the gain of the PGA circuit100. The signal input can be based on a difference in the voltage between the first signal input node and the reference voltage. The signal output can be based on the difference between the first signal output node and the reference voltage. Equation 1 shows that the signal gain can be based on a ratio between the feedback resistance value and the input resistance value. This can include a ratio between the first specified feedback impedance value and the first specified input impedance value.

The first configurable input impedance circuit120can establish a fine gain control, and the first configurable feedback impedance circuit140can establish a coarse gain control. For example, selecting the i-th switch133can include adjusting a fine gain control, and selecting the j-th switch154can include adjusting a coarse gain control. The gain step due to selecting between adjacent switches (e.g., the first switch131and the second switch132) in the first configurable input impedance circuit120can define a fine gain step, which corresponds to a minimum step of the fine gain control. The gain step due to selecting between adjacent switches in the first configurable feedback impedance circuit140can define a coarse gain step, which can define a minimum step of the coarse gain control. The gain steps associated with changes of switch states of the first configurable input impedance circuit120can be constant, or can vary from step-to-step. One or more fine gain steps can be configured to be within a specified range of one or more other fine gain steps. Similarly, one or more coarse gain steps can be configured to match one or more other coarse gain steps or the step size can be varied depending on resistor values. In an example, adjusting the fine gain control includes changing the individual one of the first plurality of switches that is closed, such as in a mutually-exclusive manner. In an example, adjusting the coarse gain control includes changing an individual one of the second plurality of switches that is closed.

The fine gain steps can be configured to be relatively smaller than the coarse gain steps. In an example, the fine gain steps can be configured to be at least five times smaller than the coarse gain steps. In an example, a total gain change associated with the range between a first and a final fine gain step can approximately match a coarse gain step (e.g., a gain difference between closing the first switch131and the fifth switch135is approximately equal to a gain difference between closing the first switch151and the second switch152).

In an example, the circuit can be initialized with the fifth switch135and the sixth switch156closed, and the remaining switches in the first configurable input impedance circuit120and the first configurable feedback impedance circuit140respectively can be open. In this configuration, the first specified input impedance value can be at a maximum value (e.g., due to all of the first plurality of resistors being arranged in series between the first signal input node111and the first input node112), and the first specified feedback impedance value can be at a minimum value (e.g., due to only a single one of the second plurality of resistors being arranged between the first output node116and the first input node112). This configuration can provide the lowest gain value of the PGA circuit100. In an example, this lowest gain value can include a unity gain value (e.g., a gain of 0 dB), such as can be due to the first specified input impedance value (e.g., the sum of the first input impedance element118and the resistance of the first configurable input impedance circuit120) matching the first specified feedback impedance value. From this configuration, the gain of the circuit can be increased, such as by closing different switches in the first configurable input impedance circuit120or the first configurable feedback impedance circuit140.

In an example, the signal gain can be increased using the fine gain control, such as can include opening the fifth switch135and closing the fourth switch134. In an example, increasing the fine gain control can include closing a switch in the first plurality of switches that is farther to the left, such as can decrease the value of the first specified input impedance value. In an example, the fine gain control can be stepped through in sequence, such as by closing an individual one of the first plurality of switches in a sequence from right to left (e.g., first the fifth switch135, then the fourth switch134, etc.).

In an example, the signal gain can be increased using the coarse gain control, such as can include adjusting the coarse gain control following stepping through one or more of the fine gain steps, such as can include opening the sixth switch156and closing the fifth switch155. In an example, increasing the coarse gain control can include closing a switch in the second plurality of switches that is farther to the left, such as can increase a value of the first specified feedback impedance value. In an example, one or more steps of the fine gain control can be stepped through between adjusting respective steps of the coarse gain control.

In an example, the resistance value of the first input impedance element118can be approximately 18.3 kiloohms, and each of the resistors in the first plurality of resistors can have a resistance of approximately 57.6 ohms. This can provide for an input resistance (e.g., resistance of the first input impedance element118plus the resistance of the first configurable input impedance circuit120) range of approximately 18.3 kiloohms to 20.08 kiloohms in 57.6 ohm steps, in a system with 31 resistors in the first plurality of resistors. This can provide for a fine gain step of approximately 0.025 dB or less, such as between all the fine gain steps.

FIG.2shows an example of a portion of a PGA circuit100. The PGA circuit100ofFIG.2can be configured similarly to the PGA circuit100ofFIG.1, or can differ in one or more ways.FIG.2shows that the differential-input amplifier115can include a fully differential-input amplifier, such as can include a second output node216. The PGA circuit100can include a second configurable input impedance circuit220and a second configurable feedback impedance circuit240.

The gain controller circuit110can be configured to control one or more of the second configurable input impedance circuit220or the second configurable feedback impedance circuit240. The second output node216can include an inverting output. The differential-input amplifier115can be configured to amplify a difference in voltage between the first input node112and the second input node113to a difference in voltage between the first output node116and the second output node216. In an example, the second input node113may not be connected to a reference potential.

The second configurable input impedance circuit220can be configured similarly to the first configurable input impedance circuit120, or can differ in one or more ways. The second configurable input impedance circuit220can be arranged between a second signal input node211and the second input node113. The second configurable input impedance circuit220can be configured to provide a second specified input impedance value. The220can include a third series arrangement of third plurality of resistors and a third plurality of switches.

The third plurality of resistors can include the first resistor221, the second resistor222, and the third resistor223. Similar to the first configurable input impedance circuit120, there can be one or more additional resistors between the second resistor222and the third resistor223. The resistance values of the third plurality of resistors can be configured to match, or one or more resistors can differ from one or more other resistors. In an example, corresponding resistors in the first configurable input impedance circuit120have a resistance matching corresponding resistors in the second configurable input impedance circuit220. In an example, all of the resistors in the first plurality of resistors and the third plurality of resistors can have the same resistance value.

The third plurality of switches can include a first switch231, a second switch232, an i-th switch233, a fourth switch234, and a fifth switch235. Similar to the first configurable input impedance circuit120, the i-th switch233can represent the individual switch selected by the gain controller circuit110to be closed in a specified configuration. In an example, the first configurable input impedance circuit120and the second configurable input impedance circuit220can be configured similarly. In an example, the first configurable input impedance circuit120and the second configurable input impedance circuit220can be operated similarly, such as can result in the first specified input impedance value substantially matching the second specified input impedance value. There can be a second input impedance element218arranged in series with the second configurable input impedance circuit220between the second signal input node211and the first input node112.

The second configurable feedback impedance circuit240can be configured similarly to the first configurable feedback impedance circuit140, or can differ in one or more ways. The second configurable feedback impedance circuit240can be arranged between a second signal output node214and the second input node113. The second configurable feedback impedance circuit240can be configured to provide a second specified feedback impedance value. The second configurable feedback impedance circuit240can include a fourth series arrangement of a fourth plurality of resistors and a fourth plurality of switches.

The fourth plurality of resistors can include the first resistor241, the second resistor242, the third resistor243, the fourth resistor244, and the fifth resistor245. Similar to the first configurable feedback impedance circuit140, there can be one or more additional resistors between the third resistor243and the fourth resistor244. The resistance values of the fourth plurality of resistors can be configured to match, or one or more of the resistors can differ from one or more other resistors. In an example, corresponding resistors in the first configurable feedback impedance circuit140have a resistance matching corresponding resistors in the second configurable feedback impedance circuit240. In an example, all of the resistors in the second plurality of resistors and the fourth plurality of resistors can have the same resistance value.

The fourth plurality of switches can include the first switch251, the second switch252, the third switch253, the j-th switch254, the fifth switch255, and the sixth switch256. Similar to the first configurable feedback impedance circuit140, the j-th switch254can represent the individual switch selected by the gain controller circuit110to be closed in a specific configuration. In an example, the first configurable feedback impedance circuit140and the second configurable feedback impedance circuit240can be configured similarly. In an example, the first configurable feedback impedance circuit140and the second configurable feedback impedance circuit240can be operated similarly, such as can result in the first specified feedback impedance value substantially matching the second specified feedback impedance value.

In the fully differential implementation ofFIG.2, the input signal can be based on the difference between the second signal input node211and the first signal input node111, and the output signal can be based on the difference between the second signal output node214and the first signal output node114. The gain of the PGA circuit100ofFIG.2can be shown by equation 1 (e.g., the gain of the PGA circuit100ofFIG.2can match the gain of the PGA circuit100ofFIG.1).

FIG.3shows an example of a portion of the PGA circuit100ofFIG.2and an example of an application circuit in which the PGA circuit100can be used.FIG.3shows that the PGA circuit100can receive a signal input from a microphone320, and can pass the signal output to an audio processing circuitry310. In an example, the first configurable input impedance circuit120and the second configurable input impedance circuit220can include the first input impedance element118and the second input impedance element218, respectively.

The microphone320can be configured to generate an electrical signal corresponding to a received audio signal. The audio signal can include a pressure disturbance in a medium (e.g., air, water), and can include signals at one or more frequencies (e.g., a periodic audio signal). The microphone320can be a transducer that converts sound waves into an electrical signal. The electrical signal from the microphone320can be passed to the PGA circuit100. Passing the signal from the microphone320to the PGA circuit100can include passing the signal through a coupling resistor321or and/or a coupling capacitor322. In an example, one or more of the coupling resistor321or the coupling capacitor322can be internal to the microphone320or the PGA circuit100. The input impedance of the PGA circuit100experienced by the microphone320can include the sum of the impedances of the coupling resistor321, the coupling capacitor322, and the first configurable input impedance circuit120. The coupling capacitor322can have the effect of a high-pass filter. The corner frequency of the high-pass filter can be determined as a function of the impedance values of one or more of the coupling resistor321, the coupling capacitor322, and the first configurable input impedance circuit120. Adjusting the first configurable input impedance circuit120, such as to adjust a gain of the PGA circuit100, can have the effect of changing the corner frequency of the filter. This can make it desirable to minimize a change in the resistance value of the first configurable input impedance circuit120, such as to help maintain a consistent frequency response.

The audio processing circuitry310can include one or more of an analog-to-digital converter or other audio processing circuitry. The audio processing circuitry310can be used in a process, such as one or more of audio digitization for storage or communications applications, noise cancelation, or the like. The PGA circuit100can scale the input signal to the audio processing circuitry310to an appropriate range, such as an appropriate range for digitization or other downstream processing. This can help a dynamic range of the signal provided to the ADC should approximately match the ADC dynamic range, such as can help to maximize or otherwise tailor SNR. In an example, the310can amplify a signal received from the PGA circuit100, such as can include amplifying an audio signal to be sent to one or more speakers. In this example, the audio processing circuitry310can have a specified gain value, such as can include an adjustable gain value.

FIG.4shows a plot of simulated operating characteristics of a PGA circuit100as shown inFIG.3.FIG.4shows the corner frequency of the high-pass filter formed by the input impedance of the PGA circuit100across a range of signal gain values. When the first configurable input impedance circuit120and the second configurable input impedance circuit220(e.g., the input) include the fine gain control, the input impedance remains substantially the same across the gain range, such as at approximately 8 Hz, such as can be due to the input impedance remaining relatively constant (e.g., changing less than 10 percent). When the first configurable input impedance circuit120and the second configurable input impedance circuit220include the coarse gain control, such as in a case where the fine gain control is not present or is present in one or more of the first configurable input impedance circuit120, the second configurable input impedance circuit220, the first configurable feedback impedance circuit140or the second configurable feedback impedance circuit240, the corner frequency can change across the gain range, such as from a value of approximately 8 Hz to 125 Hz. When the coarse gain control is on the input, the corner frequency shifts substantially in response to changing can.

FIG.5shows a plot of simulated operating characteristics of a PGA circuit100as shown inFIG.3.FIG.5shows the gain of the PGA circuit100across a range of coarse gain control settings (e.g., selecting between the first switch151and the second switch152, etc.).FIG.5shows that when the fine gain control is on the input, the gain steps are relatively linear. When the coarse gain control is on the input, such as in a case where the fine gain control is not present or is present on the feedback, the gain steps are not as linear, such as can be due to a changing corner frequency of the high pass filter, as discussed above with respect toFIG.4.

FIG.6shows a plot of simulated operating characteristics of a PGA circuit100as shown inFIG.3.FIG.6shows the input resistance of the PGA circuit100across a range of signal gains for the coarse gain control.FIG.6shows that when the fine gain control is on the input, such as in a case where the fine gain control is not present or is present on the feedback, the input resistance of the PGA circuit100remains relatively constant, such as at approximately 20 kiloohms. When the coarse gain control is on the input, the input resistance varies, such as from approximately 29.5 kiloohms to 0.3 kiloohms.

FIG.7shows an example of portions of a method700for operating a PGA circuit, such as the PGA circuit100. At step702, a signal gain can be compared to a specified signal gain. For example, an effective signal gain of the PGA circuit100can be compared to a specified signal gain. The specified signal gain can be determined by the gain controller circuit110, a user, or both. The signal gain can be determined by comparing the signal input to the signal output. The signal gain can be compared to the specified signal gain in digital logic, analog logic, or both. If the signal gain matches the specified signal gain (e.g., matches within a specified tolerance, such as can be approximately equal to the fine gain step), the method700can include returning to step702, such as to recurrently compare the signal gain to the specified signal gain. If the signal gain does not match the specified signal gain, the method700can include going to step704.

At step704, it can be determined if the gain is too high or too low. This can include comparing the signal gain to the specified signal gain. If the gain is too high, the method700can include going to step714. If the gain is too low, the method700can include going to step706.

At step706, the signal gain can be increased. Increasing the signal gain can include, at step708, checking whether the fine gain control is at an upper limit (e.g., whether the fine gain control configured to produce the maximum signal gain). If the fine gain control is not at the upper limit, the fine gain control can be increased at step710, such as can include adjusting the fine gain control in the direction indicated by the comparison at step704. If the fine gain control is at an upper limit, the fine gain control can be reset to a lower limit, and the coarse gain control can be increased at step712. In an example, the system can be configured such that the gain increase by resetting the fine gain control and increasing the coarse gain control is approximately equal to one step of the fine gain control. In an example, the fine gain control may not be reset to the lowest setting, but may be set to an intermediate setting, such as to produce the desired gain step size (e.g., resetting the fine gain control while increasing the coarse gain control could cause a decrease in gain for some coarse gain settings, which may not be desirable). Following step710or step712, the method700can include returning to step702.

At step714, the signal gain can be decreased. Decreasing the signal gain can include, at step716, checking whether the fine gain control is at a lower limit. If the fine gain control is not at the lower limit, the fine gain control can be decreased at step718. If the fine gain control is at a lower limit, the fine gain control can be set to the upper limit, and the coarse gain control can be decreased at step720. Following step718or step720, the method700can include returning to step702.

The shown order of steps is not intended to be a limitation on the order the steps are performed in. In an example, two or more steps may be performed simultaneously or at least partially concurrently.

The machine800may include a hardware processor802(e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory804, a static memory (e.g., memory or storage for firmware, microcode, a basic-input-output (BIOS), and mass storage808(e.g., hard drives, tape drives, flash storage, or other block devices) some or all of which may communicate with each other via an interlink830(e.g., bus). The machine800may further include a display unit810, an alphanumeric input device812(e.g., a keyboard), and a user interface (UI) navigation device814(e.g., a mouse). In an example, the display unit810, input device812and UI navigation device814may be a touch screen display. The machine800may additionally include a signal generation device818(e.g., a speaker), a network interface device820, and one or more sensors816, such as a global positioning system (GPS) sensor, compass, accelerometer, or other sensor. The machine800may include an output controller828, such as a serial (e.g., universal serial bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection to communicate or control one or more peripheral devices (e.g., a printer, card reader, etc.).

Registers of the processor802, the main memory804, the static memory806, or the mass storage808may be, or include, a machine readable medium822on which is stored one or more sets of data structures or instructions824(e.g., software) embodying or utilized by any one or more of the techniques or functions described herein. The instructions824may also reside, completely or at least partially, within any of registers of the processor802, the main memory804, the static memory806, or the mass storage808during execution thereof by the machine800. In an example, one or any combination of the hardware processor802, the main memory804, the static memory806, or the mass storage808may constitute the machine readable media822. While the machine readable medium822is illustrated as a single medium, the term “machine readable medium” may include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) configured to store the one or more instructions824.

In an example, information stored or otherwise provided on the machine readable medium822may be representative of the instructions824, such as instructions824themselves or a format from which the instructions824may be derived. This format from which the instructions824may be derived may include source code, encoded instructions (e.g., in compressed or encrypted form), packaged instructions (e.g., split into multiple packages), or the like. The information representative of the instructions824in the machine readable medium822may be processed by processing circuitry into the instructions to implement any of the operations discussed herein. For example, deriving the instructions824from the information (e.g., processing by the processing circuitry) may include: compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamically or statically linking), encoding, decoding, encrypting, unencrypting, packaging, unpackaging, or otherwise manipulating the information into the instructions824.

In an example, the derivation of the instructions824may include assembly, compilation, or interpretation of the information (e.g., by the processing circuitry) to create the instructions824from some intermediate or preprocessed format provided by the machine readable medium822. The information, when provided in multiple parts, may be combined, unpacked, and modified to create the instructions824. For example, the information may be in multiple compressed source code packages (or object code, or binary executable code, etc.) on one or several remote servers. The source code packages may be encrypted when in transit over a network and decrypted, uncompressed, assembled (e.g., linked) if necessary, and compiled or interpreted (e.g., into a library, stand-alone executable etc.) at a local machine, and executed by the local machine.

EXAMPLES

Example 1 is a programmable gain amplifier (PGA) circuit for adjusting a signal gain between a signal input and a signal output, the PGA circuit comprising: a differential-input amplifier comprising a first input node, a second input node, and a first output node, wherein the differential-input amplifier is configured to amplify a difference in signal level between the first input node and the second input node for being provided on the first output node; a first configurable input impedance circuit, arranged between a first signal input node and the first input node, wherein the first configurable input impedance circuit is configured to provide a first specified input impedance value; wherein the first configurable input impedance circuit includes: a first series arrangement of a first plurality of resistors, wherein a first end of the first series arrangement is coupled to the first signal input node, wherein respective connection points between respective ones of the first plurality of resistors define respective input impedance tap points; and a first plurality of switches, wherein a first end of respective ones of the first plurality of switches is coupled to the first input node and a second end of the respective ones of the first plurality of switches is coupled to corresponding ones of the input impedance tap points; and a first configurable feedback impedance circuit, arranged between a first signal output node and the first input node, wherein the first configurable feedback impedance circuit is configured to provide a first specified feedback impedance value, wherein the first configurable feedback impedance circuit includes: a second series arrangement of a second plurality of resistors, wherein a first end of the second series arrangement is coupled to the first signal output node, wherein respective connection points between respective ones of the second plurality of resistors define respective feedback impedance tap points; and a second plurality of switches, wherein a first end of respective ones of the second plurality of switches is coupled to the first input node and a second end of the respective ones of the second plurality of switches is coupled to corresponding ones of the feedback impedance tap points.In Example 2, the subject matter of Example 1 optionally includes a gain controller circuit, coupled to the first configurable input impedance circuit and the first configurable feedback impedance circuit, wherein the gain controller circuit is configured to control the first specified input impedance value and the first specified feedback impedance value such that the PGA circuit provides a specified value of the signal gain.In Example 3, the subject matter of Example 2 optionally includes wherein the gain controller circuit is configured to: control the first configurable input impedance circuit by closing an individual one of the first plurality of switches; and control the first configurable feedback impedance circuit by closing an individual one of the second plurality of switches.In Example 4, the subject matter of any one or more of Examples 1-3 optionally include wherein: each of the first plurality of resistors include a same first resistance value; and each of the second plurality of resistors include a same second resistance value.In Example 5, the subject matter of any one or more of Examples 1-4 optionally include wherein: the second input node is coupled to a reference voltage; the signal input is based on a difference in voltage between the first signal input node and the reference voltage; and the signal output is based on a difference in voltage between the first signal output node and the reference voltage.In Example 6, the subject matter of any one or more of Examples 1-5 optionally include wherein: the differential-input amplifier includes a fully differential-input amplifier, including a second output node; the PGA circuit includes: a second configurable input impedance circuit, arranged between a second signal input node and the second input node, wherein the second configurable input impedance circuit is configured to provide a second specified input impedance value; and a second configurable feedback impedance circuit, arranged between a second signal output node and the second input node, wherein the second configurable feedback impedance circuit is configured to provide a second specified feedback impedance value; and the signal input it based on a difference in voltage between the first signal input node and the second signal input node; and the signal output is based on a difference in voltage between the first signal output node and the second signal output node.In Example 7, the subject matter of Example 6 optionally includes wherein the PGA circuit is configured such that: the second specified input impedance value matches the first specified input impedance value; and the second specified feedback impedance value matches the first specified feedback impedance value.In Example 8, the subject matter of any one or more of Examples 1-7 optionally include wherein: a ratio between the first specified feedback impedance value and the first specified input impedance value determines the signal gain.In Example 9, the subject matter of Example 8 optionally includes wherein: adjusting the first specified input impedance value comprises adjusting a fine gain control; and adjusting the first specified feedback impedance value comprises adjusting a coarse gain control; and wherein a minimum adjustment of the fine gain control comprises and adjustment at least five times smaller than a minimum adjustment of the coarse gain control.In Example 10, the subject matter of any one or more of Examples 1-9 optionally include an input impedance element, arranged between the first signal input node and the first configurable input impedance circuit, wherein the input impedance element includes a specified input impedance element value.In Example 11, the subject matter of Example 10 optionally includes wherein: the specified input impedance element value is at least five times greater than a difference between a maximum and a minimum value of the first specified input impedance value.In Example 12, the subject matter of any one or more of Examples 1-11 optionally include wherein: the PGA circuit is arranged to amplify a signal from a microphone; and the microphone includes a capacitance in series with the first signal input node.Example 13 is a method of operating a programmable gain amplifier (PGA) circuit for adjusting a signal gain between a signal input and a signal output, the method comprising: comparing the signal gain to a specified signal gain; adjusting a fine gain control in a direction indicated by the comparison; and in response to the fine gain control reaching one of an upper limit or a lower limit, adjusting a coarse gain control in the direction indicated by the comparison and setting the fine gain control to one of the upper limit or the lower limit opposite to the limit reached, wherein the PGA circuit includes: a differential-input amplifier including a first input node, a second input node, and a first output node, wherein the differential-input amplifier is configured to amplify a difference in signal level between the first input node and the second input node for being provided at the first output node; a first configurable input impedance circuit, arranged between a first signal input node and the first input node, wherein the first configurable input impedance circuit is configured to provide a first specified input impedance value; and a first configurable feedback impedance circuit, arranged between a first signal output node and the first input node, wherein the first configurable feedback impedance circuit is configured to provide a first specified feedback impedance value.In Example 14, the subject matter of Example 13 optionally includes wherein: adjusting the first specified input impedance value comprises adjusting the fine gain control; and adjusting the first specified feedback impedance value comprises adjusting the coarse gain control.In Example 15, the subject matter of any one or more of Examples 13-14 optionally include wherein: a first gain change due to: (1) to adjusting the coarse gain control in the direction indicated by the comparison, and (2) setting the fine gain control to one of the upper limit or the lower limit opposite to the limit reached, is configured to match a gain change due to adjusting the fine gain control in a direction indicated by the comparison.In Example 16, the subject matter of any one or more of Examples 13-15 optionally include wherein: the first configurable input impedance circuit includes: a first series arrangement of a first plurality of resistors, wherein a first end of the first series arrangement is coupled to the first signal input node, wherein respective connection points between respective ones of the first plurality of resistors define respective input impedance tap points; and a first plurality of switches, wherein a first end of respective ones of the first plurality of switches is coupled to the first input node and a second end of the respective ones of the first plurality of switches is coupled to corresponding ones of the input impedance tap points; and the first configurable feedback impedance circuit includes: a second series arrangement of a second plurality of resistors, wherein a first end of the second series arrangement is coupled to the first signal output node, wherein respective connection points between respective ones of the second plurality of resistors define respective feedback impedance tap points; and a second plurality of switches, wherein a first end of respective ones of the second plurality of switches is coupled to the first input node and a second end of the respective ones of the second plurality of switches is coupled to corresponding ones of the feedback impedance tap points.In Example 17, the subject matter of Example 16 optionally includes controlling the first configurable input impedance circuit by closing an individual one of the first plurality of switches; and controlling the first configurable feedback impedance circuit by closing an individual one of the second plurality of switches, wherein: adjusting the fine gain control includes changing the individual one of the first plurality of switches that is closed; and adjusting the coarse gain control includes changing the individual one of the second plurality of switches that is closed.Example 18 is at least one non-transitory machine-readable medium for controlling a programmable gain amplifier (PGA) circuit for adjusting a signal gain between a signal input and a signal output, including instructions, which when executed, cause processing circuitry to perform operations to: compare the signal gain to a specified signal gain; adjust a fine gain control in a direction indicated by the comparison; and in response to the fine gain control reaching one of an upper limit or a lower limit, adjust a coarse gain control in the direction indicated by the comparison and setting the fine gain control to one of the upper limit or the lower limit opposite to the limit reached, wherein the PGA circuit includes: a differential-input amplifier include a first input node, a second input node, and a first output node, wherein the differential-input amplifier is configured to amplify a difference in signal level between the first input node and the second input node for being provided at the first output node; a first configurable input impedance circuit, arranged between a first signal input node and the first input node, wherein the first configurable input impedance circuit is configured to provide a first specified input impedance value; and a first configurable feedback impedance circuit, arranged between a first signal output node and the first input node, wherein the first configurable feedback impedance circuit is configured to provide a first specified feedback impedance value.In Example 19, the subject matter of Example 18 optionally includes wherein: to adjust the first specified input impedance value comprises adjusting the fine gain control; and to adjust the first specified feedback impedance value comprises adjusting the coarse gain control.In Example 20, the subject matter of any one or more of Examples 18-19 optionally include wherein: the first configurable input impedance circuit includes: a first series arrangement of a first plurality of resistors, wherein a first end of the first series arrangement is coupled to the first signal input node, wherein respective connection points between respective ones of the first plurality of resistors define respective input impedance tap points; and a first plurality of switches, wherein a first end of respective ones of the first plurality of switches is coupled to the first input node and a second end of the respective ones of the first plurality of switches is coupled to corresponding ones of the input impedance tap points; and the first configurable feedback impedance circuit includes: a second series arrangement of a second plurality of resistors, wherein a first end of the second series arrangement is coupled to the first signal output node, wherein respective connection points between respective ones of the second plurality of resistors define respective feedback impedance tap points; and a second plurality of switches, wherein a first end of respective ones of the second plurality of switches is coupled to the first input node and a second end of the respective ones of the second plurality of switches is coupled to corresponding ones of the feedback impedance tap points.Example 21 is at least one machine-readable medium including instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement of any of Examples 1-20.Example 22 is an apparatus comprising means to implement of any of Examples 1-20.Example 23 is a system to implement of any of Examples 1-20.Example 24 is a method to implement of any of Examples 1-20.

Each of the non-limiting aspects above can stand on its own or can be combined in various permutations or combinations with one or more of the other aspects or other subject matter described in this document.

Method examples described herein can be machine or computer-implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code may form portions of computer program products. Such instructions can be read and executed by one or more processors to enable performance of operations comprising a method, for example. The instructions are in any suitable form, such as but not limited to source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like.

Further, in an example, the code can be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media can include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.