Frequency demodulator circuit with zero-crossing counter

A digital frequency demodulator circuit works on the principle of determining the number of zero crossings of a band-limited input signal in a given period of time, in corresponding prior art analog circuits. The circuit includes an analog-to-digital converter, three delay elements, two edge detectors, an up/down counter, two arcsin read-only memories, a 1/2 multiplier and a multiple adder.

BACKGROUND OF THE INVENTION 
The invention pertains to a frequency demodulator circuit working on the 
principle of determining the number of zero crossings of a band-limited 
input signal in a given period of time by means of a periodically reset 
counter. 
In British patent specification No. 1 214 514, page 1, this principle is 
briefly described for analog signals as the prior art from which the 
subject matter protected in that patent specification is distinguished. 
SUMMARY OF THE INVENTION 
One object of the invention as claimed is to eliminate the disadvantages of 
the known principle which are described in the patent specification 
referred to above which are essentially that the degree of accuracy is 
reduced when there is an excessive frequency deviation. The digital 
frequency demodulation principle which is known per se from that patent 
specification is to be applied to the principle of determining the number 
of zero crossings in a given period of time. 
One of the advantages offered by the invention is that the only digital 
computing circuits required are adders, whereas the various embodiments of 
the above prior art require, inter alia, multipliers and dividers. These 
digital computing circuits require a considerable area on integrated 
circuit chips with which such frequency demodulator circuits are commonly 
implemented. The solution in accordance with the invention therefore has 
the added advantage of requiring considerably less chip area than the 
prior art arrangement. It can be used to advantage if relatively 
narrow-band signals are modulated on a high carrier frequency, as is the 
case with the audio signals of the common television standards (, 
NTSC).

DETAILED DESCRIPTION 
The band-limited signal to be demodulated is applied as an 
amplitude-normalized signal fm to the input of the analog-to-digital 
converter ad, which is clocked by the sampling signal s. In accordance 
with the sampling theorem, its frequency must be chosen to be at least 
twice as high as the sum of the carrier frequency and half the so-called 
Carson bandwidth. The amplitude normalization can take place either before 
or after the analog-to-digital converter ad, i.e., either on the analog 
side or on the digital side, and may be performed by an analog or digital 
amplitude control circuit. 
The output of the analog-to-digital converter ad is coupled to the input of 
the quadrant detector qd, which senses in which quarter of the period of 
the signal fm the instantaneous sample value of the latter lies. The term 
"quadrant" is used here in the same sense as in the discussion of 
trigonometric functions in mathematics; the first quadrant is thus the 
angular range from 0.degree. to 90.degree., the second the angular range 
from 90.degree. to 180.degree., the third the angular range from 
180.degree. to 270.degree., and the fourth the angular range from 
270.degree. to 360.degree. or 0.degree.. Since a digital signal for four 
posssible states is thus produced by means of the quadrant detector qd, 
this is a two-bit digital signal in the straight binary code. From the use 
of the quadrant detector qd, an additional condition follows for the 
frequency of the sampling signal s: This frequency must be greater than 
four times the above-mentioned sum of the carrier frequency and half the 
Carson bandwidth. 
The output of the quadrant detector qd is fed to the first delay element 
v1, which provides a delay equal to k times the period of the sampling 
signal s, where k denotes the integral ratio of the frequency of the 
sampling signal s to the frequency of the clock signal t, at whose pulse 
repetition rate the digital words of the demodulated signal fm' are 
processed. In accordance with the sampling theorem, the frequency of this 
clock signal t must be chosen to be at least twice as high as the highest 
frequency occurring in the demodulated signal fm'. 
The output of the analog-to-digital converter ad is also coupled to the 
input of the second delay element v2, which provides a delay equal to that 
of the quadrant detector qd and has its output connected to the input of 
the third delay element v3, whose delay is equal to that of the first 
delay element v1. 
The outputs of the second and third delay elements v2 and v3 are connected 
to the address inputs ae of the first and second arcsin read-only memories 
rm1 and rm2, respectively, in which the arcsin values of the first 
quadrant of the sine function are permanently stored, with each address 
signal causing an associated argument or angle signal to be delivered at 
the output of the read-only memory. 
The output signals of the two read-only memories rm1 and rm2 are combined 
with the output signals of the quadrant detector qd and the first delay 
element v1, respectively, i.e., the bits of the output signals of the two 
read-only memories are linked to the two bits of the output signals of the 
quadrant detector qd and the first delay element v1, respectively. These 
signals are fed to the multiple adder ma. 
The sign bits of the outputs of the second and third delay elements v2 and 
v3 are fed, respectively, through the edge detectors fd1 and fd2 to the up 
input ve and the down input re of the up/down counter z, whose count 
output is fed through the 1/2 multiplier m to a further input of the 
multiple adder ma. 
The output of the multiple adder ma is followed by the decimator dz, which 
is clocked by the clock signal t and may also be clocked by the sampling 
signal s. The output of the decimator dz provides the digital demodulated 
signal fm'. By means of the decimator dz, the data sequence is reduced 
from the sampling rate to the clock rate. 
The two edge detectors fd1 and fd2 respond to an H-to-L or L-to-H 
transition of the above-mentioned sign bit, with H and L denoting the two 
levels of a binary signal. 
The frequency demodulator circuit according to the invention differs from 
the above-mentioned analog frequency demodulator not only in that it is 
implemented as a digital circuit, but also in specific details which 
follow from such an implementation and have no equivalent in the analog 
circuit. For example, the choice of the up/down counter z as an equivalent 
to the counter used in the known principle eliminates the need for the 
periodic resetting. While, in the known principle, the measured time is 
the time between two reset pulses, in the invention, the delay produced by 
the first and third delay elements v1, v3, which is determined by the 
quantity k, is equivalent to the measured time. 
In the invention, the qudrant detector qd and the three delay elements v1, 
v2, v3 are clocked circuits to which the clock signal s is applied; this 
is not shown in the figure to simplify the illustration. The decimator dz 
is a clocked circuit, too. 
As mentioned at the beginning, the frequency demodulator circuit according 
to the invention can be implemented using integrated-circuit techniques, 
with insulated-gate field-effect transistor integrated circuits (MOS 
circuits) being particularly advantageous, because it is an all-digital 
circuit.