SEMICONDUCTOR DEVICE AND SCAN TESTING METHOD

During the scan testing, the peak power that instantaneously occurs in the shift operation is reduced. The semiconductor device of the present invention, the phase of the ATE clock signal (ATE_Clk) is shifted in several variations, by external control, as set in the scan testing scan chain has a clock operating unit for distributing the phase shifted clocks.

BACKGROUND

In recent years, in LSI designs which have become highly integrated, large-scale, and high-speed, it has become indispensable to apply scan test (especially at-speed scan testing), which is one of the test methods for semiconductor integrated circuits, from the viewpoint of reducing the cost required for specification assurance and testing (test).

However, in scan testing, a very large amount of power is consumed in comparison with the function operation (in normal operation). Therefore, it is required to reduce the power consumption during the scan test, and the influence of the peak power and the importance of the reduction are also increasing rapidly.

There are disclosed techniques listed below.[Patent Document 1] Japanese Unexamined Patent Application Publication No. 2012-185127[Non-Patent Document 1] Ran Wang, et al., “A Programmable Method for Low-Power Scan Shift in SoC Integrated Circuits.” In Proceedings of the 34th VLSI Test Symposium, April 2016.[Non-Patent Document 2] Takaki Yoshida, Masafumi Watari, “MD-scan method for low power scan testing.” In Proceedings of the 11th Asian Test Symposium, pp. 80-85, November 2002.

For example, Patent Document 1 aims to reduce the peak power during capture mode in scan testing. For a plurality of circuit blocks, including scan chains and combination circuits, with no data path dependence among them, each block is assigned with a clock selection logic. The clock selection logic can switch between internal PLL clock and a particular scan clock generated by an additional scan clock control logic. The scan clock control logic can generate shift clocks, switching in the same timing, for all blocks during shift mode in scan testing, and generate capture clocks, switching in different timings, for all blocks during capture mode in scan testing. In Patent Document 1, all clocks generated by the scan clock control logic are called block scan clocks.

Furthermore, Non-Patent Document 1 discloses a method to reduce peak power during shift mode in scan testing, in SoC (System on Chip) designs. As shown inFIG.12, each block of SoC products has a shift stagger circuit that shifts the phase of the shifting clock supplied from a semiconductor testing device (ATE: Automated Test Equipment) in several variations. On/off of the phase shift function of the shift stagger circuit is controlled by an enable signal (enableStagger), and in addition, only one of the variations of the phase shift clock is selected by the selection signal (Stagger_Sel) as the output clock. The selected output clock (StagClkOut) is fed to all scan chains in the block. Thus, by shifting the clock timing of each scan chain, instantaneously high-power consumption can be avoided.

In Non-Patent Document 1, all blocks in a SoC design are divided into adjacent (sharing power supply) and non-adjacent (not sharing power supply) blocks. By assigning different phase shift clocks to all adjacent blocks, peak shift power caused by simultaneous shifting of all blocks can be reduced.

In Non-Patent Document 2, in order to reduce the power supply voltage drop in the shift mode of scan testing, MD-SCAN (Multi Duty-Scan) technique is proposed.

SUMMARY

The prior art disclosed in Non-Patent Document 1 can prevent all adjacent blocks in the SoC product from using the same phase shift clock, yet test may still fail, in the case of a group contains only one block, and the peak power consumption caused by only testing this block still across the critical line.

Other issues and novel features will be explained in the description of this specification and the accompanying drawings.

According to one embodiment, a semiconductor device is equipped with a clock operator circuit that can shift the phase of the ATE clock signal (ATE_Clk) into several different variations and distribute the phase shifted clock to scan chains scan testing based on external control signals.

According to the one embodiment, a semiconductor device can reduce the peak shift power during scan testing, reducing over-kill and improving the yield.

DETAILED DESCRIPTION

Hereinafter, a semiconductor device according to an embodiment will be described in detail by referring to the drawings. In the specification and the drawings, the same or corresponding form elements are denoted by the same reference numerals, and a repetitive description thereof is omitted. In the drawings, for convenience of description, the configuration may be omitted or simplified. Also, at least some of the embodiments may be arbitrarily combined with each other.

First Embodiment

FIG.1is a block diagram showing a configuration of a semiconductor device according to the first embodiment.

In the first embodiment, as an example of a semiconductor device, microcomputer1will be described. Microcomputer1as a semiconductor device, for example, a semiconductor substrate (semiconductor chip) such as a single-crystal silicon, is formed using a known CMOS manufacturing process. Microcomputer1includes a plurality of scan chains S1, S2, S3, S4, and Clock Operator11to shift the phase of ATE clock signal14(ATE_Clk) supplied from a tester (not shown) and distributing the signals to the scan chains.

FIG.2is a block diagram illustrating a configuration of Clock Operator11. Clock Operator11includes Shift Clock Duty Shifter111for shifting the phase of the supplied ATE clock signal14(ATE_Clk) into several variations, and Shift Clock Selector112for distributing phase shifted clock signals to each scan chain in accordance with the order specified by external control signals.

Shift Clock Duty Shifter111is controlled by shift control signal13(ShifterEN), if shift control signal13(ShifterEN) is ON, the phase of the supplied ATE clock signal14(ATE_Clk) will be shifted. On the other hand, when shift control signal13(ShifterEN) is OFF, it outputs ATE clock signal14(ATE_Clk) without changing its phase.

Shift Clock Selector112is controlled by clock sort signal12(Clk_Sort[x:0]) and selects the input ATE clock signal14(ATE_Clk) in the defined order and outputs it to the clock port of each scan chain. Here, the value of x is determined by the number of the phase shifted clocks c (c>1) and the number of scan chains s; More specifically, x=(√c)*s.

(Operation of the Shift Clock Duty Shifter)

FIG.3is a circuit diagram showing a configuration of Shift Clock Duty Shifter111. Shift Clock Duty Shifter111, for example, can be implemented by combining a set of clock buffers and multiplexers.

In the example shown inFIG.3, the input ATE clock signal14(ATE_Clk) branches and go through clock buffers31A,31B,31C,31D. Clock buffers31A,31B,31C,31D are formed by delay elements, shifting the phase of ATE clock signal14(ATE_Clk). The outputs of multiplexers32A,32B,32C are controlled by shift control signal13(ShifterEN), they can switch freely between ATE clock signal14(ATE_Clk) and the phase shift clocks.

As the truth table ofFIG.4shows, when shift control signal13(ShifterEN) is 0, from the outputs Q1, Q2, Q3, Q4of Shift Clock Duty Shifter111, ATE clock signal (ATE_Clk) is output without phase shifting. In contrast, when shift control signal13(ShifterEN) is 1, among the outputs of Shift Clock Duty Shifter111, Q1outputs ATE clock signal14(ATE_Clk) and Q2, Q3, Q4output the phase shifted clock signal2(Clk2), clock signal3(Clk3), and clock signal4(Clk4), respectively. The buffer implemented in the output path of Q1is for adjusting the clock skew.

(Operation of Shift Clock Selector)

FIG.5is a circuit diagram showing an example of Shift Clock Selector112. Shift Clock Selector112is implemented, for example, by a combination of a four-input one-output multiplexer and the corresponding clock sort signal Clk_Sort[1:0].

In the example illustrated inFIG.5, the outputs Q1, Q2, Q3, Q4of the Shift Clock Duty Shifter111are input, and the multiplexers51A,51B,51C,51D can freely switch the Q1, Q2, Q3, Q4inputs by the clock sort signal (Clk_Sort).

The truth table ofFIG.6shows an example of the operation of a four-input one-output multiplexer. Q1is selected when the clock sort signal Clk_Sort[1:0] is “00”, Q2is selected when the clock sort signal Clk_Sort[1:0] is “01”, Q3is selected when the clock sort signal Clk_Sort[1:0] is “10”, and Q4is selected when the clock sort signal Clk_Sort[1:0] is “11”. Although the ATE clock signal14in the first embodiment (ATE_Clk) is divided into four variations, it can be less than or more than four.

(Explanation of Design Flow1)

FIG.7is a diagram illustrating an implementation flow in Design-For-Testability (DFT) design of microcomputer1. Incidentally, the standard design steps that are not directly related to the present invention are omitted.

For the pre-DFT netlist (gate level) of microcomputer1inFIG.7, first, a normal scan-based DFT circuit implementation is performed (step S702). Thereafter, Clock Operator11is implemented according to the granularity of the shift clock to be controlled (in unit of one per scan chain or one per group of multiple scan chains) (step S703).

The above steps generate a post DFT netlist of microcomputer1(step S704), and for the generated post DFT netlist (step S705), a clock tree is implemented by clock tree synthesis. Here, as an application condition of the present invention, the sub clock trees from Clock Operator11to each scan chain or scan chain group need to be independent from each other. After clock tree synthesis, P&R (Place & Route) is executed for the netlist and a post-layout netlist is generated (step S706). Finally, the scan chain grouping considering the layout information which can maximize the reduction of the peak shift power is calculated, and the grouping result is applied through the external control in the scan testing.

(Explanation of Design Flow2)

FIG.8is a diagram illustrating a design flow of Clock Operator11of microcomputer1. Incidentally, the standard design steps that are not directly related to the present invention are omitted.

InFIG.8, each two steps are connected by an arrow, it appears that these steps are performed in a time series according to the direction of the arrow.

For a post scan netlist implemented with scan design-based DFT circuit of microcomputer1, the connection between clock source (Clk source) and the clock input of each scan FF is first deleted (step S802). Then, clock operator module with clock outputs (Clk_Sx (x=1, 2, . . . , n)) are generated and implemented in accordance with the number of scan chains, n (step S803). Here, clock source (Clk source), Clk_Sort and shift control signal (ShifterEN) are connected to the inputs of Clock Operator11(step S804). Further, as the output side of Clock Operator11, each clock output (Clk_Sx) is connected to clock input (clk_in) of all scan FF of scan chain Sx (step S805). The above steps generate a post DFT netlist of microcomputer1.

(Effect of the First Embodiment)

During the shift operation of the scan test, in microcomputer1, it is possible to reduce the peak power consumption caused instantaneously by the toggle timing to shift the scan FF belonging to each scan chain.

Furthermore, On/Off of the phase shift function of the shift clock can be controlled by shift control signal (ShifterEN).

In addition, in order to realize the function of independently controlling the clocks of each scan chain, the sub clock trees fanning out from the Clock Operator to each scan chain must be independent from each other.

Second Embodiment

In the second embodiment, the semiconductor device shows a configuration capable of coping with a design having a plurality of clock domains.

FIG.9shows a configuration diagram of a semiconductor device in the second embodiment. Compare with the case of the first embodiment, microcomputer9is different in the point that it comprises a plurality of clock domains therein. If more than one clock domains exist, multiple Clock Operators need to be implemented corresponding to the number of clock domains.

As shown inFIG.9, microcomputer9includes two clock domains (91A,91B), and each clock domain has a plurality of scan chains. The first clock domain (91A) has scan chains S1, S2, S3, S4, and the second clock domain (91B) has scan chains S5, S6, S7, S8.

Clock Operator1(92A) has shift control signal1(ShifterEN1) and ATE clock signal1(ATE_Clk1). Clock Operator2(92B) has shift control signal2(ShifterEN2) and ATE clock signal2(ATE_Clk2).

Furthermore, in order to control the clock of scan chain, the clock sort signal (Clk_Sort[x:0]) of the first embodiment is divided into clock sort signal1(Clk_Sort1[y:0]) and clock sort signal2(Clk_Sort2[x:y]), being assigned to Clock Operator1(92A) and Clock Operator2(92B), respectively. In the second embodiment, but this is not a limitation for applying the present invention.

During the shift operation in scan testing, it is not always necessary to input the same clock to ATE clock signal1(ATE_Clk1) and ATE clock signal2(ATE_Clk2). By shifting the phase of ATE clock signal1(ATE_Clk1) and ATE clock signal2(ATE_Clk2) in advance, the variation of clocks generated from Clock Operator1(92A) and Clock Operator2(92B) can be increased. As a result, the structure of Clock Operators can be simplified, and it is possible to increase the degree of freedom in performing scan chain grouping.

In addition, since the values of clock sort signal1(Clk_Sort1) and clock sort signal2(Clk_Sort2) can be changed by external control, it is also possible to change them by the test pattern (wafer test, assembly test, different tester types, etc.). Thus, even after semiconductor products are manufactured, shift power consumption reduction can be realized according to the actual situation, dynamically.

Furthermore, when microcomputer1is a SoC, the control of shift control signal1(ShifterEN1) and shift control signal2(ShifterEN2) also allows control in block units as in the prior art.

(Effect of the Second Embodiment)

The second embodiment can accommodate a larger scale design compare to the first embodiment. In addition, it can correspond to more complicated clock designs.

Third Embodiment

FIG.10Ais a block diagram showing a configuration of a semiconductor device according to the third embodiment. In this case, an example of the semiconductor device is microcomputer10equipped with Clock Operator101that can output two types of phase shifted clocks.

In microcomputer10, there is an optimization area Z that is particularly sensitive to voltage drop (V-drop), scan chains S1, S2, S3and their output cones C1, C2, C3. The optimization area Z is an LSI design-dependent region, for example, the central area of the chip where the power supply is weak, the area where the logic paths are dense, the area where there is a critical path which is hard to meet the timing constraint, or other reasons. The output cone refers to all logic paths from the output port of the FF belonging to each scan chain to the input port of any FF or the output port of the circuit. Output cones C1, C2, C3overlap with the optimization area Z, respectively. In the overlapped areas switching activity can occur during shift operation.

During shift operation, if the Clock Operator is “On” (e.g. shift control signal (ShifterEN) is “1”), the generated two shift clocks need to be assigned to scan chain S1, S2, S3. As a result, it is necessary to group the scan chains.

After scan chain grouping, the overlap area of each scan chain group should be minimized to suppress the voltage drop (V-drop) of the optimization area Z. Such grouping is the most suitable one.

As shown inFIG.10B, when all scan chains S1, S2, S3perform shift operation at the same timing by the same shift clock, the voltage drop (V-drop) in the optimization area Z exceeds the threshold.

On the other hand,FIG.11Ashows a case where the scan chains S1, S2and the scan chain S3perform shift operation at different timings by the control of Clock Operator101. When the shift operation is performed at different timings, as shown inFIG.11B, the voltage drop (V-drop) within the optimization area Z falls within a predetermined range.

As a result, the reduction effect of peak shift power can be maximized with less shift clock variations.

In examples ofFIG.10AandFIG.11A, one optimization area is one, but there may be a plurality of optimization areas.

Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the embodiment described above, and it is needless to say that various modifications can be made without departing from the gist thereof.