FRONTSIDE DEEP TRENCH ISOLATION (FDTI) STRUCTURE FOR CMOS IMAGE SENSOR

In some embodiments, the present disclosure relates to a method for forming an image sensor and associated device structure. A FDTI trench is formed from a frontside of a substrate between a first pixel region and a second pixel region and then filled to form a FDTI structure. A cap layer is formed over the FDTI structure overlying the first pixel region and the second pixel region of the substrate. A first photodiode is formed in the first pixel region and a second photodiode is formed in the second pixel region. A FD node is formed within the cap layer between the first pixel region and the second pixel region overlying the FDTI structure. The FD node may be shared by a group of pixel regions not separated by the FDTI structure, such that few metal contacts are needed and thus reduce parasitic capacitance issues of proximity metal contacts.

BACKGROUND

Many modern day electronic devices, such as digital cameras and video cameras, contain image sensors to convert optical images to digital data. An image sensor comprises an array of pixel regions, and each pixel region contains a photodiode configured to capture optical signals (e.g., light) and convert it to digital data (e.g., a digital image). Complementary metal-oxide-semiconductor (CMOS) image sensors are often used over charge-coupled device (CCD) image sensors because of their many advantages, such as lower power consumption, faster data processing, and lower manufacturing costs.

DETAILED DESCRIPTION

An image sensor includes a plurality of pixel regions arranged in an array. Each of the plurality of pixel regions may comprise a photodiode configured to detect incident light and convert the incident light to charge carriers. A transfer gate is configured to control the flow of the converted charge carriers to a floating diffusion (FD) node. The FD node is a capacitor-like structure that collects and stores charge carriers generated by the photodiode. The charge carriers stored in the FD node is then converted into a voltage signal by a readout circuitry (e.g., a plurality of transistors including a reset transistor, a source follower transistor, etc.). As image sensors scale down in size, cross-talk can become a more serious problem due to increased pixel densities and reduced distances between the pixels. In one aspect, as the pixel size shrinks, electrical cross-talk becomes more significant, due to the proximity of parasitic capacitances and resistances between conductive structures, such as adjacent metal contacts or the gate and source/drain regions of a transistor. In another aspect, optical cross-talk occurs when light leaks from one pixel to another due to diffraction, reflection, or scattering. As the pixel size decreases, the amount of light that can be captured by each pixel also decreases, which can increase the likelihood of optical cross-talk. Both electrical and optical cross-talk can degrade the image quality.

Frontside deep trench isolation (FDTI) and backside deep trench isolation (BDTI) are two isolation techniques used to provide for separation among the pixels, in order to reduce cross-talk in CMOS image sensors. An image sensor includes a frontside including active areas of pixels and readout circuitry disposed thereon and a backside on the other side of the active area opposite to the readout circuitry. The FDTI involves creating a deep trench from the frontside of the image sensor between the active areas of the pixels, which is then filled with isolation material. The BDTI, on the other hand, involves creating a deep trench from the backside of the image sensor, which is then filled with isolation material. The BDTI is formed after frontside device procedures and handling wafer bonding. Thus, the BDTI formation may have overlap control issues for front pattern alignments because of wafer thickness and bending caused by the bonding. In addition, the BDTI may cause additional device downgrades and even failure since it may introduce additional stress and chemicals after completing the frontside device procedures. Meanwhile, the FDTI occupies surface area that would otherwise be silicon surface area that can be used for active area or for transfer and readout transistors. As discussed above, as scaling down continues, the problem of FDTI is more significant due to the proximity of pixels. For example, for some shared pixel layouts, FD nodes for a group of pixels may be arranged close to one another, and metal contacts and/or metal routing for the FD nodes are causing significant parasitic capacitance issues.

In view of the above, some embodiments of the present disclosure relate to an improved method to form an image sensor including forming a cap layer over a FDTI structure and forming a FD node within the cap layer overlying the FDTI structure, and an associated image sensor device. Specifically, in some embodiments, a FDTI trench is formed from a frontside of a substrate between a first pixel region and a second pixel region adjacent to the first pixel region and then filled to form a FDTI structure. A cap layer is formed over the FDTI structure and overlying the first pixel region and the second pixel region of the substrate. A first photodiode is formed in the first pixel region and a second photodiode is formed in the second pixel region. A FD node is formed within the cap layer between the first pixel region and the second pixel region overlying the FDTI structure. The FD node may be shared by a group of pixel regions, rather than having an individual FD node for each of the pixels, such that fewer metal contacts are needed and thus parasitic capacitance issues of proximity metal contacts is reduced. In addition, by forming the cap layer and forming the shared FD node within the cap layer overlying the FDTI structure, the surface area for active devices is expanded, and thus pixel areas and distance between adjacent gates are increased. As a result, the image sensor would achieve less noise, better image quality, and an increased dynamic range to capture a wider range of light levels from low light conditions to brightest highlights without losing detail.

FIGS.1A-1Dillustrate a series of cross-sectional views100A-100D of some embodiments of a method of forming an image sensor. As shown in the cross-sectional view100A ofFIG.1A, a FDTI structure124is formed from a frontside102fof a substrate102opposite to a backside102b.The FDTI structure124may be formed by performing an etch to form a deep trench followed by filling the deep trench by an isolation material. The isolation material may comprise a stack of dielectric and metal layers. As shown in the cross-sectional view100B ofFIG.1B, in some embodiments, a cap layer112is formed over the FDTI structure124, after forming the FDTI structure124and prior to forming doping areas for active devices on the cap layer112. As shown in the cross-sectional view100C ofFIG.1C, the doping areas are formed on the cap layer112. The doping areas may include photodiodes104, a FD node108, and source/drain regions of other pixel devices, for example. In some embodiments, the FD node108is shared by a group of pixel regions such as pixel regions103a,103binFIGS.1A-1D. As shown in the cross-sectional view100D ofFIG.1D, in some embodiments, a transfer gate110may respectively be formed between the photodiode104and the FD node108. The transfer gate110is configured to control current flow between the photodiode104and the FD node108. The transfer gate110may comprise a gate electrode and a gate dielectric that are disposed along the frontside102fof the substrate102. An inter-layer dielectric (ILD) layer132may be formed over the substrate202and the transfer gate110. Conductive contacts142such as gate contact142aand FD node contact142band metal interconnect layers (not shown) may be subsequently formed through the ILD layer132for the transfer gate110and the FD node108. By forming the cap layer112over the FDTI structure124and forming the doping areas within the cap layer112including the FD node108overlying the FDTI structure124, the surface area for active devices is expanded, and thus pixel areas and distances between adjacent transfer gates110are increased. Also, by forming the FD node108separated from the FDTI structure124by the cap layer112and shared by a group of pixels, parasitic capacitance caused by proximate FD node contacts for neighboring pixels is reduced or avoided.

FIGS.2A-2Billustrate a top view200A and a cross-sectional view200B of some embodiments of an image sensor having a plurality of pixel regions103separated and isolated by a FDTI structure124.FIGS.3-4illustrate cross-sectional views300,400of some additional embodiments of the image sensor with FDTI structure124disposed in the substrate102and the shared FD node108overlying the FDTI structure124. The FDTI structure124may have different shapes as a result of various formation procedures as shown byFIGS.3-4. The cross-sectional views200B,300,400ofFIG.2B,300,400may be taken along line A-A′ inFIG.2A.

As shown in the top view200A ofFIG.2A, the FDTI structure124separates pixel regions103of the image sensor. The FDTI structure124is configured to provide for isolation of the neighboring pixel regions. In some embodiments, a FD node108may be disposed at a crossroad of a group of pixel regions103a-103doverlying the FDTI structure124. The FD node108is of a first doping type, for example, an n-type. The group of pixel regions103a-103dmay be coupled to one same integral FD node, the FD node108. Although a group of four pixel regions103a-103dare illustrated in the figures and described in the specification as sharing a FD node, it is appreciated that a different amount of pixel regions can be designed to share the FD node. A same pattern or multiple different patterns can be repeated to constitute a suitable number of pixel regions arranged for the image sensor.

In some embodiments, each pixel region103of the group of pixel regions103a-103dcomprises a transfer gate110and a photodiode104. The transfer gate110is configured to control current flow between the photodiode104and the FD node108. The transfer gate110may comprise a gate electrode and a gate dielectric that are disposed along a frontside102fof the substrate102. The transfer gate110may vertically extend in the substrate202for better control of the current flow. The gate electrode may comprise, for example, doped polysilicon, a conductive metal (e.g., aluminum), or the like. The gate dielectric may comprise a high-k dielectric, an oxide (e.g., such as silicon dioxide), or the like. The photodiodes104are disposed within respective pixel regions103. The photodiodes104are of the first doping type, for example, an n-type.

As shown inFIG.2B and3-4, for example, the substrate102has a first pixel region103aand a second pixel region103dadjacent to the first pixel region103a.The substrate102may comprise any type of semiconductor body (e.g., silicon/CMOS bulk, SiGe, etc.) such as a semiconductor wafer or one or more die on a wafer, as well as any other type of semiconductor and/or epitaxial layers formed thereon and/or otherwise associated therewith. The substrate102may be prepared with a second doping type (e.g. p-type), by a blanket implant or a grading epitaxial growth process, for example.

In some embodiments, a cap layer112is disposed over a frontside102fof the substrate102. The cap layer112may be disposed blanketly across the pixel regions103of the image sensor. In some embodiments, the cap layer112is of the same material as the substrate102. As an example, the cap layer112may be or be comprised of polysilicon.

In some embodiments, a first photodiode104ais disposed in the first pixel region103a,and a second photodiode104dis disposed in the second pixel region103dadjacent to the first pixel region103a.The first photodiode104aand the second photodiode104dare of a first doping type, for example, an n-type. The first photodiode104aand the second photodiode104dextend from the cap layer112into the substrate102. The FDTI structure124is disposed between the first pixel region103aand the second pixel region103dand separating the first photodiode104aand the second photodiode104d.In some embodiments, the FDTI structure124has a tilted sidewall with a smaller width at a bottom side closer to the backside102bof the substrate102and a greater width at a top side124tcloser to the frontside102fof the substrate102. A tilting range of the FDTI structure124can range from a few degrees to as much as 45 degrees or more. The FDTI structure124may have the width monotonically increasing from the bottom side closer or aligned to the backside102bof the substrate102to the top side124tcloser to the frontside102fof the substrate102.

As shown byFIG.2Bfor example, in some embodiments, the FDTI structure124may be disposed through the substrate102and may have a full depth of the substrate102. Having the FDTI structure124extended through the substrate102, an optimal optical isolation between neighboring pixel regions103a,103dis provided. Also shown byFIG.2Bfor example, in some embodiments, the top side124tof the FDTI structure124is conical-shaped. As shown byFIG.3orFIG.4for example, in some alternative embodiments, the top side124tof the FDTI structure124is planar-shaped. Also as shown byFIG.3orFIG.4for example, in some embodiments, the top side124tof the FDTI structure124may be recessed back from the frontside102fof the substrate102. The FDTI structure124may extend from a backside102bof the substrate102to a position within the substrate102. As shown byFIG.3for example, in some embodiments, a cap-shaped stop layer118can be disposed between the FDTI structure124and the cap layer112. The cap-shaped stop layer118may be disposed on the planar-shaped top side124tof the FDTI structure124. The top side124tof the FDTI structure124may be fully covered by the cap layer112.

The FD node108of the first doping type, for example, the n-type, is disposed within the cap layer112and between the first photodiode104aand the second photodiode104d.The first pixel region103aand second pixel region103dmay share the FD node108. In some embodiments, the FD node108is spaced apart from the FDTI structure124by the cap layer112. A ratio of thicknesses of the cap layer112to the FDTI structure124may be in a range of from about 0.1 to about 0.4. As an example, a depth of the FDTI structure124may be in a range of from about 2 μm and about 10 μm. A width of the FDTI structure124may be in a range of between from about 40 nm to about 400 nm, or in a range of from about 100 nm to about 150 nm. The cap layer112may have a thickness in a range of between about 2000 Å to about 4000 Å. The FD node108may have a thickness in a range of between about 500 Å to about 1000 Å. By having the cap layer112sufficiently thick, e.g., greater than 0.1 times of the thickness of FDTI structure124, or greater than 2000 Å, the FD node108is sufficiently separated from the FDTI structure124, such that the FD node108can be an integral component shared by the first pixel region103aand second pixel region103dwithout being interrupted by the FDTI structure124. By having the cap layer112sufficiently thin, e.g., smaller than 0.4 times of the thickness of FDTI structure124, or smaller than 4000 Å, the top side124tof the FDTI structure124is closer to a top of the first photodiode104aand the second photodiode104d,such that the first pixel region103aand second pixel region103dare sufficiently isolated.

In some embodiments, though not shown in the figures, an anti-reflective layer and color filters can be disposed on the backside102bof the substrate102corresponding to the pixel regions103a,103d.The color filter is configured to allow for the transmission of radiation having a specific range of wavelength while blocking light of wavelengths outside of the specified range. A color filter isolation structure, such as a composite grid, may be formed separating the color filters for isolation purpose. In addition, micro-lenses may be formed over the color filters.

During operation, incident radiation pass through the micro-lenses and the color filters to hit the backside102bof the substrate102and passes from the backside102bof the substrate102to the photodiode104. The photodiode104is configured to convert the incident radiation (e.g., photons) into an electric signal (i.e., to generate electron-hole pairs from the incident radiation). The FDTI structure124isolates the pixel regions103a,103dwhile still prevents leakage of the electrical signal from the FD node108by having the FDTI structure124overlying and spaced apart from the FD node108.

FIGS.5-12illustrate cross-sectional views of some embodiments of a method of forming an image sensor having a FDTI structure and a shared FD node overlying the FDTI structure. AlthoughFIGS.5-12are described in relation to a method, it will be appreciated that the structures disclosed inFIGS.5-12are not limited to such a method, but instead may stand alone as structures independent of the method.

As shown inFIG.5, a FDTI trench122is formed from a frontside102fof a substrate102between a first pixel region103aand a second pixel region103dadjacent to the first pixel region103a.The FDTI trench122may also be formed at a peripheral region of the first pixel region103aand the second pixel region103d.In some embodiments, the FDTI trench122may have a width monotonically increasing from a bottom side closer to the backside102bof the substrate102to a top side closer to the frontside102fof the substrate102. In some embodiments, a hard mask120may be formed over the frontside102fof the substrate102. The hard mask120may be formed by one or more deposition or spin-on processes of various polymer, dielectric, and/or metal materials. An example hard mask120may comprise a tri-layer structure including a carbon-based hard mask, a silicon contained hard mask and a photoresist stacked from bottom to top.

The hard mask120is subsequently patterned to form the FDTI trench122separating the first pixel region103aand the second pixel region103d.The hard mask120can be patterned by a photolithography process with a photoresist layer134patterned, followed by an etching process to etch the hard mask120according to the patterned photoresist layer134. In various embodiments, the etch may comprise a dry etching process having an etching chemistry comprising a fluorine species (e.g., CF4, CHF3, C4F8, etc.) and/or a wet etchant (e.g., hydrofluoric acid (HF) or Tetramethylammonium hydroxide (TMAH)).

As shown inFIG.6, in some embodiments, the FDTI trench122is filled with an isolation material to form a FDTI structure124. In some embodiments, a FDTI precursor124′ may be formed by filling a first set of isolation material from the frontside102fof the substrate. After finishing front-side processes, the work piece is flipped, and the FDTI precursor124′ is replaced by a second set of isolation material in order to form a final FDTI structure124. The isolation material may comprise a stack of dielectric and metal layers. For example, the filling of the isolation material may comprise forming a FDTI liner142′aof dielectric and/or metal lining sidewall and bottom surfaces of the FDTI trench122and a main filling column142′bof polysilicon followed by an etching back procedure. A planarization process may be performed to remove an excessive portion of the isolation material above the substrate102. In addition, in some embodiments, the FDTI precursor124′ is recessed back to a position lower than the frontside102fof the substrate102, and the FDTI precursor124′ is formed with a first depth smaller than a full depth of the substrate102. Though an isolation material replacement process is illustrated below with various embodiments, the FDTI structure can also be directly formed from the frontside102fof the substrate102without a subsequent isolation material replacement process.

As shown inFIG.7, in some embodiments, a cap layer112is formed over the substrate102. In some embodiments, the cap layer112is formed of the same material as the substrate102, such that the photodiodes can be formed smoothly from the cap layer112to extend into the substrate102. In some embodiments, the cap layer112is formed blanketly across the first pixel region103aand the second pixel region103dof the image sensor. In some embodiments, the cap layer112is of the same material as the substrate102. As an example, the cap layer112may be formed of polysilicon that is lightly doped with the second doping type, for example, p-type. In some embodiments, the cap layer112has a doping concentration substantially similar as the substrate102. In some embodiments, the cap layer112is formed by a thermal melt procedure or by an epitaxial deposition process.

Also shown inFIG.7, in some embodiments, the cap layer112is formed with voids114formed between the cap layer112and the FDTI structure124, or the FDTI precursor124′ if an isolation replacement procedure is performed later in the back-side processes. The voids114may have a conical-shape as a result of the growth and merge orientation.

FIGS.8-10show some examples to form various doped regions and gate structures after forming the cap layer112. As shown by more detailed examples below, in some embodiments, a plurality of photodiodes104of a first doping type (e.g., n-type) is formed correspondingly within the plurality of pixel regions. A shared FD node108of the first doping type may be formed at a crossroad region of a group of pixel regions103. A plurality of transfer gate110may be formed correspondingly between the plurality of photodiodes104and the FD node108.

As shown inFIG.8, in some embodiments, the photodiode104is formed within each of the group of pixel regions103a-103d(seeFIG.2Afor example). The photodiode104may comprise doped regions of the first doping type (e.g., n-type) and may be formed by an implantation process from the cap layer112reaching in to the substrate102from the frontside102f.The photodiodes104may comprise multiple doped layers of different doping concentration, and sidewalls of the multiple doped layers are not necessarily aligned. In addition, the FD node108may be formed by doping a portion of the cap layer112with the first doping type (e.g., n-type) and a doping concentration greater than the photodiodes104. In some embodiments, the FD node108has a greater doping concentration than the photodiodes104. The cap layer112may separate the FD node108from the photodiodes104and the substrate102.

Though not shown in the Figures, in some embodiments, an isolation well may be formed along the frontside102fof the substrate102separating the group of pixel regions103a-103d.The isolation well may be formed by selectively performing an implantation process of a second doping type (e.g., p-type) into the substrate102with a masking layer in place to form doped isolation regions. In some embodiments, a shallow trench isolation (STI) (not shown) may also be formed along the frontside102fof the substrate102separating the group of pixel regions103a-103d.The STI structure may be formed by selectively etching the substrate from the frontside102fto form a shallow trench and subsequently forming an oxide or other dielectric material within the shallow trench. The isolation well may be formed from the frontside102fof the substrate102to a position within the cap layer112or all the way through the cap layer112. The isolation well may be centrally aligned with the STI structure.

As shown inFIG.9, in some embodiments, a plurality of transfer gates110is formed correspondingly between the plurality of photodiodes104and the FD node108. The transfer gate110may be formed by depositing a gate dielectric film and a gate electrode film over the substrate102. The gate dielectric film and the gate electrode film are subsequently patterned to form a gate dielectric layer and a gate electrode. The transfer gate110may be a vertical gate extending into the photodiode104. A gate sidewall spacer (not shown) may be formed on a sidewall of the transfer gate110. The transfer gate110may be formed such that it overlies portions of the photodiode104and/or the FD node108.

As shown inFIG.10, in some embodiments, an etch stop layer116may be formed over the cap layer112and the transfer gate110. In some embodiments, the etch stop layer116may comprise a nitride (e.g., silicon nitride), a carbide (e.g., silicon carbide), an oxide (e.g., silicon dioxide), or the like. In some embodiments, the etch stop layer116is formed contouring an upper surface of the frontside102fof the substrate102and sidewall and upper surfaces of the plurality of transfer gates110. Then, an inter-layer dielectric (ILD) layer132is formed over the etch stop layer116, and conductive contacts such as gate contact142aand FD node contact142bcan be formed through the ILD layer132and the etch stop layer116coupled to the transfer gate110and the FD node108. The ILD layer132can be then bonded to a handle substrate144or another functional device (not shown). In some embodiments, the bonding process may use an intermediate bonding oxide layer arranged between the ILD layer132and the handle substrate144. In some embodiments, the bonding process may comprise a fusion bonding process.

Additionally, prior to bonding the handle substrate144, a metallization stack comprising metal interconnect layers arranged within additional ILD layers can be formed over the ILD layer132and electrically coupled to the gate contact142aand the FD node contact142b.In some embodiments, the conductive contacts and the metallization stack may be formed by a damascene process (e.g., a single damascene process or a dual damascene process). Specifically, the ILD layers may be deposited and subsequently etched to form via holes and/or metal trenches. The via holes and/or metal trenches are then filled with a conductive material to form the conductive contacts and the metal interconnect layers. In some embodiments, the ILD layer may be deposited by a physical vapor deposition technique (e.g., PVD, CVD, etc.). The plurality of metal interconnect layers may be formed using a deposition process and/or a plating process (e.g., electroplating, electroless plating, etc.). In various embodiments, the plurality of metal interconnect layers may comprise tungsten, copper, or aluminum-copper, for example.

FIGS.11-12show some examples of flipping over the substrate102for further processing on a backside102bthat is opposite to the frontside102f.As shown inFIG.11, the substrate102may be firstly thinned from the backside102bto reduce a thickness of the substrate102. The substrate102may be thinned to expose the FDTI precursor124′ and allow for radiation to pass through the backside102bof the substrate102to the photodiode104. In some embodiments, the substrate102may be thinned by etching or mechanical grinding the backside102bof the substrate102. In some embodiments, the FDTI precursor124′ may be then removed and replaced with different isolation material filled into the FDTI trench122to form the FDTI structure124. As an example, as shown inFIG.16, a FDTI liner124aof dielectric including high-k dielectric and/or metal, is firstly formed lining sidewall and bottom surface of the FDTI trench122, followed by forming a main filling column124bof polysilicon. A planarization process is then performed to remove excess isolation material. Since the bottom surface of the FDTI trench122may be a conical-shape from the exposed cap layer112, the replaced FDTI structure124may have a conical-shaped top side124tcloser to the frontside102fof the substrate102.

Also shown inFIG.12, in some embodiments, a plurality of color filters128can be subsequently formed over the backside102bof the substrate102. In some embodiments, the plurality of color filters128may be formed individually by forming and patterning respective color filter layers corresponding to the group of pixel regions103a-103d.A color filter layer is a material that allows for the transmission of radiation (e.g., light) having a specific range of wavelength while blocking light of wavelengths outside of the specified range. A color filter isolation structure (not shown), such as a composite grid, may be formed separating the color filters128for isolation purpose.

In addition, a plurality of micro-lenses130may be formed over the plurality of color filters128. As an example, the plurality of micro-lenses may be formed by depositing a micro-lens material above the plurality of color filters128(e.g., by a spin-on method or a deposition process). A micro-lens template having a curved upper surface is patterned above the micro-lens material. In some embodiments, the micro-lens template may comprise a photoresist material exposed using a distributing exposing light dose (e.g., for a negative photoresist more light is exposed at a bottom of the curvature and less light is exposed at a top of the curvature), developed and baked to form a rounding shape. The plurality of micro-lenses is then formed by selectively etching the micro-lens material according to the micro-lens template.

FIGS.13-16show an example where alternative to leaving voids when forming the cap layer112as shown and discussed above associated withFIGS.7-12, in some other embodiments, a stop layer118can be formed between the cap layer112and the FDTI precursor124′. As shown inFIG.13, the stop layer118may be formed within a remaining upper portion of the FDTI trench122and contacting the FDTI precursor124′. In some embodiments, the stop layer118is formed by forming a fill material of dielectric, polysilicon or metal within the remaining upper portion of the FDTI trench122and contacting the FDTI precursor124′ followed by a recess etching process to remove excessive material above the first photodiode104aand the second photodiode104b.In some embodiments, the stop layer118may be formed with a conical shape by adjusting the recess etching process and/or the subsequent wet cleaning, such that the stop layer118can have a top contour matching the voids to be generated from forming the cap layer112. Remaining fabrication steps can be similar to what is discussed above associated withFIGS.7-12, where doping areas are formed within the cap layer112including forming the first photodiode104aand the second photodiode104breaching into the substrate102from the frontside102fof the substrate102, as shown inFIG.14. The work piece may then be flipped to thin down the substrate102from the backside102b.In some embodiments, as shown inFIGS.15-16, the stop layer118may not be removed from the FDTI trench122when flipping the work piece and replacing isolation material from the backside102bto replace the FDTI precursor124′ with the FDTI structure124. The FDTI structure124may be formed with a planar bottom surface contacting the planar bottom surface of the stop layer118. As an example, as shown inFIG.16, a FDTI liner124aof dielectric including high-k dielectric and/or metal, is firstly formed lining sidewall surface of the FDTI trench122and the bottom surface of the stop layer118, followed by forming a main filling column124bof polysilicon. A planarization process is then performed to remove excess isolation material.

FIGS.17-20show an example where alternative to leaving the voids114when forming the cap layer112as shown and discussed above associated withFIGS.7-12or forming the stop layer118in the place of the voids caused by forming the cap layer112as shown and discussed above associated withFIGS.13-16, in some other embodiments, the cap layer112can be formed to fully fill the remaining upper portion of the FDTI trench122and contacting the recessed FDTI structure124. By adjusting forming parameters, such as melt temperature/time, epitaxy pressure/growth rate, and/or final thermal anneal, the cap layer112can be formed with a planar bottom surface covering the entire top surface of the FDTI precursor124′, as shown inFIG.17. Remaining fabrication steps are similar to what is discussed above associated withFIGS.7-12, where doping areas are formed within the cap layer112including forming the first photodiode104aand the second photodiode104breaching into the substrate102from the frontside102fof the substrate102, as shown inFIG.18. The work piece may then be flipped to thin down the substrate102from the backside102b.In some embodiments, as shown inFIGS.19-20, when flipping the work piece and replacing isolation material from the backside102bto replace the FDTI precursor124′ with the FDTI structure124, the FDTI structure124may be formed with a planar bottom surface contacting the planar bottom surface of the cap layer112. As an example, as shown inFIG.20, a FDTI liner124aof dielectric including high-k dielectric and/or metal, is firstly formed lining sidewall surface of the FDTI trench122and the bottom surface of the cap layer112, followed by forming a main filling column124bof polysilicon. A planarization process is then performed to remove excess isolation material.

FIG.21illustrates a flow diagram of some embodiments of a method2100of forming an image sensor having a plurality of pixel regions separated from one another by a FDTI structure and a shared FD node overlying the FDTI structure.

At act2102, an FDTI trench is formed on a frontside of a substrate separating pixel regions. The FDTI trench may also be formed at peripheral regions of the pixel regions. In some embodiments, the FDTI trench may have a width monotonically increasing from a bottom side closer to the backside of the substrate to a top side closer to the frontside of the substrate. See, for example,FIG.5.

At act2104, the FDTI trench is filled with an isolation material. The isolation material may comprise a stack of dielectric and metal layers. For example, the filling of the isolation material may comprise forming a FDTI liner of dielectric and/or metal lining sidewall and bottom surfaces of the FDTI trench and a main filling column of polysilicon followed by an etching back procedure. A planarization process may be performed to remove an excessive portion of the isolation material above the substrate. In addition, in some embodiments, the isolation material is recessed back to a position lower than the frontside of the substrate. See, for example,FIG.6.

At act2106, a cap layer is formed over the FDTI structure and overlying the pixel regions. The cap layer may be formed of the same material as the substrate such that the photodiodes can be formed smoothly from the cap layer to extend into the substrate. In some embodiments, the cap layer is formed blanketly across the pixel regions of the image sensor. In some embodiments, the cap layer is formed by a thermal melt procedure or by an epitaxial deposition process. In some embodiments, the cap layer is formed with voids between the cap layer and the FDTI structure or the precursor. The voids may have a conical-shape as a result of the growth and merge orientation. See, for example,FIG.7.

In some alternative embodiments, the cap layer112can be formed to fully fill the remaining upper portion of the FDTI trench and contacting the isolation material. By adjusting forming parameters, such as melt temperature/time, epitaxy pressure/growth rate, and/or final thermal anneal, the cap layer can be formed with a planar bottom surface covering the entire top surface of the recessed isolation material. See, for example,FIG.17.

Further alternative to leaving the voids between the cap layer and the isolation material when forming the cap layer or forming the cap layer without voids above the isolation material by adjusting process parameters as discussed above, in some embodiments, a stop layer is formed within the remaining space of the FDTI trench. The stop layer may be formed by forming a fill material of dielectric, polysilicon or metal within the remaining upper portion of the FDTI trench followed by a recess etching process to remove excessive material above the substrate. In some embodiments, the stop layer may be formed with a conical shape by adjusting the recess etching process and/or the subsequent wet cleaning, such that the stop layer can have a top contour matching the voids to be generated from forming the cap layer. See, for example,FIG.13.

At act2108, the frontside of the substrate is prepared for forming an image sensor. Specifically, a plurality of photodiodes of a first doping type may be formed in the substrate respectively within a plurality of pixel regions arranged in rows and columns from a top view. A floating diffusion (FD) node of the first doping type may be formed from the frontside of the substrate at a crossroad of the plurality of pixel regions. The FD node may be formed by doping a portion of the cap layer with a doping concentration greater than the photodiodes. The FD node may be separated from the photodiodes by the cap layer. See, for example,FIG.8.

At act2110, a plurality of transfer gates may be formed correspondingly between the plurality of photodiodes and the FD node. The plurality of transfer gates is formed correspondingly between the plurality of photodiodes and the FD node. The transfer gates may be formed by depositing a gate dielectric film and a gate electrode film over the substrate. The gate dielectric film and the gate electrode film are subsequently patterned to form a gate dielectric layer and a gate electrode. An ILD layer is formed over the transfer gates, and conductive contacts such as gate contacts and FD node contacts can be formed through the ILD layer. The ILD layer can be then bonded to a handle substrate or another functional device (not shown). In some embodiments, the bonding process may use an intermediate bonding oxide layer arranged between the ILD layer and the handle substrate. In some embodiments, the bonding process may comprise a fusion bonding process. In some embodiments, prior to bonding, a metallization stack comprising metal interconnect layers arranged within additional ILD layers can be formed over the ILD layer and electrically coupled to the gate contacts and the FD node contacts. In some embodiments, the conductive contacts and the metallization stack may be formed by a damascene process (e.g., a single damascene process or a dual damascene process). The transfer gate may be a vertical gate extending into the photodiodes. See, for example,FIGS.9-10.

At act2112, the work piece is flipped and a backside of the substrate is prepared. A plurality of color filters and/or micro-lenses may be formed at the backside of the substrate corresponding to the plurality of photodiodes. The substrate may be firstly thinned from the backside of the substrate to reduce a thickness of the substrate. The substrate may be thinned to allow for radiation to pass through the backside of the substrate to the photodiode. In some embodiments, the substrate may be thinned to expose the FDTI precursor, and the FDTI precursor may be then partially or fully removed and replaced with different isolation material filled into the FDTI trench to form the FDTI structure. A planarization process is then performed to remove excess isolation material. See, for example,FIGS.11-12.

Therefore, the present disclosure relates to a new method of formation and corresponding device structure of an image sensor. The image sensor is formed to have pixel regions surrounded and isolated from one another by a FDTI structure and a FD node disposed at a crossroad of a group of pixels within a cap layer and overlying the FDTI structure.

Accordingly, in some embodiments, the present disclosure relates to a method for forming an image sensor. The method includes forming a frontside deep trench isolation (FDTI) trench from a frontside of a substrate between a first pixel region and a second pixel region adjacent to the first pixel region and filling the FDTI trench to form a FDTI structure with a first depth. The method further includes forming a cap layer over the FDTI structure and overlying the first pixel region and the second pixel region of the substrate. The method further includes forming a first photodiode in the first pixel region and a second photodiode in the second pixel region. The first photodiode and the second photodiode are of a first doping type. The method further includes forming a floating diffusion (FD) node of the first doping type within the cap layer between the first pixel region and the second pixel region. The FD node overlies the FDTI structure.

In other embodiments, the present disclosure relates to a method for forming an image sensor. The method includes forming a frontside deep trench isolation (FDTI) structure from a frontside of a substrate separating a plurality of pixel regions arranged in rows and columns from a top view and forming a cap layer over the FDTI structure and overlying the plurality of pixel regions. The method further includes forming a plurality of photodiodes of a first doping type from the cap layer and extending in the substrate and forming a floating diffusion (FD) node of the first doping type within the cap layer shared by a group of pixel regions within the plurality of pixel regions. The FD node is arranged at a crossroad of the group of pixel regions overlying the FDTI structure.

In yet other embodiments, the present disclosure relates to image sensor including a substrate having a first pixel region and a second pixel region adjacent to the first pixel region. A cap layer is disposed over a frontside of the substrate. A first photodiode and a second photodiode extend from the cap layer into the substrate. The first photodiode is disposed in the first pixel region, and the second photodiode is disposed in the second pixel region. The first photodiode and the second photodiode are of a first doping type. A frontside deep trench isolation (FDTI) structure is disposed between the first pixel region and the second pixel region. A floating diffusion (FD) node of the first doping type is disposed within the cap layer and spaced apart from the FDTI structure by the cap layer.