Impedance calibration for source series terminated serial link transmitter

Substantially-accurate calibration of output impedance of a device-under-test (DUT) to within a predetermined range of allowable impedance. The DUT is part of a source series terminated (SST) serial link transmitter, in which two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series-connected resistor to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. Output impedance of the DUT is compared to the resistance of a reference resistor, and the comparator provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that individually turns on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates generally to electronic devices and in particular to calibration of electronic devices. Still more particularly, the present invention relates to a method, system, and electronic circuit for providing impedance calibration of electronic devices.

2. Description of the Related Art

Conventional HSS (high speed serializer/deserializer) standards require a transmitter have a differential output impedance in the range of 100 Ohms plus-or-minus (±)20% or better. The more accurate the output impedance (i.e., the smaller the percentage variance around the 100 Ohms), the better (more predictable and accurate) are the operating characteristics of the transmitter. Typically, the measured output impedance is provided by a resistor along with other circuit components (e.g., transistors), with measurable impedance characteristics. The resistor is frequently series-connected to the other components, which themselves may be either series or parallel connected to each other.

A source-series transmitter (SST) (or an inverter driver), is one example transmitter that is required to comply with this differential output impedance standard. With an SST, the output impedance typically consists of field effect transistor (FET) impedance in series with a resistor. FET impedance varies on the order of ±400% across different processes and allowable ASIC (application-specific integrated circuit) voltage variations. Thus, when the FET impedance represents a large enough portion of the overall output impedance, the (variable) FET impedance may easily cause the output impedance to fall out of the required range (i.e., ±20%) for differential output impedance.

The majority of voltage-mode transmitter implementations utilize very large FETs, which provide negligible FET impedance relative to the series connected resistor. These large FETs operate well at lower frequencies, but are not designed to handle the faster (high speed) transmission frequencies desired for current high speed applications (e.g., applications with transmission rates above 3 Gbps, non-return to zero (NRZ) data stream). Thus, smaller transistors, which support the higher speed rating are desired for most devices/applications currently being designed. These smaller transistors exhibit much larger impedances that may cause the circuit device to fall out of the desire range of output impedance.

Designing a transmitter that provides the output impedance characteristics while enabling the faster transmission rates via use of the smaller FETs requires some method of determining when the device being designed meets the requirements for the output impedance characteristics. A need therefore exists for an accurate, reliable process of calibrating a device, such as the transmitter, to meet particular output impedance requirements. This need is addressed by the present invention.

SUMMARY OF THE INVENTION

Disclosed is a method, system and circuit device that enables reliable and substantially accurate calibration of the output impedance of a device-under-test (DUT) to within a predetermined range of allowable output impedance. The electrical characteristics of a DUT are controlled by a feedback control signal such that a desired electrical characteristic is achieved. To achieve the particular electrical characteristic, the DUT is fed a control input that is also applied to an active circuit. One or more reference voltages are compared with the output voltage of the DUT and, based on the comparison, an adjustment is made to the control signal that is fed back to the DUT and to the active circuit. When the comparisons yield a desired output, the DUT is calibrated to the desired electrical characteristic. The control signal is then applied to the active circuit which consequently exhibits the desired electrical characteristic.

In one embodiment, the DUT is part of an inverter circuit that is configured as a source series terminated (SST) serial link transmitter. In the SST transmitter, two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series connected resistor value to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. The output impedance of the DUT is compared to the resistance of a reference resistor. A comparator compares the electrical characteristics of the DUT relative to the reference resistance and provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that operates to individually turn on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

The present invention provides a method, system and circuit device that enables reliable and substantially accurate calibration of the output impedance of a device-under-test (DUT) to within a predetermined range of allowable output impedance. The electrical characteristics of a DUT are controlled by a feedback control signal such that a desired electrical characteristic is achieved. To achieve the particular electrical characteristic, the DUT is fed a control input that is also applied to an active circuit. One or more reference voltages are compared with the output voltage of the DUT and, based on the comparison, an adjustment is made to the control signal that is fed back to the DUT and to the active circuit. When the the comparisons yield a desired output, the DUT is calibrated to the desired electrical characteristic. The control signal is then applied to the active circuit which consequently exhibits the desired electrical characteristic.

In one embodiment, the DUT is part of an inverter circuit that is configured as a source series terminated (SST) serial link transmitter. In the SST transmitter, two branches of parallel transistors each provide an impedance value when particular transistors of the parallel branch are turned on. The impedance value is added to a series connected resistor value to provide the output impedance. The DUT consists of one branch of parallel transistors in series with a resistor. The output impedance of the DUT is compared to the resistance of a reference resistor. A comparator compares the electrical characteristics of the DUT relative to the reference resistance and provides a control signal based on whether the output impedance falls within the pre-set percentage variance of the reference resistance. The control signal is processed by a FSM (finite state machine) that operates to individually turn on or off the transistors within the parallel branch until the DUT impedance value falls within the desired range.

With reference now to the figures,FIG. 1provides a block circuit diagram illustrating basic calibration of a DUT in a continuous feedback loop configuration. The feedback loop enables a continuous approach to the DUT calibration. As illustrated, DUT110provides an output test voltage (Vtst)120, which is applied as a first input to an operational amplifier (Op AMP)140. Op AMP140receives a second input, reference voltage (Vref)125from reference generator130. At Op AMP140, output voltage (Vo) is generated as voltage gain (Av) (of Op AMP140) multiplied by the difference between Vtst120(which is shown as upper (+) input) and Vref125(which is shown as the lower (−) input). This calculated output voltage is represented as control voltage (Vctl)145, which is provided to DUT110via feedback loop155.

DUT110exhibits change in electrical characteristics due to small changes to Vctl145due to changes in Vtst120. By providing Vctl145to DUT110via feedback loop155, the calibration mechanism is able to continuously adjust the value of the Vctl145until a desired characteristic (e.g., Vtst=Vref) is measure or exhibited by the DUT110(as determined by the value of Vtst120). The resulting value of Vctl145is applied to active circuit150which consequently exhibits the desired behavior. DUT110is representative of active circuit150such that when Vctl145is applied to active circuit150, active circuit150exhibits the same (or scaled) electrical characteristics as DUT110.

Operation of the circuit occurs as follows. Active circuit150is controlled by a small-signal voltage (i.e., Vctl145). DUT110generates a small-signal test voltage (i.e., Vtst120). Vtst120and reference voltage, Vref125, are applied to Op AMP140. Op AMP140has voltage gain Av and transfer characteristic Vo=Av*(V+−V−). In ideal operating environments, Av approaches infinity, and as Av approaches infinity, Op AMP140forces Vctl145to a voltage that causes Vtst120to be substantially equal to Vref125. Thus, DUT110is calibrated to approximate the electrical behavior that produces the desired reference voltage (Vref125) such that Vref=Vtst. The same small-signal control voltage (Vctl145) is applied to the active circuit150, which approximates the desired electrical behavior.

The calibration method provided byFIG. 1is referred to as a continuous approach.FIG. 2illustrates a discrete implementation of the calibration method that yields a resulting electrical characteristic which falls within an upper and lower bound. Within the descriptions of the figures, similar elements are provided similar names and reference numerals as those of the previous figure(s). Where a later figure utilizes the element in a different context or with different functionality, the element is provided a different leading numeral representative of the figure number (e.g,2xxforFIG. 2 and 3xxforFIG. 3). The specific numerals assigned to the elements are provided solely to aid in the description and not meant to imply any limitations (structural or functional) on the invention.

InFIG. 2, calibration of DUT110is completed iteratively via a Finite State Machine (FSM)260through logic control signal, CTL255, (on feedback loop). DUT110generates Vtst120that is compared to two reference voltages, low reference voltage (Vlo)225and high reference voltage (Vhi)227at respective comparator circuits. The comparator circuits are low voltage comparator (CMPL)235and high voltage comparator (CMPH)240. Vlo225is generated by a low bound reference generator230, while Vhi227is generated by high bound reference generator235.

Each comparator circuit receives Vtst120as a first input, illustrated as input “A” and a second input comprising one of the reference voltages, illustrated as input B. Thus, within each comparator, “B” represents the value of Vlo or Vhi, respectively, while “A” represents the current value of Vtst120. Each comparator completes a respective comparison for each new value/input of Vtst120, and each comparator then outputs a 1 or 0 to indicate the result of the comparison. The inequality illustrated indicates the desired value of Vtst120and the particular comparison provided by that particular comparator. Both values together indicate the range of the output electrical characteristics being measured. In the illustrative embodiment, an output of1for either comparator indicates that the inequality shown within the comparator evaluates as true (i.e., A>B for CMPL or A<B for CMPH), while a0indicates the inequality evaluates as false.

Thus, when Vtst120is greater than Vlo225, CMPL236is set to a logic high (‘1’). Otherwise, CMPL236is a logic low (‘0’). The inverse conditions apply to CMPH241, that is logic high (1) is achieve when Vtst120is less than Vhi227and 0 is achieved when Vtst120is greater than Vhi227. Effectively, Vlo225and Vhi227are utilized to bound voltage Vtst120. Finite state machine (FSM)260receives logic signals CMPL236and CMPH241and incrementally sets VCtl245accordingly. When both of the comparators provide a 1 at its output, Vtst120is within the required range, and FSM260stops iterating new values of Vctl245. Table I below provides an example output and the resulting effects on CTL245transmitted to DUT110via feedback loop255.

Since the value of Vtst120cannot be both less than Vlo225and higher than Vhi227, the “0,0” output is not applicable to the discussion and only applies when the calibration mechanism is turned off. According to the table a “1,1” output is desired, and different changes are made to CTL245depending on whether Vtst120is below Vlo225or above Vhi227.

FSM260processes the logic signals CMPL236and CMPH241such that Vctl245forces the DUT's voltage, Vtst120, to be greater than Vlo and less than Vhi. Thus, DUT110is forced to approximate the electrical behavior (e.g., impedance) that produces the desired voltage range. CTL245is also applied to active circuit150, which approximates the desired electrical behavior. In the illustrative embodiments, the calibration mechanism operates as a voltage divider. The mechanism is applicable to other types of circuits that require calibration.

FIG. 3illustrates an exemplary circuit that is utilized as the active circuit that requires calibration, according to one embodiment. According to the embodiment, the active circuit is a controlled-impedance CMOS circuit (also referred to as an impedance-controlled inverter or SST driver)300. In the illustrated embodiment, the calibration features of the invention are applied to a replica SST driver segment of the active circuit, which replica segment is calibrated against an accurate resistor. That is, the DUT in the illustrative embodiments is a replica of the top portion or bottom portion of the active circuit illustrated byFIG. 3.

As illustrated, SST driver300is configured with parallel FET fingers (i.e., the FET is broken into many parallel fingers), such that the FET may be trimmed to the allocated impedance for a given process and voltage corner. The sizes of the fingers are such that the change in the parallel FET impedance is monotonic when the total FET impedance approaches the desired value.

During implementation, the FET impedance is allocated to be a preset percentage of the total impedance relative to the series resistor (i.e. 20% FET versus 80% resistor) such that the required accuracy is met with a reasonable number of FET fingers. Notably, this configuration limits the size of the driver output stage, which is important due to bandwidth and ASIC core size constraints.

Referring specifically to theFIG. 3, SST driver300comprises a pull-up (PFET) circuit and a pull-down (NFET) circuit, receiving the same input340but exhibiting inverted output voltage characteristics relative to each other. Pull-up circuit (also illustrated byFIG. 4, described below) is the portion illustrated at the top of SST driver300, and comprises P-type input transistor (Tdatap)315, connected at its source to a parallel branch310of N×P-type transistors (e.g., PFETs)312, where N is an integer number of the total number of parallel PFETs312, numbered Tp0-TpN-1. Each PFET312receives a corresponding control input signal313as its gate input. PFETs312are connected at their source to a high voltage (VTT)305and at their drains to the source of input transistor315.

The impedance of Tdatap is very small and negligible to the total impedance of the pull-up circuit. Further, when SST driver300is in a pull-up operational mode (P-FETS are on), Tdatan impedance approaches infinity. Conversely, when SST driver300is in the pull-down mode (N-FETS are on), Tdatap impedance approaches infinity. Parallel-connected PFETs312provide collective impedance referred to herein as Rpon360, which is shown merely for illustration and simplicity of the description since Rpon360is not a physical component within circuit300. The collective impedance value of Rpon360is variable depending on the number of PFETs312that are turned on, which is in turn controlled by the (on/off) values of the corresponding control inputs313.

Coupled to the drain of Tdatap315is resistor (Rp)320, which is in turn connected at its other end to output node for output terminal350. In one embodiment, Rp320exhibits resistive characteristics of +/−10%. When “on” input340is applied across the gate of Tdatap315and one or more of PFETs312are turned on, the output node sees an output impedance equal to Rp320plus the impedance value of Rpon360(with the impedance of Tdatap315being negligible).

Pull-down circuit (also illustrated byFIG. 5, described below) is the portion illustrated at the bottom of circuit300, and is very similarly configured to pull-up circuit except that the transistors are all N-type transistors and the lower parallel branch330comprises MxN-type transistors, where M is an integer value that may be different from N. Thus circuit300does not necessarily have the same number of P-type transistors and N-type transistors, particularly within the respective parallel groups. Notably, while the transistors within each circuit is described as PFETS and NFETs, respectively, those skilled in the art appreciate that the particular circuit configuration and calibration features of the invention may apply to other types of transistors other than FETs. Specific reference to FETs is thus not meant to imply any limitation on any aspect of the invention or application thereof to a circuit/device to be calibrated.

As shown byFIG. 3, pull-down circuit comprises N-type input transistor (Tdatan)317that is connected at its drain to parallel grouping310of M×N-type transistors (NFETs)332, where M is an integer number of the total number of NFETs332, numbered Tn0-TnM-1. Each NFET332receives a corresponding control input signal333as its gate input. NFETs310are connected at their drains to a low voltage (VSS)307and at their source to the drain of input transistor (Tdatan)317. The impedance of Tdatan317is very small and negligible to the total impedance of the pull-down circuit. NFETs332provide collective impedance referred to herein as Rnon365(which is again shown merely for illustration and simplicity of the description since it is not a physical component within circuit300). The collective impedance value of Rnon365is variable depending on the number of NFETs332that are turned on, which is in turn controlled by the (on/off) values of the corresponding control inputs333.

Coupled to the source of Tdatan317is resistor (Rn)325, which is in turn connected at its other end to output node350. When “on” input340is applied across the gate of Tdatan317and one or more of NFETs332are turned on (via control input333), output node sees an output impedance equal to Rn325plus the impedance value of Rnon365(with the impedance of input transistor317being negligible).

Operation of the above circuit300, which is relevant to its utilization as a device under test and/or active circuit is as follows. For an input voltage of VTT (i.e., a digital ‘1’), Tdatan317is turned on, and Tdatap315is off. The M parallel NFETs act as switches that are on or off as dictated by the logic control bus NCTL<m−1:0>. Each parallel NFET332has an on-impedance Rnon<i> for i=[m−1, m−2, . . . , 0]. Each control bit333is a digital ‘1’ or ‘0’.

At this operational state, the output impedance of SST driver's pull down circuit is equal to the sum of the resistance Rn325in series with the M parallel NFETs Tm<m−1>, Tm<m−2>, . . . Tm<0>. With the impedance of Tdatan317assumed to be negligible, the effective impedance of the parallel NFETs is denoted Rnon365and determined as follows:
[NCTL<m−1>* 1/Rnon<n−1>+NCTL<n−2>* 1/Rnon<n−2>+. . . +NCTL<0>* 1/Rnon<0>]−1.
With this value of Rnon365, the output impedance of SST driver's (or inverter circuit's) pull down circuit is Rn+Rnon.

For an input voltage of VSS (or a digital ‘0’), the input PFET Tdatap315is turned on, and the NFET Tdatan317is off. In this operational state, the output impedance of SST driver's pull up circuit is derived in a similar manner to be Rp+Rpon. As stated above, the number of parallel PFETs may differ from the number of parallel NFETs, but for simplicity, M is assumed to be the same as N. To achieve a desired output impedance for the impedance-controlled inverter ofFIG. 3, the logic control buses NCTL<m−1:0>and PCTL<n−1:0>must be set to turn one or all of the respective devices on (or off). Applying the calibration mechanism ofFIG. 2to the circuit ofFIG. 3provides a discrete approach to setting the control busses313/333and ultimately calibrating the inverter's output impedance characteristics.FIG. 4andFIG. 5illustrate the calibration mechanism ofFIG. 2individually applied to pull-up and pull-down circuits ofFIG. 3.

As described below, the pull-up or pull-down circuit of above SST driver300is calibrated against another reference resistor (Rref),. Then, the FET impedance in series combination with a resistor is calibrated to be Rref plus-or-minus (+/−) a pre-selected/determined tolerance (e.g., +/−10%). When applied to the calibration mechanism, the PFET and NFET portions of the SST driver segment are separated into independently calibrated halves. Each FET-resistor combination is placed in a voltage divider configuration with Rref, and the resulting voltage, Vtst, is compared to a reference voltage. A state machine observes the comparator output and sets the FET controls appropriately. When the output signal from the comparator is substantially zero, indicating both inputs are substantially the same, the resistance of the FET-resistor combination correctly matches Rref. When the output is not zero, then the controller adjusts the setting of the variable resistor (FET resistance) by turning on/off one or more of the FETs (fingers) within the particular parallel branch.

As shown byFIG. 4, the pull-up circuit is connected as the DUT110of the calibration circuit illustrated byFIG. 2. Rp320is connected to a reference resistor, Rref410, with the node at which the resistors connect providing the signal Vptst420. Additionally, each reference generator is represented as a series-connected pair of resistors, with the first resistor, f(R)415/425, connected at one end to VTT and the second resistor, R417/430, connected to a lower voltage source. As provided by the figure, f(R) is a resistor that is some percentage (x%) higher or lower than R417, where f is a function that adds/subtracts x% to provide a range of resistance around the value of R417. Thus, for the low bound reference generator230, f(R)=(1−x)*R, while for high-bound reference generator235, f(R)=(1+x)*R. In the illustrative embodiment, x is assumed to be 10%.

Comparators235and240compare Vptst420against the reference voltages Vlo425and Vhi427, respectively. COMPPL=Av*(Vlo−Vptst) and COMPPH=Av*(Vptst−Vhi). COMPPL, COMPPH=‘11’ when Vxtst range is Vlo>Vptst and Vhi<Vptst. Under this condition, Rpon+Rp>(1−x)Rref and Rpon+Rp<(1+x)Rref. When this condition is not met, however, adjustments are made to Vctl245and COMPPL, COMPPH=‘11’ when the desired value of Vtst is found.

As with the comparison described above with reference toFIG. 2and Table I, if Vptst420is less than Vlo425, then the output COMPPL is ‘1’. Also, when Vptst420is greater than Vhi427, then the output COMPPH is ‘1’. That is, if Vlo>Vptst and Vptst<Vhi, then COMPPL, COMPPH=‘11’ and Vptst is calibrated within the desired range. The methodology for determining the condition where Vptst is less than Vlo involves setting VTT*Rref/(Rpon+Rp+Rref)<VTT/(2−x), then solving for Rpon+Rp, as follows:
VTT*Rref/(Rpon+Rp+Rref)<VTT/(2−x)
1/(Rpon+Rp+Rref)<1/(Rref(2−x))
Rpon+Rp+Rref>Rref(2−x)
Rpon+Rp>(1−x)Rref
With the above, Vptst is less than Vlo when Rp+Rpon>(1−x)Rref. Then, solving Vptst >Vhi gives Rpon+Rp<(1+x)Rref. When the above analysis is completed, the comparators provide COMPPL, COMPPH=‘11’ only when (1−x)*Rref<Rpon+Rp<(1+x)*Rref.

Once the results are outputted by comparators235and240, COMPPL and COMPPH are evaluated by FSM242. FSM242alters the control bus PCTL<n−1:0>245(by reducing the overall impedance of DUT410) until the condition COMPPL, COMPPH=‘11’ is met. Reduction of the overall output impedance (Rpon+Rp) involves switching “on” one or more additional parallel transistors312to reduce the value of Rpon. For calibration that requires increasing the value of the output impedance (i.e., where Rpon+R<Rlo), one or more of the (currently on) parallel transistors312are switched off. Switching the transistors on or off is controlled by control input313, which is a discrete signal received from PCTL245.

During actual calibration, one starting point may be when Vtst is low and Rpon+Rp is high, indicating that the PFETS are turned off. By turning on PFETs, using feedback control gate signals, the Rpon+Rp resistance decreases and Vtst increases accordingly. Similarly, the calibration may begin with Vtst high and the resistance value low, indicating that the PFETS are turned on. The value of Vtst is then adjusted by turning off PFETs again via feedback control gate signals until Vtst falls within the range of voltage desired.

As mentioned above, SST driver300is calibrated in two stages, withFIG. 4providing the calibration of the PFET component (i.e., the pull-up circuit). A similar process is applied to the NFET component (i.e., pull-down circuit) withinFIG. 5where DUT110represents the pull-down circuit ofFIG. 3series-connected with Rref510at VTT. When pull-down circuit is utilized, the process sets NCTL<n−1:0> such that (1−x)*Rref<Rnon+Rn<(1+x)*Rref. Thus, when the SST driver300is provided as DUT110, both control outputs, PCTL<n−1:0> and NCTL<n−1:0> are applied to the active circuit150ofFIG. 3. The SST driver300then has an output resistance bounded by [(1−x)Rref, (1+x)Rref].

Notably, in one implementation, the impedance-controlled inverter described herein is utilized as an SST transmitter fabricated on-chip with the calibration mechanism also integrated on the chip. The transmitter may be a part of a termination network and the calibration mechanism is utilized to calibrate each half of the voltage mode driver. The impedance is measured and adjusted as operating conditions (e.g., temperature) changes. This implementation enables dynamic calibration of voltage mode transmitter so that the transmitter's impedance matches that of the transmission channel to which the transmitter is coupled. This point at which the impedances match (and the point at which the test voltage falls within the desired range) may be referred to as a point of calibration for the circuit.

As a final matter, it is important that while an illustrative embodiment of the present invention has been, and will continue to be, described in the context of a fully functional computer system with installed management software, those skilled in the art will appreciate that the software aspects of an illustrative embodiment of the present invention are capable of being distributed as a program product in a variety of forms, and that an illustrative embodiment of the present invention applies equally regardless of the particular type of signal bearing media used to actually carry out the distribution. Examples of signal bearing media include recordable type media such as floppy disks, hard disk drives, CD ROMs, and transmission type media such as digital and analogue communication links.