Method and apparatus for correcting errors in memory device

A memory controller analyzes read data received from a memory device and first error correction code (ECC) data of the read data. A control unit generates a plurality of sub-data from write data to be written in the memory device where the number of error bits in the read data is greater than a number of error bits that can be corrected using the first ECC data. An ECC block generates the first ECC data and second ECC data by using substantially the same algorithm to correct errors in each of the sub-data. The control unit transmits each of the sub-data, the first ECC data and the second ECC data to the memory device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2010-0125710 filed on Dec. 9, 2010, the disclosure of which is hereby incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

Embodiments of the inventive concept relate generally to error correction technology. More particularly, embodiments of the inventive concept relate to a memory controller that controls a memory device to generate error correction code (ECC) data and uses the ECC data to correct errors in read data.

Semiconductor memory devices can be roughly divided into two categories according to whether they retain stored data when disconnected from power. These categories include volatile memory devices, which lose stored data when disconnected from power, and nonvolatile memory devices, which retain stored data when disconnected from power. Examples of volatile memory devices include dynamic random access memory (DRAM) and static random access memory (SRAM). Examples of nonvolatile memory devices include flash memory, electrically erasable programmable read-only memory (EEPROM), and a resistive random access memory (RRAM).

Flash memory is an especially popular form of nonvolatile memory due to various attractive features such as relatively high storage capacity, low power consumption, and resistance to mechanical shock. However, as the storage capacity of flash memory increases, it becomes more difficult to maintain reliable performance. Consequently, researchers continue to develop error correction strategies to address reliability issues in newer flash memory devices.

SUMMARY OF THE INVENTION

According to one embodiment of the inventive concept, a memory controller comprises a control unit that analyzes read data received from a memory device and first ECC data of the read data, and generates a plurality of sub-data from write data to be written in the memory device where the number of error bits in the read data is greater than the number of error bits that can be corrected by using the first ECC data. The memory controller further comprises an ECC block that generates the first ECC data and second ECC data by using substantially the same algorithm to correct errors in different units of the sub-data. The control unit transmits each of the plurality of sub-data, the first ECC data and the second ECC data to the memory device.

According to another embodiment of the inventive concept, a memory controller comprises a control unit that receives bad block information for a plurality of memory cells included in a memory device and generates multiple units of sub-data from write data to be written in the memory device where the received bad block information indicates a bad block. The memory controller further comprises an ECC block that generates first ECC data and second ECC data by using substantially the same algorithm to correct errors in each unit of sub-data. The control unit transmits each of the units of sub-data, the first ECC data and the second ECC data to the memory device.

According to another embodiment of the inventive concept, an error correction method comprises receiving information indicating a number of errors in data stored in a memory device, determining whether the number of errors is greater than a number of errors that can be corrected using a first ECC, and upon determining that the number of errors in the data is greater than the number of errors that can be corrected by the first ECC, generating multiple units of sub-data from write data to be written in the memory device, and generating the first ECC and a second ECC by using substantially the same algorithm to correct errors in different units of the sub-data, and transmitting the sub-data, the first ECC data and the second ECC data to the memory device.

These and other embodiments can improve the reliability of read operations performed by a memory device such as a flash memory device.

DETAILED DESCRIPTION

Selected embodiments of the inventive concept are described below with reference to the corresponding drawings. These embodiments are presented as teaching examples and should not be construed to limit the scope of the inventive concept.

In the description that follows, where a feature is referred to as being “connected” or “coupled” to another feature, it can be directly connected or coupled to the other feature or intervening features may be present. In contrast, where a feature is referred to as being “directly connected” or “directly coupled” to another feature, there are no intervening features present. As used herein, the term “and/or” encompasses any and all combinations of one or more of the associated listed items and may be abbreviated as “/”.

The terms first, second, etc., are used herein to describe various features, but the described features should not be limited by these terms. Rather, these terms are used merely to distinguish between different features. For example, a first signal could be termed a second signal, and, similarly, a second signal could be termed a first signal without departing from the disclosed teachings.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a”, “an” and “the” are intended to encompass plural forms as well, unless the context clearly indicates otherwise. Terms such as “comprises” and/or “comprising,” or “includes” and/or “including” specify the presence of stated features, but do not preclude the presence or addition of one or more other features.

FIG. 1is a block diagram of a memory system10according to an embodiment of the inventive concept, andFIG. 2is a conceptual diagram illustrating operations of a memory controller shown inFIG. 1.

Referring toFIGS. 1 and 2, memory system10comprises a memory controller20and a memory device40. Memory controller20comprises a host interface25, a memory interface26, a control unit22, and an ECC block24. Memory controller20controls the overall operation of memory device40in response to a request from a host30.

Host interface25communicates with host30to transmit and receive data. Host interface25typically comprises a standardized interface such as a peripheral component interconnect (PCI) interface or a universal serial bus (USB) interface. Memory interface26communicates with memory device40to transmit and receive data. The data can include, for instance, a command, an address, data, or a control signal. Interfaces25and26can be implemented in a variety of ways, such as by hardware, or software for driving the hardware.

Control unit22controls the operation of ECC block24. Control unit22receives read data RDATA output from memory device40via memory interface26, and it receives first ECC data ECC1from ECC block24. First ECC data ECC1is an error correction code for read data RDATA.

Control unit22analyzes the received read data RDATA and first ECC data ECC1, determines whether the number of error bits in the read data is greater than the number of error bits that can be corrected by using first ECC data ECC1. Upon determining that the number of error bits in the read data is greater than the number of error bits that can be corrected by using first ECC data ECC1, control unit22determines that a read failure has occurred.

Memory controller20receives write data WDATA, and control unit22generates sub-data WDATAa and WDATAb from write data WDATA. Here, each of sub-data WDATAa and WDATAb has the same number of bits as write data WDATA before division. Each of sub-data WDATAa and WDATAb is appended to ECC data ECC1or ECC2.

Referring toFIG. 2, control unit22divides write data WDATA of 1024 bytes into data WDATA1and WDATA2of 512 bytes and generates sub-data WDATAa or WDATAb by padding data WDATA1and WDATA2with zeros (Z-PAD1and Z-PAD2). The padding can be, for example, 512 bytes for each of data WDATA1and WDATA2. Accordingly, the number of bytes of each of sub-data WDATAa and WDATAb is equal to the number of bytes of write data WDATA.

Control unit22controls ECC block24so that first ECC data ECC1and second ECC data ECC2is generated by using the same algorithm to correct an error of each divided sub-data WDATAa or WDATAb. Control unit22transmits each of divided sub-data WDATAa and WDATAb, first ECC data ECC1, and second ECC data ECC2to memory device40through memory interface26. That is, control unit22transmits data including sub-data WDATAa, first ECC data ECC1, data including sub-data WDATAb and second ECC data ECC2to memory device40.

Control unit22can output addresses ADD such that first ECC data ECC1and second ECC data ECC2are stored in the same memory block or different memory blocks of memory device40. In addition, control unit22can output addresses ADD such that first ECC data ECC1and second ECC data ECC2are stored in the same page or different pages.

In some embodiments, memory controller20receives bad clock information INF for a plurality of memory cells included in memory device40and monitors whether the received bad block information INF indicates a bad block or good block.

Where bad block information INF indicates a bad block, control unit22divides write data WDATA into sub-data WDATAa and WDATAb after write data WDATA from host30is input to memory controller20through host interface25.

Control unit22controls ECC block24to generate first ECC data ECC1and second ECC data ECC2by using the same algorithm to correct each error of divided sub-data WDATAa and WDATAb and transmits each of the divided sub-data WDATAa and WDATAb, first ECC data ECC1and second ECC data ECC2to memory device40through memory interface26.

FIG. 3is a status table displaying bad block information of memory device40ofFIG. 1. As illustrated inFIG. 3, bad block information INF includes a number of program/erase cycles30-1, a program/read count30-2, an ECC error count30-3, and a program/erase failure count30-4of memory device40. For example, a block0is shown with bad block information30-1through30-4having values 82, 800, 8 and 1, respectively.

In some embodiments, bad block information INF is stored in a region where metadata is stored. The metadata typically includes state information on an available block, a page and a memory cell of the memory device. The metadata can be stored in memory device40or a nonvolatile memory device50separate from memory device40. Nonvolatile memory device50can be, for example, a NAND flash memory device. Bad block information INF is typically updated periodically to reflect a current state.

ECC block24comprises an ECC decoder24-1and an ECC encoder24-2. ECC decoder24-1detects an error in read data RDATA output from memory device40and corrects the error using first ECC data ECC1. For example, where read data RDATA and first ECC data ECC1are received from memory device40according to a request from host30, and an error is detected in the received read data RDATA, ECC block24corrects the error using first ECC data ECC1.

In addition, where each of sub-data WDATAa and WDATAb, and each of ECC data ECC1and ECC2are received from memory device40and an error is detected in each received sub-data WDATAa and WDATAb, ECC block24corrects errors in sub-data WDATAa and WDATAb using ECC data ECC1and ECC2, respectively. Error-corrected read data RDATA or error-corrected divided sub-data WDATA1and WDATA2is transmitted to host30through host interface25.

ECC encoder24-2generates first ECC data ECC1under the control of control unit22and generates second ECC data ECC2having the same number of bits as first ECC data ECC1with first ECC data ECC1using the same algorithm.

FIG. 4is a memory map of memory device40illustrated inFIG. 1according to an embodiment of the inventive concept. As illustrated in the memory map, memory device40comprises a plurality of memory blocks41,42and43, and memory blocks41,42and43comprise a plurality of pages Page 0 through Page n. AlthoughFIG. 4illustrates three memory blocks41,42and43, memory device40is not limited to these memory blocks.

Memory blocks41,42and43include a data area40-1storing write data WDATA output from host30and a spare area40-2storing first ECC data ECC1including information related to write data WDATA (or the first ECC data ECC1and the second ECC data ECC2). In some embodiments, first ECC data ECC1and second ECC data ECC2are stored in the same memory block according to addresses ADD output from memory controller20. For example, first ECC data ECC1and second ECC data ECC2can be stored in a first block41. In other embodiments, first ECC data ECC1and second ECC data ECC2are stored different memory blocks according to addresses ADD output from memory controller20. For example, first ECC data ECC1can be stored in a first block41and second ECC data ECC2may be stored in a second block42. Where first ECC data ECC1and second ECC data ECC2are stored in the same memory block, first ECC data ECC1and second ECC data ECC2can be stored in the same page or different pages according to addresses ADD output from memory controller20.

FIG. 5is a block diagram illustrating an electronic device100incorporating a memory system according to another embodiment of the inventive concept. In this embodiment, electronic device100takes the form of a mobile communication device, such as a cellular phone, a smart phone, a personal digital assistant (PDA), or a radio communication device.

Referring toFIG. 5, electronic device100comprises memory controller20, memory device40, a processor110, a display120, a radio transceiver130, and an input device140. Memory controller20controls data access operation of memory device40, such as program operations, erase operations, and read operations, under the control of a processor110. A program-verify operation is typically included as a part of a program operation.

Page data programmed in memory device40can be displayed through display120under the control of processor110and/or memory controller20.

Radio transceiver130transmits and receives radio signals through an antenna ANT. Radio transceiver130converts a radio signal received through antenna ANT into a signal to be processed by processor110, and processor110processes the signal output from radio transceiver130and transmits a processed signal to memory controller20or display120. Memory controller20programs a signal processed by processor110in memory device40. Moreover, radio transceiver130converts a signal output from processor110into a radio signal and outputs a converted radio signal to an external device through an antenna ANT.

Input device140receives a control signal for controlling an operation of processor110or data to be processed by processor110. Input device140can take a variety of forms, such as a touch pad, a computer mouse, a keypad, or a keyboard.

Processor110controls operations of display130so that data output from memory controller20, data output from radio transceiver130, and data output from input device140is displayed through display120. In some embodiments, memory controller20is implemented as a part of a processor or as a chip separate from a processor.

FIG. 6is a block diagram illustrating an electronic device200incorporating a memory system according to another embodiment of the inventive concept. In this embodiment, electronic device200takes the form of an information processing system such as a personal computer (PC), a tablet PC, a net-book, an e-reader, a personal digital assistant (PDA), a portable multimedia player (PMP), a MP3 player, or a MP4 player.

Referring toFIG. 6, electronic device200comprises memory controller20, memory device40, a processor210, an input device220, and a display230. Processor210displays data stored in memory device40through display230according to data input through input device220. Input device220can take any of various forms, such as a touch pad, a computer mouse, a keypad, or a keyboard.

Processor210controls overall operations of memory system200and memory controller20, and memory controller20controls operations of memory device40. In some embodiments, memory controller20can be implemented as part of processor210, or in a chip separate from processor210.

FIG. 7is a block diagram illustrating an electronic device300incorporating a memory system according to still another embodiment of the inventive concept. In this embodiment, electronic device300takes the form of a memory card or a smart card.

Referring toFIG. 7, electronic device300comprises memory controller20, memory device40, and a card interface320. Memory controller20controls data exchange between memory device40and card interface320. Card interface320can be, for example, a secure digital (SD) card interface or a multi-media card (MMC) interface. However, it is not restricted to these types of interfaces.

Card interface320enables data exchange between a host and memory controller20according to protocol of a host. Card interface320typically implements a standardized protocol, such as USB or interchip (IC)—USB protocol. Card interface320can be implemented by hardware supporting a protocol used in a host, software, or some other technique.

Where electronic device300is connected to a host such as a PC, a tablet PC, a digital camera, a digital audio player, a cellular phone, console video game hardware or a digital set-top box, the host may perform data communication with memory device40through card interface320and memory controller20.

FIG. 8is a block diagram illustrating an electronic device400incorporating a memory system according to still another embodiment of the inventive concept. In this embodiment, electronic device400takes the form of an image processing device, such as a digital camera or a digital camera-equipped cellular phone.

Referring toFIG. 8, electronic device400comprises memory controller20, memory device40, a processor410, an image sensor420, and a display430. Image sensor420converts an optical image into digital signals, and the converted digital signals are transmitted to processor410or memory controller20. Under the control of processor410, the converted digital signals are displayed through display430or stored in memory device40through memory controller20.

Data stored in memory device40is displayed through display430under the control of processor410and memory controller20. In various alternative embodiments, memory controller20can be incorporated in processor410or in a chip separate from processor410.

FIG. 9is a block diagram illustrating an electronic device600incorporating a memory system according to still another embodiment of the inventive concept. In this embodiment, electronic device600takes the form of a data storage device such as a solid state drive (SSD).

Referring toFIG. 9, electronic device600comprises memory controller20, a plurality of memory devices40, a buffer manager620, a DRAM630, and a host640.

Memory controller20controls data processing operations of memory devices40, volatile DRAM630, and buffer manager620. For example, it controls storage of data received from host640in volatile memory device630.

FIG. 10is a flowchart illustrating an error correction method according to an embodiment of the inventive concept. For convenience, the method is described with reference to the memory controller ofFIG. 1, but it is not restricted to this memory controller.

Referring toFIGS. 1,2and10, memory controller20receives read data RDATA and first ECC data ECC1from memory device40in response to a request from host30(S101).

Memory controller20analyzes read data RDATA and first ECC data ECC1and determines if the number of error bits included in read data RDATA is greater than the number of error bits that can be corrected using first ECC data ECC1(S102). If so (S102=Yes), memory controller20divides write data WDATA to be written in the memory device40into sub-data WDATAa and WDATAb, generates first ECC data ECC1and second ECC data ECC2using substantially the same algorithm to correct each error of the divided sub-data WDATAa and WDATAb, and transmits each divided sub-data WDATAa and WDATAb, first ECC data ECC1and second ECC data ECC2to memory device40(S103).

Memory device40stores sub-data WDATAa and WDATAb, first ECC data ECC1and second ECC data ECC2in a memory block designated by addresses ADD output from memory controller20(S105). The number of bits of each divided sub-data WDATAa and WDATAb becomes equal to the number of bits of the write data WDATA through zero padding. Where the number of error bits included in read data RDATA is equal to or less than the number of error bits that can be corrected by using first ECC data ECC1according to a determination result (S102=No), memory controller20generates only first ECC data ECC1on write data WDATA and transmits write data WDATA and first ECC data ECC1to memory device40(S104).

Memory device40stores write data WDATA and first ECC data ECC1in a memory block designated by addresses ADD output from memory controller20(S105).

FIG. 11is a flowchart illustrating an error correction method according to another embodiment of the inventive concept. For convenience, the method is described with reference to the memory controller ofFIG. 1, but it is not restricted to this memory controller.

Referring toFIGS. 1,2and11, memory controller20receives bad block information INF for a plurality of memory cells included in memory device40(S111). Memory controller20then determines whether received bad block information INF indicates a bad block or a good block (S112). Where bad block information INF indicates a bad block (S112=Yes), memory controller20divides write data WDATA to be written in memory device40into sub-data WDATAa and WDATAb, generates first ECC data ECC1and second ECC data ECC2by using the same algorithm to correct each error of sub-data WDATAa and WDATAb, and transmits sub-data WDATAa and WDATAb, and first ECC data ECC1and second ECC data ECC2to memory device40(S113).

Here, bad block information INF includes the number of program/erase cycles30-1, program/read count30-2, ECC error count30-3, or program/erase failure count30-4of memory device40

Memory device40stores each of sub-data WDATAa and WDATAb, and first ECC data ECC1and second ECC data ECC2in a memory block designated by addresses ADD output from memory controller20(S115). Where bad block information INF indicates a good block (S112=No), memory controller20generates first ECC data for write data WDATA and transmits write data WDATA and first ECC data ECC1to memory device40(S114). Memory device40stores write data WDATA and first ECC data ECC1in a memory block designated by addresses output from memory controller20(S115).

FIG. 12is a graph illustrating a corrected block error rate as a function of a bit error rate of a multi level cell (MLC) in a memory device according to an embodiment of the inventive concept. The data ofFIG. 12is generated using an error correction method of memory controller20as described above. The error correction method uses two ECC algorithms to correct errors in 512 byte data using 16 bytes of data. This can provide superior error correction compared with an ECC algorithm that corrects errors in 1024 byte data using 16 bytes. This improvement is illustrated by a difference between a line A and a line B.

As indicated by the foregoing, a memory controller and a related error correction method can correct errors using a different number of bits according to the number of errors. It can do this by dividing data into sub-data and applying error correction codes to the sub-data using substantially the same algorithm. The described techniques and technologies can improve the reliability of stored data in a relatively efficient way.

The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the inventive concept. Accordingly, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims.