Semiconductor device

According to one embodiment, a semiconductor device includes a first electrode, first regions, second regions, an eighth semiconductor region, a ninth semiconductor region of the second conductivity type, a tenth semiconductor region, second electrodes, and a third electrode. Each first region includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, and a gate electrode. The first regions and the second regions alternate in the second direction. Each of the second regions includes a fifth semiconductor region, a sixth semiconductor region, and a seventh semiconductor region. The eighth semiconductor region is provided between the first semiconductor regions and between the fifth semiconductor regions. The eighth semiconductor region is electrically connected to the first semiconductor regions. The third electrode is provided on the tenth semiconductor region with a first insulating layer interposed. The third electrode is electrically connected to the gate electrodes.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2017-022571, filed on Feb. 9, 2017; the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

As a semiconductor device to be used in power conversion or the like, there is an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) in which an FWD (Free Wheeling Diode) is incorporated in an IGBT (Insulated Gate Bipolar Transistor). This semiconductor device desirably has a high avalanche resistance.

DETAILED DESCRIPTION

According to one embodiment, a semiconductor device includes a first electrode, a plurality of first regions, a plurality of second regions, an eighth semiconductor region of the first conductivity type, a ninth semiconductor region of the second conductivity type, a tenth semiconductor region of the first conductivity type, a plurality of second electrodes, and a third electrode. Each of the first regions includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a fourth semiconductor region of the second conductivity type, and a gate electrode. The first semiconductor region is provided on the first electrode. The second semiconductor region is provided on the first semiconductor region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided on the third semiconductor region. The gate electrode is provided on the second semiconductor region. The gate electrode faces the third semiconductor region with a gate insulating layer interposed in a second direction. The second direction is perpendicular to a first direction directed from the first semiconductor region toward the second semiconductor region. The first regions are separated from each other in the second direction and a third direction. The third direction is perpendicular to the first direction and the second direction. The second regions are separated from each other in the second direction and the third direction. The first regions and the second regions alternate in the second direction. Each of the second regions includes a fifth semiconductor region of the second conductivity type, a sixth semiconductor region of the second conductivity type, and a seventh semiconductor region of the first conductivity type. The fifth semiconductor region is provided on the first electrode. The sixth semiconductor region of the second conductivity type is provided on the fifth semiconductor region. The seventh semiconductor region is provided on the sixth semiconductor region. The eighth semiconductor region is provided between the first semiconductor regions and between the fifth semiconductor regions in the third direction. The eighth semiconductor region is electrically connected to the first semiconductor regions. The ninth semiconductor region is provided on the eighth semiconductor region. The tenth semiconductor region of the first conductivity type is provided on the ninth semiconductor region. The second electrodes are provided on the third semiconductor regions, the fourth semiconductor regions, and the seventh semiconductor regions. The second electrodes are electrically connected to the fourth semiconductor regions and the seventh semiconductor regions. The third electrode is provided on the tenth semiconductor region with a first insulating layer interposed. The third electrode including an interconnect portion located between the second electrodes. The third electrode is separated from the second electrodes. The third electrode is electrically connected to the gate electrodes.

The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated.

In the drawings and the specification of the application, components similar to those described thereinabove are marked with like reference numerals, and a detailed description is omitted as appropriate.

An XYZ orthogonal coordinate system is used in the description of the embodiments. A direction from a p+-type collector region1toward a semiconductor layer10(an n−-type semiconductor region11) is taken as a Z-direction (a first direction). Two mutually-orthogonal directions perpendicular to the Z-direction are taken as an X-direction (a third direction) and a Y-direction (a second direction).

In the following description, the notations of n+, n, n−, p+, and p indicate relative levels of the impurity concentrations of the conductivity types. In other words, a notation marked with “+” indicates an impurity concentration relatively higher than a notation not marked with either “+” or “−;” and a notation marked with “−” indicates an impurity concentration relatively lower than a notation not marked with either “+” or “−.”

The embodiments described below may be implemented by reversing the p-type (a first conductivity type) and the n-type (a second conductivity type) of the semiconductor regions.

FIG. 1is a plan view of a semiconductor device100according to an embodiment.

FIG. 2is a perspective sectional view including an A-A′ section ofFIG. 1.

FIG. 3is a perspective sectional view including a B-B′ section ofFIG. 1.

FIG. 4is a perspective sectional view including a C-C′ section ofFIG. 1.

FIG. 5is a plan view showing a structure of a lower surface of the semiconductor device100according to the embodiment.

The semiconductor device100is an RC-IGBT.

As shown inFIG. 1, the semiconductor device100includes a plurality of IGBT regions R1(first regions) and a plurality of FWD regions R2(second regions). The plurality of IGBT regions R1is separated from each other in the X-direction and the Y-direction. The plurality of FWD regions R2is separated from each other in the X-direction and the Y-direction. The IGBT regions R1and the FWD regions R2alternate in the Y-direction.

As shown inFIG. 1, the emitter electrode31and the gate pad32are separated from each other on an upper surface of the semiconductor device100. The emitter electrode31is multiply provided in the X-direction. Each emitter electrode31is provided on the IGBT regions R1and the FWD regions R2that alternate in the Y-direction. The gate pad32includes an interconnect portion32asurrounding the plurality of emitter electrodes31.

A part of the interconnect portion32aextends in the Y-direction between the emitter electrodes31. The part of the interconnect portion32ais located between the IGBT regions R1adjacent to each other in the X-direction and between the FWD regions R2adjacent to each other in the X-direction when viewed from the Z-direction.

As shown inFIG. 2, the collector electrode30is provided on a lower surface of the semiconductor device100. The p+-type collector region1and the n+-type cathode region2are provided on the collector electrode30and electrically connected to the collector electrode30. The n-type buffer region3is provided on the p+-type collector region1and the n+-type cathode region2.

The n−-type semiconductor layer10is provided on the n-type buffer region3. The n−-type semiconductor layer10includes an n−-type semiconductor region11(second semiconductor region) and an n−-type semiconductor region12(sixth semiconductor region). The n−-type semiconductor region11is located on the p+-type collector region1. The n−-type semiconductor region12is located on the n+-type cathode region2.

The p-type base region5and the gate electrode20are provided on the n−-type semiconductor region11. The gate electrode20faces the p-type base region5with the gate insulating layer21interposed in the Y-direction. The n+-type emitter region6and the p+-type contact region7are selectively provided on the p-type base region5.

The p-type anode region8and the field plate electrode25are provided on the n−-type semiconductor region12. The field plate electrode25faces the p-type anode region8with the insulating layer26interposed in the Y-direction. The p+-type anode region9is selectively provided on the p-type anode region8.

The emitter electrode31is provided on the p-type base region5, the n+-type emitter region6, the p+-type contact region7, the p-type anode region8, the p+-type anode region9, and the field plate electrode25, and electrically connected to these members. The insulating layer27is provided between the gate electrode20and the emitter electrode31, and these electrodes are electrically separated from each other.

A plurality of p-type base regions5, a plurality of n+-type emitter regions6, a plurality of p+-type contact regions7, a plurality of p-type anode regions8, a plurality of p+-type anode regions9, a plurality of gate electrodes20, and a plurality of field plate electrodes25are provided in the Y-direction, and each of them extends in the X-direction.

The IGBT region R1includes the p+-type collector region1, a part of the n-type buffer region3, the n−-type semiconductor region11, the p-type base region5, the n+-type emitter region6, the p+-type contact region7, the gate electrode20, the gate insulating layer21, and the insulating layer27described above.

The FWD region R2includes the n+-type cathode region2, another part of the n-type buffer region3, the n−-type semiconductor region12, the p-type anode region8, the p+-type anode region9, the field plate electrode25, and the insulating layer26described above.

As shown inFIGS. 3 and 4, the p+-type semiconductor region14is provided between the p+-type collector regions1and between the n+-type cathode regions2in the X-direction. The n−-type semiconductor layer10further includes an n−-type semiconductor region13(ninth semiconductor region) provided on the p+-type semiconductor region14.

The p+-type semiconductor region15is provided on the n−-type semiconductor region13. The p+-type semiconductor region15is provided between the p-type base regions5, between the p-type anode regions8, between the gate electrodes20, and between the field plate electrodes25in the X-direction. The p+-type semiconductor region15is in contact with the p-type base region5and the p-type anode region8in the Y-direction. The p+-type semiconductor region15is electrically connected to the emitter electrode31via the p-type base region5and the p-type anode region8.

A length in the Z-direction of the p+-type semiconductor region15is larger than a length in the Z-direction of the gate electrode20and larger than a length in the Z-direction of the field plate electrodes25. A lower end of the p+-type semiconductor region15is located on a lower side of a lower end of the gate insulating layer21and a lower end of the insulating layer26.

A concentration of a p-type impurity in the p+-type semiconductor region14is, for example, the same as a concentration of a p-type impurity in the p+-type collector region1. Or the concentration of a p-type impurity in the p+-type semiconductor region14may be different from the concentration of a p-type impurity in the p+-type collector region1.

The p+-type collector region1and the p+-type semiconductor region14are, for example, integrally formed. Or the p+-type collector region1and the p+-type semiconductor region14may be separately formed.

The contact portion28is electrically connected to the gate electrode20. The contact portion28is provided on the p+-type semiconductor region15with the insulating layer27interposed. A part of the interconnect portion32ais provided on the contact portion28and is electrically connected to the contact portion28. In other words, the gate electrodes20of each IGBT region R1is electrically connected to the gate pad32shown inFIG. 1via the contact portion28.

As shown inFIG. 5, the p+-type semiconductor region14extends in the Y-direction between the p+-type collector regions1and between the n+-type cathode regions2. The plurality of p+-type collector regions1arranged in the Y-direction is electrically connected to each other via the p+-type semiconductor region14. A part of the n-type buffer region3is, for example, provided around the plurality of p+-type collector regions1, the plurality of n+-type cathode regions2, and the p+-type semiconductor region14.

Examples of materials of the respective constituent elements will be described.

The p+-type collector region1, the n+-type cathode region2, the n-type buffer region3, the p-type base region5, the n+-type emitter region6, the p+-type contact region7, the p-type anode region8, the p+-type anode region9, and the n−-type semiconductor layer10contain silicon, silicon carbide, gallium nitride, or gallium arsenide as a semiconductor material. In the case where silicon is used as the semiconductor material, as an n-type impurity, arsenic, phosphorus, or antimony can be used. As a p-type impurity, boron can be used.

The gate electrode20, the field plate electrode25, and the contact portion28contain a conductive material such as polysilicon. The gate insulating layer21, the insulating layer26, and the insulating layer27contain an insulating material such as silicon oxide. The collector electrode30, the emitter electrode31, and the gate pad32contain a metal such as aluminum.

Next, an operation of the semiconductor device100will be described.

When a voltage of a threshold value or more is applied to the gate electrode20in a state where a positive voltage is applied to the collector electrode30with respect to the emitter electrode31, a channel (inversion layer) is formed in a region near the gate insulating layer21in the p-type base region5. The IGBT region R1is brought into an on-state. At this time, electrons are injected into the n−-type semiconductor layer10from the n+-type emitter region6through this channel, and holes are injected into the n−-type semiconductor layer10from the p+-type collector region1. Thereafter, when a voltage applied to the gate electrode20is decreased to less than the threshold value, the channel in the p-type base region5disappears. The IGBT regions R1is brought into an off-state.

In the case where, for example, a bridge circuit is formed by a plurality of semiconductor devices100, when one semiconductor device100is switched from an on-state to an off-state, an induced electromotive force is applied to the emitter electrode31of another semiconductor device100. This is based on an inductance component of the bridge circuit. According to the induced electromotive force, the FWD region R2in this another semiconductor device100operates. At this time, holes are injected into the n−-type semiconductor layer10from the p-type base region5(p-type contact region7), and electrons are injected into the n−-type semiconductor layer10from the n+-type cathode region2.

An effect of the embodiment will be described with reference toFIG. 6.

FIG. 6is a plan view showing a structure of a lower surface of a semiconductor device110according to a reference example.

As shown inFIG. 6, the semiconductor device110does not have the p+-type semiconductor region14in comparison with the semiconductor device100. In the semiconductor device110, in place of the p+-type semiconductor region14, a part of the n-type buffer region3is provided between the p+-type collector regions1and between the n+-type cathode regions2. Although not shown inFIG. 6, in the semiconductor device110, the p+-type semiconductor region15shown inFIGS. 3 and 4is not provided.

When the semiconductor devices100and110are turned off, a large voltage is applied to the collector electrode30with respect to the emitter electrode31by an induced electromotive force or the like. Due to the large voltage, the semiconductor devices100and110are shifted to an avalanche state. At this time, impact ionization occurs in a bottom portion of the gate insulating layer21or in a bottom portion of the insulating layer26, and electrons and holes are generated in the n−-type semiconductor layer10. The generated electrons are drifted toward the collector electrode30to decrease a potential on a side of the collector electrode30of the n−-type semiconductor layer10. A built-in potential between the n−-type semiconductor region11and the p+-type collector region1decreases. Holes are injected into the n−-type semiconductor region11from the p+-type collector region1, and a current flows through the semiconductor devices100and110.

The ease of occurrence of impact ionization varies from each gate insulating layer21and each insulating layer26. This is based on a variation in depth, shape, or the like of the gate insulating layer21and the insulating layer26. When impact ionization occurs locally in a part of the gate insulating layers21and the insulating layers26, a current flows locally in the p+-type collector region1(IGBT region R1) near the part. According to this local current flow, a current filament occurs.

In a place where the current filament occurs, a temperature increases with the lapse of time. When the temperature increases, a mean free path length of a carrier decreases. Due to this, impact ionization becomes less likely to occur. Therefore, when the temperature increases, the current filament moves to a region having a low temperature adjacent thereto.

In the FWD region R2where the n+-type cathode region2is provided on the lower surface, holes are not injected from the collector electrode30. Due to this configuration, the current filament does not move to the FWD region R2. In the case of the semiconductor device110according to the reference example, the current filament continues to move in the IGBT region R1.

For example, when a temperature on a center side of the IGBT region R1increases, a part of the current filament moves to a vicinity of a boundary between the IGBT region R1and the FWD region R2. At this time, the current filament does not move to the FWD region R2, or move to a center side of the IGBT region R1having an increased temperature. The current filament continues to occur in the vicinity of the boundary between the IGBT region R1and the FWD region R2. As a result, the temperature in the vicinity of the boundary between the IGBT region R1and the FWD region R2continues to increase by the current filament. Finally, the semiconductor device110is destroyed by thermal runaway.

In the semiconductor device100according to the embodiment, the p+-type semiconductor region14is provided between the p+-type collector regions1and between the n+-type cathode regions2in the X-direction. The plurality of p+-type collector regions1is electrically connected to each other via the p+-type semiconductor region14. The p+-type semiconductor region15electrically connected to the emitter electrode31is provided on an upper side of the p+-type semiconductor region14.

Holes are injected into the n−-type semiconductor layer from the collector electrode30through the p+-type semiconductor region14. Therefore, the current filament moves to the p+-type semiconductor region14on an outside of the IGBT region R1, and can move to another IGBT region R1. Further, in the case where the p+-type semiconductor region15is provided on an upper side of the p+-type semiconductor region14, impact ionization occurs on a p-n junction surface between the n−-type semiconductor region13and the p+-type semiconductor region15. According to this configuration, the current filament easily moves to a region where the p+-type semiconductor region14is provided. As a result, a local increase in temperature in the semiconductor device100is suppressed. A possibility that the semiconductor device100is destroyed by the current filament can be decreased. That is, the avalanche resistance is enhanced.

On the p+-type semiconductor region15, the interconnect portion32aof the gate pad32is provided with the insulating layer27interposed, and the interconnect portion32aand the gate electrodes20of each IGBT region R1are electrically connected to each other. According to this configuration, a distance between the pad portion of the gate pad32and each gate electrode20can be decreased. Therefore, delay of a signal to the gate electrode20when a voltage is applied to the pad portion can be suppressed.

As described above, according to the embodiment, while enhancing the avalanche resistance, delay of a gate signal can be suppressed.

A concentration of a p-type impurity in the p+-type semiconductor region15is higher than a concentration of a p-type impurity in the p-type base region5, and is higher than a concentration of a p-type impurity in the p-type anode region8. According to this configuration, in the case where a current filament occurs in the vicinity of the p+-type semiconductor region15, holes are discharged to the emitter electrode31in a shorter time. An increase in potential of the p-type base region5is suppressed. An n-p-n parasitic transistor composed of the n+-type emitter region6, the p-type base region5, and the n−-type semiconductor layer10becomes difficult to operate. As a result, a possibility that the semiconductor device100is destroyed can be further decreased.

An experimental result of the semiconductor device100according to the embodiment will be described with reference toFIG. 7.

FIG. 7is a graph showing a characteristic of the semiconductor device according to the embodiment.

The p+-type semiconductor region14includes a first portion14aas shown inFIG. 4. The first portion14ais provided between the n+-type emitter regions6in the X-direction.

InFIG. 7, a horizontal axis represents a length L1(μm) in the X-direction of the first portion14a, and a vertical axis represents an avalanche resistance Eavaof the semiconductor device100. That is,FIG. 7shows a change in the avalanche resistance Eavawhen the length L1of the first portion14ais changed. InFIG. 7, the avalanche resistance Eavaof each semiconductor device100is expressed by a relative ratio.

In an experiment related toFIG. 7, a plurality of semiconductor devices100in which the length L1is changed are used. The voltage of the collector electrode30in an off-state is set to 600 V. The avalanche resistance Eavaof each semiconductor device100is measured.

From the experimental result shown inFIG. 7, it is found that when the length L1is 100 μm or less, a variation in the avalanche resistance Eavais large, and also an average of the avalanche resistance Eavais low. It is found that when the length L1is 200 μm or more, a high avalanche resistance Eavais obtained as compared with the case where the length L1is 500 μm or less. Therefore, the length L1is desirably 520 μm or more.

In the semiconductor device100according to the embodiment, the n-type buffer region3, the p+-type contact region7, the p+-type anode region9, the field plate electrode25, and the insulating layer26are not essential, and it is also possible to omit these constituent elements. The arrangement, shape, number, etc. of the IGBT region R1and the FWD region R2are not limited to the examples shown inFIGS. 1 to 5, and can be appropriately changed.

FIG. 8is a plan view showing a structure of a lower surface of another semiconductor device according to the embodiment.

In the example shown inFIG. 5, a part of the n-type buffer region3is provided around the p+-type collector region1and the p+-type semiconductor region14. A p-type semiconductor region16may be provided as shown inFIG. 8, in place of the n-type buffer region3.

A concentration of a p-type impurity in the p-type semiconductor region16is, for example, lower than a concentration of a p-type impurity in the p+-type collector region1. Alternatively, a concentration of a p-type impurity in the p-type semiconductor region16may be the same as a concentration of a p-type impurity in the p+-type collector region1. The p-type semiconductor region16may be integrally formed with the p+-type collector region1and the p+-type semiconductor region14.

FIG. 9is a sectional view showing a part of a semiconductor device200according to a first variation of the embodiment.

The semiconductor device200is different from the semiconductor device100in the arrangement of the n+-type emitter region6and the p+-type contact region7provided on the p-type base region5, and the arrangement of the p+-type anode region9provided on the p-type anode region8.

In the semiconductor device100, the n+-type emitter region6and the p+-type contact region7are arranged with in the Y-direction on the p-type base region5. Each of the n+-type emitter region6and the p+-type contact region7extends in the X-direction.

In the semiconductor device200, the n+-type emitter regions6and the p+-type contact regions7alternate in the X-direction on the p-type base region5. A plurality of p+-type anode regions9is provided on the p-type anode region8. The p+-type anode regions9are separated from each other in the X-direction.

Also in the semiconductor device200according to the variation, in the same manner as the semiconductor device100shown inFIGS. 3 to 5, delay of a gate signal can be suppressed while enhancing the avalanche resistance of the semiconductor device200by providing the p+-type semiconductor region14and the p+-type semiconductor region15.

FIG. 10is a plan view showing a structure of a lower surface of a semiconductor device300according to a second variation of the embodiment.

FIG. 11is a perspective sectional view including an A-A′ section ofFIG. 10.

FIG. 12is a perspective sectional view including a B-B′ section ofFIG. 10.

The semiconductor device300is different from the semiconductor device100in that a plurality of p+-type collector regions1is arranged in the IGBT region R1. The p+-type collector regions1are separated from each other. The plurality of p+-type collector regions1is, for example, arranged along the X-direction and the Y-direction as shown inFIG. 10. As shown inFIGS. 11 and 12, an n-type semiconductor region (a part of the n-type buffer region3) is provided between the p+-type collector regions1.

A distance between the adjacent p+-type collector regions1is set so that a current filament can move between these p+-type collector regions1. For example, the distance between the p+-type collector regions1is smaller than the length in the X-direction or the Y-direction of the p+-type collector region1. The distance between the p+-type collector regions1may be 10 μm or less.

An effective concentration of a p-type impurity in the lower surface of the IGBT region R1can be decreased by providing the p+-type collector regions1which are separated from each other in the IGBT region R1. Due to the decrease of the effective concentration, injection of holes from the lower surface when the IGBT region R1is operated is suppressed, and a switching time is reduced, and thus, switching loss can be reduced.

Also in the variation, the p+-type semiconductor region14extends in the Y-direction between the IGBT regions R1and between the n+-type cathode regions2. Therefore, a current filament occurring in the IGBT region R1can move to another IGBT region R1. A possibility that the semiconductor device300is destroyed by the current filament can be decreased.

A shape of an outer periphery of the p+-type collector region1is arbitrary. In the example shown inFIG. 10, the outer periphery of the p+-type collector region1is circular. The shape of the outer periphery may be elliptical or polygonal.

FIG. 13is a plan view showing a structure of a lower surface of a semiconductor device400according to a third variation of the embodiment.

FIG. 14is a perspective sectional view including an A-A′ section ofFIG. 13.

The semiconductor device400is different from the semiconductor device100in that a region where a concentration of a p-type impurity is relatively high and a region where a concentration of the p-type impurity is relatively low are provided in the p+-type collector region1in the IGBT region R1. Specifically, as shown inFIGS. 13 and 14, the p+-type collector region1includes a second portion1bwhere a concentration of a p-type impurity is relatively high and a third portion1cwhere a concentration of the p-type impurity is relatively low. For example, a plurality of second portions1bis arranged in the X-direction and the Y-direction. The second portions1bare side separated from each other. The third portion1cis provided between the second portions1band around the plurality of second portions1b.

According to the configuration, a p-type impurity concentration distribution may be formed in the p+-type collector region1. Also in the variation, in the same manner as the second variation, an effective concentration of a p-type impurity in the lower surface of the IGBT region R1can be decreased, and switching loss can be reduced. A current filament can move between the IGBT regions R1through the p+-type semiconductor region14. Therefore, a possibility that the semiconductor device400is destroyed can be decreased.

FIG. 15is a plan view showing a structure of a lower surface of a semiconductor device500according to a fourth variation of the embodiment.

FIG. 16is a perspective sectional view including an A-A′ section ofFIG. 15.

The semiconductor device500is different from the semiconductor device100in that a plurality of p+-type semiconductor regions14is provided in place of the p+-type semiconductor region14extending in the Y-direction. The plurality of p+-type semiconductor regions14is arranged along the Y-direction. The p+-type semiconductor regions14are separated from each other. A part of the plurality of p+-type semiconductor regions14is provided in the IGBT region R1(between the p+-type collector regions1) in the X-direction. Another part of the plurality of p+-type semiconductor regions14is provided in the FWD region R2(between the n+-type cathode regions2) in the X-direction.

A distance between the p+-type collector region1and the p+-type semiconductor region14which are the most contiguous to each other, and a distance between the p+-type semiconductor regions14are set so that a current filament can move between these regions. For example, each of these distances is smaller than a length in the X-direction or the Y-direction of the p+-type semiconductor region14. Each of these distances is, for example, 10 μm or less.

In the same manner as the second variation and the third variation, switching loss of the semiconductor device500can be reduced by providing the plurality of p+-type semiconductor regions14separated from each other in place of the p+-type semiconductor region14extending in the Y-direction.

It is also possible to use the structure of the p+-type semiconductor region14according to the variation in combination with the structure of the IGBT region R1shown in the second variation and the third variation. Switching loss of the semiconductor device500can be further reduced.

FIG. 17is a plan view showing a structure of a lower surface of a semiconductor device600according to a fifth variation of the embodiment.

FIG. 18is a perspective sectional view including an A-A′ section ofFIG. 17.

The semiconductor device600is different from the semiconductor device100in that the p+-type semiconductor region14includes a region where a concentration of a p-type impurity is high and a region where a concentration of the p-type impurity is low. Specifically, as shown inFIGS. 17 and 18, the p+-type semiconductor region14includes a fourth portion14dand a fifth portion14e. A concentration of a p-type impurity in the fourth portion14dis relatively high. A concentration of the p-type impurity in the fifth portion14eis relatively low. For example, a plurality of fourth portions14dis arranged in the X-direction and in the Y-direction. The fourth portions14dare separated from each other. The fifth portion14eis provided between the fourth portions14dand around the plurality of fourth portions14d.

Also in the variation, in the same manner as the fourth variation, switching loss of the semiconductor device500can be reduced. It is also possible to use the structure of the p+-type semiconductor region14according to the variation in combination with the structure of the IGBT region R1shown in the second variation and the third variation.

FIG. 19is a plan view showing a structure of a lower surface of a semiconductor device700according to a sixth variation of the embodiment.

The semiconductor device700is different from the semiconductor device100in that a plurality of p+-type semiconductor regions14is provided in the X-direction as shown inFIG. 19. Three or more IGBT regions R1are arranged in the X-direction and three or more FWD regions R2are arranged in the X-direction in the semiconductor device700. The p+-type semiconductor region14is provided between the IGBT regions R1adjacent to each other in the X-direction and between the FWD regions R2adjacent to each other in the X-direction.

A current filament can more easily move between the p+-type collector regions1by providing the plurality of p+-type semiconductor regions14. Therefore, according to the variation, a possibility that the semiconductor device700is destroyed can be further decreased.

FIG. 20is a plan view showing a structure of a lower surface of a semiconductor device800according to a seventh variation of the embodiment.

FIG. 21is a perspective sectional view including an A-A′ section ofFIG. 20.

The semiconductor device800is different from the semiconductor device100in the structure of the p+-type semiconductor region14. The p+-type semiconductor region14includes a sixth portion14fand a seventh portion14g. As shown inFIG. 21, the sixth portion14fof the p+-type semiconductor region14extends in the Y-direction between the IGBT regions R1and between the FWD regions R2. The seventh portion14gof the p+-type semiconductor region14extends in the X-direction between the FWD regions R2.

As shown inFIG. 21, on the seventh portion14gextending in the X-direction, the n-type semiconductor region12is provided, and thereon, the p-type anode region8and the field plate electrode25are provided. In other words, the p+-type semiconductor region15is not provided on the seventh portion14g.

A region where a current filament can move can be made larger by including the sixth portion14fand the seventh portion14gin the p+-type semiconductor region14. In particular, the current filament can move between the sixth portions14fby connecting the sixth portions14fto each other via the seventh portion14gprovided in the FWD region R2. Therefore, according to the variation, a possibility that the semiconductor device800is destroyed can be further decreased.

FIG. 22is a plan view showing a structure of a lower surface of a semiconductor device900according to an eighth variation of the embodiment.

The semiconductor device900is different from the semiconductor device800in that a plurality of seventh portions14gof the p+-type semiconductor region14is provided in the X-direction. In this manner, the number of seventh portions14gin the X-direction can be changed as appropriate. Also, the number of sixth portions14fin the Y-direction is not limited to the example shown inFIGS. 20 and 22, and can be changed as appropriate.

It is also possible to appropriately combine the structure of the p+-type semiconductor region14according to the sixth variation to the eighth variation with the structure of the IGBT region R1and the structure of the p+-type semiconductor region14according to the second variation to the fifth variation. By combining these, switching loss of the semiconductor device can be reduced.

The respective variations described above can be appropriately combined and carried out. For example, in the first variation to the eighth variation, as shown inFIG. 8, the p-type semiconductor region16may be provided around the p+-type collector region1and the p+-type semiconductor region14.

It is possible to confirm the relative levels of the impurity concentrations of the semiconductor regions in the embodiments described above, for example, using a SCM (scanning capacitance microscope). The carrier concentrations of the semiconductor regions may be considered to be equal to the activated impurity concentrations of the semiconductor regions. Accordingly, the relative levels of the carrier concentrations of the semiconductor regions can be confirmed using SCM. It is possible to measure the impurity concentrations of the semiconductor regions, for example, using a SIMS (secondary ion mass spectrometer).