A method of forming a semiconductor structure includes forming a first fin in a p-FET device region of a semiconductor substrate and a second fin in an n-FET device region of the semiconductor substrate substantially parallel to the first fin. The first fin and the second fin each comprise a strained semiconductor material. Next, the second fin is amorphized to form a relaxed fin by implanting ions into the second fin while protecting the first fin.

BACKGROUND

The present invention generally relates to semiconductor devices, and more particularly to field effect transistor (FET) devices including FinFET structures, and a method for making the same.

Complementary Metal-oxide-semiconductor (CMOS) technology is commonly used for fabricating field effect transistors (FETs) as part of advanced integrated circuits (IC), such as CPUs, memory, storage devices, and the like. At the core of a planar FET is a channel region formed in an n-doped or p-doped semiconductor substrate on which a gate structure is formed. Depending whether the on-state current is carried by electrons or holes, the FET can become an n-FET device or a p-FET device. The overall fabrication process may include forming a gate structure over a channel region connecting a source region and a drain region within the substrate on opposite sides of the gate, typically with some vertical overlap between the gate and the source and drain region.

As integrated circuits continue to scale downward in size, fin field effect transistors (FinFETs) or tri-gate structures are becoming more widely used, primarily because FinFETs can offer better performance than planar FETs at the same power budget. FinFETs are three dimensional (3-D), fully depleted metal-oxide semiconductor field effect transistor (MOSFET) devices having a fin structure formed from the semiconductor substrate material. The fins extend between the device source and drain enfolding the channel region forming the bulk of the semiconductor device. The gate structure is located over the fins covering the channel region. Such architecture may allow for a more precise control of the conducting channel by the gate, and may reduce the amount of current leakage when the device is in an off-state.

Existing CMOS high-k devices rely on n-FET and p-FET metals to allow near band-edge workfunctions. Such metals can shift the threshold voltage (Vt) of a gate stack towards either the n-FET or p-FET band-edge. The threshold voltage (Vt) may be defined as the value at which the n-FET or p-FET device starts to conduct current. One way to achieve this threshold voltage shift in n-FET devices is to use one of many potential n-FET metals. However, less p-FET metal options exist for band-edge workfunctions in p-FET devices. A possible solution includes making the device channel out of a semiconductor with a different band-gap, namely silicon-germanium (SiGe). A silicon-germanium channel may allow achieving near band-edge workfunctions with simpler metallurgical stacks. However, FinFET structures may pose challenges to the growth of a SiGe layer on the fin surface due to size dimensions and other constraints. Another potential solution may be to deposit a material on the silicon fin which can diffuse germanium into the fin and form a thermal SiGe layer on the fin. While these options may work in principle, they can be difficult to implement in practice. Additionally, another problem is that silicon-germanium does not work well for n-FET devices.

SUMMARY

Improved FinFET channel fabrication processes integrating SiGe channel technology may facilitate advancing the capabilities of current high-k device technology.

According to an embodiment of the present disclosure, a method of forming a semiconductor structure includes forming a first fin in a p-FET device region of a semiconductor substrate and a second fin in an n-FET device region of the semiconductor substrate substantially parallel to the first fin. The first fin and the second fin each include a strained semiconductor material. The second fin is amorphized to form a relaxed fin by implanting ions into the second fin while protecting the first fin.

According to another embodiment of the present disclosure, a method of forming a semiconductor structure includes: forming a silicon-germanium-on-insulator (SGOI) substrate including a base substrate, a buried oxide layer on the base substrate, and a silicon-germanium-on-insulator (SGOI) layer on the buried oxide layer. The SGOI layer is etched to form a first fin in a p-FET device region of the SGOI substrate and a second fin in an n-FET device region of the SGOI substrate. The second fin being substantially parallel to the first fin. The first fin in the p-FET device region is masked and ions are implanted into the second fin to relax the second fin. Then, the first fin in the p-FET device region is unmasked.

According to another embodiment of the present disclosure, a semiconductor structure includes: a first fin located in a p-FET device region of a semiconductor substrate, the first fin including a relaxed semiconductor material and a second fin located in an n-FET device region of the semiconductor substrate substantially parallel to the first fin, the second fin including a strained semiconductor material.

DETAILED DESCRIPTION

Exemplary embodiments now will be described more fully herein with reference to the accompanying drawings, in which exemplary embodiments are shown. This invention may, however, be modified in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessary obscuring the presented embodiments.

A method of forming a FinFET device having relaxed SiGe fins to optimized threshold voltage in an n-FET device region is described in detail below by referring to the accompanying drawings inFIGS. 1-10, in accordance with an illustrative embodiment of the present disclosure. More specifically, a method of forming a FinFET device on a silicon-germanium-on-insulator substrate that can allow for the functioning of n-FET devices by forming relaxed silicon-germanium fins is described in detail below by referring to the accompanying drawings inFIGS. 8-10. The method may provide a FinFET device having a silicon-germanium channel that can suit p-FET devices and n-FET devices equally. The method requires simpler metallurgical stacks than conventional FinFET fabrication where epitaxial silicon-germanium or carbon-doped silicon layers are grown over the fin surface in order to achieve the desire p-FET or n-FET workfunctions.

Referring toFIG. 1a silicon-germanium (SiGe)-on-insulator (SGOI) substrate100is shown. The SGOI substrate100may include a base substrate106, a buried oxide (BOX) layer104formed on top of the base substrate106, and a SGOI layer or SiGe layer102formed on top of the BOX layer104. The BOX layer104isolates the SiGe layer102from the base substrate106.

The base substrate106may be made from any of several known semiconductor materials such as, for example, silicon, germanium, silicon-germanium alloy, silicon carbide, silicon-germanium carbide alloy, and compound (e.g. III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, and indium phosphide. In one embodiment of the present disclosure, the base substrate106includes silicon. Typically the base substrate106may be about several hundred microns thick. For example, the base substrate106may include a thickness ranging from about 0.5 μm to about 75 μm.

The BOX layer104may be formed from any of several dielectric materials. Non-limiting examples include, for example, oxides, nitrides and oxynitrides of silicon. The BOX layer104may also include oxides, nitrides and oxynitrides of elements other than silicon. In addition, the BOX layer104may include crystalline or non-crystalline dielectric material. Moreover, the BOX layer104may be formed using any of several methods. Non-limiting examples include ion implantation methods, thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods and physical vapor deposition methods. The BOX layer104may include a thickness ranging from about 5 nm to about 200 nm. In one embodiment, the BOX layer104may be about 25 nm thick.

The SiGe layer102may be formed using any of several methods known in the art. Non-limiting examples include SIMOX (Separation by IMplantation of OXygen), wafer bonding, and ELTRAN® (Epitaxial Layer TRANsfer). Typically, the SiGe layer102includes a thickness ranging from about 5 nm to about 100 nm. In one embodiment, the SiGe layer102may be about 15 nm thick.

Referring toFIGS. 2-7, the process of forming fins in the SGOI substrate100will be described. The fins may be formed by any method known in the art, such as for example: sidewall image transfer (SIT).

FIG. 2illustrates an intermediate step in the FinFET fabrication process. At this step, a mandrel layer108may be deposited on the SGOI substrate100. The mandrel layer108may be made from any of several known semiconductor materials such as, for example, polycrystalline silicon, silicon oxide, silicon nitride, and the like. The mandrel layer108may be deposited by any technique known in the art, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or plasma enhanced chemical vapor deposition (PECVD).

The mandrel layer108may preferably include a material that is different enough from the material of the sidewall spacers (described below) so that they may be selectively removed. The particular material chosen may partly depend upon the desired pattern to be formed and the materials selected in subsequent steps discussed below. In one embodiment, the mandrel layer108may be formed with a vertical thickness ranging from about 30 nm to about 150 nm.

Referring now toFIG. 3, the mandrel layer108(shown inFIG. 2) may be lithographically patterned to create mandrels110. The mandrels110can be formed by applying known patterning techniques involving exposing a photo-resist and transferring the exposed pattern of the photo-resist by etching the mandrel layer108(shown inFIG. 2). Next, a layer of dielectric material112(hereinafter “dielectric layer”) may be conformally deposited directly on top of the SiGe layer102and the mandrels110. In one embodiment, the dielectric layer112may include, for example, silicon nitride or silicon oxide. It should be noted that the dielectric layer112should include a material that allows the mandrels110to be selectively etched in order to avoid further erosion of sidewall spacers114(shown inFIG. 4) formed from the dielectric layer112.

The dielectric layer112may be deposited with a conformal deposition technique, using any known atomic layer deposition technique, molecular layer deposition techniques, or any other suitable deposition technique. In one embodiment, the dielectric layer112may have a conformal and uniform thickness ranging from about 5 nm to about 50 nm.

Referring toFIG. 4sidewall spacers114may be formed adjacent to the mandrels110by subjecting the dielectric layer112(FIG. 3) to a directional etching process such as a reactive-ion-etching technique. The directional etching process may remove a portion of the dielectric layer112(FIG. 3) from above the SiGe layer102and from the top of the mandrels110. A portion of the dielectric layer112may remain along opposite sidewalls of the mandrels110, forming the sidewall spacers114. Furthermore, the mandrels110and the sidewall spacers114should each include materials that would allow the mandrels110to be subsequently removed selective to the sidewall spacers114. Here, it should be noted that the sidewall spacers114depicted inFIG. 4are for illustration purposes and can have a different shape from those shown. The sidewall spacers114will subsequently define a fin pattern which ultimately may be transferred into the underlying SiGe layer102.

Referring toFIG. 5, the mandrels110have been removed selective to the sidewall spacers114. Removing the mandrels110should not compromise the integrity of the sidewall spacers114. In one embodiment, the mandrels110may be removed using a typical standard cleaning technique, including ammonium hydroxide and hydrogen peroxide, in which the sidewall spacers114may not be trimmed.

Referring now toFIG. 6, a fin pattern defined by the sidewall spacers114may be transferred into the SiGe layer102(shown inFIG. 5) to form strained SiGe fins116. In the present step, the sidewall spacers114may function as a mask, and may have high etch selectivity relative to the SiGe layer102. Next, the SiGe layer102may then be etched to a desired depth. The desired depth can depend on the ultimate function of the semiconductor device. A directional etching technique such as a reactive ion etching may be used to etch the SiGe layer102. In one embodiment, the SiGe layer102may be etched with a reactive ion etching technique using a chlorine or a bromine based etchant. Furthermore, the sidewall spacers114may be removed in subsequent steps using any suitable removal technique known in the art.

Referring now toFIG. 7, the sidewall spacers114shown inFIG. 6have been selectively removed by means of an etching technique, which can include any suitable wet or dry etching technique. Etching of the sidewall spacers114should not compromise the integrity of the strained SiGe fins116. It should be noted that any number of fins applicable for a specific FinFET design may be manufactured.

With continued reference toFIG. 7, the SGOI substrate100having strained silicon-germanium (SiGe) fins116may include a p-FET device region200and an n-FET device region300selected according to a determined FinFET design for the formation of p-FET devices and n-FET devices. The strained SiGe fins116may be formed in the p-FET device region200and n-FET device region300. In one embodiment of the present disclosure, the p-FET device region200may include the strained SiGe fins116required to form a p-FET device while the n-FET device region300may include the strained SiGe fins116required to form an n-FET device. It is understood that as few as one fin may be included in each region.

At this point of the fabrication process, the strained SiGe fins116located in the p-FET device region200may provide a strained SiGe channel to the p-FET device to be built in this region thus providing the appropriate p-FET workfunction. However, the strained SiGe fins116located in the n-FET device region300may not provide the required workfunction for the n-FET device to be built in this region. In order to decrease or relax the strain provided by the strained SiGe fins116in the n-FET device region, an ion implantation technique may be conducted in order to change the crystal lattice of the strained SiGe fins116to force the silicon-germanium workfunction to closely match the silicon workfunction typically used in n-FET device manufacturing (discussed below).

Referring now toFIG. 8, the p-FET device region200may be covered by a hardmask layer118in order to protect the strained SiGe fins116located within this area of the SGOI substrate100. The steps involved in masking the p-FET device region200are conventional and well known to those skilled in the art. In on embodiment of the present disclosure, the hardmask layer118may include silicon nitride and may have a thickness of approximately15nm.

Referring now toFIG. 9, an ion implantation technique may be performed on the uncovered n-FET device region300of the SGOI substrate100. The ion implantation technique, represented by arrows120, may be used to amorphize the strained SiGe fins116of the n-FET device region300. In an embodiment of the present disclosure, the ion implantation process may include the use of inert amorphizing species such as argon (Ar) or xenon (Xe). In another embodiment of the present disclosure, the ion implantation process may include the use of n-type dopants, such as phosphorus (P) or arsenic (As). The implantation of these atoms may relax the compressively strained SiGe fins116in the n-FET device region300.

According to an embodiment of the present disclosure, the concentration of inert amorphizing species namely argon (Ar) or xenon (Xe) to achieve substantial amorphization of the strained SiGe fins116in the n-FET device region300may range from about 1×1014ions/cm2to about 1×1015ions/cm2with a tilt angle ranging from about 0 degrees to about20degrees and an implantation energy ranging from about 0.5 keV to about 10 keV.

According to another embodiment of the present disclosure, the dopant concentration of phosphorous (P) to achieve substantial amorphization of the strained SiGe fins116in the n-FET device region300may range from about 1×1014ions/cm2to about 1×1015ions/cm2with a tilt angle ranging from about 0 degrees to about 20 degrees and an implantation energy ranging from about 0.5 keV to about 10 keV. Furthermore, the dopant concentration of arsenic (As) to achieve substantial amorphization of the strained SiGe fins116in the n-FET device region300may range from about 1×1014ions/cm2to about 9×1014ions/cm2with a tilt angle ranging from about 0 degrees to about 20 degrees and an implantation energy ranging from about 0.5 keV to about 10 keV.

The amorphization of the strained SiGe fins116may transform the orderly crystalline structure of the silicon-germanium forming the strained SiGe fins116into an amorphous or damaged crystalline structure having different lattice and strain characteristics from those in its original state. The ion implantation process may be conducted with the appropriate dopant concentration and depth so that the entire body of the strained SiGe fins116located in the n-FET device region300can be substantially amorphized.

After the ion implantation, the directional strain of the strained SiGe fins116located in the n-FET device region300may be more similar to that of silicon. The implant damage may cause the compressively strained SiGe fins116in the n-FET device region300to relax forming relaxed SiGe fins122. The relaxed SiGe fins122may now be tensely strained in the n-FET device region300which in turn may enhance electron mobility in the n-FET device.

In one embodiment of the present disclosure, some recrystallization may occur within the relaxed SiGe fins122during subsequent high thermal processes required in FinFET manufacturing such as for example high thermal annealing processes. However, the recrystallization may not occur to the original state since the crystalline structure of the strained SiGe fins116was substantially disrupted during the ion implantation process.

Referring now toFIG. 10, the hardmask layer118has been removed from the strained SiGe fins116in the p-FET device region200by a method known in the art, for example, a reactive ion etching (RIE) technique. The SGOI substrate100includes strained SiGe fins116located in the p-FET device region200and relaxed SiGe fins120located in the n-FET device region300. The strained SiGe fins116in the p-FET device region200may remain compressively strained, thus improving hole mobility in the p-FET device. The strained SiGe fins116and the relaxed SiGe fins120may provide the appropriate workfunctions to the p-FET and n-FET devices respectively, in order to optimize voltage threshold and in turn carrier mobility and device performance.

After formation of the relaxed SiGe fins122, the manufacturing process can continue following typical steps of FinFET device fabrication. Including forming a high-k metal gate using a gate first or a gate last process and the subsequent formation of device contacts.

The steps described above may provide a method for forming FinFET devices having a SiGe channel that may allow for the band-edge threshold voltage required for p-FET devices as well as n-FET devices, using a single material with differing strain characteristics. FinFET devices having a SiGe channel may achieve near band-edge workfunctions with simpler metallurgical stacks than FinFET devices fabricated using traditional straining techniques where epitaxial silicon-germanium or carbon-doped silicon layers may be grown over the surface of silicon fins in order to achieve the desire p-FET or n-FET workfunction. The steps described above may also provide a method for forming FinFET devices that may have enhanced carrier mobility and device performance while decreasing the amount of steps required for achieving the appropriate device workfunction.