Method for forming a floating gate in a recess of a shallow trench isolation (STI) region

A method includes forming a shallow trench isolation (STI) region in a substrate, the STI region comprising an etch stop layer; etching the STI region by a first etch to the etch stop layer to form a recess in the STI region; and forming a floating gate, the floating gate comprising a portion that extends into the recess in the STI region, wherein the etch stop layer separates the portion of the floating gate that extends into the recess in the STI region from the substrate.

BACKGROUND

This disclosure relates generally to the field of computer memory, and more particular to a non-volatile memory (NVM) device formed with an etch stop layer in the shallow trench isolation (STI) regions.

NVM devices are used in various types of computer memory, for example, flash devices. An NVM device includes a floating gate separated from a control gate by a gate dielectric layer. A major concern in NVM devices is the gate coupling factor. A high gate coupling factor results in good control of the floating gate by the control gate during device operation and increases NVM device performance. The gate coupling factor of a NVM device is dependent on both the capacitance between the control gate and the floating gate, and the capacitance between the floating gate and the substrate. For an increase of 1 volt (V) of the control gate potential, the floating gate potential increases by a factor αCG, which is a factor related to the coupling factor between the floating gate and the control gate. αCGneeds to be relatively low to ensure good control of the floating gate by the control gate during device operation. However, capacitance that exists between the floating gate and the device substrate may act to raise αCG. Therefore, in order to raise the gate coupling factor of a NVM device, the capacitance between the control gate and the floating gate needs to be raised and/or the capacitance between the substrate and the floating gate needs to be lowered.

One way to increase the capacitance between the floating gate and the control gate is to decrease the equivalent oxide thickness (EOT) of the gate dielectric located between the floating gate and control gate. However, if the gate dielectric is made too thin, a tunneling current between the floating gate and control gate may arise, leading to the loss of data that is stored in the NVM device. Various floating gate shapes that are used in NVM devices to increase the capacitance between the floating gate and the control gate may also have the effect of increasing the capacitance between the floating gate and the substrate, which results in a relatively low net increase in the gate coupling factor of the device, and hence low increase in NVM device performance.

SUMMARY

In one aspect, a method includes forming a shallow trench isolation (STI) region in a substrate, the STI region comprising an etch stop layer; etching the STI region by a first etch to the etch stop layer to form a recess in the STI region; and forming a floating gate, the floating gate comprising a portion that extends into the recess in the STI region, wherein the etch stop layer separates the portion of the floating gate that extends into the recess in the STI region from the substrate.

In another aspect, a device includes a substrate; a shallow trench isolation (STI) region located in the substrate, the STI region comprising an etch stop layer, and further comprising a recess in the STI region, the recess having a bottom and sides, wherein the sides of the recess are defined by the etch stop layer; and a floating gate, wherein a portion of the floating gate is located on a side of the recess in the STI region and is separated from the substrate by the etch stop layer.

Additional features are realized through the techniques of the present exemplary embodiment. Other embodiments are described in detail herein and are considered a part of what is claimed. For a better understanding of the features of the exemplary embodiment, refer to the description and to the drawings.

DETAILED DESCRIPTION

Embodiments of a NVM device formed with an etch stop layer in a shallow trench isolation (STI) region, and a method of forming a NVM device with an etch stop layer in a STI region are provided, with exemplary embodiments being discussed below in detail. Inclusion of an etch stop layer in the STI region allows controlled etching of a recess in the STI region. The floating gate and the control gate of the NVM device are then formed such that they extend into the recess in the STI region, inducing a relatively high capacitance between the floating gate and the control gate. The floating gate may be separated from the substrate by the etch stop layer, so that the distance between the floating gate and substrate may be relatively high, resulting in a relatively low capacitance between the substrate and the floating gate. The overall coupling factor of the device may be thereby increased. The etch stop layer may be located on the both the sides and bottom of the STI trench in some embodiments, or may only be located on the sides of the STI trench in other embodiments. Inclusion of etch stop layers in the STI regions between NVM devices may also reduce variability in the gate coupling factor across a plurality of NVM devices.

FIG. 1shows a flowchart of a method100of forming a NVM device with an etch stop layer in a shallow trench isolation (STI) region. Two embodiments of the process flow ofFIG. 1are discussed in detail. In the first embodiment, the etch stop layer in the STI region may be formed such that the etch stop layer covers the sides and bottom of the STI trench; formation of a STI region including such an etch stop layer in the STI region is discussed with respect to method200A ofFIG. 2A, and the process flow of formation of a memory device according to the first embodiment is discussed with respect toFIGS. 3-15. In the second embodiment, the etch stop layer in the STI region may be formed such that the etch stop layer only covers the sides of the STI trench; formation of a STI region including such an etch stop layer in the STI region is discussed with respect to method200B ofFIG. 2B, and the process flow of formation of a memory device according to the first embodiment is discussed with respect toFIGS. 3-8 and 16-23.

Turning to the first embodiment of the process flow of method100ofFIG. 1, first, in block101ofFIG. 1, STI regions comprising an etch stop layer may be formed in a wafer comprising a silicon substrate. A flowchart of a method200A of formation of the STI regions according to the first embodiment is shown inFIG. 2A. Referring toFIG. 2A, in block201A, first, a padox layer, which comprises a uniform, relatively thin layer of oxide, may be formed on a top surface of a silicon substrate.FIG. 3shows an embodiment of a device300including a silicon substrate301after formation of a padox layer302on the top surface of the silicon substrate. Then, returning toFIG. 2A, flow proceeds to block202A, in which a nitride layer may be formed over the padox layer.FIG. 4shows the device300ofFIG. 3after formation of a nitride401over the padox layer302.

Next, returning to method200A ofFIG. 2A, in block203A the nitride and the padox are etched to form a mask for etching of an STI trench. The padox acts as an etch stop for the nitride during patterning of the nitride; the padox may then be subsequently patterned.FIG. 5shows the device400ofFIG. 4after etching the nitride401and the padox layer302. Then, proceeding to block204A of method200A ofFIG. 2A, the STI trench may be etched in the silicon substrate.FIG. 6shows the device500ofFIG. 5after etching of an STI trench601in the silicon substrate301. After etching of the STI trench, flow of method200A ofFIG. 2Aproceeds to block205A, in which an STI liner may be formed in the STI trenches. The STI liner may comprise oxide, and may be formed by any appropriate method.FIG. 7shows the device600ofFIG. 6after formation of an STI liner701on the bottom and sides of the STI trench601.

Flow of method200A ofFIG. 2Athen proceeds to block206A, in which the etch stop layer may be deposited over the STI liner in the STI trench. The etch stop layer may comprise nitride.FIG. 8shows an embodiment of the device700ofFIG. 6after deposition of the etch stop layer801over the STI liner701. The etch stop layer covers the bottom and sides of the STI trench601. The thickness of the etch stop layer determines the distance between the floating gate (discussed below with respect to block104) and the substrate; therefore the deposition of the etch stop layer may be controlled to produce an etch stop layer having a desired thickness to improve the operation of the finished NVM device. Method200A ofFIG. 2Athen proceeds to block207A, in which an STI oxide fill may be deposited over the device, filling STI trench over the etch stop layer.FIG. 9shows the device800ofFIG. 8after deposition of the oxide fill901over the device800; the oxide fill901fills the STI trench601and covers the etch stop layer801. Lastly, in block208A ofFIG. 2A, the top of the STI oxide fill may be polished down to expose the top surface of the etch stop layer, the excess etch stop and nitride on top of the substrate are removed by etching, the padox may be removed by etching so as to expose the top surface of the silicon substrate, and the top of oxide fill may be further removed to the level of the top surface of the silicon substrate. The excess oxide fill may be removed by chemical mechanical polishing (CMP) in some embodiments.FIG. 10shows the device900ofFIG. 9after removal of the excess portion of oxide fill901, the excess portion of the etch stop layer801, nitride401, and padox layer302to expose the top surface of silicon substrate301. Device1000ofFIG. 10comprises a silicon substrate301with STI regions including STI liner701, etch stop layer801over the STI liner701, and STI oxide fill1001.

Returning to method100ofFIG. 1, after formation of STI regions including an etch stop layer on the sides and bottom of the STI trench according to the method200A outlined inFIG. 2Ain block101ofFIG. 1, flow proceeds to block102, in which the oxide fill in the STI regions may be etched to form a recess. In the first embodiment of the process flow ofFIG. 1, the oxide fill may be etched down to the etch stop layer on the sides and the bottom of the STI trench. The etch of the oxide fill may comprise a hydrofluoric (HF) etch in some embodiments.FIG. 11shows the device1000ofFIG. 10after etching the oxide fill1001down to etch stop layer801to form recess1101.

Flow of method100ofFIG. 1then proceeds to block103, in which well implantation and tunnel oxide growth may be performed. The well implantation forms active regions in the silicon substrate near the top surface of the substrate. In some embodiments, the well implantation may be performed before etching of the STI oxide fill may be performed in block102ofFIG. 1. After well implantation, tunnel oxide may be grown over the implanted well regions of the substrate. The well region implantation and the tunnel oxide growth may be performed by any appropriate method. For example, the tunnel oxide may be grown by chemical vapor deposition (CVD) or in-situ steam generation (ISSG) in various embodiments. The tunnel oxide may comprise a high k dielectric such as hafnium oxide (HfO2), hafnium silicate (HfSiO2) nitrided hafnium silicate (HfSiON), silicon oxinitride (SiOxNy), silicon nitride (Si3N4) or aluminum oxide (Al2O3) in some embodiments. In some embodiments, the order of blocks102and103in method100ofFIG. 1may be reversed, and the etch of the oxide fill that is performed in block102may be performed after the well implantation and tunnel oxide growth of block103.FIG. 12shows the device1100ofFIG. 11after implantation of well regions1202in the silicon substrate301, and after growth of tunnel oxide1201over the well regions1202.

Turning again to method100ofFIG. 1, in block104, the floating gates may be formed by deposition and patterning of a floating gate material, which may comprise polysilicon or a metal such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), and tantalum nitride (TaN), or may comprise multiple layers, such as a polysilicon layer on top of one or more metal layers. The floating gates may be deposited by conformal deposition, and are formed such that a portion of the floating gates may be located on the etch stop layer in the STI recess that was formed by removal of the oxide fill from the STI regions. In various embodiments, the sides of the floating gates may be vertical, or in other embodiments the sides of the floating gates may be sloped. In embodiments in which the sides of the floating gates are sloped, the etch chemistry of the etch that is used to pattern a polysilicon floating gate may be CHxFy+O2, and the angle of the slope may be about 10 degrees. In other embodiments, the etch chemistry used to pattern a polysilicon floating gate may be HBr+O or HCl+O. Floating gates with sloped sides may help to prevent formation of voids during deposition of the control gate (discussed below with respect to block106andFIG. 15). Additionally, in some embodiments, the sides of the floating gate regions may be implanted with dopants after deposition. The implantation may comprise tilted implantation in some embodiments.FIGS. 13A-Bshow the device1200ofFIG. 12after formation of floating gates1301A,1302A,1301B, and1302B. Floating gates1301A and1302A as shown inFIG. 13Ahave vertical sides extending into recess1101, and floating gates1301B and1302bas shown inFIG. 13Bhas sloped sides extending into recess1101. The depth and shape of the floating gates1301A,1302A,1301B, and1302B may be dependent on the etch chemistry used to pattern the floating gate material after it is deposited; a floating gate such as floating gates1301A,1302A,1301B, and1302B may have any appropriate depth and shape in various embodiments. Additionally, whileFIGS. 14-15, which illustrate further processing steps of method100ofFIG. 1, are shown with respect to an example device1300A including floating gates1301A and1302A with vertical sides, the same processing steps may be applied to the device1300B including floating gates1301B and1302B with sloped sides to form a memory device in various embodiments. A NVM that includes floating gates such as floating gates1301A-B having sloped sides may help to prevent void formation during deposition of the control gate. Each of floating gates1301A,1302A,1301B, and1302B comprise a portion that is located in the STI recess1101on the etch stop layer801, which separates the floating gates1301A,1302A,1301B, and1302B from the substrate301, lowering the capacitance between the floating gates1301A,1302A,1301B, and1302B and the substrate301.

Returning to method100ofFIG. 1, in block105, a gate dielectric layer may be deposited over the device, covering the floating gates and the etch stop layer located at the bottom of the recess. The gate dielectric layer may be formed by conformal deposition, and may include one or more layers of oxide and/or nitride. The gate dielectric layer may comprise a high k dielectric such as HfO2, HfSiO2, HfSiON, SiOxNyor Al2O3in some embodiments. Additionally, in some embodiments, the gate dielectric layer may include an oxide-nitride-oxide (ONO) dielectric layer.FIG. 14shows the device1300A ofFIG. 13Aafter formation of the gate dielectric layer1401over the floating gates1301A and1302A and the portion of the etch stop layer801that is located at the bottom of recess1101.

Lastly, the flow of method100ofFIG. 1proceeds to block106, in which the control gate may be formed over the gate dielectric layer. The control gate may comprise polysilicon or a metal such as TiN, TiAlN, or TaN, and may be deposited using any appropriate method of deposition. The control gate may be separated from the floating gates by the gate dielectric layer. Both the floating gates and the control gate extend into the recess in the STI region that is defined by the etch stop layer, and the floating gate may be separated from the substrate by the etch stop layer, thereby improving the gate coupling factor of the NVM device.FIG. 15shows the device1400after formation of a control gate1501to form a NVM device1500. As shown inFIG. 15, both the control gate1501and the floating gates1301A and1302A extend into the recess defined by etch stop layer801. The etch stop layer801also separates the substrate301and the floating gates (for example, portion1502of floating gate1301A).

The second embodiment of the process flow of method100ofFIG. 1, in which the etch stop layer may be located only on the sides of the STI trench, is now discussed with respect toFIG. 2B,FIGS. 3-8, and 16-23. First, in block101ofFIG. 1, STI regions comprising an etch stop layer may be formed in a wafer comprising a silicon substrate. A flowchart of a method200B of formation of the STI regions according to the second embodiment is shown inFIG. 2B. Referring toFIG. 2B, in block201B, first, a padox layer, which comprises uniform, relatively thin layer of oxide, may be formed on a top surface of a silicon substrate.FIG. 3shows an embodiment of a device300including a silicon substrate301after formation of a padox layer302on the top surface of the silicon substrate. Then, returning toFIG. 2B, flow proceeds to block202B, in which a nitride layer may be formed over the padox layer.FIG. 4shows the device300ofFIG. 3after formation of a nitride401over the padox layer302.

Next, returning to method200B ofFIG. 2B, in block203B the nitride and the padox may be etched to form a mask for etching of an STI trench. The padox acts as an etch stop for the nitride during patterning of the nitride; the padox may then be subsequently patterned.FIG. 5shows the device400ofFIG. 4after etching the nitride401and the padox layer302. Then, proceeding to block204B of method200B ofFIG. 2B, the STI trench may be etched in the silicon substrate.FIG. 6shows the device500ofFIG. 5after etching of an STI trench601in the silicon substrate301. After etching of the STI trench, flow of method200B ofFIG. 2Bproceeds to block205B, in which an STI liner may be formed in the STI trenches. The STI liner may comprise oxide, and may be formed by any appropriate method.FIG. 7shows the device600ofFIG. 6after formation of an STI liner701on the bottom and sides of the STI trench601.

Flow of method200B ofFIG. 2Bthen proceeds to block206B, in which the etch stop layer may be deposited over the STI liner in the STI trench. The etch stop layer may comprise nitride.FIG. 8shows an embodiment of the device700ofFIG. 6after deposition of the etch stop layer801over the STI liner701. The etch stop layer covers the bottom and sides of the STI trench601. The thickness of the etch stop layer determines the distance between the floating gate (discussed below with respect to block104) and the substrate; therefore the deposition of the etch stop layer may be controlled to produce an etch stop layer having a desired thickness to improve the operation of the finished NVM device. Then, in block207B of method200B ofFIG. 2B, a portion of the etch stop layer located at the bottom of the STI trench may be removed. Removal of the portion of the etch stop layer located at the bottom of the STI trench may be performed using an anisotropic nitride etch or a CHxFy+O2etch.FIG. 16shows the device800ofFIG. 8after removal of the portion of the etch stop layer801located at the bottom of the STI trench601, exposing the bottom1601of the STI trench601.

Method200B ofFIG. 2Bthen proceeds to block208B, in which an STI oxide fill may be deposited over the device, filling STI trench over the etch stop layer.FIG. 17shows the device1600ofFIG. 16after deposition of the oxide fill1701over the device1600; the oxide fill1701fills the STI trench601and covers the etch stop layer801. Lastly, in block209B ofFIG. 2B, the top of the STI oxide fill may be polished down to expose the top surface of the etch stop layer, the excess etch stop and nitride on top of the substrate may be removed by etching, the padox may be removed by etching so as to expose the top surface of the silicon substrate, and the top of oxide fill may be further removed to the level of the top surface of the silicon substrate. The excess oxide fill may be removed by chemical mechanical polishing (CMP) in some embodiments.FIG. 18shows the device1700ofFIG. 17after removal of the excess portion of oxide fill1701, the excess portion of the etch stop layer801, nitride401, and padox layer302to expose the top surface of silicon substrate301. Device1800ofFIG. 18comprises a silicon substrate301with STI regions including STI liner701, etch stop layer801over the STI liner701, and STI oxide fill1801.

Returning to method100ofFIG. 1, after formation of STI regions including an etch stop layer on the sides of the STI trench according to the method200B outlined inFIG. 2Bin block101ofFIG. 1, flow proceeds to block102, in which the oxide fill in the STI regions may be etched to form a recess. In the second embodiment of the process flow ofFIG. 1, the oxide fill may be partially etched, such that the etch stop layer controls the location of the sides of the recess, while a portion of the oxide fill remains at the bottom of the STI trench. The etch of the oxide fill may comprise a hydrofluoric (HF) etch in some embodiments.FIG. 19shows the device1800ofFIG. 18after etching the oxide fill1801to etch stop layer801on the sides of the STI trench to form recess1902, leaving oxide fill1901at the bottom of the STI trench.

Flow of method100ofFIG. 1then proceeds to block103, in which well implantation and tunnel oxide growth are performed. The well implantation forms active regions in the silicon substrate near the top surface of the substrate. In some embodiments, the well implantation may be performed before etching of the STI oxide fill is performed in block102ofFIG. 1. After well implantation, tunnel oxide may be grown over the implanted well regions of the substrate. The well region implantation and the tunnel oxide growth may be performed by any appropriate method. For example, the tunnel oxide may be grown by chemical vapor deposition (CVD) or in-situ steam generation (ISSG) in various embodiments. The tunnel oxide may comprise a high k dielectric such as HfO2, HfSiO2, HfSiON, SiOxNyor Al2O3in some embodiments. In some embodiments, the order of blocks102and103in method100ofFIG. 1may be reversed, and the etch of the oxide fill that is performed in block102may be performed after the well implantation and tunnel oxide growth of block103.FIG. 20shows the device1900ofFIG. 19after implantation of well regions2002in the silicon substrate301, and after growth of tunnel oxide2001over the well regions2002.

Turning again to method100ofFIG. 1, in block104, the floating gates are formed by deposition and patterning of a floating gate material, which may be polysilicon or a metal such as TiN, TiAlN, or TaN. The floating gates may be deposited by conformal deposition, and formed such that a portion of the floating gate located on the etch stop layer in the STI recess that was formed by removal of the oxide fill from the STI regions. In various embodiments, the sides of the floating gates may be vertical, or in other embodiments the sides of the floating gates may be sloped. In embodiments in which the sides of the floating gates are sloped, the etch chemistry of the etch that is used to pattern a polysilicon floating gate may be CHxFy+O2, and the angle of the slope may be about 10 degrees. In other embodiments, the etch chemistry used to pattern a polysilicon floating gate may be HBr+O or HCl+O. Floating gates with sloped sides may help to prevent formation of voids during deposition of the control gate (discussed below with respect to block106andFIG. 23). Additionally, in some embodiments, the sides of the floating gate regions may be implanted with dopants after deposition. The implantation may comprise tilted implantation in some embodiments.FIGS. 21A-Bshow the device2000ofFIG. 20after formation of floating gates2101A,2102A,2101B, and2102B. Floating gates2101A and2102A as shown inFIG. 21Ahave vertical sides extending into recess1902, and floating gates2101B and2102bas shown inFIG. 21Bhas sloped sides extending into recess1902. The depth and shape of the floating gates2101A,2102A,2101B, and2102B may be dependent on the etch chemistry used to pattern the floating gate material after it is deposited; a floating gate such as floating gates2101A,2102A,2101B, and2102B may have any appropriate depth and shape in various embodiments. Additionally, whileFIGS. 22-23, which illustrate further processing steps of method100ofFIG. 1, are shown with respect to an example device2100A including floating gates2101A and2102A with vertical sides, the same processing steps may be applied to the device2100B including floating gates2101B and2102B with sloped sides to form a memory device in various embodiments. A NVM that includes floating gates such as floating gates2101A-B having sloped sides may help to prevent void formation during deposition of the control gate. Each of floating gates2101A,2102A,2101B, and2102B comprise a portion that may be located in the STI recess1902on the etch stop layer801, which separates the floating gates2101A,2102A,2101B, and2102B from the substrate301, lowering the capacitance between the floating gates2101A,2102A,2101B, and2102B and the substrate301.

Returning to method100ofFIG. 1, in block105, a gate dielectric layer may be deposited over the device, covering the floating gates and the etch stop layer located at the bottom of the recess. The gate dielectric layer may be formed by conformal deposition, and may include one or more layers of oxide and/or nitride. The gate dielectric layer may comprise a high k dielectric such as HfO2, HfSiO2, HfSiON, SiOxNyor Al2O3in some embodiments. Additionally, in some embodiments, the gate dielectric layer may include an oxide-nitride-oxide (ONO) dielectric layer.FIG. 22shows the device2100A ofFIG. 21Aafter formation of the gate dielectric layer2201over the floating gates2101A and2102A and remaining oxide fill1901located at the bottom of recess1902.

Lastly, the flow of method100ofFIG. 1proceeds to block106, in which the control gate may be formed over the gate dielectric layer. The control gate may comprise polysilicon or a metal such as TiN, TiAlN, or TaN, and may be deposited using any appropriate method of deposition. The control gate may be separated from the floating gates by the gate dielectric layer. Both the floating gates and the control gate extend into the recess in the STI region defined by the etch stop layer and the remaining oxide fill, and the floating gate may be separated from the substrate by the etch stop layer, thereby improving the gate coupling factor of the NVM device.FIG. 23shows the device2200after formation of a control gate2301to form a NVM device2300. As shown inFIG. 23, both the control gate2301and the floating gates2101A and2102A extend into the recess defined by etch stop layer801and the remaining oxide fill1901. The etch stop layer801also separates the substrate301and the floating gates (for example, portion2302of floating gate2101A).

The technical effects and benefits of exemplary embodiments include formation of an NVM memory device having an improved gate coupling factor and therefore improved performance.