Polarization defined zero misalignment vias for semiconductor packaging

Techniques that can assist with fabricating a semiconductor package that includes a zero misalignment-via (ZMV) and/or a trace formed using a polarization process are described. The disclosed techniques can result in creation of ZMVs and/or traces between the ZMVs using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.). One embodiment of a technique includes modulating an intensity of light applied to one or more resist layers by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. One embodiment of another technique includes creating patterns on one or more resist layers with different types of polarized light formed from a photomask and at least one polarizer. The disclosed techniques can assist with reducing manufacturing costs, reducing development time, and increasing I/O density.

FIELD

Embodiments generally relate to semiconductor packages. More specifically, embodiments relate to techniques of fabricating a semiconductor package having at least one zero misalignment vertical interconnect access (ZMV) fabricated using a polarization process.

BACKGROUND INFORMATION

One of the main drivers for package design rules is the input/output (I/O) density per mm per layer (IO/mm/layer). The I/O density may be limited by the via pad sizes. However, current packaging technologies limit the extent to which the size of the via pads may be reduced.

Traditionally organic substrate manufacturing is performed utilizing semi-additive processing (SAP), with interconnections between layers made by laser drilling processes. Such interconnections include at least one vertical interconnect access (via) that includes a pad. Currently, via pads need to be relatively large due to the laser drilling processes used to create via openings through a dielectric layer above the via pads. Laser drilling is limited by the minimum feature size and the misalignment of the laser when drilling via openings. Some lasers, such as ultraviolet (UV) lasers, can reduce the via opening more than other types of lasers, but throughput is also greatly decreased.

As explained above, current laser drilling processes may result in creation of an alignment margin that causes a pad beneath a via to be larger than an opening of the via (via opening). This relatively large pad (when compared to the via opening) may limit the I/O density of a device, which may exacerbate difficulties associated with achieving I/O densities that are equal to or greater than 50 IO/mm/layer.

One alternative to the laser drilling processes described above is a process of fabricating a zero misalignment via (ZMV). The process of creating a ZMV (ZMV process) can be used to fabricate vias and pads that can increase I/O densities (when compared to the I/O densities achieved by laser drilling processes). The ZMV process method utilizes a photoresist layer with sensitivity to two different light wavelengths, two different light intensities, two different gray-scale masks, or a combination thereof. In this way, the photoresist layer can be differentially patterned in conjunction with a dose sensitive resist layer. This allows the vias and traces to be plated in a two-step process without removal of the photoresist layer. Consequently, the ZMV process can assist with avoiding any alignment impact on these layers. In the ZMV process, the line width and line spacing—that is, the pitch—is limited by the resolution of the exposure tool and the resist capability. Another approach of the ZMV process includes use of a dual color—i.e., a dual-tone resist that is sensitive to two distinct wavelengths. There are, however, some drawbacks to these approaches. Resist materials, such as liquid resists, are used for a ZMV process that uses a dual-tone resist. In addition, utilizing the previously discussed methods results in a via shape that is not well defined in the direction along the trace and this may have an effect on via's reliability.

DETAILED DESCRIPTION

Embodiments described herein provide techniques of fabricating a semiconductor package having at least one zero misalignment vertical interconnect access (ZMV) fabricated using a polarization process. That is, ZMVs and corresponding traces between the ZMVs are created using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.).

In one embodiment, which may be referred to herein as a “polarization intensity modulation technique,” an intensity of light incident on one or more resist layers is modulated by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. In another embodiment, which may be referred to herein as a “different polarization technique,” patterns are created on one or more resist layers with different types of polarized light that is formed from un-polarized, mixed polarization, and/or randomly polarized light using from a photomask and at least one polarizer. For example, a first pattern is formed on one or more resist layers from a first type of polarized light that is processed by a photomask and at least one polarizer, while a second pattern is formed on the one or more resist layers from a second type of polarized light that is processed by a photomask and at least one polarizer. For this example, the first type of polarized light is parallel to an incident surface of the one or more resist layers and the second type of polarized light is perpendicular to the incident surface of the one or more resist layers. Also, and for this example, the different types of polarized light may be incident on the one or more resist layers (e.g., an anisotropic photoresist layer, etc.), which would cause the one or more resist layers to respond differently depending on the incident polarization.

In specific embodiments, each of the techniques described above (e.g., the polarization intensity modulation technique, the different polarization technique, etc.) result in creation of two patterns on the one or more resist layers (e.g., a photoresist layer, etc.). Following exposure operations performed on the one or more resist layers (e.g., a photoresist layer, etc.), a first pattern of the two patterns is developed and then a first layer formed from a conductive material (e.g., copper (Cu), etc.) is deposited. This first layer will eventually form a ZMV. Next, a second pattern of the two patterns is developed and plated to form the ZMV and a trace. The two patterns are formed with a photomask and, as a result, no pads are formed in a semiconductor package formed using the embodiments described herein. As explained above, the photomask receives light that passes through at least one polarizer.

Numerous advantages result from embodiments of the techniques described herein. These advantages provide benefits over some currently available techniques for fabricating ZMVs and traces. Examples of these currently available techniques include, but are not limited to, using a dose selective dual development approach with an intensity modulating mask and using a dual-tone/wavelength approach with a color/wavelength selective mask.

One advantage is that embodiments of the polarization techniques described herein includes using polarized light to increase the width of the ZMV process window, which in turn, can assist with improving a high degree of repeatability (i.e., yield). In a currently available technique that involves use of a dual dose mask, the mask has a different transparency of light for vias and traces, which in turn leads to differential dosing of the one or more resist layers. This currently available technique, however, has a drawback because the doses of light passing through the dual dose mask cannot be changed after the mask has been created. As a result of this drawback, the currently available techniques that involve use of a dual dose mask limits flexibility in the manufacturing process. This is because any inadvertent changes in the intensity of the light source can lead to unwanted changes in the structures (e.g., ZMVs, traces, etc.) being manufactured. Embodiments of the polarization techniques described herein can assist with minimizing or eliminating the limitation associated with the dual dose mask. For example, an embodiment of the polarization intensity modulation technique includes use of an adjustable polarizer (e.g., a circular polarizer, a linear polarizer, a combination thereof, etc.) that is placed between the light source and a photomask, as described in further detail below. This adjustable polarizer can, in some embodiments, assist with monitoring and modulating an intensity of light passed through the photomask during the manufacturing process, which can in turn assist with providing increased flexibility and control over the manufacturing process. This increased flexibility and control can in turn assist with improving both the quality of the two patterns and the amount of yield. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a semiconductor package, and with increasing the I/O density in a semiconductor package.

Embodiments of the polarization techniques described herein can also assist with overcoming one or more limitations associated with dual wavelength lithography. Specifically, dual wavelength lithography includes using a dual wavelength absorbing resist together with an exposure tool that can filter and/or enable different wavelengths. Using a dual wavelength absorbing resist together with an exposure tool can complicate photoresist and lithography tool development. In contrast, embodiments of the polarization techniques described herein include use of a photomask, at least one polarizer, and one or more resist layers that can be readily integrated into existing exposure tools without changing the lens configuration or light source. Additionally, embodiments of the polarization techniques described herein include use of one or more polarization-selective photoresist layers, which can assist enabling improved contrast over currently available techniques that include use of dual patterning techniques. Embodiments of the polarization-selective photoresist layers described herein can be created by incorporation of dichroic photoinitiator materials that allow polarized light to participate polymerization. Embodiments of the resist layers described herein can assist with enhancing the patterning resolution when propagation of the polarized light has a predetermined directional alignment, a predetermined critical dimension, and a high numerical aperture (NA) to capture higher diffraction orders.

In addition, illumination areas that can be achieved with embodiments of the polarization techniques described herein (e.g., the different polarization technique, etc.) provide an advantage over some currently available techniques. This is because as the illumination areas achieved with embodiments of the polarization techniques described herein can be larger than those achieved by currently available techniques, which can in turn assist with improving can assist with reducing manufacturing costs and reducing development time of fabricating a semiconductor package, and with increasing the I/O density in a semiconductor package.

FIGS. 1A-1Fare cross-sectional side view illustrations of a method of forming a package layer100in a semiconductor package that includes at least one ZMV fabricated using a polarization process according to one embodiment. The polarization process shown inFIGS. 1A-1Fcan be one or more of: (i) a polarization intensity modulation technique, as described above; and (ii) a different polarization technique, as described above.

With regard now toFIG. 1A, where a method of forming a package layer100begins. As shown, the package layer100comprises a photoresist layer107on a seed layer109on a dielectric layer111. The dielectric layer111may reside on a substrate core (not shown). Persons having ordinary skill in the art will appreciate that the substrate core is not shown or described to avoid obscuring or convoluting embodiments of the inventive concepts described herein.

In one embodiment, the dielectric layer111may be formed, for example, from thermal or native growth of silicon dioxide on the surface of a crystalline silicon substrate and/or using a bumpless build-up layer (BBUL) process with a material such as, for example, a polymer. One example of a suitable material is a polymeric epoxy film known as Ajinomoto Build-up Film (ABF), available from Ajinomoto Fine-Techno Company, Inc. The dielectric layer111can be deposited using one or more suitable dielectric deposition techniques, e.g., electroless plating or any other dielectric layer deposition technique known to one of ordinary skill in the art of electronic device manufacturing.

In one embodiment, the seed layer109is a conductive seed layer. Examples of the conductive materials that may be used for the seed layer include, but are not limited to, metals, e.g., copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides, e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide, other conductive materials, or any combination thereof. In more specific embodiments, the seed layer109is a copper layer. The seed layer109can be deposited using one or more conductive layer deposition techniques, e.g., electroless plating, electroplating, sputtering, chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or any other conductive layer deposition technique known to one of ordinary skill in the art of electronic device manufacturing.

In one embodiment, the photoresist layer107is formed from a positive tone photoresist that is a dual-tone photoresist. For one example, the photoresist comprises a polymer, a photoactive agent, and a dissolution inhibitor. In a positive tone photoresist, the area exposed to the radiation or light will define the area where the photoresist will be removed. Generally, a dual-tone photoresist allows printing of two images in an exposure of a photomask (e.g., photomask105, etc.). In one embodiment, the photoresist layer107comprises materials that react differently to different light wavelengths, different light intensities, or both. In one embodiment, the photoresist layer107is a dual-tone, wavelength selective photoresist. In another embodiment, the photoresist layer107is a dual-tone, dose selective photoresist. In one embodiment, the photoresist layer107contains a bis-azide added to a positive-tone resist containing a diazoketone dissolution inhibitor. In another embodiment, the photoresist layer107comprises a positive photosensitizer, a negative photosensitizer, a polymeric matrix resin, or any combination thereof. In another embodiment, the photoresist layer107comprises a photo-acid and/or photo-base generator and a chemically amplified photoresist. In one embodiment, the photoresist layer107is deposited using a dry film process. In another embodiment, the photoresist layer107is deposited by application of a solution using for example, a spin-coating, a slit-coating, a spray-coating, or any other coating technique, or any other photoresist depositing techniques known to one of ordinary skill in the art of electronic device manufacturing. The photoresist layer107may be patterned to form metal features. Generally, a semi-additive metallization process involves forming a photoresist mask that defines the regions on the photoresist layer107where metal features are formed later on in a process.

As shown inFIG. 1, the photoresist layer107is exposed to a light101through an adjustable polarizer103and a photomask105to pattern at least two images at a time. In one embodiment, the light101comprises un-polarized light or light having mixed polarization. In one embodiment, the light101passes through the adjustable polarizer103before passing through the photomask105. The adjustable polarizer103filters the light101such that some of the light101having a particular spatial characteristic, frequency (wavelength), phase, and/or polarization state passes through the adjustable polarizer103to the photomask105, while the rest of the light101is prevented from passing through the adjustable polarizer103to the photomask105. In one embodiment, the adjustable polarizer103can comprise one or more linear polarizers, one or more circular polarizers, or a combination thereof. Furthermore, the adjustable polarizer103can be adjusted such that portions of the light101having a particular spatial characteristic, frequency (wavelength), phase, and/or polarization state may be filtered. For example, the adjustable polarizer103can be adjusted at a first time such that portions of the light101having a first particular spatial characteristic, frequency (wavelength), phase, and/or polarization state may pass through the polarizer103to the photomask105. Also, and for this example, the adjustable polarizer103can be adjusted at a second time (that differs from the first time) such that portions of the light101having a second particular spatial characteristic, frequency (wavelength), phase, and/or polarization state (that differs from the first particular spatial characteristic, frequency (wavelength), phase, and/or polarization state) may pass through the polarizer103to the photomask105.

In one embodiment, the polarized light101that passes through the adjustable polarizer103travels to the photomask105by way of a series of optical elements. In one embodiment, the image formed by passage of the polarized light101through the photomask105is projected onto the photoresist layer107by way of a series of optical elements. In one embodiment, the size of the projected field and the images thereon is reduced or magnified in size compared to the mask field. In one embodiment, the polarized light101is generated by a broadband light source (not shown). In yet another embodiment, the polarized light101is generated by a plurality of wavelength light sources. The photomask105comprises at least three regions, e.g., an open region119, a polarized region121, and two closed regions117.

In one embodiment, the polarized light101comprises multiple wavelengths in one or more wavelength ranges. In one embodiment, a polarization intensity modulation technique is used to pattern the photoresist layer107. Here, different portions of the photomask105transmit different doses of the polarized light101. In this embodiment, the photomask105comprises one or more grayscale masks, so that different regions of the photomask105transmit different doses of the polarized light101. These different regions of the photomask105allow multi-patterning of photoresist layer107due to varying amounts of intensity of the polarized light101. In one embodiment, the open region119transmits a fixed dose115(e.g., one or more first intensities or doses of the polarized light101), the polarized region121transmits a variable dose113(e.g., one or more second intensities or doses of the polarized light101), and the closed regions117are opaque to the polarized light101. In one embodiment, the open region119is transparent to the polarized light101, the closed regions117are opaque to the polarized light101, and the polarized region121is also transparent to the polarized light101.

In one embodiment, a different polarization technique is used to pattern the photoresist layer107. This technique includes utilizing different types of polarized light to pattern the photoresist layer105. In one embodiment, this technique uses linearly polarized light101, a photomask105with a polarized region121formed from a polarization filter, and a photoresist layer107formed from polarization-selective resist materials. In one embodiment, the linearly polarized light101comprises transversely polarized light and longitudinally polarized light. Transversely polarized light can be created by one or more linear polarizers, which are known so they are not described in detail herein. Generating longitudinally polarized light may include use of more or different optical components than the optical components used for generating transversely polarized light. Additional details about embodiments of the different polarization technique are provided below in connection withFIGS. 2A-2G.

The materials for the photomask105are selected based on the optical properties. In one embodiment, photomask105comprises fused silica, glass, chromium, a polymer, a multilayer dielectric interference filter, a spin-on glass of inorganic oxide, or any combination thereof.

As explained above, the photomask105includes a polarized region121. The polarized region121may comprise one or more linear polarizers, one or more circular polarizers, or a combination thereof. In one embodiment, the polarized region121is designed such that portions of the light101having a specified or fixed spatial characteristic, frequency (wavelength), phase, and/or polarization state may pass through the polarized region121.

In one embodiment, the polarized region121and the adjustable polarizer103are used in combination to control or vary an intensity of the light101transmitted through the photomask105based on a function of an incident polarization state. One benefit of varying an intensity of the light101based on a function of an incident polarization state is that the intensity of the light101that is transmitted onto the photoresist layer107may be finely tuned and adjusted in an improvised or extemporaneous manner (i.e., “on-the-fly”). In one embodiment, an intensity meter (not shown inFIG. 1A) monitors the intensity of the light101before and during the transmission onto the photoresist layer107. The monitored information may then be provided to the adjustable polarizer103, which would then compensate for intensity fluctuations. In this way, the photoresist layer107receives much lower dose fluctuations and, as a result, a much more accurate or tighter process window can be achieved (as opposed to the less accurate process windows associated with one or more currently available techniques of forming ZMVs and traces). In this way, the use of the adjustable polarizer103and the polarized region121can assist with reducing the development time and increasing the quality associated with fabrication of ZMVs and traces. Moreover, use of the adjustable polarizer103and the polarized region121can assist with increasing repeatability of the process by reducing fluctuations in doses of the light101.

Referring again toFIG. 1A, the light101passing through the photomask105results in creation of two patterns on the photoresist layer107. The first pattern is created using the full dose/intensity of the light101(i.e., 100% of the dose of the light101) in an area of the photoresist layer under the open region119of the photomask105. The second pattern is created using the less than the full dose/intensity of the light101(i.e., less than 100% of the dose of the light101) in an area of the photoresist layer under the polarized region121of the photomask105.

Referring now toFIG. 1B, which illustrates the package layer100after the photoresist layer107is exposed to the light101according to one embodiment. Following exposure to the light101through the photomask105and the adjustable polarizer103, the photoresist layer107undergoes chemical responses that vary according to the exposure in the various regions of the resist. As shown inFIG. 1B, after the exposure, at least three two dimensional (2D) regions in the photoresist layer107are created, e.g., two regions123, a region125, and a region127. In one embodiment, the region125represents a 2D image of a first feature (e.g., a via, or any other feature) to be formed on the dielectric layer111; the region127represents a 2D image of a second feature (e.g., a trace, or any other feature adjacent to the first feature) to be formed on the dielectric layer111. The region(s)123are used to protect portions of the seed layer109on the dielectric layer111from exposure. That is, at least two images of the features are created at the same time. Generally, the number of patterned regions, such as regions123,125and127, created is determined by the photoresist chemistry. In alternative embodiments, additional regions in addition to regions123,125and127are created to pattern more than two images at a time.

As shown inFIG. 1B, each of the created regions123,125and127has been exposed to different doses of the polarized light101. In a non-limiting example, region(s)123have not been exposed to the polarized light101; region125has been exposed to light having one intensity or dose (e.g., 100% of light101); and region127has been exposed to light having an intensity or dose different from the intensity or dose of the light to which region125has been exposed (e.g., less than 100% of light101). In one non-limiting example, a region125is a base-soluble portion of the photoresist layer107; regions123are unexposed portions of the photoresist layer107; and region127is a cross-linked portion of the photoresist layer107.

Referring now toFIG. 1C, which illustrates the package layer100after the region125of the photoresist layer107has been removed to uncover a top side of the seed layer109according to one embodiment. In one embodiment, region125is selectively removed by dissolution in an aqueous basic developer solution, while leaving regions123and127intact. In a specific embodiment, region125becomes soluble in an aqueous basic developer solution, while other regions (e.g., regions123and127) remain insoluble, either due to a presence of a dissolution inhibitor (e.g., region123, which is unexposed) or due to cross-linking (e.g., region127). In alternative embodiments, region125is selectively removed using other photoresist removal techniques known to one of ordinary skill in the art of electronic device manufacturing (e.g., a dry etch technique, etc.). In one embodiment, one or more features to be formed in the region125comprise a via-pad structure (also referred to herein as a ZMV). In one embodiment, the soluble region125is selectively removed to form one or more openings, e.g., an opening129, to expose one or more portions of the seed layer109, e.g., a portion131, while leaving regions123and127intact to form one or more ZMVs later on in the process. Opening129can have a circular, oval, elliptical, square, rectangular, or any other shape.

With regard now toFIG. 1D, which illustrates the package layer100after a first conductive layer133is deposited onto the uncovered top side of a portion131of the seed layer109according to one embodiment. In one embodiment, a first conductive layer133is a part of a via-pad structure. Examples of the conductive materials that may be used for the conductive layer include, but are not limited to, metals, e.g., copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide), other conductive materials, or any combination thereof. In more specific embodiment, the conductive layer133is a copper layer. In one embodiment, a thickness of the first conductive layer133is determined by both the height of the via and the thickness of a trace adjacent to the via. In one embodiment, a thickness of the first conductive layer133is smaller than the thickness of the photoresist layer107. In one embodiment, a thickness of the first conductive layer133corresponds to a difference between the height of the via and the thickness of the metal line adjacent to the via.

As shown inFIG. 1D, the conductive layer133is deposited while leaving portions123and127of the photoresist layer107intact. In one embodiment, the conductive layer133is deposited using one of electroplating techniques known to one of ordinary skill in the art of electronic device manufacturing. In more specific embodiment, conductive layer133is deposited by an electrolytic plating technique at conditions such that the electrolytic plating does not dissolve any of the remaining portions123and127of the photoresist layer107, e.g., a solution of copper (II) sulfate and sulfuric acid at room temperature, used for depositing copper. In alternative embodiments, the conductive layer133is deposited using one of conductive layer deposition techniques, e.g., electroless plating, electroplating, sputtering, chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or any other conductive layer deposition technique known to one of ordinary skill in the art of electronic device manufacturing.

Referring now toFIG. 1E, which illustrates the package layer100after a region127of the photoresist layer107is removed to uncover a portion137of the seed layer109according to one embodiment. In one embodiment, one or more features formed on the portion137of the seed layer109comprise a trace. As shown inFIG. 1E, the region127is selectively removed to form one or more open regions, such as open region135, to expose one or more portions, such as a portion137of the seed layer109while leaving regions123of the photoresist layer107and conductive layer133intact. As shown inFIG. 1E, the conductive layer133is bounded by a top surface and a sidewall surface. The sidewall surface of the conductive layer133is exposed by removal of the region127of the photoresist layer107. In one embodiment, region127is selectively removed by dissolution in an appropriate solvent that is not a solvent for other remaining regions123of the photoresist layer107. In one embodiment, the region127is removed directly after conductive layer133is deposited. In another embodiment, the region127is treated with an additional exposure, e.g., a flood exposure, heating, or contact with a chemical (which can include the chemicals used during electrolytic plating of the conductive layer127), to effect a change in the solubility and improve solubility selectivity. In a more specific embodiment, the treated region is removed by dissolution in an organic solvent or, in another embodiment, by dissolution by an aqueous base solution. In one embodiment, the additional treatment of the region127is performed before electrolytic plating of the conductive layer133. In another embodiment, the additional treatment of the region127is performed during electrolytic plating of the conductive layer133. In yet another embodiment, the additional treatment of the region127is performed after electrolytic plating of the conductive layer133. In alternative embodiments, region127is selectively removed using other photoresist removal techniques known to one of ordinary skill in the art of electronic device manufacturing. In one embodiment, the width of the openings135is determined by design, e.g., by the width of the trace formed later on in the process. In one embodiment, the length of the opening135is determined by design, e.g., by the length of the trace formed later on in a process.

With regard now toFIG. 1F, which illustrates the package layer100after a second conductive layer139is deposited onto the first conductive layer133and the exposed portion137of the seed layer109according to one embodiment. As shown inFIG. 1F, a second conductive layer139is deposited onto the portions137and simultaneously on top of a first conductive layer133. The second conductive layer139comprises three portions. A first portion of the second conductive layer139forms one or more traces. A second portion of the second conductive layer139is deposited directly on top of first conductive layer133. A third portion of the second conductive layer139forms a transition region between the first and second portions of the second conductive layer139. Examples of the conductive materials that may be used for the second conductive layer139include, but are not limited to, metals, e.g., copper, tungsten, tantalum, titanium, hafnium, zirconium, aluminum, silver, tin, lead, metal alloys, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, aluminum carbide), other conductive materials, or any combination thereof. In more specific embodiments, the second conductive layer139is a copper layer. In one embodiment, a thickness of the second conductive layer139is determined by the thickness of the trace and is approximately equal in the first and second portions of the second conductive layer139. In one specific embodiment, the second conductive layer139is deposited in an isotropic process. In an alternative embodiment, the second conductive layer139is deposited in an anisotropic process.

As shown inFIG. 1F, the second conductive layer139is deposited while leaving portions123of the photoresist layer107intact. In one embodiment, the second conductive layer139is deposited using one of electroplating techniques known to one of ordinary skill in the art of electronic device manufacturing. In a more specific embodiment, the second conductive layer139is deposited by an electrolytic plating technique at the conditions such that the remaining portions123of the photoresist layer107is not dissolved, e.g., by immersion into a solution of copper (II) sulfate and sulfuric acid at room temperature, used for depositing copper. In alternative embodiments, the second conductive layer139is deposited using one of conductive layer deposition techniques, e.g., electroless plating, electroplating, sputtering, chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or any other conductive layer deposition technique known to one of ordinary skill in the art of electronic device manufacturing.

InFIG. 1F, the first conductive layer133and the second portion of the second conductive layer139(as described above) collectively form a via-pad structure, such a ZMV with a pad. The lower portion of the via-pad structure, extending from the top of seed layer109up to the top of the first portion of the second conductive layer139forms a pad. The upper portion of the via-pad structure, extending from the top of the pad to the top of the second portion of the second conductive layer139, represents a via (e.g., a ZMV, etc.). In one embodiment, a height of the pad is less than or equal to a height of the via, in which case the pad and the via each comprise portions of the first conductive layer133and the second conductive layer139. In an alternative embodiment, the height of the pad is greater than the height of the via, in which case the pad comprises portions of the first conductive layer133and the second conductive layer139, while the via comprises the second conductive layer139only. In one embodiment, the first and second portions of the second conductive layer139are adjacent along only one direction, and the third, transition portion of the second conductive layer139extends only in one direction between the first and second portions of the second conductive layer139. In an alternative embodiment, the first and second portions of the second conductive layer139are adjacent along multiple directions, and the third, transition portion of the second conductive layer139extends in multiple directions between the first and second portions of the second conductive layer139.

In one embodiment, where the photoresist layer107comprises more than three patterned regions, the remaining patterned regions are developed and a conductive layer is deposited in a manner similar to the manner described with respect toFIGS. 1A-1F. Generally, deposition of the conductive layer is additive, so each successive conductive layer deposition operation adds to the height of all uncovered conductive structures.

With regard now toFIG. 1G, which illustrates the package layer100after regions123of the photoresist layer107and portions of the seed layer109are removed to uncover one or more portions of the dieletric layer111according to one embodiment. The regions123are removed to expose underlying portions of the seed layer109. Subsequently, the underlying portions of the seed layer109are removed to define a metal pattern. In one embodiment, the regions123of the photoresist layer107are removed by using one of a stripping solution, an ashing, an etching technique, or any other photoresist removal technique known to one of ordinary skill in the art of electronic device manufacturing. In one embodiment, the underlying portions of the seed layer109are removed using one of a wet etching, dry etching, or both dry and wet etching techniques known to one of ordinary skill in the art of electronic device manufacturing. As shown inFIG. 1G, the via-pad structure formed from the conductive layers133and139comprise a via portion141and a trace portion143. In one embodiment, dimensions of the via portion141are at least approximately similar in all directions other than the direction of trace portion143. In this way, a zero misalignment via (ZMV)141is advantageously achieved. As shown inFIG. 1G, the ZMV141does not effectively include a pad. This is because it is effectively eliminated, as the extent of the pad portion in all directions other than the direction of the trace143is reduced to the extent of the via portion141. In one embodiment, a width of the pad portion (not shownFIG. 1G) is at least approximately the same as the width of the via portion141and the width of the trace143. For one embodiment, a length of the trace143attached to the via141is at least approximately greater than the width of the pad. In one non-limiting example, forming ZMV structures141and the trace143assist with increasing the I/O density of 10 connections to about 250/mm/layer.

FIGS. 2A-2Gare cross-sectional side view illustrations of a method of forming a package layer400in a semiconductor package that includes at least one ZMV fabricated using a polarization process according to yet another embodiment. The polarization process shown inFIGS. 2A-2Gcan be similar to or the same as a different polarization technique, as described above.

With regard now toFIG. 2A, where a method of forming a package layer400begins. As shown, the package layer400comprises a photoresist layer407on a seed layer409, where the seed layer409is on a dielectric layer411. The dielectric layer411may reside on a substrate core (not shown). Persons having ordinary skill in the art will appreciate that the substrate core is not shown or described to avoid obscuring or convoluting embodiments of the inventive concepts described herein.

The dielectric layer411is similar to or the same as the dielectric layer111, so it is not described again for brevity. The seed layer409is similar to or the same as the seed layer109, so it is not described again for brevity.

In one embodiment, the photoresist layer407is similar to or the same as the photoresist layer107, so it is not described again for brevity. In a further embodiment, the photoresist layer407comprises a polarization-selective photoresist material. That is, the photoresist layer407is selectively sensitive to longitudinally polarized light and transversely polarized light. In a specific embodiment, the photoresist layer407is more sensitive to longitudinally polarized light than to transversely polarized light.

As shown inFIG. 2A, the photoresist layer407is exposed to a light401. In one embodiment, the light401passes through an adjustable linear polarizer311, a waveplate313, and a photomask405(comprising a circular wire grid polarizer and a high NA lens) to pattern at least two images at a time on the photoresist layer407. The adjustable linearly polarizer311processes light (e.g., randomly polarized, un-polarized light, etc.) to generate linearly polarized light. In one embodiment, this linear polarizer311may be part of the adjustable polarizer103or the polarized region121of the photomask105(which are both described above in connection withFIGS. 1A-1G).

FIG. 2Aalso includes processing of the linearly polarized light by a waveplate313(e.g., a half-wave plate, quarter-wave plate, a combination thereof, etc.) to generate circular polarized light. When the waveplate313includes a half-wave plate, the half-wave plate shifts the polarization direction of linearly polarized light. When the waveplate313includes a quarter-wave plate, it converts the linearly polarized light into circularly polarized light. The waveplate313can be formed from a birefringent material (e.g., quartz, mica, etc.) for which the index of refraction is different for different orientations of the linearly polarized light passing through it. The behavior of the waveplate313depends on the thickness of the crystal, the wavelength of the linearly polarized light, and the variation of the index of refraction. By appropriate choice of the relationship between these parameters, it is possible to introduce a controlled phase shift between the two polarization components of a light wave, thereby altering its polarization. In one embodiment, the controlled phase shift introduced by the waveplate313is π/2.

The photomask405may include a circular wire grid polarizer (WGP) and a high NA lens. The output of the wavelet313can be passed to the circular polarized light, which processes the received output to generate radially polarized light. The circular WGP comprises several fine parallel metallic wires that are placed in a plane that mostly reflect non-transmitted polarization and can thus be used as a polarizing beam splitter.

After generation of the radially polarized light, a high NA lens processes the radially polarized light that is output by the circular WGP to generate longitudinally polarized light. This light is parallel to the direction of light propagation.

In one embodiment, the light401comprises un-polarized light, mixed polarization light, or the randomly polarized light described above in connection with one or more ofFIGS. 1A-1G. In one embodiment, the adjustable linear polarizer311processes the light401to generate transversely polarized light413, as described above. This light413is then passed to the waveplate313, which processes the transversely polarized light413to generate circular polarized light, as described above. The circular polarized light may be passed to the photomask405, which processes the circular polarized light to generate longitudinally polarized light415, as described above. In one embodiment, each of the waveplate313and the photomask405includes a region419that allows the transversely polarized light413to reach the photoresist layer407and dose a portion of the photoresist layer407. In one embodiment, the photomask405also includes a region421comprising a circular wire grid polarizer and a high NA lens, as described above. The photomask405also includes closed regions417which are similar to or the same the closed regions117described above in connection withFIG. 1A, so they are not described again for brevity.

The adjustable linear polarizer311filters the light401such that some of the light401having a particular spatial characteristic, frequency (wavelength), phase, and/or polarization state passes through the adjustable linear polarizer311to the waveplate313and the photomask405, while the rest of the light401is prevented from passing through the adjustable linear polarizer311. In one embodiment, the adjustable linear polarizer311can comprise one or more linear polarizers. Furthermore, the adjustable linear polarizer311can be adjusted such that portions of the light401having a particular spatial characteristic, frequency (wavelength), phase, and/or polarization state may be filtered. For example, the adjustable linear polarizer311can be adjusted at a first time such that portions of the light401having a first particular spatial characteristic, frequency (wavelength), phase, and/or polarization state may pass through the polarizer311to the waveplate313and the photomask405. Also, and for this example, the adjustable linear polarizer311can be adjusted at a second time (that differs from the first time) such that portions of the light401having a second particular spatial characteristic, frequency (wavelength), phase, and/or polarization state (that differs from the first particular spatial characteristic, frequency (wavelength), phase, and/or polarization state) may pass through the polarizer311to the waveplate313and the photomask405.

In one embodiment, the polarized light401comprises multiple wavelengths in one or more wavelength ranges. In one embodiment, a different polarization technique is used to pattern the photoresist layer407. Here, different portions of the photomask405transmit doses of different types of polarized light to the photoresist layer401. The different types of polarized light include: (i) transversally polarized light413; and (ii) longitudinally polarized light415. In this embodiment, the photomask405comprises an open region419, a polarized region421(comprising a circular wire grid polarizer and a high NA lens), and closed regions417, so that different regions of the photomask405transmit different types of the polarized light401. These different regions of the photomask405allow multi-patterning of photoresist layer107due to differing types of the polarized light401. In one embodiment, the open region419transmits a dose of transversely polarized light413(e.g., a first type of the polarized light401), the polarized region421transmits a dose of longitudinally polarized light415(e.g., a second type of the polarized light401), and the closed regions417are opaque to the polarized light401. In one embodiment, the open region419is transparent to the polarized light401after it has been processed into transversely polarized light413, the closed regions117are opaque to the polarized light401, and the polarized region421is transparent to the polarized light401after it has been processed into longitudinally polarized light415.

Returning now toFIG. 2A, the materials for the photomask405are similar to or the same as the photomask105. In a further embodiment, the polarized region421includes a circular wire grid polarizer and high NA lens. In one embodiment, the polarized region421, the waveplate313, and the adjustable linear polarizer311are used in combination to control types of the light401transmitted through the photomask405. One benefit of controlling the types of the light401is that the photoresist layer407may be finely tuned and adjusted in an improvised or extemporaneous manner (i.e., “on-the-fly”). In one embodiment, a polarization meter (not shown inFIG. 2A) monitors the type of the light401before and during the transmission onto the photoresist layer407. The monitored information may then be provided to the adjustable linear polarizer311, which would then compensate for fluctuations in the types of light patterning the photoresist layer407. In this way, the photoresist layer407receives much fewer variations in the type of light401and, as a result, a much more accurate or tighter process window can be achieved (as opposed to the less accurate process windows associated with one or more currently available techniques of forming ZMVs and traces).

The use of the adjustable linear polarizer311, the waveplate313, and the photomask405can assist with reducing the development time and increasing the quality associated with fabrication of ZMVs and traces. Moreover, use of the adjustable linear polarizer311, the waveplate313, and the photomask405can assist with increasing repeatability of the process by reducing variations in the types of the light401.

InFIG. 2A, the light401passing through the photomask405results in creation of two patterns on the photoresist layer407. The first pattern is created using a dose of the longitudinally polarized light415in an area of the photoresist layer407under the polarized region421of the photomask405. The second pattern is created using a dose of the transversely polarized light413in an area of the photoresist layer407under the open region419of the photomask405.

Referring now toFIG. 2B, which illustrates the package layer400after the photoresist layer407is exposed to the transversely polarized light413and the longitudinally polarized light415according to one embodiment. Following exposure to the lights413,415through the photomask405, the waveplate313, and the adjustable linear polarizer311, the photoresist layer407undergoes chemical responses that vary according to the exposure in the various regions of the resist. As shown inFIG. 2B, after the exposure, at least three 2D regions in the photoresist layer407are created, e.g., two regions423, a region425, and a region427. In one embodiment, the region425represents a 2D image of a first feature (e.g., a via, or any other feature) to be formed on the dielectric layer411; the region427represents a 2D image of a second feature (e.g., a trace, or any other feature adjacent to the first feature) to be formed on the dielectric layer411. The region(s)423are used to protect portions of the seed layer409on the dielectric layer411from exposure. That is, at least two images of the features are created at the same time. Generally, the number of patterned regions, such as regions423,425and427, created is determined by the photoresist chemistry. In alternative embodiments, additional regions in addition to regions423,425and427are created to pattern more than two images at a time.

As shown inFIG. 2B, each of the created regions423,425and427has been exposed to doses of different types of polarized light413,415. In a non-limiting example, region(s)423have not been exposed to the doses of different types of polarized light413,415; region425has been exposed to a dose of longitudinally polarized light415; and region427has been exposed to a dose of transversely polarized light413. The amount of the doses of light413,415can be the same or similar to each other. The amount of the doses of light413,415can be different from each other.

In one non-limiting example, a region425is a base-soluble portion of the photoresist layer407; regions423are unexposed portions of the photoresist layer407; and region427is a cross-linked portion of the photoresist layer407.

Referring now toFIG. 2C, which illustrates the package layer400after the region425of the photoresist layer407has been removed to uncover a top side of the seed layer409according to one embodiment. In one embodiment, region425is selectively removed by dissolution in an aqueous basic developer solution, while leaving regions423and427intact. These other regions (e.g., regions423and427) remain insoluble, either due to a presence of a dissolution inhibitor (e.g., region423, which is unexposed) or due to cross-linking (e.g., region427). In alternative embodiments, region425is selectively removed using other photoresist removal techniques known to one of ordinary skill in the art of electronic device manufacturing (e.g., a dry etch technique, etc.). In one embodiment, one or more features to be formed in the region425comprise a via-pad structure (or ZMV). In one embodiment, the soluble region425is selectively removed to form one or more openings, e.g., an opening429, to expose one or more portions of the seed layer409, e.g., a portion431, while leaving regions423and427intact to form one or more via-pad structures later on in the process. Opening429can have a circular, oval, elliptical, square, rectangular, or any other shape.

With regard now toFIG. 2D, which illustrates the package layer400after a first conductive layer433is deposited onto the uncovered top side of a portion431of the seed layer409according to one embodiment. In one embodiment, a first conductive layer433is a part of a via-pad structure (e.g., a ZMV). Examples of the conductive materials are described above in connection with at leastFIG. 1D. In one embodiment, the conductive layer433is similar to or the same as the conductive layer133described above in connection with at leastFIG. 1D, so the conductive layer433is not described in detail for brevity.

Referring now toFIG. 2E, which illustrates the package layer400after a region427of the photoresist layer407is removed to uncover a top side of a portion437of the seed layer409according to one embodiment. One or more features formed on the portion437of the seed layer409comprise a trace. As shown inFIG. 2E, the region427is selectively removed to form one or more open regions, such as open region435to expose one or more portions, such as a portion437of the seed layer409while leaving regions423of the photoresist layer407and conductive layer433intact. As shown inFIG. 2E, the conductive layer433is bounded by a top surface and a sidewall surface. The sidewall surface of the conductive layer433is exposed by removal of the region427of the photoresist layer407. In one embodiment, region427is removed using removal techniques that are similar to or the same as the removal techniques used on region127, so the removal of region427is not described in detail for brevity.

With regard now toFIG. 2F, which illustrates the package layer400after a second conductive layer439is deposited onto the first conductive layer433and the exposed portion437of the seed layer409according to one embodiment. As shown inFIG. 2F, a second conductive layer439is deposited onto the portions437and simultaneously on top of a first conductive layer433. The second conductive layer439is similar to or the same as the second conductive layer139ofFIGS. 1F-1Gthat is described above, so the second conductive layer439is not described in detail for brevity.

In one embodiment, where the photoresist layer407comprises more than three patterned regions, the remaining patterned regions are developed and a conductive layer is deposited in a manner similar to the manner described with respect toFIGS. 2A-2F. Generally, deposition of the conductive layer is additive, so each successive conductive layer deposition operation adds to the height of all uncovered conductive structures.

With regard now toFIG. 2G, which illustrates the package layer400after regions423of the photoresist layer407and portions of the seed layer409are removed to uncover one or more portions of the dieletric layer411according to one embodiment. The regions423are removed to expose underlying portions of the seed layer409. Subsequently, the underlying portions of the seed layer409are removed to define a metal pattern. In one embodiment, the regions423of the photoresist layer407are removed using removal techniques that are similar to or the same as the removal techniques used to remove regions123of the photoresist layer107that are described above in connection withFIG. 1G. In one embodiment, the underlying portions of the seed layer409are removed using removal techniques that are similar to or the same the removal techniques used on the underlying portions of the seed layer109that are described above in connection withFIG. 1G. As shown inFIG. 2G, the via-pad structure (e.g., a ZMV, etc.) formed from the conductive layers433and439comprise a via portion441and a trace portion443. The via portion441is similar to or the same as the via portion141that is described above in connection withFIG. 1G. The trace portion443is similar to or the same as the trace portion143that is described above in connection withFIG. 1G.

FIG. 3illustrates a schematic of computer system800according to an embodiment. The computer system800(also referred to as an electronic system800) can include a semiconductor package that includes at least one ZMV and/or a trace in accord with any of the embodiments and their equivalents as set forth in this disclosure. The computer system800may be a mobile device, a netbook computer, a wireless smart phone, a desktop computer, a hand-held reader, a server system, a supercomputer, or a high-performance computing system.

The electronic system800can be a computer system that includes a system bus820to electrically couple the various components of the electronic system800. The system bus820is a bus or any combination of busses according to various embodiments. The electronic system800includes a voltage source830that provides power to the integrated circuit810. In one embodiment, the voltage source830supplies current to the integrated circuit810through the system bus820.

The integrated circuit810is electrically coupled to the system bus820and includes any circuit, or combination of circuits according to an embodiment. For an embodiment, the integrated circuit810includes a processor812that can be of any type. As used herein, the processor812may mean any type of circuit such as, but not limited to, a microprocessor, a microcontroller, a graphics processor, a digital signal processor, or another processor. For an embodiment, the processor812includes, or is coupled with, a semiconductor package that includes at least one ZMV and/or a trace in accord with any of the embodiments and their equivalents, as described in the foregoing specification. For an embodiment, static random-access memory (SRAM) embodiments are found in memory caches of the processor. Other types of circuits that can be included in the integrated circuit810are a custom circuit or an application-specific integrated circuit (ASIC), such as a communications circuit814for use in wireless devices such as cellular telephones, smart phones, pagers, portable computers, two-way radios, and similar electronic systems, or a communications circuit for servers. For an embodiment, the integrated circuit810includes on-die memory816such as SRAM. For an embodiment, the integrated circuit810includes embedded on-die memory816such as embedded dynamic random-access memory (eDRAM). For one embodiment, the on-die memory816may be packaged with a process that includes one or more embodiments of protection against galvanic corrosion in accord with any of the embodiments and their equivalents, as described in the foregoing specification.

For an embodiment, the integrated circuit810is complemented with a subsequent integrated circuit811. Useful embodiments include a dual processor813and a dual communications circuit815and dual on-die memory817such as SRAM. For an embodiment, the dual integrated circuit810includes embedded on-die memory817such as eDRAM.

For an embodiment, the electronic system800also includes an external memory840that in turn may include one or more memory elements suitable to the particular application, such as a main memory842in the form of RAM, one or more hard drives844, and/or one or more drives that handle removable media846, such as diskettes, compact disks (CDs), digital variable disks (DVDs), flash memory drives, and other removable media known in the art. The external memory840may also be embedded memory848such as the first die in a die stack, according to an embodiment.

For an embodiment, the electronic system800also includes a display device850and an audio output860. For an embodiment, the electronic system800includes an input device such as a controller870that may be a keyboard, mouse, trackball, game controller, microphone, voice-recognition device, or any other input device that inputs information into the electronic system800. For an embodiment, an input device870is a camera. For an embodiment, an input device870is a digital sound recorder. For an embodiment, an input device870is a camera and a digital sound recorder.

At least one of the integrated circuits810or811can be implemented in a number of different embodiments, including a semiconductor package that includes at least one ZMV and/or a trace as described herein, an electronic system, a computer system, one or more methods of fabricating an integrated circuit, and one or more methods of fabricating an electronic assembly that includes a semiconductor package that includes at least one ZMV and/or a trace, according to any of the several disclosed embodiments as set forth herein in the various embodiments and their art-recognized equivalents. The elements, materials, geometries, dimensions, and sequence of operations can all be varied to suit particular I/O coupling requirements including array contact count, array contact configuration for a microelectronic die embedded in a processor mounting substrate according to any of the semiconductor packages that includes at least one ZMV and/or a trace in accordance with any of the several disclosed embodiments as set forth herein and their art-recognized equivalents. A foundation substrate may be included, as represented by the dashed line ofFIG. 3. Passive devices may also be included, as is also depicted inFIG. 3.

Reference throughout this specification to “one embodiment,” “an embodiment,” “another embodiment” and their variations means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment,” “in an embodiment,” “in another embodiment,” or their variations in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.

The description provided above in connection with one or more embodiments as described herein that is included as part of a process of forming semiconductor packages may also be used for other types of IC packages and mixed logic-memory package stacks. In addition, the processing sequences may be compatible with both wafer level packages (WLP), and integration with surface mount substrates such as LGA, QFN, and ceramic substrates.

In the foregoing specification, abstract, and/or Figures, numerous specific details are set forth, such as specific materials and processing operations, in order to provide a thorough understanding of embodiments described herein. It will, however, be evident that any of the embodiments described herein may be practiced without these specific details. In other instances, well-known features, such as the integrated circuitry of semi conductive dies, are not described in detail in order to not unnecessarily obscure embodiments described herein. Furthermore, it is to be understood that the various embodiments shown in the Figures and described in connection with the Figures are illustrative representations and are not necessarily drawn to scale. Thus, various modifications and/or changes may be made without departing form the broader spirit and scope of the embodiments described in connection with the foregoing specification, abstract, and/or Figures.

Embodiments described herein include a method of forming a semiconductor package, the method comprising: depositing a photoresist layer on a seed layer that is on a dielectric layer, wherein the photoresist layer comprises dual-tone photoresist materials; removing a first region of the photoresist layer to uncover a first portion of the seed layer to form a zero misalignment-via (ZMV), wherein the first region of the photoresist layer is exposed to a first dose of light; depositing a first conductive layer onto the first portion; removing a second region of the photoresist layer adjacent to the first region to uncover a second portion of the seed layer to form a trace, wherein the second region of the photoresist layer is exposed to a second dose of light that differs from the first dose of light; and depositing a second conductive layer onto the first conductive layer and the second portion of the seed layer.

Additional embodiments include a method, wherein the light is processed by an adjustable polarizer and a photomask to generate polarized light.

Additional embodiments include a method, wherein the adjustable polarizer comprises one or more of: one or more linear polarizers; and one or more circular polarizers.

Additional embodiments include a method, wherein the photomask comprises one or more gray-scale masks.

Additional embodiments include a method, wherein the photomask comprises: a first region that prevents the polarized light from passing through the photomask; a second region comprising a polarizer that allows varying doses of the polarized light to pass through the photomask; and a third region that allows a fixed dose of the polarized light to pass through the photomask.

Additional embodiments include a method, wherein the first dose is the fixed dose.

Additional embodiments include a method, wherein the second dose is selected from one or more of the varying doses.

Additional embodiments include a method, wherein the photoresist layer is formed from a positive resist material.

Embodiments described herein include a method of forming a semiconductor package, the method comprising: depositing a photoresist layer on a seed layer that is on a dielectric layer, wherein the photoresist layer comprises dual-tone photoresist materials; removing a first region of the photoresist layer to uncover a first portion of the seed layer to form a zero misalignment-via (ZMV), wherein the first region of the photoresist layer is exposed to a first type of light; depositing a first conductive layer onto the first portion; removing a second region of the photoresist layer adjacent to the first region to uncover a second portion of the seed layer to form a trace, wherein the second region of the photoresist layer is exposed to a second type of light that differs from the first type of light; and depositing a second conductive layer onto the first conductive layer and the second portion of the seed layer.

Additional embodiments include a method, wherein the light is processed by an adjustable polarizer, a waveplate, and a photomask to generate transversely polarized light and longitudinally polarized light.

Additional embodiments include a method, wherein the adjustable polarizer comprises one or more linear polarizers for generating the transversely polarized light.

Additional embodiments include a method, wherein the waveplate processes the transversely polarized light to generate circular polarized light.

Additional embodiments include a method, wherein the photomask comprises: a first region that prevents the polarized light from passing through the photomask; a second region comprising a circular wire grid polarizer and a numerical aperture lens that processes the circular polarized light to generate the longitudinally polarized light, wherein the second region allows the longitudinally polarized light to pass through the photomask; and a third region that allows the transversely polarized light to pass through the photomask.

Additional embodiments include a method, wherein the first type of light is the longitudinally polarized light.

Additional embodiments include a method, wherein the second type of light is the transversely polarized light.

Additional embodiments include a method, wherein the photoresist layer is formed from a positive resist material.

Additional embodiments include a method, wherein the photoresist layer is formed from a polarization-selective resist material.

Additional embodiments include a method, wherein the light comprises longitudinally polarized light and transversely polarized light and wherein the photoresist layer is more sensitive to the longitudinally polarized light than the transversely polarized light.

Embodiments described herein include a method of forming a semiconductor package, the method comprising: depositing a photoresist layer on a seed layer that is on a dielectric layer, wherein the photoresist layer comprises dual-tone photoresist materials; removing a first region of the photoresist layer to expose a first portion of the seed layer to form a zero misalignment-via (ZMV), wherein the first region of the photoresist layer is exposed to longitudinally polarized light; depositing a first conductive layer onto the first portion; removing a second region of the photoresist layer adjacent to the first region to expose a second portion of the seed layer to form a trace, wherein the second region of the photoresist layer is exposed to transversely polarized light; and depositing a second conductive layer onto the first conductive layer and the second portion of the seed layer.

Additional embodiments include a method, wherein the photoresist layer is formed from a polarization-selective resist material and wherein the photoresist layer is more sensitive to the longitudinally polarized light than the transversely polarized light.

The terms used in the following claims should not be construed to limit any of the embodiments described in connection with the foregoing specification, abstract, and/or Figures to the specific embodiments set forth in the foregoing specification, abstract, Figures, and/or claims. Rather, the scope of the claims are to be construed in accordance with established doctrines of claim interpretation.