Tunneling field effect transistor switch device

A tunneling field effect transistor (TFET) device includes a semiconductor substrate having a layer of relatively intermediate bandgap semiconductor material, a layer of relatively low bandgap semiconductor material overlying the layer of relatively intermediate bandgap semiconductor material, and a layer of relatively high bandgap semiconductor material overlying the layer of relatively low bandgap semiconductor material. The TFET device includes a source region, a drain region, and a channel region defined in the semiconductor substrate. The TFET device also has a gate structure overlying at least a portion of the channel region. The source region is highly doped with an impurity dopant having a first conductivity type, and the drain region is highly doped with an impurity dopant having a second conductivity type. The layer of relatively low bandgap semiconductor material promotes tunneling at a first junction between the source region and the channel region, and the layer of relatively high bandgap semiconductor material inhibits tunneling at a second junction between the source region and the channel region.

TECHNICAL FIELD

Embodiments of the subject matter described herein relate generally to semiconductor devices. More particularly, embodiments of the subject matter relate to an improved tunneling field effect transistor (TFET) structure that is suitable for use as a semiconductor switch device.

BACKGROUND

The prior art includes TFET devices, which can be used as semiconductor switches. Conventional TFET devices take advantage of tunneling current between the source region and the channel region. The tunneling occurs under certain bias voltage conditions; otherwise, the TFET device functions as a reverse-biased diode. In this regard,FIG. 1is a schematic cross sectional view of a conventional N-type TFET device100. TFET device100includes a layer of semiconductor material102, a source region104, a drain region106, and a gate structure108. Most of semiconductor material102is lightly doped with an N-type impurity (N−). Source region104, which is formed in semiconductor material102, is highly doped with a P-type impurity (P+). Drain region106, which is also formed in semiconductor material102, is highly doped with an N-type impurity (N+). TFET device100includes a channel region110that is located between source region104and drain region106. As shown inFIG. 1, channel region110is generally located below gate structure108, as is well understood.

When used as a semiconductor switch device, TFET device100is biased such that the drain voltage (Vd) is higher than the source voltage (Vs). The gate voltage (Vg) is then controlled to turn the switch on or off. More specifically, if Vg is higher than the threshold voltage (Vt) of TFET device100, then the switch turns on and source-to-drain current flows. If, however, Vg is less than Vt, then the switch remains off, TFET device100functions as a reverse-biased diode, and no current flows.FIG. 1depicts a state where TFET device100is conducting source-to-drain current (Vs=0.0 volts; Vg=1.0 volts; Vd=1.0 volts). Under these bias conditions, electrons accumulate in channel region110near the upper surface of semiconductor material102and directly under gate structure108. This accumulation of electrons in turn creates a very well defined and localized P+/N+ junction between source region104and channel region110. This stiff P+/N+ junction represents a tunneling junction112for TFET device100. Electrons and holes can easily pass or tunnel through tunneling junction112, which results in high source-to-drain current.

A TFET device may also be fabricated as a P-type device.FIG. 2is a schematic cross sectional view of a conventional P-type TFET device200. TFET device200(which is very similar to TFET device100) includes a layer of semiconductor material202, a source region204, a drain region206, and a gate structure208. In contrast to TFET device100, however, most of semiconductor material202is lightly doped with a P-type impurity (P−), source region204is highly doped with an N-type impurity (N+), and drain region206is highly doped with a P-type impurity (P+). TFET device200includes a channel region210that is located between source region204and drain region206.

When used as a semiconductor switch device, TFET device200is biased such that Vd is less than Vs. The gate voltage (Vg) is then controlled to turn the switch on or off. More specifically, if Vg is lower than Vt, then the switch turns on and source-to-drain current flows. If, however, Vg is greater than Vt, then the switch remains off.FIG. 2depicts a state where TFET device200is conducting source-to-drain current (Vs=1.0 volts; Vg=0.0 volts; Vd=0.0 volts). Under these bias conditions, holes accumulate in channel region210near the upper surface of semiconductor material202and directly under gate structure208. This accumulation of holes in turn creates a very well defined and localized N+/P+ junction between source region204and channel region210. This stiff N+/P+ junction represents a tunneling junction212for TFET device200. Electrons and holes can easily pass or tunnel through tunneling junction212, which results in high source-to-drain current.

BRIEF SUMMARY

A semiconductor device is provided, wherein the semiconductor device includes a first layer of semiconductor material, a second layer of semiconductor material overlying the first layer of semiconductor material, the second layer of semiconductor material comprising a relatively low bandgap material, and a third layer of semiconductor material overlying the second layer of semiconductor material, the third layer of semiconductor material comprising a relatively high bandgap material. The semiconductor device also includes a gate structure formed on the third layer of semiconductor material, a source region defined in the third layer of semiconductor material and in the second layer of semiconductor material, and a drain region defined in the third layer of semiconductor material and in the second layer of semiconductor material.

Also provided is a semiconductor switch device having a semiconductor substrate, a gate structure formed on the semiconductor substrate, a source region defined in the semiconductor substrate, a drain region defined in the semiconductor substrate, and a channel region defined in the semiconductor substrate. The source region is heavily doped with a first conductivity type impurity, the drain region is heavily doped with a second conductivity type impurity, and at least a portion of the channel region is underlying the gate structure. In the channel region, the semiconductor substrate comprises an upper layer formed from a relatively high bandgap material and a lower layer formed from a relatively low bandgap material.

A TFET device is also provided. The TFET device includes a semiconductor substrate comprising a layer of relatively intermediate bandgap semiconductor material, a layer of relatively low bandgap semiconductor material overlying the layer of relatively intermediate bandgap semiconductor material, and a layer of relatively high bandgap semiconductor material overlying the layer of relatively low bandgap semiconductor material. The TFET device also includes a source region defined in the semiconductor substrate, the source region being highly doped with impurity dopant having a first conductivity type. The TFET device also includes a drain region defined in the semiconductor substrate, the drain region being highly doped with impurity dopant having a second conductivity type. The TFET device also includes a channel region defined in the semiconductor substrate between the source region and the drain region, and a gate structure formed on the semiconductor substrate, the gate structure overlying at least a portion of the channel region. The layer of relatively low bandgap semiconductor material promotes tunneling at a first junction between the source region and the channel region, and the layer of relatively high bandgap semiconductor material inhibits tunneling at a second junction between the source region and the channel region.

DETAILED DESCRIPTION

For the sake of brevity, conventional techniques related to semiconductor device fabrication may not be described in detail herein. Moreover, the various tasks and process steps described herein may be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor based transistors are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well known process details.

The techniques and technologies described herein may be utilized to fabricate MOS devices, including NMOS transistor switch devices, PMOS transistor switch devices, and CMOS devices. Although the term “MOS device” properly refers to a device having a metal gate electrode and an oxide gate insulator, that term will be used throughout to refer to any semiconductor device that includes a conductive gate electrode (whether metal or other conductive material) that is positioned over a gate insulator (whether oxide or other insulator) which, in turn, is positioned over a semiconductor substrate.

Semiconductor switches based on conventional CMOSFET designs perform well if the transistors are relatively large. Modern semiconductor fabrication processes, however, create extremely small scale devices. For example, modern processes can employ 15 nm node technologies that result in very short gate lengths. At such a small scale, conventional CMOSFET switches do not perform reliably or adequately, if at all. TFET switch devices have been introduced as an alternative to conventional CMOSFET switches, and TFET switch devices do not suffer from the same scaling limitations as CMOSFET switches.

Ideally, the source junction of a TFET switch device is precisely aligned with the sidewall of the gate structure, as depicted inFIG. 1andFIG. 2. With such edge alignment, the vertical field from the gate structure is less than the lateral field from the source region. Accordingly, the on/off transition (current conduction) for an edge-aligned TFET switch device is not critically dependent on the gate bias, which results in sharp on/off behavior. Manufacturing TFET switch devices with precise edge alignment between the gate structure and the source region is very difficult to achieve in practice. Rather, a given semiconductor fabrication process may result in some edge-aligned TFET switch devices, and some “offset” TFET switch devices.

FIG. 3is a schematic cross sectional view of a TFET device300having an inwardly offset source region302. Here, source region302protrudes beneath the gate structure304of TFET device300; gate structure304overlaps at least a portion of source region302. If the source-to-channel junction is located under gate structure304, then gate induced drain leakage current will be caused by the vertical electric field established between source region302and gate structure304(under bias conditions intended to switch TFET device300on). The gate induced drain leakage current will increase the driving current, but it will be strongly dependent upon the gate field. As a result, the off/on characteristic of TFET device300is less than ideal. More specifically, the off/on transition is gradual rather than steep and sharp as desired.

Conversely,FIG. 4is a schematic cross sectional view of a TFET device400having an outwardly offset source region402. Here, source region402is spaced apart from the gate structure404of TFET device400; the edge of gate structure404is not aligned with the source junction. If the source junction is located a distance away from gate structure404, then the required tunneling distance becomes extended (relative to the ideal gate-aligned configuration). As a result, the performance of TFET device400is less than ideal. More specifically, current conduction suffers and the amount of current is less than that exhibited by an ideal gate-aligned TFET device.

The semiconductor TFET switch device described below has an improved structure that makes it less sensitive to source/gate misalignment. Even if source/gate misalignment occurs, the TFET switch device described below will still function as intended. Thus, the current conduction and off/on transition characteristics of the TFET switch device are relatively predictable and consistent over a range of practical fabrication tolerances.

FIG. 5is a schematic cross sectional view of an exemplary embodiment of an N-type TFET device500. Although the following description refers to an N-type implementation, the concepts, techniques, and technologies also apply equivalently to a P-type implementation. Those familiar with semiconductor devices and related manufacturing processes will understand how an equivalent P-type TFET device can be fabricated and operated. Indeed, both N-type and P-type TFET devices could be fabricated on a common wafer using CMOS process technologies.

The illustrated embodiment of TFET device500is formed on a semiconductor substrate502. Semiconductor substrate502includes, without limitation: a first layer of semiconductor material504; a second layer of semiconductor material506overlying the first layer of semiconductor material504; and a third layer of semiconductor material508overlying the second layer of semiconductor material506. The first layer of semiconductor material504is preferably a silicon material as typically used in the semiconductor industry, e.g., relatively pure silicon as well as silicon admixed with other elements. Alternatively, the first layer of semiconductor material504may be germanium, gallium arsenide, or the like. The first layer of semiconductor material504can be either N-type or P-type, but is typically P-type (which is then doped with an appropriate impurity dopant). Moreover, the first layer of semiconductor material504may be part of a bulk semiconductor wafer, or it may be realized as a thin layer of semiconductor material on an insulating substrate (commonly known as semiconductor-on-insulator or SOI) that, in turn, is supported by a carrier wafer.

For this embodiment, the first layer of semiconductor material504comprises silicon that is lightly doped with an N-type impurity dopant such as arsenic, phosphorus, or antimony. This lightly doped state is indicated by the label (N−) inFIG. 5. In exemplary embodiments, the doping concentration may be in the range between about 1016to 1018cm−3. Typically, the first layer of semiconductor material504will be realized as a lightly doped N-type well formed within a larger region of a P-type semiconductor layer (not shown inFIG. 5).

The second layer of semiconductor material506is preferably a silicon material that is admixed with at least one other element. For example, the second layer of semiconductor material506may include silicon germanium (SiGe), pure Ge, GaAs, or InGaAs. In preferred embodiments, the second layer of semiconductor material506is epitaxially grown SiGe that is grown to a desired thickness on the first layer of semiconductor material504using well known techniques and technologies. Although the actual thickness of the second layer of semiconductor material506may vary to suit the particular application, a typical thickness can be within the range of about 5-50 nm. The epitaxially grown SiGe material need not be in-situ doped, for reasons that will become apparent.

The third layer of semiconductor material508is preferably a silicon material that is admixed with at least one other element. For example, the third layer of semiconductor material508may include silicon carbon (SiC), or pure Si. In preferred embodiments, the third layer of semiconductor material508is epitaxially grown SiC that is grown to a desired thickness on the second layer of semiconductor material506using well known techniques and technologies. As shown inFIG. 5, the second layer of semiconductor material506resides between the first layer of semiconductor material504and the third layer of semiconductor material508. Although the actual thickness of the third layer of semiconductor material508may vary to suit the particular application, a typical thickness can be within the range of about 1-5 nm. The epitaxially grown SiC material need not be in-situ doped, for reasons that will become apparent.

Notably, the first layer of semiconductor material504is formed from a relatively intermediate bandgap material, the second layer of semiconductor material506is formed from a relatively low bandgap material, and the third layer of semiconductor material508is formed from a relatively high bandgap material. As used herein, “bandgap” refers to an energy difference (typically expressed in electron volts, eV) between the valence band and the conduction band of a semiconductor material. The bandgap energy represents the minimum amount of energy needed for an electron to jump from the valence band to the conduction band.

In certain embodiments, the relatively low bandgap material used for the second layer of semiconductor material506exhibits a bandgap within the range of about 1.0 to 1.2 eV, the relatively intermediate bandgap material used for the first layer of semiconductor material504exhibits a bandgap within the range of about 0.6 to 1.0 eV, and the relatively high bandgap material used for the third layer of semiconductor material508exhibits a bandgap within the range of about 1.0 to 2.8 eV. It should be appreciated that the specific bandgap values may vary from one device to another, from one fabrication process to another, and/or to suit the needs of the given application. The above exemplary ranges are typical, and are not intended to limit or otherwise restrict the scope of the subject matter described herein.

TFET device500also includes a gate structure520formed on semiconductor substrate502. More specifically, gate structure520is formed overlying the third layer of semiconductor material508. TFET device500also includes a source region522defined in semiconductor substrate502, a drain region524defined in semiconductor substrate502, and a channel region526defined in semiconductor substrate502. Channel region526is located between source region522and drain region524, and gate structure520overlies at least a portion of channel region526.

Gate structure520may include a gate insulator540, a gate electrode542overlying gate insulator540, and a gate contact area544. Gate insulator540can be formed from a layer of thermally grown silicon dioxide or a deposited insulator such as a silicon oxide, silicon nitride, or the like. Gate insulator540preferably has a thickness of about 1-10 nm, although the actual thickness can be determined based on the particular application or circuit being implemented. In accordance with one embodiment, gate electrode542is formed from polycrystalline silicon. Gate contact area544is preferably realized as a metal silicide area formed on gate electrode542.

Gate structure520includes two sidewalls: a source sidewall546that is proximate the source side of TFET device500; and a drain sidewall548that is proximate the drain side of TFET device500. The illustrated embodiment of TFET device500includes a spacer550on source sidewall546, and a spacer552on drain sidewall548. Spacers550/552are formed from a suitable dielectric material such as silicon oxide and/or silicon nitride, preferably silicon nitride.

During fabrication of TFET device500, gate structure520may be used as a part of an ion implantation mask (during one or more ion implantation steps that create source region522and drain region524). In this regard, source region522and drain region524can be formed by implanting ions of an appropriate species. In preferred embodiments, source region522becomes heavily doped with a P-type impurity dopant (as indicated by the P+ label), and drain region524becomes heavily doped with an N-type impurity dopant (as indicated by the N+ label). The P-type dopant may be, without limitation: boron, aluminum, gallium, or indium. The N-type impurity may be, without limitation: arsenic, phosphorus, or antimony. In exemplary embodiments, the doping concentration may be in the range between about 1020to 5×1021cm−3.

For the illustrated embodiment, at least a portion of source region522is defined and formed in each of the three layers of semiconductor substrate502. In other words, portions of all three layers are heavily doped to form the P+ source region522. More specifically, an upper portion522aof source region522is defined in the third layer of semiconductor material508, a middle portion522bof source region522is defined in the second layer of semiconductor material506, and a lower portion522cof source region522is defined in the first layer of semiconductor material504. Similarly, at least a portion of drain region524is defined and formed in each of the three layers of semiconductor substrate502. Thus, portions of all three layers are heavily doped to form the N+ drain region524. More specifically, an upper portion524aof drain region524is defined in the third layer of semiconductor material508, a middle portion524bof drain region524is defined in the second layer of semiconductor material506, and a lower portion524cof drain region524is defined in the first layer of semiconductor material504. Likewise, channel region526includes or is formed in each of the three layers of semiconductor substrate502. In other words, an upper portion526aof channel region526is defined in the third layer of semiconductor material508, a middle portion526bof channel region526is defined in the second layer of semiconductor material506, and a lower portion526cof channel region526is defined in the first layer of semiconductor material504.

As described above, the third layer of semiconductor material508has a relatively large bandgap, the second layer of semiconductor material506has a relatively small bandgap, and the first layer of semiconductor material504has a relatively intermediate bandgap (i.e., a bandgap that falls between the relatively small bandgap and the relatively large bandgap). The relatively low bandgap material used for the second layer of semiconductor material506enhances and promotes tunneling at a junction that is defined in the second layer of semiconductor material506. More particularly, this enhanced tunneling occurs at a junction between source region522and channel region526, where the junction is located in the second layer of semiconductor material506.FIG. 6includes a circled region that indicates this source-to-channel junction560. Referring also toFIG. 5, source-to-channel junction560represents the junction between the middle portion522bof source region522and the middle portion526bof channel region526. Conversely, the relatively high bandgap material used for the third layer of semiconductor material508inhibits or impedes tunneling at a junction that is defined in the third layer of semiconductor material508. More particularly, tunneling is reduced, impeded, or inhibited at a second junction between source region522and channel region526, where this second junction is located in the third layer of semiconductor material508. Referring also toFIG. 5, this second junction represents the junction between the upper portion522aof source region522and the upper portion526aof channel region526.

TFET device500includes a source contact area570for source region522, and a drain contact area572for drain region524. Source contact area570is preferably realized as a metal silicide area formed on the section of the third layer of semiconductor material508that corresponds to upper portion522aof source region522. Similarly, drain contact area572is preferably realized as a metal silicide area formed on the section of the third layer of semiconductor material508that corresponds to upper portion524aof drain region524. Source contact area570, gate contact area544, and drain contact area572are utilized to establish respective bias potentials for source region522, gate electrode542, and drain region524, as is well understood. Although not depicted in the figures, TFET device500may include additional features, elements, and/or layers, such as an overlying dielectric layer and conductive plugs formed in the dielectric layer. The conductive plugs are electrically coupled to source contact area570, gate contact area544, and drain contact area572, and the conductive plugs are used to provide the various bias voltages to TFET device500.

FIG. 6depicts TFET device500under bias conditions that turn the switch on, i.e., TFET device500conducts current. The bias conditions are as follows: Vd>Vs; and Vg>Vt. Under these conditions, the relatively low bandgap characteristics of the second layer of semiconductor material506results in tunneling at the source-to-channel junction560. In turn, relatively high source-to-drain current flows within the second layer of semiconductor material506(the solid arrow inFIG. 6represents this current flow). Conversely, the relatively high bandgap characteristics of the third layer of semiconductor material508results in little or no tunneling at the source-to-channel junction in the third layer of semiconductor material508. Although a small amount of source-to-drain current may flow within the third layer of semiconductor material508(the dashed arrow inFIG. 6represents this current flow), a significant amount of the overall source-to-drain current results from the tunneling at the source-to-channel junction560.

Notably, the configuration of TFET device500is such that tunneling occurs deeper in the semiconductor substrate502(compared to conventional structures that achieve tunneling at or near the lower surface of the gate structure). Accordingly, TFET device500is designed to improve tunneling efficiency below gate structure520, and to degrade tunneling efficiency directly below gate structure520. These characteristics of TFET device500make it less sensitive to offsetting of gate structure520relative to source region522. Therefore, it is possible to design the device with the source region522inwardly offset relative to gate structure520. This will give more process control margin than conventional structures, which require perfect alignment between the source region and the gate structure. In operation, the tunneling (on/off) characteristics of TFET device500are less dependent on Vg, relative to conventional TFET designs.

FIG. 5andFIG. 6depict an NTFET device implementation. Those familiar with semiconductor devices and related manufacturing processes will understand that the techniques and technologies described above for TFET device500can be extended and equivalently applied to a PTFET device implementation. The same semiconductor substrate configuration, materials, and properties are utilized for both NTFET and PTFET implementations. For a PTFET device, however, the device will be formed in a lightly doped P-type region, the source region will be heavily doped with an N-type impurity, and the drain region will be heavily doped with a P-type impurity. In addition, the bias voltages will be different (as explained above with reference toFIG. 2).

A TFET device (such as TFET device500) can be fabricated using known semiconductor fabrication techniques. The TFET devices described herein can be fabricated using relatively small scale semiconductor device manufacturing process technologies, e.g., 32 nm node technology, 15 nm node technology, and beyond (however, the use of such node technologies is not a requirement). Moreover, a suitable CMOS manufacturing process could be used to create both NTFET and PTFET switch devices on a common substrate.

FIGS. 7-10are schematic cross sectional views that illustrate an exemplary fabrication process for an N-type TFET device. Referring toFIG. 7, the fabrication process may begin with a suitably configured semiconductor substrate602. This embodiment of semiconductor substrate602includes a layer of silicon material604that is lightly doped with an N-type impurity species, a layer of SiGe material606formed on silicon material604, and a layer of SiC material608formed on SiGe material606. As mentioned previously, silicon material604has a relatively intermediate bandgap characteristic, SiGe material606has a relatively low bandgap characteristic, and SiC material608has a relatively high bandgap characteristic. Semiconductor substrate602may be created by epitaxially growing SiGe material606on silicon material604, and by thereafter epitaxially growing SiC material608on SiGe material606.

Although other fabrication steps or sub-processes may be performed on semiconductor substrate602, this example continues by forming a gate structure620on semiconductor substrate602(seeFIG. 8). Gate structure620can be formed using well known process steps that are typically associated with a gate module in an overall fabrication process. These process steps may involve, without limitation: material deposition, growth, or forming steps; photolithography steps; etching steps; cleaning steps; and the like. As described above with reference toFIG. 5, gate structure620may include, without limitation: a gate insulator622, a gate electrode624, and sidewalls626.

Although other fabrication steps or sub-processes may be performed after the formation of gate structure620, this example continues by forming a source region630and a drain region632in semiconductor substrate602(seeFIG. 9). For this NTFET implementation, source region630will be a heavily doped P-type region, and drain region632will be a heavily doped N-type region. Source region630can be formed by introducing ions of an appropriate P-type impurity species into the three layers of semiconductor substrate602. Likewise, drain region632can be formed by introducing ions of an appropriate N-type impurity species into the three layers of semiconductor substrate602. In practice, the formation of source region630and drain region632may require two separate ion implantation steps, using gate structure620and possibly other structures such as patterned photoresist material (not shown) as an ion implantation mask.

Although other fabrication steps or sub-processes may be performed at this time (e.g., thermal annealing, formation of additional spacers, etc.), this example continues by forming metal silicide contact areas640on the exposed areas of SiC material608. In addition, a metal silicide contact area642may be formed on gate electrode624(seeFIG. 10). It should be apparent thatFIG. 10depicts a TFET device structure650after a number of known process steps have been performed. For the sake of brevity, these intermediate steps will not be described in detail. In practice, an appropriate silicidation process is performed to create metal silicide contact areas640and642. For example, a layer of silicide-forming metal (not shown) is deposited onto the surfaces of SiC material608and onto the surface of gate electrode624. The silicide-forming metal can be deposited, for example, by sputtering to a thickness of about 5-50 nm and preferably to a thickness of about 10 nm. The semiconductor substrate602is then heated, for example by rapid thermal annealing, to form metal silicide contact areas640and642. The silicide-forming metal can be, for example, cobalt, nickel, rhenium, ruthenium, or palladium, or alloys thereof. Any silicide-forming metal that is not in contact with exposed silicon does not react during heating and, therefore, does not form a silicide. This excess metal may be removed by wet etching or any suitable procedure.

Thereafter, any number of known process steps can be performed to complete the fabrication of the TFET switch device. For example, an insulating layer may be formed over TFET device structure650, and the insulating layer may be used to accommodate conductive plugs for metal silicide contact areas640and642. In turn, the conductive plugs can be utilized to control the bias voltage conditions of the TFET switch device (to turn the TFET switch device on and off). For the sake of brevity, additional backend process steps and the resulting TFET switch device are not shown or described here.