INTEGRATED DEVICE COMPRISING PLATE INTERCONNECTS AND A MAGNETIC MATERIAL

A device comprising a die substrate, a plurality of interconnects located over the die substrate, at least one magnetic layer, and at least one dielectric layer located over the die substrate. The plurality of interconnects comprise a first plurality of plate interconnects, a second plurality of plate interconnects, and a plurality of via interconnects coupled to the first plurality of plate interconnects and the second plurality of plate interconnects. The first plurality of plate interconnects, the plurality of via interconnects, and the second plurality of plate interconnects are configured to operate as an inductor. The at least one magnetic layer surrounds at least part of the plurality of via interconnects.

FIELD

Various features relate to packages, integrated devices and/or integrated passive devices.

BACKGROUND

Packages can include a substrate, an integrated device and integrated passive device. The substrate may include a plurality of interconnects. The integrated device and/or the integrated passive device may be coupled to interconnects of the substrate.

There is an ongoing need to provide smaller packages with improved performances.

SUMMARY

Various features relate to packages, integrated devices and/or integrated passive devices.

One example provides a device comprising a die substrate, a plurality of interconnects located over the die substrate, at least one magnetic layer, and at least one dielectric layer located over the die substrate. The plurality of interconnects comprise a first plurality of plate interconnects, a second plurality of plate interconnects, and a plurality of via interconnects coupled to the first plurality of plate interconnects and the second plurality of plate interconnects. The first plurality of plate interconnects, the plurality of via interconnects and the second plurality of plate interconnects are configured to operate as an inductor. The at least one magnetic layer surrounds at least part of the plurality of via interconnects.

Another example provides a device comprising a first integrated device, a second integrated device, and a third integrated device. The first integrated device includes a die substrate, a plurality of interconnects located over the die substrate, at least one magnetic layer, and at least one dielectric layer located over the die substrate. The plurality of interconnects comprise a first plurality of plate interconnects, a second plurality of plate interconnects, and a plurality of via interconnects coupled to the first plurality of plate interconnects and the second plurality of plate interconnects. The first plurality of plate interconnects, the plurality of via interconnects and the second plurality of plate interconnects are configured to operate as an inductor. The at least one magnetic layer surrounds at least part of the plurality of via interconnects. The second integrated device is configured as power management integrated device, where the second integrated device is configured to be electrically coupled to the first integrated device through a first electrical path. The third integrated device is configured to be electrically coupled to the first integrated device through a second electrical path.

Another example provides a method that provides a die substrate. The method forms a plurality of interconnects over the die substrate, where forming the plurality of interconnects comprises: forming a first plurality of plate interconnects, forming a plurality of via interconnects that coupled are coupled to the first plurality of plate interconnects, and forming a second plurality of plate interconnects that are coupled to the plurality of via interconnects. The first plurality of plate interconnects, the plurality of via interconnects and the second plurality of plate interconnects are configured to operate as an inductor. The method forms at least one magnetic layer that surrounds at least part of the plurality of via interconnects. The method forms at least one dielectric layer over the die substrate.

DETAILED DESCRIPTION

The present disclosure describes a device comprising a die substrate, a plurality of interconnects located over the die substrate, at least one magnetic layer, and at least one dielectric layer located over the die substrate. The plurality of interconnects comprise a first plurality of plate interconnects, a second plurality of plate interconnects, and a plurality of via interconnects coupled to the first plurality of plate interconnects and the second plurality of plate interconnects. The first plurality of plate interconnects, the plurality of via interconnects and the second plurality of plate interconnects are configured to operate as an inductor. The at least one magnetic layer surrounds at least part of the plurality of via interconnects. The at least one magnetic layer includes an insulating layer, a dielectric layer and/or a non-electrical conducting material. The at least one magnetic layer has a permeability value (e.g., relative permeability value) that is greater than 1. The use of the plate interconnects and the magnetic layer helps improve (e.g., reduce) the resistance of a current that passes through the inductor and improve (e.g., increase) the quality factor and/or the inductance of the inductor.

Exemplary Integrated Device Comprising Plate Interconnects and Magnetic Material

FIG.1illustrates a profile view of an assembly100that includes a board101, a substrate102, an integrated device103, a passive device104, a passive device106, an integrated device105and an integrated device107. The board101includes at least one board dielectric layer110and a plurality of board interconnects112. The board101may include a printed circuit board (PCB).

The integrated device103is coupled to board interconnects112from the board101through a plurality of solder interconnects130. The integrated device103may be configured as a power management integrated device. For example, the integrated device103may be a power management integrated circuit (PMIC). The passive device104is coupled to board interconnects112from the board101through a plurality of solder interconnects140. The passive device104may be a discrete inductor. The passive device106is coupled to board interconnects112from the board101through a plurality of solder interconnects160. The passive device106may be a discrete capacitor. In some implementations, the integrated device103, the passive device104and/or the passive device106may be configured as a voltage regulator109.

FIG.1illustrates a package108that is coupled to the board interconnects112of the board101through a plurality of solder interconnects124. The package108includes the substrate102, the integrated device105and the integrated device107. The substrate102includes at least one dielectric layer120(e.g., substrate dielectric layer) and a plurality of interconnects122(e.g., substrate interconnects). The integrated device105may be coupled to the substrate102through a plurality of solder interconnects150. The integrated device105may be coupled to the substrate102through a plurality of pillar interconnects152and the plurality of solder interconnects150. The integrated passive device107may be coupled to the substrate102through a plurality of solder interconnects170. The integrated passive device107may be coupled to the substrate102through a plurality of pillar interconnects172and the plurality of solder interconnects170. A substrate may have a different number of metal layers. Different implementations may use different substrates. The substrate may include an embedded trace substrate (ETS). The at least one dielectric layer120may include prepreg.

The package (e.g.,108) may be implemented in a radio frequency (RF) package. The RF package may be a radio frequency front end (RFFE) package. A package (e.g.,108) may be configured to provide Wireless Fidelity (WiFi) communication and/or cellular communication (e.g., 2G, 3G, 4G, 5G). The package (e.g.,108) may be configured to support Global System for Mobile (GSM) Communications, Universal Mobile Telecommunications System (UMTS), and/or Long-Term Evolution (LTE). The package (e.g.,108) may be configured to transmit and receive signals having different frequencies and/or communication protocols.

As will be further described below, the integrated device105may include a plurality of plate interconnects and at least one magnetic layer. The plate interconnects and the at least one magnetic layer is configured to improve resistance (e.g., reduce resistance) of a current passing through the integrated device105and improve the inductance and/or quality factor of an inductor that is located in and/or surrounded by a magnetic layer. With improved resistance and improved inductor performance, smaller and more compact inductors may be formed in the integrated device105.

The integrated device105may be a first integrated device. In some implementations, the integrated device105may include an integrated passive device. The integrated device103may be a second integrated device. As will be further described below, the integrated device105may be configured as voltage regulator (e.g., integrated voltage regulator). As mentioned above, the integrated device103may be configured as a power management integrated device. The integrated device103may be configured as a voltage regulator and/or part of a voltage regulator. The integrated device107may be a third integrated device. The integrated device107may include a system on chip (SoC). The integrated device107may include a processor.

The integrated device105may be configured to be electrically coupled to the integrated device103through an electrical path194(e.g., first electrical path). The integrated device105may be configured to be electrically coupled to the integrated device107through an electrical path196(e.g., second electrical path). An electrical path (e.g., third electrical path)198may be coupled to the integrated device103.

The electrical path194may be configured as an electrical path for power between the integrated device103and the integrated device105. A power (e.g., first power) traveling through the electrical path194may have a voltage (e.g., first voltage). In some implementations, the first voltage may be in a range between 1-5 volts (V). The electrical path194may include at least one solder interconnect from the plurality of solder interconnects130, at least one board interconnect from the plurality of board interconnects112, at least one solder interconnect from the plurality of solder interconnects124, at least one interconnect from the plurality of interconnects122, and at least one solder interconnect from the plurality of solder interconnects150. The electrical path194may also include at least one pillar interconnect from the plurality of pillar interconnects152.

The electrical path196may be configured as an electrical path for power between the integrated device105and the integrated device107. A power (e.g., second power) traveling through the electrical path196may have a voltage (e.g., second voltage). The second voltage may be different from the first voltage. The second voltage may be less than the first voltage. In some implementations, the second voltage may be about 1 volt (V) or less. The electrical path196may include at least one solder interconnect from the plurality of solder interconnects150, at least one interconnect from the plurality interconnects122and at least one solder interconnect from the plurality of solder interconnects170. The electrical path196may also include at least one pillar interconnect from the plurality of pillar interconnects152and/or at least one pillar interconnect from the plurality of pillar interconnects172.

The electrical path198may extend through the board interconnects112and the plurality of solder interconnects130. The electrical path198may be configured to provide an electrical path for power having a voltage (e.g., third voltage). The third voltage traveling through the electrical path198may be greater than the second voltage traveling through the electrical path194. In some implementations, the first voltage may be about 5 volts (V) or greater.

As will be further described below, the integrated device105includes an inductor and a magnetic material. The integrated device105may include an integrated passive device. The integrated device105may include an active portion that includes transistors. The inductor of the integrated device105may be defined by a plurality of interconnects that include a plurality of plate interconnects.

FIG.2illustrates an inductor200that may be implemented in the integrated device105. The inductor200includes a first plurality of plate interconnects210, a plurality of via interconnects220and a second plurality of plate interconnects230. The first plurality of plate interconnects210are coupled to the plurality of via interconnects220. The second plurality of plate interconnects230are coupled to the plurality of via interconnects220. The plurality of via interconnects220are located between the first plurality of plate interconnects210and the second plurality of plate interconnects230. Although not shown, a magnetic layer may be located between the first plurality of plate interconnects210and the second plurality of plate interconnects230. The magnetic layer may laterally surround the plurality of via interconnects220. A magnetic layer is further described below in at leastFIG.8.

The first plurality of plate interconnects210are located on a first metal layer, and the second plurality of plate interconnects230are located on a second metal layer. The first metal layer may be located above the second metal layer. In some implementations, the second metal layer may be located above the first metal layer. The plurality of via interconnects220includes a via interconnect220a, a via interconnect220b, a via interconnect220c, a via interconnect220d, a via interconnect220e, a via interconnect220f, a via interconnect220g, a via interconnect220h, and a via interconnect220i. Different implementations may have different number of via interconnects.

The first plurality of plate interconnects210includes a plate interconnect210a(e.g., first plate interconnect) and a plate interconnect210b(e.g., second plate interconnect). The first plurality of plate interconnects210are aligned in a first direction. The second plurality of plate interconnects230includes a plate interconnect230a(e.g., first plate interconnect) and a plate interconnect230b(e.g., second plate interconnect). The second plurality of plate interconnects230are aligned in a second direction that is different from the first direction. In some implementations, the second direction is orthogonal to the first direction. A trace interconnect211is coupled to the plate interconnect210a. A trace interconnect231is coupled to the plate interconnect230b. Different implementations may have different number of plate interconnects and/or plate interconnects that are arranged and/or aligned in different directions.

A plate interconnect is an interconnect that has a width that is at least twice as wide as the width of a trace interconnect. For example, one of the plate interconnects (e.g.,210a,210b) may have a first width, one of the plate interconnects (e.g.,230a,230b) may have a second width, and a trace may have a trace width, where the first width and/or the second width has a width that is at least twice as wide as the trace width. A via interconnect may have a via width (e.g., via diameter). In some implementations, the first width and/or the second width of a plate interconnect has a width that is at least twice as wide as the via width. In some implementations, the via interconnects and/or the plate interconnects may have variable widths. In some implementations, a plate interconnect may have a width in a ranged of about 300-400 micrometers. In some implementations, a via interconnect may have a via width that is 100 micrometers or less (e.g., about 50-100 micrometers). In some implementations, a trace interconnect may have a trace width that is 100 micrometers or less. However, different implementations may use different widths for the plate interconnects, the via interconnects, and/or the trace interconnects. The via interconnects may have an aspect ratio of between 1:1 and 2:1. An aspect ratio is a height to width ratio. In some implementations, a via interconnect may have a height in a range of about 75-100 micrometers. However, different implementations may use different heights and/or aspect ratio for the via interconnects.

The plate interconnect210amay be coupled to the via interconnect220g, the via interconnect220h, and the via interconnect220i. The plate interconnect230amay be coupled to the via interconnect220g, the via interconnect220h, and the via interconnect220i. The plate interconnect230amay be coupled to the via interconnect220d, the via interconnect220e, and the via interconnect220f. The plate interconnect210bmay be coupled to the via interconnect220d, the via interconnect220e, and the via interconnect220f. The plate interconnect210bmay be coupled to the via interconnect220a, the via interconnect220b, and the via interconnect220c. The plate interconnect210amay be coupled to the via interconnect220a, the via interconnect220b, and the via interconnect220c. The trace interconnect211may be coupled to the plate interconnect210a. The trace interconnect231may be coupled to the plate interconnect230b.

FIG.3illustrates an example of an electrical path300through the inductor200. The electrical path300through the inductor200may include the plate interconnect230b, the via interconnect220a, the via interconnect220b, the via interconnect220c, the plate interconnect210b, the via interconnect220d, the via interconnect220e, the via interconnect220f, the plate interconnect230a, the via interconnect220g, the via interconnect220h, the via interconnect220i, and the plate interconnect210a. A current (e.g., power) may enter the inductor200through the trace interconnect231and exit through the trace interconnect211. In some implementations, a current (e.g., power) may enter the inductor200through the trace interconnect211and exit through the trace interconnect231.

FIGS.4and5illustrate an inductor with a different design that provides improved inductance.FIG.4illustrates an inductor400that may be implemented in the integrated device105. The inductor400is similar to the inductor200ofFIG.2. The inductor400includes the first plurality of plate interconnects210, the plurality of via interconnects220and the second plurality of plate interconnects230.FIG.4illustrates that the plate interconnect210aincludes a slot410and the plate interconnect230bincludes a slot430. The slot410and/or the slot430may be filed with a dielectric layer. In some implementations, other plate interconnects may have their own respective slot. In some implementations, a plate interconnect may have more than one slot. Different slots may have different sizes and/or shapes. The use of one or more slots helps improve the inductance of the inductor400.

The first plurality of plate interconnects210of the inductor400are coupled to the plurality of via interconnects220of the inductor400in a similar manner as described for the inductor200. The second plurality of plate interconnects230of the inductor400are coupled to the plurality of via interconnects220of the inductor400in a similar manner as described for the inductor200.

The plate interconnect210amay be coupled to the via interconnect220g, the via interconnect220h, and the via interconnect220i. The plate interconnect230amay be coupled to the via interconnect220g, the via interconnect220h, and the via interconnect220i. The plate interconnect230amay be coupled to the via interconnect220d, the via interconnect220e, and the via interconnect220f. The plate interconnect210bmay be coupled to the via interconnect220d, the via interconnect220e, and the via interconnect220f. The plate interconnect210bmay be coupled to the via interconnect220a, the via interconnect220b, and the via interconnect220c. The plate interconnect210amay be coupled to the via interconnect220a, the via interconnect220b, and the via interconnect220c. The trace interconnect211may be coupled to the plate interconnect210a. The trace interconnect231may be coupled to the plate interconnect230b.

FIG.5illustrates an example of an electrical path500through the inductor400. The electrical path500through the inductor400may include the plate interconnect230b, the via interconnect220a, the via interconnect220b, the via interconnect220c, the plate interconnect210b, the via interconnect220d, the via interconnect220e, the via interconnect220f, the plate interconnect230a, the via interconnect220g, the via interconnect220h, the via interconnect220i, and the plate interconnect210a. A current (e.g., power) may enter the inductor200through the trace interconnect231and exit through the trace interconnect211. In some implementations, a current (e.g., power) may enter the inductor200through the trace interconnect211and exit through the trace interconnect231.

FIGS.6and7illustrate graphs that show how inductance is improved through the use of slots in a plate interconnect.FIG.6illustrates an exemplary graph600that includes a plot line of inductance through various frequency for the inductor200.FIG.7illustrates an exemplary graph700that includes a plot line of inductance through various frequency for the inductor400, which include a slot in a plate interconnect. As shown inFIGS.6and7, for certain frequencies, the inductor400has a higher inductance than the inductor200.

FIG.8illustrates an exemplary profile cross sectional view of an integrated device801. The integrated device801may be an integrated passive device. The integrated device801includes a die substrate800, a dielectric layer810, a dielectric layer820, a dielectric layer850, a dielectric layer860, at least one magnetic layer840. The integrated passive device801may also include a plurality of interconnects802. The plurality of interconnects802may include at least one interconnect821, at least one interconnect822, at least one interconnect832, at least one interconnect851, at least one interconnect861and/or at least one interconnect862. As will be further described below, at least some of the interconnects from the plurality of interconnects802are configured to operate as an inductor. The integrated device801may be an example of the integrated device105.

Some of the at least one interconnect832may correspond to the plurality of via interconnects230. In some implementations, some of the at least one interconnect832, the at least one interconnect822and/or the at least one interconnect851may correspond to the plurality of via interconnects230. Some of the at least one interconnect821may correspond to the first plurality of plate interconnects210. Some of the at least one interconnect861may correspond to the second plurality of plate interconnects230.

In some implementations, some of the at least one interconnect861may correspond to the first plurality of plate interconnects210and/or some of the at least one interconnect821may correspond to the second plurality of plate interconnects230.

The die substrate800may include silicon (Si). The die substrate800may include a wafer. The die substrate800may be free of transistors. The dielectric layer810is coupled to a surface of the die substrate800. The dielectric layer810, the dielectric layer820, the dielectric layer850, and the dielectric layer860may be represented as one or more dielectric layers. Thus, in some implementations, one dielectric layer may represent the dielectric layer810, the dielectric layer820, the dielectric layer850, and/or the dielectric layer860. In some implementations, there may be a dielectric layer that laterally surrounds and touches a side surface of the at least one interconnect832(e.g.,832a,832b). In such instances, the dielectric layer may be located between the side surface of the at least one interconnect832and the at least one magnetic layer840. In some implementations, two or more dielectric layers may represent the dielectric layer810, the dielectric layer820, the dielectric layer850, and/or the dielectric layer860. The dielectric layer810, the dielectric layer820, the dielectric layer850, and/or the dielectric layer860may include one or more polyimide (PI). In some implementations, the dielectric layer860may include a passivation layer.

The at least one interconnect821is located over the dielectric layer810. The at least one interconnect822is coupled to the at least one interconnect832and the at least one interconnect821. The at least one interconnect832is coupled to the at least one interconnect851. The at least one interconnect851is coupled to the at least one interconnect861. The at least one interconnect861is coupled to the at least one interconnect862. The at least one interconnect821, the at least one interconnect822, the at least one interconnect832, the at least one interconnect851, and the at least one interconnect861may include copper. In some implementations, the at least one interconnect862may include nickel and/or gold. The at least one interconnect821, at least one interconnect822, at least one interconnect832, at least one interconnect851, at least one interconnect861, and/or at least one interconnect862may be configured to operate as an inductor (e.g., solenoid inductor).

The plurality of interconnects802may include a plurality of metallization interconnects. That is for example, in some implementations, at least some of the interconnects from the plurality of interconnects802may be implemented as a plurality of metallization interconnects. A plurality of metallization interconnects may include a plurality of redistribution interconnects (e.g., redistribution layer (RDL) interconnects). The at least one interconnect832includes an interconnect832aand an interconnect832b. The interconnect832bis planar to the interconnect832a. The interconnect832amay be a via interconnect (e.g., first via interconnect). The interconnect832bmay be a via interconnect (e.g., second via interconnect).

As mentioned above, the integrated device801includes at least one magnetic layer840. The at least one magnetic layer840, laterally surrounds and touches the interconnect832aand/or laterally surrounds and touches the interconnect832b. In some implementations, there may be a dielectric layer that is between the interconnect (e.g.,832a,832b) and the at least one magnetic layer840. Thus, in some implementations, the at least one magnetic layer840may not directly touch the plurality of interconnects832.

The at least one magnetic layer840may include one or more magnetic layers. The at least one magnetic layer840includes an insulating layer, a dielectric layer and/or a non-electrical conducting material (e.g., material that does not electrically conduct). The at least one magnetic layer840may be both a dielectric material and a magnetic material. Thus, the at least one magnetic layer840may have both dielectric properties and magnetic properties. The at least one magnetic layer840may include one or more materials. The at least one magnetic layer840has a permeability value that is greater than 1 (e.g., about 10 or greater, range of 6-12). The magnetic layer840may have different permeability values at different frequencies. The permeability value of a magnetic material and/or a magnetic layer, as described in the disclosure is a relative permeability value that is defined as a ratio of the permeability of a material to the permeability of free space. Thus, the permeability values that are described for the magnetic materials and/or magnetic layers that are illustrated and/or described in the disclosure may represent a relative permeability value that is relative to a defined permeability value (e.g., reference permeability value) of free space. In some implementations, free space may be defined to have a defined permeability value of μ0=4π×10−7H/m (Henry per meter). A material that has a relative permeability value that is greater than 1 may be considered to be a magnetic material. Similarly, a material layer that has a relative permeability value that is greater than 1 may be considered to be a magnetic layer. The at least one magnetic layer840may include a magnetic loss tangent value that is in a range of about 0.01-0.04. For example, the at least one magnetic layer may include a magnetic loss tangent value that is in a range of about 0.01-0.04 for frequencies up to 100 MHz. The at least one magnetic layer840may include may include various magnetic materials. For example, the at least one magnetic layer840may include Ajinomoto Magnetic Film (AMF). The at least one magnetic layer840is configured to improve the inductance and/or quality factor of an inductor that is located in and/or surrounded by the at least one magnetic layer840. With improved inductor performance, smaller and more compact inductors may be formed in the integrated passive device and/or the integrated device.

FIG.9illustrates an exemplary profile cross sectional view of an integrated device901. The integrated device901may be similar to the integrated device801. The integrated device901includes additional metal layer of interconnects. The integrated device901may represent the integrated device105.

The integrated device901includes a die substrate800, a dielectric layer810, a dielectric layer820, a dielectric layer850, a dielectric layer860, a dielectric layer870at least one magnetic layer840. The integrated passive device801may also include a plurality of interconnects802. The plurality of interconnects802may include at least one interconnect821, at least one interconnect822, at least one interconnect832, at least one interconnect851, at least one interconnect861, at least one interconnect871, at least one interconnect881, and/or at least one interconnect891. As will be further described below, at least some of the interconnects from the plurality of interconnects802are configured to operate as an inductor. The integrated device901includes a plurality of pillar interconnects893coupled to the at least one interconnects891. A plurality of solder interconnects895are coupled to the plurality of pillar interconnects893. In some implementations, there may be a dielectric layer that laterally surrounds and touches a side surface of the at least one interconnect832(e.g.,832a,832b). In such instances, the dielectric layer may be located between the side surface of the at least one interconnect832and the at least one magnetic layer840.

Some of the at least one interconnect832may correspond to the plurality of via interconnects230. In some implementations, some of the at least one interconnect832, the at least one interconnect822, and/or the at least one interconnect851may correspond to the plurality of via interconnects230. Some of the at least one interconnect821may correspond to the first plurality of plate interconnects210. Some of the at least one interconnect861may correspond to the second plurality of plate interconnects230.

In some implementations, some of the at least one interconnect861may correspond to the first plurality of plate interconnects210and/or some of the at least one interconnect821may correspond to the second plurality of plate interconnects230.

In some implementations, the integrated device801and/or the integrated device901may include an active portion located in and/or over the die substrate (e.g.,800). The active portion may include at least part of the die substrate800and a plurality of transistors. The plurality of transistors may be formed and/or located in and/or over the die substrate800. The die substrate800may include silicon (Si). The plurality of transistors may form and/or define one or more logical blocks. The plurality of transistors may be any type of transistors (e.g., CMOS transistors, planar transistors, field effect transistors).

An integrated device (e.g.,103,105,107) may include a die (e.g., semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include a radio frequency (RF) device, a passive device, a filter, a capacitor, an inductor, an antenna, a transmitter, a receiver, a gallium arsenide (GaAs) based integrated device, a surface acoustic wave (SAW) filter, a bulk acoustic wave (BAW) filter, a light emitting diode (LED) integrated device, a silicon (Si) based integrated device, a silicon carbide (SiC) based integrated device, a memory, power management processor, and/or combinations thereof. An integrated device (e.g.,103,105,107) may include at least one electronic circuit (e.g., first electronic circuit, second electronic circuit, etc. . . . ). An integrated device may include transistors. An integrated device may be an example of an electrical component and/or electrical device. In some implementations, an integrated device may include a chiplet. A chiplet may be fabricated using a process that provides better yields compared to other processes that are used to fabricate other types of integrated devices, which can lower the overall cost of fabricating a chiplet. Different chiplets may have different sizes and/or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different width and/or spacing). In some implementations, several chiplets may be used to perform the functionalities of one or more chips (e.g., one more integrated devices). Using several chiplets that perform several functions may reduce the overall cost of a package relative to using a single chip to perform all of the functions of a package.

Having described various integrated devices and/or integrated passive devices with at least one magnetic layer, a process for fabricating an integrated device with at least one magnetic layer will be described below.

Exemplary Sequence for Fabricating an Integrated Device Comprising a Plate Interconnect and Magnetic Layer

FIGS.10A-10Eillustrate an exemplary sequence for providing or fabricating an integrated device comprising at least one magnetic layer. In some implementations, the sequence ofFIGS.10A-10Emay be used to provide or fabricate the integrated device105and/or the integrated device801described in the disclosure. In some implementations, the sequence ofFIGS.10A-10Emay be used to provide or fabricate the integrated device105and/or the integrated device901described in the disclosure.

It should be noted that the sequence ofFIGS.10A-10Emay combine one or more stages in order to simplify and/or clarify the sequence for providing or fabricating an integrated device. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more of processes may be replaced or substituted without departing from the spirit of the disclosure. Different implementations may fabricate an integrated device differently. The sequence shown inFIGS.10A-10Emay be implemented on a wafer (e.g., silicon wafer) and then singulated into several integrated devices. A similar approach may be implemented for integrated devices with plate interconnects and a magnetic layer.

Stage1, as shown inFIG.10A, illustrates a state after a die substrate800is provided. The die substrate800may include silicon (Si). A dielectric layer810may be located over a surface of the die substrate800. The die substrate800may be provided with the dielectric layer810. In some implementations, the dielectric layer810may be formed over the surface of the die substrate800. Providing the die substrate800may include providing a wafer (e.g., silicon wafer). In some implementations, a die substrate800may be provided with a plurality of transistors.

Stage2illustrates a state after at least one interconnect821is formed over the dielectric layer810. A plating process and a patterning process may be used to form the at least one interconnect821.

Stage3, as shown inFIG.10B, illustrates a state after at least one dielectric layer820is formed and patterned. A deposition, a lamination, an exposure, a development and/or an etching process may be used to form and pattern the at least one dielectric layer820. The at least one dielectric layer820may be formed over and around the at least one interconnect821. The at least one dielectric layer820may include at least one via-hole1020.

Stage4illustrates a state after at least one interconnect822and at least one interconnect832are formed. A plating process and a patterning process may be used to form the at least one interconnect822and the at least one interconnect832. Forming the at least one interconnect822may include forming via interconnects in the at least one via-hole1020of the at least one dielectric layer820. The at least one interconnect822may be coupled to the at least one interconnect821and the at least one interconnect832. The at least one interconnect832includes an interconnect832aand an interconnect832b. A width of the at least one interconnect832may be greater than a width of the at least one interconnect822.

Stage5, as shown inFIG.10C, illustrates a state after a magnetic layer840is formed over the dielectric layer820. A lamination process may be used to form the magnetic layer840. A printing process may be used to form paste of the magnetic layer840over the dielectric layer820.

Stage6illustrates a state after portions of the magnetic layer840are removed. A polishing process and/or a grinding process may be used to remove portions of the magnetic layer840. Removing portions of the magnetic layer840exposes the at least one interconnect832. It is noted that portions of the at least one interconnect832may also be removed through the polishing and/or grinding process.

Stage7, as shown inFIG.10D, illustrates a state after at least one dielectric layer850is formed and patterned. A deposition, a lamination, an exposure, a development and/or an etching process may be used to form and pattern the at least one dielectric layer850. The at least one dielectric layer850may be formed over and around the at least one interconnect832and the magnetic layer840. The at least one dielectric layer850may include at least one via-hole1050.

Stage8illustrates a state after the at least one interconnect851and at least one interconnect861are formed. A plating process and a patterning process may be used to form the at least one interconnect851and the at least one interconnect861. Forming the at least one interconnect851may include forming via interconnects in the at least one via-hole1050of the at least one dielectric layer850. The at least one interconnect851may be coupled to the at least one interconnect832and the at least one interconnect861.

Stage9, as shown inFIG.10E, illustrates a state after the at least one interconnect862is formed. A plating process and a patterning process may be used to form the at least one interconnect862. The at least one interconnect862is formed and coupled to the at least one interconnect861. The at least one interconnect862may include nickel and/or gold.

Stage10illustrates a state after at least one dielectric layer860is formed and patterned. A deposition, a lamination, an exposure, a development and/or an etching process may be used to form and pattern the at least one dielectric layer860. The at least one dielectric layer860may include at least one opening1060, which is configured as an opening in the dielectric layer860and exposes the interconnect861and/or the interconnect862. A solder interconnect may be configured to be coupled to the interconnect862and/or the interconnect861through the opening in the dielectric layer860.

As mentioned above, the above sequence may be performed on a wafer (e.g., silicon wafer) such that several integrated devices are formed at the same time, and the wafer is then singulated to form individual integrated devices comprising a magnetic layer. The above sequence may be fabricated in one facility or at several facilities. For example, when a wafer includes an active portion and an interconnection portion, a portion that includes the magnetic layer may be fabricated over the interconnection portion. The wafer comprising the active portion, the interconnection portion and the magnetic layer may be singulated to form several integrated devices.

Exemplary Flow Diagram of a Method for Fabricating an Integrated Device Comprising a Plate Interconnect and Magnetic Layer

In some implementations, fabricating an integrated device includes several processes.FIG.11illustrates an exemplary flow diagram of a method1100for providing or fabricating an integrated device that includes a plate interconnect and at least one magnetic layer. In some implementations, the method1100ofFIG.11may be used to provide or fabricate the integrated device105, the integrated device801, and/or the integrated device901. The method1100may be implemented on a wafer (e.g., silicon wafer) and then singulated into several integrated devices.

It should be noted that the method1100ofFIG.11may combine one or more processes in order to simplify and/or clarify the method for providing or fabricating an integrated device. In some implementations, the order of the processes may be changed or modified.

The method provides (at1105) a die substrate (e.g.,800). The die substrate800may include silicon (Si). The die substrate800may include a wafer (e.g., silicon wafer). A dielectric layer may be formed and/or located over the die substrate800. A plurality of transistors may be formed in and/or over the die substrate800. A plurality of logic blocks may be formed and/or defined by the plurality of transistors. When fabricating an integrated passive device, the die substrate800may be free of the plurality of transistors (e.g., free of active devices). Stage1ofFIG.10A, illustrates and describes an example of providing a die substrate.

The method forms (at1110) a plurality of interconnects (e.g.,802) over the die substrate, where at least some of the interconnects from the plurality of interconnects (e.g.,802) are configured to operate as an inductor. A plating process and a patterning process may be used to form the at least one interconnect802. The plurality of interconnects802may include the plurality of interconnects832. The plurality of interconnects may be formed in and/or over at least one dielectric layer. The plurality of interconnects802may include a first plurality of plate interconnects210, a plurality of via interconnects220, and a second plurality of plate interconnects230, as described inFIGS.2-5. Thus, forming the plurality of interconnects may include forming a first plurality of plate interconnects, forming a plurality of via interconnects, and forming a second plurality of plate interconnects. In some implementations, one or more plate interconnects may include one or more slots. The plurality of via interconnects220are coupled to the first plurality of plate interconnects210and the second plurality of plate interconnects230.

The method forms (at1115) at least one magnetic layer (e.g.,840). A printing process that provide a magnetic layer as paste may be used to provide and form the at least one magnetic layer840. The at least one magnetic layer840may laterally surround the plurality of interconnects832. The at least one magnetic layer840may laterally surround the plurality of via interconnects220. The at least one magnetic layer840may be located between the first plurality of plate interconnects210and the second plurality of plate interconnects230. The at least one magnetic layer840may be formed in between when the plurality of interconnects are formed and when the at least one dielectric layer are formed. For example, the magnetic layer840may be formed after at least one dielectric layer is formed and a plurality of interconnects are formed. In some implementations, once the magnetic layer840is formed, additional dielectric layers and an additional plurality of interconnects may be formed. Stages5and6ofFIG.10C, illustrate and describe an example of forming a magnetic layer.

The method forms and patterns (at1120) at least one dielectric layer (e.g.,820,850,860) over the die substrate (e.g.,800). A deposition, a lamination, an exposure, a development and/or an etching process may be used to form and pattern the at least one die dielectric layer (e.g.,820,850,860). It is noted that forming the plurality of interconnects and the at least one dielectric layer may be performed iteratively. That is, a dielectric layer may be formed followed by forming a plurality of interconnects, then forming another dielectric layer and then forming another plurality of interconnects. Thus, the method forming (at1110) the plurality of interconnects and forming (at1120) at least one dielectric layer may be performed iteratively for as many layers as required. In some implementations, the dielectric layer is formed and then the plurality of interconnects are formed. Stages2ofFIG.10Athrough Stage4ofFIG.10B, and Stages7ofFIG.10Dthrough Stage11ofFIG.10E, illustrate and describe an example of forming a plurality of interconnects and forming at least one dielectric layer.

Exemplary Flow Diagram of a Method for Fabricating an Integrated Device Comprising a Plate Interconnect and Magnetic Layer

In some implementations, fabricating an integrated device includes several processes.FIG.12illustrates an exemplary flow diagram of a method1200for providing or fabricating an integrated device that includes a plate interconnect and at least one magnetic layer. In some implementations, the method1200ofFIG.12may be used to provide or fabricate the integrated device105. The method1200may be implemented on a wafer (e.g., silicon wafer) and then singulated into several integrated devices.

It should be noted that the method1200ofFIG.12may combine one or more processes in order to simplify and/or clarify the method for providing or fabricating an integrated device. For example, one or more of the processes of the method1200may1200may include one or more of the processes of the method1100. In some implementations, the order of the processes may be changed or modified.

The method provides (at1205) a die substrate (e.g.,800). The die substrate800may include silicon (Si). The die substrate800may include a wafer (e.g., silicon wafer). A plurality of transistors may be formed in and/or over the die substrate800. A plurality of logic blocks may be formed and/or defined by the plurality of transistors. The die substrate800may be part of and/or define an active portion of an integrated device. When fabricating an integrated passive device, the die substrate800may be free of the plurality of transistors (e.g., free of active devices).

The method forms (at1210) a die interconnection portion over the die substrate (e.g.,800), where forming the die interconnection portion includes forming at least one die dielectric layer and forming a plurality of die interconnects. The die interconnection portion may be coupled to the die substrate800. Forming the die interconnection portion may include forming at least one die dielectric layer and forming and patterning at least one die interconnect.

The method forms (at1215) a packaging portion over the die interconnection portion (e.g.,603), where forming the packaging portion includes forming a plurality of interconnects coupled to the plurality of die interconnects, and forming at least one magnetic layer. The packaging portion may be coupled to the die interconnection portion.

Forming the packaging portion may include forming and patterning a plurality of interconnects (e.g.,802), forming a magnetic layer and forming at least one dielectric layer (e.g.,820,850,860). The packaging portion may include an inductor that is defined by at least one interconnect from the plurality of interconnects (e.g.,802). The plurality of interconnects802may include a first plurality of plate interconnects210, a plurality of via interconnects220and a second plurality of plate interconnects230. The at least one magnetic layer includes an insulating layer, a dielectric layer, and/or a non-electrical conducting material. The at least one magnetic layer has a permeability value (e.g., relative permeability value) that is greater than 1.

In some implementations, the magnetic layer may laterally surround and touch one or more interconnects, and at least one dielectric layer may laterally surround and touch the magnetic layer, in a similar manner as described for the integrated device601. In some implementations, the at least one dielectric layer may laterally surround and touch one or more interconnects, and the magnetic layer may laterally surround and touch the at least one dielectric layer, in a similar manner as described for the integrated device701.

The method1200may iteratively repeat the process of (i) forming and patterning interconnects and (ii) forming and grinding a dielectric layer and/or a magnetic layer, for as many layers are required.

As mentioned above, the method1200may be performed on a wafer (e.g., silicon wafer) such that several integrated devices are formed at the same time, and the wafer is then singulated to form individual integrated devices comprising a magnetic layer.

Exemplary Electronic Devices

FIG.13illustrates various electronic devices that may be integrated with any of the aforementioned device, integrated device, integrated circuit (IC) package, integrated circuit (IC) device, semiconductor device, integrated circuit, die, interposer, package, package-on-package (PoP), System in Package (SiP), or System on Chip (SoC). For example, a mobile phone device1302, a laptop computer device1304, a fixed location terminal device1306, a wearable device1308, or automotive vehicle1310may1310may include a device1300as described herein. The device1300may be, for example, any of the devices and/or integrated circuit (IC) packages described herein. The devices1302,1304,1306and1308and the vehicle1310illustrated inFIG.13are merely exemplary. Other electronic devices may also feature the device1300including, but not limited to, a group of devices (e.g., electronic devices) that includes mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of things (IoT) devices, servers, routers, electronic devices implemented in automotive vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

One or more of the components, processes, features, and/or functions illustrated inFIGS.1-9,10A-10E, and/or11-13may be rearranged and/or combined into a single component, process, feature or function or embodied in several components, processes, or functions. Additional elements, components, processes, and/or functions may also be added without departing from the disclosure. It should also be notedFIGS.1-9,10A-10E, and/or11-13and its corresponding description in the present disclosure is not limited to dies and/or ICs. In some implementations,FIGS.1-9,10A-10E, and/or11-13and its corresponding description may be used to manufacture, create, provide, and/or produce devices and/or integrated devices. In some implementations, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package-on-package (PoP) device, a heat dissipating device and/or an interposer.

It is noted that the figures in the disclosure may represent actual representations and/or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and/or transistors. In some instances, the figures may not be to scale. In some instances, for purpose of clarity, not all components and/or parts may be shown. In some instances, the position, the location, the sizes, and/or the shapes of various parts and/or components in the figures may be exemplary. In some implementations, various components and/or parts in the figures may be optional.

The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term “coupled” is used herein to refer to the direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C may still be considered coupled to one another-even if they do not directly physically touch each other. The term “electrically coupled” may mean that two objects are directly or indirectly coupled together such that an electrical current (e.g., signal, power, ground) may travel between the two objects. Two objects that are electrically coupled may or may not have an electrical current traveling between the two objects. The use of the terms “first”, “second”, “third” and “fourth” (and/or anything above fourth) is arbitrary. Any of the components described may be the first component, the second component, the third component or the fourth component. For example, a component that is referred to a second component, may be the first component, the second component, the third component or the fourth component. The term “encapsulating” means that the object may partially encapsulate or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component that is located on top may be located over a component that is located on a bottom. A top component may be considered a bottom component, and vice versa. As described in the disclosure, a first component that is located “over” a second component may mean that the first component is located above or below the second component, depending on how a bottom or top is arbitrarily defined. In another example, a first component may be located over (e.g., above) a first surface of the second component, and a third component may be located over (e.g., below) a second surface of the second component, where the second surface is opposite to the first surface. It is further noted that the term “over” as used in the present application in the context of one component located over another component, may be used to mean a component that is on another component and/or in another component (e.g., on a surface of a component or embedded in a component). Thus, for example, a first component that is over the second component may mean that (1) the first component is over the second component, but not directly touching the second component, (2) the first component is on (e.g., on a surface of) the second component, and/or (3) the first component is in (e.g., embedded in) the second component. A first component that is located “in” a second component may be partially located in the second component or completely located in the second component. The term “about ‘value X’”, or “approximately value X”, as used in the disclosure means within 10 percent of the ‘value X’. For example, a value of about 1 or approximately 1, would mean a value in a range of 0.9-1.1.

In some implementations, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements and/or components. In some implementations, an interconnect may include a trace, a via, a pad, a pillar, a metallization layer, a redistribution layer, and/or an under bump metallization (UBM) layer/interconnect. In some implementations, an interconnect may include an electrically conductive material that may be configured to provide an electrical path for a signal (e.g., a data signal), ground and/or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and/or sequences for forming the interconnects. In some implementations, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a sputtering process, a spray coating, and/or a plating process may be used to form the interconnects.

In the following, further examples are described to facilitate the understanding of the disclosure.

Aspect 1: A device comprising a die substrate, a plurality of interconnects, at least one magnetic layer, and at least one dielectric layer located over the die substrate. The plurality of interconnects are located over the die substrate. The plurality of interconnects comprise: a first plurality of plate interconnects; a second plurality of plate interconnects; and a plurality of via interconnects coupled to the first plurality of plate interconnects and the second plurality of plate interconnects. The first plurality of plate interconnects, the plurality of via interconnects, and the second plurality of plate interconnects are configured to operate as an inductor. The at least one magnetic layer surrounds at least part of the plurality of via interconnects.

Aspect 2: The device of aspect 1, wherein the plurality of interconnects comprises a first via interconnect and a second via interconnect, and wherein the at least one magnetic layer laterally surrounds and touches (i) the first via interconnect, and (ii) the second via interconnect.

Aspect 3: The device of aspects 1 through 2, wherein a plate interconnect from the first plurality of plate interconnects includes a first width, wherein a plate interconnect from the second plurality of plate interconnects includes a second width, wherein a via interconnect from the plurality of via interconnects includes a via width, and wherein the first width and the second width are each at least twice as wide as the via width.

Aspect 4: The device of aspect 3, wherein the first plurality of plate interconnects are aligned in a first direction, wherein the second plurality of plate interconnects are aligned in a second direction, and wherein an electrical path through the inductor includes a first plate interconnect from the first plurality of plate interconnects, a first plurality of via interconnects from the plurality of via interconnects, a first plate interconnect from the second plurality of plate interconnects, a second plurality of via interconnects from the plurality of via interconnects, a second plate interconnect from the first plurality of plate interconnects, a third plurality of via interconnects from the plurality of via interconnects, and a second plate interconnect from the second plurality of plate interconnects.

Aspect 5: The device of aspect 4, wherein the first plate interconnect from the first plurality of plate interconnects includes a first slot, and wherein the second plate interconnect from the second plurality of plate interconnects includes a second slot.

Aspect 6: The device of aspects 1 through 5, further comprising a plurality of transistors located in the die substrate.

Aspect 7: The device of aspects 1 through 6, wherein the at least one magnetic layer includes an insulating layer and/or a dielectric layer.

Aspect 8: The device of aspects 1 through 7, wherein the at least one magnetic layer includes a non-electrical conducting material.

Aspect 9: The device of aspects 1 through 8, wherein the at least one magnetic layer has a relative permeability value that is greater than 1.

Aspect 10: The device of aspects 1 through 10, wherein the device is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.

Aspect 11: A device comprising a first integrated device, a second integrated device and a third integrated device. The first integrated device comprises a die substrate, a plurality of interconnects located over the die substrate. The plurality of interconnects comprise: a first plurality of plate interconnects; a second plurality of plate interconnects; and a plurality of via interconnects coupled to the first plurality of plate interconnects and the second plurality of plate interconnects. The first plurality of plate interconnects, the plurality of via interconnects and the second plurality of plate interconnects are configured to operate as an inductor. The first integrated device includes at least one magnetic layer that surrounds at least part of the plurality of via interconnects, and at least one dielectric layer located over the die substrate. The second integrated device is configured as a power management integrated device, wherein the second integrated device is configured to be electrically coupled to the first integrated device through a first electrical path. The third integrated device is configured to be electrically coupled to the first integrated device through a second electrical path.

Aspect 12: The device of aspect 11, wherein the plurality of interconnects comprises a first via interconnect and a second via interconnect, and wherein the at least one magnetic layer laterally surrounds and touches (i) the first via interconnect, and (ii) the second via interconnect.

Aspect 13: The device of aspects 11 through 12, wherein a plate interconnect from the first plurality of plate interconnects includes a first width, wherein a plate interconnect from the second plurality of plate interconnects includes a second width, wherein a via interconnect from the plurality of via interconnects includes a via width, and wherein the first width and the second width are each at least twice as wide as the via width.

Aspect 14: The device of aspect 13, wherein the first plurality of plate interconnects are aligned in a first direction, wherein the second plurality of plate interconnects are aligned in a second direction, and wherein an electrical path through the inductor includes a first plate interconnect from the first plurality of plate interconnects, a first plurality of via interconnects from the plurality of via interconnects, a first plate interconnect from the second plurality of plate interconnects, a second plurality of via interconnects from the plurality of via interconnects, a second plate interconnect from the first plurality of plate interconnects, a third plurality of via interconnects from the plurality of via interconnects, and a second plate interconnect from the second plurality of plate interconnects.

Aspect 15: The device of aspect 14, wherein the first plate interconnect from the first plurality of plate interconnects includes a first slot, and wherein the second plate interconnect from the second plurality of plate interconnects includes a second slot.

Aspect 16: The device of aspects 11 through 15, further comprising a plurality of transistors located in the die substrate.

Aspect 17: The device of aspects 11 through 16, wherein the at least one magnetic layer includes an insulating layer, a dielectric layer and/or a non-electrical conducting material, and wherein the at least one magnetic layer has a relative permeability value that is greater than 1.

Aspect 18: The device of aspects 11 through 17, wherein the first electrical path is configured as an electrical path for power having a first voltage, and wherein the second electrical path is configured as an electrical path for power having a second voltage that is different than the first voltage.

Aspect 19: The device of aspects 11 through 18, wherein the first integrated device and the second integrated device are part of a power distribution network (PDN).

Aspect 20: The device of aspect 11 through 19, wherein the device is selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an internet of things (IoT) device, and a device in an automotive vehicle.

Aspect 21: A method provides a die substrate. The method forms a plurality of interconnects over the die substrate, wherein forming the plurality of interconnects comprises: forming a first plurality of plate interconnects; forming a plurality of via interconnects that coupled are coupled to the first plurality of plate interconnects; and forming a second plurality of plate interconnects that are coupled to the plurality of via interconnects. The first plurality of plate interconnects, the plurality of via interconnects and the second plurality of plate interconnects are configured to operate as an inductor. The method forms at least one magnetic layer that surrounds at least part of the plurality of via interconnects. The method forms at least one dielectric layer over the die substrate.

Aspect 22: The method of aspect 21, wherein the at least one magnetic layer is formed after the plurality of via interconnects are formed, and wherein forming the at least one dielectric layer comprises: forming a first dielectric layer before forming the plurality of via interconnects; and forming a second dielectric layer after forming the at least one magnetic layer.

Aspect 23: The method of aspects 21 through 22, wherein a plate interconnect from the first plurality of plate interconnects includes a first width, wherein a plate interconnect from the second plurality of plate interconnects includes a second width, wherein a via interconnect from the plurality of via interconnects includes a via width, and wherein the first width and the second width are each at least twice as wide as the via width.

Aspect 24: The method of aspect 23, wherein the first plurality of plate interconnects are aligned in a first direction, wherein the second plurality of plate interconnects are aligned in a second direction, and wherein an electrical path through the inductor includes a first plate interconnect from the first plurality of plate interconnects, a first plurality of via interconnects from the plurality of via interconnects, a first plate interconnect from the second plurality of plate interconnects, a second plurality of via interconnects from the plurality of via interconnects, a second plate interconnect from the first plurality of plate interconnects, a third plurality of via interconnects from the plurality of via interconnects, and a second plate interconnect from the second plurality of plate interconnects.

Aspect 25: The method of aspect 24, wherein the first plate interconnect from the first plurality of plate interconnects includes a first slot, and wherein the second plate interconnect from the second plurality of plate interconnects includes a second slot.

Aspect 26: The method of aspects 21 through 25, further comprising a plurality of transistors located in the die substrate.