SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

A semiconductor device may include a gate structure including gate lines and insulating layers that are alternately stacked; a channel structure extending through the gate structure; a dummy gate structure including stacked dummy gate lines; a dummy channel structure extending through the dummy gate structure; and an isolation insulating structure including horizontal portions stacked between the gate structure and the dummy gate structure and vertical portions extending through the horizontal portions.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0094449 filed on Jul. 20, 2023, which is incorporated herein by reference in its entirety.

BACKGROUND

1. Technical Field

Embodiments of the present disclosure relate to an electronic device, and more particularly, to a semiconductor device and a manufacturing method of the semiconductor device.

2. Related Art

The degree of integration of a semiconductor device is mainly determined by the area occupied by a unit memory cell. Recently, as the improvement in the degree of integration of a semiconductor device for forming memory cells in a single layer on a substrate reaches a limit, a three-dimensional semiconductor device for stacking memory cells on a substrate has been proposed. Furthermore, to improve the operational reliability of such a semiconductor device, various structures and manufacturing methods have been developed.

SUMMARY

In an embodiment, a semiconductor device may include: a gate structure including gate lines and insulating layers that are alternately stacked; a channel structure extending through the gate structure; a dummy gate structure including stacked dummy gate lines; a dummy channel structure extending through the dummy gate structure; and an isolation insulating structure including horizontal portions stacked between the gate structure and the dummy gate structure and vertical portions extending through the horizontal portions.

In an embodiment, a semiconductor device may include: a gate structure including stacked gate lines; a channel structure extending through the gate structure; contact plugs extending through the gate structure and connected to the gate lines, respectively; a dummy gate structure adjacent to the gate structure in a first direction and including stacked dummy gate lines; a dummy channel structure extending through the dummy gate structure; and an isolation insulating structure located between the gate structure and the dummy gate structure, extending in a second direction intersecting the first direction, and including dummy contact plugs arranged in the second direction.

In an embodiment, a manufacturing method of a semiconductor device may include: forming a first stack including first material layers and second material layers that are alternately stacked; forming dummy holes in the first stack; forming a second stack on the first stack, the second stack including third material layers and fourth material layers that are alternately stacked; forming a dummy contact hole in the second stack, the dummy contact hole being connected to the dummy holes; forming an isolation trench by etching the first material layers and the third material layers through the dummy contact hole and the dummy holes; and forming an isolation insulating structure in the isolation trench.

In an embodiment, a manufacturing method of a semiconductor device may include: forming a first stack including first material layers and second material layers that are alternately stacked; forming a dummy hole in the first stack; forming a second stack on the first stack, the second stack including third material layers and fourth material layers that are alternately stacked; forming a dummy contact hole in the second stack, the dummy contact hole being connected to the dummy hole and having a greater width than the dummy hole; forming contact holes in the second stack, the contact holes exposing the first material layers and the third material layers, respectively; forming an isolation trench by etching the first material layers and the third material layers through the dummy contact hole and the dummy hole; forming an isolation insulating structure in the isolation trench; forming a dummy contact plug in the isolation insulating structure; and forming contact plugs in the contact holes.

DETAILED DESCRIPTION

Various embodiments of the present disclosure are directed to a semiconductor device having a stable structure and improved characteristics and a manufacturing method of the semiconductor device.

By stacking memory cells in three dimensions, it is possible to improve the degree of integration of a semiconductor device. It is also possible to provide a semiconductor device having a stable structure and improved reliability.

Hereafter, embodiments in accordance with the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

FIGS.1A and1Bare diagrams illustrating the structure of a semiconductor device in accordance with an embodiment of the present disclosure.FIG.1Ais a plan view, andFIG.1Bis a cross-sectional view taken along line A-A′ ofFIG.1A.

Referring toFIGS.1A and1B, the semiconductor device may include a gate structure GST, a channel structure CH, a dummy gate structure D_GST, a dummy channel structure D_CH, and an isolation insulating structure IS. The semiconductor device may further include at least one of a slit structure SLS, a contact plug CP, a chip guard structure CG, a first insulating spacer SP1, and a second insulating spacer SP2.

The semiconductor device may be a chip, and may include a guard region GR defined at an edge of the chip. A plurality of planes may be located in the guard region GR. Each plane may include a plurality of memory blocks MB. Each memory block MB may include a block center region BCR and a block edge region BER. The block edge region BER may be located between the block center region BCR and the guard region GR. The gate structure GST may be located in the block center region BCR, and the dummy gate structure D_GST may be located in the block edge region BER and guard region GR.

The gate structure GST may include gate lines11G and insulating layers12that are alternately stacked. The gate lines11G may be word lines, source select lines, drain select lines, and the like. The gate lines11G may each include a conductive material such as, for example, polysilicon or metal. The insulating layers12insulate the stacked gate lines11G from each other. The insulating layers12may each include an insulating material such as, for example, an oxide, or a nitride. In some embodiments, the insulating layers12may each include a gap.

The gate structure GST may include a cell region CR and a contact region CTR as illustrated inFIG.1B. The cell region CR may be a region where memory cells are located. The contact region CTR may be a region where an interconnection structure such a contact plug and a line are located. The interconnection structure may provide a path for transmitting a bias for driving the stacked memory cells.

The channel structure CH may extend through the gate structure GST. The channel structure CH may be located in the cell region CR of the gate structure GST. The channel structure CH may include at least one of a channel layer13, a memory layer14, and an insulating core15. The memory layer14may include a floating gate, polysilicon, a charge trap material, nitride, a variable resistance material, or the like. For reference, some of the channel structures CH penetrating through the gate structure GST may be dummy channel structures. According to an example, channel structures CH located adjacent to the contact region CTR among the channel structures CH may be dummy channel structures. Channel structures CH located adjacent to the dummy gate structure D_GST among the channel structures CH may be dummy channel structures.

The contact plug CP may extend through the gate structure GST, and may be electrically connected to the gate lines11G. The contact plug CP may be located in the contact region CTR of the gate structure GST. The contact plug CP may include a conductive plug16and a barrier layer17surrounding the conductive plug16. The conductive plug16may include a metal such as, for example, tungsten or molybdenum. The barrier layer17may include a metal nitride such as, for example, a titanium nitride. The first insulating spacer SP1may surround the sidewalls of the contact plug CP. The first insulating spacer SP1may include an insulating material such as, for example, an oxide or a nitride.

The dummy gate structure D_GST may include stacked dummy gate lines11D. The dummy gate lines11D may be located at levels corresponding to the gate lines11G. The insulating layers12may extend between the dummy gate lines11D, and the dummy gate lines11D and the insulating layers12may be alternately stacked. The dummy gate lines11D may each include a conductive material such as, for example, polysilicon or metal. The gate structure GST and the dummy gate structure D_GST may be adjacent to each other in a first direction I.

The dummy gate structure D_GST may include a guard region GR and an edge region ER. The edge region ER may be located between the guard region GR and the cell region CR. The dummy channel structure D_CH may be located in the edge region ER. The chip guard structure CG may be located in the guard region GR.

At least a portion of the dummy gate structure D_GST may include sacrificial layers instead of the dummy gate lines11D. For example, the sacrificial layers may be layers remaining without being replaced by the dummy gate lines11D in a manufacturing process. According to an example, the sacrificial layers and the insulating layers12may be alternately stacked in the guard region GR.

The dummy channel structure D_CH may extend through the edge region ER of the dummy gate structure D_GST. The dummy channel structure D_CH may have a structure similar to that of the channel structure CH. The dummy channel structure D_CH may include at least one of a dummy channel layer13D, a dummy memory layer14D, and a dummy insulating core15D. The dummy memory layer14D may include a floating gate, polysilicon, a charge trap material, nitride, a variable resistance material, or the like.

The chip guard structure CG may be located at the edge of the chip. The chip guard structure CG may extend through the guard region GR of the dummy gate structure D_GST. The chip guard structure CG may include a conductive material such as, for example, polysilicon or metal. The second insulating spacer SP2may surround sidewalls of the chip guard structure CG.

The isolation insulating structure IS may be located between the gate structure GST and the dummy gate structure D_GST. The isolation insulating structure IS may extend in a second direction II intersecting the first direction I, and may electrically isolate the gate structure GST and the dummy gate structure D_GST from each other. A plurality of isolation insulating structures IS may be arranged along the second direction II, and may be isolated from each other.

The isolation insulating structure IS may include an isolation layer6. The isolation layer6may include horizontal portions HP and vertical portions VP. The horizontal portions HP may be stacked between the gate structure GST and the dummy gate structure D_GST. The horizontal portions HP may be located to correspond to the gate lines11G and the dummy gate lines11D, and may be located between the gate lines11G and the dummy gate lines11D. The insulating layers12may extend between the horizontal portions HP, and the horizontal portions HP and the insulating layers12may be alternately stacked. The vertical portions VP may extend through the horizontal portions HP. The isolation layer6may include an insulating material such as, for example, an oxide or a nitride.

The isolation insulating structure IS may include at least one dummy contact plug D_CP. The dummy contact plug D_CP may be located inside the isolation layer6, and the isolation layer6may surround the dummy contact plug D_CP. The dummy contact plugs D_CP may be arranged in the second direction II, and the isolation layers6may extend in the second direction II while surrounding sidewalls of the dummy contact plugs D_CP.

The dummy contact plug D_CP may have a structure similar to that of the contact plug CP. The dummy contact plug D_CP may include a conductive plug18and a barrier layer19surrounding the conductive plug18. The conductive plug18may include a metal such as, for example, tungsten or molybdenum. The barrier layer19may include a metal nitride such as, for example, a titanium nitride. The dummy contact plug D_CP may be located on the horizontal portions HP. The vertical portions VP may extend along sidewalls of the dummy contact plug D_CP.

The slit structure SLS may be located between the gate structures GST. The slit structure SLS may be located between memory blocks MB adjacent to each other in the second direction II, and the memory blocks MB adjacent to each other may be electrically isolated from each other by the slit structure SLS. The slit structure SLS may extend from the block center region BCR to the block edge region BER. It is also possible that the slit structure SLS extends to the guard region GR. The slit structure SLS may be formed in a slit in a manufacturing process, and the slit may be used as a passage for replacing sacrificial layers with the gate lines11G or the dummy gate lines11D. The slit structure SLS may extend along the first direction I, and may insulate gate structures GST adjacent to each other in the second direction II from each other. The slit structure SLS may extend between the isolation insulating structures IS and between the dummy gate structures D_GST.

The slit structure SLS may include at least one of an insulating material, a conductive material, and a semiconductor material. According to an example, the slit structure SLS may include an insulating material such as, for example, an oxide or a nitride. The slit structure SLS may include a semiconductor material such as, for example, a silicon or a germanium. In an embodiment, the slit structure SLS may include a source contact structure therein, and the source contact structure may be electrically connected to a source line.

According to the structure described above, a pattern density at which the dummy channel structures D_CH are disposed in the edge region ER and a pattern density at which the channel structures CH are disposed in the cell region CR may be substantially the same as or similar to each other. Accordingly, it is possible to reduce bending of a stack, a slit, and the like, in a region having a relatively low pattern density in the manufacturing process. A shape of the slit structure SLS may not be changed to compensate for a pattern density difference, and the slit structure SLS may have a uniform width. In addition, by locating the gate structure GST in the block center region BCR and the dummy gate structure D_GST in the block edge region BER, it is possible to reduce the occurrence of wafer warpage. Wafer warpage refers to the deformation or distortion of the wafer.

FIGS.2A,3A,4A,5A, and6AandFIGS.2B,3B,4B,5B, and6Bare diagrams for describing a manufacturing method of a semiconductor device in accordance with an embodiment of the present disclosure. Hereinafter, the content overlapping with the previously described content may be omitted.

Referring toFIGS.2A and2B, a first stack ST1including first material layers21and second material layers22that are alternately stacked may be formed. According to an example, the first stack ST1may be formed in a block center region BCR and a block edge region BER of a memory block. The first material layers21may be used to form gate lines. The first material layers21may each include a sacrificial material such as nitride or a conductive material such as, for example, polysilicon or metal. The second material layers22may each include an insulating material such as, for example, an oxide or a nitride.

Subsequently, first dummy holes DH1may be formed in the first stack ST1. The first dummy holes DH1may be located in the block edge region BER. First channel holes CHH1may be formed in the first stack ST1. The first channel holes CHH1may be located in the block center region BCR. When the first dummy holes DH1are formed, the first channel holes CHH1may be formed. The first dummy holes DH1and the first channel holes CHH1may be formed at the same time. The first dummy holes DH1and the first channel holes CHH1may be formed with a uniform pattern density in the block edge region BER and the block center region BCR, respectively.

Subsequently, first sacrificial layers23A may be formed in the first dummy holes DH1. The first sacrificial layers23A may each include a material having a high etching selectivity with respect to the first material layers21and the second material layers22. First sacrificial layers23B may be formed in the first channel holes CHH1. The first sacrificial layers23B may each include a material having a high etching selectivity with respect to the first material layers21and the second material layers22. When the first sacrificial layers23A are formed, the first sacrificial layers23B may be formed.

Referring toFIGS.3A and3B, a second stack ST2may be formed on the first stack ST1. The second stack ST2may include third material layers31and fourth material layers32that are alternately stacked. According to an example, the second stack ST2may be formed in the block center region BCR and the block edge region BER of the memory block. The third material layers31may be used to form gate lines. The third material layers31may each include a sacrificial material such as nitride or a conductive material such as, for example, polysilicon or metal. The fourth material layers32may each include an insulating material such as, for example, an oxide or a nitride.

Subsequently, second dummy holes DH2may be formed in the second stack ST2. The second dummy holes DH2may be located in the block edge region BER, and may be connected to the first dummy holes DH1. The number of second dummy holes DH2may be the same as or different from the number of first dummy holes DH1. According to an example, the number of second dummy holes DH2may be smaller than the number of first dummy holes DH1, and some of the first dummy holes DH1may not be connected to the second dummy holes DH2. The second dummy holes DH2may not be formed in a region where a dummy contact hole is to be formed in a subsequent process. The second dummy holes DH2may not be formed in a portion of the block edge region BER adjacent to the block center region BCR.

Second channel holes CHH2may be formed in the second stack ST2. The second channel holes CHH2may be located in the block center region BCR, and may be connected to the first channel holes CHH1. When the second dummy holes DH2are formed, the second channel holes CHH2may be formed.

Referring toFIGS.4A and4B, the first sacrificial layers23A may be removed through the second dummy holes DH2. Through this, the first dummy holes DH1may be reopened. The first sacrificial layers23B may be removed through the second channel holes CHH2. Through this, the first channel holes CHH1may be reopened. Subsequently, channel structures CH may be formed.

According to an example, the channel structures CH may be formed in the first channel holes CHH1and the second channel holes CHH2connected to each other. The channel structure CH may include at least one of a channel layer43, a memory layer44, and an insulating core45. Dummy channel structures D_CH may be formed. According to an example, the dummy channel structures D_CH may be formed in the first dummy holes DH1and the second dummy holes DH2connected to each other. The dummy channel structure D_CH may include at least one of a dummy channel layer43D, a dummy memory layer44D, and a dummy insulating core45D. When the channel structures CH are formed, the dummy channel structures D_CH may be formed. Because the second dummy holes DH2are not formed in a region where a dummy contact hole D_CTH is to be formed in a subsequent process, the first sacrificial layers23A may remain in the first dummy holes DH1of the corresponding region. The dummy channel structures D_CH may not be formed in the corresponding region. Subsequently, the fourth material layer32may be additionally formed to cover the channel structures CH.

Subsequently, the dummy contact hole D_CTH may be formed in the second stack ST2. According to an example, a mask pattern34may be formed on the second stack ST2, and the dummy contact hole D_CTH may be formed by etching the second stack ST2using the mask pattern34as an etching barrier.

In a plan view, the dummy contact hole D_CTH may have a greater size than the first dummy hole DH1. According to an example, the first dummy hole DH1may have a first width W1, and the dummy contact hole D_CTH may have a second width W2that is greater than the first width W1. The dummy contact hole D_CTH may be connected to a plurality of first dummy holes DH1. The dummy contact hole D_CTH may be located in the block edge region BER, and may be located between the dummy channel structures D_CH and the channel structures CH. The first dummy holes DH1and the first sacrificial layers23A may be exposed through the dummy contact hole D_CTH. Referring toFIGS.5A and5B, the first sacrificial layers23A may be removed through the dummy contact hole D_CTH. Through this, the first dummy holes DH1may be reopened. Subsequently, the first material layers21and the third material layers31exposed through the first dummy holes DH1and the dummy contact hole D_CTH may be etched. The first material layers21between adjacent first dummy holes DH1may be removed, and the adjacent first dummy holes DH1may be connected to each other. Irregularities may be formed on sidewalls of the dummy contact holes D_CTH. Through this, an isolation trench IST may be formed.

When the dummy channel structures D_CH were formed in a region where the isolation trench IST is to be formed, the dummy channel structures D_CH should be removed to form the isolation trench IST. According to an embodiment of the present disclosure, because the second dummy holes DH2are not formed in the region where the isolation trench IST is to be formed, the dummy channel structures D_CH may not be formed in the corresponding region. Accordingly, it is possible to form the isolation trench IST without removing the dummy channel structures D_CH.

The first material layers21formed in the block center region BCR and the first material layers21formed in the block edge region BER may be isolated from each other by the isolation trench IST. The third material layers31formed in the block center region BCR and the third material layers31formed in the block edge region BER may be isolated from each other by the isolation trench IST. The first material layers21and the third material layers31may be selectively etched, and the second material layers22and the fourth material layers32may maintain a shape in which they extend from the block center region BCR to the block edge region BER.

Referring toFIGS.6A and6B, an isolation insulating structure IS may be formed in the isolation trench IST. First, an isolation layer36may be formed in the isolation trench IST. The isolation layer36may include a material having a high etching selectivity with respect to the first material layers21and the third material layers31. The isolation layer36may be formed by depositing an insulating material such as, for example, an oxide or a nitride. The isolation layer36may be formed at a thickness enough to fill the first dummy holes DH1, and may be formed along an inner surface of the dummy contact hole D_CTH. A central region of the dummy contact hole D_CTH may not be filled with the isolation layer36, and may be opened. Subsequently, a dummy contact plug D_CP may be formed in the isolation layer36. The dummy contact plug D_CP may be located in the dummy contact hole D_CTH. According to an example, a barrier layer39may be formed in the isolation layer36, and a conductive plug38may be formed to gap fill the space defined by the barrier layer39.

The first material layers21and the third material layers31may be replaced with fifth material layers41. A replacement process may be performed through a slit. The fifth material layers41may each include metal such as, for example, tungsten or molybdenum, and may be gate lines41G or dummy gate lines41D. According to an example, the first material layers21and the third material layers31may be selectively etched, and the fifth material layers41may be respectively formed in regions where the first material layers21and the third material layers31are removed.

Through this, a gate structure GST located in the block center region BCR and a dummy gate structure D_GST located in the block edge region BER may be formed. The gate structure GST may include the gate lines41G and the second material layers22that are alternately stacked and the gate lines41G and the fourth material layers32that are alternately stacked. The dummy gate structure D_GST may include the dummy gate lines41D and the second material layers22that are alternately stacked and the dummy gate lines41D and the fourth material layers32that are alternately stacked.

According to the manufacturing method described above, when the channel structures CH are formed in the block center region BCR, the dummy channel structures D_CH may be formed in the block edge region BER. By making the pattern densities of the block center region BCR and the block edge region BER uniform, it is possible to reduce bending of an end of the stack ST when the first material layers21and the third material layers31are replaced with the fifth material layers41. In addition, the isolation insulating structure IS may be formed using a process of forming the channel structure CH.

The exposed first material layers21and third material layers31around the first dummy holes DH1and the dummy contact hole D_CTH may be replaced with the isolation layer36. Through this, the first material layers21and the third material layers31may be removed in advance in a portion of the block edge region BER adjacent to the block center region BCR. Accordingly, the dummy gate structure D_GST and the gate structure GST may be isolated from each other by the isolation insulating structure IS.

FIGS.7A,8A,9A,10A,11A,12A,13A,14A,15A,16A, and17AandFIGS.7B,8B,9B,10B,11B,12B,13B,14B,15B,16B, and17Bare diagrams for describing a manufacturing method of a semiconductor device in accordance with an embodiment of the present disclosure. Hereinafter, the content overlapping with the previously described content may be omitted.

Referring toFIGS.7A and7B, a first stack ST1may be formed including alternating first and second material layers51and52. According to an example, the first stack ST1may be formed in a center region and an edge region of a memory block. The first stack ST1may include a cell region CR, a contact region CTR, and an edge region ER arranged along the first direction I (SeeFIG.8A). The edge region ER may be an end or edge region of the first stack ST1. The cell region CR may be located between the edge region ER and the contact region CTR.

Subsequently, first dummy holes DH1may be formed in the first stack ST1. The first dummy holes DH1may be located in the edge region ER. First channel holes CHH1may be formed in the first stack ST1. The first channel holes CHH1may be located in the cell region CR. When the first dummy holes DH1are formed, the first channel holes CHH1may be formed. The first dummy holes DH1and the first channel holes CHH1may be formed at the same time. The first dummy holes DH1and the first channel holes CHH1may be formed with a uniform pattern density in the edge region ER and the cell region CR, respectively.

Subsequently, first sacrificial layers53A may be formed in the first dummy holes DH1. First sacrificial layers53B may be formed in the first channel holes CHH1. When the first sacrificial layers53A are formed, the first sacrificial layers53B may be formed. The first sacrificial layers53A and the first sacrificial layers53B may be formed at the same time.

Referring toFIGS.8A and8B, a second stack ST2may be formed on the first stack ST1. The second stack ST2may include third material layers61and fourth material layers62that are alternately stacked. The second stack ST2may include a cell region CR, a contact region CTR, and an edge region ER. The edge region ER may be an end of the second stack ST2. The cell region CR may be located between the edge region ER and the contact region CTR.

Subsequently, second dummy holes DH2may be formed in the second stack ST2. The second dummy holes DH2may be located in the edge region ER, and may be connected to the first dummy holes DH1. The second dummy holes DH2may not be formed in a portion of the edge region ER adjacent to the cell region CR. Second channel holes CHH2may be formed in the second stack ST2. The second channel holes CHH2may be located in the cell region CR, and may be connected to the first channel holes CHH1. When the second dummy holes DH2are formed, the second channel holes CHH2may be formed.

Subsequently, second sacrificial layers63A may be formed in the second dummy holes DH2. The second sacrificial layers63A may each include a material having a high etching selectivity with respect to the third material layers61and the fourth material layers62. Second sacrificial layers63B may be formed in the second channel holes CHH2. The second sacrificial layers63B may each include a material having a high etching selectivity with respect to the third material layers61and the fourth material layers62. When the second sacrificial layers63A are formed, the second sacrificial layers63B may be formed.

Referring toFIGS.9A and9B, the first dummy holes DH1and the second dummy holes DH2may be reopened by removing the second sacrificial layers63A and the first sacrificial layers53A. The first channel holes CHH1and the second channel holes CHH2may be reopened by removing the second sacrificial layers63B and the first sacrificial layers53B. When the first dummy holes DH1and the second dummy holes DH2are reopened, the first channel holes CHH1and the second channel holes CHH2may be reopened.

Subsequently, dummy channel structures D_CH may be formed in the first dummy holes DH1and the second dummy holes DH2connected to each other. Channel structures CH may be formed in the first channel holes CHH1and the second channel holes CHH2connected to each other. The channel structure CH may include at least one of a channel layer64, a memory layer65, and an insulating core66. The dummy channel structure D_CH may include at least one of a dummy channel layer64D, a dummy memory layer65D, and a dummy insulating core66D. When the channel structures CH are formed, the dummy channel structures D_CH may be formed.

Subsequently, a hard mask pattern67may be formed on the second stack ST2. According to an example, the hard mask pattern67may be formed by forming a hard mask layer on the second stack ST2and etching the hard mask layer using a first mask pattern71as an etching barrier. The hard mask pattern67may include openings OPA corresponding to locations where contact plugs are to be formed in a subsequent process and openings OPB corresponding to locations where dummy contact plugs are to be formed in the subsequent process. The second stack ST2may be exposed through the openings OPA and OPB. In a process of forming the hard mask pattern67, the second stack ST2may be partially etched, and preliminary contact holes PHA connected to the openings OPA and preliminary contact holes PHB connected to the openings OPB may be formed. The hard mask pattern67may include polysilicon, and the first mask pattern71may include a photoresist.

Referring toFIGS.10A and10B, a sacrificial layer68may be formed on the hard mask pattern67, and a second mask pattern72may be formed on the sacrificial layer68. The sacrificial layer68may be formed in the preliminary contact holes PHA and PHB, and may include voids V respectively located in the preliminary contact holes PHA and PHB. The sacrificial layer68may include amorphous carbon, and the second mask pattern72may include a photoresist.

Referring toFIGS.11A and11B, the sacrificial layer68may be etched using the second mask pattern72as an etching barrier. Through this, at least one of the preliminary contact holes PHA may be exposed, and the preliminary contact holes PHB may be exposed. Subsequently, the second stack ST2may be etched using the second mask pattern72and the hard mask pattern67as etching barriers. Through this, the exposed preliminary contact holes PHA and PHB may extend into the second stack ST2. Contact holes CTH may be formed in the contact region CTR, and dummy contact holes D_CTH may be formed in the edge region ER. The contact holes CTH and the dummy contact holes D_CTH may have substantially the same depth.

Referring toFIGS.12A and12B, the second mask pattern72may be reduced. By etching the second mask pattern72to expand openings, the number of exposed preliminary contact holes PHA may be increased. Subsequently, the sacrificial layer68may be etched using the reduced second mask pattern72A as an etching barrier. Subsequently, the second stack ST2may be etched using the second mask pattern72A and the hard mask pattern67as etching barriers. Through this, the previously formed contact holes CTH and dummy contact holes D_CTH may extend into the second stack ST2. The newly exposed preliminary contact holes PHA may extend into the second stack ST2.

A process of reducing the second mask pattern72A and etching the sacrificial layer68and the second stack ST2may be repeatedly performed. Through this, contact holes CTH respectively exposing the third material layers61included in the second stack ST2may be formed. At least one of the contact holes CTH may extend into the first stack ST1, and may expose at least one of the first material layers51. In addition, a dummy contact hole D_CTH exposing the first sacrificial layers53A may be formed. When the contact holes CTH are formed, the dummy contact hole D_CTH may be formed. As the contact holes CTH extend into the second stack ST2, the dummy contact hole D_CTH may also extend into the second stack ST2. When the contact hole CTH extends into the first stack ST1, the dummy contact hole D_CTH may also extend into the first stack ST1. A contact hole CTH having the greatest depth among the contact holes CTH and the dummy contact hole D_CTH may have substantially the same depth. The dummy contact hole D_CTH may expose the first sacrificial layers53A, and may be connected to the first dummy holes DH1.

For reference, as the process of reducing the second mask pattern72A and etching the sacrificial layer68and the second stack ST2is repeatedly performed, an upper surface of the hard mask pattern67may be etched. Irregularities, stair structures, or the like, may be formed on the upper surface of the hard mask pattern67.

Referring toFIGS.13A and13B, the second mask pattern72and the sacrificial layer68may be removed. Subsequently, the first sacrificial layers53A in the first dummy holes DH1may be removed through the dummy contact hole D_CTH. For reference, when the second mask pattern72or the sacrificial layer68is removed, the first sacrificial layers53A may be removed.

Subsequently, a third mask pattern73may be formed. The third mask pattern73may cover the edge region ER and the cell region CR, and may expose a portion of the contact region CTR. The third mask pattern73may cover some of the contact holes CTH and expose the other contact holes CTH. The third mask pattern73may be formed in the first dummy holes DH1and the dummy contact hole D_CTH, and may be formed in some of the contact holes CTH. The third mask pattern73may include a photoresist.

Subsequently, the first stack ST1may be etched using the third mask pattern73and the hard mask pattern67as etching barriers. Through this, the other contact holes CTH may extend into the first stack ST1. The extending other contact holes CTH may expose the first material layers51, respectively. Accordingly, the contact holes CTH may have different depths, and may expose the first material layers51and the third material layers61, respectively.

Referring toFIGS.14A and14B, the third mask pattern73may be removed. Subsequently, a fourth mask pattern74may be formed. The fourth mask pattern74may cover the contact region CTR and may expose the edge region ER. The fourth mask pattern74may cover at least a portion of the cell region CR. Through this, the first dummy holes DH1and the dummy contact hole D_CTH may be exposed. The fourth mask pattern74may be formed in the contact holes CTH. The fourth mask pattern74may include a photoresist.

Subsequently, the first material layers51and the third material layers61may be etched through the dummy contact hole D_CTH and the first dummy holes DH1. Through this, an isolation trench IST may be formed in the first stack ST1and the second stack ST2.

By selectively etching the first material layers51, the first dummy holes DH1may be expanded in a horizontal direction and may be connected to each other. The expanded first dummy holes E_DH1may be located in the first stack ST1. By selectively etching the third material layers61, the dummy contact hole D_CTH may be expanded in the horizontal direction. The expanded dummy contact hole E_DCTH may be located in the second stack ST2. Depending on an interval between dummy contact holes D_CTH adjacent to each other in the second direction II, the expanded dummy contact holes E_DCTH may be connected to or isolated from each other. Through this, the isolation trench IST including the expanded first dummy holes E_DH1and the expanded dummy contact hole E_UTH may be formed.

Referring toFIGS.15A and15B, an insulating liner76may be formed in the isolation trench IST. The insulating liner76may partially fill the isolation trench IST. According to an example, the insulating liner76may be filled in the expanded first dummy holes E_DH1, and may extend along inner walls of the expanded dummy contact hole E_DCTH. A central region of the expanded dummy contact hole E_DCTH may be opened without being filled with the insulating liner76.

An insulating liner76may be formed in the contact holes CTH. The insulating liner76may be formed along an inner surface of the contact hole CTH, and may partially fill the contact hole CTH. The insulating liner76may extend along an upper surface of the second stack ST2. The insulating liner76formed in the isolation trench IST and the insulating liner76formed in the contact holes CTH may be connected to each other.

The insulating liner76may include a material having a high etching selectivity with respect to the first material layers51and the third material layers61. The insulating liner76may include an insulating material such as, for example, an oxide or a nitride. By forming the insulating liner76using the insulating material, it is possible to reduce generation of a bridge between gate lines formed in a subsequent process.

Subsequently, sacrificial layers77may be formed in the insulating liners76. The sacrificial layers77may be located in the expanded dummy contact hole E_DCTH and the contact holes CTH, respectively. The sacrificial layers77may include a material having an etching selectivity with respect to the insulating liner76. According to an example, the sacrificial layers77may include polysilicon.

Referring toFIGS.16A and16B, the first material layers51and the third material layers61may be replaced with fifth material layers81. According to an example, a slit SL extending through the second stack ST2and the first stack ST1may be formed. Subsequently, openings may be formed by selectively etching the first material layers51and the third material layers61through the slit SL. When the first material layers51and the third material layers61are etched, the insulating liners76may be used as an etch stop layer. Subsequently, the fifth material layers81may be formed in the openings. The fifth material layers81may be gate lines81G or dummy gate lines81D. Through this, a gate structure GST located in the cell region CR and the contact region CTR may be formed. A dummy gate structure D_GST located in the edge region ER may be formed.

Referring toFIGS.17A and17B, the sacrificial layers77may be removed. According to an example, the sacrificial layers77may be removed using a dip-out process. Subsequently, insulating spacers76A may be formed in the contact holes CTH, respectively. An isolation layer76B may be formed in the isolation trench IST. According to an example, the insulating liner76may be etched using an etch-back process. Through this, a portion of the insulating liner76formed on an upper surface of the gate structure GST and a portion of the insulating liner76formed on an upper surface of the dummy gate structure D_GST may be removed. Portions of the insulating liner76formed on bottom surfaces of the contact holes CTH may be removed, and the gate lines81G may be exposed. A portion of the insulating liner76formed in the isolation trench IST may be partially etched.

Subsequently, contact plugs CP may be formed. The contact plugs CP may be located in the contact holes CTH, respectively, and may be electrically connected to the gate lines81G. A barrier layer87may be formed in the contact hole CTH, and a conductive plug86may be formed to gap fill the space defined by the barrier layer87. A dummy contact plug D_CP may be formed. The dummy contact plug D_CP may be located in the dummy contact hole D_CTH. A barrier layer89may be formed in the isolation layer76B, and a conductive plug88may be formed to gap fill the space defined by the barrier layer89. Through this, an isolation insulating structure IS including the isolation layer76B and the dummy contact plug D_CP may be formed.

The dummy contact plug D_CP may have an electrically floated state. When the dummy contact plug D_CP is formed, the contact plug CP may be formed also.

According to the manufacturing method described above, when the channel structures CH are formed in the cell region CR, the dummy channel structures D_CH may be formed in the edge region ER. By making the pattern densities of the cell region CR and the edge region ER uniform, it is possible to reduce bending of the first and second stacks ST1and ST2when the slit SL is formed. A shape of the slit SL may not be changed to prevent the bending of the first and second stacks ST1and ST2. The slit SL may be formed in a line shape having a uniform width. In addition, the isolation insulating structure IS may be formed using a process of forming the channel structure CH and a process of forming the contact plug CP.

Although embodiments according to the technical idea of the present disclosure have been described above with reference to the accompanying drawings, this is only for describing the embodiments according to the concept of the present disclosure, and the present disclosure is not limited to the above embodiments. Various types of substitutions, modifications, and changes for the embodiments may be made by those skilled in the art, to which the present disclosure pertains, without departing from the technical idea of the present disclosure defined in the following claims, and it should be construed that these substitutions, modifications, and changes belong to the scope of the present disclosure. Furthermore, the embodiments may be combined to form additional embodiments.