Method for fabricating stacked layer silicon nitride for low leakage and high capacitance

A method is provided for forming silicon nitride stacks. A semiconductor substrate is cleaned to remove any native oxide, and an insulative material is disposed thereon. A plurality of films are deposited superjacent the insulative material, and each of the plurality of films converted into a dielectric to form a multi-layered stack. A fill layer is formed superjacent the multi-layered stack to seal any pinholes. The fill layer is formed by at least one of low temperature chemical vapor deposition (CVD) of oxide, low temperature deposition of nitride, low temperature re-oxidation of ozone, the low temperature is at least 20.degree. C.

FIELD OF THE INVENTION 
This invention relates to semiconductor processes and to a method for 
fabricating a stacked layer of Si.sub.3 N.sub.4. More particularly, the 
invention relates to a process for formulating a thin dielectric layer 
having low leakage and high capacitance characteristics. 
BACKGROUND OF THE INVENTION 
As the trend of scaling down integrated circuits continues, the 
semiconductor industry is forced to consider new techniques for 
fabricating precise components at submicron levels. This is of particular 
relevance to the manufacture of memory devices. The expansion of the 
memory capacity is dependent on the ability to fabricate smaller cells 
having increased capacitances. Dielectric layers are the foundation to the 
creation of cell capacitors. As such, if a thinner a dielectric layer is 
manufactured which has the necessary dielectric constant, the smaller the 
memory cell. 
In metal oxide semiconductor ("MOS") technology, small, high performance 
transistors require thin gate and cell dielectrics. An ultrathin 
(.ltoreq.100 .ANG.) dielectric layer should minimally comprise enhanced 
dielectric properties. 
However, several additional design considerations must be examined in the 
manufacture of ultrathin dielectric layers. These include uniformity in 
thickness, reliability, high dielectric constant, as well as 
imperviousness to electrical and thermal breakdown. Ultimately, high 
performance, ultrathin dielectric layers should also comprise a low 
diffusion rate for impurities, low interface state density, and chemical 
stability. Nevertheless, the physical constraints of the materials and 
methods of fabrication employed have made the characteristics of the 
dielectrics less than the optimum. 
Silicon dioxide, at thicknesses greater than 100 .ANG., provides a cost 
effective, high quality dielectric layer for single crystal silicon, 
polycrystalline silicon ("polysilicon"), or amorphous silicon substrates. 
Nonetheless, for dielectric layers less than 100 .ANG., silicon dioxide is 
known to have a high defect density. Silicon dioxide also exhibits poor 
characteristics as a diffusion mask against impurities. Further, silicon 
dioxide has a relatively low dielectric constant. 
In light the inherent limitations of silicon dioxide for dielectric layers 
of 100 .ANG. or less, several alternatives have been developed. One such 
alternative is the use of silicon nitride (Si.sub.3 N.sub.4) as a 
dielectric layer. This layer can be formed on a substrate surface through 
a process which includes Rapid Thermal Nitridation ("RTN"). Under RTN, the 
silicon substrate is exposed to either pure ammonia (NH.sub.3) or an 
ammonia plasma at temperatures approximately between 850.degree. C. and 
1200.degree. C. to form a silicon nitride film. 
Precise ultrathin dielectric layers are currently fabricated employing RTN. 
However, these layers have several shortcomings. RTN-type ultrathin 
dielectrics lack uniformity in their overall composition. Further, they 
have questionable reliability in part because of their susceptibility to 
high electrical leakage, as well as electrical and thermal breakdown. 
Hence, the overall cell capacitance of the known art is limited. 
Moreover, current techniques for fabricating ultrathin dielectric layers, 
such as silicon nitride, have failed to address current leakage caused by 
the bulk effects of semiconductor wafers, also known as, pinholes. This 
problem is of significance where the dielectric layer is substantially in 
the 100 .ANG. range. A pinhole having a sufficient length enables current 
leakage, and as such, reduces the overall reliability of the device. 
One solution to the problem of pinholes is to divide the dielectric layer 
having a specified thickness and dielectric constant into two comparable 
dielectric layers which have both a composite thickness and dielectric 
constant. 
Referring to FIG. 1, a first dielectric layer 5 is illustrated superjacent 
a semiconductor substrate 1. First dielectric layer 5 comprises a pinhole 
4. Superjacent first dielectric layer 5 is a second dielectric layer 9 
comprising a pinhole 6. If both first and second dielectric layers, 5 and 
9, are replaced with a single dielectric layer having an equivalent 
dielectric constant, a pinhole therein may be sufficient to cause 
electrical leakage. 
However, by forming two independent dielectric layers, the probability is 
substantially reduced that both pinholes 4 and 6 are aligned in such a way 
as to create the potential for leakage. 
SUMMARY OF THE INVENTION 
The primary object of the present invention is to eliminate the 
aforementioned drawbacks of the prior art. 
It is a further object of the present invention to provide a method of 
fabricating an ultrathin dielectric layer which isolates and overcomes the 
bulk effects of semiconductor wafers. 
Another object of the present invention is to provide a method of 
fabricating an ultrathin dielectric layer having substantially reduced 
leakage current, and reduced overall thermal budget. 
Yet another object of the present invention is to provide a method for 
fabricating a semiconductor wafer having reduced structural defects, and 
enhanced electrical properties. 
A further object of the present invention is to provide a method of 
fabricating an ultrathin dielectric layer having reduced sensitivity 
towards pinholes. 
Still another object of the present invention is to provide a method of 
fabricating an ultrathin dielectric layer having an increased overall 
electrical reliability. 
Yet another object of the present invention is to provide a method of 
fabricating an ultrathin dielectric layer independent of process time. 
In order to achieve the hereinabove objects, as well as others that will 
become apparent hereafter, a method for fabricating semiconductor wafers 
is disclosed wherein a rugged and/or smooth, atomically clean, 
semiconductor substrate is provided in a chamber. Subsequently, a first 
silicon nitride layer is formed in situ under high pressure superjacent 
the substrate by introducing a gas containing nitrogen, preferably 
NH.sub.3 combined with N.sub.2, at a temperature within the range of 
850.degree. C. to 1150.degree. C. for approximately 10 to 60 seconds. This 
results in the first layer having a thickness of at least 5 .ANG.. 
A semiconductor film is then deposited in situ under high pressure 
superjacent the first silicon nitride layer, preferably by means of Rapid 
Thermal Processing Chemical Vapor Deposition ("RTPCVD"). In an alternate 
embodiment of the present invention, this is accomplished by either Low 
Pressure Chemical Vapor Deposition ("LPCVD") or Molecular Beam Epitaxy 
("MBE"). The thickness of the film is at least 10 .ANG.. 
Consequently, the film is transformed in situ under high pressure into a 
second silicon nitride layer by introducing a gas containing nitrogen, 
preferably NH.sub.3 combined with N.sub.2, at a temperature substantially 
within the range of 850.degree. C. to 1150.degree. C. applied for 
approximately 10 to 60 seconds. The thickness of the second silicon 
nitride layer is substantially in the range of the thickness of the film. 
In one embodiment of the present invention, only a portion of the film is 
transformed into a second silicon nitride layer, thereby creating a 
remainder of the film subjacent the second silicon nitride layer. In this 
embodiment, the thickness of the second silicon nitride layer is less than 
the thickness of the film. 
Finally, a second semiconductor film is deposited superjacent the second 
layer in situ under high pressure. 
In one alternate embodiment of the present invention, a pair of silicon 
dioxide layers are grown between the step of providing a semiconductor 
substrate and the step of depositing a second semiconductor film. It 
should be noted that the semiconductor substrate, the semiconductor film, 
and the second semiconductor film each comprise at least one of 
single-crystal silicon, polycrystalline silicon, and amorphous silicon. 
Other objects and advantages will become apparent to those skilled in the 
art from the following detailed description read in conjunction with the 
appended claims and the drawings attached hereto.

DETAILED DESCRIPTION OF THE INVENTION 
Referring to FIG. 2, a semiconductor substrate 10 within a chamber 80 is 
illustrated prior to undergoing process of the present invention. 
Substrate 10 preferably comprises polycrystalline silicon ("polysilicon"), 
though single crystal silicon, amorphous silicon or any other suitable 
material known in art can also be employed. Further, substrate 10 can be 
rugged and/or smooth. Alternatively, the substrate can also be rippled or 
corrugated, in the case of cylindrical or contained capacitor structures. 
Substrate 10 is atomically cleaned in the process of the present invention. 
The clean is necessary because a native silicon dioxide layer 70 easily 
forms superjacent substrate 10 by simple exposure to the atmosphere. 
Unfortunately, native silicon dioxide has inferior electrical and 
structural characteristics when compared with other dielectric type 
materials, such as grown silicon dioxide. As such, the overall electrical 
and structural characteristics of the completed wafer having native 
silicon dioxide are substantially impacted. Thus, in order to maintain the 
integrity of the wafer, any native silicon dioxide formed is removed by 
atomically cleaning substrate 10. 
There are a variety of techniques for removing native oxide 25. Those known 
to one of ordinary skill in the art are not described. In one embodiment 
of the present invention, the substrate 10 is cleaned by radiating vapor 
phase ozone (O.sub.3) with energy from an ultra-violet source. This 
reaction takes place at a room temperature, i.e. at least 20.degree. C. 
This process effectively removes the native oxide layer in just a few 
seconds. 
An alternative embodiment employs an in-situ vapor clean using a hydrogen 
halide, such as hydrofluoric acid (HF) and hydrochloric acid (HCl). This 
vapor clean is also performed at room temperature, although higher 
temperatures can also be used. This method also is effective to remove any 
native oxide in a few seconds. In an alternative embodiment, methanol is 
added to the hydrogen halide. The methanol is used as a dilutant. The 
above described techniques for native oxide removal are advantageous for 
sub-half micron densities, for which lower thermal budgets are critical. 
Another alternative embodiment of the present invention, native silicon 
dioxide is removed by introducing a reactive gas, for example as NF.sub.3, 
GeH.sub.4, HF, or H.sub.2 further diluted with an inert gas, such as 
Ar--H.sub.2, and heat at a temperature substantially within the range of 
850.degree. C. to 1250.degree. C. for approximately 10 to 60 seconds. 
Relying on this method, any native silicon dioxide formation between 10 
.ANG. and 20 .ANG. is easily removed. 
The process of the present invention involves providing an atomically 
cleaned substrate 10 into a chamber 88, before growing any further layers. 
To simplify the entire process, the chamber is preferably a Rapid Thermal 
Processing ("RTP") chamber. By employing an RTP chamber, substrate 10 is 
directly cleaned within the chamber. As such, the remaining steps of the 
present inventive method are preferably performed in situ, under high 
vacuum. 
However, in an alternate embodiment of the present invention, the remaining 
steps are performed ex situ, on cluster tools. Employing such an approach, 
a load lock is created between each tool to avoid exposing the wafer 
during any part of the process to the atmosphere and contaminants. 
The process of the present invention can also be performed using in situ 
cluster processing, in which the wafer is not exposed to the atmosphere 
during fabrication of the stacked dielectric layers. 
Referring to FIG. 3, a first dielectric layer 20 is illustrated superjacent 
atomically clean substrate 10. Upon providing clean substrate 10, first 
dielectric layer 20 is grown relying on the principles of Rapid Thermal 
Nitridation ("RTN"). 
Substrate 10 is exposed to a gas and heat at a temperature substantially 
within the range of 850.degree. C. to 1150.degree. C. for approximately 10 
to 60 seconds. The gas to be introduced in the preferred embodiment of the 
present invention comprises nitrogen, such as NH.sub.3 combined with 
N.sub.2 for example. By employing a nitrogen based gas, first dielectric 
layer 20 forms comprising silicon nitride and having an approximate 
thickness in the range of 5 .ANG. to 30 .ANG.. This range is in part 
effected by the self limiting nature of silicon nitride grown by means of 
RTN. This is followed by the deposition of a first nitride layer using 
Chemical Vapor Deposition ("CVD"), Low Pressure Chemical Vapor Deposition 
("LPCVD"), Molecular Beam Epitaxy ("MBE"), etc. First dielectric layer 20 
is thus formed by RTN and deposition of a nitride film. 
Subsequently, this film is re-oxidized using ozone gas at a temperature of 
at least 100.degree. C. In another embodiment, following the formation of 
layer 20, a thin layer of amorphous silicon is deposited having a 
thickness of at least 20 .ANG.. This amorphous silicon layer is then 
subjected to Rapid Thermal Nitridation ("RTN"). 
This sequence of forming multiple layers is continued until the desired 
thickness for the specific application is achieved. The stacked silicon 
nitride structures formed using this embodiment of the process of the 
present invention are fabricated in a single wafer RTCVD-type system that 
provides an easy switching of various gas chemistries without 
cross-contamination. 
In another alternative embodiment, the stacked layer is re-oxidized using a 
wet oxidation with ultra-violet radiation to form layer 20. This 
re-oxidation method can also be performed at any of the interfaces of the 
multi-layer dielectric stack. The purpose is to fill any pinholes which 
have formed in the composite dielectric structure. 
Referring to FIG. 4, a film 30 is deposited superjacent said first 
dielectric layer 20. Film 30 preferably comprises polycrystalline silicon 
("polysilicon"), though single crystal silicon, amorphous silicon, or any 
other suitable material known in art can also be employed. Moreover, film 
30 can be rugged and/or smooth, as well as rippled or corrugated. 
Preferably, film 30 has an approximate thickness in the range of 10 .ANG. 
to 40 .ANG., though it can also be a monolayer. 
There are a variety of known techniques for depositing film 30. As such, 
those known to one of ordinary skill in the art are not described. In the 
preferred embodiment of the present invention, film 30 is deposited in 
situ under high vacuum, superjacent first dielectric layer 20 by means of 
Rapid Thermal Processing Chemical Vapor Deposition ("RTPCVD"). 
In an alternate embodiment, the depositing is accomplished by either Low 
Pressure Chemical Vapor Deposition ("LPCVD") or Molecular Beam Epitaxy 
("MBE"). Relying on RTPCVD principles, this step involves introducing film 
30 at a temperature substantially within the range of 300.degree. C. to 
1000.degree. C. for approximately 10 to 60 seconds. 
Referring to FIG. 5, a second dielectric layer 40 is depicted superjacent 
first dielectric layer 20. Film 30 is transformed into second dielectric 
layer 40. This is accomplished by introducing gas and heat at a 
temperature substantially within the range of 850.degree. C. to 
1150.degree. C. for approximately 10 to 60 seconds, preferably, in situ 
under high vacuum. The gas introduced in the preferred embodiment of the 
present invention comprises nitrogen, such as, NH.sub.3 combined with 
N.sub.2, for example. By employing a nitrogen based gas, second dielectric 
layer 40 forms comprising silicon nitride. 
The relationship between the thickness of second dielectric layer 40 and 
film 30 is dependent on the complete interaction of film 30 with the 
nitrogen based gas introduced. As such, in the preferred embodiment of the 
present invention, the approximate thickness of second dielectric layer 40 
is substantially in the range of the thickness of film 30. 
However, in an alternate embodiment, only a portion 45 of film 30 is 
converted to second dielectric layer 40, as shown in FIG. 7. In this 
scheme, a floating film remainder 90 is created subjacent portion 45 of 
film 30 which is converted to second dielectric layer 40. The floating 
film remainder 90, given the relatively high dielectric constant of 
silicon, polysilicon and amorphous silicon, provides a means for 
increasing the dielectric constant of the composite layer--first 
dielectric layer 20, second dielectric layer 40 and floating film 
remainder 90. 
It should be obvious to one of ordinary skill in the art that floating film 
remainder 90, acting as a dielectric layer, has an optimum thickness for 
formulating a high capacitance value. As such, floating film remainder 90 
should be substantially less than 100 .ANG.. 
Referring to FIG. 6, a coating 50 is shown superjacent second dielectric 
layer 40. Coating 50 preferably comprises polycrystalline silicon 
("polysilicon"), though single crystal silicon, amorphous silicon, or any 
other suitable material known in art can also be employed. Further, 
coating 50 can be rugged and/or smooth, as well as rippled or corrugated. 
The deposition of coating 50, given first and second dielectric layers, 20 
and 40, and substrate 10, gives rise to a complex structure. This 
structure can be employed in the formation of cell capacitors and 
transistors. 
Coating 50 acts as a "fill" for any pinholes which have formed during the 
above-described process. The presence of coating 50 prevents the pinholes 
from extending through the multi-stack structure. 
There are a variety of known techniques for depositing coating 50 
superjacent second dielectric layer 40. As such, those known to one of 
ordinary skill in the art are not described. One embodiment employs rapid 
thermal oxidation ("RTO"). Employing this scheme, silicon dioxide layer 50 
is grown, preferably in situ under high vacuum, by introducing a gas 
containing oxygen, such as O.sub.2 and N.sub.2 O, at a temperature between 
850.degree. C. and 1250.degree. C. for approximately 5 seconds to 30 
seconds. 
Another alternative embodiment is to fill the pinholes with CVD oxide. This 
embodiment is performed at a lower temperature than either Rapid Thermal 
Nitridation ("RTN") or Rapid Thermal Oxidation ("RTO"). 
In another alternative embodiment of the present invention, coating 50 is 
provided superjacent second dielectric layer 40 in situ under high vacuum 
by means of Rapid Thermal Processing Chemical Vapor Deposition ("RTPCVD"). 
In another alternate embodiment, this step is accomplished by either LPCVD 
or MBE. Relying on RTPCVD principles, this step involves introducing 
coating 50 at a temperature substantially within the range of 300.degree. 
C. to 1000.degree. C. for approximately 10 to 60 seconds. 
In another alternate embodiment of the present invention, additional 
silicon dioxide layers 100 and 100' are formed between coating 50 and 
substrate 10, preferably by means of Rapid Thermal Oxidation. Employing 
this scheme, silicon dioxide layers 100 and 100' are grown, preferably in 
situ under high vacuum, by introducing a gas containing oxygen, such as 
O.sub.2 and N.sub.2 O, at a temperature between 850.degree. C. and 
1250.degree. C. for approximately 5 seconds to 30 seconds. 
The addition of silicon dioxide layers 100 and 100' provide a particular 
approach for improving the electrical leakage and reliability of the 
overall composite layer--first dielectric layer 20, second dielectric 
layer 40 and floating film remainder 90--given the inherent electrical 
properties of silicon dioxide. 
It should be noted that while FIG. 8 illustrates silicon dioxide layer 100 
subjacent first dielectric layer 20 and silicon dioxide layer 100' 
superjacent second dielectric layer 40, there are many alternate 
configurations that one of ordinary skill in the art could devise to 
promote the present invention. 
While the particular process as herein shown and disclosed in detail is 
fully capable of obtaining its objects and advantages herein before 
stated, it is to be understood that it is merely illustrative of the 
presently preferred embodiments of the invention and that no limitations 
are intended to the details herein shown, other than as described in the 
appended claims. 
The present invention is equally applicable to memory devices, such as 
flash memories, DRAMs, SRAMs, VRAMs, as well as other technologies 
requiring the dielectric layers. Moreover, the present invention is not 
limited to silicon, polysilicon and amorphous silicon. Materials such as 
SiGe and GeO.sub.2 are applicable. The particular sensitivity of GeO.sub.2 
to water in the fabrication of semiconductor wafers is particularly 
overcome by the present inventive method. 
Further, it is to be understood that although the present invention has 
been described in a preferred embodiment, various modifications known to 
those skilled in the art may be made without departing from the spirit of 
the invention, as recited in the claims appended hereto.