Method for fabricating a micro resistance layer and method for fabricating a micro resistor

A method for fabricating a micro resistance layer and a method for fabricating a micro resistor are provided. The method for fabricating a micro resistance layer includes: providing a substrate; forming a first resistance layer on the substrate by using a screen printing process or a sputtering process; dividing the first resistance layer into second resistance layers, wherein each one of the product regions includes a second resistance layer, and an area of each one of the product regions is smaller than 0.4*0.2 mm2; and trimming the second resistance layer of each one of the product regions according to a predetermined resistance value to enable the pattern of each one of the second resistance layers to correspond to the predetermined resistance value. The method for fabricating a micro resistor uses the method for fabricating a micro resistance layer for fabrication of the micro resistor.

RELATED APPLICATION

This application claims priority to Taiwan Application Serial Number 110149006, filed Dec. 28, 2021, which is herein incorporated by reference.

BACKGROUND

Technical Field

The present disclosure generally relates to a method for fabricating a micro resistance layer and method for fabricating a micro resistor.

Description of Related Art

With rapid development of economy and technologies, it is required for various electronic products such as smart phones, tablets and notebooks to provide more functions to meet user's demands. For example, the smart phones provide functions of image capturing and image processing to meet user's demands for image quality. Accordingly, it is required for the electronic products to use electric components having smaller sizes for integrating more electric components to meet user's demands.

Resistors are necessary components in the fabrication of the electronic products. In order to meet the demands for small product sizes, various resistors having small sizes such as 01005 type resistors and 0075 type resistors are developed for the demands for small sizes. However, a plenty of time and higher cost are required for typical fabrication method of the small size resistors. Therefore, a micro resistor fabrication method requiring lower fabrication cost and less fabrication time is needed.

SUMMARY

To solve the above mentioned problems, embodiments of the present disclosure provides a method for fabricating a micro resistance layer and a method for fabricating a micro resistor, which may greatly decrease fabrication time and fabrication cost of the micro resistor.

In accordance with an embodiment of the present disclosure, the method for fabricating a micro resistance layer includes: providing a substrate, in which a plurality of product regions are defined on the substrate, and an area of each of the product regions is small than or equal to 0.4*0.2 mm2; forming a first resistance layer on the substrate by using a screen printing process or a sputtering process, in which the first resistance layer covers the product regions; dividing the first resistance layer into a plurality of second resistance layers, in which each of the product regions encompasses one of the second resistance layers, and an area of each of the second resistance layers is small than 0.4*0.2 mm2; and trimming a pattern of each of the second resistance layers in accordance with a predetermined resistance value to enable the pattern of each one of the second resistance layers to correspond to the predetermined resistance value.

In some embodiments, the screen printing process is performed by using a fully-open screen.

In some embodiments, dividing the first resistance layer into the second resistance layers is performed by using a laser.

In some embodiments, trimming the pattern of each of the second resistance layers in accordance with a predetermined resistance value to enable the pattern of each one of the second resistance layers to correspond to the predetermined resistance value is performed by using a laser.

In accordance with an embodiment of the present disclosure, the method for fabricating a micro resistor includes: providing a substrate, in which the substrate has a first surface and a second surface opposite to the first surface, a plurality of resistor regions are defined on the substrate, and an area of each of the resistor regions is small than or equal to 0.4*0.2 mm2; forming a plurality of first inner electrode pairs on the first surface, in which each of the resistor regions encompasses one of the first inner electrode pairs; forming a plurality of second inner electrode pairs on the second surface, in which each of the resistor regions encompasses one of the second inner electrode pairs; forming a first resistance layer on the first surface of the substrate by using a screen printing process or a sputtering process to cover the resistor regions; dividing the first resistance layer into a plurality of second resistance layers, in which each of the resistor regions encompasses one of the second resistance layers, and each of the second resistance layers is smaller than 0.4*0.2 mm2; trimming a pattern of the second resistance layer of each of the resistor regions in accordance with a predetermined resistance value to enable the pattern of the second resistance layer of each of the resistor regions to correspond to the predetermined resistance value; dividing the substrate into a plurality of substrate strips in accordance with the resistor regions; forming an outer electrode layer on each of the substrate strips, in which the outer electrode layer comprises a side electrode layer, and is electrically connected to the first inner electrode pair, the second inner electrode pair and the second resistance layer of each of the resistor regions; and dividing each of the substrate strips in accordance with the resistor regions to obtain a plurality of micro resistors each having an area small than or equal to 0.4*0.2 mm2.

In some embodiments, dividing the first resistance layer into the second resistance layers is performed by using a laser.

In some embodiments, trimming the pattern of the second resistance layer of each of the resistor regions in accordance with the predetermined resistance value is performed by using a laser.

In some embodiments, the screen printing process is performed by using a fully-open screen.

In some embodiments, the resistor regions are arranged in a matrix having a plurality of resistor columns and a plurality of resistor rows.

In some embodiments, the fully-open screen comprises a plurality of openings, and an area of each of the openings is determined in accordance with an area of each of the resistor columns of the matrix.

In accordance with an embodiment of the present disclosure, the method for fabricating a micro resistor includes: providing a substrate, in which the substrate has a first surface and a second surface opposite to the first surface, a plurality of resistor regions are defined on the substrate, and an area of each of the resistor regions is small than or equal to 0.4*0.2 mm2; forming a plurality of first inner electrode pairs on the first surface, in which each of the resistor regions encompasses one of the first inner electrode pairs; forming a plurality of second inner electrode pairs on the second surface, in which each of the resistor regions encompasses one of the second inner electrode pairs; forming a first resistance layer on the first surface of the substrate by using a screen printing process or a sputtering process to cover the resistor regions; dividing the first resistance layer into a plurality of second resistance layers, in which each of the resistor regions encompasses one of the second resistance layers, and each of the second resistance layers is smaller than 0.4*0.2 mm2; trimming a pattern of the second resistance layer of each of the resistor regions in accordance with a predetermined resistance value to enable the pattern of the second resistance layer of each of the resistor regions to correspond to the predetermined resistance value; performing an outer electrode forming step to form an outer electrode layer in each of the resistor regions, in which the outer electrode layer comprises a side electrode layer, and is electrically connected to the first inner electrode pair, the second inner electrode pair and the second resistance layer of each of the resistor regions; and dividing the substrate in accordance with the resistor regions to obtain a plurality of micro resistors each having an area small than or equal to 0.4*0.2 mm2.

In some embodiments, dividing the first resistance layer into the second resistance layers is performed by using a laser.

In some embodiments, trimming the pattern of the second resistance layer of each of the resistor regions in accordance with the predetermined resistance value is performed by using a laser.

In some embodiments, the resistor regions are arranged in a matrix having a plurality of resistor columns and a plurality of resistor rows.

In some embodiments, the screen printing process is performed by using a fully-open screen.

DETAILED DESCRIPTION

Specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings, however, the embodiments described are not intended to limit the present invention and it is not intended for the description of operation to limit the order of implementation. Moreover, any device with equivalent functions that is produced from a structure formed by a recombination of elements shall fall within the scope of the present invention. Additionally, the drawings are only illustrative and are not drawn to actual size.

The using of “first”, “second”, “third”, etc. in the specification should be understood for identifying units or data described by the same terminology, but are not referred to particular order or sequence.

Referring toFIG.1,FIG.1is a schematic diagram showing a flow chart of a method100for fabricating a micro resistance layer in accordance with an embodiment of the present disclosure. The micro resistance layer fabrication method100is adapted for fabrication of a micro resistance layer having an area small than or equal to 0.4*0.2 mm2. In the micro resistance layer fabrication method100, at first, step110is performed to provide a substrate210, as shown inFIG.2A. The substrate210can be formed by using insulation material, for example glass fibers, Aluminum Nitride material, Silicon-based material or Ceramic material, but embodiments of the present disclosure are not limited thereto. A plurality of product regions212are defined on the substrate210through a plurality of virtual cutting lines CL. The product region212is pre-defined for a product having a resistance layer, for example a resistor or other component having a resistance layer. In this embodiment, the product region212has an area small than or equal to 0.4*0.2 mm2, and the resistor regions212are arranged in a matrix having a plurality of product columns PC and a plurality of product rows PR. In some embodiments, the product region212has an area substantially equal to 0.3*0.15 mm2.

Then, step120is performed to use a screen printing process to form a first resistance layer220on the substrate210, as shown inFIG.2B. In this embodiment, the screen printing process of the step120uses a fully-open screen to form the first resistance layer220on the first resistance layer220. The first resistance layer220includes a plurality of sub resistance layers222formed on the product columns PC accordingly. For example, in this embodiment, the sub resistance layers222are formed corresponding to the product columns PC and formed across the product rows PR. However, embodiments of the present disclosure are not limited thereto.

Thereafter, step130and step140are performed to divide the first resistance layer220into a plurality of second resistance layer222ain accordance with the product regions212, and to trim the second resistance layer222a. In step130, each of the sub resistance layers222of the first resistance layer220is divided into the second resistance layers222aas shown inFIG.2C. For example, each of the sub resistance layers222is divided into the second resistance layers222ain accordance with the product rows PR to enable each of the product regions212to encompass one second resistance layer222a. In this embodiment, because the product region212has an area small than or equal to 0.4*0.2 mm2, an area of the second resistance layer222aof each of the product regions212is small than 0.4*0.2 mm2. In step140, a pattern of the second resistance layer222aof each of the product regions212is trimmed in accordance with a predetermined resistance value (for example, forming a long opening OP by cutting the second resistance layer222a) to enable the pattern of the second resistance layer222ato be corresponding to the predetermined resistance value as shown inFIG.2D. In this embodiment, the operations of dividing the first resistance layer220and trimming the pattern of the second resistance layer222aare performed by using a laser, but embodiments of the present disclosure are not limited thereto.

In addition, in some embodiments, the above step120may include a mask forming step to form a mask (not shown) on the substrate210in advance. The mask has a plurality of openings to expose portions of the substrate210. Then, a fully-open screen310is used to form the first resistance layer220on the mask and covering the substrate210, in which the fully-open screen310does not have any mesh and knot, and an opening312of the fully-open screen310has a size substantially equal to the size of the matrix of the product regions212, as shown inFIG.3A. Therefore, the first resistance layer220covering the matrix of the product regions212can be formed, in which portions of the first resistance layer220are formed on the exposed portions of the substrate210. Then, the mask and the first resistance layer220formed on the mask are removed to obtain the first resistance layer220as shown inFIG.2B.

In some embodiments, another fully-open screen320is used in the above step120as shown inFIG.3B, in which the fully-open screen320does not have any mesh and knot, and has a plurality of openings322. To form the first resistance layer220as shown inFIG.2B, an area of each of the openings322is determined in accordance with the product column PC. For example, a length of the opening322is substantially equal to a length of the product column PC, and a width of the opening322is slightly smaller than a width of the product column PC.

In accordance with the above descriptions, in the micro resistance layer fabrication method100of the embodiment of the present disclosure, the screen printing process is used to form a micro resistance layer having a small size, in which the screen printing process uses the fully-open screen to form the micro resistance layer. Because the micro resistance layer fabrication method100uses the fully-open screen to form the micro resistance layer, disadvantages, for example deletion of a shape of the printed layer, insufficiency of a thickness of the printed layer or undesired holes on the printed layer caused by the mesh and knot of the screen are avoid. Further, using the screen printing process to fabricate the micro resistance layer can greatly decrease the fabrication cost and fabrication time of the micro resistance layer.

Referring toFIG.4,FIG.4is a schematic diagram showing a flow chart of a method400for fabricating a micro resistor in accordance with an embodiment of the present disclosure. The micro resistor fabrication method400uses the above micro resistance layer fabrication method100to fabricate a micro resistor such as a 01005 type resistor, a 0075 type resistor or a micro resistor having a smaller size. In the micro resistor fabrication method400, at first, step410is performed to provide a substrate510, as shown inFIG.5A. The substrate510can be formed by using insulation material, for example glass fibers, Aluminum Nitride material, Silicon-based material or Ceramic material, but embodiments of the present disclosure are not limited thereto. A plurality of resistor regions512are defined on the substrate510through a plurality of virtual cutting lines CL. The resistor region512is pre-defined for a resistor. In this embodiment, the resistor region512has an area small than or equal to 0.4*0.2 mm2, and the resistor regions512are arranged in a matrix having a plurality of resistor columns RC and a plurality of resistor rows RR. In some embodiments, the resistor region512has an area substantially equal to 0.3*0.15 mm2.

Then, step420and step430are performed to form a plurality of first electrode pairs FE and second electrode pairs BE respectively on a first surface510aand a second surface510bof the substrate510, as shown inFIG.5BandFIG.5C. In this embodiment, the first surface510ais a front side of the substrate510, and the second surface510bis a back side of the substrate510. The front side of each of the resistor regions512encompasses one first electrode pairs FE, and each of the first electrode pairs FE includes two electrodes FE1and FE2. The back side of each of the resistor regions512encompasses one second electrode pairs BE, and each of the second electrode pairs BE includes two electrodes BE1and BE2.

Then, a step440is performed to use a screen printing process to form a first resistance layer520on the first surface510aof the substrate510, as shown inFIG.5D. In this embodiment, the screen printing process of the step440uses the fully-open screen to form a first resistance layer520on the first surface510aof the substrate510. The first resistance layer520includes a plurality of sub resistance layers522formed on the resistor columns RC accordingly. For example, in this embodiment, the sub resistance layers522are formed corresponding to the resistor columns RC and formed across the resistor rows RR. However, embodiments of the present disclosure are not limited thereto.

In some embodiments of the present disclosure, a sequence of steps410-430can be adjusted in accordance with user's demands. For example, the first resistance layer520can be formed at first, and then the first electrode pairs FE are formed.

Thereafter, step450and step460are performed to divide the first resistance layer520into a plurality of second resistance layer522ain accordance with the resistor regions512, and to trim the second resistance layer522a. In step450, each of the sub resistance layers522of the first resistance layer520is divided into the second resistance layers522aas shown inFIG.5E. For example, each of the sub resistance layers522is divided into the second resistance layers522ain accordance with the resistor rows RR to enable each of the resistor regions512to encompass one second resistance layer522a. In this embodiment, because the resistor region512has an area small than or equal to 0.4*0.2 mm2, an area of the second resistance layer522aof each of the resistor regions512is small than 0.4*0.2 mm2. In step460, a pattern of the second resistance layer522aof each of the resistor regions512is trimmed in accordance with a predetermined resistance value to enable the pattern of the second resistance layer522ato be corresponding to the predetermined resistance value as shown inFIG.5F. In this embodiment, the operations of dividing the first resistance layer520and trimming the pattern of the second resistance layer522aare performed by using a laser, but embodiments of the present disclosure are not limited thereto.

It can be understood that the micro resistance layer fabrication method100is used in steps410-460, and thus the micro resistor fabrication method400can form a micro resistance pattern on each of the resistor regions512.

Thereafter, step470and step480are performed to form outer electrode layers530on each of the resistor regions512, and to divide the resistor regions512into a plurality of micro resistors540each having an area smaller than 0.4*0.2 mm2, as shown inFIG.5G. InFIG.5G, the outer electrode layers530cover two terminals of the micro resistor540, and are electrically connected to the first electrode pair FE, the second electrode pair BE and the second resistance layer522a. For example, the outer electrode layers530include side electrode layers, and the side electrode layers extend to the backside of the micro resistor540along two terminal sidewalls of the micro resistor540, to achieve the electric connection between the first electrode pair FE and the second electrode BE.

In some embodiments, the step470is performed to divide the substrate510into a plurality of substrate strips in accordance with the resistor columns RC, and then to form outer electrode layers530on the substrate strips. Then, the step480is performed to divide the substrate strips into the micro resistors540in accordance with the resistor rows RR.

In some embodiments, the step470is performed to form the outer electrode layers530in each of the resistor regions512, in which the substrate510is not divided. Then, the step480is performed to divide the substrate510into the micro resistors540in accordance with the resistor rows RR.

In accordance with the above descriptions, the micro resistor fabrication method400uses the micro resistance layer fabrication method100, the pattern of the resistance layer of the micro resistor540fabricated by using the micro resistor fabrication method400has less deletion, and the fabrication cost and fabrication time of the micro resistor540can be greatly decreased.

In some embodiments of the present disclosure, the micro resistance layer/micro resistor fabrication method100/400can be performed by using a sputtering process instead of using the screen printing process. Therefore, a micro resistance layer/micro resistor having a smaller resistance value (<1Ω) can be obtained.

Referring toFIG.6,FIG.6is a schematic diagram showing a flow chart of a method600for fabricating a micro resistance layer in accordance with an embodiment of the present disclosure. The micro resistance layer fabrication method600is adapted for fabrication of a micro resistance layer having an area small than or equal to 0.4*0.2 mm2. In the micro resistance layer fabrication method600, at first, step610is performed to provide a substrate710, as shown inFIG.7A. The substrate610can be formed by using insulation material, for example glass fibers, Aluminum Nitride material, Silicon-based material or Ceramic material, but embodiments of the present disclosure are not limited thereto. A plurality of product regions712are defined on the substrate710through a plurality of virtual cutting lines CL. The product region712is pre-defined for a product having a resistance layer, for example a resistor or other component having a resistance layer. In this embodiment, the product region712has an area small than or equal to 0.4*0.2 mm2, and the product regions712are arranged in a matrix having a plurality of product columns PC and a plurality of product rows PR. In some embodiments, the product region712has an area substantially equal to 0.3*0.15 mm2.

Then, step620is performed to use a sputtering process to form a first resistance layer720on the substrate710, as shown inFIG.7B. In this embodiment, the sputtering process is used to form the resistance layer720covering a whole surface of the substrate710.

Thereafter, step630and step640are performed to divide the first resistance layer720into a plurality of second resistance layer722ain accordance with the product regions712, and to trim the second resistance layer722a. In step630, each of the sub resistance layers722of the first resistance layer720is divided into the second resistance layers722aalong a length-direction of the product region712as shown inFIG.7C. Each of the sub resistance layers722extends across the product columns PC, and thus the second resistance layer722acan be defined on each of the sub resistance layers722in accordance with the product columns PC to enable each of the product regions712to encompass one second resistance layer722a. In this embodiment, because the product region712has an area small than or equal to 0.4*0.2 mm2, an area of the second resistance layer722aof each of the product regions712is small than 0.4*0.2 mm2. In step640, a pattern of the second resistance layer722aof each of the product regions712is trimmed in accordance with a predetermined resistance value (for example, forming a long opening OP by cutting the second resistance layer722a) to enable the pattern of the second resistance layer722ato be corresponding to the predetermined resistance value as shown inFIG.7D. In this embodiment, the operations of dividing the first resistance layer720and trimming the pattern of the second resistance layer722aare performed by using a laser, but embodiments of the present disclosure are not limited thereto.

Referring toFIG.8,FIG.8is a schematic diagram showing a flow chart of a method800for fabricating a micro resistor in accordance with an embodiment of the present disclosure. The micro resistor fabrication method800uses the above micro resistance layer fabrication method600to fabricate a micro resistor such as a 01005 type resistor, a 0075 type resistor or a micro resistor having a smaller size. In the micro resistor fabrication method800, at first, step810is performed to provide a substrate910, as shown inFIG.9A. The substrate910can be formed by using insulation material, for example glass fibers, Aluminum Nitride material, Silicon-based material or Ceramic material, but embodiments of the present disclosure are not limited thereto. A plurality of resistor regions912are defined on the substrate910through a plurality of virtual cutting lines CL. The resistor region912is pre-defined for a resistor. In this embodiment, the resistor region912has an area small than or equal to 0.4*0.2 mm2, and the resistor regions912are arranged in a matrix having a plurality of resistor columns RC and a plurality of resistor rows RR. In some embodiments, the resistor region912has an area substantially equal to 0.3*0.15 mm2.

Then, step820is performed to use a sputtering process to form a first resistance layer920on the substrate910, as shown inFIG.9B. In this embodiment, the sputtering process is used to form the resistance layer920covering a whole surface of the substrate910(for example, a front side of the substrate910).

Thereafter, step830and step840are performed to divide the first resistance layer920into a plurality of second resistance layer922ain accordance with the resistor regions912, and to trim the second resistance layer922a. In step830, each of the sub resistance layers922of the first resistance layer920is divided into the second resistance layers922aalong a length-direction of the resistor region912as shown inFIG.9C. Each of the sub resistance layers922extends across the resistor columns RC, and thus the second resistance layer922acan be defined on each of the sub resistance layers922in accordance with the resistor columns RC to enable each of the resistor regions912to encompass one second resistance layer922a. In this embodiment, because the resistor region912has an area small than or equal to 0.4*0.2 mm2, an area of the second resistance layer922aof each of the resistor regions912is small than 0.4*0.2 mm2. In step840, a pattern of the second resistance layer922aof each of the resistor regions912is trimmed in accordance with a predetermined resistance value (for example, forming a long opening OP by cutting the second resistance layer922a) to enable the pattern of the second resistance layer922ato be corresponding to the predetermined resistance value as shown inFIG.9D. In this embodiment, the operations of dividing the first resistance layer920and trimming the pattern of the second resistance layer922aare performed by using a laser, but embodiments of the present disclosure are not limited thereto.

Then, step850and860are performed to form a plurality of first electrode pairs FE and second electrode pairs BE respectively on a front side and a backside of the substrate910, as shown inFIG.9EandFIG.9F. In this embodiment, each of the first electrode pairs FE includes two electrodes FE1and FE2formed on the second resistance layer922aon the front side of the substrate910and covering opposite two terminals of the second resistance layer922a, as shown inFIG.9E. The back side of each of the resistor regions512encompasses one second electrode pairs BE, and each of the second electrode pairs BE includes two electrodes BE1and BE2. Each of the second electrode pairs BE includes two electrodes BE1and BE2formed on the backside of the substrate910corresponding to the two electrodes FE1and FE2, as shown inFIG.9F.

Thereafter, step870and step880are performed to form outer electrode layers930on each of the resistor regions912, and to divide the resistor regions912into a plurality of micro resistors940each having an area smaller than 0.4*0.2 mm2, as shown inFIG.9G. InFIG.9G, the outer electrode layers930cover two terminals of the micro resistor940, and are electrically connected to the first electrode pair FE, the second electrode pair BE and the second resistance layer922a. For example, the outer electrode layers930include side electrode layers, and the side electrode layers extend to the backside of the micro resistor940along two terminal sidewalls of the micro resistor940, to achieve the electric connection between the first electrode pair FE and the second electrode BE.

In some embodiments, the step870is performed to divide the substrate910into a plurality of substrate strips in accordance with the resistor columns RC, and then to form outer electrode layers930on the substrate strips. Then, the step880is performed to divide the substrate strips into the micro resistors940in accordance with the resistor rows RR.

In some embodiments, the step870is performed to form the outer electrode layers930in each of the resistor regions912, in which the substrate910is not divided. Then, the step880is performed to divide the substrate910into the micro resistors940in accordance with the resistor rows RR.