Method, system and program product that automatically generate coverage instrumentation for configuration constructs within a digital system

A method, data processing system, and program product for building an instrumented simulation model of a digital design are disclosed. According to the method, a model build tool locates, within design data collectively defining a simulation model of the digital design, a definition of a configuration construct specifying a relationship between values of one or more configuration latches within the digital design and settings of the configuration construct. In response to locating the definition of the configuration construct, the model build tool automatically creates an instrumentation entity within the design data. The instrumentation entity has one or more inputs logically coupled to the one or more configuration latches and one or more outputs for providing signals indicating characteristics of the configuration construct during simulation.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is related to the following co-pending U.S. patent applications, which are assigned to the assignee of the present application and incorporated herein by reference in their entireties:(1) U.S. patent application Ser. No. 10/366,438, filed Feb. 13, 2003; and(2) U.S. patent application Ser. No. 10/425,076, filed Apr. 28, 2003.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates in general to designing, simulating and configuring digital devices, modules and systems, and in particular, to methods and systems for computer-aided design, simulation, and configuration of digital devices, modules and systems described by a hardware description language (HDL) model.

2. Description of the Related Art

In a conventional automated design process utilizing an electronic computer-aided design (ECAD) system, a designer enters a high-level description of a digital design utilizing a hardware description language (HDL), such as VHDL, producing a digital representation of various circuit blocks and their interconnections. The ECAD system compiles the design description into a format (often called a simulation model) that is best suited for simulation. A simulator is then utilized to verify the logical correctness of the digital design prior to developing a circuit layout.

A simulator is typically a software tool that applies a list of input stimuli representing inputs of the digital design to the simulation model to generate a numerical representation of the response of the digital design. The numerical representation of the response may then either be presented on a display as a list of values or further interpreted, often by a separate software program, and presented in graphical form.

As discussed in detail in above-referenced U.S. patent application Ser. No. 10/366,438, the accuracy and completeness of the simulation data generated by the simulator can be improved by the designer including, within the HDL files defining the functional portion of the simulation model, references to instrumentation entities. These instrumentation entities, although not forming a functional portion of the digital design, can perform a number of important checking functions during simulation. Such instrumentation entities can include, for example, logical failure detectors and event and cycle counters.

The designer's control of the simulation and operation of a digital design can be further enhanced by the definition of configuration constructs (e.g., Dials) within the HDL files specifying the digital design. As described in detail in above-referenced U.S. patent application Ser. No. 10/425,076, Dials can be logically connected to the various configuration latches distributed throughout a digital design in order to provide a well-defined interface through which appropriate configuration values may be loaded into the configuration latches.

The present invention recognizes that while instrumentation entities have been defined to monitor and collect simulation data regarding the operation of the design entities comprising the functional portion of a digital design under simulation, heretofore there has been no convenient method and system for generating instrumentation entities to collect simulation data regarding configuration constructs, such as Dials. In particular, prior to the present invention, there has been no automated method and system for generating instrumentation entities to collect important simulation data, such as the number of testcases and simulation cycles that have been executed for each combination of configuration latch settings.

SUMMARY OF THE INVENTION

In view of the foregoing, the present invention provides a method, system and program product for automatically generating instrumentation entities that collect simulation data regarding configuration constructs (e.g., Dials) utilized to configure a simulation model of a digital design.

In one embodiment of the present invention, a model build tool locates, within design data collectively defining a simulation model of a digital design, a definition of a configuration construct specifying a relationship between values of one or more configuration latches within the digital design and settings of the configuration construct. In response to locating the definition of the configuration construct, the model build tool automatically creates an instrumentation entity within the design data. The instrumentation entity has one or more inputs logically coupled to the one or more configuration latches and one or more outputs for providing signals indicating characteristics of the configuration construct during simulation.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENT

With reference now to the figures, and in particular with reference toFIG. 1, there is depicted an exemplary embodiment of a data processing system that may be utilized to build and execute a simulation model containing configuration and instrumentation entities in accordance with the present invention. The depicted embodiment can be realized, for example, as a workstation, server, or mainframe computer.

As illustrated, data processing system6includes one or more processing nodes8a–8n, which, if more than one processing node8is implemented, are interconnected by node interconnect22. Processing nodes8a–8nmay each include one or more processors10, a local interconnect16, and a system memory18that is accessed via a memory controller17. Processors10a–10mare preferably (but not necessarily) identical and may comprise a processor within the POWER™ line of processors available from International Business Machines (IBM) Corporation of Armonk, New York. In addition to the registers, instruction flow logic and execution units utilized to execute program instructions, which are generally designated as processor core12, each of processors10a–10malso includes an on-chip cache hierarchy14that is utilized to stage data to the associated processor core12from system memories18.

Each of processing nodes8a–8nfurther includes a respective node controller20coupled between local interconnect16and node interconnect22. Each node controller20serves as a local agent for remote processing nodes8by performing at least two functions. First, each node controller20snoops the associated local interconnect16and facilitates the transmission of local communication transactions to remote processing nodes8. Second, each node controller20snoops communication transactions on node interconnect22and masters relevant communication transactions on the associated local interconnect16. Communication on each local interconnect16is controlled by an arbiter24. Arbiters24regulate access to local interconnects16based on bus request signals generated by processors10and compile coherency responses for snooped communication transactions on local interconnects16.

Local interconnect16is coupled, via mezzanine bus bridge26, to a mezzanine bus30. Mezzanine bus bridge26provides both a low latency path through which processors10may directly access devices among I/O devices32and storage devices34that are mapped to bus memory and/or I/O address spaces and a high bandwidth path through which I/O devices32and storage devices34may access system memory18. I/O devices32may include, for example, a display device, a keyboard, a graphical pointer, and serial and parallel ports for connection to external networks or attached devices. Storage devices34may include, for example, optical or magnetic disks that provide non-volatile storage for operating system, middleware and application software. In the present embodiment, such application software includes an ECAD system35, which can be utilized to develop, verify and simulate a digital circuit design in accordance with the methods and systems of the present invention.

Simulation models of digital circuit designs created utilizing ECAD system35are comprised of at least one, and usually many, sub-units referred to hereinafter as design entities. Referring now toFIG. 2, there is illustrated a block diagram representation of an exemplary design entity200which may be created utilizing ECAD system35. Design entity200is defined by a number of components: an entity name, entity ports, and a representation of the function performed by design entity200. Each design entity within a given model has a unique entity name (not explicitly shown inFIG. 2) that is declared in the HDL description of the design entity. Furthermore, each design entity typically contains a number of signal interconnections, known as ports, to signals outside the design entity. These outside signals may be primary input/outputs (I/Os) of an overall design or signals connected to other design entities within an overall design.

Typically, ports are categorized as belonging to one of three distinct types: input ports, output ports, and bi-directional ports. Design entity200is depicted as having a number of input ports202that convey signals into design entity200. Input ports202are connected to input signals204. In addition, design entity200includes a number of output ports206that convey signals out of design entity200. Output ports206are connected to a set of output signals208. Bi-directional ports210are utilized to convey signals into and out of design entity200. Bi-directional ports210are in turn connected to a set of bi-directional signals212. A design entity, such as design entity200, need not contain ports of all three types, and in the degenerate case, contains no ports at all. To accomplish the connection of entity ports to external signals, a mapping technique, known as a “port map”, is utilized. A port map (not explicitly depicted inFIG. 2) consists of a specified correspondence between entity port names and external signals to which the entity is connected. When building a simulation model, ECAD software35is utilized to connect external signals to appropriate ports of the design entity according to a port map specification.

As further illustrated inFIG. 2, design entity200contains a body section214that describes one or more functions performed by design entity200. In the case of a digital design, body section214contains an interconnection of logic gates, storage elements, etc., in addition to instantiations of other entities. By instantiating an entity within another entity, a hierarchical description of an overall design is achieved. For example, a microprocessor may contain multiple instances of an identical functional unit. As such, the microprocessor itself will often be modeled as a single entity. Within the microprocessor entity, multiple instantiations of any duplicated functional entities will be present.

Each design entity is specified by one or more HDL files that contain the information necessary to describe the design entity. Although not required by the present invention, it will hereafter be assumed for ease of understanding that each design entity is specified by a respective HDL file.

With reference now toFIG. 3, there is illustrated a diagrammatic representation of an exemplary simulation model300that may be employed by ECAD system35to represent a digital design (e.g., an integrated circuit chip or a computer system) in a preferred embodiment of the present invention. For visual simplicity and clarity, the ports and signals interconnecting the design entities within simulation model300have not been explicitly shown.

Simulation model300includes a number of hierarchically arranged design entities. As within any simulation model, simulation model300includes one and only one “top-level entity” encompassing all other entities within simulation model300. That is to say, top-level entity302instantiates, either directly or indirectly, all descendant entities within the digital design. Specifically, top-level entity302directly instantiates (i.e., is the direct ancestor of) two instances,304aand304b, of the same FiXed-point execution Unit (FXU) entity304and a single instance of a Floating Point Unit (FPU) entity314. FXU entity instances304, having instantiation names FXU0and FXU1, respectively, in turn instantiate additional design entities, including multiple instantiations of entity A306having instantiation names A0and A1, respectively.

Each instantiation of a design entity has an associated description that contains an entity name and an instantiation name, which must be unique among all descendants of the direct ancestor entity, if any. For example, top-level entity302has a description320including an entity name322(i.e., the “TOP” preceding the colon) and also includes an instantiation name324(i.e., the “TOP” following the colon). Within an entity description, it is common for the entity name to match the instantiation name when only one instance of that particular entity is instantiated within the ancestor entity. For example, single instances of entity B310and entity C312instantiated within each of FXU entity instantiations304aand304bhave matching entity and instantiation names. However, this naming convention is not required by the present invention as shown by FPU entity314(i.e., the instantiation name is FPU0, while the entity name is FPU).

The nesting of entities within other entities in a digital design can continue to an arbitrary level of complexity, provided that all entities instantiated, whether singly or multiply, have unique entity names and the instantiation names of all descendant entities within any direct ancestor entity are unique with respect to one another.

Associated with each design entity instantiation is a so called “instantiation identifier”. The instantiation identifier for a given instantiation is a string including the enclosing entity instantiation names proceeding from the top-level entity instantiation name. For example, the design instantiation identifier of instantiation312aof entity C312within instantiation304aof FXU entity304is “TOP.FXU0.B.C”. This instantiation identifier serves to uniquely identify each instantiation within a simulation model.

As discussed above, a digital design, whether realized utilizing physical integrated circuitry or as a software model such as simulation model300, typically includes configuration latches utilized to configure the digital design for proper operation. In contrast to prior art design methodologies that employ stand-alone configuration software to determine values for the configuration latches, the present invention employs a configuration specification language that permits a digital designer to specify configuration values for signals as a natural part of the design process. In particular, the configuration specification language of the present invention permits a design configuration to be specified utilizing statements either embedded in one or more HDL files specifying the digital design (as illustrated inFIG. 4A) or in one or more external configuration files referenced by the one or more HDL files specifying the digital design (as depicted inFIG. 4B).

Referring now toFIG. 4A, there is depicted an exemplary HDL file400, in this case a VHDL file, including embedded configuration statements in accordance with the present invention. In this example, HDL file400specifies entity A306of simulation model300and includes three sections of VHDL code, namely, a port list402that specifies ports202,206and210, signal declarations404that specify the signals within body section214, and a design specification406that specifies the logic and functionality of body section214. Interspersed within these sections are conventional VHDL comments denoted by an initial double-dash (“--”). In addition, embedded within design specification406are one or more configuration specification statements in accordance with the present invention, which are collectively denoted by reference numerals408and410. As shown, these configuration specification statements are written in a special comment form beginning with “--##” in order to permit a compiler to easily distinguish the configuration specification statements from the conventional HDL code and HDL comments. Configuration specification statements preferably employ a syntax that is insensitive to case and white space.

As further illustrated inFIG. 4A, HDL file400also includes an instrumentation entity instantiation420distinguished by a special comment form beginning with “--!!”. Instrumentation entity instantiation420identifies by name (“Instr_entity_name.vhdl”) an external instrumentation entity HDL file422containing an HDL (in this case, VHDL) definition of an instrumentation entity that is associated with and that collects simulation data regarding the operation of entity A306defined by HDL file400. A detailed description of instrumentation entity HDL file422may be found in above-referenced U.S. patent application Ser. No. 10/366,438.

With reference now toFIG. 4B, there is illustrated an exemplary HDL file400′ that includes a reference to an external configuration file containing one or more configuration specification statements in accordance with the present invention. As indicated by prime notation (′), HDL file400′ is identical to HDL file400in all respects except that configuration specification statements408,410are replaced with one or more (and in this case only one) configuration file reference statement412referencing a separate configuration file414containing configuration specification statements408,410.

Configuration file reference statement412, like the embedded configuration specification statements illustrated inFIG. 4A, is identified as a configuration statement by the identifier “--##”. Configuration file reference statement412includes the directive “cfg_file”, which instructs the compiler to locate a separate configuration file414, and the filename of the configuration file (i.e., “file00”). Configuration files, such as configuration file412, preferably all employ a selected filename extension (e.g., “.cfg”) so that they can be easily located, organized, and managed within the file system employed by data processing system6.

As discussed further below with reference toFIG. 8, configuration specification statements and instrumentation specification statements, whether embedded within an HDL file or collected in one or more configuration files414, are processed by a compiler together with the associated HDL files.

In accordance with a preferred embodiment of the present invention, configuration specification statements, such as configuration specification statements408,410, facilitate configuration of configuration latches within a digital design by instantiating one or more instances of a configuration construct referred to herein generically as a “Dial.” A Dial's function is to map between an input value and one or more output values. In general, such output values ultimately directly or indirectly specify configuration values of configuration latches. Each Dial is associated with a particular design entity in the digital design, which by convention is the design entity specified by the HDL source file containing the configuration specification statement or configuration file reference statement that causes the Dial to be instantiated. Consequently, by virtue of their association with particular design entities, which all have unique instantiation identifiers, Dials within a digital design can be uniquely identified as long as unique Dial names are employed within any given design entity. As will become apparent, many different types of Dials can be defined, beginning with a Latch Dial (or “LDial”).

Referring now toFIG. 5A, there is depicted a representation of an exemplary LDial500. In this particular example, LDial500, which has the name “bus ratio”, is utilized to specify values for configuration latches in a digital design in accordance with an enumerated input value representing a selected ratio between a component clock frequency and bus clock frequency.

As illustrated, LDial500, like all Dials, logically has a single input502, one or more outputs504, and a mapping table503that maps each input value to a respective associated output value for each output504. That is, mapping table503specifies a one-to-one mapping between each of one or more unique input values and a respective associated unique output value. Because the function of an LDial is to specify the legal values of configuration latches, each output504of LDial500logically controls the value loaded into a respective configuration latch505. To prevent conflicting configurations, each configuration latch505is directly specified by one and only one Dial of any type that is capable of setting the configuration latch505.

At input502, LDial500receives an enumerated input value (i.e., a string) among a set of legal values including “2:1”, “3:1” and “4:1”. The enumerated input value can be provided directly by software (e.g., by a software simulator or service processor firmware) or can be provided by the output of another Dial, as discussed further below with respect toFIG. 7A. For each enumerated input value, the mapping table503of LDial500indicates a selected binary value (i.e., “0” or “1”) for each configuration latch505.

With reference now toFIG. 5B, there is illustrated a diagrammatic representation of a simulation model logically including Dials. Simulation model300′ ofFIG. 5B, which as indicated by prime notation includes the same design entities arranged in the same hierarchical relation as simulation model300ofFIG. 3, illustrates two properties of Dials, namely, replication and scope.

Replication is a process by which a Dial that is specified in or referenced by an HDL file of a design entity is automatically instantiated each time that the associated design entity is instantiated. Replication advantageously reduces the amount of data entry a designer is required to perform to create multiple identical instances of a Dial. For example, in order to instantiate the six instances of LDials illustrated inFIG. 5B, the designer need only code two LDial configuration specification statements utilizing either of the two techniques illustrated inFIGS. 4A and 4B. That is, the designer codes a first LDial configuration specification statement (or configuration file reference statement pointing to an associated configuration file) into the HDL file of design entity A306in order to automatically instantiate LDials506a0,506a1,506b0and506b1within entity A instantiations306a0,306a1,306b0and306b1, respectively. The designer codes a second LDial configuration specification statement (or configuration file reference statement pointing to an associated configuration file) into the HDL file of design entity FXU304in order to automatically instantiate LDials510aand510bwithin FXU entity instantiations304aand304b, respectively. The multiple instances of the LDials are then created automatically as the associated design entities are replicated by the compiler. Replication of Dials within a digital design can thus significantly reduce the input burden on the designer as compared to prior art methodologies in which the designer had to individually enumerate in the configuration software each configuration latch value by hand. It should be noted that the property of replication does not necessarily require all instances of a Dial to generate the same output values; different instances of the same Dial can be set to generate different outputs by providing them different inputs.

The “scope” of a Dial is defined herein as the set of entities to which the Dial can refer in its specification. By convention, the scope of a Dial comprises the design entity with which the Dial is associated (i.e., the design entity specified by the HDL source file containing the configuration specification statement or configuration file reference statement that causes the Dial to be instantiated) and any design entity contained within the associated design entity (i.e., the associated design entity and its descendents). Thus, a Dial is not constrained to operate at the level of the design hierarchy at which it is instantiated, but can also specify configuration latches at any lower level of the design hierarchy within its scope. For example, LDials510aand510b, even though associated with FXU entity instantiations304aand304b, respectively, can specify configuration latches within entity C instantiations312aand312b, respectively.

FIG. 5Billustrates another important property of LDials (and other Dials that directly specify configuration latches). In particular, as shown diagrammatically inFIG. 5B, designers, who are accustomed to specifying signals in HDL files, are permitted in a configuration specification statement to specify signal states set by a Dial rather than values to be loaded into an “upstream” configuration latch that determines the signal state. Thus, in specifying LDial506, the designer can specify possible signal states for a signal514set by a configuration latch512. Similarly, in specifying LDial510, the designer can specify possible signal states for signal522set by configuration latch520. The ability to specify signal states rather than latch values not only coincides with designers' customary manner of thinking about a digital design, but also reduces possible errors introduced by the presence of inverters between the configuration latch512,520and the signal of interest514,522, as discussed further below.

Referring now toFIG. 5C, there is depicted another diagrammatic representation of a simulation model including an LDial. As indicated by prime notation, simulation model300″ ofFIG. 5Cincludes the same design entities arranged in the same hierarchical relation as simulation model300ofFIG. 3.

As shown, simulation model300″ ofFIG. 5Cincludes an LDial524associated with top-level design entity302. LDial524specifies the signal states of each signal sig1514, which is determined by a respective configuration latch512, the signal states of each signal sig2522, which is determined by a respective configuration latch520, the signal state of signal sig4532, which is determined by configuration latch530, and the signal state of signal sig3536, which is determined by configuration latch534. Thus, LDial524configures the signal states of numerous different signals, which are all instantiated at or below the hierarchy level of LDial524(which is the top level).

As discussed above with respect toFIGS. 4A and 4B, LDial524is instantiated within top-level entity302of simulation model300″ by embedding within the HDL file of top-level entity302a configuration specification statement specifying LDial524or a configuration file reference statement referencing a separate configuration file containing a configuration specification statement specifying LDial524. In either case, an exemplary configuration specification statement for LDial524is as follows:

The exemplary configuration specification statement given above begins with the keyword “LDial,” which specifies that the type of Dial being declared is an LDial, and the Dial name, which in this case is “bus ratio.” Next, the configuration specification statement enumerates the signal names whose states are controlled by the LDial. As indicated above, the signal identifier for each signal is specified hierarchically (e.g., FXU0.A0.SIG1 for signal514a0) relative to the default scope of the associated design entity so that different signal instances having the same signal name are distinguishable. Following the enumeration of the signal identifiers, the configuration specification statement includes a mapping table listing the permitted enumerated input values of the LDial and the corresponding signal values for each enumerated input value. The signal values are associated with the signal names implicitly by the order in which the signal names are declared. It should again be noted that the signal states specified for all enumerated values are unique, and collectively represent the only legal patterns for the signal states.

Several different syntaxes can be employed to specify the signal states. In the example given above, signal states are specified in either binary format, which specifies a binary constant preceded by the prefix “0b”, or in hexadecimal format, which specifies a hexadecimal constant preceded by the prefix “0x”. Although not shown, signal states can also be specified in integer format, in which case no prefix is employed. For ease of data entry, the configuration specification language of ECAD system35also preferably supports a concatenated syntax in which one constant value, which is automatically extended with leading zeros, is utilized to represent the concatenation of all of the desired signal values. In this concatenated syntax, the mapping table of the configuration specification statement given above can be rewritten as:{2:1=>0;3:1=>0×183821;4:1=>0×1FFFFF}; in order to associate enumerated input value 2:1 with a concatenated bit pattern of all zeros, to associate the enumerated input value 3:1 with the concatenated bit pattern ‘0b110000011100000100001’, and to associate the enumerated input value 4:1 with a concatenated bit pattern of all ones.

With reference now toFIG. 5D, there is illustrated a diagrammatic representation of a special case of an LDial having a one-bit output, which is defined herein as a Switch. As shown, a Switch540has a single input502, a single 1-bit output504that controls the setting of a configuration latch505, and a mapping table503that maps each enumerated input value that may be received at input502to a 1-bit output value driven on output504.

Because Switches frequently comprise a significant majority of the Dials employed in a digital design, it is preferable if the enumerated value sets for all Switches in a simulation model of a digital design are the same (e.g., “ON”/“OFF”). In a typical embodiment of a Switch, the “positive” enumerated input value (e.g., “ON”) is mapped by mapping table503to an output value of0b1and the “negative” enumerated input value (e.g., “OFF”) is mapped to an output value of0b0. In order to facilitate use of logic of the opposite polarity, a Negative Switch or NSwitch declaration is also preferably supported that reverses this default correspondence between input values and output values in mapping table503.

The central advantage to defining a Switch primitive is a reduction in the amount of input that designers are required to enter. In particular, to specify a comparable 1-bit LDial, a designer would be required to enter a configuration specification statement of the form:

LDial mode (signal) ={ON =>b1;OFF =>b0};
A Switch performing the same function, on the other hand, can be specified with the configuration specification statement:Switch mode (signal);
Although the amount of data entry eliminated by the use of Switches is not particularly significant when only a single Switch is considered, the aggregate reduction in data entry is significant when the thousands of switches in a complex digital design are taken into consideration.

Referring now toFIG. 6A, there is depicted a diagrammatic representation of an Integer Dial (“IDial”) in accordance with a preferred embodiment of the present invention. Like an LDial, an IDial directly specifies the value loaded into each of one or more configuration latches605by indicating within mapping table603a correspondence between each input value received at an input602and an output value for each output604. However, unlike LDials, which can only receive as legal input values the enumerated input values explicitly set forth in their mapping tables503, the legal input value set of an IDial includes all possible integer values within the bit size of output604. (Input integer values containing fewer bits than the bit size of output(s)604are right justified and extended with zeros to fill all available bits.) Because it would be inconvenient and tedious to enumerate all of the possible integer input values in mapping table603, mapping table603simply indicates the manner in which the integer input value received at input602is applied to the one or more outputs604.

IDials are ideally suited for applications in which one or more multi-bit registers must be initialized and the number of legal values includes most values of the register(s). For example, if a 4-bit configuration register comprising 4 configuration latches and an 11-bit configuration register comprising 11 configuration latches were both to be configured utilizing an LDial, the designer would have to explicitly enumerate up to 215input values and the corresponding output bit patterns in the mapping table of the LDial. This case can be handled much more simply with an IDial utilizing the following configuration specification statement:IDial cnt_value (sig1(0..3), sig2(0..10));
In the above configuration specification statement, “IDial” declares the configuration construct as an IDial, “cnt_value” is the name of the IDial, “sig1” is a 4-bit signal output by the 4-bit configuration register and “sig2” is an 11-bit signal coupled to the 11-bit configuration register. In addition, the ordering and number of bits associated with each of sig1and sig2indicate that the 4 high-order bits of the integer input value will be utilized to configure the 4-bit configuration register associated with sig1and the 11 lower-order bits will be utilized to configure the 11-bit configuration register associated with sig2. Importantly, although mapping table603indicates which bits of the integer input values are routed to which outputs, no explicit correspondence between input values and output values is specified in mapping table603.

IDials may also be utilized to specify the same value for multiple replicated configuration registers, as depicted inFIG. 6B. In the illustrated embodiment, an IDial610, which can be described as an IDial “splitter”, specifies the configuration of three sets of replicated configuration registers each comprising 15 configuration latches605based upon a single 15-bit integer input value. An exemplary configuration specification statement for instantiating IDial610may be given as follows:

Although the configuration of a digital design can be fully specified utilizing LDials alone or utilizing LDials and IDials, in many cases it would be inefficient and inconvenient to do so. In particular, for hierarchical digital designs such as that illustrated inFIG. 5C, the use of LDials and/or IDials alone would force many Dials to higher levels of the design hierarchy, which, from an organizational standpoint, may be the responsibility of a different designer or design group than is responsible for the design entities containing the configuration latches controlled by the Dials. As a result, proper configuration of the configuration latches would require not only significant organizational coordination between design groups, but also that designers responsible for higher levels of the digital design learn and include within their HDL files details regarding the configuration of lower level design entities. Moreover, implementing Dials at higher levels of the hierarchy means that lower levels of the hierarchy cannot be independently simulated since the Dials controlling the configuration of the lower level design entities are not contained within the lower level design entities themselves.

In view of the foregoing, the present invention recognizes the utility of providing a configuration construct that supports the hierarchical combination of Dials to permit configuration of lower levels of the design hierarchy by lower-level Dials and control of the lower-level Dials by one or more higher-level Dials. The configuration specification language of the present invention terms a higher-level Dial that controls one or more lower-level Dials as a Control Dial (“CDial”).

Referring now toFIG. 7A, there is depicted a diagrammatic representation of a CDial700ain accordance with the present invention. CDial700a, like all Dials, preferably has a single input702, one or more outputs704, and a mapping table703that maps each input value to a respective associated output value for each output704. Unlike LDials and IDials, which directly specify configuration latches, a CDial700does not directly specify configuration latches. Instead, a CDial700controls one or more other Dials (i.e., CDials and/or LDials and/or IDials) logically coupled to CDial700in an n-way “Dial tree” in which each lower-level Dial forms at least a portion of a “branch” that ultimately terminates in “leaves” of configuration latches. Dial trees are preferably constructed so that no Dial is instantiated twice in any Dial tree.

In the exemplary embodiment given inFIG. 7A, CDial700areceives at input702an enumerated input value (i.e., a string) among a set of legal values including “A”, . . . , “N”. If CDial700a(or an LDial or IDial) is a top-level Dial (i.e., there are no Dials “above” it in a Dial tree), CDial700areceives the enumerated input value directly from software (e.g., simulation software or firmware). Alternatively, if CDial700aforms part of a “branch” of a dial tree, then CDial700areceives the enumerated input value from the output of another CDial. For each legal enumerated input value that can be received at input702, CDial700aspecifies a selected enumerated value or bit value for each connected Dial (e.g., Dials700b,500and600) in mapping table703. The values in mapping table703associated with each output704are interpreted by ECAD system35in accordance with the type of lower-level Dial coupled to the output704. That is, values specified for LDials and CDials are interpreted as enumerated values, while values specified for IDials are interpreted as integer values. With these values, each of Dials700b,500and600ultimately specifies, either directly or indirectly, the values for one or more configuration latches705.

With reference now toFIG. 7B, there is illustrated another diagrammatic representation of a simulation model containing a Dial tree including a top-level CDial that controls multiple lower-level LDials. As indicated by prime notation, simulation model300′″ ofFIG. 7Bincludes the same design entities arranged in the same hierarchical relation as simulation model300ofFIG. 3and contains the same configuration latches and associated signals as simulation model300″ ofFIG. 5C.

As shown, simulation model300′″ ofFIG. 7Bincludes a top-level CDial710associated with top-level design entity302. Simulation model300′″ further includes four LDials712a,712b,714and716. LDial712a, which is associated with entity instantiation FXU0304a, controls the signal states of each signal sig1514a, which is determined by a respective configuration latch512a, and the signal state of signal sig2522a, which is determined by configuration latch520a. LDial712b, which is a replication of LDial712aassociated with entity instantiation FXU1304b, similarly controls the signal states of each signal sig1514b, which is determined by a respective configuration latch512b, and the signal state of signal sig2522b, which is determined by configuration latch520b. LDial714, which is associated with top-level entity302, controls the signal state of signal sig4532, which is determined by configuration latch530. Finally, LDial716, which is associated with entity instantiation FPU0314, controls the signal state of signal sig3536, which is determined by configuration latch534. Each of these four LDials is controlled by CDial710associated with top-level entity302.

As discussed above with respect toFIGS. 4A and 4B, CDial710and each of the four LDials depicted inFIG. 7Bis instantiated within the associated design entity by embedding a configuration specification statement (or a configuration file reference statement pointing to a configuration file containing a configuration specification statement) within the HDL file of the associated design entity. An exemplary configuration specification statement utilized to instantiate each Dial shown inFIG. 7Bis given below:

By implementing a hierarchical Dial tree in this manner, several advantages are realized. First, the amount of software code that must be entered is reduced since the automatic replication of LDials712within FXU entity instantiations304aand304ballows the code specifying LDials712to be entered only once. Second, the organizational boundaries of the design process are respected by allowing each designer (or design team) to specify the configuration of signals within the design entity for which he is responsible. Third, coding of upper level Dials (i.e., CDial710) is greatly simplified, reducing the likelihood of errors. Thus, for example, the CDial and LDial collection specified immediately above performs the same function as the “large” LDial specified above with reference toFIG. 5C, but with much less complexity in any one Dial.

Many Dials, for example, Switches utilized to disable a particular design entity in the event an uncorrectable error is detected, have a particular input value that the Dial should have in nearly all circumstances. For such Dials, the configuration specification language of the present invention permits a designer to explicitly specify in a configuration specification statement a default input value for the Dial. In an exemplary embodiment, a Default value is specified by including “=default value” following the specification of a Dial and prior to the concluding semicolon. For example, a default value for a CDial, can be given as follows:

CDial BusRatio (FXU0.BUSRATIO, FXU1.BUSRATIO,FPU0.BUSRATIO, BUSRATIO)={2:1 => 2:1, 2:1, 2:1, 2:1;3:1 => 3:1, 3:1, 3:1, 3:1;4:1 => 4:1, 4:1, 4:1, 4:1} = 2:1;
It should be noted that for CDials and LDials, the specified default value is required to be one of the legal enumerated values, which are generally (i.e., except for Switches) listed in the mapping table. For Switches, the default value must be one of the predefined enumerated values of “ON” and “OFF”.

A default value for an IDial can similarly be specified as follows:

The use of default values for Dials is subject to a number of rules. First, a default value may be specified for any type of Dial including LDials, IDials (including those with split outputs) and CDials. Second, if default values are specified for multiple Dials in a multiple-level Dial tree, only the highest-level default value affecting each “branch” of the Dial tree is applied (including that specified for the top-level Dial), and the remaining default values, if any, are ignored. Despite this rule, it is nevertheless beneficial to specify default values for lower-level Dials in a Dial tree because the default values may be applied in the event a smaller portion of a model is independently simulated, as discussed above. In the event that the combination of default values specified for lower-level Dials forming the “branches” of a Dial tree do not correspond to a legal output value set for a higher-level Dial, the compiler will flag an error. Third, a default value is overridden when a Dial receives an input to actively set the Dial.

By specifying default values for Dials, a designer greatly simplifies use of Dials by downstream organizational groups by reducing the number of Dials that must be explicitly set for simulation or hardware configuration. In addition, as discussed further below, use of default values assists in auditing which Dials have been actively set.

In addition to defining syntax for configuration specification statements specifying Dials, the configuration specification language of the present invention supports at least two additional HDL semantic constructs: comments and attribute specification statements. A comment, which may have the form:BusRatio.comment=“The bus ratio Dial configures the circuit in accordance with a selected processor/interconnect frequency ratio”;
permits designers to associate arbitrary strings delimited by quotation marks with particular Dial names. As discussed below with reference toFIG. 8, these comments are processed during compilation and included within a configuration documentation file in order to explain the functions, relationships, and appropriate settings of the Dials.

Attribute specification statements are statements that declare an attribute name and attribute value and associate the attribute name with a particular Dial name. For example, an attribute specification statement may have the form:BusRatio.attribute (myattribute)=scom57(0:9);
In this example, “BusRatio.attribute” declares that this statement is an attribute specification statement associating an attribute with a Dial having “BusRatio” as its Dial name, “myattribute” is the name of the attribute, and “scom57(0:9)” is a string that specifies the attribute value. Attributes support custom features and language extensions to the base configuration specification language.

Referring now toFIG. 8, there is depicted a high level flow diagram of a model build process in which HDL files containing configuration and instrumentation statements are compiled to obtain a simulation executable model and a simulation configuration database for a digital design. The illustrated process, in addition to generating design entities comprising the functional portion of a digital design and configuration constructs for configuring configuration latches within the design entities, creates instrumentation entities to track desired characteristics of the design entities and configuration constructs. The depicted process includes execution of an instrumentation load tool that is cognizant of configuration (e.g., Dial) information placed in design intermediate (proto) files and utilizes this information and to automatically create instrumentation entities to track the characteristics of the appropriate Dials.

Simulation data regarding Dials is helpful for simulation and design teams, which would like to be able to determine whether all the various settings of the Dials have, in fact, been tested during simulation and to determine what percentage of the simulation effort has been applied to each of the different settings of the Dials. In addition, attaching instrumentation entities to Dials advantageously facilitates automatic checking of Dial settings prior to simulation testing to verify that the Dials are in legal configurations. While the values to which Dials may be set can be constrained by APIs, other means, including direct alteration of latch values and logical errors in the design, can still alter Dials' underlying configuration latches to illegal states.

As shown inFIG. 8, the process begins with one or more HDL source code files800, which include one or more design entity HDL files defining one or more design entities comprising the digital design to be simulated. As described above with reference toFIGS. 4A and 4B, these design entity HDL files include configuration specification statements and/or configuration file reference statements referring to one or more configuration specification reference files802. Such configuration specification statements and/or configuration specification reference files define Dials (and, optionally, other configuration constructs) associated with the design entities defined by the design entity HDL files.

HDL source code files800may further include one or more instrumentation entity HDL files defining instrumentation entities for collecting simulation data regarding the design entities comprising the digital design. The designer need not, however, explicitly define instrumentation entities within HDL source code files800that collect simulation data regarding configuration constructs (e.g., Dials) because these instrumentation entities will be automatically generated during the model build process.

HDL compiler804processes HDL file(s)800and configuration specification file(s)802, if any, beginning with the top level entity of a simulation model and proceeding in a recursive fashion through all HDL file(s)800describing a complete simulation model. In addition to (possibly) conventional HDL compilation of the design entity HDL files, HDL compiler804compiles the HDL files defining instrumentation entities, as described in U.S. patent application Ser. No. 10/366,438. HDL compiler804also places information in design intermediate data806to signify to instrumentation load tool820which design entities include instrumentation entities. In addition, HDL compiler804places information about the configuration constructs, if any, in design intermediate data806. Thus, as HDL compiler804processes each HDL file800, HDL compiler804creates “markers” in the design intermediate (or proto) data806produced in memory to identify instrumentation and configuration statements embedded in the HDL code and any configuration specification files referenced by an embedded configuration file reference statement. In a preferred embodiment, design intermediate data806comprise intermediate design files defining the various design entities, instrumentation entities and configuration constructs within the digital design, as well as one or more data structures defining the relationship of various instantiations of the design and instrumentation entities and configuration constructs.

The design intermediate data806in memory are then processed by a configuration compiler808in order to create a configuration documentation file812and a configuration database814. Configuration documentation file812lists, in human-readable format, information describing the Dials associated with the simulation model. The information includes the Dials' names, their mapping tables, the structure of Dial trees, if any, instance information, etc. In addition, as noted above, configuration documentation file812includes strings contained in comment statements describing the functions and settings of the Dials in the digital design. In this manner, configuration documentation suitable for use with both a simulation model and a hardware implementation of a digital design is aggregated in a “bottom-up” fashion from the designers responsible for creating the Dials. The configuration documentation is then made available to all downstream organizational groups involved in the design, simulation, laboratory hardware evaluation, and commercial hardware implementation of the digital design.

Configuration database814contains a number of data structures pertaining to Dials. As described in U.S. patent application Ser. No. 10/425,076, these data structures include Dial data structures describing Dial entities, latch data structures, and Dial instance data structures. These data structures associate particular Dial inputs with particular configuration values used to configure the digital design (i.e., simulation executable model826). In a preferred embodiment, the configuration values can be specified in terms of either signal states or configuration latch values, and the selection of which values are used is user-selectable. Configuration database814is accessed via Application Programming Interface (API) routines during simulation of the digital design utilizing simulation executable model826and is further utilized to generate similar configuration databases for configuring physical realizations of the digital design. In a preferred embodiment, the APIs are designed so that only top-level Dials (i.e., LDials, IDials or CDials without a CDial logically “above” them) can be set and all Dial values can be read.

Instrumentation load tool820also processes design intermediate data806to create and/or alter the in-memory data structures of the simulation model in order to add the instrumentation entities specified within design intermediate data806to the simulation model and to connect the instrumentation entities to the appropriate design entities. In addition, instrumentation load tool820searches through all the design intermediate data806to find Dials that can be instrumented and automatically creates an instrumentation entity for each design entity containing at least one Dial that can be instrumented. The in-memory data resulting from the processing performed by instrumentation load tool820are referred to as instrumented design intermediate (proto) data822. Additional detail regarding an exemplary method of processing of design intermediate (proto) data806by instrumentation load tool820to instantiate instrumentation entities and attach the instrumentation entities to associated design entities is given below in the description ofFIG. 9and in the description ofFIG. 4Dof above-referenced U.S. patent application Ser. No. 10/366,438.

Instrumented design intermediate data822are then received as inputs by model build tool824. Model build tool824processes instrumented design intermediate data822into a simulation executable model826that, when executed, models the logical functions of the digital design, which may represent, for example, a portion of an integrated circuit, an entire integrated circuit or module, or a digital system including multiple integrated circuits or modules.

It should be noted that no designer intervention is required during the entire model build process and that instrumentation entities for Dials are created automatically by intrumentation load tool820. However, in a preferred embodiment, options regarding the automated generation of instrumentation for Dials are provided for user selection at model build time. For example, a user can preferably select the Dials to which instrumentation will automatically be applied.

In general, the process illustrated inFIG. 8preferably automatically instruments only those Dials having a reasonably small number of values, for example, LDials (and by implication Switches), CDials, and small IDials. Large IDials (i.e., those exceeding a width determined by default or by the user) are preferably not automatically instrumented because the large number of possible values for such IDials could generate an undesirably large number of counters. For example, fully instrumenting a 20-bit IDial would, in theory, lead to the creation of at least one event counter for each of the over one million possible settings of the IDial. Accordingly, instrumentation load tool820typically searches and instruments only LDials, CDials, and those IDials having less than a user-specified or default width (e.g., 7 bits). With reference now toFIG. 9, there is illustrated a more detailed logical flowchart of an exemplary method by which instrumentation load tool820automatically instruments Dials within a digital design. To enhance understanding,FIG. 9is described below with reference to exemplary design entity1000depicted inFIG. 10. As shown, design entity1000includes a number of configuration latches1030a–1030nfor configuring design entity1000. The various legal combinations of values for configuration latches1030form the settings of a Dial defined within design intermediate data806.

The automatic instrumentation process depicted inFIG. 9begins at block900after instrumentation load tool820has completed the instrumentation process for any designer-specified instrumentation, as described in U.S. patent application Ser. No. 10/366,438. As disclosed therein, this preliminary instrumentation process includes the creation of an instrumentation logic block1002(FIG. 10) within the top-level design entity of the simulation model. Instrumentation logic block1002includes counters and associated logic to support the counting of events signaled by instrumentation entities within the simulation model.

Following block900the process illustrated inFIG. 9thereafter proceeds to block901, which illustrates instrumentation load tool820automatically creating logic within instrumentation logic block1002to support the collection of simulation data of interest regarding Dials. In the exemplary embodiment, it is assumed that for each Dial to be instrumented, at least one and up to three classes of simulation data may be of interest, namely, the number of testcases run in each legal setting of the Dial, the number of simulation cycles run in each legal setting of the Dial, and logical failures causing the Dial to assume an illegal setting.

As shown inFIG. 10, the logic created by instrumentation load tool820at block901ofFIG. 9includes a testcase_qualifier latch1006. As described further below, testcase_qualifier latch1006outputs a global testcase_qualifier signal1008utilized to qualify counting of testcases by testcase count instrumentation. In this manner, the Run Time eXecutive (RTX) program that controls simulation is able to specify (e.g., through an API) exactly when to increment testcase counts by setting global testcase_qualifier latch1006to pulse testcase_qualifier signal1008once during execution of each testcase.

The logic created by instrumentation load tool820at block901ofFIG. 9further includes a failure_qualifier latch1012. Failure_qualifier latch1012outputs a global failure_qualifier signal1014, which is activated by the RTX (through appropriate setting of failure_qualifier latch1012via an API) to indicate when fail events detected by Dial instrumentation logic are of interest. In general, it is common for Dials in the simulation model to be in undefined or illegal state during the initial cycles of a simulation run while the simulation model is being initialized and prepared to execute a testcase. Because the simulation model has no internal mechanism to distinguish such transient illegal states from logical failures of interest, the RTX preferably disables the monitoring of the failure events for Dials during initialization. After initialization is complete and the simulation model has stabilized, the RTX generally enables the global failure_qualifier signal1012for the remainder of the simulation run of the current testcase by setting failure_qualifier latch1012.

Following block901, the automatic instrumentation process illustrated inFIG. 9proceeds to block902, which depicts instrumentation load tool820entering a processing loop in which instrumentation load tool820processes each design entity specified within design intermediate data806. If instrumentation load tool820has already processed all design entities specified by design intermediate data806, then instrumentation load tool820ends execution of the automatic instrumentation process at block904. If, however, instrumentation load tool820detects another design entity to be processed, for example, design entity1000ofFIG. 10, the process then proceeds to block912.

Block912depicts instrumentation load tool820determining whether or not the design entity (hereafter assumed to be design entity1000ofFIG. 10) has already been instrumented, for example, through an incremental compilation process in which instrumented design entities are stored in non-volatile storage for inclusion in a later created simulation model. If instrumentation load tool820determines that design entity1000has already been instrumented, the process returns to block902, which has been described. If, however, instrumentation load tool820determines at bock912that design entity1000has not already been instrumented, instrumentation load tool820scans the design intermediate data describing design entity1000to determine whether or not the design intermediate data contains a reference to a Dial (e.g., Switch, LDial, CDial, or “small” IDial) to be instrumented, as shown at block914. If not, the process returns to block902, which has been described.

Returning to block914, in response to determining that the design intermediate data of design entity1000contains at least one Dial to be instrumented, the process proceeds to block916. Block916illustrates instrumentation load tool820instantiating an embedded instrumentation entity1020within design entity1000. The function of instrumentation entity1020is to generate, for each instrumented Dial associated with design entity1000, one or more logic signals indicating the occurrence of events of interest (e.g., testcase count events, fail events, simulation cycle events). These event signals are recorded by associated counters within instrumentation logic block1002for subsequent analysis, as described in U.S. patent application Ser. No. 10/366,438. As further described in U.S. patent application Ser. No. 10/366,438, instrumentation load tool820names embedded instrumentation entity1020utilizing a special format in order to avoid name collisions with user-created instrumentation entities or design entities.

Following the creation of instrumentation entity1020at block916, instrumentation load tool820examines the information within design intermediate data806for a next Dial to be instrumented, as illustrated at block920. Next, instrumentation load tool820automatically generates instrumentation within instrumentation entity1020to gather simulation data on the Dial selected at block920. In the illustrated embodiment, the instrumentation automatically created by instrumentation load tool820includes, at a minimum, failure detection instrumentation, that is, instrumentation to detect an illegal state of the Dial while global failure_qualifier1014is asserted. In addition, instrumentation load tool820optionally creates cycle count instrumentation and testcase count instrumentation in response to default or user-selected settings chosen at model build time. It will be appreciated that this implementation is merely illustrative and that, in other embodiments, additional instrumentation (or no instrumentation) could be generated for a particular Dial based upon Dial type, user-selected settings, or other factors.

In order to create failure detection instrumentation for a selected Dial, instrumentation load tool820first creates within instrumentation entity1020a decoder1022relating values of the underlying configuration latches1030a-1030nassociated with the Dial to each of the Dial's legal settings, as illustrated at block922. If the Dial is an LDial or Switch, instrumentation load tool820constructs decoder1022directly from the mapping table503(or if a Switch, the inherent mapping table) of the Dial specified in design intermediate data806(possibly after tracing back specified signals to underlying latches). If, however, the Dial is a CDial, instrumentation load tool820constructs decoder1022by recursively examining the Dial tree controlled by the current CDial to determine the overall set of configuration latches1030a–1030ncontrolled by the CDial and their associated legal values. Decoder1022thus contains all of the logic necessary to decode all the legal patterns of configuration latches1030a–1030nand produce decode signals1024a–1024meach corresponding to one of the legal values for the Dial.

As further illustrated at block922ofFIG. 10, after decoder1022is created, instrumentation load tool820creates input signals1032a–1032nto connect the underlying configuration latches1030a–1030nassociated with the Dial to embedded instrumentation entity1020and then to decoder1022.

Following block922, instrumentation load tool820creates failure instrumentation for the Dial at block924. Creating the failure instrumentation includes inserting within instrumentation entity1020a NOR gate1026and an AND gate1028. NOR gate1026receives all of decode signals1024a–1024mas inputs and produces an unqualified fail signal1027, which is then qualified with global failure_qualifier signal1014by AND gate1028to obtain a qualified fail signal1040indicating whether or not the Dial is in one of its legal settings. Qualified fail signal1040is connected to instrumentation logic block1002. If qualified fail signal1040is asserted, a failure event is recorded by instrumentation logic block1002, and simulation is halted.

The process then proceeds from block924to blocks930-936, which collectively represent the selective creation of testcase count and cycle count instrumentation. In particular, instrumentation load tool820determines at block930whether or not cycle count instrumentation has been disabled for at least the current Dial by a user-specified setting. If so, the process passes directly from block930to block934, which is described below. If, however, cycle count instrumentation has not been disabled, instrumentation load tool820creates the cycle count instrumentation within instrumentation entity1020. In particular, instrumentation load tool820creates cycle count signals1050and connects each of them to a respective one of decode signals1024a–1024m. Cycle count signals1050are automatically connected by instrumentation load tool820to respective event counters within instrumentation logic block1002in order to record the number of simulation cycles that are executed in each of the Dial's legal settings.

The process shown inFIG. 9proceeds from block932(or block930) to block934, which depicts instrumentation load tool820determining whether or not testcase count instrumentation has been disabled for at least the present Dial. If so, the process passes to block940, which is described below. If, however, testcase count instrumentation has not been disabled for the present Dial, instrumentation load tool820creates testcase count instrumentation within instrumentation entity1020. In particular, instrumentation load tool820inserts AND gates1060to qualify each decode signal1024with global testcase_qualifier signal1008to obtain testcase count signals1062. Testcase count signals1062, which instrumentation load tool820automatically connects to a corresponding number of event counters within instrumentation logic block1002, indicate the number of testcases that have been executed in each of the Dial's legal settings.

Following block936(or block934), instrumentation load tool820determines whether or not any other Dials remain to be instrumented within the present design entity. If so, the process returns to block920and following blocks, which collectively represent instrumentation load tool820automatically creating instrumentation within instrumentation entity1020for each additional Dial to be instrumented with design entity1000. If, on the other hand, no additional Dials to be instrumented remain in the present design entity, the process returns to block902, which illustrates instrumentation load tool820examining the next design entity, if any.

As has been described, the present invention provides an improved method and system for facilitating the collection of simulation data regarding configuration constructs, such as Dials, that are utilized to configure a simulation model. According to a preferred embodiment of the present invention, an instrumentation entity for collecting simulation data for a Dial is automatically generated and embedded within the design entity containing the configuration latch(es) associated with the Dial. In one embodiment, the instrumentation entity generates output signals indicating the number of simulation cycles and testcases executed for each Dial setting are recorded for appropriate Dials. In addition, a failure event is triggered if the Dial assumes an illegal setting during simulation.

While the invention has been particularly shown as described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. For example, it will be appreciated that the concepts disclosed herein may be extended or modified to apply to other types of configuration constructs having different rules than the particular exemplary embodiments disclosed herein. In addition, although aspects of the present invention have been described with respect to a computer system executing software that directs the functions of the present invention, it should be understood that present invention may alternatively be implemented as a program product for use with a data processing system. Programs defining the functions of the present invention can be delivered to a data processing system via a variety of signal-bearing media, which include, without limitation, non-rewritable storage media (e.g., CD-ROM), rewritable storage media (e.g., a floppy diskette or hard disk drive), and communication media, such as digital and analog networks. It should be understood, therefore, that such signal-bearing media, when carrying or encoding computer readable instructions that direct the functions of the present invention, represent alternative embodiments of the present invention.