Memory system, operating method thereof, and data processing system for processing duplicate data

A memory system may include: a nonvolatile memory device comprising a plurality of memory regions; and a controller in communication with the nonvolatile memory device to control operations of the nonvolatile memory device and configured to: receive a first write request including a first logical address and a second logical address; determine a duplicate physical address mapped to the second logical address; and selectively map the first logical address to the duplicate physical address based on a duplicate count corresponding to the duplicate physical address.

PRIORITY CLAIM AND CROSS-REFERENCES TO RELATED APPLICATION

This patent application document claims the priority and benefits of Korean application number 10-2021-0155867, filed on Nov. 12, 2021, which is incorporated herein by reference in its entirety as part of the disclosure of this patent application document.

TECHNICAL FIELD

Various embodiments generally relate to a memory system and a data processing system, and more particularly, to a memory system including a nonvolatile memory device, and a data processing system.

BACKGROUND

Memory systems are used to store information for use in a computer or other electronic devices. Memory systems may store data provided from a host device in response to a write request of the host device and provide data stored therein to the host device in response to a read request of the host device. The host device can be any electric device that writes or reads data to or from a memory system, such as a computer, a digital camera, a mobile phone and others. The memory system may be electrically connected to the host device or may be in communication with the host device.

SUMMARY

The technology disclosed in this patent document can be implemented in various embodiments to provide memory system, operating methods, and data processing systems for efficiently managing duplicate data.

In an embodiment, a memory system may include: a nonvolatile memory device comprising a plurality of memory regions; and a controller in communication with the nonvolatile memory device to control operations of the nonvolatile memory device and configured to: receive a first write request including a first logical address and a second logical address; determine a duplicate physical address mapped to the second logical address; and selectively map the first logical address to the duplicate physical address based on a duplicate count corresponding to the duplicate physical address.

In an embodiment, an operating method of a memory system may include: receiving a first write request including a first logical address and a second logical address; determining a duplicate physical address mapped to the second logical address, in response to the first write request; and determining whether to map the first logical address to the duplicate physical address based on a duplicate count corresponding to the duplicate physical address.

In an embodiment, a data processing system may include: a host device configured to generate a first write request including a current logical address and a duplicate logical address; and a memory system in communication with the host device to perform a memory operation in response to a request from the host device, the memory system configured to receive the first write request from the host device, determine a duplicate physical address mapped to the duplicate logical address, and selectively map the current logical address to the duplicate physical address based on a duplicate count corresponding to the duplicate physical address.

In an embodiment, a memory system may include: a nonvolatile memory device comprising a plurality of memory regions; and a controller configured to determine a duplicate physical address mapped to a second logical address in response to a first write request including a first logical address and the second logical address, and selectively map the first logical address to the duplicate physical address according to a result obtained by referring to a duplicate count corresponding to the duplicate physical address.

In an embodiment, an operating method of a memory system may include the steps of: receiving a first write request including a first logical address and a second logical address; deciding a duplicate physical address mapped to the second logical address, in response to the first write request; and deciding whether to map the first logical address to the duplicate physical address, according to a result obtained by referring to a duplicate count corresponding to the duplicate physical address.

In an embodiment, a data processing system may include: a host device configured to generate a first write request including a current logical address and a duplicate logical address; and a memory system configured to receive the first write request from the host device, determine a duplicate physical address mapped to the duplicate logical address, and selectively map the current logical address to the duplicate physical address according to a result obtained by referring to a duplicate count corresponding to the duplicate physical address.

In an embodiment, a memory system may include: a nonvolatile memory device comprising a plurality of memory regions configured to store data in one or more physical addresses of the memory regions by mapping one or more logical addresses to the one or more physical addresses; and a controller in communication with the nonvolatile memory device to control operations of the nonvolatile memory device and configured to: receive a first write request including a first logical address and a second logical address; determine a duplicate physical address mapped to the second logical address, wherein the duplicate physical address corresponds to a memory region in which duplicate data is stored; and selectively map the first logical address to the duplicate physical address based on a duplicate count corresponding to the duplicate physical address, wherein the duplicate count indicates a number of duplicate physical addresses that store duplicate data.

In an embodiment, an operating method of a memory system may include: receiving a first write request including a first logical address and a second logical address; determining a duplicate physical address mapped to the second logical address, in response to the first write request, wherein the duplicate physical address corresponds to a memory region in which duplicate data is stored; and determining whether to map the first logical address to the duplicate physical address based on a duplicate count corresponding to the duplicate physical address, wherein the duplicate count indicates a number of duplicate physical addresses that store duplicate data.

In an embodiment, a data processing system may include: a host device configured to generate a first write request including a current logical address and a duplicate logical address; and a memory system in communication with the host device to perform a memory operation in response to a request from the host device, the memory system configured to receive the first write request from the host device, determine a duplicate physical address mapped to the duplicate logical address, wherein the duplicate physical address and the duplicate logical address correspond to a memory region in which duplicate data is stored, and selectively map the current logical address to the duplicate physical address based on a duplicate count corresponding to the duplicate physical address, wherein the duplicate count indicates a number of duplicate physical addresses that store duplicate data.

DETAILED DESCRIPTION

The technology disclosed in this patent document can be implemented in some embodiments to provide a memory system that can efficiently manage its memory space by reducing duplicate data.

Hereafter, some embodiments of the disclosed technology will be described in detail with reference to the drawings.

FIG.1is a block diagram illustrating an example of a data processing system100based on some embodiments of the disclosed technology.

A memory system may be in a host device or remotely in communication with the host device. In some implementations, the data processing system100may include a host device110and a memory system120.

In some implementations, the host device110may include an electric device capable of processing data, and examples thereof may include a computer, a digital camera, a mobile phone and others. The host device110may store data in the memory system120and read data from the memory system120. In some implementations, the host device110may generate a first write request WRITE1including a first logical address, e.g., a current logical address W-LBA, and a second logical address, e.g., a duplicate logical address D-LBA, and transmit the first write request WIRTE1to the memory system120.

In an embodiment, the host device110may generate the first write request WRITE1for first data DATA1, when copying the first data DATA1. The duplicate logical address D-LBA may be a logical address originally or previously allocated to the first data DATA1, and the current logical address W-LBA may be an address newly allocated to the copied first data DATA1. At this time, it may be determined that both of the current logical address W-LBA and the duplicate logical address D-LBA are validly allocated to the first data DATA1.

The memory system120may include a controller121and a nonvolatile memory device122.

The controller121may control overall operations of the memory system120. The controller121may control the nonvolatile memory device122to perform a foreground operation according to an instruction of the host device110. The foreground operation may include an operation of writing data to the nonvolatile memory device122and reading data from the nonvolatile memory device122, according to a write request and read request of the host device110.

Furthermore, the controller121may control the nonvolatile memory device122to perform a background operation which is performed internally without any request from the host device110. The background operation may include one or more of a wear-leveling operation, a garbage collection operation, an erase operation, a read reclaim operation and a refresh operation on the nonvolatile memory device122. The background operation may include writing data to the nonvolatile memory device122and reading data from the nonvolatile memory device122, like the foreground operation.

The controller121may receive the first write request WRITE1from the host device110. The controller121may determine a physical address (hereafter referred to as duplicate physical address) mapped to the duplicate logical address D-LBA in response to the first write request WRITE1, and selectively map the current logical address W-LBA to the duplicate physical address according to a result obtained by referring to a duplicate count corresponding to the duplicate physical address.

Specifically, when the duplicate count corresponding to the duplicate physical address is less than a threshold value, the controller121may increase the duplicate count corresponding to the duplicate physical address, and map the current logical address W-LBA to the duplicate physical address. In this case, the controller121does not write the first data DATA1to the nonvolatile memory device122in response to the first write request WRITE1.

On the other hand, when the duplicate count corresponding to the duplicate physical address is equal to the threshold value, the controller121may write the first data DATA1corresponding to the first write request WRITE1to a memory region selected among memory regions MR of the nonvolatile memory device122, and map the current logical address W-LBA to the physical address of the selected memory region. The host device110may transmit the first data DATA1along with the first write request WRITE1to the controller121, and the controller121may store the first data DATA1transmitted from the host device110in the selected memory region of the nonvolatile memory device122. In an embodiment, the first write request WRITE1may not include the first data DATA1, and the controller121may read the first data DATA1from the memory region corresponding to the duplicate physical address in the nonvolatile memory device122, and store the read first data DATA1in the selected memory region.

In an embodiment, the controller121may store zero value (0) for the duplicate count corresponding to the physical address of the selected memory area, when storing the first data DATA1in the selected memory region of the nonvolatile memory device122.

In an embodiment, the host device110may transmit, to the controller121, a second write request (not illustrated) which includes the current logical address W-LBA but does not include the duplicate logical address D-LBA. The controller121may store second data corresponding to the second write request in a memory region selected among the memory regions MR of the nonvolatile memory device122, in response to the second write request, and map the current logical address W-LBA to the physical address of the selected memory region. In an embodiment, the controller121may determine the previous is physical address which has been mapped to the current logical address W-LBA, in response to the second write request. When the duplicate count corresponding to the previous physical address exceeds 0, the controller121may decrease the duplicate count corresponding to the previous physical address. In an embodiment, the controller121may store zero value (0) for the duplicate count corresponding to the physical address of the selected memory region, when storing the second data DATA2in the selected memory region.

The controller121may refer to address mapping information MAP_IF in order to determine a physical address mapped to a logical address. The address mapping information MAP_IF may include the mapping relationships between logical addresses used by the host device110and the physical addresses of the memory regions MR. Furthermore, the controller121may refer to a duplicate count corresponding to a physical address, from duplicate count information DCNT_IF. The duplicate count information DCNT_IF may include duplicate counts corresponding to physical addresses, respectively.

The nonvolatile memory device122may store data transmitted from the controller121, and read data stored therein and transmit the read data to the controller121, under control of the controller121. The nonvolatile memory device122may include a plurality of memory regions MR corresponding to different physical addresses, respectively.

Examples of the nonvolatile memory device122may include a flash memory device such as NAND flash or NOR flash, FeRAM (Ferroelectric Random Access Memory), PCRAM (Phase-Change Random Access Memory), MRAM (Magnetic Random Access Memory), ReRAM (Resistive Random Access Memory) and others.

The nonvolatile memory device122may include one or more planes, one or more memory chips, one or more memory dies, or one or more memory packages.FIG.1illustrates that the memory system120includes one nonvolatile memory device122, but the number of nonvolatile memory devices included in the memory system120is not limited thereto.

FIG.2Ais a diagram illustrating an operating method of the controller121based on some embodiments of the disclosed technology.

Referring toFIG.2A, the host device110may transmit the first write request WRITE1to the controller121. The first write request WRITE1may include a current logical address W-LBA (e.g., L2), a duplicate logical address D-LBA (e.g., L1), and first data DATA1. When copying the first data DATA1, the host device110may transmit, to the controller121, the first write request WRITE1including the duplicate logical address D-LBA as well as the current logical address W-LBA. The duplicate logical address D-LBA may be a logical address originally or previously allocated to the existing first data DATA1, and the current logical address W-LBA may be a logical address newly allocated to the copied first data DATA1. Therefore, the first data DATA1included in the first write request WRITE1may be duplicate data. The duplicate data may indicate the same data allocated to two or more different logical addresses.

In some implementations, the controller121may receive the first write request WRITE1, and update the address mapping information MAP_IF and the duplicate count information DCNT_IF on the basis of the first write request WRITE1, if necessary. In one example, the controller121may determine a duplicate physical address P1mapped to the duplicate logical address D-LBA (L1) on the basis of the address mapping information MAP_IF. Furthermore, the controller121may update the address mapping information MAP_IF by mapping the current logical address W-LBA (L2) to the duplicate physical address P1. In other words, the controller121may update the address mapping information MAP_IF by mapping both the duplicate logical address D-LBA (L1) and the current logical address W-LBA (L2) to the duplicate physical address P1. In some implementations, the controller121does not actually write the duplicate data DATA1to a memory region of the nonvolatile memory device122in response to the first write request WRITE1.

The address mapping information MAP_IF may include a mapping or look-up table having logical addresses LBA as indices, for example. In an embodiment, as illustrated inFIG.2B, address mapping information MAP_IF_1may include a table having physical addresses PBA as indices. The address mapping information MAP_IF_1ofFIG.2Bmay be configured according to a multi-mapping method, which is used to map one or more logical addresses to each physical address. In the address mapping information MAP_IF_1, the duplicate physical address P1may be mapped to the duplicate logical address D-LBA (L1) and the current logical address W-LBA (L2) at the same time.

Referring back toFIG.2A, the controller121may update the duplicate count information DCNT_IF by increasing the duplicate count DCNT corresponding to the duplicate physical address P1by 1. A duplicate count DCNT that is equal to or greater than 1 may indicate that two or more logical addresses are mapped to the duplicate physical address P1. For example, when the duplicate count DCNT is k, it may indicate that (k+1) logical addresses are mapped to the duplicate physical address P1. When the duplicate count DCNT is equal to or greater than 1, it may indicate that duplicate data is stored in the memory region of the duplicate physical address P1.

FIG.3is a diagram illustrating an example of an operating method of the controller121based on some embodiments of the disclosed technology. Unlike the method described with reference toFIGS.2A and2B, the controller121may further determine whether the duplicate count DCNT exceeds a threshold value TH, in response to the first write request WRITE1for the duplicate data, e.g., the first data DATA1.

In some implementations, referring toFIG.3, the host device110may transmit the first write request WRITE1to the controller121. The first write request WRITE1may include the current logical address is W-LBA (L2), the duplicate logical address D-LBA (L1), and the first data DATA1.

In some implementations, the controller121may receive the first write request WRITE1, and update the address mapping information MAP_IF and the duplicate count information DCNT_IF on the basis of the first write request WRITE1, if necessary. In one example, the controller121may determine the duplicate physical address P1mapped to the duplicate logical address D-LBA (L1) on the basis of the address mapping information MAP_IF. The controller121may not update the duplicate count information DCNT_IF, when the duplicate count DCNT corresponding to the duplicate physical address P1is equal to the threshold value TH on the basis of the duplicate count information DCNT_IF. In other words, when the duplicate count DCNT corresponding to the duplicate physical address P1is equal to the threshold value TH, the duplicate count DCNT corresponding to the duplicate physical address P1may remain unchanged at the threshold value TH. Furthermore, the controller121may store the first data DATA1in a selected memory region of the nonvolatile memory device122, and update the address mapping information MAP_IF by mapping the current logical address W-LBA (L2) to a physical address P2of the selected memory region.

On the other hand, when the duplicate count DCNT corresponding to the duplicate physical address P1is less than the threshold value TH, the controller121may operate as described with reference toFIG.2A. That is, the controller121may perform the operation of mapping the current logical address W-LBA (L2) to the duplicate physical address P1and does not actually store the duplicate data DATA1in a memory region of the nonvolatile memory device122.

The first data DATA1, which is duplicate data, and the first write request WRITE1may be transmitted as illustrated inFIGS.2A,2B and3. In an embodiment, the first write request WRITE1may not include the first data DATA1, and the controller121may read the first data DATA1from the memory region corresponding to the duplicate physical address P1, and store the read first data DATA1in the selected memory region of the nonvolatile memory device122.

In an embodiment, the controller121may update the duplicate count information DCNT_IF by storing zero value (0) for the duplicate count DCNT corresponding to the physical address P2. When the duplicate count DCNT is 0, it may indicate that only one logical address (e.g., L2) is mapped to the physical address P2.

FIGS.4A and4Bare diagrams illustrating an operating method of the controller121based on some embodiments of the disclosed technology.

Referring toFIG.4A, the host device110may transmit a second write request WRITE2to the controller121. The second write request WRITE2may include a current logical address W-LBA (L2) and second data DATA2. For example, the host device110may update the second data DATA2originally or previously allocated to the current logical address W-LBA (L2), and then also allocate the current logical address W-LBA (L2) to the updated second data DATA2. Here, the second write request WRITE2for the updated second data DATA2may not include a duplicate logical address D-LBA. When the current logical address W-LBA (L2) is not allocated to any data, the host device110may allocate the current logical address W-LBA (L2) to newly generated second data DATA2. Here, the second write request WRITE2for new data may not include a duplicate logical address D-LBA.

The controller121may receive the second write request WRITE2, and update the address mapping information MAP_IF and the duplicate count information DCNT_IF on the basis of the second write request WRITE2, if necessary. In some implementations, the controller121may determine the previous physical address P1mapped to the current logical address W-LBA (L2) on the basis of the address mapping information MAP_IF. The controller121may check the duplicate count DCNT corresponding to the previous physical address P1on the basis of the duplicate count information DCNT_IF. When the duplicate count DCNT is equal to or greater than 1, it may indicate that duplicate data is stored in the memory region of the previous physical address P1. When the duplicate count DCNT is equal to or greater than 1, it may indicate that the previous data of the current logical address W-LBA (L2), e.g., data that is not yet updated to the second data DATA2, is the duplicate data. Therefore, the controller121may update the duplicate count information DCNT_IF by decreasing the duplicate count is DCNT by 1. Furthermore, the controller121may store the second data DATA2in the selected memory region, and update the address mapping information MAP_IF by mapping the current logical address W-LBA (L2) to the physical address P2of the selected memory region.

In an embodiment, the controller121may update the duplicate count information DCNT_IF by storing zero value for the duplicate count DCNT corresponding to the physical address P2. That is, when the duplicate count DCNT is 0, it may indicate that only one logical address (e.g., L2) is mapped to the physical address P2. When the duplicate count DCNT is 0, it may indicate that the data stored in the memory region of the physical address P2is not duplicate data.

FIG.4Billustrates the duplicate count DCNT corresponding to the previous physical address P1is 0. When the duplicate count DCNT is 0, it may indicate that data stored in the memory region of the physical address P1is not duplicate data. Therefore, as described with reference toFIG.4A, the controller121does not need to decrease the duplicate count DCNT corresponding to the previous physical address P1.

As described with reference toFIG.4A, however, the controller121may store the second data DATA2in the selected memory region, and update the address mapping information MAP_IF by mapping the current logical address W-LBA (L2) to the physical address P2of the selected memory region. In an embodiment, the controller121may update the duplicate count information DCNT_IF by storing, as 0, the duplicate count DCNT corresponding to the physical address P2.

In an embodiment, when the second data DATA2is not updated data but newly generated data, the current logical address W-LBA (L2) may not be mapped to any physical addresses in the address mapping information MAP_IF. In this case, the operation of referring to the duplicate count information DCNT_IF may be omitted.

In an embodiment, a write request (e.g., the first write request WRITE1) for duplicate data and a write request (e.g., the second write request WRITE2) for updated data (or new data) may be transmitted in different formats. Therefore, the controller121may distinguish between the write request for duplicate data and the write request for updated data (or new data), and operate as described with reference toFIGS.2A,2B,3,4A, and4B. In an embodiment, the controller121may determine whether a write request includes the duplicate logical address D-LBA or not, and thus distinguish between the write request for duplicate data and the write request for updated data (or new data).

In an embodiment, the duplicate count information DCNT_IF may be generated for all physical addresses. In this case, when the duplicate count DCNT corresponding to a certain physical address is 0, it may indicate that data stored in the memory region of the corresponding physical address is not duplicate data. When the duplicate count DCNT corresponding to a certain physical address is 0, it may indicate that the memory region of the corresponding physical address is an empty memory region. When the duplicate count DCNT corresponding to a certain physical address is k, it may indicate that (k+1) logical addresses are mapped to the corresponding physical address.

In an embodiment, the duplicate count information DCNT_IF may be generated for the physical addresses of memory regions in which valid data are stored. In this case, when the duplicate count DCNT corresponding to a certain physical address is 0, it may indicate that data stored in the memory region of the corresponding physical address is not duplicate data. When the duplicate count DCNT corresponding to a certain physical address is k, it may indicate that (k+1) logical addresses are mapped to the corresponding physical address. When invalid data (e.g., previous data of updated data) is stored in the memory region corresponding to a certain physical address, the duplicate count DCNT of the corresponding physical address may be deleted (removed or invalidated) from the duplicate count information DCNT_IF. For example, inFIG.4B, the previous data of the second data DATA2is stored in the memory region of the previous physical address P1. Thus, the duplicate count DCNT of the previous physical address P1may be deleted (removed or invalidated) from the duplicate count information DCNT_IF.

In an embodiment, the duplicate count information DCNT_IF may be generated only for the physical addresses of memory regions in which duplicate data are stored. In this case, the minimum value of the duplicate count DCNT included in the duplicate count information DCNT_IF may be 1. When the duplicate count DCNT corresponding to a certain physical address is k, it may indicate that (k+1) logical addresses are mapped to the corresponding physical address. When duplicate data is no longer stored in a certain physical address included in the duplicate count information DCNT_IF, the duplicate count DCNT of the corresponding physical address may be deleted (removed or invalidated) from the duplicate count information DCNT_IF.

In some embodiments of the disclosed technology, when two or more logical addressees are allocated to store the same duplicate data, the memory system120does not store the duplicate data in two or more memory regions. Therefore, the entire volume of valid data is decreased, and thus a management operation of the memory system120, such as a garbage collection operation including migrating valid data to a new memory region, may be more efficiently performed.

FIG.5is a flowchart illustrating an example of an operating method of the memory system120ofFIG.1based on some embodiments of the disclosed technology.FIG.5is based on the assumption that the duplicate count information DCNT_IF is generated for all physical addresses.

Referring toFIG.5, the controller121may receive a write request from the host device110at S101.

At S102, the controller121may determine whether the write request includes a duplicate logical address D-LBA. When it is determined that the write request includes the duplicate logical address D-LBA, the procedure may proceed to S103. When it is determined that the write request does not include the duplicate logical address D-LBA, the procedure may proceed to S106.

At S103, the controller121may determine a duplicate physical address mapped to the duplicate logical address D-LBA on the basis of the address mapping information MAP_IF.

At S104, the controller121may increase, by 1, a duplicate count corresponding to the duplicate physical address in the duplicate count information DCNT_IF.

At S105, the controller121may update the address mapping information MAP_IF by mapping the current logical address W-LBA to the duplicate physical address.

At S106, the controller121may determine a previous physical address mapped to the current logical address W-LBA on the basis of the address mapping information MAP_IF.

At S107, the controller121may determine whether the duplicate count corresponding to the previous physical address exceeds 0, on the basis of the duplicate count information DCNT_IF. When it is determined that the duplicate count exceeds 0, the procedure may proceed to step S108. When it is determined that the duplicate count does not exceed 0, the procedure may proceed to step S109.

At S108, the controller121may decrease, by 1, the duplicate count corresponding to the previous physical address in the duplicate count information DCNT_IF.

At S109, the controller121may store data corresponding to a write request in a selected memory region, and update the address mapping information MAP_IF by mapping the current logical address W-LBA to the physical address of the selected memory region.

At S110, the controller121may store, as 0, the duplicate count corresponding to the physical address of the selected memory region in the duplicate count information DCNT_IF.

FIG.6is a flowchart illustrating an example of an operating method of the memory system120ofFIG.1based on some embodiments of the disclosed technology.

Operations S201to S210shown inFIG.6may be performed in a similar manner to operations S101to S110shown inFIG.5. Therefore, the detailed descriptions thereof will be omitted herein.

At S211, the controller121may determine whether the duplicate count corresponding to the duplicate physical address is less than a threshold value TH, on the basis of the duplicate count information DCNT_IF. When it is determined that the duplicate count is less than the threshold value TH, the procedure may proceed to S204. When it is determined that the duplicate count is not less than the threshold value TH, the procedure may proceed to S209.

FIG.7is a diagram illustrating an example of a data is processing system1000including a solid state drive (SSD)1200based on some embodiments of the disclosed technology. Referring toFIG.7, the data processing system1000may include a host device1100and the SSD1200. The host device1100may include the host device110shown inFIG.1.

The SSD1200may include a controller1210, a buffer memory device1220, a plurality of nonvolatile memory devices1231to123n, a power supply1240, a signal connector1250, and a power connector1260.

The controller1210may control general operations of the SSD1200. The controller1210may include the controller121shown inFIG.1. The controller1210may include a host interface unit1211, a control unit1212, a random access memory1213, an error correction code (ECC) unit1214, and a memory interface unit1215.

The host interface unit1211may exchange a signal SGL with the host device1100through the signal connector1250. The signal SGL may include a command, an address, data, and so forth. The host interface unit1211may interface the host device1100and the SSD1200according to the protocol of the host device1100. For example, the host interface unit1211may communicate with the host device1100through any one of standard interface protocols such as secure digital, universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), personal computer memory card international association (PCMCIA), parallel advanced technology attachment (PATA), serial advanced technology attachment (SATA), small computer system interface (SCSI), serial attached SCSI (SAS), peripheral component interconnect (PCI), PCI express (PCI-E) and universal flash storage (UFS).

The control unit1212may analyze and process the signal SGL received from the host device1100. The control unit1212may control operations of internal function blocks according to a firmware or a software for driving the SSD1200. The random access memory1213may be used as a working memory for driving such a firmware or software.

The ECC unit1214may generate the parity data of data to be transmitted to at least one of the nonvolatile memory devices1231to123n. The generated parity data may be stored together with the data in the nonvolatile memory devices1231to123n. The ECC unit1214may detect an error of the data read from at least one of the nonvolatile memory devices1231to123n, based on the parity data. If a detected error is within a correctable range, the ECC unit1214may correct the detected error.

The memory interface unit1215may provide control signals such as commands and addresses to at least one of the nonvolatile memory devices1231to123n, according to control of the control unit1212. Moreover, the memory interface unit1215may exchange data with at least one of the nonvolatile memory devices1231to123n, according to control of the control unit1212. For example, the memory is interface unit1215may provide the data stored in the buffer memory device1220, to at least one of the nonvolatile memory devices1231to123n, or provide the data read from at least one of the nonvolatile memory devices1231to123n, to the buffer memory device1220.

The buffer memory device1220may temporarily store data to be stored in at least one of the nonvolatile memory devices1231to123n. Further, the buffer memory device1220may temporarily store the data read from at least one of the nonvolatile memory devices1231to123n. The data temporarily stored in the buffer memory device1220may be transmitted to the host device1100or at least one of the nonvolatile memory devices1231to123naccording to control of the controller1210.

The nonvolatile memory devices1231to123nmay be used as storage media of the SSD1200. The nonvolatile memory devices1231to123nmay be coupled with the controller1210through a plurality of channels CH1to CHn, respectively. One or more nonvolatile memory devices may be coupled to one channel. The nonvolatile memory devices coupled to each channel may be coupled to the same signal bus and data bus.

The power supply1240may provide power PWR inputted through the power connector1260, to the inside of the SSD1200. The power supply1240may include an auxiliary power supply1241. The auxiliary power supply1241may supply power to allow the SSD1200to be normally terminated when a sudden power-off occurs. The is auxiliary power supply1241may include large capacity capacitors.

The signal connector1250may be configured by various types of connectors depending on an interface scheme between the host device1100and the SSD1200.

The power connector1260may be configured by various types of connectors depending on a power supply scheme of the host device1100.

FIG.8is a diagram illustrating an example of a data processing system2000including a memory system2200based on some embodiments of the disclosed technology. Referring toFIG.8, the data processing system2000may include a host device2100and the memory system2200.

The host device2100may be configured in the form of a board such as a printed circuit board. Although not shown, the host device2100may include internal function blocks for performing the function of a host device.

The host device2100may include a connection terminal2110such as a socket, a slot or a connector. The memory system2200may be mounted to the connection terminal2110.

The memory system2200may be configured in the form of a board such as a printed circuit board. The memory system2200may be referred to as a memory module or a memory card. The memory system2200may include a controller2210, a buffer memory device2220, nonvolatile memory devices2231and2232, a power management integrated circuit (PMIC)2240, and a connection terminal2250.

The controller2210may control general operations of the memory system2200. The controller2210may be configured in the same manner as the controller1210shown inFIG.7.

The buffer memory device2220may temporarily store data to be stored in the nonvolatile memory devices2231and2232. Further, the buffer memory device2220may temporarily store the data read from the nonvolatile memory devices2231and2232. The data temporarily stored in the buffer memory device2220may be transmitted to the host device2100or the nonvolatile memory devices2231and2232according to control of the controller2210.

The nonvolatile memory devices2231and2232may be used as storage media of the memory system2200.

The PMIC2240may provide the power inputted through the connection terminal2250, to the inside of the memory system2200. The PMIC2240may manage the power of the memory system2200according to control of the controller2210.

The connection terminal2250may be coupled to the connection terminal2110of the host device2100. Through the connection terminal2250, signals such as commands, addresses, data and so forth and power may be transferred between the host device2100and the memory system2200. The connection terminal2250may be configured into various types depending on an interface scheme between the host device2100and the memory system2200. The connection terminal2250may be disposed on any one side of the memory system2200.

FIG.9is a diagram illustrating an example of a data processing system3000including a memory system3200based on some embodiments of the disclosed technology. Referring toFIG.9, the data processing system3000may include a host device3100and the memory system3200.

The host device3100may be configured in the form of a board such as a printed circuit board. Although not shown, the host device3100may include internal function blocks for performing the function of a host device.

The memory system3200may be configured in the form of a surface-mounting type package. The memory system3200may be mounted to the host device3100through solder balls3250. The memory system3200may include a controller3210, a buffer memory device3220, and a nonvolatile memory device3230.

The controller3210may control general operations of the memory system3200. The controller3210may be configured in the same manner as the controller1210shown inFIG.7.

The buffer memory device3220may temporarily store data to be stored in the nonvolatile memory device3230. Further, the buffer memory device3220may temporarily store the data read from the nonvolatile memory device3230. The data temporarily stored in the buffer memory device3220may be transmitted to the host device3100or the nonvolatile memory device3230according to control of the controller3210.

The nonvolatile memory device3230may be used as the storage medium of the memory system3200.

FIG.10is a diagram illustrating an example of a network system4000including a memory system4200based on some embodiments of the disclosed technology. Referring toFIG.10, the network system4000may include a server system4300and a plurality of client systems4410to4430which are coupled through a network4500.

The server system4300may service data in response to requests from the plurality of client systems4410to4430. For example, the server system4300may store the data provided from the plurality of client systems4410to4430. For another example, the server system4300may provide data to the plurality of client systems4410to4430.

The server system4300may include a host device4100and the memory system4200. The memory system4200may be configured by the memory system120shown inFIG.1, the SSD1200shown inFIG.7, the memory system2200shown inFIG.8or the memory system3200shown inFIG.9.

FIG.11is a block diagram illustrating an example of a nonvolatile memory device300included in a memory system based on some embodiments of the disclosed technology. Referring toFIG.11, the nonvolatile memory device300may include a memory cell array310, a row decoder320, a data read/write block330, a column decoder340, a voltage generator350, and a control logic360.

The memory cell array310may include memory cells MC which are arranged at areas where word lines WL1to WLm and bit lines BL1to BLn intersect with each other.

The row decoder320may be coupled with the memory cell array310through the word lines WL1to WLm. The row decoder320may operate according to control of the control logic360. The row decoder320may decode an address provided from an external device (not shown). The row decoder320may select and drive the word lines WL1to WLm, based on a decoding result. For instance, the row decoder320may provide a word line voltage provided from the voltage generator350, to the word lines WL1to WLm.

The data read/write block330may be coupled with the memory cell array310through the bit lines BL1to BLn. The data read/write block330may include read/write circuits RW1to RWn respectively corresponding to the bit lines BL1to BLn. The data read/write block330may operate according to control of the control logic360. The data read/write block330may operate as a write driver or a sense amplifier according to an operation mode. For example, the data read/write block330may operate as a write driver which stores data provided from the external device, in the memory cell array310in a write operation. For another example, the data read/write block330may operate as a sense amplifier which reads out data from the memory cell array310in a read operation.

The column decoder340may operate according to control of the control logic360. The column decoder340may decode an address provided from the external device. The column decoder340may couple the read/write circuits RW1to RWn of the data read/write block330respectively corresponding to the bit lines BL1to BLn with data input/output lines or data input/output buffers, based on a decoding result.

The voltage generator350may generate voltages to be used in internal operations of the nonvolatile memory device300. The voltages generated by the voltage generator350may be applied to the memory cells of the memory cell array310. For example, a program voltage generated in a program operation may be applied to a word line of memory cells for which the program operation is to be performed. For another example, an erase voltage generated in an erase operation may be applied to a well area of memory cells for which the erase operation is to be performed. For still another example, a read voltage generated in a read operation may be applied to a word line of memory cells for which the read operation is to be performed.

The control logic360may control general operations of the nonvolatile memory device300, based on control signals provided from the external device. For example, the control logic360may control is operations of the nonvolatile memory device300such as read, write and erase operations of the nonvolatile memory device300.

While various embodiments of the disclosed technology related to a memory system, a data processing system and operations thereof have been described above, variations and enhancements of the disclosed embodiments and other embodiments may be made based on what is disclosed and/or illustrated in this patent document.