THREE-DIMENSIONAL (3D) FERROELECTRIC RANDOM ACCESS MEMORY (FERAM) AND MANUFACTURING METHOD THEREOF

A 3D FeRAM is provided. The 3D FeRAM includes a semiconductor patterns stacked in a vertical direction on a substrate and spaced apart from each other in a first horizontal direction, bit lines on first side surface of the semiconductor patterns, extending in the first horizontal direction, and spaced apart from each other in the vertical direction, first electrodes on second side surfaces of the semiconductor patterns and spaced apart from each other in both the vertical direction and the first horizontal direction, a ferroelectric layer on the first electrodes, second electrodes on the ferroelectric layers, extending in the first horizontal direction, and spaced apart from each other in the vertical direction, and word lines between two adjacent semiconductor patterns extending in the vertical direction.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to Korean Patent Application Nos. 10-2023-0039111, filed on Mar. 24, 2023, and 10-2023-0063808, filed on May 17, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.

BACKGROUND

The present disclosure relates to a semiconductor memory device, and in particular, to a three-dimensional (3D) ferroelectric random access memory (FeRAM) and a manufacturing method thereof.

As electronic products require miniaturization, multifunctionality, and high performance, high capacity semiconductor memory devices are required and increased integration is required to provide high capacity semiconductor memory devices. Because the degree of integration of a two-dimensional (2D) semiconductor memory device is mainly determined by an area occupied by a unit memory cell, the degree of integration of the 2D semiconductor memory device is increasing but still limited. Accordingly, a 3D semiconductor memory device that increases memory capacity by stacking a plurality of memory cells in a vertical direction on a substrate has been proposed.

SUMMARY

One or more embodiments provide a three-dimensional (3D) ferroelectric random access memory (FeRAM) with excellent endurance and no leakage problem, and a manufacturing method thereof.

Problems to be solved by the present disclosure are not limited to the above-mentioned problems, and other problems may be clearly understood by one of ordinary skill in the art from the description below.

According to an aspect of an example embodiment, there is provided a three-dimensional (3D) ferroelectric random access memory (FeRAM) including: a substrate; semiconductor patterns stacked in a vertical direction on the substrate in a multilayer structure with insulating layers therebetween, and spaced apart from each other in a first horizontal direction; bit lines on first side surfaces of the semiconductor patterns in a second horizontal direction, wherein the second horizontal direction is perpendicular to the first horizontal direction, and the bit lines extend in the first horizontal direction and are spaced apart from each other in the vertical direction; first electrodes on second side surfaces of the semiconductor patterns in the second horizontal direction, wherein the first electrodes are spaced apart from each other in both the vertical direction and the first horizontal direction; a ferroelectric layer on the first electrodes in the second horizontal direction, wherein the ferroelectric layer extends in the first horizontal direction; second electrodes on the ferroelectric layer in the second horizontal direction, wherein the second electrodes extend in the first horizontal direction and are spaced apart from each other in the vertical direction; and word lines between two adjacent semiconductor patterns among the semiconductor patterns in the first horizontal direction, wherein the word lines extend in the vertical direction.

According to another aspect of an example embodiment, there is provided a 3D FeRAM including: a substrate; semiconductor patterns stacked in a vertical direction on the substrate in a multilayer structure with insulating layers therebetween, and spaced apart from each other in a first horizontal direction; bit lines on first side surfaces of the semiconductor patterns in a second horizontal direction, wherein the second horizontal direction is perpendicular to the first horizontal direction, and the bit lines extend in the first horizontal direction and are spaced apart from each other in the vertical direction; first electrodes on second side surfaces of the semiconductor patterns in the second horizontal direction, wherein the first electrodes are spaced apart from each other in both the vertical direction and the first horizontal direction, and each of the first electrodes has a ‘’ shape on each of a horizontal cross-section perpendicular to the vertical direction and a vertical cross-section perpendicular to the first horizontal direction; a ferroelectric layer on the first electrodes in the second horizontal direction, wherein the ferroelectric layer extends in the first horizontal direction, and includes a ‘’-shaped portion along each of the horizontal cross-section and the vertical cross-section, in correspondence to the ‘’ shape of each of the first electrodes; second electrodes on the ferroelectric layer in the second horizontal direction, wherein the second electrodes extend in the first horizontal direction and are spaced apart from each other in the vertical direction, and each of the second electrodes has a rectangular shape filling a ‘’-shaped inside of the ferroelectric layer on the vertical cross-section; and word lines between two adjacent semiconductor patterns among the semiconductor patterns in the first horizontal direction, wherein the word lines extend in the vertical direction.

According to another aspect of an example embodiment, there is provided a 3D FeRAM including: a substrate; semiconductor patterns stacked in a vertical direction on the substrate in a multilayer structure with insulating layers therebetween, and spaced apart from each other in a first horizontal direction; bit lines on first side surface of the semiconductor patterns in a second horizontal direction, wherein the second horizontal direction is perpendicular to the first horizontal direction, and the bit lines extend in the first horizontal direction and are spaced apart from each other in the vertical direction; first electrodes on second side surfaces of the semiconductor patterns in the second horizontal direction, wherein the first electrodes are spaced apart from each other in both the vertical direction and the first horizontal direction, wherein each of a horizontal cross-section perpendicular to the vertical direction and a vertical cross-section perpendicular to the first horizontal direction has a rectangular shape; ferroelectric layers on the first electrodes in the second horizontal direction, wherein the ferroelectric layers in the first horizontal direction, are spaced apart from each other in the vertical direction, and have a ‘’ shape on the vertical cross-section; second electrodes on the ferroelectric layers in the second horizontal direction, wherein the second electrodes extend in the first horizontal direction, are spaced apart from each other in the vertical direction, and each has a rectangular shape filling a ‘’-shaped inside of each of the ferroelectric layers on the vertical cross-section; and word lines between two adjacent semiconductor patterns among the semiconductor patterns in the first horizontal direction, wherein the word lines extend in the vertical direction.

According to another aspect of an example embodiment, there is provided a substrate; semiconductor patterns stacked on the substrate in a multilayer structure with insulating layers therebetween and spaced apart from each other in a first horizontal direction; bit lines on first side surfaces of the semiconductor patterns in a second horizontal direction, wherein the second horizontal direction is perpendicular to the first horizontal direction, and the bit lines extend in a vertical direction and are spaced apart from each other in the first horizontal direction; first electrodes on second side surfaces of the semiconductor patterns in the second horizontal direction, wherein the first electrodes are spaced apart from each other in both the vertical direction and the first horizontal direction; a ferroelectric layer on the first electrodes in the second horizontal direction, wherein the ferroelectric layer extends in the vertical direction; second electrodes on the ferroelectric layer in the second horizontal direction, wherein the second electrodes extend in the vertical direction and are spaced apart from each other in the first horizontal direction; and word lines between two adjacent semiconductor patterns among the semiconductor patterns in the vertical direction, wherein the word lines extend in the first horizontal direction.

According to another aspect of an example embodiment, there is provided a manufacturing method of a 3D FeRAM including: forming a stacked structure by alternately stacking first insulating layers and semiconductor layers in a vertical direction on a substrate; separating the semiconductor layers from each other in a second horizontal direction by forming second insulating layers, wherein the second insulating layers penetrate the stacked structure, extend in a first horizontal direction, and are spaced apart from each other in the second horizontal direction, and wherein the second horizontal direction is perpendicular to the first horizontal direction; forming a first recess in the first horizontal direction by forming a first trench penetrating the stacked structure and extending in the second horizontal direction, and partially etching the semiconductor layers exposed on an inner wall of the first trench; forming first electrodes that are spaced apart from each other in the first recess in the vertical direction and the second horizontal direction, wherein each of the first electrodes has a ‘’ shape on each of a vertical cross-section perpendicular to the second horizontal direction and a horizontal cross-section perpendicular to the vertical direction in the first recess; forming a ferroelectric layer which extends in the vertical direction and the second horizontal direction on the first electrodes and the second insulating layers, and includes a ‘’-shaped portion along each of the horizontal cross-section and the vertical cross-section, in correspondence to a ‘’shape of each of the first electrodes; forming second electrodes which extend in the second horizontal direction and are spaced apart from each other in the vertical direction on the ferroelectric layer; forming semiconductor patterns by forming a second trench penetrating the stacked structure and extending in the second horizontal direction at a position opposite to the first trench in the first horizontal direction with respect to the semiconductor layers, partially etching the semiconductor layers exposed on an inner wall of the second trench, and forming a second recess in the first horizontal direction; forming bit lines which fill the second recess, extend in the second horizontal direction, and are spaced apart from each other in the vertical direction; and forming word lines between two adjacent semiconductor patterns among the semiconductor patterns in the second horizontal direction, wherein the word lines extend in the vertical direction.

According to another aspect of an example embodiment, there is provided a manufacturing method of a 3D FeRAM including: forming a stacked structure by alternately stacking first insulating layers and semiconductor layers in a vertical direction on a substrate; forming a first recess in a second horizontal direction by forming a first trench penetrating the stacked structure and extending in a first horizontal direction, and partially etching the semiconductor layers exposed on an inner wall of the first trench, wherein the second horizontal direction is perpendicular to the first horizontal direction; forming first electrode lines in the first recess, wherein the first electrode lines extend in the first horizontal direction, are spaced apart from each other in the vertical direction, and each has a rectangular shape on a vertical cross-section perpendicular to the first horizontal direction; forming ferroelectric layers on the first electrode lines in the first recess which extend in the first horizontal direction, are spaced apart from each other in the vertical direction, and each has a ‘’ shape on the vertical cross-section; forming second electrodes on the ferroelectric layers which extend in the first horizontal direction, are spaced apart from each other in the vertical direction, and each has a quadrangular shape filling a ‘’-shaped inside of each of the ferroelectric layers on the vertical cross-section; forming a second recess in the second horizontal direction by forming a second trench penetrating the stacked structure and extending in the first horizontal direction at a position opposite to the first trench in the second horizontal direction with respect to the semiconductor layers, and, partially etching the semiconductor layers exposed on an inner wall of the second trench; forming bit lines which fill the second recess, extend in the first horizontal direction, and are spaced apart from each other in the vertical direction; forming first electrodes and semiconductor patterns by forming second insulating layers penetrating the stacked structure, extending in the second horizontal direction, and spaced apart from each other in the first horizontal direction; and forming word lines between two adjacent semiconductor patterns among the semiconductor patterns in the first horizontal direction, wherein the word lines extend in the vertical direction.

DETAILED DESCRIPTION

Hereinafter, embodiments are described with reference to the accompanying drawings. Embodiments described herein are example embodiments, and thus, the present disclosure is not limited thereto, and may be realized in various other forms. Each embodiment provided in the following description is not excluded from being associated with one or more features of another example or another embodiment also provided herein or not provided herein but consistent with the present disclosure. It will be understood that when an element or layer is referred to as being “on,” “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. By contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled to” another element or layer, there are no intervening elements or layers present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. For example, the expression, “at least one of a, b, and c,” should be understood as including only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. It will be also understood that, even if a certain step or operation of manufacturing an apparatus or structure is described later than another step or operation, the step or operation may be performed later than the other step or operation unless the other step or operation is described as being performed after the step or operation. The same reference numerals are used for the same components in the drawings, and redundant descriptions thereof are omitted.

FIG.1is a conceptual diagram illustrating a three-dimensional (3D) ferroelectric random access memory (FeRAM) according to an embodiment.FIGS.2A and2Bare vertical and horizontal cross-sectional views of the 3D FeRAM ofFIG.1, whereinFIG.2Ais a vertical cross-sectional view of a portion A-A′ ofFIG.2B, andFIG.2Bis a horizontal cross-sectional view of a portion B-B′ ofFIG.2A.

The substrate101may include silicon (Si), for example, single crystal Si, polycrystalline Si (poly Si), or amorphous Si. However, a material of the substrate101is not limited to Si. For example, in some embodiments, the substrate101may include a group IV semiconductor such as germanium (Ge), a group IV-IV compound semiconductor such as silicon germanium (SiGe) or silicon carbide (SiC), or a group III-V compound semiconductor such as gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP), etc.

The substrate101may be based on a silicon bulk substrate. In addition, the substrate101may be based on a silicon on insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. The substrate101is not limited to the bulk, SOI, or GeOI substrate, and may be a substrate based on an epitaxial wafer, a polished wafer, an annealed wafer, etc. The substrate101may include a conductive region, for example, a well doped with impurities, or various structures doped with impurities. In addition, the substrate101may constitute a P-type substrate or an N-type substrate according to the type of impurity ions to be doped. In addition, a peripheral circuit and a wiring layer connected to the peripheral circuit may be disposed on a partial region of the substrate101.

The semiconductor patterns110may be alternately disposed with interlayer insulating layers170in a vertical direction (z direction) on the substrate101. The semiconductor patterns110may be alternately disposed with isolation insulating layers180in a second horizontal direction (y direction). In addition, one or two word lines160may be disposed between two adjacent semiconductor patterns110in the second horizontal direction (y direction). The word line160may extend in the vertical direction (z direction) in a structure penetrating the isolation insulating layer180.

The semiconductor pattern110may include an undoped semiconductor material or a doped semiconductor material. In some embodiments, the semiconductor pattern110may include a general semiconductor material such as single crystal Si, poly Si, SiGe, or SiC. In some embodiments, the semiconductor pattern110may include a two-dimensional (2D) semiconductor material including transition metal dichalcogenides (TMDs) such as CuS2, CuSe2, WSe2, MoS2, MoSe2, WS2, etc., hexagonal boron nitride (h-BN), graphene, carbon nano tube (CNT), or a combination thereof. In some embodiments, the semiconductor pattern110may include an amorphous metal oxide semiconductor material, a polycrystalline metal oxide semiconductor material, or a combination thereof. For example, a metal oxide semiconductor material may include at least one of In—Zn-based oxide (IZO), Zn—Sn-based oxide (ZTO), In—Ga-based oxide (IGO), Y—Zn-based oxide (YZO), or In—Ga—Zn-based oxide (IGZO). However, the material of the semiconductor pattern110is not limited to the above materials.

The semiconductor pattern110may have a rectangular shape elongated in the first horizontal direction (x direction). The semiconductor pattern110may have a rectangular pillar shape elongated in the first horizontal direction (x direction). The semiconductor pattern110may include a channel region CH in a central portion in a first horizontal direction (x direction) and a first impurity region SD1and a second impurity region SD2on both sides of the channel region CH in the first horizontal direction (x direction). The first impurity region SD1may be connected to the bit line120, and the second impurity region SD2may be connected to the first electrode130.

The first impurity region SD1and the second impurity region SD2may be formed by doping impurity ions on both sides of the semiconductor pattern110in the first horizontal direction (x direction) by using gas phase doping. The first impurity region SD1and the second impurity region SD2may respectively constitute, for example, a source junction and a drain junction. In addition, for ohmic contact with a metal, a silicide layer may be formed between the first impurity region SD1and the bit line120and between the second impurity region SD2and the first electrode130. The silicide layer may include, for example, at least one of titanium (Ti) silicide, tungsten (W) silicide, cobalt (Co) silicide, or nickel (Ni) silicide.

The bit lines120may be spaced apart from each other on the substrate101in the vertical direction (z direction) and disposed at positions corresponding to the semiconductor pattern110. In addition, a bit line120may be disposed on one side of the semiconductor pattern110in the first horizontal direction (x direction) and extend in the second horizontal direction (y direction). For example, in one layer in the vertical direction (z direction), the semiconductor patterns110disposed in the second horizontal direction (y direction) may be connected to the bit lines120disposed on the corresponding layer.

A side surface of a bit line120contacting the semiconductor pattern110in the first horizontal direction (x direction) may have a concave-convex shape in the second horizontal direction (y direction), and an opposite side surface thereof may have a straight line shape in the second horizontal direction (y direction). The one side surface of the bit line120may have the concave-convex shape because the 3D FeRAM100includes the isolation insulating layer180, and an etching rate between the interlayer insulating layer170and the isolation insulating layer180differs. The structure of the bit line120is described in more detail in the description of a manufacturing method of the 3D FeRAM100ofFIGS.6A to16B.

The bit line120may include a conductive material. The bit line120may include, for example, any one of a doped semiconductor material, a metal, a conductive metal nitride, and a metal-semiconductor compound.

The first electrodes130may be spaced apart from each other on the substrate101in the vertical direction (z direction) and may be disposed at positions corresponding to the semiconductor pattern110. In addition, the first electrodes130may be disposed on one side surface of the semiconductor patterns110in the first horizontal direction (x direction) and be spaced apart from each other in the second horizontal direction (y direction). For example, the bit line120may be disposed on one side surface of the semiconductor pattern110in the first horizontal direction (x direction), and the first electrode130may be disposed on the other side surface thereof in the first horizontal direction (x direction).

Unlike the bit line120, the first electrodes130may be respectively connected to the semiconductor patterns110. In this regard, like the semiconductor patterns110, the first electrodes130may be spaced apart from each other in the vertical direction (z direction) and the second horizontal direction (y direction). As may be seen inFIGS.2A and2B, the horizontal cross-section and the vertical cross-section of the first electrode130may be in the ‘’ shape. Here, the vertical section may indicate a section perpendicular to the second horizontal direction (y direction). Accordingly, the first electrode130may have a shape of a rectangular tube in which the side of the semiconductor pattern110is closed in the first horizontal direction (x direction) and the other side thereof is opened three-dimensionally.

The first electrode130may include any one of a doped semiconductor material, a metal, a conductive metal nitride, and a conductive metal oxide. Here, the metal may include, for example, ruthenium, iridium, titanium, tantalum, etc. The conductive metal nitride may include titanium nitride, tantalum nitride, niobium nitride, tungsten nitride, etc. The conductive metal oxide may include iridium oxide, niobium oxide, etc. However, a material of the first electrode130is not limited to the above materials.

The ferroelectric layer140may extend from the substrate101in the vertical direction (z direction) and may also extend in the second horizontal direction (y direction). The ferroelectric layer140may be connected to the first electrode130and include a ‘’ shaped portion at a position corresponding to the semiconductor pattern110in the vertical direction (z direction) and the second horizontal direction (y direction). That is, the ferroelectric layer140may include the ‘’-shaped portion on the horizontal cross-section and the vertical cross-section, in correspondence to the first electrode130having the ‘’ shape.

InFIGS.2A and2B, a first line cut LC1may be a region used to form the first electrode130, the ferroelectric layer140, and the second electrode150, and may be filled by the interlayer insulating layer170in the final structure. The first line cut LC1may extend in the vertical direction (z direction) and the second horizontal direction (y direction) and may have a somewhat uniform width in the first horizontal direction (x direction). InFIG.2A, an outer side surface of the ferroelectric layer140may contact the first line cut LC1in the first horizontal direction (x direction). On the other hand, inFIG.2B, the outer side surface of the ferroelectric layer140in the first horizontal direction (x direction) may be spaced apart from the first line cut LC1, and a part of the second electrode150may be disposed therebetween. The structure of the ferroelectric layer140is described in more detail in the description of the manufacturing method of 3D FeRAM ofFIGS.6A to16B.

The ferroelectric layer140may include a ferroelectric material. For example, the ferroelectric layer140may include a hafnium (Hf)-based oxide. Specifically, the Hf-based oxide may include hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), etc. When the ferroelectric layer140includes the Hf-based oxide, the ferroelectric layer140may include a dopant of at least one of Zr, Si, Al, Y, Gd, La, Sc, and Sr. However, a material of the ferroelectric layer140is not limited to the above materials.

Moreover, the ferroelectric layer140may include a single layer or multiple layers. When the ferroelectric layer140includes multiple layers, both outermost parts thereof may include ferroelectric thin films. As a specific example, the ferroelectric layer140may have a triple layer structure of a first ferroelectric thin film, an AlO thin film, and a second ferroelectric thin film. Also, the ferroelectric layer140may have a five layer structure of the first ferroelectric thin film, a first AlO thin film, the second ferroelectric thin film, a second AlO thin film, and a third ferroelectric thin film. However, a multilayer structure of the ferroelectric layer140is not limited to the triple layer or five layer structure.

The second electrodes150may be spaced apart from each other on the substrate101in the vertical direction (z direction) and may be disposed at a position corresponding to the semiconductor pattern110. The second electrode150may be disposed on one side surface of the ferroelectric layer140in the first horizontal direction (x direction) and extend in the second horizontal direction (y direction). That is, the first electrode130may be disposed on one side surface of the ferroelectric layer140in the first horizontal direction (x direction) and the second electrode150may be disposed on the other side surface thereof.

As may be seen inFIG.2B, the second electrode150may include an extension150E extending in the second horizontal direction (y direction) on the horizontal cross-section and a protrusion150P protruding from the extension150E in the first horizontal direction (x direction) in correspondence to the ferroelectric layer140having the ‘’ shape on the horizontal cross-section. In addition, as may be seen inFIG.2A, a vertical cross-section of the second electrode150may have a quadrangular shape filling a ‘’ shaped inside of the ferroelectric layer140. The second electrode150may include substantially the same conductive material as that of the first electrode130. However, according to an embodiment, the second electrode150may include a conductive material that is different from that of the first electrode130.

In addition, the first electrode130, the ferroelectric layer140, and the second electrode150may constitute a ferroelectric capacitor (hereinafter referred to as ‘FeCap’). FeCap may store information of [0] or [1] due to a hysteresis characteristic with respect to a dielectric polarization of the ferroelectric layer140. For reference, FeRAM may be classified into a 1Tr1Cap type in which FeCap is disposed between a bit line and a transistor Tr, similar to DRAM, and a 1Tr type in which a gate dielectric film of an FET is replaced with a ferroelectric layer, similar to the FET. The 3D FeRAM100may belong to, for example, the 1TR1Cap type.

The word line160may extend from the substrate101in the vertical direction (z direction) and may be disposed in the second horizontal direction (y direction). As may be seen fromFIGS.1and2B, two word lines160may be disposed between adjacent semiconductor patterns110in the second horizontal direction (y direction). Furthermore, the word line160may be surrounded by a gate dielectric layer162. Accordingly, the gate dielectric layer162may be disposed between the semiconductor pattern110and the word line160.

Furthermore, in a structure in which two word lines160are disposed between the adjacent semiconductor patterns110, a double gate transistor in which the word lines160are disposed on both sides of the channel region CH may be configured. Accordingly, as indicated by a rectangle of a dotted-dot chain line inFIG.2B, one semiconductor pattern110, the word lines160on both sides of the corresponding semiconductor pattern110in the second horizontal direction (y direction), and the bit line120and the FeCap connected to the corresponding semiconductor pattern110in the first horizontal direction (x direction) may constitute a unit cell UC. For reference, inFIGS.2A and2B, the 3D FeRAM100may have a left-right symmetrical structure with respect to a center line of each of the first line cut LC1and a second line cut LC2.

According to an embodiment, one word line160may be disposed between the adjacent semiconductor patterns110in the second horizontal direction (y direction). In a structure in which one word line160is disposed between adjacent semiconductor patterns110, the single gate transistor having one word line160disposed in each channel region CH may be formed. The structure in which one word line160is disposed between the adjacent semiconductor patterns110is described in detail with reference toFIGS.4A and4B.

The 3D FeRAM100has a 1TR1Cap structure, thereby solving an endurance problem of FeRAM of 1Tr structure (i.e., FeFET) and also solving a problem of having to stack channels of single-crystal Si caused by a leakage issue in a vertical stack (VS)-DRAM. That is, in the 3D FeRAM100, even when poly Si is used for the semiconductor pattern110constituting a channel, a leakage problem may not occur. In addition, the 3D FeRAM100may have a structure in which the second electrodes150are separated from each other in correspondence to the bit lines120for each layer in the vertical direction (z direction). As described above, the second electrodes150are separated in the vertical direction (z direction), which may solve a read disturb problem caused by a structure in which the second electrodes150are tied together in the form of a plate electrode, and accordingly, the reliability of FeRAM may be greatly improved. For reference, as may be seen inFIG.2A, the 3D FeRAM100may have a structure in which in one layer in the vertical direction (z direction), the horizontal channel region CH, the horizontal bit line120, the horizontal first electrode130, the horizontal second electrode150, and a part of the vertical word line160are disposed.

FIGS.3A and3Bare vertical and horizontal cross-sectional views of a 3D FeRAM according to an embodiment.FIG.3Ais a vertical cross-sectional view of a portion A-A′ ofFIG.3B, andFIG.3Bis a horizontal cross-sectional view of a portion B-B′ ofFIG.3A.FIGS.3A and3Bare described together with reference toFIG.1, and the description already provided with reference toFIGS.1to2Bis briefly repeated or omitted.

Referring toFIGS.3A and3B, a 3D FeRAM100amay be different from the 3D FeRAM100ofFIG.1in a structure of bit lines120a, first electrodes130a, ferroelectric layers140a, and second electrodes150a. Specifically, the 3D FeRAM100amay include the substrate101, the semiconductor patterns110, the bit lines120a, the first electrodes130a, the ferroelectric layers140a, the second electrodes150a, and the word lines160. Structures and materials of the substrate101, the semiconductor patterns110, and the word lines160are the same as those described in the description of the 3D FeRAM100ofFIG.1.

The bit lines120amay be spaced apart from each other in the vertical direction (z direction) on the substrate101and may be disposed at positions corresponding to the semiconductor patterns110. In addition, the bit line120amay be disposed on one side surface of the semiconductor pattern110in the first horizontal direction (x direction) and extend in the second horizontal direction (y direction). For example, the semiconductor patterns110disposed in the second horizontal direction (y direction) on one layer in the vertical direction (z direction) may be connected together to the bit lines120adisposed in the corresponding layer.

Both sides of the bit line120ain the first horizontal direction (x direction) may have a straight line shape in the second horizontal direction (y direction). This may be due to the fact that the 3D FeRAM100adoes not include an isolation insulating layer. The structure of the bit line120ais described in more detail in the description of the manufacturing method of the 3D FeRAM100aofFIGS.18A to24B. The material of the bit line120ais the same as in the description of the 3D FeRAM100ofFIG.1.

The first electrodes130amay be spaced apart from each other in the vertical direction (z direction) on the substrate101and may be disposed at positions corresponding to the semiconductor patterns110. Also, the first electrodes130amay be disposed on one side surface of the semiconductor pattern110in the first horizontal direction (x direction) and be spaced apart from each other in the second horizontal direction (y direction). For example, the bit line120amay be disposed on one side surface of the semiconductor pattern110in the first horizontal direction (x direction), and the first electrode130amay be disposed on the other side surface thereof.

The first electrodes130amay be respectively disposed in and connected to the semiconductor patterns110. Also, as may be seen fromFIGS.3A and3B, a horizontal cross-section and a vertical cross-section of the first electrode130amay have a rectangular shape. Here, the vertical cross-section may indicate a cross-section perpendicular to the second horizontal direction (y direction). Accordingly, the first electrode130amay have a 3D rectangular pillar shape. The material of the first electrode130ais the same as in the description of the 3D FeRAM100ofFIG.1.

The ferroelectric layers140amay be spaced apart from each other on the substrate101in the vertical direction (z direction) and may extend in the second horizontal direction (y direction). The ferroelectric layer140amay contact the first electrode130aat a position corresponding to the semiconductor pattern110in the vertical direction (z direction) and the second horizontal direction (y direction). As the ferroelectric layers140aare spaced apart from each other in the vertical direction (z direction), unlike the structure of the 3D FeRAM100ofFIG.1, the ferroelectric layers140amay be separated from each other in the vertical direction (z direction). This may be similar to a structure in which the ferroelectric layers140aare separated from each other in the second horizontal direction (y direction) in a 3D FeRAM100dofFIG.5.

The ferroelectric layer140amay include an extension140E extending in the second horizontal direction (y direction) on a horizontal cross-section, and a protrusion140P protruding from the extension140E in the first horizontal direction (x direction) to contact the first electrode130aon a horizontal cross-section. As shown inFIG.3A, the ferroelectric layer140amay have a ‘’ shape in a vertical cross-section. Here, the vertical cross-section may indicate a cross-section perpendicular to the second horizontal direction (y direction). A material of the ferroelectric layer140aand a single layer or multilayer structure are the same as those described in the 3D FeRAM100ofFIG.1.

The second electrodes150amay be spaced apart from each other in the vertical direction (z direction) on the substrate101and may be disposed at positions corresponding to the semiconductor patterns110. The second electrode150amay be disposed on one side surface of the ferroelectric layer140ain the first horizontal direction (x direction) and extend in the second horizontal direction (y direction). That is, the first electrode130amay be disposed on one side surface of the ferroelectric layer140ain the first horizontal direction (x direction) and the second electrode150amay be disposed on the other side surface thereof.

The second electrode150amay have a straight strip shape extending in the second horizontal direction (y direction) in the horizontal cross-section. In addition, the second electrode150amay have a quadrangular shape filling the ‘’-shaped inside of the ferroelectric layer140in the vertical cross-section. A material of the second electrode150ais the same as in the description of the 3D FeRAM100ofFIG.1.

The 3D FeRAM100amay be different from the 3D FeRAM100ofFIG.1in the structure of the first electrode130a, the ferroelectric layer140a, and the second electrode150aconstituting an FeCap. However, the 3D FeRAM100amay be substantially the same as the 3D FeRAM100ofFIG.1in the circuit connection relationship with the semiconductor pattern110, except that the ferroelectric layers140aare not connected to each other in the vertical direction (z direction). Therefore, the 3D FeRAM100amay have a 1TR1Cap structure, thereby solving an endurance problem and a leakage issue due to use of poly Si. In addition, the 3D FeRAM100amay have a structure in which the second electrodes150aare separated from each other in correspondence to the bit lines120afor each layer in the vertical direction (z direction), thereby solving a read disturb problem. For reference, as may be seen inFIG.3A, the 3D FeRAM100amay also have a structure in which in one layer in the vertical direction (z direction), the horizontal channel region CH, the horizontal bit line120a, the horizontal first electrode130a, the horizontal second electrode150a, and a part of the vertical word line160are disposed.

FIGS.4A and4Bare horizontal cross-sectional views of a 3D FeRAM according to an embodiment and respectively correspond toFIGS.2B and3B. The description already provided with reference toFIGS.1to3Bis briefly repeated or omitted.

Referring toFIG.4A, a 3D FeRAM100bmay be different from the 3D FeRAM100ofFIG.2Bin a structure of the word line160a. Specifically, in the 3D FeRAM100b, the word line160amay extend from the substrate101in the vertical direction (z direction) and may be disposed in the second horizontal direction (y direction). As may be seen fromFIG.4A, one word line160amay be disposed between adjacent semiconductor patterns110in the second horizontal direction (y direction). Accordingly, the 3D FeRAM100bmay include a single gate transistor in which one word line160ais disposed in each channel region CH.

Referring toFIG.4B, a 3D FeRAM100cmay be different from the 3D FeRAM100aofFIG.3Bin the structure of the word line160a. Specifically, in the 3D FeRAM100c, the word line160amay extend from the substrate101in the vertical direction (z direction) and may be disposed in the second horizontal direction (y direction). As may be seen fromFIG.4B, one word line160amay be disposed between the adjacent semiconductor patterns110in the second horizontal direction (y direction). Accordingly, the 3D FeRAM100cmay include a single gate transistor in which one word line160ais disposed in each channel region CH.

FIG.5is a conceptual diagram illustrating a 3D FeRAM according to an embodiment. The description already provided with reference toFIGS.1to4Bis briefly repeated or omitted.

Referring toFIG.5, a 3D FeRAM100dmay be different the 3D FeRAM100aofFIG.3Ain extension directions of bit lines120b, ferroelectric layers140b, second electrodes150b, and word lines160b. Specifically, the 3D FeRAM100dmay include the substrate (see101inFIG.3A), the semiconductor patterns110, the bit lines120b, the first electrodes130a, the ferroelectric layers140b, the second electrodes150b, and the word lines160b. Structures and materials of the substrate101, the semiconductor pattern110, and the first electrode130aare the same as those described in the 3D FeRAM100aofFIG.3A.

The bit line120bmay extend in the vertical direction (z direction) on the substrate101. In addition, the bit lines120bmay be spaced apart from each other in the second horizontal direction (y direction) and disposed at positions corresponding to the semiconductor pattern110. For example, the bit line120bmay be disposed on one side surface of the semiconductor pattern110in the first horizontal direction (x direction), and in a column in the second horizontal direction (y direction), the semiconductor patterns110disposed in the vertical direction (z direction) may be connected together to the bit lines120bdisposed in the corresponding column.

The ferroelectric layers140bmay be disposed spaced apart from each other in the second horizontal direction (y direction) on the substrate101and may extend in the vertical direction (z direction). The ferroelectric layer140bmay contact the first electrode130aat a position corresponding to the semiconductor pattern110in the vertical direction (z direction) and the second horizontal direction (y direction). As the ferroelectric layers140bare spaced apart from each other in the second horizontal direction (y direction), the ferroelectric layers140bmay be separated from each other in the second horizontal direction (y direction).

A specific structure of the ferroelectric layer140bmay be substantially the same as that of the ferroelectric layer140aof the 3D FeRAM100aofFIG.3A, except for a direction in which the ferroelectric layer140bextends. Accordingly, the ferroelectric layer140bmay include an extension extending in the vertical direction (z direction) on a vertical cross-section, and a protrusion protruding in the first horizontal direction (x direction) from the extension and contacting the first electrode130aon a vertical cross-section. Also, the ferroelectric layer140bmay have a ‘’ shape on a horizontal cross-section. Here, the vertical cross-section may indicate a cross-section perpendicular to the second horizontal direction (y direction). A material of the ferroelectric layer140band a single layer or multilayer structure are the same as in the description of the 3D FeRAM100ofFIG.1.

In addition, the ferroelectric layer140bmay have a structure of the ferroelectric layer140of the 3D FeRAM100ofFIG.1. That is, the ferroelectric layer140bmay have a structure extending in each of the vertical direction (z direction) and the second horizontal direction (y direction). In such a structure, the first electrode130amay have the structure of the first electrode130of the 3D FeRAM100ofFIG.1.

The second electrode150bmay extend from the substrate101in the vertical direction (z direction). In addition, the second electrodes150bmay be spaced apart from each other in the second horizontal direction (y direction) and may be disposed at positions corresponding to the semiconductor patterns110. The second electrode150bmay be disposed on one side surface of the ferroelectric layer140bin the first horizontal direction (x direction). That is, the first electrode130amay be disposed on one side surface of the ferroelectric layer140bin the first horizontal direction (x direction) and the second electrode150bmay be disposed on the other side surface thereof.

A specific structure of the second electrode150bmay be substantially the same as that of the second electrode150aof the 3D FeRAM100aofFIG.3A, except for a direction in which the second electrode150bextends. Accordingly, the second electrode150bmay have a straight strip shape extending in the vertical direction (z direction) on the vertical cross-section. In addition, the second electrode150bmay have a rectangular shape filling the ‘’-shaped inside of the ferroelectric layer140bon the horizontal cross-section. Here, the vertical cross-section may indicate a cross-section perpendicular to the second horizontal direction (y direction). A material of the second electrode150bis the same as in the description of the 3D FeRAM100ofFIG.1.

The word lines160bmay be spaced apart from each other in the vertical direction (z direction) on the substrate101and may extend in the second horizontal direction (y direction). As may be seen fromFIG.5, two word lines160bmay be disposed between adjacent semiconductor patterns110in the vertical direction (z direction). However, according to an embodiment, one word line160bmay be disposed between the adjacent semiconductor patterns110in the vertical direction (z direction).

A comparison between the 3D FeRAM100dand the 3D FeRAM100aofFIG.3Ais as follows. In the 3D FeRAM100aofFIG.3A, the bit line120a, the ferroelectric layer140a, and the second electrode150amay extend in the second horizontal direction (y direction) on the substrate101, and the word line160may extend in the vertical direction (z direction) on the substrate101. In contrast, in the 3D FeRAM100d, the word line160bmay extend in the second horizontal direction (y direction) on the substrate101, and the bit line120b, the ferroelectric layer140b, and the second electrode150bmay extend in the vertical direction (z direction) on the substrate101. As described above, the 3D FeRAM100dmay be substantially the same as the 3D FeRAM100aofFIG.3Ain a circuit connection relationship, except for extension directions of the bit line120b, the ferroelectric layer140b, and the second electrode150b. Accordingly, the 3D FeRAM100dmay have substantially the same advantages as the 3D FeRAM100aofFIG.3A.

FIGS.6A to16Bare vertical and horizontal cross-sectional views illustrating a process of manufacturing the 3D FeRAM ofFIGS.2A and2B.FIGS.6A,7A,8A,9A,10A,11A,12A,13A,14A,15A and16Aare vertical cross-sectional views corresponding toFIG.2A, andFIGS.6B,7B,8B,9B,10B,11B,12B,13B,14B,15B and16Bare horizontal cross-sectional views corresponding toFIG.2B.FIGS.6A to16Bare described with reference toFIGS.1to2B, and the description already provided with reference toFIGS.1to2Bis briefly repeated or omitted.

Referring toFIGS.6A and6B, in the manufacturing method of the 3D FeRAM, first, first insulating layers1701and semiconductor layers1101are alternately stacked on the substrate101. The first insulating layer1701may include, for example, silicon oxide, and the semiconductor layer1101may include, for example, poly Si. However, the first insulating layer1701and the semiconductor layer1101are not limited to the above materials. Hereinafter, the first insulating layers1701and the semiconductor layers1101stacked on the substrate101are referred to as a ‘stacked structure’.

Referring toFIGS.7A and7B, trenches penetrating the stacked structure, extending in the vertical direction (z direction) and the first horizontal direction (x direction), and spaced apart from each other in the second horizontal direction (y direction) are formed. An upper surface of the substrate101may be exposed through an inner bottom surface of the trench. In addition, the first insulating layers1701and the semiconductor layers1101, which are alternately stacked, may be exposed through an inner side surface of the trench. After the trench is formed, the trench is filled with a second insulating layer1801. The semiconductor layers1101may be separated from each other in the second horizontal direction (y direction) by the second insulating layers1801. In addition, the stacked structure may include the second insulating layer1801.

The second insulating layer1801may have a different etching rate from that of the first insulating layer1701. For example, with respect to an etchant that etches the semiconductor layer1101, the etching rate of the second insulating layer1801may be higher than that of the first insulating layer1701. Specifically, with respect to the etchant that etches the semiconductor layer1101, the etching rate of the semiconductor layer1101is the highest, the etching rate of the second insulating layer1801is the second highest, and the etching rate of the first insulating layer1701may have the lowest. When the semiconductor layer1101includes poly Si and the first insulating layer1701includes oxide, the second insulating layer1801may include nitride. However, materials of the semiconductor layer1101, the first insulating layer1701, and the second insulating layer1801are not limited to the above materials.

Referring toFIGS.8A and8B, after the second insulating layer1801is formed, the first line cut LC1penetrating the stacked structure and extending in the vertical direction (z direction) and the second horizontal direction (y direction) is formed. The upper surface of the substrate101may be exposed through an inner bottom surface of the first line cut LC1, and the first insulating layer1701and the second insulating layer1801, and the semiconductor layer1101, which are alternately stacked, may be exposed through an inner side surface of the first line cut LC1. After the first line cut LC1is formed, a first recess R1is formed in the first horizontal direction (x direction) by etching the semiconductor layer1101exposed through the inner side surface of the first line cut LC1.

As described above, the etching rate of the first insulating layer1701is lower than that of the second insulating layer1801, and accordingly, when the semiconductor layer1101is etched, the second insulating layer1801may be slightly etched. However, the first insulating layer1701may hardly be etched. Accordingly, when the semiconductor layer1101is etched by a first thickness A1in the first horizontal direction (x direction) from the first line cut LC1indicated by a dotted line inFIG.8B, the second insulating layer1801may be etched by a second thickness A2, which is less than the first thickness A1. The first insulating layer1701may be etched to a very fine thickness or hardly etched in the first horizontal direction (x direction) from the first line cut LC1. For example, the first insulating layer1701may be etched by a third thickness which is less than the second thickness A2.

After the first recess R1is formed, a junction may be formed by doping a side portion of the semiconductor layer1101exposed through the first recess R1with impurities. In addition, a silicide layer may be formed by performing a silicide process for ohmic contact with a metal layer, for example, the first electrode130.

Referring toFIGS.9A and9B, a first electrode material layer1301is formed on the semiconductor layer1101, the first insulating layer1701, and the second insulating layer1801exposed through the first line cut LC1and the first recess R1. The first electrode material layer1301may be formed as thin as several tens to hundreds of nm. However, a thickness of the first electrode material layer1301is not limited to the above numerical range. As shown inFIGS.9A and9B, the first electrode material layer1301may include a ‘’ shaped portion on a horizontal cross-section and a vertical cross-section.

Referring toFIGS.10A and10B, after the first electrode material layer1301is formed, third insulating layers190filling the ‘’-shaped portion of the first electrode material layer1301are formed. The third insulating layer190may be formed by allowing an insulating material to remain only in the ‘’-shaped portion through an anisotropic etching process after filling both the ‘’-shaped portion of the first electrode material layer1301and the first line cut LC1with the insulating material. The third insulating layer190may be formed to protect the ‘’-shaped portion of the first electrode material layer1301in a node separation process of the first electrode material layer1301. The third insulating layer190may include a material having an etching rate that is different from that of each of the first insulating layer1701and the second insulating layer1801.

Referring toFIGS.11A and11B, the node separation process of the first electrode material layer1301is performed. Through the node separation process, the first electrode material layers1301are separated from each other in the vertical direction (z direction) and the second horizontal direction (y direction), and thus, the first electrode130may be formed. The node separation process may be performed by etching the first electrode material layer1301exposed through the first line cut LC1. As described above, in the node separation process, because the ‘’-shaped portion of the first electrode material layer1301is covered by the third insulating layer190, the ‘’-shaped portion may remain without being etched. After the first electrode130is formed, the third insulating layer190may be removed.

Referring toFIGS.12A and12B, after the first electrode130is formed, the ferroelectric layer140and a second electrode material layer1501are sequentially formed on the first electrode130. According to an embodiment, the ferroelectric layer140may have a multilayer structure. For example, the ferroelectric layer140may have a triple layer structure of a first ferroelectric thin film, an AlO thin film, and a second ferroelectric thin film or a five layer structure of the first ferroelectric thin film, a first AlO thin film, the second ferroelectric thin film, a second AlO thin film, and a third ferroelectric thin film. However, a multilayer structure of the ferroelectric layer140is not limited to the triple layer or five layer structure.

As shown inFIGS.12A and12B, the second electrode material layer1501may fill both a ‘’-shaped portion of the ferroelectric layer140and the first line cut LC1. However, according to an embodiment, the second electrode material layer1501may be formed to a certain thickness on a sidewall and a bottom surface of the first line cut LC1by filling entirely the ‘’ shaped portion of the ferroelectric layer140but partially filling the first line cut LC1.

Referring toFIGS.13A and13B, after the second electrode material layer1501is formed, the second electrode150is formed by re-etching the first line cut LC1and separating the second electrode material layers1501from each other in the vertical direction (z direction). By re-etching the first line cut LC1, as shown inFIG.13A, the second electrodes150may be spaced apart from each other in the vertical direction (z direction). In addition, as shown inFIG.13B, the second electrode150may include the extension150E extending in the second horizontal direction (y direction) on the horizontal cross-section and the protrusion150P protruding from the extension150E in the first horizontal direction (x direction on the horizontal cross-section. After the second electrode150is formed, the first line cut LC1may be filled with the first insulating layer1701.

Referring toFIGS.14A and14B, thereafter, at a position opposite to the first line cut LC1in the first horizontal direction (x direction) with respect to the semiconductor layer1101, the second line cut LC2penetrating the stacked structure and extending in the second horizontal direction (y direction) and the vertical direction (z direction) is formed. An upper surface of the substrate101may be exposed through an inner bottom surface of the second line cut LC2, and the first insulating layer1701, the second insulating layer1801, and the semiconductor layer1101may be exposed through an inner side surface of the second line cut LC2. After the second line cut LC2is formed, a second recess R2is formed in the first horizontal direction (x direction) by etching the semiconductor layer1101exposed through the inner side surface of the second line cut LC2. The semiconductor pattern110may be formed through the formation of the second recess R2.

As described above, with respect to the etching etchant of the semiconductor layer1101, the etching rate of the first insulating layer1701is lower than that of the second insulating layer1801, and accordingly, when the semiconductor layer1101is etched, the second insulating layer1801may be slightly etched. However, the first insulating layer1701may hardly be etched. Accordingly, when the semiconductor layer1101is etched by a first thickness B1in the first horizontal direction (x direction) from the second line cut LC2indicated by a dotted line inFIG.14B, the second insulating layer1801may be etched by a second thickness B2, which is less than the first thickness B1.

After the second recess R2is formed, a junction may be formed by doping a side portion of the semiconductor pattern110exposed through the second recess R2with impurities. In addition, a silicide layer may be formed by performing a silicide process for ohmic contact with a metal layer, for example, the bit line120.

Referring toFIGS.15A and15B, the bit line120is formed on the semiconductor pattern110, the first insulating layer1701, and the second insulating layer1801exposed through the second line cut LC2and the second recess R2. More specifically, first, a bit line material layer filling the second line cut LC2and the second recess R2is formed. Thereafter, the bit line120is formed by re-etching the second line cut LC2and separating the bit line material layers from each other in the vertical direction (z direction). As shown inFIG.15A, the bit lines120may be spaced apart from each other in the vertical direction (z direction). In addition, as shown inFIG.15B, a side portion of the bit line120extending in the second horizontal direction (y direction) and contacting the semiconductor pattern110in the first horizontal direction (x direction) may have a concave-convex shape, and an opposite side portion thereof may have a straight line shape. The concave-convex shape of the side portion of the bit line120may be caused by etching a part of the second insulating layer1801during the etching of the semiconductor layer1101. After the bit line120is formed, the interlayer insulating layer170may be formed by filling the second line cut LC2with the first insulating layer1701.

Referring toFIGS.16A and16B, a first trench T1is formed between adjacent semiconductor patterns110in the second horizontal direction (y direction). The first trench T1may penetrate the second insulating layer1801, extend in the vertical direction (z direction), and expose the upper surface of the substrate101through an inner bottom surface thereof. The isolation insulating layer180may be formed through the formation of the first trench T1.

As shown inFIG.16B, two first trenches T1may be formed between the adjacent semiconductor patterns110in the second horizontal direction (y direction). However, according to an embodiment, one first trench T1may be formed between the adjacent semiconductor patterns110in the second horizontal direction (y direction). After the first trench T1is formed, the word line160may be formed by filling the first trench T1with the gate dielectric layer162and a conductive layer.

FIGS.17A and17Bare plan views illustrating a mask structure for forming the word line160aof the 3D FeRAM ofFIG.4A or4Band a mask structure for forming the word line160of the FeRAM ofFIG.2B or3B, respectively.

Referring toFIG.17A, to form the word line160aas shown inFIG.4A or4B, when the first trench T1is formed, a first mask M1may be used. The first mask M1may have a first open portion OP1extending in the second horizontal direction (y direction), and the semiconductor pattern110and the second insulating layer1801may be partially exposed through the first open portion OP1. Thereafter, one first trench T1may be formed between the adjacent semiconductor patterns110in the second horizontal direction (y direction) by removing only the second insulating layer1801by using the difference in the etching rate between the semiconductor pattern110and the second insulating layer1801. Thereafter, the word line160aas shown inFIG.4A or4Bmay be formed by filling the first trench T1with the gate dielectric layer162and a conductive layer.

Referring toFIG.17B, to form the word line160as shown inFIG.2B or3B, when the first trench T1is formed, a second mask M2may be used. The second mask M2may have a second open portion OP2in a rectangular shape, and the semiconductor pattern110and a part of the second insulating layer1801on both sides of the semiconductor pattern110in the second horizontal direction (y direction) may be exposed through the second open portion OP2. Thereafter, two first trenches T1may be formed between the adjacent semiconductor patterns110in the second horizontal direction (y direction) by removing only a part of the second insulating layer1801by using the difference in the etching rate between the semiconductor pattern110and the second insulating layer1801. Thereafter, the word line160as shown inFIG.2B or3Bmay be formed by filling the first trench T1with the gate dielectric layer162and a conductive layer.

FIGS.18A to24Bare vertical and horizontal cross-sectional views illustrating a process of manufacturing the 3D FeRAM ofFIGS.3A and3B.FIGS.18A,19A,20A,21A,22A,23A and24Aare vertical cross-sectional views corresponding toFIG.3A, andFIGS.18B,19A,20B,21B,22B,23B and24Bare horizontal cross-sectional views corresponding toFIG.3B.FIGS.18A to24Bare described together with reference toFIGS.1,3A, and3B, and the description already provided with reference toFIGS.1,3A, and3Bis briefly repeated or omitted.

Referring toFIGS.18A and18B, in the manufacturing method of 3D FeRAM, first, the first insulating layers1701and the semiconductor layers1101are alternately stacked on the substrate101. The first insulating layer1701may include, for example, silicon oxide, and the semiconductor layer1101may include, for example, poly Si. However, the first insulating layer1701and the semiconductor layer1101are not limited to the above materials. Hereinafter, the first insulating layers1701and the semiconductor layers1101stacked on the substrate101are referred to as a ‘stacked structure’.

Subsequently, the first line cut LC1penetrating the stacked structure and extending in the vertical direction (z direction) and the second horizontal direction (y direction) is formed. An upper surface of the substrate101may be exposed through an inner bottom surface of the first line cut LC1, and the first insulating layers1701and the semiconductor layers1101, which are alternately stacked, may be exposed through an inner side surface of the first line cut LC1. After the first line cut LC1is formed, a third recess R3is formed in the first horizontal direction (x direction) by etching the semiconductor layer1101exposed through an inner side surface of the first line cut LC1.

After the third recess R3is formed, a junction may be formed by doping a side portion of the semiconductor layer1101exposed through the third recess R3with impurities. In addition, a silicide layer may be formed by performing a silicide process for ohmic contact with the first electrode130a.

Referring toFIGS.19A and19B, the first electrode material layer1301is formed on an inner portion of the third recess R3. The first electrode material layer1301may be formed by forming an electrode material to fill the third recess R3, and then, forming a recess again by etching a part of the electrode material, and leaving a part of the electrode material inside the recess. The first electrode material layers1301may extend in the second horizontal direction (y direction) and be spaced apart from each other in the vertical direction (z direction).

Referring toFIGS.20A and20B, after the first electrode material layer1301is formed, the ferroelectric material layer1401and the second electrode150aare formed on the first electrode material layer1301. The ferroelectric material layer1401and the second electrode150amay be formed by sequentially forming ferroelectric materials and electrode materials on the first electrode material layer1301, separating the ferroelectric materials from each other, and separating the electrode materials from each other in the vertical direction (z direction) by re-etching the first line cut LC1.

The ferroelectric material layers1401may be spaced apart from each other in the vertical direction (z direction) and may extend in the second horizontal direction (y direction). In addition, the ferroelectric material layer1401may have a straight band shape extending in the second horizontal direction (y direction) on a horizontal cross-section, and may have a ‘’ shape on a vertical cross-section. The second electrodes150amay be spaced apart from each other in the vertical direction (z direction) and may extend in the second horizontal direction (y direction). In addition, the second electrode150amay have a straight band shape extending in the second horizontal direction (y direction) on the horizontal cross-section, and may have a quadrangular shape filling a ‘’ shaped inside of the ferroelectric material layer1401on the vertical cross-section. After the ferroelectric material layer1401and the second electrode150aare formed, the first line cut LC1may be filled with the first insulating layer1701.

Referring toFIGS.21A and21B, the second line cut LC2penetrating the stacked structure and extending in the vertical direction (z direction) and the second horizontal direction (y direction) is formed. An upper surface of the substrate101may be exposed through an inner bottom surface of the second line cut LC2, and the first insulating layer1701and the semiconductor layer1101may be exposed through an inner side surface of the second line cut LC2. After the second line cut LC2is formed, a fourth recess R4is formed in the first horizontal direction (x direction) by etching the semiconductor layer1101exposed through the inner side surface of the second line cut LC2.

After the fourth recess R4is formed, a junction may be formed by doping a side portion of the semiconductor layer1101exposed through the fourth recess R4with impurities. In addition, a silicide layer may be formed by performing a silicide process for ohmic contact with the bit line120a.

Referring toFIGS.22A and22B, the bit line120ais formed on the semiconductor layer1101and the first insulating layer1701exposed through the second line cut LC2and the fourth recess R4. More specifically, first, bit line material layers filling the second line cut LC2and the fourth recess R4is formed. Then, the bit line120ais formed by re-etching the second line cut LC2and separating the bit line material layers from each other in the vertical direction (z direction). As shown inFIG.22A, the bit lines120amay be spaced apart from each other in the vertical direction (z direction). Also, as shown inFIG.22B, the bit line120amay have a straight band shape extending in the second horizontal direction (y direction). After the bit line120ais formed, the second line cut LC2may be filled with the first insulating layer1701.

Referring toFIGS.23A and23B, trenches spaced apart from each other in the second horizontal direction (y direction) and penetrating the stacked structure are formed. The trench may extend in the vertical direction (z direction), and may expose the upper surface of the substrate101through an inner bottom surface thereof. Through the formation of the trench, the semiconductor layer1101and the first electrode material layer1301are separated from each other in the second horizontal direction (y direction), so that the semiconductor pattern110and the first electrode130amay be formed. The semiconductor pattern110may have a rectangular pillar shape extending in the first horizontal direction (x direction). The first electrode130amay also have a rectangular pillar shape, and accordingly, each of a vertical cross-section and a horizontal cross-section thereof may have a rectangular shape.

Through the formation of the trench, the ferroelectric layer140amay be formed by etching a part of the side surface of the ferroelectric material layer1401. Accordingly, the ferroelectric layer140amay include the extension140E extending in the second horizontal direction (y direction) and the protrusion140P on the side surface of the semiconductor pattern110on the horizontal cross-section. The trench may be filled with the first insulating layer1701.

Referring toFIGS.24A and24B, the first trench T1penetrates the stacked structure and is formed between adjacent semiconductor patterns110in the second horizontal direction (y direction). The first trench T1may extend in a vertical direction (z direction) and may expose the upper surface of the substrate101on an inner bottom surface thereof. As shown inFIG.24B, two first trenches T1may be formed between the adjacent semiconductor patterns110in the second horizontal direction (y direction). However, according to an embodiment, one first trench T1may be formed between the adjacent semiconductor patterns110in the second horizontal direction (y direction). The interlayer insulating layer170may be formed through the formation of the first trench T1. After the first trench T1is formed, the word line160may be formed by filling the first trench T1with the gate dielectric layer162and a conductive layer.

While aspects of embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.