Mechanism for generating a virtual identifier

In one embodiment, a method is provided that may include generating, at least in part, an identifier to be associated with a group of devices. The group of devices may comprise at least two devices. The identifier may be generated, at least in part, based, at least in part, upon respective source identifiers identifying, at least in part, respective sources of the at least two devices. Of course, many modifications, variations, and alternatives are possible without departing from this embodiment.

FIELD

This disclosure relates to identifier generation.

BACKGROUND

In one conventional data storage network, a computer node includes a host processor and a host bus adapter (HBA). The HBA communicates with a plurality of physical data storage devices in a redundant array of inexpensive disks (RAID). The data storage devices may be identified by respective unique world wide names (WWNs) that the HBA may use to identify the data storage devices in its communications with the data storage devices.

From the vantage point of a human user's management of, and interaction with the data storage arrangement, it may be desirable to consider the plurality of physical data storage devices as constituting a single logical or virtual data storage device. In order to facilitate the user's management of and interaction with such a logical or virtual data storage device, the HBA may generate a WWN to identify the logical or virtual data storage device that comprises the plurality of physical data storage devices. If the WWN generated by the HBA conflicts with the WWN of another physical, logical, or virtual device in the network, it may no longer be possible to uniquely identify the devices having the conflicting WWNs. Disadvantageously, this may have a deleterious effect on the network's performance and manageability.

Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.

DETAILED DESCRIPTION

FIG. 1illustrates a system embodiment100. System100may include a host processor12coupled to a chipset14. Host processor12may comprise, for example, an Intel® Pentium® IV microprocessor that is commercially available from the Assignee of the subject application. Of course, alternatively, host processor12may comprise another type of microprocessor, such as, for example, a microprocessor that is manufactured and/or commercially available from a source other than the Assignee of the subject application, without departing from this embodiment.

Chipset14may comprise a host bridge/hub system that may couple host processor12, a system memory21and a user interface system16to each other and to a bus system22. Chipset14may also include an input/output (I/O) bridge/hub system (not shown) that may couple the host bridge/bus system to bus22. Chipset14may comprise one or more integrated circuit chips, such as those selected from integrated circuit chipsets commercially available from the assignee of the subject application (e.g., graphics memory and I/O controller hub chipsets), although one or more other integrated circuit chips may also, or alternatively be used, without departing from this embodiment. User interface system16may comprise, e.g., a keyboard, pointing device, and display system that may permit a human user to input commands to, and monitor the operation of, system100.

Bus22may comprise a bus that complies with the Peripheral Component Interconnect (PCI) Express™ Base Specification Revision 1.0, published Jul. 22, 2002, available from the PCI Special Interest Group, Portland, Oreg., U.S.A. (hereinafter referred to as a “PCI Express™ bus”). Alternatively, bus22instead may comprise a bus that complies with the PCI-X Specification Rev. 1.0a, Jul. 24, 2000, available from the aforesaid PCI Special Interest Group, Portland, Oreg., U.S.A. (hereinafter referred to as a “PCI-X bus”). Also alternatively, bus22may comprise other types and configurations of bus systems, including, for example, other or later developed versions of the PCI Express™ or PCI-X buses, without departing from this embodiment.

System embodiment100may comprise storage27. Storage27may comprise RAID29. RAID29may comprise a plurality of physical storage devices28A,28B, . . .28N. Storage27may be communicatively coupled to operative circuitry38of circuit card20via one or more communication media40. Each of the storage devices28A,28B, . . .28N may comprise one or more respective mass storage devices. As used herein, the terms “storage” and “storage device” may be used interchangeably to mean one or more apparatus into, and/or from which, data and/or commands may be stored and retrieved, respectively. Also, as used herein, the term “mass storage device” means one or more storage devices capable of non-volatile storage of data and/or commands, and, for example, in this embodiment, may include, without limitation, one or more magnetic, optical, and/or semiconductor storage devices.

In this embodiment, card20may comprise, for example, an HBA. Of course, the number of storage devices28A,28B . . .28N, and/or the number of communication media comprised in media40may vary without departing from this embodiment.

As used herein, a “communication medium” means a physical entity through which electromagnetic energy may be transmitted and/or received. When communicatively coupled together via one or more media40, storage27, circuitry38, and host computer system110may together comprise a network10.

The RAID level that may be implemented by RAID29may be 0, 1, or greater than 1. Depending upon, for example, the RAID level implemented in RAID29, the number of mass storage devices comprised in storage devices28A,28B, . . .28N may vary so as to permit the number of such mass storage devices to be at least sufficient to implement the RAID level implemented in RAID29.

Processor12, system memory21, chipset14, bus22, and circuit card slot30may be comprised in a single circuit board, such as, for example, a system motherboard32. Host computer system110may comprise system motherboard32.

In this embodiment, operative circuitry38may exchange data and/or commands with storage27, via one or more media40in accordance with, e.g., Serial Attached Small Computer Systems Interface (SAS) protocol, Small Computer Systems Interface (SCSI) protocol, Fibre Channel (FC) protocol, and/or iSCSI protocol. Of course, alternatively, circuitry38may exchange data and/or commands with storage27in accordance with other and/or additional communication protocols, without departing from this embodiment.

In accordance with this embodiment, if circuitry38and storage27exchange data and/or commands in accordance with FC protocol, the FC protocol may comply or be compatible with the protocol described in ANSI Standard Fibre Channel (FC) Physical and Signaling Interface-3 X3.303:1998 Specification (hereinafter, the “FC Specification”), and/or later-published versions and/or modifications of the FC Specification. If circuitry38and storage27exchange data and/or commands in accordance with SCSI protocol, the SCSI protocol may comply or be compatible with the interface/protocol described in American National Standards Institute (ANSI) Small Computer Systems Interface-2 (SCSI-2) ANSI X3.131-1994 Specification (hereinafter, the “SCSI Specification”), and/or later-published versions and/or modifications of the SCSI Specification. If circuitry38and storage27exchange data and/or commands in accordance with SAS protocol, the SAS protocol may comply or be compatible with the protocol described in “Information Technology—Serial Attached SCSI (SAS),” Working Draft American National Standard of International Committee For Information Technology Standards (INCITS) T10 Technical Committee, Project T10/1562-D, Revision 2b, published 19 Oct. 2002, by American National Standards Institute (hereinafter, the “SAS Standard”) and/or later-published versions and/or modifications of the SAS Standard. If circuitry38and storage27exchange data and/or commands in accordance with iSCSI protocol, the iSCSI protocol may comply or be compatible with the protocol described in, Satran et al., “iSCSI,” draft-ietf-ips-iscsi-20, Internet Draft, Internet Engineering Task Force, IP Storage Working Group, Jan. 19, 2003 (hereinafter, the “iSCSI Specification”), and/or later-published versions and/or modifications of the iSCSI Specification.

Depending upon, for example, whether bus22comprises a PCI Express™ bus or a PCI-X bus, circuit card slot30may comprise, for example, a PCI Express™ or PCI-X bus compatible or compliant expansion slot or interface36. Interface36may comprise a bus connector37may be electrically and mechanically mated with a mating bus connector34that may be comprised in a bus expansion slot or interface35in circuit card20.

As used herein, “circuitry” may comprise, for example, singly or in any combination, analog circuitry, digital circuitry, hardwired circuitry, programmable circuitry, state machine circuitry, and/or memory that may comprise program instructions that may be executed by programmable circuitry. In this embodiment, circuit card20may comprise operative circuitry38. Circuitry38may comprise, for example, identifier generator circuitry52, computer-readable memory44, computer-readable memory42, and counter circuitry48.

Memory44, memory42, and system memory21each may comprise one or more of the following types of memories: semiconductor firmware memory, programmable memory, non-volatile memory, read only memory, electrically programmable memory, random access memory, flash memory, magnetic disk memory, and/or optical disk memory. Either additionally or alternatively, memory44, memory42, and/or system memory21may comprise other and/or later-developed types of computer-readable memory.

Machine-readable program instructions may be stored in memory21and memory44. These instructions may be accessed and executed by operative circuitry38and/or processor12. When executed by circuitry38and/or processor12, these instructions may result in circuitry38, processor12, and/or system110performing the operations described herein as being performed by circuitry38, processor12, and/or system110.

Slot30and card20may be constructed to permit card20to be inserted into slot30. When card20is properly inserted into slot30, connectors34and36may become electrically and mechanically coupled to each other. When connectors34and36are so coupled to each other, circuitry38becomes electrically coupled to bus22and may exchange data and/or commands with system memory21, host processor12, and/or user interface system16via bus22and chipset14.

Alternatively, without departing from this embodiment, operative circuitry38may not be comprised in card20, but instead, may be comprised in other structures, systems, and/or devices. These other structures, systems, and/or devices may be, for example, comprised in motherboard32, coupled to bus22, and exchange data and/or commands with other components (such as, for example, system memory21, host processor12, and/or user interface system16) in system100. For example, without departing from this embodiment, some or all of circuitry38may be comprised in one or more integrated circuits comprised in chipset14.

In this embodiment, counter circuitry48may be capable of determining an activation time and of maintaining value50may indicate and/or specify that time. For example, in this embodiment, circuitry48may be capable of counting the number of seconds that elapse after the last most recent restarting and/or resetting of circuitry38, system100, and/or system110. Circuitry48may maintain and store value50in not shown computer-readable memory comprised in circuitry48. At any given time, value50may be equal to the number of seconds that have currently elapsed after this last most recent restarting and/or resetting of circuitry38, system100, and/or system110.

In this embodiment, operative circuitry38may store and maintain in memory42table46. As shown inFIG. 2, table46may contain identifiers200A,200B,200C . . .200N of storage devices28A,28B, . . .28N, and/or other physical, logical, and/or virtual devices in system100. As used herein, “identifier” means one or more strings, values, and/or symbols capable of being used to identify, at least in part, one or more physical, logical, and/or virtual devices, and/or one or more groups of such devices.

In this embodiment, each of these identifiers200A,200B,200C, . . .200N may be or comprise a respective WWN in accordance with, for example, FC protocol, SAS protocol, and/or iSCSI protocol. Alternatively or additionally, depending upon, for example, the one or more communication protocols in accordance with which circuitry38may exchange data and/or commands with storage27, one or more of identifiers200A,200B,200C, . . .200N may comprise, for example, a medium access control (MAC) address that may comply or be compatible with, for example, an Ethernet protocol that may comply or be compatible with the protocol described in Institute of Electrical and Electronics Engineers, Inc. (IEEE) Std. 802.3, published on Oct. 20, 2000. Of course, the number and types of identifiers and/or WWNs in table46may vary without departing from this embodiment.

In this embodiment, each of the identifiers200A,200B,200C . . .200N may comprise a respective plurality of fields. Each of these fields may contain a respective numerical value. For example, in this embodiment, identifier200A may comprise fields202A,204A,206A that may contain numerical values203A,205A,207A, respectively; identifier200B may comprise fields202B,204B,206B that may contain numerical values203B,205B,207B, respectively; identifier200C may comprise fields202C,204C,206C that may contain numerical values203C,205C,207C, respectively; and, identifier200N may comprise fields202N,204N,206N that may contain numerical values203N,205N,207N, respectively.

In this embodiment, depending upon, for example, the type of identifiers that may be stored in table46, values203A,203B,203C, and203N may be or comprise respective IEEE Naming Assignment Authority (NAA) assigned WWN type values, for example, that may be compatible and/or in compliance with IEEE Std. 802, published 1990 (hereinafter the “IEEE Standard”). Also in this embodiment, depending upon, for example, the identifiers200A,200B,200C, . . .200N that may be stored in table46, values205A,205B,205C, . . .205N may be or comprise WWN company identification numbers that may identify the manufacturer (e.g., manufacturing company) of the devices identified by identifiers200A,200B,200C, . . .200N. Additionally, in this embodiment, depending upon, for example, the identifiers200A,200B,200C, . . .200N that may be stored in table46, values207A,207B,207C, . . .207N may be or comprise source identifiers of the devices identified by identifiers200A,200B,200C, . . .200N. As used herein, a “source identifier” means one or more strings, values, and/or symbols that may be capable of being used to identify, at least in part, at least one source and/or origin of one or more physical, logical, and/or virtual devices, and/or one or more groups of such devices. For example, in this embodiment, values207A,207B,207C, . . .207N may be or comprise WWN vendor identification numbers that may uniquely identify, at least in part, vendors of the devices identified by identifiers200A,200B,200C, . . .200N. Of course, depending upon the identifiers200A,200B,200C, . . .200N in table46, the values203A,205A,207A,203B,205B,207B,203C,205C,207C,203N,205N, and207N that may be comprised in identifiers200A,200B,200C, . . .200N may differ without departing from this embodiment.

One or more program processes25, such as, for example, one or more operating system processes, may reside in memory21and be executed by processor12. The execution of these one or more processes25may permit and/or facilitate, for example, a human user (not shown) to control and monitor, using system16, operation of storage27and circuitry38.

With reference now being made toFIG. 3, operations300that may be performed in system100in accordance with an embodiment will be described. After, for example, a reset and/or restart of circuitry38, system100, and/or system110, the execution of one or more processes25by processor12may result in processor12requesting, at least in part, that circuitry38generate an identifier that may identify a logical and/or virtual device that may represent and/or comprise all or at least one or more respective portions of a group of two or more devices, for example, in order to facilitate the ability of the human user of system100to control and/or manage RAID29. For example, processor12may request that circuitry38generate an identifier that may identify a logical and/or virtual storage device that may comprise a group54of physical storage devices28A and28B in RAID29.

In response, at least in part, to this request from processor12, circuitry38may signal circuitry52. This may result in circuitry52extracting from one or more WWNs identifying, at least in part, one or more of devices28A and28B one or more vendor identification numbers, as illustrated by operation302inFIG. 3. For example, in this embodiment, identifiers200A and200B may be or comprise WWNs identifying devices28A and28B in group54, and source identifiers207A and207B may be or comprise vendor identification numbers identifying the respective vendors of devices28A and28B. In this example, as part of operation302, circuitry52may extract these vendor identification numbers from identifiers200A and200B.

Thereafter, in this embodiment, based at least in part upon source identifiers207A and207B and/or the vendor identification numbers comprised in source identifiers207A and207B, circuitry52may generate, at least in part, an identifier to be associated with group54of devices28A and28B, as illustrated by operation303inFIG. 3. Thereafter, as illustrated by operation312, circuitry54may generate, at least in part, a WWN to be associated with group54of devices28A and28B, based at least in part upon the identifier generated, at least in part, as a result of operation303. Thereafter, circuitry38may store in table46the WWN generated, at least in part, as a result of operation312, and circuitry38may provide this WWN to processor12. This WWN may be used by one or more processes25and/or circuitry38to identify a logical and/or virtual device that may represent and/or comprise group54of devices28A and28B.

For example, in this embodiment, as part of operation303, circuitry52may rotate, by a predetermined, random, or pseudorandom number of bits, one of the two vendor identification numbers207A and207B that may be extracted as a result of operation302(e.g., in this embodiment, the vendor identification number of the second WWN appearing in table46of a device comprised in group54, such as, for example, vendor identification number207B) to generate a rotated number, as illustrated by operation304inFIG. 3. Thereafter, also as part of operation303, circuitry52may perform, as illustrated by operation306, a logical exclusive or (XOR) operation of the other of vendor identification numbers207A and207B (e.g., in this embodiment, the vendor identification number of the first WAN appearing in table46of a device comprised in group54, such as, for example, vendor identification number207A) with the rotated number generated as a result of operation304, to produce a resulting value. Of course many variations are possible without departing from this embodiment.

In this example, group54comprises only devices28A and28B. However, although not shown in the Figures, if, alternatively, group54comprises one or more additional physical devices, operations300may comprise additional operations. For example, if group54comprises an additional physical device identified by identifier200C (seeFIG. 2), operations300may comprise an additional operation in which circuitry52may rotate vendor identification number207C by a predetermined, random, or pseudorandom number of bits, and may perform a logical XOR of the resulting value generated as a result of operation306with the result of the rotation of vendor identification number207C. In like manner, if, further alternatively, yet additional physical devices are comprised in group54, additional iterations of these additional operations may be performed by circuitry52, with the respective additional iterations being directed to rotating the respective vendor identification numbers of the WWNs of these yet additional physical devices, and performing additional respective logical XOR operations involving the respective results of the most recently preceding logical XOR operation iteration with the result of the most recently rotated vendor identification number. In this alternative arrangement, circuitry52may perform, as operation310discussed below, a logical XOR of the final resulting value from completing all of these additional operations and iterations, instead of the resulting value resulting from operation306, with the rotated value generated as a result of operation308.

Returning to the previous example, after operation306has been performed, also as part of operation303, circuitry52may obtain value50from circuitry48, and circuitry52may rotate value50by a predetermined, random, or pseudorandom number of bits, to generate a rotated value, as illustrated by operation308. Also as part of operation303, as illustrated by operation310, circuitry52may perform a logical XOR of this rotated value resulting from operation308, with the resulting value resulting from operation306. In this embodiment, the output value resulting from this logical XOR may be used as an identifier to be associated with group54.

For example, in this embodiment, circuitry52may generate, based at least in part, upon this identifier generated as a result of operation310, a WWN300(seeFIG. 2) to be associated with group54, as illustrated by operation312. WWN300generated as a result of operation312may comprise, for example, fields302,304, and306, that may contain a NAA WWN type value303, WWN company identification number305, and identifier307, respectively. Value303may be equal to at least one of the NAA WWN type values203A and203B in at least one of the identifiers200A and200B. Number305may be equal to or comprise the identifier generated as a result of operation310. Thus, as part of operation312, circuitry52may concatenate value303, number305, and identifier307, and circuitry38may store the resulting concatenation in table46as WWN300. Circuitry38may provide WWN300to processor12. WWN300may be used by one or more processes25and/or circuitry38to identify a logical and/or virtual device that may represent and/or comprise group54of devices28A and28B.

In this embodiment, as a result, at least in part, of generating, identifier306and WWN300, based at least in part upon unique vendor identification numbers207A and207B, and the results of operations304,306,308, and310, it may be highly improbable that the identifier306and WWN300generated as a result of operation303and312, respectively, may be identical to any other vendor identification number and WWN used in system100or network40. Advantageously, this reduces the probability that WWN300may conflict with the WWN of another physical, logical, or virtual device in system100or network40. Additionally, as a result of operations308and310, in this embodiment, identifier306and WWN300may be generated based at least in part upon a rotation of a value indicative of an activation time of system100, circuitry38, and/or system110. Advantageously, this increases the probability that, even if the same physical device is comprised in two or more groups of devices for which identifiers and/or WWNs are generated in accordance with this embodiment, these WWNs will not conflict with the WWN of another physical, logical, or virtual device in system100or network40.

Thus, one system embodiment may comprise a circuit board comprising a circuit card slot and a circuit card capable of being inserted into the slot. The circuit card may comprise circuitry to generate, at least in part, an identifier to be associated with a group of two or more devices. The circuitry may be capable of generating, at least in part, the identifier based, at least in part, upon respective source identifiers identifying of the at least two devices.

Without departing from this embodiment, one or more of the operations comprised in operations300may be carried out, at least in part, by circuitry, one or more software processes, or a combination of circuitry and one or more software processes. Many modifications are possible without departing from this embodiment.