DISPLAY DEVICE

According to one embodiment, a display device includes a base, a first insulating layer, a first pixel electrode on the first insulating layer in a pixel, a second pixel electrode on the first insulating layer in a dummy pixel, a second insulating layer on the first insulating layer, a first organic layer in the pixel and in contact with the first pixel electrode, a second organic layer in the dummy pixel, a partition wall on the second insulating layer and between the organic layers and a common electrode covering the organic layers and the partition wall. An end portion of the first organic layer is in contact with a side surface of the partition wall.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-191068, filed Nov. 17, 2020, the entire contents of which are incorporated herein by reference.

FIELD

BACKGROUND

In recent years, display devices to which organic light-emitting diodes (OLEDs) are applied as display elements have been used in practical applications. Such a display device comprises a pixel electrode, a common electrode, and an organic layer disposed between the pixel electrode and the common electrode.

When patterning elements such as electrodes and wiring lines, which are repeatedly provided in the display area, the shape of the outermost one of these elements are, in some cases, not formed as designed. For example, when patterning pixel electrodes of pixels by etching, the outermost one of the pixel electrodes may be excessively eroded. If such a shape error occurs, the display quality of the display device is degraded.

DETAILED DESCRIPTION

In general, according to one embodiment, a display device includes a base, a first insulating layer disposed on the base, a first pixel electrode disposed on the first insulating layer in a pixel located in a display area, a second pixel electrode disposed on the first insulating layer in a dummy pixel located in a peripheral area on an outer side of the display area, a second insulating layer disposed on the first insulating layer and comprising an opening overlapping the first pixel electrode, a first organic layer disposed in the pixel and in contact with the first pixel electrode via the opening, a second organic layer disposed in the dummy pixel, a partition wall disposed on the second insulating layer and between the first organic layer and the second organic layer and a common electrode covering the first organic layer, the second organic layer and the partition wall. An end portion of the first organic layer is in contact with a side surface of the partition wall.

According to such a configuration, a display device which can improve the display quality can be provided.

Further, in order to make the descriptions more easily understandable, some of the drawings illustrate an X axis, a Y axis and a Z axis orthogonal to each other. A direction along the X axis is referred to as an X direction or a first direction, a direction along the Y axis is referred to as a Y direction or a second direction and direction along the Z axis is referred to as a Z direction or a third direction. A plane defined by the X axis and the Y axis is referred to as an X-Y plane, and a plane defined by the X axis and the Z axis is referred to as an X-Z plane. Here, viewing towards the X-Y plane is referred to as planar view.

Display devices DSP of the embodiments are each an organic electroluminescent display device comprising an organic light-emitting diode (OLED) as a display element, which is to be mounted on a TV, PC, in-vehicle device, mobile terminal, cell phone, etc.

First Embodiment

FIG. 1shows a configuration example of a display device DSP according to the first embodiment. The display device DSP includes a display area DA which displays images and a peripheral area SA on an outer side of the display area DA, on an insulating base10. The base10may be glass or a flexible resin film.

The display area DA comprises a plurality of pixels PX arranged in a matrix along the first direction X and the second direction Y. Each pixel PX comprises a plurality of sub-pixels SP. For example, the pixel PX comprises a red sub-pixel SP1, a green sub-pixel SP2, and a blue sub-pixel SP3. Note that, in addition to the three color sub-pixels, the pixel PX may include four or more sub-pixels of other colors, such as white and the like.

Each sub-pixel SP comprises a pixel circuit1and a display element20that is driven and controlled by the pixel circuit1. The pixel circuit1comprises a pixel switch2, a drive transistor3and a capacitor4. The pixel switch2and the drive transistor3are switching elements each formed of for example, a thin-film transistor.

In the pixel switch2, the gate electrode is connected to a respective scanning line GL, the source electrode is connected to a respective signal line SL, and the drain electrode is connected to one of the electrodes which constitute the capacitor4and the gate electrode of the drive transistor3. In the drive transistor3, the source electrode is connected to the other electrode of the capacitor4and a respective power line PL, and the drain electrode is connected to the anode of the display element20. Note that the configuration of the pixel circuit1is not limited to that of the example illustrated in the figure.

The display element20is an organic light-emitting diode (OLED) as a light-emitting element. For example, a sub-pixel SP1comprises a display element that emits light corresponding to a red wavelength, a sub-pixel SP2comprises a display element that emits light corresponding to a green wavelength, and a sub-pixel SP3comprises a display element that emits light corresponding to a blue wavelength. The configuration of the display elements20will be described later.

The peripheral area SA comprises a plurality of dummy pixels DP that do not display images. For example, the dummy pixels DP surrounds the display area DA. In other words, the dummy pixels DP are located between those pixels PX located on the outermost circumference and each side of the base10.

The dummy pixels DP each comprise a plurality of dummy sub-pixels DS. For example, each dummy pixel DP comprises a dummy sub-pixel DS1having a configuration similar to that of the sub-pixel SP1, a dummy sub-pixel DS2having a configuration similar to that of the sub-pixel SP2, and a dummy sub-pixel DS3having a configuration similar to that of the sub-pixel SP3.

FIG. 2shows an example of the layout of the sub-pixels SP1, SP2and SP3and the dummy sub-pixels DS1, DS2and DS3. Here, four pixels PX enclosed by a single-dotted frame and five dummy pixels DP located therearound as shown inFIG. 1will be focused.

In each of the pixels PX, sub-pixels SP1and SP2are aligned along the second direction Y, sub-pixels SP1and SP3are aligned along the first direction X, and sub-pixels SP2and SP3are aligned along the first direction X. The sub-pixel SP1is formed into substantially a rectangular shape extending along the first direction X. The sub-pixels SP2and SP3are each formed into substantially a rectangular shape extending along the second direction Y. The area of the sub-pixel SP2is greater than the area of the sub-pixel SP1, and the area of the sub-pixel SP3is greater than the area of the sub-pixel SP2. Note that the area of the sub-pixel SP1may be the same as that of the sub-pixel SP2.

Now, let us focus on those pixels PX arranged in the display area DA, the sub-pixels SP1and the sub-pixels SP3are alternately aligned along the first direction X. The sub-pixels SP2and the sub-pixels SP3are also alternately aligned along the first direction X. The sub-pixels SP1and the sub-pixels SP2are alternately aligned along the second direction Y. The sub-pixels SP3are aligned along the second direction Y without interposing the sub-pixels SP1and SP2.

The dummy sub-pixels DS1have the same shape as that of the sub-pixels SP1, the dummy sub-pixels DS2have the same shape as that of the sub-pixels SP2, and the dummy sub-pixels DS3have the same shape as that of the sub-pixels SP3. The arrangement of the dummy sub-pixels DS1, DS2and DS3in each dummy pixel DP is the same as that of the sub-pixels SP1, SP2and SP3in each pixel PX. The shape and arrangement of the dummy sub-pixels DS1, DS2and DS3may be different from the shape and arrangement of the sub-pixels SP1, SP2and SP3.

Note that the outlines of the sub-pixels SP1, SP2and SP3and the dummy sub-pixels DS1, DS2and DS3shown inFIG. 2correspond to the outlines of the pixel electrodes or the light-emitting area of the display device, but they are shown in a simplified form and do not necessarily reflect the actual shape.

FIG. 3is a schematic cross-sectional view of the display device DSP taken along line inFIG. 2. The display device DSP comprises an insulating layer11(first insulating layer) disposed on the base10and an insulating layer12(second insulating layer) disposed on the insulating layer11. The pixel circuit1and other components shown inFIG. 1are disposed on the base10and covered by the insulating layer11, illustration of which is omitted. The insulating layers11and12are, for example, organic insulating layers. The insulating layer11may be referred to as an underlayer of the display element20. The insulating layer12is formed to partition the display element20or the sub-pixel SP, and may be referred to as ribs or partition walls.

As in the sub-pixel SP3shown inFIG. 3, the display element20of each sub-pixel SP comprises a pixel electrode PE1(first pixel electrode), an organic layer OR1(first organic layer) and a common electrode CE. The pixel electrode PE1is an electrode provided for each sub-pixel SP or each display element20, and may be referred to as an upper electrode or anode. The common electrode CE is an electrode commonly provided for a plurality of sub-pixels SP or a plurality of display elements20, and may be referred to as a counter electrode, upper electrode or cathode.

The pixel electrode PE1is disposed on the insulating layer11, and its peripheral portion is covered by the insulating layer12. The pixel electrode PE1is electrically connected to the drive transistor3shown inFIG. 1. The pixel electrode PE1is a transparent electrode formed of, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). Note that the pixel electrode PE1may also be a metal electrode formed of a metal material such as silver, aluminum or the like. Further, the pixel electrode PE1may be of a stacked body of transparent electrode and metal electrode. For example, the pixel electrode PE1may be configured as a stacked body in which a transparent electrode, a metal electrode and a transparent electrode are stacked in this order, or may be configured as a stacked body of three or more layers.

The insulating layer12comprises an opening OP superimposed on the pixel electrode PE1in each sub-pixel SP. The organic layer OR1is disposed on the insulating layer12and is in contact with the pixel electrode PE1through the opening OP.

FIG. 4is a cross-sectional view showing an example of a layer configuration that can be applied to the organic layer OR1. For example, the organic layer OR1includes a functional layer F1(first functional layer), a light-emitting layer EL and a functional layer F2(second functional layer), which are stacked in order from the pixel electrode PE1towards the common electrode CE. The functional layers F1and F2each are, for example, a hole injection layer, a hole transport layer, a hole blocking layer, an electron injection layer, an electron transport layer or an electron blocking layer, but may be other functional layers. Each of the functional layers F1and F2is not limited to a single layer, but as well be a stacked body in which multiple functional layers are stacked on one another. Further, at least one of the functional layers F1and F2may be omitted.

As shown inFIGS. 3 and 4, the common electrode CE covers the organic layer OR1. The common electrode CE is a transparent electrode formed of, for example, a transparent conductive material such as ITO or IZO. The common electrode CE may be covered by a transparent protective film (including at least one of an inorganic insulating film and an organic insulating film).

When the potential of the pixel electrode PE1is relatively higher than that of the common electrode CE, the pixel electrode PE1corresponds to the anode and the common electrode CE corresponds to the cathode. On the other hand, when the potential of the common electrode CE is relatively higher than that of the pixel electrode PE1, the common electrode CE corresponds to the anode and the pixel electrode PE1corresponds to the cathode.

For example, when the pixel electrode PE1corresponds to the anode, the functional layer F1includes at least one of the hole injection layer and the hole transport layer, and the functional layer F2includes at least one of the electron transport layer and the electron injection layer.

As in the dummy sub-pixels DS1and DS3shown inFIG. 3, the dummy sub-pixels DS each include a pixel electrode PE2(second pixel electrode) and an organic layer OR2(second organic layer). As in the case of the pixel electrode PE1, the pixel electrode PE2is disposed on the insulating layer11and is covered by the insulating layer12. The pixel electrode PE2is formed by the same process and of the same material as those of the pixel electrode PE1. As in the case of the organic layer OR1, the organic layer OR2is disposed on the insulating layer12and is covered by the common electrode CE. The organic layer OR2has the same structure as that of the organic layer OR1, and for example, it contains the light-emitting layer EL and the functional layers F1and F2.

In the example illustrated inFIG. 3, the insulating layer12does not comprise an opening in the dummy sub-pixels DS. Therefore the pixel electrode PE2and the organic layer OR2of each dummy sub-pixel DS oppose each other via the insulating layer12. In the dummy sub-pixels DS with such a configuration, even if a potential difference is created between the pixel electrode PE2and the common electrode CE, the organic layer OR2does not emit light.

The dummy sub-pixels DS may comprise a pixel circuit1similar to that of the sub-pixels SP. This pixel circuit1may or may not be connected to the pixel electrode PE2. When the dummy sub-pixel DS comprises the pixel circuit1, this pixel circuit1can protect the pixel circuit1of the sub-pixel SP from electrostatic discharge which may be generated in the manufacturing process of the display device DSP, etc.

Between the organic layers OR1disposed respectively on two adjacent sub-pixels SP, between the organic layer OR1disposed on a sub-pixels SP and the organic layer OR2disposed on a dummy sub-pixel DS adjacent to this sub-pixels SP and between the organic layers OR2disposed respectively on two adjacent dummy sub-pixels DS, partition walls PT are respectively provided. In the example illustrated inFIG. 3, a dummy sub-pixel is placed between two dummy sub-pixels. In the example shown inFIG. 3, a partition wall PT is placed on a right side of the dummy sub-pixel DS3as well. The partition walls PT each are, for example, an organic insulating layer.

In the following descriptions, the four partition walls PT shown inFIG. 3may be referred to respectively as a partition wall PT1(first partition wall), a partition wall PT2(second partition wall), a partition wall PT3(third partition wall) and a partition wall PT4(fourth partition wall) in order from left to right. The partition walls PT1, PT2, PT3and PT4are disposed on the insulating layer12.

Each partition wall PT has a forward tapered shape. The forward tapered shape means such a shape as shown in the partition wall PT1shown inFIG. 3that a width W1of an upper portion is less than a width W2of a lower portion. Each side surface of the partition walls PT may be a plane inclined to the third direction Z, or it may be a curved surface. The partition wall PT may be configured to include a plurality of portions whose widths decrease in steps from the lower portion toward the upper portion.

The organic layer OR1of the sub-pixel SP3is located between the partition wall PT1and the partition wall PT2. The organic layer OR2of the dummy sub-pixel DS1is located between the partition wall PT2and the partition wall PT3. The organic layer OR2of the dummy sub-pixel DS3is located between the partition wall PT3and the partition wall PT4.

The common electrode CE continuously covers the organic layers OR1, OR2and the partition walls PT1, PT2, PT3and PT4. The common electrode CE is formed entirely over the area including the sub-pixels SP and dummy sub-pixels DS, for example, by vapor deposition. In the following descriptions, the portion of the common electrode CE, which covers the organic layer OR1may be referred to as the first portion P1, the portion which covers the organic layer OR2as the second portion P2, the portion which covers the upper portion of the partition wall PT as the third portion P3, and the portion located on an outer side of the partition wall PT (partition wall PT4), which is located at an outermost end may be referred to as the fourth portion P4. In this embodiment, the first portion P1, the second portion P2, the third portion P3and the fourth portion P4are connected together.

The display device DSP further comprises a conductive layer CL1(first conductive layer) disposed between the insulating layers11and12, and a conductive layer CL2(second conductive layer) disposed between the base10and the insulating layer11. In the peripheral area SA, the insulating layer12comprises a contact hole CH1(first contact hole) and the insulating layer11comprises a contact hole CH2(second contact hole). For example, the conductive layer CL1is formed by the same process and of the same material as those of the pixel electrodes PE1and PE2.

The fourth portion P4of the common electrode CE is in contact with the conductive layer CL1via the contact hole CH1. The conductive layer CL1is in contact with the conductive layer CL2via the contact hole CH2. A common voltage is supplied to the conductive layer CL2. The common voltage is supplied to the entire common electrode CE via the conductive layer CL1.

In the example shown inFIG. 3, an organic layer OR3(third organic layer) is disposed between the partition wall PT4and the contact hole CH1. The organic layer OR3is disposed on the insulating layer12and covered by the fourth portion P4. For example, in the organic layers OR1and OR2, the light-emitting layers EL are each formed separately for the respective color of the sub-pixel SP and dummy sub-pixel DS. On the other hand, at least some of the layers contained in the functional layers F1and F2described above are formed at the same time entirely for the area including the sub-pixels SP and the dummy sub-pixels DS. For example, the organic layer OR3is a part where the layer (common layer) formed at the same time for each sub-pixel SP and each dummy sub-pixel DS as just mentioned, is divided by the partition wall PT4. In this case, the organic layer OR3may not necessarily contain the light-emitting layer EL.

The organic layer OR1of the sub-pixel SP3includes a first end portion E1on a side of the partition wall PT1and a second end portion E2on a side of the partition wall PT2. The first end portion E1and the second end portion E2are located above the insulating layer12.

FIG. 5is an enlarged schematic cross-sectional view showing the vicinity of the second end portion E2. The partition wall PT2includes an upper surface SF1and a side surface SF2. The second end portion E2is in contact with the side surface SF2.

In the example shown inFIG. 5, end portions of the light-emitting layer EL and the functional layers F1and F2are in contact with the side surface SF2. The common electrode CE continuously covers the functional layer F2, the side surface SF2and the upper surface SF1. The common electrode CE is not in contact with the light-emitting layer EL and the functional layer F1.

Note that at least part of the layers which constitute the organic layer OR1may be disposed on the upper surface SF1while the part being separated from the second end portion E2. For example, when the light-emitting layer EL and the functional layers F1and F2are formed in the area overlapping the partition wall PT2, part of the light-emitting layer EL and the functional layers F1and F2can be placed between the upper surface SF1and the common electrode CE. If the inclination of the side surface SF2is steep, such part is divided from the light-emitting layer EL and the functional layers F1and F2formed near the partition wall PT2.

The relationship between the first end portion E1and the partition wall PT1is similar to the relationship between the second end portion E2and the partition wall PT2. In other words, the first end portion E1is in contact with a side surface of the partition wall PT1. Further, both end portions of the organic layer OR2of the dummy sub-pixel DS1shown inFIG. 3are in contact with the respective side surfaces of the partition walls PT2and PT3and both end portions of the organic layer OR2of the dummy sub-pixel DS3are in contact with the respective side surfaces of the partition walls PT3and PT4.

FIG. 6is a schematic plan view of the pixel electrodes PE1, PE2and the organic layers OR1, OR2and OR3. The pixel electrodes PE1are spaced apart from each of the sub-pixels SP1, SP2and SP3. The pixel electrodes PE1overlap the above-described openings OP, respectively. The pixel electrodes PE2are spaced apart from each of the dummy sub-pixels DS1, DS2and DS3.

The organic layers OR1overlaps the pixel electrodes PE1respectively in the sub-pixels SP1, SP2and SP3. In the example shown inFIG. 6, a continuous organic layer OR1is provided for a plurality of sub-pixels SP3aligned along the second direction Y.

The organic layers OR2overlap the pixel electrodes PE2, respectively, in the dummy sub-pixels DS1, DS2and DS3. In the example shown inFIG. 6, a continuous organic layer OR2is provided for a plurality of dummy sub-pixels DS3aligned along the second direction Y. The organic layer OR2of the dummy sub-pixel DS3located adjacent to a sub-pixel SP3along the second direction Y is connected to the organic layer OR1of the sub-pixel SP3.

The organic layer OR3includes a portion extending along the first direction X and a portion extending along the second direction Y. For example, the organic layer OR3is formed in a ring shape in the peripheral area SA. The dummy sub-pixels DS1, DS2and DS3are located between the display area DA and the organic layer OR3.

FIG. 7is a schematic plan view of the partition walls PT, a common electrode CE and conductive layers CL1and CL2. The partition walls PT includes partition walls PTx extending along the first direction X and partition walls PTy extending along the second direction Y. The partition walls PT1, PT2, PT3and PT4shown inFIG. 3are all partition walls PTy.

The partition walls PTx and PTy are disposed between two adjacent sub-pixels SP, between two adjacent dummy sub-pixels DS and between adjacent pairs of respective sub-pixels SP and respective dummy sub-pixels DS, and are formed into a grid pattern as a whole. Note that the partition walls PTx may not be provided between two sub-pixels SP3aligned along the second direction Y, between two dummy sub-pixels DS3aligned along the second direction Y, and between adjacent pairs of respective sub-pixels SP3and respective dummy sub-pixels DS3aligned along the second direction Y.

For example, the conductive layers CL1and CL2are formed into a ring shape in the peripheral area SA. The dummy sub-pixels DS1, DS2and DS3are located between the display area DA and the conductive layers CL1and CL2.

In the example shown inFIG. 7, a large number of contact holes CH1and CH2are formed around the dummy sub-pixels DS1, DS2and DS3. The contact holes CH1are located closer to the side of the display area DA than the contact holes CH2. As another example, the contact holes CH1may have an elongated shape in which a plurality of contact holes CH1aligned along the first direction X or those aligned along the second direction Y inFIG. 7are connected together into one. Similarly, the contact holes CH2may have an elongated shape in which a plurality of contact holes CH2aligned along the first direction X or those aligned along the second direction Y inFIG. 7are connected together into one.

As indicated by the dashed lines inFIG. 7, the common electrode CE is disposed in the area including the sub-pixels SP1, SP2and SP3and the dummy sub-pixels DS1, DS2and DS3. An edge of the common electrode CE is located between the contact holes CH1and CH2.

FIG. 3shows the cross-sectional structure of the sub-pixels SP3and the dummy sub-pixels DS1and DS3along the first direction X. The cross-sectional structure of the sub-pixels SP1and SP2along the first direction X is also similar to that of the sub-pixel SP3, and the cross-sectional structure of the dummy sub-pixel DS2along the first direction X is also similar to that of the dummy sub-pixel DS1. Further, the cross-sectional structure of the sub-pixels SP1, SP2, and SP3along the second direction Y is similar to that of the sub-pixel SP3inFIG. 3, and the cross-sectional structure of the dummy sub-pixels DS1, DS2, and DS3along the second direction Y is similar to that of the dummy sub-pixels DS1and DS3inFIG. 3.

Of the elements disposed in the sub-pixels SP in the display area DA, for example, the pixel electrodes PE1are patterned by etching. When multiple elements are formed at the same time by etching, the outermost circumferential ones of these elements may be excessively eroded. Therefore, if there is no conductive layer similar to the pixel electrodes PE1on an outer side of the outermost pixel electrodes PE1in the display area DA, the pixels PX including the outermost pixel electrodes PE1cannot be formed to have a configuration as designed, and the display quality may be degraded.

In contrast, in this embodiment, the dummy pixels DP including the pixel electrodes PE2are disposed on an outer side of the outermost pixels PX in the display area DA. With this structure, excessive erosion of the pixel electrodes PE1of the outermost pixels PX does not easily occur, and as a result, the display quality of the display device DSP can be improved.

Further, in this embodiment, the partition walls PT are placed at boundaries of the sub-pixels SP and dummy sub-pixels SP, and the end portions of the organic layers OR1are respectively brought into contact with the side surfaces of the partition walls PT. One of the advantageous effects of this configuration will be explained below.

FIG. 8is a schematic cross-sectional view of a display device of a comparative example with respect to this embodiment, showing the vicinity of the end portion E of the organic layer OR1as inFIG. 5. The comparative example is different from the structure inFIG. 5in that partition walls PT are not provided. The second end portion E2is located above the insulating layer12and is covered by the common electrode CE.

In the comparative example, the light-emitting layer EL and the functional layer F1are in contact with the common electrode CE at the end portion E. Therefore, unlike the original current path through the functional layer F1, the light-emitting layer EL and the functional layer F2, a leak path LP is formed that directly connects the functional layer F1and the light-emitting layer EL to the common electrode CE. The leak path LP thus formed can cause a degradation in display quality and an increase in power consumption.

In particular, when a single mask is used to form each layer of the organic layer OR1, the material of each layer is also deposited at an edges of the opening of the mask; therefore the later the layer is formed, the slightly smaller, the size becomes. Thus, as shown inFIG. 8, the end portion E is inclined and the contact area between each layer of the organic layer OR1and the common electrode CE increases, which makes the formation of the leak path LP easy.

In contrast, when the end portion of the organic layer OR1is in contact with the side surface of each partition wall PT as in this embodiment, the light-emitting layer EL and the functional layer F1are not easily exposed from the functional layer F2. Therefore, the formation of the leakage path is suppressed, which makes it possible to improve the display quality of the display device DSP and to reduce the power consumption.

Apart from the above, various other advantageous effects can be obtained from this embodiment.

Second Embodiment

The second embodiment will now be described. Note that the configuration not specifically referred to here is similar to that of the first embodiment.

FIG. 9is a schematic cross-sectional view of an example of a display device DSP of this embodiment.FIG. 10is a schematic cross-sectional view of another example of the display device DSP according to this embodiment. In these figures, the common electrode CE comprises a first layer L1and a second layer L2. The first layer L1and the second layer L2are formed of, for example, a transparent conductive material such as ITO or IZO.

The first layer L1covers organic layers OR1, OR2, OR3, partition walls PT1, PT2, PT3, PT4and an insulating layer12around a contact hole CH1. The second layer L2covers the first layer L1. In this embodiment, a first portion P1, a second portion P2, a third portion P3and a fourth portion P4of the common electrode CE each include the first layer L1and the second layer L2.

In the example shown inFIG. 9, the first layer L1in the first portion P1, the second portion P2, the third portion P3and the fourth portion P4are continuously connected. Further, the second layer L2is continuously provided in the first portion P1, the second portion P2, the third portion P3and the fourth portion P4.

In the example shown inFIG. 10, the first layer L1in the first portion P1is separated from the first layer L1in the third portion P3, the first layer L1in the second portion P2is separated from the first layer L1in the third portion P3, and the first layer L1in the fourth portion P4is separated from the first layer L1in the third portion P3. On the other hand, the second layer L2is continuously provided in the first portion P1, second portion P2, third portion P3and fourth portion P4.

When the common electrode CE is thin, there is a possibility that the common electrode CE may break due to the steps formed by the partition wall PT and the opening OP as in the case of the first layer L1inFIG. 10. On the other hand, due to limitations of the manufacturing equipment, it may not be possible to make the transparent conductive layer, which is a single layer, sufficiently thick. However, as in this embodiment, when the common electrode CE is formed of two layers, the continuity of the entire common electrode CE can be maintained just in case where one layer is broken as in the example shown inFIG. 10by the other layer connected.

FIG. 11is a schematic cross-sectional view of still another example of the display device DSP of this embodiment. In the example illustrated in this figure, the first layer L1is formed in the display area DA, but not in the peripheral area SA. The second layer L2is formed in both the display area DA and the peripheral area SA.

With this configuration, the first portion P1and the third portion P3above the partition wall PT1include both the first layer L1and the second layer L2, but the second portion P2, the fourth portion P4and the third portion P3above the partition walls PT2, PT3and PT4contain the second layer L2and do not contain the first layer L1. In this configuration, the thickness of the first portion P1is greater than the thickness of the second portion P2.

When no opening OP is provided in the dummy sub-pixel DS, there are fewer stepped portions in the peripheral area SA, which makes the common electrode CE less breakable. Therefore, even in a configuration where the common electrode CE is multilayered in the display area DA and not multilayered in the peripheral area SA as in the example shown inFIG. 11, a sufficient effect of improving the conductivity of the common electrode CE can be obtained.

Third Embodiment

The third embodiment will now be described. The configuration that is not specifically referred to here is similar to that of the first embodiment.

FIG. 12is a schematic cross-sectional view of a display device DSP of this embodiment. In this embodiment, a power feed line FL is disposed on each partition wall PT. The power feed line FL is formed of a metal material. In the following descriptions, the four power feed lines FL shown inFIG. 12may be referred to as a power feed line FL1(first power feed line), a power feed line FL2(second power feed line), a power feed line FL3(third power feed line) and a power feed lines FLs, in order from left to right.

The power feed line FL1is disposed above the partition wall PT1. The power feed line FL2is disposed above the partition wall PT2. The power supply line FL3is disposed on the partition wall PT3. The power feed line FLs is located on the partition wall PT4. The power feed line FLs is wider than the power feed lines FL1, FL2and FL3and overlaps the contact hole CH1.

In the example shown inFIG. 12, the common electrode CE is divided by the partition walls PT1, PT2, PT3and PT4. More specifically, the first portion P1, the second portion P2, the third portion P3and the fourth portion P4of the common electrode CE are separated from each other.

The power supply line FL1is in contact with two first portions P1located on respective sides of the partition wall PT1. The power feed line FL2is in contact with the first portion P1and the second portion P2located on respective sides of the partition wall PT2. The power feed line FL3is in contact with two second portions P2located on respective sides of the partition wall PT3. The power feed line FLs is in contact with the second portion P2and the fourth portion P4located on respective sides of the partition wall PT4. The third portion P3is located between the partition wall PT1and the power feed line FL1, between the partition wall PT2and the power feed line FL2, between the partition wall PT3and the power feed line FL3, and between the partition wall PT4and the power feed line FLs.

FIG. 13is a schematic plan view of the partition walls PT, the power feed lines FL, the common electrode CE and the conductive layers CL1and CL2. The shapes of the partition walls PT, the common electrode CE and the conductive layers CL1, CL2are similar to those of the example shown inFIG. 7.

The power feed lines FL include power feed lines FLx extending along the first direction X and power feed lines FLy extending along the second direction Y. The power feed line FLx are respectively disposed above the partition walls PTx, and the power feed lines FLy are respectively disposed above the partition walls PTy. The power feed lines FL1, FL2and FL3shown inFIG. 12are all power feed lines FLy. The power feed lines FLs are formed into a ring shape in the peripheral area SA. The end portions of the power feed lines FLx and FLy are connected to the power feed lines FLs.

Thus, in this embodiment, the metal-made power feed lines FLs are disposed in the area including the sub-pixels SP and the dummy sub-pixels DS. With this configuration, it possible to reduce the resistance of the common electrode CE. Further, even if the common electrode CE is divided at the locations of the partition walls PT as in the example shown inFIG. 12, the common voltage can be well supplied to the display element20of each sub-pixel SP by connecting the divided portions by the power feed lines FL.

In each of the above embodiments, the layout and configuration of the pixels PX and dummy pixels DP are not limited to those shown inFIGS. 1 and 2. For example, in each pixel PX, the sub-pixels SP (SP1, SP2and SP3) of the same shape may be aligned along the first direction X. Similarly, in each dummy pixel DP, the dummy sub-pixels DS (DS1, DS2and DS3) of the same shape may be aligned along the first direction X. InFIGS. 1 and 2, dummy pixels DP are arranged only one circumference around the display area DA, but they may be arranged two or more times.

Note thatFIGS. 9, 10 and 11each illustrate a case where the common electrode CE is formed of two layers, but the common electrode CE may be formed of three or more layers. If a single layer can be made thick, the common electrode CE may be formed thick, not from multiple layers.

In the configurations shown inFIGS. 3, 9, 10 and 11, the power feed lines FL shown inFIGS. 12 and 13may be provided.

The second portions P2disposed in the dummy sub-pixels DS may not be connected to the third portions P3or the power supply lines FL, respectively. In this case, the second portions P2may be floating.

In the configuration shown inFIG. 10, each of the third portion P3may not include the first layer L1. Further, in the configuration shown inFIG. 11, the third portion P3above the partition wall PT1may not include the first layer L1. Further, in the configuration shown inFIG. 12, the third portion P3may not be disposed between each partition wall PT and each respective power feed line FL.

Based on the display device which has been described in the above-described embodiments, a person having ordinary skill in the art may achieve a display device with an arbitral design change; however, as long as they fall within the scope and spirit of the present invention, such a display device shall be encompassed by the scope of the present invention.

A skilled person would conceive various changes and modifications of the present invention within the scope of the technical concept of the invention, and naturally, such changes and modifications are encompassed by the scope of the present invention. For example, if a skilled person adds/deletes/alters a structural element or design to/from/in the above-described embodiments, or adds/deletes/alters a step or a condition to/from/in the above-described embodiment, as long as they fall within the scope and spirit of the present invention, such addition, deletion, and altercation are encompassed by the scope of the present invention.

Further, regarding the present embodiments, any advantage and effect those will be obvious from the description of the specification or arbitrarily conceived by a skilled person are naturally considered achievable by the present invention.