Method for multi-level etch, semiconductor sensing device, and method for manufacturing semiconductor sensing device

Present disclosure provides a method for multi-level etch. The method includes providing a substrate, forming a first reference feature over a control region of the substrate, forming an etchable layer over the first reference feature and a target region over the substrate, patterning a masking layer over the etchable layer, the masking layer having a first opening projecting over the control region and a second opening projecting over the target region, and removing a portion of the etchable layer through the first opening and the second opening until the first reference feature is reached. A semiconductor sensing device manufactured by the multi-level etch is also disclosed.

BACKGROUND

1. Technical Field

Present disclosure is related to a method for multi-level etch, a semiconductor sensing device, and a method for manufacturing the semiconductor sensing device by applying the multi-level etch. Particularly, to a multi-level etch employing a reference feature.

2. Description of the Related Art

Dry etching and wet etching operations are often used during the course of semiconductor structure manufacturing. Etchable material is removed to expose another material selective to the etching chemistry. Character of dry etching operation includes providing a controllable dimension of material removal, however, due to high energy atom/molecular bombardment, surface of the exposed material may be damaged in a macroscopic or even a microscopic level. When the material to be exposed possesses a miniature dimension and/or is configured as crucial carrier channel, structural defects may deteriorate the electrical performance thereof.

Wet etching operation, on the other hand, provides a milder approach to remove etchable material and expose another material selective to the etching chemistry, however, due to the isotropic nature of the wet etching operation, dimension of the material to be removed is less controllable than exploiting dry etching operation. In other words, process variation in a wet etch operation is expected to be greater than that of the dry etching operation. Similarly, when the material to be exposed possesses a miniature dimension and/or is configured as crucial carrier channel, such process variation may contribute to device performance variations.

A method for multi-level etch, combining the advantages of the dry etching and wet etching operation, is thus required when the etching operation involves the exposure of miniature dimension structure and/or crucial carrier channel structure.

SUMMARY

In some embodiments, the present disclosure provides a method for multi-level etch. The method includes providing a substrate, forming a first reference feature over a control region of the substrate, forming an etchable layer over the first reference feature and a target region over the substrate, patterning a masking layer over the etchable layer, the masking layer having a first opening projecting over the control region and a second opening projecting over the target region, and removing a portion of the etchable layer through the first opening and the second opening until the first reference feature is reached.

In some embodiments, the present disclosure provides a method for manufacturing a semiconductor sensing device. The method includes providing a substrate, forming a reference feature over a control region of the substrate, forming a sensing feature over a target region of the substrate, forming an etchable layer over the control region and the target region of the substrate, patterning a masking layer over the etchable layer. The masking layer has a first opening projecting over the reference feature and a second opening projecting over the sensing feature; and removing a portion of the etchable layer through the first opening and the second opening until the reference feature is reached.

In some embodiments, the present disclosure provides a semiconductor sensing device. The device includes a substrate having a sensing region. The sensing region includes an active feature having an anchor portion on a top surface of the substrate, an elevated portion spaced from the top surface of the substrate by a vertical distance and connected to the anchor portion, and a nanowire portion on the top surface of the substrate and connected to the anchor portion. The vertical distance is greater than or equal to a thickness of the nanowire portion.

DETAILED DESCRIPTION

Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are specified with respect to a certain component or group of components, or a certain plane of a component or group of components, for the orientation of the component(s) as shown in the associated figure. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such arrangement.

Present disclosure provides a method for multi-level etch by implementing a dry etching and a wet etching operation on a material stack structure. Such multi-level etch provides sufficient control over the dimension of material removal, and simultaneously reduce the damage caused to the surface of the materials to be exposed.

Present disclosure provides a semiconductor sensing device manufactured by the multi-level etch and possessing a reference feature in a material stack structure.

Present disclosure provides a method for manufacturing the semiconductor sensing device by implementing a dry etching and a wet etching operation on a material stack structure including at least a reference feature. Such multi-level etch provides sufficient control over the dimension of material removal, and simultaneously reduce the damage caused to a channel structure to be exposed.

FIG. 1Ais a cross sectional view of a structure during an intermediate stage of a multi-level etch, in accordance to some embodiments of the present disclosure. In some embodiments, the structure inFIG. 1Ais a semiconductor structure including a semiconductor substrate101, an etchable layer105, and a masking layer107. The semiconductor substrate101includes at least a control region101A configured as a control pivot in an etching operation implemented for a target feature103′ in a target region101B of the semiconductor substrate101. InFIG. 1A, means for controlling the etching operation includes a reference feature103in the control region101A. The reference feature103may possess a predetermined height H1. A first opening107A in the masking layer107is projected over the control region101A and the reference feature103. A second opening107B in the masking layer107is projected over the target region101B and the target feature103′. The first opening107A and the second opening107B may be wider or narrower than a width of the reference feature103and the target feature103′, respectively, as long as a portion of the reference feature103and the target feature103′ is partially overlapped with the first opening107A and the second opening107B. When a portion of the etchable layer105is being removed through the first opening107A and the second opening107B in a single etching operation, a top surface of the reference feature103is reached prior to a top surface of the target feature103′ being reached. Materials of the reference feature103can be different from that of the etchable layer105, therefore, a material-sensitive indication can be obtained when the etching level approaches the top surface of the reference feature103. Alternatively stated, an indication of a suitable form, for example, color of the plasma, or real-time mass spectroscopy, can be obtained when a reference level105A over the control region101A is reached during the etching operation, and at the meantime, a control level105B over the target region101B is reached correspondingly. After receiving this indication, the etching operation may be altered, for example, terminating the etching operation or changing the etching chemistry or conditions in consideration of the target feature103′ under the control level105B. As shown inFIG. 1A, the reference level105A possesses an etch depth H105A measured from a top surface of the etchable layer105, and the control level105B possesses an etch depth H105B measured from the top surface of the etchable layer105.

FIG. 1AAis a cross sectional view of a structure during an intermediate stage of a multi-level etch, in accordance to some embodiments of the present disclosure. As shown inFIG. 1AandFIG. 1AA, position of the control level105B can be determined by the height H1of the reference feature103, the width W1of the first opening107A, and/or the width W2of the second opening107B. InFIG. 1A, the width W1is wider than the width W2, under the single etching operation, for example, a plasma-containing etch, an anisotropic etch, or a dry etch, the reference level105A shall be lower than the control level105B. InFIG. 1AA, the width W1is narrower than the width W2, under the single etching operation, for example, a plasma-containing etch, an anisotropic etch, or a dry etch, the reference level105A shall be higher than the control level105B.

In some embodiments, the reference feature103can be composed of material different from the material of etchable layer105. In some embodiments, the target feature can be composed of material substantially identical or different from that of the reference feature. In some embodiments, the reference feature is composed of one or more materials, and the target feature is substantially identical to one of the one or more materials. In some embodiments, the target feature can be a connection structure connecting terminals at its respective ends in a semiconductor structure. In some embodiments, the target feature can be a semiconductor connection structure connecting conductive terminals at its respective ends in a semiconductor structure. In some embodiments, the target feature can be a semiconductor nanowire connecting a source and a drain at its respective ends in a semiconductor sensing device.

FIG. 1AA′ is a cross sectional view of a structure during an intermediate stage of a multi-level etch, in accordance to some embodiments of the present disclosure.FIG. 1AA′ can be an etching operation subsequent to that inFIG. 1AA. When the reference level105A is reached inFIG. 1AA, the etching condition may change from, for example, an etch with more anisotropic weight toward an etch with less anisotropic, and more isotropic, weight. A compartment105A′ and a compartment1053can be obtained through the etch with less anisotropic weight from the reference level105A and the control level105B, respectively. The compartment105A′ and/or the compartment1053can have a wider lateral width than the opening at the reference level105A. The compartment105A′ and/or the compartment1053can have a non-vertical sidewall. The compartment105A′ and/or the compartment1053can have a curved sidewall.

FIG. 1Bis a cross sectional view of a structure during an intermediate stage of a multi-level etch, in accordance to some embodiments of the present disclosure. The reference feature103in the control region101A of the substrate101is composed of a core portion103A and a cap portion103B over a top surface and sidewalls of the core portion103A. The core portion103A may be a discrete pattern locally residing in the control region101A. The core portion103A can be composed of insulated materials such as oxides or nitrides. The cap portion103B extends from the reference region101A to the target region101B, and forming the target feature103′ in the target region101B. In some embodiments, the cap portion103B and the target feature103′ are composed of same material, for example, polysilicon or other semi conductive materials.FIG. 1Balso shows an opening107C in the masking layer107over another target region101C in the substrate101. The opening107C allows a portion of the etchable layer105to be removed during the single etching operation implemented with respect to the openings107A,107B, and107C. A control level105C rendered by the opening107C can be obtained over the target region101C when the reference level105A being reached. As shown inFIG. 1B, the width W3of the opening107C is narrower than the width W1of the opening107A, therefore, under the single etching operation, for example, a plasma-containing etch, an anisotropic etch, or a dry etch, the reference level105A shall be lower than the control level105C.

FIG. 1Cis a cross sectional view of a structure during an intermediate stage of a multi-level etch, in accordance to some embodiments of the present disclosure. The reference feature103and the target feature103′ inFIG. 1Cmay be a continuous layer extending over the reference region101A and the target region101B. The opening107A in the masking layer107is one wide opening with a width W1. The opening107B in the masking layer107includes a plurality of narrow openings, for instance, one of the plurality of narrow openings may have a width W2, the width W2being narrower than the width W1. Under the single etching operation, for example, a plasma-containing etch, an anisotropic etch, or a dry etch, the reference level105A shall be lower than the control level105B when the top surface of the reference feature103is reached. InFIG. 1C, even if the reference feature103and the target feature103′ share a same height H1, multi-level etch can still be obtained by having different width arrangements at the opening107A over the control region101A and the opening107B over the target region101B.

FIG. 2A,FIG. 2B,FIG. 2C,FIG. 2D,FIG. 2E, andFIG. 2E′ (an optional operation) are cross sectional views of a structure inFIG. 1Aduring various intermediate stages of a multi-level etch, in accordance to some embodiments of the present disclosure. InFIG. 2A, a substrate101is provided. A reference feature103is formed over a control region101A of the substrate101inFIG. 2B. In some embodiments, the reference feature103can be a discrete pattern composed of insulated materials such as oxide or nitride. Subsequently, a target feature103′ is formed over a target region101B of the substrate101, followed by the formation of an etchable layer105, such as a dielectric layer, covering the reference feature103and the target feature103′, as shown inFIG. 2C. InFIG. 2D, a masking layer107is formed over the top surface of the etchable layer105, and then an opening107A over the reference region101A and an opening107B over the target region101B are patterned in the masking layer107. InFIG. 2E, a multi-level etch operation, for example, a plasma-containing etch, an anisotropic etch, or a dry etch, is performed through the openings107A and107B, until the top surface of the reference feature103, or the reference level105A is reached. Meanwhile, the control level105B over the target region101B is reached correspondingly. Depending on the widths of the openings107A,107D, as well as the height of the reference feature103, the control level105B can be pre-designed to be higher or lower than the reference level105A.FIG. 2E′ can be an optional operation associated with re-patterning the masking layer107inFIG. 2Eto form a re-patterned masking layer107′ in order to alter the widths of the openings107A,107B for subsequent operations. Related discussion can be further found inFIG. 5of the present disclosure.

FIG. 3is a cross sectional view of a structure during an intermediate stage of a multi-level etch, in accordance to some embodiments of the present disclosure. In addition to the reference feature103,FIG. 3shows another reference feature103″ over a control region101D of the substrate101, configured as a second control pivot of the multi-level etch. The reference feature103″ may have a height H2different from the height H1of the reference feature103.FIG. 3may be an etching operation subsequent to that shown inFIG. 1B. Similarly, materials of the reference feature103can be different from that of the etchable layer105, therefore, a material-sensitive indication can be obtained when the etching level approaches the top surface of the reference feature103″. Alternatively stated, an indication of a suitable form, for example, color of the plasma, or real-time mass spectroscopy, can be obtained when a reference level105D over the control region101D is reached during the etching operation, and at the meantime, a control level105B over the target region101B and a control level105C over the target region101C are reached correspondingly. After receiving this indication, the etching operation be altered, for example, terminating the etching operation or changing the etching chemistry or conditions in consideration of the target feature (not shown inFIG. 3) under the control level105B and control level105C.

FIG. 4is a cross sectional view of a structure during an intermediate stage of a multi-level etch, in accordance to some embodiments of the present disclosure.FIG. 4can be an etching operation subsequent to that inFIG. 3. When the reference level105A and the reference label105D are reached inFIG. 3, the etching condition may change from, for example, an etch with more anisotropic weight toward an etch with less anisotropic, and more isotropic, weight. A compartment105A′, a compartment105D′, a compartment105B′, and a compartment105C′ can be obtained through the etch with less anisotropic weight from the reference levels105A,105D, and the control levels105B,105C, respectively. The compartments105A′ to105D′ can have a wider lateral width than the opening at the reference levels105A,105D and/or at the control levels105B,105C. The compartments105A′ to105D′ can have a non-vertical sidewall. The compartments105A′ to105D′ can have a curved sidewall.

FIG. 5is a cross sectional view of a structure during an intermediate stage of a multi-level etch, in accordance to some embodiments of the present disclosure.FIG. 5can be an etching operation subsequent to that inFIG. 3. Alternatively, the compartments105B′ to105D′ can have a narrower lateral width than the opening at the reference level105D and/or at the control levels105B,105C by re-patterning the masking layer107after the reference level105D being reached. For example, the masking layer107inFIG. 3may be removed after the reference level105D being reached, subsequently, another masking layer107′ inFIG. 5may be patterned over the top surface and etch trench sidewalls of the etchable layer105. As a result, the openings107B,107C,107D in the re-patterned masking layer107′ may possess different widths W2′, W3′, and W4′ compared to those inFIG. 3. As shown inFIG. 5, widths W2′, W3′, and W4′ are narrower than widths W2, W3, and W4inFIG. 3, and therefore, corresponding compartments105B′,105C′, and105D′ may possess narrower lateral width than the opening at the reference level105D and/or at the control levels105B,105C. In some embodiments, the compartments105A′ to105D′ can have a non-vertical sidewall. The compartments105A′ to105D′ can have a curved sidewall.

FIG. 6A,FIG. 6B,FIG. 6C,FIG. 6D,FIG. 6E,FIG. 6F,FIG. 6FA,FIG. 6FB,FIG. 6FC,FIG. 6FD,FIG. 6FE,FIG. 6FA′,FIG. 6FB′,FIG. 6FC′,FIG. 6FD′ are cross sectional views of a structure during various intermediate stages of a multi-level etch, in accordance to some embodiments of the present disclosure.FIG. 6FAtoFIG. 6FEare operations in one embodiment following operation inFIG. 6F.FIG. 6FA′ toFIG. 6FD′ are operations in another embodiment following operation inFIG. 6F. InFIG. 6A, a substrate101is provided. InFIG. 6C, a reference feature103over a control region101A of the substrate101is formed. Referring toFIG. 6BandFIG. 6C, the formation of the reference feature103includes forming a core portion103A of the reference feature103, followed by forming a cap portion103B of the reference feature103. In some embodiments, regions between the control region101A is the target region101B. As shown inFIG. 6C, formation of the cap portion103B in the control region101A simultaneously forms a sensing feature in the target region101B, as the cap portion103B extends from the control region101A to the target region101B. In some embodiments, the cap portion103B is composed of semi conductive materials, or subsequently in the following operation, an active layer configured for carrier transport. InFIG. 6D, a first masking layer105′ is patterned over the reference feature103to separate a portion of the reference feature103from another portion. For example, an active portion600of the reference feature103is electrically separated from a signal enhancement portion601of the reference feature103, as shown inFIG. 6DandFIG. 6E. An etchable layer105, for example, a dielectric layer, is conformably formed over the patterned reference feature103. The etchable layer105may be deposited by a chemical vapor deposition operation, carry the underlying morphology of the patterned reference feature103at the top surface of said etchable layer105, as shown inFIG. 6F. The etchable layer105may be formed by a spin-on operation using flowable materials such as boro-phospho-silicate-glass (BPSG) or phospho-silicate-glass (PSG) to obtain a planarized surface, as shown inFIG. 6FA.

InFIG. 6FA, when a planarization operation, for example, a chemical mechanical polishing (CMP), is performed on the etchable layer105carrying the underlying morphology of the patterned reference feature103, or when the flowable materials are utilized as the etchable layer105, a substantially planarized surface of the etchable layer105can be obtained. InFIG. 6FB, an opening107A in a masking layer107is patterned over the signal enhancement portion601, and an opening107B in the masking layer107is patterned over the active portion600of the reference feature103. InFIG. 6FC, an etching operation, for example, a plasma-containing etch, an anisotropic etch, or a dry etch, is performed through the openings107A,107B, until the top surface of the reference feature103is reached. At the meantime, the sensing feature in the target region101B is still covered by the etchable layer105. The signal enhancement portion601of the reference feature103may enhance the material-sensitive signal in order to indicate the active portion600of the reference feature103is reached. InFIG. 6FD, the etching condition may change from, for example, an etch with more anisotropic weight toward an etch with less anisotropic, and more isotropic, weight, to fulfill a delicate or mild etching condition of the sensing feature in the target region101B. InFIG. 6FE, the masking layer107is subsequently removed.

InFIG. 6FA′, when a planarization operation is omitted, a morphology of the patterned reference feature103is carried to the top surface of the etchable layer105. A masking layer107with an opening107A over the signal enhancement portion601and an opening107B over the active portion600is formed over the etchable layer105. InFIG. 6FB′, an etching operation, for example, a plasma-containing etch, an anisotropic etch, or a dry etch, is performed through the openings107A,107B, until the top surface of the reference feature103is reached. At the meantime, the sensing feature in the target region101B is still covered by the etchable layer105. Difference betweenFIG. 6FB′ andFIG. 6FClies in that, the top surface of the portion of the etchable layer105directly over the sensing feature is lower than the top surface of the portion of the etchable layer105directly over the reference feature103, thereby after the etching operation ofFIG. 6FB′, remaining dielectric material over the sensing feature inFIG. 6FB′ is thinner than that inFIG. 6FC. Description regardingFIG. 6FC′ andFIG. 6FD′ can be referred to previously providedFIG. 6FDandFIG. 6FE.

FIG. 7Ais a top view of a layout of several masking layers, in accordance to some embodiments of the present disclosure. The masking layer701may be utilized to pattern the core portion103A of the reference feature103. The masking layer702may be utilized to pattern the cap portion103B of the reference feature103.FIG. 7BandFIG. 7Care cross sectional views of a semiconductor sensing device during an intermediate manufacturing stage utilizing the masking layers ofFIG. 7A.FIG. 7BandFIG. 7Ccorrespond to the semiconductor sensing device dissecting along line AA and line BB, respectively, ofFIG. 7A, in accordance to some embodiments of the present disclosure. Referring toFIG. 7AandFIG. 7B, on the left end ofFIG. 7B, line AA runs along a principal dimension103A1and the body of the core portion103A, therefore an extended and continuous insulated stripe is shown inFIG. 7B. The masking layer702patterns the cap portion103B to expose a center portion of the insulated stripe. Referring toFIG. 7AandFIG. 7B, on the right end ofFIG. 7B, the masking layer702covers and extends beyond boundaries of the masking layer701, therefore the core portion103AA is covered by the cap portion103BB. Referring toFIG. 7AandFIG. 7C, on the left end ofFIG. 7C, line BB runs along a principal dimension103A1and deviated from the body of the core portion103A, therefore two discrete insulated blocks are shown inFIG. 7C. The masking layer702patterns the cap portion103B so that the cap portion103B covers the discrete insulated blocks. Referring toFIG. 7AandFIG. 7C, on the right end ofFIG. 7C, only the cap portion103BB is passed by line BB, therefore only a cap portion103BB is shown on the right end ofFIG. 7C. In some embodiments, as shown inFIG. 7B, the reference feature103is formed both in the control region (e.g., the region covered by the cap portion103B and103BB) and the target region (e.g., the region occupied by the core portion103A not covered by the cap portion103B) on the substrate.

FIG. 7A′ is a top view of a semiconductor sensing device, in accordance to some embodiments of the present disclosure. After patterning the core portion103A and the cap portion103B of the reference feature103as shown inFIG. 7A,FIG. 7B, andFIG. 7C, the core portion103A in the sensing region is at least partially removed, an active feature of the sensing device is then obtained.FIG. 7B′ andFIG. 7C′ correspond to the semiconductor sensing device dissecting along line AA′ and line BB′, respectively, ofFIG. 7A′. A portion of the etchable layer105is removed to form an etch level proximal to the reference feature103inFIG. 7B, followed by a selective etch to remove the core portion103A or the insulated pattern, as well as the remaining etchable layer over the reference feature103. The selective etch demonstrates a greater selectivity on the core portion103A than the cap portion103B. For example, the selective etch is configured to remove oxide or nitride in a greater speed than to remove polysilicon. Referring toFIG. 7A′ andFIG. 7B′, line AA′ runs along a principal dimension103A1and the body of the core portion103A, which is partially removed after the selective etch operation. Shaded area inFIG. 7A′ exemplifies the partially removed region of the core portion103A. Referring toFIG. 7A′ andFIG. 7C′, line BB′ runs along a principal dimension103A1and deviated from the body of the core portion103A, which may be remained after the selective etch operation. As shown inFIG. 7C′, two discrete insulated patterns remained are covered by the cap portion103B and connected by a nanowire110.

The active feature inFIG. 7B′ shows an anchor portion103AN on a top surface101T of the substrate101and an elevated portion103EL, which is positioned at an elevated level with respect to the anchor portion103AN, connected to the anchor portion103AN. The elevated portion103EL has a bottom surface spaced from the top surface101T by a vertical distance H′. ComparingFIG. 7BandFIG. 7B′, the space under the elevated portion103EL is originally filled with the core portion103A or the insulated pattern. The anchor portion103AN may possess a thickness TAN substantially identical to a thickness TEL of the elevated portion103EL, depending on the thickness uniformity at the formation of the cap portion103B.

The active feature inFIG. 7C′ shows two anchor portions103AN immediately surrounding the elevated portion103EL. A nanowire portion103NW connecting two adjacent anchor portions103AN at its respective ends. In some embodiments, the nanowire portion103NW includes one or more nanowires110. Each of the nanowires110may have a thickness TNW that is smaller than or equal to the vertical distance H′ of the corresponding elevated portion103EL. The elevated portion103EL corresponds to the nanowire110when they form a physical or electrical integrated body. The anchor portion103AN, the elevated portion103EL, and the nanowire portion103NW may be composed of identical active material such as polysilicon. When the anchor portion103AN and the elevated portion103EL are configured as a source or drain, and the nanowire portion103NW is configured as a channel of the sensing device, the anchor portion103AN and the elevated portion103EL may be composed of doped polysilicon while the nanowire portion103NW may be composed of undoped polysilicon. One of the anchor portion103AN and the elevated portion103EL of the active feature may be further connected to an interconnect structure receiving an external bias or signal.

In some embodiments, a top surface103T2of the anchor portion103AN is at a level higher than a top surface110T of the nanowire portion103NW if the patterning of the cap portion103B consumes the cap portion103B at the sidewall of the core portion103A. In some embodiments, a top surface103T2of the anchor portion103AN is at a level substantially identical to a top surface110T of the nanowire portion103NW if the patterning of the cap portion103B does not consume the cap portion103B at the sidewall but only consume the cap portion103B at the top surface of the core portion103A.

FIG. 8Ais a top view of a layout of several masking layers, in accordance to some embodiments of the present disclosure. The masking layer801may be utilized to pattern the core portion103A of the reference feature103. The masking layer802may be utilized to pattern the cap portion103B of the reference feature103.FIG. 8BandFIG. 8Care cross sectional views of a semiconductor sensing device during an intermediate manufacturing stage utilizing the masking layers ofFIG. 8A.FIG. 8BandFIG. 8Ccorrespond to the semiconductor sensing device dissecting along line CC and line DD, respectively, ofFIG. 8A, in accordance to some embodiments of the present disclosure. Referring toFIG. 8AandFIG. 8B, on the left end ofFIG. 8B, line CC runs along a principal dimension103A1and the body of the core portion103A, therefore an extended and continuous insulated stripe is shown inFIG. 8B. The masking layer802patterns the cap portion103B to expose a center portion of the insulated stripe. Referring toFIG. 8AandFIG. 8B, on the right end ofFIG. 8B, the masking layer802covers and extends beyond boundaries of the masking layer801, therefore the core portion103AA is covered by the cap portion103BB. Referring toFIG. 8AandFIG. 8C, on the left end ofFIG. 8C, line DD runs along a principal dimension103A1and deviated from the body of the core portion103A, therefore an extended and continuous cap portion103B is shown inFIG. 8C. The masking layer802patterns the cap portion103B so that the portion of the cap portion103B covered by the masking layer802possesses a greater thickness than the portion exposed from the making layer802. InFIG. 8C, the portion of the cap portion103B exposed from the masking layer802is in contact with the vertical sidewall of the core portion103A and subsequently becoming a nanowire structure. Referring toFIG. 8AandFIG. 8C, on the right end ofFIG. 8C, only the cap portion103BB is passed by line DD, therefore only a cap portion103BB is shown on the right end ofFIG. 8C.

FIG. 8A′ is a top view of a semiconductor sensing device, in accordance to some embodiments of the present disclosure. After patterning the core portion103A and the cap portion103B of the reference feature103as shown inFIG. 8A,FIG. 8B, andFIG. 8C, the core portion103A in the sensing region is removed, an active feature of the sensing device is then obtained.FIG. 8B′ andFIG. 8C′ correspond to the semiconductor sensing device dissecting along line CC′ and line DD′, respectively, ofFIG. 8A′. A portion of the etchable layer105is removed to form an etch level proximal to the reference feature103inFIG. 8B, followed by a selective etch to remove the core portion103A or the insulated pattern, as well as the remaining etchable layer over the reference feature103. The selective etch demonstrates a greater selectivity on the core portion103A than the cap portion103B. For example, the selective etch is configured to remove oxide or nitride in a greater speed than to remove polysilicon. Referring toFIG. 8A′ andFIG. 8B′, line CC′ runs along a principal dimension103A1and the body of the core portion103A, which is removed after the selective etch operation. Shaded area inFIG. 8A′ exemplifies the removed region of the core portion103A. Referring toFIG. 8A′ andFIG. 8C′, line DD′ runs along a principal dimension103A1and deviated from the body of the core portion103A. As shown inFIG. 8C′, a continuous cap portion103B is disposed on the top surface101T of the substrate101.

The active feature inFIG. 8B′ shows an anchor portion103AN on a top surface101T of the substrate101and an elevated portion103EL, which is positioned at an elevated level with respect to the anchor portion103AN, connected to the anchor portion103AN. The elevated portion103EL has a bottom surface spaced from the top surface101T by a vertical distance H′. ComparingFIG. 8BandFIG. 8B′, the space under the elevated portion103EL is originally filled with the core portion103A or the insulated pattern. The anchor portion103AN may possess a thickness TAN substantially identical to a thickness TEL of the elevated portion103EL, depending on the thickness uniformity at the formation of the cap portion103B. The elevated portion103EL possess a width WEL, which can be determined by the overlapping feature of the masking layer801and the masking layer802. In some embodiments, the width WEL is about 0.3 micrometer in consideration of the accessibility of the selective etchant that removes the core portion103A originally resides under the elevated portion103EL of the active feature.

The active feature inFIG. 8C′ shows a nanowire portion103NW connecting two adjacent anchor portions103AN at its respective ends. In some embodiments, the nanowire portion103NW includes one or more nanowires110. Each of the nanowires110may have a thickness TNW that is smaller than or equal to the vertical distance H′ of the corresponding elevated portion103EL. The elevated portion103EL corresponds to the nanowire110when they form a physical or electrical integrated body. The anchor portion103AN, the elevated portion103EL, and the nanowire portion103NW may be composed of identical active material such as polysilicon. When the anchor portion103AN and the elevated portion103EL are configured as a source or drain, and the nanowire portion103NW is configured as a channel of the sensing device, the anchor portion103AN and the elevated portion103EL may be composed of doped polysilicon while the nanowire portion103W may be composed of undoped polysilicon. One of the anchor portion103AN and the elevated portion103EL of the active feature may be further connected to an interconnect structure receiving an external bias or signal.

In some embodiments, a top surface103T2of the anchor portion103AN is at a level higher than a top surface110T of the nanowire portion103NW if the patterning of the cap portion103B consumes the cap portion103B at the sidewall of the core portion103A. In some embodiments, a top surface103T2of the anchor portion103AN is at a level substantially identical to a top surface110T of the nanowire portion103NW if the patterning of the cap portion103B does not consume the cap portion103B at the sidewall but only consume the cap portion103B at the top surface of the core portion103A.

FIG. 9Ais a top view of a semiconductor sensing device, in accordance to some embodiments of the present disclosure.FIG. 9B,FIG. 9C, andFIG. 9Dare cross sectional views of the semiconductor sensing device corresponding to line EE, line FF, and line GG, respectively, ofFIG. 9A, in accordance to some embodiments of the present disclosure. InFIG. 9B, an anchor portion103AN extends over the top surface101T of the substrate101. InFIG. 9C, an elevated portion103EL is connected to anchor portions103AN at both sides of an insulated pattern (currently removed). InFIG. 9D, a nanowire portion103NW includes two nanowires110residing at both sides of an insulated pattern (currently removed). Each nanowire110includes a vertical sidewall110V and a curved sidewall110C mutually connected. The vertical sidewall110V follows the morphology of the sidewalls of the insulated pattern (currently removed).

FIG. 10is a cross sectional view of a semiconductor sensing device associated toFIG. 9D. In some embodiments, a sensing layer90is coated over the vertical sidewall110V and the curved sidewall110C of both nanowires110in order to increase the contact area with the sensing target. Referring back toFIG. 7B′,FIG. 7C′,FIG. 8B′ andFIG. 8C′, the anchor portion103AN and the elevated portion103EL act as a baffle that enhances the agitation effect in a microfluid which contains sensing target, so that possibility of collisions between sensing target and the sensing layer90coated over the nanowires110can be increased.

FIG. 11A,FIG. 11B, andFIG. 11Care perspective views of a semiconductor sensing device during sequential manufacturing stages, in accordance to some embodiments of the present disclosure. Intermediate operations betweenFIG. 6CandFIG. 6Dare further described inFIG. 11A,FIG. 11B, andFIG. 11C. Referring toFIG. 6DandFIG. 11A, the active portion600of the reference feature103can be formed by forming a core portion103A, for example, an insulated pattern, and a cap portion103B, for example, an active layer, covering the core portion103A. Although the insulated pattern shown inFIG. 11Aappears as a stripe, other patterns can also be adopted, for example, a zig-zag pattern. NoteFIG. 11A,FIG. 11B, andFIG. 11Cshow only one half of the reference feature103by dissecting the reference feature103from a geometric center. Subsequently, performing an ion implantation over the cap portion103B of the reference feature103, for instance, the implanted dopants reside at a top surface of the cap portion103B. In some embodiments, the active layer may be composed of a polysilicon film, for example, an undoped or a doped polysilicon film. InFIG. 11B, the cap portion103B is patterned to expose a center portion1100C of the isolative pattern, leaving an edge portion1100E of the insulated pattern covered by the cap portion103B. The center portion1100C and the edge portion1100E of the insulated pattern are further depicted inFIG. 12E′ andFIG. 12E″ from a top view perspective. The patterning of the cap portion103B includes an anisotropic etch that possesses an etching rate greater at a horizontal surface than at a vertical surface. As shown inFIG. 11B, the cap portion103B at the vertical surface of the core portion103A is preserved and subsequently forms the nanowire portion103NW as previously described. In some embodiments, the preserved cap portion103B at the vertical surface of the core portion may be substantially undoped. In some embodiments, a dopant concentration of the cap portion103B may be different from a dopant concentration of the nanowire portion103NW. In some embodiments, a conductivity type of the dopant in the cap portion103B may be different from a conductivity type of the dopant in the nanowire portion103NW. InFIG. 11C, the remaining part of cap portion103B undergoes an annealing operation in order to activate the dopants and diffuse the dopants downward from the top surface. The integration configuration of the nanowires and the cap portion103B as shown can effectively prevent dopant diffusion from the cap portion103B toward the nanowire during the annealing operation.

FIG. 12A,FIG. 12B,FIG. 12C,FIG. 12D,FIG. 12E,FIG. 12F,FIG. 12G,FIG. 12H,FIG. 12I,FIG. 12Jare cross sectional views of a semiconductor sensing device during various intermediate manufacturing stages, in accordance to some embodiments of the present disclosure.FIG. 12E′ andFIG. 12E″ are top views of the semiconductor sensing device during the intermediate stage ofFIG. 12E, in accordance to some embodiments of the present disclosure. Intermediate operations betweenFIG. 6BandFIG. 6Care further described fromFIG. 12AtoFIG. 12E. InFIG. 12A, a substrate101is provided. InFIG. 12B, an insulating layer120is blanket formed over the substrate101, and a core layer103A′ is formed over the insulating layer120. InFIG. 12C, the core layer103A′ is patterned to form a core portion103A, which can be an isolative stripe, over the insulating layer120. The insulated stripe may possess a principal dimension103A1, as shown inFIG. 12E′ andFIG. 12E″. InFIG. 12D, a cap portion103B is formed over the core portion103A as well as the top surface of the insulating layer120. InFIG. 12E, the cap portion103B is patterned to expose a top surface of the core portion103A and forming a desired pattern121over the insulating layer120. The remaining cap material at the vertical sidewalls of the core portion103A after the patterning operation ofFIG. 12Eform a nanowire structure122in a sensing region of a semiconductor sensing device. In some embodiments, the pattern121can be a source or a drain of a sensing structure in the sensing region of the substrate101, the pattern121being connected to the nanowire structure122, as shown inFIG. 12E′.FIG. 12Emay be a cross sectional view dissecting from line12X ofFIG. 12E′. In some embodiments, the pattern121can be a gate structure of a transistor in a circuit region of the substrate101, as shown inFIG. 12E″. The circuit region and the sensing region each occupies different areas of the substrate101. The circuit region may include one or more transistor structure and/or memory structure.FIG. 12Emay be a cross sectional view dissecting from line12X′ ofFIG. 12E″. InFIG. 12F, an inter-layer dielectric (ILD)124may be formed to cover the core portion103A, the nanowire structure122, and the pattern121. InFIG. 12G, a contact125may be formed in the ILD124to pick up the gate structure in the circuit region of the source or drain in the sensing region for subsequent interconnect preparation. InFIG. 12H, dielectric layers126including oxide and/or nitride are stacked over the contact125and the ILD124. An opening is formed in the dielectric layers and projecting over the core portion103A and the nanowire structure122. Another opening is formed in the dielectric layers and projecting over the contact125in the circuit region or the sensing region.

Intermediate operations betweenFIG. 6FDandFIG. 6FEare further described fromFIG. 12IandFIG. 12J. InFIG. 12I, a masking layer123is formed to expose only the opening projecting over the core portion103A and the nanowire structure122. A plasma-containing etch, an anisotropic etch, or a dry etch is performed through the masking layer123until the top surface of a reference feature, or a reference level, is reached (not shown inFIG. 12I). Subsequently, a selective etch, which is more selective to the materials of the core portion103A and the inter-layer dielectric ILD than the materials of the nanowire structure122and the insulating layer120, is performed to remove the core portion103A and release the nanowire structure122to become free-standing nanowires.

FIG. 13is a top view of a layout of several masking layers for manufacturing a semiconductor sensing device, in accordance to some embodiments of the present disclosure.FIG. 14is a top view and several cross sectional views xx1, yy1, zz1of the semiconductor sensing device during an intermediate manufacturing stage utilizing the making layers ofFIG. 13, in accordance to some embodiments of the present disclosure. It is shown that the masking layer1301possesses a stripe pattern with gradual narrowing width from a center1100C toward an end1100E. The gradual narrowing feature can be in a form of step shapes, as depicted inFIG. 13. However, the gradual narrowing feature may take other forms as long as the width is decreased to a predetermined value at the end of the stripe pattern. In the following figures, subsequent structures manufactured using the masking layer1301and masking layer1302are demonstrated at three cross sections xx, yy, and zz. InFIG. 13, the masking layer1301may be utilized to form a photoresist pattern1301′ inFIG. 14. The photoresist pattern1301′ subsequently being transferred into a core layer1030A, for example, insulated materials such as oxides or nitrides, inFIG. 14. As shown inFIG. 14, prior to an etching operation transferring the photoresist pattern1301′ into the core layer1030A, the gradually narrowing feature possesses different photoresist heights at cross sections xx1, yy1, and zz1, respectively.

FIG. 15is a top view and several cross sectional views xx2, yy2, zz2of the semiconductor sensing device during an intermediate manufacturing stage utilizing the masking layers ofFIG. 13, in accordance to some embodiments of the present disclosure. InFIG. 15, the cap layer1030B is blanket-deposited over the core portion103A which takes in the photoresist pattern1301′. As shown in cross sections xx2, yy2, and zz2, the closer the core portion103A to a center of the stripe pattern, the higher the core portion103A. The cap layer1030B conforms to the morphology of the underlying core portion103A.

FIG. 16is a top view and several cross sectional views xx3, xx3′, yy3, yy3′, zz3, zz3′ ww3, ww3′ of the semiconductor sensing device during an intermediate manufacturing stage utilizing the masking layers ofFIG. 13, in accordance to some embodiments of the present disclosure.FIG. 16shows a masking layer1601for patterning the source and drain of the semiconductor sensing device. The masking layer1601resides at the portion of the insulated stripe possessing constant width. InFIG. 16, an anisotropic etch is then performed to remove the portion of the cap layer1030B on horizontal surfaces, including the top horizontal surface of the core portion103A and the top horizontal surface of the substrate, thereby exposing the top horizontal surface of the core portion103A and the top horizontal surface of the substrate. After the anisotropic etch, the portion of the cap layer1030B at sidewalls of the core portion103A stays un-removed and becomes nanowires in current semiconductor sensing device. Due to the narrow width and small height of the core portion103A at the end of the insulated stripe, the nanowires may not be continuous at said end of the insulated stripe, thereby forming broken wire as shown at the proximity of cross sections zz3and zz3′ ofFIG. 16. In this illustration, the nanowire obtained after the anisotropic etch may be discontinued at both ends of the insulated stripe, forming two discrete or electrically isolated nanowires which are not electrically connected. A single nanowire device may provide better sensitivity than multi-nanowire device as far as the electrical characteristics, for example, current and/or resistivity, is being used as a sensing indication. Patterning of a core portion103A with gradual narrowing width from a center1100C toward an end1100E may lead to the self-discontinuity of the nanowire because the narrowest portion of the core portion103A at cross section zz3or zz3′ may be close to or exceed the photolithography line width limit. The narrowest portion at cross section zz3or zz3′ possesses a smaller height than any of the portion at cross sections xx3, xx3′, yy3, yy3′ so that the un-removed cap layer1030B at the vertical sidewall of the narrowest portion at cross section zz3or zz3′ may be discontinued during the anisotropic etch. A cross section ww3traversing the masking layer1601and the insulated stripe shows a cap portion103B being elevated to reside at the top surface of the core portion103A. Depending on the extent of overlap between the masking layer1601and the core portion103A, a width of the elevated portion of the cap portion103B may vary.

FIG. 17is a top view and several cross sectional views xx4, xx4′, yy4, yy4′, zz4, zz4′ ww4, ww4′ of the semiconductor sensing device during an intermediate manufacturing stage utilizing the making layers ofFIG. 13, in accordance to some embodiments of the present disclosure. InFIG. 17, the masking layer1601inFIG. 16is removed after the anisotropic etch. The cap portion103B exposed from the masking layer1601is configured as a source or a drain in the semiconductor sensing device, and only a single nanowire is connecting the source and the drain. A single nanowire semiconductor sensing device, which includes a nanowire connecting to a source and a drain at respective ends, can be obtained by a self-aligned manner. A length of the nanowire is defined by the source and the drain at its respective ends, and hence is defined at the completion of the anisotropic etch. In some embodiments, the device density of the single nanowire semiconductor sensing device depends on the width P of the insulated stripe, or the core portion103A, as shown in the masking layer1301ofFIG. 13.

FIG. 18is a top view of a layout of several masking layers for manufacturing a semiconductor sensing device, in accordance to some embodiments of the present disclosure.FIG. 19is a top view and several cross sectional views of the semiconductor sensing device during an intermediate manufacturing stage utilizing the making layers ofFIG. 18, in accordance to some embodiments of the present disclosure. It is shown that the masking layer1801possesses a stripe pattern with gradual narrowing width from a center1100C toward an end1100E. The gradual narrowing feature can be in a form of step shapes, as depicted inFIG. 18. However, the gradual narrowing feature may take other forms as long as the width is decreased to a predetermined value at the end of the stripe pattern. In the following figures, subsequent structures manufactured using the masking layer1801and masking layer1802are demonstrated at three cross sections xx, yy, and zz. InFIG. 18, the masking layer1301may be utilized to form a photoresist pattern1801′ inFIG. 19. The photoresist pattern1801′ subsequently being transferred into a core layer1030A, for example, a blanket-deposited polysilicon layer, inFIG. 19. As shown inFIG. 19, prior to an etching operation transferring the photoresist pattern1301′ into the core layer1030A, the gradually narrowing feature possesses different photoresist heights at cross sections xx1, yy1, and zz1, respectively.

FIG. 20is a top view and several cross sectional views xx2, yy2, zz2of the semiconductor sensing device during an intermediate manufacturing stage utilizing the masking layers ofFIG. 18, in accordance to some embodiments of the present disclosure. InFIG. 20, the cap layer1030B is blanket-deposited over the core portion103A which takes in the photoresist pattern1801′. As shown in cross sections xx2, yy2, and zz2, the closer the core portion103A to a center of the stripe pattern, the higher the core portion103A. The cap layer1030B conforms to the morphology of the underlying core portion103A.

FIG. 21is a top view and several cross sectional views xx3, xx3′, yy3, yy3′, zz3, zz3′, ww3, ww3′, ww3″ of the semiconductor sensing device during an intermediate manufacturing stage utilizing the masking layers ofFIG. 18, in accordance to some embodiments of the present disclosure.FIG. 21shows a masking layer2101for patterning the source and drain of the semiconductor sensing device. The masking layer2101resides at the portion of the insulated stripe with a width change. InFIG. 21, an anisotropic etch is then performed to remove the portion of the cap layer1030B on horizontal surfaces, including the top horizontal surface of the core portion103A and the top horizontal surface of the substrate, thereby exposing the top horizontal surface of the core portion103A and the top horizontal surface of the substrate. After the anisotropic etch, the portion of the cap layer1030B at sidewalls of the core portion103A stays un-removed and becomes nanowires in current semiconductor sensing device. Due to the narrow width and small height of the core portion103A at the end of the insulated stripe, the nanowires may not be continuous at said end of the insulated stripe, thereby forming broken wire as shown at the proximity of cross section zz3ofFIG. 21. In this illustration, the nanowire obtained after the anisotropic etch may be discontinued at both ends of the insulated stripe, forming two discrete or electrically isolated nanowires. Cross sections ww3′ and ww3traversing the masking layer2101and the insulated stripe shows a cap portion103B being elevated to reside at the top surface of the core portion103A. Depending on the extent of overlap O between the masking layer2101and the core portion103A, a width of the elevated portion of the cap portion103B may vary. Cross sections ww3″ traversing the remaining cap portion103B and the core portion103A, after the anisotropic etch, shows the nanowire (i.e., the remaining cap portion103B) at the sidewall of the core portion103A.

FIG. 22is a top view and several cross sectional views xx3, xx3′, yy3, yy3′, zz3, zz3′, ww3, ww3′, ww3″ of the semiconductor sensing device during an intermediate manufacturing stage utilizing the masking layers ofFIG. 18, in accordance to some embodiments of the present disclosure. InFIG. 22, the masking layer2101inFIG. 21is removed after the anisotropic etch. The cap portion103B exposed from the masking layer2101is configured as a source or a drain in the semiconductor sensing device, and only a single nanowire is connecting the source and the drain. A single nanowire semiconductor sensing device, which includes a nanowire connecting to a source and a drain at respective ends, can be obtained by a self-aligned manner. Cross sections at xx3, xx3′, yy3, yy3′, zz3, zz3′, ww3, ww3′, and ww3″ are provided inFIG. 22.

FIG. 23is a top view and a perspective view enlarging a junction portion J of the semiconductor sensing device during an intermediate manufacturing stage. InFIG. 23, at least a portion of the core portion103A is removed by a selective etch operation, exposing vertical sidewalls of the nanowires110in the nanowire portion103NW. The nanowires110are released from being in contact with the core portion103A. In some embodiments, a portion of the core portion103A outside of the nanowire region103NW and in proximity to the broken wires is remained in the semiconductor sensing device. The enlarged view of the junction portion shows the detailed structure of the anchor portion103AN, the elevated portion103EL, and the nanowire portion103NW previously described inFIG. 7B′,FIG. 7C′,FIG. 8B′, andFIG. 8C′.

A length of the nanowire is defined by the source and the drain at its respective ends, and hence is defined at the completion of the anisotropic etch. In some embodiments, the device density of the single nanowire semiconductor sensing device depends on the width P of the insulated stripe, or the core portion103A, as shown in the making layer1801ofFIG. 18