Structure for protecting an integrated circuit from electrostatic discharges

An integrated protective structure provides protection from electrostatic discharges of structures to an integrated circuit functionally connected to a certain external pin. The protective structure is formed in a single epitaxial tub and includes a triggering Zener diode and a vertical bipolar transistor. The collector region of the vertical bipolar transistor is connected to the pin and constitutes also one of the two terminal regions of the triggering Zener. Around the emitter region and separated therefrom by the smallest distance feasible, is an annular region, having a heavier doping than the base region of the transistor formed with the purpose of intercepting the avalanche current of the Zener junction and distributing it in a uniform manner into the base region of the vertical transistor as well as acting as a shield for eventual electrons moving from the emitter region toward the breakdown junction. Optionally, a further emitter region, may be formed in front of the collector/cathode region and connected to the annular region in order to create a lateral bipolar transistor which triggers-on during an electrostatic discharge; thus, reducing the ohmic drop through the protective structure and the breakdown voltage.

FIELD OF THE INVENTION 
The present invention relates to an integrated structure for protecting 
from electrostatic discharges an integrated circuit which is electrically 
connected to device which may be hit by an electrostatic discharge, as a 
consequence of tribologic effects during handling. The structure may be 
realized in a single isolated epitaxial tub and includes a vertical 
bipolar transistor and a triggering Zener diode. 
BACKGROUND OF THE INVENTION 
When handling integrated circuits, electrostatic discharge currents, 
deriving from an eventual discharging of electrified bodies (e.g. the 
human body of operators, metal tools, packages, etc.), may hit external 
pins of integrated circuits. There are various standardized models for 
simulating these phenomena, such as the so-called "human body model" and 
"the charged device model." 
In order to protect the integrated circuit, it is necessary to couple to an 
external pin, which may be hit by an electrostatic discharge, an 
integrated device or structure. This protecting device or structure 
protects the integrated devices or structures of the circuit which are 
connected to the particular external pin and are susceptible of 
destructive breakdown. The protecting structure must be as inconspicuous 
as possible during the normal functioning of the integrated circuit and 
must come into action by deriving across itself the discharge current 
whenever an electrostatic event, having a nonnegligeable level, occurs on 
the particular pin. Commonly, diodes or equivalent structures, capable of 
undergoing breakdown before the vulnerable structures of the integrated 
circuit connected to the pin breakdown, are connected between the pin to 
be protected and ground. The intrinsic disadvantage of Zener diodes, which 
are commonly used for this purpose, is that the discharge current tends to 
"concentrate" through the edge zone of the heavier diffusion of the 
junction undergoing breakdown because of the lower breakdown voltage 
exhibited by the curved zone of the junction. This current "concentration" 
effect causes a relatively large power dissipation within a restricted 
region of the semiconductor and an attendant localized overheating may 
lead to the melting of silicon and destruction of the protecting device. 
In some instances, the same pin may be connected through a second diode 
also to the supply rail, in order to distribute the discharge current over 
a larger number of junctions, which are normally connected to the supply 
rail. This offers more junctions to withstand the current. This second 
diode arrangement, however, may not be feasible in certain cases or may 
generate other problems. 
SUMMARY OF THE INVENTION 
Accordingly, a general object of the present invention is to provide a 
protective structure for protecting against electrostatic discharges (EDS) 
which structure, though being easy to implement, possibly, for example, in 
the form of a simple Zener junction having a relatively limited 
encumbrance, also has the ability of effectively limiting the 
above-discussed current concentration phenomena and its destructive 
consequences. 
This object and other advantages are achieved by the integrated protection 
structure of the present invention. Basically the integrated structure of 
the invention utilizes a vertical bipolar transistor and a triggering 
Zener diode which may be both advantageously integrated in a single 
isolated epitaxial tub. The emitter region of the vertical transistor is 
surrounded by a shielding ring, constituted by an annular diffusion of the 
same type of conductivity as the base region of the transistor but having 
a heavier doping level then the latter. This annular shielding region 
intercepts the avalanche current of the Zener junction and distributes 
this avalanche current to the base of the transistor in a uniform manner, 
thus effectively preventing a dangerous concentration of current through 
restricted zones of the ground-connected emitter region of the transistor.

DETAILED DESCRIPTION 
The depicted examples pertain to the case of the protecting structure used 
in an integrated circuit formed having an n- type epitaxial layer grown on 
a p type substrate solely for illustrative and nonlimitating purposes. The 
protecting integrated structure of the invention may advantageously be 
used alternatively in integrated circuits formed having an epitaxial layer 
of an opposite type of conductivity by simply inverting all the 
polarities, as will be evident to a person skilled in the art. 
With reference to FIG. 1, a protective structure of the present invention 
is formed in an epitaxial region 1 of an n- type epitaxial layer grown on 
a p type substrate 2. The region 1 is defined at the bottom by an n+ type 
buried layer 3 and laterally by a p type isolation diffusion 4. A first n+ 
type region 5 or at least a portion thereof may be advantageously formed 
directly under a metallization layer 12 of a connection pad 6. Region 5 
provides protection against ESD events of the integrated circuit. 
Alternatively, region 5 may be electrically connected to the metallization 
layer and the region 5 is also connected through a deep n+ (sinker) 
contact region 6 to the buried layer 3. The region 5 constitutes a first 
"terminal" of a triggering Zener diode of the protection structure. In the 
example depicted, the cathode region 5 of the diode acts also as a 
collector region of a bipolar vertical transistor, which, in the depicted 
example, is an NPN transistor, as will be described hereinbelow. A p- type 
region 7, which may have a diffusion profile as that of a p-well region, 
is entirely contained within the epitaxial tub and constitutes a second 
terminal region of the triggering Zener diode as well as a base region of 
the NPN vertical transistor. The emitter of the vertical NPN transistor is 
constituted by a second n+ type region 8 which is formed within the region 
7 and is electrically connected to ground. 
A p+ type annular region 9 entirely surrounds the emitter region 8 of the 
vertical NPN transistor and acts as a shield-distributor for the current 
injected into the base region during an electrostatic discharge having a 
sufficient intensity to bring into breakdown the Zener junction between 
the cathode region 5 and the anode region 7 of the triggering diode. 
Essentially, the annular region 9 has a higher doping level than the base 
region 7 and performs two functions. The first function is that of 
distributing in a more uniform manner, the current into the base region of 
the NPN vertical transistor in order to prevent a current concentration in 
restricted zones (curved zone) of the emitter junction. A second function 
is that of acting as a shield for an eventual flow of electrons which, 
from the emitter region 8, may be accelerated toward the junction between 
regions 5 and 7 when the latter goes into a breakdown condition. 
It has been observed, in fact, that the impact-ionization action caused by 
these high kinetic energy electrons, the in absence of a p+ ring region 9, 
in turn causes a remarkable current leakage, also under relatively low 
voltage bias, and a lowering of the breakdown voltage of the structure. 
Preferably, the separation distance between the annular region 9 and the 
emitter region 8 is as small as is permitted by the fabrication technology 
used for making the integrated circuit. The current which is distributed 
into the base region by the p+ ring 9 causes an injection of electrons 
from the emitter 8, which electrons are gathered by the n- epitaxial layer 
underlying the p- base region and thereafter by the n+ buried layer 3 
which is highly conductive. This action complies with a typical operating 
scheme of an NPN vertical transistor. 
It is important that the metal remain in contact with the region 5 of the 
cathode-collector region at a sufficient distance from the junction zone 
between the cathode region 5 and the anode region 7. 
The structure of the invention offers the advantage of distributing the 
discharge current over the breakdown junction and the base-collector 
junction of the vertical NPN transistor. The discharge current flowing 
through the vertical transistor structure is less critical then the 
current flowing through the breakdown junction n+/p-. In fact, the current 
flowing through the breakdown junction concentrates on the extreme edge of 
the relatively thin n+ diffused region, while the current through the 
vertical structure distributes more uniformly over the entire 
base-collector junction area, underneath the emitter 8. This offers 
durability and longevity to the protecting structure. 
A further advantage of the structure of the invention is due to the fact 
that the n+ cathode-collector region 5 is not entirely placed above the p- 
well region 7 partly so and partly above the n- epitaxial region 1. This 
advantage is as follows. If, during a particularly strong discharge, a 
vertical "spike" of aluminum of the pad metallization layer should form 
under the cathode contact, and even if the metal spike reaches the 
underlying n+ diffusion, there will not be any serious damage of the 
structure which will remain operative. 
A functional circuit diagram of the protection structure of FIG. 1 is 
depicted in FIG. 2 and comprises a triggering Zener diode DZ and a 
vertical NPN transistor. 
According to an alternative embodiment of the integrated protection 
structure of the invention, as schematically depicted in FIG. 3, the 
series resistance of the protection structure may be reduced by forming a 
third n+ region 10 in front of the n+ cathode-collector region 5 and by 
connecting this additional region 10 to the annular p+ region 9 with a 
metal connector 13. This causes the triggering of a lateral NPN transistor 
during an electrostatic discharge, whose emitter is constituted by the 
additional n+ region 10 which is short-circuited to the p+ annular region 
9. 
During a discharge, the operation is the following. The current caused by 
the breakdown of the n+/p- Zener junction (regions 5 and 7, respectively), 
by flowing through the resistive path (R) within the p- layer 7 underlying 
the n+ region 10 creates a forward conduction of the edge portion of the 
junction between said n+ diffusion 10 and the p- region 7. Electrons 
injected into the p- base region migrate toward the n+ region 5 which acts 
as cathode-collector for such a lateral NPN transistor. This operation 
procures two advantageous effects: 
1) a reduction of the breakdown voltage of the avalanche junction (between 
regions 5 and 7) because of the impact-ionization caused by electrons 
injected thereto; and 
2) a current flow through the lateral NPN structure is no longer due only 
to a drift current but also to a diffusion current (electrons diffusing 
from the emitter to the collector); this achieves a lower ohmic drop 
through the lateral structure and, therefore, a reduction of the voltage 
which will be reached by the protected pin (6) during a discharge. 
An equivalent electric circuit diagram of the integrated protective 
structure of FIG. 3 during an electrostatic discharge, in accordance with 
the operation described hereinabove, is shown in FIG. 4. As shown, the 
circuit includes a lateral NPN transistor and a vertical NPN transistor. 
It is to be appreciated that the foregoing description is presented by way 
of example only and in no way is intended to be limiting. The scope of 
protection is defined by the appended claims and equivalents thereto.