INFORMATION PROCESSING SYSTEM AND RELAY DEVICE

An information processing system includes: a first relay device provided with a plurality of end points and a root complex for relay; and a second relay device provided with a plurality of end points and an end point for relay. The plurality of end points of the first relay device individually connects to any of a plurality of first information processing devices over an expansion bus. The root complex for relay: relays communication between the first information processing devices via the corresponding end points of the first relay device; connects to the second relay device over an expansion bus; and functions as a root complex. The plurality of end points of the second relay device individually connects to any of a plurality of second information processing devices over an expansion bus.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-094753, filed May 20, 2019, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described herein relate to an information processing system and a relay device.

BACKGROUND

In an information processing system, in which a plurality of information processing devices are connected via a relay device including a plurality of connection I/F (for example, expansion bus slots), parallel distributed control to distribute pieces of processing among the information processing devices may be performed.

In such an information processing system, in a case of trying to perform communication between the information processing devices connected over the connection I/F (expansion bus slot), it is required to assign an address to each of the information processing devices.

However, in the information processing system of the related art mentioned above, when an address is assigned to each of the information processing devices connected to the respective relay devices, an address conflict may be arisen.

SUMMARY

An information processing system according to a first aspect of the present disclosure includes a first relay device and a second relay device. The first relay device is provided with a plurality of end points and a root complex for relay. The second relay device is provided with a plurality of end points and an end point for relay. The plurality of end points of the first relay device are configured to be individually connectable to any of a plurality of first information processing devices over an expansion bus. The root complex for relay is configured to: relay communication between the first information processing devices via the corresponding end points of the first relay device; be connectable to the second relay device over an expansion bus; and function as a root complex. The plurality of end points of the second relay device are configured to be individually connectable to any of a plurality of second information processing devices over an expansion bus. The end point for relay is configured to: relay communication between the second information processing devices via the corresponding end points of the second relay device; be connectable to the first relay device over an expansion bus; and function as an end point. The second relay device is configured to relay communication between the first information processing devices and the second information processing devices via the end point for relay. The first relay device or the second relay device further comprises a memory and one or more hardware processors. The memory is configured to store address specifying information used for assigning addresses to the first information processing devices or the second information processing devices connected to the respective positions of the corresponding end points, the addresses to be assigned being based on a relation between the first relay device and the second relay device and based on positions of the end points of the first relay device or the second relay device. The one or more hardware processors are configured to: specify the relation between the first relay device and the second relay device; and assign the addresses to the first information processing devices or the second information processing devices connected to the end points of the first relay device or the second relay device based on the specified relation, the positions of the connected end points, and the address specifying information.

A relay device according to a second aspect of the present disclosure includes a plurality of end points, a root complex for relay or an end point for relay, and a memory. The plurality of end points is configured to be individually connectable to any of a plurality of information processing devices over an expansion bus. The root complex for relay or an end point for relay is configured to be connectable to another relay device over an expansion bus, and function as a root complex or an end point. The memory is configured to store address specifying information used for assigning addresses to the information processing devices connected to the respective positions of the end points, the addresses to be assigned being based on a relation with another relay device and positions of the end points.

DETAILED DESCRIPTION

According to the information processing system disclosed herein, it is capable of implementing appropriate communication processing between the information processing devices connected via the relay devices.

FIG. 1is a diagram illustrating an example of a whole configuration of an information processing system according to an embodiment. As illustrated inFIG. 1, an information processing system1according to the present embodiment includes a first relay device101, a second relay device102, a main unit111, a plurality of platforms112-1to112-6on a master side, and a plurality of platforms113-1to113-8on a slave side.

The first relay device101and the second relay device102are connected to each other over an expansion bus (in the present embodiment, a PCI Express bus (hereinafter, also referred to as a PCIe bus)). In the present embodiment, the first relay device101functions as a master, and the second relay device102functions as a slave.

The main unit111and the platforms112_1to112_6on the master side are connected to the first relay device101over the expansion bus (for example, the PCIe bus).

In the following description, when the platforms112_1to112_6on the master side are not required to be distinguished from each other, the platforms112_1to112_6on the master side may be collectively referred to as a platform112on the master side. The following describes an example in which the information processing system1according to the present embodiment includes six platforms on the master side. However, it is sufficient for the information processing system1to include two or more platforms (information processing devices).

The platforms113_1to113_8on the slave side are connected to the second relay device102over the expansion bus (for example, the PCIe bus).

In the following description, when the platforms113_1to113_8on the slave side are not required to be distinguished from each other, the platforms113_1to113_8on the slave side may be collectively referred to as a platform113on the slave side. The following describes an example in which the information processing system1according to the present embodiment includes eight platforms on the slave side. However, it is sufficient that the information processing system1includes two or more platforms (information processing devices).

When the platforms112_1to112_6on the master side and the platforms113_1to113_8on the slave side are not required to be distinguished from each other, the platforms112_1to112_6on the master side and the platforms113_1to113_8on the slave side may be collectively referred to as platforms112and113.

The first relay device101is provided with a switch103and a bus control processor104. The first relay device101is also provided with eight end points105(a first end point105_1to an eighth end point105_8) as a plurality of connection units that are connectable to the main unit111and the platforms112on the master side. The first relay device101is also provided with a root complex (RC) for relay106as a relay connection unit that is connectable to another relay device, the RC enabling the first relay device101to connect to the second relay device102.

When the first end point105_1to the eighth end point105_8are not required to be distinguished from each other, the first end point105_1to the eighth end point105_8may be collectively referred to as the end point105.

The switch103is a hardware switch configured to switch the first relay device101between the master and the slave. In the present embodiment, while the switch103of the first relay device101is set to be the master, the switch103of the second relay device102is set to be the slave. Accordingly, the first relay device101functions as the master, and the second relay device102functions as the slave.

The bus control processor104of the first relay device101controls communication with each of the main unit111and the platforms112on the master side connected to the respective end points105. The bus control processor104of the first relay device101controls communication with the platforms113on the slave side connected to the second relay device102via the relay root complex106of the expansion bus (in the present embodiment, the PCIe bus). The bus control processor104is not limited to a single processor, and may be configured by combining a plurality of processors.

The bus control processor104includes a specification unit141and an acquisition unit142as software configurations. For example, the bus control processor104implements the specification unit141and the acquisition unit142such that a central processor unit (CPU) (not illustrated) reads a computer program corresponding to those units from a read only memory (ROM) (not illustrated) and executes the computer program.

The specification unit141specifies a relation between the first relay device101and the second relay device102, in other words, specifies that the first relay device101is the master or the slave, by referring to a setting of the switch103. The specification unit141according to the present embodiment specifies that the first relay device101is the master. The present embodiment describes, as an example of specifying the relation between the relay devices, processing of specifying that the relay device is the master or the slave. However, the embodiment is not limited to the specification as to the master or the slave. In a case in which three or more relay devices are connected, a hierarchy thereof and the like may be specified. Then, the bus control processor104of the first relay device101performs control based on the relation between the relay devices.

The acquisition unit142accesses the root complex (RC) for relay106to acquire state information representing presence/absence of connection to each of the end points105of the second relay device102. The acquisition unit142then transmits the acquired state information to each of the end points105of the first relay device101. Thus, each of the end points105is able to recognize a connection state of the second relay device102.

The first end point (EP)105_1to the eighth end point (EP)105_8each include a processing unit108and a memory109, and also includes a connection I/F with the expansion bus (PCIe bus) for making connection with the main unit111or each of the platforms112and113.

The memory109of the end point105is an example of a storage unit configured to store address specifying information used for assigning a corresponding MAC address to each of the main unit111and the platforms112and113. Details thereof will be described later. The processing unit108of the end point105performs data transfer to/from a root complex114included in the main unit111or the platforms112and113, each being connected via the connection I/F.

The processing unit108can identify the connection state of each of the end points105of the first relay device101(i.e., identify whether the main unit or the platform112on the master side is connected to each end point105) over an internal bus of the first relay device101.

The processing unit108can also identify whether the platform is connected to the end point105in the second relay device102by receiving the state information from the acquisition unit142.

The processing unit108then performs processing for writing an identification result and the received state information into a memory116of the root complex114. By this processing, a processing unit115of the root complex114can recognize the connection state of each of the end points105of the first relay device101and the second relay device102.

The root complex (RC) for relay106includes a processing unit121and a memory122, and also includes a connection I/F for making connection with an end point (EP) for relay107.

The root complex for relay106is configured to relay communication between the platforms112on the master side and the platforms113on the slave side via the relay end point107.

The memory122of the root complex for relay106stores the state information representing presence/absence of connection of the main unit111and the platforms112on the master side to the respective end points105included in the first relay device101. By this, the end point (EP) for relay107of the second relay device102can acquire the state information representing presence/absence of connection to each of the end points105included in the first relay device101.

The processing unit121of the root complex for relay106is configured to control data transfer between the first relay device101and the second relay device102.

The second relay device102includes the switch103and the bus control processor104. The second relay device102further includes eight end points105as connection units that are connectable to the respective platforms113on the slave side. The second relay device102further includes, as the relay connection unit that is connectable to another relay device, the end point (EP) for relay107enabling the second relay device102to connect to the first relay device101. The configurations of the second relay device102are the same as the configurations of the first relay device101except the end point (EP) for relay107. Thus, the configurations are denoted by the same reference numerals, and description thereof will not be repeated.

The bus control processor104of the second relay device102is configured to control communication with each of the platforms113on the slave side connected to the respective end points105. The bus control processor104of the second relay device102also controls communication with the platforms112on the master side connected to the first relay device101via the relay end point107of the expansion bus (in the present embodiment, the PCIe bus).

The bus control processor104includes a specification unit151and an acquisition unit152as software configurations.

The specification unit151of the bus control processor104in the second relay device102is configured to specify a relation between the first relay device101and the second relay device102, in other words, specify that the second relay device102is the master or the slave, by referring to the setting of the switch103. The specification unit151according to the present embodiment specifies that the second relay device102is the slave.

The acquisition unit152of the bus control processor104in the second relay device102is configured to access the end point for relay107to acquire the state information representing presence/absence of connection to each of the end points105of the first relay device101. The acquisition unit152then transmits the state information to each of the end points105of the second relay device102. By this, each of the end points105of the second relay device102is able to recognize the connection state of the first relay device101.

The first end point (EP)105_1to the eighth end point (EP)105_8of the second relay device102are the same as the first end point (EP)105_1to the eighth end point (EP)105_8of the first relay device101, so that the description thereof is omitted.

The end point for relay107includes a processing unit131and a memory132, and also includes a connection I/F for making connection with the root complex for relay106.

The end point for relay107relays communication between the platforms113on the slave side and the platforms112on the master side via the root complex for relay106.

The memory132of the end point for relay107is configured to store the state information representing presence/absence of connection to each of the end points105of the second relay device102via the bus control processor104. By this, the root complex for relay106of the first relay device101is able to acquire the state information representing presence/absence of connection to each of the end points105of the second relay device102.

The processing unit131of the end point for relay107is configured to control data transfer using the memory132to/from the first relay device101that is connected to the second relay device102via the connection I/F.

The main unit111includes two root complexes (RCs)114, the processing unit115, and the memory116. When the processing unit115executes a computer program stored in the memory116, the main unit111operates as a host personal computer (PC) functioning as a control unit and a graphical user interface (GUI) of the information processing system1.

The platforms112on the master side and the platforms113on the slave side are each an information processing device that includes the root complex (RC)114of the expansion bus (in the present embodiment, the PCIe bus), the processing unit115, and the memory116, and performs various arithmetic operations. When the processing unit115executes a computer program stored in the memory116, artificial intelligence (AI) inference processing, image processing, and the like are performed by the platforms112on the master side and the platforms113on the slave side.

The respective processing units115included in the main unit111, the platforms112on the master side, and the platforms113on the slave side may be provided by different manufacturers (vendors), or may be provided by the same manufacturer.

The root complex114includes a connection I/F for making connection with the end point105.

The memory116of each of the main unit111and the platforms112and113is used at the time of performing various kinds of processing. For example, the memory116is used to store information such as the address specifying information when it transmitted from the end point105.

The processing unit115of each of the main unit111and the platforms112and113controls, by using the memory116, data transfer to/from the end point105that is connected thereto via the root complex114.

In the present embodiment, at the time of performing communication among the main unit111and the platforms112and113, control similar to the control for communication over a virtual LAN is implemented by calling a virtual LAN driver and transmitting or receiving data. The following describes specific software configurations.

FIG. 2is a block diagram exemplifying software configurations of the main unit and the platforms according to the present embodiment.

As illustrated inFIG. 2, the processing unit115of the main unit111executes an application209by implementing a BIOS202, an OS203, a driver204, a service205, a virtual LAN driver206, a distributed control unit207, and common software208. A PC platform201of the main unit111is a hardware resource of the main unit111.

The main unit111includes the BIOS202functions to read the OS203at the time of activation and perform basic input/output control for the main unit111. The OS203is activated by the BIOS202. The OS203may be Windows (registered trademark), for example, but any OS can be used.

The OS203functions to read various drivers204including a bridge driver204A that is used for controlling the expansion bus (for example, the PCIe bus) and access the root complex114to communicate with another platform (for example, any of the platforms112_1to112-6on the master side and the platforms113_1to113_8on the slave side). The OS203also functions to read the service205for performing various kinds of control to perform various kinds of processing.

The virtual LAN driver206and the distributed control unit207are implemented in an upper layer of the driver204and the service205. The application209implements communication with another platform (for example, any of the platforms112_1to112-6on the master side and the platforms113_1to113_8on the slave side) over a virtual LAN by accessing the virtual LAN driver206via the common software208.

Similarly, the platforms112_1and112_2on the main side can perform distributed processing A and distributed processing B by implementing a Bootloader212, an OS213, a driver214, a virtual LAN driver215, a distributed control unit216, and common software217. A hardware platform211is a hardware resource of the platforms112_1and112_2on the main side.

In the platforms112_1and112_2on the main side, the Bootloader212is activated when a power supply is turned on, and the Bootloader212activates the OS213.

The OS213reads various drivers214including a bridge driver214A for controlling the expansion bus (for example, the PCIe bus), and accesses the root complex114to communicate with another platform (for example, any of the main unit111, the platforms112_3to112-6on the master side, and the platforms113_1to113_8on the slave side).

The virtual LAN driver215and the distributed control unit216are implemented in an upper layer of the driver214. By accessing the virtual LAN driver215via the common software217, the distributed processing A and the distributed processing B implement communication with another platform (for example, any of the main unit111, the platforms112_3to112-6on the master side, and the platforms113_1to113_8on the slave side) over the virtual LAN.

In order to implement communication over the virtual LAN as described above, it is required to assign a virtual Media Access Control (MAC) to each PCIe expansion bus. It may be considered that the virtual MAC address is assigned to each of the first end point105_1to the eighth end point105_8based on a CH number of the corresponding end point.

However, in a case of assigning the virtual MAC address based on the CH number alone, MAC addresses may conflict with each other between the first relay device101and the second relay device102. Thus, in the present embodiment, the MAC address is assigned based on that the relay device is the master or the slave, in other words, based on the relation between the relay devices.

FIG. 3is a diagram exemplifying a main ID and a sub ID assigned to each of the main unit111and the platforms112and113according to the present embodiment.

As illustrated inFIG. 3, CH0to CH7are respectively assigned to the first end point105_1to the eighth end point105_8of the first relay device101. Thus, main IDs “0038” to “003F” corresponding to CH numbers are respectively and uniquely assigned to the main unit111and the platforms112on the main side connected to the first end point105_1to the eighth end point105_8. Additionally, the relation (“master”) specified by the specification unit151is passed to the first end point105_1to the eighth end point105_8of the first relay device101. By this, the processing unit108of each of the first end point105_1to the eighth end point105_8of the first relay device101specifies a sub ID “0028” corresponding to the relation (“master”) as the sub ID to be assigned to each of the main unit111and the platforms112on the main side that are connected thereto.

CH0to CH7are respectively assigned to the first end point105_1to the eighth end point105_8of the second relay device102. Thus, the main IDs “0038” to “003F” corresponding to the CH numbers are respectively and uniquely assigned to the platforms113on the slave side connected to the first end point105_1to the eighth end point105_8. Additionally, the relation (“slave”) specified by the specification unit151is passed to the first end point105_1to the eighth end point105_8of the second relay device102. Due to this, the processing unit108of each of the first end point105_1to the eighth end point105_8of the second relay device102specifies a sub ID “0029” corresponding to the relation (“slave”) as the sub ID to be assigned to each of the platforms113on the slave side that are connected thereto.

FIG. 4is a diagram exemplifying a table structure of the address specifying information stored in the memory109according to the embodiment. As illustrated inFIG. 4, in the address specifying information, the main ID representing a position of the end point (connection unit) of the first relay device101or the second relay device102, the sub ID representing the relation between the first relay device and the second relay device, and the virtual MAC address are linked with each other. The virtual MAC address here refers to an address that is virtually assigned to use within the virtual LAN driver for performing communication over the expansion bus (PCIe bus) in a lower layer while causing an upper layer to recognize a virtual LAN connection.

The processing unit108of the end point105transmits the main ID (the ID corresponding to a connecting position), the specified sub ID (the ID based on the relation), and the address specifying information to the main unit111or the platform112or113connected to this end point105.

By referring to the address specifying information, the processing unit115of each of the main unit111and the platforms112and113assigns the virtual MAC address to implement transmission control performed by the virtual LAN driver of its own based on the specified sub ID and the main ID (ID corresponding to the position to which the main unit or the platform112or113is connected).

In a case of transmitting data to the platform within the same relay device, the processing unit115of each of the main unit111and the platforms112and113can specify the virtual MAC address assigned to a transmission destination based on the sub ID and the main ID corresponding to the position of the transmission destination (ID corresponding to the position to which the main unit or the platform112or113is connected) by referring to the address specifying information.

The processing unit108of the end point105transmits, as needed, the state information representing the connection state of the end point105of another relay device to the main unit111or the platform112or113connected thereto.

Therefore, the processing unit115of each of the main unit111and the platforms112and113can confirm whether the transmission destination is connected, based on the state information in a case in which the platforms112and113connected to another relay device is the transmission destination. When it is confirmed that the transmission destination is connected, the processing unit115can specify, by referring to the address specifying information, the virtual MAC address assigned to the transmission destination based on the main ID representing the connecting position of the transmission destination and the sub ID representing the relation of the connection destination.

For example, in a case in which any one of the main unit111and the platforms112on the master side connected to the first relay device101transmits some information to any one of the platforms113on the slave side connected to the second relay device102, the processing unit115of each of the main unit111and the platforms112on the master side acquires the state information from the end point105, and confirms whether any one of the platforms113on the slave side as the transmission destination is connected thereto based on the state information. Then, when it is confirmed that the transmission destination is connected thereto, any one of the main unit111and the platforms112on the master side specifies the virtual MAC address assigned to the transmission destination by referring to the address specifying information. The virtual LAN driver206or215operated by the processing unit115performs data transmission control based on the virtual MAC address (assuming that the main unit111or the platform112or113linked with the virtual MAC address is the transmission destination).

FIG. 5is a flowchart illustrating processing for specifying the virtual MAC address by the platform112or113according to the present embodiment.

Firstly, the power supply of the information processing system1is turned on by being operated by a user (S501).

Next, the specification unit141or151of the bus control processor104of the first relay device101or the second relay device102determines whether the switch103is set to be the master (S502).

When it is determined that the switch103is set to be the master (Yes at S502), the specification unit141of the bus control processor104specifies the sub ID corresponding to the master and gives the specified sub ID to the end point105in the relay device101(S503).

On the other hand, when it is determined that the switch103is not set to be the master, in other words, the switch103is set to be the slave (No at S502), the specification unit141of the bus control processor104specifies the sub ID corresponding to the slave and gives the sub ID to the end point105in the relay device102(S504).

The processing unit108of the end point105in the relay device101or102transmits the main ID corresponding to the position of the end point, the given sub ID, and the address specifying information to the root complex114connected to this end point105(S505). The processing unit115of the main unit111or the platform112or113writes, into the memory116, the main ID, the sub ID, and the address specifying information transmitted from the root complex114.

The processing unit115of the main unit111or the platform112or113then specifies the virtual MAC address linked with the main ID and the sub ID by referring to the address specifying information (S506).

By the above processing, the virtual MAC address is assigned to each of the main unit111and the platforms112and113.

FIG. 6is a flowchart illustrating processing for transmitting the information by the platform112or113according to the present embodiment.

Firstly, the processing unit115of the main unit111or the platform112or113determines whether the transmission destination is another platform in the own (or local) relay device (S601).

When it is determined that the transmission destination is another platform in the own relay device (Yes at S601), the processing unit115of the main unit111or the platform112or113confirms whether the platform112or113is connected to the end point105as the transmission destination via the end point105(S602).

On the other hand, if it is determined that the transmission destination is not another platform112or113in the own relay device (No at S601), the processing unit115of the main unit111or the platform112or113acquires the state information that has been acquired by the acquisition unit152of the bus control processor104(S603). The state information represents that the platform112or113is connected or not connected to another relay device.

The processing unit115of the platform112or113confirms, by referring to the state information, whether the platform112or113as the transmission destination of another relay device is connected (S604).

When it is confirmed that the platform is connected to the end point, the processing unit115of the main unit111or the platform112or113specifies the virtual MAC address corresponding to the platform112or113as the transmission destination by referring to the address specifying information (S605).

Then, the virtual LAN driver implemented in a processor (not illustrated) of the platform112or113performs data transmission control using the virtual MAC address specified as the transmission destination and the virtual MAC address for identifying the own platform112or113(S606). For example, the virtual LAN driver specifies which of channels on the master side or the slave side corresponds to the virtual MAC address, and performs data transmission control by using the specified channel as the transmission destination via the bridge driver204A or214A. In this way, in a hierarchical level upper than a software layer in a hierarchy of a communication protocol, a destination is designated with the MAC address at the time of transmitting data. In a driver layer lower than the software layer, transmission control is performed by using a channel on the master side or the slave side specified with the MAC address as the transmission destination.

While the present embodiment describes an example in which the address specifying information is stored in the memory109of the end point105, a storage destination of the address specifying information is not limited thereto. For example, the address specifying information may be stored in advance in the memory116of the main unit111or the platform112or113.

The present embodiment describes an example in which the processing unit115of the main unit111or the platform112or113specifies the virtual MAC address. The processing unit that specifies the virtual MAC address is not limited to the processing unit115of the main unit111or the platform112or113. For example, the processing unit108of the end point105may specify the virtual MAC address to be transmitted to the root complex114, or a processing unit (not illustrated) in the root complex114may specify the virtual MAC address. Alternatively, the bus control processor104may specify the virtual MAC address for each of the end points105to be transmitted to each of the root complexes114.

The present embodiment describes an example of storing the table in which the main ID, the sub ID, and the virtual MAC address are linked with each other as the address specifying information. However, the address specifying information is not limited to the table in which the main ID, the sub ID, and the virtual MAC address are linked with each other. For example, the address specifying information may be information that enables assignment of a virtual MAC address based on the relation between the first relay device101and the second relay device102, and the position of the connection unit of the first relay device101or the second relay device102. The virtual MAC address may be generated by combining a predetermined number, a number denoting the main ID, and a number denoting the sub ID. In this case, the predetermined number is stored in the memory109of the end point105as the address specifying information. The present embodiment describes the example of specifying the virtual MAC address, but a target to be specified is not limited to the MAC address. The target may be an address that can specify the main unit111or the platform112or113.

Modification

The above embodiment describes a case in which the platform performs data transmission control for another platform. However, the use of the virtual MAC address is not limited to the case described in the above embodiment.

FIG. 7is an explanatory diagram exemplifying a configuration of a common memory in each of the platforms according to a modification. As illustrated inFIG. 7, platforms711_1to711_8on the master side and platforms712_1to712_8on the slave side include common memories CM1to CM16having the same configuration.

The common memories CM1to CM16each include a first region Slot #0 to a sixteenth region Slot #15.

The first region Slot #0 in the common memory CM1is a region where data to be received by the platform711_1on the master side from another platforms711_1to711_8on the master side and the platforms712_1to712_8on the slave side is written. The second region Slot #1 is a region where data (including an application) to be transmitted from the platform711_1on the master side to the platform711_2on the master side is written. Similarly, the third region Slot #2 to the eighth region Slot #7 are each a region where data to be transmitted from the platform711_1on the master side to the platforms711_3to711_8on the master side is written. The ninth region Slot #8 to the sixteenth region Slot #15 are each a region where data to be transmitted from the platform711_1on the master side to the platforms712_1to712_8on the slave side connected to the second relay device102is written. The second region Slot #1 in the common memory CM2is a region where data to be received by the platform711_2on the master side from the other platforms711_1and711_3to711_8on the master side and the platforms712_1to712_8on the slave side is written. The first region Slot #0 and the third region Slot #2 to the eighth region Slot #7 are each a region where data to be transmitted from the platform711_2on the master side to the other platforms711_1and711_3to711_8on the master side is written. The ninth region Slot #8 to the sixteenth region Slot #15 are each a region where data to be transmitted from the platform711_2on the master side to the platforms712_1to712_8on the slave side connected to the second relay device102is written.

The same configuration as above applies to the other common memories CM3to CM16, so that the description thereof is omitted. One of the regions of the common memory is a region where data to be received from another platform is written, and the other regions of the shared memory are regions where data to be transmitted to the other platforms is written.

In the configuration described above, when any of the platforms writes data to be transmitted to another platform into a predetermined address of a corresponding region, the address of the region into which the data is written is given to the bus control processor104via a device driver.

The bus control processor104discriminates the common memory of the platform as a transfer destination of the written data based on the given address of the region. Then, the bus control processor104transfers the data and writes the data into the address of the corresponding region (that is, the same address as the address of the region into which the data is written by the platform as a transmission source). In this control, the virtual MAC address is used as the transmission source and the transmission destination of the platform. A method of transmitting the data that is actually performed is the same as that in the embodiment, and the description thereof is omitted.

In the present modification, a result of an arithmetic processing performed by each platform can be read out from the common memory, so that transmission and reception of the data are facilitated.

In the embodiment and the modification, while the first relay device101to which the main unit111and the platforms112on the master side includes the root complex (RC) for relay106, the second relay device102includes the end point (EP) for relay107. However, the embodiment and the modification are not limited to such a configuration. For example, it is possible to employ a configuration in which the end point (EP) for relay107is provided to the first relay device101to which the main unit111and the platforms112on the master side while the root complex (RC) for relay106is provided to the second relay device102.

In addition, the correspondence between the first/second relay devices defined in Claims and those in the embodiment is not fixed but is flexible. For example, it is possible to interpret that the first relay device101in the embodiment corresponds to the second relay device in Claims while the second relay device102in the embodiment corresponds to the first relay device in Claims.

With the information processing system according to the embodiment and the modification described above, when communication is performed between the information processing devices that are connected to each other via the relay devices, the address conflict between the virtual MAC addresses can be prevented by assigning the virtual MAC addresses based on the relation between the relay devices. Thus, appropriate communication processing can be implemented between the information processing devices connected via the relay devices.