PACKAGING MODULE AND ELECTRONIC DEVICE

A packaging module includes a substrate layer disposed in a stacking manner, and a plurality of chip layers stacked on the substrate layer. The plurality of chip layers include a top chip layer, and the top chip layer is a chip layer furthest from the substrate layer in the plurality of chip layers. The top chip layer includes a first chip, a connection surface of the first chip faces the substrate layer, and the connection surface of the first chip is conductively connected to a chip of an adjacent chip layer by using a first conductor. The connection surface of the first chip faces the substrate layer, so that the first conductor connected to the first chip and another chip does not occupy additional space, to reduce the thickness of the packaging module, and facilitate miniaturization of the packaging module.

TECHNICAL FIELD

This disclosure relates to the field of chip packaging technologies, and in particular, to a packaging module and an electronic device.

BACKGROUND

A semiconductor device is widely used in electronic devices such as a mobile phone and a smartwatch, and is used as a main electronic component of the electronic devices. With thinning development of the electronic device, a size of a packaging module becomes a main factor restricting further thinning of the electronic device.

With continuous development of the semiconductor industry, a size of the semiconductor device is becoming smaller and a density of internal electronic components of the semiconductor device is becoming higher. In addition, a plurality of semiconductor devices are stacked and packaged to form a packaging module, to further reduce occupied space. However, for a system-level packaging module in the electronic device, because the system-level packaging module needs to carry a relatively large quantity of chips, and a relatively large quantity of substrates are used when the chips are carried, the packaging module cannot further implement miniaturization, and a miniaturization requirement of an existing electronic device cannot be met.

SUMMARY

This disclosure provides a packaging module and an electronic device, to improve a size of the packaging module and facilitate miniaturization development of the packaging module.

According to a first aspect, a packaging module is provided. The packaging module includes a substrate layer disposed in a stacking manner, and a plurality of chip layers stacked on the substrate layer. The substrate layer serves as a supporting structure to support the plurality of chip layers. In addition, the substrate layer is also provided with a circuit layer, to be conductively connected to the chip layer, thereby implementing a function of the packaging module. The plurality of chip layers include a top chip layer, and the top chip layer is a chip layer furthest from the substrate layer in the plurality of chip layers. The top chip layer includes a first chip, a connection surface of the first chip faces the substrate layer, and the connection surface of the first chip is conductively connected to a chip of an adjacent chip layer by using a first conductor. In the foregoing technical solution, all chips are supported by one substrate (the substrate layer), to reduce a quantity of used substrates, and further reduce a thickness of the packaging module. In addition, the connection surface of the first chip faces the substrate layer, so that the first conductor connected to the first chip and another chip does not occupy additional space, to reduce the thickness of the packaging module, and facilitate miniaturization of the packaging module.

In a specific possible implementation, a connection surface of the chip of the adjacent chip layer faces the substrate layer, one end of the first conductor is connected to the connection surface of the first chip, and the other end thereof is connected to the connection surface of the chip of the adjacent chip layer. Therefore, disposition of the first conductor is facilitated.

In a specific possible implementation, the first conductor is located on a side of the first chip facing the substrate layer. This reduces an impact of the first conductor on a height of the packaging module.

In a specific possible implementation, the connection surface of the first chip is provided with an exposed connection area relative to an upper surface of the chip of the adjacent chip layer, and one end of the first conductor is connected to the exposed connection area. Therefore, disposition of the first conductor is facilitated.

In a specific possible implementation, the connection area of the first chip is located in an edge area or a middle area of the connection surface of the first chip. Therefore, disposition of the first conductor is facilitated.

In a specific possible implementation, the conductor is a bonding wire, to facilitate connection between chips of different layers.

In a specific possible implementation, the adjacent chip layer is closer to the substrate layer than the top chip layer, and the adjacent chip layer includes one or more chips. A connection surface or connection surfaces of the one or more chips faces or all face the substrate layer and is or are conductively connected to a circuit layer of the substrate layer. The connection surface of the first chip is connected to any one of the connection surface or the connection surfaces of the one or more chips by using one first conductor. Two chip layers are used to implement a function of the packaging module.

In a specific possible implementation, the adjacent chip layer includes a plurality of chips, and the plurality of chips include a second chip and a third chip. Connection surfaces of the second chip and the third chip both face the substrate layer, and the second chip and the third chip are separately conductively connected to the circuit layer of the substrate layer. The first chip is conductively connected to the second chip by using the first conductor; or the first chip is conductively connected to the second chip by using one first conductor, and the first chip is conductively connected to the third chip by using another first conductor. Two chip layers are used to implement the function of the packaging module.

In a specific possible implementation, the adjacent chip layer includes a plurality of chips, and the plurality of chips include a fourth chip and a fifth chip. A connection surface of the fourth chip faces the substrate layer, and the connection surface of the first chip is conductively connected to the connection surface of the fourth chip by using the first conductor. A connection surface of the fifth chip faces away from the substrate layer, and the connection surface of the fifth chip is conductively connected to the circuit layer of the substrate layer by using a second conductor. Two chip layers are used to implement the function of the packaging module.

In a specific possible implementation, the substrate layer is provided with an avoidance groove for avoiding the first conductor. A thickness of the packaging module is further reduced.

In a specific possible implementation, the plurality of chip layers further include a bottom chip layer, the bottom chip layer is a chip layer closest to the substrate layer, and the adjacent chip layer is located between the bottom chip layer and the top chip layer.

A chip located at the adjacent chip layer includes a sixth chip, and a connection surface of the sixth chip faces the substrate layer. A chip located at the bottom chip layer includes a seventh chip, and a connection surface of the seventh chip faces the substrate layer and is conductively connected to a circuit layer of the substrate layer. The connection surface of the sixth chip is conductively connected to the connection surface of the first chip by using one first conductor, and is conductively connected to the connection surface of the seventh chip by using another first conductor. Three chip layers are used to implement the function of the packaging module.

In a specific possible implementation, the packaging module further includes an embedded chip disposed at the substrate layer, and the embedded chip is conductively connected to the circuit layer of the substrate layer. The thickness of the packaging module is further reduced.

In a specific possible implementation, the plurality of chip layers further include a bottom chip layer, the bottom chip layer is a chip layer closest to the substrate layer, and the adjacent chip layer is located between the bottom chip layer and the top chip layer.

A chip located at the adjacent chip layer includes an eighth chip, and a connection surface of the eighth chip faces the substrate layer. A chip located at the bottom chip layer includes a ninth chip, and a connection surface of the ninth chip faces the substrate layer and is conductively connected to a circuit layer of the substrate layer. The connection surface of the first chip is conductively connected to the connection surface of the eighth chip by using the first conductor, and the connection surface of the ninth chip is conductively connected to the circuit layer of the substrate layer by using a third conductor. Three chip layers are used to implement the function of the packaging module.

In a specific possible implementation, adjacent chip layers in the plurality of chip layers are bonded. This facilitates fastening between chip layers.

In a specific possible implementation, the packaging module further includes a packaging layer that packages the plurality of chip layers. This improves chip security.

According to a second aspect, an electronic device is provided, and the electronic device includes a housing and the packaging module according to any one of the foregoing implementations disposed in the housing. In the foregoing technical solution, all chips are supported by one substrate (the substrate layer), to reduce a quantity of used substrates, and further reduce the thickness of the packaging module. In addition, the connection surface of the first chip faces the substrate layer, so that the first conductor connected to the first chip and another chip does not occupy additional space, to reduce the thickness of the packaging module, and facilitate miniaturization of the packaging module.

DESCRIPTION OF EMBODIMENTS

The following further describes the embodiments of this disclosure with reference to the accompanying drawings.

To facilitate understanding of a packaging module provided in embodiments of this disclosure, an application scenario of the packaging module is first described.

The packaging module provided in the embodiments of this disclosure is applied to an electronic device such as a mobile phone or a smartwatch.FIG.1is a schematic diagram of a structure of a packaging module applied to an electronic device. The electronic device includes a housing100and a main board200disposed in the housing100. A packaging module300is fastened on the main board200and is conductively connected to the main board200.

A conventional system-level packaging module is shown inFIG.2. The packaging module includes a first substrate1and a second substrate2that are stacked, and the first substrate1and the second substrate2are connected by using a solder ball. The first substrate1carries a chip6, and the chip6is connected to the first substrate1by using a solder ball and is located between the first substrate1and the second substrate2. The second substrate2carries a chip3and a chip4that are stacked and a packaging layer5that packages the chip3and the chip4. The chip3and the chip4are disposed in a positive mounting manner. To be specific, a connection surface of the chip3and a connection surface of the chip4are located on an upper surface of a chip (a surface of the chip facing away from the second substrate2). In this embodiment of this disclosure, a connection surface of a chip refers to a surface on which the chip is provided with a solder pad or a window used for conductive connection to another chip or a circuit layer. When the chip3and the chip4are connected to the second substrate2, the connection surfaces of the chip3and the chip4are connected to the second substrate2separately by using a bonding wire7. It can be seen fromFIG.2that, the packaging module in the conventional technology includes at least two substrates (the first substrate1and the second substrate2), and a height of the bonding wire7needs to be reserved along a height direction of the packaging module. With miniaturization development of an electronic device, internal space of the electronic device is also gradually reduced. As a result, the packaging module in the conventional technology is not applicable to a miniaturized electronic device, and becomes a main factor restricting further miniaturization of the electronic device. Therefore, an embodiment of this disclosure provides a packaging module, to further miniaturize the packaging module by improving a combination manner of chips in the packaging module. The following describes in detail the packaging module provided in the embodiments of this disclosure with reference to specific accompanying drawings.

The packaging module provided in the embodiments of this disclosure is a system-level packaging module, and the system-level packaging module may include chips with different functions such as a CPU (central processing unit), SOC (system-on-chip), a DRAM (dynamic random access memory), and an NAND (NAND flash memory).

FIG.3is a schematic diagram of a cross section of a packaging module according to an embodiment of this disclosure. The packaging module includes a substrate layer10and a plurality of chip layers, and layer structures of the packaging module are named for ease of description. The plurality of chip layers of the packaging module include a top chip layer30and a bottom chip layer20. The top chip layer30is a chip layer furthest from the substrate layer10in the plurality of chip layers, and the bottom chip layer20is a chip layer closest from the substrate layer10in the plurality of chip layers. In a structure shown inFIG.3, the substrate layer10, the bottom chip layer20, and the top chip layer30are stacked in a vertical direction (the vertical direction may also be referred to as a thickness direction of the packaging module, and the thickness direction of the packaging module is the same as that of the substrate layer10). The bottom chip layer20is an adjacent chip layer of the top chip layer30. In addition, the bottom chip layer20is closer to the substrate layer10than the top chip layer30.

The substrate layer10serves as a structure for carrying the top chip layer30and the bottom chip layer20. In addition, the substrate layer10is further used to implement conductive connection between an external circuit and chips of the top chip layer30and the bottom chip layer20. For example, a circuit layer is separately disposed on a surface of the substrate layer10and inside the substrate layer10, and the circuit layer on the surface of the substrate layer10and the circuit layer inside the substrate layer10may be electrically connected by using a via.

In an optional solution, an embedded chip is disposed in the substrate layer10, and the embedded chip is electrically connected to the circuit layer on the surface of the substrate layer10or the circuit layer embedded in the substrate layer10by using a via or a first conductor a.FIG.3shows two embedded chips: a first embedded chip11and a second embedded chip12. The first embedded chip11and the second embedded chip12are conductively connected to the circuit layer of the substrate layer10by using a via. It should be understood that, although two embedded chips are shown inFIG.3, a quantity of embedded chips is not specifically limited in the packaging module provided in this embodiment of this disclosure, and the quantity of embedded chips may be one, three, or the like.

In an optional solution, the substrate layer10may be a printed circuit board or another type of circuit board.

The bottom chip layer20is a layer structure formed by chips disposed at a same layer. For example, a chip of the bottom chip layer20includes one or more chips. The one or more chips are chips used to connect to a first chip31of the top chip layer. As shown inFIG.3, for example, the bottom chip layer20includes a second chip21and a third chip22. When the chip of the bottom chip layer20is disposed, a connection surface or connection surfaces of the one or more chips faces or all face the substrate layer10and is or are conductively connected to the circuit layer of the substrate layer10. For example, a connection surface of the second chip21faces the substrate layer10, and is conductively connected to the circuit layer of the substrate layer10by using a solder ball. A connection surface of the third chip22faces the substrate layer10, and the connection surface of the third chip22is conductively connected to the circuit layer of the substrate layer10. During assembly, the connection surface of the second chip21is conductively connected to the circuit layer of the substrate layer10by using a solder ball, and the connection surface of the third chip22is conductively connected to the circuit layer of the substrate layer10by using a solder ball. The second chip21and the third chip22may be electrically connected to the embedded chip (the first embedded chip or the second embedded chip) by using the circuit layer of the substrate layer10.

It should be understood that the packaging module provided in this embodiment of this disclosure does not limit a quantity of chips of the bottom chip layer20, and different quantities of chips may be disposed as required. For example, the quantity of chips of the bottom chip layer20is one, two, or three.

The top chip layer30is a layer structure formed by chips disposed at a same layer. The top chip layer30includes the first chip31. InFIG.3, for example, the top chip layer30includes one first chip31. The first chip31, the second chip21, and the third chip22are stacked. A connection surface of the first chip31faces the substrate layer10, and the connection surface of the first chip31is conductively connected to the connection surface of the second chip21by using the first conductor a. To be specific, one end of the first conductor a is connected to the connection surface of the first chip31, and the other end thereof is connected to a connection surface of a chip (the second chip21) of an adjacent chip layer. For example, the first conductor a may be a bonding wire or another type of conducting wire.

Still referring toFIG.3, when being disposed, the first conductor a is disposed on a side of the first chip31facing the substrate layer10, and a highest point of the first conductor a is lower than an upper surface of the first chip31(a surface facing away from the substrate layer10).

When the first chip31is connected to the second chip21, the connection surface of the first chip31is separately bonded, by using an adhesive, to an upper surface that is of the second chip21and that faces away from the connection surface and an upper surface that is of the third chip22and that faces away from the connection surface. The connection surface of the first chip31is provided with an exposed connection area311relative to the second chip21and the third chip22. One end of the first conductor a is connected to the connection area311. As shown inFIG.3, for example, the connection area311is located in an edge area of the connection surface of the first chip31. Therefore, disposition of the first conductor a is facilitated.

The packaging module provided in this embodiment of this disclosure further includes a packaging layer40. The packaging layer40wraps the bottom chip layer20, the top chip layer30, the first conductor a between the bottom chip layer20and the top chip layer30, and the solder ball used for connecting the bottom chip layer20to the substrate layer10, to protect a component such as the chip in the packaging module.

To facilitate understanding of the packaging module provided in this embodiment of this disclosure, the following describes in detail preparation steps of the packaging module.

Step 1: Attach the first chip31to a carrying plate400.

Referring toFIG.4a, the carrying plate400may be prepared by using a material such as metal, glass, or silicon. The carrying plate400is covered with a layer of film adhesive material, and this layer of material is used to fasten the first chip31. The film adhesive material may be a light sensitive or thermosensitive material. After being lit by ultraviolet light or under a specific heating condition, an adhesive force of the material is greatly reduced, to facilitate an interface separation operation later. When the first chip31is fastened on the carrying plate400, the connection surface of the first chip31faces away from the carrying plate400. A thickness range of the first chip31may be 25 μm to 400 μm. For example, a thickness of the first chip31may be 25 μm, 50 μm, 80 μm, or 400 μm.

Step 2: Attach the third chip22and the second chip21to the first chip31.

Referring toFIG.4b, an adhesive material is provided at a bottom of the third chip22and a bottom of the second chip21, and is used to bond and fasten the third chip22and the second chip21on the first chip31. A surface of the third chip22and a surface of the second chip21each are provided with a solder pad structure (not shown in the figure), to be connected to the circuit layer of the substrate layer. When the third chip22and the second chip21are fastened to the first chip31, a solder pad (a structure on the connection surface) of the third chip22and a solder pad of the second chip21face away from the first chip31. The second chip21, the third chip22, and the first chip31form a stack chip.

A bonding material used for bonding between the third chip22and the second chip21and the first chip31may be cured at a specific temperature or in an ultraviolet environment. The thickness of the first chip31is set to be the same as a thickness of the second chip21. For example, a thickness range of each of the third chip22and the second chip21is 25 μm to 400 μm. For example, the thickness of the second chip21and a thickness of the third chip22each are 25 μm, 50 μm, 80 μm, or 400 μm.

Step 3: Connect the first chip31and the second chip21by using a bonding wire.

Referring toFIG.4c, a wire bonding process is used to implement bonding wire connection on the connection surface of the first chip31and the solder pad of the second chip21. Wire bonding refers to tightly welding a metal lead and a substrate solder pad by using a fine bonding wire through heat, pressure, and ultrasonic energy. A gold, copper, or alloy bonding wire may be used as the foregoing bonding wire, and a diameter of the bonding wire may be 18 μm to 30 μm. For example, the diameter of the bonding wire is 18 μm, 25 μm, or 30 μm.

Step 4: Take out the stack chip from the carrying plate400and place the stack chip upside down.

Referring toFIG.4d, the adhesive force of the film adhesive material on the carrying plate400is greatly reduced because of ultraviolet light or heating, and then the second chip21and an upper surface of the second chip21are suctioned by a vacuum rubber suction nozzle. The vacuum rubber suction nozzle is driven up by a lifting device to separate the first chip31from the carrying plate400, and a stack chip structure is placed on a temporary carrying table500upside down.

Step 5: Manufacture the substrate layer10, and implant a metal bump13on the surface of the substrate layer10.

Referring toFIG.4e, the substrate layer10is implemented by using a fan-out molding technology or a panel level package technology. The substrate layer10is embedded with the first embedded chip11and the second embedded chip12, and the first embedded chip11and the second embedded chip12implement a rewiring structure on the surface of the substrate layer10by using the circuit layer and the via respectively, to fan out a connection end of the first embedded chip11and a connection end of the second embedded chip12. The circuit layer on the surface of the substrate layer10includes a solder pad structure, and the metal bump13is implanted into the solder pad structure to connect to the main board or another circuit structure. The circuit layer on the surface of the substrate layer10may be made of a copper material, a material of the solder pad structure may use copper, and a material of the bump on the solder pad may use copper or tin.

When the metal bump13is prepared onto the substrate layer10, the metal bump13is implanted into the solder pad structure by printing or electroplating. A height of the metal bump13may be 20 μm to 70 μm. For example, the height of the metal bump13is 20 μm, 40 μm, or 70 μm.

Step 6: Bond the stack chip structure with the substrate layer10by using the metal bump.

Referring toFIG.4f, the stack chip structure and the substrate layer10are placed together, so that the metal bump is aligned with a pad corresponding to the third chip22and a pad corresponding to the second chip21. The metal bump is metal bonded with the pad on the third chip22and the pad on the second chip21through a reflow soldering process or a hot press-fitted process. In the foregoing preparation process, a temperature is risen through the reflow soldering process and the hot press-fitted process to melt solder and melt bond the solder with a material of the metal bump.

Step 7: Plastically package an entire packaging structure and implant a solder ball into the substrate layer10.

Referring toFIG.4g, an entire chip structure may be packaged by using a molding tool and a thermosetting material, and a packaging material is cured by heating to form the packaging layer40. Finally, the solder ball is implanted into a lower surface of the substrate layer10, and the solder ball may be implanted through solder printing and reflow soldering.

It can be learned from the foregoing description that, in the packaging module provided in this embodiment of this disclosure, the first chip31is inverted (the connection surface of the first chip31faces the substrate layer10), so that a height value of the first conductor a for connecting the first chip31to the second chip21may be within a thickness range of the second chip21, and no additional height is required. Therefore, the packaging module can be thinner.

To facilitate understanding of a thinning effect of the packaging module provided in this embodiment of this disclosure, the packaging module provided in this embodiment of this disclosure is compared with the packaging module in the conventional technology shown inFIG.2.

In this embodiment of this disclosure, the chip shown inFIG.2is disposed in a positive mounting manner, and connection surfaces of the chips (the chip3and the chip4) face away from the substrate layer. Therefore, when the chip is connected to the second substrate, the bonding wire needs to be routed out from a top of the chip4. When the bonding wire is routed, a necessary bending radian needs to be reserved, and a thickness from the packaging layer5to a top chip (the chip4) should reach at least 100 μm, to cover the bonding wire. However, in the packaging module provided in this embodiment of this disclosure, because the connection surface of the first chip faces the substrate layer, the bonding wire is disposed toward the substrate layer. Although a bending radian needs to be reserved when the bonding wire is connected to a chip of the bottom chip layer, space occupied by bending of the bonding wire overlaps space of the solder ball used for welding the bottom chip layer and the substrate layer, so that no additional space is required. It can be seen fromFIG.3of this disclosure that, a highest point (a point connected to the connection surface of the first chip) of the bonding wire along a chip stacking direction is lower than the upper surface of the first chip, to effectively lower a limitation on a thickness from the packaging layer to a top surface of the first chip. Therefore, the packaging module can be thinner, and a size of the packaging module is minimized.

In addition, the system-level packaging module in the conventional technology includes two substrates (the first substrate1and the second substrate2), so that a packaging thickness of the packaging module is increased. However, in this embodiment of this disclosure, some chips (the first embedded chip11and the second embedded chip12) are disposed in an embedding manner, and other chips (the first chip31, the second chip21, and the third chip22) are directly bonded with the substrate layer10. This saves a thickness of one substrate component compared with the system-level packaging module shown inFIG.2, and reduces an overall thickness of the packaging module. In addition, by using a direct bonding manner of the chip and the substrate layer, more I/O (input/output) connections can be implemented compared with the conventional system-level packaging module, to increase connection bandwidth between chips of the system-level packaging module or reduce power consumption.

It can be learned from the foregoing description that, compared with the packaging module in the conventional technology, the packaging module disclosed in this embodiment of this disclosure can greatly reduce a packaging occupation height. For example, in the conventional technology, an occupation height of a packaging layer in a stacking packaging module of a processor chip of a mobile phone is about 1.2 mm, and an occupation height of a packaging layer in a stacking packaging module of a processor of a smartwatch is about 0.8 mm. However, a thickness of the packaging layer in the packaging module provided in this embodiment of this disclosure is only about 0.5 mm In addition, compared with a solution in the conventional technology in which the packaging module uses two substrates, in the packaging module provided in this embodiment of this disclosure, when a chip is directly connected to the substrate layer, a quantity of I/O interconnections of chips inside the packaging module can be increased. For example, in the conventional technology, a quantity of I/O connections between a CPU and upper-layer DRAM packaging in a stacking packaging module is about 200, and a quantity of I/O connections between an embedded chip and an upper-layer chip that are of the substrate layer provided in this embodiment of this disclosure is greater than 500. This greatly increases the quantity of I/O connections, and further increases connection bandwidth or reduces power consumption.

FIG.5shows a variant structure based on the packaging module shown inFIG.3. The second chip21and the third chip22are located at the bottom chip layer20, and the first chip31is located at the top chip layer30. For connection manners of the second chip21and the third chip22and the substrate layer10, refer to related descriptions inFIG.3. Details are not described herein again.

The substrate layer10may also be provided with an avoidance groove14for avoiding the bonding wire, and the avoidance groove14is located on a surface of the substrate layer10facing the second chip. A disposed location, width, and depth of the avoidance groove14may be matched based on a location and a size of a bending structure of a bonding wire a connected to the first chip31and the second chip21. This is not specifically limited in this embodiment of this disclosure.

In addition, a quantity of avoidance grooves14is not specifically limited in this embodiment of this disclosure, and the quantity may match a quantity of bonding wires a, or the quantity of avoidance grooves14is less than the quantity of bonding wires a. During arrangement, one avoidance groove14may accommodate a bending structure of one bonding wire a, or one avoidance groove14accommodates bending structures of a plurality of bonding wires a. During specific disposition, a location of the avoidance groove14and the quantity of avoidance grooves14may be flexibly arranged based on metal routing of the circuit layer on the surface of the substrate layer10, to prevent a disposed avoidance groove14from affecting the metal routing of the circuit layer.

It can be seen fromFIG.5that, when the avoidance groove14is disposed, a size of the packaging module can be further reduced, so that the solder ball connecting the second chip21and the third chip22to the substrate layer10can have a smaller size, to further reduce a height of the packaging module. In addition, the avoidance groove14is disposed, so that the bonding wire has larger space for bending. This ensures reliability of the bonding wire after being bent.

FIG.6shows another variant structure based on the packaging module shown inFIG.3. The second chip21and the third chip22are located at the bottom chip layer20, and the first chip31is located at the top chip layer30. For connection manners of the second chip21and the third chip22and the substrate layer10, refer to related descriptions inFIG.3. Details are not described herein again.

In a packaging structure shown inFIG.6, the second chip21and the third chip22of the packaging module are separately connected to a middle area of the first chip31. As can be seen fromFIG.6, the connection area311of the first chip31is located in the middle area of the connection surface of the first chip31, the second chip21and the third chip22are arranged at intervals, and space for exposing the connection area311is disposed at intervals between the second chip21and the third chip22. When the first chip31is connected to the second chip21and the third chip22, the first chip31is conductively connected to the second chip21by using one first conductor, and the first chip31is conductively connected to the third chip22by using another first conductor.

The first conductor uses a bonding wire. For example, a bonding wire b and a bonding wire c are located in a gap between the second chip21and the third chip22. When the packaging structure shown inFIG.6is used, space for accommodating the bonding wire b and the bonding wire c is formed between the second chip21and the third chip22by utilizing a difference in a size of the first chip31, a size of the second chip21, and a size of the third chip22. Therefore, the bonding wire b and the bonding wire c do not affect a size of the packaging module in a horizontal direction (a direction B shown inFIG.6). This further reduces the size of the packaging module, and facilitates miniaturization of the packaging module.

In addition, the packaging module shown inFIG.6may also use the avoidance groove shown inFIG.5. To be specific, an avoidance groove matching the bonding wire b and the bonding wire c may also be disposed on the substrate layer10of the packaging module shown inFIG.6, to further reduce a height of the packaging module.

FIG.7shows a packaging module obtained by a variation based on the packaging module shown inFIG.3. For some reference numerals inFIG.7, refer to the same reference numerals inFIG.3. A fourth chip23and a fifth chip24are located at the bottom chip layer20, and the first chip31is located at the top chip layer30.

In the packaging module shown inFIG.7, routed-out surfaces of some chips of the bottom chip layer20face the substrate layer10. As shown inFIG.7, a routed-out surface of the fourth chip23faces the substrate layer10. For a connection manner of the fourth chip23and the substrate layer10, refer to related descriptions of the second chip21and the substrate layer10inFIG.3. Details are not described herein again. When the fifth chip24is disposed, the fifth chip24is bonded with the substrate layer10, and a connection surface of the fifth chip24faces away from the substrate layer10. The connection surface of the fifth chip24is conductively connected to the circuit layer of the substrate layer10by using a second conductor. For example, the second conductor may use a bonding wire d.

When the first chip31and the fifth chip24are disposed, the fifth chip24and the first chip31are disposed in a staggered manner, so that the connection surface of the fifth chip24is exposed at an outer side of the first chip31, and the bonding wire d is connected to a part of the connection surface of the fifth chip24exposed at the outer side of the first chip31.

In an optional solution, a height of the bonding wire d is lower than a height of a surface of the first chip31facing away from the substrate layer10, to prevent the disposed bonding wire d from affecting a height of the packaging module.

FIG.8shows another variant structure based on the packaging module shown inFIG.3. For some reference numerals inFIG.8, refer to the same reference numerals inFIG.3. A plurality of chip layers include the top chip layer30, a middle chip layer50, and the bottom chip layer20. The bottom chip layer20is a chip layer closest to the substrate layer. The middle chip layer50is a chip layer located between the bottom chip layer20and the top chip layer30, and the middle chip layer50is a chip layer adjacent to the top chip layer30. The top chip layer30includes the first chip31, and the middle chip layer includes a sixth chip51. A connection surface of the sixth chip51faces the substrate layer10, and the bottom chip layer20includes a seventh chip25and a tenth chip26. A connection surface of the seventh chip25and a connection surface of the tenth chip26face the substrate layer10and are conductively connected to the circuit layer of the substrate layer10.

For connection manners of the seventh chip25and the tenth chip26of the bottom chip layer20and the substrate layer10, refer to the connection manners of the second chip21and the third chip22and the substrate layer10shown inFIG.3. Details are not described herein again.

The connection surface of the sixth chip51is separately conductively connected to the connection surface of the first chip31and the connection surface of the seventh chip25by using first conductors. As shown inFIG.8, the first conductor is a bonding wire e and a bonding wire f. The first chip31and the sixth chip51are connected by using the bonding wire e, and the sixth chip51and the seventh chip25are connected by using the bonding wire f. For a specific connection manner, refer to the manner in which the first chip31and the second chip21are connected by using the bonding wire a inFIG.3. Details are not described herein again.

FIG.9shows another variant structure based on the packaging module shown inFIG.3. In the structure shown inFIG.9, it may be understood as that the embedded chip of the substrate layer10shown inFIG.3is disposed on a surface of the substrate layer.

InFIG.9, a plurality of chip layers include the top chip layer30, the middle chip layer50, and the bottom chip layer20. The bottom chip layer20is a chip layer closest to the substrate layer. The middle chip layer50is a chip layer located between the bottom chip layer20and the top chip layer30, and the middle chip layer50is a chip layer adjacent to the top chip layer20. The bottom chip layer20includes a ninth chip27and an eleventh chip28, the middle chip layer50includes an eighth chip52and a twelfth chip53, and the top chip layer30includes the first chip31.

For connection manners of the ninth chip27and the eleventh chip28of the bottom chip layer20and the substrate layer10, refer to the connection manners of the second chip21and the third chip22and the substrate layer10shown inFIG.3. Details are not described herein again.

A connection surface of the ninth chip27and a connection surface of the eleventh chip28both face the substrate layer10. The ninth chip27and the eleventh chip28are conductively connected to the circuit layer of the substrate layer10by using a solder pad. In addition, the ninth chip27and the eleventh chip28are spaced at intervals, to reserve routing space for conductive connection between another chip and the circuit layer of the substrate layer10.

The eighth chip52of the middle chip layer50and the ninth chip27are bonded by adhesive. The eighth chip52and the ninth chip27are disposed in a staggered manner, so that the eighth chip52is partially exposed outside the ninth chip27. A connection surface of the eighth chip52faces the substrate layer10, and a part of the connection surface of the eighth chip52exposed outside the ninth chip27is conductively connected to the circuit layer of the substrate layer10by using a conductive column h. The twelfth chip53is bonded with the ninth chip27and the eleventh chip28by adhesive. The twelfth chip53and the eleventh chip28are disposed in a staggered manner, so that the twelfth chip53is partially exposed outside the eleventh chip28. A connection surface of the twelfth chip53faces the substrate layer10, and a part of the connection surface of the twelfth chip53exposed outside the ninth chip27and the eleventh chip28is conductively connected to the circuit layer of the substrate layer10by using a conductive column (a third conductor). As shown inFIG.9, the twelfth chip53is conductively connected to the circuit layer of the substrate layer10by using a conductive column j and a conductive column i separately. It should be understood that a conductive connection manner of the twelfth chip53and the circuit layer of the substrate layer10shown inFIG.9is merely a specific example manner. In actual production, a routing design may be implemented based on a specific location of a chip.

The top chip layer30includes the first chip31, and the first chip31is separately bonded with the eighth chip52and the twelfth chip53by adhesive. In addition, the first chip31and the eighth chip52are disposed in a staggered manner, so that the first chip31is partially exposed outside the eighth chip52. The connection surface of the first chip31faces the substrate layer10, and a part of the connection surface of the first chip31exposed outside the eighth chip52is conductively connected to the connection surface of the eighth chip52by using a bonding wire g (the first conductor).

It should be understood that, although the foregoing example shows that different chip layers include one or two chips, in this embodiment of this disclosure, a quantity of chips of each chip layer is not specifically limited, and different quantities of chips may be selected based on an actual situation.

It can be learned from the structure of the packaging module shown inFIG.9that, in the packaging module provided in this embodiment of this disclosure, a chip of a top layer is inverted, so that a conductor for a conductive connection between the chip of the top layer and a chip of another layer does not occupy space of the packaging module. A size of the packaging module is reduced. In addition, although the packaging module shown inFIG.9does not use an embedded chip, the packaging module shown inFIG.9reduces a quantity of used substrates compared with the packaging module shown inFIG.2. This also reduces the size of the packaging module.

An embodiment of this disclosure further provides an electronic device such as a mobile phone or a smartwatch. A structure of the electronic device shown inFIG.1is used as an example. The electronic device includes the housing100and the main board200disposed in the housing100. The packaging module300is fastened on the main board200and is conductively connected to the main board200. When the packaging module300uses the packaging module in the foregoing example, all chips are supported by one substrate (a substrate layer), to reduce a quantity of used substrates, and further reduce a thickness of the packaging module. In addition, a connection surface of a first chip faces the substrate layer, so that a first conductor connected to the first chip and another chip does not occupy additional space, to reduce the thickness of the packaging module, and facilitate miniaturization of the packaging module.

A person skilled in the art can make various modifications and variations to this disclosure without departing from the scope of this disclosure. This disclosure is intended to cover these modifications and variations of this disclosure provided that the modifications and variations fall within the scope of protection defined by the following claims and their equivalent technologies.