Systems and methods for reducing memory array leakage in high capacity memories by selective biasing

A source-biasing mechanism for leakage reduction in SRAM in which SRAM cells are arranged into a plurality of sectors. In standby mode, the SRAM cells in a sector in the plurality of sectors are deselected and a source-biasing potential is provided to the SRAM cells of the plurality sectors. In working mode, the source-biasing potential provided to the SRAM cells of a selected sector in the plurality of sectors is deactivated and the SRAM cells in a physical row within the selected sector are read while the remaining SRAM cells in the unselected sectors continue to be source-biased. The source-biasing potential provided to the SRAM cells that are in standby mode can be set to different voltages based on the logical state of control signals.

The present disclosure relates generally to semiconductor memories. More particularly, and not by way of any limitation, the present disclosure is directed to a sector-based source-biasing scheme for reducing leakage in static random access memory (SRAM) cells.

Static random access memory or SRAM devices comprising a plurality of memory cells are typically configured as an array of rows and columns, with one or more I/Os (e.g., ×4, ×8, ×16, etc. configurations). Also, such memories may be provided in a multi-bank architecture for applications where high density, high speed and low power are required. Regardless of the architecture and type, each SRAM cell is operable to store a single bit of information. Access to this information is facilitated by activating all memory cells in a given physical row (by driving a wordline associated therewith) and outputting the data onto bitlines associated with a selected column for providing the stored data value to the selected output. Once the data is disposed on the bitlines, voltage levels on the bitlines begin to separate to opposite power supply rails (e.g., VDDand ground), and a sense amplifier is utilized to latch the logic levels sensed on the bitlines after they are separated by a predetermined voltage difference, typically ten percent or less of VDD. Furthermore, the sense amplifier may be provided as a differential sense amplifier, with each of the memory cells driving both a data signal and a data-bar signal on the complementary bitlines (e.g., data lines) associated with each column. In operation, prior to activating the memory cells, the bitlines are precharged and equalized to a common value. Once a particular row and column are selected, the memory cell corresponding thereto is activated such that it pulls one of the data lines toward ground, with the other data line remaining at the precharged level, typically VDD. The sense amplifier coupled to the two complementary bitlines senses the difference between the two bitlines once it exceeds a predetermined value and the sensed difference is indicated to the sense amplifier as the differing logic states of “0” and “1”.

As the transistor device sizes continue to decrease, e.g., 0.13 microns or smaller, several issues begin to emerge with respect to the operation of SRAM cells, chiefly because at such dimensions the devices suffer from high values of leakage in the off state in standby mode. Essentially, these devices are no longer ideal switches; rather they are closer to sieves, having a non-negligible constant current flow path from drain to source or from drain/source to substrate even in the off state. The high leakage causes two major problems. First, because of the generation of large static current as leakage, there is increased static power consumption as a result. Second, which is more serious, is the issue of incorrect data reads from the SRAM cells. The accumulated leakage current from all the bitcells in a selected column is now comparable to the read current, thereby significantly eroding the bitline differential required for reliable sensing operations.

A technique for reducing standby leakage currents in a SRAM cell is disclosed in “16.7 fA/cell Tunnel-Leakage-Suppressed 16 Mb SRAM for Handling Cosmic-Ray-Induced Multi-Errors” by Kenichi Osada, Yoshikazu Saitoh, Eishi Ibe and Koichiro Ishibashi (in IEEE International Solid-State Circuits Conference, 2003, pages 302 303), where the source terminals of a plurality of SRAM cells on a single bitline column are coupled together for providing a biasing potential. Whereas such a scheme is seen to reduce total standby current, it does not improve the ratio of read current (IR) to cell leakage current (IL), however.

A technique for reducing standby leakage currents in SRAM cells is also disclosed in U.S. Pat. No. 7,061,794 B1. As disclosed therein, when memory cells of a given sector are in standby mode, the write-lines to each physical row of memory cells in the sector are in a deselected state whereas the sector source lines are driven to a select potential in order to reduce memory leakage. When a memory read is activated for a given physical row in the sector, the write line associated with the desired physical row is driven high. This causes the logic associated with the desired physical row to drive the source line for the physical row low. The source lines for other physical rows in the sector are maintained at the selected (biased) potential. The voltage differentials of each of the cells in the selected physical row are sensed and the memory cells are restored to standby mode upon the commencement of another read operation for another physical row.

While the memory architectures disclosed in U.S. Pat. No. 7,061,794 B1 are very useful in their own right, they suffer some drawbacks. The disclosed memory architectures require logic for biasing each physical row in the SRAM. In particular, the decoding logic and the biasing circuit are part of the X-decoder (X-address decoder). This extra logic presents an overhead for each of the physical rows in the memory thereby causing significant overall area overhead. In other words, this extra logic takes up space on the chip that could otherwise be used for other functions, such as placement of additional memory cells. Moreover, the biasing logic in the memory architectures disclosed in U.S. Pat. No. 7,061,794 B1 are in the access path, resulting in significant speed loss. Additionally, the bias voltage used to bias cells in the memory architectures disclosed in U.S. Pat. No. 7,061,794 B1 cannot be adjusted. This represents another drawback because it has been determined that slight variances in the doping of silicon, and/or other features of silicon that affect the optimum value for preventing voltage leakage. In other words, different silicon environments dictate different bias voltages in order to minimize the amount of leakage.

Given the above-background, what are needed in the art are improved systems and methods for reducing leakage in SRAM.

Discussion or citation of a reference herein will not be construed as an admission that such reference is prior art.

Disclosed are approaches that address the drawbacks with known memory leakage techniques. Instead of removing the bias for a single physical row during a read operation, as disclosed in U.S. Pat. No. 7,061,794 B1, the bias voltage is removed from an entire sector of physical rows (e.g., 32 physical rows) that contains the physical row to be read during a given read operation. This allows for the sector decode logic and biasing logic to be placed at the top and/or bottom of the array together with the placement of ground lines vertically that get connected to the corresponding sectors inside the array. It provides significant area overhead savings since the control circuitry is just placed a few times, at most, per memory bank instead of at each physical row of each sector in the memory bank. The disclosed memory architectures have the additional advantage that the extra logic and circuitry for the sector bias scheme does not gate the memory access path. Thus, memory read operations are faster using the disclosed memory leakage techniques and circuitry.

One embodiment provides a sector-based source-biasing scheme for SRAM in order to reduce leakage. In standby mode, sectors of physical rows are deselected and a source-biasing potential is provided to SRAM cells. In read mode, a sector containing a selected physical row is deactivated (the source bias is removed) by deactivating the source-biasing potential provided to the physical rows of the selected sector, whereas the remaining SRAM cells in the remaining sectors in the memory continue to be source-biased. Source-biasing potential may be provided by applying a select voltage to the source terminal of the SRAM cells in the selected sector or by appropriately biasing the body well potential thereof.

The main idea of the source-biasing scheme is to reduce the leakage across the access devices (or, pass gates) of the bitcells (e.g., the memory cells) of the memory. Since the leakage across the pass gate is due to VDS(=supply voltage), the present disclosure is directed to reducing it by raising the potential of ground node within each bitcell. Thus, in one implementation, the ground nodes (e.g., source terminals of the pull-down devices) of bitcells the physical rows in a sector of a memory bank are connected together and maintained at around 50 to 250 millivolts. This bias voltage can vary based on the cell technology, design rules, operating voltage, chip composition, etc. When a given physical row is selected for a read operation, the ground potential for the physical rows in the sector that include the given physical row is driven to a ground voltage by using a pair of sector decoders and sector bias circuit mechanisms. During this read operation, the bitcells of other sectors in the memory bank are driven to a bias voltage thereby causing such bitcells to substantially reduce leakage because of the biasing potential that continues to be maintained. Therefore, only the bitcells in the sector containing the physical row being accessed will have leakage across their pass gates; the cells of all other cells in the remaining sectors in the memory bank will have significantly reduced leakage (due to their raised ground nodes) resulting in a read current that is significantly greater than any accumulated leakage.

In one embodiment, a static random access memory (SRAM) is provided. The SRAM comprises a plurality of sectors. Typically, these sectors are arranged into a plurality of memory banks. In one example, the SRAM comprises eight memory banks, with each memory bank comprising two sectors. Each sector in the plurality of sectors comprises a plurality of SRAM cells arranged in a plurality bitline rows and a plurality of bitline columns. Each of these bitline rows is a physical row in the sector and may contain any number of SRAM cells, meaning that they have a common write line. Thus, there may be any number of bitline columns. In one example, there are 32 bitline rows in a sector.

For each respective sector in the plurality of sectors, each SRAM cell in the plurality of SRAM cells of the respective sector includes a pair of cross-coupled inverters that are coupled to form a pair of data nodes. For each respective sector in the plurality of sectors, each SRAM cell in the plurality of SRAM cells of the respective sector includes a pull-down device. For each respective sector in the plurality of sectors, the pull-down devices of the plurality of SRAM cells of the respective sector are coupled together. The plurality of SRAM cells of the respective sector are selectively in (i) a working mode (unbiased) in which data in the plurality of SRAM cells can be accessed and in which the pull-down devices of the SRAM cells in the sector are driven to a first voltage or (ii) a standby mode (biased) in which the pull-down devices of the SRAM cells in the sector are driven by a second voltage.

The SRAM also comprises a sector decoder. The decoder is configured to identify a sector in the plurality of sectors to be selectively activated to the working mode based on a decoded sector address in a range of sector addresses. The decoder provides a sector selective no bias signal based on the decoded sector address

The SRAM also comprises a plurality of sector bias circuits. Each respective sector bias circuit in the plurality of sector bias circuits is coupled to (i) the sector decoder and (ii) a sector, in the plurality of sectors, which corresponds to the respective sector bias circuit. Each respective sector bias circuit in the plurality of sector bias circuits is selectively configured to provide the first voltage or the second voltage to the pull-down devices of the SRAM cells in the sector that is coupled to the respective sector bias circuit. The respective sector bias circuit provides the second voltage (bias voltage) to the pull-down devices of the SRAM cells in the sector that is coupled to the respective sector bias circuit when the respective sector bias circuit is not receiving the sector selective no bias signal from the sector decoder. The respective sector bias circuit provides the first voltage (working mode voltage, ground voltage) to the pull-down devices of the SRAM cells in the sector that is coupled to the respective sector bias circuit when the respective sector bias circuit is receiving the sector selective no bias signal from the sector decoder.

Another aspect of the present disclosure provides a memory operation method associated with a SRAM. The SRAM comprises a plurality of sectors, each sector in the plurality of sectors comprising a plurality of SRAM cells arranged in a plurality bitline rows and a plurality of bitline columns. For each respective sector in the plurality of sectors, each SRAM cell in the plurality of SRAM cells of the respective sector includes a pair of cross-coupled inverters that are coupled to form a pair of data nodes. For each respective sector in the plurality of sectors, each SRAM cell in the plurality of SRAM cells of the respective sector includes a pull-down device. The pull-down devices of the plurality of SRAM cells of the respective sector are coupled together.

In the memory operation method, a first sector address in a range of sector addresses for a first memory read operation is decoded thereby obtaining a first decoded sector address. The plurality of SRAM cells of a first sector in the plurality of sectors is selectively activated based on the first decoded sector address by driving pull-down devices of the plurality of SRAM cells of the first sector with a first voltage (working mode voltage, ground voltage). A data value stored at a selected SRAM cell in the first sector is read while continuing to drive pull-down devices of the plurality of SRAM cells of the first sector with the first voltage. A second sector address for a second memory read operation is decoded thereby obtaining a second decoded sector address. The plurality of SRAM cells of a second sector are selectively activated based on the second decoded sector address by driving pull-down devices of the plurality of SRAM cells of the second sector with the first voltage. The pull-down devices of the plurality of SRAM cells in the first sector are driven with a second (biasing) voltage thereby restoring the first sector to a biased state.

5 DETAILED DESCRIPTION

In the drawings, like or similar elements are designated with identical reference numerals throughout the several views thereof, and the various elements depicted are not necessarily drawn to scale.

FIG. 1illustrates a top level block diagram of a high capacity memory100structured with eight banks112, each bank112having its own control and sector biasing scheme. Although high capacity memory100is depicted as having eight banks112(112-1through112-112-8), in practice, high capacity memory100may have any number of banks High capacity memory100has global I/O circuitry102and global control104that is known in the art.

In the embodiment illustrated inFIG. 1, banks112in high capacity memory100are paired (e.g., bank112-1is paired with ban112-2) with paired banks sharing local I/O108and local control110circuitry. As further disclosed inFIG. 1, each bank112comprises a pair of sectors114. For example, bank112-1comprises sectors114-1-1and114-1-2. Each bank112also comprises XDEC circuitry106.

FIG. 2provides more detail regarding a memory bank114of memory100and the XDEC logic106that corresponds to the memory bank114in accordance with the present disclosure. Bank114comprises a plurality of sectors212. InFIG. 2, bank114is depicted as having eight sectors212. However, in practice, bank114can have more or less sectors212. Each sector212in the plurality of sectors of the bank114comprises a plurality of SRAM cells (not shown inFIG. 2) arranged in a plurality bitline rows and a plurality of bitline columns. Each bitline row is referred to as a physical row216herein. For the sake of conveying the details of bank114with clarity, only two of the physical rows216of each given sector212are shown inFIG. 2. In practice each sector212can have more than two physical rows216of bitcells. In fact, in preferred embodiments, each sector212comprises 32 or 64 physical rows216of bitcells, with each physical row216comprising any number of bitcells.

As illustrated inFIG. 2, in an embodiment, the plurality of sectors are divided into a first set of sectors (e.g., sectors212-1through212-4) and a second set of sectors (e.g., sectors212-5through212-8). The first set of sectors is electrically isolated from the second set of sectors by isolator214. Sectors212in the first set of sectors are isolated from each other by array straps230as shown inFIG. 2. Sectors212in the second set of sectors are also isolated from each other by array straps230as also shown inFIG. 2.

In the embodiment depicted inFIG. 2, each of the physical rows216in the sectors212in the first set of sectors are connected to a select bias control line218originating from bias control blocks206in a first sector bias control204-1. Further, each of the physical rows216in the sectors212in the second set of sectors are connected to a select bias control line218originating from bias control blocks206in a second sector bias control204-2.

While logically there is no requirement for a plurality of bias control blocks206in a sector bias control204, in practice, there are a plurality of bias control blocks206in order to assert a bias control voltage uniformly across the entire physical row216of each of the physical rows216in a sector212.

In some embodiments not shown, the plurality of sectors212of bank114are not divided into a first set and a second set of sectors and bias control lines218from bias circuits206of a single sector bias control204provide the sector bias signal to the physical rows216of all the sectors212in the bank114.

In the embodiment depicted inFIG. 2, XDEC circuitry106decodes a sector address into a sector address in a first range of sector addresses (e.g. a decoded sector address in the range of212-1through212-4) or second range of sector addresses (e.g. a decoded sector address in the range of212-5through212-8) for a first memory read operation. If the sector address is in the first range of sector addresses, a control signal is sent through bus240to sector decoder202-1in order to selectively unbias the bitcells of a specified sector212in the first set of sectors. If the sector address is in the second range of sector addresses, a control signal is sent through bus250to sector decoder202-2in order to selectively unbias the bitcells of a specified sector212in the second set of sectors.

Referring toFIG. 3, details of how the bias voltage of each sector212in the first set of sectors is controlled in accordance with an embodiment of the disclosure are provided. Sector decoder202-1is respectively coupled to sector bias circuits302-1through302-4of sector bias block206by control lines308-1(No_Bias1) through308-4(No_Bias4). In turn, sector bias circuits302-1through302-4are respectively coupled to sectors212-1through212-4by VSS_SEC lines218-1through218-4.

When sector decoder202-1is not receiving an address in the first range of sector addresses, sector decoder202-1drives308-1No_Bias1through308-4No_Bias4to a logical low state. Then, as discussed above in conjunction withFIG. 2, when an address received by sector decoder202-1is in a first range of sector addresses, a control signal is sent through bus240to sector decoder202-1in order to selectively unbias the bitcells of a specified sector212in the first set of sectors. Sector decoder202-1decodes this address into an identity of a sector212in the first range of sector addresses (e.g., as depicted inFIG. 3, sector212-1,212-2,212-3, or212-4). Consequently, sector decoder202-1drives the No_Bias line308of the sector bias circuit302coupled to the sector212specified by the sector address to a high state.

In the embodiment illustrated inFIG. 3, when the No_Bias line308between address decoder202-1and a sector bias circuit302is driven to the high state, the sector bias circuit302drives the corresponding VSS_SEC line218coupled to the circuit302to a ground voltage (first voltage, working voltage) specified by VSS310. When the No_Bias line308between address decoder202-1and a sector bias circuit302is driven to a low state, the sector bias circuit302drives the corresponding VSS_SEC line218to a bias voltage (second voltage). In some embodiments, this bias voltage (second voltage) is determined by a function of the combination of a VSS voltage310, a BC1control signal312, and a BC2control signal314. Alternatively, in some embodiments, this bias voltage (second voltage) is predetermined and cannot be adjusted.

FIG. 4illustrates a sector bias circuit302in accordance with an embodiment of the present invention. When No_Bias308is driven high by the address decoder202-1(not shown inFIG. 4) coupled to a sector bias circuit302, field effect transistor (FET)402is opened, allowing current to flow through FET402, and VSS_SEC218is driven to ground state VSS310. When No_Bias308is driven low by the address decoder, FET402is closed, preventing current from flowing through FET402, and VSS_SEC218is driven to a voltage that is determined by control signals312(BC1) and314(BC2) as set forth in the following truth table.

TABLE 1Truth TableNO_BIASBC1BC2Voltage value of VSS_SEC 218308312314(output from sector bias circuit 302)000VSS_SEC 218 is floating; shut down mode,array content is corrupted001VSS_SEC is biased to VSS level 1(maximum leakage reduction)010VSS_SEC is biased to VSS level 2(moderate leakage reduction)011VSS_SEC is Biased to VSS level 3(least leakage reduction)
For example, referring toFIG. 4, when No Bias308is driven low such that FET402is closed, and both BC1312and BC2314are driven high, the voltage of VSS_SEC218is determined by the voltage drop across both FET410and FET408. When No Bias308is driven low such that FET402is closed, BC1312is driven low, and BC2314is driven high, the voltage of VSS_SEC218is determined by the voltage drop across FET408. When No Bias308is driven low such that FET402is closed, BC1312is driven high, and BC2314is driven low, the voltage of VSS_SEC218is determined by the voltage drop across FET410. The ability to program VSS_SEC to one of three voltage levels (VSS level 1, VSS level 2, VSS level 3) is highly advantageous because it allows for minimization of leakage across different silicon chips (e.g. chips having different dopants and/or other features that affect the optimum value for preventing voltage leakage).

Referring now toFIG. 5, depicted therein is an exemplary embodiment of a source-biased SRAM cell500in accordance with the teachings of the present disclosure where leakage is advantageously reduced without disturbing the integrity of stored data. As illustrated, SRAM cell500is provided with a pair of complementary bitlines, BT514A and BB514B where each of the complementary bitlines may be coupled to appropriate precharge circuitry (not shown inFIG. 5) such that it is pulled to a power supply rail or a reference voltage source (typically VDDor any portion thereof) when the precharge circuitry is activated.

The memory cell500, also referred to as bitcell, is comprised of a latch502that includes a pair of cross-coupled inverters to form a pair of data nodes508A and508B. A first P-channel field effect transistor (P-FET)506A operating as a pull-up device of one of the inverters has its source/drain terminals connected between VDDand a first data node508A, with the gate thereof connected to a second data node508B. As is well known, the data nodes508A and508B operate as the two complementary storage nodes in the memory cell500. An N-channel FET (N-FET)504A operating as a pull-down device has its drain connected to the data node508A and its source connected to a wordline-based source bias control line (VSS_SEC)316that is switchably connected to a bias potential as previously described. The gate of N-FET504A is coupled to the second data node508B. With respect to the other inverter, a second P-FET506B is operable as a pull-up device having its source/drain terminals connected between VDDand the data node508B, with the gate thereof connected to the data node508A. A second N-FET504B is operable as a pull-down device in which the drain is coupled to the data node508B and the source is commonly connected to the source bias control line316.

A first N-FET access device512A is disposed between BT514A and the data node508A, with the gate thereof coupled to a wordline (WL)510. In similar fashion, a second N-FET access device512B has the source/drain thereof connected between BB514B and the data node508B so that its gate is also driven by WL510. The cross-coupled inverters of the memory cell form latch502, where nodes508A and508B are operable to hold logic levels that correspond to stored data.

Referring toFIG. 6, a sector212in the plurality of sectors of a memory bank114is disclosed. The sector212comprises a plurality of SRAM cells arranged in a plurality bitline rows216and a plurality of bitline columns. As discussed above in conjunction withFIG. 5, each SRAM cell500in the plurality of SRAM cells includes a pair of cross-coupled inverters that are coupled to form a pair of data nodes, and each SRAM cell500in the plurality of SRAM cells includes a pull-down device. The pull-down devices of the plurality of SRAM cells of the sector212are coupled together and to VSS_SEC218. The plurality of SRAM cells are selectively in (i) a working mode in which data in the plurality of SRAM cells can be accessed and in which the pull-down devices of the SRAM cells are driven by VSS_SEC218to a first voltage (ground voltage) or (ii) a standby mode in which the pull-down devices of the SRAM cells in the sector are driven by VSS_SEC218to a second voltage (bias voltage).

When a first sector address in a range of sector addresses is decoded for a first memory read operation and the first decoded sector address specifies a physical row216in the sector212depicted inFIG. 6, the plurality of SRAM cells ofFIG. 6are selectively activated by driving VSS_SEC to a first voltage (ground voltage). This drives the pull-down devices of the plurality of SRAM cells of the sector212to the first voltage. This first voltage is typically ground (0 V). A data value stored at a selected SRAM cell500in the sector212is read while continuing to drive pull-down devices of the plurality of SRAM cells of the sector212with the first voltage. The data value stored at a selected SRAM cell is read by (i) selecting a particular bitline row216in the sector212based on a row address, (ii) driving the WL line for the particular bitline row216to a high reading voltage, and (iii) selecting a particular bitline column in the sector212based on a column address. The selection of a particular bitline column in the sector based on a column address is performed by reading the columns into MUX and sense amplifier602that is controlled by Y-decoder620to select the desired column based on a truth table generated associated with control signals Y0and Y1(e.g., when Y0and Y1are both high, select YD0; when Y0and Yiare both low, select YD4; when Y0is low and Y1is high, select YD2; and when Y0is high and Y1is low, select YD3). The value of the selected SRAM cell500is output to output buffer604from MUX and sense amplifier602.

In practice, a physical row216typically comprises more than four bitcells500. In fact, in typically embodiments, a physical row216comprises considerably more than four bitcells500. Conventional MUX blocks are available for receiving the values of four bitcells500, eight bitcells500, or sixteen bitcells500. However, quite typically, there are more bitcells500in a physical row216than can be read into a single MUX block. Thus, in typical embodiments, a physical row216is read into a plurality of MUX blocks. For example, bitcells Y1through Y4may be read into a first MUX block, bitcells Y5through Y8may be read into a second MUX block, and so forth.

Referring toFIG. 7, disclosed is a memory operation method in accordance with an embodiment of the present disclosure in which, in step702, memory cells500of a sector212are in standby mode. In this standby mode, the write lines to the memory cells500in the sector212are in a deselected state (driven low). Moreover, the sector No_Bias signal308for the sector212is driven to a low state thereby driving the VSS_SEC lines to the memory cells in the sector to a biased potential (second voltage).

In step704, a first memory read address for a selected physical row216in the sector212is activated. A WL corresponding to the selected physical row216is driven high. Remaining WLs in the sector212remain in a deselected state (driven low). The sector No_Bias308signal for the sector212is driven to a high state thereby driving the VSS_SEC line to the memory cells500in the sector to a ground state (first voltage). The sector No_Bias signal308for other sectors212in the memory bank114are driven to an unelevated state thereby driving the VSS_SEC lines to the memory cells500in the other sectors212to a biased potential (second voltage).

In step706, voltage differentials of memory cells500in the selected physical row216are sensed. In step708, the logical value of each memory cell500in the selected physical row216is passed through one or more mux circuits602to select the value of a requested memory cell500.

In step710, a second memory read address for a selected physical row216in a sector212is activated. A WL corresponding to the selected physical row216is driven high. Remaining WLs in the sector212are driven to a deselected state (driven low). The sector No_Bias signal308for the sector212is driven to an elevated state thereby driving the VSS_SEC line218to the memory cells in the sector212to a ground state (first voltage). The sector No_Bias signal308for other sectors212in the memory bank114are driven to allow state thereby driving the VSS_SEC lines218to the memory cells500in the other sectors212to a biased potential (second voltage).

Based on the foregoing, it should be appreciated that the present invention provides a simple yet efficient and elegant leakage reduction scheme whereby cell read currents are not compromised as the memory cell technology evolves beyond the current designs of 0.13 microns. Additionally, the wordline-based source biasing mechanism as disclosed herein is adaptable to different SRAM sizes, configurations, and device sizes, wherein source-bias potential levels may be appropriately selected so as not to have deleterious effects (e.g., with respect to the integrity of stored data). Those skilled in the art should also readily recognize upon reference hereto that source-biasing potential may be provided by applying a select voltage to the source terminal of an SRAM cell or by appropriately biasing the body well potential thereof. Furthermore, it should be apparent that the teachings of the present invention may be practiced in standalone SRAM devices as well as compilable SRAM applications having one or more SRAM instances.

6 REFERENCES CITED

It is believed that the operation and construction of the present invention will be apparent from the foregoing Detailed Description. While some aspects of the method and circuitry shown and described may have been characterized as being preferred, it should be readily understood that various changes and modifications could be made therein without departing from the scope of the present invention as set forth in the following claims.