Adaptive high-side gate drive for ringing mitigation in switching power converters

A power converter includes a high side device, a low side device connected to the high side device at a switch node, an inductor connected to the high side device and the low side device at the switch node, and a high side driver. The high side driver is configured to drive a gate of the high side device at a first current for a first period of time. In response to the first period of time ending, the high side driver is configured to step down the first current for a second period of time. In response to the second period of time ending, the high side driver is configured to drive the gate of the high side device at the first current.

BACKGROUND

A switching power converter is an electronic circuit that converts an input direct current (DC) supply voltage into one or more DC output voltages that are higher or lower in magnitude than the input DC supply voltage. A switching power converter that generates an output voltage lower than the input voltage is termed a buck or step-down converter. A switching power converter that generates an output voltage higher than the input voltage is termed a boost or step-up converter.

A typical switching power converter may include a high side device (i.e., switch) and a low side device (i.e., switch) that alternately open and close a current path through a switch node to an inductor and capacitor. By opening and closing the high side device and the low side device alternately, a square wave type voltage signal is received at the switch node. This signal then is filtered by the inductor and capacitor (i.e., averaged) to generate a DC output signal that may be provided to an electrical load. Switching power converters are widely used to power electronic devices, particularly battery-powered devices, such as portable cellular phones, laptop computers, and other electronic systems in which efficient use of power is desirable.

SUMMARY

In accordance with at least one embodiment of the invention, a power converter includes a high side device, a low side device connected to the high side device at a switch node, an inductor connected to the high side device and the low side device at the switch node, and a high side driver. The high side driver is configured to drive a gate of the high side device at a first current for a first period of time. In response to the first period of time ending, the high side driver is configured to step down the first current for a second period of time. In response to the second period of time ending, the high side driver is configured to drive the gate of the high side device at the first current.

Another illustrative embodiment is a high side driver that includes a weak driver and a strong driver. The weak driver is configured to close a first switch in response to a first period of time beginning. The first switch is coupled to the gate of the high side device. The strong driver is configured to close a second switch in response to the first period of time beginning to drive the high side device at a first current. The strong driver is also configured to open the second switch in response to the first period of time ending to drive the high side device at a second current. The strong driver is also configured to close the second switch a second time in response to a second period of time ending to drive the high side device at the first current. The second switch is coupled to the gate of the high side device. The first current is greater than the second current.

Yet another illustrative embodiment is a method for driving a high side device in a switching power converter to mitigate ringing in the switch node of the switching power converter. The method includes driving the gate of the high side device at a first current for a first period of time. The method also includes, in response to the first period of time ending, driving the gate of the high side device at a second current for a second period of time, the second current being less than the first current. The method also includes, in response to the second period of time ending, driving the gate of the high side device at the first current.

NOTATION AND NOMENCLATURE

DETAILED DESCRIPTION

Switching converters are high efficiency electronic devices that translate a supply voltage to another voltage. For example, a switching converter may step up one voltage to a higher voltage or may step down one voltage to a lower voltage. In switching converters, power is transferred to the output of the converter by applying the input voltage to a switch node between two switches that alternate being switched open and closed and averaging the resulting waveform. However, a parasitic inductance, created due to the package or the printed circuit board (PCB) upon which the switching converter is utilized, is excited by the fast switching transients which generates significant ringing at the switch node. This leads to degraded device reliability, increased high-frequency EMI transmissions, and increased core-losses. In order to mitigate ringing at the switch node, the damping factor of an equivalent RLC network of the power loop in the converter should be kept large as the voltage in the switch node transitions during switching. By controlling the change in current with respect to the change in time when the high side device is closed, it is possible to maintain a large damping factor.

In accordance with various examples, an adaptive high side gate driver is provided that segments the current drive into three phases over three periods of time. A large gate drive current is provided on the high side device over a short pulse over a first period of time followed by a small gate drive current for a second period of time. This dampens the change in current with respect to change in time until the voltage in the switch node begins to rise. Once the voltage in the switch node begins to rise, a large gate drive current is provided on the high side device. This enables control in the change in current with respect to the change in time to provide ringing mitigation in the voltage at the switch node.

FIG. 1shows an illustrative block diagram of a power conversion system100in accordance with various examples. The power conversion system100may include a power supply102, a switching power converter104, and a load106. Power supply102may be any type of DC power supply to provide electrical energy to the switching power converter104. In some embodiments, the power supply102is a voltage regulator that provides a constant input voltage122to the switching power converter104.

The switching power converter104may be configured to receive the input voltage122and translate the input voltage122into an output voltage124at a second level. For example, the switching power converter104may be configured to step up the input voltage122to generate an output voltage124at a higher level, and/or the switching power converter104may be configured to step down the input voltage122to generate an output voltage124at a lower level. The output voltage124then may drive electric load106.

The switching power converter104may include an adaptive high side driver112, a low side driver114, a switching circuit116, a detection circuit118, a coarse counter152, and a fine counter154.FIG. 2shows an illustrative circuit diagram of the switching circuit116being driven by adaptive high side driver112and low side driver114in accordance with various examples. The switching circuit116may include a high side device202, a low side device204, and an inductor206connected at a switch node250. The switching circuit116may also include a capacitor208. The high side and low side devices may act as switches, and thus, may be power transistors. In some embodiments, the high side device202and the low side device204are n-channel metal oxide semiconductor (NMOS) transistors. However, in alternative embodiments, the high side device202and the low side device204may be any type of transistor, including p-channel metal oxide semiconductor (PMOS) transistors, a p-type junction gate field-effect transistor (PJFET), a n-type junction gate field-effect transistor (NJFET), and a bipolar junction transistor (BJT) (including PNP and NPN transistors).

The high side device202and the low side device204act to drive the inductor206and capacitor208, acting as an LC tank, in addition to load106. Therefore, the inductor206and capacitor208act to filter the input voltage122at the output voltage124. The high side device202and low side device204are alternatively switched open and closed to generate an approximate square wave pattern at the switch node250. Thus, the low side driver is configured to drive the low side device204with drive signal134to cause the low side device204to alternatively open and close. Similarly, the adaptive high side driver112is configured to the drive the high side device with drive signal132to cause the high side device202to alternatively open and close. The voltage at the switch node250(the approximate square wave voltage) is filtered out (averaged) into the DC output voltage124which is used to supply the load106.

However, the parasitic inductance, shown as Lpar210and Lpar212, in the power loop, inside the package or the PCB in which the switching circuit116is utilized, is excited by fast switching transients which generates ringing in the voltage at the switch node250. In order to mitigate any ringing in voltage at the switch node250, the change in current with respect to the change in time may be controlled in the high side device202through the drive signal132generated by the adaptive driver112.

In order to control the change in current with respect to the change in time in the high side device202, to close the high side device202, the adaptive high side driver112may be configured to generate a short pulse at a first drive current (a relatively large gate drive current which, in some embodiments, may be approximately 350 mA) for a first period of time. This short pulse of drive current (in some embodiments approximately 2 ns) enables the Vgs of the high side device202to reach its threshold voltage. Once the first period of time has ended (the Vgs on the high side device202has reached its threshold voltage), the high side driver202may be configured to step down the drive current to a second lower drive current (a relatively small gate drive current which, in some embodiments, may be less than 50 mA) for a second period of time. By lowering the drive current for the high side device202during the second period of time, the drain current of the high side device202will ramp relatively slowly which provides a low change in current with respect to change in time. Once, the voltage in the switch node250begins to rise, the second period of time ends, and the adaptive high side driver112will again drive the high side device202with the first drive current (i.e., the relatively high drive current (e.g., approximately 350 mA) that drove the high side device202during the first period of time). In some embodiments, the adaptive high side driver112may be configured to continue to drive the high side device202at the first drive current until the high side device202is turned fully ON and thus, the high side device202is closed. By controlling this change in current with respect to the change in time during the closing of the high side device202in this manner, ringing at the switch node may be mitigated.

FIG. 3shows an illustrative circuit diagram of adaptive high side driver112in accordance with various examples. The adaptive high side driver112may include a weak driver302, a strong driver304, a first switch (the NW switch306), and a second switch (the MW switch308). The NW switch306and the MW switch308may, in some embodiments, be PMOS transistors; however, in alternative embodiments, the NW switch306and the MW switch308may be any type of switch including NMOS transistors, PJFETs, NJFETs, BJTs, and/or any combination thereof.

In response to receiving an enable signal (a signal indicating that the high side driver202is to close), both the weak driver302and the strong driver304are configured to close their respective switches. In other words, in response to receiving the enable signal, the weak driver302may be configured to generate a drive current to close the NW switch306and the strong driver304may be configured to generate a drive current to close the MW switch308. When the NW switch306closes, a drive current320that is equal to the second drive current discussed above (i.e., the relatively low drive current which in some embodiments is less than 50 mA) drives the gate of the high side device202as at least part of the drive signal132. When the MW switch308closes, a drive current322that is just less than the first current discussed above drives the gate of the high side device as at least part of the drive signal132. Thus, when the MW switch308is closed, the combination of the drive current320and the drive current322equals the first current discussed above (e.g., approximately 350 mA) as the drive signal132to drive the gate of the high side device202.

The weak driver302may be enabled for the entire time the high side device202is configured to be closed. However, the strong driver304may be enabled for only a first period of time322and after a second period of time324. Thus, when the enable signal is received, the first period of time begins, and the weak driver302drives the gate of the NW switch306, causing the NW switch306to close, and the strong driver304drives the gate of the MW switch308, causing the MW switch308to close a first time during the cycle (i.e., a cycle begins when the high side device202is closed and continues while the high side device202is opened and the low side device204is closed—a new cycle begins again when the high side device202is closed again). Thus, the first current drives the gate of the high side device202for the first period of time322. The first period of time, may be a fixed period of time (in some embodiments approximately 2 ns) that enables the Vgs of the high side device202to reach its threshold voltage. Once the first period of time322ends, the strong driver304may remove drive current from the gate of the MW switch308, thus opening the MW switch308. This may stop the drive current322from driving the high side device202. However, the weak driver302maintains drive current on the gate of the NW switch306which causes the NW switch306to remain closed. Thus, in response to the first period of time322ending, the drive current320may be the only drive current to drive the gate of the high side device202. The time that the drive current320may be the only drive current to drive the gate of the high side device202is the second period of time324. As discussed above, the ending of the second period of time324may correspond with a detection of a rising voltage at the switch node250. Thus, the second period of time324may change from cycle to cycle as will be discussed below. Once the second period of time324ends, the strong driver304, once again drives the gate of the MW switch308to close the MW switch308a second time during the cycle. Thus, the first current (i.e., the combination of drive currents320and322) once again drives the gate of the high side device202as discussed above. In this way, the adaptive high side driver112may provide a segmented gate driver for the high side device202that provides the change in current with respect to the change in time that reduces and/or mitigates ringing in the voltage at the switch node250.

Returning toFIG. 1, the detection circuit118may be any circuit that is configured to detect a rising voltage at the switch node250. The detection circuit118may also make a determination of whether the rising voltage at the switch node250is detected before or after the MW switch322closes for the second time in a cycle. For example, a comparator (not shown) may be utilized to make this determination. The coarse counter152and the fine counter154may be utilized to adjust the second period of time324for an immediate subsequent cycle or any subsequent cycle. The coarse counter152may be any circuit that is configured to make coarse adjustments to the second period of time324for an immediate subsequent cycle while the fine counter154may be utilized to make fine adjustments to the second period of time324for an immediate subsequent cycle.

For example, the switching power converter104may be initialized to, for a first cycle of operation, to have a second period of time324of0. In other words, the first time the high side device202switches closed, the second period of time324may be set to 0. In such a case, the MW switch308does not close a second time, and the first current (i.e., the relatively high drive current) drives the gate of the high side device202for the entire time the high side device202is closed during the first cycle. Thus, the time that the first time the MW switch308closes (which in the first cycle may be considered the second time the MW switch308closes) is compared to time that the rising voltage at the switch node250is detected. In this case, the time that the rising voltage at the switch node250is detected will be after the first and only time the MW switch308closes; therefore, the coarse counter will add a coarse delay unit to a coarse delay unit count. In some embodiments, each count in the coarse delay unit count corresponds to approximately 1-1.5 ns. In response to the added coarse delay unit to the coarse delay unit count, in the immediate subsequent cycle, (e.g., the second cycle), the second period of time324is increased from 0 by the amount of time corresponding to a coarse delay unit (e.g., 1-1.5 ns). This process (i.e., comparing the rising voltage at the switch node250to the closing of the MW switch308a second time during a cycle and adding a coarse delay unit in response to a determination that the rising voltage at the switch node250occurs after the closing of the MW switch308a second time during a single cycle) will repeat for each subsequent cycle until the detection circuit118detects the rising voltage at the switch node250occurs before the MW switch308closes a second time in a cycle.

Once, the detection circuit118detects rising voltage at the switch node250occurs before the MW switch308closes a second time in a cycle, the fine counter may be engaged and configured to subtract a fine delay unit to a fine delay unit count. In some embodiments, each count in the fine delay unit count corresponds to approximately 200-300 ps. In response to the subtracted fine delay unit to the fine delay unit count, in the immediate subsequent cycle, the second period of time324is decreased from the immediate previous cycle by the amount of time corresponding to a fine delay unit (e.g., 200-300 ps). In subsequent cycles, the fine delay unit count is either subtracted from or added to based on whether the rising voltage at the switch node250occurs after (add to the fine delay unit count) or before (subtract from the fine delay unit count) the closing of the MW switch308a second time in a cycle. If, for a threshold number of cycles in a row (e.g., four straight cycles) the fine delay unit count is added to, then the coarse counter152may be re-engaged and a coarse delay unit is added to the coarse delay unit count and the second period of time324is increased by the amount of time corresponding to a coarse delay unit (e.g., 1-1.5 ns) in the immediate subsequent cycle. Similarly, if, for a threshold number of cycles in a row (e.g., four straight cycles) the fine delay unit count is subtracted from, then the coarse counter152is re-engaged and a coarse delay unit is subtracted from the coarse delay unit count and the second period of time324is decreased by the amount of time corresponding to a coarse delay unit in the immediate subsequent cycle. In subsequent cycles, the coarse delay unit count is either subtracted from or added to based on whether the rising voltage at the switch node250occurs after (add to the coarse delay unit count) or before (subtract from the coarse delay unit count) the closing of the MW switch308a second time in a cycle until the coarse delay unit count overshoots (i.e., if the coarse delay unit count is added to, there is overshoot as soon as the rising voltage at the switch node250is detected before the closing of the MW switch308in the cycle and if the coarse delay unit count is subtracted from, there is overshoot as soon as the rising voltage at the switch node250is detected after the closing of the MW switch308in the cycle). Once a determination is made that there is overshoot, the fine counter154is re-engaged to control, as discussed above, the timing of the second period of time324. In this way, the second period of time324is regulated so that the MW switch308closes at a time that corresponds closest with the time the voltage at the switch node250begins to rise. This, in turn, as discussed previously, regulates the change in current with respect to the change in time to reduce and/or mitigate ringing in the voltage at the switch node250.

In addition to the second period of time324affecting the ringing in the voltage of the switch node250, the ratio of the weak drive and the strong drive in the adaptive high side driver112also may affect the ringing in the voltage of the switch node250. Therefore, in some embodiments, a saturation count loop may focus on the coarse delay unit count. The coarse delay unit count may saturate. To alleviate the possibility of saturation in the coarse unit delay count, the saturation count will compare the coarse unit delay count to the saturation level of the coarse counter152. Once the coarse unit delay count drops below 25% of the range of the coarse counter152and/or rises above 75% of the range of the coarse counter, the strength of the adaptive high side driver112may be adjusted. In some embodiments, if the coarse unit delay count drops below 25% of the range of the coarse counter152, the number of fingers in the NW switch306and/or the MW switch308is adjusted such that the adaptive high side driver112provides a weaker (i.e., lower) drive current to the gate of the high side device202. However, in some embodiments, if the coarse unit delay count rises above 75% of the range of the coarse counter152, the number of fingers in the NW switch306and/or the MW switch308is adjusted such that the adaptive high side driver112provides a stronger (i.e., higher) drive current to the gate of the high side device202. This may provide an additional measure to reduce ringing in the voltage of the switch node250.

FIG. 4shows an illustrative timing diagram400in accordance with various examples. The timing diagram400shows an illustrative enable signal402for the weak driver302to drive the gate of the NW switch306. As shown, the enable signal402is HIGH the length of the cycle that the high side device202is to be closed. Thus, the weak driver302is configured to drive the gate of the NW switch306to keep the NW switch306closed for the entire cycle that the high side device202is to be closed. The timing diagram400also shows an illustrative enable signal404for the strong driver304to drive the gate of the MW switch308. As shown, the enable signal404is HIGH for the first period of time322. Thus, for the first period of time322, the strong driver304drives the gate of the MW switch308to keep the MW switch308closed for the first period of time322. Thus, during the first period of time322, the gate of the high side device202is driven by the combined currents320and322(i.e., a relatively large current). However, the enable signal404is LOW for the second period of time324. Thus, for the second period of time324, the strong driver304causes the MW switch308to open for the second period of time324. Thus, during the second period of time324, the gate of the high side device202may be driven by current320only (i.e., a relatively small current). Also, as shown, the enable signal404is HIGH upon the ending414of the second period of time324. Thus, for the remainder of the cycle that the high side device202is to be closed, after the second period of time324ends, the strong driver304drives the gate of the MW switch308to keep the MW switch308closed for the remainder of the cycle. Thus, during the remainder of the cycle that the high side device202is to be closed, the gate of the high side device202is driven by the combined currents320and322(i.e., a relatively large current).

The signal406illustrates a comparison of the time of a rising voltage of the switch node250to the closing of the MW switch308a second time during a cycle (i.e., the end414of the second period of time324). In the example of signal406, the MW switch308is closed prior to the rising voltage of the switch node250is detected. Therefore, either the coarse delay unit count and/or the fine delay unit count is added to, so that in an immediate subsequent cycle, the MW switch308will close later in the cycle. In the example of signal408, the MW switch308is closed after the rising voltage of the switch node250is detected. Therefore, either the coarse delay unit count and/or the fine delay unit count is subtracted from, so that in an immediate subsequent cycle, the MW switch308will close earlier in the cycle.

FIG. 5shows an illustrative flow diagram of a method500driving a high side device in a switching power converter to mitigate ringing in a switch node of the switching power converter in accordance with various examples. Though depicted sequentially as a matter of convenience, at least some of the actions shown can be performed in a different order and/or performed in parallel. Additionally, some embodiments may perform only some of the actions shown. In some embodiments, at least some of the operations of the method500, as well as other operations described herein, can be performed by the switching power converter104(including the adaptive high side driver112, low side driver, switching circuit116, detection circuit118, coarse counter152, and/or fine counter154) and implemented in logic and/or by a processor executing instructions stored in a non-transitory computer readable storage medium.

The method500begins in block502with driving the gate of a high side device, such as high side device202, at a first current for a first period of time, such as first period of time322. For example, an adaptive high side driver, such as adaptive high side driver112, may be configured to drive the gate of the high side device at a relatively high current for a fixed period of time (e.g., 2 ns). In block504, the method500continues with determining whether the first period of time is over. For example, a determination may be made whether 2 ns has elapsed since the adaptive high side driver began driving the gate of the high side device. If, in block504, a determination is made that the first period of time is not over, then the method500continues in block502with driving the gate of the high side device at the first current.

If, however, in block504, a determination is made that the first period of time is over, then the method500continues in block506with driving the gate of the high side device at a second current for a second period of time. For example, the adaptive high side driver may be configured to drive the gate of the high side device at a relatively low current for a second period of time, such as second period of time324. Thus, the first current may be greater than the second current.

In block508, the method500continues with detecting a rising voltage at a switch node. For example, a detection circuit, such as the detection circuit118, may be configured to monitor a voltage at a switch node, such as switch node250, attached to the high side device to detect when the voltage in the switch node begins to rise. The method500continues in block510with determining whether the second period of time is over. For example, the second period of time may be over at the time that a switch, such as MW switch308, connected to a strong driver, such as strong driver304, in the adaptive high side driver has closed for a second time during a single cycle.

If, in block510, a determination is made that the second period of time is over, then the method500continues in block512with driving the gate of the high side device at the first current. For example, once the second switch closes for the second time in the cycle, the gate of the high side device is driven at the relatively high first current.

In block514, the method500continues with adding to a coarse delay unit count. For example, because the rising voltage at the switch node is detected after the second period of time is over, a coarse counter, such as the coarse counter152, may be configured to add a coarse delay unit to a coarse delay unit count. The method500continues in block516with increasing the second period of time for a subsequent switching cycle. For example, with an increase in the coarse delay unit count, the second period of time is increased in the subsequent cycle by the amount of time corresponding to the coarse delay unit count (e.g., 1-1.5 ns). The method500then may continue in block502in a subsequent cycle with driving the gate of the high side device at the first current for the first period of time.

If, in block510, a determination is made that the second period of time is not over, then the method500continues in block510with determining whether the second period of time is over. Additionally, because the rising voltage at the switch node is detected before the second period of time is over, the method500continues in block518with subtracting from a fine delay unit count. For example, a fine counter, such as fine counter154, may be configured to subtract a fine delay unit to a fine delay unit count. In block520, the method continues with decreasing the second period of time for a subsequent switching cycle. For example, with a decrease in the fine delay unit count, the second period of time is decreased in the subsequent cycle by the amount of time corresponding to the fine delay unit count (e.g., 200-300 ps). The method500then may continue in block502in a subsequent cycle with driving the gate of the high side device at the first current for the first period of time.