Control module with an estimator of an input electric quantity for a switching converter and method for controlling a switching converter

Described herein is a module for controlling a switching converter, which includes at least one inductor element and one switch element and generates an output electric quantity starting from an input electric quantity. The control module generates a command signal for controlling the switching of the switch element and includes an estimator stage, which generates an estimation signal proportional to the input electric quantity, on the basis of the command signal and of an input signal indicating a time interval in which the inductor element is demagnetized. The control module generates the command signal on the basis of the estimation signal.

BACKGROUND

Technical Field

The present disclosure relates to a control module for a switching converter, which includes an estimator of an input electric quantity. In addition, the present disclosure relates to a method for controlling a switching converter.

Description of the Related Art

As is known, there exist various types of switching converters, amongst which there may, for example, be cited flyback, boost, and buck converters.

In general, in the field of switching converters there is particularly felt the need to have available converters that are characterized by a high power factor, as well as a low total harmonic distortion (THD) and a low zero-load power dissipation. In order to obtain the aforementioned characteristics, switching converters are known that implement, for example, a circuit layout of the type illustrated inFIG. 1.

In detail,FIG. 1shows a switching power supply1of a flyback type, referred to hereinafter as “flyback power supply1”.

In greater detail, the flyback power supply1includes a bridge rectifier2, which has two input terminals, designed to receive an a.c. voltage from a supply line, and a first output terminal and a second output terminal, which are connected, respectively, to a first ground and to a first terminal of a filtering capacitor Cin, the second terminal of which is connected to the first ground. The bridge rectifier2supplies on its own second output terminal a voltage Vin(θ), referred to hereinafter as “input voltage Vin(θ)”, where θ is the phase of the a.c. voltage present on the supply line.

The flyback power supply1further comprises a flyback converter3, which on the primary side includes, in addition to the filtering capacitor Cin, a transformer4, which comprises a first inductor Lpand a second inductor Ls, which function respectively as primary winding Lpand secondary winding Lsand share a same magnetic core, referred to hereinafter as “core of the transformer4”. Furthermore, the transformer4comprises an auxiliary winding Laux. A first terminal of the primary winding Lpis connected to the first terminal of the filtering capacitor Cin.

The flyback converter3further comprises a control module15, a resistive divider16, which includes a first resistor Raand a second resistor Rb, and a transistor M formed, for example, by a power MOSFET.

The first resistor Rahas a first terminal and a second terminal, which are connected, respectively, to the first terminal of the filtering capacitor Cinand to a first terminal of the second resistor Rb, the second terminal of which is connected to the first ground. In practice, the second terminal of the first resistor Raand the first terminal of the second resistor Rbform a node electrically coinciding with a first input terminal MULT of the control module15.

The flyback converter3further comprises a third resistor RZCDand a fourth resistor Rs. The first and second terminals of the third resistor RZCDare connected, respectively, to the first terminal of the auxiliary winding Laux, the second terminal of which is connected to the first ground, and to a second input terminal ZCD of the control module15. The first and second terminals of the fourth resistor Rsare connected, respectively, to the source terminal of the transistor M and to the first ground. Further, the first terminal of the fourth resistor Rsis connected to a third input terminal CS of the control module15. Once again with reference to the transistor M, the drain terminal is connected to the second terminal of the primary winding Lp, whereas the gate terminal is connected to an output terminal GD of the control module15, which further includes a feedback terminal FB, described hereinafter, and a fourth input terminal GND, connected to the first ground.

In practice, the fourth resistor Rsenables detection of the current that flows in the primary winding Lpwhen the transistor M is on. InFIG. 1, the current that flows in the fourth resistor Rsis designated by Ip(t,θ).

The flyback converter3further comprises a clamping circuit20, which is arranged between the first and second terminals of the primary winding Lpfor limiting the spikes of the voltage present on the drain terminal of the transistor M, caused, for example, by parasitic inductances.

On its own secondary side, the flyback converter3comprises a feedback circuit22, a diode D, referred to hereinafter as “output diode D”, and a further capacitor Cout, referred to hereinafter as “output capacitor Cout”; typically, the output capacitor Coutis of an electrolytic type.

The anode of the output diode D is connected to a first terminal of the secondary winding Ls, whereas the cathode is connected to a first terminal of the output capacitor Cout, the second terminal of which is connected to a second ground, as on the other hand also the second terminal of the secondary winding Ls. In general, the voltage across the output capacitor Coutis referred to hereinafter as “output voltage Vout”. Further, the output voltage Voutrepresents the voltage that is to be regulated by the flyback converter3. InFIG. 1, the current that flows in the output diode D is designated by Is(t,θ).

The feedback circuit22is connected to the first terminal of the output capacitor Coutand to the feedback terminal FB of the control module15. In addition, the feedback circuit22is configured to generate an error signal proportional to the difference between the output voltage Voutand a reference voltage, as well as for transferring the error signal on the primary side of the flyback converter3, generally using an opto-coupler. This transfer entails generation of a control voltage Vcon the primary side, and in particular on the feedback terminal FB of the control module15. In this connection, the control module15generates on a own node an internal voltage Vint, and further has a fifth resistor Rc, which is arranged between the aforementioned node and the feedback terminal FB of the control module15. Furthermore, the control module15and the feedback circuit22are coupled in such a way that, at output from the feedback terminal FB of the control module15, a current IFBis present that depends upon the aforementioned error signal. The current IFBcauses a voltage drop on the fifth resistor Rc. The aforementioned control voltage Vcis, precisely, the voltage present on the feedback terminal FB of the control module15and depends upon the error signal in such a way as to regulate the output voltage Vout. To a first approximation, the control voltage Vcmay be considered constant because the band of the control loop is much lower than the frequency of the input voltage Vin(θ).

The control module15further comprises a multiplier24, a comparator26, a flip-flop28of a set-reset type, a driver30, a starter circuit32, a first logic gate34of an OR type, and a circuit36referred to hereinafter as “zero-current detection circuit36”.

In detail, the multiplier24has a first input, connected to the feedback terminal FB of the control module15for receiving the control voltage Vc, and a second input, connected to the first input terminal MULT for receiving the voltage present thereon, which is proportional to the input voltage Vin(θ) through the division ratio R2/(R1+R2) introduced by the resistive divider16, where R1and R2are the values of resistance of the first and second resistors Ra, Rb. The multiplier24generates a voltage VcsREF(θ) on an own output, which is connected to a negative input terminal of the comparator26. The voltage VcsREF(θ) has the form of a rectified sinusoid, the amplitude of which depends upon the control voltage Vcand the effective voltage present on the supply line.

The positive input terminal of the comparator26is connected to the third input terminal CS of the control module15for receiving the voltage (designated by Vcs(t,θ)) present on the fourth resistor Rs. The voltage Vcs(t,θ) is directly proportional to the current present in the primary winding Lpwhen the transistor M is in conduction, i.e., during magnetization of the primary winding Lpitself.

The output of the comparator26is connected to the reset input of the flip-flop28, the output of which (designated by Q) is connected to the input of the driver30, the output of which forms the output terminal GD of the control module15. The output of the flip-flop28is further connected to the set input of the flip-flop28itself, by interposition of the starter circuit32. In particular, the input of the starter circuit32is connected to the output Q of the flip-flop28, whereas the output of the starter circuit32is connected to a first input of the first logic gate34. The second input and the output of the first logic gate34are connected, respectively, to the output of the zero-current detection circuit36and to the set input of the flip-flop28. The input of the ZCD circuit36is connected to the second input terminal ZCD of the control module15.

In use, assuming that the transistor M is on, there occurs a linear growth of the current Ip(t,θ) in the primary winding Lpand hence of the voltage Vcs(t,θ). When the voltage Vcs(t,θ) becomes equal to the voltage VcsREF(θ), the comparator26resets the output of the flip-flop28, and the transistor M is turned off. Consequently, the voltage supplied by the resistive divider16, which has the form of a rectified sinusoid, determines the peak value of the current in the primary winding Lp, which is thus enveloped by a rectified sinusoid.

When the transistor M turns off, the energy stored in the primary winding Lpis transferred by magnetic coupling to the secondary winding Ls, and hence in the output capacitor Coutuntil the secondary winding Lsdemagnetizes. Furthermore, as long as a current flows in the secondary winding Ls, the voltage of the drain terminal of the transistor M is equal to Vin(θ)+VR, where VRis the so-called reflected voltage, equal to n·Vout, where n is the ratio between the number of the turns of the primary winding Lpand the number of the turns of the secondary winding Lsof the transformer4.

Following upon demagnetization of the secondary winding Ls, the output diode D opens, and the drain terminal of the transistor M becomes floating and tends to assume a voltage equal to the input voltage Vin(θ) through damped oscillations caused by a parasitic capacitance resonating with the primary winding Lp. However, the fast drop in voltage that takes place on the drain terminal of the transistor M following upon demagnetization of the transformer4is coupled to the second input terminal ZCD of the control module15through the auxiliary winding Lauxand the third resistor RZCD. Furthermore, the zero-current detection circuit36generates a pulse whenever it detects that a falling edge of the voltage present on its own input drops below a threshold. This pulse forces a corresponding change of the output of the flip-flop28and consequently leads to turning-on of the transistor M and start of a new switching cycle.

The starter circuit32enables start of the first switching cycle after turning-on of the flyback converter3, i.e., when no signal is yet present on the second input terminal ZCD of the control module15, and further prevents the flyback converter3from remaining blocked if for any reason the signal on the second input terminal ZCD of the control module15is lost.

Examples of the signals that are generated in use within the flyback converter3are illustrated inFIG. 2, which, in addition to the aforementioned quantities Ip(t,θ), Is(t,θ), Vcs(t,θ), VcsREF(θ), shows:the voltage VDSbetween the drain and source terminals of the transistor M;the voltage Vin,pksin θ, where Vin,pkis the peak value of the input voltage Vin;the voltage Vauxpresent on the auxiliary winding Laux;the voltage VZCDpresent on the second input terminal ZCD of the control module15;the thresholds VZCDarmand VZCDtrigof the voltage VZCDat which the zero-current detection circuit36is armed and generates a pulse, respectively;the state ARM of the zero-current detection circuit36;the signal sS (of a logic type) present on the set input of the flip-flop28, and hence the pulses TRIGGER generated by the zero-current detection circuit36;the signal sR (of a logic type) present on the reset input of the flip-flop28;the signal sGD (of a logic type) present on the output Q of the flip-flop28, which governs turning-on of the transistor M (it is assumed that the driver30does not introduce any delay); anda so-called “freewheel” state FW, corresponding to the period in which there occurs demagnetization of the transformer4.

In general, it should be noted that, in indicating the quantities, the fact of not rendering any dependence upon parameters (in the case in point, the phase θ or the time t) explicit does not imply that the quantity in question is necessarily constant.

In addition,FIG. 2represents the following periods:the period TON, in which the transistor M is on, i.e., in conduction, and hence the period in which the core of the transformer4is magnetized;the period TFW, in which demagnetization of the core of the transformer4occurs; andthe period TR, i.e., the delay that elapses between complete demagnetization of the core of the transformer4and next turning-on of the transistor M, i.e., start of new magnetization of the core of the transformer4.

The resulting plots of the currents Ip(t,θ), Is(t,θ), as well as the corresponding envelopes of the corresponding peaks Ipkp(θ), Ipks(θ) and the average, cycle by cycle, Iin(θ) of the current in the primary winding Lpare illustrated inFIG. 3. For completeness, designating by T the switching period, we have T=TFW+TR+TON.

For practical purposes, the flyback converter3is of the quasi-resonant type. In fact, turning-on of the transistor M is synchronized with the instant of complete demagnetization of the transformer4(i.e., with the instant when the current in the secondary winding Lsbecomes zero), albeit with a delay such that it occurs at a so-called “valley” of the voltage VDS. Turning-off of the transistor M is, instead, determined by detecting the moment when the current in the primary winding Lpreaches a given value. Furthermore, the flyback converter3is of the current-mode control type, and in particular of the peak-current-mode control type. In addition, since the peak envelope of the current that flows in the fourth resistor Rs, and hence in the primary winding Lp, is sinusoidal, a power factor higher than 0.9 is obtained.

In practice, as illustrated inFIG. 4, the flyback converter3implements an electrical layout formed by a conversion stage40, which is operatively coupled to the control module15. In particular, the conversion stage40receives at input the input voltage Vin(θ) and is controlled by the control module15in such a way as to supply the output voltage Vout. As illustrated inFIG. 4, control of the conversion stage40occurs thanks to the aforementioned signal sGD (more precisely, thanks to the voltage VGApresent on the gate terminal of the transistor M), as well as thanks to the voltage VZCD. Further, even though not illustrated inFIG. 2, the conversion stage40is controlled also on the basis of the feedback present between the output of the conversion stage40and the control module15. In addition, in order to control the conversion stage40, the control module15receives at input, through the resistive divider16, a fraction of the input voltage Vin(θ), designated by VMULTinFIG. 4.

FIG. 5shows a further example of converter, and in particular shows a boost converter50, which is here described just as regards the differences with respect to the flyback converter3. InFIG. 5, components already illustrated inFIG. 1have the same reference numbers, except where otherwise specified. The clamping circuit20is absent.

In detail, instead of the transformer4, a coupled inductor54is present, which includes the primary winding and the auxiliary winding, designated, respectively, by L1and Laux, but not the secondary winding. The primary winding and the auxiliary winding L1and Lauxshare a same magnetic core. The first terminal of the primary winding L1is still connected to the first terminal of the filtering capacitor Cin, but the second terminal is connected to the anode of the output diode D. The auxiliary winding Lauxis electrically connected as in the case of the flyback converter3and performs the same electrical function. The drain terminal of the transistor M is still connected to the second terminal of the primary winding L1. Hence, it is now connected to the anode of the output diode D.

The feedback circuit, designated by52, comprises a sixth resistor Rdand a seventh resistor Re, which form a corresponding resistive divider, which is arranged between the cathode of the output diode D and ground and the central node of which is connected to the feedback terminal FB of the control module, here designated by55.

The control module55comprises, instead of the fifth resistor Rc, an amplifier58, referred to hereinafter as “error amplifier58”. The non-inverting terminal of the error amplifier58is connected to a reference node, which is set at an internal reference voltage Vref_int, whereas the non-inverting terminal forms the feedback terminal FB of the control module55. The output of the error amplifier58is connected to the first input of the multiplier24, the second input of which is still connected to the resistive divider16. The output of the multiplier24is connected to the negative input terminal of the comparator26, the positive input terminal of which is connected to the third input terminal CS of the control module55.

The boost converter50further comprises a loop-compensation circuit60, which extends between a respective first node and a respective second node and includes an eighth resistor Rfand a ninth resistor Rg, as well as a further capacitor62, referred to hereinafter as “additional capacitor62”. In particular, the eighth resistor Rfis arranged between the aforementioned first and second nodes of the loop-compensation circuit60and is arranged in parallel to the series circuit formed by the additional capacitor62and by the ninth resistor Rg. Furthermore, the first node of the loop-compensation circuit60is connected to the feedback terminal FB of the control module55, whereas the second node of the loop-compensation circuit60is connected to the output of the error amplifier58.

In practice, the error amplifier58compares a portion of the output voltage Voutwith the internal reference voltage Vref_intand generates the control voltage Vc, which depends upon an error signal proportional to the deviation between the aforementioned portion of the output voltage Voutand the internal reference voltage Vref_intfor regulating the output voltage Vout. As explained previously, to a first approximation, the control voltage Vcmay be considered constant. The subsequent operation of the boost converter50is similar to that of the flyback converter3. Examples of the time plots of the signals sS, sR, sGD and of the current I(t,θ) in the primary winding L1are illustrated inFIGS. 6aand 6b. Further,FIG. 6ashows a signal sZCD indicating the period in which the current iLthrough the primary winding L1is zero.

In greater detail, the boost converter50operates in the so-called “transition mode” (TM) since the current in the primary winding L1vanishes for a short period of time.

This being said, irrespective of the topology of the switching converter considered (flyback, boost, buck, etc.), there occurs generation of a sinusoidal reference, by a sort of line-sensing circuitry that includes a resistive divider and enables detection of a percentage of the rectified line voltage. This entails a dissipation on the resistive divider, which, according to the application and the corresponding sizing of the switching converter, may range between about ten milliwatts and some tens of milliwatts. This loss is hence not negligible and the desire to reduce it as much as possible is particularly felt.

BRIEF SUMMARY

One embodiment of the present disclosure is a control module for a switching converter that will overcome at least in part the drawbacks of the known art.

One embodiment of the present disclosure is a module for controlling a switching converter, which includes an inductor element and one switch element and is configured to generate an output electric quantity starting from an input electric quantity. The control module includes a switch control circuit configured to generate a command signal for controlling switching of the switch element; and an estimator stage configured to generate an estimation signal proportional to the input electric quantity, based on the command signal and a first input signal indicating a time interval in which the inductor element is demagnetized. The switch control circuit is configured to generate the command signal based on the estimation signal.

DETAILED DESCRIPTION

The present Applicant has noted how, given a switching converter, it is possible to generate a signal proportional to the input voltage Vin(θ), without resorting to a resistive divider, but rather implementing an estimator circuit, which receives at input signals generated in use by the switching converter. This being said, in what follows the present control module is described with reference to a boost converter, even though it may be used also in the case of converters of a different type. In particular, the present control module is described with reference to the boost converter60illustrated inFIG. 7, which in turn is described with reference to the differences with respect to the boost converter50illustrated inFIG. 5. Components of the boost converter60already present in the boost converter50are designated by the same reference numbers, except where otherwise specified.

In detail, the control module of the boost converter60, designated by65, includes an estimator circuit67and is without the first input terminal MOLT. Further, the boost converter60is without the resistive divider16.

In greater detail, the estimator circuit67comprises a current generator68and a first switch70, a second switch72, and a third switch74, as well as a respective resistor76and a respective capacitor78, referred to hereinafter as “estimation resistor76” and the “estimation capacitor78”, respectively.

In particular, the current generator68is arranged between a first internal node N1and a second internal node N2and is configured to inject a constant current I into the second internal node N2.

The first switch70is connected between the second internal node N2and a third internal node N3.

The estimation capacitor78is connected between the third internal node N3and ground. The estimation resistor76is connected to the third internal node N3and to the second switch72, which is further connected to ground. In other words, the second switch72and the estimation resistor76form a sort of series circuit arranged in parallel to the estimation capacitor78. In addition, the third internal node N3is connected to the second input of the multiplier24.

The third switch74is connected between the second internal node N2and ground.

The first, second, and third switches70,72,74are controlled by a first command signal, a second command signal, and a third command signal, respectively. Further, the third command signal is equal to the logic negation of the first command signal. Consequently, it is possible to designate the first, second, and third command signals by A, B and Ā, respectively.

In detail, when A=‘1’, the current generator68is electrically connected to the third internal node N3. Instead, when A=‘0’, the current generator68is connected to ground. Furthermore, when B=‘1’, the estimation capacitor78is connected in parallel to the estimation resistor76. Instead, when B=‘0’, the estimation resistor76is floating.

It is thus possible to designate by TAthe period in which the estimation capacitor78is being charged, i.e., when A=‘1’ and B=‘0’. Likewise, it is possible to designate by TBthe period in which the estimation capacitor78is discharging, i.e., when A=‘0’ and B=‘1’. Once again, it is possible to designate by TABthe period in which the estimation capacitor78is floating, i.e., when A=‘0’ and B=‘0’. In addition, assuming a switching period T(θ)=TA(θ)+TB(θ)+TAB(θ)<<R*C<<1/fline, where flineis the frequency of the supply line, and R and C are, respectively, the resistance of the estimation resistor76and the capacitance of the estimation capacitor78, it is possible to ignore the ripple on the estimation capacitor78, and further it may be assumed that the voltage on the estimation capacitor78follows the waveform of the line voltage. This being said, by applying the charge balance on the estimation capacitor78, we obtain:

ITA⁡(θ)=Ve⁡(θ)R⁢TB⁡(θ)(1)
where R is the resistance of the estimation resistor76. Consequently, the voltage Ve(θ) on the estimation capacitor78itself is

This being said, the calculation of the balance of the magnetic flux on the primary winding L1yields:
Vin(θ)TON(θ)=[(Vout+VF)−Vin(θ)]TFW(θ)  (3)
where TFW(θ) is the period in which demagnetization of the core of the primary winding L1occurs, whereas TON(θ) is the period in which the transistor M is in conduction, and hence the period in which magnetization of the core of the primary winding L1takes place.

Vi⁢n⁡(θ)Vout+VF=TFW⁡(θ)TON⁡(θ)+TFW⁡(θ)=TFW⁡(θ)T⁡(θ)-TR(4)
where Vout+VFis, to a first approximation, constant, and VFis the voltage drop on the output diode D.

Once again with reference to Eq. (2), by imposing TA=TFWand TB=T−TR, we obtain:

Ve⁡(θ)=RI⁢TFW⁡(θ)T⁡(θ)-TR(5)
i.e., the voltage Vc(θ) has the same plot, but for a scale factor, as the input voltage Vin(θ). In fact, from Eqs. (4) and (5) we obtain:

Ve⁡(0)=RI⁢Vi⁢n⁡(θ)(Vout+VF)=KVi⁢n⁡(0)(6)
which demonstrates the direct proportionality present between the voltage Ve(θ) on the estimation capacitor78, and hence at input to the multiplier24, and the input voltage Vin(θ). The voltage Ve(θ) and the voltage Vin(θ) hence have a same phase, and consequently a same time plot.

For the boost converter ofFIG. 7, the control module65includes a logic circuit79that provides the control signals A, Ā, and B based on the signals sZCD and sGD such that A=sFW and B=sZCD, where sFW is a signal that is equal to ‘1’ when there occurs demagnetization of the primary winding L1, and is equal to ‘0’ during the magnetization of the primary winding L1or when the signal sZCd is equal to ‘1’, whereas the signalsZCDis equal to the logic negation of the signal sZCD, which is equal to ‘1’ when the primary winding L1is completely demagnetized, i.e., when the current I(t,θ) in the primary winding L1is zero, and is equal to ‘0’ otherwise.

In greater detail, the signal sZCD may be generated, for example, by the zero-current detection circuit36. In this case, the zero-current detection circuit36is provided not only with the aforementioned output connected to the first logic gate34, but also with a further output, on which it supplies the signal sZCD. In addition, the zero-current detection circuit36continues to provide, on the output connected to the logic gate34, a signal such that on the set input of the flip-flop28the aforementioned signal sS is present.

As regards the signal sFW, it is generated, as illustrated inFIG. 8, on the basis of the signal sZCD and of the signal sGD, which, as has been said, is equal to ‘1’ when the transistor M is in conduction and is equal to ‘0’ when the transistor M is inhibited. In particular, even though not illustrated inFIG. 7, the logic circuit79of the control module65comprises a second logic gate80of a negated OR type, which receives at input the signals sGD and sZCD and generates the signal sFW, and logic inverters configured to generate the signalssZCDandsFW, starting, respectively, from the signals sZCD and sFW. The electrical connections that involve the second logic gate80are not shown, as neither, on the other hand, are the logic inverters connected to the second switch72and the third switch74and designed to generate the signalssZCDandsFW. Examples of the signals sFW, sGD and sZCD are represented inFIG. 9.

As illustrated inFIG. 10, and as mentioned previously, the estimator circuit67may be used also in the case of a flyback converter, here designated by90. In this case, the estimator circuit67is again included in the control module, designated by95. Further, we have A=sFW and B=sGD, for the reasons described in what follows. InFIG. 10, the connections between the estimator circuit67and the zero-current detection circuit36and the output Q of the flip-flop28, as well as the second logic gate80and inverter for producing Ā, are not represented.

In detail, the balance of the magnetic flux on the primary winding, designated by Lp, yields:
Vin(θ)TON(θ)=n(Vout+VF)TFW(θ)  (7)
whence we obtain:

Furthermore, the estimator circuit67may be used also in the case of converters of topologies equivalent to the flyback topology, i.e., converters having the same conversion ratio Vout/Vinas the one that characterizes flyback converters. In this case, the first, second, and third command signals A, B and Ā are the same as what has been described with reference toFIG. 10.

Examples of topologies equivalent to the flyback topology are illustrated synthetically inFIGS. 11a-11d. InFIGS. 11a-11d, components that have already been illustrated previously are designated by the same reference numbers. Further,FIGS. 11a-11dare described briefly, with reference just to the differences with respect to what has been described with reference toFIG. 10. In addition, the primary winding is referred to as “first inductor L1”. Again, the circuit diagrams illustrated inFIGS. 11a-11dare principle circuit diagrams, and hence they are not complete, but rather are limited to showing some components and some electrical connections of the corresponding converters in order to highlight the type of the converters themselves, which substantially depends upon the arrangement of the reactive elements and of the transistor M.

In particular,FIG. 11ashows a buck-boost converter111a, where the anode of the output diode D is connected to the second terminal of the first inductor L1, whereas the output capacitor Coutis connected to the first terminal of the first inductor L1and to the cathode of the output diode. Furthermore, designated inFIG. 11ais by100is a gate-driving stage, which includes the control module95. For the reason explained previously, the gate-driving stage100is illustrated as being without inputs, even though in actual fact it possesses the aforementioned inputs ZCD and CS, as well as the feedback terminal FB, connected in a per se known manner.

FIG. 11bshows a Cuk converter111b, which further comprises an additional capacitor C1, which is connected to the second terminal of the first inductor L1and to the anode of the output diode D, the cathode of which is connected to the source terminal of the transistor M. In addition, the second inductor L2is present, which is connected between the anode of the output diode D and a first terminal of the output capacitor Cout, the second terminal of which is connected to the source terminal of the transistor M.

FIG. 11cshows a SEPIC converter111c, in which the positions of the output diode D and of the second inductor L2are reversed as compared to the Cuk converter111b. Consequently, the anode of the output diode D and a first terminal of the second inductor L2are connected to the terminal of the additional capacitor C1not connected to the first inductor L1. The second terminal of the second inductor L2is connected to the source terminal of the transistor M. The output capacitor Coutis arranged between the cathode of the output diode D and the source terminal of the transistor M.

FIG. 11dshows a Zeta converter111d, also known as “inverted SEPIC”, where the drain and source terminals of the transistor M are connected, respectively, to a first terminal of the input capacitor Cinand to a first terminal of the first inductor L1, the second terminal of which is connected to the second terminal of the input capacitor Cin. The additional capacitor C1is arranged between the first terminal of the first inductor L1and the cathode of the output diode D, the anode of which is connected to the second terminal of the first inductor L1. A first terminal of the second inductor L2is connected to the cathode of the diode D. The output capacitor Coutis arranged between the second terminal of the second inductor L2and the anode of the output diode D.

As illustrated inFIG. 12, the estimator circuit67may be used also in the case of a buck converter120. In particular,FIG. 12shows a principle diagram of the buck converter120, in a way similar to the representation ofFIGS. 11a-11d, i.e., without including all the components and the corresponding connections.

In detail, the drain and source terminals of the transistor M are connected, respectively, to a first terminal of the input capacitor Cinand to the cathode of the output diode D, the anode of which is connected to the second terminal of the input capacitor Cin. A first terminal of the first inductor L1is connected to the cathode of the output diode D, whereas a second terminal of the first inductor L1is connected to a first terminal of the output capacitor Cout, the second terminal of which is connected to the anode of the output diode.

In this case, the estimator circuit67is still included in the gate-driving stage100. Further, we have A=sZCDand B=sGD, for the reasons given below.

In detail, the balance of the magnetic flux on the first inductor L1yields:
[Vin(θ)−Vout]TON(θ)=(Vout+VF)TFW(θ)  (10)
whence, noting that VF<<Vout, we obtain, to a first approximation,

The estimator circuit67may be used also in the case of converters of topologies equivalent to the buck topology. In this case, the first, second, and third command signals A, B and Ā are the same as what has been described with reference toFIG. 12.

An example of a topology equivalent to the buck topology is illustrated synthetically inFIG. 13.

In particular,FIG. 13shows a reverse-buck converter130, where the cathode of the output diode D and a first terminal of the output capacitor Coutare connected to a first input terminal Cin. The anode of the output diode D and the second terminal of the output capacitor Coutare connected, respectively, to a first terminal and a second terminal of the first inductor L1. The drain and source terminals of the transistor M are connected, respectively, to the first terminal of the first inductor L1and to the second terminal of the input capacitor Cin.

FIG. 14shows a further embodiment, described in what follows as regards the differences from the embodiment illustrated inFIG. 7.

In detail, the boost converter, designated by160is without the multiplier24. Furthermore, the current generator, designated by168, of the estimator circuit, designated by167, is of a variable type.

In greater detail, the current generator168receives at input the control voltage Vcgenerated by the error amplifier58. Furthermore, in a per se known manner, the current generated by the current generator168is directly proportional to the control voltage Vc. In other words, designating by ICHthe current generated by the current generator168, we have ICH=GM·Vc, with GMconstant and equal to the transconductance of the current generator168.

The third internal node N3of the estimator circuit167is directly connected to the negative input terminal of the comparator26.

This being said, and recalling that Eqs. (3) and (4) still apply, the charge balance on the estimation capacitor78yields:

ICH⁡(θ)⁢TFW⁡(θ)=VcsREF⁡(θ)R⁡[T⁡(θ)-TR](13)
where Veis set equal to VcsREF.

It follows that:

Applying Eq. (4) and expressing Vin(θ) as Vin,pk·sin (θ), where Vin,pkis the input peak voltage, we finally obtain:

Considering the boost converter60of a known type illustrated inFIG. 5, and designating by VcsREF′ the voltage present on the output of the multiplier24, we have
VcsREF′(θ)=KMVcMULT(θ)=KMKPVcVin,pksin θ  (16)
where KP=R2/(R1+R2), and KMis the gain of the multiplier24. Consequently, considering Eqs. (15) and (16), it may be noted how VcsREF=VcsREF′, if KM·Kp=(GM·R)/(Vout+VF). Examples of signals generated within the boost converter160are illustrated inFIGS. 15aand15b.

In practice, by adopting a current generator variable in a way directly proportional to the control voltage Vc, the voltage Ve(θ) that is obtained on the estimation capacitor78may be equated to the voltage VcsREFgenerated traditionally by the multiplier24, which commonly generates a reference signal that is directly proportional to the control voltage Vcand has the same profile as the voltage present on the input capacitor Cin. It is hence possible to remove the multiplier24, thus simplifying the control module and reducing the area thereof. Furthermore, even thoughFIG. 14refers purely by way of example to a boost converter, the current generator168of a variable type may be used in converters of any type, such as, for example, flyback converters or buck converters and/or equivalent converters. In this way, it is possible to remove the multiplier also in these converters.

Irrespective of the presence or otherwise of the multiplier, any one of the switching converters previously described (hence, including the estimator circuit) may be used for supplying, for example, one or more solid-state lighting devices. For instance,FIG. 16shows a lighting system200, which, without any loss of generality, is connected to an a.c. voltage generator202. The lighting system200comprises the bridge rectifier2and a switching converter204according to any one of the embodiments previously described. Furthermore, the lighting system200comprises a load206formed, for example, by a LED or an array of LEDs.

From what has been described and illustrated previously, the advantages that the present solution affords emerge clearly.

In particular, the present control module enables generation of the voltage VcsREF(θ) in such a way that it has the form of a rectified sinusoid and an amplitude that depends upon the control voltage Vc, without any need to couple a resistive divider to the input capacitor Cin, and hence eliminating the losses associated to the aforesaid resistive divider.

Furthermore, the present control module may be applied also in the case where at input to the converter a d.c. voltage is present, instead of an a.c. voltage, as also in the case where the converter is configured to regulate an output current instead of an output voltage. In the latter case, the feedback circuit generates a signal proportional to the output current, instead of to the output voltage, in a per se known manner.

In addition, in the case where the current generator of the estimator circuit is variable and directly proportional to the control voltage Vc, the control module is without the traditional multiplier.

In conclusion, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the scope of the present disclosure.

For instance, the third switch74may be connected not only to the second internal node N2, but also to the first internal node N1, instead of to ground. Furthermore, the positions within the series circuit of the estimation resistor76and of the second switch72may be reversed.

Furthermore, the present control module may be included also in a switching converter controlled in the so-called “voltage mode”, or else also in a switching converter controlled in average-current mode.

Finally, the present estimator circuit may be used also outside a control module of a switching converter, i.e., independently of subsequent use of the voltage Vewithin a control loop of a switching converter.