Manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor

The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor. In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements regarding the tolerances of the lithography in the gate contact plane are diminished.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor.

BACKGROUND OF THE INVENTION

Although in principle applicable to arbitrary integrated circuits, the following invention and the underlying problems will be explained with respect to integrated memory circuits in silicon technology.

U.S. Patent Publication 2005/0042833 A1, discloses a method of manufacturing an integrated circuit device including a recessed channel transistor. The method includes the steps of defining an active region by forming a trench device isolation region on an integrated circuit substrate, forming a mask pattern on the integrated substrate that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region which is exposed by the mask pattern to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recessed gate that fills the gate trench.

FIG. 15shows schematic planar view of the geometric arrangement of a recessed channel array transistor as an example of the problems underlying the present invention.

InFIG. 15a schematic planar view of the active region RT and the isolation region of a recessed channel array transistor is shown. Two cross-sections of the planar view ofFIG. 15are denoted A–A′ and B–B′, respectively.

FIGS. 15A,7B show two different schematic cross-sections along lines A–A′ and B–B′ ofFIG. 15, respectively, of a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor as an example of the problems underlying the present invention.

FIG. 15Ashows a cross-section in parallel to the current flow direction, whereasFIG. 15Bshows a cross-section perpendicular to the current flow direction.

InFIG. 15A, reference sign1denotes the silicon semiconductor substrate. Provided in the silicon semiconductor substrate1are isolation trenches IT filled with silicon oxide. In the middle of the transistor cell there is a trench5in the flow direction filled with a gate electrode30made of polysilicon. Not shown on the trench wall is a gate dielectric20made of silicon dioxide. Source and drain regions40,50are provided in the surface area on both sides of the trench5. Moreover, reference sign60denotes a gate electrode contact made of tungsten, and70denotes a nitride spacer on both sides of the gate electrode30and the gate electrode contact60.

Problems in such recessed channel array transistors are caused by the overlap of the vertical gate30with the highly doped source/drain regions40,50. This overlap causes high electrical fields that generate leakage currents in the turned-off state of the transistor. Provided that the planar gate and thus the spacer70can be aligned sufficient above the recessed channel device, it can prevent high doping concentrations directly at the gate edge when used as source/drain implant mask. The scalability of the recessed channel array transistor is therefore limited by the alignment of the planar gate.

SUMMARY OF THE INVENTION

The present invention provides an improved manufacturing method for a recessed channel array transistor and corresponding recessed channel array transistor which provide excellent scalability.

In one embodiment, the present invention uses a self-adjusting spacer on the substrate surface to provide the required distance between the gate and the source/drain regions. Thus, the requirements regarding the tolerances of the lithography in the gate contact plane are diminished.

According to a preferred embodiment, the steps of depositing and structuring a gate contact layer and an isolation layer above said gate electrode and the spacers are performed.

According to another preferred embodiment, the step of forming second isolating spacers on the structured gate contact layer and isolation layer above the gate electrode and said spacers is performed.

According to another preferred embodiment, the step of introducing impurities into the substrate in the forming area for providing lightly doped source/drain regions after the step of providing said gate electrode and before the step of forming the spacers is performed.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1shows a schematic planar view of the geometric arrangement of a recessed channel array transistor as a first embodiment of the present invention, and FIGS.1A,B show two different schematic cross-sections along lines A–A′ and B–B′, respectively, ofFIG. 1.

InFIG. 1, reference sign1denotes a semiconductor substrate having a nitride sacrificial layer3on its surface and having isolation trenches IT′ adjoining a forming area RT for said recessed channel array transistor, said isolation trenches IT′ being filled with SiO2as an isolation material which extends to a same upper surface as said substrate1. In particular, such an arrangement may be obtained by a CMP (chemical mechanical polishing) process.

Thereafter, a sacrificial layer opening3ais formed in said sacrificial layer3which extends in the direction B–B′ and exposes said substrate1in the middle part of said forming area RT. The opening3adefines the location of a trench5to be etched in the substrate1in the following step.

FIGS.2A,B to7A,B show the two different schematic cross-sections along lines A–A′ and B–B′, respectively, ofFIG. 1of a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor as the first embodiment of the present invention which starts from FIGS.1A,B.

In the following process step which is depicted inFIGS. 2A,2B, the trench5of the recessed channel array transistor is provided by a dry etch process. Reference sign U denotes the bottom of the trench5. The dry etch process is a selective etching process which etches silicon with high selectivity with respect to the sacrificial layer3which in this step acts as a hard mask.

In the next process step which is depicted inFIGS. 3A,3B, a wet etch is performed for removing a part of the silicon oxide of the isolation trenches IT′ adjacent to the trench5in the direction B–B′ as may be clearly obtained fromFIG. 3B. This wet etch step etches silicon oxide with high selectivity with respect to the silicon of the silicon substrate1. In this wet etch step, the trench5is broadened in the B–B′ direction and underetching areas5aare formed along the B–B′ direction which underetching areas5aare located below the bottom U of the trench5and which are adjacent to the trench5. By providing these under-etching areas5a, the control of the gate over the channel region is improved by the tri-gate arrangement, because the gate can be extended to below the corners at the bottom U.

Subsequently, as shown inFIGS. 4A,4B, a gate dielectric20of silicon dioxide is formed along the substrate1in the trench5. Then, the trench5and the adjacent under-etched areas5ain the isolation trenches IT are filled with the gate electrode30′ made of polysilicon, preferably by a deposition and a following CMP process step. The gate electrode30′ made of polysilicon then extends to the surface of the sacrificial layer3.

With regard toFIGS. 5A,5B, the sacrificial layer layer3of silicon nitride is then removed in a selective etching step. Moreover, a first implantation I1is performed in a self-aligned manner in order to provide a lightly doped drain/source region4on both sides of the trench5as may be obtained fromFIG. 4A.

In a following process step which is depicted inFIGS. 6A,6B, after a subsequent nitride deposition, spacers70′ are formed adjacent to the polysilicon gate electrode30′ which spacers extend along the A–A′ and B–B′ direction. These self-adjusting spacers70′ made of silicon nitride prevent adverse electric field effects in the turned-off state of the recessed channel array transistor and provide the possibility of alignment tolerances in a later gate contact forming step.

According toFIGS. 7A,7B, a gate contact layer60′ and a cap nitride layer80are deposited and structured over the gate electrode30′ and the self-adjusted nitride spacer70′. This process step is not sensitive against slight misalignments of the sacrificial layer for structuring the layers60′,80. In a next process step, second silicon nitride spacers90are formed on the sides of the layer60′,80and on the first spacers70′.

When combining the deposition of said gate contact layer60′ with the formation of the gate contact layer of planar support devices in memory applications, a gate dielectric which is formed before the deposition of said gate contact layer has to be removed from the gate electrode30to ensure electrical contact between gate contact layer60′ and the gate electrode30.

Finally, a second implantation I2is performed for providing source/drain regions4′. Also, this implantation I2is self-adjusted by the isolation trenches IT and the spacers70′. Due to the presence of the lightly doped source/drain areas4, it can be assured that the source/drain regions4′ are suitably connected to the channel region along the trench5periphery. In order to expand the implanted source/drain areas4′, it is possible to perform an additional thermal diffusion step. Thus, by the method of this first embodiment of the present invention, a recessed channel area transistor may be formed which has excellent scaling characteristics.

FIG. 8shows a schematic planar view of the geometric arrangement of a recessed channel array transistor as a second embodiment of the present invention, and FIGS.8A,B show two different schematic cross-sections along lines A–A′ and B–B′, respectively, ofFIG. 8.

In contrast to the above described first embodiment, here a sacrificial layer opening3ais formed in said sacrificial layer3which extends in the direction B–B′ and exposes not only said substrate1in the middle part of said forming area RT, but also the adjoining isolation trenches IT′ in this direction. The opening3adefines the location of a trench5to be etched in the substrate1and in the isolation trenches IT′ in the following step.

FIGS.9A,B to15A,B show the two different schematic cross-sections along lines A–A′ and B–B′, respectively, ofFIG. 8of a manufacturing method for a recessed channel array transistor and a corresponding recessed channel array transistor as the first embodiment of the present invention which starts from FIGS.8A,B.

In the following process step which is depicted inFIGS. 9A,9B, the trench5of the recessed channel array transistor is provided by a dry etch process. Reference sign U denotes the bottom of the trench5. The dry etch process is a selective etching process which etches silicon and silicon oxide with high selectivity with respect to the sacrificial layer3which in this step acts as a hard mask. As may be seen fromFIG. 9B, the isolation trenches IT′ in the B–B′ direction are etched down to the same level as the bottom U of the trench.

In the next process step which is depicted inFIGS. 10A,10B, a wet etch is performed for removing a part of the silicon oxide of the isolation trenches IT′ adjacent to the trench5in the direction B–B′ as may be clearly obtained fromFIG. 10B. This wet etch step etches silicon oxide with high selectivity with respect to the silicon of the silicon substrate1. In this wet etch step, underetching areas5a′ are formed along the B–B′ direction which underetching areas5a′ are located below the bottom U of the trench5and which are adjacent to the trench5. By providing these under-etching areas5a, the control of the gate over the channel region is improved by the tri-gate arrangement, because the gate can be extended to below the corners at the bottom U.

Subsequently, as shown inFIGS. 11A,11B, a gate dielectric20of silicon dioxide is formed along the substrate1in the trench5. Then, the trench5and the adjacent under-etched areas5a′ in the isolation trenches IT′ are filled with the gate electrode30′ made of polysilicon, preferably by a deposition and a following CMP process step. The gate electrode30′ made of polysilicon then extends to the surface of the sacrificial layer3.

With regard toFIGS. 12A,12B, the sacrificial layer layer3of silicon nitride is then removed in a selective etching step. Moreover, a first implantation I1is performed in a self-aligned manner in order to provide a lightly doped drain/source region4on both sides of the trench5as may be obtained fromFIG. 12A.

In a following process step which is depicted inFIGS. 13A,13B, after a subsequent nitride deposition, spacers70′ are formed adjacent to the polysilicon gate electrode30′ which spacers extend along the B–B′ direction. These self-adjusting spacers70′ made of silicon nitride prevent adverse electric field effects in the turned-off state of the recessed channel array transistor and provide the possibility of alignment tolerances in a later gate contact forming step.

According toFIGS. 15A,15B, a gate contact layer60′ and a cap nitride layer80are deposited and structured over the gate electrode30′ and the self-adjusted nitride spacer70′. This process step is not sensitive against slight misalignments of the sacrificial layer for structuring the layers60′,80. In a next process step, second silicon nitride spacers90are formed on the sides of the layer60′,80and on the first spacers70′. When combining the deposition of said gate contact layer60′ with the formation of the gate contact layer of planar support devices in memory applications, a gate dielectric which is formed before the deposition of said gate contact layer has to be removed from the gate electrode30to ensure electrical contact between gate contact layer60′ and the gate electrode30.

Finally, a second implantation I2is performed for providing source/drain regions4′. Also, this implantation I2is self-adjusted by the isolation trenches IT and the spacers70′. Due to the presence of the lightly doped source/drain areas4, it can be assured that the source/drain regions4′ are suitably connected to the channel region along the trench5periphery. In order to expand the implanted source/drain areas4′, it is possible to perform an additional thermal diffusion step.

Thus, by the method of this second embodiment of the present invention, also a recessed channel area transistor may be formed which has excellent scaling characteristics.

Although the present invention has been described with respect to a preferred embodiment, it is not limited thereto, but can be modified in various manners which are obvious for the person skilled in the art.

Particularly, the selection of the materials is only an example and can be varied variously.

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