Shift register and driving circuit of LCD using the same

A shift register is provided, which adopts a shift operation delay for each memory device, or a data conversion control system through the estimation of conversion of data storage state. A driver circuit of LCD is provided, which adopts such a shift register, to thereby prevent instantaneous increase of electric power consumption while preventing EMI. Accordingly, shift registers operate as being sequentially delayed for each memory device or data conversion is minimized, thus preventing instantaneous excessive consumption of electric power.

DETAILED DESCRIPTION OF THE INVENTION The present invention will be explained in more detail with reference to the attached drawings. Referring to FIG. 1 , driving circuit of LCD includes a controller 10 , column driver ICs 20 and scan driver ICs 18 , each of which adopts a shift register. The driver circuit of LCD is configured as follows. A plurality of bits of color data and control signal are transmitted from a predetermined image supply source such as a main body of computer or an image transmitting device, and input to the controller 10 . A power supply unit 12 is arranged to supply constant voltages required for the operation of the controller 10 , a gradation generating unit 14 and a gate voltage generating unit 16 . The gate voltage generating unit 16 is arranged to supply voltages to scan driver ICs 18 so as to generate turn on/off voltages, and the gradation generating unit is arranged to supply gradation voltages to the column driver ICs 20 . The controller 10 generates control signals by using a shift register arranged therein with logic, and determines timing format while delaying data. As a result, column control signals and data output from the controller 10 are distributed to column driver ICs 20 , and scan control signals are output as being distributed to scan driver ICs 18 . In addition, column driver ICs 20 generate a column signal by utilizing data, column control signals and gradation voltage, and applies the generated signal to a liquid crystal panel 22 , while scan driver ICs 18 generate a scan control signal by utilizing a scan control signal and voltages applied from the gate voltage generating unit 16 and applies the generated signal to the liquid crystal panel 22 . The liquid crystal panel 22 then performs an optical shutter function, while forming an image. In the above-described scheme, the controller 10 , column driver ICs 20 and scan driver ICs 18 have shift registers incorporated therein. FIG. 2 illustrates a shift register adopted to such configuration. The shift register illustrated in FIG. 2 is for storing 4-bit data being input in serial, wherein D flip flop is employed as a memory device. Referring to FIG. 2, D flip flops M 0 , M 2 , M 2 , M 3 are connected in line in so as to transmit data according to the order of their arrangement. D flip flop M 0 has an input terminal provided with a delay unit 30 connected thereto, and the other D flip flops M 1 , M 2 , M 3 have clock signal input terminals CLK 1 , CLK 2 , CLK 3 provided with delay units 32 , 34 , 36 respectively connected thereto. Here, the delay unit 36 has delay time “t” set therein, the delay unit 34 has delay time “2t” set therein, and the other delay units 30 , 32 have delay time “3t” set therein. Accordingly, clock signals are input to D flip flop M 3 through clock signal input terminal CLK 4 without delay time, D flip flop M 2 through clock signal input terminal CLK 3 with delay time of “t”, D flip flop M 1 through clock signal input terminal CLK 2 with delay time of “2t”, and D flip flop M 1 through clock signal input terminal CLK 1 with delay time of “3t”. The data is delayed for “3t” time by the delay unit 30 and input the input terminal of D flip flop M 0 . As a result, D flip flop M 3 is firstly synchronized with the clock signal and outputs 5 data, then D flip flop M 2 is synchronized with clock signal with delay time of “t” and outputs data which is stored in D flip flop M 3 . D flip flop M 2 which operates with time delay of “t” stores data of D flip flop M 1 which is synchronized and output with time delay of “t” after operation of data output. D flip flop M 1 which operates with time delay of “2t” stores data of D flip flop M 0 which is synchronized and output with time delay of “t” after operation of data output. D flip flop M 0 stores 1-bit data which is delayed by “3t” through the delay unit 30 . The above-described configuration of D flip flop that starts output side operation prior to the input side operation is to output data of D flip flop with stability and to store safely the data being shifted and input. As shown in FIG. 3 , clock signals for each of D flip flops are input to D flip flops M 2 , M 1 , M 0 , delayed as long as “t”, “2t”, “3t”, respectively, when reference is made to the clock signal applied to D flip flop M 3 . The data applied to D flip flop M 0 is delayed “3t” so as to correspond to the time of applying clock signal. Accordingly, each of D flip flops, i.e., memory devices, operates with time difference arranged therebetween, and have different timings of power requirement for operation. This configuration does not require a large amount of current at the same time. As a consequence, instantaneous power consumption can be reduced, while at the same time reducing EMI caused by the supply of instantaneous large amount of current. The above-described configuration of shift register employing delay units illustrated and explained with reference to FIGS. 2 and 3 , can be also applied to m×n matrix configuration. The shift register of m×n matrix configuration minimizes shifting by checking the state of data being shifted, to thereby decrease instantaneous power consumption and EMI, as shown in FIGS. 4 and 5 . FIG. 4 illustrates 4×4 matrix structured shift register, wherein D flip flops M 00 , M 01 -M 15 as memory devices constituting the shift register are arranged in matrix. The first column of the matrix consists of D flip flops M 00 , M 01 , M 02 , M 03 , the second column of the matrix consists of D flip flops M 04 , M 05 , M 06 , M 07 , the third column of the matrix consists of D flip flops M 08 , M 09 , M 10 , M 1 , and fourth column of the matrix consists of D flip flops M 12 , M 13 , M 14 , M 15 . D flip flops M 00 , M 04 , M 08 , M 12 constituting the first row have input terminals with switching logics 40 , 42 , 44 , 46 , respectively. Switching logics 40 , 42 , 44 , 46 classifies input data D 00 , D 10 , D 20 , D 30 into positive and negative, and selectively outputs the data to the corresponding D flip flop by a first switching control signal. D flip flops M 03 , M 07 , M 11 , M 15 constituting the fourth row have output terminals with switching logics 50 , 52 , 54 , 56 , respectively. Switching logics 50 , 52 , 54 , 56 classifies data output from D flip flops M 03 , M 07 , M 11 , M 15 into positive and negative, and selectively outputs data D 01 , D 11 , D 21 , D 31 by a second switching control signal. Data D 02 , D 12 , D 22 , D 32 obtained by dividing data D 00 , D 10 , D 20 , D 30 and output D 03 , D 13 , D 23 , D 33 of D flip flops M 00 , M 04 , M 08 , M 12 of the first row are input to the shift comparing unit 60 . The shift comparing unit 60 applies, as the first switching control signal, the result of processing the input data using the logic process configured as shown in FIG. 5 , to switching logics 40 , 42 , 44 , 46 , and at the same time inputting a flag signal to the input terminal of D flip flop MFO. To shift the flag signal, D flip flops MF 0 , MF 1 , MF 2 , MF 3 of the counts same as those of column of matrix, constitute a column. D flip flops MF 0 , MF 1 , MF 2 , MF 3 are shift comparing shift registers. The flag signal is shifted passing through D flip flops MF 0 , MF 1 , MF 2 , MF 3 , and input as the second switching control signal of switching logics 50 , 52 , 54 , 56 . Each of D flip flops M 00 , M 01 -M 15 , MF 0 , MF 1 , MF 2 , MF 3 is applied with a clock signal CLK for operation of flip flops. The shift comparing unit 60 consists of exclusive OR gates 70 , 72 , 74 , 76 and a logical combination unit( 80 ). In detail, the exclusive OR gate 70 obtains exclusive logical sum S 0 of data D 02 and D 03 , the exclusive OR gate 72 obtains exclusive logical sum S 1 of data D 12 and D 13 , the exclusive OR gate 74 obtains exclusive logical sum S 2 of data D 22 and D 23 , and the exclusive OR gate 76 obtains exclusive logical sum S 3 of data D 3 2 and D 33 . The logical combination unit 80 consists of four AND gates 82 , 84 , 86 , 88 and an OR gate 90 for logically summing outputs of the four AND gates. The AND gate 82 obtains product of exclusive logical sums S 0 , S 1 , S 2 . The AND gate 84 obtains product of exclusive logical sums S 0 , S 1 , S 3 . The AND gate 86 obtains product of exclusive logical sums SO, S 2 , S 3 . And the AND gate 88 obtains product of exclusive logical sums S 1 , S 2 , S 3 . Outputs of AND gates 82 , 84 , 86 , 88 are logically summed in the OR gate 90 , and input to switching logics 40 , 42 , 44 , 46 and D flip flop MF 0 , as a first switching control signal and a flag signal, respectively. Under the assumption that data “0000” is stored in D flip flops M 00 , M 04 , M 08 , M 12 of the first row, respectively, and data to be input D 00 , D 10 , D 20 , D 30 is “1111”, D flip flops M 00 , M 04 , M 08 , M 12 of the first row shift, when clock signal CLK is input, the stored data “0000” to D flip flops M 01 , M 05 , M 09 , M 13 of the second row and store new data “1111”. However, in this case, all of D flip flops M 00 , M 04 , M 08 , M 12 of the first row shift require current supply for converting from logic “0” to “1”. If D flip flops constituting the matrix perform the above-described data conversion in their entirety, a significant amount of instantaneous power supply is needed. In the first embodiment of the present invention, data D 02 , D 12 , D 22 , D 32 which are divided from the data to be input to the first row, and data D 03 , D 13 , D 23 , D 33 output from D flip flops constituting the first row are compared in the shift comparing unit 60 . This prevents data conversion that may require huge volume of power supply. In other words, the exclusive OR gate 70 compares input data and output data of D flip flop M 00 , and outputs logic “0” if they are the same, and logic “1” if two data if they are different. The other exclusive OR gates 72 , 74 , 76 compare input data and output data of D flip flops M 04 , M 08 , M 12 , and outputs “0” or “1” as a logic result. 1 TABLE 1 AND AND AND S0 S1 S2 S3 gate(84) gate(86) gate(88) 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 1 1 1 Each of exclusive OR gates 70 , 72 , 74 , 76 have outputs S 0 , S 1 , S 2 , S 3 as shown in Table 1, and AND gates 82 , 84 , 86 , 88 accordingly have outputs as shown in Table 1. In other words, AND gates 82 , 84 , 86 , 88 output logic “1” when input data and output data of D flip flops D 00 , D 04 , D 08 , D 12 of the first row are compared and a change is found in the set state. Then, the OR gate 90 outputs a first switching control signal and a flag signal as logic “1”. Switching logics 40 , 42 , 44 , 46 inverts the state of input data and outputs the result to D flip flop M 00 , M 04 , M 08 , M 12 , when the first switching control signal is fed from the shift comparing unit 60 as logic “1”. Then, the flag signal for recognizing conversion of data for corresponding row is input to D flip flop MF 0 constituting the shift comparing shift register. The flag signal to be stored in D flip flop MF 1 is synchronized with clock CLK and shifted like other data stored in D flip flops D 00 , D 04 , D 08 , D 12 of the first row. When data state change is estimated in three or more D flip flops of each row, the data being input is converted and stored in the corresponding D flip flop, and the corresponding flag is stored. In this manner, data conversion of flip flops can be maintained minimum, while at the same time reducing instantaneous power supply, preventing the occurrence of EMI. When thus-stored data and flag are shifted, D flip flops M 03 , M 07 , M 11 , M 15 of the last row output data, and the flag signal is output from the last D flip flop of the shift comparing shift register. The flag signal output from D flip flop MF 3 is a second switching control signal, and is input to switching logics 50 , 52 , 54 , 56 . Therefore, switching logics 50 , 52 , 54 , 56 invert data output from D flip flops M 03 , M 07 , M 11 , M 15 constituting the last row of the shift register and output data D 01 , D 11 , D 21 , D 31 when the flag signal, i.e., the second switching control signal, is applied as logic “1”. When data is stored as “0000” to D flip flops M 00 , M 04 , M 08 , M 12 of the first row and data D 00 , D 10 , D 20 , D 30 are input as “1111”, switching logics 40 , 42 , 44 , 46 invert the state of data D 00 , D 10 , D 20 , D 30 and input “0000” to D flip flops M 00 , M 04 , M 08 , M 12 . Here, the flag signal generated together with the first switching control signal applied to switching logics 40 , 42 , 44 , 46 , is stored in D flip flop MFO of the shift comparing shift register. When such data and flag signal are synchronized with the clock signal, gradually shifted, output from D flip flops M 03 , M 07 , M 11 , M 15 of the last row, and input to switching logics 50 , 52 , 54 , 56 , data of logic “0000” is inverted into the original state “1111” by the second switching control signal output from D flip flop MF 3 of the shift comparing shift register. The above-described shift register can be employed for controllers, column driver ICs, and scan driver ICs of LCD with configuration shown in FIG. 1 . By a method of checking and estimating delayed or input data and shifted data, a phenomenon where a large amount of power is instantaneously supplied to shift registers arranged within controllers, column driver ICs and scan driver ICs, can be prevented while at the same time preventing the occurrence of EMI. The present invention has an advantage in that shift registers operate as being sequentially delayed for each memory device or data conversion is minimized, thus preventing instantaneous excessive supply of electric power. With the shift register of the present invention adopted to components of LCD, EMI problem can be solved.