Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailable

Clock generation circuit generating multiple divided signals satisfying respective desired offsets. A phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The circuit divides the PLL output by a corresponding divisor to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least an associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and with respect to a time reference signal otherwise. This arrangement is extended to use the internal time reference signal even for the cases where the reference clock is present by blocking the reference clock while the output systems across PLLs are aligned using the internal time reference signal to ensure desired offsets across different PLLs with a small uncertainty.

PRIORITY CLAIM

The instant patent application is related to and claims priority from the co-pending India provisional patent application entitled, “Managing Input to Output Delays Across Single and Multiple PLLs Having the Same Input Clock”, Ser. No.: 202141050628, Filed: 3 Nov. 2021, inventors: Raja Prabhu, et al; which is incorporated in its entirety herewith to the extent not inconsistent with the description herein.

BACKGROUND

Technical Field

Embodiments of the present disclosure relate generally to phase-locked loops (PLLs), and more specifically to generating divided signals from phase-locked loop output when reference clock is unavailable.

Related Art

Phase-locked loops (PLLs) are frequently used to generate clock signal(s). A PLL receives an input (reference) clock and generates an output clock (PLL output) locked in phase with the input signal, but at a frequency that is a desired multiple of the frequency of the input clock. PLLs are used in various communication scenarios, as is well known in the relevant arts.

Divided (clock) signals are often generated from PLL outputs, with each divided signal having a time period that is an integral multiple of that of the PLL output. The environments requiring such divided signals often specify a respective phase offset, for example from input clock, that each divided signal is to satisfy.

However, there are often situations when the input clock becomes unavailable. Aspects of the present disclosure are directed to generating divided signals in such situations.

DETAILED DESCRIPTION

A clock generation circuit provided according to an aspect of the present disclosure generates multiple divided signals, each satisfying a respective desired offset specified potentially as a specification from an external source. In an embodiment, a phase locked loop (PLL) is used to generate a PLL output having a frequency which is a desired multiple of that of a reference clock. The clock generation circuit receives a corresponding desired time offset for each divided signal.

The clock generation circuit divides the PLL output by a corresponding integer or fractional number (division ratio/divisor) to generate a corresponding divided signal, wherein each divided signal is offset from a common reference by at least the associated desired time offset. The common reference is timed with respect to the reference clock when the reference clock is available and is timed with respect to a time reference signal when the reference clock is not available. The time reference signal is generated external to (i.e., independent of, for example, as not being derived from) the reference clock.

According to another aspect, when the reference clock is available, an edge of each divided signal is timed to the associated time offset immediately after an edge of the PLL output, the edge of the PLL output closely following an edge of the reference clock. When the reference clock is not available, an edge of each divided signal is timed to the associated time offset immediately after an edge of the PLL output, with the edge of the PLL output closely following an edge of the time reference signal. The time reference signal is used similarly for generating all divided signals when the reference clock is not available.

Thus, both when the reference clock is available and not available, a relative phase difference is maintained between the divided signals, as required by an external specification. However, when the reference clock is available, all the divided signals are generated timed with reference to an edge of the reference clock, but further synchronized with the (high frequency) PLL output. Specifically, each divided clock is synchronized with a PLL output edge that closely follows (e.g., one or two PLL output clock cycles) the edge of the reference clock (in addition to satisfying the associated offset requirement). When the reference clock is not available, the time reference signal is substituted for the corresponding function provided by the reference clock.

According to another aspect, the dividing operation may entail counting a number of clock cycles of the PLL output from a first time instance specified satisfying the timing noted above.

According to another aspect a multiplexor is used to select one of the reference clock and the time reference signal as the common reference under the control of a select signal (which indicates whether or not the reference signal is available). A first flip-flop synchronizes a first reset signal with the common reference to generate a first synchronized signal. A second flip-flop synchronizes the first synchronized signal with the PLL output to generate a second synchronized signal and a delay block delays the second synchronized signal by the associated time offset to set the first time instance from which the counting starts.

According to another aspect, the PLL operates in a hold-over mode when the reference clock is not available, wherein the hold-over mode entails the PLL continuing to generate the PLL output without further using the reference clock. Accordingly, the divided signals are generated based on the same timing reference provided by reference clock prior to entering the hold-over mode. However, upon receiving an external reset signal (when the PLL is operating in the hold-over mode), the first reset signal is generated to cause the time reference signal thereafter to control the timing of the divided signals. In an embodiment, the time reference signal is realized in the form of an internal clock signal generated within the clock generation circuit.

2. Example Component

FIG.1is a block diagram illustrating the details of an example component which can be extended according to several aspects of the present disclosure. The block diagram is shown containing PLL100and dividers110-1through110-M, which are explained with respect to the timing diagram ofFIG.2for conciseness. The dividers will individually or collectively be referred by reference number110, as will be clear from the context. Similar convention is employed for the respective associated signals also.

PLL100is shown receiving an input clock fref101and generating PLL output fout131. PLL100may be implemented in a known way. Each divider110divides fout131by respective ratio105received from external sources to generate corresponding divided signal195.

Each ratio105can be an integer or an integer plus a fractional component, and in addition any pair of ratios are required to be related to each other by a fixed ratio. Thus, fout131is shown locked to fref101with a frequency of 10 times that of fref101for illustration. Divided signals195-1and195-2are respectively shown with division factors 4 and 2 respectively, thereby satisfying the fixed ratio requirement as an example.

The phase of each divided signal195is controlled by offset106, also received from external sources. Thus, divided signals195-1an195-2are shown with corresponding offsets Ø1and Ø2in relation to a rising edge of fref101assuming these offset values are received on106-1and106-2respectively.

However, there are often scenarios when fref101is unavailable, but there is a requirement at least in some environments (such as PLLs in telecom systems) to continue to generate divided signals with similar requirements noted above. For example, a receiving array of time-interleaved Analog to Digital Converters (ADCs) will still require the SYSREF (input reference clock) and Device Clocks (divided signals) at the correct ratio of frequency and more importantly, relative delays between the divided signals from the PLL. Aspects of the present invention operate to provide divided signals even in such scenarios as well, as described below in further detail.

3. Generating Divided Signals

FIG.3is a flowchart illustrating the manner in which divided signals are generated according to an aspect of the present disclosure. The flowchart is described with respect to the components ofFIG.1merely for illustration. However, many of the features can be implemented in other components/systems and/or other environments also without departing from the scope and spirit of several aspects of the present disclosure, as will be apparent to one skilled in the relevant arts by reading the disclosure provided herein.

In step310, PLL100generates PLL output131having a frequency which is a desired multiple of that of a reference clock101. In step320, a corresponding desired offset for each divided signal is received. In step330, a controller checks whether reference clock101has become unavailable, i.e., a previously operative clock signal is now unavailable. Control passes to step340if the clock is found to continue to be available and to step350otherwise.

In step340, the divided signals are generated with offset by respective desired offsets with respect to reference clock. Thus reference clock provides a common (time) reference for all the divided signals when the reference clock is available. Control then passes to step330.

In step350, an internal clock is generated and in step360, the divided signals are generated with respective desired offsets with respect to the internal clock. It may be appreciated that the edges of the internal clock provide a common reference for controlling the relative timing of the divided signals. However, other time reference signals (e.g., a set of pulses) can be employed, as suited in the corresponding environments. Control then passes to step330.

Thus, the approach ofFIG.3operates to ensure the divided signals (of corresponding desired division factors) are provided at least with relative phase differences maintained, while using another time reference as common reference when the reference clock101is unavailable.

It may be observed that the flowchart ofFIG.3operates under the assumption that a previously operative reference clock signal has become unavailable (for example, after an external reset). However, there can be situations when the reference clock (fref) is unavailable initially, i.e., at the first instance of wake-up of the system containing the PLL. Such a situation may arise, for example, due to a physical disruption in a telecommunication line supplying the reference clock, etc. Aspects of the present disclosure provide divided signals with the pre-specified relative phase delays in such situations as well, as described below with examples.

4. Clock Generation Circuit

FIG.4is a block diagram of a clock generation circuit implemented according to several aspects of the present disclosure, in an embodiment. Clock generation circuit400is shown containing multiplexer (MUX)405, flip-flops415and420, internal clock generator460, controller450, PLL100, and output-generators480-1through480-2. Each output-generator480in turn is shown containing flip-flop430, delay block435and counter410.

Only representative components (e.g., number of output-generators) are shown for conciseness. The specific blocks/components of clock generation circuit400ofFIG.4are shown merely by way of illustration. Other embodiments of clock generation circuit400can be implemented with other blocks/components (analog, digital and/or a combination of analog and digital), as would be apparent to one skilled in the relevant arts by reading the disclosure herein. For example, although blocks460,405,450,415and420are shown as being implemented external to PLL100, in alternative embodiments, the blocks may be implemented as part of PLL100.

Internal clock generator460generates a (high-precision and high-stability) internal clock411(fint), which is used as described below. Internal clock411is used to re-time divided signals upon receipt of a logic high on path409, as described below. Internal clock411may be a series of pulses used to synchronize the divided clocks, or internal clock411may be a continuous clock. There are no requirements on the frequency of this clock, as the key aspect is to be able to use this as an event marker to align with suitable relative delay across all the divided outputs from PLL100.

MUX405is shown as receiving input (reference) clock, fref (101) and clock fint (411). MUX405forwards one of fref (101) and fint (411) as a common (time) reference on path406, based on the logic value of select-signal451. In an embodiment, when the value of select-signal451is a logic HIGH, MUX405forwards fint (411) as the selected common reference, and fref (101) otherwise.

Controller450determines whether or not the reference clock is available on path101, and controls select-signal451to cause fref101to be selected when the reference clock is available and fint411otherwise. Thus, controller450controls the selection of common reference on path406. In an embodiment, signal443is used by external components to indicate the presence of another clock signal (not shown, but would be provided as an input to MUX405), and controller may control select signal451to select such another clock signal as the common reference on path406. Alternatively, controller450might be completely controlled using on-chip internal indicators. In one embodiment, such indicators could be the various clock loss and frequency drift monitors for reference clock101.

In operation, controller450may be pre-programmed to consider fref (101) as a primary clock and fint (411) as a secondary/redundant/back-up clock. Thus, by default (e.g., upon power-up of PLL100), controller450may program the binary value of select-signal451to cause MUX405to forward fref on path406. Controller450continues to check if fref (101) is functional (and thus available). On determining that fref (101) has failed (is invalid/nonfunctional) controller450may program the binary value of select-signal451to cause MUX405to forward fint on path406.

Flip-flop415is clocked by common reference generated by MUX405on path406. Flip-flop415receives a reset signal on path409at its D input and generates output (Q), sync-1, on path416. In an embodiment, flip-flop415is implemented as a positive edge triggered flip-flop. Accordingly, flip-flop415operates to synchronize reset signal (409) with a first rising edge of fref (101) immediately following the receipt of reset signal on path409. In this embodiment, reset signal409is shown as being received from PLL100. However, in alternative embodiments, reset signal409may also be an external signal that is available from a different reference such as another sub-system on the chip, or an external signal received by the chip.

Similarly, flip-flop420operates to synchronize sync-1(416) with a first edge of fout (131) immediately following the first rising edge of fref (101) noted above. As may be readily observed, the reset signal is forwarded synchronized with the first positive edge following the arrival of the reset signal. The term “immediately following” is used to express such timing relationship.

On the other hand, when a small number of clock cycles (e.g., 2 in the embodiments below) can elapse before the output is provided, the term “closely following” is used instead. In general, given that PLL output131operates at a much higher frequency than the reference signal101and divided signals495, the resynchronized signals closely follow the corresponding edge of the common reference.

Each output-generator480receives PLL output fout on path131, sync-2on path421and generates divided signal on corresponding path495. Flip-flop430is clocked by PLL output, and operates to further synchronize sync-2to fout (131), with the generated signal being provided on path432. Flip-flop430is used to synchronize sync-2signal received on path421with respect to fout (131). This is done to reduce the uncertainty that may be introduced due to routing delays between different output-generators480. In other words, signal sync-1may be subject to routing delays and may be received at different times at different output-generators480. Hence, a second set of synchronization is needed with two flip-flops420and430that work on signal fout (131) which is typically the highest frequency clock available in the system. Even after synchronizing sync-1(416) with fout by using flip-flop420, there exists a possibility that each output-generator480may receive sync-2(421) at different time instances because of routing delays, and accordingly each output-generator480may start generating divided signal495(after applying the associated offset) asynchronously, thus resulting in not being able to maintain the specified relative phase difference (between divided signals). Using two flip-flops takes care of any such problems. It is also worth noting that the use of a cascade of two flip-flops ensures that there are no metastability issues in the synchronization with respect to clock fout (131). For example, the signal sync-1(416) may be metastable with respect to fout (131); hence signal sync-1(416) cannot be sent directly to flip-flops430and it is essential to add the single unique flip flop420.

Delay block435delays the signal received on path432by a magnitude represented on106. As delay block435is clocked by fout131, the magnitude may also be converted into a number of clock cycles of fout. The output of the delay block thus represents a timing corresponding to an offset (106) from a specific edge of fout, with the specific edge closely following (2 clock cycles in the example) an edge of the common reference. Delay block360may also be implemented in a known way (e.g., using counters, delay lines, RC delay, inverter delay, etc.). In such a case, the delays are not in the unit of cycles of fout (131,) and a more generalized implementation may be employed.

Counter410divides the frequency of fout131by a desired divisor (which may be integer or fraction). The operation of counter410may be viewed as counter410counting a number of clock cycles of fout131starting from a time instance specified on path436. When the number equals the integer value received on path105(when the divisor is an integer) or when the average number of clock cycles of fout equals the fractional divisor received on path105(when the divisor is a fraction), one cycle of the divided signal is deemed to have elapsed. Thus, counter410operates to divide the frequency of fout (131) by a desired ratio (based on divide-code105, specified by user via corresponding means not shown) starting from a time specified on path436. The generated divided signal (f-div) is provided on path495.

From the description above, it may be appreciated that reset signal409trigger re-timing of the divided clock signals. Though not noted above, reset signal409can be used to re-time when reference signal101becomes available also (after being unavailable). Reset signal can be used to support operation during a hold-over mode, briefly described below first.

5. Support in Hold-Over Mode

Hold-over mode refers to a duration in which PLL100continues to generate PLL output131with characteristics similar to those before entering the hold-over mode. Thus, PLL100may enter the hold-over mode when fref101is unavailable.

In general, in hold-over mode, PLL100operates in open-loop mode, in which the oscillator (not shown) inside PLL100does not respond to input clock fref101(i.e., does not respond to changes in fref101). The last-known valid state of oscillator (not shown) in PLL100is stored and used to continue to generate fout (131). PLL operation in hold-over mode is described in more detail in in U.S. Pat. No. 10,514,720, entitled, “Hitless Switching When Generating an Output Clock Derived from Multiple Redundant Input Clocks”.

According to an aspect of the present disclosure, upon entry of hold-over mode, no re-timing is immediately initiated. Rather, PLL100generates reset signal409only after receipt of external reset on path471, for example, after PLL100is powered-up and reaches steady state. External reset471may be generated with, and transition to, appropriate logic levels based on corresponding conventions, and would be well known. Accordingly divided signals are re-timed according to internal clock fint411after external reset is received on path471. The corresponding timing relationships in an embodiment are illustrated below.

6. Timing Relationship when Reference Clock is Unavailable

FIG.5is a timing diagram (not to scale) illustrating the manner in which divided signals are generated from PLL output when input clock is unavailable.FIG.5shows example waveforms of fref (101), fint (411), fout (131), select-signal (451), common reference (406), first-reset (409), sync-1(416), sync-2(421), fdiv-1(495-1) and fdiv-2(495-2).

PLL100is in steady state until time t501with or without fref (101) being available (as described below). Thus, prior to t501, select-signal (451) is at logic LOW. Accordingly, clock fref101is shown as having been selected as the output of MUX405on path406. Divided signals fdiv-1(495-1) and fdiv-2(495-2) are shown as being generated with respective desired (programmed) ratios. Internal clock fint (411) generated by internal clock generator460ofFIG.4is shown as being always ON and available, and having a same frequency as fref (101). However, internal clock fint (411) is shown with a phase shift with respect to fref (101) by phase Ødiff.

Between time t501and t503, input (reference) clock fref (101) becomes unavailable. Once the clock loss is detected (at t503), PLL100is forced to operate in hold-over mode by a component (not shown) internal to PLL100. In an alternative scenario, clock fref (101) may not be present at all, and hence PLL100operates in hold-over state from the start of operation (for example, prior to t501). In such scenarios, since there is no last-known valid state of oscillator, PLL operates using an (internal) oscillator (not shown) to generate PLL output (fout). PLL100is shown as operating in hold-over mode starting at time t503. Starting at time t503, fref (101) is indicated by the dotted portion merely to illustrate the phase of fref had it been available.

At t503(after a finite interval of time after loss of clock fref), controller450detects the clock loss. Accordingly, controller450generates a logic HIGH on path451(select-signal) starting at t503. As a result, clock fint131is shown as having been selected as the output of MUX405on path406from t503.

At t507, it is assumed that PLL100is reset by signal received on path471. A ‘reset’ may include one or more of a full power cycle (power-down and power-up sequence) of the part containing PLL100, a hard reset of the chip containing PLL100, etc. Output-generators480are held in reset starting at t507. This time instant can be extended to a case where this was the first wake-up ever of PLL100and hence select signal451was switched to logic HIGH after this instant once it is realized that input clock fref (101) is not present.

On power-up, since fref101is unavailable, PLL100operates in hold-over mode as noted above. Also, clock fint411is selected as the output of MUX405on path406.

At t511, PLL100generates reset signal (asynchronously) on path409to release output-generators480from reset. Signal409is provided to the D input of flip-flop415. The Q output of flip-flop415is the synchronized signal sync-1(416) (synchronized with a rising edge (E1) of fint occurring at time t513), shown asserted starting at time t513. Sync-1(416) is forwarded as the D input of flip-flop420. Accordingly, the Q output of flip-flop420is the synchronized signal sync-2(421), shown asserted starting at time t515(at the occurrence of the rising edge O1of fout131immediately following edge E1of fint411).

Each flip-flop430receives sync-2(421) as the D input, and generates respective Q output on path432at t517, synchronized with rising edge O2of fout, closely following rising edge E1of fint411. In other words, an edge of each divided signal is timed to the respective offset immediately after edge O2of fout (131), where edge O2closely follows (i.e., by a small number of cycles of fout, e.g., 1-2 clock cycles of fout as depicted in the illustrative embodiment) edge E1of clock fint (411).

At t517, upon receiving output of flip-flop430on path432, each delay block435delays the reset of the corresponding output-generator480by the respective pre-determined offset (106). Accordingly, delay block435-1delays the release of reset of output-generator480-1by offset Ø1(i.e., till time t523), while delay block435-2delays the release of reset of output-generator480-2by offset Ø2(i.e., till time t525).

As noted above, there may be situations where the reference clock (fref) is unavailable initially. In such scenarios, the PLL starts operation in a hold-over mode. However, since there is no last-known valid state of oscillator (generating PLL output), the PLL operates using another (internal) oscillator to generate PLL output (fout), and the divided signals are synchronized to fout (now generated based on another internal oscillator) even if the reference clock is not present.

Once reference clock fref (101) becomes available, all divided signals get synchronized to reference clock (fref). Such an arrangement is typically used in the form of a nested or cascaded architecture of PLLs. It may be appreciated that aspects of the present disclosure provide divided signals that have a fixed and known relative phase delay at every wake-up in such scenarios as well.

According to another aspect of the present disclosure, output-generators of multiple PLLs operating on a common input (e.g., fref101) may be synchronously released from reset, as will be described next with respect toFIG.6.

7. Generating Divided Signals of Multiple PLLs

FIG.6is a block diagram illustrating the implementation details of generating divided signals of a multi-PLL clock generation circuit600, in an embodiment of the present disclosure.FIG.6is shown containing sync block610, PLLs600-1through600-X, flip-flops620-1through620-X. Each PLL600in turn is shown associated with a corresponding set of output-generators680. Thus, PLL600-1is shown associated with output-generators680-1-1through680-1-A, PLL600-2is shown associated with output-generators680-2-1through680-2-B, while PLL600-X is shown associated with output-generators680-N-1through680-N-Y.

Sync block610contains components corresponding to blocks405,450,460and415ofFIG.4, and is common to PLLs600-1through600-X. In other words, in the illustrative embodiment depicted inFIG.6, there is only one instance of sync block610for PLLs600-1through600-X. Sync block610is shown as receiving signals609and fref (601), and generating signal616. Signal fref (601) corresponds to signal101shown inFIG.4. Sync block610also generates internal clock/set of pulses, fint (not shown). Signal609represents a common release-from-reset signal, which is asserted to signal release-from-reset only when all PLLs are ready and generating the respective output clocks.

Sync block610operates to synchronize signal609with fref (601) if present, or to fint, if fref (601) is not present. The selection of fref or fint for synchronization is performed by a multiplexer (inside sync block610, but not shown inFIG.6) equivalent to MUX405ofFIG.4.

Each PLL600operates as PLL100ofFIG.4, and would have all the components/blocks of PLL400ofFIG.4, except blocks405,450,460and415. Each output-generator680operates as out-generator480ofFIG.4. Flip-flops520-1operate in a manner similar to flip-flop420ofFIG.4and the description is not repeated here in the interest of brevity.

Each PLL600is shown as receiving fref on path601, and generating a corresponding PLL output fout on path631. Signals631correspond to signal131shown inFIG.4. As noted above and as depicted inFIG.6, signal616is common across all PLLs. Each PLL600synchronizes signal616with respect to the respective fout (631) to generate corresponding re-timed signal621, and the uncertainty between PLLs is reduced to a small number of cycles of the various fout (631). In an embodiment, the small number is 2. As noted above, since signal fout (631) is a very high frequency signal, the relative uncertainty is very small. Signal621is in turn used to release respective counters (not shown) in output-generator680from reset. In this manner, output-generators of multiple PLLs operating on a common reference (fref or fint) may be synchronously released from reset.

In an embodiment, a controller external to circuit600reads the lock status (indicative of PLL having reached the steady state noted above) of each PLL, and sets signal609to logic HIGH only after all PLLs have reached steady state. In an alternative embodiment, such operations may be effected by firmware that may be stored in a non-volatile memory within circuit600.

In an alternative embodiment, multi-PLL clock generation circuit600ofFIG.6is implemented by replicating clock generation circuit400ofFIG.4as many times as the number of PLLs in circuit600. A common sync block610is not implemented. In the embodiment, each of such replicated circuits400could be ready and generating the corresponding output clock asynchronously with respect to each other. Therefore, fref (601), even if available, is temporarily blocked inside each of the replicated circuits400following every external reset (including first wake-up) indicator (such as471ofFIG.4) until such time as when all the PLLs have become ready and generating respective output clocks. Similarly, internal clock fint of each replica circuit400is also blocked for such duration. Blocking of signals fref and fint in each replica circuit400may be implemented in a known way (e.g., by using switches in the input paths to the multiplexer.

In an alternative scenario, fref may continue to be blocked (despite being available), and divided signals of all PLLs may be synchronized to internal clock (or set of pulses), fint, noted above. This may be useful at least in some environments where it is required that divided signals across multiple PLLs be synchronized to a common reference other than fref. Such an objective may be achieved, for example, by controlling select signal of equivalent MUX405in a known way.

It may be appreciated that since the individual PLLs wake-up (initialize and reach steady state) in a sequence (and not all together), blocking fref (601) and fint in each replica circuit400until all PLLs reach steady state ensures that the relative alignment between the divided signals across different PLLs is maintained across resets. In the absence of such blocking, each PLL upon wake-up would have started generating the corresponding divided signals, and therefore the divided signals from the multiple PLLs would not start synchronous to each other, but at different time instances.

The above technique ensures that for a multi-PLL system, the input reference clock (even when it is present) can be blocked inside the chip to emulate a loss of clock and this arrangement can be used to ensure that the output-generators are released together or with a known phase difference even when they are from different PLLs. This provides a unique use case where the divided signals across PLLs can be aligned or provided at known relative delays even for the cases where the input reference clocks are present. This is useful for cases where the PLLs are enabled (reach a steady state) in a sequence such that if the input reference clock was present all the time, the output-generators would start producing the divided signals as soon as the PLL is enabled. With this scheme, the output-generators will wait for the common internally generated reference to start the output dividers (counters).

Clock generation circuit400/600implemented as described above can be incorporated in a larger device or system as described briefly next.

FIG.7is a block diagram of an example system containing a PLL implemented according to various aspects of the present disclosure, as described in detail above. System700is shown containing SyncE (Synchronous Ethernet) timing cards (710and720) and line cards1through N, of which only a single line card730is shown for simplicity. Line card730is shown containing jitter attenuator PLL740and SyncE PHY Transmitters745-1and745-2. The components ofFIG.7may operate consistent with the Synchronous Ethernet (SyncE) network standard. As is well known in the relevant arts, SyncE is a physical layer (PHY)-based technology for achieving synchronization in packet-based Ethernet networks. The SyncE clock signal transmitted over the physical layer should be traceable to an external master clock (for example, from a timing card such as card710or720). Accordingly, Ethernet packets are re-timed with respect to the master clock, and then transmitted in the physical layer. Thus, data packets (e.g., on path731and741) are re-timed and transmitted without any time stamp information being recorded in the data packet. The packets may be generated by corresponding applications such as IPTV (Internet Protocol Television), VoIP (Voice over Internet Protocol), etc.

Thus, line card730receives data packets on paths731and741, and forwards the respective packets on outputs746and747after the packets are re-timed (synchronized) with a master clock.

The master clock (711/clock1) is generated by timing card710. Timing card720generates a redundant clock (721/clock-2) that is to be used by line cards730and750upon failure of master clock711. Master clock711and redundant clock721are provided via a backplane (represented by numeral770) to each of lines cards730and750.

In line card730, jitter attenuator PLL740may be implemented as clock generation circuit400described above in detail, and receives clocks711and721, with outputs of a pair of output-generators connected respectively to SyncE PHY Transmitters745-1and745-2. PLL740generates output clocks771and781, which are used to synchronize (re-time) packets received respectively on paths731and741, and forwarded as re-timed packets on paths746and747. Any specified relative phase difference between outputs on paths746and747may be repeatably maintained across resets of line card730even when clocks711/721become unavailable. Another example is the case of an array of data converters such that745-1and745-2are two data converters that need the clocks to have a similar relative phase difference.

While in the illustrations ofFIGS.1,4,6and7, although terminals/nodes are shown with direct connections to (i.e., “connected to”) various other terminals, it should be appreciated that additional components (as suited for the specific environment) may also be present in the path, and accordingly the connections may be viewed as being “electrically coupled” to the same connected terminals.

Accordingly, in the instant application, the power and ground terminals are referred to as constant reference potentials, the source (emitter) and drain (collector) terminals of transistors (though which a current path is provided when turned on and an open path is provided when turned off) are termed as current terminals, and the gate (base) terminal is termed as a control terminal.