SEMICONDUCTOR PACKAGE

A semiconductor package according to an embodiment includes a first semiconductor chip, a second semiconductor chip, a first dielectric film surrounding the first semiconductor chip and the second semiconductor chip; first vias; second vias; a bridge chip; a second dielectric film surrounding the bridge chip and having an upper surface and a lower surface opposite to the upper surface; and a third via, some of the first vias are electrically connected to some of the bridge chip pads, some of the second vias are electrically connected to others of the bridge chip pads, and the passivation layer includes a same material as a material of the first dielectric film.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0080676, filed on Jun. 22, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.

BACKGROUND

Embodiments of the present disclosure relate to a semiconductor package, and more particularly, to a semiconductor package having a small thickness and improved reliability.

Recently, in the electronic product market, demand for portable devices is rapidly increasing, and as a result, miniaturization and weight reduction of electronic components mounted on these electronic products are continuously required. In order to reduce the size and weight of electronic components, a semiconductor package mounted therein is required to process high-capacity data while the volume of the semiconductor package is small.

SUMMARY

Embodiments of the present disclosure provide a semiconductor package having a small thickness in which a first chip and a second chip are connected to a bridge chip through direct bonding, the first chip, the second chip, and the bridge chip are fixed through a first oxide film and a first dielectric film instead of a molding member and a substrate, and thermal characteristics and reliability are enhanced by utilizing a second carrier substrate as a heat dissipation member.

Embodiments of the present disclosure are not limited to solving the above-mentioned problems, and other problems that are solved by embodiments of the present disclosure may be clearly understood by those skilled in the art from the description below.

According to embodiments of the present disclosure, a semiconductor package is provided. The semiconductor package includes: a first semiconductor chip; a second semiconductor chip spaced apart from the first semiconductor chip in a horizontal direction; a first dielectric film surrounding the first semiconductor chip and the second semiconductor chip; first vias extending from a lower surface of the first dielectric film to a lower surface of the first semiconductor chip; second vias extending from the lower surface of the first dielectric film to a lower surface of the second semiconductor chip; a bridge chip on the lower surface of the first dielectric film and electrically connected to each of the first semiconductor chip and the second semiconductor chip, the bridge chip including bridge chip pads and a passivation layer surrounding the bridge chip pads; a second dielectric film surrounding the bridge chip and having an upper surface and a lower surface opposite to the upper surface of the second dielectric film; and third vias extending from the lower surface of the second dielectric film to the upper surface of the second dielectric film, wherein a first set of the first vias is electrically connected to a first set of the bridge chip pads, wherein a first set of the second vias is electrically connected to a second set of the bridge chip pads, and wherein the passivation layer includes a same material as a material of the first dielectric film.

According to embodiments of the present disclosure, a semiconductor package is provided. The semiconductor package includes: a first semiconductor chip; a second semiconductor chip spaced apart from the first semiconductor chip in a horizontal direction; a first dielectric film surrounding the first semiconductor chip and the second semiconductor chip; a carrier substrate that contacts an upper surface of the first semiconductor chip, an upper surface of the second semiconductor chip, and an upper surface of the first dielectric film; first vias extending from a lower surface of the first dielectric film to a lower surface of the first semiconductor chip; second vias extending from the lower surface of the first dielectric film to a lower surface of the second semiconductor chip; a bridge chip on the lower surface of the first dielectric film and electrically connected to each of the first semiconductor chip and the second semiconductor chip, the bridge chip including bridge chip pads and a passivation layer surrounding the bridge chip pads; a second dielectric film surrounding the bridge chip and having an upper surface and a lower surface opposite to the upper surface of the second dielectric film; and third vias extending from the lower surface of the second dielectric film to the upper surface of the second dielectric film, wherein a first set of the first vias is electrically connected to a first set of the bridge chip pads, wherein a first set of the second vias is electrically connected to a second set of the bridge chip pads, and wherein the passivation layer includes a same material as a material of the first dielectric film, the first set of the first vias and the first set of the bridge chip pads include a same material as each other, and the first set of the second vias and the second set of the bridge chip pads include a same material as each other.

According to embodiments of the present disclosure, a semiconductor package is provided. The semiconductor package includes: a first semiconductor chip; a second semiconductor chip spaced apart from the first semiconductor chip in a horizontal direction; a first dielectric film surrounding the first semiconductor chip and the second semiconductor chip; at least one third dielectric film on a upper surface of the first semiconductor chip and an upper surface of the second semiconductor chip; a carrier substrate including a fourth dielectric film that contacts an upper surface of the at least one third dielectric film and an upper surface of the first dielectric film; first vias extending from a lower surface of the first dielectric film to a lower surface of the first semiconductor chip; second vias extending from the lower surface of the first dielectric film to a lower surface of the second semiconductor chip; a bridge chip on the lower surface of the first dielectric film and electrically connected to each of the first semiconductor chip and the second semiconductor chip, the bridge chip including bridge chip pads and a passivation layer surrounding the bridge chip pads; a second dielectric film surrounding the bridge chip and having an upper surface and a lower surface opposite to the upper surface of the second dielectric film; third vias extending from the lower surface of the second dielectric film to the upper surface of the second dielectric film, and a first bump on the lower surface of the second dielectric film and electrically connected to one of the third vias, wherein a first set of the first vias is electrically connected to a first set of the bridge chip pads, wherein a first set of the second vias is electrically connected to a second set of the bridge chip pads, wherein the passivation layer includes a same material as a material of the first dielectric film, the first set of the first vias and the first set of the bridge chip pads include a same material as each other, and the first set of the second vias and the second set of the bridge chip pads include a same material as each other, and wherein lower surfaces of the first set of the first vias and upper surfaces of the first set of the bridge chip pads are in contact with each other, lower surfaces of the first set of the second vias and upper surfaces of the second set of the bridge chip pads are in contact with each other, and each of the first dielectric film and the second dielectric film includes one from among a silicon oxide film and a silicon nitride film.

DETAILED DESCRIPTION

Hereinafter, non-limiting example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Like reference numerals are used for elements that are substantially identical to each other, and the descriptions thereof may not be repeated.

FIG.1is a schematic cross-sectional view illustrating a semiconductor package10according to an embodiment.FIG.2is a schematic bottom view of the semiconductor package10ofFIG.1.

Referring toFIGS.1and2, the semiconductor package10according to an embodiment includes a first semiconductor chip100, a second semiconductor chip200, a first dielectric film300, a first via310, a second via330, a bridge chip400, a second dielectric film500, a third via510, and a second carrier substrate700.

The first semiconductor chip100and the second semiconductor chip200may be positioned under the second carrier substrate700. According to some embodiments, the first semiconductor chip100and the second semiconductor chip200may be disposed to be in contact with a lower surface of the second carrier substrate700. At this time, the meaning of being in contact may include direct contact between upper surfaces of the first semiconductor chip100and the second semiconductor chip200, respectively, with the lower surface of the second carrier substrate700as well as contacting the upper surfaces of the first semiconductor chip100and the second semiconductor chip200, respectively, with the lower surface of the second carrier substrate700by interposing a dielectric film therebetween.

The first semiconductor chip100and the second semiconductor chip200may be spaced apart from each other in a horizontal direction. The first semiconductor chip100and the second semiconductor chip200may include memory chips or logic chips. In this case, both the first semiconductor chip100and the second semiconductor chip200may be the same type of chip or may be different types of chips. For example, both the first semiconductor chip100and the second semiconductor chip200may be memory chips, or one of the first semiconductor chip100and the second semiconductor chip200may be a memory chip and the other one may be a logic chip.

The memory chip may be, for example, a volatile memory chip such as dynamic random access memory (DRAM) or static random access memory (SRAM), or a non-volatile memory chip such as phase-change random access memory (PRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM). In addition, the logic chip may be, for example, a microprocessor (e.g., a central processing unit (CPU), a graphics processing unit (GPU), or an application processor (AP)), an analog device, or a digital signal processor.

In the drawings, an X-axis direction and a Y-axis direction represent directions parallel to the upper or lower surface of the first dielectric film300, and the X-axis direction and the Y-axis direction may be directions perpendicular to each other. A Z-axis direction may indicate a direction perpendicular to the upper or lower surface of the first dielectric film300. In other words, the Z-axis direction may be a direction perpendicular to an X-Y plane.

Also, in the drawings, a first horizontal direction, a second horizontal direction, and a vertical direction may be understood as follows. The first horizontal direction may be understood as the X-axis direction, the second horizontal direction may be understood as the Y-axis direction, and the vertical direction may be understood as the Z-axis direction.

According to some embodiments, the upper surface of the first dielectric film300may be positioned at substantially the same level in the vertical direction (Z) as the upper surface of the first semiconductor chip100and the upper surface of the second semiconductor chip200. In other words, the upper surface of the first dielectric film300may be positioned on substantially the same plane as the upper surface of the first semiconductor chip100and the upper surface of the second semiconductor chip200.

According to some embodiments, the lower surface of the first dielectric film300may be at a level in the vertical direction (Z) lower than the lower surface of the first semiconductor chip100and the lower surface of the second semiconductor chip200. In this case, the first dielectric film300may cover the lower surfaces of each of the first semiconductor chip100and the second semiconductor chip200. . . .

The first via310may be a through electrode penetrating the first dielectric film300from the lower surface of the first dielectric film300to the lower surface of the first semiconductor chip100. The first via310may have a shape extending from the lower surface of the first dielectric film300toward the lower surface of the first semiconductor chip100. In some embodiments, the first via310may have a pillar shape extending in the vertical direction Z. However, the shape of the first via310is not limited thereto. For example, the first via310may have a tapered shape in which a horizontal width increases or decreases as the level in the vertical direction Z decreases.

A plurality of the first vias310may be provided. Each of the plurality of the first vias310may extend from the lower surface of the first semiconductor chip100to the lower surface of the first dielectric film300. Some of the plurality of the first vias310may be electrically connected to a plurality of the third vias510and other ones of the plurality of the first vias310may be electrically connected to the bridge chip400. In some embodiments, each of the plurality of the first vias310connected to the plurality of the third vias510may not overlap the bridge chip400in the vertical direction Z, and each of the plurality of the first vias310connected to the bridge chip400may overlap the bridge chip400in the vertical direction Z.

According to some embodiments, each of the plurality of the first vias310may be connected to each of the plurality of the third vias510. That is, one first via310may be connected to one third via510. However, embodiments of the present disclosure are not limited thereto. For example, the first via310and the third via510may be connected at different ratios according to signal configuration.

According to some embodiments, each of the plurality of the first vias310connected to the bridge chip400may be connected to a plurality of bridge chip pads410formed on an upper surface of the bridge chip400. At least some of the plurality of the first vias310may overlap the bridge chip pads410in the vertical direction Z.

A plurality of the second vias330may be provided. Each of the plurality of the second vias330may extend from the lower surface of the second semiconductor chip200to the lower surface of the first dielectric film300. Some of the plurality of the second vias330may be electrically connected to a plurality of the third vias510and other ones may be electrically connected to the bridge chip400. In some embodiments, each of the plurality of the second vias330connected to the plurality of the third vias510may not overlap the bridge chip400in the vertical direction Z, and each of the plurality of the second vias330connected to the bridge chip400may overlap the bridge chip400in the vertical direction Z.

According to some embodiments, each of the plurality of the second vias330may be connected to each of the plurality of the third vias510. However, embodiments of the present disclosure are not limited thereto. For example, the second via330and the third via510may be connected at different ratios according to signal configuration.

According to some embodiments, each of the plurality of the second vias330connected to the bridge chip400may be connected to a plurality of bridge chip pads410formed on the upper surface of the bridge chip400. At least some of the plurality of the second vias330may overlap the bridge chip pads410in the vertical direction Z.

At least some of the plurality of the first vias310and at least some of the plurality of the third vias510may be connected to each other without a separate connecting member (e.g., a metal pillar, a solder bump, etc.), and at least some of the plurality of the second vias330and other ones of the plurality of the third vias510may also be connected to each other without a separate connecting member.

At least some of the plurality of the first vias310and the bridge chip pads410may be connected to each other without a separate connection member, and in this case, the at least some of the plurality of the first vias310and the bridge chip pads410may be connected through direct bonding. The direct bonding may include a dielectric-to-dielectric bonding, a copper-to-copper bonding, and a hybrid bonding in which the dielectric-dielectric bonding and the metal-metal bonding occur together. The direct bonding may be a diffusion bonding in which, after two interfaces including the same material are arranged to face each other, metal atoms or dielectric materials in contact with each other are brought into contact with each other and heated to form an integral body through diffusion.

A lower surface of the first via310and an upper surface of at least one of the bridge chip pads410may be positioned to face each other, and the lower surface of the first dielectric film300surrounding the plurality of the first vias310and an upper surface of a passivation layer430surrounding the bridge chip pads410may face each other. That is, the lower surface of the first via310is in contact with at least one of the bridge chip pads410, and the lower surface of the first dielectric film300surrounding the plurality of the first vias310may contact the upper surface of the passivation layer430surrounding the bridge chip pads410.

At least some of the plurality of the second vias330and the bridge chip pads410may be connected to each other without a separate connection member, and the at least some of the plurality of the second vias330and the bridge chip pads410may be connected through direct bonding.

The bridge chip400may be positioned under the first dielectric film300. The bridge chip400may electrically connect the first semiconductor chip100to the second semiconductor chip200. The bridge chip400is a chip connecting different types of semiconductor chips, and the different types of chips may include process chips, logic chips, memory chips, and the like. The bridge chip400may, for example, perform as a bridge electrically connecting a logic chip and a memory chip and may have a pitch corresponding to a fine pitch of each of the logic chip and the memory chip.

According to some embodiments, the bridge chip400may be electrically connected to at least some of the plurality of the first vias310and at least some of the plurality of the second vias330. The bridge chip400may include the plurality of bridge chip pads410, a wiring pattern420, and the passivation layer430. The bridge chip pads410may be disposed on the upper surface of the bridge chip400. The upper surface of the bridge chip400may be a surface facing the first dielectric film300. The plurality of bridge chip pads410may be spaced apart from each other in the horizontal direction. Among the plurality of bridge chip pads410, the bridge chip pads410connected to the plurality of the first vias310may include the same material as the plurality of the first vias310, and among the plurality of bridge chip pads410, the bridge chip pads410connected to the plurality of the second vias330may include the same material as the plurality of the second vias330.

In this case, the plurality of the first vias310and the plurality of the second vias330may include the same material but are not limited thereto. For example, the plurality of the first vias310and the plurality of the second vias330may include different materials.

The passivation layer430may surround the bridge chip pads410. The passivation layer430may be positioned on the upper surface of the bridge chip400. The passivation layer430may surround side surfaces of the bridge chip pads410. An upper surface of each of the bridge chip pads410may be exposed upward from the passivation layer430in the vertical direction Z.

The passivation layer430may include any one from among silicon oxide and silicon nitride. The passivation layer430may include the same material as the first dielectric film300. For example, when the first dielectric film300includes silicon oxide, the passivation layer430may include silicon oxide.

In some embodiments, each of the bridge chip pads410may include a plurality of layers. For example, each of the bridge chip pads410may include a copper layer made of copper (Cu), a nickel layer made of nickel (Ni), and a silver layer made of silver (Ag), and the copper layer, the nickel layer, and the silver layer may be stacked one after another in the vertical direction Z.

The wiring pattern420may be formed inside the bridge chip400and electrically connect different bridge chip pads410to each other. According to some embodiments, the wiring pattern420may include a bridge circuit. The bridge circuit may have a pitch corresponding to a fine pitch of pads formed on each of different semiconductor chips and may perform as a bridge electrically connecting the semiconductor chips to each other.

For example, the first semiconductor chip100may be electrically connected to the bridge chip pads410located on the left side of the upper surface of the bridge chip400through the plurality of the first vias310located on the right side of the lower surface of the first semiconductor chip100. In addition, the second semiconductor chip200may be electrically connected to the bridge chip pads410located on the right side of the upper surface of the bridge chip400through the plurality of the second vias330located on the left side of the lower surface of the second semiconductor chip200. Because the wiring pattern420electrically connects the bridge chip pads410, the first semiconductor chip100and the second semiconductor chip200may be electrically connected to each other.

The second dielectric film500is positioned below the first dielectric film300and may surround the bridge chip400. According to some embodiments, the second dielectric film500may include one from among silicon nitride and silicon oxide. The second dielectric film500has an upper surface and a lower surface opposite to the upper surface, and the upper surface of the second dielectric film500may be at substantially the same level as the upper surface of the bridge chip400(or the upper surface of the bridge chip pads410) in the vertical direction Z. The lower surface of the second dielectric film500may be at substantially the same level as the lower surface of the bridge chip400in the vertical direction Z.

The first dielectric film300and the second dielectric film500may include the same material but are not limited thereto. For example, the first dielectric film300and the second dielectric film500may include different materials. For example, the first dielectric film300may include silicon oxide and the second dielectric film500may include silicon nitride.

The plurality of the third vias510may extend from the lower surface to the upper surface of the second dielectric film500. According to some embodiments, each of the plurality of the third vias510may have a tapered shape in which a horizontal width increases as the level in the vertical direction Z decreases. However, it is not limited thereto. For example, each of the plurality of the third vias510may have a shape in which the horizontal width decreases as the level in the vertical direction Z decreases or may have a column shape in which the horizontal width is constant.

The plurality of third the via510may be provided, wherein some of the plurality of the third vias510may be connected to at least some of the plurality of the first vias310and others of the plurality of the third vias510may be connected to at least some of the plurality of the second vias330. Lower surfaces of the plurality of the third vias510may be exposed downward from the second dielectric film500in the vertical direction Z. First bumps530may be connected to the lower surface of the plurality of the third vias510. The first bumps530may have a pillar structure, a ball structure, or a solder layer.

The second carrier substrate700may be disposed on the upper surface of the first semiconductor chip100, the upper surface of the second semiconductor chip200, and the upper surface of the first dielectric film300. The second carrier substrate700may include silicon (Si). The carrier substrate may be a substrate for fixing the first semiconductor chip100and the second semiconductor chip200in a process of manufacturing the semiconductor package10and may be a substrate that is removed again during the manufacturing process. However, the second carrier substrate700of the semiconductor package10according to some embodiments is not removed during the manufacturing process and may function as a part of a final structure of the semiconductor package10. The second carrier substrate700may include silicon (Si). Because a thickness of the second carrier substrate700may be freely adjusted in the vertical direction Z through grinding or the like, a thickness of the semiconductor package10in the vertical direction Z may be adjusted according to demand or suitable for preventing warpage. In addition, the second carrier substrate700may function as a heat dissipation member that discharges heat generated inside the semiconductor package10to the outside.

The second carrier substrate700may be coupled to the upper surface of the first semiconductor chip100, the upper surface of the second semiconductor chip200, and the upper surface of the first dielectric film300through direct bonding, which will be described later in detail with reference toFIG.3.

In the semiconductor package10according to some embodiments, because the bridge chip400is connected to the first semiconductor chip100and the second semiconductor chip200through direct bonding, even if the first semiconductor chip100, the second semiconductor chip200, and the bridge chip400have a fine pitch, they may be easily bonded. In addition, because the bridge chip400is mounted on the second dielectric film500instead of a conventional substrate, and because the first dielectric film300surrounds the first semiconductor chip100and the second semiconductor chip200, it is possible to prevent voids from occurring inside the semiconductor package10. In addition, because an underfill process may be omitted by the first dielectric film300and the second dielectric film500, the manufacturing process may be simplified and the thickness of the semiconductor package10in the vertical direction Z may be formed to be thin.

FIG.3is an enlarged view illustrating coupling of the first semiconductor chip100, the second semiconductor chip200, and the first dielectric film300ofFIG.1to the second carrier substrate700.

Referring toFIG.3, each of the first semiconductor chip100and the second semiconductor chip200may include third dielectric films110and210. The third dielectric films110and210may be formed on the upper surfaces of each of the first semiconductor chip100and the second semiconductor chip200. In other words, the upper surface of the first semiconductor chip100and the upper surface of the second semiconductor chip200may be coated with the third dielectric films110and210. In some embodiments, the third dielectric films110and210may include the same material as the first dielectric film300. For example, when the first dielectric film300includes silicon oxide, the third dielectric films110and210may include silicon oxide. Accordingly, the upper surface of the first dielectric film300, the upper surface of the first semiconductor chip100, and the upper surface of the second semiconductor chip200that contact the lower surface of the second carrier substrate700may all include the same material. Here, the upper surface of the first semiconductor chip100and the upper surface of the second semiconductor chip200may be understood as the upper surfaces of third dielectric films110and210unless otherwise specified.

A fourth dielectric film710may be formed on the lower surface of the second carrier substrate700. The fourth dielectric film710may include the same material as the first dielectric film300. The lower surface of the second carrier substrate700may be coated with the fourth dielectric film710. The lower surface of the second carrier substrate700may contact the upper surface of the first dielectric film300, the upper surface of the first semiconductor chip100, and the upper surface of the second semiconductor chip200. Here, the lower surface of the second carrier substrate700may be understood as the fourth dielectric film710unless otherwise specified.

The second carrier substrate700may be coupled to the first dielectric film300, the first semiconductor chip100, and the second semiconductor chip200through direct bonding. Because the first dielectric film300, the upper surface of the first semiconductor chip100, the upper surface of the second semiconductor chip200, and the lower surface of the second carrier substrate700all include the same material, they may be combined through dielectric-dielectric bonding.

The third dielectric films110and210may be dielectric films formed by applying a dielectric material on the upper surface of each of the first semiconductor chip100and the second semiconductor chip200, respectively, but are not limited thereto, and may be previously existing dielectric films, such as silicon oxide films formed on a silicon surface.

Similarly, the fourth dielectric film710may be a dielectric film formed by coating a dielectric material on the lower surface of the second carrier substrate700but may also be a previously existing dielectric film, such as a silicon oxide film formed on a silicon surface.

FIG.4is a schematic cross-sectional view of a semiconductor package11according to an embodiment. Hereinafter, in the description of the semiconductor package11ofFIG.4, descriptions identical to descriptions about the semiconductor package10given above with reference toFIGS.1and2may be omitted.

Referring toFIG.4, the semiconductor package11may include a first semiconductor chip100, a second semiconductor chip201, a first dielectric film300, a plurality of first via310, a plurality of second via331, a bridge chip400, a second dielectric film500, a plurality of third via510, and a second carrier substrate700.

According to some embodiments, a thickness of the first semiconductor chip100in the vertical direction Z may be greater than a thickness of the second semiconductor chip201in the vertical direction Z. When the second carrier substrate700has a flat plate shape, because an upper surface of the first semiconductor chip100and an upper surface of the second semiconductor chip201are in contact with a lower surface of the second carrier substrate700, the upper surface of the first semiconductor chip100and the upper surface of the second semiconductor chip201are at the same level in the vertical direction Z to each other, and a lower surface of the first semiconductor chip100may be at a level lower than a level of a lower surface of the second semiconductor chip201in the vertical direction Z.

A length of each of the plurality of the first vias310in the vertical direction Z may be less than a length of each of the plurality of the second vias331in the vertical direction Z. According to some embodiments, lower surfaces of the plurality of the first vias310and lower surfaces of the plurality of the second vias331are at substantially the same level in the vertical direction Z, and upper surfaces of the plurality of the first vias310are at a level lower than a level of the upper surfaces of the plurality of the second vias331in the vertical direction Z. In some embodiments, a length of the first semiconductor chip100in the first horizontal direction X may be less than a length of the second semiconductor chip201in the first horizontal direction X. A footprint (e.g., an area when viewed from a top view) of the first semiconductor chip100may be less than a footprint of the second semiconductor chip201.

FIG.5is a schematic cross-sectional view of a semiconductor package12according to an embodiment. Hereinafter, in the description of the semiconductor package12ofFIG.5, descriptions identical to descriptions about the semiconductor package10given above with reference toFIGS.1and2may be omitted.

Referring toFIG.5, the semiconductor package12may include a first semiconductor chip100, a second semiconductor chip200, a first dielectric film300, a plurality of first via310, a plurality of second via330, a bridge chip400, a second dielectric film500, a plurality of third via510, a second carrier substrate700, external connection terminals850, and a first substrate800.

The first substrate800may be positioned below the second dielectric film500and electrically connected to the plurality of the third vias510formed inside the second dielectric film500through the first bumps530. The first substrate800may be formed based on or include, for example, a ceramic substrate, a printed circuit board (PCB), an organic substrate, or the like. In some embodiments, the first substrate800may be a redistribution substrate formed through a redistribution process.

The external connection terminals850may be located on at least one pad disposed on a lower surface of the first substrate800. The external connection terminals850may be electrically connected to the at least one pad. The external connection terminals850may be electrically connected to wiring patterns formed inside the first substrate800through the at least one pad. The external connection terminals850may be electrically connected to an external device, for example, a motherboard. Accordingly, the semiconductor package12may be electrically connected to an external device through the external connection terminals850.

The external connection terminals850may include a solder ball. However, according to embodiments, the external connection terminals850may have a structure including a pillar and a solder. The external connection terminals850may include at least one from among copper (Cu), silver (Ag), gold (Au), and tin (Sb).

According to some embodiments, the first semiconductor chip100and the second semiconductor chip200may be different types of chips. For example, the first semiconductor chip100may be a memory chip and the second semiconductor chip may be a logic chip. In some embodiments, the first semiconductor chip100may include a high bandwidth memory (HBM) DRAM chip. In this case, the first semiconductor chip100may be a chip stack structure in which HBM DRAM chips are stacked in the vertical direction Z.

When the semiconductor package12further includes a first substrate800and the first semiconductor chip100and the second semiconductor chip200include different types of chips, the semiconductor package12may be understood as a 2.3D package. The 2.3D package may be understood as a package in which heterogeneous semiconductor chips, that is, the first semiconductor chip100and the second semiconductor chip200, are spaced apart from each other in the horizontal direction and the bridge chip400electrically connects the first semiconductor chip100to the second semiconductor chip200instead of an interposer substrate.

FIG.6is a schematic cross-sectional view of a semiconductor package13according to an embodiment. Hereinafter, in the description of the semiconductor package13ofFIG.6, descriptions identical to descriptions about the semiconductor package10given above with reference toFIGS.1and2may be omitted.

Referring toFIG.6, the semiconductor package13may include a first semiconductor chip100, a second semiconductor chip200, a first dielectric film300, a plurality of first via310, a plurality of second via330, a bridge chip400, the second dielectric film500, a plurality of third via510, a second carrier substrate700, a second substrate900, a third semiconductor chip1000, conductive pillars950, an adhesive layer550, and a molding member970.

The adhesive layer550may be configured to surround the first bumps530and to fix the molding member970and the second dielectric film500. The adhesive layer550may include, for example, a nonconductive film (NCF) or an underfill material layer.

The conductive pillars950may be positioned below the second dielectric film550and electrically connected to the first bumps530. The conductive pillars950may have a shape extending in the vertical direction Z. The conductive pillars950may pass through the molding member970and extend in the vertical direction Z. The conductive pillars950may be, for example, through mold vias or conductive posts. The conductive pillars950may include, for example, copper (Cu). The conductive pillars950may electrically connect redistribution patterns910to the first bumps530.

The third semiconductor chip1000may be mounted on the second substrate900and may be spaced apart from the conductive pillars950in the horizontal direction. The third semiconductor chip1000may be a memory chip or a logic chip. In some embodiments, the third semiconductor chip1000may be an application specific integrated circuit (ASIC) chip.

The molding member970may surround the third semiconductor chip1000and the conductive pillars950. The molding member970may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin containing a reinforcing material such as an inorganic filler, specifically ajinomoto build-up film (ABF), FR-4, BT, and the like, but the molding member970may be formed from a molding material such as an epoxy molding compound (EMC) or a photosensitive material such as photo imageable encapsulant (PIE). In some embodiments, a portion of the molding member970may include an insulating material such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film.

The second substrate900may be positioned below the molding member970and may be electrically connected to the conductive pillars950and the third semiconductor chip1000. The second substrate900may be formed based on or include a ceramic substrate, a PCB, an organic substrate, or the like but is not limited thereto. For example, the second substrate900may be a redistribution substrate formed through a redistribution process. Hereinafter, it is assumed and described that the second substrate900is a redistribution substrate formed through a redistribution process.

The second substrate900may include redistribution insulating layers920and the redistribution patterns910. The second substrate900may include the redistribution insulating layers920mutually stacked in the vertical direction Z. The redistribution insulating layers920may include, for example, photo imageable dielectric (PID) or photosensitive polyimide (PSPI).

The redistribution patterns910may be provided in the redistribution insulating layers920. The redistribution patterns910may be formed to penetrate the redistribution insulating layers920from an upper surface to a lower surface of the second substrate900. Accordingly, the redistribution patterns910may serve as an electrical connection passage penetrating the upper and lower surfaces of the second substrate900. That is, the third semiconductor chip1000positioned on the upper surface of the second substrate900and external connection terminals990positioned on the lower surface of the second substrate900may be electrically connected. In addition, the redistribution patterns910may electrically connect the conductive pillars950to the third semiconductor chip1000and electrically connect the conductive pillars950to the external connection terminals990.

The redistribution pattern910may include a metal, for example, copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc. or an alloy of metals, but the redistribution pattern910is not limited thereto. In some embodiments, the redistribution patterns910may be formed by depositing a metal or a metal alloy on a seed layer including copper (Cu), titanium (Ti), titanium nitride (TiN), or titanium tungsten (TiW).

The redistribution patterns910may include a redistribution line pattern and a redistribution via pattern. The redistribution patterns910may have a multilayer structure in which redistribution line patterns and redistribution via patterns are alternately stacked.

The redistribution line patterns may have a shape extending in the horizontal direction along at least one of upper and lower surfaces of each of the redistribution insulating layers920. The redistribution via patterns may have a shape extending through the redistribution insulating layers920in the vertical direction Z. The redistribution via patterns may electrically connect redistribution line patterns located at different levels in the vertical direction Z. In some embodiments, at least some of the redistribution line patterns may be integrally formed with some of the redistribution via patterns.

The semiconductor package13may be a package on package type semiconductor package because the semiconductor package13further includes the conductive pillars950, the molding member970, the third semiconductor chip1000, the second substrate900, etc.

FIGS.7A to7Mare cross-sectional views illustrating a method of manufacturing the semiconductor package10, according to an embodiment. Hereinafter, a method of manufacturing the semiconductor package10will be described with reference toFIGS.7A to7M.

Referring toFIG.7A, the first semiconductor chip100and the second semiconductor chip200are provided on a first carrier substrate600. The first dielectric film300and the plurality of the first vias310passing through the first dielectric film300may be positioned between the first carrier substrate600and the first semiconductor chip100, and the first dielectric film300and the plurality of the second vias330may be positioned between the first carrier substrate600and the second semiconductor chip200. According to some embodiments, each of the first dielectric films300provided under each of the first semiconductor chip100and the second semiconductor chip200may be spaced apart from each other in the first horizontal direction X.

Referring toFIG.7B, the first dielectric film300may be deposited by coating a dielectric material on the upper surface of the first carrier substrate600. In some embodiments, an upper surface of the first dielectric film300may be substantially at the same level as or higher than the upper surfaces of the first semiconductor chip100and the second semiconductor chip200in the vertical direction Z.

Referring toFIG.7C, thicknesses of the first semiconductor chip100, the second semiconductor chip200, and the first dielectric film300in the vertical direction Z are reduced. For example, the thicknesses of the first semiconductor chip100, the second semiconductor chip200, and the first dielectric film300in the vertical direction Z may be adjusted through a grinding process or a chemical mechanical polishing (CMP) process.

Referring toFIGS.7D and7E, after adjusting the thicknesses of the first semiconductor chip100, the second semiconductor chip200, and the first dielectric film300in the vertical direction Z, the second carrier substrate700is attached such that the second carrier substrate700contacts the upper surface of each of the second semiconductor chip200and the third semiconductor chip1000. The second carrier substrate700may be coupled to upper surfaces of the first semiconductor chip100, the second semiconductor chip200, and the first dielectric film300through direct bonding. After the second carrier substrate700is coupled to the upper surfaces of the first semiconductor chip100, the second semiconductor chip200, and the first dielectric film300, as shown inFIG.7E, the resultant product is turned over so that the second carrier substrate700is located at the bottom. After that, the first carrier substrate600is removed from the first semiconductor chip100and the second semiconductor chip200.

Hereinafter, an upper surface and a lower surface are defined based onFIG.7E. For example, a surface referred to as a lower surface inFIGS.7A and7Dmay be understood as an upper surface inFIG.7Eand below.

Referring toFIG.7F, after the first carrier substrate600is removed, the bridge chip400may be mounted on the upper surfaces of the first semiconductor chip100and the second semiconductor chip200. According to some embodiments, the bridge chip400may be connected to the first semiconductor chip100and the second semiconductor chip200through hybrid bonding. In this case, the passivation layer430of the bridge chip400may include the same material as a material of the first dielectric film300, the bridge chip pads410connected to the plurality of the first vias310may include the same material as the plurality of the first vias310, and the bridge chip pads410connected to the plurality of the second vias330may include the same material as a material of the plurality of the second vias330. Accordingly, the bridge chip400may be coupled to the first semiconductor chip100and the second semiconductor chip200through hybrid bonding in which dielectric-dielectric bonding and metal-metal bonding occur together.

Referring toFIGS.7G and7H, the second dielectric film500is formed on the first dielectric film300to cover the bridge chip400. The second dielectric film500may be formed to cover the upper surface of the bridge chip400or only cover side surfaces of the bridge chip400. The second dielectric film500may include the same material as a material of the first dielectric film300but is not limited thereto. For example, the second dielectric film500may include a different material from a material of the first dielectric film300. After forming the second dielectric film500, the thicknesses of the second dielectric film500and the bridge chip400in the vertical direction Z may be reduced through a grinding process or a CMP process.

Referring toFIGS.71and7J, a photoresist layer1100is formed on the upper surface of the second dielectric film500. The photoresist layer1100may include a pattern formed through an exposure process and a development process. After forming the photoresist layer1100, openings OP may be formed in the second dielectric film500through an etching process. In this case, the photoresist layer1100may act as a hard mask. The openings OP may extend from the upper surface to the lower surface of the second dielectric film500, and the upper surfaces of the plurality of the first vias310and the upper surfaces of the plurality of the second vias330may be exposed upward in the vertical direction Z by the openings OP. According to some embodiments, the openings OP may have a shape in which a horizontal width decreases as a level in the vertical direction Z decreases.

Referring toFIGS.7K and7L, the plurality of the third vis510may be formed by filling the openings OP formed in the second dielectric film500with a metal material. The plurality of the third vias510may have a shape in which a horizontal width decreases as the level in the vertical direction Z decreases. The plurality of the third vias510may have substantially the same thickness as a thickness of the bridge chip400in the vertical direction Z. After forming the plurality of the third vias510, the first bumps530are formed on the upper surface of the third vias510.

Referring toFIG.7M, after forming the first bumps530, the thickness of the second carrier substrate700in the vertical direction Z is adjusted. The thickness of the second carrier substrate700in the vertical direction Z may be reduced through a grinding process or a CMP process. Because the second carrier substrate700includes silicon, the thickness of the second carrier substrate700in the vertical direction Z may be adjusted without a separate limitation. The second carrier substrate700is not finally removed and may function as a heat dissipation member that discharges heat generated inside the semiconductor package10to the outside.

While non-limiting example embodiments of the present disclosure have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.