Single-event upset immune frequency divider circuit

A single-event upset immune frequency divider circuit is disclosed. The single-event upset immune frequency divider circuit includes a dual-path shift register, a dual-path multiplexor, and a summing circuit. The dual-path shift register has a clock input, one signal input pair and multiple signal output pairs. The dual-path multiplexor has multiple signal input pairs and one output pair. The signal input pairs of the dual-path multiplexor are respectively connected to the signal output pairs of the dual-input shift register. The dual-path multiplexor selects one of the signal output pairs of the dual-path shift register for feeding back into the signal input pair of the dual-path shift register. The summing circuit then sums the signal input pair of the dual-path shift register to generate an output clock signal that is a fraction of the frequency of an input clock signal at the clock input of the dual-path shift register.

BACKGROUND OF THE INVENTION

1. Technical Field

The present invention relates to electronic circuits in general, and in particular to frequency divider circuits. Still more particularly, the present invention relates to a single-event upset immune frequency divider circuit.

2. Description of the Related Art

Frequency divider circuits are commonly used in electronic devices that include counting circuits, phase-locked loop circuits, and/or frequency synthesizer circuits. Generally speaking, frequency dividers are used to generate signals of relatively lower frequencies by dividing a high frequency signal already existed within an electronic system. For example, if a 50 MHz signal is desired from a 100 MHz clock signal existed within an electronic system, a frequency divider is used to divide the 100 MHz clock signal by two.

Referring now to the drawings and, in particular, to FIG. 1 , there is depicted a block diagram of a frequency divider circuit according to the prior art. As shown, a frequency divider circuit 10 includes a D-type flip-flop circuit 11 and an inverter 12 . An input clock signal is applied to a clock input of D-type flip-flop circuit 11 , which transitions the logical state of a signal from an output Q to be equal to the logical state of an input signal at an input D when the input clock signal transitions from a logical low state to a logical high state. Inverter 12 applies to the input D a signal that is opposite in logical state to the output signal at output Q so that the output Q changes logical state in response to the rising edge of the input clock signal. As a result, the output signal at the output Q has a frequency that is one half of the input signal frequency.

One problem with prior art frequency divider circuits, such as frequency divider circuit 10 , is that they are very susceptible to single-event upsets (SEUs) or single-event transients (SETs) that can result in runt pulses occurred on the clock path and subsequently phase shifts in the output signals. Consequently, it is desirable to provide an SEU immune frequency divider circuit.

SUMMARY OF THE INVENTION

In accordance with a preferred embodiment of the present invention, a single-event upset immune frequency divider circuit includes a dual-path shift register, a dual-path multiplexor, and a summing circuit. The dual-path shift register has a clock input, one signal input pair and multiple signal output pairs. The dual-path multiplexor has multiple signal input pairs and one output pair. The signal input pairs of the dual-path multiplexor are respectively connected to the signal output pairs of the dual-input shift register. The dual-path multiplexor selects one of the signal output pairs of the dual-path shift register for feeding back into the signal input pair of the dual-path shift register. The summing circuit then sums the selected signal output pair of the dual-path multiplexor to generate an output clock signal that is a fraction of the frequency of an input clock signal at the clock input of the dual-path shift register.

DESCRIPTION OF A PREFERRED EMBODIMENT

With reference now to FIG. 2 , there is depicted a block diagram of a single-event upset (SEU) immune frequency divider circuit, in accordance with the preferred embodiment of the present invention. As shown, an SEU immune frequency divider circuit 20 includes a summing circuit 21 , a dual-path shift register 22 and a dual-path multiplexor 23 . SEU immune frequency divider circuit 20 also includes a clock input 24 and a clock output 25 . Dual-path shift register 22 includes four output pairs, namely, QB 11 -QB 21 , QB 12 -QB 22 , QB 13 -QB 23 and QB 14 -QB 24 . Dual-path multiplexor 23 may select any one of the four output pairs of dual-path shift register 22 to be fed back to an input pair DB 11 -DB 12 of dual-path shift register 22 . Depending on the selected output pair to be fed back, SEU immune frequency divider circuit 20 may divide an input clock signal from, for example, a system clock at clock input 24 by 2, 4, or 8 times in order to produce an output clock signal that is one-half, one-fourth, or one-eighth of the input clock signal, respectively, at clock output 25 .

Summing circuit 21 is a tri-state circuit having a dual-input inverter 26 and inverters 27 - 29 . The purpose of inverters 27 - 29 is to boost the strength of input/output signals to/from summing circuit 21 . Dual-input inverter 26 has two inputs and one output. Dual-input inverter 26 sums the two outputs from dual-path multiplexor 23 to produce a single output at clock output 25 for SEU immune frequency divider circuit 20 . Dual-input inverter 26 preferably includes two serially connected p-channel transistors connected in series with two serially connected n-channel transistors. Each of the two inputs of dual-input inverter 26 , which is provided by connecting the gates of a p-channel transistor and an n-channel transistor, is connected to one of the two outputs of dual-path multiplexor 23 . For example, if the four transistors within dual-input inverter 26 are labelled as p-channel transistors a, b and n-channel transistors c, d, then OUT 1 from dual-path multiplexor 23 can be connected to the gates of both p-channel transistor a and n-channel transistor c (via inverter 29 ) while OUT 2 from dual-path multiplexor 23 can be connected to the gates of p-channel transistor b and n-channel transistor d (via inverter 28 ). Alternatively, OUT 1 from dual-path multiplexor 23 can be connected to the gates of both p-channel transistor b and n-channel transistor c (via inverter 29 ) while OUT 2 from dual-path multiplexor 23 can be connected to the gates of both p-channel transistor a and n-channel transistor d (via inverter 28 ).

Referring now to FIG. 3 , there is depicted a detailed block diagram of dual-path shift register 22 , in accordance with the preferred embodiment of the present invention. As shown, dual-path shift register 22 includes four dual-path D-type flip-flip (DFF) circuits 41 - 44 . DFF circuits 41 - 44 function as a pseudo shift register where the inverted output of one DFF circuit feeds the inverting input of the next DFF. Specifically, the two inverted outputs of DFF circuit 41 (QB 11 -QB 21 ) are separately connected to the two inverting inputs of DFF circuit 42 ; the two inverted outputs of DFF circuit 42 (QB 12 -QB 22 ) are separately connected to the two inverting inputs of DFF 43 ; and the two inverted outputs of DFF circuit 43 (QB 13 -QB 23 ) are separately connected to the two inverting inputs of DFF circuit 44 . In addition, outputs QB 11 and QB 21 are connected to inputs IN 11 and IN 21 of dual-path multiplexor 23 (from FIG. 2 ), respectively. Similarly, outputs QB 12 and QB 22 are connected to inputs IN 12 and IN 22 of dual-path multiplexor 23 , respectively; outputs QB 13 and QB 23 are connected to inputs IN 13 and IN 23 of dualpath multiplexor 23 , respectively; and outputs QB 14 and QB 24 are connected to inputs IN 14 and IN 24 of dual-path multiplexor 23 , respectively. The clock inputs of DFF circuits 41 - 44 are all connected to clock input 24 .

As will be further explained in FIG. 7 , for an one-half signal division, the two inverted outputs of DFF circuit 41 (QB 11 -QB 21 ) are fed back into the two inverting inputs of DFF circuit 41 by dual-path multiplexor 23 . For an one-fourth signal division, the two inverted outputs of DFF 42 (QB 12 -QB 22 ) are fed back into the two inverting inputs of DFF circuit 41 by dual-path multiplexor 23 . For an one-eighth signal division, the inverted outputs of DFF circuits 41 and 43 - 44 (QB 11 -QB 21 , QB 13 -QB 23 and QB 14 -) QB 24 ) are fed back into the two inverting inputs of DFF circuit 41 by dual-path multiplexor 23 .

Since DFF circuits 41 - 44 are identical, only DFF circuit 41 will be further illustrated. With reference now to FIG. 4 , there is depicted a schematic diagram of DFF circuit 41 , in accordance with a preferred embodiment of the present invention. As shown, DFF circuit 41 includes an SEU latch 45 and an SEU latch 46 . Each of the two inputs of SEU latch 45 is connected to an inverter. Each of the two outputs of SEU latch 45 is connected to a respective input of SEU latch 46 . Each of the two outputs of SEU latch 46 is connected to an inverter to provide an output for DFF circuit 41 . SEU latch 45 and SEU latch 46 share a common clock input.

Referring now to FIG. 5 , there is depicted a schematic diagram of SEU latch 45 from FIG. 4 , in accordance with a preferred embodiment of the present invention. As shown, SEU latch 45 includes a cross-coupled tri-state inverter 50 and a cross-coupled inverter 57 . Cross-coupled tri-state inverter 50 includes a first tri-state inverter connected to a second tri-state inverter in a cross-coupled fashion. The first tri-state inverter includes two serially connected p-channel transistors 53 a - 54 a connected in series with two serially connected n-channel transistors 55 a - 56 a . Similarly, the second tri-state inverter includes two serially connected p-channel transistors 53 b - 54 b connected in series with two serially connected n-channel transistors 55 b - 56 b . The gate of transistor 56 a is connected to the gate of transistor 53 b to provide a first feedback input for cross-coupled tri-state inverter 50 , and the gate of transistor 53 a is connected to the gate of transistor 56 b to provide a second feedback input for cross-coupled tri-state inverter 50 . The first forward input for cross-coupled tri-state inverter 50 is from the gate of transistor 54 a and the gate of transistor 55 a . The second forward input for cross-coupled tri-state inverter 50 is from the gate of transistor 54 b and the gate of transistor 55 b.

Cross-coupled inverter 57 includes a first inverter connected to a second inverter in a cross-coupled fashion. The first inverter includes a p-channel transistor 58 a connected in series with an n-channel transistor 59 a . Similarly, the second inverter includes a p-channel transistor 58 b connected in series with an n-channel transistor 59 b . The gate of transistor 58 a is connected to the gate of transistor 59 b to provide a first forward input for cross-coupled inverter 57 , and the gate of transistor 59 a is connected to the gate of transistor 58 b to provide a second forward input for cross-coupled inverter 57 . A first output 61 a of cross-coupled inverter 57 is provided at a node S 3 between transistor 58 a and transistor 59 a . A second output 61 b of cross-coupled inverter 57 is provided at a node S 4 between transistor 58 b and transistor 59 b.

Cross-coupled inverter 57 is connected to cross-coupled tri-state inverter 50 . Specifically, first output of cross-coupled inverter 57 (i.e., node S 3 ) is fed back to the first feedback input of cross-coupled tri-state inverter 50 (i.e., the gates of transistors 56 a and 53 b ). Also, second output 61 b of cross-coupled inverter 57 (i.e., node S 4 ) is fed back to the second feedback input of cross-coupled tri-state inverter 50 (i.e., the gates of transistors 53 a and 56 b ).

During operation, data enter through an input 60 a . A transmission gate 52 a allows data to enter cross-coupled tri-state inverter 50 when the clock signal CLK at clock input 24 (from FIG. 3 ) is at a logical low state. Concurrently, data also enter through an input 60 b . A transmission gate 52 b allows data to enter cross-coupled tri-state inverter 50 when the clock signal CLK at clock input 24 is at a logical low state.

Since transistors 54 a - 55 a and transistors 54 b - 55 b are turned off when clock signal CLK is at a logical low state, data from input 60 a are sent to a storage node S 1 (i.e., the first forward input of cross-coupled inverter 57 ), and data from input 60 b are sent to a storage node S 2 (i.e., the second forward input of cross-coupled inverter 57 ). If the data at input 60 a and input 60 b are both, for example, logical 1's, then transistors 59 a and 59 b are turned on such that a logical 0 is showed up at both outputs 61 a and 61 b . The logical 0's at outputs 61 a and 61 b are then converted to logical 1's by inverters 62 a and 62 b , respectively. If the signals at inputs 60 a and 60 b are both, for example, logical 1's, then transistors 59 a and 59 b are turned on such that logical 0's show up at both output 61 a and output 61 b . Nodes S 3 and S 4 , at outputs 61 a and 61 b , respectively, are considered as non-inverting nodes.

When the clock signal CLK at clock input 24 is at a logical high state, then DFF circuit 41 holds the data from a previous cycle. For example, if nodes S 1 and S 2 are both at logical 1's at the previous cycle, that means nodes S 3 and S 4 are both at logical 0's at the previous cycle. The logical 0's from nodes S 3 and S 4 are also sent to the first feedback input of cross-coupled tri-state inverter 50 (i.e., the gates of transistors 56 a and 53 b ) and the second feedback input of cross-coupled tri-state inverter 50 (i.e., the gates of transistors 53 a and 56 b ), respectively. The logical 0 from node S 3 turns on transistor 53 b ; thus, the logical 1 at node S 2 is maintained. The logical 0 from node S 4 turns on transistor 53 a ; thus, the logical 1 at node S 1 is maintained.

On the other hand, if nodes S 1 and S 2 are both at logical 0's at the previous cycle, that means nodes S 3 and S 4 are both at logical 1's at the previous cycle. The logical 1's from nodes S 3 and S 4 are also sent to the first feedback input of cross-coupled tri-state inverter 50 and the second feedback input of cross-coupled tri-state inverter 50 , respectively. The logical 1 from node S 3 turns on transistor 56 a ; thus, the logical 0 at node S 1 is maintained. The logical 1 from node S 4 turns on transistor 56 b ; thus, the logical 0 at node S 2 is maintained.

When writing to nodes S 1 and S 2 , if the signal at input 60 a is a logical 1 and the signal at input 60 b is a logical 0 (or vice versa) due to an incident of single-effect upset, then the inadvertently written state will not be held when clock signal CLK becomes high. For example, if node S 1 is at logical 1, node S 2 is at logical 1, node S 3 is at logical 0, and node S 4 is at logical 0 before a write cycle. Due to an SEU, a logical 1 is written to node S 1 and a logical 0 is written to node S 2 , which leads node S 3 being the same state and node S 4 will be at logical 0 or 1. The logical 0 from node S 3 turns on transistor 53 b and node S 2 will be changed to logical 1 . The logical 1 from node S 4 turns on transistor 56 b , and node S 2 will be changed to logical 0 at node S 2 .

With reference now to FIG. 6 , there is depicted a schematic diagram of SEU latch 46 from FIG. 4 , in accordance with a preferred embodiment of the present invention. As shown, SEU latch 46 includes a cross-coupled tri-state inverter 80 and a cross-coupled inverter 87 . Cross-coupled tri-state inverter 80 is identical to cross-coupled tri-state inverter 50 from FIG. 5 , and cross-coupled inverter 87 is identical to cross-coupled inverter 57 from FIG. 5 . The main difference between SEU latch 46 and SEU latch 45 is that the clock input to transmission gates 82 a and 82 b . As a result, transmission gate 82 a allows data to enter cross-coupled tri-state inverter 80 when the clock signal CLK at clock input 24 (from FIG. 3 ) is at a logical high state. Concurrently, transmission gate 82 b allows data to enter cross-coupled tri-state inverter 80 when the clock signal CLK at clock input 24 is at a logical high state.

Referring now to FIG. 7 , there is depicted a detailed block diagram of dual-path multiplexor 23 , in accordance with a preferred embodiment of the present invention. As shown, dual-path multiplexor 23 includes two decode circuits 70 a - 70 b and multiple logic gates for coupling eight inputs to decode circuits 70 a - 70 b . The eight inputs can be grouped into four input pairs, namely, input pair IN 11 -IN 21 , input pair IN 12 -IN 22 , input pair IN 13 -IN 23 and input pair IN 14 -IN 24 . One or more of the four input pairs can be directed by decode circuits 70 a - 70 b as outputs at output pair OUT 1 -OUT 2 via control inputs CTRL 1 and CTRL 2 . Specifically, decode circuit 70 a turns on one of transfer gates 71 a - 73 a , according to control inputs CTRL 1 and CTRL 2 , to allow signals at one or more of the inputs IN 11 , IN 12 , IN 13 and IN 14 to transfer to output OUT 1 . Similarly, decode 70 b turns on one of transfer gates 71 b - 73 b , according to control inputs CTRL 1 and CTRL 2 , to allow signals at one or more of the inputs IN 21 , IN 22 , IN 23 and IN 24 to transfer to output OUT 2 . In essence, control inputs CTRL 1 and CTRL 2 dictate which two outputs of one of DFF circuits 41 - 44 (from FIG. 2 ) to be fed back into the two inputs of DFF circuit 41 and the two inputs of summing circuit 21 (from FIG. 2 ) in order to control the output frequency of frequency divider 20 (from FIG. 2 ).

For an one-half signal division, transmission gates 71 a and 71 b will be turned on to allow input pair IN 11 -IN 21 (i.e., the two inverted outputs from DFF circuit 41 ) to be fed back into the two inverting inputs of DFF circuit 41 . For an one-fourth signal division, transmission gates 72 a and 72 b will be turned on to allow input pair IN 12 -IN 22 (i.e., the two inverted outputs of DFF 42 ) to be fed back into the two inverting inputs of DFF circuit 41 . For an one-eighth signal division, transmission gates 73 a and 73 b will be turned on to allow input pairs IN 11 -IN 21 , IN 13 -IN 23 and IN 14 -IN 24 (i.e., the inverted outputs of DFF circuits 41 and 43 - 44 ) to be fed back into the two inverting inputs of DFF circuit 41 . In the present example, an AND gate 74 a and an OR gate 75 a are used to combine the inputs IN 11 , IN 13 and IN 14 for transmission gate 73 a , and an AND gate 74 b and an OR gate 75 b are used to combine the inputs IN 21 , IN 23 and IN 24 for transmission gate 73 b . However, it is understood by those skilled in the art that any combination of logic gates can be utilized to perform the function of logic gates 74 a , 75 a , 74 b and 75 b.

As has been described, the present invention provides a SEU immune frequency divider circuit.