Clock recovery for optical transmission systems

A receiver for an optical communications system which corrects distortion of a received signal. A clock recovery system utilizing a feedback and feedforward system are provided. The feedback loop comprises a phase detector and a clock source, while the feedforward loop comprises the phase detector and a delay element for delaying the output of distortion correction system. The feedback loop has a significantly lower bandwidth than the feedforward path. There are also provided methods of optimizing tap weights and of acquiring initial tap weights.

BACKGROUND

This invention relates to a receiver for an optical communications system, and in particular to clock recovery in a Dual Polarisation Quadrature Phase Shift Keying System.

Two principle forms of modulation are utilised in optical communications systems; Amplitude Shift Keying (ASK) and Phase Shift Keying (PSK), which encode data in the amplitude and phase, respectively, of the transmitted light. Direct detection methods can be utilised to detect and receive ASK signals, but not PSK signals in which the data cannot be recovered from the power envelope of the light. Coherent detection, in which the received light is mixed with an optical Local Oscillator (LO), enables the reception of PSK signals.

The optical LO may be locked to the frequency and phase of the incoming optical signal (homodyne reception), or, may be held very close to, but not locked precisely to, the incoming optical signal (intradyne reception), or may be at a significantly different frequency in relation to the incoming optical signal (heterodyne reception). Locking an optical LO to an incoming signal for a homodyne system presents many practical difficulties in the optical implementation, while heterodyne reception requires the use of high frequency electronics to remove the frequency offset. Intradyne reception offers a compromise where control of the optical LO is relatively easy to achieve, and the bandwidth of the electrical signal is kept to frequencies which are also relatively simple to manage and process.

A particular form of PSK is Quadrature PSK (QPSK) in which two bits are encoded per symbol. The symbol rate of a QPSK signal is thus half the bit rate carried by the signal.FIG. 1shows power10and electrical field11eyes of a QPSK signal. As can be seen, the optical power of each symbol is the same, with the information residing in the optical phase of the signal. Variations in the optical power envelope are caused by transitions between symbols and do not convey any information.

Light sources used for optical transmission systems are generally well-polarised lasers. Independently modulated sources can thus be polarisation multiplexed for transmission, thereby transmitting four bits per symbol at a single wavelength in a Dual Polarisation QPSK (DP-QPSK) format. In a DP-QPSK signal the power and field eyes shown inFIG. 1are repeated independently, although usually aligned in time at the transmitter, on each polarisation.

A DP-QPSK optical signal is conveniently generated from 4 independent data signals, each at the symbol rate. A 40 Gb/s DP-QPSK signal can thus be generated from four 10 Gb/s electrical signals, thereby utilising relatively cheap 10 Gb/s electrical components.FIG. 2shows a schematic diagram of a DP-QPSK modulator driven by four signals20-23, at the symbol rate.

FIG. 3shows an example of a receiver for receiving a DP-QPSK signal. The received signal30is split into two orthogonal polarisations by polarisation beam splitter31and each signal is fed to a 90° optical hybrid32,33. An optical LO34is also fed to each hybrid32,33for mixing with the data signals. The outputs of each hybrid are passed to separate photodetectors35a, b, c, dto convert their amplitudes to electrical signals which are converted to digital values by Analogue to Digital Converters (ADCs)36a, b, c, d. Those values are passed to ASIC37for digital signal processing.

The outputs from the photodiodes can be expressed as shown below.
Vx0=|Esx+ELO|2=|Esx|2+|ELO|2+2e{EsxELO*}
Vx90=|Esx+jELO|2=|Esx|2+|ELO|2+2ℑm{EsxELO*}
Vy0=|Esy+ELO|2=|Esy|2+|ELO|2+2e{EsyELO*}
Vy90=|Esy+jELO|2=|Esy|2+|ELO|2+2ℑm{EsyELO*}

The first two terms on the right in each equation are small, or can be removed by electrical components, leaving the detected signals represented by the right hand term on each line. Each of the electrical signals passed to ASIC37thus represent a combination of the data signal and the optical LO. The ASIC must therefore remove the residual LO from the signals to enable decoding of the data.

Optical signals suffer distortion during their transmission, for example due to Chromatic dispersion. It is known that Finite Impulse Response (FIR) filters are effective at removing linear dispersions such as Chromatic Dispersion (CD) (see, for example, J. H. Winters, “Equalization in Coherent Lightwave Systems Using a Fractionally Spaced Equalizer”, JLT, Vol. 8, No. 10, October 1990 and Taylor, M. (2004), ‘Coherent detection method using DSP for demodulation of signal and subsequent equalization of propagation impairments’,Photonics Technology Letters, IEEE16(2), 674-676.), both of which are incorporated herein by reference.FIG. 4shows a simplified block diagram of a receiver for a single polarisation utilizing an FIR filter40to correct distortion and a carrier recovery block41to remove the residual LO offset signal.

After correction by the FIR filter40the symbols are discrete, but located at arbitrary phases (as shown at42) due to the LO offset. The carrier recovery block41removes that offset resulting in the phases lying on the expected constellation43for a QPSK signal.

FIG. 5shows an example configuration of a FIR filter40, implemented as is known in the art.

During transmission the polarisation of the optical signal is rotated and may be received in any arbitrary alignment, not necessarily aligned with the receiver as has been assumed above. A butterfly structure of FIR filters may be utilised to process the received signals when the polarisation is in an unknown state.FIG. 6shows a filter structure for performing this demultiplexing as described in, for example, Savory et al., “Digital Equalisation of 40 Gbit/s per Wavelength Transmission over 2480 km of Standard Fibre without Optical Dispersion Compensation”, ECOC2006, Paper 2.5.5, 2006, incorporated herein by reference.

FIG. 7shows a block diagram of a digital receiver system for an optical communications system. As explained above, the input signal70is mixed with a local oscillator in block32and fed to a set of four photodiodes35. The outputs of the photodiodes are digitised in ADCs36, the output being passed to a digital processing system71. The digital processing system71is typically provided by a CMOS Application Specific Integrated Circuit (ASIC) specifically designed to process the digitised signals including an equaliser74to correct distortion, but may be any system suitable for performing the tasks required, for example a DSP may be appropriate. The processing system processes the data in real time and therefore must be capable of operating on the full data payload. For example, a typical receiver may receive a 10-40 Gb/s signal for processing. ASICs provide convenient systems for performing this processing as they allow the design of a highly parallel system to cope with processing such high data rates.

The ADCs and processing system and other components may be provided by a single device, or separated between different devices as appropriate. The same or different type of device may be appropriate for each function.

The data clock frequency and phase of the incoming signal must be derived such that the ADCs can sample the incoming signal at the correct point and sample rate. A conventional approach, as shown inFIG. 7, is to use an analogue Phase Locked Loop (PLL) formed of phase detector73and Voltage Controlled Oscillator (VCO)72. Although not shown explicitly, it will be appreciated that a loop filter will be incorporated in the PLL. It is generally convenient to locate this in close proximity to the VCO and it may therefore be considered to form part of the VCO block72inFIG. 7. However, the incoming signal may be so distorted that this system cannot track the signal to acquire the clock phase. For example, the distortion correction may tolerate 10,000-20,000 ps/nm of dispersion which is significantly higher than conventional analogue PLLs have been shown to work over.

An alternative method shown inFIG. 8is to utilise a digital phase detector80operating from the equalised signals to control the VCO72. In order to meet certain telecommunications standards (for example G.8251) a PLL bandwidth of greater than 1 MHz may be required. However, the correction system74introduces delay into the PLL which affects operation. In particular, gain peaking is introduced making it extremely difficult, if not impossible, to meet the performance required by the standards. The processor may require 10-40 clock cycles to perform the equalisation process and typically operates at 300-600 MHz giving 30-100 ns of delay in the feedback loop which is sufficient to degrade the performance of a 1 MHz PLL.FIG. 9shows a Jitter mask demonstrating the effect of delay on the PLL ofFIG. 8with a 1 MHz bandwidth. Performance is reduced to below the required level even with 16 clock cycles of delay in the loop. In contrast, in similar implementations in the radio domain the processing rate is far higher than the data rate, making the delay less significant to the operation of the feedback loop.

There is therefore a requirement for a clock recovery system that can perform clock recovery from a highly distorted signal, such as an uncompensated DP-QPSK signal.

The startup of an optical transmission system receiver may be difficult, or impossible. The clock recovery and compensation systems are inter-dependent and one cannot begin operation without the other being at least partially operational. There is therefore a need for a method which can initialise the receiver in such a system.

SUMMARY

There is provided a receiver for receiving at least one input signal from a photodiode in an optical communications system, comprising an Analogue to Digital Converter (ADC) configured to digitise the at least one input signal and output a digitised signal, a digital processing system configured to process the digitised signal and output a processed signal, a phase detector configured to detect the timing phase of the processed signal and output a signal indicative of that phase, a clock source providing a sampling clock signal to the analogue to digital converter, the clock source having the signal indicative of the phase of the processed signal as an input to control the sampling clock signal, and a delay element configured to delay the processed signal and output a delayed processed signal, the delay of the delay element being controlled by the output of the phase detector.

The processing of the digital signal may comprise correction of distortion introduced in the optical transmission system.

The digital processing system may comprise a Finite Impulse Response (FIR) filter for processing the digitised signal.

The FIR may comprise variable tap weights.

A tap weight update algorithm may be implemented in the processing system.

The receiver may further comprise a low pass filter configured to filter the signal indicative of the phase.

The filtered signal indicative of the phase may be utilised by the delay element, and the unfiltered signal is utilised by the clock source.

The filtered signal indicative of the phase may be utilised by the delay element, and the clock source.

The clock source may be implemented in a device with the at least one ADC.

The clock source may be implemented as a separate device to the at least one ADC.

The at least one ADC and clock source may be implemented in a first device and the processing system is implemented in a second device.

The second device may be an ASIC.

The processing system may process the signals in real time.

The receiver may further comprise at least one photodiode, each providing an input to an ADC.

The receiver may comprise four ADCs.

The receiver may further comprise an optical Local Oscillator and at least one optical hybrid configured to mix the optical Local Oscillator with a received optical signal, the output of the at least one optical hybrid being the input to the at least one photodiode.

The receiver may further comprise a carrier recovery system operating at the output of the digital processing system.

The receiver may further comprise a decision system configured to decide the value of received symbols.

The tap update algorithm may utilise inputs comprising a delayed version of the at least one input signal, the delay being the same as the delay applied by the delay element to the processed signal, the output of the delay element, and the decided symbols.

The phase detector may be configured to select one or both of two signals relating to two polarisations.

The receiver may further comprise a tap weight centralisation system for centralising the tap weights of the FIR filter.

The receiver may be configured to receive, correct and decode a dual polarisation quadrature phase shift keyed optical signal.

There is also provided a method of receiving a modulated optical signal, comprising the steps of receiving the optical signal in at least one photodiode, digitising the output of the photodiode to provide an input signal utilising an ADC, processing the input signal to correct distortion and outputting a corrected signal, monitoring the timing phase of the corrected signal and outputting a phase signal indicative of that phase, utilising the phase signal to control a clock source providing a clock signal to the ADC, and delaying the corrected signal in accordance with the phase signal.

There is also provided a method of optimising tap weights in an FIR filter utilised to correct distortion in an optical communications receiver, comprising the steps of monitoring the tap weight centre of the FIR filter, calculating the offset of tap weight centre from the central tap position of the FIR filter, and utilising that offset to define a sampling clock phase of an ADC, the output of which is passed to the FIR filter.

The sampling clock phase may be defined by adding a signal indicative of the offset to a signal indicative of the phase of a signal output by the FIR filter.

The offset may be utilised to adjust a delay applied to the output of the FIR filter.

There is also provided a method of initially acquiring tap weights for an FIR filter used to correct distortion in an optical communications receiver, the method being performed by the receiver and comprising the steps of acquiring and storing a series of samples of a received signal, and applying a blind optimisation algorithm to the series of samples to obtain an estimate of tap weights for a Finite Impulse Response (FIR) filter of the receiver configured to equalise a received optical signal.

The method may further comprise the step of transferring the series of samples to a digital processing system and performing the blind optimisation in that processing system.

The blind optimisation algorithm may be applied in both forwards and backwards directions to the series of samples.

The method may further comprise the step of transferring the estimated tap weights to the FIR filter.

The method may further comprise the step of commencing correcting distortion in a received signal utilising the FIR filter.

The method may further comprise the step of activating a clock recovery system in the receiver.

The method may further comprise the steps of acquiring and storing a further series of samples of a received signal, and applying a blind optimisation algorithm to the further series of samples to obtain an improved estimate of the tap weights.

The method may further comprise the step of applying the improved tap weights to the FIR filter and utilising those tap weights for correction of distortion in a received signal.

The method may further comprise the step of activating a decision system in the receiver to decode the values represented by a received signal.

The method may further comprise the step of activating a tap update algorithm, said algorithm being configured to optimise the tap weights.

DETAILED DESCRIPTION

Embodiments of the present invention are described below by way of example only. These examples represent the best ways of putting the invention into practice that are currently known to the Applicant although they are not the only ways in which this could be achieved.

The description sets forth the functions of the example and the sequence of steps for constructing and operating the example. However, the same or equivalent functions and sequences may be accomplished by different examples.

A 40 Gbit/s DP-QPSK transmission system is utilised as the basis for the following description, but the techniques described are applicable to a range of transmission formats and rates without unduly burdensome modification.

FIG. 10shows a block diagram of a clock recovery system, using a feedback loop90and a feedforward path91. Phase Detector92detects the phase of the output of equaliser74. The phase detector92output is fed back to Voltage Controlled Oscillator (VCO)72which provides a clock for the Analogue to Digital Converter (ADC)36sampling. The VCO72, ADCs36, equaliser74and phase detector92form a Phase Locked Loop (PLL). The phase detector92output is also fed forward to digital delay element94which acts to delay the samples output from the equaliser74. The digital delay element94provides a time adjustment function acting on the samples passed to that element. The digital delay element94can be implemented using an interpolator, for example as described in H. Meyr, M. Moeneclaey, S. A. Fechtel, ‘Digital Communication Receivers’, Wiley & Sons, ISBN 0-471-50275-8. Chapter 9, which is incorporated herein by reference.

The PLL has a relatively low bandwidth of the order of 50-100 kHz and removes the frequency offset and slowly varying phase offset from the clock. The low bandwidth of the PLL means that the processing delay of equaliser74does not cause significant gain peaking in the feedback loop, as seen when the bandwidth of the PLL is sufficient to also remove the fast varying phase offset.

The delay element94removes higher frequency phase jitter remaining on the signals by acting as a digital interpolator to delay the position of the samples output from equaliser74. The Low pass filter95prior to the delay element has a bandwidth of the order of 1-4 MHz.

The Low pass filter may be combined with the phase detector, provided the filter bandwidth is at least about 10 times that of the PLL, such that it effectively only affects the feed-forward path. Regardless of whether the low pass filter is incorporated into the phase detector, or is separate, the bandwidth of the external loop should be lower than the bandwidth of the phase detector and delay element94.

The combination of a lower frequency feedback loop and a delay element controlled by a feedforward signal mitigates at least some of the problems described with prior systems and enables a clock recovery system to meet the required standards.

FIG. 11shows the G.8251 Jitter mask and a series of plots for the system ofFIG. 10. Dashed line100marks the minimum jitter values which must be tolerated. The simulation assumed a processing delay of 372 ns (125 clock cycles), and a 100 kHz analogue closed-loop bandwidth. Even with this relatively large processing delay, the standard can be comfortably met with a Low Pass Filter with a 5.4 MHz 3 dB point.FIG. 12shows a block diagram of a receiver system for correcting distortion, performing clock recovery, and decoding received data. The system shown inFIG. 12relates to a single polarisation and is duplicated (apart from the photodiodes and ADCs which are shared) for the second polarisation.

As explained previously, four photodiodes35receive four outputs from 90° hybrids mixing the optical signal with the optical Local Oscillator. The outputs of those photodiodes are digitised using ADCs36, the sampling clock of which is provided by VCO72configured in conjunction with phase detector92as described in relation toFIG. 8.

The upper pair of photodiodes (solid signal lines) are for a first output of the polarisation splitter described above and the lower pair (dashed signal lines) for the second output of that splitter. The signals from each pair are combined to give a complex valued signal (composing of real and imaginary parts)110,111and passed to the equaliser112. As explained previously, the ‘butterfly’ equaliser structure corrects for the unknown polarisation of the incoming optical signal.

Delay element113acts on the output of the equaliser112to remove any high frequency phase jitter not tracked by the PLL. The output of the delay element113is passed to a carrier recovery system114to remove the Local Oscillator offset. Example carrier recovery systems are disclosed in Viterbi, A. (1983), ‘Nonlinear estimation of PSK-modulated carrier phase with application to burst digital transmission’, Information Theory, IEEE Transactions on29(4), 543-551, and H. Meyr, M. Moeneclaey, S. A. Fechtel, ‘Digital Communication Receivers’, Wiley & Sons, ISBN 0-471-50275-8. pp. 311-322, which are incorporated herein by reference.

Decision circuit115decides values of the symbols (in this example DP-QPSK system the output from the equaliser represents a QPSK signal and therefore each symbol carries two bits) and outputs the decided symbols at119.

A decision-directed tap update system116is provided to control and maintain the tap weights of the equaliser112such that the system continuously monitors and tracks the incoming signals. The tap update system116operates a tap update algorithm which takes inputs of the input signal117, the equalised signal118and the decided symbols119. To ensure correlation between the input signal and the equalised signal118a second delay element1100is utilised on the input signal feed to the tap update system to mimic the delay applied by the first delay element. The input signal passed to the update algorithm is therefore actually a delayed input signal1101such that the algorithm does not see the delay introduced by the first delay element113. The decided symbols signal119also differs from the input signal1101and equalised data118as the carrier offset has been removed. The decided symbols must therefore be ‘re-spun’ such that they correlate with the other signals. This is achieved by applying1102the output of the carrier phase estimator1103to the decided symbols.

The tap update algorithm may be any suitable algorithm for providing the required functionality, and various options are known in the art. By way of example, the following description is given in relation to a Least Mean Squares (LMS) algorithm.

Firstly, an error vector of the difference between the equaliser output and the decided symbol is calculated as below:—
ēk=yk−pk

We note the use of a line over variables to indicate a complex value, and bold type to indicate a matrix. Where ykis the decided symbol output:—
y=d(k)e+j{circumflex over (φ)}k

And pkis the equaliser output:—
p=wHv
where H is the Hermitian transpose (or conjugate transpose). The tap coefficients are then calculated:—
wk+1=(1−α)wk+μēk*vk

Wherew=tap weight matrix, α=leakage factor, μ is the update rate andvis the unequalised input signal matrix. The delayed input signalvkis multiplied by the error value, ēk, and by μ, the tap update rate. The first terms in the equation apply the ‘leakage factor’ α to the previous tap weights, which causes them to decay over time.

The receiver system ofFIG. 12thus provides a system for equalising a received signal, performing clock recovery, dynamically updating the equaliser to track changing conditions, and determining the value of the received symbols. As noted previously, a comparable system may be utilised to process the second polarisation of a DP-QPSK system.

FIG. 13shows a block diagram of a phase detector suitable for a DP-DQPSK system. The operation of such a phase detector is described in Oerder, H. (May 1988), ‘Digital filter and square timing recovery’, Communications, IEEE Transactions on36(5), 605-612 and Zhu, M. S. M. (November 2005), ‘Feedforward symbol timing recovery technique using two samples per symbol’, Circuits and Systems I: Regular Papers, IEEE Transactions on [Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on]52(11), 2490-2500, incorporated herein by reference.

For clarity, the following description is given in relation to the first signal and blocks shown inFIG. 13, but applies to each of the blocks duplicated in parallel inFIG. 13.

As described in the above references the incoming signal120is first multiplied by a half-rate sine or cosine clock. In the implementation shown inFIG. 13which operates using two samples per symbol, this is implemented by passing alternate samples to separate data paths121and122. Path121receives the even (A) samples and path122receives the odd (B) samples. Even and odd are used as labels only to distinguish one sub set of samples from the other. The samples are then passed through low pass filter123, for example a Finite Impulse Response (FIR) filter to remove high frequency components from the signal which would distort the phase detector output when working with 2 samples per symbol. The complex value (u+vj) is then squared at block124to give a clock phase vector125.

The four clock phase vector signals are added in adders120,121. Adders120,121are selectable to allow the selection of one or more of the clock phase vector signals. When in steady state it is likely to be most preferable for the phase detector to operate on all signals (i.e. both polarisations) to give the best accuracy. However, during startup, or at other times, it is possible that the output of the equaliser for one polarisation is poor and thus the phase detector may utilise only the good polarisation to detect the phase. The phase detector may therefore be switched dynamically based on the system's performance to utilise one or both of the polarisation signals.

The clock phase vectors are then averaged at blocks122,123and converted to a phase value using an a tan ((½π)tan−1(N/D)) block124. Averaging the phase vectors rather than the phase value makes the system more robust against cycle slips. The parameters of the Average blocks122,123define the bandwidth of the phase detector.

Unwrap block125removes discontinuities at +/−π radian intervals and allows the phase detector to track phase changes over multiple unit intervals as shown inFIG. 14(a plot of Phase Detector Output (Unit Intervals (UI)) against Input Phase (UI)) which shows an idealized output. As shown inFIG. 14the output should be linear since the signal is utilized as a feedforward signal to control Delay Element113. Delay Element113cannot provide an infinite delay and so saturation block126saturates the signal at a predetermined value (2 unit intervals inFIG. 14).

The phase value output is split and may be adjusted127,128according to tap weight phase detector1202as described below. The outputs129,1200are utilised as inputs to the VCO72and Delay Element113, respectively.

FIG. 15shows a block diagram of a clock frequency offset monitor1201which may be provided to analyse and indicate whether the clock recovery system has locked to the received data signal. Successive phase values are compared at block140to give the phase change between those values. Block141performs an unwrap function to prevent false indications when the phase moves over an edge of the tan θ function. Infinite Impulse Response (11R) filter142filters the signal resulting in a signal143indicating the offset between the received data clock and the local clock. When this value is stable, lock has been obtained. The indication of clock lock may be utilised by the processing system to control decoding of data or for general system control.

FIR filters, such as those used in the equaliser, can act as variable delay elements by interpolating between samples. This occurs by the tap weights shifting to the left or the right.FIGS. 15aand 15bshow plots of tap weights of an FIR filter, each having the same impulse response but the tap weights inFIG. 16bare shifted off-centre to introduce a delay compared to the weights inFIG. 16a. The centred weights shown inFIG. 16aare better able to correct for increased distortion than the off-centre ones shown inFIG. 16b, and therefore it is preferable for the tap weights to be centralised for optimum equaliser performance.

The equaliser112, being an FIR, attempts to track and correct any slow clock phase drift which causes the tap weights to move from their central position. The off-centre tap weights are less able to equalise increased distortion and therefore system performance may be degraded. The slow clock phase drift should be corrected by the PLL, not the equaliser.

A tap weight phase detector1202is provided to monitor the centralisation of the tap weights and provide a correction signal indicative of the tap weight centre offset.

The correction signal output by tap weight phase detector1202is split for use by the VCO72and delay element113. The signal for the VCO72passes to multiplier1203where it is multiplied by a coefficient KtapPLL. The signal for the delay element passes to multiplier1204where it is multiplied by a coefficient KtapDE. KtapPLLand KtapDEdefine the magnitude of the correction signal that is added to the phase value for the VCO72and Delay Element113respectively. Adders127and128add the correction signal to the phase signal for the VCO72and delay element133respectively.

In a first example, KtapDEis set to zero such that the correction signal is only applied to the VCO72. In a second example, KtapDEmay be non-zero such that the correction is applied to both the VCO72and Delay Element133.

The correction signal applied to the VCO72(and Delay Element113if KtapDE≠0) causes the tap weights to re-centralise under the action of the tap update system.

In an alternative implementation, the correction signal could be utilised to directly adjust the tap weights. The signal should be applied slowly to allow the VCO72and Delay Elements133to track the change thereby avoiding degradation of the equaliser performance.

The tap weight centre for the x-polarisation can be calculated using the following equation:—

Wherehxxnandhyxnare the nth elements of the complex-valued sub matriceshxxandhyxfor the X-X and Y-X filters respectively which equalise the X-polarisation:

A comparable equation is used for the Y-polarisation. The tap weight phase (the difference between the tap weight centre and the central tap) is then given by:—
φtapX=ncentre−{circumflex over (n)}X

Where ncentreis the number of the central tap.

The tap weight phase is combined with the output of the phase detector, as shown inFIG. 13, to correct the phase of the VCO72and Delay Element113,1100, which in turn results in the tap weights moving to the centralised position. The tap weight phase signal output may be a combination of both the X and Y polarisations, or may be based on one or the other polarisation. It may be desirable to select from one or both polarisations depending on the relatively quality of the signals, or if one of the polarisations has not correctly acquired stable tap weights.

On startup of a transmission system the receiver has no knowledge of the correct clock phase or tap weights for the equaliser. For the phase detector to acquire the phase of the signal (and hence for the clock recovery system to operated) the equaliser must, at least to a certain degree, equalise the received signal. However, determination of the tap weights for the equaliser relies on the clock recovery system.

FIG. 17shows a flow chart of a system for acquiring the clock phase and initial tap weights to allow startup of the system.FIG. 19provides an alternative view of the methods ofFIGS. 17 and 18to exhibit the functions performed by each part of the system and the transfer of data between the ASIC and the DSP during the acquisition187and tracking188phases. Reference numerals onFIG. 19relate to the blocks ofFIGS. 17 and 18.

At block160a series of samples180of the data183is acquired by the ASIC181. For example, 4000 samples may be acquired, which at a typical sample rate of two samples per symbol, gives 2000 symbols. At block161the series of samples is transferred to a Digital Signal Processor (DSP)182for processing according to the programming of that DSP. At block162the DSP applies a blind-optimisation algorithm to the samples180in order to identify an initial set of tap weights which may be used to equalise the incoming signal.

The use of a DSP182associated with the ASIC181for performing the algorithm is convenient as it may be programmed to perform the specific algorithms required. Since the algorithm need not be applied in real time there is a reduced requirement on the performance of the DSP182compared to the processing system which processes the received data in real time. Providing this function in the ASIC181is likely to be substantially more expensive and complex than utilising a DSP182and therefore the use of two devices may be more cost effective. However, the method can equally be applied within a single device if appropriate. In addition, ASIC implementations will typically work in a highly parallel manner, and the update rate μ may be limited by feedback delays. A non-real time implementation allows substantially higher update coefficients to be used, and the same data may be processed several times until the tap weights have converged. The use of a short block of data means that clock offsets (which may be 100-200 ppm) are not significant to prevent acquisition of an initial set of tap weights.

At block163the initial tap weights are transferred to the ASIC181and applied to the equaliser. The equaliser output is now a partially corrected signal from which the phase detector can operate. At block164the PLL is activated. Provided the channel is stable, the output of the equaliser will be valid and the PLL will acquire the clock at block165and will remove the clock offset.

Once the clock has been acquired, at block166the digital delay elements and decision-directed feedback systems are activated and the system enters tracking mode. Provided the initial tap estimates are sufficiently accurate the system will optimise the tap weights, PLL and delay elements. In order for this to succeed the tap weights must be sufficiently accurate for the decision directed update to function, which requires approximately <˜10−2BER.

Algorithms for the blind-compensation of DP-QPSK are known, for example as described in Raheli, R. & Picchi, G. (1991),Synchronous and fractionally-spaced blind equalization in dually-polarized digital radio links, in ‘Communications,1991. ICC91, Conference Record. IEEE International Conference on’, pp. 156-161 vol. 1, incorporated herein by reference. A further known blind acquisition method which may be applicable in relation to the method ofFIG. 17is a constant modulus algorithm as described in Godard, D. (1980), ‘Self-Recovering Equalization and Carrier Tracking in Two-Dimensional Data Communication Systems’, Communications, IEEE Transactions on [legacy, pre—1988] 28(11), 1867-1875, incorporated herein by reference.

The optimisation algorithm utilised in block162may be applied a number of times to the series of samples. A particularly efficient method is to apply the algorithm to the samples alternately forwards and backwards such that any clock offset is not relevant. The update coefficients used in the algorithm may be considerable higher than are utilised in a continual optimisation system as it is only desired to acquire an initial set of tap weights, not to provide continual performance. High update coefficients tend to lead to sporadic changes in tap weights and hence degradation in performance, but provide a more rapid convergence to the initial tap weights.

Prior to the tap weights being transferred to the ASIC they may be re-centred184by shifting the taps in response to a calculation of the tap weight centre, or by applying a shift using a digital interpolation function.

The method shown inFIG. 17assumes that the acquisition phase, polarisation or channel model does not change significantly during the period of the acquisition. It is reasonable to assume that the polarisation and channel model does not change during this phase (approximately 20-500 ms), and a maximum clock offset of 250 ppm is reasonable. With that offset a drift of 0.5 unit intervals will occur in the 2000 symbols, which equates to a shift of 1 equaliser tap. This is not a significant shift and so the required assumptions are reasonable. If the assumptions are not met, then a new series of samples may be acquired and the process restarted.

FIG. 18shows a flow chart of an extension of the method ofFIG. 17to improve the equalisation before tracking mode is activated. After the clock has been acquired at block165a further series of samples185are acquired at block170. At block171those samples185are transferred to the DSP182and again processed using the blind optimisation algorithm at block172. Since the clock offset has been removed from this second series of samples a more accurate set of tap weights can be derived. At block173those tap weights (after optional recentering186) are transferred to the equaliser and applied to the received signal.

At block174the decision-directed tracking and digital delay elements are activated and the receiver enters tracking mode. Frame detection may then be obtained and the system goes on to continuously track the channel.

All parameters and results given in the above description relate to a 40 Gbit/s DP-QPSK transmission system and are given to describe that system. All parameters may be modified in conventional manners as required based on the particular system being utilised without departing from the invention.

Where functions or algorithms have been described as being performed by a particular device or type of device, this is for example only and is not intended to be limiting in any way. As will be appreciated any suitable mode of implementation may be utilised as appropriate.

The blocks and demarcation between functions described above is given by way of example only, and as will be appreciated the functions may be demarked and distributed in any suitable way. Where a function has been described as being performed by a particular type of device (for example an ASIC) it will be appreciated that the principles described herein are also applicable to other methods of implementing those functions (for example in software running on a DSP).

The term Voltage Controlled Oscillator is used to describe a component which produces an output signal for clocking the ADCs in dependence on an input signal. As will be appreciated, it is not intended to restrict the component to one which is controlled directly by a varying voltage, but rather to describe the function of the component. For example, the component may equally be controlled by a digital signal indicating values.

Although not shown or described explicitly, it will be appreciated that, as is well known in the art for PLLs, a loop filter will be incorporated at a convenient location in the various PLLs described herein. That filter may be conveniently located in close proximity to the clock source, and may form part of the same device as that source. Alternatively, the filter may be located at any convenient location and provided by any convenient means.

The manner of implementation of the techniques described herein is dependent on the particular system and the implementation is within the capabilities of the skilled reader once they have been made aware of the functions required by this document.

Any reference to an item refers to one or more of those items. The term ‘comprising’ is used herein to mean including the method blocks or elements identified, but that such blocks or elements do not comprise an exclusive list and a method or apparatus may contain additional blocks or elements.

The term ‘computer’ is used herein to refer to any device with processing capability such that it can execute instructions. Those skilled in the art will realize that such processing capabilities are incorporated into many different devices and therefore the term ‘computer’ includes PCs, servers, mobile telephones, personal digital assistants and many other devices. Similarly DSP or ASIC is not intended to restrict the invention to any particular type of processing device, but those terms are simply used to refer to one possible implementation.

The methods described herein may be performed by software in machine readable form on a tangible storage medium. The software can be suitable for execution on a parallel processor or a serial processor such that the method steps may be carried out in any suitable order, or substantially simultaneously.