Simulation apparatus, simulation method, and computer readable medium

In a simulation apparatus (100), a selection unit (101) repetitively selects context information individually generated for each of a plurality of cores and indicating an instruction to be executed by a corresponding one of the plurality of cores. A simulation unit (102) simulates execution of the instruction indicated by the context information of a core during a period from when the context information of the core is selected by the selection unit (101) till when the context information of another core is selected by the selection unit (101). An adjustment unit (103) refers to definition information (251) to individually define a length of the period for at least one or some instructions. If the instruction whose execution is to be simulated by the simulation unit (102) is the at least one or some instructions, then after the context information of a core to execute the at least one or some instructions is selected by the selection unit (101), the adjustment unit (103) adjusts a timing for causing the selection unit (101) to select the context information of another core according to the definition information (251) that is referred to.

TECHNICAL FIELD

The present invention relates to a simulation apparatus, a simulation method, and a simulation program.

BACKGROUND ART

In recent years, use of an instruction set simulator (ISS) enables software debugging before production of actual hardware. The ISS is a simulator to convert an instruction set of a target central processing unit (CPU) to an instruction set of a host CPU and execute the instruction set after the conversion. The target CPU is a processor of a target machine to be simulated. The host CPU is a processor of a host machine to execute the simulation.

Conventionally, there is a method of simulating simultaneous operations of a plurality of systems including respective processor cores having different operating frequencies (see, for example, Patent Literature 1). As in this method, simulation of a multi-core CPU system and simulation of a multi-CPU system are also enabled. The multi-core CPU system is a system in which a plurality of cores are mounted in a single processor. The multi-CPU system is a system having a plurality of processors.

CITATION LIST

Patent Literature

Patent Literature 1: JP 2004-21904 A

SUMMARY OF INVENTION

Technical Problem

In the conventional method, a reference clock cycle period is set, and simulation of the plurality of systems is switched for execution, for each one clock cycle period. In this method, a synchronization process is executed for each system, for each clock cycle period. Thus, it takes time to perform the simulation.

An object of the present invention is to speed up simulation.

Solution to Problem

A simulation apparatus according to one aspect of the present invention is a simulation apparatus to simulate parallel processing operations of a system including a plurality of components to individually execute instructions of a program. The simulation apparatus may include:

a selection unit to repetitively select context information individually generated for each of the plurality of components and indicating an instruction to be executed by a corresponding one of the plurality of components;

a simulation unit to simulate execution of the instruction indicated by the context information corresponding to a component during a period from when the context information corresponding to the component is selected by the selection unit till when the context information corresponding to another component is selected by the selection unit;

a storage medium to store definition information to individually define a length of the period for at least one or some instructions out of the instructions to be executed by the plurality of components; and

an adjustment unit to, if the instruction whose execution is to be simulated by the simulation unit is the at least one or some instructions, then after the context information corresponding to a component to execute the at least one or some instructions is selected by the selection unit, adjust a timing for causing the selection unit to select the context information corresponding to another component according to the definition information stored in the storage medium.

Advantageous Effects of Invention

In the present invention, a timing for switching simulation of the plurality of components is adjusted depending on execution of which instruction is to be simulated. Therefore, according to the present invention, the simulation can be sped up.

DESCRIPTION OF EMBODIMENTS

A description will be given about an example of a hardware configuration of a system500whose operations are to be simulated in each embodiment of the present invention, with reference toFIG. 1.

The system500includes a multi-core CPU510, a memory520, and a plurality of inputs/outputs (I/Os)530.

The multi-core CPU510includes a core X511, a core Y512, an L1 cache513connected to the core X511, an L1 cache514connected to the core Y512, and an L2 cache515connected to the L1 caches513and514. The multi-core CPU510corresponds to a target CPU.

Each I/O530is an interface with a peripheral device, a direct memory access (DMA) controller, or the like.

In each embodiment of the present invention, program execution in the system500including the multi-core CPU510is simulated. As illustrated inFIG. 1, the multi-core CPU510is a processor including a plurality of cores. The “plurality of cores” are an example of a plurality of components to individually execute instructions of a program. The “plurality of components” are not limited to two cores as in the example inFIG. 1, and three or more cores may be treated as the “plurality of components”. Alternatively, a plurality of processors may be treated as the “plurality of components”. That is, each embodiment of the present invention may be modified so that program execution in a multi-CPU system is simulated.

In software processing by multiple cores or multiple CPUs, timings at which synchronization is necessary are limited. Accordingly, simulation can be executed without problem if the synchronization is performed only at those timings. In each embodiment of the present invention, synchronization is not constantly performed for every clock cycle period. Basically, the synchronization is performed for every plurality of clock cycle periods, and synchronization timings are adjusted as necessary. Thus, the simulation can be sped up.

Hereinafter, embodiments of the present invention will be described, using the drawings. Note that, in the respective drawings, same or corresponding portions are given the same reference numeral. Explanation of the same or corresponding portions in the description of the embodiments will be omitted or simplified as necessary.

First Embodiment

A configuration of an apparatus according to this embodiment, operations of the apparatus according to this embodiment, and effects of this embodiment will be sequentially described.

A configuration of a simulation apparatus100that is the apparatus according to this embodiment will be described, with reference toFIG. 2.

The simulation apparatus100is an apparatus to simulate parallel processing operations of the system500including the core X511and the core Y512, as the “plurality of cores”.

The simulation apparatus100includes a storage medium200.

The storage medium200stores context information X201being context information of the core X511and context information Y202being context information of the core Y512. The storage medium200stores definition information251.

The simulation apparatus100further includes a selection unit101, a simulation unit102, and an adjustment unit103.

The selection unit101repetitively selects the context information stored in the storage medium200. The context information is individually generated for each of the core X511and the core Y512. The context information indicates an instruction to be executed by a corresponding one of the core X511and the core Y512. That is, the context information X201indicates an instruction to be executed by the core X511. The context information Y202indicates an instruction to be executed by the core Y512. Though simulation of the multi-core system having two cores is executed in this embodiment, three or more cores can be accommodated by preparing the context information corresponding to the number of cores. Alternatively, by preparing the context information for each processor, two or more processors can be accommodated. The context information may be obtained from outside the simulation apparatus100instead of being obtained from the storage medium200.

The simulation unit102simulates execution of the instruction indicated by the context information corresponding to a core during a period from when the context information corresponding to the core is selected by the selection unit101till when the context information corresponding to another core is selected by the selection unit101. That is, when the context information X201is selected by the selection unit101, the simulation unit102simulates execution of the instruction indicated by the context information X201during a period until the context information Y202is selected by the selection unit101. When the context information Y202is selected by the selection unit101, the simulation unit102simulates execution of the instruction indicated by the context information Y202during a period until the context information X201is selected by the selection unit101. A description will be given later about how the length of the “period” is determined.

The adjustment unit103refers to the definition information251stored in the storage medium200. The definition information251individually defines the length of the “period” for at least one or some instructions out of the instructions to be executed by the core X511and the core Y512. If the instruction whose execution is to be simulated by the simulation unit102is the at least one or some instructions, then after the context information corresponding to a core to execute the at least one or some instructions is selected by the selection unit101, the adjustment unit103adjusts a timing for causing the selection unit101to select the context information corresponding to another core according to the definition information251that is referred to. That is, if execution of the instruction which is indicated by the context information X201and for which an individual period is defined by the definition information251is to be simulated by the simulation unit102, then the adjustment unit103controls the selection unit101so that the context information Y202is selected by the selection unit101when the defined individual period has elapsed. If execution of the instruction which is indicated by the context information Y202and for which an individual period is defined by the definition information251is to be simulated by the simulation unit102, then the adjustment unit103controls the selection unit101so that the context information X201is selected by the selection unit101when the defined individual period has elapsed.

In this embodiment, the definition information251defines the length of the “period” by specifying the number of instructions whose execution is to be successively simulated by the simulation unit102. That is, the definition information251specifies the individual number of instructions, as an individual period. Assume that the instruction whose execution is to be simulated by the simulation unit102is an instruction for which the individual number of instructions is specified by the definition information251. Then, after the context information corresponding to a core to execute the instruction is selected by the selection unit101, the adjustment unit103causes the selection unit101to select the context information corresponding to another core when execution of one or more instructions, the number of which is specified by the definition information251, has been simulated by the simulation unit102. That is, if execution of the instruction which is indicated by the context information X201and for which the individual number of instructions is specified by the definition information251is to be simulated by the simulation unit102, then, the instruction being the first instruction, the adjustment unit103causes the selection unit101to select the context information Y202when the number of instructions whose execution has been simulated by the simulation unit102reaches the specified number of instructions. If execution of the instruction which is indicated by the context information Y202and for which the individual number of instructions is specified by the definition information251is to be simulated by the simulation unit102, then, the instruction being the first instruction, the adjustment unit103causes the selection unit101to select the context information X201when the number of instructions whose execution has been simulated by the simulation unit102reaches the specified number of instructions. The definition information251may define the length of the “period” by specifying a period of time during which execution of the instructions is to be simulated by the simulation unit102.

Though the definition information251may define the length of the “period” for all the instructions to be executed by the core X511and the core Y512, the definition information251in this embodiment defines the length of the “period” for some instructions out of the instructions to be executed by the core X511and the core Y512. Assume that the instruction whose execution is to be simulated by the simulation unit102is a different instruction from the one or some instructions. Then, after the context information corresponding to a core to execute the different instruction is selected by the selection unit101, the adjustment unit103causes the selection unit101to select the context information corresponding to another core when execution of one or more instructions, the number of which is a fixed number, has been simulated by the simulation unit102. In this embodiment, however, when execution of a branch or synchronization instruction has been simulated by the simulation unit102, the adjustment unit103causes the selection unit101to select the context information corresponding to another core even before the execution of the one or more instructions, the number of which is the fixed number, is simulated by the simulation unit102. That is, if execution of the instruction which is indicated by the context information X201and for which the individual number of instructions is not specified by the definition information251is to be simulated by the simulation unit102, then, the instruction being the first instruction, the adjustment unit103causes the selection unit101to select the context information Y202when the number of instructions whose execution has been simulated by the simulation unit102reaches the fixed number set in advance or when the execution of the branch or synchronization instruction has been simulated by the simulation unit102. If execution of the instruction which is indicated by the context information Y202and for which the individual number of instructions is not specified by the definition information251is to be simulated by the simulation unit102, then, the instruction being the first instruction, the adjustment unit103causes the selection unit101to select the context information X201when the number of instructions whose execution has been simulated by the simulation unit102reaches the fixed number set in advance or when the execution of the branch or synchronization instruction has been simulated by the simulation unit102.

In this embodiment, the simulation unit102converts a target instruction code301that is an instruction code of the target CPU to a host instruction code302that is an instruction code of a host CPU and executes the host instruction code302. The adjustment unit103manages processes of the simulation unit102.

The simulation unit102includes a decode processing unit121, a conversion processing unit122, and an execution processing unit123.

The decode processing unit121performs an instruction decode process. Specifically, in accordance with a command from the adjustment unit103, the decode processing unit121checks whether a host instruction code302is stored in the storage medium200with respect to the address of a target instruction code301that can be executed by the target CPU. When the host instruction code302is not stored in the storage medium200, the decode processing unit121interprets the type of the instruction included in the target instruction code301, and respective registers or memory addresses that serve as the source and destination of the instruction.

The conversion processing unit122performs an instruction conversion process. Specifically, the conversion processing unit122converts the target instruction code301interpreted by the decode processing unit121to one or more host instruction codes302that can be executed by the host CPU. The conversion processing unit122stores the one or more host instruction codes302in the storage medium200.

The execution processing unit123performs an instruction execution process. Specifically, the execution processing unit123executes the one or more host instruction codes302stored in the storage medium200by the conversion processing unit122and corresponding to the target instruction code301to be executed, thereby performing simulation.

When simulation of a target instruction code301that has been executed once is executed again, the decode processing unit121searches the storage medium200. If corresponding one or more host instruction codes302are stored, the adjustment unit103issues an instruction execution process command to the execution processing unit123without issuing an instruction decode process command to the decode processing unit121and without issuing an instruction conversion process command to the conversion processing unit122. By omitting the instruction decode process and the instruction conversion process and by performing the instruction execution process alone, simulation can be performed at high speed.

The adjustment unit103includes a core determination unit131and a timing management unit132.

The core determination unit131determines whether the target instruction code301to be subsequently executed is an instruction code of the core X511or an instruction code of the core Y512. The core determination unit131transmits to the selection unit101the context information to be selected, according to a result of the determination. The context information X201and the context information Y202include information on internal registers of the target CPU, information on addresses held by the cores, and information on resources such as time and interrupt, which are necessary when the core X511and the core Y512of the target CPU execute target instruction codes301, respectively. When the cores are switched at a time of simulation execution, the decode processing unit121, the conversion processing unit122, and the execution processing unit123that are common can be used by switching the context information as well.

When the target instruction code301to be subsequently executed is the instruction code of the core X511, the selection unit101reads the context information X201. When the target instruction code301to be subsequently executed is the instruction code of the core Y512, the selection unit101reads the context information Y202. The selection unit101provides the context information that has been read, as resource information to be used for the instruction execution process by the execution processing unit123.

The simulation apparatus100further includes a time management unit104.

The time management unit104simulates a time lapse of the target CPU according to execution of each host instruction code302. Each time one host instruction code302is executed, the time management unit104computes a period of time taken for the execution and a period of time taken for a memory access, an I/O access, and so on, and reflects results of the computations on the context information X201and the context information Y202provided for the respective cores. Basically, time information of each core is synchronized for each certain timing. The time information of each core can be used with an instruction execution status, as performance information.

When a synchronization timing is fixed, times of the respective cores are synchronized for a short interval of each instruction, thereby enabling simulation with a good time accuracy. However, a simulation period is increased. Assume that the simulation period is long. Then, when simulation of a large program is executed or when simulation is repetitively executed, poor efficiency is obtained. By extending an interval of synchronizing the times of the respective cores to a certain degree, the simulation period can be reduced. However, time accuracy deteriorates and data to be used for performance analysis cannot be collected. Further, when the interval of synchronizing the times of the respective cores is too long, a problem may occur in a software operation. Specifically, a computation error that cannot be corrected later or that is not permitted to be corrected later, use of erroneous data, or the like may occur.

When performing performance analysis, there is a case where an overall operation of a program is desired to be grasped and a case where a processing status of a part of the program is desired to be analyzed. When performing program development or hardware development, or at a time of occurrence of a trouble due to a performance problem after shipment, an operation status of a specific task or process is often desired to be analyzed in detail. Thus, in this embodiment, an address range of a target instruction code301for execution of the specific task or process, a demanded accuracy, and a synchronization interval are defined in a definition table250in advance. The synchronization interval is defined by the number of instructions, as described above. When the address of the target instruction code301whose simulation is to be executed is included in a range defined in the definition table250, the timing management unit132adjusts the interval of synchronizing the time of the respective cores to the interval defined in the definition table250. If the address of the target instruction code301whose simulation is to be executed is not included in the range defined in the definition table250, the timing management unit132can set the interval of synchronizing the times of the respective cores to be long at a level that will cause no problem in the software operation.

The definition information251is stored in the definition table250. As described above, in this embodiment, the definition information251defines the length of the “period” for each address range of the memory520included in the system500, where the instructions are stored.

FIG. 3illustrates an example of the definition table250. In this example, the definition table250illustrates each set of start and end addresses for disposing the instructions to be analyzed in detail, and the number of instructions for a corresponding synchronization interval. The start address and the end address may be replaced with the start address and the instruction size. The number of instructions for the corresponding synchronization interval may be replaced with a period of time of the corresponding synchronization interval.

In this embodiment, a timing for synchronizing the times of the respective cores is dynamically adjusted. With this arrangement, among the instructions of the program to be simulated, simulation with a good time accuracy can be performed for the instruction disposed within an address region necessary for the performance analysis, and simulation at high speed can be performed for the instruction disposed outside the address region necessary for the performance analysis.

In this embodiment, the “plurality of components” are the plurality of cores of the processor. As described above, the “plurality of components” may be the plurality of processors. That is, in this embodiment, simulation of the multi-core system is performed; however, simulation of the multi-CPU system may be performed by a similar method.

Operations of the simulation apparatus100will be described, with reference toFIG. 4. The operations of the simulation apparatus100correspond to a simulation method according to this embodiment. The operations of the simulation apparatus100correspond to a processing procedure of a simulation program according to this embodiment.

In step S11, the core determination unit131that is a constituent of the adjustment unit103determines the core to subsequently execute an instruction. When there is no difference in instruction execution statuses of the respective cores, or when time lapses of the respective cores are equivalent, the core determination unit131selects an arbitrary core. When there is a difference in the instruction execution statuses of the respective cores, or when a time of one of the cores is ahead, the core determination unit131selects the core whose time is delayed.

In step S12, the selection unit101selects the context information of the core selected in step S11, as reference information for execution of the instructions.

An execution instruction address that is the address of the instruction to be subsequently executed by the core selected in step S11is defined by the context information of that core. In step S13, if the instruction at the execution instruction address constitutes a target instruction code301that is not converted to a host instruction code302, the flow proceeds to step S14. If the instruction at the execution instruction address constitutes a target instruction code301that has already been converted to the host instruction code302, the flow proceeds to step S19.

In step S14, the decode processing unit121that is a constituent of the simulation unit102loads the target instruction code301at the execution instruction address.

In step S15, the decode processing unit121decodes the target instruction code301loaded in step S14.

In step S16, the conversion processing unit122that is a constituent of the simulation unit102converts the target instruction code301decoded in step S15to one or more host instruction codes302. The host instruction codes302are an instruction string including one or more instructions. The conversion processing unit122embeds internal resource information of a register and so on into the one or more host instruction codes302by referring to the context information selected in step S12.

In step S17, the conversion processing unit122stores the one or more host instruction codes302obtained in step S16in the storage medium200as one block.

In step S18, the timing management unit132that is a constituent of the adjustment unit103refers to the definition table250to determine whether the execution instruction address of the instruction converted in step S16is within the range defined in the definition table250. If the execution instruction address is within the range defined in the definition table250, the timing management unit132determines whether the number of instructions converted in step S15which has occurred since step S12occurred last is less than the number of instructions for the synchronization interval defined in the definition table250. If the number of the converted instructions is less than the number of instructions for the synchronization interval, the flow returns to step S13. If the number of the converted instructions is not less than the number of instructions for the synchronization interval, the flow proceeds to step S19. If the execution instruction address is outside the range defined in the definition table250, the timing management unit132determines whether the number of the converted instructions is less than the certain number of instructions. If the number of the converted instructions is less than the certain number of instructions, the flow returns to step S13. If the number of the converted instructions is not less than the certain number of instructions, the flow proceeds to step S19.

If the flow returns from step S18to step S13and the processes from step S14to step S17are performed, that is, if the instruction decode process and the instruction conversion process are continuously performed, the host instruction codes302obtained in step S16are stored in the storage medium200as the same block. At a point of time when the flow proceeds to step S19, that is, at a point of time when the instruction decode process and the instruction conversion process are completed, registration of that block is completed.

In step S19, the execution processing unit123that is a constituent of the simulation unit102executes the one or more host instruction codes302obtained in step S17. The one or more host instruction codes302are executed for each block. When execution of one block is completed, time lapses of the cores are synchronized. That is, after step S19, the flow returns to step S11, and the core out of the core X511and the core Y512whose time lapse is delayed is selected, as the core that is to subsequently execute an instruction.

In this embodiment, the synchronization interval defined in the definition table250is the number of instructions to be converted into one block in the processes from step S14to step S17. Each time when execution of one block is finished, synchronization between the cores is performed. Thus, by changing the number of instructions to be converted into one block according to the address range of the target instruction code301, the synchronization can be performed at timings at which the synchronization is necessary. With respect to the target instruction code301whose address is not included in the range defined in the definition table250, one or more instructions, the number of which is the certain number defined in advance, are converted into the same block. Therefore, the number of times of synchronization is greatly reduced though a synchronization interval is extended. Accordingly, host instruction codes302can be executed at high speed. The “certain number defined in advance” is in the order of dozens of instructions. As described above, a method of closing each block using a branch instruction or a synchronization instruction is also used together.

FIG. 5illustrates an example of a synchronization process of the simulation apparatus100. It is assumed in this example that addresses of instructions0to2of the core X511and addresses of instructions0to2of the core Y512are all within the ranges defined in the definition table250. It is assumed that the number of instructions for the synchronization interval with respect to each of those ranges defined in the definition table250is 1.

It is assumed that the core X511has been first selected, and that execution of the instruction0of the core X511has been simulated. With respect to the instruction0of the core X511, the number of instructions for the synchronization interval is 1. Thus, execution of one block is completed at a point of time when execution of the instruction0of the core X511has been simulated. Since a situation occurs where the time of the core X511advances just by one instruction, the core Y512is subsequently selected, and execution of the instruction0of the core Y512is simulated. This synchronizes the times of the core X511and the core Y512. It may be so arranged that the core Y512is first selected and that execution of the instruction0of the core Y512is simulated.

With respect to the instruction0of the core Y512as well, the number of instructions for the synchronization interval is 1. Thus, execution of one block is completed at a point of time when execution of the instruction0of the core Y512has been simulated. Subsequently, the core X511may be selected, or the core Y512may be selected because the selection is to be made immediately after the times of the core X511and the core Y512is synchronized. It is assumed herein that the core X511has been selected and execution of the instruction1of the core X511has been simulated. With respect to the instruction1of the core X511as well, the number of instructions for the synchronization interval is 1. Thus, execution of one block is completed at a point of time when execution of the instruction1of the core X511has been simulated. Since a situation occurs again where the time of the core X511advances just by one instruction, the core Y512is subsequently selected, and execution of the instruction1of the core Y512is simulated. This synchronizes the times of the core X511and the core Y512. Thereafter, the instruction2of the core X511and the instruction2of the core Y512are sequentially executed in a similar way. When time lapses differ for each instruction, time comparison is made for core selection. That is, the core whose time is delayed is selected.

FIG. 6illustrates another example of the synchronization process of the simulation apparatus100. It is assumed in this example that addresses of instructions0to9of the core X511and addresses of instructions0to9of the core Y512are all within the ranges defined in the definition table250. It is assumed that the number of instructions for the synchronization interval with respect to each of those ranges of defined in the definition table250is 5. Even if the addresses of the instructions0to9of the core X511and the addresses of the instructions0to9of the core Y512are outside the ranges defined in the definition table250, the process is the same as that illustrated inFIG. 6if the “certain number defined in advance” is 5.

It is assumed that the core X511has been first selected, and that execution of the instruction0of the core X511has been simulated. With respect to the instructions0to4of the core X511, the number of instructions for the synchronization interval is 5. Thus, execution of one block is not completed at a point of time when execution of the instruction0of the core X511has been simulated. Accordingly, execution of the instructions1to4of the core X511is successively simulated. Execution of one block is completed at a point of time when execution of the instruction4of the core X511has been simulated. Since a situation occurs where the time of the core X511advances just by 5 instructions, the core Y512is subsequently selected, and execution of the instruction0of the core Y512is simulated. With respect to the instructions0to4of the core Y512as well, the number of instructions for the synchronization interval is 5. Thus, execution of one block is not completed at a point of time when execution of the instruction0of the core Y512has been simulated. Accordingly, execution of the instructions1to4of the core Y512is successively simulated. This synchronizes the times of the core X511and the core Y512. It may be so arranged that the core Y512is first selected and that execution of the instruction0of the core Y512is simulated.

Execution of one block is completed at a point of time when execution of the instruction4of the core Y512has been simulated. Subsequently, the core X511may be selected, or the core Y512may be selected because the selection is to be made immediately after the times of the core X511and the core Y512are synchronized. It is assumed herein that the core X511has been selected and execution of the instruction5of the core X511has been simulated. With respect to the instructions5to9of the core X511as well, the number of instructions for the synchronization interval is 5. Thus, execution of one block is not completed at a point of time when execution of the instruction5of the core X511has been simulated. Accordingly, execution of the instructions6to9of the core X511is successively simulated. Execution of one block is completed at a point of time when execution of the instruction9of the core X511has been simulated. Since a situation occurs again where the time of the core X511advances just by 5 instructions, the core Y512is subsequently selected, and execution of the instruction5of the core Y512is simulated. With respect to the instructions5to9of the core Y512as well, the number of instructions for the synchronization interval is 5. Thus, execution of one block is not completed at a point of time when execution of the instruction5of the core Y512has been simulated. Accordingly, execution of the instructions6to9of the core Y512is successively simulated. This synchronizes the times of the core X511and the core Y512.

In this embodiment, a timing for switching simulation of the core X511and the core Y512is adjusted depending on execution of which instruction is to be simulated. Therefore, according to this embodiment, the simulation can be sped up.

Second Embodiment

With respect to this embodiment, a difference from the first embodiment will be mainly described.

A configuration of a simulation apparatus100according to this embodiment will be described, with reference toFIG. 7.

As in the first embodiment, definition information251is stored in a definition table250. In the first embodiment, the definition information251defines the length of the “period” for each address range of the memory520included in the system500, where the instructions are stored. On the other hand, in this embodiment, the definition information251defines the length of a “period” for each identifier (ID) to identify, among functions included in a program to be executed by the system500, a function corresponding to at least one or some instructions.

FIG. 8illustrates an example of the definition table250. In this example, the definition table250gives an ID for each function to execute one or more instructions to be analyzed in detail and the number of instructions for a corresponding synchronization interval. The number of instructions for the corresponding synchronization interval may be replaced with a period of time of the corresponding synchronization interval.

As illustrated inFIG. 7, in this embodiment, a function disposition map260is stored in the storage medium200. The function disposition map260includes address map information on each function to be generated when the program to be simulated is compiled and linked.

Operations of the simulation apparatus100are the same as those in the first embodiment illustrated inFIG. 4, except step S18.

In step S18, a timing management unit132that is a constituent of an adjustment unit103identifies an execution task which is a function to execute an instruction converted in step S16, based on information of the function disposition map260. The timing management unit132refers to the definition table250to determine whether the identified execution task is defined in the definition table250. If the execution task is defined in the definition table250, the timing management unit132determines whether the number of instructions converted in step S15which has occurred since step S12occurred last is less than the number of instructions for the synchronization interval defined in the definition table250. If the number of the converted instructions is less than the number of instructions for the synchronization interval, the flow returns to step S13. If the number of the converted instructions is not less than the number of instructions for the synchronization interval, the flow proceeds to step S19. If the execution task is not defined in the definition table250, the timing management unit132determines whether the number of the converted instructions is less than the certain number of instructions. If the number of the converted instructions is less than the certain number of instructions, the flow returns to step S13. If the number of the converted instructions is not less than the certain number of instructions, the flow proceeds to step S19.

In this embodiment, the synchronization interval defined in the definition table250is the number of instructions to be converted into one block in the processes from step S14to step S17, as in the first embodiment. Each time execution of one block is finished, synchronization between the cores is performed. Thus, by changing the number of instructions to be converted into one block according to the function of a target instruction code301, the synchronization can be performed at timings at which the synchronization is necessary. With respect to the target instruction code301whose function is not defined in the definition table250, one or more instructions, the number of which is the certain number defined in advance, are converted into the same block. Therefore, the number of times of synchronization is greatly reduced though a synchronization interval is extended. Accordingly, a host instruction code302can be executed at high speed. In this embodiment as well, the method of closing each block using a branch instruction or a synchronization instruction is also used together.

Hereinafter, an example of a hardware configuration of the simulation apparatus100according to each embodiment of the present invention will be described with reference toFIG. 9.

The simulation apparatus100is a computer. The simulation apparatus100includes hardware devices such as a processor901, an auxiliary storage device902, a memory903, a communication device904, an input interface905, and a display interface906. The processor901is connected to the other hardware devices via a signal line910, and controls the other hardware devices. The input interface905is connected to an input device907. The display interface906is connected to a display908.

The processor901is an integrated circuit (IC) to perform processing. The processor901corresponds to the host CPU.

The auxiliary storage device902is a read only memory (ROM), a flash memory, or a hard disk drive (HDD), for example. The auxiliary storage device902corresponds to the storage medium200.

The memory903is a random access memory (RAM), for example. The memory903corresponds to the storage medium200.

The communication device904includes a receiver921to receive data and a transmitter922to transmit data. The communication device904is a communication chip or a network interface card (NIC), for example.

The input interface905is a port to which a cable911of the input device907is connected. The input interface905is a universal serial bus (USB) terminal, for example.

The display interface906is a port to which a cable912of the display908is connected. The display interface906is a USB terminal or a high definition multimedia interface (HDMI (registered trademark)) terminal, for example.

The input device907is a mouse, a stylus, a keyboard, or a touch panel, for example.

The display908is a liquid crystal display (LCD), for example.

A program to implement functions of “units” such as the selection unit101, the simulation unit102, and the adjustment unit103is stored in the auxiliary storage device902. This program is loaded into the memory903, read into the processor901, and executed by the processor901. An operating system (OS) is also stored in the auxiliary storage device902. At least part of the OS is loaded into the memory903, and the processor901executes the program to implement the functions of the “units” while executing the OS.

ThoughFIG. 9illustrates one processor901, the simulation apparatus100may include a plurality of processors901. Then, the plurality of processors901may cooperate and execute programs to implement the functions of the “units”.

Information, data, signal values, and variable values indicating results of processes executed by the “units” are stored in the auxiliary storage device902, the memory903, or a register or a cache memory in the processor901.

The “units” may be provided as “circuitry”. Alternatively, a “unit” may be read as a “circuit”, a “step”, a “procedure”, or a “process”. The “circuit” and the “circuitry” are each a concept including not only the processor901but also a processing circuit of a different type such as a logic IC, a gate array (GA), an application specific integrated circuit (ASIC), or a field-programmable gate array (FPGA).

Embodiments of the present invention have been described above; some of these embodiments may be combined to be carried out. Alternatively, any one or some of these embodiments may be partially carried out. Only one of the “units” described in the descriptions of these embodiments may be adopted, or an arbitrary combination of some of the “units” may be adopted, for example. The present invention is not limited to these embodiments, and various modifications are possible as necessary.

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