Method and system for correcting timing errors in high data rate automated test equipment

A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by another component in the system. Embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error. The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.

BACKGROUND OF THE INVENTION

As the speed and complexity of integrated circuits increase, the data rates used by automated test equipment (ATE) for testing such integrated circuits is also increasing. For example, while data rates near a single Gbps were once sufficient for the testing of most any integrated circuit, modern integrated circuits require much higher data rates approaching 10 Gbps. And in the future, data rates required to test new integrated circuits will continue to increase as technology improves.

In addition to higher data rates, the testing of modern integrated circuits also requires higher precision with reduced timing error. As discussed in U.S. Pat. No. 6,496,953 to Helland, which is hereby incorporated by reference in its entirety, timing error in an ATE test signal varies based upon the pulse width of the signal preceding a given event (e.g., a transition from one state to another of the test signal). As such, timing error due to pulse width should be accounted for to increase edge placement accuracy and enable the testing of higher speed integrated circuits.

Although the '953 patent proposes a solution for correcting pulse width timing error, the data rate for testing integrated circuits of the system taught in the '953 patent is limited. As such, as higher-speed integrated circuits emerge, the system taught in the '953 patent will be able to test fewer and fewer devices.

SUMMARY OF THE INVENTION

Accordingly, a need exists for automated test equipment (ATE) capable of testing high speed integrated circuits. Additionally, a need exists for testing such high speed integrated circuits with reduced timing error. Further, a need exists to reduce pulse width timing error in an ATE instrument capable of testing high speed integrated circuits. Embodiments of the present invention provide novel solutions to these needs and others as described below.

Embodiments of the present invention are directed towards a system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. More specifically, embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating processing tasks to multiple test components, where the resulting data rate of the system may approach the sum of the data rates of the individual components. Each component is able to perform data-dependent timing error correction on data processed by the component, where the timing error may result from data processed by the component itself or another component in the system. In the case where the timing error results from data processed by another component, embodiments enable timing error correction by making the component performing the correction aware of the data (e.g., processed by another component) causing the error (e.g., a pulse width timing error). The data may be shared between components using existing timing interfaces, thereby saving the cost associated with the design, verification and manufacturing of new and/or additional hardware.

In one embodiment, an automated test equipment system includes a first test component for generating a first test signal for testing an integrated circuit, the first test signal generated in response to receiving a first portion of functional data for testing the integrated circuit, wherein the first test component is operable to correct timing errors in the first test signal using data from the first portion. The system also includes a second test component for generating a second test signal for testing the integrated circuit, the second test signal generated in response to receiving a second portion of the functional data for testing the integrated circuit, wherein the second test component is operable to correct timing errors in the second test signal using data from the second portion. An interface is coupled to the second test component and for enabling the second test component to access a select sub-portion of the first portion of the functional data. The second test component is further operable to correct timing errors in the second test signal using the select sub-portion fed to the second test component via the interface, where the select sub-portion is processed before the second portion of the functional data.

In another embodiment, a method for correcting timing errors in automated test equipment includes accessing functional data for testing an integrated circuit, the functional data comprising a first data portion and a second data portion, the first data portion for processing on a first test component and the second data portion for processing on a second test component. A timing value is determined for the second data portion, the timing value indicating when an event associated with the second data portion shall occur. A timing correction value is also determined for the second data portion based upon a portion of a pulse width associated with the first data portion. The timing value is then adjusted by the timing correction value to generate an updated timing value for the event.

And in yet another embodiment, a method for increasing data rates of automated test equipment with data-dependent timing correction capabilities includes accessing functional data for testing an integrated circuit, the functional data comprising a first data portion and a second data portion, the first data portion adjoining and processed before the second data portion. The first data portion is allocated to a first test component for generating a first test signal, wherein the first data portion comprises a portion of a pulse width. The second data portion is allocated to a second test component for generating a second test signal, wherein the second data portion has a timing value indicating when an event associated with the second data portion shall occur. An updated timing value is generated for the event by applying a timing correction value to the timing value, the timing correction value based upon the portion of a pulse width of the first data portion. The first test signal is generated. The second test signal is generated in accordance with the updated timing value. The first and second test signals are then provided to the integrated circuit for testing thereof.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the Invention

FIG. 1shows exemplary timing diagram100of state and timing characteristics of a test event in accordance with one embodiment of the present invention. As shown inFIG. 1, test signal110(e.g., generated from functional test data) undergoes several events (e.g., a transition from state0to state1, or from state1to state0). For example, event120involves a change from state1to state0at a given timing value (e.g., labeled “original timing value”). As such, each test event (e.g.,120) has a respective state (e.g., state0) and a respective timing value (e.g., “original timing value”).

Test signal110may be fed from automated test equipment (ATE) to an integrated circuit (e.g., a device under test or DUT) for testing thereof. As such, the DUT may receive the test signal (e.g.,110) comprising an event sequence, where a response from the DUT may be processed by the ATE (e.g., to determine whether the DUT passes or fails the test).

One of the most significant sources of error in ATE test signals (e.g.,110) is pulse width timing error. Pulse width timing error is caused by a pulse in functional data preceding an edge (e.g., a test signal transition comprising an event), where the duration of the pulse may affect edge placement accuracy. For example, pulse width130, which begins at event140and ends at event120, may cause incorrect edge placement of event120. As such, embodiments enable a corrected timing value (e.g., as indicated by the dashed lines) to be determined (e.g., based upon functional data preceding an event) and applied to event120to reduce associated timing error (e.g., represented inFIG. 1by the distance between the original and corrected timing values for event120). Additionally, embodiments enable timing error correction in systems utilizing multiple test components processing respective portions of a functional data stream, where data contributing to a timing error affecting an event can be processed on a different system from that processing the functional data comprising the event itself.

FIG. 2shows exemplary system200with multiple test components for testing integrated circuits in accordance with one embodiment of the present invention. As shown inFIG. 2, programmable logic component210(e.g., implemented by an FPGA or the like) receives both functional data (FData) and timing information conveyed over the vector type select (VTS) input. The FData (e.g., comprising at least one test pattern for testing a coupled DUT) is fed to component210using a 32-bit stream of functional data (e.g., conveyed over a 32-bit wide interface, using a 32-bit word length, etc.), which may indicate multiple events to be performed in accordance with timing information fed to component210(e.g., via the VTS input). The FData is then split into multiple portions (e.g., F0-F15, F16-F31, etc.) to feed respective test components230aand230b. In one embodiment, test components230aand230bmay be implemented in accordance with the '953 patent to Helland.

In response to receipt of FData and/or VTS signals, test components (e.g.,230aand230b) may generate test signals (e.g.,110) for testing DUT250. As shown inFIG. 2, the test signals are fed to and/or from DUT250via pin electronics component240(e.g., comprising drivers, comparators, etc. necessary to communicate signals between DUT250and test components of system200).

Since the test signals generated by each test component may represent adjoining portions of FData, sending the respective test signals to a DUT may effectively replicate a more powerful test component sending a single test signal representing the FData data stream input to component210. As such, data processing tasks are divided among multiple test components (e.g.,230a,230b, etc.) to effectively increase the data rate of system200(e.g., to a data rate approaching the sum of the individual data rates of components230aand230b).

In addition to offering higher data rates for testing DUTs (e.g.,250), system200can provide timing correction for test signals generated by the multiple test components (e.g.,230a,230b, etc.). Component210comprises multiplexers220and225(e.g., implemented in hardware, software, etc.) to enable test components of system200to receive portions of data (e.g., labeled FData′) allocated to other test components of system200, thereby enabling the test components to correct timing errors resulting from functional data (e.g. comprising at least a portion of a pulse width preceding an event) processed by other test components. For example, multiplexer220conveys FData′ bits F29-F31(e.g., processed by test component230b) to test component230asuch that test component230acan correct timing errors resulting from data processed by test component230b(e.g., where bits F29, F30and/or F31may comprise a portion of a pulse width causing timing error for an event processed by test component230b). Similarly, multiplexer225conveys FData′ bits F13-F15(e.g., processed by test component230a) to test component230bsuch that test component230bcan correct timing errors resulting from data processed by test component230a(e.g., where bits F13, F14and/or F15may comprise a portion of a pulse width causing timing error for an event processed by test component230a).

As shown inFIG. 2, component210sends the portions of FData′ used for correcting timing errors over unused portions of the VTS interface to the respective test components (e.g.,230a,230b, etc.). For example, a number of bits are siphoned off of the VTS input to component210to generate VTS signal211, where the siphoned portion (e.g., thereafter unused) is fed to multiplexers220and225via respective input signals212and213. The unused bits (e.g., those originally occupied by bits comprising signals212and213) may then be replaced with FData′ bits (e.g., accessed from the main FData′ input to component210) by combining the FData′ bits output from multiplexers220and225with the remaining VTS bits conveyed by signal211. Test components (e.g.,230aand/or230b) may then receive the combined VTS/FData′ signals (e.g., timing information and timing correction information) to generate test signals for testing coupled DUTs (e.g.,250). Thus, by sending portions of the FData′ needed for timing correction over existing VTS paths, embodiments save the cost associated with the design, verification and manufacturing of new and/or additional hardware.

AlthoughFIG. 2shows only two test components (e.g.,230aand230b), it should be appreciated that more than two test components may process data from the same data stream and generate test signals for testing a DUT (e.g.,250) at even higher data rates in other embodiments. Additionally, although only one pin electronics component (e.g.,240) is depicted inFIG. 2, it should be appreciated that more than one pin electronics component may be used in other embodiments. Further, although only one DUT (e.g.,250) is depicted inFIG. 2, It should also be appreciated that multiple DUTs may be tested simultaneously in other embodiments.

Although programmable logic component210is depicted with specific signal paths and components (e.g., multiplexers220and225), it should be appreciated that component210may be alternatively configured (e.g., to accommodate more test components, to accommodate alternatively-configured test components, to direct FData and/or FData′ over different signal paths, using lookup tables instead of multiplexers, etc.). Additionally, althoughFIG. 2shows only a 32-bit FData signal path feeding component210, it should be appreciated that a larger or smaller FData signal path may be used in other embodiments. Further, althoughFIG. 2depicts only a 3-bit FData′ signal path leading to multiplexers220and222for timing correction purposes, it should be appreciated that a larger or smaller number of FData′ bits may be used in other embodiments. Additionally, althoughFIG. 2depicts an even allocation of FData between test components, it should be appreciated that an uneven allocation may be used in other embodiments.

FIG. 3shows exemplary test component230(e.g., used to implement components230aand/or230bofFIG. 2) in accordance with one embodiment of the present invention. It should be appreciated that test component230may be implemented using an application-specific integrated circuit (ASIC), or the like. Alternatively, test components230may be implemented in accordance with the '953 patent to Helland. As shown inFIG. 3, timing information (e.g., generated by a user input to programmable logic component210, generated automatically by a software program, etc.) and timing correction information (labeled as VTS/FData′) is fed to test component230. The timing information (VTS) may then be fed to compression component310for compressing the timing information and generating compressed timing information (VTS′). The timing information may be compressed in accordance with compression information (e.g., a lookup table which may be indexed using uncompressed timing information to retrieve compressed timing information) stored in compression memory320. The compressed timing information may then be joined with the timing correction information (FData′) and fed to test signal processors (e.g.,330a-330n, where n may represent any number greater than two) for providing timing information and timing correction information for generated test signals.

Test signal processors330athrough330nmay generate test signals based upon functional data (FData) received by test component230and fed to each test signal processor. As such, the test signal processors may receive state information (e.g., a bit state as shown and described above with respect toFIG. 1) from the FData signal, which may then be used in conjunction with corrected timing information received from the VTS′/FData′ signal to generate test signals for testing a DUT (e.g.,250ofFIG. 2).

As shown inFIG. 3, the signals output from each test signal processor may be fed to a respective pin of a DUT (e.g.,250ofFIG. 2) using a pin electronics component (e.g.,240ofFIG. 2), where a similar test signal processor of another test component may also couple to the respective pins of the DUT to effectively send a complied test signal representing the FData input to the system (e.g., system200ofFIG. 2). Alternatively, signals from one or more test signal processors (e.g., of the same test component) may be fed to a DUT pin, where test signals from other test components may additionally be fed to the DUT pin.

FIG. 4shows exemplary test signal processor330(e.g., used to implement processors330a-330nofFIG. 3) in accordance with one embodiment of the present invention. As shown inFIG. 4, timing value generator generates timing values (e.g., the original timing value as shown inFIG. 1) for events (e.g.,120ofFIG. 1) by accessing timing value memory420using VTS′ information fed to generator410. The VTS′ information may indicate a portion of timing information (e.g., a set of timing information for a group of data sharing a common timing offset, test period, etc.) stored in memory420, where generator410may then select a timing value from the portion of timing information for a currently-processed event. Once the timing value is generated by generator410, it may be output to timing logic450for timing correction (if needed) as discussed below.

Timing value memory420may be periodically filled and/or refreshed based upon test characteristics input to test signal processor330. In one embodiment, the filling and/or refreshing may be performed by timing value generator410. The values input to memory420may be determined in one embodiment by the equation:
Tx=O+((P/B)*x),
where Tx represents a timing value for a given bit of a bit stream, O represents a timing offset (e.g., applied to one or more bits processed by a test component), P represents a test period (e.g., a time required for a test component to process a given string of bits), B represents a number of bits processed by an individual test component (e.g.,16as shown inFIG. 2), and x is varied from zero to B-1to generate timing values comprising a timing value set to be stored in memory420(e.g., as a data table therein). Other timing value sets may be generated and stored in memory420, where each set may have at least one common test characteristic (e.g., offset, period, etc.).

FIG. 5shows exemplary timing value data table500stored in memory (e.g., timing value memory420) in accordance with one embodiment of the present invention. As shown inFIG. 5, data table500comprises multiple timing sets which may be selected (e.g., using VTS′ input to timing value generator410), where each timing set has values which may correspond to a bit in a functional data stream (e.g., the 32-bit FData stream as shown inFIG. 2). Each timing set shares a common timing offset (e.g., each timing value of timing set1has an offset of 1.1 ns, etc.). However, in other embodiments, each set may share another test characteristic (e.g., period, etc.). Alternatively, timing sets of data table500may comprise different shared test characteristics. Additionally, althoughFIG. 5shows timing sets with timing values for only 32 bits, it should be appreciated that data table500may comprise timing values for a larger or smaller number of bits in other embodiments.

Turning back toFIG. 4and using the timing values ofFIG. 5as examples, timing value generator may begin processing a bit of a functional data stream (e.g., FData ofFIG. 2) representing an event (e.g.,120ofFIG. 1). A received VTS′ input may indicate that a specific timing set is to be used to determine a timing value for that event. Thereafter, generator may use the indicated timing set and the bit number of the event to determine a timing value. For example, if the current event processed by a test component comprises bit F2of the data stream and the VTS′ input indicates that timing set2is to be used, then generator410may determine that the timing value for that event is 2.125 ns. The determined timing value may then be sent to timing logic450for correction (if needed).

As shown inFIG. 4, timing correction value generator430receives data (e.g., FData′ and/or portions of FData) for generating a timing correction value. FData′ may comprise functional data processed by other test components than that processing the event, while the portions of FData may comprise functional data processed by the same test component processing the event. As such, portions of the FData′ signal may be used if data preceding the event and contributing to the timing error are processed as events by another test component.

FIG. 6shows exemplary data stream610for allocation among multiple test components in accordance with one embodiment of the present invention. As shown inFIG. 5, data stream610may comprise functional data representing event states for a plurality of bits (e.g., F0-F31). Bits F0-F15may be allocated for event processing to a first test component (e.g.,230aofFIG. 2), while bits F16-F31may be allocated for event processing to a second test component (e.g.,230bofFIG. 2).

As shown inFIG. 6, several 4-bit data blocks are denoted. Block620represents an event processed at bit F10, where generation of a timing correction value for the event may consider a pulse duration (or a portion thereof) within bits F7through F10(e.g., all processed by the first test component). Similarly, block630represents an event processed at bit F22, where generation of a timing correction value may consider a pulse duration (or a portion thereof) within bits F19through F22(e.g., all processed by the second test component). However, block640represents an event processed at bit F16, where generation of a timing correction value may consider a pulse duration (or a portion thereof) within bits F13through F16. As such, block640presents a situation where correction of a timing error must use FData′ from another test component (e.g., the first test component inFIG. 6) than that processing the event (e.g., the second test component inFIG. 6), while blocks620and630required only the use of FData from the same test component processing the event.

Turning back toFIG. 4, timing correction value generator430may generate a timing correction value by accessing timing correction value memory440. FData and/or FData′ input to generator430may be used to identify a timing correction value stored within memory440, where generator430may then access the identified timing correction value for generation thereof. Once the timing correction value is generated by generator430, it may be output to timing logic450for timing correction (if needed) as discussed below.

FIG. 7shows exemplary timing correction value data table700stored in memory (e.g., timing correction value memory440) in accordance with one embodiment of the present invention. As shown inFIG. 7, the first four columns of data table700comprise bit states for an event bit (Fn) and the three bits leading up to the event bit (e.g., Fn-3through Fn-1). The bit states may represent a portion of a pulse width preceding an event that contributes to timing error for the event (e.g.,120ofFIG. 1). The fifth column specifies exemplary timing correction values for a given ordering of bit states shown in the rows of data table700. As such, a memory (e.g.,440) comprising data table700may be accessed with four bit states to then identify an appropriate timing correction value.

AlthoughFIGS. 6 and 7use 4-bit data blocks, it should be appreciated that data blocks of longer or shorter lengths may be used. Additionally, although the data blocks shown inFIG. 6and indicated inFIG. 7are continuous, it should be appreciated that non-continuous data may be used to generate timing correction values in other embodiments. Additionally, although specific data blocks are identified inFIG. 6, it should be appreciated that other data blocks may be identified in other embodiments which require a larger or smaller number of FData and/or FData′ bits to be accessed.

Turning back toFIGS. 4 and 6, when timing correction value generator430is ready to process bit F10of block620ofFIG. 6, the four bit values in block620(e.g., 1, 0, 0, 1) may be used to access data table700and determine a timing correction value of −10 ps. Alternatively, when timing correction value generator430is ready to process bit F22of block630ofFIG. 6, the four bit values in block630(e.g., 0, 1, 0, 0) may be used to access data table700and determine a timing correction value of 0 ps (e.g., no timing correction needed). Alternatively, when timing correction value generator430is ready to process bit F16of block640ofFIG. 6, the four bit values in block640(e.g., 1, 1, 0, 1) may be used to access data table700and determine a timing correction value of 15 ps.

As shown inFIG. 4, timing logic450may access both a timing value (e.g., output by generator410) and a timing correction value (e.g., output by generator430) to generate an updated timing value for a currently-processed event. In one embodiment, the logic may add the timing correction value to the timing value to generate the updated timing value. In other embodiments, other functions may be used to determine the updated timing value for a currently-processed event. If the timing correction value indicates that no correction is necessary (e.g., outputting a timing correction value of zero), then the timing value output by generator410may be output by logic450instead of an updated timing value.

Test signal generator460may access an event timing output from timing logic450(e.g., comprising the updated timing value where timing correction is needed, comprising the original timing value where no timing correction is needed, etc.) and an event state input from an FData input to test signal processor330. From this information, generator460may output a test signal (e.g.,110) comprising the event state and event timing, where the test signal may be fed to a DUT (e.g.,250ofFIG. 2) for testing (e.g., via a pin electronics component).

FIG. 8shows exemplary process800for correcting timing errors in automated test equipment in accordance with one embodiment of the present invention. As shown inFIG. 8, step810involves accessing a first and second data portion of functional data for testing an integrated circuit (DUT). The first portion may comprise bits leading up to an event bit (e.g., bits F13-F15of block640ofFIG. 6), while the second portion may comprise an event bit (e.g., F16ofFIG. 6). Additionally, the first data portion may be processed by a first test component (e.g.,230aofFIG. 2) and the second data portion may be processed by a second test component (e.g.,230bofFIG. 2), thereby dividing processing among multiple test components to increase the data rate of the system (e.g. to approach the sum of the data rates of the individual test components).

Step820involves determining a timing value for the second data portion. The timing value may be determined by a timing value generator (e.g.,410) accessing a timing value memory (e.g.,420). The timing value may depend upon one or more test characteristics (e.g., timing offset, period, etc.), which may be input to an ATE system (e.g.,200ofFIG. 2) either manually (e.g., by a user) or automatically (e.g., by a software program, etc.).

Step830involves determining a timing correction value for the second data portion. The timing correction value may be determined by a timing correction value generator (e.g.,430) accessing a timing correction value memory (e.g.,440). The timing correction value may depend upon a duration of a portion of a pulse width in data preceding the event data (e.g., represented by event120ofFIG. 1) for which the timing correction value is being determined. For example, the three bits preceding the event bit in a functional data stream may be used to determine a timing correction value (e.g., by accessing a memory similar to memory440as shown inFIG. 7). The data used for determining the timing correction value may be accessed from either the component processing the event or from another component (e.g., by feeding FData′ portions from the other components as described in the preceding Figures), thereby enabling timing error reduction for ATE systems (e.g.,200) using multiple test components regardless of which test component's data the error may be attributed.

Step840involves adjusting the timing value by the timing correction value to generate an updated timing value. The updated timing value may be generated by timing logic (e.g.,450), where the logic is operable to apply the timing correction value to the timing value to generate the updated timing value. In one embodiment, the timing correction value may be added to the timing value to generate the updated timing value. In other embodiments, other functions may be used to determine the updated timing value for a currently-processed event. If the timing correction value indicates that no correction is necessary (e.g., outputting a timing correction value of zero), then the timing value may be used instead of an updated timing value.

Step850involves generating a test signal in accordance with the updated timing value. The test signal may be generated by a test signal generator (e.g.,460of a test component (e.g.,230a,230b, etc.), where the test signal is representative of a portion of the FData fed to the test component. Thereafter, the generated test signal may be fed to a DUT (e.g.,250ofFIG. 2) in step860for testing thereof.

FIG. 9shows exemplary process900for determining a timing value in accordance with one embodiment of the present invention. As shown inFIG. 9, step910involves accepting a first input indicating desired timing characteristics for DUT testing. The desired timing characteristics may comprise test characteristics (e.g., timing offset, period, etc.). Additionally, the timing characteristics may be input to a timing value generator (e.g.,410), where the input may be either manual (e.g., by a user) or automatic (e.g., by a software program, etc.).

Step920involves calculating timing information based upon the desired timing characteristics. The timing information may comprise timing values, where the timing values may be calculated as discussed above with respect toFIG. 4.

Step930involves storing the timing information for access by a test component. The timing information (e.g., data table500) may be stored in a timing value memory (e.g.,420ofFIG. 4), where the timing information may indicate sets of timing values for various bit locations in a functional data string. The timing value sets may share at least one common test characteristic (e.g., timing offset, period, etc.).

Step940involves accessing a select timing value from the timing information based on a second input. The second input may comprise a timing set selection, where the timing set selection may be used to access a timing value memory to identify and access an appropriate timing value for a currently-processed event. The second input may be either manual (e.g., by a user) or automatic (e.g., by a software program, etc.).

FIG. 10shows exemplary process1000for increasing data rates of automated test equipment with data-dependent correction capabilities in accordance with one embodiment of the present invention. As shown inFIG. 10, step1010involves accessing a first and second data portion of functional data for testing an integrated circuit (DUT). Step1010may be performed analogously to step810ofFIG. 8.

Step1020involves allocating the first and second data portions to respective test components for processing thereon. For example, the first data portion may be processed on a first test component (e.g.,230aofFIG. 2) of a system (e.g.,200ofFIG. 2), while the second data portion may be processed on a second test component (e.g.,230bofFIG. 2) of the same system. As such, higher data rates (e.g., approaching the sum of the individual components' data rates) are possible as processing is divided among multiple test components.

Step1030involves generating an updated timing value for an event. The updated timing value may be generated as discussed above with respect toFIG. 840ofFIG. 8.

Step1040involves generating a first test signal. The first test signal may be generated by a first test component (e.g.,230aofFIG. 2) and representative of a first portion of a functional data stream (e.g., FData input to system200inFIG. 2).

Step1050involves generating a second test signal in accordance with the updated timing value. Step1050may be performed analogously to step850ofFIG. 8.

Step1060involves providing the first and second test signals to the DUT for testing thereof. As such, the DUT may be tested at higher data rates using multiple test components, where embodiments enable timing error reduction regardless of which component is processing the functional data contributing to the error.

In the foregoing specification, embodiments of the invention have been described with reference to numerous specific details that may vary from implementation to implementation. Thus, the sole and exclusive indicator of what is, and is intended by the applicant to be, the invention is the set of claims that issue from this application, in the specific form in which such claims issue, including any subsequent correction. Hence, no limitation, element, property, feature, advantage, or attribute that is not expressly recited in a claim should limit the scope of such claim in any way. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.