Semiconductor device and fabrication method

Semiconductor devices and fabrication methods are provided. First metal layers are provided in a substrate including a first region and a second region. An interlayer dielectric (ILD) layer formed over the substrate includes a top surface in the second region coplanar with a bottom of a trench in the ILD layer in the first region. Through-holes are formed in the ILD layer. A polymer layer fills the through-holes and the trench in ILD layer and covers top surface of ILD layer in both regions. The polymer layer is exposed and developed to form vias, each including an upper via in the polymer layer and a lower via in ILD layer. A second metal layer is formed to fill each via on a corresponding first metal layer in both regions. The polymer layer between adjacent second metal layers is removed to form air gaps in the second region.

CROSS-REFERENCES TO RELATED APPLICATIONS

This application claims priority to Chinese Patent Application No. CN201310739057.9, filed on Dec. 27, 2013, the entire content of which is incorporated herein by reference.

FIELD OF THE DISCLOSURE

The present disclosure relates to the field of semiconductor manufacturing technology and, more particularly, relates to semiconductor devices and fabrication methods.

BACKGROUND

With rapid development of semiconductor manufacturing technology, semiconductor chips are manufactured with high degree of integration to provide fast computing speed, great data storage capacity, and more functions. High integration degree of a semiconductor chip can provide semiconductor devices in the semiconductor chip with small critical dimensions (CDs).

When CDs of semiconductor devices are increasingly smaller, distance between adjacent interconnect structures become smaller. Consequently, capacitance between adjacent interconnect structures increases. Such capacitance is also known as parasitic capacitance. Parasitic capacitance may affect RC delay effect of the semiconductor devices and thus affect operating speed of the semiconductor chip along with reliability of the semiconductor devices in the semiconductor chip.

Conventional methods for solving problems due to parasitic capacitance include using materials with low dielectric constant to replace materials (e.g., silicon oxide) with high dielectric constant as an interlayer dielectric layer and/or a dielectric layer between metal layers to reduce capacitance between adjacent interconnect structures.

However, semiconductor devices formed by conventional methods still have parasitic capacitance problems. At certain points, RC delay effects may still cause slow operating speed and poor reliability of the semiconductor devices.

BRIEF SUMMARY OF THE DISCLOSURE

According to various embodiments, there is provided a method for forming a semiconductor device. First metal layers are provided in a substrate including a first region and a second region. The first metal layers have a top surface coplanar with a top surface of the substrate. An interlayer dielectric layer is formed over the substrate, and includes a trench in the first region and includes a top surface in the second region coplanar with a bottom of the trench in the first region. Through-holes are formed in the interlayer dielectric layer, each through-hole corresponding to one first metal layer in the first region and the second region.

A polymer layer is formed to fill the through-holes and the trench in the interlayer dielectric layer and to cover the top surface of the interlayer dielectric layer in the first and second regions. The polymer layer has a different solubility in an exposed area and in a non-exposed area. The polymer layer is exposed and developed to form vias, each including an upper via in the polymer layer and a lower via in the interlayer dielectric layer. Each via is formed on a corresponding first metal layer in the first and second regions. A second metal layer is formed to fill each via and to electrically connect to the corresponding first metal layer. The polymer layer between adjacent second metal layers is removed to form air gaps between the adjacent second metal layers in the second region.

According to various embodiments, there is also provided a semiconductor device including a substrate having a first region and a second region. First metal layers are disposed in the first and second regions. The first metal layers have a top surface coplanar with a top surface of the substrate. An interlayer dielectric layer is disposed over the substrate. Second metal layers are disposed on corresponding first metal layers in the first and second regions. Each second metal layer has a lower metal layer through the interlayer dielectric layer and an upper metal layer protruded over and disposed on a top surface of the interlayer dielectric layer.

Air gaps are formed between adjacent second metal layers in the second region by: forming through-holes in the interlayer dielectric layer, each through-hole corresponding to one first metal layer in the first region and the second region. The interlayer dielectric layer further includes a trench in the first region. A polymer layer is formed to fill the through-holes and the trench in the interlayer dielectric layer and to cover the top surface of the interlayer dielectric layer in the first and second regions. The polymer layer has a different solubility in an exposed area and in a non-exposed area, and is then exposed and developed the polymer layer to form vias. Each via includes an upper via in the polymer layer and a lower via in the interlayer dielectric layer, and each via is formed on a corresponding first metal layer in the first and second regions. A second metal layer fills each via and electrically connects to the corresponding first metal layer. The polymer layer between adjacent second metal layers is then removed to form air gaps between the adjacent second metal layers in the second region.

DETAILED DESCRIPTION

Semiconductor devices formed by conventional methods may have parasitic capacitance problems such as RC delay effects, which may cause slow operating speed and poor reliability of the semiconductor devices. Parasitic capacitance can be proportional to dielectric constant k of a semiconductor device. Lowering the k value of an interlayer dielectric layer and/or a dielectric layer between metal layers may reduce parasitic capacitance of the semiconductor device. Ideally, the dielectric constant k of the interlayer dielectric layer and the dielectric layer between metal layers can be reduced to about 1.0, which is the dielectric constant of vacuum. The dielectric constant of air is about 1.001, close to that of the vacuum.

An air gap can be formed between interconnect structures of a semiconductor device to effectively reduce parasitic capacitance of the semiconductor device and to improve RC delay effect, operating speed, and reliability of the semiconductor device.

FIG. 1depicts a semiconductor device including air gaps. As shown inFIG. 1, semiconductor substrate100is provided and includes a first region I′ and a second region II′. In the second region II′, first metal layers101can be formed in the semiconductor substrate100. Etch stop layer102is formed on surface of semiconductor substrate100. Interlayer dielectric layer103is formed on surface of etch stop layer102. Openings are formed in interlayer dielectric layer103by an etching process performed in the second region II′, followed by filling the openings with metals to form second metal layers109. Air gaps110are then formed in interlayer dielectric layer103between adjacent second metal layers109.

Air gaps110are formed by a photolithographic process using a patterned photoresist layer (not shown). For example, the patterned photoresist layer can be formed on interlayer dielectric layer103. The patterned photoresist layer can have openings corresponding to air gaps110to be formed in interlayer dielectric layer103and can be used as an etch mask in an etching process for forming air gaps110in interlayer dielectric layer103.

Air gaps110formed in interlayer dielectric layer103as shown inFIG. 1, however, has a small feature size (or critical dimension). The formed semiconductor device can thus have a small area of air gaps, which may have limited air-gap effect on effectively reducing k value of the semiconductor device. RC delay effect of the semiconductor device may still occur and operating speed of the semiconductor device may need to be improved.

In addition, air gaps110are formed in interlayer dielectric layer103by a photolithographic process. Overlay errors may occur to the openings in the patterned photoresist layer after the etching process for forming the openings. To avoid undesired etching of second metal layer109caused by the overlay errors (or misalignment) when forming air gaps110, the patterned photoresist layer has to be formed to provide a sufficient distance between second metal layers109to provide a sufficient window for the patterning and etching processes in interlayer dielectric layer103. Further, interlayer dielectric layer103between air gap110and second metal layer109can take up a certain width/area, which in turn results in small air gaps.

In various embodiments, air gaps can be formed by completely removing interlayer dielectric layer between adjacent second metal layers such that the feature size of an air gap can be can be significantly increased. Dielectric constant k value of the formed semiconductor device can thus be effectively reduced. RC delay effect can be improved and operating speed of the semiconductor device can be increased.

For example, through-holes can be formed through an interlayer dielectric layer on a substrate surface. A polymer layer can be formed in the through-holes and on surface of the interlayer dielectric layer. Vias can be formed in the polymer layer and the interlayer dielectric layer. By annealing remaining polymer layer after forming the vias, the polymer layer can be oxidized into an oxide layer. A second metal layer can be formed by filling the vias with metal material(s). The oxide layer between adjacent second metal layers can then be completely removed to form air gaps. As such, the air gaps can have large feature sizes to effectively reduce the k value of the semiconductor device. RC delay effect can be improved and operating speed of the semiconductor device can be increased. In addition, the manufacturing process is simplified.

FIGS. 2-10depict cross-sectional views of an exemplary semiconductor device at various stages during its formation in accordance with various disclosed embodiments.

Referring toFIG. 2, substrate200is provided. Substrate200includes a first region I and a second region II. First metal layers201are formed in the first and second regions of substrate200. First metal layers201can have a top surface coplanar with a top surface of substrate200(e.g., in Step1102).

Substrate200can provide a platform for subsequent processes of forming a semiconductor device. Substrate200can be made of a material including silicon, polycrystalline silicon, or amorphous silicon. In some cases, substrate200can be made of a material including a silicon germanium compound, or silicon-on-insulator (SOI). In one embodiment, semiconductor devices, such as MOS transistors, can be made within substrate200. In an exemplary embodiment, substrate200can be a silicon substrate.

The first region I and the second region II can be positioned or arranged interchangeably and/or can be positioned adjacently or separately, e.g., in a whole wafer. The first region I and the second region II of substrate200can be used to define areas in substrate200for forming or not-forming air gaps.

For example, the first region I and the second region II can be positioned adjacent with one another, while air gaps are formed in the second region II and no air gaps are formed in the first region I, as shown inFIGS. 2-10. In some embodiments, substrate200can include the first region I and the second region II each containing air gaps formed therein (not illustrated). In other embodiments, substrate200can only include an area for forming air gaps (not illustrated).

First metal layers201can be electrically connected to interconnect structures to be formed subsequently. In various embodiments, first metal layers201can be used to electrically connect the interconnect structures to be formed subsequently with an external circuit or other metal layer(s). First metal layers201can be made of a material including Cu, Al, W, and/or any suitable conductive material(s).

Note that any number (e.g., one, two, four, eight, etc.) of first metal layers201can be included in the exemplary regions of substrate200, althoughFIG. 2shows one first metal layer in the first region I and three first metal layers in the second region II of substrate200for illustration purposes.

In the embodiment when air gaps are formed in the second region II and no air gaps are formed in the first region I, first metal layers201arranged in the second region II can have a density greater than those arranged in the first region I. Accordingly, second metal layers subsequently formed on first metal layers201in the second region II can have a density greater than those arranged in the first region I. While air gaps are to be formed between adjacent densely-arranged second metal layers in the second region II, less-densely-arranged second metal layers in the first region I can also be formed, e.g., surrounding the second region II, to provide a physical stand-up strength for the semiconductor device. In one embodiment, the second metal layers subsequently formed in the first region I can include ISO (isolated, as opposed to “dense”) copper line structures, compared with dense copper line structures formed in the second region II.

Still referring toFIG. 2, interlayer dielectric layer203can be formed on the top surface of substrate200(e.g., in Step1104). Optionally, protective layer204can be formed on surface of interlayer dielectric layer203.

Interlayer dielectric layer203can be made of a material including silicon dioxide, a low-k dielectric material (e.g., having a dielectric constant k less than about 3.9), or an ultra-low-k dielectric material (e.g., having a dielectric constant k less than about 2.5). In various embodiments, use of a low-k or ultra-low k dielectric material for the Interlayer dielectric layer203can facilitate to reduce dielectric constant of the semiconductor device and to improve the RC delay effect along with the operating speed of the semiconductor device.

Noted that, to prevent damage to interlayer dielectric layer203during subsequent removal of oxide layer formed by oxidation of a polymer layer, a material can be selected for interlayer dielectric layer203having an etching selectivity over the oxide layer. When the oxide layer is etched, no damages to interlayer dielectric layer203can occur during the etching process.

In one embodiment, etch stop layer202can be optionally formed between substrate200and interlayer dielectric layer203. Etch stop layer202can be used to protect first metal layers201from being damaged by subsequent manufacturing processes. Etch stop layer202can be used as a barrier layer to prevent metal ions from being diffused from first metal layers201, e.g., into interlayer dielectric layer203.

In one embodiment, etch stop layer202can be formed by a chemical vapor deposition. Etch stop layer202can be made of SiCN. Etching stop layer202can have a thickness ranging from about 50 angstroms to about 150 angstroms. In various embodiments, interlayer dielectric layer203can be formed directly on the top surface of substrate200without forming the etch stop layer202.

Protective layer204formed on the top surface of interlayer dielectric layer203can be used as a buffer layer between interlayer dielectric layer203and subsequently formed mask layer to protect interlayer dielectric layer203. For example, protective layer204can be used to protect interlayer dielectric layer203in the first region I in subsequent manufacturing processes.

In one embodiment, protective layer204is a silicon layer. Protective layer204can have a thickness ranging from about 50 angstroms to about 200 angstroms. In another embodiment, protective layer204can be made of tetraethoxysilane (TEOS: Si(OC2H5)4). In some embodiments, protective layer204may not be formed on interlayer dielectric layer203.

Referring toFIG. 3, protective layer204and a thickness portion of interlayer dielectric layer203in both the first and second regions can be removed to expose a remaining portion of interlayer dielectric layer203.

As shown inFIG. 3, the remaining portion of interlayer dielectric layer203can include a trench207in the first region II, and interlayer dielectric layer203in the second region II can have a top surface coplanar with a bottom of trench207in the first region I.

To form interlayer dielectric layer203, a patterned photoresist layer can be formed on surface of protective layer204as shown inFIG. 2and can be used as an etch mask to etch protective layer204and interlayer dielectric layer203to expose the remaining portion of interlayer dielectric layer203in the first and second regions. In one embodiment, a dry etching process can be used for the etching process.

The remaining portion of interlayer dielectric layer203can have a thickness used to determine a height of through-holes to be formed through the remaining portion of interlayer dielectric layer203. For example, the removed thickness portion of interlayer dielectric layer203in the second region II can provide a thickness used as a height of through-holes to be formed. In various embodiments, the thickness of the removed thickness portion of interlayer dielectric layer203can be determined according to specific application.

Referring toFIG. 4, the remaining portion of interlayer dielectric layer203can be etched to form through-holes205through interlayer dielectric layer203to expose surface portions of etch stop layer202(e.g., in Step1106).

Through-holes205can be formed, e.g., by forming an initial mask layer (not shown) on an entire surface of the semiconductor device shown inFIG. 3, i.e., on surface of both the first region I and the second region II. A patterned photoresist layer (not shown) can then be formed on the initial mask layer. The patterned photoresist layer is patterned corresponding to through-holes to be formed in the remaining portion of interlayer dielectric layer203. The patterned photoresist layer can be used as an etch mask to pattern and etch the initial mask layer to form a patterned initial mask layer (not shown). The patterned initial mask layer has openings corresponding to through-holes to be formed subsequently. The patterned photoresist layer can then be removed from the patterned initial mask layer, which can then be used as an etch mask to etch the remaining portion of interlayer dielectric layer203to form through-holes205in the first and second regions.

Note that although one through-hole205is formed in the first region I and three through-holes205are formed in the second region II for illustration purposes, any number of three through-holes, more or less than three, can be encompassed in the present disclosure without limitations. In one embodiment, a dry etching process can be used for forming through-holes205including, e.g., a plasma etching process.

Through-holes205can be formed in a position and having a width such that, when subsequently removing etch stop layer202at the bottom of through-holes205, surfaces of first metal layers201can be exposed for electrical connections. In one embodiment, each through-hole205can be positioned in line with a corresponding first metal layer201.

Referring toFIG. 5, polymer layer206is formed to fill through-holes205and to cover surface of the remaining portions of protective layer204and interlayer dielectric layer203(e.g., as shown inFIG. 4) in the first and second regions (e.g., in Step1108).

Polymer layer206formed in the first region I and the second region II can be coplanar with one another. For example, more amount of polymer layer can be formed in the second region II than in the first region I. In one embodiment, polymer layer206can be formed, e.g., by a spin coating process.

Polymer layer206can have different dissolving characteristics in response to an exposure, e.g., from a photolithographic tool. For example, polymer layer206placed in an exposed area may be dissolved, while polymer layer206placed in a non-exposed area may not be dissolved; or vice versa.

In addition, polymer layer206can be selected that can be oxidized to form an oxide layer by an annealing process. In one embodiment, polymer layer206can be made of a material of hydrogen silsesquioxane (HSQ: H8Si8O12).

In one embodiment, when selecting HSQ for forming polymer layer206, HSQ can provide desired advantages. For example, HSQ has photoresist features. When exposed to e-beams or extreme ultraviolet (EUV) radiation, HSQ material in the exposed area can undergo cross-linking reactions. After a developing process, cross-linked HSQ material in the exposed areas can remain intact, while HSQ material in the non-exposed area can be dissolved in the developing process. In other words, HSQ material can have a negative photoresist characteristic.

Subsequently, vias can be formed by exposure and developing polymer layer206, without using an etching process. Manufacturing process can thus be simplified. In addition, etching errors (deviations) can be avoided to increase accuracy in positioning the vias and thus to improve accuracy in positioning air gaps. Further, after a subsequent annealing process, HSQ material can be converted into a silicon oxide material which can be easily removed to allow a simple process to form air gaps.

Referring toFIG. 6, polymer layer206can be exposed and then developed to form vias in the first and second regions (e.g., in Step1110). As such, each via includes an upper via207and a lower via205. Upper via207is on lower via205and has a width greater than lower via205. The lower via205can be the same as the through-hole205inFIG. 4after removal of polymer layers in the through-hole205.

The vias can be formed, for example, by first exposing polymer layer206to an e-beam or EUV radiation, to define an exposed area and a non-exposed area. Polymer layer in the exposed area can be cross-linked, which may not be dissolved by a developing process. In contrast, polymer layer in the non-exposed area may not be cross-linked and may then be dissolved by the developing process. After the developing process, vias can be formed.

As such, vias each including the upper via207in the polymer layer206and the lower via205in the interlayer dielectric layer203as shown inFIG. 6, can be formed by exposure and developing processes, without using an etching process to polymer layer206. Accuracy in forming vias can then be improved. Because subsequently-formed air gaps are formed adjacent to vias, air gaps can be formed with precise positioning.

Further, air gaps are formed by subsequent removal of polymer layer206remained in the second region II, (that is, a width of the second region II of the remaining polymer layer206is a width of air gaps to be formed), shapes, dimensions, and position of air gaps can be controlled by controlling the exposure process of polymer layer206. For example, the width of remaining polymer layer206in the second region II may be adjusted by adjusting width of the exposed area and the non-exposed area. When increasing (or decreasing) the width of the non-exposed areas of polymer layer206in the second region II, air gaps with increased (or decreased) feature size can be controlled and obtained.

By forming vias in polymer layer206, etching process and etching related errors can be avoided. This is different than a typical via-forming process, where patterns are transferred by a photolithography process to a mask layer to form a patterned mask layer, which is then used as an etch mask to form vias by an etching process. Such etching process may generate etching related errors and vias formed thereby (and thus air gaps) may not have desired, accurate positions/dimensions.

Polymers are often considered as soft matter. After subsequent formation of a second metal layer (e.g., layer209inFIG. 9), a chemical mechanical polishing (CMP) process may be applied to the second metal layer. When the second metal layer is disposed on soft surface of the polymer layer206, the CMP process may cause deformation of polymer layer206. Reliability and electrical properties of the resultant semiconductor device can be adversely affected.

To avoid the above problems, optionally, oxide layer208can be formed from remaining polymer layer206by an annealing process, after vias are formed. Compared with polymer layer206, oxide layer208can provide improved stability and desired hardness to prevent occurrence of deformation. Reliability of the semiconductor device during a subsequent CMP process can be improved.

The annealing process can break and/or recombine covalent bond of the polymer material of polymer layer206to oxide layer208. In one embodiment, the oxide layer208includes a silicon oxide material.

Note that removal process of polymeric materials (e.g., HSQ) is complex and often leaves residues, while removal of a non-polymeric inorganic material (e.g., silicon oxide) can be relatively simpler. In addition, etching selectivity ratio between a silicon oxide layer and a dielectric material layer is sufficiently high. This can allow a short-time removal of the oxide layer208without damaging interlayer dielectric layer203and the second metal layer (due to excessive etching). Electrical properties of the resultant semiconductor device can be improved.

In various embodiments, the annealing process can be a rapid thermal annealing (RTA), for example, at an annealing temperature of about 450° C. to about 800° C. for about 0.01 milliseconds to about 10 milliseconds. In other embodiments, the annealing process may be omitted after forming the vias.

Referring toFIG. 8, the exposed portions of etch stop layer202is removed at the bottom of the via (in particular, the lower via205) to expose at least a surface portion of first metal layer201. The exposed first metal layers201can provide electrical connection with subsequently formed second metal layer. In one embodiment, etch stop layer202can be etched, e.g., by a dry etching process to remove the exposed portions thereof.

Referring toFIG. 9, vias are filled with metal material(s) to form second metal layers209(e.g., in Step1112). Second metal layer209and the first metal layer201are electrically connected.

Second metal layer209can be formed by, e.g., first forming a metal film to fill the vias and to cover a surface of protective layer204in the first region I and oxide layer208in the second region II. A CMP process can be performed to remove the metal film in the first and second regions and to expose protective layer204in the first region I. For example, the CMP process can remove the metal film and a portion of oxide layer208in the second region II that are above the exposed protective layer204, e.g., to form a flat or coplanar top surface for the semiconductor device as shown inFIG. 9. Second metal layers209are then formed in the vias in the second region II. As oxide layer208can provide sufficient hardness, oxide layer208can maintain intact during the CMP process.

Optionally, the CMP process can be further performed to remove the entire protective layer204and to provide a coplanar surface for second metal layers209, interlayer dielectric layer203, and oxide layer208.

In various embodiments, second metal layer209can have a single layer structure or a multilayer structure. A single-layer structure of second metal layer209can include a bulk metal layer filled in the vias.

Optionally, a multilayer structure of second metal layer209can include a metal barrier layer (not shown) formed on interior surfaces of vias (including upper via207and lower via205) and on the exposed first metal layer201at bottom of the vias. The multilayer structure of second metal layer209can further include a bulk metal layer formed on the metal barrier layer to completely fill the vias.

In an example when the multilayer structure is formed for second metal layers209, the metal barrier layer can be used to prevent metal ions diffused from second metal layer209into interlayer dielectric layer203to improve performance of interconnect structure. In addition, the metal barrier layer can provide an interface for a desired adhesion between the metal barrier layer and second metal layer209.

The metal barrier layer can be made of a material including, e.g., Ti, Ta, W, TiN, TaN, TiSiN, TaSiN, WN, WC, or a combination thereof. The metal barrier layer can be a single layer structure or a multilayer structure. The metal barrier layer can be formed by a chemical vapor deposition, a physical vapor deposition, and/or an atomic layer deposition.

The bulk metal layer of second metal layer can be made of a material including, e.g., W, Cu, Al, Ag, Pt, and/or any alloy thereof. The bulk metal layer can be a monolayer structure or a multilayer structure.

In one embodiment, the metal barrier layer can include a metal material Ta. The metal barrier layer can have a thickness ranging from about 10 Å to about 500 Å. The metal barrier layer can be formed by a physical vapor deposition. The bulk metal layer for second metal layer209can include Cu and can be formed by an electro-plating process.

Referring toFIG. 10, oxide layer208between adjacent second metal layers209is removed, e.g., by a wet etching process, to form air gaps210(e.g., in Step1114).

During the wet etching process, an etch rate for removing oxide layer208can be greater than an etch rate for removing interlayer dielectric layer203. In an exemplary embodiment, the wet etching process can use an etching liquid of hydrofluoric (HF) acid solution having a volume ratio between hydrofluoric acid and deionized water of about 1:700 to about 1:300.

In an exemplary embodiment, a desired high etch selectivity ratio can be provide for the wet etching process, where interlayer dielectric layer203is a low-k or ultra-low-k dielectric material, and oxide layer208is silicon oxide. As such, when wet etching oxide layer208, the wet etching process may have no adverse effect on interlayer dielectric layer203. In addition, second metal layers209are made of metal material(s), which can also have high etch selectivity ratio over oxide layer208. The wet etching process may not affect second metal layers209.

Accordingly, the wet etching can substantially remove all oxide layer208between adjacent second metal layers209to form air gaps210between adjacent second metal layers209, in particular, between upper metal layers. Each air gap210can have a width substantially same as the width between upper vias207formed as shown inFIG. 8. Compared with conventional air gaps, feature sizes of air gap210can be increased significantly. The dielectric constant k value of the semiconductor device and parasitic capacitance can be effectively reduced. RC delay effect, along with operating speed of the semiconductor device and electrical properties of the semiconductor device can be improved.

In this manner, each second metal layer209can have a lower metal layer in the interlayer dielectric layer203and an upper metal layer protruded over and disposed on a top surface of the interlayer dielectric layer203. The lower metal layer of each second metal layer is electrically connected to one of first metal layers201. Air gaps210are formed between adjacent second metal layers209.

In other embodiments, after forming the vias and before forming the second metal layer, the annealing of the polymer layer may be omitted. In this case, after forming the second metal layer, a wet etching process can be used to remove polymer layer between adjacent second metal layers to form air gaps having a width between adjacent second metal layers. The air gaps can also have an increased feature size.