Nonvolatile memory device having read circuits for performing Read-While-Write (RWW) operation and Read-Modify-Write (RMW) operation

A nonvolatile memory device includes a memory array having multiple nonvolatile memory cells, a first read circuit and a second read circuit. The first read circuit is configured to read first data from the memory array during a first read operation and to provide one or more protection signals indicating a victim period during the first read operation. The second read circuit is configured to read second data from the memory array during a second read operation and to provide one or more check signals indicating an aggressor period during the second read operation.

CROSS-REFERENCE TO RELATED APPLICATION

A claim for priority under 35 U.S.C. §119 is made to Korean Patent Application No. 10-2013-0023007, filed on Mar. 4, 2013, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.

BACKGROUND

Nonvolatile memories using resistance materials include phase-change random access memories (PRAMs), resistive RAMs (RRAMs), and magnetic RAMs (MRAMs). While dynamic RAMs (DRAMs) or flash memories store data using charges, nonvolatile memories using resistance materials store data using a state change of a phase-change material, such as chalcogenide alloy (in the case of PRAMs), a resistance change of a variable resistance material (in the case of RRAMs), or a resistance change of a magnetic tunnel junction (MTJ) thin film according to a magnetization state of a ferromagnetic material (in the case of MRAMs).

For example, in a phase-change memory device, a phase-change material is changed into a crystalline state or an amorphous state while being heated and then cooled. The phase-change material typically exhibits a relatively low resistance in the crystalline state, which is typically defined as “set” data, and a relatively high resistance in the amorphous state, which is typically defined as “reset” data.

SUMMARY

Embodiments of the inventive concept relate to nonvolatile memory devices using variable resistive elements. Embodiments of the inventive concept provide a nonvolatile memory device having improved reliability of a read operation. The above and other objects will be described in or be apparent from the following description.

According to an aspect of the inventive concept, there is provided a nonvolatile memory device including a memory array having multiple nonvolatile memory cells, a first read circuit and a second read circuit. The first read circuit is configured to read first data from the memory array during a first read operation and to provide one or more protection signals indicating a victim period during the first read operation. The second read circuit is configured to read second data from the memory array during a second read operation and to provide one or more check signals indicating an aggressor period during the second read operation.

According to another aspect of the inventive concept, there is provided a nonvolatile memory device including a memory array having multiple nonvolatile memory cells, a first read circuit and a second read circuit. The first read circuit is configured to read first data from the memory array to perform a read while write (RWW) operation. The second read circuit is configured to read second data from the memory array to perform a read modification write (RMW) operation. The second read circuit stops the RMW operation while the first read circuit performs one of a bitline precharge of the RWW operation, a sense amplifier operation start, and a data dump.

According to another aspect of the inventive concept, there is a nonvolatile memory including first and second read circuits. The first read circuit is configured to read first data from memory cells having variable resistive materials during a first read operation and to generate at least one protection signal indicating a victim period during the first read operation. The first read circuit includes a first precharge circuit for precharging a sensing node electrically connected to a memory cell to a predetermined level during a bitline precharge period, a first sense amplifier for comparing levels of the sensing node and a set reference voltage, the first sense amplifier being enabled by a first sense amplifier control signal, and a first multiplexer for outputting an output signal of the first sense amplifier as data, the first multiplexer being enabled by a first multiplexer control signal. The victim period includes at least one of a portion of the bitline precharge period, activation of the sense amplifier control signal, and a portion of a data dump period activated in response to the first multiplexer control signal. The second read circuit is configured to read second data from the memory cells having variable resistive materials during a second read operation and to generate at least one check signal indicating an aggressor period during the second read operation. The second read circuit includes a second sense amplifier for comparing levels of a sensing node and a set reference voltage, the second sense amplifier being enabled by a second sense amplifier control signal, and a second multiplexer for outputting an output signal of the second sense amplifier as data, the second multiplexer being enabled by a second multiplexer control signal. The aggressor period includes at least one of first noise generated at an operation start time of the second sense amplifier, second noise generated at an operation start time of the second multiplexer, and third noise generated during a data dump period activated in response to the second multiplexer control signal.

DETAILED DESCRIPTION OF EMBODIMENTS

Exemplary embodiments of the inventive concept will hereinafter be described in detail, using a phase-change random access memory (PRAM) device as an example. However, embodiments of the inventive concept are not restricted to PRAM devices. That is, embodiments may also be applied to other nonvolatile memory devices using resistance materials including, for example, a resistive random access memory (RRAM) device, a ferroelectric random access memory (FRAM) device, and the like.

FIG. 1is a block diagram of a nonvolatile memory device, according to embodiments of the inventive concept.FIG. 2is a circuit diagram illustrating a nonvolatile memory cell in the memory array shown inFIG. 1, according to an embodiment of the inventive concept.

Referring toFIG. 1, nonvolatile memory device1includes a memory array190, a first read circuit210_1and a second read circuit210_2.

The memory array190may include multiple nonvolatile memory cells (e.g., MCs inFIG. 2). The nonvolatile MCs may write or read data using a resistance material. Each of the nonvolatile MCs includes a variable resistive circuit (RC), including a phase change material having different resistance values according to the data stored, and an access circuit (AC) controlling current flowing into the AC. The ACs may include diodes, transistors, and the like, coupled to the RCs in series. In the embodiment shown inFIG. 2, a diode is used as the AC. GeSbTe, which is a combination of germanium (Ge), antimony (Sb) and tellurium (Te), may be used as the phase change material, although other phase change material may be incorporated. For example, the phase change material may be a combination of two elements, such as GaSb, InSb, InSe, Sb2Te3or GeTe, a combination of three elements, such as GeSbTe, GaSeTe, InSbTe, SnSb2Te4or InSbGe, or a combination of four elements such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe) or Te81Ge15Sb2S2.

The first read circuit210_1performs a first read operation on first data DATA1from the memory array190. For example, the first read circuit210_1may perform a read while write (RWW) operation. The first read circuit210_1is used in a normal read operation.

In the RWW operation, a read operation is performed while a write operation is performed. For example, a write operation may be performed in a region and a read operation may be performed in another region at substantially the same time. Hereinafter, a read command input during the RWW operation is referred to as an “RWW read command” and a read operation performed during the RWW operation is referred to as “RWW read.” The RWW read command is the same as a normal read command except that it is input during a write operation.

The second read circuit210_2performs a second read operation on second data DATA2from the memory array190. For example, the second read circuit210_2may read the second data DATA2during a read modification write (RMW) operation.

In the RMW operation, the data stored in the memory array190is read, the read data and data to be written are compared with each other, and only bits of the data to be written that are different from bits of the read data are written. That is, in an RMW operation, a read operation is performed prior to a write operation. Hereinafter, a read command input during the RMW operation is referred to as an “RMW read command” and a read operation performed during the RMW operation is referred to as “RMW read.”

Meanwhile, in the nonvolatile memory device1according to various embodiments, the first read circuit210_1generates one or more protection signals PROTRGN1and PROTRGN2corresponding to a “victim period” during the first read operation. InFIG. 1, two protection signals PROTRGN1and PROTRGN2are shown for purposes of explanation, although various aspects of the inventive concept are not limited thereto.

The “victim period” refers to a period vulnerable to changes in the bias (e.g., voltage) during a read operation. As described below with reference toFIG. 4, the read operation may be performed in order of bitline discharge, bitline precharge, develop, data sensing by a sense amplifier, and data dump to a peripheral region, although aspects of the inventive concept are not limited thereto.

In the read operation, the victim period may include, for example, at least a portion of a bitline precharge period of the first read circuit210_1, a period including an operation start time of the sense amplifier of the first read circuit210_1, and a data dump period of the first read circuit210_1. The victim period may be determined through simulation and/or experimentation, and may vary according to specific requirements and/or configurations.

The second read circuit210_2generates one or more check signals corresponding to an “aggressor period” during the second read operation. The “aggressor period” refers to a period during which considerable changes in the bias (e.g., voltage) may be caused during a read operation. In other words, the aggressor period is a period in which noise may be generated. For example, a current peak may be generated in the aggressor period.

The aggressor period in the read operation may include, for example, an operation start time of the sense amplifier of the second read circuit210_2, an operation start time of the MUX of the second read circuit210_2, and a data dump period of the second read circuit210_2. The aggressor period may be determined through simulation and/or experimentation and may vary according to specific requirements and/or configurations.

The second read circuit210_2checks whether the protection signals PROTRGN1and PROTRGN2supplied from the first read circuit210_1overlap with the one or more check signals. If the protection signals PROTRGN1and PROTRGN2do overlap with the one or more check signals, the second read circuit210_2stops the second read operation. If it is determined using the one or more check signals that the protection signals PROTRGN1and PROTRGN2are inactivated (or if the protection signals PROTRGN1and PROTRGN2do not overlap with the one or more check signals), the second read circuit210_2resumes the second read operation. Here, it will be understood that when the protection signals PROTRGN1and PROTRGN2overlap with the one or more check signals, the first read operation of the first read circuit210_1may be in a victim period and the second read operation of the second read circuit210_2may be in an aggressor period. That is, the first read operation may be adversely affected by the second read operation. Therefore, the second read operation is stopped, thereby ensuring reliability of the first read operation.

That is, a RMW read (i.e., a read performed in the second read circuit210_2) may be controlled according to the progress of the RWW read (i.e., a read performed in the first read circuit210_1). A read operation is controlled so as not to simultaneously perform two types of reads in a period in which reliability of a read operation is difficult to attain.

In the above-described embodiment, the RMW read is controlled according to the progress of the RWW read, although aspects of the inventive concept are not limited thereto. That is, the RWW read may be controlled according to the progress of the RMW read. In particular, each of the RWW read and the RMW read has an aggressor period and a victim period. Therefore, it is optional to first perform the RWW read to then control the progress the RMW read, or to first perform the RMW read to then control the progress the RWW read. The order may be chosen based on various factors, such as specifications, timing, and so on.

Hereinafter, an exemplary first read circuit210_1(and second read circuit210_2) is described with reference toFIG. 3, and timing diagram corresponding to a method of operating the first read circuit210_1(and the second read circuit210_2), including the victim period and the aggressor period, are described with reference toFIG. 4. Also, a process of matching protection signals to check signals are described with reference toFIGS. 5 to 9, a process of choosing the protection signals is described with reference toFIG. 10, and an exemplary circuit for matching the protection signals to the check signals is described with reference toFIG. 11.

FIG. 3is a circuit diagram of an exemplary first read circuit shown inFIG. 1, according to an embodiment. The depicted first read circuit is provided for purposes of illustration, and aspects of the inventive concept are not limited thereto.

Referring toFIG. 3, the first read circuit210_1includes a first discharge unit211, a first precharge unit212, a first compensation unit214, a first clamping unit216, a first sense amplifier (AMP)218, and a first multiplexer (MUX)219.

The first discharge unit211discharges a bit line (i.e., a sensing node) electrically connected to the nonvolatile MC. The first discharge unit211may include an NMOS transistor, for example, controlled by a discharge control signal PLBLDIS.

The first precharge unit212precharges a sensing node to a predetermined level, for example, a power supply voltage VDD or a step-up voltage VPPSA, during a precharge period, preceded by a develop operation. The first precharge unit212may include a PMOS transistor with a source connected to the power supply voltage VDD or the step-up voltage VPPSA, for example, and controlled by a precharge control signal PCHG.

In order to compensate for a reduction in the level of a sensing node generated by penetration current Icell flowing through the selected nonvolatile memory cell (MC ofFIG. 2), the first compensation unit214supplies a compensation current to the sensing node. More particularly, when a nonvolatile memory cell is in a SET state, the resistance of the phase change material may be small, so the amount of penetration current Icell is large. When a nonvolatile memory cell is in a RESET state, the resistance of the phase change material may be large, so the amount of penetration current Icell is small. The amount of the compensation current supplied from the first compensation unit214compensates for the penetration current Icell in the RESET state. In this case, a level of the sensing node in the SET state is reduced while a level of the sensing node in the RESET state is maintained constant. Thus, the difference between the level of sensing node in the RESET state and the level of sensing node in the SET state may be relatively large, making it easier to distinguish between the SET state and the RESET state. By doing so, a sensing margin may be increased. The first compensation unit214may include a PMOS transistor controlled by a compensation control signal PBIAS and a PMOS transistor controlled by a voltage signal VBIAS, for example.

The first clamping unit216clamps a level of the bit line BL coupled to the selected nonvolatile memory cell within a proper range to read. In detail, the first clamping unit216clamps the level of bit line BL to a predetermined level lower than a critical voltage of the phase change material. This is because, if the level of the bit line BL is equal to or higher than the critical voltage, the phase of the phase change material of the selected phase change memory cell may be changed. The first clamping unit216may include an NMOS transistor, for example, controlled by a clamping control signal VCMP.

The first sense AMP218compares a level of the sensing node and a set reference voltage Vref, and outputs results of the comparison to an output terminal. The first sense AMP218may be a current sense amplifier or a voltage sense amplifier. The first sense AMP218may be enabled by a sense amplifier control signal PSA.

The first MUX219outputs an output signal of the first sense AMP218as data. The first MUX219may be enabled by a MUX control signal PMUX.

The second read circuit210_2(not shown) may have substantially the same circuit configuration as that of the first read circuit210_1, discussed above. That is, the second read circuit210_2may include a second discharge unit, a second precharge unit, a second compensation unit, a second clamping unit, a second sense AMP, and a second MUX.

FIG. 4is a timing diagram showing an exemplary method of operating the first read circuit, according to an embodiment of the inventive concept.

Referring toFIG. 4, a core read start signal RSARD is an internal command to start a core read operation. The discharge control signal PLBLDIS is activated in response to the core read start signal RSARD (S501). As described above, the discharge control signal PLBLDIS controls the first discharge unit211of the first read circuit (210_1ofFIG. 3). A word line select signal PWLX is activated in response to the discharge control signal PLBLDIS (S502). The precharge control signal PCHG is activated in response to the word line select signal PWLX (S503). As described above, the precharge control signal PCHG controls the first precharge unit212of the first read circuit (210_1ofFIG. 3).

The compensation control signal PBIAS is activated in response to the precharge control signal PCHG (S504). As described above, the compensation control signal PBIAS controls the first compensation unit214of the first read circuit (210_1ofFIG. 3).

The sense AMP control signal PSA is activated in response to the compensation control signal PBIAS (S505). As described above, the sense AMP control signal PSA controls the first sense AMP218of the first read circuit (210_1ofFIG. 3).

The MUX control signal PMUX is activated in response to the sense AMP control signal PSA (S506). As described above, the MUX control signal PMUX controls the first MUX219of the first read circuit (210_1ofFIG. 3).

A data dump signal DATADUMP is activated in response to the MUX control signal PMUX (S507). The data dump signal DATADUMP is a signal for transmitting data to a peripheral region.

As described above, an aggressor period during a read operation may be a period in which noise is generated. First noise301is generated at the operation start time of a sense AMP (e.g., at a rising edge of the sense AMP control signal PSA), second noise302is generated at the operation start time of a MUX (e.g., at a rising edge of the MUX control signal PMUX), and third noise303is generated during the data dump period (e.g., an active period of the data dump signal DATADUMP). One or more check signals (CHK1, CHK2and CHK3, described below) may be generated in such noise generated periods.

Meanwhile, the victim period during a read operation may include, for example, period P1including at least a portion of a bitline precharge period (e.g., a portion of an active period of the precharge control signal PCHG), period P2including sense AMP operation start time (e.g., a rising edge of the sense AMP control signal PSA), and period P3including at least a portion of a data dump period (e.g., an active period of the data dump signal DATADUMP).

In addition, to accommodate convenient control, the victim period may be set as period Pa, including period P1, period P2and period P3. Alternatively, the victim period may be set as period Pb, including period P1and period P2. Alternatively, the victim period may be set as period Pc, including period P2and period P3. One or more protection signals (PROTRGN1and PROTRGN2, described below) may be generated to indicate the victim periods defined as above.

FIGS. 5 to 9are conceptual diagrams for explaining methods for matching protection signals to check signals.

Referring toFIG. 5, as described above, it is assumed that a first read operation has three victim periods P1, P2and P3corresponding to the protection signals. Also, a second read operation has an aggressor period (noise generating period), where three check signals CHK1, CHK2and CHK3correspond to the aggressor period.

It is checked whether the check signal CHK1is overlapped (or matched) with all of the victim periods P1, P2and P3(411,412and413). It is checked whether the check signal CHK2is overlapped (or matched) with all of the victim periods P1, P2and P3(421,422and423). It is checked whether the check signal CHK3is overlapped (or matched) with all of the victim periods P1, P2and P3(431,432and433). When any one check signal (e.g., CHK1) of the check signals is overlapped with the victim periods P1, P2and P3, the second read operation may be stopped until the first read operation is completed.

Referring toFIG. 6, it is checked whether the check signal CHK1is overlapped with one victim period P1(411), whether the check signal CHK2is overlapped with one victim period P2(422) and whether the check signal CHK3is overlapped with one victim period P3(433). When any one check signal (e.g., CHK1) of the check signals is overlapped with a corresponding one of the victim periods P1, P2and P3, the second read operation may be stopped until the first read operation is completed.

Referring toFIG. 7, the first read operation has a victim period Pa including all of the victim periods P1, P2and P3. To accommodate convenient control, the victim period may be set as the period Pa including period P1, period P2and period P3. It is checked whether the check signals CHK1, CHK2and CHK3are overlapped (or matched) with the victim period Pa (415,425and435).

Referring toFIG. 8, the first read operation has a victim period Pb including victim periods P1and P2. To accommodate convenient control, the victim period may be set as the period Pb including period P1and period P2. It is checked whether the check signals CHK1and CHK2are overlapped (or matched) with the victim periods Pb and P3(415,416,425and426). That is, it is checked whether the check signal CHK1is overlapped with the victim periods Pb and P3(415and416), whether the check signal CHK2is overlapped with the victim periods Pb and P3(425and426) and/or whether the check signal CHK3is overlapped with the victim periods P3and Pb (435and436).

Referring toFIG. 9, the first read operation has a victim period Pc including victim periods P2and P3. To accommodate convenient control, the victim period may be set as the period Pc including period P2and period P3. It is checked whether the check signals CHK2and CHK3are overlapped (or matched) with the victim periods P1and Pc (427,428,437and438). That is, it is checked whether the check signal CHK1is overlapped with the victim periods P1and Pc (417and418), whether the check signal CHK2is overlapped with the victim periods Pc and P1(427and428) and/or whether the check signal CHK3is overlapped with the victim periods Pc and P3(437and438).

FIG. 10is a timing diagram illustrating an exemplary process of choosing protection signals, according to an embodiment of the inventive concept.

Referring toFIG. 10, a first read operation may have, for example, a victim period Pa including all of victim periods P1, P2and P3. A protection signal PROTRGN0may correspond to the victim period Pa. However, in the nonvolatile memory device1according an embodiment of the inventive concept, a first protection signal PROTRGN1may be used in consideration of tXing, which represents time required to address with metastability problems. Therefore, the first protection signal PROTRGN1is activated earlier than PROTRGN0by the time tXing.

In addition, in the nonvolatile memory device1, according to an embodiment of the inventive concept, a second protection signal PROTRGN2may be used in consideration of tAGG_ECCDEC, which represents time required for operating an error correcting code (ECC) decoder of a second read circuit. The time tAGG_ECCDEC may be substantially the same as a data dump period, discussed above.

As described above with reference toFIG. 4, the data dump period is longer than periods of the other noise (e.g., the operation start time of the sense AMP or the operation start time of the MUX). Therefore, the second protection signal PROTRGN2is set longer than the first protection signal PROTRGN1by the data dump period. In such a manner, aggression, which may occur around the start portion of the victim period Pa due to a data dump, can be prevented.

FIG. 11is a circuit diagram illustrating generating and matching protection signals and check signals, according to an embodiment of the inventive concept.

Referring toFIG. 11, a protection signal generator210ais positioned in a first read circuit210_1, and a check signal generator210bis positioned in a second read circuit210_2.

The protection signal generator210aincludes multiple delay units611,612,613and614, a first SR latch651, and a second SR latch652. A first pulse RSAPLS formed based on an RWW read command is input to the protection signal generator210a, and a first termination signal RSA_DONE indicating that the RWW read is completed is output from the protection signal generator210a.

The first SR latch651receives a pulse DP1delayed by two delay units611and612and the first termination signal RSA_DONE, and generates a first protection signal PROTRGN1. In a state in which the first termination signal RSA_DONE is at a low level, when the delayed pulse DP1is input, the first protection signal PROTRGN1is activated (e.g., high level). When the first termination signal RSA_DONE goes from the low level to a high level, the first protection signal PROTRGN1is inactivated (e.g., low level).

The second SR latch652receives a pulse DP2delayed by one delay unit611and the first termination signal RSA_DONE, and generates a second protection signal PROTRGN2. As described above with reference toFIG. 10, the second protection signal PROTRGN2is activated longer than the first protection signal PROTRGN1by an additional time (e.g., the data dump period).

The check signal generator210bincludes multiple delay units621,622,623and624, multiple delay units631,632and633, multiple flipflops641,642and643, multiple operation units661,662and663. A second pulse WSAPL formed based on the RMW read command is input to the check signal generator210band a second termination signal WSA_DONE indicating that the RMW read is completed is output from the check signal generator210b.

The delay unit621delays the second pulse WSAPLS to generate the first check signal CHK1. The first check signal CHK1may correspond to a second AMP operation start time of the second read circuit210_2. The flipflop641transmits the first protection signal PROTRGN1in response to the first check signal CHK1.

The operation unit661performs a first checking process to determine whether the first check signal CHK1overlaps with the first protection signal PROTRGN1. In the depicted embodiment, the operation unit661includes an inverter, two AND gates, and an OR gate, although other configurations may be incorporated.

A signal (tXing delayed by the delay unit631), the first protection signal PROTRGN1and the first termination signal RSA_DONE are input to the operation unit661. When the first protection signal PROTRGN1is inactivated (e.g., low level), an output signal C1of the operation unit661is activated (e.g., high level). Conversely, when the first protection signal PROTRGN1is activated (e.g., high level), the output signal C1of the operation unit661is maintained in an inactivated state (e.g., low level). Meanwhile, when the first termination signal RSA_DONE in the activated state (e.g., high level) is input, the output signal C1is activated (e.g., high level).

If the output signal C1is activated, the sense AMP control signal PSA is activated using the output signal C1. That is, a data sensing operation of the second read operation may be performed. When the output signal C1is inactivated, the data sensing operation may not be performed.

Similarly, the delay unit622delays the output signal C1and generates a second check signal CHK2. The second check signal CHK2may correspond to a second MUX operation start time of the second read circuit210_2. The flipflop642transmits the first protection signal PROTRGN1in response to the second check signal CHK2.

The operation unit662performs a second checking process to determine whether the second check signal CHK2overlaps with the first protection signal PROTRGN1. In the depicted embodiment, the operation unit662includes an inverter, two AND gates, and an OR gate, although other configurations may be incorporated.

A signal (tXing delayed by the delay unit632), the first protection signal PROTRGN1and the first termination signal RSA_DONE are input to the operation unit662. When the first protection signal PROTRGN1is inactivated, an output signal C2of the operation unit662is activated. Conversely, when the first protection signal PROTRGN1is activated, the output signal C2of the operation unit662is maintained in an inactivated state. Meanwhile, when the first termination signal RSA_DONE in the activated state is input, the output signal C2is activated.

If the output signal C2is activated, the MUX control signal PMUX is activated using the output signal C2. In such a manner, the MUX of the second read operation may operate. When the output signal C2is inactivated, the MUX may not operate.

In summary, when the first check signal CHK1and the second check signal CHK2overlap with the first protection signal PROTRGN1, the second read circuit210_2stops the second read operation, and after the first read operation is completed, the second read operation may be resumed.

In addition, the delay unit623delays the output signal C2and generates the third check signal CHK3. The third check signal CHK3corresponds to a data dump period of the second read circuit210_2. The flipflop643transmits the second protection signal PROTRGN2in response to the third check signal CHK3.

The operation unit663performs a third checking process to determine whether the third check signal CHK3overlaps with the second protection signal PROTRGN2. The operation unit663includes an inverter, two AND gates, and an OR gate, although other configurations may be incorporated.

A signal (tXing delayed by the delay unit633), the second protection signal PROTRGN2and the first termination signal RSA_DONE are input to the operation unit663. When the second protection signal PROTRGN2is inactivated, an output signal C3of the operation unit663is activated. Conversely, when the second protection signal PROTRGN2is activated, the output signal C3of the operation unit663is maintained in an inactivated state. Meanwhile, when the first termination signal RSA_DONE in the activated state is input, the output signal C3is activated.

If the output signal C3is activated, the data dump signal DATADUMP is activated using the output signal C3. In such a manner, the data dump operation of the second read operation may occur. When the output signal C3is inactivated, the data dump operation does not occur.

In summary, when the third check signal CHK3overlaps with the second protection signal PROTRGN2, the second read circuit210_2stops the second read operation, and after the first read operation is completed, the second read operation may be resumed.

The delay unit624delays the output signal C3and generates the second termination signal WSA_DONE.

FIG. 12is a block diagram of a nonvolatile memory system, according to embodiments of the inventive concept.

Referring toFIG. 12, nonvolatile memory system1000includes a nonvolatile memory device1100and a controller1200. The nonvolatile memory device1100may be configured and driven in the same manner described above with reference toFIGS. 1 to 11. The controller1200is connected to a host and the nonvolatile memory device1100.

The controller1200is configured to access the nonvolatile memory device1100in response to requests from the host. For example, the controller1200may control read, write, erase, and background operations of the nonvolatile memory device1100. The controller1200provides interfacing between the nonvolatile memory device1100and the host. The controller1200may drive firmware for controlling the nonvolatile memory device1100.

For example, the controller1200may include well-known components, such as random access memory (RAM), a processing unit, a host interface, a memory interface, and the like. The RAM may be used as at least one of operating memory of the processing unit, cache memory between the nonvolatile memory device1100and the host, and buffer memory between the nonvolatile memory device1100and the host. The processing unit controls the overall operation of the controller1200.

The host interface includes a protocol for exchanging data and/or commands between the host and the controller1200. For example, the controller1200may be configured to communicate with an external device (host) through one of various interface protocols, such as universal serial bus (USB), multimedia card (MMC), peripheral component interconnection (PCI) protocol, PCI-express (PCI-E) protocol, advanced technology electronics (ATA) protocol, serial-ATA protocol, parallel-ATA protocol, small computer small interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, and integrated drive electronics (IDE) protocol. The memory interface interfaces with the nonvolatile memory device1100. Here, the memory interface may include, for example, a NAND interface or a NOR interface.

The memory system1000may further include an error correction block. The error correction block may be configured to detect and correct errors in data stored in the memory system1100using an error correction code (ECC). For example, the error correction block may be provided as a component of the controller1200. Alternatively or in addition, the error correction block may be provided as a component of the nonvolatile memory device1100.

The controller1200and the nonvolatile memory device1100may be integrated into one semiconductor device. For example, the controller1200and the nonvolatile memory device1100may be integrated into one semiconductor device to form a memory card. For example, the controller1200and the nonvolatile memory device1100may be integrated into one semiconductor device to form a Multi Media Card (MMC, RS-MMC, MMCmicro), a Secure Digital card (SD, miniSD, microSD), a Universal Flash Storage (UFS), a PC card (originally PCMCIA or PCMCIA card), a Compact Flash (CF) card, a Smart Media (SM) Card, a memory stick, and the like, but are not limited thereto.

As another example, the controller1200and the nonvolatile memory device1100may be integrated into one semiconductor device to form a Solid State Disk/Drive (SSD). The SSD includes a storage device configured to store data in a semiconductor memory. When the memory system1000is used as an SSD, the operating speed of the host connected to the memory system1000may be significantly improved.

As another example, the memory system1000may include or be incorporated in a computer, an ultra mobile personal computer (UMPC), a work station, a net-book, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game console, a navigation device, a black box, a digital camera, a 3-dimensional television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, digital video recorder, a digital video player, a device capable of transmitting/receiving information in wireless environments, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, RFID devices, or embedded systems, but is not limited thereto.

As an example, the nonvolatile memory device1100and/or the memory system1000may be packaged in a variety of ways. For example, the nonvolatile memory device1100and/or the memory system1000may be mounted in a package on package (PoP), a ball grid array (BGA) package, a chip scale package (CSP), a plastic leaded chip carrier (PLCC), a plastic dual in-line package (PDIP), a die in waffle pack, a die in wafer form, a chip-on-board (COB), a ceramic dual in-line package (CERDIP), a plastic metric quad flat pack (MQFP), a thin quad flatpack (TQFP), a small outline (SOIC), a shrink small outline package (SSOP), a thin small outline (TSOP), a thin quad flatpack (TQFP), a system in package (SIP), a multi-chip package (MCP), a wafer-level fabricated package (WFP) or a wafer-level processed stack package (WSP), but is not limited thereto.

FIG. 13is a block diagram illustrating an exemplary application of the memory system shown inFIG. 12, according to embodiments of the inventive concept.

Referring toFIG. 13, memory system2000includes nonvolatile memory2100and a controller2200. The nonvolatile memory2100includes multiple nonvolatile memory chips. The nonvolatile memory chips are divided into groups, where each group of the nonvolatile memory chips is configured to communicate with the controller2200through a common channel. For example, the nonvolatile memory chips may communicate with the controller2200through first to kth channels CH1to CHk. Each of the nonvolatile memory chips is configured in substantially the same manner as the nonvolatile memory100discussed above with reference toFIGS. 1 to 11.

While multiple nonvolatile memory chips (in a group) are exemplarily shown connected to one channel inFIG. 13, it is understood by one skilled in the art that the memory system2000may be modified to connect each nonvolatile memory chip to one channel.

FIG. 14is a block diagram illustrating a computing system, including the memory system shown inFIG. 13, according to embodiments of the inventive concept.

Referring toFIG. 14, computing system3000includes a central processing unit (CPU)3100, random access memory (RAM)3200, a user interface3300, a power supply3400, and the memory system2000.

The memory system2000may be electrically connected to the CPU3100, the RAM3200, the user interface3300and the power supply3400through a system bus3500. The data supplied through the user interface3300or processed by the CPU3100may be stored in the memory system2000.

InFIG. 14, the nonvolatile memories2100are connected to the system bus3500through the controller2200. However, in alternative configurations, the nonvolatile memories2100may be directly connected to the system bus3500.