Semiconductor device manufacturing method

This invention is directed to the reduction of voltage dependence and thus allows easy design of integrated semiconductor circuits. The device is equipped with a P− type resistance layer, in which a first voltage is applied to one end and a second voltage is applied to the other end and which is formed on the surface of an N-well region on the semiconductor substrate, a thin oxide film on the resistance layer, and a resistance bias electrode which includes the silicon layer formed on the thin oxide film. By adjusting the voltage applied to the resistance bias electrode, the voltage dependence of the resistance of the resistance layer is reduced.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

This invention relates to a semiconductor device and its manufacturing method, especially to a semiconductor device in which resistor elements are integrated on a semiconductor substrate.

2. Background of the Invention

Resistor elements have been used in a variety of semiconductor integrated circuits, including resistors for delay circuits, resistors for oscillator circuits, and ladder resistors for Analog-Digital converters.FIG. 11is a cross-sectional view of the structure of a prior art semiconductor device. On N− type semiconductor substrate50, field oxide films51are formed. P− type resistance layer52is formed on the surface of the N− type semiconductor substrate50between the field oxide films51. Also, on both sides of the P− type resistance layer52, P+ type electrode pad layers53and54are formed.

FIG. 12is shows a cross section of the semiconductor device ofFIG. 11in use. The voltage VL is applied to the electrode pad layer53, and the voltage VH is applied to the electrode pad layer54in the Figure. Hence, when the voltage of the N type semiconductor substrate50is 0V, it is supposed that VH<VL<0V. That is, forward bias of the P+ type electrode pad layers53and54and the N type semiconductor substrate50is prevented. Also, in terms of absolute value, voltage VH is greater than voltage VL. Therefore, electric current goes through the P− type resistance layer52according to the voltage difference (VH−VL).

When the resistance layer52is used as a resistor element in a semiconductor integrated circuit, it is desirable that there be no voltage dependence of the resistance value for the sake of circuit design. However, when voltage VH is applied to the P+ type electrode pad layer54, the depletion layer55between the N type semiconductor substrate50and the resistance layer52is expanded. Therefore, the P− type resistance layer52is narrowed down, causing the change in a resistance value, which depends on the voltage VH applied to the P+ type electrode pad layer54. Also, when the voltage VH rises further, a pinch-off state takes place near the P+ type electrode pad layer54, leading to saturation of the electric current.

SUMMARY OF THE INVENTION

This invention is directed to reducing voltage dependence as much as possible, which can simplify the design of semiconductor integrated circuits.

The semiconductor device of this invention has a resistance layer of a second conductivity type formed on the surface of the semiconductor substrate of a first conductivity type, where a first voltage is applied to one end of the device and a second voltage is applied to the other end, an oxide film formed on the resistance layer of the second conductivity type, and a resistance bias electrode layer comprising silicon layer on the oxide film. By adjusting the voltage applied to the resistance bias electrode layer, the voltage dependence of the resistance of the resistance layer of the second conductivity type can be reduced.

The method of manufacturing the semiconductor device of this invention includes forming an oxide film and a first silicon layer on the semiconductor device of the first conductivity type, selectively forming a oxidation resistance film on the first silicon layer, forming a field oxide film by thermal oxidation, removing the oxidation resistance film, forming a resistance layer of the second conductivity type on the surface of the semiconductor substrate by ion implantation of the impurity of the second conductivity type piercing through the first silicon layer and the oxide film, forming a second silicon layer covering the whole area, forming a resistance bias electrode layer on the resistance layer through the patterning of the first and second silicon layers, and forming a wiring layer for providing the resistance bias electrode layer with the predetermined voltage.

The manufacturing method of this invention allows for the reduction of manufacturing process steps, because the first silicon layer remains intact when the field oxide film is formed and then is used as a part (that is, a lower part) of the resistance bias electrode layer.

Furthermore, the resistance layer of the second conductivity type is formed by the ion implantation of the impurity of the second conductivity type piercing through the first silicon layer and the oxide film. Then, the second silicon layer is deposited on the first silicon layer. Thus, the first silicon layer functions as a buffer film against the ion implantation, and the acceleration energy of the ion implantation can be reduced compared to the case in which the single silicon layer is used as the resistance bias electrode layer.

DETAILED DESCRIPTION OF THE INVENTION

Now, the semiconductor device and the manufacturing method to which this invention applies will be explained by referring toFIGS. 1-6. InFIGS. 1-6, the region where the diffusion resistance is to be formed is shown in the right sides of the figures, and the region where P-channel MOS transistor is to be formed is shown in the left sides of the figures, respectively.

As seen fromFIG. 1, on the P− type silicon substrate1, N− type well region2is formed. Also, on the P type silicon substrate1, a thin oxide film3of a thickness of 10 nm-20 nm is formed by thermal oxidation. On this thin oxide film3, the first polysilicon layer4of a thickness of 50 nm-100 nm and the silicon nitride film (Si3N4)5of 50 nm-100 nm are formed by an LPCVD method. Then, etching is performed selectively on the silicon nitride film5. Here, instead of the first polysilicon layer4, an amorphous silicon layer can be used.

By this, the double layer comprising the first polysilicon layer4and the silicon nitride film5remains in predetermined areas in both the P-channel MOS transistor forming region and the polysilicon resistance element forming region. Here, it is also possible to perform the etching selectively on the first polysilicon layer4and the silicon nitride film5.

Then, thermal oxidation at about 1000° C. is performed. As shown inFIG. 2, the field oxide film6is formed in the area where the silicon nitride film has been removed by etching. The thickness of the field oxide film6is about 500 nm.

Here, the silicon nitride film5functions as an oxidation resistance film. Also, the thin oxide film3is also called a pad oxide film, and it prevents crystal defects on the P type silicon substrate under the so-called bird's beak of the field oxide film6.

Additionally, the first polysilicon layer4is called a pad polysilicon layer (pad silicon layer) and works to shorten the bird's beak. Usually, the thin oxide film3and the first polysilicon layer4are removed after the field oxidation. However, this manufacturing process keeps them intact and utilizes them as structural components of the resistor element as described later.

Next, as shown inFIG. 3, a photoresist layer7is formed on the P-channel MOS transistor forming region after the silicon nitride film5is removed. Using this photoresist layer7as a mask, ion implantation of P− type impurity is performed piercing the first polysilicon layer4and the thin oxide film3, and the P− type resistance layer8is formed on the surface of the N type well region2. Here, the preferable condition of the ion implantation process is as follows: boron ion is used in the ion implantation, the acceleration energy is 60 KeV, and the dose is 5×1012/cm2.

During the ion implantation process described above, the first polysilicon layer4and the thin oxide film3function as a buffer film against the ion implantation and prevent crystal defects on the surface of the semiconductor substrate. Also, since the first polysilicon layer4is relatively thin, the acceleration energy of the ion implantation can be reduced.

Then, as shown inFIG. 4, the second polysilicon layer9of a thickness of 50 nm-100 nm is deposited to cover the whole surface by an LPCVD method after the removal of the photoresist layer7from the P-channel MOS transistor forming region. To the second polysilicon layer9, the doping of an impurity such as phosphorus is performed by thermal diffusion, resulting in the reduction of the resistance of the second polysilicon layer9. Here, by causing the impurity to diffuse reaching to the first polysilicon layer4beneath the second polysilicon layer9, the resistance of the first polysilicon layer4is also reduced.

By this, the second polysilicon layer9is deposited on the first polysilicon layer4in the P-channel MOS transistor forming region as well as in the diffusion resistance forming region.

Then, as shown inFIG. 5, in the predetermined area on the second polysilicon layer9, the photoresist layer (not shown in the figure) is formed. Using this photoresist layer as a mask, the etching on the second polysilicon layer9and the first polysilicon layer4is sequentially and selectively performed.

By this, in the diffusion resistance forming region, a resistance bias electrode10, on which the first polysilicon layer4and the second polysilicon layer9are deposited, is formed. On the other hand, in the P-channel MOS transistor forming region, a gate electrode11, on which the first polysilicon layer4and the second polysilicon layer8are deposited, is formed. Also, on the field oxide film6, a polysilicon wiring layer (not shown in the figure) comprising the second polysilicon layer9(single layer) is formed.

Furthermore, by implanting an ion such as boron, the P+ type electrode pad layers12,13, the P+ type source layer14and the P+ type drain layer15of the P-channel MOS transistor are formed.

Next, as shown inFIG. 6, an interlayer oxide film16, such as a BPSG (boron-phosphorus silicon glass) film, is formed on the whole surface. On the P+ type electrode pad layers12,13, P+ type source layer14and the P+ type drain layer15, contact holes are formed. Through those contact holes, resistance connection electrode17,18comprising Al layer, a source electrode19, and a drain electrode20are formed. This completes the semiconductor device with the diffusion resistance. Although the explanation about forming the MOS transistor is omitted here, it is formed on the same silicon substrate and is structured the same as the CMOS.

FIG. 7is a plan view of the diffusion resistance shown inFIG. 6. Astrip of P− type resistance layer8extends between the P+ type electrode pad layers12and13. Reference numerals C1and C2denote the contact holes formed on the P+ type electrode pad layers12and13. The length of the P− type resistance layer8is determined according to the desired resistance value. Also, P− type resistance layer8is covered with the resistance bias electrode10with the thin oxide film3between them. This resistance bias electrode10is connected to the Al wiring layer21through the contact hole C3. A predetermined bias voltage VG is applied to the Al wiring layer21from a power source. By adjusting this bias voltage VG, the expansion of the depletion layer between the P− type resistance layer8and the N type well region2is suppressed.

FIG. 8is another plan view of the diffusion resistance. Here, contact hole C4is formed in the middle of the P− type resistance layer8in lateral direction, and contact hole C5is formed on the resistance bias electrode10. Through these contact holes C4and C5, the P− type resistance layer8and the resistance bias electrode10are connected by the Al wiring layer22. In this case, the voltage taken out from the P− type resistance layer8is applied to the resistance bias electrode10. Thus, use of an additional power voltage source is not required, which is one of the advantages of this embodiment.

Next, experimental results of the semiconductor device will be explained by referring toFIGS. 9 and 10, which show the voltage characteristics and the resistance characteristics of the diffusion resistance (the difference in the voltages between both sides of resistance being shown on the X-axis, and the electric current I and the resistance Rs being shown on the Y-axes). Here, the voltage applied to the P+ type electrode pad layer13is VH, the voltage applied to the P+ type electrode pad layer12is VL, and the voltage applied to the resistance bias electrode10is VG.

It is defined that R=VG/(VH−VL), where R denotes the ratio of the voltages applied to the P+ type electrode pad layers12,13(VH−VL) against the voltage VG applied to the resistance bias electrode10. According to this definition, in FIG.9(A), R=0, inFIG. 9(B), R=0.2, and in FIG.9(C), R=0.4. Also in FIG.10(A), R=0.5, in FIG.10(B), R=0.6, and in FIG.10(C), R=0.8.

As shown by the above experimental results, the voltage dependence becomes smallest when R=0.6. When R=0.5, the voltage dependence is also small enough to be ignored. But when R=0.4 or less, the resistance value Rs rises as the voltage VH increases. It is believed that this is because the depletion layer has been expanded. On the other hand, when R=0.8, the resistance value Rs goes down as the voltage VH increases. It is believed that this is because an accumulation of carriers has taken place.

As explained above, since the semiconductor device of this invention is equipped with the oxide film as well as the resistance bias electrode on the resistance layer, the expansion of the depletion layer between the semiconductor substrate and the resistance layer is suppressed. Thus, the voltage dependence of the resistance of the resistance layer can be reduced.

The invention also has the advantage that an additional power source is not required, since the voltage applied to the resistance bias electrode layer is provided from the middle of the resistance layer in lateral direction.

Furthermore, the manufacturing method of this invention allows for the reduction of manufacturing process steps, because the first silicon layer remains intact when the field oxide film is formed and then is used as a part (lower part) of the resistance bias electrode layer.

Also, the resistance layer of the second conductivity type is formed by the ion implantation of the impurity of the second conductivity type piercing through the first silicon layer and the oxide film. Then, the second silicon layer is deposited on the first silicon layer. Thus, the first silicon layer functions as the buffer film against the ion implantation and the acceleration energy of the ion implantation can be reduced compared to the case in which the single silicon layer is used as the resistance bias electrode layer.