Apparatus and method including a memory device having multiple sets of memory banks with duplicated data emulating a fast access time, fixed latency memory device

An apparatus includes two multi-bank memory devices for storing duplicate data in each memory bank in an embodiment of the invention. The two memory devices are able to replace a more expensive fast-cycle, fixed latency single memory device. In an embodiment of the invention, a memory controller includes controller logic and a plurality of write buffers for interleaving write transactions to each memory bank in the two memory devices. A memory controller also includes tag memory for identifying valid data in the memory banks. In another embodiment of the invention, a game console includes the apparatus and executes game software that requires fixed latency in a mode of operation. In yet another embodiment of the invention, each memory device is coupled to respective write channels. Write data is simultaneously written to two memory banks in respective sets of memory banks in a memory device in an embodiment of the present invention. In an alternate embodiment of the present invention, an apparatus includes four memory devices for storing duplicate data with each memory device having a set of memory banks. The four memory devices are coupled to a controller by four respective write channels.

FIELD OF THE INVENTION

The present invention relates to the transfer of data in a memory apparatus.

BACKGROUND

A memory apparatus typically includes a master device, such as a memory controller, and a plurality of memory devices for storing data. A user of a memory apparatus is generally interested in being able to store as much data as possible in the memory devices as well as being able to transfer the data to and from the memory devices as fast as possible.

Some memory apparatus include memory devices having a single memory bank. A single bank memory device may be used in the apparatus because single bank memory devices generally have faster access times than multi-bank memory devices. Second, if multi-bank memory devices are used instead of single bank memory devices, the actual throughput of data transferred in the apparatus may be reduced. Memory bank conflict during concurrent read transactions to the same memory bank may cause the actual throughput to be less than the theoretical maximum. Third, an apparatus having multi-bank memory devices generally requires a more complex controller to keep track of read and write transactions to the various memory banks. An apparatus with a single bank memory device often has a fixed latency of transferring data.

While users may prefer the benefits of a memory apparatus having a single bank memory device, single bank memory devices having relatively fast access times are generally more expensive than the slower multi-bank memory devices. Accordingly, when a user wants to upgrade or replace the memory devices in the apparatus, the user has to pay for the more expensive single bank memory devices.

Further, when a user replaces or upgrades the memory devices, the user generally wants to run the same software applications that were previously executed using the previous memory devices.

Therefore, it is desirable to provide an apparatus and method having the software compatibility and benefits of a single bank memory device, without the added cost.

DETAILED DESCRIPTION

An apparatus includes two multi-bank memory devices for storing duplicate data in each memory bank in an embodiment of the invention. The two memory devices are able to replace a more expensive fast-cycle, fixed latency single memory device. In an embodiment of the invention, a memory controller includes controller logic and a plurality of write buffers for interleaving write transactions to each memory bank in the two memory devices. A memory controller also includes tag memory for identifying valid data in the memory banks.

In another embodiment of the invention, a game console includes the apparatus and executes game software that requires fixed latency in a mode of operation.

In yet another embodiment of the invention, each memory device is coupled to respective write channels. Write data is simultaneously written to two memory banks in respective sets of memory banks in a memory device in an embodiment of the present invention. In an alternate embodiment of the present invention, an apparatus includes four memory devices for storing duplicate data with each memory device having a set of memory banks. The four memory devices are coupled to a controller by four respective write channels.

An access time of a memory device, also known as cycle time or row cycle time (“tRC”), is an amount of time required to read or write a set of data from or to a storage location in a bank of a memory device. A transport time is an amount of time required to move the set of data between a memory device and a memory controller.

FIG. 1illustrates a memory device100having a single bank101, in a core100a, and a coupling interface100b. Bank101is a two dimensional array of storage cells and associated circuitry for reading and writing the cells. Memory device100includes a bus A for providing control and address signals for addressing a storage location in bank101. Bus A is coupled to circuitry105for coupling interface100bto core100a. Pipeline register102is coupled to circuitry105and receiver108. Bus RQ is coupled to receiver108and carries external control and address signals. Bus S is an internal bidirectional bus for providing read/write data signals to and from the addressed memory location. Bus S is coupled to circuitry106and107for coupling interface100bto core100a. Pipeline registers103and104are coupled to circuitry106and107, respectively. Transmitter109and receiver110are coupled to pipeline registers103and104, respectively. An external bus DQ transfers external bidirectional read/write signals and is coupled to transmitter109and receiver110. A CLK line provides a clock signal to registers102-104for synchronizing memory device100transactions.

The pipeline registers102,103, and104are used for synchronization of the information between the internal and external buses. Registers102-104may also be used for generating delay, as would be required if the internal and external buses used a different number of signals. Although memory device100shows a single level (clock cycle) of pipeline registers, two or more levels (clock cycles) of delay are used in an alternative embodiment of the present invention.

FIG. 2ashows a timing diagram illustrating a sequence of read transactions. A read transaction includes generating a READ command having an address of the memory location to be read on bus RQ and transferring the read data signals from bank101onto bus DQ in an embodiment of the present invention. In an embodiment of the present invention, READ commands (R0, R1, R2. . . ), containing address and control information, are received on every fourth rising edge in a four clock cycle memory apparatus. A first READ command R0is accessed between clock edges0and4, and the read data signal on bus S is loaded into pipeline register103and transported between clock edges4and8. In other words, the transport time is also four clock cycles as the data signal is divided into four pieces or sets of data (R0a, R0b, R0c, R0d), and each piece is transported during a clock cycle. This allows the next READ command R1to perform its access during the transport of the R1READ command.

Although memory device100illustrates a single memory bank, two or more memory banks that do not use overlapped operations are used in an alternative embodiment of the present invention. In other words, if the access times of two successive read transactions do not overlap (even if directed to two different banks), then a two (or more) bank memory device is functionally equivalent to the one bank memory device shown inFIG. 1. An important distinction is whether the access time of successive transactions is overlapped or not overlapped.

An example of a single bank memory device is a “Splash” MoSys® 1T-SRAM memory device manufactured by Monolithic System Technology, Inc, Sunnyvale, Calif., United States of America.

FIG. 2bshows a timing diagram illustrating a sequence of write transactions. A write transaction includes generating a WRITE command having an address of the memory location to be written on bus RQ and transferring the write data signals on bus DQ to the addressed memory location in bank101in an embodiment of the present invention. WRITE commands (W0, W1, W2. . . ), containing address and control information, are received on every fourth rising edge in a four clock cycle memory apparatus. Data signals or a set of data for a first WRITE command W0is transported between clock edges0and4, and the write data signals are driven onto bus S from pipeline registers104and accessed (written to the storage location) between clock edges4and8. In other words, a write access time is also four cycles. This allows the next WRITE command W1to perform its transport during the access of the W0WRITE command. Access and transport steps are reversed for read and write transactions.

The timing relationships seen inFIGS. 2a-brepresent one method of arranging the timing slots for the RQ, A, S, and DQ buses for the read and write transactions. Other arrangements are possible, but will not affect the important distinction of whether the access times of successive transactions are overlapped or not.

FIG. 3illustrates a memory device300, having two memory banks b1301and b2302, with a slower access time than memory device100shown inFIG. 1. In embodiments of the present invention, memory device300is a double data rate 1 (“DDR1”), or a double data rate 2 (“DDR2”) memory device.

Banks301and302are two-dimensional array of storage cells and associated circuitry for reading and writing the cells. In embodiments of the present invention, the memory cells of bank b0301and/or b1302may be dynamic random access memory (“DRAM”) cells, static random access memory (“SRAM”) cells, read-only memory (“ROM”) cells, or other equivalent types of memory cells.

Memory device300includes a bus A for providing control and address signals for addressing a storage location in bank b0301or bank b1302. Bus A is coupled to circuitry305for coupling interface300bto core300a. Pipeline register312is coupled to circuitry305and receiver308. Bus RQ is coupled to receiver308and carries external control and address signals.

Bus S is an internal bidirectional bus for providing read/write data signals to and from the addressed memory location of bank b0301or b1302. Bus S is coupled to circuitry306and307for coupling interface300bto core300a. Pipeline registers303and304are coupled to circuitry306and307, respectively. Transmitter309and receiver310are coupled to pipeline registers303and304, respectively. An external bus DQ transfers external bidirectional read/write signals and is coupled to transmitter309and receiver310. A CLK line provides a clock signal to pipeline registers312,303and304for synchronizing memory device300transactions.

The pipeline registers312,303and304are used for synchronization of the information between the internal and external buses. Pipeline registers312,303and304also may be used for generating delay, as would be required if the internal and external buses used a different number of signals. Although memory device300shows a single level (clock cycle) of pipeline registers, two or more levels (clock cycles) of delay are used in an alternative embodiment of the present invention.

FIG. 4ashows a timing diagram illustrating a sequence of read transactions for the memory device shown inFIG. 3. READ commands (R0, R1, R2, R3. . . ), containing address and control information, are received on every fourth rising edge in an apparatus where a read access time is 8 clock cycles. The first READ command R0for bank b0301is accessed between clock edges0and8, and the read data signals on bus S are loaded into pipeline register303and transported between clock edges8and12(R0a, R0b, R0c, R0d). In other words, the transport time is four clock cycles.

A second READ command R1is accessed between clock edges4and12from bank b1302, and read data signals on bus S are loaded into pipeline register303and transported between clock edges12and16(R1a, R1b, R1c, R1d). The access steps of the first and second transactions can be overlapped because their addresses select different banks.

A third READ command R2is accessed between clock edges8and16, and the read data signal on bus S is loaded into pipeline register303and transported between clock edges16and20(R2a, R2b, R2c, R2d). During clock cycles8to12, three transactions are being processed by memory device300, each at a different step (first-half-access of bank b0301, second-half-access of bank b1302and transport).

Throughput, also known as data bandwidth, of memory device300is the same as memory device100. However, because the access time of memory device300is longer due to greater memory cell density, memory device300will typically be less expensive to manufacture.

The timing relationships seen inFIGS. 4a-band5a-brepresent one method of arranging the timing slots for the RQ, A, S, and DQ buses for the read and write transactions. Other arrangements are possible, but will not affect the important distinction of whether the access times of successive transactions are overlapped or not.

A disadvantage of memory device300is that memory bank conflict is possible as seen inFIGS. 5a-b. For example, memory bank conflict occurs when two successive READ commands (R1and R3) must access the same bank b1302. An access step for READ command R3must wait until the access step of READ command R1has completed, and a four-cycle bubble or gap is inserted into the read data stream on bus DQ. Thus, throughput of memory device300can be less than the theoretical maximum, and the effective throughput depends upon the distribution of addresses in a command stream.

Because of the possibility of memory bank conflict, some memory apparatus will not use a memory device that overlaps access steps for two successive transactions; only the transport and access steps will be overlapped as illustrated inFIGS. 2a-b. In this memory apparatus, a memory device is being operated as if it effectively has a single memory bank, even though it has multiple banks.

Such memory apparatus tend to have a more limited storage capacity, or a more limited data bandwidth, than a memory apparatus built from slower multi-bank memory devices. However, it would have performance characteristics that were more predictable because of the absence of bank conflicts.

FIG. 6shows an apparatus690for writing and reading data to and from a plurality of multi-bank memory devices that emulates a single bank memory device.FIG. 6illustrates a memory apparatus690having slave devices, and in particular memory devices d0300and d1300, and a master device, such as a memory controller600. The contents of memory devices d0300and d1300are duplicated. Thus, only one-half of the storage capacity can be used.

InFIG. 6, reference numbers refer to like components shown inFIG. 3and described above for both memory devices d0300and d1300.

External buses RQ d0/d1and DQ d0/d1and a Clk line couple memory controller600to memory devices d0300and d1300.

In an embodiment of the present invention, buses described herein are interconnects that include a plurality of conducting elements such as a plurality of wires and/or metal traces/lines. In an embodiment of the present invention, external buses include control and data signal lines. In an alternate embodiment of the present invention, external buses include only data lines or only control lines. In still another embodiment of the present invention, an external bus is a unidirectional bus. Circuit components described herein are likewise coupled by a single or multiple interconnects that may be represented in the figures by a single line or multiple lines in embodiments of the invention.

In an alternate embodiment of the present invention, buses RQ-d0and RQ-d1are shared, since buses RQ-d0and RQ-d1are not simultaneously utilized. In an alternate embodiment of the present invention, buses DQ-d0and DQ-d1are shared, since buses DQ-d0and DQ-d1are not simultaneously utilized.

In an alternate embodiment of the present invention, buses shown inFIGS. 6,9,12,13,16and19are used in intrachip, as well as interchip, communications. In an alternate embodiment of the present invention, components shown inFIGS. 6,9,12,13and19are incorporated on an integrated monolithic circuit.

In an alternate embodiment of the present invention, memory devices are positioned on a substrate used in a memory module.

In alternate embodiments of the present invention, a master device is a central processing unit. In alternate embodiments of the present invention, apparatuses690,990,1390,1690and1990are in a processing device such as a mainframe computer, a desktop computer, a laptop computer, a hand-held computer, a network controller, a personal digital assistant, a telephone, a cellular telephone, a game console, a printer, an information appliance, or an equivalent thereof.

Apparatus690includes memory devices d0300and d1300having multiple memory banks; yet, emulates read and write transactions as if memory devices d0300and d1300were a single bank memory device as seen inFIG. 1. In other words, memory devices d0300and d1300operate as if they have the approximate fixed latency of a single bank memory device100. Write transactions are performed for each memory bank in a memory device to ensure duplicate data. Accordingly, apparatus690includes memory devices d0300and d1300that have respective longer access times and are less expensive than a single memory bank memory device, while maintaining at least the same throughput. By having duplicate data in each memory bank, no bank conflict occurs. Write transactions are issued to memory devices d0300and d1300from memory controller600, performing interleaved transactions to the two memory banks of each memory device d0300and d1300.

Memory controller600is coupled to buses RQ-d0, DQ-d1, RQ-d0, DQ-d1and clock line CLK in an embodiment of the present invention. Memory controller600also includes two memory write buffers602-603or write queues in an embodiment of the present invention. In addition, memory controller600includes memory address and control generation logic601for generating WRITE and READ commands to memory devices d0300and d1300.

Write data is input to one of two write buffers602and603—one write buffer for memory banks b0and one write buffer for memory banks b1—as shown inFIGS. 6 and 7. Write data is sent to the selected bank of both devices d0300and d1300by way of multiplexer604and bus DQ-d0/d1.

Memory address and control generation logic601initiates a read transaction to either memory device d0300or d1300on bus RQ-d0/d1. Similarly, memory address and control generation logic601initiates a write transaction to both memory devices d0300and d1300on bus RQ-d0/d1. Address and control information is input to memory address and control generation logic601.

Read data is received by memory controller600on bus DQ-d0/d1and may also be received from write buffers602and603on a coherency path. Multiplexer605selects the read data from either memory device d0300or d1300, or write buffers602or603.

If the read is to an address for a pending write in one of the write buffers602or603, the read data is returned from the pending write by way of the coherency path. As seen inFIG. 7, if a read is made to address (adr=2) of bank b0or either memory device d0300or d1300, then the new write data “O” will be returned from the write buffer602for bank b0instead of the old (stale) data E in address (adr=2) of bank b0of either memory device d0300or d1300.

If the read is made to address (adr=1) of bank b1of either memory device d0300or d1300, then the new write data “P” will be returned from the write buffer for bank b1instead of the old (stale) data “D” in address (adr=1) of bank b1of either memory device d0300or d1300.

In an embodiment of the present invention, entries in the write buffers602and603are added to the next empty slot (shown with the label “empty”). Write buffers602and603are emptied from the next full slot (the data “O” and “R”, as seen inFIG. 7). This allows write buffers602and603to be managed with two pointers (one for full and one for empty), which wrap around at a minimum and maximum slot in the write buffer. Such a write buffer is also known as a circular queue.

A timing diagram illustrating the read and write transactions of apparatus690are shown inFIGS. 8a-b.

FIG. 8aillustrates interleaved read transactions. Memory device d0300handles the read transactions in every eighth cycle slot (at t0, t8, t16. . . ); while memory device d1300handles the read transactions in the alternate slots (at t4, t12, t20. . . ) as seen inFIG. 8a. Cross-hatched slots are not needed, since the data is duplicated in the two memory devices.

FIG. 8billustrates interleaved write transactions. The same data is written to both memory devices d0300and d1300into the same bank at the same address (A/S-b0-d0and A/S-b0-d1). Write buffers ensure that sequential write transactions are directed to alternate banks (b0, b1, b0, b1. . . ).

There will be enough bandwidth for write transactions as long as no bank conflicts occur. It is easier to reduce bank conflict rate for write transactions than for read transactions. A read transaction is latency-sensitive; if it is held in memory controller600, an execution of logic or software elsewhere in apparatus690is being starved of read data that it needs in order to proceed. A write transaction is latency-insensitive; if it is held in memory controller600(and coherency logic is provided so this held data is returned if a read transaction is made to the affected storage location), the write transaction may be held off indefinitely.

Thus, write transactions are accumulated in two write buffers602-603, or queues, one for a first memory bank in the memory devices d0/d1300and a second for the second memory bank in the memory devices d0/d1300. This allows writes to be issued out-of-order from the queues so that bank conflicts can be avoided when a burst of write transactions are issued. The deeper the write queues are made, the less likely the chance of a bank conflict and its imposition of bubble cycles.

The approximate relationship between bubble probability and queue depth is:
Bubble probability=[(N−1)/B]Q*B
whereN=access time/transport timeB=number of banksQ=queue depth (per bank)
For this embodiment, N is 2 and B is 2. For a queue depth of 32 entries, the probability of a bubble is about 10−20. Because of this exponential relationship, it is easy to reduce the chance of a bubble to an arbitrarily small value. Also, it should be noted that the address-matching time of the write buffer (for coherency checking) is not in a critical path, since it will occur in parallel with a normal read transaction.

FIG. 9illustrates another embodiment of the present invention.FIG. 9, likeFIG. 6, illustrates an apparatus990having multiple memory devices having two memory banks with duplicated data. InFIG. 9, reference numbers refer to like components shown inFIG. 6and described above. However,FIG. 9illustrates an apparatus990including a controller900having tag memory906.

At each bank address adr, one of the two following cases is true: adr-b0-d0is valid; adr-b0-d1is valid; adr-b1-d0is invalid and adr-b1-d1is invalid, or adr-b0-d0is invalid; adr-b0-d1is invalid; adr-b1-d0is valid; adr-b1-d1is valid. In either case, the valid data at location adr is identical between the two devices. Thus, only one-fourth of the storage capacity can be used.

Memory address and control generation logic901initiates a read transaction to either memory device d0300or d1300on bus RQ. Similarly, memory address and control generation logic901initiates a write transaction to both memory devices d0300and d1300on bus RQ. Memory address and control generation logic901reads and writes to tag memory906. Address and control information is also input to memory address and control generation logic901.

Write data is provided to memory devices d0300and d1300by bus DQ as seen inFIG. 9. If a write transaction is to be issued, controller900may choose to write the data to either bank b0of both devices d0300and d1300, or to bank b1of both devices d0300and d1300. The bank selection is the opposite of the bank that was used in the previous write transaction (this avoids bank conflict). Tag memory906is updated with the bank selection, so memory address and control generation logic901will know for subsequent read transactions which bank contains valid data and which bank contains invalid data at each address.

Read data is provided from bus DQ and multiplexed by multiplexer905. If a read is made to address (adr=1), controller900must use bank b0301in either memory device d0300or d1300as seen inFIG. 10. This is because at adr=1, bank b0of each memory device contains the data “B,” and bank b1of each device is invalid. Memory controller900determines that it must read from bank b0at adr=1 by reading the content of the tag memory906at adr=1. The content is a single bit indicating that bank b0is valid. In an embodiment of the present invention, tag memory906has the same number of address locations (each one bit in size) as each bank of the memory devices.

FIGS. 11a-billustrate interleaved read and write transactions of apparatus990shown inFIG. 9.FIG. 11ashows how bank b0has valid data at the address associated with READ command R0; bank b1has valid data at the address associated with READ command R1; bank b1has valid data at the address associated with READ command R3; bank b0has valid data at the address associated with READ command R4; and bank b0has valid data at the address associated with READ command R6. Cross-hatched slots are not needed, since the data is duplicated in memory devices d0300and d1300.

FIG. 11bshows interleaved write transactions. The same data is written to both memory devices d0300and d1300into the same address of either bank b0or bank b1(the opposite of the bank used by the previous write transaction).FIG. 11bshows how bank b0is written with valid data at the address associated with WRITE command W0; bank b1is written with valid data at the address associated with WRITE command W2; bank b0is written with valid data at the address associated with WRITE command W3; bank b1is written with valid data at the address associated with WRITE command W7; bank b0is written with valid data at the address associated with WRITE command W6and bank b1is written with valid data at the address associated with WRITE command W1.

FIG. 12illustrates a game console1200embodiment of the present invention. In an embodiment of the present invention, game console1200is a GameCube Console (Indigo) manufactured by Nintendo®. Game console1200includes a disk drive1201for inserting a compact disk read-only memory (“CD-ROM”) storing game software1201a. In alternate embodiments of the present invention, other equivalent storage media and drives may be used to store and read game software1201a. In an alternate embodiment of the present invention, game software1201ais downloaded from a network or the Internet. Game software1201aincludes machine readable executable instructions that are played by a user or executed by game console1200in an embodiment of the invention.

Processor1202is coupled to disk drive1201by bus1205. Processor1202includes mode logic1202athat determines the version of game software1201aor in what mode game console1200needs to operate in playing game software1201a. In an embodiment of the present invention, the function of mode logic1202ais carried out by software. Mode logic1202athen generates a mode signal to controller1203by way of bus1205when game software1201ais an older or “legacy” version. In an embodiment of the present invention, a mode signal is input to memory address and control generation logic601and/or901. As described above, controller1203is coupled to multibank memory devices1204by a CLK line as well as buses RQ and DQ.

Controller1203then generates duplicate data from game software1201aon multibank memory devices1204as described herein in order to accommodate the fixed latency requirement of game software1201a. Game console1200is then able to operate in a mode emulating a single memory bank memory device architecture. If mode logic1202adetermines that game software1201ais not an older version, a mode signal is not generated by processor1202to controller1203. Controller1203then does not write duplicate data from game software1201ato memory device1204and game software1201ais able to use the extra memory available by not duplicating data. Thus, game console1200is able to run an older game software that requires fixed latency as well as recent game software that can take advantage of extra memory.

FIG. 13is a block diagram of an apparatus1390including two memory devices d01300and d11301, with duplicated data, having two sets of memory banks that emulate a fixed latency memory device according to an embodiment of the present invention. As described above, memory devices d01300and d11301operate as if they have the approximate fixed latency of a single bank memory device100. Memory devices d01300and d11301each include at least two memory bank sets0and1in cores1300aand1301a, respectively. Contents of both memory bank sets0and1of each memory device1300and1301are identical, thus only one-fourth of the available storage capacity can be used in an embodiment of the present invention. Memory devices d01300and d11301have a slower access time than memory device100shown inFIG. 1. In an embodiment of the present invention, memory devices d01300and d11301are extreme data rate (“XDR”) memory devices.

Memory bank sets0and1each include a plurality of memory banks with each memory bank having a two-dimensional array of storage cells and associated circuitry for reading and writing the cells. In embodiments of the present invention, the memory cells in a memory bank of memory bank sets0or1may be DRAM cells, SRAM cells, ROM cells, or other equivalent types of memory cells.

Memory device d01300, like memory device d11301, includes buses A0and A1for providing control and address signals for addressing a storage location in a memory bank of memory bank sets0and1, respectively. Buses A0and A1are coupled to circuitry1305for coupling interfaces1300band1301bto cores1300aand1301a, respectively. Pipeline register1302is coupled to circuitry1305and receiver1308. Bus RQ-d0is coupled to receiver1308and carries external control and address signals.

Buses S0and S1are internal bidirectional buses for providing read/write data signals to and from the addressed memory location of a memory bank in memory bank sets0and1, respectively. Buses S0and S1are coupled to circuitry1306and1307for coupling interfaces1300band1301bto cores1300aand1301a, respectively. Pipeline registers1303and1304are coupled to circuitry1306and1307, respectively. Transmitter1309and receiver1310are coupled to pipeline registers1303and1304, respectively. An external bus DQ transfers external bidirectional read/write signals and is coupled to transmitter1309and receiver1310. A CLK line provides a clock signal to registers1302-1304for synchronizing memory device1300transactions.

The pipeline registers1302,1303, and1304are used for synchronization of the information between the internal and external buses. Pipeline registers1302-1304also may be used for generating delay, as would be required if the internal and external buses used a different number of signals. Although memory devices d01300and d11301show a single level (clock cycle) of pipeline registers, two or more levels (clock cycles) of delay are used in an alternative embodiment of the present invention.

FIG. 13also shows a master device, such as a memory controller1350, for writing duplicate data to memory devices d01300and d11301.

Memory controller1350also includes four memory buffers1352-1355or write queues in an embodiment of the present invention. In addition, memory controller1350includes memory address and control generation logic1351for generating WRITE and READ commands to memory devices d01300and d11301. A read transaction is directed to either memory bank set0or memory bank set1of either memory device d01300or d11301. A write transaction is directed to both memory bank sets0and1of both memory devices d01300and d11301in an embodiment of the present invention.

Write data is input to one of four write buffers1352-1355—one write buffer for memory banks b0, one write buffer for memory banks b1, one write buffer for memory bank b2and one write buffer for memory bank b3as shown inFIGS. 13 and 14. Write data is sent to the selected bank of both memory devices d01300and d11301by way of multiplexer1357, delay1358and bus DQ-d0/d1. Write data is sent, with a staggered delay, to the selected bank of all four memory bank sets in memory devices d01300and d11301by delay1358.

Multiplexer1356selects the read data to be output from either memory device d01300or d11301. If a read data is to an address for a pending write in one of the write buffers1352-1355, the read data is returned from the pending write buffer via coherency path1359. For example, as seen inFIG. 14, if a read is made to address (adr=1) of memory bank b3of either memory device1300or1301, new write data “U” will be returned from write buffer for memory bank b31355instead of the old (stale) data “H” in address (adr=1) of memory bank b3of either memory bank sets0or1of either memory device1300or1301.

FIG. 14illustrates address space content in memory bank sets0and1in memory devices d01300and d11301and write buffer content in the four write buffers1352-1355of the memory controller1350shown inFIG. 13according to an embodiment of the present invention. In an embodiment of the present invention, each write buffer is a circular queue. Write data is added to the next empty location in write buffers1352-1355(shown with the label “empty” and indicated by the label “tail”). A write buffer is emptied from the next full location (the write data “I”, “L”, “P”, and “T” shown inFIG. 14). This allows each write buffer1352-1355to be managed with two respective pointers (a first pointer for a “head” and a second pointer for a “tail”) that wrap around at the minimum and maximum limits in each write buffer.

FIGS. 15a-bare timing diagrams illustrating read and write transactions of apparatus1390shown inFIGS. 13 and 14. The timing diagrams shown inFIGS. 15a-billustrate how multi-set memory bank memory devices d01300, d11301and memory controller1350operate to emulate an apparatus containing a memory device having a single memory bank with a fixed latency. For example, a READ transaction for reading data R0is asserted at the input of memory device d01300before the first cycle time slot. Then, ACTIVATION command A0for transaction R0is asserted on bus RQ-d0-s0in memory device d01300in the third cycle time slot. Read command R0is input to memory bank set0on bus RQ-d0-s0in the eighth cycle time slot. Read data is then output on bus DQ-d0-s0as read data Q0in the 14thand 15thcycle time slots and received by memory controller1350in the 16thcycle time slot. The time difference between when a read transaction R0is received on an addr/ctrl bus to when read data Q0is returned at the “Read Data” internal bus of the memory controller1350is constant or has an approximate fixed latency. Thus, read and write transactions are handled at fixed intervals regardless of which memory bank is addressed.

FIG. 16is a block diagram of an apparatus1690including two memory devices, with duplicated data, having two sets of memory banks and two independent write channels or buses labeled DQ-d0and DQ-d1, according to an embodiment of the present invention. Two memory devices1300and1301, as described above, have two sets of memory banks that emulate a fixed latency, single memory bank device according to an embodiment of the present invention. Like reference numbers inFIG. 16refer to like components described above. Likewise, apparatus1690includes memory controller1350, as described above, in an embodiment of the present invention.

32 bytes of write data is written into each memory bank set in each four-cycle time interval, as illustrated byFIG. 17, in an embodiment of the present invention. A cycle time tCYCLEis 1/324 Mhz or approximately 3.1 ns in an embodiment of the present invention. A row cycle time tRCis 16 cycles or approximately 50 ns. Thus, each memory bank set will have four staggered write transactions in process during every 16 cycles.

In apparatus1690, memory controller1350alternates writing to the two memory bank sets0and1in each memory device1300and1301on each independent write channel DQ-d0and DQ-d1, respectively, as illustrated byFIG. 17. Accordingly, the column cycle time tccis equal to 2*tcycleor approximately 6.2 ns.

The aggregate data rate, combining the data rates of write channel DQ-d0and DQ-d1, is 5184 MB/s (16×324). In an embodiment of the present invention, the width N of each write channel0and1, is 16 bits which allows for a data rate for each bit to be 2592 Mb/s (8*324). In an alternate embodiment of the present invention, the width N of each write channel0and1is 32 bits that allows for a data rate for each bit to be 1296 Mb/s (4*324).

FIG. 18is a timing diagram illustrating simultaneous write transactions to both memory bank sets in either memory device d01300or d11301of apparatus1690shown inFIG. 16. This operation of apparatus1690reduces the data rate on each write channel0and1. A column cycle time tCCis four-cycle times tcycleor approximately 12.4 ns. Accordingly, each write channel0and1transfers 32 bytes in 12.4 ns, so the aggregate data transfer rate is 2595 MB/s (8*324). In an embodiment of the present invention, the width N of each write channel0and1is 8 bits that allows for a data rate for each bit to be 2592 Mb/s (8*324). In an alternate embodiment of the present invention, the width N of each write channel0and1is 16 bits that allows for a data rate for each bit to be 1296 Mb/s (4*324). In an alternate embodiment of the present invention, the width N of each write channel0and1, is 32 bits which allows for a data rate for each bit to be 648 Mb/s (2*324).

FIG. 19is a block diagram of an apparatus1990including four memory devices d01300, d11301, d21322and d31323having respective sets of memory banks with duplicated data according to an embodiment of the present invention. The apparatus1990shown inFIG. 19requires only four memory banks, rather than eight memory banks in an embodiment of the present invention. Also, apparatus1990allows for reduced data rate on each write channel0,1,2and3coupled to memory controller1350.

Memory devices d01300, d11301, d21322and d31323each have a set of memory banks that in combination emulate a fixed latency, single memory bank device according to an embodiment of the present invention. As described above, memory devices d01300, d11301, d21322and d31323operate as if they have the approximate fixed latency of a single bank memory device100. Memory devices d01300, d11301, d21322and d31323are similar to memory devices d01300and d11301shown inFIG. 16where like reference numbers refer to like components described above. Memory devices d21322and d31323have cores1302aand1303a, as well as interfaces1302band1303b, that operate similar to cores1300a-1301aand interfaces1300band1302b. Likewise, apparatus1990includes memory controller1350, as described above, in an embodiment of the present invention. However unlike apparatus1390, memory devices d01300, d11301, d21322and d31323shown inFIG. 19each have a single set of memory banks and a single internal bus A and S. Further unlike apparatus1390, memory controller1350shown inFIG. 19is coupled to memory devices d01300, d13101, d21322, d31323by four independent write channels or buses labeled as DQ-d0, DQ-d1, DQ-d2and DQ-d3, respectively.

FIG. 20is a timing diagram illustrating write transactions of apparatus1990shown inFIG. 19. A column cycle time tCCis four-cycle times tcycleor approximately 12.4 ns. Accordingly, each write channel0,1,2and3transfers 32 bytes in 12.4 ns, so the aggregate data transfer rate is 2595 MB/s (8*324). In an embodiment of the present invention, the width N of each write channel0,1,2and3is 8 bits that allows for a data rate for each bit to be 2592 Mb/s (8*324). In an alternate embodiment of the present invention, the width N of each write channel0,1,2and3is 16 bits that allows for a data rate for each bit to be 1296 Mb/s (4*324). In an alternate embodiment of the present invention, the width N of each write channel0,1,2and3is 32 bits that allows for a data rate for each bit to be 648 Mb/s (2*324).

As one of ordinary skill in the art would appreciate, adequate bandwidth control of the RQ buses in apparatuses1390,1690and1990must be ensured such that read transactions can be completed within an approximate fixed latency, and with the same fixed latency as previous so-called fast cycle, fixed latency memory devices used in a game console. Thus, legacy game software1201ais able to run on a game console1200, as seen inFIG. 12, while using the emulating apparatuses1390,1690and1990described herein.