Semiconductor device including a vertical edge termination structure and method of manufacturing

A semiconductor device includes a semiconductor body with a first surface at a first side, a second surface opposite to the first surface and an edge surface connecting the first and second surfaces. An edge termination structure includes a glass structure and extends along the edge surface, at least from a plane coplanar with the first surface towards the second surface. A conductive structure extends parallel to the first surface and overlaps the glass structure at the first side.

BACKGROUND

In power semiconductor devices edge termination structures along the outer edge of a semiconductor die are vitally important for achieving a high blocking capability. In the blocking mode vertical edge termination structures support the blocking voltage along a vertical direction of the semiconductor die, wherein the electric field lines run along the vertical direction and the equipotential lines run approximately parallel to the main surfaces of the semiconductor die. There is a need for improved vertical edge termination structures.

SUMMARY

An embodiment refers to a semiconductor device that includes a semiconductor body with a first surface at a first side, a second surface opposite to the first surface and an edge surface connecting the first and second surfaces. An edge termination structure includes a glass structure and extends along the edge surface at least from a plane coplanar with the first surface towards the second surface. A conductive structure extends parallel to the first surface and overlaps the glass structure at the first side.

Another embodiment refers to a method of manufacturing a semiconductor device. A frame trench is formed that extends from a first surface into a semiconductor substrate. The frame trench is filled with an edge termination structure including a glass structure. A conductive layer is formed on the semiconductor substrate and the edge termination structure. A portion of the conductive layer above the edge termination structure is removed, wherein a remnant portion of the conductive layer covers a portion of the edge termination structure directly adjoining a sidewall of the frame trench.

DETAILED DESCRIPTION

The term “electrically connected” describes a permanent low-ohmic connection between electrically connected elements, for example a direct contact between the concerned elements or a low-ohmic connection via a metal and/or highly doped semiconductor. The term “electrically coupled” includes that one or more intervening element(s) adapted for signal transmission may be provided between the electrically coupled elements, for example elements that are controllable to temporarily provide a low-ohmic connection in a first state and a high-ohmic electric decoupling in a second state.

The semiconductor device500ofFIG. 1Amay be a semiconductor diode with a semiconductor body100provided from a single-crystalline semiconductor material, for example silicon (Si), silicon carbide (SiC), germanium (Ge), a silicon germanium crystal (SiGe), gallium nitride (GaN) or gallium arsenide (GaAs), by way of example.

A distance between a planar first surface101of the semiconductor body100at a first side and a planar second surface102parallel to the first surface101at an opposite second side may be at least 20 μm, for example, at least 150 μm and may reach several hundred μm. A perpendicular to the first surface101defines a vertical direction and directions orthogonal to the vertical direction are lateral directions.

The semiconductor body100includes a drift zone120of a first conductivity type and an anode region115of a second conductivity type, which is complementary to the first conductivity type. A mean impurity concentration in the drift zone120may be between 5×1012(5E12) cm−3and 5×1014(5E14) cm−3, by way of example. The anode region115and the drift zone120form a pn junction parallel to the first surface101.

A heavily doped pedestal region130of the first conductivity type and arranged between the drift zone120and the second surface102is effective as a cathode region. The pedestal region130may be a continuous layer of the first or the second conductivity type, wherein the impurity concentration in the pedestal region130may be at least 5×1017(5E17) cm−3, e.g., at least 5×1018(5E18) cm−3to ensure an ohmic contact between the pedestal region130and a metallization directly adjoining the second surface102. According to other embodiments, the pedestal region130may include heavily doped first zones of the first conductivity type and heavily doped second zones of the second conductivity type.

Between the drift zone120and the pedestal region130the semiconductor body100may include a field stop layer128with an impurity concentration at least ten times as high as the impurity concentration in the drift zone120and at most a tenth of the impurity concentration in the pedestal region130. The field stop layer128may include two or more sub layers, wherein in each sub layer the vertical impurity concentration profile may have a local maximum.

In the blocking mode of the semiconductor diode a depletion zone extending from the pn junction into the direction of the second surface102extends at most up to a unipolar homojunction, e.g. a pp+or nn+junction, between the field stop layer128and the pedestal region130. As a consequence, at least up to the nominal breakdown voltage of the semiconductor device500the pedestal region130is devoid of an electric field.

An edge surface103, which may be straight or stepped, connects the first and the second surfaces101,102. A slope angle α of the edge surface103with respect to a normal to the first surface101may be between −60 and +60 degree, wherein the semiconductor body100tapers from the second102to the first surface101. According to the illustrated embodiment, the edge surface103is straight and approximately vertical.

An edge termination structure400including a glass structure450directly adjoins at least a portion of the edge surface103. The edge termination structure400may include an optional auxiliary structure440extending from the first surface101towards the second surface102. The auxiliary structure440may separate at least the anode region115and the drift zone120from the glass structure450. According to the illustrated embodiment the auxiliary structure440also separates the field stop layer128and the pedestal region130from the glass structure450.

The auxiliary structure440may be a homogeneous structure or may include two or more auxiliary layers with vertical interfaces. For example, the auxiliary structure440may include a first and a second auxiliary layer. One of the auxiliary layers may provide a moisture passivation and another auxiliary layer may be effective as a gettering layer and/or as an adhesive layer. The auxiliary layers may be conformally deposited and may have uniform thickness, respectively. One of the auxiliary layers may be a silicon nitride layer having a thickness of at least 10 nm. Another auxiliary layer may be a BPSG (boron phosphorus silicate glass) layer having a thickness of at least 10 nm. Other embodiments of the auxiliary layers include doped and undoped silicon oxide layers, carbon layers, diamond-like carbon layers, aluminum oxide layers, high-k dielectric layers, and low-k dielectric layers.

The glass structure450may result from a glass molding process using a source material like, e.g. soda-lime glass, undoped silica, or silica containing at least one dopant selected from a group comprising boron, sodium, calcium, potassium, and aluminum. According to an embodiment, the glass structure450may be bonded to the semiconductor body100along an interface with the pedestal structure130. The edge termination structure400may fill a step formed in the stepped edge surface103completely and without voids.

A first load electrode310is arranged at a first side facing the first surface101and directly adjoins the first surface101, a face surface of the auxiliary structure440parallel to the first surface101and at least a portion of the glass structure450directly adjoining the auxiliary structure440. According to an embodiment, an overlap between the first load electrode310and the edge termination structure400is at least 1% of the vertical extension of the semiconductor body100, for example at least 5% or 10%.

A second load electrode320directly adjoins the second surface102. In the illustrated embodiment the first load electrode310forms an anode electrode which may form or which may be electrically connected or coupled to an anode terminal A of the semiconductor device500. The second load electrode320forms a cathode electrode that may be electrically connected or coupled to a cathode terminal K.

Each of the first and second load electrodes310,320may consist of or contain, as main constituent(s) heavily doped polycrystalline silicon, molybdenum (Mo), aluminum (Al), copper (Cu) or alloys of aluminum or copper, for example AlSi, AlCu or AlSiCu. According to other embodiments, at least one of the first and second load electrodes310,320may contain, as main constituent(s), nickel (Ni), vanadium (V), molybdenum (Mo), titanium (Ti), tungsten (W), silver (Ag), gold (Au), platinum (Pt), and/or palladium (Pd). For example, at least one of the first and second load electrodes310,320may include two or more sub-layers, wherein each sub-layer contains one or more of Ni, V, Mo, Ti, Ag, Au, Pt, W, and Pd as main constituent(s), e.g. a silicide, a nitride and/or an alloy.

A passivation layer410may cover the first load electrode310such that the first load electrode310is embedded between the passivation layer410, the semiconductor body100and the edge termination structure400. The passivation layer410may be a homogeneous layer or may include two or more sub-layers of different materials. According to an embodiment the passivation layer410consists of or includes hard dielectric layers, e.g., a silicon oxide layer, a silicon nitride layer and/or a silicon oxynitride layer.

A protection layer420may completely cover the passivation layer410. The protection layer420and the edge termination structure400may form an outward step such that the protection layer420does not reach an outer surface104of the edge termination structure400. The material of the protection layer420may be a dielectric material having a smaller Young's modulus than the material of the passivation layer410. According to an embodiment, the dielectric material of the protection layer420may be a polymer, for example polyimide, benzocyclobutene, polynorbornene, polystyrene, polycarbonate, parylene, epoxy resin, polybenzoxazole or a mixture therefrom.

The semiconductor device500may be mounted on a support component600, e.g., a conductive lead frame, a DBC (direct bonded copper) or a PCB (printed circuit board). For example, the second load electrode320may be soldered or glued onto a surface of the support component600. At least one of the conductive structures connected to the second surface102, e.g., the second load electrode320or the support component600may project beyond the edge surface103of the semiconductor body100. The edge termination structure400supports an additional electric field component between the first and second load electrodes310,320outside the semiconductor body100resulting from the projecting portions of the second load electrode320and/or the support component600and prevents a critical field enhancement at an outer edge of the anode region115.

The vertical extension of the edge termination structure400is at least 20 μm, for example at least 50 μm or at least 100 μm. A lateral width of the edge termination structure400is at least 2 μm, for example at least 20 μm or at least 50 μm. Other than organic dielectric materials, the glass structure450provides high mechanical and thermal robustness and prevents an outer edge of the semiconductor body100from mechanical damages, for example cracks, and mechanical strain which may degrade the blocking capabilities of the semiconductor device500. The vertical extension of the edge termination structure400is easily scalable from 2 μm up to several 100 μm.

Other than spin-on-glasses, the glass structure450resulting from glass molding as described above does not contain organic components like hydrocarbon compounds which are detectable in probes of spin-on-glass, e.g., by SIMS (secondary ion mass spectrometry). The glass structure450can be mechanically connected with silicon-containing structures like the semiconductor body100and the auxiliary structure440in a form-fitting and force-fitting manner such that no gaps occur between the edge termination structure400including the glass structure450, and the semiconductor body100along the horizontal interface with the pedestal structure130. The glass structure450may be in-situ bonded to the semiconductor body100.

The edge termination structure400is mechanically robust, suppresses the occurrence of field peaks along the outer edge of the anode regions115and prevents the degradation of the blocking capabilities caused by crystal lattice disturbances and impurities along the edge surface103.

The glass structure450in the edge termination structure450further protects the semiconductor body100against contact with solder materials used, for example, to solder the semiconductor die onto a support component. In the conductive mode a portion of the semiconductor body100between the edge termination structure400and the second load electrode320mainly remains devoid of a charge carrier plasma such that the edge termination structure400intrinsically embodies a high dynamic robustness concept.

With respect to lateral edge termination concepts, the vertical edge termination structure400saves chip area. The edge termination structure400including the glass structure450as well as the overlapping first load electrode310are easily scalable for semiconductor devices500specified for different voltage classes.

InFIG. 1Bthe edge termination structure400extends at least from a plane which is coplanar with the first surface101to a plane which is coplanar with the second surface102. The second load electrode320directly adjoins the edge termination structure400. A slope angle α between the perpendicular to the first surface101and the edge surface103may be between −60 and +60 degree. As regards further details reference is made to the description ofFIG. 1A.

The edge surface103of the semiconductor device500inFIG. 1Cincludes a horizontal portion103bparallel to the first surface101and non-horizontal portions103a,103cconnecting the horizontal portion103bwith the first and the second surfaces101,102. According to the illustrated embodiment, the non-horizontal portions103a,103care approximately vertical. An outer edge104of the edge termination structure400may be flush with an outer edge of the outer one of the non-horizontal sections103a,103c. The edge termination structure400may fill a step formed in the stepped edge surface103completely and without voids. In the blocking mode, equipotential lines exit from the semiconductor body100exclusively along the protected non-horizontal section103a.

FIG. 1Dillustrates an embodiment with stepped edge surface103and a sloped non-horizontal portion103abetween the first surface101and a horizontal portion103b.

The semiconductor devices500ofFIGS. 2A and 2Bare IGFETs with the semiconductor bodies100including trench structures with gate electrodes150and gate dielectrics155insulating the gate electrodes150from body regions115aof the second conductivity type. The trench structures may further include field electrodes160and field dielectrics170insulating them from the semiconductor material of the semiconductor body100as well as from the gate electrodes150. Lateral cross-sectional areas of the trench structures may be circles, ovals or rectangles with or without rounded corners or stripes. According to other embodiments, the trench structures may be stripes. The trench structures may taper with increasing distance to the first surface101, may have rounded or edged bottom portions and straight or bulgy sidewalls. The semiconductor device500may include trench structures of different vertical and/or lateral dimensions.

InFIG. 2Aa termination region115zof the second conductivity type extends in the semiconductor body100along at least a portion of the first surface101between the outermost trench structure and the edge termination structure400. InFIG. 2Bthe termination region115zis absent and a portion of the drift zone120adjoins the first surface101between the outermost trench structure and the edge termination structure400.

A dielectric structure220may be formed between the first load electrode310and the first surface101, wherein contact structures305extend through openings in the dielectric structure220between the first load electrode310and the semiconductor body100. The contact structures305may extend into the semiconductor body100and may directly adjoin the body regions115aas well as source regions110of the first conductivity type, which may be formed along the first surface101and which the body regions115aseparate from the drift zone120. The thicker the dielectric structure220is the more a field plate, which is embodied by a portion of the first load electrode310, overlaps with the glass structure450.

The first load electrode310is effective as a source electrode which may be or which may be electrically coupled or connected to a source terminal S. The second load electrode320may form a drain electrode, which may be or which may be electrically coupled or connected to a drain terminal D. For further details, reference is made to the description ofFIGS. 1A to 1D.

The first load electrode310is an emitter electrode which may be or which may be electrically connected or coupled to an emitter terminal E. The second load electrode320is a collector electrode which may be or which may be electrically connected or coupled to a collector terminal C. The pedestal region130is a collector layer that may have the second conductivity type or that may include zones of both conductivity types.

The IGBTs may include trench structures including gate electrodes150and gate dielectrics155dielectrically insulating the gate electrodes150from body regions115aof the second conductivity type. The body regions115aseparate source regions110of the first conductivity type and formed along the first surface101from the drift zone120. Some or all of the trench structures may include gate electrodes and some trench structures may include field electrodes or floating electrodes. For further details, for example as regards the trench structures, reference is made to the description ofFIGS. 1A and 1Das well asFIGS. 2A to 2B.

FIG. 4Aschematically shows an edge termination structure400of a semiconductor diode501mounted on an electrically conducting support component600projecting beyond a vertical edge surface103of a semiconductor body100. In addition to the vertical field lines within the semiconductor body100further field lines exiting from the projecting portion of the support component600enter the semiconductor body100in a portion of the edge surface103around a pn junction between a drift zone120and an anode region115in the semiconductor body100. The electric field strength is locally increased and may result in a local breakdown.

FIG. 4Bshows the equipotential lines for a comparative example of a semiconductor diode502with the first load electrode310not protruding beyond a vertical edge surface103of the semiconductor body100as well as a second load electrode320projecting beyond an edge surface103. In the semiconductor body100the equipotential lines are bowed and denser in a region where the pn junction meets the edge surface103.

By contrast, the semiconductor diode503ofFIG. 4Cincludes a first load electrode310that projects beyond the edge surface103and partially overlaps the adjoining edge termination structure400. The equipotential lines are disturbed only within the edge termination structure400that can support a higher electric field strength without breaking through. Within the semiconductor body100the equipotential lines are parallel to each other and the electric field strength is not locally increased within the semiconductor body100.

FIG. 5Ashows a base substrate100awith a frame trench400aextending from a first surface101into the base substrate100a. The glass piece450aon the right-hand side is obtained by glass molding including pressing a source material onto the first surface101of the base substrate100asuch that the source material fluidifies, flows into the frame trench400aand re-solidifies after filling the frame trench400acompletely.

FIG. 5Bshows a frame trench400awith a width of approximately 50 μm and a depth of approximately 100 μm. A source material is brought into contact with the first surface101aof the base substrate100a, and pressed against the base substrate100aat a temperature at which the source material fluidifies. After re-solidifying, a glass structure450afills the upper portion of the frame trench400aand leaves a void451in a lower portion of the frame trench400a.FIG. 5Cshows the same frame trench400aafter a press capacity (force) has been exerted sufficiently long. A glass structure450bfills the frame trench400acompletely with no void between the base substrate100aand the glass structure450b.

FIGS. 6A to 6Nrefer to a method of manufacturing semiconductor devices with a vertical edge termination structure as discussed above. A first sacrificial layer612is formed on a first surface101of a base substrate100a. The base substrate100ais a single-crystalline semiconductor material, e.g., silicon (Si), germanium (Ge), silicon germanium crystal (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN) or another AIIIBVsemiconductor and may contain impurities of a first conductivity type. According to an embodiment, the base substrate100ais a silicon wafer with a thickness of, for example, 600 to 800 μm.

The first sacrificial layer612may be a semiconductor oxide, e.g., a silicon oxide grown by thermal oxidation on the first surface101. A first mask layer614may be deposited on the first sacrificial layer612. The first mask layer614may be provided from a material against which the materials of the first sacrificial layer612and the base substrate100amay be etched with high selectivity. According to an embodiment the first mask layer614is a silicon nitride layer deposited from the gaseous phase using CVD (chemical vapor deposition). Impurities of a second conductivity type opposite to the first conductivity type may be implanted through the first surface101into a portion of the base substrate100aoriented to the first surface101. According to the illustrated embodiment, the first conductivity type is the n-type and the second conductivity type the p-type, wherein the implanted impurities may be boron, aluminum, gallium and/or indium atoms/ions, by way of example. According to other embodiments, the base substrate100amay have the p-type and n-type impurities are implanted through the first surface101.

FIG. 6Ashows the first mask layer614deposited on the first sacrificial layer612which together form a hard mask610on the first surface101of the base substrate100a. In the base substrate100aa p-type impurity region along the first surface101forms an anode layer115xand the remaining n-type portion forms a drift layer120a. A pn junction between the anode and drift layers115x,120aextends parallel to the first surface101. An impurity concentration of the p-type impurities may depend from the diffusion depth reached during thermal diffusion, wherein the area dose may be in a range from 2E12 cm−2to 5E13 cm−2.

In regions assigned to active areas of semiconductor devices device-specific processes may be performed during which the illustrated edge regions remain covered by the hard mask610. For example, in the active areas the hard mask may be used to form transistor cells including gate electrodes formed in trench structures extending from the first surface101into the base substrate100a. Further implants of the first conductivity type may provide source zones along the first surface101.

Before providing a front side metallization layer or, if applicable, an intermediate dielectric on the first surface101, the formation of a vertical edge termination structure may be initiated, for example by locally opening the hard mask610. Since a plurality of identical semiconductor devices are formed from one single base substrate100a, the opening forms a grid with the active areas of the semiconductor devices formed in the meshes of the grid. A photoresist layer is deposited, partially exposed using a photolithographic mask and developed. The developed photoresist layer forms an etch mask for transferring the pattern from the photoresist layer into the hard mask610by using wet etch or plasma etch processes to form a patterned hard mask from the hard mask610.

An isotropic or anisotropic dry or wet etch process forms a frame trench400ain the base substrate100a, wherein openings in the patterned hard mask define position and width of the frame trench400a. The etch process may be based on an alkaline solution like KOH (potassium hydroxide) or TMAH (tetramethyl ammonium hydroxide), which may contain modifications and additives like surfactants, dissolved gases and the like. According to an embodiment, wet etch processes are used that prevent crystal defects along the sidewalls of the frame trench400a. If applicable, a further selective wet etch may remove portions of the patterned hard mask projecting beyond the edges of the frame trench400a. Impurities may be introduced through the sidewalls of the frame trench400, for example using an implantation which is tilted against the vertical direction by, for example at least 5 degree and at most 85 degree. A LOCOS (local oxidation of silicon) process may locally oxidize exposed portions of the base substrate100a. The local oxidation may be combined with a heating process for activating the implant for the anode layer115a. In the frame trench400athe locally generated oxide layer forms a first auxiliary layer441. According to other embodiments, instead of or in addition to the local oxidation, other dielectric materials may be deposited, for example a nitride, a CVD oxide or semi-insulating layers from amorphous or polycrystalline materials like amorphous silicon (a-Si), amorphous carbon hydrogen (a-C:H) or a plurality of layers.

FIG. 6Bshows the frame trench400aextending from the first surface101into the base substrate100athrough the segmented anode layer115a. Remnants of the first mask layer614may be removed. The first sacrificial layer612covers the first surface101and the first auxiliary layer441covers sidewalls and the bottom portion of the frame trench400a. The depth of the frame trench400adepends on a blocking voltage for which the finalized semiconductor devices are specified. For example, in semiconductor devices specified for a blocking voltage of 1200 V, the depth of the frame trench400amay be at least 100 μm, for example at least 120 μm. The width of the frame trench400amay be between 10 and 200 μm, by way of example. The first auxiliary layer441may be or may include a contamination barrier or may form an adhesive interface with the following layers.

Atoms/ions which are effective as recombination centers may be introduced through the first surface101, for example platinum (Pt) or gold (Au). Also crystal lattice damage by e.g. helium (He) or hydrogen (H) implantation can act recombinative. A deposition method, e.g., CVD deposits a stop layer442athat may line a front side of the semiconductor substrate500aoriented to the first surface101in a conformal manner. The stop layer442amay be a silicon nitride layer, by way of example. If applicable, atoms/ions effective as recombination center may be introduced through a process surface102aaverted from the front side.

A source material is brought into contact with the front surface of the semiconductor substrate500adefined by the first surface101. The source material exhibits a glass transition and fluidifies when the temperature of the source material exceeds the glass transition temperature. The source material may be soda-lime glass with a glass transition temperature above 400 degree Celsius, undoped silica, silica doped with at least one dopant, the dopant(s) selected from a group containing boron B, sodium Na, calcium Ca, potassium K, lead Pb, and aluminum Al. The source material may be a flat glass piece, e.g. a glass disc with a flat surface. According to other embodiments, the source material may be a glass piece with preformed protrusions approximately complementary to the frame trench400a. A press capacity (force) is exerted to press the source material and the semiconductor substrate500aagainst each other. Press capacity and temperature of the source material are controlled to exceed the glass transition temperature in the course of pressing. The source material fluidifies and the fluidified source material flows into the frame trench400a. A process time is selected such that the source material fills the frame trench400acompletely. Then, the press capacity and the temperature of the source material are controlled in a way that the fluidified source material re-solidifies.

FIG. 6Cshows a re-solidified glass piece450aresulting from the glass molding. A portion of the glass piece450afills the frame trench400acompletely. The glass piece450acan be mechanically connected with silicon-containing structures in a form-fitting and force-fitting manner, wherein no gaps remain between the glass piece450aincluding the glass structure450and the base substrate100a. The glass piece450amay be in-situ bonded to the stop layer442awhich may be effective as an adhesive interface. The glass piece450aand the base substrate100amay form a laminate or a bonded composite after re-solidifying of the source material. Other than organic dielectrics based on polymers like BCB or imides the insulator characteristics of the glass piece450aare long-time stable and reliable.

The formation of the glass piece450amay get along without high temperature processes above 600 degree Celsius. Other than methods like spin-on, stencil-print or inkjet print, glass molding fills wide and deep trenches at high quality without voids. The thermal expansion coefficient may be adjusted using suitable dopants in the glass piece450a.

A thinning process including grinding, polishing and/or, etching, for example, spin-etch or CMP (chemical mechanical polishing), removes portions of the glass piece450aoutside the frame trench400a, wherein the exposure of portions of the stop layer442amay terminate the thinning process. For example, the exposure of the stop layer442amay deliver an optical stop signal or the stop layer442ais robust against the thinning process and impacts the thinning process in a way that the exposure of the stop layer442acan be detected by monitoring a process parameter.

FIG. 6Dshows a remaining glass structure450filling the frame trench400a. Outside the frame trench400aportions of the stop layer442aare exposed. The portions of the stop layer442aoutside the frame trench400as well as the first sacrificial layer612may be removed at high material selectivity, for example using an appropriate wet etch solution.

FIG. 6Eshows the first sacrificial layer612exposed by removal of the portions of the stop layer442aoutside the frame trench400a. Within the frame trench400aremaining portions of the stop layer442amay form a second auxiliary layer442.

FIG. 6Fshows the semiconductor substrate500awith exposed first surface sections101after removal of the first sacrificial layer612.

An interlayer dielectric may be deposited on the first surface101and above the glass structure450. If applicable, remnant portions of the first sacrificial layer612may be part of the interface dielectric. A front metallization layer is formed on the front side of the semiconductor substrate500a, e.g., by using a galvanic deposition process that may use a lithography step effective on a seed layer or by PVD (physical vapor deposition), for example vapor deposition or sputtering, wherein the deposited front metallization layer is patterned by lithography to form a front metallization with openings470above the glass structures450.

A passivation layer410amay be deposited that covers the front metallization and that lines the opening470. The passivation layer410amay be a dielectric passivation layer. A protection layer420amay be deposited on the passivation layer410a.

FIG. 6Gshows the front metallization forming first load electrodes310. The passivation layer410acovers the first load electrodes310and a portion of the glass structure450. The material of the passivation layer410amay be a hard dielectric such as silicon oxide, silicon nitride or silicon oxynitride. The passivation layer410amay be a homogeneous layer or may include two or more different sub-layers. The material(s) of the protection layer420acovering the passivation layer410amay include polymers, for example a polyimide, benzocyclobutene or polybenzoxazole.

A further lithographic process defines a frame opening480through the protection layer420aand the passivation layer410aover and within the opening470between the first load electrodes310. The process may be combined with exposing bond pad areas of the first load electrodes310.

The lithography process may include plasma and/or wet etch processes. The mask for the frame opening480in the passivation and protection layers410a,420amay be adjusted by detecting the slopes421of the protection layer420along the edges of the glass structure450or the edges of specific additional adjustment features.

FIG. 6Hshows the frame opening480separating the deposited protection and passivation layers420a,410ainto separated protection and passivation layers420,410. The frame opening480is aligned to the opening470separating the first load electrodes310. A carrier490may be mounted onto the front side of the semiconductor substrate500a.

FIG. 6Ishows the carrier490which may include an adhesive layer and a main portion. The main portion may be a rigid carrier, e.g., a glass plate, or a grinding tape. The adhesive layer could be deposited separately or in combination with the main portion. The carrier490mechanically stabilizes the semiconductor substrate500aand protects the front side during the following processes.

A thinning or grinding process that may or may not include etch processes and chemical mechanical polishing processes thins the base substrate100afrom a process surface102aat a rear side of the semiconductor substrate500aopposite to the front side. The thinning process may be controlled to stop immediately at or with a time lag after detection of the buried edge of the first auxiliary layer441, or the buried edge of the second auxiliary layer442or the buried edge of the glass structure450, respectively.

According to the embodiment illustrated inFIG. 6Jthe thinning process removes portions of the base substrate100abelow the buried edge of the glass structure450and exposes a working surface102bopposite to the first surface101.

A deposition process, for example, a physical sputter process may deposit an amorphous silicon layer on the working surface102b. According to other embodiments, a metal or a patterned reflex layer may be deposited on the working surface102b.

FIG. 6Kshows the deposited amorphous pedestal layer130aforming an amended portion of the base substrate100a.

An anneal, for example an LTA (laser thermal anneal) may transform the amorphous pedestal layer130aofFIG. 6Kinto a crystalline pedestal layer130bwhose crystal lattice may grow in registry with the crystal lattice of the base substrate100a. A patterned reflex layer may represent an optic barrier for the laser illumination. Alternatively, the laser exposure may be patterned for local activation. N-type impurities, for example phosphorus atoms/ions may be introduced from the exposed surface of the crystalline pedestal layer130b, for example through implants at one, two or more implant energies. Outdiffusion of the implants may be controlled, at least partly by the LTA from the rear side.

FIG. 6Lshows the crystalline pedestal layer130b, which for IGFETs and diodes has the first conductivity type and which for IGBTs may have the second conductivity type, or, for RC-IGBTs (reverse conducting IGBTs) and some diode types, e.g. MCDs (MOS controlled diode) may have zones of both the first and second conductivity types. The outdiffused impurities may also form a field stop layer128. According to other embodiments, the field stop layer128may be formed by implanting impurities, e.g., protons.

Proceeding withFIG. 6M, the carrier490may be removed from the semiconductor substrate500aand a rear metallization layer320amay be deposited, for example, sputtered onto the exposed surface of the crystalline pedestal layer130b. The carrier490may be removed before or after the deposition of the rear metallization layer320a.

A separation process divides the semiconductor substrate500aofFIG. 6Minto a plurality of identical semiconductor dies509as illustrated inFIG. 6N, each with a semiconductor body100including an anode region115along the first surface101, a pedestal region130along the second surface102, a drift zone120forming a pn junction with the anode region115and a field stop layer128separating the drift zone120from the pedestal region130. The separation process may be performed with the carrier490still attached to the semiconductor substrate500aofFIG. 6Mor after attaching a further carrier, e.g. a dicing frame including a tape, on the rear side at the second surface102of the semiconductor substrate500a.

A portion of an outer surface104of the semiconductor die509along which equipotential lines leave the semiconductor die509in a blocking mode is formed by a portion of the glass structure450. The glass structures450passivate and protect the sidewalls of the semiconductor bodies100. In addition the sidewall of the semiconductor body100is not formed by sawing or another mechanical process locally damaging the crystal lattice.