Memory system with read and write caches and method of controlling memory system with read and write caches

A controller sets, out of a data range that is specified in a read request from a host device, a predetermined size of a first data range that follows a top portion of the data range and a predetermined size of a second data range that follows the first data range, and after transfer, to the host device, of data corresponding to the first data range from a second storage unit or a third storage unit having smaller data output latency than the first storage unit in which read/write of data is performed is started, the controller searches for data corresponding to the second data range in the second storage unit or the third storage unit.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-335504, filed on Dec. 27, 2008; the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a memory system having a nonvolatile semiconductor memory and a controller.

2. Description of the Related Art

Data storage apparatuses (memory systems) include a data storage medium, a host device, and a control device that performs transmission and reception of data between the host device and the data storage medium. In such a data storage apparatus, by providing a cache memory (a read cache function) that can be accessed quicker than the data storage medium, access performance from the host device is enhanced.

In a data storage apparatus having a cache memory, by using a prefetch function for data in the data storage medium when a sequential read request is received from the host device, the access performance is enhanced.

The prefetch function for data is a function of reading data in a sequential area (a subsequent area) from the data storage medium into the cache memory in advance when a read request issued from the host device has sequentiality. The sequentiality represents that a read request with respect to a subsequent data area is to be issued in sequence. When a read request having sequentiality is issued from the host device and the prefetch of data is to be performed, data in the sequential subsequent area for which a read request is expected to be issued is read from the data storage medium into the cache memory in advance prior to reception of a read request therefor from the host device.

A data storage medium described in Japanese Patent Laid-open No. 2007-241927 determines that a read request has sequentiality when the transfer size of a read request from a host computer is equal to a prefetch determination size set in advance, and prefetches, while transmitting data requested by the read request to the host computer, data in a subsequent storage area that continues from the data corresponding to the read request from a storage device to a cache memory.

However, in the technique disclosed in Japanese Patent Laid-open No. 2007-241927, there is a problem that it takes a long time to read data by the host device as a result of late start of data transfer to the host device, because it takes a long time for a search process to determine whether requested data is stored in the cache memory. Such a problem also occurs in a solid state drive (SSD) on which a nonvolatile semiconductor memory such as a NAND flash memory is mounted. Specifically, in an SSD that is configured to read data at a high speed from a flash memory by providing a cache memory between the flash memory and a host device, it takes a long time for a searching process to determine whether data for which a data request has been issued by the host device is stored in the cache memory, and therefore, it takes a long time for the host device to read data.

BRIEF SUMMARY OF THE INVENTION

A memory system according to an embodiment of the present invention comprises: a first storage unit that is constituted by a nonvolatile semiconductor storage device in which reading and writing of data is performed; a second storage unit that is constituted by a semiconductor storage device having smaller data output latency than the nonvolatile semiconductor storage device; a third storage unit that is constituted by a semiconductor storage device having smaller data output latency than the nonvolatile semiconductor storage device; and a controller that writes data for which a write request has been issued by a host device in the first storage unit through the second storage unit, and that transfers data for which a read request has been issued to the host device by reading from any one of the second storage unit and the third storage unit, or by reading from the first storage unit through the third storage unit, wherein the controller sets, out of a data range that is specified in a read request from the host device, a predetermined size of a data range that follows a top portion of the data range as a first data range, sets a predetermined size of a data range that follows the first data range as a second data range, and searches for data corresponding to the second data range in any one of the second storage unit and the third storage unit after transfer of data corresponding to the first data range from any one of the second storage unit and the third storage unit to the host device is started.

A controller according to an embodiment of the present invention comprises: a control unit that controls a first storage unit that is constituted by a nonvolatile semiconductor storage device in which reading and writing of data is performed, a second storage unit that is constituted by a semiconductor storage device having smaller data output latency than the nonvolatile semiconductor storage device, a third storage unit that is constituted by a semiconductor storage device having smaller data output latency than the nonvolatile semiconductor storage device, wherein the control unit writes data for which a write request has been issued by a host device in the first storage device through the second storage unit, and transfers data for which a read request has been issued to the host device by reading from any one of the second storage unit and the third storage unit, or by reading from the first storage unit through the third storage unit, and sets, out of a data range that is specified in a read request from the host device, a predetermined size of a data range that follows a top portion of the data range as a first data range, sets a predetermined size of a data range that follows the first data range as a second data range, and searches for data corresponding to the second data range in any one of the second storage unit and the third storage unit after transfer of data corresponding to the first data range from any one of the second storage unit and the third storage unit to the host device is started.

DETAILED DESCRIPTION OF THE INVENTION

Exemplary embodiments of a memory system and a controller according to the present invention will be explained below in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments. In the following descriptions, constituent elements having the same function or configuration are denoted by like reference numerals and explanations thereof will be omitted.

FIG. 1is a block diagram of a configuration example of an SSD according to an embodiment of the present invention. An SSD1is a semiconductor storage device (a memory system) that is connected to a host device6such as a personal computer and a central processing unit (CPU) core, and that functions as an external memory of the host device6.

The SSD1includes a host interface (I/F)2that is an interface for memory connection, a dynamic random access memory (DRAM)3serving as a volatile semiconductor memory, a NAND flash (a NAND memory)4serving as a nonvolatile semiconductor memory, and a controller (a drive control circuit)5. The SSD1is connected to the host device6through the host I/F2, and performs data communication with the host device6. The host device6writes data in the SSD1and reads data from the SSD1.

The NAND flash is constituted by a plurality of stacked NAND memory chips (for example, 1 chip=2 GB). The NAND flash (a first storage unit)4stores, in a data storage area12, data that is temporarily stored in the DRAM3and provided by the host device6. The data storage area12has a plurality of blocks that are the smallest units for deleting data in the NAND flash4. The NAND flash4stores an address conversion table13(a management table9) described later together with the data provided by the host device6.

The DRAM3functions as a cache for data transfer between the host device6and the NAND flash4and a memory for a work area. A storage area of the DRAM3is divided into a write cache (WC)7and a read cache (RC)8. Furthermore, the DRAM3stores the management table9in the work area. The WC (a second storage unit)7temporarily stores data written by the host device6and the RC (a third storage unit)8temporarily stores data read from the NAND flash4. The WC7and the RC8can use a storage area in an identical memory chip in common, or can be constituted by separate memory chips. The WC7is constituted by a volatile semiconductor storage device to which data is written at a higher speed than to the NAND flash4, and the RC8is constituted by a volatile semiconductor storage device from which data is read at a higher speed than from the NAND flash4.

The DRAM3temporarily stores the address conversion table13that is read from the NAND flash4as the management table9when the SSD1is active. The address conversion table13is read from the NAND flash4to the DRAM3at the time of the initialization of the SSD1to be used.

The address conversion table13is an information table that indicates association between a logical address and a physical address of data to be written/read with respect to the SSD1, and is used when conversion between a logical address and a physical address is performed. The logical address is a logical address that is assigned by the host device6when the host device6writes/reads data to and from the SSD1, and is input from the host device6to the SSD1as logical block addressing (LBA).

The address conversion table13is present only in the NAND flash4when an operation of the SSD1is stopped, while the address conversion table13is read to the DRAM3as the management table9to be used. When writing/reading of data with respect to the SSD1is instructed by the host device6, contents of the management table9on the DRAM3is updated. The management table9is written in the NAND flash4at a predetermined timing, to avoid loss of the contents due to power cut or the like.

The controller5controls transfer of data between the host device6and the NAND flash4through the DRAM3, and controls the respective components of the SSD1. The controller5includes a CPU (not shown), and controls the SSD1by commands executed by the CPU. The CPU of the controller5includes a write control unit11and a read control unit10. In practice, a computer program (a write/read control program) executed by the CPU is a module including the write control unit11and the read control unit10. The write/read control program is read from a ROM (not shown) or the like and executed by the CPU, thereby implementing the write control unit11and the read control unit10in the CPU.

The write control unit11controls writing of data to the WC7from the host device6and writing of data to the NAND flash4from the WC7according to a request from the host device6. When writing of data to the NAND flash4from the WC7is performed, data in the RC8at an identical logical address is nullified. The read control unit10controls reading of data from the NAND flash4to the RC8and data transfer from the RC8or the WC7to the host device6according to a request from the host device6. The data in the RC8is one read from the NAND flash4and temporarily stored therein. When data is written at the same logical address as that of the data in the RC8from the host, the written data is the latest data, and is stored in the WC7. Accordingly, when data corresponding to the identical logical address is present in the WC7, the RC8, and the NAND flash4, the order of newness of the data is as the WC7, the RC8, and the NAND flash4, and therefore, the data in the WC7takes precedence for data to be returned to the host.

The controller5converts a logical address of data provided by the host device6into a physical address at which the data is actually stored in the NAND flash4. Specifically, the controller5records, when data provided by the host device6is stored in the NAND flash4, the external address of the data and the physical address of the data at which the data is stored in the NAND flash4in association in the management table9(the address conversion table13). Upon reception of a read request from the host device6, the controller5converts the logical address in the read request into the physical address that corresponds to the logical address, using the management table9. Specifically, the address conversion is performed by converting an upper portion (several bits) of the logical address (LBA) provided by the host device6into a page position in blocks in the NAND flash4, and converting the remaining lower portion (several bits) into a data position in a page.

The controller5updates addresses in the address conversion table13that is temporarily stored in the DRAM3corresponding to reading/writing of data with respect to the NAND flash4. The update of the address conversion table13in the NAND flash4is performed at an arbitrary timing such as when the SSD1stops the operation.

Although in the example shown inFIG. 1, the DRAM3is used as the cache for data transfer, another memory having less latency than the NAND flash4can be used instead of the DRAM3. For example, instead of the NAND flash4, a ferroelectric RAM (FeRAM) can be used. The cache for data transfer is not necessarily required to be constituted by a volatile semiconductor memory, and can be constituted by a nonvolatile semiconductor memory. If the cache for data transfer is constituted by a nonvolatile semiconductor memory, the address conversion table13is not necessarily required to be stored in the NAND flash4.

Next, an operation of the SSD according to the embodiment is explained.FIG. 2is a flowchart of the operation of the SSD according to the embodiment.FIG. 3is a schematic diagram for explaining the operation of the SSD. Procedures of a data search process, a data read process from the NAND flash4, and a data transfer process to the host device6are explained below.

When a data read request is sent to the SSD1from the host device6, the SSD1receives this read request through the host I/F2(Step S10). The read request sent from the host device6includes a requested transfer range X of data. The requested transfer range X indicates a range of data that is requested to be read by a start logical address of data requested to be read (read request data) and a transfer size, for example.

In the requested transfer range X, the read control unit10of the controller5checks whether a predetermined size of data at top is present in the RC8in sequence from the top, referring to the management table9. The requested transfer range X is a range of data for which the read request is issued, and can be divided into a first part A (data range having a size α) that is a first data range, and a second part B that is a second data range. The first part A indicates a data range of the first part in the requested transfer range X, and the second part B indicates a data range of the second part following the first part A. In the present embodiment, the read control unit10divides a range of data requested to be read by the host device6into a first part and a second part having a predetermined size. In other words, the read control unit10sets the first part in a predetermined size and the second part in a predetermined size in the range of data requested to be read by the host device6. Out of the first part A, a top portion a is the first area of the data range indicated by the requested transfer range X, and out of the second part B, a top portion b is the first data area in the second part B. The read control unit10searches for sequential data from the top portion a in the first part A out of the requested transfer range X in the RC8(Step S20). When it is present in the RC8, the size of the top portion a is the size of the sequential data from the top of the first part A found in the RC8.

When the data of the top portion a is present in the RC8(YES at Step S20), the read control unit10searches for the data present in the RC8in the WC7(Step S30). The search in the WC7is a process required to transfer the latest data written by the host device6as data requested to be read. The read control unit10starts transferring data that is present in the WC7from the WC7, data not present in the WC7from the RC8, to the host device6. Furthermore, the read control unit10deletes a data range for which transfer to the host device6has been started, that is the size of the top portion a, from the remaining transfer range (Step S40). The remaining transfer range is a data range for which transfer to the host device6has not been started out of the requested transfer range X.

The size of the data that is found in the RC8as the top portion a and the size of the first part A are compared to determine whether the sizes are equal to each other. In other words, the read control unit10determines whether the entire part of the first part A (entire data range) is present in the RC8referring to the management table9(Step S50). When the entire part of the first part A is present in the RC8(YES at Step S50), the read control unit10transfers the data from the WC7as for the data present in the WC7, and from the RC8as for the data not present in the WC7, to the host device6. The read control unit10then deletes a data range for which transfer to the host device6has been started from the remaining transfer range. Thus, the remaining transfer range corresponds to a data range of the second part B. The processes at Steps S20and S30correspond to a process of (1) inFIG. 3, and the process at Step S40corresponds to a process of (2) inFIG. 3.

After data transfer of the first part A to the host device6is started, the read control unit10searches for sequential data from the top portion b in the RC8out of the second part B, which is the remaining transfer range, referring to the management table9(Step S60). When the data of the top portion b is present in the RC8(YES at Step S60), the size of the top portion b corresponds to the size of the sequential data from the top of the second part B found in the RC8, and the read control unit10searches the data of the top portion b present in the RC8in the WC7(Step S70). The read control unit10starts transferring the data to the host device6from the WC7as for the data present in the WC7, and from the RC8as for the data not present in the WC7. Moreover, the read control unit10deletes a data range for which transfer to the host device6has been started, that is the size of the top portion b, from the remaining transfer range (Step S80). The processes at Steps S60and S70correspond to a process of (3) inFIG. 3, and the process at Step S80corresponds to a process of (4) inFIG. 3.

The read control unit10determines whether the remaining transfer range is larger than 0 (Step S90). In other words, the read control unit10determines whether data that is not present in the RC8is present out of data specified by the requested transfer range X, referring to the management table9. Thus, the read control unit10determines whether data that has not been found in the RC8is present.

When the remaining transfer range is larger than 0 (YES at Step S90), the read control unit10starts reading data corresponding to the remaining transfer range from the NAND flash4to the RC8(Step S100). Thereafter, the read control unit10searches the data corresponding to the remaining transfer range in the WC7(Step S110). The read control unit10starts transferring the data to the host device6from the WC7as for the data present in the WC7, and from the NAND flash4as for the data not present in the WC7, upon reading the data therefrom to the RC8(Step S120). Subsequently, all the data corresponding to the remaining transfer range is transferred to the host device6from the WC7or the NAND flash4(the RC8), and the data transfer process is ended. When the remaining transfer range is 0 (NO at Step S90), the read control unit10ends the data transfer process.

Furthermore, when the data of the top portion a is not present in the RC8at Step S20(NO at Step S20), when the entire part of the first part A is not present in the RC8at Step S50(NO at Step S50), and when the data of the top portion b is not present in the RC8at Step S60(NO at Step S60), the read control unit10performs a process of reading data from the NAND flash4(Steps S90to S120).

As described above, in the present embodiment, after data search and data transfer of the first part A are started, the data search process for the second part B is started. This enables to make the first response to the host device6quickly. Furthermore, because data transfer to the host device6has already been started at the time of starting data search for the second part B, a processing time required for following data search can be inconspicuous.

Furthermore, in the present embodiment, when data reading from the NAND flash4is executed for the remaining range, the process of reading data from the NAND flash4to the RC8is started before performing the process of searching data in the WC7. This is because it is important to start reading from the NAND flash4as early as possible since data is rarely read from the WC7and the NAND flash4has large latency in data output. Once reading from the NAND flash4is started, there is no major difference between data transfer to the host device6from the WC7and data transfer to the host device6after reading data from the NAND flash4to the RC8.

Therefore, in the present embodiment, the SSD1starts reading the entire data of the remaining transfer range from the NAND flash4before searching the data in the WC7. Thereafter, the SSD1searches for the remaining transfer range in the WC7, and as for the data that is found in the WC7, the SSD1transfers the data from the WC7to the host device6, and as for the data that is not present in the WC7, the SSD1transfers the data to the host device6from the NAND flash4via the RC8. Thus, data output from the NAND flash4can be performed at an early timing, and response to the host device6can be quick. Furthermore, because the search process of the WC7can be inconspicuously performed with the data output latency of the NAND flash4, and therefore, data transfer to the host device6can be performed at a high speed.

The processing time for data transfer to the host device6is the shortest when a processing time for data search of the second part B and a processing time for data transfer of the first part A are equal to each other. Therefore, the SSD1can perform data transfer to the host device6in such a manner that the processing time for data search of the second part B is equal to the processing time for data transfer of the first part A. In this case, the read control unit10sets the first part A and the second part B such that the processing time for data search of the second part B and the processing time for data transfer of the first part A are equal to each other.

Although in the present embodiment, the case that the requested transfer range X is divided into two parts of the first part A and the second part B, the read control unit10can divide the requested transfer range X into three or more data ranges. For example, the read control unit10divides the requested transfer range X into data ranges of a first line to an nth line (where n is a positive integer equal to or larger than 3). In this case, the read control unit10starts a data search process of the second line after data transfer of the first line is started.

The SSD1according to the present embodiment can be configured to prefetch a predetermined size of data in a logical address range subsequent to a logical address range for which read request is issued in the RC8. In this case, the data prefetched according to the previous read request is already been stored in the RC8at the time of receiving a new read request. Thus, the access performance can be improved for a read request having sequentiality. Furthermore, as a prefetch method, various methods such as those described in U.S. patent application Ser. No. 11/717,072 and U.S. patent application Ser. No. 12/394,692 can be applied to the present embodiment.

As described above, according to the present embodiment, because the data search process of the second part B is started after data transfer of the first part A to the host device6is started, the data transfer to the host device6can be started at an early timing, and as a result, data read can be performed at a high speed.

Furthermore, because reading of data that is not present in the RC8from the NAND flash4is started before searching for the data in the WC7, reading of data from the NAND flash4to the RC8can be performed at an early timing. Therefore, even when data for which read request has been issued is present only in the NAND flash4, data read can be performed at a high speed.