Asymmetric 8-shaped inductor and corresponding switched capacitor array

A semiconductor device includes a substrate; a first terminal and a second terminal; and a conductor arranged on the substrate between the first terminal and the second terminal to constitute an inductor shaped for forming a first loop and a second loop. A first crossing of the conductor with itself is present between the first loop and the second loop. The first loop and the second loop define a first enclosed area and a second enclosed area, respectively. The first enclosed area is smaller than the second enclosed area.

BACKGROUND

This invention relates to integrated circuit inductors, and more particularly to an asymmetric, 8-shaped inductor capable for interference mitigation of inductor-capacitor voltage-controlled oscillators (LC-VCO) and a semiconductor device using the same.

Integrated circuit inductors are essential to realize the voltage-controlled oscillators (VCO) needed in many fully integrated transceiver chips serving a multitude of wireless communication protocols. It is known to form inductors using multiple loops, and with multiple paths per loop. The conductive track is preferably provided on two levels with cross overs between paths of the conductive track.

One approach of reducing mutual electromagnetic coupling between VCO resonators on a single semiconductor chip or die involves using inductors that are substantially symmetrical about their horizontal and/or their vertical axes and providing current to the inductors in a way so that the resulting magnetic field components tend to cancel each other by virtue of the symmetry. In addition, two such inductors may be placed near each other and oriented in a way so that the induced current in the second inductor due to the magnetic field originating from first inductor is significantly reduced. A symmetric, 8-shaped inductor is a commonly implemented method for the on-die inductor.

SUMMARY

It is one object of the present disclosure to provide an improved integrated inductor for mitigating inductor noise coupling and a device using the same.

One aspect of the invention provides a semiconductor device including a substrate; a first terminal and a second terminal; and a conductor arranged on the substrate between the first terminal and the second terminal to constitute an inductor shaped for forming a first loop and a second loop. A first crossing of the conductor with itself is present between the first loop and the second loop. The first loop and the second loop define a first enclosed area and a second enclosed area, respectively. The first enclosed area is smaller than the second enclosed area.

According to some embodiments, the first terminal and a second terminal are two terminals of a switched capacitor array (SCA).

According to some embodiments, the second loop is disposed closer to the SCA and the first loop is disposed farther away from the SCA.

According to some embodiments, the inductor is at least partially surrounded by a ground metal ring.

According to some embodiments, the ground metal ring is constructed at a top metal layer over the substrate.

According to some embodiments, the conductor is provided with a second crossing with itself between the terminals and the second loop.

According to some embodiments, the conductor is further shaped for forming a third loop and a fourth loop, wherein a third crossing of the conductor with itself is present between the third loop and the fourth loop, and wherein the third loop and the fourth loop define a third enclosed area and a fourth enclosed area, respectively, and wherein the fourth enclosed area is greater than the third enclosed area.

According to some embodiments, the conductor is further provided with a fourth crossing with itself connecting the first loop with the third loop thereby further defining the boundaries of the first enclosed area and the third enclosed area.

According to some embodiments, the first loop is connected between the fourth loop and the second loop, the fourth loop is connected between the first loop and the third loop to obtain an 8-shaped structure in series with an 8-shaped structure.

According to some embodiments, the third loop is arranged within the first loop and the fourth loop is arranged within the second loop thereby forming a fifth crossing for further defining the fourth enclosed area, and forming a sixth crossing for further defining the first and second enclosed area, to obtain an 8-within-8 shaped structure.

According to some embodiments, the inductor is part of an inductor-capacitor voltage-controlled oscillator (LC-VCO).

DETAILED DESCRIPTION

In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the disclosure may be practiced.

These embodiments are described in sufficient detail to enable those skilled in the art to practice them, and it is to be understood that other embodiments may be utilized and that mechanical, chemical, electrical, and procedural changes may be made without departing from the spirit and scope of the present disclosure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of embodiments of the present invention is defined only by the appended claims.

As the integration surface on silicon is getting smaller and smaller, interactions among sensitive blocks and electromagnetic (EM) sources (like VCOs) become stronger. An inductor-capacitor voltage-controlled oscillator (LC-VCO) is comprised of a negative gm cell, a switched capacitor array (SCA), an inductor, and so on. As previously mentioned, symmetric, 8-shaped inductors are typically used in the inductor-capacitor voltage-controlled oscillator. However, the noise coupling has become an issue for such symmetric, 8-shaped inductor, especially when an adjacent ground top metal is present.

The present disclosure provides a semiconductor device comprising an asymmetric, 8-shaped inductor for on-die inductor coupling mitigation in order to address this problem. A better electrical performance can be obtained in a case that the inductor according to the present disclosure is used in, for example a voltage-controlled oscillator. According to the experimental results, a 20 dB coupled noise reduction can be observed at the inductor of a victim circuit.

FIG.1shows an asymmetric, 8-shaped inductor in accordance with an embodiment of the invention. As shown inFIG.1, a semiconductor device1acomprises a substrate100such as a silicon-based substrate and an inductor IN fabricated on the substrate100. According to an embodiment, the inductor IN is at least partially surrounded by a ground metal ring GR. According to an embodiment, for example, the ground metal ring GR is constructed at top metal layers202over the substrate100. The top metal layer mentioned herein is not limited to the topmost metal layer. For example, the top metal layers may comprise the topmost metal layer and several upper metal layers below the topmost metal layer. It is to be understood that the ground metal ring GR may be defined in any of the top metal layers.

According to an embodiment, for example, the top metal layer202may be an aluminum layer, but is not limited thereto. The inductor IN is formed by using a conductor210that is arranged between two terminals A, B of a victim circuit VC that is disposed adjacent to an opened end OP of the ground metal ring GR. Although an open-loop type ground ring GR is illustrated, it is to be understood that in some embodiments the ground metal ring GR may be a close-loop type ground ring. According to an embodiment, for example, the victim circuit VC may be a switched capacitor array of an inductor-capacitor voltage-controlled oscillator, but is not limited thereto.

According to an embodiment, the conductor210is shaped for forming a first loop L1and a second loop L2of the single-turn inductor IN. A crossing C is present between the first loop L1and the second loop L2. The first loop L1encloses a first area and the second loop L2encloses a second area. The first loop L1is defined by the conductor210and the crossing C, which makes the first enclosed area, at least in projection in a direction perpendicular to the plane in which the first loop is arranged, fully enclosed. The second loop L2is defined by the conductor210and the crossing C. According to an embodiment, the second enclosed area is not fully enclosed.

According to an embodiment, the first loop L1is asymmetric to the second loop L2with respect to the axis AS. According to an embodiment, the first enclosed area is smaller than the second enclosed area. According to an embodiment, the second loop L2is disposed closer to the victim circuit VC and the first loop L1is disposed farther away from the victim circuit VC.

The inductor IN may be fabricated on the substrate100by conventional semiconductor fabrication processes including but not limited to deposition, lithography, etching, cleaning, polishing, annealing or the like. The inductor IN may be composed of at least two interconnect layers. Generally, the thicker top interconnect layer has lower resistance and the inductor IN is generally laid out in the top metal layers, except for the locations where the conductor210crosses itself. At those crossings the lower interconnect layer is used. For example, inFIG.1, the conductor210may be located in the top metal layers and connected to an underlying interconnect layer211at the crossing C1. The interconnect layer211may be located in the lower metal layer.

FIG.2shows an asymmetric, 8-shaped inductor in accordance with another embodiment of the invention, wherein like regions, layers or elements are designated by like numeral numbers or labels. As shown inFIG.2, likewise, the single-turn, 8-shaped inductor1bcomprises a substrate100such as a silicon-based substrate and an inductor IN fabricated on the substrate100. According to an embodiment, the inductor IN is at least partially surrounded by a ground metal ring GR. According to an embodiment, for example, the ground metal ring GR is constructed at a top metal layer202over the substrate100. According to an embodiment, for example, the top metal layer202may be an aluminum layer, but is not limited thereto. The inductor IN is formed by using a conductor210that is arranged between two terminals A, B of a victim circuit VC that is disposed adjacent to an opened end OP of the ground metal ring GR. According to an embodiment, for example, the victim circuit VC may be a switched capacitor array of an inductor-capacitor voltage-controlled oscillator, but is not limited thereto.

According to an embodiment, the conductor210is shaped for forming a first loop L1and a second loop L2of the single-turn inductor IN. A first crossing C1is present between the first loop L1and the second loop L2. The first loop L1encloses a first area and the second loop L2encloses a second area. The first loop L1is defined by the conductor210and the first crossing C1, which makes the first enclosed area. The second loop L2is defined by the conductor210, the first crossing C1, and a second crossing C2in between the second loop L2and the terminals A, B. According to an embodiment, the first loop L1is asymmetric to the second loop L2with respect to the axis AS. According to an embodiment, the first enclosed area is smaller than the second enclosed area. According to an embodiment, the second loop L2is disposed closer to the victim circuit VC and the first loop L1is disposed farther away from the victim circuit VC.

The inductor IN may be fabricated on the substrate100by conventional semiconductor fabrication processes including but not limited to deposition, lithography, etching, cleaning, polishing, annealing or the like. The inductor IN may be composed of at least two interconnect layers. Generally, the thicker top interconnect layer has lower resistance and the inductor IN is generally laid out in the top metal layers, except for the locations where the conductor210crosses itself. At those crossings the lower interconnect layer is used. For example, inFIG.2, the conductor210may be located in the top metal layers and connected to underlying interconnect layers211,212at the crossings C1, C2, respectively. The interconnect layers211,212may be located in the metal layer below the top metal layers.

FIG.3shows an asymmetric, 8-shaped inductor in accordance with another embodiment of the invention, wherein like regions, layers or elements are designated by like numeral numbers or labels. As shown inFIG.3, the semiconductor device1ccomprises a substrate100such as a silicon-based substrate and a double-turn, 8-shaped inductor IN fabricated on the substrate100. It is understood that the present invention is applicable to multiple turn inductors, not limited to a double-turn inductor. According to an embodiment, the inductor IN is at least partially surrounded by a ground metal ring GR. According to an embodiment, for example, the ground metal ring GR is constructed at a top metal layer202over the substrate100. According to an embodiment, for example, the top metal layer202may be an aluminum layer, but is not limited thereto. The inductor IN is formed by using a conductor210that is arranged between two terminals A, B of a switched capacitor array20that is disposed adjacent to an opened end OP of the ground metal ring GR. According to an embodiment, for example, the switched capacitor array20may be electrically connected to a negative gm cell30. It is understood that the arrangement of the inductor IN, switched capacitor array20and the negative gm cell30is for illustration purposes only.

According to an embodiment, the conductor210is shaped for forming a first loop L1and a second loop L2of the inductor IN. A first crossing C1is present between the first loop L1and the second loop L2. The first loop L1encloses a first area and the second loop L2encloses a second area. The first loop L1is generally defined by the conductor210and the first crossing C1, which makes the first enclosed area. The second loop L2is generally defined by the conductor210, the first crossing C1, and the terminals A, B. According to an embodiment, the first loop L1is asymmetric to the second loop L2with respect to the axis AS. According to an embodiment, the first enclosed area is smaller than the second enclosed area. According to an embodiment, the second loop L2is disposed closer to the switched capacitor array20and the first loop L1is disposed farther away from the switched capacitor array20.

According to an embodiment, the conductor210is further shaped for forming a third loop L3and a fourth loop L4. According to an embodiment, a third crossing C3of the conductor210with itself is present between the third loop L3and the fourth loop L4. According to an embodiment, the third loop L3and the fourth loop L4define a third enclosed area and a fourth enclosed area, respectively. According to an embodiment, the fourth enclosed area is greater than the third enclosed area.

According to an embodiment, the conductor210is further provided with a fourth crossing C4with itself connecting the first loop L1with the third loop L3thereby further defining the boundaries of the first enclosed area and the third enclosed area.

According to an embodiment, the first loop L1is connected between the fourth loop L4and the second loop L2. According to an embodiment, the fourth loop L4is connected between the first loop L1and the third loop L3to obtain an 8-shaped structure in series with an 8-shaped structure.

According to an embodiment, the third loop L3is arranged within the first loop L1and the fourth loop L4is arranged within the second loop L2thereby forming a fifth crossing C5for further defining the fourth enclosed area, and forming a sixth crossing C6for further defining the first and second enclosed area, to obtain an 8-within-8 shaped structure.

The inductor IN may be fabricated on the substrate100by conventional semiconductor fabrication processes including but not limited to deposition, lithography, etching, cleaning, polishing, annealing or the like. The inductor IN may be composed of at least two interconnect layers. Generally, the thicker top interconnect layer has lower resistance and the inductor IN is generally laid out in the top metal layers, except for the locations where the conductor210crosses itself. At those crossings the lower interconnect layer is used. For example, inFIG.3, the conductor210may be patterned in the top metal layers and connected to underlying interconnect layers211,213,214,215at the crossings C1, C3, C4, C5-C6, respectively. The interconnect layers211,214, and215may be located in the lower metal layer just below the top metal layers. The interconnect layer213may be located in the metal layer below the interconnect layers211,214, and215.

FIG.4shows an asymmetric, 8-shaped inductor in accordance with another embodiment of the invention, wherein like regions, layers or elements are designated by like numeral numbers or labels. As shown inFIG.4, the device1dcomprises a substrate100such as a silicon-based substrate and a double-turn, 8-shaped inductor IN fabricated on the substrate100. It is understood that the present invention is applicable to multiple turn inductors, not limited to a double-turn inductor. According to an embodiment, the inductor IN is at least partially surrounded by a ground metal ring GR. According to an embodiment, for example, the ground metal ring GR is constructed at a top metal layer202over the substrate100. According to an embodiment, for example, the top metal layer202may be an aluminum layer, but is not limited thereto. The inductor IN is formed by using a conductor210that is arranged between two terminals A, B of a switched capacitor array20that is disposed adjacent to an opened end OP of the ground metal ring GR. According to an embodiment, for example, the switched capacitor array20may be electrically connected to a negative gm cell30. It is understood that the arrangement of the inductor IN, switched capacitor array20and the negative gm cell30is for illustration purposes only.

According to an embodiment, the conductor210is shaped for forming a first loop L1and a second loop L2of the inductor IN. A first crossing C1is present between the first loop L1and the second loop L2. The first loop L1encloses a first area and the second loop L2encloses a second area. The first loop L1is generally defined by the conductor210and the first crossing C1, which makes the first enclosed area. The second loop L2is generally defined by the conductor210, the first crossing C1, and a second crossing C2in between the second loop L2and the terminals A, B. According to an embodiment, the first loop L1is asymmetric to the second loop L2with respect to the axis AS. According to an embodiment, the first enclosed area is smaller than the second enclosed area. According to an embodiment, the second loop L2is disposed closer to the switched capacitor array20and the first loop L1is disposed farther away from the switched capacitor array20.

According to an embodiment, the conductor210is further shaped for forming a third loop L3and a fourth loop L4. According to an embodiment, a third crossing C3of the conductor210with itself is present between the third loop L3and the fourth loop L4. According to an embodiment, the third loop L3and the fourth loop L4define a third enclosed area and a fourth enclosed area, respectively. According to an embodiment, the fourth enclosed area is greater than the third enclosed area.

According to an embodiment, the conductor210is further provided with a fourth crossing C4with itself connecting the first loop L1with the third loop L3thereby further defining the boundaries of the first enclosed area and the third enclosed area.

According to an embodiment, the first loop L1is connected between the fourth loop L4and the second loop L2. According to an embodiment, the fourth loop L4is connected between the first loop L1and the third loop L3to obtain an 8-shaped structure in series with an 8-shaped structure.

According to an embodiment, the third loop L3is arranged within the first loop L1and the fourth loop L4is arranged within the second loop L2thereby forming a fifth crossing C5for further defining the fourth enclosed area, and forming a sixth crossing C6for further defining the first and second enclosed area, to obtain an 8-within-8 shaped structure.

The inductor IN may be fabricated on the substrate100by conventional semiconductor fabrication processes including but not limited to deposition, lithography, etching, cleaning, polishing, annealing or the like. The inductor IN may be composed of at least two interconnect layers. Generally, the thicker top interconnect layer has lower resistance and the inductor IN is generally laid out in the top meal layers, except for the locations where the conductor210crosses itself. At those crossings the lower interconnect layer is used. For example, inFIG.4, the conductor210may be patterned in the top metal layers and connected to underlying interconnect layers211,212,213,214,215at the crossings C1, C2, C3, C4, C5-C6, respectively. The interconnect layers211,212,214, and215may be located in the lower metal layer just below the top metal layers. The interconnect layer213may be located in the metal layer below the interconnect layers211,212,214, and215.

FIG.5shows an asymmetric, 8-shaped inductor in accordance with still another embodiment of the invention, wherein like regions, layers or elements are designated by like numeral numbers or labels. As shown inFIG.5, the device1ecomprises a substrate100such as a silicon-based substrate and a single-turn, 8-shaped inductor IN fabricated on the substrate100. It is understood that the present invention is applicable to multiple turn inductors, not limited to a double-turn inductor. According to an embodiment, the inductor IN is at least partially surrounded by a ground metal ring GR. According to an embodiment, for example, the ground metal ring GR is constructed at a top metal layer202over the substrate100. According to an embodiment, for example, the top metal layer202may be an aluminum layer, but is not limited thereto. The inductor IN is formed by using a conductor210that is merged with connecting parts22,24of a switched capacitor array20that is disposed adjacent to an opened end OP of the ground metal ring GR. According to an embodiment, for example, the switched capacitor array20may be electrically connected to a negative gm cell30. It is understood that the arrangement of the inductor IN, switched capacitor array20and the negative gm cell30is for illustration purposes only.

It is beneficial to cancel the terminals A, B inFIG.3because the metal connection between the switched capacitor array20and the inductor IN may induce an additional current loop and thus degrade an aggressor to the inductor coupling. By merging the inductor IN with the connecting parts22,24of the switched capacitor array20, the undesired current loop can be avoided.

According to an embodiment, likewise, the conductor210is shaped for forming a first loop L1and a second loop L2of the inductor IN. A first crossing C1is present between the first loop L1and the second loop L2. The first loop L1encloses a first area and the second loop L2encloses a second area. The first loop L1is generally defined by the conductor210and the first crossing C1, which makes the first enclosed area. The second loop L2is generally defined by the conductor210, the first crossing C1, and the connecting parts22,24of the switched capacitor array20. According to an embodiment, the first loop L1is asymmetric to the second loop L2with respect to the axis AS. According to an embodiment, the first enclosed area is smaller than the second enclosed area. According to an embodiment, the second loop L2is disposed closer to the switched capacitor array20and the first loop L1is disposed farther away from the switched capacitor array20.

The inductor IN may be fabricated on the substrate100by conventional semiconductor fabrication processes including but not limited to deposition, lithography, etching, cleaning, polishing, annealing or the like. The inductor IN may be composed of at least two interconnect layers. Generally, the thicker top interconnect layer has lower resistance and the inductor IN is generally laid out in the top metal layers, except for the locations where the conductor210crosses itself. At those crossings the lower interconnect layer is used. For example, inFIG.5, the conductor210may be patterned in the top metal layers and connected to an underlying interconnect layer211at the crossing C1.

FIG.6shows an asymmetric, 8-shaped inductor in accordance with still another embodiment of the invention, wherein like regions, layers or elements are designated by like numeral numbers or labels. As shown inFIG.6, the device1fcomprises a substrate100such as a silicon-based substrate and a double-turn, 8-shaped inductor IN fabricated on the substrate100. It is understood that the present invention is applicable to multiple turn inductors, not limited to a double-turn inductor. According to an embodiment, the inductor IN is at least partially surrounded by a ground metal ring GR. According to an embodiment, for example, the ground metal ring GR is constructed at a top metal layer202over the substrate100. According to an embodiment, for example, the top metal layer202may be an aluminum layer, but is not limited thereto. The inductor IN is formed by using a conductor210that is merged with connecting parts22,24of a switched capacitor array20that is disposed adjacent to an opened end OP of the ground metal ring GR. According to an embodiment, for example, the switched capacitor array20may be electrically connected to a negative gm cell30. It is understood that the arrangement of the inductor IN, switched capacitor array20and the negative gm cell30is for illustration purposes only.

It is beneficial to cancel the terminals A, B as depicted inFIG.3because the metal connection between the switched capacitor array20and the inductor IN may induce an additional current loop and thus degrade an aggressor to the inductor coupling. By merging the inductor IN with the connecting parts22,24of the switched capacitor array20, the undesired current loop can be avoided.

According to an embodiment, likewise, the conductor210is shaped for forming a first loop L1and a second loop L2of the inductor IN. A first crossing C1is present between the first loop L1and the second loop L2. The first loop L1encloses a first area and the second loop L2encloses a second area. The first loop L1is generally defined by the conductor210and the first crossing C1, which makes the first enclosed area. The second loop L2is generally defined by the conductor210, the first crossing C1, and the connecting parts22,24of the switched capacitor array20. According to an embodiment, the first loop L1is asymmetric to the second loop L2with respect to the axis AS. According to an embodiment, the first enclosed area is smaller than the second enclosed area. According to an embodiment, the second loop L2is disposed closer to the switched capacitor array20and the first loop L1is disposed farther away from the switched capacitor array20.

According to an embodiment, the conductor210is further shaped for forming a third loop L3and a fourth loop L4. According to an embodiment, a third crossing C3of the conductor210with itself is present between the third loop L3and the fourth loop L4. According to an embodiment, the third loop L3and the fourth loop L4define a third enclosed area and a fourth enclosed area, respectively. According to an embodiment, the fourth enclosed area is greater than the third enclosed area.

According to an embodiment, the conductor210is further provided with a fourth crossing C4with itself connecting the first loop L1with the third loop L3thereby further defining the boundaries of the first enclosed area and the third enclosed area.

According to an embodiment, the first loop L1is connected between the fourth loop L4and the second loop L2. According to an embodiment, the fourth loop L4is connected between the first loop L1and the third loop L3to obtain an 8-shaped structure in series with an 8-shaped structure.

According to an embodiment, the third loop L3is arranged within the first loop L1and the fourth loop L4is arranged within the second loop L2thereby forming a fifth crossing C5for further defining the fourth enclosed area, and forming a sixth crossing C6for further defining the first and second enclosed area, to obtain an 8-within-8 shaped structure.

The inductor IN may be fabricated on the substrate100by conventional semiconductor fabrication processes including but not limited to deposition, lithography, etching, cleaning, polishing, annealing or the like. The inductor IN may be composed of at least two interconnect layers. Generally, the thicker top interconnect layer has lower resistance and the inductor IN is generally laid out in the top metal layers, except for the locations where the conductor210crosses itself. At those crossings the lower interconnect layer is used. For example, inFIG.6, the conductor210is located in the top metal layers and connected to underlying interconnect layers211,213,214,215at the crossings C1, C3, C4, C5-C6, respectively. The interconnect layers211,214, and215may be located in the lower metal layer below the top metal layers. The interconnect layers213may be located in the metal layer below the interconnect layers211,214, and215.