Display device

A display device comprises: selector transistors in each of which one of conductive electrodes is connected to each of ends of gate lines, the selector transistor being divided into a plurality; selection signal supplying wirings each of which is provided in each block, and connected to each control electrode of the selector transistors corresponding to the block; gate voltage supplying wirings that are commonly connected to the other conductive electrode of each of the selector transistors; a gate driver that sequentially supplies a gate voltage to the gate voltage supplying wirings while supplying a control voltage to the selection signal supplying wiring in order to on or off the selector transistor, and a light shielding part that is disposed between at least the two adjacent blocks.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from Japanese application JP2015-195072, filed Sep. 30, 2015. This Japanese application is incorporated herein by reference.

TECHNICAL FIELD

The present invention relates to a display device.

BACKGROUND

Nowadays, in a display panel, the number of gate lines increases due to high resolution. With increasing number of gate lines, the number of lead wirings of the gate lines increases to enlarge an area of a frame region. Therefore, for example, Japanese unexamined patent application publication JP2008-77007A discloses a driving system in which the gate lines are scanned in each block (group) while divided into a plurality of blocks. In the driving system of JP2008-77007A, the number of lead wirings of the gate lines is decreased, so that the area of the frame region can be reduced.

SUMMARY

However, in the conventional technology, the following problem occurs. Due to an arrangement of a thin film transistors (TFT) for selecting the gate lines, there are gaps between each neighboring two blocks. In this case, light from a backlight leaks from the gaps. Then, the leakage light enters a display area, as a result, display unevenness such as a transverse strip is observed in a region corresponding to a boundary between the blocks in a display image.

An object of the present disclosure is to reduce the display unevenness in the display device with the driving system that scans the gate lines in each group.

To solve the above problem, a display device according to the present disclosure comprises: a plurality of groups, each group having a plurality of data lines extending in a first direction and a plurality of gate lines extending in a second direction, wherein the plurality of gate lines for each group are adjacent in the first direction; a plurality of blocks, each block including: a plurality of selector transistors and each of the plurality of selector transistors includes: a first conductive electrode connected to an end of a corresponding gate line of the plurality of gate lines, a second conductive electrode, and a control electrode, wherein each block among the plurality of blocks corresponds to a group among the plurality of the groups; a plurality of selection signal supplying wirings each of which is connected to the control electrode of each of the plurality of selector transistors for a corresponding block of the plurality of blocks; a plurality of gate voltage supplying wirings each of which is connected to the second conductive electrode of one of the plurality of selector transistors in each of the groups; and a gate driver that sequentially supplies a gate voltage to the plurality of gate voltage supplying wirings and supplies a control voltage to the plurality of selection signal supplying wirings to turn on or off one or more of the plurality of selector transistors, and a light shielding part that is disposed between at least two adjacent blocks among the plurality of blocks.

In the display device according to the present disclosure, a first block and a second block-among the plurality of blocks may be sequentially arranged in a scanning direction, and the light shielding part is disposed between a selector transistor connected to a gate line scanned last in the first block and a selector transistor connected to a gate line scanned first in the second block.

In the display device according to the present disclosure, the control electrodes for each of the plurality of selector transistors included in a block among the plurality of blocks may be formed in one piece.

In the display device according to the present disclosure, the light shielding part may be an extended part of the control electrode of a selector transistor among the plurality of selector transistors.

In the display device according to the present disclosure, the light shielding part may include a dummy transistor that has a control electrode, and the control electrode of each of the plurality of selector transistors included in a first block among the plurality of blocks and the control electrode of the dummy transistor adjacent to the first block are integrally formed.

In the display device according to the present disclosure, the dummy transistor may include a first conductive electrode and a second conductive electrode, wherein each of the plurality of selection signal supplying wirings is not connected to the first conductive electrode and the second conductive electrode of the dummy transistor, and wherein each of the plurality of gate voltage supplying wirings is not connected to the first conductive electrode and the second conductive electrode of the dummy transistor.

In the display device according to the present disclosure, a dummy signal supplying wiring through which a dummy signal is supplied may be connected to a first conductive electrode of each dummy transistor, and a capacitance may be connected to a second conductive electrode of each dummy transistor.

The display device according to the present disclosure may further comprise: a plurality of dummy transistors, each of the dummy transistors including a first conductive electrode and a second conductive electrode; and a dummy signal supplying wiring through which a dummy signal is supplied, wherein the dummy signal supplying wiring is connected to the first conductive electrode of each of the plurality of dummy transistors, and the second conductive electrodes of the plurality of dummy transistors are electrically connected to each other.

In the display device according to the present disclosure, a first conductive electrode of the dummy transistor may be connected to a corresponding gate voltage supplying wiring among the plurality of gate voltage supplying wirings, and a capacitance may be connected to the second conductive electrode of the dummy transistor.

The display device according to the present disclosure may further comprise: a plurality of dummy transistors, each of the dummy transistors including a first conductive electrode and a second conductive electrode; wherein a corresponding gate voltage supplying wiring among the plurality of gate voltage supplying wirings is connected to the first conductive electrode of each of the plurality of dummy transistors, and the second conductive electrodes of the plurality of dummy transistors are electrically connected to each other.

The display device according to the present disclosure may further comprise: a plurality of dummy transistors, each of the dummy transistors including a first conductive electrode and a second conductive electrode; wherein a corresponding gate voltage supplying wiring among the plurality of gate voltage supplying wirings is connected to the first conductive electrode of each of the plurality of dummy transistors, a first capacitance is connected to the second conductive electrode of each dummy transistor corresponding to an odd-numbered block, wherein each block among the plurality of blocks is numerically sorted and the odd-numbered blocks are blocks having an odd number, and a second capacitance is connected to the second conductive electrode of each dummy transistor corresponding to an even-numbered block, wherein the even numbered blocks are blocks having an even number.

The display device according to the present disclosure may further comprise: a plurality of dummy transistors, each of the dummy transistors including a first conductive electrode and a second conductive electrode; wherein a corresponding gate voltage supplying wiring among the plurality of gate voltage supplying wirings is connected to the first conductive electrode of each of the plurality of dummy transistors, the second conductive electrodes of the plurality of dummy transistors corresponding to odd-numbered blocks are electrically connected to each other, wherein each block among the plurality of blocks are numerically sorted and the odd-numbered blocks are blocks having an odd number, and the second conductive electrodes of the plurality of dummy transistors corresponding to even-numbered blocks are electrically connected to each other, wherein the even numbered blocks are blocks having an even number.

In the display device of the present disclosure, the display device with the driving system that scans the gate lines in each group can be reduced.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings. In the exemplary embodiments, a liquid crystal display device is described as an example of the display device. However the present disclosure is not limited to this. For example the present disclosure may be an organic electroluminescence display (OLED) device. In addition, in the exemplary embodiments, although a liquid crystal display with COG (Chip On Glass) technology is described as an example, the present disclosure is not limited to this. For example, the present disclosure may be a liquid crystal display with COF (Chip On Film) technology or TCP (Tape Carrier Package) technology.

FIG. 1is plan and side views illustrating a schematic configuration of a liquid crystal display device according to an exemplary embodiment. Liquid crystal display device100includes display panel10, source driver IC2, gate driver IC3, and a backlight device (not illustrated). Display panel10includes thin film transistor substrate4(TFT substrate), color-filter substrate5(CF substrate), and liquid crystal layer6sandwiched between the substrates. Source driver IC2and gate driver IC3are directly mounted on a glass substrate constituting TFT substrate4. Source driver IC2and gate driver IC3are arranged in line along a side of display panel10. There is no limitation to the numbers of source driver IC2and gate driver IC3. Display panel10includes display region10athat displays an image and frame region10baround display region10a.

FIG. 2is a plan view illustrating a schematic configuration of display region10ain display panel10. A plurality of data lines11extending in a first direction (for example, a row direction) and a plurality of gate lines12extending in a second direction (for example, a column direction) are provided in display panel10. A thin film transistor (hereinafter, referred to as a pixel TFT)13is provided in an intersection portion of each data line11and each gate line12. Each data line11is electrically connected to a source driver IC2(seeFIG. 1), and each gate line12is electrically connected to a gate driver IC3(seeFIG. 1). First data line D1is disposed at an end in the column direction of the plurality of data lines11, and second data line D2is adjacent to first data line D1in the column direction. First gate line G1is disposed at an end in the row direction of the plurality of gate lines12, and second gate line G2is adjacent to first gate line G1in the row direction. First gate line G1and second gate line G2is scanned in this order.

In display panel10, a plurality of pixels14are arranged into a matrix shape (in the row and column directions) according to intersection portions of data lines11and gate lines12. A plurality of pixel electrodes15disposed in each pixel14and a common electrode16common to the plurality of pixels14are provided in TFT substrate4. Common electrode16may be provided in CF substrate5.

A data signal (data voltage) is supplied to each data line11from corresponding source driver IC2. A gate signal (a gate-on voltage and a gate-off voltage) is supplied to each gate line12from gate driver IC3. Common voltage Vcom is supplied to common electrode16from a common driver (not illustrated) through common wiring17. When an on voltage (gate-on voltage) of the gate signal is supplied to gate line12, pixel TFT13connected to gate line12is turned on to supply the data voltage to pixel electrode15through data line11connected to pixel TFT13. An electric field is generated by a difference between the data voltage supplied to pixel electrode15and common voltage Vcom supplied to common electrode16. The liquid crystal is driven by the electric field to control transmittance of light transmitted from a backlight, thereby displaying the image. Desired data voltages are applied to data signal lines11connected to pixel electrodes15of pixels14, which are formed by striped color filters to correspond to red, green, and blue, thereby performing color display.

FIG. 3is a plan view illustrating a detailed configuration of display panel10. Source driver IC2(SD-IC) electrically connected to one end of each data line11, gate driver IC3(GD-IC) electrically connected to one end of each gate line12, and terminal Vcom connected to one end of common wiring17are disposed in a marginal portion (a left side inFIG. 3) of frame region10bof display panel10. The other end of gate line12is connected to one of conductive electrodes (source electrode, first conductive electrode) of thin film transistor (hereinafter, referred to as a selector TFT)21for selecting gate lines12, and the other conductive electrode (drain electrode, second conductive electrode) of selector TFT21is electrically connected to gate voltage supplying wiring31. Selector TFT21acts as a switch that selects corresponding gate line12. The plurality of gate lines12are electrically connected to one gate voltage supplying wiring31. Specifically, for example, in the case that the number of gate lines12is1920, 1st, 31st, 61st, . . . , 1891st gate lines G1, G31, G61, . . . , G1891are connected to gate voltage supplying wiring VG1through corresponding selector TFTs21, and 2nd, 32nd, 62nd, . . . , 1892nd gate lines G2, G32, G62, . . . , G1892are connected to gate voltage supplying wiring VG2through corresponding selector TFTs21. Similarly, 30th, 60th, 90th, . . . , 1920th gate lines G30, G60, G90, . . . , G1920are connected to gate voltage supplying wiring VG30through corresponding selector TFTs21. In the example ofFIG. 3, gate line12is connected to identical gate voltage supplying wiring31in each 30 gate lines12. 64 gate lines12are electrically connected to one gate voltage supplying wiring31. 30 adjacent gate lines12connected to gate voltage supplying wirings VG1to VG30constitute one group. For example, gate lines G1to G30constitute one group (first group), gate lines G31to G60constitute one group (2nd group), and gate lines G1891to G1920constitute one group (64th group). In the example ofFIG. 3, gate line12includes 64 groups.

Each of the control electrodes (gate electrodes) of 30 selector TFTs21corresponding to one group is connected to identical gate selection signal supplying wirings (selection signal supplying wirings)32and the control electrodes of 30 selector TFTs21corresponding to one group are formed in one piece. A one block consists of a plurality of selector TFTs21corresponding to one group. Each block includes 30 selector TFT here. For example, in a first block corresponding to the first group including gate lines G1to G30, each of the control electrodes of 30 selector TFTs21connected to gate lines G1to G30is connected to gate selection signal supplying wiring CLK1and all of the control electrodes of 30 selector TFTs21connected to gate lines G1to G30are formed in one piece. For example, in a second block corresponding to the second group including gate lines G31to G60, each of the control electrodes of 30 selector TFTs21connected to gate lines G31to G60is connected to gate selection signal supplying wiring CLK2and all of the control electrodes of 30 selector TFTs21connected to gate lines G31to G60are formed in one piece. Similarly, in the 64th block corresponding to the 64th group including gate lines G1891to G1920, each of the control electrodes of 30 selector TFTs21connected to gate lines G1891to G1920is connected to gate selection signal supplying wiring CLK64and all of the control electrodes of 30 selector TFTs21connected to gate lines G1891to G1920are formed in one piece. That is, different gate selection signal supplying wiring32is provided for each block. An operation of a display panel10will be described below.FIG. 4is a timing chart illustrating the operation of the display panel10. InFIG. 4, clocks CK1, CK2are input from control circuit (not illustrated) to gate driver IC3, voltages CLK1, CLK2are supplied to gate selection signal supplying wirings CLK1, CLK2, and voltages VG1to VG30are supplied to gate voltage supplying wirings VG1to VG30.

First, at rise timing of clock CK1, gate driver IC3supplies voltage (gate-on voltage) to gate selection signal supplying wiring CLK1to turn on selector TFTs21. Therefore, 30 selector TFTs21of the first block which are connected to gate lines G1to G30of the first group are put into an on state. Then, at rise timing of clock CK2, gate driver IC3supplies a voltage (gate-on voltage Vgh) to gate voltage supplying wiring VG1to turn on pixel TFTs13(seeFIG. 2). Therefore, first-column pixel TFTs13connected to gate line G1are put into the on state, and the data voltage output from source driver IC2is supplied to first-column pixel electrodes15through data lines11connected to pixel TFTs13. Then, at the rise timing of clock CK2, gate driver IC3supplies gate-on voltage Vgh to gate voltage supplying wiring VG2while supplying a voltage (gate-off voltage Vgl) to gate voltage supplying wiring to turn off pixel TFTs13. Therefore, first-column pixel TFTs13connected to gate line G1are turned off, second-column pixel TFTs13connected to gate line G2are put into the on state, and the data voltage output from source driver IC2is supplied to second-column pixel electrodes15through data lines11connected to pixel TFTs13. Thus, in display panel10, first-group gate lines G1to G30are sequentially driven to supply the data voltage to corresponding pixel electrode15.

Then, at the rise timing of clock CK1, gate driver IC3supplies gate-on voltage to gate selection signal supplying wiring CLK2while supplying voltage (gate-off voltage) to gate selection signal supplying wiring CLK1to turn off selector TFTs21. Therefore, 30 selector TFTs21of the first block which are connected to first-group gate lines G1to G30are turned off, and selector TFTs21connected to second-group gate lines G31to G60are put into the on state. Then, at the rise timing of clock CK2, gate driver IC3supplies gate-on voltage Vgh to gate voltage supplying wiring VG1. Therefore, 31st-column pixel TFTs13connected to gate line G31are put into the on state, and the data voltage output from source driver IC2is supplied to 31st-column pixel electrodes15through data lines11connected to pixel TFTs13Then, at the rise timing of clock CK2, gate driver IC3supplies gate-on voltage Vgh to gate voltage supplying wiring VG2while supplying gate-off voltage Vgl to gate voltage supplying wiring VG1. Therefore, 31st-column pixel TFTs13connected to gate line G31are turned off, 32nd-column pixel TFTs13connected to gate line G32are put into the on state, and the data voltage output from source driver IC2is supplied to 32nd-column pixel electrodes15through data lines11connected to pixel TFTs13. Thus, in display panel10, second-group gate lines G31to G60are sequentially driven to supply the data voltage to corresponding pixel electrode15.

Hereinafter, in display panel10, gate lines12in each group are sequentially driven to supply the data voltage to corresponding pixel electrode15. A method for driving display panel10with gate-selector type is not limited to the above driving method, can be applied well-known driving method.

In the above configuration, because the number of wirings connected to gate driver IC3can be decreased smaller than the number of gate lines12, the area of the frame region in the column direction can be reduced compared to a configuration in which all gate lines12are drawn to the gate driver IC.

Referring toFIG. 3, in display panel10of the exemplary embodiment, a dummy thin film transistor (hereinafter, referred to as a dummy TFT)22that is not electrically connected to gate line12is further disposed between the two adjacent blocks. Specifically, in each block, dummy TFTs22are arranged in an opposite direction to the scanning direction with respect to selector TFTs21connected to gate lines G1, G31, G61, . . . , G1891that are scanned first. Dummy TFT22includes a gate electrode, a drain electrode, and a source electrode. A gate electrode of dummy TFT22has a light shielding property, and is formed integrally with a gate electrode of selector TFT21. That is, dummy TFT22acts as a light shielding part that shields light leaking from a gap between the two adjacent blocks.

There is no particular limitation to the configuration of display panel10including dummy TFT22, but various configurations can be adopted. A specific configuration example of display panel10including dummy TFT22will be described below.

FIG. 3illustrates a configuration of display panel10according to a first configuration example.FIG. 5is a plan view illustrating a detailed configuration of display panel10of the first configuration example. As illustrated inFIG. 5, in block B1, dummy TFT22ais disposed in the opposite direction to the scanning direction with respect to selector TFT connected to gate line G1scanned first. A gate electrode of dummy TFT22ais formed integrally with a gate electrode of each selector TFT21in block B1while electrically connected to gate selection signal supplying wiring CLK1, but a drain electrode (first conductive electrode) and a source electrode (second conductive electrode) of dummy TFT22ais connected to any signal line. In other words, each of the plurality of gate lines12is not connected to a first conductive electrode and a second conductive electrode of the dummy TFT22a, and each of the plurality of gate voltage supplying wirings31is not connected to a first conductive electrode and a second conductive electrode of dummy TFT22a.FIG. 5schematically illustrates the gate electrode common to the plurality of selector TFTs and the drain electrode, source electrode, and semiconductor layer (a-Si), which correspond to each selector TFT. The same holds true for the following drawings. Dummy TFT22bis disposed between blocks B1, B2. A gate electrode of dummy TFT22bis formed integrally with a gate electrode of each selector TFT21in block B2while electrically connected to gate selection signal supplying wiring CLK2, but a drain electrode and a source electrode of dummy TFT22bis not connected to any signal line. Similarly, dummy TFT22cis disposed between blocks B2, B3. A gate electrode of dummy TFT22cis formed integrally with a gate electrode of each selector TFT21in block B3while electrically connected to gate selection signal supplying wiring CLK3, but a drain electrode and a source electrode of dummy TFT22cis not connected to any signal line.

Dummy TFTs22a,22b,22care arranged in a straight line with selector TFT21. The gate electrodes of dummy TFTs22a,22b,22care formed integrally with each of the gate electrodes of selector TFTs21of blocks B1, B2, B3, respectively.

In the above configuration, the light leaking from the gap between the blocks is shielded, so that a transverse strip caused by the leak light can be prevented from occurring.

FIG. 6is a plan view illustrating a detailed configuration of the block of display panel10according to a second configuration example. In the configuration of display panel10of the second configuration example, dummy signal supplying wiring23through which a dummy signal having a predetermined voltage is supplied and capacitance24are added to display panel10of the first configuration example inFIG. 5. The dummy signal may be the gate-on voltage or a voltage lower than the gate-on voltage. A gate electrode of dummy TFT22ais formed integrally with a gate electrode of each selector TFT21in block B1while electrically connected to gate selection signal supplying wiring CLK1, a drain electrode of dummy TFT22ais connected to dummy signal supplying wiring DM1, and a source electrode of dummy TFT22ais connected to capacitance24. A gate electrode of dummy TFT22bis formed integrally with a gate electrode of each selector TFT21in block B2while electrically connected to gate selection signal supplying wiring CLK2, a drain electrode of dummy TFT22bis connected to dummy signal supplying wiring DM2, and a source electrode of dummy TFT22bis connected to capacitance24. A gate electrode of dummy TFT22cis formed integrally with a gate electrode of each selector TFT21in block B3while electrically connected to gate selection signal supplying wiring CLK3, a drain electrode of dummy TFT22cis connected to dummy signal supplying wiring DM3, and a source electrode of dummy TFT22cis connected to capacitance24. In the second configuration example, because capacitance24acts as a load capacitance of each dummy TFT22, current is passed through each dummy TFT22to generate heat. Particularly, a heating value of each of selector TFTs21connected to gate lines G1, G31, G61, . . . , G1891scanned first in the blocks can be brought close to heating values of other selector TFTs21. Therefore, the transverse strip caused by the leak light can be prevented from occurring, and the transverse strip caused by the heat generation can be prevented from occurring.

FIG. 7is a plan view illustrating a detailed configuration of the block of display panel10according to a third configuration example. In the configuration of display panel10of the third configuration example, dummy signal supplying wiring23and dummy wiring25are added to display panel10of the first configuration example inFIG. 5. A gate electrode of dummy TFT22ais formed integrally with a gate electrode of each selector TFT21in block B1while electrically connected to gate selection signal supplying wiring CLK1, a drain electrode of dummy TFT22ais connected to dummy signal supplying wiring DM1, and a source electrode of dummy TFT22ais connected to dummy wiring25. A gate electrode of dummy TFT22bis formed integrally with a gate electrode of each selector TFT21in block B2while electrically connected to gate selection signal supplying wiring CLK2, a drain electrode of dummy TFT22bis connected to dummy signal supplying wiring DM2, and a source electrode of dummy TFT22bis connected to dummy wiring25. A gate electrode is formed integrally with a gate electrode of each selector TFT21in block B3while electrically connected to gate selection signal supplying wiring CLK3, a drain electrode of dummy TFT22cis connected to dummy signal supplying wiring DM3, and a source electrode of dummy TFT22cis connected to dummy wiring25. A signal is not supplied to dummy wiring25, but dummy wiring25is disposed in a floating state. In the third configuration example, for example, dummy TFT22acorresponding to block B1is connected to dummy TFT22bcorresponding to block B2and dummy TFT22ccorresponding to block B3through dummy wiring25, and dummy TFTs22b,22chave the same function as the load capacitance inFIG. 6, whereby the current is passed through dummy TFT22ato generate the heat. Therefore, similarly to the second configuration example, the transverse strip caused by the heat generation can be prevented from occurring.

FIG. 8is a plan view illustrating a detailed configuration of the block of display panel10according to a fourth configuration example. In the configuration of display panel10of the fourth configuration example, gate voltage supplying wiring VG0and capacitance24are added to display panel10of the first configuration example inFIG. 5. A gate electrode of dummy TFT22ais formed integrally with a gate electrode of each selector TFT21in block B1while electrically connected to gate selection signal supplying wiring CLK1, a drain electrode of dummy TFT22ais connected to gate voltage supplying wiring VG0, and a source electrode of dummy TFT22ais connected to capacitance24. A gate electrode of dummy TFT22bis formed integrally with a gate electrode of each selector TFT21in block B2while electrically connected to gate selection signal supplying wiring CLK2, a drain electrode of dummy TFT22bis connected to gate voltage supplying wiring VG0, and a source electrode of dummy TFT22bis connected to capacitance24. A gate electrode of dummy TFT22cis formed integrally with a gate electrode of each selector TFT21in block B3while electrically connected to gate selection signal supplying wiring CLK3, a drain electrode of dummy TFT22cis connected to gate voltage supplying wiring VG0, and a source electrode of dummy TFT22cis connected to capacitance24. In the fourth configuration example, the gate-on voltage is sequentially supplied to the drain electrodes of dummy TFTs22in scanning order of selector TFT21. Because capacitance24acts as the load capacitance of each dummy TFT22, the current is passed through each dummy TFT22to generate heat. Therefore, similarly to the second configuration example, the transverse strip caused by the heat generation can be prevented from occurring.

FIG. 9is a plan view illustrating a detailed configuration of the block of display panel10according to a fifth configuration example. In the configuration of display panel10of the fifth configuration example, gate voltage supplying wiring VG0and dummy wiring25are added to display panel10of the first configuration example inFIG. 5. A gate electrode of dummy TFT22ais formed integrally with a gate electrode of each selector TFT21in block B1while electrically connected to gate selection signal supplying wiring CLK1, a drain electrode of dummy TFT22ais connected to gate voltage supplying wiring VG0, and a source electrode of dummy TFT22ais connected to dummy wiring25. A gate electrode of dummy TFT22bis formed integrally with a gate electrode of each selector TFT21in block B2while electrically connected to gate selection signal supplying wiring CLK2, a drain electrode of dummy TFT22bis connected to gate voltage supplying wiring VG0, and a source electrode of dummy TFT22bis connected to dummy wiring25. A gate electrode of dummy TFT22cis formed integrally with a gate electrode of each selector TFT21in block B3while electrically connected to gate selection signal supplying wiring CLK3, a drain electrode of dummy TFT22cis connected to gate voltage supplying wiring VG0, and a source electrode of dummy TFT22cis connected to dummy wiring25. In the fifth configuration example, the gate-on voltage is sequentially supplied to the drain electrodes of dummy TFTs22in scanning order of selector TFT21. Additionally, in the fifth configuration example, for example, dummy TFT22acorresponding to block B1is connected to dummy TFT22bcorresponding to block B2and dummy TFT22ccorresponding to block B3through dummy wiring25, and dummy TFTs22b,22chave the same function as the load capacitance inFIG. 6, whereby the current is passed through dummy TFT22ato generate the heat. Therefore, similarly to the second configuration example, the transverse strip caused by the heat generation can be prevented from occurring.

In the first to fifth configuration examples, dummy TFT22(light shielding part) is disposed between the two adjacent blocks. However, the exemplary embodiment is not limited to the first to fifth configuration examples. For example, dummy TFTs22may be disposed between the two adjacent blocks and at a predetermined position in each block. For example, in the case that a gap exists between two adjacent selector TFTs21, dummy TFT22may be disposed in the gap between two adjacent selector TFTs21. The above configuration can be applied to the first to fifth configuration examples.

In the first to fifth configuration examples, dummy TFT22is disposed in a head (front) position of each block. However, the exemplary embodiment is not limited to the first to fifth configuration examples. For example, as illustrated inFIG. 10, dummy TFTs22may be disposed at the head and final (last) positions in each block. The configuration inFIG. 10corresponds to the first configuration example. However, the configuration inFIG. 10can also be applied to the second to fifth configuration examples. In the above configuration, the transverse strip caused by the leak light can be prevented from occurring irrespective of the scanning direction.

In the first to fifth configuration examples, selector TFT21and dummy TFT22are provided on one end side of gate line12. However, selector TFT21and dummy TFT22may be provided on both end sides of gate line12. That is, the exemplary embodiment can be applied to a display panel with a system that drives gate line12from both ends.

In the second configuration example (seeFIG. 6) and the fourth configuration example (seeFIG. 8), the source electrode of each dummy TFT22is connected to one capacitance24. However, display panel10of the exemplary embodiment is not limited to the second and fourth configuration examples. For example, as illustrated inFIG. 11, in display panel10, the source electrodes of the dummy TFTs (such as22a,22c) corresponding to odd-numbered blocks (such as B1, B3) may be connected to capacitance24a(first capacitance), and the source electrodes of the dummy TFTs (such as22b,22d) corresponding to even-numbered blocks (such as B2, B4) may be connected to capacitance24b(second capacitance). The two adjacent dummy TFTs can be electrically separated from each other, so that a defect that is caused by electrically connecting the two adjacent dummy TFTs to each other because the dummy TFTs are simultaneously put into the on state can be prevented in the configuration in which the gate-on voltage is simultaneously supplied to two adjacent gate selection signal supplying wirings CLK to drive the corresponding gate line.FIG. 11illustrates an example applied to the configuration inFIG. 6, and the example inFIG. 11can also be applied to the configuration inFIG. 8.

Similarly, in the third configuration example (seeFIG. 7) and the fifth configuration example (seeFIG. 9), the source electrode of each dummy TFT22is connected to one dummy wiring25. However, the exemplary embodiment is not limited to the third and fifth configuration examples. For example, as illustrated inFIG. 12, in display panel10, the source electrodes of the dummy TFTs (such as22a,22c) corresponding to the odd-numbered blocks (such as B1, B3) may be connected to dummy wiring25a, and the source electrodes of the dummy TFTs (such as22b,22d) corresponding to the even-numbered blocks (such as B2, B4) may be connected to dummy wiring25b. Therefore, the source electrodes of the dummy TFTs corresponding to the odd-numbered blocks are electrically connected to each other, and the source electrodes of the dummy TFTs corresponding to the even-numbered blocks are electrically connected to each other. The two adjacent dummy TFTs can be electrically separated from each other, so that a defect that is caused by electrically connecting the two adjacent dummy TFTs to each other because the dummy TFTs are simultaneously put into the on state can be prevented in the configuration in which the gate-on voltage is simultaneously supplied to two adjacent gate selection signal supplying wirings CLK to drive the corresponding gate line.FIG. 12illustrates an example applied to the configuration inFIG. 7, and the example inFIG. 12can also be applied to the configuration inFIG. 9.

As described above, in display panel10of the exemplary embodiment, the light shielding part is disposed between at least two adjacent blocks. The light shielding part is not limited to dummy TFTs22of the first to fifth configuration examples. For example, the light shielding part may be gate electrode extended part26that is of a region where the gate electrode of the selector transistor is extended.FIG. 13is a plan view illustrating a configuration of display panel10in the case that gate electrode extended part26is used in the first configuration example.

In the above, the specific embodiments of the present application have been described, but the present application is not limited to the above-mentioned embodiments, and various modifications may be made as appropriate without departing from the spirit of the present application.