Integrated circuit amplifier device and method using FET tunneling gate current

An integrated circuit amplifier includes, in an exemplary embodiment, a first field effect transistor (FET) device configured as a common source amplifier with source degeneration and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the source follower. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the common source amplifier with source degeneration is configured so as to set an output conductance of the amplifier.

BACKGROUND

The present invention relates generally to semiconductor devices, and, more particularly, to an integrated circuit amplifier device and method utilizing FET tunneling gate current.

Amplifiers are commonly used in RF and analog applications. For a field effect transistor (FET) amplifier, a high gain associated therewith generally results from a device having a large gate width. The gain of an FET amplifier is given by the expression:
Gain=Gm/Gds(eq. 1);

wherein Gmand Gdsare, respectively, the transconductance and output conductance of the FET. In turn, the transconductance, Gm, of the FET is given by the expression:
Gm=d(ID)/d(Vg) at a given value of Vds(eq. 2);

while the output conductance of the FET is given by the expression:
Gds=d(ID)/d(Vds) at a given value of Vg(eq. 3).

The transconductance of an FET is strongly dependent upon the channel length of the device (i.e., the shorter the channel length, the greater the transconductance of the FET). However, given certain technologies having minimum channel lengths associated therewith, the value of Gmcannot be arbitrarily increased. Moreover, the peak value of transconductance occurs at a specific gate voltage for a minimum channel length and, as such, the FET amplifier would need to be designed for that specific gate voltage to take advantage of the peak Gm. Thus, the voltage options for the design of a conventional FET amplifier are limited in this sense. Furthermore, because a high output voltage (Vds) is desired, and since the input voltage Vgscould be at low overdrive (or at 0.5 Vds), both of these conditions can lead to hot carrier degradation.FIG. 1is a graph that illustrates the degradation of amplification factor due to hot carrier effects.

Since Gmand Gdsfor a conventional FET amplifier are not decoupled from each other, but rather are both dependent upon the design of a given FET, each parameter cannot be independently optimized with respect to one another for gain purposes (i.e., increasing Gmwhile also decreasing Gdsfor the same device). Still a further consideration is the fact that the frequency response of the amplifier is limited by the gate oxide capacitance, which increases as CMOS scaling is intensified. The increase of gain is again coupled with optimization of the frequency response, since the two parameters are controlled by the same FET with an ultra-thin gate oxide.

Accordingly, it would be desirable to have an integrated circuit amplifier device in which the various gain parameters are capable of independent optimization with respect to one another.

SUMMARY

The foregoing discussed drawbacks and deficiencies of the prior art are overcome or alleviated by an integrated circuit amplifier including, in an exemplary embodiment, a first field effect transistor (FET) device configured as a common source amplifier with source degeneration and a second FET device configured as a tunneling gate FET, the tunneling gate FET coupled to the common source amplifier with source degeneration. The tunneling gate FET is further configured so as to set a transconductance of the amplifier and the common source amplifier with source degeneration is configured so as to set an output conductance of the amplifier.

In another embodiment, an integrated circuit differential amplifier includes a first field effect transistor (FET) device configured as a first common source amplifier with source degeneration, a second FET device configured as a second common source amplifier with source degeneration, a third FET device configured as a first tunneling gate FET, the first tunneling gate FET coupled between the first common source amplifier with source degeneration and the second common source amplifier with source degeneration, and a fourth FET device configured as a second tunneling gate FET, the second tunneling gate FET coupled between the first common source amplifier with source degeneration and the second common source amplifier with source degeneration. The first and second tunneling gate FETs are farther configured so as to set a transconductance of the differential amplifier, and the first and second common source amplifier with source degenerations are configured so as to set an output conductance of the differential amplifier.

In still another embodiment, a method for implementing an integrated circuit amplifier comprises configuring a first field effect transistor (FET) device as a common source amplifier with source degeneration, and configuring a second FET device as a tunneling gate FET coupled to the common source amplifier with source degeneration. The tunneling gate FET is further configured so as to set a transconductance of the amplifier, and the common source amplifier with source degeneration is configured so as to set an output conductance of the amplifier.

DETAILED DESCRIPTION

Disclosed herein is an integrated circuit amplifier device and method that independently optimizes the gain parameters and frequency response of an FET device by utilizing the highly non-linear relationship between gate tunneling current and gate voltage for ultra-thin gate oxides. Briefly stated, a two-terminal amplifier device is configured in which an ultra-thin gate oxide RET device (e.g., having a thickness of about 0.8 nm to about 2.2 nm) used to control transconductance, in combination with a thick oxide common source amplifier with source degeneration (e.g., having a thickness of about 5.0 nm to about 7.0 nm) for controlling the output conductance of the amplifier device.

A maximum tunneling current for the ultra-thin gate oxide FET is obtained with the source and drain terminals thereof at ground, with the channel inverted, and with Vgbiased above threshold voltage (Vt). For this two-terminal device, the gate thereof could be biased at a DC voltage, with a small signal superimposed thereon for amplification. For such a tunneling gate amplifier (TGA), there are no hot carrier effects, and no degradation under normal conditions. With the tunneling gate amplifier device used in combination with a thick gate oxide common source amplifier with source degeneration, sufficient gain can be achieved with a good frequency bandwidth, and the device dimensions can be properly chosen to achieve optimum performance and reliability. Thereby, the device parameters Gm, Gds, gain and frequency response may be independently optimized.

Referring flow toFIG. 2, there is shown a graph that illustrates gate tunneling current characteristics of an FET as function of oxide thickness (at 25° C.), for different values of gate voltage. The source, drain and substrate of the FET are all at ground potential. The transconductance, Gm, of the tunneling FET, given in A/(V·μm2) and calculated from (eq. 2), is illustrated inFIG. 3as a function of gate voltage at 25° C. for different oxide thicknesses.

In accordance with an embodiment of the invention,FIG. 4is a schematic diagram of a novel tunneling amplifier circuit100that includes a first FET device102configured as a common source amplifier with source degeneration, in which the source terminal thereof is coupled to the gate terminal of a second FET device104configured as a tunneling FET. Thus configured, the transconductance of the tunneling device104effectively sets the transconductance of the circuit. The resultant current change in the tunneling device104now appears at the drain of the common source amplifier with source degeneration102. Furthermore, this current can be pulled through a load106(e.g., a traditional load or another tunneling device, if a low gain is desired) to create an amplified voltage output signal. The load106is connected to a supply voltage (VS1)110. In addition, a current source108may be configured in parallel with the tunneling FET104for increasing the total current into the common source amplifier with source degeneration102, allowing for more optimization of the circuit gain.

Since the tunneling structure104is essentially a leaky capacitor, the gain of the amplifier circuit100will have a frequency response influenced by the tunneling structure. At DC and low frequencies, the gain should be a function of the transconductance Gmof the tunneling structure, as defined above. The −3 dB point of the rollover in gain should occur at ½πR0CT, wherein R0is the output resistance of the NFET common source amplifier with source degeneration102and CTis the capacitance of the tunneling FET104. The voltage amplification of the circuit100is provided between the input (In) and output (Out) voltages.

The load circuit106may be either another tunneling structure or a traditional current source. Once again, the output conductance of the NFET common source amplifier with source degeneration102must be significantly lower than the transconductance of the tunneling device104to allow the circuit100to have gain. In order to reduce output conductance of the common source amplifier with source degeneration102(and thus increase the gain of the circuit100), a thick oxide device (e.g., 5.2 nm) is utilized for the common source amplifier with source degeneration102.FIG. 5is a graph illustrating the output conductance Gdsof the common source amplifier with source degeneration102as function of gate-to-source voltage (Vgs) at a channel length of 1.0 μm, for different values of drain-to-source voltage (Vds).FIG. 6is a graph illustrating the output conductance of the common source amplifier with source degeneration102as a function of channel length (in microns) at a gate-to-source voltage Vgs=0.5 volts, for different values of drain-to-source voltage (Vds).

In order to optimize the design of the common source amplifier with source degeneration102, the tunneling FET104, and the current source108each of the design parameters are considered in the following equations:

Tunneling FET

The gate tunneling current density, Igd, of the tunneling FET104is given by:
Log(Igd)=AN2+[AN1·Tox]  (eq. 4);
wherein the gate current density Igdis expressed in units of amperes per square micron (A/μm2), and Toxis the gate oxide thickness in nanometers (nm). AN1and AN2are parameters that are functions of the gate voltage Vg. AN1and AN2may in turn be expressed as follows:
AN1=[0.673·Log(Vg)]−9.917  (eq. 5);
AN2=−9.685·exp[−1.159·Vg]  (eq. 6).

The complete expression of the NFET tunneling gate current density (in A/μm2) as function of temperature, oxide thickness and gate voltage is:
Log(Igd)=AN2+[AN1·Tox]+{ΔH[(1/T1)−(1/T2)]/K}(eq. 7)
wherein K is Bolztman's constant, T1is 298° K. (25° C.), T2is the application temperature in ° K., and ΔH is the activation energy which is equal to 0.017 eV. The tunneling gate current Ig(in Amperes) is given by:
Ig=Igd·WT·LT(eq. 8);

where WTand LTare, respectively, the width and length of the tunneling FET104in microns. The transconductance, in terms of density, in units of A/(V·μm2) for the tunneling FET104is calculated from eq. 2 with replacing device current IDby gate current Igfor the two-terminal FET104. The transconductance, in density, is designated by Gmdand is given by:
Gmd=Igd·{[0.673·Tox/Vg]+[11.225·exp(−1.159·Vg)]}  (eq. 9).

Thus, the transconductance of the tunneling FET104in (A/V) as a function of gate current density, channel length, channel width and temperature is given by:
Gm=Gmd·WT·LT=Igd·WT·LT·KT(eq. 10);
whereKT=[0.673·Tox/Vg]+[11.225·exp(−1.159·Vg)]

As described hereinafter, the current source108in parallel with the tunneling FET104provides an additional source of current, designated by IS, and may be used for optimization of the circuit gain and frequency response.

Common Source Amplifier with Source Degeneration

The output conductance of the common source amplifier with source degeneration102, in (A/V), may be expressed as follows:
Gds=WS·B1·exp[(A2·Vgs)−(C2·LS)]  (eq. 11).

Again, the common source amplifier with source degeneration102is preferably made from a thick gate oxide (e.g., 5.2 nm). Vgs, WS, and LSare, respectively, the gate to source voltage, channel width and channel length, of the common source amplifier with source degeneration. The values of the parameters B1, A2and C2are functions of Vds, the drain-to-source voltage of the common source amplifier with source degeneration102. Equation (11) is valid for LSin the range of about 0.5 μm to about 1.5 μm, and for Vgin the range of about 0.5 V to about 1.0 V. For Vdsof about 1.5 V, B1=0.0003, A2=5.2961, and C2=3.8274.

The common source amplifier with source degeneration102operates in the saturation range wherein the drain current there through is equal to the gate tunneling current (Ig) of the tunneling FET104. This gate current in turn is equal to the drain to source current of the common source amplifier with source degeneration102, which is given by:
Ig=[WS/(2·LS)]·μn·Ci·Vdsat2(eq. 12);
wherein μnis the electron mobility, Ciis the gate oxide capacitance/unit area, and Vdsatis given by:
Vdsat=Vgs−Vt(eq. 13).

Vtis the threshold voltage in saturation, which is about 0.4 volts. Vgsfor the common source amplifier with source degeneration102is given by:
Vgs=VS2−Vg(eq. 14);
where VS2is the input voltage to the gate of the common source amplifier with source degeneration and Vgis the gate voltage of the tunneling FET104. The drain-to-source voltage of the common source amplifier with source degeneration (Vds) is >Vdsat. The load resistor RL(i.e., load106) has a voltage thereacross of about 0.05 volts. The Vdsfor the common source amplifier with source degeneration is given by:
Vds=VS1−0.05−Vg(eq. 15);
where VS1is the supply voltage110connected to the load resistor RL.
Circuit Gain

The circuit gain for the tunneling gate amplifier100is given by:
Gain=(Gmd·WT·LT)/Gds(eq. 16).

From equations (11), (12), and (16), the gain can also be expressed as:
Gain=(Igd·WT·LT·KT)·exp[(C2·LS)−(A2·Vgs)]·(μn·Ci·Vdsat2)/[B1·2·LS·Igd·WT·LT]  (eq. 17).

This may be further expressed as:
Gain=KT·exp[(C2·LS)−(A2·Vgs)]·(μn·Ci·Vdsat2)/[B1·2·LS]  (eq. 18).

As can be seen from (eq. 18), the circuit gain is independent of Igd, which is the current density of the tunneling FET104. The gain is also independent of the dimensions of the tunneling FET104(WTand LT). However, the circuit gain increases with increasing LSand Vgsfor the common source amplifier with source degeneration102. It should also be noted that, for a given channel length (LS) of the common source amplifier with source degeneration102, the channel width thereof has to satisfy (eq. 12).

With regard to the current source108, the transconductance Gmfor the parallel combination of the tunneling FET104and the current source108is the same as would be the case where the tunneling FET104is used without the current source108. This is due to the fact that because the current value of the current source108remains constant and does not change with gate voltage. Accordingly, the derivative of the total current with respect to voltage will be the same as that for the tunneling FET. The circuit gain when constant current source108is used is expressed by:
Gain=(Igd·WT·LT)·KT·exp[(C2·LS)−(A2·Vgs)]·(μn·Ci·Vdsat2)/{B1·2·LS·[(Igd·WT·LT)+IS]}  (eq. 19).

As can be seen from (eq. 19), when adding a constant current source108in parallel with the tunneling FET104, the circuit gain decreases with increasing ISdue to the increase in total current and corresponding increase in the width and conductance Gdsfor the common source amplifier with source degeneration102. Also, in adding the constant current source108, the gain will increase with increasing area of tunneling FET104, provided that the magnitude of the current source108is significantly larger than the gate current of the tunneling FET104.

−3 dB Upper Frequency Point For Gain

The −3 dB point of the rollover in gain is FU=½πR0CT, where R0is the output resistance of the NFET common source amplifier with source degeneration and CTis the total capacitance of the combination of the tunneling FET and the common source amplifier with source degeneration. The total capacitance is determined as follows:
CT=(6.641·LS·WS)+(34.531·LT·WT/Tox)fF  (eq. 20)
where LS, WS, LT, and WTare all in microns and Toxis in nm. The load resistance RL(106) is given by VL/(Ig+IS), wherein as described above, VLis the voltage across the output resistor and is equal to about 0.05 volts. Using (eq. 12) and (eq. 13), and for a general case where a constant current source is included, the upper frequency roll-off point is expressed as:
FU={[(10·WS/LS)·μn·Ci·(Vgs−Vt)2]+IS}·1015/{2π·[(6.641·LS·WS)+(34.531·LT·WT/Tox)]}Hz  (eq. 21).

For the case where IS=0, it will be noted that WS, for a given LS, is determined by (eq. 12), which gives Ws as direct function of the tunneling gate current and the area of the tunneling RET104. If the gate capacitance of the tunneling RET104is much larger than that of the current source, then FUwill be independent of the area of the tunneling FET104. In any case, FUdecreases with increasing LS, and increases with increasing Vgs.

For the case when the parallel constant current source108is not zero, and if ISis greater than the gate current of the tunneling RET104, then the −3 dB frequency point will decrease with increasing area of the tunneling FET104. Again, FUwill decease with increasing LS, and increase with increasing Vgs. FUwill also increase with increasing value of the current source IS.

In order to illustrate the effect of the above described design parameters on the amplifier output gain and −3 dB upper frequency (FU), 4 design examples (cases) are considered and are presented in Table 1.

Using the parameters specified in Case1,FIGS. 7 and 8illustrate, respectively, the gain and −3 dB (FU) frequency point as a function of channel length of the common source amplifier with source degeneration102. These results show, as expected, increasing gain with increasing LSand Vgs. In addition, FUincreases with Vgsbut decreases with increasing LS. It will be noted that for the range of LSindicated in the Figures, WSfor the common source amplifier with source degeneration is determined from (eq. 12) and is required to be equal to or greater than 0.3 μm. As an example, inFIGS. 7 and 8, for Vgs=0.75 V, the area of the tunneling FET cannot be less than 1.0 μm2, so that WSis not less than 0.3 μm.

Using the parameters specified in Case2,FIGS. 9 and 10illustrate, respectively, the gain and FUas a function of channel length of the common source amplifier with source degeneration102. In this example, Toxfor the tunneling FET104is increased to 1.2 nm (from 1.0 nm in case1), thereby causing FUto be lower than for Case1but without affecting the gain. In Case3, a constant current source of 2 mA is added as compared to the parameters of Case2. The gain and FUas a function of channel length of the common source amplifier with source degeneration102are shown inFIGS. 11 and 12, respectively. Consistent with the trends depicted in Table 1, the gain in Case3is lower than that for Cases1and2, while the −3 dB point is higher. Lastly, for Case4, FUis increased with respect to Case3as the area of the tunneling FET104is increased. Again, the gain and FUas a function of channel length of the common source amplifier with source degeneration102are shown inFIGS. 13 and 14, respectively.

Finally,FIG. 15is a schematic diagram illustrating a differential version of a tunneling amplifier circuit200, in accordance with a further embodiment of the invention. As is shown, the differential tunneling amplifier circuit200includes a pair common source amplifiers with source degeneration202a,202b, the gate terminals of which represent the differential voltage input. In addition, a pair of tunneling gate FETs204a,204b, are used to set the transconductance of the circuit, wherein the tunneling gate FETs are cross-coupled to one another for equal loading on the differential pair. In other words, the gate terminal of tunneling FET204ais coupled to the source of common source amplifier with source degeneration202a, while the source and drain terminals of tunneling FET204aare coupled to the source of common source amplifier with source degeneration202b. Similarly, the gate terminal of tunneling FET204bis coupled to the source of common source amplifier with source degeneration202b, while the source and drain terminals of tunneling FET204bare coupled to the source of common source amplifier with source degeneration202a. Furthermore, in addition to a common-mode load circuit206a,206bcoupled to the drain of respective common source amplifiers with source degeneration202a,202b, a differential-mode load circuit207may be coupled between the drain terminals of the common source amplifiers with source degeneration202a,202b. The differential mode load207could include, for example, back-to-back tunneling devices for precise gain control. It is further noted that the circuit200includes a pair of current sources208a,208b. Common-mode load206aand206bare connected, respectively, to supply voltages210aand210b.

As will be appreciated, the above described invention embodiments provide an amplifier circuit that advantageously utilizes the gate tunneling current of an ultra-thin oxide FET by using this current as the drain current for a thick oxide common source amplifier with source degeneration. As such, the transconductance Gmof the amplifier circuit is dictated by the constant tunneling current, while the output conductance Gdsis controlled by the common source amplifier with source degeneration. Accordingly, this configuration provides the capability of independent control of the transconductance and output conductance by designing a tunneling FET having an ultra thin gate oxide in conjunction with a common source amplifier with source degeneration with a thick gate oxide. Furthermore, the amplifier is resistant to hot carrier effects, and thus resistant to time dependent degradation of gain due to hot carriers.

Moreover, selective optimization of the gain and the −3 dB frequency point can be made with respect to several parameters such as Vds, Vgs, channel length and width for common source amplifier with source degeneration, as well as area, gate voltage, and oxide thickness of the tunneling RET. In this manner, the particular selection of FET parameters may also be used, for example, to reduce the total area required for the amplifier circuit (i.e., to determine a trade off between performance and device area need). Still another means of optimizing the gain and frequency performance of the amplifier is through the use of a constant current source in parallel with the tunneling FET, which also allows for higher oxide thicknesses for the tunneling FET. In addition, as also disclosed herein, a differential form of the tunneling amplifier may be utilized for precise control of the circuit gain.