Embedded package in PCB build up

An apparatus including a printed circuit board including a body of a plurality of alternating layers of conductive material and insulating material; and a package including a die disposed within the body of the printed circuit board. A method including forming a printed circuit board including a core and a build-up section including alternating layers of conductive material and insulating material coupled to the core; and coupling a package including a die to the core of the printed circuit board such that at least a portion of a sidewall of the package is embedded in at least a portion of the build-up section. An apparatus including a printed circuit board including a body; a computing device including a package including a microprocessor disposed within the body of the printed circuit board; and a peripheral device that provides input or output to the computing device.

FIELD

Printed Circuit Boards.

BACKGROUND

Mobile and handheld products are trending towards thinner form factors. Studies show that consumers are willing to pay for thinner and lighter devices to achieve true mobility. Thus device manufacturers are putting emphasis on engineering resources to satisfy consumers.

DETAILED DESCRIPTION

One component of a computing device that affects an overall thickness of a device, particularly mobile and handheld products, is the motherboard. Currently, a thickness of mobile handheld devices, including mobile personal computers (PCs) and notebooks, is limited by a total of a motherboard stack over the keyboard due to the physical size of the motherboard. Even where the motherboard is installed at a similar level to a battery and other discreet boards, the size of the motherboard impacts these components, such as impacts the battery size which is a key performance specification. One technique to reduce a thickness or Z height and/or a motherboard size is utilizing a high density interconnect (HDI) printed circuit board process. Generally, the HDI process utilizes build up layers on a multilayer core with laser drilled microvias on each buildup to perform signal connections as opposed to a conventional type3printed circuit board that uses plated through holes. The use of the laser drilled microvia process in the HDI process enables higher density routing with smaller dimensioned interconnect vias, hence reducing the total board size as well as z-height.

A printed circuit board such as a motherboard is used to mechanically support and electrically connect an electronic component such as a microprocessor or application processor.FIG. 1shows a cross-sectional side view of a portion of a printed circuit board having an embedded component, in this case a package including a microprocessor (e.g., central processing unit, system on chip), connected to the core of the printed circuit board. Referring toFIG. 1, in this embodiment, printed circuit board110includes core120of an insulative material such as a prepreg material onto which conductive planes (e.g., ground plane, power plane) or tracks or pathways or signal traces are formed. In this embodiment, a top conductive plane or signal line includes an array of conductive pads160that may be connected to the conductive plane of signal line or other planes or signal lines through, for example, conductive microvias. Pads160are configured for and are aligned to connect to conductive pads or points of package140. Package140is, for example, a flip-chip package (e.g., ultra thin core flip-chip package) or a Bumpless Build-Up Layer (BBUL) package having, for example, a land grid array defining contact points, lands or pads165to connect to conductive pads160. The connection of contact points165to conductive pads may be through solder connections or, in another embodiment through a conductive paste, such as an anisotropic conductive film (ACF) epoxy adhesive.FIG. 1also shows die150that is, for example, a microprocessor, connected to package140on a side opposite the side in contact with conductive pads160.

As noted above, package140is connected to a pad array on core120of printed circuit board110. Package140including die150is embedded in circuit board110in the sense that since it is coupled to the core at its base and buildup layers of a printed circuit board surround the opposing sides of the package.FIG. 1shows buildup layer portion130A and buildup layer portion130B connected to core120. Each of buildup layer portion130A and buildup layer portion130B includes alternating layers of conductive material and dielectric material. The conductive material forms, for example, planes, signal traces or pathways while the insulating material insulates one conductive layer from another. In the embodiment shown inFIG. 1, each of buildup layer portion130A and buildup layer portion130B includes two build up layers (e.g., two layers of conductive material and insulating material). It is appreciated that in other embodiments, less than or more than two buildup layers may be utilized and the number of layers of conductive material and insulating material need not be the same in each of buildup layer portion130A and buildup layer portion130B.

In the embodiment shown inFIG. 1, package140includes contact points, lands or pads165on a bottom side of the package (as viewed) as well as contact points, lands or pads170on a topside (device side). Contact points, lands or pads165and contact points, lands or pads170may be used to connect to printed circuit board110. Additionally, contact points, lands or pads165and contacts points, lands or pads170may be utilized to connect package140to a device external to the printed circuit board, such as a memory device (e.g., a dynamic random access memory (DRAM)).FIG. 1shows conductive microvias180formed, for example, by a laser drill process connecting to contact points of external device190A through a contact material such as a solder ball. Similar microvias may be used to connect one or more contact points of device190B with package140.

As noted, in the embodiment shown inFIG. 1, package140and die150are embedded in printed circuit board110in the sense that at least package140, and opposing sides and a bottom of die150are surrounded by a material of buildup layer portion130A. By embedding package140and die150in printed circuit board110, it can be seen that a z-height of the board and package is reduced as the package and die are no longer connected to contact points on a surface (e.g., a superior surface (as viewed)) of printed circuit board110. The z-height is reduced in the sense that the z-height of printed circuit board110and package140is the z-height of printed circuit board110as package140is no longer connected to contact points on a superior surface of printed circuit board110. Also, in this embodiment, a portion of a topside of die150is exposed. In one embodiment, overlying chip150on a surface of printed circuit board110(top surface as viewed) may be a heat-transfer device198, such as heat spreader, or other device.

FIG. 2shows another embodiment of a printed circuit board including an embedded package. In this embodiment, printed circuit board210, such as an HDI printed circuit board, includes core220of an insulating material having one or more planes and/or pathways or signal traces. Overlying a surface of core220is an array of contact points lands or pads260positioned to connect and connected to an array of contact points, lands or pads265of package240. Package240is, for example, a flip-chip package or a BBUL package having contact points265as a land grid array patterned to connect to conductive points260through, for example, a solder connection or ACF.

Referring toFIG. 2, package240including die250is embedded in buildup layers of printed circuit board210.FIG. 2shows buildup layer portion230A and buildup layer portion230B connected to core220with package240including die250embedded in buildup layer portion230A. Buildup layer portion230A and buildup layer portion230B are each defined by are alternating layers of conductive material and insulating material. In the embodiment shown inFIG. 2, buildup layer portion230A and buildup layer portion230B each include two conductive layers and two insulating layers. It is appreciated that in other embodiments, less than or more than two conductive layers may be included and the number of conductive and insulating layers may be different for each of buildup layer portion230A and buildup layer portion230B.

In the embodiment shown inFIG. 2, package240includes contact points, lands or pads265on a bottom surface thereof (as viewed). Package240also includes contact points, lands or pads270as a land grid array on a superior or device side surface. As noted, contact points or pads260are connected to contact points260on core220that are connected to signal lines or planes (ground planes, power planes). In this embodiment, contact points or pads270on a superior surface of package240may be connected to signal traces or planes associated with buildup layer portion230A and/or to an external device.FIG. 2shows external device290that is, for example, a memory device (e.g., a DRAM device) connected to contact points270thorough conductive microvias280in buildup layer portion230A.

In the embodiment shown inFIG. 2, package240including die250is embedded in buildup layer portion230A. In this embodiment, the buildup layers surround sides and a top or superior surface each of package240and die250so that the package and die are completely embedded within printed circuit board210. By completely embedding package240and die250within the circuit board210, it can be seen that the z-height of the printed circuit board and package is reduced to that of the z-height of the printed circuit board as the package and die are no longer connected to contact points on a surface of the printed circuit board but the package is embedded in the printed circuit board.

FIGS. 3-6describe a process of forming a printed circuit board with an embedded package. In this embodiment, the process relates to forming a printed circuit board/embedded package similar to structure200shown inFIG. 2. Referring toFIG. 3,FIG. 3shows printed circuit board core310that is, for example, a core formed according to an printed circuit board process. Core310is, for example, a multilayer core including dielectric layer315of, for example, a prepreg material onto which conductive and insulative layers are introduced, such as by a film process wherein a film or sheet of insulative material and conductive material are alternately laid on, in this case, opposite sides of core315.FIG. 3shows conductive layer320A and conductive layer320B of, for example, a copper that is, for example, is a conductive material that serves as, for example, a power or ground plane or pathway or signal trace. A plane, such as a ground plane or power plane may simply be a conductive sheet or may be patterned as desired. Similarly, where conductive layer320A is a pathway or signal trace, the layer may be patterned. A film or sheet may be patterned using photolithographic and etch techniques.

Overlying respective ones of conductive layer320A and conductive layer320B is insulating layer325A and325B. Insulating layer325A and insulating layer325B may be introduced as a film or sheet of, for example, a prepreg material to a thickness suitable to insulate conductive layer320A and conductive layer320B, respectively. Overlying respective lines of insulating layer325A and insulating layer325B is conductive layer330A and330B similar to conductive layer320A and320B, each of conductive layer330A and conductive layer330B may be a power or ground plane or pathway or signal trace. Where desired, each conductive layer may be patterned as is appropriate. The total number of conductive layers and insulating layers can be more or less than illustrated.

Overlying conductive layer330A on a surface of core310are an array of contact points, lands or pads335. Contact points335are a conductive pattern resulting from an etching and plating process. Contact points335may be arranged in an array to correspond to an array of contact points, lands or pads of a package to be placed on core310. Overlying contacts points335, in one embodiment, is bonding material340. In one embodiment, bonding material340is a conductive adhesive such as an epoxy adhesive such as anisotropic film (ACF). In another embodiment, bonding material340may be a solder material. An advantage to a conductively adhesive for bonding material340is that it will tend to increase the reliability of the circuit board contact point to package contact point connection while providing a relatively minimal z-height contribution.

FIG. 4shows the structure ofFIG. 3following the introduction of package345onto core310. In one embodiment, package345is a flip-chip package including device350such as a die including a microprocessor. In another embodiment, package345is a BBUL package. On a bottom side of package345(as viewed) the package includes an array of contact points, lands or pads360arranged, for example, as a land grid array. The array of contact points360may be aligned with one or more of contact points335on core310. In this manner, desired ones of the array of contact points360may be connected to contact points335using, for example, bonding material340(e.g., a conductive epoxy adhesive).

A superior or device side of package345in the embodiment shown inFIG. 4, also, includes contact points, lands or pads365. Contact points365may be routed to signal lines or traces or planes associated with core310subsequent build up layers and/or a device that could be external to the ultimate printed circuit board that is fabricated.

FIG. 5shows the structure ofFIG. 4with package345connected to core310and shows the addition of buildup layers to the printed circuit board structure. Buildup layers may be introduced using an HDI printed circuit board process wherein a film or sheet of conductive or insulative material is introduced. In the embodiment shown inFIG. 5, package345and die350extend from a superior surface (surface332A) of core310. Accordingly, a film or sheet of insulating or conductive material cannot be directly applied to core310as a conventional HDI printed circuit board process without contacting package345and/or die350. Therefore, in one embodiment, prior to applying an insulating or conductive material as a sheet or film, an opening having dimensions equivalent to the dimensions of the wider of package345and die350is made in the films where necessary to place the film(s) on core310. One way an opening may be made in a film or a sheet is by a laser cutting process. Once an opening is made, the film(s) may be introduced onto core310.FIG. 5shows insulating film370being introduced initially on core310and on surface332A of conductive layer330A. In one embodiment, insulating film370A is a prepreg material introduced to a desired thickness as an insulator in an HDI printed circuit board process. Overlying insulating layer370A is conductive film375A of, for example, a copper material. Conductive layer375A may be introduced as a sheet and, where necessary, patterned, using, for example, photolithography and etch techniques. The addition of buildup layers to core310may continue as desired.FIG. 5shows additional buildup layers of insulating film380A and conductive film385A to define a buildup layer portion on one side of core310. It is appreciated that where an opening are formed in a film prior to the film being applied to the core, the opening in such film need only be as large of an area as necessary or desired to surround package345and/or die350. Accordingly, an area of an opening of insulating layer380A and/or conductive film385A may be less than an area of openings in conductive film375A and/or insulating film370A.FIG. 5finally shows insulating films370B and380B and conductive films375B and385B defining another buildup layer portion on a second side of core310.

FIG. 6shows the structure ofFIG. 5following the introduction of multiple buildup layers on core310. In this embodiment, two pairs of conductive and insulative layers constitute the buildup layers. It is appreciated, that the buildup layers may consist of less than or more than two pairs of buildup layers. Referring toFIG. 6, the structure shows insulating layer370A on a superior surface of core310and insulating layer370B on the bottom surface of core310. Overlying insulating layer370A is conductive layer375A and underlying insulating layer370B is conductive layer375B. Overlying conductive layer375A is insulating layer380A and underlying conductive layer375B is insulating layer380B. Overlying conductive layer375A is insulating layer380A followed by conductive layer385A. Underlying conductive layer375B is insulating layer380B followed by conductive layer385B. It is appreciated that in addition to introducing insulating and conductive layers or core310, a HDI printed circuit board process may be followed. This includes patterning conductive films as desired (e.g., through photolithography and etch techniques) and locating and forming conductive microvias by way of, for example, laser drilling and filling operation.

FIG. 6illustrates a printed circuit board including an embedded package therein. The z-height of the printed circuit board and package is equivalent to a z-height of the printed circuit board. In this embodiment, package345includes contact points, pads or lands on a superior on top side surface (as viewed) contact points or pads365provide an increased density of second level of interconnects that allows for signal breakout on the superior side of the board and improves signal integrity performance with shorter signal paths to component(s) that are placed on a superior side of the die. Embedding package345in a printed circuit board also eliminates the need for an interposer that has been used, for example, in package on package configurations, since the build-up layer portion around package345can function as an interposer. Further, power delivery is improved since decoupling capacitors can be mounted directly on top of die350as viewed (e.g., directly on top of a central processing unit or system on a chip). In another embodiment, one or more decoupling capacitors may be embedded.

To form the structure ofFIG. 1, the insulating and/or conductive build-up films of the printed circuit board may be applied with an opening to expose a surface of die350or the opening(s) may be cut in the film(s) after their introduction. Representatively, a die350can be a device operating at higher power where it may be desirable to include thermal dissipation. In such an embodiment, a heat spreader or other thermal solution may be introduced on an exposed surface of the die (seeFIG. 1). Additional devices (e.g., a DRAM device) can then be mounted beside the heat spreader using, for example, an embedded conducting film (e.g., a microstrip) to perform the input/output connection through microvias.

In each of the embodiments described with reference toFIG. 1andFIG. 2and the process ofFIGS. 3-6, a single component, a die, is embedded in a printed circuit board. In another embodiment, additional components may be embedded using the same techniques.

FIG. 7illustrates a computing device400in accordance with one implementation of the invention. Computing device400houses board402. Board402may include a number of components, including but not limited to processor404and at least one communication chip406. Processor404is physically and electrically coupled to board402. In some implementations the at least one communication chip406is also physically and electrically coupled to board402. In further implementations, communication chip406is part of processor404.

Processor404of computing device400includes an integrated circuit die packaged within processor404. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as transistors and CMOS implementations, that are formed in accordance with embodiments herein. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Communication chip406also includes an integrated circuit die packaged within communication chip406. In accordance with another implementation, the integrated circuit die of the communication chip includes one or more devices, such as transistors and CMOS implementations, that are formed in accordance with implementations described above.

In further implementations, another component housed within computing device400may contain an integrated circuit die that includes one or more devices, such as transistors and CMOS implementations, that are formed in accordance with implementations described above

In the description above, for the purposes of explanation, numerous specific details have been set forth in order to provide a thorough understanding of the embodiments. It will be apparent however, to one skilled in the art, that one or more other embodiments may be practiced without some of these specific details. The particular embodiments described are not provided to limit the invention but to illustrate it. The scope of the invention is not to be determined by the specific examples provided above but only by the claims below. In other instances, well-known structures, devices, and operations have been shown in block diagram form or without detail in order to avoid obscuring the understanding of the description. Where considered appropriate, reference numerals or terminal portions of reference numerals have been repeated among the figures to indicate corresponding or analogous elements, which may optionally have similar characteristics.

It should also be appreciated that reference throughout this specification to “one embodiment”, “an embodiment”, “one or more embodiments”, or “different embodiments”, for example, means that a particular feature may be included in the practice of the invention. Similarly, it should be appreciated that in the description various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects may lie in less than all features of a single disclosed embodiment. Thus, the claims following the Detailed Description are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment of the invention.