OXIDE LAYER DOPING ON A SUB CHANNEL OF A TRANSISTOR STRUCTURE

Embodiments described herein may be related to apparatuses, processes, and techniques related to minimizing sub channel leakage within stacked GAA nanosheet transistors by doping an oxide layer on top of the sub channel. In embodiments, this doping may include selective introduction of charge species, for example carbon, within the gate oxide layer. Other embodiments may be described and/or claimed.

FIELD

Embodiments of the present disclosure generally relate to the field of semiconductor packaging, and in particular to oxide layers on sub channels.

BACKGROUND

Continued growth in virtual machines, cloud computing, and portable devices will continue to increase the demand for high density transistors within chips and packages.

DETAILED DESCRIPTION

Embodiments described herein may be related to apparatuses, processes, and techniques directed to minimizing sub channel leakage within stacked GAA nanosheet transistors by introducing dopants in oxide layer on top of the sub channel. In embodiments, this doping may include selective introduction of charge species, for example carbon, within the gate oxide layer. In embodiments, the doping may be referred to as introducing electrically active defects into the gate oxide layer. By doping the oxide layer next to the sub channel, which may also be referred to as a parasitic transistor, and not doping oxide layers in the channels above the sub channel, this will in effect turn off or greatly reduce leakage in the sub channel. This may also be referred to as reducing the electric participation of the sub channel. As a result, in embodiments, power dissipation is decreased and performance of GAA transistors is improved.

In legacy implementations of stacked GAA nanosheet transistors, sub channel leakage is a limiting aspect that affects performance and usability. Sub channel leakage includes a parasitic leakage path due to inferior electrostatics at the sub channel, or the bottom-most surface, which could be a silicon substrate. Sub channel leakage is analogous to sub-fin leakage in FinFET devices. Legacy techniques to reduce sub-fin leakage may be used in GAA devices in attempt to solve the sub channel leakage. One of these legacy techniques include doping of the silicon substrate both under the channels above the sub channel to increase the local threshold voltage and under the epitaxial layers (source/drain) to reduce punch through or leakage under the contacts. Another legacy technique is to use a thick dielectric on the sub channel to isolate the sub channel (substrate) from both the channel and source/drain contacts. This technique controls the electric field in a lateral or horizontal direction with respect to a top surface of the sub channel. These legacy implementations not only produce additional complexity to manufacturing process flow, but also require tighter controls during manufacturing. Embodiments described herein may be used to control the electric field in a direction perpendicular to the top surface of the sub channel by creating a local dipole in the oxide, therefore improving reliability.

Various Figures herein may depict one or more layers of one or more package assemblies. The layers depicted herein are depicted as examples of relative positions of the layers of the different package assemblies. The layers are depicted for the purposes of explanation, and are not drawn to scale. Therefore, comparative sizes of layers should not be assumed from the Figures, and sizes, thicknesses, or dimensions may be assumed for some embodiments only where specifically indicated or discussed.

FIG.1illustrates a GAA FET with stacked nanosheet transistors on a sub channel that includes a doped oxide, in accordance with various embodiments. GAA FET100includes a sub channel102, which may also be referred to as a substrate102that is in contact with a source104and a drain106. In embodiments, the source104may be referred to as an epitaxial source, and the drain106may be referred to as an epitaxial drain. A plurality of channels108are above the sub channel102, and also coupled with the source104and the drain106. In embodiments, the channels108may be nanoribbons or nanosheets that may include silicon.

In embodiments, an oxide layer110, which may also be referred to as a gate oxide, may be coupled with each of the channels108. The area between each of the channels108may include a spacer112, a dielectric114, which may be a high-k dielectric and a metal gate116. In embodiments, a conductor119may be included inside the metal gate116, and may be used for interconnects. Note that each of the oxide layers110maybe legacy oxide layers without any special doping or electrically active defects, such as carbon atoms, added.

Oxide layer120, above sub channel102, has been modified to include electrically active defects, such as carbon atoms, within the oxide layer120. In embodiments, the oxide layer120may be referred to as having been doped. Because these active defects are introduced within the oxide layer120, they electrically modify the control voltage, the voltage at which a transistor will turn on, for the sub channel102and make the control voltage large enough so that the transistor of the sub channel102will not turn on, even though the channels108will turn on. This may also be referred to as suppressing sub channel102leakage.

FIGS.2A-2Fillustrate manufacturing stages in a process for creating stacked nanosheet transistor on a sub channel that includes a doped oxide, in accordance with various embodiments.FIG.2Aincludes first cross section side view200A1and an orthogonal cross section side view200A2of a sub channel202, that may be similar to sub channel102ofFIG.1. Sub channel202may include silicon, and may be part of a polysilicon layer203.

FIG.2Bincludes a first cross section side view200B1and an orthogonal cross section side view200B2of the result of a implanting process indicated by arrows205used to implant atoms207below a surface of the sub channel202. The implanted atoms207may also be referred to as introducing species or introducing defects within the sub channel202embodiments, carbon atoms may be used because they form electrically active defect levels that are favorable to reduce the leakage in the local sub channel region, and do not affect other parts of the transistor.

FIG.2Cincludes a first cross section side view200C1and an orthogonal cross section side view200C2that show the buildup of multiple channels. In embodiments, layers of a sacrificial material209, that may include silicon germanium (SiGe), may be progressively placed and onto which channels208, which may be similar to channels108ofFIG.1, may be formed. As shown, four channels208are created. In embodiments, these channels208may include silicon, or some other semiconductors suited for FET devices like Ge and may also include 2D materials such as WSe2, Ws2 etc. In embodiments, the channels208may be nanowires, nanosheets or nanoribbons. In embodiments, the application of the sacrificial material209will not significantly affect the positioning of the atoms207within the sub channel202. Note that for clarity of illustration forFIGS.2C-2F, other portions of the transistor shown inFIG.1may not be shown.

FIG.2Dincludes a first cross section side view200D1and an orthogonal cross section side view200D2where the sacrificial material209fromFIG.2Cis removed, leaving the channels208above the sub channel202.

FIG.2Eincludes a first cross section side view200E1and an orthogonal cross section side view200E2where an oxide layer210is placed around the channels208and an oxide layer220is placed over the sub channel202. The oxide layer210,220, which may be similar to oxide layer110,120ofFIG.1, may be deposited using atomic layer deposition(ALD) or chemical vapor deposition (CVD) techniques. The oxide layer210,220may also be referred to as a gate oxide layer, and may be the same oxide material, that may include dielectrics used as gate oxides such as aluminum oxide, silicon-germanium oxide, zirconium oxide.

FIG.2Fincludes a first cross section side view200F1and an orthogonal cross section side view200F2where an annealing process is applied to provide heat which will cause the atoms207ofFIG.2Eto migrate in a direction211to form atoms213within the oxide layer220. These defects segregate in the oxide and remain local to the sub channel region. In embodiments, there may be some atoms207ofFIG.2Ewithin sub channel202that have not fully migrated into the oxide layer220. As a result of the annealing process, a better quality oxide210is formed around the channels208increasing their electrical performance, and the doped oxide layer220above the sub channel202decreases its electrical performance, thereby reducing electrical leakage through the sub channel202.

FIGS.3A-3Gillustrate manufacturing stages in another process for creating stacked nanosheet transistor on a sub channel that includes a doped oxide, in accordance with various embodiments.FIG.3Aincludes first cross section side view300A1and an orthogonal cross section side view300A2of a sub channel302, that may be similar to sub channel102ofFIG.1. Sub channel302may include silicon, and may be part of a polysilicon layer303.

FIG.3Bincludes a first cross section side view300B1and an orthogonal cross section side view300B2that show the buildup of multiple channels. In embodiments, layers of a sacrificial material309, which may be similar to sacrificial material209ofFIG.2C, that may include SiGe, may be progressively placed onto which channels308, which may be similar to channels108ofFIG.1. As shown, four channels308are created. In embodiments, these channels308may include silicon, silicon-germanium, germanium or some other material suitable for channels such as 2D materials. In embodiments, the channels308may be nanowires, nanosheets or nanoribbons. Note that for clarity of illustration forFIGS.3B-3G, other portions of the transistor shown inFIG.1may not be shown.

FIG.3Cincludes a first cross section side view300C1and an orthogonal cross section side view300C2where the sacrificial material309fromFIG.3Bis removed, leaving the channels308above the sub channel302.

FIG.3Dincludes a first cross section side view300D1and an orthogonal cross section side view300D2where a layer of electrically active defects324is applied onto the sub channel302. In embodiments, the layer324may be applied using atomic layer deposition (ALD) process. The layer324may include carbon atoms, for example C6H19N3Si.

FIG.3Eincludes a first cross section side view300E1and an orthogonal cross section side view300E2where a flare/flash anneal process is applied. In embodiments, this anneal process may be performed in an inert ambient such as an argon (Ar) ambient, which disassociates the long carbon ligands in the layer of electrically active defects324that may then be chemisorbed into the surface of the sub channel302as dimers. As a result, the atoms307, which may be carbon atoms, are moved into the surface of the sub channel302.

FIG.3Fincludes a first cross section side view300F1and an orthogonal cross section side view300F2where the layer of electrically active defects324is removed, and an oxide layer310, which may be similar to oxide layer210ofFIG.2Eis placed around the channels308and an oxide layer320, which may be similar to oxide layer220ofFIG.2E, is placed over the sub channel302. The oxide layers310,320, may be deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques. The oxide layer310,320may also be referred to as a gate oxide layer, and may be the same oxide material, that may include silicon di-oxide, aluminum oxide etc.

FIG.3Gincludes a first cross section side view300G1and an orthogonal cross section side view300G2where an annealing process is applied to provide heat which will cause the atoms307ofFIG.3Fto migrate in a direction311to form atoms313within the oxide layer320. In embodiments, there may be some atoms307ofFIG.3Fwithin sub channel302that have not fully migrated into the oxide layer320. As a result of the annealing process, a better quality oxide layer310is formed around the channels308increasing their electrical performance, and the doped oxide layer320above the sub channel302decreases its electrical performance, thereby reducing electrical leakage through the sub channel302.

FIG.4illustrates an example process for creating a stacked nanosheet transistor on a sub channel that includes a doped oxide, in accordance with various embodiments. Process400may be performed using the techniques, processes, apparatus, and/or systems as described herein and particularly with respect toFIGS.1-3G.

At block402, the process may include identifying a sub channel of a gate structure.

At block404, the process may further include forming an oxide layer on a side of the sub channel, wherein the oxide layer includes electrically active defects.

A plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFET or simply MOS transistors), may be fabricated on the substrate. In various implementations of the invention, the MOS transistors may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or gate-all-around transistors such as nanoribbon and nanowire transistors. Although the implementations described herein may illustrate only Finfet transistors, it should be noted that the invention may also be carried out using planar transistors.

The gate electrode layer is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.

In some implementations of the invention, a pair of sidewall spacers may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching/deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

One or more interlayer dielectrics (ILD) are deposited over the MOS transistors. The ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (SiO2), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant.

FIG.5illustrates a computing device500in accordance with one implementation of the invention. The computing device500houses a board502. The board502may include a number of components, including but not limited to a processor504and at least one communication chip506. The processor504is physically and electrically coupled to the board502. In some implementations the at least one communication chip506is also physically and electrically coupled to the board502. In further implementations, the communication chip506is part of the processor504.

The processor504of the computing device500includes an integrated circuit die packaged within the processor504. In some implementations of the invention, the integrated circuit die of the processor includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention. The term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

The communication chip506also includes an integrated circuit die packaged within the communication chip506. In accordance with another implementation of the invention, the integrated circuit die of the communication chip includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention.

In further implementations, another component housed within the computing device500may contain an integrated circuit die that includes one or more devices, such as MOS-FET transistors built in accordance with implementations of the invention.

FIG.6illustrates an interposer600that includes one or more embodiments of the invention. The interposer600is an intervening substrate used to bridge a first substrate602to a second substrate604. The first substrate602may be, for instance, an integrated circuit die. The second substrate604may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer600is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer600may couple an integrated circuit die to a ball grid array (BGA)606that can subsequently be coupled to the second substrate604. In some embodiments, the first and second substrates602/604are attached to opposing sides of the interposer600. In other embodiments, the first and second substrates602/604are attached to the same side of the interposer600. And in further embodiments, three or more substrates are interconnected by way of the interposer600.

The interposer600may include metal interconnects608and vias610, including but not limited to through-silicon vias (TSVs)612. The interposer600may further include embedded devices614, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radiofrequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer600. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer600.

The above description of illustrated embodiments, including what is described in the Abstract, is not intended to be exhaustive or to limit embodiments to the precise forms disclosed. While specific embodiments are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the embodiments, as those skilled in the relevant art will recognize.

These modifications may be made to the embodiments in light of the above detailed description. The terms used in the following claims should not be construed to limit the embodiments to the specific implementations disclosed in the specification and the claims. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.

EXAMPLES

Example 1 is a gate structure comprising: a sub channel; and an oxide layer on a side of the sub channel, wherein the oxide layer includes electrically active defects.

Example 2 includes the gate structure of example 1, wherein the electrically active defects include carbon atoms.

Example 3 includes the gate structure of example 1, further comprising a channel above the sub channel, wherein the channel includes an oxide layer that does not include electrically active defects.

Example 4 includes the gate structure of example 3, wherein the channel is a nanoribbon.

Example 5 includes the gate structure of example 4, wherein the nanoribbon is a silicon nanoribbon.

Example 6 includes the gate structure of example 2, further comprising a source and a drain that electrically couple the sub channel with the channel.

Example 7 includes the gate structure of example 1, wherein the sub channel includes silicon.

Example 8 includes the gate structure of example 1, wherein the sub channel is a portion of a substrate.

Example 9 includes the gate structure of example 1, wherein a portion of the sub channel proximate to the oxide layer includes electrically active defects.

Example 10 includes the gate structure of any one of examples 1-9, wherein the gate structure is a portion of a gate all around (GAA) transistor structure.

Example 11 is a method comprising: identifying a sub channel of a gate structure; and forming an oxide layer on a side of the sub channel, wherein the oxide layer includes electrically active defects.

Example 12 includes the method of example 11, wherein forming an oxide layer further includes: implanting electrically active defects into a side of the sub channel; applying an oxide layer to the side of the sub channel; and moving at least a portion of the electrically active defects into the oxide layer by performing an annealing process.

Example 13 includes the method of example 12, wherein after implanting electrically active defects, the method further comprising: applying a sacrificial layer to the side of the sub channel; forming a channel on top of the sacrificial layer; removing the sacrificial layer; and applying an oxide layer to a side of the formed channel.

Example 14 includes the method of example 13, wherein the sacrificial layer includes silicon and germanium.

Example 15 includes the method of example 13, wherein the sub channel and the channel include silicon.

Example 16 includes the method of example 11, wherein forming an oxide layer further includes: applying a layer that includes electrically active defects to the side of the sub channel; moving at least a portion of the electrically active defects within the applied layer into the sub channel by performing an annealing process; removing the applied layer to expose the side of the sub channel; applying an oxide layer on the side of the sub channel; and moving at least a portion of the electrically active defects in the sub channel into the oxide layer by performing an annealing process.

Example 17 includes the method of example 16, wherein the applied layer includes a selected one or more of carbon, hydrogen, nitrogen, and/or silicon.

Example 18 includes the method of example 16, wherein after applying the layer that includes electrically active defects, the method further comprising: applying a sacrificial layer to a side of the applied layer opposite the sub channel; forming a channel on top of the sacrificial layer; and removing the sacrificial layer.

Example 19 includes the method of example 18, wherein applying an oxide layer on the side of the sub channel further includes applying the oxide layer on a side of the channel.

Example 20 includes the method of any one of example 16-19, wherein the sub channel is a portion of a silicon substrate.

Example 21 is a transistor comprising: a sub channel; a plurality of channels above the sub channel; a source coupled with the sub channel and coupled with a portion, respectively, of the plurality of channels; a drain coupled with the sub channel and coupled with another portion, respectively, of the plurality of channels; an oxide layer, respectively, on each of the plurality of channels; and an oxide layer on the sub channel, wherein the oxide layer on the sub channel includes dopants.

Example 22 includes the transistor of example 21, wherein the doping includes carbon atoms.

Example 23 includes the transistor of example 21, wherein the plurality of channels above the sub channel are silicon nanoribbons.

Example 24 includes the transistor of example 21, wherein the oxide layer on each of the plurality of channels includes doping below a threshold level of 5E14cm-2.

Example 25 includes the transistor of any one of examples 21-24, wherein the sub channel is a portion of a silicon substrate.