Use of a biased precoat for reduced first wafer defects in high-density plasma process

According to various embodiments, the present teachings include methods for reducing first wafer defects in a high-density plasma chemical vapor deposition process. In an exemplary embodiment, the method can include running a deposition chamber for deposition of film on a first batch of silicon wafers and then cleaning interior surfaces of the deposition chamber. The method can further include inserting a protective electrostatic chuck cover (PEC) wafer on an electrostatic chuck in the deposition chamber and applying power to bias the PEC wafer while simultaneously precoating the deposition chamber with an oxide. The exemplary method can also include re-starting the deposition chamber for deposition of film on a second batch of silicon wafers.

FIELD OF THE INVENTION

The subject matter of this invention relates to chemical vapor deposition processes. More particularly, the subject matter of this invention relates to the use of a biased precoat process for reducing first wafer defects in high-density plasma chemical vapor deposition processes.

DESCRIPTION OF THE RELATED ART

High-density plasma (HDP) chemical vapor deposition (CVD) chambers, such as SPEED™ HDP CVD chambers manufactured by Novellus Systems, are employed to perform HDP CVD processes to deposit films on a substrate in the fabrication of integrated circuits. Existing HDP CVD processes typically perform film deposition with a processing gas mixture that includes oxygen, silane, and inert gases, such as helium, to achieve simultaneous dielectric etching and deposition. During film deposition, RF power is applied to an electrostatic chuck to bias a silicon wafer placed thereon. Some of the gas molecules are ionized in the plasma and accelerate toward the surface of the silicon wafer when the RF power is applied. Film material is thereby sputtered when the ions strike the wafer surface.

However, the film material is also deposited on all the surfaces of the deposition chamber exposed to the processing gas, including the interior surfaces of the deposition chamber. Therefore, the deposition chamber must be periodically cleaned to prevent a build-up of the excess film material from contaminating films deposited on the wafer, which can cause defects in the processed wafer. A conditioning step typically follows the cleaning step to bring the deposition chamber to an equilibrium state. During the conditioning step, a protective cover is placed on the electrostatic chuck to protect the chuck. RF power is not applied during the conditioning step to avoid damaging or breaking the protective cover, and thus the protective cover is unbiased.

After the deposition chamber is cleaned and conditioned, silicon wafers are inserted for film deposition and bias is applied to the wafers. Problems arise because the application of bias on the wafers, and in particular the first wafer after the cleaning and conditioning steps, causes gas flow patterns in the deposition chamber that dislodge loose material from the deposition chamber's dome and injectors. The dislodged material falls on the wafers and becomes embedded in the deposited film, which causes rip-outs during subsequent chemical-mechanical polishing, leading to wafer defects and yield losses.

Existing solution for reducing wafer defects and yield losses caused by dislodged material is to replace the dome and injectors of the deposition chamber. However, replacing the parts requires twelve to sixteen hours of unscheduled downtime on a fabrication tool. Therefore, there is a need to overcome these and other problems of the prior art to provide methods for reducing first wafer defects in high-density plasma chemical vapor deposition processes.

SUMMARY OF THE INVENTION

During high-density plasma chemical vapor deposition (HDP CVD) processing, the interior surfaces of the HDP CVD chamber are cleaned after processing a batch of silicon wafers. After the deposition chamber is cleaned, it is precoated with undoped and doped oxides to condition the deposition chamber. The exemplary methods of the invention provide for an application of high frequency (HF) radio frequency (RF) power to bias a protective electrostatic chuck cover (PEC) wafer via an electrostatic chuck during precoat, which replicates the chamber conditions of a subsequent HDP CVD process on silicon wafers. An application of 500 watts or more of HF RF power that biases the PEC wafer causes gas flow patterns in the deposition chamber that dislodge loose material and particles. If the PEC wafer is not biased during precoat, then the loose material would instead become dislodged when bias is initially applied to a silicon wafer in a film deposition process subsequent to the cleaning and precoat processes.

Furthermore, the application of HF RF power that biases the PEC wafer also produces gas flow patterns in the deposition chamber during precoat that are similar to the gas flow patterns during a subsequent film deposition on silicon wafers, which causes loose particles in the deposition chamber to fall on the PEC wafer during precoat instead of on the silicon wafers and in particular the first silicon wafer during film deposition subsequent to the cleaning and precoat processes. If the loose particles fall on the silicon wafers during film deposition, the loose particles would become embedded in the deposited film and cause rip-outs during chemical-mechanical polishing (CMP). By applying HF RF power that biases the PEC wafer during precoat, the loose particles fall on the PEC wafer instead of the silicon wafers, thereby minimizing yield losses caused by embedded loose particles.

According to various embodiments, the present teachings include a method for reducing first wafer defects that can include inserting a protective cover and applying power to bias the protective cover while simultaneously precoating the deposition chamber.

According to various embodiments, the present teachings include methods for reducing first wafer defects in a high-density plasma chemical vapor deposition process. In an exemplary embodiment, the method can include running a deposition chamber for deposition of film on a first batch of a plurality of silicon wafers and then cleaning interior surfaces of the deposition chamber. The method can further include inserting a PEC wafer on an electrostatic chuck in the deposition chamber and applying power to bias the PEC wafer while simultaneously precoating the deposition chamber with an oxide. The exemplary method can also include re-starting the deposition chamber for deposition of film on a second batch of a plurality of silicon wafers.

DETAILED DESCRIPTION

Referring toFIG. 1, which is a schematic view showing a semiconductor fabrication apparatus according to various embodiments of the present teachings. The fabrication apparatus, such as a Novellus SPEED™ HDP CVD apparatus, includes a deposition chamber100having an electrostatic chuck (E-chuck)130. Deposition chamber100can include an upper lid or dome105, typically made of a ceramic such as aluminum oxide (Al2O3). A gas manifold150connecting to deposition chamber100can be coupled to an inlet airflow controlling valve155. In various embodiments, E-chuck130is coupled to a radio frequency source (RF source)140. E-chuck130is configured to hold a wafer120during high-density plasma (HDP) chemical vapor deposition (CVD) processing, including film deposition, cleaning, precoat, and the like.

Wafer120can be a silicon wafer, a dummy wafer, or a protective cover such as a protective electrostatic chuck cover (PEC) wafer made of a ceramic including, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), silicon carbide (SiC), and the like. The PEC wafer can be used as a surrogate substrate to protect E-chuck130from exposure to plasma100created in exemplary methods of the invention. Gas manifold150can inlet processing gas used to form plasma110and the inlet airflow can be controlled by inlet airflow controlling valve155. Materials deposited during HDP CVD processing include, for example, phosphosilicate glass (PSG), fluorosilicate glass (FSG), undoped silicate glass (USG), and the like. One skilled in the art will appreciate that other materials can be deposited. During the precoat process, processing gases are introduced into deposition chamber100, and plasma110of the processing gases is generated within deposition chamber100to precoat the interior surfaces of deposition chamber100.

RF source140can provide 500 or more watts of RF power to bias wafer120via E-chuck130during HDP CVD processing. According to various embodiments, RF source140can provide 500 or more wafts of high frequency (HF) RF power to bias the PEC wafer during precoat. Applying bias to the PEC wafer can cause gas flow patterns in deposition chamber100that dislodge loose material on dome105and one or more injectors to form loose particles. If the PEC wafer is not biased during precoat, then the loose material would instead become dislodged when bias is initially applied to a silicon wafer during film deposition post-clean and post-precoat. Moreover, applying bias to the PEC wafer can produce gas flow patterns in deposition chamber100during precoat that are similar to the gas flow patterns during a subsequent film deposition on silicon wafers, and thus cause loose particles in deposition chamber100to fall on the PEC wafer during precoat instead of on the silicon wafers and in particular the first silicon wafer processed immediately subsequent to the cleaning and precoat processes. If the loose particles fall on the silicon wafers during film deposition, the loose particles would become embedded in the deposited film and cause rip-outs during chemical-mechanical polishing (CMP). By applying 500 or more watts of HF RF power to bias the PEC wafer during precoat, the loose particles fall on the PEC wafer instead of the silicon wafers during film deposition, thereby minimizing yield losses caused by embedded loose particles. One skilled in the art will appreciate that other methods can be used to electrically bias the PEC wafer to reduce first silicon wafer defects.

FIG. 2is a flowchart outlining an exemplary flow of a method, performed in deposition chamber100, for performing a biased precoat process during HDP CVD processing to reduce first wafer defects in accordance with various embodiments. One of ordinary skill in the art will appreciate that the flow diagram depicted inFIG. 2represents a generalized schematic illustration and that other steps may be added or existing steps may be removed or modified.

After performing film deposition on a number of silicon wafers, an accumulation of deposition material and other materials on the interior surfaces of deposition chamber100, and in particular on walls of dome105and the injectors, becomes problematic. For example, the accumulated material can flake off during film deposition and contaminate a film deposited on a silicon wafer. Therefore, deposition chamber100is typically cleaned and precoated after each processing cycle, such as after deposition a batch of five silicon wafers. As shown in step210, a PEC wafer can be inserted into deposition chamber100and placed on E-chuck130. The PEC wafer can be inserted after the last silicon wafer has been removed from deposition chamber100, either prior to the cleaning process or prior to the precoat process. In step220, a low frequency passivation is performed to passivate the interior surfaces of deposition chamber100in preparation for the precoat process.

Next, in steps230to250, precoat gases can be inlet into deposition chamber100and turned into plasma110to precoat the interior surfaces of deposition chamber100, and in particular the walls of dome105and the injectors, with various oxides. Precoat steps230to250bring deposition chamber100to an equilibrium state so that subsequent deposition of film onto silicon wafers yields consistent deposition rates. Depending on the nature of the oxide deposited, the precoat layer may consist of multiple layers of undoped and doped oxides to produce best adhesion properties.

According to various embodiments, in step250, RF source140can bias the PEC wafer by applying HF RF power to E-chuck130while deposition chamber100is being precoated with the doped oxide. Thus, the biased precoat process as shown in step250can simultaneously precoat deposition chamber100with the doped oxide and bias the PEC wafer. The application of bias on the PEC wafer can cause gas flow patterns in deposition chamber100that dislodge loose material on dome105and the injectors to form loose particles. If the PEC wafer is not biased during the precoat process, then the loose material would instead become dislodged when bias is initially applied to a silicon wafer in a film deposition process after the cleaning and precoat processes.

Therefore, the biased PEC wafer can cause the precoat gas and plasma110generated thereform to flow in a precoat gas flow pattern in deposition chamber100substantially identical to a processing gas flow pattern during subsequent film deposition. The precoat gas flow pattern can then cause loose particles in deposition chamber100to fall on and/or couple with the PEC wafer during the precoat process. If the PEC wafer is not biased, then the loose particles would fall on the silicon wafers and in particular the first silicon wafer during film deposition subsequent to the cleaning and precoat processes. If the loose particles fall on the silicon wafers during film deposition, the loose particles would become embedded in the deposited film and cause rip-outs during CMP. By applying HF RF power that biases the PEC wafer during precoat, the loose materials in interior surfaces of deposition chamber100become dislodged as loose particles during precoat, and the loose particles fall on the PEC wafer instead of the silicon wafers during film deposition, thereby minimizing yield losses caused by embedded loose particles.

According to various embodiments, RF source140can apply 500 or more wafts of HF RF power to bias the PEC wafer without damaging or breaking the PEC wafer. In an embodiment, RF source140can apply 500 or more watts of HF RF power to bias the PEC wafer to cause loose particles in deposition chamber100to fall on and/or couple with the PEC wafer during the precoat process, which reduces a defect rate of subsequently processed silicon wafers caused by the loose particles. Finally, in step260the PEC wafer is removed from deposition chamber100prior to commencing film deposition and/or other HDP CVD processes.

FIG. 3Aillustrates wafer defect counts for conventional HDP CVD processes in which the deposition chamber is cleaned and precoated after processing a batch of five silicon wafers and the PEC wafer is not biased during precoat.FIG. 3Billustrates wafer defect counts for exemplary HDP CVD processes that include a biased precoat process according to various embodiments of the invention. For example, as shown inFIG. 3A, wafer defect counts 305 for first silicon wafers processed subsequent to the cleaning and precoat processes can reach nearly 200 defects and average about 150 defects, which is about four times higher than wafer defect counts for the subsequently processed silicon wafers. In contrast, exemplary wafer defect counts 355 as shown inFIG. 3Baverage less than 35 defects for first silicon wafers processed subsequent to the cleaning and biased precoat processes, which translates to a greater than seventy-five percent reduction in first wafer defects.

One of ordinary skill in the art will recognize that the methods disclosed herein are exemplary and that the steps of the methods may be performed in a different order than illustrated or simultaneously. Further, it should be appreciated that, while the disclosed methods have been described in conjunction with HDP CVD semiconductor fabrication processes and apparatus, exemplary methods according to this disclosure are not limited to such applications. Exemplary embodiments of methods according to this disclosure can be advantageously applied to virtually any process and apparatus that perform vapor deposition to deposit a film on a substrate. Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.