SOI transistor having drain and source regions of reduced length and a stressed dielectric material adjacent thereto

By reconfiguring material in a recess formed in drain and source regions of SOI transistors, the depth of the recess may be increased down to the buried insulating layer prior to forming respective metal silicide regions, thereby reducing series resistance and enhancing the stress transfer when the corresponding transistor element is covered by a highly stressed dielectric material. The material redistribution may be accomplished on the basis of a high temperature hydrogen bake.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the subject matter disclosed herein relates to the formation of integrated circuits, and, more particularly, to the formation of transistors having strained channel regions by using stress sources, stressed overlayers and the like to enhance charge carrier mobility in the channel region of a MOS transistor.

2. Description of the Related Art

Generally, a plurality of process technologies are currently practiced in the field of semiconductor production, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region.

The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed near the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length is a dominant design criterion for accomplishing an increase in the operating speed and packing density of the integrated circuits.

The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is providing low sheet and contact resistivity in drain and source regions and any contacts connected thereto and maintaining channel controllability. For example, reducing the channel length may necessitate an increase of the capacitive coupling between the gate electrode and the channel region, which may call for reduced thickness of the gate insulation layer. Presently, the thickness of silicon dioxide based gate insulation layers is in the range of 1-2 nm, wherein a further reduction may be less desirable in view of leakage currents which typically exponentially increase when reducing the gate dielectric thickness.

The continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques concerning the above-identified problems. It has been proposed to improve transistor performance by enhancing the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the above-mentioned problems such as gate dielectric scaling. One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, for standard silicon substrates, creating tensile strain in the channel region increases the mobility of electrons, which in turn may directly translate into a corresponding increase in the conductivity and thus drive current and operating speed. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.

According to one promising approach, stress may be created by, for instance, layers located close to the transistor, spacer elements and the like to induce a desired strain within the channel region. However, the process of creating the strain in the channel region by applying a specified external stress may suffer from an inefficient translation of the external stress into strain in the channel region. Hence, although providing significant advantages, the efficiency of the stress transfer mechanism may depend on the process and device specifics and may result in a reduced performance gain for well-established standard transistor designs, since the overlaying layer may be significantly offset from the channel region, thereby reducing the strain finally created in the channel region. Therefore, recessed transistor architectures have been proposed for enhancing the lateral stress transfer.

With reference toFIGS. 1a-1g, conventional strategies for forming recessed transistor architectures will now be described in more detail in order to explain principal advantages of this device configuration and also describe problems, especially involved with SOI (silicon-on-insulator) architectures.

FIG. 1aschematically illustrates a top view of a semiconductor device100comprising a transistor element150. The transistor element150typically comprises drain and source regions151and a gate electrode152, which may have formed on the sidewalls thereof respective sidewall spacers153. Furthermore, respective contacts157may extend substantially perpendicular to the drawing plane ofFIG. 1aso as to establish electrical connections of the drain and source regions151to a respective higher wiring level (not shown). Furthermore, a respective dielectric material for passivating the material150may not be shown inFIG. 1aso as to not unduly obscure the respective structure of the transistor element150.

FIG. 1bschematically illustrates a cross-sectional view of the semiconductor device100taken along the line Ib-Ib ofFIG. 1a. First, a substantially planar configuration is shown inFIG. 1bin order to demonstrate the advantages of a recessed transistor configuration, as will be explained in more detail with reference toFIGS. 1c-1d. InFIG. 1b, the semiconductor device100comprises a substrate101, which represents a bulk silicon substrate including, on an upper portion thereof, a semiconductor layer102. Hence, the transistor150may represent a bulk transistor wherein the drain and source regions151and a corresponding channel region155are electrically connected to the substrate101. Moreover, in this manufacturing stage, respective metal silicide regions154may also be formed on the gate electrode152and in the drain and source regions151, wherein a corresponding lateral offset to the gate electrode152may be substantially defined by the spacer structure153. For convenience, the metal silicide regions154are not shown inFIG. 1a.

Moreover, a strain-inducing dielectric layer103, for instance a silicon nitride layer, is formed above the transistor150so as to induce a desired type of strain in the channel region155. Typically, the dielectric layer103may represent a portion of an interlayer dielectric material provided to encapsulate the transistor150prior to forming respective wiring levels or metallization layers (not shown) which provide the required electrical connections of respective circuit elements in the semiconductor device100. When the transistor150represents an N-channel transistor, tensile strain in the channel region155may significantly enhance the electron mobility therein, thereby providing enhanced transistor performance. In this case, the dielectric material of the layer103may be provided with a high intrinsic tensile stress in order to mechanically transfer stress into the channel region155.

It should be appreciated that highly efficient strain-inducing mechanisms may be available for P-channel transistors, such as the provision of embedded silicon/germanium material in the respective drain and source regions151, thereby enabling significant transistor improvements for PMOS transistors, wherein, additionally, appropriately stressed dielectric materials, such as the layer103, may be provided, however, in this case, with a high compressive stress, in order to even further enhance the overall transistor performance. Silicon nitride is well known to be capable of being provided with high intrinsic stress, wherein well-established deposition techniques on the basis of plasma enhanced chemical vapor deposition (PECVD) result in high intrinsic stress, wherein extremely high compressive values may be obtained, while a respective tensile strain is less pronounced. Consequently, in the following, it may be assumed that the transistor150may represent an N-channel transistor whose performance is to be further enhanced in order to reduce the imbalance in performance gain of P-channel transistors and N-channel transistors by strain engineering techniques. For example, the respective mechanical transfer of stress into the channel region155may be enhanced by recessing the drain and source regions151in order to provide an increased “direct” stress component acting substantially laterally on the channel region155.

FIG. 1cschematically illustrates the semiconductor device100including the transistor150with a recessed drain and source architecture. That is, the drain and source regions151comprise a surface portion151R that is located at a significantly lower height level with respect to the channel region155, when compared with the situation of the substantially planar configuration as shown inFIG. 1b. Therefore, the stressed material of the layer103may act in a substantially lateral direction, as previously explained. Additionally, the recessed architecture provides an increased surface area of the metal silicide regions154in the drain and source regions151, since an additional sidewall area151sof the recessed drain and source regions151may be available during the corresponding silicidation process. Consequently, the overall series resistance of the transistor150may be reduced compared to the planar configuration as shown inFIG. 1b.

For this reason, the corresponding manufacturing sequence for forming the transistor element150as shown inFIG. 1bmay be appropriately modified to introduce additional process steps for forming a corresponding recess in the drain and source regions151resulting in the transistor configuration as shown inFIG. 1c. For example, well-established process techniques may be used for forming the transistor150as shown inFIG. 1cup to a state where the drain and source regions151are to be formed in the semiconductor layer102. During the corresponding process sequence, the implantation sequence may be appropriately designed to obtain the desired depth of the drain and source regions151in order to take into consideration the desired degree of recess to be formed therein. As may be evident from the explanation given above, an increased depth of the surface151R may result in increased performance gain due to the increased efficiency of the stress transfer and the increased amount of metal silicide in the regions154. Hence, in the bulk transistor configuration as shown inFIG. 1c, a respective adaptation of conventional process techniques may be used to obtain the desired depth of the recessed drain and source regions151, which may be formed on the basis of an appropriately designed etch process. During the corresponding etch process, other transistor elements, such as P-channel transistors or any other transistors that do not require the recessed configuration, may be appropriately covered by a corresponding etch mask. Thereafter, further processing may be continued on the basis of well-established techniques, for instance by forming the metal silicide regions154and depositing the dielectric layer103on the basis of appropriate deposition parameters in order to obtain the desired high degree of intrinsic stress. Thereafter, an interlayer dielectric material104, such as silicon dioxide, may be deposited on the basis of well-established techniques.

FIG. 1dschematically illustrates the transistor150ofFIG. 1cshown according to a cross-sectional view as indicated by line Id-Id inFIG. 1a. Thus, the contacts157, which may be comprised of any appropriate conductive material, such as tungsten, copper, silver or any other materials and alloys, may extend through the interlayer dielectric material104and the stressed layer103to the metal silicide regions154. The contacts157may be formed on the basis of anisotropic etch techniques, wherein the layer103may be efficiently used as an etch stop material for first patterning the material104. Thereafter, the layer103may be opened and the resulting openings may be subsequently filled by the desired conductive material. Hence, significant advantages may be obtained by the recessed configuration in terms of strain and series resistance, wherein a respective performance gain is substantially determined by the depth of the respective drain and source regions151. The depth is substantially limited by the location of the PN junctions of the drain and source regions151since the metal silicide regions154must not extend beyond the respective PN junctions. Thus, in the bulk configuration, the respective transistor design may be modified to obtain the desired depth of the drain and source regions151without shorting the respective PN junctions by appropriately designing the respective dopant profile.

With reference toFIGS. 1e-1g, further advantages of a recessed transistor configuration will be illustrated. InFIG. 1e, the semiconductor device100comprises neighboring transistor elements150A,150B according to a planar configuration, wherein each of the transistors150A,150B may substantially correspond to the transistor as shown inFIG. 1d. In this configuration, the contact157may be positioned between the two transistors150A,150B, wherein the metal silicide region154may provide sufficient drive current capability in order to avoid undue increase of series resistance, since significant current crowding in the metal silicide region154may be avoided, although the conductivity of the contact157may be significantly higher compared to the conductivity of metal silicide in the region154, which in turn is significantly higher compared to the conductivity of the drain and source regions151.

FIG. 1fschematically illustrates the semiconductor device100in advanced applications, wherein the corresponding spacing between the neighboring transistors150A,150B may be significantly reduced, thereby resulting in a significantly reduced ratio of the lateral extension of the metal silicide region154and the contact157. In the example shown inFIG. 1f, this ratio may even become approximately 1, thereby resulting in a significant current crowding within the metal silicide material, which may unduly reduce the overall performance of the semiconductor device100due to increased current crowding at portions157A.

FIG. 1gschematically illustrates a semiconductor device100similar to the device ofFIG. 1fwherein, however, a recessed drain and source configuration is used, as is previously explained with reference toFIGS. 1cand 1d. As is evident, due to the increased interface between the contact157and the metal silicide region154at the areas157A, undue increase of the series resistance may be avoided or at least reduced, thereby also making the recessed drain and source configuration highly advantageous in semiconductor devices requiring reduced spacings between neighboring transistor elements.

In principle, the recessed transistor configuration may also be advantageous in the context of SOI devices, wherein, however, the depth of the recess of the SOI configuration is limited by the initial thickness of the semiconductor layer formed above the buried insulating layer. Thus, techniques have been proposed to etch the recess close to the buried insulating layer yet maintain sufficient silicon as required by the subsequent silicide process. That is, in order to maintain silicide integrity, a residual layer is maintained, the thickness of which is substantially determined by the silicide thickness required in the gate electrode for obtaining the desired low gate resistance. For example, in modern SOI transistors having a recessed drain/source configuration, a minimum thickness of approximately 20 nm may be required in order to provide process uniformity and silicide integrity. Hence, there is still room for improvement in enhancing performance of SOI transistors having a recessed drain/source configuration.

SUMMARY OF THE INVENTION

Generally, the subject matter disclosed herein relates to techniques for enhancing the transistor performance by increasing the stress transfer mechanism and/or reducing the series resistance in SOI transistors by providing SOI transistors having a reduced “drain and source length,” thereby providing the potential for forming the strain-inducing material laterally adjacent to the drain and source regions down to the buried insulating layer. Consequently, the strain-inducing material may laterally act along substantially the entire depth of the adjacent drain and source regions, thereby significantly increasing the overall strain in the respective channel region. In some aspects, the exposure of a portion of the buried insulating layer may be accomplished with a high degree of compatibility with other process techniques for forming recessed drain/source configurations, thereby not unduly contributing to additional process complexity. In further aspects, respective process steps may be introduced at any appropriate manufacturing stage so as to not unduly affect the overall process sequence and transistor characteristics.

One illustrative semiconductor device disclosed herein comprises a transistor formed above a buried insulating layer, wherein the transistor comprises drain and source regions located in a semiconductor material formed on the buried insulating layer. The semiconductor device further comprises a strain-inducing layer formed above the transistor, wherein the strain-inducing layer substantially extends to the buried insulating layer adjacent to the drain and source regions.

In one illustrative method disclosed herein, a recess is formed laterally offset from a gate electrode structure of a transistor in a silicon-containing semiconductor layer that is formed on a buried insulating layer. The method further comprises performing a heat treatment in a hydrogen-containing ambient for inducing a material flow in the recess to substantially expose a portion of the buried insulating layer.

In another illustrative method disclosed herein, a recess is formed that is offset from a gate electrode of a field effect transistor, wherein the gate electrode is located above a semiconductor layer which is formed on a buried insulating layer, wherein the recess substantially extends to the buried insulating layer. The method further comprises forming a drain region and a source region adjacent to the gate electrode and forming a dielectric strain-inducing layer above the field effect transistor and within the recess.

DETAILED DESCRIPTION OF THE INVENTION

Generally, the subject matter disclosed herein addresses the limitations in SOI transistors caused by the finite thickness of the active semiconductor layer and the formation of recessed drain and source regions in combination with efficient metal silicide regions. For this purpose, aspects of the subject matter disclosed herein refer to manufacturing techniques, in which a recess may be formed adjacent to the drain and source regions, which may substantially completely extend down to the buried insulating layer, while nevertheless providing sufficient process margins during the subsequent metal silicide processing. Consequently, after the formation of the metal silicide regions, a corresponding strain-inducing dielectric material may be deposited above the substantially exposed portion of the buried insulating layer, thereby significantly enhancing the overall stress transfer mechanism compared to conventional recessed drain/source architectures in SOI devices. Moreover, the overall conductivity from the respective contact portions into the channel region may be enhanced compared to the conventional designs, as previously explained, since further device scaling, and thus reducing the pitch between neighboring transistor elements, may not unduly reduce the overall transistor performance. Since the entire available depth of the active semiconductor layer in an SOI configuration may be available for the stress transfer mechanism, an appropriate adjustment of the overall strain in the respective SOI transistors may be accomplished on the basis of the internal stress of the corresponding dielectric material to be filled in the recess formed adjacent to the drain and source regions. Consequently, a wide bandwidth for adjusting the respective strain characteristics may be provided on the basis of a single process step, i.e., the deposition of the stressed dielectric material which may readily be provided so as to obtain the desired degree of strain in various device regions.

In some aspects, the principles disclosed herein may be applied in a highly selective manner to provide significant performance gain in selected transistor devices, while substantially not affecting other transistor devices. For example, the techniques disclosed herein may be advantageously applied to N-channel transistors in order to provide the high performance gain obtained by strain engineering techniques on the basis of stressed dielectric materials encapsulating a respective SOI transistor. In this case, the imbalance with respect to strain-inducing mechanisms between N-channel transistors and P-channel transistors may be at least partially compensated for by applying these techniques to N-channel transistors only. In other illustrative embodiments, the techniques disclosed herein may be advantageously applied to P-channel transistors and N-channel transistors, which may provide the potential of obtaining enhanced transistor performance based on a single strain-inducing mechanism while at the same time providing enhanced series conductivity, as is previously explained. In still other aspects, the techniques disclosed herein may be advantageously combined with additional strain-inducing sources, such as semiconductor alloys provided in drain and source regions and/or the channel regions.

Consequently, the subject matter disclosed herein should not be considered as being restricted to a single type of transistor, although, in illustrative examples disclosed herein, an SOI N-channel transistor may be referred to.

FIG. 2aschematically illustrates a cross-sectional view of a semiconductor device200comprising a substrate201, which may represent any carrier material for forming there-above a transistor device according to an SOI configuration. For example, the substrate201may represent a silicon substrate as typically used in SOI devices. Furthermore, a buried insulating layer205comprised of any appropriate material, such as silicon dioxide, silicon nitride and the like, is formed above the substrate201and separates a silicon-based semiconductor layer202from the substrate201. The silicon-based semiconductor layer202may represent any appropriate silicon-based material in a substantially crystalline structure, wherein a silicon-based material is to be understood as a semiconductor material comprising a significant amount of silicon, such as approximately 50 volume percent silicon or more, while other species may also be present, such as isoelectronic species, such as germanium, carbon and the like, as well as dopants for adjusting the conductivity of the semiconductor layer202. The semiconductor layer202and the underlying buried insulating layer205define an SOI configuration, wherein it should be appreciated that the corresponding SOI configuration may not necessarily extend across the entire substrate201but may be locally restricted to respective device areas, in which the advantageous characteristics of SOI transistors may be desired. For instance, the transistor250may represent a circuit element in a functional block requiring high operating speed which may be provided by the transistor250due to the enhanced performance of SOI transistors, due to reduced parasitic capacitance and the like. In other device areas, a bulk configuration may be provided, for instance by omitting the buried insulating layer205, when the respective bulk transistors are considered superior for device operation, for instance when considering static memory areas and the like.

In the embodiment shown, the transistor250may comprise respective drain and source regions251defined by an appropriate lateral dopant profile which may also extend down to the buried insulating layer205. A channel region255is formed between the drain and source regions251with a gate electrode structure252separated therefrom by a gate insulation layer256. In sophisticated applications, a gate length of the gate electrode252, i.e., inFIG. 2athe horizontal extension, may be approximately 50 nm and significantly less, such as 30 nm and less. The gate electrode252may be encapsulated by a sidewall spacer structure253, which may be comprised of any appropriate material, such as silicon nitride, silicon dioxide and the like. For instance, the spacer structure253may comprise one or more individual spacer elements, which may be separated from each other by a respective liner material having a high etch selectivity with respect to the spacer material. In other cases, the structure253may be formed by a substantially homogenous material composition. Furthermore, a cap layer259, for instance comprised of substantially the same material as the spacer structure253, such as silicon nitride, may be formed on top of the gate electrode252, wherein a respective liner material258, such as silicon dioxide and the like, may be provided.

The semiconductor device200as shown inFIG. 2amay be formed on the basis of the following processes. After providing the substrate201having formed thereon, at least locally, the buried insulating layer205and the semiconductor layer202, respective active regions may be defined in the layer202corresponding to transistor areas or other semiconductor areas requiring a specific conductivity. For this purpose, appropriate isolation structures (not shown) may be formed and thereafter the required dopant concentration may be introduced for setting transistor characteristics, such as conductivity type, threshold voltage and the like. Next, the gate electrode252and the gate insulation layer256may be formed based on well-established techniques, wherein sophisticated oxidation and/or deposition techniques may be used for the material of the gate insulation layer256, followed by the deposition of an appropriate gate electrode material, which may include respective cap materials, anti-reflecting coating (ARC) materials and the like, as required. For instance, the material for the cap layer259and the liner258may be formed prior to patterning the gate electrode material. The patterning may be performed on the basis of sophisticated lithography and etch techniques, while in other cases the gate electrode252may be formed at a later stage by forming a place holder structure and removing the same in a later stage. Thereafter, further process steps may be performed in accordance with device requirements. For instance, in some transistors, strain-inducing mechanisms may be implemented, for instance in the form of semiconductor alloys of any appropriate composition in order to modify the crystalline structure in at least a portion of the respective active region. For instance, respective recesses may be formed and may be refilled with epitaxially grown semiconductor materials, such as silicon/germanium, if compressive strain may be desired in a certain type of transistor, such as P-channel transistors.

In the following, it may be assumed that the transistor250may represent an N-channel transistor which may receive an appropriate type of strain in the channel region255by a corresponding stressed dielectric material still to be formed, without providing additional strain-inducing sources. Thus, after patterning the gate electrode252, possibly in combination with the liner258, which may have a thickness in the range of approximately 2-5 nm, and the cap layer259, which may have a thickness of approximately 20-40 nm, respective implantation processes may be performed, for instance halo implantation, source/drain extension implantation and the like. For this purpose, an appropriate offset spacer, if required, may be formed followed by the formation of one or more additional spacer elements so as to obtain the spacer structure253. During the respective steps for forming spacer elements, respective implantation processes may be formed so as to finally obtain the desired lateral profile of the drain and source regions251.

FIG. 2bschematically illustrates the semiconductor device200when exposed to the etch ambient of an etch process210. During the etch process210, a recess210R may be formed in the drain and source regions251with a predefined depth210D, which may be selected on the basis of device requirements in view of a subsequent modification of the drain and source regions with respect to a degree of tapering to be formed therein, as will be described later on. For instance, in some illustrative embodiments, the etch process210may be designed to exhibit a high degree of compatibility with etch processes for forming recessed drain and source configurations in SOI devices, thereby maintaining a required thickness of the layer202, as previously explained. Hence, in this case, well-established process recipes may be used. In one embodiment, the etch process210may be designed so as to simultaneously etch the material of the spacer structure253and the cap layer259, wherein the etch front may be reliably stopped on the liner258, thereby substantially avoiding undue damage of the gate electrode252when comprised of polysilicon. In other illustrative embodiments, the etch process210may include a selective etch process for removing material of the layer202with a subsequent selective etch step for removing the cap layer259and a portion of the structure253. Respective selective etch recipes, for instance for silicon, silicon nitride and silicon dioxide, are well established in the art. The etch process210may be performed on the basis of an appropriately designed etch mask (not shown) when other areas of the semiconductor device200do not need to receive respective recesses210R. For example, if respective transistor elements have been formed, which may include additional strain-inducing sources, such as embedded semiconductor alloys and the like, the corresponding transistors may not require a further enhancement of strain transfer mechanisms provided by overlaying stressed layers, and hence the corresponding transistors may be covered by a resist mask and the like. In other illustrative embodiments, the recesses210R may be formed in other types of transistors, such as P-channel transistors, when a corresponding finally desired amount of strain may be adjusted by the amount of intrinsic stress of a corresponding dielectric material to be filled into the recesses210R in a later manufacturing stage.

FIG. 2cschematically illustrates the semiconductor device200in a further advanced manufacturing stage. Here, the device is subjected to a heat treatment211in the presence of a hydrogen ambient in order to initiate a material flow of any non-passivated silicon-based material, i.e., of silicon material in the layer202, which may not be covered by temperature-resistant materials, such as the spacer structure253. The heat treatment may be performed at temperatures in the range of 750-1000° C., or in a range of 800-950° C., for a time period of several seconds to several minutes, such as approximately 30 seconds to 5 minutes. During this “high temperature hydrogen bake,” the silicon-based material moves in order to reduce its surface area, as indicated by arrows211A. In some illustrative embodiments, the heat treatment211may be performed in a state of the transistor250in which respective anneal processes for activating dopants and curing crystalline damage have already been performed, while, in other illustrative embodiments, the heat treatment211may be used as a first step of re-crystallizing damaged areas in the drain and source regions251and activating, to a certain degree, the corresponding dopant atoms. It should be appreciated that the material flow211A may be substantially restricted to exposed silicon-based areas in which a respective reduction of the overall exposed surface area is possible. For instance, in other device areas in which substantially planar exposed silicon-containing regions may be subjected to the heat treatment211, only a reduced material flow may be observed, or, in other embodiments, respective exposed portions may be covered by an appropriate material, such as silicon dioxide, silicon nitride and the like.

FIG. 2dschematically illustrates the device200after the heat treatment211. As shown, the material flow211A may result in the removal of the material of the layer202previously covering the buried insulating layer205and may accumulate adjacent to the gate electrode structure in such as way as to reduce the overall surface area of the silicon material compared to the drain and source regions including the recess210R. Thus, the previously recessed drain and source regions251may comprise an additional portion251A having a substantially trapezoidal edge251S due to the preceding heat treatment211. Consequently, a respective portion205A of the buried insulating layer205may be substantially exposed during the heat treatment211, thereby also reducing the effective “length”251L of the drain and source regions251at a height level corresponding to the buried insulating layer205. Since the corresponding dopant atoms in the silicon-based material may have also been transferred to the additional portions251A, a desired high dopant concentration may still be maintained within the entire drain and source regions251having the reduced length. Furthermore, the portion251A may now be available for a subsequent silicidation process and may provide sufficient process margin in order to avoid an undue shorting of the respective PN junctions, substantially independently of a degree of silicidation as required by the gate electrode252so as to reduce the resistance thereof. Furthermore, by appropriately adjusting the depth210D (FIG. 2b) of the recess210R, the amount of silicon-based material in the drain and source regions251may be adjusted, thereby providing the potential for appropriately dimensioning the size of the additional portion251A and thus the offset of the edge251S from the respective PN junctions. Hence, a respective silicidation process may not result in an undue silicide growth into the drain and source regions251so as to create the risk for shorting the PN junction.

FIG. 2eschematically illustrates the semiconductor device200in a further advanced manufacturing stage. Respective metal silicide regions254are formed in the gate electrode252and the additional portion251S according to the requirements for a reduced gate resistance, as previously explained. For the corresponding silicidation process, well-established process techniques may be used, wherein non-reacted metals, such as nickel, platinum, cobalt and the like, which may be used for forming the metal silicide regions254, may be efficiently removed from non-silicon areas, such as the portion205A of the buried insulating layer205and the spacer253. If a further reduced series resistance may be desired and/or an even further enhanced stress transfer, the spacer structure253may be reduced in width by performing a respective selective etch process on the basis of well-established etch recipes. In this case, the offset to the channel region255may be reduced, depending on the degree of spacer removal, while nevertheless a risk for PN junction shorting in the lower portion of the drain and source regions251may still be avoided due to the additional portion251A.

After the formation of the metal silicide regions254, a stressed dielectric material203may be provided on the basis of well-established techniques. For example, in the embodiment shown, the layer203may comprise dielectric material of high tensile stress in order to create a respective tensile strain in the channel region255. Since the highly stressed layer203may be formed along the entire depth of the drain and source regions251and may be in contact with the buried insulating layer205, that is, the portion205A, a significantly enhanced stress transfer mechanism may be achieved. In some illustrative embodiments (not shown), a further etch process may be performed in the device200as shown inFIG. 2din order to selectively remove material from the exposed portion205A of the buried insulating layer on the basis of a selective etch process. In this case, the highly stressed material of the layer203may even extend beyond the drain and source regions251, thereby further enhancing the overall strain-inducing mechanism. During a corresponding etch process, material of respective isolation structures may also be removed, if comprised of substantially the same material as the buried insulating layer205, which may be acceptable since the corresponding material may then be replaced by material of the layer203.

FIG. 2fschematically illustrates the semiconductor device200in a cross-sectional view taken along a plane in which respective contacts253are provided, similar to the cross-sectional view indicated inFIG. 1aby the line Id-Id. As is evident, the contacts257may form an increased interface area with the edge251S of the metal silicide regions254in the drain and source regions251, due to the substantially tapered form of the respective edges251S. Even for a slight misalignment of the contact257, a significant overlap between the contact257and the respective metal silicide region254may still be obtained so as to result in non-significant current crowding, as previously explained when referring to conventional configuration. Thus, the contact257may engage with the metal silicide regions254in the drain and source regions251, thereby forming an angle that is substantially defined by the degree of tapering of the drain and source regions251. For example, a corresponding angle may be in the range of approximately 20-60 degrees.

FIG. 5schematically illustrates the advantages of the semiconductor device200compared to a conventional transistor having a recessed drain/source configuration, as for instance described with reference toFIGS. 1band 1c. As is evident, due to the extra height230, i.e., the difference of the thickness of the initial layer202and the recess230A of the conventional transistor shown at the left hand side, which is available for a lateral stress transfer from the stressed layer202into the semiconductor material forming the drain and source regions251and the channel region255, the corresponding overall transistor performance may be enhanced compared to the device100. Furthermore, the entire sidewall area of the edge251S down to the buried insulating layer205is available for current flow, thereby also efficiently reducing the series resistance in the transistor250.

FIG. 6schematically illustrates the semiconductor device200when comprising closely spaced transistors250A,250B, each of which may have substantially the same configuration as the transistor250described above. As shown, the contact257may encounter the respective increased sidewall areas of the edges251S, enabling a current flow from the contact257into the metal silicide regions254down to the buried insulating layer205, thereby also significantly relaxing any issues with respect to current crowding, even if contacts between densely spaced transistors are to be provided.

With reference toFIGS. 3a-3d, further illustrative embodiments will now be described in which exposure of a portion of buried insulating layer may occur in an earlier manufacturing stage.

FIG. 3aschematically illustrates a semiconductor device300comprising a transistor350at an early manufacturing stage. The transistor350may comprise a substrate301including a buried insulating layer305having formed thereon a silicon-based semiconductor layer302. Furthermore, a gate electrode352may be formed above the semiconductor layer302and may be separated therefrom by a gate insulation layer356. Regarding the components described so far, the same criteria may apply as previously explained with reference to the devices100and200. Moreover, in this manufacturing stage, the gate electrode352may be encapsulated by an appropriately designed sidewall spacer structure353and a cap layer359wherein, if required, a corresponding liner358may be provided. It should be appreciated that in some illustrative embodiments the semiconductor device300may comprise other transistor areas, in which a recess may have to be formed so as to incorporate therein a respective semiconductor alloy, such as silicon/germanium and the like. Thus, respective sidewall spacers353and cap layers359may also be provided in other transistor areas. The spacer353may be formed on the basis of well-established spacer techniques, i.e., by conformally depositing an appropriate material, such as silicon nitride, possibly in combination with an appropriate liner material (not shown), and anisotropically etching the material so as to obtain the final spacers353. The cap layer359may be formed in accordance with process techniques as previously described with reference to the cap layer259.

Next, the device300may be subjected to an etch process310in order to remove material from exposed portions of the semiconductor layer302. For this purpose well-established etch recipes are available in the art.

FIG. 3bschematically illustrates the device300after the etch process310and after the removal of the spacer structure353and the cap layer359. Hence, a respective recess310R may be formed in the layer302wherein the size and dimension of the recess310R may possibly correspond to the size and dimension as required in other transistor types, such as P-channel transistors, which may receive a corresponding silicon/germanium material. In other cases, the dimensions of the recess310R and in particular the offset to the gate electrode352may be selected in accordance with the requirements as demanded by the finally desired drain and source length.

FIG. 3cschematically illustrates the semiconductor device300in a further advanced manufacturing stage, wherein respective offset spacers353A may be formed on sidewalls of the gate electrode352, which have a width as required for a subsequent implantation process for defining respective drain and source extension regions. The spacers353A may be formed on the basis of well-established techniques, for instance by depositing an appropriate material, such as silicon dioxide and the like. Furthermore, the device300may be subjected to a heat treatment311in the presence of hydrogen, as previously described, in order to reconfigure the semiconductor material in the layer302, thereby initiating a corresponding material flow due to the material's tendency to reduce its surface area, as previously explained. Consequently, the treatment311may result in a substantially exposed portion305A of the buried insulating layer305thereby effectively shortening the length of drain and source regions still to be formed. Consequently, the heat treatment311may not substantially affect the finally obtained dopant profile, since respective PN junctions may be formed after the heat treatment311. A corresponding implantation process may be performed on the basis of an appropriate dopant species in order to define respective extension regions in the material of the layer302.

FIG. 3dschematically illustrates the semiconductor device300in a further advanced manufacturing stage. As shown, respective extension regions351E may be formed in the layer302, as previously explained. Furthermore, a spacer structure353B including a liner353C may be provided. The spacer353B, in combination with the liner353C, may be formed on the basis of well-established techniques, i.e., the material353C may be deposited on the basis of any appropriate deposition technique, such as chemical vapor deposition (CVD) in the form of silicon dioxide and the like, in order to provide a high etch selectivity with respect to the material of the spacers353B. Thereafter, the spacer material may be deposited in a highly conformal manner and an anisotropic etch process may be subsequently performed to obtain respective spacer elements. It should be appreciated that, due to the inclined surface351S, the corresponding material removal during the anisotropic etch process may be less efficient compared to substantially horizontal surface portions. Consequently, the respective etch process may be performed with a certain over-etch time so as to completely remove the material from the surface portion351S. In this case, the height of the spacers353B may be reduced which may, however, substantially not negatively affect the further processing. In other illustrative embodiments, subsequent to the anisotropic etch process, a short highly selective isotropic etch process may be performed to substantially completely remove any material residues at the inclined sidewall portion351S. For example, a corresponding isotropic etch process may be performed on the basis of a corresponding etch mask, which may cover other device areas that may not receive an isotropic etch treatment. The corresponding etch mask may then also be used for a subsequent ion implantation312for defining respective drain and source regions351on the basis of well-established implantation parameters. Thereafter, the further processing may be continued as previously described, i.e., by performing respective anneal cycles for activating the dopants in the drain and source regions351and for curing lattice damage. Thereafter, respective cleaning processes may be performed in order to prepare exposed surface portions for a metal silicide process. Consequently, the advantageous transistor configuration of a reduced drain and source length may be provided on the basis of the heat treatment311at an early manufacturing stage, thereby substantially avoiding any undue effects with respect to dopant diffusion, while substantially not contributing to undue process complexity. It should be appreciated that a corresponding process for forming the recess310R may be advantageously combined with the formation of recesses in other device areas, such as P-channel transistors, thereby enhancing process uniformity during the corresponding etch process. If a subsequent selective epitaxial growth process may be performed in other device areas, a corresponding growth mask may be formed within the recess310, for instance on the basis of an appropriately selected material layer, such as silicon dioxide and silicon nitride, which may be formed by oxidation, deposition and the like, selectively in the transistor350.

With reference toFIGS. 4a-4b, further illustrative embodiments will now be described in which the drain and source configuration may be modified on the basis of an etch process in order to expose a portion of the buried insulating layer.

FIG. 4aschematically illustrates a semiconductor device400comprising a transistor450having substantially the same configuration as the transistor250as shown inFIG. 2a. Thus, the device may comprise a substrate401, a buried insulating layer405and a semiconductor layer402. The transistor450may comprise a gate electrode452formed on a gate insulation layer456, separating the gate electrode from a channel region455that is enclosed by respective drain and source regions451. A sidewall spacer structure453, which may include an appropriate liner material, may be formed on sidewalls of the gate electrode452, which may be capped by a cap layer459in combination with an etch stop layer458. The components described so far may be formed on the basis of the same process techniques as previously described.

Next, a spacer layer440may be formed prior to recessing the drain and source regions451, wherein a thickness of the spacer layer440may be selected so as to obtain a desired offset to the PN junction in the drain and source regions451. The spacer layer440may be formed of any appropriate material and may, in some illustrative embodiments, be comprised of a material having substantially the same etch rate as the material of the spacer453and the cap layer459. Next, an anisotropic etch process may be performed, which may remove material of the spacer layer440and the materials encapsulating the gate electrode452while also removing material of the semiconductor layer402. For instance, an anisotropic etch process may be performed wherein respective process parameters and etch components may be appropriately adapted in an advanced stage of the etch process to obtain an enhanced isotropic component during the etch process. Thus, during the ongoing etch process, a substantially tapered shape of the corresponding recess may be obtained. The etch process may be continued until a portion of the buried insulating layer405may be exposed.

FIG. 4bschematically illustrates the semiconductor device400after a corresponding etch sequence. Hence, the recess410R extending down to the buried insulating layer405may be formed adjacent to the drain and source regions451with an inclined sidewall portion due to the preceding isotropic component of the etch process. Furthermore, the width of the spacers453also may have been reduced during the isotropic phase of the preceding etch process. However, the corresponding liner material may reliably prevent exposure of the gate electrode452and may also provide a desired offset for a subsequent silicidation process. Thus, based on the configuration shown inFIG. 4b, the further processing may be continued by forming the respective metal silicide regions and forming a strained dielectric material in the recess410R, as previously explained.

As a result, the subject matter disclosed provides a technique and respective semiconductor devices obtained therefrom in which the transistor characteristics of SOI devices may be significantly enhanced by recessing drain and source regions substantially down to the buried insulating layer prior to forming respective metal silicide regions and a strained dielectric material. This may be accomplished in some aspects on the basis of a heat treatment in the presence of a hydrogen ambient at appropriate temperatures so as to induce a material flow caused by the material's tendency in reducing its surface. Thus, a tapered drain and source region with reduced effective length may be provided, thereby substantially completely removing the material from the buried insulating layer so that a corresponding stressed material may advantageously act on the drain and source region along the entire depth thereof. Thus, enhanced stress transfer and reduced series resistance may be obtained, even for highly scaled semiconductor devices comprising densely spaced transistor elements. The technique of “reducing the effective drain length” may be used for N-channel transistors and P-channel transistors, wherein, in some illustrative embodiments, the technique disclosed herein may be advantageously applied to N-channel transistors only to provide additional strain-inducing sources for this type of transistors in order to efficiently reduce the imbalance of performance gain between P-channel transistors and N-channel transistors. The corresponding process step for initiating the material flow may be incorporated at any appropriate stage without unduly affecting the overall process sequence. In still other illustrative embodiments, a corresponding removal of material from the drain and source regions in order to expose a portion of the buried insulating layer may be accomplished on the basis of an etch process, which may be performed at any appropriate manufacturing stage, for instance after completing the drain and source regions, without unduly affecting the overall manufacturing sequence.