Timing signal calibration for access operation of a memory device

Methods, systems, and devices for timing signal calibration for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous with an input signal. To support asynchronous timing, a timing signal generation component of a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. Delay components may have characteristics that are sensitive to fabrication or operational variability, such that timing signals may also be affected by such variability. In accordance with examples as disclosed herein, a memory device may include delay components, associated with access operation timing signal generation, that are configured to be selectively enabled or disabled based on a calibration operation of the memory device, which may improve an ability of the memory device to account for various sources of timing signal variability.

BACKGROUND

The following relates generally to one or more memory systems and more specifically to timing signal calibration for a memory device.

Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technologies, and others. Memory cells may be volatile or non-volatile. Non-volatile memory, e.g., FeRAM, may maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, e.g., DRAM, may lose their stored state when disconnected from an external power source.

DETAILED DESCRIPTION

In some memory devices, accessing memory cells may involve multiple operations controlled by multiple signals. The multiple operations may be performed with timing that is generated from an input signal. Thus, at least some internal operations may occur at a different time than a rising edge transition or a falling edge transition of an input signal such as a clock signal or command signal. Such operations may be triggered or otherwise supported by core timing signals of the memory device, which may be generated by a timing signal generation component of the memory device. To support timing of multiple signals, a timing signal generation component of a memory device may include delay components that support generating a timing signal having aspects that are delayed or timed relative to an input signal, which may be received from or otherwise related to signaling from a host device. Such timing signals generated by delay elements may be referred to as asynchronous timing signals. In one example, a delay component may support generating a read strobe signal, which may trigger or initiate latching information detected by a sense amplifier, or transferring information to an input/output component of a memory device, among other purposes. A read strobe signal may have a transition (e.g., rising edge, falling edge) that is delayed relative to a transition of an input signal (e.g., a column selection signal, a column activation signal), or may have a pulse width (e.g., a duration between a rising edge and a falling edge) that is based at least in part on delay elements.

A delay component may include various circuit elements that impose a delay between a transition of an input signal and a corresponding transition of an output signal. For example, a delay component may include one or more gate delays or gate delay components, which may be associated with a duration between an input signal of the component crossing a threshold voltage and an output signal of the component crossing the threshold voltage. Gate delay components may be chained together in series, where such a configuration of components may be referred to as a delay chain. In some examples (e.g., to support a delay between a rising edge of an input signal and a rising edge of an output signal), a delay chain may include an even number of inverters connected in series. However, other configurations may be used to support timing signal generation. In some examples, delay components may have timing characteristics that are sensitive to fabrication variability (e.g., process variability) or operating condition variability (e.g., voltage variability, temperature variability), such that asynchronous timing signals may also be affected by such variability. The variability of asynchronous timing signals may be associated with adverse performance of a memory device, including reduced read margins, increased read or write errors, longer latency to support timing or signaling uncertainties, and others.

In accordance with examples as disclosed herein, a memory device may include delay components, associated with access operation timing signal generation, that are configured to be selectively enabled or disabled (e.g., bypassed) based on a calibration operation of the memory device. In some examples, the calibration operation may include sequentially processing a first timing signal (e.g., a calibration timing signal) through each of a first set of delay components to generate a set of delayed timing signals. The different delays associated with respective ones of the set of delayed timing signals may support an identification of which delay components, or how many delay components, of a second set of delay components should be enabled to support access operation timing signals of the memory device. The selective enabling or disabling of such delay components may improve the ability of a memory device to account for fabrication variability, operating condition variability, or other phenomena, including aspects related to asynchronous timing signal generation.

Features of the disclosure are initially described in the context of memory systems and dies as described with reference toFIGS. 1 and 2. Features of the disclosure are described in the context of timing signal calibration circuitry and operations, and timing signal generation leveraging such calibration circuitry and operations, as described with reference toFIGS. 3 through 5. These and other features of the disclosure are further illustrated by and described with reference to an apparatus diagram and flowcharts that relate to timing signal calibration for a memory device as described with reference toFIGS. 6 and 7.

FIG. 1illustrates an example of a system100that supports timing signal calibration for a memory device in accordance with examples as disclosed herein. The system100may include a host device105, a memory device110, and a plurality of channels115coupling the host device105with the memory device110. The system100may include one or more memory devices110, but aspects of the one or more memory devices110may be described in the context of a single memory device (e.g., memory device110).

At least portions of the system100may be examples of the host device105. The host device105may be an example of a processor or other circuitry within a device that uses memory to execute processes, such as within a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an internet-connected device, a vehicle controller, or some other stationary or portable electronic device, among other examples. In some examples, the host device105may refer to the hardware, firmware, software, or a combination thereof that implements the functions of an external memory controller120. In some examples, the external memory controller120may be referred to as a host or a host device105.

The memory device110may be operable to store data for the components of the host device105. In some examples, the memory device110may act as a slave-type device to the host device105(e.g., responding to and executing commands provided by the host device105through the external memory controller120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

The host device105may include one or more of an external memory controller120, a processor125, a basic input/output system (BIOS) component130, or other components such as one or more peripheral components or one or more input/output controllers. The components of host device may be in coupled with one another using a bus135.

The device memory controller155may include circuits, logic, or components operable to control operation of the memory device110. The device memory controller155may include the hardware, the firmware, or the instructions that enable the memory device110to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device110. The device memory controller155may be operable to communicate with one or more of the external memory controller120, the one or more memory dies160, or the processor125. In some examples, the device memory controller155may control operation of the memory device110described herein in conjunction with the local memory controller165of the memory die160.

In some examples, operations for accessing memory arrays170may be triggered or otherwise supported by core timing signals of the memory device110, which may be generated by a timing signal generation component of the memory device110(e.g., of a device memory controller155, of a local memory controller165). To support asynchronous timing, a timing signal generation component of the memory device110may include delay components that support generating a timing signal having aspects that are delayed or timed relative to an input signal, which may be received from or otherwise related to signaling from the host device105(e.g., a command signal received on a CA channel186). In one example, a timing signal generation component may generate a read strobe signal, which may trigger or initiate latching information detected by a sense amplifier or read latch, or transferring information to an input/output component of a memory device (e.g., latching information for output on a DQ channel190or related signal path of the memory device110).

In some examples, delay components may have characteristics that are sensitive to fabrication variability (e.g., process variability) or operating condition variability (e.g., voltage variability, temperature variability), such that core timing signals may also be affected by such variability. Variability of core timing signals may be associated with adverse performance of the memory device110, or the system100as a whole, including reduced read margins, increased read or write errors, longer latency to support timing or signaling uncertainties, and others. In accordance with examples as disclosed herein, the memory device110may include delay components, associated with access operation timing signal generation, that are configured to be selectively enabled or disabled (e.g., bypassed) based on a calibration operation of the memory device110. The selective enabling or disabling of such delay components may improve the ability of the memory device110to account for fabrication variability, operating condition variability, or other phenomena.

FIG. 2illustrates an example of a memory die200that supports timing signal calibration for a memory device in accordance with examples as disclosed herein. The memory die200may be an example of the memory dies160described with reference toFIG. 1. In some examples, the memory die200may be referred to as a memory chip, a memory device, or an electronic memory apparatus. The memory die200may include one or more memory cells205that may each be programmable to store different logic states (e.g., programmed to one of a set of two or more possible states). For example, a memory cell205may be operable to store one bit of information at a time (e.g., a logic 0 or a logic 1). In some examples, a memory cell205(e.g., a multi-level memory cell) may be operable to store more than one bit of information at a time (e.g., a logic 00, logic 01, logic 10, a logic 11). In some examples, the memory cells205may be arranged in an array, such as a memory array170described with reference toFIG. 1.

A memory cell205may store a charge representative of the programmable states in a capacitor. DRAM architectures may include a capacitor that includes a dielectric material to store a charge representative of the programmable state. In other memory architectures, other storage devices and components are possible. For example, nonlinear dielectric materials may be employed. The memory cell205may include a logic storage component, such as capacitor230, and a switching component235. The capacitor230may be an example of a dielectric capacitor or a ferroelectric capacitor. A node of the capacitor230may be coupled with a voltage source240, which may be the cell plate reference voltage, such as Vpl, or may be ground, such as Vss.

The memory die200may include one or more access lines (e.g., one or more word lines210and one or more digit lines215) arranged in a pattern, such as a grid-like pattern. An access line may be a conductive line coupled with a memory cell205and may be used to perform access operations on the memory cell205. In some examples, word lines210may be referred to as row lines. In some examples, digit lines215may be referred to as column lines or bit lines. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or their analogues, are interchangeable without loss of understanding or operation. Memory cells205may be positioned at intersections of the word lines210and the digit lines215.

Operations such as reading and writing may be performed on the memory cells205by activating or selecting access lines such as one or more of a word line210or a digit line215. By biasing a word line210and a digit line215(e.g., applying a voltage to the word line210or the digit line215), a single memory cell205may be accessed at their intersection. The intersection of a word line210and a digit line215in either a two-dimensional or three-dimensional configuration may be referred to as an address of a memory cell205.

Accessing the memory cells205may be controlled through a row decoder220or a column decoder225. For example, a row decoder220may receive a row address from the local memory controller260and activate a word line210based on the received row address. A column decoder225may receive a column address from the local memory controller260and may activate a digit line215based on the received column address.

Selecting or deselecting the memory cell205may be accomplished by activating or deactivating the switching component235using a word line210. The capacitor230may be coupled with the digit line215using the switching component235. For example, the capacitor230may be isolated from digit line215when the switching component235is deactivated, and the capacitor230may be coupled with digit line215when the switching component235is activated.

A word line210may be a conductive line in electronic communication with a memory cell205that is used to perform access operations on the memory cell205. In some architectures, the word line210may be coupled with a gate of a switching component235of a memory cell205and may be operable to control the switching component235of the memory cell. In some architectures, the word line210may be coupled with a node of the capacitor of the memory cell205and the memory cell205may not include a switching component.

A digit line215may be a conductive line that connects the memory cell205with a sense component245. In some architectures, the memory cell205may be selectively coupled with the digit line215during portions of an access operation. For example, the word line210and the switching component235of the memory cell205may be operable to couple and/or isolate the capacitor230of the memory cell205and the digit line215. In some architectures, the memory cell205may be coupled with the digit line215.

The sense component245may be operable to detect a state (e.g., a charge) stored on the capacitor230of the memory cell205and determine a logic state of the memory cell205based on the stored state. The sense component245may include one or more sense amplifiers to amplify or otherwise convert a signal resulting from accessing the memory cell205. The sense component245may compare a signal detected from the memory cell205to a reference250(e.g., a reference voltage). The detected logic state of the memory cell205may be provided as an output of the sense component245(e.g., to an input/output255), and may indicate the detected logic state to another component of a memory device that includes the memory die200.

The local memory controller260may control the accessing of memory cells205through the various components (e.g., row decoder220, column decoder225, sense component245). The local memory controller260may be an example of the local memory controller165described with reference toFIG. 1. In some examples, one or more of the row decoder220, column decoder225, and sense component245may be co-located with the local memory controller260. The local memory controller260may be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller120associated with a host device105, another controller associated with the memory die200), translate the commands or the data (or both) into information that can be used by the memory die200, perform one or more operations on the memory die200, and communicate data from the memory die200to a host device105based on performing the one or more operations. The local memory controller260may generate row signals and column address signals to activate the target word line210and the target digit line215. The local memory controller260may also generate and control various voltages or currents used during the operation of the memory die200. In general, the amplitude, the shape, or the duration of an applied voltage or current discussed herein may be varied and may be different for the various operations discussed in operating the memory die200.

The local memory controller260may be operable to perform one or more access operations on one or more memory cells205of the memory die200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, access operations may be performed by or otherwise coordinated by the local memory controller260in response to various access commands (e.g., from a host device105). The local memory controller260may be operable to perform other access operations not listed here or other operations related to the operating of the memory die200that are not directly related to accessing the memory cells205.

The local memory controller260may be operable to perform a write operation (e.g., a programming operation) on one or more memory cells205of the memory die200. During a write operation, a memory cell205of the memory die200may be programmed to store a desired logic state. The local memory controller260may identify a target memory cell205on which to perform the write operation. The local memory controller260may identify a target word line210and a target digit line215coupled with the target memory cell205(e.g., the address of the target memory cell205). The local memory controller260may activate the target word line210and the target digit line215(e.g., applying a voltage to the word line210or digit line215) to access the target memory cell205. The local memory controller260may apply a specific signal (e.g., write pulse) to the digit line215during the write operation to store a specific state (e.g., charge) in the capacitor230of the memory cell205. The pulse used as part of the write operation may include one or more voltage levels over a duration.

The local memory controller260may be operable to perform a read operation (e.g., a sense operation) on one or more memory cells205of the memory die200. During a read operation, the logic state stored in a memory cell205of the memory die200may be determined. The local memory controller260may identify a target memory cell205on which to perform the read operation. The local memory controller260may identify a target word line210and a target digit line215coupled with the target memory cell205(e.g., the address of the target memory cell205). The local memory controller260may activate the target word line210and the target digit line215(e.g., applying a voltage to the word line210or digit line215) to access the target memory cell205. The target memory cell205may transfer a signal to the sense component245in response to biasing the access lines. The sense component245may amplify the signal. The local memory controller260may activate the sense component245(e.g., latch the sense component) and thereby compare the signal received from the memory cell205to the reference250. Based on that comparison, the sense component245may determine a logic state that is stored on the memory cell205.

Access operations of the memory die200may be triggered or otherwise supported by core timing signals of the memory die200, or a memory device110that includes the memory die200, which may be generated by a timing signal generation component of the memory die200or associated memory device100. In one example, a local memory controller260may include a timing signal generation component265, but a timing signal generation component265may be included in other portions of a memory device110, or distributed between multiple components of a memory device. In one example, the timing signal generation component265may generate a read strobe signal, which may be an example of an asynchronous timing signal to support (e.g., trigger, initiate) latching information detected by the sense component245(e.g., output by a sense amplifier of the sense component245), transferring information to the input/output component255, or latching information of the input/output component255to a channel shared with a host device100(e.g., a DQ channel), among other purposes. The timing signal generation component265may generate a read strobe signal having a transition (e.g., rising edge, falling edge) that is delayed relative to a transition of a second signal, such as a column selection signal associated with the column decoder225selecting or activating a digit line215. In some examples, the timing signal generation component265may generate a read pulse signal having a pulse width (e.g., a duration between a rising edge and a falling edge) that is based at least in part on delay elements of the timing signal generation component265.

The timing signal generation component265may have operating characteristics that are sensitive to fabrication variability (e.g., process variability) or operating condition variability (e.g., voltage variability, temperature variability), such that timing signals of the memory die200may also be affected by such variability. Variability of timing signals may be associated with adverse performance of the memory die200, or a memory device110or system that includes the memory die200, including reduced read margins, increased read or write errors, longer latency to support timing or signaling uncertainties, and others. In accordance with examples as disclosed herein, the timing signal generation component265may include delay components, associated with access operation timing signal generation, that are configured to be selectively enabled or disabled (e.g., bypassed) based on a calibration operation. The selective enabling or disabling of such delay components may improve the ability of access operations performed on the memory die to be less dependent on fabrication variability, operating condition variability, or other phenomena.

FIG. 3illustrates an example of a timing circuit300that supports timing signal calibration for a memory device in accordance with examples as disclosed herein. The timing circuit300may refer to circuitry of a memory device110, and may be a component of a device memory controller155, a local memory controller165, or a local memory controller260, or other portions of a memory device110or memory die200. The timing circuit300includes a timing signal generation component310(e.g., an access timing component) configured to generate an access operation timing signal330based at least in part on one or more input signals320. The timing signal generation component310may be an example of the timing signal generation component265described with reference toFIG. 2.

The access operation timing signal330may be used to trigger or initiate various access operations (e.g., asynchronous operations) of a memory device110or memory die200that includes the timing circuit300. In one example, an access operation timing signal330may be a read strobe signal, which may be used to support (e.g., initiate, trigger) latching read data for output by a sense component245or input/output component255or other read latch. However, in other examples of the described techniques, an access operation timing signal330may refer to other types of timing or logical signals, including asynchronous timing or logical signals (e.g., asynchronous relative to a clock signal, asynchronous relative to a command signal), such as a read trigger signal, a signal used to support such operations as a row decoder220opening a row of memory cells205, a column decoder225activating one or more columns of memory cells205, a sense component245generating or latching sense signals, or a input/output component255latching or receiving an information exchange, among other operations.

The access operation timing signal330may be generated with various delays or durations relative to the one or more input signals320, where an input signal320may include such signals as a clock signal, a command signal, or some other synchronization or sequencing signal at a memory device110. In some examples, an input signal320may be received directly or indirectly from a host device105(e.g., over a CK channel, over a CA channel, via a device memory controller155). In some examples, an input signal320may be generated at or forwarded by a component of a memory device110, which may or may not be based on another signal received from a host device105.

The delays or durations of an access operation timing signal330relative to an input signal320may be supported by one or more delay components315of the timing signal generation component310. In some examples, a duration of a delay (e.g., an asynchronous delay) between an input signal320and an access operation timing signal330(e.g., between a rising edge or falling edge of the input signal320and a rising edge or falling edge of the access operation timing signal330) may be based at least in part one or more of the delay components315. In some examples, a pulse width of an access operation timing signal330(e.g., a duration between a rising edge and a falling edge of an access operation timing signal330, a duration between a falling edge and a rising edge of an access operation timing signal330) may be based at least in part on one or more of the delay components315. The delay components315may include such components or circuitry as transistors, inverters, capacitors, resistors, gate delay components, or other components that are associated with a timing or duration between transitions or levels of an input signal and an output signal. In some cases, the delay components315may be configured in a delay chain (e.g., in series with each other). In some cases, each of the delay components315may have the same or a similar delay (e.g., a same number of delay gates). Alternatively, the delay components315may be in parallel with each other (e.g., may have different delays), and the access operation timing signal330may be selected from an output of one of the delay components315.

Operating characteristics of the delay components315, or other components of a memory device110(e.g., other components of the timing signal generation component310, other components of a memory die200configured to support access operations), may be affected by variability, such as variations due to fabrication (e.g., processing variability, manufacturing variability) or operating conditions (e.g., voltage variability, temperature variability, frequency variability), such that access operation timing signals330may also be affected by such variability. For example, as a result of process or operating condition variability, access operation timing signals330may have longer or shorter delays relative to an input signal320, or may have a longer or shorter pulse width, among other variability.

To reduce the sensitivity of the timing signal generation component310, or other components or operations of a memory device110, to processing or operational variability, the timing circuit300may include a calibration component340configured to selectively enable or disable one or more of the delay components315of the timing signal generation component310. For example, the calibration component340may provide a calibration signal360(e.g., a delay configuration signal) to the delay components315, or other supporting circuitry of the timing signal generation component310(e.g., signal path selection components or circuitry), to cause a respective delay component315to be enabled (e.g., included in an access operation timing signal delay chain) or disabled (e.g., bypassed from an access operation timing signal delay chain). In various examples, the calibration component340may be co-located with the timing signal generation component310(e.g., in a memory die200), or the calibration component340may be located in a different portion of a memory device110(e.g., in a device memory controller155).

In some examples, the calibration component340may be configured to process a calibration input signal350(e.g., an input signal, a timing signal) sequentially through a set of delay components (e.g., of the calibration component340, which may be different than the delay components315) to generate a set of delayed timing signals. Each of the delayed timing signals may have a different delay duration, and respective timing signals may be compared directly or indirectly (e.g., using an intermediary signal based at least in part on the delayed timing signal) against another signal to evaluate a target delay duration, or whether an existing delay duration should be lengthened (e.g., by enabling one or more delay components315that was disabled) or shortened (e.g., by disabling one or more delay components315that was enabled. In other words, the different delays associated with respective ones of the set of delayed timing signals of the calibration component340may support an identification or inference of which delay components315, or how many delay components315, of the timing signal generation component310should be enabled to support the timing signal generation component310generating an access operation timing signal330.

The selective enabling or disabling of delay components315may improve the ability of a memory device to account for fabrication variability, operating condition variability, or other phenomena. For example, when the access operation timing signal330refers to a read strobe signal, a pulse width or timing of the read strobe signal may be sensitive to fabrication or operational variability of a memory device110. If a pulse width of a read strobe signal is too short, or a read strobe signal otherwise transitions at a duration too soon after a column selection or activation signal, read signals based on accessing a memory cell205may not be fully developed, which may be referred to as or otherwise associated with a setup margin failure. If a pulse width of a read strobe signal is too long, or a read strobe signal otherwise transitions without satisfying a hold margin relative to a first column selection or activation signal, a second column selection or activation signal may be issued prior to latching signaling or information based on accessing a first memory cell205associated with the first column selection or activation signal. In some such cases, a logic value associated with accessing the first memory cell205may be lost, or a different memory cell205may have been accessed (e.g., as associated with the second column selection or activation signal), which may be referred to as or otherwise associated with a hold margin failure. Thus, to support properly accessing a memory cell205for a read operation, aspects of a read strobe signal may be adjusted to account for fabrication or operational variations, among other reasons.

In some examples of generating read strobe signals, the calibration component340may be configured to calibrate the timing signal generation component310(e.g., by way of selectively enabling or disabling delay components315) to generate a read strobe signal with a pulse with that is equal to, or otherwise based at least in part on a pulse width, or cycle time (e.g., periodicity), of a clock signal or other reference signal. The clock signal used for such a calibration may be sampled or otherwise received at an instance that is unrelated to a particular access command, such that an access operation signal33is not itself generated based on the clock signal. Rather, the calibration component340may determine a calibration result from a received clock signal, with such a result stored or otherwise applied in multiple subsequent access operations to generate subsequent access operation timing signals330.

In some examples, the timing signal generation component310may be calibrated to generate a timing for an access operation timing signal330, relative to a column selection or activation signal, based on a selective enabling or disabling of delay components315. In some examples, a clock signal or other reference signal may be provided to the calibration component340as a calibration input signal350, such that the calibration component340generates the calibration signal360based on which delay components315or a quantity of delay components315that should be enabled or disabled to generate a read strobe signal (e.g., an access operation timing signal330) with the desired pulse width or duration. Such timing calibration may be based at least in part on performing a calibration operation that uses delay components of the calibration component340that are the same (e.g., having the same number or type of delay components), or different than the delay components315.

Thus, according to these and other examples, the timing signal generation component310may be configured for generating an access operation timing signal330having timing characteristics that are based at least in part on a selective enabling or disabling of delay components315, with such selective enabling or disabling being based at least in part on a calibration signal360. In some examples, the timing signal generation component310may support generating a pulse width for the access operation timing signal330based at least in part on the selective enabling or disabling of the second plurality of delay components315. Additionally or alternatively, the timing signal generation component310may support generating a timing or delay of the access operation timing signal330(e.g., a timing of a rising edge or falling edge, relative to the input signal320, such as a column selection signal) based at least in part on the selective enabling or disabling of the second plurality of delay components315.

Calibration operations using the calibration component340may be triggered or initiated based on various operations of a memory device110or memory die200. In some examples, performing calibration operations may be initiated based at least in part on identifying an initial configuration operation after powering on a memory device110, such as an initial mode register write operation performed after powering on a memory device110. In some examples, performing calibration operations may be initiated based at least in part on identifying a change of a frequency set point of a memory device110, which may be initiated by signaling received from a host device105. Calibration operations of the calibration component340may additionally or alternatively be initiated based on other operational modes or detections, such as a detection of an assembly or installation operation, an identified change in operating conditions, an identified change in operational modes, an identified abnormality in access timing (e.g., an identification of a setup margin failure or an identification of a hold margin failure), or an identified error detection or error correction condition, among other conditions, which may support dynamically adjusting timing characteristics of an access operation timing signal330in response to or to otherwise account for various sources of variability.

FIGS. 4A and 4Billustrate examples of a calibration input signal generator400and a calibration signal generator450, respectively, that support timing signal calibration for a memory device in accordance with examples as disclosed herein. The calibration input signal generator400and the calibration signal generator450may be included in a calibration component340described with reference toFIG. 3. The calibration signal generator450may support generating signals CAL<0:2> as a single calibration signal360-aor set of calibration signals360-a. The calibration input signal generator400may support generating signals EN1and EN2, which may be provided to the calibration signal generator450for generating signal or signals CAL<0:2>. Generating signals EN and EN2may be based at least in part on signal CLK, which may be an example of a calibration input signal350-a.

The calibration input signal generator400may be configured to support the calibration signal generator450performing a calibration operation based on an initial configuration operation after powering a memory device110. For example, a signal PWRUP may be enabled when the memory device110is powered, and a signal MRW may be enabled during a mode register write operation of the memory device110. Accordingly, during an initial mode register write operation (e.g., an initial enabling of signal MRW after enabling signal PWRUP), the calibration input signal generator400may proceed with generating signals EN1and EN2(e.g., based at least in part on toggling signal EN). The calibration input signal generator400may also be configured to support the calibration signal generator450performing a calibration operation based on a change in frequency set point of the memory device110. For example, a signal MDFSP may be enabled when the memory device110has been commanded with or is otherwise performing a frequency set point change. Accordingly, during an frequency set point operation, the calibration input signal generator400may proceed with generating signals EN1and EN2(e.g., based at least in part on toggling signal EN).

Generating signal EN1may be based at least in part on providing signal EN to a first D flip-flop (DFF), also fed by clock signal CLK. The first DFF may introduce a delay relative to signal EN, as a state transition of an output of the first DFF is triggered by a transition of clock signal CLK. The output of the first DFF may be fed through two inverters (e.g., delay inverters, gate delay components), which may introduce further delay, for generating the signal EN1(e.g., a rising edge of signal EN1).

Generating signal EN2may be based at least in part on providing the output of the first DFF to two further DFFs, also fed by clock signal CLK. The further DFFs may introduce further delays relative to signal EN, as a state transition of respective outputs of the further DFFs are triggered by a transition of clock signal CLK. The outputs of these DFFs may be fed through a NOR gate and inverter, as shown, for generating the signal EN2(e.g., a rising edge of signal EN2), which may be delayed relative to signal EN1. The signal EN2may be passed back through the calibration input signal generator400for generating falling edges of both signal EN1and signal EN2.

Signals EN1and EN2may be provided to the calibration signal generator450to support the generation of signals CAL<0:2>. For example, a duration between a rising edge of EN1and a rising edge of EN2may be approximately equal to a duration of one clock cycle (e.g., of clock signal CLK), which may be insensitive, or relatively insensitive, to fabrication or operating condition variations of the calibration input signal generator400. Such a duration between rising edges of EN1and EN2may be related to a target duration or pulse width for a read strobe signal, and the calibration signal generator450may accordingly enable or disable each of signals CAL<0:2> to support a timing signal generation component310generating a read strobe signal with such a duration or pulse width, or otherwise reducing variation to such a target that might be attributed to fabrication or operational variability.

The calibration signal generator450may receive the signal EN1(e.g., a timing signal, a calibration input signal350), and process the signal EN1through each of four delay components455(e.g., calibration delay components) as shown. Although four delay components455are shown in the calibration signal generator450, a calibration signal generator of calibration component340may include any quantity of delay components455. In some examples, at least some of a quantity of delay components455may be associated with or correspond to a quantity of delay components315of a timing signal generation component310that are configured to be selectively enabled or disabled.

Each of the delay components455may be associated with a respective quantity of gate delays, such as a quantity of inverters (e.g., delay inverters, gate delay components) or other delaying component (e.g., an 8-gate delay). A signal through the first delay component455-a(e.g., Default) may have a default delay, a signal through the second delay component455-b(e.g., D0) may have the accumulated delay of two of the delay components (e.g., delay components455-aand455-b), a signal through the third delay component455-c(e.g., D1) may have the accumulated delay of three of the delay components (e.g., delay components455-a,455-b, and455-c), and a signal through the fourth delay (e.g., D2) may have the accumulated delay of all four of the delay components (e.g., delay components455-a,455-b,455-c, and455-d). The signals D0, D1, and D2may be an example of delayed timing signals that each correspond to an output of a respective delay component.

The signals D0, D1, and D2may be provided to respective NAND gates, each being also provided with an inversion of the signal EN2, for generating respective signals N0, N1, and N2. The signals N0, N1, and N2may be processed through a glitch elimination circuit460, which may include respective glitch elimination circuit paths through skewed delay components, inverters, and gates as shown, for generating respective signals ND0, ND1, and ND2. However, in some examples, glitch elimination circuit460may be omitted. The calibration signal generator450may also process the signal EN2through a skewed delay component and inverters as shown, for generating a signal CONTROL. The skewed delay component and inverters for processing EN2may introduce a delay similar to that introduced by respective processing paths of the glitch elimination circuit460, which may help to maintain similar processing delays between signal EN2and signals NO, N1, and N2.

Each of the signals ND0, ND1, and ND2may be provided to a respective DFF465, which may be triggered by the signal CONTROL. Accordingly, each of the DFFs465may support comparing a second timing signal (e.g., CONTROL) to each of a set of reference signals (e.g., ND0, ND1, and ND2), each reference signal of the set of reference signals based at least in part on a respective one of a set of delayed timing signals (e.g., D0, D1, D2). In another example, each of the DFFs465may support latching, storing, or outputting a state of each of a set of reference signals based at least in part on (e.g., triggered by) a second timing signal. Thus, the DFFs465may be considered as a comparison component, a latching component, or a storage component that supports evaluating signals having different timing or delays, with such an evaluation being based at least in part on a target delay or pulse width for generating an access operation timing signal330.

The result of such a comparison or latching may be fed through further inverters and NAND gates as shown, for generating the signals CAL<0:2> (e.g., calibration signals360-a), which may be provided to a timing signal generation component310for selectively enabling one or more delay components315. For example, signal CAL<0> may support selectively including or bypassing a first delay component315in a delay chain of a timing signal generation component310, signal CAL<1> may support selectively including or bypassing a second delay component315in the delay chain, and signal CAL<2> may support selectively including or bypassing a third delay component315in the delay chain. In some examples, the second delay component455-bfor processing signal EN1may have a delay that is equal to, comparable, or otherwise representative of a delay of the first delay component315(e.g., corresponding to signal CAL<0>), the third delay component455-cfor processing signal EN1may have a delay that is equal to, comparable, or otherwise representative of a delay of the second delay component315(e.g., corresponding to signal CAL<1>), and the fourth delay component455-dfor processing signal EN1may have a delay that is equal to, comparable, or otherwise representative of a delay of the third delay component315(e.g., corresponding to signal CAL<2>). Although described with reference to three selectable delay components315, the calibration signal generator450may be extended to support generating a signal CAL<0:N−1> for any number N of selectable delay components.

According to these and other examples, the delay components455of the calibration signal generator450(e.g., a component of a calibration component340) may be surrogates for or otherwise correspond to respective delay components315of a timing signal generation component310. Operational variability of the delay components455may be used to infer operational variability of the delay components315, and comparisons or evaluations of a calibration operation may be used to mitigate the effect such variability of the delay components315would have on the access operation timing signal330, by way of selectively enabling or disabling delay components315.

FIGS. 5A and 5Billustrate examples of timing diagrams500and550, respectively, that support timing signal calibration for a memory device in accordance with examples as disclosed herein. The timing diagram500may illustrate an example of signaling of the calibration input signal generator400, and the timing diagram550may illustrate an example of signaling of the calibration signal generator450, described with reference toFIGS. 4A and 4B

The timing diagram500illustrates an example for generating signals EN1and EN2. In the example of timing diagram500, the signal MRW may transition to a high state, which may correspond to a first mode register write after powering a memory device110or memory die200that includes the calibration input signal generator. Thus, the timing diagram500illustrates an example of generating calibration signals or otherwise initiating a calibration operation based at least in part on a configuration operation of the memory device110, which may be an initial configuration operation after powering on the memory device110. Signals EN1and EN2may be based at least in part on clock signal CLK (e.g., a calibration input signal350-b), such as having a timing or pulse width that is based at least in part on clock signal CLK (e.g., a cycle time or period, tCLK, of clock signal CLK).

The timing diagram550illustrates an example for generating signals CAL<0:2> (e.g., calibration signals360-b) based at least in part on signals EN1and EN2. In the example of timing diagram550, a signal EN2fmay illustrate a signal after a first inverter that is provided with the signal EN2, and may represent an inversion of EN2. A duration between the rising edge of EN1and the falling edge of EN2fmay be approximately equal to a clock cycle duration, tCLK(e.g., as described with reference to timing diagram500), and may be used as a calibration duration for determining which of the signals CAL<0:2> should be enabled or activated.

The timing diagram550illustrates signals D0, D1, and D2, which may be an example of a set of delayed timing signals that each correspond to a respective delay component455of the calibration signal generator450. Signals D0, D1, and D2may have a similar pulse width as signal EN1, but each of D0, D1, and D3may have a different respective delay in time, as shown. Signals ND0, ND1, and ND2may refer to the processed signals output by the glitch elimination circuit460of calibration signal generator450. The signals ND0, ND1, and ND2may be compared, latched, or stored by respective DFFs465, as triggered by the rising edge of the signal CONTROL (e.g., at time555). The resulting output of the DFFs465may be further processed, and used to evaluate whether to enable respective ones of the signals CAL<0:2>. In the example of timing diagram550, signals ND0and ND1are at a low signal state during the rising edge of CONTROL, and accordingly, signals CAL<0> and CAL<1> may transition to a high signal state. Signal ND2is at a high signal state during the rising edge of CONTROL, and accordingly, signal CAL<2> may remain in a low signal state.

Timing diagram550illustrates an example where, at the calibration signal generator450, a default delay (e.g., according to a single delay component) is insufficient to meet a target timing (e.g., a duration of one clock cycle). Rather, the calibration signal generator450determines that delays of at least two additional delay components (e.g., delay components315) should be enabled (e.g., corresponding to the generation of signals D0and D1). The calibration signal generator450also determines that a delay of a third additional delay (e.g., corresponding to the generation of signal D2) component would be excessive relative to the target. Such determinations may account for fabrication or operational variations of the calibration signal generator450(e.g., of the delay components for generating the signals ND0, ND1, ND2, including delay components, inverters, and gates), which may correspond to similar operational variations that may be experienced at a timing signal generation component310. By activating signals CAL<0> and CAL<1>, and deactivating signal CAL<2>, (e.g., calibration signals360-b) the calibration signal generator450may provide, to a timing signal generation component310, an indication that corresponding delay components315should be enabled, or disabled, respectively.

In another example, not shown, the signal processing of calibration signal generator450may operate more quickly (e.g., due to processing or operational variation), such that signal ND2is also at a low state during the rising edge of CONTROL. In such a case, signal CAL<2> may also be activated, activating or enabling an additional delay component315of a timing signal generation component310(e.g., to lengthen a read strobe pulse duration that would otherwise be too short due to the processing or operational variation). In yet another example, not shown, the signal processing of calibration signal generator450may operate more slowly (e.g., due to processing or operational variation), such that neither the signal ND1nor the signal ND2is at a low state during the rising edge of CONTROL. In such a case, signals CAL<1> and CAL<2> may be deactivated, such that one delay component315of timing signal generation component310is selectively enabled or activated (e.g., bypassing certain delay components315to shorten a read strobe pulse duration that would otherwise be too long due to the processing or operational variation).

FIG. 6illustrates an example of delay circuitry600that supports timing signal calibration for a memory device in accordance with examples as disclosed herein. In the example of delay circuitry600, a signal AF may represent a column selection or activation signal (e.g., a signal320-c), and a signal YF may represent a read strobe signal (e.g., an access operation timing signal330-c) generated based at least in part on the signal AF and a set of delay components605.

The delay components605may each represent a respective set of one or more gate delay components, and may accordingly each correspond to a respective delay duration. The delay component605-amay generate a delay between the signal AF, as input to the delay circuitry600, and the output signal YF, such as a delay between a rising edge of AF and a rising edge of YF. Further delay between a rising edge of AF and a rising edge of YF may be introduced by the inverters or gates, as shown. A rising edge of the signal YF may be returned through a feedback loop to generate a falling edge, for example, and a duration between the rising edge of YF and the falling edge of YF may correspond to a pulse width of signal YF.

The feedback loop may include delay components605-band605-c, which may contribute to a default delay for the feedback loop. The feedback loop may also include delay components605-d,605-e, and605-f, which may be examples of delay components315described with reference toFIG. 3. Each of delay components605-d,605-e, and605-fmay illustrate an example of a delay component of the delay circuitry600that is configured to be selectively enabled (e.g., included in the feedback loop) or disabled (e.g., bypassed in the feedback loop). For example, the selective enabling or disabling of delay components605-d,605-e, and605-fmay be supported by signals tm<0:2>, which may correspond to inverted states of signals CAL<0:2>, respectively, as described with reference toFIG. 5B.

For example, the delay component605-dmay be selectively enabled or disabled by way of signal tm<0>, which may be described as a disabling or bypassing signal associated with the delay component605-d. When signal tm<0> is at a high state, the output of the NAND gate610-amay be effectively disabled, since the high state of signal tm<0> may cause an output of the NAND gate610-ato remain at a low state regardless of the state at node615. Accordingly, any rising edge or falling edge of signaling at the node615may instead pass through the NAND gate610-b, as fed by the inverted state of tm<0> (e.g., inverted to a low state), effectively bypassing the delay component605-d. When signal tm<0> is at a low state, the output of the NAND gate610-bmay be effectively disabled, since the inverted low state of signal tm<0> (e.g., a high state) may cause an output of the NAND gate610-bto remain at a low state regardless of the state at node615. Accordingly, any rising edge or falling edge of signaling at the node615may instead pass through the NAND gate610-a, as fed by the low state of tm<0>, and any rising or falling edge at the node615may be delayed by passing through the delay component605-d. Similarly, the delay component605-emay be selectively enabled or disabled by way of signal tm<1>, which may be described as a disabling or bypassing signal associated with the delay component605-e, and the delay component605-fmay be selectively enabled or disabled by way of signal tm<2>, which may be described as a disabling or bypassing signal associated with the delay component605-f.

Thus, the delay circuitry600may be included in a timing signal generator, such as timing signal generation component310described with reference toFIG. 3, where delay components605-d,605-e, and605-fmay be examples of delay components315that are configured to be selectively enabled or disabled. Delay components605-a,605-b, and605-cmay be examples of other delay components of a timing signal generator that are not configured to be selectively enabled or disabled (e.g., are included in the delay chain regardless of a calibration signal360). By including delay components605-d,605-e, and605-f, the delay circuitry600may support a dynamic calibration of read strobe timing, such as a dynamic calibration of a pulse width of the read strobe signal. Such a calibration may support hold margins or setup margins that track process or operational variability, which may improve operations of a memory device110or system100that includes the delay circuitry600compared to operations of a memory device110or system100that does not include the delay circuitry600or other configurable timing signal generation component310.

FIG. 7shows a block diagram700of a memory device705that supports timing signal calibration for a memory device in accordance with examples as disclosed herein. The memory device705may be an example of aspects of a memory device as described with reference toFIGS. 1 through 5. The memory device705may include a calibration delay chain component710, a calibration signal comparison component715, an access operation delay chain component720, an access operation timing signal generation component725, a memory device initialization component730, a calibration initiation component735, a memory device frequency configuration component740, a comparison signal generation component745, and a glitch elimination component750. Each of these modules may communicate, directly or indirectly, with one another (e.g., via one or more buses).

The calibration delay chain component710may process a first timing signal sequentially through each of a first set of delay components of a memory device to generate a set of delayed timing signals that each correspond to an output of a respective delay component of the first set of delay components.

The calibration signal comparison component715may compare a second timing signal to each of a set of reference signals, each reference signal of the set of reference signals based on a respective one of the set of delayed timing signals.

The access operation delay chain component720may selectively enable or disable, based on the comparing, a second set of delay components configured for generating an access operation timing signal of the memory device. In some examples, the second set of delay components may be different than the first set of delay components.

In some examples, the access operation timing signal generation component725may generate the access operation timing signal for latching data for output by the memory device based on the selectively enabling or disabling of the second set of delay components.

In some examples, to generate the access operation timing signal, the access operation timing signal generation component725may generate a pulse width for the access operation timing signal based on the selectively enabling or disabling of the second set of delay components.

In some examples, to generate the access operation timing signal, the access operation timing signal generation component725may generate a timing for the access operation timing signal relative to a column selection of the memory device based on the selectively enabling or disabling of the second set of delay components.

In some examples, the memory device initialization component730may identify an initial configuration operation after powering the memory device.

In some examples, the calibration initiation component735may generate the first timing signal based on identifying the initial configuration operation.

In some examples, the memory device frequency configuration component740may identify a change of a frequency set point of the memory device.

In some examples, the calibration initiation component735may generate the first timing signal based on identifying the change of the frequency set point.

In some examples, the comparison signal generation component745may generate the second timing signal based on a pulse width of a clock signal received at the memory device.

In some examples, glitch elimination component750may generate each of the set of reference signals based on processing a respective one of the set of delayed timing signals through a respective glitch elimination component.

FIG. 8shows a flowchart illustrating a method or methods800that supports timing signal calibration for a memory device in accordance with aspects of the present disclosure. The operations of method800may be implemented by a memory device or its components as described herein. For example, the operations of method800may be performed by a memory device as described with reference toFIG. 7. In some examples, a memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Additionally or alternatively, a memory device may perform aspects of the described functions using special-purpose hardware.

At805, the memory device may process a first timing signal sequentially through each of a first set of delay components of a memory device to generate a set of delayed timing signals that each correspond to an output of a respective delay component of the first set of delay components. The operations of805may be performed according to the methods described herein. In some examples, aspects of the operations of805may be performed by a calibration delay chain component as described with reference toFIG. 7.

At810, the memory device may compare a second timing signal to each of a set of reference signals, each reference signal of the set of reference signals based on a respective one of the set of delayed timing signals. The operations of810may be performed according to the methods described herein. In some examples, aspects of the operations of810may be performed by a calibration signal comparison component as described with reference toFIG. 7.

At815, the memory device may selectively enable or disabling, based on the comparing, a second set of delay components configured for generating an access operation timing signal of the memory device. The operations of815may be performed according to the methods described herein. In some examples, aspects of the operations of815may be performed by an access operation delay chain component as described with reference toFIG. 7.

In some examples, an apparatus as described herein may perform a method or methods, such as the method800. The apparatus may include features, circuitry, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for processing a first timing signal sequentially through each of a first set of delay components of a memory device to generate a set of delayed timing signals that each correspond to an output of a respective delay component of the first set of delay components, comparing a second timing signal to each of a set of reference signals, each reference signal of the set of reference signals based on a respective one of the set of delayed timing signals, and selectively enabling or disabling, based on the comparing, a second set of delay components configured for generating an access operation timing signal of the memory device.

Some examples of the method800and the apparatus described herein may further include operations, features, circuitry, means, or instructions for generating the access operation timing signal for latching data for output by the memory device based on the selectively enabling or disabling of the second set of delay components.

In some examples of the method800and the apparatus described herein, generating the access operation timing signal may include operations, features, circuitry, means, or instructions for generating a pulse width for the access operation timing signal based on the selectively enabling or disabling of the second set of delay components.

In some examples of the method800and the apparatus described herein, generating the access operation timing signal may include operations, features, circuitry, means, or instructions for generating a timing for the access operation timing signal relative to a column selection of the memory device based on the selectively enabling or disabling of the second set of delay components.

Some examples of the method800and the apparatus described herein may further include operations, features, circuitry, means, or instructions for identifying an initial configuration operation after powering the memory device, and generating the first timing signal based on identifying the initial configuration operation.

Some examples of the method800and the apparatus described herein may further include operations, features, circuitry, means, or instructions for identifying a change of a frequency set point of the memory device, and generating the first timing signal based on identifying the change of the frequency set point.

Some examples of the method800and the apparatus described herein may further include operations, features, circuitry, means, or instructions for generating the second timing signal based on a pulse width of a clock signal received at the memory device.

Some examples of the method800and the apparatus described herein may further include operations, features, circuitry, means, or instructions for generating each of the set of reference signals based on processing a respective one of the set of delayed timing signals through a respective glitch elimination component.

In some examples of the method800and the apparatus described herein, the second set of delay components may be different than the first set of delay components.

An apparatus is described. The apparatus may include an array of memory cells, a timing calibration component including: a first set of delay components configured to generate a set of delayed timing signals that each correspond to an output of a respective delay component of the first set of delay components, and a comparison component configured to generate a set of delay configuration signals, each delay configuration signal generated based on comparing a second timing signal to a respective one of a set of reference signals, each reference signal of the set of reference signals based on a respective one of the set of delayed timing signals. The apparatus may also include an access timing component coupled with the array of memory cells and the timing calibration component, the access timing component including a second set of delay components configured to generate an access operation timing signal to access the array of memory cells, where each delay component of the second set of delay components may be configured for being selectively enabled or disabled based on the set of delay configuration signals.

In some examples, the access timing component may be configured to generate the access operation timing signal for latching data for output by the apparatus based on the second set of delay components being selectively enabled or disabled.

In some examples, the access timing component may be configured to generate the access operation timing signal with a pulse width that is based on the second set of delay components being selectively enabled or disabled.

In some examples, the access timing component may be configured to generate the access operation timing signal with a timing, relative to a column selection of the array of memory cells, that is based on the second set of delay components being selectively enabled or disabled.

In some examples, the timing calibration component may be configured to generate the set of delay configuration signals based on identifying an initial configuration operation after powering the apparatus.

In some examples, the timing calibration component may be configured to generate the set of delay configuration signals based on identifying a change of frequency set point of the apparatus.

Some examples of the apparatus may include a second signal generator configured for generating the second timing signal based on a pulse width of a clock signal.

In some examples, the timing calibration component may include a set of glitch elimination circuits, and the timing calibration component may be configured for generating each reference signal of the set of reference signals based on a respective one of the set of glitch elimination circuits.

In some examples, each delay component of the first set of delay components includes a respective set of transistor gate delay components.

In some examples, each delay component of the second set of delay components includes a respective second set of transistor gate delay components different than the respective set of transistor gate delay components of the first set of delay components.

Another apparatus is described. The apparatus may include an array of memory cells, a column decoder coupled with the array of memory cells and configured to activate a column of the array of memory cells based on a column selection signal, a read latch coupled with the array of memory cells and configured to latch a result of accessing a memory cell of the activated column based on a read trigger signal, and a signal generator coupled with the column decoder and the read latch, the signal generator configured to generate the read trigger signal with a timing, relative to the column selection signal, that is based on selectively enabling or disabling a set of delay components according to a delay value.

Some examples of the apparatus may include delay calibration circuitry configured to process a first timing signal sequentially through each of a second plurality of delay components to generate a plurality of delayed timing signals, each delayed timing signal of the plurality of delayed timing signals corresponding to an output of a respective delay component of the second plurality of delay components, compare a second timing signal to each of a plurality of reference signals, each reference signal of the plurality of reference signals based at least in part on a respective one of the plurality of delayed timing signals, and generate the delay value associated with the selectively enabling or disabling the plurality of delay components of the signal generator

In some examples of the apparatus, the delay calibration circuitry may be configured to generate the second timing signal based on a pulse width of a clock signal received at the apparatus.

In some examples of the apparatus, the delay calibration circuitry may be configured to generate each of the set of reference signals based on processing a respective one of the set of delayed timing signals through a respective glitch elimination component.

In some examples of the apparatus, the delay calibration circuitry may be configured to identify an initial configuration operation after powering the apparatus, and generate, based on identifying the initial configuration operation, a set of delay configuration signals associated with the selectively enabling or disabling the set of delay components of the signal generator.

In some examples of the apparatus, the delay calibration circuitry may be configured to identify a change of a frequency set point of the apparatus, and generate, based on identifying the change of the frequency set point, a set of delay configuration signals associated with the selectively enabling or disabling the set of delay components of the signal generator.

In some examples, the signal generator may be configured to generate the read trigger signal with a pulse width that may be based on the selective enabling or disabling.