Driving apparatus

A driving apparatus is provided. A first stage inverter circuit and a second stage inverter circuit respectively generate a first output signal and a second output signal according to a first voltage dividing control signal and a second voltage dividing control signal, wherein the first output signal and the second output signal are respectively output to the second-stage inverter circuit and the first-stage inverter circuit to appropriately control the gate voltages of transistors of pull-up circuit and the pull-down circuit in the first-stage inverter circuit and the second-stage inverter circuit, so that source-drain voltages differences of the transistors can be more evenly distributed.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan application Ser. No. 107141806, filed on Nov. 23, 2018. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

BACKGROUND

Field of the Invention

The invention relates to an electronic apparatus and more particularly, to a driving apparatus.

Description of Related Art

In a general driver circuit, an inverter circuit is usually used to invert or delay signals. The inverter circuit may be formed by, for example, a plurality of P-type transistors connected in series and a plurality of N-type transistors connected in series. Gates of the P-type transistors connected in series and gates of the N-type transistors connected in series may be coupled to the same input voltage to obtain an inverted voltage at an output terminal of the inverter circuit. However, when the transistors connected in series are in turned-off states, the gate voltages of the transistors are the same, which causes the voltage difference between the source and the drain of each of the transistors connected in series to be different. As a result, a part of the transistors connected in series in the inverter circuit will endure the larger voltage differences, such that the life of the transistors is reduced, and leakage currents of the transistors are increased. Moreover, it may further cause breakdown in the transistors, and the driver circuit may be incapable of driving a later stage circuit normally.

SUMMARY

A driving apparatus of the invention includes a first voltage dividing circuit, a second voltage dividing circuit, a first stage inverter circuit and a second stage inverter circuit. The first voltage dividing circuit divides the first input signal to generate a first voltage dividing control signal. The second voltage dividing circuit divides the second input signal to generate a second voltage dividing control signal, wherein the first input signal and the second input signal are inverted with respect to each other. The first stage inverter circuit is coupled to the first voltage dividing circuit and generates a first output signal according to the first voltage dividing control signal. The second stage inverter circuit is coupled to the second voltage dividing circuit and the first stage inverter circuit. The second stage inverter circuit generates a second output signal and a first driving signal according to the second voltage dividing control signal, wherein the first output signal is configured to bias the second stage inverter circuit, and the second output signal is configured to bias the first stage inverter circuit.

DESCRIPTION OF EMBODIMENTS

FIG. 1is a schematic diagram illustrating a driving apparatus according to an embodiment of the invention. Please refer toFIG. 1. A driving apparatus includes a signal input circuit102, a voltage dividing circuit104, a voltage dividing circuit106, a first stage inverter circuit108and a second stage inverter circuit110. The voltage dividing circuit104is coupled to the signal input circuit102and the first stage inverter circuit108. The second stage inverter circuit110is coupled to the voltage dividing circuit106and the first stage inverter circuit108. The signal input circuit102may receive an input signal Vin2and invert the input signal Vin2to generate an input signal Vin1. The input signal Vin1and the input signal Vin2are respectively provided to the voltage dividing circuit104and the voltage dividing circuit106. The voltage dividing circuit104may divide the input signal Vin1to generate a voltage dividing control signal Vd1, and the voltage dividing circuit106may divide the input signal Vin2to generate a voltage dividing control signal Vd2.

In addition, the first stage inverter circuit108generates an output signal Vcon1according to the voltage dividing control signal Vd1, and the second stage inverter circuit110generates an output signal Vcon2and a driving signal Vout1according to the voltage dividing control signal Vd2. The output signal Vcon1is configured to bias the second stage inverter circuit110, the output signal Vcon2is configured to bias the first stage inverter circuit108, and the driving signal Vout1is configured to drive a later stage circuit, for example, a radio frequency (RF) switch circuit, but the invention is not limited thereto. In this way, the output signal Vcon1and the output signal Vcon2are respectively generated by the first stage inverter circuit108and the second stage inverter circuit110according to the voltage dividing control signal Vd1and the voltage dividing control signal Vd2to control the gate voltages of the transistors connected in series in the first stage inverter circuit108and the second stage inverter circuit110, such that the voltage difference of the transistors in the first-stage inverter circuit108and the second-stage inverter circuit110may be distributed evenly to reduce the leakage currents of the transistors and avoid the breakdown in the transistors, so that the driving apparatus may normally drive the later stage circuit (for example, a RF switching circuit, but the invention is not limited thereto) and extend the life of the circuit.

FIG. 2is a schematic diagram illustrating a driving apparatus according to another embodiment of the invention. Please refer toFIG. 2, the first stage inverter circuit108and the second stage inverter circuit110of the embodiment illustrated inFIG. 1may respectively include pull-up circuits and pull-down circuits, as illustrated inFIG. 2. Referring toFIG. 2, a pull-up circuit202of the first stage inverter circuit108is coupled to the voltage dividing circuit104, a pull-down circuit204and a pull-down circuit208. A pull-up circuit206of the second stage inverter circuit110is coupled to the voltage dividing circuit106, the pull-down circuit208and the pull-down circuit204. The pull-up circuit202and the pull-up circuit206may respectively provide pull-up paths to change voltage levels of the output signal Vcon1, the output signal Vcon2and the driving signal Vout1by turning on or turning off the pull-up paths. In addition, the pull-down circuit204and the pull-down circuit208respectively provide pull-down paths to change the voltage levels of the output signal Vcon1, the output signal Vcon2and the driving signal Vout1by turning on or turning off the pull-down paths.

In detail, the driving apparatus of the embodiment illustrated inFIG. 2may be implemented, for example, by a circuit of the embodiment illustrated inFIG. 3. In the embodiment illustrated inFIG. 3, the signal input circuit102includes P-type transistors P1and P2and N-type transistors M1and M2. The P-type transistors P1and P2and the N-type transistors M1and M2are connected in series between an operation voltage terminal for providing an operation voltage Vdd and a reference potential terminal for providing a reference voltage (which may be a ground voltage, but the invention is not limited thereto). The P-type transistors P1and P2and the N-type transistors M1and M2are coupled to the input signal Vin2. An inverter circuit formed by the P-type transistors P1and P2and the N-type transistors M1and M2may generate the input signal Vin1which is inverted with respect to the input signal Vin2. In another embodiment, the P-type transistor P2and the N-type transistor M2may be omitted, such that the signal input circuit102includes the P-type transistor P1and the N-type transistor M1which are connected in series between the operation voltage terminal for providing the operation voltage Vdd and the reference potential terminal for providing the reference voltage.

The voltage dividing circuit104, the voltage dividing circuit106, the first stage inverter circuit108and the second stage inverter circuit110may be formed by, for example, an SOI process or a bulk CMOS process, but the invention is not limited thereto. The voltage dividing circuit104and the voltage dividing circuit106may respectively include a plurality of voltage dividing elements. The voltage dividing elements included in the voltage dividing circuit104are connected in series between an input signal terminal for providing the input signal Vin1and the reference potential terminal for providing the reference voltage to distribute a voltage of the input signal Vin1. The voltage dividing elements included in the voltage dividing circuit106are connected in series between an input signal terminal providing the input signal Vin2and the reference potential terminal for providing the reference voltage to distribute a voltage of the input signal Vin2. The voltage dividing elements may at least include, for example, resistors, diodes or transistors, but the invention is not limited thereto. In the present embodiment, the voltage dividing circuit104and the voltage dividing circuit106include resistors R1to R3and resistors R4to R6, respectively. The voltage of the input signal Vin1may be divided by the resistors R1to R3connected in series to generate divided voltages VdA to VdC (the divided voltages VdA to VdC are voltage signals included in the voltage dividing control signal Vd1). Similarly, the voltage of the input signal Vin2may be divided by the resistors R4-R6connected in series to generate divided voltages VdD to VdF (the divided voltages VdD to VdF are voltage signals included in the voltage dividing control signal Vd2). For example, the voltage of the input signal Vin1may be, for example, 0V, and the voltage of the input signal Vin2may be, for example, 3V, the divided voltages VdA to VdC may be, for example, 0V, and the divided voltages VdD to VdF may be, for example, 3V, 1.6V and 0V, respectively. The configuration of each of the divided voltages may be determined according to resistance values of the resistors, the number of the diodes or the sizes of the transistors in the voltage dividing elements.

The pull-up circuits and pull-down circuits may respectively include first conductivity type transistors and second conductivity type transistors. The first conductivity type transistors and the second conductivity type transistors may at least include, for example, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Pseudomorphic High Electron Mobility Transistors (PHEMTs) or Bipolar Junction Transistors (BJTs), but the invention is not limited thereto. For example, in the present embodiment, the pull-up circuit202and the pull-up circuit206respectively include P-type transistors P3to P5and P-type transistors P6to P8, and the pull-down circuit204and the pull-down circuit208respectively include N-type transistors M3to M5and N-type transistors M6to M8, and the P-type transistors P3to P5, P6-P8and the N-type transistors M3to M5, M6to M8are connected in series between the operation voltage terminal for providing the operation voltage Vdd and an operation voltage terminal for providing the operation voltage Vss, wherein the operation voltage Vdd is greater than the operation voltage Vss. Gates of the P-type transistors P3to P5in the pull-up circuit202may respectively receive the divided voltages VdA to VdC, such that the P-type transistors P3to P5may respectively provide the output voltages Vc1to Vc3from sources thereof (wherein, the output voltages Vc1to Vc3are voltage signals included in the output signal Vcon1). Similarly, gates of the P-type transistors P6to P8in the pull-up circuit206may respectively receive the divided voltages VdD to VdF, such that the P-type transistors P6to P8may respectively provide the output voltage Vc4, the output voltage Vc5and the driving signal Vout1from sources thereof (wherein the output voltages Vc4and Vc5and the driving signal Vout1are voltage signals included in the output signal Vcon2). That is, the second pull-up circuit206pulls up/generates a voltage of the second output signal Vcon2(including the driving signal Vout1) according to the divided voltages VdD to VdF of the second voltage dividing control signal. In addition, the output voltages Vc1to Vc3may be respectively provided to gates of the N-type transistors M6to M8in the pull-down circuit208, and the output voltage Vc4, the output voltage Vc5and the driving signal Vout1may be respectively provided to gates of the N-type transistors M3to M5in the pull-down circuit204. In this way, the voltage dividing circuits104and106are utilized to adaptively divide the voltages of the input signals Vin1and Vin2and to control gate voltages of the P-type transistors P3to P8in the pull-up circuit202and the pull-up circuit206according to the divided voltages VdA to VdF, such that voltage differences of the transistors in the pull-up circuit206and the pull-down circuit204may be equal to each other, i.e., the source-drain voltage differences of the transistors in the pull-up circuit206and the pull-down circuit204may be evenly distributed. Thereby, the driving apparatus may be prevented from being incapable of normally driving the later stage circuit due to breakdown in the transistors, leakage cuiTents of the transistors may be reduced, and the life of the transistors may be extended. In addition, in another embodiment, the source-drain voltage differences of the transistors may also not be equal to each other, that is, the voltage difference that does not cause the breakdown in the transistors is acceptable.

For example, when the operation voltage Vdd is 3V, the operation voltage Vss is -2V, the voltage of the input signal Vin1is 0V, the voltage of the input signal Vin2is 3V, and the resistance of each of the resistors R1to R6is 1MΩ, the divided voltages VdA to VdC may be 0V, and the divided voltages VdD to VdF may be, for example, 3V, 1.6V and 0V, respectively. The gates of the P-type transistors P3to P5in the pull-up circuit202are respectively controlled by the divided voltages VdA to VdC which are divided from the input signal Vin1, and are in turned-on states (i.e., the pull-up path provided by the pull-up circuit202is turned on), such that the output voltages Vc1to Vc3are equal to 3V. In addition, the gates of the N-type transistors M6to M8in the pull-down circuit208are controlled by the output voltages Vc1to Vc3, and are in turned-on states (i.e., the pull-down path provided by the pull-down circuit208is turned on). That is, the turning on and turning off of the pull-down path of the pull-down circuit208is related to the output voltages Vc1to Vc3and the input signal Vin1. The gates of the P-type transistors P6to P8in the pull-up circuit206are respectively controlled by the divided voltages VdD to VdF which are divided from the input signal Vin2, and are in turned-off states (i.e., the pull-up path provided by the pull-up circuit206is turned off), such that the output voltage Vc4, the output voltage Vc5and the driving signal Vout1are equal to 1.6V, 0V and -2V, respectively. In the present embodiment, the driving signal Vout1is in phase with the input signal Vin1and is inverted with respect to the input signal Vin2, and thus, the driving apparatus may be substantially an inverter. In addition, the gates of the N-type transistors M3to M5in the pull-down circuit204are respectively controlled by the output voltage Vc4, the output voltage Vc5and the driving signal Vout1to turn off the pull-down path provided by the pull-down circuit204. That is, the turning on and turning off of the pull-down path of the pull-down circuit204are responsive to the output voltage Vc4, the output voltage Vc5, the driving signal Vout1and the input signal Vin2. In the present embodiment, since the gates of the P-type transistors P6to P8in the pull-up circuit206and the gates of the N-type transistors M3to M5in the pull-down circuit204are controlled by different voltages, the source-drain voltage differences of the P-type transistors P6to P8and the N-type transistors M3to M5may be adaptively adjusted to avoid a part of the transistors enduring the larger voltage differences in the pull-up circuit206and the pull-down circuit204when the pull-up path provided by the pull-up circuit206and the pull-down path provide by the pull-down circuit204are turned off. In this way, the driving apparatus may be prevented from being incapable of normally driving the later stage circuit due to the breakdown in the transistors, the leakage currents of the transistors may be effectively reduced and the life of the transistors may be extended. By deriving by analogy, when the voltage of the input signal Vin1is 3V and the voltage of the input signal Vin2is 0V, the voltages of the input signals Vin1and Vin2may also be adaptively divided by the voltage dividing circuits104and106, such that the voltage differences of the transistors in the pull-up circuits and the pull-down circuits of which the paths are turned off may be evenly distributed, but the related details will-no not be repeatedly described.

It should be noted that in other embodiments, the driving apparatus is not limited to have only two stages of inverter circuits as that in the embodiments described above, and the driving apparatus may also have more stages of inverter circuits.FIG. 4is a schematic diagram lustrating a driving apparatus according to another embodiment of the invention. The embodiment inFIG. 4is different from the embodiment inFIG. 1in that the driving apparatus illustrated inFIG. 4further includes a third stage inverter circuit402which is coupled to the second stage inverter circuit110. In the present embodiment, the second stage inverter circuit may generate output signals Vcon2and Vcon3according to the voltage dividing control signal Vd2and the output signal Vcon1. The third stage inverter circuit402may generate a driving signal Vout2according to the output signals Vcon2and Vcon3to drive a later stage circuit (for example, an RF switch circuit, which is not limited in the invention). Similarly, as illustrated inFIG. 5, the third stage inverter circuit402may also include a pull-up circuit502and a pull-down circuit504. A common terminal of the pull-up circuit502and the pull-down circuit504generates the driving signal Vout2. The pull-up circuit502may provide a pull-up path for pulling up a voltage of the driving signal Vout2. Turning on and turning off of the pull-up path of the pull-up circuit502for pulling up the voltage of the driving signal Vout2is related to the input signal Vin1and the output signal Vcon3. The pull-down circuit504may provide a pull-down path for pulling down the voltage of the driving signal Vout2. Turning on and turning off of the pull-down path of the pull-down circuit504for pulling down the voltage of the driving signal Vout2is related to the input signal Vin2and the output signal Vcon2.

In detail, the driving apparatus of the embodiment illustrated inFIG. 5may be implemented by, for example, a circuit of the embodiment illustrated inFIG. 6. In the embodiment illustrated inFIG. 6, implementation of the signal input circuit102, the voltage dividing circuit104, the voltage dividing circuit106, the pull-up circuit202, the pull-up circuit206, the pull-down circuit204and the pull-down circuit208are the same as those in the embodiment illustrated inFIG. 5and thus will not be repeatedly described. Similarly, the pull-up circuit502and the pull-down circuit504of the embodiment illustrated inFIG. 6may respectively include first conductivity type transistors and second conductivity type transistors. The first conductivity type transistors and the second conductivity type transistors may at least include, for example, Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), Pseudomorphic High Electron Mobility Transistors (PHEMTs) or Bipolar Junction Transistors (BJTs), but the invention is not limited. For example, in the present embodiment, the pull-up circuit502and the pull-down circuit504include P-type transistors P9-P11and N-type transistors M9-M11which are connected in series between the operation voltage terminal for providing the operation voltage Vdd and the operation voltage terminal for providing the operation voltage Vss. Gates of the P-type transistors P9to P11are controlled by the driving signal Vout1, an output voltage Vc6and an output voltage Vc7(wherein the driving signal Vout1, the output voltage Vc6and the output voltage Vc7are voltage signals included in the output signal Vcon3). When a pull-down path of the N-type transistors M6to M8in the pull-down circuit208is turned on, voltages of the driving signal Vout1, the output voltage Vc6and the output voltage Vc7are pulled down to the operation voltage Vss, such that the P-type transistors P9-P11in the pull-up circuit502are turned on, i.e., the pull-up path provided by the pull-up circuit502is turned on. In addition, gates of the N-type transistors M9to M11are controlled by the output voltage Vc4, the output voltage Vc5and the driving signal Vout1provided by the pull-up circuit206(wherein the driving signal Vout1, the output voltage Vc4and the output voltage Vc5are voltage signals included in the output signal Vcon2) and are in turned-off states (i.e., the pull-down path provided by the pull-down circuit504is turned off). That is, turning on and turning off of the pull-up path of the pull-up circuit502are responsive to the output voltage Vc6, the output voltage Vc7, the driving signal Vout1and the input signal Vin1, and turning on and turning off of the pull-down path of the pull-down circuit504are responsive to the output voltage Vc4, the output voltage Vc5, the driving signal Vout1and the input signal Vin2. The driving signal Vout1is related to the output signals Vcon2and Vcon3. According to the embodiments above, when the pull-down path in the pull-down circuit504is turned off, the output voltage Vc4, the output voltage Vc5and the driving signal Vout1may be adaptively adjusted by the dividing of the voltage dividing circuit106, such that source-drain voltage differences of the N-type transistors M9to M11may be evenly distributed to avoid a part of the transistors enduring the larger voltage differences. Following the example provided in the embodiment illustrated inFIG. 3, when the operation voltage Vdd is 3V, the operation voltage Vss is -2V, the voltage of the input signal Vin1is 0V, and the voltage of the input signal Vin2is 3V, the voltages of the driving signal Vout1, the output voltages Vc6and Vc7will be -2V, and a voltage level of the driving signal Vout2will be 3V to drive the later stage circuit. In the present embodiment, the driving signal Vout2is inverted with respect to the input signal Vin1and is in phase with the input signal Vin2, and thus, the driving apparatus may be substantially an inverter.

The embodiments of present invention utilize the voltage dividing circuits to adaptively divide the input voltages and control the gate voltages of the transistors in the pull-up circuit and the pull-down circuit in the inverter circuits according to the divided voltages which are divided from the voltages of the input signals. Even in the case where the driving apparatus has more stages of inverter circuits, the source-drain voltage differences of the transistors of the pull-up circuits and the pull-down circuits in which the paths are turned off in the inverter circuits of the respective stages are relatively close or equal. That is, the voltage differences of the transistors may be more evenly distributed to avoid a part of the transistors enduring the larger voltage differences. In this way, the driving apparatus can be prevented from being incapable of normally driving the later stage circuit due to the breakdown in the transistors, the leakage currents of the transistors can be reduced, and the life of the transistors can be extended.

Although the invention has been described with reference to the above embodiments, it will be apparent to one of ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims and not by the above detailed descriptions.