Image sensor system and amplifying/digitizing circuit therof for promoting performance while saving on power consumption and reducing the circuit area

An amplifying/digitizing circuit with a signal amplifying capability and a comparator capability is provided. The amplifying/digitizing circuit includes an amplifier having an input end and an output end, and a control circuit. The control circuit is coupled to the input end and the output end of the amplifier. When the amplifying/digitizing circuit is operated under an amplifying mode, the control circuit has a first configuration to receive a first input signal and makes the amplifier generate an output voltage at the output end according to the first input signal and an amplification factor. When the amplifying/digitizing circuit is operated under an ADC mode, the control circuit has a second configuration to receive a second input signal and makes the amplifier generate a comparison result according to the second input signal and the output voltage.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an image sensor, and more particularly, to an image sensor and an amplifying/digitizing circuit thereof.

2. Description of the Prior Art

In an image system, an analog-to-digital converter (ADC) is indispensable for converting a sensed signal of an analog format into a digital format, and is broadly used in various applications, such as a CMOS Image Sensor (CIS) system. The ADCs can be divided into flash ADCs, ramp ADCs, pipelined ADCs, and successive approximation ADCs, etc. according to corresponding circuit structures.

Please refer toFIG. 1.FIG. 1is a conventional image sensor system100, which includes a sensor array110, a column amplifier120, an ADC130, and an image processor140. The signals from the sensor array110are first amplified by the column amplifiers120and then converted into digital form by the ADC130. Conventionally, the image sensor system100may use a ramp ADC as the ADC130.

Due to the existing ADC structures lack the amplification functionality, the conventional image sensor system100has to adopt an amplification circuit as the column amplifier120for improving the SNR and promoting the image quality of the image sensor system100.

In order to minimize the chip area and enhance the performance, manufacturers are dedicated to design new circuits to achieve the goals.

SUMMARY OF THE INVENTION

It is therefore one of the objectives of the present invention to provide an amplifying/digitizing circuit by using a single operational amplifier, to promote performance while saving on power consumption and reducing the circuit area, and provide an image sensor system thereof.

According to an aspect of the present invention, an amplifying/digitizing circuit is provided. The amplifying/digitizing circuit includes an amplifier having an input end and an output end, and a control circuit. The control circuit is coupled to the input end and the output end of the amplifier. When the amplifying/digitizing circuit is operated under an amplifying mode, the control circuit has a first configuration to receive a first input signal and makes the amplifier generate an output voltage at the output end according to the first input signal and an amplification factor. When the amplifying/digitizing circuit is operated under an ADC mode, the control circuit has a second configuration to receive a second input signal and makes the amplifier generate a comparison result according to the second input signal and the output voltage.

According to another aspect of the present invention, an amplifying/digitizing circuit is provided. The amplifying/digitizing circuit includes an amplifier having an input end and an output end, a first capacitor, a second capacitor, a first switch, a second switch, a third switch, and a fourth switch. The first capacitor has a first node coupled to the first input signal, and a second node coupled to the input end of the amplifier. The second capacitor has a first node coupled to the input end of the amplifier, and a second node. The first switch is coupled between the second node of the first capacitor and the input end of the amplifier; the second switch is coupled between the input end of the amplifier and the output end of the amplifier; the third switch is coupled between the output end of the amplifier and the second node of the second capacitor; and the fourth switch is coupled between the second node of the second capacitor and the second input signal.

According to yet another aspect of the present invention, an image sensor system is provided. The image sensor system includes a sensor array and an amplifying/digitalizing circuit, wherein the sensor array senses photons to output an electrical signal and the amplifying/digitalizing circuit amplifies and digitalizes the electronic signal to output a digital signal. The amplifying/digitalizing circuit includes an amplifier, a first capacitor, a second capacitor, a first switch, and a second switch. Wherein the amplifier has an input end and an output end; the first capacitor has a first node and a second node which is connected to the input end of the amplifier; the first switch selectively connects the electrical signal from the sensor to the input end of the amplifier; and the second switch connects the second node of the second capacitor selectively to the output end of the amplifier or a ramp voltage.

DETAILED DESCRIPTION

One embodiment of the present invention provides an amplifying/digitizing circuit which uses a single operational amplifier to achieve an amplification function and an analog-to-digital conversion function, and an image sensor system adopts the amplifying/digitizing circuit therein. By controlling the on/off states of the switches implemented in the proposed amplifying/digitizing circuit of the present invention, the exemplary amplifying/digitizing circuit can execute the amplification function and the analog-to-digital function respectively under an amplifying mode and an ADC mode. By applying the amplifying/digitizing circuit disclosed here, low power consumption and compact chip area can be realized.

Please refer toFIG. 2.FIG. 2is a block diagram illustrating an exemplary embodiment of an image sensor system200of the present invention. InFIG. 2, the image sensor system200includes a sensor array210for sensing photons and generating an electrical signal accordingly; an amplifying/digitalizing circuit220for amplifying the magnitude of the electrical signal and then digitalizing the amplified electrical signal to generate a digital signal; and an image processor230, for processing the digital signal to generate output data. Since the operations of sensor arrays and image processors are well known by people skilled in this art, further descriptions of the sensor array210and image processor230are omitted here for the sake of brevity. In one example, the amplifying/digitalizing circuit220uses an amplifier for the amplifying function, and uses the amplifier and a counter as a ramp ADC structure to execute the analog-to-digital conversion function.

Please refer toFIG. 3in conjunction withFIG. 2.FIG. 3is a block diagram illustrating an exemplary embodiment of an amplifying/digitizing circuit (e.g., the amplifying/digitalizing circuit220inFIG. 2) of the present invention. InFIG. 3, the exemplary amplifying/digitizing circuit300includes an amplifier310, a control circuit320and a counter330. The amplifying/digitizing circuit300can be operated under a reset mode, an amplifying mode or an ADC mode, controlled by the control circuit320. In this way, the amplifier310may be for example an operational amplifier to amplify the sensed signal generated from the sensor array210under the amplifying mode, and then execute the comparing operation under the ADC mode.

In this exemplary embodiment, the control circuit320includes, but is not limited to, a first capacitor C1, a second capacitor C2, a first switch SW1, a second switch SW2, a third switch SW3, and a fourth switch SW4. The first capacitor C1has a first node321and a second node322where the first node321is coupled to a first input signal Sin, and the second node322is coupled to an input end312of the amplifier310via the first switch SW1. The second capacitor C2has a first node331and a second node332, where the first node331of the second capacitor C2is coupled to the input end312of the amplifier310. The first switch SW1is coupled between the second node322of the first capacitor C1and the input end312of the amplifier310. The second switch SW2is coupled between the input end312and the output end314of the amplifier310. The third switch SW3is coupled between the output end314of the amplifier310and the second node332of the second capacitor C2. The fourth switch SW4is coupled between the second node332of the second capacitor C2and a second input signal Vramp.

Each time before the amplifying/digitizing circuit300starts processing the first input signal Sin, the amplifying/digitizing circuit300enters the reset mode for resetting the amplifier310and/or the first capacitor C1and the second capacitor C2. As is well known to people skilled in this art, the sensed signals at one row are processed at a time, and here the amplifying/digitizing circuit300can serve as part of a ramp ADC. For each signal processing cycle, the exemplary amplifying/digitizing circuit300is configured to operate under three different modes in the following order: reset mode, amplifying mode, and ADC mode. However, with appropriate adjustments, the amplifying/digitizing circuit300can be applied in other ADC structures to dynamically provide the amplification capability as well as the ADC capability as needed; these alternative designs obey and fall within the scope of the present invention.

In detail, the amplifying/digitizing circuit300enters the reset mode when it is powered on and/or before starting processing of a sensed signal of a row. Next, amplifying/digitizing circuit300enters the amplifying mode to amplify the first input signal Sinreceived from the first node321of the first capacitor C1according to an amplification factor to promote the SNR of the sensed signal. Then, the amplifying/digitizing circuit300enters the ADC mode to digitize the amplified sensed signal.

Under the ADC mode, the amplifier310of the amplifying/digitizing circuit300serves as a comparator, and receives a ramp voltage (i.e., the second input signal Vramp) via the fourth switch SW4. The detailed descriptions are disclosed in the following paragraphs.

Please refer toFIG. 4in conjunction withFIG. 2˜3.FIG. 4is a diagram illustrating an exemplary embodiment of a configuration of the amplifying/digitizing circuit300under the reset mode. In the reset mode, the control circuit310has a first configuration that the first switch SW1, the second switch SW2, and the fourth switch SW4are switched on and the third switch SW3is switched off so as to reset the amplifier310and the capacitors C1and C2. For illustrative purposes, in the following descriptions, the amplifier310is a single-ended amplifier. However, the aforementioned exemplary design is for illustrative purposes only. Actually, under different design requirements, the amplifier310can be implemented using a differential amplifier. Furthermore, provided that substantially the same result is obtained, the control circuit310may have other circuit structures obeying the spirit of the present invention to provide different configurations corresponding to the reset mode, amplifying mode and the ADC mode, respectively. These alternative designs still fall within the scope of the present invention.

After the reset operation is completed, the amplifying/digitizing circuit300enters the amplifying mode for amplifying a sensed signal. Please refer toFIG. 5in conjunction withFIG. 2˜4.FIG. 5is a diagram illustrating an exemplary embodiment of the configuration of the amplifying/digitizing circuit300under the amplifying mode. Under the amplifying mode, the control circuit320has a second configuration that the first switch SW1and the third switch SW3are switched on while the second switch SW2and the fourth switch SW4are switched off, such that the sensed signal (i.e., the first input signal Sin) is fed into the amplifying/digitizing circuit300via the first capacitor C1. In this way, the generated signal at the output end314of the amplifier310has a voltage level equal to

C⁢⁢1C⁢⁢2⁢Sin,
where ‘C1’ represents the capacitive value of the first capacitor C1, ‘C2’ represents the capacitive value of the second capacitor C2, and ‘Sin’ represents the voltage level of the first input signal Sin. That is, the SNR of the processed signal of the CIS system is greatly improved by selecting the capacitive values of the first capacitor C1and the second capacitor C2.

Please refer toFIG. 6in conjunction withFIG. 2-5.FIG. 6is a diagram illustrating an exemplary embodiment of the configuration of the amplifying/digitizing circuit300under the ADC mode. In one implementation, the amplifying/digitizing circuit300is integrated in a ramp ADC which includes a ramp voltage source (i.e., the second input signal Vramp) coupled to the fourth switch SW4. Under the ADC mode, the ramp voltage is a time-variant signal, and when the time-variant ramp signal Vrampreaches a voltage level

C⁢⁢1C⁢⁢2⁢Sin
derived under the former amplifying mode, the amplifier310will make the comparison result Southave a transition from a first logic level (e.g., ‘1’) to a second logic level (e.g., ‘0’).

For an example of this, please refer toFIG. 7in conjunction withFIGS. 2˜6.FIG. 7is a timing diagram illustrating operations of a ramp ADC which employs the exemplary amplifying/digitizing circuit of the present invention. As shown inFIG. 7, the ramp voltage Vrampincreases according to operations of a counter. When the ramp voltage Vrampreaches the voltage level

C⁢⁢1C⁢⁢2⁢Sin
generated in the amplifying mode, the amplifier310acting as a comparator will have a transition from the first logic level (e.g., ‘1’) to the second logic level (e.g., ‘0’) due to characteristics of the circuit architecture proposed in the embodiment of the present invention. Please note that the magnitude of the first logic level and the second logic level is not meant to be a limitation of the present invention. When the comparison result at the output end314of the amplifier310changes, the counter330outputs the ADC output code. Since the operations and details of the ramp ADC are well known to people skilled in this art, further descriptions are omitted here for the sake of brevity.

Please refer toFIG. 8in conjunction withFIGS. 2˜7.FIG. 8is a timing diagram illustrating operations of the amplifying/digitizing circuit300under the reset mode, the amplifying mode, and the ADC mode. In the reset mode, the first switch SW1, the second SW2and the fourth SW4are switched on, where the second switch SW2is turned off slightly early than the third switch SW3does. In the amplifying mode, the fourth switch SW4is turned off and the third switch SW3is turned on, while the first switch SW1remains on and the second switch SW2is turned off. Moreover, under the amplifying mode, the output signal at the output end314of the operational amplifier310is

C⁢⁢1C⁢⁢2⁢Sin
when the sensed signal received at the first node321is Sin. Under the ADC mode, the ramp voltage Vrampincreases when the counter keeps counting, until the ramp voltage Vrampreaches the voltage level of the amplified signal

C⁢⁢1C⁢⁢2⁢Sin
derived under the amplifying mode. In this exemplary embodiment, the output end314of the amplifier310outputs logic “1” when the ramp voltage Vrampis lower than the voltage level of the amplified signal

C⁢⁢1C⁢⁢2⁢Sin,
and the comparison result changes to logic level “0” when the ramp voltage Vrampreaches

In conclusion, the present invention provides an amplifying/digitizing circuit which can be switched under at least an amplifying mode and an ADC mode, to amplify a received signal before a comparison operation is performed, and an image sensor system adopts the amplifying/digitizing circuit therein. In one implementation, the disclosed amplifying/digitizing circuit is applied to a ramp ADC; however, a person skilled in the art would readily appreciate that the disclosed amplifying/digitizing circuit can also be applied to other ADC architectures when there is a need to perform the amplification and comparison through use of a single operational amplifier. Furthermore, no matter whether the aforementioned amplification and/or comparison functionalities are realized, any application employing the exemplary the proposed amplifying/digitizing circuit still falls within the scope of the present invention. The image sensor system adopts an amplifying/digitizing circuit with both an amplifying function and a digitalizing function via a signal amplifier obeys and falls within the scope of the present invention.