Method, apparatus, and system for improved read operation in memory

Various embodiments include methods, apparatus, and systems for reading an adjacent cell of a memory array in an electronic device to determine a threshold voltage value of the adjacent cell, the adjacent cell being adjacent a target cell, and reading the target cell of the memory array using a wordline voltage value based on the threshold voltage value of the adjacent cell. Additional apparatus, systems, and methods are described.

FIELD

Embodiments described herein relate to memory devices, including read operations in flash memory devices.

BACKGROUND

Non-volatile memory devices, such as flash memory devices, are used to store data and other kinds of information. Many computers and electronic devices, for example, digital audio players, digital cameras, digital recorders, and cellular phones, have flash memory devices. Flash memory devices may also be used as portable storage devices, such as portable Universal Serial Bus (USB) flash drives or “thumb” drives. Flash memory devices may not need power to maintain the information stored in the device.

A flash memory device stores information in numerous memory cells, which are usually formed in a semiconductor chip. Each of the cells often has a metal-oxide semiconductor (MOS) transistor with two different transistor gates: a control gate and a so-called “floating” gate or FG. The control gate may be used to turn the transistor on and off to control access to the cell. The floating gate may be the place where either one bit or multiple bits of information is stored in each cell.

The value of the information stored in the floating gate may be determined by the amount of electrons or charge in the floating gate. Different amount of electrons in the floating gate may correspond to different values of information. The amount of electrons in the floating gate may be varied by either adding electrons to or extracting electrons from the floating gate.

A flash memory device usually has a programming operation (which is also sometimes referred to as a write operation) to add electrons to the floating gate, and an erase operation to extract electrons from the floating gate. Information in the cells may be read in a read operation. Each cell has a threshold voltage value dependent on the amount of electrons in the floating gate. A read operation determines the threshold voltage value of the cell being read to provide the value of the information stored in the cell.

In some cases, the physical distance among adjacent floating gates of adjacent cells, or the number of electrons in adjacent floating gates, or both, may create floating gate to floating gate (FG-FG) interference among adjacent cells. The FG-FG interference may cause the threshold voltage value of a cell to shift, leading to reduced reliability of information stored in the cell when the information is read.

DETAILED DESCRIPTION

FIG. 1shows a block diagram of an apparatus including a memory device100according to an embodiment of the invention. Memory device100may include a memory array102with memory cells104arranged in rows and columns. Row decoder106and column decoder108may respond to an address register112to access cells104based on row address and column address signals on terminals110. A data input/output circuit114may transfer data between cells104and terminals110. Terminals110and111may be external terminals of memory device100(e.g., terminals exposed outside a chip or semiconductor package that contain memory device100). A control circuit116may control operations of memory device100based on signals present on terminals110and111. The operations may include a programming operation to write data from terminals110to cells104(e.g., transfer data from terminals110to cells104), a read operation to read data from cells104to terminals110(e.g., transfer data from cells104to terminals110), and an erase operation to erase data (e.g., clear data) from all cells104or from a portion of cells104.

Memory device100may receive voltages Vcc and Vss. Vcc may be the supply voltage for memory device100, and Vss may be ground. Memory device100may also include a voltage generator140. Voltage generator140and control circuit116may act separately or together to provide different voltages to memory array102or to cause memory array102to have different voltages during various operations of memory device100.

Memory device100may include a counter117to count the number of signal cycles of a count signal COUNT during a read operation of memory device100. Based on a count by counter117, an appropriate voltage value may be used to read cells104during the read operation. The function of counter117is described in more detail with reference toFIG. 11.

InFIG. 1, the COUNT signal may include a periodic signal (e.g., a clock signal) that may be internally generated by memory device100. In some embodiments, the COUNT signal may be generated based on a clock signal provided to memory device100by an external source. For example, the COUNT signal may include a clock signal CLK or may be generated based on the CLK signal provided to memory device100at terminals111by another source external from memory device100.

Memory device100may include a storage area118, which may include storage components such as flash memory cells components, read only memory (ROM) components, registers, or a combination thereof. Storage area118may include a hardware portion, a firmware portion, or both, of memory device100. Storage area118may include codes (e.g., software programming instructions) to determine a shift threshold voltage value of one or more target cells of memory device100. Storage area118may also store the shift threshold voltage values of the target cell of memory device100. The shift threshold voltage value of a target cell is described in more detail below with reference toFIG. 2throughFIG. 13.

A “target cell” as described herein refers to a cell that is selected to be read or intended to be read in response to a command such as a read command. The command to read the target cell may be received at terminals of the memory device, such as terminals110or111of memory device100ofFIG. 1. The read command may be sent to the memory device by another device, e.g., by a processor or by a memory controller that is separated from the memory device. The information read from the target cell may be transferred to terminals of the memory device, e.g., terminal110ofFIG. 1, for further use by another device such as by a processor or a memory controller.

In response to the command to read a target cell, memory device100may generate an internal read command (in addition to the original read command) to read an adjacent cell before reading the target cell. Memory device100may obtain feedback information when reading the adjacent cell. Then, memory device100may read the target cell based on the feedback information. Thus, memory device100may operate to read the adjacent cell to obtain feedback information before reading the target cell, without receiving a specific external command (e.g., from a processor or a memory controller) to read the adjacent cell.

Memory device100may include a flash memory device. In some embodiments, memory device100may include a multi-level cell (MLC) flash memory device. In some embodiments, memory device100may include a NAND flash memory device where cells104may include flash cells arranged in a NAND flash memory arrangement. One skilled in the art will readily recognize that memory device100may include other parts, which are omitted fromFIG. 1to focus on the various embodiments described herein. In some embodiments, memory device100may include embodiments ofFIG. 2 through 13described below.

FIG. 2shows a partial schematic diagram of a memory device200according to an embodiment of the invention. Memory device200may correspond to memory device100ofFIG. 1, perhaps forming a portion of the array102shown therein. InFIG. 2, memory device200may include cells210,211,212,213,220,221,222,223,230,231,232, and233.

In the description ofFIG. 2, the term “the cells” (plural), when used without accompanying reference numbers, refers to some or all of cells of a memory device such as cells210,211,212,213,220,221,222,223,230,231,232, and233. Further, the term “the cell” (singular), when used without an accompanying reference number, refers to one of the cells of a memory device such as one of cells210,211,212,213,220,221,222,223,230,231,232, and233.

As shown inFIG. 2, the cells are arranged in rows240,241,242, and243, and columns244,245, and246. The cells in the same column may be connected in a series (sometimes called a string) of cells, such as strings250,251, and252.FIG. 2shows an example where each string250,251, and252may include four cells. In some embodiments, the number of cells in each of strings250,251, and252may vary.

Each of the cells ofFIG. 2may include a floating gate208and a control gate209. Control gates209of cells in the same row (e.g., row220) may be coupled to one of lines (e.g., wordlines)260,261,262, and263. Memory device200may use lines260,261,262, and263to access the cells. Wordline signals (e.g., voltages) WL0, WL1, WL2, and WL3on lines260,261,262, and263may be used to activate the cells to read information in the cells. In an operation, such as read operation, each of wordline signals WL0, WL1, WL2, and WL3may have different signal levels representing different voltage values on lines260,261,262, and263. In this description, the term wordline includes a line that a device, such as memory device100ofFIG. 1or memory device200ofFIG. 2, may use the line to access a memory cell of the device. The term wordline voltage includes a voltage applied to a line that is used to access a memory cell associated with that line.

Each floating gate208ofFIG. 2may store information in the form of an amount of electrons or charge. Different amount of electrons in the floating gate of each of the cells inFIG. 2may cause each cell to have a different threshold voltage value. Different threshold voltage values of the cell may represent different values of the information stored in the cell. The threshold voltage value in each of the cells ofFIG. 2may represent a logical value including two or more data bits. For example, in an MLC memory device where each of the cells ofFIG. 2may store four data bits (4 bits per cell), the threshold voltage value in each cell may represent a logical value of one of 16 possible logical combinations of four binary bits.

As mentioned above, FG-FG interference may cause the threshold voltage value (Vt) of a cell to shift (e.g., change in value), leading to a reduced reliability of reading information stored in the cell. The value of the shift in the threshold voltage value of a cell (e.g., a target cell, as mentioned above), due to FG-to-FG interference, is referred to as a shift threshold voltage value or VSHIFT.

FIG. 3shows an example of threshold voltage value distribution of memory device200ofFIG. 2including an example of a VSHIFT.FIG. 3shows an example of only four different possible threshold voltage values Vt1, Vt2, Vt3, and Vt4. In some embodiments, the number of threshold voltage values may vary. For example, in three bits per cell, the number of threshold voltage values may be eight. In another example, in four bits per cell, the number of threshold voltage values may be 16. Each cell ofFIG. 2may have one of Vt1, Vt2, Vt3, and Vt4(FIG. 3), depending on the value of the information stored in the cell. As shown inFIG. 3, each of Vt1, Vt2, Vt3, and Vt4may be within a voltage range (e.g., Vt1may be between voltage VL and voltage VH).

FIG. 3shows an example of some of the cells (which may include cell220, a target cell in this example) ofFIG. 2having a threshold voltage of Vt2, corresponding to some stored value of information. Vt2may correspond to the original threshold voltage of cell220. However, due to FG-to-FG interference, Vt2may be shifted by VSHIFTand become Vt2b. The value of VSHIFTmay be determined based on the threshold voltage values of the cells that are adjacent cell220, such as cells210,230,211,221, and231ofFIG. 2.

InFIG. 2, in a read operation, when a memory device200receives a command to read a target cell, memory device200may read one or more cells adjacent the target cell to obtain feedback information, then memory device200may read the target cell based on the feedback information. The feedback information may include information related to VSHIFTof the target cell. For example, when memory device200receives a command to read a target cell (e.g., cell220), memory device200may read one or more of the adjacent cells211,221,231,210, and230to obtain VSHIFTof cell220. Then, memory device200reads the target cell, which is cell220in this example, based on VSHIFT.

As show inFIG. 3, a threshold voltage value of a target cell may shift (e.g., Vt2ofFIG. 2may shift by VSHIFT). Thus, if VSHIFTof the target cell is taken into account when the target cell is read, the effect of the FG-FG may be reduced such that the accuracy or reliability of the information stored in the target cell may be improved. A way to determine VSHIFTof a cell is described in connection withFIG. 4throughFIG. 6.

FIG. 4shows a partial schematic diagram of a memory device400depicting a target cell and adjacent cells according an embodiment of the invention. In some embodiments, memory device400may correspond to memory device100ofFIG. 1. InFIG. 4, memory device400may include row440having cells410,420, and430with associated line460and wordline signal WL0, and row441having cells411,421, and431with associated line461and wordline signal WL1. As shown inFIG. 4, row440is adjacent row441such that row440is located immediately next to row441.

For purposes of describing a read operation of memory device400, cell420is assumed to be a target cell, and cells410,430,411,421, and431may be called adjacent cells410,430,411,421, and431(which are cells adjacent target cell420). Memory device400may use line460to access cells410,420and430and line461to access cells411,421, and431.

Adjacent cells410and430may be referred to as wordline adjacent cells, such that adjacent cell410is located immediately next to a first side of target cell420in row440, and adjacent cell430is located immediately next to a second side of target cell420in row440, each in a wordline direction, along wordline460. Adjacent cell421may be referred to as bit line adjacent cell, such that adjacent cell421is located immediately next to target cell420in a bit line direction450. Adjacent cells411and431may be referred to as diagonally adjacent cells, such that adjacent cell411is located diagonally from target cell420in a diagonal direction471, and adjacent cell431is located diagonally from target cell420in a diagonal direction472.

InFIG. 4, due to the FG-FG interference, target cell420may have a VSHIFTcaused by each of adjacent cells410,430,411,421, and431.

FIG. 5is a chart showing calculation of VSHIFTof target cell420. As shown inFIG. 5, VSHIFTof target cell420is a total of VSHIFT1+VSHIFT2+VSHIFT3+VSHIFT4+VSHIFT5. VSHIFT1is the shift threshold voltage value of cell420caused by cell410. VSHIFT2is the shift threshold voltage value of target cell420caused by adjacent cell430. VSHIFT3is the shift threshold voltage value of target cell420caused by adjacent cell411. VSHIFT4is the shift threshold voltage value of target cell420caused by adjacent cell421. VSHIFT5is the shift threshold voltage value of target cell420caused by adjacent cell431. Each of VSHIFT1+VSHIFT2+VSHIFT3+VSHIFT4+VSHIFT5may be determined from the charts shown inFIG. 6.

FIG. 6depicts a number of charts601,602,603,604,605, and606showing examples of different threshold voltage values and different shift threshold voltage values according an embodiment of the invention. Each of these charts shows a corresponding threshold voltage value of an adjacent cell and a portion of VSHIFTof the target cell420caused by each adjacent cell. In chart601, VSHIFT1may have different voltage values aV, bV, cV, and dV, where V corresponds to a voltage value (e.g., 100 millivolts or some other value), and each of a, b, c, and d corresponds to a real number. The values aV, bV, cV, and dV in chart601mean that the threshold voltage value of adjacent cell420may be shifted by a voltage amount of aV, bV, cV, or dV, depending on the threshold voltage value of adjacent cell410(Vt410). V0, V1, V2, and VX in chart601correspond to different values of Vt410. Thus, as shown in chart601, when Vt410has a value of V0, the threshold voltage value of target cell420(Vt420) may be shifted by a voltage amount of aV volts. In another example, when Vt410has a value of V1, Vt420may be shifted by a voltage amount of bV volts. Thus, from chart601, VSHIFT1may be determined based on Vt410. As described above, the threshold voltage value of an adjacent cell, such as Vt410, may be determined by reading cell410in a read operation.

In chart601ofFIG. 6, each of aV, bV, cV, and dV of VSHIFT1may be determined (e.g., measured) by the following technique. At a beginning of a measurement, Vt410(Vt of cell410) and Vt420(Vt of cell420) may be set to an initial value (e.g., one volt) by an initial programming of cells410and420. Then, the initial value of Vt410may be changed to a different value (e.g., by a second programming of cell410with a different threshold voltage value). For example, after Vt410and Vt420are set to an initial value of one volt, Vt410may be increased from one volt to 1.5 volts while Vt420is not increased (e.g., not programming target cell420in the second programming operation). After Vt410is increased to 1.5 volts, Vt420may be measured (e.g., by reading target cell420after cell410is programmed). The shift in Vt420(caused by the change in Vt410from one to 1.5 volts) may be determined by the difference in Vt420before and after Vt410is changed. The result of the measurement may be recorded in a chart such as chart601. For example, if Vt420shifts from one volt to 1.2 volts when Vt410is changed from one to 1.5 volts, then VSHIFT1is 200 millivolts (1.2 volts minus one volt) corresponding to Vt410of 1.5 volts. Thus, in this example, in chart601, V0would be replaced with 1.5 volts and aV would be replaced with 200 millivolts. Following this technique, other values for VSHIFT1in chart601may be recorded. Shift threshold voltage values may be positive, zero or negative.

Chart606inFIG. 6shows example threshold voltage values of an adjacent cell (Vtn) and a corresponding VSHIFTnof a target cell caused by that adjacent cell. For example, when the adjacent cell in chart606has threshold voltage values of 1, 1.5, 2, or 5 volts, a target cell may be shifted by an amount of 100, 200, 300, or 800 millivolts, respectively. Chart606may represent example values of one of charts601,602,603,604, and605.

In each of charts602,603,604, and605, V0, V1, V2, and VX represent the threshold voltage values of the adjacent cell in that chart.

In chart602, eV, fV, gV, hV present the shift threshold voltage values of target cell420based on threshold voltage values V0, V1, V2, and VX, respectively, of adjacent cell430.

In chart603, iV, jV, kV, lV present the shift threshold voltage values of target cell420based on threshold voltage values V0, V1, V2, and VX, respectively, of adjacent cell411.

In chart604, mV, nV, oV, pV present the shift threshold voltage values of target cell420based on threshold voltage values V0, V1, V2, and VX, respectively, of adjacent cell421.

In chart605, qV, rV, sV, tV present the shift threshold voltage values of target cell420based on threshold voltage values V0, V1, V2, and VX, respectively, of adjacent cell431.

The shift threshold voltage values (aV, bV, and cV through tV) among charts601,602,603,604, and605may have different values. For example, in chart601, the shift threshold voltage value aV in chart601may be at one value (e.g., 100 millivolts) when V0in chart601is 1.5 volt, but in chart602, the shift threshold voltage value eV may be a different value (e.g., 80 millivolts) when V0in chart601is 1.5 volt.

Information in each of charts601,602,603,604, and605may be stored using different techniques, such as by software, firmware, hardware, or a combination thereof. For example, in chart601, each of V0, V1, V2, VX and aV, bV, cV, and dV may be entries of a table with actual number values (i.e., voltage values). The entries may be accessed during the read operation of adjacent cell410to find the values of VSHIFTcorresponding to a particular threshold voltage value of adjacent cell410. With software implementation, programming instructions may be used to access entries in the table in the software to determine the shift threshold voltage value of the target cell based on the threshold voltage of the adjacent cell.

In another example, with firmware or hardware implementation, the values of V0, V1, V2, VX and aV, bV, cV, and dV of chart601may be stored in the storage area118of memory device100ofFIG. 1. Memory device400ofFIG. 4may access the storage area to locate the entries to determine the shift threshold voltage value of the target cell based on the threshold voltage of the adjacent cells. The storage area to store the entries, such as V0, V1, V2, VX and aV, bV, cV, and dV of chart601, may be included in storage area118of memory device100ofFIG. 1.

In some embodiments, memory device400may record the relationship (e.g., linear relationship) between the threshold voltage value of the adjacent cell and the shift threshold voltage value of the target cell, then memory device400may calculate (instead of looking up a chart or table for stored values) the value of each of VSHIFT1, VSHIFT2, VSHIFT3, VSHIFT4, and VSHIFT5based on the threshold voltage value of each of cells410,430,411,421, and431.

FIG. 7is a flow diagram showing a method700for a read operation of memory device400according to an embodiment of the invention. The following description refers toFIG. 4andFIG. 7.

Activity710of method700inFIG. 7may include receiving a command to read target cell420of memory device400ofFIG. 4. The command may be received by memory device400from another device (e.g., a processor or a memory controller).

Activity720ofFIG. 7, in response to the command received in activity710, may include reading at least one of adjacent cells410,430,411,421, and431, before reading the target cell, to obtain feedback information. For example, memory device400may be configured to read only one of adjacent cells410,430,411,421, and431when a command to read target cell420is received. In another example, memory device400may be configured to read two, three, four, or all five of adjacent cells410,430,411,421, and431when a command to read target cell420is received. If the target cell is included in the center of an array of other cells, even more adjacent cells (e.g., eight) may be read. In any case, a control circuit of memory device400, similar to or identical to control circuit116of memory device100, may be set to read either one or more than one adjacent cells in response to a command to read a target cell.

The feedback information obtained from reading an adjacent cell may include at least one of VSHIFT1, VSHIFT2, VSHIFT3, VSHIFT4, and VSHIFT5, as shown inFIG. 6. For example, if only one adjacent cell (e.g., cell421) is read, then the feedback information includes only VSHIFT4(chart604). In the case where one adjacent cell421is read, the value of VSHIFT4is based on the threshold voltage of adjacent cell421. For example, if the threshold voltage of adjacent cell421is V1, then VSHIFT4is nV. Thus, the feedback information, where one adjacent cell421is read, has a value corresponding to nV when the threshold voltage of adjacent cell421is V1. In this example, the feedback information (e.g., nV) may be determined by locating an entry in a chart (e.g., chart604) or a table in memory device400.

In another example, if three adjacent cells (e.g., cells411,421, and431) are read, then the feedback information is a total of three of VSHIFT1, VSHIFT2, VSHIFT3, VSHIFT4, and VSHIFT5(e.g., total VSHIFT3, VSHIFT4, and VSHIFT5).

Each of VSHIFT1, VSHIFT2, VSHIFT3, VSHIFT4, and VSHIFT5may be called a feedback voltage value of the feedback information. Thus, depending on the number of adjacent cells read, the feedback voltage value of the feedback information may be either one of VSHIFT1, VSHIFT2, VSHIFT3, VSHIFT4, and VSHIFT5or a total of two or more of VSHIFT1, VSHIFT2, VSHIFT3, VSHIFT4, and VSHIFT5.

In activity720, after receiving the command to read the target cell, memory device400may issue an internal read command to read one or more adjacent cells before reading the target cell. Since memory device400may issue an internal read command to read one or more adjacent cells, memory device400may read adjacent cells without receiving (e.g., from a processor or a memory controller) a specific external command to read the adjacent cell. After the feedback information is obtained in activity720, method700may continue with activity730.

Activity730may include reading target cell420based on the feedback information. In activity720described above, to read an adjacent cell (e.g., adjacent cell421), memory device400(FIG. 4) may apply to line461wordline signal WL1with an initial wordline voltage value (V0ADJ). In activity730, to read target cell420, memory device400may apply to line460wordline signal WL0with an initial wordline voltage value (V0TAR) different from V0ADJ. For example, V0TARmay be approximately equal to the sum of V0ADJand VSHIFT(V0TAR=V0ADJ+VSHIFT). In this description, when two quantities or two sides of an equation are said to be approximately equal (or are said to be equal), it means that a difference of 50 millivolts or less may exist between the two quantities or between two sides of the equation.

FIG. 8is a chart showing a relationship between an initial wordline voltage value used when reading an adjacent cell and an initial wordline voltage value used when reading a target cell according an embodiment of the invention. As shown inFIG. 8, V0ADJrepresents an initial wordline voltage value applied to a wordline associated with an adjacent cell when the adjacent cell is read. For example, when adjacent cell411,421, or431(line461,FIG. 4) is read, the initial wordline voltage value V0ADJ(FIG. 8) represents the initial wordline voltage value applied to line461. In another example, when adjacent cell410or430(line460) is read, the initial wordline voltage value V0ADJ(FIG. 8) represents the initial wordline voltage value applied to line460.

A different initial wordline voltage value may be applied to a wordline associated with the target cell when the target is read. For example, inFIG. 8, V0TARrepresents an initial wordline voltage value that may be applied to line460(FIG. 4) when target cell420is read.

As shown inFIG. 8, the initial wordline voltage value V0TARis equal to the sum of the initial wordline voltage value V0ADJand VSHIFT. As described inFIG. 7, VSHIFT(e.g., the feedback voltage value of the feedback information) may be either one or a total of two or more of VSHIFT1, VSHIFT2, VSHIFT3, VSHIFT4, and VSHIFT5.

FIG. 9is a diagram showing an initial wordline voltage value and other voltage values of a wordline associated with an adjacent cell in a read operation according an embodiment of the invention. WL0/WL1in the vertical axis may represent wordline signals (e.g., voltages) WL0and WL1ofFIG. 4. InFIG. 9, V0ADJ, having voltage value902, may represent an initial wordline voltage applied to a line (e.g., wordline) associated with an adjacent cell.

For example, between times T0and T1(FIG. 9), initial wordline voltage V0ADJmay be applied to line460(FIG. 4) when adjacent cell410or430ofFIG. 4is read to determine the threshold voltage value (Vt410) of adjacent cell410or the threshold voltage value (Vt430) of adjacent cell430. Thus, between times T0and T1inFIG. 9, wordline signal WL0may have initial wordline voltage V0ADJ. In some embodiments, if the threshold voltage value (Vt410or Vt430) of the adjacent cell being read is unsuccessfully determined between times T0and T1, then the wordline voltage value of wordline signal WL0may be increased to an increased voltage value (e.g., voltage value903) or decreased to a decreased voltage value (e.g., voltage value901).

In another example, between times T0and T1, initial wordline voltage V0ADJmay be applied to line461when adjacent cell411,412, or431is read to determine the threshold voltage value (e.g., Vt411, Vt421, or Vt431) of the adjacent cell. Thus, between times T0and T1, wordline signal WL1may have initial wordline voltage V0ADJ. If the threshold voltage value (e.g., Vt411, Vt421, or Vt431) of the adjacent cell being read is unsuccessfully determined between times T0and T1, then the wordline voltage value of wordline signal WL1may be increased to an increased voltage value (e.g., voltage value903) or decreased to a decreased voltage value (e.g., voltage value901).

Between times T1and T2, wordline voltage value of wordline signal WL0(or WL1) applied to line460(or line461) may be between voltage values901and902to read the adjacent cell to determine its threshold voltage value. For example, in an MLC memory device where the adjacent cell has one of a number of X possible threshold voltage levels, wordline voltage value of wordline signal WL0, which is applied to line460when reading adjacent cell410, may be changed (increased or decreased) up to X times to determine threshold voltage value of adjacent cell410. X, as described herein, corresponds to an integer.

FIG. 10is a diagram showing an initial wordline voltage value and other voltage values of a wordline associated with a target cell in a read operation according an embodiment of the invention. WL0in the vertical axis may represent wordline signal or voltage WL0ofFIG. 4. V0TAR, having voltage value1002, may represent an initial wordline voltage applied to a wordline associated with a target cell. For example, between times Ta and Tb ofFIG. 10, initial wordline voltage V0TARmay be applied to line460ofFIG. 4when target cell420is read to determine the threshold voltage value (Vt420) of target cell420. Thus, between times Ta and Tb, wordline signal WL0may have initial wordline voltage V0TAR.

As shown inFIG. 10, initial wordline voltage V0TARis greater than V0ADJby an amount of VSHIFT. Thus, the initial wordline voltage V0TARis equal to the sum initial wordline voltage V0ADJand VSHIFT. The time interval between Ta and Tb may occur after the time interval between T1and T2(FIG. 9).

InFIG. 10, between times Ta and Tb, if the threshold voltage value (e.g., Vt420) of the target cell is unsuccessfully determined, then the wordline voltage value of wordline signal WL0may be increased to an increased voltage value (e.g., voltage value1003) or decreased to a decreased voltage value (e.g., voltage value1001). Between times Tb and Tc, wordline voltage value of wordline signal WL0applied to line460ofFIG. 4may be between voltage values1001and1002to read target cell420to determine its threshold voltage value.

Each of the cells inFIG. 4may be associated with multiple logical pages in which each of the multiple pages may correspond to a threshold voltage value of the cell. For example, in four bits per cell (each cell may store information representing a combination of four binary bits), each of the cells inFIG. 4may be associated with 16 logical pages corresponding to 16 threshold voltage values of the cell. Thus, target cell420ofFIG. 4may be associated with multiple logical pages. InFIG. 10, the multiple logical pages associated with target cell420may be read using different wordline voltage value. For example, if the threshold voltage value (e.g., Vt420) of the target cell420is unsuccessfully determined in one read, then in another read, wordline voltage WLN may be changed from first voltage value (e.g., V0TAR) to a second voltage value (e.g., one of voltage values1001and1103) between reading the first logical page (e.g., one of the 16 logical pages) associated with target cell420and reading the second logical page (e.g., another one of the 16 logical pages) associated with target cell420.

FIG. 11shows a partial schematic diagram of a memory device1100with multiple target cells according an embodiment of the invention. In some embodiments, memory device1100may correspond to memory device100ofFIG. 1. InFIG. 11, memory device1100may include row1170having cells1110,1120,1130,1140,1150, and1160with associated line1180and wordline signal WLN, and row1171having cells1111,1121,1131,1141,1151, and1161with associated line1181and wordline signal WLM. As show inFIG. 11, row1170is adjacent row1171such that row1170is located immediately next to row1171.

For purposes of describing a read operation of memory device1100, cells1120and1150are assumed to be target cells. Since cells1110,1130,1111,1121, and1131are adjacent target cell1120, cells1110,1130,1111,1121, and1131may be called adjacent cells or a first group of adjacent cells. Since cells1140,1160,1141,1151, and1161are adjacent target cell1150, cells1140,1160,1141,1151, and1161may also be called adjacent cells or a second group of adjacent cells. Memory device1100may use line1180to access cells1110,1120,1130,1140,1150, and1160and line1181to access cells1111,1121,1131,1141,1151, and1161.

FIG. 12is a flow diagram showing a method1200for a read operation of memory device1100according to an embodiment of the invention. The following description refers toFIG. 11andFIG. 12.

Activity1210may include reading the group of adjacent cells1110,1130,1111,1121, and1131. Memory device1100may read the group of adjacent cells1110,1130,1111,1121, and1131in response to the command to read target cell1120. The command may be sent to memory device1100by another device. In some embodiments, activity1210may include reading fewer than all cells in the group of adjacent cells1110,1130,1111,1121, and1131. For example, activity1210may include reading only cells1111,1121, and1131.

Activity1220may include obtaining first feedback information. The first feedback information may be obtained by determining a shift threshold voltage value of target cell1120based on the threshold voltage values of the adjacent cells that are read as part of activity1210. Thus, the first feedback information may include a feedback voltage value, which is the shift threshold voltage value of target cell1120, or VSHIFTof target cell1120, based on the on the threshold voltage value of the adjacent cells that are read as part of activity1210. VSHIFTof target cell1120in method1200may be determined in a method similar to that described above with reference toFIG. 4throughFIG. 8.

Activity1230may read the group of adjacent cells1140,1160,1141,1151, and1161. Memory device1100may operate to read the group of adjacent cells1140,1160,1141,1151, and1161in response to the command to read target cell1150. In some embodiments, activity1230may include reading fewer than all cells in the group of adjacent cells1140,1160,1141,1151, and1161. For example, activity1230may read only cells1141,1151, and1161.

Activity1240may include obtaining second feedback information. The second feedback information may be obtained by determining a shift threshold voltage value of target cell1150based on the threshold voltage values of the adjacent cells that are read as part of activity1230. Thus, the second feedback information may include a feedback voltage value, which is the total of the shift threshold voltage value of target cell1150, or VSHIFTof target cell1150, based on the threshold voltage value of the adjacent cells that are read as part of activity1230. VSHIFTof target cell1150in method1200may be determined in a method similar to that described above with reference toFIG. 4throughFIG. 8.

Activity1250may include reading target cell1120based on the first feedback information obtained from activity1220. Memory device1100(FIG. 11) may operate to apply to line1180wordline signal WLN with an initial wordline voltage value V0TAR=V0ADJ1+VSHIFTof target cell1120, where V0ADJ1corresponds to an initial wordline voltage value when reading each of1110,1130,1111,1121, and1131.

Activity1260may include reading target cell1150based on the second feedback information obtained from activity1240. Memory device1100may operate to apply to line1180wordline signal WLN with an initial wordline voltage value V0TAR=V0ADJ2+VSHIFTof target cell1150, where V0ADJ2corresponds to an initial wordline voltage value when reading each of1140,1160,1141,1151, and1161. Initial wordline voltage value V0ADJ1may be equal to initial wordline voltage value V0ADJ2. However, VSHIFTof target cell1120may be unequal to VSHIFTof target cell1150.

FIG. 13is an example timing diagram showing wordline voltage values applied to wordlines of the multiple target cells1120and1150ofFIG. 11. WLN in the vertical axis represents wordline signal WLN ofFIG. 11. V1120represents a wordline voltage value at which target cell1120is read. V1150represents a wordline voltage value at which target cell1150is read. Initial wordline voltage value V0ADJrepresents V0ADJ1or V0ADJ2that may be used to read an adjacent of the first or second group of adjacent cells to obtain the threshold voltage value of the adjacent cell, as described above with reference toFIG. 12.

As shown inFIG. 13, V1120may be equal to the sum of V0ADJand VSHIFT1120(VSHIFTof target cell1120). V1150may be equal to the sum of V0ADJand VSHIFT1150(VSHIFTof target cell1150).

As shown inFIG. 13, wordline signal or voltage WLN may be increased step-wise, such that the voltage value of wordline signal WLN may be increased by an equal amount of VINCafter each signal cycle1301of a count signal COUNT. Memory device1100may operate to generate the COUNT signal internally or receive the COUNT signal from an external clock source. In some embodiments, the COUNT signal may include a clock signal in which the clock signal may be internally generated by the memory device1100or may be provided to memory device1100by an external source.

InFIG. 13, wordline signal WLN may start at a voltage value V0ADJat time Td, then target cell1120may be read when wordline signal WLN reaches voltage value V1120at time Te. A counter of memory device1100, such as counter117ofFIG. 1, may count the number of signal cycles of the COUNT signal starting from time Te. Target cell1120may be read when the count (or the number of signal cycles of the COUNT signal) reaches a quantity corresponding to time Te. Similarly, target cell1150may be read when the count (or the number of signal cycles of the COUNT signal) reaches another quantity corresponding to time Tf. In some embodiments, the number of signal cycles of the COUNT signal during time interval1320, between times Td and Te, may be determined by dividing VSHIFT1120by VINC. In some embodiments, the number of signal cycles of the COUNT signals during time interval1350, between times Td and Tf, may be determined by dividing VSHIFT1150by VINC.

FIG. 14shows a system1400according to an embodiment of the invention. System1400may include a processor1410, an image sensor device1420, a memory device1425, a memory controller1430, a graphics controller1440, an additional circuit1445, an input and output (I/O) controller1450, a display1452, a keyboard1454, a pointing device1456, a peripheral device1458, a transceiver1459, a bus1460to transfer information among the components of system1400, and an antenna1470to wirelessly transmit and receive information to and from system1400. Transceiver1459may perform a transferring of information from one or more the components of system1400(e.g., at least one of processor1410and memory device1430) to antenna1470. Transceiver1459may also perform a transferring of information received at antenna1470to at least one of the processor and the flash memory device. The information received at antenna1470may be transmitted to system1400by a source external to system1400.

Processor1410may include a general-purpose processor or an application specific integrated circuit (ASIC). Processor1410may include a single core processor or a multiple-core processor. Processor1410may execute one or more programming commands to process information. The information may include digital output information provided by other components of system1400, such as by image sensor device1420or memory device1425.

Image sensor device1420may include a complementary metal-oxide-semiconductor (CMOS) image sensor having a CMOS pixel array or charge-coupled device (CCD) image sensor having a CCD pixel array.

Memory device1425may include a volatile memory device, a non-volatile memory device, or a combination of both. For example, memory device1425may comprise a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, or a combination of these memory devices. In some embodiments, memory device1425may include one or more embodiments of the invention, as shown and described with respect toFIG. 1throughFIG. 13(e.g., memory devices100,200,400, or1100).

Display1452may include an analog display or a digital display. Display1452may receive information from other components. For example, display1452may receive information that is processed by one or more of image sensor device1420, memory device1425, graphics controller1440, and processor1410to display information such as text or images.

Additional circuit1445may include a circuit components used in a vehicle. Additional circuit1445may receive information from other components to activate one or more subsystem of the vehicle. For example, additional circuit1445may receive information that is processed by one or more of image sensor device1420, memory device1425, and processor1410, to activate one or more of an air bag system of a vehicle, a vehicle security alarm, and an obstacle alert system.

The illustrations of apparatus such as memory devices100,200,400, and1100, and systems such as embodiments of system1400are intended to provide a general understanding of the structure of various embodiments, and not as a complete description of all the elements and features of apparatus and systems that might make use of the structures described herein.

Any of the components previously described can be implemented in a number of ways, including simulation via software. Thus, apparatus such as memory devices100,200,400, and1100, and systems such as embodiments of system1400described above may all be characterized as “modules” herein. Such modules may include hardware circuitry, single and/or multi-processor circuits, memory circuits, software program modules and objects, and/or firmware, and combinations thereof, as desired by the architect of the apparatus such as memory devices100,200,400, and1100, and systems such as embodiments of system1400, and as appropriate for particular implementations of various embodiments. For example, such modules may be included in a system operation simulation package, such as a software electrical signal simulation package, a power usage and distribution simulation package, a capacitance-inductance simulation package, a power/heat dissipation simulation package, a signal transmission-reception simulation package, and/or a combination of software and hardware used to operate, or simulate the operation of various potential embodiments.

The novel apparatus and systems of various embodiments may include or be included in electronic circuitry used in high-speed computers, communication and signal processing circuitry, single or multi-processor modules, single or multiple embedded processors, multi-core processors, data switches, and application-specific modules including multilayer, multi-chip modules. Such apparatus and systems may further be included as sub-components within a variety of electronic systems, such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., MP3 (Motion Picture Experts Group, Audio Layer 3) players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.), set top boxes, and others.

FIG. 15shows a flow diagram showing a method1500for a read operation in a system according to an embodiment of the invention. Activity1510may send a program command (e.g., a read command) from a first electronic device to a second electronic device to read a target cell in the second electronic device. The first electronic device in method1500may include a component of a system, such as processor1410, memory controller1430, graphics controller1440, additional circuit1445, or I/O controller1450of system1400ofFIG. 14. The second electronic device in method1500may include a component of a system, such as memory device1425or image sensor device1420of system1400ofFIG. 14.

In activity1510, the first electronic device may send the second electronic device the program command to read the target cell, without sending the second electronic device a second program command (e.g., a read command) to read one or more adjacent cells adjacent the target cell.

Activity1520may include reading one or more adjacent cells to determine a threshold voltage value of the adjacent cell.

Activity1530may include reading the target cell based on the threshold voltage value of the adjacent cell(s). For example, activity1530may include applying a wordline voltage value to a wordline associated with the target cell to read the target cell, in which the wordline voltage value may include a shift threshold voltage value of the target cell based on the on the threshold voltage value of the adjacent cell(s).

Method1500may include one or more activities of method700and1200described above with reference toFIG. 7andFIG. 12.

The above description and the drawings illustrate some embodiments of the invention to enable those skilled in the art to practice the embodiments of the invention. Other embodiments may incorporate structural, logical, electrical, process, and other changes. In the drawings, like features or like numerals describe substantially similar features throughout the several views. Examples merely typify possible variations. Portions and features of some embodiments may be included in, or substituted for, those of others. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. Therefore, the scope of various embodiments of the invention is determined by the appended claims, along with the full range of equivalents to which such claims are entitled.

The Abstract is provided to comply with 37 C.F.R. §1.72(b) requiring an abstract that will allow the reader to quickly ascertain the nature and gist of the technical disclosure. The Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.