Nanosheet CMOS semiconductor device and the method of manufacturing the same

This invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a subtract; a P-type semiconductor channel and an N-type semiconductor channel, suspended on the subtract; a gate dielectric layer, wrapped around the P-type semiconductor channel and the N-type semiconductor channel; a gate electrode layer, wrapped around the gate dielectric layer; a P-type source region and a P-type drain region, connected to two ends of the P-type semiconductor channel respectively; an N-type source region and an N-type drain region, connected to two ends of the N-type semiconductor channel respectively; wherein the doping concentration at the surface of the P-type semiconductor channel is the highest, then decreases from the surface to the center region, the doping concentration at the surface of the N-type semiconductor channel is the highest, then decreases from the surface to the center region, and a cross-sectional width of the P-type semiconductor channel is greater than that of the N-type semiconductor channel. The present invention has ability to realize multi-layer staking under unit area, and reducing the length of the channel effectively so as to reduce channel effect and improve carrying capacity and integration level of the device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to P.R.C. Patent Application No. 201811021268.8 titled “semiconductor device and manufacturing method thereof,” filed on Sep. 3, 2018, with the State Intellectual Property Office of the People's Republic of China (SIPO).

TECHNICAL FIELD

The present disclosure relates to the design and manufacture of integrated circuits, and particularly, to a three-dimensional stacked gate-all-around nanosheet complementary inverter with junctionless transistors and gradient channel doping profile, and a method for manufacturing the same.

BACKGROUND

With the continuous development of semiconductor technology, the size of semiconductor components is shrunk, the performance of driving current is improved continuously, the power consumption is reduced continuously, and at the same time, more and more serious short-channel effects, increasingly complex semiconductor manufacturing processes and higher production costs are encountered.

Fin field-effect transistor (FinFET) is a new complementary MOS transistor. The shape of the FinFET is similar to that of a fin. This design can improve circuit control, reduce leakage current and shorten the gate length of the transistor

FinFET is an innovative design of a transistor-Field Effect Transistor (FET) derived from the traditional standard. In a conventional transistor structure, the gate can only control the on and off of a current in a surface of the channel region, which is a planar structure. In the FinFET architecture, the gate is designed in a fin-shaped 3D architecture that can control the on and off of the circuit on either side of the finned gate. This design can greatly improve circuit control and reduce leakage, and can also significantly shorten the channel length of the transistor.

In early 2011, Intel introduced a commercial FinFET which is used on its 22 nm node process to provide faster and more power saving processors for future mobile processors, etc. In 2015, Samsung took the lead in using FinFET technology for 10 nm process. In 2016, TSMC also used FinFET technology for 10 nm process nodes.

As an improvement of the FinFET technology, the three-sided surrounding gate field effect transistor can effectively improve the power and efficiency of the field effect transistor, which has only recently begun to be used in the fields of server, computers and equipment, such that the three-sided surrounding gate field effect transistor will be the mainstream technology for the next few years.

As the demand for integration level, power, and performance of the device are further improved, power and performance can be further improved by stacking silicon nanosheets together. In U.S. Pat. No. 8,350,298, Xiao Deyuan et al. propose a hybrid crystal orientation accumulation type full-encapsulation gate CMOS field effect transistor, as shown inFIG. 1, which includes: a bottom semiconductor substrate1010, a PMOS region having a first channel1301, an NMOS region having a second channel1301, and a gate region1500. The cross sections of the first channel1401and the second channel1301are all racetrack shapes. The gate region1500completely wraps the surfaces of the first channel1401and the second channel1301. This device can avoid polycrystalline silicon gate depletion and short channel effects, and increasing the threshold voltage of the device. However, this device has a large limitation on the channel electron mobility, and the device still cannot fully meet the demand for further improvement in power and performance.

Based on the above, it is necessary to provide a semiconductor device structure that can improve the power and performance of the device.

SUMMARY

In light of the abovementioned problems, an object of the present disclosure is to provide a semiconductor device and a manufacturing method thereof, which can solve the problem of low carrier mobility of the device in the prior art.

An objective of the present invention is to provide a semiconductor device. The semiconductor device may comprise a subtract; a P-type semiconductor channel, suspended on the subtract; an N-type semiconductor channel, suspended on the subtract; a gate dielectric layer, wrapped around the P-type semiconductor channel and the N-type semiconductor channel; a gate electrode layer, wrapped around the gate dielectric layer; a P-type source region and a P-type drain region, connected to two ends of the P-type semiconductor channel respectively; and an N-type source region and an N-type drain region, connected to two ends of the N-type semiconductor channel respectively; wherein the doping concentration at the surface of the P-type semiconductor channel is the highest, then decreases from the surface to the center region, the doping concentration at the surface of the N-type semiconductor channel is the highest, then decreases from the surface to the center region, and a cross-sectional width of the P-type semiconductor channel is greater than that of the N-type semiconductor channel.

In accordance with some embodiments, the doping concentration of the P-type semiconductor channel is linear or gradient decreased from the surface towards to the center region, and the doping concentration of the N-type semiconductor channel is linear or gradient decreased from the surface towards to the center region.

In accordance with some embodiments, the doping concentration of the P-type semiconductor channel decreased from the surface towards to the center region is no less than the order of 102, and the doping concentration of the N-type semiconductor channel decreased from the surface towards to the center region is no less than the order of 102.

In accordance with some embodiments, the material of the P-type semiconductor channel comprises P-type ion-doped Si, and the material of the N-type semiconductor channel comprises N-type ion-doped Si.

In accordance with some embodiments, the material of the P-type source region and the P-type drain region comprises the P-type ion-doped SiGe, the material of the N-type source region and the N-type drain region comprises the N-type ion-doped SiC.

In accordance with some embodiments, a cross-sectional width of the P-type source region and the P-type drain region is greater than that of the P-type semiconductor channel, the P-type source region and the P-type drain region are wrapped around the two ends of the P-type semiconductor channel, a cross-sectional width of the N-type source region and the N-type drain region is greater than that of the N-type semiconductor channel, and the N-type source region and the N-type drain region are wrapped around the two ends of the N-type semiconductor channel.

In accordance with some embodiments, the cross-sectional width of the P-type semiconductor channel is 1.5-10 times of that of the N-type semiconductor channel.

In accordance with some embodiments, the cross-sectional width of the P-type semiconductor channel is 2-4 times of that of the N-type semiconductor channel.

In accordance with some embodiments, each of the P-type semiconductor channel and N-type semiconductor channel is rounded to have a cross-sectional shape of a rounded rectangle.

In accordance with some embodiments, the semiconductor device comprises at least two P-type semiconductor channels stacked upward from the substrate and at least two N-type semiconductor channels stacked upward from the substrate, junctionless P-type field effect transistors are formed based on the P-type semiconductor channels, junctionless N-type field effect transistors are formed based on the N-type semiconductor channels, a gap is between two adjacent junctionless P-type field effect transistors and a gap is between two adjacent junctionless N-type field effect transistors, and a gate electrode layer of the junctionless N-type field effect transistors is connected to a gate electrode of the junctionless P-type field effect transistors by a common electrode to form an inverter.

In accordance with some embodiments, the material of the gate electrode layer of the N-type field effect transistors comprises one of TiN, TaN, TiAl, and Ti, and the material of the gate electrode layer of the P-type field effect transistors comprises one of TiN, TaN, TiAl, and Ti, and the material of the common electrode comprises one of Al, W and Cu.

Another objective of the present invention is to provide a manufacturing method of a semiconductor device. The manufacturing method of the semiconductor device includes the steps of: 1) providing a subtract with a P-type semiconductor channel and a N-type semiconductor channel suspended above the subtract, in which a cross-sectional width of the P-type semiconductor channel is greater than that of the N-type semiconductor channel, and the doping concentration at the surface of the P-type semiconductor channel is the highest, then decreases from the surface to the center region, the doping concentration at the surface of the N-type semiconductor channel is the highest, then decreases from the surface to the center region; 2) forming a gate dielectric layer wrapped around the P-type semiconductor channel and the N-type semiconductor channel; 3) forming a gate electrode layer wrapped around the gate dielectric layer; 4) forming a P-type source region and a P-type drain region at the two ends of the P-type semiconductor channel; and forming an N-type source region and an N-type drain region at the two ends of the N-type semiconductor channel.

In accordance with some embodiments, step 1) comprises the steps of: 1-1) providing the substrate with a plurality of substrate structure layers stacked on the substrate, in which the substrate structure layers comprise a sacrificial layer and a channel layer on the sacrificial layer; 1-2) etching the pluralities of substrate structure layers to form a first fin structure and a second fin structure adjacent with each other, in which the first fin structure comprises a plurality of first sacrificial units and a plurality of first semiconductor channels stacked alternatively, the second fin structure comprises a plurality of second sacrificial units and a plurality of a plurality of second semiconductor channels stacked alternatively, and a cross-sectional width of the first semiconductor channels is greater than that of the second semiconductor channels; 1-3) selectively removing the first sacrificial units in the first fin structure and the second sacrificial units in the second fin structure to obtain the pluralities of suspended first semiconductor channels and the pluralities of suspended second semiconductor channels; and 1-4) doping P-type ions in the first semiconductor channels to form P-type semiconductor channels, and doping N-type ions in the second semiconductor channels to form N-type semiconductor channels.

In accordance with some embodiments, step 1-4) doping P-type ions in the first semiconductor channels to form P-type semiconductor channels comprises the steps of: a) depositing a heavily boron doped dielectric layer on the surface of the first semiconductor channels; b) performing heat treatment to drive boron dopants in the dielectric layer diffused towards the first semiconductor channels to form the P-type semiconductor channels, wherein the doping concentration of the P-type semiconductor channels decreased from the surface towards to the center region; and c) wet etching to remove the dielectric layer.

In accordance with some embodiments, step 1-4) doping N-type ions in the second semiconductor channels to form N-type semiconductor channels comprises the steps of: a) depositing a heavily phosphorus (P) or arsenic (As) doped dielectric layer on the surface of the second semiconductor channels; b) performing heat treatment to drive phosphorus or arsenic dopants in the dielectric layer diffused towards the second semiconductor channels to form the N-type semiconductor channels, wherein the doping concentration of the N-type semiconductor channels decreased from the surface towards to the center region; and c) wet etching to remove the dielectric layer.

In accordance with some embodiments, the doping concentration of the P-type semiconductor channel is linear or gradient decreased from the surface towards to the center region, and the doping concentration of the N-type semiconductor channel is linear or gradient decreased from the surface towards to the center region.

In accordance with some embodiments, the doping concentration of the P-type semiconductor channel decreased from the surface towards to the center region is no less than the order of 102, and the doping concentration of the N-type semiconductor channel decreased from the surface towards to the center region is no less than the order of 102.

In accordance with some embodiments, the material of the P-type semiconductor channel comprises P-type ion-doped Si, and the material of the N-type semiconductor channel comprises N-type ion-doped Si.

In accordance with some embodiments, the material of the P-type source region and the P-type drain region comprises the P-type ion-doped SiGe, the material of the N-type source region and the N-type drain region comprises the N-type ion-doped SiC.

In accordance with some embodiments, a cross-sectional width of the P-type source region and the P-type drain region is greater than that of the P-type semiconductor channel, the P-type source region and the P-type drain region are wrapped around the two ends of the P-type semiconductor channel, a cross-sectional width of the N-type source region and the N-type drain region is greater than that of the N-type semiconductor channel, and the N-type source region and the N-type drain region are wrapped around the two ends of the N-type semiconductor channel.

In accordance with some embodiments, the cross-sectional width of the P-type semiconductor channel is 1.5-10 times of that of the N-type semiconductor channel.

In accordance with some embodiments, the cross-sectional width of the P-type semiconductor channel is 2-4 times of that of the N-type semiconductor channel.

In accordance with some embodiments, step 1) further comprises a step of rounding the P-type semiconductor channel and the N-type semiconductor channel such that each of the P-type semiconductor channel and the N-type semiconductor channel has a cross-sectional shape of a rounded rectangle.

In accordance with some embodiments, step 1) comprises forming at least two P-type semiconductor channels stacked upward from the substrate and at least two N-type semiconductor channels stacked upward from the substrate, in which a gap is between two adjacent P-type semiconductor channels and a gap is between two adjacent N-type semiconductor channels, the step 4) comprises a step of forming junctionless P-type field effect transistors based on the P-type semiconductor channels, the step 5) comprises a step of forming junctionless N-type field effect transistors based on the N-type semiconductor channels, and further comprising a step of depositing a common electrode after the step 5), in which the common electrode connects a gate electrode layer of the junctionless N-type field effect transistors to a gate electrode of the junctionless P-type field effect transistor to form an inverter.

In accordance with some embodiments, the material of the gate electrode layer of the junctionless N-type field effect transistors comprises one of TiN, TaN, TiAl, and Ti, the material of the gate electrode layer of the junctionless P-type field effect transistors comprises one of TiN, TaN, TiAl, and Ti, and the material of the common electrode comprises one of Al, W and Cu.

As described above, the semiconductor device and the manufacturing method thereof have the following beneficial effects:

At least one of the above and other features and advantages of the present invention may be realized by providing a three-dimensional stacked gate-all-around nanosheet complementary inverter with junctionless transistors and gradient channel doping profile, which can realize multi-layer stack of device under an unit area, reduce the length of the channel of the device, reduce short channel effects, effectively improve the integration level of device, and greatly improve the power of device.

The present invention with a cross-sectional width of the P-type semiconductor channel greater than that of the N-type semiconductor channel has an ability to greatly improve the mobility of holes, improve the current carrying capacity of the P-type field effect transistor, and reduce the resistance and power consumption by increasing the cross-sectional area of the P-type semiconductor channel to increase the migration of the hole. At the same time, the cross-sectional width of the N-type semiconductor channel is designed to be smaller based on the mobility of the electron of the N-type semiconductor channel higher than that of the P-type semiconductor channel, so as to make sure the current carrying capacity of the N-type field effect transistor, reduce the area of the N-type semiconductor channel, reduce the voltage required to turn it off, reduce the total area of components, and improve the integration level of device.

The present invention has an ability to effectively improve the hole mobility of the P-type source region and P-type drain region and improve the electron mobility of the N-type source region and N-type drain region by forming the P-type source region and P-type drain region of the P-type field effect transistor and the N-type source region and N-type drain region of the N-type field effect transistor through epitaxial growth, and using SiGe as material of the substrate of the P-type source region and P-type drain region and using SiC as material of the substrate of the N-type source region and N-type drain region, such that the on-resistance of the inverter can be effectively reduced, and the driving current of the inverter can be improved.

The present invention provides a design of the doping concentration at the surface of both the P-type semiconductor channel and the N-type semiconductor channel are the highest, then decreases gradient from the surface to the center region, which can reduce the hot carrier concentration not controlled by the gate electrode, so as to increase the gate controllability of holes or electrons in the channel, and to increase the device performance.

DETAILED DESCRIPTION

The embodiments of the present invention are described below by way of specific examples, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The present invention may be embodied or applied in various other specific embodiments, and various modifications and changes can be made without departing from the spirit and scope of the invention.

Referring toFIGS. 2 through 13. It should be noted that the illustrations provided in this embodiment merely illustrate the basic concept of the present invention in a schematic manner, and only the components related to the present invention are shown in the drawings, instead of the number and shape of components in actual implementation. Dimensional drawing, the actual type of implementation of each component type, number and proportion can be a random change, and its component layout can be more complicated.

As shown inFIG. 2, the present disclosure provides a three-dimensional stacked junctionless semiconductor device, which comprises: a substrate101, P-type semiconductor channels305, N-type semiconductor channels405, gate dielectric layers303,403, gate electrode layers304,404, a P-type source region and P-type drain region306, and an N-type source region and an N-type drain region406.

The substrate101may be a silicon (Si) substrate, a silicon carbide (SiC) substrate101, a silicon germanium (SiGe) substrate101, etc. In this embodiment, the substrate101is a silicon substrate101, in which an insulator layer102is formed on a surface of the silicon substrate101to insulate the substrate101from a drain region and a sequentially formed common electrode50of the device for improving the performance of the device.

As shown inFIG. 2, the P-type semiconductor channels305and the N-type semiconductor channels405are suspended over the substrate101. The P-type semiconductor channels305and the N-type semiconductor channels405can be rounded to have a cross-sectional shape of a rounded rectangle. The material of the P-type semiconductor channels305may be P-type ion-doped Si, and the material of the N-type semiconductor channels405may be N-type ion-doped Si. In this embodiment, the semiconductor device can include two P-type semiconductor channels305stacked upward from the substrate101and two N-type semiconductor channels405stacked upward from the substrate101, in which the P-type semiconductor channels305can be configured to be P-type field effect transistors, the N-type semiconductor channels405can be configured to be N-type field effect transistors, and a cross-sectional width of each of the P-type semiconductor channels305may be greater than that of each of the N-type semiconductor channels405. For example, the cross-sectional width of each of the P-type semiconductor channels305may be 1.5-10 times of that of each of the N-type semiconductor channels405, more preferably, the cross-sectional width of each of the P-type semiconductor channels305may be 2-4 times of that of each of the N-type semiconductor channels405. Since the hole mobility of the P-type semiconductor channels305is generally about one third of the electron mobility of the N-type semiconductor channels405, the cross-sectional width of each of the P-type semiconductor channels305designed to be 2-4 times of that of each of the N-type semiconductor channels405can effectively improve the load capacity of the P-type field effect transistor while ensuring a small footprint of the P-type field effect transistor. The present invention with the cross-sectional width of the P-type semiconductor channels305greater than that of the N-type semiconductor channels405has an ability to greatly improve the mobility of holes, improve the current carrying capacity of the P-type field effect transistor, and reduce the resistance and power consumption by increasing the cross-sectional area of the P-type semiconductor channels305to increase the migration of the hole. At the same time, the cross-sectional width of the N-type semiconductor channels405is designed to be smaller based on the mobility of the electron of the N-type semiconductor channel405higher than that of the P-type semiconductor channels305, so as to make sure the current carrying capacity of the N-type field effect transistor, reduce the area of the N-type semiconductor channels405, reduce the voltage required to turn it off, reduce the total area of components, and improve the integration level of device.

The doping concentration at the surface of the P-type semiconductor channel305is the highest, then decreases from the surface to the center region, the doping concentration at the surface of the N-type semiconductor channel405is the highest, then decreases from the surface to the center region, for example, the doping concentration of the P-type semiconductor channel305is linear or gradient decreased from the surface towards to the center region, and the doping concentration of the N-type semiconductor channel405is linear or gradient decreased from the surface towards to the center region. In accordance with some embodiments, the doping concentration of the P-type semiconductor channel305decreased from the surface towards to the center region is no less than the order of 102, and the doping concentration of the N-type semiconductor channel405decreased from the surface towards to the center region is no less than the order of 102in order to obtain the better performance of the present invention. The present invention provides a design of the doping concentration at the surface of both the P-type semiconductor channel and the N-type semiconductor channel are the highest, then decreases gradient from the surface to the center region, which can reduce the hot carrier concentration not controlled by the gate electrode, so as to increase the gate controllability of holes or electrons in the channel, and to increase the device performance.

As shown inFIG. 2, the gate dielectric layers303,403can be wrapped all around t the P-type semiconductor channels305and the N-type semiconductor channels405. The material of the gate dielectric layers303,403can include one of high dielectric constant (k) material, such as silicon dioxide (SiO2), aluminum oxide (AlO), nitride-oxide-silicon (SiOxNy) compound, silicon-carbon-oxide (SiOC) compound, hafnium (Hf) base, etc.

The gate electrode layers304,404can be wrapped around the gate dielectric layers303,403, in which the gate electrode layers304,404may include gate electrode layers404of the N-type field effect transistor and gate electrode layers304of the P-type field effect transistor, the gate electrode layers304of the P-type field effect transistor may be disposed corresponding to the first semiconductor channels302, and the gate electrode layers404of the N-type field effective transistor may be disposed corresponding to the second semiconductor channels402.

The material of the gate electrode layers404of the N-type field effective transistor may include one of TiN, TaN, TiAl and Ti. The material of the gate electrode layers304of the P-type field effect transistor may include one of TiN, TaN, TiAl and Ti. For example, the material of the gate electrode layers404of the N-type field effective transistor may be the same with the material of the gate electrode layers304of the P-type field effect transistor.

As shown inFIG. 2, the P-type source region and P-type drain region306may be connected to the two ends of the P-type semiconductor channels305. The N-type source region and N-type drain region406is connected to the two ends of the N-type semiconductor channels405. The material of the P-type source region and P-type drain region306may include P-type ion-doped SiGe, and the material of the N-type source region and N-type drain region406may include N-type ion-doped SiC. The cross-sectional area of the P-type source region and P-type drain region306may be greater than the cross-sectional area of the P-type semiconductor channels305, and the P-type source region and P-type drain region306may be wrapped around the two ends of the P-type semiconductor channels305. The cross-sectional area of the N-type source region and N-type drain region406may be greater than the cross-sectional area of the N-type semiconductor channels405, and the N-type source region and N-type drain region406may be wrapped around the two ends of the N-type semiconductor channels405. The present invention has an ability to effectively improve the hole mobility of the P-type source region and P-type drain region306and improve the electron mobility of the N-type source region and N-type drain region406by forming the P-type source region and P-type drain region306of the P-type field effect transistor and the N-type source region and N-type drain region406of the N-type field effect transistor through epitaxial growth, and using SiGe as material of the substrate of the P-type source region and P-type drain region306and using SiC as material of the substrate of the N-type source region and N-type drain region406, such that the on-resistance of the inverter can be effectively reduced, and the driving current of the inverter can be improved.

As shown inFIG. 2, the semiconductor device may include at least two P-type semiconductor channels305stacked upward from the substrate and at least two N-type semiconductor channels405stacked upward from the substrate101, in which a junctionless P-type filed effect transistor may be formed based on the P-type semiconductor channels305and a junctionless N-type filed effect transistor may be formed based on the N-type semiconductor channels405. There may be a gap between two adjacent junctionless N-type field effect transistors and a gap between two adjacent junctionless P-type field effect transistors. The gate electrode layer of the junctionless N-type field effect transistor may be connected to the gate electrode of the junctionless P-type field effect transistor by a common electrode50to form an inverter, in which the material of the common electrode50may include one of Al, W, and Cu.

The present invention provides a three-dimensional stacked gate-all-around nanosheet complementary inverter with junctionless transistors and gradient channel doping profile, which can realize multi-layer stack of device under a unit area, reduce the length of the channel of the device, reduce short channel effects, effectively improve the integration level of device, and greatly improve the power of device.

FIG. 3depicts a schematic circuit diagram of the N-type field effect transistor connected with the P-type field effect transistor by the common electrode50according to some embodiments of the present disclosure. The gate electrode layer406of the N-type field effect transistor may be connected with the gate electrode of the P-type field effect transistor as an input terminal Vin. The source of the P-type field effect transistor may be connected with power source VDD. The drain of the N-type field effect transistor may be connected with the drain of the P-type field effect transistor as an output terminal Vout. The source of the N-type field effect transistor may be grounded.

As shown inFIGS. 4 through 13, the present disclosure provides a manufacturing method of a three-dimensional stacked gate-all-around nanosheet complementary inverter with junctionless transistors and gradient channel doping profile. The manufacturing method may include the steps of:

As shown inFIG. 4, step 1) is first performed, a subtract101with a plurality of body structure layers20stacked above the subtract101, in which each of the body structure layers20may include a sacrifice layer201and a channel layer202on the sacrifice layer201.

The substrate101may be a Si substrate, a silicon carbide substrate101, a silicon germanium (SiGe) substrate101etc. In this embodiment, the substrate101is a silicon substrate101. Then, the sacrificial layer201and the channel layer202are repeatedly formed on the substrate101by a process such as chemical vapor deposition. The material of the sacrificial layer201may be a silicon dioxide, and the material of the channel layer202may be silicon.

In this embodiment, the range of the thickness of the sacrificial layer201may be between 10˜200 nm, such as 50 nm, 100 nm, or 150 nm, and the range of the thickness of the channel layer202may be between 10˜00 nm, such as 25 nm, 50 nm, or 75 nm.

As shown inFIG. 5, step 2) is then performed, the pluralities of body structure layers20are etched by a photolithography process and an etching process to form a first fin structure30and a second fin structure40adjacent with each other on the substrate101, the width D1of the first fin structure30is greater than that of the width D2of the second fin structure40in which the first fin structure30may include a plurality of first sacrificial units301and a plurality of first semiconductor channels302alternatively stacked, and the second fin structure40may include a plurality of second sacrificial units401and a plurality of second semiconductor channels402alternatively stacked. The first sacrificial units301and the second sacrificial units401may be formed by etching the sacrificial layer201, and the first semiconductor channels302and the second semiconductor channels402may be formed by etching the channel layer202.

As shown inFIG. 6, step 3) is then performed, the first sacrificial units301in the first fin structure30and the second sacrificial units401in the second fin structure40are selectively removed to obtain suspended first semiconductor channels302and suspended second semiconductor channels402.

More specifically, the first sacrificial units301in the first fin structure30and the second sacrificial units401in the second fin structure40are wet etched by using a dilute hydrofluoric acid solution DHF to selectively remove the first sacrificial units301in the first fin structure30and the second sacrificial units401in the second fin structure40and to obtain the suspended first semiconductor channels302and the suspended second semiconductor channels402.

As shown inFIG. 7throughFIG. 9, the semiconductor channels are rounded to have a cross-sectional shape of a rounded rectangle. More specifically, the rounded process may include: a) the first semiconductor channels302and the second semiconductor channels402may be oxidized by a thermal oxidation process to obtain thermal oxide layers wrapped all around the first semiconductor channels302and the second semiconductor channels402, in which the oxidation temperature of the thermal oxidation process may be between 800° C. and 1200° C., and the oxidation period may be between 5 minutes and 8 hours; b) the thermal oxide layers may be wet etched using a dilute hydrofluoric acid solution DHF to remove it to obtain the first semiconductor channels302and the second semiconductor channels402having a rounded rectangular (or racetrack shape) cross-sectional shape.

As shown inFIG. 8, P-type ions are doped in the first semiconductor channels to form the P-type semiconductor channels305. For example, the first semiconductor channels may be doped with the P-type ions to from the P-type semiconductor channels305by the following steps:a) using a chemical vapor deposition process (CVD) or an atomic layer deposition process (ALD) to deposit a heavily boron doped dielectric layer on the surface of the first semiconductor channels302, wherein the heavily boron doped dielectric layer can be a heavily boron doped boron-silicate glass;b) performing heat treatment to drive the boron dopants in the dielectric layer diffused towards the first semiconductor channels302in order to form the P-type semiconductor channels305, wherein the doping concentration at the surface of the P-type semiconductor channel305is the highest, then decreases rom the surface to the center region, and the oxidation temperature of the thermal oxidation process may be between 800° C. and 1200° C., and the oxidation period may be between 5 minutes and 8 hours; preferably, the doping concentration of the P-type semiconductor channel305decreased from the surface towards to the center region is no less than in the order of 102times;c) using wet etching to remove the dielectric layer, for example the dielectric layer can be removed by using a dilute hydrofluoric acid solution DHF to remove it.

As shown inFIG. 9, N-type ions are doped in the second semiconductor channels to form the N-type semiconductor channels405. For example, the second semiconductor channels may be doped with the N-type ions to from the N-type semiconductor channels405by the following steps:a) depositing a heavily phosphorus (P) or arsenic (As) doped dielectric layer on the surface of the second semiconductor channels402, wherein the heavily phosphorus or arsenic doped dielectric layer can be a heavily phosphorus or arsenic doped phosphosilicate glass;b) performing heat treatment to drive the phosphorus or arsenic dopants in the dielectric layer diffused towards the second semiconductor channels402in order to form the N-type semiconductor channels405, wherein the doping concentration at the surface of the N-type semiconductor channel405is the highest, then decreases gradient from the surface to the center region, and the oxidation temperature of the thermal oxidation process may be between 800° C. and 1200° C., and the oxidation period may be between 5 minutes and 8 hours; preferably, the doping concentration of the N-type semiconductor channel405decreased from the surface towards to the center region is no less than in the order of 102times;c) using wet etching to remove the dielectric layer, for example the dielectric layer can be removed by using a dilute hydrofluoric acid solution DHF to remove it.

The present invention provides a design of the doping concentration at the surface of both the P-type semiconductor channel and the N-type semiconductor channel are the highest, then decreases from the surface to the center region, which can reduce the hot carrier concentration not controlled by the gate electrode, so as to increase the gate controllability of holes or electrons in the channel, and to increase the device performance.

In this embodiment, the semiconductor device can include two P-type semiconductor channels305stacked upward from the substrate101and two N-type semiconductor channels405stacked upward from the substrate101, in which the P-type semiconductor channels305can be configured to be P-type field effect transistors, and the N-type semiconductor channels405can be configured to be N-type field effect transistors.

The cross-sectional width of each of the P-type semiconductor channels305may be 1.5-10 times of that of each of the N-type semiconductor channels. More preferably, the cross-sectional width of each of the P-type semiconductor channels305may be 2-4 times of that of each of the N-type semiconductor channels405. Since the hole mobility of the P-type semiconductor channels305is generally about one third of the electron mobility of the N-type semiconductor channels405, the cross-sectional width of each of the P-type semiconductor channels305designed to be 2-4 times of that of each of the N-type semiconductor channels405can effectively improve the load capacity of the P-type field effect transistor while ensuring a small footprint of the P-type field effect transistor.

As shown inFIG. 10, step 4) is performed, the gate dielectric layers303,403are formed to be wrapped all around the P-type semiconductor channels305and the N-type semiconductor channels405.

For example, the gate dielectric layers303,403wrapped all around the P-type semiconductor channels305and the N-type semiconductor channels405may be formed by using a chemical vapor deposition process (CVD) or an atomic layer deposition process (ALD), in which the material of the gate dielectric layers303,403may be one of high k material, such as SiO2, AlO, SiOxNycompound, SiOC compound, Hf base, etc.

While the gate dielectric layers303,403are formed, an isolation layer102may be formed on the surface of the substrate101to isolate the substrate101from the source region of the device and the subsequently formed common electrode50, thereby improving the performance of the device.

As shown inFIG. 11, step 5) is performed. The gate electrode layers304,404are formed to be wrapped all around the gate dielectric layers303,403.

For example, the gate electrode layers304,404wrapped all around the gate dielectric layers303,403may be formed by using a chemical vapor deposition process (CVD) or an atomic layer deposition process (ALD), in which the material of the gate electrode layer404of the N-type field transistor may include one of TiN, TaN, TiAl and Ti. The material of the gate electrode layer304of the P-type field transistor may include one of TiN, TaN, TiAl and Ti. As shown inFIG. 12, the common electrode50may be formed by deposited to be connected to the gate electrode layers304,404, in which the material of the common electrode50may include one of Al, W, and Cu.

As shown inFIG. 13, step 6) is performed. The P-type source region and P-type drain region306may be formed on the two ends of the P-type semiconductor channels305to form the junctionless P-type field effect transistor. The N-type source region and N-type drain region406may be formed on the two ends of the N-type semiconductor channels405to form the junctionless N-type field effect transistor. The gate electrode layers404of the junctionless N-type field effect transistor may be connected to the gate electrode layers304of the junctionless P-type field effect transistor by the common electrode50to form the inverter.

The material of the P-type source region and P-type drain region306may comprise the P-type ion-doped SiGe, the material of the N-type source region and the N-type drain region406may comprise the N-type ion-doped SiC. The cross-sectional area of the P-type source region and P-type drain region306may be greater than the cross-sectional area of the P-type semiconductor channels305, and the P-type source region and P-type drain region306may be wrapped around the two ends of the P-type semiconductor channels305. The cross-sectional area of the N-type source region and N-type drain region406may be greater than the cross-sectional area of the N-type semiconductor channels405, and the N-type source region and N-type drain region406may be wrapped around the two ends of the N-type semiconductor channels405.

The material of the P-type source region and P-type drain region306may include P-type ion-doped SiGe, and the material of the N-type source region and N-type drain region406may include N-type ion-doped SiC. The cross-sectional area of the P-type source region and P-type drain region306may be greater than the cross-sectional area of the P-type semiconductor channels305, and the P-type source region and P-type drain region306may be wrapped around the two ends of the P-type semiconductor channels305. The cross-sectional area of the N-type source region and N-type drain region406may be greater than the cross-sectional area of the N-type semiconductor channels405, and the N-type source region and N-type drain region406may be wrapped around the two ends of the N-type semiconductor channels405.

The present invention has an ability to effectively improve the hole mobility of the P-type source region and P-type drain region306and improve the electron mobility of the N-type source region and N-type drain region406by forming the P-type source region and P-type drain region306of the P-type field effect transistor and the N-type source region and N-type drain region406of the N-type field effect transistor through epitaxial growth, and using SiGe as material of the substrate of the P-type source region and P-type drain region306and using SiC as material of the substrate of the N-type source region and N-type drain region406, such that the on-resistance of the inverter can be effectively reduced, and the driving current of the inverter can be improved.

As described above, the semiconductor device and the manufacturing method thereof have the following beneficial effects:

At least one of the above and other features and advantages of the present invention may be realized by providing a three-dimensional stacked gate-all-around nanosheet complementary inverter with junctionless transistors and gradient channel doping profile, which can realize multi-layer stack of device under a unit area, reduce the length of the channel of the device, reduce short channel effects, effectively improve the integration level of device, and greatly improve the power of device.

The present invention with a cross-sectional width of the P-type semiconductor channel greater than that of the N-type semiconductor channel has an ability to greatly improve the mobility of holes, improve the current carrying capacity of the P-type field effect transistor, and reduce the resistance and power consumption by increasing the cross-sectional area of the P-type semiconductor channel to increase the migration of the hole. At the same time, the cross-sectional width of the N-type semiconductor channel is designed to be smaller based on the mobility of the electron of the N-type semiconductor channel higher than that of the P-type semiconductor channel, so as to make sure the current carrying capacity of the N-type field effect transistor, reduce the area of the N-type semiconductor channel, reduce the voltage required to turn it off, reduce the total area of components, and improve the integration level of device.

The present invention has an ability to effectively improve the hole mobility of the P-type source region and P-type drain region and improve the electron mobility of the N-type source region and N-type drain region by forming the P-type source region and P-type drain region of the P-type field effect transistor and the N-type source region and N-type drain region of the N-type field effect transistor through epitaxial growth, and using SiGe as material of the substrate of the P-type source region and P-type drain region and using SiC as material of the substrate of the N-type source region and N-type drain region, such that the on-resistance of the inverter can be effectively reduced, and the driving current of the inverter can be improved.

The present invention provides a design of the doping concentration at the surface of both the P-type semiconductor channel and the N-type semiconductor channel are the highest, then decreases gradient from the surface to the center region, which can reduce the hot carrier concentration not controlled by the gate electrode, so as to increase the gate controllability of holes or electrons in the channel, and to increase the device performance.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.