Active configurable and stackable interface connector

An interface connector system that provides active buffering, amplification, level shifting, filtering, and other functional electronic processing between one side of the connector and the opposing side. In addition, the local generation of electrical stimulus and signals can be provided on one side of the connector. Modules are installed into a housing for each signal pin at manufacture to perform a specific function. The housing populated with the modules is inserted between a circuit board or connector of a cable assembly on one side and integrated circuit, multi-chip module or another cable connector on the other side. The signals that transit between the two sides are electrically processed. Since the functionality is provided from one side to the next, modules can be stacked to enable multiple processes as the signal transitions from one connector to the next connector. The signal transitions through the interface connector between any combination of printed wiring board, integrated circuit, multi-chip module, system on a chip (SOC), or cable-assembly. By inserting the connector in-line, short connections are provided, hence inductance and capacitance are decreased thereby improving high-speed and RF performance while decreasing noise generation or pickup. The housing of the connector not only mechanically supports the individual modules but also can supply power, grounds and otherwise interconnect the modules. The modules, whose outer profile closely matches the profile of the housing openings can have the powers, grounds and other signals bonded to the conductive layers of the housing by heating the assembly to thereby flow the pre-applied solder or by compression fitting, either by pressing or thermal fitting.

FIELD OF THE INVENTION

The present invention is in the field of electronic/electrical connectors and systems capable of handling high frequencies and providing low-noise while also providing low capacitance, low-inductance with minimal loading. More particularly, the invention relates to multi-connector assemblies in high density arrays including connectors being used as an interposer between high-density and/or miniaturized electronic devices and circuit board assemblies.

Known Art

Present trends in designing microelectronic devices and circuits are toward increased miniaturization, higher component density and greater number of component leads per piece-part that are also capable of being configured in high-density, large-number arrays. Such interconnections must be capable of supporting low-noise signals, signals with fast edges (Δv/Δt) or radio-frequencies (RF) signals. In addition, there is more of a need to provide signal buffering, conditioning, filtering or signal termination to reduce parasitic inductance and capacitance. Techniques known in the art for providing high-density interconnections between an integrated circuit (IC) or multi-chip module (MCM) and a printed wiring board (PWB) include using land grid arrays (LGA's), ball grid arrays (BGA's), and flip-chip techniques. LGA's and BGA's have become popular in part because production equipment used to mount and solder surface-mount devices onto circuit boards can be easily adapted. This ease of manufacture is enhanced by the tendency of BGAs during soldering to self-align because of the effects of surface tension caused from the molten solder. Flip-chip techniques provide the lower inductance for getting signals in and out of IC's and MCM's since thereby allowing higher frequencies and less generated noise.

As electronic devices and integrated circuits are becoming more complex with increasing signal densities, increasing speeds and with decreasing signal voltage levels, there is a corresponding need to improve signal integrity issues and reduce noise. Consequently, there is an increasing need to provide interconnections with a minimal amount of permutations to reduce generated noise. Such permutations include interconnecting stub lengths and changes in characteristic impedance caused from physical transitions within the connector. In addition, short connections are required to reduce interconnecting inductance and capacitance and to also decrease attenuation at higher frequencies. With this need to accommodate increasing speeds and densities in environments of decreasing voltage levels, there is a need to increase functionality and flexibility within the connector while maintaining or improving signal integrity issues and low noise operation. Such functionality and flexibility include signal buffering, amplification, level-shifting or many miscellaneous functions to include voltage regulation, signal generation (an oscillator) or phase-lock loops.

Description of Known Art

U.S. Pat. No. 5,085,590 issued to Michael D. Galloway entitled SHIELDED STACKABLE CONNECTOR ASSEMBLY describes a way to stack contact elements that are shielded from adjacent contact elements and supported by brackets. Even though this connector provides a means to stack contacts the structure is restricted to printed circuit boards, does not lend itself to high density nor does it incorporate any active devices to provide a means to isolate, condition or process signals between connecting members or provide a means to incorporate signal generation.

U.S. Pat. Nos. 6,540,558 B1 and B2 issued to Bernardus L. F. Paagman entitled CONNECTOR, PREFERABLY A RIGHT ANGLE CONNECTOR, WITH INTEGRATED PCB ASSEMBLY and ELECTRICAL CONNECTOR WITH INTEGRATED PCB ASSEMBLY consist of contact units mounted on perpendicular printed circuit boards that are stacked together to form an array of contact units. It cannot provide in-line interconnections between signals, and, even though this connector can be adapted to higher density it also does not provide a means to incorporate active circuitry.

U.S. Pat. No. 5,042,146 ('146) entitled METHOD AND APPARATUS OF MAKING AN ELECTRICAL INTERCONNECTION ON A CIRCUIT BOARD by the present inventor, discloses a process and apparatus for forming double-helix contact receptacles directly from insulated wire for interconnecting components independent of printed circuitry. Some of the apparatus disclosed therein, specifically the wire processing mechanism including cutting, stripping, and handling assemblies, is readily adaptable to the present invention which, like the ‘146’ patent, is capable of handling and incorporating both single and twisted-pair insulated wire. Alternatively, coaxial cable can be used with the center conductor in lieu of a single conductor, provided the shield does not contact the center conductor.

U.S. Pat. No. 5,250,759 ('759), also by the present inventor, for SURFACE MOUNT COMPONENT PADS, is incorporated herein by reference in its entirety; '759 discloses a method to form pads for surface-mount electronic components by inserting a stripped portion of insulated wire into an elongated rectangular opening, and anchoring the U-shaped loop thus formed into place with epoxy or a plug. Although the pads disclosed in the '759 patents can be used with area arrays, their elongated pads will not mesh well geometrically with the square pads normally used in arrays. In addition, due to their shape, elongated pads cannot be disposed sufficiently dense in planar arrays to meet the close proximity requirements of LGA's or BGA's.

U.S. Pat. No. 5,755,596, also by the present inventor, for a HIGH-DENSITY COMPRESSION CONNECTOR, also incorporated herein by reference in its entirety, discloses a method to form contact receptacles for high-density area arrays and connectors from sections of insulated wire. In this patent a stripped section of insulated wire is formed into a short loop, this loop inserted into an insulating sleeve, and this insulating sleeve is inserted into a receptacle of a housing. In an allowed continuation-in-part of '596, entitled SLEEVELESS HIGH-DENSITY COMPRESSION CONNECTOR, the insulation portion of insulated wire takes the place of the insulating sleeve.

U.S. Pat. No. 6,010,342 also by the present inventor, for a SLEEVELESS HIGH-DENSITY COMPRESSION CONNECTOR, also incorporated herein by reference in its entirety, discloses a method to form contact receptacles for high-density area arrays and connectors from sections of insulated wire, but does not use the sleeve of the '596 patent. This patent, also using a stripped section of insulated wire to form an interconnecting loop, is inserted into an insulating housing.

U.S. Pat. No. 6,517,383, also by the present inventor, for a IMPEDANCE CONTROLLED HIGH-DENSITY COMPRESSION CONNECTOR, and also incorporated herein by reference, discloses a method to fabricate an impedance-controlled element within a high-density connector array by the insertion of central plugs into a metal housing, where this connector is capable of incorporating series and parallel resistive elements into each connector element.

The above referenced U.S. Pat. Nos. '146, '626, '759, '342 and '596, are cited for the use of insulated wire to interconnect formed component receptacles; they cannot be stacked or incorporate active circuitry. Although U.S. Pat. No. 6,517,383 and the present invention are similar in construction, U.S. Pat. No. 6,517,383 incorporates a metal housing and neither provides for intermediate connections within the connector nor does it support any active circuitry but instead incorporates passive devices for the central element.

BACKGROUND OF THE INVENTION

For purposes of the present disclosure, passive components are defined as components that have no source of power other than the input signal(s), e.g. resistors, capacitors, inductors and transformers, while “active” as used herein is intended as defined in the McGraw Hill Dictionary of Scientific and Technical Terms: “a component such as an electron tube or transistor that is capable of amplifying the current or voltage in a circuit”, which is reasonably assumed to include integrated circuits, and as defined in the IEEE Standard Dictionary of Electrical and Electronics Terms relating to “active” transducers: “A transducer whose output waves are dependent upon sources of power, apart from that supplied by any of the actuating waves.”

Passive components typically have two terminals that constitute two distinct nodes in an electrical circuit, as distinguished from a conductor whose two ends constitute only a single node. While it is possible to operate an active device with only two terminals by utilizing special “phantom” powering techniques, typical active devices have at least three of the following terminals: − DC power, + DC power, input (amplifier), output (amplifier or signal source) and common ground (optionally combined with one DC power terminal).

The present invention is directed to utilizing advanced discrete and/or surface deposition implementations to meet the stringent requirements of compact interface connection assemblies and associated modules incorporating state-of-the art high frequency analog and/or high speed digital active devices, along with the capability of also readily incorporating passive components as required.

OBJECTS OF THE INVENTION

It is a primary object of the present invention to provide a multi-unit connector assembly providing a means to reduce signal degradation within any signal's interconnect by buffering or isolating a signal adjacent to the input of an electronic device.

It is another object to provide an ability to process a signal being input or output from an electronic device.

Another object is to provide a multi-unit connector assembly capable of stacking, thereby providing increasing functionality to the electronic device.

Another object is to provide a multi-unit connector that is simple to manufacture.

Another object is to achieve high density and ability to interconnect to microelectronic circuits such as area-arrayed electronic devices including ball-grid arrays, land-grid array, chip-scale or flip-chip packages.

Yet another object is to provide a multi-unit connector that is capable of generating a signal for input to an electronic device.

SUMMARY OF THE INVENTION

These and other objects are achieved by the present invention, a compression-contact connector assembly having a plurality of cylindrical electronic active elements mounted in an array of cylindrical through-openings in a housing panel. The housing panel incorporates alternating layers of traces or planes of electrically conductive material separated by layers of dielectric material. These layers of electrically conductive material provide power and ground to the connector elements while traces of conductive material etched in the conductive layers can serve to interconnect the connector elements. The active connector elements can include digital or analog, differential or single-ended drivers or receivers. Digital devices can include latches, logic gates, level-shifting devices (for translating voltage levels from one logic family to another) and analog devices can include signal, RF or power transistors, voltage regulators, phase-lock loops, or any type of amplifier. In fact, for the purpose of this disclosure the term active refers to the use of any semiconductor or a device for the generation of a signal, such as oscillators or transducers. Essentially, what differentiates this interface connector from other types of connectors, interface or otherwise, is that active modules are inserted internal to the housing with each module preselected and installed into individual openings of the housing for the needed functionality. This arrangement ultimately matches the layout of the interfacing device, such as an integrated circuit, multi-chip module, system on a chip (SOC) or a connector of a cable assembly. The connector array is typically situated between a circuit board and integrated circuit or alternatively can be stacked with multiple units between the circuit board and integrated circuit. This stacking can serve to process one or more of the signals as they transition each connector array. In addition the present invention can be used as an interposer between two connector assemblies as described in U.S. Pat. Nos. ″759, '596, '383 or '342.

DETAILED DESCRIPTION

FIG. 1shows an exploded three-dimensional view of a complete stacked interface connector system10that, in this scenario, consist of two interface connector assemblies15A and15B that are sandwiched between an area array electronic package20which can consist of a land-grid/ball-grid/column-grid array device and circuit board25. Interface connectors15A and15B interface and connect area array20to circuit board25. As partially detailed inFIG. 1but best seen inFIG. 2(the side view ofFIG. 1) pad30A of interface connector15A connects to pad35of area array20, pad30B of interface connector15A connects to pad40A of interface connector15B and pad40B of interface connector15B connects to pad45of circuit board25. Other scenarios as an alternative for system10can consist of just one interface connector assembly (either15A or15B) or alternatively three or more interface connector assemblies (to make15C,15D, etc.—not shown) between area array20and circuit board25.

FIG. 3shows interface connector assembly15with three forward interface connector modules50A,50B and50C that are elevated from housing55. Each module is retained in separate cavities within housing55and thus modules50A,50B and50C are retained in cavities60A,60B, and60C. Optional lower end caps65A,65B and65C which in this figure are separated from modules50A,50B and50C provide the mechanical and electrical interface to the opposing contact (not shown). Housing55is constructed of alternating layers of electrical conductive material70and dielectric material75and can be similar in construction to that used within printed-circuit boards. The layers of electrically conductive material can be used to supply electrical power and grounds to the modules or be used to interconnect the modules with etched traces of conductive material. The dielectric material can serve to separate the power and ground planes or can be used to separate a trace from a reference plane as used with signal traces in a strip-line or micro-strip configuration, thereby providing interconnecting one or more modules with traces of a pre-determined characteristic impedance. During manufacture, specific modules (60A,60B,60C, etc.) are inserted into predetermined locations within interface connector assembly15, where the function of each nodule is determined by the particular function needed at that location. The modules are retained within the cavities of interface connector assembly15by epoxy or can be pressed-fit into place.

FIG. 4Ashows a interface connector module50with end caps65and80attached. The entire surface area85of the end cap can be conductive or a confined area90can be the only conductive area. A limited conductive area may be necessary under certain conditions, such as if end caps80touch each other or to electrically isolate the caps from an conductive surface of the interface connector assembly. End caps65and80can help increase the conductive area to contact an opposing contact area or can be used to help retain module50within housing55. The conductive contact surface can also be plated with a noble metal in order to impede oxidation of the contact surface.

FIG. 4Bshows an alternate interface connector module100without end caps65and80of FIG.4A. Module100can be an alternative to module50but at a cost of losing conductive surface area or a means of retaining the module. As with end cap80of module50, the entire surface area105can be conductive or the conductive area can be confined to an area110. In both modules50and100of FIG.4A andFIG. 4Bconductive bands115and120provide an electrical interface between one of the conductive planes70of housing55and modules50and100, wherein they are connected to transfer power, ground, or signals between housing55and the modules. Each module consists of a minimum of two or more connection bands in order to supply power to any active device (e.g. VCC and ground) and additional bands would be required to connect to additional traces within the housing. Bands115and120are bonded to one of the conductive layers70during manufacture either by an air-tight press fit, a conductive epoxy, or by the use of solder. When using the solder technique, one possible method is to pre-deposited solder onto conductive bands115and120of the modules and inserting the modules into the cavities of housing55after which the assembly is elevated in temperature to flow the solder, thereby electrically bonding conductive bands115and120to the conductive layers70. The cavity which retains a module can be unkeyed (e.g. circular) to allow unfettered rotational positioning of the module within the cavity or be keyed to provide specific positioning of the module within the cavity, thereby enabling bands115or120to contact conductive plane70only at a specific location.

FIG.5A throughFIG. 5Dare sectioned side views of different functional configurations of modules represented with electronic schematic symbols that are situated within housing55of FIG.3.

FIG. 5Ais a sectioned side view of a interface connector assembly showing circuit schematics of three types of modules consisting of a type CMOS FET transistor buffer125. In module130A the flow of the signal is from end cap30A to end cap40A while in module130B the signal flow is from40B to30B. Module130C consists of two stages of CMOS FET transistors where input logic level at end cap30C is translated to a different logic level at the output at end cap40C. Such a two-stage buffer can be used for level shifting from one logic family to another, such as from TTL to PECL or vise-versa. Power and ground for modules130A,130B and130C are tapped off through conductive bands at115A,120A,115B,120B,115C,120C, and115D,120D. In module130A the positive connection is transferred from the conductive plane at70A to the source of the FET via conductive band115A and the negative or ground connection is from conductive plane70B via conductive band120A. In module130B the negative or ground connection is transferred from the conductive plane at70C to the source of the FET via conductive band115B and the positive connection is from conductive plane70D via conductive band120B. All power and ground connections to bias the active devices in the modules are connected in a similar manner, except the particular planes to which the active devices are connected are dependent on the voltage levels at which the active devices require and the pre-determined arrangement of the stack-up of the planes.

FIG. 5Bis a sectioned side view of a interface connector assembly schematic showing two modules consisting of two analog amplifiers. Module130D serves as an output buffer where the signal flow goes from end cap30D to end cap40D and module130E serves as an input amplifier where the signal flow goes from end cap40E to end cap30E. Operational amplifiers130D and130E can include any type of analog amplifier including a generic operational amplifier, instrumentation amplifier, trans-impedance amplifier or isolation amplifier.

FIG. 5Cshows a sectioned side view of a interface connector assembly schematic where modules130F and130G are interconnected through trace131within conductive layer70G. Within module130F a signal enters cap30F from the interconnecting electronic package, connector or circuit board, is buffered with an active device in module130F, enters trace131from contact133A, enters the active device in module130G from contact133B, and is then output from the active device in module130G. From active device in module130G the signal then reenters the interconnecting electronic package, connector or circuit board at cap30G. Within modules130F and130G the signal exiting the active device of module130F or being input into module130G can optionally connect to pads40F and40G as indicated with connections represented with the dashed lines135A or135B. Other applications of using a conductive trace131within one of the conductive layers not only can convey data information but also can convey control signals, such as a device enable, 3-state enable, reset, strobe, or any other control functions.

FIG. 5Dshows a sectioned side view of a module130H that represents any active device, as designated with a box at140. Module130H can output at30H and having an optional input at40H or alternatively can output at40H and having an optional input at30H. Module130H can be a voltage regulator, a voltage reference, a delay line, a one-shot, a logical inverter, or any other active function that receives their input at either cap30H or40H and output at the opposing cap. Module130H can also be an output-only device such as a temperature transducer or an oscillator, where power and ground are connected to conductive planes70H and70J via connections115E and120E and the output can exist at either cap30H or40H. The voltage regulator and voltage reference can also function as an output-only device (the input-end not used) when the voltage is input from conductive planes70H and70J via connections115E or120E.

FIGS. 6A through 6DandFIG. 7show different methods of implementing active circuitry into or onto a module. In each of these methods caps30,40,65or80may be included to connect to the opposing connection point/contact or optionally be not included, as shown.

FIG. 6Ashows module150which is one method to implement active circuitry onto a module. Module150has a CMOS FET transistor deposited on the surface and can be similar in function to the CMOS FET of module130A in FIG.5A. In this representation, one layer of deposition is shown on surface155of module150. In practice multiple layers can be sequentially deposited to increase the complexity and functionality of the module. As shown on module150, conductor160connects end conductive pad area110to the gate region165. Conductor170transfers current from one of the conductive bands at175to one of the source terminal of the CMOS FET and conductor180transfers current from the conductive band at185to the other source terminal of the CMOS FET connection. The drain terminals of the CMOS FET are tied together and connected to conductive trace190which connects the drain terminals to conductive metal195(not visible in this view) at the end of the module. This conductive metal195at the end of the module in turn connects to the next module, circuit board pad or the pad of the electronic package.

FIG. 6Bshows another method to apply active circuitry within a module. Module200retains an active device205within slot210of the module where pad215of the active device connects to pad220of the module through wire bonds225. Internal interconnections within the module (not shown) connect conductive bands230and235to the appropriate pads of the active device205. In addition, end conductive pad area110and end conductive pad area195(not visible in this view) each have a connection to one of the pads220(these connection also are not shown).

FIG. 6Cshows module250, yet another method to apply active circuitry within a module, where active device255is shown elevated away from module250in order to better view the pads of the device and module. Interconnecting pads located on the bottom of active device255(pads not shown) are placed against pads260of the module and are electrically connected using direct-chip attach or flip-chip methods. Direct-chip attach and flip-chip attachment methodology are known in the electronics industry and the are an alternative to wire bonding techniques when bonding electronic packages to a circuit board or a substrate. As with module200ofFIG. 6Binternal interconnections within the module (interconnections are not shown) connect conductive bands265and270to the appropriate pads of the active device255and end conductive pad area110and end conductive pad area195(not visible in this view) each have a connection to one of the pads260through one of the conductive traces275.

FIG. 6Dis an exploded view of module300which is yet another method to implement active circuitry within a module. Active device305as shown is elevated away from module300with the pads for the active device (device pads are not shown) that connects to module pads310with the use of direct-chip attach or flip-chip techniques, in a manner similar to that of module250. In module300, module half315A folds onto module half315B, with active device305residing within cavity320. Internal interconnecting traces325connects module pads310of the module to conductive band330and conductive band335, while also connecting module pad310to end conductive pad area340and end conductive pad area345(not visible in this view).

Active circuitry and supporting circuitry can be implemented within modules by a combination of deposition as with module150of FIG.6A and the use of a package as with modules200,250and300inFIGS. 6B,6C and6D. As an example, the crosshatched area340ofFIG. 6Cis a resistive load and can be deposited between interconnect area110and conductive band265. Other types of circuitry including semiconductor can be deposited onto the module250to add or increase functionality.

FIG. 7shows module350which is adapted to the output of differential signals and optionally the input of differential signals. As with active device305of module300residing within cavity320, the active device355of module350resides within cavity360and the pads of active device355(pads not shown) directly attached to module pads365A through365F. Alternative implementations for active circuit implementations can deposit active circuitry onto the surface of module350similar to that as implemented with module150of FIG.6A. In this instance for module350interconnecting pads365A,365B365E and365F respectively connect to traces370A,370B,370E,370F (trace370E not shown) which in turn respectively connects to pads375A,375B,375C, and375D (pads375C and375D are not shown) which in turn respectively connect to conductive areas380A,380B,380C, and380D of caps385A,385B,385C and385D. Also shown with active device355is a resistive load390having pads395A and395B which are respectively connected to pads400A and400B which in turn connects to module pads365E and365F. To transfer power and return current connections to active device355, conductive traces410A and410B within the housing which are bonded and connect to conductive bands405A and405B once module350is installed into cavity415. Conductive bands405A and405B in turn connect to pads365C and365D via traces370C and370D. The differential-signal capability of module350is needed when connecting to differential signals or when referencing one signal to the next, such as required with phase-lock loops where the coincidence of one frequency source is compared with the coincidence of an opposing frequency source. Other applications of two-inputs for module350can be for the inverting and non-inverting inputs of an operational amplifier or two inputs for a logic function such as an OR, AND or XOR logic function. In addition, module350can serve as a differential input device with a single-output or a single-input device with differential outputs. Such applications include the translation of differential signals to single-ended signals or the translation of single-ended signals to differential signals. When differential signals enter module350from (the ends represented with) caps385A and385B, single ended signals can be output from either (the ends represented with) caps385C or385D, or both. Alternatively when differential signals enter module350from (the ends represented with) caps385C and385D, single ended signals can be output from either (the ends represented with) caps385A or385B, or both. Alternatively a differential-signal input can be processed by an active device and the output connected to another active device in the interface array via a pair of intermediate traces, in a manner similar to that of the single-ended modules130F and130G of FIG.5C. Other alternatives for module350can include tandem-signal outputs such as an oscillator or temperature-measuring device having differential outputs and requiring no signal inputs.

In the practice of this invention a method is provided to insert modules into a housing panel comprised of openings to process, isolate, buffer or generate signals being input into an integrated circuit or multi-chip module or process, isolate or buffer signals being output from an integrated circuit or multi-chip module, whether the signals are single-ended or differential in nature. The geometry to which is being interfaced by the interface connector is not restricted to ball-grid, land-grid or column-grid arrays but can easily be adapted to other types of surface-mount devices comprised of leads, including quad flat-pack devices. The only disadvantage of using leaded devices is the penalty in real estate for the number of connections per unit area.

This invention may be embodied and practiced in other specific forms without departing from the spirit and essential characteristics thereof. The present embodiments therefore are considered in all respects as illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than by the foregoing description. All variations, substitutions, and changes that come within the meaning and range of equivalency of the claims therefore are intended to be embraced therein.