Thin film transistor with small storage capacitor with metal oxide switch

Disclosed herein is a sub-pixel circuit for a display device. The sub-pixel circuit has a driving TFT and at least one switching TFT. The at least one switching TFT is an oxide TFT. The sub-pixel circuit additionally has at least one storage capacitor wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF.

BACKGROUND

Field

The present disclosure generally relates to a thin film transistor having a storage capacitor that is miniaturized. The thin film transistor may be utilized in a display screen such as an organic light emitting diode (OLED) display screen.

Description of the Related Art

Input devices including display devices may be used in a variety of electronic systems. The display resolution tells you how many pixels your screen can display horizontally and vertically. It's written in the form N×M. In this example, the screen can show N pixels horizontally, and M vertically. If you're comparing two screens of the same size but with different resolutions, the screen with the higher resolution (that's the one with more pixels) will be able to show you more of what you're working on, so you don't have to scroll so much. The higher the resolution of the display, the greater degree of detail for clear quality images the display will produce.

High resolution display devices for organic light emitting diode OLED, having greater than 600 ppi (pixels per inch), require very small pixel sizes. Each pixel may have three or more sub-pixels to set a color at the pixel. With shrinking pixel sizes, everything becomes smaller with high resolution displays. For example, the circuitry driving the sub-pixel will have a smaller foot print. The circuitry driving the sub-pixel has a plurality of thin film transistors and capacitors as well as an organic light emitting diode (OLED) area. The thin film transistor (TFT) size can be shrunken based on pixel size shrinkage from high resolution. However, it is difficult to make storage capacitors associated with the TFT circuit smaller since the required storage capacitance is mainly determined by frame rate and leakage current through the TFT connected to the storage capacitance. Thus, further reduction of the pixel footprint is difficult.

As a result, new technology should be developed that can reduce the pixel footprint size.

SUMMARY

Disclosed herein is a sub-pixel circuit for a display device. In one embodiment, the sub-pixel circuit has a driving TFT and at least one switching TFT. The at least one switching TFT is an oxide TFT. The sub-pixel circuit additionally has at least one storage capacitor wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF.

In another embodiment, a sub-pixel circuit is formed in a stack. The sub-pixel circuit has a driving TFT. The driving TFT has a source disposed on a top surface of the stack, a drain on the top surface of the stack, and a conductive channel formed in the stack. The conductive channel has a first end and a second end. The first end is electrically coupled to the source and the second end is electrically coupled to the drain. The sub-pixel circuit has at least one switching TFT. The sub-pixel circuit additionally has at least one storage capacitor wherein the storage capacitor is inside the driving TFT disposed above the conductive channel and below the top surface.

In another embodiment, a display has a plurality of pixels. The pixels have a plurality of sub-pixels. Each sub-pixel of the plurality of pixels has an OLED area and a sub-pixel circuit. The sub-pixel circuit has a driving TFT and at least one switching TFT, wherein the at least one switching TFT is an oxide TFT. The sub-pixel circuit additionally has at least one storage capacitor wherein the storage capacitor has a capacitance between about 1 fF and about 55 fF.

DETAILED DESCRIPTION

The following detailed description is merely exemplary in nature and is not intended to limit the disclosure or the application and uses of the disclosure. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding background, summary, or the following detailed description.

Off leakage current (loff) of metal oxide (MOx) thin film transistors (TFT) is usually 3 orders of magnitude lower than low temperature polysilicon (LTPS) TFT. Switching TFTs made by MOx TFTs can hold storage capacitance effectively due to the low loff for OLED pixel devices. Thus, the storage capacitance size can be reduced due to the lower leakage current across the switching TFT made by using a MOx than LTPS.

High resolution display devices for OLED (i.e., greater than 600 pixels per inch (ppi)) will have smaller pixel size. Everything shrinks with high resolution displays due to the shrunken pixel size. The TFT size can be shrunken based on pixel size shrinkage from high resolution. However, storage capacitor capacitance, i.e., size, is mainly determined by frame rate and the leakage current through the switching TFT connected to the storage capacitor for the OLED display. As results, disclosed herein is pixel circuits and device structures which permit the operation of high resolution OLED with smaller storage capacitor sizes.

Using the MOx switching TFT, a 3 order lower off leakage current (loff) can be achieved over LTPS switching TFTs. Thus, the MOx switching TFT can maintain storage capacitance for 1 frame holding time without losing capacitance over the LTPS switching TFT. This characteristic can reduce storage capacitor size between about 5 to about 10 times. The reduced capacitor sizes provide the space for a higher pixel density. The high k solution for smaller capacitor size s effective for up to about a 1200 pixels per inch (ppi) OLED while a switching MOx TFT can be applied to higher resolutions such as a resolution greater than 1200 ppi.

In order to operate a sub-pixel of an OLED pixel for a display, at least two transistors and one capacitor are required. A switching TFT passes data voltage to the capacitor (storage). The storage capacitor is connected to a gate for the driving TFT. The gate voltage of the driving TFT connected to the storage capacitance determines how much current of the driving TFT is flowing to the OLED to control brightness. The required capacitance of the storage capacitor is determined by the frame rate and the leakage current of the switching TFT connected to both the storage capacitor and the gate of the driving TFT for the display and is expressed in the following equation:
ΔQ=C×ΔV=leakage current×Δt

If the leakage current is 1 order lower, the capacitance (C) can be 1 order less as well. Replacing a conventional LTPS switching TFT with a MOx switching TFT can reduce leakage current by at least 1 to 2 orders of magnitude. The required capacitance can be also be reduced by the same level. Thus, the storage capacitor size can be reduced by using the MOx switching TFT. Further description of this arrangement may be found in the description of the figures below.

FIG. 1is a schematic of an active matrix organic light emitting diode (OLED) panel100. The OLED panel100has an array of pixels190, i.e., a first pixel1901, a second pixel1902, a third pixel1903, etc., arranged in rows160and columns180. Each pixel190has a plurality of sub-pixels150for determining a value of the pixel190. For example, a first pixel1901has a first sub-pixel1501A, a second sub-pixel1501Band a third sub-pixel1501C. Each sub-pixel150being a single color element of a respective pixel190. However, the first pixel1901may have more than three sub-pixels150, for example, a sub-pixel1501Nwherein ‘1N’ can represent any number of sub-pixels150for the first pixel1901. Each row160in the OLED panel100can be accessed independently using gate lines110. Each column180in the OLED panel100can be accessed using data lines120. Addressing a first gate line112and a first data line122accesses the first sub-pixel1501Ain the first pixel1901of the OLED panel100. Each sub-pixel150may be similarly addressed in the OLED panel100. In various embodiments, while each sub-pixel150is illustrated as being coupled to a single select line, each sub-pixel may be coupled to a plurality of select lines that may be used to control updating each sub-pixel150. In such embodiments, the select lines may be driven at different times with different select signals to control the update timing of the sub-pixels150.

In one or more embodiments, the OLED panel100may be an organic light emitting diode (OLED) display device. In such an embodiment, each of the sub-pixels150may comprise an anode electrode that is coupled to a corresponding select line or lines and a data line via one or more transistors. A sub-pixel data signal or signals is applied to each activated anode electrode to drive the anode electrode to a specified voltage level. An OLED display device additionally includes a cathode electrode that is driven to a voltage level by a processing system for display updating and one or more organic layers. The supply voltage is applied to each sub-pixel to drive sub-pixel for updating. In one embodiment, a positive supply voltage may be referred to as ELVDD and a negative supply voltage may be referred to as ELVSS.

FIG. 2Ashows a schematic illustration with a bottom emission OLED display. OLED is positioned on the top of the sub-pixel circuit220. Light from the OLED cannot pass through the sub-pixel circuit area220due to the direction of light emission, downward. The single sub-pixel150may be the first sub-pixel1501A. However, the single sub-pixel150shown inFIG. 2Ais generic to each of the sub-pixels150, such as the first sub-pixel1501A, and further discussion will be with regard to the generic sub-pixel150. The sub-pixel150has a sub-pixel area250. A portion of the sub-pixel area250is occupied by an organic light emitting diode (OLED) area210. The OLED area210is the light-emitting element of the sub-pixel150. The OLED area210is a current driven light-emitting device. The remaining portion of the sub-pixel area250is occupied by a sub-pixel circuit220that has one or more transistors, capacitors and metal routing connecting the transistors and capacitors for forming the sub-pixel circuit220. The one or more transistors, capacitors and metal routing may be disposed within a different metal layer of a substrate (device) than another one of the transistors, capacitors and metal routing in forming the sub-pixel circuit220. The sub-pixel circuit220controls the OLED area210providing the power needed to drive the sub-pixel150, i.e., to emit or not emit light.

FIG. 2Bshows a schematic illustration with a top emission OLED display. For the top emission OLED display, the OLED is positioned on the top of the sub-pixel circuit220. The direction of light from the OLED is upward, so the sub-pixel circuits220do not block the light. Therefore, the area of the sub-pixel circuits220from top emission OLED display can be comparable with the OLED area210, which allows higher density than the bottom emission OLED display.

FIG. 3andFIG. 4illustrate example schematics of the sub-pixel circuit220for the sub-pixel150, according to one or more embodiments. The sub-pixel circuit220has a plurality of thin-film transistor (TFT) and a storage capacitor. However, it should be appreciated that the sub-pixel circuit220may have more than two transistors and/or more than one capacitor. Generally, the sub-pixel circuit220includes a switching transistor310, a current regulator or a driving transistor330, and a storage capacitor320. The transistors310,330may be relatively low-leakage current transistors, such as oxide transistor, a low-temperature polycrystalline silicon (LTPS) transistor, or a hybrid of the LTPS and oxide, i.e., LTPO transistor. Preferably, the switching transistor310has a leakage current of not more than about 10−12A. The driving TFT330may be a p-type LTPS TFT (Tp2) or a n-type LTPS TFT or n-type oxide TFT (Tn2). The switching TFT310may be an oxide TFT (Tn1) or hybrid LTPO.

The switching TFT310gate (G1) is connected to selection scan line (Vscan)386and the source-drain are connected between Vdata line384and the gate (G2) of driving TFT330. An OLED388, disposed in the OLED area210of the sub-pixel150pixel in a full-color display, is electrically connected to the driving transistor330. The circuit for the OLED388continues further to a low level supply voltage (VSS) or ground (GND). The OLED388is controlled by the sub-pixel circuit220and has the cathode connected to the common terminal or conductor and the anode is connected through the source-drain of the driving TFT330to a high level power supply (VDD)382. The role of the storage capacitor (Cst)320is for holding the gate voltage of the driving TFT (Tn2/Tp2)330. InFIG. 3, the storage capacitor320is connected between the VDD382and the gate (G2) of driving TFT330. InFIG. 4, the storage capacitor320is connected between the OLED388and the gate (G2) of driving TFT330.

When a select signal appears on Vscan line386and a data signal appears on Vdata line384, the OLED388is addressed or selected. The transistors may be turned on and off by applying a select signal to the gate of the transistor310/330via the selected line. The signal on the Vscan line386is applied to the gate (G1) of switching transistor310, turning “ON” the transistor. The data signal on Vdata line384is applied through the source-drain of switching transistor310to the gate (G2) of driver transistor330, turning the driver transistor330“ON” according to the amplitude and/or duration of the data signal. The driver transistor330then supplies power, generally in the form of driving current, to OLED388, the brightness or intensity of light generated by OLED388may depend upon the amount and/or duration of current supplied. The storage capacitor320memorizes the voltage on the Vdata line384after switching transistor310is turned “OFF”.

FIG. 5illustrates graph of the change in voltage across the switching transistor, according to one or more embodiments. The graph500illustrates the voltage for the Vdata line384and the Vscan line386over a time570. The Vscan line386traverses between a low Vscan voltage518and a high Vscan voltage512over time570. The Vdata line384traverses between a low Vdata voltage528and a high Vdata voltage522over the same period of time570. A voltage value, by which the pixel voltage is reduced, is referred to as a kickback voltage (ΔVp) shown at item550in the graph ofFIG. 5. The kickback voltage550is varied based on the data signal and induced when the gate signal falls, i.e., the Vscan line386moves from the high Vscan voltage512to the low Vscan voltage518. The gate (G2) voltage (VG2) for driving the OLED is maintained by the capacitor (Cst)320. Leakage across the switching TFT310results in a declining value for the VG2. Graph line530illustrates the VG2without leakage through the switching TFT310(Oxide TFT−Tn1). Graph line540illustrates the VG2having a small leakage through the switching TFT310(LTPS TFT−Tn1). The voltage difference560between the VG2having no leakage (line530) and the VG2having leakage (line540) is compensated by the capacitor Cst320. The capacitor Cst320is sized to compensate for the kickback voltage and the leakage to maintain the voltage at the gate (G2). Where Cgd1is the TFT capacitor between G1and D1and Cgs2is the TFT capacitor between G2and D2, both the VG2and kickback voltage (ΔVp) can be calculated with the following equations:
VG2=(Vdata,High−Vdata,Low)×{(Cst+Cgs2)/(Cst+Cgd1+Cgs2)
ΔVp=(Vdata,High−Vdata,Low)×{(Cgd1)/(Cst+Cgd1+Cgs2)

If oxide TFT instead of LTPS TFT is used as Tn1, VG2voltage drop can be minimize due to the smaller leakage current through Tn1. If Cst is much greater than Cgd1, the kick back voltage ΔVp and the VG2voltage drop, which is caused by Cgd1(TFT capacitor between G1and D1), can be minimize.

Referring back toFIG. 3, if oxide TFT instead of LTPS TFT is used as Tn1, can minimize VG2voltage drop due to the smaller leakage current through Tn1. If Cst is much greater than the Cgd1, the kickback voltage ΔVp and the voltage drop VG2, which is caused by Cgd1(TFT capacitor between G1and D1) can be minimized. Here, Tn1is an n-type Oxide TFT, Tp2is a p-type LTPS TFT. At least 2 TFTs are utilized with one being the driving TFT (Tp2) and the other being the switching TFT (Tn1).

Referring back toFIG. 4, if an oxide TFT is used instead of LTPS TFT as Tn1, the voltage drop VG2, due to the smaller leakage current through Tn1can be minimized. If Cst is much greater than Cgd1, the kickback voltage ΔVp, the voltage drop VG2, caused by Cgd1(TFT capacitor between G1and D1) can all be minimized. Here, Tn1is an n-type oxide TFT and Tn2is an n-type LTPS TFT or n-type oxide TFT. Thus, at least one capacitor and two TFTs are utilized for the sub-pixel circuit220wherein the two TFTs involve one driving TFT (Tn2) and one switching TFT (Tn1).

The Cst320is sized to compensate for the ΔVp550as well as leakage current across the switching TFT310. Referring now toFIGS. 3 and 4, the capacity (size) of the Cst needs to be greater than about 9 time Cgs to minimize voltage kick back where Cgs is the capacitance between the gate and the source of the switching TFT310.

For a TFT length of about 10 μm, width of about 40 μm and a gate oxide thickness of about 100 nm and a Cgs of about 0.50 fF/μm2, the preferred Cst value range is between about 2.2 fF greater than the Cst and less than about 55 fF.

For a TFT length of about 10 μm, width of about 40 μm and a gate oxide thickness of about 150 nm and a Cgs of about 0.34 fF/μm2, the preferred Cst value range is between about 1.5 fF greater than the Cst and less than about 37 fF.

For a TFT length of about 10 μm, width of about 40 μm and a gate oxide thickness of about 200 nm and a Cgs of about 0.25 fF/μm2, the preferred Cst value range is between about 1.1 fF greater than the Cst and less than about 28 fF.

FIGS. 6A and 6Billustrate examples of a sub-pixel circuit formed in a stack650, according to one or more embodiments. The stacks650have a first layer602. A second layer604is disposed on the first layer602. In one embodiment, the second layer604is in contact with the first layer602. A third layer606is disposed on the second layer604. In one embodiment, the third layer606is in contact with the second layer604. A fourth layer608is disposed on the third layer606. In one embodiment, the fourth layer608is in contact with the third layer606. A fifth layer610is disposed on the fourth layer608. In one embodiment, the fifth layer610is in contact with the fourth layer608. A sixth layer612is disposed on the fifth layer610. In one embodiment, the sixth layer612is in contact with the fifth layer610.

The first layer602may be a glass or other suitable flexible substrate. The second layer604is a first buffer layer. The second layer604(buffer1) may be composed of a material such as a p-type silicon (boron-doped silicon), vanadium oxide (V2O5), aluminum nitride (AlN), tungsten nitride, other metal oxides or metal nitrides, or combinations thereof. The third layer606is a gate insulating layer (GI). The third layer606(GI) may be composed of a material such as for example, silicon di-oxide (SiO2), polymethylsilsesquioxane (PMSG) or other suitable material. The fourth layer608is a first inter layer dielectric (ILD). The fourth layer608(ILD1) may be composed of a material such as oxides (both doped and undoped), nitrides, oxynitrides, and carbides such as silicon-based dielectric films. The fifth layer610is a second buffer layer. The fifth layer610(buffer2) may be formed from substantially the same list of materials as the second layer604(buffer1). The sixth layer612is a second inter layer dielectric (ILD). The sixth layer612(ILD2) may be formed from substantially the same list of materials as the fourth layer608(ILD1).

The switching TFT310is illustrated in the sixth layer612(ILD2). The switching TFT310is an oxide TFT. The switching TFT310has a source (S1) and a drain (D1) disposed on top of the ILD2, i.e., sixth layer612. The source (S1) and drain (D1) are coupled to vias in the sixth layer612to a conductive channel (IGZO), in this example the conductive channel formed from indium gallium zinc oxide (IGZO), but other materials may be equally suitable. The conductive channel (IGZO) is formed on the top of the fifth layer610(buffer2). A gate insulating (GI) material is formed on the conductive channel (IGZO) in the sixth layer612(ILD2). The GI material is composed of silicon di-oxide (S102), polymethylsilsesquioxane (PMSG) or other suitable material. A gate G1material is formed on top of the gate insulating (GI) material. The gate (G1) is a metal conducting material, for example indium tin oxide (ITO), zinc oxide, indium gallium zinc oxide (IGZO), or other suitable material.

The driving TFT330is illustrated in third layer606through the sixth layer612(ILD2). The driving TFT330is an LTPS TFT. The driving TFT330has a source (S2) and a drain (D2) disposed on top of the ILD2, i.e., sixth layer612. The source (S2) and drain (D2) are coupled to vias in the sixth layer612and the fifth layer610, and a second source (S2)664and second drain (D2) disposed in the fifth layer610(buffer2). The vias extend further through the ILD1and into the GI layer to a conductive channel634of polycrystalline silicon (LTPS). The conductive channel634formed on the top surface of the second layer604(Buffer1). A gate (G2)632is formed in the fourth layer608(ILD1) above the conductive channel634and on top of the third layer606(GI). The G2material is composed of silicon di-oxide (SiO2), polymethylsilsesquioxane (PMSQ) or other suitable material. The third layer606(GI) being the gate insulating material between the conductive channel634and the gate (G2)632.

Turning now strictly toFIG. 6A, the capacitor320is formed in the third layer606(GI), the fourth layer608(ILD1) and the fifth layer610(Buffer2) adjacent the driving TFT330. The second source (S2)664extends in laterally in the fifth layer610(Buffer2) in a direction opposite from the second drain (D2). A via662extends from the second source (S2)664through the fourth layer608(ILD1) and into the third layer606(GI). The via662extends to a conductive channel640of polycrystalline silicon (LTPS). The conductive channel640is disposed on the top surface of the second layer604(Buffer1). The conductive channel634is isolated from the conductive channel640by the gate insulating material of the third layer606. A gate (G2)670is formed in the fourth layer608(ILD1) above the conductive channel640and on top of the third layer606(GI). The gate (G2)670is isolated from the gate (G2)632with the via662there between.

Turning now strictly toFIG. 6B, the capacitor320is formed in the fourth layer608(ILD1) and the fifth layer610(Buffer2) adjacent the driving TFT330. The second source (S2)664extends laterally in the fifth layer610(Buffer2) in a direction away from the second drain (D2). The gate (G2)670is formed in the fourth layer608(ILD1) and on top of the third layer606(GI). The resulting capacitor having one more mask reduction from the capacitor formed inFIG. 6A.

The benefit illustrated above inFIGS. 6A and 6Bis that one more mask reduction is possible and the formation of the sub-pixel circuit220is less complex.

FIGS. 7A and 7Billustrate examples of a sub-pixel circuit formed in a substrate, according to one or more embodiments. The switching TFT310illustrated is an oxide type and substantially similar to that described above with respect toFIGS. 6A and 6B.

Turning now strictly toFIG. 7A, the driving TFT330is illustrated in third layer606through the sixth layer612(ILD2). The driving TFT330is an LTPS TFT. The driving TFT330has a source (S2) and a drain (D2) disposed on top of the ILD2, i.e., sixth layer612. The source (S2) and drain (D2) are coupled to vias in the sixth layer612and the fifth layer610, and a second source (S2)664and second drain (D2) disposed in the fifth layer610(buffer2). The vias extend further through the ILD1and into the GI layer to a conductive channel634of polycrystalline silicon (LTPS). The conductive channel634formed on the top surface of the second layer604(Buffer1). A gate (G2)632is formed in the fourth layer608(ILD1) above the conductive channel634and on top of the third layer606(GI). The G2material is composed of silicon di-oxide (SiO2), polymethylsilsesquioxane (PMSQ) or other suitable material. The third layer603(GI) being the gate insulating material between the conductive channel634and the gate (G2)632.

The capacitor320is formed in the fourth layer608(ILD1) and the fifth layer610(Buffer2) within the driving TFT330. A second source (S2)760extends laterally in the fifth layer610(Buffer2) in a direction towards the second drain (D2) and above the gate (G2)632formed in the fourth layer608(ILD1). The resulting capacitor located in the driving TFT330reducing the footprint for the sub-pixel circuit220.

Turning now strictly toFIG. 7B, the driving TFT330is illustrated in the sixth layer612(ILD2). The driving TFT330is an oxide TFT. The driving TFT330has a source (S2)762and a drain (D2) disposed on top of the ILD2, i.e., sixth layer612. The source (S2) and drain (D2) are coupled to vias in the sixth layer612to a conductive channel (IGZO), in this example the conductive channel formed from indium gallium zinc oxide (IGZO), but other materials may be equally suitable. The conductive channel (IGZO) is formed on the top of the fifth layer610(buffer2). A gate insulating (GI) material742is formed on the conductive channel (IGZO) in the sixth layer612(ILD2). The GI material742is composed of silicon di-oxide (SiO2), polymethylsilsesquioxane (PMSQ) or other suitable material. A gate G2material is formed in on top of the gate insulating (GI) material742. The gate (G2) is a metal conducting material, for example indium tin oxide (ITO), zinc oxide, indium gallium zinc oxide (IGZO), or other suitable material.

The capacitor320is formed inside the driving TFT330. The source (S2)762extends along the top surface of the sixth layer612toward the drain (D2) and above the gate (G2) material to form the capacitor.

Advantageously, the storage capacitor320is formed nearer to the driving TFT330resulting in higher resolution by the reduction of pixel circuitry area.

FIGS. 8A and 8Billustrate examples of a sub-pixel circuit formed in a substrate, according to one or more embodiments. The switching TFT310illustrated is an oxide type and substantially similar to that described above with respect toFIGS. 6A and 6B. InFIG. 8A, the switching TFT310has a light shield810formed in the fifth layer610(buffer2) under the conductive channel (IGZO). InFIG. 8B, the switching TFT310has a light shield820formed in the fourth layer608(ILD1) under the conductive channel (IGZO). The light shields810/820are formed from a metal material. The metal is used under the oxide switching TFT310to improve the stability thereof.

The driving TFT330and capacitor320illustrated inFIGS. 8A and 8Bare substantially as described with respect to the driving TFT330discussed above with respect toFIG. 7A. The driving TFT330is an LTPS TFT and is disposed in third layer606through the sixth layer612(ILD2). The capacitor320is formed in the fourth layer608(ILD1) and the fifth layer610(Buffer2) within the driving TFT330. The resulting capacitor located in the driving TFT330reduces the footprint for the sub-pixel circuit220.

Advantageously, the storage capacitor320is formed near the driving TFT330resulting in higher resolution by the reduction of pixel circuitry area. Additionally as stated above, the light shield810/820improves the stability of the switching TFT310.

FIGS. 9A and 9Billustrate examples of a sub-pixel circuit formed in a substrate, according to one or more embodiments. The switching TFT310illustrated is an oxide type and substantially similar to that described above with respect toFIGS. 6A and 6B. The light shield810is formed in the fifth layer610(buffer2) under the conductive channel (IGZO). Additionally, a gate material (G2)934is formed in the fourth layer608(ILD1) under the light shield810. The gate material (G2)934is formed from a metal material. The light shields810and gate material (G2)934forms a second capacitor920under the switching TFT310.

Turning now strictly toFIG. 9A, the driving TFT330and the capacitor are as described above with respect toFIG. 7A. That is, the capacitor320is formed inside the driving TFT330for minimizing the sub-pixel circuit220.

Turning now strictly toFIG. 9B, the driving TFT330and the capacitor320are as described above with respect toFIG. 7B. The capacitor320is formed inside the driving TFT330for minimizing the sub-pixel circuit220. Additionally, a gate material (G2)936is formed in the fourth layer608(ILD1) under a source layer (S2)950. The gate material (G2)936is formed from a metal material. The source layer (S2)950and gate material (G2)936forms yet another capacitor991under the driving TFT330.

Advantageously, the storage capacitor320is formed near the driving TFT330resulting in higher resolution by the reduction of pixel circuitry area. The light shield810improves the stability of the switching TFT310. Additionally, a storage capacitor920is formed under the switching TFT310maintaining the footprint of the sub-pixel circuit220while increasing the storage capacity and allowing for a longer frame rate.

Pixel circuits consist of one driving TFT, at least one switching TFT and at least one storage capacitor. The switching TFT is connected to both the gate of the driving TFT and the storage capacitor. The storage capacitor size can be reduced by using oxide TFT as a switching TFT due to a two to three order of magnitude lower leakage current compared to LTPS TFT. However, the storage capacitor cannot be very small due to the voltage kick back. Shown above, the storage capacitor (Cst) proposed size is between about 1 fF and about 55 fF. The gate insulator thickness is between about 100 nm and about 200 nm. The TFT channel length is between about 0.5 μm and 3 μm. And the TFT channel width is between about 1 um and about 4 μm.

Device structures of the switching TFT shown above illustrated a storage capacitor and driving TFT having the storage capacitor formed between the polycrystalline silicon and gate metal. Alternately, the structure illustrates the storage capacitor formed between the gate and the source metals for reducing the number of masks during the production. In yet another alternative, a high resolution structure is provided where the storage capacitor is formed by overlapping gate and source metals of driving transistor. In yet another alternative, a high resolution structure is provided where the storage capacitor is formed under the oxide TFT. In yet other structures, a light shield formed of metal is added under oxide TFT. These structures provided an oxide TFT having a leakage current of less than 1E-12 (A) which allowed for a storage capacitor of about 7.5 pA×( 1/60 sec)/0.35V or about 36 fF.

Significant OLED panel power saving are achieved with variable refresh rate (VRR) [60 Hz 30 Hz, 15 Hz, 1 Hz]. However, refresh rates lower than 60 Hz can result in visual artifacts such as flicker and sudden change in brightness. The flicker and sudden change in brightness is minimized with a smaller leakage current through switching TFT connected to hold storage capacitor (C1) for data voltage holding in LCD and OLED. If the storage capacitor (C1) value needed is greater than 36 fF, an additional storage capacitor can be provided as seen inFIG. 9AandFIG. 9B. If the storage capacitor size is to be double (for example to 72 fF), the ΔVG will be about half, i.e., around 0.175V. Thus an improve uniformity by the reduction of VG variation is achieved. Additionally, if the leakage current is half, the required storage capacitor value will be half, i.e., around 18 fF. The in pixel storage capacitor area is reduced to about half of the previous size for the circuit allowing higher PPI by the reduction of the pixel size area.

These and other advantages may be realized in accordance with the specific embodiments described as well as other variations. It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other embodiments and modifications within the spirit and scope of the claims will be apparent to those of skill in the art upon reviewing the above description. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled. In the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.