Method for forming a semiconductor structure having a strained silicon layer

A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer. A low temperature silicon layer is then epitaxially grown with tensile strain, correlated to the tensile strain of the thin silicon layer, on the thin silicon layer using trisilane at a temperature preferably not in excess of 500 degrees Celsius. The resulting tensile strain, correlated to the strain of the thin silicon layer, is thus also correlated to the germanium concentration of the relaxed SiGe layer. The thickness of the low temperature silicon layer, using the trisilane at low temperature, is significantly greater than what would normally be expected for a silicon layer of that tensile strain.

FIELD OF THE INVENTION

The present invention relates generally to semiconductor processing, and more specifically, to forming a strained silicon layer.

RELATED ART

In semiconductor processing, strained semiconductor layers are used to form improved semiconductor devices. For example, compressive strained silicon germanium layers may be used to form improved p-channel devices where the strained silicon germanium allows for improved hole mobility. Similarly, tensile strained silicon layers may be used to form improved n-channel devices where the strained silicon allows for improved electron mobility.

In the case of strained silicon, one method used today for forming strained silicon includes forming a bilayer of strained silicon over silicon germanium. For example, this method includes providing a relaxed silicon germanium layer (which may be part of a bulk silicon germanium wafer or a silicon germanium layer formed over an insulator layer as part of a semiconductor-on-insulator wafer). A silicon layer is then formed on the silicon germanium layer, which, due to the mismatch in lattice constants between the silicon germanium layer and the silicon layer, results in a strained silicon layer. Devices are then formed in these layers. However, the use of this bilayer method introduces dopant diffusion issues related to the formation of shallow source/drain extension and source/drain regions which extend through the silicon layer into the silicon germanium layer. In addition, extended defects typically form along the heterointerface of the Si/SiGe bilayer during subsequent thermal processing which can cause electrical failures especially in short-channel devices. Furthermore, using silicon germanium as the body may cause problems due to self-heating issues of silicon germanium, which may degrade device performance. Therefore, although the strained silicon may improve carrier mobility for the devices, other problems may be introduced. Therefore, a need exists for an improved method for forming a strained silicon layer.

DETAILED DESCRIPTION OF THE DRAWINGS

As discussed above, the use of a bilayer method to obtain a strained silicon layer may result in problems. Therefore, one currently known technique forms a strained silicon layer directly on an insulator layer. In this manner, devices can be formed in a uniform material rather than in a bilayer and there is no interface between semiconductor layers to cause problems. One prior art method forms a strained silicon layer on a relaxed silicon germanium layer on a donor wafer and performs a layer transfer to transfer the strained silicon layer to a handle wafer such that, after exfoliation (i.e. the separation or cleaving of the handle wafer from the donor wafer), the handle wafer includes a dielectric layer with the strained silicon layer directly on the dielectric layer. In this prior art method, after exfoliation, the surface of the handle wafer is prepared (which includes removing any excess silicon germanium remaining after exfoliation). Furthermore, in this prior art method, the strain silicon layer may be epitaxially thickened. However, the strain and thickness of the strained silicon layer has to be balanced and limited in order to prevent defects. For example, as will be described below, as the strain of the strained silicon layer formed on the donor wafer is increased, the achievable thickness without dislocations of the strained silicon layer on the handle wafer decreases. Therefore, it may not be possible to achieve both the desired thickness and desired strain together.

In this layer transfer prior art method, after exfoliation, the strained silicon layer is epitaxially thickened using a silane precursor. This has to be performed at a high temperature (of at least 650 degrees Celsius) in order to achieve a sufficient quality epitaxial growth. Also, the silane cannot be performed at a lower temperature because the growth rate would be too low. However, due to the high temperature of at least 650 degrees Celsius, the critical thickness for the strained silicon layer on the handle wafer is limited, where the critical thickness refers to the maximum thickness achievable without losing strain through the formation of defects like dislocations. Therefore, as the temperature used in epitaxially thickening the strained silicon layer increases, the critical thickness decreases.

Furthermore, the problems introduced by the high temperature epitaxial growth is exacerbated as the strain of the silicon layer is increased. That is, the greater the strain, the better the device performance. However, as the strain is increased, the critical thickness is further decreased. Thicker strained layers, though, are needed in order to form high performance and high quality partially depleted devices, which are compatible with current technologies and provide ease of integration (such as by not requiring major changes at the circuit level). The strain in the epitaxially thickened silicon layer is controlled by the germanium concentration in the relaxed silicon germanium layer underlying the strained silicon layer prior to the layer transfer. That is, the greater the germanium concentration in the relaxed silicon germanium layer, the greater the strain in the subsequently formed strained silicon layer and epitaxially thickened silicon layer. The prior art method uses a 20-25% germanium concentration. If the germanium concentration is increased beyond 25%, the critical thickness of the epitaxially grown silicon layer after the layer transfer is overly limited due to the high temperature epitaxial growth, thus not allowing for thicknesses to reach or exceed 300 Angstroms. Therefore, the prior art is unable to achieve a thickness of at least 300 Angstroms, without dislocations, while being able to maintain the stress introduced by over 25% germanium content.

FIG. 1illustrates a semiconductor structure10having a donor wafer21in accordance with one embodiment of the present invention. Donor wafer21includes a silicon layer12, a graded silicon germanium (SiGe) layer14over silicon substrate12, and a SiGe buffer layer16over graded SiGe layer14. Silicon layer12has a relaxed strain. Graded SiGe is graded from silicon layer12at about a 0% germanium concentration up to a desired germanium concentration over a particular thickness. For example, in one embodiment, graded SiGe layer14is graded from about 0% germanium concentration to at least about 30% germanium concentration, where it may be graded, for example, at about 10% per micron. SiGe buffer layer16has a relaxed strain and a germanium concentration of the desired final germanium concentration of graded SiGe layer14. For example, SiGe buffer layer16may have a germanium concentration of at least about 30%, or, alternatively, at least about 40%. In one embodiment, SiGe buffer layer16has a thickness of at least about 1 micron, or, more preferably, at least about 2 microns.

Donor wafer21also includes an epitaxially grown strained silicon layer18over SiGe buffer layer16which has a tensile strain due to the mismatch of lattice constants between the silicon of silicon layer18and the SiGe of SiGe buffer layer16. Therefore, note that the germanium concentration of SiGe buffer layer16controls the amount of tensile strain in strained silicon layer18. Also, in one embodiment, strained silicon layer18has a thickness of at most about 200 Angstroms.

Donor wafer21also includes a dielectric layer20over strained silicon layer18. In one embodiment, dielectric layer20is an oxide layer formed by high temperature oxide (HTO). HTO is a deposition which, in one embodiment, is performed at a temperature of at least about 750 degrees Celsius, or, more preferably, at least about 800 degrees Celsius, using dichlorosilene and nitrous oxide (N2O) as precursors. In one embodiment, HTO is performed at a temperature between about 800 and 850 degrees Celsius.

FIG. 2illustrates donor wafer21receiving an implant22in order to form a cleave line24in SiGe buffer layer16. In one embodiment, implant22includes a hydrogen implant or a helium implant. The hydrogen or helium forms a defect layer which corresponds to cleave line24, such that a separation can occur at cleave line24. The dose and energy of implant22can be controlled, as known in the art, in order to control the location of cleave line24.

FIG. 3illustrates donor wafer21after bonding with a handle wafer30. Handle wafer30includes a mechanical substrate28(also referred to as a supporting substrate) and a dielectric layer26over mechanical substrate28. In one embodiment, dielectric layer26is an oxide layer and may therefore be referred to as a buried oxide (BOX). During the bonding process, dielectric layer26is brought into contact and chemically bonded with dielectric layer20of donor wafer21.

FIG. 4illustrates handle wafer30after exfoliation or cleaving (i.e. separation from donor wafer21). As described above, implant22creates a defect layer which forms cleave line24. For example, in one embodiment, the cleave line24includes bubbles and fissures caused by implant22. Cleaving may include applying a mechanical force to separate donor wafer21and handle wafer30along cleave line24due to the defects along cleave line24. Note that after exfoliation, a portion of SiGe buffer layer16remains on handle wafer30. Therefore, after exfoliation, surface preparation of handle wafer30may be performed where this may include removing the remaining portion of SiGe layer16to expose strained silicon layer18. This may be performed using a selective etch process, as known in the art. Therefore, a layer transfer of strained silicon layer18(also referred to as a thin silicon layer) has been performed from donor wafer21to handle wafer30where the strain of strained silicon layer18on handle wafer30correlates to the germanium concentration of SiGe buffer layer16on donor wafer21.

FIG. 5illustrates handle wafer30after epitaxially growing silicon on strained silicon layer18at a low temperature to form a low temperature silicon layer32. The strain of low temperature silicon layer32therefore correlates to the strain of strained silicon layer18(and thus to the germanium concentration of SiGe buffer layer16). In one embodiment, this epitaxial growth is performed by applying a trisilane precursor at a temperature of less than about 650 degrees Celsius. In one embodiment, the epitaxial growth is performed at a temperature of not greater than about 500 degrees Celsius, or, alternatively, not greater than about 400 degrees Celsius. In one embodiment, either hydrogen or helium is applied with the trisilane to form low temperature silicon layer32. In one embodiment, low temperature silicon layer32is grown to a thickness of at least about 300 Angstroms. Furthermore, since the use of the trisilane precursor allows for the use of a low temperature epitaxial deposition to form low temperature silicon layer32, the strain of strained silicon layer18is maintained throughout the thickness of low temperature silicon layer32without dislocations. In one embodiment, the biaxial tensile strain of strained silicon layer18that is maintained throughout the thickness of low temperature silicon layer32is at least about 1.2% (which correlates to the at least about 30% germanium concentration in SiGe buffer layer16). Note that the prior art method described above cannot achieve a strain of at least about 1.2% while allowing for a sufficient thickness of at least about 300 Angstroms.

In alternate embodiments, even thicker strained silicon layers may be needed. For example, low temperature silicon layer32may have a thickness of at least about 500 Angstroms or at least about 1000 Angstroms. Also, in one embodiment, low temperature silicon layer32may be grown to a thickness of at least three times thicker than strained silicon layer18. With the prior art method described above, if these thicknesses are desired (of, e.g., greater than 300 Angstroms, 500 Angstroms, 1000 Angstroms, or 3 times the thickness of strained silicon layer18), then a lower strain silicon layer has to be used in order to prevent dislocations during the epitaxial thickening of the strained silicon layer using silane. That is, in forming these thicknesses using the prior art method, the concentration of germanium in the silicon germanium layer cannot exceed 25%. Therefore, the use of trisilane at a low temperature of at most 650 degrees Celsius to form low temperature silicon layer32allows for both the higher concentration of germanium in SiGe buffer layer16(at least about 30% or at least about 40%) and the greater thickness of low temperature silicon layer32(e.g. in excess of about 300 Angstroms) than what would normally be expected. For example, low temperature silicon layer32can be grown to a thickness of greater than 500 Angstroms at a temperature of not greater than 500 degrees Celsius.

Also, in the prior art method discussed above, a tetraethylorthosilicate (TEOS) deposited oxide is used the dielectric layer formed over the relaxed silicon germanium layer prior to formation of the cleave line. However, since TEOS deposited oxide is deposited at a lower temperature, it is less dense as compared to HTO oxide. Since TEOS oxide is less dense, it is more susceptible to change during the thickening process used to epitaxially thicken the strained silicon layer. Therefore, the HTO oxide is better able to support the higher strain of low temperature semiconductor layer32as compared to the prior art method.

FIG. 6illustrates handle wafer30after formation of a transistor36in and on low temperature silicon layer32. Transistor36includes gate dielectric42over low temperature silicon layer32, a gate38over gate dielectric42, sidewall spacers adjacent gate38, and source/drain regions44and46in strained silicon layer32under spacers40and under at least a portion of gate dielectric42. Note that gate38is over a space between source/drain regions44and46. In the illustrated embodiment, transistor36is a partially depleted n-channel device formed in low temperature strained silicon layer32. The strain of layer32allows for improved performance of transistor36, and the ability to achieve a greater thickness for layer32allows for improved performance and the ability to be partially depleted. Furthermore, transistor36avoids the bilayer problems. For example, note that source/drain regions44and46do not extend across a layer boundary.

Note that transistor36is just an example of a semiconductor device that can be formed in and on layer32, and may be formed using known processes. Also, gate38can be any type of gate electrode, and each of gate dielectric42, gate38, and spacers40can include any number and type of appropriate materials. Also, source/drain regions can be formed using known methods.

Although the above embodiments have been described as applicable to the formation of n-channel transistors, such as transistor36, any device requiring a thicker body may benefit from the formation of low temperature silicon layer32.

Although the above descriptions were provided with respect to forming relaxed SiGe and a strained Si on the relaxed SiGe, other materials may be used to form other types of strained semiconductor materials directly on a dielectric, such as dielectric26of handle wafer30. For example, strained SiGe can be formed directly on silicon layer12of donor wafer21where the layer transfer would transfer the strained SiGe to handle wafer30. The strained SiGe could then be epitaxially thickened. Also, rather than strained SiGe in this example, strained SiC or strained Ge can be formed. In another alternate embodiment, strained Ge can be formed on the graded SiGe layer, where the strained Ge is transferred to the handle wafer.