SINGLE CORNER MIXED VOLTAGE NOISE IMPACT ON FUNCTION ANALYSIS

A method, system, and computer program product are disclosed for implementing enhanced noise impact on function (NIOF) analysis of an IC design having nets in multiple different variable voltage domains next to each other and modeling all multiple worst-case victim-aggressor voltage configurations in a single run leveraging noise abstracts characterized at a single voltage corner. The NIOF analysis enables accurately identifying incorrect victim switching or functional fails, effectively and efficiently providing design verification and the ability to sign-off an IC design with a single run, and enable modifying an integrated circuit design to fix NIOF failures, and fabricating an integrated circuit.

BACKGROUND

The present invention relates to integrated circuits, and more specifically, to noise impact on function (NIOF) analysis for integrated circuit (IC) designs.

NIOF analysis of an IC design is performed to identify noise coupling between a steady-state victim wire or net and switching aggressor nets that could cause functional fails or incorrect switching on the victim net. NIOF analysis is complicated in modern IC designs by mixed voltage conditions with wires or nets in different voltage domains next to each other, such as different voltages or voltage rails VDD1, VDD2, VDD3, etc. and the potential for the actual voltage of the voltage rails to vary across independent voltage ranges based on current processing needs. This creates multiple worst-case voltage conditions depending upon victim and aggressor voltage domains and the voltage domains changing across a range of potential voltage values. NIOF voltage-in voltage-out (ViVo) tables and noise abstracts characterized at the victim operation voltage are required for NIOF modeling of source and sink noise tolerance, propagation and drive strength. For example, using the traditional NIOF process flow with multiple different voltages VDD1, VDD2, VDD3addressing multiple worst case conditions requires three sets of ViVo tables and noise abstracts characterized at victim operation voltage domains, VDD1, VDD2, VDD3. While characterized libraries at the multiple voltage levels are possible, the library size and standard cell load time are significantly expanded. Further using the traditional NIOF process flow, multiple NIOF analysis runs are required to test each of the different worst case voltage corners, causing significantly increased analysis run time.

SUMMARY

Embodiments of the present disclosure are directed to enhanced noise impact on function (NIOF) analysis of an integrated circuit (IC) design having nets in multiple different variable voltage domains next to each other and including all multiple worst-case victim-aggressor voltage configurations in a single run leveraging noise abstracts characterized at a single voltage corner. A non-limiting example computer-implemented method for performing NIOF analysis for an IC design includes for each victim net, identifying a Victim minimum operating voltage (Victim Vmin) of a supply rail powering gates connected to the victim net, and determining a Victim Scaling Factor (VSF) to scale Victim Vmin to equal a characterized voltage (CV). The computer-implemented method includes for each aggressor net coupled to the victim net, identifying an Aggressor maximum operating voltage (Aggressor Vmax) of power supplies powering gates connected to the aggressor net, scaling the Aggressor Vmax by VSF to a Scaled Aggressor Vmax voltage to maintain a relative voltage ratio between victim and aggressor voltage nets. The NIOF analysis is performed with the victim at the characterized voltage CV and the aggressor nets coupled to the victim net at respective Scaled Aggressor Vmax voltages. The NIOF analysis enables accurately identifying incorrect victim switching or functional fails, effectively and efficiently providing design verification and the ability to sign-off an IC design with a single run. The NIOF analysis enables modifying an integrated circuit design to fix NIOF failures, and fabricating an integrated circuit.

Other disclosed embodiments include a computer system and computer program product for performing NIOF analysis for IC designs implementing features of the above-disclosed method.

DETAILED DESCRIPTION

In accordance with features of one or more disclosed embodiments, improved computer system performance for NIOF analysis is enabled for an IC design having nets in multiple different variable voltage domains next to each other. Conventional NIOF process flows for an IC design for different variable voltage domains and multiple worst-case voltage conditions greatly expands the library size required for storing multiple sets noise abstracts for multiple voltage levels and greatly expands required cell load time and requires multiple runs to be able to test each of the different worst case voltage corners. Features of embodiments disclosed enable enhanced NIOF analysis that is efficiently and effectively implemented with reduced memory requirements and reduced run time over conventional NIOF analysis.

In accordance with features of embodiments of the disclosure, computing system operations for NIOF analysis minimize required memory for storing NIOF ViVo tables and noise abstracts and other possible types of NIOF characterized or modeling files, and reduce system power requirements over traditional flow, with faster run time enabled. ViVo tables and noise abstracts, and other types of NIOF modeling files are characterized at a selected voltage level enabling enhanced NIOF modeling of source and sink noise tolerance, propagation and drive strength. Advantages of embodiments of the disclosure enable improved computer system performance for NIOF analysis, accurately identifying incorrect victim switching or functional fails, effectively and efficiently providing design verification and the ability to sign-off an IC design with a single run, and enable modifying an integrated circuit design to fix NIOF failures, and fabricating an integrated circuit.

With reference now toFIG.1, there is shown an example computing environment100. Computing environment100contains an example of an environment for the execution of at least some of the computer code involved in performing the inventive methods at block180for performing NIOF analysis for an IC design, such as a single corner mixed voltage NIOF analysis logic program182, a cell library, ViVo tables and noise abstracts184characterized at a single characterized voltage (CV)184and NIOF results to verify and fabricate an IC design186. In addition to block180, computing environment100includes, for example, computer101, wide area network (WAN)102, end user device (EUD)103, remote server104, public cloud105, and private cloud106. In this embodiment, computer101includes processor set110(including processing circuitry120and cache121), communication fabric111, volatile memory112, persistent storage113(including operating system122and block180, as identified above), peripheral device set114(including user interface (UI) device set123, storage124, and Internet of Things (IoT) sensor set125), and network module115. Remote server104includes remote database130. Public cloud105includes gateway140, cloud orchestration module141, host physical machine set142, virtual machine set143, and container set144.

In accordance with features of embodiments of the disclosure, the single corner mixed voltage NIOF analysis logic182together with the cell library, ViVo tables and noise abstracts184and the NIOF results186enable enhanced NIOF analysis, accurately and efficiently modeling all worst-case voltage configurations in a single run, identifying incorrect victim switching or functional fails, and providing design verification including the ability to sign-off an IC design with a single corner analysis.

Referring toFIG.2, a circuit200provides an example wire or net model illustrating example circuit components for NIOF analysis of an IC design in accordance with one or more disclosed embodiments. Circuit200includes a victim wire or net202and associated with the victim net202, a plurality of aggressor nets or aggressor nets204,206,208,210and a ground GND capacitance212representing coupling capacitance between the nets. The victim net202includes a source214and a sink216connected by a victim net, where the source214and sink216represent various logic gates, or inverters as shown. The aggressor nets204,206,208,210also include a source and a sink (not shown) connected by an aggressor net.

Noise coupling by the aggressor nets204,206,208,210to the victim net202(due to capacitance coupling) is represented by respective waveforms shown adjacent the victim net202. NIOF analysis of one or more disclosed embodiments, identifies possible noise coupling between a steady-state victim net202and switching aggressor nets204,206,208,210that could cause incorrect switching on the victim net or functional fails. As shown, aggressor nets208,210represent blockage aggressor nets that are outside a visible boundary of the IC design being modeled that are analyzed using an artificial boundary for circuit200and are assigned to a worst-case voltage of all design voltage domains for the circuit200. A single voltage corner characterization at the voltage CV is used to generate a noise abstract218for the victim source214and a noise abstract220for victim sink216in circuit200.

In accordance with one or more disclosed embodiments, NIOF analysis is performed for multiple worst-case victim-aggressor voltage configurations in a single run leveraging noise abstracts characterized at a single voltage corner. A minimum operating voltage connected to each victim net, such as victim net202in the IC design, is identified and a scaling factor is determined to scale the victim minimum voltage to a single characterized voltage CV. The single voltage CV used for the IC design is selected based on the different voltage domains in the IC design and is used for NIOF analysis of the victim nets. A single voltage corner characterization for the standard cell library for all gates and macros in the IC design, such as the illustrated inverters source214and sink216, is generated at the single characterized voltage CV. All NIOF ViVo tables and noise abstracts184for the IC design, such as shown in circuit200and stored in block180of computer101are characterized at the victim operation voltage equal to the single characterized voltage CV for effective NIOF modeling source and sink noise tolerance, propagation and drive strength.

In accordance with one or more disclosed embodiments, the NIOF analysis is performed for each of the aggressor nets capacitively coupled to the victim net, such as the illustrated aggressor nets204,206,208,210with a maximum aggressor voltage scaled to respective appropriate Scaled Aggressor Vmax values. A NIOF analysis of all victim nets202in the IC design can be performed in a single run including all multiple worst-case victim-aggressor voltage configurations leveraging noise abstracts, such as noise abstracts218,220characterized at a single voltage corner. Performing the NIOF analysis in accordance with one or more disclosed embodiments enables accurate analysis of noise impacts on victim nets with aggressors at different voltage levels and enables correctly identifying NIOF failures and design verification. Results of the NIOF analysis in accordance with one or more disclosed embodiments advantageously are used to verify an IC design, and are used to make design changes to fix NIOF problems and fabricate an IC design.

Referring toFIG.3, there is shown a flow chart illustrating example operations of a computer-implemented method300of one or more disclosed embodiments of NIOF analysis for an IC design. Method300may be implemented with computer101for example, with operations of method300included in the single corner mixed voltage NIOF analysis logic182, and used together with the cell library, ViVo tables and noise abstracts184using single corner characterization at the single characterized voltage (CV) and NIOF analysis results148. Method300is performed for NIOF analysis of an IC design, such as circuit200ofFIG.2, and for various complex integrated circuit designs with multiple different voltage domains including, for example, microprocessors, and application-specific integrated circuits (ASICs).

As shown inFIG.3, method300begins at a block302with NIOF analysis logic182of computer101identifying each victim net in the IC design. Each voltage domain has a minimum and maximum allowed operating voltage (Vmin and Vmax), which can be the same voltage value in some cases. At block304NIOF analysis logic182identifies for the victim net, a victim supply domain and a minimum operating voltage Vmin of the associated victim supply domain for the supply rail powering gates connected to victim net using the stored cell library, ViVo tables and noise abstracts184of computer system memory106. At block304the victim net is set to the minimum operating voltage value (Victim Vmin).

The cell library, ViVo tables and noise abstracts184are generated at a characterized voltage CV and stored in block180. The cell library, ViVo tables and noise abstracts184typically are characterized at the victim operation voltage. Using the voltage CV to pre-characterize the cell library, ViVo tables and noise abstracts184provides an effective basis for scaling victim-aggressor voltages to enable modeling multiple worst-case victim-aggressor voltage configurations with multiple different voltage domains.

As shown at block306NIOF analysis logic182determines a VSF to scale Victim Vmin of the victim net to the characterized equal CV, (in this case VSF=CV/Victim Vmin). In one embodiment, the identified scaling factor VSF is used to scale a maximum operating voltage of each aggressor net having a noise impact on the victim net to maintain an appropriate voltage ratio between the scaled victim and aggressor voltages.

It should be understood that embodiments of the disclosure are not limited to the illustrated example shown at block306where VSF is set equal CV/Victim Vmin. In other embodiments, the scaling factor VSF may implemented with a non-linear function design. For example at block306, a scaling factor VSF identified by a non-linear function design may be used to adjust the minimum operating voltage value Victim Vmin toward the characterized voltage CV.

The victim and aggressor voltage ratio provided by VSF enables effectively modeling multiple worst-case victim-aggressor voltage configurations at the single voltage corner CV. Using traditional NIOF flows, addressing multiple worst case conditions requires multiple sets of noise abstracts respectively characterized at the multiple different voltage domains in the IC design. Operations of method300performed by the single corner mixed voltage NIOF analysis logic182, uses the cell library, ViVo tables and noise abstracts184generated by voltage corner characterization at the characterized voltage CV, avoiding the need for multiple sets of noise abstracts respectively characterized the multiple different voltage domains of traditional flow processes. NIOF analysis logic182performs method300using the pre-characterized ViVo tables and noise abstracts184at CV, avoids the need for the expanded library size and expanded cell load time required for traditional NIOF flows.

Each potential aggressor net having possible noise impact on the victim net is identified at block308. NIOF analysis logic182performs method300at block310completing the operations at blocks312and314for each aggressor net. At block312, an aggressor supply domain is identified from aggressor nets powering gates connected to the aggressor net and then a maximum voltage Vmax for the aggressor net is identified from the voltage range of the associated aggressor supply domain. At block312, the aggressor net is set to the identified maximum voltage (Aggressor Vmax). As shown at block314, a Scaled Aggressor Vmax value is determined by scaling the Aggressor Vmax value by VSF to provide the voltage used in actual simulation and maintain a relative voltage ratio between the victim and aggressor nets. In one embodiment, In one embodiment, where the VSF for victim and aggressor can be both linear and identical to ensure balanced voltage scaling for both types of nets. In other embodiments, the VSF scaling function can be non-linear, or can be designed to scale victim and aggressor nets to different relative voltages. One example includes modifying the aggressor's VSF scaling by some additional incremental voltage value in order to add additional pessimism to the model by artificially increasing the aggressor voltage to be higher than the victim's voltage. In this example the aggressor's VSF might look like this VSF=CV/Victim Vmin+Vpessimism-modifier.

NIOF analysis logic182performs NIOF analysis of each victim net with the victim net at voltage CV and the aggressor nets at their respective scaled Aggressor Vmax voltage values at block316. For example, inFIG.5, an example table500is shown with example victim and aggressor voltage domains and scaled voltages. InFIG.5, a scaled voltage for a victim net502is set to the voltage CV by scaling the minimum victim voltage VDD by VSF and for aggressors504,508,510, VSF is used to scale the illustrated respective maximum voltages VDD2, VDD3, Vunknown−max of the aggressors.

Using VSF to scale the minimum operating voltage of the victim net and the maximum operating voltage of respective aggressor nets of method300maintains a relative voltage ratio between the victim and aggressor nets, and enables performing NIOF analysis of each victim net in a single run with multiple worst-case victim-aggressor voltage configurations, leveraging noise abstracts characterized at the characterized voltage CV.

At block316, NIOF analysis logic182performs NIOF analysis of the victim net at the relative voltage CV and the aggressor nets having a noise impact on the victim net at the scaled Aggressor Vmax values. NIOF analysis logic182effectively identifies NIOF failures at block316.

At block316, NIOF analysis logic182performs NIOF analysis for each victim net and identified aggressor nets to the victim net in the IC design. In one run of method300at block316, a first net is identified as a victim, and nearby nets having possible noise impact on the victim net are identified as aggressors. In another run of method300, an aggressor net to the first victim net can be identified as a next victim, and the first victim net becomes an aggressor net to the identified next victim net. That is, the method300can be performed or re-run for each net including identified victim nets and aggressor nets in the IC design. At block318, NIOF analysis logic182uses identified NIOF failures results at block316to verify an integrated circuit design and to make design changes to fix NIOF problems and fabricate an integrated circuit.

Method300provides accurate NIOF analysis of noise impacts on victim nets with aggressors at multiple different voltage levels, accurately identifying NIOF failures. NIOF analysis performed at block316enables a single run for signing off the IC design, enabling design verification without adding excessive pessimism defining nets as the worst possible voltage differentials and without characterizing noise abstracts at multiple different voltage corners.

FIGS.4A and4Btogether show a flow chart illustrating example operations of a computer-implemented method400to identify a supply domain for each net including victims and aggressors in the IC design, as shown at blocks304,312inFIG.3of method operations in method300. With multiple wiring layers and multiple voltage domains in a circuit design, identifying a voltage domain for a net can be challenging. As shown inFIG.4A, method400begins at a block402with NIOF analysis logic182identifying for each net, victim nets and potential aggressor nets to the victim net in the IC design. At block404, NIOF analysis logic182performs checking to find a source gate and associated pin for the net. Then NIOF analysis logic182determines if the source gate is a single voltage domain block at decision block406. When a single voltage domain block is identified for the source gate, the net is assigned to the source gate voltage domain at block408.

Otherwise, for multiple voltage domains or situations where the source gate's voltage is unknown, NIOF analysis logic182performs checking to determine if the source gate has a defined pin to voltage domain mapping using the stored cell library184at decision block410. If yes, NIOF analysis logic182assigns the net voltage based upon pin to voltage domain mapping at block412.

Without pin to voltage domain mapping, NIOF analysis logic182performs checking to identify all sink gates and associated pins for the nets at block414and, as shown at block416NIOF analysis logic182iterates through the sink gates until the net voltage is determined or all sink gates are traversed. Operations of method400at block416are accomplished for example by operations described with respect to blocks418-428shown inFIG.4B.

Referring toFIG.4B, at block418method400identifies each sink gate and associated pin. NIOF analysis logic182determines if the sink gate is a single voltage domain block at decision block420. When NIOF analysis logic182identifies a single domain block for the sink gate, the net is assigned to the sink gate voltage domain at block422. Otherwise, for multiple voltage domain blocks, NIOF analysis logic182performs checking to determine if the sink gate has a defined pin to voltage mapping at decision block424. If yes, the net voltage domain is assigned based upon the pin to voltage domain mapping at block426. Without pin to voltage domain mapping, NIOF analysis logic182performs checking to determine if all sink gates are traversed at decision block428. If all sink gates have not been traversed operations return to block418and continue. Without pin to voltage domain mapping, an aggressor net voltage domain cannot be definitively assigned and more sink gates must be checked. When all sink gates have been traversed, NIOF analysis logic182performs checking to determine whether all source and sink gates and associated pins have a defined voltage domain at decision block430. If yes, at block432NIOF analysis logic182assigns the net to the worst of all source and sink gate voltage domains, where the worst voltage domain (identified as the domain with the lowest possible minimum voltage of all observed voltage domains) is assigned to a victim net, and the worst voltage domain (identified at the domain with the highest possible maximum voltage) is assigned to an aggressor net. For any nets where one or more source or sink gates and associated pins do not having a defined voltage domain, the net is identified as being in an undefined voltage domain at block434. The undefined voltage domain is designed to assign the worst of all possible design voltage domains to the victim and or aggressor net.

FIG.5illustrates an example table500of example victim and aggressor voltage domains and scaled voltages in accordance with one or more disclosed embodiments of NIOF analysis for an integrated circuit design. As shown, a victim net502has a voltage domain VDD, and because it is a victim wire, we have assigned it the minimum allowed VDD voltage value which we refer to as Victim Vmin. The minimum voltage Victim Vmin for victim502is scaled by VSF to equal CV. An aggressor net504has an example voltage domain VDD2, and because it is an aggressor net, we assign it the maximum allowed VDD2voltage value which we refer to as Vmax. The scaled voltage for aggressor net504is VDD2scaled by VSF. A blockage aggressor net508has an example voltage domain VDD3equal to a maximum blockage voltage Vblk-max. The scaled voltage for aggressor net508is VDD3scaled by VSF. An undefined or unknown aggressor net510, for example outside the IC design or with source/sink gates with unknown voltage domain pin mappings, has an example maximum unknown voltage Vunknown−max. The scaled voltage for aggressor net510is Vunknown−max scaled by VSF. Table500illustrates example victim net502scaled to the voltage CV, and the aggressor voltages VDD2, VDD3, Vunknown−max are scaled by VSF to maintain an appropriate voltage ratio between victim and aggressor voltage nets.