Semiconductor structure comprising regions having an isolation trench with a stepped bottom surface therebetween and method of forming the same

A semiconductor structure includes a substrate having a first region and a second region around the first region. A first fin structure is disposed within the first region. A second fin structure is disposed within the second region. A first isolation trench is disposed within the first region and situated adjacent to the first fin structure. A first trench isolation layer is disposed in the first isolation trench. A second isolation trench is disposed around the first region and situated between the first fin structure and the second fin structure. The bottom surface of the second isolation trench has a step height. A second isolation layer is disposed in the second isolation trench.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of semiconductor technology, in particular to a semiconductor structure and a manufacturing method thereof.

2. Description of the Prior Art

It is known that in an advanced semiconductor manufacturing process, in order to improve the operating efficiency of the device, epitaxial SiGe layers are usually formed in the drain and source regions of the PMOS transistor.

However, in an integrated circuit with a very small pitch, for example, a static random access memory macro (SRAM macro), especially two adjacent pull-up transistors or PL transistors in an SRAM cell, SiGe bridge may occur, causing short circuit problems.

SUMMARY OF THE INVENTION

It is one object of the present invention to provide an improved semiconductor structure and its manufacturing method to solve the above-mentioned shortcomings or deficiencies of the prior art.

One aspect of the invention provides a semiconductor structure including a substrate having a first region and a second region around the first region; at least one first fin structure disposed within the first region; at least one second fin structure disposed within the second region; a first isolation trench disposed within the first region and situated adjacent to the at least one first fin structure; a first trench isolation layer in the first isolation trench; a second isolation trench disposed around the first region and situated between the at least one first fin structure and the at least one second fin structure, wherein a bottom surface of the second isolation trench has a step height; and a second isolation layer in the second isolation trench.

According to some embodiments, the bottom surface comprises a first surface within the first region and a second surface within the second region, wherein the first surface is lower than the second surface.

According to some embodiments, a top surface of the first trench isolation layer is coplanar with a top surface of the second trench isolation layer.

According to some embodiments, the first region is a PMOS region and the second region is an NMOS region.

According to some embodiments, the second region surrounds the first region.

According to some embodiments, a top surface of the at least one first fin structure is lower than a top surface of the at least one second fin structure.

According to some embodiments, the semiconductor structure further comprises: a first gate disposed on the at least one first fin structure; a first source region disposed on the at least one first fin structure and adjacent to the first gate; and a first drain region disposed on the at least one first fin structure and adjacent to the first gate.

According to some embodiments, the first source region and the first drain region comprise an epitaxial SiGe layer.

According to some embodiments, the semiconductor structure further comprises: a second gate disposed on the at least one second fin structure; a second source region disposed on the at least one second fin structure and adjacent to the second gate; and a second drain region disposed on the at least one second fin structure and adjacent to the second gate.

According to some embodiments, the second source region and the second drain region comprise an epitaxial SiP layer.

Another aspect of the invention provides a method of forming a semiconductor structure. A substrate having a first region and a second region around the first region is provided. The substrate is etched to form a recess in the first region. A trench isolation process is performed to form a first isolation trench within the first region, at least one first fin structure within the first region, a second isolation trench around the first region, at least one second fin structure within the second region, a first trench isolation layer in the first isolation trench, and a second isolation layer in the second isolation trench. The second isolation trench is situated between the at least one first fin structure and the at least one second fin structure. The bottom surface of the second isolation trench has a step height.

According to some embodiments, the bottom surface comprises a first surface within the first region and a second surface within the second region, wherein the first surface is lower than the second surface.

According to some embodiments, a top surface of the first trench isolation layer is coplanar with a top surface of the second trench isolation layer.

According to some embodiments, the first region is a PMOS region and the second region is an NMOS region.

According to some embodiments, the second region surrounds the first region.

According to some embodiments, a top surface of the at least one first fin structure is lower than a top surface of the at least one second fin structure.

According to some embodiments, the method further comprises: forming a first gate on the at least one first fin structure; forming a first source region on the at least one first fin structure and adjacent to the first gate; and forming a first drain region on the at least one first fin structure and adjacent to the first gate.

According to some embodiments, the method further comprises: forming an epitaxial SiGe layer on the first source region and the first drain region.

According to some embodiments, the method further comprises: forming a second gate on the at least one second fin structure; forming a second source region on the at least one second fin structure and adjacent to the second gate; and forming a second drain region on the at least one second fin structure and adjacent to the second gate.

According to some embodiments, the method further comprises: forming an epitaxial SiP layer on the second source region and the second drain region.

DETAILED DESCRIPTION

In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

Please refer toFIG. 1andFIG. 2.FIG. 1is a top view of a semiconductor structure according to an embodiment of the present invention.FIG. 2is a schematic cross-sectional view taken along the line I-I′ inFIG. 1. As shown inFIG. 1andFIG. 2, the semiconductor structure1includes a substrate100, for example, a silicon substrate, having a first region R1and a second region R2around the first region R1. According to an embodiment of the present invention, the second region R2may surround the first region R1.

According to an embodiment of the present invention, the semiconductor structure1may be, for example, a part of a static random access memory, wherein the first region R1may be the area as indicated by the dotted line. For example, the first region R1includes at least two PMOS pull-up transistors PL1and PL2. According to an embodiment of the present invention, the first region R1may be a PMOS region, that is, only PMOS transistors are provided in the first region R1, and the second region R2may be an NMOS region, that is, only NMOS transistors are provided in the second region R2.

InFIG. 1, four active regions AA1to AA4extending along the reference Y axis and four gates G1to G4extending along the reference X axis are illustrated. According to an embodiment of the present invention, the gate G1crosses the active area AA2to form a PMOS pull-up transistor PL1, and the gate G2crosses the active area AA3to form a PMOS pull-up transistor PL2. Between the active regions AA1to AA4is a shallow trench isolation (STI) region110.

As shown inFIG. 2, the semiconductor structure1includes at least one first fin structure F1disposed in the first region R1, and at least one second fin structure F2disposed in the second region R2. In the first region R1, a first isolation trench T1is provided adjacent to the first fin structure F1. A first trench isolation layer IM1such as a silicon oxide layer, is provided in the first isolation trench T1. Around the first region R1, a second isolation trench T2is provided. The second isolation trench T2is located between the first fin structure F1and the second fin structure F2. A second trench isolation layer IM2, such as a silicon oxide layer, is provided in the second isolation trench T2.

According to an embodiment of the present invention, the bottom surface S of the second isolation trench T2has a step height H. According to an embodiment of the present invention, the bottom surface S of the second isolation trench T2includes a first surface S1in the first region R1and a second surface S2in the second region R2, and the first surface S1is lower than the second surface S2, thereby constituting the step height H at the interface between the first region R1and the second region R2. According to an embodiment of the present invention, for example, the step height H is about 30-100 angstroms, but it is not limited thereto.

According to an embodiment of the present invention, the top surface ST1of the first trench isolation layer IM1and the top surface ST2of the second trench isolation layer IM2are coplanar. According to an embodiment of the present invention, the top surface FST1of the first fin structure F1is lower than the top surface FST2of the second fin structure F2.

According to an embodiment of the present invention, as shown inFIG. 1, the gate G1of the semiconductor structure1may be disposed on the first fin structure F1. According to an embodiment of the present invention, a first source region SD1adjacent to the gate G1, for example, a P+doped region, is provided on the first fin structure F1. According to an embodiment of the present invention, a first drain region DD1adjacent to the gate G1, for example, a P+doped region, is provided on the first fin structure F1. The gate G1, the first source region SD1and the first drain region DD1may constitute the PMOS pull-up transistor PL1. According to an embodiment of the present invention, the first source region SD1and the first drain region DD1include an epitaxial SiGe layer SG1, which has a height h of about 5-25 nm above the top surface ST1of the first trench isolation layer EVIL but not limited to this. The distance W between the epitaxial SiGe layer SG1and the adjacent epitaxial SiGe layer SG2on the top surface ST1of the first trench isolation layer IM1is at least 20 nm, for example, between 20 and 60 nm. Therefore, the semiconductor structure1of the present invention can effectively avoid the short circuit problem caused by the SiGe bridge.

According to an embodiment of the present invention, the gate G2of the semiconductor structure1may be disposed on the second fin structure F2. According to an embodiment of the present invention, a second source region SD2adjacent to the gate G2, for example, an N+doped region, is provided on the second fin structure F2. According to an embodiment of the present invention, a second drain region DD2adjacent to the gate G2, for example, an N+doped region, is provided on the second fin structure F2. The gate G2, the second source region SD2and the second drain region DD2can constitute an NMOS transistor. According to an embodiment of the present invention, the second source region SD2and the second drain region DD2include an epitaxial SiP layer SPE.

FIG. 3toFIG. 15illustrate a method of forming a semiconductor structure. As shown inFIG. 3, first, a substrate100, such as a silicon substrate, is provided with a first region R1and a second region R2around the first region R1. According to an embodiment of the present invention, the second region R2may surround the first region R1. According to an embodiment of the present invention, the first region R1may be a PMOS region, that is, only PMOS transistors are provided in the first region R1, and the second region R2may be an NMOS region, that is, only NMOS transistors are provide in the second region R2.

Subsequently, using a lithographic process and etching process, the substrate100in the first region R1is etched to form a recess RA in the first region R1, and a step height RH is formed at the interface between the first region R1and the second region R2. According to an embodiment of the present invention, for example, the step height RH is about 30-100 angstroms, but it is not limited thereto. A hard mask layer HM is then deposited on the substrate100in a blanket manner. The hard mask layer HM may include a silicon nitride layer, but is not limited thereto.

Next, as shown inFIG. 4toFIG. 8, a trench isolation process is performed. As shown inFIG. 4, a lithographic process and an etching process may be performed to etch the hard mask layer HM and the substrate100in the predetermined area, and a first isolation trench T1is formed in the first area R1, and a second isolation trench T2is formed around the first area R1. Concurrently, at least one first fin structure F1is formed in the first region R1, and at least one second fin structure F2is formed in the second region R2. The second isolation trench T2is located between the first fin structure F1and the second fin structure F2. Between two fin-like structures F2. According to an embodiment of the present invention, for example, the top surface FST1of the first fin structure F1is lower than the top surface FST2of the second fin structure F2by about 30-100 angstroms.

According to an embodiment of the present invention, the bottom surface S of the second isolation trench T2has a step height H. According to an embodiment of the present invention, the bottom surface S of the second isolation trench T2includes a first surface S1in the first region R1and a second surface S2in the second region R2, and the first surface S1is lower than the first surface S1, thereby forming a step height H at the interface between the first region R1and the second region R2. According to an embodiment of the present invention, for example, the step height H is about 30-100 angstroms, but it is not limited thereto.

As shown inFIG. 5, a chemical vapor deposition (CVD) process is then performed to deposit an insulating layer102, such as a silicon oxide layer, on the substrate100in a blanket manner. According to an embodiment of the present invention, the insulating layer102covers the hard mask layer HM, and fills the first isolation trench T1and the second isolation trench T2.

As shown inFIG. 6, the insulating layer102is then subjected to a planarization process, for example, a chemical mechanical polishing (CMP) process, to polish the insulating layer102until the top surface of the hard mask layer HM in the second region R2is first exposed. At this point, the top surface of the hard mask layer HM in the first region R1may still be covered by the insulating layer102.

As shown inFIG. 7, an etch-back process is then performed, using dry etching or wet etching to etch away the insulating layer102of a predetermined thickness, revealing the top surface of the hard mask layer HM in the first region R1, so that a first trench isolation layer IM1is formed in the first isolation trench T1, and a second trench isolation layer IM2is formed in the second isolation trench T2. According to an embodiment of the present invention, the top surface ST1of the first trench isolation layer IM1and the top surface ST2of the second trench isolation layer IM2are coplanar.

As shown inFIG. 8, an etching process, such as wet etching, is then used to remove the hard mask layer HM to reveal the top surface FST1of the first fin structure F1and the top surface FST2of the second fin structure F2. According to an embodiment of the present invention, the top surface ST1of the first trench isolation layer IM1and the top surface ST2of the second trench isolation layer IM2are higher than the top surface FST2of the second fin structure F2, and the top surface FST2of the second fin structure F2is higher than the top surface FST1of the first fin structure F1. The height difference ht between the top surface FST2of the second fin structure F2and the top surface FST1of the first fin structure F1is about 30-100 angstroms, but is not limited thereto.

As shown inFIG. 9, an ion implantation process is then performed to form ion wells, such as P-type wells or N-type wells (not shown) in the substrate100. Then, a cleaning process is performed. The above cleaning process may consume part of the thickness of the first trench isolation layer IM1and the second trench isolation layer IM2, so that the top surface ST1of the first trench isolation layer IM1and the top surface ST2of the second trench isolation layer IM2will be closer to the top surface FST2of the second fin structure F2, but still higher than the top surface FST1of the first fin structure F1. According to an embodiment of the present invention, the height difference ht between the top surface ST1of the first trench isolation layer IM1and the top surface FST1of the first fin structure F1is about 30-100 angstroms, but is not limited thereto. In addition, after the above-mentioned cleaning process is completed, the upper corners of the first trench isolation layer IM1will be rounded.

As shown inFIG. 10, an oxidation process is then performed to form a gate oxide layer GOX1and a gate oxide layer GOX2on the top surface FST1of the first fin structure F1and the top surface FST2of the second fin structure F2, respectively. According to an embodiment of the present invention, the gate oxide layer GOX1and the gate oxide layer GOX2may include silicon oxide layers, but are not limited thereto. According to one embodiment, the gate oxide layer GOX1and the gate oxide layer GOX2may be formed of the same material. According to one embodiment, the gate oxide layer GOX1and the gate oxide layer GOX2may be formed of different materials.

As shown inFIG. 11, a polysilicon layer POL is then deposited on the substrate100in a blanket manner.

As shown inFIG. 12, the polysilicon layer POL is patterned by using a lithographic process and an etching processes to form a gate G1on the first fin structure F1and a gate G2on the second fin structure F2(as shown inFIG. 1). Since the polysilicon layer POL on this cross-section is removed, only the outline of the gate G2is shown by dotted lines in the figure. Subsequently, spacers (not shown) can be formed on the gate G1and the gate G2.

As shown inFIG. 13, a recessed region RE1and a recessed region RE2adjacent to the gate G1(not shown) are then formed on the first fin structures F1in the first region R1. The method of forming the recessed region RE1and the recessed region RE2on the first fin structures F1may comprise wet etching, but is not limited thereto. According to an embodiment of the present invention, the recessed region RE1and the recessed region RE2are separated by the first trench isolation layer IM1. According to an embodiment of the present invention, at this point, the top surface ST1of the first trench isolation layer IM1and the top surface ST2of the second trench isolation layer IM2are still coplanar.

As shown inFIG. 14, an epitaxial process is then performed to form an epitaxial SiGe layer SG1and an epitaxial SiGe layer SG2in the recessed region RE1and the recessed region RE2in the first region R1, respectively. For example, the epitaxial SiGe layer SG1and the epitaxial SiGe layer SG2can be formed by an organometallic vapor phase epitaxy method, but are not limited thereto. During the above epitaxial process, the second region R2can be masked. The distance W between the epitaxial SiGe layer SG1and the adjacent epitaxial SiGe layer SG2on the top surface ST1of the first trench isolation layer IM1is at least 20 nm, for example, between 20 and 60 nm. Therefore, the semiconductor structure1of the present invention can effectively avoid the short circuit problem caused by the SiGe bridge.

As shown inFIG. 15, the epitaxy process is performed to form an epitaxial SiP layer SPE on the second fin structure F2in the second region R2.