Bidrectional shifter register and method of driving same

A bidirectional shift register includes first, second, third and four control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3 and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having a first input node and a second input node, where the plurality of shift register stages is grouped into a first section and a second section, wherein the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1 and Bi2, respectively, and the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3 and Bi4, respectively.

FIELD OF THE INVENTION

The present invention relates generally to a shift register, and more particularly, to a bidirectional shift register with four control signals.

BACKGROUND OF THE INVENTION

A liquid crystal display (LCD) includes an LCD panel formed with liquid crystal cells and pixel elements with each associating with a corresponding liquid crystal cell. These pixel elements are substantially arranged in the form of a matrix having gate lines in rows and data lines in columns. The LCD panel is driven by a driving circuit including a gate driver and a data driver. The gate driver generates a plurality of gate signals (scanning signals) sequentially applied to the gate lines for sequentially turning on the pixel elements row-by-row. The data driver generates a plurality of source signals (data signals), i.e., sequentially sampling image signals, simultaneously applied to the data lines in conjunction with the gate signals applied to the gate lines for aligning states of the liquid crystal cells on the LCD panel to control light transmittance therethrough, thereby displaying an image on the LCD.

In such a driving circuit, a bi-directional shift register is usually utilized in the gate driver to generate the plurality of gate signals for sequentially driving the gate lines, so as to allow a positive or a reverse display image. Typically, a plurality of 2-to-2 bi-directional control circuits is employed in the bi-directional shift register to control the scanning direction, forward or backward, of the plurality of gate signals.

FIG. 1illustrates a conventional bi-directional shift register, where the 2-to-2 bi-directional control circuit has two input terminals P and N, and two output terminals D1and D2, and are operably controlled by two control nodes Bi and XBi. The control nodes Bi and XBi are two DC signals set to have opposite polarities, such as a high level voltage and a low level voltage.

FIG. 2shows a conventional two-way shift register with a set of shift register circuits S1to SN. The control signal lines Bi1and Bi2receive two complementary control voltage signals directed to each control node Bi and XBi. When the control node Bi receives, from the control signal line Bi1, a control voltage signal of a high level voltage level, the control node XBi would complementary receive, from the control signal line Bi2, a control voltage signal of a low level voltage level. Likewise, when the control node XBi receives, from the control signal line Bi2, a control voltage signal of a high level voltage level, the control node Bi would complementary receive, from the control signal line Bi1, a control voltage signal of a low level voltage level.

However, over a period of time, transistors in shift register circuits S1to SNconnected to Bi or XBi would deteriorate due to electrical degradation caused by the high level voltage. Such deterioration or degradation of electrical characteristics, particularly for amorphous silicon (a-Si) components, is likely to lead to a circuit breakdown or operation failure.

SUMMARY OF THE INVENTION

The present invention, in one aspect, relates to a bidirectional shift register. In one embodiment, the bidirectional shift register comprises first, second, third and four control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3and Bi4, respectively, and a plurality of shift register stages electrically coupled in serial, each shift register stage having a first input node, a second input node and an output node, wherein the first through K-th shift register stages of the plurality of shift register stages is grouped into a first section and the (K+1)-th through M-th shift register stages of the plurality of shift register stages is grouped into a second section such that each of the first and second sections comprises a corresponding number of consecutive shift register stages, wherein K is an integer greater than 1 but less than the number, M, of the plurality of shift register stages, wherein the first and second input nodes of each shift register stage in the first section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1and Bi2, respectively, and wherein the first and second input nodes of each shift register stage in the second section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3and Bi4, respectively.

In one embodiment, each shift register stage further has third and fourth input nodes configured to receive a first clock signal, CK, and a second clock signal, XCK, respectively, wherein each clock signal comprises an AC signal characterized with a period, TCKand a phase, and the periods of the first and second clock signals are substantially identical, and the phases of the first and second clock signals are substantially reversed, wherein the period TCKis much shorter than a gate line period, TGL, defined by the active scanning time during a frame.

The first and second control signals Bi1and Bi2, and the third and fourth control signals Bi3and Bi4are adapted for respectively controlling the first and second sections of the shift register in a forward scanning operation or a backward scanning operation.

During the forward scanning operation, each of the first and third control signals Bi1and Bi3comprises an AC signal characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage, wherein the duration T satisfies T=(TGL/2+2S) and 2S≧TCK, wherein S is a half of an overlap time 2S between the high level voltage duration of the first control signal Bi1and the high level voltage duration of the third control signal Bi3, and the third control signal Bi3is shifted from the first control signal Bi1by TGL/2 such that the high level voltage duration of the first control signal Bi1and the high level voltage duration of the third control signal Bi3are overlapped by 2S, and the rising time of the first control signal Bi1is earlier than the beginning of the active scanning time during a frame by a half of the overlap time 2S and the falling time of the third control signal Bi3is later than the end of the active scanning time during a frame by a half of the overlap time 2S. Each of the second and fourth control signals Bi2and Bi4comprises a DC signal with a low level voltage.

During the backward scanning operation, each of the first and third control signals Bi1and Bi3comprises a DC signal with a low level voltage, and each of the second and fourth control signals Bi2and Bi4comprises an AC signal characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage, wherein the duration T satisfies T=TGL/2+2S, and the second control signal Bi2is shifted from the fourth control signal Bi4by TGL/2 such that the rising time of the fourth control signal Bi4is earlier than the beginning of the active scanning time during a frame by a half of the overlap time 2S and the falling time of the second control signal Bi2is later than the end of the active scanning time during a frame by a half of the overlap time 2S.

In one embodiment, each shift register stage comprises a first transistor T1having a gate electrically coupled to the output node of its immediately prior shift register stage, a drain electrically coupled to the first input node, and a source; a second transistor T2having a gate electrically coupled to the output node of its immediately next shift register stage, a drain electrically coupled to the source of the first transistor T1, and a source electrically coupled to the second input node; a third transistor T3having a gate electrically coupled to the source of the first transistor T1, a drain electrically coupled to the third input node, and a source electrically coupled to the output node; and a control circuit electrically coupled to the first, second and third transistors T1, T2and T3.

In one embodiment, the control circuit has a fourth transistor T4having a gate, a drain electrically coupled to the source of the third transistor T3, and a source electrically coupled to a voltage supply for receiving a reference voltage, VSS, therefrom; a fifth transistor T5having a gate electrically coupled to the source of the first transistor T1, a drain electrically coupled to the gate of the fourth transistor T4, and a source electrically coupled to the voltage supply; a sixth transistor T6having a gate electrically coupled to the fourth input node, a drain electrically coupled to the output node, and a source electrically coupled to the source of the fourth transistor T4; a seventh transistor T7having a gate electrically coupled to the gate of the fourth transistor T4, a drain electrically coupled to the gate of third transistor T3, and a source electrically coupled to the source of the third transistor T3; a first capacitor C1electrically coupled between the gate of the third transistor T3and the output node; and a second capacitor C2electrically coupled between the third input node and the gate of the seventh transistor T7.

In another embodiment, the control circuit has a fourth transistor T4having a gate, a drain electrically coupled to the source of the third transistor T3, and a source electrically coupled to a voltage supply for receiving a reference voltage, VSS, therefrom; a fifth transistor T5having a gate electrically coupled to the source of the first transistor T1, a drain electrically coupled to the gate of the fourth transistor T4, and a source electrically coupled to the voltage supply; a sixth transistor T6having a gate electrically coupled to the fourth input node, a drain electrically coupled to the output node, and a source electrically coupled to the source of the fourth transistor T4; a seventh transistor T7having a gate electrically coupled to the gate of the fourth transistor T4, a drain electrically coupled to the gate of third transistor T3, and a source electrically coupled to the voltage supply; a eighth transistor T8having a gate electrically coupled to the third input node, a drain electrically coupled to the gate, and a source electrically coupled to the drain of the fifth transistor T5; a ninth transistor T9having a gate electrically coupled to the drain of the fifth transistor T5, a drain electrically coupled to the drain of the eighth transistor T8, and a source electrically coupled to the source of the eighth transistor T8; and a first capacitor C1electrically coupled between the gate of the third transistor T3and the output node.

In another aspect, the present invention relates to a bidirectional shift register. In one embodiment, a bidirectional shift register includes first, second, third and four control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3and Bi4, respectively; and a plurality of shift register stages electrically coupled in serial, each shift register stage having a first input node, a second input node and an output node, wherein the plurality of shift register stages is grouped into 2N sections such that each section comprises a corresponding number of consecutive shift register stages, N being positive integer, wherein each section has at least one shift register stage, wherein each shift register stage in each odd section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1and Bi2, and wherein each shift register stage in each even section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3and Bi4.

In one embodiment, the first and second input nodes of each shift register stage in each (4j+1)-th section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1and Bi2, respectively; the first and second input nodes of each shift register stage in each (4j+3)-th section are electrically coupled to the second and first control signal bus lines for receiving the second and first control signals Bi2and Bi1, respectively, j=0, 1, 2, . . . ; the first and second input nodes of each shift register stage in each (4j+2)-th section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3and Bi4, respectively, and the first and second input nodes of each shift register stage in each (4j+4)-th section are electrically coupled to the fourth and third control signal bus lines for receiving the fourth and third control signals Bi4and Bi3, respectively.

In one embodiment, each shift register stage further has third and fourth input nodes configured to receive a first clock signal, CK, and a second clock signal, XCK, respectively, wherein each clock signal comprises an AC signal characterized with a period, TCK, and a phase, and the periods of the first and second clock signals are substantially identical, and the phases of the first and second clock signals are substantially reversed, and the period TCKis much shorter than a gate line period, TGL, defined by the active scanning time during a frame.

Each of the first, second, third and fourth control signals Bi1, Bi2, Bi3and Bi4comprises an AC signal characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage, wherein the duration T satisfies T=(TGL/4+2S).

In one embodiment, the first, second, third and fourth control signals Bi1, Bi2, Bi3and Bi4are shifted from each other such that the rising time of the first control signal Bi1is earlier than the beginning of the active scanning time during a frame by S; the rising time of the second control signal Bi2is later than the falling time of the first control signal Bi1by (TGL/4−2S); the rising time of the third control signal Bi3is earlier than the falling time of the second control signal Bi2by (TGL/2+2S); the rising time of the fourth control signal Bi4is later than the falling time of the third control signal Bi3by (TGL/4−2S); and the falling time of the fourth control signal Bi4is later than the end of the active scanning time during a frame.

In another embodiment, the first, second, third and fourth control signals Bi1, Bi2, Bi3and Bi4are shifted from each other such that the rising time of the first control signal Bi1is later than the beginning of the active scanning time during a frame by (TGL/4−S); the rising time of the second control signal Bi2is later than the falling time of the first control signal Bi1by (TGL/4−2S); the falling time of the second control signal Bi2is later than the end of the active scanning time during a frame by S; the rising time of the third control signal Bi3is earlier than the beginning of the active scanning time during a frame by S; and the rising time of the fourth control signal Bi4is later than the falling time of the third control signal Bi3by (TGL/4−2S).

In one embodiment, each shift register stage comprises a first transistor T1having a gate electrically coupled to the output node of its immediately prior shift register stage, a drain electrically coupled to the first input node, and a source; a second transistor T2having a gate electrically coupled to the output node of its immediately next shift register stage, a drain electrically coupled to the source of the first transistor T1, and a source electrically coupled to the second input node; a third transistor T3having a gate electrically coupled to the source of the first transistor T1, a drain electrically coupled to the third input node, and a source electrically coupled to the output node; a fourth transistor T4having a gate, a drain electrically coupled to the source of the third transistor T3, and a source electrically coupled to a voltage supply for receiving a reference voltage, VSS, therefrom; a fifth transistor T5having a gate electrically coupled to the source of the first transistor T1, a drain electrically coupled to the gate of the fourth transistor T4, and a source electrically coupled to the voltage supply; a sixth transistor T6having a gate electrically coupled to the fourth input node, a drain electrically coupled to the output node, and a source electrically coupled to the source of the fourth transistor T4; a seventh transistor T7having a gate electrically coupled to the gate of the fourth transistor T4, a drain electrically coupled to the gate of third transistor T3, and a source electrically coupled to the source of the third transistor T3; a first capacitor C1electrically coupled between the gate of the third transistor T3and the output node; and a second capacitor C2electrically coupled between the third input node and the gate of the seventh transistor T7.

In another embodiment, each shift register stage comprises a first transistor T1having a gate electrically coupled to the output node of its immediately prior shift register stage, a drain electrically coupled to the first input node, and a source; a second transistor T2having a gate electrically coupled to the output node of its immediately next shift register stage, a drain electrically coupled to the source of the first transistor T1, and a source electrically coupled to the second input node; a third transistor T3having a gate electrically coupled to the source of the first transistor T1, a drain electrically coupled to the third input node, and a source electrically coupled to the output node; a fourth transistor T4having a gate, a drain electrically coupled to the source of the third transistor T3, and a source electrically coupled to a voltage supply for receiving a reference voltage, VSS, therefrom; a fifth transistor T5having a gate electrically coupled to the source of the first transistor T1, a drain electrically coupled to the gate of the fourth transistor T4, and a source electrically coupled to the voltage supply; a sixth transistor T6having a gate electrically coupled to the fourth input node, a drain electrically coupled to the output node, and a source electrically coupled to the source of the fourth transistor T4; a seventh transistor T7having a gate electrically coupled to the gate of the fourth transistor T4, a drain electrically coupled to the gate of third transistor T3, and a source electrically coupled to the voltage supply; a eighth transistor T8having a gate electrically coupled to the third input node, a drain electrically coupled to the gate, and a source electrically coupled to the drain of the fifth transistor T5; a ninth transistor T9having a gate electrically coupled to the drain of the fifth transistor T5, a drain electrically coupled to the drain of the eighth transistor T8, and a source electrically coupled to the source of the eighth transistor T8; and a first capacitor C1electrically coupled between the gate of the third transistor T3and the output node.

In yet another aspect, the present invention relates to a method of driving a bidirectional shift register having a plurality of shift register stages electrically coupled in serial, each shift register stage having first and second input nodes.

In one embodiment, the method includes the steps of: providing first, second, third and fourth control signals, Bi1, Bi2, Bi3and Bi4from first, second, third and four control signal bus lines, respectively; and dividing a plurality of shift register stages into 2N sections such that each section comprises a corresponding number of consecutive shift register stages, N being positive integer, wherein each section has at least one shift register stage; and electrically coupling each shift register stage in each odd section to the first and second control signal bus lines for receiving the first and second control signals Bi1and Bi2, and each shift register stage in each even section to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3and Bi4, wherein the coupling step is performed such that the first and second input nodes of each shift register stage in each (4j+1)-th section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1and Bi2, respectively, and the first and second input nodes of each shift register stage in each (4j+3)-th section are electrically coupled to the second and first control signal bus lines for receiving the second and first control signals Bi2and Bi1, respectively, j=0, 1, 2, . . . ; and the first and second input nodes of each shift register stage in each (4j+2)-th section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3and Bi4, respectively, and the first and second input nodes of each shift register stage in each (4j+4)-th section are electrically coupled to the fourth and third control signal bus lines for receiving the fourth and third control signals Bi4and Bi3, respectively.

In one embodiment, the method further comprises the step of providing a first clock signal, CK, and a second clock signal, XCK, where each clock signal comprises an AC signal characterized with a period, TCK, and a phase, and wherein the periods of the first and second clock signals are substantially identical, and the phases of the first and second clock signals are substantially reversed, where the period TCKis much shorter than a gate line period, TGL, defined by the active scanning time during a frame.

The first, second, third and fourth control signals Bi1, Bi2, Bi3and Bi4are adapted for respectively controlling the corresponding sections of the shift register in a forward scanning operation or a backward scanning operation. In one embodiment, each of the first, second, third and fourth control signals Bi1, Bi2, Bi3and Bi4comprises an AC signal characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage, wherein the duration T satisfies T=(TGL/4+2S).

In one embodiment, the first, second, third and fourth control signals Bi1, Bi2, Bi3and Bi4are shifted from each other such that the rising time of the first control signal Bi1is earlier than the beginning of the active scanning time during a frame by S; the rising time of the second control signal Bi2is later than the falling time of the first control signal Bi1by (TGL/4−2S); the rising time of the third control signal Bi3is earlier than the falling time of the second control signal Bi2by (TGL/2+2S); the rising time of the fourth control signal Bi4is later than the falling time of the third control signal Bi3by (TGL/4−2S); and the falling time of the fourth control signal Bi4is later than the end of the active scanning time during a frame by S. The shift register is in the forward scanning operation.

In another embodiment, the first, second, third and fourth control signals Bi1, Bi2, Bi3and Bi4are shifted from each other such that the rising time of the first control signal Bi1is later than the beginning of the active scanning time during a frame by (TGL/4−S); the rising time of the second control signal Bi2is later than the falling time of the first control signal Bi1by (TGL/4−2S); the falling time of the second control signal Bi2is later than the end of the active scanning time during a frame by S; the rising time of the third control signal Bi3is earlier than the beginning of the active scanning time during a frame by S; and the rising time of the fourth control signal Bi4is later than the falling time of the third control signal Bi3by (TGL/4−2S). The shift register is in the backward scanning operation.

In a further aspect, the present invention relates to a shift register. In one embodiment, the shift register includes first, second, third and four control signal bus lines for providing first, second, third and fourth control signals, Bi1, Bi2, Bi3and Bi4, respectively; and a plurality of shift register stages electrically coupled in serial, each shift register stage having a first input node, a second input node and an output node, wherein the plurality of shift register stages is grouped into (2N+1) sections, N being positive integer, wherein each section has at least one shift register stage, wherein each shift register stage in each odd section are electrically coupled to the first and third control signal bus lines for receiving the first and third control signals Bi1and Bi3, and wherein each shift register stage in each even section are electrically coupled to the second and fourth control signal bus lines for receiving the second and fourth control signals Bi2and Bi4.

Specifically, the first and second input nodes of each shift register stage in each (4j+1)-th section are electrically coupled to the first and third control signal bus lines for receiving the first and third control signals Bi1and Bi3, respectively. The first and second input nodes of each shift register stage in each (4j+3)-th section are electrically coupled to the third and first control signal bus lines for receiving the third and first control signals Bi3and Bi1, respectively, j=0, 1, 2, . . . . The first and second input nodes of each shift register stage in each (4j+2)-th section are electrically coupled to the second and fourth control signal bus lines for receiving the second and fourth control signals Bi2and Bi4, respectively. The first and second input nodes of each shift register stage in each (4j+4)-th section are electrically coupled to the fourth and second control signal bus lines for receiving the fourth and second control signals Bi4and Bi2, respectively.

In one embodiment, each shift register stage further has third and fourth input nodes configured to receive a first clock signal, CK, and a second clock signal, XCK, respectively, where each clock signal comprises an AC signal characterized with a period, TCKand a phase, and the periods of the first and second clock signals are substantially identical, and the phases of the first and second clock signals are substantially reversed. The period TCKis much shorter than a gate line period, TGL, defined by the active scanning time during a frame.

The first, second, third and fourth control signals Bi1, Bi2, Bi3and Bi4are adapted for respectively controlling the corresponding sections of the shift register in a forward scanning operation or a backward scanning operation.

During the forward scanning operation, each of the first, second and third control signals Bi1, Bi2and Bi3comprises an AC signal characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage, wherein the duration T satisfies T=(TGL/3+2S), wherein the first, second and third control signals Bi1, Bi2and Bi3are shifted from each other such that the rising time of the first control signal Bi1is earlier than the beginning of the active scanning time during a frame by S; the rising time of the second control signal Bi2is earlier than the falling time of the first control signal Bi1by 2S; the rising time of the third control signal Bi3is earlier than the falling time of the second control signal Bi2by 2S; the falling time of the third control signal Bi3is later than the end of the active scanning time during a frame by S. The fourth control signal Bi4comprises a DC signal with low level voltage.

During the backward scanning operation, each of the first, third and fourth control signals Bi1, Bi3and Bi4comprises an AC signal characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage, wherein the duration T satisfies T=(TGL/3+2S), wherein the first, third and fourth control signals Bi1, Bi3and Bi4are shifted from each other such that the rising time of the first control signal Bi1is earlier than the beginning of the active scanning time during a frame by S; the rising time of the fourth control signal Bi4is earlier than the falling time of the first control signal Bi1by 2S; the rising time of the third control signal Bi3is earlier than the falling time of the fourth control signal Bi4by 2S; the falling time of the third control signal Bi3is later than the end of the active scanning time during a frame by S. The second control signal Bi2comprises a DC signal with low level voltage.

Each shift register stage comprises a first transistor T1having a gate electrically coupled to the output node of its immediately prior shift register stage, a drain electrically coupled to the first input node, and a source; a second transistor T2having a gate electrically coupled to the output node of its immediately next shift register stage, a drain electrically coupled to the source of the first transistor T1, and a source electrically coupled to the second input node; a third transistor T3having a gate electrically coupled to the source of the first transistor T1, a drain electrically coupled to the third input node, and a source electrically coupled to the output node; and a control circuit electrically coupled to the first, second and third transistors T1, T2and T3.

In one embodiment, the control circuit has a fourth transistor T4having a gate, a drain electrically coupled to the source of the third transistor T3, and a source electrically coupled to a voltage supply for receiving a reference voltage, VSS, therefrom; a fifth transistor T5having a gate electrically coupled to the source of the first transistor T1, a drain electrically coupled to the gate of the fourth transistor T4, and a source electrically coupled to the voltage supply; a sixth transistor T6having a gate electrically coupled to the fourth input node, a drain electrically coupled to the output node, and a source electrically coupled to the source of the fourth transistor T4; a seventh transistor T7having a gate electrically coupled to the gate of the fourth transistor T4, a drain electrically coupled to the gate of third transistor T3, and a source electrically coupled to the source of the third transistor T3; a first capacitor C1electrically coupled between the gate of the third transistor T3and the output node; and a second capacitor C2electrically coupled between the third input node and the gate of the seventh transistor T7.

In another embodiment, the control circuit has a fourth transistor T4having a gate, a drain electrically coupled to the source of the third transistor T3, and a source electrically coupled to a voltage supply for receiving a reference voltage, VSS, therefrom; a fifth transistor T5having a gate electrically coupled to the source of the first transistor T1, a drain electrically coupled to the gate of the fourth transistor T4, and a source electrically coupled to the voltage supply; a sixth transistor T6having a gate electrically coupled to the fourth input node, a drain electrically coupled to the output node, and a source electrically coupled to the source of the fourth transistor T4; a seventh transistor T7having a gate electrically coupled to the gate of the fourth transistor T4, a drain electrically coupled to the gate of third transistor T3, and a source electrically coupled to the voltage supply; a eighth transistor T8having a gate electrically coupled to the third input node, a drain electrically coupled to the gate, and a source electrically coupled to the drain of the fifth transistor T5; a ninth transistor T9having a gate electrically coupled to the drain of the fifth transistor T5, a drain electrically coupled to the drain of the eighth transistor T8, and a source electrically coupled to the source of the eighth transistor T8; and a first capacitor C1electrically coupled between the gate of the third transistor T3and the output node.

In a further aspect, the present invention relates to a method of driving a shift register having a plurality of shift register stages electrically coupled in serial, each shift register stage having first and second input nodes. In one embodiment, the method comprises the steps of providing first, second, third and fourth control signals, Bi1, Bi2, Bi3and Bi4from first, second, third and four control signal bus lines, respectively; dividing a plurality of shift register stages into (2N+1) sections, N being positive integer, wherein each section has at least one shift register stage; and electrically coupling each shift register stage in each odd section to the first and third control signal bus lines for receiving the first and third control signals Bi1and Bi3, and each shift register stage in each even section to the second and fourth control signal bus lines for receiving the second and fourth control signals Bi2and Bi4.

In one embodiment, the coupling step is performed such that the first and second input nodes of each shift register stage in each (4j+1)-th section are electrically coupled to the first and third control signal bus lines for receiving the first and third control signals Bi1and Bi3, respectively, and the first and second input nodes of each shift register stage in each (4j+3)-th section are electrically coupled to the third and first control signal bus lines for receiving the third and first control signals Bi3and Bi1, respectively, j=0, 1, 2, . . . ; and the first and second input nodes of each shift register stage in each (4j+2)-th section are electrically coupled to the second and fourth control signal bus lines for receiving the second and fourth control signals Bi2and Bi4, respectively, and the first and second input nodes of each shift register stage in each (4j+4)-th section are electrically coupled to the fourth and second control signal bus lines for receiving the fourth and second control signals Bi4and Bi2, respectively.

The method further comprises the step of providing a first clock signal, CK, and a second clock signal, XCK, wherein each clock signal comprises an AC signal characterized with a period, TCK, and a phase, and wherein the periods of the first and second clock signals are substantially identical, and the phases of the first and second clock signals are substantially reversed, wherein the period TCKis much shorter than a gate line period, TGL, defined by the active scanning time during a frame.

The first, second, third and fourth control signals Bi1, Bi2, Bi3and Bi4are adapted for respectively controlling the corresponding sections of the shift register in a forward scanning operation or a backward scanning operation.

During the forward scanning operation, each of the first, second and third control signals Bi1, Bi2and Bi3comprises an AC signal characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage, wherein the duration T satisfies T=(TGL/3+2S), wherein the first, second and third control signals Bi1, Bi2and Bi3are shifted from each other such that the rising time of the first control signal Bi1is earlier than the beginning of the active scanning time during a frame by S; the rising time of the second control signal Bi2is earlier than the falling time of the first control signal Bi1by 2S; the rising time of the third control signal Bi3is earlier than the falling time of the second control signal Bi2by 2S; the falling time of the third control signal Bi3is later than the end of the active scanning time during a frame by S. The fourth control signal Bi4comprises a DC signal with low level voltage.

During the backward scanning operation, each of the first, third and fourth control signals Bi1, Bi3and Bi4comprises an AC signal characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage, wherein the duration T satisfies T=(TGL/3+2S), wherein the first, third and fourth control signals Bi1, Bi3and Bi4are shifted from each other such that the rising time of the first control signal Bi1is earlier than the beginning of the active scanning time during a frame by S; the rising time of the fourth control signal Bi4is earlier than the falling time of the first control signal Bi1by 2S; the rising time of the third control signal Bi3is earlier than the falling time of the fourth control signal Bi4by 2S; the falling time of the third control signal Bi3is later than the end of the active scanning time during a frame by S. The second control signal Bi2comprises a DC signal with low level voltage.

DETAILED DESCRIPTION OF THE INVENTION

The terms used in this specification generally have their ordinary meanings in the art, within the context of the disclosure, and in the specific context where each term is used. Certain terms that are used to describe the disclosure are discussed below, or elsewhere in the specification, to provide additional guidance to the practitioner regarding the description of the disclosure. The use of examples anywhere in this specification, including examples of any terms discussed herein, is illustrative only, and in no way limits the scope and meaning of the disclosure or of any exemplified term. Likewise, the disclosure is not limited to various embodiments given in this specification.

The description will be made as to the embodiments of the present invention in conjunction with the accompanying drawings inFIGS. 3-13. In accordance with the purposes of this invention, as embodied and broadly described herein, this invention, in one aspect, relates to a bidirectional shift register with control signal bus lines connected to respective shift register circuits with embedded bidirectional scanning function.

Referring in general toFIGS. 3-5, and in particular toFIG. 3, a plurality of bidirectional shift register circuits302are grouped into two sections321and322, i.e., a first section321and second section322, according to one embodiment of the present invention. Each of the first and second sections321and322includes a corresponding number of consecutive shift register circuits302. For example, the first section321has the first shift register circuit S1through the K-th shift register circuit SKof the plurality of shift register circuits302while the second section322has the (K+1)-th shift register circuit SK+1through the M-th shift register circuit SMof the plurality of shift register circuits302, where K is an integer greater than 1 but less than the number, M, of the plurality of shift register circuits302. Each shift register circuit302performs a shift operation with respect to each frame period. Each shift register circuit302includes a first polarity (input) node Bi and a second polarity (input) node XBi. Each of the first polarity nodes Bi of bidirectional shift register circuits302in the first section321is connected to a first control signal bus line311, and controlled by a corresponding control voltage signal Bi1. Each of the second polarity nodes XBi of bidirectional shift register circuits302in the first section321is connected to a second control signal bus line312, and controlled by a corresponding control voltage signal Bi2. Each of the first polarity nodes Bi of the bidirectional shift register circuits302in the second section322is connected to a third control signal line313, and controlled by a corresponding control voltage signal Bi3. Each of the second polarity nodes XBi of bidirectional shift register circuits302in the second section322is connected to a fourth control signal bus line314, and controlled by a corresponding control voltage signal Bi4. The first and second control signals Bi1and Bi2, and the third and fourth control signals Bi3and Bi4are adapted for respectively controlling the first and second sections321and322of the shift register302in a forward scanning operation or a backward scanning operation.

Referring toFIG. 4, a timing diagram illustrates timings of various control voltages during the forward scanning operation for the embodiment as shown inFIG. 3. In the timing diagram, a gate line period, TGL, is defined by the active scanning time during a frame, i.e., from the first gate line signal outputs to the last gate line signal outputs in one frame. A voltage signal CK is a clock control signal characterized with a period, TCK, and a phase. The time period TCKis defined by the duration of a high level state and a low level state of the clock control signal CK in view of the voltage change. Each of the first and third control signals Bi1and Bi3is an AC signal and each of the second and fourth control signals Bi2and Bi4is a DC signal with low level voltage. The AC signal is characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage. The duration T satisfies T=(TGL/2+2S). Further, the third control signal Bi3is shifted from the first control signal Bi1by TGL/2 such that the rising time of the first control signal Bi1is earlier than the beginning of the active scanning time during a frame by a half of 2S, wherein the 2S is the overlap time between Bi1and Bi3, and the falling time of the third control signal Bi3is later than the end of the active scanning time during a frame by a half of the overlap time 2S.

Referring toFIG. 5, a timing diagram illustrates timings of various control voltage signals during the backward (reverse) scanning operation for the embodiment as shown inFIG. 3. In the timing diagram, each of the first and third control signals Bi1and Bi3is a DC signal with low level voltage, while each of the second and fourth control signals Bi2and Bi4is an AC signal that is characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage, where the duration T satisfies T=(TGL/2+2S). The second control signal Bi2is shifted from the fourth control signal Bi4by TGL/2 such that the rising time of the fourth control signal Bi4is earlier than the beginning of the active scanning time during a frame by a half of the overlap time 2S and the falling time of the second control signal Bi2is later than the end of the active scanning time during a frame by a half of the overlap time 2S.

FIG. 6shows a schematic diagram of a bidirectional shift register600according to another embodiment of the present invention. In this exemplary embodiment, the bidirectional shift register600having a plurality of shift register stage602are divided into four (4) sections621,622,623and624. It would be appreciated to people skilled in the art that the plurality of shift register stage602can also be divided into other number of sections according to the present invention. Each section has one or more shift register circuit/stage602. Each shift register stage602has a first polarity input node Bi and a second polarity input node XBi, and performs a shift operation with respect to each frame period. Further, the bidirectional shift register600has first, second, third and four control signal bus lines611,612,613and614for providing first, second, third and fourth control signals, Bi1′, Bi2′, Bi3′ and Bi4′, respectively. The first, second, third and fourth control signals Bi1′, Bi2′, Bi3′ and Bi4′ are adapted for respectively controlling the corresponding sections of the shift register600in a forward scanning operation or a backward scanning operation.

According to the present invention, each shift register stage602in the first and third sections621and623is electrically coupled to the first and second control signal bus lines611and612for receiving the first and second control signals Bi1′ and Bi2′, while each shift register stage602in the second and fourth sections622and624is electrically coupled to the third and fourth control signal bus lines613and614for receiving the third and fourth control signals Bi3′ and Bi4′. More specifically, the first and second input nodes Bi and XBi of each shift register stage602in the first section621are electrically coupled to the first and second control signal bus lines611and612for receiving the first and second control signals Bi1′ and Bi2′, respectively. The first and second input nodes Bi and XBi of each shift register stage602in the third section623are electrically coupled to the second and first control signal bus lines612and611for receiving the second and first control signals Bi2′ and Bi1′, respectively. The first and second input nodes Bi and XBi of each shift register stage602in the second section622are electrically coupled to the third and fourth control signal bus lines613and614for receiving the third and fourth control signals Bi3′ and Bi4′, respectively. The first and second input nodes Bi and XBi of each shift register stage602in the fourth section424are electrically coupled to the fourth and third control signal bus lines614and613for receiving the fourth and third control signals Bi4′ and Bi3′, respectively.

Referring toFIG. 7, a timing diagram illustrates timings of various control voltage signals during the forward scanning operation for the embodiment as shown inFIG. 6. In the timing diagram, a gate line period, TGL, is defined by the active scanning time during a frame, i.e., from the first gate line signal outputs to the last gate line signal outputs in one frame. A voltage signal CK is a clock control signal characterized with a period, TCK, and a phase. The time period TCKis defined by the duration of a high level state and a low level state of the clock control signal CK in view of the voltage change.

In this embodiment, each of the first, second, third and fourth control signals Bi1′, Bi2′, Bi3′ and Bi4′ is an AC signal characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage, where the duration T satisfies T=(TGL/4+2S). Further, the first, second, third and fourth control signals Bi1′, Bi2′, Bi3′ and Bi4″ are shifted from each other such that the rising time of the first control signal Bi1′ is earlier than the beginning of the active scanning time during a frame by S; the rising time of the second control signal Bi2′ is later than the falling time of the first control signal Bi1′ by (TGL/4−2S); the rising time of the third control signal Bi3′ is earlier than the falling time of the second control signal Bi2′ by (TGL/2+2S); the rising time of the fourth control signal Bi4′ is later than the falling time of the third control signal Bi3′ by (TGL/4−2S); and the falling time of the fourth control signal Bi4′ is later than the end of the active scanning time during a frame by S. For such a configuration, during the first one fourth (¼) period of the gate line period TGL, the first control signal Bi1′ is in the high level voltage; during the second one fourth (¼) period of the gate line period TGL, the third control signal Bi3′ is in the high level voltage; during the third one fourth (¼) period of the gate line period TGL, the second control signal Bi2′ is in the high level voltage; and during the fourth one fourth (¼) period of the gate line period TGL, the fourth control signal Bi4″ is in the high level voltage.

Referring toFIG. 8, a timing diagram illustrates timings of various control voltage signals during the backward (reverse) scanning operation for the embodiment as shown inFIG. 6. The first, second, third and fourth control signals Bi1′, Bi2′, Bi3′ and Bi4′ are shifted from each other such that the rising time of the first control signal Bi1′ is later than the beginning of the active scanning time during a frame by (TGL/4−S); the rising time of the second control signal Bi2′ is later than the falling time of the first control signal Bi1′ by (TGL/4−2S); the falling time of the second control signal Bi2′ is later than the end of the active scanning time during a frame by S; the rising time of the third control signal Bi3′ is earlier than the beginning of the active scanning time during a frame by S; and the rising time of the fourth control signal Bi4′ is later than the falling time of the third control signal Bi3′ by (TGL/4−2S). For such a configuration, during the first one fourth (¼) period of the gate line period TGL, the third control signal Bi3′ is in the high level voltage; during the second one fourth (¼) period of the gate line period TGL, the first control signal Bi1′ is in the high level voltage; during the third one fourth (¼) period of the gate line period TGL, the fourth control signal Bi4′ is in the high level voltage; and during the fourth one fourth (¼) period of the gate line period TGL, the second control signal Bi2′ is in the high level voltage.

FIG. 9shows a schematic diagram of a bidirectional shift register900according to yet another embodiment of the present invention. In this exemplary embodiment, the bidirectional shift register900having a plurality of shift register stage902are divided into three (3) sections921,922and923. It would be appreciated to people skilled in the art that the plurality of shift register stage902can also be divided into other number of sections according to the present invention. Each section has one or more shift register circuit/stage902. Each shift register stage902has a first polarity input node Bi and a second polarity input node XBi, and performs a shift operation with respect to each frame period. Further, the bidirectional shift register900has first, second, third and four control signal bus lines911,912,913and914for providing first, second, third and fourth control signals, Bi1″, Bi2″, Bi3″ and Bi4″, respectively. The first, second, third and fourth control signals Bi1″, Bi2″, Bi3″ and Bi4″ are adapted for respectively controlling the corresponding sections of the shift register900in a forward scanning operation or a backward scanning operation.

According to the present invention, each shift register stage902in the first and third sections921and923is electrically coupled to the first and third control signal bus lines911and913for receiving the first and third control signals Bi1″ and Bi3″, while each shift register stage902in the second sections922is electrically coupled to the second and fourth control signal bus lines912and914for receiving the second and fourth control signals Bi2″ and Bi4″. More specifically, the first and second input nodes Bi and XBi of each shift register stage902in the first section921are electrically coupled to the first and third control signal bus lines911and913for receiving the first and third control signals Bi1″ and Bi3″, respectively. The first and second input nodes Bi and XBi of each shift register stage902in the third section923are electrically coupled to the third and first control signal bus lines913and911for receiving the third and first control signals Bi3″ and Bi1″, respectively. The first and second input nodes Bi and XBi of each shift register stage902in the second section922are electrically coupled to the second and fourth control signal bus lines912and914for receiving the second and fourth control signals Bi2″ and Bi4″, respectively.

Referring toFIG. 10, a timing diagram illustrates timings of various control voltage signals during the forward scanning operation for the embodiment as shown inFIG. 9. In the timing diagram, a gate line period, TGL, is defined by the active scanning time during a frame, i.e., from the first gate line signal outputs to the last gate line signal outputs in one frame. In this embodiment, each of the first, second and third control signals Bi1″, Bi2″ and Bi3″ is an AC signal characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage, where the duration T satisfies T=(TGL/3+2S). Further, the first, second and third control signals Bi1″, Bi2″ and Bi3″ are shifted from each other such that the rising time of the first control signal Bi1″ is earlier than the beginning of the active scanning time during a frame by S; the rising time of the second control signal Bi2″ is earlier than the falling time of the first control signal Bi1″ by 2S; the rising time of the third control signal Bi3″ is earlier than the falling time of the second control signal Bi2″ by 2S; the falling time of the third control signal Bi3″ is later than the end of the active scanning time during a frame by S. The fourth control signal Bi4″ comprises a DC signal with low level voltage. For such a configuration, during the first one third (⅓) period of the gate line period TGL, the first control signal Bi1″ is in the high level voltage; during the second one third (⅓) period of the gate line period TGL, the fourth control signal Bi4″ is in the high level voltage; and during the third one third (⅓) period of the gate line period TGL, the third control signal Bi3″ is in the high level voltage.

Referring toFIG. 11, a timing diagram illustrates timings of various control voltage signals during the backward (reverse) scanning operation for the embodiment as shown inFIG. 9. Each of the first, third and fourth control signals Bi1″, Bi3″ and Bi4″ comprises an AC signal characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage, wherein the duration T satisfies T=(TGL/3+2S). Further, the first, third and fourth control signals Bi1″, Bi3″ and Bi4″ are shifted from each other such that the rising time of the first control signal Bi1″ is earlier than the beginning of the active scanning time during a frame by S; the rising time of the fourth control signal Bi4″ is earlier than the falling time of the first control signal Bi1″ by 2S; the rising time of the third control signal Bi3″ is earlier than the falling time of the fourth control signal Bi4″ by 2S; the falling time of the third control signal Bi3″ is later than the end of the active scanning time during a frame by S. The second control signal Bi″2comprises a DC signal with low level voltage. For such a configuration, during the first one third (⅓) period of the gate line period TGL, the first control signal Bi1″ is in the high level voltage; during the second one third (⅓) period of the gate line period TGL, the second control signal Bi2″ is in the high level voltage; and during the third one third (⅓) period of the gate line period TGL, the third control signal Bi3″ is in the high level voltage.

FIG. 12shows a circuit diagram of a stage of a bidirectional shift register according to one embodiment of the present invention. The shift register stage comprises seven transistors T1-T7and two capacitors C1and C2. The first transistor T1has a gate electrically coupled to the output node of its immediately prior shift register stage, a drain electrically coupled to the first input node, and a source. The second transistor T2has a gate electrically coupled to the output node of its immediately next shift register stage, a drain electrically coupled to the source of the first transistor T1, and a source electrically coupled to the second input node. The third transistor T3has a gate electrically coupled to the source of the first transistor T1, a drain electrically coupled to the third input node, and a source electrically coupled to the output node. The fourth transistor T4has a gate, a drain electrically coupled to the source of the third transistor T3, and a source electrically coupled to a voltage supply for receiving a reference voltage, VSS, therefrom. The fifth transistor T5having a gate electrically coupled to the source of the first transistor T1, a drain electrically coupled to the gate of the fourth transistor T4, and a source electrically coupled to the voltage supply. The sixth transistor T6has a gate electrically coupled to the fourth input node, a drain electrically coupled to the output node, and a source electrically coupled to the source of the fourth transistor T4. The seventh transistor T7has a gate electrically coupled to the gate of the fourth transistor T4, a drain electrically coupled to the gate of third transistor T3, and a source electrically coupled to the source of the third transistor T3. The first capacitor C1is electrically coupled between the gate of the third transistor T3and the output node. The second capacitor C2is electrically coupled between the third input node and the gate of the seventh transistor T7.

In another embodiment, as shown inFIG. 13, the shift register stage comprises a first transistor T1having a gate electrically coupled to the output node of its immediately prior shift register stage, a drain electrically coupled to the first input node, and a source; a second transistor T2having a gate electrically coupled to the output node of its immediately next shift register stage, a drain electrically coupled to the source of the first transistor T1, and a source electrically coupled to the second input node; a third transistor T3having a gate electrically coupled to the source of the first transistor T1, a drain electrically coupled to the third input node, and a source electrically coupled to the output node; a fourth transistor T4having a gate, a drain electrically coupled to the source of the third transistor T3, and a source electrically coupled to a voltage supply for receiving a reference voltage, VSS, therefrom; a fifth transistor T5having a gate electrically coupled to the source of the first transistor T1, a drain electrically coupled to the gate of the fourth transistor T4, and a source electrically coupled to the voltage supply; a sixth transistor T6having a gate electrically coupled to the fourth input node, a drain electrically coupled to the output node, and a source electrically coupled to the source of the fourth transistor T4; a seventh transistor T7having a gate electrically coupled to the gate of the fourth transistor T4, a drain electrically coupled to the gate of third transistor T3, and a source electrically coupled to the voltage supply; a eighth transistor T8having a gate electrically coupled to the third input node, a drain electrically coupled to the gate, and a source electrically coupled to the drain of the fifth transistor T5; a ninth transistor T9having a gate electrically coupled to the drain of the fifth transistor T5, a drain electrically coupled to the drain of the eighth transistor T8, and a source electrically coupled to the source of the eighth transistor T8; and a first capacitor C1electrically coupled to between the gate of the third transistor T3and the output node.

One aspect of the present invention relates to a method of driving a bidirectional shift register having a plurality of shift register stages electrically coupled in serial, each shift register stage having first and second input nodes.

The method in one embodiment includes the following steps: first, second, third and fourth control signals, Bi1, Bi2, Bi3and Bi4are provided from first, second, third and four control signal bus lines, respectively. The plurality of shift register stages grouped into 2N sections, N being positive integer, where each section has at least one shift register stage. Then, each shift register stage in each odd section is electrically coupling to the first and second control signal bus lines for receiving the first and second control signals Bi1and Bi2, and each shift register stage in each even section is electrically coupling to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3and Bi4. Specifically, the first and second input nodes of each shift register stage in each (4j+1)-th section are electrically coupled to the first and second control signal bus lines for receiving the first and second control signals Bi1and Bi2, respectively, and the first and second input nodes of each shift register stage in each (4j+3)-th section are electrically coupled to the second and first control signal bus lines for receiving the second and first control signals Bi2and Bi1, respectively, j=0, 1, 2, . . . ; and the first and second input nodes of each shift register stage in each (4j+2)-th section are electrically coupled to the third and fourth control signal bus lines for receiving the third and fourth control signals Bi3and Bi4, respectively, and the first and second input nodes of each shift register stage in each (4j+4)-th section are electrically coupled to the fourth and third control signal bus lines for receiving the fourth and third control signals Bi4and Bi3, respectively.

The method further includes the step of providing a first clock signal, CK, and a second clock signal, XCK, where each clock signal comprises an AC signal characterized with a period, TCK, and a phase, and wherein the periods of the first and second clock signals are substantially identical, and the phases of the first and second clock signals are substantially reversed. The period TCKis much shorter than a gate line period, TGL, defined by the active scanning time during a frame.

Further, each of the first, second, third and fourth control signals Bi1, Bi2, Bi3and Bi4comprises an AC signal characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage, wherein the duration T satisfies T=(TGL/4+2S).

In one embodiment, the first, second, third and fourth control signals Bi1, Bi2, Bi3and Bi4are shifted from each other such that the rising time of the first control signal Bi1is earlier than the beginning of the active scanning time during a frame by S; the rising time of the second control signal Bi2is later than the falling time of the first control signal Bi1by (TGL/4−2S); the rising time of the third control signal Bi3is earlier than the falling time of the second control signal Bi2by (TGL/2+2S); the rising time of the fourth control signal Bi4is later than the falling time of the third control signal Bi3by (TGL/4−2S); and the falling time of the fourth control signal Bi4is later than the end of the active scanning time during a frame by S. Accordingly, the shift register is in the forward scanning operation

In another embodiment, the first, second, third and fourth control signals Bi1, Bi2, Bi3and Bi4are shifted from each other such that the rising time of the first control signal Bi1is later than the beginning of the active scanning time during a frame by (TGL/4−S); the rising time of the second control signal Bi2is later than the falling time of the first control signal Bi1by (TGL/4−2S); the falling time of the second control signal Bi2is later than the end of the active scanning time during a frame by S; the rising time of the third control signal Bi3is earlier than the beginning of the active scanning time during a frame by S; and the rising time of the fourth control signal Bi4is later than the falling time of the third control signal Bi3by (TGL/4−2S). Accordingly, the shift register is in the backward scanning operation.

Another aspect of the present invention relates to a method of driving a shift register having a plurality of shift register stages electrically coupled in serial, each shift register stage having first and second input nodes. In one embodiment, the method comprises the steps of providing first, second, third and fourth control signals, Bi1, Bi2, Bi3and Bi4from first, second, third and four control signal bus lines, respectively; dividing a plurality of shift register stages into (2N+1) sections, N being positive integer, wherein each section has at least one shift register stage; and electrically coupling each shift register stage in each odd section to the first and third control signal bus lines for receiving the first and third control signals Bi1and Bi3, and each shift register stage in each even section to the second and fourth control signal bus lines for receiving the second and fourth control signals Bi2and Bi4.

Further, the coupling step is performed such that the first and second input nodes of each shift register stage in each (4j+1)-th section are electrically coupled to the first and third control signal bus lines for receiving the first and third control signals Bi1and Bi3, respectively, and the first and second input nodes of each shift register stage in each (4j+3)-th section are electrically coupled to the third and first control signal bus lines for receiving the third and first control signals Bi3and Bi1, respectively, j=0, 1, 2, . . . ; and the first and second input nodes of each shift register stage in each (4j+2)-th section are electrically coupled to the second and fourth control signal bus lines for receiving the second and fourth control signals Bi2and Bi4, respectively, and the first and second input nodes of each shift register stage in each (4j+4)-th section are electrically coupled to the fourth and second control signal bus lines for receiving the fourth and second control signals Bi4and Bi2, respectively.

The first, second, third and fourth control signals Bi1, Bi2, Bi3and Bi4are adapted for respectively controlling the corresponding sections of the shift register in a forward scanning operation or a backward scanning operation.

During the forward scanning operation, each of the first, second and third control signals Bi1, Bi2and Bi3comprises an AC signal characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage, wherein the duration T satisfies T=(TGL/3+2S), wherein the first, second and third control signals Bi1, Bi2and Bi3are shifted from each other such that the rising time of the first control signal Bi1is earlier than the beginning of the active scanning time during a frame by S; the rising time of the second control signal Bi2is earlier than the falling time of the first control signal Bi1by 2S; the rising time of the third control signal Bi3is earlier than the falling time of the second control signal Bi2by 2S; the falling time of the third control signal Bi3is later than the end of the active scanning time during a frame by S. The fourth control signal Bi4comprises a DC signal with low level voltage.

During the backward scanning operation, each of the first, third and fourth control signals Bi1, Bi3and Bi4comprises an AC signal characterized with a waveform having a high level voltage defining a duration, T, and a low level voltage, wherein the duration T satisfies T=(TGL/3+2S), wherein the first, third and fourth control signals Bi1, Bi3and Bi4are shifted from each other such that the rising time of the first control signal Bi1is earlier than the beginning of the active scanning time during a frame by S; the rising time of the fourth control signal Bi4is earlier than the falling time of the first control signal Bi1by 2S; the rising time of the third control signal Bi3is earlier than the falling time of the fourth control signal Bi4by 2S; the falling time of the third control signal Bi3is later than the end of the active scanning time during a frame by S. The second control signal Bi2comprises a DC signal with low level voltage.

With the aid of the control signals in the disclosed bidirectional shift register, low frequency exchange is enabled and bidirectional scanning is maintained, thereby reducing voltage stress and enhance reliability.