Two step molding grinding for packaging applications

Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a method including mounting a die to a top surface of a substrate to form a device, encapsulating the die and top surface of the substrate in a mold compound, the mold compound having a first thickness over the die, and removing a portion, but not all, of the thickness of the mold compound over the die. The method further includes performing further processing on the device, and removing the remaining thickness of the mold compound over the die.

BACKGROUND

The semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node (e.g., shrink the process node towards the sub-20 nm node). As the demand for miniaturization, higher speed and greater bandwidth, as well as lower power consumption and latency has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.

DETAILED DESCRIPTION

Embodiments will be described with respect to embodiments in a specific context, namely a Die-Interposer-Substrate stacked package using Chip-on-Wafer-on-Substrate (CoWoS) processing. Other embodiments may also be applied, however, to other packages, such as a Die-Die-Substrate stacked package, and other processing.

In general terms, embodiments of the present disclosure may provide for an improved approach to reduce or minimize or perhaps entirely eliminate electro-static discharge (ESD) events during a manufacturing process, such as, for example, a C4(controlled collapse chip connection) manufacturing process. As such, the process windows for manufacturing CoWoS devices can be expanded, reducing manufacturing costs and complexity, while increasing process yield.

While static electricity cannot be totally eliminated in the manufacturing environment, its impact can be reduced. One approach, as described herein, is to maintain an isolation layer on a die (such as the backside of a die) during a C4bump process. This may reduce or eliminate the path by which static electricity can reach and damage sensitive components.

FIGS. 1 through 10illustrate cross-sectional views of intermediate steps in forming a package in accordance with some embodiments, andFIG. 11is a flow chart of the process illustrated inFIGS. 1 through 10in accordance with some embodiments.

FIG. 1illustrates the formation of one or more dies110(step702). A substrate102comprises one or more dies110during processing. The substrate102includes an interconnect structure106over an active surface102A with bond pads108formed in and/or on the interconnect structure106.

The substrate102may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate102may be a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or combinations thereof.

The substrate102may include active and passive devices (not shown inFIG. 1). As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the one or more dies110. The devices may be formed using any suitable methods.

An interconnect structure106comprising one or more dielectric layer(s) and respective metallization pattern(s) is formed on the active surface202A. The metallization pattern(s) in the dielectric layer(s) may route electrical signals between the devices, such as by using vias and/or traces, and may also contain various electrical devices, such as capacitors, resistors, inductors, or the like. The various devices and metallization patterns may be interconnected to perform one or more functions. The functions may include memory structures, processing structures, sensors, amplifiers, power distribution, input/output circuitry, or the like.

One or more inter-metallization dielectric (IMD) layers formed in the interconnect structure208may be formed, for example, of a low-K dielectric material, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like, by any suitable method known in the art, such as spinning, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), or the like. A metallization pattern may be formed in the IMD layer, for example, by using photolithography techniques to deposit and pattern a photoresist material on the IMD layer to expose portions of the IMD layer that are to become the metallization pattern. An etch process, such as an anisotropic dry etch process, may be used to create recesses and/or openings in the IMD layer corresponding to the exposed portions of the IMD layer. The recesses and/or openings may be lined with a diffusion barrier layer and filled with a conductive material. The diffusion barrier layer may comprise one or more layers of TaN, Ta, TiN, Ti, CoW, or the like, deposited by atomic layer deposition (ALD), or the like, and the conductive material may comprise copper, aluminum, tungsten, silver, and combinations thereof, or the like, deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. Any excessive diffusion barrier layer and/or conductive material on the IMD layer may be removed, such as by using a chemical mechanical polish (CMP).

The bond pads108are formed in and/or on the interconnect structure106. In some embodiments, the bond pads108are formed by forming recesses (not shown) into one or more of the dielectric layers of the interconnect structure106. The recesses may be formed to allow the bond pads108to be embedded into the interconnect structure106. In other embodiments, the recesses are omitted as the bond pads108are formed on the interconnect structure106. The bond pads108electrically and/or physically couple the one or more dies110to the subsequently bonded substrate202(seeFIG. 4). In some embodiments, the bond pads108include a thin seed layer (not shown) made of copper, titanium, nickel, gold, the like, or a combination thereof. The conductive material of the bond pads108may be deposited over the thin seed layer. The conductive material may be formed by an electro-chemical plating process, CVD, ALD, PVD, the like, or a combination thereof. In an embodiment, the conductive material of the bond pads108is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

In an embodiment, the bond pads108are underbump metallizations (UBMs) that include three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel. However, one of ordinary skill in the art will recognize that there are many suitable arrangements of materials and layers, such as an arrangement of chrome/chrome-copper alloy/copper/gold, an arrangement of titanium/titanium tungsten/copper, or an arrangement of copper/nickel/gold, that are suitable for the formation of the UBMs108. Any suitable materials or layers of material that may be used for the UBMs108are fully intended to be included within the scope of the current application.

InFIG. 2, the substrate102including the interconnect structure106is singulated into individual dies110(step704). Typically, the dies110contain the same circuitry, such as devices and metallization patterns, although the dies may have different circuitry. In some embodiments, the singulation is by sawing, laser, dicing, the like, or a combination thereof.

FIG. 3illustrates the formation of a first side of a substrate202(step706). The substrate202may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate202may be a SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The substrate202is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include bismaleimide-triazine (BT) resin, or alternatively, other PC board materials or films. Build up films such as Ajinomoto build-up film (ABF) or other laminates may be used for substrate202.

The substrate202may include active and passive devices (not shown inFIG. 3) formed in and/or on a first surface202A of the substrate202. As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the substrate202. The devices may be formed using any suitable methods. In some embodiments, the substrate202is an interposer that generally does not include active devices therein, although the interposer may include passive devices formed in and/or on a first surface202A.

Through-vias (TVs)206are formed to extend from the first surface202A of the substrate202into the substrate202. The TVs206are also sometimes referred to as through-substrate vias or through-silicon vias when the substrate202is a silicon substrate. The TVs206may be formed by forming recesses in the substrate202by, for example, etching, milling, laser techniques, the like, or a combination thereof. A thin barrier layer may be conformally deposited over the front side of the substrate202and in the openings, such as by CVD, ALD, PVD, thermal oxidation, the like, or a combination thereof. The barrier layer may comprise a nitride or an oxynitride, such as titanium nitride, titanium oxynitride, tantalum nitride, tantalum oxynitride, tungsten nitride, the like, or a combination thereof. A conductive material may be deposited over the thin barrier layer and in the openings. The conductive material may be formed by an electro-chemical plating process, CVD, ALD, PVD, the like, or a combination thereof. Examples of conductive materials are copper, tungsten, aluminum, silver, gold, the like, or a combination thereof. Excess conductive material and barrier layer is removed from the front side of the substrate202by, for example, a CMP. Thus, the TVs206may comprise a conductive material and a thin barrier layer between the conductive material and the substrate202.

An interconnect structure208is formed over the first surface202A of the substrate202, and is used to electrically connect the integrated circuit devices, if any, and/or the TVs206together and/or to external devices. The interconnect structure208may include one or more dielectric layer(s) and respective metallization pattern(s) in the dielectric layer(s). The metallization patterns may comprise vias and/or traces to interconnect any devices and/or TVs206together and/or to an external device. The metallization patterns are sometimes referred to as Redistribution Lines (RDLs). The dielectric layers may comprise silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, low-K dielectric material, such as PSG, BPSG, FSG, SiOxCy, Spin-On-Glass, Spin-On-Polymers, silicon carbon material, compounds thereof, composites thereof, combinations thereof, or the like. The dielectric layers may be deposited by any suitable method known in the art, such as spinning, CVD, PECVD, HDP-CVD, or the like. A metallization pattern may be formed in the dielectric layer, for example, by using photolithography techniques to deposit and pattern a photoresist material on the dielectric layer to expose portions of the dielectric layer that are to become the metallization pattern. An etch process, such as an anisotropic dry etch process, may be used to create recesses and/or openings in the dielectric layer corresponding to the exposed portions of the dielectric layer. The recesses and/or openings may be lined with a diffusion barrier layer and filled with a conductive material. The diffusion barrier layer may comprise one or more layers of TaN, Ta, TiN, Ti, CoW, or the like, deposited by ALD, or the like, and the conductive material may comprise copper, aluminum, tungsten, silver, and combinations thereof, or the like, deposited by CVD, PVC, or the like. Any excessive diffusion barrier layer and/or conductive material on the dielectric layer may be removed, such as by using a CMP.

Electrical connectors210are formed at the top surface of and electrically coupled to the interconnect structure208. The electrical connectors210may be solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, electroless nickel-electroless palladium-immersion gold technique (ENEPIG) formed bumps, or the like. The electrical connectors210may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In an embodiment in which the electrical connectors210are solder bumps, the electrical connectors210are formed by initially forming a layer of solder through such commonly used methods such as evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a layer of solder has been formed on the structure, a reflow may be performed in order to shape the material into the desired bump shapes. In another embodiment, the electrical connectors210are metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on the top of the metal pillar connectors210. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process.

FIG. 4illustrates attaching the dies110to the first side of the first substrate (step708), for example, through flip-chip bonding to form a die package. The electrical connectors210electrically couple the circuits in the dies110to the interconnect structure208and TVs206.

The dies110may include a logic die, such as a central processing unit (CPU), a graphics processing unit (GPU), the like, or a combination thereof. In some embodiments, the dies110include a die stack (not shown) which may include both logic dies and memory dies. The dies110may include an input/output (I/O) die, such as a wide I/O die.

The bonding between the dies110and the interconnect structure208may be a solder bonding or a direct metal-to-metal (such as a copper-to-copper or tin-to-tin) bonding. In an embodiment, the dies110are bonded to the interconnect structure208by a reflow process. During this reflow process, the electrical connectors210are in contact with the bond pads108and the interconnect structure208to physically and electrically couple the dies110to the interconnect structure208.

An underfill material302may be injected or otherwise formed in the space between the dies110and the interconnect structure208and surrounding the electrical connectors210. The underfill material302may, for example, be a liquid epoxy, deformable gel, silicon rubber, or the like, that is dispensed between the structures, and then cured to harden. This underfill material is used, among other things, to reduce damage to and to protect the electrical connectors210.

After the dies110are attached to the substrate202, the dies110are encapsulated (step710). In some embodiments, the dies110are encapsulated by a molding material304. The molding material304may be molded on the dies110, for example, using compression molding. In some embodiments, the molding material304is made of a molding compound, a polymer, an epoxy, silicon oxide filler material, the like, or a combination thereof. A curing step may be performed to cure the molding material304, wherein the curing may be a thermal curing, a Ultra-Violet (UV) curing, the like, or a combination thereof.

In some embodiments, the dies110are buried in the molding material304, and after the curing of the molding material304, a first planarization process is performed on the molding material304(step712) as illustrated inFIG. 5. In an embodiment, the first planarization process is a grinding process, although other techniques including etching, laser ablation, polishing, and the like could be employed. The first planarization process is used planarize the molding material304to provide a substantially planar top surface304A of the molding material304. The first planarization process removes some, but not all, of molding material304over the dies110such that backside surfaces110A of the dies110are still buried in molding material304. In an embodiment, the remaining amount of molding material304over the backside surfaces110A of the dies110has a thickness T1of greater than about 30 μm, such as from about 30 μm to about 50 μm.

The thickness T1is a sufficient thickness of molding material304to block the electro-static discharge path between the dies110and the carrier substrate402and also to allow a possible rework of the molding compound304without exposing the dies110. For example, after the first planarization process, a defect could be found on the molding compound304and a rework process, e.g. a grinding process, may need to be performed to remove the defect. By having at least 30 μm of molding compound304over the backside surfaces110A of the dies110, the backside surfaces110A of the dies110will not be exposed during the rework process, and hence, they will remain protected by the molding compound304.

FIG. 6illustrates flipping over the die package and adhering the surface304A of the molding material304to a carrier substrate402to allow formation of the formation of a second side of the substrate202. The carrier substrate402may be any suitable substrate that provides (during intermediary operations of the fabrication process) mechanical support for the components and structures over the carrier substrate402. The carrier substrate402may be a wafer including glass, quartz, silicon (e.g., a silicon wafer), silicon oxide, a metal plate, a ceramic material, or the like.

In the formation of the second side, a thinning process is performed on the second side of the substrate202to thin the substrate202to a second surface202B until the TVs206are exposed. In an embodiment, the thinning process is a grinding process, although other techniques including etching, laser ablation, polishing, and the like could be employed. A dielectric layer(s)404is formed on the second surface202B of the substrate202. A metallization pattern(s)406may be formed on the second surface202B and in dielectric layer(s)404, using similar processes as discussed above.

Electrical connectors408are also formed on the second side of substrate202and are electrically coupled to the TVs206. In some embodiments, the electrical connectors408are solder balls, metal pillars, C4bumps, micro bumps, ENEPIG formed bumps, or the like. The electrical connectors408may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In another embodiment, the electrical connectors408are metal pillars (such as a copper pillar) formed by a sputtering, printing, electro plating, electroless plating, CVD, or the like. The metal pillars may be solder free and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on the top of the metal pillar connectors408. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof and may be formed by a plating process. The electrical connectors408may be used to bond to an additional electrical component, which may be a semiconductor substrate, a package substrate, a Printed Circuit Board (PCB), or the like.

During the formation of the second side of the substrate202(e.g. formation of the dielectric layer(s)404, metallization patterns(s)406, and/or electrical connectors408), the dies110, the substrate202, and the electrical connectors408can become positively charged, while the carrier substrate402can become negatively charged, or vice versa. Hence, the interface between the dies110and the carrier substrate402can be an electro-static discharge path. The discharging of this electro-static energy can damage devices in and/or on the dies110and the substrate202. By leaving an amount of the molding material304covering the backside surfaces110A of the dies110, the molding material304forms an isolation layer, which blocks the electro-static discharge path between the dies110and the carrier substrate402. The carrier substrate402and the backside surfaces110A of the dies110are separated by molding material304having the thickness T1, which is a sufficient thickness of molding material304to block the electro-static discharge path between the dies110and the carrier substrate402.

FIG. 7illustrates applying a protection film420to the second side of the substrate202(step714) and removing the carrier substrate402. The protection film420may be a tape, such as a backgrinding (BG) tape (UV or non-UV type), which may be used to protect the second side of the substrate202from grinding debris during a subsequent molding material planarization process (seeFIG. 8). The protective film420may be applied over the second side of the substrate202using, for example, a roller (not shown). The protective film420may have a sufficient thickness to fully cover the electrical connectors408as illustrated inFIG. 7.

FIG. 8illustrates performing a second planarization process to the molding material304(step716). In an embodiment, the second planarization process is a grinding process, although other techniques including etching, laser ablation, polishing, and the like could be employed. The second planarization process is used to remove excess portions of the molding material304, which excess portions are over backside surfaces110A of the dies110. In some embodiments, the backside surfaces110A of the dies110are exposed, and are level with the surface304A of the molding material304.

In some embodiments, after the second planarization process, the dies110can have a thickness from the active surface102A to the backside surface110A of about 2.2 μm, as compared to a die not using the above-described two-step molding material planarization process, which typically has a thickness of about 1.05 μm. Another aspect of embodiments of the present disclosure is a difference in the roughness of the surface304A of the molding material304when the above-described processes are employed. For instance, in some embodiments, a roughness of about 1 to about 3 μm was observed, relative to a roughness of about 0 to about 1 μm when the process is not employed. The differences of the thickness of the dies110and the surface roughness of the molding material304are at least partially attributed to performing the second molding material planarization process (see step716above) while the protective film420is on the opposite side of the die package (e.g. over the second side of the substrate202), because the protective film420is softer than the substrate202, which is on the opposite side of the die package during the first molding material planarization process (see step712above). Hence, the softer protective film420can compress and absorb some of the pressure being applied during the second molding material planarization process, which can cause the second molding material process to consume less of the backside surface110A of the dies110and can also increase the roughness of the surface304A of the molding material304.

FIG. 9illustrates removing the protective film420and attaching an optional heat sink502to the backside surfaces110A of the dies110and the surface304A of the molding material304. The heat sink502can adhered to the dies110and the molding material304by an adhesive film (not shown). The adhesive film may be applied to the heat sink502or to the backside surfaces110A of the dies110and the surface304A of the molding material304to have a thickness such that it is not so thick as to suppress thermal dissipation. The adhesive film may be an epoxy, resin, the like, or a combination thereof. The heat sink502may be a metal plate. Exemplary materials for the metal plate are copper, nickel-plated copper, aluminum, the like, or a combination thereof. The heat sink502generally may have good thermal conductivity and/or have a coefficient of thermal expansion (CTE) comparable to the CTE of the dies110. The heat sink502typically dissipates heat when in the completed package.

FIG. 10illustrates attaching the die package to a substrate602(step718). The substrate602may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenic, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenic phosphide, gallium indium phosphide, combinations of these, and the like, may also be used. Additionally, the substrate602may be a SOI substrate. Generally, an SOI substrate includes a layer of a semiconductor material such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or combinations thereof. The substrate602is, in one alternative embodiment, based on an insulating core such as a fiberglass reinforced resin core. One example core material is fiberglass resin such as FR4. Alternatives for the core material include BT resin, or alternatively, other PC board materials or films. Build up films such as ABF or other laminates may be used for substrate602.

The substrate602may include active and passive devices (not shown inFIG. 10). As one of ordinary skill in the art will recognize, a wide variety of devices such as transistors, capacitors, resistors, combinations of these, and the like may be used to generate the structural and functional requirements of the design for the substrate602. The devices may be formed using any suitable methods. In some embodiments, the substrate602is package substrate.

The substrate602includes bond pads606on a first side of the substrate602and electrical connectors604on a second side of the substrate, the second side being opposite the first side. The bond pads606and the electrical connectors604may be similar to the bond pads108and the electrical connectors408, respectively, described above and the descriptions are not repeated herein, although the bond pads108and606and the electrical connectors408and604need not be the same.

The bonding between the die package and the substrate602may be a solder bonding or a direct metal-to-metal (such as a copper-to-copper or tin-to-tin) bonding. In an embodiment, the die package is bonded to the substrate602by a reflow process. During this reflow process, the electrical connectors408are in contact with the metallization patterns406and bond pads606to physically and electrically couple the die package to the substrate602.

An underfill material608may be injected or otherwise formed in the space between the die package and the substrate602and surrounding the electrical connectors408. The underfill material608may, for example, be a liquid epoxy, deformable gel, silicon rubber, or the like, that is dispensed between the structures, and then cured to harden. This underfill material is used, among other things, to reduce damage to and to protect the electrical connectors408.

By maintaining an isolation layer on a die (such as the backside of a die) during a bump formation process, the path by which static electricity can reach and damage sensitive components may be significantly reduced or eliminated altogether. As such, the process windows for manufacturing CoWoS devices can be expanded, reducing manufacturing costs and complexity, while increasing process yield.

For example, during the formation of a second side of a substrate (e.g. formation of dielectric layer(s), metallization patterns(s), and/or electrical connectors), the dies attached to the substrate, the substrate itself, and the electrical connectors can become positively charged, while a carrier substrate (attached to backside of dies) can become negatively charged, or vice versa. Hence, the interface between the dies110and the carrier substrate can be an electro-static discharge path. By leaving an amount of the molding material covering the backside surfaces of the dies, the molding material forms an isolation layer, which blocks the electro-static discharge path between the dies and carrier substrate.

An embodiment is a method including mounting a die to a top surface of a substrate to form a device, encapsulating the die and top surface of the substrate in a mold compound, the mold compound having a first thickness over the die, and removing a portion, but not all, of the thickness of the mold compound over the die. The method further includes performing further processing on the device, and removing the remaining thickness of the mold compound over the die.

Another embodiment is a method including attaching an active surface of a first die to a first side of a first substrate to form a die package, encapsulating the first die and the first side of the substrate with a molding material, the molding material having a first thickness from a first surface of the molding material to a backside surface of the first die, the backside surface being opposite the active surface, and performing a first planarizing step to the first surface of the molding material to have a second thickness from the first surface of the molding material to the backside surface of the first die, the second thickness being less than the first thickness. The method further includes attaching the first surface of the molding material to a carrier substrate, forming an electrical connector over a second side of the first substrate, removing the carrier substrate, and performing a second planarizing step to the first surface of the molding material to remove the remaining molding material over the backside surface of the first die.

A further embodiment is a method including attaching a die to a first surface of a first substrate to form a device package, encapsulating the die and the first surface of the first substrate with a molding compound, the molding compound extending over the die, and removing a portion of the molding compound extending over the die. The method further includes performing further processing on the device package, and removing the remaining portion of the molding compound over the die to expose a surface of the die.