Clock data recovery circuit with phase decision circuit

A clock data recovery circuit with feedback type phase discrimination. The clock data recovery circuit has an output signal of B bits and comprises a sampler, a phase region decision circuit, a phase status register and a multiplexer. The sampler oversamples k*B bits per cycle from a data input signal according to a sampling clock signal. The phase region decision circuit generates a plurality of binary up-down decision signals according to the oversampled data input signal and a current phase status signal. The phase status register generates the current phase status signal according to the binary up-down decision signals. The multiplexer selects data of B bits from the oversampled data input signal according to the current phase status signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to clock data recovery and, in particular, to clock data recovery circuits with phase decision circuits.

2. Description of the Related Art

Some data streams, especially high-speed serial data streams, (such as the raw stream of data from the magnetic head of a disk drive) are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and phase-aligns to the transitions in the data stream with a phase locked loop (PLL). In order for this scheme to work, the data stream must have frequent enough transition to correct any drift in the PLL's oscillator. Thus, clock data recovery circuits can be a key circuit block in a receiver.

FIG. 1shows a conventional clock data recovery circuit as disclosed in “A 0.5 um CMOS 4 Gbit/s Serial Link Transceiver with Data Recovery Using Oversampling”, IEEE J. Solid-State Circuits, vol. 33, pp 713-722, May. 1998, by C. K. Yang and M. Horowitz. The clock data recovery circuit comprises a sampler110, an XOR circuit block120, a shift register130, a voter140, a multiplexer150and a post process logic circuit160. The sampler110receives an input data stream IN and a sampling clock signal CLK. The XOR circuit120is coupled to the sampler110and receives the oversampled input data stream IN′. The shift register130is coupled to the XOR circuit block120. The voter140is coupled to the shift register130and generates a voting result according to the oversampled input data stream IN′. The multiplexer150is coupled to the voter140and selects data from the oversampled input data stream IN′ according to the voting result. Data processing of the selected data is performed by the post process logic circuit160and thus an output signal is provided. In this conventional clock data recovery circuit, number of voting needs to be large enough such that voting error rate is reduced. Hardware cost is also an issue.

FIG. 2shows another conventional clock data recovery circuit as disclosed in “Multi-Gigabit-Rate Clock and Data Recovery Based on Blind Oversampling”, IEEE Communication Magazine, pp. 68-74, December 2003, by J. Kim and D. K. Jeong. The clock data recovery circuit comprises a sampler210, an XOR circuit block220, a first voter230, a shift register240, a second voter250, a multiplexer260and a post process logic circuit270. The sampler210receives an input data stream IN and a sampling clock signal CLK. The XOR circuit220is coupled to the sampler210and receives the oversampled input data stream IN′. The first voter230is coupled to the XOR circuit block220and performs a first voting. The shift register240is coupled to the first voter230and receives the first voting result. The second voter250is coupled to the shift register240and generates a second voting result according to an output signal of the shift register240. The multiplexer260is coupled to the second voter250and selects data from the oversampled input data stream IN′ according to the second voting result. Data processing of the selected data is performed by the post process logic circuit270and thus an output signal is provided. In this conventional clock data recovery circuit, number of voting still needs to be large enough such that voting error rate is reduced. Hardware cost, while lower than in the previous conventional clock data recovery circuit, remains an issue.

BRIEF SUMMARY OF THE INVENTION

An embodiment of a clock data recovery circuit with feedback type phase decision generates an output signal of B bits and comprises a sampler, a phase region decision circuit, a phase status register and a multiplexer. The sampler oversamples k*B bits per cycle from a data input signal according to a sampling clock signal. The phase region decision circuit generates a plurality of binary up-down decision signals according to the oversampled data input signal and a current phase status signal. The phase status register generates the current phase status signal according to the binary up-down decision signals. The multiplexer selects data of B bits from the oversampled data input signal according to the current phase status signal. The multiplexer selects the data sampled in at a phase Φn5, wherein n5is a modulus of nx5/k, and nx5is a sum of k and m. The binary up-down decision signals comprise a first up signal, a first down signal, a second up signal, and a second down signal. The first up signal has a value of 1 if a phase region of the oversampled data input signal is Rn1, wherein n1is a modulus of nx1/k, nx1is one of n+1, n+2, . . . and n+ny1, and ny1is one of 1, 2, . . . , and m. The first down signal has a value of 1 if a phase region of the oversampled data input signal is Rn2, wherein n2is a modulus of nx2/k, nx2is one of n,n−1, . . . and n−ny2, and ny2is one of 0, 1, . . . , and m. The second up signal has a value of 1 if a phase region of the oversampled data input signal is Rn3, wherein n3is a modulus of nx3/k, nx3is one of n, n+1, . . . and n+ny3, and ny3is one of 0, 1, . . . , and m. The second down signal has a value of 1 if a phase region of the oversampled data input signal is Rn4, wherein n4is a modulus of nx4/k, nx2is one of n−1, n−2, . . . and n−ny4, and ny4is one of 1, 2, . . . , and m, wherein n is one of 0, 1, . . . , k−1 and m is an integer of (k−1)/2. The current phase status Φn5is indicated by the current phase status signal.

Another embodiment of a clock data recovery circuit with feedback type phase decision has an output signal of B bits and comprises a sampler, a phase region decision circuit, a phase status register and a multiplexer. The sampler oversamples k*B bits per cycle from a data input signal according to a sampling clock signal. The phase region decision circuit generates a plurality of binary up-down decision signals according to the oversampled data input signal and a current phase status signal. The phase status register generates the current phase status signal according to the binary up-down decision signals. The multiplexer selects data of B bits from the oversampled data input signal according to the current phase status signal. The multiplexer selects the data sampled at a phase Φn. The binary up-down decision signals comprise an up signal and a down signal. The up signal has a value of 1 if a phase region of the oversampled data input signal is Rn1, wherein n1is a modulus of nx1/k, nx1is one of n−m+1, . . . and n−m+1+ny1, and ny1is one of 0, 1, . . . , and m−1. The down signal has a value of 1 if a phase region of the oversampled data input signal is Rn2, wherein n2is a modulus of nx2/k, nx2is one of n+m,n+m−1, . . . and n+m−ny2, and ny2is one of 0, 1, . . . , and m−1, wherein n is one of 0, 1, . . . , k−1 and m is an integer of k/2. The current phase status Φn is indicated by the current phase status signal.

An embodiment of a phase region decision circuit comprises a phase region comparator and a statistical circuit. The phase region decision circuit receives an un-voted and over-sampled input signal from a sampling circuit. The sampling circuit includes a sampler and an XOR circuit block for checking data transition. The sampler over-sampling k*B bits per cycle from a serial input data stream IN according to a sampling clock signal CLK. The phase region decision circuit is coupled to a multiplexer which selects data of B bits from the over-sampled input data stream. The phase region decision circuit comprises a phase region comparator and a statistical circuit. The phase region comparator generates at least one set of up-down decision signals including a first up signal and a first down signal according to the over-sampled input data stream. The statistical circuit generates a set of phase-up and phase-down signals and to a phase status register which provides a current phase status signal coupled to the phase region comparator receiving the set of up-down decision signals and generating a current phase status signal to the phase region comparator for comparison and to the multiplexer for selectively outputting the over-sampled data from the sampling circuit corresponding to the current phase status signal. The multiplexer selects the data sampled in at a phase Φn5, wherein n5is a modulus of nx5/k, and nx5is a sum of k and m. The binary up-down decision signals comprise a first up signal, a first down signal, a second up signal, and a second down signal. The first up signal has a value of 1 if a phase region of the oversampled data input signal is Rn1, wherein n1is a modulus of nx1/k, nx1is one of n+1, n+2, . . . and n+ny1, and ny1is one of 1, 2, . . . , and m. The first down signal has a value of 1 if a phase region of the oversampled data input signal is Rn2, wherein n2is a modulus of nx2/k, nx2is one of n,n−1, . . . and n−ny2, and ny2is one of 0, 1, . . . , and m. The second up signal has a value of 1 if a phase region of the oversampled data input signal is Rn3, wherein n3is a modulus of nx3/k, nx3is one of n, n+1, . . . and n+ny3, and ny3 is one of 0, 1, . . . , and m. The second down signal has a value of 1 if a phase region of the oversampled data input signal is Rn4, wherein n4is a modulus of nx4/k, nx2is one of n−1, n−2, . . . and n−ny4, and ny4is one of 1, 2, . . . , and m, wherein n is one of 0, 1, . . . , k−1 and m is an integer of (k−1)/2. The current phase status Φn5is indicated by the current phase status signal.

An embodiment of a phase region decision circuit comprises a phase region comparator and a statistical circuit. The phase region decision circuit receives an un-voted and over-sampled input signal from a sampling circuit. The sampling circuit includes a sampler and an XOR circuit block for checking data transition. The sampler over-sampling k*B bits per cycle from a serial input data stream IN according to a sampling clock signal CLK. The phase region decision circuit is coupled to a multiplexer which selects data of B bits from the over-sampled input data stream. The phase region decision circuit comprises a phase region comparator and a statistical circuit. The phase region comparator generates at least one set of up-down decision signals including a first up signal and a first down signal according to the over-sampled input data stream. The statistical circuit generates a set of phase-up and phase-down signals and to a phase status register which provides a current phase status signal coupled to the phase region comparator receiving the set of up-down decision signals and generating a current phase status signal to the phase region comparator for comparison and to the multiplexer for selectively outputting the over-sampled data from the sampling circuit corresponding to the current phase status signal. The multiplexer selects data of B bits from the oversampled data input signal according to the current phase status signal. The multiplexer selects the data sampled at a phase Φn. The binary up-down decision signals comprise an up signal and a down signal. The up signal has a value of 1 if a phase region of the oversampled data input signal is Rn1, wherein n1is a modulus of nx1/k, nx1is one of n−m+1, . . . and n−m+1+ny1, and ny1is one of 0, 1, . . . , and m−1. The down signal has a value of 1 if a phase region of the oversampled data input signal is Rn2, wherein n2is a modulus of nx2/k, nx2 is one of n+m,n+m−1, . . . and n+m−ny2, and ny2 is one of 0, 1, . . . , and m−1, wherein n is one of 0, 1, . . . , k−1 and m is an integer of k/2. The current phase status Φn5is indicated by the current phase status signal.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 3Ais a block diagram of a clock data recovery circuit with feedback type phase detection according to an embodiment of the invention. The clock data recovery circuit provides an output signal of B bits and comprises a sampler310, an XOR circuit block320, a phase region decision circuit330, a phase status register350, a multiplexer360, and a post-process logic circuit370. The sampler310receives a serial input data stream IN and a sampling clock signal CLK and generates an oversampled input data stream IN′. The XOR circuit block320is coupled to the sampler310and receives the oversampled input data stream IN′. The phase region decision circuit330is coupled to the XOR circuit block320and generates a plurality of binary up-down decision signals according to the oversampled input data stream IN′ and a current phase status signal CPS. The phase region decision circuit330comprises a voter335, a phase region comparator340, and two divided by N circuits345and345′. The voter335is coupled to the XOR circuit block320and generates a voting result according to the oversampled input data stream IN′. The phase region comparator340is coupled to the voter335and generates the binary up-down decision signals according to the voting result. The two divided by N circuits345and345′ are coupled to the phase region comparator340. The phase status register350is coupled to the divided by N circuits345and345′ and generates the current phase status signal CPS according to the binary up-down decision signals. The multiplexer360is coupled to the phase status register350, the phase region decision circuit330and the sampler310. The multiplexer360selects data of B bits from the oversampled input data stream IN′ according to the current phase status signal CPS. The post process logic circuit370is coupled to the sampler310, the phase decision circuit330and the multiplexer360. The post process logic circuit370generates the output signal OUT according to the data and the current phase status signal CPS.

In FIG.3A., the serial input data stream IN is oversampled by the sampler310. The number of bit samples in each bit period is nominally an oversampling ratio (k). The reference character B represents the number of bits sampled in a cycle. Since there are k*B sampling clocks in the sampling clock signal in a cycle, the oversampled input data stream IN′ has k*B bits in a cycle. Every two consecutive data bits of the oversampled input data stream IN′ are sent to an XOR logic in the XOR circuit block320, as shown inFIG. 4. InFIG. 4, the data bits of the oversampled input data stream IN′ are represented by Sxyz, wherein x is the number of the sampling cycle, y the yth bit of the input data stream IN in a sampling cycle, and z in which phase the sampling occurs. The output signal Xx′y′z′ of the XOR logic equals “1” when the input data stream IN transitions between two consecutive samplings. In other words, the XOR logic detects in which phase region the input data stream IN transitions. For example, if X213has a value of 1, the first bit in the input data stream IN transitions in the third phase region. In the voter335, the output signal of several XOR logics, B XOR logics more specifically, corresponding to the same phase region is summed, as shown inFIG. 5. The summed number of each region is sent to a comparator338inside the voter335and the comparator338determines in which region data transition is most likely to occur. The voting result of the voter335is sent to the phase region comparator340. The phase region comparator340compares the current phase status and the result of the current vote and generates binary up-down decision signals. The binary up-down decision signals comprise a first up signal UP1, a first down signal DN1, a second up signal UP2, and a second down signal DN2. The first up signal UP1has a value of 1 if a phase region of the oversampled input data stream IN′ is Rn1, wherein n1is a modulus of nx1/k, nx1is one of n+1,n+2, . . . and n+ny1, and ny1is one of 1, 2, . . . , and m. The first down signal DN1has a value of 1 if a phase region of the oversampled input data stream IN′ is Rn2, wherein n2is a modulus of nx2/k, nx2is one of n,n−1, . . . and n−ny2, and ny2is one of 0, 1, . . . , and m. The second up signal UP2has a value of 1 if a phase region of the oversampled input data stream IN′ is Rn3, wherein n3is a modulus of nx3/k, nx3is one of n,n+1, . . . and n+ny3, and ny3is one of 0, 1, . . . , and m. The second down signal DN2has a value of 1 if a phase region of the oversampled input data stream IN′ is Rn4, wherein n4is a modulus of nx4/k, nx2is one of n−1, n−2, . . . . and n−ny4, and ny4is one of 1, 2, . . . , and m, wherein n is one of 0, 1, . . . , k−1 and m is an integer of (k−1)/2. In the embodiment, the current phase status Φn5is indicated by the current phase status signal.

The first divided by N circuit345receives the first up signal UP1and the first down signal DN1and generates a phase-up signal PH_UP and a first phase-hold signal PH_hold1. The second divided by N circuit345′ receives the second up signal UP2and the second down signal DN2and generates a phase-down signal PH_DN and a second phase-hold signal PH_hold2. The phase status register350dynamically adjusts and generates a current phase status signal CPS, indicating in which phase the output signal should be, according to the phase-up, phase-down, and phase-hold signals. The current phase status signal CPS is fed back to the phase region comparator340such that the phase region comparator340stays informed of whether the current region needs to be changed. The current phase status signal CPS is an indicator of from which phase region the output data signal should be selected. As a result, the multiplexer360selects data of B bits from the oversampled input data stream IN′ according to the current phase status signal CPS. More, specifically, the multiplexer360selects the data sampled in at a phase Φn5, wherein n5is a modulus of nx5/k, and nx5is a sum of k and m.

With oversampling ratio K of 3 (K=3) as an example, as shown inFIG. 6, if the current phase status is Φ2, the decision rule of the phase region comparator340is defined as follows. The first up signal UP1is defined, by the phase region comparator340, as 1 when the result of the current vote is the second region (R2). The first down signal DN1is defined as 1 when the result of the current vote is the first region (R1) or either the 0th region (R0) or the first region (R1). The second up signal UP2is defined as1when the result of the current vote is the first region (R1) or either the first region (R1) or the second region (R2). The second down signal DN2is defined as 1 when the result of the current vote is 0th region (R0). After processing of the two divided_by_N circuits345and345′, two OR logics346and346′ and the phase status register350, a signal is fed back to the phase region comparator340and the multiplexer360. Accordingly, the multiplexer360selects the data bits sampled at a phase Φ2. In other words, the data bits are selected in a phase which is farthest from data transition.

FIGS. 7A and 7Bare schematic diagrams of data processing of a post process logic circuit370. The post process logic circuit370is used for data processing when the phase region in which the data is sampled suddenly changes. If oversampling ratio equals 5 (k=5), for example. when the data is originally sampled in a phase region Φ0and later in a phase region Φ4, an underflow event occurs, as shown inFIG. 7A. The post process logic circuit inserts an extra bit S300into the data stream. The oversampled input data stream from S200to S290is sampled at a phase Φ0and the oversampled input data stream from S300to S394at a phase Φ4. Conversely, when the data is originally sampled in a phase region Φ4and later in a phase region Φ0, an overflow event occurs, as shown inFIG. 7B. The post process logic circuit drops a bit S300(not shown inFIG. 7B) from the data stream. The oversampled input data stream from S204to S294is sampled at a phase Φ4and the oversampled input data stream from S310to S390at a phase φ0.

FIG. 3Bshows a variation of the clock data recovery circuit inFIG. 3A, differing in that the phase region decision circuit comprises a plurality of phase region comparators340′, first and second voters335and335′, and two divided by N circuits345and345′. The phase region comparators340′ are coupled to the XOR circuit block320and respectively generate the binary up-down decision signals according to XORed results of the oversampled input data stream IN′. The binary up-down decision signals have the same content as inFIG. 3A. The first voter335receives the first up signals UP1and first down signals DN1and generates first up and down voting signals according thereto. The first up voting signal UPX1has a value of 1 if a sum of the first up signals UP1exceeds the first down signals DN1and a value of 0 if the sum is the same. The first down voting signal DNX1has a value of 1 if a sum of the first down signals DN1exceeds the first up signals UP1and a value of 0 if the sum is the same. The second voter335′ receives the second up signals UP2and second down signals DN2and generates second up and down voting signals according thereto. The second up voting signal UPX2has a value of 1 if a sum of the second up signals UP2exceeds the second down signals DN2and a value of 0 if the sum is the same. The second down voting signal DNX2has a value of 1 if a sum of the second down signals DN2exceeds the second up signals UP2and a value of 0 if the sum is the same. The divided by N circuits345and345′ are respectively coupled between the first and second voters335and335′ and the phase status register350and generate a phase-up signal, a phase-down signal, and two phase-hold signals.

FIG. 8Ashows a clock data recovery circuit with feedback type phase detection according to another embodiment of the invention. The clock data recovery circuit provides an output signal of B bits and comprises a sampler310, an XOR circuit block320, a phase region decision circuit330, a phase status register350, a multiplexer360, and a post-process logic circuit370. The sampler310receives a serial input data stream IN and a sampling clock signal CLK and generates an oversampled input data stream IN′. The XOR circuit block320is coupled to the sampler310and receives the oversampled input data stream IN′. The phase region decision circuit330is coupled to the XOR circuit block320and generates a plurality of binary up-down decision signals according to the oversampled input data stream IN′ and a current phase status signal CPS. The phase region decision circuit330comprises a voter335, a phase region comparator340, and a divided by N circuit345. The voter335is coupled to the XOR circuit block320and generates a voting result according to the oversampled input data stream IN′. The phase region comparator340is coupled to the voter335and generates the binary up-down decision signals according to the voting result. The divided by N circuit345is coupled to the phase region comparator340. The phase status register350is coupled to the divided by N circuit330and generates the current phase status signal CPS according to the binary up-down decision signals. The multiplexer360is coupled to the phase status register350, the phase region decision circuit330and the sampler310. The multiplexer360selects data of B bits from the oversampled input data stream IN′ according to the current phase status signal CPS. The post process logic circuit370is coupled to the sampler310, the phase decision circuit330and the multiplexer360. The post process logic circuit370generates the output signal OUT according to the data and the current phase status signal CPS.

Most circuit blocks in this embodiment are the same as the first embodiment. Thus, only the phase region decision circuit330and the phase status register350are described in detail herein. In the voter335, the output signal of several XOR logics, B XOR logics more specifically, corresponding to the same phase region is summed, as shown inFIG. 4. The summed number of each region is sent to a comparator338inside the voter335and the comparator338determines in which region data transition is most likely to occur. The voting result of the voter335is sent to the phase region comparator340. The phase region comparator340compares the current phase status and the result of the current vote and generates binary up-down decision signals. The binary up-down decision signals comprise an up signal UP and a down signal DN. The up signal UP has a value of 1 if a phase region of the oversampled input data stream is Rn1, wherein n1is a modulus of nx1/k, nx1is one of n−m+1, . . . and n−m+1+ny1, and ny1is one of 0, 1, . . . , and m−1. The down signal DN has a value of 1 if a phase region of the oversampled input data stream is Rn2, wherein n2is a modulus of nx2/k, nx2is one of n+m,n+m−1, . . . and n+m−ny2, and ny2is one of 0, 1, . . . , and m−1, wherein n is one of 0, 1, . . . , k−1 and m is an integer of k/2. In the embodiment, a current phase status Φn is indicated by the current phase status signal CPS.

The divided by N circuit345receives the up signal UP and the down signal DN and generates a phase-up signal PH_UP and a phase-down signal PH_DN. The phase status register350dynamically adjusts and generates a current phase status signal CPS, indicating in which phase the output signal should be, according to the phase-up and phase-down signals. The current phase status signal CPS is fed back to the phase region comparator340such that the phase region comparator340stays informed of whether the current region needs to be changed. The current phase status signal CPS is an indicator of from which phase region the output data signal should be selected. As a result, the multiplexer360selects data of B bits from the oversampled input data stream IN′ according to the current phase status signal CPS. More specifically, the multiplexer360selects the data sampled at a phase Φn.

If oversampling ratio K of 4 (K=4) is taken as an example, as shown inFIG. 9, if the current phase status is Φ1, the decision rule of the phase region comparator is defined as follows. The up signal UP is defined, by the phase region comparator, as 1 when the result of the current vote is the 0th region (R0), or either of the 0th region (R0) and the first region (R1). The down signal DN is defined as 1 when the result of the current vote is the third region (R3), or either of the third region (R3) and the second region (R2). After processing of the divided_by_N circuit345, the OR logic346and the phase status register350, a signal is fed back to the phase region comparator340and the multiplexer360. Accordingly, the multiplexer3606selects the data bits which are sampled at Φ1. In other words, the data bits are selected in a phase which is farthest from data transition.

FIG. 8Bshows a variation of the clock data recovery circuit inFIG. 8A, differing in that the phase region decision circuit comprises a plurality of phase region comparators340′, a voter335, and a divided by N circuit345. The phase region comparators340′ are coupled to the XOR circuit block320and respectively generate the binary up-down decision signals according to XORed results of the oversampled input data stream IN′. The binary up-down decision signals have the same content as inFIG. 8A. The voter335receives the up and down signals and generates up and down voting signals according thereto. The up voting signal UPX has a value of 1 if a sum of the up signals UP exceeds the down signals DN and a value of 0 if the sum is the same. The down voting signal DNX has a value of 1 if a sum of the down signals DN exceeds the up signals UP and a value of 0 if the sum is the same. The divided by N circuit345is coupled between the voter335and the phase status register350and generates the phase-up and phase-down signals according to the up and down voting signals UPX and DNX.

FIG. 10Ais a block diagram comprising a phase region decision circuit according to an embodiment of the invention as disclosed inFIG. 3A. The phase region decision circuit330receives an un-voted and over-sampled input signal from a sampling circuit390. The sampling circuit390includes a sampler310and an XOR circuit block320for checking data transition. The sampler310over-sampling k*B bits per cycle from a serial input data stream IN according to a sampling clock signal CLK. The phase region decision circuit330is coupled to a multiplexer360which selects data of B bits from the over-sampled input data stream. The phase region decision circuit330comprises a phase region comparator340and a statistical circuit380. The phase region comparator340generates at least one set of up-down decision signals including a first up signal UP1, a first down signal DN1, a second up signal UP2and a second down signal DN2according to the over-sampled input data stream. The statistical circuit380generates a set of phase-up and phase-down signals PH_UP and PH_DN to a phase status register350which provides a current phase status signal CPS to the phase region comparator340receiving the set of up-down decision signals and generates a current phase status signal CPS to the phase region comparator340for comparison and to the multiplex for selectively outputting the over-sampled data from the sampling circuit390corresponding to the current phase status signal CPS. Moreover, The statistical circuit380comprises two divided by N circuits345and345′ coupled to the phase region comparator340and receiving the up-down decision signals and two OR circuits346and346′ respectively coupled to the divided by N circuits345and345′. The sampler310receives a serial input data stream IN and a sampling clock signal CLK and generates an oversampled input data stream IN′. The XOR circuit block320is coupled to the sampler310and receives the oversampled input data stream IN′. The phase region decision circuit330is coupled to the XOR circuit block320and generates a plurality of binary up-down decision signals according to the oversampled input data stream IN′ and a current phase status signal CPS. The voter335is coupled to the XOR circuit block320and generates a voting result according to the oversampled input data stream IN′. The phase region comparator340is coupled to the voter335and generates the binary up-down decision signals according to the voting result. The two divided by N circuits345and345′ are coupled to the phase region comparator340. The phase status register350is coupled to the divided by N circuits345and345′ and generates the current phase status signal CPS according to the binary up-down decision signals. The multiplexer360is coupled to the phase status register350, the phase region decision circuit330and the sampler310. The multiplexer360selects data of B bits from the oversampled input data stream IN′ according to the current phase status signal CPS. The post process logic circuit370is coupled to the sampler310, the phase decision circuit330and the multiplexer360. The post process logic circuit370generates the output signal OUT according to the data and the current phase status signal CPS.

FIG. 10Bshows a variation of the phase region decision circuit inFIG. 10Aaccording to the embodiment as disclosed inFIG. 3B, differing in that the phase region decision circuit comprises a plurality of phase region comparators340′, first and second voters335and335′, and two divided by N circuits345and345′. The phase region comparators340′ are coupled to the XOR circuit block320and respectively generate the binary up-down decision signals according to XORed results of the oversampled input data stream IN′. The binary up-down decision signals have the same content as inFIG. 10A. The first voter335receives the first up signals UP1and first down signals DN1and generates first up and down voting signals according thereto. The first up voting signal UPX1has a value of 1 if a sum of the first up signals UP1exceeds the first down signals DN1and a value of 0 if the sum is the same. The first down voting signal DNX1has a value of 1 if a sum of the first down signals DN1exceeds the first up signals UP1and a value of 0 if the sum is the same. The second voter335′ receives the second up signals UP2and second down signals DN2and generates second up and down voting signals according thereto. The second up voting signal UPX2has a value of 1 if a sum of the second up signals UP2exceeds the second down signals DN2and a value of 0 if the sum is the same. The second down voting signal DNX2has a value of 1 if a sum of the second down signals DN2exceeds the second up signals UP2and a value of 0 if the sum is the same. The divided by N circuits345and345′ are respectively coupled between the first and second voters335and335′ and the phase status register350and generate a phase-up signal, a phase-down signal, and two phase-hold signals.

FIG. 11Ashows a phase region decision circuit according to an embodiment of the invention as disclosed inFIG. 8A. The phase region decision circuit330receives an un-voted and over-sampled input signal from a sampling circuit390. The sampling circuit390includes a sampler310and an XOR circuit block320for checking data transition. The sampler310over-sampling k*B bits per cycle from a serial input data stream IN according to a sampling clock signal CLK. The phase region decision circuit330is coupled to a multiplexer360which selects data of B bits from the over-sampled input data stream. The phase region decision circuit330comprises a phase region comparator340and a statistical circuit380. The phase region comparator340generates at least one set of up-down decision signals including a first up signal UP1and a first down signal DN1according to the over-sampled input data stream. The statistical circuit380generates a set of phase-up and phase-down signals PH_UP and PH_DN to a phase status register350which provides a current phase status signal CPS coupled to the phase region comparator340receiving the set of up-down decision signals and generating a current phase status signal CPS to the phase region comparator340for comparison and to the multiplexer for selectively outputting the over-sampled data from the sampling circuit390corresponding to the current phase status signal CPS. Moreover, The statistical circuit380comprises two divided by N circuits345and345′ coupled to the phase region comparator340and receiving the up-down decision signals and two OR circuits346and346′ respectively coupled to the divided by N circuits345and345′. The sampler310receives a serial input data stream IN and a sampling clock signal CLK and generates an oversampled input data stream IN′. The XOR circuit block320is coupled to the sampler310and receives the oversampled input data stream IN′. The phase region decision circuit330is coupled to the XOR circuit block320and generates a plurality of binary up-down decision signals according to the oversampled input data stream IN′ and a current phase status signal CPS. The phase region decision circuit330comprises a voter335, a phase region comparator340, and a divided by N circuit345. The voter335is coupled to the XOR circuit block320and generates a voting result according to the oversampled input data stream IN′. The phase region comparator340is coupled to the voter335and generates the binary up-down decision signals according to the voting result. The divided by N circuit345is coupled to the phase region comparator340. The phase status register350is coupled to the divided by N circuit330and generates the current phase status signal CPS according to the binary up-down decision signals. The multiplexer360is coupled to the phase status register350, the phase region decision circuit330and the sampler310. The multiplexer360selects data of B bits from the oversampled input data stream IN′ according to the current phase status signal CPS. The post process logic circuit370is coupled to the sampler310, the phase decision circuit330and the multiplexer360. The post process logic circuit370generates the output signal OUT according to the data and the current phase status signal CPS.

FIG. 11Bshows a variation of the phase region decision circuit inFIG. 11Aaccording to the embodiment as disclosed inFIG. 8B, differing in that the phase region decision circuit comprises a plurality of phase region comparators340′, first and second voters335and335′, and two divided by N circuits345and345′. The phase region comparators340′ are coupled to the XOR circuit block320and respectively generate the binary up-down decision signals according to XORed results of the oversampled input data stream IN′. The binary up-down decision signals have the same content as inFIG. 3A. The first voter335receives the first up signals UP1and first down signals DN1and generates first up and down voting signals according thereto. The first up voting signal UPX1has a value of 1 if a sum of the first up signals UP1exceeds the first down signals DN1and a value of 0 if the sum is the same. The first down voting signal DNX1has a value of 1 if a sum of the first down signals DN1exceeds the first up signals UP1and a value of 0 if the sum is the same. The second voter335′ receives the second up signals UP2and second down signals DN2and generates second up and down voting signals according thereto. The second up voting signal UPX2has a value of 1 if a sum of the second up signals UP2exceeds the second down signals DN2and a value of 0 if the sum is the same. The second down voting signal DNX2has a value of 1 if a sum of the second down signals DN2exceeds the second up signals UP2and a value of 0 if the sum is the same. The divided by N circuits345and345′ are respectively coupled between the first and second voters335and335′ and the phase status register350and generate a phase-up signal, a phase-down signal, and two phase-hold signals.