Liquid crystal display having reduced kickback effect

A liquid crystal display (LCD), according to an exemplary embodiment of the present invention, includes a first pixel formed between the first and second gate lines, the first and the second data lines, a first subpixel configured to have applied thereto a first data voltage and a second subpixel configured to have applied thereto a second data voltage lower than the first data voltage, a second pixel formed between the second and third gate lines, the first and second data lines, and having a third subpixel configured to have applied thereto a third data voltage and a fourth subpixel configured to have applied thereto a fourth data voltage lower than the third data voltage. The first subpixel and the third subpixel are connected to a first thin film transistor and a third thin film transistor respectively, the first thin film transistor and the third thin film transistor have source electrodes connected to the first data line and the second data line respectively, and each of the source electrodes has an open portion surrounding a portion of a drain electrode, and wherein an open direction of the source electrode of the first thin film transistor is opposite to an open direction of the source electrode of the third thin film transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to and the benefit of Korean Patent Application No. 10-2009-0012014, filed in the Korean Intellectual Property Office on Feb. 13, 2009, the entire contents of which are incorporated herein by reference.

BACKGROUND

1. Technical Field

The present invention relates to a liquid crystal display and a manufacturing method thereof.

2. Related Art

A liquid crystal display (LCD) is a type of flat panel display (FPD) having two display panels with field generating electrodes, such as pixel electrodes and a common electrode, and a liquid crystal layer interposed between the two display panels. In the LCD, voltages are applied to the field generating electrodes so as to generate an electric field over the liquid crystal (LC) layer, and then the alignment of LC molecules of the LC layer is determined by the electric field. Accordingly, the polarization of incident light is controlled, thereby performing image display.

Among the LCDs, a vertical alignment (VA) mode LCD, which aligns LC molecules such that their long axes are perpendicular to the panels in the absence of an electric field, is spotlighted because of its high contrast ratio and wide reference viewing angle. In the VA mode LCD, to obtain the wide viewing angle, a plurality of domains in which the alignment directions of the LC molecules are different may be formed in one pixel.

Methods in which a minute slit or a cutout is formed in the field generating electrodes or a protrusion is formed on the field generating electrodes have been proposed as means for forming the plurality of domains in one pixel. In this method, the plurality of domains may be formed by aligning the LC molecules vertically with respect to a fringe field generated between the edges of the cutout or the protrusion and the field generating electrodes facing the edges. On the other hand, the LCD of the VA mode has lower lateral visibility compared with frontal visibility such that one pixel is divided into two subpixels and different voltages are applied to the subpixels to solve this problem.

It should be appreciated that the above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

SUMMARY

A liquid crystal display (LCD), according to an exemplary embodiment of the present invention, includes a plurality of pixels arranged in a matrix shape, each of the pixels having a first subpixel and a second subpixel, wherein the pixels respectively include a first thin film transistor transmitting a first data voltage to the first subpixel, the first thin film transistor having a first source electrode, a first drain electrode, and a first gate electrode, and a second thin film transistor transmitting a second data voltage to the second subpixel, the second thin film transistor having a second source electrode, a second drain electrode, and a second gate electrode, wherein a relative position of the first drain electrode with respect to the first source electrode is opposite to a relative position of the second drain electrode with respect to the second source electrode in each pixel.

The first source electrode may be disposed on a left side of the first drain electrode and the second source electrode may be disposed on a right side of the second drain electrode, with reference to a length direction of the pixel. The first source electrode may include a first open portion enclosing a portion of the first drain electrode, the second source electrode may include a second open portion enclosing a portion of the second drain electrode, and an open direction of the first open portion may be opposite to an open direction of the second open portion. A first data line and a second data line respectively disposed on a first side and a second side of each pixel column among the pixels may be further included. With reference to a length direction of the pixel, right and left positions of the first thin film transistor and the second thin film transistor of two pixels neighboring in at least one direction of a row direction and a column direction may be opposite to each other for the two pixels. The first source electrode of one pixel of two pixels neighboring in at least one direction of a row direction and a column direction among the pixels may be connected to the first data line, and the first source electrode of the other pixel may be connected to the second data line. The first data voltage and the second data voltage may have different magnitudes and may be obtained from one image information.

A method for manufacturing a liquid crystal display including a plurality of pixels arranged in a matrix shape, each of the pixels having first subpixel and a second subpixel, according to an exemplary embodiment of the present invention, includes: depositing a first conductive material layer on a substrate; coating a first photosensitive film on the first conductive material layer; forming a first gate electrode and a second gate electrode by aligning a first photomask over the first photosensitive film and exposing the first photosensitive film to light by using a light exposer scanning the first photosensitive film; and depositing a second conductive material layer on the first gate electrode and the second gate electrode; coating a second photosensitive film on the second conductive material layer, and forming a first drain electrode partially overlapping the first gate electrode, a second drain electrode partially overlapping the second gate electrode, a first source electrode facing the first drain electrode, and a second source electrode facing the second drain electrode by aligning a second photomask over the second photosensitive film and exposing the second photosensitive film to light by using the light exposer scanning the second photosensitive film. The first gate electrode, the first source electrode, and the first drain electrode may form a first thin film transistor of the first subpixel, and the second gate electrode, the second source electrode, and the second drain electrode form a first thin film transistor of the second subpixel, and wherein an acute angle between a scanning direction of the light exposer and at least one of a first boundary line a second boundary line is more than 45 degrees and is equal to or less than 90 degrees, the first boundary line being a boundary line between the portion at which the first drain electrode and the first gate electrode overlap each other and the portion at which the first drain electrode and the first gate electrode do not overlap each other, the second boundary line being a boundary line between the portion at which the second drain electrode and the second gate electrode overlap each other and the portion that the second drain electrode and the second gate electrode do not overlap each other.

A relative position of the first drain electrode with respect to the first source electrode may be opposite to a relative position of the second drain electrode with respect to the second source electrode. The first source electrode may include a first open portion enclosing a portion of the first drain electrode, the second source electrode may include a second open portion enclosing a portion of the second drain electrode, and an open direction of the first open portion may be opposite to an open direction of the second open portion.

The method may include forming a first data line and a second data line respectively disposed on a first side and a second side of each pixel column among the pixels. With reference to a length direction of the pixel, right and left positions of the first thin film transistor and the second thin film transistor of two pixels neighboring in at least one direction of a row direction and a column direction may be opposite to each other for the two pixels. The first source electrode of one pixel of two pixels neighboring in at least one direction of a row direction and a column direction may be connected to the first data line, and the first source electrode of the other pixel may be connected to the second data line. The first data voltage and the second data voltage may have different magnitudes, and may be obtained from one image information.

DETAILED DESCRIPTION

A liquid crystal display (LCD), according to exemplary embodiments of the present invention, will be described with reference toFIG. 1toFIG. 3.FIG. 1is a block diagram of a LCD, according to an exemplary embodiment of the present invention.FIG. 2is a view of one pixel in a LCD, according to an exemplary embodiment of the present invention.FIG. 3is an equivalent circuit diagram of one pixel in a LCD, according to an exemplary embodiment of the present invention.

Referring toFIG. 1, a LCD according to an exemplary embodiment of the present invention includes a liquid crystal (LC) panel assembly300, a gate driver400, and a data driver500. In a view of an equivalent circuit, the display panel assembly300includes a plurality of signal lines G1-Gn and D1-D2m, and a plurality of pixels PX connected thereto and arranged substantially in a matrix. Meanwhile, in a viewpoint of the structure ofFIG. 2, the LC panel assembly300includes a lower panel100and an upper panel200facing each other, and a LC layer3interposed therebetween.

The signal lines G1-Gn and D1-D2mthat are provided in the lower panel100include a plurality of gate lines G1-Gn transmitting gate signals and a plurality of data lines D1-D2mtransmitting data signals. The gate lines G1-Gn extend in an approximate row direction and run substantially parallel to each other, and the image data lines D1-D2mextend in an approximate column direction and run substantially parallel to each other. One of the data lines D1-D2mis respectively formed on both sides of one pixel PX. The signal lines may further include storage electrode lines parallel to the gate lines G1-Gn as well as the gate lines G1-Gn and the data lines D1-D2m.

Referring toFIG. 3, each pixel PX includes a pair of a first subpixel PXa and a second subpixel PXb. Each of the first and second subpixels PXa and PXb includes a first switching element Qa and a second switching element Qb that are connected to a corresponding gate line121iand data lines171jand171(j+1), and a first LC capacitor Clca and a second LC capacitor Clcb, and a first storage capacitor Csta and a second storage capacitor Cstb.

The first switching element Qa and the second switching element Qb are three terminal elements, such as a thin film transistor provided on the lower panel100, and include a control terminal connected to the gate line121i, respective input terminals connected to different data lines171jand171(j+1) from each other, and an output terminal respectively connected to the first LC capacitor Clca and the second LC capacitor Clcb, and the first storage capacitor Csta and the second storage capacitor Cstb.

Referring toFIG. 2, the first LC capacitor Clca uses a first subpixel electrode191aof the lower panel100and a common electrode270of the upper panel200as two terminals, and the LC layer3between the two electrodes191aand270functions as a dielectric material. In one aspect, the second LC capacitor Clcb uses a second subpixel electrode191bof the lower panel100and the common electrode270of the upper panel200as two terminals, and the LC layer3between the two electrodes191aand270functions as a dielectric material. The common electrode270is formed on the whole surface of the upper panel200and receives a common voltage Vcom, and the first and second subpixel electrodes191aand191bform one pixel electrode191.

Each of the first and second storage capacitors Csta and Cstb, respectively serving as an assistant to the first and second LC capacitors Clca and Clcb, is formed as each of the first and second subpixel electrodes191aand191boverlap a signal line transmitting a common voltage Vcom, with an insulator interposed therebetween. Alternatively, the first and second storage capacitors Csta and Cstb may include the first and second subpixel electrodes191aand191band an adjacent gate line that is called a previous gate line, which overlaps the pixel electrode191via an insulator.

For color display, each pixel uniquely represents one of primary colors (i.e., spatial division) or each pixel sequentially represents the primary colors in turn (i.e., temporal division) such that a spatial or temporal sum of the primary colors is recognized as a desired color. An example of the primary colors may be three primary colors, such as red, green, and blue.FIG. 2shows an example of the spatial division in which each pixel includes a color filter230representing one of the primary colors of red, green, or blue in an area of the upper panel200facing the pixel electrode191. Alternatively, the color filter230may be provided on or under the pixel electrode191on the lower panel100. In one aspect, the LC panel assembly300may include at least one polarizer (not shown).

Referring toFIG. 1, the gate driver400is connected to the gate lines G1-Gn of the LC panel assembly300and applies gate signals, which are a combination of a gate-on voltage Von that may turn on the first and second switching elements Qa and Qb and a gate-off voltage Voff that may turn them off, to the gate lines G1-Gn. The data driver500is connected to the data lines D1-D2mof the LC panel assembly300and applies the data voltages to the data lines D1-D2m. A signal controller (not shown) for controlling the operation of the gate driver400and the data driver500may be included.

Next, an operation of the LCD will be described. In one implementation, if input image signals and input control signals for controlling the display thereof are input from an external graphics controller (not shown), the data driver500applies the data voltages of the pixels of one row to the corresponding to the data lines D1-D2maccording to the data control signal. The first and second subpixels PXa and PXb of one pixel PX may be applied with different data voltages that are previously set for one input image signal.

The gate driver400supplies a gate-on voltage Von to the gate lines G1-Gn according to a gate control signal, thereby turning on the first and second switching elements Qa and Qb connected to the gate lines G1-Gn. Then, the data voltages supplied to the data lines D1-D2mare supplied to the corresponding first and second subpixels PXa and PXb through the turned-on first and second switching elements Qa and Qb.

The difference between the data voltages applied to the first and second subpixels PXa and PXb and the common voltage Vcom is expressed as a charged voltage of the first and second LC capacitors Clca and Clcb, i.e., a pixel voltage. The arrangement of the LC molecules is changed depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the LC layer3. The change of the polarization is converted into a change of light transmittance by the polarizer attached to the display panels100and200. Here, the voltages charged to the first and second LC capacitors Clca and Clcb of one pixel PX are different such that the lateral gamma curve maximally approximates the frontal gamma curve. In this way, the lateral visibility can be enhanced. By repeating this procedure by a unit of a horizontal period (also referred to as “1H”), the gate-on voltage Von is sequentially applied to all gate lines G1-Gn and the data voltage Vd is applied to all pixels PX, thereby displaying images for a frame.

When the next frame starts after one frame finishes, the inversion control signal RVS applied to the data driver500is controlled such that the polarity of the data signals applied to each pixel PX is reversed (which may be referred to as “frame inversion”). Here, the polarity of the data voltages flowing in one data line is periodically reversed during one frame according to the characteristic of the inversion signal (for example row inversion and dot inversion), or the polarity of the data voltages applied to the row of one pixel may be reversed (for example column inversion and dot inversion).

Next, the detailed structure of the LCD, according to exemplary embodiments of the present invention, will be described with reference toFIG. 4toFIG. 7.FIG. 4is a layout view of a lower panel of a LCD, according to an exemplary embodiment of the present invention.FIG. 5is a layout view of an upper panel of a LCD, according to an exemplary embodiment of the present invention.FIG. 6is a layout view of a LCD including the lower panel ofFIG. 4and the upper panel ofFIG. 5.FIG. 7is a cross-sectional view of the LCD shown inFIG. 6taken along the line VII-VII.

Referring toFIG. 4toFIG. 7, a LCD according to an exemplary embodiment of the present invention includes a lower panel100and an upper panel200facing each other, and a LC layer3interposed between the lower and upper panels100and200.

The lower panel100will be described. A plurality of gate conductors including a plurality of gate lines121(i−1) and121iare formed on an insulating substrate110. The gate lines121(i−1) and121itransmit gate signals and extend in a transverse direction. Each of gate lines121(i−1),121iincludes a plurality of pairs of first and second gate electrodes124aand124bprotruding upward. Each of the first and second gate electrodes124aand124bincludes a pair of edges substantially perpendicular to the gate lines121(i−1) and121i.

A gate insulating layer140is formed on the gate conductors. The gate insulating layer140may be made of an inorganic insulator such as silicon nitride (SiNx) or silicon oxide (SiOx). A plurality of pairs of first and second semiconductor islands154aand154bthat are preferably made of amorphous silicon (a-Si) or polysilicon are formed on the gate insulating layer140. The first and second semiconductor islands154aand154bare respectively disposed on the first and second gate electrodes124aand124b.

A pair of ohmic contact islands (not shown) are formed on each first semiconductor island154a, and a pair of ohmic contact islands163band165bare formed on each second semiconductor island154b. The ohmic contact islands163band165bmay be made of a material such as n+ hydrogenated amorphous silicon in which an n-type impurity such as phosphorus is doped with a high concentration, or of silicide.

A plurality of pairs of first and second data lines171jand171(j+1) and a plurality of pairs of first and second drain electrodes175aand175bare formed on the ohmic contacts163band165band the gate insulating layer140.

The first and second data lines171jand171(j+1) transmit data signals, and extend substantially in the longitudinal direction thereby intersecting the gate lines121(i−1) and121i. The first and second data lines171jand171(j+1) respectively include a plurality of first and second source electrodes173aand173bextending toward the first and second gate electrodes124aand124b. Each of the first source electrode173aand the second source electrode173bmay have a shape of the letter “C” or a reversed “C” shape, and an open portion. The open portion of the first source electrode173aand the open portion of the second source electrode173bmay face each other. Alternatively, the first and second source electrodes173aand173bmay have various shapes and may be variously disposed.

The first and second drain electrodes175aand175bare separated from each other, and are separated from the data lines171jand171(j+1). The first and second drain electrodes175aand175brespectively include a bar-shaped end portion facing the first and second source electrodes173aand173bwith respect to the first and second gate electrodes124aand124b, respectively, and another end portion having a wide area. A portion of the bar-shaped end portion of the first drain electrodes175ais enclosed by the first source electrode173a, and overlaps the right edge of the first gate electrode124aand may extend in the transverse direction. A portion of the bar-shaped end portion of the second drain electrodes175bis enclosed by the second source electrode173b, and overlaps the left edge of the second gate electrode124band may extend in the transverse direction. Differently fromFIG. 4toFIG. 7, the first and second drain electrodes175aand175bmay have various shapes such as a rectangle shape, a square shape, and a bent shape.

The first/second gate electrode124a/124b, the first/second source electrode173a/173b, and the first/second drain electrode175a/175brespectively constitute the first/second thin film transistor Qa/Qb together with the first/second semiconductor154a/154b. The channel of the first/second thin film transistor Qa/Qb is formed in the first/second semiconductor154a/154bbetween the first/second source electrode173a/173band the first/second drain electrode175a/175b. In the present exemplary embodiment, the relative position of the first drain electrode175awith respect to the first source electrode173aof the first thin film transistor Qa, and the relative position of the second drain electrode175bwith respect to the second source electrode173bof the second thin film transistor Qb are opposite to each other. For example, as shown inFIG. 4andFIG. 6, when the first drain electrode175ais disposed on the right side of the first source electrode173a, the second drain electrode175bmay be disposed on the left side of the second drain electrode175b.

The ohmic contacts163band165bare formed only between the underlying semiconductors154aand154band the overlying data lines171jand171(j+1) and the drain electrodes175aand175b, and reduce the contact resistance therebetween. The first and second semiconductors154aand154bhave a portion that is exposed without being covered by the data conductors173a,173b,175a, and175b.

A passivation layer180is formed on the data lines171jand171(j+1) and the drain electrodes175aand175band exposed semiconductors154aand154b. The passivation layer180may be made of the inorganic insulator such as silicon nitride or silicon oxide, an organic insulator, or an insulating material having a low dielectric constant. The dielectric constant of the organic insulator and the insulating material may be less than 4.0, and the organic insulator may have photosensitivity. The passivation layer180may have a planarized surface.

The passivation layer180has a plurality of pairs of first and second contact holes185aand185bexposing the wide end portions of the first and second drain electrodes175aand175b. A plurality of pixel electrodes191including a first subpixel electrode191aand a second subpixel electrode191bare formed on the passivation layer180.

A pair of the first and the second subpixel electrodes191aand191bforming one pixel electrode191are separated from each other with respect to a gap91, and the outer boundary of the pixel electrode191may be an approximately quadrangular shape. The second subpixel electrode191bincludes a central electrode piece191b1disposed beside the first subpixel electrode191a, and an upper electrode piece191b2and a lower electrode piece191b3respectively disposed on the upper and lower sides of the first subpixel electrode191ain a plane view. The upper electrode piece191b2includes an upper cutout92, and the lower electrode piece191b3includes a lower cutout93. The gap91and the oblique portions of the cutouts92and93may form an angle of about 45 degrees with the gate lines121(i−1) and121i. The pixel electrode191may be made of a transparent conductive material such as ITO or IZO, or a reflective metal such as aluminum, silver, or alloys thereof.

The first/second subpixel electrodes191a/191bare physically and electrically connected to the first/second drain electrodes175a/175bthrough the contact holes185a/185b, and receive data voltages from the first/second drain electrodes175a/175b. A pair of subpixel electrodes191aand191bare applied with different data voltages that are previously set for one input image signal, and the magnitudes thereof may be differently determined according to the size and the shape of the subpixel electrodes191aand191b. Also, areas of the first and second subpixel electrodes191aand191bmay be different. As an example, the first subpixel electrode191amay be applied with a higher voltage than the second subpixel electrode191b, and may have a smaller area than the second subpixel electrode191b.

Next, the upper panel200will be described. A light blocking member220for preventing light leakage is formed on an insulation substrate210made of transparent glass. The light blocking member220has a plurality of openings225facing the pixel electrodes191and having almost same the shape as the pixel electrodes191.

A plurality of color filters230are formed on the substrate210and the light blocking member220. The color filters230are disposed substantially in the areas enclosed by the light blocking member220, and may extend substantially along the longitudinal direction along the pixel electrodes191. The color filters230may represent one of the primary colors, such as three primary colors of red, green, and blue.

An overcoat250is formed on the color filters230and the light blocking member220. The overcoat250may be made of an (organic) insulator, and prevents the color filters230from being exposed and provides a flat surface. The overcoat250may be omitted.

A common electrode270is formed on the overcoat250. The common electrode270is preferably made of a transparent conductive material, such as ITO and IZO, and has a plurality of sets of cutouts71,72,73a,73b,74a,74b, as shown inFIG. 5. The oblique portions of the cutouts71,72,73a,73b,74a, and74bmay form and angle of about 45 degrees with the gate lines121(i−1) and121i.

The number of cutouts92,93,71,72,73a,73b,74a, and74bmay be varied depending on design factors. Alignment layers11and21are coated on the display panels100and200, and may be vertical alignment layers. Polarizers (not shown) may be provided on the outer surfaces of the display panels100and200.

The LC layer3interposed between the lower panel100and the upper panel200includes LC molecules31having negative dielectric anisotropy. The LC molecules31of the LC layer3are arranged such that a longitudinal axis of the LC molecules31may be perpendicular to the surfaces of the two panels100and200in the case that an electric field does not exist.

The first/second subpixel electrodes191a/191band the common electrode270of the upper panel200form the first/second LC capacitors Clca/Clcb along with the LC layer3therebetween such that they maintain the applied voltage after the first/second thin film transistors Qa/Qb are turned off.

If the pixel electrodes191are applied with the data voltages and the common electrode270is applied with the common voltage, an electric field that is perpendicular to two display panels100and200is generated. Thus, the LC molecules31of the LC layer3are inclined so that a long axis thereof is perpendicular to the direction of the electric field in response to the electric field, and the change degree of polarization of light incident to the LC layer3changes depending on the inclination degree of the LC molecules31. On the other hand, the cutouts92,93,71,72,73a,73b,74a, and74bof the electrodes191and270and the gap91distort the electric field to make the components perpendicular to the edges of the cutouts92,93,71,72,73a,73b,74a, and74b, and the gap91. Accordingly, the LC layer3is divided into a plurality of domains having different inclination directions of the LC molecules31, thereby widening the reference viewing angle.

Next, the arrangement and the shape of the thin film transistors Qa and Qb included in the various pixels of the LCD, according to exemplary embodiments of the present invention will be described with reference toFIG. 8toFIG. 10.FIG. 8andFIG. 9are views respectively showing a change of an alignment error of a thin film transistor according to a scanning direction of a light exposer.FIG. 10is a layout view showing four pixels PX1, PX2, PX3, and PX4and the first and second subpixels PXa and PXb of each of the pixels PX1, PX2, PX3, and PX4in a LCD, according to an exemplary embodiment of the present invention.

Referring toFIG. 10, a LCD, according to an exemplary embodiment of the present invention, includes a plurality of pixels PX1, PX2, PX3, and PX4arranged in a matrix form, a plurality of gate lines121(i−1) and121i, and a plurality of pairs of data lines171j,171(j+1),171(j+2), and171(j+3), and each of the pixels PX1, PX2, PX3, and PX4includes first and second thin film transistors Qa and Qb and a pair of the first and second subpixel electrodes191aand191bconnected to the first and second thin film transistors Qa and Qb, respectively.

The position relationships (e.g., right and left position relationships) of the first and second thin film transistors Qa and Qb of two pixels PX1, PX2, PX3, and PX4neighboring in the column direction or the row direction may be opposite to each other for the two pixels PX1, PX2, PX3, and PX4. That is, the first thin film transistor Qa of the pixel PX1is connected to the data line171(j+1) disposed on the right side thereof and the second thin film transistor Qb is connected to the data line171jdisposed on the left side thereof, but the first thin film transistor Qa of the pixel PX3/PX2neighboring in the column/row directions with respect to the pixel PX1is connected to the data line171j/171(j+2) disposed on the left side thereof and the second thin film transistor Qb is connected to the data line171(j+1)/171(j+3) disposed on the right sides. That is, the first and second thin film transistors Qa and Qb are alternately connected to one of the data line171j,171(j+1),171(j+2), and171(j+3), while two first thin film transistors Qa and two second thin film transistors Qb are alternately connected to one of the gate lines121(i−1) and121i.

In one aspect, the shape of the first thin film transistor Qa and the shape of the second thin film transistor Qb may be opposite to each other in each of the pixels PX1, PX2, PX3, and PX4. That is, in each of the pixels PX1, PX2, PX3and PX4, the relative position of the first drain electrode175awith respect to the first source electrode173aof the first thin film transistor Qa may be opposite to the relative position of the second drain electrode175bwith respect to the second source electrode173bof the second thin film transistor Qb.

For example, as shown inFIG. 10, the right and left position relationship of the first source electrode173aand the first drain electrode175a, and the right and left position relationship of the second source electrode173band the second drain electrode175bare opposite to each other with reference to the length direction of each of the pixels PX1, PX2, PX3, and PX4. The open portions of the first and second source electrodes173aand173bmay be disposed in the opposite directions to each other, and may face each other in each of the pixels PX1, PX2, PX3, and PX4.

Alternatively, the open direction of the open portions of the first source electrode173aand the second source electrode173bin each of the pixels PX1, PX2, PX3, and PX4may be the same. That is, the open portions of the first source electrode173aand the second source electrode173bin each of the pixels PX1, PX2, PX3, and PX4may be all toward the right direction or left direction. For example, the second source electrode173bof the pixel PX3shown inFIG. 10may be open toward the right direction. In this case, the second source electrode173bis farther from the data line171(j+1) than the second drain electrode175bsuch that the data line171(j+1) must be bent inside to be connected to the second source electrode173b. Thus, delay degree of data signals of two data lines171jand171(j+1) are different from each other, and deterioration of display quality due to cross-talk between the data line171(j+1) bent inside of the pixel PX3and the second subpixel electrode191bmay be generated.

However, as shown inFIG. 10, if the shapes of the first thin film transistor Qa and the second thin film transistor Qb of each of the pixels PX1, PX2, PX3, and PX4are opposite to each other, signal delay of the data lines171j,171(j+1),171(j+2), and171(j+3) may be the same, and degradation of display quality due to cross-talk may be prevented. In one aspect, it may not be necessary for the data lines171j,171(j+1),171(j+2), and171(j+3) to be bent inside the pixels PX1, PX2, PX3, and PX4, and thereby reduction of the opening ratio may be reduced.

Referring toFIG. 10, the open directions of the open portions of the first source electrode173aof the first thin film transistor Qa are opposite to each other among neighboring pixels PX1, PX2, PX3, and PX4, and the same are the open directions of the open portions of the second source electrode173bof the second thin film transistor Qb.

Differently fromFIG. 10, the right and left arrangement of the first subpixel electrodes191aand the second subpixel electrode191bmay be the same per each pixel PX1, PX2, PX3, and PX4, as shown inFIG. 4,FIG. 5andFIG. 6. In one aspect, the LCD shown inFIG. 10may have the same structure as the LCD shown inFIG. 4toFIG. 7.

In the exemplary embodiment shown inFIG. 4toFIG. 7andFIG. 10, the process for forming the conductors such as the gate lines121(i−1) and121i, the data lines171j,171(j+1),171(j+2), and171(j+3) including the source electrodes173aand173b(here,171(j+2) and171(j+3) are only shown inFIG. 10), and the drain electrodes175aand175bmay include depositing a conductive material layer on a substrate and forming a photosensitive film pattern thereon. The forming of the photosensitive film pattern includes coating a photosensitive film on the deposited conductive material layer and exposing the photosensitive film to light using a photomask. In the light exposing of the photosensitive film, the substrate may be scanned and exposed to light by a light exposer.

In a manufacturing method of the LCD, according to an exemplary embodiment of the present invention, the scanning direction of the light exposer may be parallel to the gate lines121(i−1) and121ias shown inFIG. 10. Here, in one aspect, the extension direction of the bar-shape end portion of the first and second drain electrodes175aand175bof the first and second thin film transistors Qa and Qb may also be parallel to the scanning direction of the light exposer.

On the other hand, when scanning is conducted by the light exposer, a non-linear irregular error may be generated in the scanning direction such that an alignment error of the conductors to be patterned may be generated. The error of the scanning direction may be larger in the direction perpendicular to the scanning direction than the direction parallel to the scanning direction. Accordingly, if the thin film transistors Q are arranged as shown inFIG. 8, the alignment error B in the direction perpendicular to the scanning direction of the light exposer is larger than the alignment error A in the direction parallel to the scanning direction, such that the changing amount of the overlapping area of the drain electrode175and the gate electrode124is increased. However, if the thin film transistors Q are arranged as shown inFIG. 9, the alignment error A in the direction parallel to the scanning direction of the light exposer is smaller than the alignment error B in the direction perpendicular to the scanning direction, such that the changing amount of the overlapping area of the drain electrode175and the gate electrode124is small. Here, the reference number173FIG. 8andFIG. 9indicates a source electrode enclosing the drain electrode175.

Accordingly, like the exemplary embodiments ofFIG. 4toFIG. 7andFIG. 10, the first and second drain electrodes175aand175bextend in the transverse direction which is parallel to the scanning direction of the light exposer, such that the first and second drain electrodes175aand175boverlap the right and left edges of the first and second gate electrodes124aand124b, and thereby, the changing amount of the overlapping area between the first and second drain electrodes175aand175band the first and second gate electrodes124aand124bmay be reduced even when an error is generated in the scanning direction of the light exposer. That is, the boundary line between the portion at which the first and second drain electrodes175aand175boverlap the first and second gate electrodes124aand124band the portion at which the first and second drain electrodes175aand175bdo not overlap the first and the second gate electrodes124aand124bis perpendicular to the scanning direction of the light exposer, and thereby, the changing amount of the overlapping area between the first and second drain electrodes175aand175band the first and second gate electrodes124aand124bmay be reduced although an error in the scanning direction of the light exposer is generated. Differently fromFIG. 4toFIG. 7andFIG. 10, an acute angle between the boundary line between the portion at which the first and second drain electrodes175aand175boverlap the first and second gate electrodes124aand124band the portion at which the first and second drain electrodes175aand175bdo not overlap the first and second gate electrode124aand124b, and the scanning direction of the light exposer, may be more than 45 degrees and equal to or less than 90 degrees.

In this way, if the changing amount of the overlapping area between the first and second drain electrodes175aand175band the first and the second gate electrodes124aand124bmay be reduced, the changing amount and deviation of kick-back voltages, which lower data voltages applied to the first and second subpixel electrodes191aand191bdue to parasitic capacitances between the first and second drain electrodes175aand175band the first and second gate electrodes124aand124b, may also be reduced. Accordingly, change of the kick-back voltage due to a non-linear error in the direction perpendicular to the scanning direction of the light exposer may be reduced such that display deterioration such as horizontal stripe stains may be reduced.

Next, change of the data voltages of the first and second subpixel electrodes191aand191bwhen an alignment error of the gate lines121(i−1) and121iand the data lines171j,171(j+1),171(j+2), and171(j+3) (here,171(j+2) and171(j+3) are shown inFIG. 10) or the drain electrodes175aand175bis generated under a manufacturing process in the exemplary embodiments ofFIG. 10, orFIG. 4toFIG. 7will be described with reference toFIG. 11toFIG. 14as well asFIG. 10.

FIG. 11andFIG. 13are layout views of a thin film transistor portion of two pixels in a LCD, according to an exemplary embodiment of the present invention.FIG. 12andFIG. 14show a changing amount of a kick-back voltage for two pixels of a LCD, according to an exemplary embodiment of the present invention.

Referring toFIG. 11andFIG. 12, when the gate line121iincluding the first and second gate electrodes124aand124bis biased toward the right side, the overlapping area between the first gate electrode124aand the first drain electrode175ain the pixel PX1is decreased such that the kick-back voltage is also decreased, and the overlapping area between the first gate electrode124aand the first drain electrode175ain the neighboring pixel PX2is increased such that the kick-back voltage is increased. Accordingly, the changing amounts of the data voltages applied to the first subpixel electrodes191aof the neighboring pixels PX1and PX2due to kick-back voltages may be offset. Also, when the gate line121iis biased toward the right side, the overlapping area between the second gate electrode124band the second drain electrode175bin the pixel PX1is increased such that the kick-back voltage is increased, and the overlapping area between the second gate electrode124band the second drain electrode175bin the neighboring pixel PX2is decreased such that the kick-back voltage is also decreased. Accordingly, the changing amounts of the data voltages applied to the second subpixel electrodes191bof the neighboring pixels PX1and PX2due to kick-back voltages may be offset.

InFIG. 13andFIG. 14which are opposite toFIG. 11andFIG. 12, the gate line121iincluding the first and second gate electrodes124aand124bis biased toward the left side. In the present exemplary embodiment, the changing amounts of the kick-back voltages are respectively opposite to those of the cases ofFIG. 11andFIG. 12, and the changing amounts of the data voltages applied to the first and second subpixel electrodes191aand191bof two pixels PX1and PX2neighboring in the row direction may be offset.

In this way, changes of the kick-back voltages of the first subpixel electrodes191aapplied with a relatively higher voltage is offset and changes of the kick-back voltages of the second subpixel electrodes191bapplied with a relative lower voltage is offset in the neighboring pixels PX1and PX2, such that although deviations of the alignment of constituent elements such as the gate lines121(i−1) and121iare generated under a manufacturing process, display deterioration such as horizontal stripe stains due to changes of the kick-back voltages may be reduced.

According to an exemplary embodiment of the present invention, a changing amount and deviation of kick-back voltages are reduced such that display deterioration such as horizontal stripe stains may be reduced. According to another exemplary embodiment of the present invention, changes of the kick-back voltages of the neighboring pixels are offset with each other such that although deviation of the alignment of the constituent elements are generated under a manufacturing process of the LCD, display deterioration such as horizontal stripe stains due to a change in kick-back voltages may be reduced.