Thin film transistors with a crystalline oxide semiconductor source/drain

Thin film transistors (TFTs) including a channel and source/drain that comprise an oxide semiconductor. Oxide semiconductor within the source/drain may be more ordered than the oxide semiconductor within the channel. The localized increased order of the oxide semiconductor may reduce TFT access resistance while retaining good channel gating properties. In some embodiments, order within the source or drain templates from order in adjacent contact metallization. Contact metal at the interface of the oxide semiconductor may be chosen to promote grain growth in the oxide semiconductor during deposition of the oxide semiconductor, or through solid phase epitaxy of the oxide semiconductor subsequent to deposition. Where TFT circuitry is integrated into the BEOL of a CMOS FET IC fabrication process, an EOL forming gas anneal may be employed to both passivate CMOS FETs and crystalize a source/drain of the TFTs.

CLAIM OF PRIORITY

This Application is a National Stage Entry of, and claims priority to, PCT Application No. PCT/US2016/069006, filed on Dec. 28, 2016 and titled “THIN FILM TRANSISTORS WITH A CRYSTALLINE OXIDE SEMICONDUCTOR SOURE/DRAIN”, which claims priority to PCT Application No. PCT/US2016/066416, filed on Dec. 13, 2016 and titled “PASSIVATION DIELECTRICS FOR OXIDE SEMICONDUCTOR THIN FILM TRANSISTORS”, which is incorporated by reference in its entirety for all purposes.

BACKGROUND

Thin-film transistors (TFTs) are a class of field-effect transistors (FETs) in which the channel material is a deposited thin film rather than a monocrystalline material. A common application of TFT technology is liquid crystal displays (LCD), but they are also advantageous in other applications as the thin film deposition processes employed in TFT fabrication are relatively low (e.g., below 450° C.). TFTs can be made using a wide variety of semiconductor materials, such as silicon, germanium, silicon-germanium, as well as various oxide semiconductors (a.k.a. semiconducting oxides) including metal oxides like indium gallium zinc oxide (IGZO).

DETAILED DESCRIPTION

The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one component or material with respect to other components or materials where such physical relationships are noteworthy. For example in the context of materials, one material or material over or under another may be directly in contact or may have one or more intervening materials. Moreover, one material between two materials or materials may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first material or material “on” a second material or material is in direct contact with that second material/material. Similar distinctions are to be made in the context of component assemblies.

Transistors incorporating an oxide semiconductor channel coupled to contact metallization through oxide semiconductor source and/or drain (source/drain) regions are described herein. TFT device performance depends at least in part on the extent of structural order in a thin film of oxide semiconductor. For example, the oxide semiconductor thin film can be amorphous (i.e., having no structural order), or polycrystalline (e.g., having micro-scale to nano-scale crystal grains). In accordance with some advantageous embodiments, oxide semiconductor source/drains of a transistor have greater structural order than the oxide semiconductor channel. Methods of fabricating such transistors are also described herein. In accordance with some advantageous embodiments, contact metallization is employed as an epitaxial template to impart greater order in the oxide semiconductor source/drain proximal to the contact metallization than in an oxide semiconductor channel distal from the contact metallization. In some embodiments, a thermal anneal is performed following the formation of the contact metallization and the oxide semiconductor source/drain. In some advantageous embodiments wherein contact metallization is deposited on an oxide semiconductor thin film, solid-phase epitaxy or melt recrystallization occurs during a subsequent anneal.

The inventors have found that certain contact metals possessing an appropriate grain structure at the interface of the oxide semiconductor can promote solid-phase crystallization within a volume of oxide semiconductor proximal to the interface. The inventors have further found that such crystallization can increase the conductivity of the oxide semiconductor relative to oxide semiconductor having the same material composition but less crystallinity. This characteristic may be leveraged in TFT cell architectures, for example by confining oxide semiconductor having less-ordered microstructure and good gating properties to precisely within a channel (region) of the device. Oxide semiconductor having greater order is confined to extrinsic portions of the device, which may reduce extrinsic (access) resistance.

In some advantageous embodiments, the inventors have found that when a TFT is fabricated in back-end-of-line (BEOL) logic circuitry subsequent to the fabrication of front-end-of-line (FEOL) logic circuitry employing conventional monocrystalline-channeled metal-oxide-semiconductor FETs (MOSFETs), the oxide semiconductor interfacing the TFT contact metallization to the oxide semiconductor channel may undergo controlled recrystallization during a final EOL anneal. As a “passivation anneal” is often advantageous for the FEOL FETs, improved TFT performance may be accordingly achieved in hybrid TFT-CMOS circuitry with little increase in process complexity and/or cost.

FIGS. 1A, 1B, and 1Cillustrate cross-sectional views of TFT cells having source/drain regions that are more crystalline than a gate-coupled channel region, in accordance with some embodiments. InFIG. 1A-1C, the cross-section shown is through a length of channel semiconductor and source/drain semiconductor on either side of the channel semiconductor. Referring first toFIG. 1A, TFT cell101includes a semiconductor thin film110deposited over a substrate layer105. In some exemplary embodiments, substrate layer105is amorphous. Substrate layer105may be a dielectric material, such as, but not limited to, silicon dioxide (SiO), a silicon nitride (SiN), silicon oxynitride (SiON), or low-k dielectric (e.g., having a dielectric constant below 3.5). While semiconductor thin film110may have any composition known to be suitable as a TFT channel material, such as a group IV material (e.g., Si, Ge, SiGe), in some advantageous embodiments semiconductor thin film110is an oxide semiconductor. An oxide semiconductor is a semiconducting oxide. Oxide semiconductors can be advantageous for low temperature transistor fabrication, and can have excellent transistor characteristics offering high carrier mobility and a tunable material band gap and resistivity. Many oxide semiconductors have been studied, initially in the context of discrete rectifiers, and more recently in the context of transparent TFTs for display applications. Examples include metal oxides with a transition metal (e.g., IUPAC group 4-10) or post-transition metal (e.g., IUPAC groups 11-15). In advantageous embodiments, the metal oxide includes at least one of Mg, Cu, Zn, Sn, Ti, Ni, Ga, In, Sb, Sr, Cr, Co, V, or Mo. The metal oxides may be suboxides (A2O), monoxides (AO), binary oxides (AO2), ternary oxides (ABO3), and mixtures thereof.

Oxide semiconductor thin film110may be a p-type, n-type, or intrinsic material. A number of oxide semiconductors have been found to be capable of significant electron densities. Some oxide semiconductors have also been found to be capable of significant electron hole densities. Many oxide semiconductors have high defect density nearer the valence band, but display good n-type electrical properties. Some oxide semiconductors have high defect density in the conduction band, but display good p-type electrical properties. In some embodiments, semiconductor thin film110comprises a tin oxide (SnOx), such as Tin (IV) oxide, or SnO2. In other embodiments, the tin oxide is Tin (II) oxide (SnO) or a mixture of SnO and SnO2, where x may range between 1 and 2. While the range of x may be expanded, semiconducting properties may be lost (e.g., the material becomes a pure conductor if x is to low, and a pure insulator if x is too high). In some other embodiments, semiconductor thin film110comprises a zinc oxide (ZnOx), such as Zn(II) oxide, or ZnO. In other embodiments, the zinc oxide is zinc peroxide (ZnO2) or a mixture of ZnO and ZnO2, where x may range between 1 and 2. In some other embodiments, semiconductor thin film110comprises titanium oxide (TiOx), or SnOx. Exemplary oxide semiconductors that may have suitable p-type conductivity include copper oxide (CuOx). In some CuOxembodiments, oxide semiconductor thin film110is Cu(I) oxide, or Cu2O. In other embodiments, oxide semiconductor thin film110is Cu(II) oxide (CuO) or a mixture of CuO and Cu2O, where x may range between 0.5 and 1. Other exemplary oxide semiconductor thin film110compositions include NiOx.

Oxide semiconductor conductivity type is a function of composition. Although not bound by theory, the basis for n-type conductivity in many oxide semiconductors may be the presence of oxygen vacancies. The presence of other electrically active dopants, such as hydrogen, or one or more metal species, may also serve as a means of tuning the semiconducting properties of the oxide semiconductor. Semiconductor oxide thin film110may be intentionally doped, or not. Compared to intrinsic oxide semiconductor that is not intentionally doped, n-type and p-type oxide semiconductors may have a higher concentration of impurities, such as, but not limited to, one or more group III element, group V element, and/or elemental hydrogen (H). Dopant levels in oxide semiconductor thin film110may be selected to arrive at optimal threshold voltage associated with gating the oxide semiconductor within the channel region and/or for lowest bulk and/or junction resistance within the source and/or drain region. Semiconductor thin film110may comprise ZnOxdoped with In and Ga, for example. In some specific embodiments, semiconductor thin film110is InGaO3(ZnO)5, often referred to a simply IGZO.

In the illustrative embodiment, semiconductor thin film110is compositionally homogeneous. A channel region under gate electrode140and associated with a channel length Lg, has the same oxide semiconductor composition as the source/drain regions115. As such, the TFT channel region is coupled to contact metallization160through semiconductor homojunctions. In alternative embodiments, semiconductor thin film110is compositionally heterogeneous between the channel region and at least one of the source/drain regions115. The TFT channel region is then coupled to contact metallization160through semiconductor heterojunctions. In such embodiments, source/drain regions115may both include the same oxide semiconductor having a different composition than the channel region. Alternatively, source/drain regions115may be two different oxide semiconductors, and may also have complementary conductivity types (e.g., where TFT cell101is operable as a tunnel FET).

While semiconductor oxides may display some level of structural ordering (e.g., nanocrystallinity), in some embodiments amenable to lowest processing temperatures, oxide semiconductor thin film110may be deposited in an amorphous state. In some exemplary embodiments, source/drain regions115are more ordered (i.e., more crystalline) than the channel region between source/drain regions115. For example, oxide semiconductor within the channel region may be amorphous while oxide semiconductor within the source and/or drain region is polycrystalline. The size of crystal grains within source and/or drain region may vary (e.g., from nanocrystalline or microcrystalline). However, for embodiments where the oxide semiconductor within the channel is polycrystalline, the size of the crystal grains within the source and/or drain region may be significantly (e.g., greater than 15%) larger than those in the channel region.

In some exemplary embodiments, oxide semiconductor at an interface with contact metallization160has a crystal texture associated with the contact metallization crystallinity. Hence, grains within source/drain regions115have a distribution of crystallographic orientations that is associated with crystal texture within contact metallization160. Grains within source/drain regions115are therefore non-random and have some preferred orientation that is associated with the preferred orientation of grains within contact metallization160. The association of the grain texture within source/drain regions115and contact metallization160is indicative of epitaxial templating of crystal growth within the source/drain regions115off of granular texture present in contact metallization160.

For embodiments where oxide semiconductor thin film110is disposed or located between an amorphous layer and contact metallization160, the inventors currently understand contact metallization160must be compatible with oxide semiconductor thin film110to ultimately induce crystallization in the oxide semiconductor proximal to the interface of contact metallization160. Specifically, contact metallization160is to be of a composition that when deposited to interface the chosen oxide semiconductor will, either as deposited, or upon subsequent annealing, possess crystallinity that serves as a suitable template for subsequent crystallization within the oxide semiconductor proximal to the interface of the contact metallization. As such, not all contact metallizations can be expected to be a suitable template. Where contact metallization160comprises more than one compositional layer, at least the layer of metal in contact with oxide semiconductor110is to be of a suitable composition for driving crystallization within the oxide semiconductor. In some further embodiments, contact metallization160has a relatively low affinity for oxygen to limit oxygen gettering. In some embodiments, contact metallization160includes a metal nitride at the interface of (i.e., in direct contact with) oxide semiconductor thin film110. Metal nitrides offer good stability and do not ready oxidize. Exemplary metal nitrides include TiN, TaN, and WN. Whereas Ti, Ta and W interfacial metallization layers may be unsuitable (e.g., may remain amorphous and/or may getter oxygen), the inventors have found one or more of their nitrides do provide a good template for promoting crystallization within the oxide semiconductor. In other exemplary embodiments, contact metallization160includes a noble metal (e.g., Pt) at the interface of (i.e., in direct contact with) oxide semiconductor thin film110.

In some embodiments, and as illustrated inFIG. 1A, source/drain regions115have columnar grain structure. Although not illustrated inFIG. 1A, for some such embodiments, contact metallization160also has columnar grain structure. TiN, for example can be deposited onto an oxide semiconductor, such as IGZO, in a manner that results in a columnar grain structure, either as deposited, or upon subsequent thermal processing. In some embodiments, columnar grains within contact metallization160have their longitudinal axes preferentially oriented perpendicular to the interface of source/drain region115and contact metallization160. In some such embodiments, columnar grains within source/drain region115likewise have their longitudinal axis preferentially oriented perpendicular to the interface of source/drain region115and contact metallization160.

When grain growth within the source/drain regions is templated at the interface with contact metallization, the extent of crystallinity within an oxide semiconductor is a function of the anneal conditions (e.g., time and temperature) as well as the texture of the contact metallization. Columnar grains preferentially oriented perpendicular to the interface of source/drain region115may advantageously favor grain growth through a thickness of the oxide semiconductor thin film relative to lateral grain growth beyond edges of the contact metallization. In some advantageous embodiments, grain growth extends through a thickness of the oxide semiconductor that is at least equal to the depth of the channel region. In some embodiments, grain growth extends through the entire thickness of the oxide semiconductor thin film. For example, in TFT cell101(FIG. 1A) columnar grains are present throughout the entire (z) thickness of oxide semiconductor thin film110. In some such embodiments, oxide semiconductor thin film110within source/drain regions115has a thickness of 5-20 nm. In some further embodiments, crystallinity of source/drain regions115extends laterally (e.g., x-dimension) beyond an edge of contact metallization160. The amount of this lateral grain growth will reduce the effective gate length Lgof the channel region, and so it is ideally well controlled. In some embodiments, crystallinity of source/drain regions115extends laterally by an amount that is less than the thickness (e.g., z-dimension) of the crystalline source/drain regions. In some further embodiments, crystallinity of source/drain regions115extends laterally by an amount less than the lateral width of an overlying dielectric spacer130separating contact metallization160from gate electrode140. In some embodiments, crystallinity of source/drain regions115extends laterally by 2-10 nm from an edge of the contact metallization toward the channel region.

In some embodiments, a TFT with ordered source/drain oxide semiconductor includes a less-ordered channel region that is operable to be gated by a gate electrode separated from the channel region by a gate dielectric. In TFT cell101for example, a high-k gate dielectric120is between gate electrode140and the channel region of oxide semiconductor thin film110. Depending on the conductivity type of the oxide semiconductor, the gate stack is to modulate the oxide semiconductor between intrinsic and n-type or p-type material through the field effect. To do so, gate dielectric120is to form an interface of suitable quality. In some exemplary embodiments, gate dielectric120comprises a high-k dielectric having a bulk relative dielectric constant greater than at least 9. The gate dielectric may include one or more material layers. In some such embodiments, the high-k gate dielectric includes at least one Al2O3, HfO2, or HfAlOxin direct contact with the oxide semiconductor. Silicates such as HfSiOx or TaSiOx may also be suitable for either direct contact with the oxide semiconductor or with an underlying interfacial layer of the gate dielectric. HfO2may give better gate control for zinc oxide (e.g., IGZO) embodiments than do alternatives such as Al2O3. However, both Al2O3, HfO2have been found to display results superior to a conventional silicon-based gate dielectrics (e.g., SiO2). One or more material providing a suitable work function may be employed for gate electrode140. In some advantageous embodiments, gate electrode140includes a metal with a work function below 5 eV. The metal gate electrode may include an elemental metal layer, a metal alloy layer, or laminate structure of either or both. In some embodiments the gate electrode is a metal nitride, such as TiN (e.g., 4.0-4.7 eV). The gate electrode may also comprise Al (e.g., TiAlN). Other alloy constituents may also be employed, such as, but not limited to C, Ta, W, Pt, and Zn. Gate electrode140may have any lateral critical dimension (CDG). In some exemplary underlap embodiments, CDG is less than the effective gate length LginFIG. 1A. In some exemplary overlap embodiments, CDG is greater than the effective gate length Lg. In some embodiments where oxide semiconductor thin film110is of a homogenous composition (i.e., channel and source/drain regions have the same composition), the difference between CDG and Lgis a function of lateral crystallization of source/drain regions115.

Dielectric spacer130may be of any composition known to have properties suitable as an insulator separating gate electrode140from contact metallization160. Dielectric spacer130may be SiO, SiN, SiON, or any known low-k material (e.g., SiOC, etc.). Dielectric spacer130may have any lateral dimensions. In some exemplary embodiments, dielectric spacer130has a lateral width (e.g., x-dimension) of 5-20 nm. Although not depicted in FIG.1A, the terminals of TFT cell101may be interconnected with one or more other TFTs, or other FETs, by one or more interconnect metallization levels to form a functional integrated circuit.

TFTs with ordered source/drain regions in accordance with embodiments herein may have a wide range of architectures. For example, a TFT with ordered source/drain regions may include a bottom-side gate, rather than (or in addition to) the top-side gate electrode illustrated inFIG. 1A. A TFT cell102with a bottom-side gate in accordance with some embodiments is further illustrated inFIG. 1B. As shown, gate electrode140is embedded in a dielectric substrate layer105. Gate dielectric120is further disposed over substrate layer105. Oxide semiconductor thin film110is over (e.g., in direct contact with) gate dielectric120. Substrate layer105, gate electrode140, gate dielectric120, and oxide semiconductor thin film110may be any of those materials described above in the context ofFIG. 1A. Gate dielectric120may be amorphous, in which case the ordering of source/drain regions115illustrated inFIG. 1Btemplates from ordering in the overlying contact metallization160. Contact metallization160may have any of the compositions described above in the context ofFIG. 1A, for example. Where there is not also a top-side gate electrode, an ILD170may be between separate features of contact metallization160.

As another example, a TFT with ordered source/drain regions may include bottom-side contact metallization, rather than (or in addition to) the top-side contact metallization that was illustrated inFIGS. 1A and 1B. A TFT cell103with a bottom-side contact metallization in accordance with some embodiments is further illustrated inFIG. 1C. As shown, contact metallization160is embedded in substrate layer105. Oxide semiconductor thin film110is over (e.g., in direct contact with) contact metallization160. Gate dielectric120is further over oxide semiconductor thin film110. Gate electrode140is over (e.g., in direct contact with) gate dielectric120. Where there is no top-side contact metallization, a dielectric ILD170is over source/drain regions115(e.g., in direct contact with gate dielectric120). Substrate layer105, gate electrode140, gate dielectric120, oxide semiconductor thin film110, and contact metallization160may be any of those materials described above in the context ofFIG. 1A. Gate dielectric120may again be amorphous, in which case the ordering of source/drain regions115illustrated inFIG. 1Ctemplates from crystallinity in the underlying contact metallization160. Such ordering may occur during the deposition of oxide semiconductor thin film110(i.e., the oxide semiconductor is epitaxially deposited/grown), and/or solid phase crystallization may occur within source/drain regions115during a thermal treatment subsequent to the deposition of oxide semiconductor thin film110.

FIGS. 2A and 2Bare cross-sectional views of substrates upon which a TFT cell including an ordered source/drain, such as the TFT cells illustratedFIG. 1A-1C, may be fabricated. In some embodiments, a TFT cell including an ordered source/drain is fabricated over one or more interconnect metallization levels integrating a plurality of silicon CMOS FETs. In the example shown inFIG. 2A, substrate201includes a plurality of CMOS FETs206that employ a substantially monocrystalline channel material, such as, but not limited to, silicon. CMOS FETs206may be finFETs, for example. CMOS FETs206are interconnected with one or more levels of interconnect metallization207. Over any given interconnect metallization level (e.g., metal 4), a TFT may be fabricated over substrate layer105as part of a BEOL fabrication process. The interconnect metallization may, at least in part, serve as the gate electrode and/or contact metallization of the overlying TFT cell.

In some embodiments, a TFT cell including an ordered source/drain is fabricated on a back-side of a plurality of silicon CMOS FETs. In the example shown inFIG. 2B, substrate202includes a plurality of CMOS FETs206that employ a substantially monocrystalline channel material, such as, but not limited to, silicon. In the context of substrate202, CMOS FETs206may again be finFETs, for example. CMOS FETs206are interconnected with one or more levels of interconnect metallization207over a front-side of CMOS FETs206. On a side of CMOS FETs206opposite interconnect metallization207, a TFT cell may be fabricated over substrate layer105as part of a transistor substrate back-side fabrication process.

The TFTs described above may be fabricated on a substrate in a variety of manners.FIG. 3is a flow diagram illustrating exemplary methods301for fabricating a TFT cell, in accordance with some embodiments. Methods301may be employed to fabricated TFT cell101(FIG. 1A), for example.FIGS. 4A, 4B, 4C, and 4Dillustrate cross-sectional views through a length of channel semiconductor and source/drain semiconductor of a TFT that evolves as operations in methods301are practiced, in accordance with some specific embodiments.

Referring first toFIG. 3, methods301begin at operation305where a substrate is received. The substrate may have any architecture suitable for fabrication of a TFT cell, such as, but not limited to, substrate201or202introduced above, a display substrate, or similar. An oxide semiconductor thin film is then deposited over a substrate layer at operation310. Any deposition process known to be suitable for a desired oxide semiconductor composition may be performed at operation310, such as, but not limited to pulsed laser deposition (PLD), oxidation processing where a precursor is spin-coated and oxidized during an anneal, chemical vapor deposition (CVD), and atomic layer deposition (ALD). In the example further illustrated inFIG. 4A, an amorphous oxide semiconductor thin film110(e.g., comprising IGZO) is deposited on a substrate layer105that includes an amorphous dielectric layer.

Returning toFIG. 3, methods301continue at operation320where a gate stack is formed over a channel region of the oxide semiconductor thin film. The gate stack may be formed by any technique known to be suitable for a TFT. In exemplary embodiments further illustrated inFIG. 4B, gate dielectric120, comprising any of the materials introduced above, is deposited over (e.g., in direct contact with) a channel region of oxide semiconductor thin film110. In some embodiments, an ALD process is employed to deposit a high-k gate dielectric film directly on a surface of oxide semiconductor thin film110. A gate electrode140, comprising any of the materials introduced above, is deposited over (e.g., in direct contact with) gate dielectric120. In some embodiments, gate electrode140is deposited by CVD, ALD, physical vapor deposition (PVD), or any other technique known to be suitable for forming the desired material. The gate stack is then patterned, for example by masking and etching at least the gate electrode material layer. A dielectric film may then be deposited and recess etched with any suitable anisotropic etch process to form dielectric spacer130along a sidewall of gate electrode140. Any gate dielectric120unmasked by the gate stack or gate sidewall spacer may then be removed with any process (e.g., wet or dry etch) known to be suitable for the gate dielectric composition.

Returning toFIG. 3, methods301continue at operation330where contact metallization is formed over source/drain regions of the oxide semiconductor thin film. Any deposition process known to be suitable for depositing a particular contact metallization composition may be performed at operation330. In some embodiments, the deposition process induces order in the contact metallization. In the exemplary embodiment shown inFIG. 4E, contact metallization160is deposited in direct contact with portions of oxide semiconductor thin film110not protected by gate electrode140and dielectric spacer130. Contact metallization160may have any of the compositions described above. Contact metallization160may be deposited by a technique that favors the formation of grains at an interface with oxide semiconductor thin film110. Contact metallization160may be deposited by a technique that favors columnar growth of grains formed at the interface of oxide semiconductor thin film110. In some embodiments, PVD or ALD is employed to deposit a metal nitride (e.g., TiN) directly on oxide semiconductor thin film110.

Returning toFIG. 3, methods301continue at operation340where a thermal anneal is performed to crystallize a region of the oxide semiconductor thin film proximal to the contact metallization. One or more capping dielectric layers and/or interconnect metallization levels may be deposited over the TFT before the anneal is performed. Where the substrate includes CMOS circuitry, the TFT cells may also be interconnected with the CMOS circuitry prior to the thermal anneal. Thermal anneal operation340entails exposing the TFT circuitry (and CMOS circuitry) to an elevated temperature. The elevated temperature may be higher than any prior processing the TFT(s) were exposed to. The elevated temperature is advantageously 300° C., or more, and may be as high as 500° C., depending on tolerance of the substrate (including CMOS circuitry, if present) and the TFT circuitry to such thermal processing. The anneal operation340may be of short duration (e.g., on the order of seconds) in some rapid thermal processing embodiments. In alternative embodiments, the anneal operation340may be of longer duration (e.g., minutes to hours). Anneal duration for a given annealing process may be selected to control the extend of crystallization. For example, the anneal duration may be selected to ensure source/drain crystallinity does not extend through the channel region, potentially shorting the source and drain, or otherwise detrimentally impacting channel gate control.

In some embodiments, anneal operation340is performed in a non-oxidizing environment. In a specific embodiment where the TFTs are fabricated in the BEOL of a CMOS FET fabrication process, the anneal operation340comprises a post-passivation EOL, or “final” anneal performed in a forming gas (H2:N2) environment at 400° C., or less. Such forming gas anneals are often performed in a CMOS FET fabrication process as a way of passivating interfacial bonds. When performed after the fabrication of a TFT having an oxide semiconductor interface with a contact metal suitable for templating crystallization, an oxide semiconductor region proximal to the interface can crystallize with texture attributable to the contact metal, for example as described above. Electrical test (ET) performed before and after the anneal has also shown TFT performance improvements consistent with reduced source/drain resistance. Following the anneal, transmission electron microscropy (TEM) has revealed crystallinity in the source/drain regions, for example in the form of columnar grains illustrated inFIG. 4Dfor the TFT cell101, and substantially as described above in the context ofFIG. 1A. With the thermal anneal being of mutual benefit to both CMOS FET-based circuitry and TFT-based circuitry, the overhead associated increasing the order of the TFT source/drain regions is minimal and superior TFT performance may be had at little additional fabrication complexity or expense.

FIG. 5illustrates a mobile computing platform and a data server machine employing an SoC including TFTs with an crystallized oxide semiconductor having more order than the oxide semiconductor channel, for example as described elsewhere herein. The server machine506may be any commercial server, for example including any number of high-performance computing platforms within a rack and networked together for electronic data processing, which in the exemplary embodiment includes a packaged monolithic SoC550. The mobile computing platform505may be any portable device configured for each of electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform505may be any of a tablet, a smart phone, laptop computer, etc., and may include a display screen (e.g., a capacitive, inductive, resistive, or optical touchscreen), a chip-level or package-level integrated system510, and a battery515.

Either within the integrated system510illustrated in the expanded view520, or as a stand-alone packaged chip within the server machine506, monolithic SoC550includes a memory block (e.g., RAM), a processor block (e.g., a microprocessor, a multi-core microprocessor, graphics processor, or the like) including at least one TFT with a crystallized oxide semiconductor source/drain, for example as described elsewhere herein. The monolithic SoC550may be further coupled to a board, a substrate, or an interposer560along with, one or more of a power management integrated circuit (PMIC)530, RF (wireless) integrated circuit (RFIC)525including a wideband RF (wireless) transmitter and/or receiver (TX/RX) (e.g., including a digital baseband and an analog front end module further comprises a power amplifier on a transmit path and a low noise amplifier on a receive path), and a controller535.

Functionally, PMIC530may perform battery power regulation, DC-to-DC conversion, etc., and so has an input coupled to battery515and with an output providing a current supply to other functional modules. As further illustrated, in the exemplary embodiment, RFIC525has an output coupled to an antenna (not shown) to implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 4G+, and beyond. In alternative implementations, each of these board-level modules may be integrated onto separate ICs or integrated into monolithic SoC550.

FIG. 6is a functional block diagram of an electronic computing device, in accordance with some embodiments. Computing device600may be found inside platform505or server machine506, for example. Device600further includes a motherboard602hosting a number of components, such as, but not limited to, a processor604(e.g., an applications processor), which may further incorporate at least one TFT with a crystallized oxide semiconductor source/drain, for example as described elsewhere herein. Processor604may be physically and/or electrically coupled to motherboard602. In some examples, processor604includes an integrated circuit die packaged within the processor604. In general, the term “processor” or “microprocessor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be further stored in registers and/or memory.

In various examples, one or more communication chips606may also be physically and/or electrically coupled to the motherboard602. In further implementations, communication chips606may be part of processor604. Depending on its applications, computing device600may include other components that may or may not be physically and electrically coupled to motherboard602. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage device (such as hard disk drive, solid-state drive (SSD), compact disk (CD), digital versatile disk (DVD), and so forth), or the like.

Communication chips606may enable wireless communications for the transfer of data to and from the computing device600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. Communication chips606may implement any of a number of wireless standards or protocols, including but not limited to those described elsewhere herein. As discussed, computing device600may include a plurality of communication chips606. For example, a first communication chip may be dedicated to shorter-range wireless communications, such as Wi-Fi and Bluetooth, and a second communication chip may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

While certain features set forth herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Hence, various modifications of the implementations described herein, as well as other implementations, which are apparent to persons skilled in the art to which the present disclosure pertains are deemed to lie within the spirit and scope of the present disclosure. It will be recognized that principles of the disclosure are not limited to the embodiments so described, but can be practiced with modification and alteration without departing from the scope of the appended claims. For example the above embodiments may include specific combinations of features as further provided below.

In one or more first examples, a thin film transistor (TFT) structure comprises a channel comprising a semiconductor material including oxygen, a gate electrode coupled to the channel, and contact metallization coupled to the channel through a source or drain, the source or drain comprising a material and having greater crystallinity than that of the channel.

In one or more second examples, for any of the first examples the contact metallization has crystallinity, and the source or drain at an interface with the contact metallization has a crystal texture associated with the contact metallization crystallinity.

In one or more third examples, for any of the first and second examples the contact metallization has a columnar grain structure and the source or drain has a columnar grain structure.

In one or more fourth examples, for any of the first, second, or third examples a longitudinal axis of the columnar grain structure in the contact metallization and the source or drain is preferentially perpendicular to the interface of the source or drain and the contact metallization.

In one or more fifth examples, for any of the first, second, third, or fourth examples the contact metallization at the interface is a metal nitride and the source or drain comprises oxygen.

In one or more sixth examples, for any of the first, second, third, fourth or fifth examples, the metal nitride is selected from the group consisting of TiN, TaN, and WN.

In one or more seventh examples, for any of the first, second, third, fourth, fifth or sixth examples the source or drain has a thickness of 5-20 nm, the gate electrode has a lateral dimension of 10-50 nm, the contact metallization is laterally separated from the gate electrode by 3-7 nm. The greater crystallinity extends through the entire thickness of the source or drain, and the greater crystallinity extends laterally a distance beyond an edge of the contact metallization toward the channel.

In one or more eighth examples, for any of the first, second, third, fourth, fifth, sixth, or seventh examples the channel comprises a layer of semiconductor material between a gate stack and an amorphous dielectric underlayer or overlayer, the gate stack including the gate electrode and a high-k gate dielectric. The source or drain comprises a layer of semiconductor material between the contact metallization and the amorphous dielectric underlayer or overlayer.

In one or more ninth examples, for any of the first, second, third, fourth, fifth, sixth, seventh, or eighth examples the source or drain comprises a material including all the constituents in the channel.

In one or more tenth examples, for any of the first, second, third, fourth, fifth, sixth, seventh, eighth, or ninth examples the source or drain material further comprises an impurity at a concentration greater than in the channel.

In one or more eleventh examples, for any of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth or tenth examples least the channel comprises a metal oxide including at least one of Cu, Zn, Sn, Ti, Ni, Ga, In, Sb, Sr, Cr, Co, V, or Mo.

In one or more twelfth examples, for any of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth or eleventh examples at least the channel comprises a material selected from the group consisting of tin oxide, zinc oxide, and titanium oxide.

In one or more thirteenth examples, for any of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth, eleventh, or twelfth examples both the channel and source or drain comprise IGZO.

In one or more fourteenth examples, an integrated circuit (IC), comprises a plurality of n-type fin field effect transistor (finFET) structures and p-type finFET structures, one or more metallization levels interconnecting the n-type and p-type finFET structures into CMOS circuitry, and a plurality of thin film transistor (TFT) structures disposed over the metallization levels, or disposed on a side of a substrate opposite the finFET structures, and interconnected with the CMOS circuitry. Individuals of the TFT structures further comprise a channel comprising a semiconductor material including oxygen, a gate electrode over the channel, and contact metallization coupled to the channel through a source or drain, the source or drain comprising a material and having greater crystallinity than that of the channel.

In one or more fifteenth examples, for any of the fourteenth examples the oxide semiconductor within the channel and source or drain is selected from the group consisting of tin oxide, zinc oxide, and titanium oxide. The contact metallization at an interface with the semiconductor is a metal nitride selected from the group consisting of TiN, TaN, and WN. The gate electrode has a lateral dimension of 10-50 nm and is separated from the semiconductor channel by a high-k gate dielectric. The contact metallization has a columnar grain structure and the source or drain has a columnar grain structure. The source or drain has a thickness of 5-20 nm. The contact metallization is laterally separated from the gate electrode by 3-7 nm. Crystallinity within the source or drain extends through the entire thickness of the source or drain, and extends laterally a distance beyond an edge of the contact metallization toward the channel.

In one or more sixteenth examples, a method of fabricating a thin film transistor (TFT) structure comprises depositing a layer of semiconductor material comprising oxygen, forming gate stack over a first region of the semiconductor material. The method comprises forming contact metallization over a second region of the semiconductor, wherein the contact metallization includes a template layer in direct contact with the semiconductor material. The method comprises performing a thermal anneal that increases the crystallinity of the semiconductor material in the second region beyond that of the first region.

In one or more seventeenth examples, for any of the fifteenth or sixteenth examples the thermal anneal comprises exposing the TFT structure to a temperature of 300-400° C.

In one or more eighteenth examples, for any of the fifteenth, sixteenth, or seventeenth examples depositing the layer of semiconductor material further comprises depositing an amorphous layer of tin oxide, zinc oxide, and titanium oxide over an amorphous dielectric layer. Forming the contact metallization further comprises depositing metal nitride onto the semiconductor material.

In one or more nineteenth examples, for any of the fifteenth through eighteenth examples forming CMOS circuitry prior to depositing the semiconductor thin film, wherein forming the CMOS circuitry further comprises forming a plurality of n-type fin field effect transistor (finFET) structures and p-type finFET structures. The method comprises forming one or more metallization levels interconnecting the n-type and p-type finFET structures into the CMOS circuitry. The TFT structure is one of a plurality of TFT structures formed over the metallization levels, or disposed on a side of a substrate opposite the finFET structures, and interconnected with the CMOS circuitry.

In one or more twentieth examples, for any of the fifteenth through nineteenth examples the anneal comprises a forming gas anneal performed subsequent to the interconnection of the TFTs to the CMOS circuitry.

However, the above embodiments are not limited in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the invention should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.