Boot test apparatus and method of computer system

A boot test apparatus and method can repeatedly execute actions of power-on and power-off for a cold boot test of a computer to test whether the computer is operable. The boot test apparatus includes a microprocessor, a controller, and a power switch. The microprocessor generates a control signal according to a period voltage provided by an internal power supply. The control signal includes a pulse signal and a voltage signal. The controller controls a power switch to send the pulse signal to the computer through a power button of the computer, and controls the power switch to send the voltage signal to the computer through a power input port of the computer. The microprocessor further obtains test information from the computer when the computer executes a cold boot process according to the control signal, and displays the test information on an LED when the cold boot process is abnormal.

BACKGROUND

1. Technical Field

Embodiments of the present disclosure relate generally to computer system test methods and systems, and more particularly to a boot test apparatus and method of a computer system.

2. Description of Related Art

For manufacturers of computer systems, quality of computers delivered from the factory needs to be under strict control. In order to assure the stability and reliability of computer systems, it is necessary to perform a series of tests before shipping. Among these tests, one of them is a cold boot test operation, whose method is to repeatedly execute actions of power on and power off once in a certain time interval, testing whether the computer boots properly. For example, if a computer is able to start the operating system when the computer is powered on, then it is considered as a normal boot. Likewise, if the computer is able to exit the operating system when the computer is powered off, then it is consider as a normal power-off.

However, the aforesaid approach of computer cold boot test is normally performed by professional testers. During the test, when the computer is not able to boot normally, the current error conditions are not properly displayed or recorded before the next reboot test. As a result, the above-mentioned problems need to be addressed.

DETAILED DESCRIPTION

FIG. 1is a block diagram of one embodiment of a boot test apparatus1of a computer2. In the embodiment, the boot test apparatus1can repeatedly execute actions of power-on and power-off for a cold boot test of the computer2to test whether the computer2is operable. The cold boot test may include a boot process test and a power-off process test. The boot process test is to test whether the computer2can normally start an operating system when the computer2is powered on. The power-off process test is to test whether the computer2can normally exit the operating system when the computer2is powered off.

In one embodiment, the boot test apparatus1includes an internal power supply10, a microprocessor11, a controller12, a power switch13, and a light-emitting diode (LED)14. The boot test apparatus1connects to an external power supply3and the computer2to be tested through the power switch13. The external power supply3is configured to provide working powers for the computer2during the process of the cold boot test of the computer2. In some embodiment, the computer may be a personal computer, a notebook computer, a server, a workstation computer, or any other electronic device. The computer2may include a power button21, a power input port22, and a data output port23. The power switch13connects to the computer2through the power button21and the power input port22. The microprocessor11connects to the computer2through the data output port23.

The internal power supply10connects to microprocessor11, and is configured to provide a period voltage for the microprocessor11. The period voltage may be 5 volts defined as a high level voltage, or 0 volts defined as a low level voltage. The microprocessor11connects to the controller12, and is configured to generate a control signal according to the period voltage, and sends to the control signal to the controller12. In the embodiment, the control signal may be a pulse signal and a voltage signal. The pulse signal is sent to the power button21for controlling the power button21to power on or power off the computer2. The voltage signal sent to the power input port22for controlling the external power supply3to power on or power off the computer2.

In one example with respect toFIG. 2A, during the test period of the cold boot test, the computer2may perform a booting process and a power-off process when the power button21receives the pulse signal from the power switch13. In another example with respect toFIG. 2B, the computer2may also perform the booting process and the power-off process when the power input port22receives the voltage signal from the power switch13.

The controller12is configured to control the power switch13to send the pulse signal to the power button21, and control the power switch13to send the voltage signal to the power input port22. In the embodiment, the controller12enables the power switch13to power-on the computer2based on the pulse signal, or disenables the power switch13to power-off the computer2based on the voltage signal.

The computer2performs the cold boot test according to the control signal from the power switch13, and generates test information of the cold boot process correspondingly. In the embodiment, the computer2boots the operating system when the power button21receives the pulse signal form the power switch13, and exits the operating system when the power button21receives the voltage signal form the power switch13. During the execution of the cold boot process, the computer2generates test information of the cold boot process correspondingly. The test information may be include normal information and abnormal information when the Basic Input/Output System (BIOS) of the computer2executes the Power On Self Test (POST). It is understood that the normal information are generated when the computer2is workable, and abnormal information are generated when the computer2is unworkable.

The microprocessor11is configured to obtain the test information from the computer2through the data output port23during the cold boot process, and determines the cold boot process of the computer2is normal according to the test information. When the cold boot process of the computer2is abnormal, the microprocessor11displays the abnormal information on the LED14for indicating the computer2experienced an error. The data output port23may be a RS-232 interface or a USB interface for transferring the test information from the computer2to the microprocessor11.

FIG. 3is a flowchart of one embodiment of a boot test method of a computer system using the apparatus1ofFIG. 1. In the embodiment, the method can repeatedly execute actions of a power-on and power-off for a cold boot test of the computer2to test whether the computer2is operable. As mentioned above, the cold boot test may include the boot process test and the power-off process test for the computer2.

In block S31, the microprocessor11presets a number of test times for testing the cold boot process of the computer2, and initialize a counter (denoted as “T”) as zero. In one embodiment, the number of test times can be preset as 100 times, for example.

In block S32, the microprocessor11generates a control signal according to a period voltage provided by the internal power supply10, and sends to the control signal to the controller12. As mentioned above, the control signal may be a pulse signal and a voltage signal. The pulse signal is sent to the power button21to power-on or power-off the computer2. The voltage signal sent to the power input port22to control the external power supply3to power-on or power-off the computer2.

In block S33, the controller12controls the power switch13to send the pulse signal to the power button21, and controls the power switch13to send the voltage signal to the power input port22. In the embodiment, the controller12enables the power switch13to power-on the computer2based on the pulse signal, or disenables the power switch13to power-off the computer2based on the voltage signal.

In block S34, the computer2performs the cold boot test according to the control signal from the power switch13, and generates test information of the cold boot process. In the embodiment, the computer2boots the operating system when the power button21receives the pulse signal form the power switch13, and exits the operating system when the power button21receives the voltage signal form the power switch13. During the execution of the cold boot process, the computer2generates test information of the cold boot process correspondingly. The test information may be include normal information and abnormal information when the Basic Input/Output System (BIOS) of the computer2executes the Power On Self Test (POST). The normal information is generated when the computer2is workable, and the abnormal information is generated when the computer2nonfunctional.

In block S35, the microprocessor11obtains the test information from the computer2through the data output port23during the cold boot process. In block S36, the microprocessor11determines the cold boot process of the computer2is normal according to the test information. If the cold boot process of the computer2is abnormal, block S37is implemented. Otherwise, if the cold boot process of the computer2is normal, block S38is implemented.

In block S37, the microprocessor11displays the abnormal information on the LED14to indicate the computer2is nonfunctional when the cold boot process is abnormal. In block S38, the microprocessor11adds one to the counter, i.e., performs a calculation of T=T+1, once the computer2completes the cold boot process for the current test normally. In block S39, the microprocessor11checks whether the counter T is greater than the number of test times (e.g., 100 times preset by the microprocessor11). If the counter is not greater than the test time, block S32is repeated. Otherwise, if the counter is greater than the test time, the microprocessor11stops to generate the control signal and ends the cold boot test flow.