Semiconductor memory and semiconductor device with nitride memory elements

A semiconductor memory has a gate electrode and a pair of multilayer memory elements formed on side surfaces of the gate electrode. Each multilayer memory element includes, in sequence from the gate electrode outward, a first silicon oxide layer, a charge trapping silicon nitride layer, a second silicon oxide layer, all with L-shaped cross sections, and a protective silicon nitride layer with an approximately rectangular cross section seated in the L-shape of the second silicon oxide layer. The protective silicon nitride layer protects the charge trapping silicon nitride layer from etching damage during the formation of contact holes without adding to the area occupied by the memory cell.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory or semiconductor device having nonvolatile memory cells with multilayer memory elements formed on both side surfaces of a transistor gate electrode.

2. Description of the Related Art

Memory cells with this structure are advantageous because they can store two bits of information per cell. Many semiconductor memories employing this structure use an oxide-nitride-oxide (ONO) multilayer memory element in which a silicon nitride charge trapping layer is sandwiched between silicon oxide insulating layers. Japanese Patent Application Publication No. 2004-56095 discloses a memory of this type, in which the gate electrode is flanked on both sides by L-shaped first silicon oxide insulating layers, the silicon nitride trapping layers are seated in these insulating layers, and second silicon oxide insulating layers cover both the trapping layers and the edges of the first insulating layers. Japanese Patent Application Publication No. 2004-343015 discloses a generally similar memory in which the silicon nitride trapping layers are also L-shaped, and the second silicon oxide insulating layers are seated in the trapping layers. These memories are programmed by hot electron injection from the channel beneath the gate into the trapping layer, the electrons passing through the first insulating layer.

In these memories, the transistor gates and their multilayer memory elements are covered by an interlayer dielectric film of silicon oxide. Contact holes are formed in the interlayer dielectric film by an anisotropic etching process to provide electrical access to the source and drain areas of the substrate on both sides of the gate. A problem is that if the contact holes are misaligned, the anisotropic etching process may etch through part of the multilayer memory elements, reducing or eliminating the region in which hot electron injection takes place, thus making it difficult or impossible to program the memory cells.

To avoid this reliability problem, it is necessary to allow a margin of space between the contact holes and the multilayer memory elements, but that is undesirable because it makes the memories larger and more expensive.

As an alternative structure, Japanese Patent Application Publication No. 2004-343015 also discloses a memory in which the multilayer memory element has an inverted U-shape that covers the top and sides of the gate electrode. The U-shaped memory element is covered by a further outer layer of silicon nitride seventy to two hundred nanometers thick. The anisotropic etching process that forms the contact holes is highly selective, etching silicon nitride much more slowly than silicon oxide, so even if the contact holes are misaligned, the etching process does not penetrate through the thick outer silicon nitride layer and the memory elements remain undamaged.

Although this structure eliminates the need for an alignment margin, it has other disadvantages, one being that the thick outer silicon nitride layer covering the multilayer memory element, which is itself comparatively thick, limits the possible reduction in memory cell size.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a small and reliable two-bit memory cell, a semiconductor memory including such memory cells, and a semiconductor device including such a semiconductor memory.

The invented semiconductor memory has a semiconductor substrate covered by a silicon oxide interlayer dielectric film. Each memory cell has a gate electrode, a gate insulation film interposed between the gate electrode and the surface of the semiconductor substrate, a pair of highly doped diffusion regions formed in the surface of the semiconductor substrate on opposite sides of the gate electrode, and a pair of multilayer memory elements formed on the side surfaces of the gate electrode.

Each multilayer memory element comprises a first silicon oxide layer extending from substantially the top to the bottom of one side surface of the gate electrode and then outward onto one of the highly doped diffusion regions, a charge trapping nitride layer formed on the first silicon oxide layer, a second silicon oxide layer formed on the charge trapping nitride layer, and a protective silicon nitride layer formed on the second silicon oxide layer.

In this structure, the first and second silicon oxide layers and the charge trapping nitride layer may have L-shaped cross sections while the protective silicon nitride layer has a substantially rectangular cross section and with two sides resting on the second silicon oxide layer. In this configuration, when contact holes are formed in the interlayer dielectric film to provide electrical access to the highly-doped regions of the substrate, the protective silicon nitride layer protects the other parts of the multilayer memory element from etching damage without increasing the area occupied by the memory cell.

DETAILED DESCRIPTION OF THE INVENTION

Semiconductor devices including memory cells embodying the present invention will now be described with reference to the attached drawings, in which like elements are indicated by like reference characters.

First Embodiment

Referring toFIG. 1, the semiconductor device1in the first embodiment includes a plurality of memory cells formed on a semiconductor substrate2, which is a monocrystalline silicon (Si) substrate doped at a comparatively low concentration with a p-type impurity. Each memory cell is generally similar in structure to a metal-oxide-semiconductor field-effect transistor (MOSFET).

As the sources and drains of the MOSFET structure, a plurality of highly-doped regions3are formed in a surface layer of the semiconductor substrate2. The highly-doped regions3are doped at a comparatively high concentration with an n-type impurity.

As the gates of the MOSFET structure, a plurality of gate electrodes4are formed on the semiconductor substrate2between the highly-doped regions3. The gate electrodes4are formed from polysilicon and are separated from the semiconductor substrate2by a gate insulation film5of silicon oxide (SiO2). Each gate electrode4is centered between a mutually adjacent pair of highly-doped regions3.

The part of the surface layer of the semiconductor substrate2between the highly-doped regions3and the gate electrodes4is occupied by lightly doped regions6doped at a comparatively low concentration with an n-type impurity. The edges of the lightly doped regions6extend beneath the gate electrodes4. Lightly doped regions6of this type are generally referred to as lightly doped drains (LDD), regardless of whether they are disposed on the source side or the drain side of the gate.

A first silicon oxide layer8is disposed on each side surface4aof the gate electrode4in each memory cell. The first silicon oxide layer8has an L shape, extending from substantially the top to the bottom of the side surface4aand then extending outward from the side surface4ato the adjacent highly-doped region3. The first silicon oxide layers8are comparatively thin, with thicknesses in the range from three to twenty nanometers (3 to 20 nm).

A charge trapping nitride layer9(indicated by hatching) having a similar L shape is disposed on the first silicon oxide layer8. The charge trapping nitride layer9is made of silicon nitride (SiN) and is also comparatively thin, with a thickness in the range of 2 to 15 nm. The function of the charge trapping nitride layer9is to store data by trapping injected electrons.

A second silicon oxide layer10also having an L shape and a thickness in the range of 3 to 20 nm is disposed on the charge trapping nitride layer9. The second silicon oxide layer10functions as an electron barrier, preventing the electrons trapped in the charge trapping nitride layer9from migrating elsewhere.

A protective silicon nitride layer11having a substantially rectangular shape is seated in the ‘L’ of the second silicon oxide layer10. The protective silicon nitride layer11is comparatively thick, its thickness being in the range from 10 to 200 nm. The function of the protective silicon nitride layer11is to protect the charge trapping nitride layer9during an anisotropic contact hole etching process, described later. The protective silicon nitride layer11is not perfectly rectangular because one of its upper corners becomes rounded during another anisotropic etching process that exposes the top surfaces of the gate electrodes, so that two of its sides approximate an arc of a circle, ellipse, or parabola.

The silicon oxide and nitride layers8,9,10,11forming multilayer memory elements12a,12bhaving an oxide-nitride-oxide-nitride (ONON) structure. Both nitride layers9,11comprise silicon nitride (SiN); both oxide layers8,10comprise silicon dioxide (SiO2). When the memory is programmed, hot electrons injected from the channel in the semiconductor substrate2below the gate electrode4are trapped in the charge trapping nitride layer9, or at the interfaces between the charge trapping nitride layer9and one or both of the first and second silicon oxide layers8,10. In particular, the electrons are trapped in the lower part of the charge trapping nitride layer9, so that their electric field alters the resistance of the lightly doped region6. It is this property that enables the data represented by the trapped electrons to be read. The trapped electrons remain trapped even when the memory is powered off, making the memory nonvolatile.

The multilayer memory elements12a,12b, gate electrodes4, and semiconductor substrate2are covered by an interlayer dielectric film14of silicon oxide, in which contact holes are formed to provide electrical access to the highly-doped regions3. The contact hole15shown inFIG. 1occupies the space between a pair of mutually adjacent multilayer memory elements12aand12b. The contact hole15is filled with a conductive material such as tungsten (W) that forms a contact plug16electrically connecting the highly-doped region3below to a wiring pattern (not shown) above.

Next a series of processes (P1-P6) for fabricating the structure inFIG. 1will be described.

The procedure begins with an isolation process (P1) such as local oxidation of silicon (LOCOS) or shallow trench isolation (STI) that divides the surface layer of the semiconductor substrate2into active regions separated by isolation regions. The memory cells inFIG. 1and other circuit elements (not shown) will be formed in the active regions. The isolation regions are, for example, thick silicon oxide regions that electrically isolate the active regions. InFIG. 1the isolation regions (not shown) extend parallel to the surface of the drawing sheet in front of and behind the memory cells.

The next process (P2) forms a thin film of silicon oxide on the surface of the active regions of the semiconductor substrate2by, for example, thermal oxidation, deposits a layer of polysilicon on the silicon oxide film by chemical vapor deposition (CVD), coats the polysilicon layer with a resist layer, and patterns the resist layer by photolithography to form a mask defining the shapes of the gate electrodes4. The material not covered by the mask is then etched down to the surface of the semiconductor substrate2by dry etching, for example, leaving the gate electrodes4and gate insulation film5.

The next process (P3) removes the mask and implants ions of an n-type impurity at a comparatively low concentration into the surface layer of the semiconductor substrate2between the gate electrodes4, forming the lightly doped regions6. At this point each lightly doped region6extends from one gate electrode4to an adjacent gate electrode4. Next, a first silicon oxide layer, a first silicon nitride layer, a second silicon oxide layer, and a second silicon nitride layer are formed one atop another in succession on the surface and sides of the gate electrodes4and elsewhere by CVD. These layers are then etched anisotropically until the tops of the gate electrodes4are exposed. Parts of the layers are left attached to the sides of the gate electrodes4, forming the ONON structure of the multilayer memory elements12a,12b, in which the first silicon nitride layer becomes the charge trapping nitride layer9. Between the multilayer memory elements12aand12b, the etching process proceeds down to and exposes the surface of the semiconductor substrate2.

The layers constituting the multilayer memory elements12a,12bneed not all be formed by CVD. The first silicon oxide layer may be formed by thermal oxidation. If the first silicon nitride layer is deposited with a little extra thickness, the second silicon oxide layer may also be formed by thermal oxidation.

In the next process (P4), ions of an n-type impurity are implanted at a comparatively high concentration into the surface of the semiconductor substrate2that is exposed between the multilayer memory elements12a,12bon the side surfaces4aof the gate electrodes4, forming the highly-doped regions3. The highly-doped regions3are self-aligned by the multilayer memory elements12a,12b. The implantation process includes an annealing step that spreads the edges of the highly-doped regions3so that they extend partly under the multilayer memory elements12a,12b. Similarly, the edges of the lightly doped regions6extend partly under the gate electrodes4.

In the next process (P5), a thick silicon oxide layer is deposited on the entire surface of the semiconductor substrate2, including the multilayer memory elements12a,12band gate electrodes4, by CVD, and the surface of this silicon oxide layer is planarized to form the interlayer dielectric film14.FIG. 2shows the memory cells at the completion of this process.

In the next process (P6), the interlayer dielectric film14is coated with a resist layer (not shown), which is patterned by photolithography to form openings nominally centered between the gate electrodes4, and the interlayer dielectric film14is anisotropically etched through these openings to create the contact holes15. Etching conditions with a high SiO2/SiN selectivity ratio are used, so that even if the holes in the resist mask are not perfectly aligned and part of the protective silicon nitride layer11is etched, it is etched much more slowly than the silicon-oxide interlayer dielectric film14. The etching process is stopped when it reaches the highly-doped regions3in the semiconductor substrate2; then the resist mask is removed and the contact holes15are filled with a conductive material deposited by CVD, for example, to form the contact plugs16, completing the structure shown inFIG. 1.

In a further process (not shown) a wiring pattern is formed on the interlayer dielectric film14, making electrical contact with the contact plugs16, and further interlayer dielectric films, wiring layers, etc. are formed as necessary.

The data retention characteristics of memory cells fabricated as described above were evaluated under accelerated life testing conditions at an ambient temperature of 250° C. The results are indicated by points marked with triangles inFIG. 3. The vertical axis represents change in current flow between the source and drain (ΔIds) of a memory cell over time in microamperes; the horizontal axis indicates elapsed time in hours. For comparison,FIG. 3also shows results of similar tests of memory cells having a conventional ONO structure of the general type shown in FIG. 18 in Japanese Patent Application Publication No. 2004-343015; these memory cells were formed by increasing the thickness of the second silicon oxide layer10and omitting the protective silicon nitride layer11in the process (P3) described above; the test results are indicated by points marked with diamonds. For further comparison, memory cells having an ON structure were fabricated by increasing the thickness of the charge trapping nitride layer9and omitting both the second silicon oxide layer10and protective silicon nitride layer11in the above process, and these cells were also tested, giving the results indicated by squares inFIG. 3.

AsFIG. 3shows, the novel ONON structure performs just as well as the conventional ONO structure, despite the presence of the protective silicon nitride layer11near the charge trapping nitride layer9. The ON structure performs less well, allowing approximately twice as much source-drain current to flow, indicating that electrons excited by thermal energy were migrating from the lower part toward the upper part of the charge trapping nitride layer.

The substantially identical performance of the novel ONON structure and the conventional ONO structure shows that even a thin second silicon oxide layer10can suppress the unwanted migration of electrons. That is, even a thin second silicon oxide layer10can act as an electron barrier to prevent the escape of stored charge under conditions of high ambient temperature, or high internal temperature caused by the operation of other circuit elements in the device. The invented semiconductor memory can therefore be used under the same conditions as a conventional memory with an ONO structure.

The results inFIG. 3also indicate that the thinness of the charge trapping nitride layer9is a factor in preventing unwanted electron migration.

FIG. 4shows an example of the memory cells in the first embodiment in which the contact hole15is imperfectly aligned, being shifted to the left in the drawing. As a result, the process (P6) that etches the contact holes also etches part of the protective silicon nitride layer11in multilayer memory element12a. Because of the high SiO2/SiN selectivity of the etching process, however, the contact hole etching process is completed before it reaches the charge trapping nitride layer9. In particular, the lowermost part of the charge trapping nitride layer9, into which electrons are injected from the channel, remains intact, so the programming and erasing performance of the memory cell is unimpaired.

The protection provided by the protective silicon nitride layer11provides an increased alignment tolerance for the contact holes15. It also means that when the spacing between gate electrodes4is determined, it is only necessary to provide enough space to assure adequate electrical contact between the contact plugs16and the highly-doped regions3, allowing for alignment error and variation in the cross-sectional shapes of the contact plugs16; it is not necessary to allow further space to prevent etching damage to the charge trapping nitride layers9. Moreover, the silicon nitride layers11that protect the charge trapping nitride layers9from etching damage do not add to the area occupied by the memory cell, since they are seated within the L-shape of the charge trapping nitride layer9and the silicon oxide layers8,10. Consequently, a high-density memory can be fabricated with high reliability.

A semiconductor device including the memory cells of the first embodiment will normally also include peripheral circuits or logic circuits including MOSFETs. In the first embodiment, these MOSFETs have substantially the same structure as in the memory cells.

FIG. 5shows a pair of n-channel MOSFETs21in the peripheral or logic circuits of the semiconductor device. The highly-doped regions3and lightly doped regions6are again doped with an n-type impurity. Depending on the circuit layout, the length of the highly-doped regions3may be increased, as shown, but otherwise, the structure is the same as inFIG. 1, including the same semiconductor substrate2, gate electrodes4, gate insulation films5, interlayer dielectric film14, contact holes15, and contact plugs16. The sidewalls22a,22bon the side surfaces4aof the gate electrodes4are identical to the multilayer memory elements12a,12binFIG. 1, but the first silicon nitride layer functions as a silicon nitride insulating film9ainstead of a charge trapping nitride layer. The reason is that the device is not operated in such a way as to inject significant numbers of hot electrons into the silicon nitride insulating film9a. The first silicon oxide layer8, silicon nitride insulating film9a, second silicon oxide layer10, and protective silicon nitride layer11are, accordingly, all insulating layers, and the sidewalls22a,22bfunction to align the highly-doped regions3but not to store data.

The MOSFETs21inFIG. 5operate in the conventional way, current flow through the channel23being controlled by the voltage applied the gate electrode4. The lightly doped regions6function as LDD regions.

P-channel MOSFETs in the peripheral or logic circuits have a similar structure, except that they are formed in n-wells in the semiconductor substrate2and the highly-doped regions3and lightly doped regions6are doped with a p-type impurity.

The identical MOSFET structure used both in the memory cells and in peripheral or logic circuits simplifies the fabrication of the semiconductor device in the first embodiment. In particular, n-channel MOSFETs can be formed by exactly the same processes (P1-P6).

Second Embodiment

The second embodiment differs from the first embodiment in that the memory cells have self-aligned contact holes. Referring toFIG. 6, the second embodiment is a semiconductor device1with memory cells having the same semiconductor substrate2, highly-doped regions3, gate insulation films5, lightly doped regions6, and interlayer dielectric film14as in the first embodiment and the same ONON structure comprising a first silicon oxide layer8, a charge trapping nitride layer9, a second silicon oxide layer10, and a protective silicon nitride layer11, but differing in respect to the gate electrodes and contact holes and plugs.

The gate structure in the second embodiment includes a polysilicon gate electrode4overlain by a silicide film31, which is a thin film of an alloy of silicon and a metal (such as tungsten) having a comparatively high-melting point. The silicide film31reduces the electrical resistance of the gate. The silicide film31is covered by a nitride hard mask film32of silicon nitride with a thickness in the range from 50 to 300 nm, which protects the gate during self-aligned etching of the contact holes. Further protection is provided by a nitride stopper film33, which covers the top and sides of the gate structure, including the multilayer memory elements12a,12bformed on the side surface4aof the gates, and also covers the surface of the semiconductor substrate2, except at the contact holes. The thickness of the nitride stopper film33is in the range from 10 to 40 nm.

The contact holes35in the memory cells are nominally centered between adjacent gates, as in the first embodiment, but they are larger, and cut into the nitride hard mask film32in the gates on one or both sides. They then become more narrow, approximately following the curved shape of the nitride stopper film33, and finally descend along with the nitride stopper film33to the surface of the highly-doped regions3in the semiconductor substrate2. The contact holes35are filled with contact plugs36that electrically connect the highly-doped regions3to wiring (not shown) formed above the interlayer dielectric film14, as in the first embodiment.

Next a procedure for fabricating the memory cells in the second embodiment will be described. The procedure begins with the first process (P1) described in the first embodiment.

In the next process (PA2), the gate insulation film5and a layer of polysilicon are formed as in the first embodiment, then a comparatively thin layer of silicide and a thicker layer of silicon nitride are deposited by CVD. These layers are patterned by photolithography and etching as described in the first embodiment to form the gate electrode4, gate insulation film5, silicide film31, and nitride hard mask film32constituting the gates.

In the next process (PA3), the etching mask used in process PA2is removed, the lightly doped regions6are formed by ion implantation, and the multilayer memory elements12a,12bcomprising the first silicon oxide layer8, charge trapping nitride layer9, second silicon oxide layer10, and protective silicon nitride layer11are formed substantially as described in the first embodiment, except that in the upper regions of the gates, the first silicon oxide layer8is deposited on the sides of the silicide film31and nitride hard mask film32.

In the next process (PA4), the highly-doped regions3are formed by ion implantation as described in the first embodiment; then a layer of silicon nitride is deposited by CVD on all exposed surfaces, including the top of the nitride hard mask film32and the multilayer memory elements12a,12b, to form the nitride stopper film33.

In the next process (PA5), the interlayer dielectric film14is formed substantially as in the first embodiment, except that it is formed on the nitride stopper film33.FIG. 7shows the device at the conclusion of this process.

In the next process (PA6), the interlayer dielectric film14is coated with a resist layer, which is then patterned by photolithography to form openings nominally centered between the gate electrodes4, but wide enough to extend (if accurately centered) over part of the nitride hard mask film32in each gate. The interlayer dielectric film14is then anisotropically etched through these openings as in the first embodiment, using etching conditions with a high SiO2/SiN selectivity ratio. The etching time is controlled by detecting the nitride hard mask film32and stopping the etch a predetermined time after the nitride hard mask film32is exposed. The predetermined time is calculated from the known height of the nitride hard mask film32above the surface of the semiconductor substrate2and the known SiO2etching rate so that the etch stops at the surface of the nitride stopper film33in the areas between the multilayer memory elements12a,12b. For each contact hole, this etching process removes not only SiO2from the interlayer dielectric film14, but also part of the nitride hard mask film32from the adjacent gates, and some of the top part of each adjacent multilayer memory element12a,12b.FIG. 8shows the device at the end of this stage, using dotted lines to indicate the removed part18of the nitride hard mask film32and multilayer memory elements12a,12b.

The next process (PA7) is another anisotropic etching process that uses the same resist mask as in the preceding process (PA6) but has different etching conditions, chosen to etch SiN more rapidly than SiO2. This etch removes the thin layer of SiN forming the nitride stopper film33at the bottom of each contact hole, exposing the surface of the highly-doped region3. The etching time is controlled according to the SiN etching rate and the known thickness of the nitride stopper film33. Similar thicknesses of material are also removed from the nitride hard mask film32and multilayer memory elements12a,12b, enlarging the removed parts18so that they assume the size indicated inFIG. 6. Next the resist mask is removed and the contact holes35are filled with a conductive material deposited by sputtering, for example, to form the contact plugs36.

A wiring pattern (not shown) is then formed on the interlayer dielectric film14, making electrical contact with the contact plugs36, and further interlayer dielectric films, wiring layers, etc. are formed as necessary to complete the semiconductor device1.

While the memory cells are being formed, other MOSFETs may be formed by the same processes in peripheral or logic circuits in the same device, as explained in the first embodiment.

Although the nitride hard mask film32is partly removed by the anisotropic etching in the contact hole formation processes (PA6, PA7), the nitride hard mask film32and nitride stopper film33are thick enough to assure that these etching processes do not expose any part of the silicide film31and gate electrode4in the gate structure or create any short circuits between these gate layers and the contact plugs36.

As in the first embodiment, the protective silicon nitride layer11protects the lower parts of the charge trapping nitride layer9. In addition, the thinness (3-20 nm) of the first and second silicon dioxide layers8,10creates an etch-stopping effect that assures that they are not etched deeply even though the top ends of these layers are exposed during the SiO2etching process (PA6). The thinness (2-15 nm) of the charge trapping nitride layer9creates a similar etch-stopping effect that assures that the charge trapping nitride layer9is not etched deeply even though its top end is exposed during the SiN etching process (PA7). Programming, erasing, and data storage performance of the memory cells therefore remain unimpaired.

An advantage of the second embodiment is that even considerable misalignment of the contact holes35can be tolerated without diminishing the area of contact between the contact plugs36and the highly-doped regions3. This makes it possible to reduce the spacing between memory cells and the cost of the fabrication process, resulting in increased memory capacity and a smaller, denser, and less expensive semiconductor device.

Another advantage of the second embodiment is that the nitride stopper film33prevents the isolation regions formed in the initial process (P1) from being etched during the SiO2etching process (PA6). Since the isolation regions are silicon oxide regions, they also remain substantially unetched during the SiN etching process (PA7). Contact plugs can therefore be used to interconnect circuit elements in different active regions.

The invention is not limited to the preceding embodiments. For example, the semiconductor substrates2inFIGS. 1 and 6may be doped with an n-type impurity and the highly-doped regions3and lightly doped regions6may be doped with a p-type impurity.

The ONON structure of the multilayer memory elements in the preceding embodiments may also be altered, to an ONONON structure, for example. Any number of silicon oxide and silicon nitride layers may be formed on the charge trapping nitride layer9, provided that the uppermost layer is a silicon nitride layer.

The data stored in the memory cells may be read by detecting changes in the threshold voltages of the memory cells, instead of detecting changes in the resistance of the lightly doped regions6.

Those skilled in the art will recognize that further variations are possible within the scope of the invention, which is defined in the appended claims.