Internal reference voltage generating circuit for reducing standby current and semiconductor memory device including the same

An internal reference voltage generating circuit that reduces a standby current and the number of pins of a semiconductor memory device, in which a reference voltage is provided to an input buffer that receives a signal through an input to which an on die transmitor resistor is connected, includes: a voltage dividing circuit outputting the reference voltage by a power voltage; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input and a voltage level of an end of the voltage dividing circuit, and controlling the on resistor value of the pull down driver according to a result of the comparison. The internal reference voltage generating circuit is operated while the memory controller inputs a signal into a mode register set (MRS) to enable the internal reference voltage generating circuit and the output signal of the MRS is activated.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application claims priority from Korean Patent Application No. 10-2005-0135870, filed on Dec. 30, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

BACKGROUND OF THE INVENTION

1. Technical Field

The present disclosure relates to a reference voltage generating circuit and, more particularly, to an internal reference voltage generating circuit for an input buffer of a high-speed semiconductor memory device, and a semiconductor memory device including the same.

2. Discussion of the Related Art

Owing to the development of mobile systems, the demand for semiconductor memory devices operated on a high-speed low voltage has increased. Conventional semiconductor memory devices operated on such a high-speed low voltage stably receive input signals having a small swing width using input buffers based on a predetermined reference voltage.

The reference voltage of the input buffers, however, is generated outside the conventional semiconductor memory devices and is then supplied to the conventional semiconductor memory devices.

FIG. 1is a block diagram showing an external reference voltage generating circuit15and a semiconductor memory device100that receives a reference voltage from the external reference voltage generating circuit15. Referring toFIG. 1, the external reference voltage generating circuit15is formed on a printed circuit board (PCB) outside the semiconductor memory device100and generates the reference voltage VREF. The external reference voltage generating circuit15applies the reference voltage VREF to the semiconductor memory device100through a reference voltage input pin REFIN. Input buffers11and13then receive the reference voltage VREF.

The external reference voltage generating circuit15includes resistors R1and R2serially connected to a power voltage VCC and a ground voltage VSS, and generates the reference voltage VREF at a connection point of the resistors R1and R2. The external reference voltage generating circuit15provides the reference voltage VREF to the semiconductor memory device100and to a memory controller (not shown) that controls the semiconductor memory device100.

The semiconductor memory device100requires the reference voltage input pin REFIN since the reference voltage VREF is generated from outside the semiconductor memory device100. Also, a standby current flows from the power voltage VCC to the ground voltage VSS in the external reference voltage generating circuit15, thereby causing an increase in power consumption of the semiconductor memory device100.

SUMMARY OF THE INVENTION

Exemplary embodiments of the present invention provide an internal reference voltage generating circuit that reduces a standby current and reduces the number of pins of a semiconductor memory device.

Exemplary embodiments of the present invention provide a semiconductor memory device including an internal reference voltage generating circuit that reduces a standby current and reduces the number of pins of the semiconductor memory device.

According to an exemplary embodiment of the present invention, there is provided an internal reference voltage generating circuit of a semiconductor memory device providing a reference voltage to an input buffer that receives a signal through an input to which an on die termination (ODT) resistor is connected, the circuit comprising: a voltage dividing circuit outputting the reference voltage by distributing voltages; and

a pull down driver connected to the voltage dividing circuit wherein the pull down driver is turned on or off according to a command applied from outside the semiconductor memory device.

The voltage dividing circuit may comprise: a plurality of resistors serially connected between a power voltage and the pull down driver, wherein the reference voltage is output from one of contact points of the plurality of resistors, and the total sum of values of the plurality of resistors is the same as a value of the ODT resistor.

The command is a write command by which the pull down driver is turned on.

The pull down driver has the same on resistor value as an on resistor value of a pull down driver of an output driver of the memory controller that transmits data to the input of the semiconductor memory device.

According to an exemplary embodiment of the present invention, there is provided an internal reference voltage generating circuit of a semiconductor memory device providing a reference voltage to an input buffer that receives a signal through an input to which an ODT resistor is connected, the circuit comprising: a voltage dividing circuit outputting the reference voltage by distributing voltages; a pull down driver connected to the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input with a voltage level of an end of the voltage dividing circuit, and controlling the on resistor value of the pull down driver according to a result of the comparison.

The voltage dividing circuit comprises: a plurality of resistors serially connected between a power voltage and the pull down driver, wherein the reference voltage is output from one of contact points of the plurality of resistors, and the total sum of values of the plurality of resistors is the same as a value of the ODT resistor.

The pull down driver comprises: a plurality of pull down transistors in parallel connected between an end of the voltage dividing circuit and a ground voltage, and is turned on or off in response to control code signals, respectively.

The calibration control circuit controls the pull down driver to have the same on resistor value as an on resistor value of a pull down driver of an output driver of a memory controller that transmits data to the semiconductor memory device.

According to an exemplary embodiment of the present invention, there is provided a semiconductor memory device comprising: an input end; an ODT resistor connected to the input end; an input buffer that receives a signal through the input end based on a reference voltage; and an internal reference voltage generating circuit that generates the reference voltage, wherein the internal reference voltage generating circuit comprises: a voltage dividing circuit outputting the reference voltage by distributing voltages; a pull down driver connected to an end of the voltage dividing circuit, wherein the pull down driver is turned on or off according to a command applied from outside.

The voltage dividing circuit comprises: a plurality of resistors serially connected between a power voltage and the pull down driver, wherein the reference voltage is output from one of contact points of the plurality of resistors, and the total sum of values of the plurality of resistors is the same as a value of the ODT resistor.

The command is a write command by which the pull down driver is turned on.

The pull down driver has the same on resistor value as an on resistor value of a pull down driver of an output driver of a memory controller that transmits data to the input end.

According to an exemplary embodiment of the present invention, there is provided a semiconductor memory device comprising: an input end; an ODT resistor connected to the input end; an input buffer that receives a signal through the input end based on a reference voltage; and an internal reference voltage generating circuit that generates the reference voltage, wherein the internal reference voltage generating circuit comprises: a voltage dividing circuit outputting the reference voltage by distributing voltages; a pull down driver connected to an end of the voltage dividing circuit; and a calibration control circuit comparing a voltage level of the input end and a voltage level of an end of the voltage dividing circuit, and controlling the on resistor value of the pull down driver according to a result of the comparison.

The voltage dividing circuit comprises: a plurality of resistors serially connected between a power voltage and the pull down driver, wherein the reference voltage is output from one of contact points of the plurality of resistors, and the total sum of values of the plurality of resistors is the same as a value of the ODT resistor.

According to an exemplary embodiment of the present invention, the pull down driver comprises: a plurality of pull down transistors in parallel connected between an end of the voltage dividing circuit and a ground voltage, and respectively turned on or off in response to control code signals.

The calibration control circuit comprises: a voltage comparator a voltage level of the input end and a voltage level of an end of the voltage dividing circuit; and a control code generating circuit generating the control code signals in response to an output of the voltage comparator.

The calibration control circuit controls the pull down driver to have the same on resistor value as an on resistor value of a pull down driver of an output driver of a memory controller that transmits data to the semiconductor memory device.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference the accompanying drawings. Like reference numerals are used to designate like or equivalent elements throughout this disclosure.

FIG. 2is a block diagram of a semiconductor memory device200including an internal reference voltage generating circuit23according to an exemplary embodiment of the present invention. For the sake of descriptive convenience, a memory controller210that controls the semiconductor memory device200is illustrated.

Referring toFIG. 2, the semiconductor memory device200includes an input end DQ, an on die termination (ODT) resistor RT connected to the input end DQ, and an input buffer21that receives a signal input from the input end DQ based on a reference voltage VREF, wherein the internal reference voltage generating circuit23that generates the reference voltage VREF.

The input buffer21is a data input buffer that receives a data signal. When the semiconductor memory device200is a synchronous DRAM, the input buffer21can be the data input buffer or a data strobe input buffer that receives a data strobe signal.

The internal reference voltage generating circuit23includes a voltage dividing circuit231that outputs the reference voltage VREF by distributing voltages, and a pull down driver233that is connected to an end of the voltage dividing circuit231. The pull down driver233is turned on or off according to an externally applied command. More specifically, if a write command (not shown) is applied from the outside, a command decoder25decodes the write command and controls the pull down driver233to be turned on. If a command other than the write command is applied from the outside, the command decoder25controls the pull down driver233to be turned off.

The voltage dividing circuit231includes a plurality of resistors that are serially connected between a power voltage VCC and the pull down driver233, and outputs the reference voltage VREF from one of the connection points of the plurality of resistors. The total sum of values of the plurality of resistors is the same as a value of the ODT RT.

In this exemplary embodiment, the voltage dividing circuit231includes first and second resistors R3and R4. A value of the first resistor R3is the same as a half of the value of the ODT RT (RT/2). A value of the second resistor R4is also the same as a half of the value of the ODT RT (RT/2). Therefore, the total sum of the values of the first and second resistors R3and R4is the same (RT) as the value of the ODT RT. The voltage dividing circuit231outputs the reference voltage VREF from a connection point of the first and second resistors R3and R4.

The pull down driver233has the same on resistor value as an on resistor value of a pull down driver273of an output driver27of the memory controller210that transmits data to the input DQ of the semiconductor memory device200over a transmission line ZO. The output driver27of the memory controller210includes a pull up driver271and the pull down driver273.

For example, if the value of the ODT RT is 60 ohms, and the on resistor value of the pull down driver273of the output driver27of the memory controller210is 60 ohms, the values of the first and second resistors R3and R4are each 30 ohms, and the on resistor value of the pull down driver233is 60 ohms. If the write command is applied from outside, the command decoder25turns on the pull down driver233. In this exemplary embodiment, if the power voltage VCC is 10 volts, the reference voltage VREF is 1.35 volts.

When the memory controller210writes logic low data to the semiconductor memory device200, since the pull down driver273of the output driver27of the memory controller210is turned on, the logic low data over the transmission line ZO is 0.9 volts. When the memory controller210writes logic high data to the semiconductor memory device200, since the pull up driver271of the output driver27of the memory controller210is turned on, the logic high data over the transmission line ZO is 1.8 volts.

Therefore, the reference voltage VREF is half (1.35) of the voltage (0.9) of the logic low data and the voltage (1.8) of the logic high data.

The internal reference voltage generating circuit23of the exemplary embodiment of the present invention is operated when the write command is applied from outside the semiconductor memory device200, thereby reducing a standby current. Also, the internal reference voltage generating circuit23of the current embodiment of the present invention is included in the semiconductor memory device200, thereby reducing the number of pins required on the semiconductor memory device200.

FIG. 3is a block diagram of a semiconductor memory device300including an internal reference voltage generating circuit33according to an exemplary embodiment of the present invention. For the sake of descriptive convenience, a memory controller310that controls the semiconductor memory device300is illustrated.

Referring toFIG. 3, the semiconductor memory device300includes an input DQ, an ODT resistor RT connected to the input DQ, an input buffer31that receives a signal input from the input end DQ based on a reference voltage VREF, the internal reference voltage generating circuit33that generates the reference voltage VREF, and a mode register set (MRS)35that enables or disables the internal reference voltage generating circuit33.

The input buffer31is a data input buffer that receives a data signal. When the semiconductor memory device300is a synchronous DRAM, the input buffer31can be the data input buffer or a data strobe input buffer that receives a data strobe signal.

The internal reference voltage generating circuit33includes a voltage dividing circuit331that outputs the reference voltage VREF by distributing voltages, a pull down driver333that is connected to an end of the voltage dividing circuit331, and a calibration control circuit335that compares a voltage level V_DQ of the input DQ and a voltage level VFRE_CAL of an end of the voltage dividing circuit331, and controls an on resistor value of the pull down driver333according to a result of the comparison.

An output signal EN of the MRS35controls the calibration control circuit335. If the memory controller310inputs a signal (not shown) to the MRS35to enable the internal reference voltage generating circuit33, the output signal EN of the MRS35is activated, and accordingly the calibration control circuit335is enabled so that the internal reference voltage generating circuit33is operated.

The constitution of the operation of the internal reference voltage generating circuit33will now be described in detail with reference toFIG. 4.

FIG. 4is a block diagram of the internal reference voltage generating circuit33illustrated inFIG. 3. Referring toFIG. 4, the voltage dividing circuit331includes a plurality of resistors that are serially connected between a power voltage VCC and the pull down driver333, and outputs the reference voltage VREF from one of the connection points of the plurality of resistors. The sum of the values of the plurality of resistors is the same as the value of the ODT RT inFIG. 3.

The voltage dividing circuit331includes first and second resistors R5and R6. A value of the first resistor R5is the same as a half of the value of the ODT RT (RT/2). A value of the second resistor R6is the same as the half of the value of the ODT RT (RT/2). Therefore, the sum of the values of the first and second resistors R5and R6is the same (RT) as the value of the ODT RT. The voltage dividing circuit331outputs the reference voltage VREF from a contact point of the first and second resistors R5and R6.

The pull down driver333is connected in parallel to an end of the voltage dividing circuit331and the ground voltage VSS, and includes a plurality of pull down transistors N0through N2that are turned on or off in response to control code signals DS0through DS2, respectively. If occasion demands, the pull down driver333further includes a pull down transistor N3that is always turned on. The pull down transistors N0through N3are NMOS transistors.

The calibration control circuit335controls the pull down driver333to have the same on resistor value as that of the pull down driver373of the output driver37of the memory controller310illustrated inFIG. 3. The output driver37of the memory controller310includes the pull up driver371and the pull down driver373.

The calibration control circuit335includes a voltage comparator51and a control code generating circuit53. The voltage comparator51compares a voltage level V_DQ of the input end DQ and a voltage level VREF_CAL of an end of the voltage dividing circuit331. The control code generating circuit53generates the plurality of control code signals DS0through DS2in response to outputs of the voltage comparator51and latches the control code signals DS0through DS2.

The operation of the internal reference voltage generating circuit33will now be described. If the memory controller310inputs a signal to the MRS35to enable the internal reference voltage generating circuit33, the output signal EN of the MRS35is activated, and accordingly the calibration control circuit335is enabled so that the internal reference voltage generating circuit33is operated.

When the pull down driver373of the memory controller310is turned on, the voltage comparator51compares the voltage level V_DQ of the input end DQ and the voltage level VREF_CAL of the end of the voltage dividing circuit331. It is assumed that the voltage level V_DQ of the input end DQ is virtually identical to a voltage level of an output end DOUT of the memory controller310.

As a result of the comparison, if the voltage level VREF_CAL of the end of the voltage dividing circuit331is lower than the voltage level V_DQ of the input end DQ, the control code generating circuit53generates the control code signals DS0through DS2to increase the on resistor value of the pull down driver333, that is, to reduce the number of the turned-on pull down transistors DS0through DS2. If the on resistor value of the pull down driver333is increased, that is, if the number of the turned-on pull down transistors DS0through DS2is reduced, the voltage level VREF_CAL of the end of the voltage dividing circuit331is increased.

If the voltage level VREF_CAL of the end of the voltage dividing circuit331is higher than the voltage level V_DQ of the input end DQ, the control code generating circuit53generates the control code signals DS0through DS2to reduce the on resistor value of the pull down driver333, that is, to increase the number of the turned-on pull down transistors DS0through DS2. If the on resistor value of the pull down driver333is reduced, that is, if the number of the turned-on pull down transistors DS0through DS2is increased, the voltage level VREF_CAL of the end of the voltage dividing circuit331is reduced.

The operation is repeated until the voltage level VREF_CAL of the end of the voltage dividing circuit331is identical to the voltage level V_DQ of the input end DQ. This means that the on resistor value of the pull down driver333is the same as the on resistor value of the pull down driver373of the output driver37of the memory controller310.

For example, if the value of the ODT RT is 60 ohms, the values of the first and second resistors R5and R6are 30 ohms. If the power voltage VCC is 1.8 volts and the voltage level V_DQ of the input end DQ is 0.9 volts, the voltage level VREF_CAL of the end of the voltage dividing circuit331is 0.9 volts and, thus, the reference voltage VREF is 1.35 volts.

Therefore, the reference voltage VREF is half (1.35) of the sum of the voltage (0.9) of the logic low data and the voltage (1.8) of the logic high data.

The internal reference voltage generating circuit33of the exemplary embodiment of the present invention is operated while the memory controller37inputs the signal (not shown) into the MRS35to enable the internal reference voltage generating circuit33and the output signal EN of the MRS35is activated. Also, the internal reference voltage generating circuit33of the exemplary embodiment of the present invention is included in the semiconductor memory device300, thereby reducing the number of pins required for the semiconductor memory device300.

According to exemplary embodiments of the present invention, an internal reference voltage generating circuit can reduce a standby current and the number of pins of a semiconductor memory device.