DLL circuit with delay equal to one clock cycle

A DLL circuit includes a phase comparator configured to compare timing between a first clock signal and a second clock signal, a delay circuit configured to delay the first clock signal for output as the second clock signal by a delay length responsive to a result of comparison by the phase comparator, and a control circuit configured to suspend supply of the first clock signal to the phase comparator temporarily while the second clock signal is supplied to the phase comparator.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2004-123380 filed on Apr. 19, 2004, with the Japanese Patent Office, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention generally relates to DLL circuits, and particularly relates to a DLL circuit which generates a clock signal having a predetermined delay relative to a clock signal input from an exterior.

2. Description of the Related Art

A DLL (Delay Locked Loop) circuit serves to control the delay time of a delay element by a feedback loop, such that a delay clock signal derived by delaying an input clock signal by the delay element and the input clock signal have a predetermined delay time difference with each other.

FIG. 1is a block diagram showing an example of the construction of a related-art DLL circuit.

A DLL circuit10ofFIG. 1includes a phase comparator101, a charge pump102, a loop filter103, a voltage-controlled delay element (VCDL)104, and a voltage-controlled delay element (VCDL)105. A clock signal CLK input from an exterior is supplied to the voltage-controlled delay element104. The voltage-controlled delay element104receives the output of the loop filter103as an input control voltage, and delays the clock signal CLK by a delay length responsive to the control voltage. As for the construction of the voltage-controlled delay element104, provision may be made to reduce a delay length in response to a drop in the input control voltage, or may be made to reduce a delay length in response to a rise in the input control voltage. For the sake of convenience of explanation, the construction assumed here is such that the delay length is reduced in response to a drop in the input control voltage.

The delay clock signal that is output from the voltage-controlled delay element104is supplied to one input of the phase comparator101. The other input of the phase comparator101receives the clock signal CLK input from the exterior.

The phase comparator101compares the timing of edges of the clock signal CLK with the timing of edges of the delay clock signal. When the timing of the clock signal CLK is earlier, the phase comparator101supplies a down-instruction signal to the charge pump102. In response to the down-instruction signal, the charge pump102draws electric charge out of the loop filter103, resulting in the output voltage of the loop filter103being lowered. Consequently, the delay time of the voltage-controlled delay element104is shortened.

When the timing of the clock signal CLK is later, the phase comparator101supplies a up-instruction signal to the charge pump102. In response to the up-instruction signal, the charge pump102supplies electric charge to the loop filter103, resulting in the output voltage of the loop filter103being raised. Consequently, the delay time of the voltage-controlled delay element104is lengthened.

Through such feedback control, the delay of the delay clock signal is adjusted in such a manner that the edges of the delay clock signal output from the voltage-controlled delay element104are aligned with the edges of the clock signal CLK input from the exterior. Specifically, the delay of the voltage-controlled delay element104is adjusted to be equal to once clock cycle of the clock signal CLK.

The voltage-controlled delay element105has the same circuit construction as the voltage-controlled delay element104, and receives the same output voltage of the loop filter103that is supplied to the voltage-controlled delay element104. With this provision, the voltage-controlled delay element105delays a data signal DATA by a delay length equal to the clock cycle of the clock signal. The delay length controlled by the DLL circuit10is stable regardless of the operating voltage of the DLL circuit10or ambient temperature. In this manner, a data path having a desired delay length is provided.

SUMMARY OF THE INVENTION

It is a general object of the present invention to provide a DLL circuit that substantially obviates one or more problems caused by the limitations and disadvantages of the related art.

To achieve these and other advantages in accordance with the purpose of the invention, the invention provides a DLL circuit, including a phase comparator configured to compare timing between a first clock signal and a second clock signal, a delay circuit configured to delay the first clock signal for output as the second clock signal by a delay length responsive to a result of comparison by the phase comparator, and a control circuit configured to suspend supply of the first clock signal to the phase comparator temporarily while the second clock signal is supplied to the phase comparator.

In the DLL circuit according to at least one embodiment of the invention, the control circuit temporarily suspends the supply of the first clock signal for some time duration, so that the phase comparator is in such a state as to detect an edge of the second clock signal supplied from the delay circuit and to wait for an edge to be compared with the detected edge. When the control circuit resumes the supply of the first clock signal, thus, the phase comparator treats the edge of the second clock signal as an edge of earlier timing, and compares this edge with an edge of the first clock signal appearing immediately after this timing. If the delay circuit is set to a delay length shorter than one clock cycle, the edge of the second clock signal is compared with an edge appearing one cycle after a corresponding edge of the first clock signal. With this provision, therefore, the delay length of the delay circuit in the DLL circuit is adjusted so as to be equal to one clock cycle of the first clock signal.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the construction of the DLL circuit10shown inFIG. 1, the edge comparison by the phase comparator101must exhibit a displacement equal to one clock cycle in order for the delay length to be equal to one cycle of the clock signal CLK. Namely, when the first edge of the clock signal CLK is delayed to correspond to the first edge of the delay clock, the second edge immediately following the first edge of the clock signal CLK needs to be compared with the first edge of the delay clock as a corresponding edge for comparison by the phase comparator101. The delay length of the voltage-controlled delay element104thus needs to fall within an initial range between one cycle and two cycles of the clock signal CLK. Otherwise, the delay of the voltage-controlled delay element104does not become equal to one clock cycle when the DLL circuit10is stabilized.

If the initial value of the delay of the voltage-controlled delay element104is less than one cycle of the clock signal CLK, for example, the first edge of the delay clock is compared with the first edge of the clock signal CLK which is immediately preceding in time. Control is thus made such as to shorten the delay length. As a result, the control operation comes into a stable state when the delay length reaches the minimum adjustable delay of the voltage-controlled delay element104. If the initial value of the delay of the voltage-controlled delay element104is larger than two cycles of the clock signal CLK, the first edge of the delay clock is compared with the third edge of the clock signal CLK which is immediately preceding in time. As a result, a stabile state is achieved when the first edge of the delay clock becomes aligned with the third edge of the clock signal CLK, i.e., when the delay length becomes equal to two clock cycles.

Moreover, where the clock signal CLK is temporarily suspended while the DLL circuit10is placed in a stabile state, and then resumes, the delay will be stabilized at the point closest to the maximum delay length of the voltage-controlled delay element104, among points corresponding to integral multiples of the cycle of the clock signal CLK.

Accordingly, there is a need for a DLL circuit which can reliably stabilize a delay length such as to make it equal to one cycle of the input clock signal.

FIG. 2is a block diagram showing an example of the construction of a first embodiment of the DLL circuit according to the invention. A DLL circuit20ofFIG. 2includes the phase comparator101, the charge pump102, the loop filter103, the voltage-controlled delay element (VCDL)104, the voltage-controlled delay element (VCDL)105, a control circuit205, and a reset circuit206. The DLL circuit20ofFIG. 2is preferably implemented as a semiconductor integrated circuit.

The clock signal CLK input from an exterior is supplied to the voltage-controlled delay element104. The voltage-controlled delay element104receives the output of the loop filter103as an input control voltage, and delays the clock signal CLK by a delay length responsive to the control voltage. As for the construction of the voltage-controlled delay element104, provision may be made to reduce a delay length in response to a drop in the input control voltage, or may be made to reduce a delay length in response to a rise in the input control voltage. For the sake of convenience of explanation, the construction assumed here is such that the delay length is reduced in response to a drop in the input control voltage.

The delay clock signal that is output from the voltage-controlled delay element104is supplied to one input of the phase comparator101. The other input of the phase comparator101receives the clock signal CLK via the control circuit205.

In an initial state, a reset signal RESET is set to LOW. With this setting, the control circuit205blocks the clock signal CLK, which is thus not supplied to the phase comparator101. Moreover, since the reset signal RESET is LOW, an NMOS transistor of the reset circuit206becomes conductive, thereby coupling the input of the loop filter103to a ground potential to draw out the electric charge of the loop filter103. As a result, the output voltage of the loop filter103is reduced, setting the voltage-controlled delay element104to a minimum delay length.

Thereafter, the reset signal RESET is changed to HIGH. After the passage of a predetermined time period, the control circuit205supplies the clock signal CLK to the phase comparator101. Since the clock signal CLK is not supplied during the predetermined time period, the phase comparator101is in such a state as to detect an edge of the delay clock signal supplied from the voltage-controlled delay element104and to wait for an edge to be compared with the detected edge. When the supply of the clock signal CLK from the control circuit205starts, thus, the phase comparator101treats the edge of the delay clock signal as an edge of earlier timing, and compares this edge with an edge of the clock signal CLK appearing immediately after this timing. Since the voltage-controlled delay element104is set to a minimum delay length, the edge of the delay clock is compared with an edge appearing one cycle after a corresponding edge of the clock signal CLK, assuming that the minimum delay length is shorter than one clock cycle.

FIG. 3is a signal waveform chart showing the operation of the DLL circuit20ofFIG. 2. As shown inFIG. 3, only after a predetermined time period following a change to HIGH of the reset signal, does the clock signal CLK appear as a phase comparator input. Then, the timing of an edge of the clock signal CLK serving as a phase comparator input is compared with the timing of an edge of the delay clock signal. This comparison reveals that the clock signal CLK is the one that is behind. The delay length of the voltage-controlled delay element104is thus increased through control based on the phase comparator101, the charge pump102, and the loop filter103. As a result, the delay length of the voltage-controlled delay element104increases from the minimum delay length shown inFIG. 3to reach a stable delay length that is equal to one clock length.

Through this feedback control, the delay length of the voltage-controlled delay element104is adjusted equal to one cycle of the clock signal CLK.

The voltage-controlled delay element105has the same circuit construction as the voltage-controlled delay element104, and receives the same output voltage of the loop filter103that is supplied to the voltage-controlled delay element104. With this provision, the voltage-controlled delay element105delays a data signal DATA by a delay length equal to the clock cycle of the clock signal. The delay length controlled by the DLL circuit10is stable regardless of the operating voltage of the DLL circuit10or ambient temperature. In this manner, a data path having a desired delay length is provided.

In the description provided above, the reset circuit206is used for control to keep the delay length of the voltage-controlled delay element104to its minimum. The reset circuit206, however, is not necessarily required. When the control circuit205is suspending the supply of the clock signal CLK, the phase comparator101receives only the delay clock signal from the voltage-controlled delay element104. In such a state, provision may be made such that control operation makes a constant attempt to reduce the delay length of the voltage-controlled delay element104. With such provision, the delay length can be adjusted to its minimum by the time the supply of the clock signal CLK starts if the period of suspension of the clock signal CLK is sufficiently long.

Moreover, the period of suspension of the clock signal CLK is equal to one pulse in the illustration ofFIG. 3. However, the period of suspension of the clock signal may as well be more than a one-pulse period, and may be set to a time length equal to three pulses more or less, thereby achieving a stable, reliable operation.

In the description provided above, the delay length of the voltage-controlled delay element104is set to the minimum delay length. However, the delay length does not have to be reduced all the way down to its minimum. To be specific, it suffices to make the delay length of the voltage-controlled delay element104less than one cycle of the clock signal CLK.

FIG. 4is a circuit diagram showing an example of the construction of the control circuit205. The control circuit205ofFIG. 4includes a counter306and a two-input AND gate307. The counter306does not operate when the reset signal RESET is LOW. The output of the counter306in such state is LOW, and the output of the two-input AND gate307is maintained at LOW. When the reset signal RESET is HIGH, the counter306counts the pulses of the clock signal CLK. Upon counting a predetermined number, the counter306changes its output to HIGH. With the output of the counter306being HIGH, the clock signal CLK passes through the two-input AND gate307to be supplied to the phase comparator101.

In this manner, the control circuit205starts the supply of the clock signal CLK to the phase comparator101after the passage of a predetermined time period following a change to HIGH of the reset signal RESET.

FIG. 5is a block diagram showing an example of the construction of a second embodiment of the DLL circuit according to the invention. InFIG. 5, the same elements as those ofFIG. 2are referred to by the same numbers, and a description thereof will be omitted. A DLL circuit20A ofFIG. 5differs from the DLL circuit20ofFIG. 2in that the control circuit205is replaced by a control circuit205A, and that the reset circuit206is replaced by a reset circuit206A.

FIG. 6is a circuit diagram showing an example of the construction of the control circuit205A. The control circuit205A ofFIG. 6includes a counter408, a counter409, and the two-input AND gate307.FIG. 7is a signal waveform chart showing the operation of the control circuit205A ofFIG. 6.

The counter408does not operate when the reset signal RESET is LOW. The output (DLL RESET) of the counter408in this condition is LOW, so that the counter409is not operating either. Further, the NMOS transistor of the reset circuit206A shown inFIG. 5is OFF. The output of the counter409is LOW, and the output of the two-input AND gate307is maintained at LOW.

When the reset signal RESET changes to HIGH, the counter408changes its output (DLL RESET) to HIGH, and also starts counting the pulses of the clock signal CLK. InFIG. 7, the operation period of the counter408is shown as “OPERATION OF FIRST COUNTER”. During this operation period, DLL RESET is HIGH, so that the NMOS transistor of the reset circuit206A shown inFIG. 5stays conductive, thereby making the delay length of the voltage-controlled delay element104equal to the minimum delay length.

Upon counting a predetermined number, the counter408returns its output to LOW. In response to the fall of the output of the counter408, the counter409starts counting the pulses of the clock signal CLK. InFIG. 7, the operation period of the counter409is shown as “OPERATION OF SECOND COUNTER”. Upon counting a predetermined number, the counter409changes its output to HIGH. With the output of the counter409being HIGH, the clock signal CLK passes through the two-input AND gate307to be supplied to the phase comparator101.

In this manner, the control circuit205A sets the delay length of the voltage-controlled delay element104to the minimum value during a first predetermined time period following the change to HIGH of the reset signal RESET, and starts the supply of the clock signal CLK to the phase comparator101after the passage of a second predetermined time period following the first predetermined time period. In the first embodiment, the time period for the adjustment of the delay length of the voltage-controlled delay element104depends on the period during which the reset signal is LOW, so that proper control is necessary on the part of the system to control the LOW period of the reset signal. In the second embodiment, on the other hand, the counting operation of the counter408defines the period for adjustment, so that there is no need on the part of the system to take into account the detail of the reset signal such as the duration thereof. This makes it easier to control the DLL circuit.

FIG. 8is a circuit diagram showing a variation of the control circuit205A. In the control circuit205A ofFIG. 6, the counter for counting a first count and the counter for counting a second count are provided for the purpose of defining the period for delay adjustment and the period of clock suspension, respectively. For the purpose of defining these two periods, however, two counters may not be necessary. A single counter may be provided to perform a single counting operation. Provision is then made to assert a signal both at the timing the count reaches a first number and at the timing the count reaches a second number.

In the control circuit205B ofFIG. 8, a single counter410is provided in place of the counters408and409ofFIG. 6. In response to a change to HIGH in the reset signal RESET, the counter410starts counting the pulses of the clock signal CLK, and, at the same time, changes the DLL RESET signal to HIGH. When the count reaches a first number, the DLL RESET signal is changed to LOW. Counting continues thereafter, and an output to the two-input AND gate307is changed to HIGH when the count reaches a second number.

The control circuit as described above successfully performs the operation as shown inFIG. 7.

FIG. 9is a circuit diagram showing another example of the construction of the control circuit. InFIG. 9, the same elements as those ofFIG. 6are referred to by the same numbers, and a description thereof will be omitted.

InFIG. 9, an oscillator510, a counter511, and a two-input AND gate512are provided in addition to the construction of the control circuit205shown inFIG. 6. The oscillator510is constantly oscillating at predetermined frequency. The counter511performs counting operation in response to the oscillating clock of the oscillator510. The reset terminal of the counter511receives the clock signal CLK. During the period in which the clock signal CLK is supplied, the counter511is constantly subjected to resetting operation.

If the supply of the clock signal CLK stops for some reason, the counter511disengages from the reset state, and starts counting operation based on the oscillating clock of the oscillator510. When the count reaches a predetermined value, the counter511changes its output to the two-input AND gate512to HIGH. Since the reset signal RESET is in a negated (HIGH) state, the two-input AND gate512supplies a HIGH signal to the counter408in response to the HIGH signal output from the counter511. In this construction, the counter408is reset by a HIGH reset signal.

In the control circuit ofFIG. 9as described above, when the supply of the clock signal CLK stops for some reason while the DLL circuit is operating in a stabile state, the counter408is reset after the passage of a predetermined time period measured by the counter511. With this, a circuit portion identical to the control circuit205A ofFIG. 6is reset.

When the supply of the clock signal CLK resumes, the counter511is reset, resulting in the output of the two-input AND gate512being LOW. In response, the counter408recovers from the reset state, so that the same operation as that of the control circuit205A shown inFIG. 7will ensue.

In this manner, the period for delay adjustment and the period of clock suspension as shown inFIG. 7are provided in the case where the supply of the clock signal CLK stops for some reason and subsequently resumes. This makes it possible to set the delay length to its minimum and to establish proper edge correspondence for edge comparison. Accordingly, the delay of the DLL circuit is reliably set to one clock cycle even in the case of suspension and subsequent recovery of the clock signal CLK.

FIG. 10is a circuit diagram showing an example of the construction of the phase comparator101. The phase comparator101ofFIG. 10includes NAND gates51through59, inverters60and61, and buffers62through66.

Outputs DOWN and UP of the phase comparator101are negative logic signals. That is, the outputs DOWN and UP are initially maintained at HIGH, and are changed to LOW to indicate assertion. When a rising edge of the clock signal CLK arrives ahead of a rising edge of the delay clock signal, the output of the NAND gate51becomes HIGH, resulting in the signal DOWN changing to LOW for assertion. A rising edge of the delay clock signal thereafter arrives. In response, the output of the NAND gate56becomes HIGH. Before this HIGH signal reaches the NAND gate59, the output of the NAND gate57changes to LOW, so that the signal UP is kept at HIGH. In response to the LOW output of the NAND circuit57, the signal DOWN returns to HIGH. In this manner, the signal DOWN is asserted during the period from the rising edge of the clock signal CLK to the rising edge of the delay clock signal if the rising edge of the clock signal CLK is the first to come. If the rising edge of the delay clock signal is the first to come, on the other hand, the signal UP is asserted during the period from the rising edge of the delay clock signal to the rising edge of the clock signal CLK.

FIG. 11is a circuit diagram showing an example of the circuit construction of the charge pump102. The charge pump102ofFIG. 11includes inverters71through73, a PMOS transistor74, and an NMOS transistor75. The junction point of the PMOS transistor74and the NMOS transistor75is an output terminal OUT, which is coupled to the input of the loop filter103.

When the signal UP is asserted, the PMOS transistor74is turned on, and electric charge is supplied to the loop filter103through the output terminal OUT. When the signal DOWN is asserted, the NMOS transistor75is turned on, and electric charge is drawn out of the loop filter103through the output terminal OUT.

FIG. 12is a circuit diagram showing an example of the construction of the loop filter103. The loop filter103shown inFIG. 12includes a resistor81and a capacitor82. An input terminal IN is coupled to the output terminal of the charge pump102. When electric charge is supplied from the charge pump102, the electric charge will be stored in, the capacitor82through the resistor81, resulting in a voltage rise at the output terminal OUT of the loop filter103. When electric charge is drawn out by the charge pump102, the electric charge discharges from the capacitor82through the resistor81, resulting in a voltage drop at the output terminal OUT of the loop filter103.

FIG. 13is a circuit diagram showing an example of the circuit construction of the voltage-controlled delay element104. The voltage-controlled delay element104ofFIG. 13includes delay elements91through94. The delay elements91through94receive a direct-current voltage VIN as their drive power supply. This direct-current voltage VIN is a voltage that appears at the output terminal of the loop filter103. The delay elements91through94may be simple buffers, for example. As the direct-current voltage VIN serving as drive power supply rises, response speed increases, and the delay time decreases. Conversely, as the direct-current voltage VIN drops, response speed decreases and the delay time increases. The descriptions of the above embodiments have been provided with reference to a case in which the delay length of the voltage-controlled delay element104increases as the input control voltage increases. To achieve such operational characteristics, the direct-current voltage VIN may be inverted by an inverter before it is input into the delay elements91through94.

InFIG. 13, the respective outputs of the delay elements91through94are taken out. When the voltage-controlled delay element104is adjusted to have a delay length equal to one clock cycle, therefore, clock signals having 90-degree delay, 180-degree delay, 270-degree delay, and 360-degree delay are generated for use in other circuits.

The above descriptions have been given with reference to an example in which the delay element104in the DLL circuit is subjected to voltage-based analog control. Notwithstanding this, the present invention is not limited to a DLL circuit based on analog control, and is applicable to a DLL circuit based on digital control in which the delay length of a delay element is controlled based on digital values. In general, it is more difficult to set an initial delay length to a desired value in the analog-control-based DLL circuit than in the digital-control-based DLL circuit. In the analog-control-based DLL circuit, also, it is more difficult to achieve a desired value for the delay length that is locked in a stable state. Because of these reasons, the present invention may produce more advantageous results when it is applied to the analog-control-based DLL circuit.