SEMICONDUCTOR PACKAGES HAVING TEST PADS

A semiconductor package, includes: a base chip having a front surface and a back surface opposite to the front surface, the base chip including bump pads, wafer test pads, and package test pads, disposed on the front surface; connection structures disposed on the front surface of the base chip and connected to the bump pads; and semiconductor chips stacked on the back surface of the base chip, wherein each of the wafer test pads is smaller than the package test pads.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority and benefit thereof under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0143844, filed on Nov. 1, 2022, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.

BACKGROUND

The present inventive concept relates to a semiconductor package having a test pad.

2. Description of Related Art

As demands for high performance, high speed, and/or multifunctionality of semiconductor devices increase, a degree of integration of semiconductor devices is increasing. In manufacturing a semiconductor device with a fine pattern corresponding to the trend of high integration of semiconductor devices, it is required to implement patterns having a fine width or a fine separation distance. In addition, high integration of semiconductor devices mounted in a semiconductor package is required.

SUMMARY

An aspect of the present inventive concept is to provide a semiconductor package having a miniaturized test pad.

According to example embodiments, a semiconductor package may include: a base chip having a front surface and a back surface opposite to the front surface, the base chip including bump pads, wafer test pads, and package test pads disposed on the front surface thereof; connection structures disposed on the front surface of the base chip and connected to the bump pads; and semiconductor chips stacked on the back surface of the base chip. Each of the wafer test pads may be smaller than the package test pads in size.

According to example embodiments, a semiconductor package may include: a base chip having a front surface and a back surface opposite to the front surface, the base chip including bump pads, wafer test pads, and package test pads disposed on the front surface thereof; connection structures disposed on the front surface of the base chip and connected to the bump pads; and semiconductor chips stacked on the back surface of the base chip and including test pads. Each of the wafer test pads may be smaller than the package test pads and larger than or equal to the test pads in size.

According to example embodiments, a semiconductor package, may include: a base chip having a front surface and a back surface opposite to the front surface; semiconductor chips stacked on the back surface of the base chip; connection structures disposed on the front surface of the base chip; and a molded layer covering the base chip and the semiconductor chips. The base chip may include a base body; through electrodes penetrating through the base body; an internal circuit structure disposed below the base body and including internal interconnections; and a base back structure disposed on the base body. The internal circuit structure may include bump pads disposed on the front surface, wafer test pads electrically connected to at least one of the internal interconnections, and package test pads electrically connected to at least one of the semiconductor chips. Each of the wafer test pads may be smaller than the package test pads in size.

DETAILED DESCRIPTION

Hereinafter, preferred example embodiments of the present inventive concept will be described with reference to the accompanying drawings as follows. Like numerals refer to like elements throughout.

It will be understood that when an element is referred to as being “connected” or “coupled” to or “on” another element, it can be directly connected or coupled to or on the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, or as “contacting” or “in contact with” another element (or using any form of the word “contact”), there are no intervening elements present at the point of contact.

Terms such as “same,” “equal,” “planar,” or “coplanar,” as used herein when referring to orientation, layout, location, shapes, sizes, amounts, or other measures do not necessarily mean an exactly identical orientation, layout, location, shape, size, amount, or other measure, but are intended to encompass nearly identical orientation, layout, location, shapes, sizes, amounts, or other measures within acceptable variations that may occur, for example, due to manufacturing processes. The term “substantially” may be used herein to emphasize this meaning, unless the context or other statements indicate otherwise.

FIG.1is a cross-sectional view of a semiconductor package according to example embodiments.

FIG.2are cross-sectional views illustrating some components shown inFIG.1in an exploded manner.

Referring toFIGS.1and2, a semiconductor package10according to an example embodiment of the present disclosure may include connection structures20, a base chip100, and first to fourth semiconductor chips200,300,400, and500, sequentially stacked on the base chip100, and a molded layer M. The semiconductor package10may be mounted on a package substrate12through the connection structures20.

The semiconductor package10of the present disclosure may be a high bandwidth memory (HBM) package. In an example embodiment, the base chip100may be a different type of semiconductor chip from the first to fourth semiconductor chips200,300,400, and500. For example, the base chip100may be a logic chip, and the first to fourth semiconductor chips200,300,400, and500may be memory chips. The logic chip may include a microprocessor, an analog device, or a digital signal processor. The memory chips may include a volatile memory chip such as dynamic random access memory (DRAM) or static random access memory (SRAM), or a non-volatile memory chip such as phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM).

The base chip100may be mounted on the package substrate12through the connection structures20. The base chip100may include a base body105, through electrodes110, an internal circuit structure120, and a base back surface structure130. The base body105may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. The through electrodes110may extend in a vertical direction, and may penetrate through the base body105. Each of the connection structures20may be a solder ball or bump, and may be formed of a conductive material, such as a metal, for example.

The internal circuit structure120may be disposed below the base body105, and may be connected to the connection structure20. The internal circuit structure120may include internal interconnections122, a lower insulating layer124, bump pads BP, wafer test pads WTP, and package test pads PTP. The internal interconnections122may be disposed in layers, and the through electrode110may be electrically connected to at least one of the internal interconnections122. In addition, the bump pads BP may be connected to at least one of the internal interconnections122, and the package test pads PTP may be electrically connected to at least one of the internal interconnections122.

The lower insulating layer124may cover a lower surface of the base body105and the internal interconnections122. The lower insulating layer124may also partially cover side surfaces of the through electrodes110. The bump pads BP may be exposed without being completely covered by the lower insulating layer124. The bump pads BP may contact a connection structure20, and electrically connect the connection structure20to at least one of the internal interconnections122. A lower surface of the base chip100on which the bump pads BP are disposed and facing the package substrate12may be referred to as a front surface FS of the base chip100.

The wafer test pads WTP may be used to determine whether the internal circuit structure120is defective, and may be disposed on the front surface FS of the base chip100. The wafer test pads WTP may be buried in the lower insulating layer124, but may be exposed without being completely covered by the lower insulating layer124. In example embodiments, lower surfaces of the wafer test pads WTP may be coplanar with the front surface FS of the base chip100. The wafer test pads WTP may be electrically connected to at least one of the internal interconnections122. The wafer test pads WTP may not contact the connection structures20.

The package test pads PTP may be used to determine whether first to fourth semiconductor chips200,300,400, and500are defective, and may be disposed on the front surface FS of the base chip100. The package test pads PTP may be buried in the lower insulating layer124, but may be exposed without being completely covered by the lower insulating layer124. In example embodiments, lower surfaces of the package test pads PTP may be coplanar with the front surface FS of the base chip100. The package test pads PTP may be electrically connected to at least one of the first to fourth semiconductor chips200,300,400, and500through at least one of the through electrodes110. The package test pads PTP may not contact the connection structures20.

According to an example embodiment of the present disclosure, the wafer test pads WTP may be formed to be smaller than the package test pads PTP. Both the wafer test pads WTP and the package test pads PTP may be formed to be larger than the bump pads BP. In addition, the wafer test pads WTP may be disposed farther from a central portion of the front surface FS of the base chip100than the test package pads PTP. Alternatively, a distance between the wafer test pads WTP and a side surface of the base chip100, adjacent thereto may be smaller than a distance between the package test pads PTP and a side surface of the base chip100adjacent thereto.

The base back structure130may be disposed on the base body105. The base back structure130may include an internal interconnection132, an upper insulating layer134, bonding pads136, and a passivation layer138. The internal interconnection132may be disposed on the through electrodes110, and may be electrically connected to the through electrodes110. The upper insulating layer134may cover an upper surface of the base body105and the internal interconnection132. The upper insulating layer134may also partially cover side surfaces of the through electrodes110.

The bonding pads136may be disposed on the upper insulating layer134, and may be electrically connected to the through electrodes110through the internal interconnection132. The passivation layer138may cover the upper insulating layer134, and may cover side surfaces of the bonding pads136. The bonding pad136may not be completely covered by the passivation layer138, and upper surfaces of the bonding pads136may be exposed. In example embodiments, the upper surfaces of the bonding pads136may be coplanar with an upper surface of the passivation layer138. The bonding pads136may electrically connect the through electrodes110to at least one of the first to fourth semiconductor chips200,300,400, and500. An upper surface of the base chip100on which the bonding pads136are disposed and facing the first semiconductor chip200may be referred to as a back surface BS of the base chip100.

The first to fourth semiconductor chips200,300,400, and500may be sequentially stacked on the back surface BS of the base chip100. Referring further toFIG.2, the first semiconductor chip200may include a semiconductor body205, through electrodes210, an internal circuit structure220, an upper insulating layer230, bonding pads232, and a passivation layer234. The semiconductor body205may include a semiconductor material such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. The through electrodes210may extend in a vertical direction, and may penetrate through the semiconductor body205.

The internal circuit structure220may be disposed below the semiconductor body205, and may be connected to the base back surface structure130of the base chip100. The internal circuit structure220may include internal interconnections222, a lower insulating layer224, bonding pads226, test pads TP, and a passivation layer228. The internal interconnections222may be disposed in layers, and the through electrodes210may be electrically connected to at least one of the internal interconnections222. In addition, the bonding pads226and the test pads TP may be electrically connected to at least one of the internal interconnections222.

The lower insulating layer224may cover a lower surface of the semiconductor body205and the internal interconnections222. The lower insulating layer224may also partially cover side surfaces of the through electrodes210. The passivation layer228may be disposed below the lower insulating layer224, and may cover a lower surface of the lower insulating layer224. The bonding pads226and the test pads TP may be disposed below the lower insulating layer224, and may be exposed without being completely covered by the passivation layer228. For example, lower surfaces of the bonding pads226and the test pads TP may be coplanar with a lower surface of the passivation layer228. The bonding pads226of the first semiconductor chip200may contact the bonding pads136of the base chip100, and may electrically connect the base chip100to at least one of the internal interconnections222. The test pads TP may contact the passivation layer138of the base chip100, but may not be electrically connected to the base chip100. The test pads TP may not contact the bonding pads136of the base chip100.

The upper insulating layer230, the bonding pads232, and the passivation layer234may be disposed on the semiconductor body205. The upper insulating layer230may cover an upper surface of the semiconductor body205, and may partially cover side surfaces of the through electrode210. The bonding pads232may be disposed on the upper insulating layer230, and may be electrically connected to the through electrodes210. The passivation layer234may cover the upper insulating layer230, and may cover side surfaces of the bonding pads232. The bonding pads232may not be completely covered by the passivation layer234, and upper surfaces of the bonding pads232may be exposed. For example, the upper surfaces of the bonding pads232may be coplanar with an upper surface of the passivation layer234.

The second and third semiconductor chips300and400may include the same components as those of the first semiconductor chip200. For example, each of the second and third semiconductor chips300and400may include semiconductor bodies305and405, through electrodes310and410penetrating through the semiconductor bodies305and405, respectively, and test pads TP. The semiconductor bodies305and405may be substantially the same as the semiconductor body205, and the through electrodes310and410may be substantially the same as the through electrodes210. A detailed description of the second and third semiconductor chips300and400may be omitted.

The fourth semiconductor chip500may include a semiconductor body505and an internal circuit structure520disposed below the semiconductor body505. The semiconductor body505of the fourth semiconductor chip500may include the same material as the semiconductor body205of the first semiconductor chip200. The internal circuit structure520may include an internal interconnection522, a lower insulating layer524, bonding pads526, test pads TP, and a passivation layer528. The internal circuit structure520of the fourth semiconductor chip500may have substantially the same structure as that of the internal circuit structure120of the first semiconductor chip200. The bonding pads526of the fourth semiconductor chip500may contact the bonding pads of the third semiconductor chip400. The test pads TP of the fourth semiconductor chip500may contact the passivation layer of the third semiconductor chip400. The test pads TP of the fourth semiconductor chip500may not contact the bonding pads of the third semiconductor chip400.

FIG.3is a plan view of the base chip illustrated inFIG.1viewed from below.

Referring toFIG.3, bump pads BP, wafer test pads WTP, and package test pads PTP are disposed on a front surface FS of the base chip100. When viewed in plan view, the bump pads BP may have circular shapes, and the wafer test pads WTP and package test pads PTP may have square or rectangular shapes. However, an example embodiment thereof is not limited thereto, and in some example embodiments, the wafer test pads WTP and the package test pads PTP may have a shape such as a triangle, a rhombus, a circle, or the like. As described above, the wafer test pad WTP and the package test pad PTP may be larger than the bump pad BP, and the wafer test pad WTP may be smaller than the package test pad PTP. For example, an area of the wafer test pad WTP may be smaller than an area of the package test pad PTP. For example, the wafer test pad WTP may have a first side surface WTPa having a first width W1aand a second side surface WTPb having a second width W1b, wherein the first width W1amay be about 40 μm to about 60 μm, and the second width W1bmay be about 100 μm to about 150 μm. A distance D1between adjacent wafer test pads WTP may be about 10 μm to about 30 μm. Here, the distance D1between adjacent wafer test pads WTP may refer to a distance between opposite sides of the adjacent wafer test pads WTP. The package test pad PTP may have a first side surface PTPa having a first width W2aand a second side surface PTPb having a second width W2b, wherein the first width W2amay be about 65 μm to about 100 μm, and the second width W2bmay be about 100 μm to about 150 μm. A distance D2between adjacent package test pads PTP may be about 30 μm to about 50 μm. Here, the distance D2between adjacent package test pads PTP may refer to a distance between opposite sides of the adjacent package test pads PTP.

In an example embodiment, the wafer test pads WTP and the package test pads PTP may be disposed along an edge of the base chip100. For example, the base chip100may have first to fourth side surfaces101a,101b,101c, and101d, and the wafer test pads WTP and the package test pads PTP may be disposed in a row, respectively, along the first side surface101a. For example, the package test pads PTP may be disposed in a row adjacent to the first side surface101a, and the wafer test pads WTP may be disposed in another row adjacent to the first side surface101abetween the row of package test pads PTP and the first side surface101a. In addition, the package test pads PTP may be disposed in a row along the second side surface101band in a row along the third side surface101c. In an example embodiment, the wafer test pads WTP may be disposed farther from a central portion of the front surface FS of the base chip100than the package test pads PTP. For example, each of the wafer test pads WTP along (or adjacent to) the first side surface101amay be disposed closer to the first side surface101athan the package test pads PTP along (or adjacent to) the first side surface101a.

The wafer test pads WTP according to example embodiments of the present disclosure may be formed to be smaller than the package test pads PTP, and as illustrated inFIG.3, the wafer test pads WTP having the smaller size may be disposed to be closer to a side surface of the base chip100than the package test pads PTP. Therefore, the size of the base chip100may be reduced as compared to the case in which the wafer test pads WTP and the package test pads PTP are formed to have the same size, and the size of the semiconductor package10can be reduced. In addition, since the size of the wafer test pads WTP is reduced, space efficiency in which the test pads WTP and PTP are to be disposed increases, and the test pads WTP and PTP may be disposed in various manners.FIG.3is an exemplary layout diagram for illustrating wafer test pads WTP and package test pads PTP, but an example embodiment thereof is not limited thereto. In some example embodiments, various dispositional structures may be possible.

FIGS.4A to4Dare partial plan views of a base chip viewed from below according to example embodiments.FIGS.4A to4Dillustrate the partial region ofFIG.3.

Referring toFIG.4A, a base chip100aaccording to an example embodiment may include wafer test pads WTP and package test pads PTP, alternately disposed. For example, the wafer test pads WTP and the package test pads PTP may be alternately disposed along the second side surface101bof the base chip100, and the wafer test pads WTP and the package test pads PTP may be alternately disposed along the third side surface101cof the base chip100. A distance D3between adjacent wafer test pads WTP and package test pads PTP among the wafer test pads WTP and package test pads PTP, alternately disposed, may be equal to the distance D2. For example, the distance D3between adjacent wafer test pads WTP and package test pads PTP may be 30 μm to 50 μm.

As illustrated inFIG.4A, when the wafer test pads WTP and the package test pads PTP are alternately disposed, more test pads WTP and PTP may be disposed in the same space, as compared to the case in which the wafer test pads WTP and the package test pads PTP are formed to have the same size, and accordingly, the size of the semiconductor package10may be reduced.

Referring toFIG.4B, a base chip100baccording to an example embodiment may include wafer test pads WTP disposed along second and third side surfaces101band101cof the base chip100. Since the size of the wafer test pad WTP is smaller than that of the package test pad PTP, the size of the semiconductor package10may be reduced as compared to the case in which the package test pads PTP are disposed along the second and third side surfaces101band101c.

Referring toFIG.4C, a base chip100caccording to an example embodiment may include package test pads PTP disposed between bump pads BP. For example, a second row of package test pads PTP may be disposed in parallel to the first side surface101aand between bump pads BP.

Referring toFIG.4D, a base chip100daccording to an example embodiment may include wafer test pads WTP and package test pads PTP disposed between bump pads BP. The wafer test pads WTP and package test pads PTP may be disposed in a row, respectively. As illustrated inFIGS.4C and4D, the size of the semiconductor package may be reduced by disposing the wafer test pads WTP or the package test pads PTP between the bump pads BP.

FIGS.5A and5Bare schematic plan views illustrating test pads TP according to example embodiments.

FIGS.5A and5Billustrate a wafer test pad WTP and a package test pad PTP disposed on a front surface FS of a base chip100and a test pad TP disposed on lower surfaces of first to fourth semiconductor chips200,300,400, and500.

Referring toFIG.5A, in an example embodiment, the wafer test pad WTP and the test pad TP may have the same size. In addition, as described above, the wafer test pad WTP of the present disclosure may be smaller than the package test pad PTP. For example, a first width W1aof the wafer test pad WTP may be smaller than a first width W2aof the package test pad PTP and/or a second width W1bof the wafer test pad WTP may be smaller than a second width W2bof the package test pad PTP.

Referring toFIG.5B, in an example embodiment, the wafer test pad WTP may be larger than the test pad TP and smaller than the package test pad PTP. For example, the first width W1aof the wafer test pad WTP may be larger than the first width Wa of the test pad TP and/or the second width W1bof the wafer test pad WTP may be larger than the second width Wb of the test pad TP.

FIG.6is a flow chart illustrating a method of manufacturing a semiconductor package according to example embodiments.

FIGS.7to14are cross-sectional views illustrating a method of manufacturing a semiconductor package according to a process sequence according to example embodiments.

Referring toFIGS.6to14, a method of manufacturing a semiconductor package according to an embodiment of the present disclosure may include forming through electrodes110in a base wafer104(S100), forming an internal circuit structure120(S200), forming a connection structure20(S400), forming a base back structure130(S500), stacking semiconductor chips (S600), forming a molded layer M (S700), and cutting the base wafer104(S900). In addition, the method may further include forming an internal circuit structure120(S200), and then performing a test on wafer test pads WTP (S300), and forming a molded layer M (S700), and then performing a test on package test pads PTP (S800).

Referring toFIG.7, a base wafer104may be provided. The base wafer104may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. Thereafter, through electrodes110may be formed in the base wafer104(S100). Forming the through electrodes110may include forming a hole by etching one surface of the base wafer104, forming an insulating material covering an inner wall of the hole, and forming a conductive material filling the hole. The through electrodes110may not completely penetrate through the base wafer104.

Referring toFIG.8, an internal circuit structure120may be formed on the resulting structure ofFIG.7(S200). For example, internal interconnections122electrically connected to the through electrodes110may be formed in a plurality of layers on the one surface of the base wafer104, and the lower insulating layer124may be formed to cover the through electrodes110and the internal interconnections122.FIG.8illustrates that an upper surface of the base wafer104is partially recessed, but an example embodiment thereof is not limited thereto. Although not illustrated, the internal circuit structure120may further include circuit elements electrically connected to the internal interconnections122, and the circuit elements include active elements such as transistors and passive elements such as resistors and capacitors.

In addition, bump pads BP, wafer test pads WTP, and package test pads PTP electrically connected to the internal interconnections122may be formed. The wafer test pads WTP may be formed to be larger than the bump pads BP, and the package test pads PTP may be formed to be formed to be larger than the wafer test pads WTP. Each of the bump pads BP, the wafer test pads WTP, and the package test pads PTP may not be completely covered by the lower insulating layer124, and at least an upper surface thereof may be exposed. The bump pads BP may be positioned at the same level as the wafer test pads WTP and the package test pads PTP.

At least one of the bump pads BP may be electrically connected to one of the through electrodes110through an internal interconnection122. The wafer test pads WTP may be electrically connected to the internal interconnection122. Each of the package test pads PTP may be electrically connected to one of the through electrodes110through the internal interconnection122. The internal interconnections122, the bump pads BP, the wafer test pads WTP, and the package test pads PTP may include a conductive material, such as copper (Cu), aluminum (Al), or silver. (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The lower insulating layer124may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

Referring toFIG.9, a test may be performed on a wafer test pad WTP (S300). The test may be performed using a probe card P1. Since the wafer test pad WTP is electrically connected to internal interconnections122of the internal circuit structure120, it is possible to determine whether the internal circuit structure120is defective by the test. For example, the internal circuit structure120may be tested by contacting a probe pin PP of the probe card P1to the wafer test pad WTP to measure an electrical short circuit and leakage current of the internal interconnections122. In example embodiments, the internal circuit structure120may be tested by contacting a plurality of probe pins PP of the probe card P1to a plurality of wafer test pads WTP to measure an electrical short circuit and leakage current of the internal interconnections122.

Referring toFIG.10, connection structures20may be formed on an internal circuit structure120(S400). The connection structures20may be formed to contact bump pads BP, and may be electrically connected to the internal circuit structure120or the through electrodes110through the bump pads BP. The connection structures20may include tin (Sn) or an alloy (Sn—Ag—Cu) containing tin (Sn). In some example embodiments, after the connection structures20are formed, a test may be further performed on the wafer test pad WTP. The test may determine whether a defect has occurred in the internal circuit structure120in a process of forming the connection structures20.

Referring toFIG.11, a base back structure130may be formed by inverting the resulting structure ofFIG.10(S500). The base back structure130may be located on an opposite side of a base wafer104to the internal circuit structure120. Forming the base back structure130may include grinding the base wafer104to expose through electrodes110. An internal interconnection132connected to the exposed through electrodes110and an upper insulating layer134covering the internal interconnection132may be formed, and bonding pads136and a passivation layer138may be formed on the upper insulating layer134to form a base back surface structure130. Although a portion of the base wafer104is illustrated inFIG.11as being recessed, an example embodiment thereof is not limited thereto.

The internal interconnection132may be electrically connected to the through electrodes110. The upper insulating layer134may cover the base wafer104, the through electrodes110, and the internal interconnection132. The bonding pads136may be formed on the upper insulating layer134and may be electrically connected to the internal interconnection132. The passivation layer138may be formed on the upper insulating layer134, and may protect the upper insulating layer134. The bonding pads136may not be covered by the passivation layer138.

The internal interconnection132and the bonding pads136may include a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. In an example embodiment, the bonding pads136may include copper (Cu). The upper insulating layer134may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, and the passivation layer138may include a thermosetting resin.

Referring toFIG.12, semiconductor chips may be stacked on a base back surface structure130(S600). For example, first to fourth semiconductor chips200,300,400, and500may be stacked on the base back surface structure130. The base back structure130may contact and be coupled to an internal circuit structure220of the first semiconductor chip200. For example, each of the bonding pads136of the base back surface structure130may contact and be coupled to a bonding pad226of the first semiconductor chip200, and the passivation layer138of the base back surface structure130may contact and be coupled to a passivation layer228of the first semiconductor chip200. The bonding pads136of the base back structure130may be electrically connected to the through electrodes210through the bonding pads226of the first semiconductor chip200.

A second semiconductor chip300may be stacked on the first semiconductor chip200. Each bonding pad232disposed above the first semiconductor chip200may contact and be coupled to a bonding pad326disposed below the second semiconductor chip300. Thereafter, the third semiconductor chip400and the fourth semiconductor chip500may be sequentially stacked in the same manner. In an example embodiment of the present disclosure, each of the bonding pads is illustrated as directly contacting each other, but an example embodiment thereof is not limited thereto. In some example embodiments, bumps may be disposed between each of the bonding pads, and an adhesive material such as a non-conductive film (NCF) or a non-conductive paste (NCP) covering side surfaces of the bumps may be used to stack the first to fourth semiconductor chips200,300,400, and500.

Referring toFIG.13, a molded layer M may be formed (S700). The molded layer M may cover an upper surface of the base back surface structure130and side surfaces of the first to fourth semiconductor chips200,300,400, and500. In an example embodiment, after the molded layer M is formed to cover an upper surface of the fourth semiconductor chip500, an upper portion of the molded layer M may be ground so that the upper surface of the fourth semiconductor chip500is exposed.

The molded layer M may be a resin including epoxy or polyimide. For example, the resin may be a bisphenol-group epoxy resin, a polycyclic aromatic epoxy resin, an o-Cresol novolac epoxy resin, a biphenyl epoxy resin, or a naphthalene-group epoxy resin.

Referring toFIG.14, a test may be performed on a package test pad PTP (S800). The test may be performed by contacting a probe pin PP of a probe card P2to the package test pad PTP. The package test pad PTP may be electrically connected to at least one of first to fourth semiconductor chips200,300,400, and500through the through electrodes110of the internal circuit structure120. Therefore, it is possible to determine whether at least one of the first to fourth semiconductor chips200,300,400, and500is defective by the test. In example embodiments, the first to fourth semiconductor chips200,300,400, and500may be tested by contacting a plurality of probe pins PP to a plurality of package test pads PTP to determine whether at least one of the first to fourth semiconductor chips200,300,400, and500is defective by the test. Since the package test pad PTP is formed relatively larger than the wafer test pad WTP, even if the base wafer104is contracted in a horizontal direction by heat in the operation of forming the molded layer M (S700), the package test pad PTP may contact the probe pin PP. Therefore, according to example embodiments of the present disclosure, contact defects between the probe pin PP and the package test pad PTP can be prevented.

Referring back toFIG.1, a sawing process of cutting the base wafer104may proceed (S900). For example, the base wafer104together with the molded layer M may be cut, and the semiconductor package10illustrated inFIG.1may be formed. The cut and individualized base wafer104may be referred to as a base body105, and the base body105, the through electrodes110, the internal circuit structure120, and the base back structure130may form a base chip100. In some example embodiments, after the base wafer104is cut, a test may be further performed on the package test pad PTP. The test may determine whether a defect has occurred in the first to fourth semiconductor chips200,300,400, and500in the sawing process. The semiconductor package10may be mounted on the package substrate12through the connection structure20.

As set forth above, according to example embodiments of the inventive concept, a wafer test pads may be formed to be smaller than a package test pad.

Therefore, contact defects between the test pad and a probe pin can be prevented, and a miniaturized semiconductor package may be provided.