Method of utilizing trench silicide in a gate cross-couple construct

A method of forming a logic cell utilizing a TS gate cross-couple construct and the resulting device are provided. Embodiments include forming active fins and dummy fins on a substrate, the dummy fins adjacent to each other and between the active fins; forming STI regions between and next to the active and dummy fins; forming gate structures in parallel across the active and dummy fins; forming a gate cut region by cutting the gate structures between the dummy fins; forming a TS layer between the gate structures, the TS layer crossing the gate cut region; and forming a contact connecting a gate structure and the TS layer on a first side of the gate cut region and forming a contact connecting a gate structure and the TS layer on a second side of the gate cut region, the TS layer and contacts cross coupling the gate structures.

TECHNICAL FIELD

The present disclosure relates to semiconductor cross-coupling designs. The present disclosure is particularly applicable to 7 nanometer (nm) technology nodes and beyond.

BACKGROUND

Cross-couple gate structures are important for standard cell design to achieve product area scaling goals for logic and memory peripheral. For example, cross-coupling structures may be used to connect a p-type metal-oxide-semiconductor (pMOS) gate transistor and n-type MOS (nMOS) gate transistor with different gates in a logic cell. However, as technology node advances such as 14 nm technology nodes and beyond, lithography resolution is insufficient to print connected gates.

For example, middle of line (MOL) layers such as source/drain contacts (CA) and gate contacts (CB) can be used to cross couple gates. Such an approach for forming a cross-coupled logic cell is illustrated inFIGS. 1A and 1B(FIG. 1Ais a top view andFIG. 1Bis a generalized cross-sectional view). Adverting toFIG. 1A, active fins (or active layer)101aand101band dummy fins103aand103b(to be eliminated) are formed with STI regions105therebetween. Gate structures107, e.g.,107a-107e, are then formed across the active fins101aand101b, the dummy fins103aand103b, and the STI regions105. Next, gate contacts109and S/D contacts111are formed on the gate structures107athrough107eand active fins101aand101b, respectively. Thereafter, portions of gate structures107band107care cut out between the active or dummy fins103aand103b, e.g., by double patterning, to form the gate cut region113. Consequently, the neighboring pMOS formed by active fins101aand the nMOS formed by active fins101balong the same gate are disconnected.

Adverting toFIG. 1B, gate structures107are formed on a substrate121, the substrate121having silicide or salicide portions123. Next, gate contacts109and S/D contacts111are formed on the gate structures107and the silicide portions123, respectively. A metal layer125is then formed on top of the gate contacts109and S/D contacts111, respectively. As shown, gate contacts109and S/D contacts111are formed on the same level. Consequently, as shown by the arrows inFIG. 1A, tight spacing among the S/D contacts111and115and gate contacts109causes considerable congestion, which in turn reduces overall design flexibility.

A need therefore exists for methodology enabling cross coupling of disconnected gates in advanced logic cells while mitigating design congestion.

SUMMARY

An aspect of the present disclosure is a process of forming a logic cell utilizing a trench silicide (TS) layer in a gate cross-couple construct.

Another aspect of the present disclosure is a logic cell device having a TS layer gate cross-couple construct.

According to the present disclosure, some technical effects may be achieved in part by a method including: forming first and second active fins and first and second dummy fins on a substrate, the first and second dummy fins adjacent to each other and between the first and second active fins; forming STI regions between and next to the first and second active fins and the first and second dummy fins; forming first and second gate structures in parallel across the first and second active fins and the first and second dummy fins; forming a gate cut region by cutting the first and second gate structures between the first and second dummy fins; forming a TS layer between the first and second gate structures, the TS layer crossing the gate cut region; and forming a first contact connecting the first gate structure and the TS layer on a first side of the gate cut region and forming a second contact connecting the second gate structure and the TS layer on a second side of the gate cut region, the TS layer and first and second contacts cross coupling the first and second gate structures.

Aspects of the present disclosure include forming the TS layer over at least one STI region. Other aspects include forming the TS layer to approximately the same height as the height of the first and second gate structures. Further aspects include forming the TS layer of tungsten (W). Additional aspects include comprising forming connected pMOS and nMOS gate transistors with the first and second active fins, respectively, and the cross-coupled first and second gate structures. Another aspect includes comprising forming the first and second contacts by: forming first and second capping layers on the first and second gate structures; forming first and second recesses on opposite sides of the gate cut region in the TS layer and the first and second capping layers, respectively, down to the first and second parallel gate structures; and forming the first and second contacts in the first and second recesses. Other aspects include comprising forming the first and second contacts as rectangles perpendicular to the first and second gate structures, at an angle to the first and second gate structures, or in an “L” shape.

Another aspect of the present disclosure is a device including: first and second active fins formed on a substrate; a space formed between the first and second active fins first and second gate structures formed in parallel across the first and second active fins; a gate cut region formed in the space perpendicular to the first and second gate structures; a TS layer formed of W, in the space, and between the first and second gate structures, the TS layer crossing the gate cut region; and a first contact formed across the first gate structure and the TS layer on a first side of the gate cut region and a second contact formed across the second gate structure and the TS layer on a second side of the gate cut region, the TS layer and the first and second contacts cross coupling the first and second gate structures.

Aspects of the device include the TS layer being formed over at least one STI region formed between and next to the first and second active fins. Other aspects include the TS layer being formed to approximately the same height as the first and second gate structures. Further aspects include connected pMOS and nMOS gate transistors being formed by the first and second active fins and the cross-coupled first and second gate structures. Additional aspects include the first and second contacts being formed as rectangles perpendicular to the first and second gate structures, at angles to the first and second gate structures, or in an “L” shape. Another aspect includes the first and second gate structures being formed with a first and second capping layer, respectively. Other aspects include the first and second contacts being formed in the first and second capping layers, down to the first and second gate structures, respectively.

A further aspect of the present disclosure is a method including: forming first and second active fins and first and second dummy fins on a substrate, the first and second dummy fins adjacent to each other and between the first and second active fins; forming STI regions between and next to the first and second active fins and the first and second dummy fins; forming first and second gate structures in parallel across the first and second active fins and the first and second dummy fins; forming first and second capping layers on the first and second self-aligned gate structures, respectively; forming a gate cut region by cutting both the first and second self-aligned gate structures and the first and second capping layers between the first and second dummy fins; forming a TS layer of W between the first and second gate structures, the TS layer crossing the gate cut region; and forming a first self-aligned contact connecting the first gate structure and the TS layer on a first side of the gate cut region and forming a second self-aligned contact connected the second gate structure and the TS layer on a second side of the gate cut region, the TS and the first and second self-aligned contacts cross coupling the first and second gate structures.

Aspects of the present disclosure include forming the TS layer over at least one STI region. Other aspects include forming the TS layer to approximately the same height as the height of the first and second self-aligned gate structures. Further aspects include forming connected pMOS and nMOS gate transistors with the first and second plurality of active fins, respectively, and the cross-coupled first and second self-aligned gate structures. Additional aspects include the first and second self-aligned contacts in the first and second capping layers, down to the first and second gate structures, respectively. Another aspect includes forming the first and second self-aligned contacts as rectangles perpendicular to the first and second gate structures, at angles to the first and second gate structures, or in an “L” shape.

DETAILED DESCRIPTION

The present disclosure addresses and solves the current problem of design congestion and integration complexity attendant upon using an S/D contact in a logic cell for a gate cross-couple construct.

Methodology in accordance with embodiments of the present disclosure includes first and second active fins and first and second dummy fins being formed on a substrate, the first and second dummy fins adjacent to each other and between the first and second active fins. STI regions are formed between and next to the first and second active fins and the first and second dummy fins. First and second gate structures are formed in parallel across the first and second active fins and the first and second dummy fins. A gate cut region is formed by cutting the first and second gate structures between the first and second dummy fin. A TS layer is formed between the first and second gate structures, the TS layer crossing the gate cut region. A first contact connecting the first gate structure and the TS layer is formed on a first side of the gate cut region and a second contact connecting the second gate structure and the TS layer is formed on a second side of the gate cut region, the first and second gate structures being cross-coupled by the TS layer and first and second contacts.

Adverting toFIGS. 2A and 2B(FIG. 2Ais a top view andFIG. 2Bis a generalized cross-sectional view), active fins201aand201band dummy fins203aand203bmay be formed, for example, on or of a silicon substrate (not shown for illustrative convenience). Next, STI regions205may be formed, e.g., between and next to the active fins201aand201band dummy fins203aand203b. Gate structures207, e.g.,207athrough207e, may then be formed, for example, across the active fins201aand201b, the dummy fins203aand203b, and the STI regions205. Gate contacts209and S/D contacts211may then be formed, for example, on the gate structures207a-207eand fins201aand201b, respectively.

Next, gates207band207care cut, e.g., by double patterning, forming the gate cut region213. A TS layer215may then be formed, for example, between the gates207band207cand across the gate cut region213. The TS layer215may be formed, for example, of W. In addition, the TS layer215may be formed, for example, over at least one STI region205. Further, the TS layer215may also be formed, for example, to approximately the same height as gates207athrough207e, as depicted inFIG. 2B.

A contact217, e.g., contact217a, may be formed, for example, on the upper side of the gate cut region213connecting gate structure207cand the TS layer215. At or about the same time, a contact217, e.g., contact217b, may be formed, for example, on the lower side of the gate cut region213and thereby connecting gate structure207band the TS layer215. The contacts217aand217bmay be formed, for example, as a rectangular gate contact construct. In particular, if self-aligned contacts are used, the contacts217aand217bmay be formed, for example, by first forming a capping layer (not shown for illustrative convenience) on each of the gate structures207athrough207e. A recess may then be formed, for example, on opposite sides of the gate cut region213in the TS layer215and the capping layers of gate structures207band207c. Thereafter, the contacts217aand217bmay be formed, for example, in the respective recesses. In addition, the contacts217aand217beach may be formed, for example, as a rectangle perpendicular to the gate structures207band207c, at an angle to gate structures207band207c, or in an “L” shape. Consequently, the TS layer215and the contacts217aand217bcross couple the top portion of gate structure207cand the lower portion of gate structure207band, therefore, also connect the pMOS gate transistor formed over active fins201aand the nMOS gate transistor formed over active fins201b. Because the TS layer is defined as a lower level, routing congestion may be relieved for upper layers above the TS layer. In other words, by using TS layer215to enable cross couple, design flexibility can be achieved by pushing the cross coupling to a lower level than any MOL layers and, therefore, space congestion can be reduced.

Adverting toFIG. 2B, gate structures207are formed on a substrate221having silicide portions223. Next, a TS layer215may be formed, for example, between the gate structures207. The TS layer215may be formed, for example, to approximately the same height as the gate structures207. Gate contacts209are then formed on the gate structures207and contacts217, e.g., rectangular gate contact constructs, are formed on the TS layer215. A metal layer225is then formed on top of the gate contacts209and contacts217, respectively.

The embodiments of the present disclosure can achieve several technical effects including cross-coupling gates structures while mitigating design congestion. Embodiments of the present disclosure enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in any of various types of semiconductor devices including logic cells, particularly in 7 nm technologies nodes and beyond.