Display device

A display device comprises a first pattern disposed on a substrate and receiving a driving voltage, a second pattern disposed on the first pattern and receiving the driving voltage, an intermediate pattern disposed on the first pattern and receiving the driving voltage, a first source pattern disposed on the intermediate pattern and contacting the first pattern, the second pattern, and the intermediate pattern, a second source pattern disposed in the same layer as the first source pattern and contacting the intermediate pattern, and a third source pattern disposed on the second source pattern and contacting the second source pattern.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority from and the benefit of Korean Patent Application No. 10-2020-0135464, filed on Oct. 19, 2020, which is hereby incorporated by reference for all purposes as if fully set forth herein.

BACKGROUND

Field

The present disclosure generally relates to a display device. More particularly, relates to a display device including a structure of a pixel circuit part capable of securing a degree of freedom in designing the conductive patterns.

Discussion of the Background

The display device includes a plurality of pixels, and each of the pixels includes a pixel circuit part and a display element electrically connected to the pixel circuit part. The pixel circuit part has a structure in which a plurality of conductive patterns are vertically stacked, and the conductive patterns are connected to each other through contact holes. In recent years, in order to improve the display quality of the display device, the conductive patterns included in the pixel circuit part have been densely formed. Accordingly, it is impossible to freely design the shapes of the conductive patterns. Therefore, a structure of a pixel circuit part capable of securing a degree of freedom in designing the conductive patterns should be developed.

The above information disclosed in this Background section is only for understanding of the background of the present disclosure, and, therefore, it may contain information that does not constitute prior art.

SUMMARY

Some example embodiments provide a display device.

A display device according to an embodiment may include a first pattern disposed on a substrate and configured to receive a driving voltage, a second pattern disposed on the first pattern and configured to receive the driving voltage, an intermediate pattern disposed on the first pattern and configured to receive the driving voltage, a first source pattern disposed on the intermediate pattern and in direct contact with the first pattern, the second pattern, and the intermediate pattern, a second source pattern disposed in a same layer as the first source pattern and in direct contact with the intermediate pattern, and a third source pattern disposed on the second source pattern and in direct contact with the second source pattern.

According to an embodiment, the display device may further include an insulating layer disposed between the second source pattern and the third source pattern and formed of an organic insulating material.

According to an embodiment, each of the first source pattern and the second source pattern may be arranged in an island shape.

According to an embodiment, the intermediate pattern may be arranged in an island shape.

According to an embodiment, the display device may further include a second active pattern disposed on the second pattern and including an oxide semiconductor, the first pattern may be a first active pattern including a silicon semiconductor, and the intermediate pattern may be disposed between the second active pattern and the first source pattern.

According to an embodiment, the third source pattern may contact the second source pattern through a first contact hole, the second source pattern may contact the intermediate pattern through a second contact hole, the first source pattern may contact the intermediate pattern through a third contact hole, contacts the second pattern through a fourth contact hole, and contacts the first pattern through a fifth contact hole, and the third, fourth, and fifth contact holes may be spaced apart from each other.

According to an embodiment, each of plane areas of the second, third, fourth and fifth contact holes may be smaller than a plane area of the first contact hole.

According to an embodiment, the display device may further include a gate electrode disposed between the first pattern and the second pattern and arranged in an island shape and a node pattern disposed in a same layer as the second source pattern and in direct contact with the gate electrode and the second active pattern. The intermediate pattern may be disposed to surround at least a portion of the node pattern on a plane.

According to an embodiment, the display device may further include a first gate line disposed between the first pattern and the intermediate pattern and a second active pattern disposed on the intermediate pattern and including an oxide semiconductor. The first pattern may be a first active pattern including a silicon semiconductor, and the second pattern may be disposed on the second active pattern.

According to an embodiment, the third source pattern may contact the second source pattern through a first contact hole, the second source pattern may contact the intermediate pattern through a second contact hole, the first source pattern may contact the second pattern through a third contact hole, may contact the intermediate pattern through a fourth contact hole, and may contact the first pattern through a fifth contact hole, and the third, fourth, and fifth contact holes may be spaced apart from each other.

According to an embodiment, each of plane areas of the second, third, fourth, and fifth contact holes may be smaller than a plane area of the first contact hole.

According to an embodiment, the display device may further include a gate electrode disposed in a same layer as the first gate line and arranged in an island shape and a node pattern disposed in a same layer as the second source pattern and in direct contact with the gate electrode and the second active pattern. The second pattern may be disposed to be adjacent to the node pattern.

According to an embodiment, the display device may further include a first gate line disposed between the first pattern and the intermediate pattern and a second active pattern disposed on the intermediate pattern and including an oxide semiconductor. The first pattern may be a first active pattern including a silicon semiconductor, and the second pattern may be disposed in a same layer as the second active pattern.

According to an embodiment, the third source pattern may contact the second source pattern through a first contact hole, the second source pattern may contact the intermediate pattern through a second contact hole, the first source pattern may contact the second pattern through a third contact hole, may contact the intermediate pattern through a fourth contact hole, and may contact the first pattern through a fifth contact hole, and the third, fourth, and fifth contact holes may be spaced apart from each other.

According to an embodiment, the display device may further include a gate electrode disposed in a same layer as the first gate line and arranged in an island shape and a node pattern disposed in a same layer as the second source pattern and contacting the gate electrode and the second active pattern. The second pattern may be disposed to be adjacent to the node pattern.

According to an embodiment, the display device may further include a first gate line disposed between the first pattern and the second pattern and a second active pattern disposed on the second pattern and including an oxide semiconductor. The first pattern may be a first active pattern including a silicon semiconductor, and the intermediate pattern may be disposed in a same layer as the second active pattern.

According to an embodiment, the third source pattern may contact the second source pattern through a first contact hole, the second source pattern may contact the intermediate pattern through a second contact hole, the first source pattern may contact the intermediate pattern through a third contact hole, may contact the second pattern through a fourth contact hole, and may contact the first pattern through a fifth contact hole, and the third, fourth, and fifth contact holes may be spaced apart from each other.

According to an embodiment, the driving voltage may be transferred in an order of the third source pattern, the second source pattern, the intermediate pattern, and the first source pattern, and the first source pattern may transfer the driving voltage to the first pattern and the second pattern.

A display device according to another embodiment may include an active pattern disposed on a substrate and configured to receive a driving voltage, a storage capacitor electrode disposed on the active pattern and configured to receive the driving voltage, a first source pattern disposed on the storage capacitor pattern and in direct contact with the active pattern and the storage capacitor pattern, a second source pattern disposed in a same layer as the first source pattern and in direct contact with the storage capacitor pattern, and a third source pattern disposed on the second source pattern and in direct contact with the second source pattern.

According to an embodiment, the driving voltage may be transferred in an order of the third source pattern, the second source pattern, the storage capacitor electrode, and the first source pattern, and the first source pattern transfers the driving voltage to the active pattern.

Therefore, the display device may include the first source pattern, the second source pattern, and the intermediate pattern that transfer the driving voltage. Accordingly, additional contact holes for electrically connecting the third source pattern to the first pattern and the second pattern may not be added in the via insulating layer. In other words, the driving voltage may be transferred to the first pattern and the second pattern through one contact hole connecting the third source pattern and the second source pattern. Accordingly, the number of contact holes may be relatively small, and the shape of the third source pattern may be designed relatively freely.

It is to be understood that both the foregoing general description and the following detailed description provide examples, are explanatory, and are intended to provide further explanation of the present disclosure as claimed.

DETAILED DESCRIPTION

When an element, such as a layer, is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it may be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present. When, however, an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present. To this end, the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements. Further, the D1-axis, the D2-axis, and the D3-axis are not limited to three axes of a rectangular coordinate system, such as the x, y, and z-axes, and may be interpreted in a broader sense. For example, the D1-axis, the D2-axis, and the D3-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another.

Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

FIG. 1is a block diagram illustrating a display device according to embodiments.FIG. 2is an equivalent circuit diagram illustrating of a first pixel included in the display device ofFIG. 1.

Referring toFIGS. 1 and 2, a display device10according to embodiments of the present disclosure may include a display panel PNL, a data driver DDV, a gate driver GDV, a emission driver EDV, and a controller CON.

As depicted inFIG. 1, the display panel PNL may include a plurality of pixels. For example, the display panel PNL may include a first pixel PX1and a second pixel PX2. Each of the first and second pixels PX1and PX2may receive a data voltage DATA, a gate signal GS, an emission control signal EM, a driving voltage ELVDD, a common voltage ELVSS, a gate initialization voltage VINT, and an anode initialization voltage AINT.

The data driver DDV may generate the data voltage DATA based on an output image data ODAT and a data control signal DCTRL. For example, the data driver DDV may generate the data voltage DATA corresponding to the output image data ODAT, and may output the data voltage DATA in response to the data control signal DCTRL. The data control signal DCTRL may include an output data enable signal, a horizontal start signal, and a load signal.

The gate driver GDV may generate the gate signal GS based on a gate control signal GCTRL. For example, the gate signal GS may include a gate-on voltage for turning on a transistor and a gate-off voltage for turning off the transistor. The gate control signal GCTRL may include a vertical start signal, a clock signal, and the like.

The emission driver EDV may generate the emission control signal EM based on an emission driving signal ECTRL. For example, the emission driving signal ECTRL may include a vertical start signal and a clock signal, and the emission control signal EM may include a gate-on voltage for turning on a transistor and a gate-off voltage for turning off the transistor.

The controller CON (e.g., timing controller T-CON) may receive an input image data IDAT and a control signal CTRL from an external host processor (e.g., GPU). For example, the input image data IDAT may be RGB data including red image data, green image data, and blue image data. The control signal CTRL may include a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, and the like. The controller CON may generate the gate control signal GCTRL, the emission driving signal ECTRL, the data control signal DCTRL, and the output image data ODAT, based on the input image data IDAT and the control signal CTRL.

As depicted inFIG. 2, the first pixel PX1may include a first pixel circuit PC1and a first organic light emitting diode OLED1. The first pixel circuit PC1may provide a driving current to the first organic light emitting diode OLED1, and the first organic light emitting diode OLED1may generate light based on the driving current. A second pixel circuit of the second pixel PX2may have the substantially equal structure to the first pixel circuit PC1.

The first pixel circuit PC1may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, a seventh transistor T7, a storage capacitor CST, and a boosting capacitor CBS.

The first organic light emitting diode OLED1may include a first terminal (e.g., an anode terminal) and a second terminal (e.g., a cathode terminal), the first terminal of the first organic light emitting diode OLED1may be connected to the sixth transistor T6and the seventh transistor T7, and the second terminal may receive the common voltage ELVSS. The first organic light emitting diode OLED1may generate light having a luminance corresponding to the driving current.

The storage capacitor CST may include a first terminal and a second terminal. The first terminal of the storage capacitor CST may be connected to the first transistor T1, and the second terminal of the storage capacitor CST may receive the driving voltage ELVDD. The storage capacitor CST may maintain the voltage level of a gate terminal of the first transistor T1during an inactive period of the first gate signal GW.

The boosting capacitor CBS may include a first terminal and a second terminal. The first terminal of the boosting capacitor CBS may be connected to the gate terminal of the first transistor T1, and the second terminal of the boosting capacitor CBS may receive a first gate signal GW. The boosting capacitor CBS may compensate for the voltage drop of the gate terminal of the first transistor T1by increasing the voltage of the gate terminal when the provision of the first gate signal GW is stopped.

The first transistor T1may include the gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the first transistor T1may be connected to the first terminal of the storage capacitor CST. The first terminal of the first transistor T1may be connected to the second transistor T2and may receive the data voltage DATA. The second terminal of the first transistor T1may be connected to the sixth transistor T6. The first transistor T1may generate the driving current based on a voltage difference between the gate terminal and the first terminal. For example, the first transistor T1may be referred to as a driving transistor.

The second transistor T2may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the second transistor T2may receive the first gate signal GW through the gate line GL.

The second transistor T2may be turned on or off in response to the first gate signal GW. For example, when the second transistor T2is a PMOS transistor, the second transistor T2may be turned off when the first gate signal GW has a positive voltage level, and may be turned on when the first gate signal GW has a negative voltage level. The first terminal of the second transistor T2may receive the data voltage DATA through a data line DL. The second terminal of the second transistor T2may provide the data voltage DATA to the first terminal of the first transistor T1while the second transistor T2is turned on. For example, the second transistor T2may be referred to as a switching transistor.

The third transistor T3may include a gate terminal, a lower gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal and the lower gate terminal of the third transistor T3may receive a second gate signal GC. The first terminal of the third transistor T3may be connected to the second terminal of the first transistor T1. The second terminal of the third transistor T3may be connected to the gate terminal of the first transistor T1.

The third transistor T3may be turned on or off in response to the second gate signal GC. For example, when the third transistor T3is an NMOS transistor, the third transistor T3may be turned on when the second gate signal GC has a positive voltage level, and may be turned off when the second gate signal GC has a negative voltage level.

During a period in which the third transistor T3is turned on in response to the second gate signal GC, the third transistor T3may diode-connect the first transistor T1. Accordingly, the third transistor T3may compensate for the threshold voltage of the first transistor T1. For example, the third transistor T3may be referred to as a compensation transistor.

The fourth transistor T4may include a gate terminal, a lower gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal and the lower gate terminal of the fourth transistor T4may receive a third gate signal GI. The first terminal of the fourth transistor T4may be connected to the gate terminal of the first transistor T1. The second terminal of the fourth transistor T4may receive the gate initialization voltage VINT.

The fourth transistor T4may be turned on or off in response to the third gate signal GI. For example, when the fourth transistor T4is an NMOS transistor, the fourth transistor T4may be turned on when the third gate signal GI has a positive voltage level, and may be turned off when the third gate signal GI has a negative voltage level.

While the fourth transistor T4is turned on to the third gate signal GI, the gate initialization voltage VINT may be provided to the gate terminal of the first transistor T1. Accordingly, the fourth transistor T4may initialize the gate terminal of the first transistor T1to the gate initialization voltage VINT. For example, the fourth transistor T4may be referred to as a gate initialization transistor.

The fifth transistor T5may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the fifth transistor T5may receive the emission control signal EM. The first terminal of the fifth transistor T5may receive the driving voltage ELVDD. The second terminal of the fifth transistor T5may be connected to the first transistor T1. When the fifth transistor T5is turned on in response to the emission control signal EM, the fifth transistor T5may provide the driving voltage ELVDD to the first transistor T1.

The sixth transistor T6may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the sixth transistor T6may receive the emission control signal EM. The first terminal of the sixth transistor T6may be connected to the first transistor T1. The second terminal of the sixth transistor T6may be connected to the first organic light emitting diode OLED1. When the sixth transistor T6is turned on in response to the emission control signal EM, the sixth transistor T6may provide the driving current to the first organic light emitting diode OLED1.

The seventh transistor T7may include a gate terminal, a first terminal (e.g., a source terminal), and a second terminal (e.g., a drain terminal). The gate terminal of the seventh transistor T7may receive a fourth gate signal GB. The first terminal of the seventh transistor T7may be connected to the first organic light emitting diode OLED1. The second terminal of the seventh transistor T7may receive the anode initialization voltage AINT.

When the seventh transistor T7is turned on in response to the fourth gate signal GB, the seventh transistor T7may provide the anode initialization voltage AINT to the first organic light emitting diode OLED1. Accordingly, the seventh transistor T7may initialize the first terminal of the first organic light emitting diode OLED1to the anode initialization voltage AINT. For example, the seventh transistor T7may be referred to as an anode initialization transistor.

In an embodiment, the first, second, fifth, sixth, and seventh transistors T1, T2, T5, T6, T7may be PMOS transistors, and the third and fourth transistors T3and T4may be NMOS transistors. Accordingly, a first active pattern of the PMOS transistors may include a silicon semiconductor doped with positive ions, and a second active pattern of the NMOS transistors may include an oxide semiconductor. In addition, the first gate signal GW, the emission control signal EM, and the fourth gate signal GB for respectively turning on the second, fifth, sixth, and seventh transistors T2, T5, T6, and T7may have a negative voltage level and the second gate signal GC and the third gate signal GI for respectively turning on the third and fifth transistors T3and T4may have a positive voltage level.

The circuit structure of the first pixel circuit PC1illustrated inFIG. 2is an example and may be variously changed.

FIG. 3is a plan view illustrating the display device ofFIG. 1.FIG. 4is a perspective view illustrating the display device ofFIG. 1.FIG. 5is a cross-sectional view illustrating the display device ofFIG. 1.FIG. 6is an enlarged view of an enlarged area A ofFIG. 3.

Referring toFIG. 3, the display device10may include a display area DA, a non-display area NDA surrounding the display area DA, a bending area BA configured to be bended, a peripheral area SA between the display area DA and the bending area BA, and pad area PA.

For example, the plurality of pixels may be disposed in the display area DA, and a driver for driving the pixels may be disposed in the non-display area NDA. A driving voltage part ELVDDV and the data driver DDV may be disposed in the pad area PA, and the bending area BA may be bent based on a virtual bending axis. The driving voltage part ELVDDV may provide the driving voltage ELVDD to a driving voltage line PL of the display device10.

Referring toFIGS. 4 and 5, a first pixel circuit part PCP1and a first display element ED1may constitute the first pixel PX1. For example, the first pixel circuit part PCP1may correspond to the first pixel circuit PC1, and the first display element ED 1 may correspond to the first organic light emitting diode OLED1. In other words, the transistors may be formed in the first pixel circuit part PCP1, and the first pixel circuit part PCP1may provide the driving current to the first display element ED 1. In addition, the second pixel circuit part PCP2and the second display element ED2may constitute the second pixel PX2.

The first display element ED1may include a first pixel electrode ADE1, a first emission layer ELL and a common electrode CTE. For example, the first emission layer EL1may generate red light. The second display element ED2may include a second pixel electrode ADE2, a second emission layer EL2, and the common electrode CTE. For example, the second emission layer EL2may generate green light.

The first pixel circuit part PCP1may include a substrate SUB, a first active pattern1100, a first conductive pattern1200, a second conductive pattern1300, a second active pattern1400, a third conductive pattern1500, a fourth conductive pattern1600, and a fifth conductive pattern1700. Insulation layers may be disposed between the first active pattern1100to the fifth conductive pattern1700. For example, an insulation layer may be disposed between the first active pattern1100and the first conductive pattern1200. Another insulation layer may be disposed between the first conductive pattern1200and the second conductive pattern1300. Another insulation layer may be disposed between the second conductive pattern1300and the second active pattern1400. Another insulation layer may be disposed between the second active pattern1400and the third conductive pattern1500. Another insulation layer may be disposed between the third conductive pattern1500and the fourth conductive pattern1600. Another insulation layer may be disposed between the fourth conductive pattern1600and the fifth conductive pattern1700. In addition, a second via insulating layer VIA2may be disposed on the fifth conductive pattern1700, and the first and second pixel electrodes ADE1and ADE2may contact the fifth conductive pattern1700through contact holes passing through the second via insulating layer VIA2.

Referring toFIGS. 3, 4, 5, and 6, the data line DL may be electrically connected to the data driver DDV and may extend along a second direction D2. The gate line GL may be connected to the gate driver GDV and may extend along a first direction D1crossing the second direction D2. The driving voltage line PL may be connected to the driving voltage part ELVDDV and may extend along the second direction D2.

Data transfer lines FL1and FL2may be electrically connected to the data driver DDV and the data line DL. The data transfer lines FL1and FL2may be connected to the data driver DDV and the data line DL respectively.

In an embodiment, as shown inFIG. 6, first to fourth data lines DL1, DL2, DL3, and DL4, a first data transfer line FL1, and a second data line FL2may be disposed in the display device10. For example, the first and second data transfer lines FL1and FL2may be fan-out lines electrically connected to the data driver DDV and the data line DL respectively.

In an embodiment, the first data transfer line FL1may include a first vertical line VFL1and a first horizontal line HFL1, and the second data transfer line FL2may include a second vertical line VFL2and a second horizontal line HFL2. For example, the first and second vertical lines VFL1and VFL2may extend in the second direction D2, and the first and second horizontal lines HFL1and HFL2may extend in the first direction D1.

One end of the first data transfer line FL1may be electrically connected to the data driver DDV, and the other end of the first data transfer line FL1may be connected to the first data line DL1. For example, a first data voltage may be provided to the first pixel PX1through the first data transfer line FL1and the first data line DL1.

In detail, the first vertical line VFL1may be connected to a first connection line SCL1, the first connection line SCL1may be connected to a first bending connection line BCL1, and the first bending connection line BCL1may be connected to a first data connection line DCL1.

For example, the first vertical line VFL1may extend from the peripheral area SA to the display area DA, and may be formed in the same layer as the fifth conductive pattern1700. The first connection line SCL1may be disposed in the peripheral area SA, and may be formed under the first vertical line VFL1. The first bending connection line BCL1may be disposed in the bending area BA and may be formed in the same layer as the first vertical line VFL1. The first data connection line DCL1may be disposed in the pad area PA and may receive the first data voltage from the data driver DDV.

The second data transfer line FL2may electrically connect the data driver DDV and the second data line DL2. For example, the second data voltage may be provided to the second pixel PX2through the second data transfer line FL2and the second data line DL2.

In detail, the second vertical line VFL2may be connected to a second connection line SCL2, the second connection line SCL2may be connected to a second bending connection line BCL2, and the second bending connection line BCL2may be connected to a second data connection line DCL2. However, the structure of the second vertical line VFL2, the second connection line SCL2, the second bending connection line BCL2, and the second data connection line DCL2may be substantially equal to the first data transfer vertical line VFL1, the first connection line SCL1, the first bending connection line BCL1, and the first data connection line DCL1, and thus detailed description thereof will be omitted.

The third data line DL3may be connected to the data driver DDV. For example, the third data voltage may be provided to the third pixel through the third data line DL3.

In detail, the third data line DL3may be connected to a third connection line SCL3, the third connection line SCL3may be connected to a third bending connection line BCL3, the third bending connection line BCL3may be connected to a third data connection line DCL3, and finally the third data connection line DCL3may be connected to the data driver DDV.

For example, the third data line DL3may extend from the peripheral area SA to the display area DA, and may be formed in the same layer as the first vertical line VFL1. The third connection line SCL3may be disposed in the peripheral area SA and may be formed under the third data line DL3. The third bending connection line BCL3may be disposed in the bending area BA and may be formed in the same layer as the first vertical line VFL1. The third data connection line DCL3may be disposed in the pad area PA and may receive the third data voltage from the data driver DDV.

The fourth data line DL4may be connected to the data driver DDV. For example, the fourth data voltage may be provided to the fourth pixel through the fourth data line DL4.

In detail, the fourth data line DL4may be connected to a fourth connection line SCL4, the fourth connection line SCL4may be connected to a fourth bending connection line BCL4, the fourth bending connection line BCL4may be connected to a fourth data connection line DCL4, and fourth data connection line DCL4may be connected to the data driver DDV. However, the structure of the fourth data line DL4, the fourth connection line SCL4, the fourth bending connection line BCL4, and the fourth data connection line DCL4may be substantially the same as the third data transfer vertical line VFL3, the third connection line SCL3, the third bending connection line BCL3, and the third data connection line DCL3, and thus detailed description thereof will be omitted.

Referring toFIGS. 7 and 14, a display device11according to an embodiment may include the first and second pixel circuit parts PCP1and PCP2arranged in the first direction D1. In an embodiment, the second pixel circuit part PCP2may have a shape symmetrical to a shape of the first pixel circuit part PCP1. Hereinafter, the structure of the first pixel circuit part PCP1will be described in detail.

A substrate SUB may include glass, quartz, plastic, or the like. In an embodiment, the substrate SUB may include plastic, and the display device11may have a flexible characteristic. In this case, the substrate SUB may have a structure in which at least one organic film layer and at least one barrier layer are alternately stacked. For example, the organic film layer may be formed using an organic material such as polyimide, and the barrier layer may be formed using an inorganic material.

A buffer layer BFR may be disposed on the substrate SUB. The buffer layer BFR may prevent diffusion of metal atoms or impurities from the substrate SUB into the first active pattern1100. In addition, the buffer layer BFR may control a rate of providing heat during a crystallization process for forming the first active pattern1100.

The first active pattern1100may be disposed on the buffer layer BFR. In an embodiment, the first active pattern1100may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, or the like. For example, the first active pattern1100may include the polycrystalline silicon formed by crystallizing the amorphous silicon.

In an embodiment, the first active pattern1100may be a first pattern receiving the driving voltage ELVDD. In other words, the driving voltage ELVDD may be provided in the first pattern.

A first gate insulating layer GI1may cover the first active pattern1100and may be disposed on the substrate SUB. The first gate insulating layer GI1may include an inorganic insulating material. For example, the first gate insulating layer GI1may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

Referring toFIGS. 8 and 14, the first conductive pattern1200may be disposed on the first gate insulating layer GI1. The first conductive pattern1200may include a second gate wiring1210, a gate electrode1220, and a first gate wiring1230.

The second gate line1210may extend in the first direction D1. The second gate line1210may form the second transistor T2together with the first active pattern1100. For example, the first gate signal GW may be provided to the second gate line1210. In addition, the second gate line1210may constitute the seventh transistor T7together with the first active pattern1100. For example, the fourth gate signal GB may be provided to the second gate line1210. The first gate signal GW and the fourth gate signal GB may have substantially equal waveform with a time difference.

The gate electrode1220may be arranged in an island shape. The gate electrode1220may form the first transistor T1together with the first active pattern1100.

The first gate line1230may extend in the first direction D1. The first gate line1230may constitute the fifth and sixth transistors T5and T6together with the first active pattern1100. For example, the emission control signal EM may be provided to the first gate line1230. The first gate line1230may be referred to as an emission control line.

For example, the first conductive pattern1200may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, and the like. For example, the first conductive pattern1200may include silver (“Ag”), an alloy containing silver, molybdenum (“Mo”), an alloy containing molybdenum, aluminum (“Al”), an alloy containing aluminum, aluminum nitride (“AlN”), tungsten (“W”), tungsten nitride (“WN”), copper (“Cu”), nickel (“Ni”), chromium (“Cr”), chromium nitride (“CrN”), titanium (“T1”), tantalum (“Ta”), platinum (“Pt”), scandium (“Sc”), indium tin oxide (“ITO”), indium zinc oxide (“IZO”), and the like.

A second gate insulating layer GI2may cover the first conductive pattern1200and may be disposed on the first gate insulating layer GI1. The second gate insulating layer GI2may include an inorganic insulating material.

Referring toFIGS. 9 and 14, the second conductive pattern1300may be disposed on the second gate insulating layer GI2. The second conductive pattern1300may include a gate initialization voltage line1310, a third gate line1320, a fourth gate line1330, and a storage capacitor electrode1340.

The gate initialization voltage line1310may extend in the first direction D1. For example, the gate initialization voltage line1310may be spaced apart from the second gate line1210on a plane. The gate initialization voltage VINT may be provided to the gate initialization voltage line1310.

The third gate line1320may extend in the first direction D1. For example, the third gate line1320may be spaced apart from the second gate line1210on a plane. The third gate signal GI may be provided to the third gate line1320.

The fourth gate line1330may extend in the first direction D1. For example, the fourth gate line1330may be spaced apart from the second gate line1210and the third gate line1320on a plane. The second gate signal GC may be provided to the fourth gate line1330.

The storage capacitor electrode1340may overlap the first gate electrode1220and may extend in the first direction D1. For example, the storage capacitor electrode1340may form the storage capacitor CST together with the first gate electrode1220. In addition, a hole penetrating through the storage capacitor electrode1340may be formed in the storage capacitor electrode1340, and the first gate electrode1220may be exposed through the hole.

In an embodiment, the storage capacitor electrode1340may be a second pattern receiving the driving voltage ELVDD. In other words, the driving voltage ELVDD may be provided in the second pattern. For example, the second pattern may include a first exposed portion1341exposed by a fourth contact hole CNT4. The first exposed portion1341may overlap the first gate line1230. The second pattern may contact a first source pattern1670in the first exposed portion1341.

For example, the second conductive pattern1300may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, and the like.

A first interlayer insulating layer ILD1may cover the second conductive pattern1300and may be disposed on the second gate insulating layer GI2. The first interlayer insulating layer ILD1may include an inorganic insulating material. For example, the first interlayer insulating layer ILD1may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

Referring toFIGS. 10 and 14, the second active pattern1400may be disposed on the first interlayer insulating layer ILD1. For example, the second active pattern1400may overlap the third gate line1320and the fourth gate line1330.

The second active pattern1400may include an oxide semiconductor. In an embodiment, the second active pattern1400may be disposed on a different layer from the first active pattern1100and may not overlap the first active pattern1100. In other words, the second active pattern1400may be formed separately from the first active pattern1100.

A third gate insulating layer GI3may cover the second active pattern1400and may be disposed on the first interlayer insulating layer ILD1. The third gate insulating layer GI3may include an inorganic insulating material.

Referring toFIGS. 11 and 14, the third conductive pattern1500may be disposed on the third gate insulating layer GI3. The third conductive pattern1500may include a fifth gate line1510, a sixth gate line1520, and an intermediate pattern1530.

The fifth gate line1510may extend in the first direction D1. For example, the fifth gate line1510may overlap the third gate line1320and the second active pattern1400. The fifth gate line1510may constitute the fourth transistor T4together with the third gate line1320and the second active pattern1400. For example, the third gate signal GI may be provided to the fifth gate line1510.

The sixth gate line1520may extend in the first direction D1. For example, the sixth gate line1520may overlap the fourth gate line1330and the second active pattern1400. The sixth gate line1520may constitute the third transistor T3together with the fourth gate line1330and the second active pattern1400. For example, the second gate signal GC may be provided to the sixth gate line1520.

In an embodiment, the intermediate pattern1530may be arranged in an island shape and may be provided with the driving voltage ELVDD. In other words, the driving voltage EVLDD may be provided to the intermediate pattern1530. For example, the intermediate pattern1530may include a second exposed portion1531exposed through the third contact hole CNT3. The second exposed portion1531may be adjacent to the first exposed portion1341of the second pattern, and may be spaced apart from the first exposed portion1341on a plane. The intermediate pattern1530may contact the first source pattern1670in the second exposed portion1531.

For example, the third conductive pattern1500may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, and the like.

A second interlayer insulating layer ILD2may cover the third conductive pattern1500and may be disposed on the third gate insulating layer GI3. The second interlayer insulating layer ILD2may include an inorganic insulating material.

Referring toFIGS. 12 and 14, the fourth conductive pattern1600may be disposed on the second interlayer insulating layer ILD2. The fourth conductive pattern1600may include a first transfer pattern1610, a second transfer pattern1620, an anode initialization voltage line1630, a node pattern1640, a third transfer pattern1650, a first horizontal line1660, a first source pattern1670, a fourth transfer pattern1680, and a second source pattern1690.

The first transfer pattern1610may be arranged in an island shape. The first transfer pattern1610may contact the gate initialization voltage line1310and the second active pattern1400, and may transfer the gate initialization voltage VINT to the second active pattern1400.

The second transfer pattern1620may be arranged in an island shape. The second transfer pattern1620may contact the first active pattern1100and may transfer the data voltage DATA to the first active pattern1100.

The anode initialization voltage line1630may extend in the first direction D1. The anode initialization voltage line1630may contact the first active pattern1100. The anode initialization voltage AINT may be provided to the first active pattern1100through the anode initialization voltage line1630.

The node pattern1640may be arranged in an island shape. The node pattern1640may contact the gate electrode1220and the second active pattern1400. For example, the node pattern1640may electrically connect the gate terminal of the first transistor T1and the drain terminal of the third transistor T3.

In addition, in an embodiment, the intermediate pattern1530may be disposed to surround at least a portion of the node pattern1640on a plane.

The third transfer pattern1650may be arranged in an island shape. The third transfer pattern1650may contact the first active pattern1100and the second active pattern1400. For example, the third transfer pattern1650may electrically connect the drain terminal of the first transistor T1and the source terminal of the third transistor T3.

The first horizontal line1660may extend in the first direction D1. In an embodiment, the data voltage DATA may be transmitted through the first horizontal line1660. For example, the first horizontal line1660may correspond to any one of the first horizontal line HFL1and the second horizontal line HFL2described with reference toFIG. 6.

The first source pattern1670may be arranged in an island shape. For example, the first source pattern1670may receive the driving voltage ELVDD from the intermediate pattern1530, and may provide the driving voltage ELVDD to the first active pattern1100and the storage capacitor electrode1340.

In an embodiment, the first source pattern1670may contact the first active pattern1100, the storage capacitor electrode1340, and the intermediate pattern1530. For example, the first source pattern1670may contact the first active pattern1100through a fifth contact hole CNT5, may contact the storage capacitor electrode1340through the fourth contact hole CNT4, and may contact the intermediate pattern1530through the third contact hole CNT3. In an embodiment, the third, fourth, and fifth contact holes CNT3, CNT4, and CNT5may be spaced apart from each other.

The fourth transfer pattern1680may be arranged in an island shape. The fourth transfer pattern1680may contact the first active pattern1100. The fourth transfer pattern1680may receive the driving current and/or the anode initialization voltage AINT from the first active pattern1100.

The second source pattern1690may be arranged in an island shape. For example, the second source pattern1690may receive the driving voltage ELVDD from the third source pattern1730and the driving voltage ELVDD to the intermediate pattern1530.

In an embodiment, the second source pattern1690may contact the intermediate pattern1530and the third source pattern1730. For example, the second source pattern1690may contact the third source pattern1730through a first contact hole CNT1, and may contact the intermediate pattern1530through a second contact hole CNT2.

A first via insulating layer VIA1may cover the fourth conductive pattern1600and may be disposed on the second interlayer insulating layer ILD2. The first via insulating layer VIA1may include an organic insulating material. For example, the first via insulating layer VIA1may include a photoresist, a polyacrylic resin, a polyimide resin, an acrylic resin, or the like.

Referring toFIGS. 13 and 14, a fifth conductive pattern1700may be disposed on the first via insulating layer VIA1. The fifth conductive pattern1700may include a data line1710, a first vertical line1720, a third source pattern1730, and a fifth transfer pattern1740.

The data line1710may extend in the second direction D2. The data line1710may contact the first active pattern1100. In an embodiment, the data voltage DATA may be provided to the first active pattern1100through the data line1710. For example, the data line1710may correspond to any one of the first to fourth data lines DL1, DL2, DL3, and DL4described with reference toFIG. 6.

The first vertical line1720may extend in the second direction D2. In an embodiment, the data voltage DATA may be transmitted through the first vertical line1720. For example, the first vertical line1720may correspond to one of the first vertical line VFL1and the second vertical line VFL2described with reference toFIG. 6.

The third source pattern1730may extend in the second direction D2. In an embodiment, the driving voltage ELVDD may be transmitted through the third source pattern1730. For example, the third source pattern1730may correspond to the driving voltage line PL described with reference toFIG. 6.

In an embodiment, the third source pattern1730may contact the second source pattern1690through the first contact hole CNT1.

In an embodiment, the first contact hole CNT1may be formed through the first via insulating layer VIA1, the second contact hole CNT2and the third contact hole CNT3may be formed through the second interlayer insulation ILD2, the fourth contact hole CNT4may be formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, and the first interlayer insulating layer ILD1, and the fifth contact hole CNT5may be formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, the first interlayer insulating layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1. In other words, the first contact hole CNT1may pass through the layer made of an organic insulating material, and the second, third, fourth, and fifth contact holes CNT2, CNT3, CNT4, and CNT5may pass through the layers made of an inorganic insulating material. Accordingly, each of the plane areas of the second, third, fourth, and fifth contact holes CNT2, CNT3, CNT4, and CNT5may be smaller than the plane area of the first contact hole CNT1.

The fifth transfer pattern1740may be arranged in an island shape. The fifth transfer pattern1740may contact the fourth transfer pattern1680. The fifth transfer pattern1740may receive the driving current and/or the anode initialization voltage AINT from the fourth transfer pattern1680, and may transfer the driving current and/or the anode initialization voltage AINT to the first pixel electrode ADE1.

In an embodiment, as shown inFIG. 14, the third source pattern1730may contact the second source pattern1690through the first contact hole CNT1, the second source pattern1690may contact the intermediate pattern1530through the second contact hole CNT2, and the intermediate pattern1530may contact the first source pattern1670through the third contact hole CNT3. Accordingly, the driving voltage ELVDD may be transmitted to the third source pattern1730, the second source pattern1690, the intermediate pattern1530, and the first source pattern1670. In addition, the first source pattern1670may contact the storage capacitor electrode1340through the fourth contact hole CNT4and may contact the first active pattern1100through the fifth contact hole CNT5. Accordingly, the first source pattern1670may transfer the driving voltage ELVDD to the first active pattern1100and the storage capacitor electrode1340.

The display device11may include the first source pattern1670and the intermediate pattern1530that transfer the driving voltage ELVDD. Accordingly, additional contact holes for electrically connecting the third source pattern1730to the first active pattern1100and the storage capacitor electrode1340may not be added in the first via insulating layer VIA1. In other words, the driving voltage ELVDD may be transferred to the first active pattern1100and the storage capacitor electrode1340through the first contact hole CNT1formed in the first via insulating layer VIA1. Accordingly, the number of contact holes passing through the layer made of the organic insulating material may be relatively small. Therefore, the shape of the third source pattern1730may be designed relatively freely.

In addition, the intermediate pattern1530may be disposed to surround at least the portion of the node pattern1640on a plane, and the driving voltage ELVDD may be transmitted to the intermediate pattern1530. Accordingly, the intermediate pattern1530may shield the node pattern1640from the first horizontal line1660, the data line1710, and the first vertical line1720.

Referring toFIGS. 15 and 21, a display device12according to another embodiment may include the first and second pixel circuit parts PCP1and PCP2arranged in the first direction D1. In an embodiment, the second pixel circuit part PCP2may have a shape symmetrical to a shape of the first pixel circuit part PCP1. Hereinafter, the structure of the first pixel circuit part PCP1will be described in detail. In addition, the display device12may be substantially equal to the display device11described with reference toFIGS. 7, 8, 9, 10, 11, 12, 13, and 14except for the shape of a storage capacitor electrode2340and a second pattern2530.

The substrate SUB may include glass, quartz, plastic, or the like, and the buffer layer BFR may be disposed on the substrate SUB.

The first active pattern2100may be disposed on the buffer layer BFR. In an embodiment, the first active pattern2100may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, or the like. For example, the first active pattern2100may include the polycrystalline silicon formed by crystallizing the amorphous silicon.

In an embodiment, the first active pattern2100may be a first pattern receiving the driving voltage ELVDD. In other words, the driving voltage ELVDD may be provided to the first pattern.

The first gate insulating layer GI1may cover the first active pattern2100and may be disposed on the substrate SUB.

The first conductive pattern2200may be disposed on the first gate insulating layer GI1. The first conductive pattern2200may include the first gate line2210, the gate electrode2220, and a second gate line2230.

The first gate line2210may extend in the first direction D1. The first gate line2210may constitute the second transistor T2together with the first active pattern2100. In addition, the first gate line2210may constitute the seventh transistor T7together with the first active pattern2100.

The first gate electrode2220may be arranged in an island shape. The first gate electrode2220may form the first transistor T1together with the first active pattern2100.

The second gate line2230may extend in the first direction D1. The second gate line2230may constitute the fifth and sixth transistors T5and T6together with the first active pattern2100.

For example, the first conductive pattern2200may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, and the like.

The second gate insulating layer GI2may cover the first conductive pattern2200and may be disposed on the first gate insulating layer GI1. The second gate insulating layer GI2may include an inorganic insulating material.

Referring toFIGS. 16 and 21, a second conductive pattern2300may be disposed on the second gate insulating layer GI2. The second conductive pattern2300may include the gate initialization voltage line2310, the third gate line2320, the fourth gate line2330, and the storage capacitor electrode2340.

The gate initialization voltage line2310may extend in the first direction D1. The gate initialization voltage VINT may be provided to the gate initialization voltage line2310.

The third gate line2320may extend in the first direction D1. The third gate signal GI may be provided to the third gate line2320.

The fourth gate line2330may extend in the first direction D1. The second gate signal GC may be provided to the fourth gate line2330.

The storage capacitor electrode2340may overlap the first gate electrode2220and may extend in the first direction D1. For example, the storage capacitor electrode2340may constitute the storage capacitor CST together with the first gate electrode2220. In addition, a hole through the storage capacitor electrode2340may be formed in the storage capacitor electrode2340, and the first gate electrode2220may be exposed through the hole.

In an embodiment, the storage capacitor electrode2340may be an intermediate pattern receiving the driving voltage ELVDD. In other words, the driving voltage ELVDD may be provided to the intermediate pattern. For example, the intermediate pattern may include a first exposed portion2341exposed through a fourth contact hole CNT4and a second exposed portion2342exposed through a second contact hole CNT2. The first exposed portion2341may overlap the second gate line2230. The intermediate pattern may contact the first source pattern2670in the first exposed portion2341. In addition, the second exposed portion2342may contact the second source pattern2690. The intermediate pattern may contact the second source pattern2690in the second exposed portion2342.

For example, the second conductive pattern2300may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, and the like.

The first interlayer insulating layer ILD1may cover the second conductive pattern2300and may be disposed on the second gate insulating layer GI2. The first interlayer insulating layer ILD1may include an inorganic insulating material.

Referring toFIGS. 17 and 21, the second active pattern2400may be disposed on the first interlayer insulating layer ILD1. For example, the second active pattern2400may overlap the third gate line2320and the fourth gate line2330. The second active pattern1400may include an oxide semiconductor.

The third gate insulating layer GI3may cover the second active pattern2400and may be disposed on the first interlayer insulating layer ILD1. The third gate insulating layer GI3may include an inorganic insulating material.

Referring toFIGS. 18 and 21, a third conductive pattern2500may be disposed on the third gate insulating layer GI3. The third conductive pattern2500may include the fifth gate line2510, the sixth gate line2520, and the second pattern2530.

The fifth gate line2510may extend in the first direction D1. The fifth gate line2510may constitute the fourth transistor T4together with the third gate line2320and the second active pattern2400.

The sixth gate line2520may extend in the first direction D1. The sixth gate line2520may constitute the third transistor T3together with the fourth gate line2330and the second active pattern2400.

In an embodiment, the second pattern2530may be arranged in an island shape and may be provided with the driving voltage ELVDD. In other words, the driving voltage EVLDD may be provided to the second pattern2530. For example, the second pattern2530may include a third exposed portion2531exposed through a third contact hole CNT3. The third exposed portion2531may be adjacent to the first exposed portion2341, and may be spaced apart from the first exposed portion2341on a plane. The second pattern2530may contact the first source pattern1670in the third exposed portion2531.

For example, the third conductive pattern2500may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, and the like.

The second interlayer insulating layer ILD2may cover the third conductive pattern2500and may be disposed on the third gate insulating layer GI3. The second interlayer insulating layer ILD2may include an inorganic insulating material.

Referring toFIGS. 19 and 21, the fourth conductive pattern2600may be disposed on the second interlayer insulating layer ILD2. The fourth conductive pattern2600may include the first transfer pattern2610, the second transfer pattern2620, the anode initialization voltage line2630, the node pattern2640, the third transfer pattern2650, the first horizontal line2660, the first source pattern2670, the fourth transfer pattern2680, and the second source pattern2690. However, since the first transfer pattern2610, the second transfer pattern2620, the anode initialization voltage line2630, the node pattern2640, the third transfer pattern2650, and the first horizontal line2660, and the fourth transfer pattern2680are substantially equal as described above, the first source pattern2670and the second source pattern2690will be described below.

In an embodiment, the second pattern2530may be disposed to surround at least a portion of the node pattern2640on a plane.

The first source pattern2670may be arranged in an island shape. For example, the first source pattern2670may receive the driving voltage ELVDD from the storage capacitor electrode2340, and may transfer the driving voltage ELVDD to the first active pattern2100and the second pattern2530.

In an embodiment, the first source pattern2670may contact the first active pattern2100, the storage capacitor electrode2340, and the second pattern2530. For example, the first source pattern2670may contact the first active pattern2100through a fifth contact hole CNT5, may contact the storage capacitor electrode2340through the fourth contact hole CNT4, and may contact the second pattern2530through the third contact hole CNT3. In an embodiment, the third, fourth, and fifth contact holes CNT3, CNT4, and CNT5may be spaced apart from each other.

The second source pattern2690may be arranged in an island shape. For example, the second source pattern2690may receive the driving voltage ELVDD from the third source pattern2730and may transfer the driving voltage ELVDD to the storage capacitor electrode2340.

In an embodiment, the second source pattern2690may contact the storage capacitor electrode2340and the third source pattern2730. For example, the second source pattern2690may contact the third source pattern2730through a first contact hole CNT1, and may contact the storage capacitor electrode2340through the second contact hole CNT2. The first contact hole CNT1may be formed through the first via insulating layer VIA1, the second contact hole CNT2may be formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, and the first interlayer insulating layer ILD1, the third contact hole CNT3may be formed through the second interlayer insulating layer ILD2, the fourth contact hole CNT4may be formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, and the first interlayer insulating layer ILD1, and the fifth contact hole CNT5may be formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, the first interlayer insulating layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

The first via insulating layer VIA1may cover the fourth conductive pattern2600and may be disposed on the second interlayer insulating layer ILD2. The first via insulating layer VIA1may include an organic insulating material.

Referring toFIGS. 20 and 21, a fifth conductive pattern2700may be disposed on the first via insulating layer VIA1. The fifth conductive pattern2700may include the data line2710, the first vertical line2720, the third source pattern2730, and the fifth transfer pattern2740. However, the fifth conductive pattern2700may be substantially equal to the fifth conductive pattern1700described with reference toFIG. 13.

Referring toFIGS. 22 and 27, a display device13according to still another embodiment may include the first and second pixel circuit parts PCP1and PCP2arranged in the first direction D1. In an embodiment, the second pixel circuit part PCP2may have a shape symmetrical to a shape of the first pixel circuit part PCP1. Hereinafter, the structure of the first pixel circuit unit PCP1will be described in detail. In addition, the display device13may be substantially the same as the display device12described with reference toFIGS. 15, 16, 17, 18, 19, 20, and 21except for a second pattern3420.

The substrate SUB may include glass, quartz, plastic, or the like, and the buffer layer BFR may be disposed on the substrate SUB.

The first active pattern3100may be disposed on the buffer layer BFR. In one embodiment, the first active pattern3100may include a silicon semiconductor.

In an embodiment, the first active pattern3100may be a first pattern receiving the driving voltage ELVDD. In other words, the driving voltage ELVDD may be provided to the first pattern.

The first gate insulating layer GI1may cover the first active pattern3100and may be disposed on the substrate SUB.

The first conductive pattern may be disposed on the first gate insulating layer GI1. The first conductive pattern may include the first gate line3210, the gate electrode3220, and the second gate line3230. However, the first gate line3210, the gate electrode3220, and the second gate line3230may be substantially equal to the first gate line2210, the gate electrode2220, and the second gate line2230described with reference toFIG. 15.

The second gate insulating layer GI2may cover the first conductive pattern and may be disposed on the first gate insulating layer GI1. The second gate insulating layer GI2may include an inorganic insulating material.

A second conductive pattern may be disposed on the second gate insulating layer GI2. The second conductive pattern may include the gate initialization voltage line3310, the third gate line3320, the fourth gate line3330, and the storage capacitor electrode3340. However, the gate initialization voltage line3310, the third gate line3320, the fourth gate line3330, and the storage capacitor electrode3340may substantially equal to the gate initialization voltage line2310, the third gate line2320, the fourth gate line2330, and the storage capacitor electrode2340described with reference toFIG. 16. For example, the storage capacitor electrode2340may include a first exposed portion3241and a second exposed portion3342, and may be an intermediate pattern receiving the driving voltage.

The first interlayer insulating layer ILD1may cover the second conductive pattern and may be disposed on the second gate insulating layer GI2. The first interlayer insulating layer ILD1may include an inorganic insulating material.

Referring toFIGS. 23 and 27, the second active pattern3410and the second pattern3420may be disposed on the first interlayer insulating layer ILD1.

The second active pattern3410may include an oxide semiconductor. For example, the second active pattern3410may overlap the third gate line3320and the fourth gate line3330. In an embodiment, the second active pattern3410may be disposed on a different layer from the first active pattern3100and may not overlap the first active pattern3100. In other words, the second active pattern3410may be formed separately from the first active pattern3100.

The second pattern3420may be formed together with the second active pattern3410. For example, the second pattern3420may include an oxide semiconductor.

In an embodiment, the second pattern3420may be arranged in an island shape and may be provided with the driving voltage ELVDD. In other words, the driving voltage ELVDD may be provided to the second pattern3420. For example, the second pattern3420may include a third exposed portion3421exposed by a third contact hole CNT3. The third exposed part3421may be adjacent to the first exposed portion3241and may be spaced apart from the first exposed portion3241on a plane. The second pattern3420may contact the first source pattern3670in the third exposed portion3421.

The third gate insulating layer GI3may cover the second active pattern2400and may be disposed on the first interlayer insulating layer ILD1. The third gate insulating layer GI3may include an inorganic insulating material.

Referring toFIGS. 24 and 27, a third conductive pattern3500may be disposed on the third gate insulating layer GI3. The third conductive pattern3500may include the fifth gate line3510and the sixth gate line3520. However, the fifth gate line3510and the sixth gate line3520may be substantially equal to the fifth gate line2510and the sixth gate line2520described with reference toFIG. 18.

The second interlayer insulating layer ILD2may cover the third conductive pattern3500and may be disposed on the third gate insulating layer GI3. The second interlayer insulating layer ILD2may include an inorganic insulating material.

Referring toFIGS. 25 and 27, the fourth conductive pattern3600may be disposed on the second interlayer insulating layer ILD2. The fourth conductive pattern3600may include the first transfer pattern3610, the second transfer pattern3620, the anode initialization voltage line3630, the node pattern3640, the third transfer pattern3650, the first horizontal line3660, the first source pattern3670, the fourth transfer pattern3680, and the second source pattern3690. However, except for the first source pattern3670, the fourth conductive pattern3600may be substantially equal to the fourth conductive pattern2600described with reference toFIG. 19.

The first source pattern3670may be arranged in an island shape. For example, the first source pattern3670may receive the driving voltage ELVDD from the storage capacitor electrode3340, and may transfer the driving voltage ELVDD to the first active pattern3100and the second pattern3420.

In an embodiment, the first source pattern3670may contact the first active pattern3100, the storage capacitor electrode3340, and the second pattern3420. For example, the first source pattern3670may contact the first active pattern3100through a fifth contact hole CNT5, may contact the storage capacitor electrode3340through a fourth contact hole CNT4, and may contact the second pattern3420through the third contact hole CNT3. In an embodiment, the third, fourth, and fifth contact holes CNT3, CNT4, and CNT5may be spaced apart from each other. The third contact hole CNT3may be formed through the second interlayer insulating layer ILD2and the third gate insulating layer GI3, the fourth contact hole CNT4may be formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, and the first interlayer insulating layer ILD1, and the fifth contact hole CNT5may be formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, the first interlayer insulating layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

The first via insulating layer VIA1may cover the fourth conductive pattern2600and may be disposed on the second interlayer insulating layer ILD2. The first via insulating layer VIA1may include an organic insulating material.

Referring toFIGS. 26 and 27, a fifth conductive pattern3700may be disposed on the first via insulating layer VIA1. The fifth conductive pattern3700may include the data line3710, the first vertical line3720, the third source pattern3730, and the fifth transfer pattern3740. However, the fifth conductive pattern3700may be substantially equal to the fifth conductive pattern3700described with reference toFIG. 20.

FIGS. 28, 29, 30, 31, and 32are layout diagrams illustrating still another embodiment of the display device ofFIG. 1.FIG. 33is a cross-sectional view taken along line IV-IV′ ofFIG. 32.

Referring toFIGS. 28 and 33, a display device14according to still another embodiment may include the first and second pixel circuit parts PCP1and PCP2arranged in the first direction D1. In an embodiment, the second pixel circuit part PCP2may have a shape symmetrical to a shape of the first pixel circuit part PCP1. Hereinafter, the structure of the first pixel circuit part PCP1will be described in detail. In addition, the display device14may be substantially equal to the display device13described with reference toFIGS. 22, 23, 24, 25, 26, and27except for a storage capacitor electrode4340and an intermediate pattern4420.

The substrate SUB may include glass, quartz, plastic, or the like, and the buffer layer BFR may be disposed on the substrate SUB.

The first active pattern4100may be disposed on the buffer layer BFR. In an embodiment, the first active pattern4100may include a silicon semiconductor.

The first active pattern4100may be disposed on the buffer layer BFR. In an embodiment, the first active pattern4100may include a silicon semiconductor.

The first gate insulating layer GI1may cover the first active pattern4100and may be disposed on the substrate SUB.

The first conductive pattern may be disposed on the first gate insulating layer GI1. The first conductive pattern may include the first gate line4210, the gate electrode4220, and the second gate line4230. However, the first gate line4210, the gate electrode4220, and the second gate line4230may be substantially equal to the second gate line1210, the gate electrode1220, and the first gate line1230described with reference toFIG. 8.

The second gate insulating layer GI2may cover the first conductive pattern and may be disposed on the first gate insulating layer GI1. The second gate insulating layer GI2may include an inorganic insulating material.

The second conductive pattern may be disposed on the second gate insulating layer GI2. The second conductive pattern may include the gate initialization voltage line4310, the third gate line4320, the fourth gate line4330, and the storage capacitor electrode4340. However, the gate initialization voltage line4310, the third gate line4320, the fourth gate line4330, and the storage capacitor electrode4340may be substantially equal to the gate initialization voltage line1310, the third gate line1320, the fourth gate line1330, and the storage capacitor electrode1340described with reference toFIG. 9. For example, the storage capacitor electrode4340may include a first exposed portion441and may be a second pattern receiving the driving voltage.

The first interlayer insulating layer ILD1may cover the second conductive pattern and may be disposed on the second gate insulating layer GI2. The first interlayer insulating layer ILD1may include an inorganic insulating material.

Referring toFIGS. 29 and 33, the second active pattern4410and the intermediate pattern4420may be disposed on the first interlayer insulating layer ILD1.

The second active pattern4410may include an oxide semiconductor. For example, the second active pattern4410may overlap the third gate line4320and the fourth gate line4330. In an embodiment, the second active pattern4410may be disposed on a different layer from the first active pattern4100and may not overlap the first active pattern4100. In other words, the second active pattern4410may be formed separately from the first active pattern4100.

The intermediate pattern4420may be formed together with the second active pattern4410. For example, the intermediate pattern4420may include an oxide semiconductor.

In an embodiment, the intermediate pattern4420may be arranged in an island shape and may be provided with the driving voltage ELVDD. In other words, the driving voltage EVLDD may be provided to the intermediate pattern4420. For example, the intermediate pattern4420may include a second exposed portion4421exposed by a third contact hole CNT3and a third exposed portion4422exposed through a second contact hole CNT2. The second exposed part4421may be adjacent to the first exposed portion4341and may be spaced apart from the first exposed portion4341on a plane. The intermediate pattern4420may contact a first source pattern4670in the second exposure portion4421and may contact a second source pattern4690in the third exposure portion4422.

The third gate insulating layer GI3may cover the second active pattern4400and may be disposed on the first interlayer insulating layer ILD1. The third gate insulating layer GI3may include an inorganic insulating material.

Referring toFIGS. 30 and 33, a third conductive pattern4500may be disposed on the third gate insulating layer GI3. The third conductive pattern4500may include the fifth gate line4510and the sixth gate line4520. However, the fifth gate line4510and the sixth gate line4520may be substantially the same as the fifth gate line3510and the sixth gate line3520described with reference toFIG. 24.

The second interlayer insulating layer ILD2may cover the third conductive pattern4500and may be disposed on the third gate insulating layer GI3. The second interlayer insulating layer ILD2may include an inorganic insulating material.

Referring toFIGS. 31 and 33, the fourth conductive pattern4600may be disposed on the second interlayer insulating layer ILD2. The fourth conductive pattern4600may include the first transfer pattern4610, the second transfer pattern4620, the anode initialization voltage line4630, the node pattern4640, the third transfer pattern4650, the first horizontal line4660, the first source pattern4670, the fourth transfer pattern4680, and the second source pattern4690. However, except for the first source pattern4670and the second source pattern4690, the fourth conductive pattern4600may be substantially equal to the fourth conductive pattern3600.

The first source pattern4670may be arranged in an island shape. For example, the first source pattern4670may receive the driving voltage ELVDD from the intermediate pattern4420, and may transfer the driving voltage ELVDD to the first active pattern4100and the storage capacitor electrode4340.

In an embodiment, the first source pattern4670may contact the first active pattern4100, the storage capacitor electrode4340, and the intermediate pattern4420. For example, the first source pattern3670may contact the first active pattern4100through a fifth contact hole CNT5, may contact the storage capacitor electrode4340through the fourth contact hole CNT4, and may contact the intermediate pattern4420through the third contact hole CNT3. In an embodiment, the third to fifth contact holes CNT3, CNT4, and CNT5may be spaced apart from each other.

The second source pattern4690may be arranged in an island shape. For example, the second source pattern4690may receive the driving voltage ELVDD from the third source pattern4730and may transfer the driving voltage ELVDD to the intermediate pattern4420.

In an embodiment, the second source pattern4690may contact the intermediate pattern4420and the third source pattern2730. For example, the second source pattern4690may contact the third source pattern4730through a first contact hole CNT1, and may contact the intermediate pattern4420through the second contact hole CNT2.

The first via insulating layer VIA1may cover the fourth conductive pattern4600and may be disposed on the second interlayer insulating layer ILD2. The first via insulating layer VIA1may include an organic insulating material. The first contact hole CNT1may be formed through the first via insulating layer VIA1, the second contact hole CNT2may be formed through the second interlayer insulating layer ILD2and the third gate insulating layer GI3, the third contact hole CNT3may be formed through the second interlayer insulating layer ILD2and the third gate insulating layer GI3, the fourth contact hole CNT4may be formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, and the first interlayer insulating layer ILD1, and the fifth contact hole CNT5may be formed through the second interlayer insulating layer ILD2, the third gate insulating layer GI3, the first interlayer insulating layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

Referring toFIGS. 34 and 35, a fifth conductive pattern4700may be disposed on the first via insulating layer VIA1. The fifth conductive pattern4700may include the data line4710, the first vertical line4720, the third source pattern4730, and the fifth transfer pattern4740. However, the fifth conductive pattern4700may be substantially equal to the fifth conductive pattern3700described with reference toFIG. 26.

FIG. 34is a block diagram illustrating a display device according to other embodiments.FIG. 35is an equivalent circuit diagram illustrating of a first pixel included in the display device ofFIG. 34.FIG. 36is a cross-sectional view illustrating the display device of FIG.34.

Referring toFIGS. 34 and 35, a display device20according to other embodiments may include a display panel PNL, a data driver DDV, a gate driver GDV, an emission driver EDV, and a controller CON. However, the display device20may be substantially equal to the display device10described with reference toFIG. 1except for the structure of the display panel PNL.

The display panel PNL may include a plurality of pixels. For example, the display panel PNL may include a first pixel PX1and a second pixel PX2. Each of the first and second pixels PX1and PX2may be provided with a data voltage DATA, a gate signal GS, an emission control signal EM, a driving voltage ELVDD, a common voltage ELVSS, and a gate initialization voltage VINT.

The first pixel circuit PC1may include a first transistor T1, a second transistor T2, a third dual transistor T3-1and T3-2, a fourth dual transistor T4-1and T4-2, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a storage capacitor CST, and a boosting capacitor CBS. Compared with the first pixel circuit PC1described with reference toFIG. 2, the first pixel circuit PC1illustrated inFIG. 35may include the third dual transistors T3-1and T3-2and the fourth dual transistors T4-1and T4-2, and a second terminal of the seventh transistor T7may receive a gate initialization voltage VINT.

Referring toFIG. 36, the first pixel circuit part PCP1and the first display element ED1may constitute the first pixel PX1. In addition, the second pixel circuit part PCP2and the second display element ED2may constitute the second pixel PX2.

The first display element ED1may include a first pixel electrode ADE1, a first emission layer ELL and a common electrode CTE.

The first pixel circuit part PCP1may include a substrate SUB, an active pattern5100, a first conductive pattern5200, a second conductive pattern5300, a third conductive pattern5600, and a fourth conductive pattern5700. Compared with the first pixel circuit part PCP1described with reference toFIG. 5, the first pixel circuit part PCP1illustrated inFIG. 36may not include the second active pattern1400and the third conductive pattern1500.

Referring toFIGS. 37 and 42, the display device20may include the first and second pixel circuit parts PCP1and PCP2arranged in the first direction D1. In an embodiment, the second pixel circuit part PCP2may have the same shape as the first pixel circuit part PCP1. Hereinafter, the structure of the first pixel circuit part PCP1will be described in detail.

The substrate SUB may include glass, quartz, plastic, or the like, and the buffer layer BFR may be disposed on the substrate SUB.

The active pattern5100may be disposed on the buffer layer BFR. In an embodiment, the active pattern5100may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, or the like. For example, the active pattern5100may include the polycrystalline silicon formed by crystallizing the amorphous silicon.

In an embodiment, the active pattern5100may be a first pattern receiving the driving voltage ELVDD. In other words, the driving voltage ELVDD may be provided to the first pattern.

The first gate insulating layer GI1may cover the active pattern5100and may be disposed on the substrate SUB. The first gate insulating layer GI1may include an inorganic insulating material. For example, the first gate insulating layer GI1may include silicon oxide, silicon nitride, silicon oxynitride, or the like.

Referring toFIGS. 38 and 42, the first conductive pattern5200may be disposed on the first gate insulating layer GI1. The first conductive pattern5200may include a first gate line5210, a second gate line5220, a gate electrode5230, and a third gate line5240.

The first gate line5210may extend in the first direction D1. The first gate line5210may constitute the fourth dual transistors T4-1and T4-2and the seventh transistor T7together with the first active pattern5100.

The second gate line5220may extend in the first direction D1. The second gate line5220may constitute the third dual transistors T3-1and T3-2and the second transistor T2together with the first active pattern5100.

The gate electrode5230may be arranged in an island shape. The gate electrode5230may form the first transistor T1together with the active pattern5100.

The third gate line5240may extend in the first direction D1. The third gate line1240may constitute the fifth and sixth transistors T5and T6together with the active pattern5100. For example, the emission control signal EM may be provided to the third gate line5240. The third gate line5240may be referred to as an emission control line.

For example, the first conductive pattern5200may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, and the like.

The second gate insulating layer GI2may cover the first conductive pattern5200and may be disposed on the first gate insulating layer GI1. The second gate insulating layer GI2may include an inorganic insulating material.

Referring toFIGS. 39 and 42, the second conductive pattern5300may be disposed on the second gate insulating layer GI2. The second conductive pattern5300may include a gate initialization voltage line5310and a storage capacitor electrode5320.

The gate initialization voltage line5310may extend in the first direction D1. For example, the gate initialization voltage line5310may be spaced apart from the first gate line5210on a plane. The gate initialization voltage VINT may be provided to the gate initialization voltage line5310.

The storage capacitor electrode5320may overlap the first gate electrode5230and may extend in the first direction D1. For example, the storage capacitor electrode5320may constitute the storage capacitor CST together with the first gate electrode5230. In addition, a hole through the storage capacitor electrode5320may be formed in the storage capacitor electrode5320, and the first gate electrode5230may be exposed through the hole.

In an embodiment, the storage capacitor electrode5320may be a second pattern receiving the driving voltage ELVDD. In other words, the driving voltage ELVDD may be provided to the second pattern. For example, the second pattern may include a first exposed portion5321exposed by a second contact hole CNT2and a second exposed portion5322exposed by a third contact hole CNT3.

For example, the second conductive pattern5300may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like.

The first interlayer insulating layer ILD1may cover the second conductive pattern5300and may be disposed on the second gate insulating layer GI2. The first interlayer insulating layer ILD1may include an inorganic insulating material.

Referring toFIGS. 40 and 42, the third conductive pattern5600may be disposed on the first interlayer insulating layer ILD1. The third conductive pattern5600may include a first transfer pattern5610, a node pattern5620, a second source pattern5630, a first horizontal line5640, a first source pattern5650, and a second transfer pattern5660.

The first transfer pattern5610may be arranged in an island shape. The first transfer pattern5610may contact the gate initialization voltage line5310and the active pattern5100, and may transfer the gate initialization voltage VINT to the active pattern5100.

The node pattern5620may extend in the first direction D1. The node pattern5620may contact the gate electrode5230and the active pattern5100. For example, the node pattern5230may electrically connect the gate terminal of the first transistor T1and the drain terminal of the third transistor T3.

The second source pattern5630may be arranged in an island shape. For example, the second source pattern5630may receive the driving voltage ELVDD from the third source pattern5730and may transmit the driving voltage ELVDD to the storage capacitor electrode5320.

In an embodiment, the second source pattern5630may contact the storage capacitor electrode5320and the third source pattern5730. For example, the second source pattern5630may contact the third source pattern5730through a first contact hole CNT1, and may contact the storage capacitor electrode5320through the second contact hole CNT2.

The first horizontal line5640may extend in the first direction D1. In an embodiment, the data voltage DATA may be transmitted through the first horizontal line5640. For example, the first horizontal line5640may correspond to any one of the first horizontal line HFL1and the second horizontal line HFL2described with reference toFIG. 6.

The first source pattern5650may be arranged in an island shape. For example, the first source pattern5650may receive the driving voltage ELVDD from the storage capacitor electrode5320and may transmit the driving voltage ELVDD to the active pattern5100.

In an embodiment, the first source pattern5650may contact the active pattern5100and the storage capacitor electrode5320. For example, the first source pattern5650may contact the active pattern5100through a fourth contact hole CNT4, and may contact the storage capacitor electrode5320through the third contact hole CNT3. In an embodiment, the third and fourth contact holes CNT3and CNT4may be spaced apart from each other.

The second transfer pattern5660may be arranged in an island shape. The second transfer pattern5660may contact the active pattern5100. The second transfer pattern5660may receive the driving current and/or the gate initialization voltage VINT from the active pattern5100.

The first via insulating layer VIA1may cover the third conductive pattern5600and may be disposed on the first interlayer insulating layer ILD1. The first via insulating layer VIA1may include an organic insulating material.

Referring toFIGS. 41 and 42, a fourth conductive pattern5700may be disposed on the first via insulating layer VIA1. The fourth conductive pattern5700may include a data line5710, a first vertical line5720, a third source pattern5730, and a third transfer pattern5740.

The data line5710may extend in the second direction D2. The data line5710may contact the active pattern5100. In an embodiment, the data voltage DATA may be provided to the active pattern5100through the data line5710. For example, the data line5710may correspond to any one of the first to fourth data lines DL1, DL2, DL3, and DL4described with reference toFIG. 6.

The first vertical line5720may extend in the second direction D2. In an embodiment, the data voltage DATA may be transmitted through the first vertical line5720. For example, the first vertical line5720may correspond to one of the first vertical line VFL1and the second vertical line VFL2described with reference toFIG. 6.

The third source pattern5730may extend in the second direction D2. In an embodiment, the driving voltage ELVDD may be transmitted through the third source pattern5730.

In an embodiment, the third source pattern5730may contact the second source pattern5630through a first contact hole CNT1.

In an embodiment, the first contact hole CNT1may pass through the first via insulating layer VIA1, a second contact hole CNT2and the third contact hole CNT3may pass through the first interlayer insulation ILD1, and the fourth contact hole CNT4may pass through the first interlayer insulating layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1. In other words, the first contact hole CNT1may pass through a layer made of an organic insulating material, and the second, third, and fourth contact holes CNT2, CNT3, and CNT4may pass through a layer made of an inorganic insulating material. Accordingly, each of the planar areas of the second, third, and fourth contact holes CNT2, CNT3, and CNT4may be smaller than the planar area of the first contact hole CNT1. The first contact hole CNT1may be formed through the first via insulating layer VIA1, the second contact hole CNT2may be formed through the first interlayer insulating layer ILD1, the third contact hole CNT3may be formed through the first interlayer insulating layer ILD1, and the fourth contact hole CNT4may be formed through the first interlayer insulating layer ILD1, the second gate insulating layer GI2, and the first gate insulating layer GI1.

The third transfer pattern5740may be arranged in an island shape. The third transfer pattern5740may contact the second transfer pattern5660. The third transfer pattern5740may receive the driving current and/or the gate initialization voltage VINT from the second transfer pattern5660, and may transfer the driving current and/or the gate initialization voltage VINT to the first pixel electrode ADE1.

In an embodiment, as shown inFIG. 41, the third source pattern5730may contact the second source pattern5630through the first contact hole CNT1, the second source pattern5630may contact the storage capacitor electrode5320through the second contact hole CNT2, and the storage capacitor electrode5320may provide the first source pattern5650through the third contact hole CNT3. Accordingly, the driving voltage ELVDD may be transmitted to the third source pattern5730, the second source pattern5630, the storage capacitor electrode5320, and the first source pattern5650. In addition, the first source pattern5650may contact the active pattern5100through the fourth contact hole CNT4. Accordingly, the first source pattern5650may transfer the driving voltage ELVDD to the active pattern5100.

The display device20may include the first source pattern5650and the storage capacitor electrode5320for transmitting the driving voltage ELVDD. Accordingly, additional contact holes for electrically connecting the third source pattern5730to the first active pattern5100and the storage capacitor electrode5320may not be added in the first via insulating layer VIA1. In other words, the driving voltage ELVDD may be transferred to the first active pattern5100and the storage capacitor electrode5320through the first contact hole CNT1formed in the first via insulating layer VIA1. Accordingly, the number of contact holes passing through the layer made of the organic insulating material may be relatively small. Therefore, the shape of the third source pattern5730may be designed relatively freely.