SEMICONDUCTOR DEVICE INCLUDING BURIED WORD LINE

A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a substrate, a first word line, a bit line, and a first capacitor. The substrate has a first surface and a second surface opposite to the first surface. The first word line is disposed within the substrate. The bit line is disposed on the first surface of the substrate. The first capacitor is disposed on the second surface of the substrate.

TECHNICAL FIELD

The present disclosure relates to a semiconductor device and a method of manufacturing the same, and in particularly to a semiconductor device including a buried word line.

DISCUSSION OF THE BACKGROUND

With the rapid growth of the electronics industry, the development of integrated circuits (ICs) has achieved high performance and miniaturization. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation.

A Dynamic Random Access Memory (DRAM) device is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Typically, a DRAM is arranged in a square array of one capacitor and transistor per cell. A vertical transistor has been developed for the 4F2DRAM cell, in which F represents the photolithographic minimum feature width or critical dimension (CD). However, recently, DRAM manufacturers are facing significant challenges in minimizing memory cell area as word line spacing continues to be reduced.

This Discussion of the Background section is provided for background information only. The statements in this Discussion of the Background are not an admission that the subject matter disclosed herein constitutes prior art with respect to the present disclosure, and no part of this Discussion of the Background may be used as an admission that any part of this application constitutes prior art with respect to the present disclosure.

SUMMARY

One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first word line, a bit line, and a first capacitor. The substrate has a first surface and a second surface opposite to the first surface. The first word line is disposed within the substrate. The bit line is disposed on the first surface of the substrate. The first capacitor is disposed on the second surface of the substrate.

Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first word line, and a bit line. The substrate has a first surface and a second surface opposite to the first surface. The first word line is disposed within the substrate. The first word line is embedded within the substrate and exposed from the second surface of the substrate. The bit line is disposed on the first surface of the substrate.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device. The method includes: providing a substrate having a first surface and a second surface opposite to the first surface; forming a word line within the substrate; forming a bit line on the first surface of the substrate; and forming a first capacitor on the second surface of the substrate.

The embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a substrate, a word line, a bit line, and a capacitor. The word line is buried within the trench of the substrate. The bit line and the capacitor are disposed on two opposite sides of the substrate. Each units of the semiconductor device may include two transistors and a capacitor, which enhances the driving current. Further, the word line can function as a common switch to turn and/or turn off two transistors, which reduces the size of the semiconductor device. In comparison with conventional semiconductor devices, the semiconductor device of the present disclosure has a better performance.

DETAILED DESCRIPTION

It shall be understood that when an element is referred to as being “connected to” or “coupled to” another element, the initial element may be directly connected to, or coupled to, another element, or to other intervening elements.

Referring toFIG.1A,FIG.1B, andFIG.1C,FIG.1Ais a top view of a semiconductor device100,FIG.1Bis a cross-section along line A-A′ of the semiconductor device100as shown inFIG.1A, andFIG.1Cis a cross-section along line B-B′ of the semiconductor device100as shown inFIG.1A, in accordance with some embodiments of the present disclosure. The semiconductor device100may be included in a memory device. The memory device may include, for example, a dynamic random access memory (DRAM) device, a one-time programming (OTP) memory device, a static random access memory (SRAM) device, or other suitable memory devices. During read operation, a word line can be asserted, turning on the transistor. The enabled transistor allows the voltage across the capacitor(s) to be read by a sense amplifier through a bit line. During a write operation, the data to be written can be provided on the bit line when the word line is asserted.

As shown inFIG.1A, the semiconductor device100may include a plurality of unit cells U1. In some embodiments, each of the unit cells U1may include two transistors (such as denotations Z1and Z2labeled inFIG.1B) and one capacitor170. The semiconductor device100may include a substrate110. In some embodiments, the substrate110may define a plurality of openings120. The opening120may have a strip profile. The substrate110may include a plurality of doped regions113. In some embodiments, the region of the substrate110corresponding to the doped region113may also be referred to as an active region. The semiconductor device100may include a plurality of doped regions114. Each of the doped regions114may be configured to isolate adjacent unit cells U1. The semiconductor device100may include a plurality of bit lines130. The semiconductor device100may include a plurality of word lines140, each of which may extend across multiple bit lines130. In some embodiments, each of the word lines140may be located or embedded within the corresponding opening120of the substrate110. Each of the openings120may extend across multiple bit lines130. The semiconductor device100may include conductive vias161,162,163, and164. The conductive via161may be electrically connected to the doped region113. The conductive via162may be electrically connected to the doped region114. The conductive via163may be disposed at an end of the bit line130and electrically connected to the bit line130. The conductive via164may be disposed at an end of the word line140and electrically connected to the word line140.

As shown inFIG.1B, the substrate110may have a surface110s1(or a bottom surface) and a surface110s2(or a top surface) opposite to the surface110s1. The substrate110may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate110may include an elementary semiconductor including silicon or germanium in a single crystal form, a polycrystalline form, or an amorphous form, a compound semiconductor material including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP, any other suitable material, or a combination thereof. In some embodiments, the alloy semiconductor substrate may include a SiGe alloy with a gradient Ge feature in which the Si and Ge composition changes from one ratio at one location to another ratio with location of the feature. In another embodiment, the SiGe alloy is formed over a silicon substrate. In some embodiments, a SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate110may have a multilayer structure, or the substrate110may include a multilayer compound semiconductor structure. It should be noted that some doped regions, isolation structures, and/or other features may be formed within the substrate110.

The substrate110may have a well region111. The well region111may have a relatively small dopant concentration. The well region111may have a first conductive type. In some embodiments, the first conductive type may be an n type or a p type. In some embodiments, n type dopants may include, for example, arsenic (As), phosphorus (P), other group V elements, or any combination thereof. In some embodiments, p type dopants may include, for example, boron (B), other group III elements, or any combination thereof.

The substrate110may have a doped region112. The doped region112may be disposed adjacent to the surface110s1of the substrate110. The doped region112may have the first conductive type. The doped region112may be in contact with the well region111. The doped region112may have a relatively large dopant concentration. The dopant concentration of the doped region112may be greater than that of the well region111.

The doped region113may be disposed adjacent to the surface110s2of the substrate110. The doped region113may have the first conductive type. The doped region113may be in contact with the well region111. The doped region113may have a relatively large dopant concentration. The dopant concentration of the doped region113may be greater than that of the well region111. The well region111may be disposed between the doped regions112and113.

The substrate110may have a doped region114. In some embodiments, the doped region114may be disposed over or within the active region. In some embodiments, the doped region114may continuously extend between the surface110s1and surface110s2of the substrate110. In some embodiments, the doped region114may have a second conductive type different from the first conductive type. The doped region114may have a relatively large dopant concentration. The dopant concentration of the doped region114may be greater than that of the well region111. In some embodiments, the doped region114may be disposed between adjacent unit cells U1. In some embodiments, the doped region114may serve as an isolation feature configured to isolate an electrical path between unit cells U1through the substrate110.

The opening120may penetrate substrate110. In some embodiments, the opening120may be tapered along a direction from the surface110s2toward the surface110s1of the substrate110.

The semiconductor device100may include a dielectric layer121. In some embodiments, the dielectric layer121may be disposed on the surface110s1of the substrate110. In some embodiments, the dielectric layer121may cover the doped region114. In some embodiments, the dielectric layer121may vertically overlap the word line140. In some embodiments, the dielectric layer121may define a pattern exposing a portion of the well region111. The dielectric layer121may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

The semiconductor device100may include an isolation layer122. In some embodiments, the isolation layer122may be disposed on the dielectric layer121. In some embodiments, the isolation layer122may be disposed within the opening120defined by the substrate110. In some embodiments, the isolation layer122may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, a trench may be defined by the substrate110and the isolation layer122, and the word line140is located within the trench.

The semiconductor device100may include a dielectric layer123. In some embodiments, the dielectric layer123may be disposed on the surface110s2of the substrate110. In some embodiments, the dielectric layer123may cover the word line140. The dielectric layer123may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

In some embodiments, the bit line130may be disposed on the dielectric layer121. In some embodiments, the bit line130may be disposed on the surface110s1of the substrate110. The bit line130may include conductive materials, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof.

The semiconductor device100may include a conductive via132. In some embodiments, the conductive via132may fill the openings defined by the dielectric layer121. The conductive via132may extend between the surface110s1of the substrate110and the bit line130. The conductive via132may include conductive materials, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof.

In some embodiments, the word line140may be disposed within the opening120defined by the substrate110. In some embodiments, the word line140may be disposed within the trench defined by the substrate110and the isolation layer122. In some embodiments, the word line140may cover the isolation layer122. In some embodiments, the word line140may be at least partially tapered from the surface110s2toward the surface110s1of the substrate110. In some embodiments, the word line140may be spaced apart from the bit line130by the dielectric layer121and the isolation layer122. The word line140may include conductive materials, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof. In some embodiments, the word line140may include a semiconductor material, such as polysilicon. The word line140may have a surface140s1(or a top surface). In some embodiments, the surface140s1of the word line140may be exposed from the substrate110. In some embodiments, the surface140s1of the word line140may be substantially coplanar with the surface110s2of the substrate110.

In some embodiments, the word line140may have different thickness along a direction from the surface110s2to the surface110s1of the substrate110. The word line140may have a thickness T1at an edge portion120eof the opening120. The word line140may have a thickness T2at a center portion120cof the opening120. In some embodiments, the thickness T1may be different from the thickness T2. In some embodiments, the thickness T1may be greater than the thickness T2.

The semiconductor device100may include a gate dielectric layer151and a gate dielectric layer152. In some embodiments, the gate dielectric layer151may be disposed within the opening120defined by the substrate110. In some embodiments, the gate dielectric layer151may be disposed at a side140e1of the word line140. In some embodiments, a top surface (not annotated) of the gate dielectric layer151may be substantially coplanar with the surface110s2of the substrate110. In some embodiments, the top surface of the gate dielectric layer151may be substantially coplanar with the surface140s1of the word line140. In some embodiments, the gate dielectric layer151may be in contact with the isolation layer122. The bottom of the gate dielectric layer151may be connected to the isolation layer122. In some embodiments, the word line140may be spaced apart from the substrate110by the gate dielectric layer151.

In some embodiments, the gate dielectric layer152may be disposed within the opening120defined by the substrate110. In some embodiments, the gate dielectric layer152may be disposed at a side140e2of the word line140. In some embodiments, a top surface (not annotated) of the gate dielectric layer152may be substantially coplanar with the surface110s2of the substrate110. In some embodiments, the top surface of the gate dielectric layer152may be substantially coplanar with the surface140s1of the word line140. The bottom of the gate dielectric layer152may be connected to the isolation layer122. In some embodiments, the gate dielectric layer151may be nonparallel to the gate dielectric layer152. Each of the gate dielectric layers151and152may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, each of the gate dielectric layers151and152may include a high-k dielectric material(s). The high-k dielectric material may have a dielectric constant (k value) exceeding 4. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2) or another applicable material.

In some embodiments, the substrate110may define a channel111c1abutting the gate dielectric layer151. In some embodiments, the substrate110may define a channel111c2abutting the gate dielectric layer152. In some embodiments, the substrate110, the bit line130, and the word line140may collectively define transistors Z1and Z2. The word line140may serve as a common gate to turn on and/or turn off the transistors Z1and Z2. The doped regions112and113may serve as a source/drain feature. In some embodiments, the transistors Z1and Z2may at least partially located within the same opening120.

The conductive via161may be disposed on the surface110s2of the substrate110. The conductive via161may be disposed within the dielectric layer123. The conductive via161may be electrically connected to the doped region113.

The conductive via162may be disposed on the surface110s2of the substrate110. The conductive via162may be disposed within the dielectric layer123. The conductive via162may be electrically connected to the doped region114.

The conductive via163may penetrate the substrate110. The conductive via163may penetrate the dielectric layer123. The conductive via163may be electrically connected to the bit line130. In some embodiments, each of the conductive vias161,162, and163may include conductive materials, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof.

In some embodiments, the capacitor170may be disposed on the surface110s2of the substrate110. The capacitor170may be disposed on the dielectric layer123. In some embodiments, the capacitor170may be electrically connected to the conductive via161. The capacitor170may cover the word line140. The capacitor170may extend across the side140e1and side140e2of the word line140. In some embodiments, the capacitor170may be electrically connected to both the transistors Z1and Z2. In some embodiments, the capacitor170may include a capacitor dielectric layer and two capacitor electrodes. The capacitor dielectric layer may include hafnium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, aluminum oxide, titanium oxide or another applicable material. The capacitor electrode may include conductive materials, such as tungsten, copper, aluminum, tantalum, molybdenum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof.

The semiconductor device100may include a conductive trace181. The conductive trace181may be disposed on the conductive via162. The conductive trace181may be electrically connected to the conductive via162.

The semiconductor device100may include a conductive trace182. The conductive trace182may be disposed on the conductive via163. The conductive trace182may be electrically connected to the conductive via163. Each of the conductive traces181and182may include conductive materials, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof.

As shown inFIG.1C, the semiconductor device100may include a fill layer124. In some embodiments, the fill layer124may be disposed on the surface110s1of the substrate110. The fill layer124may be disposed on the dielectric layer121. The fill layer124may have a surface124s1(or a bottom surface). In some embodiments, the surface124s1of the fill layer124may be substantially coplanar with a surface130s1(or a bottom surface), as shown inFIG.1B, of the bit line130.

In some embodiments, the fill layer124and the bit line130may be collectively configured to define a hybrid bonding structure. The hybrid bonding structure may be bonded to other devices (not shown), such as a wafer, a redistribution structure, or other suitable devices.

The conductive via164may penetrate the dielectric layer123. The conductive via163may be electrically connected to the word line140.

The semiconductor device100may include a conductive trace183. The conductive trace183may be disposed on the conductive via164. The conductive trace183may be electrically connected to the conductive via164.

In this embodiments, the word line140is buried within the substrate110. The bit line130and the capacitor170are disposed on two opposite sides of the substrate110. Each units U1of the semiconductor device100includes two transistors and a capacitor, which enhances the driving current. Further, the word line140functions as a common switch to turn and/or turn off two transistors, which reduces the size of the semiconductor device. In comparison with conventional semiconductor devices, the semiconductor device100of the present disclosure has a better performance.

FIG.2is a flowchart illustrating a method200of manufacturing a semiconductor device, in accordance with some embodiments of the present disclosure.

The method200begins with operation201in which a substrate is provided. The substrate has a bottom surface and a top surface. The substrate may have a well region with a first conductive type. A first doped region with the first conductive type may be formed adjacent to the top surface of the substrate. A trench may be formed and recessed from the top surface of the substrate.

The method200continues with operation202in which a peripheral portion of an isolation layer within the trench may be removed. A gate dielectric layer may be formed on the sidewall of the trench.

The method200continues with operation203in which the top of a center portion of the isolation layer may be removed.

The method200continues with operation204in which a word line may be formed within the trench.

The method200continues with operation205in which the bottom surface of the substrate may be polished or grinded. The bottom of the isolation feature is exposed.

The method200continues with operation206in which a second doped region with the first conductive type may be formed adjacent to the bottom surface of the substrate.

The method200continues with operation207in which a third doped region with a second conductive type may be formed between the top surface and the bottom surface of the substrate.

The method200continues with operation208in which a bit line may be formed on the bottom surface of the substrate.

The method200continues with operation209in which a capacitor may be formed on the top surface of the substrate.

The method200is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, or after each operation of the method200, and some operations described can be replaced, eliminated, or reordered for additional embodiments of the method. In some embodiments, the method200can include further operations not depicted inFIG.2. In some embodiments, the method200can include one or more operations depicted inFIG.2.

Referring toFIG.3A,FIG.3B, andFIG.3C, a substrate110may be provided. The substrate110may have a well region111therein. A doped region113may be formed adjacent to the surface110s2of the substrate110. A plurality of openings (or trenches)120may be formed. The opening120may be recessed from the surface110s2of the substrate110. An isolation layer122′ may be formed within the opening120. The isolation layer122′ may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

Referring toFIG.4A,FIG.4B, andFIG.4C, a pattern191may be formed on the isolation layer122′. The pattern191may serve as a mask configured to define an etched portion during an etch process. The pattern191may be formed on a center portion (not annotated) of the isolation layer122′. An etching process may be performed to remove a peripheral portion (not annotated) of the isolation layer122′. The isolation layer122′ may be removed by, for example, a wet etching. An isolation layer122may be defined within the opening120. Openings122omay be formed. The opening122omay be recessed from the surface110s2of the substrate110.

Referring toFIG.5A,FIG.5B, andFIG.5C, the pattern191may be removed. A top portion122pof the center portion of the isolation layer122may be exposed. A gate dielectric layer151, a gate dielectric layer152, and a dielectric layer153may be formed. The dielectric layer153may be connected to the gate dielectric layers151and152. The gate dielectric layers151and152may be formed within the sidewall (not annotated) of the opening120and on the isolation layer122. The dielectric layer153may be formed on the surface110s2of the substrate110. The gate dielectric layer151, gate dielectric layer152, and dielectric layer153may include silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric material(s). The gate dielectric layer151, gate dielectric layer152, and dielectric layer153may be formed by, for example, chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable processes.

Referring toFIG.6A,FIG.6B, andFIG.6C, the dielectric layer153may be removed. In some embodiments, the top portion122pof the isolation layer122may be removed. The dielectric layer153and isolation layer122may be removed by, for example, chemical mechanical polishing process, grinding process, etching process, or other suitable processes.

Referring toFIG.7A,FIG.7B, andFIG.7C, a word line140may be formed within the opening120. The word line140may fill the opening122o.The word line140may be formed on the gate dielectric layers151and152. The word line140may be formed by PVD, CVD, ALD, LPCVD, PECVD, or other suitable processes.

Referring toFIG.8A,FIG.8B, andFIG.8C, the surface110s2of the substrate110may be attached to a supporter192. The supporter192may include a plastic supporter, a glass supporter, a ceramic supporter, or other suitable supporters.

Referring toFIG.9A,FIG.9B, andFIG.9C, a portion of the substrate110may be removed. In some embodiments, the surface110s1of the substrate110may be grinded or polished by chemical mechanical polishing process, grinding process, or other suitable processes. The bottom of the isolation layer122may be exposed from the surface110s1of the substrate110. A doped region112may be formed adjacent to the surface110s1of the substrate110.

Referring toFIG.10A,FIG.10C, andFIG.10C, a pattern193may be formed on the surface110s1of the substrate110to define a pattern of a doped region114. The doped region114may be formed within the substrate110. The doped region114may have a conductive type different from that of the doped region112(or113).

Referring toFIG.11A,FIG.11C, andFIG.11C, the pattern193may be removed. A dielectric layer121′ may be formed on the surface110s1of the substrate110. The dielectric layer121′ may include silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric material(s).

Referring toFIG.12A,FIG.12B, andFIG.12C, the dielectric layer121′ may be patterned to form the dielectric layer121. The dielectric layer121may have openings121oexposing the surface110s1of the substrate110. The doped region114may be covered by the dielectric layer121.

Referring toFIG.13A,FIG.13B, andFIG.13C, a metallization layer130′ may be formed on the surface110s1of the substrate110. The metallization layer130′ may fill the openings1210as shown inFIG.12B. The metallization layer130′ may include conductive materials, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof. The metallization layer130′ may be formed by PVD, CVD, ALD, LPCVD, PECVD, or other suitable processes.

Referring toFIG.14A,FIG.14B, andFIG.14C, the metallization layer130′ may be patterned to form bit lines130and conductive vias132over the active region. In some embodiments, the bit line130may be protruded from the dielectric layer121. The metallization layer130′ may be patterned by wet etching, dry etching, or other suitable processes.

Referring toFIG.15A,FIG.15B, andFIG.15C, a fill layer124may be formed. The fill layer124may cover the dielectric layer121. The fill layer124may cover the bit line130. The fill layer124may fill openings defined by the bit line130. The fill layer124may be formed by CVD, ALD, LPCVD, PECVD, PVD, or other suitable processes.

Referring toFIG.16A,FIG.16B, andFIG.16C, a portion of the fill layer124may be removed. As a result, the surface124s1of the fill layer124may be coplanar with the surface130s1of the bit line130. The fill layer124may be removed by, for example, CVD, grinding, or other suitable processes.

Referring toFIG.17A,FIG.17B, andFIG.17C, the supporter192may be removed. The word line140may be exposed. The bit line130and the fill layer124may be attached to a supporter194. The supporter194may include a glass supporter, a ceramic supporter, or other suitable supporters.

Referring toFIG.18A,FIG.18B, andFIG.18C, a dielectric layer123may be formed on the word line140. The dielectric layer123may be formed on the surface110s2of the substrate110. The dielectric layer123may be formed by CVD, ALD, LPCVD, PECVD, PVD, or other suitable processes.

Referring toFIG.19A,FIG.19B, andFIG.19C, conductive vias161,162, and164may be formed. Conductive traces181and183may be formed. The dielectric layer123may be patterned to define openings, a conductive layer may be formed on the dielectric layer123and fill the openings, and the conductive layer may be patterned to form the conductive vias161,162, and164as well as the conductive traces181and183.

Referring toFIG.20A,FIG.20B, andFIG.20C, a capacitor170may be formed on the dielectric layer123. The capacitor170may be electrically connected to the conductive via161.

Referring toFIG.21A,FIG.21B, andFIG.21C, a conductive via163and a conductive trace182may be formed. In some embodiments, an etching process, such as dry etching, may be performed to form an opening penetrating the dielectric layer123and the substrate110to expose the bit line130, a conductive layer may be formed on the dielectric layer123and fill the openings, and the conductive layer may be patterned to form the conductive via163and the conductive trace182.

Referring toFIG.22A,FIG.22B, andFIG.22C, the supporter194may be removed. As a result, a semiconductor device, such as the semiconductor device100as shown inFIG.1A,FIG.1B, andFIG.1C, may be produced. The fill layer124and the bit line130may collectively define a hybrid bonding structure so that the semiconductor device100may be bonded to another device.

Referring toFIG.23A,FIG.23B, andFIG.23C,FIG.23Ais a top view of a semiconductor device300,FIG.23Bis a cross-section along line C-C′ of the semiconductor device300as shown inFIG.23A, andFIG.23Cis a cross-section along line D-D′ of the semiconductor device300as shown inFIG.23A, in accordance with some embodiments of the present disclosure. The semiconductor device300may be included in a memory device. The memory device may include, for example, a DRAM device, an OTP memory device, a SRAM device, or other suitable memory devices.

As shown inFIG.23A, the semiconductor device300may include a plurality of unit cells U2. In some embodiments, each of the unit cells U2may include two transistors (such as denotations Z3and Z4labeled inFIG.23B) and two capacitors371and372. The semiconductor device300may include a substrate310. In some embodiments, the semiconductor device300may include a plurality of openings320. The opening320may have a strip profile. The substrate310may include a plurality of doped regions313. In some embodiments, the region of the substrate310corresponding to the doped region313may also be referred to as an active region. The semiconductor device300may include a plurality of doped regions314. Each of the doped regions314may be configured to isolate adjacent unit cells U2. The semiconductor device300may include a plurality of bit lines330. The semiconductor device300may include a plurality of word lines341extending across the plurality of bit lines330. The semiconductor device300may include a plurality of word lines342extending across multiple bit lines330. In some embodiments, each of the word lines341and342may be located or embedded within the corresponding opening320defined by the substrate310. Each of the openings320may extend across multiple bit lines330. The semiconductor device300may include conductive vias361,362,363,364, and365. The conductive via361may be electrically connected to the doped region313. The conductive via362may be electrically connected to the doped region314. The conductive via363may be disposed at an end of the bit line330and electrically connected to the bit line330. The conductive via364may be disposed at an end of the word line341and electrically connected to the word line341. The conductive via365may be disposed at an end of the word line342and electrically connected to the word line342.

As shown inFIG.23B, the substrate310may have a surface310s1(or a bottom surface) and a surface310s2(or a top surface) opposite to the surface310s1. The substrate310may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The substrate310may include an elementary semiconductor including silicon or germanium in a single crystal form, a polycrystalline form, or an amorphous form, a compound semiconductor material including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide, an alloy semiconductor material including at least one of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and GaInAsP, any other suitable material, or a combination thereof. In some embodiments, the alloy semiconductor substrate may include a SiGe alloy with a gradient Ge feature in which the Si and Ge composition changes from one ratio at one location to another ratio with location of the feature. In another embodiment, the SiGe alloy is formed over a silicon substrate. In some embodiments, a SiGe alloy may be mechanically strained by another material in contact with the SiGe alloy. In some embodiments, the substrate310may have a multilayer structure, or the substrate310may include a multilayer compound semiconductor structure. It should be noted that some doped regions, isolation structures, and/or other features may be formed within the substrate310.

The substrate310may have a well region311. The well region311may have a relatively small dopant concentration. The well region311may have a first conductive type. In some embodiments, the first conductive type may be an n type or a p type. In some embodiments, n type dopants may include, for example, arsenic (As), phosphorus (P), other group V elements, or any combination thereof. In some embodiments, p type dopants may include, for example, boron (B), other group III elements, or any combination thereof.

The substrate310may have a doped region312. The doped region312may be disposed adjacent to the surface310s1of the substrate310. The doped region312may have the first conductive type. The doped region312may be in contact with the well region311. The doped region312may have a relatively large dopant concentration. The dopant concentration of the doped region312may be greater than that of the well region311.

The doped region313may be disposed adjacent to the surface310s2of the substrate310. The doped region313may have the first conductive type. The doped region313may be in contact with the well region311. The doped region313may have a relatively large dopant concentration. The dopant concentration of the doped region313may be greater than that of the well region311. The well region311may be disposed between the doped regions312and313.

The substrate310may have a doped region314. In some embodiments, the doped region314may be disposed over or within the active region. In some embodiments, the doped region314may continuously extend between the surface310s1and surface310s2of the substrate310. In some embodiments, the doped region314may have a second conductive type different from the first conductive type. The doped region314may have a relatively large dopant concentration. The dopant concentration of the doped region314may be greater than that of the well region311. In some embodiments, the doped region314may be disposed between adjacent unit cells U2. In some embodiments, the doped region314may serve as an isolation feature configured to isolate an electrical path between unit cells U2through the substrate310.

The opening320may penetrate substrate310. In some embodiments, the opening320may be tapered from the surface310s2toward the surface310s1of the substrate310.

The semiconductor device300may include a dielectric layer321. In some embodiments, the dielectric layer321may be disposed on the surface310s1of the substrate310. In some embodiments, the dielectric layer321may cover the doped region314. In some embodiments, the dielectric layer321may vertically overlap the word lines341and342. In some embodiments, the dielectric layer321may define a pattern exposing a portion of the well region311. The dielectric layer321may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

The semiconductor device300may include an isolation layer322. In some embodiments, the isolation layer322may be disposed on the dielectric layer321. In some embodiments, the isolation layer322may be disposed within the opening320defined by the substrate310. In some embodiments, the isolation layer322may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, a trench may be defined by the substrate310and the isolation layer322. The word lines341and342are located within the same trench.

The semiconductor device300may include a dielectric layer323. In some embodiments, the dielectric layer323may be disposed on the surface310s2of the substrate310. In some embodiments, the dielectric layer323may cover the word lines341and342. The dielectric layer323may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

In some embodiments, the bit line330may be disposed on the dielectric layer321. In some embodiments, the bit line330may be disposed on the surface310s1of the substrate310. The bit line330may include conductive materials, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof.

The semiconductor device300may include a conductive via332. In some embodiments, the conductive via332may fill the openings defined by the dielectric layer321. The conductive via332may extend between the surface310s1of the substrate310and the bit line330. The conductive via332may include conductive materials, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof.

In some embodiments, each of the word lines341and342may be disposed within the opening320defined by the substrate310. In some embodiments, each of the word lines341and342may be disposed within the trench defined by the substrate310and the isolation layer322. In some embodiments, each of the word lines341and342may cover the isolation layer322. In some embodiments, each of the word lines341and342may be at least partially tapered along a direction from the surface310s2toward the surface310s1of the substrate310. In some embodiments, each of the word lines341and342may be spaced apart from the bit line330by the dielectric layer321and the isolation layer322. The word lines341and342may include conductive materials, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof. In some embodiments, the word lines341and342may include a semiconductor material, such as polysilicon. The word line341may have a surface341s1(or a top surface). In some embodiments, the surface341s1of the word line341may be exposed from the substrate310. In some embodiments, the surface341s1of the word line341may be substantially coplanar with the surface310s2of the substrate310. In some embodiments, the word line341may be spaced apart from the word line342by the isolation layer322.

The semiconductor device300may include a gate dielectric layer351and a gate dielectric layer352. In some embodiments, the gate dielectric layer351may be disposed within the opening320defined by the substrate310. In some embodiments, the gate dielectric layer351may be disposed at a side341e1of the word line341. In some embodiments, a top surface (not annotated) of the gate dielectric layer351may be substantially coplanar with the surface310s2of the substrate310. In some embodiments, the top surface of the gate dielectric layer351may be substantially coplanar with the surface341s1of the word line341. In some embodiments, the gate dielectric layer351may be in contact with the isolation layer322. The bottom of the gate dielectric layer351may be connected to the isolation layer322. In some embodiments, the word line341may be spaced apart from the substrate310by the gate dielectric layer351.

In some embodiments, the gate dielectric layer352may be disposed within the opening320defined by the substrate310. In some embodiments, the gate dielectric layer352may be disposed at a side342e1of the word line342. In some embodiments, a top surface (not annotated) of the gate dielectric layer352may be substantially coplanar with the surface310s2of the substrate310. The word line342may be spaced apart from the substrate310by the gate dielectric layer352. In some embodiments, the top surface of the gate dielectric layer152may be substantially coplanar with the surface341s1of the word line341. The bottom of the gate dielectric layer352may be connected to the isolation layer322. In some embodiments, the gate dielectric layer351may be nonparallel to the gate dielectric layer352. Each of the gate dielectric layers351and352may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, each of the gate dielectric layers351and352may include a high-k dielectric material(s). The high-k dielectric material may have a dielectric constant (k value) exceeding 4. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), yttrium oxide (Y2O3), aluminum oxide (Al2O3), titanium oxide (TiO2) or another applicable material.

In some embodiments, the substrate310may define a channel311c1abutting the gate dielectric layer351. In some embodiments, the substrate310may define a channel311c2abutting the gate dielectric layer352. In some embodiments, the substrate310, the bit line330, and the word line341may define a transistor Z3. In some embodiments, the substrate310, the bit line330, and the word line342may define a transistor Z4. The doped regions312and313may serve as a source/drain feature. In some embodiments, the transistors Z3and Z4may at least partially located within the same opening320defined by the substrate310.

The conductive via361may be disposed on the surface310s2of the substrate310. The conductive via361may be disposed within the dielectric layer323. The conductive via361may be electrically connected to the doped region313.

The conductive via362may be disposed on the surface310s2of the substrate310. The conductive via362may be disposed within the dielectric layer323. The conductive via362may be electrically connected to the doped region314.

The conductive via363may penetrate the substrate310. The conductive via363may penetrate the dielectric layer323. The conductive via363may be electrically connected to the bit line330. In some embodiments, each of the conductive vias361,362, and363may include conductive materials, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof.

In some embodiments, the capacitors371and372may be disposed on the surface310s2of the substrate310. The capacitors371and372may be disposed on the dielectric layer323. In some embodiments, the capacitors371and/or372may be electrically connected to the conductive via361. The capacitor371may cover the word line341. The capacitor372may cover the word line342. In some embodiments, the capacitor371may be electrically connected to the transistor Z3. In some embodiments, the capacitor372may be electrically connected to the transistor Z4. In some embodiments, each of the capacitors371and372may include a capacitor dielectric layer and two capacitor electrodes. The capacitor dielectric layer may include hafnium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, aluminum oxide, titanium oxide or another applicable material. The capacitor electrode may include conductive materials, such as tungsten, copper, aluminum, tantalum, molybdenum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof.

The semiconductor device300may include a conductive trace381. The conductive trace381may be disposed on the conductive via362. The conductive trace381may be electrically connected to the conductive via362.

The semiconductor device300may include a conductive trace382. The conductive trace382may be disposed on the conductive via363. The conductive trace382may be electrically connected to the conductive via363. Each of the conductive traces381and382may include conductive materials, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof.

As shown inFIG.23C, the semiconductor device300may include a fill layer324. In some embodiments, the fill layer324may be disposed on the surface310s1of the substrate310. The fill layer324may be disposed on the dielectric layer321. The fill layer324may have a surface324s1(or a bottom surface). In some embodiments, the surface324s1of the fill layer324may be substantially coplanar with a surface330s1(or a bottom surface), as shown inFIG.23B, of the bit line330.

In some embodiments, the fill layer324and the bit line330may be collectively configured to define a hybrid bonding structure. The hybrid bonding structure may be bonded to other devices (not shown), such as a wafer, a redistribution structure, or other suitable devices.

Each of the conductive vias364and365may penetrate the dielectric layer323. The conductive via364may be electrically connected to the word line341. The conductive via365may be electrically connected to the word line342.

The semiconductor device300may include conductive traces383and384. The conductive trace383may be disposed on the conductive via364. The conductive trace383may be electrically connected to the conductive via364. The conductive trace384may be disposed on the conductive via365. The conductive trace384may be electrically connected to the conductive via365.

In this embodiments, the word lines341and342are buried within the substrate310. The bit line330and the capacitors (e.g.,371and372) are disposed on two opposite sides of the substrate310. Each units U2of the semiconductor device300includes two transistors and two capacitors, which enhances the density of transistors per cell. In comparison with conventional semiconductor devices, the semiconductor device300of the present disclosure has a better performance.

FIG.24is a flowchart illustrating a method400of manufacturing a semiconductor device, in accordance with some embodiments of the present disclosure.

The method400begins with operation401in which a substrate is provided. The substrate has a bottom surface and a top surface. The substrate may have a well region with a first conductive type. A first doped region with the first conductive type may be formed adjacent to the top surface of the substrate. A trench may be formed and recessed from the top surface of the substrate.

The method400continues with operation402in which a peripheral portion of an isolation layer within the trench may be removed. A first gate dielectric layer and a second gate dielectric layer may be formed on two opposite sidewalls of the trench.

The method400continues with operation403in which a first word line and a second word line may be formed within the trench.

The method400continues with operation404in which the bottom surface of the substrate may be polished or grinded. The bottom of the isolation feature is exposed.

The method400continues with operation405in which a second doped region with the first conductive type may be formed adjacent to the bottom surface of the substrate.

The method400continues with operation406in which a third doped region with a second conductive type may be formed between the top surface and the bottom surface of the substrate.

The method400continues with operation407in which a bit line may be formed on the bottom surface of the substrate.

The method400continues with operation408in which a first capacitor and a second capacitor may be formed on the top surface of the substrate

The method400is merely an example, and is not intended to limit the present disclosure beyond what is explicitly recited in the claims. Additional operations can be provided before, during, or after each operation of the method400, and some operations described can be replaced, eliminated, or reordered for additional embodiments of the method. In some embodiments, the method400can include further operations not depicted inFIG.24. In some embodiments, the method400can include one or more operations depicted inFIG.24.

Referring toFIG.25A,FIG.25B, andFIG.25C, a substrate310may be provided. The substrate310may have a well region311therein. A doped region313may be formed adjacent to the surface310s2of the substrate310. A plurality of openings320(or trenches) may be formed. The opening320may be recessed from the surface310s2of the substrate310. An isolation layer322′ may be formed within the opening320. The isolation layer322′ may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

Referring toFIG.26A,FIG.26B, andFIG.26C, a pattern391may be formed on the isolation layer322′. The pattern391may serve as a mask configured to define an etched portion during an etch process. The pattern391may be formed on a center portion (not annotated) of the isolation layer322′. An etching process may be performed to remove a peripheral portion of the isolation layer322′. The isolation layer322′ may be removed by, for example, a wet etching. An isolation layer322may be defined within the opening320. Openings322o(or trench) may be formed. The opening322omay be recessed from the surface310s2of the substrate310.

Referring toFIG.27A,FIG.27B, andFIG.27C, the pattern391may be removed. A gate dielectric layer351, a gate dielectric layer352, and a dielectric layer353may be formed. The dielectric layer353may be connected to the gate dielectric layers351and352. The gate dielectric layers351and352may be formed within the sidewall (not annotated) of the opening320and on the isolation layer322. The dielectric layer353may be formed on the surface310s2of the substrate310. The gate dielectric layer351, gate dielectric layer352, and dielectric layer353may include silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric material(s). The gate dielectric layer351, gate dielectric layer352, and dielectric layer353may be formed by, for example, PVD, CVD, ALD, LPCVD, PECVD, or other suitable processes.

Referring toFIG.28A,FIG.28B, andFIG.28C, the dielectric layer353may be removed. The dielectric layer353may be removed by, for example, chemical mechanical polishing process, grinding process, etching process, or other suitable processes.

Referring toFIG.29A,FIG.29B, andFIG.29C, word lines341and342may be formed within the opening320. The word lines341and342may fill the openings3220.The word line341may be formed on the gate dielectric layer351. The word line342may be formed on the gate dielectric layer352. The word lines341and342may be formed by PVD, CVD, ALD, LPCVD, PECVD, or other suitable processes.

Referring toFIG.30A,FIG.30B, andFIG.30C, the surface310s2of the substrate310may be attached to a supporter392. The supporter392may include a plastic supporter, a glass supporter, a ceramic supporter, or other suitable supporters.

Referring toFIG.31A,FIG.31B, andFIG.31C, a portion of the substrate310may be removed. In some embodiments, the surface310s1of the substrate310may be grinded or polished by chemical mechanical polishing process, grinding process, or other suitable processes. The bottom of the isolation layer322may be exposed from the surface310s1of the substrate310. A doped region312may be formed adjacent to the surface310s1of the substrate310.

Referring toFIG.32A,FIG.32C, andFIG.32C, a pattern393may be formed on the surface310s1of the substrate310to define a pattern of a doped region314. The doped region314may be formed within the substrate310. The doped region314may have a conductive type different from that of the doped region312(or313).

Referring toFIG.33A,FIG.33C, andFIG.33C, the pattern393may be removed. A dielectric layer321′ may be formed on the surface310s1of the substrate310. The dielectric layer321′ may include silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric material(s).

Referring toFIG.34A,FIG.34B, andFIG.34C, the dielectric layer321′ may be patterned to form the dielectric layer321. The dielectric layer321may have openings321oexposing the surface310s1of the substrate310. The doped region314may be covered by the dielectric layer321.

Referring toFIG.35A,FIG.35B, andFIG.35C, a metallization layer330′ may be formed on the surface310s1of the substrate310. The metallization layer330′ may fill the openings3210as shown inFIG.35B. The metallization layer330′ may include conductive materials, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, the like, and/or a combination thereof. The metallization layer330′ may be formed by PVD, CVD, ALD, LPCVD, PECVD, or other suitable processes.

Referring toFIG.36A,FIG.36B, andFIG.36C, the metallization layer330′ may be patterned to form bit lines330and conductive via332over the active region. In some embodiments, the bit line330may be protruded from the dielectric layer321. The metallization layer330′ may be patterned by wet etching, dry etching, or other suitable processes.

Referring toFIG.37A,FIG.37B, andFIG.37C, a fill layer324may be formed. The fill layer324may cover the dielectric layer321. The fill layer324may cover the bit line330. The fill layer324may fill openings defined by the bit line330. The fill layer324may be formed by CVD, ALD, LPCVD, PECVD, PVD, or other suitable processes.

Referring toFIG.38A,FIG.38B, andFIG.38C, a portion of the fill layer324may be removed. The surface324s1of the fill layer324may be coplanar with the surface330s1of the bit line330. The fill layer324may be removed by, for example, CVD, grinding, or other suitable processes.

Referring toFIG.39A,FIG.39B, andFIG.39C, the supporter392may be removed. The word lines341and342may be exposed. The bit line330and the fill layer324may be attached to a supporter394. The supporter394may include a glass supporter, a ceramic supporter, or other suitable supporters.

Referring toFIG.40A,FIG.40B, andFIG.40C, a dielectric layer323may be formed on the word line341. The dielectric layer323may be formed on the surface310s2of the substrate310. The dielectric layer323may be formed by CVD, ALD, LPCVD, PECVD, PVD, or other suitable processes.

Referring toFIG.41A,FIG.41B, andFIG.41C, conductive vias361,362,364, and365may be formed. Conductive traces381,383and384may be formed. The dielectric layer323may be patterned to define openings, a conductive layer may be formed on the dielectric layer323and fill the openings, and the conductive layer may be patterned to form the conductive vias361,362,364, and365as well as the conductive traces381,383and384.

Referring toFIG.42A,FIG.42B, andFIG.42C, capacitors371and372may be formed on the dielectric layer323. The capacitor371may be electrically connected to or coupled the word line341. The capacitor372may be electrically connected to or coupled to the word line342.

Referring toFIG.43A,FIG.43B, andFIG.43C, a conductive via363and a conductive trace382may be formed. In some embodiments, an etching process, such as dry etching, may be performed to form an opening penetrating the dielectric layer323and the substrate310to expose the bit line330, a conductive layer may be formed on the dielectric layer323and fill the openings, and the conductive layer may be patterned to form the conductive via363and the conductive trace382.

Referring toFIG.44A,FIG.44B, andFIG.44C, the supporter394may be removed. As a result, a semiconductor device, such as the semiconductor device300as shown inFIG.23A,FIG.23B, andFIG.23C, may be produced. The fill layer324and bit line330may collectively define a hybrid bonding structure so that the semiconductor device300may be bonded to another device.

One aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first word line, a bit line, and a first capacitor. The substrate has a first surface and a second surface opposite to the first surface. The first word line is disposed within the substrate. The bit line is disposed on the first surface of the substrate. The first capacitor is disposed on the second surface of the substrate.

Another aspect of the present disclosure provides a semiconductor device. The semiconductor device includes a substrate, a first word line, a bit line and an isolation layer. The substrate has a first surface and a second surface opposite to the first surface. The first word line is embedded within the substrate and exposed from the second surface of the substrate. The first word line is exposed from the second surface of the substrate. The bit line is disposed on the first surface of the substrate. The isolation layer is covered by the first word line. The first word line is spaced apart from the bit line by the isolation layer.

Another aspect of the present disclosure provides a method for manufacturing a semiconductor device. The method includes: providing a substrate having a first surface and a second surface opposite to the first surface; forming a word line within the substrate; forming a bit line on the first surface of the substrate; and forming a first capacitor on the second surface of the substrate.

The embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a substrate, a word line, a bit line, and a capacitor. The word line is buried within the trench of the substrate. The bit line and the capacitor are disposed on two opposite sides of the substrate. Each units of the semiconductor device can define two transistors and a capacitor, which enhances the driving current. Further, the word line can function as a common switch to turn and/or turn off two transistors, which reduces the size of the semiconductor device. In comparison with conventional semiconductor devices, the semiconductor device of the present disclosure has a better performance.

Although the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above may be implemented in different methodologies and replaced by other processes, or a combination thereof.