Reception apparatus using spread spectrum communication scheme

In a reception apparatus, a matched filter that has conventionally been arranged in a searcher unit is mounted on an acquisition unit together with a large scale memory. The large scale memory once stores reception chip signals, and thereafter outputs them to the matched filter and to the delay profile calculation unit. A setting register receives an acquisition signal and outputs it to the matched filter. The matched filter performs acquisition of the reception chip signals outputted from the large scale memory, and outputs a despread timing signal to a despread circuit, a code generation circuit and the delay profile calculation unit.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a reception apparatus, and more particularly, to a reception apparatus using a spread spectrum communication scheme.

2. Description of the Background Art

Recently, in the field of mobile communication and the like, a spread spectrum communication scheme is receiving attention. Generally, a demodulation unit of a conventional reception apparatus using the spread spectrum communication scheme is roughly divided into three blocks of a searcher unit, a spread spectrum demodulation unit, and a decode unit. The searcher unit searches the channel and the path of a reception signal. The spread spectrum demodulation unit despreads the spectrum of the reception signal and performs phase correction and rake combination of the reception signal. The decode unit performs viterbi error correction and the like of the reception signal subjected to the rake combination.

The conventional spread spectrum demodulation unit receives a despread timing signal from the searcher unit, and demodulates the reception signal according to this despread timing signal. The conventional searcher unit generally uses, as acquisition means, a matched filter. Since the conventional matched filter receives data being passed as it is, it is capable of performing an acquisition at that time point, but not capable of detecting an acquisition point before and after that time point. Additionally, the conventional spread spectrum demodulation unit has many operation demodulation units that correspond to respective paths and that is referred to as fingers so as to improve accuracy of rake combination.

A conventional reception apparatus disclosed in Japanese Patent Laying-Open No. 10-209919, when combining a demodulation output of each path by a data combiner, stores the demodulation output of each finger in a memory with a value of PN (Pseudorandom Noise) phase counter indicative of the phase of PN code of each finger set as a write address, and reads data of each memory with a common read address.

A conventional matched filter and CDMA (Code Division Multiple Access) reception apparatus disclosed in Japanese Patent Laying-Open No. 2000-307471 obtains correlation values generated among a plurality of signals arrived through multipath and chip delay information of the plurality of signals behind a reference reception timing signal surely and easily without increasing the circuit scale, and performs a rake combination process, monitoring of a delay profile and other operations.

The conventional reception apparatuses each demodulate a reception signal according to a despread timing signal from the searcher unit. Accordingly, there has been a problem that the searcher unit that occupies a circuit area is essential. Further, the matched filter used in the conventional searcher unit is not capable of detecting an acquisition point before and after the time point at which data is passed. Therefore, acquisition has been required to be repeated every time an instantaneous interrupt of synchronization occurs, and therefore time has been required. Still further, as the conventional reception apparatuses each require many finger operation units, there has been a problem that the circuit scale is increased.

Though the conventional reception apparatuses disclosed in the aforementioned patent documents may be certain means for solving part of the aforementioned problems, means for solving such problems are not limited to the means disclosed in the patent documents.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a reception apparatus that is capable of reducing the circuit scale and the time required for acquisition.

The present invention is directed to a reception apparatus using a spread spectrum communication scheme, including: an input process unit wirelessly processing a reception signal and outputting a reception chip signal for each spread code; an acquisition unit performing an acquisition of the reception chip signal and outputting a timing signal together with the reception chip signal; a spread spectrum demodulation unit receiving the timing signal, performing a demodulation process of the reception chip signal outputted from the acquisition unit, and outputting a combination symbol signal, and an output process unit performing a decode process of the combination symbol signal and outputting audio data. The acquisition unit includes a memory temporarily holding the reception chip signal, and a matched filter detecting in advance a plurality of acquisition points when despreading in the spread spectrum demodulation unit based on an acquisition signal and the reception chip signal temporarily held in the memory.

According to the present invention, the circuit scale and the time required for acquisition can be reduced.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

In the following, embodiments of the present invention will be described in detail referring to the drawings. Throughout the drawings, identical or corresponding parts are denoted by the identical reference characters, and description thereof will not be repeated.

Referring toFIG. 1, in the spread spectrum communication, first, (1) data modulation is performed in a base station. As for the data modulation scheme, for example QPSK (Quadrature Phase Shift Keying) scheme is employed. In QPSK scheme, a transmission pilot symbol signal Sd of binary expression “00” is expressed as (1,1) on IQ coordinates.

Next, in the base station, (2) spread modulation is performed. In the spread spectrum communication, when transmitting certain digital data, N of spread codes generated in time sequence and one transmission data item are multiplied by N times and transmitted for N times. Here, when the value of N is great, the communication rate is reduced; when the value of N is small, the communication rate is increased. In the embodiments of the present invention, the value of N (also referred to as SF (Spreading Factor)) is set as four.

Being processed with “00” spread code, transmission pilot symbol signal Sd becomes a spread chip signal d0of which phase is rotated by 0°. Being processed with “01” spread code, it becomes a spread chip signal d1of which phase is rotated by −90°. Being processed with “10” spread code, it becomes a spread chip signal d2of which phase is rotated by 90°. Being processed with “11” spread code, it becomes a spread chip signal d3of which phase is rotated by 180°.

Thus, spread chip signals d0-d3being subjected to spread modulation are sent out from the base station as radio waves, and thereafter attain (3) space propagation. Spread chip signals d0-d3sent out from the base station as radio waves have their phases changed through fading in space and received as reception chip signals D0-D3at a mobile terminal (a reception apparatus). Reception chip signals D0-D3are slightly different from one another in the reception intensity and the amount of phase rotation even when they are the same in the spread code, depending on the magnitude of fading due to the difference in paths from the base station to the mobile terminal.

Reception chip signals D0-D3are (4) despreaded at the fingers of the mobile terminal. In despreading, reception chip signals D0-D3are each processed with a despread code corresponding to the spread code. Despreaded reception chip signals D0-D3are integrated during one symbol, that is, over four chips, and become a reception pilot symbol signal SP0converged on one point on IQ coordinates.

As shown inFIG. 1, reception pilot symbol signal SP0does not match transmission pilot symbol signal Sd. Specifically, with reception pilot symbol signal SP0, the phase rotation in the space propagation from the base station to the mobile terminal still remains. By comparing transmission pilot symbol signal Sd and reception pilot symbol signal SP0, the deterioration level of signal intensity and the amount of phase rotation due to space propagation can be estimated (channel estimation).

Accordingly, in the finger of the mobile terminal, the amount of phase rotation (channel estimation value) is calculated through (5) channel estimation. In calculating the amount of phase rotation, for example, a correction coefficient is calculated based on the difference between the coordinate where reception pilot symbol signal SP0is rotated by −45° and I axis (√2,0) of IQ coordinates. By correcting the phase rotation remaining with reception pilot symbol signal SP0with the channel estimation value, correction symbol signal S0is calculated.

In the other fingers also, in the similar manner, the correction symbol signals S1-S3are calculated. Correction symbol signals S0-S3thus calculated are subjected to (6) rake combination in the mobile terminal. Correction symbol signals S0-S3become a combination symbol signal SS through the rake combination. The specific configurations and operations of the mobile terminal (reception apparatus) in the spread spectrum communication described above will be described in detail for each of the following embodiments.

First Embodiment

FIG. 2is a schematic block diagram schematically showing a configuration of a reception apparatus1A according to a first embodiment of the present invention.

Referring toFIG. 2, reception apparatus1A of the first embodiment includes an antenna reception unit10, an RF+AD unit20, an AD interpolation circuit30, acquisition unit50A, spread spectrum demodulation unit60A, viterbi error correction circuit80, an audio decoder90, and a speaker unit100. Antenna reception unit10, RF+AD unit20and AD interpolation circuit30are also generally referred to as an input process unit. Viterbi error correction circuit80, audio decoder90and speaker100are also generally referred to as an output process unit.

Acquisition unit50A includes a large scale memory51A, a setting register52and a matched filter53. Spread spectrum demodulation unit60A includes a finger operation unit61, a delay profile calculation unit71, a path control unit72, a path-basis reception vector correction result register73, and a rake combination unit74. Finger operation unit61has a despread circuit62, a code generation circuit63, a correction circuit64, and a channel estimation unit65. Delay profile calculation unit71and path control unit72are also generally referred to as a path calculation process unit.

Reception signal SD received from antenna reception unit10is subjected to an RF (Radio Frequency) process and an AD (Analogue to Digital) conversion in RF+AD unit20, and thereafter outputted to AD interpolation circuit30. AD interpolation circuit30performs interpolation of digital data outputted from RF+AD unit20, and classifies the digital data into reception chip signals D0-D3for each spread code. Reception chip signals D0-D3classified into each spread code are outputted to a large scale memory51A in acquisition unit50A.

Large scale memory51A once stores reception chip signals D0-D3, and thereafter outputs them to matched filter53in acquisition unit50A and to delay profile calculation unit71in spread spectrum demodulation unit60A.

As to the form of large scale memory51A, while the one such as SRAM (Static Random Access Memory) that allows fast data reading and writing is preferable, DRAM (Dynamic Random Access Memory) is acceptable if it does not largely degrade the processing speed of a series of processes. Additionally, while the capacity of large memory51A of at least 64 bits×512 words (1 word equals to 64 bits) is adequate, the capacity as large as possible in an economically tolerable range is desirable, including the chip size or the circuit board size. It should be noted that the form of the large scale memory described above applies as well to the large scale memories in other embodiments.

Setting register52receives an acquisition signal SYN and outputs it to matched filter53. Matched filter53receives acquisition signal SYN and performs the acquisition of reception chip signals D0-D3outputted from large scale memory51A, and outputs a despread timing signal TM to despread circuit62, code generation circuit63and delay profile calculation unit71in spread spectrum modulation unit60A.

As above, in reception apparatus1A according to the first embodiment shown inFIG. 2, matched filter53that has conventionally been arranged in a searcher unit is mounted on acquisition unit50A together with large scale memory51A. Thus, it is not necessary to receive despread timing signal TM from a searcher unit any more, resulting in reduction of the circuit scale.

Additionally, matched filter53becomes capable of detecting in advance a plurality of acquisition points when despreading, based on acquisition signal SYN and reception chip signals D0-D3once stored in large scale memory51A. Thus, even when an instantaneous loss of synchronization occurs, deterioration in data quality in the spread spectrum communication can be avoided. Further, since reception chip signals D0-D3are once stored in large scale memory51A, despreading, channel estimation, and correction process described in the following can be performed at once at a high rate.

Code generation circuit63receives despread timing signal TM and outputs despread code PN to despread circuit62. Delay profile calculation unit71receives despread timing signal TM and performs sequencing in accordance with the reception intensity or the like of reception chip signals D0-D3, and outputs the result as a delay signal DLY to despread circuit62, channel estimation unit65and path control unit72. Path control unit72receives delay signal DLY and outputs an output timing signal EN and a combination timing signal CP.

Output timing signal EN controls the output timing of the symbol integration in finger operation unit61. Combination timing signal CP controls the rake combination timing of correction symbol signals S0-S3. Despread circuit62receives despread timing signal TM, despread code PN and delay signal DLY, despreads reception chip signals D0-D3, and outputs reception symbol signals SP0-SP3for each despreaded path to correction circuit64and channel estimation unit65. A specific circuit configuration of despread circuit62is described in the following.

FIG. 3is a circuit diagram showing a specific circuit configuration of despread circuit62according to the first embodiment of the present invention.

Among reception chip signals D0-D3outputted from large scale memory51A shown inFIG. 2, I component is expressed as D_I [7:0], and Q component is expressed as D_Q [7:0]. Among despread codes PN outputted from code generation circuit63shown inFIG. 2, I component is expressed as PN_I (for example, 15.36 MHz), and Q component is expressed as PN_Q (for example, 15.36 MHz). XOR circuit620receives despread codes PN_I, PN_Q and outputs multiplexing reference signal REF (for example, 15.36 MHz).

Multiplication operation circuit611receives reception chip signals D_I [7:0], D_Q [7:0] and outputs a signal according to multiplexing reference signal REF. Inverter612inverts a signal outputted from multiplication operation circuit611. Multiplication operation circuit613receives the signal outputted from multiplication operation circuit611and the inversion signal thereof, and outputs a signal according to despread code PN_Q to 12-bit full adder650.

Integration operation circuit631receives a signal outputted from 12-bit full adder650and outputs four signals according to a select signal SEL. Select signal SEL is a signal for switching two multiplexing operations of four-chip integrators630,635, and determined according to delay signal DLY outputted from delay profile calculation unit71and the like. Integration operation circuit632receives four signals outputted from integration operation circuit631and outputs four signals according to despread timing signal TM (for example, 15.36 MHz). Integration operation circuit633receives four signals outputted from integration operation circuit632and outputs a signal according to select signal SEL.

AND circuit640receives an inversion signal of a clear clock signal CLR and a signal outputted from integration operation circuit633, and outputs a signal to 12-bit full adder650. Clear clock signal CLR resets a symbol integration result integrated by four-chip integrators630,635.

12-bit full adder650receives a signal outputted from multiplication operation circuit613and AND circuit640, and outputs a signal according to despread code PN_Q to integration operation circuit631and flip-flop circuit660. 12-bit full adder650adds input data of chip unit and symbolize it. Flip-flop circuit660receives a signal outputted from 12-bit full adder650and outputs I component SP_I [11:0] of a reception symbol signal according to despread timing signal TM and output enable signal EN.

Multiplication operation circuit614receives reception chip signals D_I [7:0], D_Q [7:0] and outputs a signal according to multiplexing reference signal REF. Inverter615inverts a signal outputted from multiplication operation circuit614. Multiplication operation circuit616receives the signal outputted from multiplication operation circuit614and the inversion signal thereof, and outputs a signal according to despread code PN_I to 12-bit full adder651.

Integration operation circuit636receives a signal outputted from 12-bit full adder651and outputs four signals according to select signal SEL. Integration operation circuit637receives four signals outputted from integration operation circuit636and outputs four signals according to despread timing signal TM (for example, 15.36 MHz). Integration operation circuit638receives four signals outputted from integration operation circuit637and outputs a signal according to select signal SEL.

AND circuit641receives an inversion signal of clear clock signal CLR and a signal outputted from integration operation circuit638, and outputs a signal to 12-bit full adder651. 12-bit full adder651receives a signal outputted from multiplication operation circuit616and AND circuit641, and outputs a signal according to despread code PN_I to integration operation circuit636and flip-flop circuit661. Flip-flop circuit661receives a signal outputted from 12-bit full adder651and outputs Q component SP_Q [11:0] of a reception symbol signal according to despread timing signal TM and output enable signal EN.

Referring back toFIG. 2, channel estimation unit65receives reception symbol signals SP0-SP3and delay signal DLY, performs the channel estimation of reception symbol signals SP0-SP3, and outputs correction coefficients K0-K3to correction circuit64. Correction circuit64receives correction coefficients K0-K3, corrects phase rotation of reception symbol signals SP0-SP3due to fading, and outputs correction symbol signals S0-S3to path-basis reception vector correction result resistor73. Path-basis reception vector correction result resistor73outputs correction symbol signals S0-S3to rake combination unit74according to combination timing signal CP.

Rake combination unit74performs the rake combination of correction symbol signals S0-S3, and outputs combination symbol signal SS to viterbi error correction circuit80. As above, by combining large scale memory51A and finger operation unit61, the demodulation process that is not dependent on the reception rate of reception signal SD received from antenna reception unit10is realized.

Viterbi error correction circuit80(decode unit) performs a viterbi error correction of combination symbol signal SS. Audio decoder90decodes a signal outputted from viterbi error correction circuit80to an audio signal or the like. The signal decoded to an audio signal is outputted from speaker unit100as audio data.

FIG. 4is an operation waveform diagram for describing a circuit operation of reception apparatus1A of the first embodiment of the present invention.

Referring toFIG. 4, reception chip signals D0-D3outputted from AD interpolation circuit30shown inFIG. 2are successively written to large scale memory51A shown inFIG. 2with chip intervals of D00, D01. . . . As described referring toFIG. 1, reception chip signals D0-D3are slightly different from one another in the reception intensity and the amount of phase rotation even when they are the same in the spread code, depending on the magnitude of fading due to the difference in paths from the base station to the mobile terminal. This will be described referring toFIG. 5.

FIG. 5is an operation waveform diagram showing how reception chip signals D0-D3are written to a large scale memory51A depending on the difference in paths.

Referring toFIG. 5, reception chip signal group P1indicates signals that are received through a first path (path1). Reception chip signal group P2indicates signals that are received through a second path (path2). Reception chip signal group P3indicates signals that are received through a third path (path3). Reception chip signal group P4indicates signals that are received through a fourth path (path4).

In reception chip signal group P1, reception chip signal D3P1is a signal subjected to a spread code of 180° rotation. Reception chip signal D2P1is a signal subjected to a spread code of −90° rotation. Reception chip signal D1P1is a signal subjected to a spread code of +90° rotation. Reception chip signal D0P1is a signal subjected to a spread code of 0° rotation. The other reception signal groups P2-P4are similarly coded.

Referring toFIG. 5, at time point t1, reception chip signal D3P1is written to large scale memory51A. At time point t2, reception chip signal D3P2is written to large scale memory51A. At time point t3, reception chip signal D3P4is written to large scale memory51A. At time point t5, reception chip signal D3P3is written to large scale memory51A. Thus, with respect to reception chip signals subjected to the same spread code of 180° rotation, the distance of the path is increased in the order of path1, path2, path4, path3, by which arrival to reception apparatus1A is delayed. This applies as well to other reception chip signals subjected to other spread codes.

Next, from the viewpoint of the reception intensity, as reception chip signal D3P1arrives at reception apparatus1A through the shortest path, it is assumed that the signal arrives as a direct wave. On the other hand, reception chip signals D3P2-D3P4do not arrive at reception apparatus1A through the shortest path, it is assumed that the signals arrive as reflected waves. As compared to the direct wave, in the reflected waves, the signals received are weak and the amounts of phase rotation are different slightly from one another. Referring toFIG. 1, reception chip signals D0-D3on IQ coordinates after (3) space propagation indicate this state (referred to as constellation).

In finger operation unit61shown inFIG. 2, first, reception chip signals D0P1-D0P4subjected to spread code of 0° rotation are successively read in the order of arrival at reception apparatus1A to be subjected to despreading, channel estimation and correction process. Next, reception chip signals D1P1-D1P4subjected to spread code of +90° rotation are successively read in the order of arrival at reception apparatus1A to be subjected to despreading, channel estimation and correction process. Next, reception chip signals D2P1-D2P4subjected to spread code of −90° rotation are successively read in the order of arrival at reception apparatus1A to be subjected to despreading, channel estimation and correction process. Next, reception chip signals D3P1-D3P4subjected to spread code of 180° rotation are successively read in the order of arrival at reception apparatus1A to be subjected to despreading, channel estimation and correction process. The operation processes in the finger operation unit such as despreading, channel estimation and correction process are also generally referred to as a finger operation process.

Referring back toFIG. 4, reception chip signals D0-D3are once stored in matched filter53shown inFIG. 2, and thereafter in despread circuit62shown inFIG. 2, they are despreaded by despread codes PN outputted from code generation circuit63shown inFIG. 2. The despreaded reception chip signals (D0-D3)×PN are integrated during one symbol, over four chips, and outputted from despread circuit62as reception chip signals SP0-SP3for each path.

Reception symbol signals SP0-SP3are inputted to channel estimation unit65and correction circuit64shown inFIG. 2. Channel estimation unit65rotates reception symbol signals SP0-SP3by −45° and subsequently integrates them during two symbols, and measures a deviation from I axis in IQ coordinates and a distortion amount. Thus calculated correction coefficients K0-K3are updated by two symbol intervals, and outputted to correction circuit64. Correction circuit64receives correction coefficients K0-K3, and corrects the amount of phase rotation of reception symbol signals SP0-SP3by complex operation, and outputs correct symbol signals S0-S3.

Correct symbol signals S0-S3are once held in path-basis reception vector correction result resister73shown inFIG. 2, and thereafter they are subjected to the rake combination to be combination symbol signal SS in rake combination unit74shown inFIG. 2. Thus, by the rake combination of correction symbol signals S0-S3, the signal value intensity of combination symbol signal SS is enhanced.

As above, according to the first embodiment, matched filter53that has conventionally been arranged in a searcher unit is mounted on acquisition unit50A together with large scale memory51A, whereby the circuit scale and the time require for acquisition can be reduced.

Second Embodiment

FIG. 6is a schematic block diagram schematically showing a configuration of a reception apparatus1B according to a second embodiment of the present invention.

Referring toFIG. 6, reception apparatus1B according to the second embodiment is different from reception apparatus1A according to the first embodiment in that acquisition unit50A is replaced by an acquisition unit50B, and spread spectrum demodulation unit60A is replaced by a spread spectrum demodulation unit60B.

Acquisition unit50B is different from acquisition unit50A according to the first embodiment only in that large scale memory51A is replaced by a large scale memory51B. Accordingly, description of the common parts is not repeated herein. Spread spectrum demodulation unit60B is different from spread spectrum demodulation unit60A according to the first embodiment only in that finger operation unit61is replaced by finger operation units61a-61d. Accordingly, description of the common parts is not repeated herein.

The circuit configuration of each of finger operation units61a-61dis the same as that of finger operation unit61of the first embodiment. Accordingly, in order to save space, the circuit configuration of each of finger operation units61a-61dis not shown inFIG. 6.

Finger operation unit61according to the first embodiment sequentially processes all reception chip signals D0-D3subjected to different spread codes in time sequence (time division multiplexing). On the other hand, according to the second embodiment, reception signals D0-D3are processed by different finger operation units61a-61dfor each path through which the signals are arriving at reception apparatus1B.

Specifically, finger operation unit61aprocesses reception chip signals D0-D3received through a first path (path1). Finger operation unit61bprocesses reception chip signals D0-D3received through a second path (path2). Finger operation unit61cprocesses reception chip signals D0-D3received through a third path (path3). Finger operation unit61dprocesses reception chip signals D0-D3received through a fourth path (path4).

Thus, by processing reception chip signals D0-D3by different finger operation units61a-61dfor each path through which the signals are arriving at reception apparatus1B, spread spectrum demodulation unit60B can attain fast parallel operations of despreading, channel estimation and correction process of reception chip signals D0-D3. When the number of finger operation units is set as four as finger operation units61a-61dof the second embodiment, the aforementioned processing speed is approximately quadrupled. It should be noted that the number of finger operation units61a-61dcan be changed freely in accordance with the number of expected paths.

Path-basis reception vector correction result register73receives reception symbol signals SP0-SP3for each path outputted from respective finger operation units61a-61d, and outputs correction symbol signals S0-S3to rake combination unit74in accordance with combination timing signal CP. Rake combination unit74performs the rake combination of correction symbol signals S0-S3, and outputs combination symbol signal SS to large scale memory51B.

The processing speed of spread spectrum demodulation unit60B is approximately quadrupled as compared to the first embodiment. Accordingly, the demodulation rate of spread spectrum demodulation unit60B is approximately four times as fast as the reception rate of reception signal SD received at antenna reception unit10. As a result, combination symbol signal SS outputted from rake combination unit74becomes an intermittent signal.

Accordingly, large scale memory51B of the second embodiment once stores reception chip signals D0-D3and temporarily holds combination symbol signal SS. Large scale memory51B receives reception rate signal RT outputted from RF+AD unit20and restores the held combination symbol signal SS to the reception rate of reception signal SD, and outputs it to viterbi error correction circuit80.

Thus, through large scale memory51B, by restoring combination symbol signal SS from the modulation rate of spread spectrum demodulation unit60B to the reception rate of reception signal SD, the imbalance between the modulation rate and the reception rate can be adjusted.

FIG. 7is an operation waveform diagram for describing a circuit operation of the reception apparatus1B according to the second embodiment of the present invention.

Referring toFIG. 7, reception chip signals D0-D3outputted from AD interpolation circuit30shown inFIG. 6are sequentially written to large scale memory51B shown inFIG. 6with chip intervals of D0, D1, . . . . The chip intervals D0, D1, . . . of reception signals are longer as compared to the first embodiment. It means that the operation numbers of despreading in one chip time is quadrupled as compared to the first embodiment.

Reception chip signals D0-D3are once stored in matched filter53shown inFIG. 6, and thereafter each outputted to despread circuits62a-62dshown inFIG. 6(only despread circuit62ais shown) for each different spread code. Reception chip signals D0-D3each outputted to despread circuits62a-62dare despreaded by despread codes PN each outputted from code generation circuits63a-63dshown inFIG. 6(only code generation circuit63ais shown). The despreaded reception chip signals (D0-D3)×PN are integrated during one symbol, over four chips, and thereafter respectively outputted from despread circuits62a-62das reception symbol signals SP0-SP3for each path.

Channel estimation units65a-65drespectively rotate reception symbol signals SP0-SP3by −45° and thereafter integrate them during two symbols, and measure a deviation from I axis in IQ coordinates and a distortion amount. Thus calculated correction coefficients K0-K3are updated by two symbol intervals, and respectively outputted to correction circuits64a-64d. Correction circuits64a-64dreceive correction coefficients K0-K3and correct the amount of phase rotation of reception symbol signals SP0-SP3by complex operation, respectively, and output them to rake combination unit74shown inFIG. 6through path-basis reception vector correction result register73shown inFIG. 6.

Rake combination unit74performs the rake combination of the signals outputted through path-basis reception vector correction result register73(correction symbol signals S0-S3), and outputs combination symbol signal SS to large scale memory51B shown inFIG. 6. Large scale memory5B restores combination symbol signal SS from the demodulation rate to the reception rate in accordance with reception rate signal RT outputted from RF+AD unit20shown inFIG. 6.

As above, according to the second embodiment, by replacing finger operation unit61by finger operation units61a-61dand outputting combination symbol signal SS through large scale memory51B, demodulation process can be made fast without changing the reception rate.

Third Embodiment

FIG. 8is a schematic block diagram schematically showing a configuration of a reception apparatus1C according to a third embodiment of the present invention.

Referring toFIG. 8, reception apparatus1C according to the third embodiment is different from reception apparatus1B according to the second embodiment in that acquisition unit50B is replaced by an acquisition unit50C, and spread spectrum demodulation unit60B is replaced by a spread spectrum demodulation unit60C.

Acquisition unit50C is different from acquisition unit50B according to the second embodiment only in that large scale memory51B is replaced by a large scale memory51C. Accordingly, description of the common parts is not repeated herein. Spread spectrum demodulation unit60C is different from spread spectrum demodulation unit60B according to the second embodiment only in that path-basis reception vector correction result register73is removed. Accordingly, description of the common parts is not repeated herein.

In the third embodiment, correction circuits64a-64doutput correction symbol signals S0-S3having each phase rotation due to fading corrected to large scale memory51C. Path control unit72outputs combination timing signal CP that controls the rake combination timing of correction symbol signals S0-S3to large scale memory51C.

Large scale memory51C once stores reception chip signals D0-D3and temporarily holds correction symbol signals S0-S3respectively outputted from finger operation units61a-61d. Correction symbol signals S0-S3held in large scale memory51C are subjected to adjustment for restoring from the modulation rate to the reception rate or the like in accordance with combination timing signal CP, and thereafter outputted to rake combination unit74. Rake combination unit74performs the rake combination of correction symbol signals S0-S3in accordance with rake combination valid signal R_EN that indicates a valid period of rake combination, and outputs combination symbol signal SS and rake combination valid signal R_EN to viterbi error correction circuit80.

Thus, by removing path-basis reception vector correction result register73and outputting correction symbol signals S0-S3to rake combination unit74through large scale memory51C, imbalance between the modulation rate and the reception rate can be adjusted and the circuit scale can be reduced.

FIG. 9is an operation waveform diagram for describing a circuit operation of reception apparatus1C according to the third embodiment of the present invention.

The despreaded reception chip signals (D0-D3)×PN are integrated during one symbol, over four chips, and thereafter respectively outputted from despread circuits62a-62das reception symbol signals SP0-SP3for each path. Reception symbol signals SP0-SP3are inputted to channel estimation units65a-65d(only channel estimation unit65ais shown) and correction circuits64a-64d(only correction circuit64ais shown) shown inFIG. 8.

Channel estimation units65a-65drespectively rotate reception symbol signals SP0-SP3by −45° and thereafter integrate them during two symbols, and measure a deviation from I axis in IQ coordinates and a distortion amount. Thus calculated correction coefficients K0-K3are updated by two symbol intervals, and respectively outputted to correction circuits64a-64d. Correction circuits64a-64dreceive correction coefficients K0-K3and correct the amount of phase rotation of reception symbol signals SP0-SP3by complex operation, respectively, and output correct symbol signals S0-S3to large scale memory51C shown inFIG. 8.

Large scale memory51C performs adjustment or the like for restoring correction symbol signals S0-S3from the demodulation rate to the reception rate in accordance with combination timing signal CP, and thereafter outputs them to rake combination unit74shown inFIG. 8. Rake combination unit74performs the rake combination of correction symbol signals S0-S3in accordance with rake combination valid signal R_EN that indicates a valid period of rake combination, and outputs combination symbol signal SS. Combination symbols signal SS is outputted together with rake combination valid signal R_EN, and differentiated from a signal in an invalid period (time points t34-t37) of combination symbol signal SS.

As above, according to the third embodiment, by removing path-basis reception vector correction result register73and outputting correction symbol signals S0-S3to rake combination unit74through large scale memory51C, imbalance between the modulation rate and the reception rate can be adjusted and the circuit scale can be reduced.

Fourth Embodiment

FIG. 10is a schematic block diagram schematically showing a configuration of a reception apparatus1D according to a fourth embodiment of the present invention.

Referring toFIG. 10, reception apparatus1D according to the fourth embodiment is different from reception apparatus1C according to the third embodiment in that acquisition unit50C is replaced by an acquisition unit50D, and spread spectrum demodulation unit60C is replaced by a spread spectrum demodulation unit60D.

Acquisition unit50D is different from acquisition unit50C according to the third embodiment only in that large scale memory51C is replaced by a large scale memory51D. Accordingly, description of the common parts is not repeated herein. Spread spectrum demodulation unit60D is different from spread spectrum demodulation unit60C according to the third embodiment only in that finger operation units61a-61dare replaced by finger operation unit61as in the first embodiment. Accordingly, description of the common parts is not repeated herein.

In the fourth embodiment, correction circuit64of finger operation unit61outputs correction symbol signals S0-S3having each phase rotation due to fading corrected to large scale memory51D. Path control unit72outputs combination timing signal CP that controls the rake combination timing of correction symbol signals S0-S3to large scale memory51D.

Large scale memory51D once stores reception chip signals D0-D3and temporarily holds correction symbol signals S0-S3outputted from finger operation unit61. Correction symbol signals S0-S3held in large scale memory51D are outputted to rake combination unit74in accordance with combination timing signal CP. Rake combination unit74performs the rake combination of correction symbol signals S0-S3in accordance with rake combination valid signal R_EN that indicates a valid period of rake combination, and outputs combination symbol signal SS and rake combination valid signal R_EN to viterbi error correction circuit80.

Thus, by restoring finger operation units61a-61d to finger operation unit61as in the first embodiment, the circuit scale can still be reduced as compared to the third embodiment.

FIG. 11is an operation waveform diagram for describing a circuit operation of reception apparatus1D according to the fourth embodiment of the present invention.

The despreaded reception chip signals (D0-D3)×PN are integrated during one symbol, over four chips, and thereafter outputted from despread circuit62as reception symbol signals SP0-SP3for each path. Reception symbol signals SP0-SP3are inputted to channel estimation unit65and correction circuit64shown inFIG. 10.

Channel estimation unit65rotates reception symbol signals SP0-SP3by −45° and thereafter integrates them during two symbols, and measures a deviation from I axis in IQ coordinates and a distortion amount. Thus calculated correction coefficients K0-K3are updated by two symbol intervals, and outputted to correction circuit64. Correction circuit64receives correction coefficients K0-K3and corrects the amount of phase rotation of reception symbol signals SP0-SP3by complex operation, and outputs correct symbol signals S0-S3to large scale memory51D shown inFIG. 10.

Large scale memory51D adjusts the output timing of correction symbol signals S0-S3in accordance with combination timing signal CP, and thereafter outputs them to rake combination unit74shown inFIG. 10.FIG. 11shows correction symbol signals S0-S3before and after inputted/outputted to/from large scale memory51D. Rake combination unit74removes signals in invalid periods (time points t4-t7and the like) of correction symbol signals S0-S3in accordance with rake combination valid signal R_EN that indicates a valid period of rake combination, thereafter performs the rake combination of correction symbol signals S0-S3, and outputs combination symbol signal SS.

As above, according to the fourth embodiment, by restoring finger operation units61a-61dto finger operation unit61as in the first embodiment, the circuit scale can still be reduced as compared to the third embodiment.

Fifth Embodiment

FIG. 12is a schematic block diagram schematically showing a configuration of a reception apparatus1E according to a fifth embodiment of the present invention.

Referring toFIG. 12, reception apparatus1E according to the fifth embodiment is different from reception apparatus1D according to the fourth embodiment in that acquisition unit50D is replaced by an acquisition unit50E, and spread spectrum demodulation unit60D is replaced by a spread spectrum demodulation unit60E.

Acquisition unit50E is different from acquisition unit50D according to the fourth embodiment only in that large scale memory51D is replaced by a large scale memory51E. Accordingly, description of the common parts is not repeated herein. Spread spectrum demodulation unit60E is different from spread spectrum demodulation unit60D according to the fourth embodiment only in that correction circuit64is removed and rake combination unit74is replaced by a correction/rake combination unit74E. Accordingly, description of the common parts is not repeated herein.

In the fifth embodiment, despread circuit62of finger operation unit61outputs reception symbol signals SP0-SP3for each path, which are despreaded and thereafter integrated during one symbol, over four chips, to channel estimation unit65and large scale memory51E. Channel estimation unit65receives delay signal DLY outputted from delay profile calculation unit71, calculates correction coefficients K0-K3in accordance with the amount of phase rotation of reception symbol signals SP0-SP3, and outputs them to large scale memory51E. Path control unit72outputs combination timing signal CP that controls the rake combination timing of correction symbol signals S0-S3to large scale memory51E.

Large scale memory51E once stores reception chip signals D0-D3and temporarily holds reception symbol signals SP0-SP3outputted from finger operation unit61. Reception symbol signals SP0-SP3held in large scale memory51E are outputted to correction/rake combination unit74E together with combination timing signal CP and correction coefficients K0-K3. Correction/rake combination unit74E receives correction coefficients K0-K3and corrects the amount of phase rotation of reception symbol signals SP0-SP3by complex operation.

Correction/rake combination unit74E further performs the rake combination of the signals having their amount of phase rotation corrected by complex operation (correction symbol signals S0-S3) in accordance with combination timing signal CP that indicates the timing of rake combination and rake combination valid signal R_EN that indicates a valid period of rake combination, and outputs combination symbol signal SS and rake combination valid signal R_EN to viterbi error correction circuit80.

Thus, by removing correction circuit64and replacing rake combination unit74by correction/rake combination unit74E, the circuit scale can still be reduced as compared to the fourth embodiment. Further, by unifying the correction process of phase rotation due to fading and the rake combination process, the amount of operation processes of the entire reception apparatus1E can be reduced. As a result, power consumption of reception apparatus1E can be reduced.

FIG. 13is an operation waveform diagram for describing a circuit operation of reception apparatus1E according to the fifth embodiment of the present invention.

The despreaded reception chip signals (D0-D3)×PN are integrated during one symbol, over four chips, and thereafter outputted from despread circuit62as reception symbol signals SP0-SP3for each path. Reception symbol signals SP0-SP3are inputted to channel estimation unit65and large scale memory51E shown inFIG. 12. Channel estimation unit65rotates reception symbol signals SP0-SP3by −45° and thereafter integrates them during two symbols, and measures a deviation from I axis in IQ coordinates and a distortion amount. Thus calculated correction coefficients K0-K3are updated by two symbol intervals, and outputted to large scale memory51E.

Large scale memory51E temporarily holds reception symbol signals SP0-SP3, combination timing signal CP and correction coefficients K0-K3, and thereafter outputs them to correction/rake combination unit74E shown inFIG. 12. Correction/rake combination unit74E receives correction coefficients K0-K3and corrects the amount of phase rotation of reception symbol signals SP0-SP3by complex operation.

Correction/rake combination unit74E further performs the rake combination of the signals having their amount of phase rotation corrected by complex operation (correction symbol signals S0-S3) in accordance with combination timing signal CP that indicates the timing of rake combination and rake combination valid signal R_EN that indicates a valid period of rake combination, and outputs combination symbol signal SS. Combination symbol signal SS is outputted together with rake combination valid signal R_EN, and differentiated from signals in invalid periods (time points t6-t9and the like) of combination symbol signal SS.

As above, according to the fifth embodiment, by removing correction circuit64and replacing rake combination unit74by correction/rake combination unit74E, the circuit scale and power consumption of reception apparatus1E can still be reduced as compared to the fourth embodiment.

Sixth Embodiment

FIG. 14is a schematic block diagram schematically showing a configuration of a reception apparatus1F according to a sixth embodiment of the present invention.

Referring toFIG. 14, reception apparatus1F according to the sixth embodiment is different from reception apparatus1E according to the fifth embodiment in that acquisition unit50E is replaced by an acquisition unit50F, and spread spectrum demodulation unit60E is replaced by a spread spectrum demodulation unit60F.

Acquisition unit50F is different from acquisition unit50E according to the fifth embodiment only in that large scale memory51E is replaced by a large scale memory51F. Accordingly, description of the common parts is not repeated herein. Spread spectrum demodulation unit60F is different from spread spectrum demodulation unit60E according to the fifth embodiment only in that channel estimation unit65is removed and correction/rake combination unit74E is replaced by a channel estimation/correction/rake combination unit74F. Accordingly, description of the common parts is not repeated herein.

In the sixth embodiment, despread circuit62of finger operation unit61outputs reception symbol signals SP0-SP3for each path, which are despreaded and thereafter integrated during one symbol, over four chips, to large scale memory51F, together with delay signal DLY calculated in accordance with the reception intensity and the like of reception chip signals D0-D3. Path control unit72outputs combination timing signal CP that controls the rake combination timing of correction symbol signals S0-S3to large scale memory51F.

Large scale memory51F once stores reception chip signals D0-D3and temporarily holds reception symbol signals SP0-SP3outputted from finger operation unit61. Reception symbol signals SP0-SP3held in large scale memory51F are outputted to channel estimation/correction/rake combination unit74F together with combination timing signal CP. Channel estimation/correction/rake combination unit74F receives delay signal DLY and calculates correction coefficients K0-K3in accordance with the amount of phase rotation of reception symbol signals SP0-SP3.

Channel estimation/correction/rake combination unit74F further corrects the amount of phase rotation of reception symbol signals SP0-SP3by complex operation using the calculated correction coefficients K0-K3. Channel estimation/correction/rake combination unit74F further performs the rake combination of the signals having their amount of phase rotation corrected by complex operation (correction symbol signals S0-S3) in accordance with combination timing signal CP that indicates the timing of rake combination and rake combination valid signal R_EN that indicates a valid period of rake combination, and outputs combination symbol signal SS and rake combination valid signal R_EN to viterbi error correction circuit80.

Thus, by removing channel estimation unit65and replacing correction/rake combination unit74E by channel estimation/correction/rake combination unit74F, the circuit scale can still be reduced as compared to the fifth embodiment. Further, by unifying the channel estimation in accordance with the amount of phase rotation due to fading, the correction process of phase rotation and the rake combination process, the amount of operation processes of the entire reception apparatus1F can be reduced. As a result, power consumption of reception apparatus1F can be reduced.

FIG. 15is an operation waveform diagram for describing a circuit operation of reception apparatus1F according to the sixth embodiment of the present invention.

The despreaded reception chip signals (D0-D3)×PN are integrated during one symbol, over four chips, and thereafter outputted from despread circuit62as reception symbol signals SP0-SP3for each path. Reception symbol signals SP0-SP3are inputted to large scale memory51F shown inFIG. 14.FIG. 15also shows correction symbol signals S0-S3when inputted to large scale memory51F. Large scale memory51F temporarily holds reception symbol signals SP0-SP3and combination timing signal CP, and thereafter outputs them to channel estimation/correction/rake combination unit74F shown inFIG. 15.

Channel estimation/correction/rake combination unit74F rotates reception symbol signals SP0-SP3by −45° and thereafter integrates them during two symbols, and measures a deviation from I axis in IQ coordinates and a distortion amount, and calculates correction coefficients K0-K3. Channel estimation/correction/rake combination unit74F corrects the amount of phase rotation of reception symbol signals SP0-SP3by complex operation using the calculated correction coefficients K0-K3.

Channel estimation/correction/rake combination unit74F further performs the rake combination of the signals having their amount of phase rotation corrected by complex operation (correction symbol signals S0-S3) in accordance with combination timing signal CP that indicates the timing of rake combination and rake combination valid signal R_EN that indicates a valid period of rake combination, and outputs combination symbol signal SS. Combination symbol signal SS is outputted together with rake combination valid signal R_EN, and differentiated from signals in invalid periods (time points t6-t9and the like) of combination symbol signal SS.

As above, according to the sixth embodiment, by removing channel estimation unit65and replacing correction/rake combination unit74E by channel estimation/correction/rake combination unit74F, the circuit scale and power consumption of reception apparatus1F can still be reduced as compared to the fifth embodiment.

Seventh Embodiment

FIG. 16is a schematic block diagram schematically showing a configuration of a reception apparatus I G according to a seventh embodiment of the present invention.

Referring toFIG. 16, reception apparatus1G according to the seventh embodiment is different from reception apparatus1A according to the first embodiment in that acquisition unit50A is replaced by an acquisition unit50G, and spread spectrum demodulation unit60A is replaced by a spread spectrum demodulation unit60G.

Acquisition unit50G is different from acquisition unit50A according to the first embodiment only in that setting register52is replaced by a setting register52G. Accordingly, description of the common parts is not repeated herein. Spread spectrum demodulation unit60G is different from spread spectrum demodulation unit60A according to the first embodiment only in that rake combination unit74is replaced by a rake combination unit74G. Accordingly, description of the common parts is not repeated herein.

In the seventh embodiment, setting register52G of acquisition unit50G receives acquisition signal SYN and outputs it to matched filter53, and outputs reference value signal TH that indicates the reference value of the amount of phase error in a threshold value intensity of correction symbol signals S0-S3to rake combination unit74G of spread spectrum demodulation unit60G. Rake combination unit74G receives reference value signal TH and performs the rake combination of correction symbol signals S0-S3excluding correction symbol signals having an amount of phase error in a threshold value intensity greater than the reference value, and outputs combination symbol signal SS to viterbi error correction circuit80.

Thus, by outputting reference value signal TH from setting register52G to rake combination unit74G, and not adding the correction symbol signals to the rake combination that have the amount of phase error in the threshold value intensity greater than the reference value based on reference value signal TH, accuracy of rake combination can be improved.

FIG. 17is an operation waveform diagram for describing a circuit operation of reception apparatus1G according to the seventh embodiment of the present invention.

Referring toFIG. 17, reception chip signals D0-D3outputted from AD interpolation circuit30shown inFIG. 16are sequentially written to large scale memory51A shown inFIG. 16with chip intervals of D0, D1, . . . Reception chip signals D0-D3are once stored in matched filter53shown inFIG. 16, and thereafter in despread circuit62shown inFIG. 16, despreaded by despread codes PN outputted from code generation circuit63shown inFIG. 16. The despreaded reception chip signals (D0-D3)×PN are integrated during one symbol, over four chips, and thereafter outputted from despread circuit62as reception symbol signals SP0-SP3for each path.

Reception symbol signals SP0-SP3are inputted to channel estimation unit65and correction circuit64shown inFIG. 16. Channel estimation unit65rotates reception symbol signals SP0-SP3by −45° and thereafter integrates them during two symbols, and measures a deviation from I axis in IQ coordinates and a distortion amount. Thus calculated correction coefficients K0-K3are updated by two symbol intervals, and outputted to correction circuit64. Correction circuit64receives correction coefficients K0-K3, corrects the amount of phase rotation of reception symbol signals SP0-SP3by complex operation, and outputs correction symbol signals S0-S3.

Correction symbol signals S0-S3are once stored in path-basis reception vector correction result register73shown inFIG. 16, and outputted to rake combination unit74shown inFIG. 16. Rake combination unit74performs the rake combination of correction symbol signals S0-S3excluding correction symbol signals S01, S22having the amount of phase error in a threshold value intensity greater than the reference value, and outputs combination symbol signal SS: Thus, by not adding correction symbol signals S01, S22to the rake combination that have the amount of phase error in the threshold value intensity greater than the reference value, accuracy of rake combination can be improved.

As above, according to the seventh embodiment, by outputting reference value signal TH from setting register52G to rake combination unit74G, and not adding the correction symbol signals to the rake combination that have the amount of phase error in the threshold value intensity greater than the reference value based on reference value signal TH, accuracy of rake combination can be improved.

Eighth Embodiment

FIG. 18is a schematic block diagram schematically showing a configuration of a reception apparatus1H according to an eight embodiment of the present invention.

Referring toFIG. 18, reception apparatus1H according to the seventh embodiment is different from reception apparatus1A according to the first embodiment in that acquisition unit50A is replaced by an acquisition unit50H, and spread spectrum demodulation unit60A is replaced by a spread spectrum demodulation unit60H.

Acquisition unit50H is different from acquisition unit50A according to the first embodiment only in that setting register52is replaced by a setting register52H. Accordingly, description of the common parts is not repeated herein. Spread spectrum demodulation unit60H is different from spread spectrum demodulation unit60A according to the first embodiment only in that channel estimation unit65is replaced by a channel estimation unit65H. Accordingly, description of the common parts is not repeated herein.

In the eighth embodiment, setting register52H of acquisition unit50H receives acquisition signal SYN and outputs it to matched filter53, and outputs reference value signal TH that indicates the reference value of the amount of phase error in a threshold value intensity of reception symbol signals SP0-SP3to channel estimation unit65H of spread spectrum demodulation unit60H.

Channel estimation unit65H receives reference value signal TH and calculates correction coefficients only for reception symbol signals SP0-SP3excluding reception symbol signals having an amount of phase error in a threshold value intensity greater than the reference value. Correction circuit64corrects the phase rotation due to fading as to reception symbol signals SP0-SP3of which correction coefficients are calculated, and outputs them to path-basis reception vector correction result register73.

Thus, by outputting reference value signal TH from setting register52H to channel estimation unit65H, and not calculating correction coefficients for those reception symbol signals having the amount of phase error in the threshold value intensity greater than the reference value based on reference value signal TH, accuracy of rake combination can be improved. Further, by removing the reception symbol signals having the amount of phase error greater than the reference value in the threshold value at an earlier stage as compared to the seventh embodiment, the amount of operation processes of the entire reception apparatus1H can be reduced. As a result, power consumption of reception apparatus1H can be reduced.

FIG. 19is an operation waveform diagram for describing a circuit operation of reception apparatus1H according to the eighth embodiment of the present invention.

Referring toFIG. 19, reception chip signals D0-D3outputted from AD interpolation circuit30shown inFIG. 18are sequentially written to large scale memory51A shown inFIG. 18with chip intervals of D0, D1, . . . Reception chip signals D0-D3are once stored in matched filter53shown inFIG. 18, and thereafter in despread circuit62shown inFIG. 18, despreaded by despread codes PN outputted from code generation circuit63shown inFIG. 18. The despreaded reception chip signals (D0-D3)×PN are integrated during one symbol, over four chips, and thereafter outputted from despread circuit62as reception symbol signals SP0-SP3for each path.

Reception symbol signals SP0-SP3are inputted to channel estimation unit65H and correction circuit64shown inFIG. 18. Channel estimation unit65H calculates correction coefficients K0-K3only for reception symbol signals SP0-SP3having an amount of phase error in a threshold value intensity greater than the reference value, excluding correction coefficients K01, K12. Specifically, it rotates reception symbol signals SP0-SP3by −45° and thereafter integrates them during two symbols, and measures a deviation from I axis in IQ coordinates and a distortion amount.

Thus calculated correction coefficients K0-K3(excluding K01, K12) are updated by two symbol intervals, and outputted to correction circuit64. Correction circuit64receives correction coefficients K0-K3(excluding K01, K12), corrects the amount of phase rotation of reception symbol signals SP0-SP3by complex operation, and outputs correction symbol signals S0-S3. Now, as correction coefficients K01, K12are excluded, correction symbol signals S01, S22having the amount of phase error in the threshold value intensity greater than the reference value among correction symbol signals S0-S3are not outputted.

Correction symbol signals S0-S3(excluding S0, S22) are once held in path-basis reception vector correction result register73shown inFIG. 18, and thereafter subjected to rake combination by rake combination unit74shown inFIG. 18to be combination symbol signal SS. Thus, by not calculating correction coefficients for reception symbol signals SP0-SP3having the amount of phase error in the threshold value intensity, the accuracy of rake combination can be improved.

As above, according to the eighth embodiment, by outputting reference value signal TH from setting register52H to channel estimation unit65H, and not calculating the correction coefficients for reception symbol signals SP0-SP3having the amount of phase error in the threshold value intensity based on reference value signal TH, accuracy of rake combination can be improved and power consumption of receiving apparatus1H cam be reduced.