RLL code generation method for data storage device and recoding method therefor

A run length limited (RLL) code generation method for a data storage device is provided. In the RLL code generation method for generating a predetermined number of bit codewords, sequences of 16-bit data are received, and then sequences of 17-bit codewords are produced, wherein the sequences of 17-bit codewords has a first predetermined number of successive zeros as a maximum run length of zeros, and the sequences of 17-bit codewords include two subsequences each having a second predetermined number of successive zeros as a maximum run length of zeros. Thus, the RLL code generation method is helpful for an equalizer and provides a high recording density as well as a higher signal transmission rate compared to a rate 8/9(0,4/4) coding method.

BACKGROUND OF THE INVENTION 
The present invention relates to a run length limited (RLL) coding method 
used for digital data magnetic recording. More particularly, it relates to 
an RLL code generation method providing higher recording density than a 
conventional rate 8/9(0,4/4) coding method and decoding method therefor. 
Currently, research and development for effectively utilizing massive 
amounts of information have been conducted as the amount of data 
increases, particularly, in the field related to data storage devices. The 
end of the effort in the data storing field has been concentrated in the 
rapid transfer of massive amounts of information with high recording 
density and high reliability. To this end, a method for improving the 
physical properties of a data storage disk or improving the precision of 
an storage device is considered. Also, as an aspect of signal processing, 
there are provided a method for increasing the recording density of the 
storage device through effective coding, a method for reducing a data 
detection error using a signal processing technology, etc. 
Generally, data to be written in a data storage device is encoded into a 
RLL code. RLL code is a code that limits continuous-repetition of a 
specific bit pattern for timing control of a sampling clock and proper 
signal detection, that is, the number of successive "0"s between "1" and 
"1" is limited to the minimum d and the maximum k. 
As recently used among coding methods using the RLL code there are rate 
1/2(2,7) modulation code, rate 2/3(1,7) modulation code, rate 8/9(0,3) 
modulation code, rate 8/9(0,4/4) modulation code, etc. 
According to the rate 1/2(2,7) modulation code and rate 2/3(1,7) modulation 
code, "d" is equal to 1 and 2, respectively. Accordingly, interference 
between signals is decreased while redundancy is high due to the low code 
rate. Also, since the value of "k" is comparatively greater than those of 
the rate 8/9(0,3) and rate 8/9(0,4/4) modulation codes, it has less timing 
information which is helpful in the operation of a phase locked loop 
(PLL). 
The rate 8/9(0,3) coding and rate 8/9(0,4/4) coding methods provide high 
recording density due to less redundancy thereof, and include much timing 
information due to the small "k" thereof. However, interference between 
signals increases since "d" is equal to "0". 
Partial response maximum likelihood (PRML) pre-codes input signal to 
provide controlled inter-symbol interference (ISI) between the current 
data and the previous data, and then modifies into a target response 
d.sub.k =a.sub.k +a.sub.k-1 or d.sub.k =a.sub.k -a.sub.k-2, and data is 
detected using a Viterbi decoder. The PRML method shows excellent 
detecting capacity in a channel having n=1. 
RLL codes with "d" greater than zero are not necessary in PRML channels. 
Since the compensation for the ISI is inherent in the maximum likelihood 
(ML) detector, there is no need to reduce the interference by coding with 
a d condition. 
Thus, the rate 8/9(0,3) coding and rate 8/9(0,4/4) coding methods are 
employed in the PRML method utilizing the interference between signals to 
improve performance with holding high recording density and more timing 
information. 
Also, since the rate 8/9(0,3) coding and the rate 8/9(0,4/4) coding methods 
have a high code rate, they provide good effect to an equalizer with 
respect to a given partial response class compared to the rate 1/2(2,7) 
coding or rate 2/3(1,7) coding method. 
If the data sequence of an input signal is divided into an even-bit 
subsequence and an odd-bit subsequence, ML detection is independently 
applied to each subsequence. A constraint on the number of successive 
nominally zero samples in each subsequence adequately limits the detector 
delay and limits the hardware size. The maximum number of continuous "0"s 
between "1"s required for each subsequence is called "k1". The condition 
of k1 required for each subsequence is to reduce a path memory for the ML 
detector. The RLL(0,k/k1) modulation code satisfying the above condition 
is the rate 8/9(0,4/4) modulation code. 
SUMMARY OF THE INVENTION 
It is an object of the present invention to provide a partial response 
maximum likelihood (PRML) for a data storage device, providing a much 
higher recording density than a conventional rate 8/9(0,4/4) coding 
method. 
To achieve the above object, there is provided a run length limited (RLL) 
code generating method for generating a predetermined number of bit 
codewords comprising the steps of: (a) receiving sequences of 16-bit data; 
and (b) producing sequences of 17-bit codewords, wherein the sequences of 
17-bit codewords have a first predetermined number of successive zeros as 
a maximum run length of zeros, and the sequences of 17-bit codewords 
include two subsequences each having a second predetermined number of 
successive zeros as a maximum run length of zeros.

DETAILED DESCRIPTION OF THE INVENTION 
In a digital data storage device shown for example in FIG. 1, a user data 
to be recorded comes to have protection against noises or other factors 
causing various kinds of signal distortion via a compression encoder 1 and 
an error correction encoder 2. Then the signal is coded by a run length 
limited (RLL) modulation encoder 3 which is suitable for a channel 
characteristic of the storing apparatus, and then written via a signal 
generator 4 and a write equalizer 5 for example through a channel 
head/disk 11. During a reproducing process, a signal (here, from the 
channel head/disk 11) is detected via a read equalizer 6 and a detector 7 
to minimize an error probability, and then restored into the initial user 
data via an RLL modulation decoder 8, an error correction decoder 9 and a 
compression decoder 10 corresponding to the modulation encoder 3, the 
error correction encoder 2 and the compression encoder 1, respectively. 
FIG. 2 is a detailed block diagram of an encoding/decoding system using a 
16/17 RLL (0,5/5) modulation code in FIG. 1. In the system shown in FIG. 
2, an input signal is coded by an RLL 16/17(0,5/5) encoder 30 and then 
written in a storage device (for example, through head media 55) via a 
precoder 40 and equalizer 50. Then, the signal (for example, from head 
media 55) is processed by equalizers 60 for easy detection of the signal, 
and is then reproduced via ML detectors 70 and 72, each for the odd- and 
even-number subsequences, and an RLL 16/17(0,5/5) decoder 80 corresponding 
to the RLL 16/17(0,5/5) encoder 30. 
This system can transfer the signal at a higher rate at a given bandwidth 
compared with a full response signal, and provides much timing information 
to a phase locked loop (PLL) for timing recovery. Also, the signal can be 
reliably detected using the ML detectors (Viterbi detectors) 70 and 72 
having a simple structure. 
A modulation code of the present invention is expressed by three parameters 
d, k, k1. The parameters d and k represent the minimum run length and the 
maximum run length of zeros included in each sequence to be output, 
respectively, and the parameter k1 represents the maximum run length of 
zeroes included in an even-bit or odd-bit subsequence. In the code of the 
present invention, the d constraint is "0". The small k is required for 
precision in the timing and gain control, and k1 reduces the size of a 
path memory required for the ML detectors. 
The value of parameters k and k1 according to the present invention is 5, 
respectively. The present invention provides look-up tables for the coding 
and decoding of the rate 16/17 block code having these parameters. 
FIG. 3 is a flowchart illustrating an RLL code generation method according 
to the present invention. The operational principle thereof will now be 
described. The rate 16/17 RLL block code having the constraint parameters 
k and k1 of (0,5/5) provides 72750 codewords corresponding to 17-bit 
codewords, one-to-one from 16-bit data byte. Thus, all data combinations 
of 16-bit can be encoded into 17-bit codewords and decoded therefrom. 
According to the present invention, the codewords come to have a similar 
structure to that of the 16-bit data through 2 bytes partition. The 2 
bytes partition is for simplifying a one-to-one correspondence between 
16-bit binary data and the codewords. 
Assuming that Y represents 17-bit codewords of the rate 16/17(0,k/k1) RLL 
block code, Y is expressed by the following formula (1). 
EQU Y={Y.sub.1, Y.sub.2, Y.sub.3, Y.sub.4, Y.sub.5, Y.sub.6, Y.sub.7, Y.sub.8, 
Y.sub.9, Y.sub.10, Y.sub.11, Y.sub.12, Y.sub.13, Y.sub.14, Y.sub.15, 
Y.sub.16, Y.sub.17 } (1) 
In step 100 of FIG. 3, the sequences of codeword satisfying the constraint 
k=5 can be achieved by removing sequences having three or more continuous 
zeros run length at the one end and two or more continuous zeros run 
length at the other end and sequences having five or more run length. The 
constraint is given from the boolean relationship of the following formula 
(2). 
##EQU1## 
Similarly, the sequences of codeword satisfying the constraint k1=5 can be 
achieved by removing sequences having three or more continuous zeros run 
length at the one end and two or more continuous zeros run length at the 
other end and sequences having five or more zeros run length in respect to 
even-bit or odd-bit subsequence within 17-bit codeword sequences 
satisfying the constraint k=5. 
The constraint is given from the boolean relationship of the following 
formulas (3) and (4). 
EQU (Y.sub.1 +Y.sub.3 +Y.sub.5 +Y.sub.7) (Y.sub.3 +Y.sub.5 +Y.sub.7 +Y.sub.9 
+Y.sub.11 +Y.sub.13) (Y.sub.5 +Y.sub.7 +Y.sub.9 +Y.sub.11 +Y.sub.13 
+Y.sub.15) (Y.sub.7 +Y.sub.9 +Y.sub.11 +Y.sub.13 +Y.sub.15 +Y.sub.17)=1 
(3) 
EQU (Y.sub.2 +Y.sub.4 +Y.sub.6 +Y.sub.8) (Y.sub.4 +Y.sub.6 +Y.sub.8 +Y.sub.10 
+Y.sub.12 +Y.sub.14) (Y.sub.8 +Y.sub.10 +Y.sub.12 +Y.sub.14) (Y.sub.12 
+Y.sub.14 +Y.sub.16)=1 (4) 
72750 sequences meet the above formulas (2), (3) and (4). Thus, 7214 
(72750-65536) redundant codewords are used for removing an undesired 
codeword pattern or for another special purpose. 
In step 200, a method of partition is adopted for providing regularity to 
the relationship between the 17-bit codewords and the 16-bit data. 
First, sequences of 16-bit data are mapped with sequences of 17-bit 
codeword having the same bit pattern. 
That is, sequences of codeword having "1" as the middle bit among the 
sequences of 17-bit codeword satisfying the formulas (2), (3) and (4) are 
mapped with sequences of 16-bit data having the same forward and backward 
8 bits. The number of pairs mapped by the partition of 16-bit data 
sequences and the 17-bit codewords are 37849. However, in order to prevent 
the coded sequence from having all "1"s, the middle bit of the codeword 
having all "1"s is set to "0". 
In step 300, the remaining sequences of 16-bit data excluded in the step 
200 are mapped with the sequences of 17-bit codeword. 
Among 27687 17-bit codewords having 0s as middle bits, codewords having the 
same forward 8 bits Y.sub.1, Y.sub.2, Y.sub.3, Y.sub.4, Y.sub.5, Y.sub.6, 
Y.sub.7, Y.sub.8 ! are grouped and codewords having fewer zeros are 
preferably selected. Here, in step 400, codewords which have detrimental 
effects on the PLL and the ML detector can be removed to maintain timing 
information and reduce the detrimental effects on the ML detectors. Also, 
the complexity of the encoder/decoder can be reduced. 
FIG. 4 shows a portion of a table of 17-bit codewords in a hexadecimal form 
with respect to input 16-bit sequences 0000-FFFF. 
As described above, according to the present invention, a modulation code 
which is suitable for a PR channel, expressed as (1-D) (1+D).sup.n, where 
n=1, 2, . . . , using ML detectors, is provided. The modulation code 
provides abundant non-zero samples, improving the channel timing and the 
capability of the gain control circuit. 
Also, the path of the Viterbi decoder is forcibly merged, so that a path 
memory is decreased and the complexity of the ML detector is also limited. 
Also, in order to write more data on a disk, further small redundancy is 
provided, and a signal can easily be detected while maintaining a 
self-clocking of the signal. Also, the size of the path memory required 
for the ML detector is reduced, thereby reducing delay in detection and 
the complexity of the hardware. Also, according to the present invention, 
the optimized look-up tables for input and output with respect to the 
coding and decoding of the rate 16/17 (0,5/5) block code, and a simplified 
relationship between the input and output are provided. Particularly, in 
the digital data magnetic recording for a disk memory device, the signal 
can be transmitted at a high rate with higher density, compared to that of 
the conventional rate 8/9(0,4/4) coding method.