Method and apparatus for quantifying and minimizing skew between signals

Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

BACKGROUND

A double data rate (DDR) memory controller can be implemented in a field programmable gate array (FPGA) device. As the DDR memory is advanced to provide higher data throughput, e.g., up to 1 Gbs, a timing budget left for the FPGA is substantially reduced. The DDR memory interface is defined to transmit a data strobe signal in conjunction with a group of data signals for data capture in the receiver side, i.e., at the memory controller of the FPGA. All skew and jitter among the various data signals and the data strobe signal is treated as uncertainty and is subtracted from the valid data sampling window. Thus, uncertainty associated with signal skew limits the rate at which the memory controller can process incoming and outgoing data transmissions. Therefore, it is desirable to reduce skew among the data signals and data strobe signal. In view of the foregoing, a solution is needed to accurately quantify skew between signals and accurately compensate for the quantified skew to enhance device performance.

SUMMARY

In one embodiment, a signal delay measurement circuit is disclosed. The circuit includes an input register defined to receive a test data signal. The input register is defined to output the test data signal in accordance with a test clock signal. The circuit also includes an output register defined to receive a delayed version of the test data signal. The output register is defined to output the delayed version of the test data signal in accordance with a delayed version of the test clock signal. The circuit further includes an emulation module connected between the input register and the output register. The emulation module is defined to emulate an actual signal transmission path for which signal delay is to be measured. The emulation module is defined to introduce signal delay in the test data signal as the test data signal is transmitted from the input register to arrive at the output register as the delayed version of the test data signal. The circuit also includes a delay chain defined to introduce a controllable amount of signal delay in the test clock signal so as to generate the delayed version of the test clock signal.

In another embodiment, a delay element calibration circuit is disclosed. The circuit includes an input register defined to receive a test data signal. The input register is defined to output the test data signal in accordance with a test clock signal. A period of the test clock signal is adjustable. The circuit also includes an output register defined to receive a delayed version of the test data signal. The output register is defined to output the delayed version of the test data signal in accordance with the test clock signal, i.e., in accordance with the same test clock signal by which the input register is clocked. The circuit further includes a chain of delay elements connected between the input register and the output register. The chain of delay elements is defined to introduce signal delay in the test data signal as the test data signal is transmitted from the input register to arrive at the output register as the delayed version of the test data signal.

In another embodiment, a method is disclosed for minimizing skew between two signals. The method includes operations for calibrating each of a coarse delay element and a fine delay element. The method also includes operations for measuring signal delay associated with each of a first signal and a second signal. The signal delay measurement operations are performed using the calibrated coarse and fine delay elements. The method further includes an operation for determining a skew between the first and second signals. The skew is defined as a difference between the measured signal delay associated with the first signal and the measured signal delay associated with the second signal. In another operation, settings for coarse and fine delay modules are determined so as to minimize the skew between the first and second signals. The coarse and fine delay modules are defined to implement a selectable number of the coarse and fine delay elements, respectively. The method also includes an operation for storing the determined settings for the coarse and fine delay modules in non-volatile memory.

Other aspects and advantages of the invention will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the present invention.

DETAILED DESCRIPTION

A method and apparatus is disclosed for quantifying and minimizing skew between two signals, e.g., between a data signal and a data strobe signal. The delay associated with each of the two signals is accurately measured. Also, measurement of the delay associated with each of the two signals is performed using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. The delay measurement circuit is defined to emulate a delay associated with each of the two signals as propagated from a respective origin point to a respective destination point. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. Consequently, each measured delay for the two signals represents a true delay that is specific to the particular as-fabricated condition of the device. Once the delay for each of the two signals is measured using the delay measurement circuit, the skew between the two signals is quantified as the difference in the measured delays.

A coarse delay module and fine delay module are defined within the transmission path of each of the two signals. The transmission path represents the circuitry through which a given signal will be propagated from its origin point to its destination point. Based on the measured skew between the two signals, the coarse and fine delay modules associated with each of the two signals are appropriately set to compensate for the skew, i.e., minimize the skew, between the two signals. The accuracy by which the skew can be compensated is dependent upon the accuracy of the coarse and fine delay modules.

The coarse delay module provides for serial connection of a selectable number of coarse delay elements, wherein each coarse delay element is defined to provide a substantially equivalent amount of signal delay. The signal to be propagated through the coarse delay module is transmitted through the selected number of serially connected coarse delay elements within the coarse delay module. Similarly, the fine delay module provides for serial connection of a selectable number of fine delay elements, wherein each fine delay element is defined to provide a substantially equivalent amount of signal delay. The signal to be propagated through the fine delay module is transmitted through the selected number of serially connected fine delay elements within the fine delay module. Thus, the accuracy by which the delay of a given signal can be adjusted by the coarse and fine delay modules is defined by the accuracy of the coarse and fine delay elements, respectively.

To enable selection of the appropriate number of coarse and fine delay elements to be serially connected within the coarse and fine delay modules, respectively, in order to accurately compensate for the skew between the two signals, it is necessary to calibrate the coarse and fine delay elements. Calibration of the coarse and fine delay elements essentially includes determination the amount of signal delay provided by the coarse and fine delay elements, respectively, within the actual device. The signal delay provided by the coarse delay element is measured using a coarse delay calibration circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Similarly, the delay provided by the fine delay element is measured using a fine delay calibration circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated.

Thus, the measured delay associated with each of the coarse and fine delay elements is subject to the same fabrication-dependent attributes that affect the actual circuitry having the coarse and fine delay modules defined therein. Consequently, each measured amount of signal delay provided by the coarse and fine delay elements represents a true signal delay that is specific to the particular as-fabricated condition of the device. Once the coarse and fine delay elements are calibrated, it is possible to select the appropriate number of coarse and fine delay elements to be serially connected within the coarse and fine delay modules, respectively, within each of the two signal paths in order to accurately compensate for the skew between the two signals.

By way of example, the method and apparatus for quantifying and minimizing skew between two signals is described herein in the context of a memory interface performing a read operation. It should be understood, however, that the present invention is not limited to a memory interface performing a read operation or to a memory interface for that matter. It should be appreciated that the method and apparatus for quantifying and minimizing skew between two signals, as described herein, can be implemented in essentially any integrated circuit device where quantification of signal delay is necessary and/or where minimization of skew between two or more signals is desired. Additionally, the present invention may be of particular benefit in cases where signal delay measurement, skew quantification, and/or skew minimization are desired to be performed with substantial accuracy on a chip-specific basis, thus accounting for chip-specific fabrication-dependent attributes that affect signal propagation within the specific chip.

FIG. 1Ais an illustration showing a memory interface100, in accordance with one embodiment of the present invention. In one embodiment, the memory interface100resides in an on-chip memory controller and is defined to interface with an off-chip memory. For example, the memory controller having memory interface100associated therewith is defined on a programmable logic device (PLD), such as a field programmable gate array (FPGA) logically programmed to function as a memory controller. Also, by way of example, the off-chip memory may be of the type DDR, QDR, or RLDRAM, among others.

The memory interface100includes a number of data signal ports105and a data strobe signal port131. The number of data signal ports105can vary depending on the particular embodiment. For example, in a 32-bit memory interface100embodiment, there are thirty-two data signal ports105and one data strobe signal port131. It should be appreciated that the present invention does not depend upon the particular size of the memory interface100, i.e., the number of data signal ports105per data strobe signal port131. Specifically, the present invention is operable with the memory interface100having at least one data signal port105and at least one data strobe signal port131. Therefore, to avoid unnecessarily obscuring the present invention, the description hereafter is provided with regard to a single exemplary data signal path101and a single exemplary data strobe signal path103.

From the data signal port105, the data signal is transmitted through an input buffer107to an input of a coarse delay module109. From an output of the coarse delay module109, the data signal is transmitted to an input of a fine delay module111. From an output of the fine delay module111, the data signal is transmitted to data input ports associated with each of a pair of input/output (I/O) flip-flops127and129. The I/O flip-flops127and129are connected to be clocked in an opposite manner. Specifically, a clock port of the I/O flip-flop127is connected to receive a clock signal, and a clock port of the I/O flip-flop129is connected to received an inverted version of the clock signal. In this manner, the memory interface100is capable of providing double data rate throughput, such that data signals can be received at the data signal port105and clocked through the data signal path101in accordance with both rising and falling edges of the clock signal. Each I/O flip-flop127/129includes a data output port through which the data signal having been latched within the flip-flop is transmitted to be received and processed by other logic within the device.

The coarse delay module109is defined to receive a control signal from a multiplexer113. The control signal received by the coarse delay module109sets the amount of signal delay provided by the coarse delay module109. More specifically, the control signal received by the coarse delay module109sets the number of serially connected coarse delay elements within the coarse delay module109through which the data signal is transmitted. The multiplexer113is defined to receive two input signals and a select signal. One of the multiplexer113input signals is passed through the multiplexer113in accordance with the multiplexer113select signal to serve as the control signal for the coarse delay module109. Thus, each of the multiplexer113input signals represents the control signal for the coarse delay module109. The first multiplexer113input signal is stored in a configuration memory cell115of the PLD. The second multiplexer113input signal in stored in a non-volatile memory cell117. The multiplexer113select signal is stored in a configuration memory cell119of the PLD. Thus, the configuration memory cell119is configured to specify whether the control signal for the coarse delay module109is to be provided from the configuration memory cell115or from the non-volatile memory cell117.

The fine delay module111is defined to receive a control signal from a multiplexer121. The control signal received by the fine delay module111sets the amount of signal delay provided by the fine delay module111. More specifically, the control signal received by the fine delay module111sets the number of serially connected fine delay elements within the fine delay module111through which the data signal is transmitted. The multiplexer121is defined to receive two input signals and a select signal. One of the multiplexer121input signals is passed through the multiplexer121in accordance with the multiplexer121select signal to serve as the control signal for the fine delay module111. Thus, each of the multiplexer121input signals represents the control signal for the fine delay module111. The first multiplexer121input signal is stored in a configuration memory cell123of the PLD. The second multiplexer121input signal in stored in a non-volatile memory cell125. The multiplexer121select signal is stored in the same configuration memory cell119as the multiplexer113select signal. Thus, the configuration memory cell119is configured to specify whether the control signal for the fine delay module111is to be provided from the configuration memory cell123or from the non-volatile memory cell125. Because both of the multiplexers113and121are defined to receive the same select control signal, the control signals for each of the coarse delay module109and the fine delay module111will both be provided from either configuration memory or non-volatile memory.

If the coarse and fine delay module109/111control signals are provided from non-volatile memory117/125as opposed to configuration memory115/123, the control signals for the coarse and fine delay modules109/111can be “burned” into the non-volatile memory117/125before the PLD is logically programmed. Thus, provision of the option for storing the control signals of the coarse and fine delay modules109/111in the non-volatile memory117/125enables the amount of delay to be provided by the coarse and fine delay modules109/111to be determined based on test results before the PLD is logically programmed. Use of the configuration memory115/123requires that the delay settings of the coarse and fine delay modules109/111be predicted. However, use of the non-volatile memory117/125enables the delay settings of the coarse and fine delay modules109/111to be set based on measured skew between the data signal and the data strobe signal within the actual device.

The data signal is clocked into and out of the I/O flip-flops127/129in accordance with the data strobe signal received at the data strobe signal port131and transmitted through the data strobe signal path103. From the data strobe signal port131, the data strobe signal is transmitted through an input buffer133to an input of a delay chain135. In one embodiment, the delay chain135is defined as a clock-drift tracking delay chain with variable delay that will track a system clock in order to provide a consistent one-quarter clock period delay, i.e., 90 degree phase-shift delay, in the data strobe signal relative to the received data signal. Thus, the data strobe signal provided at an output of the delay chain135is delayed by one-quarter of a clock period relative to the data signal received at the data signal port105. An exemplary delay chain135is described in U.S. Pat. No. 7,030,675, which is incorporated herein by reference.

FIG. 1Bis an illustration showing the delay in the data strobe signal relative to the received data signal as provided by delay chain135, in accordance with one embodiment of the present invention. As shown inFIG. 1B, the data signal (DQ) and data strobe signal (DQS) are received at the data input port105and data strobe input port103, respectively, of the memory interface100in an edge-aligned manner. For example, in one embodiment, both the data signal (DQ) and the data strobe signal (DQS) are clocked off of a common system clock. The one-quarter clock period delay of the data strobe signal (DQS) provided by the delay chain135is intended to enable the data signal (DQ) to arrive at the I/O flip-flops127/129prior to arrival of the corresponding data strobe signal (DQS) at the I/O flip-flops127/129, thus enabling the data signal (DQ) to be correctly captured by the I/O flip-flops127/129.

Although transmission of the data strobe signal through the delay chain135is generally performed for the reasons discussed above, the data strobe signal path103includes a multiplexer137to provide an alternative to transmitting the data strobe signal through the delay chain135. Specifically, a first input of the multiplexer137is defined to receive the data strobe signal directly from the output of the input buffer133, thus bypassing the delay chain135. A second input of the multiplexer137is defined to receive the one-quarter clock period delayed version of the data strobe signal from the output of the delay chain135. The multiplexer137is set to pass through either the non-delayed data strobe signal received at its first input or the delayed data strobe signal received at its second input. The data strobe signal output from the multiplexer137is transmitted to an input of a buffer139. The buffer139assists in driving the data strobe signal through the clock tree to each of the I/O flip-flops127/129in the memory interface100.

From an output of the buffer139, the data strobe signal is transmitted to an input of a coarse delay module141. From an output of the coarse delay module141, the data strobe signal is transmitted to an input of a fine delay module143. From an output of the fine delay module143, the data strobe signal is transmitted through the clock tree to clock ports associated with each of the I/o flip-flops127/129. As previously mentioned, the I/O flip-flops127and129are connected to be clocked in an opposite manner, such that one I/O flip-flop associated with a given data path101receives the data strobe signal and the other I/O flip-flop associated with the given data path101receives an inverted version of the data strobe signal.

The coarse delay module141is defined to receive a control signal from a multiplexer145. The control signal received by the coarse delay module141sets the amount of signal delay provided by the coarse delay module141. More specifically, the control signal received by the coarse delay module141sets the number of serially connected coarse delay elements within the coarse delay module141through which the data signal is transmitted. The multiplexer145is defined to receive two input signals and a select signal. One of the multiplexer145input signals is passed through the multiplexer145in accordance with the multiplexer145select signal to serve as the control signal for the coarse delay module141. Thus, each of the multiplexer145input signals represents the control signal for the coarse delay module141. The first multiplexer145input signal is stored in a configuration memory cell147of the PLD. The second multiplexer145input signal in stored in a non-volatile memory cell149. The multiplexer145select signal is stored in a configuration memory cell151of the PLD. Thus, the configuration memory cell151is configured to specify whether the control signal for the coarse delay module141is to be provided from the configuration memory cell147or from the non-volatile memory cell149.

The fine delay module143is defined to receive a control signal from a multiplexer153. The control signal received by the fine delay module143sets the amount of signal delay provided by the fine delay module143. More specifically, the control signal received by the fine delay module143sets the number of serially connected fine delay elements within the fine delay module143through which the data signal is transmitted. The multiplexer153is defined to receive two input signals and a select signal. One of the multiplexer153input signals is passed through the multiplexer153in accordance with the multiplexer153select signal to serve as the control signal for the fine delay module143. Thus, each of the multiplexer153input signals represents the control signal for the fine delay module143. The first multiplexer153input signal is stored in a configuration memory cell155of the PLD. The second multiplexer153input signal in stored in a non-volatile memory cell157. The multiplexer153select signal is stored in the same configuration memory cell151as the multiplexer153select signal. Thus, the configuration memory cell151is configured to specify whether the control signal for the fine delay module143is to be provided from the configuration memory cell155or from the non-volatile memory cell157. Because both of the multiplexers145and153are defined to receive the same select control signal, the control signals for each of the coarse delay module141and the fine delay module143will both be provided from either configuration memory or non-volatile memory.

If the coarse and fine delay module141/143control signals are provided from non-volatile memory149/157as opposed to configuration memory147/155, the coarse and fine delay module141/143control signals can be “burned” into the non-volatile memory149/157before the PLD is logically programmed. Thus, provision of the option for storing the coarse and fine delay module141/143control signals in the non-volatile memory149/157enables the amount of delay to be provided by the coarse and fine delay modules141/143to be determined based on test results before the PLD is logically programmed. Use of the configuration memory147/155requires that the delay settings of the coarse and fine delay modules141/143be predicted. However, use of the non-volatile memory149/157enables the delay settings of the coarse and fine delay modules141/143to be set based on measured skew between the data signal and the data strobe signal within the actual device.

FIG. 1Cis an illustration showing the coarse delay module109/141, in accordance with one embodiment of the present invention. The coarse delay module109/141includes a chain of serially connected coarse delay elements161. Each of the coarse delay elements161is defined in a substantially equivalent manner such that a signal delay provided by each of the coarse delay elements161is substantially equivalent. The coarse delay module109/141also includes a multiplexer163defined to transmit one of a number of multiplexer163input signals as an output signal (out) of the coarse delay module109/141, in accordance with the control signal113/145provided to the coarse delay module109/141. The multiplexer163input signals include an input signal (in) as received by the coarse delay module109/141and each signal present at an output node of each coarse delay element161. Thus, each multiplexer163input signal represents the input signal (in) received by the coarse delay module109/141having a different amount of delay introduced therein. Therefore, it should be appreciated that the coarse delay module is capable of delaying a received input signal by an integer multiple of the signal delay provided by an individual coarse delay element161.

The exemplary coarse delay module109/141depicted inFIG. 1Cshows the chain of serially connected coarse delay elements161as including seven coarse delay elements161. Therefore, eight input signals are provided to the multiplexer163, i.e., the as-received input signal and the delay signal present at the output node of each coarse delay element161. To provide for full functionality, the control signal113/145provided to the 8-to-1 multiplexer163is a 3-bit control signal. It should be understood, however, that the present invention is not intended to be limited to the particular number of coarse delay elements161shown inFIG. 1C. In other embodiments, the coarse delay module109/141can include essentially any number of coarse delay elements161in the chain of serially connected coarse delay elements161. Also, in other embodiments, the control signal113/145can be defined by a number of bits sufficient to enable full functionality of the multiplexer163.

FIG. 1Dis an illustration showing the fine delay module111/143, in accordance with one embodiment of the present invention. The fine delay module111/143includes a chain of serially connected fine delay elements165. Each of the fine delay elements165is defined in a substantially equivalent manner such that a signal delay provided by each of the fine delay elements165is substantially equivalent. The fine delay module111/143also includes a multiplexer167defined to transmit one of a number of multiplexer167input signals as an output signal (out) of the fine delay module111/143, in accordance with the control signal121/153provided to the fine delay module111/143. The multiplexer167input signals include an input signal (in) as received by the fine delay module111/143and each signal present at an output node of each fine delay element165. Thus, each multiplexer167input signal represents the input signal (in) received by the fine delay module111/143having a different amount of delay introduced therein. Therefore, it should be appreciated that the fine delay module111/143is capable of delaying a received input signal by an integer multiple of the signal delay provided by an individual fine delay element165.

The exemplary fine delay module111/143depicted inFIG. 1Dshows the chain of serially connected fine delay elements165as including seven fine delay elements165. Therefore, eight input signals are provided to the multiplexer167, i.e., the as-received input signal and the delayed signal present at the output node of each fine delay element165. To provide for full functionality, the control signal121/153provided to the 8-to-1 multiplexer167is a 3-bit control signal. It should be understood, however, that the present invention is not intended to be limited to the particular number of fine delay elements165shown inFIG. 1D. In other embodiments, the fine delay module111/143can include essentially any number of fine delay elements165in the chain of serially connected fine delay elements165. Also, in other embodiments, the control signal121/153can be defined by a number of bits sufficient to enable full functionality of the multiplexer167.

With reference to the memory controller100ofFIG. 1A, bypassing the delay chain135, it is desirable to have essentially zero skew between the data signal path101and the data strobe signal path103. If the delay in the data signal path101is greater than the delay in the data strobe signal path103(bypassing the delay chain135), the coarse and fine delay modules141/143are set to increase the delay in the data strobe signal path103, such that the delay in each of the data signal path101and data strobe signal path103is essentially equivalent. Conversely, if the delay in the data strobe signal path103(bypassing the delay chain135) is greater than the delay in the data signal path101, the coarse and fine delay modules109/111are set to increase the delay in the data signal path101, such that the delay in each of the data signal path101and data strobe signal path103is essentially equivalent. To appropriately set the coarse and fine delay modules109/111/141/143, it is necessary to have a measure of the signal delay in each of the data signal path101and data strobe signal path103(bypassing the delay chain135).

FIG. 2Ais an illustration showing a delay measurement circuit200for measuring the signal delay in each of the data signal path101and data strobe signal path103(bypassing the delay chain135), in accordance with one embodiment of the present invention. The delay measurement circuit200is defined to use a racing condition to measure the signal delay in an emulation of the data signal path101and the data strobe signal path103. The circuit200includes an emulation module203connected between an input register201and an output register207. The emulation module203is defined to emulate either the data signal path101or the data strobe signal path103, depending on which of the path's101/103delay is to be measured. It should be appreciated that the emulation module203for the data signal path101emulates the signal delay from the data signal port105to the data input port of the I/O flip-flops127/129. Also, it should be appreciated that the emulation module203for the data strobe signal path103emulates the signal delay from the data strobe signal port131to the clock port of the I/O flip-flops127/129(bypassing the delay chain135).

The input register201is defined to receive a test data input signal (TDIN1). The test data input signal (TDIN1) is clocked into and out of the input register201in accordance with a test clock signal (TCLK1). The output signal (OUT1) from the input register201is transmitted through the emulation module203, through a multiplexer205, and is received at the output register207as delayed test data signal (DIN1). The delayed test data signal (DIN1) is clocked into and out of the output register207in accordance with a delayed test clock signal (DCLK1). The signal clocked out of the output register207is the test data output signal (TDOUT1).

The delay present between the test clock signal (TCLK1) and the delayed test clock signal (DCLK1) is adjustable via a delay chain211. The delay chain211includes a coarse delay element161connected to a chain of serially connected fine delay elements165. The delay chain211includes a multiplexer209defined to transmit one of a number of multiplexer209input signals as the delayed test clock signal (DCLK1), in accordance with a delay select signal (DLYSEL). The multiplexer209input signals include the delayed clock signal present at an output node of the coarse delay element161and each of the delayed clock signals present at an output node of each fine delay element165. Thus, each multiplexer209input signal represents the test clock signal (TCLK1) having a different amount of delay introduced therein. It should be appreciated that in various embodiments, the number of coarse and fine delay elements161/165in the delay chain211can vary depending on the amount of signal delay provided by the emulation module203.

FIG. 2Bis an illustration showing waveforms associated with operation of the delay measurement circuit200, in accordance with one embodiment of the present invention. For a given delay measurement, the test clock signal (TCLK1) is delayed by an amount (Δt1+m*Δt2) to generate the delayed test clock signal (DCLK1), where Δt1is the delay provided by the coarse delay element161, Δt2is the delay provided by the fine delay element165, and the integer number (m) represents the number of fine delay elements165that are selected to contribute to the test clock signal delay.

The delay measurement is initiated by transmitting a pair of reset pulses213in the test clock signal (TCLK1) while maintaining a low state of the test data input signal (TDIN1) to clear the input and output registers201/207. Then, the test data input signal (TDIN1) is driven high. At this point, the delay measurement circuit200is prepared for racing of the test data input signal (TDIN1) and the test clock signal (TCLK1) to the output register207. To initiate the signal race, the test clock signal (TCLK1) is pulsed. When the test clock signal (TCLK1) is pulsed, the high test data input signal (TDIN1) is clocked out of the input register201as the signal (OUT1). The delayed test data input signal (DIN1) then arrives at the output register207with the signal delay provided by the emulation module203and the multiplexer205. It should be appreciated that the multiplexer205is defined to mirror the multiplexer209, such that both the test data signal path and the test clock signal path include the same amount of multiplexer205/209delay.

The delayed test clock signal (DCLK1) arrives at the clock port of the output register207with the delay (Δt1+m*Δt2) provided by the delay chain211. If the data signal path has a longer delay than the test clock signal path, i.e., (Δt>Δt1+m*Δt2), the output register207will not catch the high delayed test data input signal (DIN1) and the test data output signal (TDOUT1) will remain low. If the data signal path has a shorter delay than the test clock signal path, i.e., (Δt<Δt1+m*Δt2), the output register207will catch the high delayed test data input signal (DIN1) and the test data output signal (TDOUT1) will go high. The delay measurement is performed by incrementally increasing the test clock signal delay provided by the delay chain211until the output register207catches the high delayed test data signal (DIN1).

When the output register207catches the high delayed test data signal (DIN1), the skew between the test data signal path and the test clock signal path is less than a setup time of the output register207, e.g., less than about 30 picoseconds. The measured delay in the emulated signal path (data signal path101or data strobe signal path103) is approximately equal to the delay (Δt1+m*Δt2) provided by the delay chain211, where (m) is the number fine delay elements165selected when the output register207catches the high delayed test data signal (DIN1).

In accordance with the foregoing, the coarse delay element161and the fine delay element165can be calibrated to enable accurate quantification of the signal delay measurement obtained using the delay measurement circuit200.FIG. 3Ais an illustration showing a coarse delay element calibration circuit300, in accordance with one embodiment of the present invention. The calibration circuit300includes a chain of serially connected coarse delay elements161connected between an input register301and an output register303. The input register301is defined to receive a test data input signal (TDIN2). The test data input signal (TDIN2) is clocked through the input register301in accordance with a test clock signal (TCLK2). The output signal (OUT2) from the input register301is transmitted through the chain of serially connected coarse delay elements161and is received at the output register303as delayed test data signal (DIN2). The delayed test data signal (DIN2) is clocked through the output register303in accordance with the test clock signal (TCLK2). The signal clocked out of the output register303is the test data output signal (TDOUT2). Also, the number (n) of coarse delay elements161is selected such that the total signal delay provided by the chain of serially connected coarse delay elements161is at least as large as the minimum achievable period of the test clock signal (TCLK2).

The calibration circuit300is defined to use a racing condition to measure the total signal delay (n*Δt1) provided by the chain of serially connected coarse delay elements161.FIG. 3Bis an illustration showing waveforms associated with operation of the coarse delay element calibration circuit300, in accordance with one embodiment of the present invention. The test data input signal (TDIN2) is delayed by an amount (n*Δt1) to generate the delayed test data signal (DIN2). The calibration measurement is initiated by transmitting a pair of reset pulses305in the test clock signal (TCLK2) while maintaining a low state of the test data input signal (TDIN2) to clear the input and output registers301/303. Then, the test data input signal (TDIN2) is driven high. At this point, the calibration circuit300is prepared for racing of the test data input signal (TDIN2) and the test clock signal (TCLK2) to the output register303. To perform the signal race, the test clock signal (TCLK2) is pulsed twice with a clock period of Tclk. When the test clock signal (TCLK2) is pulsed, the high test data input signal (TDIN2) is clocked through the input register301as the signal (OUT2). The delayed test data signal (DIN2) then arrives at the output register303with the signal delay of n*Δt1relative to the signal (OUT2).

If the data signal path has a longer delay than the clock period Tclk, i.e., (n*Δt1>Tclk), the output register303will not catch the high delayed test data signal (DIN2) and the test data output signal (TDOUT2) will remain low. If the data signal path has a shorter delay than the clock period Tclk, i.e., (n*Δt1<Tclk), the output register303will catch the high delayed test data signal (DIN2) and the test data output signal (TDOUT2) will go high. The delay measurement is performed by gradually increasing the test clock period Tclk until the output register303catches the high delayed test data signal (DIN2). When the output register303catches the high delayed test data signal (DIN2), total delay (n*Δt1) is closely matched with the test clock period Tclk. Thus, the signal delay provided by an individual coarse delay element161can be calibrated as the test clock period Tclk divided by (n).

In one embodiment, the test clock signal is generated by a phase lock loop (PLL) circuit. The PLL circuit can be defined to enable discrete adjustment of the period of the test clock signal Tclk. For example, a multiplier module within a feedback path of the PLL circuit, which is defined to control the signal frequency, i.e., signal period, output by the PLL circuit, can be multiplexed to enable selection of different multiplier values, wherein selection of different multiplier values provides a corresponding adjustment in the period of the signal output by the PLL circuit. It should be appreciated that above-mentioned PLL circuit for adjusting the test clock period Tclk is provided by way of example. Other embodiments may use different techniques to adjust the test clock period Tclk, so long as the adjusted test clock period Tclk is known.

In one embodiment, an approach similar to that described with respect to the coarse delay element161calibration circuit300ofFIGS. 3A-3Bcan be used to calibrate the fine delay element165. However, as the signal delay provided by the fine delay element165, e.g., 30 picoseconds, can be substantially smaller than the minimum achievable test clock period Tclk, e.g., 10 nanoseconds, it could take a very large number of serially connected fine delay elements165to implement a fine delay element165calibration circuit similar to the calibration circuit300ofFIG. 3A.

FIG. 4Ais an illustration showing a fine delay element calibration circuit400, in accordance with one embodiment of the present invention. The calibration circuit400is defined to use a racing condition to measure the delay provided by the fine delay element165. An input register401is connected to receive a test data input signal (TDIN3). The test data input signal (TDIN3) is clocked through the input register401as the signal (OUT3), in accordance with a test clock signal (TCLK3). The signal (OUT3) is transmitted through a coarse delay element161, through a multiplexer403, to be received as a delayed test data signal (DIN3) at an input port of an output register405. The delayed test data signal (DIN3) received by the output register405is clocked through the output register405as the test data output signal (TDOUT3), in accordance with a delayed test clock signal (DCLK3). It should be appreciated that the multiplexer403is defined to mirror the multiplexer407, such that both the test data signal path and the test clock signal path include the same amount of multiplexer403/407delay.

The delay present between the test clock signal (TCLK3) and the delayed test clock signal (DCLK3) is adjustable via a delay chain409. The delay chain409includes a chain of serially connected fine delay elements165. The delay chain409includes a multiplexer407defined to transmit one of a number of multiplexer407input signals as the delayed test clock signal (DCLK3), in accordance with a delay select signal (DLYSEL3). The multiplexer407input signals include the original test clock signal (TCLK3) and the delayed clock signal present at an output node of each fine delay element165in the chain of serially connected fine delay elements165. Thus, each multiplexer407input signal represents the test clock signal (TCLK3) having a different amount of delay introduced therein. It should be appreciated that in various embodiments, the number (p) of fine delay elements165in the delay chain409can vary depending on the amount of signal delay provided by the coarse delay element161.

FIG. 4Bis an illustration showing waveforms associated with operation of the coarse delay element calibration circuit400, in accordance with one embodiment of the present invention. The calibration measurement is initiated by transmitting a pair of reset pulses411in the test clock signal (TCLK3) while maintaining a low state of the test data input signal (TDIN3) to clear the input and output registers401/405. Then, the test data input signal (TDIN3) is driven high. At this point, the calibration circuit400is prepared for racing of the test data input signal (TDIN3) and the test clock signal (TCLK3) to the output register405.

To initiate the signal race, the test clock signal (TCLK3) is pulsed. When the test clock signal (TCLK3) is pulsed, the high test data input signal (TDIN3) is clocked through the input register401as the signal (OUT3). The delayed test data signal (DIN3) then arrives at the output register405with the signal delay provided by the coarse delay element161and the multiplexer403. The delayed test clock signal (DCLK3) arrives at the clock port of the output register405with the selected delay (p*Δt2) provided by the delay chain409. If the data signal path has a longer delay than the test clock signal path, i.e., (Δt1>p*Δt2, where p is the number of fine delay elements165that are selected to contribute to the test clock signal delay), the output register405will not catch the high delayed test data signal (DIN3) and the test data output signal (TDOUT3) will remain low. If the data signal path has a shorter delay than the test clock signal path, i.e., (Δt1<p*Δt2), the output register405will catch the high delayed test data input signal (DIN3) and the test data output signal (TDOUT3) will go high. The fine delay element calibration is performed by incrementally increasing the test clock signal delay provided by the delay chain409until the output register405catches the high delayed test data signal (DIN3).

When the output register405catches the high delayed test data signal (DIN3), the skew between the test data signal path and the test clock signal path is less than a setup time of the output register405, e.g., less than about 30 picoseconds. When the output register405catches the high delayed test data signal (DIN3), the total signal delay provided by the selected number of fine delay elements165according to the select signal (DLYSEL3) is closely matched with the signal delay provided coarse delay element161. Thus, the signal delay provided by an individual fine delay element165can be calibrated as the signal delay provide by an individual coarse delay element divided by the selected number of fine delay elements165in the delay chain409when the output register405catches the high delayed test data signal (DIN3).

FIG. 5is an illustration showing a flowchart of a method for minimizing skew between a data signal and a data strobe signal, in accordance with one embodiment of the present invention. The method includes an operation501for calibrating a coarse delay element using a signal racing circuit. In one embodiment, the operation501is performed using the coarse delay element calibration circuit300as previously described with regard toFIGS. 3A-3B. The method includes another operation503for calibrating a fine delay element using a signal racing circuit. In one embodiment, the operation503is performed using the fine delay element calibration circuit400as previously described with regard toFIGS. 4A-4B.

The method continues with an operation505for measuring a signal delay in a data signal path using a signal racing circuit that implements the coarse and fine delay modules calibrated in operations501and503, respectively. In one embodiment, the operation505is performed using the signal delay measurement circuit200as previously described with regard toFIGS. 2A-2B, wherein the emulation module203is defined to emulate the data signal path. The method further includes an operation507for measuring a signal delay in a data strobe signal path using a signal racing circuit that implements the coarse and fine delay modules calibrated in operations501and503, respectively. In one embodiment, the operation507is performed using the signal delay measurement circuit200as previously described with regard toFIGS. 2A-2B, wherein the emulation module203is defined to emulate the data strobe signal path.

It should be appreciated that the method operations501,503,505, and507are performed using circuitry that is fabricated in situ on the actual device within which the skew between the data signal and the data strobe signal is to be minimized. Thus, the measured delay associated with each of the coarse and fine delay elements, the emulated data signal path, and the emulated data strobe signal path is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the data signal and data strobe signal will be transmitted.

The method continues with an operation509for determining the skew between the data signal and the data strobe signal. The skew is determined by calculating a difference in the measured delays for the data signal path and data signal strobe path. In an operation511, appropriate settings for the coarse and fine delay modules in each of the data signal path and data strobe path are determined such that skew between the data signal and data strobe signal is minimized. If the data signal is delayed relative to the data strobe signal, the coarse and fine delay modules for the data strobe signal path will be set to introduce delay in the data strobe signal path such that the data signal and data strobe signal are subject to approximately equivalent delays. Conversely, if the data strobe signal is delayed relative to the data signal, the coarse and fine delay modules for the data signal path will be set to introduce delay in the data signal path such that the data signal and data strobe signal are subject to approximately equivalent delays.

In an operation513, the coarse and fine delay module settings determined in the operation511are stored in non-volatile memory elements on the particular device. In one embodiment, the operations511and513are performed using the memory interface100configuration described with regard toFIGS. 1A-1D. It should be understood that the non-volatile memory element using in conjunction with operation513can be essentially any type of non-volatile memory, such as a poly fuse. It should be appreciated that because the skew adjustment provided by the method is tailored to a particular device, fabrication process variations which affect signal skew among different devices can be compensated for on a device-specific basis, thus optimizing individual device performance and improving device yield.

While this invention has been described in terms of several embodiments, it will be appreciated that those skilled in the art upon reading the preceding specifications and studying the drawings will realize various alterations, additions, permutations and equivalents thereof. Therefore, it is intended that the present invention includes all such alterations, additions, permutations, and equivalents as fall within the true spirit and scope of the invention.