MOSFET having a JFET embedded as a body diode

A field effect transistor, in accordance with one embodiment, includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode.

BACKGROUND OF THE INVENTION

Referring toFIG. 1, a cross sectional view of a trench metal-oxide-semiconductor field effect transistor (TMOSFET)100according to the conventional art is shown. The TMOSFET100includes a source contact110, a plurality of source regions115, a plurality of gate regions120, a plurality of gate insulator regions125, a plurality of body regions130,135a drain region140,145and drain contact150. The drain region140,145may optionally include a first drain region140and a second drain region145. The body regions may optionally include first body regions130and second body regions135.

The body regions130,135are disposed above the drain region140,145. The source regions115, gate regions120and the gate insulator regions125are disposed within the body regions130. The gate regions120and the gate insulator regions125may extend into a portion of the drain region140,145. The gate regions120and the gate insulator regions125are formed as parallel-elongated structures. The gate insulator regions125surround the gate regions120. Thus, the gate regions120are electrically isolated from the surrounding regions by the gate insulator regions125. The gate regions120are coupled to form a common gate of the device100. The source regions115are coupled to form a common source of the device100, by the source contacts110. The source contact110also couples the source regions115to the body regions130,135.

The source regions115and the drain regions140,145may be n-doped (N) semiconductor such as silicon doped with Phosphorus or Arsenic. The body regions130,135may be p-doped (P) semiconductor, such as silicon doped with Boron. The gate region120may be n-doped (N) semiconductor, such as polysilicon doped with Phosphorus. The gate insulator regions125may be an insulator, such as silicon dioxide.

When the potential of the gate regions120, with respect to the source regions115, is increased above the threshold voltage of the device100, a conducting channel is induced in the body regions130,135along the periphery of the gate insulator regions125. The TMSOFET100will then conduct current between the drain region140,145and the source regions115. Accordingly, the device is in its on state.

When the potential of the gate regions120is reduced below the threshold voltage, the channel is no longer induced. As a result, a voltage potential applied between the drain region140,145and the source regions115will not cause current to flow there between. Accordingly, the device100is in its off state and the junction formed by the body regions130,135and the drain region140,145supports the voltage applied across the source and drain.

If the drain region135,140includes a first drain region140disposed above a second drain region145, the first drain region140is lightly n-doped (N−) semiconductor, such as silicon doped with Phosphorus or Arsenic, and the second drain region145is heavily n-doped (N+) semiconductor, such as silicon doped with Phosphorus or Arsenic. If the body regions130,135include first body regions130disposed between the source regions115and the first drain region140proximate the gate regions120, the first body regions130are moderately to lightly p-doped (P or P−) semiconductor, such as silicon doped with Boron, and the second body regions235are heavily p-doped (P+) semiconductor, such as silicon doped with Boron. The first drain region140and the first body regions130reduce the punch through effect. Accordingly, the first drain region140and the first body regions130act to increase the breakdown voltage of the TMOSFET100.

Referring now toFIG. 2, a cross sectional view of a non-trench based metal-oxide-semiconductor field effect transistor (MOSFET)200according to the conventional art is shown. The MOSFET200includes a source contact210, a plurality of source regions215, a plurality of gate regions220, a plurality of gate insulator regions225, a plurality of body regions230,235a drain region240,245and a drain contact region250. The drain region240,245may optionally include a first drain region240and a second drain region245. The body regions230,235may optionally include first body regions230and second body regions235.

The source regions215are formed as parallel elongated structures disposed above the drain region240,245. The body regions230,235are disposed between the source regions215and the drain region240,245. The gate regions220are disposed above the drain regions240,245and the body regions230,235. The gate regions220are disposed between the source regions215above the drain regions240,245. Accordingly, a portion of the drain region240,245is disposed between the body regions230,235proximate the gate regions220. The gate insulator regions225surround the gate region220. Thus, the gate regions220are electrically isolated from the surrounding regions by the gate insulator regions225. The gate regions220may be coupled to form a common gate of the device200. The source contact210may be disposed on the source regions215and the body regions230,235. The source regions215may be coupled to form a common source of the device200, by the source contact210. The source contact210also couples the source regions215to the body regions230,235.

The source regions215and the drain region240,245may be n-doped semiconductor, such as silicon doped with Phosphorus or Arsenic. The body regions230,235may be p-doped semiconductor, such as silicon doped with Boron. The gate regions220may be n-doped semiconductor, such as polysilicon doped with Phosphorus. The gate insulator region225may be an insulator, such as silicon dioxide.

When the potential of the gate regions220, with respect to the source regions215, is increased above the threshold voltage of the device200, a conducting channel is induced in the body regions230,235between the source regions215and the drain region240,245proximate the gate regions220. The MOSFET200will then conduct current between the drain region240,245and the source regions215. Accordingly, the device200is in its one state.

When the potential of the gate regions220is reduced below the threshold voltage, the channel is no longer induced. As a result, a voltage potential applied between the drain region240,245and the source regions215will not cause current to flow there between. Accordingly, the device200is in its off state and the junction formed by the body regions230,235and the drain region240,245supports the voltage applied across the source and drain.

If the drain region240,245includes a first drain region240disposed above a second drain region245proximate the body regions230,235and the gate regions220, the first drain region240is moderately to lightly n-doped (N or N−) semiconductor and the second drain region245is heavily n-doped (N+) semiconductor. If the body regions230,235includes first body regions230disposed between the source regions215and the first drain region240proximate the gate regions220, the first body regions230are moderately to lightly p-doped (P or P−) semiconductor and the second body regions235are heavily p-doped (P+) semiconductor. The first drain region240and the first body regions230reduce the punch through effect. Accordingly, the first drain region240and the first body regions235act to increase the breakdown voltage of the MOSFET200.

However, the intrinsic P-N body diode in such conventional MOSFET devices exhibit a long reverse recovery time due to the nature of the P-N depletion region, leading to excessive power loss during switching. Furthermore, the conventional MOSFET devices exhibit relatively high forward voltage drops across the body diode. Accordingly, the reverse recovery is relatively long for current applications, such as high frequency switching mode DC-DC converters.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a field effect transistor comprising a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode. In one embodiment, the field effect transistor includes first and second gate regions, first and second source regions, first and second body regions, a drain region, a source contact, and first and second gate insulator regions. The first and second source regions may be disposed proximate respective first and second gate regions. The first and second body regions may be disposed adjacent the respective source regions proximate the corresponding gate regions. The drain region may be disposed between the first and second body regions proximate the first and second gate regions. Accordingly, the first and second body regions are disposed between the drain region and the respective source regions. The source contact electrically couples the first and second source regions, the first and second body regions and corresponding portions of the drain region disposed between the first and second body regions. The first and second gate insulator regions are disposed between the respective gate regions, source regions, body regions, drain regions and the source contact.

Embodiments of the present invention also provide methods of manufacturing a field effect transistor comprising a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode. In one embodiment, the method includes depositing a first semiconductor layer upon a substrate. The first semiconductor layer and substrate may be doped with a first type of impurity. A first portion of the first semiconductor layer may be doped with a second type of impurity to form a first plurality of well regions. A second portion of the first semiconductor layer may be doped with the second type of impurity to form a second plurality of well regions substantially centered within the first plurality of well regions. A third portion of the first semiconductor layer may be doped with the first type of impurity to form a third plurality of well regions substantially centered within the second plurality of well regions. A plurality of trenches may be etched in the first semiconductor layer substantially centered within the first, second and third plurality of well regions. A dielectric layer may be formed proximate the plurality of trenches and a second semiconductor layer may deposited in the plurality of trenches lined by the dielectric layer. The second dielectric layer may be doped with the first type of impurity. A metal layer may be deposited such that the first, second and third plurality of well regions and a fourth portion of the first semiconductor layer disposed between the second plurality of well regions are electrically coupled to each other.

Embodiments of the present invention provide FET devices having low leakage current and/or faster switching, as compared to conventional power MOSFET devices. Accordingly, the JFET devices may advantageously be utilized in many applications such as high-frequency DC-DC converters and the like.

DETAILED DESCRIPTION OF THE INVENTION

Referring toFIG. 3A, a cross sectional view of a field effect transistor (FET)300, in accordance with one embodiment of the present invention, is shown. The FET device300includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode. More specifically, the FET300includes a source contact310, a plurality of source regions315, a plurality of gate regions320, a plurality of gate insulator regions325, a plurality of body regions330,335, a drain region340,345and a drain contact350. The drain region340,345may optionally include a first drain region340and a second drain region345. The body regions330,335may optionally include first body regions330and second body regions335.

The source regions315may be formed as parallel elongated structures disposed above the drain region340,345and proximate the gate regions320. The body regions330,335may be disposed adjacent the source regions315and proximate the gate regions320. The drain region340,345may be disposed the body regions330,335and proximate the gate regions320. Accordingly, the body regions330,335are disposed between the source regions315and the drain region340,345. The gate regions320may be formed as parallel elongated structures disposed within the source regions315, the body regions330,335and the drain region340,345. The gate insulator regions325surround the gate regions320. Thus, the gate regions320are electrically isolated from the surrounding regions by the gate insulator regions325. The source contact310may be disposed on the source regions315, the body regions330,335and the drain regions340,345. Accordingly, the source contact310couples the source regions315to the body regions330,335and corresponding portion of the drain region340,345disposed between the body regions330,335.

The source regions315, the drain region340and the gate regions320may be a semiconductor having a first doping type. The body regions may be a semiconductor having a second doping type. In one implementation, the source regions315and the drain region340,345may be n-doped semiconductor such as silicon doped with Phosphorus or Arsenic. The body regions330,335may be p-doped semiconductor, such as silicon doped with Boron. The gate regions320may be n-doped semiconductor, such as polysilicon doped with Phosphorus. The gate insulator regions325may be an insulator, such as silicon dioxide.

In another implementation (FIG. 3B), the source regions315and the drain region340,350may be p-doped semiconductor such as silicon doped with Boron. The body regions330,335may be n-doped semiconductor, such as silicon doped with Phosphorus or Arsenic. The gate regions320may be p-doped semiconductor, such as polysilicon doped with Phosphorus. The gate insulator region325may be an insulator, such as silicon dioxide.

In another implementation (FIG. 3A), the source regions315may be heavily n-doped (N+) semiconductor, such as silicon doped with Phosphorus or Arsenic. The second drain region345proximate the drain contact350may be heavily n-doped (N+) semiconductor, such as silicon doped with Phosphorus or Arsenic. The first drain region340proximate the body region330,335may be moderately to lightly n-doped (N or N−) semiconductor, such as silicon doped with Phosphorus or Arsenic. The first body regions330disposed between the source regions315and the first drain region340proximate the gate regions320may be moderately to lightly p-doped (P or P−) semiconductor, such as silicon doped with Boron. The second body regions335proximate the source contact310may be heavily p-doped (P+) semiconductor, such as silicon doped with Boron. The gate region320may heavily n-doped (N+) semiconductor, such as polysilicon doped with Phosphorus. The gate insulator regions325may be an insulator, such as silicon dioxide. The source contact310may be a metal or a silicide.

In another implementation (FIG. 3B), the source regions315may be heavily p-doped (P+) semiconductor, such as silicon doped with Boron. The second drain region345proximate the drain contact350may be heavily p-doped (P+) semiconductor, such as silicon doped with Boron. The first drain region340proximate the body region330,335may be moderately to lightly p-doped (P or P−) semiconductor, such a silicon doped with Boron. The first body regions330disposed between the source regions315and the first drain region340proximate the gate regions320may be moderately to lightly n-doped (N or N−) semiconductor, such as silicon doped with Phosphorus or Arsenic. The second body regions335proximate the source contact310may be heavily n-doped (N+) semiconductor, such as silicon doped with Phosphorus or Arsenic. The gate region320may heavily p-doped (P+) semiconductor, such as polysilicon doped with Boron. The gate insulator regions325may be an insulator, such as silicon dioxide. The source contact310may be a metal or a silicide.

The gate regions320may be coupled to form a common gate of a trench metal-oxide-semiconductor field effect transistor (TMOSFET). The source regions315may be coupled to form a common source of the TMOSFET. The body regions330,335may be coupled to form a common body of the TMOSFET, while the portions of the body region disposed proximate the gate regions320form a conducting channel of the TMOSFET. The drain region340,345forms the drain of the TMOSFET.

In addition, the portions of the drain region340,345disposed between the body regions330,335forms a conducting channel of a junction field effect transistor (JFET). The body regions330,335form a gate of the JFET. The source contact310and the drain region340,345form the source and drain of the JFET. Furthermore, when the source contact310is a metal, a Schottky junction is formed at the interface between the source contact310and the drain region340,345. The Schottky junction in combination with the JFET form a gated Schottky diode. In the gate Schottky diode the gates pinch off the conduction channel during reverse bias, thereby increasing the breakdown voltage of the Schottky junction and reducing the leakage current. During reverse bias recovery, the Schottky diode increases minority carrier injection into the depletion region. In addition, the resulting body diode is in effect a merged PiN diode.

When the potential of the gate regions320, with respect to the source regions315, is increased above the threshold voltage of the device300, a conducting channel is induced in the body region330,335along the periphery of the gate insulator regions325. The TMOSFET will then conduct current between the drain region340,345and the source regions315. Accordingly, the device is in its on state.

When the potential of the gate regions320is reduced below the threshold voltage, the channel is no longer induced. As a result, a voltage potential applied between the drain region340,345and the source regions315will not cause current to flow there between. Accordingly, the TMOSFET is in its off state and the depletion region formed in the portion of the first drain region340, proximate the body regions330,335supports the voltage applied across the source and drain.

It is appreciated that above-described embodiments may be readily modified to form devices including a plurality of TMOSFETs arranged in stripe cells, hexagonal cells, mesh cells or the like configuration.

Referring now toFIGS. 4A,4B,4C and4D, a flow diagram of a method of fabricating a field effect transistor (FET) device, in accordance with one embodiment of the present invention, is shown. As depicted inFIG. 4A, the method begins, at405, with various initial processes upon a semiconductor substrate. The various initial processes may include cleaning, depositing, doping, etching and/or the like. The semiconductor substrate may contain a first type of dopant at a first concentration. In an n-channel MOSFET implementation, the substrate may be silicon, gallium arsenide, indium phosphide or the like, heavily doped with Phosphorus or Arsenic (N+) at a concentration of approximately 1.0E17 cm−3to 1.0E20 cm−3. In a p-channel MOSFET implementation, the substrate may be silicon, gallium arsenide, indium phosphide or the like, heavily doped with Boron (P+).

At410, a semiconductor layer may be epitaxial deposited upon the substrate. In one implementation, an epitaxial deposited layer of approximately 30 nano-meters (nm) to 400 nm is formed upon the substrate. The epitaxial deposited semiconductor layer may contain the first type of dopant at a second concentration. The semiconductor layer may be doped by introducing the dopant into the epitaxial chamber during deposition. The epitaxial deposited semiconductor layer may also be doped by an optional high-energy implant and thermal anneal process after deposition. In the n-channel MOSFET implementation, the epitaxial deposited semiconductor layer may be silicon, gallium arsenide, indium phosphide or the like, moderately to lightly doped with Phosphorus or Arsenic (N or N−) at a concentration of approximately 5.0E14 cm−3to 5.0E16 cm−3. In the p-channel MOSFET implementation, the epitaxial deposited semiconductor layer may be silicon, gallium arsenide, indium phosphide or the like, moderately to lightly doped with Boron (P or P−).

At415, a first photo-resist may be deposited and patterned by any well-known lithography process to define a plurality of body regions. At420, a second type of dopant may be selectively implanted in the portions of the epitaxial deposited semiconductor layer exposed by the patterned first photo-resist to form a first plurality of well regions. The dopant may be implanted utilizing any well-known ion-implant process at a first energy level. The first doping process results in the formation of first well regions having a second dopant at a third concentration. In the n-channel MOSFET implementation, the first well regions may be moderately to lightly doped with Boron (P or P−)) at a concentration of approximately 5.0E14 cm−3to 5.0E16 cm−3. In the p-channel MOSFET implementation, the first well regions may be moderately to lightly doped with Phosphorus or Arsenic (N or N−). The first wells form a plurality of lightly to moderately doped body regions of the TMOSFET.

At425, the second type of dopant may be selectively implanted in the portions of the epitaxial deposited semiconductor layer exposed by the patterned first photo-resist to form a second plurality of well regions disposed above the first well region. The second type of dopant may be implanted at a second energy level that is less than the first energy level. The second doping process results in the formation of second well regions having the second dopant at fourth concentration. In the n-channel MOSFET implementation, the second well regions may be heavily doped with Boron (P or P−) at a concentration of approximately 5.0E16 cm−3to 1.0E20 cm−3. In the p-channel MOSFET implementation, the second well regions may be heavily doped with Phosphorus or Arsenic (N or N−). The second wells form a plurality of heavily doped body regions of the TMOSFET. The first and second well regions also form a plurality of gate regions of a JFET. The channel of the JFET is formed by a portion of the epitaxial layer disposed between the well regions.

At430, the first patterned photo-resist is removed utilizing an appropriate resist stripper or resist ashing process. At435, a second photo-resist may be deposited and patterned by any well-known lithography process to define a plurality of source regions disposed within the body regions. The openings in the second pattern photo-resist are smaller than the first and second well regions. The openings in the second patterned photo-resist are aligned to be substantially centered within the first and second well regions. Referring now toFIG. 4B, the first type of dopant may be selectively implanted in the portions of the epitaxial deposited semiconductor layer exposed by the patterned second photo-resist to form the third plurality of well regions disposed above the first well regions and within the second well regions, at440. The dopant may be implanted at a third energy level. The third doping process results in the formation of third plurality of well regions having the first dopant at a fifth concentration. In the n-channel MOSFET implementation, the third well regions may be heavily doped with Phosphorus or Arsenic (N+) at a concentration of approximately 1.0E17 cm−3to 1.0E20 cm−3. In the p-channel MOSFET implementation, the third well regions may be heavily doped with Boron (P+). The third wells form a plurality of source regions of the TMOSFET.

At445, the second patterned photo-resist is removed utilizing an appropriate resist stripper or resist ashing process. At450, a third photo-resist may be deposited and patterned by any well-known lithography process to define a plurality of gate regions disposed within the source and body regions. The openings in the third patterned photo-resist are smaller than the third plurality of well regions. The openings in the third pattern photo-resist are aligned to be substantially centered within the first, second and third plurality of well regions. At455, the portions of the third, second and first well regions exposed by the third patterned photo-resist may be removed by any well-known etching process. In one implementation, the resulting trenches may extend into the epitaxial deposited layer just below the first well region.

At460, the third patterned photo-resist layer may be removed utilizing an appropriate resist stripper or resist ashing process. At465, a first dielectric layer may be formed in the epitaxial deposited layer proximate the trenches. The first dielectric layer may be formed by any well-known oxidation or deposition processes. In one implementation, the dielectric is formed by oxidizing the surface of the silicon proximate the trenches to form a silicon dioxide layer. In one implementation the first dielectric layer may be approximately 15 nm to 200 nm thick. The resulting dielectric along the trench walls forms first port-ion of a plurality of gate insulator regions of the TMOSFET.

Referring now toFIG. 4C, a second semiconductor layer may be deposited in the trenches to form a plurality gate regions of the TMOSFET, at470. In one implementation, the polysilicon is deposited in the trenches by a method such as decomposition of silane (SiH4). The polysilicon may be doped by introducing the impurity during the deposition process or in a separate doping process. In the n-channel MOSFET implementation, the polysilicon may be heavily doped with Phosphorus or Arsenic (N+) at a concentration of approximately 1.0E17 cm−3to 1.0E20 cm−3. In the p-channel MOSFET implementation, the polysilicon may be heavily doped with Boron (P+). At475, an etch-back process is performed to remove excess polysilicon on the surface of the wafer. The excess polysilicon may be removed utilizing an appropriate etching and/or chemical-mechanical polishing (CMP) process.

At480, a second dielectric layer is formed on the wafer to complete the gate insulator regions disposed about the gate regions. The second dielectric layer may be formed by any well-known oxidation or deposition processes. At482, a fourth photo-resist may be deposited and patterned by any well-known lithography process to define a plurality of source-body contact openings between the gate regions. At484, the portions of the second dielectric layer exposed by the fourth patterned photo-resist may be removed by any well-known etching process. At486, the fourth patterned photo-resist layer may be removed utilizing an appropriate resist stripper or resist ashing process.

Referring now toFIG. 4D, a metal layer is deposited on the surface of the wafer, at488. The deposited metal may be deposited such that the first, second and third plurality of well regions and a fourth portion of the first semiconductor layer disposed between the second plurality of well regions are electrically coupled to each other. In one implementation, the source-body metal layer is deposited by any well-known method such as sputtering. The source-body metal layer forms a contact with the body and source regions left exposed by the patterned second dielectric layer. The source-body metal layer is isolated from the gate region by the patterned first and second dielectric layers. The source-body metal layer also forms a Schottky barrier at the interface of the epitaxial deposited layer disposed between the first, second and third well regions. In one implementation, the metal layer may be titanium, cobalt, platinum, their silicides or the like. The metal layer is then patterned utilizing a photo-resist mask and selective etching method to form source-body contact, at490. At492, fabrication continues with various other processes. The various processes typically include etching, deposition, doping, cleaning, annealing, passivation, cleaving and/or the like.

Referring now toFIG. 5, a cross sectional view of a field effect transistor (FET)500, in accordance with another embodiment of the present invention, is shown. The FET device500includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a junction field effect transistor (JFET) embedded as a body diode. More specifically, the FET500includes a source contact510, a plurality of source regions515, a plurality of gate regions520, a plurality of gate insulator regions525, a plurality of body regions530,535, a drain region540,545and a drain contact550. The drain region540,545may optionally include a first drain region540and a second drain region545. The body regions530,535may optionally include first body regions530and second body regions535.

The source regions515may be formed as parallel elongated structure disposed above the drain region540,545and proximate the gate regions. The body regions530,535may be disposed adjacent the source regions515and proximate the gate regions530,535. The gate regions520may be formed disposed above the drain region540,545and a portion of the body regions530,535. The drain regions540,545may be disposed between the body region530,535and proximate the gate regions. Accordingly, the body regions530,535are disposed between the source regions515and the drain regions540,545. The gate insulator regions525surround the gate regions520. Thus, the gate regions520are electrically isolated from the surrounding regions by the gate insulator regions525. The source contact510may be disposed upon the source regions515, the body regions530,535and the drain regions540,545between the gate regions520. Accordingly, the source contact510couples the source regions515to the body regions530,535and corresponding portions of the drain region340,345disposed between the body regions330,335.

The source regions515, the drain region540,545and the gate regions520may be a semiconductor having a first doping type. The body regions530,535may be a semiconductor having a second doping type. In one implementation, the source regions515and the drain region540,545may be n-doped semiconductor such as silicon doped with Phosphorus or Arsenic. The body regions530,535may be p-doped semiconductor, such as silicon doped with Boron. The gate regions520may be n-doped semiconductor, such as polysilicon doped with Phosphorus. The gate insulator regions525may be an insulator, such as silicon dioxide.

In another implementation, the source regions515and the drain region540,550may be p-doped semiconductor such as silicon doped with Boron. The body regions530,535may be n-doped semiconductor, such as silicon doped with Phosphorus or Arsenic. The gate regions520may be p-doped semiconductor, such as polysilicon doped with Phosphorus. The gate insulator region525may be an insulator, such as silicon dioxide.

In another implementation, the source regions515may be heavily n-doped (N+) semiconductor, such as silicon doped with Phosphorus or Arsenic. The second drain region545proximate the drain contact550may be heavily n-doped (N+) semiconductor, such as silicon doped with Phosphorus or Arsenic. The first drain region540proximate the body region530,535may be moderately to lightly n-doped (N or N−) semiconductor, such a silicon doped with Phosphorus or Arsenic. The first body regions530disposed between the source regions515and the first drain region540proximate the gate regions520may be moderately to lightly p-doped (P or P−) semiconductor, such as silicon doped with Boron. The second body regions535proximate the source contact510may be heavily p-doped (P+) semiconductor, such as silicon doped with Boron. The gate region520may heavily n-doped (N+) semiconductor, such as polysilicon doped with Phosphorus. The gate insulator regions525may be an insulator, such as silicon dioxide. The source contact510may be a metal or a silicide.

In another implementation, the source regions515may be heavily p-doped (P+) semiconductor, such as silicon doped with Boron. The second drain region545proximate the drain contact550may be heavily p-doped (P+) semiconductor, such as silicon doped with Boron. The first drain region540proximate the body region530,535may be moderately to lightly p-doped (P or P−) semiconductor, such a silicon doped with Boron. The first body regions330disposed between the source regions515and the first drain region540proximate the gate regions520may be moderately to lightly n-doped (N or N−) semiconductor, such a silicon doped with Phosphorus or Arsenic. The second body regions535proximate the source contact510may be heavily n-doped (N+) semiconductor, such as silicon doped with Phosphorus or Arsenic. The gate region520may heavily p-doped (P+) semiconductor, such as polysilicon doped with Boron. The gate insulator regions525may be an insulator, such as silicon dioxide. The source contact510may be a metal or a silicide.

The gate regions520may be coupled to form a common gate of a non-trench metal-oxide-semiconductor field effect transistor (MOSFET). The source regions515may be coupled to form a common source of the MOSFET. The body regions530,535may be coupled to form a common body of the MOSFET, while the portions of the body region disposed proximate the gate regions520form a conducting channel of the MOSFET. The drain region340,345forms the drain of the MOSFET.

In addition, the portions of the drain region540,545disposed between the body regions530,535forms a conducting channel of a junction field effect transistor (JFET). The body regions530,535form a gate of the JFET. The source contact510and the drain region540,545form the source and drain of the JFET. Furthermore, when the source contact510is a metal, a Schottky junction is formed at the interface between the source contact510and the drain region540,545. The Schottky junction in combination with the JFET form a gated Schottky diode. In the gate Schottky diode the gates pinch off the conduction channel during reverse bias, thereby increasing the breakdown voltage of the Schottky junction and reducing the leakage current. During reverse bias recovery, the Schottky diode increases minority carrier injection into the depletion region. In addition, the resulting body diode is in effect a merged PiN diode.

When the potential of the gate regions520, with respect to the source regions515, is increased above the threshold voltage of the device500, a conducting channel is induced in the body region530,535along the periphery of the gate insulator regions525. The MOSFET will then conduct current between the drain region540,545and the source regions515. Accordingly, the device is in its on state.

When the potential of the gate regions520is reduced below the threshold voltage, the channel is no longer induced. As a result, a voltage potential applied between the drain region540,545and the source regions515will not cause current to flow there between. Accordingly, the MOSFET is in its off state and the depletion region formed in the portion of the first drain region540, proximate the body regions530,535supports the voltage applied across the source and drain.

It is appreciated that above-described embodiments may be readily modified to form devices including a plurality of MOSFETs arranged in stripe cells, hexagonal cells, mesh cells or the like configuration.

Referring now toFIGS. 6A,6B,6C and6D, a flow diagram of a method of fabricating a field effect transistor (FET) device, in accordance with another embodiment of the present invention, is shown. As depicted inFIG. 6A, the method begins, at605, with various initial processes upon a semiconductor substrate. The various initial processes may include cleaning, depositing, doping, etching and/or the like. The semiconductor substrate may contain a first type of dopant at a first concentration. In an n-channel MOSFET implementation, the substrate may be silicon, gallium arsenide, indium phosphide or the like, heavily doped with Phosphorus or Arsenic (N+) at a concentration of approximately 1.0E17 cm−3to 1.0E20 cm−3. In a p-channel MOSFET implementation, the substrate may be silicon, gallium arsenide, indium phosphide or the like, heavily doped with Boron (P+).

At610, a semiconductor layer may be epitaxial deposited upon the substrate. In one implementation, an epitaxial deposited layer of approximately 30 nano-meters (nm) to 400 nm is formed upon the substrate. The epitaxial deposited semiconductor layer may contain the first type of dopant at a second concentration. The semiconductor layer may be doped by introducing the dopant into the epitaxial chamber during deposition. The epitaxial deposited semiconductor layer may also be doped by an optional high-energy implant and thermal anneal process after deposition. In the n-channel MOSFET implementation, the epitaxial deposited semiconductor layer may be silicon, gallium arsenide, indium phosphide or the like, moderately to lightly doped with Phosphorus or Arsenic (N or N−) at a concentration of approximately 5.0E14 cm−3to 5.0E16 cm−3. In the p-channel MOSFET implementation, the epitaxial deposited semiconductor layer may be silicon, gallium arsenide, indium phosphide or the like, moderately to lightly doped with Boron (P or P−).

At615, a first photo-resist may be deposited and patterned by any well-known lithography process to define a plurality of body regions. At620, a second type of dopant may be selectively implanted in the portions of the epitaxial deposited semiconductor layer exposed by the patterned first photo-resist to form a first plurality of well regions. The dopant may be implanted utilizing any well-known ion-implant process at a first energy level. The first doping process results in the formation of first well regions having a second dopant at a third concentration. In the n-channel MOSFET implementation, the first well regions may be moderately to lightly doped with Boron (P or P−)) at a concentration of approximately 5.0E14 cm−3to 5.0E16 cm−3. In the p-channel MOSFET implementation, the first well regions may be moderately to lightly doped with Phosphorus or Arsenic (N or N−). The first wells form a plurality of lightly to moderately doped body regions of the MOSFET.

At622, the first patterned photo-resist is removed utilizing an appropriate resist stripper or resist ashing process. At optional process624, a second photo-resist may be deposited and patterned by any well-known lithography process to define a second plurality of wells disposed within the first plurality of wells. At626, the second type of dopant may be selectively implanted in the portions of the epitaxial deposited semiconductor layer exposed by the patterned second photo-resist to form a second plurality of well regions disposed within the first plurality of well regions. The second type of dopant may be implanted at a second energy level that is less than the first energy level. The second doping process results in the formation of second well regions having the second dopant at fourth concentration. In the n-channel MOSFET implementation, the second well regions may be heavily doped with Boron (P or P−) at a concentration of approximately 5.0E16 cm−3to 1.0E20 cm−3. In the p-channel MOSFET implementation, the second well regions may be heavily doped with Phosphorus or Arsenic (N or N−). The second wells form a plurality of heavily doped body regions of the MOSFET. The first and second well regions also form a plurality of gate regions of a JFET. The channel of the JFET is formed by a portion of the epitaxial deposited layer disposed between the second plurality of well regions.

Referring now toFIG. 6B, the second patterned photo-resist is removed utilizing an appropriate resist stripper or resist ashing process, at630. At635, a third photo-resist may be deposited and patterned by any well-known lithography process to define a plurality of a third set of wells disposed within the first set of wells. The openings in the third pattern photo-resist are smaller than the first and second well regions. The openings in the third patterned photo-resist are aligned to be substantially centered within the first plurality of well regions. At640, the first type of dopant may be selectively implanted in the portions of the epitaxial deposited semiconductor layer exposed by the patterned third photo-resist to form a third plurality of well regions disposed within the first and second well regions. The dopant may be implanted at a third energy level. The third doping process results in the formation of third well regions having the first dopant at a fifth concentration. In the n-channel MOSFET implementation, the third well regions may be heavily doped with Phosphorus or Arsenic (N+) at a concentration of approximately 1.0E17 cm−3to 1.0E20 cm−3cm. In the p-channel MOSFET implementation, the third well regions may be heavily doped with Boron (P+). The third wells form a plurality of source regions of the MOSFET.

At642, the third patterned photo-resist is removed utilizing an appropriate resist stripper or resist ashing process. At645, a first dielectric layer may be formed on the wafer. The first dielectric layer may be formed by any well-known oxidation or deposition processes. In one implementation, the dielectric is formed by oxidizing the surface of the silicon wafer to form a silicon dioxide layer. In one implementation the first dielectric layer may be approximately 15 nm to 200 nm thick. The resulting dielectric forms a portion of a plurality of gate insulator regions of the MOSFET upon a fourth portion of the first semiconductor layer proximate the first plurality of well regions.

At650, a polysilicon layer is deposited on the first dielectric layer. In one implementation, the polysilicon is deposited by a method such as decomposition of silane (SiH4). The polysilicon may be doped by introducing the impurity during the deposition process or in a separate doping process. In the n-channel MOSFET implementation, the polysilicon may be heavily doped with Phosphorus or Arsenic (N+) at a concentration of approximately 1.0E17 cm−3to 1.0E20 cm−3. In the p-channel MOSFET implementation, the polysilicon may be heavily doped with Boron (P+). At655, a fourth photo-resist may be deposited and patterned by any well-known lithography process to define the gate regions. Referring now toFIG. 6C, the portions of the first dielectric layer, polysilicon layer and second dielectric layer exposed by the fourth patterned photo-resist may be removed by any well-known etching process, at660. At665, the fourth patterned photo-resist layer may be removed utilizing an appropriate resist stripper or resist ashing process.

At670, a second dielectric layer is on the wafer. The second dielectric layer completes the gate insulator regions disposed about the gate regions. The second dielectric layer may be formed by any well-known oxidation processes. At675, a fifth photo-resist may be deposited and patterned by any well-known lithography process to define a plurality of source-body contact openings between the gate regions. At680, the portions of the second dielectric layer exposed by the fifth patterned photo-resist may be removed by any well-known etching process. At682, the fifth patterned photo-resist layer may be removed utilizing an appropriate resist stripper or resist ashing process.

Referring now toFIG. 6D, a source-body metal layer is deposited on the surface of the wafer, at684. The source-body metal layer may be deposited such that the first second and third plurality of well regions and a fourth portion of the first semiconductor layer disposed between the second plurality of well regions are electrically coupled to each other. In one implementation, the source-body metal layer is deposited by any well-known method such as sputtering. The source-body metal layer forms a contact with the body and source regions left exposed by the patterned second dielectric layer. The source-body metal layer is isolated from the gate region by the patterned first second and third dielectric layers. The source-body metal layer also forms a Schottky barrier at the interface of the epitaxial deposited layer disposed between the first, second and third well regions. The source-body metal layer is then patterned utilizing a photo-resist mask and selective etching method as needed, at686. At688, fabrication continues with various other processes. The various processes typically include etching, deposition, doping, cleaning, annealing, passivation, cleaving and/or the like.

Accordingly, embodiments of the present invention provide JFET devices provide JFET devices having reduced leakage current and/or faster switching, as compared to conventional power MOSFET devices. The JFET devices having reduced leakage current and/or faster switching characteristics may advantageously be utilized in many applications such as high-frequency DC-DC converters and the like.