Display device and method to control driving voltages based on changes in display image frame frequency

A display device includes a display panel having a plurality of gate lines and a plurality of data lines crossing each other and pixels formed at intersections thereof; a gate driving circuit that generates a gate pulse based on a gate power voltage and applies the gate pulse to the gate lines; a data driving circuit that divides the data power voltage to convert input digital video data into an analog data voltage and applies the data voltage to the data lines; a power voltage control circuit that detects an input frame frequency and generates a different power control signal in accordance with the detected frame frequency; and a power voltage adjusting circuit that adjusts at least one of the gate power voltage and the data power voltage differently from a predetermined reference level in response to the power control signal.

This application claims the priority and the benefit under 35 U.S.C. §119(a) on Patent Application No. 10-2011-0064380 filed in Republic of Korea on Jun. 30, 2011, the entire contents of which are hereby incorporated by reference.

BACKGROUND

1. Field of the Invention

Embodiments of the disclosure relate to a display device, and more particularly, to a display device, which can change a frame frequency based on the properties of a display image.

2. Discussion of the Related Art

Known display devices for image display include a cathode ray tube, a liquid crystal display LCD, an organic light emitting diode OLED, a plasma display panel (PDP), and an electrophoretic display (EPD).

The display devices include a display panel on which pixels and signal lines are formed, a driving circuit unit for driving the signal lines of the display panel, and a power voltage generating circuit for generating a power voltage required to drive the driving circuit unit.

The signal lines comprise data lines supplied with data voltages and gate lines supplied with gate pulses for selecting pixels supplied with data voltages. The driving circuit unit comprises a data driving circuit for driving the data lines and a gate driving circuit for driving the gate lines. The power voltage generating circuit supplies a data power voltage to the data driving circuit, and supplies a gate high voltage and a gate low voltage (a gate power voltage) to the gate driving circuit. The data power voltage is fixed, and the gate power is fixed.

For such a display device, the technology for changing the frame frequency according to the properties of a display image is known. In this technology, the frame frequency of a dynamic image showing a relatively large change in the image between adjacent frames is controlled to be a first value (e.g., 60 Hz), and the frame frequency of a static image showing a relatively small change in the image between the adjacent frames is controlled to be a second value (e.g., 40 Hz). The displaying of an image at a frame frequency of 40 Hz has the advantage of lower power consumption compared to the displaying of an image at a frame frequency of 60 Hz.

As shown inFIG. 1, when the frame frequency is changed, 1 horizontal period (1H), i.e., charging time, for charging a data voltage in the pixels is varied. The charging time at the frame frequency of 40 Hz is longer than the charging time at the frame frequency of 60 Hz. As a result, the charging amount CA2at the frame frequency of 40 Hz is more than the charging amount CA1at the frame frequency of 60 Hz. In realizing the same gray level, a charging amount difference depending on frame frequency causes a change in the luminance of the display image, thereby degrading the display quality. InFIG. 1, ‘GP’ represents a gate pulse, and ‘CP’ represents a data voltage charging pulse.

The reason why the charging amount varies depending on frame frequency is because the power voltage required for driving the driving circuit unit is generated at a fixed level. Particularly, if the frame frequency is decreased from 60 Hz to 40 Hz when the power voltage is fixed, the effect of power consumption reduction is not high.

BRIEF SUMMARY

In one aspect, there is a display device including a display panel having a plurality of gate lines and a plurality of data lines crossing each other and pixels formed at intersections thereof; a gate driving circuit that generates a gate pulse based on a gate power voltage and applies the gate pulse to the gate lines; a data driving circuit that divides the data power voltage to convert input digital video data into an analog data voltage and applies the data voltage to the data lines; a power voltage control circuit that detects an input frame frequency and generates a different power control signal in accordance with the detected frame frequency; and a power voltage adjusting circuit that adjusts at least one of the gate power voltage and the data power voltage differently from a predetermined reference level in response to the power control signal.

Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. It will be paid attention that detailed description of known arts will be omitted if it is determined that the arts can mislead the embodiments of the invention.

Exemplary embodiments of the invention will be described in detail with reference toFIGS. 2 to 12.

FIG. 2is a block diagram showing a display device according to an exemplary embodiment of the present invention.

The display device according to the exemplary embodiment of the present invention may be implemented as a liquid crystal display LCD, an organic light emitting diode OLED, a plasma display panel PDP, and an electrophoretic display EPD. Hereinafter, the exemplary embodiment will be described, taking an example in which the display device is implemented as a liquid crystal display.

Referring toFIG. 2, the display device comprises a system board10, a timing controller11, a data driving circuit12, a gate driving circuit13, a display panel14, a power voltage control circuit111, and a power voltage adjusting circuit17.

The system board10is connected to an external video source interface circuit (not shown) and receives image data from the external video source interface circuit. The system board10comprises a graphic processing circuit (not shown) for processing input image data and a power supply circuit for generating a voltage Vin to be supplied to the power adjusting circuit17.

The system board10changes the frame frequency according to the properties of image data inputted from the external video source interface circuit. The system board10controls the frame frequency of a dynamic image showing a relatively large change in the image between adjacent frames to be a reference value and controls the frame frequency of a static image showing a relatively small change in the image between the adjacent frames to be a specific value smaller than the reference value. The reference value may be 60 Hz, but is not limited thereto. The specific value may be 40 Hz, but is not limited thereto. For example, when the reference value is 60 Hz, 75 Hz, 120 Hz, and 240 Hz, the specific value may be 40 Hz, 60 Hz, 60 Hz, and 120 Hz. The embodiment of the invention is described based on the reference value of 60 Hz and the specific value of 40 Hz for the sake of brevity and ease of reading. The system board10outputs digital video data RGB and timing signals Vsync, Hsync, and DE of the dynamic image based on the frame frequency of 60 Hz. Also, the system board10outputs digital video data RGB of a static image and timing signals Vsync, Hsync, and DE based on the frame frequency of 40 Hz. The timing signal Vsync is a vertical synchronization signal. The timing signal Hsync is a horizontal synchronization signal. The timing signal DE is a data enable signal.

The timing controller11aligns digital video data RGB inputted from the system board10in accordance with the display panel14and supplies the digital video data RGB to the data driving circuit12.

The timing controller11receives timing signals Vsync, Hsync and DE from the system board10. The timing controller11generates data control signals for controlling the operation timing of the data driving circuit12using the timing signals Vsync, Hsync, and DE based on the frame frequency of 60 Hz or 40 Hz and gate control signals for controlling the operation timing of the gate driving circuit13.

The data control signals are for controlling the operation timing of the data driving circuit12based on the frame frequency of 60 Hz or 40 Hz, and comprise a source start pulse SSP, a source sampling clock SSC, a source output enable SOE and a polarity control signal POL. The source start pulse SSP controls a data sampling start point of the data driving circuit12. The source sampling clock SSC is a clock signal for controlling a sampling operation of data within the source drive integrated circuit (IC) of the data driving circuit12based on a rising or falling edge. The polarity control signal POL inverts the polarity of a data voltage outputted from the data driving circuit12every N horizontal period, and N is a positive integer. The source output enable signal SOE controls the output timing of the data driving circuit12.

The gate control signals are for controlling the operation timing of the gate driving circuit13based on the frame frequency of 60 Hz or 40 Hz, and comprise a gate start pulse GSP, a gate shift clock GSC and a gate output enable GOE. The gate start pulse GSP controls the timing of a first gate pulse applied to a first gate line. The gate shift clock GSC is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output timing of the gate driving circuit13.

The data driving circuit12comprises a plurality of source drive ICs. Each of the source drive ICs samples and latches the digital video data RGB received from the timing controller11in response to the data control signal from the timing controller11and converts the latched digital video data RGB into parallelized data. Each source drive IC converts the parallelized data into an analog gamma compensation voltage and generates positive and negative analog video data voltages by which the pixels are charged. Each source driver IC inverts the polarities of the positive and negative analog data voltages under the control of the timing controller11and supplies the inverted analog data voltages to the data lines15.

The gate driving circuit13comprises a plurality of gate driving ICs. Each of the gate driving ICs generates a gate pulse swinging between a gate high voltage VGH and a gate low voltage VGL in response to the gate control signals GSP, GSC and GOE outputted from the timing controller11, and sequentially supplies the gate pulse to the gate lines16. The gate driving circuit13may be formed in a GIP (Gate In Panel) type and be disposed in a non-display area outside an effective display area with a pixel array in the display panel14. By the GIP method, the gate driving circuit13may be formed together with the pixel array in the TFT process of the pixel array.

The display panel14may be implemented as a liquid crystal display panel. The display panel14comprises an upper glass substrate and a lower glass substrate both of which face to each other with a liquid crystal layer interposed therebetween. A pixel array for image display is formed on the lower glass substrate of the display panel14and includes TFTs, pixel electrodes1, a common electrode2and a storage capacitor Cst. The TFTs are formed at intersections of the data lines15and the gate lines16. The pixel electrodes1connect to the TFTs. The common electrode2faces the pixel electrode1. The storage capacitor Cst connects to the TFTs and the pixel electrodes1. Liquid crystal cells Clc are connected to the TFTs and driven by an electric field between the pixel electrodes1and the common electrode2.

Black matrices, color filters, etc. are formed on the upper glass substrate of the display panel14. The common electrode2may be formed on the lower glass substrate together with the pixel electrodes1in a horizontal electric field driving method such as an in-plane switching (IPS) mode or a fringe field switching (FFS) mode. The common electrode2may be formed on the lower glass substrate along with the pixel electrodes1in a horizontal electric field driving method such as an in-plane switching (IPS) mode or a fringe field switching (FFS) mode.

Polarizing plates are respectively attached to the upper and lower glass substrates of the display panel14, and alignment films for setting a pre-tilt angle of liquid crystals are respectively formed on the upper and lower glass substrates of the display panel14.

A liquid crystal mode for the display panel14applicable in the present invention may be implemented by any other liquid crystal modes as well as the TN mode, the VA mode, the IPS mode and the FFS mode. Moreover, the display of the present invention may be implemented in any form such as a transmissive liquid crystal display, a semi-transmissive liquid crystal display and a reflective liquid crystal display. For the transmissive liquid crystal display and the semi-transmissive liquid crystal display, a backlight unit is required. The backlight unit may be a direct type backlight unit or an edge type backlight unit.

The power voltage control circuit111detects an input frame frequency by timing signals Vsync, Hsync, and DE inputted from the system board10and generates a power control signal CONT according to the detected frame frequency. The power voltage control circuit111may be incorporated in the timing controller11. The power voltage control circuit111will be described later in conjunction withFIGS. 3 and 4.

The power voltage adjusting circuit17generates a gate power voltage, a data power voltage and a common voltage Vcom based on the voltage Vin inputted from the system board10. The data power voltage comprises a high potential power voltage VDD, which is applied to a high potential input end of a gamma resistor string incorporated in the data driving circuit12. The gate power voltage comprises a gate high voltage VGH and a gate low voltage VGL both of which are applied to the gate driving circuit13. The gate high voltage VGH is generated at a level for turning on the TFTs of the display panel14, and the gate low voltage VGL is generated at a level for turning off the TFTs of the display panel14. The common voltage Vcom is applied to the common electrode2of the display panel14.

To minimize luminance changes and increase the effect of power consumption reduction when the frame frequency is changed depending on the properties of an image, the power voltage adjusting circuit17adjusts the gate power voltage and/or data power voltage in response to a power control signal CONT inputted from the power voltage control circuit111. The power voltage adjusting circuit17will be described later in conjunction withFIG. 3andFIGS. 5 to 11.

FIG. 3shows the detailed configuration of the power voltage control circuit111and the output of the power voltage adjusting circuit17in response to the power control signal CONT which may be comprise a first power control signal VC1and a second power control signal VC2.FIG. 4shows a frame frequency detection operation of the power voltage control circuit111.

Referring toFIG. 3, the power voltage control circuit111comprises a counter111A and a comparator111B.

The counter111A outputs a count value CT by counting the vertical synchronization signal Vsync inputted from the system board10by using a reference clock RCLK. The vertical synchronization signal Vsync may be counted directly by the timing controller11according to the data enable signal DE inputted from the system board10. The reference clock RCLK may be generated by an oscillator incorporated in the timing controller11.

One frame period1F defined by the vertical synchronization signal Vsync is varied depending on frame frequency. One frame period1F corresponding to a specific frame frequency of 40 Hz is longer than one frame period1F corresponding to the reference frame frequency of 60 Hz. Accordingly, the count value CT for the frame frequency of 40 Hz based on the same reference clock RCLK is greater than the count value CT for the frame frequency of 60 Hz.

The comparator111B compares a count value CT inputted from the counter111A with a preset reference value REF. The reference value REF is set to be the same as the count value CT for the reference frame frequency of 60 Hz. If the count value CT inputted from the counter111A is the same as the reference value REF, the comparator111B outputs a first power control signal VC1corresponding to the reference frame frequency of 60 Hz. If the count value CT inputted from the counter111A is greater than the reference value REF, the comparator111B outputs a second power control signal VC2corresponding to a specific frame frequency of 40 Hz.

The first power control signal VC1is inputted into the power voltage adjusting circuit17to control the power voltage adjusting circuit17so that the gate power voltage and data power voltage is maintained at a predetermined reference level VDD1/VGH1. The second power control signal VC2is inputted into the power voltage adjusting circuit17to control the power voltage adjusting circuit17so that the gate power voltage and/or data power voltage is changed to an adjusted level VDD2/VGH2lower than the reference level VDD1/VGH1.

FIG. 5shows a gamma resistor string incorporated in the data driving circuit.FIG. 6shows an example in which the data power voltage is adjusted depending on frame frequency.FIG. 7shows an operational effect of data power voltage control. InFIG. 7, ‘GP’ represents a gate pulse, and ‘CP’ represents a data voltage charging pulse.

Referring toFIG. 5, the data driving circuit comprises a gamma resistor string for converting digital video data into an analog data voltage. The gamma resistance string is provided with a plurality of resistors R serially connected between a high potential end into which a high potential power voltage VDD is inputted and a low potential end into which a ground voltage VSS is inputted. The gamma resistor string subdivides gamma reference voltages divided between the high potential power voltage VDD and the ground voltage VSS into a number of gray levels representable in the number of bits of the digital video data, thereby generating positive gamma compensation voltages PGMA1to PGMAi and negative gamma compensation voltages NGMA1to NGMAi corresponding to each gray level.

Referring toFIG. 6, at the reference frame frequency of 60 Hz, the high potential power voltage VDD is generated at a predetermined reference level VDD1in accordance with the reference frame frequency of 60 Hz in response to a first power control signal VC1. At a specific frame frequency of 40 Hz, the high potential power voltage VDD is generated at an adjusted level VDD2lower than the reference level VDD1in response to a second power control signal VC2.

As shown inFIG. 7, when the frame frequency is changed, one horizontal period1H, i.e., charging time, for supplying a data voltage to the pixels is varied. The charging time at the frame frequency of 40 Hz is longer than the charging time at the frame frequency of 60 Hz. If the high potential power voltage VDD is maintained at the reference level VDD1when the frame frequency is changed from 60 Hz to 40 Hz, a luminance change occurs due to a difference of the charging amount as in the conventional art. However, if the high potential power voltage VDD is lowered to the adjusted level VDD2when the frame frequency is changed from 60 Hz to 40 Hz, luminance changes are minimized. This is because, if the high potential power voltage VDD is lowered to the adjusted level VDD2at 40 Hz, the overall voltage level of the gamma compensation voltages is also decreased, and therefore the charging amount to be charged in the pixels is decreased. As shown inFIG. 7, the adjusted level VDD2may be preset such that the pixel charging amount CA2at the specific frame frequency of 40 Hz is substantially identical to the pixel charging amount CA1at the frame frequency of 60 Hz.

If the high potential power voltage VDD is adjusted as described above, following a frame frequency change depending on the properties of an image, the luminance changes caused by the frequency change can be minimized. Moreover, the output swing width of a data driving circuit is decreased in realizing a static image, thereby maximizing the effect of power consumption reduction.

FIG. 8shows an example in which the gate power voltage is adjusted depending on frame frequency.FIG. 9shows the connection configuration of TFTs formed on a display panel.FIG. 10shows a graph of the driving characteristics of the TFTs.FIG. 11shows an operational effect of gate power voltage adjustment. InFIG. 11, ‘GP’ represents a gate pulse, and ‘CP’ represents a data voltage charging pulse.

Referring toFIG. 8, at the reference frame frequency of 60 Hz, the gate high voltage VGH is generated at a predetermined reference level VGH1in accordance with the reference frame frequency of 60 Hz in response to a first power control signal VC1. At a specific frame frequency of 40 Hz, the gate high voltage VGH is generated at an adjusted level VGH2lower than the reference level VGH1in response to a second power control signal VC2.

As shown inFIG. 9, the TFT comprises a gate electrode G connected to a gate line16, a source electrode S connected to a data line15, and a drain electrode D connected to a pixel electrode1. The TFT is turned on during the application of a gate pulse at a gate high voltage VGH to permit a current path between the data line15and the pixel electrode1, and turned off during the application of a gate pulse at a gate low voltage VGL to block the current path between the data line15and the pixel electrode1.

The current Ids flowing between the source electrode S and drain electrode D of the TFT is determined by a voltage difference Vgs between the gate electrode G and source electrode S of the TFT as shown inFIG. 10. The less the voltage difference Vgs between the gate electrode G and source electrode S of the TFT, the current Ids flowing between the source electrode S and drain electrode D of TFT is reduced.

As shown inFIG. 11, when the frame frequency is changed, one horizontal period1H, i.e., charging time, for supplying a data voltage to the pixels is varied. The charging time at the frame frequency of 40 Hz is longer than the charging time at the frame frequency of 60 Hz. If the gate high voltage VGH is maintained at the reference level VGH1when the frame frequency is changed from 60 Hz to 40 Hz, a luminance change occurs due to a difference of the charging amount as in the conventional art. However, if the gate high voltage VGH is lowered to the adjusted level VGH2when the frame frequency changes from 60 Hz to 40 Hz, luminance changes are minimized. This is because, if the gate high voltage VGH is lowered to the adjusted level VGH2at 40 Hz, the voltage difference between the gate electrode G and source electrode S of the TFT is decreased. As a result, the current Ids flowing between the source electrode S and the drain electrode D is reduced, thereby reducing the charging amount to be charged in the pixel. As shown inFIG. 11, the adjusted level VGH2may be preset such that the pixel charging amount CA2at 40 Hz is substantially identical to the pixel charging amount CA1at 60 Hz.

If the gate high voltage VGH is controlled as described above, following a frame frequency change depending on the properties of an image, luminance changes caused by the frequency change can be minimized. Moreover, the output swing width of a data driving circuit is decreased in realizing a static image, thereby maximizing the effect of power consumption reduction.

Meanwhile,FIGS. 5 to 7show an example in which only the data power voltage is adjusted when the gate power voltage is fixed at a reference level, andFIGS. 8 to 11show an example in which only the gate power voltage is adjusted when the data power voltage is fixed at a reference level. The technical idea of the present invention is not limited thereto, but may include simultaneous adjustment of both of the gate power voltage and the data power voltage. In this case, two adjusted levels VDD2and VGH2may be properly set such that the pixel charging amount CA2at 40 Hz is substantially identical to the pixel charging amount CA1at 60 Hz.

FIG. 12sequentially shows a method for driving a display according to an exemplary embodiment of the present invention.

Referring toFIG. 12, in the method for driving a display, an input frame frequency is detected based on timing signals (S10).

In the method for driving a display, it is determined whether the detected input frame frequency is identical to a predetermined reference frame frequency of 60 Hz (S20).

As a result of the determination of S20, if the detected frame frequency is identical to a predetermined reference frame frequency of 60 Hz (Y), a first power control signal is generated (S30), and a gate power voltage and a data power voltage are generated at a predetermined reference level in accordance with the reference frame frequency of 60 Hz in response to the first power control signal (S40).

As a result of the determination of S20, if the detected frame frequency is not identical to a predetermined reference frame frequency of 60 Hz (N), a second power control signal is generated (S50), and the gate power voltage and the data power voltage are changed to an adjusted level lower than the predetermined reference level (S60).

As described above, in the display device and the driving method thereof according to the present invention, a data power voltage and/or gate power voltage are adjusted to be lower than a predetermined reference level in accordance with the reference frame frequency, following a frame frequency change depending on the properties of an image. By this, the display device and the driving method according to the present invention can minimize luminance changes caused by a frequency change, and reduce the output swing width of the data driving circuit and/or gate driving circuit in realizing a static image, thereby maximizing the effect of power consumption reduction.