Semiconductor device and method of forming the device using sacrificial carrier

A semiconductor device is made by forming a photoresist layer over a metal carrier. A plurality of openings is formed in the photoresist layer extending to the metal carrier. A conductive material is selectively plated in the openings of the photoresist layer using the metal carrier as an electroplating current path to form wettable contact pads. A semiconductor die has bumps formed on its surface. The bumps are directly mounted to the wettable contact pads to align the die with respect to the wettable contact pads. An encapsulant is deposited over the die. The metal carrier is removed. An interconnect structure is formed over the encapsulant and electrically connected to the wettable contact pads. A plurality of conductive vias is formed through the encapsulant and extends to the contact pads. The conductive vias are aligned by the wettable contact pads with respect to the die to reduce interconnect pitch.

FIELD OF THE INVENTION

The present invention relates in general to semiconductor devices and, more particularly, to a semiconductor device and method of forming the device using a sacrificial carrier.

BACKGROUND OF THE INVENTION

Semiconductor devices are found in many products in the fields of entertainment, communications, networks, computers, and household markets. Semiconductor devices are also found in military, aviation, automotive, industrial controllers, and office equipment. The semiconductor devices perform a variety of electrical functions necessary for each of these applications.

The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each semiconductor die contains hundreds or thousands of transistors and other active and passive devices performing a variety of electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation.

One goal of semiconductor manufacturing is to produce a package suitable for faster, reliable, smaller, and higher-density integrated circuits (IC) at lower cost. Flip chip packages or wafer level chip scale packages (WLCSP) are ideally suited for ICs demanding high speed, high density, and greater pin count. Flip chip style packaging involves mounting the active side of the die facedown toward a chip carrier substrate or printed circuit board (PCB). The electrical and mechanical interconnect between the active devices on the die and conduction tracks on the carrier substrate is achieved through a solder bump structure comprising a large number of conductive solder bumps or balls. The solder bumps are formed by a reflow process applied to solder material deposited on contact pads which are disposed on the semiconductor substrate. The solder bumps are then soldered to the carrier substrate. The flip chip semiconductor package provides a short electrical conduction path from the active devices on the die to the carrier substrate in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.

In many applications, it is desirable to stack WLCSPs. Appropriate electrical interconnect must be provided for complete device integration. The interconnect typically involves formation of redistribution layers (RDL) and other conductive lines and tracks. These metal lines have limited pitch and line spacing due to etching processing. The formation of the interconnect structure requires a high degree of alignment accuracy in attaching the die to the wafer carrier for subsequent encapsulation and further RDL buildup processes.

A need exists to form the interconnect structures for WLCSPs while accounting for the interconnect alignment requirements.

SUMMARY OF THE INVENTION

In one embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a metal carrier, forming a photoresist layer over the metal carrier, forming openings in the photoresist layer extending to the metal carrier, selectively electroplating a first conductive material in the openings of the photoresist layer using the metal carrier as an electroplating current path to form wettable contact pads, providing a first semiconductor die having a plurality of bumps formed on a surface of the first semiconductor die, mounting the bumps of the first semiconductor die directly to the wettable contact pads to align the first semiconductor die with respect to the wettable contact pads, depositing a first encapsulant over the first semiconductor die, removing the metal carrier, forming an interconnect structure over the first encapsulant and electrically connected to the wettable contact pads, forming vias through the first encapsulant over and extending to the wettable contact pads, and depositing a second conductive material in the vias. The second conductive material in the vias is aligned by the wettable contact pads with respect to the first semiconductor die to reduce interconnect pitch.

In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a metal carrier, and selectively electroplating conductive material over the metal carrier to form contact pads. The metal carrier provides an electroplating current path to form the contact pads on the metal carrier. The method further includes the steps of mounting a first semiconductor die or component to the contact pads to align the first semiconductor die or component with respect to the contact pads, depositing a first encapsulant over the first semiconductor die or component, and forming an interconnect structure over the first encapsulant and electrically connected to the contact pads.

In another embodiment, the present invention is a method of making a semiconductor device comprising the steps of providing a metal carrier, and selectively electroplating conductive material over the metal carrier to form contact pads. The metal carrier provides an electroplating current path to form the contact pads on the metal carrier. The method further includes the steps of mounting a first semiconductor die or component over the metal carrier aligned to the contact pads, depositing a first encapsulant over the first semiconductor die or component, and forming an interconnect structure over the first encapsulant and electrically connected to the contact pads.

In another embodiment, the present invention is a semiconductor device made by a process comprising the steps of providing a metal carrier, and selectively electroplating conductive material over the metal carrier to form contact pads. The metal carrier provides an electroplating current path to form the contact pads on the metal carrier. The process further includes the steps of mounting a first semiconductor die or component to the contact pads to align the first semiconductor die or component with respect to the contact pads, depositing a first encapsulant over the first semiconductor die or component, and forming an interconnect structure over the first encapsulant and electrically connected to the contact pads.

DETAILED DESCRIPTION OF THE DRAWINGS

The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each die contains hundreds or thousands of transistors and other active and passive devices performing one or more electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and/or environmental isolation.

A semiconductor wafer generally includes an active surface having semiconductor devices disposed thereon, and a backside surface formed with bulk semiconductor material, e.g., silicon. The active side surface contains a plurality of semiconductor die. The active surface is formed by a variety of semiconductor processes, including layering, patterning, doping, and heat treatment. In the layering process, semiconductor materials are grown or deposited on the substrate by techniques involving thermal oxidation, nitridation, chemical vapor deposition, evaporation, and sputtering. Photolithography involves the masking of areas of the surface and etching away undesired material to form specific structures. The doping process injects concentrations of dopant material by thermal diffusion or ion implantation.

Flip chip semiconductor packages and wafer level packages (WLP) are commonly used with integrated circuits (ICs) demanding high speed, high density, and greater pin count. Flip chip style semiconductor device10involves mounting an active area12of die14facedown toward a chip carrier substrate or printed circuit board (PCB)16, as shown inFIG. 1. Active area12contains active and passive devices, conductive layers, and dielectric layers according to the electrical design of the die. Analog circuits may be created by the combination of one or more passive device formed within active area12and may be electrically interconnected. For example, an analog circuit may include one or more inductor, capacitor and resistor formed within active area12. The electrical and mechanical interconnect is achieved through a solder bump structure20comprising a large number of individual conductive solder bumps or balls22. The solder bumps are formed on bump pads or interconnect sites24, which are disposed on active area12. The bump pads24connect to the active circuits by conduction tracks in active area12. The solder bumps22are electrically and mechanically connected to contact pads or interconnect sites26on carrier substrate16by a solder reflow process. The flip chip semiconductor device provides a short electrical conduction path from the active devices on die14to conduction tracks on carrier substrate16in order to reduce signal propagation, lower capacitance, and achieve overall better circuit performance.

Further detail of forming a semiconductor package in accordance with semiconductor device10is shown inFIGS. 2a-2f. InFIG. 2a, a dummy or sacrificial metal carrier30is shown. Metal carrier30is made with copper (Cu), aluminum (Al), or other stiff material. Carrier30can also be flexible tape. A photoresist layer32is deposited on metal carrier30. A plurality of openings is formed by a photo patterning process to define areas for selective plating. Contact pads34are then selectively plated on photoresist defined opening areas. Contact pads34can be made with Cu, tin (Sn), nickel (Ni), gold (Au), or silver (Ag). Metal carrier30serves as a support member and plating current path for the electroplating process to form wettable metal contact pads34on the metal carrier. Part or all of photoresist32is removed by a resist stripper. Alternatively, a layer of photoresist32may remain between contact pads34.

InFIG. 2b, semiconductor die36and40are mounted to contact pads34on metal carrier30with solder bumps38and42, respectively. Alternatively, discrete components or other semiconductor packages can be mounted to contact pads34. An optional underfill material can be formed below semiconductor die36and40. A molding compound44is formed around semiconductor die36and40to encapsulate the die, interconnections, and contact pads. The metal carrier is removed by an etching process to expose contact pads34as shown inFIG. 2c.

InFIG. 2d, the semiconductor die are inverted such that contact pads34face upward. An optional process carrier50is mounted to a backside of the semiconductor die using adhesive layer48to support the package. The adhesive layer can be made with thermally or ultraviolet (UV) light releasable temporary adhesive, typically having a glass transition temperature (Tg) of at least 150° C. A conductive layer46is sputtered and patterned, or selectively plated, on a surface of molded compound44using an adhesion layer, such as titanium (Ti). Conductive layer46is made with Cu, Al, Au, or alloys thereof. Conductive layer46electrically connects to contact pads34according to the electrical function and interconnect requirements of semiconductor die36and40.

InFIG. 2e, an insulating layer51is formed over molding compound44and conductive layer46. The insulating layer51can be made with single or multiple layers of photosensitive polymer material or other dielectric material having low cure temperature, e.g. less than 200° C. A portion of insulating layer51is removed by an etching process, such as photo patterning or chemical etching, to form openings and expose conductive layer46. A conductive layer52is formed over insulating layer51to electrically contact conductive layer46. An insulating layer54is formed over conductive layer52and insulating layer51. The insulating layer54can be made with single or multiple layers of photosensitive polymer material or other dielectric material having low cure temperature, e.g. less than 200° C. A portion of insulating layer54is removed by an etching process, such as photo patterning or chemical etching, to form openings and expose conductive layer52. Conductive layers46and52and insulating layers51and54constitute a portion of an interconnect structure which routes electrical signals between semiconductor die36and40, as well as external to the package. Additional insulating layers and conductive layers can be used in the interconnect structure.

InFIG. 2f, an electrically conductive solder material is deposited over conductive layer52through an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The solder material can be any metal or electrically conductive material, e.g., Sn, lead (Pb), Ni, Au, Ag, Cu, bismuthinite (Bi) and alloys thereof. The solder material is ref lowed by heating the conductive material above its melting point to form spherical balls or bumps56. In some applications, solder bumps56are ref lowed a second time to improve electrical contact to conductive layer52. An additional under bump metallization can optionally be formed under solder bumps56. The interconnections can be solder bumps or bond wires.

Process carrier50and adhesive layer48are removed. Alternatively, process carrier50and adhesive layer48can remain attached to the semiconductor device and operate as a heat sink for thermal dissipation or electromagnetic interference (EMI) barrier.

FIG. 3illustrates the semiconductor device fromFIGS. 2a-2fwith semiconductor device58electrically connected to solder bumps56. In addition, wire bonds60are electrically connected to conductive layer52. Bond wires62extend from wire bonds60to other semiconductor devices or external electrical connections. Solder bumps56and bond wires62provide electrical interconnect for semiconductor die36and40.

Another embodiment of the initial stages of making the semiconductor device is shown inFIGS. 4a-4c. InFIG. 4a, a dummy or sacrificial metal carrier70is shown. Metal carrier or foil70can be circular or rectangular and made with Cu or Al. A process carrier72is mounted to carrier70with adhesive layer74. A photoresist layer76is deposited on metal carrier70. A plurality of openings is formed by a photo patterning process to define areas for selective plating. Contact pads78are then selectively plated on photoresist defined opening areas. Contact pads78can be made with Cu, Sn, Ni, Au, or Ag. Metal carrier70serves as a support member and plating current path for the electroplating process to form wettable metal contact pads78on the metal carrier. Photoresist76is removed by a resist stripper.

InFIG. 4b, semiconductor die80and84are mounted to contact pads78on metal carrier70with solder bumps82and86, respectively. Alternatively, discrete components or other semiconductor packages can be attached to contact pads78. An optional underfill material can be formed below semiconductor die80and84. A molding compound88is formed all around semiconductor die80and84to encapsulate the die, interconnections, and contact pads. Process carrier72and adhesive74are released first, followed by removal of metal carrier70by an etching process to expose contact pads78as shown inFIG. 4c.

The interconnect structure is then formed using the steps described inFIGS. 2d-2f. More specifically, a first conductive layer like46is sputtered and patterned, or selectively plated, on a surface of molded compound88using an adhesion layer, such as Ti. The first conductive layer electrically connects to contact pads78according to the electrical function and interconnect requirements of semiconductor die80and84. A first insulating layer like51is formed over molding compound88and the first conductive layer. The first insulating layer can be made with single or multiple layers of photosensitive polymer material or other dielectric material having low cure temperature, e.g. less than 200° C. A portion of the first insulating layer is removed by an etching process to form openings and expose the first conductive layer. A second conductive layer like52is formed over the first insulating layer to electrically contact the first conductive layer. A second insulating layer like54is formed over the first conductive layer and first insulating layer. The second insulating layer can be made with single or multiple layers of photosensitive polymer material or other dielectric material having low cure temperature, e.g. less than 200° C. A portion of the second insulating layer is removed by an etching process to form openings and expose the second conductive layer. Solder bumps like56can be formed on the exposed second conductive layer. The first and second conductive layers and first and second insulating layers constitute a portion of an interconnect structure which routes electrical signals between semiconductor die80and84, as well as external to the package. Additional insulating layers and conductive layers can be used in the interconnect structure.

FIG. 5illustrates an embodiment of the semiconductor device. Contact pads94are formed using a dummy or sacrificial metal carrier as described inFIG. 2a. Semiconductor die90and98are mounted to contact pads94on the metal carrier with wire bonds96and100, respectively. A molding compound101is formed all around semiconductor die90and98to encapsulate the die, wire bonds, and contact pads, similar toFIG. 2b. The metal carrier is removed by an etching process to expose contact pads94, in the same manner as described inFIGS. 2c.

A process carrier is applied to a backside of the semiconductor die using an adhesive layer to support the package. A conductive layer102is selectively plated on a surface of molded compound101using an adhesion layer, such as Ti. Conductive layer102electrically connects to contact pads94according to the electrical function and interconnect requirements of semiconductor die90and98.

An insulating layer103is formed over molding compound101and conductive layer102. The insulating layer103can be made with material having dielectric properties. A portion of insulating layer103is removed by an etching process to form openings and expose conductive layer102. A conductive layer104is formed over insulating layer103to electrically contact conductive layer102. An insulating layer106is formed over conductive layer104and insulating layer103. The insulating layer106can be made with material having dielectric properties. A portion of insulating layer106is removed by an etching process to form openings and expose conductive layer104. Conductive layers104and106and insulating layers103and106constitute a portion of an interconnect structure to route electrical signals between semiconductor die90and98as well as external to the package. Additional insulating layers and conductive layers can be used in the interconnect structure.

An electrically conductive solder material is deposited over conductive layer104through an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The solder material can be any metal or electrically conductive material, e.g., Sn, Pb, Ni, Au, Ag, Cu, Bi, and alloys thereof. The solder material is ref lowed by heating the conductive material above its melting point to form spherical balls or bumps108. In some applications, solder bumps108are ref lowed a second time to improve electrical contact to conductive layer104. An additional under bump metallization can optionally be formed under solder bumps108. The interconnections can be solder bumps or bond wires.

FIGS. 6a-6billustrates an embodiment of the semiconductor device using a front-side and backside process carrier. InFIG. 6a, contact pads124are formed using a dummy or sacrificial metal carrier, as described inFIG. 2a. Semiconductor die120and126are mounted to contact pads124on the metal carrier with solder bumps122and128, respectively. A molding compound130is formed around semiconductor die120and126to encapsulate the die, interconnect, and contact pads, similar toFIG. 2b. The metal carrier is removed by an etching process to expose contact pads124, in the same manner as described inFIG. 2c.

A process carrier is applied to a backside of the semiconductor die using an adhesive layer to support the package. A conductive layer136is selectively plated on a surface of molded compound130using an adhesion layer, such as Ti. Conductive layer136electrically connects to contact pads124according to the electrical function and interconnect requirements of semiconductor die120and126.

An insulating layer138is formed over molding compound130and conductive layer136. The insulating layer138can be made with materials having dielectric properties. A portion of insulating layer138is removed by an etching process to form openings and expose conductive layer136. A conductive layer140is formed over insulating layer138to electrically contact conductive layer136. An insulating layer142is formed over conductive layer140and insulating layer138. The insulating layer142can be made with material having dielectric properties. A portion of insulating layer142is removed by an etching process to form openings and expose conductive layer140. Conductive layers136and140and insulating layers138and142constitute a portion of a front-side interconnect structure which routes electrical signals between semiconductor die120and126, as well as external to the package. Additional insulating layers and conductive layers can be used in the front-side interconnect structure.

A front-side process carrier146is mounted to conductive layer140and insulating layer142using adhesive layer144. The adhesive layer144can be made with thermally or UV light releasable temporary adhesive, typically having a Tg of at least 150° C. The front-side process carrier can be flexible tape or stiff material. The backside process carrier is removed. Vias are formed through molding compound130using laser drilling or deep reactive ion etch (DRIE). The vias expose contact pads124. Conductive material148is deposited in the vias and electrically connects to contact pads124. An insulating layer150is formed over conductive layer148and molding compound130. The insulating layer150can be made with material having dielectric properties. A portion of insulating layer150is removed by an etching process to form openings and expose conductive layer148. Conductive layer148and insulating layer150constitute a portion of a backside interconnect structure which routes electrical signals between semiconductor die120and126, as well as external to the package. Additional insulating layers and conductive layers can be used in the backside interconnect structure.

InFIG. 6b, an electrically conductive solder material is deposited over conductive layer140through an evaporation, electrolytic plating, electroless plating, ball drop, or screen printing process. The solder material can be any metal or electrically conductive material, e.g., Sn, Pb, Ni, Au, Ag, Cu, Bi, and alloys thereof. The solder material is ref lowed by heating the conductive material above its melting point to form spherical balls or bumps152. In some applications, solder bumps152are ref lowed a second time to improve electrical contact to conductive layer140. An additional under bump metallization can optionally be formed under solder bumps152. For the backside interconnects, solder bump or wire bond interconnects are formed on conductive layer148or the outermost layer.

The semiconductor device inFIG. 7follows a similar construction as described inFIGS. 6a-6b, with the exception that metal pillars154are formed by selective etching, using contact pads124as etching mask. Pillars154are made with Cu, Al, or alloys thereof. Metal pillars154facilitate depositing molded underfill material below semiconductor die120and126due to the elevated interconnect structure. Metal pillars154further facilitate the formation of vias by laser drilling or DRIE process as the via depth can be reduced. The semiconductor device experiences less thermal stress or thermal strain with the higher interconnection structure.

FIG. 8shows the semiconductor device ofFIG. 7with contact pads124and semiconductor die120elevated by metal pillars154. Semiconductor die158is mounted to insulating layer138with die attach adhesive160and electrically connected to contact pads124and metal pillars154with wire bonds162. The die attach adhesive160can be made with epoxy based or film based adhesive.

InFIG. 9, the semiconductor device ofFIG. 6bhas underfill material164. The underfill material can be made with resin having proper rheological and dielectric properties.

InFIG. 10, the semiconductor device ofFIG. 6bhas semiconductor die166physically mounted to and electrically connected through solder bumps152. Semiconductor die168is physically mounted to insulating layer142with die attach material170and electrically connected to conductive layer140with wire bonds172. A molding compound174is applied over semiconductor die166and168and associated interconnect structures.

FIG. 11shows the semiconductor device ofFIG. 2fwith process carrier176and adhesive layer178remaining as a heat sink for thermal dissipation or EMI shield.

FIG. 12shows the semiconductor device ofFIG. 2fwith a layer of photoresist180remaining between contact pads124.

In summary, the semiconductor device employs a copper sheet as a dummy or sacrificial carrier. A plurality of wettable contact pads is patterned on the sacrificial carrier. The individual semiconductor die are mounted to the sacrificial carrier and are electrically connected to the contact pads. The semiconductor die and contact pads are encapsulated with a molding compound. The sacrificial carrier is removed to expose the metal pads. An interconnect build-up layer is formed on the contact pads. The wettable contact pads are selectively plated on the sacrificial metal carrier to provide a highly accurate alignment of the bonding pad positions for the electrical interconnect according to the electrical function of the semiconductor die. By forming contact pads on the sacrificial carrier, a precise placement and alignment for the later formed requisite interconnect structure can be achieved. Accordingly, the semiconductor package has greater interconnect density and lower line pitch for individual traces.