DRIFT CORRECTION IN SLC AND MLC MEMORY DEVICES

Disclosed are techniques for correcting drift accumulation in memory cells. In some aspects, the techniques described herein relate to a memory device including: a memory array, the memory array including a set of memory cells; and a memory controller configured to read data from the memory array, the memory controller configured to: sense a first distribution of the set of memory cells, detect a missing cell in the first distribution, increase a voltage on the missing cell causing the missing cell to be read as part of the first distribution, detect that a second memory cell in a second distribution was read while sensing the first distribution, and mask the second memory cell and mark the second memory cell as belonging to the second distribution.

FIELD OF THE TECHNOLOGY

At least some embodiments disclosed herein relate generally to memory devices (e.g., semiconductor memory devices) and, in particular, to improvements in error correction in such memory devices.

BACKGROUND

Memory devices store data in cells that can store two or more states. Such cells are associated with threshold (“turn on”) voltages. If a sense or read voltage is applied below the threshold voltage, a cell does not conduct. If a read voltage is higher than the threshold voltage, the cell conducts. In certain memories, a two-stage bipolar read can be performed such that a positive read voltage and a negative voltage are sequentially applied to read data from a distribution of cells. During the life of a cell, its voltage threshold may change or shift, thus affecting its read performance. Excessive drift can cause a memory cell to not conduct when appropriate or conduct when inappropriate, resulting in errors in read operations.

DETAILED DESCRIPTION

In a semiconductor memory device (e.g., SLC or MLC), an error correction code (ECC) engine can be used to ensure that all the cells of a lower distribution or state are snapped during a read operation to avoid drift accumulation as well to avoid error accumulation in MLCs between first and second read phases. Some embodiments use an ECC engine embedded during the read operation (both after the first phase and, in MLC memory implementations, the second phase) to identify the erroneous cells and apply a special treatment to them to avoid drift accumulation, avoid error accumulation, and reduce the number of digital to analog conversion (DAC) steps in case of cells miscount.

For SLC embodiments, memory cells have a natural drift that tends to raise the threshold voltage (Vth) of each cell. This drift effect is canceled every time a cell is snapped. As used herein, snapping a memory cell refers to switching a cell on such that current is flowing through the cell for a short time which causes a change in the voltage threshold of the cell. During a read operation of SLC cells, the cells from the low distribution (e.g., binary one state) are snapped, and thus their drift is canceled. However, if some cells are not snapped (erroneously) due to a drift in Vth, their drift will not be canceled, and they will continue to drift to higher and higher levels.

The foregoing effect also applies to MLC memories. If a cell from a first state (e.g., set distribution) is not snapped during a first read phase, its drift is not canceled. As in the SLC embodiments, if too many cells are read during the first read phase, some cells of the second state (e.g., reset distribution) may be deactivated after the first read phase. In the various embodiments, a memory controller is configured to count until a predetermined quantity of cells is read in response to a positive polarity read voltage, and thus the target count will not be reached, and the DAC operations will rise until the Vmax, with an increased risk of intercepting cells from the third state (e.g., ternary distribution).

The example embodiments remedy these and other similar problems in the start of the art.

In some aspects, the techniques described herein relate to a memory device including: a memory array, the memory array including a set of memory cells; and a memory controller configured to read data from the memory array, the memory controller configured to: sense a first distribution of the set of memory cells, detect a missing cell in the first distribution using an ECC engine, increase a voltage on the missing cell causing the missing cell to be read as part of the first distribution, detect that a second memory cell in a second distribution was read while sensing the first distribution using the ECC engine, and mask the second memory cell and mark the second memory cell as belonging to the second distribution.

In some aspects, the techniques described herein relate to a memory device, wherein sensing a first distribution includes applying a positive read voltage to the set of memory cells and sensing a subset of the set of memory cells that conduct.

In some aspects, the techniques described herein relate to a memory device, wherein the set of memory cells includes single-level cell memory cells.

In some aspects, the techniques described herein relate to a memory device, wherein the first distribution includes a binary one state. In other impls, the first distribution may include a binary zero state and the choice is non-limiting.

In some aspects, the techniques described herein relate to a memory device, wherein the set of memory cells includes multi-level cell (MLC) memory cells.

In some aspects, the techniques described herein relate to a memory device, the memory controller further configured to: sense a second distribution of the set of memory cells; detect a second missing cell in the second distribution via the ECC engine; and increase a voltage on the second missing cell causing the second missing cell to be read as part of the second distribution.

In some aspects, the techniques described herein relate to a memory device, wherein sensing a second distribution includes applying a negative read voltage to the set of memory cells and sensing a subset of the set of memory cells that conduct.

In some aspects, the techniques described herein relate to a memory device, wherein the first distribution includes a set state second distribution and a reset state distribution.

In some aspects, the techniques described herein relate to a memory device, wherein detecting a missing cell in the first distribution includes applying an error correction code (ECC) to the first distribution.

In some aspects, the techniques described herein relate to a memory device, wherein the set of memory cells include chalcogenide-based memory cells.

In some aspects, the techniques described herein relate to a method including: sensing a first distribution of a set of memory cells, detecting a missing cell in the first distribution, increasing a voltage on the missing cell causing the missing cell to be read as part of the first distribution, detecting that a second memory cell in a second distribution was read while sensing the first distribution, and masking the second memory cell and mark the second memory cell as belonging to the second distribution.

In some aspects, the techniques described herein relate to a method, wherein sensing a first distribution includes applying a positive read voltage to the set of memory cells and sensing a subset of the set of memory cells that conduct.

In some aspects, the techniques described herein relate to a method, wherein the set of memory cells includes single-level cell memory cells.

In some aspects, the techniques described herein relate to a method, wherein the set of memory cells includes multi-level cell (MLC) memory cells.

In some aspects, the techniques described herein relate to a method, further including: sensing a second distribution of the set of memory cells; detecting a second missing cell in the second distribution; and increasing a voltage on the second missing cell causing the second missing cell to be read as part of the second distribution.

In some aspects, the techniques described herein relate to a method, wherein sensing a second distribution includes applying a negative read voltage to the set of memory cells and sensing a subset of the set of memory cells that conduct.

In some aspects, the techniques described herein relate to a method, wherein detecting a missing cell in the first distribution includes applying an error correction code (ECC) to the first distribution.

In some aspects, the techniques described herein relate to a memory device including: a memory array, the memory array including a set of memory cells; and a memory controller configured to read data from the memory array, the memory controller configured to: performing a bipolar read of a portion of the memory array, detecting at least one error using an error correction code (ECC) engine, masking at least one snapped memory cell, and applying a read retry using a negative polarity read voltage.

In some aspects, the techniques described herein relate to a memory device, wherein masking at least one snapped memory cell include masking a first memory cell snapped during a first stage of the bipolar read and a second memory cell snapped during a second stage of the bipolar read.

In some aspects, the techniques described herein relate to a memory device, wherein the at least one error occurred during a negative polarity read performed during the bipolar read, and the memory controller further configured to: mask at least one additional snapped memory cell; and apply a second read retry using a positive polarity read voltage.

FIG.1illustrates an example memory array100in accordance with various embodiments of the present disclosure.

Memory array100may also be referred to as an electronic memory apparatus. Memory array100includes memory cells105that are programmable to store different states. Each memory cell105may be programmable to store two states, denoted a logic 0 and a logic 1. In some cases, memory cell105is configured to store more than two logic states. A memory cell105may store a charge representative of the programmable states in a capacitor; for example, a charged and uncharged capacitor may represent two logic states, respectively. DRAM architectures may commonly use such a design, and the capacitor employed may include a dielectric material with linear or paraelectric electric polarization properties as the insulator. By contrast, a ferroelectric memory cell may include a capacitor with a ferroelectric as the insulating material. Different levels of charge of a ferroelectric capacitor may represent different logic states. Ferroelectric materials have non-linear polarization properties; some details and advantages of a ferroelectric memory cell105are discussed below.

Memory array100may be a three-dimensional (3D) memory array, where two-dimensional (2D) memory arrays are formed on top of one another. This may increase the number of memory cells that may be formed on a single die or substrate as compared with 2D arrays, which in turn may reduce production costs or increase the performance of the memory array, or both. According to the example depicted inFIG.1, memory array100includes two levels of memory cells105and may thus be considered a three-dimensional memory array; however, the number of levels is not limited to two. Each level may be aligned or positioned so that memory cells105may be approximately aligned with one another across each level, forming a memory cell stack145.

In some embodiments, memory cells105can comprise a chalcogenide-based memory cells that are arranged with other such memory cells in a three-dimensional (3D) architecture, such as a cross-point architecture, or arranged in a three-dimensional (3D) vertical architecture. Cross-point memory (e.g., 3D XPoint memory) uses an array of non-volatile memory cells. The memory cells in cross-point memory are transistor-less. Each of such memory cells can have a selector device and optionally a phase-change memory device that are stacked together as a column in an integrated circuit. Memory cells of such columns are connected in the integrated circuit via two layers of wires running in directions that are perpendicular to each other. One of the two layers is above the memory cells and the other layer is below the memory cells. Thus, each memory cell can be individually selected at a cross point of two wires running in different directions in two layers. Crosspoint memory devices are fast and non-volatile and can be used as a unified memory pool for processing and storage.

In some implementations, the cross point memory uses a memory cell that has an element (e.g., a sole element) acting both as a selector device and a memory device. For example, the memory cell can use a single piece of alloy with variable threshold capability. The read/write operations of such a memory cell can be based on thresholding the memory cell while inhibiting other cells in sub-threshold bias, in a way similar to the read/write operations for a memory cell having a first element acting as a selector device and a second element acting as a phase-change memory device that are stacked together as a column. A selector device usable to store information can be referred to as a selector/memory device.

Such a self-selecting memory cell, having a selector/memory device, can be programmed in cross point memory to have a threshold voltage window. The threshold voltage window can be created by applying programming pulses with opposite polarity to the selector/memory device. For example, the memory cell can be biased to have a positive voltage difference between two sides of the selector/memory device and alternatively, or to have a negative voltage difference between the same two sides of the selector/memory device. When the positive voltage difference is considered in positive polarity, the negative voltage difference is considered in negative polarity that is opposite to the positive polarity. Reading can be performed with a given/fixed polarity. When programmed, the memory cell has a low threshold (e.g., lower than the cell that has been reset, or a cell that has been programmed to have a high threshold), such that during a read operation, the read voltage can cause a programmed cell to snap and thus become conductive while a reset cell remains non-conductive.

Each row of memory cells105is connected to an access line110, and each column of memory cells105is connected to a bit line115. Access lines110may also be known as word lines110, and bit lines115may also be known digit lines115. References to word lines and bit lines, or their analogues, are interchangeable without loss of understanding or operation. Word lines110and bit lines115may be substantially perpendicular to one another to create an array. As shown inFIG.1, the two memory cells105in a memory cell stack145may share a common conductive line such as a digit line115. That is, a digit line115may be in electronic communication with the bottom electrode of the upper memory cell105and the top electrode of the lower memory cell105. Other configurations may be possible, for example, a third layer may share a word line110with a lower layer. In general, one memory cell105may be located at the intersection of two conductive lines such as a word line110and a bit line115. This intersection may be referred to as a memory cell's address. A target memory cell105may be a memory cell105located at the intersection of an energized word line110and bit line115; that is, a word line110and bit line115may be energized in order to read or write a memory cell105at their intersection. Other memory cells105that are in electronic communication with (e.g., connected to) the same word line110or bit line115may be referred to as untargeted memory cells105.

As discussed above, electrodes may be coupled to a memory cell105and a word line110or a bit line115. The term electrode may refer to an electrical conductor, and in some cases, may be employed as an electrical contact to a memory cell105. An electrode may include a trace, wire, conductive line, conductive layer, or the like that provides a conductive path between elements or components of memory array100.

Operations such as reading and writing may be performed on memory cells105by activating or selecting a word line110and bit line115, which may include applying a voltage or a current to the respective line. Word lines110and bit lines115may be made of conductive materials, such as metals (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti), etc.), metal alloys, carbon, conductively-doped semiconductors, or other conductive materials, alloys, or compounds. Accessing a target memory cell105may affect untargeted memory cells105. For example, a non-zero voltage may develop across one or more electrodes of the untargeted memory cell105. By repeatedly energizing the same word line110or bit line115, the effect may compound such that it may corrupt the stored logic values of the untargeted memory cells105. Methods disclosed herein may prevent such corruption of untargeted memory cells105. For example, a discharge pulse may be applied to the word line110or bit line115after an access operation, where the discharge voltage has a polarity opposite the polarity of the access voltage. In other cases, a delay may be instituted before a subsequent access operation to allow the untargeted memory cell105to discharge from the previous access operation.

Accessing memory cells105may be controlled through a row decoder120and a column decoder130. For example, a row decoder120may receive a row address from the memory controller140and activate the appropriate word line110based on the received row address. Similarly, a column decoder130receives a column address from the memory controller140and activates the appropriate bit line115. Thus, by activating a word line110and a bit line115, a memory cell105may be accessed.

Upon accessing, a memory cell105may be read, or sensed, by sense component125to determine the stored state of the memory cell105. For example, after accessing the memory cell105, the ferroelectric capacitor of memory cell105may discharge onto its corresponding digit line115. Discharging the ferroelectric capacitor may result from biasing, or applying a voltage, to the ferroelectric capacitor. The discharging may cause a change in the voltage of the digit line115, which sense component125may compare to a reference voltage (not shown) in order to determine the stored state of the memory cell105. For example, if digit line115has a higher voltage than the reference voltage, then sense component125may determine that the stored state in memory cell105was a logic 1 and vice versa. Sense component125may include various transistors or amplifiers in order to detect and amplify a difference in the signals, which may be referred to as latching. The detected logic state of memory cell105may then be output through column decoder130as input/output135. In some cases, sense component125may be a part of column decoder130or row decoder120. Or, sense component125may be connected to or in electronic communication with column decoder130or row decoder120.

A memory cell105may be set, or written, by similarly activating the relevant word line110and bit line115—i.e., a logic value may be stored in the memory cell105. Column decoder130or row decoder120may accept data, for example input/output135, to be written to the memory cells105. A ferroelectric memory cell105may be written by applying a voltage across the ferroelectric capacitor. Reading or writing a target memory cell105may, however, corrupt the logic states of untargeted memory cells105. This process is discussed in more detail below.

Some memory architectures, including DRAM, may lose their stored state over time unless they are periodically refreshed by an external power source. For example, a charged capacitor may become discharged over time through leakage currents, resulting in the loss of the stored information. The refresh rate of these so-called volatile memory devices may be relatively high, e.g., tens of refresh operations per second for DRAM arrays, which may result in significant power consumption. With increasingly larger memory arrays, increased power consumption may inhibit the deployment or operation of memory arrays (e.g., power supplies, heat generation, material limits, etc.), especially for mobile devices that rely on a finite power source, such as a battery. As discussed below, ferroelectric memory cells105may have beneficial properties that may result in improved performance relative to other memory architectures.

The memory controller140may control the operation (read, write, re-write, refresh, discharge, etc.) of memory cells105through the various components, for example, row decoder120, column decoder130, and sense component125. In some cases, one or more of the row decoder120, column decoder130, and sense component125may be co-located with the memory controller140. Memory controller140may generate row and column address signals in order to activate the desired word line110and bit line115. Memory controller140may also generate and control various voltage potentials or currents used during the operation of memory array100. For example, it may apply discharge voltages to a word line110or bit line115after accessing one or more memory cells105. In general, the amplitude, shape, or duration of an applied voltage or current discussed herein may be adjusted or varied and may be different for the various operations discussed in operating memory array100. Furthermore, one, multiple, or all memory cells105within memory array100may be accessed simultaneously; for example, multiple or all cells of memory array100may be accessed simultaneously during a reset operation in which all memory cells105, or a group of memory cells105, are set to a single logic state.

In some embodiments, the memory controller140can include a counter that counts the number of expected cells in each distribution. For example, in an SLC memory, the counter can manage expected number of ‘0’ cells and ‘1’ cells. In some embodiments, this counter can be updated during each write operation. Further, in some embodiments, the memory controller140can include an ECC engine that can verify codewords read from the memory. The ECC engine can comprise a hard encoder/decoder (e.g., Reed-Solomon) or a soft encoder/decoder (e.g., low density parity check). Finally, the memory controller140can comprise a drift correction circuit or logic that can perform the operations ofFIG.4or5as described herein.

FIG.2is a diagram illustrating a voltage threshold drift of a single-level cell (SLC) memory device.

Graph200A illustrates a two-state voltage distribution of an SLC cell. As illustrated, a low distribution202and a high distribution204represent the two states (binary one and zero) of the SLC memory cell. As illustrated, these two distributions are below and above an applied read voltage (Vdm). The specific voltage ranges of each distribution are not limiting, and any such range represented by the curves of low distribution202and a high distribution204may be used. Further, the low distribution202and a high distribution204are separated by a distance, generally referred to as the margin.

As illustrated in graph200A, when a given SLC cell is read, the read voltage is applied to the gates of each cell in the low distribution202and a high distribution204. Thus, any cells in low distribution202are “turned on” since the read voltage is above the voltage thresholds of the low distribution202while the cells in high distribution204are “turned off” since the read voltage is below the voltage thresholds of the high distribution204. Thus, a read resulting in an output voltage falling within the low distribution202is interpreted as storing a binary zero value, while an output voltage falling within high distribution204is interpreted as storing a binary one value.

Graph200B illustrates a drift in the voltage threshold of the SLC cells after a finite period of time. During a typical programming operation of memory cells (e.g., a block) with user data, some additional memory cells are programmed to a known one of the potential data states. Over time, the threshold voltages programmed in memory cells, including the reference cells, may shift (e.g., drift) by some amount. As illustrated, the low distribution206and high distribution208both shift higher by some non-limiting amount. However, a portion210of the low distribution206exceeds the applied read voltage and thus will be read as a binary zero (instead of a binary one), resulting in a corrupted codeword that includes cells in portion210.

Graph200C illustrates the threshold voltage distributions after or during an access operation (e.g., read operation).

In some embodiments, an access operation on a memory cell comprising a chalcogenide material can be described as including multiple events, including a thresholding event. When a bias is applied across a memory cell for a certain period, the memory cell comprising the chalcogenide material can undergo a thresholding event, characterized by a rapid increase in the amount of current flow through the memory cell and a “snapback” event, characterized by a rapid reduction in the bias across the memory cell. Once thresholded, the memory cell conducts a relatively large amount of current. Further detail on snapback events can be found in commonly owned U.S. Pat. No. 10,360,975, which is incorporated herein in its entirety.

In the illustrated graph200C, a read operation is performed that results in a snapback event with respect to low distribution206. Notably, however, portion210, having a threshold voltage above the read voltage, is not snapped back since it is (erroneously) not read. As such, portion212of the low distribution returns to a valid binary one state (with a valid voltage threshold) while portion210remains invalidly in the binary zero state.

In graph200D, the drift accumulates further as time progresses. First, portion210continues to drift higher and higher since it is not “snapped” during the read operation. Further, an additional portion216is now excluded from further snapping, similar to portion210as discussed. As such, the low distribution214continues to shrink as portions (e.g., portion210and portion212) are “broken off” above the read voltage. In the illustrated figures, high distribution208may continue to drift higher in an SLC scenario since such drift does not impact the read performance of the cell (in other embodiments, the high distribution208may also be snapped).

Thus, in the illustrated graphs, snapping reverts some of the low distribution back to a valid state. However, those portions that have already surpassed read voltage are not snapped since they are not read as invalid low distribution cells (but rather as high distribution cells). As such, this smaller portion of cells will continue to drift. While the graphs ofFIG.2illustrate SLC memory drift, a similar effect occurs in multi-level cell (MLC) memories and other types of multiple distribution memories, discussed below.

FIG.3Ais a diagram illustrating a voltage threshold drift of an MLC memory device.

The illustrated graphs plot the voltage distributions of cells in a bipolar MLC memory device. In such a device, memory cells are distributed in three states: a set (S) state, reset (R) state, and ternary (T) state. Access operations (e.g., read operations) are performed using a two-stage read process where a positive polarity read voltage (Vdm+) is first applied and the conducting cells sensed, and a negative polarity read voltage (Vdm−) is then applied, and the conducting cells are sensed. During the positive polarity read, cells in the set state are closer to the origin302(e.g., OV) and thus conduct. During the negative polarity read, these same S state cells are further from the origin302and do not conduct. Conversely, during the positive polarity read the reset state cells have a voltage threshold above Vdm+and thus do not conduct. However, during the negative polarity read, the R state cells have a threshold voltage above the negative read voltage (Vdm−) and thus conduct. Thus, R state cells only conduct during negative polarity reads while S state cells only conduct during positive polarity reads. Finally, T state cells have threshold voltages that exceed both read voltages and thus never conduct. Details of normal operations of such a bipolar memory cell (e.g., PCM cell) are described in more detail in commonly-owned U.S. Ser. No. 17/337,806 and are not repeated herein. As will be discussed, threshold drift of multiple distributions may occur in such a state, similar to that discussed inFIG.2.

At T1inFIG.3A, three state distributions are shown: a set state distribution304, reset state distribution306, and ternary state distribution308. These three states may represent three logical states that any given cell in a memory device may be in when sensed (i.e., read). Further, as discussed above reads are performed in two stages by first applying a positive polarity read voltage (Vdm+) followed by a negative polarity read voltage (Vdm−). At T1, the threshold voltages of all states have drifted. As discussed, the reset state distribution306and ternary state distribution308may not be impacted during positive polarity reads since they are not “turned on” as their threshold voltages are above the positive polarity read voltage. By contrast, set state distribution304is partially turned on when applying the positive polarity read voltage. Specifically, a portion310of the set state distribution304is not properly sensed when the positive polarity read voltage is applied. Thus, when a read operation is initiated (i.e., a positive polarity read voltage is applied) in T1, a portion of set state distribution304“snaps” back (i.e., its threshold voltage is reverted to a known state) while the portion310is not snapped and would continue to drift higher. Such a state is illustrated in T2where a portion312reverts to an expected threshold voltage below the positive polarity read voltage while the portion310remains above the positive polarity read voltage.

At T3, a negative polarity read voltage is applied as the second stage of the read operation. Here, three corresponding distributions are illustrated: a negative reset state distribution314, a negative set state distribution316, a negative ternary state distribution318. These three distributions correspond to the sensed output of the corresponding positive polarity distributions when a negative polarity read voltage is applied. As illustrated, since the threshold voltage of set state distribution304has drifted, resulting in portion310drifting, a corresponding portion320has drifted as well. However, in some implementations, the portion310and negative set state distribution316may be deactivated (e.g., not sensed) in normal operations. Notably, however, since the negative threshold voltage of negative reset state distribution314is above the negative read polarity voltage, negative reset state distribution314will snap and revert to a higher negative polarity threshold voltage. Specifically, as illustrated in T3, the negative reset state distribution322is snapped to an expected range of threshold voltages above the negative polarity read voltage. Additionally, negative set state distribution316, negative ternary state distribution318, and corresponding portion320are unchanged since they are not snapped during the negative polarity read.

Finally, in T4, the threshold voltage distributions after a read are illustrated. The reset state distribution324has “snapped” to its expected threshold voltage range, a portion312of the set state voltage range has snapped to its expected threshold voltage range, while a portion310of the set state cells has drifted above the positive polarity read voltage. As illustrated, the snapping of the reset state distribution324additionally narrows the read window between reset state distribution324and portion310.

InFIG.3Ban additional scenario is presented. In this scenario, three distributions are presented: a set state distribution326, a reset state distribution328, and a ternary state distribution330. Here, a portion332of the reset state distribution328has drifted below the positive polarity read voltage and thus will be sensed in T1while a portion334of the set state distribution326has drifted above the positive polarity read voltage and will not be sensed. After the read in T1, the threshold voltages of both the set state distribution326and portion332are lowered due to snapping. As such, the portion332(of reset state distribution328drifts further from reset state distribution328).

In T3a negative polarity read voltage is applied. In such a scenario, a negative reset distribution336, negative set state distribution338, and negative ternary state distribution340corresponding to the set state distribution326, reset state distribution328, and ternary state distribution330, respectively, are illustrated. Further, a portion342of the negative set state distribution338and a portion342of the negative set state distribution338are illustrated. As inFIG.3A, during T3, the negative set state distribution338and portion342may be deactivated. Further, however, since portion342was read (and snapped) during T1and T2, the portion342may also be deactivated. Thus, in T4, the negative reset distribution336and portion342are shifted (i.e., snapped).

In T5, the state of the memory cells after the two-stage read is illustrated. As illustrated, portion332shifts closer to the positive polarity read voltage but is still miscounted as part of set state distribution326. Further, the portion332drifts further from set state distribution326, resulting in a chronic miscounting.

InFIG.3Can additional scenario is presented. In this scenario, three distributions are presented: a set state distribution344, a reset state distribution346, and a ternary state distribution348. In T1, a portion350of reset state distribution346has a threshold voltage below the positive polarity read voltage and is thus sensed during a read in T1, thus overcounting the cells in T1. As such, in T2, the set state distribution344and portion350snap and their threshold voltages are reduced.

In T3, a negative set state distribution354, a negative reset state distribution352, and a negative ternary state distribution356corresponding to a set state distribution344, a reset state distribution346, and a ternary state distribution348are illustrated. Additionally, portion358of the negative reset state distribution356is illustrated. As inFIG.3AandFIG.3B, since the set state distribution344was sensed and snapped and the portion350was sensed and snapped, the corresponding set state distribution344and portion358are deactivated during the negative polarity read. As such, the negative reset state distribution352is undercounted during T3. Further, during T4, both negative reset state distribution and portion358snap. Finally, in T5, portion350is raised above the positive polarity read voltage, resulting in a correct count. However, as illustrated, two successive reads in T1and T5will return different data.

The foregoing examples are some, not all, of the issues caused due to threshold voltage drift in MLC cells. In general, for both SLC and MLC memory cells, snapping generally provides a “reset” of cell threshold voltages during reads. However, when a cell's threshold voltage passes a read voltage (either in negative or positive polarity), snapping can either not correct the drift or overcorrect the drift, resulting in erratic behavior. The following methods illustrate techniques for correcting such behavior.

FIG.4is a flow diagram illustrating a method for performing drift cancellation during an access operation according to some of the example embodiments.

In step402, method400can include sensing a first distribution.

In some embodiments, step402can include applying a first read voltage to a plurality of memory cells. In one embodiment, the plurality of memory cells can comprise SLC memory cells. In another embodiment, the plurality of memory cells can comprise MLC memory cells. As discussed, in some embodiments, the MLC memory cells can comprise bipolar MLC memory cells and the first read voltage can comprise a positive read voltage.

Method400senses which cells conducted in response to the first read voltage. In an SLC embodiment, these cells may correspond to the low distribution discussed inFIG.2. In an MLC embodiment, these cells may correspond to the set state cells as discussed inFIGS.3A through3C. As a result, method400obtains a first distribution of data during the first sensing.

In step404, method400can include activating an error correction code (ECC) engine in response to the first distribution. In general, an ECC engine analyzes the sensed data and detects and/or corrects any errors in the sensed data. In some embodiments, the ECC engine can comprise a hard decoder such as a Reed-Solomon decoder. In other embodiments, the ECC engine can comprise a soft decoder such as a low-density parity check decoder.

In step406, method400can include determining if cells in a first distribution are missing. In an SLC embodiment, the first distribution comprises a low distribution. In an MLC embodiment, the first distribution comprises a set state distribution. In some embodiments, method400can employ a count-based algorithm (CBA) to record the expected number of cells in any distribution. That is, upon writing, the CBA can record an expected number of cells. Thus, in step406, method400can determine if the number of sensed cells in the first distribution is equal to the expected number of cells. For example, graph200A illustrates a scenario where the sensed cells of low distribution202will be equal to the expected number of cells while graph200B illustrates when the number of sensed cells is not equal to what is expected. States T1and T2illustrate a similar scenario in the MLC embodiment.

In step408, method400can include increasing the voltage on the missing cells to force such cells to snap and thus revert to an expected threshold voltage. In an embodiment, the missing cells can be determined by analyzing the errors output by the ECC engine during step404. That is, in the SLC embodiment for example, method400can determine which bits (i.e., cells) were sensed in the high distribution that should have been sensed in the low distribution. Method400can use the ECC output to select these missing cells and increase the voltage on them until they snap and are properly read.

In step410, method400next determines if any cells in the second distribution (e.g., high distribution in the SLC embodiment, reset state in the MLC embodiment) were snapped. In an embodiment, method400again can use the ECC output to determine which cells were improperly sensed in the first distribution to make this determination.

In step412, method400can include masking these cells and, in an MLC embodiment, marking the cells as reset state cells. In the MLC embodiment, in existing scenarios, the snapped cells would be counted as part of the first distribution. As such, in step412, method400corrects this counting by explicitly marking those incorrectly snapped cells as part of the second distribution (e.g., high or reset distributions), thus allowing them to be sensed properly during a negative polarity read operation.

In step414, method400can include deactivating the snapped cells in the first distribution. As discussed, these cells correspond to validly read cells of the first (e.g., low or set) distributions and thus are masked during subsequent reads. Further, due to the explicitly snapping in step408, the total snapped cells in the first distribution is equal to the expected number of cells sensed.

In step416, method400can include sensing the second distribution. In an MLC embodiment, step416can comprise applying a negative polarity read voltage to the memory cells to read the reset state cells, as illustrated inFIGS.3A through3C. In an SLC embodiment, the second distribution read may comprise a retry read of the cells.

In step418, method400can re-activate the ECC engine to detect errors in reading, as described previously. In step420, method400can detect if any cells are missing in the second (e.g., high or reset distributions) distribution. If so, method400can increase, in step422, the voltage on these missing cells to force the cells to snap and be read as second distribution cells. Details of this process are similar to that of step406and408and are not repeated herein.

As illustrated in method400, an ECC engine is used to correct errors in sensed distributions during read operations. Specifically, method400forces snapping of erroneously unsnapped cells and explicitly adjusts cells that erroneously snapped. Method400uses the ECC engine which can detect the invalid snapping behavior of cells during read operations to determine which cells to adjust. As a result, uncontrolled drifts of memory cells can be avoided and the memory can function accurately.

FIG.5is a flow diagram illustrating a method for performing drift cancellation during an access operation according to some of the example embodiments.

In step502, method500can include performing a bipolar read on an MLC memory device. As discussed above, a bipolar read may include performing a two-stage read wherein a positive polarity read voltage is first applied to MLC memory cells and the resulting values sensed followed by a negative polarity read voltage being applied and the resulting value sensed. In some embodiments, the first sensed values are interpreted as the set state cells while the second values sensed are interpreted as the reset state cells. The remaining unsensed cells are interpreted as the ternary state cells.

In step504, method500can include activating an error correction code (ECC) engine in response to the first distribution. In general, an ECC engine analyzes the sensed data and detects and/or corrects any errors in the sensed data. In some embodiments, the ECC engine can comprise a hard decoder such as a Reed-Solomon decoder. In other embodiments, the ECC engine can comprise a soft decoder such as a low-density parity check decoder.

In step506, method500can include determining if any errors occurred during the read. As discussed above, the ECC engine can identify which cells (e.g., bits) of the read codeword(s) were incorrect, thus signaling which cells were incorrectly read. If no such errors occur, method500may end since no errors were present. Alternatively, if at least one cell is incorrectly read, method500proceeds to step508.

In general, three scenarios of errors can occur during bipolar reads: errors due to drift in both polarities, in only positive polarity, or in only negative polarity. If errors occurred on both polarities or if the errors only occurred, step508can include masking out all the previously snapped bits (i.e., read) in either of positive and negative read stages. Alternatively, if the errors only occur during the positive polarity read, method500can optionally mask out all the previously snapped bits (i.e., read) in either of the positive and negative read stages.

In step510, method500can include applying a negative polarity read. In one embodiment, method500can include using a CBA to determine which cells (that are not masked) in which to apply a second negative polarity read. In another embodiment, method500can include applying a high voltage directly to the cells to perform the negative polarity read. In some embodiments, applying a negative polarity read may be optional if errors only occur during the positive polarity read but may be necessary if the errors occur during the negative polarity read. Notably, in step510, misread cells in the set state distribution are properly detected and snapped to correct the first set distribution.

In step512, method500can include updating the snapped cell mask. In an embodiment where errors occur on both positive and negative polarity reads or errors occur only on the positive polarity read, step512can include masking out all the previously snapped bits (including those set state bits fixed in step510as well as the originally snapped bits). Conversely, if errors only occurred on the negative polarity read, step512may be optional.

In step514, method500can then apply a read retry by applying a positive polarity voltage to the unmasked cells. In an embodiment where errors occur on both positive and negative polarity reads or errors occur only on the positive polarity read, step512can include using a CBA determine which cells (that are not masked) in which to apply a second positive polarity read. In another embodiment, method500can include applying a high voltage directly to the cells to perform the second positive polarity read. Conversely, if errors only occurred on the negative polarity read, step514may be optional.

After performing the additional reads and masks in the foregoing step, method500can then re-check the responsive codeword using the ECC engine in step504. As illustrated, the process between step504and step514can be continuously re-executed until a valid codeword is detected. In some embodiments, each iteration improves the read window during retry reads and thus can ultimately result in the correct codeword being read.

FIG.6is a block diagram illustrating a computing system according to some embodiments of the disclosure.

As illustrated inFIG.6, a computing system600includes a host processor620communicatively coupled to a memory device602via a bus604. The memory device602comprises a controller606communicatively coupled to one or more memory banks (e.g., bank608A, bank608B, bank608C, bank608D, bank608N, etc.) forming a memory array via an interface612. As illustrated, the controller606includes a local cache614, firmware616, and an ECC module618.

In the illustrated embodiment, host processor620can comprise any type of computer processor, such as a central processing unit (CPU), graphics processing unit (GPU), or other types of general-purpose or special-purpose computing devices. The host processor620includes one or more output ports that allow for the transmission of address, user, and control data between the host processor620and the memory device602. In the illustrated embodiment, this communication is performed over the bus604. In one embodiment, the bus604comprises an input/output (I/O) bus or a similar type of bus.

The memory device602is responsible for managing one or more memory banks (e.g., bank608A, bank608B, bank608C, bank608D, bank608N, etc.). In one embodiment, the memory banks (e.g., bank608A, bank608B, bank608C, bank608D, bank608N, etc.) comprise NAND Flash dies or other configurations of non-volatile memory. In one embodiment, the memory banks (e.g., bank608A, bank608B, bank608C, bank608D, bank608N, etc.) comprise a memory array.

The memory banks (e.g., bank608A, bank608B, bank608C, bank608D, bank608N, etc.) are managed by the controller606. In some embodiments, the controller606comprises a computing device configured to mediate access to and from banks (e.g., bank608A, bank608B, bank608C, bank608D, bank608N, etc.). In one embodiment, the controller606comprises an ASIC or other circuitry installed on a printed circuit board housing the memory banks (e.g., bank608A, bank608B, bank608C, bank608D, bank608N, etc.). In some embodiments, the controller606may be physically separate from the memory banks (e.g., bank608A, bank608B, bank608C, bank608D, bank608N, etc.). The controller606communicates with the memory banks (e.g., bank608A, bank608B, bank608C, bank608D, bank608N, etc.) over the interface612. In some embodiments, this interface612comprises a physically wired (e.g., traced) interface. In other embodiments, the interface612comprises a standard bus for communicating with memory banks (e.g., bank608A, bank608B, bank608C, bank608D, bank608N, etc.).

The controller606comprises various modules including local cache614, firmware616and ECC module618. In one embodiment, the various modules (e.g., local cache614, firmware616and ECC module618) comprise various physically distinct modules or circuits. In other embodiments, the modules (e.g., local cache614, firmware616and ECC module618) may completely (or partially) be implemented in software or firmware.

As illustrated, firmware616comprises the core of the controller and manages all operations of the controller606. The firmware616may implement some or all of the methods described above. Specifically, the firmware616may implement the methods described in the foregoing figures.

FIG.7is a block diagram of a computing device according to some embodiments of the disclosure.

As illustrated, the device700includes a processor or central processing unit (CPU) such as CPU702in communication with a memory704via a bus714. The device also includes one or more input/output (I/O) or peripheral devices712. Examples of peripheral devices include, but are not limited to, network interfaces, audio interfaces, display devices, keypads, mice, keyboard, touch screens, illuminators, haptic interfaces, global positioning system (GPS) receivers, cameras, or other optical, thermal, or electromagnetic sensors.

In some embodiments, the CPU702may comprise a general-purpose CPU. The CPU702may comprise a single-core or multiple-core CPU. The CPU702may comprise a system-on-a-chip (SoC) or a similar embedded system. In some embodiments, a graphics processing unit (GPU) may be used in place of, or in combination with, a CPU702. Memory704may comprise a memory system including a dynamic random-access memory (DRAM), static random-access memory (SRAM), Flash (e.g., NAND Flash), or combinations thereof. In one embodiment, the bus714may comprise a Peripheral Component Interconnect Express (PCIe) bus. In some embodiments, the bus714may comprise multiple busses instead of a single bus.

Memory704illustrates an example of a non-transitory computer storage media for the storage of information such as computer-readable instructions, data structures, program modules, or other data. Memory704can store a basic input/output system (BIOS) in read-only memory (ROM), such as ROM708for controlling the low-level operation of the device. The memory can also store an operating system in random-access memory (RAM) for controlling the operation of the device.

Applications710may include computer-executable instructions which, when executed by the device, perform any of the methods (or portions of the methods) described previously in the description of the preceding figures. In some embodiments, the software or programs implementing the method embodiments can be read from a hard disk drive (not illustrated) and temporarily stored in RAM706by CPU702. CPU702may then read the software or data from RAM706, process them, and store them in RAM706again.

The device may optionally communicate with a base station (not shown) or directly with another computing device. One or more network interfaces in peripheral devices712are sometimes referred to as a transceiver, transceiving device, or network interface card (NIC).

An audio interface in peripheral devices712produces and receives audio signals such as the sound of a human voice. For example, an audio interface may be coupled to a speaker and microphone (not shown) to enable telecommunication with others or generate an audio acknowledgment for some action. Displays in peripheral devices712may comprise liquid crystal display (LCD), gas plasma, light-emitting diode (LED), or any other type of display device used with a computing device. A display may also include a touch-sensitive screen arranged to receive input from an object such as a stylus or a digit from a human hand.

A keypad in peripheral devices712may comprise any input device arranged to receive input from a user. An illuminator in peripheral devices712may provide a status indication or provide light. The device can also comprise an input/output interface in peripheral devices712for communication with external devices, using communication technologies, such as USB, infrared, Bluetooth®, or the like. A haptic interface in peripheral devices712provides tactile feedback to a user of the client device.

A GPS receiver in peripheral devices712can determine the physical coordinates of the device on the surface of the Earth, which typically outputs a location as latitude and longitude values. A GPS receiver can also employ other geo-positioning mechanisms, including, but not limited to, triangulation, assisted GPS (AGPS), E-OTD, CI, SAI, ETA, BSS, or the like, to further determine the physical location of the device on the surface of the Earth. In one embodiment, however, the device may communicate through other components, providing other information that may be employed to determine the physical location of the device, including, for example, a media access control (MAC) address, Internet Protocol (IP) address, or the like.

The device may include more or fewer components than those shown inFIG.7, depending on the deployment or usage of the device. For example, a server computing device, such as a rack-mounted server, may not include audio interfaces, displays, keypads, illuminators, haptic interfaces, Global Positioning System (GPS) receivers, or cameras/sensors. Some devices may include additional components not shown, such as graphics processing unit (GPU) devices, cryptographic co-processors, artificial intelligence (AI) accelerators, or other peripheral devices.

The subject matter disclosed above may, however, be embodied in a variety of different forms and, therefore, covered or claimed subject matter is intended to be construed as not being limited to any example embodiments set forth herein; example embodiments are provided merely to be illustrative. Likewise, a reasonably broad scope for claimed or covered subject matter is intended. Among other things, for example, subject matter may be embodied as methods, devices, components, or systems. Accordingly, embodiments may, for example, take the form of hardware, software, firmware, or any combination thereof (other than software per se). The preceding detailed description is, therefore, not intended to be taken in a limiting sense.

Throughout the specification and claims, terms may have nuanced meanings suggested or implied in context beyond an explicitly stated meaning. Likewise, the phrase “in an embodiment” as used herein does not necessarily refer to the same embodiment and the phrase “in another embodiment” as used herein does not necessarily refer to a different embodiment. It is intended, for example, that claimed subject matter include combinations of example embodiments in whole or in part.

These computer program instructions can be provided to a processor of a general purpose computer to alter its function to a special purpose; a special purpose computer; ASIC; or other programmable digital data processing apparatus, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, implement the functions or acts specified in the block diagrams or operational block or blocks, thereby transforming their functionality in accordance with embodiments herein.