Nonvolatile semiconductor memory device and data erase method thereof

A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, memory strings, drain side selection transistors, source side selection transistors, word lines, bit lines, a source line, a drain side selection gate line, a source side selection gate line, and a control circuit. The control circuit applies a first voltage to a selected bit line, thereby executing an erase operation on a selected memory string connected to the selected bit line, and the control circuit applies a second voltage to a non-selected bit line, thereby prohibiting the erase operation for the selected memory string connected to the non-selected bit line. The first voltage is more than the second voltage.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2011-124127, filed on Jun. 2, 2011, the entire contents of which are incorporated herein by reference.

FIELD

Embodiments described in this specification relate to an electrically data-rewritable nonvolatile semiconductor memory device and a data erase method thereof.

BACKGROUND

In order to improve bit density of a nonvolatile semiconductor memory device such as a NAND-type flash memory, memory cells are expected to be provided in multiple layers. As one of such examples, a stacked NAND-type flash memory in which a memory transistor is made using a vertical transistor has been proposed.

DETAILED DESCRIPTION

A nonvolatile semiconductor memory device according to an aspect includes a semiconductor substrate, a memory cell array, a plurality of memory strings, a plurality of drain side selection transistor, a plurality of source side selection transistor, a plurality of word lines, a plurality of bit lines, a source line, a drain side selection gate line, a source side selection gate line, and a control circuit. The memory cell array includes the plurality of memory strings. The plurality of memory strings has a plurality of electrically rewritable memory transistors connected in series and stacked above the semiconductor substrate. One end of the drain side selection transistor is connected to a first end of a memory string. One end of the source side selection transistor is connected to a second end of the memory string. The plurality of word lines are arranged to be commonly connected to the plurality of memory strings. The plurality of bit lines are respectively connected to the other ends of the drain side selection transistors. The source line is commonly connected the gates of the drain side selection transistors. The source side selection gate line is commonly connected the gates of the source side selection transistors. The control circuit is configured to control a voltage applied to the memory cell array. The control circuit is configured to apply a first voltage to a selected bit line, thereby executing an erase operation on a selected memory string connected to the selected bit line, and the control circuit is configured to apply a second voltage to a non-selected bit line, thereby prohibiting the erase operation for the selected memory string connected to the non-selected bit line. The first voltage is more than the second voltage.

Embodiments of nonvolatile semiconductor memory devices will be hereinafter explained with reference to drawings.

First Embodiment

Overall Configuration

First, overall configuration of a nonvolatile semiconductor memory device according to a first embodiment will be explained with reference toFIG. 1. The nonvolatile semiconductor memory device according to the first embodiment includes a memory cell array MA and a peripheral circuit CC as shown inFIG. 1. A specific configuration of the peripheral circuit CC will be explained in detail with reference toFIG. 7later.

As shown inFIG. 1, the memory cell array MA includes m memory blocks MB(1), . . . MB(m). In the explanation below, when all the memory blocks ML(1) . . . (m) are collectively referred to, all the memory blocks ML(1) . . . (m) may be denoted as a memory block MB.

Bit lines BL are formed to extend in a column direction over a plurality of memory blocks MB with a predetermined pitch in a row direction.

Each memory block MB includes memory units MU(1,1) to MU(2,n) arranged in a matrix form having n rows by 2 columns. The matrix form having n rows by 2 columns is merely an example, and the embodiment is not limited thereto. The memory unit MU includes a memory string MS, a source side selection transistor SSTr, and a drain side selection transistor SDTr. In the explanation below, the memory units MU(1,1) to (2,n) may not be distinguished from each other and may be simply denoted as memory units MU. One end of the memory unit MU is connected to the bit line BL, and the other end of the memory unit MU is connected to a source line SL.

As shown inFIG. 1, the memory string MS includes memory transistors MTr1to MTr8(memory cell) and a back gate transistor BTr connected in series. The memory transistors MTr1to MTr4, MTr5to MTr8are respectively connected in series. The back gate transistor BTr is connected between the memory transistor MTr4and the memory transistor MTr5.

The memory transistors MTr1to MTr8store data by accumulating charges in charge accumulation layers therein. The memory transistor MTr1may be used as a dummy transistor DTr which is not used for storing data. The back gate transistor BTr is in a conductive state when at least the memory string MS is selected as a target of operation.

In the memory blocks MB(1) to MB(m), word lines WL1to WL8are commonly connected to the respective gates of the memory transistors MTr1to MTr8arranged in a matrix form having n rows by 2 columns. A back gate line BG is commonly connected to the respective gates of the back gate transistors BTr in n rows by 2 columns.

A drain of the source side selection transistor SSTr is connected to a source of the memory string MS. A source of the source side selection transistor SSTr is connected to the source line SL. One source side selection gate line SGS(1) or SGS(2) is commonly connected to the gates of the n source side selection transistors SSTr arranged in a line in the row direction in each memory block MB. In the explanation below, the source side selection gate lines SGS(1), (2) may not be distinguished from each other and may be collectively denoted as source side selection gate lines SGS.

A source of the drain side selection transistor SDTr is connected to a drain of the memory string MS. A drain of the drain side selection transistor SDTr is connected to the bit line BL. One drain side selection gate line SGD(1) or SGD(2) is commonly connected to the gates of the n drain side selection transistors SDTr arranged in a line in the row direction in each memory block MB. In the explanation below, the drain side selection gate line SGD(1), (2) may not be distinguished from each other and may be collectively denoted as drain side selection gate lines SGD.

As shown inFIGS. 2 and 3, one memory block MB includes a back gate layer30, a memory layer40, a selection transistor layer50, and a wiring layer60, which are stacked in order on a semiconductor substrate20. The back gate layer30functions as the back gate transistor BTr. The memory layer40functions as the memory transistors MTr1to MTr8. The selection transistor layer50functions as the drain side selection transistor SDTr and the source side selection transistor SSTr. The wiring layer60functions as the source line SL and the bit line BL.

As shown inFIGS. 2 and 3, the back gate layer30has a back gate conductive layer31. The back gate conductive layer31functions as the back gate line BG and the gate of the back gate transistor BTr. The back gate conductive layer31is formed to extend in a plate-like manner in two dimensions, i.e., a row direction and a column direction parallel to the semiconductor substrate20. For example, the back gate conductive layer31is made of polysilicon (poly-Si).

As shown inFIG. 3, the back gate layer30includes a memory gate insulating layer43and a joining semiconductor layer44B. The memory gate insulating layer43is provided between the joining semiconductor layer44B and the back gate conductive layer31. The joining semiconductor layer44B functions as a body (channel) of the back gate transistor BTr. The joining semiconductor layer44B is formed to engrave the back gate conductive layer31. The joining semiconductor layer44B is formed in a generally rectangular form of which longitudinal direction is the column direction when seen from the above. The joining semiconductor layer44B is formed in a matrix form in the row direction and the column direction in one memory block MB. For example, the joining semiconductor layer44B is made of polysilicon (poly-Si).

As shown inFIGS. 2 and 3, the memory layer40is formed in an upper layer of the back gate layer30. The memory layer40includes four word line conductive layers41ato41d. The word line conductive layer41afunctions as the word line WL4and the gate of the memory transistor MTr4. The word line conductive layer41aalso functions as the word line WL5and the gate of the memory transistor MTr5. Likewise, the word line conductive layers41bto41drespectively function as the word lines WL1to WL3and the gates of the memory transistors MTr1to MTr3. The word line conductive layers41bto41drespectively function as the word lines WL6to WL8and the gates of the memory transistors MTr6to MTr8.

The word line conductive layers41ato41dare stacked with inter-layer insulating layers45interposed therebetween in the vertical direction. The word line conductive layers41ato41dare formed with a pitch in the column direction to extend with the row direction (direction perpendicular to the sheet surface ofFIG. 3) being the longitudinal direction. For example, the word line conductive layers41ato41dare made of polysilicon (poly-Si).

As shown inFIG. 3, the memory layer40includes a memory gate insulating layer43, columnar semiconductor layer44A, and a dummy semiconductor layer44D. The memory gate insulating layer43is provided between the columnar semiconductor layer44A and the word line conductive layers41ato41d. The columnar semiconductor layer44A functions as bodies (channels) of the memory transistors MTr1to MTr8. The dummy semiconductor layer44D does not function as the bodies of the memory transistors MTr1to MTr8.

The memory gate insulating layer43includes a block insulating layer43a, a charge accumulation layer43b, and a tunnel insulating layer43c, which are arranged from side surface sides of the word line conductive layers41ato41dto a side of the memory columnar semiconductor layer44. The charge accumulation layer43bis configured to be able to accumulate charges.

The block insulating layer43ais formed with a predetermined thickness on the side surfaces of the word line conductive layers41ato41d. The charge accumulation layer43bis formed with a predetermined thickness on a side surface of the block insulating layer43a. The tunnel insulating layer43cis formed with a predetermined thickness on a side surface of the charge accumulation layer43b. The block insulating layer43aand the tunnel insulating layer43care made of silicon oxide (SiO2). The charge accumulation layer43bis made of silicon nitride (SiN).

The columnar semiconductor layer44A is formed to penetrate through the word line conductive layers41ato41dand the inter-layer insulating layer45. The columnar semiconductor layer44A extends in a direction perpendicular to the semiconductor substrate20. The pair of columnar semiconductor layers44A is formed to be in contact with a portion close to an end portion of the joining semiconductor layer44B in the column direction. For example, the columnar semiconductor layer44A is made of polysilicon (poly-Si). The dummy semiconductor layer44D is formed to penetrate through the word line conductive layers41ato41dand the inter-layer insulating layer45. Below the dummy semiconductor layer44D, the back gate conductive layer31is not provided.

In the back gate layer30and the memory layer40, the pair of columnar semiconductor layers44A and the joining semiconductor layer44B joined with the lower ends thereof constitute the memory semiconductor layer44functioning as a body (channel) of the memory string MS. The memory semiconductor layer44is formed in a U shape when seen in the row direction.

In other words, the configuration of the back gate layer30is such that the back gate conductive layer31surrounds a side surface and a lower surface of the joining semiconductor layer44B with the memory gate insulating layer43interposed therebetween. In other words, the configuration of the memory layer40is such that the word line conductive layers41ato41dare formed to surround the side surfaces of the columnar semiconductor layer44A with the memory gate insulating layer43interposed therebetween.

As shown inFIGS. 2 and 3, the selection transistor layer50includes the source side conductive layer51a, a drain side conductive layer51b, and a dummy conductive layer51c. The source side conductive layer51afunctions as the source side selection gate line SGS and the gate of the source side selection transistor SSTr. The drain side conductive layer51bfunctions as the drain side selection gate line SGD and the gate of the drain side selection transistor SDTr. The dummy conductive layer51cdoes not function as the source side selection gate line SGS and the drain side selection gate line SGD.

The source side conductive layer51ais formed in an upper layer of one of the columnar semiconductor layers44A constituting the memory semiconductor layer44. The drain side conductive layer51bis in the same layer as the source side conductive layer51a, and is formed in an upper layer of the other of the columnar semiconductor layers44A constituting the memory semiconductor layer44. The dummy conductive layer51cis in the same layer as the source side conductive layer51a, and is arranged in a portion other than the upper layer of the columnar semiconductor layer44A. The plurality of source side conductive layers51a, drain side conductive layers51b, and dummy conductive layers51care formed to extend in the row direction with a predetermined pitch in the column direction. For example, the source side conductive layer51aand the drain side conductive layer51bare made of polysilicon (poly-Si).

As shown inFIG. 3, the selection transistor layer includes a source side gate insulating layer53a, a source side columnar semiconductor layer54a, a drain side gate insulating layer53b, a drain side columnar semiconductor layer54b, and a dummy semiconductor layer54D. The source side columnar semiconductor layer54afunctions as a body (channel) of the source side selection transistor SSTr. The drain side columnar semiconductor layer54bfunctions as a body (channel) of the drain side selection transistor SDTr.

The source side gate insulating layer53ais provided between the source side conductive layer51aand the source side columnar semiconductor layer54a. The source side columnar semiconductor layer54ais formed to penetrate through the source side conductive layer51a. The source side columnar semiconductor layer54ais connected to a side surface of the source side gate insulating layer53aand an upper surface of one of the pair of columnar semiconductor layers44A, and is formed in a pillar shape extending in a direction perpendicular to the semiconductor substrate20. For example, the source side columnar semiconductor layer54ais made of polysilicon (poly-Si).

The drain side gate insulating layer53bis provided between the drain side conductive layer51band the drain side columnar semiconductor layer54b. The drain side columnar semiconductor layer54bis formed to penetrate through the drain side conductive layer51b. The drain side columnar semiconductor layer54bis connected to a side surface of the drain side gate insulating layer53band an upper surface of the other of the pair of columnar semiconductor layers44A, and is formed in a pillar shape extending in a direction perpendicular to the semiconductor substrate20. For example, the drain side columnar semiconductor layer54bis made of polysilicon (poly-Si).

The dummy semiconductor layer54D is formed to penetrate through the dummy conductive layer51c. The dummy semiconductor layer54D is formed in an I shape. A lower surface of the dummy semiconductor layer54D is in contact with an upper surface of the dummy semiconductor layer44D.

The wiring layer60includes a source line layer61, a bit line layer62, and a plug layer63. The source line layer61functions as the source line SL. The bit line layer62functions as the bit line BL.

The source line layer61is in contact with an upper surface of the source side columnar semiconductor layer54aand is formed to extend in the row direction. The bit line layer62is in contact with an upper surface of the drain side columnar semiconductor layer54bvia the plug layer63, and is formed to extend in the column direction. For example, the source line layer61, the bit line layer62, and the plug layer63are made of metallic materials such as tungsten.

Subsequently, the form of the word line conductive layer41awill be explained in detail with reference toFIG. 4. The word line conductive layers41bto41dhave the same shapes as the word line conductive layer41a, and description thereabout is not repeated here.

As shown inFIG. 4, the pair of word line conductive layers41ais provided in one memory block MB. One of the word line conductive layers41ais formed in a T shape (protruding shape) when seen from the above. The other of the word line conductive layers41ais formed in a C shape (recessed shape) so as to face the T-shaped word line conductive layer41a.

Subsequently, the shapes of the source side conductive layer51a, the drain side conductive layer51b, and the dummy conductive layer51cwill be explained in detail with reference toFIG. 5. As shown inFIG. 5, each of the source side conductive layer51a, the drain side conductive layer51b, and the dummy conductive layer51cis formed to extend in the row direction. As shown inFIG. 1, in the nonvolatile semiconductor memory device in which n by 2 memory strings are arranged in a matrix form in one memory block MB, one memory block MB is provided with a pair of (two) source side conductive layers51a, a pair of (two) drain side conductive layers51b, and a pair of (two) dummy conductive layers51c. The pair of dummy conductive layers51cis provided at both ends of the memory block MB in the column direction. The pair of source side conductive layers51ais respectively provided adjacent to the dummy conductive layers51c. The pair of drain side conductive layers51bis arranged at a position between the pair of source side conductive layers51a.

Subsequently, the shapes of the source line layer61and the bit line layer62will be explained in detail with reference toFIG. 6. The source line layers61are formed to extend in the row direction with a predetermined pitch in the column direction. In an upper layer of the source line layer61, a common source line layer64extending in the column direction is provided. A plurality of source line layers61are commonly connected to one common source line layer64via the plug layer65. The bit line layers are formed to extend in the column direction with a predetermined pitch in the row direction.

[Configuration of Peripheral Circuit CC]

Subsequently, the specific configuration of the peripheral circuit CC according to the above first embodiment will be explained with reference toFIG. 7. As shown inFIG. 7, the peripheral circuit CC includes an address decoder circuit11, boosting circuits12ato12d, word line drive circuits13a,13b, a back gate line drive circuit14, selection gate line drive circuits15a,15b, a source line drive circuit16a, a bit line drive circuit16b, a sense amplifier circuit17, a sequencer18, and row decoder circuits19a,19b. The peripheral circuit CC can apply different voltages to respective bit lines BL with the above bit line drive circuit16b.

The address decoder circuit11is connected to row decoders19a,19bvia a bus. The address decoder circuit11outputs a signal BAD to the row decoder circuits19a,19b. The signal BAD is a signal for specifying a memory block MB (block address).

The boosting circuits12ato12dgenerate boosted voltage made by boosting a base voltage. The boosting circuit12ais connected to the word line drive circuits13a,13b. The boosting circuit12atransfers the boosted voltage to the word line drive circuits13a,13b. The boosting circuit12bis connected to the source line drive circuit16a. The boosting circuit12boutputs the boosted voltage to the source line drive circuit16a. The boosting circuit12cis connected to the bit line drive circuit16b. The boosting circuit12coutputs the boosted voltage to the bit line drive circuit16b. The boosting circuit12dis connected to the row decoder circuits19a,19b. The boosting circuit12doutputs a boosted signal RDEC to the row decoder circuits19a,19b.

The word line drive circuit13ais connected to the row decoder19a. The word line drive circuit13aoutputs signals VCG5to VCG8to the row decoder19a. The word line drive circuit13bis connected to the row decoder19b. The word line drive circuit13boutputs signals VCG1to VCG4to the row decoder19b. The signals VCG1to VCG8are used to drive the word lines WL1to WL8within the selected memory block MB.

The back gate line drive circuit14is connected to the row decoder19b. The back gate line drive circuit14outputs a signal VBG to the row decoder19b. The signal VBG is used to drive the back gate line BG of the selected memory block MB.

The selection gate line drive circuit15ais connected to the row decoder19a. The selection gate line drive circuit15aoutputs a signal VSGS2, a signal VSGD1, and a signal VSGOFF to the row decoder19a. The selection gate line drive circuit15bis connected to the row decoder19b. The selection gate line drive circuit15boutputs a signal VSGS1, a signal VSGD2, and a signal VSGOFF to the row decoder19b. The signals VSGS1, VSGS2are used to respectively drive source side selection gate lines SGS(1), SGS(2) within the selected memory block MB. The signals VSGD1, VSGD2are used to respectively drive the drain side selection gate lines SGD(1), SGD(2) within the selected memory block MB. The signal VSGOFF is used to drive the source side selection gate lines SGS(1), SGS(2) and the drain side selection gate lines SGD(1), SGD(2) within the non-selected memory block MB.

The signal VSGS2, the signal VSGD1, and the signal VSGOFF are input to various kinds of wires from the selection gate line drive circuit15avia the row decoder circuit19a. The signals VSGOFF, VSGD2, VSGS1are input to various kinds of wires from the selection gate line drive circuit15bvia the row decoder circuit19b.

The source line drive circuit16ais connected to the source line SL. The source line drive circuit16aoutputs a signal VSL to the source line SL. The signal VSL is used to drive the source line SL. The bit line drive circuit16bis connected to the bit line BL. The bit line drive circuit16bselectively supplies signals VBL(1), VBL(2) to the bit lines BL(1), BL(2) via transfer transistors Tr. In addition, the bit line drive circuit16bsupplies a signal VBLG to gates of the transfer transistors Tr to control a conductive state of the transfer transistors Tr. The signals VBL(1), VBL(2) are used to drive the bit line BL(1), BL(2). Note that, inFIG. 7, bit lines BL(3) to BL(n) are omitted.

The sense amplifier circuit17is connected to the bit line BL. The sense amplifier circuit17determines held data in the memory transistors MTr1to MTr8on the basis of change of the voltage of the bit line BL. The sequencer18is connected to the above circuits11to17. The sequencer18supplies a control signal to the circuits11to17, and controls these circuits.

One row decoder circuit19a, and one row decoder circuit19bare provided for one memory block MB, respectively. The row decoder19ais connected to the word lines WL5to WL8, the source side selection gate line SGS(2), and the drain side selection gate line SGD(1). The row decoder19bis connected to the word lines WL1to WL4, the back gate line BG, the drain side selection gate line SGD(2), and the source side selection gate line SGS(1).

The row decoder circuit19ainputs signals VCG5<i> to VCG8<i> to the gates of the memory transistors MTr5to MTr8via the word lines WL5to8on the basis of the signal BAD and the signals VCG5to VCG8. The row decoder circuit19aalso selectively inputs the signal VSGS2<i> to the gate of the source side selection transistor SSTr located in the second column of the memory block MB via the source side selection gate line SGS(2) on the basis of the signal BAD, the signal VSGS2, and the signal SGOFF. The row decoder circuit19aalso selectively inputs the signal VSGD1<i> to the gate of the drain side selection transistor SDTr located in the first column of the memory block MB via the drain side selection gate line SGD(1) on the basis of the signal BAD, the signal VSGD1, and the signal SGOFF.

The row decoder circuit19aincludes a voltage conversion circuit19aa, first transfer transistors Tra1to Tra6, and second transfer transistors Trb1, Trb2. The voltage conversion circuit19aais connected to the address decoder circuit11, the boosting circuit12d, gates of the first transfer transistors Tra1to Tra6, and gates of the second transfer transistors Trb1, Trb2. The voltage conversion circuit19aagenerates a signal VSELa<i> on the basis of the signal BAD and the signal RDEC, and outputs the signal VSELa<i> to the gates of the first transfer transistors Tra1to Tra6. The voltage conversion circuit19aagenerates a signal VUSELa<i> on the basis of the signal BAD, signal RDEC, and outputs the signal VUSELa<i> to the gates of the second transfer transistors Trb1, Trb2.

The first transfer transistors Tra1to Tra4are connected between the word line drive circuit13aand the word lines WL5to WL8, respectively. The first transfer transistors Tra1to Tra4output the signals VCG5<i> to VCG8<i> to the word lines WL5to WL8, respectively, on the basis of the signals VCG5to VCG8, VSELa<i>. The first transfer transistor Tra5is connected between the selection gate line drive circuit15aand the drain side selection gate line SGD(1). The first transfer transistor Tra6is connected between the selection gate line drive circuit15aand the source side selection gate line SGS(2).

The second transfer transistor Trb1is connected between the selection gate line drive circuit15aand the drain side selection gate line SGD(1). The second transfer transistor Trb2is connected between the selection gate line drive circuit15aand the source side selection gate line SGS(2).

The row decoder circuit19binputs the signals VCG1<i> to VCG4<i> to the gates of the memory transistors MTr1to MTr4via the word lines WL1to4on the basis of the signal BAD and the signals VCG1to VCG4. The row decoder circuit19binputs a signal VBG<i> to the gate of the back gate transistor BTr via the back gate line BG on the basis of the signal BAD and the signal VBG. The row decoder circuit19balso selectively inputs the signal VSGS1<i> to the gate of the source side selection transistor SSTr located in the first column of the memory block MB via the source side selection gate line SGS(1) on the basis of the signal BAD, the signal VSGS1, and the signal SGOFF. The row decoder circuit19balso selectively inputs the signal VSGD2<i> to the gate of the drain side selection transistor SDTr located in the second column of the memory block MB via the drain side selection gate line SGD(2) on the basis of the signal BAD, the signal VSGD2, and the signal SGOFF.

The row decoder circuit19bincludes a voltage conversion circuit19ba, first transfer transistors Trc1to Trc7and second transfer transistors Trd1, Trd2. The voltage conversion circuit19bais connected to the address decoder circuit11, the boosting circuit12d, gates of the first transfer transistors Trc1to Trc7, and gates of the second transfer transistors Trd1, Trd2. The voltage conversion circuit19bagenerates a signal VSELb<i> on the basis of the signal BAD and the signal RDEC, and outputs the signal VSELb<i> to the gates of the first transfer transistors Trc1to Trc7. The voltage conversion circuit19bagenerates a signal VUSELb<i> on the basis of the signal BAD and the signal RDEC, and outputs the signal VUSELb<i> to the gates of the second transfer transistors Trd1, Trd2.

The first transfer transistors Trc1to Trc4are connected between the word line drive circuit13band the word lines WL1to WL4, respectively. The first transfer transistors Trc1to Trc4output the signals VCG1<i> to VCG4<i> to the word lines WL1to WL4, respectively, on the basis of the signals VCG1to VCG4, VSELb<i>. The first transfer transistor Trc5is connected between the back gate line drive circuit14and the back gate line BG. The first transfer transistor Trc5outputs the signal VBG<i> to the back gate line BG on the basis of the signal VBG and the signal VSELb<i>. The first transfer transistor Trc6is connected between the selection gate line drive circuit15band the source side selection gate line SGS(1). The first transfer transistor Trc7is connected between the selection gate line drive circuit15band the drain side selection gate line SGD(2).

The second transfer transistor Trd1is connected between the selection gate line drive circuit15band the source side selection gate line SGS(1). The second transfer transistor Trd2is connected between the selection gate line drive circuit15band the drain side selection gate line SGD(2). Erase operation according to the first embodiment is enabled with the configuration of the peripheral circuit CC as shown inFIG. 7explained above.

Subsequently, erase operation according to the present embodiment will be explained with reference toFIG. 8. According to the erase operation as shown inFIG. 8, it is possible to selectively erase some of the memory transistors MTr included in one selected memory block MB. More specifically, in the selected memory block MB, only the memory units MU connected to the selected bit line BL are adopted as targets of the erase operation. The memory units MU connected to the non-selected bit line BL in the selected memory block MB are not adopted as a target of the erase operation.FIG. 8illustrates voltages applied to the bit lines BL(1) to BL(8) when this selective erase operation is performed.

Previously, the same voltage is applied to all the bit lines BL, and data in all the memory transistors MTr included in one memory block MB are erased at a time. Therefore, when changing some of the data for performing overwrite of data, it is necessary to write back the data again after collective erase operation. It takes some time to perform this operation.

Accordingly, as shown inFIG. 8, in the first embodiment, operation is executed to selectively erase data in particular memory strings MS included in the plurality of memory strings MS in a memory block MB. For this operation, for example, the peripheral circuit CC applies 20 V to the odd-numbered bit lines BL(1), BL(3), BL(5), BL(7) (hereinafter referred to as selected bit lines BL) and applies 8 V to the even-numbered bit lines BL(2), BL(4), BL(6), BL(8) (hereinafter referred to as non-selected bit lines BL). Accordingly, the voltages of the bodies of the memory strings MS (memory transistors MTr1to MTr8) are set at different voltages according to whether the memory string MS is connected to the selected bit line BL or connected to the non-selected bit line BL. Therefore, as shown inFIGS. 9 and 10below, With control of the voltages of various kinds of wires, the peripheral circuit CC can selectively execute the erase operation only on the memory units MU connected to the selected bit line BL.

On the other hand, the peripheral circuit CC can prohibit the erase operation to the memory units MU connected to the non-selected bit line BL in the selected memory block MB.

As described above, in order to reduce the size of area of the circuit of the peripheral circuit such as the row decoder, the first embodiment employs a structure in which the plurality of memory strings MS arranged in a matrix form are commonly connected to one word line WL. For example, a comparative example will be considered where a plurality of memory strings MS (memory blocks) sharing a word line WL are adopted as the minimum unit for erasing data. In this comparative example, as the number of stacked word lines WL increases, the size of one memory block increases, and as a result, the minimum unit of data erase operation also increases. In the comparative example, when the minimum unit of data erase operation is reduced, the memory capacity of data substantially decreases. In contrast, the first embodiment is configured to selectively erase only some of the memory cells in one memory block. Accordingly, in the first embodiment, even if the number of stacked word lines WL increases, the unit of data erase operation does not increase. In the first embodiment, the data memory capacity does not decrease according to the erase operation.

Subsequently, with reference toFIGS. 9 and 10, voltages applied to various kinds of wires within the selected memory block MB(1) when the above selective erase operation is executed will be explained. InFIGS. 9 and 10, the memory transistor MTr1is used as the dummy transistor DTr that is not used for store data.FIG. 9illustrates voltages applied to memory units MU(1,1), MU(2,1) connected to the selected bit line BL(1) during erase operation in the selected memory block MB(1).FIG. 10illustrates voltages applied to memory units MU(1,2), MU(2,2) connected to the non-selected bit line BL(2) during erase operation in the selected memory block MB(1).

First, the memory units MU(1,1), MU(2,1) within the selected memory block MB(1) connected to the selected bit line BL(1) will be explained with reference toFIG. 9. As shown inFIG. 9, 20 V is applied to the selected bit line BL(1), and on the other hand, 8 V is applied to the source line SL.

As shown inFIG. 9, 8 V is applied to the source side selection gate lines SGS(1), SGS(2). On the other hand, 12 V is applied to the drain side selection gate lines SGD(1), SGD(2). Accordingly, in the memory units MU(1,1), MU(2,1), a GIDL current is generated in proximity to the gate of the drain side selection transistor SDTr. Therefore, the charges generated by the GIDL current flow into the selected bit line BL(1), and on the other hand, the holes flow into the body of the memory string MS (memory transistors MTr2to MTr8).

On the other hand, in the memory units MU(1,1), MU(2,1), generation of the GIDL current is prohibited in proximity to the gate of the source side selection transistor SSTr. In the memory units MU(1,1), MU(2,1), a voltage of 8 V is applied to the source line SL, and the same voltage, i.e., 8 V is also applied to the source side selection gate lines SGS(1), SGS(2). Accordingly, the source side selection transistor STr prohibits a movement of charges from the source line SL to the memory string MS.

As shown inFIG. 9, 20 V is applied to the word line WL1. On the other hand, a ground voltage GND is applied to the word lines WL2to WL8and the back gate line BG. Since 20 V is applied to the word line WL1, in the memory units MU(1,1), MU(2,1), the holes generated in the drain side selection transistor SDTr pass through the memory transistors MTr2to8but do not pass through the dummy transistor DTr (memory transistor MTr1). Therefore, the voltages of the bodies of the memory transistors MTr2to MTr8can be increased to a voltage close to 20 V.

With a thus controlled potential difference between the bodies and the gates of the memory transistors MTr2to MTr8, the erase operation is executed on the memory transistors MTr2to MTr8in the memory units MU(1,1), MU(2,1) connected to the selected bit line BL(1).

Subsequently, the memory units MU(1,2), MU(2,2) within the selected memory block MB(1) connected to the non-selected bit line BL(2) will be explained with reference toFIG. 10. As shown inFIG. 10, 8 V is applied to the non-selected bit line BL(2), and the same voltages as those ofFIG. 9are applied to the other wires.

Accordingly, as shown inFIG. 10, in the memory units MU(1,2), MU(2,2), generation of the GIDL current is prohibited in proximity to the gate of the source side selection transistor SSTr and in proximity to the gate of the drain side selection transistor SDTr. Accordingly, in the memory units MU(1,2), MU(2,2), the voltages of the bodies of the memory transistors MTr2to MTr8do not increase.

As a result, in the memory units MU(1,2), MU(2,2) connected to the non-selected bit line BL(2), erase operation for the memory transistors MTr2to MTr8is prohibited.

In the non-selected memory block MB(2), as shown inFIGS. 9 and 10, the word lines WL1to WL8are in floating state. Accordingly, in the non-selected memory block MB(2), erase operation for the memory transistors MTr2to MTr8is prohibited.

Second Embodiment

Configuration

Subsequently, a nonvolatile semiconductor memory device according to a second embodiment will be explained. The second embodiment has the same configuration as the first embodiment. Therefore, description thereabout is not repeated here. In the second embodiment, the erase operation explained below is different from that of the first embodiment.

The erase operation of the nonvolatile semiconductor memory device according to the second embodiment will be explained. In the second embodiment, the voltages applied to the bit lines BL in the erase operation are the same as those of the first embodiment. In other words, the peripheral circuit CC selectively executes the erase operation on the memory units MU connected to the selected bit line BL, and on the other hand, the peripheral circuit CC prohibits the erase operation on the memory units MU connected to the non-selected bit line BL.

In the second embodiment, the memory transistor MTr1is not used as the dummy transistor DTr, and is used to store data. Therefore, the voltages applied to various kinds of wires except the bit line BL in the erase operation are different from those of the first embodiment. Hereinafter, with reference toFIGS. 11 and 12, voltages applied to various kinds of wires within the selected memory block MB(1) when the above selective erase operation is executed will be explained.FIG. 11illustrates voltages applied to memory units MU(1,1), MU(2,1) connected to the selected bit line BL(1) during erase operation in the selected memory block MB(1).FIG. 12illustrates voltages applied to memory units MU(1,2), MU(2,2) connected to the non-selected bit line BL(2) during erase operation in the selected memory block MB(1).

First, the memory units MU(1,1), MU(2,1) within the selected memory block MB(1) connected to the selected bit line BL(1) will be explained with reference toFIG. 11. As shown inFIG. 11, 20 V is applied to the selected bit line BL(1), and 20 V is also applied to the source line SL.

As shown inFIG. 11, 12 V is applied to the source side selection gate lines SGS(1), SGS(2) and the drain side selection gate lines SGD(1), SGD(2). Accordingly, in the memory units MU(1,1), MU(2,1), a GIDL current is generated in proximity to the gate of the drain side selection transistor SDTr and in proximity to the gate of the source side selection transistor SSTr. Therefore, the charges generated by the GIDL current flows into the selected bit line BL(1) and the source line SL, and on the other hand, the holes move toward the body of the memory string MS (memory transistors MTr1to MTr8).

As shown inFIG. 11, the ground voltage GND is applied to the word lines WL1to WL8and the back gate line BG. Accordingly, the bodies of the memory transistors MTr1to MTr8are filled with the holes generated in the drain side selection transistor SDTr and the source side selection transistor SSTr. Therefore, the voltages of the bodies of the memory transistors MTr1to MTr8increase to a voltage close to 20 V.

With a thus controlled potential difference between the bodies and the gates of the memory transistors MTr1to MTr8, erase operation is executed on the memory transistors MTr1to MTr8in the memory units MU(1,1), MU(2,1) connected to the selected bit line BL(1).

As described above, in the second embodiment, GIDL currents are generated in proximity to the source side selection transistor SSTr and the drain side selection transistor SDTr. In other words, in the first embodiment, the GIDL current is generated at one end side of the memory string MS, but in the second embodiment, the GIDL currents are generated at both ends of the memory string MS. Therefore, the erase time of the second embodiment is less than the erase time of the first embodiment. In the second embodiment, data can be erased more uniformly and reliably as compared with the first embodiment.

Subsequently, the memory units MU(1,2), MU(2,2) within the selected memory block MB(1) connected to the non-selected bit line BL(2) will be explained with reference toFIG. 12. As shown inFIG. 12, 8 V is applied to the non-selected bit line BL(2), and the same voltages as those ofFIG. 11are applied to the other wires.

Accordingly, as shown inFIG. 12, in the memory units MU(1,2), MU(2,2), a GIDL current is generated in proximity to the gate of the source side selection transistor SSTr. Therefore, the electrons generated by the GIDL current flows into the source line SL, and on the other hand, and the holes flow into the body of the memory string MS (memory transistors MTr1to MTr8). On the other hand, in the memory units MU(1,2), MU(2,2), the holes generated in the source side selection transistor SSTr flow into the non-selected bit line BL(2) via the drain side selection transistor SDTr. Accordingly, in the memory units MU(1,2), MU(2,2), the voltages of the bodies of the memory transistors MTr1to MTr8do not increase.

As a result, in the memory units MU(1,2), MU(2,2) connected to the non-selected bit line BL(2), erase operation for the memory transistors MTr1to MTr8is prohibited.

In the non-selected memory block MB(2), as shown inFIGS. 11 and 12, the word lines WL1to WL8are in floating state. Accordingly, in the non-selected memory block MB(2), erase operation for the memory transistors MTr1to MTr8is prohibited.

Third Embodiment

Configuration

Subsequently, a nonvolatile semiconductor memory device according to a third embodiment will be explained. The third embodiment has the same configuration as the first embodiment. Therefore, description thereabout is not repeated here. In the third embodiment, erase operation explained below is different from that of the first embodiment.

Erase operation of the nonvolatile semiconductor memory device according to the third embodiment will be explained with reference toFIG. 13. In the third embodiment, the voltages applied to the bit lines BL in the erase operation are different from those of the first and second embodiments. The third embodiment has the same configuration as the first embodiment. Therefore, description thereabout is not repeated here.

As shown inFIG. 13, in the third embodiment, during the erase operation, 20 V and 8 V are applied to every four bit lines BL arranged adjacent to each other in the column direction. Accordingly, the peripheral circuit CC selectively executes the erase operation on the memory units MU connected to the selected bit lines BL(1) to BL(4), and on the other hand, the peripheral circuit CC prohibits the erase operation on the memory units MU connected to the non-selected bit line BL(5) to BL(8).

As described above, in the third embodiment, 20 V and 8 V are applied to every four bit lines BL. Therefore, as compared with the first embodiment in which 20 V and 8 V are alternately applied to the bit lines BL, joining between the bit lines BL can be reduced in the third embodiment.

Other Embodiments

For example, in the erase operation, voltages of the bit lines BL(1) and BL(2) may be controlled as shown inFIG. 14.FIG. 14is a timing chart showing the erase operation due to the control circuit CC shown inFIG. 7. As shown inFIG. 14, at time t11, the control circuit CC raises voltages of the signals VBL(1), VBL(2), and VBLG to a power supply voltage Vdd. This causes the power supply voltage Vdd to be transferred to the bit lines BL(1) and BL(2). Additionally at time t11, in the selected memory block MB, the control circuit CC raises voltages of the word lines WL1to WL8(signals VCG1<i> to VCG8<i>), a voltage of the back gate line BG (signal VBG<i>), a voltage of the drain side select gate line SGD (signals VSGD1<i> and VSGD2<i>), and a voltage of the source side select gate line SGS (signals VSGS1<i> and VSGS2<i>) to a voltage Vdd-Vth.

Next, from time t12through time t13, the control circuit CC raises the signal VBL(1) to an erase voltage Vera (20 V), raises the signal VBL(2) to an intermediate voltage Vmid (8 V), and raises the signal VBLG to a voltage Vera+Vth. This causes the erase voltage Vera to be transferred to the bit line BL(1), and the intermediate voltage Vmid to be transferred to the bit line BL(2). Additionally from time t12through time t13, the control circuit CC raises the voltage of the drain side select gate line SGD (signals VSGD1<i> and VSGD2<i>) with a certain potential difference with the voltage of the bit line BL, whereby a voltage of a body of the drain side select transistor SDTr is raised. Additionally from time t12through time t13, the control circuit CC raises the voltage of the source side select gate line SGS (signals VSGS1<i> and VSGS2<i>) with a certain potential difference with the voltage VSL of the source line SL, whereby a voltage of a body of the source side select transistor SSTr is raised.

Next, from time t13through time t14, the control circuit CC sets the voltages of the word lines WL1to WL8(signals VCG1<i> to VCG8<i>) and the voltage of the back gate line BG (signal VBG<i>) to a ground voltage Vss. This results in the erase operation being executed on the memory transistor MTr from time t13through time t14.