Pseudo-supply hybrid driver

A hybrid output driver includes a voltage mode main driver having an adjustable differential output voltage swing, and a current mode emphasis driver. Differential output voltage swing is adjusted by controlling the resistance of a first adjustable resistor coupled to a first voltage supply terminal, and the resistance of a second adjustable resistor coupled to a second voltage supply terminal. Resistances of the first and second adjustable resistors are adjusted by modifying a number of resistors connected in parallel. A calibration process measures the actual resistance of a similar resistor, and uses this resistance measurement to determine the number of resistors to be connected in parallel to provide the desired resistance. The current mode emphasis driver sources/sinks currents to/from differential output terminals of the hybrid output driver in response to an emphasis signal. These currents are selected in view of the selected differential output voltage swing and selected emphasis level.

FIELD OF THE INVENTION

The present invention relates to a hybrid output driver that includes both a voltage mode component and a current mode component.

RELATED ART

The design of output driver circuits becomes more difficult as these circuits are required to operate at higher speeds (e.g., 12.5 Gb/s). Parameters that must be considered in the design of an output driver circuit include: operating speed, jitter, noise, required layout area, circuit complexity, return loss, power consumption, and emphasis variation accuracy. It would be desirable to have an improved output driver circuit design that is capable at operating at a high frequency, while minimizing jitter, noise, required layout area, circuit complexity, return loss and power consumption, while improving emphasis variation accuracy.

SUMMARY

Accordingly, the present invention provides a hybrid output driver circuit that includes a voltage mode main driver having an adjustable differential output voltage swing, and a current mode emphasis driver. The differential output voltage swing is adjusted by controlling the resistance of a first adjustable resistor coupled to a first voltage supply terminal, and the resistance of a second adjustable resistor coupled to a second voltage supply terminal. The resistances of the first and second adjustable resistors are adjusted by modifying a number of resistors connected in parallel. A calibration process measures the actual resistance of a resistor, and then uses this resistance measurement to determine the number of resistors to be connected in parallel to provide the desired resistance. The current mode emphasis driver sources/sinks currents to/from the differential output terminals of the hybrid output driver in response to an emphasis signal. These currents are selected in view of the selected differential output voltage swing.

DETAILED DESCRIPTION

FIG. 1is a circuit diagram of an output driver circuit100in accordance with one embodiment of the present invention. Output driver circuit100includes voltage mode main driver circuit101and current mode emphasis driver circuit102. Because the output driver circuit100ofFIG. 1includes both a voltage mode driver component and a current mode driver component, this output driver circuit100may be referred to as a ‘hybrid’ driver circuit. As described in more detail below, voltage mode main driver circuit101is capable of operating with a programmable output voltage swing adjustment. As also described in more detail below, current mode emphasis driver circuit102performs an equalization/emphasis function within hybrid driver circuit100.

Hybrid driver circuit100is a differential signal driver, which drives a differential output signal across output terminals OUTPand OUTN, to an external load resistor RL. In the embodiments described herein, the load resistor RLhas a resistance of 100 Ohms. However, it is understood that the load resistor RLmay have other resistances in other embodiments.

Voltage mode main driver circuit101includes p-channel transistors P1and P3, n-channel transistors N1and N3, fixed resistors RP1, RN1, RP3and RN3, adjustable resistors RTOPand RBOT, and capacitors CTOPand CBOT. Adjustable resistor RTOPis coupled between the Vdd supply voltage terminal and node NTOP. In the described embodiments, the Vdd supply voltage applied to the Vdd supply voltage terminal has a nominal value of 900 mV (although it is understood that other Vdd supply voltages can be used in other embodiments). Capacitor CTOPis connected between node NTOPand the ground supply terminal. As described in more detail below, adjustable resistor RTOPand capacitor CTOPform a pseudo-supply voltage circuit that provides a pseudo-supply voltage VTOPon node NTOP, wherein VTOPis less than the Vdd supply voltage.

P-channel transistor P1and resistor RP1are coupled in series between node NTOPand output terminal OUTP, as illustrated. Resistor RN1and n-channel transistor N1are coupled in series between output terminal OUTPand node NBOT, as illustrated. Adjustable resistor RBOTand capacitor CBOTare coupled in parallel between node NBOTand the ground supply terminal. As described in more detail below, adjustable resistor RBOTand capacitor CBOTform a pseudo-supply voltage circuit that provides a pseudo-supply voltage VBOTon node NBOT, wherein VBOTis greater than the ground supply voltage (0V).

P-channel transistor P3and resistor RP3are coupled in series between node NTOPand output terminal OUTN, as illustrated. Resistor RN3and n-channel transistor N3are coupled in series between output terminal OUTNand node NBOT, as illustrated.

The gates of transistors P1and N1are each coupled to receive an output data signal D, and the gates of transistors P3and N3are each coupled to receive the inverse of the output data signal D (i.e., D#).

Current mode emphasis driver circuit102includes p-channel transistors P2and P4, n-channel transistors N2and N4, and adjustable current supplies111and112. Adjustable current supplies111and112provide adjustable emphasis currents IEMP1and IEMP2, respectively. Adjustable current supply111is coupled between the Vdd voltage supply terminal and node NA, and p-channel transistor P2is coupled between node NAand the output terminal OUTP. N-channel transistor N2is coupled between the output terminal OUT and node NB. Adjustable current supply112is coupled between node NBand ground. The gates of transistors P2and N2are coupled to receive the emphasis signal EMP.

P-channel transistor P4is coupled between node NA and the output terminal OUTN, and n-channel transistor N4is coupled between the output terminal OUTNand node NB. The gates of transistors P4and N4are coupled to receive the inverse of the emphasis signal EMP (i.e., EMP#).

Hybrid driver circuit100implements two tap finite impulse response (FIR) equalization in the illustrated embodiment. Although the present invention is described in connection with a two tap embodiment, it is understood that other numbers of current mode taps can be implemented, depending upon the desired amount of equalization. In the embodiment illustrated byFIG. 1, cursor data (D/D#) and post-cursor data (EMP/EMP#) correspond with the two taps. In the illustrated embodiment, the post-cursor data (EMP/EMP#) is the cursor data (D/D#) delayed by one cursor data bit and inverted. In other embodiments, different taps can implement pre-cursor data and/or post-cursor data. Each additional tap will replicate the structure represented by the adjustable current supplies111-112and transistors P2/N2and P4/N4ofFIG. 1(although these additional taps will be controlled by different data, depending upon the nature of the tap). In various embodiments, the emphasis signals used to control the various taps are time-shifted versions of the cursor data.

The operation of hybrid driver circuit100will now be described. In the described embodiments, fixed resistors RP1, RN1, RP3and RN3each have a resistance of 50 Ohms. The voltages on nodes NTOPand NBOTare designated VTOPand VBOT, respectively. Capacitors CTOPand CBOTare sized to be large enough to make the voltages VTOPand VBOTlook like constant voltages (i.e., pseudo-supply voltages) at the frequency of operation (i.e., the frequency at which the output data switches). Capacitors CTOPand CBOTare also sized to minimize low frequency return loss (i.e., capacitors CTOPand CBOTare sized to have negligible impedance at frequencies of about 50 to 100 MHz.) In one embodiment, each of the capacitors CTOPand CBOThas a capacitance of about 100 pF. In an alternate embodiment, each of the capacitors CTOPand CBOTcan be implemented by a plurality of smaller capacitors coupled in parallel and distributed across (shared by) a plurality of voltage mode main drivers.

The resistances of adjustable resistors RTOPand RBOTare controlled to provide a desired reduced output voltage swing across output terminals OUTPand OUTN. In one embodiment, each of the adjustable resistors RTOPand RBOTis controlled to have a resistance of 50 Ohms. As described in more detail below, this resistance provides a differential voltage swing of 600 mV across output terminals OUT and OUTN. When the output (cursor) data value D has a logic ‘0’ value (and the inverse output data value D# has a logic ‘1’ value), transistors P1and N3are turned on, and transistors P3and N1are turned off. Under these conditions, the output voltage across the external load resistor RL(i.e., the voltage across output terminals OUTPand OUTN) can be represented by the following equations.
OUTP−OUTN=IOUT*RL(Eq. 1)
OUTP−OUTN=Vdd/(RTOP+RP1+RL+RN3+RBOT)*RL(Eq. 2)

Given the exemplary values provided above, Equation (2) can be rewritten as follows.
OUTP−OUTN=900 mV/(50+50+100+50+50)*100  (Eq. 4)
OUTP−OUTN=300 mV  (Eq. 5)
wherein the voltage on output terminal OUTP is equal to 600 mV, and the voltage on output terminal OUTN is equal to 300 mV.

When the output data value D has a logic ‘1’ value (and the inverse output data value D# has a logic ‘0’ value), transistors P3and N1are turned on, and transistors P1and N3are turned off. Under these conditions, the output voltage across the load resistor RL (i.e., the voltage across output terminals OUTP and OUTN) can be represented by the following equations.
OUTP−OUTN=IOUT*RL(Eq. 6)
OUTP−OUTN=−Vdd/(RTOP+RP3+RL+RN1+RBOT)*RL(Eq. 7)

Given the exemplary values provided above, equation (7) can be rewritten as follows.
OUTP−OUTN=−900 mV/(50+50+100+50+50)*100  (Eq. 8)
OUTP−OUTN=−300 mV  (Eq. 9)
wherein the voltage on output terminal OUTPis equal to 300 mV, and the voltage on output terminal OUTNis equal to 600 mV.

The output voltage swing of voltage mode main driver101in the present example is therefore equal to 600 mV (i.e., 300 mV−(−300 mV)). Note that the pseudo-supply voltages VTOP and VBOT have values of 750 mV and 150 mV, respectively, in the above-described example.

In accordance with one embodiment of the present invention, the resistances of adjustable resistors RTOPand RBOTcan be varied to modify the pseudo-supply voltages VTOPand VBOT, and thereby the output voltage swing across the output terminals OUTPand OUTN. For example, increasing the resistance of each of the adjustable resistors RTOP and RBOT to 100 Ohms will adjust the pseudo-supply voltages VTOPand VBOTto 675 mV and 225 mV, respectively, and will lower the nominal output current IOUTto 2.5 mA. Under these conditions, the output voltage swing across the output terminals OUTPand OUTNis lowered to a nominal value of 450 mV. Similarly, reducing the resistances of resistors RTOPand RBOTto 25 Ohms each will adjust the pseudo-supply voltages VTOPand VBOTto 810 mV and 90 mV, respectively, and will increase the nominal output current IOUTto 3.6 mA. Under these conditions, the output voltage swing across the output terminals OUTPand OUTNis increased to a nominal value of 720 mV.

Reducing the output voltage swing (by controlling the resistances of adjustable resistors RTOPand RBOTin the above-described manner) advantageously allows the emphasis currents IEMP1/IEMP2of current emphasis mode driver circuit102to have a greater effect on the output signals provided on the output terminals OUTPand OUTN.

Calibration of voltage mode main driver101is important, because the output voltage swing will vary with variations in the resistances of the various resistors. In accordance with one embodiment of the present invention, calibration is performed using adjustable resistors RTOPand RBOT.FIG. 2is a circuit diagram illustrating adjustable resistor RTOP in accordance with one embodiment of the present invention.

Adjustable resistor RTOP includes fifty nominal 1000 Ohm (1 kOhm) resistive legs that are coupled in parallel between the Vdd voltage supply terminal and node NTOP. Each of these resistive legs includes a polysilicon resistor and a p-channel transistor, which are connected in series between the Vdd supply terminal and node NTOP, as illustrated inFIG. 2. Each series-connected resistor/p-channel transistor exhibits a nominal resistance of 1 kOhm when the p-channel transistor is turned on (conductive).

Adjustable resistor RTOP includes three ‘always connected’ 1 kOhm resistive legs, which include resistors RF1-RF3and p-channel transistors SF1-SF3. The gates of p-channel transistors SF1-SF3are connected to the ground supply terminal (0V), such that these p-channel transistors SF1-SF3are always on.

Adjustable resistor RTOP further includes a 1 kOhm resistive leg that includes resistor R01and corresponding p-channel transistor S01. P-channel transistor S01is controlled by switch control signal S[0]. When the switch control signal S[0] has a first logic state (e.g., S[0]=‘0’), p-channel transistor S01becomes electrically conductive, thereby electrically connecting resistor R01between the Vdd supply terminal and node NTOP. Conversely, when the switch control signal S[0] has a second logic state (e.g., S[0]=‘1’), p-channel transistor S01becomes electrically non-conductive, thereby electrically isolating resistor R01from the Vdd voltage supply terminal.

Adjustable resistor RTOPfurther includes two parallel 1 kOhm resistive legs that include resistors R11-R12and corresponding p-channel transistors S11-S12. Switch control signal S[1] controls the operation of p-channel transistors S11-S12in the same manner that switch control signal S[0] controls the operation of p-channel transistor S01.

Adjustable resistor RTOP further includes four 1 kOhm parallel 1 kOhm resistive legs that include resistors R21-R24and corresponding p-channel transistors S21-S24. Switch control signal S[2] controls the operation of p-channel transistors S21-S24in the same manner that switch control signal S[0] controls the operation of p-channel transistor S01.

Adjustable resistor RTOPfurther includes eight 1 kOhm parallel resistive legs that include resistors R31-R38and corresponding p-channel transistors S31-S38. Switch control signal S[3] controls the operation of p-channel transistors S31-S38in the same manner that switch control signal S[0] controls the operation of p-channel transistor S01.

Adjustable resistor RTOP further includes sixteen 1 kOhm parallel resistive legs that include resistors R41-R416and corresponding p-channel transistors S41-S416. Switch control signal S[4] controls the operation of p-channel transistors S41-S416in the same manner that switch control signal S[0] controls the operation of p-channel transistor S01.

Adjustable resistor RTOPfurther includes sixteen 1 kOhm parallel resistive legs that include resistors R51-R516and corresponding p-channel transistors S51-S516. Switch control signal S[5] controls the operation of p-channel transistors S51-S516in the same manner that switch control signal S[0] controls the operation of p-channel transistor S01.

Finally, adjustable resistor RTOP further includes p-channel transistor S6, which is coupled directly between the Vdd supply terminal and node NTOP. P-channel transistor S6is controlled by switch control signal S[6], wherein p-channel transistor S6becomes electrically conductive when switch control signal S[6] has a first logic state (e.g., S[6]=‘0’). Under these conditions, the adjustable resistor RTOP has a negligible resistance, such that the full Vdd supply voltage (e.g., 900 mV) is applied directly to node NTOP (i.e., VTOP=900 mV). Note that when the adjustable resistor RBOTis similarly controlled to have a negligible resistance, the ground supply voltage is applied directly to node NBOT(i.e., VBOT=0V). Under these conditions, voltage mode main driver101operates as a standard voltage-mode driver.

P-channel transistor S6becomes electrically non-conductive when switch control signal S[6] has a second logic state (e.g., S[6]=‘1’). Under these conditions, the resistance of adjustable resistor RTOP, and therefore the voltage on node NTOP, is determined by the values of the switch control signals S[5:0].

In the described embodiments, adjustable resistor RBOTis substantially identical to adjustable resistor RTOP. However, adjustable resistor RBOTreplaces the p-channel transistors of adjustable resistor RTOPwith n-channel transistors, wherein these n-channel transistors are located between the corresponding resistors and to the ground supply terminal.

In accordance with one embodiment, adjustable resistor RBOTis controlled by the inverse of the same switch control signals (i.e., S#[6:0]), to account for the fact that the adjustable resistor RBOTimplements n-channel transistors instead of p-channel transistors. As a result, the same number of resistive legs are enabled in both adjustable resistors RTOPand RBOT. In this embodiment, the switch control signals S[6:0] may be selected by averaging the results obtained from an RTOPcalibration circuit (see, e.g.,FIG. 3Abelow), and an RBOTcalibration circuit (see, e.g.,FIG. 3Bbelow). In an alternate embodiment, the switch control signals S[6:0] used to control adjustable resistor RTOPare obtained from the RTOPcalibration circuit, and the switch control signals S#[6:0] used to control adjustable resistor RBOTare obtained from the RBOTcalibration circuit. In this embodiment, the number of resistive legs enabled in adjustable resistors RTOPand RBOTwill likely be the same, but may be different. In this embodiment, the number of resistive legs enabled in adjustable resistors RTOP and RBOT will likely be the same, but may be different. As described in more detail below, adjustable resistors RTOPand RBOT, once calibrated, will exhibit substantially identical resistances.

Note that if each of the resistive legs ofFIG. 2actually exhibits a resistance of 1 kOhms, then connecting 20 of these resistive legs in parallel between the Vdd voltage supply terminal and node NTOP (i.e., setting S[6:0]=‘1101110’) would provide a resistor RTOP having a resistance of 50 Ohms. However, due to process variations, it is possible that each of the resistive legs ofFIG. 2may have a value slightly different than 1 kOhms. Thus, in accordance with one embodiment of the present invention, a calibration process is initially performed, wherein an actual resistance of a replica resistive leg is measured, and this measurement is used to select a number of resistors to be connected in parallel to provide a desired resistance.

FIGS. 3A and 3Bare circuit diagrams of calibration circuits300and320, respectively, which are used to implement the calibration process in accordance with one embodiment of the present invention.

Calibration circuit300is used to implement the calibration of resistor RTOP. As illustrated byFIG. 3A, calibration circuit300includes a first resistive leg311that includes resistor301and p-channel transistor303, a second resistive leg312that includes resistor302and p-channel transistor304, and current supply305. Resistive legs311and312are connected in series between the Vdd voltage supply terminal and node NOUT1. Current supply305sinks a current IDCfrom node NOUT1to ground, whereby the current IDCflows through resistive legs311and312. In the described embodiment, resistive leg311has an identical layout and design as the 1 kOhm resistive legs used to implement the resistor RTOP, (e.g., resistor R01and p-channel transistor S01ofFIG. 2). Also in this embodiment, resistive leg312has an identical layout and design as 1 kOhm resistive legs which are used to implement the resistor RP1. The current IDC is selected to correspond with the expected current flowing through corresponding resistive legs in resistors RTOP and RP1for a selected output voltage swing. In the example described above, when voltage mode main driver101is configured to operate with an output voltage swing of 600 mV, the Vdd supply voltage is 900 mV, the output current IOUT has a nominal value of 3 mA, and each of the resistors RTOP and RP1has a value of 50 Ohms, which is ideally provided by twenty 1 kOhm resistive legs connected in parallel. In this example, the expected current through each 1 kOhm resistive leg would be 150 microAmps (uA) (i.e., 3 mA/20parallel 1 kOhm resistive legs). Thus, as illustrated inFIG. 3A, the current supply303is configured to draw a current IDC equal to the expected current of 150 uA, and the voltage VOUT1is measured. Because the Vdd supply voltage is 900 mV, the expected value of VOUT1is 600 mV (i.e., 900 mV−(2000 Ohms*150 uA)), assuming that the resistance of each of the resistive legs311-312is actually 1 kOhm. However, depending on variations in the process used to fabricate the resistive legs, it is possible for the resistive legs to have actual resistances less than or greater than 1 kOhm.

A measured voltage VOUT1less than 600 mV indicates that the resistive legs311-312have actual resistances greater than 1 kOhm (i.e., indicates a ‘slow’ process), while a measured voltage VOUT1greater than 600 mV indicates that the resistive legs311-312have actual resistances less than 1 kOhm (i.e., indicates a ‘fast’ process). The measured voltage VOUT1is used to select a calibration value from 0 to 10 from a lookup table. A calibration value of ‘5’ indicates a normal process, wherein resistive legs311-312have actual resistances of 1 kOhm. Higher calibration values indicate that the resistive legs311-312have actual resistances greater than 1 kOhm, and lower calibration values indicate that the resistive legs311-312have actual resistances less than 1 kOhm.

FIG. 4is a calibration lookup table400in accordance with one embodiment of the present invention. Using the calibration table400, the number of resistive legs to be enabled within the resistor RTOP ofFIG. 2can be determined in response to the selected output voltage swing and the calibration code. For example, for an output voltage swing of 600 mV, and a calibration code of ‘5’, calibration lookup table400indicates that 17 1 kOhm resistive legs must be electrically connected between the Vdd supply terminal and node NTOP (in addition to the 3 fixed 1 kOhm resistive legs represented by resistors RF1-RF3and p-channel transistors SF1-SF3) within the RTOP resistor structure ofFIG. 2. In order to accomplish this, the switch value S[6:0] may be given a value of ‘1101110’, such that p-channel transistors S01and S41-S416are turned on, and p-channel transistors S11-S12, S21-S24, S31-S38, S51-S516and S6are turned off. Under these conditions, a total of 20 1 kOhm resistive legs (including resistors RF1, RF2, RF3, R01and R41-R416) are electrically connected between the Vdd supply terminal and node NTOPfor an equivalent resistance of 50 Ohms.

Similarly, for an output voltage swing of 600 mV, and a calibration code of ‘8’, calibration lookup table400indicates that 20 1 kOhm resistive legs must be electrically connected between the Vdd supply terminal and node NTOP(in addition to the 3 fixed 1 kOhm resistive legs represented by resistors RF1-RF3and p-channel transistors SF1-SF3) within the RTOPresistor structure ofFIG. 2. In the present example, a calibration code of ‘8’ indicates that each of the resistive legs in the adjustable resistor RTOPhas an actual resistance of about 1150 Ohms. To switch in the desired number of resistors, the switch value S[6:0] may be given a value of ‘1101011’, such that p-channel transistors S21-S24and S41-S416are turned on, and p-channel transistors S01, S11-S12, S31-S38, S51-S516and S6are turned off. Under these conditions, a total of 23 1150 Ohm resistive legs (including resistors RF1, RF2, RF3, R21-R24and R41-R416) are electrically connected between the Vdd supply terminal and node NTOPfor an equivalent resistance of 50 Ohms.

Although the calibration of adjustable resistor RTOPis described above, it is understood that resistor RP1may be calibrated to have a resistance of 50 Ohms in the same manner as adjustable resistor RTOP. That is, the calibration value derived from calibration circuit300can be used to access a calibration table similar to calibration table400in order to determine the number of 1 kOhm resistive legs to be coupled in parallel to create a resistor RP1having a 50 Ohm resistance. Because resistor RP1will always have a value of 50 Ohms (in contrast with adjustable resistor RTOP, which may have other resistances, e.g., 25 Ohms or 100 Ohms) for different output voltage swings, as described above), it may be possible to control the resistance of resistor RP1using fewer switches/switch control signals than adjustable resistor RTOP. In one embodiment, resistor RP1may be calibrated to a 50 Ohm value by selectively connecting between fifteen and twenty-five nominal 1 kOhm resistive legs in parallel, depending on the calibration results.

Calibration circuit320is used to implement the calibration of resistor RBOT. As illustrated byFIG. 3B, calibration circuit320includes a first 1 kOhm resistive leg331that includes resistor321and n-channel transistor323, a second 1 kOhm resistive leg332that includes resistor322and n-channel transistor324, and current supply325. Resistive legs331and332are connected in series between the ground voltage supply terminal and node NOUT2. Current supply325sources the current IDC (described above) into node NOUT2, whereby the current IDC flows through resistive legs331and332. In the described embodiment, resistive leg331has an identical layout and design as the 1 kOhm resistive legs used to implement the resistor RBOT, and resistive leg322has an identical layout and design as 1 kOhm resistive legs which are used to implement the resistor RN1.

As described above, the current IDC is selected to correspond with the expected current flowing through the resistive legs331-332for the selected output voltage swing. In the example described above, current supply325provides a current IDC of 150 uA. The output voltage VOUT2on node NOUT2is measured with the current IDCflowing through resistive legs331-332. A measured voltage VOUT2of 300 mV indicates that each of the resistive legs331-332has a resistance of 1 kOhm (normal process). A measured voltage VOUT2less than 300 mV indicates that the resistive legs331-332have actual resistances greater than 1 kOhm (i.e., indicates a ‘slow’ process), while a measured voltage VOUT2greater than 300 mV indicates that the resistive legs331-332have actual resistances less than 1 kOhm (i.e., indicates a ‘fast’ process). Again, a calibration value is selected in response to the measured voltage VOUT2, and this calibration value is used to access calibration lookup table400, thereby providing the number of resistive legs to be enabled within the adjustable resistor RBOT. Again, the resistor RN1can be calibrated to exhibit a 50 Ohm value in the same manner described above for resistor RP1.

In one embodiment, the calibration values determined by calibration circuits300and320are averaged, and the resulting averaged calibration value is used to access calibration table400, with the result being used to control the number of resistive legs enabled within both adjustable resistors RTOPand RBOT.

Current mode emphasis driver102(FIG. 1) will now be described in more detail. In general, current mode emphasis driver102adds and subtracts current from the nominal output of hybrid driver circuit100, thereby providing equalization to the output current (and voltage). That is, the currents IEMP1/IEMP2are mirrored to the output terminals OUTP/OUTNin response to the EMP/EMP# signals. The emphasis amount varies mainly due to variations in the output voltage swing of voltage mode driver circuit101. The current values of IEMP1/IEMP2associated with adjustable current supplies111and112can be adjusted in increments of 150 uA in response to an equalization control signal EQ[4:0], wherein bits EQ[4], EQ[3], EQ[2], EQ[1], and EQ[0], when activated, add currents of 2400 uA, 1200 uA, 600 uA, 300 uA and 150 uA, respectively, to IEMP1and IEMP2. When hybrid output driver100implements an output voltage swing of 600 mV, the 150 uA step size corresponds with a step size of about 0.45 dB, or about 2.5%. The maximum output voltage swing is limited by the headroom of current mode emphasis driver102.

In accordance with one embodiment of the present invention, reducing the output voltage swing of voltage mode main driver101allows the emphasis currents IEMP1/IEMP2of the current mode emphasis driver102to be more effective at providing equalization to the output of hybrid driver circuit100. For example, by reducing the output voltage swing of voltage main mode driver101to 600 mV, the equalization provided by the emphasis currents IEMP1/IEMP2increases from about 4 dB to about 8 dB (with an emphasis current of about 2700 uA), when compared to a similar voltage main mode driver101that does not include adjustable resistors RTOPand RBOT. As a result, hybrid mode driver100is capable of operating with a relatively low power consumption. In one embodiment, hybrid mode driver100is capable of operating at a data transfer rate of 12.5 Gigabits (Gb)/sec with typical/worst case power consumption of about 3.5 mW/4.1 mW, with no emphasis current. Similarly, hybrid mode driver100is capable of operating at a data transfer rate of 15 Gb/sec with typical/worst case power consumption of about 3.5 mW/4.2 mW, with no emphasis current. Power consumption increases as the emphasis current increases. This compares favorably with the power consumption of current generation drivers, which typically exhibit power consumption of about 8-10 mW for similar performance.

In one embodiment, capacitors CTOPand CBOTcan each be implemented by multiple capacitors, some of which are shared among multiple hybrid driver circuits.FIG. 5is a circuit diagram that illustrates a pair of hybrid driver circuits501-502that implement multiple capacitors in accordance with one such embodiment. In the embodiment illustrated byFIG. 5, the 100 pF capacitor CTOPof hybrid driver circuit100(FIG. 1) is replaced by replaced by a first 25 pF capacitor CTOP1included within hybrid driver circuit501, a second 25 pF CTOP2included within hybrid driver circuit502, and a 50 pF capacitor CTOPSshared by hybrid driver circuits501-502. Similarly, the 100 pF capacitor CBOTof hybrid driver circuit100(FIG. 1) is replaced by replaced by a first 25 pF capacitor CBOT1included within hybrid driver circuit501, a second 25 pF CBOT2included within hybrid driver circuit502, and a 50 pF capacitor CBOTSshared by hybrid driver circuits501-502. Other capacitor sharing configurations would be obvious in view of the present disclosure, including, but not limited to, sharing one or more capacitors among more than two hybrid driver circuits.

Although the present invention has been described in connection with several embodiments, it is understood that this invention is not limited to the embodiments disclosed, but is capable of various modifications which would be apparent to one of ordinary skill in the art. For example, although the hybrid driver circuit100has been described in connection with a single emphasis driver circuit102, it is understood that additional emphasis driver circuits can be coupled in parallel with emphasis driver circuit102, thereby providing additional taps to the hybrid driver circuit100.FIG. 6is a block diagram, of a hybrid driver circuit600in accordance with such an embodiment, wherein one or more additional emphasis driver circuits102N are coupled in parallel with current mode emphasis driver circuit102, thereby providing increased functionality in terms of equalization. In a particular embodiment, up to six emphasis driver circuits (6 taps) are coupled in parallel with the voltage main mode driver101. In one embodiment, each of the one or more additional emphasis driver circuits102Nprovides emphasis currents to the differential output terminals OUTPand OUTNin response to a corresponding emphasis signal, in a manner similar to that described above in connection with current mode emphasis driver circuit102.

Moreover, although the present specification teaches that the resistances of adjustable resistors RTOPand RBOTare controlled to provide a desired reduced output voltage swing across output terminals OUTPand OUTN, it is understood that other circuit elements of voltage main mode driver101(e.g., P1, N1, P3, N3and the associated resistors RP1, RN1, RP3RN3) could be similarly calibrated, either separately, or in combination, to achieve the same described results. Thus, the invention is limited only by the following claims.