METHOD AND APPARATUS FOR LOW-COMPLEXITY SYMBOL-RATE RECEIVER DIGITAL SIGNAL PROCESSING

A digital signal processor (DSP) for a receiver and a method for processing signals in a receiver are provided. The DSP comprises a processor configured to: receive a digital signal at a symbol rate in a frequency domain; and compensate an impairment of the digital signal in the frequency domain.

FIELD

The present invention generally relates to digital signal processing, and in particular, to a method and apparatus for low-complexity symbol-rate receiver digital signal processing.

BACKGROUND

Coherent detection together with digital signal processing (DSP) is capable of compensating various linear and nonlinear impairments. For short-reach applications, the complexity and power consumption of DSP are major concerns. Therefore, reducing the complexity and power consumption for short-reach DSP applications is desirable.

SUMMARY

The present disclosure provides a low-power and efficient low-complexity symbol-rate DSP scheme with a frequency domain equalizer structure for short-reach applications.

The present disclosure reduces the ADC sample rate to symbol rate at the receiver so that the receiver (Rx) DSP operates at symbol rate (T/1). As such, the power consumption of both ADC and Rx DSP are greatly reduced. The present disclosure also provides an efficient T/1 timing recovery approach.

According to an aspect, there is provided a digital signal processor (DSP) for a receiver, which comprises a processor configured to: receive a digital signal at a symbol rate in a frequency domain; and compensate an impairment of the digital signal in the frequency domain.

According to an aspect, there is provided a method for processing signals in a receiver, comprising: receiving a digital signal at a symbol rate in frequency domain; and compensating an impairment of the digital signal in frequency domain.

DESCRIPTION OF EXAMPLE EMBODIMENTS

Unless otherwise defined or unless context indicates otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the described embodiments appertain.

FIG.1is a block diagram of an optical communication system10. In the example ofFIG.1, the system10comprises a transmitter12, a receiver14, and a fiber link62interconnecting the transmitter12and receiver14. The transmitter12comprises a transmitter (Tx) digital signal processor (DSP)20, a Tx digital to analog convertor (DAC)30, a driver40, an in-phase quadrature modulator (IQM)50, and a Tx laser60. The receiver14includes an integrated coherent receiver (ICR)70, a receiver (Rx) laser75, an Rx analog to digital convertor (ADC)80, a voltage-controlled oscillator90, and an Rx DSP100.

In the transmitter12, the Tx DSP20is configured to receive digital signals and process, such as pre-compensate, the received digital signals. A received digital signal is a two-dimensional vector having an X-polarization and a Y-polarization. The Tx DAC30is configured to convert the processed digital signals to analog signals. The analog signals are amplified by the driver40. The amplified analog signals are then modulated at IQM50by the Tx laser60. The IQM50converts the amplified analog signals into optical signals having X-polarization and Y-polarization.

The X- and Y-polarized optical signals are transmitted through fiber link62. In some examples, the analog signals may also be modulated to RF signals and the analog RF signals may be transmitted wirelessly by one or more antennas.

In the receiver14, the X- and Y-polarized optical signals are detected at ICR70. A local oscillator that includes Rx laser75provides an optical demodulating signal to enable the ICR70to convert or demodulate the optical signals to X-and Y-polarized analog signals.

The Rx ADC80is configured to convert the X- and Y-polarized analog signals to X- and Y-polarized digital signals. The X- and Y-polarized digital signals are then forwarded the Rx DSP100for processing.

In system10, due to the differences in hardware in the transmitter12and the receiver14, and physical characteristics of the transmission medium (e.g. fiber link62), the digital signals received at the Rx DSP100may suffer various impairments, including linear and non-linear channel impairment, frequency shift, time delay and timing misalignment, channel impairment, etc. Some impairments are non-time-varying impairments such as chromatic dispersion (CD), S21, match filtering, while some impairments are time-varying impairments such as polarization mode dispersion (PMD), polarization division de-multiplexing, etc. Adaptive equalization can be used to compensate time-varying impairments and residual non-time-varying impairments, such as residual CD.

In the present application, by processing the received digital signals, the Rx DSP100is configured to compensate various impairments suffered by the received digital signals. The Rx DSP100may compensate impairments of the digital signals by adjusting the received digital signals to reduce time delays, phase shifts, frequency offsets, timing errors, and other applicable parameters of the digital signals to an acceptable extent. In some examples, as will be described in greater detail below, the Rx DSP100may adjust the digital signals by equalizing the digital signals, such as by correlating the digital signals in frequency domain with the MIMO taps, updating MIMO taps and the digital signals, until the time domain error of the received digital signals is within an acceptable range.

However, time-domain equalization can contribute significantly to overall DSP complexity, especially when used to support a large number of taps. Frequency-domain equalization (FDEQ) structures may be used to reduce complexity by taking advantage of a block-by-block signal processing strategy in frequency domain and efficient implementation of a discrete Fourier transform (DFT) function.

In the present disclosure, in receiver14, when the Rx ADC80converts the X- and Y-polarized analog signals to digital signals, the Rx ADC80is configured to sample the X- and Y-polarized analog signals from the ICR70at a sample rate equal to the symbol rate (T/1) of the digital signals received at the Tx DSP20. As such, the digital signals output from the Rx ADC80are at the original symbol rate (T/1). The Rx ADC80forwards the X- and Y-polarized digital signals at the symbol rate to the Rx DSP100for processing, including impairment compensation, as will be described in greater detail below. The Rx DSP100is also configured to adjust the VCO90, which in turn controls the frequency and phase of sampling clock signals used in the Rx ADC80.

The optical communication system10may be a short reach application. For example, the distance between the transmitter12and receiver14, or the length of the fiber link62, is less or equal to 40 kilometers. In the short reach application, the channel impairments are not as severe as those in long haul system. Thus, in at least some applications, over sampling is not essential for impairment compensation.

The overall complexity of the Rx ADC80and Rx DSP100is proportional to sample rate. Thus, reducing sampling rate can enable a low power design. By reducing sample rate of the Rx ADC80to one sample per symbol (T/1) (e.g., sample rate= symbol rate), the complexity and power consumption Rx ADC80and Rx DSP100may be greatly reduced. As well, operating Rx ADC80at a sample rate that equals the symbol rate can consume less power.

As illustrated in the example ofFIG.2, the Rx DSP100includes a concatenator module119, a Fast Fourier Transformation (FFT) module120, a IQC unit122, a 2x2 multiple input multiple output (MIMO) module124, an Inverse Fast Fourier Transform (IFFT) module126, a save last block module127, a Carrier Recovery (CR) module128, a MIMO taps update module130, a timing error calculator132, and a loop filter134.

As used here, a “module” can refer to a combination of a hardware processing circuit and machine-readable instructions (software and/or firmware) executable on the hardware processing circuit. A hardware processing circuit can include any or some combination of a microprocessor, a core of a multi-core microprocessor, a microcontroller, a programmable integrated circuit, a programmable gate array, a digital signal processor, or another hardware processing circuit.

As illustrated inFIG.2, the Rx DSP100comprises a concatenator module119configured to concatenate X- and Y-polarized time-domain digital signals from the ADC80at a symbol rate. The mthblock of data in signal x and y in time domain contains the most recent N data samples from the previous N data samples in time domain for both X polarization and Y polarization, respectively. For example, the concatenator module119concatenates the mthblock of most recent X-polarized N data samples in the digital signals with previous block of X-polarized N data samples in the digital signals. Similarly, the block concatenator119concatenates the mthblock of most recent Y-polarized N data samples with previous block of Y-polarized N data samples in digital signals. Hence, the overall length of the mthblock of the X- and Y-polarized digital signals output from the concatenator module119is 2N.

The FFT module120is configured to convert the input time domain digital signals from the concatenator module119to frequency domain signals. The FFT module120performs 2N point FFT and transforms the X- and Y-polarized digital signals in time-domain to X- and Y-polarized digital signals in frequency domain. The X- and Y-polarized digital signals in time domain are represented by x and y, and their corresponding X- and Y-polarized digital signals frequency domain may be represented by X and Y respectively. The output signals from FFT module120are as follows:

As illustrated in the example ofFIG.2, the Rx DSP100includes an IQC unit122to compensate signals X and Y output from FFT module120. The IQC unit122is configured to compensate the In-phase Quadrature (IQ) skew and quadrature error of the signals in frequency domain. The Rx DSP100may first compensate In-phase Quadrature (IQ) skew and quadrature error in frequency domain X- and Y-polarized digital signals at IQC unit122. In-phase Quadrature Compensation (IQC) includes IQ skew compensation and quadrature error compensation. Due to imperfection of ICR70, in-phase and quadrature signals X and Y may have a delay or skew Δτ and quadrature errors ΔErr. The impairments caused by IQ skew and quadrature error are compensated in frequency domain by IQC unit122at the front-end of the Rx DSP100before compensation of other impairments. Unlike typical DSPs in which IQC is performed in the time domain, in Rx DSP100, the IQC unit122is in frequency-domain and performs IQC in frequency domain for further power reduction.

Each of signals X and Y is a complex signal, which includes, in frequency domain, a first element I, and a second element Q. For example, signal X can be denoted as X=XI + jXQ, where

where N is the number of data samples, and K is an integer.

In some examples, in IQ skew compensation, the IQC unit122compensates XQ according to the function (where skew is represented as Δτ):

In quadrature compensation, the IQC unit122compensates XQ according to the function (where quadrature error is represented as ΔErr ):

The IQC unit122also compensates signal YQ and YI in frequency domain in the same manner as signal X as descried above. By compensating the signals X and Y at IQC unit122, the skew Δτ and quadrature errors AErr are eliminated from the signals X and Y output from IQC unit122to MIMO module124. The IQ compensated signals X and Y are input to the MIMO module124and the MIMO taps update module130.

The 2x2 MIMO module124is configured to compensate for signal impairments in frequency domain, based on MIMO tap value inputs from the MIMO taps update module130, as will be described in greater detail inFIG.3.

As illustrated inFIG.2, the output signals X and Y from the 2x2 MIMO module124are provided to IFFT module126. The IFFT module126is configured to convert the signals in frequency domain to signals in time domain. In order to update values of the MIMO taps update module130, the output signals X and Y from the 2x2 MIMO module124in the frequency domain are converted to time domain signals. The IFFT module126is configured to perform 2N point IFFT to convert frequency domain digital signals X and Y to corresponding digital signals x and y in time domain.

In the example ofFIG.2, the time domain digital signals x and y output from the IFFT module126are provided to the save last block module127. The save last block module127removes first N samples from time domain digital signals x and y.

In the example ofFIG.2, after the save last block module127removes first N samples from time domain digital signals x and y, in an embodiment, the time domain digital signals x and y are input to the CR module128.

The CR module128is configured to further compensate frequency offset and phase shift of the signals in time domain. The carrier frequency offset and phase shift compensated signals x and y are then provided to the MIMO taps update module130.

In another embodiments, the time domain digital signals x and y output from the save last block module127are input to the MIMO taps update module130.

The MIMO taps update module130is configured to update the MIMO tap values based on a time domain error signal associated with the signals output from the IFFT module126. In the example ofFIG.2, the MIMO taps update module130comprises a slicer129, a first adder150, an insert zero block module152, a second FFT module140, a second multiplier142, a conjugate module141, gradient constraint unit144, a third multiplier146, a delay element148, and a second adder154.

The slicer129is configured to generate, based on the carrier frequency offset and phase shift compensated signals x and y output from the save last block module127, a desired response.

The first adder150subtracts the output of the save last block module150from the desired response from the slicer129to generate a time domain error signal. The length of the time domain error signal is N.

The time domain error signal is provided to insert zero block module152. The insert zero block module152is configured to add a block of N zeros to the time domain error signal in order to make the length of the error signal to 2N. The second FFT module140performs 2N point FFT to convert the time domain error signal into frequency domain error signals E(m), which includes Ex(m) and Ey(m) in X-polarization and Y-polarization respectively. The X- and Y-polarized frequency domain error signals Ex(m) and Ey(m) are provided to the second multiplier142.

The conjugate module141conjugates the frequency domain signals X, Y output from the IQC module122, which are IQ compensated as described above. The conjugate module141provides conjugated signals [X,Y] to the second multiplier142. The second multiplier142multiplies the conjugated signals [X,Y] with X- and Y-polarized frequency domain error signals Ex(m) and Ey(m), and provides the resultant to the gradient constraint unit144.

The gradient constraint unit144is configured to generate a gradient constraint G{.} from the output of the multiplier142. Typically, the gradient constraint unit144performs IFFT on the received signals having a length of 2N, deletes last N samples of the time domain received signal, and adds a block of N zeroes and performs 2N point FFT to the gradient constraint G{.}. The gradient constraint G{.} is multiplied with µ by the third multiplier146to generate updated MIMO taps update module130.

InFIG.2, In order to provide the 2x2 MIMO module124with current MIMO tap values W(m), the second adder154and the delay element148of the MIMO taps update module130provide a delay. The MIMO taps update module130forwards the current MIMO tap values W(m) to the MIMO module124and the timing error calculator132for compensating impairments of digital signals.

The timing error calculator132is configured to determine a timing error in Baud τBaudof the signals based on the input W(m) generated from the MIMO taps update module130.

Using τBaud, the loop filter134is configured to tune the VCO90. The VCO90is configured to adjust the sampling clock frequency of Rx ADC80.

FIG.3is a flowchart showing an operational process200of the Rx DSP100for compensating further impairments of signals X and Y. After IQC unit122compensates signals X and Y for impairments of IQ skew and quadrature error, the signals X and Y may be provided to MIMO module124for further compensating of impairments.

At step202, the MIMO module124estimates a chromatic dispersion (CD) and generates a compensation response of fixed impairments Hcompin the frequency domain to compensate fixed impairments. Hcompis a vector. The compensation response of the fixed impairments Hcompmay be obtained by CD estimation (CDE) and S21 calibration.

At step204, the MIMO module124sets the initial value for MIMO taps update module130for the 2x2 MIMO module124as

The initial value of the MIMO taps update module130is saved for use in a blind equalization at step208to be described below.

At step206, the MIMO module124is configured to perform a two-dimensional clock frequency offset and carrier frequency offset scanning. The scanning uses the training symbols inserted in the signals at the transmitter12. At the Tx DSP20in time domain, a plurality of training symbols, such as16training symbols, are inserted in the digital signals. The plurality of training symbols form a training sequence (TrainSeq). The training symbols are therefore also included in the digital signals received by the Rx DSP100. The Rx DSP100at the receiver14is pre-configured with the same training symbol information as the transmitter12, such as clock frequency of the training symbols, and the number of the training symbols.

The two-dimensional clock frequency offset and carrier frequency offset scanning estimates the clock frequency offset between Tx DAC30and Rx ADC80, and the carrier frequency offset between Tx Laser60and Rx Laser75.

Due to the separate and independent sampling clocks of the Tx DAC30and the Rx ADC80, there can be a sampling clock difference between the sampling clocks. After the signal is processed at the Rx ADC80, the signal may include a variable sampling delay τ at the time domain, and may be denoted as below:

where signal(t) denotes both x(t) and y(t) in X- and Y-polarizations in time domain.

The delay τ causes a sampling phase offset, and the sampling phase offset can be time varying due to clock frequency offset and random phase jitter. The sampling phase offset is equivalent to a phase shift ej2πƒτof the signal in frequency domain:

where fft(signal(t)) denotes both signals X and Y in frequency domain.

Blind equalizers, such as Constant Modulus Algorithm (CMA) and Least Mean Squares (LMS), can compensate the clock frequency offset to a limited extent. However, blind LMS can only lock within a limited clock frequency offset range, for example smaller than 20 ppm. If the signal has a clock frequency offset greater than 20 ppm, clock frequency offset scanning is used to roughly estimate the clock frequency offset and to ensure the convergence of blind LMS.

Clock frequency offset scanning estimates the clock frequency offset between the clock of Tx DAC30and Rx ADC80. The MIMO module124is configured to scan the clock frequency offset Δfclkby adjusting the control signal of VCO90. In some examples, the MIMO module124correlates the digital signal with the training sequence (TrainSeq) to perform the clock frequency offset scanning. Based on the correlation between the training sequence and the digital signal under different scan values of Δfclk, the estimated clock frequency offset corresponds to the scan value at the maximum correlation peak value. Under each scanning value of Δfclk, the maximum correlation peak value can be determined by multiplying the digital signal at symbol rate in frequency domain with the conjugate of training sequence (TrainSeq) in frequency domain as denoted below:

which corresponds to correlation of the training sequence and signal in time domain:

where (*) denotes correlation in time domain, which corresponds to vector conjugate multiplication (conj().) in frequency domain.

The maximum correlation peak value of the digital signal at a symbol rate with the training sequence (TrainSeq) corresponds to the minimum residual clock frequency offset with the VCO adjusting. After the scan value of clock frequency offset at the maximum correlation peak value is identified, the VCO90is configured to compensate Rx clock frequency offset with the estimated frequency offset valueΔƒclk-est. If the clock frequency offset is too big, the blind LMS cannot converge. As the carrier frequency offset also affects the maximum correlation value, another scanning dimension for carrier frequency offset estimation is also used in a two-dimensional clock frequency offset and carrier frequency offset scanning to ensure a reliable clock frequency offset scanning.

As described above, due to the separation and independence of Tx laser60and Rx laser75, there can be a central frequency difference Δf, also known as carrier frequency offset, between Tx laser60and Rx laser75. The value of Δƒ can be several GHz.

The carrier frequency offset scanning is based on the correlation between the training sequence and the digital signal with the frequency difference Δƒ. In time-domain compensation schemes, a time-domain numeral controlled oscillator (NCO) is used to compensate carrier frequency offset Δƒ to the digital signal. The estimated carrier frequency offset Δƒestcorresponds to the scan value of frequency difference at the maximum correlation value.

However, the frequency domain compensation performed by Rx DSP100at IQC unit122does not include a time-domain NCO. As frequency point spacing=sample rate/FFT size, frequency shift can be used to adjust frequency offset in low capacity cases. However, the resolution of the frequency shift in high capacity cases is too low to have a good frequency offset shift.

In Rx DSP100, the MIMO module124is configured to perform a carrier frequency offset scanning in frequency domain. The carrier frequency offset scanning in time domain corresponds to the equations (a) and (b) below:

which is equivalent to

in equations (a) and (b) above, ej2πΔƒtis the NCO for determining the carrier frequency offset Δƒ, and ∗ denotes correlation operation.

Both equations (a) and (b) may obtain the carrier frequency offset estimation. In equation (a), the training sequence is already factored in NCO, the MIMO module124adds different frequency offsets in the training sequence, and therefore, the NCO does not need to be determined in the digital signal. In equation (b), as the training sequence is not factored in the NCO, the NCO would be required to be calculated in the digital signal when the MIMO module124performs carrier frequency offset scanning. As such, the digital signal has to be first transformed back to time domain, and after NCO transformed back to frequency domain, which causes substantial extra complexity and power consumption. Therefore, in example embodiments, equation (a) is used instead of equation (b), because equation (a) enables the training sequence to be preprocessed with NCO, and is ready for use to directly correlate with the input digital signal.

As the carrier frequency offset also affects the maximum correlation value, the clock frequency offset scanning and carrier frequency offset scanning are simultaneously performed in a two-dimensional (2D) clock frequency offset and carrier frequency offset scanning, in order to obtain a relatively accurate estimation of clock frequency offset. As such, a 2D clock frequency offset and carrier frequency offset scanning simultaneously determines the estimation of sampling frequency offset Δƒclk-estand carrier frequency offset Δƒestin the digital signal. A reliable clock recovery in a T/1 receiver system typically is difficult. However, a 2D clock frequency offset and carrier frequency offset scanning ensures accuracy and stability for locking the sampling clock of the digital signal.

At step206, the 2x2 MIMO module124performs a two-dimensional clock frequency offset and carrier frequency offset scanning based on the training sequence (TrainSeq) formed by the training symbols used at the transmitter12. The input signals X and Y to the 2x2 MIMO module124are IQ compensated signals X and Y in frequency domain from the IQC unit122. As discussed above, the signals X and Y input to the MIMO module124are a two-dimensional vector [X, Y], where:

As discussed above, the sampling phase offset and carrier frequency offset still exist in the signal x and signal y. In order to determine the clock frequency offset estimation Δƒclk-estand carrier frequency offset estimation Δƒest, a 2D clock frequency offset and carrier frequency offset scanning is performed at the MIMO module124by multiplying the input signal X and Y with the values in the MIMO taps update module130, which is a 2X2 array in frequency domain:

The values of MIMO taps update module130are:

The clock frequency offset estimation Δƒclk-estand carrier frequency offset estimation Δƒestcorrespond to the scan value at the maximum correlation peak value.

In a 2D clock frequency offset and carrier frequency offset scanning, the MIMO module124scans the carrier frequency offset Δƒ. The VCO90, which is controlled by the MIMO module124of the Rx DSP100, adjusts the clock frequency offset Δfclk. The output of IFFT module126corresponds to the correlation result between the received digital signal X and Y with the known training sequences TrainSeqx, and TrainSeqy. The correlation maximum peak value is saved during each scanning that includes both clock frequency offset scanning and carrier frequency offset scanning. After the 2D clock frequency offset and carrier frequency offset scanning, the MIMO module124performs a 2D search to identify the maximum correlation peak value between the received digital signal X and Y with the known training sequences TrainSeqx, and TrainSeqy. The maximum correlation peak value determines the clock frequency offset estimation Δƒclk-estand carrier frequency offset estimation Δƒest.

The VCO90is configured to adjust the sampling clock frequency of ADC80with a -Δƒclk-estthat corresponds to the estimated clock frequency offset Δƒclk-est. After this initial compensation, the residual clock frequency offset of signals x and y output from ADC80is reduced, for example, to less than 20 ppm. With the reduced residual clock frequency offset of signals X and Y, the MIMO module124may easily converge at blind equalizer step208, such as a Blind LMS stage, and accurately and stably lock the sampling clock of the signals X and Y at a Timing Recovery (TR) stage. In some examples, the IQC unit122may roughly compensate the signals X and Y in frequency domain by the estimated carrier frequency offset estimation Δƒestwith an approximate frequency shift-Δƒest’. In some examples, the CR module128may compensate the entire or residual carrier frequency offset of signals X and Y.

After the signals X and Y are compensated with the initial estimated clock frequency offsets, at step208, the MIMO module124equalizes digital signals X and Y in frequency domain. At step208, MIMO module124uses the MIMO tap values set at step204as follows:

and the MIMO module124equalizes the input signals X = ƒƒt(signalx) and Y = ƒƒt(signaly) by multiplying the X = fft(signalx) and Y = fft(signaly) with the MIMO taps values at the MIMO taps update module130.

The output signals X and Y are updated according to the equations (1) and (2) below:

At step208, in some examples, the carrier recovery (CR) is bypassed and not involved in the signal processing process.

During the blind equalization process at step208, in order to determine that the appropriate values of the MIMO taps update module130, the MIMO module124is configured to continuously update the values of the MIMO taps update module130. The criteria whether the MIMO module124is locked will be described in detail at step210below.

In the example ofFIG.2, the output of the IFFT module126is used to update the MIMO tap values of the taps update module130, according to the following equations:

where X*(m) and Y*(m) are conjugate of the frequency domain digital signals containing X(m) and Y(m) in x and y polarization respectively, Ex(m) and Ey(m) are error signals associated with the frequency domain digital signals X(m) and Y(m) respectively, and G{.} is a gradient constraint, and µ is a step function representing a step size.

The MIMO taps update module130inFIG.2can update the MIMO tap values in accordance with equations (3)-(6).

The updated MIMO taps values are then used to update the signals X and Y using the Equations (1)-(2) above.

At step210, the MIMO module124determines whether MIMO module124is locked or converged. If the root mean square (rms) value of the time domain error signal generated by the first adder150is smaller than a threshold set by the MIMO module124, the MIMO module124is locked or converged.

If the MIMO module124is not locked, MIMO module124repeats step208to update the MIMO taps update module130in accordance with the equations (3)-(6), and to update the signals X and Y in accordance with the equations (1) and (2) until the rms value of the time domain error signal generated by the first adder150is smaller than the threshold.

After the MIMO module124is locked, at step212, the Rx DSP100continues to perform timing recovery (TR) by calculating timing error in Baud τBaudusing the timing error calculator132. The timing error calculator132inFIG.2uses the output W(m) from the adder154to obtain the determinant as follows:

The timing error calculator132derives the angle of the determinant, which contains timing error information represented by the equation below:

whereN is the number of the sample data points,k is an integer, andf=kNfs,k is an integer smaller than N,fs is a sampling rate equal to the baud rate.

The mean of difference of φ is:

and τBaudis:

Using τBaud, the loop filter134inFIG.2tunes the VCO90by the following filter:

where µpand µiare step sizes, n is an integer.

In some examples, the loop filter134tunes the VCO90by the following filter:

Filter (8) converges faster than filter (7) by using the sign() function.

VCO90in turn adjusts the sampling operation of the ADC80such that the timing error τBaudgenerated at the ADC80may be further reduced. At step214, if the RMS value of timing errors τBaudof recent p blocks of data is less than or equal to a threshold, the timing recovery (TR) of the MIMO module124is locked. If τBaudis greater than the threshold at step214, MIMO module124repeats steps208-214until timing error τBaudis less than or equal to the threshold and the timing recovery (TR) is locked.

InFIG.3, after the TR is locked, to synchronize the frames of the digital signals X and Y at the receiver14, the MIMO module124proceeds to a framer process at step216in order to determine the position of the training symbols in the digital signals X and Y.

Before the framing process, the MIMO module124saves the converged MIMO tap values as Hxx, Hyy, Hxy, Hyx.

At step216, during the framing process, the MIMO module124correlates the timing recovered digital signal X and Y in frequency domain with the correlation results of the training sequence in frequency domain and the converged MIMO taps after blind equalizer at step208.

In some examples, at step216, the timing recovered digital signals X and Y input to the MIMO module124are denoted as:

x and y are timing recovered signals at step212.

The values of the MIMO taps update module130are the vector multiplication results of the frequency domain training sequences in X and Y polarizations and respective MIMO taps update module130before framing process:

where TrainSeqx, TrainSeqy are formed by the training symbols in the X and Y-polarized signals, and Hxx, Hyy, Hxy, Hyxare vectors containing converged MIMO taps values before framing process.

By correlating (multiplying in frequency domain) the input digital signals with MIMO taps update module130at the MIMO module124, the MIMO module124derives the position of the training symbols in a frame in accordance with the position of the maximum correlation value.

At step216, the MIMO module124suspends the MMO taps updating and timing recovery (TR) during the framer process. As MIMO module124has already been locked at step216, only limited number of blocks of data is sufficient in the framing process to identify the training symbol position in the frame.

In short-reach applications, for example the distance between the transmitter12and the receiver14is within 40 Kilometers, as the adaptive channel impairments varies slowly and timing variation is slow, temporary suspension of MIMO and TR updating generally does not affect performance, such as Bit Error Rate (BER). In the worse circumstance, the framer may be misaligned by one or more symbols. Due to the misalignment, the estimated timing error may shift by one or more symbols. Although the timing error τBaudmay gradually reduce to 0, the BER of the digital signals may increase.

To solve this problem, the MIMO module124may adjust a framer index by the number of symbols corresponding to the number of symbols of a timing error shifting. For example, once the timing error is shifted by one or more symbols after framer at step216, the MIMO module124may accordingly adjust framer index by one or more symbols to reduce the BER. As such, the BER may be maintained at an acceptable range.

Before the framer synchronization, as discussed above, as the location of the training symbol at the step208is unknown, the MIMO taps update module130is updated by the desired response generated by the slicer129. After the famer synchronization at step216, the MIMO module124is able to identify the position of the training symbols in a frame, and the location of payload data in a frame. As such, the MIMO module124may further update the MIMO taps update module130with the training symbols to further compensate the impairment at step218.

At step218, MIMO module124turns on the CR module128inFIG.2and uses training symbols to further update the MIMO taps update module130. The input signal to the MIMO module124are denoted as follows:

where x and y are TR locked digital signals in time domain. The initial value of the MIMO taps update module130at step218are as follows:

In the example ofFIG.2, after the save last block module127removes first N samples from time domain digital signals x and y, the time domain digital signals x and y are input to the CR module128. The CR module128is configured to compensate the carrier frequency offset and phase shift in signals x and y. The carrier frequency offset and phase shift compensated signals x and y are then provide to the slicer129.

The slicer129, based on the identified position of the training symbols in the digital signals x and y at step216, compares the training symbols in the digital signals x and y from the save last block module127with the standard training symbols, and compares the payload portion with a desired response. The slicer129generates a time domain error signal using the comparison results of the training symbols and the payload. By using the training symbols as the reference value, the slicer129can more accurately determine the error signal than using blind desired response at step208.

The time domain error signal is provided to insert zero block module152for updating the MIMO taps update module130as described at step208above. The MIMO taps update module130may be updated in accordance with equations (3)-(6) described above, and MIMO module124updates the signal X and Y in frequency domain in accordance with equations (1)-(2).

The digital signals output from the CR module128may be used for further processing by the Rx DSP100, such as Forward Error Correction (FEC).

At step218, the MIMO module124updates the MIMO taps until the rms value of a time domain error of the digital signal X- and Y-polarizations is smaller than or equal to a second predetermined threshold. In some examples, the second predetermined threshold is smaller than the first predetermined threshold used for equalizing the digital signals at step208. As such, at step218, the errors in signals X and Y is in a smaller scale than the blind equalizing processing step208without using the training symbols.

For each subsequent signal received by the Rx DSP100, the MIMO module124may update MIMO taps update module130using only step218, without performing steps202-216.

As described above, the frequency domain signals X and Y are multiplied at the MIMO module124with the vectors of MIMO taps update module130for various impairment compensations. Frequency domain vector multiplication corresponds to correlation operation in time domain. As the MIMO module124processes the X and Y signals by vector in frequency domain, the processing speed of MIMO module124in frequency domain is therefore faster than processing one signal at a time in the time domain. As such, processing the X and Y signals in frequency domain by the MIMO module124also saves power.

In some examples, the MIMO module124may be a single-stage FDMIMO for the Rx DSP100to further reduce power consumption. Single-stage FDMIMO is disclosed in a related patent application No. 63/010,827, entitled “System and Method for signal-stage Frequency-Domain Equalization”, filed on Apr. 16, 2020, the content of which is incorporated herein in its entirety by reference.

The Rx DSP100for the receiver14provides a low-power and efficient symbol-rate Rx DSP scheme.FIG.4shows BER performance comparison of T/1.25 (sampling rate = 1.25*symbol rate) DSP and T/1 Rx DSP100at a receiver 14 in terms of received optical power (ROP) at ideal and typical test cases, respectively. Compared with T/1.25, the power consumption of Rx DSP100in T/1 in the present disclosure can be saved by around 20% for ADC80. The total saved power by the T/1 Rx DSP100may reach 30%.

It should be noted that for all the tests measured, S21 is used for both the transmitter12and receiver14, and that the ideal case is B2B case with no impairments except for S21, while ‘typical’ case corresponds to a 10 km transmission scenario with various impairments.

In ideal case, Rx DSP100performs 0.2 dB worse than T/1.25 at a Forward Error Correction (FEC) threshold of 1.25e-2. This penalty comes from imperfection of S21 shape and aliasing. While in typical case, Rx DSP100performs 0.7 dB worse than T/1.25. The increased penalty in the typical case comes from the limited ability of impairment compensation in T/1, such as skew compensation. However, the penalty is acceptable for the low-power design.

FIG.5is a block diagram, illustrating an example hardware structure of the Rx DSP100. InFIG.5, the Rx DSP100comprises a processing unit102, an Input / Output (I/O) interface104, and a memory108.

The processing unit102may be a processor, a microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a dedicated logic circuitry, or combinations thereof.

The input/output (I/O) interfaces104allows to receive input digital signals105from the ADC80and to transmit processed digital signals106for further processing in system10.

The memory108may include a volatile or non-volatile memory e.g., a flash memory, a random-access memory (RAM), and/or a read-only memory (ROM). The non-transitory memory108may store instructions for execution by the processing unit102, such as to carry out methods or processes described in the example of the present disclosure. The memory108may include other software instructions, such as for implementing an operating system and other applications/functions.

In the Rx DSP100, the Fast Fourier Transformation (FFT) module120, IQC unit122, 2x2 multiple input multiple output (MIMO)124, IFFT module126, Carrier Recovery (CR) module128and the timing error calculator132may be implemented by the processing unit102, and MIMO taps updating module130may be implemented in the processing unit102and memory108.

In some other examples, memory108may be provided by a transitory or non-transitory computer-readable medium. Examples of non-transitory computer readable media include a RAM, a ROM, an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a CD-ROM, or other portable memory storage.

The bus110providing communication channels among components of the Rx DSP100, including the processing unit102, I/O interface104, and/or memory108. The bus108may be any suitable bus architecture including, for example, a memory bus, or a peripheral bus.

An example embodiment is a method for processing signals in a receiver, comprising: receiving a digital signal at a symbol rate in frequency domain; and compensating an impairment of the digital signal in frequency domain.

In another example embodiment, in the preceding methods, compensating the impairment comprises compensating the digital signal in an in-phase and quadrature skew and a quadrature error in frequency domain.

In another example embodiment, in the preceding methods, the in-phase and quadrature skew of the digital signal in X polarization is compensated by

where XQ is a phase Q of signal X in frequency domain, and Δτ is a skew of signal X.

In another example embodiment, in the preceding methods, the quadrature error of the digital signal in X polarization is compensated by

where XI is phase I of the digital signal in X polarization in frequency domain, and ΔErr is quadrature errors of the digital signal in X polarization.

In another example embodiment, in the preceding methods, compensating the impairment comprises: determining, at a 2x2 multiple input multiple output (MIMO), a clock frequency offset estimation Δfclk-estand a carrier frequency offset estimation Δƒestin the digital signal; and adjusting a sampling clock frequency of an analog to digital convertor (ADC) of the receiver by a -Δƒclk-est.

In another example embodiment, the preceding methods further comprise: compensating, at an In-phase Quadrature Compensation (IQC), the digital signal in frequency domain by a -Δƒest.

In another example embodiment, in the preceding methods, the Δƒclk-estand the Δƒestis determined by correlating in frequency domain, at the 2X2 MIMO, digital signals x and y in time domain in X- and Y-polarizations with a MIMO taps:

and where TrainSeqx and TrainSeqy are training sequences of signals x and y in X- and Y-polarizations, respectively, wherein the Δƒclk-estand the Δƒestcorrespond to scan values at a maximum correlation peak value.

In another example embodiment, in the preceding methods, compensating the impairment of the digital signal comprises: equalizing the digital signals in X- and Y- polarizations in frequency domain until a time domain error signal of the digital signal X- and Y-polarizations is less than or equal to a predetermined threshold.

In another example embodiment, in the preceding methods, equalizing the digital signals in X- and Y- polarizations in frequency domain comprises: correlating the digital signals in X- and Y- polarizations in frequency domain with the MIMO taps, wherein values of the MIMO taps are:

and updating the digital signals in X- and Y-polarizations by

where Hcompis a compensation response to compensate non-time-varying fixed impairments.

In another example embodiment, in the preceding methods, equalizing the digital signals in X- and Y- polarizations in frequency domain comprises: updating the MIMO taps by

where X*(m) and Y*(m) are conjugate of the frequency domain digital signals containing X(m) and Y(m) in x and y polarization respectively,Ex(m) and Ey(m) are error signals associated with the frequency domain digital signals X(m) and Y(m) respectively, andG{.} is a gradient constraint, and µ is a step function.

In another example embodiment, the preceding methods further comprise:determining a timing error τBaudof the digital signal; andtuning, by a loop filter, a voltage-controlled oscillator (VCO) until the timing error is less than or equal to a threshold.

In another example embodiment, in the preceding methods, the timing error τBaudis determined based on

where Wxx, WyyWxy. Wyxare converged MIMO tap values, N is sample data point number, and

is a frequency of the digital signals, K is an integer smaller than N, fs is a sampling rate equal to a baud rate.

In another example embodiment, in the preceding methods, the loop filter tunes the VCO using a following equation:

In another example embodiment, in the preceding methods, the loop filter tunes the VCO using the following equation:

In another example embodiment, the preceding methods further comprise:suspending MIMO and timing recovery updating; anddetermining a position of training symbols in the digital signal.

In another example embodiment, in the preceding methods, determining the position of training symbols in the digital signal comprises: correlating timing error recovered digital signal in X- and Y- polarizations in frequency domain with the MIMO taps having values of:

where TrainSeqx and TrainSeqy are formed by the training symbols in the X and Y-polarized signals in time domain, and Hxx, Hyy, Hxy, Hyxare converged MIMO taps after equalizing the digital signal in X- and Y- polarizations in frequency domain.

In another example embodiment, the preceding methods further comprise adjusting, by the 2X2 MIMIO, a framer index corresponding to a timing error shifting amount.

In another example embodiment, the preceding methods further comprise: determining a time domain error of the digital signal X- and Y-polarizations in time domain by using training symbols; and updating MIMO taps until the time domain error of the digital signal X- and Y-polarizations is smaller than or equal to a second predetermined threshold.

In another example embodiment, in the preceding methods, updating the MIMO taps comprises updating the MIMO taps by:

where X* (m) and Y* (m) are conjugate of the frequency domain digital signals containing X(m) and Y(m) in x and y polarization respectively,Ex(m) and Ey(m) are error signals associated with the frequency domain digital signals X(m) and Y(m) respectively,G{.} is a gradient constraint, and µ is a step function,wherein initial value of the MIMO taps are as follows:

In another example embodiment, in the preceding methods, the second predetermined threshold is smaller than the predetermined threshold.

In another example embodiment, the preceding methods further comprise compensating for frequency offset and phase shift of the digital signals using a carrier recovery.