Power delivery architecture to increase performance of computing systems when docked

A power delivery architecture for a computing system is described. In one embodiment, an apparatus comprises a docking station; and a computing system removably coupled to the docking station and having a plurality of components and a power delivery subsystem to deliver power to integrated circuit (IC) components under direction of a controller, where the controller is communicably coupled to the docking station when the docking station is coupled to the computing system to cause power from the docking station to be delivered to at least one of the components with power from the power delivery system.

FIELD OF THE INVENTION

Embodiments of the present invention relate to the field of power delivery for computing devices (e.g., mobile phones, computer systems, etc.); more particularly, embodiments of the present invention relate to power delivery to a computing system in part from a docking station when the computing system is docked, which may allow the computing system to increase performance by using the additional power that it receives.

BACKGROUND OF THE INVENTION

Portable computing systems, such as laptops and mobile phones, run a variety of applications. The different applications utilized different amounts of computing resources to perform various operations. Because some applications require more resources, running those applications often requires more power consumption. However, as designers of portable computing systems have tried to develop lighter or more streamlined versions of such devices with reduced power consumption, some devices are not capable of executing some applications that require more power or cannot run such applications on certain devices or run them fully as running these applications increases power consumption and depletes power resources (e.g., batteries) too quickly for a user. Thus, it would be desirable to be able to provide additional power resources at times to allow such devices to execute such applications.

Docking stations are well known in the art to provide an easy way for a computing device such as a laptop computer to connect to peripheral devices. By simply plugging the computing device into the docking station, the computing device is able to access the peripheral devices.

The use of docking stations is not limited to connecting to peripheral devices. Docking stations have been used to increase performance of a computing device because the docking station provides some functionality to facilitate the higher performance. For example, some docking stations for laptops provide thermal functionality such that when a computing system is plugged into the docking station, the docking station blows air on the laptop to provide additional cooling for higher performance when the laptop is used on a desk. Additional graphics or storage has been including in docking stations to enhance functionality as well.

DETAILED DESCRIPTION OF THE PRESENT INVENTION

FIG. 1is a block diagram of a phone system with a docking station. The phone system may be docked or undocked with the docking station. Referring toFIG. 1, phone system100comprise a system-on-a-chip (SoC)101that is powered by two power phases, referred to herein phase 1 and phase 2. Both phases 1 and 2 are each 12 A and are provided by power stages103and104, respectively. A voltage regulator (VR) controller, or power management integrated circuit (PMIC),102is coupled to power stages103and104via control and sense signals111and112, respectively. Using signals111and112, VR controller102senses the power being provided by power stages103and104and controls power stages103and104. The control of power stages103and104by VR controller102may be in response to signals from SoC101received on a Serial Voltage Identification (SVID) bus110. For example, SoC101may specify a power state into which SoC101is to transition. In such as case, VR controller102receives this information over SVID bus110and uses signals111and112to power down one or both of phase 1 and phase 2, respectively, depending on the power state specified by SoC101.

FIG. 2is a block diagram of one embodiment of a system architecture having a computing system and a docking station. In one embodiment, the computing system is a portable device. The computing system may be phone, a laptop or other computer system, tablet, personal digital assistant (PDA), etc. The computing system is removably coupled to the docking station so that it can be coupled or uncoupled by a user. In one embodiment, the computing system has a number of components (e.g., integrated circuits (ICs)), including a power delivery subsystem to deliver power to components under direction of a controller. The controller is communicably coupled to the docking station such that when the computing system is docked in or on the docking station, the controller is able to cause power from the docking station to be delivered to at least one of the components along with power separately provided from the power delivery system.

Referring toFIG. 2, computing system200(e.g., a phone system, laptop computer, etc.) comprise an integrated circuit (IC) component201(e.g., a system-on-a-chip (SoC), processor, controller, etc.) that is powered by one or two phases. Phase 1 is provided by power state203, which is part of computing system200. Phase 2 is provided by power stage204which is part of docking station250. However, because phase 2 is provided by docking station250, computing system200only receives phase 2 from power stage204when computing system200is docked, or otherwise coupled to, docking station250. Note that other components in computing system200may be powered by one or both phases 1 and 2.

In one embodiment, both phases 1 and 2 are each 12 A, thereby having a 50/50 split between the power provided by the two sources to IC201. However, in other embodiments, the two phases do not have to provide the same amount of power and other splits are possible. That is, other percentages could be used. For example, one phase may provide 70% of the power while the other phase provides 30% of the power to IC201. To provide a total of 24 A, other examples include having one phase providing 9 A, while the other phase provides 15 A or one phase providing 3 A, while the other phase provides 21 A. Note that the teachings disclosed herein are not limited to providing 24 A. This is merely an example. The split between phases may be based on the computing system size (e.g., the phone system size) and the available real estate of the computing system.

Furthermore, the teachings disclosed herein are not limited to having only two phases. There may be three or more phases. In such a case, in one embodiment, the computing system may have multiple power stages providing multiple phases, with only one phase provided by the docking station, or in another embodiment, the docking station may have multiple power stages providing multiple phases, with only one phase (or more than one phase) provided by the computing system.

Computing system200includes a voltage regulator (VR) controller202. In one embodiment, VR controller202is part of a power management integrated circuit (PMIC). VR controller202is coupled to power stage203via control and sense signals211. When computing system200is docked with docking station250, VR controller202is also coupled (e.g., communicably coupled) to power stage204via control and sense signals212.

In one embodiment, docking station250is coupled to provide power to IC201and signaling with controller202through a connector230. In one embodiment, connector230comprises a flexible printed circuit (FPC) cable. In another embodiment, connector230includes contacts that mate with contacts of computing system200when computing system200is docked with docking station250. Note that other cables/connections having low impedance and a minimum voltage drop may be used as well.

Using signals211and212, VR controller202senses the power being provided by power stages203and204and controls power stages203and204. The control of power stages203and204by VR controller202may be in response to signals from IC201received on SVID bus210. For example, IC201may specify a power state into which IC201is to transition. In such as case, VR controller202receives this information over SVID bus210and uses signals211and212to control the power delivery by power stage203itself when undocked and by power stages203and204when docked in docking station250. The control may including powering down one or both of phase 1 and phase 2 depending on the power state specified by IC201.

In one embodiment, IC201comprises a configurable load line that is changed in response to computing system200being docked with or undocked from docking station250. In one embodiment, the control provided by VR controller202with respect to the power provided by power stage203and power stage204(if docked) is based on the dynamically changeable load line. In one embodiment, IC201includes an input (e.g., pin, contact, etc.) to receive an indication (e.g., a signal) as to whether computing system200is docked in docking station250and configures the load line and controls VR controller202based on the indication.

In one embodiment, IC201also has a current limit that is removed in response to computing system200being docked in docking station250. In this case, there is no limit or default. That is, if there is no limit, the maximum current specification for IC201is the limit. In one embodiment, this is controlled based knowledge of the power capability of the system to supply power to IC201. This can ca be performed statically by setting the BIOS. In another embodiment, dynamic battery power sensing technology knows what the power to IC201is and dynamically changes the Iccmax current limitation based on the input power source capability.

FIG. 3is a more detailed block diagram of an embodiment of a VR-based power delivery system. Referring toFIG. 3, as inFIG. 2, VR controller202generates power and provides the power to power stages203and204, which represent phases 1 and 2, respectively. Each of power stages203and204includes a gate driver and power gate switches (e.g., field effect transistors (FETs)). For example, power stage203includes gate driver301coupled to FETs302and303, while power stage204includes gate driver304coupled to FETs305and306. FETs302and305are connected to the system power, while FETs303and306regulate the output voltage. Each of the power stages203and204outputs power to inductors311and312, respectively. Each of the inductors311and312are coupled to bulk and ceramic capacitors313and314, respectively, which outputs a voltage Vout. The output voltage Vout is provided to power one or more ICs and devices, such as IC201(e.g., CPU, processor, SoC, etc.). Also, both power stages includes a sensing resistor (321,322) to enable VR controller202to sense the power each power stage is providing.

FIG. 4is a block diagram of another embodiment of a system architecture having a computing system and a docking station. The system architecture inFIG. 3is similar to that ofFIG. 2except the computing system300also is able to provide phase 2 power to IC301in the same way as phase 2 power is provided inFIG. 1.

There are two basic limitations to the power delivery. First, there is real estate limitation that limits the amount of power delivery that can be placed in the system. Second, besides real estate, the proximity of the power delivery subsystem to the IC (e.g., processor, SoC, etc.). These two traditional power deliver limitations, the amount of power that can be drawn from the FETs, which is limited as the current maximum of an IC, referred to herein as ICCmax, and the speed at which power can be drawn by the IC, which is limited by the AC load line of the IC, are overcome by the techniques described herein.

More specifically, in one embodiment, IC201has a programmable load line which allows for relaxing the requirement on the proximity when in docked mode without affecting the operation of the device in un-docked mode. By having a programmable load line, the power delivery may be split between the device and the docking station, thereby significantly improving the performance in docked mode without degrading the performance in the device mode. Thus, there are two different power delivery implementations with different requirements, which are made possible by the configurable AC load lines of the IC.

FIG. 5Ais an example processing flow that explains the concept with some example numbers for a design. Referring toFIG. 5A, the IC (e.g., IC201) performs a test to determine if the computing system is docked in the docking station, referred to herein as being docked, or is undocked from the docking station, referred to herein as device mode. In one embodiment, the results of the test are based on information from a logical pin of the IC to inquire as to whether the computing system is in docked or device mode. The information indicates to the IC whether the other power phase is available, which controls the IC so that it never draws more power than is available to it.

In one embodiment, the IC has the capability to program the load line and Iccmax dynamically. In one embodiment, these are programmed independently. In one embodiment, the load line is programed statically (e.g., programming a Basic Input Output System (BIOS) setting). In one embodiment, if the device is in docked mode, the Iccmax limit is removed or at least set sufficiently high that it no longer limits performance. In one embodiment, the frequency of the processor is only limited by the load line. For example, in one IC for an ideal zero load line, the processor frequency limit is 3 Ghz. However because part of the power delivery is in the device, the load line is degraded from an ideal zero to 8 mOhns. The load line degrades due to the impedance (e.g., resistance) of the printed circuit board (PCB) formed and the components, which cause the drop. The noise is 160 mV so there is a loss of nearly 360 Mhz for a nominal 1V IC. The net frequency is 2.54 Ghz. If the device is in un-docked mode, in one embodiment, the current limit (e.g., Iccmax) is reset to 5 A and the load line is improved from 8 mOhms to 5 mOhms. In this case, the device Iccmax limit is about 2 Ghz. The AC load line loss is only 100 mV 200 Mhz (10%) frequency loss. The net frequency is 1.8 Ghz. Thus, the net gain from going from the device mode to the docked mode is 700 Mhz.

To compensate for power delivery transients, which can occur in nanoseconds, the computing system needs to draw additional current from the dock in a very few clocks. This requires a sufficient amount of charge, in the form of large capacitors very close to the processor. In one embodiment, to accommodate this, more FETs (than available from the computing system200) are placed in the docking station (e.g., docking station250) to provide higher steady state currents while reducing the requirements on the transients when in docked mode. This can be done because the AC load line in the IC (e.g., IC201(e.g., processor, SoC, etc.)) receiving the power can be programmed.

In one embodiment, the load degradation is reduced when docked to reduce the impact on performance. If the degradation is so large, it wipes out the benefit of the additional Iccmax capability. By placing the FETS and other components in the docking station very close (e.g., less than 10 mm) to the IC being powered, a low impedance path from the docking station to the IC in the computing system being powered by the power delivery subsystem is created. In one embodiment, the low impedance path is created by using very short pin less connectors between the device and docking station.

FIG. 5Billustrates an example of estimated performance improvement using the techniques described herein. Referring toFIG. 5B, the performance of two different phone modes, referred to as phone mode1 and phone mode2. Phone mode1 is one in which the phone includes a power delivery subsystem that provides a 12 A power phase with another 12 A power phase coming from the docking station, while phone mode2 is one in which the phone includes a power delivery subsystem that provides a 15 A power phase along with 9 A power phase coming from the docking station. In the docket mode, both phones include an IC (e.g., SoC, processor, etc.) that receives 24 A.

With respect to increased performance; when the computing system is docked, in one embodiment, an indicator informs the system and the IC (e.g., IC201ofFIG. 2, processor, SoC, etc.) that there is more (or adequate) power to run an application which requires high performance (or power). However, in device mode, the system and IC knows there's less power that will limit the maximum frequency at which the IC can run, which limits performance. In one embodiment, whether or not to allow system to run certain applications in device or docked mode is controlled by software or an operating system to limit the usage or apply power based on priority. In one embodiment, using this type of control, photoshop type and other similar applications can only run when computing device is docked. In one embodiment, when in device mode, only the less power and/or performance hungry applications can be used such as, for example, Facebook, text, web surfing, emails, or video playback, where less performance is needed as opposed to, for example, gaming (2D or 2.5D)

FIG. 6is a flow diagram of one embodiment a process for controlling power delivery in a computing device (e.g., computer system, mobile phone system, etc.). The process is performed by processing logic that may comprise hardware (circuitry, dedicated logic, etc.), software (such as is run on a general purpose computer system or a dedicated machine), firmware, or a combination of the three.

Referring toFIG. 6, the process begins by processing logic signaling that a computing system has been docked to a docking station, where the computing system has a plurality of components and a power delivery subsystem to deliver power to integrated circuit (IC) components under direction of a controller (processing block601).

In response to docking, processing logic in the IC component (e.g., a processor, SoC, controller, etc.) receives an indication as to whether the computing system is docked in the docking station (processing block602).

In response to receiving the indication, processing logic in the IC component removes its current limit (processing block603) and changes its load line (processing block604).

Processing logic in the IC also controls a power deliver controller (e.g., VR controller, PMIC, etc.) based on the load line using a bus coupling the IC component and the controller (processing block605). In one embodiment, the bus comprises a Serial Voltage Identification (SVID) bus.

In response to the signaling, processing logic in the controller controls a power stage in the docking station to deliver power from the docking station to the IC component and a power stage in the power delivery subsystem in the computing system to deliver power from the power delivery system to the IC component (processing block606). In one embodiment, this includes signaling the docking station through a connector (e.g., a flexible printed circuit (FPC) cable, contacts, etc.) that is coupled to provide power to the at least one IC component from the docking station.

An Example of a System Containing a Power Delivery System

FIG. 7is one embodiment of a system level diagram700that may incorporate the techniques described above. For example, the techniques described above may be incorporated into a processor in system700or other part of system700.

Referring toFIG. 7, system700includes, but is not limited to, a desktop computer, a laptop computer, a netbook, a tablet, a notebook computer, a personal digital assistant (PDA), a server, a workstation, a cellular telephone, a mobile computing device, a smart phone, an Internet appliance or any other type of computing device. In another embodiment, system700implements the methods disclosed herein and may be a system on a chip (SOC) system.

In one embodiment, processor710has one or more processor cores712to712N, where712N represents the Nth processor core inside the processor710where N is a positive integer. In one embodiment, system700includes multiple processors including processors710and705, where processor705has logic similar or identical to logic of processor710. In one embodiment, system700includes multiple processors including processors710and705such that processor705has logic that is completely independent from the logic of processor710. In such an embodiment, a multi-package system700is a heterogeneous multi-package system because the processors705and710have different logic units. In one embodiment, processing core712includes, but is not limited to, pre-fetch logic to fetch instructions, decode logic to decode the instructions, execution logic to execute instructions and the like. In one embodiment, processor710has a cache memory716to cache instructions and/or data of the system700. In another embodiment of the invention, cache memory716includes level one, level two and level three, cache memory, or any other configuration of the cache memory within processor710.

In one embodiment, processor710includes a memory control hub (MCH)714, which is operable to perform functions that enable processor710to access and communicate with a memory730that includes a volatile memory732and/or a non-volatile memory734. In one embodiment, memory control hub (MCH)714is positioned outside of processor710as an independent integrated circuit.

In one embodiment, processor710is operable to communicate with memory730and a chipset720. In such an embodiment, SSD780executes the computer-executable instructions when SSD780is powered up.

In one embodiment, processor710is also coupled to a wireless antenna778to communicate with any device configured to transmit and/or receive wireless signals. In one embodiment, wireless antenna interface778operates in accordance with, but is not limited to, the IEEE 802.11 standard and its related family, HomePlug AV (HPAV), Ultra Wide Band (UWB), Bluetooth, WiMAX, or any form of wireless communication protocol.

Memory730stores information and instructions to be executed by processor710. In one embodiment, chip set720connects with processor710via Point-to-Point (PtP or P-P) interfaces717and722. In one embodiment, chipset720enables processor710to connect to other modules in the system700. In one embodiment, interfaces717and722operate in accordance with a PtP communication protocol such as the Intel QuickPath Interconnect (QPI) or the like.

In one embodiment, chip set720is operable to communicate with processor710,705, display device740, and other devices772,776,774,760,762,764,766,777, etc. In one embodiment, chipset720is also coupled to a wireless antenna778to communicate with any device configured to transmit and/or receive wireless signals.

In one embodiment, chip set720connects to a display device740via an interface726. In one embodiment, display device740includes, but is not limited to, liquid crystal display (LCD), plasma, cathode ray tube (CRT) display, or any other form of visual display device. In addition, chipset720connects to one or more buses750and755that interconnect various modules774,760,762,764, and766. In one embodiment, buses750and755may be interconnected together via a bus bridge772if there is a mismatch in bus speed or communication protocol. In one embodiment, chipset720couples with, but is not limited to, a non-volatile memory760, a mass storage device(s)762, a keyboard/mouse764, and a network interface766via interface724, smart TV776, consumer electronics777, etc.

FIG. 7also includes power delivery790that provides power to components of system700. In one embodiment, power delivery790is a VR-based power delivery system such as, for example, those shown inFIGS. 2-4, and includes one or more reconfigurable coupled inductors as described herein. In one embodiment, power delivery790controls the one or more power stages based on control signals from an IC (e.g., SoC, processor, etc.) in the system. In one embodiment, such control signals are sent on a SVID bus.

While the modules shown inFIG. 7are depicted as separate blocks within the system700, the functions performed by some of these blocks may be integrated within a single semiconductor circuit or may be implemented using two or more separate integrated circuits.

In a first example embodiment, an apparatus comprises a docking station; and a computing system removably coupled to the docking station and having a plurality of components and a power delivery subsystem to deliver power to integrated circuit (IC) components under direction of a controller, where the controller is communicably coupled to the docking station when the docking station is coupled to the computing system to cause power from the docking station to be delivered to at least one of the components with power from the power delivery system.

In another example embodiment, the subject matter of the first example embodiment can optionally include that the at least one IC component comprises a configurable load line that is changed in response to the computing system being docked in the docking station or undocked from the docking station. In another example embodiment, the subject matter of this example embodiment can optionally include a bus coupling the at least one IC component and the controller to enable the at least one IC component to control the controller based on the load line. In another example embodiment, the subject matter of this example embodiment can optionally include that the bus comprises a Serial Voltage Identification (SVID) bus.

In another example embodiment, the subject matter of the first example embodiment can optionally include that the at least one IC component has a current limit that is removed in response to the computing system being docked in the docking station. In another example embodiment, the subject matter of this example embodiment can optionally include that the at least one IC component includes an input to receive an indication as to whether the computing system is docked in the docking station and configures the load line and controls the controller based on the indication.

In another example embodiment, the subject matter of the first example embodiment can optionally include that the docking station is coupled to provide power to the at least one IC component and signaling with the controller through a connector. In another example embodiment, the subject matter of this example embodiment can optionally include that the connector comprises a flexible printed circuit (FPC) cable. In another example embodiment, the subject matter of this example embodiment can optionally include that the connector includes contacts that mate with contacts of the computing system when the computing system is docked with the docking station.

In another example embodiment, the subject matter of the first example embodiment can optionally include that the at least one IC component comprises a processor or a system-on-a-chip (SoC) and the power delivery subsystem includes a voltage regulator, wherein the controller is operable to control the voltage regulator.

In a second example embodiment, a method comprises signaling that a computing system has been docked to a docking station, wherein the computing system has a plurality of components and a power delivery subsystem to deliver power to integrated circuit (IC) components under direction of a controller, and in response to the signaling, controlling a power stage to deliver power from the docking station to at least one of the components with power from the power delivery system.

In another example embodiment, the subject matter of the second example embodiment can optionally include changing the load line of the at least one IC component in response to the computing system being docked in the docking station or undocked from the docking station. In another example embodiment, the subject matter of this example embodiment can optionally include controlling the controller based on the load line using a bus coupling the at least one IC component and the controller. In another example embodiment, the subject matter of this example embodiment can optionally include that the bus comprises a Serial Voltage Identification (SVID) bus.

In another example embodiment, the subject matter of the second example embodiment can optionally include removing a current limit in response to the computing system being docked in the docking station.

In another example embodiment, the subject matter of the second example embodiment can optionally include receiving an indication, by the at least one IC component, as to whether the computing system is docked in the docking station and changing the load line and controlling the controller based on the indication.

In another example embodiment, the subject matter of the second example embodiment can optionally include signaling between the docking station and the controller through a connector that is coupled to provide power to the at least one IC component from the docking station. In another example embodiment, the subject matter of this example embodiment can optionally include that the connector comprises a flexible printed circuit (FPC) cable. In another example embodiment, the subject matter of this example embodiment can optionally include that the connector includes contacts that mate with contacts of the computing system when the computing system is docked with the docking station.

In another example embodiment, the subject matter of the second example embodiment can optionally include that the at least one IC component comprises a processor or a system-on-a-chip (SoC) and the power delivery subsystem includes a voltage regulator, wherein the controller is operable to control the voltage regulator.

In a third example embodiment, an article of manufacture has one or more non-transitory computer readable media storing instructions which, when executed by a system, cause the system to perform a method comprising: receiving, by an integrated circuit (IC), an indication that a computing system in which the IC resides as to whether the computing system is docked to a docking station; changing the load line of the IC in response to the indication indicating that the computing system is docked in the docking station; and controlling, by the IC, a controller in the computing system that controls a power delivery subsystem that delivers power to the IC based on whether the computing system is docked to a docking station.

In another example embodiment, the subject matter of the second example embodiment can optionally include that the method further comprises signaling a power stage in the docking station to provide power from the docking station to the IC in response to a control signal sent from the IC to the controller.

In another example embodiment, the subject matter of the second example embodiment can optionally include that the method further comprises providing power to the IC from the docking station while the IC also receives power from a power delivery system of the computing system.