Testing an integrated circuit

Testing an integrated circuit in a test environment that includes a virtual test engine and a test system with an integrated circuit tester. The integrated circuit is connected to the virtual test engine via the integrated circuit tester, and the integrated circuit tester is connected to the integrated circuit via an interface. The virtual test engine communicates with the integrated circuit tester via a command interface to perform functional test during functional test mode and to perform non-functional test during non-functional test mode.

PRIOR FOREIGN APPLICATION

This application claims priority from United Kingdom patent application number 1309302.6, filed May 23, 2013, which is hereby incorporated herein by reference in its entirety.

BACKGROUND

One or more aspects relate in general to the field of functional testing of hardware components, and in particular to a method and a test environment for testing an integrated circuit. Still more particularly, one or more aspects relate to a data processing program and a computer program product for testing an integrated circuit.

Currently, standard automatic test pattern generation (ATPG) is used to statically test hardware components like integrated circuits as device under test (DUT). The automatic test pattern generation (ATPG) is performed by an integrated circuit tester connected to the device under test via a first interface and allows full and fast control of the test patterns and utilizes tester capabilities like parameter variations, Shmoo plots, etc. The automatic test pattern generation (ATPG) is a well-established process (DFT) using state-based standard format and/or add-speed-BIST (Build in Selftest).

Current functional testing via a second control interface of the integrated circuit requires additional hardware for providing the applicable service protocol. This includes a specially prepared device under test load board, an additional workstation, wiring, and a protocol-capable front end device.

So the functional test needs external hardware attached to the device under test via the second interface and depends on external data describing chip specifications and/or chip access methods. The device under test (DUT) is set up to a functional stability state by the integrated circuit tester via the first interface, wherein the device under test (DUT) is stimulated by an external field service processor via the second interface. The response of the device under test (DUT) is captured by the field service processor and transmitted to a companion box comprising a workstation with engineering data of the device under test, test procedures and/or scripts and an input/output terminal, for example.

With such an approach a scheduler of the used test-system, comprising the integrated circuit tester, is not in charge of providing the test pattern to the device under test. Thus the tester software and/or pattern generator no longer tracks the inner state of the device under test. Higher-level functionality of the test system like shmoo plots and parameter variations cannot be utilized. Software effort for the additional second control interface would be required to control both the front end and the device under test. The granularity of the test result is limited by the pattern quality of the external workstation, wherein the test procedures are not identical to system drivers of the integrated circuit tester. Stopping at a specific event like a failure and/or hit condition is not possible, and there is no interference with the tester scheduler. It is difficult to identify both that there is an error and the location of the error.

BRIEF SUMMARY

In an embodiment, a method of testing an integrated circuit in a test environment is provided. The method includes, for instance, enabling a functional test mode of an integrated circuit wherein the integrated circuit is connected to a virtual test engine of the test environment via an integrated circuit tester of the test environment, the virtual test engine to communicate with the integrated circuit tester via a command interface to perform functional test during functional test mode and to perform non-functional test during non-functional test mode, and the integrated circuit tester is connected to the integrated circuit via an interface; creating and transmitting at least one of functional or non-functional test commands to said integrated circuit tester, wherein the integrated circuit tester creates and applies test patterns as stimulus data to the integrated circuit based on said functional test commands, receives and analyzes response data from the integrated circuit, and transmits test results including said response data to said virtual test engine for further analyzing; enabling the non-functional test mode of the integrated circuit in case a failure is detected during the functional test; shifting a serial bit stream out of the integrated circuit in the non-functional test mode, wherein the integrated circuit tester transmits the serial bit stream as an error bit stream to the virtual test engine for further analyzing; and wherein the virtual test engine creates and transmits at least one of further functional or non-functional test commands to the integrated circuit tester based on at least one of the test results or the error bit stream.

In another embodiment, a test environment for testing an integrated circuit is provided. The test environment includes, for instance, a virtual test engine and a test system with an integrated circuit tester, wherein the integrated circuit is connected to the virtual test engine via the integrated circuit tester, and the integrated circuit tester is connected to the integrated circuit via an interface; the virtual test engine to communicate with the integrated circuit tester via a command interface to perform a functional test during a functional test mode and to perform a non-functional test during a non-functional test mode of the integrated circuit, wherein the integrated circuit tester includes a test vector memory to generate at least one test pattern; the virtual test engine to create and transmit at least one of functional or non-functional test commands to the integrated circuit tester; the integrated circuit tester to create and apply test patterns as stimulus data to the integrated circuit based on said functional test commands, to receive and analyze response data from the integrated circuit, and to transmit test results including the response data to the virtual test engine for further analyzing; the virtual test engine to enable the non-functional test mode of the integrated circuit in case a failure is detected during the functional test, and the integrated circuit tester to shift a serial bit stream out of the integrated circuit in the non-functional test mode, and to transmit the serial bit stream as an error bit stream to the virtual test engine for further analyzing; and the virtual test engine to create and transmit at least one of further functional or non-functional test commands to the integrated circuit tester based on at least one of the test results or the error bit stream.

In a further embodiment, a computer program product for testing an integrated circuit in a test environment is provided. The computer program product includes, for instance, a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes, for instance, enabling a functional test mode of an integrated circuit, wherein the integrated circuit is connected to a virtual test engine of the test environment via an integrated circuit tester of the test environment, the virtual test engine to communicate with the integrated circuit tester via a command interface to perform functional test during functional test mode and to perform non-functional test during non-functional test mode, and the integrated circuit tester is connected to said integrated circuit via an interface; creating and transmitting at least one of functional or non-functional test commands to the integrated circuit tester, wherein the integrated circuit tester creates and applies test patterns as stimulus data to the integrated circuit based on said functional test commands, receives and analyzes response data from the integrated circuit, and transmits test results including the response data to the virtual test engine for further analyzing; enabling the non-functional test mode of the integrated circuit in case a failure is detected during the functional test; shifting a serial bit stream out of the integrated circuit in the non-functional test mode, wherein the integrated circuit tester transmits the serial bit stream as an error bit stream to the virtual test engine for further analyzing; and wherein the virtual test engine creates and transmits at least one of further functional or non-functional test commands to the integrated circuit tester based on at least one of the test results or the error bit stream.

DETAILED DESCRIPTION

FIG. 1shows a test environment1for testing an integrated circuit5, in accordance with an embodiment of the present invention;FIG. 2shows an internal logic of an integrated circuit5as device under test;FIG. 3shows direct response actions as part of a test protocol between an integrated circuit tester20and the device under test5, in accordance with an embodiment of the present invention;FIG. 4shows a direct driven action and an indirect response action as part of a test protocol between the integrated circuit tester20and the device under test5, in accordance with an embodiment of the present invention;FIG. 5shows a test command, in accordance with an embodiment of the present invention; andFIG. 6shows a test vector memory24, in accordance with an embodiment of the present invention.

Referring toFIGS. 1 to 6, the shown embodiment of the present invention employs a test environment1to test an integrated circuit5. The test environment1comprises a virtual test engine70and a test system100with an integrated circuit tester20, a switch unit40and an input/output terminal50. The virtual test engine70could be any server system or computer system or network suitable to run a corresponding test protocol or test program. The integrated circuit5is connected to the virtual test engine70via the integrated circuit tester20. The integrated circuit tester20is connected to the integrated circuit5via an interface30. The interface30comprises a service interface32and supply and input/output pins34. The virtual test engine70communicates with the integrated circuit tester20via a command interface22to perform a functional test during a functional test mode and to perform a non-functional test during a non-functional test mode of the integrated circuit5. In the shown embodiment the test system100is also connected to a dynamic test data base60holding firmware and specification of the integrated circuit5, i.e. the device under test.

The virtual test engine70runs a functional test protocol or test program and creates and transmits corresponding functional and/or non-functional test commands, exemplary shown inFIG. 5, to the integrated circuit tester20. Such functional and/or non-functional test commands each comprise a command identification block COMMAND; an address block ADDRESS; a data block DATA; and a port block PORT. The functional test commands comprise stimulus data and expected response data from the device under test5as function of the stimulus data. Further the virtual test engine could transmit windows or ranges for values of the expected response data and corresponding response time windows or ranges within which the device under test5has to transmit the response data.

The integrated circuit tester20comprises a test vector memory24to generate at least one test pattern and a scheduler26to execute the functional and/or non-functional test commands of virtual test engine70. The integrated circuit tester20creates and applies test patterns as stimulus data to the integrated circuit5based on the functional test commands, receives and analyzes response data from the integrated circuit5; and transmits test results including the response data to the virtual test engine70for further analyzing. During the analyzing process the integrated circuit tester20compares the test results with the expected response data of the functional test commands. Referring toFIGS. 3 and 4, the functional test protocol allows a direct response r1action to a corresponding stimulus action S1or an indirect response r1action via an intermediate response r2action and an intermediate stimulus action S1′ based on a certain stimulus S1. Further, the response action r1could cause or create new stimulus data S2. Still referring toFIGS. 3 and 4, the integrated circuit5, i.e. the device under test, can create the response action r1to different points of time t2, t3, t4, to based on the stimulus data S1. The time range within which the integrated circuit5, i.e. the device under test, has to deliver the corresponding response action r1is defined by the virtual test engine70or the test protocol or test program.

The virtual test engine70enables the non-functional test mode of the integrated circuit5in case a failure is detected during the functional test, and the integrated circuit tester20shifts a serial bit stream out of the integrated circuit5in the non-functional test mode, and transmits the serial bit stream as error bit stream to the virtual test engine70for further analyzing. The virtual test engine70creates and transmits further functional and/or non-functional test commands to the integrated circuit tester20based on the test results and/or the error bit stream.

The integrated circuit5comprises an internal logic10. Referring toFIG. 2, the internal logic10comprises a sub-device under test12, for example a functional entity with a certain first bandwidth, distribution nodes16and distribution channels with a certain second bandwidth and a protocol engine14connected to the service interface32and controlling the distribution channels and distribution nodes16based on stimulus data received from the integrated circuit tester20and response data created by the internal logic10.

Further the integrated circuit tester20is configured to shift a serial bit stream in the integrated circuit5during the non-functional test mode such that state-holding latches of the internal logic10are initialized to pre-defined values when the integrated circuit5is operated in the functional test mode afterwards. The integrated circuit tester20is further configured to read these latches by shifting a serial bit stream out of the integrated circuit5in the non-functional test mode. The integrated circuit tester20supplies the pre-defined serial bit stream via the service interface32being part of the interface30to the integrated circuit5to test. The integrated circuit5to test outputs the resulting serial bit stream via the service interface32to the integrated circuit tester20.

To perform at least one static test during the non-functional test the integrated circuit tester20supplies a corresponding static test bit pattern to the pins of the interface30. The test environment1is able to perform a contact test, a power test, or automatic test pattern generation test with the integrated circuit5, i.e. the device under test.

To perform the functional test the integrated circuit tester20prepares the test vector memory24by setting signal level, signal timing and pattern templates, wherein the integrated circuit tester20stores at least two pre-defined test patterns in the test vector memory24and selects one of the pre-defined bit patterns or any combination of composite bit pattern subsets in the test vector memory24in dependence of a subset of the bits in the received bit stream of the response data.

During the function test the integrated circuit tester20is able to create a shmoo plot by monitoring at least two parameters while varying at least one of the parameters over a specified range, based on a functional test command sequence. For example, the integrated circuit tester20is configured to perform a chip pad receiver test with the device under test5by variation of supply voltage versus process speed of the device under test5, and/or to perform a chip pad driver test with the device under test5and to scope an image of the chip response.

FIGS. 7 to 10show an exemplary implemented embodiment of a method for testing an integrated circuit5, in accordance with an embodiment of the present invention.

Referring toFIG. 7, after starting the method for testing an integrated circuit5in a test environment1the virtual test engine70enables the functional test mode of the integrated circuit5, i.e. the device under test, and sets the integrated circuit tester20to the non-functional test mode in step S200. Therefore the virtual test engine70creates and transmits a non-functional test command to the integrated circuit tester20. In step S210the integrated circuit tester20applies the non-functional test to the integrated circuit5, i.e. the device under test. In step S220the integrated circuit tester20proofs if the device under test5has failed the non-functional test. In case the device under test5has failed, the device under test5is disconnected in step S240and the testing of the device under test5is finished. In case the device under test5has passed the non-functional test, the virtual test engine70sets the integrated circuit tester20to the functional test mode in step S240. In step S250the integrated circuit tester20prepares the integrated circuit5and the test vector memory24for the functional test. The integrated circuit tester20supplies a stability bit pattern to all pins of the device under test5not involved in the functional test, for example. In step S300the virtual test engine70runs the functional test program, comprising the steps S310to S580.

Referring toFIGS. 8 to 10, the virtual test engine70creates and transmits a first functional test command to the integrated circuit tester20in step S310. In steps S320and S330the integrated circuit tester20reads the functional test command and creates a test pattern based on the functional test command. In step S340the integrated circuit tester20applies the test pattern as stimulus data to the device under test5. In step S350the integrated circuit tester20receives and analyzes response data from the device under test5. During the analyzing process in step S360the integrated circuit tester20compares the test result of the device under test5based upon the stimulus Data with the expected response data of the functional test command as function of the stimulus data. In step S370the integrated circuit tester20branches to step S500, shown inFIG. 10, in case a failure is detected. In case no failure is detected, the integrated circuit tester20transmits the test result including the response data to the virtual test engine70in step S380. In step S390the virtual test engine70receives and analyzes the test result by comparing the response data of the test result with the expected response data as function of the stimulus data. In step S400(FIG. 9) the virtual test engine70branches to step S510, shown inFIG. 10, in case a failure is detected. In case no failure is detected, the virtual test engine70proofs in step S410if further functional test commands are to be performed. In case no further functional test commands are to be performed, the virtual test engine70exits the functional test without fail in step S430and the testing of the device under test5is finished. In case at least one further functional test command is to be performed, the virtual test engine70transmits the next functional test command to the integrated circuit tester20in step S420. Then the method is continued with step S320, shown inFIG. 8.

Now referring toFIG. 10, in case the integrated circuit tester20has detected a failure in step S370, the integrated circuit tester20stops the functional test and sends a test stop response to the virtual test engine70in step S500. In step S510the virtual test engine70sets the integrated circuit tester20to the non-functional test mode and generates and transmits a non-functional test command in step S520to the integrated circuit tester20based on the test stop response or the test result. In step S530the integrated circuit tester20shifts a serial bit stream out of the integrated circuit5and transmits the serial bit stream as error bit stream to the virtual test engine70for further analyzing. The virtual test engine70stores and analyzes the error bit stream in step S540to decide if a further analyzing process is to perform. In case no further analyzing process is to perform, the virtual test engine70aborts the functional test in step S560and the testing of the device under test5is finished. In case a further analyzing process is to perform, the virtual test engine70sets the integrated circuit tester20to the functional test mode in step S570. In step S580the virtual test engine70generates and transmits the next functional test command to the integrated circuit tester20based on the error bit stream. Then the method is continued with step S320, shown inFIG. 8.

A technical problem underlying one or more aspects of the present invention is to provide a method and a test environment for testing an integrated circuit without the need of additional hardware for providing an applicable service protocol and which are able to solve shortcomings and pain points of prior art methods and test environments for testing integrated circuits.

Accordingly, in an embodiment, a method for testing an integrated circuit in a test environment comprises the steps of enabling a functional test mode of the integrated circuit; and creating and transmitting functional and/or non-functional test commands to an integrated circuit tester. The integrated circuit tester creates and applies test patterns as stimulus data to the integrated circuit based on the functional test commands, receives and analyzes response data from the integrated circuit; and transmits test results including the response data to a virtual test engine for further analyzing. In further steps the method enables a non-functional test mode of the integrated circuit in case a failure is detected during the functional test and shifts a serial bit stream out of the integrated circuit in the non-functional test mode. The integrated circuit tester transmits the serial bit stream as error bit stream to the virtual test engine for further analyzing. The virtual test engine creates and transmits further functional and/or non-functional test commands to the integrated circuit tester based on the test results and/or the error bit stream. The test environment comprises the virtual test engine and a test system with the integrated circuit tester. The integrated circuit is connected to the virtual test engine via the integrated circuit tester, the virtual test engine communicates with the integrated circuit tester via a command interface to perform the functional test during functional test mode and to perform the non-functional test during non-functional test mode, and the integrated circuit tester is connected to the integrated circuit via an interface.

In further embodiments, at least one of the following static tests is performed during the non-functional test: Contact test, power test, or automatic test pattern generation test.

In further embodiments, the test result and/or the error bit stream are analyzed by comparing response data of the test result or the error bit stream with expected response data as function of the stimulus data.

In further embodiments, the functional test protocol allows a direct response action or an indirect response action via an intermediate response action based on a certain stimulus.

In further embodiments, the integrated circuit tester supplies a stability bit pattern to all pins of the interface of the integrated circuit not involved in the functional test.

In further embodiments, the integrated circuit tester prepares a test vector memory by setting signal level, signal timing and pattern templates to perform the functional test.

In further embodiments, the integrated circuit tester stores at least two pre-defined test patterns in the test vector memory and selects one of the pre-defined bit patterns or any combination of composite bit pattern subsets in the test vector memory in dependence of a subset of the bits in the received bit stream of the response data.

In further embodiments, the integrated circuit tester creates a shmoo plot during the function test by monitoring at least two parameters while varying at least one of the parameters over a specified range.

In another embodiment, a test environment for testing an integrated circuit comprises a virtual test engine and a test system with an integrated circuit tester. The integrated circuit is connected to the virtual test engine via the integrated circuit tester connected to the integrated circuit via an interface. The virtual test engine communicates with the integrated circuit tester via a command interface to perform a functional test during a functional test mode and to perform a non-functional test during a non-functional test mode of the integrated circuit. The integrated circuit tester comprises a test vector memory to generate at least one test pattern. The virtual test engine creates and transmits functional and/or non-functional test commands to the integrated circuit tester. The integrated circuit tester creates and applies test patterns as stimulus data to the integrated circuit based on the functional test commands, receives and analyzes response data from the integrated circuit; and transmits test results including the response data to the virtual test engine for further analyzing. The virtual test engine enables the non-functional test mode of the integrated circuit in case a failure is detected during the functional test, and the integrated circuit tester shifts a serial bit stream out of the integrated circuit in the non-functional test mode, and transmits the serial bit stream as error bit stream to the virtual test engine for further analyzing. The virtual test engine creates and transmits further functional and/or non-functional test commands to the integrated circuit tester based on the test results and/or the error bit stream.

In further embodiments, the integrated circuit tester is configured to shift a serial bit stream in the integrated circuit during the non-functional test mode such that state-holding latches are initialized to pre-defined values when the integrated circuit is operated in the functional test mode afterwards, and the integrated circuit tester is further configured to read these latches by shifting a serial bit stream out of the integrated circuit in the non-functional test mode.

In further embodiments, the integrated circuit tester supplies at least one static test bit pattern to pins of the interface to perform at least one of the following static tests during the non-functional test: Contact test, power test, or automatic test pattern generation test.

In further embodiments, the integrated circuit tester supplies the pre-defined serial bit stream via a service interface being part of the interface to the integrated circuit to test, and wherein the integrated circuit to test outputs the resulting serial bit stream via the service interface to the integrated circuit tester.

In further embodiments, the integrated circuit tester prepares the test vector memory by setting signal level, signal timing and pattern templates to perform the functional test, wherein the integrated circuit tester stores at least two pre-defined test patterns or any combination of composite bit pattern subsets in the test vector memory and selects one of the pre-defined bit patterns in the test vector memory in dependence of a subset of the bits in the received bit stream of the response data.

In another embodiment, a data processing program for execution in a data processing system comprises software code portions for performing a method for testing an integrated circuit when the program is run on the data processing system.

In yet another embodiment, a computer program product stored on a computer-usable medium, comprises computer-readable program means for causing a computer to perform a method for testing an integrated circuit when the program is run on the computer.

In one embodiment, the integrated circuit to test is connected to the virtual test engine of the test environment via the integrated circuit tester, so that the virtual test engine communicates with the integrated circuit tester to perform a functional test of the integrated circuit during a functional test mode and to perform a non-functional test of the integrated circuit during a non-functional test mode. So chip service interface functionality is integrated in the test system comprising the integrated circuit tester creating chip service interface test patterns executed by the test system sequencer. The device under test (DUT) is completely observed and controlled by the test system and no external hardware is connected to the device under test. The test system comprises a chip service interface terminal access mechanism to receive functional and non-functional commands from the virtual test engine, which could be any server system or computer system or network running a corresponding test protocol. The test system with the integrated circuit tester could comprise a network interface to external server systems like the System z of International Business Machines Corporation, Armonk, N.Y. This means, that original System z driver firmware is run at the integrated circuit tester. At the same time full test system debug functionality is available.

All in all, embodiments allow an interference of the test protocol run by the virtual test engine with a scheduler of the integrated circuit tester. The scheduler of the integrated circuit tester is still in charge of providing the test pattern to the device under test. Thus the tester software/pattern generator does track the inner state of the device under test. Higher-level functionality of the test system like shmoo plots and parameter variations can be utilized. Also stopping the test procedure at a specific event like a defined failure and/or hit condition is possible.

Further, embodiments allow identifying an error occurrence and a corresponding error location. Since the control- and/or observation flow is done by the scheduler of the test system error granularity and/or error observation possibilities are as good as those of the test system. Therefore a fast reproducibility of error scenarios is possible. In a minimal approach no additional external hardware is required.

Further embodiments offer better connecting possibilities to standard automatic test equipment software.

The above, as well as additional purposes, features, and advantages are apparent in the detailed written description.