Methods for flip chip stacking

A cavity wafer for flip chip stacking includes an electrostatic (ESC) chuck wafer with a plurality of cavities, and a bonding layer on a surface of the ESC chuck wafer. The bonding layer is configured to receive a through-silicon-via (TSV) interposer with solder bumps. The plurality of cavities are configured to receive the solder bumps at the TSV interposer. The bonding layer is configured to receive an electrostatic bias for bonding the ESC chuck wafer to the TSV interposer with the solder bumps.

TECHNICAL FIELD

An embodiment described herein relates generally to flip chip stacking, and in particular to methods for stacking a flip chip that includes a through-silicon-via (TSV) interposer, an integrated circuit (IC) die, and an organic substrate.

BACKGROUND

Conventional approaches for performing flip chip stacking involve placing a through-silicon-via (TSV) interposer on an organic substrate and subsequently stacking an integrated circuit on the TSV interposer to form a flip chip. Such conventional methods for flip chip stacking are characterized by the particular bonding methods and process parameters involved. Assembly yield for flip chip stacking is significantly influenced by TSV interposer warpage that occurs during conventional flip chip stacking. Conventional flip chip stacking approaches lead to significant amounts of TSV interposer warpage that ultimately affects IC performance and assembly yield.

One approach for mitigating the effects of TSV interposer warpage may be thermo-compression bonding of IC dies to TSV interposers. However, thermo-compression bonding may lead to several side effects such as flux residue and uneven heat profiles, which in turn may result in poor soldering performance.

SUMMARY

In accordance with some embodiments, a method for flip chip stacking includes forming a cavity wafer, wherein the cavity wafer comprises an electrostatic (ESC) chuck wafer, a plurality of cavities within the ESC chuck wafer, and a bonding layer on a surface of the ESC chuck wafer, placing a through-silicon-via (TSV) interposer with solder bumps coupled to a surface of the TSV interposer on the cavity wafer, such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated on the bonding layer, applying an electrostatic bias to the bonding layer to bond the TSV interposer to the cavity wafer, placing an integrated circuit (IC) die on another surface of the TSV interposer, such that the IC die, the TSV interposer, and the solder bumps form a stacked interposer unit, and removing the stacked interposer unit from the cavity wafer.

In one or more embodiments, the method further includes bonding the solder bumps at the stacked interposer unit to an organic substrate such that the stacked interposer unit and the organic substrate form a flip chip.

In one or more embodiments, the organic substrate comprises underlying circuitry.

In one or more embodiments, the act of bonding the solder bumps at the stacked interposer unit to the organic substrate comprises performing reflow joining.

In one or more embodiments, the bonding layer comprises an electrostatic carrier layer.

In one or more embodiments, the act of forming the cavity wafer comprises forming the electrostatic carrier layer on the ESC chuck wafer, patterning photoresist on the electrostatic carrier layer, performing a reactive ion dry etch of the ESC chuck wafer or the electrostatic carrier layer with the patterned photoresist, and removing the photoresist.

In one or more embodiments, the bonding layer further comprises a dielectric layer, the electrostatic carrier layer situated between the dielectric layer and the surface of the ESC chuck wafer.

In one or more embodiments, the act of forming the cavity wafer comprises forming the electrostatic carrier layer on the ESC chuck wafer, patterning photoresist on the electrostatic carrier layer, performing a reactive ion dry etch of the ESC chuck wafer or the electrostatic carrier layer with the patterned photoresist, removing the photoresist, and forming the dielectric layer on the electrostatic carrier layer.

In one or more embodiments, the method further includes performing reflow joining to attach the IC die to the other surface of the TSV interposer.

In one or more embodiments, the method further includes performing underfilling after the reflow joining is performed.

In one or more embodiments, the act of removing the stacked interposer unit from the cavity wafer comprises removing the electrostatic bias applied to the bonding layer.

In one or more embodiments, the method further includes melting IC solder bumps associated with the IC die.

In one or more embodiments, the method further includes placing another integrated circuit (IC) die on the TSV interposer.

In other embodiments, a cavity wafer for flip chip stacking includes an electrostatic (ESC) chuck wafer with a plurality of cavities, and a bonding layer on a surface of the ESC chuck wafer, wherein the bonding layer is configured to receive a through-silicon-via (TSV) interposer with solder bumps, and the plurality of cavities are configured to receive the solder bumps at the TSV interposer, and wherein the bonding layer is configured to receive an electrostatic bias for bonding the ESC chuck wafer to the TSV interposer with the solder bumps.

In one or more embodiments, the bonding layer comprises an electrostatic carrier layer.

In one or more embodiments, the bonding layer further comprises a dielectric layer, the electrostatic carrier layer situated between the dielectric layer and the surface of the ESC chuck wafer.

In one or more embodiments, the TSV interposer with the solder bumps is removable from the cavity wafer in response to a removal of the electrostatic bias applied to the bonding layer.

In one or more embodiments, the cavity wafer is reusable for performing multiple instances of flip chip stacking.

In one or more embodiments, the cavity wafer is compatible with any thermal process.

Other and further aspects and features will be evident from reading the following detailed description of the embodiments

DETAILED DESCRIPTION

Various embodiments are described hereinafter with reference to the figures. It should be noted that the figures are not drawn to scale and that the elements of similar structures or functions are represented by like reference numerals throughout the figures. It should be noted that the figures are only intended to facilitate the description of the embodiments. They are not intended as an exhaustive description of the invention or as a limitation on the scope of the claimed invention. In addition, an illustrated embodiment need not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular embodiment is not necessarily limited to that embodiment and can be practiced in any other embodiments, even if not so illustrated, or if not explicitly described. Also, reference throughout this specification to “some embodiments” or “other embodiments” means that a particular feature, structure, material, or characteristic described in connection with the embodiments is included in at least one embodiment. Thus, the appearances of the phrase “in some embodiments” or “in other embodiments” in various places throughout this specification are not necessarily referring to the same embodiment or embodiments.

FIGS. 1-1to1-5are cross-sectional views illustrating an approach for flip chip stacking. Initially an organic substrate101is formed as illustrated inFIG. 1-1. The organic substrate101may include underlying circuitry and various external pads (not shown) for forming connections to the underlying circuitry.

A through-silicon-via (TSV) interposer103may then be placed on the organic substrate101as illustrated inFIG. 1-2. The TSV interposer includes a plurality of vias105that extend from a top surface of the TSV interposer103to a bottom surface of the TSV interposer103to allow for connections to be made between the top surface and bottom surface. The bottom surface of the TSV interposer103is coupled to corresponding solder bumps107. The solder bumps107are coupled to the vias105of the TSV interposer103to allow for connections to be made to the vias105. The solder bumps107may correspond to external pads (not shown) of the organic substrate101, such that connections may be formed to the underlying circuitry of the organic substrate101through the TSV interposer103.

FIG. 1-3illustrates the TSV interposer103after it has been placed on the organic substrate101. In order to place the TSV interposer103on the organic substrate and form connections between vias105of the TSV interposer and external pads (not shown) of the organic substrate101, a process may be used to melt the solder bumps107in order to form connections between the TSV interposer103and the organic substrate101.

A plurality of integrated circuit dies109may then be placed on the top surface of the TSV interposer109to form a flip chip as illustrated inFIG. 1-4. The integrated circuit dies109may include IC solder bumps111coupled to a bottom surface to form connections between the underlying circuitry of the integrated circuit dies109and the vias105of the TSV interposer103.

FIG. 1-5illustrates the flip chip after the integrated circuit dies109have been placed on the top surface of the TSV interposer103. In order to place the integrated circuit dies109on the organic substrate101and form connections between vias105of the TSV interposer and the IC dies109, a process may be used to melt the solder bumps or copper pillar bumps111in order to form connections between the TSV interposer103and the IC dies109.

Because of the lack of mechanical support provided by the organic substrate101during the process of placing the integrated circuit dies109on the TSV interposer103, the TSV interposer103suffers from warpage as illustrated inFIG. 1-5. The amount of TSV interposer103warpage affects IC performance, with small amounts of warpage leading to some degradation of IC performance and large amounts of warpage ultimately leading to completely ineffective IC performance. This in turn affects assembly yield, as flip chips that suffer from severe TSV interposer warpage will be discarded and not used.

FIG. 2is a flow diagram illustrating a method for stacking a flip chip according to some embodiments. The method ofFIG. 2eliminates the warpage issue associated with the previously described flip chip stacking approach to accomplish high assembly yield.

Initially a cavity wafer comprising a plurality of cavities within an electrostatic (ESC) chuck wafer and a bonding layer on a surface of the ESC chuck wafer is formed as described at201. The cavity wafer may be formed by first forming an electrostatic carrier layer on an ESC chuck wafer. The electrostatic carrier layer may be deposited on a surface of the ESC chuck wafer using any known deposition techniques. The electrostatic carrier layer may then be coated with photo-resist which is patterned to define the plurality of cavities. A reactive ion dry etch of the ESC chuck wafer and the electrostatic carrier layer may then be performed to form the plurality of cavities. Optionally, a dielectric layer may be formed over the electrostatic carrier layer and the plurality of cavities.

In embodiments where the cavity wafer comprises only the electrostatic carrier layer, the ESC carrier layer will be referred to as the bonding layer. In embodiments where the cavity wafer comprises both the electrostatic carrier layer and the dielectric layer, the combination of the ESC carrier layer and the dielectric layer will be referred to as the bonding layer.

A TSV interposer with solder bumps coupled to a surface of the TSV interposer is placed on the cavity wafer as described at203. The TSV interposer includes a plurality of vias. The vias extend from a top surface of the TSV interposer to a bottom surface of the TSV interposer to allow for connections to be made between the top surface and bottom surface. The bottom surface of the TSV interposer is coupled to corresponding solder bumps to allow for connections to be made to the vias.

The TSV interposer with solder bumps is placed on the cavity wafer such that the solder bumps are situated in the plurality of cavities and the TSV interposer is situated on the bonding layer.

An electrostatic bias is then applied to the bonding layer to bond the TSV interposer with solder bumps to the cavity wafer as described at205. In embodiments where the bonding layer comprises both the electrostatic carrier layer and the dielectric layer, the electrostatic bias may be applied to the electrostatic carrier layer. In embodiments where the bonding layer comprises only the electrostatic carrier layer, the electrostatic bias may be applied to the electrostatic carrier layer.

The electrostatic bias causes the electrostatic carrier layer to generate an electrical force which causes the TSV interposer to become bonded to the TSV interposer. By applying the electrostatic bias, the TSV interposer may be mechanically stabilized such that it is immune from warpage during subsequent flip chip stacking.

An integrated circuit (IC) die is then placed on another surface of the TSV interposer to form a stacked interposer unit as described at207. The integrated circuit (IC), TSV interposer, and solder bumps form the stacked interposer unit. In some embodiments, underfilling may be performed after placing the IC die on the other surface of the TSV, such that the IC, TSV interposer, solder bumps, and underfilling together form the stacked interposer unit.

In some embodiments, a process may be used to melt IC solder bumps coupled to the IC dies in order to form connections between the TSV interposer and the IC dies (e.g., reflow joining). In some embodiments, a single IC die may be placed on the other surface of the TSV interposer. In other embodiments, more than one IC die may be placed on the surface of the TSV interposer. This method for flip chip stacking allows flexibility in the configuration (e.g., number of IC dies) of the stacked interposer unit.

Because the TSV interposer and solder bumps are mechanically stabilized by the plurality of cavities and the electrical force generated by applying an electrostatic bias to the bonding layer, placing the integrated circuit die on the surface of the TSV interposer to form a stacked interposer unit will not cause warpage to occur to the TSV interposer.

The stacked interposer unit (e.g., integrated circuit, TSV interposer, and solder bumps) is then removed from the cavity wafer as described at209. The electrical bias being applied to the bonding layer of the cavity wafer may be turned off, thereby causing the electrical force that causes the TSV interposer to become bonded to the TSV interposer to be dissipated. Once the electrical bias has been turned off, the stacked interposer unit may be easily removed from the cavity wafer.

Once the stacked interposer unit has been removed, the solder bumps of the stacked interposer unit may then be bonded to an organic substrate to form a flip chip as described at211. In some embodiments, the stacked interposer unit may be bonded to the organic substrate by a process known as reflow joining. The stacked interposer unit (e.g., IC dies, TSV interposer, and solder bumps) and the organic substrate together form the flip chip. The organic substrate may include underlying circuitry and various external pads for forming connections to its underlying circuitry. The solder bumps may correspond to external pads of the organic substrate, such that connections may be formed from the IC dies to the underlying circuitry of the organic substrate through the TSV interposer.

By introducing a cavity wafer with a plurality of cavities and a bonding layer that generates an electrical force in response to an electrical bias for bonding a TSV interposer with solder bumps to the cavity wafer during the process of placing IC dies on the TSV interposer, the TSV interposer may be shielded from warpage, thereby improving IC die performance and assembly yield in comparison to conventional flip chip stacking approaches. Moreover, utilizing an electrical force to provide mechanical stabilization eliminates the need for using polymeric materials for mechanical stabilization and also eliminates the subsequent costly cleaning process of using polymeric materials. Additionally, the cavity wafer is reusable and fully compatible with any thermal processes such as chip bonding, reflow joining, and underfilling.

FIGS. 3-1to3-12are cross-sectional views illustrating a method for flip chip stacking according to some embodiments. Initially an electrostatic (ESC) chuck wafer301is provided as illustrated inFIG. 3-1. The ESC chuck wafer301is used to form a cavity wafer which will be used to provide mechanical stabilization to a TSV interposer with solder bumps during the process of placing IC dies on the TSV interposer, which will be described in further detail below.

An electrostatic carrier layer303may then be deposited on the ESC chuck wafer301as illustrated inFIG. 3-2. The electrostatic carrier layer303may be deposited using any known deposition technique. The electrostatic carrier layer303is configured to generate an electrical force when an electrostatic bias is applied to it. The electrical force will provide mechanical stabilization to a TSV interposer with solder bumps during the process of placing IC dies on the TSV interposer.

The ESC chuck wafer301with the electrostatic carrier layer303may then be coated with photo-resist305which is patterned to define a plurality of cavities as illustrated inFIG. 3-3. In some embodiments, the photo-resist may comprise positive resist material that becomes soluble when exposed to light. In other embodiments, the photo-resist may comprise negative resist material that becomes insoluble when exposed to light. One ordinarily skilled in the art will recognize that many different techniques and materials may be used to pattern a photo-resist layer which defines the plurality of cavities.

A reactive ion dry etch of the ESC chuck wafer301or the electrostatic carrier layer303may then be performed to form the plurality of cavities307as illustrated inFIG. 3-4. One ordinarily skilled in the art will recognize that other techniques may be used to form the plurality of cavities307.

The photo-resist305may then be removed and a dielectric layer309may optionally be formed over the electrostatic carrier layer303and the plurality of cavities307as illustrated inFIG. 3-5. The combination of the electrostatic carrier layer303and the dielectric layer309will be referred to as the bonding layer. The combination of the ESC chuck wafer301, the plurality of cavities307, and the bonding layer303,309form the cavity wafer311.

A TSV interposer103with solder bumps107coupled to a bottom surface of the TSV interposer103is then placed on the cavity wafer as illustrated inFIG. 3-6. It should be noted that within the context of the subject application, when a first item (e.g., the TSV interposer) is described as being placed “on” a second item (e.g., the cavity wafer), the first item may contact the second item) in which case, the first item may be considered as directly “on” the second item), or the first item may not contact the second item (such as in the situation in which there is a third item between the first and second items, in which case the first item may be considered as indirectly “on” the second item).

The TSV interposer103includes a plurality of vias105that extend from a top surface of the TSV interposer103to a bottom surface of the TSV interposer103to allow for connections to be made between the top surface and bottom surface. The bottom surface of the TSV interposer103is couple to corresponding solder bumps107. The solder bumps107are coupled to the vias105of the TSV interposer103to allow for connections to be made to the vias105. The solder bumps107may correspond to external pads of an external component (e.g., organic substrate), such that connections may be formed to the underlying circuitry of the external component through the TSV interposer103.

The TSV interposer103and solder bumps107are placed on the cavity wafer311such that the solder bumps107are situated in the plurality of cavities307and the TSV interposer103is situated on the bonding layer (e.g., electrostatic carrier layer303and dielectric layer309).

An electrostatic bias is then applied to the bonding layer (e.g., electrostatic carrier layer303and dielectric layer309) to bond the TSV interposer103with solder bumps107to the cavity wafer311as illustrated inFIG. 3-7. The electrostatic bias may be applied to the electrostatic carrier layer303of the bonding layer (e.g., electrostatic carrier layer303and dielectric layer309).

The electrostatic bias causes the electrostatic carrier layer303to generate an electrical force which causes the TSV interposer103to become bonded to the cavity wafer311. By applying the electrostatic bias, the TSV interposer103may be mechanically stabilized such that it is immune from warpage during subsequent flip chip stacking.

One or more IC dies109may then be placed on the TSV interposer103as illustrated inFIG. 3-8. The integrated circuit dies109may include IC solder bumps111coupled to a bottom surface to form connections between the underlying circuitry of the integrated circuit dies109and the vias105of the TSV interposer103. In some embodiments, the IC solder bumps111may be copper pillar bumps.

FIG. 3-9illustrates the integrated circuit dies109after they have been placed on the top surface of the TSV interposer103. The integrated circuit dies109, TSV interposer103, and solder bumps107together form a stacked interposer unit113. In some embodiments, underfilling may be performed after placing the IC dies109on the other surface of the TSV, such that the IC dies109, TSV interposer103, solder bumps107, and underfilling (not shown) together form the stacked interposer unit113. In order to place the integrated circuit dies109on the organic substrate101and form connections between vias105of the TSV interposer and the IC dies109, a process known as reflow joining may be used to melt the IC solder bumps11to form connections between the TSV interposer103and the IC dies109.

The stacked interposer unit113may then be removed from the cavity wafer311as illustrated inFIG. 3-10. The electrical bias being applied to the electrostatic carrier layer303of the cavity wafer311may be turned off, thereby causing the electrical force that causes the TSV interposer113to become bonded to the cavity wafer311to be dissipated. Once the electrical bias has been turned off, the stacked interposer113unit may be easily removed from the cavity wafer311.

The stacked interposer unit113may then be bonded to an organic substrate101, as illustrated inFIG. 3-11. As discussed above, the organic substrate101may include underlying circuitry and various external pads (not shown) for forming connections to the underlying circuitry. The stacked interposer unit113may be placed such that solder bumps107correspond to external pads (not shown) of the organic substrate101so that connections may be formed from the IC dies to the underlying circuitry of the organic substrate101through the TSV interposer103.

FIG. 3-12illustrates the stacked interposer unit113after it has been bonded to the organic substrate101. The stacked interposer unit113(e.g., IC dies109, TSV interposer103, and solder bumps107) and the organic substrate101together form the flip chip300. In some embodiments, a process known as reflow joining may be used to melt solder bumps107coupled to the bottom surface of the TSV interposer103in order to form connections between the TSV interposer103and the organic substrate101.

As discussed above, by introducing a cavity wafer with a plurality of cavities and a bonding layer that generates an electrical force for bonding a TSV interposer with solder bumps to the cavity wafer when an electrical bias is applied during the process of placing IC dies on the TSV interposer, the TSV interposer may be shielded from warpage, thereby improving IC die performance and assembly yield in comparison to conventional flip chip stacking approaches. Moreover, utilizing an electrical force to provide mechanical stabilization eliminates the need for using polymeric materials for mechanical stabilization and also eliminates the subsequent costly cleaning process of using polymeric materials. Additionally, the cavity wafer is reusable and fully compatible with any thermal processes such as chip bonding, reflow joining, and underfilling.