Imaging sensor structure and method

The present disclosure provides an embodiment of a method for fabricating a three dimensional (3D) image sensor structure. The method includes providing to an image sensor substrate having image sensors formed therein and a first interconnect structure formed thereon, and a logic substrate having a logic circuit formed therein and a second interconnect structure formed thereon; bonding the logic substrate to the image sensor substrate in a configuration that the first interconnect structure and second interconnect structure are sandwiched between the logic substrate and the image sensor substrate; and forming a conductive feature extending from the logic substrate to the first interconnect structure, thereby electrically coupling the logic circuit to the image sensors.

BACKGROUND

As one application, imaging sensors are incorporated in an integrated circuit. The existing imaging sensor has logic and pixel array on the same Si wafer and another wafer is a carrier only. Various issues may present in the existing imaging sensor structure. In one example, process tuning to image sensors impacts logic circuit area. In another example, small pixel layout suffers low quantum efficiency (QE) and full well capacity (FWC) due to devices occupancy. In yet another example, image signal processor (ISP) seizes a larger layout area, leading to low gross die count per unit area.

Therefore, what is needed is a structure for imaging sensor and method making the same to address the above issues.

DETAILED DESCRIPTION

The present disclosure provides an imaging sensor structure and the method making the same with improved pixel performance, increased gross die count and enhanced image signal processor (ISP) function.

FIG. 1illustrates a top view of an image sensor structure10andFIG. 2illustrates a schematic view of the image sensor structure10. The image sensor structure10has a three dimensional (3D) structure that includes a first integrated circuit (IC) chip12and a second IC chip14. The IC substrate14is stacked on, mechanically bonded to, and electrically coupled with the first IC chip12. The first IC chip12is designed and configured to form various image sensors and the second IC chip14is designed and configured to form various driving circuit and logic devices to the image sensors. The first and second IC chips are also referred to as image sensor chip and logic circuit chip, respectively.

The first IC chip12includes a first substrate. In one embodiment, the first substrate includes silicon. The first substrate may additionally or alternatively include some other suitable elementary semiconductor, such as diamond or germanium; a suitable compound semiconductor, such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor, such as silicon germanium carbide, gallium arsenic phosphide, or gallium indium phosphide.

The first IC chip12includes various doped regions, and other features configured to form image sensors that are sensitive to photon or other image radiation. In one embodiment, the image sensors include photodiodes, such as complementary metal-oxide-semiconductor field-effect transistor (CMOSFET)-based photodiodes or other photosensitive devices. In one embodiment, those image sensors are further configured to form an image sensor array for various applications including imaging. In one example, the image sensors are backside illuminated CMOSFET-based image sensors, where the illumination beam is received from the backside of the image sensors. Accordingly, the first IC chip12is also referred to as image sensor chip12. The first IC chip12includes conductive material features and dielectric material features disposed on the first substrate and configured for coupling and isolating various microelectronic components, respectively. As one example, the first IC chip12includes one or more material layers, such as interleave dielectric material layers (ILDs) and metal layers that are embedded in the ILDs and are patterned to form metal lines, vias and contacts. In another embodiment, the first IC chip12may further include other microelectronic devices.

The second IC chip14includes a second substrate. In the present embodiment, the second substrate is substantially similar to the first substrate. In one example, the second substrate includes silicon. In other examples, the second substrate alternatively or additionally includes some other suitable elementary semiconductor, a suitable compound semiconductor, or a suitable alloy semiconductor.

The second IC chip14includes various microelectronic devices, such as CMOSFET-based logic devices and circuits. Particularly, the second IC chip14includes various microelectronic devices configured to form driving circuits/devices for the image sensors. In one embodiment, the driving circuits to the image sensors include address lines and data lines to the image sensor array. The driving circuits to the image sensors further include driving devices reset (RST) device, source follower (SF), and row selector (RS). In the present embodiment, those driving devices are configured in group to be coupled with one pixel of the image sensors or a subset of the pixels. Various circuits and devices formed in the second IC chip14are collectively referred to as logic devices in the later description. In one example, the second IC chip is an application-specific integrated circuit (ASIC) chip.

The first IC chip12and the second IC chip14are mechanically bonded together through a suitable bonding mechanism, such as fusion bonding, eutectic bonding or other suitable bonding technique. The first IC chip12and the second IC chip14are electrically coupled together through backside deep contact (BDCT) features. The BDCT features are formed in the deep trenches in the interconnect structure of the first IC chip12, are further extended to the interconnect structure of the second IC chip14, are configured with other conductive features to electrically couple together the driving devices in the second IC chip14and the image sensors in the first IC chip12. The BDCT features will be further described later in terms of the formation and configuration. Since the image sensors and the corresponding driving circuits/devices are distributed into two IC chips (12and14in the present embodiment), there are more freedom and flexibility to reconfigure and tune the image sensors and the driving circuits/devices for improved performance and efficiency. For example, the image sensors and the logic devices are individually tuned for their performance during the respective fabrication operations before bonding and coupling together. In the present embodiment, the 3D image sensor structure10is formed by a procedure where the first IC chip12and the second IC chip14are fabricated and bonded in wafer level and thereafter are diced to separate a plurality of the 3D image sensor structures10. In an alternative embodiment, the coupling between the first and second IC chips is achieved by a through-semiconductor via (or through-silicon via, or TSV) feature, which is different from the BDCT feature in terms of configuration and formation.

FIG. 3illustrates a schematic view of the 3D image sensor structure10constructed according to aspects of the present disclosure in another embodiment. The 3D image sensor structure10includes the first IC chip12and the second IC chip14mechanically bonded together and electrically coupled with each other. The first IC chip12is designed and configured to form various image sensors and the second IC chip14is designed and configured to form various logic circuits that include driving circuit/devices to the image sensors.

The first IC chip12includes a first substrate16. In one embodiment, the first substrate includes silicon. The first substrate may additionally or alternatively include some other suitable elementary semiconductor; a suitable compound semiconductor; or a suitable alloy semiconductor.

The first IC chip12includes various doped regions, and other features configured to form image sensors18that are sensitive to photon or other image radiation. In one embodiment, the image sensors18include photodiodes, such as CMOSFET-based photodiodes or other photosensitive devices. In one example, the image sensors are backside illuminated CMOSFET-based image sensors. In the present embodiment, the first IC chip12also includes other features, such as transfer gates (“TX” inFIG. 3) formed on the photodiodes18, respectively. The first IC chip12includes an interconnect structure (also referred to as a first interconnect structure) formed on the first substrate16. The first interconnect structure includes metal lines, vias and contacts to provide horizontal and vertical electrical routing. The interconnect structure may include a plurality of metal layers, such as a first metal layer a second metal layer,. . . and so on. The first interconnect structure includes various conductive features configured to an electrical routing20to provide electrical routing to the transfer gates.

The second IC chip14includes a second substrate22. In the present embodiment, the second substrate22is substantially similar to the first substrate16. For examples, the second substrate includes silicon.

The second IC chip14includes various microelectronic devices, such as CMOSFET-based logic devices formed on the second substrate22. Particularly, the second IC chip14includes various microelectronic devices configured to drive the image sensors18. In one embodiment, the driving devices to the image sensors include reset (RST) device, source follower (SF), and row selector (RS). In the present embodiment, those driving devices are configured in pixel levels such that a group of those devices are coupled with one pixel of the image sensors18or a subset of pixels in the image sensor array. Accordingly, the coupling between the driving devices to the image sensors are pixel-based and the conductive features to connect both need to be properly designed and configured to provide such capability with chip area efficiency.

The second IC chip14also includes an interconnect structure (also referred to as a second interconnect structure) formed on the second substrate22. The second interconnect structure includes a plurality of metal layers, such as a first metal layer, a second metal layer, . . . , and the top metal layer. One of the metal lines in the top metal layer is illustrated inFIG. 3.

The first IC chip12and the second IC chip14are mechanically bonded together through a suitable bonding mechanism. The first IC chip12and the second IC chip14are electrically coupled together through one or more backside deep contact (“BDCT” inFIG. 3) feature. The BDCT feature is formed in the deep trenches in the interconnect structure of the first IC chip12, further extended to the interconnect structure of the second IC chip14, and configured with other conductive features to electrically couple together the driving devices in the second IC chip14and the image sensors18in the first IC chip12.

The BDCT feature has a small dimension in a top view toward the first or second substrate since it is pixel-based with small footprint. In one example, the dimension of the BDCT feature is less than 1 micron. Particularly, the BDCT feature is extended from the contact feature24of the first interconnect structure in the first substrate16to a conductive feature (referred to as “BSSI” feature inFIG. 3) formed in the second substrate22. The BSSI feature is embedded in the second substrate22and formed by backside silicon (BSSI) etch. The BDCT feature is extended through a first metal line in the first metal layer and a second metal line in the top metal layer of the second interconnect structure. In the present embodiment, the BDCT has different dimensions in different portions. The BDCT includes a first portion between the BSSI feature and the second metal line, and a second portion between the second metal line and the first metal line. The first portion has a first dimension (first width) and the second portion has a second dimension (second width) less than the first dimension, as illustrated inFIG. 3. This structure can be achieved by a procedure including multiple etchings.

As noted above, the image sensors and the corresponding driving devices are respectively formed on two IC chips, with more freedom and flexibility to reconfigure and tune the image sensors and the driving devices for improved performance and efficiency. One such example of the 3D image sensor structure10is illustrated inFIG. 4in a schematically top view. The 3D image sensor structure10includes photodiodes (“PD”) and transfer gates (“TX”) formed on the first IC chip. The first IC chip is mechanically bonded and is further electrically coupled with the second IC chip through the BDCT feature and BSSI feature. The BDCT and BSSI features are formed by a 3D procedure on the backside of the second IC chip, which will be further described later. The signal lines20and ground line30of the photodiodes are configured on the pixel edges and are electrically coupled to the logic circuit/devices through BDCT feature in the 3D connection.

FIG. 5is a flowchart of a method40making the 3D image sensor structure10, andFIGS. 6-12illustrates the 3D image sensor structure10at various fabrication stages constructed according one or more embodiment. As one embodiment, the present method40is implemented in wafer-level with more efficiency and multiple 3D image sensor chips are separated by dicing after the bonding and the formation of the electrical coupling features.

Referring toFIGS. 5-7, the method40begins at operation42by bonding the first IC structure (image sensor wafer)12and the second IC structure (logic circuit wafer)14together resulting in a bonded 3D image sensor structure10. The first IC structure12, as described above, includes a plurality of photosensitive devices, such as photodiodes, formed thereon. The image sensor chip12includes a semiconductor substrate16, such as silicon wafer. The image sensor structure12further includes image sensors formed in the semiconductor substrate16. The image sensor structure12also includes a first interconnect structure62having various metal lines, vias and contacts formed in various interlayer dielectric (ILD) material layers. A metal line70in the first metal layer of the first interconnect structure is illustrated inFIG. 7.

In the present embodiment, the second IC structure14is an ASIC wafer. Particularly, the second IC structure14includes a semiconductor substrate22, such as a silicon wafer, and a logic circuit of various logic devices formed on the semiconductor substrate22. The logic devices include CMOSFET-based devices for various logic functions and driving devices, such as RST, SF and RF, to be coupled to the image sensors.

The second IC structure14includes a second interconnect structure64formed on the semiconductor substrate22. The interconnect structure64includes various metal lines (in respective metal layers), vias and contacts configured to provide electrical routing and coupled with the logic devices. The formation of the interconnect structure64(or the interconnect structure62) includes a suitable procedure, such as damascene process for copper connection. In this method, the interlayer dielectric material layer is deposited, and patterned to form trenches using lithography process and etch. The metal, such as copper, is deposited to fill in the trenches and is further polished to remove the excessive and planarize the top surface by chemical mechanical polishing (CMP). The metal deposited to the trenches may include barrier layer (such as titanium nitride or tantalum nitride) by physical vapor deposition (PVD), copper seed layer by PVD and bulk copper by plating. InFIG. 7, metal features66in the top metal layer are illustrated.

The bonding process is designed to bond the two IC structure in a configuration such that the two interconnect structures are sandwiched between the two semiconductor substrates. Particularly, in the 3D image sensor structure, the first interconnect structure62and the second interconnect structure64are sandwiched between the two substrates16and22. The bonding process may implement a suitable bonding mechanism, such as fusion bonding, eutectic bonding, or other bonding technique.

The method40may include an operation44by thinning down the second substrate22such that the thickness of the semiconductor substrate22(silicon wafer in the present case) is reduced. The thinning down process may include a suitable polishing or grinding process, such as a chemical mechanical polishing (CMP).

Referring toFIGS. 5 and 8, the method40proceeds to operation46by patterning the second substrate22to form one (or more) opening72that defines the region for the BDCT feature. The through opening72of the semiconductor substrate22exposes the second interconnect structure64within the opening. The patterning process includes a lithography process and etching. In one example, the lithography process includes coating photoresist layer on the semiconductor substrate22; performing a lithography exposure to the photoresist layer; and developing the exposed photoresist layer to form a patterned photoresist layer. The etching is designed to selectively etch the semiconductor substrate22, (selectively etch silicon in the present embodiment). In another embodiment of patterning the second substrate22, a hard mask may be employed. For example, a hard mask layer is deposited on the semiconductor substrate22, a patterned photoresist layer is formed by a lithography process, an etching process is applied to the hard mask layer using the patterned photoresist layer as an etch mask, and thereafter, another etching process is applied to the second substrate22using the patterned hard mask layer as an etch mask. In yet another example, the lithography process may include other suitable technologies, such as ultraviolet (UV) lithography, deep UV (DUV) lithography, extreme UV (EUV) lithography, or electron-beam lithography. In yet another example, the lithography process may be replaced by other suitable technologies, such as molecular imprint or maskless lithography.

Referring toFIGS. 5 and 9, the method40proceeds to operation48by forming one or more deep interconnect trench74for backend deep contact. The deep interconnect trench74vertically extends from the second IC structure14to the first IC structure12. Especially, the deep interconnect trench74extends from the second interconnect structure64of the second IC structure14to the first interconnect structure62of the first IC structure12. The deep interconnect trench74includes a first trench portion and a second trench portion with different dimensions. The first trench portion vertically spans between the metal line70in the first metal layer of the first interconnect structure and the metal line66in the top metal layer of the second interconnect structure. The second trench portion is in the second IC structure and vertically spans from the metal line66in the top metal layer of the second interconnect structure to the second substrate22. In the present example, the first trench portion has a first horizontal dimension (first trench width) W1and the second trench portion has a second horizontal dimension (second trench width) W2greater than W1, thereby providing more room for the image sensors in the first IC structure12.

The deep interconnect trench74is aligned with the metal lines66and70, and therefore electrically couple the metal lines66and70together by the corresponding BDCT feature to be formed, thereby providing the electrical interconnection between the first and second IC structures, particularly providing the electrical interconnection between the image sensors in the first IC structure12and the logic devices in the second IC structure14.

The formation of the deep interconnect trench74includes various etching processes. Since the second interconnect structure includes various metal features formed in one or more ILD material layers. The ILD material layers includes a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, polyimide, spin-on glass (SOG), fluoride-doped silicate glass (FSG), carbon doped silicon oxide, and low k dielectric material. The etching processes are designed to selectively etch the ILD material layers.

In one embodiment, the formation of the deep interconnect trench is similar to the dual damascene process, such as via-first dual damascene process, trench-first dual damascene process or other suitable dual damascene process. In furtherance of the embodiment, the metal lines66and70may serve as etch stop layers in the etch processes to form the first and second trench portions, respectively.

The formation of the deep interconnect trench74in a particular example is described below. The first etch process is applied to the ILD layers to form the second trench portion of the deep interconnect trench74through the opening72in the second semiconductor substrate22using the semiconductor substrate22as an etch mask. The opening72may be expanded to a large size during the first etch process. The first etch process is designed with an etchant to selectively remove the dielectric material of the ILD material layers and to stop on the metal line66. A second etch process is applied to the metal line66to open the metal line66within the trench. Thereafter, a processing procedure including lithography process and etch is applied to form the first trench portion. In the processing procedure, a patterned photoresist layer is formed on the semiconductor substrate22and in the second trench portion by a lithography process. The lithography process includes photoresist coating, exposure and developing, and may further include various baking steps, such as soft baking, post exposure baking and hard baking. The patterned photoresist layer includes an opening that defines the region for the first trench portion. A third etching process is applied to etch the ILD dielectric material layer of the second interconnect structure and the ILD dielectric material layer of the first interconnect structure. In one example, the third etching process is similar to the first etching process in terms of the etchant and etches selectivity. In furtherance of the example, the third etching process stops on the metal line70. Other suitable procedure that is able to form the deep interconnect trench74may be implemented. For example, additional etch stop layer may be formed on the metal lines70(or66) to stop the corresponding etch process for forming the first trench portion (or the second trench portion), to enhance the etch control.

Referring toFIGS. 5 and 10, the method40proceeds to operation50by forming the BDCT feature76. In one embodiment, the formation of the BDCT feature76is similar to the formation of metal features by the dual damascene process. In furtherance of the embodiment, the formation of the BDCT feature76includes filling the deep interconnect trench74with one or more conductive material; and performing a CMP process to remove the excessive metal deposited on the second substrate22and planarize the top surface. In various examples, the conductive material includes metal or metal alloy, such as copper, tungsten, metal silicide, aluminum or other suitable conductive material. In another example, the conductive material may include more than one material layers. The conductive material may be deposited by a suitable technique, such as physical vapor deposition (PVD), plating, chemical vapor deposition (CVD). In the present example, the BDCT feature76includes a barrier layer, such as titanium nitride or tantalum nitride deposited by PVD; a copper seed layer formed on the barrier layer by PVD; and bulk copper to fill in the deep interconnect trench by plating.

In the present embodiment, during the formation of the BDCT feature76, the opening72of the second substrate22is also filled with the conductive material, thereby forming another conductive portion in the opening72. The portion of the conductive material in the opening72is collectively labeled by numeral76inFIG. 13(it is also referred to as the BSSI feature inFIG. 3).

Additionally, a passivation layer78is formed on the substrate22and the BDCT feature76. The passivation layer78includes a suitable material for passivation, such as a silicon oxide layer, a silicon nitride or a combination thereof, formed by a suitable method, such CVD.

Referring toFIGS. 5 and 11, the method40may include an operation52by bonding a carrier substrate80(such as another silicon wafer) to the 3D image sensor structure10if it is too thin without enough mechanical strength. In one example, the second substrate22is too thin. The carrier substrate80is boned to the second substrate to the passivation layer80by a suitable bonding mechanism, such as fusion bonding or eutectic bonding.

Referring toFIGS. 5 and 12, the operation52may include a thinning-down process after the bonding of the carrier substrate80. The first substrate16is thinned down from the backside such that the thickness of the first substrate16is substantially reduced. Thereby, the image sensors formed in the first substrate16are able to receive image light more efficiently with reduced energy loss.

The method40may further include other operations to complete the formation of the 3D image sensor structure10. In one example, the method40may include forming various features to enhance the imaging effect of the image sensors, such as forming color filter and micro-lenses on the backside of the first substrate. In another example, the method40may include a dicing process to form a plurality of 3D image sensor chips after the above operations are implemented in wafer level.

The present disclosed 3D image sensor structure and the method making the same are described in various embodiments. In another embodiment, the carrier wafer as the third substrate bonded to the 3D image sensor structure includes other logic circuit for further ISP function enhancement. For example, various logic devices including the driving devices to the image sensors are properly distributed in the logic substrate and the carrier wafer for more configuration freedom and design flexibility to enhance the performance of the 3D image sensor structure. In another embodiment of the disclosed structure and method, the driving devices to the image sensors are relocated on the logic substrate for image sensor performance improvement, such as the enlargement of quantum efficiency (QE) and full well capacity (FWC). In yet another embodiment, the image sensors in the 3D image sensor structure may be replaced by other sensors to employ the advantages of the 3D structure.

FIG. 13illustrates a schematic view of the 3D image sensor structure86constructed according to aspects of the present disclosure in another embodiment. The 3D image sensor structure86includes the first IC chip12and the second IC chip14mechanically bonded together and electrically coupled with each other through a TSV feature (“TSV”). The first IC chip12is designed and configured to form various image sensors and the second IC chip14is designed and configured to form various logic circuits that include driving circuit/devices to the image sensors.

The first IC chip12includes a first substrate16. In one embodiment, the first substrate includes silicon. the first substrate may additionally or alternatively include some other suitable elementary semiconductor; a suitable compound semiconductor; or a suitable alloy semiconductor.

The first IC chip12includes various doped regions, and other features configured to form image sensors18that are sensitive to photon or other image radiation. In one embodiment, the image sensors18include photodiodes, such as CMOSFET-based photodiodes or other photosensitive devices. In one example, the image sensors are backside illuminated CMOSFET-based image sensors. In the present embodiment, the first IC chip12also includes other features, such as transfer gates (“TX”) formed on the photodiodes18, respectively. The first IC chip12includes an interconnect structure (also referred to as a first interconnect structure) formed on the first substrate16. The first interconnect structure includes metal lines, vias and contacts to provide horizontal and vertical electrical routing. The interconnect structure may include a plurality of metal layers, such as a first metal layer, a second metal layer , . . . and so on. Exemplary conductive features24,26and28(such as a metal line in one metal layer or a via between adjacent metal layers or a contact between the substrate and the first metal layer) are illustrated inFIG. 3andFIG. 13. In the present example, the conductive feature24is a contact and the conductive feature26is a metal line in the first metal layer. The contact24and the metal line26are directly connected. The first interconnect structure includes various conductive features configured to an electrical routing20to provide electrical routing to the transfer gates.

The second IC chip14includes a second substrate22. In the present embodiment, the second substrate22is substantially similar to the first substrate16. For examples, the second substrate includes silicon.

The second IC chip14includes various microelectronic devices, such as CMOSFET-based logic devices formed on the second substrate22. Particularly, the second IC chip14includes various microelectronic devices configured to drive the image sensors18. In one embodiment, the driving devices to the image sensors include reset (RST) device, source follower (SF), and row selector (RS). In the present embodiment, those driving devices are configured in pixel levels such that a group of those devices are coupled with one pixel of the image sensors18or a subset of pixels in the image sensor array. Accordingly, the coupling between the driving devices to the image sensors are pixel-based and the conductive features to connect both need to be properly designed and configured to provide such capability with chip area efficiency.

The second IC chip14also includes an interconnect structure (also referred to as a second interconnect structure) formed on the second substrate22. The second interconnect structure includes a plurality of metal layers, such as a first metal layer, a second metal layer, . . . and the top metal.

The first IC chip12and the second IC chip14are mechanically bonded together through a suitable bonding mechanism. The first IC chip12and the second IC chip14are electrically coupled together through one or more TSV feature. The TSV feature is formed in the deep trenches in the first interconnect structure of the first IC chip12and the second interconnect structure of the second IC chip14, and further extended to the second substrate22of the second IC chip14, and configured with other conductive features to electrically couple together the driving devices in the second IC chip14and the image sensors18in the first IC chip12.

The TSV feature has a greater dimension D width at the first or second substrate compared to the BDCT feature. In one example, the dimension of the TSV feature is about 10 micron. In a particular example, the TSV feature is extended from the metal line26of the first interconnect structure in the first substrate16to the second substrate22. In another example, the dimension D of the TSV feature is substantially same from the top portion in the second substrate22to the bottom portion in the first interconnect structure of the first IC chip. The TSV feature connects to the metal line24and is coupled to the image sensors18therethrough. The TSV feature is coupled to the logic circuit in the second IC chip14through various metal features. In one embodiment, various conductive features are formed in the backside of the second substrate22and are connected to the TSV feature. In another embodiment, the conductive features may be formed in one metal layer (for example, the first metal layer in the second interconnect structure). Therefore, the logic devices are coupled with the image sensors18through the TSV feature and those conductive features formed in the second substrate22. The conductive features in the second substrate22may be formed by a procedure that includes lithography patterning, etching, deposition of a barrier layer and metal, and polishing.

As noted above, the image sensors and the corresponding driving devices are respectively formed on two IC chips, with more freedom and flexibility to reconfigure and tune the image sensors and the driving devices for improved performance and efficiency.

FIG. 14is a flowchart of a method88making the 3D image sensor structure86, andFIGS. 15-22illustrates the 3D image sensor structure86at various fabrication stages constructed according one or more embodiment. As one embodiment, the present method88is implemented in wafer-level with more efficiency and multiple 3D image sensor chips are separated by dicing after the bonding and the formation of the electrical coupling features.

Referring toFIGS. 14-16, the method88begins at operation90by bonding the first IC structure (image sensor wafer)12and the second IC structure (logic circuit wafer)14together resulting in a bonded 3D image sensor structure10. The first IC structure12, as described above, includes a plurality of photosensitive devices, such as photodiodes, formed thereon. The image sensor chip12includes a semiconductor substrate16, such as silicon wafer. The image sensor structure12further includes image sensors formed in the semiconductor substrate16. The image sensor structure12also includes a first interconnect structure62having various metal lines, vias and contacts formed in various interlayer dielectric (ILD) material layers. A metal line70of one metal layer in the first interconnect structure is illustrated inFIG. 16.

In the present embodiment, the second IC structure14is an ASIC wafer. Particularly, the second IC structure14includes a semiconductor substrate22, such as a silicon wafer, and a logic circuit of various logic devices formed on the semiconductor substrate22. The logic devices include CMOSFET-based devices for various logic functions and driving devices, such as RST, SF and RF, to be coupled to the image sensors.

The second IC structure14includes a second interconnect structure64formed on the semiconductor substrate22. The interconnect structure64includes various metal lines (in respective metal layers), vias and contacts configured to provide electrical routing and coupled with the logic devices. The formation of the interconnect structure64(or the interconnect structure62) includes a suitable procedure, such as damascene process for copper connection. In this method, the interlayer dielectric material layer is deposited, and patterned to form trenches using lithography process and etch. The metal, such as copper, is deposited to fill in the trenches and is further polished to remove the excessive and planarize the top surface by chemical mechanical polishing (CMP). The metal deposited to the trenches may include barrier layer (such as titanium nitride or tantalum nitride) by physical vapor deposition (PVD), copper seed layer by PVD and bulk copper by plating.

The bonding process is designed to bond the two IC structure in a configuration such that the two interconnect structures are sandwiched between the two semiconductor substrates. Particularly, in the 3D image sensor structure, the first interconnect structure62and the second interconnect structure64are sandwiched between the two substrates16and22. The bonding process may implement a suitable bonding mechanism, such as fusion bonding, eutectic bonding, or other bonding technique.

The method88may include an operation92by thinning down the second substrate22such that the thickness of the semiconductor substrate22(silicon wafer in the present case) is reduced. The thinning down process may include a suitable polishing or grinding process, such as CMP.

Referring toFIGS. 14 and 17, the method88proceeds to operation94by depositing a polishing stop layer110on the backside of the second substrate22. The polishing stop layer110functions to stop the polishing process during the formation of the TSV feature. In the present embodiment, the polishing stop layer110includes silicon carbide or alternatively other suitable material with effective resistance to the polishing process. The polishing stop layer100is formed by a suitable deposition technique, such as chemical vapor deposition (CVD). The thickness of the polishing stop layer110is designed with enough polishing resistance.

Referring toFIGS. 14 and 18, the method88proceeds to operation96by forming one or more TSV trench112. Note the TSV trench refers to a trench and the TSV feature refers to the conductive feature formed in the TSV trench. The TSV trench112vertically extends from the second IC structure14to the first IC structure12. Especially, the TSV trench112extends through the second substrate22and the second interconnect structure64, and extends into the first interconnect structure62of the first IC structure12. The TSV trench112has a width dimension (“D”) in a top view toward the first substrate16. In one example, the width dimension D of the TSV trench110ranges between about 5 micron and 15 micron. In another example, the width dimension d is about 10 micron. The TSV trench112is aligned with the metal line70, and exposes the metal line70.

The formation of the TSV trench112includes a lithography process and one or more etching processes. Since the second interconnect structure includes various metal features formed in one or more ILD material layers. The ILD material layers includes a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, polyimide, spin-on glass (SOG), fluoride-doped silicate glass (FSG), carbon doped silicon oxide, and low k dielectric material. The etching processes are designed to selectively etch the ILD material layers and silicon at respective etching steps when more than one etch step is implemented.

The formation of the TSV trench112is described below according to one embodiment. A lithography process is performed to form a patterned resist layer. An etching process is applied to etch the polishing stop layer110, the silicon material of the second substrate22, and the dielectric materials in the first and second interconnect structures. In one example, the etching process may include one etching step to etch through all material layers, or alternatively multiple etch steps tuned with to etch respective materials. In another embodiment, a hard mask layer is formed on the backside of the second substrate22and is patterned to form an opening that defines the region for the TSV trench112. Thereafter, various material layers are patterned by one or more etching steps using the patterned hard mask layer as an etch mask. In yet another embodiment, the polishing stop layer110is first patterned to form an opening that defines the region for the through silicon via112by lithography process and etching. Thereafter, various material layers are patterned by one or more etching steps using the patterned polishing stop layer110as an etch mask. The etching process to form the TSV trench112stops on the metal line70by a mechanism, such as etching selectivity or control of the etching time.

Referring to FIGS.14and19-21, the method88proceeds to operation98by forming one or more TSV feature. The TSV feature is a conductive feature formed in the TSV trench112, providing electrical routing between the first and second IC structures12and14.

In one embodiment, a liner layer114is formed in the TSV trench112as illustrated inFIG. 19, particularly on the sidewalls of the TSV trench112. The liner layer114includes a dielectric material to provide at least one of functions that include isolation, preventing diffusion and enhance adhesion. In one embodiment, the liner layer114includes silicon oxide formed by CVD or other suitable deposition technique.

A conductive material layer116is filled in the TSV trench112on the liner layer114, as illustrated inFIG. 20. The conductive material layer116may include metal (such as copper, aluminum or tungsten), metal alloy, or other suitable conductive material. The conductive material layer includes one or more conductive materials. In one embodiment, the conductive material layer116include copper formed by a procedure that includes a physical vapor deposition (PVD) process to form a copper seed layer and a plating process to form bulk copper on the copper seed layer. In furtherance of the embodiment, before the PVD deposition of the copper seed layer, a sputtering process is applied to the image sensor structure86to remove the process liner layer114formed on the bottom of the TSV trench such that the metal line70is exposed within the TSV trench.

Thereafter, a CMP process is applied to the backside of the second substrate22remove the excessive conductive material and planarize the backside surface of the second substrate22, thereby forming the TSV feature118as illustrated inFIG. 21. The CMP process is designed and tuned to stop on the polishing stop layer110.

The method88may include other operations to form other conductive features that enable the electrical connection of the TSV feature118to the logic devices on the second IC structure14. Accordingly, the image sensors in the first IC structure12and the logic devices in the second IC structure14are electrically coupled through the TSV feature118. In one embodiment, conductive features (also referred to as metal traces) are formed on the backside of the IC structure12to be coupled with the second interconnect structure, by a suitable procedure, such as a damascene process. Alternatively, the metal traces are collectively formed with the TSV feature in s same procedure.

Referring toFIGS. 14 and 22, the method88includes an operation100by forming a passivation layer120on the second substrate22. The passivation layer120includes one or more material layer to seal the 3D image sensor structure86from outside environment, such as preventing from outside moisture and other contaminations. In one embodiment, the passivation layer120includes silicon nitride formed CVD or other suitable method. In another embodiment, the passivation layer120includes a silicon oxide layer and a silicon nitride layer configured for effective passivation.

The method88may further include other operations to complete the formation of the 3D image sensor structure86. In one example, the method86may include forming various features to enhance the imaging effect of the image sensors, such as forming color filter and micro-lenses on the backside of the first substrate. In another example, the method88may include a dicing process to form a plurality of 3D image sensor chips after the above operations are implemented in wafer level.

In another embodiment, the method88may include an operation by bonding a carrier substrate (such as another silicon wafer) to the 3D image sensor structure86to enhance the mechanical strength. In one example, the carrier substrate is bonded to the passivation layer80of the second substrate by a suitable bonding mechanism, such as fusion bonding or eutectic bonding.

In yet another embodiment, the method88may further include an operation to thin-down the first substrate after the bonding of the carrier substrate80. The first substrate16is thinned down from the backside such that the thickness of the first substrate16is substantially reduced. Thereby, the image sensors formed in the first substrate16are able to receive image light more efficiently with reduced energy loss.

The present disclosed 3D image sensor structure and the method making the same are described in various embodiments. In another embodiment, the carrier wafer as the third substrate bonded to the 3D image sensor structure includes other logic circuit for further ISP function enhancement. For example, various logic devices including the driving devices to the image sensors are properly distributed in the logic substrate and the carrier wafer for more configuration freedom and design flexibility to enhance the performance of the 3D image sensor structure. In another embodiment of the disclosed structure and method, the driving devices to the image sensors are relocated on the logic substrate for image sensor performance improvement, such as the enlargement of quantum efficiency (QE) and full well capacity (FWC). In yet another embodiment, the image sensors in the 3D image sensor structure may be replaced by other sensors to employ the advantages of the 3D structure.

Different advantages may present in various embodiments. In one embodiment, image sensor pixel performance is improved through a fine-tuning process regardless of logic circuit since the logic circuit is independently formed in the logic circuit wafer before bonding to the image sensor wafer. Accordingly, the gross dies (the number of working dies) increases relative to those in the existing approach. Other advantages includes ISP function enhancement, and easy to extend to next generation process in various embodiments.

Thus, the present disclosure provides an embodiment of a method for fabricating a three dimensional (3D) image sensor structure. The method includes providing to an image sensor substrate having image sensors formed therein and a first interconnect structure formed thereon, and a logic substrate having a logic circuit formed therein and a first interconnect structure formed thereon; bonding the logic substrate to the image sensor substrate in a configuration that the first and second interconnect structures are sandwiched between the logic substrate and the image sensor substrate; and forming a conductive feature extending from the logic substrate to the first interconnect structure, thereby electrically coupling the logic circuit to the image sensors.

The present disclosure also provides one embodiment of an image sensor structure. The image sensor structure includes a first semiconductor substrate having a plurality of imaging sensors; a first interconnect structure formed on the first semiconductor substrate; a second semiconductor substrate having a logic circuit; and a second interconnect structure formed on the second semiconductor substrate. The first and the second semiconductor substrates are bonded together in a configuration that the first and second interconnect structures are sandwiched between the first and second semiconductor substrates. The image sensor structure further includes a through-semiconductor via (TSV) feature extended from the first interconnect structure to the second interconnect structure, thereby electrically coupling the logic circuit to the image sensors.

The present disclosure also provides another embodiment of a method for fabricating a three dimensional (3D) image sensor structure. The method includes providing an image sensor substrate having image sensors formed therein and a first interconnect structure formed thereon, and a logic substrate having a logic circuit formed therein and a first interconnect structure formed thereon; bonding the logic substrate to the image sensor substrate in a configuration that the first and second interconnect structures are sandwiched between the logic substrate and the image sensor substrate; thereafter, thinning-down the logic substrate; and thereafter, performing an etching process, thereby forming a backend deep contact (BDCT) feature that continuously extends from the logic substrate, through a first metal line in the second interconnect structure and contacts a second metal line in the first interconnect structure, the BDCT feature being electrically coupling the logic circuit to the image sensors.